From 98b9484c67cdf05a7e01fa6a65d1f4f959a3633e Mon Sep 17 00:00:00 2001 From: christos Date: Sat, 24 Sep 2011 19:47:50 +0000 Subject: [PATCH] import 7.3.1 --- external/gpl3/gdb/dist/bfd/hosts/alphalinux.h | 25 + external/gpl3/gdb/dist/bfd/hosts/alphavms.h | 81 + external/gpl3/gdb/dist/bfd/hosts/decstation.h | 36 + external/gpl3/gdb/dist/bfd/hosts/delta68.h | 33 + external/gpl3/gdb/dist/bfd/hosts/dpx2.h | 27 + external/gpl3/gdb/dist/bfd/hosts/hp300bsd.h | 32 + external/gpl3/gdb/dist/bfd/hosts/i386bsd.h | 51 + external/gpl3/gdb/dist/bfd/hosts/i386linux.h | 27 + external/gpl3/gdb/dist/bfd/hosts/i386mach3.h | 44 + external/gpl3/gdb/dist/bfd/hosts/i386sco.h | 38 + external/gpl3/gdb/dist/bfd/hosts/i860mach3.h | 46 + external/gpl3/gdb/dist/bfd/hosts/m68kaux.h | 35 + external/gpl3/gdb/dist/bfd/hosts/m68klinux.h | 25 + external/gpl3/gdb/dist/bfd/hosts/m88kmach3.h | 30 + external/gpl3/gdb/dist/bfd/hosts/mipsbsd.h | 31 + external/gpl3/gdb/dist/bfd/hosts/mipsmach3.h | 29 + external/gpl3/gdb/dist/bfd/hosts/news-mips.h | 31 + external/gpl3/gdb/dist/bfd/hosts/news.h | 28 + external/gpl3/gdb/dist/bfd/hosts/pc532mach.h | 43 + external/gpl3/gdb/dist/bfd/hosts/riscos.h | 29 + external/gpl3/gdb/dist/bfd/hosts/symmetry.h | 39 + external/gpl3/gdb/dist/bfd/hosts/tahoe.h | 31 + external/gpl3/gdb/dist/bfd/hosts/vaxbsd.h | 31 + external/gpl3/gdb/dist/bfd/hosts/vaxlinux.h | 21 + external/gpl3/gdb/dist/bfd/hosts/vaxult.h | 27 + external/gpl3/gdb/dist/bfd/hosts/vaxult2.h | 27 + .../gpl3/gdb/dist/bfd/hosts/x86-64linux.h | 195 + external/gpl3/gdb/dist/bfd/po/BLD-POTFILES.in | 10 + external/gpl3/gdb/dist/bfd/po/Make-in | 298 + external/gpl3/gdb/dist/bfd/po/SRC-POTFILES.in | 353 + external/gpl3/gdb/dist/bfd/po/bfd.pot | 6002 ++ external/gpl3/gdb/dist/bfd/po/da.gmo | Bin 0 -> 134131 bytes external/gpl3/gdb/dist/bfd/po/da.po | 6159 ++ external/gpl3/gdb/dist/bfd/po/es.gmo | Bin 0 -> 139774 bytes external/gpl3/gdb/dist/bfd/po/es.po | 6385 ++ external/gpl3/gdb/dist/bfd/po/fi.gmo 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external/gpl3/gdb/dist/bfd/po/vi.po | 4146 + external/gpl3/gdb/dist/bfd/po/zh_CN.gmo | Bin 0 -> 28121 bytes external/gpl3/gdb/dist/bfd/po/zh_CN.po | 2702 + external/gpl3/gdb/dist/include/COPYING | 340 + external/gpl3/gdb/dist/include/COPYING3 | 674 + external/gpl3/gdb/dist/include/ChangeLog | 1421 + external/gpl3/gdb/dist/include/ChangeLog-9103 | 2682 + external/gpl3/gdb/dist/include/MAINTAINERS | 1 + external/gpl3/gdb/dist/include/alloca-conf.h | 45 + external/gpl3/gdb/dist/include/ansidecl.h | 423 + external/gpl3/gdb/dist/include/aout/ChangeLog | 253 + external/gpl3/gdb/dist/include/aout/adobe.h | 314 + external/gpl3/gdb/dist/include/aout/aout64.h | 516 + external/gpl3/gdb/dist/include/aout/ar.h | 55 + external/gpl3/gdb/dist/include/aout/dynix3.h | 87 + external/gpl3/gdb/dist/include/aout/encap.h | 135 + external/gpl3/gdb/dist/include/aout/host.h | 43 + external/gpl3/gdb/dist/include/aout/hp.h | 83 + .../gpl3/gdb/dist/include/aout/hp300hpux.h | 132 + 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external/gpl3/gdb/dist/include/dyn-string.h | 73 + external/gpl3/gdb/dist/include/elf/ChangeLog | 1437 + .../gpl3/gdb/dist/include/elf/ChangeLog-9103 | 1948 + external/gpl3/gdb/dist/include/elf/alpha.h | 131 + external/gpl3/gdb/dist/include/elf/arc.h | 57 + external/gpl3/gdb/dist/include/elf/arm.h | 337 + external/gpl3/gdb/dist/include/elf/avr.h | 82 + external/gpl3/gdb/dist/include/elf/bfin.h | 95 + external/gpl3/gdb/dist/include/elf/common.h | 946 + external/gpl3/gdb/dist/include/elf/cr16.h | 62 + external/gpl3/gdb/dist/include/elf/cr16c.h | 258 + external/gpl3/gdb/dist/include/elf/cris.h | 193 + external/gpl3/gdb/dist/include/elf/crx.h | 53 + external/gpl3/gdb/dist/include/elf/d10v.h | 38 + external/gpl3/gdb/dist/include/elf/d30v.h | 42 + external/gpl3/gdb/dist/include/elf/dlx.h | 53 + external/gpl3/gdb/dist/include/elf/dwarf.h | 323 + external/gpl3/gdb/dist/include/elf/external.h | 288 + external/gpl3/gdb/dist/include/elf/fr30.h | 42 + external/gpl3/gdb/dist/include/elf/frv.h | 130 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create mode 100644 external/gpl3/gdb/dist/sim/configure.ac create mode 100644 external/gpl3/gdb/dist/sim/configure.tgt diff --git a/external/gpl3/gdb/dist/bfd/hosts/alphalinux.h b/external/gpl3/gdb/dist/bfd/hosts/alphalinux.h new file mode 100644 index 000000000000..af5331d23e3f --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/alphalinux.h @@ -0,0 +1,25 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Linux dumps "struct task_struct" at the end of the core-file. This + structure is currently 1080 bytes long, but we allow up to 4096 + bytes to allow for some future growth. */ +#define TRAD_CORE_EXTRA_SIZE_ALLOWED 4096 +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ + ((abfd)->tdata.trad_core_data->u.signal) diff --git a/external/gpl3/gdb/dist/bfd/hosts/alphavms.h b/external/gpl3/gdb/dist/bfd/hosts/alphavms.h new file mode 100644 index 000000000000..2a3421200a16 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/alphavms.h @@ -0,0 +1,81 @@ +/* alphavms.h -- BFD definitions for an openVMS host + Copyright 1996, 2000, 2001, 2005, 2007, 2008, 2009 + Free Software Foundation, Inc. + Written by Klaus Kämpf (kkaempf@progis.de) + of proGIS Softwareentwicklung, Aachen, Germany + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bfd.h" +#include "filenames.h" + +#ifndef BFD_HOST_64_BIT +/* Make the basic types 64-bit quantities on the host. + Also provide the support macros BFD needs. */ +# ifdef __GNUC__ +# define BFD_HOST_64_BIT long long +# else +# define BFD_HOST_64_BIT long +# endif +typedef unsigned BFD_HOST_64_BIT uint64_type; +typedef BFD_HOST_64_BIT int64_type; + +# define sprintf_vma(s,x) sprintf (s, "%016lx", x) /* BFD_HOST_64_BIT */ +# define fprintf_vma(f,x) fprintf (f, "%016lx", x) /* BFD_HOST_64_BIT */ + +# define BYTES_IN_PRINTF_INT 4 + +/* These must have type unsigned long because they are used as + arguments in printf functions. */ +# define uint64_typeLOW(x) ((unsigned long) (((x) & 0xffffffff))) /* BFD_HOST_64_BIT */ +# define uint64_typeHIGH(x) ((unsigned long) (((x) >> 32) & 0xffffffff)) /* BFD_HOST_64_BIT */ + +#endif /* BFD_HOST_64_BIT */ + +#include "fopen-vms.h" + +#define NO_FCNTL 1 + +#ifndef O_ACCMODE +#define O_ACCMODE (O_RDONLY | O_WRONLY | O_RDWR) +#endif + +extern int getpagesize (void); +extern char *stpcpy (char *, const char *); + +/* No intl. */ +#define gettext(Msgid) (Msgid) +#define dgettext(Domainname, Msgid) (Msgid) +#define dcgettext(Domainname, Msgid, Category) (Msgid) +#define textdomain(Domainname) while (0) /* nothing */ +#define bindtextdomain(Domainname, Dirname) while (0) /* nothing */ +#define _(String) (String) +#define N_(String) (String) diff --git a/external/gpl3/gdb/dist/bfd/hosts/decstation.h b/external/gpl3/gdb/dist/bfd/hosts/decstation.h new file mode 100644 index 000000000000..ceccfcba880d --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/decstation.h @@ -0,0 +1,36 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Hopefully this should include either machine/param.h (Ultrix) or + machine/machparam.h (Mach), whichever is its name on this system. */ +#include + +#include + +#define HOST_PAGE_SIZE NBPG +/* #define HOST_SEGMENT_SIZE NBPG -- we use HOST_DATA_START_ADDR */ +#define HOST_MACHINE_ARCH bfd_arch_mips +/* #define HOST_MACHINE_MACHINE */ + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_DATA_START_ADDR USRDATA +#define HOST_STACK_END_ADDR USRSTACK + +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(core_bfd) \ + ((core_bfd)->tdata.trad_core_data->u.u_arg[0]) diff --git a/external/gpl3/gdb/dist/bfd/hosts/delta68.h b/external/gpl3/gdb/dist/bfd/hosts/delta68.h new file mode 100644 index 000000000000..3788272a0ae2 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/delta68.h @@ -0,0 +1,33 @@ +/* Copyright 2005, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Definitions for a Motorola Delta 3300 box running System V R3.0. + Contributed by manfred@lts.sel.alcatel.de. */ + +#include + +/* Definitions used by trad-core.c. */ +#define NBPG NBPC +#define HOST_DATA_START_ADDR u.u_exdata.ux_datorg +#define HOST_TEXT_START_ADDR u.u_exdata.ux_txtorg +/* User's stack, copied from sys/param.h */ +#define HOST_STACK_END_ADDR USRSTACK +#define UPAGES USIZE +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ + abfd->tdata.trad_core_data->u.u_abort diff --git a/external/gpl3/gdb/dist/bfd/hosts/dpx2.h b/external/gpl3/gdb/dist/bfd/hosts/dpx2.h new file mode 100644 index 000000000000..d1b4ff06c535 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/dpx2.h @@ -0,0 +1,27 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Definitions that are needed for core files. Core section sizes for + the DPX2 are in bytes. */ + +#include +#define NBPG 1 +#define UPAGES (USIZE * NBPP) +#define HOST_DATA_START_ADDR (u.u_exdata.ux_datorg) +#define HOST_STACK_END_ADDR (USERSTACK) diff --git a/external/gpl3/gdb/dist/bfd/hosts/hp300bsd.h b/external/gpl3/gdb/dist/bfd/hosts/hp300bsd.h new file mode 100644 index 000000000000..d00cada4231c --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/hp300bsd.h @@ -0,0 +1,32 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#ifdef BSD4_4 +#define NO_CORE_COMMAND +#endif + +#define HOST_PAGE_SIZE NBPG +#define HOST_SEGMENT_SIZE NBPG /* Data seg start addr rounds to NBPG */ +#define HOST_MACHINE_ARCH bfd_arch_m68k +/* #define HOST_MACHINE_MACHINE */ + +#define HOST_TEXT_START_ADDR 0 +#define HOST_STACK_END_ADDR 0xfff00000 +#define HOST_BIG_ENDIAN_P diff --git a/external/gpl3/gdb/dist/bfd/hosts/i386bsd.h b/external/gpl3/gdb/dist/bfd/hosts/i386bsd.h new file mode 100644 index 000000000000..b2145e6bfd58 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/i386bsd.h @@ -0,0 +1,51 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Intel 386 running any BSD Unix. */ + +#include +#include + +/* Recent versions of FreeBSD don't define NBPG. */ +#ifndef NBPG +#ifdef PAGE_SIZE +#define NBPG PAGE_SIZE +#endif +#endif + +#define HOST_PAGE_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_i386 +#define HOST_TEXT_START_ADDR USRTEXT + +/* Jolitz suggested defining HOST_STACK_END_ADDR to + (u.u_kproc.kp_eproc.e_vm.vm_maxsaddr + MAXSSIZ), which should work on + both BSDI and 386BSD, but that is believed not to work for BSD 4.4. */ + +#ifdef __bsdi__ +/* This seems to be the right thing for BSDI. */ +#define HOST_STACK_END_ADDR USRSTACK +#define HOST_DATA_START_ADDR ((bfd_vma)u.u_kproc.kp_eproc.e_vm.vm_daddr) +#else +/* This seems to be the right thing for 386BSD release 0.1. */ +#define HOST_STACK_END_ADDR (USRSTACK - MAXSSIZ) +#endif + +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(core_bfd) \ + ((core_bfd)->tdata.trad_core_data->u.u_sig) +#define u_comm u_kproc.kp_proc.p_comm diff --git a/external/gpl3/gdb/dist/bfd/hosts/i386linux.h b/external/gpl3/gdb/dist/bfd/hosts/i386linux.h new file mode 100644 index 000000000000..d0ac14e7a699 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/i386linux.h @@ -0,0 +1,27 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Linux writes the task structure at the end of the core file. Currently it + is 2912 bytes. It is possible that this should be a pickier check, but + we should probably not be too picky (the size of the task structure might + vary, and if it's not the length we expect it to be, it doesn't affect + our ability to process the core file). So allow 0-4096 extra bytes at + the end. */ + +#define TRAD_CORE_EXTRA_SIZE_ALLOWED 4096 diff --git a/external/gpl3/gdb/dist/bfd/hosts/i386mach3.h b/external/gpl3/gdb/dist/bfd/hosts/i386mach3.h new file mode 100644 index 000000000000..02df406d4d3e --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/i386mach3.h @@ -0,0 +1,44 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include + +/* This is an ugly way to hack around the incorrect + * definition of UPAGES in i386/machparam.h. + * + * The definition should specify the size reserved + * for "struct user" in core files in PAGES, + * but instead it gives it in 512-byte core-clicks + * for i386 and i860. UPAGES is used only in trad-core.c. + */ +#if UPAGES == 16 +#undef UPAGES +#define UPAGES 2 +#endif + +#if UPAGES != 2 +FIXME!! UPAGES is neither 2 nor 16 +#endif + +#define HOST_PAGE_SIZE 1 +#define HOST_SEGMENT_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_i386 +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/i386sco.h b/external/gpl3/gdb/dist/bfd/hosts/i386sco.h new file mode 100644 index 000000000000..119dbfcc85d9 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/i386sco.h @@ -0,0 +1,38 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Core file stuff. At least some, perhaps all, of the following + defines work on many more systems than just SCO. */ + +#define NBPG NBPC +#define UPAGES USIZE +#define HOST_DATA_START_ADDR u.u_exdata.ux_datorg +#define HOST_STACK_START_ADDR u.u_sub +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ + ((core_upage(abfd)->u_sysabort != 0) \ + ? core_upage(abfd)->u_sysabort \ + : -1) + +/* According to the manpage, a version 2 SCO corefile can contain + various additional sections (it is cleverly arranged so the u area, + data, and stack are first where we can find them). So without + writing lots of code to parse all their headers and stuff, we can't + know whether a corefile is bigger than it should be. */ + +#define TRAD_CORE_ALLOW_ANY_EXTRA_SIZE 1 diff --git a/external/gpl3/gdb/dist/bfd/hosts/i860mach3.h b/external/gpl3/gdb/dist/bfd/hosts/i860mach3.h new file mode 100644 index 000000000000..3dcbf2113efc --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/i860mach3.h @@ -0,0 +1,46 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file was hacked from i386mach3.h [dolan@ssd.intel.com] */ + +#include +#include + +/* This is an ugly way to hack around the incorrect + * definition of UPAGES in i386/machparam.h. + * + * The definition should specify the size reserved + * for "struct user" in core files in PAGES, + * but instead it gives it in 512-byte core-clicks + * for i386 and i860. UPAGES is used only in trad-core.c. + */ +#if UPAGES == 16 +#undef UPAGES +#define UPAGES 2 +#endif + +#if UPAGES != 2 +FIXME!! UPAGES is neither 2 nor 16 +#endif + +#define HOST_PAGE_SIZE 1 +#define HOST_SEGMENT_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_i860 +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/m68kaux.h b/external/gpl3/gdb/dist/bfd/hosts/m68kaux.h new file mode 100644 index 000000000000..756b60879945 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/m68kaux.h @@ -0,0 +1,35 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Definitions for an Apple Macintosh running A/UX 3.x. */ + +#include +#include + +/* Definitions used by trad-core.c. */ +#define NBPG NBPP + +#define HOST_DATA_START_ADDR u.u_exdata.ux_datorg +#define HOST_TEXT_START_ADDR u.u_exdata.ux_txtorg +#define HOST_STACK_END_ADDR 0x100000000 + +#define UPAGES USIZE + +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ + (abfd->tdata.trad_core_data->u.u_arg[0]) diff --git a/external/gpl3/gdb/dist/bfd/hosts/m68klinux.h b/external/gpl3/gdb/dist/bfd/hosts/m68klinux.h new file mode 100644 index 000000000000..a808d78f74fc --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/m68klinux.h @@ -0,0 +1,25 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Linux dumps "struct task_struct" at the end of the core-file. This + structure is currently 2512 bytes long, but we allow up to 4096 + bytes to allow for some future growth. */ +#define TRAD_CORE_EXTRA_SIZE_ALLOWED 4096 +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ + ((abfd)->tdata.trad_core_data->u.signal) diff --git a/external/gpl3/gdb/dist/bfd/hosts/m88kmach3.h b/external/gpl3/gdb/dist/bfd/hosts/m88kmach3.h new file mode 100644 index 000000000000..712de0ac37db --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/m88kmach3.h @@ -0,0 +1,30 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include + +#undef UPAGES +#define UPAGES 3 + +#define HOST_PAGE_SIZE NBPG +#define HOST_SEGMENT_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_m88k +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/mipsbsd.h b/external/gpl3/gdb/dist/bfd/hosts/mipsbsd.h new file mode 100644 index 000000000000..359487ae35ea --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/mipsbsd.h @@ -0,0 +1,31 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#undef ALIGN + +#define HOST_PAGE_SIZE NBPG +/* #define HOST_SEGMENT_SIZE NBPG -- we use HOST_DATA_START_ADDR */ +#define HOST_MACHINE_ARCH bfd_arch_mips +/* #define HOST_MACHINE_MACHINE */ + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK +#define NO_CORE_COMMAND diff --git a/external/gpl3/gdb/dist/bfd/hosts/mipsmach3.h b/external/gpl3/gdb/dist/bfd/hosts/mipsmach3.h new file mode 100644 index 000000000000..5a2e2295553b --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/mipsmach3.h @@ -0,0 +1,29 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include + +#define HOST_PAGE_SIZE NBPG +/* #define HOST_SEGMENT_SIZE NBPG */ +#define HOST_MACHINE_ARCH bfd_arch_mips +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_DATA_START_ADDR USRDATA +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/news-mips.h b/external/gpl3/gdb/dist/bfd/hosts/news-mips.h new file mode 100644 index 000000000000..06f9f5829436 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/news-mips.h @@ -0,0 +1,31 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Sony News running NewsOS 3.2. */ + +#include +#include + +#define HOST_PAGE_SIZE NBPG + +#define HOST_MACHINE_ARCH bfd_arch_mips + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_DATA_START_ADDR USRDATA +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/news.h b/external/gpl3/gdb/dist/bfd/hosts/news.h new file mode 100644 index 000000000000..d4301c940983 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/news.h @@ -0,0 +1,28 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Sony News running NewsOS 3.2. */ + +#include + +#define HOST_PAGE_SIZE NBPG +#define HOST_SEGMENT_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_m68k +#define HOST_TEXT_START_ADDR 0 +#define HOST_STACK_END_ADDR (KERNBASE - (UPAGES * NBPG)) diff --git a/external/gpl3/gdb/dist/bfd/hosts/pc532mach.h b/external/gpl3/gdb/dist/bfd/hosts/pc532mach.h new file mode 100644 index 000000000000..bac4a3294226 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/pc532mach.h @@ -0,0 +1,43 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include + +/* This is an ugly way to hack around the incorrect + * definition of UPAGES in ns532/machparam.h. + * + * The definition should specify the size reserved + * for "struct user" in core files in PAGES, + * but instead it gives it in 512-byte core-clicks + * for ns532, i386 and i860. UPAGES is used only in trad-core.c. + */ +#if UPAGES == 16 +#undef UPAGES +#define UPAGES 2 +#endif + +#if UPAGES != 2 +#error UPAGES is neither 2 nor 16 +#endif + +#define HOST_PAGE_SIZE 1 +#define HOST_SEGMENT_SIZE NBPG +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/riscos.h b/external/gpl3/gdb/dist/bfd/hosts/riscos.h new file mode 100644 index 000000000000..e4b7f46610fa --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/riscos.h @@ -0,0 +1,29 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* RISC/os 4.52C, and presumably other versions. */ + +#include +#include + +#define NBPG BSD43_NBPG +#define UPAGES BSD43_UPAGES +#define HOST_TEXT_START_ADDR BSD43_USRTEXT +#define HOST_DATA_START_ADDR BSD43_USRDATA +#define HOST_STACK_END_ADDR BSD43_USRSTACK diff --git a/external/gpl3/gdb/dist/bfd/hosts/symmetry.h b/external/gpl3/gdb/dist/bfd/hosts/symmetry.h new file mode 100644 index 000000000000..a5959055a1f5 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/symmetry.h @@ -0,0 +1,39 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Symmetry running either dynix 3.1 (bsd) or ptx (sysv). */ + +#define NBPG 4096 +#define UPAGES 1 + +#ifdef _SEQUENT_ +/* ptx */ +#define HOST_TEXT_START_ADDR 0 +#define HOST_STACK_END_ADDR 0x3fffe000 +#define TRAD_CORE_USER_OFFSET ((UPAGES * NBPG) - sizeof (struct user)) +#else +/* dynix */ +#define HOST_TEXT_START_ADDR 0x1000 +#define HOST_DATA_START_ADDR (NBPG * u.u_tsize) +#define HOST_STACK_END_ADDR 0x3ffff000 +#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(core_bfd) \ + ((core_bfd)->tdata.trad_core_data->u.u_arg[0]) +#endif + +#define TRAD_CORE_DSIZE_INCLUDES_TSIZE diff --git a/external/gpl3/gdb/dist/bfd/hosts/tahoe.h b/external/gpl3/gdb/dist/bfd/hosts/tahoe.h new file mode 100644 index 000000000000..fa6e7a65c12e --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/tahoe.h @@ -0,0 +1,31 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define NO_CORE_COMMAND + +#undef ALIGN /* They use it, we use it too */ +#include +#undef ALIGN /* They use it, we use it too */ + +#define HOST_PAGE_SIZE NBPG +#define HOST_MACHINE_ARCH bfd_arch_tahoe + +#define HOST_TEXT_START_ADDR 0 +#define HOST_STACK_END_ADDR (KERNBASE - (UPAGES * NBPG)) +#define HOST_BIG_ENDIAN_P diff --git a/external/gpl3/gdb/dist/bfd/hosts/vaxbsd.h b/external/gpl3/gdb/dist/bfd/hosts/vaxbsd.h new file mode 100644 index 000000000000..3e02c3de5e57 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/vaxbsd.h @@ -0,0 +1,31 @@ +/* Copyright 2005, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define NO_CORE_COMMAND /* No command name in core file */ + +#undef ALIGN /* They use it, we use it too */ + +/* Note that HOST_PAGE_SIZE -- the page size as far as executable files + are concerned -- is not the same as NBPG, because of page clustering. */ +#define HOST_PAGE_SIZE 1024 +#define HOST_MACHINE_ARCH bfd_arch_vax + +#define HOST_TEXT_START_ADDR 0 +#define HOST_STACK_END_ADDR (0x80000000 - (UPAGES * NBPG)) +#undef HOST_BIG_ENDIAN_P diff --git a/external/gpl3/gdb/dist/bfd/hosts/vaxlinux.h b/external/gpl3/gdb/dist/bfd/hosts/vaxlinux.h new file mode 100644 index 000000000000..271587ed8511 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/vaxlinux.h @@ -0,0 +1,21 @@ +/* Copyright 2005, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define TRAD_CORE_EXTRA_SIZE_ALLOWED 4096 +#define HOST_MACHINE_ARCH bfd_arch_vax diff --git a/external/gpl3/gdb/dist/bfd/hosts/vaxult.h b/external/gpl3/gdb/dist/bfd/hosts/vaxult.h new file mode 100644 index 000000000000..045a15d74f69 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/vaxult.h @@ -0,0 +1,27 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#define HOST_PAGE_SIZE (NBPG*CLSIZE) +#define HOST_MACHINE_ARCH bfd_arch_vax + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK +#undef HOST_BIG_ENDIAN_P diff --git a/external/gpl3/gdb/dist/bfd/hosts/vaxult2.h b/external/gpl3/gdb/dist/bfd/hosts/vaxult2.h new file mode 100644 index 000000000000..045a15d74f69 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/vaxult2.h @@ -0,0 +1,27 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#define HOST_PAGE_SIZE (NBPG*CLSIZE) +#define HOST_MACHINE_ARCH bfd_arch_vax + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK +#undef HOST_BIG_ENDIAN_P diff --git a/external/gpl3/gdb/dist/bfd/hosts/x86-64linux.h b/external/gpl3/gdb/dist/bfd/hosts/x86-64linux.h new file mode 100644 index 000000000000..27901c5fbfab --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/hosts/x86-64linux.h @@ -0,0 +1,195 @@ +/* Copyright (C) 2006 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +/* This is somewhat modelled after the file of the same name on SVR4 + systems. It provides a definition of the core file format for ELF + used on Linux. It doesn't have anything to do with the /proc file + system, even though Linux has one. + + Anyway, the whole purpose of this file is for GDB and GDB only. + Don't read too much into it. Don't use it for anything other than + GDB unless you know what you are doing. */ + +#include +#include +#include + +/* We define here only the symbols differing from their 64-bit variant. */ +#include + +#ifdef HAVE_STDINT_H +#include +#else +typedef unsigned int uint32_t; +#endif + +#undef HAVE_PRPSINFO32_T +#define HAVE_PRPSINFO32_T + +#undef HAVE_PRSTATUS32_T +#define HAVE_PRSTATUS32_T + +/* These are the 32-bit x86 structures. */ + +struct user_fpregs32_struct +{ + int32_t cwd; + int32_t swd; + int32_t twd; + int32_t fip; + int32_t fcs; + int32_t foo; + int32_t fos; + int32_t st_space [20]; +}; + +struct user_fpxregs32_struct +{ + unsigned short int cwd; + unsigned short int swd; + unsigned short int twd; + unsigned short int fop; + int32_t fip; + int32_t fcs; + int32_t foo; + int32_t fos; + int32_t mxcsr; + int32_t reserved; + int32_t st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ + int32_t xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ + int32_t padding[56]; +}; + +struct user_regs32_struct +{ + int32_t ebx; + int32_t ecx; + int32_t edx; + int32_t esi; + int32_t edi; + int32_t ebp; + int32_t eax; + int32_t xds; + int32_t xes; + int32_t xfs; + int32_t xgs; + int32_t orig_eax; + int32_t eip; + int32_t xcs; + int32_t eflags; + int32_t esp; + int32_t xss; +}; + +struct user32 +{ + struct user_regs32_struct regs; + int u_fpvalid; + struct user_fpregs32_struct i387; + uint32_t u_tsize; + uint32_t u_dsize; + uint32_t u_ssize; + uint32_t start_code; + uint32_t start_stack; + int32_t signal; + int reserved; + struct user_regs32_struct* u_ar0; + struct user_fpregs32_struct* u_fpstate; + uint32_t magic; + char u_comm [32]; + int u_debugreg [8]; +}; + +/* Type for a general-purpose register. */ +typedef unsigned int elf_greg32_t; + +/* And the whole bunch of them. We could have used `struct + user_regs_struct' directly in the typedef, but tradition says that + the register set is an array, which does have some peculiar + semantics, so leave it that way. */ +#define ELF_NGREG32 (sizeof (struct user_regs32_struct) / sizeof(elf_greg32_t)) +typedef elf_greg32_t elf_gregset32_t[ELF_NGREG32]; + +/* Register set for the floating-point registers. */ +typedef struct user_fpregs32_struct elf_fpregset32_t; + +/* Register set for the extended floating-point registers. Includes + the Pentium III SSE registers in addition to the classic + floating-point stuff. */ +typedef struct user_fpxregs32_struct elf_fpxregset32_t; + + +/* Definitions to generate Intel SVR4-like core files. These mostly + have the same names as the SVR4 types with "elf_" tacked on the + front to prevent clashes with Linux definitions, and the typedef + forms have been avoided. This is mostly like the SVR4 structure, + but more Linuxy, with things that Linux does not support and which + GDB doesn't really use excluded. */ + +struct prstatus32_timeval + { + int tv_sec; + int tv_usec; + }; + +struct elf_prstatus32 + { + struct elf_siginfo pr_info; /* Info associated with signal. */ + short int pr_cursig; /* Current signal. */ + unsigned int pr_sigpend; /* Set of pending signals. */ + unsigned int pr_sighold; /* Set of held signals. */ + __pid_t pr_pid; + __pid_t pr_ppid; + __pid_t pr_pgrp; + __pid_t pr_sid; + struct prstatus32_timeval pr_utime; /* User time. */ + struct prstatus32_timeval pr_stime; /* System time. */ + struct prstatus32_timeval pr_cutime; /* Cumulative user time. */ + struct prstatus32_timeval pr_cstime; /* Cumulative system time. */ + elf_gregset32_t pr_reg; /* GP registers. */ + int pr_fpvalid; /* True if math copro being used. */ + }; + + +struct elf_prpsinfo32 + { + char pr_state; /* Numeric process state. */ + char pr_sname; /* Char for pr_state. */ + char pr_zomb; /* Zombie. */ + char pr_nice; /* Nice val. */ + unsigned int pr_flag; /* Flags. */ + unsigned short int pr_uid; + unsigned short int pr_gid; + int pr_pid, pr_ppid, pr_pgrp, pr_sid; + /* Lots missing */ + char pr_fname[16]; /* Filename of executable. */ + char pr_psargs[ELF_PRARGSZ]; /* Initial part of arg list. */ + }; + + +/* The rest of this file provides the types for emulation of the + Solaris interfaces that should be implemented by + users of libthread_db. */ + +/* Register sets. Linux has different names. */ +typedef elf_gregset_t prgregset32_t; +typedef elf_fpregset_t prfpregset32_t; + +/* Process status and info. In the end we do provide typedefs for them. */ +typedef struct elf_prstatus32 prstatus32_t; +typedef struct elf_prpsinfo32 prpsinfo32_t; diff --git a/external/gpl3/gdb/dist/bfd/po/BLD-POTFILES.in b/external/gpl3/gdb/dist/bfd/po/BLD-POTFILES.in new file mode 100644 index 000000000000..15a0174c29b8 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/BLD-POTFILES.in @@ -0,0 +1,10 @@ +bfd_stdint.h +bfdver.h +elf32-ia64.c +elf32-target.h +elf64-ia64.c +elf64-target.h +peigen.c +pepigen.c +pex64igen.c +targmatch.h diff --git a/external/gpl3/gdb/dist/bfd/po/Make-in b/external/gpl3/gdb/dist/bfd/po/Make-in new file mode 100644 index 000000000000..a9d3aeaab68b --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/Make-in @@ -0,0 +1,298 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper +# Copyright 2001, 2003, 2006, 2007, 2009 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +PACKAGE = @PACKAGE@ +VERSION = @VERSION@ + +SHELL = /bin/sh +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +top_builddir = @top_builddir@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +datadir = $(prefix)/@DATADIRNAME@ +localedir = $(datadir)/locale +gnulocaledir = $(prefix)/share/locale +gettextsrcdir = $(prefix)/share/gettext/po +subdir = po + +DESTDIR = + +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +MKINSTALLDIRS = @MKINSTALLDIRS@ + +CC = @CC@ +GENCAT = @GENCAT@ +GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ +MSGFMT = @MSGFMT@ +XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ +MSGMERGE = PATH=../src:$$PATH msgmerge + +DEFS = @DEFS@ +CFLAGS = @CFLAGS@ +CPPFLAGS = @CPPFLAGS@ + +INCLUDES = -I.. -I$(top_srcdir)/intl + +COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) + +SOURCES = cat-id-tbl.c +POFILES = @POFILES@ +GMOFILES = @GMOFILES@ +DISTFILES = ChangeLog Makefile.in.in SRC-POTFILES.in BLD-POTFILES.in $(PACKAGE).pot \ +stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) + +# Note - the following line gets processed by bfd/configure and amended +# to contain the full list of source dir POTFILES. +SRC-POTFILES = \ + +# Note - the following line gets processed by bfd/configure and amended +# to contain the full list of build dir POTFILES. +BLD-POTFILES = \ + +CATALOGS = @CATALOGS@ +CATOBJEXT = @CATOBJEXT@ +INSTOBJEXT = @INSTOBJEXT@ + +.SUFFIXES: +.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat + +.c.o: + $(COMPILE) $< + +.po.pox: + $(MAKE) $(PACKAGE).pot + $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox + +.po.mo: + $(MSGFMT) -o $@ $< + +.po.gmo: + file=`echo $* | sed 's,.*/,,'`.gmo \ + && rm -f $$file && $(GMSGFMT) -o $$file $< + +.po.cat: + sed -f ../intl/po2msg.sed < $< > $*.msg \ + && rm -f $@ && $(GENCAT) $@ $*.msg + + +all: all-@USE_NLS@ + +all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot +all-no: + +$(srcdir)/$(PACKAGE).pot: $(SRC-POTFILES) $(BLD-POTFILES) + $(XGETTEXT) --default-domain=$(PACKAGE) \ + --directory=$(top_srcdir) \ + --add-comments --keyword=_ --keyword=N_ \ + --msgid-bugs-address=bug-binutils@gnu.org \ + --files-from=$(srcdir)/SRC-POTFILES.in + $(XGETTEXT) --default-domain=$(PACKAGE) \ + --directory=.. \ + --directory=. \ + --add-comments --keyword=_ --keyword=N_ \ + --join-existing \ + --msgid-bugs-address=bug-binutils@gnu.org \ + --files-from=$(srcdir)/BLD-POTFILES.in + rm -f $(srcdir)/$(PACKAGE).pot + mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot + +$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: +$(srcdir)/stamp-cat-id: $(PACKAGE).pot + rm -f cat-id-tbl.tmp + sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ + | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp + if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ + rm cat-id-tbl.tmp; \ + else \ + echo cat-id-tbl.c changed; \ + rm -f $(srcdir)/cat-id-tbl.c; \ + mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ + fi + cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id + + +install: install-exec install-data +install-exec: +install-info: +install-html: +install-pdf: +install-data: install-data-@USE_NLS@ +install-data-no: all +install-data-yes: all + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \ + else \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \ + fi + @catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + case "$$cat" in \ + *.gmo) destdir=$(gnulocaledir);; \ + *) destdir=$(localedir);; \ + esac; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $$dir; \ + else \ + $(top_srcdir)/mkinstalldirs $$dir; \ + fi; \ + if test -r $$cat; then \ + $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + else \ + $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + fi; \ + if test -r $$cat.m; then \ + $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + if test -r $(srcdir)/$$cat.m ; then \ + $(INSTALL_DATA) $(srcdir)/$$cat.m \ + $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + true; \ + fi; \ + fi; \ + done + if test "$(PACKAGE)" = "gettext"; then \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \ + else \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \ + fi; \ + $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ + $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \ + else \ + : ; \ + fi + +# Define this as empty until I found a useful application. +installcheck: + +uninstall: + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + done + rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in + +check: all + +cat-id-tbl.o: ../intl/libgettext.h + +html dvi pdf ps info tags TAGS ID: + +mostlyclean: + rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp + rm -fr *.o + +clean: mostlyclean + +distclean: clean + rm -f Makefile Makefile.in *.mo *.msg *.cat *.cat.m + rm -f SRC-POTFILES BLD-POTFILES + +maintainer-clean: distclean + @echo "This command is intended for maintainers to use;" + @echo "it deletes files that may require special tools to rebuild." + rm -f $(GMOFILES) SRC-POTFILES.in BLD-POTFILES.in + +distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) +dist distdir: update-po $(DISTFILES) + dists="$(DISTFILES)"; \ + for file in $$dists; do \ + ln $(srcdir)/$$file $(distdir) 2> /dev/null \ + || cp -p $(srcdir)/$$file $(distdir); \ + done + +update-po: Makefile + $(MAKE) $(PACKAGE).pot + PATH=`pwd`/../src:$$PATH; \ + cd $(srcdir); \ + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + mv $$lang.po $$lang.old.po; \ + echo "$$lang:"; \ + if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ + rm -f $$lang.old.po; \ + else \ + echo "msgmerge for $$cat failed!"; \ + rm -f $$lang.po; \ + mv $$lang.old.po $$lang.po; \ + fi; \ + done + +SRC-POTFILES: SRC-POTFILES.in + ( if test 'x$(srcdir)' != 'x.'; then \ + posrcprefix='$(top_srcdir)/'; \ + else \ + posrcprefix="../"; \ + fi; \ + rm -f $@-t $@ \ + && (sed -e '/^#/d' \ + -e '/^[ ]*$$/d' \ + -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ + | sed -e '$$s/\\$$//') > $@-t \ + && chmod a-w $@-t \ + && mv $@-t $@ ) + +BLD-POTFILES: BLD-POTFILES.in + ( rm -f $@-t $@ \ + && (sed -e '/^#/d' \ + -e '/^[ ]*$$/d' \ + -e "s@.*@ ../& \\\\@" < $(srcdir)/$@.in \ + | sed -e '$$s/\\$$//') > $@-t \ + && chmod a-w $@-t \ + && mv $@-t $@ ) + +SRC-POTFILES.in: @MAINT@ ../Makefile + cd .. && $(MAKE) po/SRC-POTFILES.in + +BLD-POTFILES.in: @MAINT@ ../Makefile + cd .. && $(MAKE) po/BLD-POTFILES.in + +# Note - The presence of SRC-POTFILES and BLD-POTFILES as dependencies +# here breaks the implementation of the 'distclean' rule for maintainers. +# This is because if 'make distclean' is run in the BFD directory, the +# Makefile there will be deleted before 'distclean' is made here, and so +# the dependency SRC-POTFILES -> SRC-POTFILES.in -> ../Makefile cannot +# be satisfied. +# +# The SRC-POTFILES and BLD-POTFILES dependencies cannot be removed, +# however since it is necessary that these files be built during +# *configure* time, so that configure can insert them into the +# po/Makefile that it is creating, so that the Makefile will have +# the correct dependencies. +Makefile: Make-in ../config.status SRC-POTFILES BLD-POTFILES + cd .. \ + && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ + CONFIG_HEADERS= $(SHELL) ./config.status + +# Tell versions [3.59,3.63) of GNU make not to export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/external/gpl3/gdb/dist/bfd/po/SRC-POTFILES.in b/external/gpl3/gdb/dist/bfd/po/SRC-POTFILES.in new file mode 100644 index 000000000000..729b70421849 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/SRC-POTFILES.in @@ -0,0 +1,353 @@ +aix386-core.c +aix5ppc-core.c +aout-adobe.c +aout-arm.c +aout-cris.c +aout-ns32k.c +aout-sparcle.c +aout-target.h +aout-tic30.c +aout0.c +aout32.c +aout64.c +aoutf1.h +aoutx.h +archive.c +archive64.c +archures.c +armnetbsd.c +bfd.c +bfdio.c +bfdwin.c +binary.c +bout.c +cache.c +cf-i386lynx.c +cf-sparclynx.c +cisco-core.c +coff-alpha.c +coff-apollo.c +coff-arm.c +coff-aux.c +coff-go32.c +coff-h8300.c +coff-h8500.c +coff-i386.c +coff-i860.c +coff-i960.c +coff-m68k.c +coff-m88k.c +coff-mips.c +coff-or32.c +coff-rs6000.c +coff-sh.c +coff-sparc.c +coff-stgo32.c +coff-svm68k.c +coff-tic30.c +coff-tic4x.c +coff-tic54x.c +coff-tic80.c +coff-u68k.c +coff-w65.c +coff-we32k.c +coff-x86_64.c +coff-z80.c +coff-z8k.c +coff64-rs6000.c +coffcode.h +coffgen.c +cofflink.c +coffswap.h +compress.c +corefile.c +cpu-alpha.c +cpu-arc.c +cpu-arm.c +cpu-avr.c +cpu-bfin.c +cpu-cr16.c +cpu-cr16c.c +cpu-cris.c +cpu-crx.c +cpu-d10v.c +cpu-d30v.c +cpu-dlx.c +cpu-fr30.c +cpu-frv.c +cpu-h8300.c +cpu-h8500.c +cpu-hppa.c +cpu-i370.c +cpu-i386.c +cpu-i860.c +cpu-i960.c +cpu-ia64.c +cpu-ip2k.c +cpu-iq2000.c +cpu-l1om.c +cpu-lm32.c +cpu-m10200.c +cpu-m10300.c +cpu-m32c.c +cpu-m32r.c +cpu-m68hc11.c +cpu-m68hc12.c +cpu-m68k.c +cpu-m88k.c +cpu-mcore.c +cpu-mep.c +cpu-microblaze.c +cpu-mips.c +cpu-mmix.c +cpu-moxie.c +cpu-msp430.c +cpu-mt.c +cpu-ns32k.c +cpu-openrisc.c +cpu-or32.c +cpu-pdp11.c +cpu-pj.c +cpu-plugin.c +cpu-powerpc.c +cpu-rs6000.c +cpu-rx.c +cpu-s390.c +cpu-score.c +cpu-sh.c +cpu-sparc.c +cpu-spu.c +cpu-tic30.c +cpu-tic4x.c +cpu-tic54x.c +cpu-tic6x.c +cpu-tic80.c +cpu-v850.c +cpu-vax.c +cpu-w65.c +cpu-we32k.c +cpu-xc16x.c +cpu-xstormy16.c +cpu-xtensa.c +cpu-z80.c +cpu-z8k.c +demo64.c +dwarf1.c +dwarf2.c +ecoff.c +ecofflink.c +ecoffswap.h +elf-attrs.c +elf-bfd.h +elf-eh-frame.c +elf-hppa.h +elf-ifunc.c +elf-m10200.c +elf-m10300.c +elf-strtab.c +elf-vxworks.c +elf.c +elf32-am33lin.c +elf32-arc.c +elf32-arm.c +elf32-avr.c +elf32-bfin.c +elf32-cr16.c +elf32-cr16c.c +elf32-cris.c +elf32-crx.c +elf32-d10v.c +elf32-d30v.c +elf32-dlx.c +elf32-fr30.c +elf32-frv.c +elf32-gen.c +elf32-h8300.c +elf32-hppa.c +elf32-hppa.h +elf32-i370.c +elf32-i386.c +elf32-i860.c +elf32-i960.c +elf32-ip2k.c +elf32-iq2000.c +elf32-lm32.c +elf32-m32c.c +elf32-m32r.c +elf32-m68hc11.c +elf32-m68hc12.c +elf32-m68hc1x.c +elf32-m68k.c +elf32-m88k.c +elf32-mcore.c +elf32-mep.c +elf32-microblaze.c +elf32-mips.c +elf32-moxie.c +elf32-msp430.c +elf32-mt.c +elf32-openrisc.c +elf32-or32.c +elf32-pj.c +elf32-ppc.c +elf32-rx.c +elf32-s390.c +elf32-score.c +elf32-score7.c +elf32-sh-symbian.c +elf32-sh.c +elf32-sh64-com.c +elf32-sh64.c +elf32-sparc.c +elf32-spu.c +elf32-tic6x.c +elf32-v850.c +elf32-vax.c +elf32-xc16x.c +elf32-xstormy16.c +elf32-xtensa.c +elf32.c +elf64-alpha.c +elf64-gen.c +elf64-hppa.c +elf64-hppa.h +elf64-mips.c +elf64-mmix.c +elf64-ppc.c +elf64-s390.c +elf64-sh64.c +elf64-sparc.c +elf64-x86-64.c +elf64.c +elfcode.h +elfcore.h +elflink.c +elfn32-mips.c +elfxx-mips.c +elfxx-sparc.c +epoc-pe-arm.c +epoc-pei-arm.c +format.c +freebsd.h +genlink.h +go32stub.h +hash.c +hp300bsd.c +hp300hpux.c +hpux-core.c +i386aout.c +i386bsd.c +i386dynix.c +i386freebsd.c +i386linux.c +i386lynx.c +i386mach3.c +i386msdos.c +i386netbsd.c +i386os9k.c +ieee.c +ihex.c +init.c +irix-core.c +libaout.h +libbfd.c +libbfd.h +libcoff.h +libecoff.h +libhppa.h +libieee.h +libnlm.h +liboasys.h +libpei.h +libxcoff.h +linker.c +lynx-core.c +m68k4knetbsd.c +m68klinux.c +m68knetbsd.c +m88kmach3.c +m88kopenbsd.c +mach-o-i386.c +mach-o-x86-64.c +mach-o.c +mach-o.h +merge.c +mipsbsd.c +mmo.c +netbsd.h +newsos3.c +nlm-target.h +nlm.c +nlm32-alpha.c +nlm32-i386.c +nlm32-ppc.c +nlm32-sparc.c +nlm32.c +nlm64.c +nlmcode.h +nlmswap.h +ns32k.h +ns32knetbsd.c +oasys.c +opncls.c +osf-core.c +pc532-mach.c +pdp11.c +pe-arm-wince.c +pe-arm.c +pe-i386.c +pe-mcore.c +pe-mips.c +pe-ppc.c +pe-sh.c +pe-x86_64.c +pef-traceback.h +pef.c +pef.h +pei-arm-wince.c +pei-arm.c +pei-i386.c +pei-ia64.c +pei-mcore.c +pei-mips.c +pei-ppc.c +pei-sh.c +pei-x86_64.c +peicode.h +plugin.c +ppcboot.c +reloc.c +reloc16.c +riscix.c +sco5-core.c +section.c +simple.c +som.c +som.h +sparclinux.c +sparclynx.c +sparcnetbsd.c +srec.c +stab-syms.c +stabs.c +sunos.c +syms.c +targets.c +tekhex.c +trad-core.c +vax1knetbsd.c +vaxbsd.c +vaxnetbsd.c +verilog.c +versados.c +version.h +vms-alpha.c +vms-lib.c +vms-misc.c +vms.h +xcoff-target.h +xcofflink.c +xsym.c +xsym.h +xtensa-isa.c +xtensa-modules.c diff --git a/external/gpl3/gdb/dist/bfd/po/bfd.pot b/external/gpl3/gdb/dist/bfd/po/bfd.pot new file mode 100644 index 000000000000..b41935064c03 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/bfd.pot @@ -0,0 +1,6002 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. +# FIRST AUTHOR , YEAR. +# +#, fuzzy +msgid "" +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 10:27+0100\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=CHARSET\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "" + +#: aoutx.h:1577 +#, c-format +msgid "" +"%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "" + +#: bfd.c:395 +msgid "No error" +msgstr "" + +#: bfd.c:396 +msgid "System call error" +msgstr "" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "" + +#: bfd.c:402 +msgid "No symbols" +msgstr "" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "" + +#: bfd.c:411 +msgid "Bad value" +msgstr "" + +#: bfd.c:412 +msgid "File truncated" +msgstr "" + +#: bfd.c:413 +msgid "File too big" +msgstr "" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "" + +#: bfd.c:415 +msgid "#" +msgstr "" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "" + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "" +"error: %B passes floats in float registers, whereas %B passes them in " +"integer registers" +msgstr "" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "" +"error: %B passes floats in integer registers, whereas %B passes them in " +"float registers" +msgstr "" + +#: coff-arm.c:2243 +#, c-format +msgid "" +"error: %B is compiled as position independent code, whereas target %B is " +"absolute position" +msgstr "" + +#: coff-arm.c:2246 +#, c-format +msgid "" +"error: %B is compiled as absolute position code, whereas target %B is " +"position independent" +msgstr "" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr "" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr "" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr "" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr "" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr "" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr "" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr "" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "" +"Warning: Not setting interworking flag of %B since it has already been " +"specified as non-interworking" +msgstr "" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "" +"%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "" + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "" + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "" + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "" + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "" + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "" + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "" + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "" + +#: dwarf2.c:2343 +#, c-format +msgid "" +"Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 " +"and 4 information." +msgstr "" + +#: dwarf2.c:2350 +#, c-format +msgid "" +"Dwarf Error: found address size '%u', this reader can not handle sizes " +"greater than '%u'." +msgstr "" + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "" + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" + +#: elf-attrs.c:569 +msgid "" +"error: %B: Object has vendor-specific contents that must be processed by the " +"'%s' toolchain" +msgstr "" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "" + +#: elf-eh-frame.c:1165 +msgid "" +"%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "" + +#: elf-ifunc.c:179 +msgid "" +"%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can " +"not be used when making an executable; recompile with -fPIE and relink with -" +"pie\n" +msgstr "" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "" + +#: elf-m10300.c:1569 +msgid "" +"error: inappropriate relocation type for shared library (did you forget -" +"fpic?)" +msgstr "" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr "" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "" + +#: elf.c:1943 +msgid "" +"%B: don't know how to handle allocated, application specific section `%s' [0x" +"%8x]" +msgstr "" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "" + +#: elf.c:4480 +msgid "" +"%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "" + +#: elf.c:6622 +#, c-format +msgid "" +"Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "" + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "" +"%B: warning: selected VFP11 erratum workaround is not necessary for target " +"architecture" +msgstr "" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "" + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "" + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "" + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "" + +#: elf32-arm.c:8438 +msgid "" +"%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group " +"relocations" +msgstr "" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "" + +#: elf32-arm.c:9569 +msgid "" +"Warning: Clearing the interworking flag of %B because non-interworking code " +"in %B has been linked with it" +msgstr "" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "" + +#: elf32-arm.c:9942 +msgid "" +"Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "" + +#: elf32-arm.c:10273 +msgid "" +"warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; " +"use of wchar_t values across objects may fail" +msgstr "" + +#: elf32-arm.c:10304 +msgid "" +"warning: %B uses %s enums yet the output is to use %s enums; use of enum " +"values across objects may fail" +msgstr "" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr "" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr "" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr "" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr "" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr "" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr "" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr "" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr "" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr "" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr "" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr "" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr "" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr "" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr "" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr "" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr "" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr "" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr "" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr "" + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr "" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr "" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "" +"%B: relocation %s against `%s' can not be used when making a shared object; " +"recompile with -fPIC" +msgstr "" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "" + +#: elf32-arm.c:14078 +msgid "" +"error: Source object %B has EABI version %d, but target %B has EABI version %" +"d" +msgstr "" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "" + +#: elf32-cris.c:1361 +msgid "" +"%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "" +"%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "" +"%B, section %A: relocation %s has an undefined reference to `%s', perhaps a " +"declaration mixup?" +msgstr "" + +#: elf32-cris.c:1998 +msgid "" +"%B, section %A: relocation %s is not allowed for symbol: `%s' which is " +"defined outside the program, perhaps a declaration mixup?" +msgstr "" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "" + +#: elf32-cris.c:2058 +msgid "" +"(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or " +"-mno-small-tls)" +msgstr "" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, " +"recompile with -fPIC" +msgstr "" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr "" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr "" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr "" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "" + +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "" + +#: elf32-frv.c:6728 +#, c-format +msgid "" +"%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "" + +#: elf32-frv.c:6793 +#, c-format +msgid "" +"%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%" +"lx)" +msgstr "" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "" + +#: elf32-hppa.c:1284 +msgid "" +"%B: relocation %s can not be used when making a shared object; recompile " +"with -fPIC" +msgstr "" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "" + +#: elf32-hppa.c:3449 +msgid "" +"%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr "" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "" +"%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "" + +#: elf32-i386.c:3331 +msgid "" +"%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when " +"making a shared object" +msgstr "" + +#: elf32-i386.c:3341 +msgid "" +"%B: relocation R_386_GOTOFF against protected function `%s' can not be used " +"when making a shared object" +msgstr "" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "" +"ip2k relaxer: switch table without complete matching relocation information." +msgstr "" + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "" + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "" + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "" + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr "" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr "" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr "" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "" +"Reference to the far symbol `%s' using a wrong relocation may result in " +"incorrect execution" +msgstr "" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "" +"banked address [%lx:%04lx] (%lx) is not in the same bank as current banked " +"address [%lx:%04lx] (%lx)" +msgstr "" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "" +"reference to a banked address [%lx:%04lx] in the normal address space at %" +"04lx" +msgstr "" + +#: elf32-m68hc1x.c:1225 +msgid "" +"%B: linking files compiled for 16-bit integers (-mshort) and others for 32-" +"bit integers" +msgstr "" + +#: elf32-m68hc1x.c:1232 +msgid "" +"%B: linking files compiled for 32-bit double (-fshort-double) and others for " +"64-bit double" +msgstr "" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "" + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "" + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "" + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "" + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr "" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr "" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "" + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "" + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "" + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "" +"Warning: %B uses double-precision hard float, %B uses single-precision hard " +"float" +msgstr "" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "" + +#: elf32-ppc.c:4197 +msgid "" +"%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "" + +#: elf32-ppc.c:4205 +msgid "" +"%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "" +"%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "" + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "" + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr "" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr "" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "" + +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr "" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr "" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr "" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr "" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr "" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "" + +#: elf32-spu.c:4359 +msgid "" +"non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local " +"store\n" +msgstr "" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "" + +#: elf32-v850.c:176 +#, c-format +msgid "" +"Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "" + +#: elf32-v850.c:179 +#, c-format +msgid "" +"Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "" + +#: elf32-v850.c:182 +#, c-format +msgid "" +"Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "" + +#: elf32-v850.c:185 +#, c-format +msgid "" +"Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "" + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr "" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr "" + +#: elf32-vax.c:654 +#, c-format +msgid "" +"%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of " +"%ld" +msgstr "" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "" +"%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:7265 +msgid "" +"%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY " +"relocation; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%" +"08lx\n" +msgstr "" + +#: elf64-mmix.c:1607 +#, c-format +msgid "" +"%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "" + +#: elf64-mmix.c:1726 +#, c-format +msgid "" +"%s: LOCAL directive: Register $%ld is not a local register. First global " +"register is $%ld." +msgstr "" + +#: elf64-mmix.c:2190 +#, c-format +msgid "" +"%s: Error: multiple definition of `%s'; start of %s is set in a earlier " +"linked file\n" +msgstr "" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "" + +#: elf64-ppc.c:6473 +#, c-format +msgid "" +"copy reloc against `%s' requires lazy plt linking; avoid setting " +"LD_BIND_NOW=1 or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" + +#: elf64-ppc.c:12190 +msgid "" +"%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; " +"recompile with -mminimal-toc or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:12198 +msgid "" +"%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic " +"multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, " +"or make `%s' extern" +msgstr "" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "" + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf64-x86-64.c:2801 +msgid "" +"%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "" + +#: elf64-x86-64.c:3073 +msgid "" +"%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be " +"used when making a shared object" +msgstr "" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "" + +#: elf64-x86-64.c:3189 +msgid "" +"%B: relocation %s against %s `%s' can not be used when making a shared object" +"%s" +msgstr "" + +#: elf64-x86-64.c:3191 +msgid "" +"%B: relocation %s against undefined %s `%s' can not be used when making a " +"shared object%s" +msgstr "" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "" + +#: elflink.c:1119 +msgid "" +"%s: TLS definition in %B section %A mismatches non-TLS definition in %B " +"section %A" +msgstr "" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "" + +#: elflink.c:2166 +msgid "" +"%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "" + +#: elflink.c:2177 +msgid "" +"%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the " +"object file has no symbol table" +msgstr "" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "" + +#: elflink.c:4285 +msgid "" +"Warning: alignment %u of common symbol `%s' in %B is greater than the " +"alignment (%u) of its section %A" +msgstr "" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "" + +#: elflink.c:4475 +msgid "" +"note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "" + +#: elflink.c:9428 +msgid "" +"error: %B contains a reloc (0x%s) for section %A that references a non-" +"existent global symbol" +msgstr "" + +#: elflink.c:9494 +msgid "" +"%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' " +"of %B\n" +msgstr "" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "" + +#: elfxx-mips.c:5623 +msgid "" +"%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider " +"recompiling with interlinking enabled." +msgstr "" + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "" + +#: elfxx-mips.c:9068 +msgid "" +"%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%" +"A'" +msgstr "" + +#: elfxx-mips.c:9207 +msgid "" +"small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr "" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr "" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr "" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr "" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr "" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr "" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr "" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr "" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr "" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr "" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr "" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr "" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr "" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr "" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr "" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr "" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr "" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr "" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr "" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr "" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "" + +#: mmo.c:1332 +#, c-format +msgid "" +"%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name " +"starting with `%s'\n" +msgstr "" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" + +#: mmo.c:1657 +#, c-format +msgid "" +"%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1705 +#, c-format +msgid "" +"%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1728 +#, c-format +msgid "" +"%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d " +"for lop_fixrx\n" +msgstr "" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "" + +#: mmo.c:1771 +#, c-format +msgid "" +"%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "" + +#: mmo.c:1784 +#, c-format +msgid "" +"%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" + +#: mmo.c:1890 +#, c-format +msgid "" +"%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "" + +#: mmo.c:1939 +#, c-format +msgid "" +"%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras " +"to the preceding lop_stab (%ld)\n" +msgstr "" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "" + +#: mmo.c:2889 +#, c-format +msgid "" +"%s: Bad symbol definition: `Main' set to %s rather than the start address %" +"s\n" +msgstr "" + +#: mmo.c:2981 +#, c-format +msgid "" +"%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: " +"%d. Only `Main' will be emitted.\n" +msgstr "" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "" + +#: mmo.c:3140 +#, c-format +msgid "" +"%s: invalid start address for initialized registers of length %ld: 0x%lx%" +"08lx\n" +msgstr "" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1174 +msgid "" +"%B: Recognised but unhandled machine type (0x%x) in Import Library Format " +"archive" +msgstr "" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "" + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "" + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr "" + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr "" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr "" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr "" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr "" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr "" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr "" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr "" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr "" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr "" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr "" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr "" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr "" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr "" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr "" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr "" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr "" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr "" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr "" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr "" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr "" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr "" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr "" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr "" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr "" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr "" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr "" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr "" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr "" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr "" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr "" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr "" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr "" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr "" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr "" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr "" + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr "" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr "" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr "" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr "" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr "" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr "" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr "" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr "" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr "" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr "" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr "" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr "" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr "" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr "" + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr "" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr "" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr "" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr "" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr "" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr "" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr "" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr "" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr "" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr "" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "" + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "" + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr "" + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr "" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr "" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr "" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr "" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr "" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr "" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr "" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr "" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr "" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr "" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr "" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr "" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr "" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr "" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr "" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr "" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr "" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr "" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr "" + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr "" + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr "" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr "" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr "" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr "" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr "" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr "" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr "" + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "" + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "" + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "" + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "" + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "" + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "" + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "" + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "" + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "" + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "" + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "" + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "" + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "" + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "" + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "" + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "" + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "" + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "" + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "" + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "" + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr "" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr "" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr "" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr "" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr "" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr "" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr "" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "" + +#: vms-alpha.c:7576 +#, c-format +msgid "" +"Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr "" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr "" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr "" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr "" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr "" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr "" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr "" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr "" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr "" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr "" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr "" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr "" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr "" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr "" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr "" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr "" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr "" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr "" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr "" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr "" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr "" + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "" +"%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect " +"branch." +msgstr "" + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "" +"%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%" +"A'." +msgstr "" + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "" +"%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> " +"0x1000000)." +msgstr "" + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" + +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr "" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr "" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr "" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "" +"%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because ." +"idata$6 is missing" +msgstr "" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "" +"%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because ." +"idata$6 is missing" +msgstr "" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill 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znLjn@U>nb{-ZD#`UOkhCywTunc={&{=~2sPf;Je^#~sW)CLGDiKp7}rB`OZ(Sa0vb zDG|}IA$bT7mL%5FWf?7u7B-+GA+R0<;#khE@Lto8(ISyxRtX8rv8FaSJn40u-^kRN zH-<{M#Y$b`S;CiKCIS_t^mH3_)SOykYOam7WJ#q)wz)eezJ_Evmgbtj|Z3Vq^5O=T$wIr3`}&{ zxTG<1Fd+Betyd;$Fp;bmic=IO@8^-3&RlNsZhJ@DAg03__@TldFqN(%z1S zm%_+$&BN(WS31ChUC}U24rQL>Ov7dLfoAHBD~yU3OL^9g@`xRj1M{rze7?qs^*I?Jh+-u}i5EmIF) z7L=1ze#L#dtJNg=0r7rPu!O}3ULd$1g`~uZ_q<=e=gXzHU&5E9-W$OIi1o%(1;eeNC zEz0HEhVpqsU<%YyN9#V4@OjLCh0s@KdyrLm zgb%P#5y%an?R%e{~%w>D5l6(oz>8S%VdJJ zO%D=2*zi^geynK*%aL0L(XqX?~F6fmoGB1ySw8w@@rq81a=RW=og_E5{B8O^+i*=-w zM*3c?W6@Py!emZk4Kdnf92&!?GXS%a, 2002-2003 +# Ask Hjorth Larsen , 2011 +# +# Følgende konventioner bruges, men jeg er ikke sikker pÃ¥ at de nødvendigvis er de bedste: +# +# entry (alene) -> post +# entry point -> startpunkt +# link -> lænke +# overlay -> overlay +# relax -> forenkle +# record -> post +# image -> aftryk +# TOC -> TOC (=table of contents, evt. indholdsfortegnelse) +msgid "" +msgstr "" +"Project-Id-Version: bfd-2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2011-03-16 02:31+0100\n" +"Last-Translator: Ask Hjorth Larsen \n" +"Language-Team: Danish \n" +"Language: da\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Ukendt sektionstype i a.out.adobe-fil: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Ugyldig relokeringstype eksporteret: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Ugyldig relokeringstype importeret: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Fejlagtig relokeringspost importeret: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: kan ikke repræsentere sektionen \"%s\" i a.out-objektfilformat" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: kan ikke repræsentere sektion for symbolet \"%s\" i a.out-objektfilformat" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*ukendt*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: uventet relokeringstype\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: relokérbar lænke fra %s til %s understøttes ikke" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Advarsel: arkivskrivning var langsom: genskriver tidsstempel\n" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "Læser arkivfilens ændringstidsstempel" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "Skriver opdateret armap-tidsstempel" + +#: bfd.c:395 +msgid "No error" +msgstr "Ingen fejl" + +#: bfd.c:396 +msgid "System call error" +msgstr "Systemkaldsfejl" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "Ugyldigt bfd-mÃ¥l" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "Filen er i forkert format" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "Arkivobjektfil er i forkert format" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "Ugyldig handling" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "Hukommelsen er opbrugt" + +#: bfd.c:402 +msgid "No symbols" +msgstr "Ingen symboler" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "Arkivet har intet indeks; kør ranlib til at tilføje ét" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "Ikke flere arkiverede filer" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "Forvansket arkiv" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "Filformatet ikke genkendt" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "Filformatet er flertydigt" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "Sektionen har intet indhold" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "Ikkerepræsenterbar sektion i uddata" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "Symbolet kræver fejlsøgningssektion som ikke eksisterer" + +#: bfd.c:411 +msgid "Bad value" +msgstr "Fejlagtigt værdi" + +#: bfd.c:412 +msgid "File truncated" +msgstr "Filen trunkeret" + +#: bfd.c:413 +msgid "File too big" +msgstr "Filen er for stor" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "Fejl ved læsning af %s: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s-forsikring mislykkedes %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "Intern BFD %s-fejl, afbryder ved %s linje %d i %s\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "Internt BFD %s-fejl, afbryder ved %s linje %d\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "Rapportér gerne denne fejl.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "mapper ikke: data=%lx mappet=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "mapper ikke: miljøvariabel er ikke sat\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Advarsel: Skrivning af sektionen \"%s\" til enorm (dvs negativ) afsætsbyte 0x%lx." + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax og -r kan ikke bruges sammen\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "genÃ¥bner %B: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Kan ikke hÃ¥ndtere komprimerede Alpha-binærfiler.\n" +" Brug kompilerflag eller objZ til at generere ukomprimerede binærfiler." + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: relokeringstypen %d kendes eller understøttes ikke" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "GP-relativ relokering bruges nÃ¥r GP ikke er defineret" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "bruger flere gp-værdier" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: relokering understøttes ikke: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: relokering understøttes ikke: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: ukendt relokeringstype %d" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: kan ikke finde THUMB-klistret \"%s\" til \"%s\"" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: kan ikke finde ARM-klistret \"%s\" til \"%s\"" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): advarsel: samvirken (interworking) er ikke aktiveret.\n" +" første forekomst: %B: arm-kald til thumb" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): advarsel: \"Interworking\" er ikke slÃ¥et til.\n" +" første forekomst: %B: thumb-kald til arm\n" +" overvej at genlænke med --support-old-code tilvalgt" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: fejlagtig relokeringsadresse 0x%lx i sektionen \"%s\"" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: illegalt symbolindeks i relokering: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "fejl: %B er kompileret til APCS-%d, mens %B er kompileret til APCS-%d" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "fejl: %B overfører flydende tal i flydendetalsregistre, mens %B overfører dem i heltalsregistre" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "fejl: %B overfører flydende tal i heltalsregistre, mens %B overfører dem i flydendetalsregistre" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "fejl: %s er kompileret som positionsuafhængig kode, mens mÃ¥let %B har absolut position" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "fejl: %B er kompileret som kode med absolut position, mens mÃ¥let %B er positionsuafhængigt" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Advarsel: %B understøtter samvirken (interworking), mens %B ikke gør det" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Advarsel: %B understøtter ikke samvirken (interworking), mens %B gør det" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "private flag = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [flydende tal overført i flydendetalsregistre]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [flydende tal overført i heltalsregistre]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr " [positionsuafhængigt]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr " [absolut position]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [samvirkendeflag er ikke initieret]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr " [samvirken understøttes]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr " [samvirken understøttes ikke]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Advarsel: Sætter ikke samvirkeflaget (interworking) for %B, da den allerede er angivet som ikke-samvirkende" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Advarsel: Fjerner samvirkeflaget (interworking) for %B pÃ¥ grund af anmodning udefra" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "kan ikke hÃ¥ndtere R_MEM_INDIRECT-relokering ved brug af %s-uddata" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Relokeringen \"%s\" er endnu ikke implementeret\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: advarsel: illegalt symbolindeks %ld i relokeringerne" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "usikker kaldskonvention for ikke-COFF-symbol" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "relokeringstypen understøttes ikke" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "GP-relativ relokering nÃ¥r _gp ikke var defineret" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "Ukendt relokering" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: relokeringstypen 0x%02x understøttes ikke" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: TOC-relokering ved 0x%x til symbolet \"%s\" uden nogen TOC-post" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: symbolet \"%s\" har ukendt smclas %d" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Ukendt relokeringstype 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: advarsel: ikke tilladt symbolindeks %ld i relokeringerne" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "ignorerer relokering %s\n" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: advarsel: COMDAT-symbol \"%s\" passer ikke til sektionsnavnet \"%s\"" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Advarsel: Ignorerer sektionsflag IMAGE_SCN_MEM_NOT_PAGED i sektionen %s" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Sektionsflag %s (0x%x) ignoreret" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Ukendt TI COFF-mÃ¥l-id \"0x%x\"" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: relokering mod et ikke-eksisterende symbolindeks: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: for mange sektioner (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: sektion %s: overløb i strengtabel ved afsæt %ld" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: advarsel: læsning af linjenummertabel mislykkedes" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: advarsel: illegalt symbolindeks %ld i linjetal" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: advarsel: dobbelt linjenummersinformation for \"%s\"" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: Ukendt lagringsklasse %d for %s-symbolet \"%s\"" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "advarsel: %B: lokalt symbol \"%s\" har ingen sektion" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: ikke tilladt relokeringstype %d pÃ¥ adresse 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: fejlagtig strengtabelstørrelse %lu" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Advarsel: typen pÃ¥ symbol \"%s\" ændredes fra %d til %d i %B" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: relokeringer i sektionen \"%s\", men den har intet indhold" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: relokering giver overløb: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: advarsel: %s: linjenummer giver overløb: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "fejl: %B kompileret til EP9312, mens %B er kompileret til XScale" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "advarsel: kan ikke opdatere indholdet af %s-sektion i %s" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Dwarf-fejl: Kan ikke finde %s-sektion." + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Dwarf-fejl: Afsæt (%lu) større end eller lig med %s-størrelse (%lu)." + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf-fejl: Ugyldig eller ubehandlet FORM-værdi: %u." + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf-fejl: vanskabt linjenummerssektion (fejlagtigt filnummer)." + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Dwarf-fejl: UhÃ¥ndteret .debug_line-version %d." + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Dwarf-fejl: Ugyldigt maksimalt antal operationer per instruktion." + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf-fejl: vanskabt linjenummerssektion." + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf-fejl: Kunne ikke finde forkortelsesnumret %u." + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Dwarf-fejl: fandt dwarf version \"%u\", men denne læser kan kun hÃ¥ndtere information fra version 2, 3 og 4." + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf-fejl: fandt adressestørrelsen \"%u\", denne læser kan ikke hÃ¥ndtere størrelser større end \"%u\"." + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf-fejl: Fejlagtigt forkortelsesnummer: %u." + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "Ukendt grundtype %d" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Symbol slut+1: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Første symbol: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Symbol slut+1: %-7ld Type: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Lokalt symbol: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; symbol slut+1: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; symbol slut+1: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; symbol slut+1: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Type: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "fejl: %B: Objekt har leverandørspecifikt indhold, som skal behandles med '%s'-værktøjerne" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "fejl: %B: Objektmærke \"%d, %d\" er ikke kompatibelt med mærket \"%d, %s\"" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: fejl i %B(%A); ingen .eh_frame_hdr-tabel vil blive oprettet.\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: fde-kodning i %B(%A) forhindrer .eh_frame_hdr-tabel i at blive oprettet.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: dynamisk STT_GNU_IFUNC-symbol \"%s\" med pointerlighed i \"%B\" kan ikke bruges nÃ¥r der oprettes en eksekverbar fil; genkompilér med -fPIE og genlænk med -pie\n" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "intern fejl: uden for intervallet" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "intern fejl: relokeringen understøttes ikke" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "intern fejl: farlig fejl" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "intern fejl: ukendt fejl" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): uløselig %s-relokering mod symbol \"%s\"" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "fejl: upassende relokeringstype til delt bibliotek (glemte du -fpic?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "intern fejl: mistænkelig relokeringstype brugt i delt bibliotek" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "dynamisk variabel \"%s\" har størrelse nul" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: ugyldigt strengafsæt %u >= %lu for sektionen \"%s\"" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B-symbol nummer %lu refererer SHT_SYMTAB_SHNDX-sektion, der ikke findes" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Beskadiget størrelsesfelt i gruppesektionshoved: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: ugyldig SHT_GROUP-post" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: ingen gruppeinformation for sektionen %A" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: advarsel: sh_link ikke givet for sektionen \"%s\"" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%d] sektionen \"%s\" er forkert" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: ukendt [%d] sektion \"%s\" i gruppe [%s]" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: kan ikke initiere commpress-status for sektion %s" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: kan ikke klargøre afkomprimeringsstatus for sektion %s" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Programhoved:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Dynamisk sektion:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Versionsdefinitioner:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Versionsreferencer:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " kræves fra %s:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: ugyldig lænke %lu for relokeringssektion %s (indeks %u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: ved ikke hvordan allokeret, programspecifik sektion \"%s\" [0x%8x] skal hÃ¥ndteres" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: ved ikke hvordan processorspecifik sektion \"%s\" [0x%8x] skal hÃ¥ndteres" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: ved ikke hvordan OS-specifik sektion \"%s\" [0x%8x] skal hÃ¥ndteres" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: ved ikke hvordan sektion \"%s\" [0x%8x] skal hÃ¥ndteres" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "advarsel: typen af sektionen \"%A\" ændret til PROGBITS" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link af sektion \"%A\" peger pÃ¥ forkastet sektion \"%A\" i \"%B\"" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link af sektion \"%A\" peger pÃ¥ fjernet sektion \"%A\" af \"%B\"" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: Første sektion i segmentet PT_DYNAMIC er ikke .dynamic-sektionen" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%s: Ikke tilstrækkeligt med plads til programhoveder, forsøg at lænke med -N" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "%B: sektion %A lma %#lx justeret til %#lx" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: sektion \"%A\" kan ikke allokeres i segment %d" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: advarsel: allokeret sektion \"%s\" ikke i segment" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: symbol \"%s\" kræves, men er ikke tilstede" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: advarsel: Tomt indlæseligt segment opdaget, er dette meningen?\n" + +#: elf.c:6622 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Kunne ikke finde ækvivalent uddatasektion for symbolet \"%s\" fra sektionen \"%s\"" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: relokeringstypen %s understøttes ikke" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%s(%s): advarsel: samvirken (interworking) er ikke aktiveret.\n" +" første forekomst: %B: Thumb-kald til ARM" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): advarsel: samvirken (interworking) er ikke aktiveret.\n" +" første forekomst: %B: ARM-kald til Thumb" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: kan ikke oprette stub-posten %s" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "kan ikke finde finde THUMB-klistret \"%s\" til \"%s\"" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "kan ikke finde ARM-klistret \"%s\" til \"%s\"" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: BE8-aftryk er kun gyldige i big-endian-tilstanden." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: advarsel: valgte omgÃ¥else af VFP11-erratum er ikke nødvendig for mÃ¥larkitekturen" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: kan ikke finde VFP11-veneer \"%s\"" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Ugyldig TARGET2-relokeringstype \"%s\"." + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): advarsel: samvirken (interworking) er ikke aktiveret.\n" +" første forekomst: %B: thumb-kald til arm" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Advarsel: Arm BLX-instruktion bruger Arm-funktionen \"%s\" som mÃ¥l." + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Advarsel: Thumb BLX-instruktionen bruger thumb-funktionen \"%s\" som mÃ¥l." + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): Relokering af R_ARM_TLS_LE32 er ikke tilladt i delt objekt" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Kun instruktionerne ADD og SUB er tilladt for ALU-grupperelokeringer" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Overløb ved opdeling af 0x%lx til grupperelokering %s" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s-relokering mod SEC_MERGE-sektion" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s bruges med TLS-symbol %s" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s bruges med ikke-TLS-symbol %s" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "uden for gyldigt interval" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "relokeringen understøttes ikke" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "ukendt fejl" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Advarsel: Fjerner samvirkendeflaget (interworking) i %B eftersom ikke-samvirkende kode i %B er lænket med det" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: Ukendt obligatorisk EABI-objekt-attribut %d" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Advarsel: %B: Ukendt EABI-objekt-attribut %d" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "Fejl: %B: Ukendt CPU-arkitektur" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "fejl: %B: Modstridende CPU-arkitekturer %d/%d" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "Fejl: %B har bÃ¥de nuværende og ældre Tag_MPextension_use-attributter" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "fejl: %B bruger VFP-registerargumenter, mens %B ikke gør" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "fejl: %B: kan ikke sammenføje virtualiseringsattributter med %B" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "fejl: %B: Modstridende arkitekturprofiler %c/%c" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Advarsel: %B: Modstridende platformkonfiguration" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "fejl: %B: Modstridende brug af R9" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "fejl: %B: SB-relativ adressering strider med brugen af R9" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "advarsel: %B bruger wchar_t pÃ¥ %u byte, men uddata skal bruge wchar_t pÃ¥ %u byte; brug af wchar_t-værdier pÃ¥ tværs af objekter kan gÃ¥ galt" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "advarsel: %B bruger %s-enum'er, men uddata skal bruge %s-enum'er; brug af enum-værdier pÃ¥ tværs af objekter kan gÃ¥ galt" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "fejl: %B bruger iWMMXt-registerargumenter, mens %B ikke gør" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "fejl: uoverensstemmelse i fp16-format mellem %B og %B" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "Uoverensstemmelse i DIV-forbrug mellem %B og %B" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "%B har bÃ¥de nuværende og ældre Tag_MPextension_use-attributter" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "private flag = %lx:" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [samvirkende er aktiveret]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [VFP-flydendetalsformat]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [Maverick-flydendetalformat]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [FPA-flydendetalformat]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [nyt ABI]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [gammelt ABI]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [programmeret FP]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [Version1 EABI]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [sorteret symboltabel]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [usorteret symboltabel]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [Version2 EABI]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [dynamiske symboler bruger segmentindeks]" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [mapningssymboler foretrækkes frem for andre]" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [Version3 EABI]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [Version4 EABI]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [Version5 EABI]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [relokérbar kørbar fil]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [har startpunkt]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: fejlagtigt symbolindeks: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relokeringen %s mod \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes; genkompilér med -fPIC" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Stødte pÃ¥ fejl ved behandling af filen %s" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: fejl: Cortex-A8-erratum-stub er allokeret pÃ¥ et usikkert sted" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: fejl: Cortex-A8-erratum-stub er uden for gyldigt interval (inddatafil for stor)" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: fejl: VFP11-veneer uden for gyldigt interval" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "fejl: %B er allerede i endeligt BE8-format" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "fejl: Kildeobjektet %B har EABI-version %d, men mÃ¥let %B har EABI-version %d" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "fejl: %B er kompileret til APCS-%d, mens mÃ¥let %B bruger APCS-%d" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "fejl: %B bruger VFP-instruktioner, mens %B ikke gør" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "fejl: %B bruger FPA-instruktioner, mens %B ikke gør" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "fejl: %B bruger Maverick-instruktioner, mens %B ikke gør" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "fejl: %B bruger ikke Maverick-instruktioner, men %B gør" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "fejl: %B bruger flydende tal i software, mens %B bruger hardware" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "fejl: %B bruger flydende tal i hardware, mens %B bruger software" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "intern fejl: farlig relokering" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: kan ikke oprette stub-post %s" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): uløselig relokering mod symbol \"%s\"" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): relokering mod \"%s\": fejl %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: relokering ved \"%A+0x%x\" refererer til symbolet \"%s\" med addend forskellig fra nul" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "relokering refererer symbol som ikke er defineret i modulet" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC refererer til dynamisk symbol med addend forskellig fra nul" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "kan ikke udsende fixup'er i skrivebeskyttet sektion %s" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "kan ikke udsende dynamiske relokeringer i skrivebeskyttet sektion" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE refererer dynamisk symbol med addend forskellig fra nul" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "relokeringer mellem forskellige segmenter understøttes ikke" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "advarsel: relokering refererer til et andet segment" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: relokeringstypen %i understøttes ikke" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: kan ikke lænke ikke-fdpic-objektfil ind i fdpic-eksekveringsfil" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: kan ikke lænke fdpic-objektfil ind i en ikke-fdpic-eksekveringsfil" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, sektion %A: uløselig relokering %s mod symbol \"%s\"" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, sektion %A: Hverken nogen PLT eller GOT til relokering %s mod symbol \"%s\"" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, sektion %A: Ingen PLT til relokering %s mod symbol \"%s\"" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "[hvis navn er tabt]" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, sektion %A: relokering %s med ikke-tom addend %d mod lokalt symbol" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, sektion %A: relokering %s med ikke-tom addend %d mod symbol \"%s\"" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, sektion %A: relokeringen %s er ikke tilladt for globalt symbol: \"%s\"" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, sektion %A: relokering %s oprettet uden nogen GOT" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, sektion %A: relokeringen %s har en udefineret reference til \"%s\". MÃ¥ske er der noget galt med erklæringen?" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B: relokeringen %A er ikke tilladt for symbol: \"%s\", som er defineret uden for programmet. MÃ¥ske er der noget galt med erklæringen?" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(for mange globale variable til -fpic: genkompilér med -fPIC)" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(trÃ¥dlokale data er for store til -fpic eller -msmall-tls: genkompilér med -fPIC eller -mno-small-tls)" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, sektion %A:\n" +" v10/v32-kompatibelt objekt %s mÃ¥ ikke indeholde en PIC-relokering" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, sektion %A:\n" +" relokeringen %s er ikke gyldig i et delt objekt; dette er typisk en fejl i tilvalgende - genkompilér med -fPIC" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, sektion %A:\n" +" relokeringen %s bør ikke bruges i et delt objekt; genoversæt med -fPIC" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, sektion %A til symbol \"%s\":\n" +" relokeringen %s bør ikke bruges i et delt objekt; genkompilér med -fPIC" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "Uventet maskinnummer" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [symboler har et _-præfiks]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 og v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: bruger symboler med _-præfiks, men skriver fil med symboler uden præfiks" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: bruger symboler uden præfiks, men skriver fil med symboler med _-præfiks" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B indeholder CRIS v32-kode, som er inkompatibel med tidligere objekter" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B indeholder ikke-CRIS-v32-kode, som er inkompatibel med tidligere objekter" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "relokering kræver addend pÃ¥ nul" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): relokering til \"%s+%x\" kan have forÃ¥rsaget ovenstÃ¥ende fejl" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF ikke anvendt til call-instruktion" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 ikke anvendt til en lddi-instruktion" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI ikke anvendt til en sethi-instruktion" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO ikke anvendt til en setlo- eller setlos-instruktion" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX ikke anvendt til en ldd-instruktion" + +# virkelig? +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX ikke anvendt til en calll-instruktion" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 ikke anvendt til en ldi-instruktion" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI ikke anvendt til en sethi-instruktion" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO ikke anvendt til en setlos-instruktion" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX ikke anvendt til en ld-instruktion" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI ikke anvendt til en sethi-instruktion" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO ikke anvendt til en setlos-instruktion" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC refererer dynamisk symbol med addend forskellig fra nul" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE refererer dynamisk symbol med addend forskellig fra nul" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): relokering mod \"%s\": %s" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "relokering refererer et andet segment" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: oversat med %s og lænket med moduler som bruger ikke-pic-relokering" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: oversat med %s og lænket med moduler som oversattes med %s" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: bruger andre ukendte e_flags-felter (0x%lx) end tidligere moduler (0x%lx)" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "private flag = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Relokeringer i generisk ELF (EM: %d)" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): kan ikke nÃ¥ %s, genkompilér med -ffunction-sections" + +#: elf32-hppa.c:1284 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relokeringen %s kan ikke bruges nÃ¥r et delt objekt oprettes; genkompilér med -fPIC" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "%B: dobbelt eksportstub %s" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s-\"fixup\" for instruktion 0x%x understøttes ikke i et ikke-delt lænke" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): kan ikke hÃ¥ndtere %s til %s" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr ".got-sektionen følger ikke umiddelbart efter .plt-sektion" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: ugyldig relokeringstype %d" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: TLS-overgang fra %s til %s mod \"%s\" ved 0x%lx i afsnittet \"%A\" mislykkedes" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: relokeringen %s mod STT_GNU_IFUNC-symbolet \"%s\" hÃ¥ndteres ikke af %s" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: \"%s\" tilgÃ¥s bÃ¥de som normalt symbol og trÃ¥dlokalt symbol" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: ukendt relokering (0x%x) i sektionen \"%A\"" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "skjult symbol" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "internt symbol" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "beskyttet symbol" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "symbol" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: relokeringen R_386_GOTOFF mod udefineret %s \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: relokeringen R_386_GOTOFF mod beskyttet funktion \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "forkastet uddatasektion: \"%A\"" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k relaxer: switch-tabel uden fuldstændig passende relokeringsinformation." + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k relaxer: switch-tabelhoved beskadiget." + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: manglende sideinstruktion ved 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: gentaget sideinstruktion ved 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "ikke-understøttet relokering mellem data/insn-adresserum" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: bruger andre e_flags-felter (0x%lx) end tidligere moduler (0x%lx)" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "global pointer-relativ relokering, nÃ¥r _gp ikke er defineret" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "global pointer-relativ adresse er uden for det gyldige interval" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "intern fejl: addend burde være nul for R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "SDA-relokering nÃ¥r _SDA_BASE_ ikke er defineret" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: MÃ¥let (%s) for en %s-relokering er i forkert sektion (%A)" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Instruktionssæt passer ikke med tidligere moduler" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "private flag = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": m32r-instruktioner" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": m32rx-instruktioner" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": m32r2-instruktioner" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Reference til fjernsymbol \"%s\", der bruger en forkert relokering, kan resultere i forkert udførelse" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "bankadresse [%lx:%04lx] (%lx) er ikke i samme bank som nuværende bankadresse [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "reference til bankadresse [%lx:%04lx] i det normale adresserum ved %04lx" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: lænker filer, der er kompileret til 16 bit-heltal (-mshort), og andre til 32 bit-heltal" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: lænker filer, der er kompileret til 32 bit-double (-fshort-double), og andre til 64 bit-double" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: lænkning af filer kompileret til HCS12 med andre, der er kompileret til HC12" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: bruger andre e_flags-felter (0x%lx) end tidligere moduler (0x%lx)" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "64-bit double, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "32-bit double, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +# ? +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr " [memory=bank-model]" + +# ? +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr " [memory=flat]" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "ukendt" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: GOT-overløb: Antallet af relokeringer med 8 bit-afsæt > %d" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: GOT-overløb: Antallet af relokeringer med 8 eller 16 bit-afsæt > %d" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_68K_TLS_LE32-relokering tillades ikke i delt objekt" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Relokering %s (%d) understøttes ikke i øjeblikket.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Ukendt relokeringstype %d\n" + +# ? +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B og %B er til forskellige cpu-kerner" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B og %B er til forskellige konfigurationer" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "private flag = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: ukendt relokeringstype %d" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: MÃ¥let (%s) for en %s-relokering er i forkert sektion (%s)" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: nok oversat uden -fPIC?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: fejlagtigt relokeringssektionsnavn \"%s\"" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "der sker ordret relokering for et eksternt symbol" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32-bit gp-relativ relokering forekommer for et eksternt symbol" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "generisk lænker kan ikke hÃ¥ndtere %s" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "beskadiget %s-sektion i %B" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "kan ikke læse i %s-sektion fra %B" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "advarsel: kan ikke sætte størrelsen af %s-sektion i %B" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "kunne ikke tildele plads til ny APUinfo-sektion." + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "kunne ikke beregne ny APUinfo-sektion." + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "kunne ikke installere ny APUinfo-sektion." + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: relokeringen %s kan ikke bruges nÃ¥r et delt objekt oprettes" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s-relokering mod lokalt symbol" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Advarsel: %B bruger flydende tal i hardware, %B bruger flydende tal i software" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Advarsel: %B bruger dobbeltpræcisions-float i hardware, mens %B bruger enkeltpræcisions-float i hardware" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Advarsel: %B bruger software-float, mens %B bruger enkeltpræcisions-float i hardware" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Advarsel: %B bruger ukendt ABI %d til flydende tal" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Advarsel: %B bruger ukendt vektor-ABI %d" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Advarsel: %B bruger vektor-ABI \"%s\", mens %B bruger \"%s\"" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Advarsel: %B bruger r3/r4 til smÃ¥ struktur-returneringer, mens %B bruger hukommelsen" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Advarsel: %B bruger ukendt returkonvention %d for smÃ¥strukturer" + +#: elf32-ppc.c:4197 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: kompileret med -mrelocatable og lænket med moduler som er kompileret normalt" + +#: elf32-ppc.c:4205 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: kompileret normalt og lænket med moduler som er kompileret med -mrelocatable" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "Bruger bss-plt pÃ¥ grund af %B" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: ukendt relokeringstype %d for symbol %s" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): addend forskellig fra nul pÃ¥ %s-relokering mod \"%s\"" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): relokering %s for indirekte funktion %s understøttes ikke" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: mÃ¥let (%s) for en %s-relokering er i den forkerte uddatasektion (%s)" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: relokeringen %s understøttes endnu ikke for symbolet %s." + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): relokering af %s mod \"%s\": fejl %d" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s er ikke defineret i lænker-oprettet %s" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%B:%A: Advarsel: forældet Red Hat-relokering " + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "Advarsel: RX_SYM-relokering med et ukendt symbol" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "%B(%A): fejl: kald til udefineret funktion \"%s\"" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "%B(%A): advarsel: ikke-justeret tilgang til symbol \"%s\" i det lille dataomrÃ¥de" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "%B(%A): intern fejl: uden for intervallet" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "%B(%A): intern fejl: relokeringen understøttes ikke" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "%B(%A): intern fejl: farlig relokering" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "%B(%A): intern fejl: ukendt fejl" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr " [64 bit-doubles]" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr " [dsp]" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): ugyldig instruktion til TLS-relokering %s" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "ikke nok med GOT-plads for lokale GOT-poster" + +# word er en datatype +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "adresse er ikke justeret til word-position" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Fejlagtig relokering for sektion %s opdaget" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL15-relokering ved 0x%lx er ikke mod globalt symbol" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr " [pic]" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr " [fix dep]" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: advarsel: lænker PIC-filer med ikke-PIC-filer" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: IMPORT AS-direktiv til %s skjuler forrige IMPORT AS" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: Ukendt .directive-kommando: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Kunne ikke tilføje omdøbt symbol %s" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: advarsel: fejlagtig R_SH_USES-afstand" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: advarsel: R_SH_USES peger pÃ¥ ukendt instruktion 0x%x" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: advarsel: fejlagtig R_SH_USES-indlæsningsafstand" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: advarsel: kunne ikke finde forventet relokering" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: advarsel: symbol i uventet sektion" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: advarsel: kunne ikke finde forventet COUNT-relokering" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: advarsel: fejlagtigt antal" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: fatalt: relokering giver overløb ved forenklingen" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Uventet STO_SH5_ISA32 pÃ¥ lokalt symbol hÃ¥ndteres ikke" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: fatalt: ujusteret grenmÃ¥l for relokering for forenklingsunderstøttelse" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%s: 0x%lx: fatalt: ujusteret %s-relokering 0x%lx" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatalt: R_SH_PSHA-relokering %d er uden for gyldigt interval -32..32" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatalt: R_SH_PSHL-relokering %d er uden for gyldigt interval -32..32" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%B(%A+0x%lx): kan ikke udsende \"fixup\" til \"%s\" i skrivebeskyttet sektion" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%B(%A+0x%lx): %s-relokering mod eksternt symbol \"%s\"" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%X%C: relokering til \"%s\" refererer et andet segment\n" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%C: advarsel: relokering til \"%s\" refererer et andet segment\n" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: \"%s\" tilgÃ¥s bÃ¥de som normalt symbol og FDPIC-symbol" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: \"%s\" tilgÃ¥s bÃ¥de som FDPIC-symbol og trÃ¥dlokalt symbol" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "%B: Relokering af funktionsdeskriptor med addend forskellig fra nul" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: lokal TLS-eksekveringskode kan ikke lænkes ind i delte objekter" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: oversat som 32-bitsobjekt og %s er 64-bit" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: oversat som 64-bitsobjekt og %s er 32-bit" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: objektstørrelsen stemmer ikke overens med den hos mÃ¥let %s" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: mødte dataetikettesymbol i inddata" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB passer ikke: en SHmedia-adresse (bit 0 == 1)" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA passer ikke: en SHcompact-adresse (bit 0 == 0)" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: GAS-fejl: uventet PTB-instruktion med R_SH_PT_16" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: fejl: ujusteret relokeringstype %d pÃ¥ %08x-relokering %08x\n" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: kunne ikke udskrive tilføjede .cranges-poster" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: kunne ikke udskrive sorterede cranges-poster" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: kompileret til et 64-bitssystem, men mÃ¥let er 32-bit" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: lænker little endian-filer med big endian-filer" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: overlay-sektion %A starter ikke pÃ¥ en cachelinje.\n" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: overlay-sektion %A er større end en cachelinje.\n" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: overlay-sektion %A er ikke i cacheomrÃ¥det.\n" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: overlay-sektionerne %A og %A starter ikke pÃ¥ samme adresse.\n" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "advarsel: kald til ikke-funktionssymbol %s defineret i %B" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) afviger fra analyse (%u)\n" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "%B mÃ¥ ikke definere %s" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "du har ikke lov til at definere %s i et script" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "%s i overlay-sektion" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "overløb ved overlay-stub-relokering" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "stubbe stemmer ikke overens med beregnet størrelse" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "advarsel: %s overlapper %s\n" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "advarsel: %s overstiger sektionsstørrelse\n" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v ikke fundet i funktionstabel\n" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): kald til ikke-kodesektion %B(%A), analyse ufuldstændig\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "Stak-analyse vil ignorere kaldet fra %s til %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " kald:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s er duplikeret i %s\n" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "%s duplikeret\n" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "beklager, men auto-overlay-scriptet understøtter ikke duplikerede objektfiler\n" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "ikke-overlay-størrelse af 0x%v plus den maksimale overlaystørrelse af 0x%v overstiger lokalt lager\n" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s overstiger overlay-størrelsen\n" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "Stakstørrelsen for rodknuder i funktionskaldsgrafen.\n" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Stakstørrelse til funktioner. Annotationer: '*' maks stak, 't' tail call\n" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "Maksimum pÃ¥krævet stak er 0x%v\n" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "fatal fejl ved oprettelse af .fixup" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s+0x%lx): uløselig %s-relokering mod symbol \"%s\"" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "%B: SB-relativ relokering, men __c6xabi_DSBT_BASE er ikke defineret" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "%B: relokeringstypen %d er ikke implementeret" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "farlig relokering" + +# ikke sikker pÃ¥ hvad det her betyder, sÃ¥ bruger mere direkte oversættelse end hvad der mÃ¥ske er nødvendigt +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "fejl: %B kræver mere stakjustering end %B præserverer" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "fejl: ukendt værdi for Tag_ABI_array_object_alignment i %B" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "error: ukendt værdi for Tag_ABI_array_object_align_expected i %B" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "fejl: %B kræver mere array-justering end %B præserverer" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "advarsel: %B og %B har forskellig størrelse af wchar_t" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "advarsel: forskel pÃ¥ om %B og %B er kompileret til DSBT" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "advarsel: %B og %B har forskellig positionsafhængighed af dataadressering" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "advarsel: %B og %B har forskellig positionsafhængighed af kodeadressering" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variabel \"%s\" kan ikke befinde sig i flere smÃ¥ dataomrÃ¥der" + +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variabel \"%s\" kan kun være i ét af de smÃ¥, tomme og bittesmÃ¥ dataomrÃ¥der" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variabel \"%s\" kan ikke være i bÃ¥de smÃ¥ og tomme dataomrÃ¥der samtidigt" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variabel \"%s\" kan ikke være i bÃ¥de smÃ¥ og bittesmÃ¥ dataomrÃ¥der samtidigt" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Variabel \"%s\" kan ikke være i bÃ¥de tomme og bittesmÃ¥ dataomrÃ¥der samtidigt" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "MISLYKKEDES med at finde tidligere HI16-relokering\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "kunne ikke lokalisere specielt lænkersymbol __gp" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "kunne ikke lokalisere specielt lænkersymbol __ep" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "kunne ikke lokalisere specielt lænkersymbol __ctbp" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: Arkitekturen passer ikke sammen med tidligere moduler" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "private flag = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "v850-arkitektur" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "v850e-arkitektur" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "v850e1-arkitektur" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "v850e2-arkitektur" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "v850e2v3-arkitektur" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr " [ikke-pic]" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr " [d-flydende tal]" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr " [g-flydende tal]" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: advarsel: GOT-addendum %ld til \"%s\" stemmer ikke overens med tidligere GOT-addendum %ld" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: advarsel: PLT-addendum %d til \"%s\" fra sektionen %s ignoreredes" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: advarsel: %s-relokering mod symbol \"%s\" fra sektionen %s" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: advarsel: %s-relokering til 0x%x fra sektionen %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "ikke-tomt addendum i @fptr-relokering" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): ugyldig egenskabstabel" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): relokeringsafsæt uden for gyldigt interval (størrelse=0x%x)" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "dynamisk relokering i skrivebeskyttet sektion" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "TLS-relokering er ugyldig uden dynamiske sektioner" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "intern inkonsistens i størrelsen af .got.loc-sektion" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: inkompatibel maskintype. Uddata er 0x%x. Inddata er 0x%x" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Forsøg pÃ¥ at konvertere L32R/CALLX til CALL mislykkedes" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): kunne ikke afkode instruktion; mulig konfigurationsmodstrid" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): kunne ikke afkode instruktion til XTENSA_ASM_SIMPLIFY-relokering; mulig konfigurationsmodstrid" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "ugyldig relokeringsadresse" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "overløb efter forenkling" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): uventet fiks til %s-relokering" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP-relokering fandt ingen ldah- og lda-instruktioner" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: .got-subsegment overskrider 64K (størrelse %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: gp-relativ relokering mod dynamisk symbol %s" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: pc-relativ relokering mod dynamisk symbol %s" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: ændring i gp: BRSGP %s" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: !samegp-relokering mod symbol uden .prologue: %s" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: uhÃ¥ndteret dynamisk relokering mod %s" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: pc-relativ relokering mod udefineret svagt symbol %s" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: dtp-relativ relokering mod dynamisk symbol %s" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: tp-relativ relokering mod dynamisk symbol %s" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "stubpost for %s kan ikke indlæse .plt, dp-afstand = %ld" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): kan ikke nÃ¥ %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Intern inkonsistensfejl for værdien for\n" +" lænkerallokeret globalt register: lænket: 0x%lx%08lx != forenklet: 0x%lx%08lx\n" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: base-plus-afstandsrelokering mod registersymbol: (ukendt) i %s" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: base-plus-afstandsrelokering mod registersymbol: %s i %s" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: registerrelokering mod ikke-registersymbol: (ukendt) i %s" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: registerrelokering mod ikke-registersymbol: %s i %s" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: LOCAL-direktivet er kun gyldigt med et register eller en absolutværdi" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: LOCAL-direktiv: Register $%ld er ikke et lokalt register. Første globale register er $%ld." + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Fejl: flere definitioner af \"%s\"; begyndelsen pÃ¥ %s er sat i en tidligere lænket fil\n" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "Registersektion har indhold\n" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Intern inkonsekvens: genstÃ¥ende %u != max %u.\n" +" Rapportér gerne denne fejl." + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: kompileret til et big endian-system, men mÃ¥let er little endian" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: kompileret til et little endian-system, men mÃ¥let er big endian" + +# lazy (i computersammenhæng) ~ først at gøre noget, nÃ¥r det er nødvendigt. Hvis programmøren skriver x = 2 + 2 men først bruger variablen x senere, vil udregningen 2+2 altsÃ¥ først ske senere. +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "kopiering af relokering mod \"%s\" kræver forsinket plt-lænkning; undgÃ¥ at sætte LD_BIND_NOW=1 eller opgradér gcc" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "dynreloc-fejloptælling for %B, sektion %A" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd er ikke et almindeligt array af opd-poster" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: uventet relokeringstype %u i .opd-sektion" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: udefineret symbol \"%s\" i .opd-sektion" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "%s defineret pÃ¥ fjernet toc-post" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "afsætoverløb for lang grenstub \"%s\"" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "kan ikke finde grenstub \"%s\"" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "lænketabelsfejl mod \"%s\"" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "kan ikke bygge grenstub \"%s\"" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "%B-sektionen %A overstiger stub-gruppestørrelsen" + +# ? +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"lænkerstubbe i %u gruppe%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): flere automatiske TOC'er understøttes ikke med dine crt-filer; genkompilér med -mminimal-toc eller opgradér gcc" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): \"sibling call\"-optimering til \"%s\" tillader ikke flere indholdsfortegnelser; genkompilér med -mminimal-toc eller -fno-optimize-sibling-calls eller gør \"%s\" ekstern" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: relokeringen %s understøttes ikke for symbol %s." + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: fejl: relokeringen %s er ikke et multiplum af %d" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: fejl: ujusteret relokeringstype %d pÃ¥ %08x relokering %08x\n" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Kun registrene %%g[2367] kan erklæres med STT_REGISTER" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "Register %%g%d bruges inkompatibelt: %s i %B, tidligere %s i %B" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Symbolet \"%s\" har forskellige typer: REGISTER i %B, tidligere %s i %B" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Symbolet \"%s\" har forskellige typer: %s i %B, tidligere REGISTER i %B" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: lænker UltraSPARC-specifik med HAL-specifik kode" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: \"%s\" tilgÃ¥s bÃ¥de som normalt og trÃ¥dlokalt symbol" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: relokering %s mod STT_GNU_IFUNC-symbol \"%s\" har addend forskellig fra nul: %d" + +#: elf64-x86-64.c:3073 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: relokeringen R_X86_64_GOTOFF64 mod beskyttet funktion \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "; genkompilér med -fPIC" + +#: elf64-x86-64.c:3189 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: relokeringen %s mod %s \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes%s" + +#: elf64-x86-64.c:3191 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: relokeringen %s mod udefineret %s \"%s\" kan ikke bruges nÃ¥r et delt objekt oprettes%s" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "advarsel: %s har et beskadiget strengtabelindeks - ignorerer" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: versionsantal (%ld) stemmer ikke med symbolantal (%ld)" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): relokering %d har ugyligt symbolindeks %ld" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Advarsel: %B er afkortet: forventede kernefilstørrelse >= %lu, fandt: %lu." + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-definition i %B sektion %A stemmer ikke med ikke-TLS-definition i %B sektion %A" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: TLS-reference i %B stemmer ikke med ikke-TLS-reference i %B" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: TLS-definition i %B sektion %A stemmer ikke med ikke-TLS-reference i %B" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-reference i %B stemmer ikke med ikke-TLS-definition i %B sektion %A" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: uventet omdefinition af indirekte versionstildelt symbol \"%s\"" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "%B: versionsknude ikke fundet for symbolet %s" + +#: elflink.c:2166 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: fejlagtig relokeringssymbolindeks (0x%lx >= 0x%lx) for afsæt 0x%lx i sektionen \"%A\"" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: symboltabellen (0x%lx) forskelligt fra nul for afsæt 0x%lx i sektion \"%s\" mens objektfilen ikke har nogen symboltabelc" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: relokeringsstørrelsen stemmer ikke overens i %B-sektionen %A" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "advarsel: typen og størrelsen pÃ¥ dynamisk symbol \"%s\" er ikke defineret" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: alternativ ELF-maskinkode fundet (%d) i %B; forventer %d\n" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: ugyldig version %u (max %d)" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: ugyldig krævet version %d" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Advarsel: justering %u af fælles symbol \"%s\" i %B er større end justeringen (%u) af dets sektion %A" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Advarsel: justeringen %u pÃ¥ symbolet \"%s\" i %B er mindre end %u i %B" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Advarsel: størrelsen pÃ¥ symbol \"%s\" ændredes fra %lu i %B til %lu i %B" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "%B: udefineret reference til symbol \"%s\"" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "bemærk: \"%s\" er defineret i DSO %B, sÃ¥ prøv at tilføje den til lænker-kommandolinjen" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: udefineret version: %s" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: .preinit_array-sektionen er ikke tilladt i DSO" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "udefineret %s-reference i komplekst symbol: %s" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "ukendt operator \"%c\" i komplekst symbol" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Kan ikke sortere relokeringer - de har flere forskellige størrelser" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Kan ikke sortere relokeringer - de har ukendt størrelse" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "Ikke nok hukommelse til at sortere relokeringer" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: For mange sektioner: %d (>= %d)" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: %s-symbol \"%s\" i %B refereres af DSO" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: kunne ikke finde uddatasektionen %A for inddatasektionen %A" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: %s-symbolet \"%s\" er udefineret" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "fejl: %B indeholder en relokering (0x%s) til sektionen %A, som refererer et ikke-eksisterende global symbol" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X\"%s\" refereret i sektion \"%A\" af %B: defineret i forkastet sektion \"%A\" af %B\n" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A har bÃ¥de ordnede [\"%A\" i %B] og uordnede [\"%A\" i %B] sektioner" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A har bÃ¥de ordnede og uordnede sektioner" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: kunne ikke finde uddatasektionen %s" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "advarsel: %s-sektionen har nulstørrelse" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: advarsel: opretter en DT_TEXTREL i et delt objekt.\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: kan ikke læse symboler: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Fjerner ubrugt sektion \"%s\" i filen \"%B\"" + +# gc-sections- eller gc-sektions-? +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "Advarsel: gc-sections-tilvalg ignoreret" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: ignorerer gentaget sektion \"%A\"" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: gentaget sektion \"%A\" har forskellig størrelse" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: advarsel: kunne ikke læse indholdet af sektionen \"%A\"" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: advarsel: gentaget sektion \"%A\" har forskelligt indhold" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "statisk procedure (intet navn)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "%B: %A+0x%lx: Direkte hop mellem ISA-tilstande er ikke tilladt; overvej at genkompilere med interlinking slÃ¥et til." + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Advarsel: Ugyldig \"%s\"-tilvalgsstørrelse %u mindre end dens header" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Advarsel: Kan ikke bestemme mÃ¥lfunktionen for stubsektionen \"%s\"" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Fejlagtig relokering for sektion %s opdaget" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: GOT-relokering ved 0x%lx forventes ikke i eksekveringsfiler" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL16-relokering ved 0x%lx er ikke mod globalt symbol" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "udynamiske relokeringer refererer til dynamisk symbol %s" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Kan ikke finde matchende LO16-relokering mod \"%s\" for %s ved 0x%lx i sektion \"%A\"" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "sektionen small-data overstiger 6KB; gør størrelsesgrænsen for small-data mindre (se tilvalget -G)" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: ugyldigt sektionsnavn \"%s\"" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Advarsel: %B bruger -msingle-float, %B bruger -mdouble-float" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Advarsel: %B bruger -msingle-float, %B bruger -mips32r2 -mfp64" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Advarsel: %B bruger -mdouble-float, %B bruger -mips32r2 -mfp64" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: endian-hed er ikke kompatibel den valgte emulerings endian-hed" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI er ikke kompatibel med den valgte emulerings ABI" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: advarsel: lænker abicalls-filer med ikke-abicalls-filer" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: lænker 32 bit-kode med 64 bit-kode" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: lænker %s-modul med tidligere %s-moduler" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: ABI passer ikke: lænker %s-modul med tidligere %s-moduler" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [ukendt abi]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [intet abi sat]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [ukendt ISA]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [ikke 32-bittilstand]" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "ugyldig relokeringstype %d" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Uddatafilen kræver delt bibliotek \"%s\"\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Uddatafilen kræver delt bibliotek \"%s.so.%s\"\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Symbol %s er ikke defineret for rettelser\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "Advarsel: antal rettelser stemmer ikke\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: strengen er for lang (%d tegn, max 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: ukendt symbol \"%s\" flag 0x%x" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: ikke-implementeret ATI-post %u for symbol %u" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: uventet ATN-type %d i ekstern del" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "%B: uventet type efter ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: uventet tegn \"%s\" i heksadecimal Intel-fil" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: fejlagtig kontrolsum i heksadecimal Intel-fil (forventede %u, fandt %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: fejlagtig længde pÃ¥ post for udvidet adresse i heksadecimal Intel-fil" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: fejlagtig længde pÃ¥ udvidet startadresse i heksadecimal Intel-fil" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: fejlagtig længde pÃ¥ post for udvidet lineær adresse i heksadecimal Intel-fil" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: fejlagtig længde pÃ¥ udvidet lineær startadresse i heksadecimal Intel-fil" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: ukendt ihex-type %u i heksadecimal Intel-fil" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: intern fejl i ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: fejlagtig sektionslængde i ihex_read_sektion" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: adressen 0x%s er uden for intervallet for heksadecimal Intel-fil" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "%B: kan ikke hente dekomprimeret sektion %A" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Forældet %s kaldt ved %s linje %d i %s\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Forældet %s kaldt\n" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: indirekte symbol \"%s\" til \"%s\" er en løkke" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Forsøg at lave en relokérbar lænke med %s-inddata og %s-uddata" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: advarsel: ignorerer gentaget sektion \"%A\"\n" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: advarsel: gentaget sektion \"%A\" har forskellig længde\n" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "Mach-O-header:\n" + +# eller skal det være magisk tal? +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr " magi : %08lx\n" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " cputype : %08lx (%s)\n" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " cpusubtype: %08lx\n" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " filtype : %08lx (%s)\n" + +# ? +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr " nkmd'er : %08lx (%lu)\n" + +# kan ikke sÃ¥ godt gøre de her konsistente +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " sizeofcmds: %08lx\n" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr " flag : %08lx (" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr " reserveret: %08x\n" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "Segmenter og sektioner:\n" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr " #: Segmentnavn Sektionsnavn Adresse\n" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: tilgang ud over slutningen pÃ¥ sammenflettet sektion (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Ingen kerne til at allokere sektionsnavn %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Ingen kerne til at allokere et %d byte langt symbol\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: ugyldig mmo-fil: initieringsværdi for $255 er ikke \"Main\"\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: bred tegn-sekvens som ikke understøttes 0x%02X 0x%02X efter symbolnavnet som begynder med \"%s\"\n" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: ugyldig mmo-fil: lopkode \"%d\" understøttes ikke\n" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: ugyldig mmo-fil: forventede YZ = 1 fik YZ = %d for lop_quote\n" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: ugyldig mmo-fil: forventede z = 1 eller z = 2, fik z = %d for lop_loc\n" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: ugyldig mmo-fil: forventede z = 1 eller z = 2, fik z = %d for lop_fixo\n" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: ugyldig mmo-fil: forventede y = 0, fik y = %d for lop_fixrx\n" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: ugyldig mmo-fil: forventede z = 16 eller z = 24, fik z = %d for lop_fixr\n" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: ugyldig mmo-fil: indledende byte i operandord skal være 0 eller 1, fik %d for lop_fixrx\n" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: kan ikke allokere filnavn for fil nummer %d, %d byte\n" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: ugyldig mmo-fil: fil nummer %d \"%s\", var allerede angivet som \"%s\"\n" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: ugyldig mmo-fil: filnavnet for nummer %d blev ikke angivet inden brug\n" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: ugyldig mmo-fil: felter y og z i lop_stab er ikke-tomme, y: %d, z: %d\n" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: ugyldig mmo-fil: lop_end er ikke sidste objekt i fil\n" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: ugyldig mmo-fil: YZ i lop_end (%ld) er ikke lig med antal af tetraer til den foregÃ¥ende lop_stab (%ld)\n" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: ugyldig symboltabel: dubletsymbol \"%s\"\n" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Fejlagtig symboldefinition: \"Main\" er sat til %s i stedet for startadressen %s\n" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: advarsel: symboltabellen er for stor for mmo, større end 65535 32-bit ord: %d. Kun \"Main\" vil blive sendt.\n" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: intern fejl, symboltabellen ændrede størrelse fra %d til %d ord\n" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: intern fejl, den interne registersektion %s havde indhold\n" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: ingen initierede registre; sektionslængde 0\n" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: for mange initierede registre; sektionslængde %ld\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: ugyldig startadresse for initierede registre med længden %ld: 0x%lx%08lx\n" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: kan ikke repræsentere sektionen \"%s\" i oasys" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "UhÃ¥ndteret sektionstype %d for OSF/1-hukommelsesfil\n" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: \"ld -r\" understøttes ikke med PE MIPS-objekter\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "%B: uimplementeret %s\n" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "%B: hop for langt bort\n" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: fejlagtigt par/reflo efter refhi\n" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "advarsel: størrelsen pÃ¥ .pdata-sektionen (%ld) er ikke et multiplum af %d\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Funktionstabellen (tolket indhold fra .pdata-sektionen)\n" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "vma:\t\t\tStartadresse\t Slutadresse\t Tilbagespolingsdata\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: UhÃ¥ndteret importtype; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: Ukendt importtype; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: Ukendt importnavnstype; %x" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: Ukendt maskintype (0x%x) i Import Library Format-arkiv" + +#: peicode.h:1174 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: Genkendt men uhÃ¥ndteret maskintype (0x%x) i Import Library Format-arkiv" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: størrelsesfeltet er nul i Import Library Format-header" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: streng ikke nultermineret i ILF-objektfil." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot-hoved:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Startafstand = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Længde = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Flagfelt = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Partitionsnavn = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Start pÃ¥ partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Slut pÃ¥ partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Sektor for partition[%d] = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Længde pÃ¥ partition[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Ekstraheader til kørsel\n" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers er ikke implementeret" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: Uventet tegn \"%s\" i S-post-fil\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: DÃ¥rlig tjeksum i S-post-fil\n" + +# Hvad er stabs? +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Stabs-post har ugyldigt strengindeks." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr ".stab-relokering som ikke understøttes" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "Ukendt EGSD-undertype %d" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Stakken giver overløb (%d) i _bfd_vms_push" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Stakken giver underløb i _bfd_vms_pop" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "ukendt ETIR-kommando %d" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "fejlagtigt sektionsindeks i %s" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "STA-kommando %s understøttes ikke" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "%s: understøttes ikke" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "%s: ikke implementeret" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "ugyldig brug af %s med kontekster" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "reserveret kommando %d" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "Objektmodulet IKKE fejlfri!\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Symbol %s erstattet med %s\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC uden relokeringer i sektion %s" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "Størrelsesfejl i sektion %s" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Uægte ALPHA_R_BSD-relokering" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "UhÃ¥ndteret relokering %s" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "ukendt kildekommando %d" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "DST__K_SET_LINUM_INCR er ikke implementeret" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "DST__K_SET_LINUM_INCR_W er ikke implementeret" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "DST__K_RESET_LINUM_INCR ikke implementeret" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "DST__K_BEG_STMT_MODE er ikke implementeret" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "DST__K_END_STMT_MODE er ikke implementeret" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "DST__K_SET_PC er ikke implementeret" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "DST__K_SET_PC_W er ikke implementeret" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "DST__K_SET_PC_L er ikke implementeret" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "DST__K_SET_STMTNUM er ikke implementeret" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "ukendt linjekommando %d" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Ukendt relokering %s + %s" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "Ukendt relokering %s" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "Fejlagtigt sektionsindeks i ETIR" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "Ugyldigt symbol i kommando %s" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr " EMH %u (længde=%u): " + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "Modulheader\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr " strukturniveau : %u\n" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr " maks post-str: %u\n" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr " modulnavn : %.*s\n" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr " modulversion : %.*s\n" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr " kompileringsdag: %.17s\n" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "Navn pÃ¥ sprogprocessor\n" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr " sprognavn: %.*s\n" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "Kildefilheader\n" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr " fil: %.*s\n" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "Titeltekstheader\n" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr " titel: %.*s\n" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "Ophavsretsheader\n" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr " ophavsret: %.*s\n" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "uhÃ¥ndteret emh-undertype %u\n" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr " EEOM (længde=%u):\n" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr " antal cond-lænkningspar: %u\n" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr " fuldførelseskode: %u\n" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr " overførselsadresseflag: 0x%02x\n" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr " overførselsadresse-psect: %u\n" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr " overførselsadresse : 0x%08x\n" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr " WEAK" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr " DEF" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr " UNI" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr " REL" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr " COMM" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr " VECEP" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr " NORM" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr " QVAL" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr " PIC" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr " LIB" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr " OVR" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr " GBL" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr " SHR" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr " EXE" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr " RD" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr " WRT" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr " VEC" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr " NOMOD" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr " COM" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr " 64B" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr " EGSD (længde=%u):\n" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr " EGSD-post %2u (type: %u, længde: %u): " + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "PSC - Programsektionsdefinition\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr " justering : 2**%u\n" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr " flag : 0x%04x" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr " allok (lgd): %u (0x%08x)\n" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr " navn : %.*s\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "SPSC - Shared Image Program-sektionsdefinition\n" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr " allok (længde): %u (0x%08x)\n" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr " image-afsæt : 0x%08x\n" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr " symvec-afsæt : 0x%08x\n" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr " navn : %.*s\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "SYM - Global symboldefinition\n" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr " flag : 0x%04x" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr " psect-afsæt : 0x%08x\n" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr " kodeadresse : 0x%08x\n" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr " psect-indeks for indgangspunkt : %u\n" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr " psect-indeks : %u\n" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr " navn : %.*s\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "SYM - Global symbolreference\n" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "IDC - identitetskonsistenstjek\n" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr " flag : 0x%08x" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr " id-match : %x\n" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr " fejlalvorlighed: %x\n" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr " entitetsnavn : %.*s\n" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr " objektnavn : %.*s\n" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr " binær id : 0x%08x\n" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr " ascii-id : %.*s\n" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "SYMG - Universel symboldefinition\n" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr " symbolvektorafsæt : 0x%08x\n" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr " indgangspunkt: 0x%08x\n" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr " proc-beskr : 0x%08x\n" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr " psect-indeks: %u\n" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "SYMV - vektoriseret symboldefinition\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr " vektor : 0x%08x\n" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr " psect-afsæt : %u\n" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "SYMM - Global symboldefinition med version\n" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr " versionsmaske: 0x%08x\n" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "uhÃ¥ndteret egsd-post-type %u\n" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr " lænkningsindeks: %u, erstatnings-insn: 0x%08x\n" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr " psect-idx 1: %u, afsæt 1: 0x%08x %08x\n" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr " psect-idx 2: %u, afsæt 2: 0x%08x %08x\n" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr " psect-idx 3: %u, afsæt 3: 0x%08x %08x\n" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr " globalt navn: %.*s\n" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr " %s (længde=%u+%u):\n" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr " (type: %3u, størrelse: 4+%3u): " + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "STA_GBL (stak-global) %.*s\n" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "STA_LW (stak-longword) 0x%08x\n" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "STA_QW (stak-quadword) 0x%08x %08x\n" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "STA_PQ (stak-psect base + afsæt)\n" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr " psect: %u, afsæt: 0x%08x %08x\n" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "STA_LI (stak-literal)\n" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "STA_MOD (stakmodul)\n" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "STA_CKARG (argument til sammenligningsprocedure)\n" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "STO_B (gem byte)\n" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "STO_W (gem word)\n" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "STO_LW (gem longword)\n" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "STO_QW (gem quadword)\n" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "STO_IMMR (gem omgÃ¥ende gentagelse) %u byte\n" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "STO_GBL (gem global) %.*s\n" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "STO_CA (gem kodeadresse) %.*s\n" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "STO_RB (gem relativ gren)\n" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "STO_AB (gem absolut gren)\n" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "STO_OFF (gem afsæt til psect)\n" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "STO_IMM (gem omgÃ¥ende) %u byte\n" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "STO_GBL_LW (gem globalt longword) %.*s\n" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "STO_OFF (gem LP med proceduresignatur)\n" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "STO_BR_GBL (gem gren globalt) *todo*\n" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "STO_BR_PS (gem gren-psect + afsæt) *todo*\n" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "OPR_NOP (ingen operation)\n" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "OPR_ADD (læg sammen)\n" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "OPR_SUB (træk fra)\n" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "OPR_MUL (multiplicér)\n" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "OPR_DIV (dividér)\n" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "OPR_AND (logisk og)\n" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "OPR_IOR (logisk inklusiv eller)\n" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "OPR_EOR (logisk eksklusiv eller)\n" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "OPR_NEG (negation)\n" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "OPR_COM (komplement)\n" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "OPR_INSV (indsæt felt)\n" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "OPR_ASH (aritmetisk skift)\n" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "OPR_USH (skift uden fortegn)\n" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "OPR_ROT (rotér)\n" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "OPR_SEL (vælg)\n" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "OPR_REDEF (omdefinér symbol til nuværende placering)\n" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "OPR_REDEF (definér en literal)\n" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "STC_LP (gem cond-lænkningspar)\n" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "STC_LP_PSB (gem cond-lænkningspar + signatur)\n" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr " lænkningsindeks: %u, procedure: %.*s\n" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr " signatur: %.*s\n" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "STC_GBL (gem cond globalt)\n" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr " lænkningsindeks: %u, global: %.*s\n" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "STC_GCA (gem cond-kodeadresse)\n" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr " lænkningsindeks: %u, procedurenavn: %.*s\n" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "STC_PS (gem cond-psect + afsæt)\n" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr " lænkningsindeks: %u, psect: %u, afsæt: 0x%08x %08x\n" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "STC_NOP_GBL (gem cond NOP pÃ¥ global adresse)\n" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "STC_NOP_PS (gem cond NOP pÃ¥ psect + afsæt)\n" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "STC_BSR_GBL (gem cond BSR pÃ¥ global adresse)\n" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "STC_BSR_PS (gem cond BSR pÃ¥ psect + afsæt)\n" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "STC_LDA_GBL (gem cond LDA pÃ¥ global adresse)\n" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "STC_LDA_PS (gem cond LDA pÃ¥ psect + afsæt)\n" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "STC_BOH_GBL (gem cond BOH pÃ¥ global adresse)\n" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "STC_BOH_PS (gem cond BOH pÃ¥ psect + afsæt)\n" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "STC_NBH_GBL (gem cond eller hint pÃ¥ global adresse)\n" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "STC_NBH_PS (gem cond eller hint pÃ¥ psect + afsæt)\n" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "CTL_SETRB (sæt relokeringsbase)\n" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "CTL_AUGRB (sammensæt (augment) relokeringsbase) %u\n" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "CTL_DFLOC (defineÅ• placering)\n" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "CTL_STLOC (indstil placering)\n" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "CTL_STKDL (stakdefineret placering)\n" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "*uhÃ¥ndteret*\n" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "kan ikke læse GST-post-længde\n" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "kan ikke finde EMH i første GST-post\n" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "kan ikke læse GST-post-header\n" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr " beskadiget GST\n" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "kan ikke læse GST-post\n" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr " uhÃ¥ndteret EOBJ-post-type %u\n" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr " antal bit: %u, basisadresse: 0x%08x\n" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr " bitmap: 0x%08x (antal: %u):\n" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr " %08x" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr " aftryk %u (%u elementer)\n" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr " afsæt: 0x%08x, værdi: 0x%08x\n" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr " aftryk %u (%u elementer), afsæt:\n" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr " 0x%08x" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "64 bit *uhÃ¥ndteret*\n" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "klasse: %u, dtype: %u, længde: %u, pointer: 0x%08x\n" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "usammenhængende array af %s\n" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "dimct: %u, aflags: 0x%02x, cifre: %u, skala: %u\n" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "arsize: %u, a0: 0x%08x\n" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "Trinstørrelser:\n" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "[%u]: %u\n" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "Grænser:\n" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "[%u]: Nedre: %u, øvre: %u\n" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "ujusteret bit-streng af %s\n" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "base: %u, pos: %u\n" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "vflags: 0x%02x, værdi: 0x%08x " + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "(ingen værdi)\n" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "(ikke aktiv)\n" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "(ikke tildelt)\n" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "(deskriptor)\n" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "(afsluttende værdi)\n" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "(værdi-spec følger)\n" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "(ved bitafsæt %u)\n" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "(reg: %u, disp: %u, indir: %u, type: " + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "literal" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "adresse" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "beskr" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "reg" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "Fejlsøgningssymboltabel:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "kan ikke læse DST-header\n" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr " type: %3u, længde: %3u (pÃ¥ 0x%08x): " + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "kan ikke læse DST-symbol\n" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "standarddata : %s\n" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr " navn: %.*s\n" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "modbeg\n" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr " flag: %d, sprog: %u, hoved: %u, under: %u\n" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr " modulnavn : %.*s\n" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr " kompiler : %.*s\n" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "modend\n" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "rtnbeg\n" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr " flag: %u, adresse: 0x%08x, pd-adresse: 0x%08x\n" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr " rutinenavn: %.*s\n" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "rtnend: størrelse 0x%08x\n" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "prolog: bkpt-adresse 0x%08x\n" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "epilog: flag: %u, antal: %u\n" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "blkbeg: adresse: 0x%08x, navn: %.*s\n" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "blkend: størrelse: 0x%08x\n" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "typspec (længde: %u)\n" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "septyp, navn: %.*s\n" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "recbeg: navn: %.*s\n" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "recend\n" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "enumbeg, længde: %u, navn: %.*s\n" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "enumelt, navn: %.*s\n" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "enumend\n" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "usammenhængende interval (nbr: %u)\n" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr " adresse: 0x%08x, størrelse: %u\n" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "linjenummer (længde: %u)\n" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "delta_pc_w %u\n" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "incr_linum(b): +%u\n" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "incr_linum_w: +%u\n" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "incr_linum_l: +%u\n" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "set_line_num(w) %u\n" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "set_line_num_b %u\n" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "set_line_num_l %u\n" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "set_abs_pc: 0x%08x\n" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "delta_pc_l: +0x%08x\n" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "term(b): 0x%02x" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "term_w: 0x%04x" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "delta pc +%-4d" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr " pc: 0x%08x linje: %5u\n" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *uhÃ¥ndteret* kommando %u\n" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "kilde (længde: %u)\n" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr " declfile: længde: %u, flag: %u, fil-id: %u\n" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr " filnavn : %.*s\n" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr " setfile %u\n" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr " setrec %u\n" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr " setlnum %u\n" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr " deflines %u\n" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr " formfeed\n" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *uhÃ¥ndteret* kommando %u\n" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "*uhÃ¥ndteret dst-type %u\n" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "kan ikke læse EIHD\n" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "EIHD: (størrelse: %u, bloktal: %u)\n" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr " hovednr: %u, undernr: %u\n" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "eksekverbar fil" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "lænkbart aftryk" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr " aftrykstype: %u (%s)" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "native" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "CLI" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr ", undertype: %u (%s)\n" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr " afsæt: isd: %u, aktiv: %u, symdbg: %u, imgid: %u, patch: %u\n" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr " fixup info-rva: " + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr ", symbolvektor-rva: " + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" +"\n" +" versions-arrayafsæt: %u\n" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr " img-I/O-tal: %u, antal kanaler: %u, req pri: %08x%08x\n" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr " lænkerflag: %08x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr " ident: 0x%08x, sysver: 0x%08x, match-ktrl: %u, symvect_size: %u\n" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr " BPAGE: %u" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr ", ext-fixup-afsæt: %u, no_opt psect slÃ¥et fra: %u" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr ", alias: %u\n" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "arrayinformation om systemversion:\n" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "kan ikke læse EIHVN-header\n" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "kan ikke læse EIHVN-version\n" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr " %02u " + +# ? +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "BASE_IMAGE " + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "MEMORY_MANAGEMENT" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "IO " + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "FILES_VOLUMES " + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "PROCESS_SCHED " + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "SYSGEN " + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "CLUSTERS_LOCKMGR " + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "LOGICAL_NAMES " + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "SECURITY " + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "IMAGE_ACTIVATOR " + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "NETWORKS " + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "COUNTERS " + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "STABLE " + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "MISC " + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "CPU " + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "VOLATILE " + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "SHELL " + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "POSIX " + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "MULTI_PROCESSING " + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "GALAXY " + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "*ukendt* " + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr ": %u.%u\n" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "kan ikke læse EIHA\n" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "Aftryksaktivering: (størrelse=%u)\n" + +# Den her og de nedenstÃ¥ende skal tilsyneladende passe sammen med placering af kolon +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr " Første adresse: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr " Anden adresse : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr " Tredje adresse: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr " Fjerde adresse: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr " Delt aftryk : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "kan ikke læse EIHI\n" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "Aftryksidentifikation: (hoved: %u, under: %u)\n" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr " aftryksnavn : %.*s\n" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr " lænketidspunkt : %s\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr " aftryks-id : %.*s\n" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr " lænker-id : %.*s\n" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr " aftryks bygge-id : %.*s\n" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "kan ikke læse EIHS\n" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "Aftrykssymbol- og fejlsøgningstabel: (hoved: %u, under: %u)\n" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr " symboltabel til fejlsøgning : vbn: %u, størrelse: %u (0x%x)\n" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr " global symboltabel: vbn: %u, poster: %u\n" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr " fejlsøgningsmodultabel : vbn: %u, størrelse: %u\n" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "kan ikke læse EISD\n" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "Aftrykssektionsdeskriptor: (hoved: %u, under: %u, størrelse: %u, afsæt: %u)\n" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr " sektion: base: 0x%08x%08x size: 0x%08x\n" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr " flag: 0x%04x" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr " vbn: %u, pfc: %u, matchktl: %u type: %u (" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "NORMAL" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "SHRFXD" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "PRVFXD" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "SHRPIC" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "PRVPIC" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "USRSTACK" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr " ident: 0x%08x, navn: %.*s\n" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "kan ikke læse DMT\n" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "Fejlsøgningsmodultabel:\n" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "kan ikke læse DMT-header\n" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr " modulafsæt: 0x%08x, størrelse: 0x%08x, (%u psect'er)\n" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "kan ikke læse DMT-psect\n" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr " psect-start: 0x%08x, længde: %u\n" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "kan ikke læse DST\n" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "kan ikke læse GST\n" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "Global symboltabel:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "Fixup til aftryksaktivator: (hoved: %u, under: %u)\n" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr " iaflink : 0x%08x %08x\n" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr " fixuplnk: 0x%08x %08x\n" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr " størrelse: %u\n" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr " flag: 0x%08x\n" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr " qrelfixoff: %5u, lrelfixoff: %5u\n" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr " qdotadroff: %5u, ldotadroff: %5u\n" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr " codeadroff: %5u, lpfixoff : %5u\n" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr " chgprtoff : %5u\n" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr " shlstoff : %5u, shrimgcnt : %5u\n" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr " shlextra : %5u, permctx : %5u\n" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr " base_va : 0x%08x\n" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr " lppsbfixoff: %5u\n" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr " Delelige aftryk:\n" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr " %u: størrelse: %u, flag: 0x%02x, navn: %.*s\n" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr " fixup'er til quad-word-relokeringer:\n" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr " fixup'er til long-word-relokeringer:\n" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr " fixup'er til quad-word .address-referencer:\n" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr " fixup'er til long-word .address-referencer:\n" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr " Fixup'er til kodeadressereferencer:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr " Reference-fixup'er til lænkningspar:\n" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr " Ændringsbeskyttelse (%u elementer):\n" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr " base: 0x%08x %08x, størrelse: 0x%08x, beskyttelse: 0x%08x " + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "%P: relokérbar lænke understøttes ikke\n" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "%P: flere indgangspunkter: i modulerne %B og %B\n" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "kunne ikke Ã¥bne delt aftryk \"%s\" fra \"%s\"" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted kaldt med nul byte" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted kaldt med for mange byte" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF delt objekt nÃ¥r ikke XCOFF-uddata produceres" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: dynamisk objekt uden nogen .loader-sektion" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: \"%s\" har linjenumre, men ingen omsluttende sektion" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: klasse %d-symbol \"%s\" har ingen aux-poster" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: symbol \"%s\" har ukendt csect-type %d" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: fejlagtigt XTY_ER-symbol \"%s\": klasse %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: XMC_TC0-symbol \"%s\" er klasse %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect \"%s\" er ikke i omsluttende sektion" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: fejlagtigt placeret XTY_LD \"%s\"" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: relokeringen %s:%d er ikke i csect" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: intet sÃ¥dant symbol" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "advarsel: forsøg pÃ¥ at eksportere udefineret symbol \"%s\"" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "fejl: udefineret symbol __rtinit" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: indlæserrelokering i ukendt sektion \"%s\"" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: \"%s\" i indlæserrelokering, men ikke indlæsersym" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: indlæserrelokering i skrivebeskyttet sektion %A" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "TOC giver overløb: 0x%lx > 0x10000; prøv -mminimal-toc ved oversættelse" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Kan ikke forenkle br ved 0x%lx i sektionen \"%A\". Brug venligst brl eller indirekte gren." + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "@pltoff-relokering mod lokalt symbol" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: kort datasegment løb over (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp dækker ikke kort datasegment" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: ikke-pic-kode med imm-relokering mod dynamisk symbol \"%s\"" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: @gprel-relokering mod dynamisk symbol %s" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: lænker ikke-pic-kode i en positionsuafhængig eksekverbar fil" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: @intern gren til dynamisk symbol %s" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: spekulations-fixup til dynamisk symbol %s" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: @pcrel-relokering mod dynamisk symbol %s" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "relokeringen understøttes ikke" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: manglende TLS-sektion til relokering %s mod \"%s\" ved 0x%lx i sektionen \"%A\"." + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: Kan ikke forenkle br (%s) til \"%s\" pÃ¥ 0x%lx i sektionen \"%A\" med størrelsen 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: lænker fang-ved-NULL-dereference med ikkefangende filer" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: lænker big-endian-filer med little endian-filer" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: lænker 64 bit-filer med 32 bit-filer" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: lænker konstant-gp-filer med ikke-konstant-gp-filer" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: lænker auto-pic-filer med ikke-auto-pic-filer" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: linjenummer giver overløb: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Eksportkatalog [.edata (eller hvor vi fandt det)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Importkatalog [dele af .idata]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "Resursekatalog [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "Undtagelseskatalog [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "Sikkerhedskatalog" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "Baserelokeringskatalog [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "Fejlsøgningskatalog" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "Beskrivelseskatalog" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "Specialkatalog" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "TrÃ¥dlagringskatalog [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "Indlæsningskonfigurationskatalog" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "Katalog over bundne importer" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "Importadressetabelkatalog" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "Katalog over forskinkede importer" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "CLR-runtime-header" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "Reserveret" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Der findes en importtabel, men sektionen som indeholder den kunne ikke findes\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Der findes en importtabel i %s pÃ¥ 0x%lx\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Funktionsidentifikatorer fundet pÃ¥ startadressen: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tkodebase %08lx toc (indlæseligt/reelt) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Ingen reldata-sektion! Funktionsidentifikatorer afkodedes ikke.\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Importtabellerne (tolket indhold i %s-sektion)\n" + +# Hvad er thunk? +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Tips- Tids- Fremad- DLL- Første\n" +" tabel stempel kæde navn thunk\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL-navn: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Tips/Ordn Medlemsnavn Bundet til\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Der findes en første thunk, men sektionen som indeholder den kunne ikke findes\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Der findes en eksporttabel, men sektionen som indeholder den kunne ikke findes\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Der findes en eksporttabel i %s, men den passer ikke ind i den pÃ¥gældende sektion\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Der findes en eksporttabel i %s ved 0x%lx\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Eksporttabellerne (tolket indhold i %s-sektion)\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Eksportflag \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Tids-/datostempel \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Større/mindre \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Navn \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Ordningsbase \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "Tal i:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tEksportadressetabel \t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Navnepeger/Ordningstal]-tabel\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "Tabeladresser\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tEksportadressetabel \t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tNavnepegertabel \t\t" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tOrdningstalstabel \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Eksportadressetabel -- Ordningsbase %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "Videresender-RVA" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "Eksport-RVA" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Ordningstals-/Navnepeger-]tabel\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Advarsel, størrelsen pÃ¥ .pdata-sektionen (%ld) er ikke en multipel af %d\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tStartadresse Slutadresse Tilbagespolings-information\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tStart- Slut- EH- EH- Prologsluts- Undtagelses-\n" +" \t\tadresse adresse hÃ¥ndterer data adresse maske\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " Registergemnings millikode" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " Registergenskabnings millikode" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " Klisterkodesekvens" + +# Et bogstav for meget i Undtagelse og HÃ¥ndtering, mon ikke det gÃ¥r? +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tStart Prolog Funktion Flag Undtagelse EH\n" +" \t\tAdresse Længde Længde 32b exc HÃ¥ndtering Data\n" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"PE-filbaserelokeringer (tolket indhold i .reloc-sektionen)\n" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Virtuel adresse: %08lx OmrÃ¥desstørrelse %ld (0x%lx) Antal rettelser %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\trelokering %4d afstand %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Karakteristik 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: kan ikke udfylde DataDictionary[1] fordi .idata$2 mangler" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: kan ikke udfylde DataDictionary[1] fordi .idata$4 mangler" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: kan ikke udfylde DataDictionary[12] fordi .idata$5 mangler" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: kan ikke udfylde DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)], da .idata$6 mangler" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "%B: kan ikke udfylde DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)], da .idata$6 mangler" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: kan ikke udfylde DataDictionary[9], da __tls_used mangler" + +# src/menus.c:341 +#~ msgid "Missing IHCONST" +#~ msgstr "IHCONST mangler" + +# src/menus.c:341 +#~ msgid "Missing IHIHALF" +#~ msgstr "IHIHALF mangler" + +#~ msgid "missing IHCONST reloc" +#~ msgstr "IHCONST-relokering mangler" + +#~ msgid "missing IHIHALF reloc" +#~ msgstr "IHIHALF-relokering mangler" + +#~ msgid " first occurrence: %s: arm call to thumb" +#~ msgstr " første forekomst: %s: arm-kald til thumb" + +#~ msgid " first occurrence: %s: thumb call to arm" +#~ msgstr " første forekomst: %s: thumb-kald til arm" + +#~ msgid " consider relinking with --support-old-code enabled" +#~ msgstr " overvej omlænkning med --support-old-code aktiveret" + +#~ msgid "reloc against unsupported section" +#~ msgstr "relokering mod sektion som ikke understøttes" + +#~ msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +#~ msgstr "Dwarf-fejl: DW_FORM_strp-afstanden (%lu) større end eller lig med størrelsen pÃ¥ .debug_str (%lu)." + +#~ msgid "Dwarf Error: Can't find .debug_abbrev section." +#~ msgstr "Dwarf-fejl: Kan ikke finde sektionen .debug_abbrev." + +#~ msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +#~ msgstr "Dwarf-fejl: Forkortelsesafstanden (%lu) større end eller lig med størrelsen .debug_abbrev (%lu)." + +#~ msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +#~ msgstr "%s: advarsel: uløselig relokering mod symbol \"%s\" fra sektionen %s" + +#~ msgid "%s: Not enough room for program headers (allocated %u, need %u)" +#~ msgstr "%s: Ikke tilstrækkeligt med plads for programhoveder (allokerede %u, behøver %u)" + +#~ msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +#~ msgstr "Fejl: Første sektion i segmentet (%s) begynder ved 0x%x mens segmentet begynder ved 0x%x" + +#~ msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +#~ msgstr "%s: advarsel: uløselig relokering %d mod symbol \"%s\" fra sektionen %s" + +#~ msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +#~ msgstr "FEJL: %s er oversat for EABI version %d, mens %s er oversat for version %d" + +#~ msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +#~ msgstr "%s: uløselig relokering %s mod symbol \"%s\" fra sektionen %s" + +#~ msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +#~ msgstr "%s: relokeringen %s bør ikke bruges nÃ¥r et delt objekt oprettes; genoversæt med -fPIC" + +#~ msgid "%s(%s+0x%lx): fixing %s" +#~ msgstr "%s(%s+0x%lx): retter %s" + +#~ msgid " [m68000]" +#~ msgstr " [m68000]" + +#~ msgid "Linking mips16 objects into %s format is not supported" +#~ msgstr "Lænkning af mips16-objekter til %s-format understøttes ikke" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Ukendt speciallænkertype %d" + +#~ msgid "v850ea architecture" +#~ msgstr "v850ea-arkitektur" + +#~ msgid "%s: check_relocs: unhandled reloc type %d" +#~ msgstr "%s: check_relocs: uhÃ¥ndteret relokeringstype %d" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: Sektionen %s er for stor til at stoppe hul med %ld byte i" + +#~ msgid "Error: out of memory" +#~ msgstr "Fejl: ikke mere hukommelse" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "advarsel: relokering mod fjernet sektion; nulstiller" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "lokale symboler i bortkastet sektion %s" + +#~ msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%s: %s+0x%lx: hop til stubrutine som ikke er jal" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: ISA (-mips%d) passer ikke med tidligere moduler (-mips%d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: ISA (%d) passer ikke med tidligere moduler (%d)" + +#~ msgid " [mips1]" +#~ msgstr " [mips1]" + +#~ msgid " [mips2]" +#~ msgstr " [mips2]" + +#~ msgid " [mips3]" +#~ msgstr " [mips3]" + +#~ msgid " [mips4]" +#~ msgstr " [mips4]" + +#~ msgid " [mips5]" +#~ msgstr " [mips5]" + +#~ msgid " [mips32]" +#~ msgstr " [mips32]" + +#~ msgid " [mips64]" +#~ msgstr " [mips64]" + +#~ msgid " [mips16]" +#~ msgstr " [mips16]" + +#~ msgid " [32bitmode]" +#~ msgstr " [32-bittilstand]" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "bfd_make_section (%s) mislykkedes" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) mislykkedes" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "Størrelsen passer ikke pÃ¥ sektion %s=%lx, %s=%lx" + +#~ msgid "unknown gsd/egsd subtype %d" +#~ msgstr "ukendt gsd/egsd-undertype %d" + +#~ msgid "failed to enter %s" +#~ msgstr "mislykkedes med at gÃ¥ ind i %s" + +#~ msgid "No Mem !" +#~ msgstr "Ingen hukommelse!" + +#~ msgid "%s: no symbol \"%s\"" +#~ msgstr "%s: intet symbol \"%s\"" + +#~ msgid "reserved STO cmd %d" +#~ msgstr "reserveret STO-kommando %d" + +#~ msgid "reserved OPR cmd %d" +#~ msgstr "reserveret OPR-kommando %d" + +#~ msgid "reserved CTL cmd %d" +#~ msgstr "reserveret CTL-kommando %d" + +#~ msgid "stack-from-image not implemented" +#~ msgstr "stack-from-image er ikke implementeret" + +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "stack-entry-mask er ikke helt implementeret" + +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "stack-local-symbol er ikke helt implementeret" + +#~ msgid "stack-literal not fully implemented" +#~ msgstr "stack-literal er ikke helt implementeret" + +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "stack-local-symbol-entry-point-mask er ikke helt implementeret" + +#~ msgid "obj code %d not found" +#~ msgstr "objektkode %d kunne ikke findes" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: dynamisk relokering uden spekulationsrettelser" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: spekulationsfix mod udefineret svagt symbol" + +#~ msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +#~ msgstr "%s: relokering giver overløb 1: 0x%lx > 0xffff" diff --git a/external/gpl3/gdb/dist/bfd/po/es.gmo b/external/gpl3/gdb/dist/bfd/po/es.gmo new file mode 100644 index 0000000000000000000000000000000000000000..b0bdade10b9fbf18688b4b236bd61d6af288f1a6 GIT binary patch literal 139774 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zG(Tq22zRZ06HZSnU-dcwpWD9v&CZ})oMtdE15n9d>~P;jr#KS{##SFWh+#cdz%7f1 zr?52kwcmXC`Mv3q{*0pgGs+&!Dtq&=^`_?CGxJHJ+wIny)81oJWULxnUAHIxK56@3 zPeAcc+PqC{HYEuxt9lH|leQrj=4e=1m&A7DqJnxD0m;je2@llDL;JX#fwpeKnP^z@ zxO@aaC!!w#FUZ?ZT#XoYFD~nOJPUbatfHh$NwtIKbU4Qf zkYHQvTEt1ARz-gmKgKL10v)SY^(jirsx+9-)xT!gC-BP+0)oCFjTc=Djf35b*GVER?u y$h, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2010-11-18 18:25-0600\n" +"Last-Translator: Cristian Othón Martínez Vera \n" +"Language-Team: Spanish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Tipo de sección desconocido en el fichero a.out.adobe: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Se exportó un tipo de reubicación inválido: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Se importó un tipo de reubicación inválido: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Se importó un registro de reubicación erróneo: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: no se puede representar la sección `%s' en el formato de fichero objeto a.out" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: no se puede representar la sección para el símbolo `%s' en el formato de fichero objeto a.out" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*desconocido*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: tipo de reubicación inesperado\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: no se admite el enlace reubicable de %s a %s" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Aviso: la escritura del fichero fue lenta: se reescribe la marca de tiempo\n" + +# ¡Uff! Si utilizáramos file=archivo, esta traducción sería imposible. cfuga +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "Se lee la marca de tiempo modificada del fichero en el archivo" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "Se escribe la marca de tiempo actualizada de armap" + +#: bfd.c:395 +msgid "No error" +msgstr "No hay error" + +#: bfd.c:396 +msgid "System call error" +msgstr "Error en la llamada al sistema" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "Objetivo bfd inválido" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "Fichero en formato erróneo" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "Archivo de ficheros objeto en formato erróneo" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "Operación inválida" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "Memoria agotada" + +#: bfd.c:402 +msgid "No symbols" +msgstr "No hay símbolos" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "El archivo no tiene índice; ejecute ranlib para agregar uno" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "No hay más ficheros archivados" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "Archivo malformado" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "No se reconoce el formato del fichero" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "El formato del fichero es ambiguo" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "La sección no tiene contenido" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "Sección no representable en la salida" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "Un símbolo requiere de una sección de depuración, la cual no existe" + +#: bfd.c:411 +msgid "Bad value" +msgstr "Valor erróneo" + +#: bfd.c:412 +msgid "File truncated" +msgstr "Fichero truncado" + +#: bfd.c:413 +msgid "File too big" +msgstr "El fichero es demasiado grande" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "Error al leer %s: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "falló la aseveración BFD %s %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "error interno de BFD %s, se aborta en %s línea %d en %s\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "error interno de BFD %s, se aborta en %s línea %d\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "Por favor reporte este bicho.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "no se mapea: datos=%lx mapeados%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "no se mapea: no se estableció la variable de ambiente\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Aviso: Se escribe la sección `%s' a un desplazamiento de fichero grande (pe negativo) 0x%lx." + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax y -r no se pueden usar juntos\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "se reabre %B: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: No se pueden manejar binarios Alpha comprimidos.\n" +" Use las opciones del compilador, o objZ, para generar binarios sin comprimir." + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: tipo de reubicación %d desconocida/no admitida" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "se usó una reubicación relativa a GP cuando GP no estaba definido" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "se usan valores múltiples de gp" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: tipo de reubicación no admitida: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: tipo de reubicación no admitida: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: tipo de reubicación %d desconocido" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: no se puede encontrar el pegamento THUMB '%s' para `%s'" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: no se puede encontrar el pegamento ARM '%s' para `%s'" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): aviso: no se activó la interoperabilidad.\n" +" primer suceso: %B: llamada arm a thumb" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): aviso: no se activó la interoperabilidad.\n" +" primer suceso: %B: llamada thumb a arm\n" +" considere reenlazar con --support-old-code activado" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: dirección de reubicación 0x%lx errónea en la sección `%A'" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: índice de símbolos ilegal en la reubicación: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "error: %B está compilado para APCS-%d, mientras que %B está compilado para APCS-%d" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "error: %B pasa números de coma flotante en registros de coma flotante, mientras que %B los pasa en registros enteros" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "error: %B pasa números de coma flotante en registros enteros, mientras que %B los pasa en registros de coma flotante" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "error: %B está compilado como código independiente de posición, mientras que el objetivo %B es de posición absoluta" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "error: %B está compilado como código de posición absoluta, mientras que el objetivo %B es independiente de posición" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Aviso: %B admite interoperabilidad, mientras que %B no" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Aviso: %B no admite interoperabilidad, mientras que %B sí" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "opciones privadas = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr "[números de coma flotante pasados en registros de coma flotante]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr "[números de coma flotante pasados en registros enteros]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr "[independiente de posición]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr "[posición absoluta]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr "[no se inicializó la opción de interoperabilidad]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr "[admite interoperabilidad]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr "[no admite interoperabilidad]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Aviso: No se establece la opción de interoperabilidad de %B ya que se había especificado con anterioridad como no interoperable" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Aviso: Se limpia la opción de interoperabilidad de %B debido a una petición externa" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "no se puede manejar la reubicación R_MEM_INDIRECT cuando se utiliza la salida %s" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "La reubicación `%s' aún no está implementada\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: aviso: índice de símbolos %ld ilegal en reubicaciones" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "convención de llamada incierta para un símbolo que no es COFF" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "no se admite el tipo de reubicación" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "reubicación relativa a GP cuando _gp no está definido" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "No se reconoce la reubicación" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: no se admite el tipo de reubicación 0x%02x" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: reubicación de TOC en 0x%x al símbolo `%s' sin entrada TOC" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: el símbolo `%s' tiene smclas %d que no se reconoce" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "No se reconoce el tipo de reubicación 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: aviso: índice de símbolos %ld ilegal en reubicaciones" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "se descarta la reubicación %s\n" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: aviso: el símbolo COMDAT '%s' no coincide con el nombre de sección '%s'" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Aviso: Se descarta la opción de sección IMAGE_SCN_MEM_NOT_PAGED en la sección %s" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Se descarta la opción de sección %s (0x%x)" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "No se reconoce el id de objetivo COFF TI '0x%x'" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: reubicación contra un índice de símbolo que no existe: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: Demasiadas secciones (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: sección %s: desbordamiento de tabla de cadenas en el desplazamiento %ld" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: aviso: falló la lectura de tabla de números de línea" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: aviso: índice de símbolos %ld ilegal en los números de línea" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: aviso: información de números de línea duplicada para `%s'" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: No se reconoce la clase de almacenamiento %d para %s símbolo `%s'" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "aviso: %B: el símbolo local `%s' no tiene sección" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: tipo de reubicación %d ilegal en la dirección 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: tamaño de tabla de cadenas %lu erróneo" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Aviso: el tipo del símbolo `%s' cambió de %d a %d en %B" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: reubicaciones en la sección `%A', pero no tiene contenido" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: desbordamiento de reubicación: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: aviso: %s: desbordamiento de número de línea: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "error: %B está compilado para el EP9312, mientras que %B está compilado para XScale" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "aviso: no se puede actualizar el contenido de la sección %s en %s" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Error de Dwarf: No se puede encontrar la sección %s." + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Error de Dwarf: El desplazamiento (%lu) es mayor que o igual que el tamaño de %s (%lu)." + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Error de Dwarf: Valor de FORM sin manejar o inválido: %u." + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Error de Dwarf: sección de números de línea revuelta (número de fichero erróneo)." + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Error de Dwarf: .debug_line versión %d sin manejar." + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Error de Dwarf: Máximo de operaciones por instrucción inválido." + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Error de Dwarf: sección de números de línea revuelta." + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Error de Dwarf: No se puede encontrar el número de abreviatura %u." + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Error de Dwarf: se encontró la versión de dwarf '%u', este lector solamente maneja información de las versiones 2, 3 y 4." + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Error de Dwarf: se encontró el tamaño de dirección '%u', este lector no puede manejar tamaños más grandes que '%u'." + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Error de Dwarf: Número de abreviación erróneo: %u." + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "Tipo básico %d desconocido" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Símbolo final+1: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Primer símbolo: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Símbolo final+1: %-7ld Tipo: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Símbolo local: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; símbolo final+1: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; símbolo final+1: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; símbolo final+1: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tipo: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "error: %B: El objeto tiene contenido específico del vendedor que se debe procesar con la cadena de compilación '%s'" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "error: %B: La etiqueta de objeto '%d, %s' es incompatible con la etiqueta '%d, %s'" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: error en %B(%A); no se creará la tabla .eh_frame_hdr.\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: la codificación fde en %B(%A) previene la creación de la tabla .eh_frame_hdr.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: el símbolo STT_GNU_IFUNC dinámico `%s' con igualdad de puntero en `%B' no se puede usar al hacer un ejecutable; recompile con -fPIE y reenlace con -pie\n" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "error interno: error fuera de rango" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "error interno: no se admite el error de reubicación" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "error interno: error peligroso" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "error interno: error desconocido" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): reubicación %s sin resolución contra el símbolo `%s'" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "error: tipo de reubicación inapropiada para la biblioteca compartida (¿olvidó -fpic?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "error interno: se usó un tipo de reubicación sospechosa en la biblioteca compartida" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "la variable dinámica `%s' es de tamaño cero" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: desplazamiento de cadena inválido %u >= %lu para la sección `%s'" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B el número de símbolo %lu hace referencia a la sección inexistente SHT_SYMTAB_SHNDX" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Campo de tamaño corrupto en el encabezado de la sección de grupo: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: entrada SHT_GROUP inválida" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: no hay información de grupo para la sección %A" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: aviso: no se estableció sh_link para la sección `%A'" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%d] en la sección `%A', es incorrecto" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: sección [%d] desconocida `%s' en el grupo [%s]" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: no se puede inicializar el estado comprimido de la sección %s" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: no se puede inicializar el estado descomprimido de la sección %s" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Encabezado del Programa:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Sección Dinámica:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Definiciones de versión:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Referencias de versión:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " se requere desde %s:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: enlace %lu inválido para la sección de reubicación %s (índice %u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: no se sabe cómo manejar la sección específica alojada de la aplicación `%s' [0x%8x]" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: no se sabe cómo manejar la sección específica de procesador `%s' [0x%8x]" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: no se sabe cómo manejar la sección específica de SO `%s' [0x%8x]" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: no se sabe cómo manejar la sección `%s' [0x%8x]" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "aviso: el tipo de la sección `%A' cambió a PROGBITS" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link de la sección `%A' apunta a la sección descartada `%A' de `%B'" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link de la sección `%A' apunta a la sección eliminada `%A' de `%B'" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: La primera sección en el segmento PT_DYNAMIC no es la sección .dynamic" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: No hay suficiente espacio para los encabezados del programa, pruebe enlazar con -N" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "%B: la sección %A lma %#lx se ajusta a %#lx" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: la sección `%A' no se puede asignar en el segmento %d" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: aviso: la sección asignada `%s' no está en el segmento" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: se requiere el símbolo `%s' pero no está presente" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: aviso: Se detectó un segmento cargable vacío, ¿ esto es intencional ?\n" + +#: elf.c:6622 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "No se puede encontrar la sección de salida equivalente para el símbolo '%s' de la sección '%s'" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: no se admite el tipo de reubicación %s" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): aviso: no se activó la interoperabilidad.\n" +" primer suceso: %B: llamada Thumb a ARM" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): aviso: no se activó la interoperabilidad.\n" +" primer suceso: %B: llamada ARM a Thumb" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: no se puede crear la entrada de cabo %s" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "no se puede encontrar el pegamento THUMB '%s' para `%s'" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "no se puede encontrar el pegamento ARM '%s' para `%s'" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: las imágenes BE8 sólo son válidas en modo big-endian." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: aviso: no se necesita la alternativa para evitar la errata del VFP11 seleccionado para la arquitectura objetivo" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: no se puede encontrar la chapa de VFP11 `%s'" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Tipo de reubicación TARGET2 '%s' inválido." + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%s(%s): aviso: no se activó la interoperabilidad.\n" +" primer suceso: %B: llamada thumb a arm" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Aviso: La instrucción Arm BLX apunta a la función Arm '%s'." + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Aviso: La instrucción Thumb BLX apunta a la función thumb '%s'." + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): la reubicación R_ARM_TLS_LE32 no se permite en objetos compartidos" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Sólo se permiten las instrucciones ADD o SUB en las reubicaciones de grupo ALU" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Desborde al dividirse 0x%lx para la reubicación de grupo %s" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): reubicación %s contra la sección SEC_MERGE" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): se usó %s con el símbolo TLS %s" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): se usó %s con el símbolo %s que no es TLS" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "fuera de rango" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "no se admite la reubicación" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "error desconocido" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Aviso: Se limpia la opción de interoperación en %B porque se ha enlazado con él código no interoperable en %B" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: Atributo de objeto EABI obligatorio %d desconocido" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Aviso: %B: Atributo de objeto EABI %d desconocido" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "error: %B: Arquitectura de CPU desconocida" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "error: %B: Arquitecturas de CPU en conflicto %d/%d" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "Error: %B tiene al mismo tiempo los atributos Tag_MPextension_use actuales y antiguos" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "error: %B utiliza argumentos de registro VFP, mientras que %B no" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "error: %B: no se pueden mezclar los atributos de virtualización con %B" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "error: %B: Perfiles de arquitecturas en conflicto %c/%c" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Aviso: %B: Configuración de plataformas en conflicto" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "error: %B: Uso en conflicto de R9" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "error: %B: El direccionamiento relativo a SB tiene conflictos con el uso de R9" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "aviso: %B usa wchar_t de %u bytes aunque la salida usa wchar_t de %u bytes; el uso de valores wchar_t entre objetos puede fallar" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "aviso: %B usa enums %s aunque la salida usa enums %s; el uso de valores enum entre objetos puede fallar" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "error: %B utiliza argumentos de registro iWMMXt, mientras que %B no" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "error: no coincide el formato fp16 entre %B y %B" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "no coincide el uso de DIV entre %B y %B" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "%B tiene al mismo tiempo los atributos actuales y antiguos de Tag_MPextension" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "opciones privadas = %lx:" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [interoperabilidad activada]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [formato de coma flotante VFP]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [formato de coma flotante Maverick]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [formato de coma flotante FPA]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [ABI nuevo]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [ABI antiguo]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [FP por software]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [EABI Version1]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [tabla de símbolos ordenados]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [tabla de símbolos sin ordenar]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [EABI Version2]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [los símbolos dinámicos utilizan índices de segmento]" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [el mapeo de símbolos precede a otros]" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [EABI Version3]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [EABI Version4]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [EABI Version5]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [ejecutable reubicable]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [tiene punto de entrada]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: índice de símbolos erróneo: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: no se puede usar la reubicación %s contra `%s' cuando se hace un objeto compartido; recompile con -fPIC" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Se encontraron errores al procesar el fichero %s" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: error: el cabo de errores Cortex-A8 se aloja en una ubicación insegura" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: error: el cabo de errores Cortex-A8 está fuera de rango (el fichero de entrada es demasiado grande)" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: error: la chapa VFP11 está fuera de rango" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "error: %B ya está en el formato BE8 final" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "error: El objeto fuente %B tiene EABI versión %d, pero el objetivo %B tiene EABI versión %d" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "error: %B está compilado para APCS-%d mientras que el objetivo %B usa APCS-%d" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "error: %B utiliza instrucciones VFP, mientras que %B no" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "error: %B utiliza instrucciones FPA, mientras que %B no" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "error: %B utiliza instrucciones Maverick, mientras que %B no" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "error: %B no utiliza instrucciones Maverick, mientras que %B sí" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "error: %B utiliza FP de software, mientras que %B utiliza FP de hardware" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "error: %B utiliza FP de hardware, mientras que %B utiliza FP de software" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "error interno: reubicación peligrosa" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: no se puede crear la entrada de cabo %s" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): reubicación sin resolución contra el símbolo `%s'" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): reubicación contra `%s': error %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: la reubicación en `%A+0x%x' referencía al símbolo `%s' con adición que no es cero" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "la reubicación referencía un símbolo que no está definido en el módulo" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC referencía un símbolo dinámico con adición que no es cero" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "no se pueden emitir composturas en la sección de sólo lectura" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "no se pueden emitir reubicaciones dinámicas en la sección de sólo lectura" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE referencía un símbolo dinámico con adición que no es cero" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "no se admiten las reubicaciones entre segmentos diferentes" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "aviso: la reubicación referencía un segmento diferente" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: no se admite el tipo de reubicación %i" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: no se puede enlazar el fichero objeto que no es fdpic en un ejecutable fdpic" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: no se puede enlazar el fichero objeto fdpic en un ejecutable que no es fdpic" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, sección %A: reubicación %s sin resolución contra el símbolo `%s'" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, sección %A: No hay PLT ni GOT para la reubicación %s contra el símbolo `%s'" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, sección %A: No hay PLT para la reubicación %s contra el símbolo `%s'" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "[cuyo nombre está perdido]" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, sección %A: reubicación %s con adición %d que no es cero contra el símbolo local" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, sección %A: reubicación %s con adición %d que no es cero contra el símbolo `%s'" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, sección %A: no se permite la reubicación %s para el símbolo global: `%s'" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, sección %A: la reubicación %s sin GOT creado" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, sección %A: la reubicación %s tiene una referencia sin definir a `%s', ¿tal vez una confusión en la declaración?" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, sección %A: no se permite la reubicación %s para el símbolo: `%s' el cual se define fuera del programa, ¿tal vez una confusión en la declaración?" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(demasiadas variables globales para -fpic: recompile con -fPIC)" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(datos thread-local demasiado grandes para -fpic o -msmall-tls: recompile con -fPIC o -mno-small-tls)" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, sección %A:\n" +" el objeto %s compatible con v10/v32 no debe contener una reubicación PIC" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, sección %A:\n" +" la reubicación %s no es válida en un objeto compartido; es una confusión de opción típica, recompile con -fPIC" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, sección %A:\n" +" la reubicación %s no se debe usar en un objeto compartido; recompile con -fPIC" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, sección `%A', para el símbolo `%s':\n" +" la reubicación %s no se debe usar en un objeto compartido; recompile con -fPIC" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "Número de máquina inesperado" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [los símbolos tiene un prefijo _]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 y v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: se usan símbolos con prefijo _, pero se escribe el fichero con símbolos sin prefijo" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: se usan símbolos sin prefijo, pero se escribe el fichero con símbolos con prefijo _" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B contiene código CRIS v32, incompatible con objetos previos" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B contiene código que no es CRIS v32, incompatible con objetos previos" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "la reubicación requiere una adición cero" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): la reubicación a `%s+%x' tal vez causó el error anterior" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "no se aplicó R_FRV_GETTLSOFF a una instrucción call" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "no se aplicó R_FRV_GOTTLSDESC12 a una instrucción lddi" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "no se aplicó R_FRV_GOTTLSDESCHI a una instrucción sethi" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "no se aplicó R_FRV_GOTTLSDESCLO a una instrucción setlo o setlos" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "no se aplicó R_FRV_GOTTLSDESC_RELAX a una instrucción ldd" + +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "no se aplicó R_FRV_GETTLSOFF_RELAX a una instrucción calll" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "no se aplicó R_FRV_GOTTLSOFF12 a una instrucción ldi" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "no se aplicó R_FRV_GOTTLSOFFHI a una instrucción sethi" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "no se aplicó R_FRV_GOTTLSOFFLO a una instrucción setlo o setlos" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "no se aplicó R_FRV_TLSOFF_RELAX a una instrucción ld" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "no se aplicó R_FRV_TLSMOFFHI a una instrucción sethi" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "no se aplicó R_FRV_TLSMOFFLO a una instrucción setlo o setlos" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC referencía un símbolo dinámico con adición que no es cero" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE referencía un símbolo dinámico con adición que no es cero" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): reubicación contra `%s': %s" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "la reubicación referencía un segmento diferente" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: compilado con %s y enlazado con módulos que usan reubicaciones que no son pic" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: compilado con %s y enlazado con módulos compilados con %s" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: usa campos e_flags desconocidos (0x%lx) diferentes a aquéllos de los módulos previos (0x%lx)" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "opciones privadas = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Reubicaciones en ELF genérico (EM: %d)" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): no se puede alcanzar %s, recompile con -ffuntion-sections" + +#: elf32-hppa.c:1284 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: no se puede usar la reubicación %s cuando se hace un objeto compartido; recompile con -fPIC" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "%B: cabo de exportación %s duplicado" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): la compostura %s para la insn 0x%x no se admite en un enlazado que no es compartido" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): no se puede manejar %s para %s" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr "la sección .got no está inmediatamente después de la sección .plt" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: tipo de reubicación %d inválido" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: falló la transición TLS de %s para %s contra `%s' en 0x%lx en la sección `%A'" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: la reubicación %s contra el símbolo STT_GNU_IFUNC `%s' no es manejada por %s" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: se accedió `%s' como un símbolo normal y un símbolo local de hilo" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: no se reconoce la dirección de reubicación (0x%lx) en la sección `%A'" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "símbolo oculto" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "símbolo interno" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "símbolo protegido" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "símbolo" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: no se puede usar la reubicación R_386_GOTOFF contra %s indefinida `%s' cuando se hace un objeto compartido" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: no se puede usar la reubicación R_386_GOTOFF contra la función protegida `%s' cuando se hace un objeto compartido" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "se descarta la sección de salida: `%A'" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "relajador ip2k: tabla switch sin información completa de reubicación de coincidencias." + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "relajador ip2k: encabezado de tabla switch corrupto." + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "enlazador ip2k: falta la instrucción de página en 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "enlazador ip2k: instrucción de página redundante en 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "no se admite la reubicación entre espacios de direcciones datos/insn" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: usa campos de e_flags diferentes (0x%lx) que los módulos previos (0x%lx)" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "reubicación relativa al puntero global cuando _gp no está definido" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "dirección relativa al puntero global fuera de rango" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "error interno: addend debe ser cero para R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "reubicación SDA cuando _SDA_BASE_ no está definido" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: El objetivo (%s) de una reubicación %s está en la sección errónea (%A)" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: El conjunto de instrucciones no coincide con módulos previos" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "opciones privadas = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": instrucciones m32r" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": instrucciones m32rx" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": instrucciones m32r2" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "El referenciar al símbolo far `%s' usando una reubicación incorrecta puede resultar en una ejecución incorrecta" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "la dirección almacenada [%lx:%04lx] (%lx) no está en el mismo banco que la dirección almacenada actual [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "referencia a una dirección almacenada [%lx:%04lx] en el espacio normal de direcciones en %04lx" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: se enlazan ficheros compilados con enteros de 16-bit (-mshort) y otros con enteros de 32-bit" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: se enlazan ficheros compilados con dobles de 32-bit (-fshort-double) y otros con dobles de 64-bit" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: se enlazan ficheros compilados para HCS12, con otros compilados para HC12" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: usa campos de e_flags diferentes (0x%lx) que los módulos previos (0x%lx)" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=int de 32-bit, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=int de 16-bit, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "doble de 64-bit, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "doble de 32-bit, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr " [memoria=modelo de bancos]" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr " [memoria=plana]" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "desconocido" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: desbordamiento de GOT: Número de reubicaciones con desplazamiento de 8-bit > %d" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: desbordamiento de GOT: Número de reubicaciones con desplazamiento de 8 o 16-bit > %d" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): la reubicación R_68K_TLS_LE32 no se permite en objetos compartidos" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Actualmente no se admite la reubicación %s (%d).\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Tipo de reubicación %d desconocido\n" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B y %B son para núcleos diferentes" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B y %B son para configuraciones diferentes" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "opciones privadas = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: tipo de reubicación %d desconocido" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: El objetivo (%s) de una reubicación %s está en la sección errónea (%s)" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: ¿Compilado probablemente sin -fPIC?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: nombre de sección de reubicación `%s' erróneo" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "la reubicación literal sucede para un símbolo externo" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "la reubicación relativa a gp de 32bits sucede para un símbolo externo" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "el enlazador genérico no puede manejar %s" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "sección %s corrupta en %B" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "no se puede leer en la sección %s desde %B" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "aviso: no se puede establecer el tamaño de la sección %s en %B" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "no se puede reservar espacio para la nueva sección APUinfo." + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "no se puede calcular la nueva sección APUinfo." + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "no se puede instalar la nueva sección APUinfo." + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: no se puede usar la reubicación %s cuando se hace un objeto compartido" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): reubicación %s contra un símbolo local" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Aviso: %B usa coma flotante hard, %B usa coma flotante soft" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Aviso: %B usa coma flotante hard de doble precisión, %B usa coma flotante hard de precisión simple" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Aviso: %B usa coma flotante soft, %B usa coma flotante hard de precisión simple" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Aviso: %B usa la ABI de coma flotante desconocida %d" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Aviso: %B usa la ABI de vector desconocida %d" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Aviso: %B usa la ABI de vector \"%s\", %B usa \"%s\"" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Aviso: %B usa r3/r4 para devoluciones de estructura small, %B usa memoria" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Aviso: %B usa la convención de devolución de estructura small %d" + +#: elf32-ppc.c:4197 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: compilado con -mrelocatable y enlazado con módulos compilados de forma normal" + +#: elf32-ppc.c:4205 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: compilado de forma normal y enlazado con módulos compilados con -mrelocatable" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "Se usa bss-plt debido a %B" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: tipo de reubicación %d desconocido para el símbolo %s" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): adición que no es cero en la reubicación %s contra `%s'" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): no se admite la reubicación %s para la función indirecta %s" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: el objetivo (%s) de una reubicación %s está en la sección de salida errónea (%s)" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: la reubicación %s aún no se admite para el símbolo %s." + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): reubicación %s contra `%s': error %d" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "no se definió %s en el %s creado por el enlazador" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%B:%A: Aviso: reubicación Red Hat obsoleta" + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "Aviso: reubicación RX_SYM con un símbolo desconocido" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "%B(%A): error: llamada a la función sin definir '%s'" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "%B(%A): aviso: acceso sin alinear al símbolo '%s' en el área de datos small" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "%B(%A): error interno: error fuera de rango" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "%B(%A): error interno: no se admite el error de reubicación" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "%B(%A): error interno: reubicación peligrosa" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "%B(%A): error interno: error desconocido" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr " [dobles de 64-bit]" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr " [dsp]" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): instrucción inválida para la reubicación TLS %s" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "no hay suficiente espacio GOT para entradas GOT locales" + +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "la dirección no está alineada a word" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Se detectó una reubicación malformada para la sección %s" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: la reubicación CALL15 en 0x%lx no es contra un símbolo global" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr " [pic]" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr " [fix dep]" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: aviso: se enlazan ficheros PIC con ficheros que no son PIC" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: la directiva IMPORT AS para %s oculta un IMPORT AS previo" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: No se reconoce la orden .directive: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Falló al agregar el símbolo renombrado %s" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: aviso: desplazamiento R_SH_USES erróneo" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: aviso: R_SH_USES señala al insn 0x%x que no se reconoce" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: aviso: desplazamiento de carga R_SH_USES erróneo" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: aviso: no se puede encontrar la reubicación esperada" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: aviso: símbolo en una sección inesperada" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: aviso: no se puede encontrar la reubicación COUNT esperada" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: aviso: cuenta errónea" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: fatal: desbordamiento de reubicación durante la relajación" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "No se maneja un STO_SH5_ISA32 inesperado en un símbolo local" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: fatal: objetivo de ramificación sin alineación para la reubicación de soporte de relajamiento" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: fatal: reubicación %s sin alineación 0x%lx" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: la reubicación R_SH_PSHA %d no está en el rango -32..32" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: la reubicación R_SH_PSHL %d no está en el rango -32..32" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%B(%A+0x%lx): no se pueden emitir composturas para `%s' en la sección de sólo lectura" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%B(%A+0x%lx): reubicación %s contra el símbolo externo \"%s\"" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%X%C: la reubicación de \"%s\" referencía un segmento diferente\n" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%C: aviso: la reubicación de \"%s\" referencía un segmento diferente\n" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: se accedió `%s' como un símbolo normal y un símbolo FDPIC" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: se accedió `%s' como un símbolo FDPIC y un símbolo local de hilo" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "%B: Reubicación de descriptor de función con adición que no es cero" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: el código de ejecución local TLS no se puede enlazar en objetos compartidos" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: compilado como un objeto de 32-bit y %s es de 64-bit" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: compilado como un objeto de 64-bit y %s es de 32-bit" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: el tamaño del objeto no coincide con el tamaño del objetivo %s" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: se encontró un símbolo datalabel en la entrada" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "No coincide PTB: una dirección SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "No coincide PTA: una dirección SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: error de GAS: insn PTB inesperada con R_SH_PT_16" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: error: tipo de reubicación %d sin alinear en %08x reubicación %p\n" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: no se pueden escribir las entradas .cranges agregadas" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: no se pueden escribir las entradas .cranges ordenadas" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: compilado para un sistema de 64 bit y el objetivo es de 32 bit" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: se enlazan ficheros little endian con ficheros big endian" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: la sección de sobreescritura %A no inicia en una línea de caché.\n" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: la sección de sobreescritura %A es más grande que una línea de caché.\n" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: la sección de sobreescritura %A no está en el área de caché.\n" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: las secciones de sobreescritura %A y %A no inician en la misma dirección.\n" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "aviso: se llama al símbolo %s que no es función, definido en %B" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) difiere del análisis (%u)\n" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "%B no tiene permitido definir %s" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "no se le permite definir %s en un guión" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "%s en la sección de sobreescritura" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "desbordamiento de la reubicación de cabo de sobreescritura" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "los cabos no coinciden con el tamaño calculado" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "aviso: %s sobreescribe %s\n" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "aviso: %s excede el tamaño de la sección\n" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v no se encuentra en la tabla de función\n" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): se llama a la sección %B(%A) que no es de código, análisis incompleto\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "El análisis de pila descartará la llamada de %s a %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " llama:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s duplicado en %s\n" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "%s duplicado\n" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "perdón, no se admiten ficheros objeto duplicados en el guión de sobreescritura automática\n" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "eltamaño 0x%v que no es de sobreescritura mas el tamaño de sobreescritura máximo de 0x%v excede el almacenamiento local\n" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s excede el tamaño de sobreescritura\n" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "Tamaño de la pila para los nodos raíz del grafo de llamadas.\n" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Tamaño de la pila para funciones. Anotaciones: '*' max de pila, 't' llamada cola\n" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "La pila máxima requerida es 0x%v\n" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "error fatal al crear .fixup" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s+0x%lx): reubicación %s sin resolución contra el símbolo `%s'" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "%B: reubicación relativa a SB pero _c6xabi_DSBT_BASE no está definido" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "%B: el tipo de reubicación %d aún no está implementado" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "reubicación peligrosa" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "error: %B requiere más alineación de pila que la que %B preserva" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "error: valor de Tag_ABI_array_object_alignment desconocido en %B" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "error: valor de Tag_ABI_array_object_align_expected desconocido en %B" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "error: %B requiere más alineación de matriz que la que %B preserva" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "aviso: %B y %B difieren en tamaño wchar_t" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "aviso: %B y %B difieren en si el código está compilado para DSBT" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "aviso: %B y %B difieren en el direccionamiento de datos dependiente de posición" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "aviso: %B y %B difieren en el direccionamiento de código dependiente de posición" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "La variable `%s' no puede ocupar múltiples regiones de datos small" + +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "La variable `%s' solamente puede estar en una de las regiones de datos small, zero, y tiny" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos small y zero" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos small y tiny" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "La variable `%s' no puede estar simultáneamente en las regiones de datos zero y tiny" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "FALLO para encontrar la reubicación HI16 previa\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "no se puede localizar el símbolo especial del enlazador __gp" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "no se puede localizar el símbolo especial del enlazador __ep" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "no se puede localizar el símbolo especial del enlazador __ctbp" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: No coincide la arquitectura con los módulos previos" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "opciones privadas = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "arquitectura v850" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "arquitectura v850e" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "arquitectura v850e1" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "arquitectura v850e2" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "arquitectura v850e2v3" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr " [no pic]" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr " [flotante-d]" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr " [flotante-g]" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: aviso: la adición GOT de %ld a `%s' no coincide con la adición previa GOT de %ld" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: aviso: se descarta la adición PLT de %d a `%s' de la sección %s" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: aviso: reubicación %s contra el símbolo `%s' de la sección %s" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: aviso: reubicación %s a 0x%x de la sección %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "adición que no es cero en la reubicación @fptr" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): tabla de propiedades inválida" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): desplazamiento de reubicación fuera de rango (tamaño=0x%x)" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "reubicación dinámica en la sección de sólo lectura" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "reubicación TLS inválida sin secciones dinámicas" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "inconsistencia interna en el tamaño de la sección .got.loc" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: tipo de máquina incompatible. La salida es 0x%x. La entrada es 0x%x" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Falló el intento de convertir L32R/CALLX a CALL" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): no se puede decodificar la instrucción; posible falta de coincidencia de la configuración" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): no se puede decodificar la instrucción para la reubicación XTENSA_ASM_SIMPLIFY; posible falta de coincidencia de la configuración" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "dirección de reubicación inválida" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "desbordamiento después de la relajación" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): compostura inesperada para la reubicación %s" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "la reubicación GPDISP no encontró las instrucciones ldah y lda" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: el subsegmento .got excede los 64K (tamaño %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: reubicación relativa a gp contra el símbolo dinámico %s" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: reubicación relativa a pc contra el símbolo dinámico %s" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: cambio en gp: BRSGP %s" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: reubicación !samegp contra un símbolo sin .prologue: %s" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: reubicación dinámica sin manejar contra %s" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: reubicación relativa a pc contra el símbolo débil sin definir %s" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: reubicación relativa a dtp contra el símbolo dinámico %s" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: reubicación relativa a tp contra el símbolo dinámico %s" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "la entrada de cabo para %s no puede cargar .plt, desplazamiento dp = %ld" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): no se puede alcanzar %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Error de inconsistencia interna para el valor para\n" +" un registro global colocado por el enlazador: enlazado: 0x%lx%08lx != relajado: 0x%lx%08lx\n" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: reubicación base-más-desplazamiento contra un símbolo de registro: (desconocido) en %s" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: reubicación base-más-desplazamiento contra un símbolo de registro: %s en %s" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: reubicación de registro contra un símbolo que no es registro: (desconocido) en %s" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: reubicación de registro contra un símbolo que no es registro: %s en %s" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: la directiva LOCAL sólo es válida con un registro o un valor absoluto" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: directiva LOCAL: El registro $%ld no es un registro local. El primer registro global es $%ld." + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Error: definición múltiple de `%s'; el inicio de %s está definido en un fichero enlazado con anterioridad\n" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "La sección de registros no tiene contenido\n" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Inconsistencia interna: %u restante != %u máximo.\n" +" Por favor reporte este bicho." + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: compilado para un sistema big endian y el objetivo es little endian" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: compilado para un sistema little endian y el objetivo es big endian" + +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "la reubicación de copia contra `%s' requiere de enlazado plt flojo; evite establecer LD_BIND_NOW=1 o actualice gcc" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "cuenta errónea de la reubicación dinámica de %B, sección %A" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd no es una matriz regular de entradas opd" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: tipo de reubicación %u inesperado en la sección .opd" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: símbolo `%s' sin definir en la sección .opd" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "se definió %s en la entrada toc eliminada" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "desbordamiento del desplazamiento de stub de ramificación long `%s'" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "no se puede encontrar la ramificación de cabo `%s'" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "error de la tabla de enlazado contra `%s'" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "no se puede construir la ramificación de cabos `%s'" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "%B sección %A excede el tamaño de grupo de cabos" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"cabos de enlazador en %u grupo%s\n" +" rama %lu\n" +" ajuste toc %lu\n" +" rama long %lu\n" +" ajuste toc long %lu\n" +" llamada plt %lu" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): no se admiten los TOCs múltiples automáticos, utilizando sus ficheros crt; recompile con -mminimal-toc o actualice gcc" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): la optimización de llamada hermana a `%s' no permite TOCs múltiples automáticos; recompile con -mminimal-toc ó -fno-optimize-sibling-calls, o vuelva `%s' externa" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: no se admite la reubicación %s para el símbolo %s." + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: error: la reubicación %s no es un múltiplo de %d" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: error: tipo de reubicación %d sin alinear en %08x reubicación %08x\n" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Solamente los registros %%g[2367] se pueden declarar utilizando STT_REGISTER" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "El registro %%g%d se usó de forma incompatible: %s en %B, previamente %s en %B" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "El símbolo `%s' tiene tipos divergentes: REGISTER en %B, previamente %s en %B" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "El símbolo `%s' tiene tipos divergentes: %s en %B, previamente REGISTER en %B" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: se enlaza código específico de UltraSPARC con código específico de HAL" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: se accedió a '%s' como un símbolo normal y como un símbolo local de hilo" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: la reubicación %s contra el símbolo STT_GNU_IFUNC `%s' con adición que no es cero: %d" + +#: elf64-x86-64.c:3073 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: no se puede usar la reubicación R_X86_64_GOTOFF contra la función protegida `%s' cuando se hace un objeto compartido" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "; recompile con -fPIC" + +#: elf64-x86-64.c:3189 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: no se puede usar la reubicación %s contra %s `%s' cuando se hace un objeto compartido%s" + +#: elf64-x86-64.c:3191 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: no se puede usar la reubicación %s contra %s sin definir `%s' cuando se hace un objeto compartido%s" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "aviso: %s tiene un índice de tablas de cadenas corrupto - se descarta" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: la cuenta de versión (%ld) no coincide con la cuenta de símbolos (%ld)" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): la reubicación %d tiene un índice de símbolo %ld inválido" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Aviso: se truncó %B: se esperaba el tamaño de fichero core >= %lu, se encontró: %lu." + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: la definición TLS en %B sección %A no coincide con la definición que no es TLS en %B sección %A" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: la referencia TLS en %B no coincide con la referencia que no es TLS en %B" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: la definición TLS en %B sección %A no coincide con la referencia que no es TLS en %B" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: la referencia TLS en %B no coincide con la definición que no es TLS en %B sección %A" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: redefinición inesperada del símbolo con versión indirecta `%s'" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "%B: no se encuentra la versión del nodo para el símbolo %s" + +#: elflink.c:2166 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: índice de símbolos de reubicación inválido (0x%lx >= 0x%lx) erróneo para el desplazamiento 0x%lx en la sección `%A'" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: índice de símbolos que no es cero (0x%lx) para el desplazamiento 0x%lx) en la sección `%A' cuando el fichero objeto no tiene tabla de símbolos" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: el tamaño de reubicación no coincide en %B sección %A" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "aviso: el tipo y tamaño del símbolo dinámico `%s' no están definidos" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: se encontró código máquina ELF alternativo (%d) en %B, se espera %d\n" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: versión %u inválida (máximo %d)" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: versión requerida %d inválida" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Aviso: la alineación %u del símbolo común `%s' en %B es más grande que la alineación (%u) de su sección %A" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Aviso: la alineación %u del símbolo `%s' en %B es más pequeña que %u en %B" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Aviso: el tamaño del símbolo `%s' cambió de %lu en %B a %lu en %B" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "%B: referencia sin definir al símbolo '%s'" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "nota: se define '%s' en DSO %B así que se tratará de agregarlo a la línea de órdenes del enlazador" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: versión sin definir: %s" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: no se permite la sección .preinit_array en DSO" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "referencia %s sin definir en el símbolo complejo: %s" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "operador desconocido '%c' en el símbolo complejo" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: No se pueden ordenar las reubicaciones - son de tamaños diferentes" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: No se pueden ordenar las reubicaciones - son de tamaño desconocido" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "No hay suficiente memoria para ordenar las reubicaciones" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Demasiadas secciones: %d (>= %d)" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: el símbolo %s `%s' en %B está referenciado por DSO" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: no se puede encontrar la sección de salida %A para la sección de entrada %A" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: el símbolo %s `%s' no está definido" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "error: %B contiene una reubicación (0x%s) para la sección %A que refiere a un símbolo global que no existe" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X`%s' referido en la sección `%A' de %B: se definió en la sección descartada `%A' de %B\n" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A tiene tanto secciones ordenadas [`%A' en %B] como desordenadas [`%A' en %B]" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A tiene secciones tanto ordenadas como desordenadas" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: no se puede encontrar la sección de salida %s" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "aviso: la sección %s es de tamaño cero" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: aviso: se crea un DT_TEXTREL en un objeto compartido.\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: no se pueden leer símbolos: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Se elimina la sección sin uso '%s' en el fichero '%B'" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "Aviso: se descarta la opción gc-sections" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: se descarta la sección duplicada `%A'" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: la sección duplicada `%A' tiene tamaño diferente" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: aviso: no se puede leer el contenido de la sección `%A'" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: aviso: la sección duplicada `%A' tiene contenido diferente" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "procedimiento estático (sin nombre)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "%B: %A+0x%lx: No se permiten los saltos directos entre modos ISA; considere recompilar con el entrelazado activado." + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Aviso: el tamaño de opción `%s' %u erróneo es más pequeño que su encabezado" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Aviso: no se puede determinar la función objetivo para la sección de cabo `%s'" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Se detectó una reubicación malformada para la sección %s" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: no se esperaba la reubicación GOT en 0x%lx en ejecutables" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: la reubicación CALL16 en 0x%lx no es contra un símbolo global" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "reubicaciones que no son dinámicas se refieren al símbolo dinámico %s" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: No se puede encontrar una reubicación LO16 coincidente contra `%s' para %s en 0x%lx en la sección `%A'" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "la sección small-data excede los 64KB; disminuya el límite de tamaño de small-data (vea la opción -G)" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: nombre de sección `%s' ilegal" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Aviso: %B usa -msingle-float, %B usa -mdouble-float" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Aviso: %B usa -msingle-float, %B usa -mips32r2 -mfp64" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Aviso: %B usa -mdouble-float, %B usa -mips32r2 -mfp64" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: la endianez es incompatible con aquella de la emulación seleccionada" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: la ABI es incompatible con aquella de la emulación seleccionada" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: aviso: se enlazan ficheros de llamadas abi con ficheros que no son de llamadas abi" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: se enlaza código de 32-bit con código de 64-bit" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: se enlaza el módulo %s con módulos %s previos" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: no coincide ABI: se enlaza el módulo %s con módulos %s previos" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [abi desconocido]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [no hay conjunto abi]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [ISA desconocido]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [no es modo 32bit]" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "tipo de reubicación %d inválido" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "El fichero de salida requiere la biblioteca compartida `%s'\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "El fichero de salida requiere la biblioteca compartida `%s.so.%s'\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "El símbolo %s no está definido para composturas\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "Aviso: no coincide la cuenta de composturas\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: la cadena es demasiado larga (%d caracteres, máximo 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: no se reconoce el símbolo `%s' opciones 0x%x" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: grabación ATI %u sin implementar para el símbolo %u" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: tipo ATN %d inesperado en la parte externa" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "%B: tipo inesperado después de ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: carácter `%s' inesperado en el fichero Hexadecimal de Intel" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: suma de comprobación errónea en el fichero Hexadecimal de Intel (se esperaba %u, se obtuvo %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: longitud de registro de dirección extendida errónea en el fichero Hexadecimal de Intel" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: longitud de dirección de inicio extendida errónea en el fichero Hexadecimal de Intel" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: longitud de registro de dirección lineal extendida errónea en el fichero Hexadecimal de Intel" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: longitud de dirección de inicio lineal extendida errónea en el fichero Hexadecimal de Intel" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: no se reconoce el tipo ihex %u en el fichero Hexadecimal de Intel" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: error interno en ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: longitud de sección errónea en ihex_read_section" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: la dirección 0x%s está fuera de rango en el fichero Hexadecimal de Intel" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "%B: no se puede obtener la sección %A descomprimida" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Se llamó a %s que es obsoleto en %s línea %d en %s\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Se llamó a %s que es obsoleto\n" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: el símbolo indirecto `%s' para `%s' es un ciclo" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Se intentó hacer un enlace reubicable con entrada %s y salida %s" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: aviso: se descarta la sección duplicada `%A'\n" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: aviso: la sección duplicada `%A' es de tamaño diferente\n" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "encabezado de Mach-O:\n" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr " magic : %08lx\n" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " tipocpu : %08lx (%s)\n" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " subtipocpu: %08lx\n" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " tipofich : %08lx (%s)\n" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr " nordenes : %08lx (%lu)\n" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " tamordenes: %08lx\n" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr " opciones : %08lx (" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr " reservado : %08x\n" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "Segmentos y Secciones:\n" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr " #: Nombre segmento Nombre sección Dirección\n" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: acceso más allá del final de la sección mezclada (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: No hay core para asignar el nombre de sección %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: No hay core para asignar un símbolo de %d bytes de longitud\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: fichero mmo inválido: el valor de iniciación para $255 no es `Main'\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: no se admite la secuencia de caracteres anchos 0x%02X 0x%02X después del nombre de símbolo que inicia con `%s'\n" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: fichero mmo inválido: no se admite el código de operación-l `%d'\n" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: fichero mmo inválido: se esperaba YZ = 1 se obtuvo YZ = %d para lop_quote\n" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: fichero mmo inválido: se esperaba z = 1 ó z = 2, se obtuvo z = %d para lop_loc\n" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: fichero mmo inválido: se esperaba z = 1 ó z = 2, se obtuvo z = %d para lop_fixo\n" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: fichero mmo inválido: se esperaba y = 0, se obtuvo y = %d para lop_fixrx\n" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: fichero mmo inválido: se esperaba z = 16 ó z = 24, se obtuvo z = %d para lop_fixrx\n" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: fichero mmo inválido: el byte inicial del operando word debe ser 0 ó 1, se obtuvo %d para lop_fixrx\n" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: no se puede asignar el nombre de fichero para el número de fichero %d, %d bytes\n" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: fichero mmo inválido: el número de fichero %d `%s' ya se había introducido como `%s'\n" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: fichero mmo inválido: no se especificó un nombre de fichero para el número %d antes de utilizarse\n" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: fichero mmo inválido: los campos y y z de lop_stab no son cero, y: %d, z: %d\n" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: fichero mmo inválido: lop_end no es el último elemento en el fichero\n" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: fichero mmo inválido: YZ de lop_end (%ld) no es igual al número de tetras del lop_stab precedente (%ld)\n" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: tabla de símbolos inválida: símbolo `%s' duplicado\n" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Definición de símbolo errónea: `Main' se estableció como %s en lugar de la dirección de inicio %s\n" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: aviso: la tabla de símbolos es demasiado grande para mmo, es más grande que 65535 words de 32-bit: %d. Sólo se emitirá `Main'.\n" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: error interno, la tabla de símbolos cambió de tamaño de %d a %d words\n" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: error interno, la sección interna de registros %s tiene contenido\n" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: no hay registros iniciados; longitud de sección 0\n" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: demasiados registros iniciados: longitud de sección %ld\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: dirección de inicio inválida para los registros inicializados de longitud %ld: 0x%lx%08lx\n" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: no se puede representar la sección `%s' en oasys" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Tipo de sección de fichero núcleo OSF/1 %d sin manejar\n" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: `ld -r' no se admite con objetos PE MIPS\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "%B: %s sin implementar\n" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "%B: salto demasiado lejos\n" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: pair/reflo erróneo después de refhi\n" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "aviso: el tamaño de la sección .pdata (%ld) no es un múltiplo de %d\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"La Tabla de Funciones (se interpretaron los contenidos de la sección .pdata)\n" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "vma:\t\t\tDireccInicio\t DireccFin \t InformaciónDesenvuelta\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: Tipo de importación sin manejar; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: No se reconocer el tipo de importación; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: No se reconoce el tipo de nombre de importación; %x" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: No se reconoce el tipo de máquina (0x%x) en el archivo de Formato de Importación de Bibliotecas" + +#: peicode.h:1174 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: Se reconoce el tipo de máquina (0x%x) pero no se maneja en el archivo de Formato de Importación de Bibliotecas" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: el tamaño del campo es cero en el encabezado del Formato de Importación de Bibliotecas" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: cadena que no termina en null en el fichero objeto ILF." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"encabezado de ppcboot:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Desplazamiento de entrada = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Longitud = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Campo de opciones = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Nombre de la partición = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Partición[%d] inicio = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Partición[%d] fin = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Partición[%d] sector = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Partición[%d] longitud = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Encabezado Auxiliar de Ejecución\n" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers sin implementar" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: Carácter `%s' inesperado en el fichero S-record\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: Suma de comprobación errónea en el fichero S-record\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): La entrada de cabos tiene una cadena índice inválida." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "No se admite la reubicación .stab" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "Subtipo de EGSD %d desconocido" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Desbordamiento de la pila (%d) en _bfd_vms_push" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Desbordamiento por debajo de la pila en _bfd_vms_pop" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "orden ETIR %d desconocida" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "índice de sección erróneo en %s" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "no se admite la orden STA %s" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "%s: no se admite" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "%s: sin implementar" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "uso inválido de %s en contextos" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "orden %d reservada" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "¡ El módulo objeto NO está libre de errores !\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Se reemplazó el símbolo %s por %s\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC sin reubicaciones en la sección %s" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "Error de tamaño en la sección %s" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Reubicación ALPHA_R_BSR espuria" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Reubicación %s sin manejar" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "orden fuente %d desconocida" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "DST__K_SET_LINUM_INCR sin implementar" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "DST__K_SET_LINUM_INCR_W sin implementar" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "DST__K_RESET_LINUM_INCR sin implementar" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "DST__K_BEG_STMT_MODE sin implementar" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "DST__K_END_STMT_MODE sin implementar" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "DST__K_SET_PC sin implementar" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "DST__K_SET_PC_W sin implementar" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "DST__K_SET_PC_L sin implementar" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "DST__K_SET_STMTNUM sin implementar" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "orden de línea %d desconocida" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Reubicación %s + %s desconocida" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "Reubicación %s desconocida" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "Índice de sección inválido en ETIR" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "Símbolo desconocido en la orden %s" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr " EMH %u (lon=%u): " + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "Encabezado de módulo\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr " nivel estruct : %u\n" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr " tam reg máximo : %u\n" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr " nombre módulo : %.*s\n" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr " versión módulo : %.*s\n" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr " fecha compil : %.17s\n" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "Nombre de Procesador de Lenguaje\n" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr " nombre lenguaje: %.*s\n" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "Encabezado de Ficheros Fuente\n" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr " fichero: %.*s\n" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "Encabezado de Texto de Título\n" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr " título: %.*s\n" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "Encabezado de Copyright\n" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr " copyright: %.*s\n" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "subtipo emh %u sin manejar\n" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr " EEOM (lon=%u):\n" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr " número de pares de enlace cond: %u\n" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr " código de completado: %u\n" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr " ops dirección transf: 0x%02x\n" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr " psect dirección transf: %u\n" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr " dirección transf : 0x%08x\n" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr " WEAK" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr " DEF" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr " UNI" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr " REL" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr " COMM" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr " VECEP" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr " NORM" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr " QVAL" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr " PIC" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr " LIB" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr " OVR" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr " GBL" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr " SHR" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr " EXE" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr " RD" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr " WRT" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr " VEC" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr " NOMOD" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr " COM" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr " 64B" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr " EGSD (lon=%u):\n" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr " entrada EGSD %2u (tipo: %u, lon: %u): " + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "PSC - Definición de sección de programa\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr " alineación : 2**%u\n" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr " opciones : 0x%04x" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr " aloj (lon) : %u (0x%08x)\n" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr " nombre : %.*s\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "SPSC - def sección Programa de Imagen Compartida\n" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr " aloj (lon) : %u (0x%08x)\n" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr " despl imagen : 0x%08x\n" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr " despl symvec : 0x%08x\n" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr " name : %.*s\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "SYM - Definición de símbolo global\n" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr " opciones: 0x%04x" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr " despl psect: 0x%08x\n" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr " dirección código: 0x%08x\n" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr " índice psect para punto de entrada : %u\n" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr " índice psect : %u\n" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr " nombre : %.*s\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "SYM - Referencia de símbolo global\n" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "IDC - Revisor de Consistencia de Identación\n" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr " opciones : 0x%08x" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr " coinc id : %x\n" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr " severidad err : %x\n" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr " nombre entidad: %.*s\n" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr " nombre objeto : %.*s\n" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr " ident binaria : 0x%08x\n" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr " ident ascii : %.*s\n" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "SYMG - Definición de símbolo universal\n" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr " despl vector símbolo: 0x%08x\n" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr " punto de entrada: 0x%08x\n" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr " descr proc : 0x%08x\n" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr " índice psect: %u\n" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "SYMV - Definición de símbolo vectorizado\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr " vector : 0x%08x\n" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr " despl psect : %u\n" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "SYMM - Definición de símbolo global con versión\n" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr " máscara versión: 0x%08x\n" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "tipo de entrada egsd %u sin manejar\n" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr " índice enlace: %u, insn reemplazo: 0x%08x\n" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr " ind psect 1: %u, despl 1: 0x%08x %08x\n" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr " ind psect 2: %u, despl 2: 0x%08x %08x\n" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr " ind psect 3: %u, despl 3: 0x%08x %08x\n" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr " nombre global: %.*s\n" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr " %s (lon=%u+%u):\n" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr " (tipo: %3u, tam: 4+%3u): " + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "STA_GBL (pila global) %.*s\n" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "STA_LW (pila longword) 0x%08x\n" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "STA_QW (pila quadword) 0x%08x %08x\n" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "STA_PQ (pila psect base + despl)\n" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr " psect: %u, despl: 0x%08x %08x\n" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "STA_LI (pila literal)\n" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "STA_MOD (pila módulo)\n" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "STA_CKARG (compara argumentos de procedimientos)\n" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "STO_B (almacena byte)\n" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "STO_W (almacena word)\n" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "STO_LW (almacena longword)\n" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "STO_QW (almacena quadword)\n" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "STO_IMMR (almacena inmediato repetido) %u bytes\n" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "STO_GBL (almacena global) %.*s\n" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "STO_CA (almacena direcc código) %.*s\n" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "STO_RB (almacena ramif relativa)\n" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "STO_AB (almacena ramif absoluta)\n" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "STO_OFF (almacena despl para psect)\n" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "STO_IMM (almacena inmediato) %u bytes\n" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "STO_GBL_LW (almacena global longword) %.*s\n" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "STO_OFF (almacena LP con firma de procedimiento)\n" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "STO_BR_GBL (almacena ramif global) *pend*\n" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "STO_BR_PS (almacena ramif psect + despl) *pend*\n" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "OPR_NOP (no operación)\n" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "OPR_ADD (adición)\n" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "OPR_SUB (sustracción)\n" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "OPR_MUL (multiplicación)\n" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "OPR_DIV (división)\n" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "OPR_AND (and lógico)\n" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "OPR_IOR (or lógico inclusivo)\n" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "OPR_EOR (or lógico exclusivo)\n" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "OPR_NEG (negación)\n" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "OPR_COM (complemento)\n" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "OPR_INSV (insertar campo)\n" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "OPR_ASH (despl aritmético)\n" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "OPR_USH (despl sin signo)\n" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "OPR_ROT (rotación)\n" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "OPR_SEL (selección)\n" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "OPR_REDEF (redefine símbolo a la ubicación actual)\n" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "OPR_REDEF (define una literal)\n" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "STC_LP (almacena par de enlace cond)\n" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "STC_LP_PSB (almacena par de enlace cond + firma)\n" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr " índice enlace: %u, procedimiento: %.*s\n" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr " firma: %.*s\n" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "STC_GBL (almacena cond global)\n" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr " índice enlace: %u, global: %.*s\n" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "STC_GCA (almacena dirección de código cond)\n" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr " índice enlace: %u, nombre procedimiento: %.*s\n" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "STC_PS (almacena psect cond + despl)\n" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr " índice enlace: %u, psect: %u, despl: 0x%08x %08x\n" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "STC_NOP_GBL (almacena NOP cond en dirección global)\n" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "STC_NOP_PS (almacena NOP cond en psect + despl)\n" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "STC_BSR_GBL (almacena BSR cond en dirección global)\n" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "STC_BSR_PS (almacena BSR cond en psect + despl)\n" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "STC_LDA_GBL (almacena LDA cond en dirección global)\n" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "STC_LDA_PS (almacena LDA cond en psect + despl)\n" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "STC_BOH_GBL (almacena BOH cond en dirección global)\n" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "STC_BOH_PS (almacena BOH cond en psect + despl)\n" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "STC_NBH_GBL (almacena cond o pista en dirección global)\n" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "STC_NBH_PS (almacena cond o pista en psect + despl)\n" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "CTL_SETRB (define base de reubicación)\n" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "CTL_AUGRB (aumenta base de reubicación) %u\n" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "CTL_DFLOC (define ubicación)\n" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "CTL_STLOC (establece ubicación)\n" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "CTL_STKDL (ubicación definida de pila)\n" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "*sin manejar*\n" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "no se puede leer la longitud del registro GST\n" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "no se puede encontrar EMH en el primer registro GST\n" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "no se puede leer el encabezado del registro GST\n" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr " GST corrupto\n" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "no se puede leer el registro GST\n" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr " tipo de registro EOBJ %u sin manejar\n" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr " cuenta bit: %u, direcc base: 0x%08x\n" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr " mapa bit: 0x%08x (cuenta: %u):\n" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr " %08x" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr " imagen %u (%u entradas)\n" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr " despl: 0x%08x, val: 0x%08x\n" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr " imagen %u (%u entradas), desplazamientos:\n" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr " 0x%08x" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "64 bits *sin manejar*\n" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "clase: %u, tipod: %u, long: %u, puntero: 0x%08x\n" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "matriz no contigua de %s\n" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "dimct: %u, aops: 0x%02x, dígitos: %u, escala: %u\n" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "artam: %u, a0: 0x%08x\n" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "Estribos:\n" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "[%u]: %u\n" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "Límites:\n" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "[%u]: Inferior: %u, superior: %u\n" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "cadena de bit sin alinear de %s\n" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "base: %u, pos: %u\n" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "vops: 0x%02x, valor: 0x%08x " + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "(sin valor)\n" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "(no activo)\n" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "(sin ubicar)\n" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "(descriptor)\n" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "(valor restante)\n" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "(valor spec a continuación)\n" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "(en el despl de bit %u)\n" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "(reg: %u, disp: %u, indir: %u, género: " + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "literal" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "dirección" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "desc" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "reg" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "Tabla de símbolos de depuración:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "no se puede leer el encabezado DST\n" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr " tipo: %3u, lon: %3u (en 0x%08x): " + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "no se puede leer el símbolo DST\n" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "datos estándar: %s\n" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr " nombre: %.*s\n" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "modini\n" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr " ops: %d, lenguaje: %u, mayor: %u, menor: %u\n" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr " nom módulo : %.*s\n" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr " compilador : %.*s\n" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "modfin\n" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "rtnini\n" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr " ops: %u, dirección: 0x%08x, direcc-pd: 0x%08x\n" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr " nom rutina : %.*s\n" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "rtnfin: tam 0x%08x\n" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "prolog: dirección bkpt 0x%08x\n" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "epilog: ops: %u, cuenta: %u\n" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "blkini: dirección: 0x%08x, nombre: %.*s\n" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "blkfin: tam: 0x%08x\n" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "espectip (lon: %u)\n" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "septip, nombre: %.*s\n" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "recini: nombre: %.*s\n" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "recfin\n" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "enuini, lon: %u, nombre: %.*s\n" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "enufin, nombre: %.*s\n" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "enufin\n" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "rango discontinuo (nbr: %u)\n" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr " dirección: 0x%08x, tamaño: %u\n" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "num línea (lon: %u)\n" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "delta_pc_w %u\n" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "incr_linum(b): +%u\n" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "incr_linum_w: +%u\n" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "incr_linum_l: +%u\n" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "set_line_num(w) %u\n" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "set_line_num_b %u\n" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "set_line_num_l %u\n" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "set_abs_pc: 0x%08x\n" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "delta_pc_l: +0x%08x\n" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "term(b): 0x%02x" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "term_w: 0x%04x" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "delta pc +%-4d" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr " pc: 0x%08x línea: %5u\n" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *sin manejar* ord %u\n" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "fuente (lon: %u)\n" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr " declfich: lon: %u, ops: %u, fichid: %u\n" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr " nomfichero : %.*s\n" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr " setfile %u\n" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr " setrect %u\n" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr " setlnum %u\n" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr " deflines %u\n" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr " alimforma\n" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *sin manejar* ord %u\n" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "tipo dst %u *sin manejar*\n" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "no se puede leer EIHD\n" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "EIHD: (tamaño: %u, bloques nbr: %u)\n" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr " idmayor: %u, idmenor: %u\n" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "ejecutable" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "imagen enlazable" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr " tipo imagen: %u (%s)" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "nativa" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "CLI" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr ", subtipo: %u (%s)\n" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr " despls: isd: %u, activ: %u, simdep: %u, idimg: %u, parche: %u\n" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr " info compos rva: " + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr " vector símbolo rva: " + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" +"\n" +" matriz versión despl: %u\n" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr " cuenta I/O img: %u, canales nbr: %u, pri req: %08x%08x\n" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr " opciones de enlazador: %08x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr " ident: 0x%08x, versis: 0x%08x, ctrl coinc: %u, tam_vectsim: %u\n" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr " BPAGE: %u" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr ", ext comp despl: %u, no_opt desp psect: %u" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr ", alias: %u\n" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "información de matriz de versión de sistema:\n" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "no se puede leer el encabezado EIHVN\n" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "no se puede leer la versión EIHVN\n" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr " %02u " + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "IMAGEN_BASE " + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "ADMIN_MEMORIA" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "ES " + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "VOL_FICHEROS " + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "CALEND_PROCESOS " + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "GENSIS " + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "ADMBLOQ_CLUSTERS " + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "NOMBRES_LOGICOS " + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "SEGURIDAD " + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "ACTIVADOR_IMAGEN " + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "REDES " + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "CONTADORES " + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "ESTABLE " + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "MISC " + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "CPU " + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "VOLÁTIL " + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "SHELL " + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "POSIX " + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "MULTI_PROCESAM " + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "GALAXIA " + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "*desconocido* " + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr ": %u.%u\n" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "no se puede leer EIHA\n" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "Activa imagen : (tamaño=%u)\n" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr " Primera direcc: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr " Segunda direcc: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr " Tercera direcc: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr " Cuarta direcc : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr " Imagen compar : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "no se puede leer EIHI\n" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "Identificación de imagen: (mayor: %u, menor: %u)\n" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr " nombre de imagen : %.*s\n" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr " hora enlazado : %s\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr " ident imagen : %.*s\n" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr " ident enlazador : %.*s\n" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr " ident const imagen: %.*s\n" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "no se puede leer EIHS\n" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "Símbolo de imagen y tabla de depuración: (mayor: %u, menor %u)\n" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr " tabla de símbolos de depuración : vbn: %u, tam: %u (0x%x)\n" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr " tabla de símbolos globales : vbn: %u, registros: %u\n" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr " tabla de módulo de depuración : vbn: %u, tam: %u\n" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "no se puede leer EISD\n" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "Descriptor de sección de imagen: (mayor: %u, menor: %u, tam: %u, despl: %u)\n" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr " sección: base: 0x%08x%08x tam: 0x%08x\n" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr " opciones: %04x" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr " vbn: %u, pfc: %u, coincctl: %u tipo: %u (" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "NORMAL" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "SHRFXD" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "PRVFXD" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "SHRPIC" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "PRVPIC" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "USRSTACK" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr " ident: 0x%08x, nombre: %.*s\n" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "no se puede leer DMT\n" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "Tabla de módulos de depuración\n" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "no se puede leer el encabezado DMT\n" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr " despl módulo: 0x%08x, tam: 0x%08x, (%u psects)\n" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "no se puede leer el psect DMT\n" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr " psect inicio: 0x%08x, long: %u\n" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "no se puede leer DST\n" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "no se puede leer GST\n" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "Tabla de símbolos global:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "Compostura de activador de imagen: (mayor: %u, menor: %u)\n" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr " iafenl : 0x%08x %08x\n" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr " compenl : 0x%08x %08x\n" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr " tam : %u\n" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr " ops : 0x%08x\n" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr " qrelfixoff: %5u, lrelfixoff: %5u\n" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr " qdotadroff: %5u, ldotadroff: %5u\n" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr " codeadroff: %5u, lpfixoff : %5u\n" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr " chgprtoff : %5u\n" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr " shlstoff : %5u, shrimgcnt : %5u\n" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr " shlextra : %5u, permctx : %5u\n" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr " base_va : 0x%08x\n" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr " lppsbfixoff: %5u\n" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr " Imágenes compartibles:\n" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr " %u: tam: %u, opts: 0x%02x, nombre: %.*s\n" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr " composturas de reubicación quad-word:\n" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr " composturas de reubicación long-word:\n" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr " composturas de referencia .address quad-word:\n" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr " composturas de referencia .address long-word:\n" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr " Composturas de Referencias de Dirección de Código:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr " Composturas de Referencias de Pares de Enlazado\n" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr " Cambiar Protección (%u entradas):\n" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr " base: 0x%08x %08x, tam: 0x%08x, prot: 0x%08x " + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "%P: no se admite el enlace reubicable\n" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "%P: puntos de entrada múltiples: en los módulos %B y %B\n" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "no se puede abrir la imagen compartida '%s' desde '%s'" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "se llamó _bfd_vms_output_counted con cero bytes" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "se llamó _bfd_vms_output_counted con demasiados bytes" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: objeto compartido XCOFF cuando no se produce salida XCOFF" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: objeto dinámico sin sección .loader" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: `%s' tiene números de línea pero no una sección contenedora" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: clase %d símbolo `%s' no tiene entradas auxiliares" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: el símbolo `%s' tiene un tipo csect %d que no se reconoce" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: símbolo XTY_ER `%s' erróneo: clase %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: símbolo XMC_TCO `%s' es clase %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect `%s' no está contenido en una sección" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: XTY_LD `%s' mal ubicado" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: la reubicación %s:%d no está en csect" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: no hay tal símbolo" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "aviso: se intenta exportar el símbolo sin definir `%s'" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "error: símbolo __rtinit sin definir" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: reubicación del cargador en la sección `%s' que no se reconoce" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: `%s' en la reubicación del cargador pero no es un símbolo del cargador" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: reubicación del cargador en la sección de sólo lectura %A" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "Desbordamiento de TOC: 0x%lx > 0x10000; pruebe -mminimal-toc al compilar" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: No se puede relajar br en 0x%lx en la sección `%A'. Por favor use brl o ramificación indirecta." + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "reubicación @pltoff contra un símbolo local" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: segmento de datos short desbordado (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp no cubre el segmento de datos short" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: código que no es pic con reubicación imm contra el símbolo dinámico %s" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: reubicación @gprel contra el símbolo dinámico %s" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: se enlaza código que no es pic en un ejecutable independiente de posición" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: ramificación @internal al símbolo dinámico %s" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: compostura de especulación al símbolo dinámico %s" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: reubicación @pcrel contra el símbolo dinámico %s" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "no se admite la reubicación" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: falta la sección TLS para la reubicación %s contra `%s' en 0x%lx en la sección `%A'." + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: No se puede relajar br (%s) a `%s' en 0x%lx en la sección `%A' con tamaño 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: se enlaza deferencias-captura-en-NULL con ficheros que no son de captura" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: se enlazan ficheros big-endian con ficheros little-endian" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: se enlazan ficheros de 64-bit con ficheros de 32-bit" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: se enlazan ficheros de gp constante con ficheros con gp no constante" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: se enlazan ficheros de pic automático con ficheros sin pic automático" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: desbordamiento de número de línea: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Directorio de Exportación [.edata (o donde quiera que se encuentre)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Directorio de Importación [partes de .idata]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "Directorio de Recursos [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "Directorio de Excepciones [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "Directorio de Seguridad" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "Directorio de Reubicación Base [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "Directorio de Depuración" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "Directorio de Descripciones" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "Directorio Especial" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "Directorio de Almacenamiento de Hilos [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "Directorio de Carga de Configuraciones" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "Directorio de Importación de Relaciones" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "Directorio de Tablas de Direcciones de Importación" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "Directorio de Retardo de Importación" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "Encabezado de Tiempo de Ejecución CLR" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "Reservado" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Hay una tabla de importación, pero no se puede encontrar la sección que la contiene\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Hay una tabla de importación en %s en 0x%lx\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Se localizó el descriptor de función en la dirección de inicio: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcódigo-base %08lx tabla-de-contenidos (cargable/actual) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"¡No está la sección reldata! No se decodificó el descriptor de función.\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Las Tablas de Importación (se interpretaron los contenidos de la sección %s)\n" + +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Pista Fecha Adelante DLL Primero\n" +" Tabla Estampa Cadena Nombre Thunk\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tNombre de la DLL: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Pista/Ord Nombre-Miembro Unido-A\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Hay un thunk inicial, pero no se puede encontrar la sección que lo contiene\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Hay una tabla de exportación, pero no se puede encontrar la sección que la contiene\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Hay una tabla de exportación en %s, pero no cabe en esa sección\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Hay una tabla de exportación en %s en 0x%lx\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Las Tablas de Exportación (se interpretaron los contenidos de la sección %s)\n" +"\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Opciones de Exportación \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "marca de Hora/Fecha \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Mayor/Menor \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Nombre \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Base Ordinal \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "Número en:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tTabla de Exportación de Direcciones \t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\tTabla [Nombre Puntero/Ordinal]\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "Direcciones de la Tabla\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tTabla de Exportación de Direcciones \t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tNombre de la Tabla de Punteros \t\t" + +# continuar aqui +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tTabla Ordinal \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Tabla de Exportación de Direcciones -- Base Ordinal %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "RVA Adelantador" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "RVA Exportador" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"Tabla [Puntero a Ordinal/Nombre]\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Aviso, el tamaño de la sección .pdata (%ld) no es un múltiplo de %d\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tDirección Inicio Dirección Fin Información Desenvuelta\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tInicio Fin EH EH FinPrólogo Excepción\n" +" \t\tDirecc Direcc Asa Datos Dirección Máscara\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " Registro para guardar milicódigo" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " Registro para restaurar milicódigo" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " Secuencia de código pegamento" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tInicio Prólogo Función Opciones Excepción EH\n" +" \t\tDirecc Longitud Longitud 32b exc Manejador Datos\n" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Reubicaciones de Fichero Base PE (se interpretaron los contenidos de la sección .reloc)\n" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Dirección Virtual: %08lx Tamaño del trozo %ld (0x%lx) Número de composturas %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\treubicación %4d desplazamiento %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Características 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: no se puede llenar DataDictionary[1] porque falta .idata$2" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: no se puede llenar DataDictionary[1] porque falta .idata$4" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: no se puede llenar DataDictionary[12] porque falta .idata$5" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: no se puede llenar DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] porque falta .idata$6" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "%B: no se puede llenar DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] porque falta .idata$6" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: no se puede llenar DataDictionary[9] porque falta __tls_used" + +#~ msgid "Can't Make it a Short Jump" +#~ msgstr "No se Puede Convertir en un Salto Corto" + +#~ msgid "Exceeds Long Jump Range" +#~ msgstr "Excede el Rango de Salto Largo" + +#~ msgid "Absolute address Exceeds 16 bit Range" +#~ msgstr "La dirección Absoluta Excede el Rango de 16 bit" + +#~ msgid "Absolute address Exceeds 8 bit Range" +#~ msgstr "La dirección Absoluta Excede el Rango de 8 bit" + +#~ msgid "Unrecognized Reloc Type" +#~ msgstr "No se reconoce el Tipo de Reubicación" + +#~ msgid "corrupt or empty %s section in %B" +#~ msgstr "sección %s corrupta o vacía en %B" + +#~ msgid "%s: invalid DSO for symbol `%s' definition" +#~ msgstr "%s: DSO inválido para la definición del símbolo `%s'" + +#~ msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%B: %A+0x%lx: salto a una rutina cabo la cual no es jal" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "bfd_make_section (%s) falló" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) falló" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "No coincide el tamaño de la sección %s=%lx, %s=%lx" + +#~ msgid "failed to enter %s" +#~ msgstr "falló la introducción de %s" + +#~ msgid "No Mem !" +#~ msgstr "¡ No hay Memoria !" + +#~ msgid "reserved STO cmd %d" +#~ msgstr "orden STO %d reservada" + +#~ msgid "reserved OPR cmd %d" +#~ msgstr "orden OPR %d reservada" + +#~ msgid "reserved CTL cmd %d" +#~ msgstr "orden CTL %d reservada" + +#~ msgid "reserved STC cmd %d" +#~ msgstr "orden STC %d reservada" + +#~ msgid "stack-from-image not implemented" +#~ msgstr "pila-desde-imagen sin implementar" + +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "pila-máscara-entrada no está completamente implementado" + +#~ msgid "PASSMECH not fully implemented" +#~ msgstr "PASSMECH no está completamente implementado" + +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "pila-símbolo-local no está completamente implementado" + +#~ msgid "stack-literal not fully implemented" +#~ msgstr "pila-literal no está completamente implementado" + +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "pila-símbolo-local-máscara-punto-entrada no está completamente implementado" + +#~ msgid "%s: not fully implemented" +#~ msgstr "%s: no está completamente implementado" + +#~ msgid "obj code %d not found" +#~ msgstr "no se encontró el código objeto %d" + +#~ msgid "Reloc size error in section %s" +#~ msgstr "Error del tamaño de reubicación en la sección %s" + +#~ msgid "ERROR: %B: Incompatible object tag '%s':%d" +#~ msgstr "ERROR: %B: Etiqueta de objeto '%s' incompatible:%d" + +#~ msgid "%B(%A): warning: unresolvable relocation against symbol `%s'" +#~ msgstr "%B(%A): aviso: reubicación sin resolución contra el símbolo `%s'" + +#~ msgid "%B: Internal inconsistency; no relocation section %s" +#~ msgstr "%B: Inconsistencia interna; no se encuentra la sección de reubicación %s" + +#~ msgid "Could not find relocation section for %s" +#~ msgstr "No se puede encontrar la sección de reubicación para %s" + +#~ msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d" +#~ msgstr "%B desbordamiento de GOT: Número de reubicaciones R_68K_GOT80 Y R_68K_GOT160 > %d" + +#~ msgid "%A link_order not found\n" +#~ msgstr "no se encontró link_order %A\n" + +#~ msgid "%s: no symbol \"%s\"" +#~ msgstr "%s: no existe el símbolo \"%s\"" + +#~ msgid "%s: loader reloc in unrecognized section `%s'" +#~ msgstr "%s: reubicación del cargador en la sección `%s' no reconocida" + +#~ msgid "%s: `%s' in loader reloc but not loader sym" +#~ msgstr "%s: `%s' en la reubicación del cargador pero no es un símbolo del cargador" + +#~ msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +#~ msgstr "Error de Dwarf: El desplazamiento DW_FROM_strp (%lu) es más grande o igual que el tamaño de .debug_str (%lu)." + +#~ msgid "Dwarf Error: Can't find .debug_abbrev section." +#~ msgstr "Error de Dwarf: No se puede encontrar la sección .debug_abbrev." + +#~ msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +#~ msgstr "Error de Dwarf: El desplazamiento de abreviatura (%lu) es más grande o igual que el tamaño de .debug_abbrev (%lu)." + +#~ msgid "Dwarf Error: Can't find .debug_ranges section." +#~ msgstr "Error de Dwarf: No se puede encontrar lan sección .debug_ranges." + +#~ msgid "ERROR: %B: Conflicting definitions of wchar_t" +#~ msgstr "ERROR: %B: Definiciones en conflicto de wchar_t" + +#~ msgid "%B: relocation R_X86_64_PC32 against protected function `%s' can not be used when making a shared object" +#~ msgstr "%B: no se puede usar la reubicación R_X86_64_PC32 contra la función protegida `%' cuando se hace un objeto compartido" + +#~ msgid "ERROR: %B: Conflicting enum sizes" +#~ msgstr "ERROR: %B: Tamaños de enum en conflicto" + +#~ msgid "Division by zero. " +#~ msgstr "División por cero. " + +#~ msgid " [cpu32]" +#~ msgstr " [cpu32]" + +#~ msgid " [m68000]" +#~ msgstr " [m68000]" + +#~ msgid "Linking mips16 objects into %s format is not supported" +#~ msgstr "No se admite enlazar objetos mips16 en el formato %s" + +#~ msgid ".glink and .plt too far apart" +#~ msgstr ".glink y .plt están demasiado alejados" + +#~ msgid "%B: Not enough room for program headers (allocated %u, need %u)" +#~ msgstr "%B: No hay suficiente espacio para los encabezados del programa (%u asignados, %u necesarios)" + +#~ msgid " [mips1]" +#~ msgstr " [mips1]" + +#~ msgid " [mips2]" +#~ msgstr " [mips2]" + +#~ msgid " [mips3]" +#~ msgstr " [mips3]" + +#~ msgid " [mips4]" +#~ msgstr " [mips4]" + +#~ msgid " [mips5]" +#~ msgstr " [mips5]" + +#~ msgid " [mips32]" +#~ msgstr " [mips32]" + +#~ msgid " [mips64]" +#~ msgstr " [mips64]" + +#~ msgid " [mips32r2]" +#~ msgstr " [mips32r2]" + +#~ msgid " [mips64r2]" +#~ msgstr " [mips64r2]" + +#~ msgid " [mdmx]" +#~ msgstr " [mdmx]" + +#~ msgid " [mips16]" +#~ msgstr " [mips16]" + +#~ msgid " [32bitmode]" +#~ msgstr " [modo 32bit]" + +#~ msgid "Missing IHCONST" +#~ msgstr "IHCONST faltante" + +#~ msgid "Missing IHIHALF" +#~ msgstr "IHIHALF faltante" + +#~ msgid "missing IHCONST reloc" +#~ msgstr "reubicación IHCONST faltante" + +#~ msgid "missing IHIHALF reloc" +#~ msgstr "reubicación IHIHALF faltante" + +#~ msgid "%B(%A): warning: unresolvable relocation %d against symbol `%s'" +#~ msgstr "%B(%A): aviso: reubicación %d sin resolución contra el símbolo `%s'" + +#~ msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +#~ msgstr "%s: aviso: reubicación sin resolución contra el símbolo `%s' de la sección %s" + +#~ msgid "%B(%A): unresolvable relocation against symbol `%s'" +#~ msgstr "%B(%A+0x%lx): reubicación sin resolución contra el símbolo `%s'" + +#~ msgid "Symbol %s has no GOT subsection for offset 0x%x" +#~ msgstr "El símbolo %s no tiene subsección GOT para el desplazamiento 0x%x" + +#~ msgid "%B: check_relocs: unhandled reloc type %d" +#~ msgstr "%B: check_relocs: tipo de reubicación %d sin manejar" + +#~ msgid "%B: warning: sh_link not set for section `%S'" +#~ msgstr "%B: aviso: no se estableció sh_link para la sección `%S'" + +#~ msgid " first occurrence: %s: arm call to thumb" +#~ msgstr " primera ocurrencia: %s: llamada arm a thumb" + +#~ msgid " first occurrence: %s: thumb call to arm" +#~ msgstr " primera ocurrencia: %s: llamada thumb a arm" + +#~ msgid " consider relinking with --support-old-code enabled" +#~ msgstr " considere el reenlace con --support-old-code activado" + +#~ msgid "reloc against unsupported section" +#~ msgstr "reubicación contra una sección no admitida" + +#~ msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +#~ msgstr "Error: La primera sección en el segmento (%s) inicia en 0x%x mientras que el segmento inicia en 0x%x" + +#~ msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +#~ msgstr "ERROR: %s está compilado para EABI versión %d, mientras que %s está compilado para la versión %d" + +#~ msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +#~ msgstr "%s: reubicación %s sin resolución contra el símbolo `%s' de la sección %s" + +#~ msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +#~ msgstr "%s: no se debe usar la reubicación %s cuando se hace un objeto compartido; recompile con -fPIC" + +#~ msgid "%s(%s+0x%lx): fixing %s" +#~ msgstr "%s(%s+0x%lx): fijando %s" + +#~ msgid "%s: unresolvable relocation against symbol `%s' from %s section" +#~ msgstr "%s: reubicación sin resolución contra el símbolo `%s' de la sección %s" + +#~ msgid "%s: linking non-pic code in a shared library" +#~ msgstr "%s: se enlaza código que no es pic en una biblioteca compartida" + +#~ msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +#~ msgstr "%s: desbordamiento de reubicación 1: 0x%lx > 0xffff" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Tipo de enlazador especial %d desconocido" + +#~ msgid "v850ea architecture" +#~ msgstr "arquitectura v850ea" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: La sección %s es muy grande para agregar un agujero de %ld bytes" + +#~ msgid "Error: out of memory" +#~ msgstr "Error: memoria agotada" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "aviso: reubicación contra una sección eliminada; se cambia a ceros" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "símbolos locales en la sección descartada %s" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: no coincide el ISA (-mips%d) con módulos previos (-mips%d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: no coincide el ISA (%d) con módulos previos (%d)" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: reubicación dinámica contra una compostura de especulación" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: compostura de especulación contra un símbolo débil indefinido" + +#~ msgid "\tThe Import Address Table (difference found)\n" +#~ msgstr "\tLa Tabla de Importación de Direcciones (se encontró una diferencia)\n" + +#~ msgid "\t>>> Ran out of IAT members!\n" +#~ msgstr "\t>>> ¡Se terminaron los miembros IAT!\n" + +#~ msgid "\tThe Import Address Table is identical\n" +#~ msgstr "\tLa Tabla de Importación de Direcciones es idéntica\n" + +#~ msgid "GP relative relocation when GP not defined" +#~ msgstr "reubicación GP relativa cuando GP no estaba definido" + +#~ msgid "%s: ERROR: passes floats in float registers whereas target %s uses integer registers" +#~ msgstr "%s: ERROR: pasan números de coma flotante en registros de coma flotante mientras que el objetivo %s usa registros enteros" + +#~ msgid "%s: ERROR: passes floats in integer registers whereas target %s uses float registers" +#~ msgstr "%s: ERROR: pasan números de coma flotante en registros enteros mientras que el objetivo %s usa registros de coma flotante" + +#~ msgid "Warning: input file %s supports interworking, whereas %s does not." +#~ msgstr "Aviso: el fichero de entrada %s admite interoperabilidad, mientras que %s no." + +#~ msgid "Warning: input file %s does not support interworking, whereas %s does." +#~ msgstr "Aviso: el fichero de entrada %s no admite interoperabilidad, mientras que %s sí." + +# FIXME: Revisar en el código si son abreviaturas comunes, o corresponden a +# partes fijas dentro del programa. cfuga +#~ msgid "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" +#~ msgstr "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" + +#~ msgid "elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = 0x%.8lx%s\n" +#~ msgstr "elf_symbol_from_bfd_symbol 0x%.8lx, nombre = %s, núm sim = %d, opciones = 0x%.8lx%s\n" + +#~ msgid "Warning: Not setting interwork flag of %s since it has already been specified as non-interworking" +#~ msgstr "Aviso: No se activa la opción de interoperación de %s ya que se había especificado como no interoperable" + +#~ msgid "Warning: Clearing the interwork flag of %s due to outside request" +#~ msgstr "Aviso: Se limpia la opción de interoperación de %s debido a una petición externa" + +#~ msgid " [APCS-26]" +#~ msgstr " [APCS-26]" + +#~ msgid " [APCS-32]" +#~ msgstr " [APCS-32]" + +#~ msgid "(unknown)" +#~ msgstr "(desconocido)" + +#~ msgid " previously %s in %s" +#~ msgstr " previamente %s en %s" + +#~ msgid "Symbol `%s' has differing types: %s in %s" +#~ msgstr "El símbolo `%s' tiene tipos diferentes: %s en %s" + +#~ msgid "ETIR_S_C_STO_GBL: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_GBL: no está el símbolo \"%s\"" + +#~ msgid "ETIR_S_C_STO_CA: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_CA: no está el símbolo \"%s\"" + +#~ msgid "ETIR_S_C_STO_RB/AB: Not supported" +#~ msgstr "ETIR_S_C_STO_RB/AB: No se admite" + +#~ msgid "ETIR_S_C_STO_LP_PSB: Not supported" +#~ msgstr "ETIR_S_C_STO_LP_PSB: No se admite" + +#~ msgid "ETIR_S_C_OPR_INSV: Not supported" +#~ msgstr "ETIR_S_C_OPR_INSV: No se admite" + +#~ msgid "ETIR_S_C_OPR_USH: Not supported" +#~ msgstr "ETIR_S_C_OPR_USH: No se admite" + +#~ msgid "ETIR_S_C_OPR_ROT: Not supported" +#~ msgstr "ETIR_S_C_OPR_ROT: No se admite" + +#~ msgid "ETIR_S_C_OPR_REDEF: Not supported" +#~ msgstr "ETIR_S_C_OPR_REDEF: No se admite" + +#~ msgid "ETIR_S_C_OPR_DFLIT: Not supported" +#~ msgstr "ETIR_S_C_OPR_DFLIT: No se admite" + +#~ msgid "ETIR_S_C_STC_LP: not supported" +#~ msgstr "ETIR_S_C_STC_LP: no se admite" + +#~ msgid "ETIR_S_C_STC_GBL: not supported" +#~ msgstr "ETIR_S_C_STC_GBL: no se admite" + +#~ msgid "ETIR_S_C_STC_GCA: not supported" +#~ msgstr "ETIR_S_C_STC_GCA: no se admite" + +#~ msgid "ETIR_S_C_STC_PS: not supported" +#~ msgstr "ETIR_S_C_STC_PS: no se admite" + +#~ msgid "Unimplemented STO cmd %d" +#~ msgstr "Orden STO %d sin implementar" + +#~ msgid "TIR_S_C_OPR_ASH incomplete" +#~ msgstr "TIR_S_C_OPR_ASH incompleto" + +#~ msgid "TIR_S_C_OPR_USH incomplete" +#~ msgstr "TIR_S_C_OPR_USH incompleto" + +#~ msgid "TIR_S_C_OPR_ROT incomplete" +#~ msgstr "TIR_S_C_OPR_ROT incompleto" + +#~ msgid "TIR_S_C_OPR_REDEF not supported" +#~ msgstr "TIR_S_C_OPR_REDEF no se admite" + +#~ msgid "TIR_S_C_OPR_DFLIT not supported" +#~ msgstr "TIR_S_C_OPR_DFLIT no se admite" + +#~ msgid "TIR_S_C_CTL_DFLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_DFLOC no está completamente implementado" + +#~ msgid "TIR_S_C_CTL_STLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_STLOC no está completamente implementado" + +#~ msgid "TIR_S_C_CTL_STKDL not fully implemented" +#~ msgstr "TIR_S_C_CTL_STKDL no está completamente implementado" + +#~ msgid " vma: Hint Time Forward DLL First\n" +#~ msgstr " vma: Pista Tiempo Adelante DLL Primero\n" + +#~ msgid " \t\tAddress Address Handler Data Address Mask\n" +#~ msgstr " \t\tDirección Dirección Manejador Datos Dirección Máscara\n" + +#~ msgid "integer" +#~ msgstr "entero" + +# FIXME: Revisar el contexto en el código para confirmar esta traducción. cfuga +#~ msgid "soft" +#~ msgstr "suave" + +#~ msgid "hard" +#~ msgstr "duro" + +#~ msgid "Warning: %s %s interworking, whereas %s %s" +#~ msgstr "Aviso: %s %s interoperatibilidad, mientras que %s %s" + +#~ msgid "supports" +#~ msgstr "admite" + +#~ msgid "does not" +#~ msgstr "no" + +#~ msgid "%s(%s+0x%lx): cannot find stub entry %s" +#~ msgstr "%s(%s+0x%lx): no se puede encontrar la entrada de cabo %s" + +#~ msgid "%s(%s+0x%lx): cannot relocate %s, recompile with -ffunction-sections" +#~ msgstr "%s(%s+0x%lx): no se puede reubicar %s, recompile con -ffuncion-sections" + +#~ msgid "creating section symbol, name = %s, value = 0x%.8lx, index = %d, section = 0x%.8lx\n" +#~ msgstr "se crea el símbolo de sección, nombre = %s, valor = 0x%.8lx, índice = %d, sección 0x%.8lx\n" + +#~ msgid " whereas segment starts at 0x%x" +#~ msgstr " mientras que el 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zgCDbF3U?|1fTing#KjASo46@rrH1*FpsnQsXw!fZ%geMZdHs0V`=a*4huZRNtojD* z!(-`HO(A!9I!+PPhMftwiYBAPVVw7l;<+xGBF;3O>;uI#Q3x;(VprC~$wMEyJB`+ica2+Nzj>l`k=8rUnaM#ag| zmBIlJags6h3M$;uezX&ZPQec7t{{9ni_?d4J4XkR`y6!6fj(g?&^j|9+;`MD`Y5K9CEyV zSsag}Q@!tfLkhatn``K$t#a zfm{Lysv|MadcqM8lMH^)W@w0`tqSeEcN4rK;@U_4nPXN{^z0<}nWs!CCuBbh9*Y;S`q5r82G@njeS^9`hE&6apg3J{dO?KIHZp z7C)8`ugwc6dmV9e%`0OU?rGXiFB3Jeq>2fvYEqR^%#A7GZroBN?+=wLQF_pCzrK(9 zqEsiMr{Yzw?%jjBmk(=SUObwAJ#QfNT#Zghi^j!S_c2*mR@2?spA}p38u8J6Rul)r zpKyN%y>?uKsLSAd9BnxP2RuG^$Z+2TM z8N9$1j2<6=BDjbMX7nZ(My{0o&YoFUHVzm*6#X^O8MB8J|Qc}4H8sP>%$ns$(^f-J61vs9)`&U>oOQ0?mkS+&wxB=salh~X;noFNN~ zYXg&u5jVg!5eWWqunow&(KDu1;$S^78flKXVqSF2YRR^_to#2zI~(08KnWxSCTH OP)#F(riP8p2V5Qqk?msu literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/bfd/po/fi.po b/external/gpl3/gdb/dist/bfd/po/fi.po new file mode 100644 index 000000000000..341ca76f7763 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/fi.po @@ -0,0 +1,6157 @@ +# Finnish messages for bfd +# Copyright © 2007, 2009, 2010 Free Software Foundation, Inc. +# This file is distributed under the same license as the binutils package. +# Jorma Karvonen , 2007, 2009, 2010. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2010-11-10 18:55+0200\n" +"Last-Translator: Jorma Karvonen \n" +"Language-Team: Finnish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=2; plural=(n != 1);\n" +"X-Generator: KBabel 1.11.2\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Tuntematon lohkotyyppi â€a.out.adobeâ€-tiedostossa: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Virheellinen sijoitustyyppi viety: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Virheellinen sijoitustyyppi tuotu: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Väärä sijoitustietue tuotu: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: ei voi edustaa lohkoa ’%s’ â€a.outâ€-objektitiedostomuodossa" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: ei voi edustaa lohkoa symbolille ’%s’ â€a.outâ€-objektitiedostomuodossa" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*tuntematon*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: odottamaton sijoitustyyppi\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: sijoitettava linkki kohteesta %s kohteeseen %s ei ole tuettu" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Varoitus: arkiston kirjoitus oli hidasta: aikaleiman uudelleenkirjoitus\n" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "Luetaan arkistotiedoston muokkausaikaleima" + +# Intel coff armap +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "Kirjoitetaan päivitetty â€armapâ€-aikaleima" + +#: bfd.c:395 +msgid "No error" +msgstr "Ei virhettä" + +#: bfd.c:396 +msgid "System call error" +msgstr "Järjestelmäkutsuvirhe" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "Virheellinen bfd-kohde" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "Tiedosto väärässä muodossa" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "Arkisto-objektitiedosto väärässä muodossa" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "Virheellinen toiminta" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "Muisti loppunut" + +#: bfd.c:402 +msgid "No symbols" +msgstr "Ei symboleja" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "Arkistossa ei ole hakemistoa; lisää sellainen suorittamalla ranlib" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "Ei enää arkistoituja tiedostoja" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "Muodoltaan virheellinen arkisto" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "Tiedostomuotoa ei tunnistettu" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "Tiedostomuoto ei ole yksiselitteinen" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "Lohkossa ei ole sisältöä" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "Ei-edustava lohko tulosteessa" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "Symboli tarvitsee vianjäljityslohkon, jota ei ole" + +#: bfd.c:411 +msgid "Bad value" +msgstr "Väärä arvo" + +#: bfd.c:412 +msgid "File truncated" +msgstr "Tiedosto typistetty" + +#: bfd.c:413 +msgid "File too big" +msgstr "Tiedosto on liian iso" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "Virhe luettaessa %s: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s suoritusehto epäonnistui %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %s sisäinen virhe, keskeytetään tiedostossa %s rivillä %d funktiossa %s\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %s sisäinen virhe, keskeytetään tiedostossa %s rivillä %d\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "Ilmoita tästä virheestä.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "ei kuvausta: data=%lx kuvattu=%d\n" + +# Ilmeisesti debug_windows-ympäristömuuttuja +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "ei kuvausta: ympäristömuuttuja ei ole asetettu\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Varoitus: Kirjoitetaan lohko â€%s†valtavaan (ts. negatiiviseen) tiedostosiirrososoitteeseen 0x%lx." + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: valitsimia --relax ja -r ei saa käyttää yhdessä\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "avataan uudelleen %B: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Ei voi käsitellä tiivistettyjä Alpha-binaareja.\n" +" Käytä kääntäjälippuja, tai objZ:aa, tiivistämättömien binaarien luomiseksi." + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: tuntematon/ei-tuettu sijoitustyyppi %d" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "Yleisosoitinsuhteellista sijoitusta käytetty kun yleisosoitinta ei ole määritelty" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "käytetään useita yleisosoitinarvoja" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: ei-tuettu sijoitus: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: ei-tuettu sijoitus: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: tuntematon sijoitustyyppi %d" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: ei löydetty THUMB-vihjettä â€%s†nimelle â€%sâ€" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: ei löydetty ARM-vihjettä â€%s†nimelle â€%sâ€" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): varoitus: yhteistoimivuus vanhan koodin kanssa ei ole käytössä.\n" +" ensimmäinen esiintymä: %B: â€armâ€-kutsu thumb-koodiin" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): varoitus: yhteistoimivuus vanhan koodin kanssa ei ole käytössä.\n" +" ensimmäinen esiintymä: %B: thumb-kutsu arm-koodiin\n" +" harkitse uudelleenlinkitystä --support-old-code aktivoituna" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: virheellinen reloc-tietueosoite 0x%lx lohkossa â€%Aâ€" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: virheellinen symboli-indeksi reloc-tietueessa: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "virhe: %B on käännetty APCS-%d:lle, kun taas %B on käännetty APCS-%d:lle" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "virhe: %B välittää float-liukuluvut liukulukurekistereissa, kun taas %B välittää ne kokonaislukurekistereissa" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "virhe: %B välittää float-liukuluvut kokonaislukurekistereissa, kun taas %B välittää ne float-liukulukurekistereissa" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "virhe: %B käännetään paikkariippumattomana koodina, kun taas kohde %B on absoluuttipaikkainen" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "virhe: %B käännetään absoluuttisella paikkakoodilla, kun taas kohde %B on paikkariippumaton" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Varoitus: %B tukee yhteistoimivuutta vanhan koodin kanssa, kun taas %B ei tue" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Varoitus: %B ei tue yhteistoimivuutta vanhan koodin kanssa, kun taas %B tukee" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "yksityiset liput = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [liukuluvut välitetty liukulukurekistereissä]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [liukuluvut välitetty kokonaislukurekistereissä]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr " [paikkariippumaton]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr " [absoluuttinen paikka]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [vanhan koodin kanssa toimimisen yhteistoimivuulippua ei ole alustettu]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr " [yhteistoimivuutta vanhan koodin kanssa tuettu]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr " [yhteistoimivuutta vanhan koodin kanssa ei tueta]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Varoitus: Ei aseteta %B:n lippua yhteistoimivuudesta vanhan koodin kanssa koska se on jo määritelty ei-yhteistoimivuuskohteena" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Varoitus: %B:n yhteistoimivuuslipun nollaus johtuu ulkopuolisesta pyynnöstä" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "ei voi käsitellä â€R_MEM_INDIRECT relocâ€-tietuetta kun käytetään %s tulostetta" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Sijoitusta â€%s†ei ole vielä toteutettu\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: varoitus: virheellinen symboli-indeksi %ld relocs-tietueissa" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "epävarma kutsukäytäntö ei-COFF-symbolille" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "ei-tuettu reloc-tyyppi" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "Yleisosoitinsuhteellinen sijoitus kun â€_gp†ei ole määritelty" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "Tunnistamaton reloc-tietue" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: ei-tuettu sijoitustyyppi 0x%02x" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: â€Sisältöluettelo-relocâ€-tietue osoitteessa 0x%x symboliin â€%s†ilman sisältöluettelotulokohtaa" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: symbolissa â€%s†on tunnistamaton â€smclasâ€-arvo %d" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Tunnistamaton reloc-tyyppi 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: varoitus: virheellinen symboli-indeksi %ld relocs-tietueissa" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "ei oteta huomioon reloc-tietuetta %s\n" + +# C++-kielessä on monia tilanteita, joissa kääntäjän on lähetettävä koodia tai dataa, +# mutta se ei kykenen tunnistamaan uniikkia käännösyksikköä, mihin se tulisi lähettää. +# C++ ABI-ryhmä on pyrkinyt ratkaisemaan tämän pulman sallimalla kääntäjän lähettää vaaditut +# tiedot useisiin käännösyksiköihin, mikä sallii linkkerin poistaa kaikki muuta paitsi yhden +# kopion. Tätä ominaisuutta kutsutaan useissa olemassa olevissa toteutuksissa nimellä COMDAT. +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: varoitus: COMDAT-symboli â€%s†ei täsmää lohkonimen â€%s†kanssa" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Varoitus: Ei oteta huomioon lohkolippua IMAGE_SCN_MEM_NOT_PAGED lohkossa %s" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Lohkolippua %s (0x%x) ei oteta huomioon" + +# TI tarkoittaa luultavasti Texas Instruments +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Tunnistamaton â€TI COFFâ€-kohdetunniste â€0x%xâ€" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: reloc-tietue käyttäen ei-olemassaolevaa symboli-indeksiä: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: liian monia lohkoja (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: lohko %s: merkkijonotaulun ylitys siirrososoitteessa %ld" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: varoitus: rivinumerotaulun lukeminen ei onnistunut" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: varoitus: virheellinen symboli-indeksi %ld rivinumeroissa" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: varoitus: rivinumerojen kaksoiskappaleita symbolille â€%sâ€" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: Tunnistamaton tallennusluokka: %d lohkonimi: %s symbolinimi: â€%sâ€" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "varoitus: %B: paikallisessa symbolissa â€%s†ei ole lohkoa" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: virheellinen sijoitustyyppi %d osoitteessa 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: virheellinen merkkijonotaulukoko %lu" + +# Epäilen, että lähdekoodissa on virhe: tyypit ovat kaksi viimeistä parametriä. +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Varoitus: symbolityyppi â€%s†vaihtui tyypistä %d tyyppiin %d kohteessa %B" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: relocs-tietueet lohkossa â€%Aâ€, mutta ilman sisältöä" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: reloc-tietueylivuoto: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: varoitus: %s: rivinumeroylivuoto: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "virhe: %B on käännetty EP9312:lle, kun taas %B on käännetty XScalelle" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "varoitus: ei voi päivittää %s-lohkon sisältöä kohteessa %s" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Dwarf-virhe: Ei löydy %s-lohkoa." + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Dwarf-virhe: Siirrososoite (%lu) suurempi tai yhtäsuuri kuin %s-koko (%lu)." + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf-virhe: Virheellinen tai käsittelemätön FORM-arvo: %u." + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf-virhe: runneltu rivinumerolohko (virheellinen tiedostonumero)." + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Dwarf-virhe: Käsittelemätön â€.debug_lineâ€-versio %d." + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Dwarf-virhe: Virheellinen toimintojen enimmäismäärä per käsky." + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf-virhe: runneltu rivinumerolohko." + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf-virhe: Ei löytynyt lyhennenumeroa %u." + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Dwarf-virhe: löytyi dwarf-versio ’%u’, tämä lukija käsittelee vain version 2, 3 ja 4 tietoja." + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf-virhe: löytyi osoitekoko ’%u’, tämä lukija ei voi käsitellä kokoja, jotka ovat suurempia kuin ’%u’." + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf-virhe: Väärä lyhennenumero: %u." + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "Tuntematon perustyyppi %d" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Loppu+1 symboli: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Ensimmäinen symboli: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Loppu+1 symboli: %-7ld Tyyppi: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Paikallinen symboli: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; Loppu+1 symboli: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; Loppu+1 symboli: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Loppu+1 symboli: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tyyppi: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "virhe: %B: Objektilla on toimittajakohtainen sisältö, joka on käsiteltävä ’%s’-työkaluketjulla" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "virhe: %B: Objektitunniste ’%d, %s’ ei ole yhteensopiva tunnisteen ’%d, %s’ kanssa" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: virhe kohteessa %B(%A); â€.eh_frame_hdrâ€-taulua ei luotu.\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: fde-koodaus kohteessa %B(%A) estää â€.eh_frame_hdrâ€-taulun luomisen.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: dynaamista STT_GNU_IFUNC symbolia â€%s†osoitinyhtäläisyydellä kohteessa â€%B†ei voida käyttää tekemään suoritettavaa tiedostoa; käännä uudelleen valitsimella -fPIE ja linkitä uudelleen valitsemella -pie\n" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "sisäinen virhe: â€lukualueen ulkopuolellaâ€-virhe" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "sisäinen virhe: ei-tuettu sijoitusvirhe" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "sisäinen virhe: vaarallinen virhe" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "sisäinen virhe: tuntematon virhe" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): ratkaisematon %s sijoitus symbolia â€%s†varten" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "virhe: sopimaton sijoitustyyppi jaetulle kirjastolle (unohtuiko -fpic?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "sisäinen virhe: epäilyttävää sijoitustyyppiä käytetään jaetussa kirjastossa" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "dynaaminen muuttuja â€%s†on nollakokoinen" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: virheellinen merkkijonosiirrososoite %u >= %lu lohkolle â€%sâ€" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B symbolinumero %lu viittaa puuttuvaan SHT_SYMTAB_SHNDX-lohkoon" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Rikkinäinen kokokenttä ryhmälohko-otsakkeessa: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: virheellinen SHT_GROUP-tulokohta" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: ei ryhmätietoja lohkolle %A" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: varoitus: sh_link-kenttää ei aseteta lohkolle â€%Aâ€" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%d]-kenttä lohkossa â€%A†on virheellinen" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: tuntematon [%d] lohko â€%s†ryhmässä [%s]" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: ei kyetä alustamaan tiivistystilaa lohkolle %s" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: ei kyetä alustamaan tiivistyksenpurkutilaa lohkolle %s" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Ohjelmaotsake:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Dynaaminen lohko:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Versiomäärittelyt:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Versioviitteet:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " kysytty kohteesta %s:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: virheellinen linkki %lu reloc-tietueelle %s (indeksi %u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: ei tiedä kuinka käsitellä varattua, sovelluskohtaista lohkoa â€%s†[0x%8x]" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: ei tiedä, kuinka käsitellä prosessorikohtaista lohkoa â€%s†[0x%8x]" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: ei tiedä, kuinka käsitellä käyttöjärjestelmäkohtaista lohkoa â€%s†[0x%8x]" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: ei tiedä kuinka käsitellä lohkoa â€%s†[0x%8x]" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "varoitus: lohkon â€%A†tyyppi vaihtunut tyypiksi PROGBITS" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link-lohko â€%A†osoittaa hylättyyn lohkoon â€%A†kohteessa â€%Bâ€" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link-lohko â€%A†osoittaa poistettuun lohkoon â€%A†kohteessa â€%Bâ€" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: Ensimmäinen lohko PT_DYNAMIC-segmentissä ei ole â€.dynamicâ€-lohko" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: Ei tarpeeksi tilaa ohjelmaotsakkeille, yritä linkittää â€-Nâ€-argumentilla" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "%B: lohko %A vma %#lx säädetty kohteeseen %#lx" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: lohkoa â€%A†ei voida varata segmentissä %d" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: varoitus: varattu lohko â€%s†ei ole segmentissä" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: symboli â€%s†vaadittu, mutta ei ole annettu" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: varoitus: Tyhjä ladattava segmentti havaittu, onko tämä tarkoituksellinen ?\n" + +#: elf.c:6622 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Ei löydy samanlaista tulostelohkoa symbolille â€%s†lohkosta â€%sâ€" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: ei-tuettu sijoitustyyppi %s" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): varoitus: yhteistoimivuus vanhan koodin kanssa ei ole käytössä.\n" +" ensimmäinen esiintymä: %B: Thumb-kutsu ARM-koodiin" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): varoitus: yhteistoimivuus vanhan koodin kanssa ei ole käytössä.\n" +" ensimmäinen esiintymä: %B: ARM-kutsu Thumb-koodiin" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: ei voi luoda stub-tulokohtaa %s" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "ei löydy THUMB-vihjettä â€%s†kohteelle â€%sâ€" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "ei löydy ARM-vihjettä â€%s†kohteelle â€%sâ€" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: BE8-vedokset ovat oikeita vain big-endian-tavujärjestyksessä." + +# Vector Floating Point (VFP) +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: varoitus: valittu VFP11-virheenkiertotapa ei ole välttämätön kohdearkkitehtuurille" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: ei löydy VFP11-julkisivua â€%sâ€" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Virheellinen TARGET2-sijoitustyyppi â€%sâ€." + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): varoitus: yhteistoimivuus vanhan koodin kanssa ei ole käytössä.\n" +" ensimmäinen esiintymä: %B: thumb-kutsu arm-koodiin" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Varoitus: â€Arm BLXâ€-käskykohteet Arm-funktiossa â€%sâ€." + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Varoitus: â€Thumb BLXâ€-käskykohteet thumb-funktiossa â€%sâ€." + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_ARM_TLS_LE32-sijoitukset eivät ole sallittuja jaetuissa objekteissa" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Vain ADD- tai SUB-käskyt ovat sallittuja ALU-ryhmän sijoituksille" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Ylivuoto, kun halkaistaan 0x%lx ryhmäsijoitukselle %s" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s sijoitus SEC_MERGE-lohkoa varten" + +# TLS: transport layer security +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s käytetään TLS-symbolin %s kanssa" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s käytetään ei-TLS-symbolin %s kanssa" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "lukualueen ulkopuolella" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "ei-tuettu sijoitus" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "tuntematon virhe" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Varoitus: Nollataan %B:n vanhan koodin kanssa toimimisen yhteistoimivuuslippu, koska se on linkitetty ei-yhteistoimivuuskoodiin %B:ssa" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: Tuntematon pakollinen EABI-objektiattribuutti %d" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Varoitus: %B: Tuntematon EABI-objektiattribuutti %d" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "virhe: %B: Tuntematon prosessoriarkkitehtuuri" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "virhe: %B: Ristiriitaisia prosessoriarkkitehtuureja %d/%d" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "Virhe: kohteessa %B on sekä nykyisiä että perinne-Tag_MPextension_use-attribuutteja" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "virhe: %B käyttää VFP-rekisteriargumentteja, %B ei käytä" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "virhe: %B: ei kyetä yhdistämään virtualisointiattribuutteja kohteen %B kanssa" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "virhe: %B: Ristiriitaisia arkkitehtuuriprofiileja %c/%c" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Varoitus: %B: Ristiriitainen käyttöjärjestemäkonfiguraatio" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "virhe: %B: Ristiriitainen R9:n käyttö" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "virhe: %B: SB-suhteellinen osoitteitus on ristiriidassa R9:n käytön kanssa" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "varoitus: %B käyttää %u-tavuista wchar_t-merkkiä vaikka tuloste käyttää %u-tavuista wchar_t-merkkiä; wchart_t-käyttöarvot objekteissa saattavat olla virheellisiä" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "varoitus: %B käyttää %s enums-alkioita vaikka tuloste käyttää %s enums-alkioita; enum-arvojen käyttö objekteissa saattaa olla virheellinen" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "virhe: %B käyttää iWMMXt-rekisteriargumentteja, %B ei käytä" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "virhe: fp16-muototäsmäämättömyys kohteiden %B ja %B välillä" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "DIV-käyttötäsmäämättömyys kohteiden %B ja %B välillä" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "kohteella %B on sekä nykyisiä että perinne-Tag_MPextension_use-attribuutteja" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "yksityiset liput = %lx:" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [yhteistoimivuus vanhan koodin kanssa on käytössä]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [vektoriliukulukumuoto]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [Maverick-liukulukumuoto]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [Liukulukukiihdytin-liukulukumuoto]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [uusi ABI]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [vanha ABI]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [ohjelmistoliukuluku]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [Versio 1 EABI]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [lajiteltu symbolitaulu]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [lajittelematon symbolitaulu]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [Versio 2 EABI]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [dynaamiset symbolit käyttävät segmentti-indeksiä]" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [kuvaussymbolit ylittävät tärkeydessä muut]" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [Versio 3 EABI]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [Versio 4 EABI]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [Versio 5 EABI]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [sijoitettava suoritettava tiedosto]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [on tulokohta]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: virheellinen symboli-indeksi: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: sijoitusta %s kohdetta â€%s†varten ei voida käyttää kun tehdään jaettua objektia; käännä uudelleen -fPIC-argumentilla" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Kohdattiin virheitä prosessoitaessa tiedostoa %s" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: virhe: Cortex-A8 virhe-stub on varattu turvattomaan paikkaan" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: virhe: Cortex-A8 virhe-stub lukualueen ulkopuolella (syötetiedoston on liian iso)" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: virhe: VFP11-julkisivu lukualueen ulkopuolella" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "virhe: %B on jo lopullisessa BE8-muodossa" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "virhe: Lähdeobjektissa %B on EABI-versio %d, mutta kohteessa %B on EABI-versio %d" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "virhe: %B on käännetty APCS-%d:lle, kun taas kohde %B käyttää APCS-%d:ta" + +# Vector floating point (coprosessor) +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "virhe: %B käyttää vektoriliukulukukäskyjä, kun taas %B ei käytä" + +# Floating Point Accelerator (chip) +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "virhe: %B käyttää liukulukukiihdytinkäskyjä, kun taas %B ei käytä" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "virhe: %B käyttää Maverick-käskyjä, kun taas %B ei käytä" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "virhe: %B ei käytä Maverick-käskyjä, kun taas %B käyttää" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "virhe: %B käyttää ohjelmistoliukulukuja, kun taas %B käyttää laitteistoliukulukuja" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "virhe: %B käyttää laitteistoliukulukuja, kun taas %B käyttää ohjelmistoliukulukuja" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "sisäinen virhe: vaarallinen sijoitus" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: ei voi luoda stub-tulokohtaa %s" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): ratkaisematon sijoitus symboliin â€%sâ€" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): reloc-tietue kohdetta â€%s†varten: virhe %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: sijoitus kohteessa â€%A+0x%x†viittaa symboliin â€%sâ€, jossa on ei-nolla-yhteenlaskettava" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "sijoitusviitteet-symboli ei ole määritelty modulissa" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC viittaa dynaamiseen symboliin, jossa on ei-nolla-yhteenlaskettava" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "ei voi lähettää korjauksia kirjoitussuojattuun lohkoon" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "ei voi lähettää dynaamisia sijoituksia kirjoitussuojattussa lohkossa" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE viittaa dynaamiseen symboliin, jossa on ei-nolla-yhteenlaskettava" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "sijoituksia eri segmenttien välillä ei tueta" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "varoitus: sijoitus viittaa eri segmenttiin" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: ei-tuettu sijoitustyyppi %i" + +# The FR-V FDPIC ABI: The FDPIC register is used as a base register for accessing the global offset table (GOT) and function descriptors. +# Yksi prosessorin rekistereistä on nimetty fdpic-rekisteriksi milloin data- ja tekstilohkot ovat sijoitettavia (eli niiden siirros ei ole vakio). +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: ei voi linkittää objektitiedostoa ilman fdpic-rekisteriä suoritettavaan tiedostoon, joka käyttää fdpic-rekisteriä" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: ei voi linkittää fdpic-rekisteriä käyttävää objektitiedostoa suoritettavaan tiedostoon, joka ei käytä fdpic-rekisteriä" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, lohko %A: ratkaisematon sijoitus %s symbolia â€%s†varten" + +# Procedure Linkage Table (PLT) and Global Offset Table (GOT) +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, lohko %A: Ei proseduurilinkitystaulua eikä yleissiirrostaulua sijoitukselle %s symbolia â€%s†varten" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, lohko %A: Ei proseduurilinkitystaulua sijoituksille %s symbolia â€%s†varten" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "[jonka nimi on kadonnut]" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, lohko %A: sijoitus %s ei-nolla-yhteenlaskettavalla %d paikallista symbolia varten" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, lohko %A: sijoitus %s ei-nolla-yhteenlaskettavalla %d symbolia â€%s†varten" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, lohko %A: sijoitusta %s ei sallita yleissymbolille: â€%sâ€" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, lohko %A: sijoitus %s ilman yleissiirrostaulun luontia" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, lohkon %A: sijoituksella %s on määrittelemätön viite â€%sâ€, ehkä esittelysekaannus?" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, lohko %A: sijoitusta %s ei sallita symbolille: â€%sâ€, joka määritellään ohjelman ulkopuolella, ehkä esittelysekaannus?" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(liian monta yleismuuttujaa valitsimelle -fpic: käännä uudelleen valitsimella -fPIC)" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(säikeen paikallinen data liian iso valitsimelle -fpic tai -msmall-tls: käännä uudelleen valitsimella -fPIC tai -mno-small-tls)" + +# position-independent code (PIC) +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, lohko %A:\n" +" v10/v32 yhteensopiva objekti %s ei saa sisältää paikkariippumatonta koodisijoitusta" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, lohko %A:\n" +" sijoitusta %s ei pitäisi käyttää jaetussa objektissa; tyypillisesti valitsinsekaannus, käännä uudelleen argumentilla -fPIC" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, lohko %A:\n" +" sijoitusta %s ei pitäisi käyttää jaettussa objektissa; käännä uudelleen argumentilla -fPIC" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, lohko â€%Aâ€, symboliin â€%sâ€:\n" +" sijoitusta %s ei pitäisi käyttää jaettussa objektissa; käännä uudelleen argumentilla -fPIC" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "Odottamaton konenumero" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [symboleissa on â€_â€-etuliite]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 ja v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: käyttää â€_â€-etuliitesymboleja, mutta kirjoittaa tiedoston ilman etuliitesymboleja" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: käyttää ilman etuliitesymboleja, mutta kirjoittaa tiedoston â€_â€-etuliitesymboleilla" + +# CRIS v32 info: The chip with the CRIS v32 core. +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B sisältää â€CRIS v32â€-koodia, ei ole yhteensopiva aiempien objektien kanssa" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B ei sisällä â€CRIS-v32â€-koodia, yhteensopimaton aiempien objektien kanssa" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "sijoitus vaatii nolla-yhteenlaskettavan" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): sijoitus kohteeseen â€%s+%x†saatta olla yläpuolella olevan virheen aiheuttama" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF ei sovelleta kutsukäskyyn" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 ei sovelleta â€lddiâ€-käskyyn" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI ei sovelleta â€sethiâ€-käskyyn" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO ei sovelleta â€setloâ€- tai â€setlosâ€-käskyyn" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX ei sovelleta â€lddâ€-käskyyn" + +# msgid-virhe: calll, eli yksi ällä liikaa +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX ei sovelleta kutsukäskyyn" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 ei sovelleta â€ldiâ€-käskyyn" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI ei sovelleta â€sethiâ€-käskyyn" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO ei sovelleta â€setloâ€- tai â€setlosâ€-käskyyn" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX ei sovelleta â€ldâ€-käskyyn" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI ei sovelleta â€sethiâ€-käskyyn" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO ei sovelleta â€setloâ€- tai â€setlosâ€-käskyyn" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC viittaa dynaamiseen symboliin ei-nolla-yhteenlaskettavalla" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE viittaa dynaamiseen symboliin ei-nolla-yhteenlaskettavalla" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): reloc-tietue â€%sâ€: %s varten" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "sijoitus viittaa eri segmenttiin" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: käännetty %s:n kanssa ja linkitetty paikkariippuvaisia koodisijoituksia käyttävien modulien kanssa" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: käännetty %s:n kanssa ja linkitetty moduleihin, jotka on käännetty %s:n kanssa" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: käyttää erilaisia tuntemattomia â€e_flags (0x%lx)â€-kenttiä kuin edelliset modulit (0x%lx)" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "yksityiset liput = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Sijoituksia geneerisessä ELF (EM: %d):ssa" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): ei tavoita kohdetta %s, käännä uudelleen â€-ffunction-sectionsâ€-valitsimilla" + +#: elf32-hppa.c:1284 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: sijoitusta %s ei voi käyttää kun tehdään jaettua objektia; käännä uudelleen â€-fPICâ€-argumentilla" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "%B: vienti-stubin %s kaksoiskappale" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s korjaus käskylle 0x%x ei ole tuettu ei-jaetussa linkissä" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): ei voi käsitellä %s kohteelle %s" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr "â€.gotâ€-alilohko ei ole välittömästi â€.pltâ€-lohkon jälkeen" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: virheellinen sijoitustyyppi %d" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: TLS-siirros kohteesta %s kohteeseen %s kohdetta â€%s†varten osoitteessa 0x%lx lohkossa â€%A†epäonnistui" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: sijoitusta %s kohteen STT_GNU_IFUNC-symbolia `%s' varten ei käsittele %s" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: â€%s†haettu sekä normaalina että säikeisenä paikallissymbolina" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: tunnistamaton sijoitus (0x%x) lohkossa â€%Aâ€" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "piilotettu symboli" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "sisäinen symboli" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "suojattu symboli" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "symboli" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: R_386_GOTOFF-sijoitusta määrittelemätöntä %s â€%s†varten ei voida käyttää kun tehdään jaettua objektia" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: R_386_GOTOFF-sijoitusta suojattua funktiota â€%s†varten ei voida käyttää kun tehdään jaettua objektia" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "hylätty tulostelohko: â€%Aâ€" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k-avartaja: kytkintaulu ilman täydellisesti täsmääviä sijoitustietoja." + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k-avartaja: kytkintauluotsake rikkinäinen." + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k-linkkeri: puuttuva sivukäsky kohteessa 0x%08lx (kohde = 0x%08lx)." + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k-linkkeri: redundanssisivukäsky kohteessa 0x%08lx (kohde = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "ei-tuettu sijoitus data/käskyosoitetilojen välillä" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: käyttää eri â€e_flags (0x%lx)â€-kenttiä kuin edelliset modulit (0x%lx)" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "yleisosoitinsuhteellinen sijoitus kun â€_gp†ei ole määritelty" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "yleisosoittimen suhteellinen osoite lukualueen ulkopuolella" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "sisäinen virhe: yhteenlaskettavan pitäisi olla nolla kohteelle R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "SDA-sijoitus kun â€_SDA_BASE_†ei ole määritelty" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: Kohteen (%s) sijoitus %s on väärässä lohkossa (%A)" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Käskyjoukko ei täsmää edellisten modulien kanssa" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "yksityiset liput = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": m32r-käskyt" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": m32rx-käskyt" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": m32r2-käskyt" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Viite etäsymboliin â€%s†väärää sijoitusta käyttäen saattaa aiheuttaa virheellisen suorituksen" + +# memory bank: A physical section of memory. +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "muistilohkottu osoite [%lx:%04lx] (%lx) ei ole samassa muistilohkossa kuin nykyinen muistilohkottu osoite [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "viite muistilohkottuun osoitteeseen [%lx:%04lx] tavallisessa osoitetilassa osoitteessa %04lx" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: linkitystiedostot käännetty 16-bittisille kokonaisluvuille (-mshort) ja muut 32-bittisille kokonaisluvuille" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: linkitystiedostot käännetty 32-bittiselle double-liukuluvulle (-fshort-double) ja muut 64-bittiselle double-liukuluvulle" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: linkitystiedostot käännetty HCS12:lle, muut käännetty HC12:lle" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: käyttää eri â€e_flags (0x%lx)â€-kenttiä kuin edelliset modulit (0x%lx)" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-bittinen kokonaisluku, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-bittinen kokonaisluku, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "64-bittinen double-liukuluku, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "32-bittinen double-liukuluku, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "prosessori=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "prosessori=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "prosessori=HC12]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr " [muisti=muistilohkomalli]" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr " [muisti=litteä]" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "tuntematon" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: Yleissiirrostaulun ylivuoto: 8-bittisellä siirrososoitteella varustettujen sijoitusten lukumäärä > %d" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: Yleissiirrostaulun ylivuoto: 8-bittisellä tai 16-bittisellä siirrososoitteella varustettujen sijoitusten lukumäärä > %d" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_68K_TLS_LE32-sijoitukset eivät ole sallittuja jaetuissa objekteissa" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Sijoitusta %s (%d) ei tällä hetkellä tueta.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Tuntematon sijoitustyyppi %d\n" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B ja %B ovat eri käyttöjärjestelmäytimille" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B ja %B ovat eri konfiguraatioille" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "yksityiset liput = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: tuntematon sijoitustyyppi %d" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Kohteen (%s) sijoitus %s on väärässä lohkossa (%s)" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: luultavasti käännetty ilman -fPIC-argumenttia?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: virheellinen sijoituslohkonimi â€%sâ€" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "literaali sijoitus tapahtuu ulkoiselle symbolille" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32-bittinen yleisosoitinsuhteellinen sijoitus tapahtuu ulkoiselle symbolille" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "geneerinen linkkeri ei voi käsitellä kohdetta %s" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "rikkinäinen %s-lohko kohteessa %B" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "ei voi lukea %s-lohkoon kohteesta %B" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "varoitus: ei voi asettaa %s-lohkon kokoa kohteessa %B" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "ei onnistuttu varaamaan muistitilaa uudelle APUinfo-lohkolle." + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "ei onnistuttu laskemaan uutta APUinfo-lohkoa" + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "ei onnistuttu asentamaan uutta APUinfo-lohkoa" + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: sijoitusta %s ei voi käyttää kun tehdään jaettua objektia" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s reloc-tietue paikallista symbolia varten" + +# Otaksun tässä että hard float tarkoittaa tässä muistipaikkaa (esim. rekisteriä), joka on varattu float-tyyppisille liukuluvuille +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Varoitus: %B käyttää laitteistoliukulukua, %B käyttää ohjelmistoliukulukua" + +# Otaksun tässä että hard float tarkoittaa tässä muistipaikkaa (esim. rekisteriä), joka on varattu float-tyyppisille liukuluvuille +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Varoitus: %B käyttää kaksoistarkkuuden laitteistoliukulukua, %B käyttää yksittäistarkkuuden laitteistoliukulukua" + +# Otaksun tässä että hard float tarkoittaa tässä muistipaikkaa (esim. rekisteriä), joka on varattu float-tyyppisille liukuluvuille +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Varoitus: %B käyttää ohjelmistoliukulukua, %B käyttää yksittäistarkkuuden laitteistoliukulukua" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Varoitus: %B käyttää tuntematonta liukuluku-ABI:a %d" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Varoitus: %B käyttää tuntematonta vektori-ABI:a %d" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Varoitus: %B käyttää vektori-ABI:a â€%sâ€, %B käyttää â€%sâ€" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Varoitus: %B käyttää r3/r4 pienille rakennepaluille, %B käyttää muistia" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Varoitus: %B käyttää tuntematonta pientä rakennepaluusopimusta %d" + +#: elf32-ppc.c:4197 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: käännetty â€-mrelocatableâ€-argumentilla ja linkitetty tavallisesti käännetyillä moduleilla" + +#: elf32-ppc.c:4205 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: käännetty tavallisesti ja linkitetty moduleilla, jotka on käännetty â€-mrelocatableâ€-argumentilla" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "Käytetään bss-plt-argumenttia %B:n vuoksi" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: tuntematon sijoitustyyppi %d symbolille %s" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): ei-nolla-yhteenlaskettava %s reloc-tietueessa symbolia â€%s†varten" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): sijoitusta %s epäsuoralle funktiolle %s ei tueta" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: kohde (%s) sijoituksessa %s on väärässä tulostelohkossa (%s)" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: sijoitus %s ei ole vielä tuettu symbolille %s." + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): %s reloc-tietuetta â€%s†varten: virhe %d" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s ei ole määritelty linkkerissä luodussa %s" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%B:%A: Varoitus: vanhentunut Red Hat reloc -tietue " + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "Varoitus: RX_SYM-reloc tuntemattomalla symbolilla" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "%B(%A): virhe: kutsu määrittelemättömään funktioon '%s'" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "%B(%A): varoitus: tasaamaton pääsy symboliin ’%s’ pienellä data-alueella" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "%B(%A): sisäinen virhe: â€lukualueen ulkopuolellaâ€-virhe" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "%B(%A): sisäinen virhe: ei-tuettu sijoitusvirhe" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "%B(%A): sisäinen virhe: vaarallinen sijoitus" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "%B(%A): sisäinen virhe: tuntematon virhe" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr " [64-bittiset double-liukuluvut]" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr " [paikkariippumaton koodi]" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): virheellinen käsky TLS-sijoitukselle %s" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "ei tarpeeksi yleissiirrostaulutilaa paikallisille yleissiirrostaulutulokohdille" + +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "osoite ei ole word-tasattu" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Väärän muotoinen reloc-tietue havaittu lohkolle %s" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL15 reloc-tietue kohteessa 0x%lx ei ole yleissymbolia varten" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr " [paikkariippumaton koodi]" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr " [korjaussyvyys]" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: varoitus: linkitetään paikkariippumattomia kooditiedostoja paikkariippuvaisten kooditiedostojen kanssa" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: â€IMPORT ASâ€-direktiivi kohteelle %s kätkee edellisen â€IMPORT ASâ€-direktiivin" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: Tunnistamaton â€.directiveâ€-komento: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Ei onnistuttu lisäämään uudelleennimettyä symbolia %s" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: varoitus: virheellinen R_SH_USES-siirrososoite" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: varoitus: R_SH_USES osoittaa tunnistamattomaan käskyyn 0x%x" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: varoitus: virheellinen R_SH_USES lataussiirrososoite" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: varoitus: ei voitu löytää odotettua reloc-tietuetta" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: varoitus: symboli odottamattomassa lohkossa" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: varoitus: ei voitu löytää odotettua â€COUNT relocâ€-tietuetta" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: varoitus: virheellinen lukumäärä" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: vakava: reloc-tietue ylivuoto avartamisen aikana" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Odottamatonta STO_SH5_ISA32 paikallisessa symbolissa ei käsitellä" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: vakava: tasaamaton haarautumiskohde avarrustuetulle sijoitukselle" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: vakava: tasaamaton %s sijoitus 0x%lx" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: vakava: R_SH_PSHA-sijoitus %d ei ole lukualueella -32..32" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: vakava: R_SH_PSHL-sijoitus %d ei ole lukualueella -32..32" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%B(%A+0x%lx): ei voi lähettää korjauksia kohteeseen â€%s†kirjoitussuojatussa lohkossa" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%B(%A+0x%lx): %s sijoitus ulkoista symbolia â€%s†varten" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%X%C: sijoitus kohteeseen â€%s†viittaa eri segmenttiin\n" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%C: varoitus: sijoitus kohteeseen â€%s†viittaa eri segmenttiin\n" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: â€%s†haettu sekä normaalina että FDPIC-symbolina" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: â€%s†haettu sekä FDPIC-symbolina että säikeisenä paikallissymbolina" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "%B: Funktiokuvaajasijoitus nollasta poikeavalla yhteenlaskettavalla" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: TLS-tyyppistä paikallista suoritettavaa koodia ei voida linkittää jaettuihin objekteihin" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: käännetty 32-bittisenä objektina ja %s on 64-bittinen" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: käännetty 64-bittisenä objektina ja %s on 32-bittinen" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: objektikoko ei täsmää kohteen %s objektikoon kanssa" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: kohdattiin datalabel-symboli syötteessä" + +# prepare-to-branch (PTB) instruction +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB-täsmäämättömyys: SHmedia-osoite (bitti 0 == 1)" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA-täsmäämättömyys: SHcompact-osoite (bitti 0 == 0)" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: GAS-virhe: odottamaton PTB-käsky R_SH_PT_16-tyypillä" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: virhe: tasaamaton sijoitustyyppi %d siirroksessa %08x reloc-tietue %p\n" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: ei voitu kirjoittaa lisättyjä â€.crangesâ€-tulokohtia kokonaisuudessaan" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: ei voitu kirjoittaa lajiteltuja â€.crangesâ€-tulokohtia kokonaisuudessaan" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: käännetty 64-bittiselle järjestelmälle ja kohde on 32-bittinen" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: linkitetty â€little endianâ€-tiedostoja â€big endianâ€-tiedostojen kanssa" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: päällyslohko %A ei ala välimuistissa olevalta riviltä.\n" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: päällyslohko %A on laajempi kuin välimuistissa oleva rivi.\n" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: päällyslohko %A ei ole välimuistialueella.\n" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: päällyslohkot %A ja %A eivät ala samasta osoitteesta.\n" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "varoitus: kutsu ei-funktiosymboliin %s määritelty kohteessa %B" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) eroaa analyysistä (%u)\n" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "%B ei saa määritellä kohdetta %s" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "et saa määritellä kohdetta %s skriptissä" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "%s päällyslohkossa" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "päällys-stub-sijoitusylivuoto" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "stubit ei täsmää lasketun koon kanssa" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "varoitus: %s menee päällekkäin %s:n kanssa\n" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "varoitus: %s ylittää lohkokoon\n" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v ei löytynyt funktiotaulusta\n" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): kutsu ei-koodilohkoon %B(%A), analyysi ei ole täydellinen\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "Pinoanalyysi ei ota huomioon kutsua kohteesta %s kohteeseen %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " kutsut:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s kaksoiskappale kohteessa %s\n" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "%s on tehty kahteen kertaan\n" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "ei tukea objektitiedostojen kaksoiskappaleille automaattisessa päällysskriptissä\n" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "ei-päällyksen koko 0x%v plus päällyksen maksimikoko 0x%v ylittävät paikallisen varaston\n" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s ylittää päällyskoon\n" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "Pinokoko kutsugraafijuurinodeille.\n" + +# Wikipedia: A tail call is a subroutine call just before the end of a subroutine. +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Pinokoko funktioille. Sivuhuomautukset: â€*†maksimipino, â€t†alikutsu\n" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "Vaadittu maksimipino on 0x%v\n" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "vakava virhe kun luodaan .fixup" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s+0x%lx): ratkaisematon %s sijoitus symbolia â€%s†varten" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "%B: SB-suhteellinen sijoitus, mutta __c6xabi_DSBT_BASE ei ole määritelty" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "%B: sijoitustyyppiä %d ei ole toteutettu" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "vaarallinen sijoitus" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "virhe: %B vaatii enemmän pinotasausta kuin %B säilyttää" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "virhe: tuntematon Tag_ABI_array_object_alignment-arvo kohteessa %B" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "virhe: tuntematon Tag_ABI_array_object_align_expected-arvo kohteessa %B" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "virhe: %B vaatii enemmän taulukkotasausta kuin %B säilyttää" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "varoitus: %B ja %B eroavat wchar_t size-koossa" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "varoitus: %B ja %B eroavat siinä, että koodi on käännetty kohteelle DSBT" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "varoitus: %B ja %B eroavat siinä, että datan osoitteet ovat paikkariippuvaisia" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "varoitus: %B ja %B eroavat siinä, että koodin osoitteet ovat paikkariippuvaisia" + +# small data region on sama kuin .scommon data region +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Muuttuja â€%s†ei voi sijaita useissa â€smallâ€-data-alueissa" + +# small on .scommon, zero on .zcommon ja tiny on .tcommon +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Muuttuja â€%s†voi olla vain yhdessä â€smallâ€-, â€zeroâ€- ja â€tinyâ€-data-alueista" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Muuttuja â€%s†ei voi olla sekä â€smallâ€- että â€zeroâ€-data-alueissa samanaikaisesti" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Muuttuja â€%s†ei voi olla sekä â€smallâ€- että â€tinyâ€-data-alueissa samanaikaisesti" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Muuttuja â€%s†ei voi olla sekä â€zeroâ€- että â€tinyâ€-data-alueissa samanaikaisesti" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "EI ONNISTUTTU löytämään edellistä HI16 reloc-tietuetta\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "ei voitu paikallistaa erityistä linkkerisymbolia â€__gpâ€" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "ei voitu paikallistaa erityistä linkkerisymbolia â€__epâ€" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "ei voitu paikallistaa erityistä linkkerisymbolia â€__ctbpâ€" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: Arkkitehtuuri ei täsmännyt edellisten modulien kanssa" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "yksityiset liput = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "v850-arkkitehtuuri" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "v850e-arkkitehtuuri" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "v850e1-arkkitehtuuri" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "v850e2-arkkitehtuuri" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "v850e2v3-arkkitehtuuri" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr " [paikkariippuvaisen koodin lippu]" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr " [d-float-liukulukulippu]" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr " [g-float-liukulukulippu]" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: varoitus: Yleissiirrostaulun %ld-yhteenlaskettava kohteelle â€%s†ei täsmää edellisen yleissiirrostaulun %ld-yhteenlaskettavan kanssa" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: varoitus: %d:n PLT-yhteenlaskettavaa kohteelle â€%s†lohkosta %s ei oteta huomioon" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: varoitus: %s sijoitus symbolia â€%s†varten %s-lohkosta" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: varoitus: %s sijoitus kohteeseen 0x%x â€%sâ€-lohkosta" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "ei-nolla-yhteenlaskettava â€@fptr relocâ€-tietueessa" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): virheellinen ominaisuustaulu" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): sijoitussiirrososoite lukualueen (koko=0x%x) ulkopuolella" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "dynaaminen sijoitus kirjoitussuojatussa lohkossa" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "TLS-siirros virheellinen ilman dynaamisia lohkoja" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "sisäinen epäjohdonmukaisuus â€.got.locâ€-alilohkokoossa" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: yhteensopimaton konetyyppi. Tuloste on 0x%x. Syöte on 0x%x" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Yritys muuttaa â€L32R/CALLXâ€-kutsu â€CALLâ€-kutsuksi ei onnistunut" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): ei voitu avata käskyä; mahdollinen konfiguraatiotäsmäämättömyys" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): ei voitu avata käskyä XTENSA_ASM_SIMPLIFY-sijoitukselle; mahdollinen konfiguraatiotäsmäämättömyys" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "virheellinen sijoitusosoite" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "ylivuoto avartamisen jälkeen" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): odottamaton korjaus %s-sijoitukselle" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP-sijoitus ei löytänyt â€ldahâ€- ja â€ldaâ€-käskyjä" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: â€.gotâ€-alisegmentti ylittää 64 kilotavun rajan (koko %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: yleisosoitinsuhteellinen sijoitus dynaamista symbolia %s varten" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: ohjelmalaskurisuhteellinen sijoitus dynaamista symbolia %s varten" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: vaihto yleisosoittimessa: BRSGP %s" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: â€!samegp relocâ€-tietue symbolia varten ilman â€.prologueâ€-lohkoa: %s" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: käsittelemätön dynaaminen sijoitus %s:ta varten" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: ohjelmalaskurisuhteellinen sijoitus määrittelemätöntä heikkoa symbolia %s varten" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: dtp-suhteellinen sijoitus dynaamista symbolia %s varten" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: tp-suhteellinen sijoitus dynaamista symbolia %s varten" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "stub-tulokohta kohteelle %s ei voi ladata â€.pltâ€, dp-siirrososoite = %ld" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): kohdetta %s ei voi tavoittaa" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Sisäinen yhteensopimattomuusvirhe linkkerin varaamalle\n" +" yleisrekisteriarvolle: linkitetty: 0x%lx%08lx != avarrettu: 0x%lx%08lx\n" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: â€base-plus-offsetâ€-sijoitus rekisterisymbolia varten: (tuntematon) kohteessa %s" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: â€base-plus-offsetâ€-sijoitus rekisterisymbolia varten: %s kohteessa %s" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: rekisterisijoitus ei-rekisterisymbolia varten: (tuntematon) kohteessa %s" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: rekisterisijoitus ei-rekisterisymbolia varten: %s kohteessa %s" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: direktiivi LOCAL on oikea vain rekisterissä tai absoluuttiarvona" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: LOCAL-direktiivi: Rekisteri $%ld ei ole paikallinen rekisteri. Ensimmäinen yleisrekisteri on $%ld." + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Virhe: useita â€%sâ€-määrittelyjä; %s-alku on asetettu aiemmin linkitetyssä tiedostossa\n" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "Rekisterilohkossa on sisältö\n" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Sisäinen yhteensopimattomuus: jäljelle jäävä %u != maksimi %u.\n" +" Lähetä raportit ohjelmistovioista (englanniksi) osoitteeseen http://sourceware.org/bugzilla/." + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: käännetty â€big endianâ€-järjestelmälle ja kohde on â€little endianâ€" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: käännetty â€little endianâ€-järjestelmälle ja kohde on â€big endianâ€" + +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "kopio-reloc-tietue â€%sâ€:ta varten vaatii laiskan plt-linkityksen; vältä asettamasta LD_BIND_NOW=1 tai päivitä gcc" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "dynreloc-väärinlaskenta kohteelle %B, lohko %A" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: â€.opd†ei ole säännönmukainen opd-tulokohtien taulukko" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: odottamaton reloc-tyyppi %u â€.opdâ€-lohkossa" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: määrittelemätön symboli â€%s†â€.opdâ€-lohkossa" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "%s määritelty poistetussa sisällysluettelotulokohdassa" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "pitkä haarautumis-stub â€%s†siirrososoitteen ylivuoto" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "ei löydy haarautumis-stub-kohdetta â€%sâ€" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "linkitystauluvirhe â€%sâ€:ta varten" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "ei voi muodostaa haaroitus-stub-kohdetta â€%sâ€" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "%B lohko %A ylittää stub-ryhmäkoon" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"linkkeristubit %u-ryhmä%s:ssä\n" +" haarautuminen %lu\n" +" sisältöluettelosäätö %lu\n" +" pitkä haarautuminen %lu\n" +" pitkä sisältöluettelosäätö %lu\n" +" plt-kutsu %lu" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): automaattisia useita sisältöluettelotauluja ei ole tuettu crt-tiedostoissasi; käännä uudelleen â€-mminimal-tocâ€-argumentilla tai päivitä gcc" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): sisarruskutsuoptimointi kohteeseen â€%s†ei salli automaattisia useita sisällysluettelotauluja; käännä uudelleen â€-mminimal-tocâ€-argumentilla tai â€-fno-optimize-sibling-callsâ€-argumentilla, tai tee kohteesta â€%s†ulkoinen" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: sijoitus %s ei ole tuettu symbolille %s." + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: virhe: sijoitus %s ei ole %d:n kerrannainen" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: virhe: tasaamaton sijoitustyyppi %d kohteessa %08x reloc-tietue %08x\n" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Vain rekisterit %%g[2367] voidaan esitellä käyttäen STT_REGISTER-symbolia" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "Rekisteriä %%g%d käytetty yhteensopimattomasti: %s kohteessa %B, aikaisemmin %s kohteessa %B" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Symbolissa â€%s†on eri tyyppejä: REGISTER kohteessa %B, aiemmin %s kohteessa %B" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Symbolissa â€%s†on eri tyyppejä: %s kohteessa %B, aiemmin REGISTER kohteessa %B" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: linkitetään UltraSPARC-kohtainen HAL-kohtaisella koodilla" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: â€%s†kutsuttu sekä normaalina että säikeisenä paikallissymbolina" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: sijoituksella %s kohteen STT_GNU_IFUNC-symbolia â€%s†varten on ei-nolla-yhteenlaskettava: %d" + +#: elf64-x86-64.c:3073 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: sijoitusta R_X86_64_GOTOFF64 suojattua funktiota â€%s†varten ei voida käyttää kun tehdään jaettua objektia" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "; käännetty uudelleen -fPIC-parametrillä" + +#: elf64-x86-64.c:3189 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: sijoitusta %s kohteeseen %s â€%s†ei voi käyttää kun tehdään jaettua objektia %s" + +#: elf64-x86-64.c:3191 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: sijoitusta %s kohteeseen %s â€%s†ei voi käyttää kun tehdään jaettua objektia %s" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "varoitus: %s:ssa on rikkinäinen merkkijonotauluindeksi - ei oteta huomioon" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: versiolukumäärä (%ld) ei täsmää symbolilukumäärän (%ld) kanssa" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): sijoituksessa %d on virheellinen symboli-indeksi %ld" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Varoitus: %B typistettiin: odotettu käyttöjärjestelmäydintiedoston koko >= %lu, löytyi: %lu." + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-määrittely kohteessa %B lohko %A ei täsmää ei-TLS-määrittelyn kanssa kohteessa %B lohko %A" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: TLS-viite kohteessa %B ei täsmää ei-TLS-viitteen kanssa kohteessa %B" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: TLS-määrittely kohteessa %B lohko %A ei täsmää ei-TLS-viitteen kanssa kohteessa %B" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-viite kohteessa %B ei täsmää ei-TLS-määrittelyn kanssa kohteessa %B lohko %A" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: epäsuoran versioidun symbolin â€%s†odottamaton uudelleenmäärittely" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "%B: versiosolmua ei löydetty symbolille %s" + +#: elflink.c:2166 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: virheellinen reloc-tietuesymboli-indeksi (0x%lx >= 0x%lx) siirrososoitteelle 0x%lx lohkossa â€%Aâ€" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: ei-nolla symboli-indeksi (0x%lx) siirrososoitetta 0x%lx varten lohkossa â€%A†kun objektitiedostolla ei ole symbolitaulua" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: sijoituskokotäsmäämättömyys %B:n tulolohkossa %A" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "varoitus: dynaamisen symbolin â€%s†tyyppi ja koko ei ole määritelty" + +# USA:ssa alternate-sanaa käytetään yleisesti, kun tarkoitetaan alternative. +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: vaihtoehtoinen ELF-konekoodi löydetty (%d) kohteessa %B, otetaan %d\n" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: virheellinen versio %u (maksimi %d)" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: virheellinen tarvittu versio %d" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Varoitus: tasaus %u yhteissymbolissa â€%s†kohteessa %B on suurempi kuin tasaus (%u) sen lohkossa %A" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Varoitus: tasaus %u symbolissa â€%s†kohteessa %B on pienempi kuin %u kohteessa %B" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Varoitus: symbolin â€%s†koko vaihtui koosta %lu kohteessa %B kokoon %lu kohteessa %B" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "%B: määrittelemätön viite symboliin ’%s’" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "huomatus: ’%s’ on määritelty kohteessa DSO %B, joten yritä lisätä se linkkittäjän komentoriville" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: määrittelemätön versio: %s" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: â€.preinit_arrayâ€-lohkoa ei sallita kohteessa DSO" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "määrittelemätön %s-viite kompleksisymbolissa: %s" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "tuntematon operaattori â€%c†kompleksisymbolissa" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Ei voi lajitella relocs-tietueita - niitä on useampia kuin yhtä kokoa" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Ei voi lajitella relocs-tietueita - niiden koko on tuntematon" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "Ei tarpeeksi muistia sijoitusten lajittelemiseen" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Liian monia lohkoja: %d (>= %d)" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: %s symboli â€%s†kohteessa %B on DSO:n viitteenä" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: ei löytynyt tulostelohkoa %A syötelohkolle %A" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: %s symbolia â€%s†ei ole määritelty" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "virhe: %B sisältää reloc-tietueen (0x%s) lohkolle %A, joka viittaa puuttuvaan yleissymboliin" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%Xâ€%s†viitattu lohkossa â€%A†kohteessa %B: määritelty hylätyssä lohkossa â€%A†/ %B\n" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A:ssa on sekä järjestettyjä [â€%A†kohteessa %B] että järjestämättömiä [â€%A†kohteessa %B] lohkoja" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A:ssa on sekä järjestettyjä että järjestämättömiä lohkoja" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: ei löytynyt tulostelohkoa %s" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "varoitus: %s-lohkossa on nollakoko" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: varoitus: luodaan DT_TEXTREL-tunniste jaetussa objektissa.\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: ei voi lukea symboleja: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Poistetaan käyttämätön lohko â€%s†tiedostossa â€%Bâ€" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "Varoitus: â€gc-sectionsâ€-valitsinta ei oteta huomioon" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: ei oteta huomioon lohkon â€%A†kaksoiskappaletta" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: lohkon â€%A†kaksoiskappaleessa on eri koko" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: varoitus: ei voitu lukea lohkon â€%A†sisältöä" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: varoitus: lohkon â€%A†kaksoiskappaleella on erilainen sisältö" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "staattinen proseduuri (ei nimeä)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "%B: %A+0x%lx: Suorat hypyt ISA-tilojen välillä eivät ole sallittuja; harkitse uudelleenkääntämistä käyttäen yhteislinkitystä." + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Varoitus: virheellinen â€%sâ€-valitsinkoko %u pienempi kuin sen otsake" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Varoitus: ei voi määritellä stub-lohkon â€%s†kohdefunktiota" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Muodoltaan virheellinen reloc-tietue havaittu lohkossa %s" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: Yleissiirrostaulu-reloc-tietue siirroksessa 0x%lx ei ole odotettu suoritettavissa tiedostoissa" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: â€CALL16 relocâ€-tietue siirroksessa 0x%lx ei ole yleissymbolia varten" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "ei-dynaaminen sijoitus viittaa dynaamiseen symboliin %s" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Ei löydy täsmäävää â€LO16 relocâ€-tietuetta tulolohkoa â€%s†varten symbolinimelle %s kohteessa 0x%lx lohkossa â€%Aâ€" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "â€smallâ€-datalohko ylittää 64 kilotavua; alenna â€smallâ€-datalohkon kokorajaa (katso valitsin -G)" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: virheellinen lohkonimi â€%sâ€" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Varoitus: %B käyttää â€-msingle-floatâ€-valitsinta, %B käyttää â€-mdouble-floatâ€-valitsinta" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Varoitus: %B käyttää â€-msingle-floatâ€-valitsinta, %B käyttää â€-mips32r2 -mfp64â€-valitsimia" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Varoitus: %B käyttää â€-mdouble-floatâ€-valitsinta, %B käyttää â€-mips32r2 -mfp64â€-valitsimia" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: tavujärjestys tyypiltään sopimaton valitun emuloinnin tavujärjestystyypin kanssa" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI ei ole yhteensopiva valitun emuloinnin ABIn kanssa" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: varoitus: linkitetään abi-kutsutiedostoja ei-abi-kutsutiedostoihin" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: linkitetään 32-bittinen koodi 64-bittisen koodin kanssa" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: linkitetään %s-moduli edellisten %s-modulien kanssa" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: ABI-täsmäämättömyys: linkitetään %s-moduli edellisten %s-modulien kanssa" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [abi tuntematon]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [ei abia asetettu]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [tuntematon ISA]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [ei 32-bittitila]" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "virheellinen sijoitustyyppi %d" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Tulostetiedosto vaatii jaetun kirjaston â€%sâ€\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Tulostetiedosto vaatii jaetun kirjaston â€%s.so.%sâ€\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Symbolia %s ei ole määritelty korjauksia varten\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "Varoitus: korjauslukumäärän täsmäämättömyys\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: merkkijono on liian pitkä (%d merkkiä, maksimi 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: tunnistamaton symboli â€%s†liput 0x%x" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: toteuttamaton ATI-tietue %u symbolille %u" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: odottamaton ATN-tyyppi %d ulkoisessa osassa" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "%B: odottamaton tyyppi ATN:n jälkeen" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: odottamaton merkki â€%s†Intel-heksatiedostossa" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: virheellinen tarkistussumma Intel-heksatiedostossa (odotettiin %u, löydettiin %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: virheellinen laajennettu osoitetietuepituus Intel-heksatiedostossa" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: virheellinen laajennettu aloitusosoitepituus Intel-heksatiedostossa" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: virheellinen laajennettu lineaariosoitetietuepituus Intel-heksatiedosto" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: virheellinen laajennettu lineaarialkuosoitepituus Intel-heksatiedostossa" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: tunnistamaton ihex-tyyppi %u Intel-heksatiedostossa" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: sisäinen virhe â€ihex_read_sectionâ€-lohkossa" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: virheellinen lohkopituus â€ihex_read_sectionâ€-lohkossa" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: osoite 0x%s lukualueen ulkopuolella Intel-heksatiedostolle" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "%B: ei kyetä hakemaan tiivistyksestä purettua lohkoa %A" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Käytöstä poistettu %s kutsuttiin tiedostossa %s rivillä %d funktiossa %s\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Käytöstä poistettu %s kutsuttu\n" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: epäsuora symboli â€%s†kohteeseen â€%s†on silmukka" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Yritettiin tehdä sijoitettava linkki %s-syötteellä ja %s-tulosteella" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: varoitus: ei oteta huomioon lohkon â€%A†kaksoiskappaletta\n" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: varoitus: lohkon â€%A†kaksoiskappaleessa on eri koko\n" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "Mach-O otsake:\n" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr " maaginen : %08lx\n" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " prosessorityyppi : %08lx (%s)\n" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " prosessorialityyppi : %08lx\n" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " tiedostotyyppi : %08lx (%s)\n" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr "ncmds : %08lx (%lu)\n" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " komentojenkoko : %08lx\n" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr " liput : %08lx (" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr " varattu : %08x\n" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "Segmentit ja lohkot:\n" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr " #: Segmenttinimi Lohkonnimi Osoite\n" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: pääsy lomitetun lohkon (%ld) lopun yli" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Ei käyttöjärjestelmäydintä lohkonimen %s varaamiseen\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Ei käyttöjärjestelmäydintä symbolin varaamiseksi %d tavua pitkänä\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: virheellinen mmo-tiedosto: alustusarvo kohteelle $255 ei ole â€Mainâ€\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: ei-tuettu leveämerkkisekvenssi 0x%02X 0x%02X symbolinimen jälkeen alkaen arvolla â€%sâ€\n" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: virheellinen mmo-tiedosto: ei-tuettu lopcode â€%dâ€\n" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: virheellinen mmo-tiedosto: odotettu YZ = 1 saatiin YZ = %d kohteelle lop_quote\n" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: virheellinen mmo-tiedosto: odotettiin z = 1 tai z = 2, saatiin z = %d kohteelle lop_loc\n" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: virheellinen mmo-tiedosto: odotettiin z = 1 tai z = 2, saatiin z = %d kohteelle lop_fixo\n" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: virheellinen mmo-tiedosto: odotettiin y = 0, saatiin y = %d kohteelle lop_fixrx\n" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: virheellinen mmo-tiedosto: odotettiin z = 16 tai z = 24, saatiin z = %d kohteelle lop_fixrx\n" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: virheellinen mmo-tiedosto: operandisanan etutavun on oltava 0 tai 1, saatiin %d kohteelle lop_fixrx\n" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: ei voi varata tiedostonimeä tiedostonumerolle %d, %d tavua\n" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: virheellinen mmo-tiedosto: tiedostonumero %d â€%sâ€, oli jo kirjoitettu arvona â€%sâ€\n" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: virheellinen mmo-tiedosto: tiedostonimi numerolle %d ei ole määritelty ennen käyttöä\n" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: virheellinen mmo-tiedosto: lop_stab:n kentät y ja z ovat nollasta poikkeavia, y: %d, z: %d\n" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: virheellinen mmo-tiedosto: lop_end ei ole viimeinen alkio tiedostossa\n" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: virheellinen mmo-tiedosto: lop_end:n YZ (%ld) ei ole sama kuin tetras-numero edeltävään kohteeseen lop_stab (%ld)\n" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: virheellinen symbolitaulu: symbolin â€%s†kaksoiskappale\n" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Virheellinen symbolimäärittely: â€Main†asetettu kohteeseen %s pikemmin kuin aloitusosoitteeseen %s\n" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: varoitus: symbolitaulu liian laaja kohteelle mmo, laajempi kuin 65535 32-bittistä sanaa: %d. Vain â€Main†lähetetään.\n" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: sisäinen virhe, symbolitaulu vaihtoi kokoa %d:sta sanasta %d sanaan\n" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: sisäinen virhe, sisäisessä rekisterilohkossa %s oli sisältöä\n" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: ei alustettuja rekistereitä; lohkopituus 0\n" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: liian monia alustettuja rekistereitä; lohkopituus %ld\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: virheellinen aloitusosoite alustetuille rekistereille pituudeltaan %ld: 0x%lx%08lx\n" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: ei voi edustaa lohkoa â€%s†oasys-lohkossa" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Käsittelemätön OSF/1-käyttöjärjestelmäydintiedoston lohkotyyppi %d\n" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: â€ld -r†ei tuettu â€PE MIPSâ€-objekteilla\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "%B: toteuttamaton %s\n" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "%B: hyppy liian kauas\n" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: virheellinen pari/reflo refhi:n jälkeen\n" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "varoitus: â€.pdataâ€-lohkokoko (%ld) ei ole %d:n monikerta\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Funktiotaulu (tulkittu â€.pdataâ€-lohkosisältö)\n" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "vma:\t\t\tAlkuosoite\t Loppuosoite\t Unwind-tiedot\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: Käsittelemätön tuontityyppi; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: Tunnistamaton tuontityyppi; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: Tunnistamaton tuontinimityyppi; %x" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: Tunnistamaton konetyyppi (0x%x) â€Import Library Formatâ€-arkistossa" + +#: peicode.h:1174 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: Tunnistettu, mutta käsittelemätön konetyyppi (0x%x) â€Import Library Formatâ€-arkistossa" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: kokokenttä on nolla â€Import Library Formatâ€-otsakkeessa" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: merkkijonoa ei ole päätetty nollaan ILF-objektitiedostossa." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot-otsake:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Tulokohtasiirrososoite = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Pituus = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Lippukenttä = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Osionimi = â€%sâ€\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Osio[%d] alku = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Osio[%d] loppu = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Osio[%d] sektori = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Osio[%d] pituus = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Suoritettavan tiedoston apuotsake\n" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers ei ole toteutettu" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: Odottamaton merkki â€%s†S-tietuetiedostossa\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: Virheellinen tarkistussumma S-tietuetiedostossa\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Stabs-tulokohdassa on virheellinen merkkijonoindeksi." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "â€Ei-tuettu .stabâ€-sijoitus" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "Tuntematon EGSD-alityyppi %d" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Pinon ylivuoto (%d) kohteessa _bfd_vms_push" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Pinon ylivuoto kohteessa _bfd_vms_pop" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "tuntematon ETIR-komento %d" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "virheellinen lohkoindeksi kohteessa %s" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "ei-tuettu STA-komento %s" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "%s: ei tuettu" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "%s: ei toteutettu" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "virheellinen %s-käyttö sisällöillä" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "varattu komento %d" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "Objektimoduli EI ole virheetön !\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Symboli %s korvattu kohteella %s\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC ilman relocs-tietueita lohkossa %s" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "Kokovirhe lohkossa %s" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Väärä ALPHA_R_BSR reloc-tietue" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Käsittelemätön sijoitus %s" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "tuntematon lähdekomento %d" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "DST__K_SET_LINUM_INCR ei ole toteutettu" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "DST__K_SET_LINUM_INCR_W ei ole toteutettu" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "DST__K_RESET_LINUM_INCR ei ole toteutettu" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "DST__K_BEG_STMT_MODE ei ole toteutettu" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "DST__K_END_STMT_MODE ei ole toteutettu" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "DST__K_SET_PC ei ole toteutettu" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "DST__K_SET_PC_W ei ole toteutettu" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "DST__K_SET_PC_L ei ole toteutettu" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "DST__K_SET_STMTNUM ei ole toteutettu" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "tuntematon rivikomento %d" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Tuntematon reloc-tietue %s + %s" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "Tuntematon reloc-tietue %s" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "virheellinen lohkoindeksi kohteessa ETIR" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "Tuntematon symboli komennossa %s" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr " EMH %u (pituus=%u): " + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "Moduliotsake\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr " tietuetaso: %u\n" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr " tietueen enimmäiskoko: %u\n" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr " modulinimi : %.*s\n" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr " moduliversio : %.*s\n" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr " käännöspäivämäärä : %.17s\n" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "Kielisuorittimen nimi\n" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr " kielinimi: %.*s\n" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "Lähdetiedostot-otsake\n" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr " tiedosto: %.*s\n" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "Otsikkotekstiotsake\n" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr " otsikko: %.*s\n" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "Copyright-otsake\n" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr " copyright: %.*s\n" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "käsittelemätön emh-alityyppi %u\n" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr " EEOM (pituus=%u):\n" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr " ehdollisten linkitysparien lukumäärä: %u\n" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr " täydentämiskoodi: %u\n" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr " siirto-osoiteliput: 0x%02x\n" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr " siirrososoite psect: %u\n" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr " siirto-osoite : 0x%08x\n" + +# Käännettäväksi on merkitty monia (vianjäljitys)symboleja ja vastaavia, joita ei oikeastaan pitäisi suomentaa. Joissakin kohdissa vain selväkieliset sanat on suomennettu. +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr " WEAK" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr " DEF" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr " UNI" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr " REL" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr " COMM" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr " VECEP" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr " NORM" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr " QVAL" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr " PIC" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr " LIB" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr " OVR" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr " GBL" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr " SHR" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr " EXE" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr " RD" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr " WRT" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr " VEC" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr " NOMOD" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr " COM" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr " 64B" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr " EGSD (pituus=%u):\n" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr " EGSD tulopiste %2u (tyyppi: %u, pituus: %u): " + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "PSC - Ohjelmalohkomäärittely\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr " tasaus : 2**%u\n" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr " liput : 0x%04x" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr " alloc (pituus): %u (0x%08x)\n" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr " nimi : %.*s\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "SPSC - Jaettu vedosohjelmalohkomäärittely\n" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr " alloc (pitus) : %u (0x%08x)\n" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr " vedossiirros : 0x%08x\n" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr " symvec-siirros : 0x%08x\n" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr " nimi : %.*s\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "SYM - Yleinen symbolimäärittely\n" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr " liput: 0x%04x" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr " psect-siirros: 0x%08x\n" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr " koodiosoite: 0x%08x\n" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr " psect-indeksi tulokohdalle : %u\n" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr " psect-indeksi : %u\n" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr " nimi : %.*s\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "SYM - Yleinen symboliviite\n" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "IDC - Ident-johdonmukaisuustarkistus\n" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr " liput : 0x%08x" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr " tunnistetäsmäys: %x\n" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr " virhevakavuus : %x\n" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr " yksilönimi : %.*s\n" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr " objektinimi : %.*s\n" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr " binaari-ident : 0x%08x\n" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr " ascii-ident : %.*s\n" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "SYMG - Yleinen symbolimäärittely\n" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr " symbolivektorisiirros: 0x%08x\n" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr " tulokohta: 0x%08x\n" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr " ohjelmakuvaus : 0x%08x\n" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr " psect-indeksi : %u\n" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "SYMV - Vektoroitu symbolimäärittely\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr " vektori : 0x%08x\n" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr " psect-siirros: %u\n" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "SYMM - Yleinen symbolimäärittely versiolla\n" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr " versiopeite : 0x%08x\n" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "käsittelemätön egsd-tulokohtatyyppi %u\n" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr " linkitysindeksi: %u, korvauskäsky: 0x%08x\n" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr " psect idx 1: %u, siirros 1: 0x%08x %08x\n" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr " psect idx 2: %u, siirros 2: 0x%08x %08x\n" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr " psect idx 3: %u, siirros 3: 0x%08x %08x\n" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr " yleisnimi: %.*s\n" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr " %s (pituus=%u+%u):\n" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr " (tyyppi: %3u, koko: 4+%3u): " + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "STA_GBL (pino yleinen) %.*s\n" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "STA_LW (pino longword) 0x%08x\n" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "STA_QW (pino quadword) 0x%08x %08x\n" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "STA_PQ (pino psect-kanta + siirros)\n" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr " psect: %u, siirros: 0x%08x %08x\n" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "STA_LI (pinoliteraali)\n" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "STA_MOD (pinomoduli)\n" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "STA_CKARG (vertaa proseduuriargumenttia)\n" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "STO_B (tallenna byte)\n" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "STO_W (tallenna word)\n" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "STO_LW (tallenna longword)\n" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "STO_QW (tallenna quadword)\n" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "STO_IMMR (tallenna välitön toisto) %u tavua\n" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "STO_GBL (tallenna yleinen) %.*s\n" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "STO_CA (tallenna koodiosoite) %.*s\n" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "STO_RB (tallenna suhteellinen haarautuminen)\n" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "STO_AB (tallenna absoluuttinen haarautuminen)\n" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "STO_OFF (tallenna siirros kohteeseen psect)\n" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "STO_IMM (tallenna välitön) %u tavua\n" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "STO_GBL_LW (tallenna yleinen longword) %.*s\n" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "STO_OFF (tallenna LP-proseduurituntomerkillä)\n" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "STO_BR_GBL (tallenna haarautuminen yleinen) *todo*\n" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "STO_BR_PS (tallenna haarautuminen psect + siirros) *todo*\n" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "OPR_NOP (ei-toimintoa)\n" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "OPR_ADD (lisää)\n" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "OPR_SUB (vähennä)\n" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "OPR_MUL (kerro)\n" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "OPR_DIV (jaa)\n" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "OPR_AND (looginen ja)\n" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "OPR_IOR (looginen kattava tai)\n" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "OPR_EOR (loogisesti poissulkeva tai)\n" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "OPR_NEG (kieltävä)\n" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "OPR_COM (komplementti)\n" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "OPR_INSV (lisää kenttä)\n" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "OPR_ASH (aritmeettinen sivuttaissiirto)\n" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "OPR_USH (etumerkitön sivuttaissiirto)\n" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "OPR_ROT (pyöritä)\n" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "OPR_SEL (valitse)\n" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "OPR_REDEF (määritä symboli uudelleen nykyiseen paikkaan)\n" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "OPR_REDEF (määritä literaali)\n" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "STC_LP (tallenna ehdollinen linkityspari)\n" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "STC_LP_PSB (tallenna ehdollinen linkityspari + tuntomerkki)\n" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr " linkitysindeksi: %u, proseduuri: %.*s\n" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr " tuntomerkki: %.*s\n" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "STC_GBL (tallenna ehdollinen yleinen)\n" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr " linkitysindeksi: %u, yleinen: %.*s\n" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "STC_GCA (tallenna ehdollinen koodiosoite)\n" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr " linkitysindeksi: %u, proseduurinimi: %.*s\n" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "STC_PS (tallenna ehdollinen psect + siirros)\n" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr " linkitysindeksi: %u, psect: %u, siirros: 0x%08x %08x\n" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "STC_NOP_GBL (tallenna ehdollinen NOP yleisosoitteessa)\n" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "STC_NOP_PS (tallenna ehdollinen NOP kohteessa psect + siirros)\n" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "STC_BSR_GBL (tallenna ehdollinen BSR yleisosoitteessa)\n" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "STC_BSR_PS (tallenna ehdollinen BSR kohteessa psect + siirros)\n" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "STC_LDA_GBL (tallenna ehdollinen LDA yleisosoitteessa)\n" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "STC_LDA_PS (tallenna ehdollinen LDA kohteessa psect + siirros)\n" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "STC_BOH_GBL (tallenna ehdollinen BOH yleisosoitteessa)\n" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "STC_BOH_PS (tallenna ehdollinen BOH kohteessa psect + siirros)\n" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "STC_NBH_GBL (tallenna ehdollinen tai vihje yleisosoitteessa)\n" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "STC_NBH_PS (tallenna ehdollinen tai vihje kohteessa psect + siirros)\n" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "CTL_SETRB (aseta sijoituskanta)\n" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "CTL_AUGRB (lisäyssijoituskanta) %u\n" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "CTL_DFLOC (määritä paikka)\n" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "CTL_STLOC (aseta paikka)\n" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "CTL_STKDL (pinomääritelty paikka)\n" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "*käsittelemätön*\n" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "ei voida lukea GST-tietuepituutta\n" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "ei voi löytää kohdetta EMH ensimmäisessä GST-tietueessa\n" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "ei voida lukea GST-tietueotsaketta\n" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr " rikkoutunut kohde GST\n" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "ei voida lukea GST-tietuetta\n" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr " käsittelemätön EOBJ-tietuetyyppi %u\n" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr " bittilukumäärä: %u, perusosoite: 0x%08x\n" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr " bitmap: 0x%08x (lukumäärä: %u):\n" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr " %08x" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr " vedos %u (%u alkiota)\n" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr " siirros: 0x%08x, arvo: 0x%08x\n" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr " vedos %u (%u alkiota), siirrokset:\n" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr " 0x%08x" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "64 bittinen *käsittelemätön*\n" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "luokka: %u, dtype: %u, pituus: %u, osoitin: 0x%08x\n" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "ei-yhtenäinen %s-taulukko\n" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "dimct: %u, a-liput: 0x%02x, numerot: %u, skaala: %u\n" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "arsize: %u, a0: 0x%08x\n" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "Askeleet:\n" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "[%u]: %u\n" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "Rajat:\n" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "[%u]: Alempi: %u, ylempi: %u\n" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "tasaamaton %s-bittimerkkijono\n" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "kanta: %u, paikka: %u\n" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "v-liput: 0x%02x, arvo: 0x%08x " + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "(ei arvoa)\n" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "(ei käytössä)\n" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "(ei varattu)\n" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "(kuvaaja)\n" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "(jälkiarvo)\n" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "(arvomäärittely seuraa)\n" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "(bittisiirroksessa %u)\n" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "(rekisteri: %u, sijoitus: %u, suunta: %u, tyyppi: " + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "literaali" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "osoite" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "kuvaus" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "rekisteri" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "Vianjäljityssymbolitaulu:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "ei voida lukea DST-otsaketta\n" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr " tyyppi: %3u, pituus: %3u (osoitteessa 0x%08x): " + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "ei voida lukea DST-symbolia\n" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "vakiotiedot: %s\n" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr " nimi: %.*s\n" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "modbeg-alku\n" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr " liput: %d, kieli: %u, major: %u, minor: %u\n" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr " modulinimi: %.*s\n" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr " kääntäjä : %.*s\n" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "modend-loppu\n" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "rtnbeg-alku\n" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr " liput: %u, osoite: 0x%08x, pd-osoite: 0x%08x\n" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr " rutiininimi: %.*s\n" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "rtnend-loppu: koko 0x%08x\n" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "prolog: bkpt-osoite 0x%08x\n" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "epilog: liput: %u, lukumäärä: %u\n" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "blkbeg-alku: osoite: 0x%08x, nimi: %.*s\n" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "blkend-loppu: koko: 0x%08x\n" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "typspec (pituus: %u)\n" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "septyp, nimi: %.*s\n" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "recbeg-alku: nimi: %.*s\n" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "recend-loppu\n" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "enumbeg-alku, pituus: %u, nimi: %.*s\n" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "enumelt, nimi: %.*s\n" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "enumend-loppu\n" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "ei-yhtenäinen lukualue (numero: %u)\n" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr " osoite: 0x%08x, koko: %u\n" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "rivinumero (pituus: %u)\n" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "delta_pc_w %u\n" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "incr_linum(b): +%u\n" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "incr_linum_w: +%u\n" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "incr_linum_l: +%u\n" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "set_line_num(w) %u\n" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "set_line_num_b %u\n" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "set_line_num_l %u\n" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "set_abs_pc: 0x%08x\n" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "delta_pc_l: +0x%08x\n" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "term(b): 0x%02x" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "term_w: 0x%04x" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "delta pc +%-4d" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr " pc: 0x%08x rivi: %5u\n" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *käsittelemätön* komento %u\n" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "lähde (pituus: %u)\n" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr " declfile: pituus: %u, liput: %u, tiedostotunniste: %u\n" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr " tiedostonimi: %.*s\n" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr " setfile %u\n" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr " setrec %u\n" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr " setlnum %u\n" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr " deflines %u\n" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr " formfeed\n" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *käsittelemätön* komento %u\n" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "*käsittelemätön* kohdetyyppi %u\n" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "ei voida lukea kohdetta EIHD\n" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "EIHD: (koko: %u, nbr lohkoa: %u)\n" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr " majorid: %u, minorid: %u\n" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "suoritettava tiedosto" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "linkitettävä vedos" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr " vedostyyppi: %u (%s)" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "kotoperäinen" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "CLI" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr ", alityyppi: %u (%s)\n" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr " siirrokset: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr " korjaustiedot rva: " + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr ", symbolivektori rva: " + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" +"\n" +" versiotaulukkosiirros: %u\n" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr " img I/O lukumäärä: %u, kanavien lukumäärä: %u, req pri: %08x%08x\n" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr " linkkeriliput: %08x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr " ident: 0x%08x, sysver: 0x%08x, täsmää ctrl: %u, symvect_size: %u\n" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr " BPAGE: %u" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr ", ext korjaussiirros: %u, no_opt psect -siirros: %u" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr ", alias: %u\n" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "järjestelmäversion taulukkotiedot:\n" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "ei voida lukea EIHVN-otsaketta\n" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "ei voida lukea EIHVN-versiota\n" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr " %02u " + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "PERUS_VEDOS " + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "MUISTI_HALLINTA " + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "SIIRRÄNTÄ " + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "TIEDOSTOT_TALTIOT" + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "PROSESSI_AIKAT. " + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "SYSGEN " + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "KLUSTERIEN_LUKOT " + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "LOOGISET_NIMET " + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "TURVALLISUUS " + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "VEDOS_AKTIVOIJA " + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "VERKOT " + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "LASKURIT " + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "STABIILI " + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "SEKALAISET " + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "PROSESSORI " + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "KATOAVA " + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "KUORI " + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "POSIX " + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "MONI_PROSESSOINTI" + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "GALAKSI " + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "*tuntematon* " + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr ": %u.%u\n" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "ei voida lukea kohdetta EIHA\n" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "Vedosaktivointi: (koko=%u)\n" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr " Ensimmäinen osoite : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr " Toinen osoite : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr " Kolmas osoite : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr " Neljäs osoite : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr " Jaettu vedos : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "ei voida lukea kohdetta EIHI\n" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "Vedostunnistus: (major: %u, minor: %u)\n" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr " vedosnimi : %.*s\n" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr " linkitysaika : %s\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr " vedossisennys : %.*s\n" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr " linkkeri-ident : %.*s\n" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr " vedoksen rakennusident: %.*s\n" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "ei voida lukea kohdetta EIHS\n" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "Vedossymboli- ja vianjäljitystaulu: (major: %u, minor: %u)\n" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr " vianjäljityssymbolitaulu : vbn: %u, koko: %u (0x%x)\n" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr " yleinen symbolitaulu: vbn: %u, tietueet: %u\n" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr " vianjäljitysmodulitaulu : vbn: %u, koko: %u\n" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "ei voida lukea kohdetta EISD\n" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "Vedoslohkokuvaaja: (major: %u, minor: %u, koko: %u, siirros: %u)\n" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr " lohko: kanta: 0x%08x%08x koko: 0x%08x\n" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr " liput: 0x%04x" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr " vbn: %u, pfc: %u, matchctl: %u tyyppi: %u (" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "NORMAALI" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "SHRFXD" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "PRVFXD" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "SHRPIC" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "PRVPIC" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "USRSTACK" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr " ident: 0x%08x, nimi: %.*s\n" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "ei voida lukea kohdetta DMT\n" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "Vianjäljitysmodulitaulu:\n" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "ei voida lukea DMT-otsaketta\n" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr " modulisiirros: 0x%08x, koko: 0x%08x, (%u psects)\n" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "ei voida lukea kohdetta DMT psect\n" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr " psect-alku: 0x%08x, pituus: %u\n" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "ei voida lukea kohdetta DST\n" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "ei voida lukea kohdetta GST\n" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "Yleinen symbolitaulu:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "Vedosaktivaattorikorjaus: (major: %u, minor: %u)\n" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr " iaflink : 0x%08x %08x\n" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr " fixuplnk: 0x%08x %08x\n" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr " koko : %u\n" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr " liput: 0x%08x\n" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr " qrelfixoff: %5u, lrelfixoff: %5u\n" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr " qdotadroff: %5u, ldotadroff: %5u\n" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr " codeadroff: %5u, lpfixoff : %5u\n" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr " chgprtoff : %5u\n" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr " shlstoff : %5u, shrimgcnt : %5u\n" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr " shlextra : %5u, permctx : %5u\n" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr " base_va : 0x%08x\n" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr " lppsbfixoff: %5u\n" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr " Jaettavat vedokset:\n" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr " %u: koko: %u, liput: 0x%02x, nimi: %.*s\n" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr " quad-sanaiset sijoituskorjaukset:\n" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr " long-word-sijoituskorjaukset:\n" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr " quad-word .address -viitekorjaukset:\n" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr " long-word .address -viitekorjaukset:\n" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr " Koodiosoiteviitekorjaukset:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr " Linkitysparien viitekorjaukset:\n" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr " Vaihda suoja (%u alkiota):\n" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr " kanta: 0x%08x %08x, koko: 0x%08x, prot: 0x%08x " + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "%P: sijoitettava linkki ei ole tuettu\n" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "%P: useita tulokohtia: moduuleissa %B ja %B\n" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "ei voitu avata jaettua vedosta '%s' kohteesta '%s'" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted kutsuttu nollatavuilla" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted kutsuttu liian monilla tavuilla" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF jaettu objekti kun ei tuoteta XCOFF-tulostetta" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: dynaaminen objekti ilman â€.loaderâ€-lohkoa" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: â€%s†on rivinumerot, mutta ei sulkevaa lohkoa" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: luokassa %d symbolissa â€%s†ei ole aputulokohtia" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: symbolissa â€%s†on tunnistamaton ohjauslohkotyyppi %d" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: virheellinen XTY_ER-symboli â€%sâ€: luokka %d ohjauslohkonumero %d ohjauslohkopituus %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: XMC_TC0-symboli â€%s†on luokka %d ohjauslohkopituus %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: ohjauslohkoa â€%s†ei ole sulkeutuvassa lohkossa" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: väärin sijoitettu XTY_LD â€%sâ€" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: reloc-tietue %s:%d ei ole ohjauslohkossa" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: tuntematon symboli" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "varoitus: yritettiin viedä määrittelemätön symboli â€%sâ€" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "virhe: määrittelemätön symboli â€__rtinitâ€" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: â€loader relocâ€-tietue tunnistamattomassa lohkossa â€%s" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: â€%s†â€loader relocâ€-tietueessa, mutta ei â€loader.symâ€-binaarissa" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: â€loader relocâ€-tietue kirjoitussuojatussa lohkossa %A" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "Sisältöluettelon ylivuoto: 0x%lx > 0x10000; yritä â€-mminimal-toc†käännettäessä" + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Ei voi avartaa br-käskyä kohteessa 0x%lx lohkossa â€%Aâ€. Käytä â€brlâ€-käskyä tai epäsuoraa haarautumista." + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "â€@pltoff relocâ€-tietue paikallista symbolia varten" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: â€shortâ€-datasegmentti ylivuotanut (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: â€__gp†ei kata â€shortâ€-datasegmenttiä" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: paikkariippuvainen koodi välittömällä sijoituksella dynaamista symbolia â€%s†varten" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: â€@gprelâ€-sijoitus dynaamista symbolia %s varten" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: linkitetään paikkariippuvainen koodi paikkariippumattomassa suoritettavassa tiedostossa" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: @sisäinen haarautuminen dynaamiseen symboliin %s" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: spekulaatiokorjaus dynaamiseen symboliin %s" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: â€@pcrelâ€-sijoitus dynaamista symbolia %s varten" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "ei-tuettu reloc-tietue" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: siirroksen %s puuttuva TLS-lohko kohdetta â€%s†varten osoitteessa 0x%lx lohkossa â€%Aâ€." + +# Kun käskyoperandi on sen lukualueen ulkopuolella, joka sallitaan kullekin käskykentälle, +# assembler voi muuntaa koodin käyttämään toiminnallisesti samanlaista käskyä tai käskysekvenssiä. +# Tämä prosessi tunnetaan nimellä relaxation. Tätä tehdään tyypillisesti haarautumiskäskyissä, koska +# haarautumiskohteen etäisyyttä ei tunneta ennen linkitystä. Tavallaan tällä tavalla kumotaan lukualueen +# rajoitteet (constraints). Siksi olen suomentanut sen termillä avartaminen. +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: Ei voi avartaa br-käskyä (%s) kohteelle â€%s†kohteessa 0x%lx lohkossa â€%A†koolla 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: linkitetään keskeytysnollassa uudelleenviite â€ei-keskeytetäâ€-tiedostojen kanssa" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: linkitetään â€big-endianâ€-tiedostoja â€little-endianâ€-tiedostojen kanssa" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: linkitetään 64-bittiset tiedostot 32-bittisten tiedostojen kanssa" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: linkitetään vakioyleisosoitintiedostot ei-vakioiden yleisosoitintiedostojen kanssa" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: linkitetään automaattiset paikkariippumattomat kooditiedostot ei-automaattisten paikkariippumattomien kooditiedostojen kanssa" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: rivinumeroylivuoto: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Vientihakemisto [.edata (tai missä sen sitten löysimmekin)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Tuontihakemisto [â€.idataâ€-osat]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "Resurssihakemisto [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "Poikkeushakemisto [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "Turvallisuushakemisto" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "Perussijoitushakemisto [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "Virheenetsintähakemisto" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "Kuvaushakemisto" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "Erityishakemisto" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "Säievarastohakemisto [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "Lataa konfigurationhakemisto" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "Sidottu tuontihakemisto" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "Tuontiosoitetauluhakemisto" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "Viivetuontihakemisto" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "CLR ajoaikaotsake" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "Varattu" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Tuontitaulu löytyi, mutta ei lohkoa, joka sisältää sen\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Tuontitaulu lohkossa %s osoitteessa 0x%lx\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Funktiokuvaaja sijaitsi alkuosoitteessa: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tkoodipohja %08lx sisältöluettelo (ladattava/todellinen) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Ei reldata-lohkoa! Funktiokuvaaja ei ole koodattu.\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Tuontitaulut (tulkittu %s lohkosisältö)\n" + +# Taulukko-otsake, jossa sanat on kahdella rivillä (ilman tavuviivaa), esimerkiksi: Vihjetaulu +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Vihje- Aika- Jatkoläh. DLL- Ensimmäinen\n" +" taulu leima ketju nimi Thunk-funktio\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL-nimi: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Vihje/Jär Jäsen-Nimi Sidottu\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Ensimmäinen thunk-funktio löytyi, mutta ei sen sisältävää lohkoa\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Vientitaulu löytyi, mutta ei sen sisältävää lohkoa\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Vientitaulu kohteessa %s, mutta ei sovi tuohon lohkoon\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Vientitaulu lohkossa %s osoitteessa 0x%lx\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Vientitaulut (tulkittu %s lohkosisältö)\n" +"\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Vientiliput \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Aika/Päivämääräleima \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Suurempi/Pienempi \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Nimi \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Järjestyslukukanta \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "Numero kohteessa:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tVientiosoitetaulu \t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Nimiosoitin/Järjestysnumero] taulu\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "Tauluosoitteet\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tVientiosoitetaulu \t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tNimiosoitintaulu \t\t" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tJärjestysnumerotaulu \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Vientiosoitetaulu -- Järjestyslukukanta %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "Jatkolähetyksen suhteellinen muuttujaosoite" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "Viennin suhteellinen muuttujaosoite" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Järjestysnumero/Nimiosoitin] Taulu\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Varoitus,†.pdataâ€-lohkokoko (%ld) ei ole %d:n monikerta\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tAlkuosoite Loppuosoite Unwind-tiedot\n" + +# Taulukko-otsake, jossa sanat jakautuvat taas alekkain kahdelle riville ilman tavuviivoja +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tAlku- Loppu- EH-käsit- EH- PrologEnd Poikkeus-\n" +" \t\tosoite osoite telijä data osoite peite\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " Rekisteri tallentaa millicode-bitin" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " Rekisteri palauttaa millicode-bitin" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " Vihje-koodisekvenssi" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tAlku- Prologi- Funktio- Liput Poikkeus- EH-\n" +" \t\tosoite pituus pituus 32b exc käsittelijä Data\n" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"PE-tiedostokantasijoitukset (tulkittu â€.relocâ€-lohkosisältö)\n" + +# Esimerkiksi välimuistissa RAM-alue koostuu usein pienistä palasista, joita kutsutaan nimellä chunk. Suomensin sen tässä sanalla alilohko +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Virtuaaliosoite: %08lx alilohkokoko %ld (0x%lx) Korjausten lukumäärä %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\treloc-tietue %4d siirrososoite %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Luonteenominaisuus 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: DataDictionary[1]:ia ei voi täyttää, koska â€.idata$2†puuttuu" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: DataDictionary[1]:ia ei voi täyttää, koska â€.idata$4†puuttuu" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: DataDictionary[12]:ia ei voi täyttää, koska â€.idata$5†puuttuu" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)]:ia ei voi täyttää, koska â€.idata$6†puuttuu" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "%B: DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)]:ia ei voi täyttää, koska â€.idata$6†puuttuu" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: DataDictionary[9]:ia ei voi täyttää, koska â€__tls_used†puuttuu" + +#~ msgid "Can't Make it a Short Jump" +#~ msgstr "Sitä ei voi tehdä lyhyeksi hypyksi" + +#~ msgid "Exceeds Long Jump Range" +#~ msgstr "Ylittää pitkän hypyn arvoalueen" + +#~ msgid "Absolute address Exceeds 16 bit Range" +#~ msgstr "Absoluuttinen osoite ylittää 16-bittialueen" + +#~ msgid "Absolute address Exceeds 8 bit Range" +#~ msgstr "Absoluuttinen osoite ylittää 8-bittialueen" + +#~ msgid "Unrecognized Reloc Type" +#~ msgstr "Tunnistamaton Reloc-tyyppi" + +#~ msgid "corrupt or empty %s section in %B" +#~ msgstr "rikkinäinen tai tyhjä %s-lohko kohteessa %B" + +#~ msgid "%s: invalid DSO for symbol `%s' definition" +#~ msgstr "%s: virheellinen DSO symbolin â€%s†määrittelylle" + +#~ msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%B: %A+0x%lx: hyppää stub-rutiiniin, joka ei ole jal-käsky" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "bfd_make_section (%s) ei onnistunut" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) ei onnistunut" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "Kokotäsmäämätön lohko %s=%lx, %s=%lx" + +#~ msgid "failed to enter %s" +#~ msgstr "ei onnistuttu kirjoittamaan %s" + +#~ msgid "No Mem !" +#~ msgstr "Ei muistia !" + +#~ msgid "reserved STO cmd %d" +#~ msgstr "varattu STO-komento %d" + +#~ msgid "reserved OPR cmd %d" +#~ msgstr "varattu OPR-komento %d" + +#~ msgid "reserved CTL cmd %d" +#~ msgstr "varattu CTL-komento %d" + +#~ msgid "reserved STC cmd %d" +#~ msgstr "varattu STC-komento %d" + +#~ msgid "stack-from-image not implemented" +#~ msgstr "stack-from-image ei ole toteutettu" + +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "stack-entry-mask ei ole täysin toteutettu" + +#~ msgid "PASSMECH not fully implemented" +#~ msgstr "PASSMECH ei ole täysin toteutettu" + +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "stack-local-symbol ei ole täysin toteutettu" + +#~ msgid "stack-literal not fully implemented" +#~ msgstr "stack-literal ei ole täysin toteutettu" + +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "stack-local-symbol-entry-point-mask ei ole täysin toteutettu" + +#~ msgid "%s: not fully implemented" +#~ msgstr "%s: ei ole täysin toteutettu" + +#~ msgid "obj code %d not found" +#~ msgstr "obj-koodia %d ei löytynyt" + +#~ msgid "Reloc size error in section %s" +#~ msgstr "Reloc-kokovirhe lohkossa %s" + +#~ msgid "ERROR: %B: Incompatible object tag '%s':%d" +#~ msgstr "VIRHE: %B: Yhteensopimaton objektitunnus â€%sâ€:%d" + +#~ msgid "%B(%A): warning: unresolvable relocation against symbol `%s'" +#~ msgstr "%B(%A): varoitus: ratkaisematon sijoitus symbolia â€%s†varten" + +#~ msgid "%B: Internal inconsistency; no relocation section %s" +#~ msgstr "%B: Sisäinen epäjohdonmukaisuus; ei sijoituslohkoa %s" + +#~ msgid "Could not find relocation section for %s" +#~ msgstr "Ei löytynyt sijoituslohkoa kohteelle %s" + +#~ msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d" +#~ msgstr "%B: Yleissiirrostaulun ylivuoto: R_68K_GOT8O- ja R_68K_GOT16O-sijoitusten lukumäärä > %d" + +#~ msgid "%A link_order not found\n" +#~ msgstr "%A link_order ei löytynyt\n" + +#~ msgid "%s: no symbol \"%s\"" +#~ msgstr "%s: ei symbolia â€%sâ€" + +#~ msgid "%s: loader reloc in unrecognized section `%s'" +#~ msgstr "%s: â€loader relocâ€-tietue tunnistamattomassa lohkossa â€%sâ€" + +#~ msgid "%s: `%s' in loader reloc but not loader sym" +#~ msgstr "%s: â€%s†â€loader relocâ€-tietueessa, mutta ei â€loader.symâ€-binaarissa" + +#~ msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +#~ msgstr "Dwarf-virhe: DW_FORM_strp siirrososoite (%lu) suurempi tai sama kuin â€.debug_strâ€-koko (%lu)." + +#~ msgid "Dwarf Error: Can't find .debug_abbrev section." +#~ msgstr "Dwarf-virhe: Ei löydy â€.debug_abbrevâ€-lohkoa." + +#~ msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +#~ msgstr "Dwarf-virhe: Lyhennesiirrososoite (%lu) suurempi tai sama kuin â€.debug_abbrevâ€-koko (%lu)." + +#~ msgid "Dwarf Error: Can't find .debug_ranges section." +#~ msgstr "Dwarf-virhe: Ei löydy â€.debug_rangesâ€-lohkoa." + +#~ msgid "ERROR: %B: Conflicting definitions of wchar_t" +#~ msgstr "VIRHE: %B: Ristiriitaisia wchar_t-määrittelyjä" + +#~ msgid "%B: relocation R_X86_64_PC32 against protected function `%s' can not be used when making a shared object" +#~ msgstr "%B: sijoitusta R_X86_64_PC32 suojattua funktiota â€%s†varten ei voida käyttää kun tehdään jaettua objektia" + +#~ msgid "%B: unable to initialize compress status for section %s" +#~ msgstr "%B: ei kyetä alustamaan tiivistystilaa lohkolle %s" + +#~ msgid "%B: unable to initialize decompress status for section %s" +#~ msgstr "%B: ei kyetä alustamaan tiivistyksenpurkutilaa lohkolle %s" + +#~ msgid "R_FRV_GETTLSOFF_RELAX not applied to a call instruction" +#~ msgstr "R_FRV_GETTLSOFF_RELAX ei sovelleta kutsukäskyyn" diff --git a/external/gpl3/gdb/dist/bfd/po/fr.gmo b/external/gpl3/gdb/dist/bfd/po/fr.gmo new file mode 100644 index 0000000000000000000000000000000000000000..2a73a5311444b2ea73a732e1351b7e6ada9207aa GIT binary patch literal 142671 zcmcGX1$aadSv;s1Q+opU8kk^Sxed_E`78J~IQ9X)ey-rSz?01`R}}krMDvtFi(PtcXz08`$6U7RH%Gh4Y!8(!9nm9xD#x*A`%%3C&LM_ z8Fq!&!5Q!Y@7|#%63ND#1INI9;2d~890>mdXTtuqkw`wQhqAxZn?HozF^{UVe9eZ_ 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a/external/gpl3/gdb/dist/bfd/po/fr.po b/external/gpl3/gdb/dist/bfd/po/fr.po new file mode 100644 index 000000000000..6580675e9d3f --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/fr.po @@ -0,0 +1,6035 @@ +# Messages français pour GNU concernant bfd. +# Copyright © 2010 Free Software Foundation, Inc. +# This file is distributed under the same license as the binutils package. +# Michel Robitaille , traducteur depuis/since 1996. +# Frédéric Marchal , 2010. +msgid "" +msgstr "" +"Project-Id-Version: bfd-2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2010-11-11 20:08+0100\n" +"Last-Translator: Frédéric Marchal \n" +"Language-Team: French \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=2; plural=(n > 1);\n" +"X-Generator: Lokalize 1.0\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Type de section inconnu dans le fichier a.out.adobe: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: relocalisation invalide du type exporté: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Relocalisation invalide du type importé: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Mauvais enregistrement de relocalisation importé: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: ne peut représenter la section «%s» dans le fichier format objet a.out" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: ne peut représenter la section pour le symbole «%s» dans le fichier format objet a.out" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*inconnu*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: type de relocalisation non supporté\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: lien relocalisable de %s vers %s n'est pas supporté" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Attention: l'écriture de l'archive était lente: réécriture du cachet de date-heure\n" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "Lecture du cachet date-heure modifié du fichier d'archive" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "Écriture du cachet date-heure armap mise à jour" + +#: bfd.c:395 +msgid "No error" +msgstr "Pas d'erreur" + +#: bfd.c:396 +msgid "System call error" +msgstr "Erreur d'appel système" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "Cible bfd invalide" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "Fichier dans un mauvais format" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "Fichier objet d'archive dans un mauvais format" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "Opération invalide" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "Mémoire épuisée" + +#: bfd.c:402 +msgid "No symbols" +msgstr "Aucun symbole" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "L'archive n'a pas d'index; exécuter ranlib pour en ajouter un" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "Aucun autre fichier d'archive" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "Archive mal formée" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "Format de fichier non reconnu" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "Format de fichier ambigu" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "Section sans contenu" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "Section non-représentable sur la sortie" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "Symboles ont besoin de la section de débug qui est inexistente" + +#: bfd.c:411 +msgid "Bad value" +msgstr "Mauvaise valeur" + +#: bfd.c:412 +msgid "File truncated" +msgstr "Fichier tronqué" + +#: bfd.c:413 +msgid "File too big" +msgstr "Fichier trop gros" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "Erreur lors de la lecture de %s: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD assertion %s a échoué %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD erreur interne %s, abandon à %s, ligne %d dans %s\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD erreur interne %s, abandon à %s, ligne %d\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "Merci de rapporter cette anomalie.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "pas de table de projection: données=%lx adresse de la table=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "pas de table de projection: variable d'environnement pas initialisée\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Attention: Écriture de la section «%s» vers un énorme décalage (ie négatif) dans le fichier 0x%lx." + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax et -r ne peuvent pas être utilisés en même temps\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "réouverture de %B: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Les binaires compressés pour Alpha ne sont pas supportés.\n" +" Utilisez les options du compilateur ou objZ pour produire des binaires non compressés." + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: type de relocalisation %d inconnu ou non supporté" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "Relocalisation relative GP utilisé alors que GP n'est pas défini" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "utilisation de valeurs gp multiples" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: type de relocalisation non supporté: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: type de relocalisation non supporté: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: type de relocalisation %d inconnu" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: incapable de repérer le REPÈRE de liant «%s» pour «%s»" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: incapable de repérer le liant ARM «%s» pour «%s»" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): attention: l'inter-réseautage n'est pas activé.\n" +" première occurrence: %B: appel arm au repère" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): attention: l'inter-réseautage n'est pas activé.\n" +" première occurrence: %B: appel arm au repère\n" +" reliez avec --support-old-code activé" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: mauvaise adresse de relocalisation 0x%lx dans la section «%A»" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: symbole index illégal dans la relocalisation: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "erreur: %B compilé pour APCS-%d alors que %B a été compilé pour APCS-%d" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "erreur: %B passage de valeurs en virgule flottante dans les registres FP alors que %B les passe dans les registres entiers" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "erreur: %B passage de valeurs en virgule flottante dans les registres entiers alors que %B les passe dans les registres FP" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "erreur: %B compilé avec du code à position indépendante alors que la cible %B est à position absolue" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "erreur: %B compilé avec du code à position absolu alors que la cible %B est à position indépendante" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Attention: %B supporte l'inter-réseautage, contrairement à %B" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Attention: %B ne supporte pas l'inter-réseautage, contrairement à %B" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "fanions privés = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [valeurs en virgule flottante passées dans des registres de valeurs en virgule flottante]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [valeurs en virgule flottante passées dans des registres de valeurs entières]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr " [position indépendante]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr " [position absolue]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [fanion d'inter-réseautage n'a pas été initialisé]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr " [inter-réseautage supporté]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr " [inter-réseautage non supporté]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Attention: Pas d'initialisation du fanion d'inter-réseautage de %B puisqu'il a déjà été spécifié sans inter-réseautage" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Attention: Mise à zéro du fanion d'inter-réseautage de %B en raison d'une requête externe" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "ne peut traiter la relocalisation R_MEM_INDIRECT lorsque %s est utilisé en sortie" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Relocalisation «%s» pas encore implémentée\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: attention: symbole index illégal %ld dans les relocalisations" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "convention d'appel incertaine pour un symbole non COFF" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "type de relocalisation non supporté" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "relocalisation relative GP sans que _gp ne soit défini" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "Relocalisation non reconnue" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: type de relocalisation non supporté 0x%02x" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: table des matières des relocalisations à 0x%x pour le symbole «%s» sans aucune entrée" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: symbole «%s» a une classe smclas %d non reconnue" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Type de relocalisation non reconnu 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: attention: symbole index illégal %ld dans les relocalisations" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "relocalisation %s ignorée\n" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: attention: symbole COMDAT «%s» ne concorde par avec le nom de section «%s»" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Attention: Ignore le fanion de section IMAGE_SCN_MEM_NOT_PAGED dans la section %s" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Fanion de section %s (0x%x) ignoré" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Identificateur de cible TI COFF non reconnu «0x%x»" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: relocalisation par rapport à un indexe de symbole inexistant: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: trop de sections (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: section %s: débordement de la table de chaînes à l'offset %ld" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: attention: erreur lors de la lecture de la table des numéros de ligne" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: attention: symbole d'index illégal %ld dans les numéros de ligne" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: attention: information de numéro de ligne dédoublée pour «%s»" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: Classe de stockage %d non reconnue pour %s symbole «%s»" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "attention: %B: symbole local «%s» n'a pas de section" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: type de relocalisation %d illégal à l'adresse 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: mauvaise taille de la table des chaînes %lu" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Attention: type de symbole «%s» a changé de %d à %d dans %B" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: relocalisations dans la section «%A» qui est vide" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: débordement de relocalisation: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: attention: %s: débordement du compteur de numéro de ligne: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "erreur: %B compilé pour EP9312 alors que %B a été compilé pour XScale" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "attention: incapable de mettre à jour le contenu de la section %s dans %s" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Erreur DWARF: ne peut repérer la section %s" + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Erreur DWARF: décalage de ligne (%lu) est >= à la taille de %s (%lu)" + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Erreur DWARF: valeur de FORME invalide ou non supportée: %u" + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Erreur DWARF: numéro de ligne de section mutilé (mauvais no. de fichier)" + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Erreur DWARF: Version .debug_line %d non prise en charge." + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Erreur DWARF: Opérations maximum par instruction invalide." + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Erreur DWARF: numéro de ligne de section mutilé" + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Erreur DWARF: ne peut repérer le numéro abrégé %u" + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Erreur DWARF: version DWARF trouvée «%u», ce lecteur ne supporte que les informations des versions 2, 3 et 4." + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Erreur DWARF: taille d'adresse obtenue «%u», ce lecteur ne peut traiter des tailles plus grandes que «%u»." + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Erreur DWARF: mauvais numéro abrégé: %u" + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "Type de base %d inconnu" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Dernier+1 symbole: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Premier symbole: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Dernier+1 symbole: %-7ld Type: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Symbole local: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; Symbole Fin+1: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; Dernier+1 symbole: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Dernier+1 symbol: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Type: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "erreur: %B: L'objet a un contenu spécific à un vendeur qui doit être traité par la chaîne d'outils «%s»" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "erreur: %B: Étiquette d'objet «%d, %s» incompatible avec l'étiquette «%d, %s»" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: erreur dans %B(%A); aucune table .eh_frame_hdr ne sera créée.\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: encodage fde dans %B(%A) empêche la création de la table .eh_frame_hdr.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%P%P: symbole dynamique STT_GNU_IFUNC «%s» avec une égalité de pointeur dans «%B» ne peut pas être utilisé lors de la création d'un exécutable. Recompilez avec -fPIE et reliez avec -pie\n" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "erreur interne: hors limite" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "erreur interne: erreur de relocalisation non supportée" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "erreur interne: erreur dangereuse" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "erreur interne: erreur inconnue" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): relocalisation %s sans solution vers le symbole «%s»" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "erreur: type de relocalisation inapproprié pour une librairie partagée (avez vous oublié -fpic ?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "erreur interne: type de relocalisation douteux utilisé dans une librairie partagée" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "la variable dynamique «%s» a une taille nulle" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: chaîne de décalage invalide %u >= %lu pour la section «%s»" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B le symbole numéro %lu fait référence à une section SHT_SYMTAB_SHNDX inexistante" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Champ de taille corrompu dans l'en-tête du groupe de section: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: entrée SHT_GROUP invalide" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: aucune info de groupe pour la section %A" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: attention: sh_link n'a pas de valeur pour la section «%A»" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%d] n'est pas correct dans la section «%A»" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: [%d] inconnu dans la section «%s» du groupe [%s]" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: impossible d'initialiser le statut de compression de la section %s" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: impossible d'initialiser le statut de décompression de la section %s" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"En-tête de programme:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Section dynamique:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Définitions des versions:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Références de version:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " requis par %s:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: lien invalide %lu pour la section de relocalisation %s (index %u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: je ne sais pas comment traiter la section «%s» [0x%8x] allouée et spécifique à l'application" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: je ne sais pas comment traiter la section «%s» [0x%8x] spécifique au processeur" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: je ne sais pas comment traiter la section «%s» [0x%8x] spécifique au système d'exploitation" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: je ne sais pas comment traiter la section «%s» [0x%8x]" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "attention: type de la section «%A» changé en PROGBITS" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: le sh_link de la section «%A» pointe vers la section abandonnée «%A» de «%B»" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: le sh_link de la section «%A» pointe vers la section supprimée «%A» de «%B»" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: La première section dans le segment PT_DYNAMIC n'est pas la section .dynamic" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: Pas suffisamment d'espace pour les en-têtes du programme, essayer l'option -N" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "%B: section %A avec lma %#lx ajustée à %#lx" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: la section «%A» ne peut pas être allouée dans le segment %d" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: attention: section allouée «%s» n'est pas dans le segment" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: symbole «%s» requis mais absent" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: attention: segment chargeable vide détecté, est-ce intentionnel ?\n" + +#: elf.c:6622 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Incapable de trouver un équivalent pour le symbole «%s» de la section «%s»" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: type de relocalisation %s non supporté" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): attention: l'inter-réseautage n'est pas activé.\n" +" première occurrence: %B: appel de repère vers ARM" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): attention: l'inter-réseautage n'est pas activé.\n" +" première occurrence: %B: appel ARM vers repère" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: ne peut créer l'entrée d'ébauche %s" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "incapable de repérer le REPÈRE de liant «%s» pour «%s»" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "incapable de repérer le liant ARM «%s» pour «%s»" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: les images BE8 ne sont valables qu'en mode gros boutiste." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: attention: le palliatif VFP11 n'est pas nécessaire avec l'architecture cible" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: incapable de trouver le vernis VFP11 «%s»" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Type de relocalisation TARGET2 «%s» invalide" + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): attention: l'inter-réseautage n'est pas activé.\n" +" première occurrence: %B: appel de repère vers arm" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Attention: instruction Arm BLX vise la fonction Arm «%s»." + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Attention: instruction de repérage BLX vise la fonction de repérage «%s»." + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): relocalisation R_ARM_TLS_LE32 pas permise dans un objet partagé" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Seuls ADD ou SUB sont permis dans les relocalisations du groupe ALU" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Débordement en scindant 0x%lx pour la relocalisation du group %s" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s relocalisation vers une section SEC_MERGE" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s utilisé avec le symbole TLS %s" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s utilisé avec le symbole non-TLS %s" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "hors limite" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "relocalisation non supportée" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "erreur inconnue" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Attention: mise à zéro du fanion d'inter-réseautage %B en raison du code sans inter-réseautage dans %B lié avec lui" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: L'attribut d'objet EABI obligatoire %d est manquant" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Attention: %B: Attribut d'objet EABI %d inconnu" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "erreur: %B: Architecture CPU inconnue" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "erreur: %B: Architectures CPU conflictuelles %d/%d" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "Erreur: %B utilise les deux attributs Tag_MPextension_use actuel et hérité" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "erreur: %B passe les paramètres dans un registre VFP alors que %B ne le fait pas" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "erreur: %B: impossible de fusionner les attributs de visualisation avec %B" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "erreur: %B: Profils d'architecture conflictuels %c/%c" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Attention: %B: Configuration de platforme conflictuelle" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "erreur: %B: Utilisation conflictuelle de R9" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "erreur: %B: Adressage relatif SB entre en conflit avec l'utilisation de R9" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "attention: %B utilise des wchar_t de %u octets alors que la sortie doit utiliser des wchar_t de %u octets. L'utilisation de wchar_t entre objets peu échouer" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "attantion: %B utilise des enums %s alors que la sortie doit utiliser des enums %s. L'utilisation des valeurs enum entre objets peu échouer" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "erreur: %B passe les paramètres dans le registre iWMMXt contrairement à %B" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "erreur: désaccord de format fp16 entre %B et %B" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "incohérence d'utilisation de DIV entre %B et %B" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "%B utilise les deux attributs Tag_MPextension_use actuel et hérité" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "fanions privés = %lx" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [inter-réseautage autorisé]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [format flottant VFP]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [format flottant Maverick]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [format flottant FPA]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [nouvel ABI]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [ancien ABI]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [virgule flottante logiciel]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [Version1 EABI]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [table des symboles triés]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [table des symboles non triés]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [Version2 EABI]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [symboles dynamiques utilisent un index de segment]" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [mapping de symboles précèdes les autres]" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [Version3 EABI]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [Version4 EABI]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [Version5 EABI]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [exécutables relocalisés]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [a des points d'entrées]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: symbole index erroné: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relocalisation de %s en vertu de «%s» ne peut être utilisée lors de la création d'un objet partagé; recompiler avec -fPIC" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Erreurs rencontrées pendant le traitement du fichier %s" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: erreur: L'ébauche d'erratum du Cortex A8 est allouée à un emplacement peu sûr" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: erreur: L'ébauche d'erratum du Cortex A8 est hors limite (fichier d'entrée trop grand)" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: erreur: vernis VFP11 hors limite" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "erreur: %B est déjà au format final BE8" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "erreur: L'objet source %B a l'EABI version %d alors que la cible %B a l'EABI version %d" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "erreur: %B compilé pour APCS-%d alors que la cible %B utilise APCS-%d" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "erreur: %B utilise les instructions VFP alors que %B ne les utilise pas" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "erreur: %B utilise les instructions FPA alors que %B ne les utilise pas" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "erreur: %B utilise les instructions Maverick alors que %B ne les utilise pas" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "erreur: %B n'utilise pas les instructions Maverick alors que %B les utilise" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "erreur: %B utilise le logiciel pour virgule flottante alors que %B utilise le matériel pour virgule flottante" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "erreur: %B utilise le matériel pour virgule flottante alors que %B utilise le logiciel pour virgule flottante" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "erreur interne: relocalisation dangereuse" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: ne peut créer l'entrée de l'ébauche %s" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): relocalisation sans solution vers le symbole «%s»" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): relocalisation vers «%s»: erreur %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: relocalisation à «%A+0x%x» fait référence au symbole «%s» avec un opérande non nul" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "la relocalisation fait référence à un symbole non défini dans le module" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC fait référence à un symbole dynamique avec un opérande non nul" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "impossible d'apporter des corrections dans une section en lecture seule" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "impossible d'éditer les relocalisations dynamiques dans une section en lecture seule" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE fait référence à un symbole dynamique avec un opérande non nul" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "les relocalisations entre segments différents ne sont pas supportées" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "attention: relocalisation fait référence à un segment différent" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: type de relocalisation %i non supporté" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: ne peut lier un fichier objet non fdpic dans un exécutable fdpic" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: ne peut lier un fichier objet fdpic dans un exécutable non fdpic" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, section %A: relocalisation %s non résolue sur le symbole «%s»" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, section %a: Pas de PLT ni de GOT pour relocaliser %s sur le symbole «%s»" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, section %A: Pas de PLT pour relocaliser %s sur le symbole «%s»" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "[dont le nom est perdu]" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, section %A: relocalisation de %s avec un opérande non nul %d sur le symbole local" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, section %A: relocalisation de %s avec un opérande non nul %d sur le symbole «%s»" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, section %A: la relocation de %s n'est pas permise pour le symbole global: «%s»" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, section %A: relocalisation de %s sans GOT" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, section %A: relocalisation de %s a une référence non définie vers «%s», peut-être un mélange dans les déclarations ?" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, section %A: relocalisation de %s n'est pas permise pour le symbole «%s» qui est défini en dehors du programme, peut-être un mélange dans les déclarations ?" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(trop de variables globales pour -fpic: recompilez avec -fPIC)" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(donnée locale au thread trop grande pour -fpic or -msmall-tls: recompilez avec -fPIC ou -mno-small-tls)" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, section %A:\n" +" l'objet compatible v10/v32 %s ne peut pas contenir de relocalisation PIC" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, section %A:\n" +" relocalisation de %s pas valable dans un objet partagé; typiquement un mélange dans les options. Recompilez avec -fPIC" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, section %A:\n" +" relocalisation de %s ne devrait pas être utilisée dans un objet partagé; recompilez avec -fPIC" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, section «%A», vers le symbole «%s»:\n" +" relocalisation de %s ne devrait pas être utilisée dans un objet partagé; recompilez avec -fPIC" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "Numéro de machine inattendu" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [symboles sont préfixés par « _ »]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 et v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: utilise des symboles préfixés par _ mais écrits les symboles sans préfixes dans le fichier" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: utilise des symboles sans préfixe mais ajoute le préfixe _ aux symboles dans le fichier" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B contient du code CRIS v32 incompatible avec les objets précédents" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B contient du code non CRIS v32 incompatible avec les objets précédents" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "la relocalisation exige un opérande nul" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): la relocalisation en «%s+%x» peut avoir causé le problème ci-dessus" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF pas appliqué à une instruction d'appel" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 pas appliqué à une instruction lddi" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI pas appliqué à une instruction sethi" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO pas appliqué à une instruction setlo ou setlos" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX pas appliqué à une instruction ldd" + +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX pas appliqué à une instruction calll" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 pas appliqué à une instruction ldi" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI pas appliqué à une instruction sethi" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO pas appliqué à une instruction setlo ou setlos" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX pas appliqué à une instruction ld" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI pas appliqué à une instruction sethi" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO pas appliqué à une instruction setlo ou setlos" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC fait référence à un symbole dynamique avec un opérande non nul" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE fait référence à un symbole dynamique avec un opérande non nul" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): relocalisation vers «%s»: %s" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "la relocalisation fait référence à un segment différent" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: compilé avec %s et lié avec les modules qui utilisent de la relocalisation non PIC" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: compilé avec %s et lié avec les modules compilés avec %s" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: utilise différents champs e_flags (0x%lx) que les modules précédents (0x%lx)" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "fanions privés = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Relocalisation en format ELF générique (EM: %d)" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): ne peut atteindre %s, recompilez avec -ffunction-sections" + +#: elf32-hppa.c:1284 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relocalisation de %s ne peut être utilisée lors de la création d'un objet partagé; recompilez avec -fPIC" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "%B: ébauche d'exportation en double %s" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): correction %s pour insn 0x%x n'est pas supporté dans un lien non partagé" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): ne sait pas traiter %s pour %s" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr "section .got pas immédiatement après la section .plt" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: type de relocalisation %d invalide" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: Échec de la transition TLS de %s vers %s sur «%s» à 0x%lx dans la section «%A»" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: la relocalisation %s sur le symbole STT_GNU_IFUNC «%s» n'est pas gérée par %s" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: «%s» accédé à la fois comme symbole normal et comme symbole locale au thread" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: relocalisation inconnue (0x%x) dans la section «%A»" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "symbole caché" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "symbole interne" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "symbole protégé" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "symbole" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: relocalisation R_386_GOTOFF sur le symbole %s «%s» non défini ne peut pas être utilisée lors de la création d'un objet partagé" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: relocaliastion R_386_GOTOFF vers la fonction protégée «%s» ne peut pas être utilisée lors de la création d'un objet partagé" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "section de sortie rejetée: «%A»" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "relâche ip2k: table de commutation sans concordance complète des informations de relocalisation" + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "relâche ip2k: en-tête de table de commutation corrompue" + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "liaison ip2k: instruction de page manquante à 0x%08lx (cible = 0x%08lx)." + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "liaison ip2k: instruction de page redondante à 0x%08lx (cible = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "relocalisation non supporté entre les espaces d'adresses data/insn" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: utilise des champs e_flags (0x%lx) différents des modules précédents (0x%lx)" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "relocalisation relative au pointeur global sans que _gp ne soit défini" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "adresse relative du pointeur global hors limites" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "erreur interne: opérande devrait être zéro pour R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "relocalisation SDA alors que _SDA_BASE_ n'est pas définie" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: la cible (%s) de la relocalisation %s est dans la mauvaise section (%A)" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: jeu d'instructions ne concorde par avec les modules précédents" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "fanions privés = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": instructions m32r" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": instruction m32rx" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": instructions m32r2" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Référence à un symbole far «%s» utilisant la mauvaise relocalisation peut provoquer une exécution incorrecte" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "banque d'adresses [%lx:%04lx] (%lx) n'es pas dans la même banque que la banque courante d'adresses [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "référence à une banque d'adresses [%lx:%04lx] dans l'espace normal d'adresses à %04lx" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: fichiers liés compilés pour des entiers de 16 bits (-mshort) et d'autres pour des entiers de 32 bits" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: fichiers liés compilés pour des doubles de 32 bits (-fshort-double) et d'autres pour des doubles de 64 bits" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: certains fichiers liés compilés pour HCS12 avec d'autres compilés pour HC12" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: utilise des champs e_flags (0x%lx) différents des modules précédents (0x%lx)" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "double de 64 bits, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "double de 32 bits, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr " [memory=bank-model]" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr " [memory=flat]" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "inconnu" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: débordement GOT: Nombre de relocalisations avec des offsets de 8 bits > %d" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: débordement GOT: Nombre de relocalisations avec des offsets de 8 ou 16 bits > %d" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): relocalisation R_68K_TLS_LE32 pas permise dans un objet partagé" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: relocalisation %s (%d) n'est pas actuellement supportée.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Type de relocalisation %d inconnue\n" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B et %B sont pour des noyaux différents" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B et %B sont pour des configurations différentes" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "fanions privés = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: type de relocalisation %d inconnu" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: la cible (%s) de la relocalisation %s est dans la mauvaise section (%s)" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: probablement compilé sans -fPIC?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: nom de section de relocalisation erroné «%s»" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "relocalisation littérale rencontrée pour un symbole externe" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "relocalisation relative gp 32bits rencontrée pour un symbole externe" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "liaison générique ne peut traiter %s" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "section %s corrompue dans %B" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "incapable de lire dans la section %s à partir de %B" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "attention: incapable d'initialiser la taille de la section %s dans %B" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "échec d'allocation d'espace pour une nouvelle section APUinfo" + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "échec d'évaluation de la nouvelle section APUinfo" + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "échec d'installation de la nouvelle section APUinfo" + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: relocalisation %s ne peut être utilisée lors de la création d'un objet partagé" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s relocalisation vers un symbole local" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Attention: %B utilise la virgule flottante matérielle, %B utilise la virgule flottante logicielle" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Attention: %B utilise la virgule flottante double précision matérielle, %B utilise la virgule flottante simple précision matérielle" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Attention: %B utilise la virgule flottante logicielle, %B utilise la virgule flottante simple précision matérielle" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Attention: %B utilise l'ABI inconnu %d pour la gestion des virgules flottantes" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Attention: %B utilise l'ABI inconnu %d pour les vecteurs" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Attention: %B utilise l'ABI de vecteurs «%s», %B utilise «%s»" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Attention: %B utilise r3/r4 pour les retours de petites structures, %B utilise la mémoire" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Attention: %B utilise la convention inconnue %d pour le retour des petites structures" + +#: elf32-ppc.c:4197 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: compilé avec -mrelocatable et fait l'édition de lien avec les modules compilés normalement" + +#: elf32-ppc.c:4205 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: compilé normalement et fait l'édition de lien avec les modules compilés avec -mrelocatable" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "Utilisation de bss-plt à cause de %B" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: type de relocalisation %d inconnue pour le symbole %s" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): opérande non nulle sur la relocalisation %s vers «%s»" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): relocalisation %s non supportée pour la fonction indirecte %s" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: la cible (%s) d'une relocalisation %s est dans la mauvaise section de sortie (%s)" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: relocalisation %s n'est pas encore supporté pour le symbole %s." + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): relocalisation %s vers «%s»: erreur %d" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s pas défini dans %s créé par l'éditeur de liens" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%B:%A: Attention: relocalisation Red Hat réprouvée " + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "Attention: Relocalistaion RX_SYM avec un symbole inconnu" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "%B(%A): erreur: appel à la fonction non définie «%s»" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "%B(%A): attention: accès non aligné au symbole «%s» dans la zone des petites données" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "%B(%A): erreur interne: hors limite" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "%B(%A): erreur interne: relocalisation non supportée" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "%B(%A): erreur interne: relocalisation dangereuse" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "%B(%A): erreur interne: erreur inconnue" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr " [doubles de 64 bits]" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr " [dsp]" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): instruction invalide pour la relocalisation TLS %s" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "pas suffisamment d'espace GOT pour les entrées locales GOT" + +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "adresse pas alignée sur un mot" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: relocalisation mal composée détectée dans la section %s" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: appel CALL15 de relocalisation à 0x%lx n'est pas appliqué sur un symbole global" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr " [pic]" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr " [fix dep]" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: attention: édition de liens des fichiers PIC avec des fichiers non PIC" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: la directive IMPORT AS de %s masque l'IMPORT AS précédent" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: Commande .directive non reconnue: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Échec de l'ajout du symbole renommé %s" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: attention: mauvais décalage pour R_SH_USES" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: attention: R_SH_USES pointe vers un insn inconnu 0x%x" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: attention: mauvais décalage de chargement R_SH_USES" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: attention: ne peut repérer la relocalisation attendue" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: attention: symbole dans une section inattendue" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: attention: ne peut repérer le compteur de relocalisation attendu" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: attention: mauvais décompte" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: erreur fatale: débordement de relocalisation lors des relâches" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "STO_SH5_ISA32 inattendu sur le symbole local n'est pas traité" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: fatal: cible de branchement non alignée pour une relocalisatin de type relax-support" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: fatal: relocalisation %s non alignée 0x%lx" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: relocalisation R_SH_PSHA %d pas dans l'intervalle -32..32" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: relocalisation R_SH_PSHL %d n'est pas dans l'intervalle -32..32" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%B(%A+0x%lx): impossible d'apporter des corrections à «%s» dans une section en lecture seule" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%B(%A+0x%lx): %s relocalisation vers le symbole externe «%s»" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%X%C: la relocalisation vers «%s» fait référence à un segment différent\n" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%C: attention: relocalisation vers «%s» fait référence à un segment différent\n" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: «%s» accédé à la fois comme symbole normal et comme symbole FDPIC" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: «%s» accédé à la fois comme symbole FDPIC et comme symbole local au thread" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "%B: Descripteur de fonction relocalisé avec un opérande non nul" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: code exécutable local TLS ne peut être lié en objets partagés" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: compilé comme un objet de 32 bits et %s est de 64 bits" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: compilé comme un objet de 64 bits et %s est de 32 bits" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: taille de l'objet ne concorde pas avec la taille de la cible %s" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: rencontre du symbole d'une étiquette de donnée dans l'entrée" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "Non concordance PTB: adresse SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "Non concordance PTA: adresse SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: Erreur GAS: insn PTB inattendue avec R_SH_PT_16" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: erreur: type de relocalisation %d non aligné à %08x relocalisé %p\n" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: ne peut écrire en sortie des entrées .cranges ajoutées" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: ne peut écrire en sortie des entrées .cranges triées" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: compilé pour un système à 64 bits et la cible est de 32 bits" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: édition de liens pour des fichiers à octets de poids faible avec des fichiers à octets de poids fort" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: recouvrement de la section %A ne démarre pas sur une ligne de cache.\n" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: recouvrement de la section %A est plus grand que la ligne de cache.\n" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: recouvrement de la section %A n'est pas dans une zone de cache.\n" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: recouvrement des sections %A et %A ne commencent pas à la même adresse.\n" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "attention: appel au symbole %s défini dans %B qui n'est pas une fonction" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v le lrlive .brinfo (%u) diffère de celui de l'analyse (%u)\n" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "%B ne peut pas définir %s" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "vous ne pouvez pas définir %s dans un script" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "%s dans une section de recouvrement" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "débordement de la relocalisation de l'ébauche de recouvrement" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "taille des ébauches ne concorde pas avec la taille calculée" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "attention: %s recouvre %s\n" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "attention: %s dépasse la taille de la section\n" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:%0x%v pas trouvé dans la table de fonctions\n" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): appel à la section non exécutable %B(%A), analyse incomplète\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "L'analyse de la pile ignorera l'appel de %s à %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " appels:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s dupliqué dans %s\n" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "%s dupliqué\n" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "désolé, pas de support des fichiers objet dupliqués dans un script auto-overlay\n" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "la taille de non recouvrement de 0x%v plus la taille maximum de recouvrement de 0x%v dépasse l'espace local\n" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s dépasse la taille de recouvrement\n" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "Taille de la pile des nÅ“uds racine du graph d'appel.\n" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Taille de la pile pour les fonctions. Annotations: «*» pile max, «t» appel de queue\n" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "Pile maximum requise est 0x%v\n" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "erreur fatale lors de la création de .fixup" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): relocalisation %s sans solution vers le symbole «%s»" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "%B: relocalisation relative à SB mais __c6xabi_DSBT_BASE n'est pas défini" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "%B: relocalisation de type %d pas implémentée" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "relocalisation dangereuse" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "erreur: %B nécessite un plus grand alignement de pile que ce que %B préserve" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "erreur: valeur Tag_ABI_array_object_alignment inconnue dans %B" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "erreur: valeur Tag_ABI_array_object_align_expected inconnue dans %B" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "erreur: %B nécessite un plus grand alignement de tableau que ce que %B préserve" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "attention: %B et %B on des tailles de wchar_t différentes" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "attention: %B et %B ne sont pas d'accord sur la compilation du code pour DSBT" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "attention: %B et %B divergent sur la dépendance de la position de l'adressage des données" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "attention: %B et %B divergent sur la dépendance de la position de l'adressage du code" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variable «%s» ne peut occuper de multiples petites régions de données" + +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variable «%s» peut seulement être dans une région de données petite, zéro ou minuscule" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variable «%s» ne peut être dans une région de données petite et zéro à la fois" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variable «%s» ne peut être dans une région de données petite et minuscule à la fois" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Variable «%s» ne peut être dans une région de données zéro et minuscule à la fois" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "ÉCHEC de repérage de la relocalisation précédente HI16\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "ne peut repérer le symbole spécial d'édition de lien __gp" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "ne peut repérer le symbole spécial d'édition de lien __ep" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "ne peut repérer le symbole spécial d'édition de lien __ctbp" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: L'architecture ne concorde pas avec les modules précédents" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "fanions privés = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "architecture v850" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "architecture v850e" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "architecture v850e1" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "architecture v850e2" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "architecture v850e2v3" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr " [nonpic]" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: attention: ajout GOT de %ld à «%s» ne concorde par avec l'ajout GOT précédent de %ld" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: attention: ignore l'ajout PLT de %d à «%s» de la section %s" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: attention: relocalisation %s vers le symbole «%s» de la section %s" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: attention: relocalisation %s vers 0x%x de la section %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "ajout non nul dans la relocalisation @fptr" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): table de propriété invalide" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): décalage de relocalisation hors limite (taille=0x%x)" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "relocalisation dynamique dans une section en lecture seule" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "relocalisation TLS incorrecte sans section dynamique" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "incohérence interne dans la taille de la section .got.loc" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: type de machine incompatible. Sortie est 0x%x. Entrée est 0x%x" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Échec de la tentative de convertir L32R/CALLX en CALL" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): l'instruction ne peut pas être décodée; la configuration est peut-être erronée" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): l'instruction ne peut pas être décodée pour une relocalisation XTENSA_ASM_SIMPLIFY; la configuration est peut-être erronée" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "adresse de relocalisation incorrecte" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "débordement après la relâche" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): correction inattendue pour la relocalisation %s" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "la relocalisation GPDISP n'a pas repéré les instructions ldah et lda" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: le sous-segment .got excède 64K (taille %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: relocalisation relative au gp vers le symbole dynamique %s" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: relocalisation relative au PC vers le symbole dynamique %s" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: changé dans le GP: BRSGP %s" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: relocalisation !samegp vers le symbole sans .prologue: %s" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: relocalisation dynamique non traitée vers %s" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: relocalisation relative au PC vers le symbole faible non défini %s" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: relocalisation relative au dtp vers le symbole dynamique %s" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: relocalisation relative au tp vers le symbole dynamique %s" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "entrée de l'ébauche pour %s ne peut charger .plt, décalage dp = %ld" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): ne peut atteindre %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: erreur d'incohérence interne pour la valeur du registre global\n" +" alloué à l'édition de lien: lié: 0x%lx%08lx != relâché: 0x%lx%08lx\n" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: relocalisation base plus décalage vers le symbole registre: (inconnu) dans %s" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: relocalisation base plus décalage vers le symbole registre: %s dans %s" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: relocalisation de registre vers le symbole non-registre: (inconnu) dans %s" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: relocalisation de registre vers le symbole non-registre: %s dans %s" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: directive LOCAL valide seulement avec un registre ou une valeur absolue" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: directive LOCAL: registre $%ld n'est pas un registre local. Premier registre global est $%ld." + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: erreur: multiple définitions de «%s»; début de %s est initialisé dans un précédent fichier lié\n" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "Registre de section contient\n" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Inconsistence interne: reste %u != max %u.\n" +" Merci de rapporter cette anomalie." + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "" +"%B: compilé pour un système à octets de poids fort alors que la cible\n" +"est un système à octets de poids faible" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "" +"%B: compilé pour un système à octets de poids faible alors que la cible\n" +"est un système à octets de poids fort" + +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "la copie de la relocalisation vers «%s» nécessite un lien plt paresseux, évitez de mettre LD_BIND_NOW=1 ou mettez à jour gcc" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "erreur de décompte de relocalisation dynamique pour %B, section %A" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd n'est pas un tableau régulier d'entrées opd" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: type de relocalisation %u inattendu dans la section .opd" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: symbole «%s» indéfini dans la section .opd" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "%s défini dans une entrée toc supprimée" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "débordement de l'offset du branchement long de l'ébauche «%s»" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "ne peut repérer l'ébauche de branchement «%s»" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "erreur de liaison de la table de liaison vers «%s»" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "ne peut construire l'ébauche de branchement «%s»" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "%B section %A dépasse la taille du groupe d'ébauche" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"éditeur de liens des ébauches dans %u groupe%s\n" +" branchements %lu\n" +" ajustements toc %lu\n" +" long branchements %lu\n" +" long ajustements toc %lu\n" +" appels plt %lu" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): TOC multiples et automatiques non supportées utilisant votre fichier crt; recompilez avec -mminimal-toc ou mettez à jour gcc" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): l'optimisation soeurs des appels vers «%s» ne permet par de TOC multiples et automatiques; recompilez avec -mminimal-toc ou -fno-optimize-sibling-calls, ou rendez «%s» externe" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: relocalisation %s n'est pas supportée pour le symbole %s." + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: erreur: relocalisation %s n'est pas un multiple de %d" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: erreur: type de relocalisation %d non aligné à %08x relocalisé`%08x\n" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Seuls les registres %%g[2367] peuvent être déclarés en utilisant les registres STT_REGISTER" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "Registre %%g%d utilisé de manière incompatible: %s dans %B précédemment %s dans %B" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Symbole «%s» a des types qui diffèrent: REGISTRE dans %B, précédemment %s dans %B" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Symbole «%s» a des types qui diffèrent: %s dans %B, précédemment REGISTRE dans %B" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: édition de liens spécifiques pour UltraSPARC avec du code spécifique HAL" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: symbole «%s» accédé à la fois comme normal et comme local au thread" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: la relocalisation %s vers le symbole STT_GNU_IFUNC «%s» a l'opérande non nul: %d" + +#: elf64-x86-64.c:3073 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: relocalisation R_X86_64_GOTOFF64 vers la fonction protégée «%s» ne peut pas être utilisée lors de la création d'un objet partagé" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "; recompilé avec -fPIC" + +#: elf64-x86-64.c:3189 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: relocalisation %s vers %s «%s» ne peut pas être utilisée en créant un objet partagé %s" + +#: elf64-x86-64.c:3191 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: relocalisation %s vers le %s non défini «%s» ne peut pas être utilisée en créant un objet partagé %s" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "attention: %s a un index de table de chaînes corrompu - ignoré" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: compteur de version (%ld) ne concorde pas avec le symbole du compteur (%ld)" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): relocalisation %d a un index de symbole %ld invalide" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Attention: %B est tronqué: taille attendue du cÅ“ur du fichier >= %lu, obtenu: %lu." + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: définition TLS dans %B section %A ne correspond pas à la définition non TLS dans %B section %A" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: référence TLS dans %B ne correspond pas à la référence non TLS dans %B" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: définition TLS dans %B section %A ne correspond pas à la référence TLS dans %B" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: référence TLS dans %B ne correspond pas à la définition non TLS dans %B section %A" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: attention: redéfinition inattendue du symbole indirect avec version «%s»" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "%B: version du nÅ“ud pas trouvée pour le symbole %s" + +#: elflink.c:2166 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: mauvais index de relocalisation du symbole (0x%lx >= 0x%lx) pour l'offset 0x%lx de la section «%A»" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: index de symbole non nul (0x%lx) pour l'offset 0x%lx de la section «%A» quand le fichier objet n'a pas de table de symboles" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: taille de la relocalisation ne concorde pas dans %B section %A" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "attention: type et taille du symbole dynamique «%s» ne sont pas définis" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: code machine ELF alternatif trouvé (%d) dans %B, %d est attendu\n" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: version invalide %u (max %d)" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: version requise invalide %d" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Attention: alignement %u du symbole commun «%s» dans %B est plus grand que l'alignement (%u) de sa section %A" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Attention: alignement %u du symbole «%s» dans %B est plus petit que %u dans %B" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Attention: taille du symbole «%s» a changé de %lu dans %B à %lu dans %B" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "%B: référence au symbole non défini «%s»" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "note: «%s» est défini dans le DSO %B donc essayez de l'ajouter à la ligne de commande du lieur" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: version non définie: %s" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: section .preinit_array n'est pas permise dans DSO" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "référence %s non définie dans le symbole complexe: %s" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "opérateur «%c» inconnu dans le symbole complexe" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Impossible de trier les relocalisations - plusieurs tailles rencontrées" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Impossible de trier les relocalisations - leur taille est inconnue" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "Pas assez de mémoire pour trier les relocalisations" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Trop de sections: %d (>= %d)" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: symbole %s «%s» dans %B est référencé par DSO" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: ne peut repérer la section de sortie %A pour la section d'entrée %A" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: symbole %s «%s» n'est pas défini" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "erreur: %B contient une relocalisation (0x%s) pour la section %A qui fait référence à un symbole global inexistant" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X«%s» référencé dans la section «%A» de %B: défini dans la section abandonnée «%A» de %B\n" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A a, à la fois, des sections ordonnées [«%A» dans %B] et désordonnées [«%A» dans %B]" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A a, à la fois, des sections ordonnées et désordonnées" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: ne peut repérer la section de sortie %s" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "attention: section %s a une taille nulle" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: attention: création d'un DT_TEXTREL dans un objet partagé.\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: ne peut pas lire les symboles: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Suppression de la section inutilisée «%s» dans le fichier «%B»" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "Attention: l'option de la section gc est ignorée" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: ignore les sections dupliquées «%A»" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: section dupliquée «%A» avec des tailles différentes" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: attention: ne peut pas lire le contenu de la section «%A»" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: attention: section dupliquée «%A» a des contenus différents" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "procédure statique (sans name)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "%B: %A+0x%lx: Les sauts directs entre modes ISA ne sont pas permis; envisagez de recompiler avec l'interliage activé." + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Attention: mauvaise «%s» taille d'option %u plus petite que son en-tête" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Attention: ne peut pas déterminer la fonction cible de la section d'ébauche «%s»" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: relocalisation mal composée détectée dans la section %s" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: relocalisation GOT à 0x%lx pas attendue dans les executables" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: appel CALL16 de relocalisation à 0x%lx qui n'est pas pour un symbole global" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "relocalisation non dynamique fait référence au symbole dynamique %s" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Ne trouve pas de relocalisation LO16 correspondante vers «%s» pour %s à 0x%lx de la section «%A»" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "la taille des petites données de la section dépasse 64KB; abaissez la limite de taille des petites données (voyez l'option -G)" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: nom illégal de section «%s»" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Attention: %B utilise -msingle-float, %B utilise -mdouble-float" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Attention: %B utilise -msingle-float, %B utilise -mips32r2 -mfp64" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Attention: %B utilise -mdouble-float, %B utilise -mips32r2 -mfp64" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: système de poids fort ou faible incompatible avec celui sélectionné pour l'émulation" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI est incompatible avec celui sélectionné pour l'émulation" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: attention: édition de liens des fichiers abicalls avec des fichiers non abicalls" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: édition de liens de code 32 bits avec du code 64 bits" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: édition de liens du module %s avec les modules précédents %s" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: ABI ne concorde pas: édition de lien du module %s avec les modules précédents %s" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [abi inconnu]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [aucun jeu abi]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [ISA inconnu]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [aucun mode 32 bits]" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "type de relocalisation %d invalide" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "La sortie requiert la librairie partagée «%s»\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Le fichier de sortie requiert une librairie partagée «%s.so.%s»\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Symbole %s n'est pas défini pour les corrections\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "Attention: nombre de corrections en désaccord\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: chaîne trop longue (%d caractères, max 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: symbole non reconnue «%s» fanions 0x%x" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: enregistrement ATI non implanté %u pour le symbole %u" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: type ATN %d inattendu dans la partie externe" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "%B: type inattendu après ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: caractère inattendu «%s» dans le fichier Intel hexadécimal" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: somme de contrôle erronée dans le fichier Intel hexadécimal (attendu %u, obtenu %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: longueur erronée de l'enregistrement d'adresse étendue dans le fichier Intel hexadécimal" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: longueur erronée d'adresse étendue de début dans le fichier Intel hexadécimal" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: longueur erronée de l'enregistrement d'adresse étendue linéaire dans le fichier Intel hexadécimal" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: longueur erronée d'adresse étendue linéraire de début dans le fichier Intel hexadécimal" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: type ihex %u non reconnu dans le fichier Intel hexadécima" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: erreur interne dans ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: longuer erronée de section dans ihex_read_section" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: adresse 0x%s hors limite pour le fichier Intel hexadécimal" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "%B: impossible d'obtenir la section décompressée %A" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "%s déprécié appelé à %s dans la ligne %d dans %s\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "%s appel déprécié\n" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: symbole indirect «%s» vers «%s» est une boucle" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Tentative de relocalisation d'un lien avec %s à l'entrée et %s à la sortie" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: attention: ignore la section dupliquée «%A»\n" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: attention: section dupliquée «%A» avec des tailles différentes\n" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "En-tête Mach-O:\n" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr " magique : %08lx\n" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " typecpu : %08lx (%s)\n" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " soustypecpu: %08lx\n" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " typefichier: %08lx (%s)\n" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr " ncmds : %08lx (%lu)\n" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " taillecmds: %08lx\n" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr " fanions : %08lx (" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr " réservé : %08x\n" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "Segments et Sections:\n" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr " #: Nom segment Nom section Adresse\n" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: accès au-delà de la fin de la section fusionnée (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: pas de corps pour allouer un nom de section %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: pas de corps pour allouer un symbole de %d octets de longueur\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: fichier mmo invalide: valeur d'initialisation pour $255 n'est pas «Main»\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: séquence de caractères large 0x%02X 0x%02X non supportée après le nom de symbole débutant par «%s»\n" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: fichier mmo invalide: lopcode «%d» non supporté\n" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: fichier mmo invalide: attendu YZ = 1 obtenu YZ = %d pour lop_quote\n" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: fichier mmo invalide: attendu z = 1 ou z = 2, obtenu z = %d pour lop_loc\n" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: fichier mmo invalide: attendu z = 1 ou z = 2, obtenu z = %d pour lop_fixo\n" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: fichier mmo invalide: attendu y = 0, obtenu y = %d pour lop_fixrx\n" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: fichier mmo invalide: attendu z = 16 ou z = 24, obtenu z = %d pour lop_fixrx\n" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: fichier mmo invalide: octet de tête du mot de l'opérande doit être 0 ou 1, obtenu %d pour lop_fixrx\n" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: ne paut pas allouer un nom de ficheir pour le no. de fichier %d, %d octets\n" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: fichier mmo invalide: no. de fichier %d «%s», a déjà été entré en tant que «%s»\n" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: fichier mmo invalide: nom de fichier %d n'a pas été spécifié avant son utilisation\n" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: fichier mmo invalide: champs y et z de lop_stab non nul, y: %d, z: %d\n" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: fichier mmo invalide: lop_end n'est pas le dernier élement dans le fichier\n" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: fichier mmo invalide: YZ de lop_end (%ld) n'est pas égal au nombre de tetras du lop_stab précédent (%ld)\n" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: table de symboles invalide: symbole «%s» dupliqué\n" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Définition de symbole erronée: «Main» initialisé à %s au lieu de l'adresse de départ %s\n" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: attention: table de symboles trop grande pour mmo, plus grande que 65535 mots de 32 bits: %d. Seul «Main» sera produit.\n" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: erreur interne, table de symbole a changé de taille de %d à %d mots\n" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: erreur interne, registre interne de section %s contient quelque chose\n" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: pas de registre initialisé; section de longeur 0\n" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: trop de resigstres initialisés; longueur de section %ld\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: adresse de départ invalide pour des registres initialisés de longueur %ld: 0x%lx%08lx\n" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: ne peut représenter la section «%s» dans oasys" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Type de section de fichier core OSF/1 %d non traité\n" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: «ld -r» non supporté avec les objets PE MIPS\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "%B: non implanté %s\n" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "%B: le saut va trop loin\n" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: pairage erronée pair/reflo après refhi\n" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "attention, taille de la section .pdata (%ld) n'est pas un multiple de %d\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"La table de fonctions (interprétation du contenu de la section .pdata)\n" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr " vma:\t\t\tAdresse Début\t Adresse Fin\t Unwind Info\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: type d'importation non traitée; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: type d'importation non reconnu; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: type de nom d'importation non reconnu: %x" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: type de machine non reconnu (0x%x) dans l'archive de librairie de formats d'importation" + +#: peicode.h:1174 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: type de machine reconnue mais non traitée (0x%x) dans l'archive da la librairie de formats d'importation" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: taille du champ est zéro dans l'en-tête de la librairie de formats d'importation" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: chaîne n'est pas terminée par un zéro dans le fichier objet ILF." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"En-têtes ppcboot:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Décalage de l'entrée= 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Longueur = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Champ de fanion = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Nom de partition = «%s»\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Début de partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Fin de la partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Secteur de la partition[%d] = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Longueur de la partition[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"En-tête auxiliaire de l'exec\n" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers non implémenté" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: caractère inattendu «%s» dans le fichier S-record\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: Mauvaise somme de contrôle dans le fichier S-record\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Entrée des ébauches a un indexe de chaîne invalide" + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "Relocalisation du .stab non supporté" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "Sous type EGSD %d inconnu" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Débordement de la pile (%d) dans _bfd_vms_push" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Sous dépilage de la pile dans _bfd_vms_pop" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "commande ETIR %d inconnue" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "index de section erronée dans %s" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "commande STA %s non supportée" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "%s: pas supporté" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "%s: non implémenté" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "utilisation incorrecte de %s avec des contextes" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "commande %d réservée" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "Module objet N'EST PAS sans erreur !\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Symbole %s remplacé par %s\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC sans relocalisation dans la section %s" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "Erreur de taille dans la section %s" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Relocalisation ALPHA_R_BSR parasite" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Relocalisation %s non traitée" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "commande source %d inconnue" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "DST__K_SET_LINUM_INCR pas implémenté" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "DST__K_SET_LINUM_INCR_W pas implémenté" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "DST__K_RESET_LINUM_INCR pas implémenté" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "DST__K_BEG_STMT_MODE pas implémenté" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "DST__K_END_STMT_MODE pas implémenté" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "DST__K_SET_PC pas implémenté" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "DST__K_SET_PC_W pas implémenté" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "DST__K_SET_PC_L pas implémenté" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "DST__K_SET_STMTNUM pas implémenté" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "commande de ligne %d inconnue" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Relocalisation %s + %s inconnue" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "Relocalisation %s inconnue" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "Index de section incorrect dans ETIR" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "Symbole inconnu dans la commande %s" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr " EMH %u (long=%u): " + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "En-tête module\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr " niveau de structure: %u\n" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr " taille max d'enregistrement: %u\n" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr " nom du module : %.*s\n" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr " version du module : %.*s\n" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr " date de compilation : %.17s\n" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "Nom du Processeur de Langage\n" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr " nom du language: %.*s\n" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "En-tête des fichiers sources\n" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr " fichier: %.*s\n" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "En-tête du texte du titre\n" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr " titre: %.*s\n" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "En-tête du copyright\n" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr " copyright: %.*s\n" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "sous-type emh %u non pris en charge\n" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr " EEOM (long=%u):\n" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr " nombre de paires de liaisons cond: %u\n" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr " code de complétion: %u\n" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr " fanions de transfert d'adr: 0x%02x\n" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr " psect transert adr: %u\n" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr " adresse de transert: 0x%08x\n" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr " FAIBLE" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr " DEF" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr " UNI" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr " REL" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr " COMM" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr " VECEP" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr " NORM" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr " QVAL" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr " PIC" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr " LIB" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr " OVR" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr " GBL" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr " SHR" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr " EXE" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr " RD" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr " WRT" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr " VEC" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr " NOMOD" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr " COM" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr " 64B" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr " EGSD (long=%u):\n" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr " entrée EGSD %2u (type: %u, long: %u): " + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "PSC - Définition de section du programme\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr " alignement : 2**%u\n" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr " fanions : 0x%04x" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr " alloc (long): %u (0x%08x)\n" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr " nom : %.*s\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "SPSC - Def de section de l'image partagée du programme\n" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr " alloc (long) : %u (0x%08x)\n" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr " offset d'image: 0x%08x\n" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr " offset symvec : 0x%08x\n" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr " nom : %.*s\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "SYM - Définition du symbol global\n" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr " fanions: 0x%04x" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr " offset psect: 0x%08x\n" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr " adresse code: 0x%08x\n" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr " index psect pour point d'entrée: %u\n" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr " index psect : %u\n" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr " nom : %.*s\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "SYM - Référence du symbol globaux\n" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "IDC - Vérification de la consistance d'identité\n" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr " fanions : 0x%08x" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr " correspondance id : %x\n" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr " sévérité d'erreur: %x\n" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr " nom d'entité : %.*s\n" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr " nom d'objet : %.*s\n" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr " ident binaire : 0x%08x\n" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr " ident ascii : %.*s\n" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "SYMG - Définition de symbole universel\n" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr " offset vecteur symbole: 0x%08x\n" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr " point d'entrée: 0x%08x\n" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr " descr proc : 0x%08x\n" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr " index psect: %u\n" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "SYMV - Définition symbole vectorisé\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr " vecteur : 0x%08x\n" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr " offset psect: %u\n" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "SYMM - Définition de symbole globale avec version\n" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr " masque de version: 0x%08x\n" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "type d'entrée egsd %u non supporté\n" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr " index de liaison: %u, instruction de remplacement: 0x%08x\n" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr " index psect 1: %u, offset 1: 0x%08x %08x\n" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr " index psect 2: %u, offset 2: 0x%08x %08x\n" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr " index psect 3: %u, offset 3: 0x%08x %08x\n" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr " nom global: %.*s\n" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr " %s (long=%u+%u):\n" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr " (type: %3u, taille: 4+%3u): " + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "STA_GBL (pile globals) %.*s\n" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "STA_LW (pile mot long) 0x%08x\n" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "STA_QW (pile quad mot) 0x%08x %08x\n" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "STA_PQ (base pile psect + offset)\n" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr " psect: %u, offset: 0x%08x %08x\n" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "STA_LI (pile literale)\n" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "STA_MOD (pile module)\n" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "STA_CKARG (compare les arguments de la procédure)\n" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "STO_B (stocke octet)\n" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "STO_W (stocke mot)\n" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "STO_LW (stocke mot long)\n" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "STO_QW (stocke quad mot)\n" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "STO_IMMR (stock répétition immédiate) %u octets\n" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "STO_GBL (stocke globale) %.*s\n" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "STO_CA (stock adresse code) %.*s\n" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "STO_RB (stocke branche relative)\n" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "STO_AB (stocke branche absolue)\n" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "STO_OFF (stocke offset de psect)\n" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "STO_IMM (stocke immediat) %u octets\n" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "STO_GBL_LW (stocke mot long global) %.*s\n" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "STO_OFF (stocke LP avec la signature de la procédure)\n" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "STO_BR_GBL (stocke branche globale) *todo*\n" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "STO_BR_PS (stocke branche psect + offset) *todo*\n" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "OPR_NOP (pas d'operation)\n" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "OPR_ADD (ajout)\n" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "OPR_SUB (soustraction)\n" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "OPR_MUL (multiplication)\n" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "OPR_DIV (division)\n" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "OPR_AND (et logique)\n" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "OPR_IOR (ou inclusif logique)\n" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "OPR_EOR (ou exclusif logique)\n" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "OPR_NEG (négation)\n" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "OPR_COM (complément)\n" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "OPR_INSV (insertion champ)\n" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "OPR_ASH (décalage arithmetique)\n" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "OPR_USH (décalage non signé)\n" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "OPR_ROT (rotation)\n" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "OPR_SEL (selection)\n" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "OPR_REDEF (redéfini le symbole à la position actuelle)\n" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "OPR_REDEF (définir un litéral)\n" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "STC_LP (stocke pair de liaison cond)\n" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "STC_LP_PSB (stocke pair de liaison cond + signature)\n" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr " index liaison: %u, procédure: %.*s\n" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr " signature: %.*s\n" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "STC_GBL (stocke cond globale)\n" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr " index liaison: %u, globale: %.*s\n" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "STC_GCA (stocke adresse code cond)\n" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr " index liaison: %u, nom procédure: %.*s\n" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "STC_PS (stocke psect cond + offset)\n" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr " index liaison: %u, psect: %u, offset: 0x%08x %08x\n" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "STC_NOP_GBL (stocke NOP cond à l'adresse globale)\n" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "STC_NOP_PS (stocke NOP cond à psect + offset)\n" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "STC_BSR_GBL (stocke BSR cond à l'adresse globale)\n" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "STC_BSR_PS (stocke BSR cond à psect + offset)\n" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "STC_LDA_GBL (stocke LDA cond à l'adresse globale)\n" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "STC_LDA_PS (stocke LDA cond à psect + offset)\n" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "STC_BOH_GBL (stocke BOH cond à l'adresse globale)\n" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "STC_BOH_PS (stocke BOH cond à psect + offset)\n" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "STC_NBH_GBL (stocke cond ou suggestion à l'adresse globale)\n" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "STC_NBH_PS (stocke cond or suggestion à psect + offset)\n" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "CTL_SETRB (fixe la base de relocalisation)\n" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "CTL_AUGRB (augmente la base de relocalisation) %u\n" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "CTL_DFLOC (définir position)\n" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "CTL_STLOC (fixer position)\n" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "CTL_STKDL (position définie dans la pile)\n" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "*non pris en charge*\n" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "impossible de lire la longueur de l'enregistrement GST\n" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "impossible de trouver le EMH dans le premier enregistrement GST\n" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "impossible de lire l'en-tête de l'enregistrement GST\n" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr " GST corrompu\n" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "ne peut lire l'enregistrement GST\n" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr " type d'enregistrement EOBJ %u non supporté\n" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr " décompte des bits: %u, adr base: 0x%08x\n" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr " carte des bits: 0x%08x (occurrence: %u):\n" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr " %08x" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr " image %u (%u entrées)\n" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr " offset: 0x%08x, val: 0x%08x\n" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr " image %u (%u entrées), offsets:\n" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr " 0x%08x" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "64 bits *non supporté*\n" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "classe: %u, dtype: %u, longueur: %u, pointeur: 0x%08x\n" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "table de %s non contiguë\n" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "dimct: %u, aflags: 0x%02x, digits: %u, échelle: %u\n" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "arsize: %u, a0: 0x%08x\n" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "Pas:\n" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "[%u]: %u\n" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "Limites:\n" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "[%u]: Inférieure: %u, supérieure: %u\n" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "chaine de bits de %s désalignée\n" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "base: %u, pos: %u\n" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "vflags: 0x%02x, valeur: 0x%08x " + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "(pas de valeur)\n" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "(pas active)\n" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "(pas allouée)\n" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "(descripteur)\n" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "(valeur postérieure)\n" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "(spécificités de la valeur suivent)\n" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "(à l'offset de bit %u)\n" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "(reg: %u, aff: %u, indir: %u, type: " + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "litérale" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "adresse" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "desc" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "reg" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "Table des symboles de debug:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "impossible de lire l'en-tête DST\n" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr " type: %3u, long: %3u (à 0x%08x): " + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "ne peut lire le symbole DST\n" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "données standards: %s\n" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr " nom: %.*s\n" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "début module\n" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr " fanions: %d, language: %u, majeur: %u, mineur: %u\n" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr " nom du module: %.*s\n" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr " compilateur : %.*s\n" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "fin module\n" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "début rtn\n" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr " fanions: %u, adresse: 0x%08x, pd-adresse: 0x%08x\n" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr " nom routine : %.*s\n" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "fin rtn: taille 0x%08x\n" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "prologue: adresse bkpt 0x%08x\n" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "épilogue: fanions: %u, nombre: %u\n" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "début blk: adresse: 0x%08x, nom: %.*s\n" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "fin blk: taille: 0x%08x\n" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "typspec (long: %u)\n" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "septyp, nom: %.*s\n" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "début rec: nom: %.*s\n" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "fin rec\n" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "début énumération, long: %u, nom: %.*s\n" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "énumération éléments, nom: %.*s\n" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "fin énumération\n" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "plage discontinue (nbr: %u)\n" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr " adresse: 0x%08x, taille: %u\n" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "num ligne (long: %u)\n" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "delta_pc_w %u\n" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "incr_linum(b): +%u\n" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "incr_linum_w: +%u\n" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "incr_linum_l: +%u\n" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "set_line_num(w) %u\n" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "set_line_num_b %u\n" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "set_line_num_l %u\n" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "set_abs_pc: 0x%08x\n" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "delta_pc_l: +0x%08x\n" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "term(b): 0x%02x" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "term_w: 0x%04x" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "delta pc +%-4d" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr " pc: 0x%08x ligne: %5u\n" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " cmd %u *non gérée*\n" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "source (long: %u)\n" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr " declfile: long: %u, fanions: %u, id fichier: %u\n" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr " nom fichier: %.*s\n" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr " setfile %u\n" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr " setrec %u\n" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr " setlnum %u\n" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr " deflines %u\n" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr " formfeed\n" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " cmd %u *non gérée*\n" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "type dst %u *non géré*\n" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "ne peut lire EIHD\n" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "EIHD: (taille: %u, nbr blocs: %u)\n" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr " id majeur: %u, id mineur: %u\n" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "exécutable" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "image liable" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr " type image: %u (%s)" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "natif" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "CLI" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr ", sous-type: %u (%s)\n" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr " offsets: isd: %u, actif: %u, debug symbol: %u, id image: %u, patch: %u\n" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr " correctif info rva: " + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr ", vecteur de symbol rva: " + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" +"\n" +" offset tableau version: %u\n" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr " décompte E/S img: %u, nbr canaux: %u, priv req: %08x%08x\n" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr " fanions lieur: %08x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr " ident: 0x%08x, ver sys: 0x%08x, apparier ctrl: %u, taille vectsym: %u\n" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr " BPAGE: %u" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr ", offset correctif étendu: %u, offset no_opt psect: %u" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr ", alias: %u\n" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "information sur table de version système:\n" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "ne peut lire l'en-tête EIHVN\n" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "ne peut lire la version EIHVN\n" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr " %02u " + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "BASE_IMAGE " + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "MEMORY_MANAGEMENT" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "IO " + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "FILES_VOLUMES " + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "PROCESS_SCHED " + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "SYSGEN " + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "CLUSTERS_LOCKMGR " + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "LOGICAL_NAMES " + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "SECURITY " + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "IMAGE_ACTIVATOR " + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "NETWORKS " + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "COUNTERS " + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "STABLE " + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "MISC " + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "CPU " + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "VOLATILE " + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "SHELL " + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "POSIX " + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "MULTI_PROCESSING " + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "GALAXY " + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "*inconnu* " + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr ": %u.%u\n" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "ne peut lire EIHA\n" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "Activation de l'image: (taille=%u)\n" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr " Première adresse : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr " Deuxième adresse : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr " Troisième adresse: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr " Quatrième adresse: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr " Image partagée : 0x%08x 0x%08x\n" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "ne peut lire EIHI\n" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "Identification d'image: (majeur: %u, mineur: %u)\n" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr " nom de l'image : %.*s\n" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr " heure de liaison : %s\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr " ident image : %.*s\n" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr " ident lieur : %.*s\n" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr " ident construction image: %.*s\n" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "ne peut lire EIHS\n" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "Image des symboles et table debug: (majeur: %u, mineur: %u)\n" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr " table des symboles de debug : vbn: %u, taille: %u (0x%x)\n" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr " table des symboles globale: vbn: %u, enregistrements: %u\n" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr " table des modules de debug: vbn: %u, taille: %u\n" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "ne peut lire EISD\n" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "Descripteur de section d'image: (majeur: %u, mineur: %u, taille: %u, offset: %u)\n" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr " section: base: 0x%08x%08x taille: 0x%08x\n" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr " fanions: 0x%04x" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr " vbn: %u, pfc: %u, matchctl: %u type: %u (" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "NORMAL" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "SHRFXD" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "PRVFXD" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "SHRPIC" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "PRVPIC" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "USRSTACK" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr " ident: 0x%08x, nom: %.*s\n" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "ne peut lire DMT\n" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "Table de debug du module:\n" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "ne peut lire l'en-tête DMT\n" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr " offset du module: 0x%08x, taille: 0x%08x, (%u psects)\n" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "ne peut lire le psect DMT\n" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr " début psect: 0x%08x, longueur: %u\n" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "ne peut lire DST\n" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "ne peut lire GST\n" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "Table des symboles globaux:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "Correction de l'activateur de l'image: (majeur: %u, mineur: %u)\n" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr " lien iaf : 0x%08x %08x\n" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr " lien correctif: 0x%08x %08x\n" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr " taille : %u\n" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr " fanions: 0x%08x\n" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr " qrelfixoff: %5u, lrelfixoff: %5u\n" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr " qdotadroff: %5u, ldotadroff: %5u\n" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr " codeadroff: %5u, lpfixoff : %5u\n" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr " chgprtoff : %5u\n" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr " shlstoff : %5u, shrimgcnt : %5u\n" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr " shlextra : %5u, permctx : %5u\n" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr " base_va : 0x%08x\n" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr " lppsbfixoff: %5u\n" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr " Images partageables:\n" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr " %u: taille: %u, fanions: 0x%02x, nom: %.*s\n" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr " correctifs de relocalisation des quad-mots:\n" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr " correctifs de relocalisation des mots longs:\n" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr " correctifs des références quad-mots «.address»:\n" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr " correctifs des références mots longs «.address»:\n" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr " Correctifs des références des adresses de code:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr " Correctifs des références des paires de liaison:\n" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr " Changement de protection (%u entrées):\n" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr " base: 0x%08x %08x, taille: 0x%08x, prot: 0x%08x " + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "%P: lien relocalisable pas supporté\n" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "%P: points d'entrée multiples: dans les modules %B et %B\n" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "n'a pas su ouvrir l'image partagée «%s» de «%s»" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted appelé avec un compte de zéro octet" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted appelé avec trop d'octets" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: objet XCOFF partagé alors qu'on ne produit pas de sortie XCOFF" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: objet dynamique sans section .loader" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: «%s» contient des numéros de lignes mais de section d'encadrement" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: classe %d symbole «%s» n'a pas d'entrée auxiliaire" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: symbole «%s» a un type csect %d non reconnu" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: symbole XTY_ER «%s» erroné: classe %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: XMC_TC0 symbol «%s» est la classe %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect «%s» n'est pas dans un section d'encadrement" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: XTY_LD «%s» mal placé" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: relocalisation %s:%d n'est pas dans csect" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: pas de tel symbole" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "attention: tentative d'exportation d'un symbole non défini «%s»" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "erreur: symbole __rtinit non défini" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: chargeur de relocalisation dans une section non reconnnue «%s»" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: «%s» est dans le chargeur de relocalisation mais pas dans celui des symboles" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: chargeur de relocalisation dans la section %A en lecture seule" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "Débordement de la table des entrées: 0x%lx > 0x10000; essayez l'option -mminimal-toc à la compilation" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Ne peut relâcher br à 0x%lx dans la section «%A». Veuillez utiliser brl ou un branchement indirect." + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "relocalisation @pltoff vers un symbole local" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: débordement du segment de données court (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp ne couvre pas le segment de données court" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: code non pic avec des relocalisations imm vers le symbole dynamique «%s»" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: relocalisation @gprel vers le symbole dynamique %s" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: liaison de code non-pic dans un exécutable à position indépendante" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: branchement @internal vers le symbole dynamique %s" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: spéculation d'ajustements vers le symbole dynamique %s" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: relocalisation @pcrel vers le symbole dynamique %s" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "relocalisation non supportée" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: setion TLS manquante pour la relocalisation %s vers «%s» à 0x%lx dans la section «%A»." + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B:Ne peut pas relâcher br (%s) sur «%s» à 0x%lx dans la section «%A» avec la taille 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: édition de liens trap-on-NULL-dereference avec des fichiers non-trapping" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: édition de liens entre des fichiers à octets de poids fort et des fichiers à octets de poids faible" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: édition de liens entre fichiers 64 bits et fichiers 32 bits" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: édition de liens entre fichiers constant-gp et fichiers non-constant-gp" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: édition de liens entre fichiers auto-pic et fichiers non-auto-pic" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: débordement du nombre de lignes: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Répertoire d'exportation [.edata (ou là où il a été trouvé)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Répertoire d'importation [faisant partie de .idata]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "Répertoire des resources [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "Répertoire des exceptions [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "Répertoire de la sécurité" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "Répertoire de base de relocalisation [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "Répertoire de débug" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "Répertoire de description" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "Répertoire spécial" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "Répertoire des files de stockage [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "Répertoire de chargement de configuration" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "Répertoire des importations limitées" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "Répertoire de la table d'adresse d'importation" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "Répertoire des délais d'importation" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "En-tête exécutable CLR" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "Réservé" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Il y a une table d'importation, mais la section la contenant ne peut être repérée\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Il y a une table d'importation dans %s à 0x%lx\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Descripteur de fonction localisé à l'adresse de départ: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcode-base %08lx tab. des entrées (chargeable/actuel) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Pas de section reldata! Descripteur de fonction pas décodé.\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Les tables d'importation (contenus interprété de la section %s)\n" + +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Hint Temps Avant DLL Premier\n" +" Table Estampil. Chaîne Nom Thunk\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tNom DLL: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Hint/Ord Membre Lien\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Il y a un premier «thunk», mais la section le contenant ne peut être repérée\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Il y a une table d'exportation, mais la section la contenant n'a pu être repérée\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Il y a une table d'exportation dans %s, mais elle ne rentre pas dans la section\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Il y a une table d'exportation dans %s à 0x%lx\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Les tables d'exportation (contenus interprété de la section %s)\n" +"\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Fanion d'exportation \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Tampon Heure/Date \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Majeur/Mineur \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Nom \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "base de nombre ordinal \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "Numéro dans:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tTable d'adresses d'exportation \t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\tTable [Nom pointeur/Nombre ordinal]\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "Table d'adresses\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tTable d'adresse d'exportation \t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tTable des noms de pointeurs \t\t" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tTable des ordinals \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Table d'adresses d'exportation -- base de nombre ordinal %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "Adresseur RVA" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "Exportation RVA" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"Table [Ordinal/Nom de pointeur]\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Attention, taille de la section .pdata (%ld) n'est pas un multiple de %d\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tDébut Adresse Fin Adresse Unwind Info\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tDébut Fin EH EH FinProlog Exception\n" +" \t\tAdresse Adresse Handler Données Adresse Masque\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " Registre a préservé le millicode" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " Registre a restauré le millicode" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " Séquence du code de liants" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tDébut Long. Long. Fanions Gestion. EH\n" +" \t\tAdresse Prolog. Fonction 32b exc Exception Données\n" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Fichier de base des relocalisation PE (contenus interprété de la section .reloc)\n" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Adresse virtuelle: %08lx taille des morceaux %ld (0x%lx) nombre de correctifs %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\trelocalisation %4d décalage %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Caractéristiques 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: impossible de remplir DataDictionary[1] car .idata$2 est manquant" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: impossible de remplir DataDictionary[1] car .idata$4 est manquant" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: impossible de remplir DataDictionary[12] car .idata$5 est manquant" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: impossible de remplir DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] car .idata$6 est manquant" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "%B: impossible de remplir DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] car .idata$6 est manquant" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: impossible de remplir DataDictionary[9] car __tls_used est manquant" + +#~ msgid "Can't Make it a Short Jump" +#~ msgstr "Impossible d'en faire un Saut Court" + +#~ msgid "Exceeds Long Jump Range" +#~ msgstr "Portée dépassée pour le Saut Long" + +#~ msgid "Absolute address Exceeds 16 bit Range" +#~ msgstr "L'adresse absolue déborde sur 16 bits" + +#~ msgid "Absolute address Exceeds 8 bit Range" +#~ msgstr "L'adresse absolue déborde sur 8 bits" + +#~ msgid "Unrecognized Reloc Type" +#~ msgstr "Type de relocalisation non reconnu" + +#~ msgid "corrupt or empty %s section in %B" +#~ msgstr "section %s vide ou corrompue dans %B" + +#~ msgid "%s: invalid DSO for symbol `%s' definition" +#~ msgstr "%s: DSO incorrect pour la définition du symbole «%s»" + +#~ msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%B: %A+0x%lx: saut vers la routine dans la partie de l'ébauche (stub) qui n'est pas jal" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "Échec de bfd_make_section (%s)" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) a échoué" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "Taille de section ne concorde pas %s=%lx, %s=%lx" + +#~ msgid "failed to enter %s" +#~ msgstr "échec d'insertion de %s" + +#~ msgid "No Mem !" +#~ msgstr "Mémoire épuisée!" + +#~ msgid "reserved STO cmd %d" +#~ msgstr "commande STO %d réservée" + +#~ msgid "reserved OPR cmd %d" +#~ msgstr "commande OPR %d réservée" + +#~ msgid "reserved CTL cmd %d" +#~ msgstr "commande CTL %d réservée" + +#~ msgid "reserved STC cmd %d" +#~ msgstr "commande STC %d réservée" + +#~ msgid "stack-from-image not implemented" +#~ msgstr "pile depuis l'image non implémentée" + +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "masque de pile d'entrée pas complètement implémenté" + +#~ msgid "PASSMECH not fully implemented" +#~ msgstr "PASSMECH pas complètement implémenté" + +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "symbole local de pile pas complètement implémenté" + +#~ msgid "stack-literal not fully implemented" +#~ msgstr "litéral de pile pas complètement implémenté" + +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "masque du symbole local de point d'entrée de pile pas complètement implémenté" + +#~ msgid "%s: not fully implemented" +#~ msgstr "%s: pas complètement implémenté" + +#~ msgid "obj code %d not found" +#~ msgstr "code objet %d non repéré" + +#~ msgid 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z0{YyApdt*P`U6pr>zdu6@a!q%6SC*g7e$WEj1o6vLAeO3lNPL}Yp=dfXKxx`+WGsUX9Q!rSo&TOZj zM&|8ByxZ7Zf4TH}d#g2yHIn%!R@8_+@Jz*^qM2&e9WYiV#x5(?PvHasux9zQz*I=yzf-_H8xtW=gnK5~*vM$d@C, 2008, 2009. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2009-09-07 14:05+0200\n" +"PO-Revision-Date: 2009-11-11 08:00+0700\n" +"Last-Translator: Arif E. Nugroho \n" +"Language-Team: Indonesian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Tipe bagian tidak diketahui dalam berkas a.out.adobe: %x\n" + +#: aout-cris.c:204 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Tipe relokasi tidak valid terekspor: %d" + +#: aout-cris.c:247 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Tipe relokasi tidak valid terimpor: %d" + +#: aout-cris.c:258 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Catatan relokasi buruk terimpor: %d" + +#: aoutx.h:1271 aoutx.h:1609 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: tidak dapat merepresentasikan bagian `%s' dalam a.out objek format berkas" + +#: aoutx.h:1575 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: tidak dapat merepresentasikan bagian untuk simbol `%s' dalam format berkas a.out objek" + +#: aoutx.h:1577 +msgid "*unknown*" +msgstr "*tidak diketahui*" + +#: aoutx.h:3994 aoutx.h:4320 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: tipe relokasi tidak diduga\n" + +#: aoutx.h:5354 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: link relokasi dari %s ke %s tidak didukung" + +#: archive.c:2056 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Peringatan: penulisan archive lambat: menulis ulang timestamp\n" + +#: archive.c:2342 +msgid "Reading archive file mod timestamp" +msgstr "Membaca berkas mod timestamp archive" + +#: archive.c:2366 +msgid "Writing updated armap timestamp" +msgstr "Menulis armap timestamp terupdate" + +#: bfd.c:375 +msgid "No error" +msgstr "Tidak error" + +#: bfd.c:376 +msgid "System call error" +msgstr "Pemanggilan sistem error" + +#: bfd.c:377 +msgid "Invalid bfd target" +msgstr "Target bfd tidak valid" + +#: bfd.c:378 +msgid "File in wrong format" +msgstr "Berkas dalam format salah" + +#: bfd.c:379 +msgid "Archive object file in wrong format" +msgstr "Archive berkas objek dalam format salah" + +#: bfd.c:380 +msgid "Invalid operation" +msgstr "Operasi tidak valid" + +#: bfd.c:381 +msgid "Memory exhausted" +msgstr "Kehabisan memori" + +#: bfd.c:382 +msgid "No symbols" +msgstr "Bukan simbol" + +#: bfd.c:383 +msgid "Archive has no index; run ranlib to add one" +msgstr "Archive tidak memiliki indek; jalankan ranlib untuk menambahkan satu" + +#: bfd.c:384 +msgid "No more archived files" +msgstr "Tidak lagi berkas yang ter-archive" + +#: bfd.c:385 +msgid "Malformed archive" +msgstr "Archive tidak terformat" + +#: bfd.c:386 +msgid "File format not recognized" +msgstr "Berkas format tidak dikenal" + +#: bfd.c:387 +msgid "File format is ambiguous" +msgstr "Berkas format ambigu" + +#: bfd.c:388 +msgid "Section has no contents" +msgstr "Bagian tidak memiliki isi" + +#: bfd.c:389 +msgid "Nonrepresentable section on output" +msgstr "Bagian tidak dapat direpresentasikan di keluaran" + +#: bfd.c:390 +msgid "Symbol needs debug section which does not exist" +msgstr "Simbol membutuhkan bagian debug yang mana bagian tersebut tidak ada" + +#: bfd.c:391 +msgid "Bad value" +msgstr "Nilai buruk" + +#: bfd.c:392 +msgid "File truncated" +msgstr "Berkas terpotong" + +#: bfd.c:393 +msgid "File too big" +msgstr "Berkas terlalu besar" + +#: bfd.c:394 +#, c-format +msgid "Error reading %s: %s" +msgstr "Error membaca %s: %s" + +#: bfd.c:395 +msgid "#" +msgstr "#" + +#: bfd.c:919 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s assertion gagal %s:%d" + +#: bfd.c:931 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %s error internal, menggagalkan di %s baris %d dalam %s\n" + +#: bfd.c:935 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %s error internal, menggagalkan di %s baris %d\n" + +#: bfd.c:937 +msgid "Please report this bug.\n" +msgstr "Tolong laporkan bug ini.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "tidak termap: data=%lx mapped=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "tidak termap; env var tidak terset\n" + +#: binary.c:284 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Peringatan: Menulis bagian `%s' terlalu besar (ie negatif) berkas ofset 0x%lx." + +#: bout.c:1150 elf-m10300.c:2078 elf32-avr.c:1639 elf32-frv.c:5743 +#: elf32-xtensa.c:6639 elfxx-sparc.c:2456 reloc.c:5386 reloc16.c:162 +#: vms.c:1918 elf32-ia64.c:788 elf64-ia64.c:788 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax dan -r tidak boleh digunakan secara bersamaan\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "membuka kembali %B: %s\n" + +#: coff-alpha.c:490 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Tidak dapat menangani binari yang dikompres Alpha.\n" +" Menggunakan tanda kompiler, atau objZ, untuk menghasilkan binari tidak terkompres." + +#: coff-alpha.c:647 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B; tidak diketahui/tidak didukung tipe relokasi %d" + +#: coff-alpha.c:899 coff-alpha.c:936 coff-alpha.c:2024 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "GP relatif relokasi digunakan ketika GP tidak didefinisikan" + +#: coff-alpha.c:1501 +msgid "using multiple gp values" +msgstr "menggunakan nilai gp multiple" + +#: coff-alpha.c:1560 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: relokasi tidak didukung: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1567 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: relokasi tidak didukung: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1574 elf32-m32r.c:2477 elf64-alpha.c:3943 elf64-alpha.c:4098 +#: elf32-ia64.c:4462 elf64-ia64.c:4462 +msgid "%B: unknown relocation type %d" +msgstr "%B: tipe relokasi %d tidak diketahui" + +#: coff-arm.c:1039 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: tidak dapat menemukan lem THUMB '%s' untuk `%s'" + +#: coff-arm.c:1068 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: tidak dapat menemukan lem ARM '%s' untuk `%s'" + +#: coff-arm.c:1370 elf32-arm.c:6372 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): peringatan: antar-kerja tidak diaktifkan.\n" +" pertemuan pertama: %B: arm panggil ke thumb" + +#: coff-arm.c:1460 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): peringatan: antar-kerja tidak diaktifkan.\n" +" pertemuan pertama: %B: panggilan thumb ke arm\n" +" pertimbangkan relinking dengan --support-old-code aktif" + +#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3027 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: alamat relokasi buruk 0x%lx dalam bagian `%A'" + +#: coff-arm.c:2080 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: indek simbol ilegal dalam relokasi: %d" + +#: coff-arm.c:2211 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "error: %B dikompile untuk APCS-%d, dimana %B dikompile untuk APCS-%d" + +#: coff-arm.c:2227 elf32-arm.c:10327 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "error: %B melewati float dalam register float, dimana %B melewatinya register integer" + +#: coff-arm.c:2230 elf32-arm.c:10331 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "error: %B melewati float dalam register integer, dimana %B melewatinya float register" + +#: coff-arm.c:2244 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "error: %B dikompile sebagai kode bebas posisi, dimana target %B yang memiliki posisi absolute" + +#: coff-arm.c:2247 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "error: %B dikompile sebagai kode absolute posisi, dimana target %B adalah bebas posisi" + +#: coff-arm.c:2275 elf32-arm.c:10396 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Peringatan: %B mendukung antar-kerja, dimana %B tidak" + +#: coff-arm.c:2278 elf32-arm.c:10402 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Peringatan: %B tidak mendukung antar-kerja, dimana %B ya" + +#: coff-arm.c:2302 +#, c-format +msgid "private flags = %x:" +msgstr "tanda private = %x:" + +#: coff-arm.c:2310 elf32-arm.c:10453 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [floats melewati dalam register float]" + +#: coff-arm.c:2312 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [float melewati register integer]" + +#: coff-arm.c:2315 elf32-arm.c:10456 +#, c-format +msgid " [position independent]" +msgstr " [bebas posisi]" + +#: coff-arm.c:2317 +#, c-format +msgid " [absolute position]" +msgstr " [absolute posisi]" + +#: coff-arm.c:2321 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [tanda antar-kerja tidak terinisialisasi]" + +#: coff-arm.c:2323 +#, c-format +msgid " [interworking supported]" +msgstr " [antar-kerja didukung]" + +#: coff-arm.c:2325 +#, c-format +msgid " [interworking not supported]" +msgstr " [antar-kerja tidak didukung]" + +#: coff-arm.c:2371 elf32-arm.c:9360 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Peringatan: Tidak menset tanda antar-kerja dari %B karena itu telah terspesifikasi sebagai bukan-antar-kerja" + +#: coff-arm.c:2375 elf32-arm.c:9364 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Peringatan: Menghapus tanda antar-kerja dari %B karena diluar permintaan" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "tidak dapat menangani R_MEM_INDIRECT relokasi ketika menggunakan keluaran %s" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Relokasi `%s' belum terimplementasi\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5143 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: peringatan: indek simbol ilegal %ld dalam relokasi" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "tidak tentu pemanggilan konvensi untuk non-COFF simbol" + +#: coff-m68k.c:506 elf32-bfin.c:5693 elf32-cr16.c:2965 elf32-m68k.c:4615 +msgid "unsupported reloc type" +msgstr "tipe relokasi tidak didukung" + +#: coff-maxq.c:126 +msgid "Can't Make it a Short Jump" +msgstr "Tidak dapat membuka ini sebuah lompatan pendek" + +#: coff-maxq.c:191 +msgid "Exceeds Long Jump Range" +msgstr "Melewati jangkauan lompatan panjang" + +#: coff-maxq.c:202 coff-maxq.c:276 +msgid "Absolute address Exceeds 16 bit Range" +msgstr "Alamat absolut melewati jangkauan 16 bit" + +#: coff-maxq.c:240 +msgid "Absolute address Exceeds 8 bit Range" +msgstr "Alamat absolute melewati jangkauan 8 bit" + +#: coff-maxq.c:333 +msgid "Unrecognized Reloc Type" +msgstr "Tipe relokasi tidak dikenal" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:441 elf32-score7.c:341 +#: elf64-mips.c:2018 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "GP relokasi relatif ketika _gp tidak terdefinisi" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "Relokasi tidak dikenal" + +#: coff-rs6000.c:2787 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: tipe relokasi tidak didukung 0x%02x" + +#: coff-rs6000.c:2880 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: TOC relokasi di 0x%x untuk simbol `%s' dengan tidak ada masukan TOC" + +#: coff-rs6000.c:3646 coff64-rs6000.c:2168 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: simbol `%s' memiliki smclas tidak dikenal %d" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Tipe relokasi tidak dikenal 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: peringatan: indek simbol ilegal %ld dalam relokasi" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "mengabaikan relokasi %s\n" + +#: coffcode.h:960 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: peringatan: COMDAT simbol '%s' tidak cocok dengan nama bagian '%s'" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1176 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Peringatan: Mengabaikan tanda bagian IMAGE_SCN_MEM_NOT_PAGED dalam bagian %s" + +#: coffcode.h:1240 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Tanda bagian %s (0x%x) diabaikan" + +#: coffcode.h:2382 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Target id '0x%x' TI COFF tidak dikenal" + +#: coffcode.h:2696 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: relokasi terhadap simbol indek yang tidak ada: %ld" + +#: coffcode.h:3669 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: bagian %s: tabel string overflow di offset %ld" + +#: coffcode.h:4477 +msgid "%B: warning: line number table read failed" +msgstr "%B: peringatan: pembacaan tabel nomor baris gagal" + +#: coffcode.h:4507 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: peringatan: simbol index %ld ilegal dalam nomor baris" + +#: coffcode.h:4521 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: peringatan: duplikasi informasi nomor baris untuk `%s'" + +#: coffcode.h:4912 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: kelas %d penyimpanan tidak dikenal untuk %s simbol `%s'" + +#: coffcode.h:5038 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "peringatan: %B: simbol lokal `%s' tidak memiliki bagian" + +#: coffcode.h:5181 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: tipe relokasi %d ilegal di alamat 0x%lx" + +#: coffgen.c:1571 +msgid "%B: bad string table size %lu" +msgstr "%B: string buruk ukuran tabel %lu" + +#: cofflink.c:513 elflink.c:4307 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Peringatan: tipe dari simbole `%s' berubah dari %d ke %d dalam %B" + +#: cofflink.c:2305 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: relokasi dalam bagian `%A', tetapi ini tidak memiliki isi" + +#: cofflink.c:2636 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: relokasi overflow: 0x%lx > 0xffff" + +#: cofflink.c:2645 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: peringatan: %s: nomor baris overflow: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "error: %B dikompile untuk EP9312, dimana %B dikompile untuk XScale" + +#: cpu-arm.c:332 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "peringatan: tidak dapat mengupdate isi dari %s bagian dalam %s" + +#: dwarf2.c:430 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Dwarf Error: Tidak dapat menemukan bagian %s." + +#: dwarf2.c:457 +#, c-format +msgid "Dwarf Error: unable to decompress %s section." +msgstr "Dwarf Error: tidak dapat mengekstrak bagian %s." + +#: dwarf2.c:468 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Dwarf Error: Ofset (%lu) lebih besar atau sama dengan %s ukuran (%lu)." + +#: dwarf2.c:865 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf Error: Tidak valid atau nilai FORM tidak tertangani: %u." + +#: dwarf2.c:1079 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf Error: mangled bagian nomor baris (nomor berkas buruk)." + +#: dwarf2.c:1413 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf Error: mangled bagian nomor baris." + +#: dwarf2.c:1760 dwarf2.c:1867 dwarf2.c:2139 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf Error: Tidak dapat menemukan nomor singkat %u." + +#: dwarf2.c:2100 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 and 3 information." +msgstr "Dwarf Error: menemukan versi dwarf '%u', pembaca ini hanya menangani informasi versi 2 dan 3." + +#: dwarf2.c:2107 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf Error: menemukan ukuran alamat '%u', pembaca ini tidak dapat menangani ukuran lebih besar dari '%u'." + +#: dwarf2.c:2130 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf Error: Nomor singkat buruk: %u." + +#: ecoff.c:1238 +#, c-format +msgid "Unknown basic type %d" +msgstr "Tipe dasar %d tidak diketahui" + +#: ecoff.c:1495 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Simbol End+1: %ld" + +#: ecoff.c:1502 ecoff.c:1505 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Simbol pertama: %ld" + +#: ecoff.c:1517 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Simbol End+1: %-7ld Tipe: %s" + +#: ecoff.c:1524 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Simbol lokal: %ld" + +#: ecoff.c:1532 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; simbol End+1: %ld" + +#: ecoff.c:1537 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union: End+1 simbol: %ld" + +#: ecoff.c:1542 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; End+1 simbol: %ld" + +#: ecoff.c:1548 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tipe: %s" + +#: elf-attrs.c:567 +msgid "error: %B: Must be processed by '%s' toolchain" +msgstr "error: %B: Harus diproses dengan '%s' toolchain" + +#: elf-attrs.c:575 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "error: %B: Objek tag '%d, %s' tidak kompatibel dengan tag '%d, %s'" + +#: elf-eh-frame.c:884 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: error dalam %B(%A); tidak ada .eh_frame_hdr tabel yang akan dibuat.\n" + +#: elf-eh-frame.c:1122 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: fde enkoding dalam %B(%A) menjaga .eh_frame_hdr tabel untuk dibuat.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: dynamic STT_GNU_IFUNC simbol '%s' dengan penunjuk persamaan dalam `%B' tidak dapat digunakan ketika membuat sebuah pelaksana; rekompilasi dengan -fPIE dan hubungkan kembali dengan -pie\n" + +#: elf-m10200.c:456 elf-m10300.c:1575 elf32-avr.c:1251 elf32-bfin.c:3200 +#: elf32-cr16.c:1517 elf32-cr16c.c:790 elf32-cris.c:2089 elf32-crx.c:933 +#: elf32-d10v.c:516 elf32-fr30.c:616 elf32-frv.c:4114 elf32-h8300.c:516 +#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-lm32.c:1171 +#: elf32-m32c.c:560 elf32-m32r.c:3102 elf32-m68hc1x.c:1136 elf32-mep.c:541 +#: elf32-microblaze.c:1226 elf32-moxie.c:291 elf32-msp430.c:493 elf32-mt.c:402 +#: elf32-openrisc.c:411 elf32-score.c:2752 elf32-score7.c:2591 +#: elf32-spu.c:5045 elf32-v850.c:1701 elf32-xstormy16.c:948 elf64-mmix.c:1533 +msgid "internal error: out of range error" +msgstr "internal error: diluar jangkauan error" + +#: elf-m10200.c:460 elf-m10300.c:1579 elf32-avr.c:1255 elf32-bfin.c:3204 +#: elf32-cr16.c:1521 elf32-cr16c.c:794 elf32-cris.c:2093 elf32-crx.c:937 +#: elf32-d10v.c:520 elf32-fr30.c:620 elf32-frv.c:4118 elf32-h8300.c:520 +#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-lm32.c:1175 elf32-m32c.c:564 +#: elf32-m32r.c:3106 elf32-m68hc1x.c:1140 elf32-mep.c:545 +#: elf32-microblaze.c:1230 elf32-moxie.c:295 elf32-msp430.c:497 +#: elf32-openrisc.c:415 elf32-score.c:2756 elf32-score7.c:2595 +#: elf32-spu.c:5049 elf32-v850.c:1705 elf32-xstormy16.c:952 elf64-mmix.c:1537 +#: elfxx-mips.c:9103 +msgid "internal error: unsupported relocation error" +msgstr "internal error: relokasi tidak didukung error" + +#: elf-m10200.c:464 elf32-cr16.c:1525 elf32-cr16c.c:798 elf32-crx.c:941 +#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-lm32.c:1179 elf32-m32r.c:3110 +#: elf32-m68hc1x.c:1144 elf32-microblaze.c:1234 elf32-score.c:2760 +#: elf32-score7.c:2599 elf32-spu.c:5053 +msgid "internal error: dangerous error" +msgstr "internal error error berbahaya" + +#: elf-m10200.c:468 elf-m10300.c:1592 elf32-avr.c:1263 elf32-bfin.c:3212 +#: elf32-cr16.c:1529 elf32-cr16c.c:802 elf32-cris.c:2101 elf32-crx.c:945 +#: elf32-d10v.c:528 elf32-fr30.c:628 elf32-frv.c:4126 elf32-h8300.c:528 +#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-lm32.c:1183 +#: elf32-m32c.c:572 elf32-m32r.c:3114 elf32-m68hc1x.c:1148 elf32-mep.c:553 +#: elf32-microblaze.c:1238 elf32-moxie.c:303 elf32-msp430.c:505 elf32-mt.c:410 +#: elf32-openrisc.c:423 elf32-score.c:2769 elf32-score7.c:2603 +#: elf32-spu.c:5057 elf32-v850.c:1725 elf32-xstormy16.c:960 elf64-mmix.c:1545 +msgid "internal error: unknown error" +msgstr "internal error: error tidak diketahui" + +#: elf-m10300.c:1512 elf32-arm.c:8963 elf32-i386.c:3984 elf32-m32r.c:2588 +#: elf32-m68k.c:4099 elf32-ppc.c:7906 elf32-s390.c:3015 elf32-sh.c:3429 +#: elf32-xtensa.c:3027 elf64-ppc.c:12063 elf64-s390.c:2974 elf64-sh64.c:1648 +#: elf64-x86-64.c:3657 elfxx-sparc.c:3317 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): tidak teresolf %s relokasi terhadap simbol `%s'" + +#: elf-m10300.c:1584 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "error: tipe relokasi tidak sesuai untuk shared library (apakah anda lupa -fpic?)" + +#: elf-m10300.c:1587 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "internal erro: suspicious tipe relokasi digunakan dalam shared library" + +#: elf-m10300.c:4385 elf32-arm.c:11346 elf32-cr16.c:2519 elf32-cris.c:3030 +#: elf32-hppa.c:1891 elf32-i370.c:506 elf32-i386.c:1975 elf32-lm32.c:1873 +#: elf32-m32r.c:1921 elf32-m68k.c:3188 elf32-ppc.c:4953 elf32-s390.c:1650 +#: elf32-sh.c:2574 elf32-vax.c:1052 elf64-ppc.c:6348 elf64-s390.c:1623 +#: elf64-sh64.c:3396 elf64-x86-64.c:1821 elfxx-sparc.c:1802 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "variabel dinamik `%s' memiliki ukuran nol" + +#: elf.c:329 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: string ofset tidak valid %u >= %lu untuk bagian `%s'" + +#: elf.c:439 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B nomor simbol %lu referensi tidak ada SHT_SYMTAB_SHNDX bagian" + +#: elf.c:595 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Ukuran bagian korup dalam grup bagian kepala: 0x%lx" + +#: elf.c:631 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: masukan SHT_GROUP tidak valid" + +#: elf.c:701 +msgid "%B: no group info for section %A" +msgstr "%B: tidak ada informasi grup untuk bagian %A" + +#: elf.c:730 elf.c:2960 elflink.c:9912 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: peringatan: sh_link tidak diset untuk bagian `%A'" + +#: elf.c:749 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%ld] dalam bagian `%A' tidak benar" + +#: elf.c:784 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: tidak diketahui [%d] bagian `%s' dalam grup [%s]" + +#: elf.c:1104 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Kepala Aplikasi:\n" + +#: elf.c:1146 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Bagian Dinamis:\n" + +#: elf.c:1282 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Definisi Versi:\n" + +#: elf.c:1307 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Referensi Versi:\n" + +#: elf.c:1312 +#, c-format +msgid " required from %s:\n" +msgstr " dibutuhkan dari %s:\n" + +#: elf.c:1702 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: link tidak valid %lu untuk bagian relokasi %s (indek %u)" + +#: elf.c:1870 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: tidak tahu bagaimana menangani alokasi, bagian spesifik aplikasi `%s' [0x%8x]" + +#: elf.c:1882 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: tidak tahu bagaimana menangani bagian spesifik prosesor `%s' [0x%8x]" + +#: elf.c:1893 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: tidak tahu bagaimana menangani bagian spesifik OS `%s' [0x%8x]" + +#: elf.c:1903 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: tidak tahu bagaimana menangani bagian `%s' [0x%8x]" + +#: elf.c:2500 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "peringatan: bagian `%A' tipe berubah ke PROGBITS" + +#: elf.c:2917 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link dari bagian `%A' menunjuk ke bagian terbuang `%A' dari `%B'" + +#: elf.c:2940 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link dari bagian `%A' menunjuk ke bagian terhapus `%A' dari `%B'" + +#: elf.c:4311 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: bagian pertama dalam segmen PT_DYNAMIC tidak dalam bagian .dynamic" + +#: elf.c:4338 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: tidak cukup ruang untuk kepala aplikasi, coba linking dengan -N" + +#: elf.c:4420 +msgid "%B: section %A vma 0x%lx overlaps previous sections" +msgstr "%B: bagian %A vma 0x%lx overlaps bagian sebelumnya" + +#: elf.c:4515 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: bagian `%A' tidak dapat dialokasikan dalam segmen %d" + +#: elf.c:4565 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: peringatan: alokasi bagian `%s' tidak dalam segmen" + +#: elf.c:5065 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: simbol `%s' dibutuhkan tetapi tidak ada" + +#: elf.c:5404 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: peringatan: loadable segmen kosong terdeteksi, apakah ini sengaja ?\n" + +#: elf.c:6370 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Tidak dapat menemukan bagian keluaran ekuivalen untuk simbol '%s' dari bagian '%s'" + +#: elf.c:7356 +msgid "%B: unsupported relocation type %s" +msgstr "%B: tipe relokasi tidak didukung %s" + +#: elf32-arm.c:3149 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): peringatan: antar-kerja tidak aktif.\n" +" pertemuan pertama: %B: Thumb call ke ARM" + +#: elf32-arm.c:3190 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): peringatan: antar-kerja tidak diaktifkan.\n" +" pertemuan pertama: %B: ARM panggil ke Thumb" + +#: elf32-arm.c:3387 elf32-arm.c:4692 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: tidak dapat membuat masukan stub %s" + +#: elf32-arm.c:4804 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "tidak dapat menemukan THUMB lem '%s' untuk '%s'" + +#: elf32-arm.c:4838 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "tidak dapat menemukan ARM lem '%s' untuk '%s'" + +#: elf32-arm.c:5365 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: hanya images BE8 valid dalam mode big-endian." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5590 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: peringatan: memilih VFP11 erratum penyelesaian adalah tidak diperlukan untuk arsitektur target" + +#: elf32-arm.c:6130 elf32-arm.c:6150 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: tidak dapat menemukan VFP11 veneer `%s'" + +#: elf32-arm.c:6196 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Tipe relokasi '%s' TARGET2 tidak valid." + +#: elf32-arm.c:6281 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): peringatan: antar-kerja tidak aktif.\n" +" pertemuan pertama: %B: thumb call ke arm" + +#: elf32-arm.c:7003 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Peringatan: Arm BLK instruksi target Arm fungsi '%s'." + +#: elf32-arm.c:7405 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Peringatan: Thumb BLX instruksi target thumb fungsi '%s'." + +#: elf32-arm.c:8085 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_ARM_TLS_LE32 relokasi tidak diperbolehkan dalam objek terbagi" + +#: elf32-arm.c:8300 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Hanya ADD atau SUB instruksi yang diperbolehkan untuk grup ALU relokasi" + +#: elf32-arm.c:8340 elf32-arm.c:8427 elf32-arm.c:8510 elf32-arm.c:8595 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Overflow ketika membagi 0x%lx untuk relokasi grup %s" + +#: elf32-arm.c:8821 elf32-sh.c:3325 elf64-sh64.c:1556 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s relokasi terhadap bagian SEC_MERGE" + +#: elf32-arm.c:8939 elf32-m68k.c:4134 elf32-xtensa.c:2765 elf64-ppc.c:10743 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s digunakan dengan simbol TLS %s" + +#: elf32-arm.c:8940 elf32-m68k.c:4135 elf32-xtensa.c:2766 elf64-ppc.c:10744 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s digunakan dengan simbol bukan-TLS %s" + +#: elf32-arm.c:8997 +msgid "out of range" +msgstr "diluar jangkauan" + +#: elf32-arm.c:9001 +msgid "unsupported relocation" +msgstr "relokasi tidak didukung" + +#: elf32-arm.c:9009 +msgid "unknown error" +msgstr "error tidak diketahui" + +#: elf32-arm.c:9409 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Peringatan: Menghapus tanda antar-kerja dari %B karena bukan kode antar-kerja dalam %B telah dihubungkan dengan itu" + +#: elf32-arm.c:9652 +msgid "error: %B: Unknown CPU architecture" +msgstr "error: %B: Arsitektur CPU tidak diketahui" + +#: elf32-arm.c:9690 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "error: %B: Profil arsitektur konflik %c/%c" + +#: elf32-arm.c:9747 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "error: %B menggunakan reguster argumen VFP, %B tidak" + +#: elf32-arm.c:9897 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "error: %B: Profil arsitektur konflik %c/%c" + +#: elf32-arm.c:9921 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Peringatan: %B: Konflik konfigurasi platform" + +#: elf32-arm.c:9930 +msgid "error: %B: Conflicting use of R9" +msgstr "error: %B: Konflik penggunaan R9" + +#: elf32-arm.c:9942 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "error: %B: SB pengalamatan relatif konflik dengan penggunaan dari R9" + +#: elf32-arm.c:9955 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "peringatan: %B menggunakan %u-byte wchar_t tapi keluaran menggunakan %u-byte wchar_t; menggunakan nilai wchar_t melewati objek mungkin gagal" + +#: elf32-arm.c:9986 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "peringatan: %B menggunakan %s enums tapi keluaran menggunakan %s enums; menggunakan nilai dari enum dari objek mungkin gagal" + +#: elf32-arm.c:9998 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "error: %B menggunakan iWMMXt argumen register, %B tidak" + +#: elf32-arm.c:10020 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "error: fp16 format tidak cocok diantara %B dan %B" + +#: elf32-arm.c:10063 elf32-arm.c:10156 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: atribut objek wajib EABI tidak diketahui %d" + +#: elf32-arm.c:10071 elf32-arm.c:10164 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Peringatan: %B: atribut objek EABI tidak diketahui %d" + +#: elf32-arm.c:10224 +msgid "error: %B is already in final BE8 format" +msgstr "error: %B telah dalam format akhir BE8" + +#: elf32-arm.c:10300 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "error: Sumber objek %B memiliki versi EABI %d, tetapi target %B memiliki versi EABI %d" + +#: elf32-arm.c:10316 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "error: %B dikompile untuk APCS-%d, dimana target %B menggunakan APCS-%d" + +#: elf32-arm.c:10341 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "error: %B menggunakan VFP instruksi, dimana %B tidak" + +#: elf32-arm.c:10345 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "error: %B menggunakan FPA instruksi, dimana %B tidak" + +#: elf32-arm.c:10355 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "error: %B menggunakan Maverick instruksi, dimana %B tidak" + +#: elf32-arm.c:10359 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "error: %B tidak menggunakan Maveric instruksi, dimana %B menggunakan" + +#: elf32-arm.c:10378 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "error: %B menggunakan software FP, dimana %B menggunakan hardware FP" + +#: elf32-arm.c:10382 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "error: %B menggunakan hardware FP, dimana %B menggunakan software FP" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10429 elf32-bfin.c:5082 elf32-cris.c:4110 elf32-m68hc1x.c:1280 +#: elf32-m68k.c:1169 elf32-score.c:4039 elf32-score7.c:3876 elf32-vax.c:540 +#: elfxx-mips.c:12755 +#, c-format +msgid "private flags = %lx:" +msgstr "tanda private = %lx:" + +#: elf32-arm.c:10438 +#, c-format +msgid " [interworking enabled]" +msgstr " [antar-kerja aktif]" + +#: elf32-arm.c:10446 +#, c-format +msgid " [VFP float format]" +msgstr " [VFP float format]" + +#: elf32-arm.c:10448 +#, c-format +msgid " [Maverick float format]" +msgstr " [Maverick float format]" + +#: elf32-arm.c:10450 +#, c-format +msgid " [FPA float format]" +msgstr " [FPA float format]" + +#: elf32-arm.c:10459 +#, c-format +msgid " [new ABI]" +msgstr " [ABI baru]" + +#: elf32-arm.c:10462 +#, c-format +msgid " [old ABI]" +msgstr " [ABI lama]" + +#: elf32-arm.c:10465 +#, c-format +msgid " [software FP]" +msgstr " [software FP]" + +#: elf32-arm.c:10474 +#, c-format +msgid " [Version1 EABI]" +msgstr " [EABI Versi 1]" + +#: elf32-arm.c:10477 elf32-arm.c:10488 +#, c-format +msgid " [sorted symbol table]" +msgstr " [simbol tabel terurut]" + +#: elf32-arm.c:10479 elf32-arm.c:10490 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [simbol tabel tidak terurut]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [Version2 EABI]" +msgstr " [EABI Versi 2]" + +#: elf32-arm.c:10493 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [simbol dinamis menggunakan segmen indek]" + +#: elf32-arm.c:10496 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [simbol map mendahului yang lain]" + +#: elf32-arm.c:10503 +#, c-format +msgid " [Version3 EABI]" +msgstr " [EABI Versi 3]" + +#: elf32-arm.c:10507 +#, c-format +msgid " [Version4 EABI]" +msgstr " [EABI Versi 4]" + +#: elf32-arm.c:10511 +#, c-format +msgid " [Version5 EABI]" +msgstr " [EABI Versi 5]" + +#: elf32-arm.c:10514 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10517 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10523 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10530 +#, c-format +msgid " [relocatable executable]" +msgstr " [relocatable executable]" + +#: elf32-arm.c:10533 +#, c-format +msgid " [has entry point]" +msgstr " [memiliki titik masuk]" + +#: elf32-arm.c:10538 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10783 elf32-i386.c:1300 elf32-s390.c:998 elf32-xtensa.c:1000 +#: elf64-s390.c:952 elf64-x86-64.c:1082 elfxx-sparc.c:1121 +msgid "%B: bad symbol index: %d" +msgstr "%B: memiliki indek simbol: %d" + +#: elf32-arm.c:10904 elf64-x86-64.c:1242 elf64-x86-64.c:1411 elfxx-mips.c:7870 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relokasi %s terhadap `%s' tidak dapat digunkan ketika membuat sebuah objek terbagi; rekompile dengan -fPIC" + +#: elf32-arm.c:11893 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Errors ditemui dalam pemrosesan berkas %s" + +#: elf32-arm.c:13339 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: error: Cortex-A8 erratum stub dialokasikan dalam lokasi yang tidak aman" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13366 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: error: Cortex-A8 erratum stub diluar dari jangkauan (berkas masukan terlalu besar)" + +#: elf32-arm.c:13457 elf32-arm.c:13479 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: error: VFP11 veneer diluar jangkauan" + +#: elf32-avr.c:1259 elf32-bfin.c:3208 elf32-cris.c:2097 elf32-fr30.c:624 +#: elf32-frv.c:4122 elf32-i860.c:1226 elf32-ip2k.c:1510 elf32-iq2000.c:699 +#: elf32-m32c.c:568 elf32-mep.c:549 elf32-moxie.c:299 elf32-msp430.c:501 +#: elf32-mt.c:406 elf32-openrisc.c:419 elf32-v850.c:1709 elf32-xstormy16.c:956 +#: elf64-mmix.c:1541 +msgid "internal error: dangerous relocation" +msgstr "internal error: relokasi berbahaya" + +#: elf32-avr.c:2409 elf32-hppa.c:605 elf32-m68hc1x.c:165 elf64-ppc.c:4141 +msgid "%B: cannot create stub entry %s" +msgstr "%B: tidak dapat membuat masukan stub %s" + +#: elf32-bfin.c:1581 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): relokasi tidak teresolf terhadap simbol `%s'" + +#: elf32-bfin.c:1614 elf32-i386.c:4026 elf32-m68k.c:4176 elf32-s390.c:3067 +#: elf64-s390.c:3026 elf64-x86-64.c:3697 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): relokasi terhadap `%s': error %d" + +#: elf32-bfin.c:2714 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: relokasi di `%A+0x%x' simbol referensi `%s' dengan bukan nol ditambahkan" + +#: elf32-bfin.c:2728 elf32-frv.c:2904 +msgid "relocation references symbol not defined in the module" +msgstr "relokasi referensi simbol tidak didefinisikan dalam modul" + +#: elf32-bfin.c:2825 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC referensi simbol dinamis dengan bukan nol ditambahkan" + +#: elf32-bfin.c:2866 elf32-bfin.c:2989 elf32-frv.c:3641 elf32-frv.c:3762 +msgid "cannot emit fixups in read-only section" +msgstr "tidak dapat mengeluarkan fixups dalam bagian baca-saja" + +#: elf32-bfin.c:2897 elf32-bfin.c:3027 elf32-frv.c:3672 elf32-frv.c:3806 +#: elf32-lm32.c:1104 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "tidak dapat mengeluarkan relokasi dinamis dalam bagian baca-saja" + +#: elf32-bfin.c:2947 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE referensi simbol dinamis dengan bukan nol ditambahkan" + +#: elf32-bfin.c:3112 +msgid "relocations between different segments are not supported" +msgstr "relokasi diantara segmen berbeda tidak didukung" + +#: elf32-bfin.c:3113 +msgid "warning: relocation references a different segment" +msgstr "peringatan: relokasi referensi sebuah segmen berbeda" + +#: elf32-bfin.c:4974 elf32-frv.c:6408 +msgid "%B: unsupported relocation type %i" +msgstr "%B: tipe relokasi %i tidak didukung" + +#: elf32-bfin.c:5127 elf32-frv.c:6816 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: tidak dapat menghubungkan berkas objek bukan-fdpic kedalam aplikasi fdpic" + +#: elf32-bfin.c:5131 elf32-frv.c:6820 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: tidak dapat menghubungkan berkas objek fdpic kedalam aplikasi bukan-fdpic" + +#: elf32-cris.c:1169 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, bagian %A: relokasi tidak teresolf %s terhadap simbol `%s'" + +#: elf32-cris.c:1238 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, bagian %A: Bukan PLT atau GOT untuk relokasi %s terhadap simbol `%s'" + +#: elf32-cris.c:1240 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, bagian %A: Bukan PLT untuk relokasi %s terhadap simbol `%s'" + +#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1641 elf32-cris.c:1730 +#: elf32-cris.c:1883 +msgid "[whose name is lost]" +msgstr "[yang namanya hilang]" + +#: elf32-cris.c:1365 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, bagian %A: relokasi %s dengan bukan-nol ditambahkan %d terhadap simbol lokal" + +#: elf32-cris.c:1373 elf32-cris.c:1724 elf32-cris.c:1877 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, bagian %A: relokasi %s dengan bukan-nol ditambakan %d terhadap simbol `%s'" + +#: elf32-cris.c:1399 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, bagian %A: relokasi %s tidak diperbolehkan untuk simbol global: `%s'" + +#: elf32-cris.c:1415 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, bagian %A: relokasi %s dengan tidak GOT dibuat" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1632 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, bagian %A: relokasi %s memiliki sebuah referensi tidak terdefinisi ke `%s', mungkin sebuah kesalahan deklarasi?" + +#: elf32-cris.c:2010 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, bagian %A: relokasi %s tidak diperbolehkan untuk simbol global: `%s' yang didefinisikan diluar aplikasi, mungkin sebuah kesalahan deklarasi?" + +#: elf32-cris.c:2063 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(terlalu banyak variabel global untuk -fpic: rekompilasi dengan -fPIC)" + +#: elf32-cris.c:2070 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(thread-local data terlalu besar untuk -fpic atau -msmall-tls: rekompilasi dengan -fPIC atau -mno-small-tls)" + +#: elf32-cris.c:3204 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, bagian %A:\n" +" v10/v32 objek kompatibel %s harus berisi sebuah relokasi PIC" + +#: elf32-cris.c:3309 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, bagian %A:\n" +" relokasi %s tidak valid dalam sebuah objek terbagi; umumnya sebuah kesalahan pilihan, rekompile dengan -fPIC" + +#: elf32-cris.c:3523 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, bagian %A:\n" +" relokasi %s seharusnya digunakan dalam sebuah objek terbagi; rekompile dengan -fPIC" + +#: elf32-cris.c:3940 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, bagian `%A', ke simbol `%s':\n" +" relokasi %s seharusnya digunakan dalam sebuah objek terbagi; rekompilasi dengan -fPIC" + +#: elf32-cris.c:4059 +msgid "Unexpected machine number" +msgstr "Nomor mesin tidak terduga" + +#: elf32-cris.c:4113 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [simbol memiliki sebuah awalan _]" + +#: elf32-cris.c:4116 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 dan v32]" + +#: elf32-cris.c:4119 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4164 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: menggunakan awalan _ simbol, tetapi menulis berkas dengan simbol tanpa awalan" + +#: elf32-cris.c:4165 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: menggunakan simbol tanpa awalan, tetapi menulis berkas dengan simbol awalan _" + +#: elf32-cris.c:4184 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B berisi kode CRIS v32, tidak kompatibel dengan objek sebelumnya" + +#: elf32-cris.c:4186 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B berisi kode bukan CRIS v32, tidak kompatibel dengan objek sebelumnya" + +#: elf32-frv.c:1507 elf32-frv.c:1656 +msgid "relocation requires zero addend" +msgstr "relokasi membutuhkan penambahan nol" + +#: elf32-frv.c:2891 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): relokasi ke `%s+%x' mungkin menyebabkan error diatas" + +#: elf32-frv.c:2980 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF tidak teraplikasi untuk sebuah panggilan instruksi" + +#: elf32-frv.c:3022 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 tidak teraplikasi untuk sebuah instruksi lddi" + +#: elf32-frv.c:3093 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI tidak teraplikasi untuk sebuah instruksi sethi" + +#: elf32-frv.c:3130 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO tidak teraplikasi untuk sebuah instruksi setlo atau setlos" + +#: elf32-frv.c:3178 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX tidak teraplikasi untuk sebuah instruksi ldd" + +#: elf32-frv.c:3262 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX tidak teraplikasi untuk sebuah instruksi calll" + +#: elf32-frv.c:3317 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GETTLSOFF12 tidak teraplikasi untuk sebuah instruksi ldi" + +#: elf32-frv.c:3347 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI tidak teraplikasi untuk sebuah instruksi sethi" + +#: elf32-frv.c:3376 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO tidak teraplikasi untuk sebuah instruksi setlo atau setlos" + +#: elf32-frv.c:3407 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX tidak teraplikasi untuk sebuah instruksi ld" + +#: elf32-frv.c:3452 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI tidak teraplikasi untuk sebuah instruksi sethi" + +#: elf32-frv.c:3479 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO tidak teraplikasi untuk sebuah instruksi setlo atau setlos" + +#: elf32-frv.c:3600 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC referensi simbol dinamis dengan penambahan bukan nol" + +#: elf32-frv.c:3720 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE referensi simbol dinamis dengan penambahan bukan nol" + +#: elf32-frv.c:3977 elf32-frv.c:4133 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): relokasi terhadap `%s': %s" + +#: elf32-frv.c:3979 elf32-frv.c:3983 +msgid "relocation references a different segment" +msgstr "relokasi referensi ke segmen berbeda" + +#: elf32-frv.c:6730 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: terkompile dengan %s dan terhubung dengan modul yang menggunakan relokasi bukan-pic" + +#: elf32-frv.c:6783 elf32-iq2000.c:852 elf32-m32c.c:814 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: terkompile dengan %s dan terhubung dengan modul terkompile dengan %s" + +#: elf32-frv.c:6795 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: menggunakan bagian e_flags (0x%lx) berbeda yang tidak dikenal dari modul sebelumnya (0x%lx)" + +#: elf32-frv.c:6845 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "private flags = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Relokasi dalam ELF standar (EM: %d)" + +#: elf32-hppa.c:854 elf32-hppa.c:3570 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): tidak dapat mencapai %s, rekompile dengan -ffunction-sections" + +#: elf32-hppa.c:1286 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: relokasi %s tidak dapat digunakan ketika membuat sebuah objek terbagi; rekompile dengan -fPIC" + +#: elf32-hppa.c:2780 +msgid "%B: duplicate export stub %s" +msgstr "%B: duplikasi export stub %s" + +#: elf32-hppa.c:3406 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s fixup untuk insn 0x%x tidak didukung dalam sebuah sambunga tidak terbagi" + +#: elf32-hppa.c:4260 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): tidak dapat menangani %s untuk %s" + +#: elf32-hppa.c:4567 +msgid ".got section not immediately after .plt section" +msgstr "bagian .got tidak mengikuti bagian .plt" + +#: elf32-i386.c:371 elf32-ppc.c:1666 elf32-s390.c:379 elf64-ppc.c:2283 +#: elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: tipe relokasi %d tidak valid" + +#: elf32-i386.c:1246 elf64-x86-64.c:1029 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: TLS transisi dari %s ke %s terhadap `%s' di 0x%lx dalam bagian `%A' gagal" + +#: elf32-i386.c:1387 elf32-i386.c:2970 elf64-x86-64.c:1171 elf64-x86-64.c:2680 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: relokasi %s terhadap STT_GNU_IFUNC simbol `%s' tidak ditangani oleh %s" + +#: elf32-i386.c:1548 elf32-s390.c:1180 elf32-sh.c:5065 elf32-xtensa.c:1173 +#: elf64-s390.c:1143 elfxx-sparc.c:1257 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: `%s' terakses kedua sebagai normal dan memperlakukan lokal simbol" + +#: elf32-i386.c:2805 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: relokasi tidak dikenal (0x%x) dalam bagian `%A'" + +#: elf32-i386.c:3219 elf64-x86-64.c:3081 +msgid "hidden symbol" +msgstr "simbol tersembunyi" + +#: elf32-i386.c:3222 elf64-x86-64.c:3084 +msgid "internal symbol" +msgstr "internal simbol" + +#: elf32-i386.c:3225 elf64-x86-64.c:3087 +msgid "protected symbol" +msgstr "simbol terproteksi" + +#: elf32-i386.c:3228 elf64-x86-64.c:3090 +msgid "symbol" +msgstr "simbol" + +#: elf32-i386.c:3233 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: relokasi R_386_GOTOFF terhadap %s `%s' tidak terdefinisi tidak dapat digunakan ketika membuah sebuah objek terbagi" + +#: elf32-i386.c:3243 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: relokasi R_386_GOTOFF terhadap fungsi terproteksi `%s' tidak dapat digunakan ketika membuat sebuah objek terbagi" + +#: elf32-ip2k.c:868 elf32-ip2k.c:874 elf32-ip2k.c:941 elf32-ip2k.c:947 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k relaxer: tabel switch tanpa pencocokan informasi relokasi lengkap." + +#: elf32-ip2k.c:891 elf32-ip2k.c:974 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k relaxer: switch tabel header terkorupsi." + +#: elf32-ip2k.c:1316 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: hilang halaman instruksi di 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1332 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: redundant halaman instruksi di 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1506 +msgid "unsupported relocation between data/insn address spaces" +msgstr "relokasi tidak didukung diantara data/insn ruang alamat" + +#: elf32-iq2000.c:865 elf32-m32c.c:826 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: menggunakan e_flags (0x%lx) field berbeda dari modul sebelumnya (0x%lx)" + +#: elf32-lm32.c:698 +msgid "global pointer relative relocation when _gp not defined" +msgstr "penunjuk global relokasi relatif waktu _gp tidak terdefinisi" + +#: elf32-lm32.c:753 +msgid "global pointer relative address out of range" +msgstr "penunjuk global alamat relatif diluar dari jangkauan" + +#: elf32-lm32.c:1058 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "kesalahan internal: addend seharusnya nol untuk R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "SDA relokasi ketika _SDA_BASE_ tidak terdefinisi" + +#: elf32-m32r.c:3039 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: Target (%s) dari sebuah %s relokasi berada dalam bagian yang salah (%A)" + +#: elf32-m32r.c:3567 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Set Instruksi tidak cocok dengan modul sebelumnya" + +#: elf32-m32r.c:3588 +#, c-format +msgid "private flags = %lx" +msgstr "private flags = %lx" + +#: elf32-m32r.c:3593 +#, c-format +msgid ": m32r instructions" +msgstr ": m32r instruksi" + +#: elf32-m32r.c:3594 +#, c-format +msgid ": m32rx instructions" +msgstr ": m32rx instruksi" + +#: elf32-m32r.c:3595 +#, c-format +msgid ": m32r2 instructions" +msgstr ": m32r2 instruksi" + +#: elf32-m68hc1x.c:1048 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Referensi ke simbol jauh `%s' menggunakan relokasi salah mungkin akan menghasilkan eksekusi salah" + +#: elf32-m68hc1x.c:1071 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "banked address [%lx:%04lx] (%lx) tidak dalam bank yang sama seperti dalam alamat bank sekarang [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1090 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "referensi ke alamat bank [%lx:%04lx] dalam ruang alamat normal di %04lx" + +#: elf32-m68hc1x.c:1223 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: menghubungkan berkas yang dikompile untuk 16-bit integer (-mshort) dan yang lain untuk 32-bit integer" + +#: elf32-m68hc1x.c:1230 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: menghubungkan berkas yang dikompile untuk 32-bit double (-fshort-double) dan yang lain untuk 64-bit double" + +#: elf32-m68hc1x.c:1239 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: menghubungkan berkas dikompile untuk HCS12 dengan yang lain dikompile untuk HC12" + +#: elf32-m68hc1x.c:1255 elf32-ppc.c:4255 elf64-sparc.c:698 elfxx-mips.c:12617 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: menggunakan field e_flags (0x%lx) berbeda dari modul sebelumnya (0x%lx)" + +#: elf32-m68hc1x.c:1283 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1288 +#, c-format +msgid "64-bit double, " +msgstr "64-bit double, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "32-bit double, " +msgstr "32-bit double, " + +#: elf32-m68hc1x.c:1293 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1300 +#, c-format +msgid " [memory=bank-model]" +msgstr " [memory=bank-model]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=flat]" +msgstr " [memory=flat]" + +#: elf32-m68k.c:1184 elf32-m68k.c:1185 +msgid "unknown" +msgstr "tidak dikenal" + +#: elf32-m68k.c:1645 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: GOT overflow: Jumlah dari relokasi dengan offset 8-bit > %d" + +#: elf32-m68k.c:1651 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: GOT overflow: Jumlah dari relokasi dengan offset 8- atau 16-bit > %d" + +#: elf32-m68k.c:3902 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_68K_TLS_LE32 relokasi tidak diperbolehkan dalam objek terbagi" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Relokasi %s (%d) saat ini tidak didukung.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Tipe relokasi %d tidak dikenal\n" + +#: elf32-mep.c:654 +msgid "%B and %B are for different cores" +msgstr "%B dan %B adalah untuk cores berbeda" + +#: elf32-mep.c:671 +msgid "%B and %B are for different configurations" +msgstr "%B dan %B adalah untuk konfigurasi berbeda" + +#: elf32-mep.c:708 +#, c-format +msgid "private flags = 0x%lx" +msgstr "private flags = 0x%lx" + +#: elf32-microblaze.c:737 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: tipe relokasi %d tidak diketahui" + +#: elf32-microblaze.c:862 elf32-microblaze.c:907 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Target (%s) dari sebuah %s relokasi berada dalam bagian yang salah (%s)" + +#: elf32-microblaze.c:1150 elfxx-sparc.c:2957 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: mungkin dikompile tanpa -fPIC?" + +#: elf32-microblaze.c:2086 elflink.c:12444 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: relokasi bagian nama `%s' buruk" + +#: elf32-mips.c:1045 elf64-mips.c:2083 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "literal relokasi terjadi untuk simbol eksternal" + +#: elf32-mips.c:1085 elf32-score.c:580 elf32-score7.c:480 elf64-mips.c:2126 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32bit gp relative relokasi terjadi untuk sebuah simbol eksternal" + +#: elf32-ppc.c:1731 +#, c-format +msgid "generic linker can't handle %s" +msgstr "linker generik tidak dapat menangani %s" + +#: elf32-ppc.c:2211 +msgid "corrupt or empty %s section in %B" +msgstr "korup atau kosong %s bagian dalam %B" + +#: elf32-ppc.c:2218 +msgid "unable to read in %s section from %B" +msgstr "tidak dapat membaca dalam bagian %s dari %B" + +#: elf32-ppc.c:2224 +msgid "corrupt %s section in %B" +msgstr "korup bagian %s dalam %B" + +#: elf32-ppc.c:2267 +msgid "warning: unable to set size of %s section in %B" +msgstr "peringatan: tidak dapat menset ukuran bagian %s dalam %B" + +#: elf32-ppc.c:2315 +msgid "failed to allocate space for new APUinfo section." +msgstr "gagal mengalokasikan ruang untuk bagian baru APUinfo." + +#: elf32-ppc.c:2334 +msgid "failed to compute new APUinfo section." +msgstr "gagal untuk menghitung bagian baru APUinfo." + +#: elf32-ppc.c:2337 +msgid "failed to install new APUinfo section." +msgstr "gagal untuk memasang bagian baru APUinfo." + +#: elf32-ppc.c:3364 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: relokasi %s tidak dapat digunakan ketika membuat sebuah objek terbagi" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3723 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s relokasi terhadap simbol lokal" + +#: elf32-ppc.c:4067 elf32-ppc.c:4082 elfxx-mips.c:12324 elfxx-mips.c:12350 +#: elfxx-mips.c:12372 elfxx-mips.c:12398 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Peringatan: %B menggunakan hard float, %B menggunakan soft float" + +#: elf32-ppc.c:4070 elf32-ppc.c:4074 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Peringatan: %B menggunakan double-precision hard float, %B menggunakan single-precision hard float" + +#: elf32-ppc.c:4078 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Peringatan: %B menggunakan soft float, %B menggunakan single-precision hard float" + +#: elf32-ppc.c:4085 elf32-ppc.c:4089 elfxx-mips.c:12304 elfxx-mips.c:12308 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Peringatan: %B menggunkaan floating point ABI %d" + +#: elf32-ppc.c:4131 elf32-ppc.c:4135 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Peringatan: %B menggunakan vector ABI %d tidak dikenal" + +#: elf32-ppc.c:4139 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Peringatan: %B menggunakan vector ABI \"%s\", %B menggunakan \"%s\"" + +#: elf32-ppc.c:4156 elf32-ppc.c:4159 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Peringatan: %B menggunakan r3/34 untuk arsitektur kembali kecil, %B menggunakan memori" + +#: elf32-ppc.c:4162 elf32-ppc.c:4166 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Peringatan: %B menggunakan konvensi struktur kembali kecil %d tidak diketahui" + +#: elf32-ppc.c:4220 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: dikompile dengan -mrelocatable dan dihubungkan dengan module yang dikompile secara normal" + +#: elf32-ppc.c:4228 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: dikompile secara normal dan dihubungkan dengan modul yang dikompile dengan -mrelocatable" + +#: elf32-ppc.c:4314 +msgid "Using bss-plt due to %B" +msgstr "Menggunakan bss-plt karena %B" + +#: elf32-ppc.c:7056 elf64-ppc.c:11364 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: tipe relokasi %d tidak dikenal untuk simbol %s" + +#: elf32-ppc.c:7316 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): bukan-nol ditambahkan di %s relokasi terhadap `%s'" + +#: elf32-ppc.c:7499 elf64-ppc.c:11854 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): Relokasi %s untuk fungsi tidak langsung %s tidak didukung." + +#: elf32-ppc.c:7709 elf32-ppc.c:7736 elf32-ppc.c:7787 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: target (%s) dari sebuah relokasi %s berada dalam daerah keluaran salah (%s)" + +#: elf32-ppc.c:7847 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: relokasi %s tidak didukung untuk simbol %s." + +#: elf32-ppc.c:7955 elf64-ppc.c:12110 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): %s relokasi terhadap `%s': error %d" + +#: elf32-ppc.c:8423 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s tidak didefinisikan dalam %s yang dibuat oleh penyambung" + +#: elf32-s390.c:2207 elf64-s390.c:2179 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): instruksi tidak valid untuk relokasi TLS %s" + +#: elf32-score.c:1533 elf32-score7.c:1424 elfxx-mips.c:3299 +msgid "not enough GOT space for local GOT entries" +msgstr "tidak cukup ruang GOT untuk masukan lokal GOT" + +#: elf32-score.c:2765 +msgid "address not word align" +msgstr "alamat tidak selaras dengan ukuran word" + +#: elf32-score.c:2850 elf32-score7.c:2685 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: relokasi malformat terdeteksi untuk bagian %s" + +#: elf32-score.c:2901 elf32-score7.c:2736 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL15 relokasi di 0x%lx tidak terhadap simbol global" + +#: elf32-score.c:4042 elf32-score7.c:3879 +#, c-format +msgid " [pic]" +msgstr " [pic]" + +#: elf32-score.c:4046 elf32-score7.c:3883 +#, c-format +msgid " [fix dep]" +msgstr " [fix dep]" + +#: elf32-score.c:4088 elf32-score7.c:3925 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: peringatan: menghubungkan berkas PIC dengan berkas bukan-PIC" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: IMPORT SEBAGAI direktif untuk %s menyembunyikan IMPORT SEBAGAI sebelumnya" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: Perintah .directive tidak dikenal: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Gagal menambahkan simbol diubah namanya %s" + +#: elf32-sh.c:533 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: peringatan: ofset R_SH_USES buruk" + +#: elf32-sh.c:545 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: peringatan: R_SH_USES titik tidak dikenal insn 0x%x" + +#: elf32-sh.c:562 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: peringatan: ofset R_SH_USES beban buruk" + +#: elf32-sh.c:577 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: peringatan: tidak dapat menemukan relokasi yang diperkirakan" + +#: elf32-sh.c:605 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: peringatan: simbol dalam bagian yang tidak diperkirakan" + +#: elf32-sh.c:731 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: peringatan: tidak dapat menemukan COUNT relokasi" + +#: elf32-sh.c:740 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: peringatan: jumlah buruk" + +#: elf32-sh.c:1144 elf32-sh.c:1514 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: fatal: relokasi overflow ketika relaxing" + +#: elf32-sh.c:3270 elf64-sh64.c:1526 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Tidak diperkirakan STO_SH5_ISA32 di simbol lokal tidak ditangani" + +#: elf32-sh.c:3507 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: fatal: unaligned branch target untuk relax-support relokasi" + +#: elf32-sh.c:3540 elf32-sh.c:3555 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: fatal: unaligned %s relokasi 0x%lx" + +#: elf32-sh.c:3569 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: R_SH_PSHA relokasi %d tidak dalam jangkauan -32..32" + +#: elf32-sh.c:3583 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: fatal: R_SH_PSHL relokasi %d tidak dalam jangkauan -32..32" + +#: elf32-sh.c:5256 elf64-alpha.c:4525 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: TLS lokal exec kode tidak dapat dihubungkan dalam objek terbagi" + +#: elf32-sh64.c:222 elf64-sh64.c:2333 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: dikompile sebagai 32-bit objek dan %s adalah 64-bit" + +#: elf32-sh64.c:225 elf64-sh64.c:2336 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: dikompile sebagai 64-bit objek dan %s adalah 32-bit" + +#: elf32-sh64.c:227 elf64-sh64.c:2338 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: ukuran objek tidak cocok dari target %s" + +#: elf32-sh64.c:450 elf64-sh64.c:2852 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: ditemui datalabel simbol dalam masukan" + +#: elf32-sh64.c:527 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB tidak cocok: sebuah SHmedia alamat (bit 0 ==1)" + +#: elf32-sh64.c:530 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA tidak cocok: sebuah SHcompact alamat (bit 0 == 0)" + +#: elf32-sh64.c:548 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: GAS error: tidak diduga PTB insn dengan R_SH_PT_16" + +#: elf32-sh64.c:597 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: error: tipe relokasi unaligned %d di %08x relokasi %p\n" + +#: elf32-sh64.c:673 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: tidak dapat menulis masukan tambahan .cranges" + +#: elf32-sh64.c:733 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: tidak dapat menulis masukan terurut .cranges" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: dikompile untuk sebuah sistem 64 bit dan target adalah 32 bit" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: menghubungkan berkas little endian dengan berkas big endian" + +#: elf32-spu.c:723 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: bagian overlay %A jangan diawali di sebuah baris cache.\n" + +#: elf32-spu.c:731 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: bagian overlay %A lebih besar daripada baris cache.\n" + +#: elf32-spu.c:751 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: bagian overlay %A tidak berada dalam daerah cache.\n" + +#: elf32-spu.c:791 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: bagian overlay %A dan %A jangan diawali di alamat yang sama.\n" + +#: elf32-spu.c:1015 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "peringatan: panggilan bukan-fungsi simbol %s didefinisikan dalam %B" + +#: elf32-spu.c:1365 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) berbeda dari analisa (%u)\n" + +#: elf32-spu.c:1884 +msgid "%B is not allowed to define %s" +msgstr "%B tidak diperbolehkan untuk didefinisikan %s" + +#: elf32-spu.c:1892 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "anda tidak diperbolehkan untuk mendefinisikan %s dalam sebuah script" + +#: elf32-spu.c:1926 +#, c-format +msgid "%s in overlay section" +msgstr "%s dalam daerah overlay" + +#: elf32-spu.c:1955 +msgid "overlay stub relocation overflow" +msgstr "relokasi stub overlay overflow" + +#: elf32-spu.c:1964 elf64-ppc.c:10441 +msgid "stubs don't match calculated size" +msgstr "stub tidak cocok dengan ukuran yang dihitung" + +#: elf32-spu.c:2546 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "peringatan: %s timpang tindih %s\n" + +#: elf32-spu.c:2562 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "peringatan: %s melebihi ukuran daerah\n" + +#: elf32-spu.c:2593 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v tidak ditemukan dalam tabel fungsi\n" + +#: elf32-spu.c:2740 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): panggilan untuk daerah bukan-kode %B(%A), analysis tidak lengkap\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "Stack analysis akan mengabaikan panggilan dari %s ke %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " panggilan:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4304 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s duplikasi dalam %s\n" + +#: elf32-spu.c:4308 +#, c-format +msgid "%s duplicated\n" +msgstr "%s duplikasi\n" + +#: elf32-spu.c:4315 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "maaf, tidak ada dukungan untuk duplikasi berkas objek dalam auto-overlay script\n" + +#: elf32-spu.c:4356 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "ukuran non-overlay dari 0x%v plus maksimul overlay size dari 0x%v melebihi lokal store\n" + +#: elf32-spu.c:4512 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s melebihi ukuran overlay\n" + +#: elf32-spu.c:4669 +msgid "Stack size for call graph root nodes.\n" +msgstr "Ukuran stack untuk panggilan graph titik root.\n" + +#: elf32-spu.c:4670 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Ukuran stack untuk fungsi. Anotasi: '*' max stack, 't' tail call\n" + +#: elf32-spu.c:4680 +msgid "Maximum stack required is 0x%v\n" +msgstr "Maksimal stack dibutuhkan adalah 0x%v\n" + +#: elf32-spu.c:4771 +msgid "fatal error while creating .fixup" +msgstr "kesalahan fatal ketika membuat .fixup" + +#: elf32-spu.c:5009 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s=0x%lx): tidak teresolf %s relokasi terhadap simbol `%s'" + +#: elf32-v850.c:163 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variabel `%s' tidak dapat mengisi dalam beberapa daerah data kecil" + +#: elf32-v850.c:166 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variabel `%s' hanya dapat berada dalam satu dari kecil, nol, dan sangat kecil daerah data" + +#: elf32-v850.c:169 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variabel `%s' tidak dapat berada dalam kecil dan nol daerah data secara bersamaan" + +#: elf32-v850.c:172 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variabel `%s' tidak dapat berada dalam kecil dan sangat kecil daerah data secara bersamaan" + +#: elf32-v850.c:175 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "variabel `%s' tidak dapat dalam nol dan kecil daerah data secara bersamaan" + +#: elf32-v850.c:478 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "GAGAL untuk menemukan relokasi HI16 sebelumnya\n" + +#: elf32-v850.c:1713 +msgid "could not locate special linker symbol __gp" +msgstr "tidak dapat menemukan simbol linker spesial __gp" + +#: elf32-v850.c:1717 +msgid "could not locate special linker symbol __ep" +msgstr "tidak dapat menemukan simbol linker spesial __ep" + +#: elf32-v850.c:1721 +msgid "could not locate special linker symbol __ctbp" +msgstr "tidak dapat menemukan simbol linker spesial __ctbp" + +#: elf32-v850.c:1871 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: Arsitektur tidak cocok dengan modul sebelumnya" + +#: elf32-v850.c:1890 +#, c-format +msgid "private flags = %lx: " +msgstr "private flags = %lx: " + +#: elf32-v850.c:1895 +#, c-format +msgid "v850 architecture" +msgstr "v850 arsitektur" + +#: elf32-v850.c:1896 +#, c-format +msgid "v850e architecture" +msgstr "v850e arsitektur" + +#: elf32-v850.c:1897 +#, c-format +msgid "v850e1 architecture" +msgstr "v850e1 arsitektur" + +#: elf32-vax.c:543 +#, c-format +msgid " [nonpic]" +msgstr " [bukan-pic]" + +#: elf32-vax.c:546 +#, c-format +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:549 +#, c-format +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:666 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: peringatan: GOT ditambahkan dari %ld ke `%s' tidak cocok dengan penambahan GOT sebelumnya dari %ld" + +#: elf32-vax.c:1608 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: peringatan: PLT ditambahkan dari %d ke `%s' dari %s bagian diabaikan" + +#: elf32-vax.c:1735 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: peringatan: %s relokasi terhadap simbol `%s' dari bagian %s" + +#: elf32-vax.c:1741 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: peringatan: relokasi %s ke 0x%x dari daerah %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2791 elf64-ia64.c:2791 +msgid "non-zero addend in @fptr reloc" +msgstr "bukan-nol ditambahkan dalam @fptr relokasi" + +#: elf32-xtensa.c:912 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): tabel properti tidak valid" + +#: elf32-xtensa.c:2740 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): ofset relokasi diluar jangkauan (size=0x%x)" + +#: elf32-xtensa.c:2819 elf32-xtensa.c:2940 +msgid "dynamic relocation in read-only section" +msgstr "relokasi dinamis dalam bagian baca-saja" + +#: elf32-xtensa.c:2916 +msgid "TLS relocation invalid without dynamic sections" +msgstr "relokasi TLS tidak valid tanpa bagian dinamis" + +#: elf32-xtensa.c:3133 +msgid "internal inconsistency in size of .got.loc section" +msgstr "internal tidak konsisten dalam ukuran dari daerah .got.loc" + +#: elf32-xtensa.c:3443 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: tipe mesin tidak kompatibel. Keluaran adalah 0x%x. Masukan adalah 0x%x" + +#: elf32-xtensa.c:4672 elf32-xtensa.c:4680 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Mencoba untuk mengubah L32R/CALLX ke CALL gagal" + +#: elf32-xtensa.c:6290 elf32-xtensa.c:6366 elf32-xtensa.c:7486 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): tidak dapat mendeko instruksi; mungkin konfigurasi tidak cocok" + +#: elf32-xtensa.c:7226 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): tidak dapat mendeko instruksi untuk XTENSA_ASM_SIMPLIFY relokasi; mungkin konfigurasi tidak cocok" + +#: elf32-xtensa.c:8987 +msgid "invalid relocation address" +msgstr "alamat relokasi tidak valid" + +#: elf32-xtensa.c:9036 +msgid "overflow after relaxation" +msgstr "overflow setelah relaksasi" + +#: elf32-xtensa.c:10167 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): unexpected fix untuk relokasi %s" + +#: elf64-alpha.c:452 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP relokasi tidak dapat menemukan instruksi ldah dan lda" + +#: elf64-alpha.c:2389 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: .got subsegmen melebihi 64K (size %d)" + +#: elf64-alpha.c:4269 elf64-alpha.c:4281 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: gp-relative relokasi terhadap simbol dinamis %s" + +#: elf64-alpha.c:4307 elf64-alpha.c:4442 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: pc-relative relokasi terhadap simbol dinamis %s" + +#: elf64-alpha.c:4335 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: perubahan dalam gp: BRSGP %s" + +#: elf64-alpha.c:4360 +msgid "" +msgstr "" + +#: elf64-alpha.c:4365 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: !samegp relokasi terhadap simbol tanpa .prologue: %s" + +#: elf64-alpha.c:4417 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: relokasi dinamis tidak ditangani terhadap %s" + +#: elf64-alpha.c:4449 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: pc-relative relokasi terhadap simbol lemah tidak terdefinisi %s" + +#: elf64-alpha.c:4509 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: dtp-relative relokasi terhadap simbol dinamis %s" + +#: elf64-alpha.c:4532 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: tp-relative relokasi terhadap simbol dinamis %s" + +#: elf64-hppa.c:2091 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "masukan stub untuk %s tidak dapat diload .plt, dp ofset = %ld" + +#: elf64-hppa.c:3273 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): tidak dapat mencapai %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Internal tidak konsisten error untuk nilai untuk\n" +" linker-allocated global register: terhubung: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" + +#: elf64-mmix.c:1618 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: base-plus-offset relokasi terhadap simbol register: (tidak diketahui) dalam %s" + +#: elf64-mmix.c:1623 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: base-plus-offset relokasi terhadap simbol register: %s dalam %s" + +#: elf64-mmix.c:1667 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: register relokasi terhadap non-register simbol: (tidak diketahui) dalam %s" + +#: elf64-mmix.c:1672 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: register relokasi terhadap bukan-register simbol: %s dalam %s" + +#: elf64-mmix.c:1709 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: direktif LOKAL hanya valid dengan sebuah register atau nilai absolut" + +#: elf64-mmix.c:1737 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: LOKAL direktif: Register $%ld bukan sebuah lokal register. Pertama global registar adala $%ld." + +#: elf64-mmix.c:2201 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Error: multiple definisi dari `%s'; awal dari %s adalah diset dalam sebuah sebelum berkas terlink\n" + +#: elf64-mmix.c:2259 +msgid "Register section has contents\n" +msgstr "Daerah register memiliki isi\n" + +#: elf64-mmix.c:2451 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Internal tidak konsisten: sisa %u != max %u.\n" +" Tolong laporkan bug ini." + +#: elf64-ppc.c:2691 libbfd.c:978 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: dikompile untuk sebuah sistem big endian dan target adalah little endian" + +#: elf64-ppc.c:2694 libbfd.c:980 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: dikompile untuk sebuah sistem little endian dan target adalah big endian" + +#: elf64-ppc.c:6338 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "salin relokasi terhadap `%s' membutuhkan lazy plt linking; hindari konfigurasi LD_BIND_NOW=1 atau upgrade gcc" + +#: elf64-ppc.c:6767 +msgid "dynreloc miscount for %B, section %A" +msgstr "dynareloc miscount untuk %B, bagian %A" + +#: elf64-ppc.c:6851 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd adalah bukan array regular dari masukan opd" + +#: elf64-ppc.c:6860 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: tipe relokasi %u tidak diduga dalam bagian .opd" + +#: elf64-ppc.c:6881 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: tidak terdefinisi simbol `%s' dalam bagian .opd" + +#: elf64-ppc.c:7640 elf64-ppc.c:8017 +#, c-format +msgid "%s defined in removed toc entry" +msgstr "%s terdefinisi dalam masukan toc terhapus" + +#: elf64-ppc.c:8910 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "stub brach panjang `%s' ofset overflow" + +#: elf64-ppc.c:8969 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "tidak dapat menemukan branch stub `%s'" + +#: elf64-ppc.c:9031 elf64-ppc.c:9169 +#, c-format +msgid "linkage table error against `%s'" +msgstr "linkage tabel error terhadap `%s'" + +#: elf64-ppc.c:9326 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "tidak dapat membuat branch stub `%s'" + +#: elf64-ppc.c:9799 +msgid "%B section %A exceeds stub group size" +msgstr "%B bagian %A melebihi ukuran grup stub" + +#: elf64-ppc.c:10453 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"linker stubs dalam %u grup %s\n" +" cabang %lu\n" +" toc adjust %lu\n" +" cabang panjang %lu\n" +" long toc adj %lu\n" +" plt call %lu" + +#: elf64-ppc.c:11252 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): otomatis multiple TOC tidak didukung menggunakan berkas crt anda; rekompile dengan -mminimal-toc atau upgrade gcc" + +#: elf64-ppc.c:11260 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): sibling call optimization ke `%s' tidak membolehkan otomatis multiple TOC; rekompile dengan -mminimal-toc atau -fno-optimize-sibling-calls, atau buat `%s' extern" + +#: elf64-ppc.c:11961 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: relokasi %s tidak didukung untuk simbol %s." + +#: elf64-ppc.c:12044 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: error: relokasi %s bukan multiple dari %d" + +#: elf64-sh64.c:1701 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: error: tipe relokasi %d unaligned di %08x relokasi %08x\n" + +#: elf64-sparc.c:439 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Hanya register %%g[2367] dapat dideklarasikan menggunakan STT_REGISTER" + +#: elf64-sparc.c:459 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "Register %%g%d digunakan tidak kompatibel: %s dalam %B, sebelumnya %s dalam %B" + +#: elf64-sparc.c:482 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Simbol `%s' memiliki tipe berbeda: REGISTER dalam %B, sebelumnya %s dalam %B" + +#: elf64-sparc.c:527 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Simbol `%s' memiliki tipe berbeda: %s dalam %B, sebelumnya REGISTER dalam %B" + +#: elf64-sparc.c:679 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: menghubungkan UltraSPARC spesifik dengan HAL spesifik kode" + +#: elf64-x86-64.c:1337 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: '%s' keduanya diakses secara normal dan thread simbol lokal" + +#: elf64-x86-64.c:2701 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: relokasi %s terhadap STT_GNU_IFUNC simbol `%s' memiliki addend bukan-nol: %d" + +#: elf64-x86-64.c:2980 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: relokasi R_X86_64_GOTOFF64 terhadap fungsi terproteksi `%s' tidak dapat digunakan ketika membuat sebuah objek terbagi" + +#: elf64-x86-64.c:3091 +msgid "; recompile with -fPIC" +msgstr "; rekompile dengan -fPIC" + +#: elf64-x86-64.c:3096 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: relokasi %s terhadap %s `%s' tidak dapat digunakan ketika membuat sebuah objek terbagi%s" + +#: elf64-x86-64.c:3098 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: relokasi %s terhadap tidak terdefinisi %s `%s' tidak dapat digunakan ketika membuat sebuah objek terbagi %s" + +#: elfcode.h:795 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "peringatan: %s memiliki sebuah string tabel korup index - diabaikan" + +#: elfcode.h:1201 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: versi terhitung (%ld) tidak cocok dengan simbol terhitung (%ld)" + +#: elfcode.h:1441 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): relokasi %d memiliki indek simbol tidak valid %ld" + +#: elfcore.h:251 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Peringatan: %B terpotong: diperkirakan ukuran berkas core >= %lu, ditemukan: %lu." + +#: elflink.c:1113 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS definisi dalam %B bagian %A tidak cocok bukan-TLS definisi dalam %B bagian %A" + +#: elflink.c:1117 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: TLS referensi dalam %B tidak cocok bukan-TLS referensi dalam %B" + +#: elflink.c:1121 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: TLS definisi dalam %B bagian %A tidak cocok bukan-TLS referensi dalam %B" + +#: elflink.c:1125 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS referensi dalam %B tidak cocok bukan-TLS definisi dalam %B bagian %A" + +#: elflink.c:1764 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: tidak diduga redefinisi dari indirek versioned simbol `%s'" + +#: elflink.c:2077 +msgid "%B: version node not found for symbol %s" +msgstr "%B: titik versi tidak ditemukan untuk simbol %s" + +#: elflink.c:2167 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: bad relokasi simbol indeks (0x%lx >= 0x%lx) untuk ofset 0x%lx dalam daerah `%A'" + +#: elflink.c:2178 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: bukan-nol simbol indeks (0x%lx) untuk offset 0x%lx dalam bagian `%A' ketika berkas objek tidak memiliki tabel simbol" + +#: elflink.c:2375 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: ukuran relokasi tidak cocok dalam %B bagian %A" + +#: elflink.c:2678 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "peringatan: tipe dan ukuran dari simbol dinamis `%s' tidak terdefinisi" + +#: elflink.c:3424 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: kode mesin alternatif untuk ELF ditemukan (%d) dalam %B, diduga %d\n" + +#: elflink.c:4032 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: versi %u tidak valid (max %d)" + +#: elflink.c:4068 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: tidak valid dibutuhkan versi %d" + +#: elflink.c:4253 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Peringatan: alignmen %u dari simbol umum `%s' dalam %B adalah lebih besar daripada alignment (%u) dari bagian ini %A" + +#: elflink.c:4259 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Peringatan: alignment %u dari simbol `%s' dalam %B adalah lebih kecil daripada %u dalam %B" + +#: elflink.c:4274 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Peringatan: ukuran dari simbol `%s' berubah dari %lu dalam %B ke %lu dalam %B" + +#: elflink.c:4438 +#, c-format +msgid "%s: invalid DSO for symbol `%s' definition" +msgstr "%s: tidak valid DSO untuk simbol `%s' definisi" + +#: elflink.c:5688 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: versi tidak terdefinisi: %s" + +#: elflink.c:5756 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: .preinit_array bagian tidak diperbolehkan dalam DSO" + +#: elflink.c:7484 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "undefined %s referensi dalam simbol kompleks: %s" + +#: elflink.c:7638 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "operator tidak diketahui '%c' dalam simbol kompleks" + +#: elflink.c:7976 elflink.c:7993 elflink.c:8030 elflink.c:8047 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Tidak dapat mengurutkan relokasi - mereka berada dalam lebih dari satu ukuran" + +#: elflink.c:8007 elflink.c:8061 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Tidak dapat mengurutkan relokasi - mereka dari ukuran yang tidak diketahui" + +#: elflink.c:8112 +msgid "Not enough memory to sort relocations" +msgstr "Tidak cukup memori untuk mengurutkan relokasi" + +#: elflink.c:8304 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Terlalu banyak bagian: %d (>= %d)" + +#: elflink.c:8540 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: %s simbol `%s' dalam %B adalah direferensikan oleh DSO" + +#: elflink.c:8625 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: tidak dapat menemukan bagian keluaran %A untuk daerah masukan %A" + +#: elflink.c:8745 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: %s simbol `%s' tidak didefinisikan" + +#: elflink.c:9301 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "error: %B berisi sebuah relokasi (0x%s) untuk daerah %A yang mereferensikan sebuah bukan-exist simbol global" + +#: elflink.c:9366 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X`%s' direferensikan dalam daerah `%A' dari %B: didefinisikan dalam daerah diabaikan `%A' dari %B\n" + +#: elflink.c:9991 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A memiliki keduanya terurut [`%A' dalam %B] dan daerah tidak terurut [`%A' dalam %B]" + +#: elflink.c:9996 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A memiliki daerah terurut dan tidak terurut" + +#: elflink.c:10872 elflink.c:10916 +msgid "%B: could not find output section %s" +msgstr "%B: tidak dapat menemukan daerah keluaran %s" + +#: elflink.c:10877 +#, c-format +msgid "warning: %s section has zero size" +msgstr "peringatan: %s daerah memiliki ukuran nol" + +#: elflink.c:10982 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: peringatan: membuat sebuah DT_TEXTREL dalam sebuah objek terbagi.\n" + +#: elflink.c:11165 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: tidak dapat membaca simbol: %E\n" + +#: elflink.c:11483 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Menghapus daerah tidak digunakan '%s' dalam berkas '%B'" + +#: elflink.c:11695 +msgid "Warning: gc-sections option ignored" +msgstr "Peringatan: gc-sections pilihan diabaikan" + +#: elflink.c:12242 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: peringatan daerah duplikasi `%A'" + +#: elflink.c:12249 elflink.c:12256 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: daerah duplikasi `%A' memiliki ukuran berbeda" + +#: elflink.c:12264 elflink.c:12269 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: peringatan: tidak dapat membaca isi dari daerah `%A'" + +#: elflink.c:12273 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: peringatan: duplikasi daerah `%A' memiliki isi berbeda" + +#: elflink.c:12374 linker.c:3098 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1222 +msgid "static procedure (no name)" +msgstr "prosedur statis (tidak bernama)" + +#: elfxx-mips.c:5588 +msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +msgstr "%B: %A+0x%lx: lompat ke routine stub dimana bukan jal" + +#: elfxx-mips.c:6235 elfxx-mips.c:6458 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Peringatan: pilihan `%s' buruk ukuran %u lebih kecil dari headernya" + +#: elfxx-mips.c:7205 elfxx-mips.c:7330 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Peringatan: tidak dapat menentukan fungsi terget untuk daerah stub `%s'" + +#: elfxx-mips.c:7459 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Malformed relokasi terdeteksi untuk daerah %s" + +#: elfxx-mips.c:7499 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: GOT relokasi di 0x%lx tidak diduga dalam aplikasi" + +#: elfxx-mips.c:7602 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL16 relokasi di 0x%lx tidak terhadap simbol global" + +#: elfxx-mips.c:8280 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "bukan-dinamis relokasi refer ke simbol dinamis %s" + +#: elfxx-mips.c:8985 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Tidak dapat menemukan cocok LO16 relokasi terhadap `%s' untuk %s di 0x%lx di daerah `%A'" + +#: elfxx-mips.c:9124 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "daerah data-kecil melebihi 64KB; dibawah data-kecil batas ukuran (lihat pilihan -G)" + +#: elfxx-mips.c:11940 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: nama daerah `%s' ilegal" + +#: elfxx-mips.c:12318 elfxx-mips.c:12344 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Peringatan: %B menggunakan 0msingle-float, %B menggunakan -mdouble-float" + +#: elfxx-mips.c:12330 elfxx-mips.c:12386 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Peringatan: %B menggunakan -msingle-float, %B menggunakan -mips32r2 -mfp64" + +#: elfxx-mips.c:12356 elfxx-mips.c:12392 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Peringatan: %B menggunakan -mdouble-float, %B menggunakan -mips32r2 -mfp64" + +#: elfxx-mips.c:12434 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: endianness tidak kompatibel dengan yang dipilih di emulasi" + +#: elfxx-mips.c:12445 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI tidak kompatibel dengan yang dipilih di emulasi" + +#: elfxx-mips.c:12526 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: peringatan: menghubungkan berkas abicalls dengan berkas bukan-abicalls" + +#: elfxx-mips.c:12543 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: menghubungkan 32-bit kode dengan 64-bit kode" + +#: elfxx-mips.c:12571 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: menghubungkan %s modul dengan modul %s sebelumnya" + +#: elfxx-mips.c:12594 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: ABI tidak cocok: menghubungkan modul %s dengan modul %s sebelumnya" + +#: elfxx-mips.c:12758 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=032]" + +#: elfxx-mips.c:12760 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=064]" + +#: elfxx-mips.c:12762 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12764 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12766 +#, c-format +msgid " [abi unknown]" +msgstr " [abi tidak diketahui]" + +#: elfxx-mips.c:12768 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12770 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12772 +#, c-format +msgid " [no abi set]" +msgstr " [bukan abi set]" + +#: elfxx-mips.c:12793 +#, c-format +msgid " [unknown ISA]" +msgstr " [ISA tidak diketahui]" + +#: elfxx-mips.c:12804 +#, c-format +msgid " [not 32bitmode]" +msgstr " [bukan 32bitmode]" + +#: elfxx-sparc.c:440 +#, c-format +msgid "invalid relocation type %d" +msgstr "tipe relokasi %d tidak valid" + +#: i386linux.c:455 m68klinux.c:459 sparclinux.c:453 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Berkas keluaran membutuhkan library terbagi `%s'\n" + +#: i386linux.c:463 m68klinux.c:467 sparclinux.c:461 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Berkas keluaran membutuhkan library terbagi `%s.so.%s'\n" + +#: i386linux.c:652 i386linux.c:702 m68klinux.c:659 m68klinux.c:707 +#: sparclinux.c:651 sparclinux.c:701 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Simbol %s tidak terdefinisi untuk fixups\n" + +#: i386linux.c:726 m68klinux.c:731 sparclinux.c:725 +msgid "Warning: fixup count mismatch\n" +msgstr "Peringatan: jumlah fixup tidak cocok\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: string terlalu panjang (%d chars, max 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: simbol tidak dikenal `%s' flags 0x%x" + +#: ieee.c:788 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: tidak terimplementasi ATI record %u untuk simbol %u" + +#: ieee.c:812 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: tipe ATN %d tidak diduga dalam bagian luar" + +#: ieee.c:834 +msgid "%B: unexpected type after ATN" +msgstr "%B: tidak diduga tipe sesudah ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: tidak diduga karakter `%s' dalam berkas Intel Hex" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: checksum buruk dalam berkas Intel Hex (diperkirakan %u, ditemukan %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: buruk extended alamat panjang record dalam berkas Intel Hex" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: buruk extended awal panjang alamat dalam berkas Intel Hex " + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: buruk extended alamat linear panjang record dalam berkas Intel Hex" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: buruk extended panjang awal alamat linear dalam berkas Intel Hex" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: tidak dikenal ihex tipe %u dalam berkas Intel Hex" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: internal error dalam ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: buruk panjang bagian dalam ihex_read_section" + +#: ihex.c:825 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: alamat 0x%s diluar jangkauan untuk berkas Intel Hex" + +#: libbfd.c:1008 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Deprecated %s dipanggil di %s baris %d dalam %s\n" + +#: libbfd.c:1011 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Deprecated %s dipanggil\n" + +#: linker.c:1874 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: indirect simbol `%s' ke `%s' adalah sebuah loop" + +#: linker.c:2740 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Mencoba untuk merelokasi link dengan masukan %s dan keluaran %s" + +#: linker.c:3065 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: peringatan: mengabaikan bagiann terduplikasi `%A'\n" + +#: linker.c:3079 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: peringatan: bagian terduplikasi `%A' memiliki ukuran berbeda\n" + +#: mach-o.c:3195 +#, c-format +msgid "Mach-O header:\n" +msgstr "Kepala Mach-O:\n" + +#: mach-o.c:3196 +#, c-format +msgid " magic : %08lx\n" +msgstr " majik : %08lx\n" + +#: mach-o.c:3197 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " tipe-cpu : %08lx (%s)\n" + +#: mach-o.c:3199 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " subtipecpu: %08lx\n" + +#: mach-o.c:3200 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " tipe-berkas : %08lx (%s)\n" + +#: mach-o.c:3203 +#, c-format +msgid " ncmds : %08lx\n" +msgstr " ncmds : %08lx\n" + +#: mach-o.c:3204 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " besardariperintah: %08lx\n" + +#: mach-o.c:3205 +#, c-format +msgid " flags : %08lx (" +msgstr " tanda : %08lx (" + +#: mach-o.c:3207 +#, c-format +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3208 +#, c-format +msgid " reserved : %08x\n" +msgstr " direserve : %08x\n" + +#: mach-o.c:3218 +#, c-format +msgid "Segments and Sections:\n" +msgstr "Bagian dan Daerah:\n" + +#: mach-o.c:3219 +#, c-format +msgid " #: Segment name Section name Address\n" +msgstr " #: Nama bagian Nama daerah Alamat\n" + +#: merge.c:829 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: akses diluar dari daerah merged (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Tidak ada core untuk alokasi daerah nama %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Tidak ada core untuk alokasi sebuah simbol %d bytes long\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: berkas mmo tidak valid: nilai inisialisasi untuk $255 bukan `Main'\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: tidak didukung dengan urutan karakter lebar 0x%02X 0x%02X sesudah nama simbol dimulai dengan `%s'\n" + +#: mmo.c:1566 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: berkas mmo tidak valid: lopcode tidak didukung `%d'\n" + +#: mmo.c:1576 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: berka mmo tidak valid: diduga YZ = 1 diperoleh YZ = %d untuk lop_quote\n" + +#: mmo.c:1612 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: berkas mmo tidak valid: diduga z = 1 atau z = 2, diperoleh z = %d untuk lop_loc\n" + +#: mmo.c:1658 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: berkas mmo tidak valid: diduga z = 1 atau z = 2, diperoleh z = %d untuk lop_fixo\n" + +#: mmo.c:1697 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: berkas mmo tidak valid: diduga y = 0, diperoleh y = %d untuk lop_fixrx\n" + +#: mmo.c:1706 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: berkas mmo tidak valid: diduga z = 16 atau z = 24, diperoleh z = %d untuk lop_fixrx\n" + +#: mmo.c:1729 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: berkas mmo tidak valid: awalan byte dari kata operand harus 0 atau 1, diperoleh %d untuk lop_fixrx\n" + +#: mmo.c:1752 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: tidak dapat mengalokasikan nama berkas untuk nomor berkas %d, %d bytes\n" + +#: mmo.c:1772 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: berkas mmo tidak valid: nomor berkas %d `%s', telah dimasukan sebagai `%s'\n" + +#: mmo.c:1785 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: berkas mmo tidak valid: nama berkas untuk nomor %d telah dispesifikasikan sebelum digunakan\n" + +#: mmo.c:1892 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: berkas mmo tidak valid: daerah y dan z dari lop_stab bukan-nol, y: %d, z: %d\n" + +#: mmo.c:1928 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: berkas mmo tidak valid: lop_end bukan item terakhir dalam berkas\n" + +#: mmo.c:1941 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: berkas mmo tidak valid: YZ dari lop_end (%ld) tidak sama dengan jumlah dari tetras yang mengawali lop_stab (%ld)\n" + +#: mmo.c:2651 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: tabel simbol tidak valid: duplikasi simbol `%s'\n" + +#: mmo.c:2894 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Definisi simbol buruk: `Main' di set ke %s daripada ke awal alamat %s\n" + +#: mmo.c:2986 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: Peringatan: tabel simbol terlalu besar untuk mmo, lebih besar daripada 65535 32-bit words: %d. Hanya `Main' yang akan dikeluarkan.\n" + +#: mmo.c:3031 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: internal error, tabel simbol berubah ukuran dari %d ke %d kata\n" + +#: mmo.c:3083 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: internal error, daerah internal register %s memiliki isi\n" + +#: mmo.c:3134 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: tidak ada register yang terinisialisasi; panjang daerah 0\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: terlalu banyak register yang terinisialisasi; panjang daerah %ld\n" + +#: mmo.c:3145 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: awal alaman tidak valid untuk register terinisialisasi dari panjang %ld: 0x%lx%08lx\n" + +#: oasys.c:881 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: tidak dapat merepresentasikan daerah `%s' dalam oasys" + +#: osf-core.c:139 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Tidak tertangani berkas core OSF/1 daerah tipe %d\n" + +#: pe-mips.c:613 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: `ld -r' tidak didukung dengan PE MIPS objek\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:729 +msgid "%B: unimplemented %s\n" +msgstr "%B: tidak terimplementasi %s\n" + +#: pe-mips.c:755 +msgid "%B: jump too far away\n" +msgstr "%B: lompat terlalu jauh\n" + +#: pe-mips.c:781 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: pasangan/reflo buruk setelah refhi\n" + +#: pei-x86_64.c:465 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "peringatan: besar (%ld) daerah .pdata tidak dalam kelipatan dari %d\n" + +#: pei-x86_64.c:469 peigen.c:1620 peigen.c:1799 pepigen.c:1620 pepigen.c:1799 +#: pex64igen.c:1620 pex64igen.c:1799 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Tabel Fungsi (diinterpretasikan isi daerah .pdata)\n" + +#: pei-x86_64.c:471 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr " vma:\t\t\tAlamatAwal \t AlamatAkhir\t UnwindData\n" + +#. XXX code yet to be written. +#: peicode.h:752 +msgid "%B: Unhandled import type; %x" +msgstr "%B: Tipe impor tidak tertangani; %x" + +#: peicode.h:757 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: Tipe impor tidak dikenal; %x" + +#: peicode.h:771 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: Nama tipe impor tidak dikenal; %x" + +#: peicode.h:1154 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: Tipe mesin (0x%x) tidak dikenal dalam Import Library Format archive" + +#: peicode.h:1166 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: Dikenal tetapi tidak tertangani tipe mesin (0x%x) dalam Import Library Format archive" + +#: peicode.h:1184 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: besar field adalah nol dalam Import Library Format header" + +#: peicode.h:1215 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: string tidak diakhiri kosong dalam berkas objek ILF." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot header:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Ofset masukan = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Panjang = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Tanda daerah = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Nama partisi = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Awal partisi[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Akhir partisi[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Daerah partisi[%d] = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Panjang partisi[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5114 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Tambahan exec header\n" + +#: som.c:5417 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers tidak terimplementasi" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: Karakter `%s' tidak diduga dalam berkas S-record\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: Checksum buruk dalam berkas S-record\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Masukan stabs memiliki index string tidak valid." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "Relokasi .stab tidak didukung" + +#: vms-gsd.c:350 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) gagal" + +#: vms-gsd.c:365 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) gagal" + +#: vms-gsd.c:399 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Ukuran tidak cocok daerah %s=%lx, %s=%lx" + +#: vms-gsd.c:754 +#, c-format +msgid "Unknown GSD/EGSD subtype %d" +msgstr "tidak diketahui GDS/EGSD subtype %d" + +#: vms-hdr.c:364 +msgid "Object module NOT error-free !\n" +msgstr "Modul objek Tidak bebas-error !\n" + +#: vms-hdr.c:878 +#, c-format +msgid "unknown source command %d" +msgstr "sumber perintah %d tidak diketahui" + +#: vms-hdr.c:951 +msgid "DST_S_C_SET_LINUM_INCR not implemented" +msgstr "DST_S_C_SET_LINUM_INCR belum diimplementasikan" + +#: vms-hdr.c:957 +msgid "DST_S_C_SET_LINUM_INCR_W not implemented" +msgstr "DST_S_C_SET_LINUM_INCR_W belum diimplementasikan" + +#: vms-hdr.c:963 +msgid "DST_S_C_RESET_LINUM_INCR not implemented" +msgstr "DST_S_C_RESET_LINUM_INCR belum diimplementasikan" + +#: vms-hdr.c:969 +msgid "DST_S_C_BEG_STMT_MODE not implemented" +msgstr "DST_S_C_BEG_STMT_MODE belum diimplementasikan" + +#: vms-hdr.c:975 +msgid "DST_S_C_END_STMT_MODE not implemented" +msgstr "DST_S_C_END_STMT_MODE belum diimplementasikan" + +#: vms-hdr.c:1008 +msgid "DST_S_C_SET_PC not implemented" +msgstr "DST_S_C_SET_PC belum diimplementasikan" + +#: vms-hdr.c:1014 +msgid "DST_S_C_SET_PC_W not implemented" +msgstr "DST_S_C_SET_PC_W belum diimplementasikan" + +#: vms-hdr.c:1020 +msgid "DST_S_C_SET_PC_L not implemented" +msgstr "DST_S_C_SET_PC_L belum diimplementasikan" + +#: vms-hdr.c:1026 +msgid "DST_S_C_SET_STMTNUM not implemented" +msgstr "DST_S_C_SET_STMTNUM belum diimplementasikan" + +#: vms-hdr.c:1079 +#, c-format +msgid "unknown line command %d" +msgstr "baris perintah %d tidak diketahui" + +#: vms-misc.c:588 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Stack overflow (%d) dalam _bfd_vms_push" + +#: vms-misc.c:603 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Stack underflow dalam _bfd_vms_pop" + +#: vms-misc.c:844 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted dipanggil dengan zero bytes" + +#: vms-misc.c:849 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted dipanggil dengan terlalu banyak bytes" + +#: vms-misc.c:967 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Simbol %s digantikan oleh %s\n" + +#: vms-misc.c:1026 +#, c-format +msgid "failed to enter %s" +msgstr "gagal untuk memasuki %s" + +#: vms-tir.c:83 +msgid "No Mem !" +msgstr "Tidak ada Memori !" + +#. These names have not yet been added to this switch statement. +#: vms-tir.c:346 +#, c-format +msgid "unknown ETIR command %d" +msgstr "perintah ETIR %d tidak diketahui" + +#: vms-tir.c:440 +#, c-format +msgid "bad section index in %s" +msgstr "Indek daerah buruk dalam %s" + +#: vms-tir.c:459 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "perintah %s STA tidak didukung" + +#: vms-tir.c:464 vms-tir.c:1304 +#, c-format +msgid "reserved STA cmd %d" +msgstr "perintah %d STA direserve" + +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:655 vms-tir.c:774 vms-tir.c:894 vms-tir.c:1624 +#, c-format +msgid "%s: not supported" +msgstr "%s: tidak didukung" + +#: vms-tir.c:661 vms-tir.c:1481 +#, c-format +msgid "%s: not implemented" +msgstr "%s: tidak terimplementasi" + +#: vms-tir.c:666 vms-tir.c:1485 +#, c-format +msgid "reserved STO cmd %d" +msgstr "reserved STO perintah %d" + +#: vms-tir.c:789 vms-tir.c:1629 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "reserved OPR perintah %d" + +#: vms-tir.c:852 vms-tir.c:1693 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "reserved CTL perintah %d" + +#: vms-tir.c:966 +#, c-format +msgid "reserved STC cmd %d" +msgstr "perintah %d direserve" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1212 +msgid "stack-from-image not implemented" +msgstr "stack-from-image tidak terimplementasi" + +#: vms-tir.c:1230 +msgid "stack-entry-mask not fully implemented" +msgstr "stack-entry-mask tidak terimplementasi secara penuh" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1244 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH tidak terimplementasi secara penuh" + +#: vms-tir.c:1263 +msgid "stack-local-symbol not fully implemented" +msgstr "stack-local-symbol tidak terimplementasi secara penuh" + +#: vms-tir.c:1276 +msgid "stack-literal not fully implemented" +msgstr "stack-literal tidak terimplementasi secara penuh" + +#: vms-tir.c:1297 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "stack-local-symbol-entry-point-mask tidak terimplementasi secara penuh" + +#: vms-tir.c:1571 vms-tir.c:1583 vms-tir.c:1595 vms-tir.c:1607 vms-tir.c:1672 +#: vms-tir.c:1680 vms-tir.c:1688 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: tidak terimplementasi secara penuh" + +#: vms-tir.c:1746 +#, c-format +msgid "obj code %d not found" +msgstr "obj kode %d tidak ditemukan" + +#: vms-tir.c:2019 +#, c-format +msgid "Reloc size error in section %s" +msgstr "Kesalahan ukuran relokasi dalam daerah %s" + +#: vms-tir.c:2112 vms-tir.c:2129 vms-tir.c:2147 vms-tir.c:2159 vms-tir.c:2170 +#: vms-tir.c:2182 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Relokasi %s + %s tidak diketahui" + +#: vms-tir.c:2249 +#, c-format +msgid "Unknown symbol %s in command %s" +msgstr "Simbol %s tidak diketahui dalam perintah %s" + +#: vms-tir.c:2504 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC dengan tidak ada relokasi dalam daerah %s" + +#: vms-tir.c:2556 vms-tir.c:2783 +#, c-format +msgid "Size error in section %s" +msgstr "Kesalahan ukuran dalam daerah %s" + +#: vms-tir.c:2725 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Spurious ALPHA_R_BSR relokasi" + +#: vms-tir.c:2770 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Relokasi %s tidak tertangani" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF objek shared ketika tidak menghasilkan keluaran XCOFF" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: objek dinamis dengan tidak ada daerah .loader" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: `%s' memiliki nomor baris tetapi tidak ditutupi daerah" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: kelas %d simbol `%s' tidak memiliki tambahan masukan" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: simbol `%s' memiliki tipe %d csect tidak dikenal" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: simbol XTY_ER buruk `%s': kelas %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: XMC_TC0 simbol `%s' adalah kelas %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect `%s' tidak dalam lingkup daerah" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: salah tempat XTY_LD `%s'" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: relokasi %s:%d tidak dalam csect" + +#: xcofflink.c:3177 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: tidak ada simbol seperti itu" + +#: xcofflink.c:3282 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "peringatan: mencoba untuk mengekspor simbol tidak terdefinisi `%s'" + +#: xcofflink.c:3664 +msgid "error: undefined symbol __rtinit" +msgstr "error: simbol tidak terdefinisi __rtinit" + +#: xcofflink.c:4041 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: loader relokasi dalam daerah tidak dikenal `%s'" + +#: xcofflink.c:4052 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: `%s' dalam relokasi loader tetapi bukan loader sym" + +#: xcofflink.c:4068 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: loader relokasi dalam daerah baca-saja %A" + +#: xcofflink.c:5086 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "TOC overflow: 0x%lx > 0x10000; coba -mminimal-toc ketika mengkompile" + +#: elf32-ia64.c:1050 elf64-ia64.c:1050 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Tidak dapat relaks br di 0x%lx dalam daerah `%A'. Tolong gunakan brl atau indirect branch." + +#: elf32-ia64.c:2739 elf64-ia64.c:2739 +msgid "@pltoff reloc against local symbol" +msgstr "@pltoff relokasi terhadap simbol lokal" + +#: elf32-ia64.c:4314 elf64-ia64.c:4314 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: short data segment overflowed (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4325 elf64-ia64.c:4325 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp tidak meliputi segmen data pendek" + +#: elf32-ia64.c:4595 elf64-ia64.c:4595 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: bukan-pic kode dengan relokasi imm terhadap simbol dinamis `%s'" + +#: elf32-ia64.c:4662 elf64-ia64.c:4662 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: @gprel relokasi terhadap simbol dinamis %s" + +#: elf32-ia64.c:4725 elf64-ia64.c:4725 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: menghubungkan dengan kode bukan-pic dalam sebuah executable bebas posisi" + +#: elf32-ia64.c:4862 elf64-ia64.c:4862 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: @internal branck ke simbol dinamis %s" + +#: elf32-ia64.c:4864 elf64-ia64.c:4864 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: spekulasi fixup ke simbol dinamis %s" + +#: elf32-ia64.c:4866 elf64-ia64.c:4866 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: @pcrel relokasi terhadap simbol dinamis %s" + +#: elf32-ia64.c:5063 elf64-ia64.c:5063 +msgid "unsupported reloc" +msgstr "relokasi tidak didukung" + +#: elf32-ia64.c:5101 elf64-ia64.c:5101 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: hilang daerah TLS untuk relokasi %s terhadap `%s' di 0x%lx dalam daerah `%A'." + +#: elf32-ia64.c:5116 elf64-ia64.c:5116 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: Tidak dapat relaks br (%s) ke `%s' di 0x%lx dalam daerah `%A' dengan ukuran 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5372 elf64-ia64.c:5372 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: menghubungkan trap-on-NULL-dereference dengan berkas bukan-trapping" + +#: elf32-ia64.c:5381 elf64-ia64.c:5381 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: menghubungkan berkas big-endian dengan berkas little-endian" + +#: elf32-ia64.c:5390 elf64-ia64.c:5390 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: menghubungkan berkas 64-bit dengan berkas 32-bit" + +#: elf32-ia64.c:5399 elf64-ia64.c:5399 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: menghubungkan berkas constant-gp dengan berkas bukan-constant-gp" + +#: elf32-ia64.c:5409 elf64-ia64.c:5409 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: menghubungkan berkas auto-pic dengan berkas non-auto-pic" + +#: peigen.c:999 pepigen.c:999 pex64igen.c:999 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: nomor baris overflow: 0x%lx > 0xffff" + +#: peigen.c:1026 pepigen.c:1026 pex64igen.c:1026 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Direktori expor [.edata (atau dimanapun kita menemukannya)]" + +#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027 +msgid "Import Directory [parts of .idata]" +msgstr "Impor Direktori [bagian dari .idata]" + +#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028 +msgid "Resource Directory [.rsrc]" +msgstr "Resource Direktori [.rsrc]" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Exception Directory [.pdata]" +msgstr "Exception Direktori [.pdata]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Security Directory" +msgstr "Direktori Keamanan" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Base Relocation Directory [.reloc]" +msgstr "Dasar Relokasi Direktori [.reloc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Debug Directory" +msgstr "Debug Direktori" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Description Directory" +msgstr "Direktori Penjelasan" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Special Directory" +msgstr "Direktori Spesial" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Thread Storage Directory [.tls]" +msgstr "Thread Storage Direktori [.tls]" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Load Configuration Directory" +msgstr "Direktori Konfigurasi Beban" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Bound Import Directory" +msgstr "Direktori Bound Impor" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Import Address Table Directory" +msgstr "Direktori Impor Tabel Alamat" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Delay Import Directory" +msgstr "Delay Impor Direktori" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "CLR Runtime Header" +msgstr "CLR Runtime Header" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Reserved" +msgstr "Reserved" + +#: peigen.c:1101 pepigen.c:1101 pex64igen.c:1101 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Ada tabel impor, tetapi daerah yang berisi itu tidak dapat ditemukan\n" + +#: peigen.c:1106 pepigen.c:1106 pex64igen.c:1106 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Ada impor tabel di %s pada 0x%lx\n" + +#: peigen.c:1149 pepigen.c:1149 pex64igen.c:1149 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Deskripsi fungsi ditempatkan di awal alamat: %04lx\n" + +#: peigen.c:1152 pepigen.c:1152 pex64igen.c:1152 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" + +#: peigen.c:1160 pepigen.c:1160 pex64igen.c:1160 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Tidak ada daerah reldata! Deskripsi fungsi tidak terdekode.\n" + +#: peigen.c:1165 pepigen.c:1165 pex64igen.c:1165 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Tabel Impor (diinterpretasikan isi daerah %s)\n" + +#: peigen.c:1168 pepigen.c:1168 pex64igen.c:1168 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +"vma: Tips Waktu Forward DLL Pertama\n" +" Tabel Stamp Rantai Nama Thunk\n" + +#: peigen.c:1216 pepigen.c:1216 pex64igen.c:1216 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tNama DLL: %s\n" + +#: peigen.c:1227 pepigen.c:1227 pex64igen.c:1227 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Tips/Ord Nama-Anggota Terikat-Ke\n" + +#: peigen.c:1252 pepigen.c:1252 pex64igen.c:1252 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Ada thunk pertama, tetapi daerah yang berisi itu tidak dapat ditemukan\n" + +#: peigen.c:1417 pepigen.c:1417 pex64igen.c:1417 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Ada tabel expor, tetapi daerah yang berisi itu tidak dapat ditemukan\n" + +#: peigen.c:1426 pepigen.c:1426 pex64igen.c:1426 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Ada tabel expor dalam %s, tetapi ini tidak masuk dalam daerah itu\n" + +#: peigen.c:1432 pepigen.c:1432 pex64igen.c:1432 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Ada sebuah tabel expor dalam %s di 0x%lx\n" + +#: peigen.c:1460 pepigen.c:1460 pex64igen.c:1460 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Tabel expor (diinterpretasikan isi daerah %s)\n" + +#: peigen.c:1464 pepigen.c:1464 pex64igen.c:1464 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Tanda Expor \t\t\t%lx\n" + +#: peigen.c:1467 pepigen.c:1467 pex64igen.c:1467 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Waktu/Tanggal stamp \t\t%lx\n" + +#: peigen.c:1470 pepigen.c:1470 pex64igen.c:1470 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Mayor/Minor \t\t\t%d/%d\n" + +#: peigen.c:1473 pepigen.c:1473 pex64igen.c:1473 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Nama \t\t\t\t" + +#: peigen.c:1479 pepigen.c:1479 pex64igen.c:1479 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Dasar Ordinal \t\t\t%ld\n" + +#: peigen.c:1482 pepigen.c:1482 pex64igen.c:1482 +#, c-format +msgid "Number in:\n" +msgstr "Nomor dalam:\n" + +#: peigen.c:1485 pepigen.c:1485 pex64igen.c:1485 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tTabel Alamat Expor \t\t%08lx\n" + +#: peigen.c:1489 pepigen.c:1489 pex64igen.c:1489 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Nama Pointer/Ordinal] Tabel\t%08lx\n" + +#: peigen.c:1492 pepigen.c:1492 pex64igen.c:1492 +#, c-format +msgid "Table Addresses\n" +msgstr "Tabel Alamat\n" + +#: peigen.c:1495 pepigen.c:1495 pex64igen.c:1495 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tTabel Alamat Expor \t\t" + +#: peigen.c:1500 pepigen.c:1500 pex64igen.c:1500 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tTabel Nama Pointer \t\t" + +#: peigen.c:1505 pepigen.c:1505 pex64igen.c:1505 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tTabel Ordinal \t\t\t" + +#: peigen.c:1519 pepigen.c:1519 pex64igen.c:1519 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Tabel Alamat Expor -- Ordinal Base %ld\n" + +#: peigen.c:1538 pepigen.c:1538 pex64igen.c:1538 +msgid "Forwarder RVA" +msgstr "Forwarder RVA" + +#: peigen.c:1549 pepigen.c:1549 pex64igen.c:1549 +msgid "Export RVA" +msgstr "Expor RVA" + +#: peigen.c:1556 pepigen.c:1556 pex64igen.c:1556 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Ordinal/Nama Pointer] Tabel\n" + +#: peigen.c:1616 peigen.c:1795 pepigen.c:1616 pepigen.c:1795 pex64igen.c:1616 +#: pex64igen.c:1795 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Peringatan, besar (%ld) daerah .pdata tidak dalam kelipatan dari %d\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tAwal Alamat Akhir Alamat Unwind Informasi\n" + +#: peigen.c:1625 pepigen.c:1625 pex64igen.c:1625 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tAwal Akhir EH EH PrologEnd Exception\n" +" \t\tAlamat Alamat Handler Data Alamat Topeng\n" + +#: peigen.c:1695 pepigen.c:1695 pex64igen.c:1695 +#, c-format +msgid " Register save millicode" +msgstr " Register simpan millicode" + +#: peigen.c:1698 pepigen.c:1698 pex64igen.c:1698 +#, c-format +msgid " Register restore millicode" +msgstr " Register restore millicode" + +#: peigen.c:1701 pepigen.c:1701 pex64igen.c:1701 +#, c-format +msgid " Glue code sequence" +msgstr " Urutan kode pengikat" + +#: peigen.c:1801 pepigen.c:1801 pex64igen.c:1801 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tMulai Prolog Fungsi Flags Exception EH\n" +" \t\tAlamat Panjang Panjang 32b exc Handler Data\n" + +#: peigen.c:1933 pepigen.c:1933 pex64igen.c:1933 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Berkas Dasar Relokasi PE (diinterpretasikan isi daerah .reloc)\n" + +#: peigen.c:1963 pepigen.c:1963 pex64igen.c:1963 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Alamat Maya: %08lx Besar potongan %ld (0x%lx) Jumlah dari perbaikan %ld\n" + +#: peigen.c:1976 pepigen.c:1976 pex64igen.c:1976 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\trelokasi %4d ofset %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2015 pepigen.c:2015 pex64igen.c:2015 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Karakteristik 0x%x\n" + +#: peigen.c:2292 pepigen.c:2292 pex64igen.c:2292 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: tidak dapat mengisi dalam DataDictionary[1] karena .idata$2 hilang" + +#: peigen.c:2312 pepigen.c:2312 pex64igen.c:2312 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: tidak dapat mengisi dalam DataDictionary[1] karena .data$4 hilang" + +#: peigen.c:2333 pepigen.c:2333 pex64igen.c:2333 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: tidak dapat mengisi dalam DataDictionary[12] karena .idata$5 hilang" + +#: peigen.c:2353 pepigen.c:2353 pex64igen.c:2353 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: tidak dapat mengisi dalam DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] karena .idata$6 hilang" + +#: peigen.c:2375 pepigen.c:2375 pex64igen.c:2375 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: tidak dapat mengisi dalam DataDictionary[9] karena __tls_used hilang" + +#~ msgid "ERROR: %B: Incompatible object tag '%s':%d" +#~ msgstr "ERROR: %B: Tanda objek tidak kompatibel '%s':%d" + +#~ msgid "%B(%A): warning: unresolvable relocation against symbol `%s'" +#~ msgstr "%B(%A): peringatan: tidak teresolf relokasi terhadap simbol `%s'" + +#~ msgid "%B: Internal inconsistency; no relocation section %s" +#~ msgstr "%B: Internal tidak konsisten; bagian %s tidak bisa direlokasi" + +#~ msgid "Could not find relocation section for %s" +#~ msgstr "Tidak dapat menemukan bagian relokasi untuk %s" + +#~ msgid "%B: GOT overflow: Number of R_68K_GOT8O and R_68K_GOT16O relocations > %d" +#~ msgstr "%B: Memperoleh overflow: Jumlah dari R_68K_GOT80 dan R_68K_GOT160 relokasi > %d" + +#~ msgid "%A link_order not found\n" +#~ msgstr "%A link_order tidak ditemukan\n" + +#~ msgid "%s: no symbol \"%s\"" +#~ msgstr "%s: tidak ada simbol \"%s\"" + +#~ msgid "%s: loader reloc in unrecognized section `%s'" +#~ msgstr "%s: loader relokasi dalam daerah `%s' tidak dikenal" + +#~ msgid "%s: `%s' in loader reloc but not loader sym" +#~ msgstr "%s: `%s' dalam relokasi loader tetapi bukan loader sym" diff --git a/external/gpl3/gdb/dist/bfd/po/ja.gmo b/external/gpl3/gdb/dist/bfd/po/ja.gmo new file mode 100644 index 0000000000000000000000000000000000000000..d887a711e263709d8ffe61a1b76e5cf484232d88 GIT binary patch literal 52923 zcmd^|d7PEindjfwSsIeKC2@&~z8XqEsbW*3rKrVDWD^QEB*m?&TgBC?x|Oyzg0`^PJ~-&U4Ot>L1U3|7MTh?)Q1#r@-qz>UrZ&^SnDhDNj9b#AiJ3 zJa8mkBMg13N@-Zq#+u%s> z*WgU>!r>--Hz?uF;3vSJfzsZ81t)`Nj4<`91ttFs_;K()Q0VtK_%ZM`@B;8VptQFi z{2(ZW%KHz2621VG_m|k`*Mesfo?~&b#V=Uww)hBmI`MXcL%^3ny3RXn@jKv9!aufn z)Z#m!)c4;&y2v{NB0?%}JScR%9XuCo0U^D&3j8$qEOh(pCrg^(TDfhpC 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zb9DEXWokeu3O~GHY-CwSDT%dd?q#tB_U97k9zYtcptKxbNf&+?$9^{g6r) zw=rTPdmvSkI(nPq_@nEo$Tg&1!9r>{P@)I)YrmRpm$Jl#MUB%%4*@ZxvSvjTc<*otve&x$9XBiW)iax7DY+ zqKX^NF=Voqk#r85w~VRpO5MpBn4B}~2d00Nvg+zp;<`T!5UiB;>0v^VKM+v-M*mQN z>lGN4<`;hGCr=0UnO|Uc7X00S$SDL{)nqc$emo_sRYI2XnU>2-)L%Dt6lSaW%9tUu zH&Q@BHw9Cqt|R&9yTyQw8c;8>^wnkNttE5M|r8=dC+;C;EyHPevMj4*i$G|T`7Z={4vyA$4)RK zU|mHPiVuc=FTr{XN^i~>tVZyJseRiC^>O26r?;E$X1SJM80KD z;&V9;vVJGb=Y)hStl1!2T&8~f9ShuM#&=qV83JY+K%%K4EM}VEk8`|7CD^}JV1=@r zH~AiATvYX3&qj68;G5c$>&8?pJdY1%D=FFwsihuHW(N4VPA;PoW6=H)ktkzxoPd~3 zVzjcKirpCOx^T0+B61W}LgppUQ%0lt(<)M< zqDKRsL0C|P*>8%eP`(d~t*&rcpy?aD&e36*}M<-Krai_VDBdpvo z{(y2xy+{M}kGIgZ&KP5_nAn3S-Z&Vl&yuUb&diY2Z3q+`ff*R_ItLZg&mWFLUyBL7`^4?qso<@&zQ4 z^{;}a1q>NfrZ|osiyC#aMK;8^CIqRXf1a{=u zXo}lQj1)Uw5m?S6tbcAMh{W=l{?VD>K|EFersvrfYrMe>1?TQ5Adc|QP%r45;P1+a zBvelp3-!@IO;hkZ{PQ%0FTy`j6MMs-so@0bV+US40k6v7jc?Xa4%l02vB|i~!Y+_; zQu64~$U!P^ij&SA_@Mtv_esl7IDFBJ+@~f%e{0dF0q`uycHuH+llj{`xl*=*{Ubf4-#OQre41H&Y?X7R;;>^U289RY zrVGoBp|XR{Ri~i(RK$FoY+bGHZvmlNPvBy8--m?*!BN$?ZE@+n5;$~9$qQ!)xths| g7`{<3y4=6c7e8, 2001 +# Yasuaki Taniguchi , 2010. +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2010-11-23 22:18+0900\n" +"Last-Translator: Yasuaki Taniguchi \n" +"Language-Team: Japanese \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nulurals=1; plural=0;\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: a.out.adobe ファイルã«ä¸æ˜Žãªã‚»ã‚¯ã‚·ãƒ§ãƒ³åž‹ãŒã‚ã‚Šã¾ã™: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: エクスãƒãƒ¼ãƒˆã•ã‚ŒãŸå†é…置型ãŒç„¡åŠ¹ã§ã™: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: インãƒãƒ¼ãƒˆã•ã‚ŒãŸå†é…置型ãŒç„¡åŠ¹ã§ã™: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: インãƒãƒ¼ãƒˆã•ã‚ŒãŸå†é…置レコードãŒèª¤ã£ã¦ã„ã¾ã™: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: a.out オブジェクトファイル形å¼ã§ã¯ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' を表ç¾ã§ãã¾ã›ã‚“" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: a.out オブジェクトファイル形å¼ã§ã¯ã‚·ãƒ³ãƒœãƒ« `%s' 用ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’表ç¾ã§ãã¾ã›ã‚“" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*ä¸æ˜Ž*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: 予期ã—ãªã„å†é…置タイプã§ã™\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: %s ã‹ã‚‰ %s ã¸ã®å†é…ç½®å¯èƒ½ãƒªãƒ³ã‚¯ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "警告: 書庫ã¸ã®æ›¸ãè¾¼ã¿ãŒé…ã‚Œã¾ã—ãŸ: タイムスタンプを書ãæ›ãˆã¾ã™\n" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "書庫ファイルã®æ›´æ–°æ—¥æ™‚を読ã¿è¾¼ã‚“ã§ã„ã¾ã™" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "æ›´æ–°ã•ã‚ŒãŸ armap 日時を書ãè¾¼ã¿ä¸­ã§ã™" + +#: bfd.c:395 +msgid "No error" +msgstr "エラーã¯ã‚ã‚Šã¾ã›ã‚“" + +#: bfd.c:396 +msgid "System call error" +msgstr "システムコールエラー" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "無効㪠bfd ターゲットã§ã™" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "誤ã£ãŸå½¢å¼ã®ãƒ•ã‚¡ã‚¤ãƒ«ã§ã™" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "誤ã£ãŸå½¢å¼ã®ã‚ªãƒ–ジェクトファイル書庫ã§ã™" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "無効ãªæ“作ã§ã™" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "メモリを使ã„æžœãŸã—ã¾ã—ãŸ" + +#: bfd.c:402 +msgid "No symbols" +msgstr "シンボルãŒã‚ã‚Šã¾ã›ã‚“" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "書庫ã«ç´¢å¼•ãŒã‚ã‚Šã¾ã›ã‚“。追加ã™ã‚‹ãŸã‚ã« ranlib を実行ã—ã¦ãã ã•ã„" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "ã“れ以上書庫ファイルã¯ã‚ã‚Šã¾ã›ã‚“" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "ä¸æ­£ãªå½¢å¼ã®æ›¸åº«ã§ã™" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "ファイル形å¼ãŒèªè­˜ã§ãã¾ã›ã‚“" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "ファイル形å¼ãŒæ›–昧ã§ã™" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "セクションã«å†…容ãŒã‚ã‚Šã¾ã›ã‚“" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "出力ã«å¯¾å¿œã™ã‚‹ã‚»ã‚¯ã‚·ãƒ§ãƒ³ãŒã‚ã‚Šã¾ã›ã‚“" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "存在ã—ã¦ã„ãªã„デãƒãƒƒã‚°ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’シンボルãŒå¿…è¦ã¨ã—ã¦ã„ã¾ã™" + +#: bfd.c:411 +msgid "Bad value" +msgstr "ä¸æ­£ãªå€¤ã§ã™" + +#: bfd.c:412 +msgid "File truncated" +msgstr "ファイルãŒé€”切れã¦ã„ã¾ã™" + +#: bfd.c:413 +msgid "File too big" +msgstr "ファイルãŒå¤§ãã™ãŽã¾ã™" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "%s を読ã¿è¾¼ã¿ä¸­ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºç”Ÿã—ã¾ã—ãŸ: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#<ä¸é©åˆ‡ãªã‚¨ãƒ©ãƒ¼ã‚³ãƒ¼ãƒ‰>" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s アサーション失敗 %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %1$s 内部エラー。 %4$s 内 %3$d è¡Œ %2$s ã§ä¸­æ­¢ã—ã¾ã—ãŸ\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %1$s 内部エラー。%3$d è¡Œ %2$s ã§ä¸­æ­¢ã—ã¾ã—ãŸ\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "ã“ã®ãƒã‚°ã‚’報告ã—ã¦ãã ã•ã„。\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "マップã—ã¾ã›ã‚“: データ=%lx マップ済=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "マップã—ã¾ã›ã‚“: 環境変数ãŒè¨­å®šã•ã‚Œã¦ã„ã¾ã›ã‚“\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "警告: セクション `%s' ã§å·¨å¤§ãª (例: è² æ•°) ファイルオフセット 0x%lx ã¸ã®æ›¸ãè¾¼ã¿ã§ã™" + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax ãŠã‚ˆã³ -r ã¯åŒæ™‚ã«ä½¿ç”¨ã§ãã¾ã›ã‚“\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "%B ã‚’å†ã‚ªãƒ¼ãƒ—ンã—ã¦ã„ã¾ã™: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: 圧縮ã•ã‚ŒãŸ Alpha ãƒã‚¤ãƒŠãƒªã‚’扱ã†ã“ã¨ãŒã§ãã¾ã›ã‚“。\n" +" コンパイラã®ãƒ•ãƒ©ã‚°ã¾ãŸã¯ objZ ã§éžåœ§ç¸®ã®ãƒã‚¤ãƒŠãƒªã‚’作æˆã—ã¦ãã ã•ã„。" + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: ä¸æ˜Ž/サãƒãƒ¼ãƒˆã•ã‚Œãªã„å†é…置型 %d ã§ã™" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "GP ãŒæœªå®šç¾©ã®æ™‚ã« GP 関連å†é…ç½®ãŒä½¿ã‚ã‚Œã¾ã—ãŸ" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "複数㮠gp 値を使用ã—ã¦ã„ã¾ã™" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…ç½®ã§ã™: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…ç½®ã§ã™: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: ä¸æ˜Žãªå†é…置型 %d ã§ã™" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%1$B: `%3$s' ã«å¯¾ã™ã‚‹ Thumb 糊 '%2$s' ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%1$B: `%3$s' ã«å¯¾ã™ã‚‹ ARM 糊 '%2$s' ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): 警告: ARM/Thumb 命令相互利用ãŒæœ‰åŠ¹ã«ãªã£ã¦ã„ã¾ã›ã‚“。\n" +" 最åˆã®å‡ºç¾ç®‡æ‰€: %B: Thumb を呼ã³å‡ºã™ ARM 命令" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): 警告: ARM/Thumb 命令相互利用ãŒæœ‰åŠ¹ã«ãªã£ã¦ã„ã¾ã›ã‚“。\n" +" 最åˆã®å‡ºç¾ç®‡æ‰€: %B: ARM を呼ã³å‡ºã™ Thumb 命令\n" +" --support-old-code を有効ã«ã—ã¦å†ãƒªãƒ³ã‚¯ã™ã‚‹ã“ã¨ã‚’検討ã—ã¦ãã ã•ã„" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%1$B: セクション `%3$A' 内ã«èª¤ã£ãŸå†é…置アドレス 0x%2$lx ãŒã‚ã‚Šã¾ã™" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: å†é…置内ã®ã‚·ãƒ³ãƒœãƒ«ç´¢å¼•ãŒä¸æ­£ã§ã™: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "エラー: %B 㯠APCS-%d ã«å¯¾ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ %B 㯠APCS-%d ã«å¯¾ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã¾ã™" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "エラー: %B ã¯æµ®å‹•å°æ•°ã‚’浮動å°æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã«æ¸¡ã—ã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ %B ã¯æµ®å‹•å°æ•°ã‚’整数レジスタã«æ¸¡ã—ã¦ã„ã¾ã™" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "エラー: %B ã¯æµ®å‹•å°æ•°ã‚’整数レジスタã«æ¸¡ã—ã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ %B ã¯æµ®å‹•å°æ•°ã‚’浮動å°æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã«æ¸¡ã—ã¦ã„ã¾ã™" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "エラー: %B ã¯ä½ç½®éžä¾å­˜ã‚³ãƒ¼ãƒ‰ã¨ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã‚‹ã«ã‚‚é–¢ã‚らãšã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆ %B ã¯çµ¶å¯¾ä½ç½®ã‚³ãƒ¼ãƒ‰ã«ãªã£ã¦ã„ã¾ã™" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "エラー: %B ã¯çµ¶å¯¾ä½ç½®ã‚³ãƒ¼ãƒ‰ã¨ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆ %B ã¯ä½ç½®éžä¾å­˜ã‚³ãƒ¼ãƒ‰ã«ãªã£ã¦ã„ã¾ã™" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "警告: %B 㯠ARM/Thumb 命令相互利用をサãƒãƒ¼ãƒˆã—ã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ %B ã¯ã‚µãƒãƒ¼ãƒˆã—ã¦ã„ã¾ã›ã‚“" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "警告: %B 㯠ARM/Thumb 命令相互利用をサãƒãƒ¼ãƒˆã—ã¦ã„ãªã„ã«ã‚‚ã‹ã‹ã‚らãšã€ %B ã¯ã‚µãƒãƒ¼ãƒˆã—ã¦ã„ã¾ã™" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "private フラグ = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [浮動å°æ•°ãŒæµ®å‹•å°æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã«æ¸¡ã•ã‚Œã¾ã—ãŸ]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [浮動å°æ•°ãŒæ•´æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã«æ¸¡ã•ã‚Œã¾ã—ãŸ]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr " [ä½ç½®éžä¾å­˜]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr " [絶対ä½ç½®]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [ARM/Thumb 命令相互利用ã®ãƒ•ãƒ©ã‚°ã¯åˆæœŸåŒ–ã•ã‚Œã¦ã„ã¾ã›ã‚“]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr " [ARM/Thumb 命令相互利用ãŒã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã™]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr " [ARM/Thumb 命令相互利用ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "警告: ARM/Thumb 命令相互利用をã—ãªã„よã†ã«æ—¢ã«æŒ‡å®šã•ã‚Œã¦ã„ã‚‹ãŸã‚〠%B ã® ARM/Thumb 命令相互利用フラグを設定ã—ã¾ã›ã‚“" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "警告: è¦æ±‚外ã®ãŸã‚ %s ã® ARM/Thumb 命令相互利用フラグをクリアã—ã¾ã™" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "%s 出力を利用ã—ã¦ã„る時ã«ã¯ R_MEM_INDIRECT å†é…置を扱ãˆã¾ã›ã‚“" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "å†é…ç½® `%s' ã¯ã¾ã å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: 警告: ä¸æ­£ãªã‚·ãƒ³ãƒœãƒ«ç´¢å¼• %ld ãŒå†é…置領域内ã«ã‚ã‚Šã¾ã™" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "éž COFF シンボルã«å¯¾ã™ã‚‹å‘¼ã³å‡ºã—è¦ç´„ãŒä¸ç¢ºå®šã§ã™" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…置型ã§ã™" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "GP 関連ã®å†é…置㌠_gp ãŒæœªå®šç¾©ã®æ™‚点ã§ç¾ã‚Œã¾ã—ãŸ" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "èªè­˜ã§ããªã„å†é…ç½®ã§ã™" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: å†é…置型 0x%02x ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: TOC å†é…ç½®(0x%x, シンボル `%s') ã« TOC エントリãŒã‚ã‚Šã¾ã›ã‚“" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: シンボル `%s' ã¯èªè­˜ã§ããªã„ smclas %d ã‚’æŒã£ã¦ã„ã¾ã™" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "èªè­˜ã§ããªã„å†é…置型 0x%x ã§ã™" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: 警告: ä¸æ­£ãªã‚·ãƒ³ãƒœãƒ«ç´¢å¼• %ld ãŒå†é…置領域内ã«ã‚ã‚Šã¾ã™" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "å†é…ç½® %s を無視ã—ã¦ã„ã¾ã™\n" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: 警告: COMDAT シンボル '%s' ã¯ã‚»ã‚¯ã‚·ãƒ§ãƒ³å '%s' ã«é©åˆã—ã¾ã›ã‚“" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: 警告: セクション %s 内㮠IMAGE_SCN_MEM_NOT_PAGED セクションフラグを無視ã—ã¦ã„ã¾ã™" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): セクションフラグ %s (0x%x) を無視ã—ã¾ã—ãŸ" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "TI COFF ターゲット id '0x%x' ã‚’èªè­˜ã§ãã¾ã›ã‚“" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: 存在ã—ãªã„シンボル索引ã«å¯¾ã™ã‚‹å†é…ç½®ã§ã™: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: セクションãŒå¤šã™ãŽã¾ã™ (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: セクション %s: オフセット %ld ã§æ–‡å­—列表ãŒæº¢ã‚Œã¾ã—ãŸ" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: 警告: 行番å·è¡¨ã®èª­ã¿è¾¼ã¿ã«å¤±æ•—ã—ã¾ã—ãŸ" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: 警告: 無効ãªã‚·ãƒ³ãƒœãƒ«ç´¢å¼• %ld ãŒè¡Œç•ªå·ä¸­ã«ã‚ã‚Šã¾ã™" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: 警告: `%s' ã«å¯¾ã™ã‚‹è¡Œç•ªå·æƒ…å ±ãŒé‡è¤‡ã—ã¦ã„ã¾ã™" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%1$B: %3$s シンボル `%4$s' ã«å¯¾ã™ã‚‹èªè­˜ã§ããªã„記憶域クラス %2$d ã§ã™" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "警告: %B: 局所シンボル `%s' ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’æŒã£ã¦ã„ã¾ã›ã‚“" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: ä¸æ­£ãªå†é…置型 %d ãŒã‚¢ãƒ‰ãƒ¬ã‚¹ 0x%lx ã«ã‚ã‚Šã¾ã™" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%s: 文字列表サイズ %lu ãŒèª¤ã£ã¦ã„ã¾ã™" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "警告: %4$B 内ã§ã‚·ãƒ³ãƒœãƒ« `%1$s' ã®åž‹ãŒ %2$d ã‹ã‚‰ %3$d ã«å¤‰æ›´ã•ã‚Œã¾ã—ãŸ" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: セクション `%A' ã«å†é…置領域ãŒã‚ã‚Šã¾ã™ãŒã€ä¸­èº«ãŒã‚ã‚Šã¾ã›ã‚“" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: å†é…置領域ãŒæº¢ã‚Œã¾ã—ãŸ: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: 警告: %s: 行番å·ãŒæº¢ã‚Œã¾ã—ãŸ: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "エラー: %B 㯠EP9312 ã«å¯¾ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ %B 㯠XScale ã«å¯¾ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã¾ã™" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "警告: %2$s 内ã«ã‚ã‚‹ %1$s セクションã®å†…容を更新ã§ãã¾ã›ã‚“" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Dwarf エラー: %s セクションãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“。" + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Dwarf エラー: オフセット (%lu) ㌠%s ã®ã‚µã‚¤ã‚º (%lu) 以上ã§ã™ã€‚" + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf エラー: 無効ã¾ãŸã¯æ‰±ãˆãªã„ FORM 値ã§ã™: %u" + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf エラー: 行番å·ã‚»ã‚¯ã‚·ãƒ§ãƒ³ãŒå¤‰å½¢ã•ã‚Œã¾ã—ãŸï¼ˆä¸æ­£ãªãƒ•ã‚¡ã‚¤ãƒ«ç•ªå·ï¼‰ã€‚" + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Dwarf エラー: .debug_line ãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d を扱ãˆã¾ã›ã‚“ã§ã—ãŸã€‚" + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Dwarf エラー: 無効ãªå‘½ä»¤ã”ã¨ã®æœ€å¤§æ“作数ã§ã™ã€‚" + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf エラー: 行番å·ã‚»ã‚¯ã‚·ãƒ§ãƒ³ãŒå¤‰å½¢ã•ã‚Œã¾ã—ãŸã€‚" + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf エラー: abbrev ç•ªå· %u ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“ã§ã—ãŸã€‚" + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Dwarf エラー: dwarf ãƒãƒ¼ã‚¸ãƒ§ãƒ³ '%u' ãŒè¦‹ã¤ã‹ã‚Šã¾ã—ãŸãŒã€ã“ã®å‡¦ç†ç³»ã¯ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 2, 3 ãŠã‚ˆã³ 4 ã®æƒ…å ±ã—ã‹èª­ã¿è¾¼ã‚ã¾ã›ã‚“。" + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf エラー: アドレスサイズ '%u' ãŒè¦‹ã¤ã‹ã‚Šã¾ã—ãŸãŒã€ã“ã®å‡¦ç†ç³»ã¯ã‚µã‚¤ã‚º '%u' より大ãã„サイズを扱ãˆã¾ã›ã‚“。" + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf エラー: ä¸æ­£ãª abbrev 番å·ã§ã™: %u" + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "基本型 %d ãŒä¸æ˜Žã§ã™" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" End+1 シンボル: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" 最åˆã®ã‚·ãƒ³ãƒœãƒ«: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" End+1 シンボル: %-7ld タイプ: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" 局所シンボル: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; End+1 シンボル: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; End+1 シンボル: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; End+1 シンボル: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" åž‹: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "エラー: %B: オブジェクトã«ã¯ãƒ™ãƒ³ãƒ€å›ºæœ‰ã®å†…容ãŒã‚ã‚Š '%s' ツール群ã§å‡¦ç†ã•ã‚Œãªã‘ã‚Œã°ã„ã‘ã¾ã›ã‚“" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "エラー: %B: オブジェクトタグ '%d, %s' ã¯ã‚¿ã‚° '%d, %s' ã¨äº’æ›æ€§ãŒã‚ã‚Šã¾ã›ã‚“" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: %B(%A) 内ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºç”Ÿã—ã¾ã—ãŸã€‚.eh_frame_hdr 表ã¯ä½œæˆã•ã‚Œã¾ã›ã‚“。\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: %B(%A) 内㮠fde エンコード㯠.eh_frame_hdr 表ã®ä½œæˆã‚’阻害ã—ã¾ã™ã€‚\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "内部エラー: 範囲外エラーã§ã™" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "内部エラー: 未サãƒãƒ¼ãƒˆã®å†é…置エラー" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "内部エラー: å±é™ºãªã‚¨ãƒ©ãƒ¼" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "内部エラー: ä¸æ˜Žãªã‚¨ãƒ©ãƒ¼" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%1$B(%2$A+0x%3$lx): シンボル `%5$s' ã«å¯¾ã™ã‚‹è§£æ±ºã§ããªã„ %4$s å†é…ç½®ã§ã™" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "エラー: 共有ライブラリã«å¯¾ã™ã‚‹ä¸é©åˆ‡ãªå†é…置型ã§ã™ (-fpic を忘れã¦ã„ã¾ã›ã‚“ã‹?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "内部エラー: 共有ライブラリ内ã«ç–‘å•ã®æ®‹ã‚‹å†é…置型ãŒä½¿ç”¨ã•ã‚Œã¦ã„ã¾ã™" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "動的変数 `%s' ã®ã‚µã‚¤ã‚ºãŒ 0 ã§ã™" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%1$B: `%4$s' ã«å¯¾ã™ã‚‹ç„¡åŠ¹ãªæ–‡å­—列オフセット %2$u >= %3$lu ã§ã™" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B ã‚·ãƒ³ãƒœãƒ«ç•ªå· %lu ãŒå­˜åœ¨ã—ãªã„ SHT_SYMTAB_SHNDX セクションをå‚ç…§ã—ã¦ã„ã¾ã™" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: グループセクションヘッダ内ã«å£Šã‚ŒãŸã‚µã‚¤ã‚ºãƒ•ã‚£ãƒ¼ãƒ«ãƒ‰ãŒã‚ã‚Šã¾ã™: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: 無効㪠SHT_GROUP エントリã§ã™" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: セクション %A ã«ã‚°ãƒ«ãƒ¼ãƒ—情報ãŒã‚ã‚Šã¾ã›ã‚“" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: 警告: セクション `%A' ã«å¯¾ã™ã‚‹ sh_link ãŒè¨­å®šã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%1$B: セクション `%2$A' 内㮠sh_link [%d] ã«èª¤ã‚ŠãŒã‚ã‚Šã¾ã™" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%1$B: グループ [%4$s] 内ã«ä¸æ˜Žãª [%2$d] セクション `%3$s' ãŒã‚ã‚Šã¾ã™" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: セクション %s ã«å¯¾ã™ã‚‹åœ§ç¸®çŠ¶æ…‹ã‚’åˆæœŸåŒ–ã§ãã¾ã›ã‚“" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: セクション %s ã«å¯¾ã™ã‚‹ä¼¸å¼µçŠ¶æ…‹ã‚’åˆæœŸåŒ–ã§ãã¾ã›ã‚“" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"プログラムヘッダ:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"動的セクション:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"ãƒãƒ¼ã‚¸ãƒ§ãƒ³å®šç¾©:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"ãƒãƒ¼ã‚¸ãƒ§ãƒ³å‚ç…§:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " %s ã‹ã‚‰ã®è¦æ±‚:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%1$B: å†é…置セクション %3$s ã«å¯¾ã™ã‚‹ç„¡åŠ¹ãªãƒªãƒ³ã‚¯ %2$lu ã§ã™ (索引 %4$u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: 割り当ã¦æ¸ˆã¿ã®ã‚¢ãƒ—リケーション固有ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' [0x%8x] を扱ã†æ–¹æ³•ãŒåˆ†ã‹ã‚Šã¾ã›ã‚“" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: プロセッサ固有ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' [0x%8x] を扱ã†æ–¹æ³•ãŒåˆ†ã‹ã‚Šã¾ã›ã‚“" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: OS 固有ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' [0x%8x] を扱ã†æ–¹æ³•ãŒåˆ†ã‹ã‚Šã¾ã›ã‚“" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: セクション `%s' [0x%8x] を扱ã†æ–¹æ³•ãŒåˆ†ã‹ã‚Šã¾ã›ã‚“" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "警告: セクション `%A' ã®åž‹ãŒ PROGBITS ã«å¤‰æ›´ã•ã‚Œã¾ã—ãŸ" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%1$B: セクション `%2$A' ã® sh_link ㌠`%4$B' ã®ç ´æ£„ã•ã‚ŒãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%3$A' を指ã—ã¦ã„ã¾ã™" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%1$B: セクション `%2$A' ã® sh_link ㌠`%4$B' ã®å‰Šé™¤ã•ã‚ŒãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%3$A' を指ã—ã¦ã„ã¾ã™" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: PT_DYNAMIC セグメントã®æœ€åˆã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ãŒ .dynamic セクションã§ã¯ã‚ã‚Šã¾ã›ã‚“" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: プログラムヘッダ用ã®ç©ºé–“ãŒä¸å分ã§ã™ã€‚-N を付ã‘ã¦ãƒªãƒ³ã‚¯ã—ã¦ã¿ã¦ãã ã•ã„" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: セクション `%A' をセグメント %d 内ã§å‰²ã‚Šå½“ã¦ã‚‹ã“ã¨ãŒã§ãã¾ã›ã‚“" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: 警告: 割り当ã¦æ¸ˆã¿ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' ãŒã‚»ã‚°ãƒ¡ãƒ³ãƒˆå†…ã«ã‚ã‚Šã¾ã›ã‚“" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: シンボル `%s' ãŒè¦æ±‚ã•ã‚Œã¾ã—ãŸãŒå­˜åœ¨ã—ã¾ã›ã‚“" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: 警告: 空ã®ãƒ­ãƒ¼ãƒ‰å¯èƒ½ã‚»ã‚°ãƒ¡ãƒ³ãƒˆãŒæ¤œå‡ºã•ã‚Œã¾ã—ãŸã€‚ã“ã‚Œã¯æ„図ã—ãŸã‚‚ã®ã§ã™ã‹?\n" + +#: elf.c:6622 +#, fuzzy, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "%s: 出力セクション %s (入力セクション %s 用) を見ã¤ã‘られã¾ã›ã‚“" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…置型 %s ã§ã™" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): 警告: ARM/Thumb 命令相互利用ãŒæœ‰åŠ¹ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" +" 最åˆã®å‡ºç¾ç®‡æ‰€: %B: ARM を呼ã³å‡ºã™ Thumb 命令" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): 警告: ARM/Thumb 命令相互利用ãŒæœ‰åŠ¹ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" +" 最åˆã®å‡ºç¾ç®‡æ‰€: %B: Thumb を呼ã³å‡ºã™ ARM 命令" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: スタブエントリ %s を作æˆã§ãã¾ã›ã‚“" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "'%2$s' ã«å¯¾ã™ã‚‹ Thumb 糊 '%1$s' ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "'%2$s' ã«å¯¾ã™ã‚‹ ARM 糊 '%1$s' ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: BE8 イメージã¯ãƒ“ッグエンディアンモードã§ã®ã¿æœ‰åŠ¹ã§ã™" + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "無効㪠TARGET2 å†é…置型 '%s' ã§ã™ã€‚" + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): 警告: ARM/Thumb 命令相互利用ãŒæœ‰åŠ¹ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" +" 最åˆã®å‡ºç¾ç®‡æ‰€: %B: ARM を呼ã³å‡ºã™ Thumb 命令" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: 警告: ARM ã® BLX 命令㌠ARM 関数 '%s' を指ã—ã¦ã„ã¾ã™ã€‚" + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: 警告: Thumb ã® BLX 命令㌠Thumb 関数 '%s' を指ã—ã¦ã„ã¾ã™ã€‚" + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_ARM_TLS_LE32 å†é…ç½®ã¯å…±æœ‰ã‚ªãƒ–ジェクト内ã§ã¯è¨±å¯ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): ALU グループå†é…ç½®ã«å¯¾ã—ã¦ã¯ ADD ã¾ãŸã¯ SUB 命令ã®ã¿è¨±å¯ã•ã‚Œã¦ã„ã¾ã™" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): SEC_MERGE セクションã«å¯¾ã™ã‚‹ %s å†é…ç½®ã§ã™" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s ㌠TLS シンボル %s ã¨ä½µã›ã¦ä½¿ç”¨ã•ã‚Œã¾ã—ãŸ" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s ㌠TLS ã§ã¯ãªã„シンボル %s ã¨ä½µã›ã¦ä½¿ç”¨ã•ã‚Œã¾ã—ãŸ" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "範囲外" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…ç½®" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "ä¸æ˜Žãªã‚¨ãƒ©ãƒ¼" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: ä¸æ˜Žãªå¿…é ˆ EABI オブジェクト属性 %d ã§ã™" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "警告: %B: ä¸æ˜ŽãªEABI オブジェクト属性 %d ã§ã™" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "エラー: %B: ä¸æ˜Žãª CPU アーキテクãƒãƒ£ã§ã™" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "エラー: %B: CPU アーキテクãƒãƒ£ %d/%d ãŒç«¶åˆã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "エラー: %B: アーキテクãƒãƒ£ãƒ—ロファイル %c/%c ãŒç«¶åˆã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "警告: %B: プラットフォーム設定ãŒç«¶åˆã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "エラー: %B: R9 ã®ä½¿ç”¨ãŒç«¶åˆã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "エラー: %B 㯠iWMMXt レジスタ引数を使用ã—ã¦ã„ã¾ã™ãŒã€ %B ã¯ä½¿ç”¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "エラー: fp16 ã®å½¢å¼ãŒ %B 㨠%B ã®é–“ã§ä¸€è‡´ã—ã¾ã›ã‚“" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "DIV ã®ä½¿ç”¨æ³•ãŒ %B 㨠%B ã®é–“ã§ä¸€è‡´ã—ã¾ã›ã‚“" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "private フラグ = %lx:" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [ARM/Thumb 命令相互利用ã¯æœ‰åŠ¹]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [VFP 浮動å°æ•°å½¢å¼]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [Maverick 浮動å°æ•°å½¢å¼]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [FPA 浮動å°æ•°å½¢å¼]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [æ–° ABI]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [æ—§ ABI]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [ソフトウェア浮動å°æ•°ç‚¹]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 1 EABI]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [ソート済シンボル表]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [未ソートシンボル表]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 2 EABI]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr "" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr "" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 3 EABI]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 4 EABI]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [ãƒãƒ¼ã‚¸ãƒ§ãƒ³ 5 EABI]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [å†é…ç½®å¯èƒ½å®Ÿè¡Œãƒ•ã‚¡ã‚¤ãƒ«]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [エントリãƒã‚¤ãƒ³ãƒˆã‚’æŒã£ã¦ã„ã¾ã™]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "<フラグビットセットをèªè­˜ã§ãã¾ã›ã‚“>" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: シンボル索引ã«èª¤ã‚ŠãŒã‚ã‚Šã¾ã™: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%1$B: `%3$s' ã«å¯¾ã™ã‚‹å†é…ç½® %2$s ã¯å…±æœ‰ã‚ªãƒ–ジェクト作æˆæ™‚ã«ã¯ä½¿ç”¨ã§ãã¾ã›ã‚“。-fPIC を付ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„。" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "ファイル %s を処ç†ä¸­ã«ã‚¨ãƒ©ãƒ¼ãŒç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "エラー: %B ã¯æ—¢ã«æœ€çµ‚ BE8 å½¢å¼ã§ã™" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "エラー: ソースオブジェクト %B 㯠EABI ãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d ã§ã™ãŒã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆ %B 㯠EABI ãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d ã§ã™" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "エラー: %B 㯠APCS-%d ã«å¯¾ã—ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¦ã„ã¾ã™ã€‚一方ターゲット %B 㯠APCS-%d を使用ã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "error: %B 㯠VFP 命令を使用ã—ã¦ã„ã¾ã™ã€‚一方 %B ã¯ä½¿ç”¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "エラー: %B 㯠FPA 命令を使用ã—ã¦ã„ã¾ã™ã€‚一方 %B ã¯ä½¿ç”¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "エラー: %B 㯠Maverick 命令を使用ã—ã¦ã„ã¾ã™ã€‚一方 %B ã¯ä½¿ç”¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "エラー: %B 㯠Maverick 命令を使用ã—ã¦ã„ã¾ã›ã‚“。一方 %B ã¯ä½¿ç”¨ã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "エラー: %B ã¯ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢æµ®å‹•å°æ•°ç‚¹ã‚’使用ã—ã¦ã„ã¾ã™ã€‚一方 %B ã¯ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢æµ®å‹•å°æ•°ç‚¹ã‚’使用ã—ã¦ã„ã¾ã™" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "エラー: %B ã¯ãƒãƒ¼ãƒ‰ã‚¦ã‚§ã‚¢æµ®å‹•å°æ•°ç‚¹ã‚’使用ã—ã¦ã„ã¾ã™ã€‚一方 %B ã¯ã‚½ãƒ•ãƒˆã‚¦ã‚§ã‚¢æµ®å‹•å°æ•°ç‚¹ã‚’使用ã—ã¦ã„ã¾ã™" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "内部エラー: å±é™ºãªå†é…ç½®ã§ã™" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: スタブエントリ %s を作æˆã§ãã¾ã›ã‚“" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): シンボル `%s' ã«å¯¾ã™ã‚‹è§£æ±ºã§ããªã„å†é…ç½®ã§ã™" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): `%s' ã«å¯¾ã™ã‚‹å†é…ç½®: エラー %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "å†é…ç½®ãŒãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«å†…ã§å®šç¾©ã•ã‚Œã¦ã„ãªã„シンボルをå‚ç…§ã—ã¦ã„ã¾ã™" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "読ã¿è¾¼ã¿å°‚用セクション内ã§ä¿®æ­£ã‚’è¡Œã†ã“ã¨ãŒã§ãã¾ã›ã‚“" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "読ã¿è¾¼ã¿å°‚用セクション内ã§å‹•çš„å†é…置を行ã†ã“ã¨ãŒã§ãã¾ã›ã‚“" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "ç•°ãªã‚‹ã‚»ã‚°ãƒ¡ãƒ³ãƒˆé–“ã®å†é…ç½®ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "警告: å†é…ç½®ãŒç•°ãªã‚‹ã‚»ã‚°ãƒ¡ãƒ³ãƒˆã‚’å‚ç…§ã—ã¦ã„ã¾ã™" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…置型 %i ã§ã™" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: fdpic 実行ファイル内ã«éž fdpic オブジェクトをリンクã™ã‚‹ã“ã¨ã¯ã§ãã¾ã›ã‚“" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: éž fdpic 実行ファイル内㫠fdpic オブジェクトをリンクã™ã‚‹ã“ã¨ã¯ã§ãã¾ã›ã‚“" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%1$B セクション %2$A: シンボル `%4$s' ã«å¯¾ã™ã‚‹è§£æ±ºã§ããªã„å†é…ç½® %3$s ã§ã™" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "" + +#: elf32-cris.c:1395 +#, fuzzy +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%s: å†é…ç½® %s ã¯ã‚·ãƒ³ãƒœãƒ« %s 用ã®ã‚‚ã®ã¨ã—ã¦ã¯ã¾ã ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" + +#: elf32-cris.c:3353 +#, fuzzy +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ãŸã¨ãã«ã¯ä½¿ãˆã¾ã›ã‚“ -- -fPIC を付ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„" + +#: elf32-cris.c:3567 +#, fuzzy +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ãŸã¨ãã«ã¯ä½¿ã†ã¹ãã§ã¯ã‚ã‚Šã¾ã›ã‚“ -- -fPIC ã‚’ã¤ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„" + +#: elf32-cris.c:3992 +#, fuzzy +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ãŸã¨ãã«ã¯ä½¿ã†ã¹ãã§ã¯ã‚ã‚Šã¾ã›ã‚“ -- -fPIC ã‚’ã¤ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "予期ã—ãªã„マシン番å·ã§ã™" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [ _ 接頭辞ã¤ãシンボル]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 ãŠã‚ˆã³ v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: _ 接頭辞付ãシンボルを使用ã—ã¦ã„ã¾ã™ãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ã«ã¯ _ 接頭辞無ã—シンボルã¨ã—ã¦æ›¸ãè¾¼ã¿ã¾ã™" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: _ 接頭辞無ã—シンボルを使用ã—ã¦ã„ã¾ã™ãŒã€ãƒ•ã‚¡ã‚¤ãƒ«ã«ã¯ _ 接頭辞付ãシンボルã¨ã—ã¦æ›¸ãè¾¼ã¿ã¾ã™" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B ã«ã¯ CRIS v32 コードãŒå«ã¾ã‚Œã¦ã„ã¾ã™ã€‚ã“ã‚Œã¯å‰ã®ã‚ªãƒ–ジェクトã¨äº’æ›æ€§ãŒã‚ã‚Šã¾ã›ã‚“" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B ã«ã¯éž-CRIS-v32 コードãŒå«ã¾ã‚Œã¦ã„ã¾ã™ã€‚ã“ã‚Œã¯å‰ã®ã‚ªãƒ–ジェクトã¨äº’æ›æ€§ãŒã‚ã‚Šã¾ã›ã‚“" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF 㯠call 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 㯠lddi 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI 㯠sethi 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO 㯠setlo ã¾ãŸã¯ setlos 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX 㯠ldd 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX 㯠calll 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 㯠ldi 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI 㯠sethi 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO 㯠setlo ã¾ãŸã¯ setlos 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX 㯠ld 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI 㯠sethi 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO 㯠setlo ã¾ãŸã¯ setlos 命令ã«é©ç”¨ã•ã‚Œã¾ã›ã‚“" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): `%s' ã«å¯¾ã™ã‚‹å†é…ç½®: %s" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, fuzzy, c-format +msgid "private flags = 0x%lx:" +msgstr "private フラグ = %lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +#, fuzzy +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%s(%s+0x%lx): %s ã«å±Šãã¾ã›ã‚“。-ffunction-sections を付ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„" + +#: elf32-hppa.c:1284 +#, fuzzy +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ãŸã¨ãã«ã¯ä½¿ãˆã¾ã›ã‚“ -- -fPIC を付ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¦ãã ã•ã„" + +#: elf32-hppa.c:2803 +#, fuzzy +msgid "%B: duplicate export stub %s" +msgstr "%s: export スタブ %s ãŒé‡è¤‡ã—ã¦ã„ã¾ã™" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "" + +#: elf32-hppa.c:4296 +#, fuzzy +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%s(%s+0x%lx): %s (%s) ã‚’å–り扱ãˆã¾ã›ã‚“" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr ".got セクション㌠.plt セクションã®ç›´å¾Œã«ã‚ã‚Šã¾ã›ã‚“" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: 無効ãªå†é…置型 %d ã§ã™" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: `%s' ãŒé€šå¸¸ã®ã‚·ãƒ³ãƒœãƒ«ã¨ã‚¹ãƒ¬ãƒƒãƒ‰å±€æ‰€ã‚·ãƒ³ãƒœãƒ«ã«ã‚¢ã‚¯ã‚»ã‚¹ã—ã¾ã—ãŸ" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%1$B: セクション `%3$A' ã«èªè­˜ã§ããªã„å†é…ç½® (0x%2$x) ãŒã‚ã‚Šã¾ã™" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "éš ã•ã‚ŒãŸã‚·ãƒ³ãƒœãƒ«" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "内部シンボル" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "ä¿è­·ã•ã‚ŒãŸã‚·ãƒ³ãƒœãƒ«" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "シンボル" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, fuzzy, c-format +msgid "discarded output section: `%A'" +msgstr "%s: 出力セクション %s (入力セクション %s 用) を見ã¤ã‘られã¾ã›ã‚“" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "" + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "" + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "" + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "" + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +#, fuzzy +msgid "unsupported relocation between data/insn address spaces" +msgstr "%s: サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…置タイプ %s ã§ã™" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: 使用ã—ã¦ã„ã‚‹ e_flags(0x%lx) ãŒä»¥å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« (0x%lx) ã¨ç•°ãªã£ã¦ã„ã¾ã™" + +#: elf32-lm32.c:706 +#, fuzzy +msgid "global pointer relative relocation when _gp not defined" +msgstr "GP 関連ã®å†é…置㌠_gp ãŒæœªå®šç¾©ã®æ™‚点ã§ç¾ã‚Œã¾ã—ãŸ" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "_SDA_BASE_ ãŒæœªå®šç¾©ã®æ™‚点ã§ã® SDA å†é…ç½®ã§ã™" + +#: elf32-m32r.c:3048 +#, fuzzy +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%s: ターゲット (%s, %s å†é…ç½®) ãŒé–“é•ã£ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ (%s) 内ã«ã‚ã‚Šã¾ã™" + +#: elf32-m32r.c:3576 +#, fuzzy +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%s: 命令セットãŒä»¥å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¨é©åˆã—ã¾ã›ã‚“" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "private フラグ = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": m32r 命令" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": m32rx 命令" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": m32r2 命令" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "" + +#: elf32-m68hc1x.c:1241 +#, fuzzy +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "エラー: %s 㯠APCS-%d 用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸã«ã‚‚ã‹ã‹ã‚らãšã€%s ㌠APCS-%d 用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¾ã—ãŸ" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +#, fuzzy +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: 使用ã—ã¦ã„ã‚‹ e_flags(0x%lx) ãŒä»¥å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« (0x%lx) ã¨ç•°ãªã£ã¦ã„ã¾ã™" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-ビット整数, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-ビット整数, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "64-ビットå€ç²¾åº¦æµ®å‹•å°æ•°, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "32-ビットå€ç²¾åº¦æµ®å‹•å°æ•°, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr "" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr "" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "ä¸æ˜Ž" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: å†é…ç½® %s (%d) ã¯ç¾åœ¨ã®ã¨ã“ã‚サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“。\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: ä¸æ˜Žãªå†é…置型 %d ã§ã™\n" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B ãŠã‚ˆã³ %B ã¯ç•°ãªã‚‹ã‚³ã‚¢ã«å¯¾ã™ã‚‹ã‚‚ã®ã§ã™" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B ãŠã‚ˆã³ %B ã¯ç•°ãªã‚‹è¨­å®šã«å¯¾ã™ã‚‹ã‚‚ã®ã§ã™" + +#: elf32-mep.c:701 +#, fuzzy, c-format +msgid "private flags = 0x%lx" +msgstr "private フラグ = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: å†é…置型 %d ãŒä¸æ˜Žã§ã™" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: ターゲット (%s, %s å†é…ç½®) ãŒé–“é•ã£ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ (%s) 内ã«ã‚ã‚Šã¾ã™" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: æらã -fPIC を付ã‘ãšã«ã‚³ãƒ³ãƒ‘イルã—ãŸã®ã§ã¯?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +#, fuzzy +msgid "%B: bad relocation section name `%s'" +msgstr "%s: ä¸æ­£ãªå†é…置アドレス 0x%lx ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' 内ã«ã‚ã‚Šã¾ã™" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +#, fuzzy +msgid "literal relocation occurs for an external symbol" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "" + +#: elf32-ppc.c:2199 +#, fuzzy +msgid "unable to read in %s section from %B" +msgstr "%s 用ã®å†é…置セクションを見ã¤ã‘られã¾ã›ã‚“" + +#: elf32-ppc.c:2240 +#, fuzzy +msgid "warning: unable to set size of %s section in %B" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "" + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "" + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "" + +#: elf32-ppc.c:3358 +#, fuzzy +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ã¦ã„る時点ã§ã¯åˆ©ç”¨ã§ãã¾ã›ã‚“" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +#, fuzzy +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%s: 0x%lx ã§ã® CALL16 å†é…ç½®ãŒå¤§åŸŸã‚·ãƒ³ãƒœãƒ«ã‚’対象ã¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "" + +#: elf32-ppc.c:4197 +#, fuzzy +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s: -mrelocatable を付ã‘ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸã‚‚ã®ã¨æ™®é€šã«ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¨ã‚’リンクã—ã¾ã—ãŸ" + +#: elf32-ppc.c:4205 +#, fuzzy +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s: 普通ã«ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸã‚‚ã®ã¨ -mrelocatable を付ã‘ã¦ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¨ã‚’リンクã—ã¾ã—ãŸ" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +#, fuzzy +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%s: å†é…置タイプ %d (シンボル %s) ãŒä¸æ˜Žã§ã™" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +#, fuzzy +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%s: ターゲット %s (%så†é…ç½®) ãŒé–“é•ã£ãŸå‡ºåŠ›ã‚»ã‚¯ã‚·ãƒ§ãƒ³ (%s) ã«ã‚ã‚Šã¾ã™" + +#: elf32-ppc.c:8030 +#, fuzzy +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%s: å†é…ç½® %s ã¯ã‚·ãƒ³ãƒœãƒ« %s 用ã®ã‚‚ã®ã¨ã—ã¦ã¯ã¾ã ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "" + +#: elf32-ppc.c:8629 +#, fuzzy, c-format +msgid "%s not defined in linker created %s" +msgstr "%s: シンボルå %s ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒæœªå®šç¾©ã§ã™" + +#: elf32-rx.c:544 +#, fuzzy +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%s: 0x%lx: 警告: 存在ã™ã‚‹ã¯ãšã®å†é…置領域を見ã¤ã‘られã¾ã›ã‚“" + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "" + +#: elf32-rx.c:1265 +#, fuzzy +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "警告: シンボル `%s' ã®ã‚µã‚¤ã‚ºãŒ %lu ã‹ã‚‰ %lu ã«å¤‰æ›´ã•ã‚Œã¾ã—㟠(%s 内)" + +#: elf32-rx.c:1269 +#, fuzzy +msgid "%B(%A): internal error: out of range error" +msgstr "内部エラー: 範囲外エラーã§ã™" + +#: elf32-rx.c:1273 +#, fuzzy +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "内部エラー: 未サãƒãƒ¼ãƒˆã®å†é…置エラー" + +#: elf32-rx.c:1277 +#, fuzzy +msgid "%B(%A): internal error: dangerous relocation" +msgstr "内部エラー: å±é™ºãªå†é…ç½®ã§ã™" + +#: elf32-rx.c:1281 +#, fuzzy +msgid "%B(%A): internal error: unknown error" +msgstr "内部エラー: ä¸æ˜Žãªã‚¨ãƒ©ãƒ¼" + +#: elf32-rx.c:2928 +#, fuzzy, c-format +msgid " [64-bit doubles]" +msgstr "64-ビットå€ç²¾åº¦æµ®å‹•å°æ•°, " + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr "" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "局所 GOT エントリ用㮠GOT 空間ãŒä¸å分ã§ã™" + +#: elf32-score.c:2744 +#, fuzzy +msgid "address not word align" +msgstr "å†é…置領域ãŒé©åˆ‡ã«ã‚¢ãƒ©ã‚¤ãƒ³ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, fuzzy, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "セクション %s 用ã¨ã—ã¦ã¯ãŠã‹ã—ãªå†é…置を検出ã—ã¾ã—ãŸ" + +#: elf32-score.c:2880 elf32-score7.c:2685 +#, fuzzy +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%s: 0x%lx ã§ã® CALL16 å†é…ç½®ãŒå¤§åŸŸã‚·ãƒ³ãƒœãƒ«ã‚’対象ã¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr "" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr "" + +#: elf32-score.c:4045 elf32-score7.c:3852 +#, fuzzy +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%s: PIC ファイルã«éž PIC ファイルをリンクã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "" + +#: elf32-sh-symbian.c:383 +#, fuzzy +msgid "%B: Unrecognised .directive command: %s" +msgstr "%s: import タイプをèªè­˜ã§ãã¾ã›ã‚“ -- %x" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "" + +#: elf32-sh.c:568 +#, fuzzy +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s: 0x%lx: 警告: R_SH_USES オフセットãŒä¸æ­£ã§ã™" + +#: elf32-sh.c:580 +#, fuzzy +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s: 0x%lx: 警告: R_SH_USES ãŒèªè­˜ã§ããªã„命令 0x%x を指ã—ã¦ã„ã¾ã™" + +#: elf32-sh.c:597 +#, fuzzy +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s: 0x%lx: 警告: R_SH_USES load オフセットãŒä¸æ­£ã§ã™" + +#: elf32-sh.c:612 +#, fuzzy +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%s: 0x%lx: 警告: 存在ã™ã‚‹ã¯ãšã®å†é…置領域を見ã¤ã‘られã¾ã›ã‚“" + +#: elf32-sh.c:640 +#, fuzzy +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%s: 0x%lx: 警告: シンボルãŒäºˆæœŸã›ã¬ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã«ã‚ã‚Šã¾ã™" + +#: elf32-sh.c:766 +#, fuzzy +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s: 0x%lx: 警告: 存在ã™ã‚‹ã¯ãšã® COUNT å†é…置領域を見ã¤ã‘られã¾ã›ã‚“" + +#: elf32-sh.c:775 +#, fuzzy +msgid "%B: 0x%lx: warning: bad count" +msgstr "%s: 0x%lx: 警告: count ãŒä¸æ­£ã§ã™" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +#, fuzzy +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s: 0x%lx: 致命的: relax 中ã«å†é…置領域ãŒã‚ªãƒ¼ãƒãƒ¼ãƒ•ãƒ­ãƒ¼ã—ã¾ã—ãŸ" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +#, fuzzy +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%s: ローダå†é…ç½®ãŒèª­è¾¼ã¿å°‚用セクション %s ã«ã‚ã‚Šã¾ã™" + +#: elf32-sh.c:5101 +#, fuzzy +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%s: 0x%lx ã§ã® CALL16 å†é…ç½®ãŒå¤§åŸŸã‚·ãƒ³ãƒœãƒ«ã‚’対象ã¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-sh.c:5574 +#, fuzzy, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%s: 警告: 確ä¿ã•ã‚ŒãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' ãŒã‚»ã‚°ãƒ¡ãƒ³ãƒˆå†…ã«ã‚ã‚Šã¾ã›ã‚“" + +#: elf32-sh.c:5580 +#, fuzzy, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%s: 警告: 確ä¿ã•ã‚ŒãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' ãŒã‚»ã‚°ãƒ¡ãƒ³ãƒˆå†…ã«ã‚ã‚Šã¾ã›ã‚“" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +#, fuzzy +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: `%s' ãŒé€šå¸¸ã®ã‚·ãƒ³ãƒœãƒ«ã¨ã‚¹ãƒ¬ãƒƒãƒ‰å±€æ‰€ã‚·ãƒ³ãƒœãƒ«ã«ã‚¢ã‚¯ã‚»ã‚¹ã—ã¾ã—ãŸ" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +#, fuzzy +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: `%s' ãŒé€šå¸¸ã®ã‚·ãƒ³ãƒœãƒ«ã¨ã‚¹ãƒ¬ãƒƒãƒ‰å±€æ‰€ã‚·ãƒ³ãƒœãƒ«ã«ã‚¢ã‚¯ã‚»ã‚¹ã—ã¾ã—ãŸ" + +#: elf32-sh.c:6393 +#, fuzzy +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "" +"\n" +"関数記述å­ã¯é–‹å§‹ã‚¢ãƒ‰ãƒ¬ã‚¹ã«ä½ç½®ã—ã¦ã„ã¾ã™: %04lx\n" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +#, fuzzy +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ã¦ã„る時点ã§ã¯åˆ©ç”¨ã§ãã¾ã›ã‚“" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, fuzzy, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: 64 ビットシステム用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¾ã—ãŸãŒã‚¿ãƒ¼ã‚²ãƒƒãƒˆãŒ 32 ビットã§ã™" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, fuzzy, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: 64 ビットシステム用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¾ã—ãŸãŒã‚¿ãƒ¼ã‚²ãƒƒãƒˆãŒ 32 ビットã§ã™" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "" + +#: elf32-sh64.c:598 +#, fuzzy +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%s: ä¸æ­£ãªå†é…置タイプ %d ãŒã‚¢ãƒ‰ãƒ¬ã‚¹ 0x%lx ã§è¦‹ã¤ã‹ã‚Šã¾ã—ãŸ" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "" + +#: elf32-sparc.c:89 +#, fuzzy +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%s: 64 ビットシステム用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¾ã—ãŸãŒã‚¿ãƒ¼ã‚²ãƒƒãƒˆãŒ 32 ビットã§ã™" + +#: elf32-sparc.c:102 +#, fuzzy +msgid "%B: linking little endian files with big endian files" +msgstr "%s: リトルエンディアンã®ãƒ•ã‚¡ã‚¤ãƒ«ã¨ãƒ“ッグエンディアンã®ãƒ•ã‚¡ã‚¤ãƒ«ã¨ã‚’リンクã—よã†ã¨ã—ã¦ã„ã¾ã™" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr "" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr "" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr "" + +#: elf32-spu.c:4307 +#, fuzzy, c-format +msgid "%s duplicated in %s\n" +msgstr "%s: export スタブ %s ãŒé‡è¤‡ã—ã¦ã„ã¾ã™" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "" + +#: elf32-spu.c:5006 +#, fuzzy +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf32-tic6x.c:1539 +#, fuzzy +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "GP 関連ã®å†é…置㌠_gp ãŒæœªå®šç¾©ã®æ™‚点ã§ç¾ã‚Œã¾ã—ãŸ" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +#, fuzzy +msgid "%B: relocation type %d not implemented" +msgstr "å†é…ç½® `%s' ã¯ã¾ã å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“\n" + +#: elf32-tic6x.c:1640 +#, fuzzy +msgid "dangerous relocation" +msgstr "内部エラー: å±é™ºãªå†é…ç½®ã§ã™" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "変数 `%s' ã¯è¤‡æ•°ã® small データ領域をå æœ‰ã™ã‚‹ã“ã¨ãŒã§ãã¾ã›ã‚“" + +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "変数 `%s' 㯠small, zero åŠã³ tiny データ領域ã®å†…一ã¤ã«ã®ã¿ç½®ãã“ã¨ãŒã§ãã¾ã™" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "変数 `%s' ã‚’ small 㨠zero データ領域ã¸åŒæ™‚ã«ç½®ãã“ã¨ã¯ã§ãã¾ã›ã‚“" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "変数 `%s' ã‚’ small 㨠tiny データ領域ã¸åŒæ™‚ã«ç½®ãã“ã¨ã¯ã§ãã¾ã›ã‚“" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "変数 `%s' 㯠zero 㨠tiny データ領域ã¸åŒæ™‚ã«ç½®ãã“ã¨ã¯ã§ãã¾ã›ã‚“" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "以å‰ã® HI16 å†é…置を見ã¤ã‘られã¾ã›ã‚“ã§ã—ãŸ\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "特殊リンカシンボル __gp ã®ä½ç½®ã‚’特定ã§ãã¾ã›ã‚“ã§ã—ãŸ" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "特殊リンカシンボル __ep ã®ä½ç½®ã‚’特定ã§ãã¾ã›ã‚“ã§ã—ãŸ" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "特殊リンカシンボル __ctbp ã®ä½ç½®ã‚’特定ã§ãã¾ã›ã‚“ã§ã—ãŸ" + +#: elf32-v850.c:2341 +#, fuzzy +msgid "%B: Architecture mismatch with previous modules" +msgstr "%s: 以å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ«ã¨ã‚¢ãƒ¼ã‚­ãƒ†ã‚¯ãƒãƒ£ãŒä¸€è‡´ã—ã¾ã›ã‚“" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "private フラグ = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "v850 アーキテクãƒãƒ£" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "v850e アーキテクãƒãƒ£" + +#: elf32-v850.c:2367 +#, fuzzy, c-format +msgid "v850e1 architecture" +msgstr "v850e アーキテクãƒãƒ£" + +#: elf32-v850.c:2368 +#, fuzzy, c-format +msgid "v850e2 architecture" +msgstr "v850e アーキテクãƒãƒ£" + +#: elf32-v850.c:2369 +#, fuzzy, c-format +msgid "v850e2v3 architecture" +msgstr "v850e アーキテクãƒãƒ£" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:534 +#, fuzzy, c-format +msgid " [d-float]" +msgstr "浮動å°æ•°" + +#: elf32-vax.c:537 +#, fuzzy, c-format +msgid " [g-float]" +msgstr "浮動å°æ•°" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "" + +#: elf32-vax.c:1587 +#, fuzzy, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf32-vax.c:1714 +#, fuzzy, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf32-vax.c:1720 +#, fuzzy, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +#, fuzzy +msgid "dynamic relocation in read-only section" +msgstr "%s: ローダå†é…ç½®ãŒèª­è¾¼ã¿å°‚用セクション %s ã«ã‚ã‚Šã¾ã™" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:9024 +#, fuzzy +msgid "invalid relocation address" +msgstr "%s: å†é…置タイプ %d ã¯ä¸é©åˆ‡ã§ã™" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP å†é…置㌠ldah 㨠lda 命令を見ã¤ã‘ã¾ã›ã‚“ã§ã—ãŸ" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: .got サブセグメント㌠64K を超ãˆã¦ã„ã¾ã™ (サイズ %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +#, fuzzy +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +#, fuzzy +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "" + +#: elf64-alpha.c:4395 +#, fuzzy +msgid "" +msgstr "*ä¸ æ˜Ž*" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "" + +#: elf64-alpha.c:4452 +#, fuzzy +msgid "%B: unhandled dynamic relocation against %s" +msgstr "å†é…ç½® %s ãŒå–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: elf64-alpha.c:4484 +#, fuzzy +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "GP 関連ã®å†é…置㌠_gp ãŒæœªå®šç¾©ã®æ™‚点ã§ç¾ã‚Œã¾ã—ãŸ" + +#: elf64-alpha.c:4544 +#, fuzzy +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf64-alpha.c:4567 +#, fuzzy +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "32ビット gp 関連å†é…ç½®ãŒå¤–部シンボルã®ç”¨ã«ç™ºç”Ÿã—ã¾ã—ãŸ" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "" + +#: elf64-hppa.c:3299 +#, fuzzy +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%s(%s+0x%lx): %s (%s) ã‚’å–り扱ãˆã¾ã›ã‚“" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1612 +#, fuzzy, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1661 +#, fuzzy, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: 警告: シンボル `%s' (%s セクション)ã«å¯¾ã™ã‚‹å†é…置を解決ã§ãã¾ã›ã‚“" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "" + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "" + +#: elf64-mmix.c:2248 +#, fuzzy +msgid "Register section has contents\n" +msgstr "セクションã«å†…容ãŒã‚ã‚Šã¾ã›ã‚“" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" + +#: elf64-ppc.c:2741 libbfd.c:997 +#, fuzzy +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%s: ビッグエンディアンシステム用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆãŒãƒªãƒˆãƒ«ã‚¨ãƒ³ãƒ‡ã‚£ã‚¢ãƒ³ã§ã™" + +#: elf64-ppc.c:2744 libbfd.c:999 +#, fuzzy +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%s: リトルエンディアンシステム用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆãŒãƒ“ッグエンディアンã§ã™ã€‚" + +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:6901 +#, fuzzy +msgid "dynreloc miscount for %B, section %A" +msgstr "セクション %s 用ã¨ã—ã¦ã¯ãŠã‹ã—ãªå†é…置を検出ã—ã¾ã—ãŸ" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "" + +#: elf64-ppc.c:6994 +#, fuzzy +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%s: external 部分ã«ã‚ã‚‹ ATN タイプ %d ã¨ã„ã†ã®ã¯ã‚ã‚Šå¾—ã¾ã›ã‚“" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "" + +#: elf64-ppc.c:12919 +#, fuzzy +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%s: å†é…ç½® %s ã¯ã‚·ãƒ³ãƒœãƒ« %s 用ã®ã‚‚ã®ã¨ã—ã¦ã¯ã¾ã ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elf64-ppc.c:13096 +#, fuzzy +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "警告ã€.pdata セクションサイズ (%ld) ㌠%d ã®å€æ•°ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" + +#: elf64-sh64.c:1682 +#, fuzzy, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: ä¸æ­£ãªå†é…置タイプ %d ãŒã‚¢ãƒ‰ãƒ¬ã‚¹ 0x%lx ã§è¦‹ã¤ã‹ã‚Šã¾ã—ãŸ" + +#: elf64-sparc.c:444 +#, fuzzy +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s: STT_REGISTER を使ã†ã¨å®£è¨€ã§ãã‚‹ã®ã¯ãƒ¬ã‚¸ã‚¹ã‚¿ %%g[2367] ã ã‘ã§ã™" + +#: elf64-sparc.c:464 +#, fuzzy +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "レジスタ %%g%d ã¯çŸ›ç›¾ã—ã¦ä½¿ã‚ã‚Œã¾ã—ãŸ: 以å‰ã®å®£è¨€ã¯ %s 㧠%sã€%s 㧠%s ã¨å†å®šç¾©ã•ã‚Œã¾ã—ãŸ" + +#: elf64-sparc.c:487 +#, fuzzy +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "シンボル `%s' ã¯ç•°ãªã‚‹åž‹ã‚’æŒã£ã¦ã„ã¾ã™: %s 㧠REGISTER, ã§ã™ãŒ %s 㨠%s ã§å®šç¾©ã•ã‚Œã¦ã„ã¾ã™" + +#: elf64-sparc.c:532 +#, fuzzy +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "シンボル `%s' ã¯ç•°ãªã‚‹åž‹ã‚’ã‚‚ã£ã¦ã„ã¾ã™: 以å‰ã¯ %s, %s ã§ã¯ REGISTER" + +#: elf64-sparc.c:684 +#, fuzzy +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%s: UltraSPARC 特有ã®ã‚³ãƒ¼ãƒ‰ã¨ HAL 特有ã®ã‚³ãƒ¼ãƒ‰ã¨ã‚’リンクã—よã†ã¨ã—ã¦ã„ã¾ã™" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "" + +#: elf64-x86-64.c:3073 +#, fuzzy +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ã¦ã„る時点ã§ã¯åˆ©ç”¨ã§ãã¾ã›ã‚“" + +#: elf64-x86-64.c:3184 +#, fuzzy +msgid "; recompile with -fPIC" +msgstr "%s: æらã -fPIC を付ã‘ãšã«ã‚³ãƒ³ãƒ‘イルã—ãŸã®ã§ã¯ï¼Ÿ" + +#: elf64-x86-64.c:3189 +#, fuzzy +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ã¦ã„る時点ã§ã¯åˆ©ç”¨ã§ãã¾ã›ã‚“" + +#: elf64-x86-64.c:3191 +#, fuzzy +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%s: å†é…ç½® %s ã¯å…±æœ‰ã‚ªãƒ–ジェクトを作æˆã—ã¦ã„る時点ã§ã¯åˆ©ç”¨ã§ãã¾ã›ã‚“" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: ãƒãƒ¼ã‚¸ãƒ§ãƒ³ã‚«ã‚¦ãƒ³ãƒˆ (%ld) ãŒã‚·ãƒ³ãƒœãƒ«ã‚«ã‚¦ãƒ³ãƒˆ (%ld) ã¨ä¸€è‡´ã—ã¾ã›ã‚“" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "" + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "" + +#: elflink.c:1763 +#, fuzzy +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s: 警告: `%s' ã®å†å®šç¾©ã¯ã‚ã‚Šå¾—ãªã„ã“ã¨ã§ã™" + +#: elflink.c:2076 +#, fuzzy +msgid "%B: version node not found for symbol %s" +msgstr "%s: å†é…ç½® %s ã¯ã‚·ãƒ³ãƒœãƒ« %s 用ã®ã‚‚ã®ã¨ã—ã¦ã¯ã¾ã ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elflink.c:2166 +#, fuzzy +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%s: ä¸æ­£ãªå†é…置アドレス 0x%lx ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' 内ã«ã‚ã‚Šã¾ã™" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "警告: 動的シンボル `%s' ã®åž‹ã¨ã‚µã‚¤ã‚ºãŒå®šç¾©ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "" + +#: elflink.c:4050 +#, fuzzy +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%s: %s: ä¸é©åˆ‡ãªãƒãƒ¼ã‚¸ãƒ§ãƒ³ %u (最大 %d)" + +#: elflink.c:4086 +#, fuzzy +msgid "%B: %s: invalid needed version %d" +msgstr "%s: %s: å¿…è¦ã¨ã•ã‚Œã‚‹ãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d ãŒä¸é©åˆ‡ã§ã™" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "" + +#: elflink.c:4291 +#, fuzzy +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "警告: シンボル `%s' ã®ã‚µã‚¤ã‚ºãŒ %lu ã‹ã‚‰ %lu ã«å¤‰æ›´ã•ã‚Œã¾ã—㟠(%s 内)" + +#: elflink.c:4306 +#, fuzzy +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "警告: シンボル `%s' ã®ã‚µã‚¤ã‚ºãŒ %lu ã‹ã‚‰ %lu ã«å¤‰æ›´ã•ã‚Œã¾ã—㟠(%s 内)" + +#: elflink.c:4472 +#, fuzzy +msgid "%B: undefined reference to symbol '%s'" +msgstr "%s: シンボルå %s ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒæœªå®šç¾©ã§ã™" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "" + +#: elflink.c:5779 +#, fuzzy, c-format +msgid "%s: undefined version: %s" +msgstr "%s: シンボルå %s ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒæœªå®šç¾©ã§ã™" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "" + +#: elflink.c:7598 +#, fuzzy, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "%s: シンボルå %s ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒæœªå®šç¾©ã§ã™" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "" + +#: elflink.c:8754 +#, fuzzy +msgid "%B: could not find output section %A for input section %A" +msgstr "%s: 出力セクション %s (入力セクション %s 用) を見ã¤ã‘られã¾ã›ã‚“" + +#: elflink.c:8874 +#, fuzzy +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%s: クラス %d シンボル `%s' ã«è£œåŠ©ã‚¨ãƒ³ãƒˆãƒªãŒã‚ã‚Šã¾ã›ã‚“" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: 出力セクション %s ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“ã§ã—ãŸ" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "警告: %s セクションã®ã‚µã‚¤ã‚ºãŒ 0 ã§ã™" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: 警告: 共有オブジェクト内㫠DT_TEXTREL を作æˆã—ã¦ã„ã¾ã™\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: シンボルを読ã¿è¾¼ã‚ã¾ã›ã‚“: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "ファイル '%2$B' 内ã®ä½¿ç”¨ã•ã‚Œãªã„セクション '%1$s' を削除ã—ã¦ã„ã¾ã™" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "警告: gc-sections オプションã¯ç„¡è¦–ã•ã‚Œã¾ã—ãŸ" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: é‡è¤‡ã—ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%A' を無視ã—ã¦ã„ã¾ã™" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: é‡è¤‡ã—ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%A' ãŒç•°ãªã‚‹ã‚µã‚¤ã‚ºã§ã™" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: 警告: セクション `%A' ã®ä¸­èº«ã‚’読ã¿è¾¼ã‚ã¾ã›ã‚“" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: 警告: é‡è¤‡ã—ãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%A' ã®ä¸­èº«ãŒç•°ãªã‚Šã¾ã™" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "é™çš„プロシージャ(åå‰ç„¡ã—)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "" + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: セクション %s ã«å¯¾ã™ã‚‹ãŠã‹ã—ãªå†é…ç½®ãŒæ¤œå‡ºã•ã‚Œã¾ã—ãŸ" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "" + +#: elfxx-mips.c:7670 +#, fuzzy +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s: 0x%lx ã§ã® CALL16 å†é…ç½®ãŒå¤§åŸŸã‚·ãƒ³ãƒœãƒ«ã‚’対象ã¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: ä¸æ­£ãªã‚»ã‚¯ã‚·ãƒ§ãƒ³å `%s' ã§ã™" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:12613 +#, fuzzy +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%s: abicall ファイルã«éž abicall ファイルをリンクã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "" + +#: elfxx-mips.c:12658 +#, fuzzy +msgid "%B: linking %s module with previous %s modules" +msgstr "%s: ABI ãŒä¸€è‡´ã—ã¾ã›ã‚“ -- %s モジュールを以å‰ã® %s モジュールã¨ãƒªãƒ³ã‚¯ã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elfxx-mips.c:12681 +#, fuzzy +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s: ABI ãŒä¸€è‡´ã—ã¾ã›ã‚“ -- %s モジュールを以å‰ã® %s モジュールã¨ãƒªãƒ³ã‚¯ã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [abi unknown]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [abi ãŒã‚»ãƒƒãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [ä¸æ˜Žãª ISA]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [éž 32 ビットモード]" + +#: elfxx-sparc.c:595 +#, fuzzy, c-format +msgid "invalid relocation type %d" +msgstr "%s: å†é…置タイプ %d ã¯ä¸é©åˆ‡ã§ã™" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "出力ファイルã¯å…±æœ‰ãƒ©ã‚¤ãƒ–ラリ `%s' ã‚’å¿…è¦ã¨ã—ã¦ã„ã¾ã™\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "出力ファイルã¯å…±æœ‰ãƒ©ã‚¤ãƒ–ラリ `%s.so.%s' ã‚’å¿…è¦ã¨ã—ã¦ã„ã¾ã™\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "シンボル %s 㯠fixup 用ã«å®šç¾©ã•ã‚Œã¦ã„ã¾ã›ã‚“\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "警告: fixup カウントãŒä¸€è‡´ã—ã¾ã›ã‚“\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: 文字列ãŒé•·ã™ãŽã¾ã™ (%d 文字, 最大 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: シンボル `%s' フラグ 0x%x ã‚’èªè­˜ã§ãã¾ã›ã‚“" + +#: ieee.c:792 +#, fuzzy +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%s: ATI レコード %u (シンボル %u 用) ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: ieee.c:816 +#, fuzzy +msgid "%B: unexpected ATN type %d in external part" +msgstr "%s: external 部分ã«ã‚ã‚‹ ATN タイプ %d ã¨ã„ã†ã®ã¯ã‚ã‚Šå¾—ã¾ã›ã‚“" + +#: ieee.c:838 +#, fuzzy +msgid "%B: unexpected type after ATN" +msgstr "%s: ATN ã®å¾Œã‚ã«ã‚ã‚Šå¾—ãªã„タイプãŒã‚ã‚Šã¾ã™" + +#: ihex.c:230 +#, fuzzy +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%s:%d: Intel Hex ファイルã¨ã—ã¦ã‚ã‚Šå¾—ãªã„文字 `%s' ãŒã‚ã‚Šã¾ã™\n" + +#: ihex.c:337 +#, fuzzy +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s:%d: Intel Hex ファイルã®ãƒã‚§ãƒƒã‚¯ã‚µãƒ ãŒä¸æ­£ã§ã™ (%u ã®ç­ˆãŒ %u ã§ã™)" + +#: ihex.c:392 +#, fuzzy +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%s:%d: 拡張アドレスレコード長㌠Intel Hex ファイルã¨ã—ã¦ã¯ä¸æ­£ã§ã™" + +#: ihex.c:409 +#, fuzzy +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%s:%d: 拡張開始アドレス長㌠Intel Hex ファイルã¨ã—ã¦ã¯ä¸æ­£ã§ã™" + +#: ihex.c:426 +#, fuzzy +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s:%d: 拡張リニアアドレスレコード長㌠Intel Hex ファイルã¨ã—ã¦ä¸æ­£ã§ã™" + +#: ihex.c:443 +#, fuzzy +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s:%d: 拡張リニア開始アドレス帳㌠Intel Hex ファイルã¨ã—ã¦ã¯ä¸æ­£ã§ã™" + +#: ihex.c:460 +#, fuzzy +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%s:%d: Intel Hex ファイル㮠ihex タイプ %u ã‚’èªè­˜ã§ãã¾ã›ã‚“\n" + +#: ihex.c:579 +#, fuzzy +msgid "%B: internal error in ihex_read_section" +msgstr "%s: ihex_read_section 内ã§å†…部エラー" + +#: ihex.c:613 +#, fuzzy +msgid "%B: bad section length in ihex_read_section" +msgstr "%s: ihex_read_section 内ã§ä¸æ­£ãªã‚»ã‚¯ã‚·ãƒ§ãƒ³é•·ãŒã‚ã‚Šã¾ã™" + +#: ihex.c:826 +#, fuzzy, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: アドレス 0x%s 㯠Intel Hex ファイルã®ç¯„囲を超ãˆã¦ã„ã¾ã™" + +#: libbfd.c:863 +#, fuzzy +msgid "%B: unable to get decompressed section %A" +msgstr "Dwarf エラー: %s セクションを伸張ã§ãã¾ã›ã‚“。" + +#: libbfd.c:1027 +#, fuzzy, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "BFD 内部エラー。%s ã® %d 行目 %s ã§ä¸­æ–­ã—ã¾ã—ãŸ\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "" + +#: linker.c:2778 +#, fuzzy, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "入力 %s ã¨å‡ºåŠ› %s ã¨ã‚’å†é…ç½®å¯èƒ½ãƒªãƒ³ã‚¯ã—よã†ã¨ã—ã¾ã—ãŸ" + +#: linker.c:3105 +#, fuzzy +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%s: 0x%lx: 警告: シンボルãŒäºˆæœŸã›ã¬ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã«ã‚ã‚Šã¾ã™" + +#: linker.c:3119 +#, fuzzy +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%s: 警告: 確ä¿ã•ã‚ŒãŸã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' ãŒã‚»ã‚°ãƒ¡ãƒ³ãƒˆå†…ã«ã‚ã‚Šã¾ã›ã‚“" + +#: mach-o.c:3403 +#, fuzzy +msgid "Mach-O header:\n" +msgstr "" +"\n" +"ppcboot ヘッダ:\n" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr "" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr "" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr "" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr "" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr "" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr "" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr "" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr "" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr "" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr "" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "" + +#: mmo.c:456 +#, fuzzy, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: ä¸æ­£ãªã‚»ã‚¯ã‚·ãƒ§ãƒ³å `%s' ã§ã™" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "" + +#: mmo.c:3026 +#, fuzzy, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "警告: シンボル `%s' ã®åž‹ã¯ %d ã‹ã‚‰ %d ã«å¤‰æ›´ã•ã‚Œã¾ã—㟠(%s 内)" + +#: mmo.c:3078 +#, fuzzy, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: ihex_read_section 内ã§å†…部エラー" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: oasys ã§ã¯ã‚»ã‚¯ã‚·ãƒ§ãƒ³ `%s' を表ç¾ã§ãã¾ã›ã‚“" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "OSF/1 コアファイルセクションタイプ %d ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ\n" + +#: pe-mips.c:607 +#, fuzzy +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s: `ld -r' ã‚’ PE MIPS objects ã¨å…±ã«ä½¿ã†äº‹ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +#, fuzzy +msgid "%B: unimplemented %s\n" +msgstr "%s: 未実装㮠%s ã§ã™\n" + +#: pe-mips.c:745 +#, fuzzy +msgid "%B: jump too far away\n" +msgstr "%s: ジャンプ先ãŒé ã™ãŽã¾ã™\n" + +#: pe-mips.c:771 +#, fuzzy +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%s: ä¸æ­£ãª pair/reflo ㌠refhi ã®å¾Œã‚ã«ã‚ã‚Šã¾ã™\n" + +#: pei-x86_64.c:444 +#, fuzzy, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "警告ã€.pdata セクションサイズ (%ld) ㌠%d ã®å€æ•°ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"関数テーブル (.pdata セクションã®å†…容を解釈)\n" + +#: pei-x86_64.c:450 +#, fuzzy, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr " vma:\t\t\t開始アドレス 終了アドレス Unwind 情報\n" + +#. XXX code yet to be written. +#: peicode.h:751 +#, fuzzy +msgid "%B: Unhandled import type; %x" +msgstr "%s: import タイプ %x ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: peicode.h:756 +#, fuzzy +msgid "%B: Unrecognised import type; %x" +msgstr "%s: import タイプをèªè­˜ã§ãã¾ã›ã‚“ -- %x" + +#: peicode.h:770 +#, fuzzy +msgid "%B: Unrecognised import name type; %x" +msgstr "%s: import åå‰ã‚¿ã‚¤ãƒ—ã‚’èªè­˜ã§ãã¾ã›ã‚“ -- %x" + +#: peicode.h:1162 +#, fuzzy +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s: Import Library Format 書庫内ã®ãƒžã‚·ãƒ³ã‚¿ã‚¤ãƒ— (0x%x) ã‚’èªè­˜ã§ãã¾ã›ã‚“" + +#: peicode.h:1174 +#, fuzzy +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s: Import Library Format 書庫内ã®ãƒžã‚·ãƒ³ã‚¿ã‚¤ãƒ— (0x%x) ã¯èªè­˜ã§ãã¾ã—ãŸãŒå–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: peicode.h:1192 +#, fuzzy +msgid "%B: size field is zero in Import Library Format header" +msgstr "%s: Import Library Format ヘッダ内ã®ã‚µã‚¤ã‚ºãƒ•ã‚£ãƒ¼ãƒ«ãƒ‰ãŒã‚¼ãƒ­ã§ã™" + +#: peicode.h:1223 +#, fuzzy +msgid "%B: string not null terminated in ILF object file." +msgstr "%s: ILF オブジェクトファイル内ã®æ–‡å­—列㌠null 終端ã•ã‚Œã¦ã„ã¾ã›ã‚“。" + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot ヘッダ:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "エントリオフセット = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "é•·ã• = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "フラグフィールド = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "領域å = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"領域[%d] ã®é–‹å§‹ = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "領域[%d] ã®æœ«å°¾ = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "領域[%d] セクタ = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "領域[%d] é•·ã• = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers ã¯æœªå®Ÿè£…ã§ã™" + +#: srec.c:261 +#, fuzzy +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d: `%s' 㯠S-record ファイル内ã«ã¯ã‚ã‚Šå¾—ãªã„文字ã§ã™\n" + +#: srec.c:567 srec.c:600 +#, fuzzy +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%s:%d: `%s' 㯠S-record ファイル内ã«ã¯ã‚ã‚Šå¾—ãªã„文字ã§ã™\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "" + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr ".stab å†é…ç½®ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:1287 +#, fuzzy, c-format +msgid "Unknown EGSD subtype %d" +msgstr "ä¸æ˜Žãª gsd/egsd サブタイプ %d ã§ã™" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "_bfd_vms_push ã§ã‚¹ã‚¿ãƒƒã‚¯ã‚ªãƒ¼ãƒãƒ¼ãƒ•ãƒ­ãƒ¼(%d)ã—ã¾ã—ãŸ" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "_bfd_vms_pop ã§ã‚¹ã‚¿ãƒƒã‚¯ã‚¢ãƒ³ãƒ€ãƒ¼ãƒ•ãƒ­ãƒ¼ã—ã¾ã—ãŸ" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "" + +#: vms-alpha.c:1755 +#, fuzzy, c-format +msgid "bad section index in %s" +msgstr "ETIR_S_C_STA_PQ ã«ã‚るセクションインデックスãŒä¸æ­£ã§ã™" + +#: vms-alpha.c:1768 +#, fuzzy, c-format +msgid "unsupported STA cmd %s" +msgstr "STA cmd %d ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, fuzzy, c-format +msgid "%s: not supported" +msgstr "サãƒãƒ¼ãƒˆã—ã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:1950 +#, fuzzy, c-format +msgid "%s: not implemented" +msgstr "%s: 未実装㮠%s ã§ã™\n" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "" + +#: vms-alpha.c:2240 +#, fuzzy, c-format +msgid "reserved cmd %d" +msgstr "STA cmd %d ã¯äºˆç´„済ã§ã™" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "オブジェクトモジュールãŒã‚¨ãƒ©ãƒ¼ãƒ•ãƒªãƒ¼ã§ã¯ã‚ã‚Šã¾ã›ã‚“!\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "シンボル %s 㯠%s ã§ç½®ãæ›ãˆã‚‰ã‚Œã¾ã—ãŸ\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ %s ã«ã‚ã‚Šã¾ã™ãŒå†é…ç½®ãŒã‚ã‚Šã¾ã›ã‚“" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, fuzzy, c-format +msgid "Size error in section %s" +msgstr "SEC_RELOC ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ %s ã«ã‚ã‚Šã¾ã™ãŒå†é…ç½®ãŒã‚ã‚Šã¾ã›ã‚“" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "å†é…ç½® %s ãŒå–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "" + +#: vms-alpha.c:4379 +#, fuzzy +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4385 +#, fuzzy +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4391 +#, fuzzy +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4397 +#, fuzzy +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4403 +#, fuzzy +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4430 +#, fuzzy +msgid "DST__K_SET_PC not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4436 +#, fuzzy +msgid "DST__K_SET_PC_W not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4442 +#, fuzzy +msgid "DST__K_SET_PC_L not implemented" +msgstr "ETIR_S_C_STO_HINT_GBL: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4448 +#, fuzzy +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "ETIR_S_C_STO_HINT_PS: 実装ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, fuzzy, c-format +msgid "Unknown reloc %s + %s" +msgstr "å†é…ç½® %s を無視ã—ã¾ã™\n" + +#: vms-alpha.c:5074 +#, fuzzy, c-format +msgid "Unknown reloc %s" +msgstr "å†é…ç½® %s を無視ã—ã¾ã™\n" + +#: vms-alpha.c:5087 +#, fuzzy +msgid "Invalid section index in ETIR" +msgstr "ETIR_S_C_STA_PQ ã«ã‚るセクションインデックスãŒä¸æ­£ã§ã™" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr "" + +#: vms-alpha.c:5658 +#, fuzzy, c-format +msgid "Module header\n" +msgstr "" +"\n" +"ppcboot ヘッダ:\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr "" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr "" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5665 +#, fuzzy, c-format +msgid " module version : %.*s\n" +msgstr "%s: シンボルå %s ã®ãƒãƒ¼ã‚¸ãƒ§ãƒ³ãŒæœªå®šç¾©ã§ã™" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr "" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr "" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr "" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr "" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr "" + +#: vms-alpha.c:5703 +#, fuzzy, c-format +msgid "unhandled emh subtype %u\n" +msgstr "%s: import タイプ %x ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr "" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr "" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr "" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr "" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr "" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr "" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr "" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr "" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr "" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr "" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr "" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr "" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr "" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr "" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr "" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr "" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr "" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr "" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr "" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr "" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr "" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr "" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr "" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr "" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr "" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr "" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr "" + +#: vms-alpha.c:5810 +#, fuzzy, c-format +msgid "PSC - Program section definition\n" +msgstr "" +"\n" +"ãƒãƒ¼ã‚¸ãƒ§ãƒ³å®šç¾©:\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr "" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr "" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr "" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, fuzzy, c-format +msgid " name : %.*s\n" +msgstr "領域å = \"%s\"\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr "" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5838 +#, fuzzy, c-format +msgid " name : %.*s\n" +msgstr "フラグフィールド = 0x%.2x\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr "" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr "" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, fuzzy, c-format +msgid " psect index : %u\n" +msgstr "ETIR_S_C_STA_PQ ã«ã‚るセクションインデックスãŒä¸æ­£ã§ã™" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, fuzzy, c-format +msgid " name : %.*s\n" +msgstr "領域å = \"%s\"\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "" + +#: vms-alpha.c:5886 +#, fuzzy, c-format +msgid " flags : 0x%08x" +msgstr "フラグフィールド = 0x%.2x\n" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr "" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr "" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr "" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5917 +#, fuzzy, c-format +msgid " entry point: 0x%08x\n" +msgstr " [エントリãƒã‚¤ãƒ³ãƒˆã‚’æŒã£ã¦ã„ã¾ã™]" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5921 +#, fuzzy, c-format +msgid " psect index: %u\n" +msgstr "ETIR_S_C_STA_PQ ã«ã‚るセクションインデックスãŒä¸æ­£ã§ã™" + +#: vms-alpha.c:5932 +#, fuzzy, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "" +"\n" +"ãƒãƒ¼ã‚¸ãƒ§ãƒ³å®šç¾©:\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr "" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr "" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr "" + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr "" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr "" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr "" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr "" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "" + +#: vms-alpha.c:6408 +#, fuzzy, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr "%s: import タイプ %x ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr "" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr "" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr "" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr "" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr "" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "" + +#: vms-alpha.c:6715 +#, fuzzy, c-format +msgid "(no value)\n" +msgstr "ä¸æ­£ãªå€¤ã§ã™" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "" + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "" + +#: vms-alpha.c:6747 +#, fuzzy +msgid "address" +msgstr "テーブルアドレス\n" + +#: vms-alpha.c:6750 +#, fuzzy +msgid "desc" +msgstr "サãƒãƒ¼ãƒˆã—ã¦ã„ã¾ã™" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "デãƒãƒƒã‚°ã‚·ãƒ³ãƒœãƒ«è¡¨:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr "" + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, fuzzy, c-format +msgid " name: %.*s\n" +msgstr "" +"\n" +" åž‹: %s" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr "" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr "" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr "" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr "" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr "" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr "" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr "" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr "" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr "" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr "" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr "" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr "" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr "" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr "" + +#: vms-alpha.c:7240 +#, fuzzy, c-format +msgid "*unhandled* dst type %u\n" +msgstr "%s: import タイプ %x ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr "" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr "" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr "" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr "" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr "" + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr "" + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr "" + +#: vms-alpha.c:7335 +#, fuzzy, c-format +msgid " linker flags: %08x:" +msgstr "private フラグ = %x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr "" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr "" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr "" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr "" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr "" + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "" + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "" + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "" + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "" + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "" + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "" + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "" + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "" + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "" + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "" + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "" + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "" + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "" + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "" + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "" + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "" + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "" + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "" + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "" + +#: vms-alpha.c:7469 +#, fuzzy +msgid "*unknown* " +msgstr "*ä¸æ˜Ž*" + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr "" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7519 +#, fuzzy, c-format +msgid " image name : %.*s\n" +msgstr "領域å = \"%s\"\n" + +#: vms-alpha.c:7521 +#, fuzzy, c-format +msgid " link time : %s\n" +msgstr "領域å = \"%s\"\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr "" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr "" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr "" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr "" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr "" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7588 +#, fuzzy, c-format +msgid " flags: 0x%04x" +msgstr "private フラグ = 0x%lx" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr "" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr "" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr "" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "大域シンボル表:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr "" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr "" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr "" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr "" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr "" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr "" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr "" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr "" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr "" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr "" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr "" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr "" + +#: vms-alpha.c:7805 +#, fuzzy, c-format +msgid " quad-word relocation fixups:\n" +msgstr "å†é…ç½® %s ãŒå–り扱ã‚ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr "" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr "" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr "" + +#: vms-alpha.c:7825 +#, fuzzy, c-format +msgid " Code Address Reference Fixups:\n" +msgstr "" +"\n" +"ãƒãƒ¼ã‚¸ãƒ§ãƒ³å‚ç…§:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr "" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr "" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr "" + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +#, fuzzy +msgid "%P: relocatable link is not supported\n" +msgstr "%s: %s ã‹ã‚‰ %s ã¸ã®å†é…ç½®å¯èƒ½ãƒªãƒ³ã‚¯ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted ãŒã‚¼ãƒ­ãƒã‚¤ãƒˆã§å‘¼ã³å‡ºã•ã‚Œã¾ã—ãŸ" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted 呼ã³å‡ºã—時ã®ãƒã‚¤ãƒˆæ•°ãŒå¤§ãã™ãŽã¾ã™" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF ㌠XCOFF 出力生æˆæ™‚以外ã«ã‚ªãƒ–ジェクトを共有ã—ã¾ã—ãŸ" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: 動的オブジェクト㫠.loader セクションãŒã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:1415 +#, fuzzy +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%s: `%s' ã¯è¡Œç•ªå·ã‚’æŒã¡ã¾ã™ãŒã€ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã‚’囲ã„込んã§ã„ã¾ã›ã‚“" + +#: xcofflink.c:1467 +#, fuzzy +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%s: クラス %d シンボル `%s' ã«è£œåŠ©ã‚¨ãƒ³ãƒˆãƒªãŒã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:1489 +#, fuzzy +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%s: シンボル `%s' ãŒèªè­˜ã§ããªã„ csect タイプ %d ã‚’æŒã£ã¦ã„ã¾ã™" + +#: xcofflink.c:1501 +#, fuzzy +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s: ä¸æ­£ XTY_ER シンボル `%s': クラス %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +#, fuzzy +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s: XMC_TC0 シンボル `%s' 㯠class %d scnlen %d ã§ã™" + +#: xcofflink.c:1676 +#, fuzzy +msgid "%B: csect `%s' not in enclosing section" +msgstr "%s: csect `%s' ãŒã‚»ã‚¯ã‚·ãƒ§ãƒ³ã®å›²ã¿ã®ä¸­ã«ã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:1783 +#, fuzzy +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%s: XTY_LD `%s' ã‚’ç½®ãé•ãˆã¦ã„ã¾ã™" + +#: xcofflink.c:2102 +#, fuzzy +msgid "%B: reloc %s:%d not in csect" +msgstr "%s: å†é…ç½® %s:%d ㌠csect 内ã«ã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: ãã®ã‚ˆã†ãªã‚·ãƒ³ãƒœãƒ«ã¯ã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "警告: 未定義シンボル `%s' ã‚’ export ã—よã†ã¨ã—ã¦ã„ã¾ã™" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "" + +#: xcofflink.c:4052 +#, fuzzy +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%s: ローダå†é…ç½®ãŒèªè­˜ã§ããªã„セクション `%s' ã«ã‚ã‚Šã¾ã™" + +#: xcofflink.c:4063 +#, fuzzy +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%s: `%s' ãŒãƒ­ãƒ¼ãƒ€å†é…ç½®ã«ã‚ã‚Šã¾ã™ãŒãƒ­ãƒ¼ãƒ€ã‚·ãƒ³ãƒœãƒ«ã§ã¯ã‚ã‚Šã¾ã›ã‚“" + +#: xcofflink.c:4079 +#, fuzzy +msgid "%B: loader reloc in read-only section %A" +msgstr "%s: ローダå†é…ç½®ãŒèª­è¾¼ã¿å°‚用セクション %s ã«ã‚ã‚Šã¾ã™" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "TOC オーãƒãƒ¼ãƒ•ãƒ­ãƒ¼: 0x%lx > 0x10000 -- コンパイル時㫠-mminimal-toc を試ã—ã¾ã—ょã†" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "" + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +#, fuzzy +msgid "@pltoff reloc against local symbol" +msgstr "%s: 0x%lx ã§ã® CALL16 å†é…ç½®ãŒå¤§åŸŸã‚·ãƒ³ãƒœãƒ«ã‚’対象ã¨ã—ã¦ã„ã¾ã›ã‚“" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +#, fuzzy +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%s: å†é…置タイプ %d (シンボル %s) ãŒä¸æ˜Žã§ã™" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +#, fuzzy +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%s: å†é…置タイプ %d (シンボル %s) ãŒä¸æ˜Žã§ã™" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +#, fuzzy +msgid "unsupported reloc" +msgstr "サãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ãªã„å†é…置タイプã§ã™" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "" + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "" + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +#, fuzzy +msgid "%B: linking big-endian files with little-endian files" +msgstr "%s: リトルエンディアンã®ãƒ•ã‚¡ã‚¤ãƒ«ã¨ãƒ“ッグエンディアンã®ãƒ•ã‚¡ã‚¤ãƒ«ã¨ã‚’リンクã—よã†ã¨ã—ã¦ã„ã¾ã™" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +#, fuzzy +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%s: abicall ファイルã«éž abicall ファイルをリンクã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +#, fuzzy +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%s: abicall ファイルã«éž abicall ファイルをリンクã—よã†ã¨ã—ã¾ã—ãŸ" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +#, fuzzy +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%s: abicall ファイルã«éž abicall ファイルをリンクã—よã†ã¨ã—ã¾ã—ãŸ" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: 行番å·ãŒã‚ªãƒ¼ãƒãƒ¼ãƒ•ãƒ­ãƒ¼ã—ã¾ã—ãŸ: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Export ディレクトリ [.edata (或ã„ã¯ã“ã“ã¾ã§ã«è¦‹ã¤ã‘ãŸå ´æ‰€)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Import ディレクトリ [.idata ã®éƒ¨åˆ†]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "リソースディレクトリ [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "例外ディレクトリ [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "セキュリティディレクトリ" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "基本å†é…置ディレクトリ [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "デãƒãƒƒã‚°ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "記述å­ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "スペシャルディレクトリ" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "スレッド記憶ディレクトリ [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "ロード設定ディレクトリ" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "境界 Import ディレクトリ" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "インãƒãƒ¼ãƒˆã‚¢ãƒ‰ãƒ¬ã‚¹è¡¨ãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "é…延インãƒãƒ¼ãƒˆãƒ‡ã‚£ãƒ¬ã‚¯ãƒˆãƒª" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "予約済" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"インãƒãƒ¼ãƒˆè¡¨ãŒã‚ã‚Šã¾ã™ãŒã€ã“ã“ã‚’å«ã‚“ã§ã„るセクションを見ã¤ã‘られã¾ã›ã‚“ã§ã—ãŸ\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s 内㮠0x%lx ã«ã‚ã‚‹ import テーブルã§ã™\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"関数記述å­ã¯é–‹å§‹ã‚¢ãƒ‰ãƒ¬ã‚¹ã«ä½ç½®ã—ã¦ã„ã¾ã™: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tコードベース %08lx toc (loadable/actual) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"reldata セクションãŒã‚ã‚Šã¾ã›ã‚“! 関数記述å­ãŒãƒ‡ã‚³ãƒ¼ãƒ‰ã•ã‚Œã¾ã›ã‚“ã§ã—ãŸã€‚\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Import テーブル (%s セクションã®å†…容を解釈)\n" + +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, fuzzy, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr " vma: Hint Time Forward DLL First\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL å: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, fuzzy, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Hint/Ord メンãƒå\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, fuzzy, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"import テーブルãŒã‚ã‚Šã¾ã™ãŒã€ã“ã“ã‚’å«ã‚“ã§ã„るセクションを見ã¤ã‘られã¾ã›ã‚“ã§ã—ãŸ\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"export テーブルãŒã‚ã‚Šã¾ã™ãŒã€ã“れをå«ã‚“ã§ã„るセクションを見ã¤ã‘られã¾ã›ã‚“ã§ã—ãŸ\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, fuzzy, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"export テーブルãŒã‚ã‚Šã¾ã™ãŒã€ã“れをå«ã‚“ã§ã„るセクションを見ã¤ã‘られã¾ã›ã‚“ã§ã—ãŸ\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s ã® 0x%lx ã« export テーブルãŒã‚ã‚Šã¾ã™\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Export テーブル (%s セクションã®å†…容を解釈)\n" +"\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Export フラグ \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "時刻/日付スタンプ \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Major/Minor \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "åå‰ \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "åºæ•°ãƒ™ãƒ¼ã‚¹ \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "å„種ã®æ•°å€¤:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tExport アドレステーブル\t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[åå‰ãƒã‚¤ãƒ³ã‚¿/åºæ•°] テーブル\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "テーブルアドレス\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tExport アドレステーブル\t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tåå‰ãƒã‚¤ãƒ³ã‚¿ãƒ†ãƒ¼ãƒ–ル \t\t" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tåºæ•°ãƒ†ãƒ¼ãƒ–ル \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Export アドレステーブル -- åºæ•°ãƒ™ãƒ¼ã‚¹ %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "Forwarder RVA" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "Export RVA" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[åºæ•°/åå‰ãƒã‚¤ãƒ³ã‚¿] テーブル\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "警告ã€.pdata セクションサイズ (%ld) ㌠%d ã®å€æ•°ã§ã¯ã‚ã‚Šã¾ã›ã‚“\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\t開始アドレス 終了アドレス Unwind 情報\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, fuzzy, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr " vma:\t\t開始 終了 EH EH PrologEnd 例外\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " レジスタä¿å­˜ãƒŸãƒªã‚³ãƒ¼ãƒ‰" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " レジスタ復元ミリコード" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " グルーコード列" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"PE ファイルベースå†é…ç½® (.reloc セクションã®å†…容を解釈)\n" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"仮想アドレス: %08lx ãƒãƒ£ãƒ³ã‚¯ã‚µã‚¤ã‚º %ld (0x%lx) fixups ã®å€‹æ•° %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\treloc %4d オフセット %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"固有 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "" + +#~ msgid "Can't Make it a Short Jump" +#~ msgstr "短ã„ジャンプを行ã†ã“ã¨ãŒã§ãã¾ã›ã‚“" + +#~ msgid "Exceeds Long Jump Range" +#~ msgstr "é•·ã„ジャンプã®ç¯„囲を超ãˆã¦ã„ã¾ã™" + +#~ msgid "Absolute address Exceeds 16 bit Range" +#~ msgstr "絶対アドレス㌠16 bit ã®ç¯„囲を超ãˆã¦ã„ã¾ã™" + +#~ msgid "Absolute address Exceeds 8 bit Range" +#~ msgstr "絶対アドレス㌠8 bit ã®ç¯„囲を超ãˆã¦ã„ã¾ã™" + +#~ msgid "Unrecognized Reloc Type" +#~ msgstr "èªè­˜ã§ããªã„å†é…置型ã§ã™" + +#, fuzzy +#~ msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%s: %s+0x%lx: jal ã§ã¯ãªã„スタブルーãƒãƒ³ã¸ã®ã‚¸ãƒ£ãƒ³ãƒ—ã§ã™" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "bfd_make_section (%s) ãŒå¤±æ•—ã—ã¾ã—ãŸ" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) ãŒå¤±æ•—ã—ã¾ã—ãŸ" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "セクション %s=%lx, %s=%lx ã§ã‚µã‚¤ã‚ºãŒä¸€è‡´ã—ã¾ã›ã‚“" + +#~ msgid "failed to enter %s" +#~ msgstr "%s ã¸å…¥ã‚Œã¾ã›ã‚“ã§ã—ãŸ" + +#~ msgid "No Mem !" +#~ msgstr "メモリãŒã‚ã‚Šã¾ã›ã‚“!" + +#, fuzzy +#~ msgid "reserved STO cmd %d" +#~ msgstr "STO cmd %d ã¯äºˆç´„済ã§ã™" + +#, fuzzy +#~ msgid "reserved OPR cmd %d" +#~ msgstr "OPR cmd %d ã¯äºˆç´„済ã§ã™" + +#, fuzzy +#~ msgid "reserved CTL cmd %d" +#~ msgstr "CTL cmd %d ã¯äºˆç´„済ã§ã™" + +#, fuzzy +#~ msgid "reserved STC cmd %d" +#~ msgstr "STA cmd %d ã¯äºˆç´„済ã§ã™" + +#, fuzzy +#~ msgid "stack-from-image not implemented" +#~ msgstr "Stack-from-image ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "Stack-entry-mask ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#~ msgid "PASSMECH not fully implemented" +#~ msgstr "PASSMECH ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "Stack-local-symbol ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "stack-literal not fully implemented" +#~ msgstr "Stack-literal ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "Stack-local-symbol-entry-point-mask ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "%s: not fully implemented" +#~ msgstr "PASSMECH ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#, fuzzy +#~ msgid "obj code %d not found" +#~ msgstr "オブジェクトコード %d ãŒè¦‹ã¤ã‹ã‚Šã¾ã›ã‚“" + +#, fuzzy +#~ msgid "Reloc size error in section %s" +#~ msgstr "%s: ローダå†é…ç½®ãŒèª­è¾¼ã¿å°‚用セクション %s ã«ã‚ã‚Šã¾ã™" + +#~ msgid "Missing IHCONST" +#~ msgstr "IHCONST を欠ã„ã¦ã„ã¾ã™" + +#~ msgid "Missing IHIHALF" +#~ msgstr "IHIHALF を欠ã„ã¦ã„ã¾ã™" + +#~ msgid "missing IHCONST reloc" +#~ msgstr "IHCONST å†é…置を欠ã„ã¦ã„ã¾ã™" + +#~ msgid "missing IHIHALF reloc" +#~ msgstr "IHIHALF å†é…置を欠ã„ã¦ã„ã¾ã™" + +#~ msgid "GP relative relocation when GP not defined" +#~ msgstr "GP ãŒæœªå®šç¾©ã®æ™‚ã® GP 関連å†é…ç½®ã§ã™" + +#~ msgid " first occurrence: %s: arm call to thumb" +#~ msgstr " åˆå›žç™ºç”Ÿ: %s: arm ã® thumb 呼ã³å‡ºã—" + +#~ msgid " first occurrence: %s: thumb call to arm" +#~ msgstr " åˆå›žç™ºç”Ÿ: %s: thumb ã® arm 呼ã³å‡ºã—" + +#~ msgid " consider relinking with --support-old-code enabled" +#~ msgstr " --support-old-code を有効ã«ã—ã¦å†ãƒªãƒ³ã‚¯ã™ã‚‹ã“ã¨ã‚’考慮ã—ã¦ã¿ã¦ãã ã•ã„" + +#~ msgid "%s: ERROR: passes floats in float registers whereas target %s uses integer registers" +#~ msgstr "%s: エラー: 浮動å°æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã«æµ®å‹•å°æ•°ã‚’渡ã—ã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆ %s ãŒæ•´æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã‚’使ã£ã¦ã„ã¾ã™" + +#~ msgid "%s: ERROR: passes floats in integer registers whereas target %s uses float registers" +#~ msgstr "%s: エラー: 整数レジスタã«æµ®å‹•å°æ•°ã‚’渡ã—ã¦ã„ã‚‹ã«ã‚‚ã‹ã‹ã‚らãšã€ã‚¿ãƒ¼ã‚²ãƒƒãƒˆ %s ã¯æµ®å‹•å°æ•°ãƒ¬ã‚¸ã‚¹ã‚¿ã‚’使ã£ã¦ã„ã¾ã™" + +#~ msgid "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" +#~ msgstr "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" + +#~ msgid "reloc against unsupported section" +#~ msgstr "サãƒãƒ¼ãƒˆå¤–ã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ã«å¯¾ã™ã‚‹å†é…ç½®ã§ã™" + +#~ msgid "Dwarf Error: Can't find .debug_abbrev section." +#~ msgstr "Dwarf エラー: .debug_abbrev セクションを見ã¤ã‘られã¾ã›ã‚“。" + +#~ msgid "Dwarf Error: Abbrev offset (%u) bigger than abbrev size (%u)." +#~ msgstr "Dwarf エラー: abbrev オフセット (%u) ㌠abbrev サイズ (%u) より大ãã„ã§ã™ã€‚" + +#~ msgid "Warning: Not setting interwork flag of %s since it has already been specified as non-interworking" +#~ msgstr "警告: éž interworking ã¨æ—¢ã«æŒ‡å®šã•ã‚Œã¦ã„ã‚‹ãŸã‚ã€%s ã® interwork フラグをセットã—ã¾ã›ã‚“" + +#~ msgid "Warning: Clearing the interwork flag of %s due to outside request" +#~ msgstr "警告: è¦æ±‚外ã®ãŸã‚ %s ã® interwork フラグをクリアã—ã¾ã™" + +#~ msgid "Error: %s compiled for EABI version %d, whereas %s is compiled for version %d" +#~ msgstr "エラー: %s 㯠EABI ãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d 用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚ŒãŸã«ã‚‚ã‹ã‹ã‚らãšã€%s ãŒãƒãƒ¼ã‚¸ãƒ§ãƒ³ %d 用ã«ã‚³ãƒ³ãƒ‘イルã•ã‚Œã¾ã—ãŸ" + +#~ msgid "integer" +#~ msgstr "æ•´æ•°" + +#~ msgid "soft" +#~ msgstr "ソフト" + +#~ msgid "hard" +#~ msgstr "ãƒãƒ¼ãƒ‰" + +#~ msgid "Warning: %s %s interworking, whereas %s %s" +#~ msgstr "警告: %s 㯠interworking ã‚’%sã«ã‚‚ã‹ã‹ã‚らãšã€%s ãŒ%s" + +#~ msgid "supports" +#~ msgstr "サãƒãƒ¼ãƒˆã—ã¦ã„ã‚‹" + +#~ msgid "does not" +#~ msgstr "サãƒãƒ¼ãƒˆã—ã¦ã„ã¾ã›ã‚“" + +#~ msgid " [APCS-26]" +#~ msgstr " [APCS-26]" + +#~ msgid " [APCS-32]" +#~ msgstr " [APCS-32]" + +#~ msgid "%s(%s+0x%lx): cannot find stub entry %s" +#~ msgstr "%s(%s+0x%lx): スタブエントリ %s を見ã¤ã‘られã¾ã›ã‚“" + +#~ msgid "%s(%s+0x%lx): cannot relocate %s, recompile with -ffunction-sections" +#~ msgstr "%s(%s+0x%lx): %s ã‚’å†é…ç½®ã§ãã¾ã›ã‚“。-ffunction-sections を付ã‘ã¦å†ã‚³ãƒ³ãƒ‘イルã—ã¾ã—ょã†" + +#~ msgid "%s(%s+0x%lx): fixing %s" +#~ msgstr "%s(%s+0x%lx): %s を修復ã—ã¾ã™" + +#~ msgid "Linking mips16 objects into %s format is not supported" +#~ msgstr "%s å½¢å¼ã¸ã® mips16 オブジェクトをリンクã™ã‚‹ã“ã¨ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: ISA (-mips%d) ãŒä»¥å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« (-mips%d) ã¨ä¸€è‡´ã—ã¾ã›ã‚“" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: ISA (%d) ãŒä»¥å‰ã®ãƒ¢ã‚¸ãƒ¥ãƒ¼ãƒ« (%d) ã¨ä¸€è‡´ã—ã¾ã›ã‚“" + +#~ msgid " [mips1]" +#~ msgstr " [mips1]" + +#~ msgid " [mips2]" +#~ msgstr " [mips2]" + +#~ msgid " [mips3]" +#~ msgstr " [mips3]" + +#~ msgid " [mips4]" +#~ msgstr " [mips4]" + +#~ msgid " [mips5]" +#~ msgstr " [mips5]" + +#~ msgid " [mips32]" +#~ msgstr " [mips32]" + +#~ msgid " [mips64]" +#~ msgstr " [mips64]" + +#~ msgid " [32bitmode]" +#~ msgstr " [32ビットモード]" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: スペシャルリンカタイプ %d ãŒä¸æ˜Žã§ã™" + +#~ msgid "v850ea architecture" +#~ msgstr "v850ea アーキテクãƒãƒ£" + +#~ msgid "%s: check_relocs: unhandled reloc type %d" +#~ msgstr "%s: check_relocs: å†é…置タイプ %d ã¯å–り扱ã‚ã‚Œã¾ã›ã‚“" + +#~ msgid "creating section symbol, name = %s, value = 0x%.8lx, index = %d, section = 0x%.8lx\n" +#~ msgstr "セクションシンボルを作æˆã—ã¾ã™, åå‰ = %s, 値 = 0x%.8lx, 索引 = %d, セクション = 0x%.8lx\n" + +#~ msgid "%s: Not enough room for program headers (allocated %u, need %u)" +#~ msgstr "%s: プログラムヘッダ用ã®ç©ºé–“ãŒä¸å分ã§ã™ (確ä¿æ¸ˆ %u, è¦ %u)" + +#~ msgid "Error: First section in segment (%s) starts at 0x%x" +#~ msgstr "エラー: セグメント (%s) ã®æœ€åˆã®ã‚»ã‚¯ã‚·ãƒ§ãƒ³ãŒ 0x%x ã§å§‹ã¾ã£ã¦ã„ã‚‹" + +#~ msgid " whereas segment starts at 0x%x" +#~ msgstr " ã«ã‚‚ã‹ã‹ã‚らãšã€ã‚»ã‚°ãƒ¡ãƒ³ãƒˆãŒ 0x%x ã§å§‹ã¾ã£ã¦ã„ã¾ã™" + +#~ msgid "elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = 0x%.8lx%s\n" +#~ msgstr "elf_symbol_from_bfd_symbol 0x%.8lx, åå‰ = %s, ã‚·ãƒ³ãƒœãƒ«ç•ªå· = %d, フラグ = 0x%.8lx%s\n" + +#~ msgid "%s: Section %s is already to large to put hole of %ld bytes in" +#~ msgstr "%s: æ—¢ã«ã‚»ã‚¯ã‚·ãƒ§ãƒ³ %s ã¯å¤§ãã™ãŽã¦ %ld ãƒã‚¤ãƒˆã® hole ã‚’ç½®ã‘ã¾ã›ã‚“" + +#~ msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +#~ msgstr "%s: å†é…置領域ãŒã‚ªãƒ¼ãƒãƒ¼ãƒ•ãƒ­ãƒ¼ã—ã¾ã—㟠1: 0x%lx > 0xffff" + +#~ msgid " Table Stamp Chain Name Thunk\n" +#~ msgstr " Table Stamp Chain Name Thunk\n" + +#~ msgid "\tThe Import Address Table (difference found)\n" +#~ msgstr "\tImport アドレステーブル (差異を発見)\n" + +#~ msgid "\t>>> Ran out of IAT members!\n" +#~ msgstr "\t>>> IAT メンãƒã‚’追ã„出ã—ã¾ã—ãŸ!\n" + +#~ msgid "\tThe Import Address Table is identical\n" +#~ msgstr "\tImport Address Table ãŒå…¨ãåŒã˜ã§ã™\n" + +#~ msgid " \t\tAddress Address Handler Data Address Mask\n" +#~ msgstr " \t\tアドレス アドレス ãƒãƒ³ãƒ‰ãƒ© データ アドレス マスク\n" + +#~ msgid "ETIR_S_C_STO_GBL: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_GBL: シンボル \"%s\" ãŒã‚ã‚Šã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STO_CA: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_CA: シンボル \"%s\" ãŒã‚ã‚Šã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STO_RB/AB: Not supported" +#~ msgstr "ETIR_S_C_STO_RB/AB: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STO_LP_PSB: Not supported" +#~ msgstr "ETIR_S_C_STO_LP_PSB: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_OPR_INSV: Not supported" +#~ msgstr "ETIR_S_C_OPR_INSV: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_OPR_USH: Not supported" +#~ msgstr "ETIR_S_C_OPR_USH: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_OPR_ROT: Not supported" +#~ msgstr "ETIR_S_C_OPR_ROT: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_OPR_REDEF: Not supported" +#~ msgstr "ETIR_S_C_OPR_REDEF: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_OPR_DFLIT: Not supported" +#~ msgstr "ETIR_S_C_OPR_DFLIT: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STC_LP: not supported" +#~ msgstr "ETIR_S_C_STC_LP: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STC_GBL: not supported" +#~ msgstr "ETIR_S_C_STC_GBL: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STC_GCA: not supported" +#~ msgstr "ETIR_S_C_STC_GCA: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "ETIR_S_C_STC_PS: not supported" +#~ msgstr "ETIR_S_C_STC_PS: サãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "Unimplemented STO cmd %d" +#~ msgstr "STO cmd %d ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#~ msgid "TIR_S_C_OPR_ASH incomplete" +#~ msgstr "TIR_S_C_OPR_ASH ã¯ä¸å®Œå…¨ã§ã™" + +#~ msgid "TIR_S_C_OPR_USH incomplete" +#~ msgstr "TIR_S_C_OPR_USH ã¯ä¸å®Œå…¨ã§ã™" + +#~ msgid "TIR_S_C_OPR_ROT incomplete" +#~ msgstr "TIR_S_C_OPR_ROT ã¯ä¸å®Œå…¨ã§ã™" + +#~ msgid "TIR_S_C_OPR_REDEF not supported" +#~ msgstr "TIR_S_C_OPR_REDEF ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "TIR_S_C_OPR_DFLIT not supported" +#~ msgstr "TIR_S_C_OPR_DFLIT ã¯ã‚µãƒãƒ¼ãƒˆã•ã‚Œã¾ã›ã‚“" + +#~ msgid "TIR_S_C_CTL_DFLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_DFLOC ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#~ msgid "TIR_S_C_CTL_STLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_STLOC ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" + +#~ msgid "TIR_S_C_CTL_STKDL not fully implemented" +#~ msgstr "TIR_S_C_CTL_STKDL ã¯å®Œå…¨ã«ã¯å®Ÿè£…ã•ã‚Œã¦ã„ã¾ã›ã‚“" diff --git a/external/gpl3/gdb/dist/bfd/po/ro.gmo b/external/gpl3/gdb/dist/bfd/po/ro.gmo new file mode 100644 index 0000000000000000000000000000000000000000..8621928313f63e511869ba9208f233c78692a777 GIT binary patch literal 69038 zcmcJ&37ni&mHuC#qb4HCrmXq~Xy}G?XConW2#`I&Y^FPa0w&enl}dYu^qvASByUvWbj_XYPf1h*ieV3~0Ea<;KdGpkL-@D&) z&pr3t<$U+}`@gKj-(!w0l}-oWbbP6F#{EjAxm|i&D!qO|sdO^<2Jn&K?cl?~Z-96$ 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zqNyyPQg_lfOIPMEWdgPBrL16fc)6wcvV$qq;+X}keYV;{?X2T1;)8fr&s()luEt9&#O|c(Dg5P|$x3A>oS*QbVfQ zKx9N_q(fPA<4sDI`Im}@ggbo8C_U$&QplDEI*#difdPdM!l+X#MY&EW3s2zLH&nabAS?D4I@|pdB_d`0fAGoi!vFvP literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/bfd/po/ro.po b/external/gpl3/gdb/dist/bfd/po/ro.po new file mode 100644 index 000000000000..5706e4fd9637 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/ro.po @@ -0,0 +1,3026 @@ +# Mesajele în limba românã pentru pachetul bfd. +# Copyright (C) 2003 Free Software Foundation, Inc. +# Eugen Hoanca , 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:53+0930\n" +"PO-Revision-Date: 2003-11-25 08:39+0200\n" +"Last-Translator: Eugen Hoanca \n" +"Language-Team: Romanian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-2\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:204 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s: Tip secþiune necunoscut în fiºier adobe a.out: %x\n" + +#: aout-cris.c:207 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Tip de relocare exportat invalid: %d" + +#: aout-cris.c:251 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s: Tip de relocare importat invalid: %d" + +#: aout-cris.c:262 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s: Înregistrare de relocare greºitã importatã: %d" + +#: aoutx.h:1295 aoutx.h:1716 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: nu se poate reprezenta secþiunea `%s' în format de fiºier obiect a.out" + +#: aoutx.h:1682 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: nu se poate reprezenta secþiunea pentru simbolul `%s' în formatul de fiºier obiect a.out" + +#: aoutx.h:1684 +msgid "*unknown*" +msgstr "*necunoscut*" + +#: aoutx.h:3776 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: legãtura relocalizabilã din %s cãtre %s nesuportatã" + +#: archive.c:1751 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Avertisment: scrierea arhivei a fost lentã: se rescrie marcajul de timp(timestamp)\n" + +#: archive.c:2014 +msgid "Reading archive file mod timestamp" +msgstr "Citirea fiºierului arhivã mod marcaj de timp" + +#: archive.c:2040 +msgid "Writing updated armap timestamp" +msgstr "Scriere marcaj de timp armap înnoit" + +#: bfd.c:280 +msgid "No error" +msgstr "Nici o eroare" + +#: bfd.c:281 +msgid "System call error" +msgstr "Eroare apel sistem" + +#: bfd.c:282 +msgid "Invalid bfd target" +msgstr "Þintã bfd invalidã" + +#: bfd.c:283 +msgid "File in wrong format" +msgstr "Fiºier în format eronat" + +#: bfd.c:284 +msgid "Archive object file in wrong format" +msgstr "Fiºier obiect arhivã în format eronat" + +#: bfd.c:285 +msgid "Invalid operation" +msgstr "Operaþie invalidã" + +#: bfd.c:286 +msgid "Memory exhausted" +msgstr "Memorie plinã" + +#: bfd.c:287 +msgid "No symbols" +msgstr "Nici un simbol" + +#: bfd.c:288 +msgid "Archive has no index; run ranlib to add one" +msgstr "Arhiva nu are nici un index.; rulaþi ranlib pentru a adãuga unul" + +#: bfd.c:289 +msgid "No more archived files" +msgstr "Nu mai existã fiºiere arhivate" + +#: bfd.c:290 +msgid "Malformed archive" +msgstr "Arhivã malformatã" + +#: bfd.c:291 +msgid "File format not recognized" +msgstr "Formatul de fiºier nu a fost recunoscut" + +#: bfd.c:292 +msgid "File format is ambiguous" +msgstr "Formatul de fiºier este ambiguu" + +#: bfd.c:293 +msgid "Section has no contents" +msgstr "Secþiunea nu are conþinut" + +#: bfd.c:294 +msgid "Nonrepresentable section on output" +msgstr "Secþiune de output nereprezentabilã" + +#: bfd.c:295 +msgid "Symbol needs debug section which does not exist" +msgstr "Simbolul necesitã secþiune de debug care nu existã" + +#: bfd.c:296 +msgid "Bad value" +msgstr "Valoare eronatã" + +#: bfd.c:297 +msgid "File truncated" +msgstr "Fiºier trunchiat" + +#: bfd.c:298 +msgid "File too big" +msgstr "Fiºier prea mare" + +#: bfd.c:299 +msgid "#" +msgstr "#" + +#: bfd.c:687 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "Aserþiunea BFD %s a eºuat %s:%d" + +#: bfd.c:703 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "Eroare interna BFD %s, se renunþã la %s linia %d în %s\n" + +#: bfd.c:707 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "Eroare internã BFD %s, se renunþã la %s linia %d\n" + +#: bfd.c:709 +msgid "Please report this bug.\n" +msgstr "Vã rugãm raportaþi acest bug.\n" + +#: bfdwin.c:202 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "nu se mapeazã: data=%lx mapat =%d\n" + +#: bfdwin.c:205 +msgid "not mapping: env var not set\n" +msgstr "nu se mapeazã: variabila env nu este setatã\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Avertisment: Scrierea secþiunii `%s' spre offset de fiºier imens (sau negativ) 0x%lx" + +#: coff-a29k.c:120 +msgid "Missing IHCONST" +msgstr "IHCONST lipsã" + +#: coff-a29k.c:181 +msgid "Missing IHIHALF" +msgstr "IHHALF lipsã" + +#: coff-a29k.c:213 coff-or32.c:236 +msgid "Unrecognized reloc" +msgstr "Reloc necunoscut" + +#: coff-a29k.c:409 +msgid "missing IHCONST reloc" +msgstr "IHCONST reloc lipsã" + +#: coff-a29k.c:499 +msgid "missing IHIHALF reloc" +msgstr "IHIHALF reloc lipsã" + +#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397 +msgid "GP relative relocation used when GP not defined" +msgstr "Relocare relativã GP folositã când GP nu este definit" + +#: coff-alpha.c:1488 +msgid "using multiple gp values" +msgstr "folosire de valori multiple gp" + +#: coff-arm.c:1066 elf32-arm.h:294 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "%s: nu s-a putut gãsi legãtura(glue) THUMB `%s' pentru `%s'" + +#: coff-arm.c:1096 elf32-arm.h:329 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "%s: nu s-a putut gãsi legãtura(glue) ARM `%s' pentru `%s'" + +#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "%s(%s): avertisment: interlucrul(interworking) nu este activat" + +#: coff-arm.c:1398 elf32-arm.h:1002 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr " prima gãsire: %s: apelare braþ(arm) cãtre deget(thumb)" + +#: coff-arm.c:1493 elf32-arm.h:895 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr " prima gãsire: %s: apelare deget(thumb) cãtre braþ(arm)" + +#: coff-arm.c:1496 +msgid " consider relinking with --support-old-code enabled" +msgstr " luaþi în considerare relinkuirea cu --support-old-code activat" + +#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "%s: adresã eronatã de relocare 0x%lx în secþiunea `%s'" + +#: coff-arm.c:2132 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s: index ilegal de simbol în reloc: %d" + +#: coff-arm.c:2265 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "EROARE: %s este compilat pentru APCS-%d, pe când %s e compilat pentru APCS-%d" + +#: coff-arm.c:2280 elf32-arm.h:2328 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "EROARE: %s trimite float în regiºtrii de float, pe când %s îi trimite în regiºtrii de integer" + +#: coff-arm.c:2283 elf32-arm.h:2333 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "EROARE: %s trimite integer în regiºtrii de integer, pe când %s îi trimite în regiºtrii de float" + +#: coff-arm.c:2298 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "EROARE: %s este compilat ca ºi cod independent de poziþie,pe când þinta %seste poziþie absolutã" + +#: coff-arm.c:2301 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "EROARE: %s este compilat ca ºi cod poziþie absolutã,pe când þinta %seste independentã de poziþie" + +#: coff-arm.c:2330 elf32-arm.h:2405 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "Avertisment: %s suportã interlucru(interworking), pe când %s nu suportã" + +#: coff-arm.c:2333 elf32-arm.h:2412 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "Avertisment: %s nu suportã interlucru(interworking), pe când %s suportã" + +#: coff-arm.c:2360 +#, c-format +msgid "private flags = %x:" +msgstr "marcaje(flags) private = %x:" + +#: coff-arm.c:2368 elf32-arm.h:2467 +msgid " [floats passed in float registers]" +msgstr " [floats trecuþi în regiºtri de float]" + +#: coff-arm.c:2370 +msgid " [floats passed in integer registers]" +msgstr " [floats trecuþi în regiºtrii de integer]" + +#: coff-arm.c:2373 elf32-arm.h:2470 +msgid " [position independent]" +msgstr "[ independent de poziþie]" + +#: coff-arm.c:2375 +msgid " [absolute position]" +msgstr " [poziþie absolutã]" + +#: coff-arm.c:2379 +msgid " [interworking flag not initialised]" +msgstr " [marcajul(flag) de interlucru(interworking) nu este iniþializat]" + +#: coff-arm.c:2381 +msgid " [interworking supported]" +msgstr " [interlucru(interworking) suportat]" + +#: coff-arm.c:2383 +msgid " [interworking not supported]" +msgstr " [interlucru(interworking) nesuportat]" + +#: coff-arm.c:2431 elf32-arm.h:2150 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "Avertisment: Nu se seteazã marcajul(flagu) de interlucru(interworking) al %s atâta timp cât a fost specificat ca non-interlucru(interworking)" + +#: coff-arm.c:2435 elf32-arm.h:2154 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "Avertisment: Se ºterge marcajul(flag) de interlucru(interworking) al %s datoritã unei cereri din afarã" + +#: coff-h8300.c:1096 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "nu am putut mainpula(handle) relocarea R_MEM_INDIRECT în folosirea ieºirii(output) %s" + +#: coff-i960.c:137 coff-i960.c:486 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "convenþie de apelare nesigurã pentru simbol non-COFF" + +#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783 +msgid "unsupported reloc type" +msgstr "tip de relocare nesuportat" + +#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554 +msgid "GP relative relocation when _gp not defined" +msgstr "Relocare relativã GP atâta timp cât _gp nu este definit" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2431 +msgid "reloc against unsupported section" +msgstr "relocare pe o secþiune nesuportatã" + +#: coff-mips.c:2439 +msgid "reloc not properly aligned" +msgstr "relocare incorect aliniatã" + +#: coff-rs6000.c:2790 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: tip de relocare nesuportat 0x%02x" + +#: coff-rs6000.c:2883 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: relocare TOC la 0x%x cãtre simbolul `%s' fãrã nici o intrare TOC" + +#: coff-rs6000.c:3616 coff64-rs6000.c:2109 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "%s: simbolul `%s' are un smclas necunoscut %d" + +#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Tip de relocare necunoscut 0x%x" + +#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: avertisment: index ilegal de simbol %ld în relocãri" + +#: coff-w65.c:364 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "se ignorã reloc %s\n" + +#: coffcode.h:1108 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s): Marcajul(flag) de secþiune %s (0x%x) ignorat" + +#: coffcode.h:2214 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Id þintã TI COFF necunoscut `0x%x'" + +#: coffcode.h:4437 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s: avertisment: index ilegal de simbol %ld în numãrul de linii" + +#: coffcode.h:4451 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s: avertisment: informaþie duplicat a numãrului de linii pentru `%s'" + +#: coffcode.h:4805 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%s: Clasã de depozitare(storage) %d necunoscutã pentru %s simbolul `%s'" + +#: coffcode.h:4938 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "avertisment: %s: simbolul local `%s' nu are secþiune" + +#: coffcode.h:5083 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%s: tip ilegal de relocare %d la adresa 0x%lx" + +#: coffgen.c:1666 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s: mãrime tabel ºiruri invalidã %lu" + +#: cofflink.c:538 elflink.h:1276 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "Avertisment: tipul de simbol `%s' schimbat de la %d la %d în %s" + +#: cofflink.c:2328 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "%s: relocãri în secþiunea `%s', dar fãrã conþinut" + +#: cofflink.c:2671 coffswap.h:890 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: depãºire(overflow) de relocãri: 0x%lx > 0xffff" + +#: cofflink.c:2680 coffswap.h:876 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: avertisment: %s: depãºire(overflow) numãr de linii: 0x%lx > 0xffff" + +#: cpu-arm.c:196 cpu-arm.c:206 +#, c-format +msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale" +msgstr "EROARE: %s este compilat pentru EP9312, pe când %s e compilat pentru XScale" + +#: cpu-arm.c:344 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "avertisment: imposibil de adus la zi(update) conþinutul secþiunii %s în %s" + +#: dwarf2.c:380 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_str" + +#: dwarf2.c:397 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "Eroare Pitic(Dwarf): DW_FORM_strp offset (%lu) mai mare sau egalã cu mãrimea .debug_str (%lu)." + +#: dwarf2.c:541 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_abbrev." + +#: dwarf2.c:556 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "Eroare Pitic(Dwarf): Offset abbrev(%lu) mai mare sau egal cu mãrimea .debug_abbrev (%lu)." + +#: dwarf2.c:756 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Eroare Pitic(Dwarf): Valoare FORM invalidã sau nemanipulabilã: %u." + +#: dwarf2.c:933 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Eroare Pitic(Dwarf): secþiune numãr de linii trunchiatã (numãr fiºier eronat)" + +#: dwarf2.c:1032 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Eroare Pitic(Dwarf): Nu pot gãsi secþiunea debug_line." + +#: dwarf2.c:1049 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "Eroare Pitic(Dwarf): Offsetul de linie (%lu) mai mare sau egal cu mãrimea .debug_line (%lu)" + +#: dwarf2.c:1255 +msgid "Dwarf Error: mangled line number section." +msgstr "Eroare Pitic(Dwarf): secþiune trunchiatã numãr de linii" + +#: dwarf2.c:1470 dwarf2.c:1620 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Eroare Pitic(Dwarf): Nu am putut gãsi numãrul abbrev: %u." + +#: dwarf2.c:1581 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Eroare Pitic(Dwarf): S-a gãsit dwarf versiunea `%u', acest cititor manipuleazã doar informaþii ale versiunii 2." + +#: dwarf2.c:1588 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Eroare Pitic(Dwarf): s-a gãsit adresa mãrimea `%u', acest cititor nu poate manipula mãrimi mai mari decât `%u'" + +#: dwarf2.c:1611 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Eroare Pitic(Dwarf): Numãr invalid de abbrev: %u" + +#: ecoff.c:1339 +#, c-format +msgid "Unknown basic type %d" +msgstr "Tip de bazã necunoscut %d" + +#: ecoff.c:1599 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Simbol Sfârºit+1: %ld" + +#: ecoff.c:1606 ecoff.c:1609 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Primul simbol: %ld" + +#: ecoff.c:1621 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Simbol Sfârºit+1: %-7ld Tip: %s" + +#: ecoff.c:1628 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Simbol local: %ld" + +#: ecoff.c:1636 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1641 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" uniune; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1646 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Simbol Sfârºit+1: %ld" + +#: ecoff.c:1652 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tip: %s" + +#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare nerezolvabilã pe simbolul `%s; din secþiunea `%s'" + +#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812 +#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815 +#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699 +#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510 +#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976 +#: elf64-mmix.c:1332 +msgid "internal error: out of range error" +msgstr "eroare internã: eroare depãºire de domeniu(out of range)" + +#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816 +#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819 +#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287 +#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440 +#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452 +msgid "internal error: unsupported relocation error" +msgstr "eroare internã: eroare de relocare nesuportatã" + +#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578 +#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313 +msgid "internal error: dangerous error" +msgstr "eroare internã: eroare periculoasã" + +#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824 +#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827 +#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711 +#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522 +#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988 +#: elf64-mmix.c:1344 +msgid "internal error: unknown error" +msgstr "eroare internã: eroare necunoscutã" + +#: elf.c:372 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "%s: offset de ºir invalid %u >= %lu pentru secþiunea `%s'" + +#: elf.c:624 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s: intrare SHT_GROUP invalidã" + +#: elf.c:695 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s nu existã informaþii de grup pentru secþiunea %s" + +#: elf.c:1055 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Header Program:\n" + +#: elf.c:1106 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Secþiune Dinamicã:\n" + +#: elf.c:1235 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Definiþii de versiune:\n" + +#: elf.c:1258 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Referinþe Versiune:\n" + +#: elf.c:1263 +#, c-format +msgid " required from %s:\n" +msgstr " cerute de %s:\n" + +#: elf.c:1944 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "%s: link invalid %lu pentru secþiunea de relocare %s (index %u)" + +#: elf.c:3686 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s: Memorie insuficientã pentru headerele programului (alocatã %u, necesarã %u)" + +#: elf.c:3791 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s: Memorie insuficientã pentru headerele programului, încercaþi linkuirea cu -N" + +#: elf.c:3922 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "Eroare: prima secþiune în segment (%s) începe la 0x%x pe când segmentul începe la 0x%x" + +#: elf.c:4242 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s: avertisment: secþiunea alocatã `%s' nu este în segment" + +#: elf.c:4566 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s: simbolul `%s' necesar, dar nu este prezent" + +#: elf.c:4854 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s: avertisment: S-a detectat segment încãrcabil vid, este intenþionat ?\n" + +#: elf.c:5485 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Nnu am putut gãsi secþiunea de output echivalentã pentru simbolul '%s' din secþiunea '%s'" + +#: elf.c:6298 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s: tip de relocare nesuportat: %s" + +#: elf32-arm.h:1228 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "%s: Avertisment: BLX Arm are ca þintã funcþia Arm `%s'." + +#: elf32-arm.h:1424 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%s: Avertisment: BLX Thumb are ca þintã funcþia thumb `%s'." + +#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx): %s relocare pe secþiunea SEC_MERGE" + +#: elf32-arm.h:2012 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare nerezolvabilã %d pe simbolul `%s' din secþiunea %s" + +#: elf32-arm.h:2202 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "Avertisment: Se ºterge marcajul(flag) de interlucru(interworking) al %s deoarece împreunã cu el a fost linkuit cod non-interlucru în %s" + +#: elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "EROARE: %s este compilat pentru EABI versiunea %d, pe când %s este compilat pentru versiunea %d" + +#: elf32-arm.h:2316 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "EROARE: %s este compilat pentru APCS-%d, pe când þinta %s foloseºte APCS-%d" + +#: elf32-arm.h:2344 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni VFP, pe când %s nu le foloseºte" + +#: elf32-arm.h:2349 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni FPA, pe când %s nu le foloseºte" + +#: elf32-arm.h:2360 elf32-arm.h:2365 +#, c-format +msgid "ERROR: %s uses Maverick instructions, whereas %s does not" +msgstr "EROARE: %s foloseºte instrucþiuni Maverick, pe când %s nu le foloseºte" + +#: elf32-arm.h:2385 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "EROARE: %s foloseºte FP software, pe când %s foloseºte FP hardware" + +#: elf32-arm.h:2390 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "EROARE: %s foloseºte FP hardware, pe când %s foloseºte FP software" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9238 +#, c-format +msgid "private flags = %lx:" +msgstr "marcaje(flags) private = %lx:" + +#: elf32-arm.h:2452 +msgid " [interworking enabled]" +msgstr " [interlucru(interworking) activat]" + +#: elf32-arm.h:2460 +msgid " [VFP float format]" +msgstr " [format float VFP]" + +#: elf32-arm.h:2462 +msgid " [Maverick float format]" +msgstr " [format float Maverick]" + +#: elf32-arm.h:2464 +msgid " [FPA float format]" +msgstr " [format float FPA]" + +#: elf32-arm.h:2473 +msgid " [new ABI]" +msgstr " [ABI nou]" + +#: elf32-arm.h:2476 +msgid " [old ABI]" +msgstr " [ABI vechi]" + +#: elf32-arm.h:2479 +msgid " [software FP]" +msgstr " [FP software]" + +#: elf32-arm.h:2488 +msgid " [Version1 EABI]" +msgstr " [EABI Versiunea1]" + +#: elf32-arm.h:2491 elf32-arm.h:2502 +msgid " [sorted symbol table]" +msgstr " [tabelã sortatã de simboluri]" + +#: elf32-arm.h:2493 elf32-arm.h:2504 +msgid " [unsorted symbol table]" +msgstr " [tabelã de simboluri nesortatã]" + +#: elf32-arm.h:2499 +msgid " [Version2 EABI]" +msgstr " [EABI Versiunea2]" + +#: elf32-arm.h:2507 +msgid " [dynamic symbols use segment index]" +msgstr " [simbolurile dinamice folosesc index de segment]" + +#: elf32-arm.h:2510 +msgid " [mapping symbols precede others]" +msgstr " [simbolurile de mapare le precedeazã pe celelalte]" + +#: elf32-arm.h:2517 +msgid " " +msgstr " " + +#: elf32-arm.h:2524 +msgid " [relocatable executable]" +msgstr " [executabil relocabil]" + +#: elf32-arm.h:2527 +msgid " [has entry point]" +msgstr " [are punct de intrare]" + +#: elf32-arm.h:2532 +msgid "" +msgstr "" + +#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823 +#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518 +#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984 +#: elf64-mmix.c:1340 +msgid "internal error: dangerous relocation" +msgstr "eroare internã: relocare periculoasã" + +#: elf32-cris.c:931 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%s: relocare nerezolvabilã %s pe simbolul `%s' din secþiunea `%s'" + +#: elf32-cris.c:993 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "%s:Nu existã nici PLT nici GOR pentru relocarea %s pe simbolul `%s' din secþiunea %s" + +#: elf32-cris.c:996 elf32-cris.c:1122 +msgid "[whose name is lost]" +msgstr "[al cãrui nume s-a pierdut]" + +#: elf32-cris.c:1111 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "%s: relocarea %s cu adãugarea diferitã de zero %d pe simbolul local din secþiunea %s" + +#: elf32-cris.c:1118 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "%s: relocarea %s cu adãugare non-zero %d pe simbolul `%s' din secþiunea %s" + +#: elf32-cris.c:1143 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "%s: relocarea %s nu este permisã pentru simbolul global `%s' din secþiunea %s" + +#: elf32-cris.c:1158 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "%s: relocarea %s din secþiunea %s fãrã GOT creat" + +#: elf32-cris.c:1277 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s: Inconsistenþã internã, nu existã secþiunea de relocare %s" + +#: elf32-cris.c:2500 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%s, secþiunea %s:\n" +" relocarea %s n-ar trebui folositã într-un shared object; recompilaþi cu -fPIC" + +#: elf32-cris.c:2978 +msgid " [symbols have a _ prefix]" +msgstr " [simbolurile au un _prefix]" + +#: elf32-cris.c:3017 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s: se folosesc simbolurile _-prefixate, dar se scrie fiºierul cu simboluri neprefixate" + +#: elf32-cris.c:3018 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s: se folosesc simboluri neprefixate, dar se scrie fiºierul cu simboluri _-prefixate" + +#: elf32-frv.c:1223 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: compilat cu %s ºi linkuit cu module care folosesc relocaþii non-pic" + +#: elf32-frv.c:1273 elf32-iq2000.c:895 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: compilat cu %s ºi linkuit cu module compilate cu %s" + +#: elf32-frv.c:1285 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: foloseºte câmpuri marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)" + +#: elf32-frv.c:1321 elf32-iq2000.c:933 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "marcaje(flags) private = 0x%lx" + +#: elf32-gen.c:83 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "%s: Relocãri în ELF generic (EM: %d)" + +#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: nu se poate crea intrarea trunchiatã %s" + +#: elf32-hppa.c:957 elf32-hppa.c:3538 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%s(%s+0x%lx): nu se poate gãsi %s, recompilaþi cu -ffunction-sections" + +#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%s: relocarea %s nu poate fi utilizatã când se face un shared object, recompilaþicu -fPIC" + +#: elf32-hppa.c:1360 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "%s: relocarea %s nu ar trebui utilizatã când se face un shared object, recompilaþicu -fPIC" + +#: elf32-hppa.c:1553 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "Nu se poate gãsi secþiunea de relocare pentru %s" + +#: elf32-hppa.c:2828 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "%s: exportare de ciot(stub) duplicatã %s" + +#: elf32-hppa.c:3416 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx): se fixeazã %s" + +#: elf32-hppa.c:4039 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "%s(%s+0x%lx): nu pot manipula %s pentru %s" + +#: elf32-hppa.c:4357 +msgid ".got section not immediately after .plt section" +msgstr "secþiunea .got nu urmeazã imediat dupã secþiunea .plt" + +#: elf32-i386.c:326 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s: tip de relocare invalid %d" + +#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637 +#: elf64-s390.c:943 elf64-x86-64.c:650 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s:index de simboluri invalid: %d" + +#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011 +#: elf64-s390.c:1129 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "%s: `%s' accesate ºi ca simboluri locale normale ºi ca simboluri locale pe fire (thread)" + +#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243 +#: elf64-x86-64.c:886 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s: nume secþiune relocare invalid `%s'" + +#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879 +#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664 +#: elf64-x86-64.c:2452 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): relocare nerezolvabilã pe simbolul `%s'" + +#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068 +#: elf64-x86-64.c:2490 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "%s(%s+0x%lx): relocare pe `%s': eroare %d" + +#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k relaxer: schimbare de tabel fãrã potrivirea completã a informaþiei de relocare." + +#: elf32-ip2k.c:588 elf32-ip2k.c:767 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k relaxer: headerul tablelului de schimbare este corupt." + +#: elf32-ip2k.c:1395 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: lipseºte instrucþiunea de paginã la 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1409 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: instrucþiune redundantã de paginã la 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1593 +msgid "unsupported relocation between data/insn address spaces" +msgstr "relocare nesuportatã între datã/spaþiu adresã insn" + +#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072 +#: elfxx-mips.c:9195 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: foloseºte câmpuri de marcaje e_flags (0x%lx) diferite de modulele anterioare (0x%lx)" + +#: elf32-m32r.c:930 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "Relocare SDA când _SDA_BASE_ nu este definit" + +#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958 +#: elf64-ia64.c:3958 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: tip necunoscut de relocare %d" + +#: elf32-m32r.c:1226 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Þinta (%s) unei relocãri %s este în secþiunea nepotrivitã (%s)" + +#: elf32-m32r.c:1952 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "%s: Setul de instrucþiuni nu se potriveºte cu modulele anterioare" + +#: elf32-m32r.c:1975 +#, c-format +msgid "private flags = %lx" +msgstr "marcaje (flags) private = %lx" + +#: elf32-m32r.c:1980 +msgid ": m32r instructions" +msgstr ": instrucþiuni m32r" + +#: elf32-m32r.c:1981 +msgid ": m32rx instructions" +msgstr ": instrucþiuni m32rx" + +#: elf32-m68hc1x.c:1217 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Referinþa la simbolul depãrtat `%s' folosind o relocare invalidã poate duce la execuþie incorectã" + +#: elf32-m68hc1x.c:1240 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "adresa banked [%lx:%04lx] (%lx) nu este în acelaºi bank precum adresa banked curentã [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1259 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "referinþã la adresa banked [%lx:%04lx] în spaþiul normal de adresã la %04lx" + +#: elf32-m68hc1x.c:1396 +#, c-format +msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%s: linkuire a fiºierelor compilate pentru întregi(integers) pe 16-biþi (-mshort) ºi a celorlalte pentru întregi(integers) pe 32-biþi" + +#: elf32-m68hc1x.c:1404 +#, c-format +msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%s: linkuire a fiºierelor compilate pentru double pe 32-biþi (-fshort-double) ºi a celorlalte pentru double pe 64-biþi" + +#: elf32-m68hc1x.c:1414 +#, c-format +msgid "%s: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%s:linkuire a fiºierelor compilate pentru HCS12 cu celelalte compilate pentru HC12" + +#: elf32-m68hc1x.c:1462 +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1464 +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1467 +msgid "64-bit double, " +msgstr "double pe 64-biþi, " + +#: elf32-m68hc1x.c:1469 +msgid "32-bit double, " +msgstr "double pe 32-biþi, " + +#: elf32-m68hc1x.c:1472 +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1474 +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1476 +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1479 +msgid " [memory=bank-model]" +msgstr " [memorie=mod-bank]" + +#: elf32-m68hc1x.c:1481 +msgid " [memory=flat]" +msgstr " [memorie=întinsã(flat)]" + +#: elf32-m68k.c:400 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:403 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:353 elf32-mcore.c:456 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "%s: Relocarea %s (%d) nu este încã suportatã.\n" + +#: elf32-mcore.c:441 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s: Tip necunoscut de relocare %d\n" + +#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "relocarea relativã gp 32bits are loc pe un simbol extern" + +#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "Linkuirea obiectelor mips16 în formatul %s nu este suportatã" + +#: elf32-ppc.c:2056 +#, c-format +msgid "generic linker can't handle %s" +msgstr "linkerul generic nu poate manipula(handle) %s" + +#: elf32-ppc.c:2138 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s: compilat cu -mrelocatable ºi linkuit cu module compilate normal" + +#: elf32-ppc.c:2147 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s: compilat normal ºi linkuite cu module compilate cu -mrelocatable" + +#: elf32-ppc.c:3413 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s: relocarea %s nu poate fi folositã când se creazã un shared object" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3619 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against local symbol" +msgstr "relocare %s(%s+0x%lx): %s pe simbol local" + +#: elf32-ppc.c:4862 elf64-ppc.c:7789 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%s: tip de relocare %d necunoscut pentru simbolul %s" + +#: elf32-ppc.c:5113 +#, c-format +msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%s(%s+0x%lx): adãugare non-zero în relocarea %s pentru `%s'" + +#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484 +#, c-format +msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%s: þinta (%s) unei relocãri %s este într-o secþiune invalidã de output (%s)" + +#: elf32-ppc.c:5539 +#, c-format +msgid "%s: relocation %s is not yet supported for symbol %s." +msgstr "%s: relocarea %s nu este încã suportatã pentru simbolul %s." + +#: elf32-ppc.c:5594 elf64-ppc.c:8461 +#, c-format +msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): relocare nerezolvabilã %s pe simbolul `%s'" + +#: elf32-ppc.c:5644 elf64-ppc.c:8507 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against `%s': error %d" +msgstr "%s(%s+0x%lx):relocarea %s pe `%s': eroare %d" + +#: elf32-ppc.c:5888 +#, c-format +msgid "corrupt or empty %s section in %s" +msgstr "secþiune %s coruptã sau vidã în %s" + +#: elf32-ppc.c:5895 +#, c-format +msgid "unable to read in %s section from %s" +msgstr "nu se poate citi în secþiunea %s din %s" + +#: elf32-ppc.c:5901 +#, c-format +msgid "corrupt %s section in %s" +msgstr "secþiune coruptã %s în %s" + +#: elf32-ppc.c:5944 +#, c-format +msgid "warning: unable to set size of %s section in %s" +msgstr "avertisment: nu se poate seta mãrimea secþiunii %s în %s" + +#: elf32-ppc.c:5994 +msgid "failed to allocate space for new APUinfo section." +msgstr "nu s-a putut aloca spaþiu pentru secþiunea nouã APUinfo." + +#: elf32-ppc.c:6013 +msgid "failed to compute new APUinfo section." +msgstr "nu s-a putut calcula(compute) secþiunea nouã APUinfo." + +#: elf32-ppc.c:6016 +msgid "failed to install new APUinfo section." +msgstr "nu s-a putut instala secþiunea APUinfo nouã." + +#: elf32-s390.c:2256 elf64-s390.c:2226 +#, c-format +msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%s(%s+0x%lx): instrucþiune invalidã pentur relocarea TLS %s" + +#: elf32-sh.c:2103 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s: 0x%lx: avertisment: offset R_SH_USES invalid" + +#: elf32-sh.c:2115 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s: 0x%lx: avertisment: R_SH_USES trimite cãtre insn necunoscut 0x%x" + +#: elf32-sh.c:2132 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s: 0x%lx: avertisment:offset de încãrcare R_SH_USES invalid" + +#: elf32-sh.c:2147 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s: 0x%lx: avertismetn: nu s-a putut gãsi relocarea aºteptatã" + +#: elf32-sh.c:2175 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s: 0x%lx: avertisment: simbol în secþiune neaºteptatã" + +#: elf32-sh.c:2300 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s: 0x%lx: avertisment: nu s-a putut gãsi relocarea COUNT aºteptatã" + +#: elf32-sh.c:2309 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s: 0x%lx: avertisment: numãrãtoare(count) invalidã" + +#: elf32-sh.c:2712 elf32-sh.c:3088 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s: 0x%lx: fatal: relocare depãºitã(overflow) în timpul relaxãrii" + +#: elf32-sh.c:4654 elf64-sh64.c:1585 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "STO_SH5_ISA32 neaºteptat pe simbol local ce nu poate fi manipulat" + +#: elf32-sh.c:4809 +#, c-format +msgid "%s: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: relocare nerezolvabilã pe simbolul '%s' din secþiunea `%s'" + +#: elf32-sh.c:4881 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%s: 0x%lx: fatal: ramurã þintã nealiniatã pentru relocare cu suport de relaxare" + +#: elf32-sh.c:6627 elf64-alpha.c:4848 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "%s: codul local executabil TLS nu poate fi linkuit în shared objects" + +#: elf32-sh64.c:221 elf64-sh64.c:2407 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: compilat ca obiect pe 32-biþi ºi %s este pe 64-biþi" + +#: elf32-sh64.c:224 elf64-sh64.c:2410 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: compilat ca obiect pe 64-biþi ºi %s este pe 32-biþi" + +#: elf32-sh64.c:226 elf64-sh64.c:2412 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: mãrimea obiectului nu se potriveºte cu cea a þintei %s" + +#: elf32-sh64.c:461 elf64-sh64.c:2990 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: s-a întâlnit un simbol etichetãdate(datalabel) în intrare(input)" + +#: elf32-sh64.c:544 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "nepotrivire PTB: o adresã SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:547 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "nepotrivire PTA: o adresã SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:565 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: eroare GASr: PTB insn neaºteptat cu R_SH_PT_16" + +#: elf32-sh64.c:614 elf64-sh64.c:1748 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: eroare: tip de reloare nealiniat %d la %08x relocarea %08x\n" + +#: elf32-sh64.c:698 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: nu am putut scrie intrãrile .cranges adãugate" + +#: elf32-sh64.c:760 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: nu am putut scrie intrãrile .cranges sortate" + +#: elf32-sparc.c:2521 elf64-sparc.c:2314 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "%s: probabil compilat fãrã -fPIC?" + +#: elf32-sparc.c:3348 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s: compilat pentru un sistem 64 biþi ºi þinta fiind pe 32 biþi" + +#: elf32-sparc.c:3362 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s: linkuire fiºiere little endian files cu fiºiere big endian" + +#: elf32-v850.c:753 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variabila `%s' nu poate ocupa regiuni multiple de date mici" + +#: elf32-v850.c:756 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variabila `%s' nu poate sã fie în una din regiunile mici, zero sau micuþe" + +#: elf32-v850.c:759 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date mici ºi de date zero" + +#: elf32-v850.c:762 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date mici ºi de date micuþe" + +#: elf32-v850.c:765 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Variabila `%s' nu poate fi simultan ºi în regiuni de date zero ºi de date micuþe" + +#: elf32-v850.c:1144 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "EªUARE în gãsirea relocãrii anterioare HI16\n" + +#: elf32-v850.c:1789 +msgid "could not locate special linker symbol __gp" +msgstr "nu am putut localiza simbolul special de linker __gp" + +#: elf32-v850.c:1793 +msgid "could not locate special linker symbol __ep" +msgstr "nu am putut localiza simbolul special de linker __ep" + +#: elf32-v850.c:1797 +msgid "could not locate special linker symbol __ctbp" +msgstr "nu am putut localiza simbolul special de linker __ctbp" + +#: elf32-v850.c:1963 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s: Arhitectura nu se potriveºte cu modulele anterioare" + +#: elf32-v850.c:1983 +#, c-format +msgid "private flags = %lx: " +msgstr "marcaje(flags) private=- %lx: " + +#: elf32-v850.c:1988 +msgid "v850 architecture" +msgstr "arhitecturã v850" + +#: elf32-v850.c:1989 +msgid "v850e architecture" +msgstr "arhitecturã v850e" + +#: elf32-vax.c:549 +msgid " [nonpic]" +msgstr " [nonpic]" + +#: elf32-vax.c:552 +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:555 +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:663 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: avertisment: adãugarea GOT a %ld în `%s' nu se potriveºte adãugãrii GOT anterioare a %ld" + +#: elf32-vax.c:1667 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: avertisment: adãugarea PLT a %d în `%s' din secþiunea %s ignoratã" + +#: elf32-vax.c:1802 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: avertisment: relocare %s pentru simbolul `%s' din secþiunea %s" + +#: elf32-vax.c:1808 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: avertisment: relocare %s spre 0x%x din secþiunea %s" + +#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450 +msgid "non-zero addend in @fptr reloc" +msgstr "adãugare non-zero în relocare @fptr" + +#: elf64-alpha.c:1108 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "relocarea GPDISP nu a gãsit instrucþiuni ldah ºi lda" + +#: elf64-alpha.c:3731 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s: .subsegmentul got depãseºte 64K (size %d)" + +#: elf64-alpha.c:4602 elf64-alpha.c:4614 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-gp pentru simbolul %s" + +#: elf64-alpha.c:4640 elf64-alpha.c:4773 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã pc pentru simbolul dinamic %s" + +#: elf64-alpha.c:4668 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "%s: schimbare în gp: BRSGP %s" + +#: elf64-alpha.c:4693 +msgid "" +msgstr "" + +#: elf64-alpha.c:4698 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "%s: !samegp reloc apentru simbol fãrã .prologue: %s" + +#: elf64-alpha.c:4749 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s: relocare dinamicã nemanipulabilã pentru %s" + +#: elf64-alpha.c:4832 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-dtp pentru simbolul dinamic %s" + +#: elf64-alpha.c:4855 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "%s: relocare relativã-tp pentru simbolul dinamic %s" + +#: elf64-hppa.c:2086 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "intrarea trunchiatã pentru %s nu poate încãrca .plt, offset dp = %ld" + +#: elf64-mmix.c:1032 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: eroare internã de inconsistenþã pentru valoarea\n" +"registrului global alocat de linker: linkuit: 0x%lx%08lx != relaxat: 0x%lx%08lx\n" + +#: elf64-mmix.c:1416 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s:relocare-offset-bazã-plus pentru simbolul registru: (necunoscut) în %s" + +#: elf64-mmix.c:1421 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s:relocare-offset-bazã-plus pentru simbolul registru: %s în %s" + +#: elf64-mmix.c:1465 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s:relocare registru pentru simbolul non-registru: (necunoscut) în %s" + +#: elf64-mmix.c:1470 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s:relocare registru pentru simbolul non-registru: %s în %s" + +#: elf64-mmix.c:1507 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: directiva LOCAL este validã doar cu un registru sau o valoare absolutã" + +#: elf64-mmix.c:1535 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: directivã LOCAL: Registrulr $%ld nu este un registru local. Primul registru global $%ld." + +#: elf64-mmix.c:1994 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Eroare: definiþii multiple ale `%s'; începutul lui %s este setat într-un fiºierlinkuit anterior\n" + +#: elf64-mmix.c:2053 +msgid "Register section has contents\n" +msgstr "Secþiunea registru nu are conþinut\n" + +#: elf64-mmix.c:2216 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Inconsistenþã internã: rãmâne %u ! = max %u\n" +" Vã rugãm raportaþi acest bug." + +#: elf64-ppc.c:2388 libbfd.c:831 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s: compilat pentru un sistem big endiat iar þinta este little endian" + +#: elf64-ppc.c:2391 libbfd.c:833 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s: compilat pentru un sistem little endiat iar þinta este big endian" + +#: elf64-ppc.c:4857 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s: tip de relocare neaºteptat %u în secþiune .opd" + +#: elf64-ppc.c:4877 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s: .opd nu este un domeniu(array) de intrãri opd" + +#: elf64-ppc.c:4897 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s: sym nedefinit `%s' în secþiune .opd" + +#: elf64-ppc.c:6136 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "nu pot gãsi ramura trunchiatã `%s'" + +#: elf64-ppc.c:6175 elf64-ppc.c:6250 +#, c-format +msgid "linkage table error against `%s'" +msgstr "eroare tabel de linkuire pentru `%s'" + +#: elf64-ppc.c:6340 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "nu se poate construi ramura trunchiatã `%s'" + +#: elf64-ppc.c:7047 +msgid ".glink and .plt too far apart" +msgstr ".glink ºi .plt prea departe unul de altul" + +#: elf64-ppc.c:7135 +msgid "stubs don't match calculated size" +msgstr "trunchierile(stubs) sunt în neconcordanþã cu mãrimea calculatã" + +#: elf64-ppc.c:7147 +#, c-format +msgid "" +"linker stubs in %u groups\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"trunchieri(stubs) de linker în grupurile %u\n" +" ramurã %lu\n" +" ajustare toc %lu\n" +" ramurã lungã %lu\n" +" ajust. lungã toc %lu\n" +" apelare plt %lu" + +#: elf64-ppc.c:7723 +#, c-format +msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%s(%s+0x%lx): TOCuri multiple nu sunt suportateîn folosirea fiºierelor voastre crt; recompilaþi cu -mminimal-toc sau upgradaþi gcc" + +#: elf64-ppc.c:7731 +#, c-format +msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%s(%s+0 x%lx): optimizare apelare sibling pentru `%s' nu permite automatTOCuri multiple; recompilaþi cu -mminimal-toc sau -fno-optimize-sibling-calls, sau faceþi(make) `%s' extern" + +#: elf64-ppc.c:8329 +#, c-format +msgid "%s: relocation %s is not supported for symbol %s." +msgstr "%s: relocarea %s nu este suportatã pentru simbolul %s." + +#: elf64-ppc.c:8408 +#, c-format +msgid "%s: error: relocation %s not a multiple of %d" +msgstr "%s: eroare: relocarea %s nu este multiplu de %d" + +#: elf64-sparc.c:1370 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s: check_relocs: tip de relocare nemanipulabil %d" + +#: elf64-sparc.c:1407 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s: Doar regiºtrii %%g[2367] pot fi declaraþi folosind STT_REGISTER" + +#: elf64-sparc.c:1427 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "Registrul %%g%d a folosit incompatibilitãþi: %s în %s, anterior %s în %s" + +#: elf64-sparc.c:1450 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "Simbolul `%s' are tipuri diferenþiate: REGISTER în %s, anterior %s în %s" + +#: elf64-sparc.c:1496 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "Simbolul `%s' are tipuri diferenþiate: %s în %s, anterior REGISTER în %s" + +#: elf64-sparc.c:3053 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "%s: linkuire cod specific UltraSPARC cu cod specific HAL" + +#: elf64-x86-64.c:739 +#, c-format +msgid "%s: %s' accessed both as normal and thread local symbol" +msgstr "%s: `%s' accesate ºi ca simboluri locale normale ºi ca simboluri locale pe fire (thread)" + +#: elfcode.h:1113 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: numãrul versiunii(%ld) nu se potriveºte cu numãrul simbolului (%ld)" + +#: elfcode.h:1342 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): relocarea %d are indexul de simbol invalid %ld" + +#: elflink.c:1456 +#, c-format +msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s: avertisment: redefinire neaºteptatã a simbolului indirect cu versiune(versioned) `%s'" + +#: elflink.c:1807 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s: nume de simbol versiune %s nedefinit" + +#: elflink.c:2142 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "%s: nepotrivire a mãrimii de relocare în %s secþiunea %s" + +#: elflink.c:2434 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "avertisment: tipul ºi mãrimea simbolului dinamic `%s' nu sunt definite" + +#: elflink.h:1022 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s: %s: versiune invalidã %u (max %d)" + +#: elflink.h:1063 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s: %s: versiune necesarã %d invalidã" + +#: elflink.h:1238 +#, c-format +msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s" +msgstr "Avertisment: alinierea %u al simbolului `%s' din %s este mai micã decât %u în %s" + +#: elflink.h:1252 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s" +msgstr "Avertisment: mãrimea simbolului `%s' a fost schimbatã din %lu din %s în %lu din %s" + +#: elflink.h:2160 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s:versiune %s nedefinitã" + +#: elflink.h:2226 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s: secþiunea .preinit_array section nu este permisã în DSO" + +#: elflink.h:3078 +msgid "Not enough memory to sort relocations" +msgstr "Nu existã memorie suficientã pentru a sorta relocãrile" + +#: elflink.h:3958 elflink.h:4001 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s: nu s-a putut gãsi secþiunea de output %s" + +#: elflink.h:3964 +#, c-format +msgid "warning: %s section has zero size" +msgstr "avertisment: secþiunea %s are mãrime zero" + +#: elflink.h:4483 +#, c-format +msgid "%s: %s symbol `%s' in %s is referenced by DSO" +msgstr "%s: %s simbolul `%s' în %s este referit de DSO" + +#: elflink.h:4564 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%s: nu am putut gãsi secþiunea de output %s pentru secþiunea de input %s" + +#: elflink.h:4666 +#, c-format +msgid "%s: %s symbol `%s' isn't defined" +msgstr "%s: %s simbolul `%s' nu este definit" + +#: elflink.h:5053 elflink.h:5095 +msgid "%T: discarded in section `%s' from %s\n" +msgstr "%T: abandonat(discarded) în secþiunea `%s' din %s\n" + +#: elfxx-mips.c:887 +msgid "static procedure (no name)" +msgstr "procedurã staticã (fãrã nume)" + +#: elfxx-mips.c:1897 +msgid "not enough GOT space for local GOT entries" +msgstr "nu existã destul spaþiu GOT pentru intrãrile GOT locale" + +#: elfxx-mips.c:3691 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "%s: %s+0x%lx: salt la rutinã ciot(stub) ce nu este jal" + +#: elfxx-mips.c:5192 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Relocare malformatã detectatã pentru secþiunea %s" + +#: elfxx-mips.c:5266 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s: relocarea CALL16 la 0x%lx nu este pe simbolul global" + +#: elfxx-mips.c:8692 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: nume ilegal de secþiune `%s'" + +#: elfxx-mips.c:9025 +#, c-format +msgid "%s: endianness incompatible with that of the selected emulation" +msgstr "%s: endianness incompatibilã cu aceea a emulaþiei selectate" + +#: elfxx-mips.c:9037 +#, c-format +msgid "%s: ABI is incompatible with that of the selected emulation" +msgstr "%s: ABI este incompatibil cu cel al emulaþiei selectate" + +#: elfxx-mips.c:9104 +#, c-format +msgid "%s: warning: linking PIC files with non-PIC files" +msgstr "%s: avertisment: linkuire de fiºiere PIC cu fiºiere non-PIC" + +#: elfxx-mips.c:9121 +#, c-format +msgid "%s: linking 32-bit code with 64-bit code" +msgstr "%s: linkuire cod 32-biþi cu cod 64-biþi" + +#: elfxx-mips.c:9149 +#, c-format +msgid "%s: linking %s module with previous %s modules" +msgstr "%s: linkuire a modulului %s cu modulele%s anterioare" + +#: elfxx-mips.c:9172 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s: nepotrivire ABI: linkuire modul %s cu module %s anterioare" + +#: elfxx-mips.c:9241 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:9243 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:9245 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:9247 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:9249 +msgid " [abi unknown]" +msgstr " [abi necunoscut]" + +#: elfxx-mips.c:9251 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:9253 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:9255 +msgid " [no abi set]" +msgstr " [abi nesetat]" + +#: elfxx-mips.c:9258 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:9260 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:9262 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:9264 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:9266 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:9268 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:9270 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:9272 +msgid " [mips32r2]" +msgstr " [mips32r2]" + +#: elfxx-mips.c:9274 +msgid " [unknown ISA]" +msgstr " [ISA necunoscut]" + +#: elfxx-mips.c:9277 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:9280 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:9283 +msgid " [32bitmode]" +msgstr " [mod32biþi]" + +#: elfxx-mips.c:9285 +msgid " [not 32bitmode]" +msgstr " [non-mod32biþi]" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Fiºierul de output necesitã biblioteca globalã(shared) `%s'\n" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Fiºierul de output necesitã biblioteca globalã(shared) `%s'.so.`%s'\n" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Simbolul %s nu este definit pentru acceptare(fixups)\n" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +msgid "Warning: fixup count mismatch\n" +msgstr "Avertisment: nepotrivire numãrãtori acceptare(fixup)\n" + +#: ieee.c:293 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: ºir prea lung (%d caractere, max 65535)" + +#: ieee.c:428 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: simbol necunoscut `%s' marcaje(flags) 0x%x" + +#: ieee.c:938 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "%s: înregistrare ATI neimplementatã %u pe simbolul %u" + +#: ieee.c:963 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "%s: tip ATN neaºteptat %d în parte externã" + +#: ieee.c:985 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s: tip neaºteptat dupã ATN" + +#: ihex.c:264 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s:%d: caracter neaºteptat `%s' în fiºier Intel Hex\n" + +#: ihex.c:372 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s:%u: checksum invalid în fiºier Intel Hex (se aºtepta %u, s-a gãsit %u)" + +#: ihex.c:426 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "%s: %u: mãrime înregistrare a adresei extinse invalidã în fiºier Intel Hex" + +#: ihex.c:443 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "%s: %u: mãrime adresã de start extinsã invalidã în fiºier Intel Hex" + +#: ihex.c:460 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s: %u: mãrime înregistrare a adresei lineare extinse invalidã în fiºier Intel Hex" + +#: ihex.c:477 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s: %u: mãrime adresã linearã de start extinsã invalidã în fiºier Intel Hex" + +#: ihex.c:494 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "%s: %u: tip ihex necunoscut %u în fiºier Intel Hex\n" + +#: ihex.c:619 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "%s: eroare internã în ihex_read_section" + +#: ihex.c:654 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "%s: mãrime secþiune invalidã în ihex_read_section" + +#: ihex.c:872 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: adresa 0x%s este în afara domeniului(range) pentru fiºierul Intel Hex" + +#: libbfd.c:861 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "%s învechitã apelatã la %s linia %d în %s\n" + +#: libbfd.c:864 +#, c-format +msgid "Deprecated %s called\n" +msgstr "%s învechitã apelatã\n" + +#: linker.c:1829 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "%s: simbolul indirect `%s' pentru `%s' este o buclã" + +#: linker.c:2697 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Încercare de a crea un link relocabil cu input %s ºi output %s" + +#: merge.c:896 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "%s: acces dincolo de sfârºitul secþiunii concatenate(merged) (%ld + %ld)" + +#: mmo.c:503 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s:Nu existã nucleu(core) pentru a aloca numele de secþiune %s\n" + +#: mmo.c:579 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Nu existã nucleu(core) pentru a aloca un simbol lung de %d octeþi\n" + +#: mmo.c:1287 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: fiºier mmo invalid: valoare de iniþializare pentru $255 nu este 'Main'\n" + +#: mmo.c:1433 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: secvenþã mare(wide) de caractere 0x%02X 0x%02X nesuportatã dupã numele de simbol care începe cu `%s'\n" + +#: mmo.c:1674 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: fiºier mmo invalid: lopcode `%d' nesuportat\n" + +#: mmo.c:1684 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: fiºier mmo invalid: pentru lop_quote se aºtepta YZ = 1 s-a primit YZ= %d\n" + +#: mmo.c:1720 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: fiºier mmo invalid: pentru lop_loc se aºtepta z =1 sau z = 2 s-a primit z = %d\n" + +#: mmo.c:1766 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixo se aºtepta z =1 sau z = 2 s-a primit z = %d\n" + +#: mmo.c:1805 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx se aºtepta y =0 s-a primit y = %d\n" + +#: mmo.c:1814 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx se aºtepta z =16 sau z = 24 s-a primit z = %d\n" + +#: mmo.c:1837 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: fiºier mmo invalid: pentru lop_fixrx octetul de înceout al operandului word trebuie sã fie 0 sau 1, s-a primit %d\n" + +#: mmo.c:1860 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: nu se poate aloca nume fiºier pentru fiºierul numãrul %d, %d octeþi\n" + +#: mmo.c:1880 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: fiºier mmo invalid: fiºierul numãrul %d `%s' a fost deja introdus ca `%s'\n" + +#: mmo.c:1893 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: fiºier mmo invalid: numele de fiºier pentru numãrul %d nu a fost specificat înainte de folosire\n" + +#: mmo.c:1999 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: fiºier mmo invalid: câmpurile y ºi z ale lop_stab sunt non-zero: y: %d, z: %d\n" + +#: mmo.c:2035 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: fiºier mmo invalid: lop_end nu este ultimul element în fiºier\n" + +#: mmo.c:2048 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: fiºier mmo invalid: YZ al lop_end (%ld) nu este egal cu numerele tetras ale lop_stab precedent (%ld)\n" + +#: mmo.c:2698 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: tabelã de simboluri invalidã: simbol `%s' duplicat\n" + +#: mmo.c:2949 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Definire invalidã de simbol: `Main' setat la %s în loc de adresa de start %s\n" + +#: mmo.c:3039 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: avertisment: tabela de simboluri prea mare pentru mmo, mai mare decâd 65535 cuvinte pe 32 de biþi: %d. Doar 'Main' va fi emis.\n" + +#: mmo.c:3084 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: eroare internã, tabela de simboluri ºi-a schimbat mãrimea din %d în %d cuvinte\n" + +#: mmo.c:3139 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: eroare internã, secþiunea de regiºtri internã %s nu are conþinut\n" + +#: mmo.c:3191 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: nu existã regiºtri iniþializaþi; lungime secþiune 0\n" + +#: mmo.c:3197 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: prea mulþi regiºtri iniþializaþi; lungime secþiune %ld\n" + +#: mmo.c:3202 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: adresã de start invalidã pentru regiºtrii iniþializaþi de lungime %ld: 0x%lx%08lx\n" + +#: oasys.c:1052 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: nu se poate reprezenta secþiune `%s' în oasys" + +#: osf-core.c:137 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Tip nemanipulabil %d de fiºier nucleu(core) OSF/1\n" + +#: pe-mips.c:659 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s: `ld -r' nu este suportat cu obiecte PE MIPS\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:795 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s: %s neimplementat\n" + +#: pe-mips.c:821 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s: salt prea departe(far away)\n" + +#: pe-mips.c:848 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "%s: pair/reflo invalid dupã refhi\n" + +#. XXX code yet to be written. +#: peicode.h:787 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s: Tip import nemanipulabil; %x" + +#: peicode.h:792 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s: Tip import necunoscut; %x" + +#: peicode.h:806 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s: Tip nume import necunoscut; %x" + +#: peicode.h:1164 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s: Tip maºinã necunoscut (0x%x) în arhiva Import Library Format" + +#: peicode.h:1176 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s: Tip de maºinã recunoscut dar nemanipulabil (0x%x) în arhiva Import Library Format" + +#: peicode.h:1193 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "%s: mãrimea câmpului din headerul Import Library Format este zero" + +#: peicode.h:1224 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "%s: ºirul nenul terminat în fiºier obiect ILF." + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"header ppcboot:\n" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Offset intrare = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Lungime = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Câmp Marcaj(Flag) = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Nume Partiþie = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Start Partiþie[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Sfârºit Partiþie[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Sector Partiþie[%d] sector = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Mãrime Partiþie[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5422 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers neimplementatã" + +#: srec.c:302 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d: Caracter neaºteptat `%s'în fiºier S-record\n" + +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "%s(%s+0x%lx): Intrarea bruscã(stab) are index ºir invalid." + +#: syms.c:1019 +msgid "Unsupported .stab relocation" +msgstr "Relocare .stab nesuportatã" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) eºuatã" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) eºuatã" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Mãrime nepotrivitã secþiune %s=%lx, %s=%lx" + +#: vms-gsd.c:704 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "subtip %d gsd/egsd necunoscut" + +#: vms-hdr.c:408 +msgid "Object module NOT error-free !\n" +msgstr "Modul obiect CU erori !\n" + +#: vms-misc.c:541 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Depãºire(overflow) de stivã(%d) în bfd_vms_push" + +#: vms-misc.c:559 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Subfolosire(underflow) a stivei _bfd_vms_pop" + +#: vms-misc.c:918 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted apelat cu zero octeþi" + +#: vms-misc.c:923 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted apelat cu prea mulþi octeþi" + +#: vms-misc.c:1054 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Simbolul %s înlocuit de %s\n" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "Eºec în introducerea %s" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "Nu mai existã Mem !" + +#: vms-tir.c:383 +#, c-format +msgid "bad section index in %s" +msgstr "index de secþiune invalid în %s" + +#: vms-tir.c:396 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "cmd STA %s nesuportatã" + +#: vms-tir.c:401 vms-tir.c:1261 +#, c-format +msgid "reserved STA cmd %d" +msgstr "cmd STA %d rezervatã" + +#: vms-tir.c:512 vms-tir.c:535 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "%s: nu existã simbolul \"%s\"" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850 +#: vms-tir.c:859 vms-tir.c:1584 +#, c-format +msgid "%s: not supported" +msgstr "%s: nesuportat" + +#: vms-tir.c:607 vms-tir.c:1439 +#, c-format +msgid "%s: not implemented" +msgstr "%s: neimplementat" + +#: vms-tir.c:611 vms-tir.c:1443 +#, c-format +msgid "reserved STO cmd %d" +msgstr "cmd STO %d rezervatã" + +#: vms-tir.c:729 vms-tir.c:1589 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "cmd OPR %d rezervatã" + +#: vms-tir.c:797 vms-tir.c:1653 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "cmd CTL %d rezervatã" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1169 +msgid "stack-from-image not implemented" +msgstr "stack-from-image neimplementatã" + +#: vms-tir.c:1187 +msgid "stack-entry-mask not fully implemented" +msgstr "stack-entry-mask neimplementatã complet" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1201 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH neimplementatã complet" + +#: vms-tir.c:1220 +msgid "stack-local-symbol not fully implemented" +msgstr "stack-local-symbol neimplementatã complet" + +#: vms-tir.c:1233 +msgid "stack-literal not fully implemented" +msgstr "stack-literal neimplementatã complet" + +#: vms-tir.c:1254 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "stack-local-symbol-entry-point-mask neimplementatã complet" + +#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632 +#: vms-tir.c:1640 vms-tir.c:1648 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: neimplementatã complet" + +#: vms-tir.c:1705 +#, c-format +msgid "obj code %d not found" +msgstr "codul abj %d nu a fost gãsit" + +#: vms-tir.c:2043 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC fãrã relocãri în secþiunea %s" + +#: vms-tir.c:2331 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Relocare nemanipulabilã %s" + +#: xcofflink.c:1244 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "%s: `%s' are numere de linii dar nici o secþiune de închidere" + +#: xcofflink.c:1297 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "%s: clasa %d simbolul `%s' nu are intrãri aux" + +#: xcofflink.c:1320 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "%s: simbolul `%s' are tip necunoscut csect %d" + +#: xcofflink.c:1332 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s: simbol XTY_ER invalid `%s': clasa %d scnum %d scnlen %d" + +#: xcofflink.c:1368 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s: simblul XMC_TC0 `%s' este clasa %d scnlen %d" + +#: xcofflink.c:1520 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "%s: csect `%s' nu este în secþiunea de închidere" + +#: xcofflink.c:1627 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "%s:XTY_LD `%s' rãtãcit" + +#: xcofflink.c:1958 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "%s: relocarea %s:%d nu este în csect" + +#: xcofflink.c:2095 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF shared object neproducând output XCOFF" + +#: xcofflink.c:2116 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: obiect dinamic fãrã secþiune .loader" + +#: xcofflink.c:2761 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: nu existã acest simbol" + +#: xcofflink.c:2894 +msgid "error: undefined symbol __rtinit" +msgstr "eroare: simbol __rtinit nedefinit" + +#: xcofflink.c:3455 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "avertisment: încercare de exportare a simbolului nedefinit `%s'" + +#: xcofflink.c:4448 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "suprasolicitare(overflow) TOC: 0x%lx > 0x10000; încercaþi -mminimal-toc la compilare" + +#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "%s: relocare loader în secþiune necunoscutã `%s'" + +#: xcofflink.c:5310 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "%s: `%s' în relocare loader dar nu în loader sym" + +#: xcofflink.c:5325 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "%s: relocare loader în secþiunea doar-în-citire %s" + +#: elf32-ia64.c:2392 elf64-ia64.c:2392 +msgid "@pltoff reloc against local symbol" +msgstr "relocare @pltoff pe simbol local" + +#: elf32-ia64.c:3804 elf64-ia64.c:3804 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: segment de date scurt depãºit(overflowed) (0x%lx >= 0x400000)" + +#: elf32-ia64.c:3815 elf64-ia64.c:3815 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp nu acoperã segmentul de date scurte" + +#: elf32-ia64.c:4131 elf64-ia64.c:4131 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "%s: linkuire cod non-pic într-o bibliotecã globalã(shared)" + +#: elf32-ia64.c:4164 elf64-ia64.c:4164 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "%s: relocare @gprel pe simbolul dinamic %s" + +#: elf32-ia64.c:4224 elf64-ia64.c:4224 +#, c-format +msgid "%s: linking non-pic code in a position independent executable" +msgstr "%s: linkuire cod non-pic într-un executabil independent de poziþie" + +#: elf32-ia64.c:4363 elf64-ia64.c:4363 +#, c-format +msgid "%s: @internal branch to dynamic symbol %s" +msgstr "%s: ramurã @internal cãtre simbolul dinamic %s" + +#: elf32-ia64.c:4365 elf64-ia64.c:4365 +#, c-format +msgid "%s: speculation fixup to dynamic symbol %s" +msgstr "%s: rezolvare de speculaþie cãtre simbolul dinamic %s" + +#: elf32-ia64.c:4367 elf64-ia64.c:4367 +#, c-format +msgid "%s: @pcrel relocation against dynamic symbol %s" +msgstr "%s: relocare @pcrell pe simbolul dinamic %s" + +#: elf32-ia64.c:4579 elf64-ia64.c:4579 +msgid "unsupported reloc" +msgstr "relocare nesuportatã" + +#: elf32-ia64.c:4858 elf64-ia64.c:4858 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%s: linkuire trap-on-NULL-dereference cu fiºiere non-trapping" + +#: elf32-ia64.c:4867 elf64-ia64.c:4867 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s: linkuire fiºiere big-endiancu fiºiere little-endian" + +#: elf32-ia64.c:4876 elf64-ia64.c:4876 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s: linkuire fiºiere pe 64-biþi cu fiºiere pe 32-biþi" + +#: elf32-ia64.c:4885 elf64-ia64.c:4885 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "%s: linkuire fiºiere constant-gp cu fiºiere non-constant-gp" + +#: elf32-ia64.c:4895 elf64-ia64.c:4895 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "%s: linkuire fiºiere auto-pic cu fiºiere non-auto-pic" + +#: peigen.c:985 pepigen.c:985 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: depãºire(overflow) numãr linii: 0x%lx > 0xffff" + +#: peigen.c:1002 pepigen.c:1002 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "%s: depãºire(overflow) relocare 1: 0x%lx > 0xffff" + +#: peigen.c:1016 pepigen.c:1016 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Director Exportare [.edata (sau oriunde se gãseºte)]" + +#: peigen.c:1017 pepigen.c:1017 +msgid "Import Directory [parts of .idata]" +msgstr "Director Importare [ pãrþi ale .idata]" + +#: peigen.c:1018 pepigen.c:1018 +msgid "Resource Directory [.rsrc]" +msgstr "Director Resursã [.rsrc]" + +#: peigen.c:1019 pepigen.c:1019 +msgid "Exception Directory [.pdata]" +msgstr "Director Excepþie [.pdata]" + +#: peigen.c:1020 pepigen.c:1020 +msgid "Security Directory" +msgstr "Director Securitate" + +#: peigen.c:1021 pepigen.c:1021 +msgid "Base Relocation Directory [.reloc]" +msgstr "Director Relocare de Bazã [.reloc]" + +#: peigen.c:1022 pepigen.c:1022 +msgid "Debug Directory" +msgstr "Director Debug" + +#: peigen.c:1023 pepigen.c:1023 +msgid "Description Directory" +msgstr "Director Descriere" + +#: peigen.c:1024 pepigen.c:1024 +msgid "Special Directory" +msgstr "Director Special" + +#: peigen.c:1025 pepigen.c:1025 +msgid "Thread Storage Directory [.tls]" +msgstr "Director Depozitare Fire(Thread) [.tls]" + +#: peigen.c:1026 pepigen.c:1026 +msgid "Load Configuration Directory" +msgstr "Director Încãrcare Configuraþie" + +#: peigen.c:1027 pepigen.c:1027 +msgid "Bound Import Directory" +msgstr "Director Importare de Graniþã(Bound)" + +#: peigen.c:1028 pepigen.c:1028 +msgid "Import Address Table Directory" +msgstr "Director Importare Tabelã de Adrese" + +#: peigen.c:1029 pepigen.c:1029 +msgid "Delay Import Directory" +msgstr "Director Importare Întârziere" + +#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031 +msgid "Reserved" +msgstr "Rezervat" + +#: peigen.c:1094 pepigen.c:1094 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã o tabelã de importare, dar secþiunea care o conþine n-a putut fi gãsitã\n" + +#: peigen.c:1099 pepigen.c:1099 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Existã o tabelã de importare în %s la 0x%lx\n" + +#: peigen.c:1136 pepigen.c:1136 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Descriptorul de funcþie localizat la adresa de start: %04lx\n" + +#: peigen.c:1139 pepigen.c:1139 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcode-base %08lx toc (încãrcabil/actual) %08lx/%08lx\n" + +#: peigen.c:1145 pepigen.c:1145 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Nu existã secþiune reldata! Descriptorul de funcþie nu este decodat.\n" + +#: peigen.c:1150 pepigen.c:1150 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Tabelele de Importare (interpretat conþinutul secþiunii %s)\n" + +#: peigen.c:1153 pepigen.c:1153 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Sugestie Timp Înaintare DLL Primul\n" +" Tabel Marcaj Lanþ Nume Thunk\n" + +#: peigen.c:1204 pepigen.c:1204 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tNume DLL: %s\n" + +#: peigen.c:1215 pepigen.c:1215 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Sugestie/Ord Membru-Nume Salt-La\n" + +#: peigen.c:1240 pepigen.c:1240 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã un prim thunk, dar secþiunea care îl conþine nu poate fi gãsitã\n" + +#: peigen.c:1380 pepigen.c:1380 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Existã o tabelã de export, dar secþiunea ce o conþine nu poate fi gãsitã\n" + +#: peigen.c:1385 pepigen.c:1385 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Existã o tabelã de exportare în %s la 0x%lx\n" + +#: peigen.c:1416 pepigen.c:1416 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Tabelele de Exportare (interpretare conþinut secþiune %s)\n" +"\n" + +#: peigen.c:1420 pepigen.c:1420 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Marcaje(Flags) Exportare \t\t\t%lx\n" + +#: peigen.c:1423 pepigen.c:1423 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Marcaj(stamp) Orã/Datã \t\t%lx\n" + +#: peigen.c:1426 pepigen.c:1426 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Major/Minor \t\t\t%d/%d\n" + +#: peigen.c:1429 pepigen.c:1429 +msgid "Name \t\t\t\t" +msgstr "Nume \t\t\t\t" + +#: peigen.c:1435 pepigen.c:1435 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Bazã Ordinalã \t\t\t%ld\n" + +#: peigen.c:1438 pepigen.c:1438 +msgid "Number in:\n" +msgstr "Numãr în:\n" + +#: peigen.c:1441 pepigen.c:1441 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\t Tabelã Exportare Adrese \t\t%08lx\n" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\tTabelã [Nume Pointer/Ordinal]\t%08lx\n" + +#: peigen.c:1448 pepigen.c:1448 +msgid "Table Addresses\n" +msgstr "Adrese Tabelã\n" + +#: peigen.c:1451 pepigen.c:1451 +msgid "\tExport Address Table \t\t" +msgstr "\tTabelã Exportare de Adrese \t\t" + +#: peigen.c:1456 pepigen.c:1456 +msgid "\tName Pointer Table \t\t" +msgstr "\tNume Pointer Tabelã \t\t" + +#: peigen.c:1461 pepigen.c:1461 +msgid "\tOrdinal Table \t\t\t" +msgstr "\tOrdinal Tabelã \t\t\t" + +#: peigen.c:1476 pepigen.c:1476 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Tabelã Exportare de Adrese -- Bazã Ordinalã %ld\n" + +#: peigen.c:1495 pepigen.c:1495 +msgid "Forwarder RVA" +msgstr "Trimiþãtor(Forwarder) RVA" + +#: peigen.c:1506 pepigen.c:1506 +msgid "Export RVA" +msgstr "Exportare RVA" + +#: peigen.c:1513 pepigen.c:1513 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Ordinal/Nume Pointer] Tabelã\n" + +#: peigen.c:1568 pepigen.c:1568 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Avertisment, mãrimea secþiunii .pdata (%ld) nu este multiplu de %d\n" + +#: peigen.c:1572 pepigen.c:1572 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Tabela de Funcþii (interpretare conþinut secþiune .pdata)\n" + +#: peigen.c:1575 pepigen.c:1575 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tAdresã Început Adresã Sfârºit Info Unwind\n" + +#: peigen.c:1577 pepigen.c:1577 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tÎnceput Sfârºit EH EH PrologSfârºit Excepþii\n" +" \t\tAdresã Adresã Manipulant Date Adresã Mascã\n" + +#: peigen.c:1647 pepigen.c:1647 +msgid " Register save millicode" +msgstr " Registrul salveazã millicode " + +#: peigen.c:1650 pepigen.c:1650 +msgid " Register restore millicode" +msgstr "Registrul reface millicode" + +#: peigen.c:1653 pepigen.c:1653 +msgid " Glue code sequence" +msgstr "Secvenþã de cod lipitã(glue)" + +#: peigen.c:1705 pepigen.c:1705 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Relocãri Bazã Fiºier PE (interpretare conþinut secþiune .reloc)\n" + +#: peigen.c:1735 pepigen.c:1735 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Adresã Virtualã: %08lx Mãrime Trunchiere %ld (0x%lx) Numãr acceptãri %ld\n" + +#: peigen.c:1748 pepigen.c:1748 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\trelocarea %4d offset %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1788 pepigen.c:1788 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Caracteristici 0x%x\n" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Tip special necunoscut de linker %d" + +#~ msgid "v850ea architecture" +#~ msgstr "arhitecturã v850ea" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: Secþiunea %s este prea mare pentru a adãuga o gaurã de %ld octeþi" + +#~ msgid "Error: out of memory" +#~ msgstr "Eroare: memorie plinã" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "avertisment: relocare pe secþiune eliminatã; se umple cu zero(zeroing)" + +#~ msgid "warning: relocation against removed section" +#~ msgstr "avertisment: relocare pe secþiune eliminatã" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "simboluri locale în secþiunea îndepãrtatã(discarded) %s" + +#~ msgid "%s: linking abicalls files with non-abicalls files" +#~ msgstr "%s: linkuire fiºiere abicalls cu fiºiere non-abicalls" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: nepotrivire ISA (-mips%d) cu modulele anterioare (-mips%d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: nepotrivire ISA (%d) cu modulele anterioare (%d)" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: relocare dinamicã pe acceptare(fixup) speculativã" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: speculaþie acceptare(fixup) pe simbol ambiguu(weak) nedefinit" diff --git a/external/gpl3/gdb/dist/bfd/po/ru.gmo b/external/gpl3/gdb/dist/bfd/po/ru.gmo new file mode 100644 index 0000000000000000000000000000000000000000..20863677237b41b38a36935d0b6d35b2b8a888e3 GIT binary patch literal 175235 zcmcGX2Yggj`oAXu3!o?hilTBUp@$Aas0oA`iX6p@4aJJ?Cy%a zcWi50d+%M>-q!YizUMu6G81Ck-~R9Cb9wH2dU;Pj6JFb)<*5;#w^~LbyTbmxB9Vi) zj6}xFl4&F|bx9=B2~LB%!y>pNJP7Up&wxGPm2fD05_W+t%OjBt*aL0{r^9TxH|z=5 zLxp>v=PRDyK)G+bzs0vZ43Nh{g}Wb=zXPGtaXM5wu7NwjdthJqA{+%K22O_?VITN2oC14QMk0Bz8p`~3FTV#nA`h*ybWMYk zkQYOh+a*x(-VfWu=b+O2k+)B;w({!=m9Kel5UhaP!E-#XhC3tQ0sFz{JzLb6JP>xr zd=XUmYvI=Lbl3)-4|juCLB;ck=bKRF`#qE%bXsQRJRI(VJPXRc+?yZi%`b$?_Z?92 zJq?w=k70lKE8GtDueI>TK)IU-6@Mjc3lD(`=VYk-UGDAggM*P@g4@Gw;=FJ-DF1z- z(w7Yt?mkfYuY)R|GobYCeyDo=7|LDOI*Vr%RJ{3KE{D>ugQ3D-@9nRH(({MC{lB5g zW2<@#uNUlqJRZtj0c;Ofdh=tU!o3iVfww{B`+Lu=mPaDnBJT+0uLo2*N5TNkfy(DH zsPa4pD*pAbGrZl)FF?ify=S`>);{_|)&E$i_Aw2%gLR&VL6y@PQ1Rad2f?Sk+_E7O z>4w}1wt}PK4loz0ycfVua1B&Fo$BQco_9g{e*r4|AHBTYO7lO&b3Rl#uJZEnp4UOu z`}1%Bdo!i6w^tG)et&kLZ+b%W<7Z~h)s zxc~J4KfJ*N%Q0Y1wD!m(^(tkZvzVGz*Pe7&XC8&7bgge6@ zpu%at*7}8Ra2MoJQ04_trs`a|VwJXC&{z;192>;lh&>VNKnBj8666^?X0 zBod*EkDLP=;P!`FzkDQ|gnS;9zjxpsaJ$2-{-;2uERhN*`%_?7co!TC--Ow)%i;7@ zFbb94OJN4w1Qq@#Z~z>9gpFH^p~5>B%H7Ry7<>)NfBPeCJ}?AMM_vUp;R8_h^c5Tq zyBuZZKM(dsJ`VPWH^DjZ9jJ5-KicLat3B_9Losi4409GZ7LI|}L8a$&D81kDSj*oq zScSYC&VcVimDAwkteneX59ISOUK!ty-=Rcv^Yn!u-qv2%arBLoRLdEw5RDE|j+v;g5RDF~}<>Oqa@SlVV zFKxZWKNw101V_W8;TZU!H*a~4g+C1T#JmVfPmc7w1I|YN0`3K~&o%i>SdIK4lwK}8 z&+>mfRJyK%(!-CT@-g^)YxgxU3;7~1zXp}Bb{CkQXF;W}6pn`%!9C&IQ0W?ep|#I) zI2QRtDECjmnQ)tnOkekgs{akJEBqKL-fb_o^i74kA+Lkd&vRiH_!v}qehPcRE|*yQ zm;wXjN~nAt2ZzCD;8fUZgQa&aRC-Q=Q{WR&^|#Zd7H=+8_y<7g$={*+!w+CT*qKJ7 z`kDe&jw_(j^>--yCtx1@5%z#nFE{f_sQjD>JHeZv{5=VGfuBS9Z*zs!*B)>Ja;4`r za2oPwo};d`c6u;WJa@oe@GYovZ+(^3%TzcC`7Ee>y$+=h?XI?Y(-f%umq69$NiZA! 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z5NMv=Pa&`<54;Y2W%f^uCNRT7O$j8KHx%xPE;|-BA+($YXzw3RtO8DjVkKkQ&Eq^S z`{9L4*Vg6?zs7xdff>ihFbuaXn$5jN$~^#HsME?RRF^2lNPLg_oW5O)$qKchO(5Ar ztcSI=8~~Y&@TxmQ>k%MaA31Hamq{b+^+gZbh|2nrup{<#p}T-Xug$x>S)D4?< Xl+?DDGzx&BOAWuWZjl|vO-BC*7}&d5 literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/bfd/po/ru.po b/external/gpl3/gdb/dist/bfd/po/ru.po new file mode 100644 index 000000000000..fc8084d858d9 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/ru.po @@ -0,0 +1,6033 @@ +# translation of bfd-2.20.ru.po to Russian +# Copyright (C) 2003, 2005, 2006, 2009 Free Software Foundation, Inc. +# This file is distributed under the same license as the binutils package. +# +# Yuri Kozlov , 2009, 2010. +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:31+0100\n" +"PO-Revision-Date: 2010-11-10 11:25+0300\n" +"Last-Translator: Yuri Kozlov \n" +"Language-Team: Russian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: Lokalize 1.0\n" +"Plural-Forms: nplurals=3; plural=(n%10==1 && n%100!=11 ? 0 : n%10>=2 && n%10<=4 && (n%100<10 || n%100>=20) ? 1 : 2);\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: неизвеÑтный тип раздела в файле a.out.adobe: %x\n" + +#: aout-cris.c:199 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: ÑкÑпортирован неверный тип перемещениÑ: %d" + +#: aout-cris.c:242 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%s: Импортирован неверный тип перемещениÑ: %d" + +#: aout-cris.c:253 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Импортирована Ð½ÐµÐºÐ¾Ñ€Ñ€ÐµÐºÑ‚Ð½Ð°Ñ Ð·Ð°Ð¿Ð¸ÑÑŒ о перемещении: %d" + +#: aoutx.h:1273 aoutx.h:1611 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: Ð½ÐµÐ»ÑŒÐ·Ñ Ð¿Ñ€ÐµÐ´Ñтавить раздел `%s' в объектном файле формата a.out" + +#: aoutx.h:1577 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: Ð½ÐµÐ»ÑŒÐ·Ñ Ð¿Ñ€ÐµÐ´Ñтавить раздел Ð´Ð»Ñ Ñимвола `%s' в объектном файле формата a.out" + +#: aoutx.h:1579 vms-alpha.c:7649 +msgid "*unknown*" +msgstr "*неизвеÑтно*" + +#: aoutx.h:4007 aoutx.h:4333 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: неожиданный тип перемещениÑ\n" + +#: aoutx.h:5364 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰Ð°ÐµÐ¼Ð°Ñ ÑÑылка из %s в %s не поддерживаетÑÑ" + +#: archive.c:2125 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Предупреждение: Ð¼ÐµÐ´Ð»ÐµÐ½Ð½Ð°Ñ Ð·Ð°Ð¿Ð¸ÑÑŒ в архив: обновлÑетÑÑ Ð¼ÐµÑ‚ÐºÐ° времени\n" + +#: archive.c:2416 +msgid "Reading archive file mod timestamp" +msgstr "Чтение метки времени архивного файла mod" + +#: archive.c:2440 +msgid "Writing updated armap timestamp" +msgstr "ЗапиÑÑŒ обновлённой метки времени armap" + +#: bfd.c:395 +msgid "No error" +msgstr "Ðет ошибки" + +#: bfd.c:396 +msgid "System call error" +msgstr "Ошибка ÑиÑтемного вызова" + +#: bfd.c:397 +msgid "Invalid bfd target" +msgstr "ÐÐµÐ²ÐµÑ€Ð½Ð°Ñ Ñ†ÐµÐ»ÑŒ bfd" + +#: bfd.c:398 +msgid "File in wrong format" +msgstr "Файл в неправильном формате" + +#: bfd.c:399 +msgid "Archive object file in wrong format" +msgstr "Ðрхивный объектный файл в неправильном формате" + +#: bfd.c:400 +msgid "Invalid operation" +msgstr "ÐÐµÐ²ÐµÑ€Ð½Ð°Ñ Ð¾Ð¿ÐµÑ€Ð°Ñ†Ð¸Ñ" + +#: bfd.c:401 +msgid "Memory exhausted" +msgstr "ЗакончилаÑÑŒ памÑÑ‚ÑŒ" + +#: bfd.c:402 +msgid "No symbols" +msgstr "Ðет Ñимволов" + +#: bfd.c:403 +msgid "Archive has no index; run ranlib to add one" +msgstr "Ðрхив без индекÑа; запуÑк ranlib Ð´Ð»Ñ ÑозданиÑ" + +#: bfd.c:404 +msgid "No more archived files" +msgstr "Ðрхивные файлы закончилиÑÑŒ" + +#: bfd.c:405 +msgid "Malformed archive" +msgstr "ИÑкажённый архив" + +#: bfd.c:406 +msgid "File format not recognized" +msgstr "Формат файла не раÑпознан" + +#: bfd.c:407 +msgid "File format is ambiguous" +msgstr "Формат файла неоднозначен" + +#: bfd.c:408 +msgid "Section has no contents" +msgstr "Раздел не имеет Ñодержимого" + +#: bfd.c:409 +msgid "Nonrepresentable section on output" +msgstr "Раздел, непредÑтавимый Ð´Ð»Ñ Ð²Ñ‹Ð²Ð¾Ð´Ð°" + +#: bfd.c:410 +msgid "Symbol needs debug section which does not exist" +msgstr "Ð”Ð»Ñ Ñимвола требуетÑÑ Ð¾Ñ‚Ð»Ð°Ð´Ð¾Ñ‡Ð½Ñ‹Ð¹ раздел, но его не ÑущеÑтвует" + +#: bfd.c:411 +msgid "Bad value" +msgstr "Ðекорректное значение" + +#: bfd.c:412 +msgid "File truncated" +msgstr "Файл уÑечён" + +#: bfd.c:413 +msgid "File too big" +msgstr "Файл Ñлишком большой" + +#: bfd.c:414 +#, c-format +msgid "Error reading %s: %s" +msgstr "Ошибка Ñ‡Ñ‚ÐµÐ½Ð¸Ñ %s: %s" + +#: bfd.c:415 +msgid "#" +msgstr "#<Ðеверный код ошибки>" + +#: bfd.c:939 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "Оператор ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»Ñ BFD %s обнаружил ошибку %s:%d" + +#: bfd.c:951 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "ВнутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ° BFD %s, оÑтанов на %s, Ñтрока %d в %s\n" + +#: bfd.c:955 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "ВнутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ° BFD %s, оÑтанов на %s, Ñтрока %d\n" + +#: bfd.c:957 +msgid "Please report this bug.\n" +msgstr "ПожалуйÑта, Ñообщите об Ñтой ошибке.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "не отображено: данные=%lx отображено=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "не отображено: Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ env не задана\n" + +#: binary.c:271 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Предупреждение: ВыполнÑетÑÑ Ð·Ð°Ð¿Ð¸ÑÑŒ раздела `%s' в файл по огромному (Ñ‚.е. отрицательному) Ñмещению 0x%lx." + +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1640 elf32-frv.c:5740 +#: elfxx-sparc.c:2795 reloc.c:5646 reloc16.c:162 elf32-ia64.c:842 +#: elf64-ia64.c:842 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: --relax и -r Ð½ÐµÐ»ÑŒÐ·Ñ Ð¸Ñпользовать вмеÑте\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "переоткрываетÑÑ %B: %s\n" + +#: coff-alpha.c:491 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Ðе удалоÑÑŒ обработать Ñжатые двоичные файлы Alpha.\n" +" Ð”Ð»Ñ ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ Ð½ÐµÑжатых файлов иÑпользуйте параметры компилÑтора или objZ." + +#: coff-alpha.c:648 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: неизвеÑтный/неподдерживаемый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d" + +#: coff-alpha.c:900 coff-alpha.c:937 coff-alpha.c:2025 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "ИÑпользовано отноÑительное перемещение GP, но GP не определена" + +#: coff-alpha.c:1502 +msgid "using multiple gp values" +msgstr "иÑпользуетÑÑ Ð½ÐµÑколько значений gp" + +#: coff-alpha.c:1561 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: неподдерживаемое перемещение: ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1568 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: неподдерживаемое перемещение: ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:3991 elf64-alpha.c:4140 +#: elf32-ia64.c:4582 elf64-ia64.c:4582 +msgid "%B: unknown relocation type %d" +msgstr "%B: неизвеÑтный тип перемещениÑ: %d" + +#: coff-arm.c:1038 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: не удалоÑÑŒ найти THUMB-Ñклейку '%s' Ð´Ð»Ñ `%s'" + +#: coff-arm.c:1067 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: не удалоÑÑŒ найти ARM-Ñклейку '%s' Ð´Ð»Ñ `%s'" + +#: coff-arm.c:1369 elf32-arm.c:6501 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): предупреждение: ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° не включена.\n" +" первое упоминание: %B: arm-вызов в thumb" + +#: coff-arm.c:1459 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): предупреждение: ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° не включена.\n" +" первое упоминание: %B: thumb-вызов в arm\n" +" выполните переÑборку Ñ Ð²ÐºÐ»ÑŽÑ‡Ñ‘Ð½Ð½Ñ‹Ð¼ параметром --support-old-code" + +#: coff-arm.c:1754 coff-tic80.c:695 cofflink.c:3043 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: неправильный Ð°Ð´Ñ€ÐµÑ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ 0x%lx в разделе `%A'" + +#: coff-arm.c:2079 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: недопуÑтимый Ñимвольный Ð¸Ð½Ð´ÐµÐºÑ Ð² перемещении: %d" + +#: coff-arm.c:2210 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "ошибка: %B Ñобран Ð´Ð»Ñ APCS-%d, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B Ñобран Ð´Ð»Ñ APCS-%d" + +#: coff-arm.c:2226 elf32-arm.c:14105 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "ошибка: %B передаёт чиÑла Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой в региÑтрах Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B передаёт их в целочиÑленных региÑтрах" + +#: coff-arm.c:2229 elf32-arm.c:14109 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "ошибка: %B передаёт чиÑла в целочиÑленных региÑтрах, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B передаёт их в региÑтрах Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой" + +#: coff-arm.c:2243 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "ошибка: %B Ñкомпилирован как позиционно-незавиÑимый код, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº целью %B ÑвлÑетÑÑ ÐºÐ¾Ð´ Ñ Ð°Ð±Ñолютной позицией" + +#: coff-arm.c:2246 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "ошибка: %B Ñкомпилирован как код Ñ Ð°Ð±Ñолютной позицией, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº целью %B ÑвлÑетÑÑ Ð¿Ð¾Ð·Ð¸Ñ†Ð¸Ð¾Ð½Ð½Ð¾-незавиÑимый код" + +#: coff-arm.c:2274 elf32-arm.c:14174 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Предупреждение: %B поддерживает ÑовмеÑтную работу, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B нет" + +#: coff-arm.c:2277 elf32-arm.c:14180 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Предупреждение: %B не поддерживает ÑовмеÑтную работу, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B поддерживает" + +#: coff-arm.c:2301 +#, c-format +msgid "private flags = %x:" +msgstr "ÑобÑтвенные флаги = %x:" + +#: coff-arm.c:2309 elf32-arm.c:10492 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [чиÑла Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой передаютÑÑ Ð² региÑтрах Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой]" + +#: coff-arm.c:2311 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [чиÑла Ñ Ð¿Ð»Ð°Ð²Ð°ÑŽÑ‰ÐµÐ¹ точкой передаютÑÑ Ð² целочиÑленных региÑтрах]" + +#: coff-arm.c:2314 elf32-arm.c:10495 +#, c-format +msgid " [position independent]" +msgstr " [позиционно-незавиÑимый]" + +#: coff-arm.c:2316 +#, c-format +msgid " [absolute position]" +msgstr " [Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð¾Ð¹ позицией]" + +#: coff-arm.c:2320 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [флаг ÑовмеÑтной работы не уÑтановлен]" + +#: coff-arm.c:2322 +#, c-format +msgid " [interworking supported]" +msgstr " [поддерживаетÑÑ ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð°]" + +#: coff-arm.c:2324 +#, c-format +msgid " [interworking not supported]" +msgstr " [ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° не поддерживаетÑÑ]" + +#: coff-arm.c:2370 elf32-arm.c:9520 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Предупреждение: Флаг ÑовмеÑтной работы Ð´Ð»Ñ %B не уÑтанавливаетÑÑ, так как так как он уже указывает на неÑовмеÑтную работу" + +#: coff-arm.c:2374 elf32-arm.c:9524 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Предупреждение: ОчищаетÑÑ Ñ„Ð»Ð°Ð³ ÑовмеÑтной работы Ð´Ð»Ñ %B по внешнему запроÑу" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "невозможно обработать перемещение R_MEM_INDIRECT, еÑли Ð´Ð»Ñ Ð²Ñ‹Ð²Ð¾Ð´Ð° иÑпользуетÑÑ %s" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Перемещение `%s' пока не реализовано\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5147 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: предупреждение: недопуÑтимый Ñимвольный Ð¸Ð½Ð´ÐµÐºÑ %ld в перемещениÑÑ…" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "неÑÑное Ñоглашение о вызове Ð´Ð»Ñ Ð½Ðµ-COFF Ñимвола" + +#: coff-m68k.c:506 elf32-bfin.c:5678 elf32-cr16.c:2897 elf32-m68k.c:4672 +msgid "unsupported reloc type" +msgstr "неподдерживаемый тип перемещениÑ" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 +#: elf64-mips.c:2019 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "ОтноÑительное перемещение GP, но _gp не определена" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "ÐераÑпознанное перемещение" + +#: coff-rs6000.c:2794 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: неподдерживаемый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ 0x%02x" + +#: coff-rs6000.c:2887 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: перемещение TOC по адреÑу 0x%x Ñимвола `%s' без Ñлемента TOC" + +#: coff-rs6000.c:3652 coff64-rs6000.c:2175 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: Ñимвол `%s' имеет нераÑпознанный smclas %d" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "ÐераÑпознанный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: предупреждение: в перемещениÑÑ… недопуÑтимый Ñимвольный Ð¸Ð½Ð´ÐµÐºÑ %ld" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "игнорируетÑÑ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ðµ %s\n" + +#: coffcode.h:973 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: предупреждение: COMDAT Ñимвол '%s' не ÑоответÑтвует имени раздела '%s'" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1197 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Предупреждение: ИгнорируетÑÑ Ñ„Ð»Ð°Ð³ раздела IMAGE_SCN_MEM_NOT_PAGED в разделе %s" + +#: coffcode.h:1264 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): ИгнорируетÑÑ Ñ„Ð»Ð°Ð³ раздела %s (0x%x)" + +#: coffcode.h:2390 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "ÐераÑпознанный идентификатор цели TI COFF '0x%x'" + +#: coffcode.h:2704 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: перемещение по неÑущеÑтвующему Ñимвольному индекÑу: %ld" + +#: coffcode.h:3262 +msgid "%B: too many sections (%d)" +msgstr "%B: Ñлишком много разделов: (%d)" + +#: coffcode.h:3676 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: раздел %s: переполнение таблицы Ñтрок по Ñмещению %d" + +#: coffcode.h:4481 +msgid "%B: warning: line number table read failed" +msgstr "%B: предупреждение: не удалоÑÑŒ прочитать таблицу номеров Ñтрок" + +#: coffcode.h:4511 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: предупреждение: недопуÑтимый Ñимвольный Ð¸Ð½Ð´ÐµÐºÑ %ld в номерах Ñтрок" + +#: coffcode.h:4525 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: предупреждение: повторÑющаÑÑÑ Ð¸Ð½Ñ„Ð¾Ñ€Ð¼Ð°Ñ†Ð¸Ñ Ð¾ номере Ñтроки Ð´Ð»Ñ `%s'" + +#: coffcode.h:4916 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: ÐераÑпознанный клаÑÑ Ñ…Ñ€Ð°Ð½ÐµÐ½Ð¸Ñ %d Ð´Ð»Ñ %s, Ñимвол `%s'" + +#: coffcode.h:5042 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "предупреждение: %B: локальный Ñимвол `%s' не имеет раздела" + +#: coffcode.h:5186 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: недопуÑтимый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d по адреÑу 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: неправильный размер таблицы Ñтрок %lu" + +#: cofflink.c:524 elflink.c:4339 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Предупреждение: в %B изменён тип Ñимвола `%s' Ñ %d на %d" + +#: cofflink.c:2321 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð² разделе `%A', но он не имеет Ñодержимого" + +#: cofflink.c:2652 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: переполнение перемещениÑ: 0x%lx > 0xffff" + +#: cofflink.c:2661 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: предупреждение: %s: переполнение номера Ñтроки: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "ошибка: %B Ñкомпилирован Ð´Ð»Ñ EP9312, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B Ñкомпилирован Ð´Ð»Ñ XScale" + +#: cpu-arm.c:333 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "предупреждение: не удалоÑÑŒ обновить Ñодержимое раздела %s в %s" + +#: dwarf2.c:490 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Ошибка в dwarf: Раздел %s не найден." + +#: dwarf2.c:518 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Ошибка в dwarf: Смещение (%lu) больше или равно размеру %s (%lu)." + +#: dwarf2.c:940 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Ошибка в dwarf: ÐедопуÑтимое или необработанное значение FORM: %u." + +#: dwarf2.c:1191 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Ошибка в dwarf: иÑкажённый раздел номеров Ñтрок (неверный номер файла)." + +#: dwarf2.c:1443 +#, c-format +msgid "Dwarf Error: Unhandled .debug_line version %d." +msgstr "Ошибка в dwarf: Ð½ÐµÐ¾Ð±Ñ€Ð°Ð±Ð¾Ñ‚Ð°Ð½Ð½Ð°Ñ Ð²ÐµÑ€ÑÐ¸Ñ %d у .debug_line." + +#: dwarf2.c:1465 +msgid "Dwarf Error: Invalid maximum operations per instruction." +msgstr "Ошибка в dwarf: неверное макÑимальное количеÑтво операций на инÑтрукцию." + +#: dwarf2.c:1652 +msgid "Dwarf Error: mangled line number section." +msgstr "Ошибка в dwarf: иÑкажённый раздел номеров Ñтрок." + +#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2382 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Ошибка в dwarf: Ðевозможно найти укороченный номер %u." + +#: dwarf2.c:2343 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 and 4 information." +msgstr "Ошибка в dwarf: найдена верÑÐ¸Ñ dwarf «%u», Ñ‚ÐµÐºÑƒÑ‰Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð¿Ð¾Ð½Ð¸Ð¼Ð°ÐµÑ‚ только верÑии 2, 3 и 4." + +#: dwarf2.c:2350 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Ошибка в dwarf: найден размер адреÑа «%u», Ñ‚ÐµÐºÑƒÑ‰Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð½Ðµ умеет работать Ñ Ñ€Ð°Ð·Ð¼ÐµÑ€Ð°Ð¼Ð¸ более чем «%u»." + +#: dwarf2.c:2373 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Ошибка в dwarf: Ðеверный укороченный номер: %u." + +#: ecoff.c:1237 +#, c-format +msgid "Unknown basic type %d" +msgstr "ÐеизвеÑтный начальный тип %d" + +#: ecoff.c:1494 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Символ End+1: %ld" + +#: ecoff.c:1501 ecoff.c:1504 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Первый Ñимвол: %ld" + +#: ecoff.c:1516 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Символ End+1: %-7ld Тип: %s" + +#: ecoff.c:1523 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Локальный Ñимвол: %ld" + +#: ecoff.c:1531 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; Ñимвол End+1: %ld" + +#: ecoff.c:1536 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; Ñимвол End+1: %ld" + +#: ecoff.c:1541 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Ñимвол End+1: %ld" + +#: ecoff.c:1547 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Тип: %s" + +#: elf-attrs.c:569 +msgid "error: %B: Object has vendor-specific contents that must be processed by the '%s' toolchain" +msgstr "ошибка: %B: объект Ñодержит Ñпециальное Ñодержимое производителÑ, которое должно обрабатыватьÑÑ Ð¸Ð½Ñтрументами Ñборки «%s»" + +#: elf-attrs.c:578 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "error: %B: Объектный тег «%d, %s» неÑовмеÑтим Ñ Ñ‚ÐµÐ³Ð¾Ð¼ «%d, %s»" + +#: elf-eh-frame.c:913 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: ошибка в %B(%A); таблиц .eh_frame_hdr Ñоздана не будет.\n" + +#: elf-eh-frame.c:1165 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: из-за кодировки fde в %B(%A) таблица .eh_frame_hdr Ñоздана не будет.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: динамичеÑкий STT_GNU_IFUNC Ñимвол `%s' Ñ Ð¾Ð´Ð¸Ð½Ð°ÐºÐ¾Ð²Ñ‹Ð¼ указателем в `%B' Ð½ÐµÐ»ÑŒÐ·Ñ Ð¸Ñпользовать при Ñоздании иÑполнÑемого файла; перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -fPIE и перекомпонуйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -pie\n" + +#: elf-m10200.c:450 elf-m10300.c:1560 elf32-avr.c:1263 elf32-bfin.c:3193 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4111 elf32-h8300.c:509 +#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 +#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:534 +#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 +#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 +#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +msgid "internal error: out of range error" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: ошибка выхода из диапазона" + +#: elf-m10200.c:454 elf-m10300.c:1564 elf32-avr.c:1267 elf32-bfin.c:3197 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4115 elf32-h8300.c:513 +#: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 +#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:538 +#: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 +#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 +#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 +#: elfxx-mips.c:9186 +msgid "internal error: unsupported relocation error" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: ошибка неподдерживаемого перемещениÑ" + +#: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 +#: elf32-score7.c:2548 elf32-spu.c:5050 +msgid "internal error: dangerous error" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: ошибка риÑка" + +#: elf-m10200.c:462 elf-m10300.c:1577 elf32-avr.c:1275 elf32-bfin.c:3205 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4123 elf32-h8300.c:521 +#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 +#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:546 +#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 +#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 +#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +msgid "internal error: unknown error" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: неизвеÑÑ‚Ð½Ð°Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ°" + +#: elf-m10300.c:1504 elf32-arm.c:9098 elf32-i386.c:4081 elf32-m32r.c:2604 +#: elf32-m68k.c:4156 elf32-ppc.c:8089 elf32-s390.c:3010 elf32-sh.c:4223 +#: elf32-xtensa.c:3067 elf64-ppc.c:13115 elf64-s390.c:2985 elf64-sh64.c:1636 +#: elf64-x86-64.c:3719 elfxx-sparc.c:3806 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): неразрешимое перемещение %s отноÑительно Ñимвола `%s'" + +#: elf-m10300.c:1569 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "ошибка: неподходÑщий тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкой библиотеки (не указан -fpic?)" + +#: elf-m10300.c:1572 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: подозрительный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð² динамичеÑкой библиотеке" + +#: elf-m10300.c:4372 elf32-arm.c:11392 elf32-cr16.c:2451 elf32-cris.c:3044 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2036 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-ppc.c:4994 elf32-s390.c:1652 +#: elf32-sh.c:2931 elf32-vax.c:1040 elf64-ppc.c:6483 elf64-s390.c:1635 +#: elf64-sh64.c:3377 elf64-x86-64.c:1871 elfxx-sparc.c:2104 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "динамичеÑÐºÐ°Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' имеет нулевой размер" + +#: elf.c:334 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: недопуÑтимое Ñмещение Ñтроки %u >= %lu Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° `%s'" + +#: elf.c:446 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B Ñимвольный номер %lu ÑÑылаетÑÑ Ð½Ð° неÑущеÑтвующий раздел SHT_SYMTAB_SHNDX" + +#: elf.c:602 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: Повреждённое поле размера в заголовке раздела групп: 0x%lx" + +#: elf.c:638 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: недопуÑтимый Ñлемент SHT_GROUP" + +#: elf.c:708 +msgid "%B: no group info for section %A" +msgstr "%B: нет информации о группе Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° %A" + +#: elf.c:737 elf.c:3090 elflink.c:10062 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: предупреждение: не задан sh_link Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° `%A'" + +#: elf.c:756 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: некорректный sh_link [%d] в разделе `%A'" + +#: elf.c:791 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: неизвеÑтный [%d] раздел `%s' в группе [%s]" + +#: elf.c:1041 +msgid "%B: unable to initialize commpress status for section %s" +msgstr "%B: не удалоÑÑŒ инициализировать ÑоÑтоÑние ÑÐ¶Ð°Ñ‚Ð¸Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° %s" + +#: elf.c:1050 +msgid "%B: unable to initialize decommpress status for section %s" +msgstr "%B: не удалоÑÑŒ инициализировать ÑоÑтоÑние Ñ€Ð°Ð·Ð¶Ð°Ñ‚Ð¸Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° %s" + +#: elf.c:1158 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Заголовок программы:\n" + +#: elf.c:1200 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"ДинамичеÑкий раздел:\n" + +#: elf.c:1336 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"ОбъÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÐµÑ€Ñий:\n" + +#: elf.c:1361 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"ВерÑии ÑÑылок:\n" + +#: elf.c:1366 +#, c-format +msgid " required from %s:\n" +msgstr " требуетÑÑ Ð¸Ð· %s:\n" + +#: elf.c:1773 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: недопуÑÑ‚Ð¸Ð¼Ð°Ñ ÑÑылка %lu Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° перемещений %s (Ð¸Ð½Ð´ÐµÐºÑ %u)" + +#: elf.c:1943 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: неизвеÑтно как обработать размещённый, Ñпециальный раздел Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ `%s' [0x%8x]" + +#: elf.c:1955 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: неизвеÑтно как обработать Ñпециальный раздел процеÑÑора `%s' [0x%8x]" + +#: elf.c:1966 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: неизвеÑтно как обработать Ñпециальный раздел ОС `%s' [0x%8x]" + +#: elf.c:1976 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: неизвеÑтно как обработать раздел `%s' [0x%8x]" + +#: elf.c:2603 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "предупреждение: тип раздела `%A' изменён на PROGBITS" + +#: elf.c:3047 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link раздела `%A' указывает на отброшенный раздел `%A' из `%B'" + +#: elf.c:3070 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link раздела `%A' указывает на удалённый раздел `%A' из `%B'" + +#: elf.c:4480 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: Первый раздел в Ñегменте PT_DYNAMIC не ÑвлÑетÑÑ Ñ€Ð°Ð·Ð´ÐµÐ»Ð¾Ð¼ .dynamic" + +#: elf.c:4507 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: ÐедоÑтаточно меÑта Ð´Ð»Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²ÐºÐ¾Ð² программы, попытайтеÑÑŒ Ñкомпоновать Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -N" + +#: elf.c:4594 +msgid "%B: section %A lma %#lx adjusted to %#lx" +msgstr "%B: lma %#lx раздела %A подогнано к %#lx" + +#: elf.c:4713 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: раздел «%A» не может быть раÑпределён в Ñегмент %d" + +#: elf.c:4761 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: предупреждение: раÑпределённый раздел `%s' не в Ñегменте" + +#: elf.c:5257 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: требуетÑÑ Ñимвол `%s', но он отÑутÑтвует" + +#: elf.c:5595 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: предупреждение: Обнаружен пуÑтой загружаемый Ñегмент, Ñто так задумывалоÑÑŒ?\n" + +#: elf.c:6622 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Ðе удалоÑÑŒ найти подходÑщее меÑто вывода Ð´Ð»Ñ Ñимвола '%s' из раздела '%s'" + +#: elf.c:7611 +msgid "%B: unsupported relocation type %s" +msgstr "%B: неподдерживаемый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s" + +#: elf32-arm.c:3183 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): предупреждение: ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° не включена.\n" +" первое упоминание: %B: Thumb-вызов в ARM" + +#: elf32-arm.c:3226 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): предупреждение: ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° не включена.\n" +" первое упоминание: %B: ARM-вызов в Thumb" + +#: elf32-arm.c:3432 elf32-arm.c:4807 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: невозможно Ñоздать Ñлемент заглушки %s" + +#: elf32-arm.c:4923 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "не удалоÑÑŒ найти THUMB-Ñклейку '%s' Ð´Ð»Ñ '%s'" + +#: elf32-arm.c:4959 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "не удалоÑÑŒ найти ARM-Ñклейку '%s' Ð´Ð»Ñ '%s'" + +#: elf32-arm.c:5485 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: образы BE8 разрешены только в режиме big-endian." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5715 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: предупреждение: выбранный обход ошибки VFP11 не требуетÑÑ Ð´Ð»Ñ Ñ†ÐµÐ»ÐµÐ²Ð¾Ð¹ архитектуры" + +#: elf32-arm.c:6259 elf32-arm.c:6279 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: невозможно найти Ñклейку VFP11 `%s'" + +#: elf32-arm.c:6327 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "ÐедопуÑтимый в TARGET2 тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ '%s'." + +#: elf32-arm.c:6411 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): предупреждение: interworking not enabled.\n" +" первое упоминание: %B: thumb-вызов в arm" + +#: elf32-arm.c:7130 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Предупреждение: Arm инÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ BLX в функции Arm '%s'." + +#: elf32-arm.c:7541 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "\\%B: Предупреждение: Thumb инÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ BLX в функции thumb '%s'." + +#: elf32-arm.c:8223 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): перемещение R_ARM_TLS_LE32 не разрешено Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ñемого объекта" + +#: elf32-arm.c:8438 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Ð’ группе перемещений ALU разрешена только инÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ ADD или SUB" + +#: elf32-arm.c:8478 elf32-arm.c:8565 elf32-arm.c:8648 elf32-arm.c:8733 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Переполнение во Ð²Ñ€ÐµÐ¼Ñ Ñ€Ð°Ð·Ð´ÐµÐ»ÐµÐ½Ð¸Ñ 0x%lx Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ðµ группы %s" + +#: elf32-arm.c:8963 elf32-sh.c:4112 elf64-sh64.c:1544 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s перемещение в разделе SEC_MERGE" + +#: elf32-arm.c:9074 elf32-m68k.c:4191 elf32-xtensa.c:2805 elf64-ppc.c:11689 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s иÑпользуетÑÑ Ñ TLS-Ñимволом %s" + +#: elf32-arm.c:9075 elf32-m68k.c:4192 elf32-xtensa.c:2806 elf64-ppc.c:11690 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s иÑпользуетÑÑ Ñ Ð½Ðµ-TLS Ñимволом %s" + +#: elf32-arm.c:9132 elf32-tic6x.c:1632 +msgid "out of range" +msgstr "вне диапазона" + +#: elf32-arm.c:9136 elf32-tic6x.c:1636 +msgid "unsupported relocation" +msgstr "неподдерживаемое перемещение" + +#: elf32-arm.c:9144 elf32-tic6x.c:1644 +msgid "unknown error" +msgstr "неизвеÑÑ‚Ð½Ð°Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ°" + +#: elf32-arm.c:9569 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Предупреждение: Ð¡Ð±Ñ€Ð¾Ñ Ñ„Ð»Ð°Ð³Ð° ÑовмеÑтной работы %B, как Ñ Ð½Ð¸Ð¼ был Ñкомпонован код без ÑовмеÑтной работы из %B" + +#: elf32-arm.c:9663 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: ÐеизвеÑтный обÑзательный атрибут EABI-объекта %d" + +#: elf32-arm.c:9671 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Предупреждение: %B: ÐеизвеÑтный атрибут EABI-объекта %d" + +#: elf32-arm.c:9852 +msgid "error: %B: Unknown CPU architecture" +msgstr "ошибка: %B: ÐеизвеÑÑ‚Ð½Ð°Ñ Ð¿Ñ€Ð¾Ñ†ÐµÑÑÐ¾Ñ€Ð½Ð°Ñ Ð°Ñ€Ñ…Ð¸Ñ‚ÐµÐºÑ‚ÑƒÑ€Ð°" + +#: elf32-arm.c:9890 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "ошибка: %B: Противоречащие архитектурные профили %d/%d" + +#: elf32-arm.c:9942 +msgid "Error: %B has both the current and legacy Tag_MPextension_use attributes" +msgstr "Ошибка: %B Ñодержит одновременно и текущий и уÑтаревший атрибут Tag_MPextension_use" + +#: elf32-arm.c:9967 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "ошибка: %B иÑпользует региÑтровые аргументы VFP, а %B не иÑпользует" + +#: elf32-arm.c:10112 +msgid "error: %B: unable to merge virtualization attributes with %B" +msgstr "ошибка: %B: не удалоÑÑŒ объединить атрибуты виртуализации Ñ %B" + +#: elf32-arm.c:10138 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "ошибка: %B: противоречащие архитектурные профили %c/%c" + +#: elf32-arm.c:10239 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Предупреждение: %B: Противоречивые наÑтройки платформы" + +#: elf32-arm.c:10248 +msgid "error: %B: Conflicting use of R9" +msgstr "ошибка: %B: Противоречащее иÑпользование R9" + +#: elf32-arm.c:10260 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "ошибка: %B: противоречащее иÑпользование отноÑительной адреÑации SB и R9" + +#: elf32-arm.c:10273 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "предупреждение: %B иÑпользует %u-байтовый wchar_t, Ñ…Ð¾Ñ‚Ñ ÑƒÐ¶Ðµ иÑпользовалÑÑ %u-байтовый wchar_t; иÑпользование значений wchar_t в разных объектах может привеÑти к ошибке" + +#: elf32-arm.c:10304 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "предупреждение: %B иÑпользует %s enum, Ñ…Ð¾Ñ‚Ñ ÑƒÐ¶Ðµ иÑпользовалÑÑ %s enum; иÑпользование значений enum в разных объектах может привеÑти к ошибке" + +#: elf32-arm.c:10316 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "ошибка: %B иÑпользует региÑтровые аргументы iWMMXt, а %B не иÑпользует" + +#: elf32-arm.c:10333 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "ошибка: формат fp16 раÑходитÑÑ Ð² %B и %B" + +#: elf32-arm.c:10357 +msgid "DIV usage mismatch between %B and %B" +msgstr "ИÑпользование DIV раÑходитÑÑ Ð² %B и %B" + +#: elf32-arm.c:10376 +msgid "%B has has both the current and legacy Tag_MPextension_use attributes" +msgstr "%B Ñодержит одновременно и текущий и уÑтаревший атрибут Tag_MPextension_use" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10468 elf32-bfin.c:5065 elf32-cris.c:4162 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 +#: elfxx-mips.c:12842 +#, c-format +msgid "private flags = %lx:" +msgstr "ÑобÑтвенные флаги = %lx:" + +#: elf32-arm.c:10477 +#, c-format +msgid " [interworking enabled]" +msgstr " [ÑовмеÑÑ‚Ð½Ð°Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð° включена]" + +#: elf32-arm.c:10485 +#, c-format +msgid " [VFP float format]" +msgstr " [VFP формат плавающей точки]" + +#: elf32-arm.c:10487 +#, c-format +msgid " [Maverick float format]" +msgstr " [Maverick формат плавающей точки]" + +#: elf32-arm.c:10489 +#, c-format +msgid " [FPA float format]" +msgstr " [FPA формат плавающей точки]" + +#: elf32-arm.c:10498 +#, c-format +msgid " [new ABI]" +msgstr " [новый ABI]" + +#: elf32-arm.c:10501 +#, c-format +msgid " [old ABI]" +msgstr " [Ñтарый ABI]" + +#: elf32-arm.c:10504 +#, c-format +msgid " [software FP]" +msgstr " [Ð¿Ñ€Ð¾Ð³Ñ€Ð°Ð¼Ð¼Ð½Ð°Ñ FP]" + +#: elf32-arm.c:10513 +#, c-format +msgid " [Version1 EABI]" +msgstr " [ВерÑиÑ1 EABI]" + +#: elf32-arm.c:10516 elf32-arm.c:10527 +#, c-format +msgid " [sorted symbol table]" +msgstr " [отÑÐ¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð½Ð°Ñ Ñ‚Ð°Ð±Ð»Ð¸Ñ†Ð° Ñимволов]" + +#: elf32-arm.c:10518 elf32-arm.c:10529 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [неÑÐ¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð½Ð°Ñ Ñ‚Ð°Ð±Ð»Ð¸Ñ†Ð° Ñимволов]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [Version2 EABI]" +msgstr " [ВерÑиÑ2 EABI]" + +#: elf32-arm.c:10532 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [динамичеÑкие Ñимволы иÑпользуют Ñегментный индекÑ]" + +#: elf32-arm.c:10535 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [проецируемые Ñимволы указываютÑÑ Ñ€Ð°Ð½ÑŒÑˆÐµ]" + +#: elf32-arm.c:10542 +#, c-format +msgid " [Version3 EABI]" +msgstr " [ВерÑиÑ3 EABI]" + +#: elf32-arm.c:10546 +#, c-format +msgid " [Version4 EABI]" +msgstr " [ВерÑиÑ4 EABI]" + +#: elf32-arm.c:10550 +#, c-format +msgid " [Version5 EABI]" +msgstr " [ВерÑиÑ5 EABI]" + +#: elf32-arm.c:10553 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10556 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10562 +#, c-format +msgid " " +msgstr " <нераÑÐ¿Ð¾Ð·Ð½Ð°Ð½Ð½Ð°Ñ Ð²ÐµÑ€ÑÐ¸Ñ EABI>" + +#: elf32-arm.c:10569 +#, c-format +msgid " [relocatable executable]" +msgstr " [перемещаемый иÑполнÑемый]" + +#: elf32-arm.c:10572 +#, c-format +msgid " [has entry point]" +msgstr " [имеет точку входа]" + +#: elf32-arm.c:10577 +#, c-format +msgid "" +msgstr "<ÐераÑпознанный набор битов флага>" + +#: elf32-arm.c:10824 elf32-i386.c:1322 elf32-s390.c:1000 elf32-xtensa.c:1009 +#: elf64-s390.c:960 elf64-x86-64.c:1105 elfxx-sparc.c:1370 +msgid "%B: bad symbol index: %d" +msgstr "%B: неправильный Ñимвольный индекÑ: %d" + +#: elf32-arm.c:10946 elf64-x86-64.c:1265 elf64-x86-64.c:1434 elfxx-mips.c:7942 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: перемещение %s Ð´Ð»Ñ `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта; перекомпилируйте Ñ -fPIC" + +#: elf32-arm.c:11948 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "При обработке файла %s обнаружены ошибки" + +#: elf32-arm.c:13334 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: ошибка: заглушка Ð´Ð»Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ¸ Cortex-A8 раÑположена в небезопаÑном меÑте" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13361 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: ошибка: заглушка Ð´Ð»Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ¸ Cortex-A8 находитÑÑ Ð²Ð½Ðµ диапазона (Ñлишком большой входной файл)" + +#: elf32-arm.c:13455 elf32-arm.c:13477 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: ошибка: Ñклейка VFP11 вне диапазона" + +#: elf32-arm.c:14002 +msgid "error: %B is already in final BE8 format" +msgstr "ошибка: %B уже в конечном формате BE8" + +#: elf32-arm.c:14078 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "ошибка: Объект-иÑточник %B имеет верÑию EABI %d, а цель %B имеет верÑию EABI %d" + +#: elf32-arm.c:14094 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "ошибка: %B Ñкомпилирован Ð´Ð»Ñ APCS-%d, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº цель %B иÑпользует APCS-%d" + +#: elf32-arm.c:14119 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "ошибка: %B иÑпользует инÑтрукции VFP, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B не иÑпользует" + +#: elf32-arm.c:14123 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "ошибка: %B иÑпользует инÑтрукции FPA, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B не иÑпользует" + +#: elf32-arm.c:14133 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "ошибка: %B иÑпользует инÑтрукции Maverick, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B не иÑпользует" + +#: elf32-arm.c:14137 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "ошибка: %B не иÑпользует инÑтрукции Maverick, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B иÑпользует" + +#: elf32-arm.c:14156 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "ошибка: %B иÑпользует программную FP, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B иÑпользует аппаратную FP" + +#: elf32-arm.c:14160 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "ошибка: %B иÑпользует аппаратную FP, в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº %B иÑпользует программную FP" + +#: elf32-avr.c:1271 elf32-bfin.c:3201 elf32-cris.c:2085 elf32-fr30.c:617 +#: elf32-frv.c:4119 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 +#: elf32-m32c.c:561 elf32-mep.c:542 elf32-moxie.c:290 elf32-msp430.c:494 +#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 +#: elf64-mmix.c:1530 +msgid "internal error: dangerous relocation" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: опаÑное перемещение" + +#: elf32-avr.c:2400 elf32-hppa.c:598 elf32-m68hc1x.c:166 elf64-ppc.c:4175 +msgid "%B: cannot create stub entry %s" +msgstr "%B: невозможно Ñоздать Ñлемент заглушки %s" + +#: elf32-bfin.c:1575 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): неразрешимое перемещение отноÑительно Ñимвола `%s'" + +#: elf32-bfin.c:1608 elf32-i386.c:4123 elf32-m68k.c:4233 elf32-s390.c:3062 +#: elf64-s390.c:3037 elf64-x86-64.c:3759 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): перемещение к `%s': ошибка %d" + +#: elf32-bfin.c:2707 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: перемещение `%A+0x%x' ÑÑылаетÑÑ Ð½Ð° Ñимвол `%s' Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-bfin.c:2721 elf32-frv.c:2901 +msgid "relocation references symbol not defined in the module" +msgstr "перемещение указывает на неопределённый Ñимвол в модуле" + +#: elf32-bfin.c:2818 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC указывает на динамичеÑкий Ñимвол Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-bfin.c:2859 elf32-bfin.c:2982 elf32-frv.c:3638 elf32-frv.c:3759 +msgid "cannot emit fixups in read-only section" +msgstr "невозможно Ñгенерировать меÑÑ‚Ð¾Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ Ð² разделе только Ð´Ð»Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ" + +#: elf32-bfin.c:2890 elf32-bfin.c:3020 elf32-frv.c:3669 elf32-frv.c:3803 +#: elf32-lm32.c:1103 elf32-sh.c:5021 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "невозможно Ñгенерировать динамичеÑкие Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð² разделе только Ð´Ð»Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ" + +#: elf32-bfin.c:2940 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_BFIN_FUNCDESC_VALUE указывает на динамичеÑкий Ñимвол Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-bfin.c:3105 +msgid "relocations between different segments are not supported" +msgstr "Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð¼ÐµÐ¶Ð´Ñƒ различными Ñегментами не поддерживаютÑÑ" + +#: elf32-bfin.c:3106 +msgid "warning: relocation references a different segment" +msgstr "предупреждение: перемещение ÑÑылаетÑÑ Ð½Ð° другой Ñегмент" + +#: elf32-bfin.c:4957 elf32-frv.c:6406 +msgid "%B: unsupported relocation type %i" +msgstr "%B: неподдерживаемый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %i" + +#: elf32-bfin.c:5111 elf32-frv.c:6814 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: невозможно Ñкомпоновать не-fdpic объектный файл в иÑполнÑемый fdpic" + +#: elf32-bfin.c:5115 elf32-frv.c:6818 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: невозможно Ñкомпоновать fdpic объектный файл в иÑполнÑемый не-fdpic" + +#: elf32-cris.c:1172 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, раздел %A: неразрешимое перемещение %s у Ñимвола `%s'" + +#: elf32-cris.c:1234 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, раздел %A: Ðет ни PLT ни GOT Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s у Ñимвола `%s'" + +#: elf32-cris.c:1236 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, раздел %A: Ðет PLT Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s у Ñимвола `%s'" + +#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 +#: elf32-cris.c:1871 +msgid "[whose name is lost]" +msgstr "[чьё Ð¸Ð¼Ñ Ð¿Ð¾Ñ‚ÐµÑ€Ñно]" + +#: elf32-cris.c:1361 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, раздел %A: перемещение %s Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением %d у локального Ñимвола" + +#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, раздел %A: перемещение %s Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением %d у Ñимвола `%s'" + +#: elf32-cris.c:1395 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, раздел %A: перемещение %s не разрешено Ð´Ð»Ñ Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð¾Ð³Ð¾ Ñимвола: `%s'" + +#: elf32-cris.c:1411 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, раздел %A: перемещение %s без Ñозданного GOT" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1626 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B, раздел %A: перемещение %s имеет неопределённую ÑÑылку на `%s'; возможно, Ñмешение объÑвлений?" + +#: elf32-cris.c:1998 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, раздел %A: перемещение %s не разрешено Ð´Ð»Ñ Ñимвола: `%s', который определён вне программы; возможно, Ñмешение объÑвлений?" + +#: elf32-cris.c:2051 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(Ñлишком много глобальных переменных Ð´Ð»Ñ -fpic: перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -fPIC)" + +#: elf32-cris.c:2058 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(локальный данные нити Ñлишком велики Ð´Ð»Ñ -fpic или -msmall-tls: перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -fPIC или -mno-small-tls)" + +#: elf32-cris.c:3248 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, раздел %A:\n" +" v10/v32 ÑовмеÑтимый объект %s не должен Ñодержать Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ PIC" + +#: elf32-cris.c:3353 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, раздел %A:\n" +" перемещение %s не должно иÑпользоватьÑÑ Ð² разделÑемом объекте; возможно, Ñмешение параметров, перекомпилируйте Ñ -fPIC" + +#: elf32-cris.c:3567 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, раздел %A:\n" +" перемещение %s не должно иÑпользоватьÑÑ Ð² разделÑемом объекте; перекомпилируйте Ñ -fPIC" + +#: elf32-cris.c:3992 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, раздел %A, к Ñимволу %s:\n" +" перемещение %s не должно иÑпользоватьÑÑ Ð² разделÑемом объекте; перекомпилируйте Ñ -fPIC" + +#: elf32-cris.c:4111 +msgid "Unexpected machine number" +msgstr "Ðеожидаемое машинное чиÑло" + +#: elf32-cris.c:4165 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [Ñимволы Ñодержат Ð¿Ñ€ÐµÑ„Ð¸ÐºÑ _]" + +#: elf32-cris.c:4168 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 и v32]" + +#: elf32-cris.c:4171 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4216 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: иÑпользуютÑÑ Ñимволы Ñ Ð¿Ñ€ÐµÑ„Ð¸ÐºÑом _, но в файл запиÑываютÑÑ Ñимволы без префикÑов" + +#: elf32-cris.c:4217 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: иÑпользуютÑÑ Ñимволы без префикÑа _, но в файл запиÑываютÑÑ Ñимволы Ñ Ð¿Ñ€ÐµÑ„Ð¸ÐºÑом _" + +#: elf32-cris.c:4236 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B Ñодержит код CRIS v32, который не ÑовмеÑтим Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼Ð¸ объектами" + +#: elf32-cris.c:4238 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B Ñодержит код не-CRIS v32, который не ÑовмеÑтим Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼Ð¸ объектами" + +#: elf32-frv.c:1509 elf32-frv.c:1658 +msgid "relocation requires zero addend" +msgstr "Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ñ‚Ñ€ÐµÐ±ÑƒÐµÑ‚ÑÑ Ð½ÑƒÐ»ÐµÐ²Ð¾Ðµ добавление" + +#: elf32-frv.c:2888 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): перемещение в `%s+%x' может быть вызвано предыдущей ошибкой" + +#: elf32-frv.c:2977 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции call" + +#: elf32-frv.c:3019 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции lddi" + +#: elf32-frv.c:3090 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции sethi" + +#: elf32-frv.c:3127 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции setlo или setlos" + +#: elf32-frv.c:3175 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции ldd" + +#: elf32-frv.c:3259 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции calll" + +#: elf32-frv.c:3314 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции ldi" + +#: elf32-frv.c:3344 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции sethi" + +#: elf32-frv.c:3373 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции setlo или setlos" + +#: elf32-frv.c:3404 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции ld" + +#: elf32-frv.c:3449 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции sethi" + +#: elf32-frv.c:3476 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO не применимо Ð´Ð»Ñ Ð¸Ð½Ñтрукции setlo или setlos" + +#: elf32-frv.c:3597 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC указывает на динамичеÑкий Ñимвол Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-frv.c:3717 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE указывает на динамичеÑкий Ñимвол Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-frv.c:3974 elf32-frv.c:4130 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): перемещение Ð´Ð»Ñ `%s': %s" + +#: elf32-frv.c:3976 elf32-frv.c:3980 +msgid "relocation references a different segment" +msgstr "перемещение указывает на другой Ñегмент" + +#: elf32-frv.c:6728 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: компилируетÑÑ Ñ %s и компонуетÑÑ Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñми, в которых иÑпользуютÑÑ Ð½Ðµ-pic перемещениÑ" + +#: elf32-frv.c:6781 elf32-iq2000.c:845 elf32-m32c.c:807 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: компилируетÑÑ Ñ %s и компонуетÑÑ Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñми, Ñкомпилированными Ñ %s" + +#: elf32-frv.c:6793 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: иÑпользует другие неизвеÑтные флаги e_flags (0x%lx) чем предыдущие модули (0x%lx)" + +#: elf32-frv.c:6843 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:2925 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "ÑобÑтвенные флаги = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: ÐŸÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð² универÑальном ELF (EM: %d)" + +#: elf32-hppa.c:850 elf32-hppa.c:3610 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): невозможно доÑтичь %s, перекомпилируйте Ñ -ffunction-sections" + +#: elf32-hppa.c:1284 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: перемещение %s не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта; перекомпилируйте Ñ -fPIC" + +#: elf32-hppa.c:2803 +msgid "%B: duplicate export stub %s" +msgstr "%B: повторный ÑкÑпорт заглушки %s" + +#: elf32-hppa.c:3449 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s меÑтоположение Ð´Ð»Ñ insn 0x%x не поддерживаетÑÑ Ð² неразделÑемой ÑÑылке" + +#: elf32-hppa.c:4296 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): невозможно обработать %s Ð´Ð»Ñ %s" + +#: elf32-hppa.c:4608 +msgid ".got section not immediately after .plt section" +msgstr "раздел .got не может ÑтоÑÑ‚ÑŒ Ñразу поÑле раздела .plt" + +#. Unknown relocation. +#: elf32-i386.c:371 elf32-m68k.c:383 elf32-ppc.c:1674 elf32-s390.c:379 +#: elf32-tic6x.c:1563 elf64-ppc.c:2284 elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: неверный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d" + +#: elf32-i386.c:1265 elf64-x86-64.c:1049 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: TLS-переход из %s в %s Ð´Ð»Ñ `%s' по 0x%lx в разделе `%A' завершилÑÑ Ð½ÐµÑƒÐ´Ð°Ñ‡Ð½Ð¾" + +#: elf32-i386.c:1408 elf32-i386.c:3068 elf64-x86-64.c:1194 elf64-x86-64.c:2780 +#: elfxx-sparc.c:3076 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: перемещение %s вмеÑте Ñ STT_GNU_IFUNC Ñимволом `%s' не обрабатываетÑÑ %s" + +#: elf32-i386.c:1570 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 +#: elf64-s390.c:1151 elfxx-sparc.c:1547 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: `%s' доÑтупен как обычный и как локальный Ð´Ð»Ñ Ð½Ð¸Ñ‚Ð¸ Ñимвол" + +#: elf32-i386.c:2910 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: нераÑпознанное перемещение (0x%x) в разделе `%A'" + +#: elf32-i386.c:3317 elf64-x86-64.c:3174 +msgid "hidden symbol" +msgstr "Ñкрытый Ñимвол" + +#: elf32-i386.c:3320 elf64-x86-64.c:3177 +msgid "internal symbol" +msgstr "внутренний Ñимвол" + +#: elf32-i386.c:3323 elf64-x86-64.c:3180 +msgid "protected symbol" +msgstr "защищённый Ñимвол" + +#: elf32-i386.c:3326 elf64-x86-64.c:3183 +msgid "symbol" +msgstr "Ñимвол" + +#: elf32-i386.c:3331 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: перемещение R_386_GOTOFF Ð´Ð»Ñ Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð¾Ð³Ð¾ %s `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта" + +#: elf32-i386.c:3341 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: перемещение R_386_GOTOFF Ð´Ð»Ñ Ð·Ð°Ñ‰Ð¸Ñ‰Ñ‘Ð½Ð½Ð¾Ð¹ функции `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта" + +#: elf32-i386.c:4633 elf64-x86-64.c:4206 +#, c-format +msgid "discarded output section: `%A'" +msgstr "отброшенный выходной раздел: «%A»" + +#: elf32-ip2k.c:857 elf32-ip2k.c:863 elf32-ip2k.c:930 elf32-ip2k.c:936 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k relaxer: таблица переключений без полного ÑÐ¾Ð²Ð¿Ð°Ð´ÐµÐ½Ð¸Ñ Ð¸Ð½Ñ„Ð¾Ñ€Ð¼Ð°Ñ†Ð¸Ð¸ о перемещении." + +#: elf32-ip2k.c:880 elf32-ip2k.c:963 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k relaxer: иÑпорчен заголовок у таблицы переключений." + +#: elf32-ip2k.c:1292 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: отÑутÑтвует Ñтраница инÑтрукций по адреÑу 0x%08lx (назнач = 0x%08lx)." + +#: elf32-ip2k.c:1308 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k linker: повторÑющаÑÑÑ Ñтраница инÑтрукций по адреÑу 0x%08lx (назнач = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "неподдерживаемое перемещение между адреÑным проÑтранÑтвом данных/insn" + +#: elf32-iq2000.c:858 elf32-m32c.c:819 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: иÑпользует другие неизвеÑтные флаги e_flags (0x%lx) чем предыдущие модули (0x%lx)" + +#: elf32-lm32.c:706 +msgid "global pointer relative relocation when _gp not defined" +msgstr "глобальный указатель отноÑительно перемещениÑ, но _gp не определена" + +#: elf32-lm32.c:761 +msgid "global pointer relative address out of range" +msgstr "глобальный указатель отноÑительно адреÑа вне диапазона" + +#: elf32-lm32.c:1057 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: добавление должно быть нулём Ð´Ð»Ñ R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "перемещение SDA, но _SDA_BASE_ не определена" + +#: elf32-m32r.c:3048 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: Цель (%s) Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s в ошибочном разделе (%A)" + +#: elf32-m32r.c:3576 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Ðабор инÑтрукций не Ñовпадает Ñ Ð½Ð°Ð±Ð¾Ñ€Ð¾Ð¼ у предыдущих модулей" + +#: elf32-m32r.c:3597 +#, c-format +msgid "private flags = %lx" +msgstr "ÑобÑтвенные флаги = %lx" + +#: elf32-m32r.c:3602 +#, c-format +msgid ": m32r instructions" +msgstr ": инÑтрукции m32r" + +#: elf32-m32r.c:3603 +#, c-format +msgid ": m32rx instructions" +msgstr ": инÑтрукции m32rx" + +#: elf32-m32r.c:3604 +#, c-format +msgid ": m32r2 instructions" +msgstr ": инÑтрукции m32r2" + +#: elf32-m68hc1x.c:1050 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Указание на дальний Ñимвол `%s' Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ ошибочного Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð¼Ð¾Ð¶ÐµÑ‚ привеÑти к неправильному выполнению" + +#: elf32-m68hc1x.c:1073 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "банкируемый Ð°Ð´Ñ€ÐµÑ [%lx:%04lx] (%lx) не Ñовпадает Ñ Ð±Ð°Ð½ÐºÐ¾Ð¼ текущего банкируемого адреÑа [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1092 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "ÑÑылка на банкируемый Ð°Ð´Ñ€ÐµÑ [%lx:%04lx] в обычном адреÑном проÑтранÑтве по адреÑу %04lx" + +#: elf32-m68hc1x.c:1225 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: компоновка файлов, Ñкомпилированных Ð´Ð»Ñ 16-битных целых (-mshort), Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸, Ñкомпилированными Ð´Ð»Ñ 32-битных целых" + +#: elf32-m68hc1x.c:1232 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: компоновка файлов, Ñкомпилированных Ð´Ð»Ñ 32-битных double (-fshort-double), Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸, Ñкомпилированными Ð´Ð»Ñ 64-битных double" + +#: elf32-m68hc1x.c:1241 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: компоновка файлов, Ñкомпилированных Ð´Ð»Ñ HCS12, Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸, Ñкомпилированными Ð´Ð»Ñ HC12" + +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4232 elf64-sparc.c:703 elfxx-mips.c:12704 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: иÑпользует другие неизвеÑтные флаги e_flags (0x%lx), чем предыдущие модули (0x%lx)" + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=32-битное int, " + +#: elf32-m68hc1x.c:1287 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=16-битное int, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "64-bit double, " +msgstr "64-битное double, " + +#: elf32-m68hc1x.c:1292 +#, c-format +msgid "32-bit double, " +msgstr "32-битное double, " + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HC11]" +msgstr "ЦП=HC11]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HCS12]" +msgstr "ЦП=HCS12]" + +#: elf32-m68hc1x.c:1299 +#, c-format +msgid "cpu=HC12]" +msgstr "ЦП=HC12]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=bank-model]" +msgstr " [памÑÑ‚ÑŒ=модель Ñ Ð±Ð°Ð½ÐºÐ°Ð¼Ð¸]" + +#: elf32-m68hc1x.c:1304 +#, c-format +msgid " [memory=flat]" +msgstr " [памÑÑ‚ÑŒ=плоÑкаÑ]" + +#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7292 vms-alpha.c:7307 +msgid "unknown" +msgstr "неизвеÑтно" + +#: elf32-m68k.c:1714 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: переполнение GOT: КоличеÑтво перемещений Ñ 8-битным Ñмещением > %d" + +#: elf32-m68k.c:1720 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: переполнение GOT: КоличеÑтво перемещений Ñ 8-ми или 16-битным Ñмещением > %d" + +#: elf32-m68k.c:3959 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): перемещение R_68K_TLS_LE32 не разрешено Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ñемого объекта" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Перемещение %s (%d) в данный момент не поддерживаетÑÑ.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: ÐеизвеÑтный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d\n" + +#: elf32-mep.c:647 +msgid "%B and %B are for different cores" +msgstr "%B и %B Ð´Ð»Ñ Ñ€Ð°Ð·Ð½Ñ‹Ñ… Ñдер" + +#: elf32-mep.c:664 +msgid "%B and %B are for different configurations" +msgstr "%B и %B Ð´Ð»Ñ Ñ€Ð°Ð·Ð½Ñ‹Ñ… конфигураций" + +#: elf32-mep.c:701 +#, c-format +msgid "private flags = 0x%lx" +msgstr "ÑобÑтвенные флаги = 0x%lx" + +#: elf32-microblaze.c:742 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: неизвеÑтный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d" + +#: elf32-microblaze.c:867 elf32-microblaze.c:912 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Цель (%s) Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s в ошибочном разделе (%s)" + +#: elf32-microblaze.c:1155 elfxx-sparc.c:3450 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: вероÑтно, компилÑÑ†Ð¸Ñ Ð±ÐµÐ· -fPIC?" + +#: elf32-microblaze.c:2074 elflink.c:12601 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: неправильное Ð¸Ð¼Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰Ð°ÐµÐ¼Ð¾Ð³Ð¾ раздела `%s'" + +#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "Ð´Ð»Ñ Ð²Ð½ÐµÑˆÐ½ÐµÐ³Ð¾ Ñимвола обнаружено конÑтантное перемещение" + +#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "Ð´Ð»Ñ Ð²Ð½ÐµÑˆÐ½ÐµÐ³Ð¾ Ñимвола обнаружено 32—битное отноÑительное перемещение" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "универÑальный компоновщик не Ñмог обработать %s" + +#: elf32-ppc.c:2180 +msgid "corrupt %s section in %B" +msgstr "повреждённый раздел %s в %B" + +#: elf32-ppc.c:2199 +msgid "unable to read in %s section from %B" +msgstr "не удалоÑÑŒ прочитать раздел %s из %B" + +#: elf32-ppc.c:2240 +msgid "warning: unable to set size of %s section in %B" +msgstr "предупреждение: не удалоÑÑŒ уÑтановить размер раздела %s в %B" + +#: elf32-ppc.c:2290 +msgid "failed to allocate space for new APUinfo section." +msgstr "не удалоÑÑŒ выделить меÑто Ð´Ð»Ñ Ð½Ð¾Ð²Ð¾Ð³Ð¾ раздела APUinfo." + +#: elf32-ppc.c:2309 +msgid "failed to compute new APUinfo section." +msgstr "не удалоÑÑŒ вычиÑлить новый раздел APUinfo." + +#: elf32-ppc.c:2312 +msgid "failed to install new APUinfo section." +msgstr "не удалоÑÑŒ уÑтановить новый раздел APUinfo." + +#: elf32-ppc.c:3358 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: раздел %s не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3702 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s перемещение Ð´Ð»Ñ Ð»Ð¾ÐºÐ°Ð»ÑŒÐ½Ð¾Ð³Ð¾ Ñимвола" + +#: elf32-ppc.c:4044 elf32-ppc.c:4059 elfxx-mips.c:12411 elfxx-mips.c:12437 +#: elfxx-mips.c:12459 elfxx-mips.c:12485 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Предупреждение: %B иÑпользует аппаратную плавающую точку, %B иÑпользует программную плавающую точку" + +#: elf32-ppc.c:4047 elf32-ppc.c:4051 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Предупреждение: %B иÑпользует аппаратную плавающую точку двойной точноÑти, %B иÑпользует аппаратную плавающую точку одинарной точноÑти" + +#: elf32-ppc.c:4055 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Предупреждение: %B иÑпользует программную плавающую точку, %B аппаратную плавающую точку одинарной точноÑти" + +#: elf32-ppc.c:4062 elf32-ppc.c:4066 elfxx-mips.c:12391 elfxx-mips.c:12395 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Предупреждение: %B иÑпользует неизвеÑтный ABI плавающей точки %d" + +#: elf32-ppc.c:4108 elf32-ppc.c:4112 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Предупреждение: %B иÑпользует неизвеÑтный ABI векторов %d" + +#: elf32-ppc.c:4116 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Предупреждение: %B иÑпользует ABI векторов \"%s\", %B иÑпользует \"%s\"" + +#: elf32-ppc.c:4133 elf32-ppc.c:4136 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Предупреждение: %B иÑпользует r3/r4 Ð´Ð»Ñ Ð²Ð¾Ð·Ð²Ñ€Ð°Ñ‚Ð° маленькой Ñтруктуры, %B иÑпользует памÑÑ‚ÑŒ" + +#: elf32-ppc.c:4139 elf32-ppc.c:4143 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Предупреждение: %B иÑпользует неизвеÑтное Ñоглашение %d по возврату маленькой Ñтруктуры" + +#: elf32-ppc.c:4197 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: Ñкомпилирована Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -mrelocatable и нормально Ñкомпонована Ñо Ñкомпилированными модулÑми" + +#: elf32-ppc.c:4205 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: нормально Ñкомпилирована и Ñкомпонована Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñми, Ñкомпилированными Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -mrelocatable" + +#: elf32-ppc.c:4293 +msgid "Using bss-plt due to %B" +msgstr "ИÑпользуетÑÑ bss-plt из-за %B" + +#: elf32-ppc.c:7192 elf64-ppc.c:12307 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: неизвеÑтный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d Ð´Ð»Ñ Ñимвола %s" + +#: elf32-ppc.c:7453 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): ненулевое добавление в перемещении %s Ð´Ð»Ñ `%s'" + +#: elf32-ppc.c:7651 elf64-ppc.c:12812 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): перемещение %s Ð´Ð»Ñ Ð½ÐµÑвного вызова функции %s не поддерживаетÑÑ" + +#: elf32-ppc.c:7881 elf32-ppc.c:7911 elf32-ppc.c:7958 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: назначение (%s) Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s в ошибочный выходной раздел (%s)" + +#: elf32-ppc.c:8030 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: перемещение %s пока не поддерживаетÑÑ Ð´Ð»Ñ Ñимвола %s." + +#: elf32-ppc.c:8138 elf64-ppc.c:13162 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): %s перемещение Ð´Ð»Ñ `%s': ошибка %d" + +#: elf32-ppc.c:8629 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s не определено в компоновщике, Ñозданном %s" + +#: elf32-rx.c:544 +msgid "%B:%A: Warning: deprecated Red Hat reloc " +msgstr "%B:%A: предупреждение: уÑтаревшее перемещение Red Hat" + +#: elf32-rx.c:1086 +msgid "Warning: RX_SYM reloc with an unknown symbol" +msgstr "Предупреждение: перемещение RX_SYM Ñ Ð½ÐµÐ¸Ð·Ð²ÐµÑтным Ñимволом" + +#: elf32-rx.c:1251 +msgid "%B(%A): error: call to undefined function '%s'" +msgstr "%B(%A): ошибка: вызов неопределённой функции «%s»" + +#: elf32-rx.c:1265 +msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" +msgstr "%B(%A): предупреждение: невыровненный доÑтуп к Ñимволу «%s» в малой облаÑти данных" + +#: elf32-rx.c:1269 +msgid "%B(%A): internal error: out of range error" +msgstr "%B(%A): внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: ошибка выхода из диапазона" + +#: elf32-rx.c:1273 +msgid "%B(%A): internal error: unsupported relocation error" +msgstr "%B(%A): внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: ошибка неподдерживаемого перемещениÑ" + +#: elf32-rx.c:1277 +msgid "%B(%A): internal error: dangerous relocation" +msgstr "%B(%A): внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: опаÑное перемещение" + +#: elf32-rx.c:1281 +msgid "%B(%A): internal error: unknown error" +msgstr "%B(%A): внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°: неизвеÑÑ‚Ð½Ð°Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ°" + +#: elf32-rx.c:2928 +#, c-format +msgid " [64-bit doubles]" +msgstr "[64-битные double]" + +#: elf32-rx.c:2930 +#, c-format +msgid " [dsp]" +msgstr " [dsp]" + +#: elf32-s390.c:2209 elf64-s390.c:2196 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): недопуÑÑ‚Ð¸Ð¼Ð°Ñ Ð¸Ð½ÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ Ð´Ð»Ñ TLS-Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s" + +#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3323 +msgid "not enough GOT space for local GOT entries" +msgstr "недоÑтаточно проÑтранÑтва GOT Ð´Ð»Ñ Ð»Ð¾ÐºÐ°Ð»ÑŒÐ½Ñ‹Ñ… Ñлементов GOT" + +#: elf32-score.c:2744 +msgid "address not word align" +msgstr "Ð°Ð´Ñ€ÐµÑ Ð½Ðµ выровнен по границе Ñлова" + +#: elf32-score.c:2829 elf32-score7.c:2634 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Обнаружено иÑкажённое перемещение Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° %s" + +#: elf32-score.c:2880 elf32-score7.c:2685 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: перемещение CALL15 по адреÑу 0x%lx не Ð´Ð»Ñ Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð¾Ð³Ð¾ Ñимвола" + +#: elf32-score.c:3999 elf32-score7.c:3806 +#, c-format +msgid " [pic]" +msgstr " [pic]" + +#: elf32-score.c:4003 elf32-score7.c:3810 +#, c-format +msgid " [fix dep]" +msgstr " [fix dep]" + +#: elf32-score.c:4045 elf32-score7.c:3852 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: предупреждение: выполнÑетÑÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ° PIC-файлов Ñ Ð½Ðµ-PIC файлами" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: директива IMPORT AS Ð´Ð»Ñ %s ÑкрываетÑÑ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰ÐµÐ¹ IMPORT AS" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: ÐераÑÐ¿Ð¾Ð·Ð½Ð°Ð½Ð½Ð°Ñ ÐºÐ¾Ð¼Ð°Ð½Ð´Ð° .directive: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Ðе удалоÑÑŒ добавить переименованный Ñимвол %s" + +#: elf32-sh.c:568 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: предупреждение: неправильное Ñмещение R_SH_USES" + +#: elf32-sh.c:580 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: предупреждение: R_SH_USES указывает на нераÑпознанный insn 0x%x" + +#: elf32-sh.c:597 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: предупреждение: неправильное загрузочное Ñмещение R_SH_USES" + +#: elf32-sh.c:612 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: предупреждение: невозможно найти ожидаемое перемещение" + +#: elf32-sh.c:640 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: предупреждение: Ñимвол в неожиданном разделе" + +#: elf32-sh.c:766 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: предупреждение: невозможно найти ожидаемое перемещение COUNT" + +#: elf32-sh.c:775 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: предупреждение: неправильный Ñчётчик" + +#: elf32-sh.c:1179 elf32-sh.c:1549 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: оÑтанов: переполнение Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð¿Ñ€Ð¸ оÑлаблении" + +#: elf32-sh.c:4057 elf64-sh64.c:1514 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Ðеожиданное STO_SH5_ISA32 локального Ñимвола не обрабатываетÑÑ" + +#: elf32-sh.c:4304 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: оÑтанов: невыровненное назначение ветви Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ñ Ð¿Ð¾Ð´Ð´ÐµÑ€Ð¶ÐºÐ¾Ð¹ оÑлаблениÑ" + +#: elf32-sh.c:4337 elf32-sh.c:4352 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: оÑтанов: невыровненное %s перемещение 0x%lx" + +#: elf32-sh.c:4366 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: оÑтанов: R_SH_PSHA перемещение %d вне диапазона -32..32" + +#: elf32-sh.c:4380 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: оÑтанов: R_SH_PSHL перемещение %d вне диапазона -32..32" + +#: elf32-sh.c:4524 elf32-sh.c:4994 +msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" +msgstr "%B(%A+0x%lx): невозможно Ñгенерировать меÑтоположение к «%s» в разделе только Ð´Ð»Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ" + +#: elf32-sh.c:5101 +msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" +msgstr "%B(%A+0x%lx): перемещение %s Ð´Ð»Ñ Ð²Ð½ÐµÑˆÐ½ÐµÐ³Ð¾ Ñимвола «%s»" + +#: elf32-sh.c:5574 +#, c-format +msgid "%X%C: relocation to \"%s\" references a different segment\n" +msgstr "%X%C: перемещение указывает на ÑÑылки «%s» другого Ñегмента\n" + +#: elf32-sh.c:5580 +#, c-format +msgid "%C: warning: relocation to \"%s\" references a different segment\n" +msgstr "%C: предупреждение: перемещение указывает на ÑÑылки «%s» другого Ñегмента\n" + +#: elf32-sh.c:6358 elf32-sh.c:6441 +msgid "%B: `%s' accessed both as normal and FDPIC symbol" +msgstr "%B: «%s» доÑтупен как обычный и как FDPIC Ñимвол" + +#: elf32-sh.c:6363 elf32-sh.c:6445 +msgid "%B: `%s' accessed both as FDPIC and thread local symbol" +msgstr "%B: «%s» доÑтупен как FDPIC и как локальный Ñимвол нити" + +#: elf32-sh.c:6393 +msgid "%B: Function descriptor relocation with non-zero addend" +msgstr "%B: перемещение деÑкриптора функции Ñ Ð½ÐµÐ½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ добавлением" + +#: elf32-sh.c:6629 elf64-alpha.c:4560 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: локальный иÑполнÑемый код TLS не может быть Ñкомпонован Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ñемыми объектами" + +#: elf32-sh64.c:223 elf64-sh64.c:2314 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: Ñкомпилирован как 32-битный объект, а %s 64-битный" + +#: elf32-sh64.c:226 elf64-sh64.c:2317 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: Ñкомпилирован как 64-битный объект, а %s 32-битный" + +#: elf32-sh64.c:228 elf64-sh64.c:2319 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: размер объекта не ÑоответÑтвует Ñтой цели %s" + +#: elf32-sh64.c:451 elf64-sh64.c:2833 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: во входных данных обнаружен Ñимвол метки данных" + +#: elf32-sh64.c:528 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "неÑовпадение PTB: Ð°Ð´Ñ€ÐµÑ SHmedia (бит 0 == 1)" + +#: elf32-sh64.c:531 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "неÑовпадение PTA: Ð°Ð´Ñ€ÐµÑ SHcompact (бит 0 == 0)" + +#: elf32-sh64.c:549 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: ошибка GAS: неожиданный PTB insn Ñ R_SH_PT_16" + +#: elf32-sh64.c:598 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: ошибка: невыровненный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d по адреÑу %08x перемещение %p\n" + +#: elf32-sh64.c:674 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: не удалоÑÑŒ запиÑать добавленные Ñлементы .cranges" + +#: elf32-sh64.c:734 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: не удалоÑÑŒ запиÑать отÑортированные Ñлементы .cranges" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: Ñкомпилирован Ð´Ð»Ñ 64-битной ÑиÑтемы, а цель 32-битнаÑ" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: производитÑÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ° файлов Ñ Ð¾Ð±Ñ€Ð°Ñ‚Ð½Ñ‹Ð¼ порÑдком байт Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸ Ñ Ð¿Ñ€Ñмым порÑдком байт" + +#: elf32-spu.c:719 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: раздел Ð¾Ð²ÐµÑ€Ð»ÐµÑ %A не начинаетÑÑ Ñо Ñтроки кÑша.\n" + +#: elf32-spu.c:727 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: раздел Ð¾Ð²ÐµÑ€Ð»ÐµÑ %A больше Ñтроки кÑша.\n" + +#: elf32-spu.c:747 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: раздел Ð¾Ð²ÐµÑ€Ð»ÐµÑ %A не в облаÑти кÑша.\n" + +#: elf32-spu.c:787 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: разделы оверлеев %A и %A не начинаютÑÑ Ñ Ð¾Ð´Ð¸Ð½Ð°ÐºÐ¾Ð²Ð¾Ð³Ð¾ адреÑа.\n" + +#: elf32-spu.c:1011 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "предупреждение: в %B определён вызов Ñимвола не-функции %s" + +#: elf32-spu.c:1361 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) отличаетÑÑ Ð¾Ñ‚ анализируемого (%u)\n" + +#: elf32-spu.c:1880 +msgid "%B is not allowed to define %s" +msgstr "%B не разрешает определÑÑ‚ÑŒ %s" + +#: elf32-spu.c:1888 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "вам не разрешено определÑÑ‚ÑŒ %s в Ñценарии" + +#: elf32-spu.c:1922 +#, c-format +msgid "%s in overlay section" +msgstr "%s в разделе оверлеев" + +#: elf32-spu.c:1951 +msgid "overlay stub relocation overflow" +msgstr "переполнение оверлейной заглушки перемещениÑ" + +#: elf32-spu.c:1960 elf64-ppc.c:11327 +msgid "stubs don't match calculated size" +msgstr "заглушка не ÑоответÑтвует вычиÑленному размеру" + +#: elf32-spu.c:2542 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "предупреждение: %s перекрываетÑÑ Ñ %s\n" + +#: elf32-spu.c:2558 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "предупреждение: %s превышает размер раздела\n" + +#: elf32-spu.c:2589 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v не найдена в таблице функций\n" + +#: elf32-spu.c:2729 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): вызов не кодового раздела %B(%A), анализ не полон\n" + +#: elf32-spu.c:3297 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "Ð’ анализе Ñтека будет игнорироватьÑÑ Ð²Ñ‹Ð·Ð¾Ð² из %s в %s\n" + +#: elf32-spu.c:3988 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3989 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3994 +msgid " calls:\n" +msgstr " вызовы:\n" + +#: elf32-spu.c:4002 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4307 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s повторÑетÑÑ Ð² %s\n" + +#: elf32-spu.c:4311 +#, c-format +msgid "%s duplicated\n" +msgstr "%s повторÑетÑÑ\n" + +#: elf32-spu.c:4318 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "поддержка повторÑющихÑÑ Ð¾Ð±ÑŠÐµÐºÑ‚Ð½Ñ‹Ñ… файлов в Ñценарии auto-overlay пока не Ñделана\n" + +#: elf32-spu.c:4359 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "неоверлейный размер 0x%v Ð¿Ð»ÑŽÑ Ð¼Ð°ÐºÑимальный размер Ð¾Ð²ÐµÑ€Ð»ÐµÑ 0x%v превышает локальное хранилище\n" + +#: elf32-spu.c:4514 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s превышает размер оверлеÑ\n" + +#: elf32-spu.c:4676 +msgid "Stack size for call graph root nodes.\n" +msgstr "Размер Ñтека Ð´Ð»Ñ Ð²Ñ‹Ð·Ð¾Ð²Ð° графа корневых узлов.\n" + +#: elf32-spu.c:4677 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Размер Ñтека Ð´Ð»Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ð¹. ПримечаниÑ: '*' Ð¼Ð°ÐºÑ Ñтек, 't' хвоÑтовой вызов\n" + +#: elf32-spu.c:4687 +msgid "Maximum stack required is 0x%v\n" +msgstr "Ð”Ð»Ñ Ð¼Ð°ÐºÑимального Ñтека требуетÑÑ 0x%v\n" + +#: elf32-spu.c:4778 +msgid "fatal error while creating .fixup" +msgstr "неиÑÐ¿Ñ€Ð°Ð²Ð¸Ð¼Ð°Ñ Ð¾ÑˆÐ¸Ð±ÐºÐ° при Ñоздании .fixup" + +#: elf32-spu.c:5006 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s+0x%lx): неразрешённое перемещение %s Ð´Ð»Ñ Ñимвола `%s'" + +#: elf32-tic6x.c:1539 +msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" +msgstr "%B: отноÑительное перемещение SB, но __c6xabi_DSBT_BASE не определён" + +#. Shared libraries and exception handling support not +#. implemented. +#: elf32-tic6x.c:1554 +msgid "%B: relocation type %d not implemented" +msgstr "%B: тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Â«%s» не реализован" + +#: elf32-tic6x.c:1640 +msgid "dangerous relocation" +msgstr "опаÑное перемещение" + +#: elf32-tic6x.c:1788 elf32-tic6x.c:1796 +msgid "error: %B requires more stack alignment than %B preserves" +msgstr "ошибка: Ð´Ð»Ñ %B требуетÑÑ Ð±Ð¾Ð»ÑŒÑˆÐµÐµ выравнивание Ñтека, чем Ñохранено в %B" + +#: elf32-tic6x.c:1806 elf32-tic6x.c:1815 +msgid "error: unknown Tag_ABI_array_object_alignment value in %B" +msgstr "ошибка: неизвеÑтное значение Tag_ABI_array_object_alignment в %B" + +#: elf32-tic6x.c:1824 elf32-tic6x.c:1833 +msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" +msgstr "ошибка: неизвеÑтное значение Tag_ABI_array_object_align_expected в %B" + +#: elf32-tic6x.c:1841 elf32-tic6x.c:1848 +msgid "error: %B requires more array alignment than %B preserves" +msgstr "ошибка: Ð´Ð»Ñ %B требуетÑÑ Ð±Ð¾Ð»ÑŒÑˆÐµÐµ выравнивание маÑÑива, чем Ñохранено в %B" + +#: elf32-tic6x.c:1870 +msgid "warning: %B and %B differ in wchar_t size" +msgstr "предупреждение: в %B и %B различаетÑÑ Ñ€Ð°Ð·Ð¼ÐµÑ€ wchar_t" + +#: elf32-tic6x.c:1888 +msgid "warning: %B and %B differ in whether code is compiled for DSBT" +msgstr "предупреждение: в %B и %B по-разному Ñкомпилирован код Ð´Ð»Ñ DSBT" + +#: elf32-tic6x.c:1898 +msgid "warning: %B and %B differ in position-dependence of data addressing" +msgstr "предупреждение: в %B и %B различаетÑÑ Ð°Ð´Ñ€ÐµÑÐ°Ñ†Ð¸Ñ Ð½ÐµÐ·Ð°Ð²Ð¸Ñимых по Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ Ð´Ð°Ð½Ð½Ñ‹Ñ…" + +#: elf32-tic6x.c:1908 +msgid "warning: %B and %B differ in position-dependence of code addressing" +msgstr "предупреждение: в %B и %B различаетÑÑ Ð°Ð´Ñ€ÐµÑÐ°Ñ†Ð¸Ñ Ð½ÐµÐ·Ð°Ð²Ð¸Ñимого по Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐºÐ¾Ð´Ð°" + +#: elf32-v850.c:173 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' не может занимать неÑколько маленьких облаÑтей данных" + +#: elf32-v850.c:176 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' может быть только в одном из маленьких, нулевых и крошечных облаÑтей данных" + +#: elf32-v850.c:179 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' не может быть в маленьких и нулевых облаÑÑ‚ÑÑ… данных одновременно" + +#: elf32-v850.c:182 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' не может быть в маленьких и крошечных облаÑÑ‚ÑÑ… данных одновременно" + +#: elf32-v850.c:185 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ð°Ñ `%s' не может быть в нулевых и крошечных облаÑÑ‚ÑÑ… данных одновременно" + +#: elf32-v850.c:483 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "ÐЕ УДÐЛОСЬ найти предыдущее перемещение HI16\n" + +#: elf32-v850.c:2155 +msgid "could not locate special linker symbol __gp" +msgstr "невозможно отыÑкать Ñпециальный Ñимвол компоновки __gp" + +#: elf32-v850.c:2159 +msgid "could not locate special linker symbol __ep" +msgstr "невозможно отыÑкать Ñпециальный Ñимвол компоновки __ep" + +#: elf32-v850.c:2163 +msgid "could not locate special linker symbol __ctbp" +msgstr "невозможно отыÑкать Ñпециальный Ñимвол компоновки __ctbp" + +#: elf32-v850.c:2341 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: Ðрхитектура не Ñовпадает Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼Ð¸ модулÑми" + +#. xgettext:c-format. +#: elf32-v850.c:2360 +#, c-format +msgid "private flags = %lx: " +msgstr "ÑобÑтвенные флаги = %lx: " + +#: elf32-v850.c:2365 +#, c-format +msgid "v850 architecture" +msgstr "архитектура v850" + +#: elf32-v850.c:2366 +#, c-format +msgid "v850e architecture" +msgstr "архитектура v850e" + +#: elf32-v850.c:2367 +#, c-format +msgid "v850e1 architecture" +msgstr "архитектура v850e1" + +#: elf32-v850.c:2368 +#, c-format +msgid "v850e2 architecture" +msgstr "архитектура v850e2" + +#: elf32-v850.c:2369 +#, c-format +msgid "v850e2v3 architecture" +msgstr "архитектура v850e2v3" + +#: elf32-vax.c:531 +#, c-format +msgid " [nonpic]" +msgstr " [не-pic]" + +#: elf32-vax.c:534 +#, c-format +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:537 +#, c-format +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:654 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: предупреждение: добавление GOT из %ld к `%s' не Ñовпадает Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼ добавлением GOT из %ld" + +#: elf32-vax.c:1587 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: предупреждение: добавление PLT из %d к `%s' из раздела %s игнорируетÑÑ" + +#: elf32-vax.c:1714 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: предупреждение: перемещение %s Ð´Ð»Ñ Ñимвола `%s' из раздела %s" + +#: elf32-vax.c:1720 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: предупреждение: перемещение %s к 0x%x из раздела %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2861 elf64-ia64.c:2861 +msgid "non-zero addend in @fptr reloc" +msgstr "ненулевое добавление в перемещение @fptr" + +#: elf32-xtensa.c:918 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): недопуÑÑ‚Ð¸Ð¼Ð°Ñ Ñ‚Ð°Ð±Ð»Ð¸Ñ†Ð° ÑвойÑтв" + +#: elf32-xtensa.c:2780 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): Ñмещение Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð²Ð½Ðµ диапазона (размер=0x%x)" + +#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +msgid "dynamic relocation in read-only section" +msgstr "динамичеÑкое перемещение в разделе только Ð´Ð»Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ" + +#: elf32-xtensa.c:2956 +msgid "TLS relocation invalid without dynamic sections" +msgstr "TLS-перемещение недопуÑтимо без динамичеÑких разделов" + +#: elf32-xtensa.c:3173 +msgid "internal inconsistency in size of .got.loc section" +msgstr "внутреннÑÑ Ð½ÐµÑоглаÑованноÑÑ‚ÑŒ размера раздела .got.loc" + +#: elf32-xtensa.c:3486 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: неÑовмеÑтимый машинный тип. Выходной 0x%x. Входной 0x%x" + +#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Попытка Ð¿Ñ€ÐµÐ¾Ð±Ñ€Ð°Ð·Ð¾Ð²Ð°Ð½Ð¸Ñ L32R/CALLX в CALL завершилаÑÑŒ неудачно" + +#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): невозможно декодировать инÑтрукцию; возможно неÑовпадение конфигурации" + +#: elf32-xtensa.c:7265 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): невозможно декодировать инÑтрукцию Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ XTENSA_ASM_SIMPLIFY; возможно неÑовпадение конфигурации" + +#: elf32-xtensa.c:9024 +msgid "invalid relocation address" +msgstr "недопуÑтимый Ð°Ð´Ñ€ÐµÑ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ" + +#: elf32-xtensa.c:9073 +msgid "overflow after relaxation" +msgstr "переполнение поÑле оÑлаблениÑ" + +#: elf32-xtensa.c:10205 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): неожиданное назначение Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s" + +#: elf64-alpha.c:460 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "Ðе найдены инÑтрукции ldah и lda Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ GPDISP" + +#: elf64-alpha.c:2408 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: подраздел .got превышает 64K (размер %d)" + +#: elf64-alpha.c:4304 elf64-alpha.c:4316 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: gp-отноÑительное перемещение Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf64-alpha.c:4342 elf64-alpha.c:4477 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: pc-отноÑительное перемещение Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf64-alpha.c:4370 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: изменение в gp: BRSGP %s" + +#: elf64-alpha.c:4395 +msgid "" +msgstr "<неизвеÑтно>" + +#: elf64-alpha.c:4400 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: перемещение !samegp Ð´Ð»Ñ Ñимвола без .prologue: %s" + +#: elf64-alpha.c:4452 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: необработанное динамичеÑкое перемещение Ð´Ð»Ñ %s" + +#: elf64-alpha.c:4484 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: pc-отноÑительное перемещение Ð´Ð»Ñ Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð¾Ð³Ð¾ Ñлабого Ñимвола %s" + +#: elf64-alpha.c:4544 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: dtp-отноÑительное перемещение Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf64-alpha.c:4567 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: tp-отноÑительное перемещение Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf64-hppa.c:2101 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "Ñлемент заглушки Ð´Ð»Ñ %s не может загрузить .plt, Ñмещение dp = %ld" + +#: elf64-hppa.c:3299 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): невозможно добратьÑÑ Ð´Ð¾ %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Ошибка внутреннего неÑоответÑÑ‚Ð²Ð¸Ñ Ð´Ð»Ñ Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ\n" +" глобального региÑтра назначаемого компоновщиком: Ñкомпонован: 0x%lx%08lx != оÑлаблен: 0x%lx%08lx\n" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: перемещение база-плюÑ-Ñмещение Ð´Ð»Ñ Ñ€ÐµÐ³Ð¸Ñтрового Ñимвола: (неизвеÑтно) в %s" + +#: elf64-mmix.c:1612 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: перемещение база-плюÑ-Ñмещение Ð´Ð»Ñ Ñ€ÐµÐ³Ð¸Ñтрового Ñимвола: %s в %s" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: региÑтровое перемещение Ð´Ð»Ñ Ð½ÐµÑ€ÐµÐ³Ð¸Ñтрового Ñимвола: (неизвеÑтно) в %s" + +#: elf64-mmix.c:1661 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: региÑтровое перемещение Ð´Ð»Ñ Ð½ÐµÑ€ÐµÐ³Ð¸Ñтрового Ñимвола: %s в %s" + +#: elf64-mmix.c:1698 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: директива LOCAL разрешена только Ñ Ñ€ÐµÐ³Ð¸Ñтром или абÑолютным значением" + +#: elf64-mmix.c:1726 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: директива LOCAL: РегиÑÑ‚Ñ€ $%ld не ÑвлÑетÑÑ Ð»Ð¾ÐºÐ°Ð»ÑŒÐ½Ñ‹Ð¼ региÑтром. Первый глобальный региÑÑ‚Ñ€: $%ld." + +#: elf64-mmix.c:2190 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Ошибка: множеÑтвенные объÑÐ²Ð»ÐµÐ½Ð¸Ñ `%s'; начало %s уÑтановлено в ранее Ñкомпонованном файле\n" + +#: elf64-mmix.c:2248 +msgid "Register section has contents\n" +msgstr "Ð’ региÑтровом разделе имеетÑÑ Ñодержимое\n" + +#: elf64-mmix.c:2440 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Внутреннее противоречие: оÑтаётÑÑ %u != Ð¼Ð°ÐºÑ %u.\n" +" Сообщите об ошибке." + +#: elf64-ppc.c:2741 libbfd.c:997 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: Ñкомпилировано Ð´Ð»Ñ ÑиÑтемы Ñ Ð¿Ñ€Ñмым порÑдком байт, а цель Ñ Ð¾Ð±Ñ€Ð°Ñ‚Ð½Ñ‹Ð¼ порÑдком байт" + +#: elf64-ppc.c:2744 libbfd.c:999 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: Ñкомпилировано Ð´Ð»Ñ ÑиÑтемы Ñ Ð¾Ð±Ñ€Ð°Ñ‚Ð½Ñ‹Ð¼ порÑдком байт, а цель Ñ Ð¿Ñ€Ñмым порÑдком байт" + +#: elf64-ppc.c:6473 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "копирование Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð´Ð»Ñ `%s' требует ленивой plt-компоновки; не задавайте LD_BIND_NOW=1 или обновите gcc" + +#: elf64-ppc.c:6901 +msgid "dynreloc miscount for %B, section %A" +msgstr "ошибка в вычиÑлении dynreloc %B, раздел %A" + +#: elf64-ppc.c:6985 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd не ÑвлÑетÑÑ Ð¾Ð±Ñ‹Ñ‡Ð½Ñ‹Ð¼ маÑÑивом Ñлементов opd" + +#: elf64-ppc.c:6994 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: неожиданный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %u в разделе .opd" + +#: elf64-ppc.c:7015 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: неопределённый Ñимвол `%s' в разделе .opd" + +#: elf64-ppc.c:7877 elf64-ppc.c:8392 +#, c-format +msgid "%s defined on removed toc entry" +msgstr "%s определён на удалённом Ñлементе toc" + +#: elf64-ppc.c:9459 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "переполнение ÑÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð·Ð°Ð³Ð»ÑƒÑˆÐºÐ¸ длинного перехода «%s»" + +#: elf64-ppc.c:9518 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "не найдена заглушка перехода `%s'" + +#: elf64-ppc.c:9580 elf64-ppc.c:9716 +#, c-format +msgid "linkage table error against `%s'" +msgstr "ошибка в таблице компоновки Ð´Ð»Ñ `%s'" + +#: elf64-ppc.c:9886 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "невозможно Ñобрать заглушку перехода `%s'" + +#: elf64-ppc.c:10684 +msgid "%B section %A exceeds stub group size" +msgstr "%B раздел %A превышает групповой размер заглушки" + +#: elf64-ppc.c:11339 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"заглушки компоновщика в %u группе%s\n" +" переход %lu\n" +" иÑправление toc %lu\n" +" длинный переход %lu\n" +" иÑправление длинного long %lu\n" +" plt-вызовl %lu" + +#: elf64-ppc.c:12190 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): автоматичеÑкие множеÑтвенные TOC не поддерживаютÑÑ Ñ‡ÐµÑ€ÐµÐ· ваши файлы crt; перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -mminimal-toc или обновите gcc" + +#: elf64-ppc.c:12198 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): Ð¾Ð¿Ñ‚Ð¸Ð¼Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¾Ð´Ð½Ð¾ÑƒÑ€Ð¾Ð²Ð½ÐµÐ²Ñ‹Ñ… вызовов к `%s' не разрешена из-за автоматичеÑких множеÑтвенных TOC; перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -mminimal-toc или -fno-optimize-sibling-calls, или Ñоздайте внешний `%s'" + +#: elf64-ppc.c:12919 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: перемещение %s не поддерживаетÑÑ Ð´Ð»Ñ Ñимвола %s." + +#: elf64-ppc.c:13096 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: ошибка: перемещение %s не кратно %d" + +#: elf64-sh64.c:1682 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: ошибка: невыровненный тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d по адреÑу %08x перемещение %08x\n" + +#: elf64-sparc.c:444 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Только региÑтры %%g[2367] могут объÑвлÑÑ‚ÑŒÑÑ Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ STT_REGISTER" + +#: elf64-sparc.c:464 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "ÐеÑовмеÑтимое иÑпользование региÑтра %%g%d: %s в %B, ранее %s в %B" + +#: elf64-sparc.c:487 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Символ `%s' имеет различные типы: REGISTER в %B, ранее %s в %B" + +#: elf64-sparc.c:532 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Символ `%s' имеет различные типы: %s в %B, ранее REGISTER в %B" + +#: elf64-sparc.c:684 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: UltraSPARC-ÑÐ¿ÐµÑ†Ð¸Ñ„Ð¸Ñ‡Ð½Ð°Ñ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ° Ñ HAL-Ñпецифичным кодом" + +#: elf64-x86-64.c:1360 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B: '%s' доÑтупен как обычный и как локальный Ð´Ð»Ñ Ð½Ð¸Ñ‚Ð¸ Ñимвол" + +#: elf64-x86-64.c:2801 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: перемещение %s вмеÑте Ñ STT_GNU_IFUNC Ñимволом %s имеет ненулевое добавление: %d" + +#: elf64-x86-64.c:3073 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: перемещение R_X86_64_GOTOFF64 Ð´Ð»Ñ Ð·Ð°Ñ‰Ð¸Ñ‰Ñ‘Ð½Ð½Ð¾Ð¹ функции `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта" + +#: elf64-x86-64.c:3184 +msgid "; recompile with -fPIC" +msgstr "; перекомпилируйте Ñ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ð¾Ð¼ -fPIC" + +#: elf64-x86-64.c:3189 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: перемещение %s Ð´Ð»Ñ %s `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта(ов)" + +#: elf64-x86-64.c:3191 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: перемещение %s Ð´Ð»Ñ Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð¾Ð³Ð¾ %s `%s' не может иÑпользоватьÑÑ Ð¿Ñ€Ð¸ Ñоздании разделÑемого объекта(ов)" + +#: elfcode.h:826 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "предупреждение: у %s повреждена таблица индекÑов Ñтрок - игнорируетÑÑ" + +#: elfcode.h:1236 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: Ñчётчик верÑии (%ld) не Ñовпадает Ñо Ñчётчиком Ñимвола (%ld)" + +#: elfcode.h:1476 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): перемещение %d имеет недопуÑтимый Ð¸Ð½Ð´ÐµÐºÑ Ñимвола %ld" + +#: elfcore.h:312 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Предупреждение: %B уÑечён: ожидалÑÑ Ñ€Ð°Ð·Ð¼ÐµÑ€ Ñдра файла >= %lu, найдено: %lu." + +#: elflink.c:1119 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-определение в %B раздела %A не Ñовпадает Ñ Ð½Ðµ-TLS определением в %B раздела %A" + +#: elflink.c:1123 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: TLS-ÑÑылка в %B не Ñовпадает Ñ Ð½Ðµ-TLS ÑÑылкой в %B" + +#: elflink.c:1127 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: TLS-определение в %B раздела %A не Ñовпадает Ñ Ð½Ðµ-TLS ÑÑылкой в %B" + +#: elflink.c:1131 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: TLS-ÑÑылка в %B не Ñовпадает Ñ Ð½Ðµ-TLS определением в %B раздела %A" + +#: elflink.c:1763 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: неожиданное переопределение коÑвенного верÑионного Ñимвола `%s'" + +#: elflink.c:2076 +msgid "%B: version node not found for symbol %s" +msgstr "%B: верÑÐ¸Ñ ÑƒÐ·Ð»Ð° не найдена Ð´Ð»Ñ Ñимвола %s" + +#: elflink.c:2166 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: неправильный Ð¸Ð½Ð´ÐµÐºÑ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰Ð°ÐµÐ¼Ð¾Ð³Ð¾ Ñимвола (0x%lx >= 0x%lx) Ð´Ð»Ñ ÑÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ 0x%lx в разделе `%A'" + +#: elflink.c:2177 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: ненулевой Ð¸Ð½Ð´ÐµÐºÑ Ñимвола (0x%lx) Ð´Ð»Ñ ÑÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ 0x%lx в разделе `%A', в то Ð²Ñ€ÐµÐ¼Ñ ÐºÐ°Ðº в объектном файле нет таблицы Ñимволов" + +#: elflink.c:2367 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: размер Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð½Ðµ Ñовпадает в %B раздела %A" + +#: elflink.c:2662 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "предупреждение: тип и размер динамичеÑкого Ñимвола `%s' не определён" + +#: elflink.c:3418 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: обнаружен альтернативный машинный код ELF (%d) в %B, ожидаетÑÑ %d\n" + +#: elflink.c:4050 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: недопуÑÑ‚Ð¸Ð¼Ð°Ñ Ð²ÐµÑ€ÑÐ¸Ñ %u (Ð¼Ð°ÐºÑ %d)" + +#: elflink.c:4086 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: недопуÑÑ‚Ð¸Ð¼Ð°Ñ Ð½ÐµÐ¾Ð±Ñ…Ð¾Ð´Ð¸Ð¼Ð°Ñ Ð²ÐµÑ€ÑÐ¸Ñ %d" + +#: elflink.c:4285 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Предупреждение: выравнивание %u общего Ñимвола `%s' в %B больше, чем выравнивание (%u) его раздела %A" + +#: elflink.c:4291 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Предупреждение: выравнивание %u Ñимвола `%s' в %B меньше, чем %u в %B" + +#: elflink.c:4306 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Предупреждение: размер Ñимвола `%s' изменилÑÑ Ñ %lu в %B на %lu в %B" + +#: elflink.c:4472 +msgid "%B: undefined reference to symbol '%s'" +msgstr "%B: Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð°Ñ ÑÑылка на Ñимвол «%s»" + +#: elflink.c:4475 +msgid "note: '%s' is defined in DSO %B so try adding it to the linker command line" +msgstr "замечание: «%s» определён в DSO %B, попробуйте добавить его в командную Ñтроку компоновщика" + +#: elflink.c:5779 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð°Ñ Ð²ÐµÑ€ÑиÑ: %s" + +#: elflink.c:5847 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: раздел .preinit_array не разрешаетÑÑ Ð² DSO" + +#: elflink.c:7598 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "Ð½ÐµÐ¾Ð¿Ñ€ÐµÐ´ÐµÐ»Ñ‘Ð½Ð½Ð°Ñ ÑÑылка %s в Ñложном Ñимволе: %s" + +#: elflink.c:7752 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "неизвеÑтный оператор '%c' в Ñложном Ñимволе" + +#: elflink.c:8091 elflink.c:8108 elflink.c:8145 elflink.c:8162 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Ðевозможно отÑортировать Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ - они разных размеров" + +#: elflink.c:8122 elflink.c:8176 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Ðевозможно отÑортировать Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ - они неизвеÑтного размера" + +#: elflink.c:8227 +msgid "Not enough memory to sort relocations" +msgstr "ÐедоÑтаточно памÑти Ð´Ð»Ñ Ñортировки перемещений" + +#: elflink.c:8420 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Слишком много разделов: %d (>= %d)" + +#: elflink.c:8663 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: %s Ñимвол `%s' в %B указываетÑÑ Ð¸Ð· DSO" + +#: elflink.c:8754 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: невозможно найти выходной раздел %A Ð´Ð»Ñ Ð²Ñ…Ð¾Ð´Ð½Ð¾Ð³Ð¾ раздела %A" + +#: elflink.c:8874 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: %s Ñимвол `%s' не определён" + +#: elflink.c:9428 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "ошибка: %B Ñодержит перемещение (0x%s) Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° %A, который ÑÑылаетÑÑ Ð½Ð° неÑущеÑтвующий глобальный Ñимвол" + +#: elflink.c:9494 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X`%s' указывает в раздел `%A' из %B: определён в отброшенном разделе `%A' из %B\n" + +#: elflink.c:10141 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A Ñодержит упорÑдоченные [`%A' в %B] и неупорÑдоченные [`%A' в %B] разделы" + +#: elflink.c:10146 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A Ñодержит упорÑдоченные и неупорÑдоченные разделы" + +#: elflink.c:10992 elflink.c:11036 +msgid "%B: could not find output section %s" +msgstr "%B: невозможно найти выходной раздел %s" + +#: elflink.c:10997 +#, c-format +msgid "warning: %s section has zero size" +msgstr "предупреждение: раздел %s имеет нулевой размер" + +#: elflink.c:11102 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: предупреждение: ÑоздаётÑÑ DT_TEXTREL в разделÑемом объекте.\n" + +#: elflink.c:11289 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: невозможно прочитать Ñимволы: %E\n" + +#: elflink.c:11638 +msgid "Removing unused section '%s' in file '%B'" +msgstr "УдалÑетÑÑ Ð½ÐµÐ¸Ñпользуемый раздел '%s' в файле '%B'" + +#: elflink.c:11850 +msgid "Warning: gc-sections option ignored" +msgstr "Предупреждение: параметр gc-sections игнорируетÑÑ" + +#: elflink.c:12399 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: игнорируетÑÑ Ð¿Ð¾Ð²Ñ‚Ð¾Ñ€ÑющийÑÑ Ñ€Ð°Ð·Ð´ÐµÐ» `%A'" + +#: elflink.c:12406 elflink.c:12413 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: повторÑющийÑÑ Ñ€Ð°Ð·Ð´ÐµÐ» `%A' имеет другой размер" + +#: elflink.c:12421 elflink.c:12426 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: предупреждение: невозможно прочитать Ñодержимое раздела `%A'" + +#: elflink.c:12430 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: предупреждение: повторÑющийÑÑ Ñ€Ð°Ð·Ð´ÐµÐ» `%A' имеет другое Ñодержимое" + +#: elflink.c:12531 linker.c:3138 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1220 +msgid "static procedure (no name)" +msgstr "ÑтатичеÑÐºÐ°Ñ Ð¿Ñ€Ð¾Ñ†ÐµÐ´ÑƒÑ€Ð° (без имени)" + +#: elfxx-mips.c:5623 +msgid "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider recompiling with interlinking enabled." +msgstr "%B: %A+0x%lx: прÑмые переходы между режимами ISA недопуÑтимы; попробуйте перекомпилировать Ñ Ð²ÐºÐ»ÑŽÑ‡Ñ‘Ð½Ð½Ð¾Ð¹ увÑзкой." + +#: elfxx-mips.c:6280 elfxx-mips.c:6503 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: предупреждение: размер параметра «%s» (%u) меньше, чем его заголовок" + +#: elfxx-mips.c:7254 elfxx-mips.c:7379 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: Предупреждение: невозможно определить функцию Ð½Ð°Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ Ð´Ð»Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° заглушки `%s'" + +#: elfxx-mips.c:7508 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Обнаружено иÑкажённое перемещение в разделе %s" + +#: elfxx-mips.c:7548 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: перемещение GOT по адреÑу 0x%lx не ожидаетÑÑ Ð² иÑполнÑемых файлах" + +#: elfxx-mips.c:7670 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: перемещение CALL16 по адреÑу 0x%lx не предназначено Ð´Ð»Ñ Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð¾Ð³Ð¾ Ñимвола" + +#: elfxx-mips.c:8365 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "не-динамичеÑкие Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ ÑƒÐºÐ°Ð·Ñ‹Ð²Ð°ÑŽÑ‚ на динамичеÑкий Ñимвол %s" + +#: elfxx-mips.c:9068 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Ðевозможно найти подходÑщее LO16 перемещение у `%s' Ð´Ð»Ñ %s по адреÑу 0x%lx в разделе `%A'" + +#: elfxx-mips.c:9207 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "раздел small-data превышает 64КБ - нижний предел small-data (Ñм. параметр -G)" + +#: elfxx-mips.c:12027 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: недопуÑтимое Ð¸Ð¼Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° `%s'" + +#: elfxx-mips.c:12405 elfxx-mips.c:12431 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Предупреждение: %B иÑпользует -msingle-float, %B иÑпользует -mdouble-float" + +#: elfxx-mips.c:12417 elfxx-mips.c:12473 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Предупреждение: %B иÑпользует -msingle-float, %B иÑпользует -mips32r2 -mfp64" + +#: elfxx-mips.c:12443 elfxx-mips.c:12479 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Предупреждение: %B иÑпользует -mdouble-float, %B иÑпользует -mips32r2 -mfp64" + +#: elfxx-mips.c:12521 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: порÑдок байт не ÑовмеÑтим Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ð¼ в ÑмулÑции" + +#: elfxx-mips.c:12532 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI не ÑовмеÑтим Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ð¼ в ÑмулÑции" + +#: elfxx-mips.c:12613 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: предупреждение: компоновка файлов abicalls Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸ не-abicalls" + +#: elfxx-mips.c:12630 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: компоновка 32-битного кода Ñ 64-битным кодом" + +#: elfxx-mips.c:12658 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: компоновка Ð¼Ð¾Ð´ÑƒÐ»Ñ %s Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼Ð¸ модулÑми %s" + +#: elfxx-mips.c:12681 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: неÑовпадение ABI: компоновка Ð¼Ð¾Ð´ÑƒÐ»Ñ %s Ñ Ð¿Ñ€ÐµÐ´Ñ‹Ð´ÑƒÑ‰Ð¸Ð¼Ð¸ модулÑми %s" + +#: elfxx-mips.c:12845 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12847 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12849 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12851 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12853 +#, c-format +msgid " [abi unknown]" +msgstr " [abi неизвеÑтен]" + +#: elfxx-mips.c:12855 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12857 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12859 +#, c-format +msgid " [no abi set]" +msgstr " [abi не задан]" + +#: elfxx-mips.c:12880 +#, c-format +msgid " [unknown ISA]" +msgstr " [неизвеÑтный ISA]" + +#: elfxx-mips.c:12891 +#, c-format +msgid " [not 32bitmode]" +msgstr " [не 32-битный режим]" + +#: elfxx-sparc.c:595 +#, c-format +msgid "invalid relocation type %d" +msgstr "недопуÑтимый тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %d" + +#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Ð”Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð½Ð¾Ð³Ð¾ файла требуетÑÑ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑÐºÐ°Ñ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ° `%s'\n" + +#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Ð”Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð½Ð¾Ð³Ð¾ файла требуетÑÑ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑÐºÐ°Ñ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ° `%s.so.%s'\n" + +#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 +#: sparclinux.c:650 sparclinux.c:700 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Символ %s не определён Ð´Ð»Ñ Ð¼ÐµÑтоположений\n" + +#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +msgid "Warning: fixup count mismatch\n" +msgstr "Предупреждение: не Ñовпадает Ñчётчик меÑтоположениÑ\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: Ñлишком Ð´Ð»Ð¸Ð½Ð½Ð°Ñ Ñтрока (%d Ñимволов, макÑ. 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: нераÑпознанные флаги Ñимвола `%s' (0x%x)" + +#: ieee.c:792 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: Ð½ÐµÑ€ÐµÐ°Ð»Ð¸Ð·Ð¾Ð²Ð°Ð½Ð½Ð°Ñ ATI-запиÑÑŒ %u Ð´Ð»Ñ Ñимвола %u" + +#: ieee.c:816 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: неожиданный ATN-тип %d во внешней чаÑти" + +#: ieee.c:838 +msgid "%B: unexpected type after ATN" +msgstr "%B: неожиданный тип поÑле ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: неожиданный Ñимвол `%s' в Intel Hex файле" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%u: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»ÑŒÐ½Ð°Ñ Ñумма в Intel Hex файле (должна быть %u, получена %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%u: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ Ð´Ð»Ð¸Ð½Ð° запиÑи раÑширенного адреÑа в Intel Hex файле" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%u: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ Ð´Ð»Ð¸Ð½Ð° раÑширенного начального адреÑа в Intel Hex файле" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%u: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ Ð´Ð»Ð¸Ð½Ð° запиÑи раÑширенного прÑмолинейного адреÑа в Intel Hex файле" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%u: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ Ð´Ð»Ð¸Ð½Ð° раÑширенного прÑмолинейного начального адреÑа в Intel Hex файле" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%u: нераÑпознанный ihex-тип %u в Intel Hex файле" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ° в ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: Ð½ÐµÐ¿Ñ€Ð°Ð²Ð¸Ð»ÑŒÐ½Ð°Ñ Ð´Ð»Ð¸Ð½Ð° раздела в ihex_read_section" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: Ð°Ð´Ñ€ÐµÑ 0x%s вне диапазона Ð´Ð»Ñ Intel Hex файла" + +#: libbfd.c:863 +msgid "%B: unable to get decompressed section %A" +msgstr "Ошибка в dwarf: не удалоÑÑŒ получить раÑжатый раздел %A" + +#: libbfd.c:1027 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Вызван нерекомендуемый %s Ñ€Ñдом Ñ %s в Ñтроке %d в %s\n" + +#: libbfd.c:1030 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Вызван нерекомендуемый %s\n" + +#: linker.c:1911 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: коÑвенный Ñимвол `%s' к `%s' Ñоздаёт зацикливание" + +#: linker.c:2778 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Попытка Ñделать перемещаемую ÑÑылку Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð¼ %s и выходом %s" + +#: linker.c:3105 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: предупреждение: игнорируетÑÑ Ð¿Ð¾Ð²Ñ‚Ð¾Ñ€ÑющийÑÑ Ñ€Ð°Ð·Ð´ÐµÐ» `%A'\n" + +#: linker.c:3119 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: предупреждение: повторÑющийÑÑ Ñ€Ð°Ð·Ð´ÐµÐ» `%A' имеет другой размер\n" + +#: mach-o.c:3403 +msgid "Mach-O header:\n" +msgstr "заголовок Mach-O:\n" + +#: mach-o.c:3404 +#, c-format +msgid " magic : %08lx\n" +msgstr " отл.призн : %08lx\n" + +#: mach-o.c:3405 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " тип ЦП : %08lx (%s)\n" + +#: mach-o.c:3407 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " подтип ЦП : %08lx\n" + +#: mach-o.c:3408 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " тип файла : %08lx (%s)\n" + +#: mach-o.c:3411 +#, c-format +msgid " ncmds : %08lx (%lu)\n" +msgstr " ч_кмнд : %08lx (%lu)\n" + +#: mach-o.c:3412 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " разм_кмнд : %08lx\n" + +#: mach-o.c:3413 +#, c-format +msgid " flags : %08lx (" +msgstr " флаги : %08lx (" + +#: mach-o.c:3415 vms-alpha.c:7652 +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3416 +#, c-format +msgid " reserved : %08x\n" +msgstr " зарезерв : %08x\n" + +#: mach-o.c:3426 +msgid "Segments and Sections:\n" +msgstr "Сегменты и разделы:\n" + +#: mach-o.c:3427 +msgid " #: Segment name Section name Address\n" +msgstr "" +" #: Segment name Section name Address\n" +" #: Ðазвание Ñегм Ðазвание раздела ÐдреÑ\n" + +#: merge.c:832 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: доÑтуп за конец объединённого раздела (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Ðет оÑÐ½Ð¾Ð²Ð°Ð½Ð¸Ñ Ð´Ð»Ñ Ð²Ñ‹Ð´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¸Ð¼ÐµÐ½Ð¸ раздела %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Ðет оÑÐ½Ð¾Ð²Ð°Ð½Ð¸Ñ Ð´Ð»Ñ Ð²Ñ‹Ð´ÐµÐ»ÐµÐ½Ð¸Ñ Ñимвольных %d байт\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: недопуÑтимый mmo-файл: инициализационное значение Ð´Ð»Ñ $255 не равно `Main'\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: Ð½ÐµÐ¿Ð¾Ð´Ð´ÐµÑ€Ð¶Ð¸Ð²Ð°ÐµÐ¼Ð°Ñ Ð¿Ð¾ÑледовательноÑÑ‚ÑŒ широких Ñимволов 0x%02X 0x%02X поÑле имени Ñимвола, начинающегоÑÑ Ñ `%s'\n" + +#: mmo.c:1565 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: недопуÑтимый mmo-файл: неподдерживаемый lopcode `%d'\n" + +#: mmo.c:1575 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: недопуÑтимый mmo-файл: ожидалоÑÑŒ YZ = 1, получено YZ = %d Ð´Ð»Ñ lop_quote\n" + +#: mmo.c:1611 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: недопуÑтимый mmo-файл: ожидалоÑÑŒ z = 1 или z = 2, получено z = %d Ð´Ð»Ñ lop_loc\n" + +#: mmo.c:1657 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: недопуÑтимый mmo-файл: ожидалоÑÑŒ z = 1 или z = 2, получено z = %d Ð´Ð»Ñ lop_fixo\n" + +#: mmo.c:1696 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: недопуÑтимый mmo-файл: ожидалоÑÑŒ y = 0, получено y = %d Ð´Ð»Ñ lop_fixrx\n" + +#: mmo.c:1705 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: недопуÑтимый mmo-файл: ожидалоÑÑŒ z = 16 или z = 24, получено z = %d Ð´Ð»Ñ lop_fixrx\n" + +#: mmo.c:1728 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: недопуÑтимый mmo-файл: начальный байт Ñлова операнда должен быть равен 0 или 1, получено %d Ð´Ð»Ñ lop_fixrx\n" + +#: mmo.c:1751 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: невозможно выделить меÑто Ð´Ð»Ñ Ð¸Ð¼ÐµÐ½Ð¸ файла к файлу Ñ Ð½Ð¾Ð¼ÐµÑ€Ð¾Ð¼ %d, %d байт\n" + +#: mmo.c:1771 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: недопуÑтимый mmo-файл: номер файла %d `%s', был уже введён как `%s'\n" + +#: mmo.c:1784 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: недопуÑтимый mmo-файл: Ð¸Ð¼Ñ Ñ„Ð°Ð¹Ð»Ð° Ð´Ð»Ñ Ð½Ð¾Ð¼ÐµÑ€Ð° %d не указано перед иÑпользованием\n" + +#: mmo.c:1890 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: недопуÑтимый mmo-файл: Ð¿Ð¾Ð»Ñ y и z в lop_stab не равны нулю, y: %d, z: %d\n" + +#: mmo.c:1926 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: недопуÑтимый mmo-файл: lop_end не поÑледний Ñлемент в файле\n" + +#: mmo.c:1939 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: недопуÑтимый mmo-файл: YZ в lop_end (%ld) не равно чиÑлу тетрад в указанной ранее lop_stab (%ld)\n" + +#: mmo.c:2649 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: ошибка в таблице Ñимволов: повторÑющийÑÑ Ñимвол `%s'\n" + +#: mmo.c:2889 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Ðеверное определение Ñимвола: `Main' уÑтановлена в %s, а не в начальный Ð°Ð´Ñ€ÐµÑ %s\n" + +#: mmo.c:2981 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: предупреждение: таблица Ñимволов Ñлишком Ð±Ð¾Ð»ÑŒÑˆÐ°Ñ Ð´Ð»Ñ mmo, больше чем 65535 32-битных Ñлов: %d. Будет выделена только `Main'.\n" + +#: mmo.c:3026 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°, у таблицы Ñимволов изменилÑÑ Ñ€Ð°Ð·Ð¼ÐµÑ€ Ñ %d Ñлов до %d\n" + +#: mmo.c:3078 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: внутреннÑÑ Ð¾ÑˆÐ¸Ð±ÐºÐ°, внутренний раздел региÑтров %s Ñодержит данные\n" + +#: mmo.c:3129 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s:нет инициализированных региÑтров; длина раздела равна 0\n" + +#: mmo.c:3135 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: Ñлишком много инициализированных региÑтров; длина раздела равна %ld\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: недопуÑтимый начальный Ð°Ð´Ñ€ÐµÑ Ð´Ð»Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð½Ñ‹Ñ… региÑтров длины %ld: 0x%lx%08lx\n" + +#: oasys.c:882 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: невозможно предÑтавить раздел `%s' в oasys" + +#: osf-core.c:140 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Ðеобработанный файл Ñдра OSF/1 раздела Ñ Ñ‚Ð¸Ð¿Ð¾Ð¼ %d\n" + +#: pe-mips.c:607 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: `ld -r' не поддерживаетÑÑ Ñ Ð¾Ð±ÑŠÐµÐºÑ‚Ð°Ð¼Ð¸ PE MIPS\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:719 +msgid "%B: unimplemented %s\n" +msgstr "%B: не реализовано %s\n" + +#: pe-mips.c:745 +msgid "%B: jump too far away\n" +msgstr "%B: точка перехода Ñлишком далеко\n" + +#: pe-mips.c:771 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: Ð½ÐµÐ²ÐµÑ€Ð½Ð°Ñ pair/reflo поÑле refhi\n" + +#: pei-x86_64.c:444 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "предупреждение: размер раздела .pdata (%ld) не кратен %d\n" + +#: pei-x86_64.c:448 peigen.c:1618 peigen.c:1801 pepigen.c:1618 pepigen.c:1801 +#: pex64igen.c:1618 pex64igen.c:1801 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Таблица функций (обработан раздел .pdata)\n" + +#: pei-x86_64.c:450 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "vma:\t\t\tÐач Ð°Ð´Ñ€ÐµÑ \t Кон адреÑ\t РаÑкр данные\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: Ðеобработанный тип импорта; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: ÐераÑпознанный тип импорта; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: ÐераÑпознанный именной тип импорта; %x" + +#: peicode.h:1162 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: ÐераÑпознанный машинный тип (0x%x) в архиве Import Library Format" + +#: peicode.h:1174 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: РаÑпознан, но не обработан машинный тип (0x%x) в архиве Import Library Format" + +#: peicode.h:1192 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: размер Ð¿Ð¾Ð»Ñ Ñ€Ð°Ð²ÐµÐ½ нулю в заголовке Import Library Format" + +#: peicode.h:1223 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: Ñтрока не заканчиваетÑÑ Ð½ÑƒÐ»Ñ‘Ð¼ в объектном файле ILF." + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"заголовок ppcboot:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Ðачальное Ñмещение = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Длина = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Поле флагов = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Ð˜Ð¼Ñ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Ðачало раздела[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Конец раздела[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Сектор раздела[%d] = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Длина раздела[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5471 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Ð’Ñпомогательный заголовок Exec\n" + +#: som.c:5776 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers не реализован" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d: Ðеожиданный Ñимвол `%s' в файле S-record\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: ÐÐµÐ²ÐµÑ€Ð½Ð°Ñ ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»ÑŒÐ½Ð°Ñ Ñумма в файле S-record\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Элемент Stabs имеет недопуÑтимый Ð¸Ð½Ð´ÐµÐºÑ Ñтроки." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "Ðеподдерживаемое перемещение .stab" + +#: vms-alpha.c:1287 +#, c-format +msgid "Unknown EGSD subtype %d" +msgstr "ÐеизвеÑтный подтип EGSD %d" + +#: vms-alpha.c:1318 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Переполнение Ñтека (%d) в _bfd_vms_push" + +#: vms-alpha.c:1331 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Выход за нижнюю границу Ñтека в _bfd_vms_pop" + +#. These names have not yet been added to this switch statement. +#: vms-alpha.c:1568 +#, c-format +msgid "unknown ETIR command %d" +msgstr "неизвеÑÑ‚Ð½Ð°Ñ ETIR команда %d" + +#: vms-alpha.c:1755 +#, c-format +msgid "bad section index in %s" +msgstr "неверный Ð¸Ð½Ð´ÐµÐºÑ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° в %s" + +#: vms-alpha.c:1768 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "неподдерживаемый STA cmd %s" + +#. Insert field. +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-alpha.c:1944 vms-alpha.c:1975 vms-alpha.c:2222 +#, c-format +msgid "%s: not supported" +msgstr "%s: не поддерживаетÑÑ" + +#: vms-alpha.c:1950 +#, c-format +msgid "%s: not implemented" +msgstr "%s: не реализовано" + +#: vms-alpha.c:2206 +#, c-format +msgid "invalid use of %s with contexts" +msgstr "неправильное иÑпользование %s Ñ ÐºÐ¾Ð½Ñ‚ÐµÐºÑтами" + +#: vms-alpha.c:2240 +#, c-format +msgid "reserved cmd %d" +msgstr "зарезервированный cmd %d" + +#: vms-alpha.c:2325 +msgid "Object module NOT error-free !\n" +msgstr "Объектный модуль ÐЕ error-free !\n" + +#: vms-alpha.c:2754 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Символ %s заменён на %s\n" + +#: vms-alpha.c:3757 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC без перемещений в разделе %s" + +#: vms-alpha.c:3810 vms-alpha.c:4041 +#, c-format +msgid "Size error in section %s" +msgstr "Ошибка размера в разделе %s" + +#: vms-alpha.c:3980 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Ðетипичное перемещение ALPHA_R_BSR" + +#: vms-alpha.c:4028 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Ðеобработанное перемещение %s" + +#: vms-alpha.c:4318 +#, c-format +msgid "unknown source command %d" +msgstr "неизвеÑÑ‚Ð½Ð°Ñ Ð¸ÑÑ…Ð¾Ð´Ð½Ð°Ñ ÐºÐ¾Ð¼Ð°Ð½Ð´Ð° %d" + +#: vms-alpha.c:4379 +msgid "DST__K_SET_LINUM_INCR not implemented" +msgstr "DST__K_SET_LINUM_INCR не реализован" + +#: vms-alpha.c:4385 +msgid "DST__K_SET_LINUM_INCR_W not implemented" +msgstr "DST__K_SET_LINUM_INCR_W не реализован" + +#: vms-alpha.c:4391 +msgid "DST__K_RESET_LINUM_INCR not implemented" +msgstr "DST__K_RESET_LINUM_INCR не реализован" + +#: vms-alpha.c:4397 +msgid "DST__K_BEG_STMT_MODE not implemented" +msgstr "DST__K_BEG_STMT_MODE не реализован" + +#: vms-alpha.c:4403 +msgid "DST__K_END_STMT_MODE not implemented" +msgstr "DST__K_END_STMT_MODE не реализован" + +#: vms-alpha.c:4430 +msgid "DST__K_SET_PC not implemented" +msgstr "DST__K_SET_PC не реализован" + +#: vms-alpha.c:4436 +msgid "DST__K_SET_PC_W not implemented" +msgstr "DST__K_SET_PC_W не реализован" + +#: vms-alpha.c:4442 +msgid "DST__K_SET_PC_L not implemented" +msgstr "DST__K_SET_PC_L не реализован" + +#: vms-alpha.c:4448 +msgid "DST__K_SET_STMTNUM not implemented" +msgstr "DST__K_SET_STMTNUM не реализован" + +#: vms-alpha.c:4491 +#, c-format +msgid "unknown line command %d" +msgstr "неизвеÑÑ‚Ð½Ð°Ñ Ñтрока команды %d" + +#: vms-alpha.c:4938 vms-alpha.c:4955 vms-alpha.c:4969 vms-alpha.c:4984 +#: vms-alpha.c:4996 vms-alpha.c:5007 vms-alpha.c:5019 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "ÐеизвеÑтное перемещение %s + %s" + +#: vms-alpha.c:5074 +#, c-format +msgid "Unknown reloc %s" +msgstr "ÐеизвеÑтное перемещение %s" + +#: vms-alpha.c:5087 +msgid "Invalid section index in ETIR" +msgstr "Ðеверный Ð¸Ð½Ð´ÐµÐºÑ Ñ€Ð°Ð·Ð´ÐµÐ»Ð° в ETIR" + +#: vms-alpha.c:5134 +#, c-format +msgid "Unknown symbol in command %s" +msgstr "ÐеизвеÑтный Ñимвол в команде %s" + +#: vms-alpha.c:5649 +#, c-format +msgid " EMH %u (len=%u): " +msgstr " EMH %u (len=%u): " + +#: vms-alpha.c:5658 +#, c-format +msgid "Module header\n" +msgstr "Заголовок модулÑ\n" + +#: vms-alpha.c:5659 +#, c-format +msgid " structure level: %u\n" +msgstr " уровень Ñтруктуры : %u\n" + +#: vms-alpha.c:5660 +#, c-format +msgid " max record size: %u\n" +msgstr " макÑ. размер запиÑи: %u\n" + +#: vms-alpha.c:5663 +#, c-format +msgid " module name : %.*s\n" +msgstr " Ð¸Ð¼Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñ : %.*s\n" + +#: vms-alpha.c:5665 +#, c-format +msgid " module version : %.*s\n" +msgstr " верÑÐ¸Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñ : %.*s\n" + +#: vms-alpha.c:5667 +#, c-format +msgid " compile date : %.17s\n" +msgstr " дата компилÑции : %.17s\n" + +#: vms-alpha.c:5672 +#, c-format +msgid "Language Processor Name\n" +msgstr "Ðазвание процеÑÑорного Ñзыка\n" + +#: vms-alpha.c:5673 +#, c-format +msgid " language name: %.*s\n" +msgstr " название Ñзыка : %.*s\n" + +#: vms-alpha.c:5680 +#, c-format +msgid "Source Files Header\n" +msgstr "Заголовок иÑходных файлов\n" + +#: vms-alpha.c:5681 +#, c-format +msgid " file: %.*s\n" +msgstr " файл: %.*s\n" + +#: vms-alpha.c:5688 +#, c-format +msgid "Title Text Header\n" +msgstr "Заголовок Ð½Ð°Ð·Ð²Ð°Ð½Ð¸Ñ Ñ‚ÐµÐºÑта\n" + +#: vms-alpha.c:5689 +#, c-format +msgid " title: %.*s\n" +msgstr " название : %.*s\n" + +#: vms-alpha.c:5696 +#, c-format +msgid "Copyright Header\n" +msgstr "Заголовок авторÑкого права\n" + +#: vms-alpha.c:5697 +#, c-format +msgid " copyright: %.*s\n" +msgstr " авторÑкое право: %.*s\n" + +#: vms-alpha.c:5703 +#, c-format +msgid "unhandled emh subtype %u\n" +msgstr "необработанный подтип emh %u\n" + +#: vms-alpha.c:5713 +#, c-format +msgid " EEOM (len=%u):\n" +msgstr " EEOM (len=%u):\n" + +#: vms-alpha.c:5714 +#, c-format +msgid " number of cond linkage pairs: %u\n" +msgstr " кол-во уÑловно компонуемых пар: %u\n" + +#: vms-alpha.c:5716 +#, c-format +msgid " completion code: %u\n" +msgstr " завершённый код: %u\n" + +#: vms-alpha.c:5720 +#, c-format +msgid " transfer addr flags: 0x%02x\n" +msgstr " адреÑа передачи flags: 0x%02x\n" + +#: vms-alpha.c:5721 +#, c-format +msgid " transfer addr psect: %u\n" +msgstr " Ð°Ð´Ñ€ÐµÑ Ð¿ÐµÑ€ÐµÐ´Ð°Ñ‡Ð¸ psect: %u\n" + +#: vms-alpha.c:5723 +#, c-format +msgid " transfer address : 0x%08x\n" +msgstr " Ð°Ð´Ñ€ÐµÑ Ð¿ÐµÑ€ÐµÐ´Ð°Ñ‡Ð¸ : 0x%08x\n" + +#: vms-alpha.c:5732 +msgid " WEAK" +msgstr " WEAK" + +#: vms-alpha.c:5734 +msgid " DEF" +msgstr " DEF" + +#: vms-alpha.c:5736 +msgid " UNI" +msgstr " UNI" + +#: vms-alpha.c:5738 vms-alpha.c:5759 +msgid " REL" +msgstr " REL" + +#: vms-alpha.c:5740 +msgid " COMM" +msgstr " COMM" + +#: vms-alpha.c:5742 +msgid " VECEP" +msgstr " VECEP" + +#: vms-alpha.c:5744 +msgid " NORM" +msgstr " NORM" + +#: vms-alpha.c:5746 +msgid " QVAL" +msgstr " QVAL" + +#: vms-alpha.c:5753 +msgid " PIC" +msgstr " PIC" + +#: vms-alpha.c:5755 +msgid " LIB" +msgstr " LIB" + +#: vms-alpha.c:5757 +msgid " OVR" +msgstr " OVR" + +#: vms-alpha.c:5761 +msgid " GBL" +msgstr " GBL" + +#: vms-alpha.c:5763 +msgid " SHR" +msgstr " SHR" + +#: vms-alpha.c:5765 +msgid " EXE" +msgstr " EXE" + +#: vms-alpha.c:5767 +msgid " RD" +msgstr " RD" + +#: vms-alpha.c:5769 +msgid " WRT" +msgstr " WRT" + +#: vms-alpha.c:5771 +msgid " VEC" +msgstr " VEC" + +#: vms-alpha.c:5773 +msgid " NOMOD" +msgstr " NOMOD" + +#: vms-alpha.c:5775 +msgid " COM" +msgstr " COM" + +#: vms-alpha.c:5777 +msgid " 64B" +msgstr " 64B" + +#: vms-alpha.c:5786 +#, c-format +msgid " EGSD (len=%u):\n" +msgstr " EGSD (len=%u):\n" + +#: vms-alpha.c:5798 +#, c-format +msgid " EGSD entry %2u (type: %u, len: %u): " +msgstr " запиÑÑŒ EGSD %2u (тип: %u, длина: %u): " + +#: vms-alpha.c:5810 +#, c-format +msgid "PSC - Program section definition\n" +msgstr "PSC - определение программного раздела\n" + +#: vms-alpha.c:5811 vms-alpha.c:5828 +#, c-format +msgid " alignment : 2**%u\n" +msgstr " выравнивание : 2**%u\n" + +#: vms-alpha.c:5812 vms-alpha.c:5829 +#, c-format +msgid " flags : 0x%04x" +msgstr " флаги : 0x%04x" + +#: vms-alpha.c:5816 +#, c-format +msgid " alloc (len): %u (0x%08x)\n" +msgstr " alloc (len): %u (0x%08x)\n" + +#: vms-alpha.c:5817 vms-alpha.c:5874 vms-alpha.c:5923 +#, c-format +msgid " name : %.*s\n" +msgstr " Ð¸Ð¼Ñ : %.*s\n" + +#: vms-alpha.c:5827 +#, c-format +msgid "SPSC - Shared Image Program section def\n" +msgstr "SPSC - определение программного раздела общего образа\n" + +#: vms-alpha.c:5833 +#, c-format +msgid " alloc (len) : %u (0x%08x)\n" +msgstr " alloc (len) : %u (0x%08x)\n" + +#: vms-alpha.c:5834 +#, c-format +msgid " image offset : 0x%08x\n" +msgstr " Ñмещение образа : 0x%08x\n" + +#: vms-alpha.c:5836 +#, c-format +msgid " symvec offset : 0x%08x\n" +msgstr " Ñмещение symvec: 0x%08x\n" + +#: vms-alpha.c:5838 +#, c-format +msgid " name : %.*s\n" +msgstr " Ð¸Ð¼Ñ : %.*s\n" + +#: vms-alpha.c:5851 +#, c-format +msgid "SYM - Global symbol definition\n" +msgstr "SYM - определение глобальных Ñимволов\n" + +#: vms-alpha.c:5852 vms-alpha.c:5912 vms-alpha.c:5933 vms-alpha.c:5952 +#, c-format +msgid " flags: 0x%04x" +msgstr " флаги: 0x%04x" + +#: vms-alpha.c:5855 +#, c-format +msgid " psect offset: 0x%08x\n" +msgstr " Ñмещение psect: 0x%08x\n" + +#: vms-alpha.c:5859 +#, c-format +msgid " code address: 0x%08x\n" +msgstr " Ð°Ð´Ñ€ÐµÑ ÐºÐ¾Ð´Ð°: 0x%08x\n" + +#: vms-alpha.c:5861 +#, c-format +msgid " psect index for entry point : %u\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ psect Ð´Ð»Ñ Ñ‚Ð¾Ñ‡ÐºÐ¸ входа: %u\n" + +#: vms-alpha.c:5864 vms-alpha.c:5940 vms-alpha.c:5959 +#, c-format +msgid " psect index : %u\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ psect: %u\n" + +#: vms-alpha.c:5866 vms-alpha.c:5942 vms-alpha.c:5961 +#, c-format +msgid " name : %.*s\n" +msgstr " Ð¸Ð¼Ñ : %.*s\n" + +#: vms-alpha.c:5873 +#, c-format +msgid "SYM - Global symbol reference\n" +msgstr "SYM - ÑÑылки глобальных Ñимволов\n" + +#: vms-alpha.c:5885 +#, c-format +msgid "IDC - Ident Consistency check\n" +msgstr "IDC - проверка идентификатора целоÑтноÑти\n" + +#: vms-alpha.c:5886 +#, c-format +msgid " flags : 0x%08x" +msgstr " флаги : 0x%08x" + +#: vms-alpha.c:5890 +#, c-format +msgid " id match : %x\n" +msgstr " id ÑоответÑÑ‚Ð²Ð¸Ñ : %x\n" + +#: vms-alpha.c:5892 +#, c-format +msgid " error severity: %x\n" +msgstr " ÑерьёзноÑÑ‚ÑŒ ошибки: %x\n" + +#: vms-alpha.c:5895 +#, c-format +msgid " entity name : %.*s\n" +msgstr " название категории: %.*s\n" + +#: vms-alpha.c:5897 +#, c-format +msgid " object name : %.*s\n" +msgstr " Ð¸Ð¼Ñ Ð¾Ð±ÑŠÐµÐºÑ‚Ð°: %.*s\n" + +#: vms-alpha.c:5900 +#, c-format +msgid " binary ident : 0x%08x\n" +msgstr " двоичный идентификатор: 0x%08x\n" + +#: vms-alpha.c:5903 +#, c-format +msgid " ascii ident : %.*s\n" +msgstr " ascii-идентификатор: %.*s\n" + +#: vms-alpha.c:5911 +#, c-format +msgid "SYMG - Universal symbol definition\n" +msgstr "SYMG - определение универÑальных Ñимволов\n" + +#: vms-alpha.c:5915 +#, c-format +msgid " symbol vector offset: 0x%08x\n" +msgstr " Ñмещение Ñимвольного вектора: 0x%08x\n" + +#: vms-alpha.c:5917 +#, c-format +msgid " entry point: 0x%08x\n" +msgstr " точка входа: 0x%08x\n" + +#: vms-alpha.c:5919 +#, c-format +msgid " proc descr : 0x%08x\n" +msgstr " proc descr : 0x%08x\n" + +#: vms-alpha.c:5921 +#, c-format +msgid " psect index: %u\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ psect: %u\n" + +#: vms-alpha.c:5932 +#, c-format +msgid "SYMV - Vectored symbol definition\n" +msgstr "SYMV - определение векторных Ñимволов\n" + +#: vms-alpha.c:5936 +#, c-format +msgid " vector : 0x%08x\n" +msgstr " вектор : 0x%08x\n" + +#: vms-alpha.c:5938 vms-alpha.c:5957 +#, c-format +msgid " psect offset: %u\n" +msgstr " Ñмещение psect: %u\n" + +#: vms-alpha.c:5951 +#, c-format +msgid "SYMM - Global symbol definition with version\n" +msgstr "SYMM - определение глобальных Ñимволов Ñ Ð²ÐµÑ€Ñией\n" + +#: vms-alpha.c:5955 +#, c-format +msgid " version mask: 0x%08x\n" +msgstr " маÑка верÑии: 0x%08x\n" + +#: vms-alpha.c:5966 +#, c-format +msgid "unhandled egsd entry type %u\n" +msgstr "необработанный egsd-Ñлемент типа %u\n" + +#: vms-alpha.c:6000 +#, c-format +msgid " linkage index: %u, replacement insn: 0x%08x\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸: %u, заменитель insn: 0x%08x\n" + +#: vms-alpha.c:6003 +#, c-format +msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" +msgstr " 1-й Ð¸Ð½Ð´ÐµÐºÑ psect: %u, 1-е Ñмещение: 0x%08x %08x\n" + +#: vms-alpha.c:6007 +#, c-format +msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" +msgstr " 2-й Ð¸Ð½Ð´ÐµÐºÑ psect: %u, 2-е Ñмещение: 0x%08x %08x\n" + +#: vms-alpha.c:6012 +#, c-format +msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" +msgstr " 3-й Ð¸Ð½Ð´ÐµÐºÑ psect: %u, 3-е Ñмещение: 0x%08x %08x\n" + +#: vms-alpha.c:6017 +#, c-format +msgid " global name: %.*s\n" +msgstr " глобальное имÑ: %.*s\n" + +#: vms-alpha.c:6027 +#, c-format +msgid " %s (len=%u+%u):\n" +msgstr " %s (len=%u+%u):\n" + +#: vms-alpha.c:6042 +#, c-format +msgid " (type: %3u, size: 4+%3u): " +msgstr " (тип: %3u, размер: 4+%3u): " + +#: vms-alpha.c:6046 +#, c-format +msgid "STA_GBL (stack global) %.*s\n" +msgstr "STA_GBL (глобальный Ñтек) %.*s\n" + +#: vms-alpha.c:6050 +#, c-format +msgid "STA_LW (stack longword) 0x%08x\n" +msgstr "STA_LW (Ñтек длинных Ñлов) 0x%08x\n" + +#: vms-alpha.c:6054 +#, c-format +msgid "STA_QW (stack quadword) 0x%08x %08x\n" +msgstr "STA_QW (Ñтек четверных Ñлов) 0x%08x %08x\n" + +#: vms-alpha.c:6059 +#, c-format +msgid "STA_PQ (stack psect base + offset)\n" +msgstr "STA_PQ (Ñтек psect база + Ñмещение)\n" + +#: vms-alpha.c:6060 +#, c-format +msgid " psect: %u, offset: 0x%08x %08x\n" +msgstr " psect: %u, Ñмещение: 0x%08x %08x\n" + +#: vms-alpha.c:6066 +#, c-format +msgid "STA_LI (stack literal)\n" +msgstr "STA_LI (Ñтек литерала)\n" + +#: vms-alpha.c:6069 +#, c-format +msgid "STA_MOD (stack module)\n" +msgstr "STA_MOD (Ñтек модулей)\n" + +#: vms-alpha.c:6072 +#, c-format +msgid "STA_CKARG (compare procedure argument)\n" +msgstr "STA_CKARG (аргумент процедуры ÑравнениÑ)\n" + +#: vms-alpha.c:6076 +#, c-format +msgid "STO_B (store byte)\n" +msgstr "STO_B (хранимый байт)\n" + +#: vms-alpha.c:6079 +#, c-format +msgid "STO_W (store word)\n" +msgstr "STO_W (хранимое Ñлово)\n" + +#: vms-alpha.c:6082 +#, c-format +msgid "STO_LW (store longword)\n" +msgstr "STO_LW (хранимое длинное Ñлово)\n" + +#: vms-alpha.c:6085 +#, c-format +msgid "STO_QW (store quadword)\n" +msgstr "STO_QW (хранимое учетверённое Ñлово)\n" + +#: vms-alpha.c:6091 +#, c-format +msgid "STO_IMMR (store immediate repeat) %u bytes\n" +msgstr "STO_IMMR (хранимый непоÑредÑтвенный повтор) %u байт\n" + +#: vms-alpha.c:6098 +#, c-format +msgid "STO_GBL (store global) %.*s\n" +msgstr "STO_GBL (Ñ…Ñ€Ð°Ð½Ð¸Ð¼Ð°Ñ Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð°Ñ) %.*s\n" + +#: vms-alpha.c:6102 +#, c-format +msgid "STO_CA (store code address) %.*s\n" +msgstr "STO_CA (хранимый Ð°Ð´Ñ€ÐµÑ ÐºÐ¾Ð´Ð°) %.*s\n" + +#: vms-alpha.c:6106 +#, c-format +msgid "STO_RB (store relative branch)\n" +msgstr "STO_RB (хранимый отноÑительный переход)\n" + +#: vms-alpha.c:6109 +#, c-format +msgid "STO_AB (store absolute branch)\n" +msgstr "STO_AB (хранимый абÑолютный переход)\n" + +#: vms-alpha.c:6112 +#, c-format +msgid "STO_OFF (store offset to psect)\n" +msgstr "STO_OFF (хранимое Ñмещение на psect)\n" + +#: vms-alpha.c:6118 +#, c-format +msgid "STO_IMM (store immediate) %u bytes\n" +msgstr "STO_IMM (Ñ…Ñ€Ð°Ð½Ð¸Ð¼Ð°Ñ Ð½ÐµÐ¿Ð¾ÑредÑтвенно) %u байт\n" + +#: vms-alpha.c:6125 +#, c-format +msgid "STO_GBL_LW (store global longword) %.*s\n" +msgstr "STO_GBL_LW (хранимое глобальное длинное Ñлово) %.*s\n" + +#: vms-alpha.c:6129 +#, c-format +msgid "STO_OFF (store LP with procedure signature)\n" +msgstr "STO_OFF (хранимый LP Ñ Ñигнатурой процедуры)\n" + +#: vms-alpha.c:6132 +#, c-format +msgid "STO_BR_GBL (store branch global) *todo*\n" +msgstr "STO_BR_GBL (хранимый глобальный переход) *todo*\n" + +#: vms-alpha.c:6135 +#, c-format +msgid "STO_BR_PS (store branch psect + offset) *todo*\n" +msgstr "STO_BR_PS (хранимый переход psect + Ñмещение) *todo*\n" + +#: vms-alpha.c:6139 +#, c-format +msgid "OPR_NOP (no-operation)\n" +msgstr "OPR_NOP (нет операции)\n" + +#: vms-alpha.c:6142 +#, c-format +msgid "OPR_ADD (add)\n" +msgstr "OPR_ADD (Ñложение)\n" + +#: vms-alpha.c:6145 +#, c-format +msgid "OPR_SUB (substract)\n" +msgstr "OPR_SUB (вычитание)\n" + +#: vms-alpha.c:6148 +#, c-format +msgid "OPR_MUL (multiply)\n" +msgstr "OPR_MUL (умножение)\n" + +#: vms-alpha.c:6151 +#, c-format +msgid "OPR_DIV (divide)\n" +msgstr "OPR_DIV (деление)\n" + +#: vms-alpha.c:6154 +#, c-format +msgid "OPR_AND (logical and)\n" +msgstr "OPR_AND (логичеÑкое и)\n" + +#: vms-alpha.c:6157 +#, c-format +msgid "OPR_IOR (logical inclusive or)\n" +msgstr "OPR_IOR (логичеÑкое включающее или)\n" + +#: vms-alpha.c:6160 +#, c-format +msgid "OPR_EOR (logical exclusive or)\n" +msgstr "OPR_EOR (логичеÑкое не включающее или)\n" + +#: vms-alpha.c:6163 +#, c-format +msgid "OPR_NEG (negate)\n" +msgstr "OPR_NEG (инверÑиÑ)\n" + +#: vms-alpha.c:6166 +#, c-format +msgid "OPR_COM (complement)\n" +msgstr "OPR_COM (дополнение)\n" + +#: vms-alpha.c:6169 +#, c-format +msgid "OPR_INSV (insert field)\n" +msgstr "OPR_INSV (поле вÑтавки)\n" + +#: vms-alpha.c:6172 +#, c-format +msgid "OPR_ASH (arithmetic shift)\n" +msgstr "OPR_ASH (арифметичеÑкий Ñдвиг)\n" + +#: vms-alpha.c:6175 +#, c-format +msgid "OPR_USH (unsigned shift)\n" +msgstr "OPR_USH (беззнаковый Ñдвиг)\n" + +#: vms-alpha.c:6178 +#, c-format +msgid "OPR_ROT (rotate)\n" +msgstr "OPR_ROT (цикличеÑкий Ñдвиг)\n" + +#: vms-alpha.c:6181 +#, c-format +msgid "OPR_SEL (select)\n" +msgstr "OPR_SEL (выбор)\n" + +#: vms-alpha.c:6184 +#, c-format +msgid "OPR_REDEF (redefine symbol to curr location)\n" +msgstr "OPR_REDEF (переопределение Ñимвола в текущей позиции)\n" + +#: vms-alpha.c:6187 +#, c-format +msgid "OPR_REDEF (define a literal)\n" +msgstr "OPR_REDEF (определение литерала)\n" + +#: vms-alpha.c:6191 +#, c-format +msgid "STC_LP (store cond linkage pair)\n" +msgstr "STC_LP (Ñ…Ñ€Ð°Ð½Ð¸Ð¼Ð°Ñ ÑƒÑловно ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÑƒÐµÐ¼Ð°Ñ Ð¿Ð°Ñ€Ð°)\n" + +#: vms-alpha.c:6195 +#, c-format +msgid "STC_LP_PSB (store cond linkage pair + signature)\n" +msgstr "STC_LP_PSB (Ñ…Ñ€Ð°Ð½Ð¸Ð¼Ð°Ñ ÑƒÑловно ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÑƒÐµÐ¼Ð°Ñ Ð¿Ð°Ñ€Ð° + Ñигнатура)\n" + +#: vms-alpha.c:6196 +#, c-format +msgid " linkage index: %u, procedure: %.*s\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸: %u, процедура: %.*s\n" + +#: vms-alpha.c:6199 +#, c-format +msgid " signature: %.*s\n" +msgstr " Ñигнатура: %.*s\n" + +#: vms-alpha.c:6202 +#, c-format +msgid "STC_GBL (store cond global)\n" +msgstr "STC_GBL (Ñ…Ñ€Ð°Ð½Ð¸Ð¼Ð°Ñ Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð¾Ðµ уÑловие)\n" + +#: vms-alpha.c:6203 +#, c-format +msgid " linkage index: %u, global: %.*s\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸: %u, глобальный: %.*s\n" + +#: vms-alpha.c:6207 +#, c-format +msgid "STC_GCA (store cond code address)\n" +msgstr "STC_GCA (хранимый Ð°Ð´Ñ€ÐµÑ ÑƒÑловного кода)\n" + +#: vms-alpha.c:6208 +#, c-format +msgid " linkage index: %u, procedure name: %.*s\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸: %u, Ð¸Ð¼Ñ Ð¿Ñ€Ð¾Ñ†ÐµÐ´ÑƒÑ€Ñ‹: %.*s\n" + +#: vms-alpha.c:6212 +#, c-format +msgid "STC_PS (store cond psect + offset)\n" +msgstr "STC_PS (хранимое уÑловие psect + Ñмещение)\n" + +#: vms-alpha.c:6214 +#, c-format +msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" +msgstr " Ð¸Ð½Ð´ÐµÐºÑ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸: %u, psect: %u, Ñмещение: 0x%08x %08x\n" + +#: vms-alpha.c:6221 +#, c-format +msgid "STC_NOP_GBL (store cond NOP at global addr)\n" +msgstr "STC_NOP_GBL (хранимое уÑловие NOP по глобальному адреÑу)\n" + +#: vms-alpha.c:6225 +#, c-format +msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" +msgstr "STC_NOP_PS (хранимое уÑловие NOP по psect + Ñмещение)\n" + +#: vms-alpha.c:6229 +#, c-format +msgid "STC_BSR_GBL (store cond BSR at global addr)\n" +msgstr "STC_BSR_GBL (хранимое уÑловие BSR по глобальному адреÑу)\n" + +#: vms-alpha.c:6233 +#, c-format +msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" +msgstr "STC_BSR_PS (хранимое уÑловие BSR по psect + Ñмещение)\n" + +#: vms-alpha.c:6237 +#, c-format +msgid "STC_LDA_GBL (store cond LDA at global addr)\n" +msgstr "STC_LDA_GBL (хранимое уÑловие LDA по глобальному адреÑу)\n" + +#: vms-alpha.c:6241 +#, c-format +msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" +msgstr "STC_LDA_PS (хранимое уÑловие LDA по psect + Ñмещение)\n" + +#: vms-alpha.c:6245 +#, c-format +msgid "STC_BOH_GBL (store cond BOH at global addr)\n" +msgstr "STC_BOH_GBL (хранимое уÑловие BOH по глобальному адреÑу)\n" + +#: vms-alpha.c:6249 +#, c-format +msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" +msgstr "STC_BOH_PS (хранимое уÑловие BOH по psect + Ñмещение)\n" + +#: vms-alpha.c:6254 +#, c-format +msgid "STC_NBH_GBL (store cond or hint at global addr)\n" +msgstr "STC_NBH_GBL (хранимое уÑловие или указание по глобальному адреÑу)\n" + +#: vms-alpha.c:6258 +#, c-format +msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" +msgstr "STC_NBH_PS (хранимое уÑловие или указание по psect + Ñмещение)\n" + +#: vms-alpha.c:6262 +#, c-format +msgid "CTL_SETRB (set relocation base)\n" +msgstr "CTL_SETRB (уÑтановка базы перемещениÑ)\n" + +#: vms-alpha.c:6268 +#, c-format +msgid "CTL_AUGRB (augment relocation base) %u\n" +msgstr "CTL_AUGRB (дополнение базы перемещениÑ) %u\n" + +#: vms-alpha.c:6272 +#, c-format +msgid "CTL_DFLOC (define location)\n" +msgstr "CTL_DFLOC (определение положениÑ)\n" + +#: vms-alpha.c:6275 +#, c-format +msgid "CTL_STLOC (set location)\n" +msgstr "CTL_STLOC (задание положениÑ)\n" + +#: vms-alpha.c:6278 +#, c-format +msgid "CTL_STKDL (stack defined location)\n" +msgstr "CTL_STKDL (положение определÑемое Ñтеком)\n" + +#: vms-alpha.c:6281 vms-alpha.c:6695 +#, c-format +msgid "*unhandled*\n" +msgstr "*не обработано*\n" + +#: vms-alpha.c:6311 vms-alpha.c:6350 +#, c-format +msgid "cannot read GST record length\n" +msgstr "не удалоÑÑŒ прочитать длину запиÑи GST\n" + +#. Ill-formed. +#: vms-alpha.c:6332 +#, c-format +msgid "cannot find EMH in first GST record\n" +msgstr "не удалоÑÑŒ найти EMH в первой запиÑи GST\n" + +#: vms-alpha.c:6358 +#, c-format +msgid "cannot read GST record header\n" +msgstr "не удалоÑÑŒ прочитать заголовок запиÑи GST\n" + +#: vms-alpha.c:6371 +#, c-format +msgid " corrupted GST\n" +msgstr " повреждённый GST\n" + +#: vms-alpha.c:6379 +#, c-format +msgid "cannot read GST record\n" +msgstr "не удалоÑÑŒ прочитать запиÑÑŒ GST\n" + +#: vms-alpha.c:6408 +#, c-format +msgid " unhandled EOBJ record type %u\n" +msgstr " необработанный тип запиÑи EOBJ %u\n" + +#: vms-alpha.c:6431 +#, c-format +msgid " bitcount: %u, base addr: 0x%08x\n" +msgstr " Ñчётчик бит: %u, базовый адреÑ: 0x%08x\n" + +#: vms-alpha.c:6444 +#, c-format +msgid " bitmap: 0x%08x (count: %u):\n" +msgstr " bitmap: 0x%08x (Ñчётчик: %u):\n" + +#: vms-alpha.c:6451 +#, c-format +msgid " %08x" +msgstr " %08x" + +#: vms-alpha.c:6476 +#, c-format +msgid " image %u (%u entries)\n" +msgstr " образ %u (%u Ñлементов)\n" + +#: vms-alpha.c:6481 +#, c-format +msgid " offset: 0x%08x, val: 0x%08x\n" +msgstr " Ñмещение: 0x%08x, значение: 0x%08x\n" + +#: vms-alpha.c:6502 +#, c-format +msgid " image %u (%u entries), offsets:\n" +msgstr " образ %u (%u Ñлементов), ÑмещениÑ:\n" + +#: vms-alpha.c:6509 +#, c-format +msgid " 0x%08x" +msgstr " 0x%08x" + +#. 64 bits. +#: vms-alpha.c:6631 +#, c-format +msgid "64 bits *unhandled*\n" +msgstr "64 бита *не обработано*\n" + +#: vms-alpha.c:6635 +#, c-format +msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" +msgstr "клаÑÑ: %u, dtype: %u, длина: %u, указатель: 0x%08x\n" + +#: vms-alpha.c:6646 +#, c-format +msgid "non-contiguous array of %s\n" +msgstr "неÑвÑзный маÑÑив %s\n" + +#: vms-alpha.c:6650 +#, c-format +msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" +msgstr "dimct: %u, aflags: 0x%02x, цифр: %u, шкала: %u\n" + +#: vms-alpha.c:6654 +#, c-format +msgid "arsize: %u, a0: 0x%08x\n" +msgstr "arsize: %u, a0: 0x%08x\n" + +#: vms-alpha.c:6658 +#, c-format +msgid "Strides:\n" +msgstr "Шаги:\n" + +#: vms-alpha.c:6663 +#, c-format +msgid "[%u]: %u\n" +msgstr "[%u]: %u\n" + +#: vms-alpha.c:6668 +#, c-format +msgid "Bounds:\n" +msgstr "Границы:\n" + +#: vms-alpha.c:6673 +#, c-format +msgid "[%u]: Lower: %u, upper: %u\n" +msgstr "[%u]: нижнÑÑ: %u, верхнÑÑ: %u\n" + +#: vms-alpha.c:6685 +#, c-format +msgid "unaligned bit-string of %s\n" +msgstr "Ð½ÐµÐ²Ñ‹Ñ€Ð¾Ð²Ð½ÐµÐ½Ð½Ð°Ñ Ñтрока бит %s\n" + +#: vms-alpha.c:6689 +#, c-format +msgid "base: %u, pos: %u\n" +msgstr "база: %u, позициÑ: %u\n" + +#: vms-alpha.c:6709 +#, c-format +msgid "vflags: 0x%02x, value: 0x%08x " +msgstr "vflags: 0x%02x, значение: 0x%08x " + +#: vms-alpha.c:6715 +#, c-format +msgid "(no value)\n" +msgstr "(нет значениÑ)\n" + +#: vms-alpha.c:6718 +#, c-format +msgid "(not active)\n" +msgstr "(не активно)\n" + +#: vms-alpha.c:6721 +#, c-format +msgid "(not allocated)\n" +msgstr "(не выделено)\n" + +#: vms-alpha.c:6724 +#, c-format +msgid "(descriptor)\n" +msgstr "(деÑкриптор)\n" + +#: vms-alpha.c:6728 +#, c-format +msgid "(trailing value)\n" +msgstr "(конечное значение)\n" + +#: vms-alpha.c:6731 +#, c-format +msgid "(value spec follows)\n" +msgstr "(далее значение Ñпецификации)\n" + +#: vms-alpha.c:6734 +#, c-format +msgid "(at bit offset %u)\n" +msgstr "(по битовому Ñмещению %u)\n" + +#: vms-alpha.c:6737 +#, c-format +msgid "(reg: %u, disp: %u, indir: %u, kind: " +msgstr "(reg: %u, disp: %u, indir: %u, kind: " + +#: vms-alpha.c:6744 +msgid "literal" +msgstr "литерал" + +#: vms-alpha.c:6747 +msgid "address" +msgstr "адреÑ" + +#: vms-alpha.c:6750 +msgid "desc" +msgstr "деÑк" + +#: vms-alpha.c:6753 +msgid "reg" +msgstr "рег" + +#: vms-alpha.c:6828 +#, c-format +msgid "Debug symbol table:\n" +msgstr "Таблица Ñимволов отладки:\n" + +#: vms-alpha.c:6839 +#, c-format +msgid "cannot read DST header\n" +msgstr "не удалоÑÑŒ прочитать заголовок DST\n" + +#: vms-alpha.c:6844 +#, c-format +msgid " type: %3u, len: %3u (at 0x%08x): " +msgstr " тип: %3u, длина: %3u (по 0x%08x): " + +#: vms-alpha.c:6858 +#, c-format +msgid "cannot read DST symbol\n" +msgstr "не удалоÑÑŒ прочитать Ñимвол DST\n" + +#: vms-alpha.c:6901 +#, c-format +msgid "standard data: %s\n" +msgstr "Ñтандартные данные: %s\n" + +#: vms-alpha.c:6904 vms-alpha.c:6988 +#, c-format +msgid " name: %.*s\n" +msgstr " имÑ: %.*s\n" + +#: vms-alpha.c:6911 +#, c-format +msgid "modbeg\n" +msgstr "modbeg\n" + +#: vms-alpha.c:6912 +#, c-format +msgid " flags: %d, language: %u, major: %u, minor: %u\n" +msgstr " флаги: %d, Ñзык: %u, Ñтарший: %u, младший: %u\n" + +#: vms-alpha.c:6918 vms-alpha.c:7184 +#, c-format +msgid " module name: %.*s\n" +msgstr " Ð¸Ð¼Ñ Ð¼Ð¾Ð´ÑƒÐ»Ñ: %.*s\n" + +#: vms-alpha.c:6921 +#, c-format +msgid " compiler : %.*s\n" +msgstr " компилÑтор : %.*s\n" + +#: vms-alpha.c:6926 +#, c-format +msgid "modend\n" +msgstr "modend\n" + +#: vms-alpha.c:6933 +msgid "rtnbeg\n" +msgstr "rtnbeg\n" + +#: vms-alpha.c:6934 +#, c-format +msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" +msgstr " флаги: %u, адреÑ: 0x%08x, pd-адреÑ: 0x%08x\n" + +#: vms-alpha.c:6939 +#, c-format +msgid " routine name: %.*s\n" +msgstr " Ð¸Ð¼Ñ Ð¿Ñ€Ð¾Ñ†ÐµÐ´ÑƒÑ€Ñ‹: %.*s\n" + +#: vms-alpha.c:6947 +#, c-format +msgid "rtnend: size 0x%08x\n" +msgstr "rtnend: размер 0x%08x\n" + +#: vms-alpha.c:6955 +#, c-format +msgid "prolog: bkpt address 0x%08x\n" +msgstr "пролог: Ð°Ð´Ñ€ÐµÑ bkpt 0x%08x\n" + +#: vms-alpha.c:6963 +#, c-format +msgid "epilog: flags: %u, count: %u\n" +msgstr "Ñпилог: флаги: %u, Ñчётчик: %u\n" + +#: vms-alpha.c:6972 +#, c-format +msgid "blkbeg: address: 0x%08x, name: %.*s\n" +msgstr "blkbeg: адреÑ: 0x%08x, имÑ: %.*s\n" + +#: vms-alpha.c:6981 +#, c-format +msgid "blkend: size: 0x%08x\n" +msgstr "blkend: размер: 0x%08x\n" + +#: vms-alpha.c:6987 +#, c-format +msgid "typspec (len: %u)\n" +msgstr "typspec (длина: %u)\n" + +#: vms-alpha.c:6994 +#, c-format +msgid "septyp, name: %.*s\n" +msgstr "septyp, имÑ: %.*s\n" + +#: vms-alpha.c:7003 +#, c-format +msgid "recbeg: name: %.*s\n" +msgstr "recbeg: имÑ: %.*s\n" + +#: vms-alpha.c:7010 +#, c-format +msgid "recend\n" +msgstr "recend\n" + +#: vms-alpha.c:7013 +#, c-format +msgid "enumbeg, len: %u, name: %.*s\n" +msgstr "enumbeg, длина: %u, имÑ: %.*s\n" + +#: vms-alpha.c:7017 +#, c-format +msgid "enumelt, name: %.*s\n" +msgstr "enumelt, имÑ: %.*s\n" + +#: vms-alpha.c:7021 +#, c-format +msgid "enumend\n" +msgstr "enumend\n" + +#: vms-alpha.c:7038 +#, c-format +msgid "discontiguous range (nbr: %u)\n" +msgstr "неÑмежный диапазон (nbr: %u)\n" + +#: vms-alpha.c:7040 +#, c-format +msgid " address: 0x%08x, size: %u\n" +msgstr " адреÑ: 0x%08x, размер: %u\n" + +#: vms-alpha.c:7050 +#, c-format +msgid "line num (len: %u)\n" +msgstr "номер Ñтроки (длина: %u)\n" + +#: vms-alpha.c:7067 +#, c-format +msgid "delta_pc_w %u\n" +msgstr "delta_pc_w %u\n" + +#: vms-alpha.c:7074 +#, c-format +msgid "incr_linum(b): +%u\n" +msgstr "incr_linum(b): +%u\n" + +#: vms-alpha.c:7080 +#, c-format +msgid "incr_linum_w: +%u\n" +msgstr "incr_linum_w: +%u\n" + +#: vms-alpha.c:7086 +#, c-format +msgid "incr_linum_l: +%u\n" +msgstr "incr_linum_l: +%u\n" + +#: vms-alpha.c:7092 +#, c-format +msgid "set_line_num(w) %u\n" +msgstr "set_line_num(w) %u\n" + +#: vms-alpha.c:7097 +#, c-format +msgid "set_line_num_b %u\n" +msgstr "set_line_num_b %u\n" + +#: vms-alpha.c:7102 +#, c-format +msgid "set_line_num_l %u\n" +msgstr "set_line_num_l %u\n" + +#: vms-alpha.c:7107 +#, c-format +msgid "set_abs_pc: 0x%08x\n" +msgstr "set_abs_pc: 0x%08x\n" + +#: vms-alpha.c:7111 +#, c-format +msgid "delta_pc_l: +0x%08x\n" +msgstr "delta_pc_l: +0x%08x\n" + +#: vms-alpha.c:7116 +#, c-format +msgid "term(b): 0x%02x" +msgstr "term(b): 0x%02x" + +#: vms-alpha.c:7118 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7123 +#, c-format +msgid "term_w: 0x%04x" +msgstr "term_w: 0x%04x" + +#: vms-alpha.c:7125 +#, c-format +msgid " pc: 0x%08x\n" +msgstr " pc: 0x%08x\n" + +#: vms-alpha.c:7131 +#, c-format +msgid "delta pc +%-4d" +msgstr "delta pc +%-4d" + +#: vms-alpha.c:7134 +#, c-format +msgid " pc: 0x%08x line: %5u\n" +msgstr " pc: 0x%08x Ñтрока: %5u\n" + +#: vms-alpha.c:7139 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *необработаннаÑ* команда %u\n" + +#: vms-alpha.c:7154 +#, c-format +msgid "source (len: %u)\n" +msgstr "иÑточник (длина: %u)\n" + +#: vms-alpha.c:7168 +#, c-format +msgid " declfile: len: %u, flags: %u, fileid: %u\n" +msgstr " declfile: длина: %u, флаги: %u, fileid: %u\n" + +#: vms-alpha.c:7172 +#, c-format +msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" +msgstr " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" + +#: vms-alpha.c:7181 +#, c-format +msgid " filename : %.*s\n" +msgstr " Ð¸Ð¼Ñ Ñ„Ð°Ð¹Ð»Ð° : %.*s\n" + +#: vms-alpha.c:7190 +#, c-format +msgid " setfile %u\n" +msgstr " setfile %u\n" + +#: vms-alpha.c:7195 vms-alpha.c:7200 +#, c-format +msgid " setrec %u\n" +msgstr " setrec %u\n" + +#: vms-alpha.c:7205 vms-alpha.c:7210 +#, c-format +msgid " setlnum %u\n" +msgstr " setlnum %u\n" + +#: vms-alpha.c:7215 vms-alpha.c:7220 +#, c-format +msgid " deflines %u\n" +msgstr " deflines %u\n" + +#: vms-alpha.c:7224 +#, c-format +msgid " formfeed\n" +msgstr " formfeed\n" + +#: vms-alpha.c:7228 +#, c-format +msgid " *unhandled* cmd %u\n" +msgstr " *необработаннаÑ* команда %u\n" + +#: vms-alpha.c:7240 +#, c-format +msgid "*unhandled* dst type %u\n" +msgstr "*необработанный* тип Ð½Ð°Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ %u\n" + +#: vms-alpha.c:7272 +#, c-format +msgid "cannot read EIHD\n" +msgstr "не удалоÑÑŒ прочитать EIHD\n" + +#: vms-alpha.c:7275 +#, c-format +msgid "EIHD: (size: %u, nbr blocks: %u)\n" +msgstr "EIHD: (размер: %u, nbr блоков: %u)\n" + +#: vms-alpha.c:7278 +#, c-format +msgid " majorid: %u, minorid: %u\n" +msgstr " majorid: %u, minorid: %u\n" + +#: vms-alpha.c:7286 +msgid "executable" +msgstr "иÑполнÑемый" + +#: vms-alpha.c:7289 +msgid "linkable image" +msgstr "компонуемый образ" + +#: vms-alpha.c:7295 +#, c-format +msgid " image type: %u (%s)" +msgstr " тип образа: %u (%s)" + +#: vms-alpha.c:7301 +msgid "native" +msgstr "родной" + +#: vms-alpha.c:7304 +msgid "CLI" +msgstr "CLI" + +#: vms-alpha.c:7310 +#, c-format +msgid ", subtype: %u (%s)\n" +msgstr ", подтип: %u (%s)\n" + +#: vms-alpha.c:7316 +#, c-format +msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" +msgstr " ÑмещениÑ: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" + +#: vms-alpha.c:7320 +#, c-format +msgid " fixup info rva: " +msgstr " fixup info rva: " + +#: vms-alpha.c:7322 +#, c-format +msgid ", symbol vector rva: " +msgstr ", Ñимвольный вектор rva: " + +#: vms-alpha.c:7325 +#, c-format +msgid "" +"\n" +" version array off: %u\n" +msgstr "" +"\n" +" Ñмещение маÑÑива верÑий: %u\n" + +#: vms-alpha.c:7329 +#, c-format +msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" +msgstr " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" + +#: vms-alpha.c:7335 +#, c-format +msgid " linker flags: %08x:" +msgstr " флаги компоновщика: %08x:" + +#: vms-alpha.c:7365 +#, c-format +msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" +msgstr " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" + +#: vms-alpha.c:7371 +#, c-format +msgid " BPAGE: %u" +msgstr " BPAGE: %u" + +#: vms-alpha.c:7377 +#, c-format +msgid ", ext fixup offset: %u, no_opt psect off: %u" +msgstr ", ext fixup offset: %u, no_opt psect off: %u" + +#: vms-alpha.c:7380 +#, c-format +msgid ", alias: %u\n" +msgstr ", пÑевдоним: %u\n" + +#: vms-alpha.c:7388 +#, c-format +msgid "system version array information:\n" +msgstr "маÑÑив информации верÑии ÑиÑтемы:\n" + +#: vms-alpha.c:7392 +#, c-format +msgid "cannot read EIHVN header\n" +msgstr "не удалоÑÑŒ прочитать заголовок EIHVN\n" + +#: vms-alpha.c:7402 +#, c-format +msgid "cannot read EIHVN version\n" +msgstr "не удалоÑÑŒ прочитать верÑию EIHVN\n" + +#: vms-alpha.c:7405 +#, c-format +msgid " %02u " +msgstr " %02u " + +#: vms-alpha.c:7409 +msgid "BASE_IMAGE " +msgstr "BASE_IMAGE " + +#: vms-alpha.c:7412 +msgid "MEMORY_MANAGEMENT" +msgstr "MEMORY_MANAGEMENT" + +#: vms-alpha.c:7415 +msgid "IO " +msgstr "IO " + +#: vms-alpha.c:7418 +msgid "FILES_VOLUMES " +msgstr "FILES_VOLUMES " + +#: vms-alpha.c:7421 +msgid "PROCESS_SCHED " +msgstr "PROCESS_SCHED " + +#: vms-alpha.c:7424 +msgid "SYSGEN " +msgstr "SYSGEN " + +#: vms-alpha.c:7427 +msgid "CLUSTERS_LOCKMGR " +msgstr "CLUSTERS_LOCKMGR " + +#: vms-alpha.c:7430 +msgid "LOGICAL_NAMES " +msgstr "LOGICAL_NAMES " + +#: vms-alpha.c:7433 +msgid "SECURITY " +msgstr "SECURITY " + +#: vms-alpha.c:7436 +msgid "IMAGE_ACTIVATOR " +msgstr "IMAGE_ACTIVATOR " + +#: vms-alpha.c:7439 +msgid "NETWORKS " +msgstr "NETWORKS " + +#: vms-alpha.c:7442 +msgid "COUNTERS " +msgstr "COUNTERS " + +#: vms-alpha.c:7445 +msgid "STABLE " +msgstr "STABLE " + +#: vms-alpha.c:7448 +msgid "MISC " +msgstr "MISC " + +#: vms-alpha.c:7451 +msgid "CPU " +msgstr "CPU " + +#: vms-alpha.c:7454 +msgid "VOLATILE " +msgstr "VOLATILE " + +#: vms-alpha.c:7457 +msgid "SHELL " +msgstr "SHELL " + +#: vms-alpha.c:7460 +msgid "POSIX " +msgstr "POSIX " + +#: vms-alpha.c:7463 +msgid "MULTI_PROCESSING " +msgstr "MULTI_PROCESSING " + +#: vms-alpha.c:7466 +msgid "GALAXY " +msgstr "GALAXY " + +#: vms-alpha.c:7469 +msgid "*unknown* " +msgstr "*неизвеÑтно* " + +#: vms-alpha.c:7472 +#, c-format +msgid ": %u.%u\n" +msgstr ": %u.%u\n" + +#: vms-alpha.c:7485 vms-alpha.c:7744 +#, c-format +msgid "cannot read EIHA\n" +msgstr "не удалоÑÑŒ прочитать EIHA\n" + +#: vms-alpha.c:7488 +#, c-format +msgid "Image activation: (size=%u)\n" +msgstr "ÐÐºÑ‚Ð¸Ð²Ð°Ñ†Ð¸Ñ Ð¾Ð±Ñ€Ð°Ð·Ð°: (размер=%u)\n" + +#: vms-alpha.c:7490 +#, c-format +msgid " First address : 0x%08x 0x%08x\n" +msgstr " Первый адреÑ: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7493 +#, c-format +msgid " Second address: 0x%08x 0x%08x\n" +msgstr " Второй адреÑ: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7496 +#, c-format +msgid " Third address : 0x%08x 0x%08x\n" +msgstr " Третий адреÑ: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7499 +#, c-format +msgid " Fourth address: 0x%08x 0x%08x\n" +msgstr " Четвёртый адреÑ: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7502 +#, c-format +msgid " Shared image : 0x%08x 0x%08x\n" +msgstr " Общий образ: 0x%08x 0x%08x\n" + +#: vms-alpha.c:7513 +#, c-format +msgid "cannot read EIHI\n" +msgstr "не удалоÑÑŒ прочитать EIHI\n" + +#: vms-alpha.c:7516 +#, c-format +msgid "Image identification: (major: %u, minor: %u)\n" +msgstr "Ð˜Ð´ÐµÐ½Ñ‚Ð¸Ñ„Ð¸ÐºÐ°Ñ†Ð¸Ñ Ð¾Ð±Ñ€Ð°Ð·Ð°: (Ñтарший: %u, младший: %u)\n" + +#: vms-alpha.c:7519 +#, c-format +msgid " image name : %.*s\n" +msgstr " Ð¸Ð¼Ñ Ð¾Ð±Ñ€Ð°Ð·Ð° : %.*s\n" + +#: vms-alpha.c:7521 +#, c-format +msgid " link time : %s\n" +msgstr " Ð²Ñ€ÐµÐ¼Ñ ÐºÐ¾Ð¼Ð¿Ð¾Ð½Ð¾Ð²ÐºÐ¸ : %s\n" + +#: vms-alpha.c:7523 +#, c-format +msgid " image ident : %.*s\n" +msgstr " идент-Ñ€ образа : %.*s\n" + +#: vms-alpha.c:7525 +#, c-format +msgid " linker ident : %.*s\n" +msgstr " идент-Ñ€ компоновщика: %.*s\n" + +#: vms-alpha.c:7527 +#, c-format +msgid " image build ident: %.*s\n" +msgstr " идент-Ñ€ Ñборки образа: %.*s\n" + +#: vms-alpha.c:7537 +#, c-format +msgid "cannot read EIHS\n" +msgstr "не удалоÑÑŒ прочитать EIHS\n" + +#: vms-alpha.c:7540 +#, c-format +msgid "Image symbol & debug table: (major: %u, minor: %u)\n" +msgstr "Таблица Ñимволов & отладки образа: (Ñтарший: %u, младший: %u)\n" + +#: vms-alpha.c:7545 +#, c-format +msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" +msgstr " таблица отладочных Ñимволов: vbn: %u, размер: %u (0x%x)\n" + +#: vms-alpha.c:7549 +#, c-format +msgid " global symbol table: vbn: %u, records: %u\n" +msgstr " Ð³Ð»Ð¾Ð±Ð°Ð»ÑŒÐ½Ð°Ñ Ñ‚Ð°Ð±Ð»Ð¸Ñ†Ð° Ñимволов: vbn: %u, запиÑей: %u\n" + +#: vms-alpha.c:7553 +#, c-format +msgid " debug module table : vbn: %u, size: %u\n" +msgstr " таблица отладочных модулей: vbn: %u, размер: %u\n" + +#: vms-alpha.c:7566 +#, c-format +msgid "cannot read EISD\n" +msgstr "не удалоÑÑŒ прочитать EISD\n" + +#: vms-alpha.c:7576 +#, c-format +msgid "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" +msgstr "ДеÑкриптор раздела образа: (Ñтарший: %u, младший: %u, размер: %u, Ñмещение: %u)\n" + +#: vms-alpha.c:7583 +#, c-format +msgid " section: base: 0x%08x%08x size: 0x%08x\n" +msgstr " раздел: база: 0x%08x%08x размер: 0x%08x\n" + +#: vms-alpha.c:7588 +#, c-format +msgid " flags: 0x%04x" +msgstr " флаги: 0x%04x" + +#: vms-alpha.c:7625 +#, c-format +msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" +msgstr " vbn: %u, pfc: %u, matchctl: %u тип: %u (" + +#: vms-alpha.c:7631 +msgid "NORMAL" +msgstr "NORMAL" + +#: vms-alpha.c:7634 +msgid "SHRFXD" +msgstr "SHRFXD" + +#: vms-alpha.c:7637 +msgid "PRVFXD" +msgstr "PRVFXD" + +#: vms-alpha.c:7640 +msgid "SHRPIC" +msgstr "SHRPIC" + +#: vms-alpha.c:7643 +msgid "PRVPIC" +msgstr "PRVPIC" + +#: vms-alpha.c:7646 +msgid "USRSTACK" +msgstr "USRSTACK" + +#: vms-alpha.c:7654 +#, c-format +msgid " ident: 0x%08x, name: %.*s\n" +msgstr " иден-Ñ€: 0x%08x, имÑ: %.*s\n" + +#: vms-alpha.c:7664 +#, c-format +msgid "cannot read DMT\n" +msgstr "не удалоÑÑŒ прочитать DMT\n" + +#: vms-alpha.c:7668 +#, c-format +msgid "Debug module table:\n" +msgstr "Таблица отладочных модулей:\n" + +#: vms-alpha.c:7677 +#, c-format +msgid "cannot read DMT header\n" +msgstr "не удалоÑÑŒ прочитать заголовок DMT\n" + +#: vms-alpha.c:7682 +#, c-format +msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" +msgstr " Ñмещение модулÑ: 0x%08x, размер: 0x%08x, (%u psects)\n" + +#: vms-alpha.c:7692 +#, c-format +msgid "cannot read DMT psect\n" +msgstr "не удалоÑÑŒ прочитать DMT psect\n" + +#: vms-alpha.c:7695 +#, c-format +msgid " psect start: 0x%08x, length: %u\n" +msgstr " начало psect: 0x%08x, длина: %u\n" + +#: vms-alpha.c:7708 +#, c-format +msgid "cannot read DST\n" +msgstr "не удалоÑÑŒ прочитать DST\n" + +#: vms-alpha.c:7718 +#, c-format +msgid "cannot read GST\n" +msgstr "не удалоÑÑŒ прочитать GST\n" + +#: vms-alpha.c:7722 +#, c-format +msgid "Global symbol table:\n" +msgstr "Таблица глобальных Ñимволов:\n" + +#: vms-alpha.c:7750 +#, c-format +msgid "Image activator fixup: (major: %u, minor: %u)\n" +msgstr "Ðктиватор меÑÑ‚Ð¾Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ Ð¾Ð±Ñ€Ð°Ð·Ð°: (Ñтарший: %u, младший: %u)\n" + +#: vms-alpha.c:7753 +#, c-format +msgid " iaflink : 0x%08x %08x\n" +msgstr " iaflink : 0x%08x %08x\n" + +#: vms-alpha.c:7756 +#, c-format +msgid " fixuplnk: 0x%08x %08x\n" +msgstr " fixuplnk: 0x%08x %08x\n" + +#: vms-alpha.c:7759 +#, c-format +msgid " size : %u\n" +msgstr " размер: %u\n" + +#: vms-alpha.c:7761 +#, c-format +msgid " flags: 0x%08x\n" +msgstr " флаги: 0x%08x\n" + +#: vms-alpha.c:7765 +#, c-format +msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" +msgstr " qrelfixoff: %5u, lrelfixoff: %5u\n" + +#: vms-alpha.c:7769 +#, c-format +msgid " qdotadroff: %5u, ldotadroff: %5u\n" +msgstr " qdotadroff: %5u, ldotadroff: %5u\n" + +#: vms-alpha.c:7773 +#, c-format +msgid " codeadroff: %5u, lpfixoff : %5u\n" +msgstr " codeadroff: %5u, lpfixoff : %5u\n" + +#: vms-alpha.c:7776 +#, c-format +msgid " chgprtoff : %5u\n" +msgstr " chgprtoff : %5u\n" + +#: vms-alpha.c:7779 +#, c-format +msgid " shlstoff : %5u, shrimgcnt : %5u\n" +msgstr " shlstoff : %5u, shrimgcnt : %5u\n" + +#: vms-alpha.c:7781 +#, c-format +msgid " shlextra : %5u, permctx : %5u\n" +msgstr " shlextra : %5u, permctx : %5u\n" + +#: vms-alpha.c:7784 +#, c-format +msgid " base_va : 0x%08x\n" +msgstr " base_va : 0x%08x\n" + +#: vms-alpha.c:7786 +#, c-format +msgid " lppsbfixoff: %5u\n" +msgstr " lppsbfixoff: %5u\n" + +#: vms-alpha.c:7794 +#, c-format +msgid " Shareable images:\n" +msgstr " Общие образы:\n" + +#: vms-alpha.c:7798 +#, c-format +msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" +msgstr " %u: размер: %u, флаги: 0x%02x, имÑ: %.*s\n" + +#: vms-alpha.c:7805 +#, c-format +msgid " quad-word relocation fixups:\n" +msgstr " четверное Ñлово перемещаемых меÑтоположений:\n" + +#: vms-alpha.c:7810 +#, c-format +msgid " long-word relocation fixups:\n" +msgstr " длинное Ñлово перемещаемых меÑтоположений:\n" + +#: vms-alpha.c:7815 +#, c-format +msgid " quad-word .address reference fixups:\n" +msgstr " четверное Ñлово ÑÑылочных меÑтоположений .address:\n" + +#: vms-alpha.c:7820 +#, c-format +msgid " long-word .address reference fixups:\n" +msgstr " длинное Ñлово ÑÑылочных меÑтоположений .address:\n" + +#: vms-alpha.c:7825 +#, c-format +msgid " Code Address Reference Fixups:\n" +msgstr " СÑылочные меÑÑ‚Ð¾Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ Ð°Ð´Ñ€ÐµÑа кода:\n" + +#: vms-alpha.c:7830 +#, c-format +msgid " Linkage Pairs Referece Fixups:\n" +msgstr " СÑылочные меÑÑ‚Ð¾Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÑƒÐµÐ¼Ñ‹Ñ… пар:\n" + +#: vms-alpha.c:7839 +#, c-format +msgid " Change Protection (%u entries):\n" +msgstr " Изменение защиты (%u Ñлементов):\n" + +#: vms-alpha.c:7844 +#, c-format +msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " +msgstr " база: 0x%08x %08x, размер: 0x%08x, prot: 0x%08x " + +#. FIXME: we do not yet support relocatable link. It is not obvious +#. how to do it for debug infos. +#: vms-alpha.c:8676 +msgid "%P: relocatable link is not supported\n" +msgstr "%P: Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰Ð°ÐµÐ¼Ð°Ñ ÑÑылка не поддерживаетÑÑ\n" + +#: vms-alpha.c:8746 +msgid "%P: multiple entry points: in modules %B and %B\n" +msgstr "%P: неÑколько точек входа: в модулÑÑ… %B и %B\n" + +#: vms-lib.c:1421 +#, c-format +msgid "could not open shared image '%s' from '%s'" +msgstr "не удалоÑÑŒ открыть общий образ «%s» из «%s»" + +#: vms-misc.c:360 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "Вызов _bfd_vms_output_counted Ñ Ð½ÑƒÐ»ÐµÐ²Ñ‹Ð¼ количеÑтвом байт" + +#: vms-misc.c:365 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "Вызов _bfd_vms_output_counted Ñо Ñлишком большим количеÑтвом байт" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: разделÑемый объект XCOFF без ÑÐ¾Ð·Ð´Ð°Ð½Ð¸Ñ Ð²Ñ‹Ð²Ð¾Ð´Ð° XCOFF" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: динамичеÑкий объект без раздела .loader" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: `%s' Ñодержит номера Ñтрок, но в обрамлÑющем разделе" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: клаÑÑ %d Ñимвола `%s' не имеет Ñлементов aux" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: Ñимвол `%s' имеет нераÑпознанный тип csect: %d" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: неверный Ñимвол XTY_ER `%s': клаÑÑ %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: Ñимвол XMC_TC0 `%s' ÑвлÑетÑÑ ÐºÐ»Ð°ÑÑом %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect `%s' не в обрамлÑющем разделе" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: неправильно раÑположенный XTY_LD `%s'" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: перемещение %s:%d не в csect" + +#: xcofflink.c:3186 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: нет такого Ñимвола" + +#: xcofflink.c:3291 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "предупреждение: попытка ÑкÑпортировать неопределённый Ñимвол `%s'" + +#: xcofflink.c:3673 +msgid "error: undefined symbol __rtinit" +msgstr "ошибка: неопределённый Ñимвол __rtinit" + +#: xcofflink.c:4052 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: перемещение загрузчика в нераÑпознанном разделе `%s'" + +#: xcofflink.c:4063 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: `%s' в перемещении загрузчика, но не Ñимволе загрузчика" + +#: xcofflink.c:4079 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: перемещение загрузчика в разделе %A, доÑтупном только Ð´Ð»Ñ Ñ‡Ñ‚ÐµÐ½Ð¸Ñ" + +#: xcofflink.c:5097 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "переполнение TOC: 0x%lx > 0x10000; попробуйте Ñкомпилировать Ñ -mminimal-toc" + +#: elf32-ia64.c:1110 elf64-ia64.c:1110 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Ðевозможно оÑлабить br по адреÑу 0x%lx в разделе `%A'. ИÑпользуйте brl или коÑвенный переход." + +#: elf32-ia64.c:2809 elf64-ia64.c:2809 +msgid "@pltoff reloc against local symbol" +msgstr "перемещение @pltoff Ð´Ð»Ñ Ð»Ð¾ÐºÐ°Ð»ÑŒÐ½Ð¾Ð³Ð¾ Ñимвола" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: переполнение короткого Ñегмента данных (0x%lx >= 0x400000)" + +#: elf32-ia64.c:4441 elf64-ia64.c:4441 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp не покрывает короткий Ñегмент данных" + +#: elf32-ia64.c:4708 elf64-ia64.c:4708 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: не-pic код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸ÐµÐ¼ imm Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола `%s'" + +#: elf32-ia64.c:4775 elf64-ia64.c:4775 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: перемещение @gprel Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf32-ia64.c:4838 elf64-ia64.c:4838 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: компоновка не-pic кода в позиционно-незавиÑимый иÑполнÑемый" + +#: elf32-ia64.c:4975 elf64-ia64.c:4975 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: переход @internal на динамичеÑкий Ñимвол %s" + +#: elf32-ia64.c:4977 elf64-ia64.c:4977 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: догадка меÑÑ‚Ð¾Ð¿Ð¾Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf32-ia64.c:4979 elf64-ia64.c:4979 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: перемещение @pcrel Ð´Ð»Ñ Ð´Ð¸Ð½Ð°Ð¼Ð¸Ñ‡ÐµÑкого Ñимвола %s" + +#: elf32-ia64.c:5176 elf64-ia64.c:5176 +msgid "unsupported reloc" +msgstr "неподдерживаемое перемещение" + +#: elf32-ia64.c:5214 elf64-ia64.c:5214 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: отÑутÑтвует TLS-раздел Ð´Ð»Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ %s Ð´Ð»Ñ `%s' по адреÑу 0x%lx в разделе `%A'." + +#: elf32-ia64.c:5229 elf64-ia64.c:5229 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: Ðевозможно оÑлабить br (%s) до `%s' по адреÑу 0x%lx в разделе `%A' Ñ Ñ€Ð°Ð·Ð¼ÐµÑ€Ð¾Ð¼ 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5491 elf64-ia64.c:5491 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: компоновка trap-on-NULL-dereference Ñ Ð½Ðµ-trapping файлами" + +#: elf32-ia64.c:5500 elf64-ia64.c:5500 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: компоновка файлов Ñ Ð¿Ñ€Ñмым порÑдком байт Ñ Ñ„Ð°Ð¹Ð»Ð°Ð¼Ð¸ Ñ Ð¾Ð±Ñ€Ð°Ñ‚Ð½Ñ‹Ð¼ порÑдком байт" + +#: elf32-ia64.c:5509 elf64-ia64.c:5509 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: компоновка 64-битных файлов Ñ 32-битными файлами" + +#: elf32-ia64.c:5518 elf64-ia64.c:5518 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: компоновка constant-gp файлов Ñ Ð½Ðµ-constant-gp файлами" + +#: elf32-ia64.c:5528 elf64-ia64.c:5528 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: компоновка auto-pic файлов Ñ Ð½Ðµ-auto-pic файлами" + +#: peigen.c:1002 pepigen.c:1002 pex64igen.c:1002 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: переполнение номеров Ñтрок: 0x%lx > 0xffff" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Каталог ÑкÑпорта [.edata (или где он нашёлÑÑ)]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Import Directory [parts of .idata]" +msgstr "Каталог импорта [чаÑÑ‚ÑŒ .idata]" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Resource Directory [.rsrc]" +msgstr "Каталог реÑурÑов [.rsrc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Exception Directory [.pdata]" +msgstr "Каталог иÑключений [.pdata]" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Security Directory" +msgstr "Каталог безопаÑноÑти" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Base Relocation Directory [.reloc]" +msgstr "Каталог базового Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ [.reloc]" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Debug Directory" +msgstr "Каталог отладки" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Description Directory" +msgstr "Каталог опиÑаний" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Special Directory" +msgstr "Специальный каталог" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Thread Storage Directory [.tls]" +msgstr "Каталог хранилища нитей [.tls]" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Load Configuration Directory" +msgstr "Каталог загрузки конфигурации" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "Bound Import Directory" +msgstr "Каталог обÑзательного импорта" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Import Address Table Directory" +msgstr "Каталог таблицы импорта адреÑов" + +#: peigen.c:1042 pepigen.c:1042 pex64igen.c:1042 +msgid "Delay Import Directory" +msgstr "Каталог отложенного импорта" + +#: peigen.c:1043 pepigen.c:1043 pex64igen.c:1043 +msgid "CLR Runtime Header" +msgstr "Заголовок времени Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ñ CLR" + +#: peigen.c:1044 pepigen.c:1044 pex64igen.c:1044 +msgid "Reserved" +msgstr "Зарезервировано" + +#: peigen.c:1104 pepigen.c:1104 pex64igen.c:1104 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"СущеÑтвует таблица импорта, но не найден раздел, в котором она ÑодержитÑÑ\n" + +#: peigen.c:1109 pepigen.c:1109 pex64igen.c:1109 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Ð’ %s имеетÑÑ Ñ‚Ð°Ð±Ð»Ð¸Ñ†Ð° импорта по адреÑу 0x%lx\n" + +#: peigen.c:1151 pepigen.c:1151 pex64igen.c:1151 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Ðачальный Ð°Ð´Ñ€ÐµÑ Ð¾Ð¿Ð¸ÑÐ°Ñ‚ÐµÐ»Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ð¸: %04lx\n" + +#: peigen.c:1154 pepigen.c:1154 pex64igen.c:1154 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcode-base %08lx toc (загружаемый/реальный) %08lx/%08lx\n" + +#: peigen.c:1162 pepigen.c:1162 pex64igen.c:1162 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Ðет раздела reldata! ОпиÑатель функции не раÑшифрован.\n" + +#: peigen.c:1167 pepigen.c:1167 pex64igen.c:1167 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Таблицы импорта (обработан раздел %s)\n" + +#: peigen.c:1170 pepigen.c:1170 pex64igen.c:1170 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Таблица Отметка Цепочка Ð˜Ð¼Ñ ÐŸÐµÑ€Ð²Ñ‹Ð¹\n" +" Указаний Времени ПереÑылки DLL Шлюз\n" + +#: peigen.c:1218 pepigen.c:1218 pex64igen.c:1218 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tÐ˜Ð¼Ñ DLL: %s\n" + +#: peigen.c:1229 pepigen.c:1229 pex64igen.c:1229 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Hint/Ord ИмÑ-Ñлемента ПривÑзан-к\n" + +#: peigen.c:1254 pepigen.c:1254 pex64igen.c:1254 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"СущеÑтвует первый шлюз, но не найден раздел, в котором он ÑодержитÑÑ\n" + +#: peigen.c:1415 pepigen.c:1415 pex64igen.c:1415 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"СущеÑтвует таблица ÑкÑпорта, но не найден раздел, в котором она ÑодержитÑÑ\n" + +#: peigen.c:1424 pepigen.c:1424 pex64igen.c:1424 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"СущеÑтвует таблица ÑкÑпорта в %s, но она не помещаетÑÑ Ð² Ñтот раздел\n" + +#: peigen.c:1430 pepigen.c:1430 pex64igen.c:1430 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"СущеÑтвует таблица ÑкÑпорта в %s по адреÑу 0x%lx\n" + +#: peigen.c:1458 pepigen.c:1458 pex64igen.c:1458 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Таблицы ÑкÑпорта (обработан раздел %s)\n" +"\n" + +#: peigen.c:1462 pepigen.c:1462 pex64igen.c:1462 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Флаги ÑкÑпорта \t\t\t%lx\n" + +#: peigen.c:1465 pepigen.c:1465 pex64igen.c:1465 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Метка времени/даты \t\t%lx\n" + +#: peigen.c:1468 pepigen.c:1468 pex64igen.c:1468 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Старший/Младший \t\t\t%d/%d\n" + +#: peigen.c:1471 pepigen.c:1471 pex64igen.c:1471 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Ð˜Ð¼Ñ \t\t\t\t" + +#: peigen.c:1477 pepigen.c:1477 pex64igen.c:1477 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Ðачальный порÑдковый номер \t\t\t%ld\n" + +#: peigen.c:1480 pepigen.c:1480 pex64igen.c:1480 +#, c-format +msgid "Number in:\n" +msgstr "Ðомер в:\n" + +#: peigen.c:1483 pepigen.c:1483 pex64igen.c:1483 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tТаблица ÑкÑпортируемых адреÑов \t\t%08lx\n" + +#: peigen.c:1487 pepigen.c:1487 pex64igen.c:1487 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\tТаблица [указателей имён/порÑдковых номеров]\t%08lx\n" + +#: peigen.c:1490 pepigen.c:1490 pex64igen.c:1490 +#, c-format +msgid "Table Addresses\n" +msgstr "Таблица адреÑов\n" + +#: peigen.c:1493 pepigen.c:1493 pex64igen.c:1493 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tТаблица ÑкÑпортируемых адреÑов \t\t" + +#: peigen.c:1498 pepigen.c:1498 pex64igen.c:1498 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tТаблица указателей имён \t\t" + +#: peigen.c:1503 pepigen.c:1503 pex64igen.c:1503 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tТаблица порÑдковых номеров \t\t\t" + +#: peigen.c:1517 pepigen.c:1517 pex64igen.c:1517 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Таблица ÑкÑпортируемых адреÑов -- Ðачальный порÑдковый номер %ld\n" + +#: peigen.c:1536 pepigen.c:1536 pex64igen.c:1536 +msgid "Forwarder RVA" +msgstr "ПереадреÑуемый RVA" + +#: peigen.c:1547 pepigen.c:1547 pex64igen.c:1547 +msgid "Export RVA" +msgstr "ЭкÑпортируемый RVA" + +#: peigen.c:1554 pepigen.c:1554 pex64igen.c:1554 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"Таблица [порÑдковых номеров/указателей имён]\n" + +#: peigen.c:1614 peigen.c:1797 pepigen.c:1614 pepigen.c:1797 pex64igen.c:1614 +#: pex64igen.c:1797 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Внимание, размер раздела .pdata (%ld) не кратен %d\n" + +#: peigen.c:1621 pepigen.c:1621 pex64igen.c:1621 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tÐачальный Ð°Ð´Ñ€ÐµÑ ÐšÐ¾Ð½ÐµÑ‡Ð½Ñ‹Ð¹ Ð°Ð´Ñ€ÐµÑ Ð Ð°ÑÐºÑ€Ñ‹Ð²Ð°ÑŽÑ‰Ð°Ñ Ð˜Ð½Ñ„Ð¾Ñ€Ð¼Ð°Ñ†Ð¸Ñ\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tÐачальный Конечный EH EH ÐÐ´Ñ€ÐµÑ ÐœÐ°Ñка\n" +" \t\tÐÐ´Ñ€ÐµÑ ÐÐ´Ñ€ÐµÑ ÐžÐ±Ñ€Ð°Ð±Ð¾Ñ‚Ñ‡Ð¸Ðº Данные КонцаПролога ИÑключениÑ\n" + +#: peigen.c:1697 pepigen.c:1697 pex64igen.c:1697 +#, c-format +msgid " Register save millicode" +msgstr " Милликод ÑÐ¾Ñ…Ñ€Ð°Ð½ÐµÐ½Ð¸Ñ Ñ€ÐµÐ³Ð¸Ñтра" + +#: peigen.c:1700 pepigen.c:1700 pex64igen.c:1700 +#, c-format +msgid " Register restore millicode" +msgstr " Милликод воÑÑÑ‚Ð°Ð½Ð¾Ð²Ð»ÐµÐ½Ð¸Ñ Ñ€ÐµÐ³Ð¸Ñтра" + +#: peigen.c:1703 pepigen.c:1703 pex64igen.c:1703 +#, c-format +msgid " Glue code sequence" +msgstr " ПоÑледовательноÑÑ‚ÑŒ ÑвÑзующего кода" + +#: peigen.c:1803 pepigen.c:1803 pex64igen.c:1803 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tÐачальный Длина Длина Флаги Обработчик EH\n" +" \t\tÐÐ´Ñ€ÐµÑ ÐŸÑ€Ð¾Ð»Ð¾Ð³Ð° Функции 32b exc ИÑключений Данные\n" + +#: peigen.c:1929 pepigen.c:1929 pex64igen.c:1929 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Ðачало перемещений в PE-файле (обработан раздел .reloc)\n" + +#: peigen.c:1958 pepigen.c:1958 pex64igen.c:1958 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Виртуальный адреÑ: %08lx Размер блока %ld (0x%lx) ЧиÑло меÑтоположений %ld\n" + +#: peigen.c:1971 pepigen.c:1971 pex64igen.c:1971 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\tперемещение %4d Ñмещение %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2010 pepigen.c:2010 pex64igen.c:2010 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"ХарактериÑтики 0x%x\n" + +#: peigen.c:2310 pepigen.c:2310 pex64igen.c:2310 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: невозможно заполнить DataDictionary[1], так как отÑутÑтвует .idata$2" + +#: peigen.c:2330 pepigen.c:2330 pex64igen.c:2330 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: невозможно заполнить DataDictionary[1], так как отÑутÑтвует .idata$4" + +#: peigen.c:2351 pepigen.c:2351 pex64igen.c:2351 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: невозможно заполнить DataDictionary[12], так как отÑутÑтвует .idata$5" + +#: peigen.c:2371 pepigen.c:2371 pex64igen.c:2371 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: невозможно заполнить DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)], так как отÑутÑтвует .idata$6" + +#: peigen.c:2413 pepigen.c:2413 pex64igen.c:2413 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)] because .idata$6 is missing" +msgstr "%B: невозможно заполнить DataDictionary[PE_IMPORT_ADDRESS_TABLE(12)], так как отÑутÑтвует .idata$6" + +#: peigen.c:2436 pepigen.c:2436 pex64igen.c:2436 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: невозможно заполнить DataDictionary[9], так как отÑутÑтвует __tls_used" + +#~ msgid "Can't Make it a Short Jump" +#~ msgstr "Ðевозможно выполнить короткий переход (Short Jump)" + +#~ msgid "Exceeds Long Jump Range" +#~ msgstr "Превышен диапазон длинного перехода (Long Jump)" + +#~ msgid "Absolute address Exceeds 16 bit Range" +#~ msgstr "ÐбÑолютный Ð°Ð´Ñ€ÐµÑ Ð²Ñ‹Ñ…Ð¾Ð´Ð¸Ñ‚ за 16-битный диапазон" + +#~ msgid "Absolute address Exceeds 8 bit Range" +#~ msgstr "ÐбÑолютный Ð°Ð´Ñ€ÐµÑ Ð²Ñ‹Ñ…Ð¾Ð´Ð¸Ñ‚ за 8-битный диапазон" + +#~ msgid "Unrecognized Reloc Type" +#~ msgstr "Ðе раÑпознан тип Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ (Reloc Type)" + +#~ msgid "corrupt or empty %s section in %B" +#~ msgstr "повреждённый или пуÑтой раздел %s в %B" + +#~ msgid "%s: invalid DSO for symbol `%s' definition" +#~ msgstr "%s: недопуÑтимый DSO Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ñимвола `%s'" + +#~ msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +#~ msgstr "%B: %A+0x%lx: переход в процедуру заглушки, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð½Ðµ не ÑвлÑетÑÑ jal (Jump And Link)" + +#~ msgid "bfd_make_section (%s) failed" +#~ msgstr "bfd_make_section (%s) завершилаÑÑŒ неудачно" + +#~ msgid "bfd_set_section_flags (%s, %x) failed" +#~ msgstr "bfd_set_section_flags (%s, %x) завершилаÑÑŒ неудачно" + +#~ msgid "Size mismatch section %s=%lx, %s=%lx" +#~ msgstr "ÐеÑовпадение размера раздела %s=%lx, %s=%lx" + +#~ msgid "failed to enter %s" +#~ msgstr "не удалоÑÑŒ войти %s" + +#~ msgid "No Mem !" +#~ msgstr "Ðет Mem !" + +#~ msgid "reserved STO cmd %d" +#~ msgstr "зарезервированный STO cmd %d" + +#~ msgid "reserved OPR cmd %d" +#~ msgstr "зарезервированный OPR cmd %d" + +#~ msgid "reserved CTL cmd %d" +#~ msgstr "зарезервированный CTL cmd %d" + +#~ msgid "reserved STC cmd %d" +#~ msgstr "зарезервированный STC cmd %d" + +#~ msgid "stack-from-image not implemented" +#~ msgstr "stack-from-image не реализован" + +#~ msgid "stack-entry-mask not fully implemented" +#~ msgstr "stack-entry-mask реализован не полноÑтью" + +#~ msgid "PASSMECH not fully implemented" +#~ msgstr "PASSMECH реализован не полноÑтью" + +#~ msgid "stack-local-symbol not fully implemented" +#~ msgstr "stack-local-symbol реализован не полноÑтью" + +#~ msgid "stack-literal not fully implemented" +#~ msgstr "stack-literal реализован не полноÑтью" + +#~ msgid "stack-local-symbol-entry-point-mask not fully implemented" +#~ msgstr "stack-local-symbol-entry-point-mask реализован не полноÑтью" + +#~ msgid "%s: not fully implemented" +#~ msgstr "%s: реализовано не полноÑтью" + +#~ msgid "obj code %d not found" +#~ msgstr "объектный код %d не найден" + +#~ msgid "Reloc size error in section %s" +#~ msgstr "Ошибка размера Ð¿ÐµÑ€ÐµÐ¼ÐµÑ‰ÐµÐ½Ð¸Ñ Ð² разделе %s" diff --git a/external/gpl3/gdb/dist/bfd/po/rw.gmo b/external/gpl3/gdb/dist/bfd/po/rw.gmo new file mode 100644 index 0000000000000000000000000000000000000000..49d9e2fd45e3653895273f350eef4aab94821463 GIT binary patch literal 429 zcmYL^-%i3X6vn5~#O%^*FM6+?9k4(q5)#CO=n!>!;a%CzMs>8LJp*|V-@xbcSv)gD zzVw%zw%_^pb9(gUkq(J7;(|CP`b47{aY8&2lLOCt+ugq@rt_yJ_g_=Pz*=LynKkc_ zA)n;@6|7T6$828YtQCZjKYK{|$bv+A<~I@{W-TGwTy%NZWnm|dTIV7Zf{gqL)~ZS0 z`ywtnT(nsz;)vod`R=7do?5A0CDGWJJtM3^vqWVJ2^C9fyIO2ne_7jN2po;6T#%XN zfHHMi%My4Bav8HbrMJ>, 2005 +# Steve performed initial rough translation from compendium built from translations provided by the following translators: +# Philibert Ndandali , 2005. +# Viateur MUGENZI , 2005. +# Noëlla Mupole , 2005. +# Carole Karema , 2005. +# JEAN BAPTISTE NGENDAHAYO , 2005. +# Augustin KIBERWA , 2005. +# Donatien NSENGIYUMVA , 2005. +# Antoine Bigirimana , 2005. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.15\n" +"POT-Creation-Date: 2003-07-17 14:52+0100\n" +"PO-Revision-Date: 2005-04-03 10:55-0700\n" +"Last-Translator: Steven Michael Murphy \n" +"Language-Team: Kinyarwanda \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:204 +#, fuzzy, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s:Inyuma." + +#: aout-cris.c:207 +#, fuzzy, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s:Ubwoko" + +#: aout-cris.c:251 +#, fuzzy, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s:Ubwoko cyavuye ahandi/ cyatumijwe" + +#: aout-cris.c:262 +#, fuzzy, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s:Icyabitswe cyavuye ahandi/ cyatumijwe" + +#: aoutx.h:1295 aoutx.h:1716 +#, fuzzy, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s:OYA Icyiciro in a Inyuma Igikoresho IDOSIYE Imiterere" + +#: aoutx.h:1682 +#, fuzzy, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s:OYA Icyiciro kugirango IKIMENYETSO in a Inyuma Igikoresho IDOSIYE Imiterere" + +#: aoutx.h:1684 +#, fuzzy +msgid "*unknown*" +msgstr "*Itazwi>" + +#: aoutx.h:3776 +#, fuzzy, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s:Ihuza Bivuye Kuri OYA" + +#: archive.c:1751 +#, fuzzy +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Buhoro" + +#: archive.c:2014 +#, fuzzy +msgid "Reading archive file mod timestamp" +msgstr "IDOSIYE MOD" + +#: archive.c:2040 +msgid "Writing updated armap timestamp" +msgstr "" + +# padmin/source\padialog.src:RID_AFMERROR_OK.text +#: bfd.c:280 +msgid "No error" +msgstr "Nta kosa" + +#: bfd.c:281 +#, fuzzy +msgid "System call error" +msgstr "Ikosa" + +#: bfd.c:282 +#, fuzzy +msgid "Invalid bfd target" +msgstr "Intego" + +#: bfd.c:283 +#, fuzzy +msgid "File in wrong format" +msgstr "Idosiye in Imiterere" + +#: bfd.c:284 +#, fuzzy +msgid "Archive object file in wrong format" +msgstr "Igikoresho IDOSIYE in Imiterere" + +#: bfd.c:285 +msgid "Invalid operation" +msgstr "" + +#: bfd.c:286 +msgid "Memory exhausted" +msgstr "" + +#: bfd.c:287 +#, fuzzy +msgid "No symbols" +msgstr "Ibimenyetso" + +#: bfd.c:288 +#, fuzzy +msgid "Archive has no index; run ranlib to add one" +msgstr "Oya Umubarendanga Gukoresha Kuri Kongeramo" + +#: bfd.c:289 +#, fuzzy +msgid "No more archived files" +msgstr "Birenzeho Idosiye" + +#: bfd.c:290 +msgid "Malformed archive" +msgstr "" + +#: bfd.c:291 +#, fuzzy +msgid "File format not recognized" +msgstr "Idosiye Imiterere OYA" + +#: bfd.c:292 +#, fuzzy +msgid "File format is ambiguous" +msgstr "Idosiye Imiterere ni" + +#: bfd.c:293 +#, fuzzy +msgid "Section has no contents" +msgstr "Oya Ibigize" + +#: bfd.c:294 +#, fuzzy +msgid "Nonrepresentable section on output" +msgstr "Icyiciro ku Ibisohoka" + +#: bfd.c:295 +#, fuzzy +msgid "Symbol needs debug section which does not exist" +msgstr "Kosora amakosa Icyiciro OYA" + +#: bfd.c:296 +#, fuzzy +msgid "Bad value" +msgstr "Agaciro" + +#: bfd.c:297 +#, fuzzy +msgid "File truncated" +msgstr "Idosiye" + +#: bfd.c:298 +#, fuzzy +msgid "File too big" +msgstr "Idosiye" + +#: bfd.c:299 +#, fuzzy +msgid "#" +msgstr "# 0xffff" +msgstr "%s:%s:Byarenze urugero" + +#: cofflink.c:2680 coffswap.h:876 +#, fuzzy, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s:Iburira Umurongo Umubare Byarenze urugero" + +#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783 +#, fuzzy +msgid "unsupported reloc type" +msgstr "Ubwoko" + +#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554 +#, fuzzy +msgid "GP relative relocation when _gp not defined" +msgstr "Bifitanye isano Ryari: OYA" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2431 +#, fuzzy +msgid "reloc against unsupported section" +msgstr "Icyiciro" + +#: coff-mips.c:2439 +#, fuzzy +msgid "reloc not properly aligned" +msgstr "OYA" + +#: coff-rs6000.c:2790 +#, fuzzy, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s:Ubwoko" + +#: coff-rs6000.c:2883 +#, fuzzy, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s:ku Kuri IKIMENYETSO Na: Oya Icyinjijwe" + +#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450 +#, fuzzy, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Ubwoko" + +#: coff-w65.c:364 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "" + +#: cpu-arm.c:196 cpu-arm.c:206 +#, fuzzy, c-format +msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale" +msgstr "ni kugirango i ni kugirango" + +#: cpu-arm.c:344 +#, fuzzy, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "Iburira Kuri Kuvugurura Ibigize Bya Icyiciro in" + +#: dwarf2.c:380 +#, fuzzy +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Gushaka Icyiciro" + +#: dwarf2.c:397 +#, fuzzy, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano" + +#: dwarf2.c:541 +#, fuzzy +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Gushaka Icyiciro" + +#: dwarf2.c:556 +#, fuzzy, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano" + +#: dwarf2.c:756 +#, fuzzy, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Cyangwa Agaciro" + +#: dwarf2.c:933 +#, fuzzy +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Umurongo Umubare Icyiciro IDOSIYE Umubare" + +#: dwarf2.c:1032 +#, fuzzy +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Gushaka Icyiciro" + +#: dwarf2.c:1049 +#, fuzzy, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano" + +#: dwarf2.c:1255 +#, fuzzy +msgid "Dwarf Error: mangled line number section." +msgstr "Umurongo Umubare Icyiciro" + +#: dwarf2.c:1470 dwarf2.c:1620 +#, fuzzy, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "OYA Gushaka Umubare" + +#: dwarf2.c:1581 +#, fuzzy, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Byabonetse Verisiyo iyi Verisiyo 2. Ibisobanuro" + +#: dwarf2.c:1588 +#, fuzzy, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Byabonetse Aderesi Ingano iyi OYA Biruta" + +#: dwarf2.c:1611 +#, fuzzy, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Umubare" + +#: ecoff.c:1339 +#, fuzzy, c-format +msgid "Unknown basic type %d" +msgstr "BASIC Ubwoko" + +#: ecoff.c:1599 +#, fuzzy, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "Impera 1. IKIMENYETSO" + +#: ecoff.c:1606 ecoff.c:1609 +#, fuzzy, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "IKIMENYETSO" + +#: ecoff.c:1621 +#, fuzzy, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "Impera 1. IKIMENYETSO" + +#: ecoff.c:1628 +#, fuzzy, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "IKIMENYETSO" + +#: ecoff.c:1636 +#, fuzzy, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "Impera 1. IKIMENYETSO" + +#: ecoff.c:1641 +#, fuzzy, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "Ihuza Impera 1. IKIMENYETSO" + +#: ecoff.c:1646 +#, fuzzy, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "Impera 1. IKIMENYETSO" + +# #-#-#-#-# dbaccess.pot (PACKAGE VERSION) #-#-#-#-# +# #-#-#-#-# dbaccess.pot (PACKAGE VERSION) #-#-#-#-# +#: ecoff.c:1652 +#, fuzzy, c-format +msgid "" +"\n" +" Type: %s" +msgstr "Ubwoko" + +#: elf32-arm.h:1228 +#, fuzzy, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "%s:Umumaro" + +#: elf32-arm.h:1424 +#, fuzzy, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%s:Umumaro" + +#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx):%sIcyiciro" + +#: elf32-arm.h:2012 +#, fuzzy, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro" + +#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812 +#: elf32-cris.c:1390 elf32-d10v.c:482 elf32-fr30.c:634 elf32-frv.c:815 +#: elf32-h8300.c:509 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699 +#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510 +#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976 +#: elf64-mmix.c:1332 +#, fuzzy +msgid "internal error: out of range error" +msgstr "By'imbere Ikosa Inyuma Bya Urutonde Ikosa" + +#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816 +#: elf32-cris.c:1394 elf32-d10v.c:486 elf32-fr30.c:638 elf32-frv.c:819 +#: elf32-h8300.c:513 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287 +#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440 +#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452 +#, fuzzy +msgid "internal error: unsupported relocation error" +msgstr "By'imbere Ikosa Ikosa" + +#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:490 +#: elf32-h8300.c:517 elf32-m32r.c:1291 elf32-m68hc1x.c:1313 +#, fuzzy +msgid "internal error: dangerous error" +msgstr "By'imbere Ikosa Ikosa" + +#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824 +#: elf32-cris.c:1402 elf32-d10v.c:494 elf32-fr30.c:646 elf32-frv.c:827 +#: elf32-h8300.c:521 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711 +#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522 +#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988 +#: elf64-mmix.c:1344 +#, fuzzy +msgid "internal error: unknown error" +msgstr "By'imbere Ikosa Kitazwi Ikosa" + +#: elf32-arm.h:2202 +#, fuzzy, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "i Ibendera Bya ITEGEKONGENGA in Na:" + +#: elf32-arm.h:2302 +#, fuzzy, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "ni kugirango Verisiyo ni kugirango Verisiyo" + +#: elf32-arm.h:2316 +#, fuzzy, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "ni kugirango Intego" + +#: elf32-arm.h:2344 +#, fuzzy, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s does not" +msgstr "Amabwiriza OYA" + +#: elf32-arm.h:2349 +#, fuzzy, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s does not" +msgstr "Amabwiriza OYA" + +#: elf32-arm.h:2360 elf32-arm.h:2365 +#, fuzzy, c-format +msgid "ERROR: %s uses Maverick instructions, whereas %s does not" +msgstr "Amabwiriza OYA" + +#: elf32-arm.h:2385 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "" + +#: elf32-arm.h:2390 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9240 +#, fuzzy, c-format +msgid "private flags = %lx:" +msgstr "By'umwihariko Amabendera" + +#: elf32-arm.h:2452 +#, fuzzy +msgid " [interworking enabled]" +msgstr "[Bikora" + +#: elf32-arm.h:2460 +#, fuzzy +msgid " [VFP float format]" +msgstr "[Kureremba Imiterere" + +#: elf32-arm.h:2462 +#, fuzzy +msgid " [Maverick float format]" +msgstr "[Kureremba Imiterere" + +#: elf32-arm.h:2464 +#, fuzzy +msgid " [FPA float format]" +msgstr "[Kureremba Imiterere" + +#: elf32-arm.h:2473 +#, fuzzy +msgid " [new ABI]" +msgstr "[Gishya" + +#: elf32-arm.h:2476 +#, fuzzy +msgid " [old ABI]" +msgstr "[ki/ bishaje" + +#: elf32-arm.h:2479 +msgid " [software FP]" +msgstr "" + +#: elf32-arm.h:2488 +msgid " [Version1 EABI]" +msgstr "" + +#: elf32-arm.h:2491 elf32-arm.h:2502 +#, fuzzy +msgid " [sorted symbol table]" +msgstr "[bishunguwe IKIMENYETSO imbonerahamwe#" + +#: elf32-arm.h:2493 elf32-arm.h:2504 +#, fuzzy +msgid " [unsorted symbol table]" +msgstr "[bitashunguye IKIMENYETSO imbonerahamwe#" + +#: elf32-arm.h:2499 +msgid " [Version2 EABI]" +msgstr "" + +#: elf32-arm.h:2507 +#, fuzzy +msgid " [dynamic symbols use segment index]" +msgstr "[Ibimenyetso Gukoresha Umubarendanga" + +#: elf32-arm.h:2510 +#, fuzzy +msgid " [mapping symbols precede others]" +msgstr "[Igereranya Ibimenyetso Ibindi" + +#: elf32-arm.h:2517 +#, fuzzy +msgid " " +msgstr "" +msgstr " MIME- Version: 1. 0\n" +"Content- Type: text/ plain; charset= UTF- 8\n" +"Content- Transfer- Encoding: 8bit\n" +"X- Generator: KBabel 1. 0\n" +"." + +#: elf32-i386.c:326 +#, fuzzy, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s:Sibyo Ubwoko" + +#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637 +#: elf64-s390.c:943 elf64-x86-64.c:650 +#, fuzzy, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s:IKIMENYETSO Umubarendanga" + +#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011 +#: elf64-s390.c:1129 +#, fuzzy, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "%s:`%s'birabonetse Byombi Nka Bisanzwe Na Urudodo IKIMENYETSO" + +#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243 +#: elf64-x86-64.c:886 +#, fuzzy, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s:Icyiciro Izina:" + +#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879 +#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664 +#: elf64-x86-64.c:2452 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%s(%s+0x%lx):IKIMENYETSO" + +#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068 +#: elf64-x86-64.c:2490 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "%s(%s+0x%lx):Ikosa" + +#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740 +#, fuzzy +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "Hindura imbonerahamwe# Byuzuye Ibisobanuro" + +#: elf32-ip2k.c:588 elf32-ip2k.c:767 +#, fuzzy +msgid "ip2k relaxer: switch table header corrupt." +msgstr "Hindura imbonerahamwe# Umutwempangano" + +#: elf32-ip2k.c:1395 +#, fuzzy, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "Ibuze Ipaji ku" + +#: elf32-ip2k.c:1409 +#, fuzzy, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "Ipaji ku" + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1593 +#, fuzzy +msgid "unsupported relocation between data/insn address spaces" +msgstr "hagati Ibyatanzwe Aderesi Imyanya" + +#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072 +#: elfxx-mips.c:9197 +#, fuzzy, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s:Imyanya Ibanjirije Modire" + +#: elf32-m32r.c:930 +#, fuzzy +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "Ryari: OYA" + +#: elf32-ia64.c:3817 elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 +#: elf64-ia64.c:3817 +#, fuzzy, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s:Kitazwi Ubwoko" + +#: elf32-m32r.c:1226 +#, fuzzy, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s:Intego Bya ni in i Icyiciro" + +#: elf32-m32r.c:1952 +#, fuzzy, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "%s:Gushyiraho Na: Ibanjirije Modire" + +#: elf32-m32r.c:1975 +#, fuzzy, c-format +msgid "private flags = %lx" +msgstr "By'umwihariko Amabendera" + +#: elf32-m32r.c:1980 +#, fuzzy +msgid ": m32r instructions" +msgstr ":Amabwiriza" + +#: elf32-m32r.c:1981 +#, fuzzy +msgid ": m32rx instructions" +msgstr ":Amabwiriza" + +#: elf32-m68hc1x.c:1217 +#, fuzzy, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Kuri i IKIMENYETSO ikoresha a Gicurasi Igisubizo in" + +#: elf32-m68hc1x.c:1240 +#, fuzzy, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "Aderesi ni OYA in i Nka KIGEZWEHO Aderesi" + +#: elf32-m68hc1x.c:1259 +#, fuzzy, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "Indango Kuri a Aderesi in i Bisanzwe Aderesi Umwanya ku" + +#: elf32-m68hc1x.c:1396 +#, fuzzy, c-format +msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%s:Impuza Idosiye kugirango Na Ibindi kugirango" + +#: elf32-m68hc1x.c:1404 +#, fuzzy, c-format +msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%s:Impuza Idosiye kugirango MAHARAKUBIRI MAHARAKUBIRI Na Ibindi kugirango MAHARAKUBIRI" + +#: elf32-m68hc1x.c:1414 +#, fuzzy, c-format +msgid "%s: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%s:Impuza Idosiye kugirango Na: Ibindi kugirango" + +#: elf32-m68hc1x.c:1462 +#, fuzzy +msgid "[abi=32-bit int, " +msgstr "[INT" + +#: elf32-m68hc1x.c:1464 +#, fuzzy +msgid "[abi=16-bit int, " +msgstr "[INT" + +#: elf32-m68hc1x.c:1467 +#, fuzzy +msgid "64-bit double, " +msgstr "MAHARAKUBIRI" + +#: elf32-m68hc1x.c:1469 +#, fuzzy +msgid "32-bit double, " +msgstr "MAHARAKUBIRI" + +#: elf32-m68hc1x.c:1472 +#, fuzzy +msgid "cpu=HC11]" +msgstr "CPU" + +#: elf32-m68hc1x.c:1474 +#, fuzzy +msgid "cpu=HCS12]" +msgstr "CPU" + +#: elf32-m68hc1x.c:1476 +#, fuzzy +msgid "cpu=HC12]" +msgstr "CPU" + +#: elf32-m68hc1x.c:1479 +#, fuzzy +msgid " [memory=bank-model]" +msgstr "[Ububiko Urugero" + +#: elf32-m68hc1x.c:1481 +#, fuzzy +msgid " [memory=flat]" +msgstr "[Ububiko Kirambuye" + +#: elf32-m68k.c:400 +msgid " [cpu32]" +msgstr "" + +#: elf32-m68k.c:403 +msgid " [m68000]" +msgstr "" + +#: elf32-mcore.c:353 elf32-mcore.c:456 +#, fuzzy, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "%s:ni OYA" + +#: elf32-mcore.c:441 +#, fuzzy, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s:Ubwoko" + +#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664 +#, fuzzy +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "Bifitanye isano kugirango external IKIMENYETSO" + +#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783 +#, fuzzy, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "Ibintu Imiterere ni OYA" + +#: elf32-ppc.c:2056 +#, fuzzy, c-format +msgid "generic linker can't handle %s" +msgstr "Gifitanye isano" + +#: elf32-ppc.c:2138 +#, fuzzy, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s:Na: Na Na: Modire" + +#: elf32-ppc.c:2147 +#, fuzzy, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s:Na Na: Modire Na:" + +#: elf32-ppc.c:3413 +#, fuzzy, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s:Ryari: a Igikoresho" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3619 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): %s reloc against local symbol" +msgstr "%s(%s+0x%lx):%sIKIMENYETSO" + +#: elf32-ppc.c:4862 elf64-ppc.c:7789 +#, fuzzy, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%s:Kitazwi Ubwoko kugirango IKIMENYETSO" + +#: elf32-ppc.c:5113 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%s(%s+0x%lx):Zeru ku" + +#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484 +#, fuzzy, c-format +msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%s:i Intego Bya a ni in i Ibisohoka Icyiciro" + +#: elf32-ppc.c:5539 +#, fuzzy, c-format +msgid "%s: relocation %s is not yet supported for symbol %s." +msgstr "%s:ni OYA kugirango IKIMENYETSO" + +#: elf32-ppc.c:5594 elf64-ppc.c:8461 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%s(%s+0x%lx):IKIMENYETSO" + +#: elf32-ppc.c:5644 elf64-ppc.c:8507 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): %s reloc against `%s': error %d" +msgstr "%s(%s+0x%lx):%sIkosa" + +#: elf32-ppc.c:5888 +#, fuzzy, c-format +msgid "corrupt or empty %s section in %s" +msgstr "Cyangwa ubusa Icyiciro in" + +#: elf32-ppc.c:5895 +#, fuzzy, c-format +msgid "unable to read in %s section from %s" +msgstr "Kuri Gusoma in Icyiciro Bivuye" + +#: elf32-ppc.c:5901 +#, fuzzy, c-format +msgid "corrupt %s section in %s" +msgstr "Icyiciro in" + +#: elf32-ppc.c:5944 +#, fuzzy, c-format +msgid "warning: unable to set size of %s section in %s" +msgstr "Iburira Kuri Gushyiraho Ingano Bya Icyiciro in" + +#: elf32-ppc.c:5994 +#, fuzzy +msgid "failed to allocate space for new APUinfo section." +msgstr "Byanze Kuri Umwanya kugirango Gishya Icyiciro" + +#: elf32-ppc.c:6013 +#, fuzzy +msgid "failed to compute new APUinfo section." +msgstr "Byanze Kuri Gishya Icyiciro" + +#: elf32-ppc.c:6016 +#, fuzzy +msgid "failed to install new APUinfo section." +msgstr "Byanze Kuri Kwinjiza porogaramu Gishya Icyiciro" + +#: elf32-s390.c:2256 elf64-s390.c:2226 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%s(%s+0x%lx):Sibyo kugirango" + +#: elf32-sh64.c:221 elf64-sh64.c:2407 +#, fuzzy, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s:Nka Igikoresho Na ni" + +#: elf32-sh64.c:224 elf64-sh64.c:2410 +#, fuzzy, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s:Nka Igikoresho Na ni" + +#: elf32-sh64.c:226 elf64-sh64.c:2412 +#, fuzzy, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s:Igikoresho Ingano OYA BIHUYE Bya Intego" + +#: elf32-sh64.c:461 elf64-sh64.c:2990 +#, fuzzy, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s:IKIMENYETSO in Iyinjiza" + +#: elf32-sh64.c:544 +#, fuzzy +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "a Aderesi 0 1." + +#: elf32-sh64.c:547 +#, fuzzy +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "a Aderesi 0 0" + +#: elf32-sh64.c:565 +#, fuzzy, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s:Ikosa Na:" + +#: elf32-sh64.c:614 elf64-sh64.c:1748 +#, fuzzy, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s:Ikosa Ubwoko ku" + +#: elf32-sh64.c:698 +#, fuzzy, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s:OYA Kwandika Inyuma Kyongewe Ibyinjijwe" + +#: elf32-sh64.c:760 +#, fuzzy, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s:OYA Kwandika Inyuma bishunguwe Ibyinjijwe" + +#: elf32-sh.c:2103 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s:Iburira Nta- boneza" + +#: elf32-sh.c:2115 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s:Iburira Utudomo Kuri" + +#: elf32-sh.c:2132 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s:Iburira Ibirimo Nta- boneza" + +#: elf32-sh.c:2147 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s:Iburira OYA Gushaka Ikitezwe:" + +#: elf32-sh.c:2175 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s:Iburira IKIMENYETSO in Icyiciro" + +#: elf32-sh.c:2300 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s:Iburira OYA Gushaka Ikitezwe:" + +#: elf32-sh.c:2309 +#, fuzzy, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s:Iburira IBARA" + +#: elf32-sh.c:2712 elf32-sh.c:3088 +#, fuzzy, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s:Byarenze urugero" + +#: elf32-sh.c:4654 elf64-sh64.c:1585 +#, fuzzy +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "ku IKIMENYETSO ni OYA" + +#: elf32-sh.c:4809 +#, fuzzy, c-format +msgid "%s: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s:IKIMENYETSO Bivuye Icyiciro" + +#: elf32-sh.c:4881 +#, fuzzy, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%s:Intego kugirango Gushigikira" + +#: elf32-sh.c:6627 elf64-alpha.c:4848 +#, fuzzy, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "%s:ITEGEKONGENGA Ibintu" + +#: elf32-sparc.c:2521 elf64-sparc.c:2314 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "" + +#: elf32-sparc.c:3348 +#, fuzzy, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s:kugirango a Sisitemu Na Intego ni" + +#: elf32-sparc.c:3362 +#, fuzzy, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s:Impuza Idosiye Na: Idosiye" + +#: elf32-v850.c:753 +#, fuzzy, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "in Igikubo Gitoya Ibyatanzwe" + +#: elf32-v850.c:756 +#, fuzzy, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "in Bya i Gitoya Zeru Na Bito Ibyatanzwe" + +#: elf32-v850.c:759 +#, fuzzy, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "in Byombi Gitoya Na Zeru Ibyatanzwe" + +#: elf32-v850.c:762 +#, fuzzy, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "in Byombi Gitoya Na Bito Ibyatanzwe" + +#: elf32-v850.c:765 +#, fuzzy, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "in Byombi Zeru Na Bito Ibyatanzwe" + +#: elf32-v850.c:1144 +#, fuzzy +msgid "FAILED to find previous HI16 reloc\n" +msgstr "Kuri Gushaka Ibanjirije" + +#: elf32-v850.c:1789 +#, fuzzy +msgid "could not locate special linker symbol __gp" +msgstr "OYA Bidasanzwe IKIMENYETSO" + +#: elf32-v850.c:1793 +#, fuzzy +msgid "could not locate special linker symbol __ep" +msgstr "OYA Bidasanzwe IKIMENYETSO" + +#: elf32-v850.c:1797 +#, fuzzy +msgid "could not locate special linker symbol __ctbp" +msgstr "OYA Bidasanzwe IKIMENYETSO" + +#: elf32-v850.c:1963 +#, fuzzy, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s:Na: Ibanjirije Modire" + +#: elf32-v850.c:1983 +#, fuzzy, c-format +msgid "private flags = %lx: " +msgstr "By'umwihariko Amabendera" + +#: elf32-v850.c:1988 +msgid "v850 architecture" +msgstr "" + +#: elf32-v850.c:1989 +msgid "v850e architecture" +msgstr "" + +#: elf32-vax.c:549 +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:552 +#, fuzzy +msgid " [d-float]" +msgstr "[D Kureremba" + +#: elf32-vax.c:555 +#, fuzzy +msgid " [g-float]" +msgstr "[g Kureremba" + +#: elf32-vax.c:663 +#, fuzzy, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s:Iburira Bya Kuri OYA BIHUYE Ibanjirije Bya" + +#: elf32-vax.c:1667 +#, fuzzy, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s:Iburira Bya Kuri Bivuye Icyiciro" + +#: elf32-vax.c:1802 +#, fuzzy, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro" + +#: elf32-vax.c:1808 +#, fuzzy, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s:Iburira Kuri Bivuye Icyiciro" + +#: elf32-ia64.c:2326 elf32-xstormy16.c:462 elf64-ia64.c:2326 +#, fuzzy +msgid "non-zero addend in @fptr reloc" +msgstr "Zeru in" + +#: elf64-alpha.c:1108 +#, fuzzy +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "OYA Gushaka Na Amabwiriza" + +#: elf64-alpha.c:3731 +#, fuzzy, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "" +"%s:.Project- Id- Version: basctl\n" +"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n" +"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n" +"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n" +"Content- Type: text/ plain; charset= UTF- 8\n" +"Content- Transfer- Encoding: 8bit\n" +"X- Generator: KBabel 1. 0\n" +"." + +#: elf64-alpha.c:4602 elf64-alpha.c:4614 +#, fuzzy, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "%s:Bifitanye isano IKIMENYETSO" + +#: elf64-alpha.c:4640 elf64-alpha.c:4773 +#, fuzzy, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "%s:Bifitanye isano IKIMENYETSO" + +#: elf64-alpha.c:4668 +#, fuzzy, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "%s:Guhindura>> in" + +#: elf64-alpha.c:4693 +#, fuzzy +msgid "" +msgstr "" + +#: elf64-alpha.c:4698 +#, fuzzy, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "%s:!IKIMENYETSO" + +#: elf64-alpha.c:4749 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "" + +#: elf64-alpha.c:4832 +#, fuzzy, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "%s:Bifitanye isano IKIMENYETSO" + +#: elf64-alpha.c:4855 +#, fuzzy, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "%s:Bifitanye isano IKIMENYETSO" + +#: elf64-hppa.c:2086 +#, fuzzy, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "Icyinjijwe kugirango Ibirimo Nta- boneza" + +#: elf64-mmix.c:1032 +#, fuzzy, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "%s:Ikosa kugirango Agaciro Kwiyandikisha" + +#: elf64-mmix.c:1416 +#, fuzzy, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s:SHINGIRO Guteranya Nta- boneza Kwiyandikisha IKIMENYETSO Kitazwi in" + +#: elf64-mmix.c:1421 +#, fuzzy, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s:SHINGIRO Guteranya Nta- boneza Kwiyandikisha IKIMENYETSO in" + +#: elf64-mmix.c:1465 +#, fuzzy, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s:Kwiyandikisha Kwiyandikisha IKIMENYETSO Kitazwi in" + +#: elf64-mmix.c:1470 +#, fuzzy, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s:Kwiyandikisha Kwiyandikisha IKIMENYETSO in" + +#: elf64-mmix.c:1507 +#, fuzzy, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s:Byemewe Na: a Kwiyandikisha Cyangwa Agaciro" + +#: elf64-mmix.c:1535 +#, fuzzy, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s:ni OYA a Kwiyandikisha Kwiyandikisha ni" + +#: elf64-mmix.c:1994 +#, fuzzy, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s:Igikubo Insobanuro Bya Gutangira Bya ni Gushyiraho in a" + +#: elf64-mmix.c:2053 +#, fuzzy +msgid "Register section has contents\n" +msgstr "Icyiciro" + +#: elf64-mmix.c:2216 +#, fuzzy, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "KININI Icyegeranyo iyi" + +#: elf64-ppc.c:2388 libbfd.c:831 +#, fuzzy, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s:kugirango a Sisitemu Na Intego ni" + +#: elf64-ppc.c:2391 libbfd.c:833 +#, fuzzy, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s:kugirango a Sisitemu Na Intego ni" + +#: elf64-ppc.c:4857 +#, fuzzy, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s:Ubwoko in Icyiciro" + +#: elf64-ppc.c:4877 +#, fuzzy, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "" +"%s:.Project- Id- Version: basctl\n" +"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n" +"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n" +"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n" +"Content- Type: text/ plain; charset= UTF- 8\n" +"Content- Transfer- Encoding: 8bit\n" +"X- Generator: KBabel 1. 0\n" +"." + +#: elf64-ppc.c:4897 +#, fuzzy, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s:kidasobanuye in Icyiciro" + +#: elf64-ppc.c:6136 +#, fuzzy, c-format +msgid "can't find branch stub `%s'" +msgstr "Gushaka" + +#: elf64-ppc.c:6175 elf64-ppc.c:6250 +#, fuzzy, c-format +msgid "linkage table error against `%s'" +msgstr "imbonerahamwe# Ikosa" + +#: elf64-ppc.c:6340 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:7047 +#, fuzzy +msgid ".glink and .plt too far apart" +msgstr "" +".Project- Id- Version: basctl\n" +"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n" +"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n" +"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n" +"Content- Type: text/ plain; charset= UTF- 8\n" +"Content- Transfer- Encoding: 8bit\n" +"X- Generator: KBabel 1. 0\n" +"." + +#: elf64-ppc.c:7135 +#, fuzzy +msgid "stubs don't match calculated size" +msgstr "BIHUYE Ingano" + +#: elf64-ppc.c:7147 +#, fuzzy, c-format +msgid "" +"linker stubs in %u groups\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "in" + +#: elf64-ppc.c:7723 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%s(%s+0x%lx):Byikoresha Igikubo OYA ikoresha Idosiye Na: Cyangwa" + +#: elf64-ppc.c:7731 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%s(%s+0x%lx):Kuri OYA Kwemerera Byikoresha Igikubo Na: Cyangwa Kugeza ku ndunduro Amahamagara: Cyangwa Ubwoko" + +#: elf64-ppc.c:8329 +#, fuzzy, c-format +msgid "%s: relocation %s is not supported for symbol %s." +msgstr "%s:ni OYA kugirango IKIMENYETSO" + +#: elf64-ppc.c:8408 +#, fuzzy, c-format +msgid "%s: error: relocation %s not a multiple of %d" +msgstr "%s:Ikosa OYA a Igikubo Bya" + +#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704 +#, fuzzy, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro" + +#: elf64-sparc.c:1370 +#, fuzzy, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s:Ubwoko" + +#: elf64-sparc.c:1407 +#, fuzzy, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s:ikoresha" + +#: elf64-sparc.c:1427 +#, fuzzy, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "in in" + +#: elf64-sparc.c:1450 +#, fuzzy, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "in in" + +#: elf64-sparc.c:1496 +#, fuzzy, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "in in" + +#: elf64-sparc.c:3053 +#, fuzzy, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "%s:Impuza Na: ITEGEKONGENGA" + +#: elf64-x86-64.c:739 +#, fuzzy, c-format +msgid "%s: %s' accessed both as normal and thread local symbol" +msgstr "%s:%s'birabonetse Byombi Nka Bisanzwe Na Urudodo IKIMENYETSO" + +#: elf.c:372 +#, fuzzy, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "%s:Sibyo Ikurikiranyanyuguti Nta- boneza kugirango Icyiciro" + +#: elf.c:624 +#, fuzzy, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s:Sibyo Icyinjijwe" + +#: elf.c:695 +#, fuzzy, c-format +msgid "%s: no group info for section %s" +msgstr "%s:Oya Itsinda Ibisobanuro kugirango Icyiciro" + +#: elf.c:1055 +msgid "" +"\n" +"Program Header:\n" +msgstr "" + +#: elf.c:1106 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" + +#: elf.c:1235 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" + +#: elf.c:1258 +msgid "" +"\n" +"Version References:\n" +msgstr "" + +#: elf.c:1263 +#, fuzzy, c-format +msgid " required from %s:\n" +msgstr "Bya ngombwa Bivuye" + +#: elf.c:1944 +#, fuzzy, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "%s:Sibyo Ihuza kugirango Icyiciro Umubarendanga" + +#: elf.c:3686 +#, fuzzy, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s:kugirango Porogaramu Imitwe" + +#: elf.c:3791 +#, fuzzy, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s:kugirango Porogaramu Imitwe Impuza Na:" + +#: elf.c:3922 +#, fuzzy, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "Icyiciro in ku i ku" + +#: elf.c:4242 +#, fuzzy, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s:Iburira Icyiciro OYA in" + +#: elf.c:4566 +#, fuzzy, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s:IKIMENYETSO Bya ngombwa OYA" + +#: elf.c:4854 +#, fuzzy, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s:Iburira ni iyi" + +#: elf.c:5485 +#, fuzzy, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Kuri Gushaka Ibisohoka Icyiciro kugirango IKIMENYETSO Bivuye Icyiciro" + +#: elf.c:6298 +#, fuzzy, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s:Ubwoko" + +#: elfcode.h:1113 +#, fuzzy, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s:Verisiyo IBARA OYA BIHUYE IKIMENYETSO IBARA" + +#: elfcode.h:1342 +#, fuzzy, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s):Sibyo IKIMENYETSO Umubarendanga" + +#: elflink.c:1456 +#, fuzzy, c-format +msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s:Iburira Bya BUZIGUYE IKIMENYETSO" + +#: elflink.c:1807 +#, fuzzy, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s:kidasobanuye IKIMENYETSO Izina:" + +#: elflink.c:2142 +#, fuzzy, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "%s:Ingano in Icyiciro" + +#: elflink.c:2434 +#, fuzzy, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "Iburira Ubwoko Na Ingano Bya IKIMENYETSO OYA" + +#: elflink.h:1022 +#, fuzzy, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s:%s:Sibyo Verisiyo KININI" + +#: elflink.h:1063 +#, fuzzy, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s:%s:Sibyo Verisiyo" + +#: elflink.h:1238 +#, fuzzy, c-format +msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s" +msgstr "Itunganya Bya IKIMENYETSO in ni Gitoya in" + +#: elflink.h:1252 +#, fuzzy, c-format +msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s" +msgstr "Ingano Bya IKIMENYETSO Byahinduwe Bivuye in Kuri in" + +#: elflink.h:2160 +#, fuzzy, c-format +msgid "%s: undefined version: %s" +msgstr "%s:kidasobanuye Verisiyo" + +#: elflink.h:2226 +#, fuzzy, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "" +"%s:.Project- Id- Version: basctl\n" +"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n" +"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n" +"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n" +"Content- Type: text/ plain; charset= UTF- 8\n" +"Content- Transfer- Encoding: 8bit\n" +"X- Generator: KBabel 1. 0\n" +"." + +#: elflink.h:3078 +#, fuzzy +msgid "Not enough memory to sort relocations" +msgstr "Ububiko Kuri Ishungura" + +#: elflink.h:3958 elflink.h:4001 +#, fuzzy, c-format +msgid "%s: could not find output section %s" +msgstr "%s:OYA Gushaka Ibisohoka Icyiciro" + +#: elflink.h:3964 +#, fuzzy, c-format +msgid "warning: %s section has zero size" +msgstr "Iburira Icyiciro Zeru Ingano" + +#: elflink.h:4483 +#, fuzzy, c-format +msgid "%s: %s symbol `%s' in %s is referenced by DSO" +msgstr "%s:%sIKIMENYETSO in ni ku" + +#: elflink.h:4564 +#, fuzzy, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%s:OYA Gushaka Ibisohoka Icyiciro kugirango Iyinjiza Icyiciro" + +#: elflink.h:4666 +#, fuzzy, c-format +msgid "%s: %s symbol `%s' isn't defined" +msgstr "%s:%sIKIMENYETSO si" + +#: elflink.h:5053 elflink.h:5095 +#, fuzzy +msgid "%T: discarded in section `%s' from %s\n" +msgstr "%T:in Icyiciro Bivuye" + +#: elfxx-mips.c:887 +#, fuzzy +msgid "static procedure (no name)" +msgstr "Oya Izina:" + +#: elfxx-mips.c:1897 +#, fuzzy +msgid "not enough GOT space for local GOT entries" +msgstr "OYA Umwanya kugirango Ibyinjijwe" + +#: elfxx-mips.c:3691 +#, fuzzy, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "%s:%s+0x%lx:Simbuka Kuri ni OYA" + +#: elfxx-mips.c:5192 +#, fuzzy, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s:kugirango Icyiciro" + +#: elfxx-mips.c:5266 +#, fuzzy, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s:ku OYA IKIMENYETSO" + +#: elfxx-mips.c:8693 +#, fuzzy, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s:Icyiciro Izina:" + +#: elfxx-mips.c:9027 +#, fuzzy, c-format +msgid "%s: endianness incompatible with that of the selected emulation" +msgstr "%s:Na: Bya i Byahiswemo" + +#: elfxx-mips.c:9039 +#, fuzzy, c-format +msgid "%s: ABI is incompatible with that of the selected emulation" +msgstr "%s:ni Na: Bya i Byahiswemo" + +#: elfxx-mips.c:9106 +#, fuzzy, c-format +msgid "%s: warning: linking PIC files with non-PIC files" +msgstr "%s:Iburira Impuza Idosiye Na: Idosiye" + +#: elfxx-mips.c:9123 +#, fuzzy, c-format +msgid "%s: linking 32-bit code with 64-bit code" +msgstr "%s:Impuza ITEGEKONGENGA Na: ITEGEKONGENGA" + +#: elfxx-mips.c:9151 +#, fuzzy, c-format +msgid "%s: linking %s module with previous %s modules" +msgstr "%s:Impuza Modire Na: Ibanjirije Modire" + +#: elfxx-mips.c:9174 +#, fuzzy, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s:Impuza Modire Na: Ibanjirije Modire" + +#: elfxx-mips.c:9243 +msgid " [abi=O32]" +msgstr "" + +#: elfxx-mips.c:9245 +msgid " [abi=O64]" +msgstr "" + +#: elfxx-mips.c:9247 +msgid " [abi=EABI32]" +msgstr "" + +#: elfxx-mips.c:9249 +msgid " [abi=EABI64]" +msgstr "" + +#: elfxx-mips.c:9251 +#, fuzzy +msgid " [abi unknown]" +msgstr "[Kitazwi" + +#: elfxx-mips.c:9253 +msgid " [abi=N32]" +msgstr "" + +#: elfxx-mips.c:9255 +msgid " [abi=64]" +msgstr "" + +#: elfxx-mips.c:9257 +#, fuzzy +msgid " [no abi set]" +msgstr "[Oya Gushyiraho" + +#: elfxx-mips.c:9260 +msgid " [mips1]" +msgstr "" + +#: elfxx-mips.c:9262 +msgid " [mips2]" +msgstr "" + +#: elfxx-mips.c:9264 +msgid " [mips3]" +msgstr "" + +#: elfxx-mips.c:9266 +msgid " [mips4]" +msgstr "" + +#: elfxx-mips.c:9268 +msgid " [mips5]" +msgstr "" + +#: elfxx-mips.c:9270 +msgid " [mips32]" +msgstr "" + +#: elfxx-mips.c:9272 +msgid " [mips64]" +msgstr "" + +#: elfxx-mips.c:9274 +msgid " [mips32r2]" +msgstr "" + +#: elfxx-mips.c:9276 +#, fuzzy +msgid " [unknown ISA]" +msgstr "[Kitazwi" + +#: elfxx-mips.c:9279 +msgid " [mdmx]" +msgstr "" + +#: elfxx-mips.c:9282 +msgid " [mips16]" +msgstr "" + +#: elfxx-mips.c:9285 +msgid " [32bitmode]" +msgstr "" + +#: elfxx-mips.c:9287 +#, fuzzy +msgid " [not 32bitmode]" +msgstr "[OYA" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, fuzzy, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "IDOSIYE Isomero" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, fuzzy, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "IDOSIYE Isomero" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, fuzzy, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "OYA kugirango" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +#, fuzzy +msgid "Warning: fixup count mismatch\n" +msgstr "IBARA" + +#: ieee.c:293 +#, fuzzy, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s:Ikurikiranyanyuguti KININI" + +#: ieee.c:428 +#, fuzzy, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s:IKIMENYETSO Amabendera" + +#: ieee.c:938 +#, fuzzy, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "%s:Icyabitswe kugirango IKIMENYETSO" + +#: ieee.c:963 +#, fuzzy, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "%s:Ubwoko in external" + +#: ieee.c:985 +#, fuzzy, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s:Ubwoko Nyuma" + +#: ihex.c:264 +#, fuzzy, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s:%d:Inyuguti in" + +#: ihex.c:372 +#, fuzzy, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s:%u:in IDOSIYE Ikitezwe: Byabonetse" + +#: ihex.c:426 +#, fuzzy, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "%s:%u:Byongerewe... Aderesi Icyabitswe Uburebure in IDOSIYE" + +#: ihex.c:443 +#, fuzzy, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "%s:%u:Byongerewe... Gutangira Aderesi Uburebure in IDOSIYE" + +#: ihex.c:460 +#, fuzzy, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s:%u:Byongerewe... By'umurongo Aderesi Icyabitswe Uburebure in IDOSIYE" + +#: ihex.c:477 +#, fuzzy, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s:%u:Byongerewe... By'umurongo Gutangira Aderesi Uburebure in IDOSIYE" + +#: ihex.c:494 +#, fuzzy, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "%s:%u:Ubwoko in" + +#: ihex.c:619 +#, fuzzy, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "%s:By'imbere Ikosa in" + +#: ihex.c:654 +#, fuzzy, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "%s:Icyiciro Uburebure in" + +#: ihex.c:872 +#, fuzzy, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s:Aderesi Inyuma Bya Urutonde kugirango IDOSIYE" + +#: libbfd.c:861 +#, fuzzy, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "ku Umurongo in" + +#: libbfd.c:864 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1829 +#, fuzzy, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "%s:BUZIGUYE IKIMENYETSO Kuri ni a" + +#: linker.c:2697 +#, fuzzy, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Kuri Ihuza Na: Iyinjiza Na Ibisohoka" + +#: merge.c:896 +#, fuzzy, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "%s:Impera Bya Icyiciro" + +#: mmo.c:503 +#, fuzzy, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s:Kuri Icyiciro Izina:" + +#: mmo.c:579 +#, fuzzy, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s:Kuri a IKIMENYETSO Bayite" + +#: mmo.c:1287 +#, fuzzy, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s:Sibyo IDOSIYE Agaciro kugirango ni OYA" + +#: mmo.c:1433 +#, fuzzy, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s:Inyuguti Nyuma IKIMENYETSO Izina: Na:" + +#: mmo.c:1674 +#, fuzzy, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s:Sibyo IDOSIYE" + +#: mmo.c:1684 +#, fuzzy, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s:Sibyo IDOSIYE Ikitezwe: 1. kugirango" + +#: mmo.c:1720 +#, fuzzy, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z 1. Cyangwa Z 2. Z kugirango" + +#: mmo.c:1766 +#, fuzzy, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z 1. Cyangwa Z 2. Z kugirango" + +#: mmo.c:1805 +#, fuzzy, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s:Sibyo IDOSIYE Ikitezwe: Y 0 Y kugirango" + +#: mmo.c:1814 +#, fuzzy, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z Cyangwa Z Z kugirango" + +#: mmo.c:1837 +#, fuzzy, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s:Sibyo IDOSIYE Nyobora Bayite Bya ijambo 0 Cyangwa 1. kugirango" + +#: mmo.c:1860 +#, fuzzy, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s:IDOSIYE Izina: kugirango IDOSIYE Umubare" + +#: mmo.c:1880 +#, fuzzy, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s:Sibyo IDOSIYE IDOSIYE Umubare Nka" + +#: mmo.c:1893 +#, fuzzy, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s:Sibyo IDOSIYE IDOSIYE Izina: kugirango Umubare OYA Mbere" + +#: mmo.c:1999 +#, fuzzy, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s:Sibyo IDOSIYE Imyanya Y Na Z Bya Zeru Y Z" + +#: mmo.c:2035 +#, fuzzy, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s:Sibyo IDOSIYE OYA Iheruka Ikintu in" + +#: mmo.c:2048 +#, fuzzy, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s:Sibyo IDOSIYE Bya OYA bingana Kuri i Umubare Bya Kuri i" + +#: mmo.c:2698 +#, fuzzy, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s:Sibyo IKIMENYETSO imbonerahamwe# Gusubiramo IKIMENYETSO" + +#: mmo.c:2949 +#, fuzzy, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s:IKIMENYETSO Insobanuro Gushyiraho Kuri i Gutangira Aderesi" + +#: mmo.c:3039 +#, fuzzy, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s:Iburira IKIMENYETSO imbonerahamwe# Binini kugirango Kinini Amagambo" + +#: mmo.c:3084 +#, fuzzy, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s:By'imbere Ikosa IKIMENYETSO imbonerahamwe# Byahinduwe Ingano Bivuye Kuri" + +#: mmo.c:3139 +#, fuzzy, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s:By'imbere Ikosa By'imbere Kwiyandikisha Icyiciro" + +#: mmo.c:3191 +#, fuzzy, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s:Oya Icyiciro Uburebure" + +#: mmo.c:3197 +#, fuzzy, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s:Icyiciro Uburebure" + +#: mmo.c:3202 +#, fuzzy, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s:Sibyo Gutangira Aderesi kugirango Bya Uburebure" + +#: oasys.c:1052 +#, fuzzy, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s:OYA Icyiciro in" + +#: osf-core.c:137 +#, fuzzy, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "1. IDOSIYE Icyiciro Ubwoko" + +#. XXX code yet to be written. +#: peicode.h:787 +#, fuzzy, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s:Kuzana Ubwoko" + +#: peicode.h:792 +#, fuzzy, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s:Kuzana Ubwoko" + +#: peicode.h:806 +#, fuzzy, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s:Kuzana Izina: Ubwoko" + +#: peicode.h:1164 +#, fuzzy, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s:Ubwoko in" + +#: peicode.h:1176 +#, fuzzy, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s:Ubwoko in" + +#: peicode.h:1193 +#, fuzzy, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "%s:Ingano Umwanya ni Zeru in Umutwempangano" + +#: peicode.h:1224 +#, fuzzy, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "%s:Ikurikiranyanyuguti OYA NTAGIHARI in Igikoresho IDOSIYE" + +#: pe-mips.c:659 +#, fuzzy, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s:`OYA Na:" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:795 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "" + +#: pe-mips.c:821 +#, fuzzy, c-format +msgid "%s: jump too far away\n" +msgstr "%s:Simbuka" + +#: pe-mips.c:848 +#, fuzzy, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "%s:Nyuma" + +#: ppcboot.c:416 +#, fuzzy +msgid "" +"\n" +"ppcboot header:\n" +msgstr "Umutwempangano" + +#: ppcboot.c:417 +#, fuzzy, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Nta- boneza" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:421 +#, fuzzy, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Umwanya" + +#: ppcboot.c:427 +#, fuzzy, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Izina:" + +#: ppcboot.c:446 +#, fuzzy, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Gutangira" + +#: ppcboot.c:452 +#, fuzzy, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Impera" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:459 +#, fuzzy, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Uburebure" + +#: som.c:5422 +msgid "som_sizeof_headers unimplemented" +msgstr "" + +#: srec.c:302 +#, fuzzy, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d:Inyuguti in Icyabitswe" + +#: stabs.c:319 +#, fuzzy, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "%s(%s+0x%lx):Icyinjijwe Sibyo Ikurikiranyanyuguti Umubarendanga" + +#: syms.c:1019 +msgid "Unsupported .stab relocation" +msgstr "" + +#: vms-gsd.c:356 +#, fuzzy, c-format +msgid "bfd_make_section (%s) failed" +msgstr "Byanze" + +#: vms-gsd.c:371 +#, fuzzy, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "Byanze" + +#: vms-gsd.c:407 +#, fuzzy, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Icyiciro" + +#: vms-gsd.c:704 +#, fuzzy, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "Kitazwi" + +#: vms-hdr.c:408 +#, fuzzy +msgid "Object module NOT error-free !\n" +msgstr "Modire Ikosa Kigenga" + +#: vms-misc.c:541 +#, fuzzy, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Byarenze urugero in" + +#: vms-misc.c:559 +#, fuzzy +msgid "Stack underflow in _bfd_vms_pop" +msgstr "in" + +#: vms-misc.c:918 +#, fuzzy +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "Na: Zeru Bayite" + +#: vms-misc.c:923 +#, fuzzy +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "Na: Bayite" + +#: vms-misc.c:1054 +#, fuzzy, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "ku" + +#: vms-misc.c:1117 +#, fuzzy, c-format +msgid "failed to enter %s" +msgstr "Byanze Kuri Injiza" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "" + +#: vms-tir.c:383 +#, fuzzy, c-format +msgid "bad section index in %s" +msgstr "Icyiciro Umubarendanga in" + +#: vms-tir.c:396 +#, fuzzy, c-format +msgid "unsupported STA cmd %s" +msgstr "Cmd+" + +#: vms-tir.c:401 vms-tir.c:1261 +#, fuzzy, c-format +msgid "reserved STA cmd %d" +msgstr "Cmd+" + +#: vms-tir.c:512 vms-tir.c:535 +#, fuzzy, c-format +msgid "%s: no symbol \"%s\"" +msgstr "%s:Oya IKIMENYETSO" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850 +#: vms-tir.c:859 vms-tir.c:1584 +#, fuzzy, c-format +msgid "%s: not supported" +msgstr "%s:OYA" + +#: vms-tir.c:607 vms-tir.c:1439 +#, fuzzy, c-format +msgid "%s: not implemented" +msgstr "%s:OYA" + +#: vms-tir.c:611 vms-tir.c:1443 +#, fuzzy, c-format +msgid "reserved STO cmd %d" +msgstr "Cmd+" + +#: vms-tir.c:729 vms-tir.c:1589 +#, fuzzy, c-format +msgid "reserved OPR cmd %d" +msgstr "Cmd+" + +#: vms-tir.c:797 vms-tir.c:1653 +#, fuzzy, c-format +msgid "reserved CTL cmd %d" +msgstr "Cmd+" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1169 +#, fuzzy +msgid "stack-from-image not implemented" +msgstr "Bivuye Ishusho OYA" + +#: vms-tir.c:1187 +#, fuzzy +msgid "stack-entry-mask not fully implemented" +msgstr "Icyinjijwe OYA" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1201 +#, fuzzy +msgid "PASSMECH not fully implemented" +msgstr "OYA" + +#: vms-tir.c:1220 +#, fuzzy +msgid "stack-local-symbol not fully implemented" +msgstr "IKIMENYETSO OYA" + +#: vms-tir.c:1233 +#, fuzzy +msgid "stack-literal not fully implemented" +msgstr "OYA" + +#: vms-tir.c:1254 +#, fuzzy +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "IKIMENYETSO Icyinjijwe Akadomo OYA" + +#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632 +#: vms-tir.c:1640 vms-tir.c:1648 +#, fuzzy, c-format +msgid "%s: not fully implemented" +msgstr "%s:OYA" + +#: vms-tir.c:1705 +#, fuzzy, c-format +msgid "obj code %d not found" +msgstr "ITEGEKONGENGA OYA Byabonetse" + +#: vms-tir.c:2043 +#, fuzzy, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "Na: Oya in Icyiciro" + +#: vms-tir.c:2331 +#, c-format +msgid "Unhandled relocation %s" +msgstr "" + +#: xcofflink.c:1244 +#, fuzzy, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "%s:`%s'Umurongo Imibare Oya Icyiciro" + +#: xcofflink.c:1297 +#, fuzzy, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "%s:ishuri IKIMENYETSO Oya Ibyinjijwe" + +#: xcofflink.c:1320 +#, fuzzy, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "%s:IKIMENYETSO Ubwoko" + +#: xcofflink.c:1332 +#, fuzzy, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s:IKIMENYETSO ishuri" + +#: xcofflink.c:1368 +#, fuzzy, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s:IKIMENYETSO ni ishuri" + +#: xcofflink.c:1520 +#, fuzzy, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "%s:OYA in Icyiciro" + +#: xcofflink.c:1627 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "" + +#: xcofflink.c:1958 +#, fuzzy, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "%s:OYA in" + +#: xcofflink.c:2095 +#, fuzzy, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s:Igikoresho Ryari: OYA Ibisohoka" + +#: xcofflink.c:2116 +#, fuzzy, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s:Igikoresho Na: Oya Icyiciro" + +#: xcofflink.c:2761 +#, fuzzy, c-format +msgid "%s: no such symbol" +msgstr "%s:Oya IKIMENYETSO" + +#: xcofflink.c:2894 +#, fuzzy +msgid "error: undefined symbol __rtinit" +msgstr "Ikosa kidasobanuye IKIMENYETSO" + +#: xcofflink.c:3455 +#, fuzzy, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "Iburira Kuri Kohereza kidasobanuye IKIMENYETSO" + +#: xcofflink.c:4448 +#, fuzzy, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "Byarenze urugero Ryari:" + +#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119 +#, fuzzy, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "%s:in Icyiciro" + +#: xcofflink.c:5310 xcofflink.c:6130 +#, fuzzy, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "%s:`%s'in OYA" + +#: xcofflink.c:5325 +#, fuzzy, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "%s:in Gusoma Icyiciro" + +#: elf32-ia64.c:2271 elf64-ia64.c:2271 +#, fuzzy +msgid "@pltoff reloc against local symbol" +msgstr "@IKIMENYETSO" + +#: elf32-ia64.c:3663 elf64-ia64.c:3663 +#, fuzzy, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s:Ibyatanzwe" + +#: elf32-ia64.c:3674 elf64-ia64.c:3674 +#, fuzzy, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s:_OYA Ibyatanzwe" + +#: elf32-ia64.c:3986 elf64-ia64.c:3986 +#, fuzzy, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "%s:Impuza ITEGEKONGENGA in a Isomero" + +#: elf32-ia64.c:4017 elf64-ia64.c:4017 +#, fuzzy, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "%s:@IKIMENYETSO" + +#: elf32-ia64.c:4077 elf64-ia64.c:4077 +#, fuzzy, c-format +msgid "%s: linking non-pic code in a position independent executable" +msgstr "%s:Impuza ITEGEKONGENGA in a Ibirindiro" + +#: elf32-ia64.c:4214 elf64-ia64.c:4214 +#, fuzzy, c-format +msgid "%s: @internal branch to dynamic symbol %s" +msgstr "%s:@By'imbere Kuri IKIMENYETSO" + +#: elf32-ia64.c:4216 elf64-ia64.c:4216 +#, fuzzy, c-format +msgid "%s: speculation fixup to dynamic symbol %s" +msgstr "%s:Kuri IKIMENYETSO" + +#: elf32-ia64.c:4218 elf64-ia64.c:4218 +#, fuzzy, c-format +msgid "%s: @pcrel relocation against dynamic symbol %s" +msgstr "%s:@IKIMENYETSO" + +#: elf32-ia64.c:4430 elf64-ia64.c:4430 +msgid "unsupported reloc" +msgstr "" + +#: elf32-ia64.c:4709 elf64-ia64.c:4709 +#, fuzzy, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%s:Impuza ku Na: Idosiye" + +#: elf32-ia64.c:4718 elf64-ia64.c:4718 +#, fuzzy, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s:Impuza Idosiye Na: Idosiye" + +#: elf32-ia64.c:4727 elf64-ia64.c:4727 +#, fuzzy, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s:Impuza Idosiye Na: Idosiye" + +#: elf32-ia64.c:4736 elf64-ia64.c:4736 +#, fuzzy, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "%s:Impuza Idosiye Na: Idosiye" + +#: elf32-ia64.c:4746 elf64-ia64.c:4746 +#, fuzzy, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "%s:Impuza Ikiyega Idosiye Na: Ikiyega Idosiye" + +#: peigen.c:985 pepigen.c:985 +#, fuzzy, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s:Umurongo Umubare Byarenze urugero" + +#: peigen.c:1002 pepigen.c:1002 +#, fuzzy, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "%s:Byarenze urugero 1." + +#: peigen.c:1016 pepigen.c:1016 +#, fuzzy +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Cyangwa Twebwe Byabonetse" + +#: peigen.c:1017 pepigen.c:1017 +#, fuzzy +msgid "Import Directory [parts of .idata]" +msgstr "Bya" + +#: peigen.c:1018 pepigen.c:1018 +msgid "Resource Directory [.rsrc]" +msgstr "" + +#: peigen.c:1019 pepigen.c:1019 +msgid "Exception Directory [.pdata]" +msgstr "" + +#: peigen.c:1020 pepigen.c:1020 +msgid "Security Directory" +msgstr "" + +#: peigen.c:1021 pepigen.c:1021 +#, fuzzy +msgid "Base Relocation Directory [.reloc]" +msgstr "Base" + +#: peigen.c:1022 pepigen.c:1022 +msgid "Debug Directory" +msgstr "" + +#: peigen.c:1023 pepigen.c:1023 +msgid "Description Directory" +msgstr "" + +#: peigen.c:1024 pepigen.c:1024 +msgid "Special Directory" +msgstr "" + +#: peigen.c:1025 pepigen.c:1025 +#, fuzzy +msgid "Thread Storage Directory [.tls]" +msgstr "TLS" + +#: peigen.c:1026 pepigen.c:1026 +msgid "Load Configuration Directory" +msgstr "" + +#: peigen.c:1027 pepigen.c:1027 +msgid "Bound Import Directory" +msgstr "" + +#: peigen.c:1028 pepigen.c:1028 +msgid "Import Address Table Directory" +msgstr "" + +#: peigen.c:1029 pepigen.c:1029 +msgid "Delay Import Directory" +msgstr "" + +#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031 +msgid "Reserved" +msgstr "" + +#: peigen.c:1094 pepigen.c:1094 +#, fuzzy +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "ni Kuzana imbonerahamwe# i Icyiciro OYA" + +#: peigen.c:1099 pepigen.c:1099 +#, fuzzy, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "ni Kuzana imbonerahamwe# in ku" + +#: peigen.c:1136 pepigen.c:1136 +#, fuzzy, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "ku i Gutangira Aderesi" + +#: peigen.c:1139 pepigen.c:1139 +#, fuzzy, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "ITEGEKONGENGA SHINGIRO" + +#: peigen.c:1145 pepigen.c:1145 +#, fuzzy +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "Icyiciro OYA" + +#: peigen.c:1150 pepigen.c:1150 +#, fuzzy, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "Icyiciro Ibigize" + +#: peigen.c:1153 pepigen.c:1153 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" + +#: peigen.c:1204 pepigen.c:1204 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" + +#: peigen.c:1215 pepigen.c:1215 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "" + +#: peigen.c:1240 pepigen.c:1240 +#, fuzzy +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "ni a Itangira i Icyiciro OYA" + +#: peigen.c:1380 pepigen.c:1380 +#, fuzzy +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "ni Kohereza imbonerahamwe# i Icyiciro OYA" + +#: peigen.c:1385 pepigen.c:1385 +#, fuzzy, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "ni Kohereza imbonerahamwe# in ku" + +#: peigen.c:1416 pepigen.c:1416 +#, fuzzy, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "Icyiciro Ibigize" + +#: peigen.c:1420 pepigen.c:1420 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "" + +#: peigen.c:1423 pepigen.c:1423 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "" + +#: peigen.c:1426 pepigen.c:1426 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "" + +#: peigen.c:1429 pepigen.c:1429 +#, fuzzy +msgid "Name \t\t\t\t" +msgstr "Izina" + +#: peigen.c:1435 pepigen.c:1435 +#, fuzzy, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Base" + +#: peigen.c:1438 pepigen.c:1438 +#, fuzzy +msgid "Number in:\n" +msgstr "in" + +#: peigen.c:1441 pepigen.c:1441 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "" + +#: peigen.c:1448 pepigen.c:1448 +msgid "Table Addresses\n" +msgstr "" + +#: peigen.c:1451 pepigen.c:1451 +msgid "\tExport Address Table \t\t" +msgstr "" + +#: peigen.c:1456 pepigen.c:1456 +msgid "\tName Pointer Table \t\t" +msgstr "" + +#: peigen.c:1461 pepigen.c:1461 +msgid "\tOrdinal Table \t\t\t" +msgstr "" + +#: peigen.c:1476 pepigen.c:1476 +#, fuzzy, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "Base" + +#: peigen.c:1495 pepigen.c:1495 +msgid "Forwarder RVA" +msgstr "" + +#: peigen.c:1506 pepigen.c:1506 +msgid "Export RVA" +msgstr "" + +#: peigen.c:1513 pepigen.c:1513 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" + +#: peigen.c:1568 pepigen.c:1568 +#, fuzzy, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Icyiciro Ingano ni OYA a Igikubo Bya" + +#: peigen.c:1572 pepigen.c:1572 +#, fuzzy +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "Icyiciro Ibigize" + +#: peigen.c:1575 pepigen.c:1575 +#, fuzzy +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "Impera" + +#: peigen.c:1577 pepigen.c:1577 +#, fuzzy +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "Impera" + +#: peigen.c:1647 pepigen.c:1647 +#, fuzzy +msgid " Register save millicode" +msgstr "Kubika" + +#: peigen.c:1650 pepigen.c:1650 +#, fuzzy +msgid " Register restore millicode" +msgstr "Kugarura" + +#: peigen.c:1653 pepigen.c:1653 +#, fuzzy +msgid " Glue code sequence" +msgstr "ITEGEKONGENGA" + +#: peigen.c:1705 pepigen.c:1705 +#, fuzzy +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "Idosiye Base Icyiciro Ibigize" + +#: peigen.c:1735 pepigen.c:1735 +#, fuzzy, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "Ingano Bya" + +#: peigen.c:1748 pepigen.c:1748 +#, fuzzy, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "Nta- boneza" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. 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z*n-m*W~{*#nE`X(Qn{`R4>F%H3OCy)tb@(|X;bbKnd`I@7h5m4nYsWM&D)EM-g+Dh zbH5p*anWzDD5L4P=x5gWa`xj6$#)SuJeax57?In5@KzPWKPV*3l$({e>qS_Qp9o?@7;wDtda%FYik z`EOw__^e?O5s)2&rMY5eED9HHg>ID_!qOE*pBS_4%l1js%+#D+YUtO)y6L%`L!9e| zeyCZHPa7pE$4Z80Nyw8DO~&UiN7bpTb$w{&uCqcK1`>!jJ*HQJW(6j+9@&{pJD|^W zq{hfip5hUQ&MZV~ZHr=+c3df$Kv@#aHA_vk1g6DG=aZD*q}8+lY1niEL~vKFLh, 2001, 2002, 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:53+0930\n" +"PO-Revision-Date: 2003-08-14 22:40+0200\n" +"Last-Translator: Christian Rose \n" +"Language-Team: Swedish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:204 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s: Okänd sektionstyp i a.out.adobe-fil: %x\n" + +#: aout-cris.c:207 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Ogiltig omlokaliseringstyp exporterad: %d" + +#: aout-cris.c:251 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s: Ogiltig omlokaliseringstyp importerad: %d" + +#: aout-cris.c:262 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s: Felaktig omlokaliseringstyp importerad: %d" + +#: aoutx.h:1295 aoutx.h:1716 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: kan inte representera sektionen \"%s\" i a.out-objektfilformat" + +#: aoutx.h:1682 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: kan inte representera sektion för symbolen \"%s\" i a.out-objektfilformat" + +#: aoutx.h:1684 +msgid "*unknown*" +msgstr "*okänd*" + +#: aoutx.h:3776 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: omlokaliseringsbar länk från %s till %s stöds inte" + +#: archive.c:1751 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Varning: arkivskrivning var långsam: skriver om tidsstämpel\n" + +#: archive.c:2014 +msgid "Reading archive file mod timestamp" +msgstr "Läser arkivfilens modifieringstidsstämpel" + +#: archive.c:2040 +msgid "Writing updated armap timestamp" +msgstr "Skriver uppdaterad armap-tidsstämpel" + +#: bfd.c:280 +msgid "No error" +msgstr "Inget fel" + +#: bfd.c:281 +msgid "System call error" +msgstr "Systemanropsfel" + +#: bfd.c:282 +msgid "Invalid bfd target" +msgstr "Ogiltigt bfd-mål" + +#: bfd.c:283 +msgid "File in wrong format" +msgstr "Filen är i fel format" + +#: bfd.c:284 +msgid "Archive object file in wrong format" +msgstr "Arkivobjektfil är i fel format" + +#: bfd.c:285 +msgid "Invalid operation" +msgstr "Ogiltig åtgärd" + +#: bfd.c:286 +msgid "Memory exhausted" +msgstr "Minnet är slut" + +#: bfd.c:287 +msgid "No symbols" +msgstr "Inga symboler" + +#: bfd.c:288 +msgid "Archive has no index; run ranlib to add one" +msgstr "Arkivet har inget index; kör ranlib för att lägga till ett" + +#: bfd.c:289 +msgid "No more archived files" +msgstr "Inga fler arkiverade filer" + +#: bfd.c:290 +msgid "Malformed archive" +msgstr "Trasigt arkiv" + +#: bfd.c:291 +msgid "File format not recognized" +msgstr "Filformatet känns inte igen" + +#: bfd.c:292 +msgid "File format is ambiguous" +msgstr "Filformatet är tvetydigt" + +#: bfd.c:293 +msgid "Section has no contents" +msgstr "Sektionen har inget innehåll" + +#: bfd.c:294 +msgid "Nonrepresentable section on output" +msgstr "Ickerepresenterbar sektion i utdata" + +#: bfd.c:295 +msgid "Symbol needs debug section which does not exist" +msgstr "Symbolen kräver felsökningssektion som inte finns" + +#: bfd.c:296 +msgid "Bad value" +msgstr "Felaktigt värde" + +#: bfd.c:297 +msgid "File truncated" +msgstr "Filen trunkerad" + +#: bfd.c:298 +msgid "File too big" +msgstr "Filen är för stor" + +#: bfd.c:299 +msgid "#" +msgstr "#" + +#: bfd.c:687 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s-försäkran misslyckades %s:%d" + +#: bfd.c:703 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "Internt BFD %s-fel, avbryter vid %s rad %d i %s\n" + +#: bfd.c:707 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "Internt BFD %s-fel, avbryter vid %s rad %d\n" + +#: bfd.c:709 +msgid "Please report this bug.\n" +msgstr "Rapportera gärna detta fel.\n" + +#: bfdwin.c:202 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "mappar inte: data=%lx mappat=%d\n" + +#: bfdwin.c:205 +msgid "not mapping: env var not set\n" +msgstr "mappar inte: miljövariabel är inte satt\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Varning: Skrivning av sektionen \"%s\" till enormt (dvs negativt) avlägsen byte 0x%lx." + +# src/menus.c:341 +#: coff-a29k.c:120 +msgid "Missing IHCONST" +msgstr "IHCONST saknas" + +# src/menus.c:341 +#: coff-a29k.c:181 +msgid "Missing IHIHALF" +msgstr "IHIHALF saknas" + +#: coff-a29k.c:213 coff-or32.c:236 +msgid "Unrecognized reloc" +msgstr "Okänd omlokalisering" + +#: coff-a29k.c:409 +msgid "missing IHCONST reloc" +msgstr "IHCONST-omlokalisering saknas" + +#: coff-a29k.c:499 +msgid "missing IHIHALF reloc" +msgstr "IHIHALF-omlokalisering saknas" + +#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397 +msgid "GP relative relocation used when GP not defined" +msgstr "GP-relativ omlokalisering användes då GP inte är definierad" + +#: coff-alpha.c:1488 +msgid "using multiple gp values" +msgstr "använder flera gp-värden" + +#: coff-arm.c:1066 elf32-arm.h:294 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "%s: kunde inte hitta THUMB-klistret \"%s\" till \"%s\"" + +#: coff-arm.c:1096 elf32-arm.h:329 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "%s: kunde inte hitta ARM-klistret \"%s\" till \"%s\"" + +#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "%s(%s): varning: samverkande är inte aktiverat." + +#: coff-arm.c:1398 elf32-arm.h:1002 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr " första förekomst: %s: arm-anrop till thumb" + +#: coff-arm.c:1493 elf32-arm.h:895 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr " första förekomst: %s: thumb-anrop till arm" + +#: coff-arm.c:1496 +msgid " consider relinking with --support-old-code enabled" +msgstr " överväg omlänkning med --support-old-code aktiverat" + +#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "%s: felaktig omlokaliseringsadress 0x%lx i sektionen \"%s\"" + +#: coff-arm.c:2132 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s: otillåtet symbolindex i omlokalisering: %d" + +#: coff-arm.c:2265 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "FEL: %s kompilerad för APCS-%d, medan %s är kompilerad för APCS-%d" + +#: coff-arm.c:2280 elf32-arm.h:2328 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "FEL: %s skickar flyttal i flyttalsregister, medan %s skickar dem i heltalsregister" + +#: coff-arm.c:2283 elf32-arm.h:2333 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "FEL: %s skickar flyttal i heltalsregister, medan %s skickar dem i flyttalsregister" + +#: coff-arm.c:2298 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "FEL: %s är kompilerad som positionsoberoende kod, medan målet %s har absolut position" + +#: coff-arm.c:2301 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "FEL: %s är kompilerad som kod med absolut position, medan målet %s är positionsoberoende" + +#: coff-arm.c:2330 elf32-arm.h:2405 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "Varning: %s stöder samverkande, medan %s däremot inte gör det" + +#: coff-arm.c:2333 elf32-arm.h:2412 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "Varning: %s stöder inte samverkande, medan %s däremot gör det" + +#: coff-arm.c:2360 +#, c-format +msgid "private flags = %x:" +msgstr "privata flaggor = %x:" + +#: coff-arm.c:2368 elf32-arm.h:2467 +msgid " [floats passed in float registers]" +msgstr " [flyttal skickade i flyttalsregister]" + +#: coff-arm.c:2370 +msgid " [floats passed in integer registers]" +msgstr " [flyttal skickade i heltalsregister]" + +#: coff-arm.c:2373 elf32-arm.h:2470 +msgid " [position independent]" +msgstr " [positionsoberoende]" + +#: coff-arm.c:2375 +msgid " [absolute position]" +msgstr " [absolut position]" + +#: coff-arm.c:2379 +msgid " [interworking flag not initialised]" +msgstr " [samverkandeflagga är inte initierad]" + +#: coff-arm.c:2381 +msgid " [interworking supported]" +msgstr " [samverkan stöds]" + +#: coff-arm.c:2383 +msgid " [interworking not supported]" +msgstr " [samverkan stöds inte]" + +#: coff-arm.c:2431 elf32-arm.h:2150 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "Varning: Ställer inte in samverkansflaggan för %s eftersom den redan har angivits som inte samverkande" + +#: coff-arm.c:2435 elf32-arm.h:2154 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "Varning: Stänger av samverkansflaggan för %s på grund av begäran utifrån" + +#: coff-h8300.c:1096 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "kan inte hantera R_MEM_INDIRECT-omlokalisering vid användning av %s-utdata" + +#: coff-i960.c:137 coff-i960.c:486 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "osäker anropskonvention för icke-COFF-symbol" + +#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783 +msgid "unsupported reloc type" +msgstr "omlokaliseringstypen stöds inte" + +#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554 +msgid "GP relative relocation when _gp not defined" +msgstr "GP-relativ omlokalisering då _gp inte var definierat" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2431 +msgid "reloc against unsupported section" +msgstr "omlokalisering mot sektion som inte stöds" + +#: coff-mips.c:2439 +msgid "reloc not properly aligned" +msgstr "omlokalisering inte på jämn gräns" + +#: coff-rs6000.c:2790 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: omlokaliseringstypen 0x%02x stöds inte" + +#: coff-rs6000.c:2883 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: TOC-omlokalisering vid 0x%x till symbolen \"%s\" utan någon TOC-post" + +#: coff-rs6000.c:3616 coff64-rs6000.c:2109 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "%s: symbolen \"%s\" har okänd smclas %d" + +#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Okänd omlokaliseringstyp 0x%x" + +#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: varning: otillåtet symbolindex %ld i omlokaliseringarna" + +#: coff-w65.c:364 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "ignorerar omlokalisering %s\n" + +#: coffcode.h:1108 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s): Sektionsflaggan %s (0x%x) ignorerades" + +#: coffcode.h:2214 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Okänt TI COFF-målid \"0x%x\"" + +#: coffcode.h:4437 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s: varning: otillåtet symbolindex %ld i radnummer" + +#: coffcode.h:4451 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s: varning: dubbel radnummersinformation för \"%s\"" + +#: coffcode.h:4805 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%s: Okänd lagringsklass %d för %s-symbolen \"%s\"" + +#: coffcode.h:4938 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "varning: %s: lokala symbolen \"%s\" har ingen sektion" + +#: coffcode.h:5083 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%s: otillåten omlokaliseringstyp %d på adress 0x%lx" + +#: coffgen.c:1666 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s: felaktig strängtabellstorlek %lu" + +#: cofflink.c:538 elflink.h:1276 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "Varning: typen på symbolen \"%s\" ändrades från %d till %d i %s" + +#: cofflink.c:2328 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "%s: omlokaliseringar i sektionen \"%s\", men den har inget innehåll" + +#: cofflink.c:2671 coffswap.h:890 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: omlokalisering ger överspill: 0x%lx > 0xffff" + +#: cofflink.c:2680 coffswap.h:876 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: varning: %s: radnummer ger överspill: 0x%lx > 0xffff" + +#: cpu-arm.c:196 cpu-arm.c:206 +#, c-format +msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale" +msgstr "FEL: %s kompilerad för EP9312, medan %s är kompilerad för XScale" + +#: cpu-arm.c:344 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "varning: kan inte uppdatera innehållet i %s-sektion i %s" + +#: dwarf2.c:380 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Dwarf-fel: Kan inte hitta sektionen .debug_str." + +#: dwarf2.c:397 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "Dwarf-fel: DW_FORM_strp-avståndet (%lu) större än eller lika med storleken på .debug_str (%lu)." + +#: dwarf2.c:541 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Dwarf-fel: Kan inte hitta sektionen .debug_abbrev." + +#: dwarf2.c:556 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "Dwarf-fel: Förkortningsavståndet (%lu) större än eller lika med storleken .debug_abbrev (%lu)." + +#: dwarf2.c:756 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf-fel: Ogiltig eller ohanterat FORM-värde: %u." + +#: dwarf2.c:933 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf-fel: trasig radnummerssektion (felaktigt filnummer)." + +#: dwarf2.c:1032 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Dwarf-fel: Kan inte hitta sektionen .debug_line." + +#: dwarf2.c:1049 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "Dwarf-fel: Radavståndet (%lu) större än eller lika med storleken .debug_line (%lu)." + +#: dwarf2.c:1255 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf-fel: trasig radnummerssektion." + +#: dwarf2.c:1470 dwarf2.c:1620 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf-fel: Kunde inte hitta förkortningsnumret %u." + +#: dwarf2.c:1581 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Dwarf-fel: hittade dwarf version \"%u\", denna läsare hanterar endast information från version 2." + +#: dwarf2.c:1588 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf-fel: hittade adresstorleken \"%u\", denna läsare kan inte hantera storlekar större än \"%u\"." + +#: dwarf2.c:1611 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf-fel: Felaktigt förkortningsnummer: %u." + +#: ecoff.c:1339 +#, c-format +msgid "Unknown basic type %d" +msgstr "Okänd grundtyp %d" + +#: ecoff.c:1599 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Symbol slut+1: %ld" + +#: ecoff.c:1606 ecoff.c:1609 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Första symbolen: %ld" + +#: ecoff.c:1621 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Symbol slut+1: %-7ld Typ: %s" + +#: ecoff.c:1628 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Lokal symbol: %ld" + +#: ecoff.c:1636 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" struct; symbol slut+1: %ld" + +#: ecoff.c:1641 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" union; symbol slut+1: %ld" + +#: ecoff.c:1646 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; symbol slut+1: %ld" + +#: ecoff.c:1652 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Typ: %s" + +#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: varning: olöslig omlokalisering mot symbolen \"%s\" från sektionen %s" + +#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812 +#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815 +#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699 +#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510 +#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976 +#: elf64-mmix.c:1332 +msgid "internal error: out of range error" +msgstr "internt fel: utanför intervallet" + +#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816 +#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819 +#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287 +#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440 +#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452 +msgid "internal error: unsupported relocation error" +msgstr "internt fel: omlokaliseringen stöds inte" + +#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578 +#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313 +msgid "internal error: dangerous error" +msgstr "internt fel: farligt fel" + +#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824 +#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827 +#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711 +#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522 +#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988 +#: elf64-mmix.c:1344 +msgid "internal error: unknown error" +msgstr "internt fel: okänt fel" + +#: elf.c:372 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "%s: ogiltigt strängavstånd %u >= %lu för sektionen \"%s\"" + +#: elf.c:624 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s: ogiltig SHT_GROUP-post" + +#: elf.c:695 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s: ingen gruppinformation för sektionen %s" + +#: elf.c:1055 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Programhuvud:\n" + +#: elf.c:1106 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Dynamisk sektion:\n" + +#: elf.c:1235 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Versionsdefinitioner:\n" + +#: elf.c:1258 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Versionsreferenser:\n" + +#: elf.c:1263 +#, c-format +msgid " required from %s:\n" +msgstr " krävs från %s:\n" + +#: elf.c:1944 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "%s: ogiltig länk %lu för omlokaliseringssektion %s (index %u)" + +#: elf.c:3686 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s: Inte tillräckligt med utrymme för programhuvuden (allokerade %u, behöver %u)" + +#: elf.c:3791 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s: Inte tillräckligt med utrymme för programhuvuden, försök att länka med -N" + +#: elf.c:3922 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "Fel: Första sektionen i segmentet (%s) börjar vid 0x%x medan segmentet börjar med 0x%x" + +#: elf.c:4242 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s: varning: allokerad sektion \"%s\" inte i segment" + +#: elf.c:4566 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s: symbolen \"%s\" krävs men finns inte med" + +#: elf.c:4854 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s: varning: Tomt inläsningsbart segment upptäckt, är detta meningen?\n" + +#: elf.c:5485 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Kan inte hitta ekvivalent utdatasektion för symbolen \"%s\" från sektionen \"%s\"" + +#: elf.c:6298 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s: omlokaliseringstypen %s stöds inte" + +#: elf32-arm.h:1228 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "%s: Varning: Arm BLX-instruktion använder Arm-funktionen \"%s\" som mål." + +#: elf32-arm.h:1424 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%s: Varning: Thumb BLX-instruktionen använder thumb-funktionen \"%s\" som mål." + +#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx): %s omlokalisering mot SEC_MERGE-sektion" + +#: elf32-arm.h:2012 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "%s: varning: olöslig omlokalisering %d mot symbolen \"%s\" från sektionen %s" + +#: elf32-arm.h:2202 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "Varning: Stänger av samverkandeflaggan i %s eftersom icke-samverkande kod i %s har länkats med det" + +#: elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "FEL: %s är kompilerad för EABI version %d, medan %s är kompilerad för version %d" + +#: elf32-arm.h:2316 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "FEL: %s är kompilerad för APCS-%d, medan målet %s använder APCS-%d" + +#: elf32-arm.h:2344 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s does not" +msgstr "FEL: %s använder VFP-instruktioner, men det gör inte %s" + +#: elf32-arm.h:2349 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s does not" +msgstr "FEL: %s använder FPA-instruktioner, men det gör inte %s" + +#: elf32-arm.h:2360 elf32-arm.h:2365 +#, c-format +msgid "ERROR: %s uses Maverick instructions, whereas %s does not" +msgstr "FEL: %s använder Maverick-instruktioner, men det gör inte %s" + +#: elf32-arm.h:2385 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "FEL: %s använder programvaruflyttal, medan %s använder hårdvaruflyttal" + +#: elf32-arm.h:2390 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "FEL: %s använder hårdvaruflyttal, medan %s använder programvaruflyttal" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9238 +#, c-format +msgid "private flags = %lx:" +msgstr "privata flaggor = %lx:" + +#: elf32-arm.h:2452 +msgid " [interworking enabled]" +msgstr " [samverkande är aktiverat]" + +#: elf32-arm.h:2460 +msgid " [VFP float format]" +msgstr " [VFP-flyttalsformat]" + +#: elf32-arm.h:2462 +msgid " [Maverick float format]" +msgstr " [Maverick-flyttalsformat]" + +#: elf32-arm.h:2464 +msgid " [FPA float format]" +msgstr " [FPA-flyttalsformat]" + +#: elf32-arm.h:2473 +msgid " [new ABI]" +msgstr " [nytt ABI]" + +#: elf32-arm.h:2476 +msgid " [old ABI]" +msgstr " [gammalt ABI]" + +#: elf32-arm.h:2479 +msgid " [software FP]" +msgstr " [programvaru-FP]" + +#: elf32-arm.h:2488 +msgid " [Version1 EABI]" +msgstr " [Version1 EABI]" + +#: elf32-arm.h:2491 elf32-arm.h:2502 +msgid " [sorted symbol table]" +msgstr " [sorterad symboltabell]" + +#: elf32-arm.h:2493 elf32-arm.h:2504 +msgid " [unsorted symbol table]" +msgstr " [osorterad symboltabell]" + +#: elf32-arm.h:2499 +msgid " [Version2 EABI]" +msgstr " [Version2 EABI]" + +#: elf32-arm.h:2507 +msgid " [dynamic symbols use segment index]" +msgstr " [dynamiska symboler använder segmentindex]" + +#: elf32-arm.h:2510 +msgid " [mapping symbols precede others]" +msgstr " [mappsymboler har företräde före andra]" + +#: elf32-arm.h:2517 +msgid " " +msgstr " " + +#: elf32-arm.h:2524 +msgid " [relocatable executable]" +msgstr " [omlokaliseringsbar körbar fil]" + +#: elf32-arm.h:2527 +msgid " [has entry point]" +msgstr " [har startpunkt]" + +#: elf32-arm.h:2532 +msgid "" +msgstr "" + +#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823 +#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518 +#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984 +#: elf64-mmix.c:1340 +msgid "internal error: dangerous relocation" +msgstr "internt fel: farlig omlokalisering" + +#: elf32-cris.c:931 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%s: olöslig omlokalisering %s mot symbolen \"%s\" från sektionen %s" + +#: elf32-cris.c:993 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "%s: Varken någon PLT eller GOT för omlokalisering %s mot symbolen \"%s\" från sektionen %s" + +#: elf32-cris.c:996 elf32-cris.c:1122 +msgid "[whose name is lost]" +msgstr "[vars namn tappats bort]" + +#: elf32-cris.c:1111 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "%s: omlokalisering %s med icke-tomt addendum %d mot lokal symbol från sektionen %s" + +#: elf32-cris.c:1118 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "%s: omlokalisering %s med icke-tomt addendum %d mot symbolen \"%s\" från sektionen %s" + +#: elf32-cris.c:1143 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "%s: omlokaliseringen %s är inte tillåten för global symbol: \"%s\" från sektionen %s" + +#: elf32-cris.c:1158 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "%s: omlokalisering %s i sektionen %s utan GOT skapad" + +#: elf32-cris.c:1277 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s: Intern inkonsistens; ingen omlokaliseringssektion %s" + +#: elf32-cris.c:2500 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%s, sektion %s:\n" +" omlokaliseringen %s bör inte användas i ett delat objekt; kompilera om med -fPIC" + +#: elf32-cris.c:2978 +msgid " [symbols have a _ prefix]" +msgstr " [symboler har ett _-prefix]" + +#: elf32-cris.c:3017 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s: använder symboler med _-prefix, men skriver fil med symboler utan prefix" + +#: elf32-cris.c:3018 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s: använder symboler utan prefix, men skriver fil med symboler med _-prefix" + +#: elf32-frv.c:1223 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: kompilerad med %s och länkad med moduler som använder icke-pic-omlokalisering" + +#: elf32-frv.c:1273 elf32-iq2000.c:895 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: kompilerad med %s och länkad med moduler som kompilerats med %s" + +#: elf32-frv.c:1285 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: använder andra okända e_flags-fält (0x%lx) än tidigare moduler (0x%lx)" + +#: elf32-frv.c:1321 elf32-iq2000.c:933 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "privata flaggor = 0x%lx:" + +#: elf32-gen.c:83 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "%s: Omlokalisering i allmän ELF (EM: %d)" + +#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: kan inte skapa stubbstarten %s" + +#: elf32-hppa.c:957 elf32-hppa.c:3538 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%s(%s+0x%lx): kan inte nå %s, kompilera om med -ffunction-sections" + +#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%s: omlokaliseringen %s kan inte användas då ett delat objekt skapas; kompilera om med -fPIC" + +#: elf32-hppa.c:1360 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "%s: omlokaliseringen %s bör inte användas då ett delat objekt skapas; kompilera om med -fPIC" + +#: elf32-hppa.c:1553 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "Kunde inte hitta omlokaliseringssektion för %s" + +#: elf32-hppa.c:2828 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "%s: dubbel exportstubb %s" + +#: elf32-hppa.c:3416 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx): fixar %s" + +#: elf32-hppa.c:4039 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "%s(%s+0x%lx): kan inte hantera %s för %s" + +#: elf32-hppa.c:4357 +msgid ".got section not immediately after .plt section" +msgstr ".got-sektionen följer inte omedelbart efter .plt-sektion" + +#: elf32-i386.c:326 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s: ogiltig omlokaliseringstyp %d" + +#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637 +#: elf64-s390.c:943 elf64-x86-64.c:650 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s: felaktigt symbolindex: %d" + +#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011 +#: elf64-s390.c:1129 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "%s: \"%s\" anropad både som lokal normal symbol och lokal trådsymbol" + +#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243 +#: elf64-x86-64.c:886 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s: felaktig omlokaliseringssektionsnamn \"%s\"" + +#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879 +#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664 +#: elf64-x86-64.c:2452 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): olöslig omlokalisering mot symbolen \"%s\"" + +#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068 +#: elf64-x86-64.c:2490 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "%s(%s+0x%lx): omlokalisering mot \"%s\": fel %d" + +#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k-relaxerare: switchtabell utan helt matchande omlokaliseringsinformation." + +#: elf32-ip2k.c:588 elf32-ip2k.c:767 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k-relaxerare: switchtabellshuvud trasigt." + +#: elf32-ip2k.c:1395 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k-länkare: sidinstruktion saknas vid 0x%08lx (dest = 0x%08lx)." + +#: elf32-ip2k.c:1409 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k-länkare: redundant sidinstruktion vid 0x%08lx (dest = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1593 +msgid "unsupported relocation between data/insn address spaces" +msgstr "omlokalisering mellan data/-instruktionsadressutrymmen stöds inte" + +#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072 +#: elfxx-mips.c:9195 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: använder andra e_flags-fält (0x%lx) än tidigare moduler (0x%lx)" + +#: elf32-m32r.c:930 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "SDA-omlokalisering då _SDA_BASE_ inte är definierat" + +#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958 +#: elf64-ia64.c:3958 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: okänd omlokaliseringstyp %d" + +#: elf32-m32r.c:1226 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Målet (%s) för en %s-omlokalisering är i fel sektion (%s)" + +#: elf32-m32r.c:1952 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "%s: Instruktionsuppsättning passar inte med tidigare moduler" + +#: elf32-m32r.c:1975 +#, c-format +msgid "private flags = %lx" +msgstr "privata flaggor = %lx" + +#: elf32-m32r.c:1980 +msgid ": m32r instructions" +msgstr ": m32r-instruktioner" + +#: elf32-m32r.c:1981 +msgid ": m32rx instructions" +msgstr ": m32rx-instruktioner" + +#: elf32-m68hc1x.c:1217 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Referens till den avlägsna symbolen \"%s\" med hjälp av en felaktig omlokalisering kan resultera i felaktig exekvering" + +#: elf32-m68hc1x.c:1240 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "bankad adress [%lx:%04lx] (%lx) är inte i samma bank som den aktuella bankade adressen [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1259 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "referens till en bankad adress [%lx:%04lx] i det normala adressutrymmet vid %04lx" + +#: elf32-m68hc1x.c:1396 +#, c-format +msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%s: länkar filer kompilerade för 16-bitars heltal (-mshort) och andra för 32-bitars heltal" + +#: elf32-m68hc1x.c:1404 +#, c-format +msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%s: länkar filer kompilerade för 32-bitars dubbelprecisionsflyttal (-fshort-double) och andra för 64-bitars dubbelprecisionsflyttal" + +#: elf32-m68hc1x.c:1414 +#, c-format +msgid "%s: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%s: länkar filer kompilerade för HCS12 med andra kompilerade för HC12" + +#: elf32-m68hc1x.c:1462 +msgid "[abi=32-bit int, " +msgstr "[abi=32-bitars heltal, " + +#: elf32-m68hc1x.c:1464 +msgid "[abi=16-bit int, " +msgstr "[abi=16-bitars heltal, " + +#: elf32-m68hc1x.c:1467 +msgid "64-bit double, " +msgstr "64-bitars dubbelprecisionsflyttal, " + +#: elf32-m68hc1x.c:1469 +msgid "32-bit double, " +msgstr "32-bitars dubbelprecisionsflyttal, " + +#: elf32-m68hc1x.c:1472 +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1474 +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1476 +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1479 +msgid " [memory=bank-model]" +msgstr " [memory=bank-modell]" + +#: elf32-m68hc1x.c:1481 +msgid " [memory=flat]" +msgstr " [memory=platt]" + +#: elf32-m68k.c:400 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:403 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:353 elf32-mcore.c:456 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "%s: Omlokalisering %s (%d) stöds för närvarande inte.\n" + +#: elf32-mcore.c:441 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s: Okänd omlokaliseringstyp %d\n" + +#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32-bitars gp-relativ omlokalisering förekom för en extern symbol" + +#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "Länkning av mips16-objekt till %s-format stöds inte" + +#: elf32-ppc.c:2056 +#, c-format +msgid "generic linker can't handle %s" +msgstr "allmän länkare kan inte hantera %s" + +#: elf32-ppc.c:2138 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s: kompilerad med -mrelocatable och länkad med moduler som kompilerats normalt" + +#: elf32-ppc.c:2147 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s: kompilerad normalt och länkad med moduler som kompilerats med -mrelocatable" + +#: elf32-ppc.c:3413 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s: omlokaliseringen %s kan inte användas då ett delat objekt skapas" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3619 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against local symbol" +msgstr "%s(%s+0x%lx): %s-omlokalisering mot lokal symbol" + +#: elf32-ppc.c:4862 elf64-ppc.c:7789 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%s: okänd omlokaliseringstyp %d för symbolen %s" + +#: elf32-ppc.c:5113 +#, c-format +msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%s(%s+0x%lx): icke-tomt addendum på %s-omlokalisering mot \"%s\"" + +#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484 +#, c-format +msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%s: målet (%s) för en %s-omlokalisering är i fel utdatasektion (%s)" + +#: elf32-ppc.c:5539 +#, c-format +msgid "%s: relocation %s is not yet supported for symbol %s." +msgstr "%s: omlokaliseringen %s stöds inte än för symbolen %s." + +#: elf32-ppc.c:5594 elf64-ppc.c:8461 +#, c-format +msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): olöslig %s-omlokalisering mot symbolen \"%s\"" + +#: elf32-ppc.c:5644 elf64-ppc.c:8507 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against `%s': error %d" +msgstr "%s(%s+0x%lx): %s-omlokalisering mot \"%s\": fel %d" + +#: elf32-ppc.c:5888 +#, c-format +msgid "corrupt or empty %s section in %s" +msgstr "trasig eller tom %s-sektion i %s" + +#: elf32-ppc.c:5895 +#, c-format +msgid "unable to read in %s section from %s" +msgstr "kan inte läsa in %s-sektion från %s" + +#: elf32-ppc.c:5901 +#, c-format +msgid "corrupt %s section in %s" +msgstr "trasig %s-sektion i %s" + +#: elf32-ppc.c:5944 +#, c-format +msgid "warning: unable to set size of %s section in %s" +msgstr "varning: kan inte ställa in storleken för sektionen %s i %s" + +#: elf32-ppc.c:5994 +msgid "failed to allocate space for new APUinfo section." +msgstr "misslyckades med att allokera utrymme för ny APUinfo-sektion." + +#: elf32-ppc.c:6013 +msgid "failed to compute new APUinfo section." +msgstr "misslyckades med att beräkna ny APUinfo-sektion." + +#: elf32-ppc.c:6016 +msgid "failed to install new APUinfo section." +msgstr "misslyckades med att installera ny APUinfo-sektion." + +#: elf32-s390.c:2256 elf64-s390.c:2226 +#, c-format +msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%s(%s+0x%lx): ogiltig instruktion för TLS-omlokalisering %s" + +#: elf32-sh.c:2103 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s: 0x%lx: varning: felaktigt R_SH_USES-avstånd" + +#: elf32-sh.c:2115 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s: 0x%lx: varning: R_SH_USES pekar till okänd instruktion 0x%x" + +#: elf32-sh.c:2132 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s: 0x%lx: varning: felaktigt R_SH_USES-inläsningsavstånd" + +#: elf32-sh.c:2147 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s: 0x%lx: varning: kunde inte hitta förväntad omlokalisering" + +#: elf32-sh.c:2175 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s: 0x%lx: varning: symbol i oväntad sektion" + +#: elf32-sh.c:2300 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s: 0x%lx: varning: kunde inte hitta förväntad COUNT-omlokalisering" + +#: elf32-sh.c:2309 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s: 0x%lx: varning: felaktigt antal" + +#: elf32-sh.c:2712 elf32-sh.c:3088 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s: 0x%lx: ödesdigert: omlokalisering ger överspill vid förenklingen" + +#: elf32-sh.c:4654 elf64-sh64.c:1585 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Oväntat STO_SH5_ISA32 på lokal symbol hanteras inte" + +#: elf32-sh.c:4809 +#, c-format +msgid "%s: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: olöslig omlokalisering mot symbolen \"%s\" från sektionen %s" + +#: elf32-sh.c:4881 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%s: 0x%lx: ödesdigert: ojusterat grenmål för omlokalisering för förenklingsstöd" + +#: elf32-sh.c:6627 elf64-alpha.c:4848 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "%s: lokal TLS-exekveringskod kan inte länkas in i delade objekt" + +#: elf32-sh64.c:221 elf64-sh64.c:2407 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: kompilerat som 32-bitarsobjekt och %s är 64-bitars" + +#: elf32-sh64.c:224 elf64-sh64.c:2410 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: kompilerat som 64-bitarsobjekt och %s är 32-bitars" + +#: elf32-sh64.c:226 elf64-sh64.c:2412 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: objektstorleken stämmer inte överens med den hos målet %s" + +#: elf32-sh64.c:461 elf64-sh64.c:2990 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: påträffade dataetikettssymbol i indata" + +#: elf32-sh64.c:544 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB passar inte: en SHmedia-adress (bit 0 == 1)" + +#: elf32-sh64.c:547 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA passar inte: en SHcompact-adress (bit 0 == 0)" + +#: elf32-sh64.c:565 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: GAS-fel: oväntad PTB-instruktion med R_SH_PT_16" + +#: elf32-sh64.c:614 elf64-sh64.c:1748 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: fel: ojusterad omlokaliseringstyp %d på %08x omlokalisering %08x\n" + +#: elf32-sh64.c:698 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: kunde inte skriva ut tillagda .cranges-poster" + +#: elf32-sh64.c:760 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: kunde inte skriva ut sorterade cranges-poster" + +#: elf32-sparc.c:2521 elf64-sparc.c:2314 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "%s: troligen kompilerad utan -fPIC?" + +#: elf32-sparc.c:3348 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s: kompilerat för ett 64-bitarssystem och målet är 32-bitars" + +#: elf32-sparc.c:3362 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s: länkar little endian-filer med big endian-filer" + +#: elf32-v850.c:753 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Variabel \"%s\" kan inte befinna sig i flera små dataområden" + +#: elf32-v850.c:756 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Variabel \"%s\" kan bara vara i ett av de små, tomma och pyttesmå dataområdena" + +#: elf32-v850.c:759 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Variabel \"%s\" kan inte vara i både små och tomma dataområden samtidigt" + +#: elf32-v850.c:762 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Variabel \"%s\" kan inte vara i både små och pyttesmå dataområden samtidigt" + +#: elf32-v850.c:765 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Variabel \"%s\" kan inte vara i både tomma och pyttesmå dataområden samtidigt" + +#: elf32-v850.c:1144 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "MISSLYCKADES med att hitta tidigare HI16-omlokalisering\n" + +#: elf32-v850.c:1789 +msgid "could not locate special linker symbol __gp" +msgstr "kunde inte lokalisera speciell länkarsymbol __gp" + +#: elf32-v850.c:1793 +msgid "could not locate special linker symbol __ep" +msgstr "kunde inte lokalisera speciell länkarsymbol __ep" + +#: elf32-v850.c:1797 +msgid "could not locate special linker symbol __ctbp" +msgstr "kunde inte lokalisera speciell länkarsymbol __ctbp" + +#: elf32-v850.c:1963 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s: Arkitekturen passar inte ihop med tidigare moduler" + +#: elf32-v850.c:1983 +#, c-format +msgid "private flags = %lx: " +msgstr "privata flaggor = %lx: " + +#: elf32-v850.c:1988 +msgid "v850 architecture" +msgstr "v850-arkitektur" + +#: elf32-v850.c:1989 +msgid "v850e architecture" +msgstr "v850e-arkitektur" + +#: elf32-vax.c:549 +msgid " [nonpic]" +msgstr " [icke-pic]" + +#: elf32-vax.c:552 +msgid " [d-float]" +msgstr " [d-flyttal]" + +#: elf32-vax.c:555 +msgid " [g-float]" +msgstr " [g-flyttal]" + +#: elf32-vax.c:663 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: varning: GOT-addendum %ld till \"%s\" stämmer inte överens med tidigare GOT-addendum %ld" + +#: elf32-vax.c:1667 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: varning: PLT-addendum %d till \"%s\" från sektionen %s ignorerades" + +#: elf32-vax.c:1802 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: varning: %s-omlokalisering mot symbolen \"%s\" från sektionen %s" + +#: elf32-vax.c:1808 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: varning: %s-omlokalisering till 0x%x från sektionen %s" + +#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450 +msgid "non-zero addend in @fptr reloc" +msgstr "icke-tomt addendum i @fptr-omlokalisering" + +#: elf64-alpha.c:1108 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP-omlokalisering hittade inga ldah- och lda-instruktioner" + +#: elf64-alpha.c:3731 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s: .got-subsegment överskrider 64 kB (storlek %d)" + +#: elf64-alpha.c:4602 elf64-alpha.c:4614 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "%s: gp-relativ omlokalisering mot dynamiska symbolen %s" + +#: elf64-alpha.c:4640 elf64-alpha.c:4773 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "%s: pc-relativ omlokalisering mot dynamiska symbolen %s" + +#: elf64-alpha.c:4668 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "%s: ändring i gp: BRSGP %s" + +#: elf64-alpha.c:4693 +msgid "" +msgstr "" + +#: elf64-alpha.c:4698 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "%s: !samegp-omlokalisering mot symbol utan .prologue: %s" + +#: elf64-alpha.c:4749 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s: ohanterad dynamisk omlokalisering mot %s" + +#: elf64-alpha.c:4832 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "%s: dtp-relativ omlokalisering mot dynamiska symbolen %s" + +#: elf64-alpha.c:4855 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "%s: tp-relativ omlokalisering mot dynamiska symbolen %s" + +#: elf64-hppa.c:2086 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "stubbpost för %s kan inte läsa in .plt, dp-avstånd = %ld" + +#: elf64-mmix.c:1032 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Intern inkkonsistensfel för värdet för\n" +" länkarallokerat globalt register: länkat: 0x%lx%08lx != avslappnat: 0x%lx%08lx\n" + +#: elf64-mmix.c:1416 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: bas-plus-avståndsomlokalisering mot registersymbol: (okänd) i %s" + +#: elf64-mmix.c:1421 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: bas-plus-avståndsomlokalisering mot registersymbol: %s i %s" + +#: elf64-mmix.c:1465 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: registeromlokalisering mot icke-registersymbol: (okänd) i %s" + +#: elf64-mmix.c:1470 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: registeromlokalisering mot icke-registersymbol: %s i %s" + +#: elf64-mmix.c:1507 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: LOCAL-direktivet är endast giltigt med ett register eller absolutvärde" + +#: elf64-mmix.c:1535 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s: LOCAL-direktiv: Register $%ld är inte ett lokalt register. Första globala registret är $%ld." + +#: elf64-mmix.c:1994 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s: Fel: flera definitioner av \"%s\"; början på %s är inställd i en tidigare länkad fil\n" + +#: elf64-mmix.c:2053 +msgid "Register section has contents\n" +msgstr "Registersektion har innehåll\n" + +#: elf64-mmix.c:2216 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Intern inkonsekvens: återstående %u != max %u.\n" +" Rapportera gärna detta fel." + +#: elf64-ppc.c:2388 libbfd.c:831 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s: kompilerad för big endian-system och målet är little endian" + +#: elf64-ppc.c:2391 libbfd.c:833 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s: kompilerad för ett little endian-system och målet är big endian" + +#: elf64-ppc.c:4857 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s: oväntad omlokaliseringstyp %u i .opd-sektion" + +#: elf64-ppc.c:4877 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s: .opd är inte en vanlig vektor med opd-poster" + +#: elf64-ppc.c:4897 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s: odefinierad symbol \"%s\" i .opd-sektion" + +#: elf64-ppc.c:6136 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "kan inte hitta grenstubb \"%s\"" + +#: elf64-ppc.c:6175 elf64-ppc.c:6250 +#, c-format +msgid "linkage table error against `%s'" +msgstr "länktabellsfel mot \"%s\"" + +#: elf64-ppc.c:6340 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "kan inte bygga grenstubb \"%s\"" + +#: elf64-ppc.c:7047 +msgid ".glink and .plt too far apart" +msgstr ".glink och .plt för långt ifrån varandra" + +#: elf64-ppc.c:7135 +msgid "stubs don't match calculated size" +msgstr "stubbar stämmer inte överens med beräknad storlek" + +#: elf64-ppc.c:7147 +#, c-format +msgid "" +"linker stubs in %u groups\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"länkarstubbar i %u grupper\n" +" gren %lu\n" +" toc-justering %lu\n" +" lång gren %lu\n" +" lång toc-just. %lu\n" +" plt-anrop %lu" + +#: elf64-ppc.c:7723 +#, c-format +msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%s(%s+0x%lx): flera automatiska TOC stöds inte vid användning av dina crt-filer; kompilera om med -mminimal-toc eller uppgradera gcc" + +#: elf64-ppc.c:7731 +#, c-format +msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%s(%s+0x%lx): syskonanropsoptimering till \"%s\" stöder inte flera automatiska TOC; kompilera om med -mminimal-toc eller -fno-optimize-sibling-calls, eller gör \"%s\" extern" + +#: elf64-ppc.c:8329 +#, c-format +msgid "%s: relocation %s is not supported for symbol %s." +msgstr "%s: omlokaliseringen %s stöds inte för symbolen %s." + +#: elf64-ppc.c:8408 +#, c-format +msgid "%s: error: relocation %s not a multiple of %d" +msgstr "%s: fel: omlokaliseringen %s är inte en multipel av %d" + +#: elf64-sparc.c:1370 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s: check_relocs: ohanterad omlokaliseringstyp %d" + +#: elf64-sparc.c:1407 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s: Endast register %%g[2367] kan deklareras med STT_REGISTER" + +#: elf64-sparc.c:1427 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "Register %%g%d används inkompatibelt: %s i %s, tidigare %s i %s" + +#: elf64-sparc.c:1450 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "Symbolen \"%s\" har olika typer: REGISTER i %s, tidigare %s i %s" + +#: elf64-sparc.c:1496 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "Symbolen \"%s\" har olika typer: %s i %s, tidigare REGISTER i %s" + +#: elf64-sparc.c:3053 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "%s: länkar UltraSPARC-specifik med HAL-specifik kod" + +#: elf64-x86-64.c:739 +#, c-format +msgid "%s: %s' accessed both as normal and thread local symbol" +msgstr "%s: \"%s\" anropad både som lokal normal symbol och lokal trådsymbol" + +#: elfcode.h:1113 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: versionsantal (%ld) stämmer inte med symbolantal (%ld)" + +#: elfcode.h:1342 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): omlokalisering %d har ogiltigt symbolindex %ld" + +#: elflink.c:1456 +#, c-format +msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s: varning: oväntad omdefinition av indirekt versionsangiven symbol \"%s\"" + +#: elflink.c:1807 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s: odefinierat symbolnamn med version %s" + +#: elflink.c:2142 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "%s: omlokaliseringsstorleken stämmer inte överens i %s, sektion %s" + +#: elflink.c:2434 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "varning: typen och storleken på dynamiska symbolen \"%s\" är inte definierade" + +#: elflink.h:1022 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s: %s: ogiltig version %u (max %d)" + +#: elflink.h:1063 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s: %s: ogiltig krävd version %d" + +#: elflink.h:1238 +#, c-format +msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s" +msgstr "Varning: justeringen %u på symbolen \"%s\" i %s är mindre än %u i %s" + +#: elflink.h:1252 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s" +msgstr "Varning: storleken på symbolen \"%s\" ändrades från %lu i %s till %lu i %s" + +#: elflink.h:2160 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: odefinierad version: %s" + +#: elflink.h:2226 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s: .preinit_array-sektionen är inte tillåten i DSO" + +#: elflink.h:3078 +msgid "Not enough memory to sort relocations" +msgstr "Inte tillräckligt med minne för att sortera omlokaliseringar" + +#: elflink.h:3958 elflink.h:4001 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s: kunde inte hitta utdatasektionen %s" + +#: elflink.h:3964 +#, c-format +msgid "warning: %s section has zero size" +msgstr "varning: sektionen %s har nollstorlek" + +#: elflink.h:4483 +#, c-format +msgid "%s: %s symbol `%s' in %s is referenced by DSO" +msgstr "%s: %s-symbolen \"%s\" i %s refereras till av DSO" + +#: elflink.h:4564 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%s: kunde inte hitta utdatasektionen %s för indatasektionen %s" + +#: elflink.h:4666 +#, c-format +msgid "%s: %s symbol `%s' isn't defined" +msgstr "%s: %s-symbolen \"%s\" är inte definierad" + +#: elflink.h:5053 elflink.h:5095 +msgid "%T: discarded in section `%s' from %s\n" +msgstr "%T: bortkastade i sektionen \"%s\" från %s\n" + +#: elfxx-mips.c:887 +msgid "static procedure (no name)" +msgstr "statisk procedur (inget namn)" + +#: elfxx-mips.c:1897 +msgid "not enough GOT space for local GOT entries" +msgstr "inte tillräckligt med GOT-utrymme för lokala GOT-poster" + +#: elfxx-mips.c:3691 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "%s: %s+0x%lx: hoppa till stubbrutin som inte är jal" + +#: elfxx-mips.c:5192 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: Felaktig omlokalisering för sektion %s upptäckt" + +#: elfxx-mips.c:5266 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s: CALL16-omlokalisering vid 0x%lx är inte mot global symbol" + +#: elfxx-mips.c:8692 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: ogiltigt sektionsnamn \"%s\"" + +#: elfxx-mips.c:9025 +#, c-format +msgid "%s: endianness incompatible with that of the selected emulation" +msgstr "%s: endianness inkompatibel med den för den valda emuleringen" + +#: elfxx-mips.c:9037 +#, c-format +msgid "%s: ABI is incompatible with that of the selected emulation" +msgstr "%s: ABI är inkompatibelt med den för den valda emuleringen" + +#: elfxx-mips.c:9104 +#, c-format +msgid "%s: warning: linking PIC files with non-PIC files" +msgstr "%s: varning: länkar PIC-filer med icke-PIC-filer" + +#: elfxx-mips.c:9121 +#, c-format +msgid "%s: linking 32-bit code with 64-bit code" +msgstr "%s: länkar 32-bitarskod med 64-bitarskod" + +#: elfxx-mips.c:9149 +#, c-format +msgid "%s: linking %s module with previous %s modules" +msgstr "%s: länkar %s-modul med tidigare %s-moduler" + +#: elfxx-mips.c:9172 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s: ABI passar inte: länkar %s-modul med tidigare %s-moduler" + +#: elfxx-mips.c:9241 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:9243 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:9245 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:9247 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:9249 +msgid " [abi unknown]" +msgstr " [okänt abi]" + +#: elfxx-mips.c:9251 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:9253 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:9255 +msgid " [no abi set]" +msgstr " [inget abi inställt]" + +#: elfxx-mips.c:9258 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:9260 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:9262 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:9264 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:9266 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:9268 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:9270 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:9272 +msgid " [mips32r2]" +msgstr " [mips32r2]" + +#: elfxx-mips.c:9274 +msgid " [unknown ISA]" +msgstr " [okänd ISA]" + +#: elfxx-mips.c:9277 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:9280 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:9283 +msgid " [32bitmode]" +msgstr " [32-bitarsläge]" + +#: elfxx-mips.c:9285 +msgid " [not 32bitmode]" +msgstr " [inte 32-bitarsläge]" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Utdatafilen kräver delade biblioteket \"%s\"\n" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Utdatafilen kräver delade biblioteket \"%s.so.%s\"\n" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Symbolen %s är inte definierad för fixar\n" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +msgid "Warning: fixup count mismatch\n" +msgstr "Varning: antalet fixar stämmer inte\n" + +#: ieee.c:293 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: strängen är för lång (%d tecken, max 65535)" + +#: ieee.c:428 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: okänd symbol \"%s\" flaggor 0x%x" + +#: ieee.c:938 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "%s: inte implementerad ATI-post %u för symbolen %u" + +#: ieee.c:963 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "%s: oväntad ATN-typ %d i extern del" + +#: ieee.c:985 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s: oväntad typ efter ATN" + +#: ihex.c:264 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s:%d: oväntat tecken \"%s\" i hexadecimal Intel-fil\n" + +#: ihex.c:372 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s:%u: felaktig kontrollsumma i hexadecimal Intel-fil (förväntade %u, hittade %u)" + +#: ihex.c:426 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "%s:%u: felaktig längd på post för utökad adress i hexadecimal Intel-fil" + +#: ihex.c:443 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "%s:%u: felaktig längd på utökad startadress i hexadecimal Intel-fil" + +#: ihex.c:460 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s:%u: felaktig längd på post för utökad linjär adress i hexadecimal Intel-fil" + +#: ihex.c:477 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s:%u: felaktig längd på post för utökad linjär startadress i hexadecimal Intel-fil" + +#: ihex.c:494 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "%s:%u: okänd ihex-typ %u i hexadecimal Intel-fil\n" + +#: ihex.c:619 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "%s: internt fel i ihex_read_section" + +#: ihex.c:654 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "%s: felaktig sektionslängd i ihex_read_sektion" + +#: ihex.c:872 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: adressen 0x%s är utanför intervallet för hexadecimal Intel-fil" + +#: libbfd.c:861 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "Föråldrad %s anropad vid %s rad %d i %s\n" + +#: libbfd.c:864 +#, c-format +msgid "Deprecated %s called\n" +msgstr "Föråldrad %s anropad\n" + +#: linker.c:1829 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "%s: indirekt symbol \"%s\" till \"%s\" är en slinga" + +#: linker.c:2697 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Försök att göra en omlokaliseringsbar länk med %s-indata och %s-utdata" + +#: merge.c:896 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "%s: åtkomst bortom slut på sammanslagen sektion (%ld + %ld)" + +#: mmo.c:503 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Ingen kärna för att allokera sektionsnamn %s\n" + +#: mmo.c:579 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Ingen kärna för att allokera en %d byte lång symbol\n" + +#: mmo.c:1287 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: ogiltig mmo-fil: initieringsvärde för $255 är inte \"Main\"\n" + +#: mmo.c:1433 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: bred teckensekvens som inte stöds 0x%02X 0x%02X efter symbolnamnet som börjar med \"%s\"\n" + +#: mmo.c:1674 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: ogiltig mmo-fil: lopkod \"%d\" stöds inte\n" + +#: mmo.c:1684 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: ogiltig mmo-fil: förväntade YZ = 1 fick YZ = %d för lop_quote\n" + +#: mmo.c:1720 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: ogiltig mmo-fil: förväntade z = 1 eller z = 2, fick z = %d för lop_loc\n" + +#: mmo.c:1766 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: ogiltig mmo-fil: förväntade z = 1 eller z = 2, fick z = %d för lop_fixo\n" + +#: mmo.c:1805 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: ogiltig mmo-fil: förväntade y = 0, fick y = %d för lop_fixrx\n" + +#: mmo.c:1814 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: ogiltig mmo-fil: förväntade z = 16 eller z = 24, fick z = %d för lop_fixr\n" + +#: mmo.c:1837 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: ogiltig mmo-fil: inledande byte i operandord måste vara 0 eller 1, fick %d för lop_fixrx\n" + +#: mmo.c:1860 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: kan inte allokera filnamn för fil nummer %d, %d byte\n" + +#: mmo.c:1880 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: ogiltig mmo-fil: fil nummer %d \"%s\", var redan angiven som \"%s\"\n" + +#: mmo.c:1893 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: ogiltig mmo-fil: filnamnet för nummer %d angavs inte innan användning\n" + +#: mmo.c:1999 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: ogiltig mmo-fil: fälten y och z i lop_stab är icke-tomma, y: %d, z: %d\n" + +#: mmo.c:2035 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: ogiltig mmo-fil: lop_end är inte sista objektet i fil\n" + +#: mmo.c:2048 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: ogiltig mmo-fil: YZ i lop_end (%ld) är inte lika med antalet tetra till den föregående lop_stab (%ld)\n" + +#: mmo.c:2698 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: ogiltig symboltabell: dublettsymbol \"%s\"\n" + +#: mmo.c:2949 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Felaktig symboldefinition: \"Main\" är inställd till %s istället för startadressen %s\n" + +#: mmo.c:3039 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: varning: symboltabellen är för stor för mmo, större än 65535 32-bitars ord: %d. Endast \"Main\" kommer att skickas.\n" + +#: mmo.c:3084 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: internt fel, symboltabellen ändrade storlek från %d till %d ord\n" + +#: mmo.c:3139 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: internt fel, interna registersektionen %s hade innehåll\n" + +#: mmo.c:3191 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: inga initierade register; sektionslängd 0\n" + +#: mmo.c:3197 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: för många initierade register; sektionslängd %ld\n" + +#: mmo.c:3202 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: ogiltig startadress för initierade register med längden %ld: 0x%lx%08lx\n" + +#: oasys.c:1052 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: kan inte representera sektionen \"%s\" i oasys" + +#: osf-core.c:137 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Ohanterad sektionstyp %d för OSF/1-minnesfil\n" + +#: pe-mips.c:659 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s: \"ld -r\" stöds inte med PE MIPS-objekt\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:795 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s: oimplementerat %s\n" + +#: pe-mips.c:821 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s: hopp för långt bort\n" + +#: pe-mips.c:848 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "%s: felaktigt par/reflo efter refhi\n" + +#. XXX code yet to be written. +#: peicode.h:787 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s: Ohanterad importtyp; %x" + +#: peicode.h:792 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s: Okänd importtyp; %x" + +#: peicode.h:806 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s: Okänd importnamnstyp; %x" + +#: peicode.h:1164 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s: Okänd maskintyp (0x%x) i Import Library Format-arkiv" + +#: peicode.h:1176 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s: Känd men ohanterad maskintyp (0x%x) i Import Library Format-arkiv" + +#: peicode.h:1193 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "%s: storleksfältet är noll i Import Library Format-huvud" + +#: peicode.h:1224 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "%s: sträng inte nollterminerad i ILF-objektfil." + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot-huvud:\n" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Startavstånd = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Längd = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Flaggfält = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Partitionsnamn = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Start på partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Slut på partition[%d] = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Sektor för partition[%d] = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Längd på partition[%d] = 0x%.8lx (%ld)\n" + +#: som.c:5422 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers är inte implementerat" + +#: srec.c:302 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d: Oväntat tecken \"%s\" i S-postfil\n" + +# Vad är stabs? +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "%s(%s+0x%lx): Stabbpost har ogiltigt strängindex." + +#: syms.c:1019 +msgid "Unsupported .stab relocation" +msgstr ".stab-omlokalisering som inte stöds" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) misslyckades" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) misslyckades" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Storleken passar inte på sektion %s=%lx, %s=%lx" + +#: vms-gsd.c:704 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "okänd gsd/egsd-undertyp %d" + +#: vms-hdr.c:408 +msgid "Object module NOT error-free !\n" +msgstr "Objektmodulen INTE felfri!\n" + +#: vms-misc.c:541 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Stacken ger överspill (%d) i _bfd_vms_push" + +#: vms-misc.c:559 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Stacken ger underspill i _bfd_vms_pop" + +#: vms-misc.c:918 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted anropad med noll byte" + +#: vms-misc.c:923 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted called anropad med för många byte" + +#: vms-misc.c:1054 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Symbolen %s ersatt med %s\n" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "misslyckades med att gå in i %s" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "Inget minne!" + +#: vms-tir.c:383 +#, c-format +msgid "bad section index in %s" +msgstr "felaktigt sektionsindex i %s" + +#: vms-tir.c:396 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "STA-kommando %s stöds inte" + +#: vms-tir.c:401 vms-tir.c:1261 +#, c-format +msgid "reserved STA cmd %d" +msgstr "reserverat STA-kommando %d" + +#: vms-tir.c:512 vms-tir.c:535 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "%s: ingen symbol \"%s\"" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850 +#: vms-tir.c:859 vms-tir.c:1584 +#, c-format +msgid "%s: not supported" +msgstr "%s: stöds inte" + +#: vms-tir.c:607 vms-tir.c:1439 +#, c-format +msgid "%s: not implemented" +msgstr "%s: inte implementerad" + +#: vms-tir.c:611 vms-tir.c:1443 +#, c-format +msgid "reserved STO cmd %d" +msgstr "reserverat STO-kommando %d" + +#: vms-tir.c:729 vms-tir.c:1589 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "reserverat OPR-kommando %d" + +#: vms-tir.c:797 vms-tir.c:1653 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "reserverat CTL-kommando %d" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1169 +msgid "stack-from-image not implemented" +msgstr "stack-from-image är inte implementerat" + +#: vms-tir.c:1187 +msgid "stack-entry-mask not fully implemented" +msgstr "stack-entry-mask är inte helt implementerat" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1201 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH är inte helt implementerat" + +#: vms-tir.c:1220 +msgid "stack-local-symbol not fully implemented" +msgstr "stack-local-symbol är inte helt implementerat" + +#: vms-tir.c:1233 +msgid "stack-literal not fully implemented" +msgstr "stack-literal är inte helt implementerat" + +#: vms-tir.c:1254 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "stack-local-symbol-entry-point-mask är inte helt implementerat" + +#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632 +#: vms-tir.c:1640 vms-tir.c:1648 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: inte helt implementerat" + +#: vms-tir.c:1705 +#, c-format +msgid "obj code %d not found" +msgstr "objektkod %d kunde inte hittas" + +#: vms-tir.c:2043 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC utan omlokaliseringar i sektion %s" + +#: vms-tir.c:2331 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Ohanterad omlokalisering %s" + +#: xcofflink.c:1244 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "%s: \"%s\" har radnummer men ingen inneslutande sektion" + +#: xcofflink.c:1297 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "%s: klass %d-symbolen \"%s\" har inga yttre poster" + +#: xcofflink.c:1320 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "%s: symbolen \"%s\" har okänd csect-typ %d" + +#: xcofflink.c:1332 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s: felaktig XTY_ER-symbol \"%s\": klass %d scnum %d scnlen %d" + +#: xcofflink.c:1368 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s: XMC_TC0-symbolen \"%s\" är klass %d scnlen %d" + +#: xcofflink.c:1520 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "%s: csect \"%s\" är inte i inneslutande sektion" + +#: xcofflink.c:1627 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "%s: felaktigt placerat XTY_LD \"%s\"" + +#: xcofflink.c:1958 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "%s: omlokaliseringen %s:%d är inte i csect" + +#: xcofflink.c:2095 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF delade objekt när inte XCOFF-utdata produceras" + +#: xcofflink.c:2116 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: dynamiskt objekt utan någon .loader-sektion" + +#: xcofflink.c:2761 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: ingen sådan symbol" + +#: xcofflink.c:2894 +msgid "error: undefined symbol __rtinit" +msgstr "fel: odefinierad symbol __rtinit" + +#: xcofflink.c:3455 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "varning: försök att exportera odefinierade symbolen \"%s\"" + +#: xcofflink.c:4448 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "TOC ger överspill: 0x%lx > 0x10000; prova -mminimal-toc vid kompilering" + +#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "%s: inläsaromlokalisering i okända sektionen \"%s\"" + +#: xcofflink.c:5310 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "%s: \"%s\" i inläsaromlokalisering men inte inläsarsym" + +#: xcofflink.c:5325 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "%s: inläsaromlokalisering i skrivskyddade sektionen %s" + +#: elf32-ia64.c:2392 elf64-ia64.c:2392 +msgid "@pltoff reloc against local symbol" +msgstr "@pltoff-omlokalisering mot lokal symbol" + +#: elf32-ia64.c:3804 elf64-ia64.c:3804 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: kort datasegment spillde över (0x%lx >= 0x400000)" + +#: elf32-ia64.c:3815 elf64-ia64.c:3815 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp täcker inte kort datasegment" + +#: elf32-ia64.c:4131 elf64-ia64.c:4131 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "%s: länkar icke-pic-kod i delat bibliotek" + +#: elf32-ia64.c:4164 elf64-ia64.c:4164 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "%s: @gprel-omlokalisering mot dynamiska symbolen %s" + +#: elf32-ia64.c:4224 elf64-ia64.c:4224 +#, c-format +msgid "%s: linking non-pic code in a position independent executable" +msgstr "%s: länkar icke-pic-kod i en positionsoberoende körbar fil" + +#: elf32-ia64.c:4363 elf64-ia64.c:4363 +#, c-format +msgid "%s: @internal branch to dynamic symbol %s" +msgstr "%s: @internal-gren till dynamiska symbolen %s" + +#: elf32-ia64.c:4365 elf64-ia64.c:4365 +#, c-format +msgid "%s: speculation fixup to dynamic symbol %s" +msgstr "%s: spekulationsfix till dynamiska symbolen %s" + +#: elf32-ia64.c:4367 elf64-ia64.c:4367 +#, c-format +msgid "%s: @pcrel relocation against dynamic symbol %s" +msgstr "%s: @pcrel-omlokalisering mot dynamiska symbolen %s" + +#: elf32-ia64.c:4579 elf64-ia64.c:4579 +msgid "unsupported reloc" +msgstr "omlokaliseringen stöds inte" + +#: elf32-ia64.c:4858 elf64-ia64.c:4858 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%s: länkar fånga-vid-NULL-dereferens med ickefångande filer" + +#: elf32-ia64.c:4867 elf64-ia64.c:4867 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s: länkar big endian-filer med little endian-filer" + +#: elf32-ia64.c:4876 elf64-ia64.c:4876 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s: länkar 64-bitarsfiler med 32-bitarsfiler" + +#: elf32-ia64.c:4885 elf64-ia64.c:4885 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "%s: länkar konstant-gp-filer med icke-konstant-gp-filer" + +#: elf32-ia64.c:4895 elf64-ia64.c:4895 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "%s: länkar auto-pic-filer med icke-auto-pic-filer" + +#: peigen.c:985 pepigen.c:985 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: radnummer ger överspill: 0x%lx > 0xffff" + +#: peigen.c:1002 pepigen.c:1002 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "%s: omlokalisering ger överspill 1: 0x%lx > 0xffff" + +#: peigen.c:1016 pepigen.c:1016 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Exportkatalog [.edata (eller där vi hittade det)]" + +#: peigen.c:1017 pepigen.c:1017 +msgid "Import Directory [parts of .idata]" +msgstr "Importkatalog [delar av .idata]" + +#: peigen.c:1018 pepigen.c:1018 +msgid "Resource Directory [.rsrc]" +msgstr "Resurskatalog [.rsrc]" + +#: peigen.c:1019 pepigen.c:1019 +msgid "Exception Directory [.pdata]" +msgstr "Undantagskatalog [.pdata]" + +#: peigen.c:1020 pepigen.c:1020 +msgid "Security Directory" +msgstr "Säkerhetskatalog" + +#: peigen.c:1021 pepigen.c:1021 +msgid "Base Relocation Directory [.reloc]" +msgstr "Basomlokaliseringskatalog [.reloc]" + +#: peigen.c:1022 pepigen.c:1022 +msgid "Debug Directory" +msgstr "Felsökningskatalog" + +#: peigen.c:1023 pepigen.c:1023 +msgid "Description Directory" +msgstr "Beskrivningskatalog" + +#: peigen.c:1024 pepigen.c:1024 +msgid "Special Directory" +msgstr "Specialkatalog" + +#: peigen.c:1025 pepigen.c:1025 +msgid "Thread Storage Directory [.tls]" +msgstr "Trådlagringskatalog [.tls]" + +#: peigen.c:1026 pepigen.c:1026 +msgid "Load Configuration Directory" +msgstr "Inläsningskonfigurationskatalog" + +#: peigen.c:1027 pepigen.c:1027 +msgid "Bound Import Directory" +msgstr "Katalog över bundna importer" + +#: peigen.c:1028 pepigen.c:1028 +msgid "Import Address Table Directory" +msgstr "Importadresstabellkatalog" + +#: peigen.c:1029 pepigen.c:1029 +msgid "Delay Import Directory" +msgstr "Katalog över fördröjda importer" + +#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031 +msgid "Reserved" +msgstr "Reserverad" + +#: peigen.c:1094 pepigen.c:1094 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Det finns en importtabell, men sektionen som innehåller den kunde inte hittas\n" + +#: peigen.c:1099 pepigen.c:1099 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Det finns en importtabell i %s på 0x%lx\n" + +#: peigen.c:1136 pepigen.c:1136 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Funktionsidentifierare hittad på startadressen: %04lx\n" + +#: peigen.c:1139 pepigen.c:1139 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tkodbas %08lx toc (inläsningsbar/verklig) %08lx/%08lx\n" + +#: peigen.c:1145 pepigen.c:1145 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Ingen reldata-sektion! Funktionsidentifierare avkodades inte.\n" + +#: peigen.c:1150 pepigen.c:1150 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Importtabellerna (tolkade innehåll i %s-sektion)\n" + +# Vad är thunk? +#: peigen.c:1153 pepigen.c:1153 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Tips- Tids- Framåt- DLL- Första\n" +" tabell stämpel kedja namn thunk\n" + +#: peigen.c:1204 pepigen.c:1204 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL-namn: %s\n" + +#: peigen.c:1215 pepigen.c:1215 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Tips/Ordn Medlemsnamn Bundet till\n" + +#: peigen.c:1240 pepigen.c:1240 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Det finns en första thunk, men sektionen som innehåller den kunde inte hittas\n" + +#: peigen.c:1380 pepigen.c:1380 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Det finns en exporttabell, men sektionen som innehåller den kunde inte hittas\n" + +#: peigen.c:1385 pepigen.c:1385 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Det finns en exporttabell i %s vid 0x%lx\n" + +#: peigen.c:1416 pepigen.c:1416 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Exporttabellerna (tolkade innehåll i %s-sektion)\n" + +#: peigen.c:1420 pepigen.c:1420 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Exportflaggor \t\t\t%lx\n" + +#: peigen.c:1423 pepigen.c:1423 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Tid-/Datumstämpel \t\t%lx\n" + +#: peigen.c:1426 pepigen.c:1426 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Övre/Undre \t\t\t%d/%d\n" + +#: peigen.c:1429 pepigen.c:1429 +msgid "Name \t\t\t\t" +msgstr "Namn \t\t\t\t" + +#: peigen.c:1435 pepigen.c:1435 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Ordningsbas \t\t\t%ld\n" + +#: peigen.c:1438 pepigen.c:1438 +msgid "Number in:\n" +msgstr "Tal i:\n" + +#: peigen.c:1441 pepigen.c:1441 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tExportadresstabell \t\t%08lx\n" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Namnpekare/Ordningstal]-tabell\t%08lx\n" + +#: peigen.c:1448 pepigen.c:1448 +msgid "Table Addresses\n" +msgstr "Tabelladresser\n" + +#: peigen.c:1451 pepigen.c:1451 +msgid "\tExport Address Table \t\t" +msgstr "\tExportadresstabell \t\t" + +#: peigen.c:1456 pepigen.c:1456 +msgid "\tName Pointer Table \t\t" +msgstr "\tNamnpekartabell \t\t" + +#: peigen.c:1461 pepigen.c:1461 +msgid "\tOrdinal Table \t\t\t" +msgstr "\tOrdningstalstabell \t\t\t" + +#: peigen.c:1476 pepigen.c:1476 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Exportadresstabell -- Orningsbas %ld\n" + +#: peigen.c:1495 pepigen.c:1495 +msgid "Forwarder RVA" +msgstr "Vidarebefordrar-RVA" + +#: peigen.c:1506 pepigen.c:1506 +msgid "Export RVA" +msgstr "Export-RVA" + +#: peigen.c:1513 pepigen.c:1513 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Ordningstals-/Namnpekar-]tabell\n" + +#: peigen.c:1568 pepigen.c:1568 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Varning, storleken på .pdata-sektionen (%ld) är inte en multipel av %d\n" + +#: peigen.c:1572 pepigen.c:1572 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Funktionstabellen (tolkade innehåll från .pdata-sektionen)\n" + +#: peigen.c:1575 pepigen.c:1575 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tStartadress Slutadress Ospola information\n" + +#: peigen.c:1577 pepigen.c:1577 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tStart- Slut- EH- EH- Prologsluts- Undantags-\n" +" \t\tadress adress hanterare data adress mask\n" + +#: peigen.c:1647 pepigen.c:1647 +msgid " Register save millicode" +msgstr " Registerspara millikod" + +#: peigen.c:1650 pepigen.c:1650 +msgid " Register restore millicode" +msgstr " Registeråterställ millikod" + +#: peigen.c:1653 pepigen.c:1653 +msgid " Glue code sequence" +msgstr " Klisterkodsekvens" + +#: peigen.c:1705 pepigen.c:1705 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"PE-filbasomlokaliseringar (tolkat innehåll i .reloc-sektionen)\n" + +#: peigen.c:1735 pepigen.c:1735 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Virtuell adress: %08lx Områdesstorlek %ld (0x%lx) Antal fixar %ld\n" + +#: peigen.c:1748 pepigen.c:1748 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\tomlokalisering %4d avstånd %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1788 pepigen.c:1788 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Karakteristik 0x%x\n" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Okänd speciallänkartyp %d" + +#~ msgid "v850ea architecture" +#~ msgstr "v850ea-arkitektur" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: Sektionen %s är för stor för att stoppa hål med %ld byte i" + +#~ msgid "Error: out of memory" +#~ msgstr "Fel: slut på minne" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "varning: omlokalisering mot borttagen sektion; nollställer" + +#~ msgid "warning: relocation against removed section" +#~ msgstr "varning: omlokalisering mot borttagen sektion" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "lokala symboler i bortkastade sektionen %s" + +#~ msgid "%s: linking abicalls files with non-abicalls files" +#~ msgstr "%s: länkar abicalls-filer med icke-abicalls-filer" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%s: ISA (-mips%d) passar inte med tidigare moduler (-mips%d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%s: ISA (%d) passar inte med tidigare moduler (%d)" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: dynamisk omlokalisering utan spekulationsfixar" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: spekulationsfix mot odefinierad svag symbol" + +#~ msgid "\tThe Import Address Table (difference found)\n" +#~ msgstr "\tImportadresstabellen (skillnad hittad)\n" + +#~ msgid "\t>>> Ran out of IAT members!\n" +#~ msgstr "\t>>> Slut på IAT-medlemmar!\n" + +#~ msgid "\tThe Import Address Table is identical\n" +#~ msgstr "\tImportadresstabellen är identisk\n" + +# Ska vara blanksteg här tror jag +#~ msgid "BFD %sinternal error, aborting at %s line %d\n" +#~ msgstr "Internt BFD %s-fel, avbryter vid %s rad %d\n" + +#~ msgid "GP relative relocation when GP not defined" +#~ msgstr "GP-relativ omlokalisering då GP inte är definierad" + +#~ msgid "%s: ERROR: passes floats in float registers whereas target %s uses integer registers" +#~ msgstr "%s: FEL: skickar flyttal i flyttalsregister där målet %s istället använder heltalsregister" + +#~ msgid "%s: ERROR: passes floats in integer registers whereas target %s uses float registers" +#~ msgstr "%s: FEL: skickar flyttal i heltalsregister där målet %s istället använder flyttalsregister" + +#~ msgid "Warning: input file %s supports interworking, whereas %s does not." +#~ msgstr "Varning: indatafilen %s stöder samverkande, medan %s däremot inte gör det." + +#~ msgid "Warning: input file %s does not support interworking, whereas %s does." +#~ msgstr "Varning: indatafilen %s stöder inte samverkande, medan %s däremot gör det." + +#~ msgid "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" +#~ msgstr "AUX tagndx %ld ttlsiz 0x%lx radnummer %ld nästa %ld" + +#~ msgid "elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = 0x%.8lx%s\n" +#~ msgstr "elf_symbol_from_bfd_symbol 0x%.8lx, namn = %s, symbolnr = %d, flaggor = 0x%.8lx%s\n" + +#~ msgid "Warning: Not setting interwork flag of %s since it has already been specified as non-interworking" +#~ msgstr "Varning: Ställer inte in samverkandeflaggan för %s eftersom den redan har angivits som inte samverkande" + +#~ msgid "Warning: Clearing the interwork flag of %s due to outside request" +#~ msgstr "Varning: Stänger av samverkandeflaggan för %s på grund av utomstående begäran" + +#~ msgid " [APCS-26]" +#~ msgstr " [APCS-26]" + +#~ msgid " [APCS-32]" +#~ msgstr " [APCS-32]" + +#~ msgid "(unknown)" +#~ msgstr "(okänd)" + +# Skumt! +#~ msgid " previously %s in %s" +#~ msgstr " tidigare %s i %s" + +#~ msgid "Symbol `%s' has differing types: %s in %s" +#~ msgstr "Symbolen \"%s\" har olika typer: %s i %s" + +# Alla dessa känns onödiga, borde rapporteras +#~ msgid "ETIR_S_C_STO_GBL: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_GBL: ingen symbol \"%s\"" + +#~ msgid "ETIR_S_C_STO_CA: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_CA: ingen symbol \"%s\"" + +#~ msgid "ETIR_S_C_STO_RB/AB: Not supported" +#~ msgstr "ETIR_S_C_STO_RB/AB: Stöds inte" + +#~ msgid "ETIR_S_C_STO_LP_PSB: Not supported" +#~ msgstr "ETIR_S_C_STO_LP_PSB: Stöds inte" + +#~ msgid "ETIR_S_C_STO_HINT_GBL: not implemented" +#~ msgstr "ETIR_S_C_STO_HINT_GBL: inte implementerat" + +#~ msgid "ETIR_S_C_STO_HINT_PS: not implemented" +#~ msgstr "ETIR_S_C_STO_HINT_PS: inte implementerat" + +#~ msgid "ETIR_S_C_OPR_INSV: Not supported" +#~ msgstr "ETIR_S_C_OPR_INSV: Stöds inte" + +#~ msgid "ETIR_S_C_OPR_USH: Not supported" +#~ msgstr "ETIR_S_C_OPR_USH: Stöds inte" + +#~ msgid "ETIR_S_C_OPR_ROT: Not supported" +#~ msgstr "ETIR_S_C_OPR_ROT: Stöds inte" + +#~ msgid "ETIR_S_C_OPR_REDEF: Not supported" +#~ msgstr "ETIR_S_C_OPR_REDEF: Stöds inte" + +#~ msgid "ETIR_S_C_OPR_DFLIT: Not supported" +#~ msgstr "ETIR_S_C_OPR_DFLIT: Stöds inte" + +#~ msgid "ETIR_S_C_STC_LP: not supported" +#~ msgstr "ETIR_S_C_STC_LP: stöds inte" + +#~ msgid "ETIR_S_C_STC_GBL: not supported" +#~ msgstr "ETIR_S_C_STC_GBL: stöds inte" + +#~ msgid "ETIR_S_C_STC_GCA: not supported" +#~ msgstr "ETIR_S_C_STC_GCA: stöds inte" + +#~ msgid "ETIR_S_C_STC_PS: not supported" +#~ msgstr "ETIR_S_C_STC_PS: stöds inte" + +#~ msgid "Unimplemented STO cmd %d" +#~ msgstr "Oimplementerat STO-kommando %d" + +#~ msgid "TIR_S_C_OPR_ASH incomplete" +#~ msgstr "TIR_S_C_OPR_ASH ofullständigt" + +#~ msgid "TIR_S_C_OPR_USH incomplete" +#~ msgstr "TIR_S_C_OPR_USH ofullständigt" + +#~ msgid "TIR_S_C_OPR_ROT incomplete" +#~ msgstr "TIR_S_C_OPR_ROT ofullständigt" + +#~ msgid "TIR_S_C_OPR_REDEF not supported" +#~ msgstr "TIR_S_C_OPR_REDEF stöds inte" + +#~ msgid "TIR_S_C_OPR_DFLIT not supported" +#~ msgstr "TIR_S_C_OPR_DFLIT stöds inte" + +#~ msgid "TIR_S_C_CTL_DFLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_DFLOC är inte fullständigt implementerat" + +#~ msgid "TIR_S_C_CTL_STLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_STLOC är inte fullständigt implementerat" + +#~ msgid "TIR_S_C_CTL_STKDL not fully implemented" +#~ msgstr "TIR_S_C_CTL_STKDL är inte fulständigt implementerat" + +# This is broken +# +# fprintf (file, +# _("\nThe Import Tables (interpreted %s section contents)\n"), +# section->name); +# fprintf (file, +# _(" vma: Hint Time Forward DLL First\n")); +# fprintf (file, +# _(" Table Stamp Chain Name Thunk\n")); +# +#~ msgid " vma: Hint Time Forward DLL First\n" +#~ msgstr " vma: Tips- Tids- V.bef.- DLL- Första\n" + +#~ msgid " \t\tAddress Address Handler Data Address Mask\n" +#~ msgstr " \t\tadress adress hanterare data adress mask\n" + +#~ msgid "integer" +#~ msgstr "heltal" + +#~ msgid "float" +#~ msgstr "flyttal" + +#~ msgid "soft" +#~ msgstr "mjuk" + +#~ msgid "hard" +#~ msgstr "hård" + +# _bfd_error_handler (_("# Warning: %s %s interworking, whereas %s %s"), +# bfd_get_filename (ibfd), +# in_flags & EF_INTERWORK ? _("supports") : _("does not support"), +# bfd_get_filename (obfd), +# out_flags & EF_INTERWORK ? _("does not") : _("does")); +# +# This is broken +# +# Don't split a sentence like this, use multiple full messages instead +# +#~ msgid "Warning: %s %s interworking, whereas %s %s" +#~ msgstr "Varning: %s %s samverkande, medan %s %s" + +#~ msgid "supports" +#~ msgstr "stöder" + +#~ msgid "does not" +#~ msgstr "inte gör det" + +#~ msgid "does" +#~ msgstr "gör det" + +#~ msgid "%s(%s+0x%lx): cannot find stub entry %s" +#~ msgstr "%s(%s+0x%lx): kan inte hitta stubbstarten %s" + +#~ msgid "%s(%s+0x%lx): cannot relocate %s, recompile with -ffunction-sections" +#~ msgstr "%s(%s+0x%lx): kan inte omlokalisera %s, kompilera om med -ffunction-sections" + +#~ msgid "creating section symbol, name = %s, value = 0x%.8lx, index = %d, section = 0x%.8lx\n" +#~ msgstr "skapar sektionssymbol, namn = %s, värde = 0x%.8lx, index = %d, sektion = 0x%.8lx\n" + +# Hmm +#~ msgid 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zTh+W9HYCRJH%wwVxTrOm?K!nVs`KjbxinMMXR3z?Gc>!1OFe9gtg?ZgW0P1Xm3+$de0^Yui#TsNM<-Uv7AX6|ULOoL{^3SYNfm6`*QjY1YE9A=&;Cgu~Gre(3U z(i3B}iAx%7Qu&UE@rZ3H@@xZOjA;Sm{-r1o+LywF2~CjA(ZVMnV{3v+`t2qmv{~r% d98)^8pbWGWzkING5I*%R_1JJamvTA${{xUUzaszu literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/bfd/po/tr.po b/external/gpl3/gdb/dist/bfd/po/tr.po new file mode 100644 index 000000000000..11630c6ab40f --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/tr.po @@ -0,0 +1,3193 @@ +# translation of bfd-2.14rel030712.tr.po to Turkish +# Copyright (C) 2003 Free Software Foundation, Inc. +# Deniz Akkus Kanca , 2001,2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:53+0930\n" +"PO-Revision-Date: 2003-07-13 22:07+0300\n" +"Last-Translator: Deniz Akkus Kanca \n" +"Language-Team: Turkish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: KBabel 1.0\n" + +#: aout-adobe.c:204 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s: a.out.adobe dosyasında bilinmeyen bölüm türü: %x\n" + +#: aout-cris.c:207 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Geçersiz yer deÄŸiÅŸtirme türü ihraç edilmiÅŸ: %d" + +#: aout-cris.c:251 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s: Geçersiz yer deÄŸiÅŸtirme türü ithal edilmiÅŸ: %d" + +#: aout-cris.c:262 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s: Geçersiz yer deÄŸiÅŸtirme kaydı ithal edilmiÅŸ: %d" + +#: aoutx.h:1295 aoutx.h:1716 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: `%s' bölümü a.out nesne dosya biçeminde gösterilemez" + +#: aoutx.h:1682 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: `%s' sembol bölümü a.out nesne dosyasında gösterilemez" + +#: aoutx.h:1684 +msgid "*unknown*" +msgstr "*bilinmeyen*" + +#: aoutx.h:3776 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: %s'dan %s'ya yeri deÄŸiÅŸtirilebilen baÄŸ desteklenmiyor" + +#: archive.c:1751 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Uyarı: arÅŸiv yazma iÅŸlemi yavaÅŸ: zaman damgası yeniden yazılıyor\n" + +#: archive.c:2014 +msgid "Reading archive file mod timestamp" +msgstr "ArÅŸiv dosyası deÄŸiÅŸim zaman damgası okunuyor" + +#: archive.c:2040 +msgid "Writing updated armap timestamp" +msgstr "GüncellenmiÅŸ armap zaman damgası yazılıyor" + +#: bfd.c:280 +msgid "No error" +msgstr "Hata yok" + +#: bfd.c:281 +msgid "System call error" +msgstr "Sistem çaÄŸrı hatası" + +#: bfd.c:282 +msgid "Invalid bfd target" +msgstr "Geçersiz bfd hedefi" + +#: bfd.c:283 +msgid "File in wrong format" +msgstr "Dosya yanlış biçemde" + +#: bfd.c:284 +msgid "Archive object file in wrong format" +msgstr "ArÅŸiv nesne dosyası yanlış biçemde" + +#: bfd.c:285 +msgid "Invalid operation" +msgstr "Geçersiz iÅŸlem" + +#: bfd.c:286 +msgid "Memory exhausted" +msgstr "Bellek tükendi" + +#: bfd.c:287 +msgid "No symbols" +msgstr "Sembol yok" + +#: bfd.c:288 +msgid "Archive has no index; run ranlib to add one" +msgstr "ArÅŸivin indeksi yok; ranlib çalıştırarak indeks ekleyin" + +#: bfd.c:289 +msgid "No more archived files" +msgstr "BaÅŸka arÅŸivlenmiÅŸ dosya yok" + +#: bfd.c:290 +msgid "Malformed archive" +msgstr "Bozuk arÅŸiv" + +#: bfd.c:291 +msgid "File format not recognized" +msgstr "Dosya biçemi tanınmıyor" + +#: bfd.c:292 +msgid "File format is ambiguous" +msgstr "Dosya biçemi belirsiz" + +#: bfd.c:293 +msgid "Section has no contents" +msgstr "Bölümde içerik yok" + +#: bfd.c:294 +msgid "Nonrepresentable section on output" +msgstr "Çıktıda gösterilemeyen bölüm" + +#: bfd.c:295 +msgid "Symbol needs debug section which does not exist" +msgstr "Sembol, olmayan hata ayıklama bölümünü istiyor" + +#: bfd.c:296 +msgid "Bad value" +msgstr "Geçersiz deÄŸer" + +#: bfd.c:297 +msgid "File truncated" +msgstr "Dosya budandı" + +#: bfd.c:298 +msgid "File too big" +msgstr "Dosya fazla büyük" + +#: bfd.c:299 +msgid "#" +msgstr "#" + +#: bfd.c:687 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s, olumlama baÅŸarısız %s:%d" + +#: bfd.c:703 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %s iç hatası, %s'da, %d satırı, %s içerisinde iÅŸlem durduruldu\n" + +#: bfd.c:707 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %s iç hatası, %s, %d satırında iÅŸlem durduruldu\n" + +#: bfd.c:709 +msgid "Please report this bug.\n" +msgstr "Lütfen bu hatayı bildirin.\n" + +#: bfdwin.c:202 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "eÅŸlenmeyen: veri=%lx eÅŸleÅŸen=%d\n" + +#: bfdwin.c:205 +msgid "not mapping: env var not set\n" +msgstr "eÅŸlenmeyen: çevre deÄŸiÅŸkeni atanmamış\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Uyarı: `%s' bölümü çok büyük (negatif) dosya göreli konumu 0x%lx'e yazılıyor." + +#: coff-a29k.c:120 +msgid "Missing IHCONST" +msgstr "IHCONST yok" + +#: coff-a29k.c:181 +msgid "Missing IHIHALF" +msgstr "IHIHALF yok" + +#: coff-a29k.c:213 coff-or32.c:236 +msgid "Unrecognized reloc" +msgstr "Tanınmayan yer deÄŸiÅŸtirme" + +#: coff-a29k.c:409 +msgid "missing IHCONST reloc" +msgstr "eksik IHCONST yer deÄŸiÅŸtirmesi" + +#: coff-a29k.c:499 +msgid "missing IHIHALF reloc" +msgstr "eksik IHIHALF yer deÄŸiÅŸtirmesi" + +#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397 +msgid "GP relative relocation used when GP not defined" +msgstr "GP tanımlanmamışken GP göreli yer deÄŸiÅŸtirmesi kullanılmış" + +#: coff-alpha.c:1488 +msgid "using multiple gp values" +msgstr "birden fazla gp deÄŸeri kullanılıyor" + +#: coff-arm.c:1066 elf32-arm.h:294 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "%1$s: `%3$s' için THUMB birleÅŸtiricisi '%2$s' bulunamadı " + +#: coff-arm.c:1096 elf32-arm.h:329 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "%1$s: `%3$s' için ARM birleÅŸtiricisi '%2$s' bulunamadı" + +#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "%s(%s): uyarı: beraber çalışma kipi etkin deÄŸil." + +#: coff-arm.c:1398 elf32-arm.h:1002 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr " ilk ortaya çıkış: %s: thumb'a arm'dan çaÄŸrı" + +#: coff-arm.c:1493 elf32-arm.h:895 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr " ilk ortaya çıkış: %s: arm'a thumb'dan çaÄŸrı" + +#: coff-arm.c:1496 +msgid " consider relinking with --support-old-code enabled" +msgstr " --support-old-code seçeneÄŸi ile yeniden baÄŸlamayı deneyin" + +#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "%1$s: `%3$s' bölümünde geçersiz yer deÄŸiÅŸtirme adresi 0x%2$lx" + +#: coff-arm.c:2132 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s: yer deÄŸiÅŸtirmede geçersiz sembol indeksi: %d" + +#: coff-arm.c:2265 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "Hata: %s APCS-%d için derlenmiÅŸ, fakat %s APCS-%d için derlenmiÅŸ" + +#: coff-arm.c:2280 elf32-arm.h:2328 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "" +"Hata: %s kayan sayıları kayan sayı yazmaçlarında geçiriyor, \n" +" fakat %s tamsayı yazmaçlarında geçiriyor" + +#: coff-arm.c:2283 elf32-arm.h:2333 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "" +"Hata: %s kayan sayıları tamsayı yazmaçlarında geçiriyor, \n" +" fakat %s kayan sayı yazmaçlarında geçiriyor" + +#: coff-arm.c:2298 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "HATA: %s yerden bağımsız kod olarak derlendi, fakat hedef %s yere bağımlı" + +#: coff-arm.c:2301 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "HATA: %s yere bağımlı kod olarak derlendi, fakat hedef %s yerden bağımsız" + +#: coff-arm.c:2330 elf32-arm.h:2405 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "Uyarı: %s girdi dosyası beraber çalışmayı destekliyor, fakat %s desteklemiyor." + +#: coff-arm.c:2333 elf32-arm.h:2412 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "Uyarı: %s girdi dosyası beraber çalışmayı desteklemiyor, fakat %s destekliyor." + +#: coff-arm.c:2360 +#, c-format +msgid "private flags = %x:" +msgstr "özel bayraklar = %x:" + +#: coff-arm.c:2368 elf32-arm.h:2467 +msgid " [floats passed in float registers]" +msgstr " [kayan sayılar kayan yazmaçlarda geçirildi]" + +#: coff-arm.c:2370 +msgid " [floats passed in integer registers]" +msgstr " [kayan sayılar tamsayı yazmaçlarda geçirildi]" + +#: coff-arm.c:2373 elf32-arm.h:2470 +msgid " [position independent]" +msgstr " [yerden bağımsız]" + +#: coff-arm.c:2375 +msgid " [absolute position]" +msgstr " [yere bağımlı]" + +#: coff-arm.c:2379 +msgid " [interworking flag not initialised]" +msgstr " [beraber çalışma bayrağına öndeÄŸer atanmamış]" + +#: coff-arm.c:2381 +msgid " [interworking supported]" +msgstr " [beraber çalışma destekleniyor]" + +#: coff-arm.c:2383 +msgid " [interworking not supported]" +msgstr " [beraber çalışma desteklenmiyor]" + +#: coff-arm.c:2431 elf32-arm.h:2150 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "Uyarı: %s beraber çalışma bayrağı atanmadı, çünkü beraber çalışma olmayacağı önceden belirtilmiÅŸ" + +#: coff-arm.c:2435 elf32-arm.h:2154 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "Uyarı: %s beraber çalışma bayrağı dış istek üzerine temizlendi" + +#: coff-h8300.c:1096 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "%s çıktısı kullanılırken R_MEM_INDIRECT yerdeÄŸiÅŸtirmesi kullanılamıyor" + +#: coff-i960.c:137 coff-i960.c:486 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "COFF olmayan sembol için belirsiz çaÄŸrı davranışı" + +#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783 +msgid "unsupported reloc type" +msgstr "desteklenmeyen yer deÄŸiÅŸtirme türü" + +#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554 +msgid "GP relative relocation when _gp not defined" +msgstr "_gp tanımsız iken GP göreli yer deÄŸiÅŸtirmesi" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2431 +msgid "reloc against unsupported section" +msgstr "desteklenmeyen bölümde yer deÄŸiÅŸtirme" + +#: coff-mips.c:2439 +msgid "reloc not properly aligned" +msgstr "yer deÄŸiÅŸtirme doÄŸru hizalanmamış" + +#: coff-rs6000.c:2790 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: desteklenmeyen yükleyici yerdeÄŸiÅŸimi 0x%02x" + +#: coff-rs6000.c:2883 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: 0x%x'da TOC girdisi olmayan `%s' sembolüne TOC yerdeÄŸiÅŸimi" + +#: coff-rs6000.c:3616 coff64-rs6000.c:2109 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "%s: `%s' sembolünde bilinmeyen %d var" + +#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Bilinmeyen yer deÄŸiÅŸtirme türü 0x%x" + +#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: uyarı: yer deÄŸiÅŸtirmelerde geçersiz sembol indeksi %ld" + +#: coff-w65.c:364 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "yer deÄŸiÅŸtirme %s yoksayıldı\n" + +#: coffcode.h:1108 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s): Bölüm bayrağı %s (0x%x) yoksayıldı" + +#: coffcode.h:2214 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Tanınmayan TI COFF hedef kimliÄŸi '0x%x'" + +#: coffcode.h:4437 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s: uyarı: satır numaralarında geçersiz sembol indeksi %ld" + +#: coffcode.h:4451 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s: uyarı: `%s' için tekrarlanmış satır numarası bilgisi" + +#: coffcode.h:4805 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%1$s: %3$s sembolü `%4$s' için bilinmeyen saklama sınıfı %2$d" + +#: coffcode.h:4938 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "uyarı: %s: `%s' yerel sembolünün bölümü yok" + +#: coffcode.h:5083 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%1$s: 0x%3$lx adresinde geçersiz yer deÄŸiÅŸtirme türü %2$d" + +#: coffgen.c:1666 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s: geçersiz dizge tablo boyu %lu" + +#: cofflink.c:538 elflink.h:1276 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "Uyarı: %4$s içerisinde `%1$s' sembolünün türü %2$d'den %3$d'e deÄŸiÅŸtirildi" + +#: cofflink.c:2328 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "%s: `%s' bölümünde yer deÄŸiÅŸtirmeler mevcut, fakat içi boÅŸ" + +#: cofflink.c:2671 coffswap.h:890 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: yer deÄŸiÅŸtirme taÅŸması: 0x%lx > 0xffff" + +#: cofflink.c:2680 coffswap.h:876 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: uyarı: %s: satır numarası taÅŸması: 0x%lx > 0xffff" + +#: cpu-arm.c:196 cpu-arm.c:206 +#, c-format +msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale" +msgstr "Hata: %s EP9312 için derlenmiÅŸ, fakat %s XScale için derlenmiÅŸ" + +#: cpu-arm.c:344 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "uyarı: %2$s içinde %1$s bölümünün içeriÄŸi güncellenemedi" + +#: dwarf2.c:380 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Dwarf Hatası: .debug_str bölümü bulunamadı." + +#: dwarf2.c:397 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "" +"Dwarf Hatası: DW_FORM_strp göreli konumu (%lu) .debug_str boyutundan (%lu) \n" +" daha büyük veya eÅŸit." + +#: dwarf2.c:541 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Dwarf Hatası: .debug_abbrev bölümü bulunamadı." + +#: dwarf2.c:556 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "" +"Dwarf Hatası: Kısaltma göreli konumu (%lu) kısaltma boyutundan (%lu) \n" +" daha büyük veya eÅŸit." + +#: dwarf2.c:756 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Dwarf Hatası: Geçersiz veya desteklenmeyen FORM deÄŸeri: %u." + +#: dwarf2.c:933 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Dwarf Hatası: bozulmuÅŸ satır numarası bölümü (geçersiz dosya numarası)." + +#: dwarf2.c:1032 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Dwarf Hatası: .debug_line bölümü bulunamadı." + +#: dwarf2.c:1049 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "" +"Dwarf Hatası: Satır göreli konumu (%lu) satır boyutundan (%lu)\n" +" daha büyük veya eÅŸit." + +#: dwarf2.c:1255 +msgid "Dwarf Error: mangled line number section." +msgstr "Dwarf Hatası: bozuk satır numarası bölümü." + +#: dwarf2.c:1470 dwarf2.c:1620 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Dwarf Hatası: Kısaltma numarası %u bulunamadı." + +#: dwarf2.c:1581 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Dwarf Hatası: dwarf sürümü '%u' bulundu, bu okuyucu yalnızca sürüm 2 bilgisini anlayabiliyor." + +#: dwarf2.c:1588 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Dwarf Hatası: adres boyu '%u' bulundu, bu okuyucu '%u'dan daha büyük boyları okuyamıyor." + +#: dwarf2.c:1611 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Dwarf Hatası: Geçersiz kısaltma numarası: %u." + +#: ecoff.c:1339 +#, c-format +msgid "Unknown basic type %d" +msgstr "Bilinmeyen temel tür %d" + +#: ecoff.c:1599 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Son+1 sembolü: %ld" + +#: ecoff.c:1606 ecoff.c:1609 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Ä°lk sembol: %ld" + +#: ecoff.c:1621 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Son+1 sembolü: %-7ld Tür: %s" + +#: ecoff.c:1628 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Yerel sembol: %ld" + +#: ecoff.c:1636 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" yapı; Son+1 sembolü: %ld" + +#: ecoff.c:1641 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" birleÅŸim; Son+1 sembolü: %ld" + +#: ecoff.c:1646 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" enum; Son+1 sembolü: %ld" + +#: ecoff.c:1652 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Tür: %s" + +#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%1$s: uyarı: %3$s bölümünden `%2$s' sembolüne çözümlenemeyen yer deÄŸiÅŸimi" + +#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812 +#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815 +#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699 +#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510 +#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976 +#: elf64-mmix.c:1332 +msgid "internal error: out of range error" +msgstr "iç hata: kapsam dışı hatası" + +#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816 +#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819 +#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287 +#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440 +#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452 +msgid "internal error: unsupported relocation error" +msgstr "iç hata: desteklenmeyen yer deÄŸiÅŸim hatası" + +#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578 +#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313 +msgid "internal error: dangerous error" +msgstr "iç hata: ölümcül hata" + +#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824 +#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827 +#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711 +#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522 +#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988 +#: elf64-mmix.c:1344 +msgid "internal error: unknown error" +msgstr "iç hata: bilinmeyen hata" + +#: elf.c:372 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "%1$s: `%4$s' bölümünde geçersiz dizge göreli konumu %2$u >= %3$lu" + +#: elf.c:624 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s: geçersiz SHT_GROUP girdisi" + +#: elf.c:695 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s: %s bölümünde grup bilgisi yok" + +#: elf.c:1055 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Yazılım BaÅŸlığı:\n" + +#: elf.c:1106 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Dinamik Bölüm:\n" + +#: elf.c:1235 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Sürüm tanımları:\n" + +#: elf.c:1258 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Sürüm Referansları:\n" + +#: elf.c:1263 +#, c-format +msgid " required from %s:\n" +msgstr " %s'den isteniyor:\n" + +#: elf.c:1944 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "%1$s: yerdeÄŸiÅŸim bölümü %3$s (indeks %4$u) için geçersiz baÄŸ %2$lu" + +#: elf.c:3686 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s: Yazılım baÅŸlıkları için yeterli yer yok (%u ayrıldı, %u gerekli)" + +#: elf.c:3791 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s: yazılım baÅŸlıkları için gerekli yer yok, -N ile baÄŸlamayı deneyin" + +#: elf.c:3922 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "Hata: Parçadaki (%s) ilk bölüm 0x%x'de, parça ise 0x%x'de baÅŸlıyor" + +#: elf.c:4242 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s: uyarı: ayrılmış `%s' bölümü parça içinde deÄŸil" + +#: elf.c:4566 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s: `%s' sembolü gerekli fakat mevcut deÄŸil" + +#: elf.c:4854 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s: uyarı: BoÅŸ yüklenebilir parça bulundu, bu isteyerek mi yapılıyor?\n" + +#: elf.c:5485 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "'%2$s' bölümünden '%1$s' sembolü için eÅŸdeÄŸer çıktı bölümü bulunamadı" + +#: elf.c:6298 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s: desteklenmeyen yerdeÄŸiÅŸim türü %s" + +#: elf32-arm.h:1228 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "%s: Uyarı: Arm BLX iÅŸlemi Arm iÅŸlevi '%s' hedefliyor." + +#: elf32-arm.h:1424 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%s: Uyarı: Thumb BLX iÅŸlemi thumb iÅŸlevi '%s'ı hedefliyor." + +#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx): SEC_MERGE bölümüne %s yerdeÄŸiÅŸimi" + +#: elf32-arm.h:2012 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "%1$s: uyarı: %4$s bölümünden `%3$s' sembolüne çözümlenemeyen %2$d yer deÄŸiÅŸimi" + +#: elf32-arm.h:2202 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "Uyarı: %2$s'deki beraber çalışmaz kod ona baÄŸlandığı için %1$s'nin beraber çalışma bayrağı temizlendi" + +#: elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "Hata: %s EABI sürüm %d için derlenmiÅŸ, fakat %s %d sürümü için derlenmiÅŸ" + +#: elf32-arm.h:2316 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "HATA: %s, APCS-%d için derlenmiÅŸ fakat hedef %s APCS-%d kullanıyor" + +#: elf32-arm.h:2344 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s does not" +msgstr "Hata: %s VFP iÅŸlemi kullanıyor, fakat %s kullanmıyor" + +#: elf32-arm.h:2349 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s does not" +msgstr "Hata: %s FPA iÅŸlemi kullanıyor, fakat %s kullanmıyor" + +#: elf32-arm.h:2360 elf32-arm.h:2365 +#, c-format +msgid "ERROR: %s uses Maverick instructions, whereas %s does not" +msgstr "Hata: %s Maverick iÅŸlemi kullanıyor, fakat %s kullanmıyor" + +#: elf32-arm.h:2385 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "" +"Hata: %s yazılımda kayan sayı kullanıyor,\n" +" fakat %s donanımda kayan sayı kullanıyor" + +#: elf32-arm.h:2390 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "" +"Hata: %s donanımda kayan sayı kullanıyor,\n" +" fakat %s yazılımda kayan sayı kullanıyor" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9238 +#, c-format +msgid "private flags = %lx:" +msgstr "özel bayraklar = %lx:" + +#: elf32-arm.h:2452 +msgid " [interworking enabled]" +msgstr " [beraber çalışma etkinleÅŸtirilmiÅŸ]" + +#: elf32-arm.h:2460 +msgid " [VFP float format]" +msgstr " [VFP kayan nokta biçemi]" + +#: elf32-arm.h:2462 +msgid " [Maverick float format]" +msgstr " [Maverick kayan nokta biçemi]" + +#: elf32-arm.h:2464 +msgid " [FPA float format]" +msgstr " [FPA kayan nokta biçemi]" + +#: elf32-arm.h:2473 +msgid " [new ABI]" +msgstr " [yeni ABI]" + +#: elf32-arm.h:2476 +msgid " [old ABI]" +msgstr " [eski ABI]" + +#: elf32-arm.h:2479 +msgid " [software FP]" +msgstr " [yazılım FP]" + +#: elf32-arm.h:2488 +msgid " [Version1 EABI]" +msgstr " [Sürüm1 EABI]" + +#: elf32-arm.h:2491 elf32-arm.h:2502 +msgid " [sorted symbol table]" +msgstr " [sıralanmış sembol tablosu]" + +#: elf32-arm.h:2493 elf32-arm.h:2504 +msgid " [unsorted symbol table]" +msgstr " [sıralanmamış sembol tablosu]" + +#: elf32-arm.h:2499 +msgid " [Version2 EABI]" +msgstr " [Sürüm2 EABI]" + +#: elf32-arm.h:2507 +msgid " [dynamic symbols use segment index]" +msgstr " [dinamik semboller bölüm indeksini kullanıyor]" + +#: elf32-arm.h:2510 +msgid " [mapping symbols precede others]" +msgstr " [eÅŸleÅŸme sembolleri diÄŸerlerinden önceliklidir]" + +#: elf32-arm.h:2517 +msgid " " +msgstr " " + +#: elf32-arm.h:2524 +msgid " [relocatable executable]" +msgstr " [yer deÄŸiÅŸtirebilir uygulama]" + +#: elf32-arm.h:2527 +msgid " [has entry point]" +msgstr " [girdi noktası var]" + +#: elf32-arm.h:2532 +msgid "" +msgstr "" + +#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823 +#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518 +#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984 +#: elf64-mmix.c:1340 +msgid "internal error: dangerous relocation" +msgstr "iç hata: tehlikeli yer deÄŸiÅŸim" + +#: elf32-cris.c:931 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%1$s: uyarı: %4$s bölümünden `%3$s' sembolüne çözümlenemeyen %2$s yer deÄŸiÅŸimi" + +#: elf32-cris.c:993 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "%1$s: %4$s bölümünden `%3$s' sembolüne %2$s yer deÄŸiÅŸimi için PLT veya GOT yok" + +#: elf32-cris.c:996 elf32-cris.c:1122 +msgid "[whose name is lost]" +msgstr "[adı kaybolmuÅŸ]" + +#: elf32-cris.c:1111 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "" +"%1$s: %4$s bölümünden yerel sembol sıfır olmayan %3$d eklemesi ile\n" +" %2$s yerdeÄŸiÅŸimi" + +#: elf32-cris.c:1118 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "%1$s: %5$s bölümünden `%4$s' sembolüne sıfır olmayan %3$d eklemesi ile %2$s yerdeÄŸiÅŸimi" + +#: elf32-cris.c:1143 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "%1$s: %4$s bölümünden %3$s evrensel sembolü için %2$s yerdeÄŸiÅŸimi yapılamaz" + +#: elf32-cris.c:1158 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "%1$s: `%3$s' bölümünde %2$s yer deÄŸiÅŸtirmesi mevcut, fakat GOT oluÅŸturulmamış" + +#: elf32-cris.c:1277 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s: İç tutarsızlık; %s yerdeÄŸiÅŸim bölümü yok" + +#: elf32-cris.c:2500 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%s, %s bölümü:\n" +" %s yer deÄŸiÅŸimi paylaşımlı nesne oluÅŸtururken kullanılamaz;\n" +" -fPIC ile yeniden derleyin" + +#: elf32-cris.c:2978 +msgid " [symbols have a _ prefix]" +msgstr " [semboller _ önekine sahip]" + +#: elf32-cris.c:3017 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s: _-önekli sembolleri kullanıyor, fakat dosyaya öneksiz sembolleri yazıyor" + +#: elf32-cris.c:3018 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s: öneksiz sembolleri kullanıyor, fakat dosyaya _-önekli sembolleri yazıyor" + +#: elf32-frv.c:1223 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: %s ile derlendi ve normal derlenmiÅŸ modüllerle baÄŸlandı" + +#: elf32-frv.c:1273 elf32-iq2000.c:895 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: %s ile derlendi ve %s ile derlenmiÅŸ modüllerle baÄŸlandı" + +#: elf32-frv.c:1285 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: önceki modüllerden farklı bilinmeyen e_flags (0x%lx) alanları kullanılıyor (0x%lx)" + +#: elf32-frv.c:1321 elf32-iq2000.c:933 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "özel bayraklar = 0x%lx:" + +#: elf32-gen.c:83 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "%s: Normal ELF'de yerdeÄŸiÅŸimler (EM: %d)" + +#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: koçan giriÅŸi %s oluÅŸturulamadı" + +#: elf32-hppa.c:957 elf32-hppa.c:3538 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%s(%s+0x%lx): %s'e ulaşılamadı, -ffunction-sections ile derleyin" + +#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%s: %s yer deÄŸiÅŸimi paylaşımlı nesne oluÅŸturulurken kullanılamaz; -fPIC ile yeniden derleyin" + +#: elf32-hppa.c:1360 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "%s: %s yer deÄŸiÅŸimi paylaşımlı nesne oluÅŸtururken kullanılamaz; -fPIC ile yeniden derleyin" + +#: elf32-hppa.c:1553 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "%s için yer deÄŸiÅŸtirme bölümü bulunamadı" + +#: elf32-hppa.c:2828 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "%s: birden fazla ihraç koçanı %s" + +#: elf32-hppa.c:3416 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx): %s düzeltiliyor" + +#: elf32-hppa.c:4039 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "%1$s(%2$s+0x%3$lx): %5$s için %4$s iÅŸlenemedi" + +#: elf32-hppa.c:4357 +msgid ".got section not immediately after .plt section" +msgstr ".got bölümü .plt bölümünün hemen arkasında deÄŸil" + +#: elf32-i386.c:326 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s: geçersiz yer deÄŸiÅŸim türü %d" + +#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637 +#: elf64-s390.c:943 elf64-x86-64.c:650 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s: geçersiz sembol indeksi: %d" + +#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011 +#: elf64-s390.c:1129 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "%s: `%s'a hem normal, hem de dal yerel sembolü olarak eriÅŸildi" + +#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243 +#: elf64-x86-64.c:886 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s: geçersiz yerdeÄŸiÅŸim bölümü adı `%s'" + +#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879 +#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664 +#: elf64-x86-64.c:2452 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%s(%s+0x%lx): `%s' sembolüne çözümlenemeyen yer deÄŸiÅŸimi" + +#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068 +#: elf64-x86-64.c:2490 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "%s(%s+0x%lx): %s'e yer deÄŸiÅŸimi: %d hatası" + +#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "ip2k esneticisi: tamamen eÅŸleÅŸen yerdeÄŸiÅŸim bilgisi olmadan tabloyu deÄŸiÅŸtirir." + +#: elf32-ip2k.c:588 elf32-ip2k.c:767 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "ip2k esneticisi: deÄŸiÅŸiklik tablosu baÅŸlığı bozuk." + +#: elf32-ip2k.c:1395 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k baÄŸlayıcısı: 0x%08lx adresinde sayfa iÅŸlemi eksik (hedef = 0x%08lx)." + +#: elf32-ip2k.c:1409 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "ip2k baÄŸlayıcısı: 0x%08lx adresinde gereksiz sayfa iÅŸlemi (hedef = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1593 +msgid "unsupported relocation between data/insn address spaces" +msgstr "veri/iÅŸlem adres yerleri arasında desteklenmeyen yerdeÄŸiÅŸim" + +#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072 +#: elfxx-mips.c:9195 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%1$s: önceki modüllerden (0x%3$lx) farklı e_flags (0x%2$lx) alanları kullanılıyor" + +#: elf32-m32r.c:930 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "_SDA_BASE_ tanımlanmamış iken SDA yer deÄŸiÅŸimi" + +#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958 +#: elf64-ia64.c:3958 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: bilinmeyen yer deÄŸiÅŸim türü %d" + +#: elf32-m32r.c:1226 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%1$s: Bir %3$s yer deÄŸiÅŸiminin hedefi (%2$s) yanlış bölümde (%4$s)" + +#: elf32-m32r.c:1952 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "%s: Önceki modüllerle iÅŸlem uyuÅŸmazlığı" + +#: elf32-m32r.c:1975 +#, c-format +msgid "private flags = %lx" +msgstr "özel bayraklar = %lx" + +#: elf32-m32r.c:1980 +msgid ": m32r instructions" +msgstr ": m32r iÅŸlemleri" + +#: elf32-m32r.c:1981 +msgid ": m32rx instructions" +msgstr ": m32rx iÅŸlemleri" + +#: elf32-m68hc1x.c:1217 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Uzak sembol `%s''ye yanlış bir yerdeÄŸiÅŸim ile referans yanlış iÅŸlemeye yol açabilir." + +#: elf32-m68hc1x.c:1240 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "saklanmış adres [%lx:%04lx] (%lx) ÅŸimdiki saklanmış adres [%lx:%04lx] (%lx) ile aynı saklama bankında deÄŸil" + +#: elf32-m68hc1x.c:1259 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "%3$04lx normal adresinde saklanmış adres [%1$lx:%2$04lx]'e referans var" + +#: elf32-m68hc1x.c:1396 +#, c-format +msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%s: 16-bit tamsayı için derlenmiÅŸ (-mshort) dosyalar, 32 bit tamsayı için derlenmiÅŸ baÅŸka dosyalarla baÄŸlanıyor" + +#: elf32-m68hc1x.c:1404 +#, c-format +msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%s: 32-bit double (-fshort-double) için derlenmiÅŸ dosyalar 64-bit double için derlenmiÅŸ dosyalarla baÄŸlanıyor" + +#: elf32-m68hc1x.c:1414 +#, c-format +msgid "%s: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%s: HCS12 için derlenmiÅŸ dosyalar HC12 için derlenmiÅŸ dosyalarla baÄŸlanıyor" + +#: elf32-m68hc1x.c:1462 +msgid "[abi=32-bit int, " +msgstr "[abi=32-bit int, " + +#: elf32-m68hc1x.c:1464 +msgid "[abi=16-bit int, " +msgstr "[abi=16-bit int, " + +#: elf32-m68hc1x.c:1467 +msgid "64-bit double, " +msgstr "64-bit double, " + +#: elf32-m68hc1x.c:1469 +msgid "32-bit double, " +msgstr "32-bit double, " + +#: elf32-m68hc1x.c:1472 +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1474 +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1476 +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1479 +msgid " [memory=bank-model]" +msgstr " [bellek=bank türü]" + +#: elf32-m68hc1x.c:1481 +msgid " [memory=flat]" +msgstr " [bellek=düz]" + +#: elf32-m68k.c:400 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:403 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:353 elf32-mcore.c:456 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "%s: %s (%d) yer deÄŸiÅŸimi henüz desteklenmiyor.\n" + +#: elf32-mcore.c:441 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s: Bilinmeyen yer deÄŸiÅŸim türü %d\n" + +#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "32 bitlik gp göreceli yer deÄŸiÅŸim bir dış sembol için yapılıyor" + +#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "mips16 nesnelerini %s biçemine baÄŸlamak desteklenmiyor" + +#: elf32-ppc.c:2056 +#, c-format +msgid "generic linker can't handle %s" +msgstr "jenerik baÄŸlayıcı %s desteklemiyor" + +#: elf32-ppc.c:2138 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%s: -mrelocatable ile derlendi ve normal derlenmiÅŸ modüllerle baÄŸlandı" + +#: elf32-ppc.c:2147 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%s: normal derlendi ve -mrelocatable ile derlenmiÅŸ modüllere baÄŸlandı" + +#: elf32-ppc.c:3413 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s: %s yerdeÄŸiÅŸimi paylaşımlı nesne oluÅŸturulurken kullanılamaz" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3619 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against local symbol" +msgstr "%s(%s+0x%lx): %s yerel sembole yerdeÄŸiÅŸimi" + +#: elf32-ppc.c:4862 elf64-ppc.c:7789 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%1$s: %3$s sembolü için bilinmeyen %2$d türünde yerdeÄŸiÅŸimi" + +#: elf32-ppc.c:5113 +#, c-format +msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%1$s(%2$s+0x%3$lx): %5$s'ye yerdeÄŸiÅŸimde `%4$s'de sıfır olmayan ekleme" + +#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484 +#, c-format +msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%1$s: %3$s yerdeÄŸiÅŸiminin hedefi (%2$s) yanlış çıktı bölümünde (%4$s)" + +#: elf32-ppc.c:5539 +#, c-format +msgid "%s: relocation %s is not yet supported for symbol %s." +msgstr "%s: %s yerdeÄŸiÅŸimi %s sembolü için henüz desteklenmiyor." + +#: elf32-ppc.c:5594 elf64-ppc.c:8461 +#, c-format +msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%1$s(%2$s+0x%3$lx): `%5$s' sembolüne çözümlenemeyen yer deÄŸiÅŸimi %4$s" + +#: elf32-ppc.c:5644 elf64-ppc.c:8507 +#, c-format +msgid "%s(%s+0x%lx): %s reloc against `%s': error %d" +msgstr "%1$s(%2$s+0x%3$lx): %5$s'e %4$s yer deÄŸiÅŸimi: %6$d hatası" + +#: elf32-ppc.c:5888 +#, c-format +msgid "corrupt or empty %s section in %s" +msgstr "%2$s içinde bozuk veya boÅŸ %1$s bölümü" + +#: elf32-ppc.c:5895 +#, c-format +msgid "unable to read in %s section from %s" +msgstr "%s bölümü %s'den okunamadı" + +#: elf32-ppc.c:5901 +#, c-format +msgid "corrupt %s section in %s" +msgstr "%2$s içinde bozuk %1$s bölümü" + +#: elf32-ppc.c:5944 +#, c-format +msgid "warning: unable to set size of %s section in %s" +msgstr "uyarı: %2$s içinde %1$s bölümünün boyu atanamadı" + +#: elf32-ppc.c:5994 +msgid "failed to allocate space for new APUinfo section." +msgstr "yeni APUinfo bölümü için yer ayrılamadı." + +#: elf32-ppc.c:6013 +msgid "failed to compute new APUinfo section." +msgstr "yeni APUinfo bölümü hesaplanamadı." + +#: elf32-ppc.c:6016 +msgid "failed to install new APUinfo section." +msgstr "yeni APUinfo bölümü kurulamadı." + +#: elf32-s390.c:2256 elf64-s390.c:2226 +#, c-format +msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%s(%s+0x%lx): TLS yerdeÄŸiÅŸimi %s için geçersiz iÅŸlem" + +#: elf32-sh.c:2103 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s: 0x%lx: uyarı: hatalı R_SH_USES göreli konumu" + +#: elf32-sh.c:2115 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s: 0x%lx: uyarı: R_SH_USES bilinmeyen insn 0x%x'ı imliyor" + +#: elf32-sh.c:2132 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s: 0x%lx: uyarı: hatalı R_SH_USES yükleme göreli konumu" + +#: elf32-sh.c:2147 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s: 0x%lx: uyarı: beklenen yerdeÄŸiÅŸim bulunamadı" + +#: elf32-sh.c:2175 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s: 0x%lx: uyarı: beklenmeyen bölümde sembol" + +#: elf32-sh.c:2300 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s: 0x%lx: uyarı: beklenen COUNT yerdeÄŸiÅŸimi bulunamadı" + +#: elf32-sh.c:2309 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s: 0x%lx: uyarı: hatalı sayım" + +#: elf32-sh.c:2712 elf32-sh.c:3088 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%s: 0x%lx: ölümcül: gevÅŸetilirken yerdeÄŸiÅŸim taÅŸması" + +#: elf32-sh.c:4654 elf64-sh64.c:1585 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Yerel sembolde STO_SH5_ISA32 desteklenmiyor" + +#: elf32-sh.c:4809 +#, c-format +msgid "%s: unresolvable relocation against symbol `%s' from %s section" +msgstr "%1$s: %3$s bölümünden `%2$s' sembolüne çözümlenemeyen yer deÄŸiÅŸimi" + +#: elf32-sh.c:4881 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%s: 0x%lx: ölümcül: gevÅŸetme destek yerdeÄŸiÅŸimi için hizalanmamış dal" + +#: elf32-sh.c:6627 elf64-alpha.c:4848 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "%s: TLS yerel çalıştırma kodu paylaşımlı nesnelere baÄŸlanamaz" + +#: elf32-sh64.c:221 elf64-sh64.c:2407 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: 32 bitlik sistem için derlenmiÅŸ ve %s 64 bit" + +#: elf32-sh64.c:224 elf64-sh64.c:2410 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: 64 bitlik sistem için derlenmiÅŸ ve %s 32 bit" + +#: elf32-sh64.c:226 elf64-sh64.c:2412 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: nesne boyu hedef %s'nin boyuyla eÅŸleÅŸmiyor" + +#: elf32-sh64.c:461 elf64-sh64.c:2990 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: girdide veri etiketi sembolüne rastlandı" + +#: elf32-sh64.c:544 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB uyumsuzluÄŸu: SHmedia adresi (bit 0 == 1)" + +#: elf32-sh64.c:547 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA uyumsuzluÄŸu: SHcompact adresi (bit 0 == 0)" + +#: elf32-sh64.c:565 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: GAS hatası: R_SH_PT_16 içeren PTB yönergesi beklenmiyordu" + +#: elf32-sh64.c:614 elf64-sh64.c:1748 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%1$s: %3$08x ve %4$08x yerdeÄŸiÅŸtirmesinde hizalanmamış yer deÄŸiÅŸtirme türü %2$d\n" + +#: elf32-sh64.c:698 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: eklenen .cranges girdileri yazılamadı" + +#: elf32-sh64.c:760 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: sıralanmış .cranges girdileri yazılamadı" + +#: elf32-sparc.c:2521 elf64-sparc.c:2314 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "%s: acaba -fPIC olmaksızın mı derlenmiÅŸ?" + +#: elf32-sparc.c:3348 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s: 64 bitlik sistem için derlenmiÅŸ ve hedef 32 bit" + +#: elf32-sparc.c:3362 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s: küçük sonlu dosyalar büyük sonlu dosyalarla baÄŸlanıyor" + +#: elf32-v850.c:753 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "`%s' deÄŸiÅŸkeni birden fazla küçük veri sahasını kapsayamaz" + +#: elf32-v850.c:756 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "`%s' deÄŸiÅŸkeni küçük, sıfır ve ufak veri sahalarından yalnız birinde olabilir" + +#: elf32-v850.c:759 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "`%s' deÄŸiÅŸkeni aynı anda hem küçük hem sıfır veri sahalarında bulunamaz" + +#: elf32-v850.c:762 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "`%s' deÄŸiÅŸkeni aynı anda hem küçük hem ufak veri sahalarında bulunamaz" + +#: elf32-v850.c:765 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "`%s' deÄŸiÅŸkeni aynı anda hem sıfır hem ufak veri sahalarında bulunamaz" + +#: elf32-v850.c:1144 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "önceki HI16 yerdeÄŸiÅŸimi BULUNAMADI\n" + +#: elf32-v850.c:1789 +msgid "could not locate special linker symbol __gp" +msgstr "özel baÄŸlayıcı sembolü __gp bulunamadı" + +#: elf32-v850.c:1793 +msgid "could not locate special linker symbol __ep" +msgstr "özel baÄŸlayıcı sembolü __ep bulunamadı" + +#: elf32-v850.c:1797 +msgid "could not locate special linker symbol __ctbp" +msgstr "özel baÄŸlayıcı sembolü __ctbp bulunamadı" + +#: elf32-v850.c:1963 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s: Önceki modüllerle platform uyumsuzluÄŸu" + +#: elf32-v850.c:1983 +#, c-format +msgid "private flags = %lx: " +msgstr "özel bayraklar = %lx:" + +#: elf32-v850.c:1988 +msgid "v850 architecture" +msgstr "v850 platformu" + +#: elf32-v850.c:1989 +msgid "v850e architecture" +msgstr "v850e platformu" + +#: elf32-vax.c:549 +msgid " [nonpic]" +msgstr " [nonpic]" + +#: elf32-vax.c:552 +msgid " [d-float]" +msgstr " [d-float]" + +#: elf32-vax.c:555 +msgid " [g-float]" +msgstr " [g-float]" + +#: elf32-vax.c:663 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%1$s: uyarı: `%3$s'ye GOT %2$ld eklentisi bir önceki %4$ld GOT eklentisiyle eÅŸleÅŸmiyor" + +#: elf32-vax.c:1667 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%1$s: uyarı: %4$s bölümünden `%3$s' sembolüne PLT eklentisi %2$d yok sayıldı" + +#: elf32-vax.c:1802 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%1$s: uyarı: %4$s bölümünden `%3$s' sembolüne %2$s yer deÄŸiÅŸimi" + +#: elf32-vax.c:1808 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%1$s: uyarı: %4$s bölümünden 0x%3$x'e %2$s yer deÄŸiÅŸimi" + +#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450 +msgid "non-zero addend in @fptr reloc" +msgstr "@fptr yerdeÄŸiÅŸiminde sıfır olmayan eklenti" + +#: elf64-alpha.c:1108 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP yerdeÄŸiÅŸimi ldah ve lda iÅŸlemlerini bulamadı" + +#: elf64-alpha.c:3731 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s: .got alt parçası 64K'yı aşıyor (boy %d)" + +#: elf64-alpha.c:4602 elf64-alpha.c:4614 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne gp göreceli yer deÄŸiÅŸimi" + +#: elf64-alpha.c:4640 elf64-alpha.c:4773 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne pc göreceli yer deÄŸiÅŸimi" + +#: elf64-alpha.c:4668 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "%s: gp içinde deÄŸiÅŸiklik: BRSGP %s" + +#: elf64-alpha.c:4693 +msgid "" +msgstr "" + +#: elf64-alpha.c:4698 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "%s: .prologue olmaksızın sembole !samegp yerdeÄŸiÅŸimi: %s" + +#: elf64-alpha.c:4749 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s: %s'e desteklenmeyen dinamik yerdeÄŸiÅŸim" + +#: elf64-alpha.c:4832 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne dtp göreceli yer deÄŸiÅŸimi" + +#: elf64-alpha.c:4855 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne tp göreceli yer deÄŸiÅŸimi" + +#: elf64-hppa.c:2086 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "%s için koçan girdisi .plt'yi yükleyemedi, dp görecesi = %ld" + +#: elf64-mmix.c:1032 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: baÄŸlayıcı tarafından ayrılmış global yazmaç deÄŸeri için iç tutarsızlık hatası:\n" +" 0x%lx%08lx != gevÅŸetilmiÅŸ: 0x%lx%08lx\n" + +#: elf64-mmix.c:1416 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: yazmaç sembolüne temel artı görece yerdeÄŸiÅŸimi: %s içinde (bilinmeyen)" + +#: elf64-mmix.c:1421 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%1$s: yazmaç sembolüne temel artı görece yerdeÄŸiÅŸimi: %3$s içinde %2$s" + +#: elf64-mmix.c:1465 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: yazmaç olmayan sembole yazmaç yerdeÄŸiÅŸimi: %s içinde (bilinmeyen)" + +#: elf64-mmix.c:1470 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%1$s: yazmaç olmayan sembole yazmaç yerdeÄŸiÅŸimi: %3$s içinde %2$s" + +#: elf64-mmix.c:1507 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: YEREL (LOCAL) yönergesi yalnız bir yazmaç veya kesin deÄŸerle geçerlidir" + +#: elf64-mmix.c:1535 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "" +"%s: YEREL (LOCAL) yönergesi: $%ld yazmacı yerel yazmaç deÄŸil.\n" +" Ä°lk evrensel yazmaç: $%ld." + +#: elf64-mmix.c:1994 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "" +"%s: Hata: `%s' birden fazla defa tanımlanmış; %s'nin baÅŸlangıcı daha önce\n" +" baÄŸlanan bir dosyada.\n" + +#: elf64-mmix.c:2053 +msgid "Register section has contents\n" +msgstr "Yazmaç bölümünde içerik yok\n" + +#: elf64-mmix.c:2216 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"İç uyumsuzluk: kalan %u != maksimum %u. \n" +" Lütfen bu hatayı bildirin." + +#: elf64-ppc.c:2388 libbfd.c:831 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s: büyük sonlu sistem için derlenmiÅŸ ve hedef küçük sonlu" + +#: elf64-ppc.c:2391 libbfd.c:833 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s: küçük sonlu sistem için derlenmiÅŸ ve hedef büyük sonlu" + +#: elf64-ppc.c:4857 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s: opd bölümünde beklenmeyen yerdeÄŸiÅŸim türü %u" + +#: elf64-ppc.c:4877 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s: opd, opd girdilerinin düzenli dizisi deÄŸil" + +#: elf64-ppc.c:4897 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s: opd bölümünde tanımlanmamış `%s' sembolü" + +#: elf64-ppc.c:6136 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "`%s' dal koçanı bulunamadı" + +#: elf64-ppc.c:6175 elf64-ppc.c:6250 +#, c-format +msgid "linkage table error against `%s'" +msgstr "`%s'ye baÄŸlama tablosu hatası" + +#: elf64-ppc.c:6340 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "`%s' dal koçanı derlenemedi" + +#: elf64-ppc.c:7047 +msgid ".glink and .plt too far apart" +msgstr " glink ve plt birbirine fazla uzak" + +#: elf64-ppc.c:7135 +msgid "stubs don't match calculated size" +msgstr "koçanlar hesaplanan boyla eÅŸleÅŸmiyor" + +#: elf64-ppc.c:7147 +#, c-format +msgid "" +"linker stubs in %u groups\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"%u grupta baÄŸlayıcı koçanları\n" +" dal %lu\n" +" toc ayarlama %lu\n" +" uzun dal %lu\n" +" uzun toc ayar%lu\n" +" plt çaÄŸrısı %lu" + +#: elf64-ppc.c:7723 +#, c-format +msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%s(%s+0x%lx): otomatik çoklu TOC sizin crt dosyalarınızı kullanarak desteklenmez; -mminimal-toc kullanarak yeniden derleyin veya gcc'de sürüm yükseltmesi yapın" + +#: elf64-ppc.c:7731 +#, c-format +msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%s(%s+0x%lx): `%s'e kardeÅŸ çaÄŸrı iyileÅŸtirmesi otomatik çoklu TOCa izin vermez; -mminimal-toc veya -fno-optimize-sibling-calls ile yeniden derleyin, veya make `%s' extern" + +#: elf64-ppc.c:8329 +#, c-format +msgid "%s: relocation %s is not supported for symbol %s." +msgstr "%s: %s yerdeÄŸiÅŸimi %s sembolü için desteklenmiyor." + +#: elf64-ppc.c:8408 +#, c-format +msgid "%s: error: relocation %s not a multiple of %d" +msgstr "%s: hata: %s yerdeÄŸiÅŸimi %d'nin katı deÄŸil" + +#: elf64-sparc.c:1370 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s: check_relocs: desteklenmeyen yerdeÄŸiÅŸim türü %d" + +#: elf64-sparc.c:1407 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s: Yalnız %%g[2367] yazmaçları STT_REGISTER ile bildirilebilir" + +#: elf64-sparc.c:1427 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "%%g%1$d yazmacı uyumsuz kullanılmış: %3$s içinde %2$s, daha önce %5$s içinde %4$s idi" + +#: elf64-sparc.c:1450 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "`%1$s' sembolünün farklı türleri var: %2$s içinde REGISTER (yazmaç), daha önce %4$s içinde %3$s" + +#: elf64-sparc.c:1496 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "" +"`%1$s' sembolünün farklı türleri var: %3$s içinde %2$s, \n" +" daha önce %4$s içinde REGISTER (yazmaç)" + +#: elf64-sparc.c:3053 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "%s: UltraSPARC'a özel kod HAL'e özel kod ile baÄŸlanıyor" + +#: elf64-x86-64.c:739 +#, c-format +msgid "%s: %s' accessed both as normal and thread local symbol" +msgstr "%s: `%s'a hem normal, hem de iplikçik yerel sembolü olarak eriÅŸildi" + +#: elfcode.h:1113 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: sürüm sayısı (%ld) sembol sayısı (%ld) ile eÅŸleÅŸmiyor" + +#: elfcode.h:1342 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): %d yerdeÄŸiÅŸimi geçersiz sembol indeksi %ld'ye sahip" + +#: elflink.c:1456 +#, c-format +msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%s: uyarı: endirekt sürümlü sembol `%s' için beklenmeyen yeniden tanımlama" + +#: elflink.c:1807 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s: sürümlü sembol ismi %s tanımlı deÄŸil" + +#: elflink.c:2142 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "%1$s: %3$s bölümünde %2$s içinde yerdeÄŸiÅŸim boy uyuÅŸmazlığı" + +#: elflink.c:2434 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "uyarı: `%s' dinamik sembolünün türü ve boyu tanımlı deÄŸil" + +#: elflink.h:1022 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s: %s: geçersiz sürüm %u (maksimum %d)" + +#: elflink.h:1063 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s: %s: geçersiz gerekli sürüm %d" + +#: elflink.h:1238 +#, c-format +msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s" +msgstr "Uyarı: %3$s içinde `%2$s' sembolünün %1$u hizalaması %5$s içinde %4$u'dan daha küçük" + +#: elflink.h:1252 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s" +msgstr "Uyarı: `%1$s' sembolünün boyu %3$s içinde %2$lu'dan %5$s içinde %4$lu'ya deÄŸiÅŸti" + +#: elflink.h:2160 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: tanımsız sürüm: %s" + +#: elflink.h:2226 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s: DSO içinde preinit_array'e izin verilmiyor" + +#: elflink.h:3078 +msgid "Not enough memory to sort relocations" +msgstr "YerdeÄŸiÅŸimleri sıralamak için gerekli bellek yok" + +#: elflink.h:3958 elflink.h:4001 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s: çıktı bölümü %s bulunamadı" + +#: elflink.h:3964 +#, c-format +msgid "warning: %s section has zero size" +msgstr "uyarı: %s bölümü sıfır boyunda" + +#: elflink.h:4483 +#, c-format +msgid "%s: %s symbol `%s' in %s is referenced by DSO" +msgstr "%1$s: %4$s içinde %2$s sembolü `%3$s' DSO tarafından referans ediliyor" + +#: elflink.h:4564 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%1$s: girdi bölümü %3$s için çıktı bölümü %2$s bulunamadı" + +#: elflink.h:4666 +#, c-format +msgid "%s: %s symbol `%s' isn't defined" +msgstr "%s: %s sembol `%s' tanımlı deÄŸil" + +#: elflink.h:5053 elflink.h:5095 +msgid "%T: discarded in section `%s' from %s\n" +msgstr "%1$T: %3$s `%2$s' bölümünde atıldı\n" + +#: elfxx-mips.c:887 +msgid "static procedure (no name)" +msgstr "statik altyordam (isimsiz)" + +#: elfxx-mips.c:1897 +msgid "not enough GOT space for local GOT entries" +msgstr "yerel GOT girdileri için yeterli GOT yeri yok" + +#: elfxx-mips.c:3691 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "%s: %s+0x%lx: jal olmayan koçan yordamına sıçrama" + +#: elfxx-mips.c:5192 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: %s bölümü için geçersiz yer deÄŸiÅŸim bulundu" + +#: elfxx-mips.c:5266 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%s: 0x%lx'deki CALL16 yerdeÄŸiÅŸimi evrensel sembole göre deÄŸil" + +#: elfxx-mips.c:8692 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: geçersiz bölüm adı `%s'" + +#: elfxx-mips.c:9025 +#, c-format +msgid "%s: endianness incompatible with that of the selected emulation" +msgstr "%s: seçilen öykünüm ile sonluluk uyumlu deÄŸil" + +#: elfxx-mips.c:9037 +#, c-format +msgid "%s: ABI is incompatible with that of the selected emulation" +msgstr "%s: ABI, seçilen öykünümle uyumlu deÄŸil" + +#: elfxx-mips.c:9104 +#, c-format +msgid "%s: warning: linking PIC files with non-PIC files" +msgstr "%s: uyarı: PIC dosyaları PIC olmayan dosyalarla baÄŸlanıyor" + +#: elfxx-mips.c:9121 +#, c-format +msgid "%s: linking 32-bit code with 64-bit code" +msgstr "%s: 64 bitlik dosyalar 32 bitlik dosyalarla baÄŸlanıyor" + +#: elfxx-mips.c:9149 +#, c-format +msgid "%s: linking %s module with previous %s modules" +msgstr "%s: %s modülü önceki %s modülle baÄŸlanıyor" + +#: elfxx-mips.c:9172 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s: ABI uyumsuzluÄŸu: %s modülü önceki %s modülle baÄŸlanıyor" + +#: elfxx-mips.c:9241 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:9243 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:9245 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:9247 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:9249 +msgid " [abi unknown]" +msgstr " [abi bilinmiyor]" + +#: elfxx-mips.c:9251 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:9253 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:9255 +msgid " [no abi set]" +msgstr " [abi atanmamış]" + +#: elfxx-mips.c:9258 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:9260 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:9262 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:9264 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:9266 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:9268 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:9270 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:9272 +msgid " [mips32r2]" +msgstr " [mips32r2]" + +#: elfxx-mips.c:9274 +msgid " [unknown ISA]" +msgstr " [bilinmeyen ISA]" + +#: elfxx-mips.c:9277 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:9280 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:9283 +msgid " [32bitmode]" +msgstr " [32bitkipi]" + +#: elfxx-mips.c:9285 +msgid " [not 32bitmode]" +msgstr " [32bitkipi deÄŸil]" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Çıktı dosyası için paylaşımlı kitaplık `%s' gerekli\n" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Çıktı dosyası için paylaşımlı kitaplık `%s.so.%s' gerekli\n" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "%s sembolü düzeltmeler için tanımlı deÄŸil\n" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +msgid "Warning: fixup count mismatch\n" +msgstr "Uyarı: düzeltme sayı uyumsuzluÄŸu\n" + +#: ieee.c:293 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: dizge fazla uzun (%d karakter, en fazla 65535)" + +#: ieee.c:428 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: bilinmeyen `%s' sembol bayrakları 0x%x" + +#: ieee.c:938 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "%1$s: %3$u sembolü için desteklenmeyen ATI kaydı %2$u" + +#: ieee.c:963 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "%s: dış parçada beklenmeyen ATN türü %d" + +#: ieee.c:985 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s: ATN'den sonra beklenmeyen tür" + +#: ihex.c:264 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s:%d: Intel Onaltılık dosyasında beklenmeyen `%s' karakteri\n" + +#: ihex.c:372 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "" +"%s:%u: Intel Onaltılık dosyasında hatalı saÄŸlama toplamı\n" +" (%u beklendi, %u bulundu)" + +#: ihex.c:426 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "%s:%u: Intel Onaltılık dosyasında hatalı uzun adres kaydı uzunluÄŸu" + +#: ihex.c:443 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "%s:%u: Intel Onaltılık dosyasında hatalı uzun baÅŸlangıç adresi uzunluÄŸu" + +#: ihex.c:460 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "%s:%u: Intel Onaltılık dosyasında hatalı uzun lineer adres kaydı uzunluÄŸu" + +#: ihex.c:477 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "%s:%u: Intel Onaltılık dosyasında hatalı uzun lineer baÅŸlangıç adres uzunluÄŸu" + +#: ihex.c:494 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "%s:%u: Intel Onaltılık dosyasında bilinmeyen onaltılık türü %u\n" + +#: ihex.c:619 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "%s: ihex_read_section'da iç hata" + +#: ihex.c:654 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "%s: ihex_read_section'da hatalı bölüm uzunluÄŸu" + +#: ihex.c:872 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: Intex Onaltılık dosyası için 0x%s adresi kapsamdışı" + +#: libbfd.c:861 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "GeçersizleÅŸmiÅŸ %s, %s'da, %d satırı, %s içerisinde çaÄŸrıldı\n" + +#: libbfd.c:864 +#, c-format +msgid "Deprecated %s called\n" +msgstr "GeçerliliÄŸi kalkmış %s çaÄŸrıldı\n" + +#: linker.c:1829 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "%1$s: `%3$s'den endirekt sembol `%2$s'e çevrim" + +#: linker.c:2697 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "%s girdi ve %s çıktısı ile yerdeÄŸiÅŸimli baÄŸ deneniyor" + +#: merge.c:896 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "%s: karıştırılmış bölümün sonundan ileride eriÅŸim (%ld + %ld)" + +#: mmo.c:503 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: %s bölüm adını ayıracak `core' yok\n" + +#: mmo.c:579 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: %d bayt uzunluÄŸunda bir sembole yer ayırmak için `core' yok\n" + +#: mmo.c:1287 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: geçersiz mmo dosyası: $255 için baÅŸlangıç deÄŸeri `Main' deÄŸil\n" + +#: mmo.c:1433 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "" +"%1$s: `%4$s' ile baÅŸlayan sembol adından sonra desteklenmeyen\n" +" geniÅŸ karakter dizisi 0x%2$02X 0x%3$02X\n" + +#: mmo.c:1674 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: geçersiz mmo dosyası: desteklenmeyen lopkod `%d'\n" + +#: mmo.c:1684 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: geçersiz mmo dosyası: YZ = 1 beklendi, lop_quote için YZ = %d bulundu\n" + +#: mmo.c:1720 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" +"%s: geçersiz mmo dosyası: z = 1 veya z = 2 beklendi, \n" +" lop_loc için z = %d bulundu\n" + +#: mmo.c:1766 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: geçersiz mmo dosyası: z = 1 veya z = 2 beklendi; lop_fixo için z = %d bulundu\n" + +#: mmo.c:1805 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: geçersiz mmo dosyası: y = 0 beklendi; lop_fixrx için y = %d bulundu\n" + +#: mmo.c:1814 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" +"%s: geçersiz mmo dosyası: z = 16 veya z = 24 beklendi;\n" +" lop_fixrx için z = %d bulundu\n" + +#: mmo.c:1837 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "" +"%s: geçersiz mmo dosyası: iÅŸlenen word'un ilk baytı 0 veya 1 olmalı; \n" +" lop_fixrx için %d bulundu\n" + +#: mmo.c:1860 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: %d sayılı dosya için dosya adı ayrılamadı, %d bayt\n" + +#: mmo.c:1880 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: geçersiz mmo dosyası: %d sayılı dosya, `%s', zaten `%s' olarak girilmiÅŸ\n" + +#: mmo.c:1893 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" +"%s: geçersiz mmo dosyası: %d sayısı için dosya adı kullanımdan\n" +" önce belirtilmemiÅŸ\n" + +#: mmo.c:1999 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" +"%s: geçersiz mmo dosyası: lop_stab'in y ve z alanları sıfır deÄŸil;\n" +" y: %d, z: %d\n" + +#: mmo.c:2035 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: geçersiz mmo dosyası: lop_end dosyadaki son girdi deÄŸil\n" + +#: mmo.c:2048 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "" +"%s: geçersiz mmo dosyası: lop_end'in YZ'si (%ld); bir önceki \n" +" lop_stab'in (%ld) dörtlü sayısına eÅŸit deÄŸil\n" + +#: mmo.c:2698 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: geçersiz sembol tablosu: tekrarlanmış sembol `%s'\n" + +#: mmo.c:2949 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "" +"%1$s: Hatalı sembol tanımı: `Main' baÅŸlangıç adresi %3$s yerine \n" +" %2$s olarak tanımlanmış\n" + +#: mmo.c:3039 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "" +"%s: uyarı: sembol tablosu mmo için fazla büyük, 65535 32-bit word'den\n" +" fazla: %d. Yalnız `Main' üretilecek. \n" + +#: mmo.c:3084 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: iç hata, sembol tablosu büyüklüğü %d'den %d word'e deÄŸiÅŸti\n" + +#: mmo.c:3139 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: iç hata, %s iç yazmaç bölümü içerik taşıyor\n" + +#: mmo.c:3191 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: ilklenen yazmaç yok; bölüm uzunluÄŸu 0\n" + +#: mmo.c:3197 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: çok fazla ilklenmiÅŸ yazmaç; bölüm uzunluÄŸu %ld\n" + +#: mmo.c:3202 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: %ld uzunluÄŸunda ilklenmiÅŸ yazmaçlar için hatalı baÅŸlangıç adresi: 0x%lx%08lx\n" + +#: oasys.c:1052 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: oasys'de `%s' bölümü gösterilemiyor" + +#: osf-core.c:137 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Desteklenmeyen OSF/1 core dosyası bölüm türü %d\n" + +#: pe-mips.c:659 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "%s: `ld -r' PE MIPS nesneleri ile birlikte desteklenmiyor\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:795 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s: tamamlanmamış %s\n" + +#: pe-mips.c:821 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s: sıçrama fazla uzak\n" + +#: pe-mips.c:848 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "%s: refhi'den sonra hatalı çift/reflo\n" + +#. XXX code yet to be written. +#: peicode.h:787 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s: Desteklenmeyen ithal türü; %x" + +#: peicode.h:792 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s: Tanınmayan ithal türü; %x" + +#: peicode.h:806 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s: Tanınmayan ithal isim türü; %x" + +#: peicode.h:1164 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%s: Ä°thal Kitaplık Biçem (ILF) arÅŸivinde tanınmayan makina türü (0x%x) " + +#: peicode.h:1176 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%s: Ä°thal Kitaplık Biçem (ILF) arÅŸivinde bilinen fakat desteklenmeyen makina türü (0x%x)" + +#: peicode.h:1193 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "%s: Ä°thal Kitaplık Biçem (ILF) baÅŸlığında boy alanı sıfır" + +#: peicode.h:1224 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "%s: ILF nesne dosyasında dizge boÅŸ deÄŸerle sonlanmamış." + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"ppcboot baÅŸlığı:\n" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Girdi göreli konumu = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Uzunluk = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "Bayrak alanı = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Bölüm adı = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Bölüm[%d] baÅŸlangıcı = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Bölüm[%d] sonu = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Bölüm[%d] sektörü = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Bölüm[%d] uzunluÄŸu = 0x%.8lx (%ld)\n" + +#: som.c:5422 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers tamamlanmamış" + +#: srec.c:302 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "%s:%d: S-kayıt dosyasında beklenmeyen `%s' karakteri\n" + +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "%s(%s+0x%lx): Stabs girdisinde geçersiz dizge indeksi." + +#: syms.c:1019 +msgid "Unsupported .stab relocation" +msgstr "Desteklenmeyen .stab yerdeÄŸiÅŸimi" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) baÅŸarısız" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) baÅŸarısız" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Boy uyumsuzluÄŸu bölümü %s=%lx, %s=%lx" + +#: vms-gsd.c:704 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "bilinmeyen gsd/egsd alt türü %d" + +#: vms-hdr.c:408 +msgid "Object module NOT error-free !\n" +msgstr "Nesne modülü hatasız DEĞİL !\n" + +#: vms-misc.c:541 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "_bfd_vms_push'da yığıt taÅŸması (%d)" + +#: vms-misc.c:559 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "_bfd_vms_pop'da yığıt alt taÅŸması" + +#: vms-misc.c:918 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted sıfır bayt ile çaÄŸrıldı" + +#: vms-misc.c:923 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted fazla bayt ile çaÄŸrıldı" + +#: vms-misc.c:1054 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "%s sembolü %s ile deÄŸiÅŸtirildi\n" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "%s'e giriÅŸ baÅŸarısız" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "Hafıza Yok !" + +#: vms-tir.c:383 +#, c-format +msgid "bad section index in %s" +msgstr "%s içinde hatalı bölüm indeksi" + +#: vms-tir.c:396 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "Desteklenmeyen STA komutu %s" + +#: vms-tir.c:401 vms-tir.c:1261 +#, c-format +msgid "reserved STA cmd %d" +msgstr "Ayrılmış STA komutu %d" + +#: vms-tir.c:512 vms-tir.c:535 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "%s: \"%s\" sembolü yok" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850 +#: vms-tir.c:859 vms-tir.c:1584 +#, c-format +msgid "%s: not supported" +msgstr "%s: desteklenmiyor" + +#: vms-tir.c:607 vms-tir.c:1439 +#, c-format +msgid "%s: not implemented" +msgstr "%s: tamamlanmamış" + +#: vms-tir.c:611 vms-tir.c:1443 +#, c-format +msgid "reserved STO cmd %d" +msgstr "Ayrılmış STO komutu %d" + +#: vms-tir.c:729 vms-tir.c:1589 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "Ayrılmış OPR komutu %d" + +#: vms-tir.c:797 vms-tir.c:1653 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "Ayrılmış CTL komutu %d" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1169 +msgid "stack-from-image not implemented" +msgstr "Görüntüden-yığıt tamamlanmamış" + +#: vms-tir.c:1187 +msgid "stack-entry-mask not fully implemented" +msgstr "Yığın girdi maskı tamamlanmamış" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1201 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH tamamlanmamış" + +#: vms-tir.c:1220 +msgid "stack-local-symbol not fully implemented" +msgstr "Yerel sembol yığıtı tamamlanmamış" + +#: vms-tir.c:1233 +msgid "stack-literal not fully implemented" +msgstr "Yığıt sabiti tamamlanmamış" + +#: vms-tir.c:1254 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "Yığın yerel sembol girdi noktası maskı tamamlanmamış" + +#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632 +#: vms-tir.c:1640 vms-tir.c:1648 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: tamamlanmamış" + +#: vms-tir.c:1705 +#, c-format +msgid "obj code %d not found" +msgstr "Nesne kodu %d bulunmadı" + +#: vms-tir.c:2043 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "%s bölümünde yerdeÄŸiÅŸim olmaksızın SEC_RELOC" + +#: vms-tir.c:2331 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Desteklenmeyen yerdeÄŸiÅŸim %s" + +#: xcofflink.c:1244 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "%s: `%s' satır numaralarına sahip fakat onu içeren bölümü yok" + +#: xcofflink.c:1297 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "%s: sınıf %d sembol `%s'un alternatif girdileri yok" + +#: xcofflink.c:1320 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "%s: `%s' sembolünde bilinmeyen csect türü %d var" + +#: xcofflink.c:1332 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%s: hatalı XTY_ER sembolü `%s': sınıf %d scnum %d scnlen %d" + +#: xcofflink.c:1368 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%s: XMC_TC0 sembolü `%s': sınıf %d scnlen %d" + +#: xcofflink.c:1520 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "%s: csect `%s' onu içeren bölümde deÄŸil" + +#: xcofflink.c:1627 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "%s: XTY_LD `%s'yanlış yerde" + +#: xcofflink.c:1958 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "%s: yerdeÄŸiÅŸim %s:%d csect içinde deÄŸil" + +#: xcofflink.c:2095 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: XCOFF çıktısı oluÅŸturulmazken XCOFF paylaşımlı nesnesi" + +#: xcofflink.c:2116 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s: .loader bölümü olmayan dinamik nesne" + +#: xcofflink.c:2761 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: böyle bir sembol yok" + +#: xcofflink.c:2894 +msgid "error: undefined symbol __rtinit" +msgstr "hata: tanımlanmamış sembol __rtinit" + +#: xcofflink.c:3455 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "uyarı: tanımlanmamış `%s' sembolünü ihraç denemesi" + +#: xcofflink.c:4448 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "TOC taÅŸması: 0x%lx > 0x10000; -mminimal-toc ile derlemeyi deneyin" + +#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "%s: bilinmeyen `%s' bölümünde yükleyici yerdeÄŸiÅŸimi" + +#: xcofflink.c:5310 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "%s: `%s' yükleyici yerdeÄŸiÅŸiminde fakat yükleyici sembolü deÄŸil" + +#: xcofflink.c:5325 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "%s: %s salt-okunur bölümünde yükleyici yerdeÄŸiÅŸimi" + +#: elf32-ia64.c:2392 elf64-ia64.c:2392 +msgid "@pltoff reloc against local symbol" +msgstr "yerel sembole @pltoff yerdegisimi" + +#: elf32-ia64.c:3804 elf64-ia64.c:3804 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: kısa veri bölümünde taÅŸma (0x%lx >= 0x400000)" + +#: elf32-ia64.c:3815 elf64-ia64.c:3815 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp kısa veri bölümünü kapsamıyor" + +#: elf32-ia64.c:4131 elf64-ia64.c:4131 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "%s: pic olmayan kod paylaÅŸmalı kitaplıkta baÄŸlanıyor" + +#: elf32-ia64.c:4164 elf64-ia64.c:4164 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne @gprel yerdeÄŸiÅŸimi" + +#: elf32-ia64.c:4224 elf64-ia64.c:4224 +#, c-format +msgid "%s: linking non-pic code in a position independent executable" +msgstr "%s: pic olmayan kod yer bağımsız uygulamaya baÄŸlanıyor" + +#: elf32-ia64.c:4363 elf64-ia64.c:4363 +#, c-format +msgid "%s: @internal branch to dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne @internal dalı" + +#: elf32-ia64.c:4365 elf64-ia64.c:4365 +#, c-format +msgid "%s: speculation fixup to dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne spekülasyon düzeltmesi" + +#: elf32-ia64.c:4367 elf64-ia64.c:4367 +#, c-format +msgid "%s: @pcrel relocation against dynamic symbol %s" +msgstr "%s: %s dinamik sembolüne @pcrel yerdeÄŸiÅŸimi" + +#: elf32-ia64.c:4579 elf64-ia64.c:4579 +msgid "unsupported reloc" +msgstr "desteklenmeyen yerdeÄŸiÅŸim" + +#: elf32-ia64.c:4858 elf64-ia64.c:4858 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%s: NULL-halinde-tuzakla karşı-baÅŸvurusu tuzaklamayan dosyalarla baÄŸlandı" + +#: elf32-ia64.c:4867 elf64-ia64.c:4867 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s: büyük sonlu dosyalar küçük sonlu dosyalarla baÄŸlanıyor" + +#: elf32-ia64.c:4876 elf64-ia64.c:4876 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s: 64 bitlik dosyalar 32 bitlik dosyalarla baÄŸlanıyor" + +#: elf32-ia64.c:4885 elf64-ia64.c:4885 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "%s: constant-gp dosyaları constant-gp olmayan dosyalarla baÄŸlanıyor" + +#: elf32-ia64.c:4895 elf64-ia64.c:4895 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "%s: auto-pic dosyaları auto-pic olmayan dosyalarla baÄŸlanıyor" + +#: peigen.c:985 pepigen.c:985 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: satır numarası taÅŸması: 0x%lx > 0xffff" + +#: peigen.c:1002 pepigen.c:1002 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "%s: yerdeÄŸiÅŸim taÅŸması 1: 0x%lx > 0xffff" + +#: peigen.c:1016 pepigen.c:1016 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "Ä°hraç Dizini [.edata (veya nerede bulundu ise)]" + +#: peigen.c:1017 pepigen.c:1017 +msgid "Import Directory [parts of .idata]" +msgstr "Ä°thal Dizini [.idata'nın parçaları]" + +#: peigen.c:1018 pepigen.c:1018 +msgid "Resource Directory [.rsrc]" +msgstr "Kaynak Dizini [.rsrc]" + +#: peigen.c:1019 pepigen.c:1019 +msgid "Exception Directory [.pdata]" +msgstr "Ä°stisna Dizini [.pdata]" + +#: peigen.c:1020 pepigen.c:1020 +msgid "Security Directory" +msgstr "Güvenlik Dizini" + +#: peigen.c:1021 pepigen.c:1021 +msgid "Base Relocation Directory [.reloc]" +msgstr "Temel YerdeÄŸiÅŸim Dizini [.reloc]" + +#: peigen.c:1022 pepigen.c:1022 +msgid "Debug Directory" +msgstr "Hata Ayıklama Dizini" + +#: peigen.c:1023 pepigen.c:1023 +msgid "Description Directory" +msgstr "Açıklama Dizini" + +#: peigen.c:1024 pepigen.c:1024 +msgid "Special Directory" +msgstr "Özel Dizin" + +#: peigen.c:1025 pepigen.c:1025 +msgid "Thread Storage Directory [.tls]" +msgstr "Dal Saklama Dizini [.tls]" + +#: peigen.c:1026 pepigen.c:1026 +msgid "Load Configuration Directory" +msgstr "Ayar Yükleme Dizini" + +#: peigen.c:1027 pepigen.c:1027 +msgid "Bound Import Directory" +msgstr "Sınır Ä°thal Dizini" + +#: peigen.c:1028 pepigen.c:1028 +msgid "Import Address Table Directory" +msgstr "Adres Tablosu Ä°thal Dizini" + +#: peigen.c:1029 pepigen.c:1029 +msgid "Delay Import Directory" +msgstr "Gecikmeli Ä°thal Dizini" + +#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031 +msgid "Reserved" +msgstr "Ayrılmış" + +#: peigen.c:1094 pepigen.c:1094 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Bir ithal tablosu var, fakat onu içeren bölüm bulunamadı\n" + +#: peigen.c:1099 pepigen.c:1099 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s içerisinde 0x%lx'de bir ithal tablosu var\n" + +#: peigen.c:1136 pepigen.c:1136 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"BaÅŸlangıç adresinde iÅŸlev betimleyicisi bulundu: %04lx\n" + +#: peigen.c:1139 pepigen.c:1139 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tkod temeli %08lx toc (yüklenebilir/gerçek) %08lx/%08lx\n" + +#: peigen.c:1145 pepigen.c:1145 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Reldata bölümü yok! Ä°ÅŸlev betimleyicisi çözümlenemedi.\n" + +#: peigen.c:1150 pepigen.c:1150 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Ä°thal Tabloları (%s bölüm içeriÄŸi çözümlendi)\n" + +#: peigen.c:1153 pepigen.c:1153 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Ä°pucu Zaman Ä°leri DLL Ä°lk\n" +" Tablo Damga Zincir Ä°sim Parça\n" + +#: peigen.c:1204 pepigen.c:1204 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL Adı: %s\n" + +#: peigen.c:1215 pepigen.c:1215 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Ä°pucu/Sıra Ãœye-Adı Sınır\n" + +#: peigen.c:1240 pepigen.c:1240 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Bir ilk parça var, fakat onu içeren bölüm bulunamadı\n" + +#: peigen.c:1380 pepigen.c:1380 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Bir ihraç tablosu var, fakat onu içeren bölüm bulunamadı\n" + +#: peigen.c:1385 pepigen.c:1385 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s içinde 0x%lx'de bir ihraç tablosu var\n" + +#: peigen.c:1416 pepigen.c:1416 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Ä°hraç Tabloları (%s bölüm içeriÄŸi çözümlendi)\n" +"\n" + +#: peigen.c:1420 pepigen.c:1420 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Ä°hraç Bayrakları \t\t\t%lx\n" + +#: peigen.c:1423 pepigen.c:1423 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Saat/Tarih damgası \t\t%lx\n" + +#: peigen.c:1426 pepigen.c:1426 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Majör/Minör \t\t\t%d/%d\n" + +#: peigen.c:1429 pepigen.c:1429 +msgid "Name \t\t\t\t" +msgstr "Ä°sim \t\t\t\t" + +#: peigen.c:1435 pepigen.c:1435 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "Onluk Sistem \t\t\t%ld\n" + +#: peigen.c:1438 pepigen.c:1438 +msgid "Number in:\n" +msgstr "Sayı içinde:\n" + +#: peigen.c:1441 pepigen.c:1441 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tÄ°hraç Adres Tablosu \t\t%08lx\n" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Ä°sim Gösterge/Onluk] Tablo\t%08lx\n" + +#: peigen.c:1448 pepigen.c:1448 +msgid "Table Addresses\n" +msgstr "Tablo Adresleri\n" + +#: peigen.c:1451 pepigen.c:1451 +msgid "\tExport Address Table \t\t" +msgstr "\tÄ°hraç Adres Tablosu \t\t" + +#: peigen.c:1456 pepigen.c:1456 +msgid "\tName Pointer Table \t\t" +msgstr "\tÄ°sim Gösterge Tablosu \t\t" + +#: peigen.c:1461 pepigen.c:1461 +msgid "\tOrdinal Table \t\t\t" +msgstr "\tOnluk Tablo \t\t\t" + +#: peigen.c:1476 pepigen.c:1476 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Ä°hraç Adres Tablosu -- Onluk Sistem %ld\n" + +#: peigen.c:1495 pepigen.c:1495 +msgid "Forwarder RVA" +msgstr "RVA Yönlendiricisi" + +#: peigen.c:1506 pepigen.c:1506 +msgid "Export RVA" +msgstr "RVA Ä°hracı" + +#: peigen.c:1513 pepigen.c:1513 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"[Onluk/Ä°sim Gösterge] Tablosu\n" + +#: peigen.c:1568 pepigen.c:1568 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Uyarı, .pdata bölüm boyu (%ld) %d'nin katı deÄŸil\n" + +#: peigen.c:1572 pepigen.c:1572 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Ä°ÅŸlev Tablosu (.pdata bölüm içeriÄŸi çözümlendi)\n" + +#: peigen.c:1575 pepigen.c:1575 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tBaÅŸlangıç Adresi Sonlanma Adresi Geri Al Bilgisi\n" + +#: peigen.c:1577 pepigen.c:1577 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tBaÅŸl. Son EH EH PrologSon Ä°stisna\n" +" \t\tAdres Adres Yakalay Veri Adres Maske\n" + +#: peigen.c:1647 pepigen.c:1647 +msgid " Register save millicode" +msgstr " Yazma milikodunu kaydet" + +#: peigen.c:1650 pepigen.c:1650 +msgid " Register restore millicode" +msgstr " Geri alma milikodunu kaydet" + +#: peigen.c:1653 pepigen.c:1653 +msgid " Glue code sequence" +msgstr " BirleÅŸtirici kod dizisi" + +#: peigen.c:1705 pepigen.c:1705 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"PE Dosya Temel YerdeÄŸiÅŸimi (.reloc bölüm içeriÄŸi çözümlendi)\n" + +#: peigen.c:1735 pepigen.c:1735 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Sanal Adres: %08lx Parça boyu %ld (0x%lx) Düzeltme Sayısı %ld\n" + +#: peigen.c:1748 pepigen.c:1748 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\tyer deÄŸiÅŸim %4d göreli konum %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1788 pepigen.c:1788 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Özellikler 0x%x\n" + +#~ msgid "%s: Unknown special linker type %d" +#~ msgstr "%s: Bilinmeyen özel baÄŸlayıcı türü %d" + +#~ msgid "v850ea architecture" +#~ msgstr "v850ea platformu" + +#~ msgid "%s: Section %s is too large to add hole of %ld bytes" +#~ msgstr "%s: %s bölümü içine %ld baytlık bir delik koymak için fazla büyük" + +#~ msgid "Error: out of memory" +#~ msgstr "Hata: bellek tükendi" + +#~ msgid "warning: relocation against removed section; zeroing" +#~ msgstr "uyarı: silinmiÅŸ bölüme yer deÄŸiÅŸim; sıfırlandı" + +#~ msgid "warning: relocation against removed section" +#~ msgstr "%1$s: silinmiÅŸ bölüme yerdeÄŸiÅŸim" + +#~ msgid "local symbols in discarded section %s" +#~ msgstr "atılmış %s bölümünde yerel semboller" + +#~ msgid "%s: linking abicalls files with non-abicalls files" +#~ msgstr "%s: abicalls dosyaları abicalls olmayan dosyalarla baÄŸlanıyor" + +#~ msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +#~ msgstr "%1$s: Önceki modüllerle (-mips%3$d) ile ISA uyumsuzluÄŸu (-mips%2$d)" + +#~ msgid "%s: ISA mismatch (%d) with previous modules (%d)" +#~ msgstr "%1$s: Önceki modüllerle (%3$d) ile ISA uyumsuzluÄŸu (%2$d)" + +#~ msgid "%s: dynamic relocation against speculation fixup" +#~ msgstr "%s: kuÅŸkulu düzeltmeye dinamik yerdeÄŸiÅŸim" + +#~ msgid "%s: speculation fixup against undefined weak symbol" +#~ msgstr "%s: tanımlanmamış gevÅŸek sembole tartışmalı düzeltme" + +#~ msgid "GP relative relocation when GP not defined" +#~ msgstr "GP tanımlanmamışken GP göreli yer deÄŸiÅŸtirmesi" + +#~ msgid "%s: ERROR: passes floats in float registers whereas target %s uses integer registers" +#~ msgstr "%s: HATA: kayan sayıları kayan yazmaçlarda geçiriyor fakat hedef %s tamsayı yazmaç kullanıyor" + +#~ msgid "%s: ERROR: passes floats in integer registers whereas target %s uses float registers" +#~ msgstr "%s: HATA: kayan sayıları tamsayı yazmaçlarda geçiriyor fakat hedef %s kayan yazmaç kullanıyor" + +#~ msgid "Warning: input file %s supports interworking, whereas %s does not." +#~ msgstr "Uyarı: %s girdi dosyası beraber çalışmayı destekliyor, fakat %s desteklemiyor." + +#~ msgid "Warning: input file %s does not support interworking, whereas %s does." +#~ msgstr "Uyarı: %s girdi dosyası beraber çalışmayı desteklemiyor, fakat %s destekliyor." + +#~ msgid "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" +#~ msgstr "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld sonraki %ld" + +#~ msgid "elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = 0x%.8lx%s\n" +#~ msgstr "bfd sembolünden elf sembolü:0x%.8lx, isim= %s, sem num = %d, bayrak = 0x%.8lx%s\n" + +#~ msgid "Warning: Not setting interwork flag of %s since it has already been specified as non-interworking" +#~ msgstr "Uyarı: beraber çalışmaz diye önceden belirtilmiÅŸ olduÄŸundan %s'nin beraber çalışma bayrağı atanmadı" + +#~ msgid "Warning: Clearing the interwork flag of %s due to outside request" +#~ msgstr "Uyarı: Dış isteÄŸe uyularak %s'nin beraber çalışma bayrağı temizlendi" + +#~ msgid " [APCS-26]" +#~ msgstr " [APCS-26]" + +#~ msgid " [APCS-32]" +#~ msgstr " [APCS-32]" + +#~ msgid "(unknown)" +#~ msgstr "(bilinmeyen)" + +#~ msgid " previously %s in %s" +#~ msgstr " daha önce %2$s içinde %1$s" + +#~ msgid "ETIR_S_C_STO_GBL: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_GBL: sembol yok \"%s\"" + +#~ msgid "ETIR_S_C_STO_CA: no symbol \"%s\"" +#~ msgstr "ETIR_S_C_STO_CA: sembol yok \"%s\"" + +#~ msgid "ETIR_S_C_STO_RB/AB: Not supported" +#~ msgstr "ETIR_S_C_STO_RB/AB: Desteklenmiyor" + +#~ msgid "ETIR_S_C_STO_LP_PSB: Not supported" +#~ msgstr "ETIR_S_C_STO_LP_PSB: Desteklenmiyor" + +#~ msgid "ETIR_S_C_STO_HINT_GBL: not implemented" +#~ msgstr "ETIR_S_C_STO_HINT_GBL: tamamlanmamış" + +#~ msgid "ETIR_S_C_STO_HINT_PS: not implemented" +#~ msgstr "ETIR_S_C_STO_HINT_PS: tamamlanmamış" + +#~ msgid "ETIR_S_C_OPR_INSV: Not supported" +#~ msgstr "ETIR_S_C_OPR_INSV: Desteklenmiyor" + +#~ msgid "ETIR_S_C_OPR_USH: Not supported" +#~ msgstr "ETIR_S_C_OPR_USH: Desteklenmiyor" + +#~ msgid "ETIR_S_C_OPR_ROT: Not supported" +#~ msgstr "ETIR_S_C_OPR_ROT: Desteklenmiyor" + +#~ msgid "ETIR_S_C_OPR_REDEF: Not supported" +#~ msgstr "ETIR_S_C_OPR_REDEF: Desteklenmiyor" + +#~ msgid "ETIR_S_C_OPR_DFLIT: Not supported" +#~ msgstr "ETIR_S_C_OPR_DFLIT: Desteklenmiyor" + +#~ msgid "ETIR_S_C_STC_GBL: not supported" +#~ msgstr "ETIR_S_C_STC_GBL: desteklenmiyor" + +#~ msgid "ETIR_S_C_STC_GCA: not supported" +#~ msgstr "ETIR_S_C_STC_GCA: desteklenmiyor" + +#~ msgid "ETIR_S_C_STC_PS: not supported" +#~ msgstr "ETIR_S_C_STC_PS: desteklenmiyor" + +#~ msgid "Unimplemented STO cmd %d" +#~ msgstr "Tamamlanmamış STO komutu %d" + +#~ msgid "TIR_S_C_OPR_ASH incomplete" +#~ msgstr "TIR_S_C_OPR_ASH tamamlanmamış" + +#~ msgid "TIR_S_C_OPR_USH incomplete" +#~ msgstr "TIR_S_C_OPR_USH tamamlanmamış" + +#~ msgid "TIR_S_C_OPR_ROT incomplete" +#~ msgstr "TIR_S_C_OPR_ROT tamamlanmamış" + +#~ msgid "TIR_S_C_OPR_REDEF not supported" +#~ msgstr "TIR_S_C_OPR_REDEF desteklenmiyor" + +#~ msgid "TIR_S_C_OPR_DFLIT not supported" +#~ msgstr "TIR_S_C_OPR_DFLIT desteklenmiyor" + +#~ msgid "TIR_S_C_CTL_DFLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_DFLOC tamamlanmamış" + +#~ msgid "TIR_S_C_CTL_STLOC not fully implemented" +#~ msgstr "TIR_S_C_CTL_STLOC tamamlanmamış" + +#~ msgid "TIR_S_C_CTL_STKDL not fully implemented" +#~ msgstr "TIR_S_C_CTL_STKDL tamamlanmamış" + +#~ msgid " vma: Hint Time Forward DLL First\n" +#~ msgstr " vma: Ä°pucu Zaman Ä°leri DLL Ä°lk\n" + +#~ msgid "\tThe Import Address Table (difference found)\n" +#~ msgstr "\tÄ°thal Adres Tablosu (fark bulundu)\n" + +#~ msgid "\t>>> Ran out of IAT members!\n" +#~ msgstr "\t>>> IAT üyeleri bitti!\n" + +#~ msgid "\tThe Import Address Table is identical\n" +#~ msgstr "\tÄ°thal Adres Tablosu aynı\n" + +#~ msgid " \t\tAddress Address Handler Data Address Mask\n" +#~ msgstr " \t\tAdres Adres Yön. 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RWNo$Vp^xp1QrN, 2005. +# Clytie Siddall , 2008-2010. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.20.1\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-03-03 15:03+0100\n" +"PO-Revision-Date: 2010-04-22 23:21+0930\n" +"Last-Translator: Clytie Siddall \n" +"Language-Team: Vietnamese \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=1; plural=0;\n" +"X-Generator: LocFactoryEditor 1.8\n" + +#: aout-adobe.c:127 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Không rõ kiểu phần trong tập tin a.out.adobe: %x\n" + +#: aout-cris.c:204 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Äã xuất kiểu định vị lại không hợp lệ: %d" + +#: aout-cris.c:247 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Äã nhập kiểu định vị lại không hợp lệ: %d" + +#: aout-cris.c:258 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Äã nhập mục ghi định vị lại sai: %d" + +#: aoutx.h:1271 aoutx.h:1609 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: không thể đại diện phân « %s » trong định dạng tập tin đối tượng a.out" + +#: aoutx.h:1575 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: không thể đại diện phân cho ký hiệu « %s » trong định dạng tập tin đối tượng a.ou" + +#: aoutx.h:1577 +msgid "*unknown*" +msgstr "• không rõ •" + +#: aoutx.h:3997 aoutx.h:4323 +msgid "%P: %B: unexpected relocation type\n" +msgstr "%P: %B: kiểu định vị lại bất thÆ°á»ng\n" + +#: aoutx.h:5358 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: không há»— trợ liên kết có khả năng định vị lại từ %s sang %s" + +#: archive.c:2057 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Cảnh báo : ghi kho quá chậm nên Ä‘ang ghi lại nhãn thá»i gian\n" + +#: archive.c:2344 +msgid "Reading archive file mod timestamp" +msgstr "Äang Ä‘á»c nhãn thá»i gian sá»­a đổi tập tin kho" + +#: archive.c:2368 +msgid "Writing updated armap timestamp" +msgstr "Äang ghi nhãn thá»i gian armap đã cập nhật" + +#: bfd.c:376 +msgid "No error" +msgstr "Không có lá»—i" + +#: bfd.c:377 +msgid "System call error" +msgstr "Lá»—i gá»i hệ thống" + +#: bfd.c:378 +msgid "Invalid bfd target" +msgstr "Äích bfd không hợp lệ" + +#: bfd.c:379 +msgid "File in wrong format" +msgstr "Tập tin có định dạng không đúng" + +#: bfd.c:380 +msgid "Archive object file in wrong format" +msgstr "Tập tin đối tượng kho có định dạng không đúng" + +#: bfd.c:381 +msgid "Invalid operation" +msgstr "Thao tác không hợp lệ" + +#: bfd.c:382 +msgid "Memory exhausted" +msgstr "Cạn bá»™ nhá»›" + +#: bfd.c:383 +msgid "No symbols" +msgstr "Không có ký hiệu" + +#: bfd.c:384 +msgid "Archive has no index; run ranlib to add one" +msgstr "Kho không có chỉ mục: hãy chạy ranlib để thêm" + +#: bfd.c:385 +msgid "No more archived files" +msgstr "Không còn có tập tin đã lÆ°u trữ nào nữa" + +#: bfd.c:386 +msgid "Malformed archive" +msgstr "Kho dạng sai" + +#: bfd.c:387 +msgid "File format not recognized" +msgstr "Không nhận ra định dạng tập tin" + +#: bfd.c:388 +msgid "File format is ambiguous" +msgstr "Äịnh dạng tập tin mÆ¡ hồ" + +#: bfd.c:389 +msgid "Section has no contents" +msgstr "Phần không có ná»™i dung" + +#: bfd.c:390 +msgid "Nonrepresentable section on output" +msgstr "Kết xuất có phần không thể đại diện được" + +#: bfd.c:391 +msgid "Symbol needs debug section which does not exist" +msgstr "Ký hiệu cần phần gỡ lá»—i mà không tồn tại" + +#: bfd.c:392 +msgid "Bad value" +msgstr "Giá trị sai" + +#: bfd.c:393 +msgid "File truncated" +msgstr "Tập tin bị cắt ngắn" + +#: bfd.c:394 +msgid "File too big" +msgstr "Tập tin quá lá»›n" + +#: bfd.c:395 +#, c-format +msgid "Error reading %s: %s" +msgstr "Gặp lá»—i khi Ä‘á»c %s: %s" + +#: bfd.c:396 +msgid "#" +msgstr "#" + +#: bfd.c:920 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s khắng định bị lá»—i %s:%d" + +#: bfd.c:932 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %s lá»—i ná»™i bá»™ nên hủy bá» tại %s dòng %d trong %s\n" + +#: bfd.c:936 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %s lá»—i ná»™i bá»™ nên hủy bá» tại %s dòng %d\n" + +#: bfd.c:938 +msgid "Please report this bug.\n" +msgstr "Hãy thông báo lá»—i này.\n" + +#: bfdwin.c:206 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "không Ä‘ang ánh xạ: dữ liệu=%lx đã ánh xạ=%d\n" + +#: bfdwin.c:209 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "không Ä‘ang ánh xạ: chÆ°a đặt biến môi trÆ°á»ng\n" + +#: binary.c:284 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Cảnh báo : Ä‘ang ghi phần « %s » vào khoảng bù tập tin rất lá»›n (tức là âm) 0x%lx." + +#: bout.c:1150 elf-m10300.c:2078 elf32-avr.c:1639 elf32-frv.c:5743 +#: elfxx-sparc.c:2456 reloc.c:5386 reloc16.c:162 vms.c:1918 elf32-ia64.c:788 +#: elf64-ia64.c:788 +msgid "%P%F: --relax and -r may not be used together\n" +msgstr "%P%F: không thể dùng vá»›i nhau hai tuỳ chá»n « --relax » và « -r »\n" + +#: cache.c:226 +msgid "reopening %B: %s\n" +msgstr "Ä‘ang mở lại %B: %s\n" + +#: coff-alpha.c:490 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" +"%B: Không thể xá»­ lý tập tin nhị phân Alpha chÆ°a được nén.\n" +"\tHãy dùng các cá» biên dịch, hoặc objZ, để tạo tập tin nhị phân chÆ°a được nén." + +#: coff-alpha.c:647 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "%B: kiểu định vị lại không rõ hoặc không được há»— trợ : %d" + +#: coff-alpha.c:899 coff-alpha.c:936 coff-alpha.c:2024 coff-mips.c:1003 +msgid "GP relative relocation used when GP not defined" +msgstr "ChÆ°a xác định GP thì sá»­ dụng định vị lại tÆ°Æ¡ng đối GP" + +#: coff-alpha.c:1501 +msgid "using multiple gp values" +msgstr "Ä‘ang dùng nhiá»u giá trị GP" + +#: coff-alpha.c:1560 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "%B: định vị lại không được há»— trợ : ALPHA_R_GPRELHIGH" + +#: coff-alpha.c:1567 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "%B: định vị lại không được há»— trợ : ALPHA_R_GPRELLOW" + +#: coff-alpha.c:1574 elf32-m32r.c:2477 elf64-alpha.c:3943 elf64-alpha.c:4098 +#: elf32-ia64.c:4462 elf64-ia64.c:4462 +msgid "%B: unknown relocation type %d" +msgstr "%B: không rõ kiểu định vị lại %d" + +#: coff-arm.c:1039 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: không tìm thấy keo hồ THUMB « %s » cho « %s »" + +#: coff-arm.c:1068 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: không tìm thấy keo hồ ARM « %s » cho « %s »" + +#: coff-arm.c:1370 elf32-arm.c:6372 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): cảnh báo : chÆ°a bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu tiên: %B: gá»i arm tá»›i thumb" + +#: coff-arm.c:1460 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): cảnh báo : chÆ°a bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu tiên: %B: gá»i thumb tá»›i arm\n" +" coi nhÆ° liên kết lại vá»›i « --support-old-code » được bật" + +#: coff-arm.c:1755 coff-tic80.c:695 cofflink.c:3030 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: địa chỉ định vị lại sai 0x%lx trong phần « %A »" + +#: coff-arm.c:2080 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: chỉ mục ký hiệu cấm trong định vị lại: %d" + +#: coff-arm.c:2211 +#, c-format +msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "lá»—i: %B được biên dịch cho APCS-%d, còn %B được biên dịch cho APCS-%d" + +#: coff-arm.c:2227 elf32-arm.c:10334 +#, c-format +msgid "error: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "lá»—i: %B gá»­i trôi qua trong thanh ghi trôi, còn %B gá»­i chúng qua trong thanh ghi số nguyên" + +#: coff-arm.c:2230 elf32-arm.c:10338 +#, c-format +msgid "error: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "lá»—i: %B gá»­i trôi qua trong thanh ghi số nguyên, còn %B gá»­i chúng qua trong thanh ghi trôi" + +#: coff-arm.c:2244 +#, c-format +msgid "error: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "lá»—i: %B được biên dịch nhÆ° mã không phụ thuá»™c vào vị trí, còn %B là vị trí tuyệt đối" + +#: coff-arm.c:2247 +#, c-format +msgid "error: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "lá»—i: %B được biên dịch nhÆ° mã vị trí tuyệt đối, còn %B không phụ thuá»™c vào vị trí" + +#: coff-arm.c:2275 elf32-arm.c:10403 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Cảnh báo : %B há»— trợ ảnh hưởng lẫn nhau, còn %B thì không" + +#: coff-arm.c:2278 elf32-arm.c:10409 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Cảnh báo : %B không há»— trợ ảnh hưởng lẫn nhau, còn %B thì có" + +#: coff-arm.c:2302 +#, c-format +msgid "private flags = %x:" +msgstr "các cá» riêng = %x:" + +#: coff-arm.c:2310 elf32-arm.c:10460 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [các trôi được gá»­i qua trong thanh ghi trôi]" + +#: coff-arm.c:2312 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [các trôi được gá»­i qua trong thanh ghi số nguyên]" + +#: coff-arm.c:2315 elf32-arm.c:10463 +#, c-format +msgid " [position independent]" +msgstr " [không phụ thuá»™c vào vị trí]" + +#: coff-arm.c:2317 +#, c-format +msgid " [absolute position]" +msgstr " [vị trí tuyệt đối]" + +#: coff-arm.c:2321 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [chÆ°a sở khởi cỠảnh hưởng lẫn nhau]" + +#: coff-arm.c:2323 +#, c-format +msgid " [interworking supported]" +msgstr " [há»— trợ ảnh hưởng lẫn nhau]" + +#: coff-arm.c:2325 +#, c-format +msgid " [interworking not supported]" +msgstr " [không há»— trợ ảnh hưởng lẫn nhau]" + +#: coff-arm.c:2371 elf32-arm.c:9367 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Cảnh báo : không Ä‘ang đặt cỠảnh hưởng lẫn nhau của %B vì nó đã được xác định là không ảnh hưởng lẫn nhau" + +#: coff-arm.c:2375 elf32-arm.c:9371 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Cảnh báo : Äang xoá cỠảnh hưởng lẫn nhau của %B theo yêu cầu bên ngoài" + +#: coff-h8300.c:1122 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "không thể xá»­ lý định vị lại R_MEM_INDIRECT khi sá»­ dụng kết xuất %s" + +#: coff-i860.c:147 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "ChÆ°a thá»±c hiện định vị lại « %s »\n" + +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5143 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: cảnh báo : chỉ mục ký hiệu cấm %ld trong định vị lại" + +#: coff-i960.c:143 coff-i960.c:506 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "quy Æ°á»›c gá»i không chắc chắn cho ký hiệu khác COFF" + +#: coff-m68k.c:506 elf32-bfin.c:5691 elf32-cr16.c:2965 elf32-m68k.c:4615 +msgid "unsupported reloc type" +msgstr "kiểu định vị lại không được há»— trợ" + +#: coff-maxq.c:126 +msgid "Can't Make it a Short Jump" +msgstr "Không thể làm nó má»™t bÆ°á»›c nhảy ngắn" + +#: coff-maxq.c:191 +msgid "Exceeds Long Jump Range" +msgstr "Vượt quá phạm vi bÆ°á»›c nhảy dài" + +#: coff-maxq.c:202 coff-maxq.c:276 +msgid "Absolute address Exceeds 16 bit Range" +msgstr "Äịa chỉ tuyệt đối vượt quá phạm vi 16 bit" + +#: coff-maxq.c:240 +msgid "Absolute address Exceeds 8 bit Range" +msgstr "Äịa chỉ tuyệt đối vượt quá phạm vi 8 bit" + +#: coff-maxq.c:333 +msgid "Unrecognized Reloc Type" +msgstr "Kiểu định vị lại không được nhận ra" + +#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:441 elf32-score7.c:341 +#: elf64-mips.c:2018 elfn32-mips.c:1832 +msgid "GP relative relocation when _gp not defined" +msgstr "Có định vị lại tÆ°Æ¡ng đối GP khi chÆ°a xác định _gp" + +#: coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "Äịnh vị lại không được nhận ra" + +#: coff-rs6000.c:2789 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: kiểu định vị lại không được há»— trợ 0x%02x" + +#: coff-rs6000.c:2882 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: định vị lại TOC tại 0x%x tá»›i ký hiệu « %s » không có mục nhập TOC" + +#: coff-rs6000.c:3648 coff64-rs6000.c:2170 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: ký tá»± « %s » có smclas không nhận ra %d" + +#: coff-tic4x.c:195 coff-tic54x.c:299 coff-tic80.c:458 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Không nhận ra kiểu định vị lại 0x%x" + +#: coff-tic4x.c:240 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: cảnh báo : chỉ mục ký hiệu cấm %ld trong các định vị lại" + +#: coff-w65.c:367 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "Äang lá» Ä‘i định vị lại %s\n" + +#: coffcode.h:960 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: cảnh báo : ký hiệu COMDAT « %s » không tÆ°Æ¡ng ứng vÆ¡i tên phần « %s »" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1176 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Cảnh báo: Äang lá» Ä‘i cá» của phần IMAGE_SCN_MEM_NOT_PAGED trong phần %s" + +#: coffcode.h:1240 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Äã lá» Ä‘i cá» của phần %s (0x%x)" + +#: coffcode.h:2382 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Không nhận ra mã số đích TI COFF « 0x%x »" + +#: coffcode.h:2696 +msgid "%B: reloc against a non-existant symbol index: %ld" +msgstr "%B: định vị lại so vá»›i má»™t chỉ mục ký hiệu không tồn tại: %ld" + +#: coffcode.h:3669 +msgid "%B: section %s: string table overflow at offset %ld" +msgstr "%B: phần %s: tràn bảng chuá»—i ở hiệu %ld" + +#: coffcode.h:4477 +msgid "%B: warning: line number table read failed" +msgstr "%B: Cảnh bảo : lá»—i Ä‘á»c bảng số thứ tá»± dòng" + +#: coffcode.h:4507 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: cảnh báo : chỉ mục ký hiệu cấm %ld trong các số thứ tá»± dòng" + +#: coffcode.h:4521 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: cảnh báo : thông tin số thứ tá»± dòng trùng đối vá»›i « %s »" + +#: coffcode.h:4912 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: Không nhận ra hạng lÆ°u trữ %d cho ký hiệu %s « %s »" + +#: coffcode.h:5038 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "cảnh báo : %B: ký hiệu cục bá»™ « %s » không có phần Ä‘oạn" + +#: coffcode.h:5181 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: kiểu định vị lại cấm %d ở địa chỉ 0x%lx" + +#: coffgen.c:1573 +msgid "%B: bad string table size %lu" +msgstr "%B: kích cỡ bảng chuá»—i sai %lu" + +#: cofflink.c:513 elflink.c:4308 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Cảnh báo : kiểu ký hiệu « %s » bị thay đổi từ %d thành %d trong %B" + +#: cofflink.c:2308 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: định vị lại trong phần « %A », nhÆ°ng nó không có ná»™i dung" + +#: cofflink.c:2639 coffswap.h:826 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: tràn định vị lại: 0x%lx > 0xffff" + +#: cofflink.c:2648 coffswap.h:812 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: cảnh báo : %s: tràn số thứ tá»± dòng: 0x%lx > 0xffff" + +#: cpu-arm.c:189 cpu-arm.c:200 +msgid "error: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "lá»—i: %B được biên dịch cho EP9312, còn %B được biên dịch cho XScale" + +#: cpu-arm.c:332 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "cảnh báo : không thể cập nhật ná»™i dung của phần %s trong %s" + +#: dwarf2.c:436 +#, c-format +msgid "Dwarf Error: Can't find %s section." +msgstr "Lá»—i Dwarf: không tìm thấy phần %s." + +#: dwarf2.c:463 +#, c-format +msgid "Dwarf Error: unable to decompress %s section." +msgstr "Lá»—i Dwarf: không thể giải nén phần %s." + +#: dwarf2.c:474 +#, c-format +msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." +msgstr "Lá»—i Dwarf: Khoảng bù dòng (%lu) lá»›n hÆ¡n hoặc bằng kích cỡ %s (%lu)." + +#: dwarf2.c:871 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Lá»—i Dwarf: Giá trị FORM sai hoặc chÆ°a được xá»­ lý: %u." + +#: dwarf2.c:1085 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Lá»—i Dwarf: phần số thứ tá»± dòng đã rối (số thứ tá»± tập tin sai)." + +#: dwarf2.c:1419 +msgid "Dwarf Error: mangled line number section." +msgstr "Lá»—i Dwarf: phần số thứ tá»± dòng đã rối." + +#: dwarf2.c:1698 dwarf2.c:1806 dwarf2.c:2078 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Lá»—i Dwarf: Không tìm thấy số viết tắt %u." + +#: dwarf2.c:2039 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 and 3 information." +msgstr "Lá»—i Dwarf: tìm thấy dwarf phiên bản « %u », nhÆ°ng trình Ä‘á»c này chỉ Ä‘iá»u khiển thông tin của phiên bản 2 và 3." + +#: dwarf2.c:2046 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Lá»—i Dwarf: tìm thấy kích cỡ địa chỉ « %u », nhÆ°ng trình Ä‘á»c này không Ä‘iá»u khiển được kích cỡ lá»›n hÆ¡n « %u »." + +#: dwarf2.c:2069 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Lá»—i Dwarf: Số viết tắt sai: %u." + +#: ecoff.c:1238 +#, c-format +msgid "Unknown basic type %d" +msgstr "Không rõ kiểu cÆ¡ bản %d" + +#: ecoff.c:1495 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Ký hiệu End+1: %ld" + +#: ecoff.c:1502 ecoff.c:1505 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Ký hiệu đầu tiên: %ld" + +#: ecoff.c:1517 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Ký hiệu End+1: %-7ld Kiểu : %s" + +#: ecoff.c:1524 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Ký hiệu cục bá»™ : %ld" + +#: ecoff.c:1532 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" cấu trúc; ký hiệu End+1: %ld" + +#: ecoff.c:1537 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" kết hợp; ký hiệu End+1: %ld" + +#: ecoff.c:1542 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" đếm; ký hiệu End+1: %ld" + +#: ecoff.c:1548 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Kiểu : %s" + +#: elf-attrs.c:567 +msgid "error: %B: Must be processed by '%s' toolchain" +msgstr "lá»—i: %B: Phải được dãy công cụ « %s » xá»­ lý" + +#: elf-attrs.c:575 +msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "lá»—i: %B: thẻ đối tượng « %d, %s » không tÆ°Æ¡ng thích vá»›i thẻ « %d, %s »" + +#: elf-eh-frame.c:885 +msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" +msgstr "%P: gặp lá»—i trong %B(%A); sẽ không tạo bảng .eh_frame_hdr nào.\n" + +#: elf-eh-frame.c:1123 +msgid "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" +msgstr "%P: biên mã fde trong %B(%A) thì ngăn cản tạo bảng .eh_frame_hdr.\n" + +#: elf-ifunc.c:179 +msgid "%F%P: dynamic STT_GNU_IFUNC symbol `%s' with pointer equality in `%B' can not be used when making an executable; recompile with -fPIE and relink with -pie\n" +msgstr "%F%P: ký hiệu STT_GNU_IFUNC Ä‘á»™ng « %s » vá»›i tình trạng chất lượng con trá» trong « %B » thì không dùng được khi tạo bản thá»±c thi; hãy biên dịch lại vá»›i « -fPIE » và liên kết lại vá»›i « -pie »\n" + +#: elf-m10200.c:456 elf-m10300.c:1575 elf32-avr.c:1251 elf32-bfin.c:3204 +#: elf32-cr16.c:1517 elf32-cr16c.c:790 elf32-cris.c:2084 elf32-crx.c:933 +#: elf32-d10v.c:516 elf32-fr30.c:616 elf32-frv.c:4114 elf32-h8300.c:516 +#: elf32-i860.c:1218 elf32-ip2k.c:1499 elf32-iq2000.c:691 elf32-lm32.c:1171 +#: elf32-m32c.c:560 elf32-m32r.c:3102 elf32-m68hc1x.c:1136 elf32-mep.c:541 +#: elf32-microblaze.c:1226 elf32-moxie.c:291 elf32-msp430.c:493 elf32-mt.c:402 +#: elf32-openrisc.c:411 elf32-score.c:2752 elf32-score7.c:2591 +#: elf32-spu.c:5047 elf32-v850.c:1701 elf32-xstormy16.c:948 elf64-mmix.c:1533 +msgid "internal error: out of range error" +msgstr "lá»—i ná»™i bá»™ : lá»—i ở ngoại phạm vi" + +#: elf-m10200.c:460 elf-m10300.c:1579 elf32-avr.c:1255 elf32-bfin.c:3208 +#: elf32-cr16.c:1521 elf32-cr16c.c:794 elf32-cris.c:2088 elf32-crx.c:937 +#: elf32-d10v.c:520 elf32-fr30.c:620 elf32-frv.c:4118 elf32-h8300.c:520 +#: elf32-i860.c:1222 elf32-iq2000.c:695 elf32-lm32.c:1175 elf32-m32c.c:564 +#: elf32-m32r.c:3106 elf32-m68hc1x.c:1140 elf32-mep.c:545 +#: elf32-microblaze.c:1230 elf32-moxie.c:295 elf32-msp430.c:497 +#: elf32-openrisc.c:415 elf32-score.c:2756 elf32-score7.c:2595 +#: elf32-spu.c:5051 elf32-v850.c:1705 elf32-xstormy16.c:952 elf64-mmix.c:1537 +#: elfxx-mips.c:9103 +msgid "internal error: unsupported relocation error" +msgstr "lá»—i ná»™i bá»™ : lá»—i định vị lại không được há»— trợ" + +#: elf-m10200.c:464 elf32-cr16.c:1525 elf32-cr16c.c:798 elf32-crx.c:941 +#: elf32-d10v.c:524 elf32-h8300.c:524 elf32-lm32.c:1179 elf32-m32r.c:3110 +#: elf32-m68hc1x.c:1144 elf32-microblaze.c:1234 elf32-score.c:2760 +#: elf32-score7.c:2599 elf32-spu.c:5055 +msgid "internal error: dangerous error" +msgstr "lá»—i ná»™i bá»™ : lá»—i nguy hiểm" + +#: elf-m10200.c:468 elf-m10300.c:1592 elf32-avr.c:1263 elf32-bfin.c:3216 +#: elf32-cr16.c:1529 elf32-cr16c.c:802 elf32-cris.c:2096 elf32-crx.c:945 +#: elf32-d10v.c:528 elf32-fr30.c:628 elf32-frv.c:4126 elf32-h8300.c:528 +#: elf32-i860.c:1230 elf32-ip2k.c:1514 elf32-iq2000.c:703 elf32-lm32.c:1183 +#: elf32-m32c.c:572 elf32-m32r.c:3114 elf32-m68hc1x.c:1148 elf32-mep.c:553 +#: elf32-microblaze.c:1238 elf32-moxie.c:303 elf32-msp430.c:505 elf32-mt.c:410 +#: elf32-openrisc.c:423 elf32-score.c:2769 elf32-score7.c:2603 +#: elf32-spu.c:5059 elf32-v850.c:1725 elf32-xstormy16.c:960 elf64-mmix.c:1545 +msgid "internal error: unknown error" +msgstr "lá»—i ná»™i bá»™ : lá»—i không rõ" + +#: elf-m10300.c:1512 elf32-arm.c:8970 elf32-i386.c:3986 elf32-m32r.c:2588 +#: elf32-m68k.c:4099 elf32-ppc.c:8116 elf32-s390.c:3015 elf32-sh.c:3429 +#: elf32-xtensa.c:3027 elf64-ppc.c:12252 elf64-s390.c:2974 elf64-sh64.c:1648 +#: elf64-x86-64.c:3658 elfxx-sparc.c:3317 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): định vị lại không thể giải quyết %s đối vá»›i ký hiệu « %s »" + +#: elf-m10300.c:1584 +msgid "error: inappropriate relocation type for shared library (did you forget -fpic?)" +msgstr "lá»—i: kiểu định vị lại không thích hợp cho thÆ° viện chia sẻ (bạn đã quên đặt -fpic không?)" + +#: elf-m10300.c:1587 +msgid "internal error: suspicious relocation type used in shared library" +msgstr "lá»—i ná»™i bá»™: kiểu định vị lại đáng ngỠđược dùng trong thÆ° viện chia sẻ" + +#: elf-m10300.c:4385 elf32-arm.c:11353 elf32-cr16.c:2519 elf32-cris.c:3025 +#: elf32-hppa.c:1891 elf32-i370.c:506 elf32-i386.c:1977 elf32-lm32.c:1873 +#: elf32-m32r.c:1921 elf32-m68k.c:3188 elf32-ppc.c:5026 elf32-s390.c:1650 +#: elf32-sh.c:2574 elf32-vax.c:1052 elf64-ppc.c:6394 elf64-s390.c:1623 +#: elf64-sh64.c:3396 elf64-x86-64.c:1822 elfxx-sparc.c:1802 +#, c-format +msgid "dynamic variable `%s' is zero size" +msgstr "biến Ä‘á»™ng « %s » có kích cỡ số không" + +#: elf.c:329 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "%B: khoảng bù chuá»—i không hợp lệ %u≥%lu cho phần « %s »" + +#: elf.c:441 +msgid "%B symbol number %lu references nonexistent SHT_SYMTAB_SHNDX section" +msgstr "%B số thứ tá»± ký hiệu %lu tham chiếu đến phần SHT_SYMTAB_SHNDX không tồn tại" + +#: elf.c:597 +msgid "%B: Corrupt size field in group section header: 0x%lx" +msgstr "%B: TrÆ°á»ng kích cỡ bị há»ng trong phần đầu của phần nhóm: 0x%lx" + +#: elf.c:633 +msgid "%B: invalid SHT_GROUP entry" +msgstr "%B: mục nhập SHT_GROUP không hợp lệ" + +#: elf.c:703 +msgid "%B: no group info for section %A" +msgstr "%B: không có thông tin nhóm vá» phần %A" + +#: elf.c:732 elf.c:2979 elflink.c:9922 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "%B: cảnh báo : « sh_link » chÆ°a được đặt cho phần « %A »" + +#: elf.c:751 +msgid "%B: sh_link [%d] in section `%A' is incorrect" +msgstr "%B: sh_link [%d] không đúng trong phần « %A »" + +#: elf.c:786 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "%B: không rõ [%d] phần « %s » trong nhóm [%s]" + +#: elf.c:1106 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"Phần đầu chÆ°Æ¡ng trình:\n" + +#: elf.c:1148 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"Phần Ä‘á»™ng:\n" + +#: elf.c:1284 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"Phần định nghÄ©a phiên bản:\n" + +#: elf.c:1309 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"Tham chiếu phiên bản:\n" + +#: elf.c:1314 +#, c-format +msgid " required from %s:\n" +msgstr " cần thiết từ %s:\n" + +#: elf.c:1718 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "%B: liên kết không hợp lệ %lu cho phần định vị lại %s (chỉ mục %u)" + +#: elf.c:1886 +msgid "%B: don't know how to handle allocated, application specific section `%s' [0x%8x]" +msgstr "%B: không biết cách xá»­ lý phần đã cấp phát mà đặc trÆ°ng cho ứng dụng « %s » [0x%8x]" + +#: elf.c:1898 +msgid "%B: don't know how to handle processor specific section `%s' [0x%8x]" +msgstr "%B: không biết cách xá»­ lý phần đặc trÆ°ng cho bá»™ xá»­ lý « %s » [0x%8x]" + +#: elf.c:1909 +msgid "%B: don't know how to handle OS specific section `%s' [0x%8x]" +msgstr "%B: không biết cách xá»­ lý phần đặc trÆ°ng cho HÄH « %s » [0x%8x]" + +#: elf.c:1919 +msgid "%B: don't know how to handle section `%s' [0x%8x]" +msgstr "%B: không biết cách xá»­ lý phần « %s » [0x%8x]" + +#: elf.c:2517 +#, c-format +msgid "warning: section `%A' type changed to PROGBITS" +msgstr "cảnh báo : phần « %A » có kiểu bị thay đổi thành PROGBITS" + +#: elf.c:2936 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" +msgstr "%B: sh_link của phần « %A » chỉ tá»›i phần bị hủy « %A » của « %B »" + +#: elf.c:2959 +msgid "%B: sh_link of section `%A' points to removed section `%A' of `%B'" +msgstr "%B: sh_link của phần « %A » chỉ tá»›i phần bị gỡ bỠ« %A » của « %B »" + +#: elf.c:4333 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "%B: Phần thứ nhất trong Ä‘oạn PT_DYNAMIC không phải là phần .dynamic" + +#: elf.c:4360 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "%B: Không đủ sức chứa cho các phần đầu của chÆ°Æ¡ng trình: hãy thá»­ liên kết vá»›i « -N »" + +#: elf.c:4442 +msgid "%B: section %A vma 0x%lx overlaps previous sections" +msgstr "%B: phần %A vma 0x%lx đè lên phần trÆ°á»›c" + +#: elf.c:4537 +msgid "%B: section `%A' can't be allocated in segment %d" +msgstr "%B: phần « %A » không thể được cấp phát trong Ä‘oạn %d" + +#: elf.c:4587 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "%B: cảnh báo : phần đã cấp phát « %s » không nằm trong Ä‘oạn" + +#: elf.c:5087 +msgid "%B: symbol `%s' required but not present" +msgstr "%B: ký hiệu « %s » cần thiết mà không có" + +#: elf.c:5426 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%B: cảnh báo : Phát hiện má»™t Ä‘oạn rá»—ng có thể nạp được: trÆ°á»ng hợp này có ý định trÆ°á»›c không?\n" + +#: elf.c:6393 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "Không tìm thấy phần kết xuất tÆ°Æ¡ng Ä‘Æ°Æ¡ng cho ký hiệu « %s » từ phần « %s »" + +#: elf.c:7382 +msgid "%B: unsupported relocation type %s" +msgstr "%B: kiểu định vị lại không được há»— trợ %s" + +#: elf32-arm.c:3149 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: Thumb call to ARM" +msgstr "" +"%B(%s): cảnh báo : chÆ°a bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu: %B: thumb gá»i tá»›i ARM" + +#: elf32-arm.c:3190 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: ARM call to Thumb" +msgstr "" +"%B(%s): cảnh báo : chÆ°a bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu tiên: %B: gá»i ARM tá»›i Thumb" + +#: elf32-arm.c:3387 elf32-arm.c:4692 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "%s: không thể tạo mục nhập mẩu %s" + +#: elf32-arm.c:4804 +#, c-format +msgid "unable to find THUMB glue '%s' for '%s'" +msgstr "không tìm thấy keo hồ THUMB « %s » cho « %s »" + +#: elf32-arm.c:4838 +#, c-format +msgid "unable to find ARM glue '%s' for '%s'" +msgstr "không tìm thấy keo hồ ARM « %s » cho « %s »" + +#: elf32-arm.c:5365 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: hình ảnh BE8 chỉ đúng trong chế Ä‘á»™ vá» cuối lá»›n." + +#. Give a warning, but do as the user requests anyway. +#: elf32-arm.c:5590 +msgid "%B: warning: selected VFP11 erratum workaround is not necessary for target architecture" +msgstr "%B: cảnh báo : sá»± khắc phúc các lá»—i VFP11 đã chá»n không cần thiết cho kiến trúc đích" + +#: elf32-arm.c:6130 elf32-arm.c:6150 +msgid "%B: unable to find VFP11 veneer `%s'" +msgstr "%B: không tìm thấy lá»›p gá»— mặt VFP11 « %s »" + +#: elf32-arm.c:6196 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Kiểu định vị lại TARGET2 không hợp lệ « %s »" + +#: elf32-arm.c:6281 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): cảnh báo : chÆ°a bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu: %B: thumb gá»i tá»›i arm" + +#: elf32-arm.c:7003 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Cảnh báo : Chỉ dẫn Arm BLX đăt mục tiêu hàm Arm « %s »." + +#: elf32-arm.c:7408 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Cảnh báo : Chỉ dẫn Thumb BLX đăt mục tiêu hàm thumb « %s »." + +#: elf32-arm.c:8092 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_ARM_TLS_LE32 không cho phép định vị lại trong đối tượng dùng chung" + +#: elf32-arm.c:8307 +msgid "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations" +msgstr "%B(%A+0x%lx): Chỉ cho phép chỉ dẫn kiểu ADD (cá»™ng) hoặc SUB (trừ) khi định vị lại nhóm ALU" + +#: elf32-arm.c:8347 elf32-arm.c:8434 elf32-arm.c:8517 elf32-arm.c:8602 +msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" +msgstr "%B(%A+0x%lx): Tràn trong khi tách ra 0x%lx để định vị lại nhóm %s" + +#: elf32-arm.c:8828 elf32-sh.c:3325 elf64-sh64.c:1556 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s định vị lại đối lại phần SEC_MERGE" + +#: elf32-arm.c:8946 elf32-m68k.c:4134 elf32-xtensa.c:2765 elf64-ppc.c:10939 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "%B(%A+0x%lx): %s được dùng vá»›i ký hiệu TLS %s" + +#: elf32-arm.c:8947 elf32-m68k.c:4135 elf32-xtensa.c:2766 elf64-ppc.c:10940 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "%B(%A+0x%lx): %s được dùng vá»›i ký hiệu khác TLS %s" + +#: elf32-arm.c:9004 +msgid "out of range" +msgstr "ở ngoại phạm vi" + +#: elf32-arm.c:9008 +msgid "unsupported relocation" +msgstr "định vị lại không được há»— trợ" + +#: elf32-arm.c:9016 +msgid "unknown error" +msgstr "lá»—i không rõ" + +#: elf32-arm.c:9416 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Cảnh báo : Äang xóa cỠảnh hưởng lẫn nhau của %B vì mã không ảnh hưởng lẫn nhau trong %B đã được liên kết vá»›i nó" + +#: elf32-arm.c:9659 +msgid "error: %B: Unknown CPU architecture" +msgstr "lá»—i: %B: không rõ kiến trúc CPU" + +#: elf32-arm.c:9697 +msgid "error: %B: Conflicting CPU architectures %d/%d" +msgstr "lá»—i: %B: Các kiến trúc CPU xung Ä‘á»™t vá»›i nhau %d/%d" + +#: elf32-arm.c:9754 +msgid "error: %B uses VFP register arguments, %B does not" +msgstr "lá»—i: %B sá»­ dụng các đối số thanh ghi VFP, còn %B thì không" + +#: elf32-arm.c:9904 +msgid "error: %B: Conflicting architecture profiles %c/%c" +msgstr "lá»—i: %B: Các hồ sÆ¡ kiến trúc xung Ä‘á»™t vá»›i nhau %c/%c" + +#: elf32-arm.c:9928 +msgid "Warning: %B: Conflicting platform configuration" +msgstr "Cảnh báo : %B: cấu trúc ná»n tảng xung Ä‘á»™t" + +#: elf32-arm.c:9937 +msgid "error: %B: Conflicting use of R9" +msgstr "lá»—i; %B: Dùng R9 má»™t cách xung Ä‘á»™t" + +#: elf32-arm.c:9949 +msgid "error: %B: SB relative addressing conflicts with use of R9" +msgstr "lá»—i: %B: đạt địa chỉ tÆ°Æ¡ng đối SB cÅ©ng xung Ä‘á»™t vá»›i cách dùng R9" + +#: elf32-arm.c:9962 +msgid "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail" +msgstr "cảnh báo : %B dùng wchar_t %u-byte, còn kết xuất nên dùng wchar_t %u-byte; vì vậy có thể không thành công dùng giá trị wchar_t qua các đối tượng" + +#: elf32-arm.c:9993 +msgid "warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail" +msgstr "cảnh báo : %B dùng sá»± đếm %s, còn kết xuất nên dùng sá»± đếm %s; vì vậy có thể không thành công dùng giá trị đếm qua các đối tượng" + +#: elf32-arm.c:10005 +msgid "error: %B uses iWMMXt register arguments, %B does not" +msgstr "lá»—i: %B sá»­ dụng các đối số thanh ghi iWMMXt, còn %B thì không" + +#: elf32-arm.c:10027 +msgid "error: fp16 format mismatch between %B and %B" +msgstr "lá»—i: định dạng fp16 không tÆ°Æ¡ng ứng giữa %B và %B" + +#: elf32-arm.c:10070 elf32-arm.c:10163 +msgid "%B: Unknown mandatory EABI object attribute %d" +msgstr "%B: Không rõ thuá»™c tính đối tượng EABI %d" + +#: elf32-arm.c:10078 elf32-arm.c:10171 +msgid "Warning: %B: Unknown EABI object attribute %d" +msgstr "Cảnh báo : %B: Không rõ thuá»™c tính đối tượng EABI %d" + +#: elf32-arm.c:10231 +msgid "error: %B is already in final BE8 format" +msgstr "lá»—i: %B đã theo định dạng BE8 cuối cùng" + +#: elf32-arm.c:10307 +msgid "error: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "lá»—i: Äối tượng nguồn %B có phiên bản EABI %d, còn đích %B có phiên bản EABI %d" + +#: elf32-arm.c:10323 +msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "lá»—i: %B được biên dịch cho APCS-%d, còn đích %B sá»­ dụng APCS-%d" + +#: elf32-arm.c:10348 +msgid "error: %B uses VFP instructions, whereas %B does not" +msgstr "lá»—i: %B sá»­ dụng chỉ dẫn VFP, còn %B thì không" + +#: elf32-arm.c:10352 +msgid "error: %B uses FPA instructions, whereas %B does not" +msgstr "lá»—i: %B sá»­ dụng chỉ dẫn FPA, còn %B thì không" + +#: elf32-arm.c:10362 +msgid "error: %B uses Maverick instructions, whereas %B does not" +msgstr "lá»—i: %B sá»­ dụng chỉ dẫn Maverick, còn %B thì không" + +#: elf32-arm.c:10366 +msgid "error: %B does not use Maverick instructions, whereas %B does" +msgstr "lá»—i: %B không sá»­ dụng chỉ dẫn Maverick, còn %B thì có" + +#: elf32-arm.c:10385 +msgid "error: %B uses software FP, whereas %B uses hardware FP" +msgstr "lá»—i: %B sá»­ dụng FP phần má»m, còn %B sá»­ dụng FP phần cứng" + +#: elf32-arm.c:10389 +msgid "error: %B uses hardware FP, whereas %B uses software FP" +msgstr "lá»—i: %B sá»­ dụng FP phần cứng, còn %B sá»­ dụng FP phần má»m" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:10436 elf32-bfin.c:5080 elf32-cris.c:4105 elf32-m68hc1x.c:1280 +#: elf32-m68k.c:1169 elf32-score.c:4039 elf32-score7.c:3876 elf32-vax.c:540 +#: elfxx-mips.c:12755 +#, c-format +msgid "private flags = %lx:" +msgstr "các cá» riêng = %lx:" + +#: elf32-arm.c:10445 +#, c-format +msgid " [interworking enabled]" +msgstr " [ảnh hưởng lẫn nhau đã bật]" + +#: elf32-arm.c:10453 +#, c-format +msgid " [VFP float format]" +msgstr " [Äịnh dạng trôi VFP]" + +#: elf32-arm.c:10455 +#, c-format +msgid " [Maverick float format]" +msgstr " [Äịnh dạng trôi Maverick]" + +#: elf32-arm.c:10457 +#, c-format +msgid " [FPA float format]" +msgstr " [Äịnh dạng trôi FPA]" + +#: elf32-arm.c:10466 +#, c-format +msgid " [new ABI]" +msgstr " [ABI má»›i]" + +#: elf32-arm.c:10469 +#, c-format +msgid " [old ABI]" +msgstr " [ABI cÅ©]" + +#: elf32-arm.c:10472 +#, c-format +msgid " [software FP]" +msgstr " [FP phần má»m]" + +#: elf32-arm.c:10481 +#, c-format +msgid " [Version1 EABI]" +msgstr " [EABI phiên bản 1]" + +#: elf32-arm.c:10484 elf32-arm.c:10495 +#, c-format +msgid " [sorted symbol table]" +msgstr " [bảng ký hiệu đã sắp xếp]" + +#: elf32-arm.c:10486 elf32-arm.c:10497 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [bảng ký hiệu chÆ°a sắp xếp]" + +#: elf32-arm.c:10492 +#, c-format +msgid " [Version2 EABI]" +msgstr " [EABI phiên bản 2]" + +#: elf32-arm.c:10500 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [các ký hiệu Ä‘á»™ng sá»­ dụng chỉ mục Ä‘oạn]" + +#: elf32-arm.c:10503 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [ký hiệu ánh xạ đứng trÆ°á»›c]" + +#: elf32-arm.c:10510 +#, c-format +msgid " [Version3 EABI]" +msgstr " [EABI phiên bản 3]" + +#: elf32-arm.c:10514 +#, c-format +msgid " [Version4 EABI]" +msgstr " [EABI phiên bản 4]" + +#: elf32-arm.c:10518 +#, c-format +msgid " [Version5 EABI]" +msgstr " [EABI phiên bản 5]" + +#: elf32-arm.c:10521 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:10524 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:10530 +#, c-format +msgid " " +msgstr "" + +#: elf32-arm.c:10537 +#, c-format +msgid " [relocatable executable]" +msgstr " [tập tin có thể thá»±c hiện và định vị lại]" + +#: elf32-arm.c:10540 +#, c-format +msgid " [has entry point]" +msgstr " [có Ä‘iểm vào]" + +#: elf32-arm.c:10545 +#, c-format +msgid "" +msgstr "" + +#: elf32-arm.c:10790 elf32-i386.c:1300 elf32-s390.c:998 elf32-xtensa.c:1000 +#: elf64-s390.c:952 elf64-x86-64.c:1083 elfxx-sparc.c:1121 +msgid "%B: bad symbol index: %d" +msgstr "%B: chỉ mục ký hiệu sai: %d" + +#: elf32-arm.c:10911 elf64-x86-64.c:1243 elf64-x86-64.c:1412 elfxx-mips.c:7870 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: định vị lại %s so vá»›i « %s » không thể được dùng khi tạo má»™t đối tượng chia sẻ; hãy biên dịch lại vá»›i « -fPIC »" + +#: elf32-arm.c:11900 +#, c-format +msgid "Errors encountered processing file %s" +msgstr "Gặp lá»—i khi xá»­ lý tập tin %s" + +#: elf32-arm.c:13346 +msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" +msgstr "%B: lá»—i: mẩu mục lá»—i Cortex-A8 được cấp phát ở vị trí không an toàn" + +#. There's not much we can do apart from complain if this +#. happens. +#: elf32-arm.c:13373 +msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" +msgstr "%B: lá»—i: mẩu mục lá»—i Cortex-A8 ở ngoại phạm vi (tập tin nhập quá dài)" + +#: elf32-arm.c:13464 elf32-arm.c:13486 +msgid "%B: error: VFP11 veneer out of range" +msgstr "%B: lá»—i: lá»›p gá»— mặt VFP11 ở ngoại phạm vi" + +#: elf32-avr.c:1259 elf32-bfin.c:3212 elf32-cris.c:2092 elf32-fr30.c:624 +#: elf32-frv.c:4122 elf32-i860.c:1226 elf32-ip2k.c:1510 elf32-iq2000.c:699 +#: elf32-m32c.c:568 elf32-mep.c:549 elf32-moxie.c:299 elf32-msp430.c:501 +#: elf32-mt.c:406 elf32-openrisc.c:419 elf32-v850.c:1709 elf32-xstormy16.c:956 +#: elf64-mmix.c:1541 +msgid "internal error: dangerous relocation" +msgstr "lá»—i ná»™i bá»™ : định vị lại nguy hiểm" + +#: elf32-avr.c:2409 elf32-hppa.c:605 elf32-m68hc1x.c:165 elf64-ppc.c:4146 +msgid "%B: cannot create stub entry %s" +msgstr "%B: không thể tạo mục nhập mẩu %s" + +#: elf32-bfin.c:1581 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): định vị lại không thể giải quyết đối vá»›i ký hiệu « %s »" + +#: elf32-bfin.c:1614 elf32-i386.c:4028 elf32-m68k.c:4176 elf32-s390.c:3067 +#: elf64-s390.c:3026 elf64-x86-64.c:3698 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): định vị lại đối vá»›i « %s »: lá»—i %d" + +#: elf32-bfin.c:2718 +msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" +msgstr "%B: định vị lại ở « %A+0x%x » tham chiếu đến ký hiệu « %s » vá»›i số hạng khác không" + +#: elf32-bfin.c:2732 elf32-frv.c:2904 +msgid "relocation references symbol not defined in the module" +msgstr "định vị lại tham chiếu đến ký hiệu không được định nghÄ©a trong mô-Ä‘un" + +#: elf32-bfin.c:2829 +msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC tham chiếu đến ký hiệu Ä‘á»™ng vá»›i số hạng khác không" + +#: elf32-bfin.c:2870 elf32-bfin.c:2993 elf32-frv.c:3641 elf32-frv.c:3762 +msgid "cannot emit fixups in read-only section" +msgstr "Không thể phát ra sá»± sá»­a chữa trong phần chỉ Ä‘á»c" + +#: elf32-bfin.c:2901 elf32-bfin.c:3031 elf32-frv.c:3672 elf32-frv.c:3806 +#: elf32-lm32.c:1104 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "không thể phát ra định vị lại Ä‘á»™ng trong phần chỉ Ä‘á»c" + +#: elf32-bfin.c:2951 +msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE tham chiếu đến ký hiệu Ä‘á»™ng vá»›i số hạng khác không" + +#: elf32-bfin.c:3116 +msgid "relocations between different segments are not supported" +msgstr "không há»— trợ định vị lại giữa các Ä‘oạn khác nhau" + +#: elf32-bfin.c:3117 +msgid "warning: relocation references a different segment" +msgstr "cảnh báo : định vị lại tham chiếu đến má»™t Ä‘oạn khác" + +#: elf32-bfin.c:4972 elf32-frv.c:6408 +msgid "%B: unsupported relocation type %i" +msgstr "%B: kiểu định vị lại không được há»— trợ %i" + +#: elf32-bfin.c:5125 elf32-frv.c:6816 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: không thể liên kết tập tin đối tượng khác fdpic vào tập tin fdpic có thể thá»±c hiện" + +#: elf32-bfin.c:5129 elf32-frv.c:6820 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: không thể liên kết tập tin đối tượng khác fdpic vào tập tin khác fdpic có thể thá»±c hiện" + +#: elf32-cris.c:1169 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, phần %A: định vị lại không thể giải quyết %s đối vá»›i ký hiệu « %s »" + +#: elf32-cris.c:1238 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, phần %A: Không có PLT hoặc GOT cho định vị lại %s đối vá»›i ký hiệu « %s »" + +#: elf32-cris.c:1240 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, phần %A: Không có PLT cho định vị lại %s đối vá»›i ký hiệu « %s »" + +#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1641 elf32-cris.c:1725 +#: elf32-cris.c:1878 +msgid "[whose name is lost]" +msgstr "[mất tên của ai]" + +#: elf32-cris.c:1365 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, phần %A: định vị lại %s vá»›i số hạng khác không %d đối vá»›i ký hiệu cục bá»™" + +#: elf32-cris.c:1373 elf32-cris.c:1719 elf32-cris.c:1872 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, phần %A: định vị lại %s vá»›i số hạng khác không %d đối vá»›i ký hiệu « %s »" + +#: elf32-cris.c:1399 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, phần %A: định vị lại %s không được phép cho ký hiệu toàn cục: « %s »" + +#: elf32-cris.c:1415 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, phần %A: đã tạo định vị lại %s không có GOT" + +#. We shouldn't get here for GCC-emitted code. +#: elf32-cris.c:1632 +msgid "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a declaration mixup?" +msgstr "%B: phần %A: sá»± định vị lại $s có má»™t thàm chiếu chÆ°a xác định đến « %s », có thể khai báo không rõ ?" + +#: elf32-cris.c:2005 +msgid "%B, section %A: relocation %s is not allowed for symbol: `%s' which is defined outside the program, perhaps a declaration mixup?" +msgstr "%B, phần %A: sá»± định vị lại %s không được phép cho ký hiệu « %s » mà được xác định bên ngoài chÆ°Æ¡ng trình, có thể khai báo không rõ ?" + +#: elf32-cris.c:2058 +msgid "(too many global variables for -fpic: recompile with -fPIC)" +msgstr "(quá nhiá»u biến toàn cục đối vá»›i « -fpic »: hãy biên dịch lại vá»›i « -fPIC »)" + +#: elf32-cris.c:2065 +msgid "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or -mno-small-tls)" +msgstr "(dữ liệu cục bá»™ vá»›i mạch cÅ©ng quá lá»›n đối vá»›i « fpic » hoặc « -msmall-tls »: hãy biên dịch lại vá»›i « -fPIC » hay « -mno-small-tls »)" + +#: elf32-cris.c:3199 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, phần %A:\n" +" đối tượng tÆ°Æ¡ng thích v10/v32 %s không được chứa định vị lại PIC" + +#: elf32-cris.c:3304 +msgid "" +"%B, section %A:\n" +" relocation %s not valid in a shared object; typically an option mixup, recompile with -fPIC" +msgstr "" +"%B, phần %A:\n" +" không được sá»­ dụng sá»± định vị lại %s trong má»™t đối tượng chia sẻ; bình thÆ°á»ng do khai báo không rõ, hãy biên dịch lại vá»›i « -fPIC »" + +#: elf32-cris.c:3518 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, phần %A:\n" +" không được sá»­ dụng sá»± định vị lại %s trong má»™t đối tượng chia sẻ; hãy biên dịch lại vá»›i « -fPIC »" + +#: elf32-cris.c:3935 +msgid "" +"%B, section `%A', to symbol `%s':\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, phần « %A », tá»›i ký hiệu « %s »:\n" +" không được sá»­ dụng sá»± định vị lại %s trong má»™t đối tượng chia sẻ; hãy biên dịch lại vá»›i « -fPIC »" + +#: elf32-cris.c:4054 +msgid "Unexpected machine number" +msgstr "Số thứ tá»± máy bất thÆ°á»ng" + +#: elf32-cris.c:4108 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [ký hiệu có má»™t tiá»n tố _]" + +#: elf32-cris.c:4111 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 và v32]" + +#: elf32-cris.c:4114 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:4159 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: dùng ký hiệu tiá»n tố _, nhÆ°ng Ä‘ang ghi tập tin vá»›i ký hiệu không phải tiá»n tố" + +#: elf32-cris.c:4160 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: dùng ký hiệu không phải tiá»n tố, nhÆ°ng Ä‘ang ghi tập tin vá»›i ký hiệu có tiá»n tố _" + +#: elf32-cris.c:4179 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B chứa mã CRIS v32, không tÆ°Æ¡ng thích vá»›i các đối tượng trÆ°á»›c" + +#: elf32-cris.c:4181 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B chứa mã khác CRIS v32, không tÆ°Æ¡ng thích vá»›i các đối tượng trÆ°á»›c" + +#: elf32-frv.c:1507 elf32-frv.c:1656 +msgid "relocation requires zero addend" +msgstr "định vị lại cần thiết số hạng số không" + +#: elf32-frv.c:2891 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): định vị lại tá»›i « %s+%x » có thể gây ra lá»—i trên" + +#: elf32-frv.c:2980 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF không áp dụng tá»›i má»™t chỉ dẫn call" + +#: elf32-frv.c:3022 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 không áp dụng tá»›i má»™t chỉ dẫn lddi" + +#: elf32-frv.c:3093 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI không áp dụng tá»›i má»™t chỉ dẫn sethi" + +#: elf32-frv.c:3130 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO không áp dụng tá»›i má»™t chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3178 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX không áp dụng tá»›i má»™t chỉ dẫn ldd" + +#: elf32-frv.c:3262 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX không áp dụng tá»›i má»™t chỉ dẫn calll" + +#: elf32-frv.c:3317 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 không áp dụng tá»›i má»™t chỉ dẫn ldi" + +#: elf32-frv.c:3347 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI không áp dụng tá»›i má»™t chỉ dẫn sethi" + +#: elf32-frv.c:3376 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO không áp dụng tá»›i má»™t chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3407 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX không áp dụng tá»›i má»™t chỉ dẫn ld" + +#: elf32-frv.c:3452 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI không áp dụng tá»›i má»™t chỉ dẫn sethi" + +#: elf32-frv.c:3479 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO không áp dụng tá»›i má»™t chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3600 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC tham chiếu đến ký hiệu Ä‘á»™ng vá»›i số hạng khác không" + +#: elf32-frv.c:3720 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE tham chiếu đến ký hiệu Ä‘á»™ng vá»›i số hạng khác không" + +#: elf32-frv.c:3977 elf32-frv.c:4133 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): định vị lại đối vá»›i « %s »: %s" + +#: elf32-frv.c:3979 elf32-frv.c:3983 +msgid "relocation references a different segment" +msgstr "định vị lại tham chiếu đến má»™t Ä‘oạn khác" + +#: elf32-frv.c:6730 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: biên dịch vá»›i %s và liên kết vá»›i môđun sá»­ dụng định vị lại khác pic" + +#: elf32-frv.c:6783 elf32-iq2000.c:852 elf32-m32c.c:814 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: biên dịch vá»›i %s và liên kết vá»›i môđun biên dịch vá»›i %s" + +#: elf32-frv.c:6795 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: sá»­ dụng trÆ°á»ng e_flags không rõ (0x%lx) khác vá»›i moÄ‘un trÆ°á»›c (0x%lx)" + +#: elf32-frv.c:6845 elf32-iq2000.c:889 elf32-m32c.c:850 elf32-mt.c:583 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "các cá» riêng = 0x%lx:" + +#: elf32-gen.c:69 elf64-gen.c:69 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Äịnh vị lại trong ELF chung (EM: %d)" + +#: elf32-hppa.c:854 elf32-hppa.c:3570 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): không thể tá»›i %s, hãy biên dịch lại vá»›i « -ffunction-sections »" + +#: elf32-hppa.c:1286 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: không dùng được định vị lại %s khi tạo má»™t đối tượng chia sẽ, hãy biên dịch lại vá»›i « -fPIC »" + +#: elf32-hppa.c:2780 +msgid "%B: duplicate export stub %s" +msgstr "%B: mẩu xuất trùng %s" + +#: elf32-hppa.c:3406 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s sá»± sá»­a chữa cho chỉ dẫn 0x%x không được há»— trợ trong má»™t liên kết không chia sẻ" + +#: elf32-hppa.c:4260 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): không thể xá»­ lý %s cho %s" + +#: elf32-hppa.c:4567 +msgid ".got section not immediately after .plt section" +msgstr "Phần .got không nằm ngay sau phần .pit" + +#: elf32-i386.c:371 elf32-ppc.c:1674 elf32-s390.c:379 elf64-ppc.c:2283 +#: elf64-s390.c:403 elf64-x86-64.c:234 +msgid "%B: invalid relocation type %d" +msgstr "%B: kiểu định vị lại không hợp lệ %d" + +#: elf32-i386.c:1246 elf64-x86-64.c:1030 +msgid "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" +msgstr "%B: không thành công chuyển tiếp TLS từ %s sang %s đối vá»›i « %s » ở 0x%lx trong phần « %A »" + +#: elf32-i386.c:1387 elf32-i386.c:2972 elf64-x86-64.c:1172 elf64-x86-64.c:2681 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" +msgstr "%B: sá»± định vị lại %s đối vá»›i ký hiệu STT_GNU_IFUNC « %s » không phải được %s quản lý" + +#: elf32-i386.c:1549 elf32-s390.c:1180 elf32-sh.c:5065 elf32-xtensa.c:1173 +#: elf64-s390.c:1143 elfxx-sparc.c:1257 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: đã truy cập « %s » theo ký hiệu cả hai kiểu bình thÆ°á»ng và cục bá»™ cho mạch" + +#: elf32-i386.c:2807 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: định vị lại không được nhận ra (0x%x) trong phần « %A »" + +#: elf32-i386.c:3221 elf64-x86-64.c:3082 +msgid "hidden symbol" +msgstr "ký hiệu bị ẩn" + +#: elf32-i386.c:3224 elf64-x86-64.c:3085 +msgid "internal symbol" +msgstr "ký hiệu ná»™i bá»™" + +#: elf32-i386.c:3227 elf64-x86-64.c:3088 +msgid "protected symbol" +msgstr "ký hiệu bị bảo vệ" + +#: elf32-i386.c:3230 elf64-x86-64.c:3091 +msgid "symbol" +msgstr "ký hiệu" + +#: elf32-i386.c:3235 +msgid "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when making a shared object" +msgstr "%B: không dùng được định vị lại R_386_GOTOFF đối vá»›i %s chÆ°a xác định « %s » khi tạo má»™t đối tượng chia sẻ" + +#: elf32-i386.c:3245 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: không dùng được định vị lại R_386_GOTOFF đối vá»›i hàm số đã bảo vệ « %s » khi tạo má»™t đối tượng chia sẻ" + +#: elf32-ip2k.c:868 elf32-ip2k.c:874 elf32-ip2k.c:941 elf32-ip2k.c:947 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "trình giảm nhẹ ip2k: chuyển đổi bảng mà không có thông tin định vị lại hoàn thành." + +#: elf32-ip2k.c:891 elf32-ip2k.c:974 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "trình giảm nhẹ ip2k: bảng chuyển đổi có phần đầu bị há»ng." + +#: elf32-ip2k.c:1316 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "trình liên kết ip2k: thiếu chỉ dẫn trang tại 0x%08lx (đích = 0x%08lx)." + +#: elf32-ip2k.c:1332 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "trình liên kết ip2k: thừa chủ dẫn trang tại 0x%08lx (đích = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1506 +msgid "unsupported relocation between data/insn address spaces" +msgstr "gặp định vị lại không được há»— trợ giữa vùng địa chỉ kiểu dữ liệu và chỉ dẫn" + +#: elf32-iq2000.c:865 elf32-m32c.c:826 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: sá»­ dụng trÆ°á»ng e_flags (0x%lx) khác vá»›i mo-Ä‘un trÆ°á»›c (0x%lx)" + +#: elf32-lm32.c:698 +msgid "global pointer relative relocation when _gp not defined" +msgstr "có định vị lại tÆ°Æ¡ng đối vá»›i con trá» toàn cục khi chÆ°a xác định _gp" + +#: elf32-lm32.c:753 +msgid "global pointer relative address out of range" +msgstr "địa chỉ tÆ°Æ¡ng đối vá»›i con trá» toàn cục vẫn ở ngoại phạm vi" + +#: elf32-lm32.c:1058 +msgid "internal error: addend should be zero for R_LM32_16_GOT" +msgstr "lá»—i ná»™i bá»™ : phần cá»™ng nên là số không cho R_LM32_16_GOT" + +#: elf32-m32r.c:1453 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "định vị lại SDA khi chÆ°a xác định _SDA_BASE_" + +#: elf32-m32r.c:3039 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: Äích (%s) của má»™t định vị lại %s nằm trong phần sai (%A)" + +#: elf32-m32r.c:3567 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Bá»™ chỉ dẫn không tÆ°Æ¡ng ứng vá»›i các mô-Ä‘un trÆ°á»›c" + +#: elf32-m32r.c:3588 +#, c-format +msgid "private flags = %lx" +msgstr "các cá» riêng — %lx" + +#: elf32-m32r.c:3593 +#, c-format +msgid ": m32r instructions" +msgstr ": chỉ dẫn m32r" + +#: elf32-m32r.c:3594 +#, c-format +msgid ": m32rx instructions" +msgstr ": chỉ dẫn m32rx" + +#: elf32-m32r.c:3595 +#, c-format +msgid ": m32r2 instructions" +msgstr ": chỉ dẫn m32r2" + +#: elf32-m68hc1x.c:1048 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Tham chiếu đến ký hiệu ở xa « %s » khi sá»­ dụng má»™t định vị lại sai thì có thể dẫn đến sá»± thá»±c hiện sai" + +#: elf32-m68hc1x.c:1071 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "địa chỉ đã đặt vào khối nhá»› [%lx:%04lx] (%lx) không trong cùng khối nhá»› vá»›i địa chỉ được đặt hiện thá»i vào khối nhá»› [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1090 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "tham chiếu đến má»™t địa chỉ đã đặt vào khối nhá»› [%lx:%04lx] trong vùng địa chỉ thông thÆ°á»ng tại %04lx" + +#: elf32-m68hc1x.c:1223 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: Ä‘ang liên kết các tập tin được biên dịch cho số nguyên 16 bit (-mshort) và các tập tin khác cho số nguyên 32 bit" + +#: elf32-m68hc1x.c:1230 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: Ä‘ang liên kết các tập tin được biên dịch 32 bit đôi (-mshort) và các tập tin khác cho 64 bit đôi" + +#: elf32-m68hc1x.c:1239 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: Ä‘ang liên kết tập tin được biên dịch cho HCS12 vá»›i các tập tin khác biên dịch cho HC12" + +#: elf32-m68hc1x.c:1255 elf32-ppc.c:4262 elf64-sparc.c:698 elfxx-mips.c:12617 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: sá»­ dụng trÆ°á»ng e_flags (0x%lx) khác vá»›i mo-Ä‘un trÆ°á»›c (0x%lx)" + +#: elf32-m68hc1x.c:1283 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi=số nguyên 32-bit, " + +#: elf32-m68hc1x.c:1285 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi=số nguyên 16-bit, " + +#: elf32-m68hc1x.c:1288 +#, c-format +msgid "64-bit double, " +msgstr "64-bit đôi, " + +#: elf32-m68hc1x.c:1290 +#, c-format +msgid "32-bit double, " +msgstr "32-bit đôi, " + +#: elf32-m68hc1x.c:1293 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1295 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1297 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1300 +#, c-format +msgid " [memory=bank-model]" +msgstr " [bá»™ nhá»›=chế Ä‘á»™ khối]" + +#: elf32-m68hc1x.c:1302 +#, c-format +msgid " [memory=flat]" +msgstr " [bá»™ nhá»›=phẳng]" + +#: elf32-m68k.c:1184 elf32-m68k.c:1185 +msgid "unknown" +msgstr "không rõ" + +#: elf32-m68k.c:1645 +msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" +msgstr "%B: tràn GOT: số các sá»± định vị lại vá»›i hiệu 8-bit > %d" + +#: elf32-m68k.c:1651 +msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" +msgstr "%B: tràn GOT: số các sá»± định vị lại vá»›i hiệu 8-bit hay 16-bit > %d" + +#: elf32-m68k.c:3902 +msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" +msgstr "%B(%A+0x%lx): R_68K_TLS_LE32 không cho phép định vị lại trong đối tượng chia sẻ" + +#: elf32-mcore.c:99 elf32-mcore.c:442 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Äịnh vị lại %s (%d) hiện thá»i không được há»— trợ.\n" + +#: elf32-mcore.c:428 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Kiểu định vị lại không rõ %d\n" + +#: elf32-mep.c:654 +msgid "%B and %B are for different cores" +msgstr "%B và %B dành cho lõi khác nhau" + +#: elf32-mep.c:671 +msgid "%B and %B are for different configurations" +msgstr "%B và %B dành cho cấu hình khác nhau" + +#: elf32-mep.c:708 +#, c-format +msgid "private flags = 0x%lx" +msgstr "các cá» riêng = 0x%lx" + +#: elf32-microblaze.c:737 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s: không rõ loại định vị lại %d" + +#: elf32-microblaze.c:862 elf32-microblaze.c:907 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "%s: Äích (%s) của má»™t sá»± định vị lại %s nằm trong phần không đúng (%s)" + +#: elf32-microblaze.c:1150 elfxx-sparc.c:2957 +msgid "%B: probably compiled without -fPIC?" +msgstr "%B: rất có thể được biên dịch không có « -fPIC » ?" + +#: elf32-microblaze.c:2086 elflink.c:12457 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: tên phần định vị lại sai « %s »" + +#: elf32-mips.c:1045 elf64-mips.c:2083 elfn32-mips.c:1888 +msgid "literal relocation occurs for an external symbol" +msgstr "định vị lại nghÄ©a chữ xảy ra cho má»™t ký hiệu bên ngoài" + +#: elf32-mips.c:1085 elf32-score.c:580 elf32-score7.c:480 elf64-mips.c:2126 +#: elfn32-mips.c:1929 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "định vị lại tÆ°Æ¡ng đối 32-bit gp xảy ra cho má»™t ký hiệu bên ngoài" + +#: elf32-ppc.c:1739 +#, c-format +msgid "generic linker can't handle %s" +msgstr "trình liên kết chung không thể xá»­ lý %s" + +#: elf32-ppc.c:2219 +msgid "corrupt or empty %s section in %B" +msgstr "Gặp phần %s bị há»ng hoặc còn rá»—ng trong %B" + +#: elf32-ppc.c:2226 +msgid "unable to read in %s section from %B" +msgstr "không thể Ä‘á»c trong phần %s từ %B" + +#: elf32-ppc.c:2232 +msgid "corrupt %s section in %B" +msgstr "phần %s bị há»ng trong %b" + +#: elf32-ppc.c:2275 +msgid "warning: unable to set size of %s section in %B" +msgstr "cảnh báo : không thể đặt kích cỡ của phần %s trong %B" + +#: elf32-ppc.c:2323 +msgid "failed to allocate space for new APUinfo section." +msgstr "lá»—i cấp phát sức chứa cho phần thông tin APUinfo má»›i." + +#: elf32-ppc.c:2342 +msgid "failed to compute new APUinfo section." +msgstr "lá»—i tính phần thông tin APUinfo má»›i." + +#: elf32-ppc.c:2345 +msgid "failed to install new APUinfo section." +msgstr "lá»—i cài đặt phần thông tin APUinfo má»›i." + +#: elf32-ppc.c:3379 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: không dùng được định vị lại %s khi tạo má»™t đối tượng chia sẻ" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3732 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s định vị lại đối vá»›i ký hiệu cục bá»™" + +#: elf32-ppc.c:4074 elf32-ppc.c:4089 elfxx-mips.c:12324 elfxx-mips.c:12350 +#: elfxx-mips.c:12372 elfxx-mips.c:12398 +msgid "Warning: %B uses hard float, %B uses soft float" +msgstr "Cảnh báo : %B dùng trôi cứng, còn %B dùng trôi má»m" + +#: elf32-ppc.c:4077 elf32-ppc.c:4081 +msgid "Warning: %B uses double-precision hard float, %B uses single-precision hard float" +msgstr "Cảnh báo : %B dùng trôi cứng chính xác đôi, còn %B dùng trôi cứng chính xác Ä‘Æ¡n" + +#: elf32-ppc.c:4085 +msgid "Warning: %B uses soft float, %B uses single-precision hard float" +msgstr "Cảnh báo : %B dùng trôi má»m, còn %B dùng trôi cứng chính xác Ä‘Æ¡n" + +#: elf32-ppc.c:4092 elf32-ppc.c:4096 elfxx-mips.c:12304 elfxx-mips.c:12308 +msgid "Warning: %B uses unknown floating point ABI %d" +msgstr "Cảnh báo : %B dùng Ä‘iểm trôi không rõ ABI %d" + +#: elf32-ppc.c:4138 elf32-ppc.c:4142 +msgid "Warning: %B uses unknown vector ABI %d" +msgstr "Cảnh báo : %B dùng véc-tÆ¡ không nhận ra ABI %d" + +#: elf32-ppc.c:4146 +msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" +msgstr "Cảnh báo : %B dùng véc-tÆ¡ ABI « %s », còn %B dùng « %s »" + +#: elf32-ppc.c:4163 elf32-ppc.c:4166 +msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" +msgstr "Cảnh báo : %B dùng r3/r4 để trả lại cấu trúc nhá», %B dùng phần nhá»›" + +#: elf32-ppc.c:4169 elf32-ppc.c:4173 +msgid "Warning: %B uses unknown small structure return convention %d" +msgstr "Cảnh báo : %B dùng quy Æ°á»›c trả lại cấu trúc nhá» không rõ %d" + +#: elf32-ppc.c:4227 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: đã biên dịch vá»›i « -mrelocatable » và đã liên kết vá»›i các môđun biên dịch bình thÆ°á»ng" + +#: elf32-ppc.c:4235 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: đã biên dịch bình thÆ°á»ng và đã liên kết vá»›i các môđun biên dịch vá»›i « -mrelocatable »" + +#: elf32-ppc.c:4323 +msgid "Using bss-plt due to %B" +msgstr "Äang dùng biss-pit do %B" + +#: elf32-ppc.c:7219 elf64-ppc.c:11541 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: không rõ kiểu định vị lại %d cho ký hiệu %s" + +#: elf32-ppc.c:7480 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): số hạng khác không trên định vị lại %s đối vá»›i « %s »" + +#: elf32-ppc.c:7678 elf64-ppc.c:12043 +msgid "%B(%A+0x%lx): relocation %s for indirect function %s unsupported" +msgstr "%B(%A+0x%lx): không há»— trợ sá»± định vị lại %s cho hàm gián tiếp %s" + +#: elf32-ppc.c:7908 elf32-ppc.c:7938 elf32-ppc.c:7985 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: đích (%s) của má»™t định vị lại %s nằm trong phần kết xuất không đúng (%s)" + +#: elf32-ppc.c:8057 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: định vị lại %s chÆ°a được há»— trợ cho ký hiệu %s." + +#: elf32-ppc.c:8165 elf64-ppc.c:12299 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): %s định vị lại đối vá»›i « %s »: lá»—i %d" + +#: elf32-ppc.c:8656 +#, c-format +msgid "%s not defined in linker created %s" +msgstr "%s chÆ°a được xác định trong bá»™ liên kết được tạo %s" + +#: elf32-s390.c:2207 elf64-s390.c:2179 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): chỉ dẫn không hợp lệ cho định vị lại TLS %s" + +#: elf32-score.c:1533 elf32-score7.c:1424 elfxx-mips.c:3299 +msgid "not enough GOT space for local GOT entries" +msgstr "không đủ sức chứa GOT cho các mục nhập GOT cục bá»™" + +#: elf32-score.c:2765 +msgid "address not word align" +msgstr "địa chỉ không sắp hàng từ" + +#: elf32-score.c:2850 elf32-score7.c:2685 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "%s: định vị lại dạng sai được phát hiện cho phần %s" + +#: elf32-score.c:2901 elf32-score7.c:2736 +msgid "%B: CALL15 reloc at 0x%lx not against global symbol" +msgstr "%B: CALL15 định vị lại tại 0x%lx không phải so vá»›i ký hiệu toàn cục" + +#: elf32-score.c:4042 elf32-score7.c:3879 +#, c-format +msgid " [pic]" +msgstr " [ảnh]" + +#: elf32-score.c:4046 elf32-score7.c:3883 +#, c-format +msgid " [fix dep]" +msgstr " [sá»­a quan hệ phụ thuá»™c]" + +#: elf32-score.c:4088 elf32-score7.c:3925 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "%B: cảnh báo : Ä‘ang liên kết tập tin PIC vá»›i tập tin khác PIC" + +#: elf32-sh-symbian.c:130 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "%B: chỉ thị IMPORT AS (nhập dạng) cho %s cÅ©ng ẩn chỉ thị IMPORT AS trÆ°á»›c" + +#: elf32-sh-symbian.c:383 +msgid "%B: Unrecognised .directive command: %s" +msgstr "%B: Không nhận ra câu lệnh .directive: %s" + +#: elf32-sh-symbian.c:503 +msgid "%B: Failed to add renamed symbol %s" +msgstr "%B: Lá»—i thêm ký hiệu đã đặt tên lại %s" + +#: elf32-sh.c:533 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: cảnh báo : khoảng bù R_SH_USES sai" + +#: elf32-sh.c:545 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: cảnh báo : R_SH_USES chỉ tá»›i má»™t chỉ dẫn không nhận ra 0x%x" + +#: elf32-sh.c:562 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: cảnh báo : khoảng bù nạp R_SH_USES sai" + +#: elf32-sh.c:577 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: cảnh báo : không tìm thấy định vị lại mong đợi" + +#: elf32-sh.c:605 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: cảnh báo : ký hiệu nằm trong phần bất thÆ°á»ng" + +#: elf32-sh.c:731 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: cảnh báo : không tìm thấy định vị lại COUNT (đếm) mong đợi" + +#: elf32-sh.c:740 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: cảnh báo : đếm sai" + +#: elf32-sh.c:1144 elf32-sh.c:1514 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: lá»—i nặng: tràn định vị lại trong khi giảm nhẹ" + +#: elf32-sh.c:3270 elf64-sh64.c:1526 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Không xá»­ lý được STO_SH5_ISA32 không mong đợi trên ký hiệu cục bá»™" + +#: elf32-sh.c:3507 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "%B: 0x%lx: lá»—i nặng: có đích nhánh chÆ°a sắp hàng cho định vị lại há»— trợ giảm nhẹ" + +#: elf32-sh.c:3540 elf32-sh.c:3555 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "%B: 0x%lx: lá»—i nặng: định vị lại %s chÆ°a sắp hàng 0x%lx" + +#: elf32-sh.c:3569 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "%B: 0x%lx: lá»—i nặng: R_SH_PSHA định vị lại %d không nằm trong phạm vi -32..32" + +#: elf32-sh.c:3583 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "%B: 0x%lx: lá»—i nặng: R_SH_PSHL định vị lại %d không nằm trong phạm vi -32..32" + +#: elf32-sh.c:5256 elf64-alpha.c:4525 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "%B: mã thá»±c hiện cục bá»™ TLS không thể được liên kết vào đối tượng chia sẻ" + +#: elf32-sh64.c:222 elf64-sh64.c:2333 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: biên dịch nhÆ° má»™t đối tượng 32-bit và %s là 64-bit" + +#: elf32-sh64.c:225 elf64-sh64.c:2336 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: biên dịch nhÆ° má»™t đối tượng 64-bit và %s là 32-bit" + +#: elf32-sh64.c:227 elf64-sh64.c:2338 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: kích cỡ đối tượng không tÆ°Æ¡ng ứng vá»›i kích cỡ của đích %s" + +#: elf32-sh64.c:450 elf64-sh64.c:2852 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: gặp ký hiệu nhãn dữ liệu trong dữ liệu nhập vào" + +#: elf32-sh64.c:527 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "Sai khá»›p PTB: má»™t địa chỉ SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:530 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "Sai khá»›p PTA: má»™t địa chỉ SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:548 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: Lá»—i GAS: chỉ dẫn PTB bất thÆ°á»ng vá»›i R_SH_PT_16" + +#: elf32-sh64.c:597 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: lá»—i: kiểu định vị lại chÆ°a sắp hàng %d tại %08x định vị lại %p\n" + +#: elf32-sh64.c:673 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: không thể ghi ra các mục nhập .cranges đã thêm" + +#: elf32-sh64.c:733 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: không thể ghi ra các mục nhập .cranges đã sắp xếp" + +#: elf32-sparc.c:89 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "%B: được biên dịch cho hệ thống 64-bit, còn đích là 32-bit" + +#: elf32-sparc.c:102 +msgid "%B: linking little endian files with big endian files" +msgstr "%B: Ä‘ang liên kết tập tin vá» cuối nhá» vá»›i tập tin vá» cuối lá»›n" + +#: elf32-spu.c:713 +msgid "%X%P: overlay section %A does not start on a cache line.\n" +msgstr "%X%P: phần phủ %A không bắt đầu ở má»™t dòng nhá»› tạm.\n" + +#: elf32-spu.c:721 +msgid "%X%P: overlay section %A is larger than a cache line.\n" +msgstr "%X%P: phần phủ %A lá»›n hÆ¡n má»™t dòng nhá»› tạm.\n" + +#: elf32-spu.c:741 +msgid "%X%P: overlay section %A is not in cache area.\n" +msgstr "%X%P: phần phủ %A không phải trong vùng nhá»› tạm.\n" + +#: elf32-spu.c:781 +msgid "%X%P: overlay sections %A and %A do not start at the same address.\n" +msgstr "%X%P: hai phần phủ %A và %A không bắt đầu ở cùng má»™t địa chỉ.\n" + +#: elf32-spu.c:1005 +msgid "warning: call to non-function symbol %s defined in %B" +msgstr "cảnh báo : cuá»™c gá»i ký hiệu khác hàm %s được xác định trong %B" + +#: elf32-spu.c:1355 +msgid "%A:0x%v lrlive .brinfo (%u) differs from analysis (%u)\n" +msgstr "%A:0x%v lrlive .brinfo (%u) khác vá»›i phân tích (%u)\n" + +#: elf32-spu.c:1874 +msgid "%B is not allowed to define %s" +msgstr "không cho phép %B xác định %s" + +#: elf32-spu.c:1882 +#, c-format +msgid "you are not allowed to define %s in a script" +msgstr "không cho phép bạn xác định %s trong má»™t văn lệnh" + +#: elf32-spu.c:1916 +#, c-format +msgid "%s in overlay section" +msgstr "%s trong phần phủ" + +#: elf32-spu.c:1945 +msgid "overlay stub relocation overflow" +msgstr "tràn định vị lại mẩu phủ" + +#: elf32-spu.c:1954 elf64-ppc.c:10637 +msgid "stubs don't match calculated size" +msgstr "các mẩu không tÆ°Æ¡ng ứng vá»›i kích cỡ đã tính" + +#: elf32-spu.c:2536 +#, c-format +msgid "warning: %s overlaps %s\n" +msgstr "cảnh báo : %s đè lên %s\n" + +#: elf32-spu.c:2552 +#, c-format +msgid "warning: %s exceeds section size\n" +msgstr "cảnh báo : %s vượt quá kích cỡ phần\n" + +#: elf32-spu.c:2583 +msgid "%A:0x%v not found in function table\n" +msgstr "%A:0x%v không tìm thấy trong bảng hàm\n" + +#: elf32-spu.c:2723 +msgid "%B(%A+0x%v): call to non-code section %B(%A), analysis incomplete\n" +msgstr "%B(%A+0x%v): gá»i phần khác mã %B(%A), chÆ°a phân tích hoàn toàn\n" + +#: elf32-spu.c:3291 +#, c-format +msgid "Stack analysis will ignore the call from %s to %s\n" +msgstr "Tiến trình phân tích đống sẽ bá» qua cuá»™c gá»i từ %s cho %s\n" + +#: elf32-spu.c:3982 +msgid " %s: 0x%v\n" +msgstr " %s: 0x%v\n" + +#: elf32-spu.c:3983 +msgid "%s: 0x%v 0x%v\n" +msgstr "%s: 0x%v 0x%v\n" + +#: elf32-spu.c:3988 +msgid " calls:\n" +msgstr " cuá»™c gá»i:\n" + +#: elf32-spu.c:3996 +#, c-format +msgid " %s%s %s\n" +msgstr " %s%s %s\n" + +#: elf32-spu.c:4301 +#, c-format +msgid "%s duplicated in %s\n" +msgstr "%s bị nhân đôi trong %s\n" + +#: elf32-spu.c:4305 +#, c-format +msgid "%s duplicated\n" +msgstr "%s bị nhân đôi\n" + +#: elf32-spu.c:4312 +msgid "sorry, no support for duplicate object files in auto-overlay script\n" +msgstr "tiếc là văn lệnh tá»± Ä‘á»™ng phủ không há»— trợ tập tin đối tượng tăng đôi\n" + +#: elf32-spu.c:4353 +msgid "non-overlay size of 0x%v plus maximum overlay size of 0x%v exceeds local store\n" +msgstr "kích cỡ khác phủ 0x%v cá»™ng vá»›i kích cỡ phủ tối Ä‘a 0x%v thì vượt quá kho cục bá»™\n" + +#: elf32-spu.c:4509 +msgid "%B:%A%s exceeds overlay size\n" +msgstr "%B:%A%s vượt quá kích cỡ phủ\n" + +#: elf32-spu.c:4671 +msgid "Stack size for call graph root nodes.\n" +msgstr "Kích cỡ đống cho các nút thông tin gốc đồ thị cuá»™c gá»i.\n" + +#: elf32-spu.c:4672 +msgid "" +"\n" +"Stack size for functions. Annotations: '*' max stack, 't' tail call\n" +msgstr "" +"\n" +"Kích cỡ đống cho hàm, Ghi chú :\n" +" *\tđống tối Ä‘a\n" +" t\tcuá»™c gá»i Ä‘uôi\n" + +#: elf32-spu.c:4682 +msgid "Maximum stack required is 0x%v\n" +msgstr "Äống tối Ä‘a cần thiết là 0x%v\n" + +#: elf32-spu.c:4773 +msgid "fatal error while creating .fixup" +msgstr "gặp lá»—i nghiêm trá»ng trong khi tạo .fixup" + +#: elf32-spu.c:5011 +msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%s+0x%lx): không thể giải quyết định vị lại %s so vá»›i ký hiệu « %s »" + +#: elf32-v850.c:163 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "Biến « %s » không thể chiếm nhiá»u vùng dữ liệu nhá»" + +#: elf32-v850.c:166 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "Biến « %s » chỉ có thể nằm trong má»™t của vùng dữ liệu kiểu nhá», số không và rất nhá»" + +#: elf32-v850.c:169 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "Biến « %s » không thể nằm đồng thá»i trong cả hai vùng dữ liệu kiểu nhá» và số không" + +#: elf32-v850.c:172 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "Biến « %s » không thể nằm đồng thá»i trong cả hai vùng dữ liệu kiểu nhá» và rất nhá»" + +#: elf32-v850.c:175 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "Biến « %s » không thể nằm đồng thá»i trong cả hai vùng dữ liệu kiểu rất nhá» và số không" + +#: elf32-v850.c:478 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "Lá»–I tìm định vị lại HI16 trÆ°á»›c\n" + +#: elf32-v850.c:1713 +msgid "could not locate special linker symbol __gp" +msgstr "không tìm thấy ký hiệu liên kết đặc biệt __gp" + +#: elf32-v850.c:1717 +msgid "could not locate special linker symbol __ep" +msgstr "không tìm thấy ký hiệu liên kết đặc biệt __ep" + +#: elf32-v850.c:1721 +msgid "could not locate special linker symbol __ctbp" +msgstr "không tìm thấy ký hiệu liên kết đặc biệt __ctbp" + +#: elf32-v850.c:1871 +msgid "%B: Architecture mismatch with previous modules" +msgstr "%B: sai khá»›p kiến trúc vá»›i mô-Ä‘un khác" + +#: elf32-v850.c:1890 +#, c-format +msgid "private flags = %lx: " +msgstr "các cá» riêng — %lx: " + +#: elf32-v850.c:1895 +#, c-format +msgid "v850 architecture" +msgstr "Kiến trúc v850" + +#: elf32-v850.c:1896 +#, c-format +msgid "v850e architecture" +msgstr "Kiến trúc v850e" + +#: elf32-v850.c:1897 +#, c-format +msgid "v850e1 architecture" +msgstr "Kiến trúc v850e1" + +#: elf32-vax.c:543 +#, c-format +msgid " [nonpic]" +msgstr " [khác pic]" + +#: elf32-vax.c:546 +#, c-format +msgid " [d-float]" +msgstr " [trôi d]" + +#: elf32-vax.c:549 +#, c-format +msgid " [g-float]" +msgstr " [trôi g]" + +#: elf32-vax.c:666 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "%s: cảnh báo : số hạng GOT của %ld cho « %s » không tÆ°Æ¡ng ứng vá»›i số hạng GOT trÆ°á»›c của %ld" + +#: elf32-vax.c:1608 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "%s: cảnh báo : số hạng PLT của %d cho « %s » từ phần %s bị bá» qua" + +#: elf32-vax.c:1735 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "%s: cảnh báo : định vị lại %s so vá»›i ký hiệu « %s » từ phần %s" + +#: elf32-vax.c:1741 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "%s: cảnh báo : định vị lại %s sang 0x%x từ phần %s" + +#: elf32-xstormy16.c:451 elf32-ia64.c:2791 elf64-ia64.c:2791 +msgid "non-zero addend in @fptr reloc" +msgstr "số hạng khác không trong định vị lại @fptr" + +#: elf32-xtensa.c:912 +msgid "%B(%A): invalid property table" +msgstr "%B(%A): bảng thuá»™c tính sai" + +#: elf32-xtensa.c:2740 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "%B(%A+0x%lx): khoảng bù định vị lại ở ngoại phạm vi (kích cỡ=0x%x)" + +#: elf32-xtensa.c:2819 elf32-xtensa.c:2940 +msgid "dynamic relocation in read-only section" +msgstr "định vị lại Ä‘á»™ng trong vùng chỉ Ä‘á»c" + +#: elf32-xtensa.c:2916 +msgid "TLS relocation invalid without dynamic sections" +msgstr "Äịnh vị lại TLS không hợp lệ mà không có phần Ä‘á»™ng" + +#: elf32-xtensa.c:3133 +msgid "internal inconsistency in size of .got.loc section" +msgstr "sá»± mâu thuẫn ná»™i bá»™ trong kích cỡ của phần .got.loc" + +#: elf32-xtensa.c:3443 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "%B: kiểu máy không tÆ°Æ¡ng thích. Kết xuất là 0x%x. Dữ liệu nhập vào là 0x%x." + +#: elf32-xtensa.c:4672 elf32-xtensa.c:4680 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "Lá»—i thá»­ chuyển đổi L32R/CALLX sang CALL" + +#: elf32-xtensa.c:6290 elf32-xtensa.c:6366 elf32-xtensa.c:7482 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "%B(%A+0x%lx): không thể giải mã chỉ dẫn; có thể sai khá»›p cấu hình" + +#: elf32-xtensa.c:7222 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "%B(%A+0x%lx): không thể giải mã chỉ dẫn cho định vị lại XTENSA_ASM_SIMPLIFY; có thể sai khá»›p cấu hình" + +#: elf32-xtensa.c:8983 +msgid "invalid relocation address" +msgstr "địa chỉ định vị lại không hợp lệ" + +#: elf32-xtensa.c:9032 +msgid "overflow after relaxation" +msgstr "tràn sau khi giảm nhẹ" + +#: elf32-xtensa.c:10163 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "%B(%A+0x%lx): sá»­a chữa bất thÆ°á»ng cho định vị lại %s" + +#: elf64-alpha.c:452 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "Äịnh vị lại GPDISP không tìm thấy các chỉ dẫn ldah và lda" + +#: elf64-alpha.c:2389 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "%B: Ä‘oạn phụ .got vượt quá 64 K (kích cỡ %d)" + +#: elf64-alpha.c:4269 elf64-alpha.c:4281 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "%B: định vị lại tÆ°Æ¡ng đối vá»›i gp (gp-relative) so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf64-alpha.c:4307 elf64-alpha.c:4442 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "%B: định vị lại tÆ°Æ¡ng đối vá»›i pc (pc-relative) so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf64-alpha.c:4335 +msgid "%B: change in gp: BRSGP %s" +msgstr "%B: thay đổi trong gp: BRSGP %s" + +#: elf64-alpha.c:4360 +msgid "" +msgstr "" + +#: elf64-alpha.c:4365 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "%B: định vị lại !samegp so vá»›i ký hiệu không có .prologue: %s" + +#: elf64-alpha.c:4417 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "%B: không xá»­ lý được định vị lại Ä‘á»™ng so vá»›i %s" + +#: elf64-alpha.c:4449 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "%B: định vị lại tÆ°Æ¡ng đối vá»›i pc (pc-relative) so vá»›i ký hiệu yếu chÆ°a được xác định %s" + +#: elf64-alpha.c:4509 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "%B: định vị lại tÆ°Æ¡ng đối vá»›i dtp (dtp-relative) so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf64-alpha.c:4532 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "%B: định vị lại tÆ°Æ¡ng đối vá»›i tp (tp-relative) so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf64-hppa.c:2091 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "mục nhập mẩu cho %s không thể nạp .plt, khoảng bù dp = %ld" + +#: elf64-hppa.c:3273 +msgid "%B(%A+0x%lx): cannot reach %s" +msgstr "%B(%A+0x%lx): không thể tá»›i %s" + +#: elf64-mmix.c:1177 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" +"%s: Gặp lá»—i mâu thuẫn ná»™i bá»™ cho giá trị của thanh ghi toàn cục\n" +"cấp phát cho bá»™ liên kết:\n" +"đã liên kết: 0x%lx%08lx != đã giảm nhẹ: 0x%lx%08lx\n" + +#: elf64-mmix.c:1618 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "%s: định vị lại base-plus-offset so vá»›i ký hiệu thanh ghi: (không rõ) trong %s" + +#: elf64-mmix.c:1623 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "%s: định vị lại base-plus-offset so vá»›i ký hiệu thanh ghi: %s trong %s" + +#: elf64-mmix.c:1667 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "%s: định vị lại thanh ghi so vá»›i ký hiệu khác thanh ghi: (không rõ) trong %s" + +#: elf64-mmix.c:1672 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "%s: định vị lại thanh ghi so vá»›i ký hiệu khác thanh ghi: %s trong %s" + +#: elf64-mmix.c:1709 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s: chỉ thị LOCAL (cục bá»™) hợp lệ chỉ vá»›i má»™t thanh ghi hoặc giá trị tuyệt đối" + +#: elf64-mmix.c:1737 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "" +"%s: chỉ thị LOCAL (cục bá»™): Thanh ghi $%ld không phải là má»™t thanh ghi cục bá»™.\n" +"Thanh ghi toàn cục thứ nhất là $%ld." + +#: elf64-mmix.c:2201 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "" +"%s: Lá»—i: định nghÄ©a nhiá»u lần « %s »; đầu của %s được đặt\n" +"trong má»™t tập tin đã liên kết sá»›m hÆ¡n\n" + +#: elf64-mmix.c:2259 +msgid "Register section has contents\n" +msgstr "Phần thanh ghi có ná»™i dung\n" + +#: elf64-mmix.c:2451 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"Sá»± mâu thuẫn ná»™i bá»™ : còn lại %u != tối Ä‘a %u.\n" +" Hãy thông báo lá»—i này." + +#: elf64-ppc.c:2691 libbfd.c:978 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "%B: được biên dịch cho má»™t hệ thống vá» cuối lá»›n, còn đích vá» cuối nhá»" + +#: elf64-ppc.c:2694 libbfd.c:980 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "%B: được biên dịch cho má»™t hệ thống vá» cuối nhá», còn đích vá» cuối lá»›n" + +#: elf64-ppc.c:6384 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "định vị lại sao chép so vá»›i « %s » thì cần thiết chức năng liên kết plt uể oải; hãy tránh đặtLD_BIND_NOW=1, hoặc nân cấp GCC" + +#: elf64-ppc.c:6811 +msgid "dynreloc miscount for %B, section %A" +msgstr "sai đếm định vị lại Ä‘á»™ng cho %B, phần %A" + +#: elf64-ppc.c:6895 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "%B: .opd không phải là má»™t mảng chính quy các mục nhập opd" + +#: elf64-ppc.c:6904 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "%B: gặp kiểu định vị lại bất thÆ°á»ng %u trong phần .opd" + +#: elf64-ppc.c:6925 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "%B: gặp sym (liên kết má»m?) chÆ°a được xác định « %s » trong phần .opd" + +#: elf64-ppc.c:7767 elf64-ppc.c:8144 +#, c-format +msgid "%s defined in removed toc entry" +msgstr "%s được xác định trong mục nhập toc bị gỡ bá»" + +#: elf64-ppc.c:9085 +#, c-format +msgid "long branch stub `%s' offset overflow" +msgstr "mẩu nhánh dài « %s » tràn khoảng bù" + +#: elf64-ppc.c:9144 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "không tìm thấy mẩu nhánh « %s »" + +#: elf64-ppc.c:9206 elf64-ppc.c:9342 +#, c-format +msgid "linkage table error against `%s'" +msgstr "lá»—i bảng liên kết so vá»›i « %s »" + +#: elf64-ppc.c:9510 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "không thể xây dá»±ng mẩu nhánh « %s »" + +#: elf64-ppc.c:9995 +msgid "%B section %A exceeds stub group size" +msgstr "%B phần %A vượt quá kích cỡ nhóm mẩu" + +#: elf64-ppc.c:10649 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" +"các mẩu liên kết trong nhóm %u%s\n" +" nhánh\t\t\t\t%lu\n" +" Ä‘iá»u chỉnh toc\t\t%lu\n" +" nhánh dài\t\t\t%lu\n" +" Ä‘iá»u chỉnh toc dài\t\t%lu\n" +" cuá»™c gá»i pit\t\t\t%lu" + +#: elf64-ppc.c:11428 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "%B(%A+0x%lx): tá»± Ä‘á»™ng tạo nhiá»u TOC không được há»— trợ khi dùng các tập tin CRT của bạn; hãy biên dịch lại vá»›i « -mminimal-toc », hoặc nâng cấp GCC" + +#: elf64-ppc.c:11436 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "%B(%A+0x%lx): tối Æ°u hoá cuá»™c gá»i cùng chá»— cho « %s » không cho phép tá»± Ä‘á»™ng tạo nhiá»u TOC; hãy biên dịch lại vá»›i « -mminimal-toc » hoặc « -fno-optimize-sibling-calls », hoặc làm cho « %s » là bên ngoài" + +#: elf64-ppc.c:12150 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "%B: không há»— trợ định vị lại %s cho ký hiệu %s." + +#: elf64-ppc.c:12233 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "%B: lá»—i: định vị lại %s không phải là bá»™i số cho %d" + +#: elf64-sh64.c:1701 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "%s: lá»—i: kiểu định vị lại chÆ°a sắp hàng %d ở %08x định vị lại %08x\n" + +#: elf64-sparc.c:439 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%B: Chỉ các thanh ghi %%g[2367] có thể được tuyên bố dùng STT_REGISTER" + +#: elf64-sparc.c:459 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "Thanh ghi %%g%d được dùng má»™t cách không tÆ°Æ¡ng thích: %s trong %B, trÆ°á»›c là %s trong %b" + +#: elf64-sparc.c:482 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "Ký hiệu « %s » có các kiểu khác hau: REGISTER (thanh ghi) trong %B, trÆ°á»›c là %s trong %B" + +#: elf64-sparc.c:527 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "Ký hiệu « %s » có các kiểu khác hau: %s trong %b, trÆ°á»›c là REGISTER (thanh ghi) trong %B" + +#: elf64-sparc.c:679 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "%B: Ä‘ang liên kết UltraSPARC dứt khoát vá»›i mã đặc trÆ°ng cho HAL" + +#: elf64-x86-64.c:1338 +msgid "%B: '%s' accessed both as normal and thread local symbol" +msgstr "%B; « %s » được truy cập nhÆ° là ký hiệu cả hai kiểu bình thÆ°á»ng và mạch cục bá»™" + +#: elf64-x86-64.c:2702 +msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" +msgstr "%B: sá»± định vị lại %s đối vá»›i ký hiệu STT_GNU_IFUNC « %s » có phần cá»™ng khác số không: %d" + +#: elf64-x86-64.c:2981 +msgid "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be used when making a shared object" +msgstr "%B: định vị lại R_X86_64_GOTOFF64 so vá»›i hàm đã bảo vệ « %s » thì không thể được dùng khi tạo má»™t đối tượng chia sẻ" + +#: elf64-x86-64.c:3092 +msgid "; recompile with -fPIC" +msgstr "; biên dịch lại vá»›i « -fPIC »" + +#: elf64-x86-64.c:3097 +msgid "%B: relocation %s against %s `%s' can not be used when making a shared object%s" +msgstr "%B: không dùng được định vị lại %s đối vá»›i %s « %s » khi tạo má»™t đối tượng chia sẻ %s" + +#: elf64-x86-64.c:3099 +msgid "%B: relocation %s against undefined %s `%s' can not be used when making a shared object%s" +msgstr "%B: không dùng được định vị lại %s đối vá»›i %s chÆ°a xác định « %s » khi tạo má»™t đối tượng chia sẻ %s" + +#: elfcode.h:811 +#, c-format +msgid "warning: %s has a corrupt string table index - ignoring" +msgstr "cảnh báo : %s có má»™t chỉ mục bảng chuá»—i bị há»ng: nên bá» qua" + +#: elfcode.h:1217 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s: số đếm phiên bản (%ld) không tÆ°Æ¡ng ứng vá»›i số đếm ký hiệu (%ld)" + +#: elfcode.h:1457 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "%s(%s): định vị lại %d có chỉ mục ký hiệu không hợp lệ %ld" + +#: elfcore.h:251 +msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." +msgstr "Cảnh báo : %B bị cắt ngắn: kích cỡ tập tin lõi mong đợi ≥%lu còn tìm %lu." + +#: elflink.c:1113 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "%s: lá»i định nghÄ©a TLS trong %B phần %A không tÆ°Æ¡ng ứng vá»›i lá»i định nghÄ©a TLS trong %B phần %A" + +#: elflink.c:1117 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "%s: lá»i định nghÄ©a TLS trong %B không tÆ°Æ¡ng ứng vá»›i lá»i định nghÄ©a khác TLS trong %B" + +#: elflink.c:1121 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "%s: lá»i định nghÄ©a TLS trong %B phần %A không tÆ°Æ¡ng ứng vá»›i lá»i định nghÄ©a khác TLS trong %B" + +#: elflink.c:1125 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "%s: lá»i định nghÄ©a TLS trong %B không tÆ°Æ¡ng ứng vá»›i lá»i định nghÄ©a khác TLS trong %B phần %A" + +#: elflink.c:1764 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "%B: gặp lá»i định nghÄ©a lại bất thÆ°á»ng của ký hiệu gián tiếp đặt phiên bản « %s »" + +#: elflink.c:2077 +msgid "%B: version node not found for symbol %s" +msgstr "%B: không tìm thấy nút thông tin phiên bản cho ký hiệu %s" + +#: elflink.c:2167 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "%B: chỉ mục ký hiệu định vị lại sai (0x%lx ≥ 0x%lx) cho khoảng bù 0x%lx trong phần « %A »" + +#: elflink.c:2178 +msgid "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the object file has no symbol table" +msgstr "%B: chỉ mục ký hiệu khác số không (0x%lx) cho hiệu 0x%lx trong phần « %A » mà tập tin đối tượng không có bảng ký hiệu" + +#: elflink.c:2376 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "%B: sai khá»›p kích cỡ định vị lại trong %B phần %A" + +#: elflink.c:2679 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "cảnh báo : chÆ°a xác định kiểu và kích cỡ của ký hiệu Ä‘á»™ng « %s »" + +#: elflink.c:3425 +msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" +msgstr "%P: mã máy ELF luân phiên được tìm (%d) trong %B, còn mong đợi %d\n" + +#: elflink.c:4033 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "%B: %s: phiên bản không hợp lệ %u (tối Ä‘a %d)" + +#: elflink.c:4069 +msgid "%B: %s: invalid needed version %d" +msgstr "%B: %s: phiên bản cần thiết mà không hợp lệ %d" + +#: elflink.c:4254 +msgid "Warning: alignment %u of common symbol `%s' in %B is greater than the alignment (%u) of its section %A" +msgstr "Cảnh báo : vị trí sắp hàng %u của ký hiệu dùng chung « %s » trong %B là lá»›n hÆ¡n vị trí sắp hàng (%u) của phần %A của nó" + +#: elflink.c:4260 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "Cảnh báo : vị trí sắp hàng %u của ký hiệu « %s » trong %B là nhá» hÆ¡n %u trong %B" + +#: elflink.c:4275 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "Cảnh báo : kích cỡ của ký hiệu « %s » đã thay đổi từ %lu trong %B thành %lu trong %B" + +#: elflink.c:4440 +#, c-format +msgid "%s: invalid DSO for symbol `%s' definition" +msgstr "%s: DSO không hợp lệ cho lá»i định nghÄ©a ký hiệu « %s »" + +#: elflink.c:5692 +#, c-format +msgid "%s: undefined version: %s" +msgstr "%s: phiên bản chÆ°a được xác định: %s" + +#: elflink.c:5760 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "%B: không cho phép phần « .preinit_array » trong DSO" + +#: elflink.c:7493 +#, c-format +msgid "undefined %s reference in complex symbol: %s" +msgstr "gặp tham chiếu %s chÆ°a được xác định trong ký hiệu phức tạp %s" + +#: elflink.c:7647 +#, c-format +msgid "unknown operator '%c' in complex symbol" +msgstr "không rõ toán tá»­ « %c » trong ký hiệu phức tạp" + +#: elflink.c:7985 elflink.c:8002 elflink.c:8039 elflink.c:8056 +msgid "%B: Unable to sort relocs - they are in more than one size" +msgstr "%B: Không thể sắp xếp các sá»± định vị lại: chúng có kích cỡ khác nhau" + +#: elflink.c:8016 elflink.c:8070 +msgid "%B: Unable to sort relocs - they are of an unknown size" +msgstr "%B: Không thể sắp xếp các sá»± định vị lại: chúng có kích cỡ không rõ" + +#: elflink.c:8121 +msgid "Not enough memory to sort relocations" +msgstr "Không đủ bá»™ nhá»› để sắp xếp các sá»± định vị lại" + +#: elflink.c:8314 +msgid "%B: Too many sections: %d (>= %d)" +msgstr "%B: Quá nhiá»u phần: %d (≥ %d)" + +#: elflink.c:8550 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "%B: %s ký hiệu « %s » trong %B được DSO tham chiếu" + +#: elflink.c:8635 +msgid "%B: could not find output section %A for input section %A" +msgstr "%B: không thể tìm thấy phần kết xuất %A cho phần dữ liệu nhập vào %A" + +#: elflink.c:8755 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "%B: %s: chÆ°a xác định ký hiệu « %s »" + +#: elflink.c:9311 +msgid "error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol" +msgstr "lá»—i: %B chứa má»™t định vị lại (0x%s) cho phần %A mà tham chiếu đến má»™t ký hiệu toàn cục không tồn tại" + +#: elflink.c:9376 +msgid "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "%X« %s » được tham chiếu trong phần « %A » của %B: được định nghÄ©a trong phần bị hủy « %A » của %B\n" + +#: elflink.c:10001 +msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" +msgstr "%A có phần cả hai được sắp xếp [« %A » trong %B] và chÆ°a sắp xếp [« %A » trong %B]" + +#: elflink.c:10006 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "%A có phần cả hai được sắp xếp và chÆ°a sắp xếp" + +#: elflink.c:10882 elflink.c:10926 +msgid "%B: could not find output section %s" +msgstr "%B: không tìm thấy phần kết xuất %s" + +#: elflink.c:10887 +#, c-format +msgid "warning: %s section has zero size" +msgstr "cảnh báo : phần %s có kích cỡ số không" + +#: elflink.c:10992 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" +msgstr "%P: cảnh báo : Ä‘ang tạo má»™t DT_TEXTREL trong má»™t đối tượng chia sẻ.\n" + +#: elflink.c:11175 +msgid "%P%X: can not read symbols: %E\n" +msgstr "%P%X: không thể Ä‘á»c các ký hiệu : %E\n" + +#: elflink.c:11494 +msgid "Removing unused section '%s' in file '%B'" +msgstr "Äang gỡ bá» phần không dùng « %s » trong tập tin « %B »" + +#: elflink.c:11706 +msgid "Warning: gc-sections option ignored" +msgstr "Cảnh báo : tùy chá»n gc-sections bị bá» qua" + +#: elflink.c:12255 +msgid "%B: ignoring duplicate section `%A'" +msgstr "%B: Ä‘ang bá» qua phần trùng « %A »" + +#: elflink.c:12262 elflink.c:12269 +msgid "%B: duplicate section `%A' has different size" +msgstr "%B: phần trùng « %A » có kích cỡ khác" + +#: elflink.c:12277 elflink.c:12282 +msgid "%B: warning: could not read contents of section `%A'" +msgstr "%B: cảnh báo : không thể Ä‘á»c ná»™i dung của phần « %A »" + +#: elflink.c:12286 +msgid "%B: warning: duplicate section `%A' has different contents" +msgstr "%B: cảnh báo : phần trùng « %A » có ná»™i dung khác" + +#: elflink.c:12387 linker.c:3104 +msgid "%F%P: already_linked_table: %E\n" +msgstr "%F%P: already_linked_table: %E\n" + +#: elfxx-mips.c:1222 +msgid "static procedure (no name)" +msgstr "thủ tục tÄ©nh (không có tên)" + +#: elfxx-mips.c:5588 +msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +msgstr "%B: %A+0x%lx: nhảy tá»›i hàm mẩu mà không phải jal" + +#: elfxx-mips.c:6235 elfxx-mips.c:6458 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "%B: Cảnh báo : kích cỡ tùy chá»n « %s » sai: nhá» hÆ¡n phần đầu của nó" + +#: elfxx-mips.c:7205 elfxx-mips.c:7330 +msgid "%B: Warning: cannot determine the target function for stub section `%s'" +msgstr "%B: cảnh báo : không thể quyết định hàm đích cho phần mẩu « %s »" + +#: elfxx-mips.c:7459 +msgid "%B: Malformed reloc detected for section %s" +msgstr "%B: Phát hiện sá»± định vị lại dạng sai cho phần %s" + +#: elfxx-mips.c:7499 +msgid "%B: GOT reloc at 0x%lx not expected in executables" +msgstr "%B: định vị lại GOT ở 0x%lx không mong đợi trong tập tin có khả năng thá»±c hiện" + +#: elfxx-mips.c:7602 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "%B: định vị lại CALL16 ở 0x%lx không phải so vá»›i ký hiệu toàn cục" + +#: elfxx-mips.c:8280 +#, c-format +msgid "non-dynamic relocations refer to dynamic symbol %s" +msgstr "định vị lại khác Ä‘á»™ng cÅ©ng tham chiếu đến ký hiệu Ä‘á»™ng %s" + +#: elfxx-mips.c:8985 +msgid "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `%A'" +msgstr "%B: Không tìm thấy định vị lại LO16 tÆ°Æ¡ng ứng so vá»›i « %s » cho %s ở 0x%lx trong phần « %A »" + +#: elfxx-mips.c:9124 +msgid "small-data section exceeds 64KB; lower small-data size limit (see option -G)" +msgstr "Phần small-data (dữ liệu nhá») vượt quá 64 KB; hãy giảm giá»›i hạn dữ liệu nhá» (xem tùy chá»n « -G »)" + +#: elfxx-mips.c:11940 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s: tên phần cấm « %s »" + +#: elfxx-mips.c:12318 elfxx-mips.c:12344 +msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" +msgstr "Cảnh báo : %B dùng « -msingle-float », còn %B dùng « -mdouble-float »" + +#: elfxx-mips.c:12330 elfxx-mips.c:12386 +msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" +msgstr "Cảnh báo : %B dùng « -msingle-float », còn %B dùng « -mips32r2 -mfp64 »" + +#: elfxx-mips.c:12356 elfxx-mips.c:12392 +msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" +msgstr "Cảnh báo : %B dùng « -mdouble-float », còn %B dùng « -mips32r2 -mfp64 »" + +#: elfxx-mips.c:12434 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "%B: tình trạng vá» cuối không tÆ°Æ¡ng thích vá»›i cái của bản mô phá»ng đã chá»n" + +#: elfxx-mips.c:12445 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "%B: ABI không tÆ°Æ¡ng thích vá»›i cái của bản mô phá»ng đã chá»n" + +#: elfxx-mips.c:12526 +msgid "%B: warning: linking abicalls files with non-abicalls files" +msgstr "%B: cảnh báo : Ä‘ang liên kết tập tin abicalls vá»›i tập tin khác abicalls" + +#: elfxx-mips.c:12543 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "%B: Ä‘ang liên kết mã 32-bit vá»›i mã 64-bit" + +#: elfxx-mips.c:12571 +msgid "%B: linking %s module with previous %s modules" +msgstr "%B: Ä‘ang liên kết mô-Ä‘un %s vá»›i các mô-Ä‘un %s trÆ°á»›c" + +#: elfxx-mips.c:12594 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "%B: sai khá»›p ABI: Ä‘ang liên kết mô-Ä‘un %s vá»›i các mô-Ä‘un %s trÆ°á»›c" + +#: elfxx-mips.c:12758 +#, c-format +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:12760 +#, c-format +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:12762 +#, c-format +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:12764 +#, c-format +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:12766 +#, c-format +msgid " [abi unknown]" +msgstr " [abi không rõ]" + +#: elfxx-mips.c:12768 +#, c-format +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:12770 +#, c-format +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:12772 +#, c-format +msgid " [no abi set]" +msgstr " [chÆ°a đặt abi]" + +#: elfxx-mips.c:12793 +#, c-format +msgid " [unknown ISA]" +msgstr " [không rõ ISA]" + +#: elfxx-mips.c:12804 +#, c-format +msgid " [not 32bitmode]" +msgstr " [không phải 32bitmode]" + +#: elfxx-sparc.c:440 +#, c-format +msgid "invalid relocation type %d" +msgstr "kiểu định vị lại không hợp lệ %d" + +#: i386linux.c:455 m68klinux.c:459 sparclinux.c:453 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Tập tin kết xuất cần thiết thÆ° viện chia sẻ « %s »\n" + +#: i386linux.c:463 m68klinux.c:467 sparclinux.c:461 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Tập tin kết xuất cần thiết thÆ° viện chia sẻ « %s.so.%s »\n" + +#: i386linux.c:652 i386linux.c:702 m68klinux.c:659 m68klinux.c:707 +#: sparclinux.c:651 sparclinux.c:701 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "Ký hiệu %s chÆ°a được xác định để sá»­a chữa\n" + +#: i386linux.c:726 m68klinux.c:731 sparclinux.c:725 +msgid "Warning: fixup count mismatch\n" +msgstr "Cảnh báo : sai khá»›p số đếm sá»± sá»­a chữa\n" + +#: ieee.c:159 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s: chuá»—i quá dài (%d ký tá»±, tối Ä‘a 65535)" + +#: ieee.c:286 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s: không nhận ra ký hiêu « %s » các cá» 0x%x" + +#: ieee.c:788 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "%B: mục ghi ATI %u chÆ°a được thá»±c hiện đối vá»›i ký hiệu %u" + +#: ieee.c:812 +msgid "%B: unexpected ATN type %d in external part" +msgstr "%B: gặp kiểu ATN bất thÆ°á»ng %d trong phần bên ngoài" + +#: ieee.c:834 +msgid "%B: unexpected type after ATN" +msgstr "%B: gặp kiểu bất thÆ°á»ng đằng sau ATN" + +#: ihex.c:230 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "%B:%d: gặp ký tá»± bất thÆ°á»ng trong tập tin thập lục Intel" + +#: ihex.c:337 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%B:%d: gặp tổng kiểm sai trong tập tin thập lục Intel (đợi %u còn tìm %u)" + +#: ihex.c:392 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "%B:%d: gặp chiá»u dài mục ghi địa chỉ đã mở rá»™ng sai trong tập tin thập lục Intel" + +#: ihex.c:409 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "%B:%d: gặp chiá»u dài địa chỉ đầu đã mở rá»™ng sai trong tập tin thập lục Intel" + +#: ihex.c:426 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "%B:%d: gặp chiá»u dài mục ghi địa chỉ tuyến đã mở rá»™ng sai trong tập tin thập lục Intel" + +#: ihex.c:443 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "%B:%d: gặp chiá»u dài địa chỉ tuyến đã mở rá»™ng sai trong tập tin thập lục Intel" + +#: ihex.c:460 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "%B:%d: gặp kiểu ihex không được nhận ra %u trong tập tin thập lục Intel" + +#: ihex.c:579 +msgid "%B: internal error in ihex_read_section" +msgstr "%B: gặp lá»—i ná»™i bá»™ trong ihex_read_section" + +#: ihex.c:613 +msgid "%B: bad section length in ihex_read_section" +msgstr "%B: gặp chiá»u dài phần sai trong ihex_read_section" + +#: ihex.c:826 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "%s: địa chỉ 0x%s ở ngoại phạm vi đối vá»›i tập tin thập lục Intel" + +#: libbfd.c:1008 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "%s bị phản đối được gá»i tại dòng %s %d trong %s\n" + +#: libbfd.c:1011 +#, c-format +msgid "Deprecated %s called\n" +msgstr "%s bị phản đối được gá»i\n" + +#: linker.c:1877 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "%B: ký hiệu gián tiếp « %s » tá»›i « %s » thì tạo má»™t vòng lặp" + +#: linker.c:2744 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "Thá»­ làm liên kết có khả năng định vị lại vá»›i đầu vào %s và đầu ra %s" + +#: linker.c:3071 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "%B: cảnh báo : Ä‘ang bá» qua phần trùng « %A »\n" + +#: linker.c:3085 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "%B: cảnh báo : phần trùng « %A » có kích cỡ khác\n" + +#: mach-o.c:3195 +#, c-format +msgid "Mach-O header:\n" +msgstr "Phần đầu Mach-O :\n" + +#: mach-o.c:3196 +#, c-format +msgid " magic : %08lx\n" +msgstr " ma thuật : %08lx\n" + +#: mach-o.c:3197 +#, c-format +msgid " cputype : %08lx (%s)\n" +msgstr " kiểu CPU : %08lx (%s)\n" + +#: mach-o.c:3199 +#, c-format +msgid " cpusubtype: %08lx\n" +msgstr " kiểu phụ CPU : %08lx\n" + +#: mach-o.c:3200 +#, c-format +msgid " filetype : %08lx (%s)\n" +msgstr " kiểu tập tin : %08lx (%s)\n" + +#: mach-o.c:3203 +#, c-format +msgid " ncmds : %08lx\n" +msgstr " ncmds : %08lx\n" + +#: mach-o.c:3204 +#, c-format +msgid " sizeofcmds: %08lx\n" +msgstr " kích cỡ cmds : %08lx\n" + +#: mach-o.c:3205 +#, c-format +msgid " flags : %08lx (" +msgstr " cá» : %08lx (" + +#: mach-o.c:3207 +#, c-format +msgid ")\n" +msgstr ")\n" + +#: mach-o.c:3208 +#, c-format +msgid " reserved : %08x\n" +msgstr " dành riêng : %08x\n" + +#: mach-o.c:3218 +#, c-format +msgid "Segments and Sections:\n" +msgstr "Äoạn và Phần:\n" + +#: mach-o.c:3219 +#, c-format +msgid " #: Segment name Section name Address\n" +msgstr " #: Tên Ä‘oạn Tên phần Äịa chỉ\n" + +#: merge.c:831 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "%s: truy cập vượt quá kết thúc của phần đã gá»™p lại (%ld)" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "%s: Không có lõi nào để cấp phát tên phần %s\n" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "%s: Không có lõi nào để cấp phát má»™t ký hiệu có chiá»u dài %d byte\n" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "%s: tập tin mmo không hợp lệ: giá trị khởi tạo cho $255 không phải là « Main » (chính)\n" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "%s: dãy ký tá»± rá»™ng không được há»— trợ 0x%02X 0x%02X đằng sau tên ký hiệu bắt đầu vá»›i « %s »\n" + +#: mmo.c:1566 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "%s: tập tin mmo không hợp lệ: mã lop không được há»— trợ « %d »\n" + +#: mmo.c:1576 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "%s: tập tin mmo không hợp lệ: đợi YZ=1, còn nhận YZ=%d đối vá»›i lop_quote (trích dẫn)\n" + +#: mmo.c:1612 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "%s: tập tin mmo không hợp lệ: đợi z=1 hoặc z=2, còn nhận z=%d đối vá»›i lop_loc (định vị)\n" + +#: mmo.c:1658 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "%s: tập tin mmo không hợp lệ: đợi z=1 hoặc z=2, còn nhận z=%d đối vá»›i lop_fixo\n" + +#: mmo.c:1697 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "%s: tập tin mmo không hợp lệ: đợi y=0, còn nhận y=%d cho lop_fixrx\n" + +#: mmo.c:1706 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "%s: tập tin mmo không hợp lệ: đợi z=16 hoặc z=24, còn nhận z=%d đối vá»›i lop_fixrx\n" + +#: mmo.c:1729 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "%s: tập tin mmo không hợp lệ: byte đứng đầu của tên số hạng phải là 0 hoặc 1, còn nhận %d đối vá»›i lop_fixrx\n" + +#: mmo.c:1752 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "%s: không thể cấp phát tên tập tin cho tên số %d, %d byte\n" + +#: mmo.c:1772 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "%s: tập tin mmo không hợp lệ: tập tin số %d « %s » đã được nhập vào dạng « %s »\n" + +#: mmo.c:1785 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "%s: tập tin mmo không hợp lệ: tên tập tin cho số %d đã không được ghi rõ trÆ°á»›c khi dùng\n" + +#: mmo.c:1892 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "%s: tập tin mmo không hợp lệ: hai trÆ°á»ng y và z của lop_stab không phải là số không, y: %d, z: %d\n" + +#: mmo.c:1928 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "%s: tập tin mmo không hợp lệ: lop_end không phải là mục cuối cùng trong tập tin\n" + +#: mmo.c:1941 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "%s: tập tin mmo không hợp lệ: YZ của lop_end (%ld) không phải bằng vá»›i số tetra tá»›i lop_stab Ä‘i trÆ°á»›c (%ld)\n" + +#: mmo.c:2651 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "%s: bảng ký hiệu không hợp lệ: ký hiệu trùng « %s »\n" + +#: mmo.c:2894 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "%s: Sai xác định ký hiệu : « Main » (chính) được đặt thành %s hÆ¡n là địa chỉ đầu %s\n" + +#: mmo.c:2986 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "%s: cảnh báo : bảng ký hiệu quá lá»›n cho mmo, lá»›n hÆ¡n 65535 từ 32-bit: %d, nên chỉ phát ra « Main » (chính).\n" + +#: mmo.c:3031 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "%s: gặp lá»—i ná»™i bá»™ : bảng ký hiệu đã thay đổi kích cỡ từ %d thành %d từ\n" + +#: mmo.c:3083 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "%s: gặp lá»—i ná»™i bá»™ : phần thanh ghi ná»™i bá»™ %s có ná»™i dung\n" + +#: mmo.c:3134 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "%s: không có thanh ghi đã khởi tạo, chiá»u dài phần 0\n" + +#: mmo.c:3140 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "%s: quá nhiá»u thanh ghi đã khởi tạo ; chiá»u dài phần %ld\n" + +#: mmo.c:3145 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "%s: địa chỉ đầu không hợp lệ cho các thanh ghi đã khởi tạo có chiá»u dài %ld: 0x%lx% 08lx\n" + +#: oasys.c:881 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "%s: không thể đại diện phần « %s » theo oasys" + +#: osf-core.c:139 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "Kiểu phần tập tin lõi OSF/1 không được quản lý %d\n" + +#: pe-mips.c:613 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "%B: « ld -r » không được há»— trợ vá»›i đối tượng MIPS PE\n" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to. +#: pe-mips.c:729 +msgid "%B: unimplemented %s\n" +msgstr "%B: %s chÆ°a được thá»±c hiện\n" + +#: pe-mips.c:755 +msgid "%B: jump too far away\n" +msgstr "%B: bÆ°á»›c nhảy quá xa\n" + +#: pe-mips.c:781 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "%B: pair/reflo sai đằng sau refhi\n" + +#: pei-x86_64.c:465 +#, c-format +msgid "warning: .pdata section size (%ld) is not a multiple of %d\n" +msgstr "cảnh báo : kích cỡ phần .pdata (%ld) không phải là bá»™i số cho %d\n" + +#: pei-x86_64.c:469 peigen.c:1620 peigen.c:1799 pepigen.c:1620 pepigen.c:1799 +#: pex64igen.c:1620 pex64igen.c:1799 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" +"\n" +"Bảng Hàm (phiên dịch ná»™i dung phần .pdata)\n" + +#: pei-x86_64.c:471 +#, c-format +msgid "vma:\t\t\tBeginAddress\t EndAddress\t UnwindData\n" +msgstr "vma:\t\t\tÄịa chi đầu Äịa chỉ cuối Thông tin tháo ra\n" + +#. XXX code yet to be written. +#: peicode.h:751 +msgid "%B: Unhandled import type; %x" +msgstr "%B: Kiểu nhập không được quản lý; %x" + +#: peicode.h:756 +msgid "%B: Unrecognised import type; %x" +msgstr "%B: Kiểu nhập không được nhận ra; %x" + +#: peicode.h:770 +msgid "%B: Unrecognised import name type; %x" +msgstr "%B: Kiểu tên nhập không được nhận ra; %x" + +#: peicode.h:1160 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "%B: Kiểu máy không được nhận ra (0x%x) trong kho lÆ°u Äịnh dạng ThÆ° viện Nhập" + +#: peicode.h:1172 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "%B: Kiểu máy được nhận ra còn không được quản lý (0x%x) trong kho lÆ°u Äịnh dạng ThÆ° viện Nhập" + +#: peicode.h:1190 +msgid "%B: size field is zero in Import Library Format header" +msgstr "%B: trÆ°á»ng kích cỡ là số không trong phần đầu Äịnh dạng ThÆ° viện Nhập" + +#: peicode.h:1221 +msgid "%B: string not null terminated in ILF object file." +msgstr "%B: chuá»—i không phải kết thúc vô hiệu lá»±c trong tập tin đối tượng ILF. " + +#: ppcboot.c:414 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" +"\n" +"Phần đầu ppcboot:\n" + +#: ppcboot.c:415 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "Khoảng bù vào = 0x%.8lx (%ld)\n" + +#: ppcboot.c:417 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "Dài = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "TrÆ°á»ng cá» = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "Tên phân vùng = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"Phân vùng[%d] đầu = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "Phân vùng[%d] cuối = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "Phân vùng[%d] rãnh ghi = 0x%.8lx (%ld)\n" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "Phân vùng[%d] dài = 0x%.8lx (%ld)\n" + +#: som.c:5114 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" +"\n" +"Phần đầu phụ thá»±c hiện\n" + +#: som.c:5417 +msgid "som_sizeof_headers unimplemented" +msgstr "som_sizeof_headers chÆ°a được thá»±c hiện" + +#: srec.c:261 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "%B:%d Gặp ký tá»± bất thÆ°á»ng « %s » trong tập tin S-record\n" + +#: srec.c:567 srec.c:600 +msgid "%B:%d: Bad checksum in S-record file\n" +msgstr "%B:%d: sai tổng kiểm trong tập tin S-record\n" + +#: stabs.c:279 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "%B(%A+0x%lx): Mục nhập Stabs có chỉ mục chuá»—i không hợp lệ." + +#: syms.c:1079 +msgid "Unsupported .stab relocation" +msgstr "Äịnh vị lại .stab không được há»— trợ" + +#: vms-gsd.c:350 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "bfd_make_section (%s) bị lá»—i" + +#: vms-gsd.c:365 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "bfd_set_section_flags (%s, %x) bị lá»—i" + +#: vms-gsd.c:399 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "Sai khá»›p phần %s=%lx, %s=%lx" + +#: vms-gsd.c:754 +#, c-format +msgid "Unknown GSD/EGSD subtype %d" +msgstr "Không rõ kiểu phụ GSD/EGSD %d" + +#: vms-hdr.c:364 +msgid "Object module NOT error-free !\n" +msgstr "Mô-Ä‘un đối tượng KHÔNG phải miá»…n lá»—i !\n" + +#: vms-hdr.c:878 +#, c-format +msgid "unknown source command %d" +msgstr "không rõ câu lệnh nguồn %d" + +#: vms-hdr.c:951 +msgid "DST_S_C_SET_LINUM_INCR not implemented" +msgstr "DST_S_C_SET_LINUM_INCR chÆ°a được thá»±c hiện" + +#: vms-hdr.c:957 +msgid "DST_S_C_SET_LINUM_INCR_W not implemented" +msgstr "DST_S_C_SET_LINUM_INCR_W chÆ°a được thá»±c hiện" + +#: vms-hdr.c:963 +msgid "DST_S_C_RESET_LINUM_INCR not implemented" +msgstr "DST_S_C_RESET_LINUM_INCR chÆ°a được thá»±c hiện" + +#: vms-hdr.c:969 +msgid "DST_S_C_BEG_STMT_MODE not implemented" +msgstr "DST_S_C_BEG_STMT_MODE chÆ°a được thá»±c hiện" + +#: vms-hdr.c:975 +msgid "DST_S_C_END_STMT_MODE not implemented" +msgstr "DST_S_C_END_STMT_MODE chÆ°a được thá»±c hiện" + +#: vms-hdr.c:1008 +msgid "DST_S_C_SET_PC not implemented" +msgstr "DST_S_C_SET_PC chÆ°a được thá»±c hiện" + +#: vms-hdr.c:1014 +msgid "DST_S_C_SET_PC_W not implemented" +msgstr "DST_S_C_SET_PC_W chÆ°a được thá»±c hiện" + +#: vms-hdr.c:1020 +msgid "DST_S_C_SET_PC_L not implemented" +msgstr "DST_S_C_SET_PC_L chÆ°a được thá»±c hiện" + +#: vms-hdr.c:1026 +msgid "DST_S_C_SET_STMTNUM not implemented" +msgstr "DST_S_C_SET_STMTNUM chÆ°a được thá»±c hiện" + +#: vms-hdr.c:1079 +#, c-format +msgid "unknown line command %d" +msgstr "không rõ câu lệnh dòng %d" + +#: vms-misc.c:588 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "Tràn đống (%d) trong _bfd_vms_push" + +#: vms-misc.c:603 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "Trán ngược đống trong _bfd_vms_pop" + +#: vms-misc.c:844 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "_bfd_vms_output_counted được gá»i vá»›i số không byte" + +#: vms-misc.c:849 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "_bfd_vms_output_counted được gá»i vá»›i quá nhiá»u byte" + +#: vms-misc.c:967 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "Ký hiệu %s đã bị thay thế bằng %s\n" + +#: vms-misc.c:1026 +#, c-format +msgid "failed to enter %s" +msgstr "lá»—i vào %s" + +#: vms-tir.c:83 +msgid "No Mem !" +msgstr "Không có Mem !" + +#. These names have not yet been added to this switch statement. +#: vms-tir.c:346 +#, c-format +msgid "unknown ETIR command %d" +msgstr "không rõ câu lệnh ETIR %d" + +#: vms-tir.c:440 +#, c-format +msgid "bad section index in %s" +msgstr "chỉ mục phần sai trong %s" + +#: vms-tir.c:459 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "câu lệnh STA không được há»— trợ %s" + +#: vms-tir.c:464 vms-tir.c:1304 +#, c-format +msgid "reserved STA cmd %d" +msgstr "câu lệnh STA dành riêng %d" + +#. Unsigned shift. +#. Rotate. +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:655 vms-tir.c:774 vms-tir.c:894 vms-tir.c:1624 +#, c-format +msgid "%s: not supported" +msgstr "%s: không được há»— trợ" + +#: vms-tir.c:661 vms-tir.c:1481 +#, c-format +msgid "%s: not implemented" +msgstr "%s: chÆ°a được thá»±c hiện" + +#: vms-tir.c:666 vms-tir.c:1485 +#, c-format +msgid "reserved STO cmd %d" +msgstr "câu lệnh STO dành riêng %d" + +#: vms-tir.c:789 vms-tir.c:1629 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "câu lệnh OPR dành riêng %d" + +#: vms-tir.c:852 vms-tir.c:1693 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "câu lệnh CTL dành riêng %d" + +#: vms-tir.c:966 +#, c-format +msgid "reserved STC cmd %d" +msgstr "câu lệnh STC dành riêng %d" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1212 +msgid "stack-from-image not implemented" +msgstr "stack-from-image chÆ°a được thá»±c hiện" + +#: vms-tir.c:1230 +msgid "stack-entry-mask not fully implemented" +msgstr "stack-entry-mask chÆ°a được thá»±c hiện hoàn toàn" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1244 +msgid "PASSMECH not fully implemented" +msgstr "PASSMECH chÆ°a được thá»±c hiện hoàn toàn" + +#: vms-tir.c:1263 +msgid "stack-local-symbol not fully implemented" +msgstr "stack-local-symbol chÆ°a được thá»±c hiện hoàn toàn" + +#: vms-tir.c:1276 +msgid "stack-literal not fully implemented" +msgstr "stack-literal chÆ°a được thá»±c hiện hoàn toàn" + +#: vms-tir.c:1297 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "stack-local-symbol-entry-point-mask chÆ°a được thá»±c hiện hoàn toàn" + +#: vms-tir.c:1571 vms-tir.c:1583 vms-tir.c:1595 vms-tir.c:1607 vms-tir.c:1672 +#: vms-tir.c:1680 vms-tir.c:1688 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s: chÆ°a được thá»±c hiện hoàn toàn" + +#: vms-tir.c:1746 +#, c-format +msgid "obj code %d not found" +msgstr "Không tìm thấy mã đối tượng %d" + +#: vms-tir.c:2019 +#, c-format +msgid "Reloc size error in section %s" +msgstr "Gặp lá»—i kích cỡ sá»± định vị lại trong phần %s" + +#: vms-tir.c:2112 vms-tir.c:2129 vms-tir.c:2147 vms-tir.c:2159 vms-tir.c:2170 +#: vms-tir.c:2182 +#, c-format +msgid "Unknown reloc %s + %s" +msgstr "Không rõ sá»± định vị lại %s + %s" + +#: vms-tir.c:2249 +#, c-format +msgid "Unknown symbol %s in command %s" +msgstr "Gặp ký hiệu lạ %s trong câu lệnh %s" + +#: vms-tir.c:2504 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "SEC_RELOC không có định vị lại trong phần %s" + +#: vms-tir.c:2556 vms-tir.c:2783 +#, c-format +msgid "Size error in section %s" +msgstr "Gặp lá»—i kích cỡ trong phần %s" + +#: vms-tir.c:2725 +msgid "Spurious ALPHA_R_BSR reloc" +msgstr "Gặp sá»± định vị lại ALPHA_R_BSR giả" + +#: vms-tir.c:2770 +#, c-format +msgid "Unhandled relocation %s" +msgstr "Äịnh vị lại không được quản lý %s" + +#: xcofflink.c:836 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "%s: có đối tượng dùng chung XCOFF khi không xuất dữ liệu XCOFF" + +#: xcofflink.c:857 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "%s đối tượng Ä‘á»™ng không có phần .loader" + +#: xcofflink.c:1415 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "%B: « %s » có số thứ tá»± dòng mà không có phần bao bá»c" + +#: xcofflink.c:1467 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "%B: hạng %d ký hiệu « %s » không có mục nhập phụ" + +#: xcofflink.c:1489 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "%B: ký hiệu « %s » có kiểu csect không được nhận ra %d" + +#: xcofflink.c:1501 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "%B: ký hiệu XTY_ER sai « %s » hạng %d scnum %d scnlen %d" + +#: xcofflink.c:1530 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "%B: ký hiệu XMC_TC0 « %s » là hạng %d scnlen %d" + +#: xcofflink.c:1676 +msgid "%B: csect `%s' not in enclosing section" +msgstr "%B: csect « %s » không phải trong phần bao bá»c" + +#: xcofflink.c:1783 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "%B: không đúng chá»— XTY_LD « %s »" + +#: xcofflink.c:2102 +msgid "%B: reloc %s:%d not in csect" +msgstr "%B: định vị lại %s:%d không phải trong csect" + +#: xcofflink.c:3177 +#, c-format +msgid "%s: no such symbol" +msgstr "%s: không có ký hiệu nhÆ° vậy" + +#: xcofflink.c:3282 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "cảnh báo : thá»­ xuất ký hiệu chÆ°a được xác định « %s »" + +#: xcofflink.c:3664 +msgid "error: undefined symbol __rtinit" +msgstr "lá»—i: chÆ°a xác định ký hiệu __rtinit" + +#: xcofflink.c:4041 +msgid "%B: loader reloc in unrecognized section `%s'" +msgstr "%B: gặp sá»± định vị lại bá»™ nạp trong phần không được nhận ra « %s »" + +#: xcofflink.c:4052 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "%B: « %s » trong định vị lại bá»™ nạp nhÆ°ng không phải liên kết má»m đến bá»™ nạp" + +#: xcofflink.c:4068 +msgid "%B: loader reloc in read-only section %A" +msgstr "%B: định vị lại bá»™ nạp trong phần chỉ Ä‘á»c %A" + +#: xcofflink.c:5086 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "Tràn TOC: 0x%lx > 0x10000; hãy thá»­ « -mminimal-toc » khi biên dịch" + +#: elf32-ia64.c:1050 elf64-ia64.c:1050 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "%B: Không thể giảm nhẹ br ở 0x%lx trong phần « %A ». Hãy dùng brl hoặc nhánh gián tiếp." + +#: elf32-ia64.c:2739 elf64-ia64.c:2739 +msgid "@pltoff reloc against local symbol" +msgstr "định vị lại @pltoff so vá»›i ký hiệu cục bá»™" + +#: elf32-ia64.c:4314 elf64-ia64.c:4314 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "%s: tràn Ä‘oạn dữ liệu ngắn (0x%lx ≥ 0x400000)" + +#: elf32-ia64.c:4325 elf64-ia64.c:4325 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "%s: __gp không trải ra Ä‘oạn dữ liệu ngắn" + +#: elf32-ia64.c:4595 elf64-ia64.c:4595 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "%B: mã khác pic vá»›i định vị lại imm so vá»›i ký hiệu Ä‘á»™ng « %s »" + +#: elf32-ia64.c:4662 elf64-ia64.c:4662 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "%B: định vị lại @gprel so vá»›i ký hiệu Ä‘á»™ng « %s »" + +#: elf32-ia64.c:4725 elf64-ia64.c:4725 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "%B: Ä‘ang liên kết mã khác pin trong má»™t tập tin có khả năng thá»±c hiện mà không phụ thuá»™c vào vị trí" + +#: elf32-ia64.c:4862 elf64-ia64.c:4862 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "%B: nhánh @internal (ná»™i bá»™) tá»›i ký hiệu Ä‘á»™ng %s" + +#: elf32-ia64.c:4864 elf64-ia64.c:4864 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "%B: sá»± sá»­a chữa suy Ä‘oán so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf32-ia64.c:4866 elf64-ia64.c:4866 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "%B: định vị lại @pcrel so vá»›i ký hiệu Ä‘á»™ng %s" + +#: elf32-ia64.c:5063 elf64-ia64.c:5063 +msgid "unsupported reloc" +msgstr "định vị lại không được há»— trợ" + +#: elf32-ia64.c:5101 elf64-ia64.c:5101 +msgid "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `%A'." +msgstr "%B: thiếu phần TLS để định vị lại %s đối vá»›i « %s » ở 0x%lx trong phần « %A »." + +#: elf32-ia64.c:5116 elf64-ia64.c:5116 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "%B: Không thể giảm nhẹ br (%s) tá»›i « %s » tại 0x%lx trong phần « %A » vá»›i kích cỡ 0x%lx (> 0x1000000)." + +#: elf32-ia64.c:5372 elf64-ia64.c:5372 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "%B: Ä‘ang liên kết trap-on-NULL-dereference vá»›i tập tin không đặt bẫy" + +#: elf32-ia64.c:5381 elf64-ia64.c:5381 +msgid "%B: linking big-endian files with little-endian files" +msgstr "%B: Ä‘ang liên kết tập tin vá» cuối lá»›n vá»›i tập tin vá» cuối nhá»" + +#: elf32-ia64.c:5390 elf64-ia64.c:5390 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "%B: Ä‘ang liên kết tập tin 64-bit vá»›i tập tin 32-bit" + +#: elf32-ia64.c:5399 elf64-ia64.c:5399 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "%B: Ä‘ang liên kết tập tin constant-gp vá»›i tập tin non-constant-gp" + +#: elf32-ia64.c:5409 elf64-ia64.c:5409 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "%B: Ä‘ang liên kết tập tin auto-pic vá»›i tập tin non-auto-pic" + +#: peigen.c:999 pepigen.c:999 pex64igen.c:999 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: tràn số thứ tá»± dòng: 0x%lx > 0xffff" + +#: peigen.c:1026 pepigen.c:1026 pex64igen.c:1026 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "ThÆ° mục Xuất [.edata (hoặc ở nÆ¡i nào chúng ta đã tìm nó)]" + +#: peigen.c:1027 pepigen.c:1027 pex64igen.c:1027 +msgid "Import Directory [parts of .idata]" +msgstr "ThÆ° mục Nhập [các phần của .idata]" + +#: peigen.c:1028 pepigen.c:1028 pex64igen.c:1028 +msgid "Resource Directory [.rsrc]" +msgstr "ThÆ° mục Tài nguyên [.rsrc]" + +#: peigen.c:1029 pepigen.c:1029 pex64igen.c:1029 +msgid "Exception Directory [.pdata]" +msgstr "ThÆ° mục Ngoại lệ [.pdata]" + +#: peigen.c:1030 pepigen.c:1030 pex64igen.c:1030 +msgid "Security Directory" +msgstr "ThÆ° mục Bảo mật" + +#: peigen.c:1031 pepigen.c:1031 pex64igen.c:1031 +msgid "Base Relocation Directory [.reloc]" +msgstr "ThÆ° mục Äịnh vị lại CÆ¡ bản [.reloc]" + +#: peigen.c:1032 pepigen.c:1032 pex64igen.c:1032 +msgid "Debug Directory" +msgstr "ThÆ° mục Gỡ lá»—i" + +#: peigen.c:1033 pepigen.c:1033 pex64igen.c:1033 +msgid "Description Directory" +msgstr "ThÆ° mục Mô tả" + +#: peigen.c:1034 pepigen.c:1034 pex64igen.c:1034 +msgid "Special Directory" +msgstr "ThÆ° mục Äặc biệt" + +#: peigen.c:1035 pepigen.c:1035 pex64igen.c:1035 +msgid "Thread Storage Directory [.tls]" +msgstr "ThÆ° mục LÆ°u trữ Mạch [.tls]" + +#: peigen.c:1036 pepigen.c:1036 pex64igen.c:1036 +msgid "Load Configuration Directory" +msgstr "ThÆ° mục Cấu hình Nạp" + +#: peigen.c:1037 pepigen.c:1037 pex64igen.c:1037 +msgid "Bound Import Directory" +msgstr "ThÆ° mục Nhập đã Äóng kết" + +#: peigen.c:1038 pepigen.c:1038 pex64igen.c:1038 +msgid "Import Address Table Directory" +msgstr "ThÆ° mục Bảng Äịa chỉ Nhập" + +#: peigen.c:1039 pepigen.c:1039 pex64igen.c:1039 +msgid "Delay Import Directory" +msgstr "ThÆ° mục Nhập Hoãn" + +#: peigen.c:1040 pepigen.c:1040 pex64igen.c:1040 +msgid "CLR Runtime Header" +msgstr "Phần đầu Lúc chạy CLR" + +#: peigen.c:1041 pepigen.c:1041 pex64igen.c:1041 +msgid "Reserved" +msgstr "Dành riêng" + +#: peigen.c:1101 pepigen.c:1101 pex64igen.c:1101 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Có má»™t bảng nhập, nhÆ°ng không tìm thấy phần chứa nó\n" + +#: peigen.c:1106 pepigen.c:1106 pex64igen.c:1106 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" +"\n" +"Có má»™t bảng nhập trong %s tại 0x%lx\n" + +#: peigen.c:1149 pepigen.c:1149 pex64igen.c:1149 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" +"\n" +"Bá»™ mô tả hàm được tìm tại địa chỉ đầu : %04lx\n" + +#: peigen.c:1152 pepigen.c:1152 pex64igen.c:1152 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "\tcÆ¡ bản mã %08lx toc (nạp được/thật) %08lx/%08lx\n" + +#: peigen.c:1160 pepigen.c:1160 pex64igen.c:1160 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" +"\n" +"Không có phần reldata ! Vì thế chÆ°a giải mã bá»™ mô tả hàm.\n" + +#: peigen.c:1165 pepigen.c:1165 pex64igen.c:1165 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" +"\n" +"Các Bảng Nhập (phiên dịch %s ná»™i dung phần)\n" + +#: peigen.c:1168 pepigen.c:1168 pex64igen.c:1168 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" +" vma: Gợi ý Giá» Tiếp DLL Äầu\n" +" Bảng Nhãn Dây Tên Thunk\n" + +#: peigen.c:1216 pepigen.c:1216 pex64igen.c:1216 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tTên DLL: %s\n" + +#: peigen.c:1227 pepigen.c:1227 pex64igen.c:1227 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "\tvma: Gợi_ý/Thứ_tá»± Tên_thành_viên Äóng_kết_vá»›i\n" + +#: peigen.c:1252 pepigen.c:1252 pex64igen.c:1252 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" +"\n" +"Có má»™t thunk đầu tiên, nhÆ°ng không tìm thấy phần chứa nó\n" + +#: peigen.c:1417 pepigen.c:1417 pex64igen.c:1417 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" +"\n" +"Có má»™t bảng xuất, nhÆ°ng không tìm thấy phần chứa nó\n" + +#: peigen.c:1426 pepigen.c:1426 pex64igen.c:1426 +#, c-format +msgid "" +"\n" +"There is an export table in %s, but it does not fit into that section\n" +msgstr "" +"\n" +"Có má»™t bảng xuất trong %s, nhÆ°ng nó không vừa trong phần đó\n" + +#: peigen.c:1432 pepigen.c:1432 pex64igen.c:1432 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"Có má»™t bảng xuất trong %s tại 0x%lx\n" + +#: peigen.c:1460 pepigen.c:1460 pex64igen.c:1460 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" +"\n" +"Các Bảng Xuất (phiên dịch %s ná»™i dung phần)\n" + +#: peigen.c:1464 pepigen.c:1464 pex64igen.c:1464 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "Cá» xuất \t\t\t%lx\n" + +#: peigen.c:1467 pepigen.c:1467 pex64igen.c:1467 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "Nhãn Ngày/Giá» \t\t%lx\n" + +#: peigen.c:1470 pepigen.c:1470 pex64igen.c:1470 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "Chính/Phụ \t\t\t%d/%d\n" + +#: peigen.c:1473 pepigen.c:1473 pex64igen.c:1473 +#, c-format +msgid "Name \t\t\t\t" +msgstr "Tên \t\t\t\t" + +#: peigen.c:1479 pepigen.c:1479 pex64igen.c:1479 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "CÆ¡ bản thứ tá»± \t\t\t%ld\n" + +#: peigen.c:1482 pepigen.c:1482 pex64igen.c:1482 +#, c-format +msgid "Number in:\n" +msgstr "Số trong:\n" + +#: peigen.c:1485 pepigen.c:1485 pex64igen.c:1485 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "\tBảng Äịa chỉ Xuất \t\t%08lx\n" + +#: peigen.c:1489 pepigen.c:1489 pex64igen.c:1489 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "\t[Cái_chỉ_tên/Thứ_tá»±] Bảng\t%08lx\n" + +#: peigen.c:1492 pepigen.c:1492 pex64igen.c:1492 +#, c-format +msgid "Table Addresses\n" +msgstr "Äịa chỉ bảng\n" + +#: peigen.c:1495 pepigen.c:1495 pex64igen.c:1495 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "\tBảng Äịa chỉ Xuất \t\t" + +#: peigen.c:1500 pepigen.c:1500 pex64igen.c:1500 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "\tBảng Cái Chỉ Tên \t\t" + +#: peigen.c:1505 pepigen.c:1505 pex64igen.c:1505 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "\tBảng Thứ Tá»± \t\t\t" + +#: peigen.c:1519 pepigen.c:1519 pex64igen.c:1519 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" +"\n" +"Bảng Äịa chỉ Xuất — CÆ¡ bản Thứ tá»± %ld\n" + +#: peigen.c:1538 pepigen.c:1538 pex64igen.c:1538 +msgid "Forwarder RVA" +msgstr "Bá»™ chuyển tiếp RVA" + +#: peigen.c:1549 pepigen.c:1549 pex64igen.c:1549 +msgid "Export RVA" +msgstr "Xuất RVA" + +#: peigen.c:1556 pepigen.c:1556 pex64igen.c:1556 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" +"\n" +"Bảng [Cái chỉ Thứ tá»±/Tên]\n" + +#: peigen.c:1616 peigen.c:1795 pepigen.c:1616 pepigen.c:1795 pex64igen.c:1616 +#: pex64igen.c:1795 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "Cảnh báo : kích cỡ phần .pdata (%ld) không phải là bá»™i số cho %d\n" + +#: peigen.c:1623 pepigen.c:1623 pex64igen.c:1623 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr " vma:\t\t\tÄịa chi đầu Äịa chỉ cuối Thông tin tháo ra\n" + +#: peigen.c:1625 pepigen.c:1625 pex64igen.c:1625 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" +" vma:\t\tÄầu Cuối EH EH PrologEnd Ngoại lệ\n" +" \t\tÄịa chỉ Äịa chỉ Bá»™ quản lý Dữ liệu Äịa chỉ Mặt nạ\n" + +#: peigen.c:1695 pepigen.c:1695 pex64igen.c:1695 +#, c-format +msgid " Register save millicode" +msgstr " Mili-mã lÆ°u thanh ghi" + +#: peigen.c:1698 pepigen.c:1698 pex64igen.c:1698 +#, c-format +msgid " Register restore millicode" +msgstr " Mili-mã phục hồi thanh ghi" + +#: peigen.c:1701 pepigen.c:1701 pex64igen.c:1701 +#, c-format +msgid " Glue code sequence" +msgstr " Dãy mã nối lại" + +#: peigen.c:1801 pepigen.c:1801 pex64igen.c:1801 +#, c-format +msgid "" +" vma:\t\tBegin Prolog Function Flags Exception EH\n" +" \t\tAddress Length Length 32b exc Handler Data\n" +msgstr "" +" vma:\t\tÄầu Prolog Cá» hàm Ngoại lệ EH\n" +" \t\tÄịa chỉ Dài Dài 32b exc Quản lý Dữ liệu\n" + +#: peigen.c:1933 pepigen.c:1933 pex64igen.c:1933 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" +"\n" +"\n" +"Äịnh vị lại cÆ¡ bản tập tin PE (phiên dịch ná»™i dung phần .reloc)\n" + +#: peigen.c:1963 pepigen.c:1963 pex64igen.c:1963 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" +"\n" +"Äịa chỉ ảo: %08lx Kích cỡ khúc %ld (0x%lx) Số sá»± sá»­a chữa %ld\n" + +#: peigen.c:1976 pepigen.c:1976 pex64igen.c:1976 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "\tđịnh vị lại %4d bù %4x [%4lx] %s" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:2015 pepigen.c:2015 pex64igen.c:2015 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" +"\n" +"Äặc tính 0x%x\n" + +#: peigen.c:2292 pepigen.c:2292 pex64igen.c:2292 +msgid "%B: unable to fill in DataDictionary[1] because .idata$2 is missing" +msgstr "%B: không thể Ä‘iá»n vào DataDictionary[1] vì .idata$2 còn thiếu" + +#: peigen.c:2312 pepigen.c:2312 pex64igen.c:2312 +msgid "%B: unable to fill in DataDictionary[1] because .idata$4 is missing" +msgstr "%B: không thể Ä‘iá»n vào DataDictionary[1] vì .idata$4 còn thiếu" + +#: peigen.c:2333 pepigen.c:2333 pex64igen.c:2333 +msgid "%B: unable to fill in DataDictionary[12] because .idata$5 is missing" +msgstr "%B: không thể Ä‘iá»n vào DataDictionary[12] vì .idata$5 còn thiếu" + +#: peigen.c:2353 pepigen.c:2353 pex64igen.c:2353 +msgid "%B: unable to fill in DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] because .idata$6 is missing" +msgstr "%B: không thể Ä‘iá»n vào DataDictionary[PE_IMPORT_ADDRESS_TABLE (12)] vì .idata$6 còn thiếu" + +#: peigen.c:2375 pepigen.c:2375 pex64igen.c:2375 +msgid "%B: unable to fill in DataDictionary[9] because __tls_used is missing" +msgstr "%B: không thể Ä‘iá»n vào DataDictionary[9] vì __tls_used còn thiếu" diff --git a/external/gpl3/gdb/dist/bfd/po/zh_CN.gmo b/external/gpl3/gdb/dist/bfd/po/zh_CN.gmo new file mode 100644 index 0000000000000000000000000000000000000000..65998865d3a8f6281dfca807fb97ee9c6deee143 GIT binary patch literal 28121 zcmcJW3wV{)neRW_dLgymtMyX*sicCE$X$&$kh?{oB-nZ@?qqMm)}6i6y|V@E%$%9F z({|eF>2x}CI&-F{Q%qYCsS-#+NC*f-0s%ryLcp|ITPankZ3h)`l=l4oYprizazXk$ z=j?~Y|66Ol>-Mhqeb>7#dFg_W{Hw=r%4wc=1$ae)=RKqEi3BD?eHrgL-xMw z@COc`0L6lJ;8|chI1=mvuL0i%3&BenoW^kncnP==6y3uhB;I$xOTnLkYQG&k6MWvq zUjSAAD-M6>(%*LRKRY}Nrit!+Q1x5}s^23)jrRr@p8~2Mp8?fw1*q}=H7Gv*Bghnb zwJv=#sQKFqirU%v#4!4VLR1#bdx2cuvS zxC$Hv_JQKdpTQf!PhRbLI`;0N)1HP9cq!fpfv};7U;Ry* zOaawS+Tjnu`-!)McYxP0X{x^hRQyMv+J70;crTza^=~!^3%n(u^1lYs6|V_|)cZN; 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zzd9ecUwuz^w|Ln?@+|kRu@jOl*t|C&KLygDjbTXxf?;djziIP}jW0JH3;OL@=N$jT zj@e!r1wp{+snDpgCp(PC1*9| zcR#=RXLT)oO`NhIF29D_Tr+!hC+Rv&=-DMLf)E;!=tgY-=r=-sh&wKFM;%0*1&%kdCzWYsX+jRwq!>&#kLl{(Hwe(l4Gs znU`0R-%PGKcXheEv>G;#msM&&$CTQrSw>_ZRcR7+BbHIN0<(O&BDMS2l^Pw+Y(JVi zO`=ngZ1Vaw>yK?{?0jM%wNc#xiGjM=N=#<=^R4goY}aBXIT2fei}SoCF)(VmD`SwB zUF3YddD2-veji>45p$5Xn^P)t?`I!A~ONTgq|Ij`m_JU z&JB&dJB}C&j(yRCrtR-@ZH5h#Q71|7nFb{3Ia837x5f^9+=OM+xsDzO^XMu2nkj!} z&U?xge6O$y`(A=#V9I1QG-8-8Qf1(mF>FZ0VshYg?py?Z3(NA$UVz PE4Hh#PE+ZqY1aF{uK&%$ literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/bfd/po/zh_CN.po b/external/gpl3/gdb/dist/bfd/po/zh_CN.po new file mode 100644 index 000000000000..6e0fb10487f5 --- /dev/null +++ b/external/gpl3/gdb/dist/bfd/po/zh_CN.po @@ -0,0 +1,2702 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) 2003 Free Software Foundation, Inc. +# Wang Li , 2003. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2003-03-11 09:46+0800\n" +"Last-Translator: Wang Li \n" +"Language-Team: Chinese (simplified) \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=gb2312\n" +"Content-Transfer-Encoding: 8bit\n" + +#: aout-adobe.c:197 +#, c-format +msgid "%s: Unknown section type in a.out.adobe file: %x\n" +msgstr "%s£ºa.out.adobe ÎļþÖнڵÄÀàÐÍδ֪£º%x\n" + +#: aout-cris.c:208 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s£ºµ¼³öÎÞЧµÄÖض¨Î»ÀàÐÍ£º%d" + +#: aout-cris.c:252 +#, c-format +msgid "%s: Invalid relocation type imported: %d" +msgstr "%s£ºµ¼ÈëÎÞЧµÄÖض¨Î»ÀàÐÍ£º%d" + +#: aout-cris.c:263 +#, c-format +msgid "%s: Bad relocation record imported: %d" +msgstr "%s£ºµ¼Èë´íÎóµÄÖض¨Î»¼Ç¼£º%d" + +#: aoutx.h:1282 aoutx.h:1699 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s£ºÎÞ·¨ÔÚ a.out ¶ÔÏóÎļþ¸ñʽÖбíʾ½Ú¡°%s¡±" + +#: aoutx.h:1669 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s£ºÎÞ·¨ÔÚ a.out ¶ÔÏóÎļþ¸ñʽÖÐΪ·ûºÅ¡°%s¡±±íʾ½Ú" + +#: aoutx.h:1671 +msgid "*unknown*" +msgstr "*δ֪*" + +#: aoutx.h:3732 +#, c-format +msgid "%s: relocateable link from %s to %s not supported" +msgstr "%s£º²»Ö§³Ö´Ó %s µ½ %s µÄ¿ÉÖض¨Î»µÄÁ¬½Ó" + +#: archive.c:1826 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "¾¯¸æ£ºÐ´Èë¹éµµ¹ýÂý£ºÖØÐÂдÈëʱ¼ä´Á\n" + +#: archive.c:2093 +msgid "Reading archive file mod timestamp" +msgstr "ÕýÔÚ¶ÁÈëÎļþÐÞ¸Äʱ¼ä´Á" + +#. FIXME: bfd can't call perror. +#: archive.c:2120 +msgid "Writing updated armap timestamp" +msgstr "ÕýÔÚ¸üРarmap ʱ¼ä´Á" + +#: bfd.c:274 +msgid "No error" +msgstr "ÎÞ´íÎó" + +#: bfd.c:275 +msgid "System call error" +msgstr "ϵͳµ÷ÓôíÎó" + +#: bfd.c:276 +msgid "Invalid bfd target" +msgstr "ÎÞЧµÄ bfd Ä¿±ê" + +#: bfd.c:277 +msgid "File in wrong format" +msgstr "Îļþ¸ñʽ´íÎó" + +#: bfd.c:278 +msgid "Archive object file in wrong format" +msgstr "¹éµµÄ¿±êÎļþ¸ñʽ´íÎó" + +#: bfd.c:279 +msgid "Invalid operation" +msgstr "ÎÞЧµÄ²Ù×÷" + +#: bfd.c:280 +msgid "Memory exhausted" +msgstr "ÄÚ´æºÄ¾¡" + +#: bfd.c:281 +msgid "No symbols" +msgstr "ÎÞ·ûºÅ" + +#: bfd.c:282 +msgid "Archive has no index; run ranlib to add one" +msgstr "¹éµµÃ»ÓÐË÷Òý£»ÔËÐÐ ranlib ÒÔÌí¼ÓÒ»¸ö" + +#: bfd.c:283 +msgid "No more archived files" +msgstr "ûÓиü¶àµÄ¹éµµÎļþ" + +#: bfd.c:284 +msgid "Malformed archive" +msgstr "»ûÐεĹ鵵" + +#: bfd.c:285 +msgid "File format not recognized" +msgstr "²»¿Éʶ±ðµÄÎļþ¸ñʽ" + +#: bfd.c:286 +msgid "File format is ambiguous" +msgstr "¶þÒåÐÔµÄÎļþ¸ñʽ" + +#: bfd.c:287 +msgid "Section has no contents" +msgstr "½ÚûÓÐÄÚÈÝ" + +#: bfd.c:288 +msgid "Nonrepresentable section on output" +msgstr "Êä³ö²»¿É±íʾµÄ½Ú" + +#: bfd.c:289 +msgid "Symbol needs debug section which does not exist" +msgstr "·ûºÅÐèÒª²»´æÔڵĵ÷ÊÔ½Ú" + +#: bfd.c:290 +msgid "Bad value" +msgstr "´íÎóµÄÖµ" + +#: bfd.c:291 +msgid "File truncated" +msgstr "Îļþ±»½Ø¶Ï" + +#: bfd.c:292 +msgid "File too big" +msgstr "Îļþ¹ý´ó" + +#: bfd.c:293 +msgid "#" +msgstr "#<ÎÞЧµÄ´íÎóÂë>" + +#: bfd.c:700 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s ¶ÏÑÔʧ°Ü %s£º%d" + +#: bfd.c:719 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %1$s ÄÚ²¿´íÎó£¬Òì³£ÖÐÖ¹ÓÚ %4$s µÄ %3$d ÐÐµÄ %2$s\n" + +#: bfd.c:723 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %1$s ÄÚ²¿´íÎó£¬Òì³£ÖÐÖ¹ÓÚ %3$d ÐÐµÄ %2$s\n" + +#: bfd.c:725 +msgid "Please report this bug.\n" +msgstr "Ç뱨¸æ¸Ã BUG¡£\n" + +#: binary.c:306 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "¾¯¸æ£º½«½Ú¡°%s¡±Ð´Èë¹ý´ó(ÀýÈ縺Êý)ÎļþÆ«ÒÆÁ¿µÄλÖà 0x%lx¡£" + +#: coff-a29k.c:119 +msgid "Missing IHCONST" +msgstr "ÒÅʧ IHCONST" + +#: coff-a29k.c:180 +msgid "Missing IHIHALF" +msgstr "ÒÅʧ IHIHALF" + +#: coff-a29k.c:212 coff-or32.c:229 +msgid "Unrecognized reloc" +msgstr "ÎÞ·¨Ê¶±ðµÄÖض¨Î»" + +#: coff-a29k.c:408 +msgid "missing IHCONST reloc" +msgstr "ÒÅʧ IHCONST Öض¨Î»" + +#: coff-a29k.c:498 +msgid "missing IHIHALF reloc" +msgstr "ÒÅʧ IHIHALF Öض¨Î»" + +#: coff-alpha.c:881 coff-alpha.c:918 coff-alpha.c:1989 coff-mips.c:1432 +msgid "GP relative relocation used when GP not defined" +msgstr "ÔÚ GP 䶨ÒåµÄÇé¿öÏÂʹÓÃÁË GP Ïà¶ÔÖض¨Î»" + +#: coff-alpha.c:1485 +msgid "using multiple gp values" +msgstr "ʹÓÃÁ˶à¸ö GP Öµ" + +#: coff-arm.c:1066 elf32-arm.h:285 +#, c-format +msgid "%s: unable to find THUMB glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1096 elf32-arm.h:320 +#, c-format +msgid "%s: unable to find ARM glue '%s' for `%s'" +msgstr "" + +#: coff-arm.c:1391 coff-arm.c:1486 elf32-arm.h:887 elf32-arm.h:991 +#, c-format +msgid "%s(%s): warning: interworking not enabled." +msgstr "" + +#: coff-arm.c:1395 elf32-arm.h:994 +#, c-format +msgid " first occurrence: %s: arm call to thumb" +msgstr "" + +#: coff-arm.c:1490 elf32-arm.h:890 +#, c-format +msgid " first occurrence: %s: thumb call to arm" +msgstr "" + +#: coff-arm.c:1493 +msgid " consider relinking with --support-old-code enabled" +msgstr " ³¢ÊÔÆôÓà --support-old-code ÖØÐÂÁ¬½Ó" + +#: coff-arm.c:1785 coff-tic80.c:686 cofflink.c:3031 +#, c-format +msgid "%s: bad reloc address 0x%lx in section `%s'" +msgstr "" + +#: coff-arm.c:2127 +#, c-format +msgid "%s: illegal symbol index in reloc: %d" +msgstr "%s£ºÖض¨Î»ÖзǷ¨µÄ·ûºÅË÷Òý£º%d" + +#: coff-arm.c:2255 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d" +msgstr "´íÎó£º%s ÊÇΪ APCS-%d ±àÒëµÄ£¬¶ø %s ÊÇΪ APCS-%d ±àÒëµÄ" + +#: coff-arm.c:2270 elf32-arm.h:2297 +#, c-format +msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers" +msgstr "´íÎó£º%s ÔÚ¸¡µã¼Ä´æÆ÷Öд«µÝ¸¡µãÊý£¬¶ø %s ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝËüÃÇ" + +#: coff-arm.c:2273 elf32-arm.h:2302 +#, c-format +msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers" +msgstr "´íÎó£º%s ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝ¸¡µãÊý£¬¶ø %s ÔÚ¸¡µãÊý¼Ä´æÆ÷Öд«µÝËüÃÇ" + +#: coff-arm.c:2288 +#, c-format +msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position" +msgstr "´íÎó£º%s ±»±àÒëΪλÖÃÎ޹شúÂ룬¶øÄ¿±ê %s ²ÉÓþø¶ÔλÖÃ" + +#: coff-arm.c:2291 +#, c-format +msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent" +msgstr "´íÎó£º%s ±»±àÒëΪ¾ø¶ÔλÖôúÂ룬¶øÄ¿±ê %s ÊÇλÖÃÎ޹صÄ" + +#: coff-arm.c:2320 elf32-arm.h:2358 +#, c-format +msgid "Warning: %s supports interworking, whereas %s does not" +msgstr "¾¯¸æ£º%s Ö§³Ö»¥²Ù×÷£¬¶ø %s ²»Ö§³Ö" + +#: coff-arm.c:2323 elf32-arm.h:2365 +#, c-format +msgid "Warning: %s does not support interworking, whereas %s does" +msgstr "¾¯¸æ£º%s ²»Ö§³Ö»¥²Ù×÷£¬¶ø %s Ö§³Ö" + +#: coff-arm.c:2350 +#, c-format +msgid "private flags = %x:" +msgstr "˽ÓбêÖ¾ = %x£º" + +#: coff-arm.c:2358 elf32-arm.h:2418 +msgid " [floats passed in float registers]" +msgstr " [ÔÚ¸¡µã¼Ä´æÆ÷Öд«µÝ¸¡µãÊý]" + +#: coff-arm.c:2360 +msgid " [floats passed in integer registers]" +msgstr " [ÔÚÕûÊý¼Ä´æÆ÷Öд«µÝ¸¡µãÊý]" + +#: coff-arm.c:2363 elf32-arm.h:2421 +msgid " [position independent]" +msgstr " [λÖÃÎÞ¹Ø]" + +#: coff-arm.c:2365 +msgid " [absolute position]" +msgstr " [¾ø¶ÔλÖÃ]" + +#: coff-arm.c:2369 +msgid " [interworking flag not initialised]" +msgstr " [»¥²Ù×÷±ê־δ³õʼ»¯]" + +#: coff-arm.c:2371 +msgid " [interworking supported]" +msgstr " [Ö§³Ö»¥²Ù×÷]" + +#: coff-arm.c:2373 +msgid " [interworking not supported]" +msgstr " [²»Ö§³Ö»¥²Ù×÷]" + +#: coff-arm.c:2421 elf32-arm.h:2124 +#, c-format +msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking" +msgstr "¾¯¸æ£ºÓÉÓÚ %s ÒѾ­±»Ö¸¶¨Îª²»¿É»¥²Ù×÷µÄ£¬Òò¶øûÓÐÉ趨»¥²Ù×÷±êÖ¾" + +#: coff-arm.c:2425 elf32-arm.h:2128 +#, c-format +msgid "Warning: Clearing the interworking flag of %s due to outside request" +msgstr "¾¯¸æ£ºÕýÔÚ¸ù¾ÝÍâ½çÇëÇóÇå³ý %s µÄ»¥²Ù×÷±êÖ¾" + +#: coff-i960.c:136 coff-i960.c:485 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "¹ØÓÚ·Ç-COFF ·ûºÅ²»È·¶¨µÄµ÷ÓÃÔ¼¶¨" + +#: coff-m68k.c:481 coff-mips.c:2429 elf32-m68k.c:2157 elf32-mips.c:1844 +msgid "unsupported reloc type" +msgstr "²»Ö§³ÖµÄÖض¨Î»ÀàÐÍ" + +#: coff-mips.c:874 elf32-mips.c:1062 elf64-mips.c:1609 +msgid "GP relative relocation when _gp not defined" +msgstr "" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2466 +msgid "reloc against unsupported section" +msgstr "¹ØÓÚ²»Ö§³Ö½ÚµÄÖض¨Î»" + +#: coff-mips.c:2474 +msgid "reloc not properly aligned" +msgstr "Öض¨Î»Ã»ÓÐÕýÈ·¶ÔÆë" + +#: coff-rs6000.c:2766 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s£º²»Ö§³ÖµÄÖض¨Î»ÀàÐÍ 0x%02x" + +#: coff-rs6000.c:2859 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "" + +#: coff-rs6000.c:3590 coff64-rs6000.c:2091 +#, c-format +msgid "%s: symbol `%s' has unrecognized smclas %d" +msgstr "" + +#: coff-tic54x.c:279 coff-tic80.c:449 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "ÎÞ·¨Ê¶±ðµÄÖض¨Î»ÀàÐÍ 0x%x" + +#: coff-tic54x.c:390 coffcode.h:4974 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s£º¾¯¸æ£ºÖض¨Î»ÖзǷ¨µÄ·ûºÅË÷Òý %ld" + +#: coff-w65.c:363 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "ÕýÔÚºöÂÔÖض¨Î» %s\n" + +#: coffcode.h:1086 +#, c-format +msgid "%s (%s): Section flag %s (0x%x) ignored" +msgstr "%s (%s)£ººöÂÔ½Ú±êÖ¾ %s (0x%x)" + +#: coffcode.h:2143 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "ÎÞ·¨Ê¶±ðµÄ TI COFF Ä¿±ê id ¡°0x%x¡±" + +#: coffcode.h:4365 +#, c-format +msgid "%s: warning: illegal symbol index %ld in line numbers" +msgstr "%s£º¾¯¸æ£ºÐкÅÖеķǷ¨·ûºÅË÷Òý %ld" + +#: coffcode.h:4379 +#, c-format +msgid "%s: warning: duplicate line number information for `%s'" +msgstr "%s£º¾¯¸æ£ºÎª¡°%s¡±¸´ÖÆÐкÅÐÅÏ¢" + +#: coffcode.h:4736 +#, c-format +msgid "%s: Unrecognized storage class %d for %s symbol `%s'" +msgstr "" + +#: coffcode.h:4867 +#, c-format +msgid "warning: %s: local symbol `%s' has no section" +msgstr "¾¯¸æ£º%s£º±¾µØ·ûºÅ¡°%s¡±Ã»ÓнÚ" + +#: coffcode.h:5012 +#, c-format +msgid "%s: illegal relocation type %d at address 0x%lx" +msgstr "%1$s£ºÎ»ÓÚµØÖ· 0x%3$lx ´¦µÄ·Ç·¨Öض¨Î»ÀàÐÍ %2$d" + +#: coffgen.c:1661 +#, c-format +msgid "%s: bad string table size %lu" +msgstr "%s£º×Ö·û´®±íµÄ´óС´íÎó %lu" + +#: cofflink.c:534 elflink.h:1912 +#, c-format +msgid "Warning: type of symbol `%s' changed from %d to %d in %s" +msgstr "¾¯¸æ£º%4$s ÖеķûºÅ¡°%1$s¡±µÄÀàÐÍÓÉ %2$d ±äΪ %3$d" + +#: cofflink.c:2321 +#, c-format +msgid "%s: relocs in section `%s', but it has no contents" +msgstr "" + +#: cofflink.c:2664 coffswap.h:877 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s£º%s£ºÖض¨Î»Òç³ö£º0x%lx > 0xffff" + +#: cofflink.c:2673 coffswap.h:864 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s£º¾¯¸æ£º%s£ºÐкÅÒç³ö£º0x%lx > 0xffff" + +#: dwarf2.c:382 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_str ½Ú¡£" + +#: dwarf2.c:399 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "" + +#: dwarf2.c:543 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_abbrev ½Ú¡£" + +#: dwarf2.c:560 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "" + +#: dwarf2.c:757 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "С´íÎó£ºÎÞЧ»òδ´¦ÀíµÄ±íµ¥Öµ£º%u¡£" + +#: dwarf2.c:852 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "" + +#: dwarf2.c:938 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "С´íÎó£ºÎÞ·¨ÕÒµ½ .debug_line ½Ú¡£" + +#: dwarf2.c:961 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "" + +#: dwarf2.c:1159 +msgid "Dwarf Error: mangled line number section." +msgstr "" + +#: dwarf2.c:1355 dwarf2.c:1566 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "" + +#: dwarf2.c:1527 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "" + +#: dwarf2.c:1534 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "" + +#: dwarf2.c:1557 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "С´íÎ󣺴íÎóµÄËõд±àºÅ£º%u¡£" + +#: ecoff.c:1318 +#, c-format +msgid "Unknown basic type %d" +msgstr "δ֪µÄ»ù±¾ÀàÐÍ %d" + +#: ecoff.c:1578 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1585 ecoff.c:1588 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" µÚÒ»¸ö·ûºÅ£º%ld" + +#: ecoff.c:1600 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" End+1 ·ûºÅ£º%-7ld ÀàÐÍ£º%s" + +#: ecoff.c:1607 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" ±¾µØ·ûºÅ£º%ld" + +#: ecoff.c:1615 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" ½á¹¹£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1620 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" ÁªºÏ£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1625 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" ö¾Ù£»End+1 ·ûºÅ£º%ld" + +#: ecoff.c:1631 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" ÀàÐÍ£º%s" + +#: elf-hppa.h:1476 elf-hppa.h:1509 elf32-ppc.c:3091 elf32-sh.c:4213 +#: elf64-sh64.c:1659 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%1$s£º¾¯¸æ£ºÀ´×Ô %3$s ½ÚµÄ¹ØÓÚ·ûºÅ¡°%2$s¡±µÄ²»¿É½âÎöµÄÖض¨Î»" + +#: elf-m10200.c:446 elf-m10300.c:656 elf32-arm.h:2084 elf32-avr.c:833 +#: elf32-cris.c:1403 elf32-d10v.c:481 elf32-fr30.c:635 elf32-frv.c:809 +#: elf32-h8300.c:548 elf32-i860.c:1031 elf32-m32r.c:1278 elf32-openrisc.c:439 +#: elf32-v850.c:1691 elf32-xstormy16.c:933 elf64-mmix.c:1302 +msgid "internal error: out of range error" +msgstr "ÄÚ²¿´íÎ󣺳¬³ö·¶Î§´íÎó" + +#: elf-m10200.c:450 elf-m10300.c:660 elf32-arm.h:2088 elf32-avr.c:837 +#: elf32-cris.c:1407 elf32-d10v.c:485 elf32-fr30.c:639 elf32-frv.c:813 +#: elf32-h8300.c:552 elf32-i860.c:1035 elf32-m32r.c:1282 elf32-openrisc.c:443 +#: elf32-v850.c:1695 elf32-xstormy16.c:937 elf64-mmix.c:1306 elfxx-mips.c:5264 +msgid "internal error: unsupported relocation error" +msgstr "ÄÚ²¿´íÎ󣺲»Ö§³ÖµÄÖض¨Î»´íÎó" + +#: elf-m10200.c:454 elf-m10300.c:664 elf32-arm.h:2092 elf32-d10v.c:489 +#: elf32-h8300.c:556 elf32-m32r.c:1286 +msgid "internal error: dangerous error" +msgstr "ÄÚ²¿´íÎó£ºÎ£ÏյĴíÎó" + +#: elf-m10200.c:458 elf-m10300.c:668 elf32-arm.h:2096 elf32-avr.c:845 +#: elf32-cris.c:1415 elf32-d10v.c:493 elf32-fr30.c:647 elf32-frv.c:821 +#: elf32-h8300.c:560 elf32-i860.c:1043 elf32-m32r.c:1290 elf32-openrisc.c:451 +#: elf32-v850.c:1715 elf32-xstormy16.c:945 elf64-mmix.c:1314 +msgid "internal error: unknown error" +msgstr "ÄÚ²¿´íÎó£ºÎ´ÖªµÄ´íÎó" + +#: elf.c:343 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "" + +#: elf.c:589 +#, c-format +msgid "%s: invalid SHT_GROUP entry" +msgstr "%s£ºÎÞЧµÄ SHT_GROUP ÌõÄ¿" + +#: elf.c:660 +#, c-format +msgid "%s: no group info for section %s" +msgstr "%s£ºÃ»ÓйØÓÚ½Ú %s µÄ×éÐÅÏ¢" + +#: elf.c:1023 +msgid "" +"\n" +"Program Header:\n" +msgstr "" +"\n" +"³ÌÐòÍ·£º\n" + +#: elf.c:1073 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" +"\n" +"¶¯Ì¬½Ú£º\n" + +#: elf.c:1202 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" +"\n" +"°æ±¾¶¨Ò壺\n" + +#: elf.c:1225 +msgid "" +"\n" +"Version References:\n" +msgstr "" +"\n" +"°æ±¾ÒýÓãº\n" + +#: elf.c:1230 +#, c-format +msgid " required from %s:\n" +msgstr "" + +#: elf.c:1902 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "" + +#: elf.c:3603 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "%s£ºÃ»ÓÐ×ã¹»µÄ¿Õ¼ä±£´æ³ÌÐòÍ·£¨·ÖÅä %u£¬ÐèÒª %u£©" + +#: elf.c:3708 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "%s£ºÃ»ÓÐ×ã¹»µÄ¿Õ¼ä±£´æ³ÌÐòÍ·£¬ÊÔÓà -N ½øÐÐÁ¬½Ó" + +#: elf.c:3833 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x" +msgstr "´íÎ󣺶Π(%s) ÖеĵÚÒ»¸ö½Ú¿ªÊ¼ÓÚ 0x%x£¬È»¶ø¶Î¿ªÊ¼ÓÚ 0x%x" + +#: elf.c:4148 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "%s£º¾¯¸æ£ºÒÑ·ÖÅäµÄ½Ú¡°%s¡±²»ÔÚ¶ÎÖÐ" + +#: elf.c:4472 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "%s£º±ØÐèµÄ·ûºÅ¡°%s¡±²»´æÔÚ" + +#: elf.c:4749 +#, c-format +msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "%s£º¾¯¸æ£º·¢ÏֿյĿÉ×°Èë¶Î£¬ËüÊÇÄÚ²¿µÄ£¿\n" + +#: elf.c:6193 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "%s£º²»Ö§³ÖµÄÖض¨Î»µÄÀàÐÍ %s" + +#: elf32-arm.h:1221 +#, c-format +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "" + +#: elf32-arm.h:1417 +#, c-format +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "" + +#: elf32-arm.h:1914 elf32-sh.c:4125 +#, c-format +msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%s(%s+0x%lx)£º¹ØÓÚ SEC_MERGE ½ÚµÄÖض¨Î» %s" + +#: elf32-arm.h:2008 +#, c-format +msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section" +msgstr "" + +#: elf32-arm.h:2176 +#, c-format +msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it" +msgstr "" + +#: elf32-arm.h:2271 +#, c-format +msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d" +msgstr "´íÎó£º%s ÊÇΪ EABI °æ±¾ %d ±àÒëµÄ£¬¶ø %s ÔòÊÇΪ°æ±¾ %d ±àÒëµÄ" + +#: elf32-arm.h:2285 +#, c-format +msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d" +msgstr "´íÎó£º%s ÊÇΪ APCS-%d ±àÒëµÄ£¬¶øÄ¿±ê %s ʹÓà APCS-%d" + +#: elf32-arm.h:2313 +#, c-format +msgid "ERROR: %s uses VFP instructions, whereas %s uses FPA instructions" +msgstr "´íÎó£º%s ʹÓà VFP Ö¸Á¶ø %s ʹÓà FPA Ö¸Áî" + +#: elf32-arm.h:2318 +#, c-format +msgid "ERROR: %s uses FPA instructions, whereas %s uses VFP instructions" +msgstr "´íÎó£º%s ʹÓà FPA Ö¸Á¶ø %s ʹÓà VFP Ö¸Áî" + +#: elf32-arm.h:2338 +#, c-format +msgid "ERROR: %s uses software FP, whereas %s uses hardware FP" +msgstr "´íÎó£º%s ʹÓÃÈí¼þ FP£¬¶ø %s ʹÓÃÓ²¼þ FP" + +#: elf32-arm.h:2343 +#, c-format +msgid "ERROR: %s uses hardware FP, whereas %s uses software FP" +msgstr "´íÎó£º%s ʹÓÃÓ²¼þ FP£¬¶ø %s ʹÓÃÈí¼þ FP" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#: elf32-arm.h:2396 elf32-cris.c:2988 elf32-m68k.c:410 elf32-vax.c:543 +#: elfxx-mips.c:7756 +#, c-format +msgid "private flags = %lx:" +msgstr "˽ÓбêÖ¾ = %lx£º" + +#: elf32-arm.h:2405 +msgid " [interworking enabled]" +msgstr " [ÆôÓû¥²Ù×÷]" + +#: elf32-arm.h:2413 +msgid " [VFP float format]" +msgstr " [VFP ¸¡µã¸ñʽ]" + +#: elf32-arm.h:2415 +msgid " [FPA float format]" +msgstr " [FPA ¸¡µã¸ñʽ]" + +#: elf32-arm.h:2424 +msgid " [new ABI]" +msgstr " [РABI]" + +#: elf32-arm.h:2427 +msgid " [old ABI]" +msgstr " [¾É ABI]" + +#: elf32-arm.h:2430 +msgid " [software FP]" +msgstr " [Èí¼þ FP]" + +#: elf32-arm.h:2438 +msgid " [Version1 EABI]" +msgstr " [°æ±¾1 EABI]" + +#: elf32-arm.h:2441 elf32-arm.h:2452 +msgid " [sorted symbol table]" +msgstr " [ÅÅÐò¹ýµÄ·ûºÅ±í]" + +#: elf32-arm.h:2443 elf32-arm.h:2454 +msgid " [unsorted symbol table]" +msgstr " [δÅÅÐòµÄ·ûºÅ±í]" + +#: elf32-arm.h:2449 +msgid " [Version2 EABI]" +msgstr " [°æ±¾2 EABI]" + +#: elf32-arm.h:2457 +msgid " [dynamic symbols use segment index]" +msgstr " [¶¯Ì¬·ûºÅʹÓöÎË÷Òý]" + +#: elf32-arm.h:2460 +msgid " [mapping symbols precede others]" +msgstr "" + +#: elf32-arm.h:2467 +msgid " " +msgstr " <²»¿Éʶ±ðµÄ EABI °æ±¾>" + +#: elf32-arm.h:2474 +msgid " [relocatable executable]" +msgstr " [¿ÉÖØж¨Î»µÄ¿ÉÖ´ÐгÌÐò]" + +#: elf32-arm.h:2477 +msgid " [has entry point]" +msgstr " [º¬ÓÐÈë¿Úµã]" + +#: elf32-arm.h:2482 +msgid "" +msgstr "<ÎÞ·¨Ê¶±ðµÄ±ê־λ¼¯ºÏ>" + +#: elf32-avr.c:841 elf32-cris.c:1411 elf32-fr30.c:643 elf32-frv.c:817 +#: elf32-i860.c:1039 elf32-openrisc.c:447 elf32-v850.c:1699 +#: elf32-xstormy16.c:941 elf64-mmix.c:1310 +msgid "internal error: dangerous relocation" +msgstr "ÄÚ²¿´íÎó£ºÎ£ÏÕµÄÖض¨Î»" + +#: elf32-cris.c:949 +#, c-format +msgid "%s: unresolvable relocation %s against symbol `%s' from %s section" +msgstr "%1$s£ºÀ´×Ô %4$s ½ÚµÄ¹ØÓÚ·ûºÅ¡°%3$s¡±µÄÎÞ·¨½âÎöµÄÖض¨Î» %2$s" + +#: elf32-cris.c:1012 +#, c-format +msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1015 elf32-cris.c:1141 +msgid "[whose name is lost]" +msgstr "" + +#: elf32-cris.c:1130 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section" +msgstr "" + +#: elf32-cris.c:1137 +#, c-format +msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1155 +#, c-format +msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section" +msgstr "" + +#: elf32-cris.c:1170 +#, c-format +msgid "%s: relocation %s in section %s with no GOT created" +msgstr "" + +#: elf32-cris.c:1288 +#, c-format +msgid "%s: Internal inconsistency; no relocation section %s" +msgstr "%s£ºÄÚ²¿²»Ò»Ö£»Ã»ÓÐÖض¨Î»½Ú %s" + +#: elf32-cris.c:2514 +#, c-format +msgid "" +"%s, section %s:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-cris.c:2991 +msgid " [symbols have a _ prefix]" +msgstr " [·ûºÅÓиö _ ǰ׺]" + +#: elf32-cris.c:3030 +#, c-format +msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%s£ºÊ¹Óôø _ ǰ׺µÄ·ûºÅ£¬µ«ÒÔÎÞǰ׺·ûºÅдÈëÎļþ" + +#: elf32-cris.c:3031 +#, c-format +msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%s£ºÊ¹ÓÃÎÞǰ׺·ûºÅ£¬µ«ÒÔ´ø _ ǰ׺µÄ·ûºÅдÈëÎļþ" + +#: elf32-frv.c:1217 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "" + +#: elf32-frv.c:1267 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s£ºÒÔ %s ±àÒ벢ͬÒÔ %s ±àÒëµÄÄ£¿éÁ¬½Ó" + +#: elf32-frv.c:1279 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-frv.c:1315 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "˽ÓбêÖ¾ = 0x%lx£º" + +#: elf32-gen.c:82 elf64-gen.c:82 +#, c-format +msgid "%s: Relocations in generic ELF (EM: %d)" +msgstr "" + +#: elf32-hppa.c:671 elf64-ppc.c:2323 +#, c-format +msgid "%s: cannot create stub entry %s" +msgstr "" + +#: elf32-hppa.c:956 elf32-hppa.c:3555 +#, c-format +msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "" + +#: elf32-hppa.c:1338 elf64-x86-64.c:673 +#, c-format +msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-hppa.c:1358 +#, c-format +msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC" +msgstr "" + +#: elf32-hppa.c:1551 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "ÎÞ·¨Îª %s ÕÒµ½Öض¨Î»½Ú" + +#: elf32-hppa.c:2855 +#, c-format +msgid "%s: duplicate export stub %s" +msgstr "" + +#: elf32-hppa.c:3433 +#, c-format +msgid "%s(%s+0x%lx): fixing %s" +msgstr "%s(%s+0x%lx)£ºÕýÔÚÐÞ¸´ %s" + +#: elf32-hppa.c:4080 +#, c-format +msgid "%s(%s+0x%lx): cannot handle %s for %s" +msgstr "" + +#: elf32-hppa.c:4393 +msgid ".got section not immediately after .plt section" +msgstr ".got ½Ú²»Äܽô½ÓÔÚ .plt ½ÚÖ®ºó" + +#: elf32-i386.c:379 +#, c-format +msgid "%s: invalid relocation type %d" +msgstr "%s£ºÎÞЧµÄÖض¨Î»ÀàÐÍ %d" + +#: elf32-i386.c:876 elf32-s390.c:649 elf64-s390.c:595 elf64-x86-64.c:591 +#, c-format +msgid "%s: bad symbol index: %d" +msgstr "%s£º´íÎóµÄ·ûºÅË÷Òý£º%d" + +#: elf32-i386.c:948 +#, c-format +msgid "%s: `%s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf32-i386.c:1072 elf32-s390.c:808 elf64-ppc.c:2827 elf64-s390.c:759 +#: elf64-x86-64.c:761 +#, c-format +msgid "%s: bad relocation section name `%s'" +msgstr "%s£º´íÎóµÄÖض¨Î»½ÚÃû³Æ¡°%s¡±" + +#: elf32-i386.c:1159 elf64-alpha.c:4768 +#, c-format +msgid "%s: TLS local exec code cannot be linked into shared objects" +msgstr "" + +#: elf32-i386.c:2747 elf32-s390.c:1981 elf32-sparc.c:1571 elf64-ppc.c:5918 +#: elf64-s390.c:1945 elf64-sparc.c:2578 elf64-x86-64.c:1948 +#, c-format +msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "" + +#: elf32-i386.c:2784 elf32-s390.c:2019 elf64-ppc.c:5977 elf64-s390.c:1983 +#: elf64-x86-64.c:1986 +#, c-format +msgid "%s(%s+0x%lx): reloc against `%s': error %d" +msgstr "" + +#: elf32-m32r.c:924 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "ÔÚ _SDA_BASE_ 䶨Òåʱ³öÏÖ SDA Öض¨Î»" + +#: elf32-ia64.c:3687 elf32-m32r.c:1013 elf32-ppc.c:2987 elf64-alpha.c:4185 +#: elf64-alpha.c:4313 elf64-ia64.c:3687 +#, c-format +msgid "%s: unknown relocation type %d" +msgstr "%s£ºÎ´ÖªµÄÖض¨Î»ÀàÐÍ %d" + +#: elf32-m32r.c:1221 +#, c-format +msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" +msgstr "" + +#: elf32-m32r.c:1947 +#, c-format +msgid "%s: Instruction set mismatch with previous modules" +msgstr "" + +#: elf32-m32r.c:1970 +#, c-format +msgid "private flags = %lx" +msgstr "˽ÓбêÖ¾ = %lx" + +#: elf32-m32r.c:1975 +msgid ": m32r instructions" +msgstr "£ºm32r Ö¸Áî" + +#: elf32-m32r.c:1976 +msgid ": m32rx instructions" +msgstr "£ºm32rx Ö¸Áî" + +#: elf32-m68k.c:413 +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:416 +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:354 elf32-mcore.c:457 +#, c-format +msgid "%s: Relocation %s (%d) is not currently supported.\n" +msgstr "" + +#: elf32-mcore.c:442 +#, c-format +msgid "%s: Unknown relocation type %d\n" +msgstr "%s£ºÎ´ÖªµÄÖض¨Î»ÀàÐÍ %d\n" + +#: elf32-mips.c:1152 elf64-mips.c:1783 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "" + +#: elf32-mips.c:1301 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "½« mips16 Ä¿±êÎļþÁ¬½Óµ½ %s ¸ñʽÊDz»Ö§³ÖµÄ" + +#: elf32-ppc.c:1460 +#, c-format +msgid "%s: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "" + +#: elf32-ppc.c:1468 +#, c-format +msgid "%s: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "" + +#: elf32-ppc.c:1494 elf64-sparc.c:2989 elfxx-mips.c:7713 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "" + +#: elf32-ppc.c:1592 +#, c-format +msgid "%s: Unknown special linker type %d" +msgstr "%s£ºÎ´ÖªµÄÌض¨Á¬½ÓÆ÷ÀàÐÍ %d" + +#: elf32-ppc.c:2273 elf32-ppc.c:2307 elf32-ppc.c:2342 +#, c-format +msgid "%s: relocation %s cannot be used when making a shared object" +msgstr "%s£º´´½¨¹²ÏíÄ¿±êÎļþʱ²»ÄÜʹÓÃÖض¨Î» %s" + +#: elf32-ppc.c:3126 elf64-ppc.c:5473 +#, c-format +msgid "%s: unknown relocation type %d for symbol %s" +msgstr "%1$s£º¹ØÓÚ·ûºÅ %3$s µÄδ֪Öض¨Î»ÀàÐÍ %2$d" + +#: elf32-ppc.c:3482 elf32-ppc.c:3503 elf32-ppc.c:3553 +#, c-format +msgid "%s: The target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "" + +#: elf32-ppc.c:3619 +#, c-format +msgid "%s: Relocation %s is not yet supported for symbol %s." +msgstr "%s£ºÉв»Ö§³Ö¹ØÓÚ·ûºÅ %s µÄÖض¨Î» %s¡£" + +#: elf32-sh.c:1964 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎóµÄ R_SH_USES Æ«ÒÆÁ¿" + +#: elf32-sh.c:1976 +#, c-format +msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%s£º0x%lx£º¾¯¸æ£ºR_SH_USES Ö¸ÏòÎÞ·¨Ê¶±ðµÄÖ¸Áî 0x%x" + +#: elf32-sh.c:1993 +#, c-format +msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎóµÄ R_SH_USES ×°ÈëÆ«ÒÆÁ¿" + +#: elf32-sh.c:2008 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected reloc" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÎÞ·¨ÕÒµ½Ô¤ÆÚµÄÖض¨Î»" + +#: elf32-sh.c:2036 +#, c-format +msgid "%s: 0x%lx: warning: symbol in unexpected section" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÒâÍâ½ÚÖгöÏÖ·ûºÅ" + +#: elf32-sh.c:2153 +#, c-format +msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%s£º0x%lx£º¾¯¸æ£ºÎÞ·¨ÕÒµ½Ô¤ÆÚµÄ COUNT Öض¨Î»" + +#: elf32-sh.c:2162 +#, c-format +msgid "%s: 0x%lx: warning: bad count" +msgstr "%s£º0x%lx£º¾¯¸æ£º´íÎó¼ÆÊý" + +#: elf32-sh.c:2550 elf32-sh.c:2926 +#, c-format +msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "" + +#: elf32-sh.c:4073 elf64-sh64.c:1576 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "" + +#: elf32-sh.c:4284 +#, c-format +msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "" + +#: elf32-sh64.c:203 elf64-sh64.c:2364 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s£º±àÒëΪ 32-λĿ±êÎļþµ« %s ÊÇ 64-λµÄ" + +#: elf32-sh64.c:206 elf64-sh64.c:2367 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s£º±àÒëΪ 64-λĿ±êÎļþµ« %s ÊÇ 32-λµÄ" + +#: elf32-sh64.c:208 elf64-sh64.c:2369 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s£ºÄ¿±êÎļþ´óСºÍÄ¿±ê %s ²»Æ¥Åä" + +#: elf32-sh64.c:440 elf64-sh64.c:2941 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s£ºÔÚÊäÈëÖÐÓöµ½Êý¾Ý±êÇ©·ûºÅ" + +#: elf32-sh64.c:523 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "PTB ²»Æ¥Å䣺SHmedia µØÖ· (λ 0 == 1)" + +#: elf32-sh64.c:526 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "PTA ²»Æ¥Å䣺SHcompact µØÖ· (λ 0 == 0)" + +#: elf32-sh64.c:544 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s£ºGAS ´íÎó£ºÒâÍâµÄ´øÓÐ R_SH_PT_16 µÄ PTB Ö¸Áî" + +#: elf32-sh64.c:593 elf64-sh64.c:1703 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "" + +#: elf32-sh64.c:677 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s£ºÎÞ·¨Ð´³ö .cranges ÌõÄ¿" + +#: elf32-sh64.c:739 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s£ºÎÞ·¨Ð´³ö¾­ÅÅÐòµÄ .cranges ÌõÄ¿" + +#: elf32-sparc.c:1535 elf64-sparc.c:2224 +#, c-format +msgid "%s: probably compiled without -fPIC?" +msgstr "" + +#: elf32-sparc.c:2002 +#, c-format +msgid "%s: compiled for a 64 bit system and target is 32 bit" +msgstr "%s£ºÎª 64 λϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇ 32 λµÄ" + +#: elf32-sparc.c:2016 +#, c-format +msgid "%s: linking little endian files with big endian files" +msgstr "%s£ºÁ¬½ÓС¶ËÎļþºÍ´ó¶ËÎļþ" + +#: elf32-v850.c:682 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "±äÁ¿¡°%s¡±²»ÄÜÕ¼¾Ý¶à¸öСÊý¾ÝÇø" + +#: elf32-v850.c:685 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "±äÁ¿¡°%s¡±Ö»ÄܳöÏÖÔÚСÊý¾ÝÇø¡¢ÁãÊý¾ÝÇø¡¢Î¢Êý¾ÝÇøÖ®Ò»" + +#: elf32-v850.c:688 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚСÊý¾ÝÇøºÍÁãÊý¾ÝÇø" + +#: elf32-v850.c:691 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚСÊý¾ÝÇøºÍ΢Êý¾ÝÇø" + +#: elf32-v850.c:694 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "±äÁ¿¡°%s¡±²»ÄÜͬʱ³öÏÖÔÚÁãÊý¾ÝÇøºÍ΢Êý¾ÝÇø" + +#: elf32-v850.c:1072 +msgid "FAILED to find previous HI16 reloc\n" +msgstr "Ñ°ÕÒÉÏÒ»¸ö HI16 Öض¨Î»Ê§°Ü\n" + +#: elf32-v850.c:1703 +msgid "could not locate special linker symbol __gp" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁ¬½ÓÆ÷·ûºÅ __gp" + +#: elf32-v850.c:1707 +msgid "could not locate special linker symbol __ep" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁ¬½ÓÆ÷·ûºÅ __ep" + +#: elf32-v850.c:1711 +msgid "could not locate special linker symbol __ctbp" +msgstr "ÎÞ·¨¶¨Î»ÌØÊâÁª»úÆ÷·ûºÅ __ctbp" + +#: elf32-v850.c:1875 +#, c-format +msgid "%s: Architecture mismatch with previous modules" +msgstr "%s£ºÌåϵ½á¹¹Í¬Ç°Ò»¸öÄ£¿é²»Æ¥Åä" + +#: elf32-v850.c:1895 +#, c-format +msgid "private flags = %lx: " +msgstr "˽ÓбêÖ¾ = %lx£º" + +#: elf32-v850.c:1900 +msgid "v850 architecture" +msgstr "v850 Ìåϵ½á¹¹" + +#: elf32-v850.c:1901 +msgid "v850e architecture" +msgstr "v850e Ìåϵ½á¹¹" + +#: elf32-v850.c:1902 +msgid "v850ea architecture" +msgstr "v850ea Ìåϵ½á¹¹" + +#: elf32-vax.c:546 +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:549 +msgid " [d-float]" +msgstr "" + +#: elf32-vax.c:552 +msgid " [g-float]" +msgstr "" + +#: elf32-vax.c:674 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "" + +#: elf32-vax.c:1679 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "" + +#: elf32-vax.c:1814 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "" + +#: elf32-vax.c:1820 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "" + +#: elf32-ia64.c:2280 elf32-xstormy16.c:414 elf64-ia64.c:2280 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf64-alpha.c:1097 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "GPDISP Öض¨Î»ÎÞ·¨ÕÒµ½ ldah ºÍ lda Ö¸Áî" + +#: elf64-alpha.c:3675 +#, c-format +msgid "%s: .got subsegment exceeds 64K (size %d)" +msgstr "%s£º.got ×Ó½Ú³¬¹ýÁË 64K (´óС %d)" + +#: elf64-alpha.c:4498 elf64-alpha.c:4510 +#, c-format +msgid "%s: gp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4536 elf64-alpha.c:4676 +#, c-format +msgid "%s: pc-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4564 +#, c-format +msgid "%s: change in gp: BRSGP %s" +msgstr "" + +#: elf64-alpha.c:4589 +msgid "" +msgstr "<δ֪>" + +#: elf64-alpha.c:4594 +#, c-format +msgid "%s: !samegp reloc against symbol without .prologue: %s" +msgstr "" + +#: elf64-alpha.c:4639 +#, c-format +msgid "%s: unhandled dynamic relocation against %s" +msgstr "%s£ºÎ´´¦ÀíµÄ¹ØÓÚ %s µÄ¶¯Ì¬Öض¨Î»" + +#: elf64-alpha.c:4752 +#, c-format +msgid "%s: dtp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4775 +#, c-format +msgid "%s: tp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-hppa.c:2080 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "" + +#: elf64-mmix.c:1002 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" + +#: elf64-mmix.c:1386 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1391 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1435 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1440 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1477 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "%s£ºÖ¸Áî LOCAL Ö»¶Ô¼Ä´æÆ÷»ò¾ø¶ÔÖµÓÐЧ" + +#: elf64-mmix.c:1505 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "%s£ºLOCAL Ö¸Á¼Ä´æÆ÷ $%ld ²»ÊDZ¾µØ¼Ä´æÆ÷¡£ µÚÒ»¸öÈ«¾Ö¼Ä´æÆ÷ÊÇ $%ld¡£" + +#: elf64-mmix.c:1965 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "%s£º´íÎó£ºÖظ´¶¨Òå¡°%s¡±£»%s µÄÆðµãÔÚ´ËÇ°Á¬½ÓµÄÎļþÖÐÒÑÉ趨\n" + +#: elf64-mmix.c:2024 +msgid "Register section has contents\n" +msgstr "¼Ä´æÆ÷½ÚÓÐÄÚÈÝ\n" + +#: elf64-mmix.c:2186 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" +"ÄÚ²¿²»Ò»Ö£ºÊ£Óà %u != ×î´ó %u¡£\n" +" Ç뱨¸æ¸Ã bug¡£" + +#: elf64-ppc.c:1669 libbfd.c:1435 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "%s£ºÎª´ó¶Ëϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇС¶ËµÄ" + +#: elf64-ppc.c:1671 libbfd.c:1437 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "%s£ºÎªÐ¡¶Ëϵͳ±àÒ뵫Ŀ±êƽ̨ÊÇ´ó¶ËµÄ" + +#: elf64-ppc.c:3610 +#, c-format +msgid "%s: unexpected reloc type %u in .opd section" +msgstr "%s£º.opd ½ÚÖÐÒâÍâµÄÖض¨Î»ÀàÐÍ %u" + +#: elf64-ppc.c:3630 +#, c-format +msgid "%s: .opd is not a regular array of opd entries" +msgstr "%s£º.opd ²»ÊÇ opd ÌõÄ¿µÄÆÕͨÊý×é" + +#: elf64-ppc.c:3672 +#, c-format +msgid "%s: undefined sym `%s' in .opd section" +msgstr "%s£º.opd ½ÚÖÐ䶨ÒåµÄ¡°%s¡±" + +#: elf64-ppc.c:4397 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:4436 elf64-ppc.c:4501 +#, c-format +msgid "linkage table error against `%s'" +msgstr "" + +#: elf64-ppc.c:4573 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:5179 +msgid "stubs don't match calculated size" +msgstr "" + +#: elf64-ppc.c:5828 +#, c-format +msgid "%s: Relocation %s is not supported for symbol %s." +msgstr "%s£ºÖض¨Î» %s ²»Ö§³Ö·ûºÅ %s¡£" + +#: elf64-ppc.c:5872 +#, c-format +msgid "%s: error: relocation %s not a multiple of 4" +msgstr "%s£º´íÎó£ºÖض¨Î» %s ²»ÊÇ 4 µÄ±¶Êý" + +#: elf64-sparc.c:1280 +#, c-format +msgid "%s: check_relocs: unhandled reloc type %d" +msgstr "%s£ºcheck_relocs£ºÎ´´¦ÀíµÄÖض¨Î»ÀàÐÍ %d" + +#: elf64-sparc.c:1317 +#, c-format +msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "%s£ºÖ»ÓмĴæÆ÷ %%g[2367] ¿ÉÒÔÓà STT_REGISTER À´ÉùÃ÷" + +#: elf64-sparc.c:1337 +#, c-format +msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s" +msgstr "²»¼æÈݵØʹÓüĴæÆ÷ %%g%1$d£ºÔÚ %3$s ÖÐΪ %2$s£¬ÔÚÇ°ÃæµÄ %5$s ÖÐΪ %4$s" + +#: elf64-sparc.c:1360 +#, c-format +msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s" +msgstr "·ûºÅ¡°%1$s¡±µÄÀàÐͲ»Í¬£º%2$s ÖÐΪ¼Ä´æÆ÷£¬ÔÚÇ°ÃæµÄ %4$s ÖÐΪ %3$s" + +#: elf64-sparc.c:1406 +#, c-format +msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s" +msgstr "" + +#: elf64-sparc.c:2970 +#, c-format +msgid "%s: linking UltraSPARC specific with HAL specific code" +msgstr "" + +#: elfcode.h:1198 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "%s£º°æ±¾¼ÆÊý (%ld) ÎÞ·¨Æ¥Åä·ûºÅ¼ÆÊý (%ld)" + +#: elflink.c:440 +#, c-format +msgid "%s: Section %s is too large to add hole of %ld bytes" +msgstr "" + +#: elflink.h:1090 +#, c-format +msgid "%s: warning: unexpected redefinition of `%s'" +msgstr "%s£º¾¯¸æ£ºÒâÍâµÄÖØж¨Òå¡°%s¡±" + +#: elflink.h:1727 +#, c-format +msgid "%s: %s: invalid version %u (max %d)" +msgstr "%s£º%s£ºÎÞЧµÄ°æ±¾ %u (×î´ó %d)" + +#: elflink.h:1768 +#, c-format +msgid "%s: %s: invalid needed version %d" +msgstr "%s£º%s£ºÎÞЧµÄ±Ø±¸°æ±¾ %d" + +#: elflink.h:1890 +#, c-format +msgid "Warning: size of symbol `%s' changed from %lu to %lu in %s" +msgstr "¾¯¸æ£º%4$s ÖеķûºÅ¡°%1$s¡±µÄ´óСÓÉ %2$lu ±äΪ %3$lu" + +#: elflink.h:3174 +#, c-format +msgid "%s: .preinit_array section is not allowed in DSO" +msgstr "%s£ºDSO Öв»ÔÊÐí³öÏÖ .preinit_array ½Ú" + +#: elflink.h:4030 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "¾¯¸æ£º¶¯Ì¬·ûºÅ¡°%s¡±µÄÀàÐͺʹóС䶨Òå" + +#: elflink.h:4345 +#, c-format +msgid "%s: undefined versioned symbol name %s" +msgstr "%s£ºÎ´¶¨ÒåµÄÓа汾·ûºÅÃû %s" + +#: elflink.h:4611 elflink.h:4619 elflink.h:6508 elflink.h:7600 +msgid "Error: out of memory" +msgstr "´íÎó£ºÃ»ÓÐÄÚ´æ" + +#: elflink.h:4781 +msgid "Not enough memory to sort relocations" +msgstr "ûÓÐ×ã¹»µÄÄÚ´æ½øÐÐÖض¨Î»ÅÅÐò" + +#: elflink.h:5682 elflink.h:5725 +#, c-format +msgid "%s: could not find output section %s" +msgstr "%s£ºÎÞ·¨ÕÒµ½Êä³ö½Ú %s" + +#: elflink.h:5688 +#, c-format +msgid "warning: %s section has zero size" +msgstr "¾¯¸æ£º%s ½ÚµÄ´óСΪÁã" + +#: elflink.h:6275 +#, c-format +msgid "%s: could not find output section %s for input section %s" +msgstr "%1$s£ºÎÞ·¨ÎªÊäÈë½Ú %3$s ÕÒµ½Êä³ö½Ú %2$s" + +#: elflink.h:6486 +#, c-format +msgid "%s: relocation size mismatch in %s section %s" +msgstr "" + +#: elflink.h:6849 +msgid "warning: relocation against removed section; zeroing" +msgstr "¾¯¸æ£º¹ØÓÚÒÑɾ³ýµÄ½ÚµÄÖض¨Î»£»ÕýÔÚÇåÁã" + +#: elflink.h:6879 +msgid "warning: relocation against removed section" +msgstr "¾¯¸æ£º¹ØÓÚÒÑɾ³ýµÄ½ÚµÄÖض¨Î»" + +#: elflink.h:6892 +#, c-format +msgid "local symbols in discarded section %s" +msgstr "ÒѽûÓÃµÄ½Ú %s Öеı¾µØ·ûºÅ" + +#: elfxx-mips.c:734 +msgid "static procedure (no name)" +msgstr "¾²Ì¬¹ý³Ì (ÎÞÃû³Æ)" + +#: elfxx-mips.c:1601 +msgid "not enough GOT space for local GOT entries" +msgstr "ûÓÐ×ã¹»µÄ GOT ¿Õ¼äÓÃÓÚ GOT ÌõÄ¿" + +#: elfxx-mips.c:2750 +#, c-format +msgid "%s: %s+0x%lx: jump to stub routine which is not jal" +msgstr "" + +#: elfxx-mips.c:4270 +#, c-format +msgid "%s: Malformed reloc detected for section %s" +msgstr "" + +#: elfxx-mips.c:4348 +#, c-format +msgid "%s: CALL16 reloc at 0x%lx not against global symbol" +msgstr "" + +#: elfxx-mips.c:7301 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "%s£º·Ç·¨µÄ½ÚÃû¡°%s¡±" + +#: elfxx-mips.c:7615 +#, c-format +msgid "%s: linking PIC files with non-PIC files" +msgstr "%s£º½« PIC Îļþͬ·Ç-PIC ÎļþÁ¬½Ó" + +#: elfxx-mips.c:7625 +#, c-format +msgid "%s: linking abicalls files with non-abicalls files" +msgstr "" + +#: elfxx-mips.c:7654 +#, c-format +msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" +msgstr "%s£ºISA (-mips%d) ͬǰÃæµÄÄ£¿é(-mips%d)²»Æ¥Åä" + +#: elfxx-mips.c:7676 +#, c-format +msgid "%s: ISA mismatch (%d) with previous modules (%d)" +msgstr "%s£ºISA (%d) ͬǰÃæµÄÄ£¿é (%d) ²»Æ¥Åä" + +#: elfxx-mips.c:7699 +#, c-format +msgid "%s: ABI mismatch: linking %s module with previous %s modules" +msgstr "%s£ºABI ²»Æ¥Å䣺ÕýÔÚ½«Ä£¿é %s ͬǰһ¸öÄ£¿é %s ½øÐÐÁ¬½Ó" + +#: elfxx-mips.c:7759 +msgid " [abi=O32]" +msgstr " [abi=O32]" + +#: elfxx-mips.c:7761 +msgid " [abi=O64]" +msgstr " [abi=O64]" + +#: elfxx-mips.c:7763 +msgid " [abi=EABI32]" +msgstr " [abi=EABI32]" + +#: elfxx-mips.c:7765 +msgid " [abi=EABI64]" +msgstr " [abi=EABI64]" + +#: elfxx-mips.c:7767 +msgid " [abi unknown]" +msgstr " [abi δ֪]" + +#: elfxx-mips.c:7769 +msgid " [abi=N32]" +msgstr " [abi=N32]" + +#: elfxx-mips.c:7771 +msgid " [abi=64]" +msgstr " [abi=64]" + +#: elfxx-mips.c:7773 +msgid " [no abi set]" +msgstr "" + +#: elfxx-mips.c:7776 +msgid " [mips1]" +msgstr " [mips1]" + +#: elfxx-mips.c:7778 +msgid " [mips2]" +msgstr " [mips2]" + +#: elfxx-mips.c:7780 +msgid " [mips3]" +msgstr " [mips3]" + +#: elfxx-mips.c:7782 +msgid " [mips4]" +msgstr " [mips4]" + +#: elfxx-mips.c:7784 +msgid " [mips5]" +msgstr " [mips5]" + +#: elfxx-mips.c:7786 +msgid " [mips32]" +msgstr " [mips32]" + +#: elfxx-mips.c:7788 +msgid " [mips64]" +msgstr " [mips64]" + +#: elfxx-mips.c:7790 +msgid " [unknown ISA]" +msgstr " [δ֪µÄ ISA]" + +#: elfxx-mips.c:7793 +msgid " [mdmx]" +msgstr " [mdmx]" + +#: elfxx-mips.c:7796 +msgid " [mips16]" +msgstr " [mips16]" + +#: elfxx-mips.c:7799 +msgid " [32bitmode]" +msgstr " [32λģʽ]" + +#: elfxx-mips.c:7801 +msgid " [not 32bitmode]" +msgstr " [·Ç 32λģʽ]" + +#: i386linux.c:458 m68klinux.c:462 sparclinux.c:459 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "Êä³öÎļþÐèÒª¹²Ïí¿â¡°%s¡±\n" + +#: i386linux.c:466 m68klinux.c:470 sparclinux.c:467 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "Êä³öÎļþÐèÒª¹²Ïí¿â¡°%s.so.%s¡±\n" + +#: i386linux.c:655 i386linux.c:705 m68klinux.c:662 m68klinux.c:710 +#: sparclinux.c:657 sparclinux.c:707 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "" + +#: i386linux.c:729 m68klinux.c:734 sparclinux.c:731 +msgid "Warning: fixup count mismatch\n" +msgstr "" + +#: ieee.c:235 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "%s£º×Ö·û´®¹ý³¤ (%d ×Ö·û£¬×î´ó 65535)" + +#: ieee.c:365 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "%s£ºÎÞ·¨Ê¶±ðµÄ¡°%s¡±±êÖ¾ 0x%x" + +#: ieee.c:877 +#, c-format +msgid "%s: unimplemented ATI record %u for symbol %u" +msgstr "" + +#: ieee.c:902 +#, c-format +msgid "%s: unexpected ATN type %d in external part" +msgstr "" + +#: ieee.c:924 +#, c-format +msgid "%s: unexpected type after ATN" +msgstr "%s£ºATN Ö®ºó³öÏÖÒâÍâµÄÀàÐÍ" + +#: ihex.c:258 +#, c-format +msgid "%s:%d: unexpected character `%s' in Intel Hex file\n" +msgstr "%s£º%d£ºIntel Ê®Áù½øÖÆÎļþÖеÄÒâÍâ×Ö·û¡°%s\n" + +#: ihex.c:366 +#, c-format +msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "%s£º%u£ºIntel Ê®Áù½øÖÆÎļþÖеÄУÑéºÍ´íÎó (ӦΪ %u¡¢ÊµÎª %u)" + +#: ihex.c:420 +#, c-format +msgid "%s:%u: bad extended address record length in Intel Hex file" +msgstr "" + +#: ihex.c:437 +#, c-format +msgid "%s:%u: bad extended start address length in Intel Hex file" +msgstr "" + +#: ihex.c:454 +#, c-format +msgid "%s:%u: bad extended linear address record length in Intel Hex file" +msgstr "" + +#: ihex.c:471 +#, c-format +msgid "%s:%u: bad extended linear start address length in Intel Hex file" +msgstr "" + +#: ihex.c:488 +#, c-format +msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n" +msgstr "" + +#: ihex.c:607 +#, c-format +msgid "%s: internal error in ihex_read_section" +msgstr "" + +#: ihex.c:642 +#, c-format +msgid "%s: bad section length in ihex_read_section" +msgstr "" + +#: ihex.c:860 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "" + +#: libbfd.c:492 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "" + +#: libbfd.c:495 +msgid "not mapping: env var not set\n" +msgstr "" + +#: libbfd.c:1466 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "" + +#: libbfd.c:1469 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1873 +#, c-format +msgid "%s: indirect symbol `%s' to `%s' is a loop" +msgstr "" + +#: linker.c:2776 +#, c-format +msgid "Attempt to do relocateable link with %s input and %s output" +msgstr "" + +#: merge.c:892 +#, c-format +msgid "%s: access beyond end of merged section (%ld + %ld)" +msgstr "" + +#: mmo.c:460 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "" + +#: mmo.c:536 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "" + +#: mmo.c:1245 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "" + +#: mmo.c:1391 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "" + +#: mmo.c:1633 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "" + +#: mmo.c:1643 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "" + +#: mmo.c:1679 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" + +#: mmo.c:1725 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "" + +#: mmo.c:1764 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1773 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1796 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1819 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "" + +#: mmo.c:1839 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "" + +#: mmo.c:1852 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" + +#: mmo.c:1958 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" + +#: mmo.c:1994 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "" + +#: mmo.c:2007 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "" + +#: mmo.c:2670 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "" + +#: mmo.c:2921 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "" + +#: mmo.c:3011 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "" + +#: mmo.c:3056 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "" + +#: mmo.c:3111 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "" + +#: mmo.c:3163 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "" + +#: mmo.c:3169 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "" + +#: mmo.c:3174 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "" + +#: oasys.c:1029 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "" + +#: osf-core.c:132 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "" + +#: pe-mips.c:658 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:794 +#, c-format +msgid "%s: unimplemented %s\n" +msgstr "%s£ºÎ´ÊµÏÖµÄ %s\n" + +#: pe-mips.c:820 +#, c-format +msgid "%s: jump too far away\n" +msgstr "%s£ºÌøת¹ýÔ¶\n" + +#: pe-mips.c:847 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "" + +#. XXX code yet to be written. +#: peicode.h:785 +#, c-format +msgid "%s: Unhandled import type; %x" +msgstr "%s£ºÎ´´¦ÀíµÄµ¼ÈëÀàÐÍ£»%x" + +#: peicode.h:790 +#, c-format +msgid "%s: Unrecognised import type; %x" +msgstr "%s£ºÎ´Ê¶±ðµÄµ¼ÈëÀàÐÍ£»%x" + +#: peicode.h:804 +#, c-format +msgid "%s: Unrecognised import name type; %x" +msgstr "%s£ºÎ´Ê¶±ðµÄµ¼ÈëÃû×ÖÀàÐÍ£»%x" + +#: peicode.h:1162 +#, c-format +msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1174 +#, c-format +msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1191 +#, c-format +msgid "%s: size field is zero in Import Library Format header" +msgstr "" + +#: peicode.h:1219 +#, c-format +msgid "%s: string not null terminated in ILF object file." +msgstr "" + +#: ppcboot.c:416 +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" + +#: ppcboot.c:417 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "ÌõÄ¿Æ«ÒÆÁ¿ = 0x%.8lx (%ld)\n" + +#: ppcboot.c:418 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "³¤¶È = 0x%.8lx (%ld)\n" + +#: ppcboot.c:421 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "±êÖ¾Óò = 0x%.2x\n" + +#: ppcboot.c:427 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "·ÖÇøÃû = \"%s\"\n" + +#: ppcboot.c:446 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" +"\n" +"·ÖÇø[%d] Æðµã = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:452 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "·ÖÇø[%d] ÖÕµã = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" + +#: ppcboot.c:458 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "·ÖÇø[%d] ÉÈÇø = 0x%.8lx (%ld)\n" + +#: ppcboot.c:459 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "·ÖÇø[%d] ³¤¶È = 0x%.8lx (%ld)\n" + +#: som.c:5398 +msgid "som_sizeof_headers unimplemented" +msgstr "" + +#: srec.c:301 +#, c-format +msgid "%s:%d: Unexpected character `%s' in S-record file\n" +msgstr "" + +#: stabs.c:319 +#, c-format +msgid "%s(%s+0x%lx): Stabs entry has invalid string index." +msgstr "" + +#: syms.c:1044 +msgid "Unsupported .stab relocation" +msgstr "²»Ö§³ÖµÄ .stab Öض¨Î»" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "" + +#: vms-gsd.c:702 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "" + +#: vms-hdr.c:406 +msgid "Object module NOT error-free !\n" +msgstr "" + +#: vms-misc.c:543 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "" + +#: vms-misc.c:561 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "" + +#: vms-misc.c:919 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "" + +#: vms-misc.c:924 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "" + +#: vms-misc.c:1055 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "" + +#: vms-misc.c:1117 +#, c-format +msgid "failed to enter %s" +msgstr "" + +#: vms-tir.c:81 +msgid "No Mem !" +msgstr "" + +#: vms-tir.c:362 +#, c-format +msgid "bad section index in %s" +msgstr "%s ÖеĴíÎó½ÚË÷Òý" + +#: vms-tir.c:375 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "²»Ö§³ÖµÄ STA ÃüÁî %s" + +#: vms-tir.c:380 vms-tir.c:1240 +#, c-format +msgid "reserved STA cmd %d" +msgstr "" + +#: vms-tir.c:491 vms-tir.c:514 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:581 vms-tir.c:693 vms-tir.c:803 vms-tir.c:821 vms-tir.c:829 +#: vms-tir.c:838 vms-tir.c:1563 +#, c-format +msgid "%s: not supported" +msgstr "%s£º²»Ö§³Ö" + +#: vms-tir.c:586 vms-tir.c:1418 +#, c-format +msgid "%s: not implemented" +msgstr "%s£ºÎ´ÊµÏÖ" + +#: vms-tir.c:590 vms-tir.c:1422 +#, c-format +msgid "reserved STO cmd %d" +msgstr "±£ÁôµÄ STO ÃüÁî %d" + +#: vms-tir.c:708 vms-tir.c:1568 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "±£ÁôµÄ OPR ÃüÁî %d" + +#: vms-tir.c:776 vms-tir.c:1632 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "±£ÁôµÄ CTL ÃüÁî %d" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1148 +msgid "stack-from-image not implemented" +msgstr "δʵÏÖ stack-from-image" + +#: vms-tir.c:1166 +msgid "stack-entry-mask not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-entry-mask" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1180 +msgid "PASSMECH not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ PASSMECH" + +#: vms-tir.c:1199 +msgid "stack-local-symbol not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-local-symbol" + +#: vms-tir.c:1212 +msgid "stack-literal not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-literal" + +#: vms-tir.c:1233 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "ÉÐδÍêȫʵÏÖ stack-local-symbol-entry-point-mask" + +#: vms-tir.c:1510 vms-tir.c:1522 vms-tir.c:1534 vms-tir.c:1546 vms-tir.c:1611 +#: vms-tir.c:1619 vms-tir.c:1627 +#, c-format +msgid "%s: not fully implemented" +msgstr "%s£ºÉÐδÍêȫʵÏÖ" + +#: vms-tir.c:1684 +#, c-format +msgid "obj code %d not found" +msgstr "" + +#: vms-tir.c:2019 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "" + +#: vms-tir.c:2307 +#, c-format +msgid "Unhandled relocation %s" +msgstr "δ´¦ÀíµÄÖض¨Î» %s" + +#: xcofflink.c:1243 +#, c-format +msgid "%s: `%s' has line numbers but no enclosing section" +msgstr "" + +#: xcofflink.c:1296 +#, c-format +msgid "%s: class %d symbol `%s' has no aux entries" +msgstr "" + +#: xcofflink.c:1319 +#, c-format +msgid "%s: symbol `%s' has unrecognized csect type %d" +msgstr "" + +#: xcofflink.c:1331 +#, c-format +msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "" + +#: xcofflink.c:1367 +#, c-format +msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "" + +#: xcofflink.c:1519 +#, c-format +msgid "%s: csect `%s' not in enclosing section" +msgstr "" + +#: xcofflink.c:1626 +#, c-format +msgid "%s: misplaced XTY_LD `%s'" +msgstr "" + +#: xcofflink.c:1957 +#, c-format +msgid "%s: reloc %s:%d not in csect" +msgstr "" + +#: xcofflink.c:2092 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "" + +#: xcofflink.c:2113 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "" + +#: xcofflink.c:2758 +#, c-format +msgid "%s: no such symbol" +msgstr "" + +#: xcofflink.c:2891 +msgid "error: undefined symbol __rtinit" +msgstr "´íÎó£ºÎ´¶¨ÒåµÄ·ûºÅ __rtinit" + +#: xcofflink.c:3453 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "¾¯¸æ£ºÊÔͼµ¼³ö䶨ÒåµÄ·ûºÅ¡°%s¡±" + +#: xcofflink.c:4447 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "" + +#: xcofflink.c:5287 xcofflink.c:5756 xcofflink.c:5818 xcofflink.c:6119 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "" + +#: xcofflink.c:5309 xcofflink.c:6130 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "" + +#: xcofflink.c:5324 +#, c-format +msgid "%s: loader reloc in read-only section %s" +msgstr "" + +#: elf32-ia64.c:2222 elf64-ia64.c:2222 +msgid "@pltoff reloc against local symbol" +msgstr "" + +#: elf32-ia64.c:3562 elf64-ia64.c:3562 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf32-ia64.c:3573 elf64-ia64.c:3573 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf32-ia64.c:3858 elf64-ia64.c:3858 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "" + +#: elf32-ia64.c:3891 elf64-ia64.c:3891 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4030 elf64-ia64.c:4030 +#, c-format +msgid "%s: dynamic relocation against speculation fixup" +msgstr "" + +#: elf32-ia64.c:4038 elf64-ia64.c:4038 +#, c-format +msgid "%s: speculation fixup against undefined weak symbol" +msgstr "" + +#: elf32-ia64.c:4271 elf64-ia64.c:4271 +msgid "unsupported reloc" +msgstr "²»Ö§³ÖµÄÖض¨Î»" + +#: elf32-ia64.c:4551 elf64-ia64.c:4551 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf32-ia64.c:4560 elf64-ia64.c:4560 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "%s£º½«´ó¶ËÎļþͬС¶ËÎļþ" + +#: elf32-ia64.c:4569 elf64-ia64.c:4569 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "%s£º½« 64-λÎļþͬ 32-λÎļþÁ¬½Ó" + +#: elf32-ia64.c:4578 elf64-ia64.c:4578 +#, c-format +msgid "%s: linking constant-gp files with non-constant-gp files" +msgstr "" + +#: elf32-ia64.c:4588 elf64-ia64.c:4588 +#, c-format +msgid "%s: linking auto-pic files with non-auto-pic files" +msgstr "" + +#: peigen.c:962 pepigen.c:962 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "%s£ºÐкÅÒç³ö£º0x%lx > 0xffff" + +#: peigen.c:979 pepigen.c:979 +#, c-format +msgid "%s: reloc overflow 1: 0x%lx > 0xffff" +msgstr "" + +#: peigen.c:993 pepigen.c:993 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "µ¼³öĿ¼ [.edata (»òÕßÆäËüÈκÎÄÜÕÒµ½ËüµÄµØ·½)]" + +#: peigen.c:994 pepigen.c:994 +msgid "Import Directory [parts of .idata]" +msgstr "µ¼ÈëĿ¼ [.idata µÄÒ»²¿·Ö]" + +#: peigen.c:995 pepigen.c:995 +msgid "Resource Directory [.rsrc]" +msgstr "×ÊԴĿ¼ [.rsrc]" + +#: peigen.c:996 pepigen.c:996 +msgid "Exception Directory [.pdata]" +msgstr "" + +#: peigen.c:997 pepigen.c:997 +msgid "Security Directory" +msgstr "°²È«Ä¿Â¼" + +#: peigen.c:998 pepigen.c:998 +msgid "Base Relocation Directory [.reloc]" +msgstr "" + +#: peigen.c:999 pepigen.c:999 +msgid "Debug Directory" +msgstr "µ÷ÊÔĿ¼" + +#: peigen.c:1000 pepigen.c:1000 +msgid "Description Directory" +msgstr "ÃèÊöĿ¼" + +#: peigen.c:1001 pepigen.c:1001 +msgid "Special Directory" +msgstr "ÌØÊâĿ¼" + +#: peigen.c:1002 pepigen.c:1002 +msgid "Thread Storage Directory [.tls]" +msgstr "Ï̴߳洢Ŀ¼ [.tls]" + +#: peigen.c:1003 pepigen.c:1003 +msgid "Load Configuration Directory" +msgstr "×°ÈëÅäÖÃĿ¼" + +#: peigen.c:1004 pepigen.c:1004 +msgid "Bound Import Directory" +msgstr "" + +#: peigen.c:1005 pepigen.c:1005 +msgid "Import Address Table Directory" +msgstr "µ¼ÈëµØÖ·±íĿ¼" + +#: peigen.c:1006 pepigen.c:1006 +msgid "Delay Import Directory" +msgstr "ÑÓ³Ùµ¼ÈëĿ¼" + +#: peigen.c:1007 peigen.c:1008 pepigen.c:1007 pepigen.c:1008 +msgid "Reserved" +msgstr "±£Áô" + +#: peigen.c:1071 pepigen.c:1071 +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1076 pepigen.c:1076 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1113 pepigen.c:1113 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" + +#: peigen.c:1116 pepigen.c:1116 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "" + +#: peigen.c:1122 pepigen.c:1122 +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" + +#: peigen.c:1127 pepigen.c:1127 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" + +#: peigen.c:1130 pepigen.c:1130 +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" + +#: peigen.c:1181 pepigen.c:1181 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" +"\n" +"\tDLL Ãû³Æ£º%s\n" + +#: peigen.c:1192 pepigen.c:1192 +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "" + +#: peigen.c:1217 pepigen.c:1217 +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1357 pepigen.c:1357 +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1362 pepigen.c:1362 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" +"\n" +"%s Öеĵ¼³ö±íλÓÚ 0x%lx\n" + +#: peigen.c:1393 pepigen.c:1393 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" + +#: peigen.c:1397 pepigen.c:1397 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "µ¼³ö±êÖ¾ \t\t\t%lx\n" + +#: peigen.c:1400 pepigen.c:1400 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "ÈÕÆÚ/ʱ¼ä´Á \t\t%lx\n" + +#: peigen.c:1403 pepigen.c:1403 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "" + +#: peigen.c:1406 pepigen.c:1406 +msgid "Name \t\t\t\t" +msgstr "Ãû³Æ \t\t\t\t" + +#: peigen.c:1412 pepigen.c:1412 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "" + +#: peigen.c:1415 pepigen.c:1415 +msgid "Number in:\n" +msgstr "" + +#: peigen.c:1418 pepigen.c:1418 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "" + +#: peigen.c:1422 pepigen.c:1422 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "" + +#: peigen.c:1425 pepigen.c:1425 +msgid "Table Addresses\n" +msgstr "±íµØÖ·\n" + +#: peigen.c:1428 pepigen.c:1428 +msgid "\tExport Address Table \t\t" +msgstr "\tµ¼³öµØÖ·±í \t\t" + +#: peigen.c:1433 pepigen.c:1433 +msgid "\tName Pointer Table \t\t" +msgstr "\tÃû³ÆÖ¸Õë±í \t\t" + +#: peigen.c:1438 pepigen.c:1438 +msgid "\tOrdinal Table \t\t\t" +msgstr "" + +#: peigen.c:1453 pepigen.c:1453 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" + +#: peigen.c:1472 pepigen.c:1472 +msgid "Forwarder RVA" +msgstr "" + +#: peigen.c:1483 pepigen.c:1483 +msgid "Export RVA" +msgstr "µ¼³ö RVA" + +#: peigen.c:1490 pepigen.c:1490 +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" + +#: peigen.c:1545 pepigen.c:1545 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "" + +#: peigen.c:1549 pepigen.c:1549 +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" + +#: peigen.c:1552 pepigen.c:1552 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "" + +#: peigen.c:1554 pepigen.c:1554 +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" + +#: peigen.c:1624 pepigen.c:1624 +msgid " Register save millicode" +msgstr "" + +#: peigen.c:1627 pepigen.c:1627 +msgid " Register restore millicode" +msgstr "" + +#: peigen.c:1630 pepigen.c:1630 +msgid " Glue code sequence" +msgstr "" + +#: peigen.c:1682 pepigen.c:1682 +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" + +#: peigen.c:1712 pepigen.c:1712 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" + +#: peigen.c:1725 pepigen.c:1725 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1765 pepigen.c:1765 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" diff --git a/external/gpl3/gdb/dist/include/COPYING b/external/gpl3/gdb/dist/include/COPYING new file mode 100644 index 000000000000..623b6258a134 --- /dev/null +++ b/external/gpl3/gdb/dist/include/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/external/gpl3/gdb/dist/include/COPYING3 b/external/gpl3/gdb/dist/include/COPYING3 new file mode 100644 index 000000000000..94a9ed024d38 --- /dev/null +++ b/external/gpl3/gdb/dist/include/COPYING3 @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. 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If the +Program specifies that a certain numbered version of the GNU General +Public License "or any later version" applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU General Public License, you may choose any version ever published +by the Free Software Foundation. + + If the Program specifies that a proxy can decide which future +versions of the GNU General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + + Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + + 15. Disclaimer of Warranty. + + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY +APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT +HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY +OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM +IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF +ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF +DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD +PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), +EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF +SUCH DAMAGES. + + 17. Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/external/gpl3/gdb/dist/include/ChangeLog b/external/gpl3/gdb/dist/include/ChangeLog new file mode 100644 index 000000000000..fc1dd5667903 --- /dev/null +++ b/external/gpl3/gdb/dist/include/ChangeLog @@ -0,0 +1,1421 @@ +2011-07-02 Jan Kratochvil + + * demangle.h (DMGL_RET_POSTFIX): Extend the comment. + (DMGL_RET_DROP): New. + +2011-03-31 Tristan Gingold + + * dwarf2.h (dwarf_line_number_hp_sfc_ops): New enum. + +2011-03-24 Mark Wielaard + + * dwarf2.h (dwarf_form): Remove deprecated DW_FORM_sig8 define. + +2010-03-23 Rafael Ãvila de Espíndola + + * plugin-api.h (ld_plugin_get_view): New. + (ld_plugin_tag): Add LDPT_GET_VIEW. + (ld_plugin_tv): Add tv_get_view. + +2011-03-16 Jakub Jelinek + + * dwarf2.h (DW_TAG_GNU_call_site, DW_TAG_GNU_call_site_parameter, + DW_AT_GNU_call_site_value, DW_AT_GNU_call_site_data_value, + DW_AT_GNU_call_site_target, DW_AT_GNU_call_site_target_clobbered, + DW_AT_GNU_tail_call, DW_AT_GNU_all_tail_call_sites, + DW_AT_GNU_all_call_sites,, DW_AT_GNU_all_source_call_sites, + DW_OP_GNU_entry_value): New. + +2011-02-28 Kai Tietz + + * filenames.h (filename_ncmp): New prototype. + +2011-02-23 Kai Tietz + + * dwarf2.h (_ELF_DWARF2_H): Renamed to + _DWARF2_H. + (DWARF2_External_LineInfo, DWARF2_Internal_LineInfo, + DWARF2_External_PubNames, DWARF2_Internal_PubNames, + DWARF2_External_CompUnit, DWARF2_Internal_CompUnit, + DWARF2_External_ARange, DWARF2_Internal_ARange): Removed. + +2011-02-08 Ulrich Weigand + + * dwarf2.h (enum dwarf_calling_convention): Add DW_CC_GDB_IBM_OpenCL. + +2011-01-12 Iain Sandoe + + * dwarf2.h: Update value for DW_AT_hi_user. + +2010-11-25 Andreas Krebbel + + * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU. + +2010-11-16 Ian Lance Taylor + + * simple-object.h (simple_object_attributes_merge): Declare, + replacing simple_object_attributes_compare. + +2010-11-16 Jie Zhang + + * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. + (EF_BFIN_DATA_IN_L1): Define. + +2010-11-04 Ian Lance Taylor + + * dwarf2.h (enum dwarf_source_language): Add DW_LANG_Go. + +2010-11-02 Ian Lance Taylor + + * simple-object.h: New file. + +2010-10-15 Dave Korn + + Sync LD plugin patch series (part 1/6) with src/include/. + * plugin-api.h (LDPT_GNU_LD_VERSION): New ld_plugin_tag enum member. + +2010-10-14 Dave Korn + + Apply LD plugin patch series (part 6/6). + * bfdlink.h (struct_bfd_link_callbacks): Document new argument + to add_archive_element callback used to return a replacement bfd which + is to be added to the hash table in place of the original element. + +2010-10-14 Dave Korn + + Apply LD plugin patch series (part 1/6). + * plugin-api.h (LDPT_GNU_LD_VERSION): New ld_plugin_tag enum member. + +2010-10-06 Andi Kleen + + * libiberty.h (setproctitle): Add prototype. + +2010-09-29 Bernd Schmidt + + * opcode/tic6x-control-registers.h (tscl): Now read_write. + +2010-09-27 Andreas Krebbel + + * opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. + +2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_V6Z): Remove. + (ARM_EXT_SEC): New define. + (ARM_AEXT_V6Z): Use Security Extensions. + (ARM_AEXT_V6ZK): Likeiwse. + (ARM_AEXT_V6ZT2): Likewise. + (ARM_AEXT_V6ZKT2): Likewise. + (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. + (ARM_ARCH_V7A_SEC): New define. + (ARM_ARCH_V7A_MP): Rename... + (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. + +2010-09-09 Jakub Jelinek + + * dwarf2.h (DW_OP_GNU_implicit_pointer): New. + +2010-07-06 Ken Werner + + * floatformat.h (floatformat_ieee_half_big): Add declaration. + (floatformat_ieee_half_little): Likewise. + +2010-06-29 Alan Modra + + * dis-asm.h: Remove references to maxq. + +2010-06-21 Rafael Espindola + + * plugin-api.h (ld_plugin_set_extra_library_path): New. + (ld_plugin_tag): Add LDPT_SET_EXTRA_LIBRARY_PATH. + (ld_plugin_tv): Add tv_set_extra_library_path. + +2010-06-21 Jakub Jelinek + + * dwarf2.h (enum dwarf_type): Add DW_ATE_UTF. + +2010-06-18 Rafael Espindola + + * plugin.h (ld_plugin_add_input_file, ld_plugin_add_input_library): + Make argument const. + +2010-06-08 Laurynas Biveinis + + * splay-tree.h: Update copyright years. + (splay_tree_s): Document fields. + (splay_tree_new_typed_alloc): New. + + * hashtab.h: Update copyright years. + (htab_create_typed_alloc): New. + +2010-06-10 Tristan Gingold + + * dwarf2.h (enum dwarf_tag): Add DW_TAG_HP_Bliss_field and + DW_TAG_HP_Bliss_field_set. + (enum dwarf_attribute): Add DW_AT_HP_prologue, DW_AT_HP_epilogue, + DW_AT_HP_unit_name, DW_AT_HP_unit_size, DW_AT_HP_widened_byte_size, + DW_AT_HP_definition_points, DW_AT_HP_default_location and + DW_AT_HP_is_result_param. + (enum dwarf_type): Add DW_ATE_HP_VAX_float, DW_ATE_HP_VAX_float_d, + DW_ATE_HP_packed_decimal, DW_ATE_HP_zoned_decimal, DW_ATE_HP_edited, + DW_ATE_HP_signed_fixed, DW_ATE_HP_unsigned_fixed, + DW_ATE_HP_VAX_complex_float and DW_ATE_HP_VAX_complex_float_d. + (enum dwarf_line_number_x_ops): Add + DW_LNE_HP_source_file_correlation. + (enum dwarf_source_language): Add DW_LANG_HP_Bliss, + DW_LANG_HP_Basic91, DW_LANG_HP_Pascal91, DW_LANG_HP_IMacro, + DW_LANG_HP_Assembler. + +2010-06-01 Rafael Espindola + + * plugin-api.h (ld_plugin_tag): Add LDPT_OUTPUT_NAME. + +2010-04-26 Pedro Alves + + * filenames.h (PATH_SEPARATOR): Delete. + +2010-04-23 Pedro Alves + + * filenames.h (IS_DIR_SEPARATOR_1): Rename from IS_DIR_SEPARATOR, + always define it independently of host, add `dos_based' parameter, + and handle it. + (PATH_SEPARATOR): Define. + (HAS_DRIVE_SPEC_1): Rename from HAS_DRIVE_SPEC, always define it + independently of host, add `dos_based' parameter, and handle it. + (IS_ABSOLUTE_PATH_1): Rename from IS_ABSOLUTE_PATH, always define + it independently of host, add `dos_based' parameter, and handle + it. + (IS_DOS_DIR_SEPARATOR, IS_DOS_ABSOLUTE_PATH) + (IS_UNIX_DIR_SEPARATOR, IS_UNIX_ABSOLUTE_PATH) + (HAS_DOS_DRIVE_SPEC): New. + (HAS_DRIVE_SPEC): Reimplement on top of HAS_DRIVE_SPEC_1. + (IS_DIR_SEPARATOR): Reimplement on top of IS_DIR_SEPARATOR_1. + (IS_ABSOLUTE_PATH): Reimplement on top of IS_ABSOLUTE_PATH_1. + * libiberty.h (dos_lbasename, unix_lbasename): Declare. + +2009-05-31 Ian Lance Taylor + + * ansidecl.h: Add extern "C" when compiling with C++. Treat C++ + the way we treat an ISO C compiler. Don't define inline as a + macro when compiling with C++. + * dyn-string.h: Add header guard DYN_STRING_H. Add extern "C" + when compiling with C++. + * fibheap.h: Add extern "C" when compiling with C++. + +2010-04-23 Pedro Alves + + * filenames.h (IS_DIR_SEPARATOR_1): Rename from IS_DIR_SEPARATOR, + always define it independently of host, add `dos_based' parameter, + and handle it. + (HAS_DRIVE_SPEC_1): Rename from HAS_DRIVE_SPEC, always define it + independently of host, add `dos_based' parameter, and handle it. + (IS_ABSOLUTE_PATH_1): Rename from IS_ABSOLUTE_PATH, always define + it independently of host, add `dos_based' parameter, and handle + it. + (IS_DOS_DIR_SEPARATOR, IS_DOS_ABSOLUTE_PATH) + (IS_UNIX_DIR_SEPARATOR, IS_UNIX_ABSOLUTE_PATH) + (HAS_DOS_DRIVE_SPEC): New. + (HAS_DRIVE_SPEC): Reimplement on top of HAS_DRIVE_SPEC_1. + (IS_DIR_SEPARATOR): Reimplement on top of IS_DIR_SEPARATOR_1. + (IS_ABSOLUTE_PATH): Reimplement on top of IS_ABSOLUTE_PATH_1. + * libiberty.h (dos_lbasename, unix_lbasename): Declare. + +2010-04-20 Nick Clifton + + * sha1.h: Update copyright notice to use GPLv3. + +2010-04-15 Nick Clifton + + * bout.h: Update copyright notice to use GPLv3. + * hp-symtab.h: Likewise. + * oasys.h: Likewise. + * progress.h: Likewise. + * sha1.h: Likewise. + * xtensa-isa-internal.h: Likewise. + * xtensa-isa.h: Likewise. + +2010-04-14 Doug Evans + + * filenames.h (HAS_DRIVE_SPEC, STRIP_DRIVE_SPEC): New macros. + +2010-04-05 Jakub Jelinek + + * dwarf2.h (DWARF2_Internal_LineInfo): Add li_max_ops_per_insn + field. + +2010-03-25 Joseph Myers + + * dis-asm.h (print_insn_tic6x): Declare. + +2010-03-23 Joseph Myers + + * symcat.h (CONCAT5, CONCAT6, XCONCAT5, XCONCAT6): Define. + +2010-01-13 Joel Brobecker + + Add new DW_AT_use_GNAT_descriptive_type CU attribute. + * dwarf2.h (dwarf_attribute): Add DW_AT_use_GNAT_descriptive_type. + +2010-01-11 Tristan Gingold + + * demangle.h (ada_demangle): Add prototype. + +2010-01-05 Rainer Orth + + PR bootstrap/41771 + * ansidecl.h: Fix inline test for C99 and Sun Studio cc. + +2009-12-29 Joel Brobecker + + * dwarf2.h (enum dwarf_attribute): Add DW_AT_GNAT_descriptive_type. + +2009-12-14 Doug Kwan + + * bfdlink.h (struct bfd_link_callbacks): Rename function parameters + to avoid shadowed variable warnings. + * dis-asm.h (struct disassemble_info): Ditto. + (disassemble_init_for_target): Ditto. + (init_disassemble_info): Ditto. + +2009-12-03 David Daney + Adam Nemet + + * elf/mips.h (E_MIPS_MACH_OCTEON2): New machine flag. + +2009-11-18 Alan Modra + + * alloca-conf.h: Clarify comment. + +2009-11-06 Jonas Maebe + + Add DWARF attribute value for the "Borland fastcall" calling + convention. + * elf/dwarf2.h: Add DW_CC_GNU_borland_fastcall_i386 constant. + +2009-10-23 Kai Tietz + + * splay-tree.h (libi_uhostptr_t): Add gcc specific + __extension__ for long long type case to silent cX9. + (libi_shostptr_t): Likewise. + +2009-10-19 Rafael Avila de Espindola + + PR40790 + * plugin-api.h: Don't include stdint.h unconditionally. + +2009-10-15 Jakub Jelinek + + * include/dwarf2.h (DW_LANG_Python): Add comment that it is + a DWARF 4 addition. + +2009-10-14 Alan Modra + + * bfdlink.h (enum bfd_link_common_skip_ar_symbols): Rename from + bfd_link_common_skip_ar_aymbols. + (struct bfd_link_info): Here too. + +2009-10-09 Rafael Espindola + + * plugin-api.h (ld_plugin_add_input_library): Change argument name to + libname. + +2008-10-03 Rafael Espindola + + * plugin-api.h: New. + * lto-symtab.h: New. + +2009-10-05 Rafael Espindola + + * plugin-api.h (ld_plugin_status): Add LDPS_BAD_HANDLE. + (ld_plugin_get_input_file): New. + (ld_plugin_release_input_file): New. + (ld_plugin_add_input_library): New. + (ld_plugin_message): Mark format const. + (ld_plugin_level): Add LDPT_GET_INPUT_FILE, LDPT_RELEASE_INPUT_FILE and + LDPT_ADD_INPUT_LIBRARY. + (ld_plugin_tv): Add tv_get_input_file, tv_release_input_file and + tv_add_input_library. + +2009-10-04 Jerry Quinn + + * plugin-api.h: Fix compile. + +2009-09-29 Jason Merrill + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_LAMBDA, DEMANGLE_COMPONENT_DEFAULT_ARG, + DEMANGLE_COMPONENT_UNNAMED_TYPE. + (struct demangle_component): Add s_unary_num. + +2009-09-29 DJ Delorie + + * dis-asm.h: Add prototype for print_insn_rx. + +2009-09-25 Dodji Seketeli + + * dwarf2.h (enum dwarf_tag): Rename DW_TAG_template_parameter_pack and + DW_TAG_formal_parameter_pack into DW_TAG_GNU_template_parameter_pack + and DW_TAG_formal_parameter_pack until DWARF 5 is out. + +2009-09-25 Cary Coutant + + Add rest of new values from DWARF Version 4. + * dwarf2.h (DW_TAG_rvalue_reference_type, DW_TAG_template_alias): + New tags. + (DW_FORM_ref_sig8): New name for DW_FORM_sig8. + (DW_AT_main_subprogram, DW_AT_data_bit_offset, DW_AT_const_expr, + DW_AT_enum_class, DW_AT_linkage_name, DW_AT_GNU_guarded_by, + DW_AT_GNU_pt_guarded_by, DW_AT_GNU_guarded, DW_AT_GNU_pt_guarded, + DW_AT_GNU_locks_excluded, DW_AT_GNU_exclusive_locks_required, + DW_AT_GNU_shared_locks_required, DW_AT_GNU_odr_signature): New + attributes. + (DW_LANG_Python): New language. + +2009-09-24 Cary Coutant + + * dwarf2.h (DW_TAG_rvalue_reference_type, DW_TAG_template_alias): + New tags. + (DW_FORM_ref_sig8): New name for DW_FORM_sig8. + (DW_AT_main_subprogram, DW_AT_data_bit_offset, DW_AT_const_expr, + DW_AT_enum_class, DW_AT_linkage_name, DW_AT_GNU_guarded_by, + DW_AT_GNU_pt_guarded_by, DW_AT_GNU_guarded, DW_AT_GNU_pt_guarded, + DW_AT_GNU_locks_excluded, DW_AT_GNU_exclusive_locks_required, + DW_AT_GNU_shared_locks_required, DW_AT_GNU_odr_signature): New + attributes. + (DW_LANG_Python): New language. + +2009-09-22 Dodji Seketeli + + * dwarf2.h (enum dwarf_tag): Add + DW_TAG_template_parameter_pack and DW_TAG_formal_parameter_pack. + +2009-09-09 Martin Thuresson + + * bfdlink.h (struct bfd_link_hash_common_entry): Move to top + level. + +2009-09-04 Jie Zhang + + * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. + (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. + (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, + PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): + Adjust accordingly. + (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and + PseudoDbg_Assert_grp_mask. + +2009-08-06 Michael Eager + + * dis-asm.h: Decl print_insn_microblaze(). + +2009-07-24 Ian Lance Taylor + + * libiberty.h (crc32): Declare. + +2009-07-20 Cary Coutant + Doug Evans + + Add some dwarf4 values. + * dwarf2.h (enum dwarf_tag): Add DW_TAG_type_unit. + (enum dwarf_form): Add DW_FORM_sec_offset, DW_FORM_exprloc, + DW_FORM_flag_present, DW_FORM_sig8. + (enum dwarf_attribute): Add DW_AT_signature. + +2009-07-17 Jan Kratochvil + + * demangle.h + (enum demangle_component_type ) + (enum demangle_component_type ): + New. + +2009-07-10 Tom Tromey + + * dwarf2.h: New file, moved from elf/. + +2009-07-09 Jakub Jelinek + + * dwarf2.h (enum dwarf_location_atom): Add DW_OP_implicit_value + and DW_OP_stack_value. + +2009-07-09 Tom Tromey + + * elf/dwarf2.h: Remove, renaming to... + * dwarf2.h: ... this. + +2009-06-29 Tom Tromey + + * elf/dwarf2.h: New file. Merged with gdb. + +2009-06-18 Nick Clifton + + * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags + field of struct disassemble_info. + +2009-06-09 Ian Lance Taylor + + * ansidecl.h (ATTRIBUTE_UNUSED_LABEL): Define for C++. + +2009-06-15 Nick Clifton + + * dis-asm.h (DISASSEMBLE_DATA): New value for the flags field of + struct disassemble_info. + +2009-06-02 Ian Lance Taylor + + * ansidecl.h (EXPORTED_CONST): Define. + +2009-05-31 Ian Lance Taylor + + * ansidecl.h: Add extern "C" when compiling with C++. Treat C++ + the way we treat an ISO C compiler. Don't define inline as a + macdro when compiling with C++. + * dyn-string.h: Add header guard DYN_STRING_H. Add extern "C" + when compiling with C++. + * fibheap.h: Add extern "C" when compiling with C++. + +2009-05-25 Tristan Gingold + + * fopen-vms.h (FOPEN_RB, FOPEN_WB, FOPEN_AB, FOPEN_RUB, FOPEN_WUB, + FOPEN_AUB): Use "rfm=udf,rat=none" attribute. + +2009-04-22 Taras Glek + + * hashtab.h: Update GTY annotations to new syntax. + * splay-tree.h: Likewise. + +2009-04-08 H.J. Lu + + * bfdlink.h (bfd_link_info): Add warn_alternate_em. + +2009-03-18 Alan Modra + + * alloca-conf.h: Revise based on autoconf-2.61, autoconf-2.13 + documentation. + +2009-03-17 Jason Merrill + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_FUNCTION_PARAM. + +2008-12-01 Cary Coutant + + * plugin-api.h (LDPS_BAD_HANDLE): New constant. + (ld_plugin_get_input_file): New typedef. + (ld_plugin_release_input_file): New typedef. + (LDPT_GET_INPUT_FILE, LDPT_RELEASE_INPUT_FILE): New constants. + (struct ld_plugin_tv): Add two new fields. + +2008-12-23 Jon Beniston + + * dis-asm.h: Add LM32 disassembler function prototype. + +2008-12-10 Jason Merrill + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_FIXED_TYPE. + +2008-12-01 Cary Coutant + + * plugin-api.h (ld_plugin_message): Change format parameter to const. + +2008-12-01 Cary Coutant + + * plugin-api.h: Fix syntax error when compiling with C++. + +2008-11-26 Alan Modra + + PR 7047 + * bfdlink.h (struct bfd_elf_version_expr): Delete "symbol". + Add "literal". + +2008-11-21 Sterling Augustine + + * xtensa-isa-internal.h (XTENSA_STATE_IS_SHARED_OR): New flag. + * xtensa-isa.h (xtensa_state_is_shared_or): New prototype. + +2008-11-19 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_MUL16, XCHAL_HAVE_MUL32, XCHAL_HAVE_DIV32) + (XCHAL_HAVE_MINMAX, XCHAL_HAVE_SEXT, XCHAL_HAVE_THREADPTR) + (XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): Change to 1. + (XCHAL_NUM_AREGS): Change to 32. + (XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE): Change to 16K. + (XCHAL_ICACHE_LINESIZE, XCHAL_DCACHE_LINESIZE): Change to 32. + (XCHAL_ICACHE_LINEWIDTH, XCHAL_DCACHE_LINEWIDTH): Change to 5. + (XCHAL_DCACHE_IS_WRITEBACK): Change to 1. + (XCHAL_DEBUGLEVEL): Change to 6. + +2008-11-14 Tristan Gingold + + * fopen-vms.h (FOPEN_RB): Use a single string to match the + standard prototype. + (FOPEN_WB): Ditto. + (FOPEN_AB): Ditto. + (FOPEN_RUB): Ditto. + (FOPEN_WUB): Ditto. + (FOPEN_AUB): Ditto. + +2008-10-21 Alan Modra + + * obstack.h (obstack_finish ): Cast result to void *. + +2008-10-06 Jason Merrill + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_PACK_EXPANSION. + +2008-09-24 Richard Henderson + + * elf/dwarf2.h (DW_OP_GNU_encoded_addr): New. + +2008-09-22 Rafael Espindola + + * plugin-api.h (ld_plugin_status): Remove comma from the last item. + Use C style comment. + (ld_plugin_api_version, ld_plugin_output_file_type, + ld_plugin_symbol_kind, ld_plugin_symbol_visibility, + ld_plugin_symbol_resolution, ld_plugin_level, ld_plugin_tag): Remove + comma from the last item. + +2008-09-18 Cary Coutant + + Add plugin functionality for link-time optimization (LTO). + * plugin-api.h: New file. + +2008-09-09 Jason Merrill + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_DECLTYPE. + +2008-08-25 Alan Modra + + * binary-io.h: New file, imported from gnulib, but don't + #include or . + +2008-08-17 Alan Modra + + * bfdlink.h (bfd_generic_link_read_symbols): Declare. + +2008-08-08 Anatoly Sokolov + + * elf/avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31, + E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define. + (EF_AVR_MACH): Redefine to 0x7F. + * opcode/avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. + (AVR_ISA_AVR3): Redefine. + (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, + AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, + AVR_ISA_AVR6): Define. + +2008-07-12 Jie Zhang + + Revert + 2008-07-12 Jie Zhang + * bfdlink.h (struct bfd_link_info): Add sep_code member + variable. + * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. + (EF_BFIN_DATA_IN_L1): Define. + +2008-07-12 Jie Zhang + + * bfdlink.h (struct bfd_link_info): Add sep_code member + variable. + * elf/bfin.h (EF_BFIN_CODE_IN_L1): Define. + (EF_BFIN_DATA_IN_L1): Define. + +2008-07-07 Stan Shebs + + * dis-asm.h (struct disassemble_info): Add endian_code field. + +2008-07-07 Joel Brobecker + + * safe-ctype.h: Add #include of ctype.h before redefining + the ctype.h macros. + +2008-07-04 Joel Brobecker + + * safe-ctype.h: Remove #error when detecting that ctype.h has been + included. Redefine the various macros provided by ctype.h as + undefined variables. + +2008-06-23 Kaveh R. Ghazi + + * libiberty.h (XALLOCA, XDUP, XALLOCAVEC, XDUPVEC, XALLOCAVAR, + XDUPVAR, XOBNEWVEC, XOBNEWVAR): New. + +2008-06-06 Alan Modra + + * bfdlink.h (struct bfd_link_info): Add "path_separator". + +2008-04-10 Andreas Krebbel + + * dis-asm.h (print_s390_disassembler_options): + Prototype added. + +2008-03-24 Ian Lance Taylor + + * sha1.h: New file, from gnulib. + + * md5.h: Add extern "C" when compiled with C++. + +2008-03-24 Ian Lance Taylor + + * md5.h: Add extern "C" when compiled with C++. + +2008-03-21 Ian Lance Taylor + + * filenames.h: Add extern "C" when compiled with C++. + +2008-02-15 Alan Modra + + * bfdlink.h (struct bfd_link_hash_table): Delete creator field. + (struct bfd_link_info): Add output_bfd. + +2008-02-11 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_THREADPTR): Redefine to zero. + (XCHAL_NUM_AREGS, XCHAL_MAX_INSTRUCTION_SIZE): New. + +2008-01-26 David Daney + + * demangle.h (demangle_component_type): Add + DEMANGLE_COMPONENT_JAVA_RESOURCE, + DEMANGLE_COMPONENT_COMPOUND_NAME, and + DEMANGLE_COMPONENT_CHARACTER as new enum values. + (demangle_component): Add struct s_character to union u. + +2007-11-07 Joseph Myers + Daniel Jacobowitz + + * floatformat.h (struct floatformat): Add split_half field. + (floatformat_ibm_long_double): New. + +2007-09-06 Tom Tromey + + * libiberty.h (pex_free): Document process killing. + +2007-08-31 Douglas Gregor + + * demangle.h (enum demangle_component_type): Add + DEMANGLE_COMPONENT_RVALUE_REFERENCE. + +2007-07-25 Ben Elliston + + * ternary.h: Remove. + +2007-07-18 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_THREADPTR): New. + (XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): New. + +2007-07-17 Nick Clifton + + * COPYING3: New file. Contains version 3 of the GNU General + Public License. + +2007-07-12 Kai Tietz + + * splay-tree.h (libi_uhostptr_t, libi_shostptr_t): Adjust types + work-a-round whitespace problem in gcc gengtype. + + * splay-tree.h (libi_uhostptr_t, libi_shostptr_t): New types, + needed for WIN64 when a long is not wide enough for a pointer. + (splay_tree_key, splay_tree_value): Use the new types. + +2007-07-09 Roland McGrath + + * bfdlink.h (struct bfd_link_info): Add member emit_note_gnu_build_id. + +2007-07-06 Nick Clifton + + * bfdlink.h: Update copyright notice to refer to GPLv3. + +2007-06-29 M R Swami Reddy + + * dis-asm.h (print_insn_cr16): New prototype. + +2007-06-01 Noah Misch + Alan Modra + + * bfdlink.h (struct bfd_link_info): Add input_bfds_tail. + +2007-05-07 Nathan Froyd + + * libiberty.h (writeargv): Declare. + +2007-04-30 Alan Modra + + * bfdlink.h (struct bfd_link_info): Add "info" and "minfo". + +2007-04-25 Mark Mitchell + + * demangle.h: Change license to LGPL + exception. + +2007-04-10 Richard Henderson + + * bfdlink.h (struct bfd_link_info): Add relax_trip. + +2007-03-29 Joel Brobecker + + * filenames.h (FILENAME_CMP): Adjust define to call filename_cmp + regardless of the type of file system. + +2007-03-06 Jan Hubicka + + * ansidecl.h (ATTRIBUTE_COLD, ATTRIBUTE_HOT): New. + +2007-02-21 Nick Clifton + + * bfdlink.h (struct bfd_link_callbacks): Add + override_segment_assignment field. + +2007-02-17 Mark Mitchell + Nathan Sidwell + Vladimir Prus + + * bin-bugs.h: Remove. + +2007-02-09 Joseph S. Myers + + * libiberty.h (pex_write_input): Remove prototype. + +2007-02-05 Dave Brolley + + * Contribute the following changes: + 2001-03-26 Ben Elliston + + * dis-asm.h (print_insn_mep): Declare. + +2007-02-02 H.J. Lu + + * dis-asm.h (print_i386_disassembler_options): New. + +2007-01-31 Vladimir Prus + + * libiberty.h (PEX_STDERR_TO_PIPE): New define. + (PEX_BINARY_ERROR): New define. + (pex_read_err): New function. + +2007-01-29 Simon Baldwin + + * demangle.h: New cplus_demangle_print_callback, + cplus_demangle_v3_callback, and java_demangle_v3_callback function + prototypes, and demangle_callbackref type definition. + +2007-01-16 H.J. Lu + + PR ld/3831 + * bfdlink.h (bfd_link_info): Rename dynamic to dynamic_list. + Add dynamic and dynamic_data. + +2006-12-05 Michael Tautschnig + Nick Clifton + + * ansidecl.h (ATTRIBUTE_PACKED): Define. + +2006-11-30 Andrew Stubbs + J"orn Rennecke + + PR driver/29931 + * libiberty.h (make_relative_prefix_ignore_links): Declare. + +2006-11-27 Bob Wilson + + * xtensa-config.h (XSHAL_ABI): New. + (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New. + +2006-11-27 Bob Wilson + + * xtensa-isa.h (STATIC_LIBISA): Delete. + +2006-10-30 Paul Brook + + * dis-asm.h (disassemble_info): Add symtab, symtab_pos and + symtab_size. + +2006-10-30 H.J. Lu + + PR ld/3111 + * bfdlink.h (bfd_link_info): Add reduce_memory_overheads. + +2006-10-25 Trevor Smigiel + Yukishige Shibata + Nobuhisa Fujinami + Takeaki Fukuoka + Alan Modra + + * dis-asm.h (print_insn_spu): Declare. + +2006-09-17 Mei Ligang + + * dis-asm.h: Add prototypes for Score disassembler routines. + +2006-09-07 H.J. Lu + + * bfdlink.h (bfd_elf_dynamic_list): New. + (bfd_link_info): Add a dynamic field. + +2006-08-04 Marcelo Tosatti + + * bfdlink.h (struct bfd_link_info): New field: print_gc_sections. + +2006-07-10 Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add emit_hash and + emit_gnu_hash bitfields. + +2006-04-11 Jim Blandy + + * libiberty.h (pex_input_file, pex_input_pipe): New declarations. + +2006-04-06 H.J. Lu + + * bfdlink.h (bfd_link_info): Replace need_relax_finalize with + relax_pass. + +2006-02-17 Shrirang Khisti + Anil Paranjape + Shilin Shakti + + * dis-asm.h (print_insn_xc16c): New prototype. + +2006-01-18 DJ Delorie + + * md5.h: Include ansidecl.h + +2006-01-17 Andreas Schwab + + PR binutils/1486 + * dis-asm.h (struct disassemble_info): Add + disassembler_needs_relocs. + +2006-01-09 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_MUL32_HIGH): Define. + +2005-12-30 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_WIDE_BRANCHES): New. + +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * dis-asm.h (print_insn_mt): Renamed. + +2005-12-10 Terry Laurenzo + + PR java/9861 + * demangle.h : Add DMGL_RET_POSTFIX define to enable alternative + output format for return types + +2005-11-03 Alan Modra + + * bfdlink.h (struct bfd_link_order): Tweak comment. + +2005-10-31 Mark Kettenis + + * floatformat.h (enum floatformat_byteorders): Add + floatformat_vax. + (floatformat_vax_aingle, floatformat_vax_double): Declare. + +2005-10-28 Dave Brolley + + Contribute the following changes: + 2003-09-29 Dave Brolley + + * dis-asm.h (disassemble_info): insn_sets now (void *) to allow for + more exotic underlying types to be used. + +2005-10-25 Arnold Metselaar + + disasm.h: Add declaration for print_insn_z80 + +2005-09-30 Catherine Moore + + * dis-asm.h (print_insn_bfin): Declare. + +2005-09-26 Mark Mitchell + + * libiberty.h (expandargv): New function. + +2005-08-18 Alan Modra + + * bfdlink.h: Remove mention of a29k. + * dis-asm.h: Remove a29k support. + +2005-08-17 Mark Kettenis + + * floatformat.h (struct floatformat): Change type of large + argument for is_valid member to `const void *'. + (floatformat_to_double): Change type of second argument to `const + void *'. + (floatformat_from_double): Change type of last argument to `void + *'. + (floatformat_is_valid): Change type of last argument to `const + void *'. + +2005-07-14 Jim Blandy + + * dis-asm.h (print_insn_m32c): New declaration. + +2005-07-12 Ben Elliston + + * xregex2.h (regexec): Qualify this prototype with __extension__ + when compiling with GNU C. + +2005-07-07 Kaveh R. Ghazi + + * dis-asm.h (fprintf_ftype): Add format attribute. + +2005-07-03 Steve Ellcey + + PR other/13906 + * ansidecl.h (ATTRIBUTE_ALIGNED_ALIGNOF): New. + * md5.h (md5_uintptr): New. + (md5_ctx): Align buffer field. + +2005-06-30 Daniel Berlin + + * hashtab.h (HTAB_DELETED_ENTRY): New macro. + (HTAB_EMPTY_ENTRY): New macro. + +2005-06-20 Geoffrey Keating + + * libiberty.h (strverscmp): Prototype. + +2005-06-17 Jakub Jelinek + + * elf/external.h (GRP_ENTRY_SIZE): Define. + +2005-06-08 Zack Weinberg + + * dis-asm.h (get_arm_regnames): Update prototype. + +2005-06-07 Aldy Hernandez + Michael Snyder + Stan Cox + + * dis-asm.h: Externalize print_insn_ms1. + +2005-06-06 Gabriel Dos Reis + + * libiberty.h (XOBFINISH): New. + +2005-06-03 Alan Modra + + * bfdlink.h (struct bfd_link_callbacks): Add einfo. + +2005-06-01 Kaveh R. Ghazi + + * libiberty.h (vsnprintf): Add format attribute. + +2005-05-29 Kaveh R. Ghazi + + * ansidecl.h: Add ATTRIBUTE_FPTR_PRINTF. + +2005-05-28 Eli Zaretskii + + * libiberty.h: (snprintf) [!HAVE_DECL_SNPRINTF]: Declare if + needed. + (vsnprintf) [!HAVE_DECL_VSNPRINTF]: Declare if needed. + +2005-05-25 Richard Henderson + + * demangle.h (DEMANGLE_COMPONENT_HIDDEN_ALIAS): New. + +2005-05-24 Gabriel Dos Reis + + * libiberty.h (ACONCAT): Properly cast value of alloca(). + + * ansidecl.h (ATTRIBUTE_UNUSED_LABEL): Don't define if + __cplusplus. + +2005-05-12 Steve Ellcey + + libiberty.h: Do not define empty basename prototype. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + COPYING, ansidecl.h, bfdlink.h, bout.h, demangle.h, dis-asm.h, + dyn-string.h, fibheap.h, filenames.h, floatformat.h, + fnmatch.h, gdbm.h, getopt.h, hashtab.h, hp-symtab.h, ieee.h, + libiberty.h, md5.h, oasys.h, objalloc.h, obstack.h, os9k.h, + partition.h, progress.h, safe-ctype.h, sort.h, splay-tree.h, + symcat.h, ternary.h, xregex2.h, xtensa-config.h, + xtensa-isa-internal.h, xtensa-isa.h + +2005-04-25 Kaveh R. Ghazi + + * libiberty.h (unlock_std_streams): New. + +2005-04-19 Kaveh R. Ghazi + + * hashtab.h, libiberty.h, objalloc.h, splay-tree.h, ternary.h: + Don't use the PTR macro. + + * sort.h: Don't use the PARAMS macro. + +2005-04-16 Kaveh R. Ghazi + + * libiberty.h (unlock_stream): New. + +2005-04-13 Kaveh R. Ghazi + + * libiberty.h (fopen_unlocked, fdopen_unlocked, freopen_unlocked): + Remove parameter names. + +2005-04-11 Kaveh R. Ghazi + + * libiberty.h (fopen_unlocked, fdopen_unlocked, freopen_unlocked): + Provide prototypes for new functions. + +2005-03-29 Ian Lance Taylor + + * libiberty.h: Fix indentation. + +2005-03-28 Ian Lance Taylor + + * libiberty.h: Include . + (PEX_RECORD_TIMES, PEX_USE_PIPES, PEX_SAVE_TEMPS): Define. + (PEX_LAST, PEX_SEARCH, PEX_SUFFIX, PEX_STDERR_TO_STDOUT): Define. + (PEX_BINARY_INPUT, PEX_BINARY_OUTPUT): Define. + (pex_init, pex_run, pex_read_output): Declare. + (pex_get_status, pex_get_times, pex_free, pex_one): Declare. + (struct pex_time): Define. + +2005-03-28 Mark Mitchell + + * libiberty.h (ffs): Declare, if necessary. + +2005-03-27 Gabriel Dos Reis + + * ternary.h: Don't use PARAMS anymore. + +2005-03-27 Gabriel Dos Reis + + * md5.h: Remove definition and uses of __P. + * dyn-string.h: Remove uses of PARAMS. + * fibheap.h: Likewise. + * floatformat.h: Likewise. + * hashtab.h: Likewise. + +2005-03-26 Gabriel Dos Reis + + * demangle.h: Remove uses of PARAMS. + + * libiberty.h (ANSI_PROTOTYPES): Remove guard since + ANSI_PROTOTYPES is always assumed. + Remove uses of PARAMS throughout. + +2005-03-24 Kaveh R. Ghazi + + * libiberty.h (xstrndup): Declare. + +2005-03-22 Kaveh R. Ghazi + + * libiberty.h (make_relative_prefix): Add ATTRIBUTE_MALLOC. + +2005-03-22 Bob Wilson + + * xtensa-isa.h: Update a comment and whitespace. + +2005-03-16 H.J. Lu + + * bfdlink.h (bfd_link_info): Add gc_sections. + +2005-03-09 Mark Mitchell + + * libiberty.h (gettimeofday): Declare. + +2005-03-01 Jan Beulich + + * libiberty.h: Declare unlink_if_ordinary. + +2005-02-21 Alan Modra + + * xtensa-isa-internal.h (xtensa_length_decode_fn): Warning fix. + * xtensa-isa.h (xtensa_insnbuf_to_chars): Likewise. + (xtensa_insnbuf_from_chars, xtensa_isa_length_from_chars): Likewise. + +2005-02-14 Paolo Bonzini + + PR bootstrap/19818 + * ansidecl.h (PARAMS): Guard from redefinition. + +2005-02-03 Alan Modra + + * bfdlink.h (struct bfd_link_hash_entry): Add u.undef.weak. + +2005-02-01 Alan Modra + + * bfdlink.h (bfd_link_repair_undef_list): Declare. + +2005-01-10 Andreas Schwab + + * dis-asm.h (struct disassemble_info): Add skip_zeroes and + skip_zeroes_at_end. + +2004-12-11 Ben Elliston + + * fibheap.h (struct fibnode): Only use unsigned long bitfields + when __GNUC__ is defined and ints are less than 32-bits wide. + +2004-11-04 Paul Brook + + * bfdlink.h (bfd_link_info): Add default_imported_symver. + +2004-11-12 Bob Wilson + + * xtensa-isa-internal.h (xtensa_interface_internal): Add class_id. + * xtensa-isa.h (xtensa_interface_class_id): New prototype. + +2004-11-08 Inderpreet Singh + Vineet Sharma + + * dis-asm.h: Add prototype for print_insn_maxq_little. + +2004-10-26 Paul Brook + + * bfdlink.h (struct bfd_link_info): Add create_default_symver. + +2004-10-21 H.J. Lu + + PR 463 + * bfdlink.h (bfd_link_callbacks): Add a pointer to struct + bfd_link_hash_entry to reloc_overflow. + +2004-10-07 Bob Wilson + + * xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS, + XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New. + (XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete. + + * xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete. + (config_sturct struct): Delete. + (XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE, + XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN, + XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP, + XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL, + XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define. + (xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New. + (xtensa_insn_decode_fn): Rename to ... + (xtensa_opcode_decode_fn): ... this. + (xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn, + xtensa_undo_reloc_fn): Update. + (xtensa_encoding_template_fn): Delete. + (xtensa_opcode_encode_fn, xtensa_format_decode_fn, + xtensa_length_decode_fn): New. + (xtensa_format_internal, xtensa_slot_internal): New types. + (xtensa_operand_internal): Delete operand_kind, inout, isPCRelative, + get_field, and set_field fields. Add name, field_id, regfile, + num_regs, and flags fields. + (xtensa_arg_internal): New type. + (xtensa_iclass_internal): Change operands field to array of + xtensa_arg_internal. Add num_stateOperands, stateOperands, + num_interfaceOperands, and interfaceOperands fields. + (xtensa_opcode_internal): Delete length, template, and iclass fields. + Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses. + (opname_lookup_entry): Delete. + (xtensa_regfile_internal, xtensa_interface_internal, + xtensa_funcUnit_internal, xtensa_state_internal, + xtensa_sysreg_internal, xtensa_lookup_entry): New. + (xtensa_isa_internal): Replace opcode_table field with opcodes field. + Change type of opname_lookup_table. Delete num_modules, + module_opcode_base, module_decode_fn, config, and has_density fields. + Add num_formats, formats, format_decode_fn, length_decode_fn, + num_slots, slots, num_fields, num_operands, operands, num_iclasses, + iclasses, num_regfiles, regfiles, num_states, states, + state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table, + max_sysreg_num, sysreg_table, num_interfaces, interfaces, + interface_lookup_table, num_funcUnits, funcUnits and + funcUnit_lookup_table fields. + (xtensa_isa_module, xtensa_isa_modules): Delete. + (xtensa_isa_name_compare): New prototype. + (xtisa_errno, xtisa_error_msg): New. + * xtensa-isa.h (XTENSA_ISA_VERSION): Define. + (xtensa_isa): Change type. + (xtensa_operand): Delete. + (xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg, + xtensa_interface, xtensa_funcUnit, xtensa_isa_status, + xtensa_funcUnit_use): New types. + (libisa_module_specifier): Delete. + (xtensa_isa_errno, xtensa_isa_error_msg): New prototypes. + (xtensa_insnbuf_free, xtensa_insnbuf_to_chars, + xtensa_insnbuf_from_chars): Update prototypes. + (xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa, + xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn, + xtensa_encode_insn, xtensa_insn_length, + xtensa_insn_length_from_first_byte, xtensa_num_operands, + xtensa_operand_kind, xtensa_encode_result, + xtensa_operand_isPCRelative): Delete. + (xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field, + xtensa_operand_set_field, xtensa_operand_encode, + xtensa_operand_decode, xtensa_operand_do_reloc, + xtensa_operand_undo_reloc): Update prototypes. + (xtensa_isa_maxlength, xtensa_isa_length_from_chars, + xtensa_isa_num_pipe_stages, xtensa_isa_num_formats, + xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states, + xtensa_isa_num_sysregs, xtensa_isa_num_interfaces, + xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup, + xtensa_format_decode, xtensa_format_encode, xtensa_format_length, + xtensa_format_num_slots, xtensa_format_slot_nop_opcode, + xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode, + xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump, + xtensa_opcode_is_loop, xtensa_opcode_is_call, + xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands, + xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses, + xtensa_opcode_funcUnit_use, xtensa_operand_name, + xtensa_operand_is_visible, xtensa_operand_is_register, + xtensa_operand_regfile, xtensa_operand_num_regs, + xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative, + xtensa_stateOperand_state, xtensa_stateOperand_inout, + xtensa_interfaceOperand_interface, xtensa_regfile_lookup, + xtensa_regfile_lookup_shortname, xtensa_regfile_name, + xtensa_regfile_shortname, xtensa_regfile_view_parent, + xtensa_regfile_num_bits, xtensa_regfile_num_entries, + xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits, + xtensa_state_is_exported, xtensa_sysreg_lookup, + xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number, + xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name, + xtensa_interface_num_bits, xtensa_interface_inout, + xtensa_interface_has_side_effect, xtensa_funcUnit_lookup, + xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes. +2004-10-07 Jeff Baker + + * bfdlink.h (bfd_link_info): Add bitfield: warn_shared_textrel. + +2004-09-17 Alan Modra + + * bfdlink.h (struct bfd_link_hash_entry): Move und_next into elements + of union. + +2004-09-13 Aaron W. LaFramboise + + * libiberty.h (basename): Prototype for __MINGW32__. + +2004-09-04 Kaveh R. Ghazi + + * ansidecl.h (ATTRIBUTE_SENTINEL): Define. + * libiberty.h (concat, reconcat, concat_length, concat_copy, + concat_copy2): Use ATTRIBUTE_SENTINEL. + +2004-08-13 Alan Modra + + * bfdlink.h (struct bfd_link_callbacks): Remove "error_handler". + (LD_DEFINITION_IN_DISCARDED_SECTION): Delete. + +2004-08-02 Gabriel Dos Reis + + * libiberty.h (XDELETE, XDELETEVEC, XRESIZEVEC): Remove any + const-qualification before disposal. + +2004-07-24 Bernardo Innocenti + + * ansidecl.h (ARG_UNUSED): New Macro. + +2004-07-23 H.J. Lu + + * bin-bugs.h (REPORT_BUGS_TO): Set to + "". + +2004-07-21 Paolo Bonzini + + * ansidecl.h (ATTRIBUTE_PURE): New. + +2004-07-13 Bernardo Innocenti + + * libiberty.h (XNEW, XCNEW, XNEWVEC, XCNEWVEC, XOBNEW): Move here from + libcpp/internal.h. + (XDELETE, XRESIZEVEC, XDELETEVEC, XNEWVAR, XCNEWVAR, XRESIZEVAR): New + macros. + +2004-07-13 Bernardo Innocenti + + * libiberty.h (ASTRDUP): Add casts required for stricter + type conversion rules of C++. + * obstack.h (obstack_free): Likewise. + +2004-07-07 Tomer Levi + + * dis-asm.h (print_insn_crx): Declare. + +2004-06-24 Alan Modra + + * bfdlink.h (struct bfd_link_order): Update comment. + +2004-05-11 Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add relro, relro_start and + relro_end fields. + +2004-05-04 Andreas Jaeger + + * demangle.h: Do not use C++ reserved keyword typename as + parameter for cplus_demangle_fill_builtin_type. + +2004-04-22 Richard Henderson + + * hashtab.h (struct htab): Add size_prime_index. + +2004-04-13 Jeff Law + + * hashtab.h (htab_remove_elt_with_hash): Prototype new function. + +2004-03-30 Zack Weinberg + + * hashtab.h, splay-tree.h: Use new shorter form of GTY markers. + +2004-03-25 Stan Shebs + + * mpw/: Remove subdirectory and everything in it. + +2004-03-23 Alan Modra + + PR 51. + * bfdlink.h (struct bfd_link_info): Add wrap_char. + +2004-03-20 H.J. Lu + + * bfdlink.h (bfd_link_info): Correct comments for the + unresolved_syms_in_objects field. + +2004-02-24 Ian Lance Taylor + + * dyn-string.h: Update copyright date. + +2004-02-23 Ian Lance Taylor + + * dyn-string.h: Remove test of IN_LIBGCC2 and IN_GLIBCPP_V3 and + the associated #defines. + +2004-01-12 Ian Lance Taylor + + * demangle.h: Instead of checking ANSI_PROTOTYPES, just include + "libiberty.h". + + * demangle.h: If ANSI_PROTOTYPES is defined, include . + + * demangle.h (enum demangle_component_type): Define. + (struct demangle_operator_info): Declare. + (struct demangle_builtin_type_info): Declare. + (struct demangle_component): Define. + (cplus_demangle_fill_component): Declare. + (cplus_demangle_fill_name): Declare. + (cplus_demangle_fill_builtin_type): Declare. + (cplus_demangle_fill_operator): Declare. + (cplus_demangle_fill_extended_operator): Declare. + (cplus_demangle_fill_ctor, cplus_demangle_fill_dtor): Declare. + (cplus_demangle_v3_components): Declare. + (cplus_demangle_print): Declare. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/ChangeLog-9103 b/external/gpl3/gdb/dist/include/ChangeLog-9103 new file mode 100644 index 000000000000..3eeb77c1bbaa --- /dev/null +++ b/external/gpl3/gdb/dist/include/ChangeLog-9103 @@ -0,0 +1,2682 @@ +2003-12-19 Andreas Tobler + + * include/fibheap.h (fibnode): Use __extension__ for + bit-fields mark and degree if __GNUC__. + +2003-12-18 Kazu Hirata + + * include/fibheap.h (fibnode): Use unsigned long int for + bit-fields if __GNUC__ is defined. + +2003-12-19 Andreas Tobler + + * fibheap.h (fibnode): Use __extension__ for + bit-fields mark and degree if __GNUC__. + +2003-12-18 Kazu Hirata + + * fibheap.h (fibnode): Use unsigned long int for + bit-fields if __GNUC__ is defined. + +2003-12-04 H.J. Lu + + * bfdlink.h (bfd_link_info): Change relax_finalizing to + need_relax_finalize. + +2003-12-03 Alan Modra + + * bfdlink.h (struct bfd_link_hash_entry): Rename "next" to "und_next". + +2003-12-02 Alan Modra + + * bfdlink.h (struct bfd_link_info): Remove mpc860c0 field. + +2003-11-14 Nick Clifton + + * dis-asm.h (struct disassemble_info): Add new field + 'symbol_is_valid' which is a function which can tell the + disassembler to skip certain symbols as they should not be + displayed to the user. + (arm_symbol_is_valid): New prototype. This is the ARM + specific function for the symbol_is_valid field. + (generic_symbol_is_valid): New prototype. This is the default + function pointed to by the symbol_is_valid field. + +2003-11-06 Bruno Rohee + + * hp-symtab.h: Fix "the the" typo. + +2003-10-24 H.J. Lu + + * bfdlink.h (bfd_elf_version_expr): Add "symbol" and remove + "wildcard". + +2003-10-22 Joseph S. Myers + + * obstack.h: Merge the following change from gnulib: + 2003-10-21 Paul Eggert + * obstack.h (obstack_1grow_fast): Properly parenthesize arg. + (obstack_ptr_grow_fast, obstack_int_grow_fast): + Don't use lvalue casts, as GCC plans to remove support for them + in GCC 3.5. Reported by Joseph S. Myers. This bug + was also present in the non-GCC version, indicating that this + code had always been buggy and had never been widely used. + (obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank): + Use the fast variant of each macro, rather than copying the + definiens of the fast variant; that way, we'll be more likely to + catch future bugs in the fast variants. + +2003-10-22 Jakub Jelinek + + * bfdlink.h (struct bfd_elf_version_expr): Remove match field. + Add wildcard and mask fields. + (BFD_ELF_VERSION_C_TYPE): Define. + (BFD_ELF_VERSION_CXX_TYPE): Likewise. + (BFD_ELF_VERSION_JAVA_TYPE): Likewise. + (struct bfd_elf_version_expr_head): New. + (struct bfd_elf_version_tree): Add match field. + Change type of globals and locals fields + to struct bfd_elf_version_expr_head. + +2003-09-22 Andrew Cagney + + * floatformat.h (struct floatformat): Add field "is_valid". + +2003-09-15 Andrew Cagney + + * floatformat.h (floatformat_to_double): Make input buffer constant. + (floatformat_from_double, floatformat_is_valid): Ditto. + +2003-09-15 Andrew Cagney + + * floatformat.h (struct floatformat): Make "exp_bias" signed. + +2003-09-15 Daniel Jacobowitz + + * floatformat.h (floatformat_is_valid): Add prototype. + +2003-08-27 Andrew Cagney + + * dis-asm.h (init_disassemble_info): Declare. + (INIT_DISASSEMBLE_INFO): Redefine as a call to + init_disassemble_info. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Ditto. + +2003-08-20 Nick Clifton + + * bfdlink.h (enum report_method): New enum. Describes how to + report something. + (struct bfd_link_info): Delete fields 'no_undefined' and + 'allow_shlib_undefined'. Replace with + 'unresolved_symbols_in_objects' and + 'unresolved_symbols_in_shared_libs'. + +2003-08-07 Alan Modra + + * bfdlink.h: Remove PARAMS macro. Replace PTR with void *. + * dis-asm.h: Likewise. + +2003-07-09 Bob Wilson + + * xtensa-config.h: Undef all macros before defining them. + +2003-07-06 H.J. Lu + + * demangle.h: Support C++. + +2003-07-01 Zack Weinberg + + * filenames.h: New file imported from binutils. + +2003-06-30 Bob Wilson + + * xtensa-config.h: New file imported from binutils. + +2003-06-30 Bob Wilson + + * xtensa-config.h (XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, + XCHAL_HAVE_ADDX, XCHAL_HAVE_L32R): Define. + +2003-06-25 Alan Modra + + * bfdlink.h: Correct spelling of "relocatable". + +2003-06-22 Zack Weinberg + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to + HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC + respectively. + +2003-06-21 Zack Weinberg + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET): + New #defines. + +2003-06-17 Kaveh R. Ghazi + + * ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support. + +2003-05-23 Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add execstack and noexecstack. + +2003-06-03 H.J. Lu + + * bfdlink.h (LD_DEFINITION_IN_DISCARDED_SECTION): New. + +2003-05-30 Ulrich Drepper + Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add pie and executable + bits. + +2003-05-21 Nick Clifton + + * bfdlink.h (struct bfd_link_hash_table): Fix typo in comment. + +2003-05-15 Jim Blandy + + * libiberty.h (hex_value): Make the value an unsigned int, to + avoid unexpected sign-extension when cast to unsigned types larger + than int --- like bfd_vma, on some platforms. + (_hex_value): Update declaration. + +2003-05-09 Alan Modra + + * xtensa-isa-internal.h (xtensa_isa_module_struct): Remove const on + gen_num_opcodes_fn return type. + +2003-05-07 Jason Merrill + + * hashtab.h (iterative_hash): Prototype. + (iterative_hash_object): New macro. + +2003-04-28 H.J. Lu + + * bfdlink.h (bfd_link_info): Add relax_finalizing. + +2003-04-23 H.J. Lu + + * bfdlink.h (bfd_link_callbacks): Add error_handler. + +2003-04-02 Bob Wilson + + * xtensa-config.h: Remove comment indicating that this is a + generated file. + +2003-04-01 Bob Wilson + + * dis-asm.h (print_insn_xtensa): Declare. + * xtensa-config.h: New file. + * xtensa-isa-internal.h: Likewise. + * xtensa-isa.h: Likewise. + +2003-03-17 Kaveh R. Ghazi + + * ansidecl.h (ATTRIBUTE_NONNULL, ATTRIBUTE_NULL_PRINTF, + ATTRIBUTE_NULL_PRINTF_1, ATTRIBUTE_NULL_PRINTF_2, + ATTRIBUTE_NULL_PRINTF_3, ATTRIBUTE_NULL_PRINTF_4, + ATTRIBUTE_NULL_PRINTF_5): New. + (ATTRIBUTE_PRINTF): Add ATTRIBUTE_NONNULL. + +2003-03-17 Jan Hubicka + + * hashtab.h (htab_traverse_noresize): Declare. + +2003-02-27 Kaveh R. Ghazi + + * libiberty.h: Document return value of physmem routines. + +2003-02-20 Kaveh R. Ghazi + + * libiberty.h (physmem_total, physmem_available): Prototype. + +2003-02-20 Daniel Jacobowitz + + * libiberty.h (lrealpath): Add declaration. + +2003-01-31 Grant Grundler + + * hppa.h (ldwa, ldda): Add ordered opcodes. + +2003-01-26 Daniel Jacobowitz + + * hashtab.h (htab_alloc_with_arg, htab_free_with_arg): Add new types. + (struct htab): Add alloc_arg, alloc_with_arg_f, free_with_arg_f. + (htab_create_alloc_ex): New prototype. + (htab_set_functions_ex): New prototype. + +2002-07-17 Geoffrey Keating + + * splay-tree.h (GTY): Define if undefined. + (splay_tree_allocate_fn): Return PTR for compatibility, not void *. + (struct splay_tree_node_s): Support gengtype. + (struct splay_tree_s): Likewise. Make allocate_data a PTR, + not a void *. + +2002-01-02 Ben Elliston + + * dis-asm.h (print_insn_iq2000): Declare. + +2002-12-24 Dmitry Diky + + * dis-asm.h: Add msp430 disassembler prototype. + +2002-12-27 Chris Demetriou + + * dis-asm.h (print_mips_disassembler_options): Prototype. + +2002-12-23 Alan Modra + + * bfdlink.h (struct bfd_link_info): Add "strip_discarded". + +2002-12-20 Alan Modra + + * bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with + bit-fields. Rearrange to put all like types together. + +2002-11-30 Alan Modra + + * bfdlink.h: Replace boolean with bfd_boolean. Formatting. + +2002-11-23 Simon Burge + + * libiberty.h (basename): Add NetBSD to the list. + +2002-11-22 Daniel Jacobowitz + + * libiberty.h (make_relative_prefix): Add prototype. + +2002-11-14 Egor Duda + + * bfdlink.h (struct bfd_link_info): Add new boolean + field pei386_runtime_pseudo_reloc. + +2002-10-26 Roger Sayle + + * partition.h: Close the extern "C" scope when compiling with C++. + +2002-10-26 Roger Sayle + DJ Delorie + + PR bootstrap/8351 + * getopt.h: Avoid prototyping getopt with no arguments in C++. + +2002-10-24 Nathan Tallent + + * ansidecl.h (__STDC__): Add (__alpha && __cplusplus) to the + list of platform compilers that may look, smell and act + like __STDC__ but that may not define it. + +2002-10-11 David O'Brien + + * getopt.h: getopt is in unistd.h (based on SUSv2). + +2002-09-26 Andrew Cagney + + * regs/: Delete directory. + +2002-09-19 Alexandre Oliva + + * libiberty.h (asprintf, vasprintf): Don't declare them if the + corresponding HAVE_DECL_ macro is 1. + +2002-09-19 Nathan Tallent + + * dis-asm.h: Remove (errant) trailing semicolon (;) from the + extern "C" { } declaration. + +2002-09-04 Nick Clifton + + * dis-asm.h (print_ppc_disassembler_options): Prototype. + +2002-08-28 Michael Hayes + + * dis-asm.h: Add standard disassembler for tic4x. + +2002-08-07 H.J. Lu + + * bfdlink.h (bfd_link_info): Add allow_undefined_version. + (bfd_elf_version_expr): Add symver and script. + +2002-07-31 Ian Dall + + * bfdlink.h (bfd_link_common_skip_ar_symbols): New enum. + (struct bfd_link_info): Add new field 'common_skip_ar_symbols'. + +2002-07-19 Denis Chertykov + Matthew Green + + * dis-asm.h (print_insn_ip2k): Declare. + +2002-07-01 Alan Modra + + * bfdlink.h (struct bfd_sym_chain): Declare. + (struct bfd_link_info): Add gc_sym_list. Formatting fixes. + +2002-06-25 Alan Modra + + * demangle.h: #include "ansidecl.h" rather than #include . + * fibheap.h: Likewise. + * hashtab.h: Likewise. + * partition.h: Likewise. + * sort.h: Likewise. + * splay-tree.h: Likewise. + +2002-06-24 Alan Modra + + * libiberty.h (basename): Don't declare if HAVE_DECL_BASENAME. + * getopt.h (getopt): Don't declare if HAVE_DECL_GETOPT. + +2002-06-18 Dave Brolley + + From Catherine Moore: + * dis-asm.h (print_insn_frv): New prototype. + +2002-06-09 Andrew Cagney + + * remote-sim.h: Move to directory gdb/. + * callback.h: Move to directory gdb/. + +2002-06-07 Charles Wilson + + * bfdlink.h (struct bfd_link_info): Change type of + pei386_auto_import field to int so that -1 can mean enabled by + default and 1 can mean enabled by command line switch. + +2002-06-06 DJ Delorie + + * hashtab.h (htab): Rearrange new members for backward + compatibility. + (htab_create): Don't use a macro that requires other headers. + +2002-06-05 Geoffrey Keating + + * hashtab.h (htab_create): Restore prototype for backward + compatibility. + (htab_try_create): Likewise. + +2002-05-22 Geoffrey Keating + + * hashtab.h (struct htab): Update for change to length specifier. + +2002-05-10 Geoffrey Keating + + * hashtab.h (GTY): Define if undefined. + (htab_alloc): New typedef. + (htab_free): New typedef. + (struct htab): Support gengtype; allow user-specified memory + allocation. + (htab_create_alloc): New. + (htab_create): Replace with #define. + (htab_try_create): Delete. + +2002-05-28 Kuang Hwa Lin + + * dis-asm.h: Prototype print_insn_dlx. + +2002-05-23 Andrew Cagney + + * sim-d10v.h: Delete file. Moved to include/gdb/. + +2002-05-21 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add allow_multiple_definition. + +2002-05-17 J"orn Rennecke + + * dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype. + +2002-04-16 David S. Miller + + * xregex2.h (__restrict_arr): Define to __restrict on GCC + 3.1 and later. Do not redefine. + +2002-04-01 Phil Edwards + + * dyn-string.h: Also allow IN_GLIBCPP_V3 to redefine names. + +2002-03-10 Daniel Jacobowitz + + * gdb: New directory. + +2002-03-06 Andrew Cagney + + * floatformat.h (floatformat_arm_ext): Delete declaration. + +2002-02-21 Jim Blandy + + Allow the user to specify functions for allocating memory for + splay tree roots and nodes. + * splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn): + New types. + (splay_tree): New fields: `allocate', `deallocate', and + `allocate_data'. + (splay_tree_new_with_allocator): New function declaration. + +2002-02-15 Alan Modra + + Support arbitrary length fill patterns. + * bfdlink.h (enum bfd_link_order_type): Remove bfd_fill_link_order. + (struct bfd_link_order): Remove fill. Add data.size. + +2002-02-08 Alexandre Oliva + + Contribute sh64-elf. + 2000-11-25 Hans-Peter Nilsson + * dis-asm.h (print_insn_sh64): New prototype. + (print_insn_sh64l): New prototype. + (print_insn_sh64x_media): New prototype. + +2002-02-05 Frank Ch. Eigler + + * dis-asm.h (disassemble_info): New field `insn_sets'. + (INIT_DISASSEMBLE_INFO): Clear it. + +2002-02-05 Jason Merrill + + * demangle.h (cplus_demangle_v3): Add "options" parm. + (cplus_demangle_v3_type): Remove prototype. + (DMGL_VERBOSE): New macro. + (DMGL_TYPES): New macro. + +2002-02-02 H.J. Lu (hjl@gnu.org) + + * demangle.h (cplus_demangle_v3_type): New prototype. + +2002-01-31 Ivan Guzvinec + + * dis-asm.h : Add support for or32 targets + +2002-01-28 Kaveh R. Ghazi + + * libiberty.h (C_alloca): Add ATTRIBUTE_MALLOC. + +2002-01-27 David O'Brien + + * cgen.h (BFD_VERSION): Use BFD_VERSION_DATE instead. + +2001-12-14 Nick Clifton + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise the + disassembler_options field (to NULL). + +2001-12-13 Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add eh_frame_hdr field. + +2001-12-07 Geoffrey Keating + + * dis-asm.h (print_insn_xstormy16): Declare. + +2001-12-06 Richard Henderson + + * demangle.h (no_demangling): New. + (NO_DEMANGLING_STYLE_STRING): New. + +2001-11-14 Alan Modra + + * dis-asm.h (print_insn_i386): Declare. + +2001-11-11 Timothy Wall + + * dis-asm.h: Fix comment to refer to octets rather than bytes. + +2001-10-30 Hans-Peter Nilsson + + * dis-asm.h (print_insn_mmix): Add prototype. + +2001-10-24 Neil Booth + + * safe-ctype.h (_sch_isbasic, IS_ISOBASIC): New. + +2001-10-22 Kaveh R. Ghazi + + * libiberty.h (hex_init): Revert delete. + + * libiberty.h (_hex_value): Const-ify. + (hex_init): Delete. + +2001-10-16 Christopher Faylor + + * filenames.h: Add cygwin to the list of dosish style path systems. + +2001-10-07 Kaveh R. Ghazi + + * demangle.h (demangler_engine): Const-ify. + * libiberty.h (buildargv): Likewise. + +2001-10-03 Vassili Karpov + + * bfdlink.h (struct bfd_link_info): Add nocopyreloc field. + +2001-09-24 Kaveh R. Ghazi + + * libiberty.h (reconcat): New function. + +2001-09-18 Kaveh R. Ghazi + + * libiberty.h (concat, concat_length, concat_copy, concat_copy2, + ACONCAT): Improve comments. + +2001-09-18 Alan Modra + + * objalloc.h (OBJALLOC_ALIGN): Define using offsetof. + +2001-09-17 Kaveh R. Ghazi + + * libiberty.h (concat_length, concat_copy, concat_copy2, + libiberty_concat_ptr, ACONCAT): New. + + * libiberty.h (ASTRDUP): New macro. + libiberty_optr, libiberty_nptr, libiberty_len): Declare. + +2001-08-29 Kaveh R. Ghazi + + * ansidecl.h: Update comments reflecting previous change. + +2001-08-27 Kaveh R. Ghazi + + * ansidecl.h (VA_OPEN, VA_CLOSE): Allow multiple uses. + +2001-08-25 Nick Clifton + + * bfdlink.h (struct bfd_link_info): Change 'spare_dynamic_tags' to + unsigned to remove a compile time warning message. + +2001-08-24 H.J. Lu + + * bfdlink.h (bfd_link_hash_table_type): New. The linker hash + table type, bfd_link_generic_hash_table and + bfd_link_elf_hash_table. + (bfd_link_hash_table): Add a new field, type, for the linker + hash table type. + +2001-08-23 Jakub Jelinek + + * bfdlink.h (struct bfd_link_info): Add combreloc and + spare_dynamic_tags fields. + +2001-08-23 Lars Brinkhoff + + * dyn-string.h, fibheap.h, partition.h, sort.h, splay-tree.h: + replace "GNU CC" with "GCC". + +2001-08-21 Richard Henderson + + * fibheap.h: Tidy formatting. + (fibnode_t): Limit degree to 31 bits to avoid warning. + +2001-08-20 Daniel Berlin + + * fibheap.h: New file. Fibonacci heap. + +2001-08-20 Andrew Cagney + + * floatformat.h (floatformat_arm_ext): Document as deprecated. + (floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword) + (floatformat_ia64_spill_little, floatformat_ia64_quad_little) + (floatformat_ia64_spill_big, floatformat_ia64_quad_big) + (floatformat_m88110_harris_ext): Declare. + +2001-08-18 Zack Weinberg + + * ansidecl.h: Reorganize for readability, remove documentation + of obsolete macros, document PARAMS and VPARAMS. Add new + macros VA_OPEN, VA_CLOSE, and VA_FIXEDARG for nicer variadic + function implementation. + +2001-08-16 Richard Henderson + + * hashtab.h (htab_hash_string): Declare. + +2001-08-10 Andrew Cagney + + * libiberty.h (lbasename): Change function declaration to return a + const char pointer. + +2001-08-02 Mark Kettenis + + * xregex.h (_REGEX_RE_COMP): Define. + (re_comp): Define to xre_comp. + (re_exec): Define to xre_exec. + +2001-08-02 Charles Wilson + + * bfdlink.h (struct bfd_link_info): add new boolean + field pei386_auto_import. + +2001-07-18 Andreas Jaeger + + * xregex2.h: Place under LGPL version 2.1. + +2001-07-10 Jeff Johnston + + * xregex.h: New file to support libiberty regex. + * xregex2.h: Ditto. + +2001-06-15 Hans-Peter Nilsson + + * bfdlink.h (struct bfd_link_info): New member export_dynamic. + +2001-05-16 Matt Kraai + + * partition.h: Fix misspelling of `implementation'. + +2001-05-10 Kaveh R. Ghazi + + * ansidecl.h (NULL_PTR): Delete. + +2001-05-07 Zack Weinberg + + * demangle.h: Use PARAMS for all prototypes. + * ternary.h: Use PARAMS for all prototypes. Use PTR, not void *. + Make arguments constant where possible. + +2001-05-07 Mark Mitchell + + * splay-tree.h (splay_tree_max): New function. + (splay_tree_min): Likewise. + +2001-04-27 Johan Rydberg + + * dis-asm.h (print_insn_openrisc): Add prototype. + +2001-04-15 Daniel Berlin + + * ternary.h: New file - Ternary search tree header. + +2001-04-13 Jakub Jelinek + + * bfdlink.h (bfd_link_discard): Add discard_sec_merge. + +2001-04-03 Zack Weinberg + + * ansidecl.h: All logic from gcc/gansidecl.h moved here. + +2001-03-31 Kaveh R. Ghazi + + * libiberty.h (alloca): Handle setting C_ALLOCA. + +2001-03-20 Jim Blandy + + * demangle.h (enum gnu_v3_constructor_kinds, + is_gnu_v3_mangled_ctor, enum gnu_v3_destructor_kinds, + is_gnu_v3_mangled_dtor): New declarations. + +2001-03-14 Nick Clifton + + * ansidecl.h: Fix copyright dates. + * demangle.h: Fix copyright dates. + * floatformat.h: Fix copyright dates. + * fnmatch.h: Fix copyright dates. + * getopt.h: Fix copyright dates. + * libiberty.h: Add FSF copyright notice. + * md5.h: Fix copyright dates. + * obstack.h: Fix copyright dates. + * splay-tree.h: Fix copyright dates. + +2001-03-10 Neil Booth + John David Anglin + + * libiberty.h: Add lbasename. + +2001-03-06 Zack Weinberg + + * libiberty.h: Prototype C_alloca; define alloca to either + __builtin_alloca or C_alloca as appropriate. + +2001-03-01 John David Anglin + + * safe-ctype.h (_sch_test): Cast enum bit to unsigned short int for pcc + compatibility. + +2001-02-18 lars brinkhoff + + * dis-asm.h: Add PDP-11 target. + +2001-02-09 Martin Schwidefsky + + * dis-asm.h: Add linux target for S/390. + +2001-01-11 Peter Targett + + * dis-asm.h (arc_get_disassembler): Correct declaration. + +2001-01-09 Philip Blundell + + * bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'. + +2000-12-18 Joseph S. Myers + + * COPYING: Update to current + ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references + to 19yy as example year in copyright notice). + +2000-12-19 Hans-Peter Nilsson + + * dis-asm.h (struct disassemble_info): New member "section". + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member. + Initialize section member. + +2000-12-16 Herman A.J. ten Brugge + + * safe-ctype.h: Make code work on all targets and not just on + targets where a char is 8 bits. + +2000-12-10 Fred Fish + + * bfdlink.h (struct bfd_link_info): Add new allow_shlib_undefined + member to struct for systems where it is normal to have undefined + symbols in shared libraries at runtime and the runtime linker + takes care of redirecting them. + +2000-12-07 Zack Weinberg + + * safe-ctype.h: New file. + +2000-12-06 Rodney Brown + + * getopt.h obstack.h: Standarize copyright statement. + +2000-12-04 Richard Henderson + + * demangle.h: Change "new_abi" to "v3" everywhere. + +2000-11-22 Zack Weinberg + + * libiberty.h: Move #includes to top. Prototype xmalloc_failed. + +2000-11-15 Kenneth Block + + * demangle.h: Add gnat and java demangle styles. + +2000-11-04 Hans-Peter Nilsson + + * hashtab.h (struct htab): Add member return_allocation_failure. + (htab_try_create): New prototype. Mention which functions may + return NULL when this is used. + +2000-11-03 Hans-Peter Nilsson + + * hashtab.h: Change void * to PTR where necessary. + +2000-10-11 Mark Mitchell + + * splay-tree.h (splay_tree_predecessor): Declare. + +2000-09-29 Hans-Peter Nilsson + + * dis-asm.h: Declare cris_get_disassembler, not print_insn_cris. + Fix typo in comment. + +2000-09-28 John David Anglin + + * alloca-conf.h: New file (copied from libiberty). + +2000-09-05 John David Anglin + + * md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX. + +2000-09-04 Alex Samuel + + * dyn-string.h: Adjust formatting. + (dyn_string_insert_char): New macro. New declaration. + +2000-08-28 Jason Merrill + + * md5.h: New file. + +2000-08-24 Greg McGary + + * libiberty.h (ARRAY_SIZE): New macro. + +2000-07-29 Nick Clifton + + * os9k.h: Add copyright notice. + Fix formatting. + +2000-07-22 Jason Eckhardt + + * dis-asm.h (print_insn_i860): Add prototype. + +2000-07-20 H.J. Lu + + * bfdlink.h (bfd_link_info): Add new_dtags. + +2000-07-20 Hans-Peter Nilsson + + * dis-asm.h (print_insn_cris): Declare. + +2000-07-19 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add flags and flags_1. + +2000-06-05 DJ Delorie + + * MAINTAINERS: new + +2000-06-21 Alex Samuel + + * dyn-string.h (dyn_string_init, dyn_string_new, + dyn_string_delete, dyn_string_release, dyn_string_resize, + dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring_dyn_string_eq): + Define as same name with __cxa_ prepended, if IN_LIBGCC2. + (dyn_string_init, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring): Change return type + to int. + +2000-06-18 Stephane Carrez + + * dis-asm.h (print_insn_m68hc12): Define. + (print_insn_m68hc11): Likewise. + +2000-06-18 Nick Clifton + + * os9k.h: Change values of MODSYNC and CRCCON due to bug report + from Russ Magee . + +2000-06-07 Kaveh R. Ghazi + + * demangle.h (demangling_styles): Remove trailing comma in enum. + + * dyn-string.h (dyn_string_append_char): Change parameter from + char to int. + +2000-06-04 Alex Samuel + + * dyn-string.h: Move here from gcc/dyn-string.h. Add new functions. + + * demangle.h (DMGL_GNU_NEW_ABI): New macro. + (DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI. + (current_demangling_style): Add gnu_new_abi_demangling. + (GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro. + (GNU_NEW_ABI_DEMANGLING): Likewise. + (cplus_demangle_new_abi): New declaration. + +Tue May 30 16:53:34 2000 Andrew Cagney + + * floatformat.h (struct floatformat): Add field name. + +2000-05-26 Eli Zaretskii + + * filenames.h: New file. + (HAVE_DOS_BASED_FILE_SYSTEM, IS_DIR_SEPARATOR) + (IS_ABSOLUTE_PATH, FILENAME_CMP): New macros. + +2000-05-23 Kaveh R. Ghazi + + * getopt.h (getopt): Also check HAVE_DECL_* when prototyping. + + * libiberty.h (basename): Likewise. + +2000-05-17 S. Bharadwaj Yadavalli + Rick Gorton + + * bfdlink.h (struct bfd_link_info): Add emitrelocations flag. + +2000-05-08 Alan Modra + + * dis-asm.h (print_insn_tic54x): Declare. + +2000-05-06 Zack Weinberg + + * ansidecl.h: #define __extension__ to nothing if + GCC_VERSION < 2008. + +2000-05-04 Kaveh R. Ghazi + + * demangle.h (demangler_engine): Constify. + +Thu May 4 17:15:26 2000 Philippe De Muyter + + * sort.h (sys/types.h): File included unconditionnaly. + (stddef.h): File include only #ifdef __STDC__. + +2000-05-03 Zack Weinberg + + * symcat.h: Remove #endif label. + +2000-04-28 Kenneth Block + Jason Merrill + + * demangle.h (libiberty_demanglers): new table for different styles. + (cplus_demangle_set_style): New function for setting style. + (cplus_demangle_name_to_style): New function to translate name. + +2000-04-24 Mark Mitchell + + * hashtab.h (hash_pointer): Declare. + (eq_pointer): Likewise. + +2000-04-23 Mark Mitchell + + * sort.h: New file. + +Fri Apr 21 13:20:53 2000 Richard Henderson + David Mosberger + + * dis-asm.h (print_insn_ia64): Declare. + +Tue Apr 18 16:22:30 2000 Richard Kenner + + * hashtab.h (enum insert_option): New type. + (htab_find_slot, htab_find_slot_with_hash): Use it. + +2000-04-17 Kaveh R. Ghazi + + * symcat.h: Honor autoconf macro HAVE_STRINGIZE. Add + comments/caveats with regard to traditional C behavior. + +2000-04-05 Richard Henderson + + * splay-tree.h (splay_tree_remove): Declare. + +2000-04-04 Alan Modra + + * bin-bugs.h (REPORT_BUGS_TO): Remove translated part. + +2000-04-03 Alan Modra + + * bin-bugs.h: New file. + +2000-03-30 Mark Mitchell + + * hashtab.h (hashval_t): New type. + (htab_find_with_hash): Use it as an argument. + (htab_find_slot_with_hash): Likewise. + +2000-03-27 Denis Chertykov + + * dis-asm.h (print_insn_avr): Declare. + +2000-03-14 Bernd Schmidt + + * hashtab.h (htab_trav): Modify type so that first arg is of type + void **. + (htab_find_with_hash, htab_find_slot_with_hash): Declare new + functions. + +2000-03-09 Alex Samuel + + * partition.h: New file. + +2000-03-09 Zack Weinberg + + * hashtab.h (struct htab): Add del_f. + (htab_del): New type. + (htab_create): Add fourth argument. + +2000-03-08 Zack Weinberg + + * hashtab.h (hash_table_t): Rename to htab_t. + (struct hash_table): Rename to struct htab. Shorten element + names. Reorder elements by size. + (htab_hash, htab_eq, htab_trav): New typedefs for the callback + function pointers. + (hash_table_entry_t): Discard; just use void * for element + type. + +2000-03-01 H.J. Lu + + * bfdlink.h (bfd_link_callbacks): Add a boolean arg to + the undefined_symbol callback. + +2000-02-23 Linas Vepstas + + * dis-asm.h (print_insn_i370): Declare. + +Tue Feb 22 15:19:54 2000 Andrew Cagney + + * remote-sim.h (sim_trace): Document return values. + (sim_set_trace): Declare. Deprecate. + +2000-02-21 Alan Modra + + * dis-asm.h (struct disassemble_info): Change `length' param of + read_memory_func to unsigned. Change type of `buffer_length' and + `octets_per_byte' to unsigned. + (buffer_read_memory): Change `length' param to unsigned. + +2000-02-16 Nick Clifton + + * dis-asm.h: Add prototypes for ARM register name functions. + +Wed Feb 9 18:45:49 2000 Andrew Cagney + + * wait.h: Delete. No longer used by GDB. + +Tue Feb 8 17:01:13 2000 Andrew Cagney + + * remote-sim.h (sim_resume): Clarify use of SIGGNAL. + (sim_stop_reason): Clarify meaning of sim_signalled. + +2000-02-03 Timothy Wall + + * dis-asm.h (struct disassemble_info): Added octets_per_byte + field and initialize it to one (1). + +2000-01-27 Nick Clifton + + * dis-asm.h: Add prototype for disassembler_usage(). + Add prototype for arm_disassembler_options(). + Remove prototype for arm_toggle_regnames(). + Add prototype for parse_arm_disassembler_option(). + +Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson + + * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s" + to stringify argument s. + +Wed Dec 15 11:22:56 1999 Jeffrey A Law (law@cygnus.com) + + * hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant. + (HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN. + +1999-12-15 Doug Evans + + * dis-asm.h: Enclose in extern "C" ifdef __cplusplus. + +1999-12-05 Mark Mitchell + + * splay-tree.h (struct splay_tree_node): Rename to ... + (struct splay_tree_node_s): ... this. + (struct splay_tree): Rename to ... + (struct splay_tree_s): ... this. + +1999-11-30 Kaveh R. Ghazi + + * ansidecl.h (ATTRIBUTE_MALLOC): New macro. + + * libiberty.h (buildargv, dupargv, concat, choose_temp_base, + make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add + ATTRIBUTE_MALLOC. + (xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN. + +1999-11-28 Kaveh R. Ghazi + + * libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined. + (asprintf, vasprintf): Provide declarations. + +Wed Nov 10 12:43:21 1999 Philippe De Muyter + Kaveh R. Ghazi + + * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'. + +1999-11-04 Jimmy Guo + + * hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind + fields, change location type to CORE_ADDR from int. + (dntt_type_const): Name the 5th field location_type. + +Sun Oct 24 19:11:32 1999 Andrew Cagney + + * sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define. + +1999-10-23 08:51 -0700 Zack Weinberg + + * hashtab.h: Give hash_table_t a struct tag. Add prototypes + for clear_hash_table_slot and traverse_hash_table. Correct + prototype of all_hash_table_collisions. + +Sat Oct 23 19:00:13 1999 Andrew Cagney + + * sim-d10v.h: New file. + +Fri Oct 15 01:47:51 1999 Vladimir Makarov + + * hashtab.h: New file. + +1999-10-10 Kaveh R. Ghazi + + * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of + explicitly testing __GNUC__ and __GNUC_MINOR__. + + (ATTRIBUTE_PRINTF): Use `__format__', not `format'. + +1999-09-25 Kaveh R. Ghazi + + * libiberty.h (make_temp_file): Add a prototype. + +Tue Sep 14 00:35:02 1999 Marc Espie + + * libiberty.h (basename): OpenBSD has a correct prototype. + (xrealloc): Remove outdated comment. + +1999-09-07 Jeff Garzik + + * libiberty.h (xmemdup): Add prototype for new function. + +1999-09-04 Steve Chamberlain + + * dis-asm.h (print_insn_pj): Declare. + +1999-09-01 Kaveh R. Ghazi + + * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts + in calls to `_obstack_memcpy' from here ... + + (_obstack_memcpy): ... to here, except in the __STDC__ case which + doesn't need it. + +1999-08-30 Kaveh R. Ghazi + + * libiberty.h (getpwd): Prototype. + +1999-08-01 Mark Mitchell + + * splay-tree.h (splay_tree_insert): Return the new node. + +1999-07-11 Ian Lance Taylor + + * ansidecl.h: Copy attribute support macros from egcs. + +1999-06-22 Mark Mitchell + + * bfdlink.h (struct bfd_link_hash_entry): Add init_function and + fini_function. + +1999-06-20 Mark Mitchell + + * mips.h (Elf32_Internal_Msym): New structure. + (Elf32_External_Msym): Likewise. + (ELF32_MS_REL_INDEX): New macro. + (ELF32_MS_FLAGS): Likewise. + (ELF32_MS_INFO): Likewise. + +1999-06-14 Nick Clifton + + * dis-asm.h (arm_toggle_regnames): New prototype. + (struct diassemble_info): New field: disassembler_options. + +1999-04-11 Richard Henderson + + * bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'. + Add `match' callback function. + +1999-04-10 Richard Henderson + + * bfdlink.h (bfd_link_info): Add no_undefined. + +1999-04-08 Nick Clifton + + * dis-asm.h: Add prototype for print_insn_mcore. + +1999-04-02 Mark Mitchell + + * splay-tree.h (splay_tree_compare_pointers): Declare. + +1999-03-30 Mark Mitchell + + * splay-tree.h (splay_tree_compare_ints): Declare. + +Wed Mar 24 12:46:29 1999 Andrew Cagney + + * libiberty.h (basename): Cygwin{,32} should have the prototype. + +1999-02-22 Jim Lemke + + * bfdlink.h (bfd_link_info): add field "mpc860c0". + +Mon Feb 1 21:05:46 1999 Catherine Moore + + * dis-asm.h (print_insn_i386_att): Declare. + (print_insn_i386_intel): Declare. + +1998-12-30 Michael Meissner + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and + FPRINTF_FUNC to avoid compiler warnings. + +Wed Dec 30 16:07:14 1998 David Taylor + + * dis-asm.h: change void * to PTR (two places). + +Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi + + * demangle.h: Don't check IN_GCC anymore. + * splay-tree.h: Likewise. + +Tue Dec 8 00:30:31 1998 Elena Zannoni + + The following changes were made by Elena Zannoni + and Edith Epstein + as part of a project to merge in + changes made by HP; HP did not create ChangeLog entries. + + * dis-asm.h (struct disassemble_info): change the type of stream + from FILE* to void*, for use with gdb's new type GDB_FILE. + (fprintf_ftype): change FILE* parameter type to void*. + + * demangle.h: (DMGL_EDG): new macro for Kuck and Associates + (DMGL_STYLE_MASK): modify to include Kuck and Assoc style + (demangling_styles): add new edg_demangling style + (EDG_DEMANGLING_STYLE_STRING): new macro + (EDG_DEMANGLING): new macro + (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_STYLE_MASK): modify to include new HP's style. + (demangling_styles): add new hp_demangling value. + (HP_DEMANGLING_STYLE_STRING): new macro. + (ARM_DEMANGLING): coerce to int. + (HP_DEMANGLING): new macro. + + * hp-symtab.h: rewritten, from HP. + (quick_procedure): change type of language field to unsigned int + (quick_module): change type of language field to unsigned int + (struct dntt_type_svar): add field thread_specific. + (hp_language): add languages modcal and dmpascal. + +Fri Nov 20 13:14:00 1998 Andrew Cagney + + * libiberty.h (basename): Add prototype for FreeBSD. + +Fri Nov 13 19:19:11 1998 Kaveh R. Ghazi + + * libiberty.h: Prototype xcalloc. + +Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi + + * ansidecl.h: Wrap problematic macros with !IN_GCC. + + * demangle.h: Never define PARAMS(). + * splay-tree.h: Likewise. + +Sat Nov 7 18:30:20 1998 Peter Schauer + + * dis-asm.h (print_insn_vax): Declare. + +Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi + + * demangle.h: Don't include gansidecl.h. + * splay-tree.h: Likewise. + +1998-10-26 16:03 Ulrich Drepper + + * bfdlink.h (struct bfd_link_info): Add new field optimize. + +Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi + + * splay-tree.h: Wrap function pointer parameter declarations in + PARAMS() macro. + +1998-10-21 Mark Mitchell + + * splay-tree.h: New file. + +Fri Oct 9 00:02:03 1998 Jeffrey A Law (law@cygnus.com) + + * Merge devo and egcs include directories. + +Sat Sep 5 12:16:33 1998 Jeffrey A Law (law@cygnus.com) + + * getopt.h, obstack.h: Updated from gcc. + +1998-08-03 Jason Molenda (jsm@bugshack.cygnus.com) + + * libiberty.h (xexit): Change decl to use modern GCC attribute + to indicate exit does not return. + +Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.h: Update to latest FSF version. + +Tue Feb 24 13:05:02 1998 Doug Evans + + * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols' + and made an "asymbol **". New member num_symbols. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Update. + +Tue Feb 17 12:32:18 1998 Andrew Cagney + + * remote-sim.h (sim_fetch_register, sim_store_register): Add + register length parameter. Functions return actual length of + register. + +Thu Feb 12 16:29:01 1998 Ian Lance Taylor + + * getopt.h: Update to latest FSF version. + +Wed Feb 11 16:56:06 1998 Doug Evans + + * symcat.h: New file. + +Mon Feb 2 17:13:31 1998 Steve Haworth + + * dis-asm.h (print_insn_tic30): Declare. + +Thu Jan 22 16:23:59 1998 Fred Fish + + * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly + function there is a reloc on this line. + +Mon Dec 8 11:22:23 1997 Nick Clifton + + * dis-asm.h: Remove prototype of disasm_symaddr() as this function + no longer exists. + +Tue Dec 2 10:20:53 1997 Nick Clifton + + * dis-asm.h (disasm_symaddr): New prototype. + +Mon Dec 1 11:29:35 1997 Doug Evans + + * callback.h (CB_SYSCALL): Comment out arg names in prototypes. + +Wed Nov 26 16:47:58 1997 Michael Meissner + + * callback.h (CB_SYSCALL): Consistantly use names for prototype + arguments. + +Wed Nov 26 11:39:30 1997 Doug Evans + + * callback.h (CB_SYSCALL): Change byte count arguments to + {read,write}_mem to `int'. New member `magic'. + (CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros. + +Tue Nov 25 01:35:52 1997 Doug Evans + + * callback.h (struct stat): Move forward decl up. + (host_callback): Pass stat struct pointer to stat,fstat. + (CB_SYS_nnn): Reorganize. + (CB_SYSCALL): New members p1,p2. + (cb_host_to_target_stat): Delete fourth arg. + +Sat Nov 22 23:34:15 1997 Andrew Cagney + + * remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC + argument. + +Mon Nov 17 14:00:51 1997 Doug Evans + + * callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map. + (host_callback): Add stat, fstat, syscall_map, errno_map, open_map, + signal_map, stat_map. + (errn_map,open_map): Renamed to cb_init_foo_map. + (cb_host_to_target_errno,cb_target_to_host_open): Renamed from + host_to_target_errno,target_to_host_open. + (cb_read_target_syscall_maps): Add prototype. + (cb_target_to_host_syscall): Likewise. + (cb_host_to_target_stat): Likewise. + (cb_syscall): Likewise. + (CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat, + argvlen,argv,chdir,stat,chmod,utime,time}): Define. + (CB_SYSCALL): New type. + (CB_RC): New enum. + +Fri Nov 7 10:34:09 1997 Rob Savoye + + * libiberty.h: Add extern "C" { so it can be used with C++ + programs. + * remote-sim.h: Add extern "C" { so it can be used with C++ + programs. + +Tue Oct 14 16:07:51 1997 Nick Clifton + + * dis-asm.h (struct disassemble_info): New field + 'symbol_at_address_func'. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with + generic_symbol_at_address. + +Mon Oct 13 10:17:15 1997 Andrew Cagney + + * remote-sim.h: Clarify sim_read, sim_write MEM argument. + +Wed Sep 24 18:03:10 1997 Stu Grossman + + * remote-sim.h (SIM_RC): Add a bunch of new return codes for + breakpoint stuff. + * Add functions to tell the simulator to set/clear/enable/disable + intrinsic breakpoints. + +Thu Aug 28 19:41:42 1997 Andrew Cagney + + * libiberty.h (dupargv): Add prototype. + +Tue Aug 26 12:25:49 1997 Andrew Cagney + + * remote-sim.h (sim_create_inferior): Add ABFD arg. Document. + +Mon Aug 25 10:50:51 1997 Andrew Cagney + + * remote-sim.h (sim_open): Add ABFD arg. Document. + +Fri Aug 8 16:43:56 1997 Doug Evans + + * dis-asm.h (arc_get_disassembler): Declare. + +Wed Jul 30 11:39:50 1997 Per Bothner + + * demangle.h (DMGL_JAVA): New option to request Java demangling. + +Tue Jul 22 17:59:54 1997 Ian Lance Taylor + + * libiberty.h (PEXECUTE_*): Define. + (pexecute, pwait): Declare. + +Fri Jun 6 13:02:33 1997 Andrew Cagney + + * remote-sim.h (sim_kill): Mark as depreciated. + +Fri May 23 13:43:41 1997 Fred Fish + + * bfdlink.h (struct bfd_link_info): Add task_link member. + +Thu May 22 11:32:49 1997 Andrew Cagney + + * remote-sim.h: Review documentation. Clarify restrictions on + when functions can be called. + +Wed May 21 16:47:53 1997 Andrew Cagney + + * remote-sim.h (sim_set_profile_size): Add prototype, document as + depreciated. + +Tue May 20 09:32:22 1997 Andrew Cagney + + * remote-sim.h (sim_open): Add callback struct. + (sim_set_callbacks): Drop SIM_DESC argument. Document. + (sim_size): Remove recently added SIM_DESC argument. Document. + +Mon May 19 19:14:44 1997 Andrew Cagney + + * remote-sim.h: Pass SD into sim_size. + +Thu May 15 01:24:16 1997 Mark Alexander + + * obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun, + obstack_freefun): Eliminate compile warnings in gdb. + +Tue Apr 22 10:24:34 1997 Fred Fish + + * floatformat.h (floatformat_byteorders): Add comments for previous + formats and add floatformat_littlebyte_bigword, primarily for ARM. + Add declaration for floatformat_ieee_double_littlebyte_bigword. + +Fri Apr 18 13:04:49 1997 Andrew Cagney + + * remote-sim.h (sim_stop): New interface - asynchronous + notification of a request to stop / suspend the running + simulation. + + * remote-sim.h (enum sim_stop): Add sim_running and sim_polling as + states for use internal to simulators. + + * callback.h (struct host_callback_strut): Put a magic number at + the end of the struct to allow basic checking. + (struct host_callback_struct ): Add poll_quit - so + that the console etc can be polled at regular intervals. + +Thu Apr 17 02:17:12 1997 Doug Evans + + * remote-sim.h (struct _bfd): Declare. + (sim_load): Return SIM_RC. New arg `abfd'. + (sim_create_inferior): Return SIM_RC. Delete arg `start_address'. + +Wed Apr 2 17:09:12 1997 Andrew Cagney + + * remote-sim.h (sim_trace, sim_size): Make these global. They + will go away shortly. + +Wed Apr 2 15:23:49 1997 Doug Evans + + * remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums. + (sim_open): New argument `kind'. + +Wed Apr 2 14:45:51 1997 Ian Lance Taylor + + * COPYING: Update FSF address. + +Fri Mar 28 15:29:54 1997 Mike Meissner + + * callback.h (top level): Include stdarg.h or varargs.h if + va_start is not defined. + (host_callback_struct): Make {,e}vprintf_filtered take a va_list + instead of void *, since va_list might be an array or structure + type. + +Fri Mar 28 15:44:41 1997 H.J. Lu + + * libiberty.h (basename): Add prototype for glibc and linux. + +Mon Mar 17 19:22:12 1997 Ian Lance Taylor + + * objalloc.h: New file. + +Mon Mar 17 14:57:55 1997 Andrew Cagney + + * remote-sim.h: New file, copied in from gdb/remote-sim.h. One + day this will be placed in a directory of its own. + +Sat Mar 15 19:00:14 1997 Ian Lance Taylor + + * obstack.h: Update to current FSF version. + +Thu Mar 6 15:46:59 1997 Andrew Cagney + + * callback.h (struct host_callback_struct): Add callbacks - + flush_stdout, write_stderr, flush_stderr, vprintf_filtered, + evprintf_filtered. Delete redundant callbacks - printf_filtered. + +Thu Feb 27 23:18:27 1997 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_info): Remove lprefix and lprefix_len + fields. + +Tue Feb 25 00:10:49 1997 Ian Lance Taylor + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize + bytes_per_chunk and display_endian. + +Mon Feb 24 17:47:02 1997 Ian Lance Taylor + + From Eric Youngdale : + * bfdlink.h (struct bfd_elf_version_expr): Define. + (struct bfd_elf_version_deps): Define. + (struct bfd_elf_version_tree): Define. + +Thu Feb 6 14:20:01 1997 Martin M. Hunt + + * dis-asm.h: (disassemble_info): Add new fields + bytes_per_chunk and display_endian to control the + display of raw instructions. + +Fri Dec 27 22:17:37 1996 Fred Fish + + * dis-asm.h (print_insn_tic80): Declare. + +Sun Dec 8 17:11:12 1996 Doug Evans + + * callback.h (host_callback): New member `error'. + +Wed Nov 20 00:40:23 1996 Doug Evans + + * callback.h: New file, moved here from gdb. + +Mon Nov 18 16:34:00 1996 Dawn Perchik + + * libiberty.h: Checkin again; last checkin failed due to sticky tag. + +Wed Nov 13 08:22:00 1996 Dawn Perchik + + * libiberty.h: Revert last commit due to conflicts with hpux + system headers. + +Tue Nov 12 16:31:00 1996 Dawn Perchik + + * libiberty.h: Move prototypes from argv.c here. + +Thu Oct 31 14:56:18 1996 Doug Evans + + * ansidecl.h (VPARAMS,VA_START): Define. + +Fri Oct 25 12:08:04 1996 Ian Lance Taylor + + * dis-asm.h (disassemble_info): Add bytes_per_line field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize bytes_per_line field. + +Thu Oct 24 17:10:01 1996 Ian Lance Taylor + + * dis-asm.h (disassemble_info): Add symbol field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize symbol field. + +Thu Oct 17 11:17:40 1996 Doug Evans + + * dis-asm.h (print_insn_m32r): Declare. + +Mon Oct 14 23:56:52 1996 Ian Lance Taylor + + * libiberty.h: Declare parameter types for xmalloc and xrealloc. + +Thu Oct 3 13:45:27 1996 Ian Lance Taylor + + * fnmatch.h: New file. + +Thu Oct 3 10:33:14 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Delete declaration. + (print_insn_mn10200, print_insn_mn10300): Declare. + +Wed Oct 2 21:24:43 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Declare. + +Mon Sep 30 13:56:11 1996 Fred Fish + + * libiberty.h: Remove #ifndef PRIVATE_XMALLOC. + +Sat Aug 31 13:27:06 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_v850): Declare. + +Tue Aug 13 16:10:30 1996 Stu Grossman (grossman@critters.cygnus.com) + + * obstack.h: Change bcopy to memcpy. Works better on Posix + systems, which generally lack bcopy. + +Mon Aug 12 17:03:18 1996 Stu Grossman (grossman@critters.cygnus.com) + + * ansidecl.h: Change WIN32 to _WIN32. + +Fri Jul 26 13:58:18 1996 Ian Lance Taylor + + * dis-asm.h: Add flavour field. + (print_insn_alpha): Declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Don't declare. + (INIT_DISASSEMBLE_INFO): Initialize flavour field. + +Tue Jul 23 17:37:58 1996 Fred Fish + + * libiberty.h (PRIVATE_XMALLOC): Enclose xmalloc/xrealloc + definitions inside #ifndef so that programs that want to + can define PRIVATE_XMALLOC and then define xmalloc and + xrealloc anyway they want. + (basename): Document in source that we can't declare the + parameter type because it is declared inconsistently across + different systems. + +Mon Jul 22 13:16:13 1996 Richard Henderson + + * dis-asm.h (print_insn_alpha): Don't declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Declare. + +Wed Jul 17 14:45:12 1996 Martin M. Hunt + + * dis-asm.h: (print_insn_d10v): Declare. + +Mon Jul 15 16:55:38 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h: Get rid of decls for print_insn_i8086, + print_insn_sparc64 and print_insn_sparclite. + * (INIT_DISASSEMBLE_INFO): Split into two pieces. One, + INIT_DISASSEMBLE_INFO_NO_ARCH inits everything except for endian, + mach, and arch. + +Fri Jul 12 10:19:27 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_i8086): Declare. + +Wed Jul 3 16:02:39 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_sparclite): Declare. + +Tue Jun 18 16:02:46 1996 Jeffrey A. Law + + * dis-asm.h (print_insn_h8300s): Declare. + +Tue Jun 18 15:11:33 1996 Klaus Kaempf + + * fopen-vms.h: New file. + +Tue Jun 4 18:58:16 1996 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_info): Add notice_all field. + +Fri Apr 26 10:33:12 1996 Doug Evans + + * demangle.h (#ifdef IN_GCC): #include "gansidecl.h". + (PROTO,PTR,const): Delete. + +Mon Apr 22 17:27:42 1996 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_info): Add traditional_format field. + +Mon Apr 15 15:16:56 1996 Doug Evans + + * libiberty.h (choose_temp_base): Add prototype. + +Tue Mar 12 17:29:46 1996 Ian Lance Taylor + + * bfdlink.h (bfd_wrapped_link_hash_lookup): Declare. + (struct bfd_link_info): Add wrap_hash field. + +Wed Feb 14 16:49:17 1996 Martin Anantharaman + + * ieee.h (ieee_record_enum_type): Define + ieee_external_reference_info_enum. + +Fri Feb 2 17:09:25 1996 Doug Evans + + * dis-asm.h (DISASM_RAW_INSN): Delete. + +Tue Jan 23 09:21:47 1996 Doug Evans + + * dis-asm.h (INIT_DISASSEMBLE_INFO): Set endian to BFD_ENDIAN_UNKNOWN. + New argument FPRINTF_FUNC. + +Mon Jan 22 16:37:59 1996 Doug Evans + + * dis-asm.h (disassemble_info): New members arch, mach, endian. + (INIT_DISASSEMBLE_INFO): Initialize them. + (DISASM_RAW_INSN{,FLAG}): Define. + +Thu Jan 18 11:32:38 1996 Ian Lance Taylor + + * demangle.h (cplus_demangle_opname): Change opname parameter to + const char *. + (cplus_mangle_opname): Change return type and opname parameter to + const char *. + +Fri Jan 5 00:01:22 1996 Ian Lance Taylor + + * ieee.h (enum ieee_record): Add ieee_asn_record_enum, + ieee_at_record_enum, ieee_ty_record_enum, ieee_atn_record_enum, + ieee_bb_record_enum, and ieee_be_record_enum. + +Wed Jan 3 13:12:09 1996 Fred Fish + + * obstack.h: Update copyright to 1996. + (_obstack_memory_used): Declare. + (obstack_memory_used): Define macro. + +Thu Dec 28 11:42:12 1995 Ian Lance Taylor + + * libiberty.h (xstrdup): Declare. + +Thu Dec 21 14:47:17 1995 Michael Meissner + + * wait.h: Protect all macros with #ifndef. + +Tue Oct 24 21:45:40 1995 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_info): Add static_link field. + +Tue Sep 12 16:28:04 1995 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_callbacks): Add symbol parameter to + warning callback. + +Fri Sep 1 13:11:51 1995 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_callbacks): Change warning callback + to take BFD, section, and address arguments. + +Thu Aug 31 16:45:12 1995 steve chamberlain + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Tue Aug 22 03:18:23 1995 Ken Raeburn + + * libiberty.h: Declare xstrerror. From Pat Rankin. + +Mon Aug 21 18:11:36 1995 steve chamberlain + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Wed Aug 2 08:14:12 1995 Doug Evans + + * dis-asm.h (print_insn_sparc64): Declare. + +Mon Jul 10 13:26:49 1995 Eric Youngdale + + * bfdlink.h (struct bfd_link_info): Add new field symbolic. + +Sun Jul 2 17:48:40 1995 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_info): Change type of base_file to + PTR. + +Thu Jun 29 00:02:45 1995 Steve Chamberlain + + * bfdlink.h (struct bfd_link_info): Added base_file member. + +Tue Jun 20 16:40:04 1995 Steve Chamberlain + + * ansidecl.h: win32s is ANSI enough. + +Thu May 18 04:25:50 1995 Ken Raeburn + + Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * dis-asm.h (print_insn_arm): Delete declaration. + (print_insn_{little,big}_arm): New declarations. + + * floatformat.h (floatformat_arm_ext): Declare. + +Sat May 13 10:14:08 1995 Steve Chamberlain + + * bfdlink.h (subsytem, stack_heap_parameters): New. + +Thu May 4 14:36:42 1995 Jason Merrill + + * demangle.h: Don't include ansidecl.h if IN_GCC. + +Tue Feb 21 00:37:28 1995 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: Don't use bitfield enumerations, the HP C compiler + does not handle them correctly. + +Thu Feb 9 14:20:27 1995 Ian Lance Taylor + + * libiberty.h (basename): Don't declare parameter type; some + systems have this in their header files. + +Wed Feb 8 17:35:38 1995 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_hash_entry): Change format of common + symbol information, to remove restrictions on maximum size and + alignment power, by using a pointer to a structure instead. + +Mon Feb 6 14:55:32 1995 Ian Lance Taylor + + * bfdlink.h (enum bfd_link_hash_type): Rename bfd_link_hash_weak + to bfd_link_hash_undefweak. Add bfd_link_hash_defweak. + +Mon Jan 16 21:00:23 1995 Stan Shebs + + * dis-asm.h (GDB_INIT_DISASSEMBLE_INFO, etc): Remove all + GDB-specific definitions. + +Sun Jan 15 18:39:35 1995 Steve Chamberlain + + * dis-asm.h (print_insn_w65): Declare. + +Thu Jan 12 17:51:17 1995 Ken Raeburn + + * libiberty.h (hex_p): Fix sense of test. + +Wed Jan 11 22:36:40 1995 Ken Raeburn + + * libiberty.h (_hex_array_size, _hex_bad, _hex_value, hex_init, + hex_p, hex_value): New macros and declarations, for hex.c. + +Fri Jan 6 17:44:14 1995 Ian Lance Taylor + + * dis-asm.h: Make idempotent. + +Wed Dec 14 13:08:43 1994 Stan Shebs + + * progress.h: New file, empty definitions for progress macros. + +Fri Nov 25 00:14:05 1994 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: New file describing the debug symbols emitted + by the HP C compilers. + +Fri Nov 11 15:48:37 1994 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size from 24 + to 26 bits, and change u.c.alignment_power from 8 to 6 bits. 6 + bit in the alignment power is enough for a 64 bit address space. + +Mon Oct 31 13:02:51 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_mangle_opname): Declare. + +Tue Oct 25 11:38:02 1994 Ian Lance Taylor + + * bfdlink.h (struct bfd_link_callbacks): Fix comments for + multiple_common field. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * dis-asm.h: Add support for the ARM. + +Wed Aug 10 12:51:41 1994 Doug Evans (dje@canuck.cygnus.com) + + * libiberty.h (strsignal): Document its existence even if we + can't declare it. + +Tue Aug 2 14:40:03 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * os9k.h: Remove u_int16, u_int32, and owner_id typedefs and + expand their uses. Those names conflict with Mach headers. + +Fri Jul 22 14:17:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size into a + bitfield. Add field u.c.alignment_power. + +Sun Jul 10 00:26:39 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * dis-asm.h: Add print_insn_ns32k declaration. + +Mon Jun 20 17:13:29 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (bfd_link_hash_table): Make creator a const pointer. + +Sat Jun 18 16:09:32 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_demangle_opname): Declare. + +Thu Jun 16 15:19:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_info): Add new field shared. + +Mon Jun 6 14:39:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Remove written field: + not needed for all backends. + +Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * dis-asm.h (disassembler): Declare. + +Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) + + * obstack.h: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. + +Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (enum bfd_link_order_type): Add bfd_data_link_order. + (struct bfd_link_order): Add data field to union. + +Mon Mar 21 18:45:26 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Change bitsize argument + to add_to_set to reloc. Remove bitsize argument from constructor. + Comment that reloc_overflow, reloc_dangerous and unattached_reloc + must handle NULL pointers for reloc location. + (enum bfd_link_order_type): Add bfd_section_reloc_link_order and + bfd_symbol_reloc_link_order. + (struct bfd_link_order): Add reloc field to union. + (struct bfd_link_order_reloc): Define. + +Mon Mar 14 12:27:50 1994 Ian Lance Taylor (ian@cygnus.com) + + * ieee-float.h: Removed; no longer used. + +Tue Mar 1 18:10:49 1994 Kung Hsu (kung@mexican.cygnus.com) + + * os9k.h: os9000 target specific header file, the header of the + object file is used now. + +Sun Feb 27 21:52:26 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * floatformat.h: New file, intended to replace ieee-float.h. + +Sun Feb 20 17:15:42 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * ansidecl.h (ANSI_PROTOTYPES): Define if using ANSI prototypes. + +Wed Feb 16 01:07:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * libiberty.h: Don't declare strsignal, to avoid conflicts with + Solaris system header files. + +Sat Feb 12 22:11:32 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * libiberty.h (xexit): Use __volatile__ to avoid losing if + compiling with gcc -traditional. + +Thu Feb 10 14:05:41 1994 Ian Lance Taylor (ian@cygnus.com) + + * libiberty.h: New file. Declares functions provided by + libiberty. + +Tue Feb 8 05:19:52 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + Handle obstack_chunk_alloc returning NULL. This allows + obstacks to be used by libraries, without forcing them + to call exit or longjmp. + * obstack.h (struct obstack): Add alloc_failed flag. + _obstack_begin, _obstack_begin_1): Declare to return int, not void. + (obstack_finish): If alloc_failed, return NULL. + (obstack_base, obstack_next_free, objstack_object_size): + If alloc_failed, return 0. + (obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow, + obstack_int_grow, obstack_blank): If alloc_failed, do nothing that + could corrupt the obstack. + +Mon Jan 24 15:06:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add name, reloc_name and + addend argments to reloc_overflow callback. + +Fri Jan 21 19:13:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (print_insn_big_powerpc, print_insn_little_powerpc, + print_insn_rs6000): Declare. + +Thu Jan 6 14:15:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to + add_to_set field. Add new callback named constructor. + +Thu Dec 30 10:44:06 1993 Ian Lance Taylor (ian@rtl.cygnus.com) + + * bfdlink.h: New file for new BFD linker backend routines. + +Mon Nov 29 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma. + +Sat Oct 2 20:42:26 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Move comment to right place. + +Mon Aug 9 19:03:35 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * obstack.h (obstack_chunkfun, obstack_freefun): Add defns from + previous version. Are these Cygnus local changes? + +Fri Aug 6 17:05:47 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * getopt.h, obstack.h: Update to latest FSF version. + +Mon Aug 2 14:45:29 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Move enum outside of struct defn to avoid warnings. + +Mon Aug 2 08:49:30 1993 Stu Grossman (grossman at cygnus.com) + + * wait.h (WEXITSTATUS, WSTOPSIG): Mask down to 8 bits. This is + for systems that store stuff into the high 16 bits of a wait + status. + +Fri Jul 30 18:38:02 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns, + data_size, insn_type, target, target2. These are used to return + information from the instruction decoders back to the calling + program. Add comments, make more readable. + +Mon Jul 19 22:14:14 1993 Fred Fish (fnf@deneb.cygnus.com) + + * nlm: New directory containing NLM/NetWare includes. + +Thu Jul 15 12:10:04 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (struct disassemble_info): New field application_data. + +Thu Jul 15 12:41:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h: Added declaration of print_insn_m88k. + +Fri Jul 2 10:31:59 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: Use ANSI macros if __mips and _SYSTYPE_SVR4 are + defined, since RISC/OS cc handles ANSI declarations in SVR4 mode + but does not define __STDC__. + +Sun Jun 20 18:27:52 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * dis-asm.h: Don't need to include ansidecl.h any more. + +Fri Jun 18 03:22:10 1993 John Gilmore (gnu@cygnus.com) + + * oasys.h: Eliminate "int8_type", "int16_type", "int32_type", and + their variants. These changes are coordinated with corresponding + changes in ../bfd/oasys.c. + +Wed Jun 16 10:43:08 1993 Fred Fish (fnf@cygnus.com) + + * bfd.h: Note that it has been removed. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * dis-asm.h (print_insn_h8300, print_insn_h8300h): Declare it. + +Tue Jun 1 07:35:03 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * ansidecl.h (const): Don't define it if it's already defined. + +Thu May 27 18:19:51 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (print_insn_hppa): Declare it. + + * bfd.h: Moved to bfd directory. Small stub here includes it + without requiring "-I../bfd". + +Thu Apr 29 12:06:13 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * bfd.h: Updated with BSF_FUNCTION. + +Mon Apr 26 18:15:50 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h, dis-asm.h: Updated with Hitachi SH. + +Fri Apr 23 18:41:38 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Updated with alpha changes. + * dis-asm.h: Added alpha. + +Fri Apr 16 17:35:30 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Update for signed bfd_*get_*. + +Thu Apr 15 09:24:21 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Updated for file_truncated error. + +Thu Apr 8 10:53:47 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: If no ANSI, define const to be empty. + +Thu Apr 1 09:00:10 1993 Jim Kingdon (kingdon@cygnus.com) + + * dis-asm.h: Declare a29k and i960 print_insn_*. + + * dis-asm.h: Add print_address_func and related stuff. + + * dis-asm.h (dis_asm_read_memory): Fix prototype. + +Wed Mar 31 17:40:16 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Add print_insn_sparc. + +Wed Mar 31 17:51:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size + prototypes. + +Wed Mar 31 16:35:12 1993 Stu Grossman (grossman@cygnus.com) + + * dis-asm.h: (disassemble_info): Fix typo in prototype of + dis_asm_memory_error(). + +Tue Mar 30 19:09:23 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h (disassembler_info): Add read_memory_func, + memory_error_func, buffer, and length. + ({GDB_,}INIT_DISASSEMBLE_INFO): Set them. + print_insn_*: Remove second argument. + +Tue Mar 30 14:48:55 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Update for lma field of section. + +Tue Mar 30 12:22:55 1993 Jim Kingdon (kingdon@cygnus.com) + + * ansidecl.h: Use ANSI versions on AIX regardless of __STDC__. + +Fri Mar 19 14:49:49 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * dis-asm.h: Add h8500. + +Thu Mar 18 13:49:09 1993 Per Bothner (bothner@rtl.cygnus.com) + + * ieee-float.h: Moved from ../gdb. + * dis-asm.h: New file. Interface to dis-assembler. + +Thu Mar 11 10:52:57 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h (DMGL_NO_OPTS): Add define (set to 0) to use + in place of bare 0, for readability reasons. + +Tue Mar 2 17:50:11 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h: Replace all references to cfront with ARM. + +Tue Feb 23 12:21:14 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for new elements in JUMP_TABLE. + +Tue Feb 16 00:51:30 1993 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update for BFD_VERSION 2.1. + +Tue Jan 26 11:49:20 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for SEC_IS_COMMON flag. + +Tue Jan 19 12:25:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update for bfd_asymbol_value bug fix. + +Fri Jan 8 16:37:18 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update to include ECOFF tdata and target_flavour. + +Sun Dec 27 17:52:30 1992 Fred Fish (fnf@cygnus.com) + + * bfd.h: Add declaration for bfd_get_size(). + +Tue Dec 22 22:42:46 1992 Fred Fish (fnf@cygnus.com) + + * demangle.h: Protect file from multiple inclusions with + #if !defined(DEMANGLE_H)...#define DEMANGLE_H...#endif. + +Mon Dec 21 21:25:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: Update to get hppa_core_struct from bfd.c. + +Thu Dec 17 00:42:35 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to get tekhex tdata name change from bfd. + +Mon Nov 9 23:55:42 1992 John Gilmore (gnu@cygnus.com) + + * ansidecl.h: Update comments to discourage use of EXFUN. + +Thu Nov 5 16:35:44 1992 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update to bring in SEC_SHARED_LIBRARY. + +Thu Nov 5 03:21:32 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to match EXFUN, bfd_seclet_struct, and SDEF + cleanups in bfd. + +Wed Nov 4 07:28:05 1992 Ken Raeburn (raeburn@cygnus.com) + + * bout.h (N_CALLNAME, N_BALNAME): Define as char-type values, so + widening works consistently. + +Fri Oct 16 03:17:08 1992 John Gilmore (gnu@cygnus.com) + + * getopt.h: Update to Revised Standard FSF Version. + +Thu Oct 15 21:43:22 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * getopt.h (struct option): use the provided enum for has_arg. + + * demangle.h (AUTO_DEMANGLING, GNU_DEMANGLING, + LUCID_DEMANGLING): ultrix compilers require enums to be + enums and ints to be ints and casts where they meet. cast some + enums into ints. + +Thu Oct 15 04:35:51 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update after comment changes. + +Thu Oct 8 09:03:02 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h (bfd_get_symbol_leading_char): new macro for getting in xvec + +Thu Sep 3 09:10:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h (struct reloc_howto_struct): size needs to be signed if + it's going to hold negative values. + +Sun Aug 30 17:50:27 1992 Per Bothner (bothner@rtl.cygnus.com) + + * demangle.h: New file, moved from ../gdb. Made independent + of gdb. Allow demangling style option to be passed as a + parameter to cplus_demangle(), but using the + current_demangling_style global as the default. + +Sat Aug 29 10:07:55 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge comment change from current FSF version. + +Thu Aug 27 12:59:29 1992 Brendan Kehoe (brendan@cygnus.com) + + * bfd.h: add we32k + +Tue Aug 25 15:07:47 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after Z8000 stuff + +Mon Aug 17 09:01:23 1992 Ken Raeburn (raeburn@cygnus.com) + + * bfd.h: Regenerated after page/segment size changes. + +Sat Aug 1 13:46:31 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge changes from current FSF version. + +Mon Jul 20 21:06:23 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h (area_id, flags): Remove, replace with extra_arg, + use_extra_arg, and maybe_empty_object. + * obstack.h (OBSTACK_MAYBE_EMPTY_OBJECT, OBSTACK_MMALLOC_LIKE): + Remove, replaced by maybe_empty_object and use_extra_arg bitfields. + * obstack.h (obstack_full_begin, _obstack_begin): Remove area_id + and flags arguments. + * obstack.h (obstack_alloc_arg): New macro to set extra_arg. + +Thu Jul 16 08:12:44 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after adding BFD_IS_RELAXABLE + +Sat Jul 4 03:22:23 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen after adding BSF_FILE. + +Mon Jun 29 14:18:36 1992 Fred Fish (fnf at sunfish) + + * obstack.h: Convert bcopy() use to memcpy(), which is more + portable, more standard, and can take advantage of gcc's builtin + functions for increased performance. + +Thu Jun 25 04:46:08 1992 John Gilmore (gnu at cygnus.com) + + * ansidecl.h (PARAMS): Incorporate this macro from gdb's defs.h. + It's a cleaner way to forward-declare function prototypes. + +Fri Jun 19 15:46:32 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: HPPA merge. + +Tue Jun 16 21:30:56 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: gratuitous white space changes merged from other prep + releases. + +Thu Jun 11 01:10:55 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen'd from bfd.c after removing elf_core_tdata_struct. + +Mon May 18 17:29:03 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from make-3.62.11. + + * getopt.h: merged changes from grep-1.6 (alpha). + +Fri May 8 14:53:32 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from bison-1.18. + +Sat Mar 14 17:25:20 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Add "area_id" and "flags" members to obstack + structure. Add obstack_chunkfun() and obstack_freefun() to + set functions explicitly. Convert maybe_empty_object to + a bit in "flags". + +Thu Feb 27 22:01:02 1992 Per Bothner (bothner@cygnus.com) + + * wait.h (WIFSTOPPED): Add IBM rs6000-specific version. + +Fri Feb 21 20:49:20 1992 John Gilmore (gnu at cygnus.com) + + * obstack.h: Add obstack_full_begin. + * bfd.h, obstack.h: Protolint. + +Thu Jan 30 01:18:42 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Remove comma from enum declaration. + +Mon Jan 27 22:01:13 1992 Steve Chamberlain (sac at cygnus.com) + + * bfd.h : new target entr, bfd_relax_section + +Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) + + * bfd.h, ieee.h: ANSIfy enums. + +Thu Dec 12 20:59:56 1991 John Gilmore (gnu at cygnus.com) + + * fopen-same.h, fopen-bin.h: New files for configuring + whether fopen distinguishes binary files or not. For use + by host-dependent config files. + +Sat Nov 30 20:46:43 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * bfd.h: change the documentation format. + + * created coff, elf and opcode and aout directories. Moved: + + aout64.h ==> aout/aout64.h + ar.h ==> aout/ar.h + a.out.encap.h ==> aout/encap.h + a.out.host.h ==> aout/host.h + a.out.hp.h ==> aout/hp.h + a.out.sun4.h ==> aout/sun4.h + ranlib.h ==> aout/ranlib.h + reloc.h ==> aout/reloc.h + stab.def ==> aout/stab.def + stab.gnu.h ==> aout/stab_gnu.h + + coff-a29k.h ==> coff/a29k.h + coff-h8300.h ==> coff/h8300.h + coff-i386.h ==> coff/i386.h + coff-i960.h ==> coff/i960.h + internalcoff.h ==> coff/internal.h + coff-m68k.h ==> coff/m68k.h + coff-m88k.h ==> coff/m88k.h + coff-mips.h ==> coff/mips.h + coff-rs6000.h ==> coff/rs6000.h + + elf-common.h ==> elf/common.h + dwarf.h ==> elf/dwarf.h + elf-external.h ==> elf/external.h + elf-internal.h ==> elf/internal.h + + a29k-opcode.h ==> opcode/a29k.h + arm-opcode.h ==> opcode/arm.h + h8300-opcode.h ==> opcode/h8300.h + i386-opcode.h ==> opcode/i386.h + i860-opcode.h ==> opcode/i860.h + i960-opcode.h ==> opcode/i960.h + m68k-opcode.h ==> opcode/m68k.h + m88k-opcode.h ==> opcode/m88k.h + mips-opcode.h ==> opcode/mips.h + np1-opcode.h ==> opcode/np1.h + ns32k-opcode.h ==> opcode/ns32k.h + pn-opcode.h ==> opcode/pn.h + pyr-opcode.h ==> opcode/pyr.h + sparc-opcode.h ==> opcode/sparc.h + tahoe-opcode.h ==> opcode/tahoe.h + vax-opcode.h ==> opcode/vax.h + + + +Wed Nov 27 10:38:31 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * internalcoff.h: (internal_scnhdr) took out #def dependency, now + s_nreloc and s_nlnno are always long. (internal_reloc): allways + has an offset field now. + +Fri Nov 22 08:12:58 1991 John Gilmore (gnu at cygnus.com) + + * coff-rs6000.h: Lint; use unsigned chars for external fields. + * internalcoff.h: Lint; cast storage classes to signed char. + +Thu Nov 21 21:01:05 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Remove the GNU extended type codes (e.g. N_SETT). + * aout64.h: The heuristic for distinguishing between + sunos-style and bsd-style ZMAGIC files (wrt. where the + text segment starts) is moved into (the default definition of) + the macro N_HEADER_IN_TEXT. This definition is only used + if no other definition is used - e.g. bfd/newsos3.c defines + N_HEADER_IN_TEXT(x) to be always 0 (as before). + +Thu Nov 21 11:53:03 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h (N_TXTADDR, N_TXTOFF, N_TXTSIZE): New definitions + that should handle all uses. LOGICAL_ versions deleted. + Eliminate N_HEADER_IN_TEXT, using a_entry to determine which + kind of zmagic a.out file we are looking at. + * coff-rs6000.h: Typo. + +Tue Nov 19 18:43:37 1991 Per Bothner (bothner at cygnus.com) + + (Note: This is a revised entry, as was aout64.h.) + * aout64.h: Some cleanups of N_TXTADDR and N_TXTOFF: + Will now work for both old- and new-style ZMAGIC files, + depending on N_HEADER_IN_TEXT macro. + Add LOGICAL_TXTADDR, LOICAL_TXTOFF and LOGICAL_TXTSIZE + that don't count the exec header as part + of the text segment, to be consistent with bfd. + * a.out.sun4.h: Simplified/fixed for previous change. + +Mon Nov 18 00:02:06 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: Update to DWARF draft 5 version from gcc2. + +Thu Nov 14 19:44:59 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Added defs for extended GNU symbol types, + such as N_SETT. These are normally ifdef'd out (because + of conflicts with a.out.gnu.h), but are used by bfb_stab_name(). + +Thu Nov 14 19:17:03 1991 Fred Fish (fnf at cygnus.com) + + * elf-common.h: Add defines to support ELF symbol table code. + +Mon Nov 11 19:01:06 1991 Fred Fish (fnf at cygnus.com) + + * elf-internal.h, elf-external.h, elf-common.h: Add support for + note sections, which are used in ELF core files to hold copies + of various /proc structures. + +Thu Nov 7 08:58:26 1991 Steve Chamberlain (sac at cygnus.com) + + * internalcoff.h: took out the M88 dependency in the lineno + struct. + * coff-m88k.h: defines GET_LINENO_LNNO and PUT_LINENO_LNNO to use + 32bit linno entries. + * a29k-opcode.h: fixed encoding of mtacc + +Sun Nov 3 11:54:22 1991 Per Bothner (bothner at cygnus.com) + + * bfd.h: Updated from ../bfd/bfd-in.h (q.v). + +Fri Nov 1 11:13:53 1991 John Gilmore (gnu at cygnus.com) + + * internalcoff.h: Add x_csect defines. + +Fri Oct 25 03:18:20 1991 John Gilmore (gnu at cygnus.com) + + * Rename COFF-related files in `coff-ARCH.h' form. + coff-a29k.h, coff-i386.h, coff-i960.h, coff-m68k.h, coff-m88k.h, + coff-mips.h, coff-rs6000.h to be exact. + +Thu Oct 24 22:11:11 1991 John Gilmore (gnu at cygnus.com) + + RS/6000 support, by Metin G. Ozisik, Mimi Phûông-ThÃ¥o Võ, and + John Gilmore. + + * a.out.gnu.h: Update slightly. + * bfd.h: Add new error code, fix doc, add bfd_arch_rs6000. + * internalcoff.h: Add more F_ codes for filehdr. Add + rs/6000-dependent fields to aouthdr. Add storage classes + to syments. Add 6000-specific auxent. Add r_size in reloc. + * rs6000coff.c: New file. + +Thu Oct 24 04:13:20 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: New file for dwarf support. Copied from gcc2 + distribution. + +Wed Oct 16 13:31:45 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Remove PAGE_SIZE defines; they are target-dependent. + Add N_FN_SEQ for N_FN symbol type used on Sequent machines. + * stab.def: Include N_FN_SEQ in table. + * bout.h: External formats of structures use unsigned chars. + +Fri Oct 11 12:40:43 1991 Steve Chamberlain (steve at cygnus.com) + + * bfd.h:upgrade from bfd.c + * internalcoff.h: add n_name, n_zeroes and n_offset macros + * amdcoff.h: Define OMAGIC and AOUTHDRSZ. + +Fri Oct 11 10:58:06 1991 Per Bothner (bothner at cygnus.com) + + * a.out.host.h: Change SEGMENT_SIZE to 0x1000 for Sony. + * bfd.h (align_power): Add (actually move) comment. + +Tue Oct 8 15:29:32 1991 Per Bothner (bothner at cygnus.com) + + * sys/h-rtbsd.h: Define MISSING_VFPRINT (for binutils/bucomm.c). + +Sun Oct 6 19:24:39 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Move struct internal_exec to ../bfd/libaout.h so + it can be shared by all `a.out-family' code. Rename + EXTERNAL_LIST_SIZE to EXTERNAL_NLIST_SIZE. Use basic types + for nlist members, and make strx integral rather than pointer. + More commentary on n_type values. + * bout.h: Provide a struct external_exec rather than an + internal_exec. + * m68kcoff.h: Remove `tagentries' which snuck in from the i960 + COFF port. + +Fri Oct 4 01:25:59 1991 John Gilmore (gnu at cygnus.com) + + * h8300-opcode.h: Remove `_enum' from the typedef for an enum. + * bfd.h: Update to match bfd changes. + + * sys/h-i386mach.h, sysdep.h: Add 386 Mach host support. + +Tue Oct 1 04:58:42 1991 John Gilmore (gnu at cygnus.com) + + * bfd.h, elf-common.h, elf-external.h, elf-internal.h: + Add preliminary ELF support, sufficient for GDB, from Fred Fish. + * sysdep.h, sys/h-amix.h: Support Amiga SVR4. + + * sys/h-vaxult.h: Make it work. (David Taylor ) + * a.out.vax.h: Remove unused and confusing file. + +Mon Sep 30 12:52:35 1991 Per Bothner (bothner at cygnus.com) + + * sysdep.h: Define NEWSOS3_SYS, and use it. + +Fri Sep 20 13:38:21 1991 John Gilmore (gnu at cygnus.com) + + * a.out.gnu.h (N_FN): Its value *really is* 0x1F. + Fix it, and add comments warning about or-ing N_EXT with it + and/or N_WARNING. + * aout64.h (N_FN): Fix value, add comments about N_EXT. + * stab.def (table at end): Update to show all the type + values <0x20, including low order bits. Move N_FN to + its rightful place. + +Tue Sep 17 17:41:37 1991 Stu Grossman (grossman at cygnus.com) + + * sys/h-irix3.h: sgi/irix support. + +Tue Sep 17 07:52:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * stab.def (N_DEFD): Add GNU Modula-2 debug stab, from Andrew + Beers. + +Thu Sep 12 14:12:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * internalcoff.h (SYMNMLEN, FILNMLEN, DIMNUM): Define these + for internalcoff, separately from the various external coff's. + * amdcoff.h, bcs88kcoff.h, i386coff.h, intel-coff.h, m68kcoff.h, + m88k-bcs.h: Prefix SYMNMLEN, FILNMLEN, and DIMNUM with E_'s for + the external struct definitions. + * ecoff.h: Remove these #define's, kludge no longer needed. + + * sys/h-ultra3.h: Add new Ultracomputer host. + * sysdep.h: Add ULTRA3_SYM1_SYS and use it. + +Tue Sep 10 10:11:46 1991 John Gilmore (gnu at cygint.cygnus.com) + + * i386coff.h (LINESZ): Always 6, not based on sizeof(). + (Fix from Peter Schauer .) + +Wed Sep 4 08:58:37 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, aout64.h: Add N_WARNING. Change N_FN to 0x0E, + to match SunOS and BSD. Add N_COMM as 0x12 for SunOS shared lib + support. + * stab.def: Add N_COMM to table, fix overlap comment. + +Tue Sep 3 06:29:20 1991 John Gilmore (gnu at cygint.cygnus.com) + + Merge with latest FSF versions of these files. + + * stab.gnu.h: Add LAST_UNUSED_STAB_CODE. + * stab.def: Update to GPL2. Move N_WARNING out, since not a + debug symbol. Change comments, and reorder table to numeric + order. Update final table comment. + (N_DSLINE, N_BSLINE): Renumber from 0x66 and 0x68, to 0x46 and 0x48. + + * obstack.h: GPL2. Merge. + +Fri Aug 23 01:54:23 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, a.out.sun4.h: Make SEGMENT_SIZE able to depend + on the particular a.out being examined. + * a.out.sun4.h: Define segment sizes for Sun-3's and Sun-4's. + * FIXME: a.out.gnu.h is almost obsolete. + * FIXME: a.out.sun4.h should be renamed a.out.sun.h now. + +Wed Aug 21 20:32:13 1991 John Gilmore (gnu at cygint.cygnus.com) + + * Start a ChangeLog for the includes directory. + + * a.out.gnu.h (N_FN): Fix value -- was 15, should be 0x1E. + * stab.def: Update allocation table in comments at end, + to reflect reality as I know it. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/MAINTAINERS b/external/gpl3/gdb/dist/include/MAINTAINERS new file mode 100644 index 000000000000..d59a3bd7f889 --- /dev/null +++ b/external/gpl3/gdb/dist/include/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/external/gpl3/gdb/dist/include/alloca-conf.h b/external/gpl3/gdb/dist/include/alloca-conf.h new file mode 100644 index 000000000000..628a5987e7af --- /dev/null +++ b/external/gpl3/gdb/dist/include/alloca-conf.h @@ -0,0 +1,45 @@ +#include "config.h" + +/* This is a merge of code recommended in the autoconf-2.61 documentation + with that recommended in the autoconf-2.13 documentation, with added + tweaks to heed C_ALLOCA. */ + +#if defined HAVE_ALLOCA_H && !defined C_ALLOCA +# include +#else +# if defined __GNUC__ && !defined C_ALLOCA +# if !defined alloca +# define alloca __builtin_alloca +# endif +# else +# if defined _AIX +/* Indented so that pre-ansi C compilers will ignore it, rather than + choke on it. Some versions of AIX require this to be the first + thing seen by the compiler except for comments and preprocessor + directives. */ + #pragma alloca +# else +# if defined _MSC_VER && !defined C_ALLOCA +# include +# define alloca _alloca +# else +# if !defined alloca +# if defined __STDC__ || defined __hpux +# if defined HAVE_STDDEF_H +# include +# if defined __cplusplus +extern "C" void *alloca (size_t); +# else +extern void *alloca (size_t); +# endif +# else +extern void *alloca (); +# endif +# else +extern char *alloca (); +# endif +# endif +# endif +# endif +# endif +#endif diff --git a/external/gpl3/gdb/dist/include/ansidecl.h b/external/gpl3/gdb/dist/include/ansidecl.h new file mode 100644 index 000000000000..8b76647426bf --- /dev/null +++ b/external/gpl3/gdb/dist/include/ansidecl.h @@ -0,0 +1,423 @@ +/* ANSI and traditional C compatability macros + Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, + 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010 + Free Software Foundation, Inc. + This file is part of the GNU C Library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ANSI and traditional C compatibility macros + + ANSI C is assumed if __STDC__ is #defined. + + Macro ANSI C definition Traditional C definition + ----- ---- - ---------- ----------- - ---------- + ANSI_PROTOTYPES 1 not defined + PTR `void *' `char *' + PTRCONST `void *const' `char *' + LONG_DOUBLE `long double' `double' + const not defined `' + volatile not defined `' + signed not defined `' + VA_START(ap, var) va_start(ap, var) va_start(ap) + + Note that it is safe to write "void foo();" indicating a function + with no return value, in all K+R compilers we have been able to test. + + For declaring functions with prototypes, we also provide these: + + PARAMS ((prototype)) + -- for functions which take a fixed number of arguments. Use this + when declaring the function. When defining the function, write a + K+R style argument list. For example: + + char *strcpy PARAMS ((char *dest, char *source)); + ... + char * + strcpy (dest, source) + char *dest; + char *source; + { ... } + + + VPARAMS ((prototype, ...)) + -- for functions which take a variable number of arguments. Use + PARAMS to declare the function, VPARAMS to define it. For example: + + int printf PARAMS ((const char *format, ...)); + ... + int + printf VPARAMS ((const char *format, ...)) + { + ... + } + + For writing functions which take variable numbers of arguments, we + also provide the VA_OPEN, VA_CLOSE, and VA_FIXEDARG macros. These + hide the differences between K+R and C89 more + thoroughly than the simple VA_START() macro mentioned above. + + VA_OPEN and VA_CLOSE are used *instead of* va_start and va_end. + Immediately after VA_OPEN, put a sequence of VA_FIXEDARG calls + corresponding to the list of fixed arguments. Then use va_arg + normally to get the variable arguments, or pass your va_list object + around. You do not declare the va_list yourself; VA_OPEN does it + for you. + + Here is a complete example: + + int + printf VPARAMS ((const char *format, ...)) + { + int result; + + VA_OPEN (ap, format); + VA_FIXEDARG (ap, const char *, format); + + result = vfprintf (stdout, format, ap); + VA_CLOSE (ap); + + return result; + } + + + You can declare variables either before or after the VA_OPEN, + VA_FIXEDARG sequence. Also, VA_OPEN and VA_CLOSE are the beginning + and end of a block. They must appear at the same nesting level, + and any variables declared after VA_OPEN go out of scope at + VA_CLOSE. Unfortunately, with a K+R compiler, that includes the + argument list. You can have multiple instances of VA_OPEN/VA_CLOSE + pairs in a single function in case you need to traverse the + argument list more than once. + + For ease of writing code which uses GCC extensions but needs to be + portable to other compilers, we provide the GCC_VERSION macro that + simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various + wrappers around __attribute__. Also, __extension__ will be #defined + to nothing if it doesn't work. See below. + + This header also defines a lot of obsolete macros: + CONST, VOLATILE, SIGNED, PROTO, EXFUN, DEFUN, DEFUN_VOID, + AND, DOTS, NOARGS. Don't use them. */ + +#ifndef _ANSIDECL_H +#define _ANSIDECL_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* Every source file includes this file, + so they will all get the switch for lint. */ +/* LINTLIBRARY */ + +/* Using MACRO(x,y) in cpp #if conditionals does not work with some + older preprocessors. Thus we can't define something like this: + +#define HAVE_GCC_VERSION(MAJOR, MINOR) \ + (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) + +and then test "#if HAVE_GCC_VERSION(2,7)". + +So instead we use the macro below and test it against specific values. */ + +/* This macro simplifies testing whether we are using gcc, and if it + is of a particular minimum version. (Both major & minor numbers are + significant.) This macro will evaluate to 0 if we are not using + gcc at all. */ +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif /* GCC_VERSION */ + +#if defined (__STDC__) || defined(__cplusplus) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) +/* All known AIX compilers implement these things (but don't always + define __STDC__). The RISC/OS MIPS compiler defines these things + in SVR4 mode, but does not define __STDC__. */ +/* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other + C++ compilers, does not define __STDC__, though it acts as if this + was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ + +#define ANSI_PROTOTYPES 1 +#define PTR void * +#define PTRCONST void *const +#define LONG_DOUBLE long double + +/* PARAMS is often defined elsewhere (e.g. by libintl.h), so wrap it in + a #ifndef. */ +#ifndef PARAMS +#define PARAMS(ARGS) ARGS +#endif + +#define VPARAMS(ARGS) ARGS +#define VA_START(VA_LIST, VAR) va_start(VA_LIST, VAR) + +/* variadic function helper macros */ +/* "struct Qdmy" swallows the semicolon after VA_OPEN/VA_FIXEDARG's + use without inhibiting further decls and without declaring an + actual variable. */ +#define VA_OPEN(AP, VAR) { va_list AP; va_start(AP, VAR); { struct Qdmy +#define VA_CLOSE(AP) } va_end(AP); } +#define VA_FIXEDARG(AP, T, N) struct Qdmy + +#undef const +#undef volatile +#undef signed + +/* inline requires special treatment; it's in C99, and GCC >=2.7 supports + it too, but it's not in C89. */ +#undef inline +#if __STDC_VERSION__ >= 199901L || defined(__cplusplus) || (defined(__SUNPRO_C) && defined(__C99FEATURES__)) +/* it's a keyword */ +#else +# if GCC_VERSION >= 2007 +# define inline __inline__ /* __inline__ prevents -pedantic warnings */ +# else +# define inline /* nothing */ +# endif +#endif + +/* These are obsolete. Do not use. */ +#ifndef IN_GCC +#define CONST const +#define VOLATILE volatile +#define SIGNED signed + +#define PROTO(type, name, arglist) type name arglist +#define EXFUN(name, proto) name proto +#define DEFUN(name, arglist, args) name(args) +#define DEFUN_VOID(name) name(void) +#define AND , +#define DOTS , ... +#define NOARGS void +#endif /* ! IN_GCC */ + +#else /* Not ANSI C. */ + +#undef ANSI_PROTOTYPES +#define PTR char * +#define PTRCONST PTR +#define LONG_DOUBLE double + +#define PARAMS(args) () +#define VPARAMS(args) (va_alist) va_dcl +#define VA_START(va_list, var) va_start(va_list) + +#define VA_OPEN(AP, VAR) { va_list AP; va_start(AP); { struct Qdmy +#define VA_CLOSE(AP) } va_end(AP); } +#define VA_FIXEDARG(AP, TYPE, NAME) TYPE NAME = va_arg(AP, TYPE) + +/* some systems define these in header files for non-ansi mode */ +#undef const +#undef volatile +#undef signed +#undef inline +#define const +#define volatile +#define signed +#define inline + +#ifndef IN_GCC +#define CONST +#define VOLATILE +#define SIGNED + +#define PROTO(type, name, arglist) type name () +#define EXFUN(name, proto) name() +#define DEFUN(name, arglist, args) name arglist args; +#define DEFUN_VOID(name) name() +#define AND ; +#define DOTS +#define NOARGS +#endif /* ! IN_GCC */ + +#endif /* ANSI C. */ + +/* Define macros for some gcc attributes. This permits us to use the + macros freely, and know that they will come into play for the + version of gcc in which they are supported. */ + +#if (GCC_VERSION < 2007) +# define __attribute__(x) +#endif + +/* Attribute __malloc__ on functions was valid as of gcc 2.96. */ +#ifndef ATTRIBUTE_MALLOC +# if (GCC_VERSION >= 2096) +# define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) +# else +# define ATTRIBUTE_MALLOC +# endif /* GNUC >= 2.96 */ +#endif /* ATTRIBUTE_MALLOC */ + +/* Attributes on labels were valid as of gcc 2.93 and g++ 4.5. For + g++ an attribute on a label must be followed by a semicolon. */ +#ifndef ATTRIBUTE_UNUSED_LABEL +# ifndef __cplusplus +# if GCC_VERSION >= 2093 +# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED +# else +# define ATTRIBUTE_UNUSED_LABEL +# endif +# else +# if GCC_VERSION >= 4005 +# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED ; +# else +# define ATTRIBUTE_UNUSED_LABEL +# endif +# endif +#endif + +#ifndef ATTRIBUTE_UNUSED +#define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) +#endif /* ATTRIBUTE_UNUSED */ + +/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the + identifier name. */ +#if ! defined(__cplusplus) || (GCC_VERSION >= 3004) +# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED +#else /* !__cplusplus || GNUC >= 3.4 */ +# define ARG_UNUSED(NAME) NAME +#endif /* !__cplusplus || GNUC >= 3.4 */ + +#ifndef ATTRIBUTE_NORETURN +#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) +#endif /* ATTRIBUTE_NORETURN */ + +/* Attribute `nonnull' was valid as of gcc 3.3. */ +#ifndef ATTRIBUTE_NONNULL +# if (GCC_VERSION >= 3003) +# define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) +# else +# define ATTRIBUTE_NONNULL(m) +# endif /* GNUC >= 3.3 */ +#endif /* ATTRIBUTE_NONNULL */ + +/* Attribute `pure' was valid as of gcc 3.0. */ +#ifndef ATTRIBUTE_PURE +# if (GCC_VERSION >= 3000) +# define ATTRIBUTE_PURE __attribute__ ((__pure__)) +# else +# define ATTRIBUTE_PURE +# endif /* GNUC >= 3.0 */ +#endif /* ATTRIBUTE_PURE */ + +/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. + This was the case for the `printf' format attribute by itself + before GCC 3.3, but as of 3.3 we need to add the `nonnull' + attribute to retain this behavior. */ +#ifndef ATTRIBUTE_PRINTF +#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) +#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) +#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) +#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) +#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) +#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) +#endif /* ATTRIBUTE_PRINTF */ + +/* Use ATTRIBUTE_FPTR_PRINTF when the format attribute is to be set on + a function pointer. Format attributes were allowed on function + pointers as of gcc 3.1. */ +#ifndef ATTRIBUTE_FPTR_PRINTF +# if (GCC_VERSION >= 3001) +# define ATTRIBUTE_FPTR_PRINTF(m, n) ATTRIBUTE_PRINTF(m, n) +# else +# define ATTRIBUTE_FPTR_PRINTF(m, n) +# endif /* GNUC >= 3.1 */ +# define ATTRIBUTE_FPTR_PRINTF_1 ATTRIBUTE_FPTR_PRINTF(1, 2) +# define ATTRIBUTE_FPTR_PRINTF_2 ATTRIBUTE_FPTR_PRINTF(2, 3) +# define ATTRIBUTE_FPTR_PRINTF_3 ATTRIBUTE_FPTR_PRINTF(3, 4) +# define ATTRIBUTE_FPTR_PRINTF_4 ATTRIBUTE_FPTR_PRINTF(4, 5) +# define ATTRIBUTE_FPTR_PRINTF_5 ATTRIBUTE_FPTR_PRINTF(5, 6) +#endif /* ATTRIBUTE_FPTR_PRINTF */ + +/* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A + NULL format specifier was allowed as of gcc 3.3. */ +#ifndef ATTRIBUTE_NULL_PRINTF +# if (GCC_VERSION >= 3003) +# define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) +# else +# define ATTRIBUTE_NULL_PRINTF(m, n) +# endif /* GNUC >= 3.3 */ +# define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) +# define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) +# define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) +# define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) +# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) +#endif /* ATTRIBUTE_NULL_PRINTF */ + +/* Attribute `sentinel' was valid as of gcc 3.5. */ +#ifndef ATTRIBUTE_SENTINEL +# if (GCC_VERSION >= 3005) +# define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__)) +# else +# define ATTRIBUTE_SENTINEL +# endif /* GNUC >= 3.5 */ +#endif /* ATTRIBUTE_SENTINEL */ + + +#ifndef ATTRIBUTE_ALIGNED_ALIGNOF +# if (GCC_VERSION >= 3000) +# define ATTRIBUTE_ALIGNED_ALIGNOF(m) __attribute__ ((__aligned__ (__alignof__ (m)))) +# else +# define ATTRIBUTE_ALIGNED_ALIGNOF(m) +# endif /* GNUC >= 3.0 */ +#endif /* ATTRIBUTE_ALIGNED_ALIGNOF */ + +/* Useful for structures whose layout must much some binary specification + regardless of the alignment and padding qualities of the compiler. */ +#ifndef ATTRIBUTE_PACKED +# define ATTRIBUTE_PACKED __attribute__ ((packed)) +#endif + +/* Attribute `hot' and `cold' was valid as of gcc 4.3. */ +#ifndef ATTRIBUTE_COLD +# if (GCC_VERSION >= 4003) +# define ATTRIBUTE_COLD __attribute__ ((__cold__)) +# else +# define ATTRIBUTE_COLD +# endif /* GNUC >= 4.3 */ +#endif /* ATTRIBUTE_COLD */ +#ifndef ATTRIBUTE_HOT +# if (GCC_VERSION >= 4003) +# define ATTRIBUTE_HOT __attribute__ ((__hot__)) +# else +# define ATTRIBUTE_HOT +# endif /* GNUC >= 4.3 */ +#endif /* ATTRIBUTE_HOT */ + +/* We use __extension__ in some places to suppress -pedantic warnings + about GCC extensions. This feature didn't work properly before + gcc 2.8. */ +#if GCC_VERSION < 2008 +#define __extension__ +#endif + +/* This is used to declare a const variable which should be visible + outside of the current compilation unit. Use it as + EXPORTED_CONST int i = 1; + This is because the semantics of const are different in C and C++. + "extern const" is permitted in C but it looks strange, and gcc + warns about it when -Wc++-compat is not used. */ +#ifdef __cplusplus +#define EXPORTED_CONST extern const +#else +#define EXPORTED_CONST const +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ansidecl.h */ diff --git a/external/gpl3/gdb/dist/include/aout/ChangeLog b/external/gpl3/gdb/dist/include/aout/ChangeLog new file mode 100644 index 000000000000..f3a5b86229ad --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/ChangeLog @@ -0,0 +1,253 @@ +2010-04-15 Nick Clifton + + * adobe.h: Update copyright notice to use GPLv3. + * aout64.h: Likewise. + * ar.h: Likewise. + * dynix3.h: Likewise. + * encap.h: Likewise. + * host.h: Likewise. + * hp.h: Likewise. + * hp300hpux.h: Likewise. + * ranlib.h: Likewise. + * reloc.h: Likewise. + * stab.def: Likewise. + * stab_gnu.h: Likewise. + * sun4.h: Likewise. + +2009-10-02 Alan Modra + + * aout64.h (N_SHARED_LIB): Define as zero if not already defined. + * sun4.h (N_SHARED_LIB): Define. + * hp300hpux.h (N_SHARED_LIB): Don't define. + +2008-08-28 Tristan Gingold + + * stab.def: Add BNSYM, ENSYM, OSO for darwin. + +2008-03-27 Cary Coutant + + * ar.h (ARMAGT): New magic string for thin archives. + +2005-08-18 Alan Modra + + * encap.h: Remove a29k support. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + adobe.h, aout64.h, ar.h, dynix3.h, encap.h, host.h, hp.h, + ranlib.h, reloc.h, stab.def, stab_gnu.h, sun4.h + +2004-01-06 Mark Kettenis + + * stab.def: Add N_PATCH to DO definition. + +2003-03-06 Elias Athanasopoulos + + * aout64.h (BYTES_IN_WORD): Define if necessary. + +2001-09-18 Alan Modra + + * aout64.h: Formatting fixes. + (N_TXTADDR): Evaluate to a bfd_vma. + (N_DATADDR): Avoid negative unsigned warning. + * hp300hpux.h: Formatting fixes. + (N_DATADDR): Avoid negative unsigned warning. + +2000-04-03 Hans-Peter Nilsson + + * aout64.h (RELOC_EXT_BITS_EXTERN_BIG): Wrap definition in #ifndef. + (RELOC_EXT_BITS_EXTERN_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_SH_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_SH_LITTLE): Ditto. + +1999-07-12 Ian Lance Taylor + + * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is + defined as 0. + +1998-06-28 Peter Schauer + + * stab.def: Add N_ALIAS from SunPro F77. + +1996-03-11 Ian Lance Taylor + + * stab.def: Use __define_stab_duplicate rather than __define_stab + for duplicate entries N_BROWS and N_MOD2. + * stab_gnu.h (__define_stab_duplicate): Define before including + stab.def. + +1995-10-27 Niklas Hallqvist + + * aout64.h, host.h, hp300hpux.h, sun4.h: Changed PAGE_SIZE to + TARGET_PAGE_SIZE. + +1995-09-12 Ian Lance Taylor + + * sun4.h (struct internal_sun4_dynamic_link): Change all fields + from long to unsigned long. + +1995-07-12 Ken Raeburn + + * sun4.h (PAGE_SIZE): Undefine before defining. + +1994-09-04 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * aout64.h: Only define QMAGIC if it isn't already defined. + +1994-06-16 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * aout64.h (BMAGIC): Define. + +1994-06-11 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + Add weak symbols as an extension to a.out. + * aout64.h (N_WEAKU, N_WEAKA, N_WEAKT, N_WEAKD, N_WEAKB): Define. + * stab.def: Update symbol value table. + +1994-06-02 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * sun4.h (EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE): Correct from 28 to + 24. Fix up ld_got comment. + +1994-03-30 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * dynix3.h: Cleanup, adapt to current bfd version. + +1994-02-26 Ian Lance Taylor (ian@cygnus.com) + + * aout64.h: Add casts to avoid warnings from SVR4 cc. + +1994-02-11 Stan Shebs (shebs@andros.cygnus.com) + + * ar.h (ARMAG, ARMAGB, ARFMAG): Change '\n' to '\012', for greater + portability. + +1994-01-21 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * sun4.h: Added information about SunOS shared libraries. + +1994-01-07 Jim Kingdon (kingdon@deneb.cygnus.com) + + * aout64.h (N_TXTADDR): Add comment regarding OMAGIC and NMAGIC. + +1993-12-25 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h (N_DATOFF): Don't pad (revert change of 8 Jul 1993). + +1993-11-16 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h: New macros ZMAGIC_DISK_BLOCK_SIZE and N_DISK_BLOCK_SIZE + for Linux ZMAGIC. + (N_TXTOFF, N_DATOFF): Use them. + +1993-11-04 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * aout64.h (RELOC_STD_BITS_RELATIVE_LITTLE): Fixed value to match + sun3 system; used to overlap other fields. + (RELOC_STD_BITS_JMPTABLE_LITTLE): Likewise. + +1993-11-03 David J. Mackenzie (djm@thepub.cygnus.com) + + * aout64.h (RELOC_STD_BITS_BASEREL_LITTLE): Make it 0x10 (Ken's + suggestion) to avoid conflict with RELOC_STD_BITS_EXTERN_LITTLE. + +1993-10-29 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * hp300hpux.h (N_SHARED_LIB): Define to be 0. + +1993-09-13 John Gilmore (gnu@cygnus.com) + + * ar.h (ARMAP_TIME_OFFSET): Add and describe. + +Mon Aug 23 Sean Fagan (sef@cygnus.com) + + * aout64.h [ARCH_SIZE != 64]: Allow N_BADMAG to be overridden. + +1993-08-16 Jim Kingdon (kingdon@lioth.cygnus.com) + + * stab_gnu.h: Include aout/stab.def not just stab.def. + +1993-07-18 Jim Kingdon (kingdon@rtl.cygnus.com) + + * dynix3.h: New, for symmetry running dynix. + +1993-07-08 Jim Kingdon (kingdon@lioth.cygnus.com) + + * aout64.h (N_BADMAG): Recognize QMAGIC. + N_TXTOFF, N_TXTADDR, N_TXTSIZE: Special code for QMAGIC. + N_DATOFF: Pad text size if we need to. + +1993-06-18 Jim Kingdon (kingdon@lioth.cygnus.com) + + * stab.def (N_ECOML): Fix comment. + +1993-05-31 Jim Kingdon (kingdon@cygnus.com) + + * stab.def: Remove Solaris information on N_FUN stabstring grammar; + I've transferred it to gdb/doc/stabs.texinfo, where it belongs. + +1993-05-10 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * hp300hpux.h: Patch from Glenn Engel for linker problem and + compatibility fix: + (OMAGIC, NMAGIC): New definitions. + (SHAREMAGIC): Deleted. + (HPUX_DOT_O_MAGIC): New macro. + (_N_BADMAG): Adjusted. + (N_HEADER_IN_TEXT, N_DATADDR): New macros. + +1993-04-29 Ken Raeburn (raeburn@deneb.cygnus.com) + + * hp300hpux.h: New file from Glenn Engel, glenne@lsid.hp.com. + +1993-04-27 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * aout64.h (struct external_exec, *MAGIC, N_BADMAG): Don't define + if `external_exec' is already defined as a macro. + (N_DATOFF, N_TRELOFF, N_DRELOFF, N_SYMOFF, N_STROFF): Don't define + if already defined. + (struct external_nlist, EXTERNAL_NLIST_SIZE): Don't define if + `external_nlist' is already defined as a macro. + +1992-08-15 John Gilmore (gnu@cygnus.com) + + * adobe.h: Add description of a.out.adobe format. + +1992-07-03 John Gilmore (gnu at cygnus.com) + + * stab.def: Update more Solaris definitions. + * stab_gnu.h: Add N_SO language types, and Solaris basic float types. + +1992-06-14 John Gilmore (gnu at cygnus.com) + + * stab.def: Update descriptions of Solaris-2 stabs; add N_UNDF. + +1992-06-11 John Gilmore (gnu at cygnus.com) + + * stab.def: Add N_OBJ and N_OPT from Solaris-2. + +1992-01-30 John Gilmore (gnu at cygnus.com) + + * aout64.h: N_TXTSIZE needs some more parentheses. + I don't trust C precedence. + +1991-12-18 Per Bothner (bothner at cygnus.com) + + * aout64.h: Move common sunos-specific test + to recognize shared libraries into new macro N_SHARED_LIB. + Use it to simplify & reformat N_TXTADDR, N_TXTOFF, N_TXTSIZE. + +1991-11-30 Steve Chamberlain (sac at rtl.cygnus.com) + + * aout64.h, ar.h, encap.h, host.h, hp.h, ranlib.h, reloc.h, + stab.def, stab_gnu.h, sun4.h: All moved from the devo/include + directory. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/aout/adobe.h b/external/gpl3/gdb/dist/include/aout/adobe.h new file mode 100644 index 000000000000..ce225527787f --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/adobe.h @@ -0,0 +1,314 @@ +/* `a.out.adobe' differences from standard a.out files + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef __A_OUT_ADOBE_H__ +#define __A_OUT_ADOBE_H__ + +#define BYTES_IN_WORD 4 + +/* Struct external_exec is the same. */ + +/* This is the layout on disk of the 32-bit or 64-bit exec header. */ + +struct external_exec +{ + bfd_byte e_info[4]; /* magic number and stuff */ + bfd_byte e_text[BYTES_IN_WORD]; /* length of text section in bytes */ + bfd_byte e_data[BYTES_IN_WORD]; /* length of data section in bytes */ + bfd_byte e_bss[BYTES_IN_WORD]; /* length of bss area in bytes */ + bfd_byte e_syms[BYTES_IN_WORD]; /* length of symbol table in bytes */ + bfd_byte e_entry[BYTES_IN_WORD]; /* start address */ + bfd_byte e_trsize[BYTES_IN_WORD]; /* length of text relocation info */ + bfd_byte e_drsize[BYTES_IN_WORD]; /* length of data relocation info */ +}; + +#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7) + +/* Magic numbers for a.out files */ + +#undef ZMAGIC +#define ZMAGIC 0xAD0BE /* Cute, eh? */ +#undef OMAGIC +#undef NMAGIC + +#define N_BADMAG(x) ((x).a_info != ZMAGIC) + +/* By default, segment size is constant. But some machines override this + to be a function of the a.out header (e.g. machine type). */ +#ifndef N_SEGSIZE +#define N_SEGSIZE(x) SEGMENT_SIZE +#endif +#undef N_SEGSIZE /* FIXMEXXXX */ + +/* Segment information for the a.out.Adobe format is specified after the + file header. It contains N segment descriptors, followed by one with + a type of zero. + + The actual text of the segments starts at N_TXTOFF in the file, + regardless of how many or how few segment headers there are. */ + +struct external_segdesc { + unsigned char e_type[1]; + unsigned char e_size[3]; + unsigned char e_virtbase[4]; + unsigned char e_filebase[4]; +}; + +struct internal_segdesc { + unsigned int a_type:8; /* Segment type N_TEXT, N_DATA, 0 */ + unsigned int a_size:24; /* Segment size */ + bfd_vma a_virtbase; /* Virtual address */ + unsigned int a_filebase; /* Base address in object file */ +}; + +#define N_TXTADDR(x) \ + +/* This is documented to be at 1024, but appears to really be at 2048. + FIXME?! */ +#define N_TXTOFF(x) 2048 + +#define N_TXTSIZE(x) ((x).a_text) + +#define N_DATADDR(x) + +#define N_BSSADDR(x) + +/* Offsets of the various portions of the file after the text segment. */ + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_TRELOFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_SYMOFF(x) ( N_DRELOFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) + +/* Symbols */ +struct external_nlist { + bfd_byte e_strx[BYTES_IN_WORD]; /* index into string table of name */ + bfd_byte e_type[1]; /* type of symbol */ + bfd_byte e_other[1]; /* misc info (usually empty) */ + bfd_byte e_desc[2]; /* description field */ + bfd_byte e_value[BYTES_IN_WORD]; /* value of symbol */ +}; + +#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD) + +struct internal_nlist { + unsigned long n_strx; /* index into string table of name */ + unsigned char n_type; /* type of symbol */ + unsigned char n_other; /* misc info (usually empty) */ + unsigned short n_desc; /* description field */ + bfd_vma n_value; /* value of symbol */ +}; + +/* The n_type field is the symbol type, containing: */ + +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol -- defined at particular addr */ +#define N_TEXT 4 /* Text sym -- defined at offset in text seg */ +#define N_DATA 6 /* Data sym -- defined at offset in data seg */ +#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg */ +#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink) */ +#define N_FN 0x1f /* File name of .o file */ +#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh) */ +/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT, + N_DATA, or N_BSS. When the low-order bit of other types is set, + (e.g. N_WARNING versus N_FN), they are two different types. */ +#define N_EXT 1 /* External symbol (as opposed to local-to-this-file) */ +#define N_TYPE 0x1e +#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol */ + +#define N_INDR 0x0a + +/* The following symbols refer to set elements. + All the N_SET[ATDB] symbols with the same name form one set. + Space is allocated for the set in the text section, and each set + elements value is stored into one word of the space. + The first word of the space is the length of the set (number of elements). + + The address of the set is made into an N_SETV symbol + whose name is the same as the name of the set. + This symbol acts like a N_DATA global symbol + in that it can satisfy undefined external references. */ + +/* These appear as input to LD, in a .o file. */ +#define N_SETA 0x14 /* Absolute set element symbol */ +#define N_SETT 0x16 /* Text set element symbol */ +#define N_SETD 0x18 /* Data set element symbol */ +#define N_SETB 0x1A /* Bss set element symbol */ + +/* This is output from LD. */ +#define N_SETV 0x1C /* Pointer to set vector in data area. */ + +/* Warning symbol. The text gives a warning message, the next symbol + in the table will be undefined. When the symbol is referenced, the + message is printed. */ + +#define N_WARNING 0x1e + +/* Relocations + + There are two types of relocation flavours for a.out systems, + standard and extended. The standard form is used on systems where the + instruction has room for all the bits of an offset to the operand, whilst + the extended form is used when an address operand has to be split over n + instructions. Eg, on the 68k, each move instruction can reference + the target with a displacement of 16 or 32 bits. On the sparc, move + instructions use an offset of 14 bits, so the offset is stored in + the reloc field, and the data in the section is ignored. +*/ + +/* This structure describes a single relocation to be performed. + The text-relocation section of the file is a vector of these structures, + all of which apply to the text section. + Likewise, the data-relocation section applies to the data section. */ + +struct reloc_std_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ +}; + +#define RELOC_STD_BITS_PCREL_BIG 0x80 +#define RELOC_STD_BITS_PCREL_LITTLE 0x01 + +#define RELOC_STD_BITS_LENGTH_BIG 0x60 +#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */ +#define RELOC_STD_BITS_LENGTH_LITTLE 0x06 +#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 + +#define RELOC_STD_BITS_EXTERN_BIG 0x10 +#define RELOC_STD_BITS_EXTERN_LITTLE 0x08 + +#define RELOC_STD_BITS_BASEREL_BIG 0x08 +#define RELOC_STD_BITS_BASEREL_LITTLE 0x08 + +#define RELOC_STD_BITS_JMPTABLE_BIG 0x04 +#define RELOC_STD_BITS_JMPTABLE_LITTLE 0x04 + +#define RELOC_STD_BITS_RELATIVE_BIG 0x02 +#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02 + +#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry */ + +struct reloc_std_internal +{ + bfd_vma r_address; /* Address (within segment) to be relocated. */ + /* The meaning of r_symbolnum depends on r_extern. */ + unsigned int r_symbolnum:24; + /* Nonzero means value is a pc-relative offset + and it should be relocated for changes in its own address + as well as for changes in the symbol or section specified. */ + unsigned int r_pcrel:1; + /* Length (as exponent of 2) of the field to be relocated. + Thus, a value of 2 indicates 1<<2 bytes. */ + unsigned int r_length:2; + /* 1 => relocate with value of symbol. + r_symbolnum is the index of the symbol + in files the symbol table. + 0 => relocate with the address of a segment. + r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS + (the N_EXT bit may be set also, but signifies nothing). */ + unsigned int r_extern:1; + /* The next three bits are for SunOS shared libraries, and seem to + be undocumented. */ + unsigned int r_baserel:1; /* Linkage table relative */ + unsigned int r_jmptable:1; /* pc-relative to jump table */ + unsigned int r_relative:1; /* "relative relocation" */ + /* unused */ + unsigned int r_pad:1; /* Padding -- set to zero */ +}; + + +/* EXTENDED RELOCS */ + +struct reloc_ext_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ + bfd_byte r_addend[BYTES_IN_WORD]; /* datum addend */ +}; + +#define RELOC_EXT_BITS_EXTERN_BIG 0x80 +#define RELOC_EXT_BITS_EXTERN_LITTLE 0x01 + +#define RELOC_EXT_BITS_TYPE_BIG 0x1F +#define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#define RELOC_EXT_BITS_TYPE_LITTLE 0xF8 +#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 + +/* Bytes per relocation entry */ +#define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) + +enum reloc_type +{ + /* simple relocations */ + RELOC_8, /* data[0:7] = addend + sv */ + RELOC_16, /* data[0:15] = addend + sv */ + RELOC_32, /* data[0:31] = addend + sv */ + /* pc-rel displacement */ + RELOC_DISP8, /* data[0:7] = addend - pc + sv */ + RELOC_DISP16, /* data[0:15] = addend - pc + sv */ + RELOC_DISP32, /* data[0:31] = addend - pc + sv */ + /* Special */ + RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */ + RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */ + RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */ + RELOC_22, /* data[0:21] = (addend + sv) */ + RELOC_13, /* data[0:12] = (addend + sv) */ + RELOC_LO10, /* data[0:9] = (addend + sv) */ + RELOC_SFA_BASE, + RELOC_SFA_OFF13, + /* P.I.C. (base-relative) */ + RELOC_BASE10, /* Not sure - maybe we can do this the */ + RELOC_BASE13, /* right way now */ + RELOC_BASE22, + /* for some sort of pc-rel P.I.C. (?) */ + RELOC_PC10, + RELOC_PC22, + /* P.I.C. jump table */ + RELOC_JMP_TBL, + /* reputedly for shared libraries somehow */ + RELOC_SEGOFF16, + RELOC_GLOB_DAT, + RELOC_JMP_SLOT, + RELOC_RELATIVE, + + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, /* data[0:21] = (addend + sv) >> 42 */ + RELOC_HLO10, /* data[0:9] = (addend + sv) >> 32 */ + + /* 29K relocation types */ + RELOC_JUMPTARG, + RELOC_CONST, + RELOC_CONSTH, + + NO_RELOC + }; + + +struct reloc_internal { + bfd_vma r_address; /* offset of of data to relocate */ + long r_index; /* symbol table index of symbol */ + enum reloc_type r_type; /* relocation type */ + bfd_vma r_addend; /* datum addend */ +}; + +#endif /* __A_OUT_ADOBE_H__ */ diff --git a/external/gpl3/gdb/dist/include/aout/aout64.h b/external/gpl3/gdb/dist/include/aout/aout64.h new file mode 100644 index 000000000000..384909e05e76 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/aout64.h @@ -0,0 +1,516 @@ +/* `a.out' object-file definitions, including extensions to 64-bit fields + + Copyright 1999, 2000, 2001, 2003, 2009, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef __A_OUT_64_H__ +#define __A_OUT_64_H__ + +#ifndef BYTES_IN_WORD +#define BYTES_IN_WORD 4 +#endif + +/* This is the layout on disk of the 32-bit or 64-bit exec header. */ + +#ifndef external_exec +struct external_exec +{ + bfd_byte e_info[4]; /* Magic number and stuff. */ + bfd_byte e_text[BYTES_IN_WORD]; /* Length of text section in bytes. */ + bfd_byte e_data[BYTES_IN_WORD]; /* Length of data section in bytes. */ + bfd_byte e_bss[BYTES_IN_WORD]; /* Length of bss area in bytes. */ + bfd_byte e_syms[BYTES_IN_WORD]; /* Length of symbol table in bytes. */ + bfd_byte e_entry[BYTES_IN_WORD]; /* Start address. */ + bfd_byte e_trsize[BYTES_IN_WORD]; /* Length of text relocation info. */ + bfd_byte e_drsize[BYTES_IN_WORD]; /* Length of data relocation info. */ +}; + +#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7) + +/* Magic numbers for a.out files. */ + +#if ARCH_SIZE==64 +#define OMAGIC 0x1001 /* Code indicating object file. */ +#define ZMAGIC 0x1002 /* Code indicating demand-paged executable. */ +#define NMAGIC 0x1003 /* Code indicating pure executable. */ + +/* There is no 64-bit QMAGIC as far as I know. */ + +#define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC) +#else +#define OMAGIC 0407 /* Object file or impure executable. */ +#define NMAGIC 0410 /* Code indicating pure executable. */ +#define ZMAGIC 0413 /* Code indicating demand-paged executable. */ +#define BMAGIC 0415 /* Used by a b.out object. */ + +/* This indicates a demand-paged executable with the header in the text. + It is used by 386BSD (and variants) and Linux, at least. */ +#ifndef QMAGIC +#define QMAGIC 0314 +#endif +# ifndef N_BADMAG +# define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC \ + && N_MAGIC(x) != QMAGIC) +# endif /* N_BADMAG */ +#endif + +#endif + +#ifdef QMAGIC +#define N_IS_QMAGIC(x) (N_MAGIC (x) == QMAGIC) +#else +#define N_IS_QMAGIC(x) (0) +#endif + +/* The difference between TARGET_PAGE_SIZE and N_SEGSIZE is that TARGET_PAGE_SIZE is + the finest granularity at which you can page something, thus it + controls the padding (if any) before the text segment of a ZMAGIC + file. N_SEGSIZE is the resolution at which things can be marked as + read-only versus read/write, so it controls the padding between the + text segment and the data segment (in memory; on disk the padding + between them is TARGET_PAGE_SIZE). TARGET_PAGE_SIZE and N_SEGSIZE are the same + for most machines, but different for sun3. */ + +/* By default, segment size is constant. But some machines override this + to be a function of the a.out header (e.g. machine type). */ + +#ifndef N_SEGSIZE +#define N_SEGSIZE(x) SEGMENT_SIZE +#endif + +/* Virtual memory address of the text section. + This is getting very complicated. A good reason to discard a.out format + for something that specifies these fields explicitly. But til then... + + * OMAGIC and NMAGIC files: + (object files: text for "relocatable addr 0" right after the header) + start at 0, offset is EXEC_BYTES_SIZE, size as stated. + * The text address, offset, and size of ZMAGIC files depend + on the entry point of the file: + * entry point below TEXT_START_ADDR: + (hack for SunOS shared libraries) + start at 0, offset is 0, size as stated. + * If N_HEADER_IN_TEXT(x) is true (which defaults to being the + case when the entry point is EXEC_BYTES_SIZE or further into a page): + no padding is needed; text can start after exec header. Sun + considers the text segment of such files to include the exec header; + for BFD's purposes, we don't, which makes more work for us. + start at TEXT_START_ADDR + EXEC_BYTES_SIZE, offset is EXEC_BYTES_SIZE, + size as stated minus EXEC_BYTES_SIZE. + * If N_HEADER_IN_TEXT(x) is false (which defaults to being the case when + the entry point is less than EXEC_BYTES_SIZE into a page (e.g. page + aligned)): (padding is needed so that text can start at a page boundary) + start at TEXT_START_ADDR, offset TARGET_PAGE_SIZE, size as stated. + + Specific configurations may want to hardwire N_HEADER_IN_TEXT, + for efficiency or to allow people to play games with the entry point. + In that case, you would #define N_HEADER_IN_TEXT(x) as 1 for sunos, + and as 0 for most other hosts (Sony News, Vax Ultrix, etc). + (Do this in the appropriate bfd target file.) + (The default is a heuristic that will break if people try changing + the entry point, perhaps with the ld -e flag.) + + * QMAGIC is always like a ZMAGIC for which N_HEADER_IN_TEXT is true, + and for which the starting address is TARGET_PAGE_SIZE (or should this be + SEGMENT_SIZE?) (TEXT_START_ADDR only applies to ZMAGIC, not to QMAGIC). */ + +/* This macro is only relevant for ZMAGIC files; QMAGIC always has the header + in the text. */ +#ifndef N_HEADER_IN_TEXT +#define N_HEADER_IN_TEXT(x) \ + (((x).a_entry & (TARGET_PAGE_SIZE-1)) >= EXEC_BYTES_SIZE) +#endif + +/* Sun shared libraries, not linux. This macro is only relevant for ZMAGIC + files. */ +#ifndef N_SHARED_LIB +#define N_SHARED_LIB(x) (0) +#endif + +/* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on + the assumption that we are dealing with a .o file, not an + executable. This is necessary for OMAGIC (but means we don't work + right on the output from ld -N); more questionable for NMAGIC. */ + +#ifndef N_TXTADDR +#define N_TXTADDR(x) \ + (/* The address of a QMAGIC file is always one page in, \ + with the header in the text. */ \ + N_IS_QMAGIC (x) \ + ? (bfd_vma) TARGET_PAGE_SIZE + EXEC_BYTES_SIZE \ + : (N_MAGIC (x) != ZMAGIC \ + ? (bfd_vma) 0 /* Object file or NMAGIC. */ \ + : (N_SHARED_LIB (x) \ + ? (bfd_vma) 0 \ + : (N_HEADER_IN_TEXT (x) \ + ? (bfd_vma) TEXT_START_ADDR + EXEC_BYTES_SIZE \ + : (bfd_vma) TEXT_START_ADDR)))) +#endif + +/* If N_HEADER_IN_TEXT is not true for ZMAGIC, there is some padding + to make the text segment start at a certain boundary. For most + systems, this boundary is TARGET_PAGE_SIZE. But for Linux, in the + time-honored tradition of crazy ZMAGIC hacks, it is 1024 which is + not what TARGET_PAGE_SIZE needs to be for QMAGIC. */ + +#ifndef ZMAGIC_DISK_BLOCK_SIZE +#define ZMAGIC_DISK_BLOCK_SIZE TARGET_PAGE_SIZE +#endif + +#define N_DISK_BLOCK_SIZE(x) \ + (N_MAGIC(x) == ZMAGIC ? ZMAGIC_DISK_BLOCK_SIZE : TARGET_PAGE_SIZE) + +/* Offset in an a.out of the start of the text section. */ +#ifndef N_TXTOFF +#define N_TXTOFF(x) \ + (/* For {O,N,Q}MAGIC, no padding. */ \ + N_MAGIC (x) != ZMAGIC \ + ? EXEC_BYTES_SIZE \ + : (N_SHARED_LIB (x) \ + ? 0 \ + : (N_HEADER_IN_TEXT (x) \ + ? EXEC_BYTES_SIZE /* No padding. */ \ + : ZMAGIC_DISK_BLOCK_SIZE /* A page of padding. */))) +#endif +/* Size of the text section. It's always as stated, except that we + offset it to `undo' the adjustment to N_TXTADDR and N_TXTOFF + for ZMAGIC files that nominally include the exec header + as part of the first page of text. (BFD doesn't consider the + exec header to be part of the text segment.) */ +#ifndef N_TXTSIZE +#define N_TXTSIZE(x) \ + (/* For QMAGIC, we don't consider the header part of the text section. */\ + N_IS_QMAGIC (x) \ + ? (x).a_text - EXEC_BYTES_SIZE \ + : ((N_MAGIC (x) != ZMAGIC || N_SHARED_LIB (x)) \ + ? (x).a_text \ + : (N_HEADER_IN_TEXT (x) \ + ? (x).a_text - EXEC_BYTES_SIZE /* No padding. */ \ + : (x).a_text /* A page of padding. */ ))) +#endif +/* The address of the data segment in virtual memory. + It is the text segment address, plus text segment size, rounded + up to a N_SEGSIZE boundary for pure or pageable files. */ +#ifndef N_DATADDR +#define N_DATADDR(x) \ + (N_MAGIC (x) == OMAGIC \ + ? (N_TXTADDR (x) + N_TXTSIZE (x)) \ + : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1) \ + & ~ (bfd_vma) (N_SEGSIZE (x) - 1)))) +#endif +/* The address of the BSS segment -- immediately after the data segment. */ + +#define N_BSSADDR(x) (N_DATADDR (x) + (x).a_data) + +/* Offsets of the various portions of the file after the text segment. */ + +/* For {Q,Z}MAGIC, there is padding to make the data segment start on + a page boundary. Most of the time the a_text field (and thus + N_TXTSIZE) already contains this padding. It is possible that for + BSDI and/or 386BSD it sometimes doesn't contain the padding, and + perhaps we should be adding it here. But this seems kind of + questionable and probably should be BSDI/386BSD-specific if we do + do it. + + For NMAGIC (at least for hp300 BSD, probably others), there is + padding in memory only, not on disk, so we must *not* ever pad here + for NMAGIC. */ + +#ifndef N_DATOFF +#define N_DATOFF(x) (N_TXTOFF (x) + N_TXTSIZE (x)) +#endif +#ifndef N_TRELOFF +#define N_TRELOFF(x) (N_DATOFF (x) + (x).a_data) +#endif +#ifndef N_DRELOFF +#define N_DRELOFF(x) (N_TRELOFF (x) + (x).a_trsize) +#endif +#ifndef N_SYMOFF +#define N_SYMOFF(x) (N_DRELOFF (x) + (x).a_drsize) +#endif +#ifndef N_STROFF +#define N_STROFF(x) (N_SYMOFF (x) + (x).a_syms) +#endif + +/* Symbols */ +#ifndef external_nlist +struct external_nlist +{ + bfd_byte e_strx[BYTES_IN_WORD]; /* Index into string table of name. */ + bfd_byte e_type[1]; /* Type of symbol. */ + bfd_byte e_other[1]; /* Misc info (usually empty). */ + bfd_byte e_desc[2]; /* Description field. */ + bfd_byte e_value[BYTES_IN_WORD]; /* Value of symbol. */ +}; +#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD) +#endif + +struct internal_nlist +{ + unsigned long n_strx; /* Index into string table of name. */ + unsigned char n_type; /* Type of symbol. */ + unsigned char n_other; /* Misc info (usually empty). */ + unsigned short n_desc; /* Description field. */ + bfd_vma n_value; /* Value of symbol. */ +}; + +/* The n_type field is the symbol type, containing: */ + +#define N_UNDF 0 /* Undefined symbol. */ +#define N_ABS 2 /* Absolute symbol -- defined at particular addr. */ +#define N_TEXT 4 /* Text sym -- defined at offset in text seg. */ +#define N_DATA 6 /* Data sym -- defined at offset in data seg. */ +#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg. */ +#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink). */ +#define N_FN 0x1f /* File name of .o file. */ +#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh). */ +/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT, + N_DATA, or N_BSS. When the low-order bit of other types is set, + (e.g. N_WARNING versus N_FN), they are two different types. */ +#define N_EXT 1 /* External symbol (as opposed to local-to-this-file). */ +#define N_TYPE 0x1e +#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol. */ + +#define N_INDR 0x0a + +/* The following symbols refer to set elements. + All the N_SET[ATDB] symbols with the same name form one set. + Space is allocated for the set in the text section, and each set + elements value is stored into one word of the space. + The first word of the space is the length of the set (number of elements). + + The address of the set is made into an N_SETV symbol + whose name is the same as the name of the set. + This symbol acts like a N_DATA global symbol + in that it can satisfy undefined external references. */ + +/* These appear as input to LD, in a .o file. */ +#define N_SETA 0x14 /* Absolute set element symbol. */ +#define N_SETT 0x16 /* Text set element symbol. */ +#define N_SETD 0x18 /* Data set element symbol. */ +#define N_SETB 0x1A /* Bss set element symbol. */ + +/* This is output from LD. */ +#define N_SETV 0x1C /* Pointer to set vector in data area. */ + +/* Warning symbol. The text gives a warning message, the next symbol + in the table will be undefined. When the symbol is referenced, the + message is printed. */ + +#define N_WARNING 0x1e + +/* Weak symbols. These are a GNU extension to the a.out format. The + semantics are those of ELF weak symbols. Weak symbols are always + externally visible. The N_WEAK? values are squeezed into the + available slots. The value of a N_WEAKU symbol is 0. The values + of the other types are the definitions. */ +#define N_WEAKU 0x0d /* Weak undefined symbol. */ +#define N_WEAKA 0x0e /* Weak absolute symbol. */ +#define N_WEAKT 0x0f /* Weak text symbol. */ +#define N_WEAKD 0x10 /* Weak data symbol. */ +#define N_WEAKB 0x11 /* Weak bss symbol. */ + +/* Relocations + + There are two types of relocation flavours for a.out systems, + standard and extended. The standard form is used on systems where the + instruction has room for all the bits of an offset to the operand, whilst + the extended form is used when an address operand has to be split over n + instructions. Eg, on the 68k, each move instruction can reference + the target with a displacement of 16 or 32 bits. On the sparc, move + instructions use an offset of 14 bits, so the offset is stored in + the reloc field, and the data in the section is ignored. */ + +/* This structure describes a single relocation to be performed. + The text-relocation section of the file is a vector of these structures, + all of which apply to the text section. + Likewise, the data-relocation section applies to the data section. */ + +struct reloc_std_external +{ + bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */ + bfd_byte r_index[3]; /* Symbol table index of symbol. */ + bfd_byte r_type[1]; /* Relocation type. */ +}; + +#define RELOC_STD_BITS_PCREL_BIG ((unsigned int) 0x80) +#define RELOC_STD_BITS_PCREL_LITTLE ((unsigned int) 0x01) + +#define RELOC_STD_BITS_LENGTH_BIG ((unsigned int) 0x60) +#define RELOC_STD_BITS_LENGTH_SH_BIG 5 +#define RELOC_STD_BITS_LENGTH_LITTLE ((unsigned int) 0x06) +#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 + +#define RELOC_STD_BITS_EXTERN_BIG ((unsigned int) 0x10) +#define RELOC_STD_BITS_EXTERN_LITTLE ((unsigned int) 0x08) + +#define RELOC_STD_BITS_BASEREL_BIG ((unsigned int) 0x08) +#define RELOC_STD_BITS_BASEREL_LITTLE ((unsigned int) 0x10) + +#define RELOC_STD_BITS_JMPTABLE_BIG ((unsigned int) 0x04) +#define RELOC_STD_BITS_JMPTABLE_LITTLE ((unsigned int) 0x20) + +#define RELOC_STD_BITS_RELATIVE_BIG ((unsigned int) 0x02) +#define RELOC_STD_BITS_RELATIVE_LITTLE ((unsigned int) 0x40) + +#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry. */ + +struct reloc_std_internal +{ + bfd_vma r_address; /* Address (within segment) to be relocated. */ + /* The meaning of r_symbolnum depends on r_extern. */ + unsigned int r_symbolnum:24; + /* Nonzero means value is a pc-relative offset + and it should be relocated for changes in its own address + as well as for changes in the symbol or section specified. */ + unsigned int r_pcrel:1; + /* Length (as exponent of 2) of the field to be relocated. + Thus, a value of 2 indicates 1<<2 bytes. */ + unsigned int r_length:2; + /* 1 => relocate with value of symbol. + r_symbolnum is the index of the symbol + in files the symbol table. + 0 => relocate with the address of a segment. + r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS + (the N_EXT bit may be set also, but signifies nothing). */ + unsigned int r_extern:1; + /* The next three bits are for SunOS shared libraries, and seem to + be undocumented. */ + unsigned int r_baserel:1; /* Linkage table relative. */ + unsigned int r_jmptable:1; /* pc-relative to jump table. */ + unsigned int r_relative:1; /* "relative relocation". */ + /* unused */ + unsigned int r_pad:1; /* Padding -- set to zero. */ +}; + + +/* EXTENDED RELOCS. */ + +struct reloc_ext_external +{ + bfd_byte r_address[BYTES_IN_WORD]; /* Offset of of data to relocate. */ + bfd_byte r_index[3]; /* Symbol table index of symbol. */ + bfd_byte r_type[1]; /* Relocation type. */ + bfd_byte r_addend[BYTES_IN_WORD]; /* Datum addend. */ +}; + +#ifndef RELOC_EXT_BITS_EXTERN_BIG +#define RELOC_EXT_BITS_EXTERN_BIG ((unsigned int) 0x80) +#endif + +#ifndef RELOC_EXT_BITS_EXTERN_LITTLE +#define RELOC_EXT_BITS_EXTERN_LITTLE ((unsigned int) 0x01) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_BIG +#define RELOC_EXT_BITS_TYPE_BIG ((unsigned int) 0x1F) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_BIG +#define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#endif + +#ifndef RELOC_EXT_BITS_TYPE_LITTLE +#define RELOC_EXT_BITS_TYPE_LITTLE ((unsigned int) 0xF8) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_LITTLE +#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 +#endif + +/* Bytes per relocation entry. */ +#define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) + +enum reloc_type +{ + /* Simple relocations. */ + RELOC_8, /* data[0:7] = addend + sv */ + RELOC_16, /* data[0:15] = addend + sv */ + RELOC_32, /* data[0:31] = addend + sv */ + /* PC-rel displacement. */ + RELOC_DISP8, /* data[0:7] = addend - pc + sv */ + RELOC_DISP16, /* data[0:15] = addend - pc + sv */ + RELOC_DISP32, /* data[0:31] = addend - pc + sv */ + /* Special. */ + RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */ + RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */ + RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */ + RELOC_22, /* data[0:21] = (addend + sv) */ + RELOC_13, /* data[0:12] = (addend + sv) */ + RELOC_LO10, /* data[0:9] = (addend + sv) */ + RELOC_SFA_BASE, + RELOC_SFA_OFF13, + /* P.I.C. (base-relative). */ + RELOC_BASE10, /* Not sure - maybe we can do this the */ + RELOC_BASE13, /* right way now */ + RELOC_BASE22, + /* For some sort of pc-rel P.I.C. (?) */ + RELOC_PC10, + RELOC_PC22, + /* P.I.C. jump table. */ + RELOC_JMP_TBL, + /* Reputedly for shared libraries somehow. */ + RELOC_SEGOFF16, + RELOC_GLOB_DAT, + RELOC_JMP_SLOT, + RELOC_RELATIVE, + + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, /* data[0:21] = (addend + sv) >> 42 */ + RELOC_HLO10, /* data[0:9] = (addend + sv) >> 32 */ + + /* 29K relocation types. */ + RELOC_JUMPTARG, + RELOC_CONST, + RELOC_CONSTH, + + /* All the new ones I can think of, for sparc v9. */ + RELOC_64, /* data[0:63] = addend + sv */ + RELOC_DISP64, /* data[0:63] = addend - pc + sv */ + RELOC_WDISP21, /* data[0:20] = (addend + sv - pc)>>2 */ + RELOC_DISP21, /* data[0:20] = addend - pc + sv */ + RELOC_DISP14, /* data[0:13] = addend - pc + sv */ + /* Q . + What are the other ones, + Since this is a clean slate, can we throw away the ones we dont + understand ? Should we sort the values ? What about using a + microcode format like the 68k ? */ + NO_RELOC + }; + + +struct reloc_internal +{ + bfd_vma r_address; /* Offset of of data to relocate. */ + long r_index; /* Symbol table index of symbol. */ + enum reloc_type r_type; /* Relocation type. */ + bfd_vma r_addend; /* Datum addend. */ +}; + +/* Q. + Should the length of the string table be 4 bytes or 8 bytes ? + + Q. + What about archive indexes ? */ + +#endif /* __A_OUT_64_H__ */ diff --git a/external/gpl3/gdb/dist/include/aout/ar.h b/external/gpl3/gdb/dist/include/aout/ar.h new file mode 100644 index 000000000000..de0438222dbe --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/ar.h @@ -0,0 +1,55 @@ +/* archive file definition for GNU software + + Copyright 2001, 2008, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* So far this is correct for BSDish archives. Don't forget that + files must begin on an even byte boundary. */ + +#ifndef __GNU_AR_H__ +#define __GNU_AR_H__ + +/* Note that the usual '\n' in magic strings may translate to different + characters, as allowed by ANSI. '\012' has a fixed value, and remains + compatible with existing BSDish archives. */ + +#define ARMAG "!\012" /* For COFF and a.out archives. */ +#define ARMAGB "!\012" /* For b.out archives. */ +#define ARMAGT "!\012" /* For thin archives. */ +#define SARMAG 8 +#define ARFMAG "`\012" + +/* The ar_date field of the armap (__.SYMDEF) member of an archive + must be greater than the modified date of the entire file, or + BSD-derived linkers complain. We originally write the ar_date with + this offset from the real file's mod-time. After finishing the + file, we rewrite ar_date if it's not still greater than the mod date. */ + +#define ARMAP_TIME_OFFSET 60 + +struct ar_hdr +{ + char ar_name[16]; /* Name of this member. */ + char ar_date[12]; /* File mtime. */ + char ar_uid[6]; /* Owner uid; printed as decimal. */ + char ar_gid[6]; /* Owner gid; printed as decimal. */ + char ar_mode[8]; /* File mode, printed as octal. */ + char ar_size[10]; /* File size, printed as decimal. */ + char ar_fmag[2]; /* Should contain ARFMAG. */ +}; + +#endif /* __GNU_AR_H__ */ diff --git a/external/gpl3/gdb/dist/include/aout/dynix3.h b/external/gpl3/gdb/dist/include/aout/dynix3.h new file mode 100644 index 000000000000..808e53a76348 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/dynix3.h @@ -0,0 +1,87 @@ +/* a.out specifics for Sequent Symmetry running Dynix 3.x + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef A_OUT_DYNIX3_H +#define A_OUT_DYNIX3_H + +#define external_exec dynix_external_exec + +/* struct exec for Dynix 3 + + a_gdtbl and a_bootstrap are only for standalone binaries. + Shared data fields are not supported by the kernel as of Dynix 3.1, + but are supported by Dynix compiler programs. */ +struct dynix_external_exec + { + unsigned char e_info[4]; + unsigned char e_text[4]; + unsigned char e_data[4]; + unsigned char e_bss[4]; + unsigned char e_syms[4]; + unsigned char e_entry[4]; + unsigned char e_trsize[4]; + unsigned char e_drsize[4]; + unsigned char e_g_code[8]; + unsigned char e_g_data[8]; + unsigned char e_g_desc[8]; + unsigned char e_shdata[4]; + unsigned char e_shbss[4]; + unsigned char e_shdrsize[4]; + unsigned char e_bootstrap[44]; + unsigned char e_reserved[12]; + unsigned char e_version[4]; + }; + +#define EXEC_BYTES_SIZE (128) + +/* All executables under Dynix are demand paged with read-only text, + Thus no NMAGIC. + + ZMAGIC has a page of 0s at virtual 0, + XMAGIC has an invalid page at virtual 0. */ +#define OMAGIC 0x12eb /* .o */ +#define ZMAGIC 0x22eb /* zero @ 0, demand load */ +#define XMAGIC 0x32eb /* invalid @ 0, demand load */ +#define SMAGIC 0x42eb /* standalone, not supported here */ + +#define N_BADMAG(x) ((OMAGIC != N_MAGIC(x)) && \ + (ZMAGIC != N_MAGIC(x)) && \ + (XMAGIC != N_MAGIC(x)) && \ + (SMAGIC != N_MAGIC(x))) + +#define N_ADDRADJ(x) ((ZMAGIC == N_MAGIC(x) || XMAGIC == N_MAGIC(x)) ? 0x1000 : 0) + +#define N_TXTOFF(x) (EXEC_BYTES_SIZE) +#define N_DATOFF(x) (N_TXTOFF(x) + N_TXTSIZE(x)) +#define N_SHDATOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_TRELOFF(x) (N_SHDATOFF(x) + (x).a_shdata) +#define N_DRELOFF(x) (N_TRELOFF(x) + (x).a_trsize) +#define N_SHDRELOFF(x) (N_DRELOFF(x) + (x).a_drsize) +#define N_SYMOFF(x) (N_SHDRELOFF(x) + (x).a_shdrsize) +#define N_STROFF(x) (N_SYMOFF(x) + (x).a_syms) + +#define N_TXTADDR(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? 0 \ + : TEXT_START_ADDR + EXEC_BYTES_SIZE) + +#define N_TXTSIZE(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? ((x).a_text) \ + : ((x).a_text - N_ADDRADJ(x) - EXEC_BYTES_SIZE)) + +#endif /* A_OUT_DYNIX3_H */ diff --git a/external/gpl3/gdb/dist/include/aout/encap.h b/external/gpl3/gdb/dist/include/aout/encap.h new file mode 100644 index 000000000000..7ebec698bac5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/encap.h @@ -0,0 +1,135 @@ +/* Yet Another Try at encapsulating bfd object files in coff. + Copyright 1988, 1989, 1991, 2010 Free Software Foundation, Inc. + Written by Pace Willisson 12/9/88 + + This file is obsolete. It needs to be converted to just define a bunch + of stuff that BFD can use to do coff-encapsulated files. --gnu@cygnus.com + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* + * We only use the coff headers to tell the kernel + * how to exec the file. Therefore, the only fields that need to + * be filled in are the scnptr and vaddr for the text and data + * sections, and the vaddr for the bss. As far as coff is concerned, + * there is no symbol table, relocation, or line numbers. + * + * A normal bsd header (struct exec) is placed after the coff headers, + * and before the real text. I defined a the new fields 'a_machtype' + * and a_flags. If a_machtype is M_386, and a_flags & A_ENCAP is + * true, then the bsd header is preceeded by a coff header. Macros + * like N_TXTOFF and N_TXTADDR use this field to find the bsd header. + * + * The only problem is to track down the bsd exec header. The + * macros HEADER_OFFSET, etc do this. + */ + +#define N_FLAGS_COFF_ENCAPSULATE 0x20 /* coff header precedes bsd header */ + +/* Describe the COFF header used for encapsulation. */ + +struct coffheader +{ + /* filehdr */ + unsigned short f_magic; + unsigned short f_nscns; + long f_timdat; + long f_symptr; + long f_nsyms; + unsigned short f_opthdr; + unsigned short f_flags; + /* aouthdr */ + short magic; + short vstamp; + long tsize; + long dsize; + long bsize; + long entry; + long text_start; + long data_start; + struct coffscn + { + char s_name[8]; + long s_paddr; + long s_vaddr; + long s_size; + long s_scnptr; + long s_relptr; + long s_lnnoptr; + unsigned short s_nreloc; + unsigned short s_nlnno; + long s_flags; + } scns[3]; +}; + +/* Describe some of the parameters of the encapsulation, + including how to find the encapsulated BSD header. */ + +/* FIXME, this is dumb. The same tools can't handle a.outs for different + architectures, just because COFF_MAGIC is different; so you need a + separate GNU nm for every architecture!!? Unfortunately, it needs to + be this way, since the COFF_MAGIC value is determined by the kernel + we're trying to fool here. */ + +#define COFF_MAGIC_I386 0514 /* I386MAGIC */ +#define COFF_MAGIC_M68K 0520 /* MC68MAGIC */ + +#ifdef COFF_MAGIC +short __header_offset_temp; +#define HEADER_OFFSET(f) \ + (__header_offset_temp = 0, \ + fread ((char *)&__header_offset_temp, sizeof (short), 1, (f)), \ + fseek ((f), -sizeof (short), 1), \ + __header_offset_temp==COFF_MAGIC ? sizeof(struct coffheader) : 0) +#else +#define HEADER_OFFSET(f) 0 +#endif + +#define HEADER_SEEK(f) (fseek ((f), HEADER_OFFSET((f)), 1)) + +/* Describe the characteristics of the BSD header + that appears inside the encapsulation. */ + +/* Encapsulated coff files that are linked ZMAGIC have a text segment + offset just past the header (and a matching TXTADDR), excluding + the headers from the text segment proper but keeping the physical + layout and the virtual memory layout page-aligned. + + Non-encapsulated a.out files that are linked ZMAGIC have a text + segment that starts at 0 and an N_TXTADR similarly offset to 0. + They too are page-aligned with each other, but they include the + a.out header as part of the text. + + The _N_HDROFF gets sizeof struct exec added to it, so we have + to compensate here. See . */ + +#undef _N_HDROFF +#undef N_TXTADDR +#undef N_DATADDR + +#define _N_HDROFF(x) ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) : 0) + +/* Address of text segment in memory after it is loaded. */ +#define N_TXTADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + sizeof (struct coffheader) + sizeof (struct exec) : 0) +#define SEGMENT_SIZE 0x400000 + +#define N_DATADDR(x) \ + ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \ + (SEGMENT_SIZE + ((N_TXTADDR(x)+(x).a_text-1) & ~(SEGMENT_SIZE-1))) : \ + (N_TXTADDR(x)+(x).a_text)) diff --git a/external/gpl3/gdb/dist/include/aout/host.h b/external/gpl3/gdb/dist/include/aout/host.h new file mode 100644 index 000000000000..4260cc53619b --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/host.h @@ -0,0 +1,43 @@ +/* host.h - Parameters about the a.out format, based on the host system + on which the program is compiled. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Address of data segment in memory after it is loaded. + It is up to you to define SEGMENT_SIZE on machines not listed here. */ +#ifndef SEGMENT_SIZE + +#if defined(hp300) || defined(pyr) +#define SEGMENT_SIZE page_size +#endif + +#ifdef sony +#define SEGMENT_SIZE 0x1000 +#endif /* Sony. */ + +#ifdef is68k +#define SEGMENT_SIZE 0x20000 +#endif + +#if defined(m68k) && defined(PORTAR) +#define TARGET_PAGE_SIZE 0x400 +#define SEGMENT_SIZE TARGET_PAGE_SIZE +#endif + +#endif /*!defined(SEGMENT_SIZE)*/ + diff --git a/external/gpl3/gdb/dist/include/aout/hp.h b/external/gpl3/gdb/dist/include/aout/hp.h new file mode 100644 index 000000000000..b60741a7020d --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/hp.h @@ -0,0 +1,83 @@ +/* Special version of for use under HP-UX. + Copyright 1988, 1991, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* THIS FILE IS OBSOLETE. It needs to be revised as a variant "external" + a.out format for use with BFD. */ + +/* The `exec' structure and overall layout must be close to HP's when + we are running on an HP system, otherwise we will not be able to + execute the resulting file. */ + +/* Allow this file to be included twice. */ +#ifndef __GNU_EXEC_MACROS__ + +struct exec +{ + unsigned short a_machtype; /* machine type */ + unsigned short a_magic; /* magic number */ + unsigned long a_spare1; + unsigned long a_spare2; + unsigned long a_text; /* length of text, in bytes */ + unsigned long a_data; /* length of data, in bytes */ + unsigned long a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned long a_trsize; /* length of relocation info for text, in bytes */ + unsigned long a_drsize; /* length of relocation info for data, in bytes */ + unsigned long a_spare3; /* HP = pascal interface size */ + unsigned long a_spare4; /* HP = symbol table size */ + unsigned long a_spare5; /* HP = debug name table size */ + unsigned long a_entry; /* start address */ + unsigned long a_spare6; /* HP = source line table size */ + unsigned long a_spare7; /* HP = value table size */ + unsigned long a_syms; /* length of symbol table data in file, in bytes */ + unsigned long a_spare8; +}; + +/* Tell a.out.gnu.h not to define `struct exec'. */ +#define __STRUCT_EXEC_OVERRIDE__ + +#include "../a.out.gnu.h" + +#undef N_MAGIC +#undef N_MACHTYPE +#undef N_FLAGS +#undef N_SET_INFO +#undef N_SET_MAGIC +#undef N_SET_MACHTYPE +#undef N_SET_FLAGS + +#define N_MAGIC(exec) ((exec) . a_magic) +#define N_MACHTYPE(exec) ((exec) . a_machtype) +#define N_SET_MAGIC(exec, magic) (((exec) . a_magic) = (magic)) +#define N_SET_MACHTYPE(exec, machtype) (((exec) . a_machtype) = (machtype)) + +#undef N_BADMAG +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define _N_BADMACH(x) \ +(((N_MACHTYPE (x)) != HP9000S200_ID) && \ + ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#define SEGMENT_SIZE 0x1000 + +#endif /* __GNU_EXEC_MACROS__ */ diff --git a/external/gpl3/gdb/dist/include/aout/hp300hpux.h b/external/gpl3/gdb/dist/include/aout/hp300hpux.h new file mode 100644 index 000000000000..97a3eb58f528 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/hp300hpux.h @@ -0,0 +1,132 @@ +/* Special version of for use under HP-UX. + Copyright 1988, 1993, 1995, 2001, 2009, 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +struct hp300hpux_exec_bytes +{ + unsigned char e_info[4]; /* a_machtype/a_magic */ + unsigned char e_spare1[4]; + unsigned char e_spare2[4]; + unsigned char e_text[4]; /* length of text, in bytes */ + unsigned char e_data[4]; /* length of data, in bytes */ + unsigned char e_bss[4]; /* length of uninitialized data area , in bytes */ + unsigned char e_trsize[4]; /* length of relocation info for text, in bytes*/ + unsigned char e_drsize[4]; /* length of relocation info for data, in bytes*/ + unsigned char e_passize[4];/* HP = pascal interface size */ + unsigned char e_syms[4]; /* HP = symbol table size */ + unsigned char e_spare5[4]; /* HP = debug name table size */ + unsigned char e_entry[4]; /* start address */ + unsigned char e_spare6[4]; /* HP = source line table size */ + unsigned char e_supsize[4];/* HP = value table size */ + unsigned char e_drelocs[4]; + unsigned char e_extension[4]; /* file offset of extension */ +}; +#define EXEC_BYTES_SIZE 64 + +struct hp300hpux_nlist_bytes + { + unsigned char e_value[4]; + unsigned char e_type[1]; + unsigned char e_length[1]; /* length of ascii symbol name */ + unsigned char e_almod[2]; /* alignment mod */ + unsigned char e_shlib[2]; /* info about dynamic linking */ + }; +#define EXTERNAL_NLIST_SIZE 10 + +struct hp300hpux_reloc + { + unsigned char r_address[4];/* offset of of data to relocate */ + unsigned char r_index[2]; /* symbol table index of symbol */ + unsigned char r_type[1]; /* relocation type */ + unsigned char r_length[1]; /* length of item to reloc */ + }; + +struct hp300hpux_header_extension +{ + unsigned char e_syms[4]; + unsigned char unique_headers[12*4]; + unsigned char e_header[2]; /* type of header */ + unsigned char e_version[2]; /* version */ + unsigned char e_size[4]; /* bytes following*/ + unsigned char e_extension[4];/* file offset of next extension */ +}; +#define EXTERNAL_EXTENSION_HEADER_SIZE (16*4) + +/* hpux separates object files (0x106) and impure executables (0x107) */ +/* but the bfd code does not distinguish between them. Since we want to*/ +/* read hpux .o files, we add an special define and use it below in */ +/* offset and address calculations. */ + +#define HPUX_DOT_O_MAGIC 0x106 +#define OMAGIC 0x107 /* object file or impure executable. */ +#define NMAGIC 0x108 /* Code indicating pure executable. */ +#define ZMAGIC 0x10B /* demand-paged executable. */ + +#define N_HEADER_IN_TEXT(x) 0 + +#if 0 /* libaout.h only uses the lower 8 bits */ +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C +#endif +#define HP98x6_ID 0x0A +#define HP9000S200_ID 0x0C + +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define N_DATADDR(x) \ + ((N_MAGIC (x) == OMAGIC || N_MAGIC (x) == HPUX_DOT_O_MAGIC) \ + ? (N_TXTADDR (x) + N_TXTSIZE (x)) \ + : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1) \ + & ~ (bfd_vma) (N_SEGSIZE (x) - 1)))) + +#define _N_BADMACH(x) \ + (((N_MACHTYPE (x)) != HP9000S200_ID) && ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define _N_BADMAG(x) (N_MAGIC(x) != HPUX_DOT_O_MAGIC \ + && N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC ) + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#undef N_DATOFF +#undef N_PASOFF +#undef N_SYMOFF +#undef N_SUPOFF +#undef N_TRELOFF +#undef N_DRELOFF +#undef N_STROFF + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_PASOFF(x) ( N_DATOFF(x) + (x).a_data) +#define N_SYMOFF(x) ( N_PASOFF(x) /* + (x).a_passize*/ ) +#define N_SUPOFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_TRELOFF(x) ( N_SUPOFF(x) /* + 0 (x).a_supsize*/ ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_EXTHOFF(x) ( N_DRELOFF(x) /* + 0 (x).a_drsize */) +#define N_STROFF(x) ( 0 /* no string table */ ) + +/* use these when the file has gnu symbol tables */ +#define N_GNU_TRELOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_GNU_DRELOFF(x) (N_GNU_TRELOFF(x) + (x).a_trsize) +#define N_GNU_SYMOFF(x) (N_GNU_DRELOFF(x) + (x).a_drsize) + +#define TARGET_PAGE_SIZE 0x1000 +#define SEGMENT_SIZE 0x1000 +#define TEXT_START_ADDR 0 diff --git a/external/gpl3/gdb/dist/include/aout/hppa.h b/external/gpl3/gdb/dist/include/aout/hppa.h new file mode 100644 index 000000000000..7e185de768a4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/hppa.h @@ -0,0 +1,7 @@ +#include "filehdr.h" +#include "aouthdr.h" +#include "scnhdr.h" +#include "spacehdr.h" +#include "syms.h" + + diff --git a/external/gpl3/gdb/dist/include/aout/ranlib.h b/external/gpl3/gdb/dist/include/aout/ranlib.h new file mode 100644 index 000000000000..92bec46890f1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/ranlib.h @@ -0,0 +1,63 @@ +/* ranlib.h -- archive library index member definition for GNU. + Copyright 1990, 1991, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The Symdef member of an archive contains two things: + a table that maps symbol-string offsets to file offsets, + and a symbol-string table. All the symbol names are + run together (each with trailing null) in the symbol-string + table. There is a single longword bytecount on the front + of each of these tables. Thus if we have two symbols, + "foo" and "_bar", that are in archive members at offsets + 200 and 900, it would look like this: + 16 ; byte count of index table + 0 ; offset of "foo" in string table + 200 ; offset of foo-module in file + 4 ; offset of "bar" in string table + 900 ; offset of bar-module in file + 9 ; byte count of string table + "foo\0_bar\0" ; string table */ + +#define RANLIBMAG "__.SYMDEF" /* Archive file name containing index */ +#define RANLIBSKEW 3 /* Creation time offset */ + +/* Format of __.SYMDEF: + First, a longword containing the size of the 'symdef' data that follows. + Second, zero or more 'symdef' structures. + Third, a longword containing the length of symbol name strings. + Fourth, zero or more symbol name strings (each followed by a null). */ + +struct symdef + { + union + { + unsigned long string_offset; /* In the file */ + char *name; /* In memory, sometimes */ + } s; + /* this points to the front of the file header (AKA member header -- + a struct ar_hdr), not to the front of the file or into the file). + in other words it only tells you which file to read */ + unsigned long file_offset; + }; + +/* Compatability with BSD code */ + +#define ranlib symdef +#define ran_un s +#define ran_strx string_offset +#define ran_name name +#define ran_off file_offset diff --git a/external/gpl3/gdb/dist/include/aout/reloc.h b/external/gpl3/gdb/dist/include/aout/reloc.h new file mode 100644 index 000000000000..6f1bc52e48a4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/reloc.h @@ -0,0 +1,67 @@ +/* reloc.h -- Header file for relocation information. + Copyright 1989, 1990, 1991, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Relocation types for a.out files using reloc_info_extended + (SPARC and AMD 29000). */ + +#ifndef _RELOC_H_READ_ +#define _RELOC_H_READ_ 1 + +enum reloc_type + { + RELOC_8, RELOC_16, RELOC_32, /* simple relocations */ + RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* pc-rel displacement */ + RELOC_WDISP30, RELOC_WDISP22, + RELOC_HI22, RELOC_22, + RELOC_13, RELOC_LO10, + RELOC_SFA_BASE, RELOC_SFA_OFF13, + RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* P.I.C. (base-relative) */ + RELOC_PC10, RELOC_PC22, /* for some sort of pc-rel P.I.C. (?) */ + RELOC_JMP_TBL, /* P.I.C. jump table */ + RELOC_SEGOFF16, /* reputedly for shared libraries somehow */ + RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE, + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, + RELOC_HLO10, + + /* 29K relocation types */ + RELOC_JUMPTARG, RELOC_CONST, RELOC_CONSTH, + + RELOC_WDISP14, RELOC_WDISP21, + + NO_RELOC + }; + +#define RELOC_TYPE_NAMES \ +"8", "16", "32", "DISP8", \ +"DISP16", "DISP32", "WDISP30", "WDISP22", \ +"HI22", "22", "13", "LO10", \ +"SFA_BASE", "SFAOFF13", "BASE10", "BASE13", \ +"BASE22", "PC10", "PC22", "JMP_TBL", \ +"SEGOFF16", "GLOB_DAT", "JMP_SLOT", "RELATIVE", \ +"11", "WDISP2_14", "WDISP19", "HHI22", \ +"HLO10", \ +"JUMPTARG", "CONST", "CONSTH", "WDISP14", \ +"WDISP21", \ +"NO_RELOC" + +#endif /* _RELOC_H_READ_ */ + +/* end of reloc.h */ diff --git a/external/gpl3/gdb/dist/include/aout/stab.def b/external/gpl3/gdb/dist/include/aout/stab.def new file mode 100644 index 000000000000..ad1c62ed88ba --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/stab.def @@ -0,0 +1,283 @@ +/* Table of DBX symbol codes for the GNU system. + Copyright 1988, 1991, 1992, 1993, 1994, 1996, 1998, 2004, 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* New stab from Solaris 2. This uses an n_type of 0, which in a.out files + overlaps the N_UNDF used for ordinary symbols. In ELF files, the + debug information is in a different file section, so there is no conflict. + This symbol's n_value gives the size of the string section associated + with this file. The symbol's n_strx (relative to the just-updated + string section start address) gives the name of the source file, + e.g. "foo.c", without any path information. The symbol's n_desc gives + the count of upcoming symbols associated with this file (not including + this one). */ +/* __define_stab (N_UNDF, 0x00, "UNDF") */ + +/* Global variable. Only the name is significant. + To find the address, look in the corresponding external symbol. */ +__define_stab (N_GSYM, 0x20, "GSYM") + +/* Function name for BSD Fortran. Only the name is significant. + To find the address, look in the corresponding external symbol. */ +__define_stab (N_FNAME, 0x22, "FNAME") + +/* Function name or text-segment variable for C. Value is its address. + Desc is supposedly starting line number, but GCC doesn't set it + and DBX seems not to miss it. */ +__define_stab (N_FUN, 0x24, "FUN") + +/* Data-segment variable with internal linkage. Value is its address. + "Static Sym". */ +__define_stab (N_STSYM, 0x26, "STSYM") + +/* BSS-segment variable with internal linkage. Value is its address. */ +__define_stab (N_LCSYM, 0x28, "LCSYM") + +/* Name of main routine. Only the name is significant. */ +__define_stab (N_MAIN, 0x2a, "MAIN") + +/* Solaris2: Read-only data symbols. */ +__define_stab (N_ROSYM, 0x2c, "ROSYM") + +/* MacOS X: + The beginning of a relocatable function block - including stabs. */ +__define_stab (N_BNSYM, 0x2e, "BNSYM") + +/* Global symbol in Pascal. + Supposedly the value is its line number; I'm skeptical. */ +__define_stab (N_PC, 0x30, "PC") + +/* Number of symbols: 0, files,,funcs,lines according to Ultrix V4.0. */ +__define_stab (N_NSYMS, 0x32, "NSYMS") + +/* "No DST map for sym: name, ,0,type,ignored" according to Ultrix V4.0. */ +__define_stab (N_NOMAP, 0x34, "NOMAP") + +/* New stab from Solaris 2. Like N_SO, but for the object file. Two in + a row provide the build directory and the relative path of the .o from it. + Solaris2 uses this to avoid putting the stabs info into the linked + executable; this stab goes into the ".stab.index" section, and the debugger + reads the real stabs directly from the .o files instead. */ +__define_stab (N_OBJ, 0x38, "OBJ") + +/* New stab from Solaris 2. Options for the debugger, related to the + source language for this module. E.g. whether to use ANSI + integral promotions or traditional integral promotions. */ +__define_stab (N_OPT, 0x3c, "OPT") + +/* Register variable. Value is number of register. */ +__define_stab (N_RSYM, 0x40, "RSYM") + +/* Modula-2 compilation unit. Can someone say what info it contains? */ +__define_stab (N_M2C, 0x42, "M2C") + +/* Line number in text segment. Desc is the line number; + value is corresponding address. On Solaris2, the line number is + relative to the start of the current function. */ +__define_stab (N_SLINE, 0x44, "SLINE") + +/* Similar, for data segment. */ +__define_stab (N_DSLINE, 0x46, "DSLINE") + +/* Similar, for bss segment. */ +__define_stab (N_BSLINE, 0x48, "BSLINE") + +/* Sun's source-code browser stabs. ?? Don't know what the fields are. + Supposedly the field is "path to associated .cb file". THIS VALUE + OVERLAPS WITH N_BSLINE! */ +__define_stab_duplicate (N_BROWS, 0x48, "BROWS") + +/* GNU Modula-2 definition module dependency. Value is the modification time + of the definition file. Other is non-zero if it is imported with the + GNU M2 keyword %INITIALIZE. Perhaps N_M2C can be used if there + are enough empty fields? */ +__define_stab(N_DEFD, 0x4a, "DEFD") + +/* New in Solaris2. Function start/body/end line numbers. */ +__define_stab(N_FLINE, 0x4C, "FLINE") + +/* MacOS X: This tells the end of a relocatable function + debugging info. */ +__define_stab(N_ENSYM, 0x4E, "ENSYM") + +/* THE FOLLOWING TWO STAB VALUES CONFLICT. Happily, one is for Modula-2 + and one is for C++. Still,... */ +/* GNU C++ exception variable. Name is variable name. */ +__define_stab (N_EHDECL, 0x50, "EHDECL") +/* Modula2 info "for imc": name,,0,0,0 according to Ultrix V4.0. */ +__define_stab_duplicate (N_MOD2, 0x50, "MOD2") + +/* GNU C++ `catch' clause. Value is its address. Desc is nonzero if + this entry is immediately followed by a CAUGHT stab saying what exception + was caught. Multiple CAUGHT stabs means that multiple exceptions + can be caught here. If Desc is 0, it means all exceptions are caught + here. */ +__define_stab (N_CATCH, 0x54, "CATCH") + +/* Structure or union element. Value is offset in the structure. */ +__define_stab (N_SSYM, 0x60, "SSYM") + +/* Solaris2: Last stab emitted for module. */ +__define_stab (N_ENDM, 0x62, "ENDM") + +/* Name of main source file. + Value is starting text address of the compilation. + If multiple N_SO's appear, the first to contain a trailing / is the + compilation directory. The first to not contain a trailing / is the + source file name, relative to the compilation directory. Others (perhaps + resulting from cfront) are ignored. + On Solaris2, value is undefined, but desc is a source-language code. */ + +__define_stab (N_SO, 0x64, "SO") + +/* Apple: This is the stab that associated the .o file with the + N_SO stab, in the case where debug info is mostly stored in the .o file. */ +__define_stab (N_OSO, 0x66, "OSO") + +/* SunPro F77: Name of alias. */ +__define_stab (N_ALIAS, 0x6c, "ALIAS") + +/* Automatic variable in the stack. Value is offset from frame pointer. + Also used for type descriptions. */ +__define_stab (N_LSYM, 0x80, "LSYM") + +/* Beginning of an include file. Only Sun uses this. + In an object file, only the name is significant. + The Sun linker puts data into some of the other fields. */ +__define_stab (N_BINCL, 0x82, "BINCL") + +/* Name of sub-source file (#include file). + Value is starting text address of the compilation. */ +__define_stab (N_SOL, 0x84, "SOL") + +/* Parameter variable. Value is offset from argument pointer. + (On most machines the argument pointer is the same as the frame pointer. */ +__define_stab (N_PSYM, 0xa0, "PSYM") + +/* End of an include file. No name. + This and N_BINCL act as brackets around the file's output. + In an object file, there is no significant data in this entry. + The Sun linker puts data into some of the fields. */ +__define_stab (N_EINCL, 0xa2, "EINCL") + +/* Alternate entry point. Value is its address. */ +__define_stab (N_ENTRY, 0xa4, "ENTRY") + +/* Beginning of lexical block. + The desc is the nesting level in lexical blocks. + The value is the address of the start of the text for the block. + The variables declared inside the block *precede* the N_LBRAC symbol. + On Solaris2, the value is relative to the start of the current function. */ +__define_stab (N_LBRAC, 0xc0, "LBRAC") + +/* Place holder for deleted include file. Replaces a N_BINCL and everything + up to the corresponding N_EINCL. The Sun linker generates these when + it finds multiple identical copies of the symbols from an include file. + This appears only in output from the Sun linker. */ +__define_stab (N_EXCL, 0xc2, "EXCL") + +/* Modula-2 scope information. Can someone say what info it contains? */ +__define_stab (N_SCOPE, 0xc4, "SCOPE") + +/* Solaris2: Patch Run Time Checker. */ +__define_stab (N_PATCH, 0xd0, "PATCH") + +/* End of a lexical block. Desc matches the N_LBRAC's desc. + The value is the address of the end of the text for the block. + On Solaris2, the value is relative to the start of the current function. */ +__define_stab (N_RBRAC, 0xe0, "RBRAC") + +/* Begin named common block. Only the name is significant. */ +__define_stab (N_BCOMM, 0xe2, "BCOMM") + +/* End named common block. Only the name is significant + (and it should match the N_BCOMM). */ +__define_stab (N_ECOMM, 0xe4, "ECOMM") + +/* Member of a common block; value is offset within the common block. + This should occur within a BCOMM/ECOMM pair. */ +__define_stab (N_ECOML, 0xe8, "ECOML") + +/* Solaris2: Pascal "with" statement: type,,0,0,offset */ +__define_stab (N_WITH, 0xea, "WITH") + +/* These STAB's are used on Gould systems for Non-Base register symbols + or something like that. FIXME. I have assigned the values at random + since I don't have a Gould here. Fixups from Gould folk welcome... */ +__define_stab (N_NBTEXT, 0xF0, "NBTEXT") +__define_stab (N_NBDATA, 0xF2, "NBDATA") +__define_stab (N_NBBSS, 0xF4, "NBBSS") +__define_stab (N_NBSTS, 0xF6, "NBSTS") +__define_stab (N_NBLCS, 0xF8, "NBLCS") + +/* Second symbol entry containing a length-value for the preceding entry. + The value is the length. */ +__define_stab (N_LENG, 0xfe, "LENG") + +/* The above information, in matrix format. + + STAB MATRIX + _________________________________________________ + | 00 - 1F are not dbx stab symbols | + | In most cases, the low bit is the EXTernal bit| + + | 00 UNDEF | 02 ABS | 04 TEXT | 06 DATA | + | 01 |EXT | 03 |EXT | 05 |EXT | 07 |EXT | + + | 08 BSS | 0A INDR | 0C FN_SEQ | 0E WEAKA | + | 09 |EXT | 0B | 0D WEAKU | 0F WEAKT | + + | 10 WEAKD | 12 COMM | 14 SETA | 16 SETT | + | 11 WEAKB | 13 | 15 | 17 | + + | 18 SETD | 1A SETB | 1C SETV | 1E WARNING| + | 19 | 1B | 1D | 1F FN | + + |_______________________________________________| + | Debug entries with bit 01 set are unused. | + | 20 GSYM | 22 FNAME | 24 FUN | 26 STSYM | + | 28 LCSYM | 2A MAIN | 2C ROSYM | 2E | + | 30 PC | 32 NSYMS | 34 NOMAP | 36 | + | 38 OBJ | 3A | 3C OPT | 3E | + | 40 RSYM | 42 M2C | 44 SLINE | 46 DSLINE | + | 48 BSLINE*| 4A DEFD | 4C FLINE | 4E | + | 50 EHDECL*| 52 | 54 CATCH | 56 | + | 58 | 5A | 5C | 5E | + | 60 SSYM | 62 ENDM | 64 SO | 66 | + | 68 | 6A | 6C ALIAS | 6E | + | 70 | 72 | 74 | 76 | + | 78 | 7A | 7C | 7E | + | 80 LSYM | 82 BINCL | 84 SOL | 86 | + | 88 | 8A | 8C | 8E | + | 90 | 92 | 94 | 96 | + | 98 | 9A | 9C | 9E | + | A0 PSYM | A2 EINCL | A4 ENTRY | A6 | + | A8 | AA | AC | AE | + | B0 | B2 | B4 | B6 | + | B8 | BA | BC | BE | + | C0 LBRAC | C2 EXCL | C4 SCOPE | C6 | + | C8 | CA | CC | CE | + | D0 PATCH | D2 | D4 | D6 | + | D8 | DA | DC | DE | + | E0 RBRAC | E2 BCOMM | E4 ECOMM | E6 | + | E8 ECOML | EA WITH | EC | EE | + | F0 | F2 | F4 | F6 | + | F8 | FA | FC | FE LENG | + +-----------------------------------------------+ + * 50 EHDECL is also MOD2. + * 48 BSLINE is also BROWS. + */ diff --git a/external/gpl3/gdb/dist/include/aout/stab_gnu.h b/external/gpl3/gdb/dist/include/aout/stab_gnu.h new file mode 100644 index 000000000000..60b5272c59c0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/stab_gnu.h @@ -0,0 +1,55 @@ +/* gnu_stab.h Definitions for GNU extensions to STABS + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ +#ifndef __GNU_STAB__ + +/* Indicate the GNU stab.h is in use. */ + +#define __GNU_STAB__ + +#define __define_stab(NAME, CODE, STRING) NAME=CODE, +#define __define_stab_duplicate(NAME, CODE, STRING) NAME=CODE, + +enum __stab_debug_code +{ +#include "aout/stab.def" +LAST_UNUSED_STAB_CODE +}; + +#undef __define_stab + +/* Definitions of "desc" field for N_SO stabs in Solaris2. */ + +#define N_SO_AS 1 +#define N_SO_C 2 +#define N_SO_ANSI_C 3 +#define N_SO_CC 4 /* C++ */ +#define N_SO_FORTRAN 5 +#define N_SO_PASCAL 6 + +/* Solaris2: Floating point type values in basic types. */ + +#define NF_NONE 0 +#define NF_SINGLE 1 /* IEEE 32-bit */ +#define NF_DOUBLE 2 /* IEEE 64-bit */ +#define NF_COMPLEX 3 /* Fortran complex */ +#define NF_COMPLEX16 4 /* Fortran double complex */ +#define NF_COMPLEX32 5 /* Fortran complex*16 */ +#define NF_LDOUBLE 6 /* Long double (whatever that is) */ + +#endif /* __GNU_STAB_ */ diff --git a/external/gpl3/gdb/dist/include/aout/sun4.h b/external/gpl3/gdb/dist/include/aout/sun4.h new file mode 100644 index 000000000000..06f7584cf115 --- /dev/null +++ b/external/gpl3/gdb/dist/include/aout/sun4.h @@ -0,0 +1,239 @@ +/* SPARC-specific values for a.out files + + Copyright 2001, 2009, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Some systems, e.g., AIX, may have defined this in header files already + included. */ +#undef TARGET_PAGE_SIZE +#define TARGET_PAGE_SIZE 0x2000 /* 8K. aka NBPG in */ +/* Note that some SPARCs have 4K pages, some 8K, some others. */ + +#define SEG_SIZE_SPARC TARGET_PAGE_SIZE +#define SEG_SIZE_SUN3 0x20000 /* Resolution of r/w protection hw */ + +#define TEXT_START_ADDR TARGET_PAGE_SIZE /* Location 0 is not accessible */ +#define N_HEADER_IN_TEXT(x) 1 + +/* Non-default definitions of the accessor macros... */ + +/* Segment size varies on Sun-3 versus Sun-4. */ + +#define N_SEGSIZE(x) (N_MACHTYPE(x) == M_SPARC? SEG_SIZE_SPARC: \ + N_MACHTYPE(x) == M_68020? SEG_SIZE_SUN3: \ + /* Guess? */ TARGET_PAGE_SIZE) + +/* Virtual Address of text segment from the a.out file. For OMAGIC, + (almost always "unlinked .o's" these days), should be zero. + Sun added a kludge so that shared libraries linked ZMAGIC get + an address of zero if a_entry (!!!) is lower than the otherwise + expected text address. These kludges have gotta go! + For linked files, should reflect reality if we know it. */ + +#define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR \ + && (x).a_text >= EXEC_BYTES_SIZE) + +/* This differs from the version in aout64.h (which we override by defining + it here) only for NMAGIC (we return TEXT_START_ADDR+EXEC_BYTES_SIZE; + they return 0). */ + +#define N_TXTADDR(x) \ + (N_MAGIC(x)==OMAGIC? 0 \ + : (N_MAGIC(x) == ZMAGIC && (x).a_entry < TEXT_START_ADDR)? 0 \ + : TEXT_START_ADDR+EXEC_BYTES_SIZE) + +/* When a file is linked against a shared library on SunOS 4, the + dynamic bit in the exec header is set, and the first symbol in the + symbol table is __DYNAMIC. Its value is the address of the + following structure. */ + +struct external_sun4_dynamic +{ + /* The version number of the structure. SunOS 4.1.x creates files + with version number 3, which is what this structure is based on. + According to gdb, version 2 is similar. I believe that version 2 + used a different type of procedure linkage table, and there may + have been other differences. */ + bfd_byte ld_version[4]; + /* The virtual address of a 28 byte structure used in debugging. + The contents are filled in at run time by ld.so. */ + bfd_byte ldd[4]; + /* The virtual address of another structure with information about + how to relocate the executable at run time. */ + bfd_byte ld[4]; +}; + +/* The size of the debugging structure pointed to by the debugger + field of __DYNAMIC. */ +#define EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE (24) + +/* The structure pointed to by the linker field of __DYNAMIC. As far + as I can tell, most of the addresses in this structure are offsets + within the file, but some are actually virtual addresses. */ + +struct internal_sun4_dynamic_link +{ + /* Linked list of loaded objects. This is filled in at runtime by + ld.so and probably by dlopen. */ + unsigned long ld_loaded; + + /* The address of the list of names of shared objects which must be + included at runtime. Each entry in the list is 16 bytes: the 4 + byte address of the string naming the object (e.g., for -lc this + is "c"); 4 bytes of flags--the high bit is whether to search for + the object using the library path; the 2 byte major version + number; the 2 byte minor version number; the 4 byte address of + the next entry in the list (zero if this is the last entry). The + version numbers seem to only be non-zero when doing library + searching. */ + unsigned long ld_need; + + /* The address of the path to search for the shared objects which + must be included. This points to a string in PATH format which + is generated from the -L arguments to the linker. According to + the man page, ld.so implicitly adds ${LD_LIBRARY_PATH} to the + beginning of this string and /lib:/usr/lib:/usr/local/lib to the + end. The string is terminated by a null byte. This field is + zero if there is no additional path. */ + unsigned long ld_rules; + + /* The address of the global offset table. This appears to be a + virtual address, not a file offset. The first entry in the + global offset table seems to be the virtual address of the + sun4_dynamic structure (the same value as the __DYNAMIC symbol). + The global offset table is used for PIC code to hold the + addresses of variables. A dynamically linked file which does not + itself contain PIC code has a four byte global offset table. */ + unsigned long ld_got; + + /* The address of the procedure linkage table. This appears to be a + virtual address, not a file offset. + + On a SPARC, the table is composed of 12 byte entries, each of + which consists of three instructions. The first entry is + sethi %hi(0),%g1 + jmp %g1 + nop + These instructions are changed by ld.so into a jump directly into + ld.so itself. Each subsequent entry is + save %sp, -96, %sp + call

    + + The reloc_number is the number of the reloc to use to resolve + this entry. The reloc will be a JMP_SLOT reloc against some + symbol that is not defined in this object file but should be + defined in a shared object (if it is not, ld.so will report a + runtime error and exit). The constant 0x010000000 turns the + reloc number into a sethi of %g0, which does nothing since %g0 is + hardwired to zero. + + When one of these entries is executed, it winds up calling into + ld.so. ld.so looks at the reloc number, available via the return + address, to determine which entry this is. It then looks at the + reloc and patches up the entry in the table into a sethi and jmp + to the real address followed by a nop. This means that the reloc + lookup only has to happen once, and it also means that the + relocation only needs to be done if the function is actually + called. The relocation is expensive because ld.so must look up + the symbol by name. + + The size of the procedure linkage table is given by the ld_plt_sz + field. */ + unsigned long ld_plt; + + /* The address of the relocs. These are in the same format as + ordinary relocs. Symbol index numbers refer to the symbols + pointed to by ld_stab. I think the only way to determine the + number of relocs is to assume that all the bytes from ld_rel to + ld_hash contain reloc entries. */ + unsigned long ld_rel; + + /* The address of a hash table of symbols. The hash table has + roughly the same number of entries as there are dynamic symbols; + I think the only way to get the exact size is to assume that + every byte from ld_hash to ld_stab is devoted to the hash table. + + Each entry in the hash table is eight bytes. The first four + bytes are a symbol index into the dynamic symbols. The second + four bytes are the index of the next hash table entry in the + bucket. The ld_buckets field gives the number of buckets, say B. + The first B entries in the hash table each start a bucket which + is chained through the second four bytes of each entry. A value + of zero ends the chain. + + The hash function is simply + h = 0; + while (*string != '\0') + h = (h << 1) + *string++; + h &= 0x7fffffff; + + To look up a symbol, compute the hash value of the name. Take + the modulos of hash value and the number of buckets. Start at + that entry in the hash table. See if the symbol (from the first + four bytes of the hash table entry) has the name you are looking + for. If not, use the chain field (the second four bytes of the + hash table entry) to move on to the next entry in this bucket. + If the chain field is zero you have reached the end of the + bucket, and the symbol is not in the hash table. */ + unsigned long ld_hash; + + /* The address of the symbol table. This is a list of + external_nlist structures. The string indices are relative to + the ld_symbols field. I think the only way to determine the + number of symbols is to assume that all the bytes between ld_stab + and ld_symbols are external_nlist structures. */ + unsigned long ld_stab; + + /* I don't know what this is for. It seems to always be zero. */ + unsigned long ld_stab_hash; + + /* The number of buckets in the hash table. */ + unsigned long ld_buckets; + + /* The address of the symbol string table. The first string in this + string table need not be the empty string. */ + unsigned long ld_symbols; + + /* The size in bytes of the symbol string table. */ + unsigned long ld_symb_size; + + /* The size in bytes of the text segment. */ + unsigned long ld_text; + + /* The size in bytes of the procedure linkage table. */ + unsigned long ld_plt_sz; +}; + +/* The external form of the structure. */ + +struct external_sun4_dynamic_link +{ + bfd_byte ld_loaded[4]; + bfd_byte ld_need[4]; + bfd_byte ld_rules[4]; + bfd_byte ld_got[4]; + bfd_byte ld_plt[4]; + bfd_byte ld_rel[4]; + bfd_byte ld_hash[4]; + bfd_byte ld_stab[4]; + bfd_byte ld_stab_hash[4]; + bfd_byte ld_buckets[4]; + bfd_byte ld_symbols[4]; + bfd_byte ld_symb_size[4]; + bfd_byte ld_text[4]; + bfd_byte ld_plt_sz[4]; +}; diff --git a/external/gpl3/gdb/dist/include/bfdlink.h b/external/gpl3/gdb/dist/include/bfdlink.h new file mode 100644 index 000000000000..0d6e9f8aeb0d --- /dev/null +++ b/external/gpl3/gdb/dist/include/bfdlink.h @@ -0,0 +1,786 @@ +/* bfdlink.h -- header file for BFD link routines + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, + 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. + Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef BFDLINK_H +#define BFDLINK_H + +/* Which symbols to strip during a link. */ +enum bfd_link_strip +{ + strip_none, /* Don't strip any symbols. */ + strip_debugger, /* Strip debugging symbols. */ + strip_some, /* keep_hash is the list of symbols to keep. */ + strip_all /* Strip all symbols. */ +}; + +/* Which local symbols to discard during a link. This is irrelevant + if strip_all is used. */ +enum bfd_link_discard +{ + discard_sec_merge, /* Discard local temporary symbols in SEC_MERGE + sections. */ + discard_none, /* Don't discard any locals. */ + discard_l, /* Discard local temporary symbols. */ + discard_all /* Discard all locals. */ +}; + +/* Describes the type of hash table entry structure being used. + Different hash table structure have different fields and so + support different linking features. */ +enum bfd_link_hash_table_type + { + bfd_link_generic_hash_table, + bfd_link_elf_hash_table + }; + +/* These are the possible types of an entry in the BFD link hash + table. */ + +enum bfd_link_hash_type +{ + bfd_link_hash_new, /* Symbol is new. */ + bfd_link_hash_undefined, /* Symbol seen before, but undefined. */ + bfd_link_hash_undefweak, /* Symbol is weak and undefined. */ + bfd_link_hash_defined, /* Symbol is defined. */ + bfd_link_hash_defweak, /* Symbol is weak and defined. */ + bfd_link_hash_common, /* Symbol is common. */ + bfd_link_hash_indirect, /* Symbol is an indirect link. */ + bfd_link_hash_warning /* Like indirect, but warn if referenced. */ +}; + +enum bfd_link_common_skip_ar_symbols +{ + bfd_link_common_skip_none, + bfd_link_common_skip_text, + bfd_link_common_skip_data, + bfd_link_common_skip_all +}; + +struct bfd_link_hash_common_entry + { + unsigned int alignment_power; /* Alignment. */ + asection *section; /* Symbol section. */ + }; + +/* The linking routines use a hash table which uses this structure for + its elements. */ + +struct bfd_link_hash_entry +{ + /* Base hash table entry structure. */ + struct bfd_hash_entry root; + + /* Type of this entry. */ + enum bfd_link_hash_type type; + + /* A union of information depending upon the type. */ + union + { + /* Nothing is kept for bfd_hash_new. */ + /* bfd_link_hash_undefined, bfd_link_hash_undefweak. */ + struct + { + /* Undefined and common symbols are kept in a linked list through + this field. This field is present in all of the union element + so that we don't need to remove entries from the list when we + change their type. Removing entries would either require the + list to be doubly linked, which would waste more memory, or + require a traversal. When an undefined or common symbol is + created, it should be added to this list, the head of which is in + the link hash table itself. As symbols are defined, they need + not be removed from the list; anything which reads the list must + doublecheck the symbol type. + + Weak symbols are not kept on this list. + + Defined and defweak symbols use this field as a reference marker. + If the field is not NULL, or this structure is the tail of the + undefined symbol list, the symbol has been referenced. If the + symbol is undefined and becomes defined, this field will + automatically be non-NULL since the symbol will have been on the + undefined symbol list. */ + struct bfd_link_hash_entry *next; + bfd *abfd; /* BFD symbol was found in. */ + bfd *weak; /* BFD weak symbol was found in. */ + } undef; + /* bfd_link_hash_defined, bfd_link_hash_defweak. */ + struct + { + struct bfd_link_hash_entry *next; + asection *section; /* Symbol section. */ + bfd_vma value; /* Symbol value. */ + } def; + /* bfd_link_hash_indirect, bfd_link_hash_warning. */ + struct + { + struct bfd_link_hash_entry *next; + struct bfd_link_hash_entry *link; /* Real symbol. */ + const char *warning; /* Warning (bfd_link_hash_warning only). */ + } i; + /* bfd_link_hash_common. */ + struct + { + struct bfd_link_hash_entry *next; + /* The linker needs to know three things about common + symbols: the size, the alignment, and the section in + which the symbol should be placed. We store the size + here, and we allocate a small structure to hold the + section and the alignment. The alignment is stored as a + power of two. We don't store all the information + directly because we don't want to increase the size of + the union; this structure is a major space user in the + linker. */ + struct bfd_link_hash_common_entry *p; + bfd_size_type size; /* Common symbol size. */ + } c; + } u; +}; + +/* This is the link hash table. It is a derived class of + bfd_hash_table. */ + +struct bfd_link_hash_table +{ + /* The hash table itself. */ + struct bfd_hash_table table; + /* A linked list of undefined and common symbols, linked through the + next field in the bfd_link_hash_entry structure. */ + struct bfd_link_hash_entry *undefs; + /* Entries are added to the tail of the undefs list. */ + struct bfd_link_hash_entry *undefs_tail; + /* The type of the link hash table. */ + enum bfd_link_hash_table_type type; +}; + +/* Look up an entry in a link hash table. If FOLLOW is TRUE, this + follows bfd_link_hash_indirect and bfd_link_hash_warning links to + the real symbol. */ +extern struct bfd_link_hash_entry *bfd_link_hash_lookup + (struct bfd_link_hash_table *, const char *, bfd_boolean create, + bfd_boolean copy, bfd_boolean follow); + +/* Look up an entry in the main linker hash table if the symbol might + be wrapped. This should only be used for references to an + undefined symbol, not for definitions of a symbol. */ + +extern struct bfd_link_hash_entry *bfd_wrapped_link_hash_lookup + (bfd *, struct bfd_link_info *, const char *, bfd_boolean, + bfd_boolean, bfd_boolean); + +/* Traverse a link hash table. */ +extern void bfd_link_hash_traverse + (struct bfd_link_hash_table *, + bfd_boolean (*) (struct bfd_link_hash_entry *, void *), + void *); + +/* Add an entry to the undefs list. */ +extern void bfd_link_add_undef + (struct bfd_link_hash_table *, struct bfd_link_hash_entry *); + +/* Remove symbols from the undefs list that don't belong there. */ +extern void bfd_link_repair_undef_list + (struct bfd_link_hash_table *table); + +/* Read symbols and cache symbol pointer array in outsymbols. */ +extern bfd_boolean bfd_generic_link_read_symbols (bfd *); + +struct bfd_sym_chain +{ + struct bfd_sym_chain *next; + const char *name; +}; + +/* How to handle unresolved symbols. + There are four possibilities which are enumerated below: */ +enum report_method +{ + /* This is the initial value when then link_info structure is created. + It allows the various stages of the linker to determine whether they + allowed to set the value. */ + RM_NOT_YET_SET = 0, + RM_IGNORE, + RM_GENERATE_WARNING, + RM_GENERATE_ERROR +}; + +struct bfd_elf_dynamic_list; + +/* This structure holds all the information needed to communicate + between BFD and the linker when doing a link. */ + +struct bfd_link_info +{ + /* TRUE if BFD should generate a relocatable object file. */ + unsigned int relocatable: 1; + + /* TRUE if BFD should generate relocation information in the final + executable. */ + unsigned int emitrelocations: 1; + + /* TRUE if BFD should generate a "task linked" object file, + similar to relocatable but also with globals converted to + statics. */ + unsigned int task_link: 1; + + /* TRUE if BFD should generate a shared object. */ + unsigned int shared: 1; + + /* TRUE if BFD should pre-bind symbols in a shared object. */ + unsigned int symbolic: 1; + + /* TRUE if BFD should export all symbols in the dynamic symbol table + of an executable, rather than only those used. */ + unsigned int export_dynamic: 1; + + /* TRUE if shared objects should be linked directly, not shared. */ + unsigned int static_link: 1; + + /* TRUE if the output file should be in a traditional format. This + is equivalent to the setting of the BFD_TRADITIONAL_FORMAT flag + on the output file, but may be checked when reading the input + files. */ + unsigned int traditional_format: 1; + + /* TRUE if we want to produced optimized output files. This might + need much more time and therefore must be explicitly selected. */ + unsigned int optimize: 1; + + /* TRUE if ok to have multiple definition. */ + unsigned int allow_multiple_definition: 1; + + /* TRUE if ok to have version with no definition. */ + unsigned int allow_undefined_version: 1; + + /* TRUE if a default symbol version should be created and used for + exported symbols. */ + unsigned int create_default_symver: 1; + + /* TRUE if a default symbol version should be created and used for + imported symbols. */ + unsigned int default_imported_symver: 1; + + /* TRUE if symbols should be retained in memory, FALSE if they + should be freed and reread. */ + unsigned int keep_memory: 1; + + /* TRUE if every symbol should be reported back via the notice + callback. */ + unsigned int notice_all: 1; + + /* TRUE if executable should not contain copy relocs. + Setting this true may result in a non-sharable text segment. */ + unsigned int nocopyreloc: 1; + + /* TRUE if the new ELF dynamic tags are enabled. */ + unsigned int new_dtags: 1; + + /* TRUE if non-PLT relocs should be merged into one reloc section + and sorted so that relocs against the same symbol come together. */ + unsigned int combreloc: 1; + + /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment + should be created. */ + unsigned int eh_frame_hdr: 1; + + /* TRUE if global symbols in discarded sections should be stripped. */ + unsigned int strip_discarded: 1; + + /* TRUE if generating a position independent executable. */ + unsigned int pie: 1; + + /* TRUE if generating an executable, position independent or not. */ + unsigned int executable : 1; + + /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W|PF_X + flags. */ + unsigned int execstack: 1; + + /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W + flags. */ + unsigned int noexecstack: 1; + + /* TRUE if PT_GNU_RELRO segment should be created. */ + unsigned int relro: 1; + + /* TRUE if we should warn when adding a DT_TEXTREL to a shared object. */ + unsigned int warn_shared_textrel: 1; + + /* TRUE if we should warn alternate ELF machine code. */ + unsigned int warn_alternate_em: 1; + + /* TRUE if unreferenced sections should be removed. */ + unsigned int gc_sections: 1; + + /* TRUE if user shoudl be informed of removed unreferenced sections. */ + unsigned int print_gc_sections: 1; + + /* TRUE if .hash section should be created. */ + unsigned int emit_hash: 1; + + /* TRUE if .gnu.hash section should be created. */ + unsigned int emit_gnu_hash: 1; + + /* If TRUE reduce memory overheads, at the expense of speed. This will + cause map file generation to use an O(N^2) algorithm and disable + caching ELF symbol buffer. */ + unsigned int reduce_memory_overheads: 1; + + /* TRUE if all data symbols should be dynamic. */ + unsigned int dynamic_data: 1; + + /* TRUE if some symbols have to be dynamic, controlled by + --dynamic-list command line options. */ + unsigned int dynamic: 1; + + /* Non-NULL if .note.gnu.build-id section should be created. */ + char *emit_note_gnu_build_id; + + /* What to do with unresolved symbols in an object file. + When producing executables the default is GENERATE_ERROR. + When producing shared libraries the default is IGNORE. The + assumption with shared libraries is that the reference will be + resolved at load/execution time. */ + enum report_method unresolved_syms_in_objects; + + /* What to do with unresolved symbols in a shared library. + The same defaults apply. */ + enum report_method unresolved_syms_in_shared_libs; + + /* Which symbols to strip. */ + enum bfd_link_strip strip; + + /* Which local symbols to discard. */ + enum bfd_link_discard discard; + + /* Criteria for skipping symbols when determining + whether to include an object from an archive. */ + enum bfd_link_common_skip_ar_symbols common_skip_ar_symbols; + + /* Char that may appear as the first char of a symbol, but should be + skipped (like symbol_leading_char) when looking up symbols in + wrap_hash. Used by PowerPC Linux for 'dot' symbols. */ + char wrap_char; + + /* Separator between archive and filename in linker script filespecs. */ + char path_separator; + + /* Function callbacks. */ + const struct bfd_link_callbacks *callbacks; + + /* Hash table handled by BFD. */ + struct bfd_link_hash_table *hash; + + /* Hash table of symbols to keep. This is NULL unless strip is + strip_some. */ + struct bfd_hash_table *keep_hash; + + /* Hash table of symbols to report back via the notice callback. If + this is NULL, and notice_all is FALSE, then no symbols are + reported back. */ + struct bfd_hash_table *notice_hash; + + /* Hash table of symbols which are being wrapped (the --wrap linker + option). If this is NULL, no symbols are being wrapped. */ + struct bfd_hash_table *wrap_hash; + + /* The output BFD. */ + bfd *output_bfd; + + /* The list of input BFD's involved in the link. These are chained + together via the link_next field. */ + bfd *input_bfds; + bfd **input_bfds_tail; + + /* If a symbol should be created for each input BFD, this is section + where those symbols should be placed. It must be a section in + the output BFD. It may be NULL, in which case no such symbols + will be created. This is to support CREATE_OBJECT_SYMBOLS in the + linker command language. */ + asection *create_object_symbols_section; + + /* List of global symbol names that are starting points for marking + sections against garbage collection. */ + struct bfd_sym_chain *gc_sym_list; + + /* If a base output file is wanted, then this points to it */ + void *base_file; + + /* The function to call when the executable or shared object is + loaded. */ + const char *init_function; + + /* The function to call when the executable or shared object is + unloaded. */ + const char *fini_function; + + /* Number of relaxation passes. Usually only one relaxation pass + is needed. But a backend can have as many relaxation passes as + necessary. During bfd_relax_section call, it is set to the + current pass, starting from 0. */ + int relax_pass; + + /* Number of relaxation trips. This number is incremented every + time the relaxation pass is restarted due to a previous + relaxation returning true in *AGAIN. */ + int relax_trip; + + /* Non-zero if auto-import thunks for DATA items in pei386 DLLs + should be generated/linked against. Set to 1 if this feature + is explicitly requested by the user, -1 if enabled by default. */ + int pei386_auto_import; + + /* Non-zero if runtime relocs for DATA items with non-zero addends + in pei386 DLLs should be generated. Set to 1 if this feature + is explicitly requested by the user, -1 if enabled by default. */ + int pei386_runtime_pseudo_reloc; + + /* How many spare .dynamic DT_NULL entries should be added? */ + unsigned int spare_dynamic_tags; + + /* May be used to set DT_FLAGS for ELF. */ + bfd_vma flags; + + /* May be used to set DT_FLAGS_1 for ELF. */ + bfd_vma flags_1; + + /* Start and end of RELRO region. */ + bfd_vma relro_start, relro_end; + + /* List of symbols should be dynamic. */ + struct bfd_elf_dynamic_list *dynamic_list; +}; + +/* This structures holds a set of callback functions. These are called + by the BFD linker routines. Except for the info functions, the first + argument to each callback function is the bfd_link_info structure + being used and each function returns a boolean value. If the + function returns FALSE, then the BFD function which called it should + return with a failure indication. */ + +struct bfd_link_callbacks +{ + /* A function which is called when an object is added from an + archive. ABFD is the archive element being added. NAME is the + name of the symbol which caused the archive element to be pulled + in. This function may set *SUBSBFD to point to an alternative + BFD from which symbols should in fact be added in place of the + original BFD's symbols. */ + bfd_boolean (*add_archive_element) + (struct bfd_link_info *, bfd *abfd, const char *name, bfd **subsbfd); + /* A function which is called when a symbol is found with multiple + definitions. NAME is the symbol which is defined multiple times. + OBFD is the old BFD, OSEC is the old section, OVAL is the old + value, NBFD is the new BFD, NSEC is the new section, and NVAL is + the new value. OBFD may be NULL. OSEC and NSEC may be + bfd_com_section or bfd_ind_section. */ + bfd_boolean (*multiple_definition) + (struct bfd_link_info *, const char *name, + bfd *obfd, asection *osec, bfd_vma oval, + bfd *nbfd, asection *nsec, bfd_vma nval); + /* A function which is called when a common symbol is defined + multiple times. NAME is the symbol appearing multiple times. + OBFD is the BFD of the existing symbol; it may be NULL if this is + not known. OTYPE is the type of the existing symbol, which may + be bfd_link_hash_defined, bfd_link_hash_defweak, + bfd_link_hash_common, or bfd_link_hash_indirect. If OTYPE is + bfd_link_hash_common, OSIZE is the size of the existing symbol. + NBFD is the BFD of the new symbol. NTYPE is the type of the new + symbol, one of bfd_link_hash_defined, bfd_link_hash_common, or + bfd_link_hash_indirect. If NTYPE is bfd_link_hash_common, NSIZE + is the size of the new symbol. */ + bfd_boolean (*multiple_common) + (struct bfd_link_info *, const char *name, + bfd *obfd, enum bfd_link_hash_type otype, bfd_vma osize, + bfd *nbfd, enum bfd_link_hash_type ntype, bfd_vma nsize); + /* A function which is called to add a symbol to a set. ENTRY is + the link hash table entry for the set itself (e.g., + __CTOR_LIST__). RELOC is the relocation to use for an entry in + the set when generating a relocatable file, and is also used to + get the size of the entry when generating an executable file. + ABFD, SEC and VALUE identify the value to add to the set. */ + bfd_boolean (*add_to_set) + (struct bfd_link_info *, struct bfd_link_hash_entry *entry, + bfd_reloc_code_real_type reloc, bfd *abfd, asection *sec, bfd_vma value); + /* A function which is called when the name of a g++ constructor or + destructor is found. This is only called by some object file + formats. CONSTRUCTOR is TRUE for a constructor, FALSE for a + destructor. This will use BFD_RELOC_CTOR when generating a + relocatable file. NAME is the name of the symbol found. ABFD, + SECTION and VALUE are the value of the symbol. */ + bfd_boolean (*constructor) + (struct bfd_link_info *, bfd_boolean constructor, const char *name, + bfd *abfd, asection *sec, bfd_vma value); + /* A function which is called to issue a linker warning. For + example, this is called when there is a reference to a warning + symbol. WARNING is the warning to be issued. SYMBOL is the name + of the symbol which triggered the warning; it may be NULL if + there is none. ABFD, SECTION and ADDRESS identify the location + which trigerred the warning; either ABFD or SECTION or both may + be NULL if the location is not known. */ + bfd_boolean (*warning) + (struct bfd_link_info *, const char *warning, const char *symbol, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a relocation is attempted against + an undefined symbol. NAME is the symbol which is undefined. + ABFD, SECTION and ADDRESS identify the location from which the + reference is made. IS_FATAL indicates whether an undefined symbol is + a fatal error or not. In some cases SECTION may be NULL. */ + bfd_boolean (*undefined_symbol) + (struct bfd_link_info *, const char *name, bfd *abfd, + asection *section, bfd_vma address, bfd_boolean is_fatal); + /* A function which is called when a reloc overflow occurs. ENTRY is + the link hash table entry for the symbol the reloc is against. + NAME is the name of the local symbol or section the reloc is + against, RELOC_NAME is the name of the relocation, and ADDEND is + any addend that is used. ABFD, SECTION and ADDRESS identify the + location at which the overflow occurs; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*reloc_overflow) + (struct bfd_link_info *, struct bfd_link_hash_entry *entry, + const char *name, const char *reloc_name, bfd_vma addend, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a dangerous reloc is performed. + MESSAGE is an appropriate message. + ABFD, SECTION and ADDRESS identify the location at which the + problem occurred; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*reloc_dangerous) + (struct bfd_link_info *, const char *message, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a reloc is found to be attached + to a symbol which is not being written out. NAME is the name of + the symbol. ABFD, SECTION and ADDRESS identify the location of + the reloc; if this is the result of a + bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then + ABFD will be NULL. */ + bfd_boolean (*unattached_reloc) + (struct bfd_link_info *, const char *name, + bfd *abfd, asection *section, bfd_vma address); + /* A function which is called when a symbol in notice_hash is + defined or referenced. NAME is the symbol. ABFD, SECTION and + ADDRESS are the value of the symbol. If SECTION is + bfd_und_section, this is a reference. */ + bfd_boolean (*notice) + (struct bfd_link_info *, const char *name, + bfd *abfd, asection *section, bfd_vma address); + /* Error or warning link info message. */ + void (*einfo) + (const char *fmt, ...); + /* General link info message. */ + void (*info) + (const char *fmt, ...); + /* Message to be printed in linker map file. */ + void (*minfo) + (const char *fmt, ...); + /* This callback provides a chance for users of the BFD library to + override its decision about whether to place two adjacent sections + into the same segment. */ + bfd_boolean (*override_segment_assignment) + (struct bfd_link_info *, bfd * abfd, + asection * current_section, asection * previous_section, + bfd_boolean new_segment); +}; + +/* The linker builds link_order structures which tell the code how to + include input data in the output file. */ + +/* These are the types of link_order structures. */ + +enum bfd_link_order_type +{ + bfd_undefined_link_order, /* Undefined. */ + bfd_indirect_link_order, /* Built from a section. */ + bfd_data_link_order, /* Set to explicit data. */ + bfd_section_reloc_link_order, /* Relocate against a section. */ + bfd_symbol_reloc_link_order /* Relocate against a symbol. */ +}; + +/* This is the link_order structure itself. These form a chain + attached to the output section whose contents they are describing. */ + +struct bfd_link_order +{ + /* Next link_order in chain. */ + struct bfd_link_order *next; + /* Type of link_order. */ + enum bfd_link_order_type type; + /* Offset within output section. */ + bfd_vma offset; + /* Size within output section. */ + bfd_size_type size; + /* Type specific information. */ + union + { + struct + { + /* Section to include. If this is used, then + section->output_section must be the section the + link_order is attached to, section->output_offset must + equal the link_order offset field, and section->size + must equal the link_order size field. Maybe these + restrictions should be relaxed someday. */ + asection *section; + } indirect; + struct + { + /* Size of contents, or zero when contents size == size + within output section. + A non-zero value allows filling of the output section + with an arbitrary repeated pattern. */ + unsigned int size; + /* Data to put into file. */ + bfd_byte *contents; + } data; + struct + { + /* Description of reloc to generate. Used for + bfd_section_reloc_link_order and + bfd_symbol_reloc_link_order. */ + struct bfd_link_order_reloc *p; + } reloc; + } u; +}; + +/* A linker order of type bfd_section_reloc_link_order or + bfd_symbol_reloc_link_order means to create a reloc against a + section or symbol, respectively. This is used to implement -Ur to + generate relocs for the constructor tables. The + bfd_link_order_reloc structure describes the reloc that BFD should + create. It is similar to a arelent, but I didn't use arelent + because the linker does not know anything about most symbols, and + any asymbol structure it creates will be partially meaningless. + This information could logically be in the bfd_link_order struct, + but I didn't want to waste the space since these types of relocs + are relatively rare. */ + +struct bfd_link_order_reloc +{ + /* Reloc type. */ + bfd_reloc_code_real_type reloc; + + union + { + /* For type bfd_section_reloc_link_order, this is the section + the reloc should be against. This must be a section in the + output BFD, not any of the input BFDs. */ + asection *section; + /* For type bfd_symbol_reloc_link_order, this is the name of the + symbol the reloc should be against. */ + const char *name; + } u; + + /* Addend to use. The object file should contain zero. The BFD + backend is responsible for filling in the contents of the object + file correctly. For some object file formats (e.g., COFF) the + addend must be stored into in the object file, and for some + (e.g., SPARC a.out) it is kept in the reloc. */ + bfd_vma addend; +}; + +/* Allocate a new link_order for a section. */ +extern struct bfd_link_order *bfd_new_link_order (bfd *, asection *); + +/* These structures are used to describe version information for the + ELF linker. These structures could be manipulated entirely inside + BFD, but it would be a pain. Instead, the regular linker sets up + these structures, and then passes them into BFD. */ + +/* Glob pattern for a version. */ + +struct bfd_elf_version_expr +{ + /* Next glob pattern for this version. */ + struct bfd_elf_version_expr *next; + /* Glob pattern. */ + const char *pattern; + /* Set if pattern is not a glob. */ + unsigned int literal : 1; + /* Defined by ".symver". */ + unsigned int symver : 1; + /* Defined by version script. */ + unsigned int script : 1; + /* Pattern type. */ +#define BFD_ELF_VERSION_C_TYPE 1 +#define BFD_ELF_VERSION_CXX_TYPE 2 +#define BFD_ELF_VERSION_JAVA_TYPE 4 + unsigned int mask : 3; +}; + +struct bfd_elf_version_expr_head +{ + /* List of all patterns, both wildcards and non-wildcards. */ + struct bfd_elf_version_expr *list; + /* Hash table for non-wildcards. */ + void *htab; + /* Remaining patterns. */ + struct bfd_elf_version_expr *remaining; + /* What kind of pattern types are present in list (bitmask). */ + unsigned int mask; +}; + +/* Version dependencies. */ + +struct bfd_elf_version_deps +{ + /* Next dependency for this version. */ + struct bfd_elf_version_deps *next; + /* The version which this version depends upon. */ + struct bfd_elf_version_tree *version_needed; +}; + +/* A node in the version tree. */ + +struct bfd_elf_version_tree +{ + /* Next version. */ + struct bfd_elf_version_tree *next; + /* Name of this version. */ + const char *name; + /* Version number. */ + unsigned int vernum; + /* Regular expressions for global symbols in this version. */ + struct bfd_elf_version_expr_head globals; + /* Regular expressions for local symbols in this version. */ + struct bfd_elf_version_expr_head locals; + /* List of versions which this version depends upon. */ + struct bfd_elf_version_deps *deps; + /* Index of the version name. This is used within BFD. */ + unsigned int name_indx; + /* Whether this version tree was used. This is used within BFD. */ + int used; + /* Matching hook. */ + struct bfd_elf_version_expr *(*match) + (struct bfd_elf_version_expr_head *head, + struct bfd_elf_version_expr *prev, const char *sym); +}; + +struct bfd_elf_dynamic_list +{ + struct bfd_elf_version_expr_head head; + struct bfd_elf_version_expr *(*match) + (struct bfd_elf_version_expr_head *head, + struct bfd_elf_version_expr *prev, const char *sym); +}; + +#endif diff --git a/external/gpl3/gdb/dist/include/binary-io.h b/external/gpl3/gdb/dist/include/binary-io.h new file mode 100644 index 000000000000..2984271f7e3a --- /dev/null +++ b/external/gpl3/gdb/dist/include/binary-io.h @@ -0,0 +1,62 @@ +/* Binary mode I/O. + Copyright (C) 2001, 2003, 2005, 2008 Free Software Foundation, Inc. + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef _BINARY_H +#define _BINARY_H + +/* Include this header after and , because + systems that distinguish between text and binary I/O usually + define O_BINARY in , and the MSVC7 doesn't + like to be included after '#define fileno ...' + + We don't include here because not all systems have + that header. */ + +#if !defined O_BINARY && defined _O_BINARY + /* For MSC-compatible compilers. */ +# define O_BINARY _O_BINARY +# define O_TEXT _O_TEXT +#endif +#ifdef __BEOS__ + /* BeOS 5 has O_BINARY and O_TEXT, but they have no effect. */ +# undef O_BINARY +# undef O_TEXT +#endif +#if O_BINARY +# if defined __EMX__ || defined __DJGPP__ || defined __CYGWIN__ +# include /* declares setmode() */ +# else +# define setmode _setmode +# undef fileno +# define fileno _fileno +# endif +# ifdef __DJGPP__ +# include /* declares isatty() */ +# /* Avoid putting stdin/stdout in binary mode if it is connected to the +# console, because that would make it impossible for the user to +# interrupt the program through Ctrl-C or Ctrl-Break. */ +# define SET_BINARY(fd) (!isatty (fd) ? (setmode (fd, O_BINARY), 0) : 0) +# else +# define SET_BINARY(fd) setmode (fd, O_BINARY) +# endif +#else + /* On reasonable systems, binary I/O is the default. */ +# undef O_BINARY +# define O_BINARY 0 +# define SET_BINARY(fd) /* nothing */ +#endif + +#endif /* _BINARY_H */ diff --git a/external/gpl3/gdb/dist/include/bout.h b/external/gpl3/gdb/dist/include/bout.h new file mode 100644 index 000000000000..4a302283c2e9 --- /dev/null +++ b/external/gpl3/gdb/dist/include/bout.h @@ -0,0 +1,192 @@ +/* This file is a modified version of 'a.out.h'. It is to be used in all + GNU tools modified to support the i80960 (or tools that operate on + object files created by such tools). + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* All i80960 development is done in a CROSS-DEVELOPMENT environment. I.e., + object code is generated on, and executed under the direction of a symbolic + debugger running on, a host system. We do not want to be subject to the + vagaries of which host it is or whether it supports COFF or a.out format, + or anything else. We DO want to: + + o always generate the same format object files, regardless of host. + + o have an 'a.out' header that we can modify for our own purposes + (the 80960 is typically an embedded processor and may require + enhanced linker support that the normal a.out.h header can't + accommodate). + + As for byte-ordering, the following rules apply: + + o Text and data that is actually downloaded to the target is always + in i80960 (little-endian) order. + + o All other numbers (in the header, symbols, relocation directives) + are in host byte-order: object files CANNOT be lifted from a + little-end host and used on a big-endian (or vice versa) without + modification. + ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER + FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO + USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== + + o The downloader ('comm960') takes care to generate a pseudo-header + with correct (i80960) byte-ordering before shipping text and data + off to the NINDY monitor in the target systems. Symbols and + relocation info are never sent to the target. */ + +#define BMAGIC 0415 +/* We don't accept the following (see N_BADMAG macro). + They're just here so GNU code will compile. */ +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ + +/* FILE HEADER + All 'lengths' are given as a number of bytes. + All 'alignments' are for relinkable files only; an alignment of + 'n' indicates the corresponding segment must begin at an + address that is a multiple of (2**n). */ +struct external_exec + { + /* Standard stuff */ + unsigned char e_info[4]; /* Identifies this as a b.out file */ + unsigned char e_text[4]; /* Length of text */ + unsigned char e_data[4]; /* Length of data */ + unsigned char e_bss[4]; /* Length of uninitialized data area */ + unsigned char e_syms[4]; /* Length of symbol table */ + unsigned char e_entry[4]; /* Runtime start address */ + unsigned char e_trsize[4]; /* Length of text relocation info */ + unsigned char e_drsize[4]; /* Length of data relocation info */ + + /* Added for i960 */ + unsigned char e_tload[4]; /* Text runtime load address */ + unsigned char e_dload[4]; /* Data runtime load address */ + unsigned char e_talign[1]; /* Alignment of text segment */ + unsigned char e_dalign[1]; /* Alignment of data segment */ + unsigned char e_balign[1]; /* Alignment of bss segment */ + unsigned char e_relaxable[1];/* Assembled with enough info to allow linker to relax */ + }; + +#define EXEC_BYTES_SIZE (sizeof (struct external_exec)) + +/* These macros use the a_xxx field names, since they operate on the exec + structure after it's been byte-swapped and realigned on the host machine. */ +#define N_BADMAG(x) (((x).a_info)!=BMAGIC) +#define N_TXTOFF(x) EXEC_BYTES_SIZE +#define N_DATOFF(x) ( N_TXTOFF(x) + (x).a_text ) +#define N_TROFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_TRELOFF N_TROFF +#define N_DROFF(x) ( N_TROFF(x) + (x).a_trsize ) +#define N_DRELOFF N_DROFF +#define N_SYMOFF(x) ( N_DROFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_DATADDR(x) ( (x).a_dload ) + +/* Address of text segment in memory after it is loaded. */ +#if !defined (N_TXTADDR) +#define N_TXTADDR(x) 0 +#endif + +/* A single entry in the symbol table. */ +struct nlist + { + union + { + char* n_name; + struct nlist * n_next; + long n_strx; /* Index into string table */ + } n_un; + + unsigned char n_type; /* See below */ + char n_other; /* Used in i80960 support -- see below */ + short n_desc; + unsigned long n_value; + }; + + +/* Legal values of n_type. */ +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol */ +#define N_TEXT 4 /* Text symbol */ +#define N_DATA 6 /* Data symbol */ +#define N_BSS 8 /* BSS symbol */ +#define N_FN 31 /* Filename symbol */ + +#define N_EXT 1 /* External symbol (OR'd in with one of above) */ +#define N_TYPE 036 /* Mask for all the type bits */ +#define N_STAB 0340 /* Mask for all bits used for SDB entries */ + +/* MEANING OF 'n_other' + + If non-zero, the 'n_other' fields indicates either a leaf procedure or + a system procedure, as follows: + + 1 <= n_other <= 32 : + The symbol is the entry point to a system procedure. + 'n_value' is the address of the entry, as for any other + procedure. The system procedure number (which can be used in + a 'calls' instruction) is (n_other-1). These entries come from + '.sysproc' directives. + + n_other == N_CALLNAME + the symbol is the 'call' entry point to a leaf procedure. + The *next* symbol in the symbol table must be the corresponding + 'bal' entry point to the procedure (see following). These + entries come from '.leafproc' directives in which two different + symbols are specified (the first one is represented here). + + + n_other == N_BALNAME + the symbol is the 'bal' entry point to a leaf procedure. + These entries result from '.leafproc' directives in which only + one symbol is specified, or in which the same symbol is + specified twice. + + Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry, + but not every N_BALNAME entry must have an N_CALLNAME entry. */ +#define N_CALLNAME ((char)-1) +#define N_BALNAME ((char)-2) +#define IS_CALLNAME(x) (N_CALLNAME == (x)) +#define IS_BALNAME(x) (N_BALNAME == (x)) +#define IS_OTHER(x) ((x)>0 && (x) <=32) + +#define b_out_relocation_info relocation_info +struct relocation_info + { + int r_address; /* File address of item to be relocated. */ + unsigned +#define r_index r_symbolnum + r_symbolnum:24, /* Index of symbol on which relocation is based, + if r_extern is set. Otherwise set to + either N_TEXT, N_DATA, or N_BSS to + indicate section on which relocation is + based. */ + r_pcrel:1, /* 1 => relocate PC-relative; else absolute + On i960, pc-relative implies 24-bit + address, absolute implies 32-bit. */ + r_length:2, /* Number of bytes to relocate: + 0 => 1 byte + 1 => 2 bytes -- used for 13 bit pcrel + 2 => 4 bytes. */ + r_extern:1, + r_bsr:1, /* Something for the GNU NS32K assembler. */ + r_disp:1, /* Something for the GNU NS32K assembler. */ + r_callj:1, /* 1 if relocation target is an i960 'callj'. */ + r_relaxable:1; /* 1 if enough info is left to relax the data. */ +}; diff --git a/external/gpl3/gdb/dist/include/cgen/ChangeLog b/external/gpl3/gdb/dist/include/cgen/ChangeLog new file mode 100644 index 000000000000..a8d5df9e6c2b --- /dev/null +++ b/external/gpl3/gdb/dist/include/cgen/ChangeLog @@ -0,0 +1,10 @@ +2010-01-05 Doug Evans + + * basic-modes.h (MAKEDI): New macro. + +2009-10-23 Doug Evans + + * basic-modes.h: New file. Moved here from opcodes/cgen-types.h. + * basic-ops.h: New file. Moved here from opcodes/cgen-ops.h. + * bitset.h: New file. Moved here from ../opcode/cgen-bitset.h. + Update license to GPL v3. diff --git a/external/gpl3/gdb/dist/include/cgen/basic-modes.h b/external/gpl3/gdb/dist/include/cgen/basic-modes.h new file mode 100644 index 000000000000..bd87f3acb06d --- /dev/null +++ b/external/gpl3/gdb/dist/include/cgen/basic-modes.h @@ -0,0 +1,52 @@ +/* Basic CGEN modes. + Copyright 2005, 2007, 2009 Free Software Foundation, Inc. + Contributed by Red Hat. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING3. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef CGEN_BASIC_MODES_H +#define CGEN_BASIC_MODES_H + +/* This file doesn't contain all modes, + just the basic/portable ones. + It also provides access to stdint.h (*1) so the includer doesn't have + to deal with the portability issues. + (*1): To the extent that bfd_stdint.h does for now. */ + +/* IWBN to avoid unnecessary dependencies on bfd-anything. */ +#include "bfd_stdint.h" + +typedef int8_t QI; +typedef uint8_t UQI; + +typedef int16_t HI; +typedef uint16_t UHI; + +typedef int32_t SI; +typedef uint32_t USI; + +typedef int64_t DI; +typedef uint64_t UDI; + +typedef int INT; +typedef unsigned int UINT; + +/* Cover macro to create a 64-bit integer. */ +#define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo))) + +#endif /* CGEN_BASIC_MODES_H */ diff --git a/external/gpl3/gdb/dist/include/cgen/basic-ops.h b/external/gpl3/gdb/dist/include/cgen/basic-ops.h new file mode 100644 index 000000000000..324f0b15ebdb --- /dev/null +++ b/external/gpl3/gdb/dist/include/cgen/basic-ops.h @@ -0,0 +1,347 @@ +/* Basic semantics ops support for CGEN. + Copyright 2005, 2007, 2009 Free Software Foundation, Inc. + Contributed by Red Hat. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING3. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef CGEN_BASIC_OPS_H +#define CGEN_BASIC_OPS_H + +#include + +#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE) +#define SEMOPS_DEFINE_INLINE +#define SEMOPS_INLINE extern inline +#else +#define SEMOPS_INLINE +#endif + +/* These don't really have a mode. */ +#define ANDIF(x, y) ((x) && (y)) +#define ORIF(x, y) ((x) || (y)) + +#define SUBBI(x, y) ((x) - (y)) +#define ANDBI(x, y) ((x) & (y)) +#define ORBI(x, y) ((x) | (y)) +#define XORBI(x, y) ((x) ^ (y)) +#define NEGBI(x) (- (x)) +#define NOTBI(x) (! (BI) (x)) +#define INVBI(x) (~ (x)) +#define EQBI(x, y) ((BI) (x) == (BI) (y)) +#define NEBI(x, y) ((BI) (x) != (BI) (y)) +#define LTBI(x, y) ((BI) (x) < (BI) (y)) +#define LEBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTBI(x, y) ((BI) (x) > (BI) (y)) +#define GEBI(x, y) ((BI) (x) >= (BI) (y)) +#define LTUBI(x, y) ((BI) (x) < (BI) (y)) +#define LEUBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTUBI(x, y) ((BI) (x) > (BI) (y)) +#define GEUBI(x, y) ((BI) (x) >= (BI) (y)) + +#define ADDQI(x, y) ((x) + (y)) +#define SUBQI(x, y) ((x) - (y)) +#define MULQI(x, y) ((x) * (y)) +#define DIVQI(x, y) ((QI) (x) / (QI) (y)) +#define UDIVQI(x, y) ((UQI) (x) / (UQI) (y)) +#define MODQI(x, y) ((QI) (x) % (QI) (y)) +#define UMODQI(x, y) ((UQI) (x) % (UQI) (y)) +#define SRAQI(x, y) ((QI) (x) >> (y)) +#define SRLQI(x, y) ((UQI) (x) >> (y)) +#define SLLQI(x, y) ((UQI) (x) << (y)) +extern QI RORQI (QI, int); +extern QI ROLQI (QI, int); +#define ANDQI(x, y) ((x) & (y)) +#define ORQI(x, y) ((x) | (y)) +#define XORQI(x, y) ((x) ^ (y)) +#define NEGQI(x) (- (x)) +#define NOTQI(x) (! (QI) (x)) +#define INVQI(x) (~ (x)) +#define ABSQI(x) ((x) < 0 ? -(x) : (x)) +#define EQQI(x, y) ((QI) (x) == (QI) (y)) +#define NEQI(x, y) ((QI) (x) != (QI) (y)) +#define LTQI(x, y) ((QI) (x) < (QI) (y)) +#define LEQI(x, y) ((QI) (x) <= (QI) (y)) +#define GTQI(x, y) ((QI) (x) > (QI) (y)) +#define GEQI(x, y) ((QI) (x) >= (QI) (y)) +#define LTUQI(x, y) ((UQI) (x) < (UQI) (y)) +#define LEUQI(x, y) ((UQI) (x) <= (UQI) (y)) +#define GTUQI(x, y) ((UQI) (x) > (UQI) (y)) +#define GEUQI(x, y) ((UQI) (x) >= (UQI) (y)) + +#define ADDHI(x, y) ((x) + (y)) +#define SUBHI(x, y) ((x) - (y)) +#define MULHI(x, y) ((x) * (y)) +#define DIVHI(x, y) ((HI) (x) / (HI) (y)) +#define UDIVHI(x, y) ((UHI) (x) / (UHI) (y)) +#define MODHI(x, y) ((HI) (x) % (HI) (y)) +#define UMODHI(x, y) ((UHI) (x) % (UHI) (y)) +#define SRAHI(x, y) ((HI) (x) >> (y)) +#define SRLHI(x, y) ((UHI) (x) >> (y)) +#define SLLHI(x, y) ((UHI) (x) << (y)) +extern HI RORHI (HI, int); +extern HI ROLHI (HI, int); +#define ANDHI(x, y) ((x) & (y)) +#define ORHI(x, y) ((x) | (y)) +#define XORHI(x, y) ((x) ^ (y)) +#define NEGHI(x) (- (x)) +#define NOTHI(x) (! (HI) (x)) +#define INVHI(x) (~ (x)) +#define ABSHI(x) ((x) < 0 ? -(x) : (x)) +#define EQHI(x, y) ((HI) (x) == (HI) (y)) +#define NEHI(x, y) ((HI) (x) != (HI) (y)) +#define LTHI(x, y) ((HI) (x) < (HI) (y)) +#define LEHI(x, y) ((HI) (x) <= (HI) (y)) +#define GTHI(x, y) ((HI) (x) > (HI) (y)) +#define GEHI(x, y) ((HI) (x) >= (HI) (y)) +#define LTUHI(x, y) ((UHI) (x) < (UHI) (y)) +#define LEUHI(x, y) ((UHI) (x) <= (UHI) (y)) +#define GTUHI(x, y) ((UHI) (x) > (UHI) (y)) +#define GEUHI(x, y) ((UHI) (x) >= (UHI) (y)) + +#define ADDSI(x, y) ((x) + (y)) +#define SUBSI(x, y) ((x) - (y)) +#define MULSI(x, y) ((x) * (y)) +#define DIVSI(x, y) ((SI) (x) / (SI) (y)) +#define UDIVSI(x, y) ((USI) (x) / (USI) (y)) +#define MODSI(x, y) ((SI) (x) % (SI) (y)) +#define UMODSI(x, y) ((USI) (x) % (USI) (y)) +#define SRASI(x, y) ((SI) (x) >> (y)) +#define SRLSI(x, y) ((USI) (x) >> (y)) +#define SLLSI(x, y) ((USI) (x) << (y)) +extern SI RORSI (SI, int); +extern SI ROLSI (SI, int); +#define ANDSI(x, y) ((x) & (y)) +#define ORSI(x, y) ((x) | (y)) +#define XORSI(x, y) ((x) ^ (y)) +#define NEGSI(x) (- (x)) +#define NOTSI(x) (! (SI) (x)) +#define INVSI(x) (~ (x)) +#define ABSSI(x) ((x) < 0 ? -(x) : (x)) +#define EQSI(x, y) ((SI) (x) == (SI) (y)) +#define NESI(x, y) ((SI) (x) != (SI) (y)) +#define LTSI(x, y) ((SI) (x) < (SI) (y)) +#define LESI(x, y) ((SI) (x) <= (SI) (y)) +#define GTSI(x, y) ((SI) (x) > (SI) (y)) +#define GESI(x, y) ((SI) (x) >= (SI) (y)) +#define LTUSI(x, y) ((USI) (x) < (USI) (y)) +#define LEUSI(x, y) ((USI) (x) <= (USI) (y)) +#define GTUSI(x, y) ((USI) (x) > (USI) (y)) +#define GEUSI(x, y) ((USI) (x) >= (USI) (y)) + +#ifdef DI_FN_SUPPORT +extern DI ADDDI (DI, DI); +extern DI SUBDI (DI, DI); +extern DI MULDI (DI, DI); +extern DI DIVDI (DI, DI); +extern DI UDIVDI (DI, DI); +extern DI MODDI (DI, DI); +extern DI UMODDI (DI, DI); +extern DI SRADI (DI, int); +extern UDI SRLDI (UDI, int); +extern UDI SLLDI (UDI, int); +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +extern DI ANDDI (DI, DI); +extern DI ORDI (DI, DI); +extern DI XORDI (DI, DI); +extern DI NEGDI (DI); +extern int NOTDI (DI); +extern DI INVDI (DI); +extern int EQDI (DI, DI); +extern int NEDI (DI, DI); +extern int LTDI (DI, DI); +extern int LEDI (DI, DI); +extern int GTDI (DI, DI); +extern int GEDI (DI, DI); +extern int LTUDI (UDI, UDI); +extern int LEUDI (UDI, UDI); +extern int GTUDI (UDI, UDI); +extern int GEUDI (UDI, UDI); +#else /* ! DI_FN_SUPPORT */ +#define ADDDI(x, y) ((x) + (y)) +#define SUBDI(x, y) ((x) - (y)) +#define MULDI(x, y) ((x) * (y)) +#define DIVDI(x, y) ((DI) (x) / (DI) (y)) +#define UDIVDI(x, y) ((UDI) (x) / (UDI) (y)) +#define MODDI(x, y) ((DI) (x) % (DI) (y)) +#define UMODDI(x, y) ((UDI) (x) % (UDI) (y)) +#define SRADI(x, y) ((DI) (x) >> (y)) +#define SRLDI(x, y) ((UDI) (x) >> (y)) +#define SLLDI(x, y) ((UDI) (x) << (y)) +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +#define ANDDI(x, y) ((x) & (y)) +#define ORDI(x, y) ((x) | (y)) +#define XORDI(x, y) ((x) ^ (y)) +#define NEGDI(x) (- (x)) +#define NOTDI(x) (! (DI) (x)) +#define INVDI(x) (~ (x)) +#define ABSDI(x) ((x) < 0 ? -(x) : (x)) +#define EQDI(x, y) ((DI) (x) == (DI) (y)) +#define NEDI(x, y) ((DI) (x) != (DI) (y)) +#define LTDI(x, y) ((DI) (x) < (DI) (y)) +#define LEDI(x, y) ((DI) (x) <= (DI) (y)) +#define GTDI(x, y) ((DI) (x) > (DI) (y)) +#define GEDI(x, y) ((DI) (x) >= (DI) (y)) +#define LTUDI(x, y) ((UDI) (x) < (UDI) (y)) +#define LEUDI(x, y) ((UDI) (x) <= (UDI) (y)) +#define GTUDI(x, y) ((UDI) (x) > (UDI) (y)) +#define GEUDI(x, y) ((UDI) (x) >= (UDI) (y)) +#endif /* DI_FN_SUPPORT */ + +#define EXTBIQI(x) ((QI) (BI) (x)) +#define EXTBIHI(x) ((HI) (BI) (x)) +#define EXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTBIDI (BI); +#else +#define EXTBIDI(x) ((DI) (BI) (x)) +#endif +#define EXTQIHI(x) ((HI) (QI) (x)) +#define EXTQISI(x) ((SI) (QI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTQIDI (QI); +#else +#define EXTQIDI(x) ((DI) (QI) (x)) +#endif +#define EXTHIHI(x) ((HI) (HI) (x)) +#define EXTHISI(x) ((SI) (HI) (x)) +#define EXTSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTHIDI (HI); +#else +#define EXTHIDI(x) ((DI) (HI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI EXTSIDI (SI); +#else +#define EXTSIDI(x) ((DI) (SI) (x)) +#endif + +#define ZEXTBIQI(x) ((QI) (BI) (x)) +#define ZEXTBIHI(x) ((HI) (BI) (x)) +#define ZEXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTBIDI (BI); +#else +#define ZEXTBIDI(x) ((DI) (BI) (x)) +#endif +#define ZEXTQIHI(x) ((HI) (UQI) (x)) +#define ZEXTQISI(x) ((SI) (UQI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTQIDI (QI); +#else +#define ZEXTQIDI(x) ((DI) (UQI) (x)) +#endif +#define ZEXTHISI(x) ((SI) (UHI) (x)) +#define ZEXTHIHI(x) ((HI) (UHI) (x)) +#define ZEXTSISI(x) ((SI) (USI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTHIDI (HI); +#else +#define ZEXTHIDI(x) ((DI) (UHI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI ZEXTSIDI (SI); +#else +#define ZEXTSIDI(x) ((DI) (USI) (x)) +#endif + +#define TRUNCQIBI(x) ((BI) (QI) (x)) +#define TRUNCHIBI(x) ((BI) (HI) (x)) +#define TRUNCHIQI(x) ((QI) (HI) (x)) +#define TRUNCSIBI(x) ((BI) (SI) (x)) +#define TRUNCSIQI(x) ((QI) (SI) (x)) +#define TRUNCSIHI(x) ((HI) (SI) (x)) +#define TRUNCSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern BI TRUNCDIBI (DI); +#else +#define TRUNCDIBI(x) ((BI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern QI TRUNCDIQI (DI); +#else +#define TRUNCDIQI(x) ((QI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern HI TRUNCDIHI (DI); +#else +#define TRUNCDIHI(x) ((HI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern SI TRUNCDISI (DI); +#else +#define TRUNCDISI(x) ((SI) (DI) (x)) +#endif + +/* Composing/decomposing the various types. + Word ordering is endian-independent. Words are specified most to least + significant and word number 0 is the most significant word. + ??? May also wish an endian-dependent version. Later. */ + +QI SUBWORDSIQI (SI, int); +HI SUBWORDSIHI (SI, int); +QI SUBWORDDIQI (DI, int); +HI SUBWORDDIHI (DI, int); +SI SUBWORDDISI (DI, int); + +#ifdef SEMOPS_DEFINE_INLINE + +SEMOPS_INLINE QI +SUBWORDSIQI (SI in, int byte) +{ + assert (byte >= 0 && byte <= 3); + return (UQI) (in >> (8 * (3 - byte))) & 0xFF; +} + +SEMOPS_INLINE HI +SUBWORDSIHI (SI in, int word) +{ + if (word == 0) + return (USI) in >> 16; + else + return in; +} + +SEMOPS_INLINE QI +SUBWORDDIQI (DI in, int byte) +{ + assert (byte >= 0 && byte <= 7); + return (UQI) (in >> (8 * (7 - byte))) & 0xFF; +} + +SEMOPS_INLINE HI +SUBWORDDIHI (DI in, int word) +{ + assert (word >= 0 && word <= 3); + return (UHI) (in >> (16 * (3 - word))) & 0xFFFF; +} + +SEMOPS_INLINE SI +SUBWORDDISI (DI in, int word) +{ + if (word == 0) + return (UDI) in >> 32; + else + return in; +} + +#endif /* SUBWORD,JOIN */ + +#endif /* CGEN_BASIC_OPS_H */ diff --git a/external/gpl3/gdb/dist/include/cgen/bitset.h b/external/gpl3/gdb/dist/include/cgen/bitset.h new file mode 100644 index 000000000000..7a6a99304566 --- /dev/null +++ b/external/gpl3/gdb/dist/include/cgen/bitset.h @@ -0,0 +1,56 @@ +/* Header file the type CGEN_BITSET. + Copyright 2002, 2005, 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this library; see the file COPYING3. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef CGEN_BITSET_H +#define CGEN_BITSET_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* A bitmask represented as a string. + Each member of the set is represented as a bit + in the string. Bytes are indexed from left to right in the string and + bits from most significant to least within each byte. + + For example, the bit representing member number 6 is (set->bits[0] & 0x02). +*/ +typedef struct cgen_bitset +{ + unsigned length; + char *bits; +} CGEN_BITSET; + +extern CGEN_BITSET *cgen_bitset_create PARAMS ((unsigned)); +extern void cgen_bitset_init PARAMS ((CGEN_BITSET *, unsigned)); +extern void cgen_bitset_clear PARAMS ((CGEN_BITSET *)); +extern void cgen_bitset_add PARAMS ((CGEN_BITSET *, unsigned)); +extern void cgen_bitset_set PARAMS ((CGEN_BITSET *, unsigned)); +extern int cgen_bitset_compare PARAMS ((CGEN_BITSET *, CGEN_BITSET *)); +extern void cgen_bitset_union PARAMS ((CGEN_BITSET *, CGEN_BITSET *, CGEN_BITSET *)); +extern int cgen_bitset_intersect_p PARAMS ((CGEN_BITSET *, CGEN_BITSET *)); +extern int cgen_bitset_contains PARAMS ((CGEN_BITSET *, unsigned)); +extern CGEN_BITSET *cgen_bitset_copy PARAMS ((CGEN_BITSET *)); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/coff/ChangeLog b/external/gpl3/gdb/dist/include/coff/ChangeLog new file mode 100644 index 000000000000..11aec52c2092 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/ChangeLog @@ -0,0 +1,317 @@ +2011-03-31 Tristan Gingold + + * internal.h (C_NULL_VALUE): Define. + +2010-06-29 Alan Modra + + * maxq.h: Delete file. + +2010-04-15 Nick Clifton + + * alpha.h: Update copyright notice to use GPLv3. + * apollo.h: Likewise. + * arm.h: Likewise. + * aux-coff.h: Likewise. + * ecoff.h: Likewise. + * external.h: Likewise. + * go32exe.h: Likewise. + * h8300.h: Likewise. + * h8500.h: Likewise. + * i386.h: Likewise. + * i860.h: Likewise. + * i960.h: Likewise. + * ia64.h: Likewise. + * internal.h: Likewise. + * m68k.h: Likewise. + * m88k.h: Likewise. + * maxq.h: Likewise. + * mcore.h: Likewise. + * mips.h: Likewise. + * mipspe.h: Likewise. + * or32.h: Likewise. + * pe.h: Likewise. + * powerpc.h: Likewise. + * rs6000.h: Likewise. + * rs6k64.h: Likewise. + * sh.h: Likewise. + * sparc.h: Likewise. + * ti.h: Likewise. + * tic30.h: Likewise. + * tic4x.h: Likewise. + * tic54x.h: Likewise. + * tic80.h: Likewise. + * w65.h: Likewise. + * we32k.h: Likewise. + * x86_64.h: Likewise. + * xcoff.h: Likewise. + * z80.h: Likewise. + * z8k.h: Likewise. + +2009-12-02 Jerker Bäck + + PR binutils/11017 + * i386lh (COFF_PAGE_SIZE): Define. + * x86_64.h (COFF_PAGE_SIZE): Define. + +2009-10-17 Arnold Metselaar + + * z80.h: Store alignment requirement in section header, to allow + ld to preserve alignment. Some code was copied from ti.h. + +2009-09-05 Martin Thuresson + + * ti.h (GET_LNSZ_SIZE, PUT_LNSZ_SIZE): Updated name of class + variable to in_class to match changes in function that use this + macro. + +2009-08-10 Jan Kratochvil + + Fix references past allocated memory for i386-*-go32. + * ti.h (COFF_ADJUST_FILEHDR_IN_POST, COFF_ADJUST_FILEHDR_OUT_POST): + Reference F_TARGET_ID only when !COFF0_P. + +2009-08-10 Jan Kratochvil + + Stop using bfd_usrdata in libbfd. + * go32exe.h (struct external_filehdr_go32_exe , FILHSZ): Replace + STUBSIZE by GO32_STUBSIZE. + (STUBSIZE): Move the definition ... + * internal.h (GO32_STUBSIZE): ... here and rename it. + (struct internal_filehdr , F_GO32STUB): New. + +2009-06-03 Ulrich Weigand + + * symconst.h (btLong64, btULong64, btLongLong64, btULongLong64, + btAdr64, btInt64, btUInt64): New defines. + +2009-04-21 Kai Tietz + + * pe.h (pex64_runtime_function): New structure. + (external_pex64_runtime_function): Likewise. + (pex64_unwind_code): Likewise. + (external_pex64_unwind_code): Likewise. + (pex64_unwind_info): Likewise. + (external_pex64_unwind_info): Likewise. + (external_pex64_scope): Likewise. + (pex64_scope): Likewise. + (pex64_scope_entry): Likewise. + (external_pex64_scope_entry): Likewise. + (PEX64_IS_RUNTIME_FUNCTION_CHAINED): New macro. + (PEX64_GET_UNWINDDATA_UNIFIED_RVA): Likewise. + (PEX64_UNWCODE_CODE): Likewise. + (PEX64_UNWCODE_INFO): Likewise. + (UWOP_...): Add defines for unwind code. + (UNW_FLAG_...): Add defined for unwind info flags. + (PEX64_SCOPE_ENTRY_SIZE): New macro. + (PEX64_UWI_VERSION): Likewise. + (PEX64_UWI_FLAGS): Likewise. + (PEX64_UWI_FRAMEREG): Likewise. + (PEX64_UWI_FRAMEOFF): Likewise. + (PEX64_UWI_SIZEOF_UWCODE_ARRAY): Likewise. + (PEX64_OFFSET_TO_UNWIND_CODE): Likewise. + (PEX64_OFFSET_TO_HANDLER_RVA): Likewise. + (PEX64_OFFSET_TO_SCOPE_COUNT): Likewise. + (PEX64_SCOPE_ENTRY): Likewise. + +2009-04-17 H.J. Lu + + * pe.h (IMAGE_SUBSYSTEM_EFI_ROM): Renamed to ... + (IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER): This. + +2009-04-01 Richard Sandiford + + * xcoff.h (xcoff_link_hash_table): Move to bfd/xcofflink.c. + +2009-03-14 Richard Sandiford + + * xcoff.h (XCOFF_EXPALL, XCOFF_EXPFULL): New flags. + (xcoff_loader_info): Add auto_export_flags. + +2009-03-14 Richard Sandiford + + * internal.h (C_AIX_WEAKEXT): New macro. + (C_WEAKEXT): Use the GNU definition in the generic part of the file, + and conditionally reset it to C_AIX_WEAKEXT in the XCOFF part of + the file. + (CSECT_SYM_P): New macro. + * xcoff.h (L_WEAK): Define. + (EXTERN_SYM_P): New macro. + +2009-03-14 Richard Sandiford + + * xcoff.h (XCOFF_ALLOCATED): New flag. + +2009-03-14 Richard Sandiford + + * xcoff.h (XCOFF_CALLED, XCOFF_IMPORT): Update comments. + (XCOFF_WAS_UNDEFINED): New flag. + (xcoff_link_hash_table): Add an "rtld" field. + +2009-03-14 Dave Korn + + * internal.h (struct internal_extra_pe_aouthdr): Correct type + of DllCharacteristics flags field to unsigned. + * pe.h (IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE, + IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE, + IMAGE_DLL_CHARACTERISTICS_NX_COMPAT, + IMAGE_DLLCHARACTERISTICS_NO_ISOLATION, + IMAGE_DLLCHARACTERISTICS_NO_SEH, + IMAGE_DLLCHARACTERISTICS_NO_BIND, + IMAGE_DLLCHARACTERISTICS_WDM_DRIVER, + IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE): New macros to + define flag bit values for DllCharacteristics field of PEAOUTHDR, + PEPAOUTHDR. + +2008-12-23 Johan Olmutz Nielsen + + * ti.h (COFF_ADJUST_SCNHDR_OUT_PRE): Define. + +2008-06-17 Nick Clifton + + * ti.h (GET_SCNHDR_NLNNO): Provide an alternative version of this + macro which does not trigger an array bounds warning in gcc. + (PUT_SCNHDR_NLNNO): Likewise. + (GET_SCNHDR_FLAGS): Likewise. + (PUT_SCNHDR_FLAGS): Likewise. + (GET_SCNHDR_PAGE): Likewise. + (PUT_SCNHDR_PAGE): Likewise. + +2007-11-05 Danny Smith + + * pe.h (COFF_ENCODE_ALIGNMENT) Define. + +2007-08-02 H.J. Lu + + * pe.h (IMAGE_SCN_ALIGN_POWER_BIT_POS): New. + (IMAGE_SCN_ALIGN_POWER_BIT_MASK): Likewise. + (IMAGE_SCN_ALIGN_POWER_NUM): Likewise. + (IMAGE_SCN_ALIGN_POWER_CONST): Likewise. + (IMAGE_SCN_ALIGN_128BYTES): Likewise. + (IMAGE_SCN_ALIGN_256BYTES): Likewise. + (IMAGE_SCN_ALIGN_512BYTES): Likewise. + (IMAGE_SCN_ALIGN_1024BYTES): Likewise. + (IMAGE_SCN_ALIGN_2048BYTES): Likewise. + (IMAGE_SCN_ALIGN_4096BYTES): Likewise. + (IMAGE_SCN_ALIGN_8192BYTES): Likewise. + (IMAGE_SCN_ALIGN_1BYTES): Redefined with + IMAGE_SCN_ALIGN_POWER_CONST. + (IMAGE_SCN_ALIGN_2BYTES): Likewise. + (IMAGE_SCN_ALIGN_4BYTES): Likewise. + (IMAGE_SCN_ALIGN_8BYTES): Likewise. + (IMAGE_SCN_ALIGN_16BYTES): Likewise. + (IMAGE_SCN_ALIGN_32BYTES): Likewise. + (IMAGE_SCN_ALIGN_64BYTES): Likewise. + +2007-07-12 Kai Tietz + + * internal.h (struct internal_syment): Use bfd_hostptr_t for + _n_zeroes and _n_offset fields. + +2007-04-27 Alan Modra + + * rs6000.h: Write Mimi's name in ASCII. + +2007-03-19 H.J. Lu + + * internal.h (internal_extra_pe_aouthdr): Add Magic, + MajorLinkerVersion, MinorLinkerVersion, SizeOfCode, + SizeOfInitializedData, SizeOfUninitializedData, + AddressOfEntryPoint, BaseOfCode and BaseOfData. + +2006-12-05 Michael Tautschnig + Nick Clifton + + * external.h (struct external_aouthdr): Add ATTRIBUTE_PACKED. + (struct external_syment): Likewise. + (union external_auxent): Likewise. + +2006-11-14 Phil Lello + + * pe.h: Added defines for IMAGE_SUBSYSTEM_EFI_ROM and + IMAGE_SUBSYSTEM_XBOX. + * internal.h: Added defines for PE directory entry types. + NB: in internal.h because IMAGE_NUMBEROF_DIRECTORY_ENTRYIES is in + pe.h + +2006-09-20 Kai Tietz + + * external.h: Add proper external_aouthdr64 structure (without + data_start member). + (AOUTHDRSZ64): Set according structure size. + (AOUTHDR64): As typedef of external_aouthdr64 structure. + * internal.h: Add relocation identifiers for coff. + * pe.h: Add define IMAGE_FILE_MACHINE_AMD64 the coff signature. + (PEPAOUTHDR): Adjust structure to have proper size (using AOUTHDR64). + (PEPAOUTSZ): Calculated size of 240. + * x86_64.h: Coff information for x86_64 (AMD64). + +2006-02-05 Arnold Metselaar + + * internal.h: Add relocation number R_IMM24 for Z80. + +2005-10-25 Arnold Metselaar + + * internal.h: Add relocation number for Z80 + * z80.h: New file. + +2005-08-18 Alan Modra + + * a29k.h: Delete. + +2005-07-14 Daniel Marques + + * alpha.h (ALPHA_ECOFF_COMPRESSEDMAG): Define. + * ecoff.h (ALPHA_MAGIC_COMPRESSED): Define. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + a29k.h, alpha.h, apollo.h, arm.h, aux-coff.h, ecoff.h, external.h, + go32exe.h, h8300.h, h8500.h, i386.h, i860.h, i960.h, ia64.h, + internal.h, m68k.h, m88k.h, maxq.h, mcore.h, mips.h, mipspe.h, + or32.h, pe.h, powerpc.h, rs6k64.h, sh.h, sparc.h, ti.h, tic30.h, + tic4x.h, tic54x.h, tic80.h, w65.h, we32k.h, xcoff.h, z8k.h + +2005-02-21 Alan Modra + + * xcoff.h (struct xcoff_loader_info): Warning fix. + +2005-01-10 Inderpreet Singh + + * maxq.h (F_MAXQ10, F_MAXQ20): Define. + +2004-11-08 Inderpreet Singh + Vineet Sharma + + * maxq.h: New file: Defintions for the maxq port. + +2004-11-08 Aaron W. LaFramboise + + * pe.h (IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY): Define. + (IMAGE_WEAK_EXTERN_SEARCH_LIBRARY): Same. + (IMAGE_WEAK_EXTERN_SEARCH_ALIAS): Same. + +2004-08-13 Mark Kettenis + + * symconst.h (langMax): Fix typo in comment. + +2004-04-23 Chris Demetriou + + * mips.h (MIPS_R_RELHI, MIPS_R_RELLO, MIPS_R_SWITCH): Remove + (MIPS_R_PCREL16): Update comment. + * ecoff.h (struct ecoff_value_adjust): Remove structure. + (struct ecoff_debug_info): Remove 'adjust' member. + +2004-04-20 DJ Delorie + + * internal.h (R_SECREL32): Add. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/coff/ChangeLog-9103 b/external/gpl3/gdb/dist/include/coff/ChangeLog-9103 new file mode 100644 index 000000000000..98a778456fd8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/ChangeLog-9103 @@ -0,0 +1,1177 @@ +2005-04-13 H.J. Lu + + Moved from ../ChangeLog + + 2003-04-04 Svein E. Seldal + * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x + and s/c3x/tic3x/ + + 2003-01-20 Svein E. Seldal + * tic4x.h (TICOFF_TARGET_MACHINE_GET): Fixed define bug + * ti.h (TICOFF_TARGET_MACHINE_GET): Added macros + + 2002-08-28 Michael Hayes + * internal.h: Add new relocation types. + * ti.h: Add file-header flags for tic4x code. + * tic4x.h: New file + +2003-12-02 Graham Reed + + * internal.h (C_WEAKEXT): Add alternative value for AIX 5.2 + based targets. + +2003-08-23 Jason Eckhardt + + * coff/i860.h (COFF860_R_PAIR, COFF860_R_LOW0, COFF860_R_LOW1, + COFF860_R_LOW2, COFF860_R_LOW3, COFF860_R_LOW4, COFF860_R_SPLIT0, + COFF860_R_SPLIT1, COFF860_R_SPLIT2, COFF860_R_HIGHADJ, + COFF860_R_BRADDR): Define new relocation constants and document. + Minor formatting adjustments. + +2003-08-07 Alan Modra + + * ti.h (GET_SCNHDR_NRELOC): Rename PTR param to LOC. + (PUT_SCNHDR_NRELOC, GET_SCNHDR_NLNNO, PUT_SCNHDR_NLNNO): Likewise. + (GET_SCNHDR_FLAGS, PUT_SCNHDR_FLAGS): Likewise. + (GET_SCNHDR_PAGE, PUT_SCNHDR_PAGE): Likewise. + +2003-07-17 Jeff Muizelaar + + * pe.h: (IMAGE_FILE_NET_RUN_FROM_SWAP): Define. + (IMAGE_FILE_MACHINE_WCEMIPSV2): Define. + (IMAGE_FILE_MACHINE_SH3DSP): Define. + (IMAGE_FILE_MACHINE_SH3E): Define. + (IMAGE_FILE_MACHINE_SH5): Define. + (IMAGE_FILE_MACHINE_AM33): Define. + (IMAGE_FILE_MACHINE_POWERPCFP): Define. + (IMAGE_FILE_MACHINE_AXP64): Define. + (IMAGE_FILE_MACHINE_TRICORE): Define. + (IMAGE_FILE_MACHINE_CEF): Define. + (IMAGE_FILE_MACHINE_EBC): Define. + (IMAGE_FILE_MACHINE_AMD64): Define. + (IMAGE_FILE_MACHINE_M32R): Define. + (IMAGE_FILE_MACHINE_CEE): Define. + +2003-07-14 Christian Groessler + + * i860.h (AOUTSZ): Define for i860 coff. + +2003-06-29 Andreas Jaeger + + * xcoff.h (struct __rtinit ): Convert to ISO C90 prototypes. + + * ecoff.h: Convert to ISO C90 prototypes. Replace PTR by void *. + +2003-04-24 Dhananjay Deshpande + + * coff/h8300.h (H8300HNMAGIC, H8300SNMAGIC): New. + (H8300HNBADMAG, H8300SNBADMAG): New. + +2003-04-15 Rohit Kumar Srivastava + + * sh.h: Replace occurrances of 'Hitachi' with 'Renesas'. + * h8300.h: Likewise. + * h8500.h: Likewise. + +2003-03-25 Stan Cox + Nick Clifton + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm.h (ARM_NOTE_SECTION): Define. + +2002-11-30 Alan Modra + + * ecoff.h: Replace boolean with bfd_boolean. + * xcoff.h: Likewise. + +2002-03-18 Tom Rix + + * rs6k64.h: Add U64_TOCMAGIC, AIX 5 64 bit magic number. + +2002-02-01 Tom Rix + + * xcoff.h: Conditionally support for pre AIX 4.3. + +2002-01-31 Ivan Guzvinec + + * or32.h: New file. + +2001-12-24 Tom Rix + + * xcoff.h (xcoff_big_format_p): Make the default archive + format. + (XCOFFARMAG_ELEMENT_SIZE, XCOFFARMAGBIG_ELEMENT_SIZE): Define for + archive header ascii elements. + +2001-12-17 Tom Rix + + * xcoff.h : Add .except and .typchk section string and styp flags. + Fix xcoff_big_format_p macro. + +2001-12-16 Tom Rix + + * xcoff.h : Clean up formatting. + +2002-01-15 Richard Earnshaw + + * arm.h (F_VFP_FLOAT): Define. + +2001-11-11 Timothy Wall + + * ti.h: Move arch-specific stuff from here... + (COFF_ADJUST_SYM_IN/OUT): Optionally put page flag into symbol + value. + * tic54x.h: ...to here. + +2001-10-26 Christian Groessler + + * external.h (GET_LINENO_LNNO): Fix usage of H_GET_32/16. + (PUT_LINENO_LNNO): Likewise with H_PUT_32/16. + +2001-09-21 Nick Clifton + + * ti.h (GET_SCNHDR_PAGE): Fix compile time warning. + +2001-09-18 Alan Modra + + * external.h (GET_LINENO_LNNO): Use H_GET_32/16. + (PUT_LINENO_LNNO): Use H_PUT_32/16. + * m88k.h (GET_LNSZ_SIZE, GET_LNSZ_LNNO, GET_SCN_NRELOC, + GET_SCN_NLINNO): Use H_GET_32. + (PUT_LNSZ_LNNO, PUT_LNSZ_SIZE, PUT_SCN_NRELOC, PUT_SCN_NLINNO): + Use H_PUT_32. + * ti.h: Formatting fixes. Make use of H_GET_* and H_PUT_* throughout. + * xcoff.h: White space changes. + +2001-09-05 Tom Rix + + * xcoff.h : Add XCOFF_SYSCALL32 and XCOFF_SYSCALL64 hash table flags. + +2001-08-27 Andreas Jaeger + + * xcoff.h (struct __rtinit): Make proper prototype for rtl. + +Fri Aug 24 01:18:51 2001 J"orn Rennecke + + * internal.h (R_JMP2, R_JMPL2, R_MOVL2): Comment spelling fix. + +2001-04-05 Tom Rix + + * rs6000.h : move xcoff32 external structures from xcofflink. + * rs6k64.h : move xcoff64 external structures from xcofflink. + * internal.h : promote 32 bit structure elements to 64 bit + for xcoff64 support + * xcoff.h : New file. + +2001-03-23 Nick Clifton + + * a29k.h: Fix compile time warning. + * external.h: Fix compile time warning. + * m88k.h: Fix compile time warning. + +2001-03-13 Nick Clifton + + * external.h: New file. Common structure definitions found in + other COFF header files. + + * a29k.h: Use external.h. + * apollo.h: Use external.h. + * arm.h: Use external.h. + * h8300.h: Use external.h. + * h8500.h: Use external.h. + * i386.h: Use external.h. + * i860.h: Use external.h. + * ia64.h: Use external.h. + * m68k.h: Use external.h. + * m88k.h: Use external.h. + * mcore.h: Use external.h. + * mips.h: Use external.h. + * mipspe.h: Use external.h. + * powerpc.h: Use external.h. + * rs6000.h: Use external.h. + * rs6k64.h: Use external.h. + * sh.h: Use external.h. + * sparc.h: Use external.h. + * tic30.h: Use external.h. + * tic80.h: Use external.h. + * w65.h: Use external.h. + * we32k.h: Use external.h. + * z8k.h: Use external.h. + +2001-02-09 David Mosberger + + * pe.h (PEPAOUTSZ): Rename from PEP64AOUTSZ. + Rename from PEPAOUTHDR. + +2001-01-23 H.J. Lu + + * pe.h (struct external_PEI_DOS_hdr): New. + (struct external_PEI_IMAGE_hdr): New. + +2000-12-11 Alan Modra + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warning to #error. + +2000-12-08 Alan Modra + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warn to #warning. + +2000-06-30 DJ Delorie + + * pe.h: Clarify a comment. + +2000-05-05 Clinton Popetz + + * rs6k64.h (U802TOC64MAGIC): Change to U803XTOCMAGIC. + +2000-04-24 Clinton Popetz + + * rs6k64.h: New file. + +2000-04-17 Timothy Wall + + * ti.h: Load page cleanup. + * intental.h: Add load page field. + +Mon Apr 17 16:44:01 2000 David Mosberger + + * pe.h (PEP64AOUTHDR): New header for PE+. + (PEP64AOUTSZ): New macro. + (IMAGE_SUBSYSTEM_UNKNOWN): New macro. + (IMAGE_SUBSYSTEM_NATIVE): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_GUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CUI): Ditto. + (IMAGE_SUBSYSTEM_POSIX_CUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CE_GUI): Ditto. + (IMAGE_SUBSYSTEM_EFI_APPLICATION): Ditto. + (IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER): Ditto. + (IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER): Ditto. + * internal.h (PE_DEF_FILE_ALIGNMENT): Define only if not defined + already. + * ia64.h: New file. + +2000-04-13 Alan Modra + + * ti.h (ADDR_MASK): Don't use ul suffix on constants. + (PG_MASK): Ditto. + +2000-04-11 Timothy Wall + + * ti.h: Remove load page references until load pages are + reimplemented. + * tic54x.h: Ditto. + +2000-04-07 Timothy Wall + + * internal.h: Fix some comments related to TI COFF (instead of tic80). + * ti.h: New. + * tic54x.h: New. + +Wed Apr 5 22:08:41 2000 J"orn Rennecke + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. + +2000-03-15 Kazu Hirata + + * internal.h: Fix a typo in the comment for R_MOVL2. + +2000-02-28 Nick Clifton + + * mipspe.h (MIPS_PE_MAGIC): Define. + * sh.h (SH_PE_MAGIC): Define. + +2000-02-22 Nick Clifton DJ Delorie + + * sh.h: Add Windows CE definitions. + * arm.h: Add Windows CE definitions. + * mipspe.h: New file: Windows CE definitions for MIPS. + * pe.h: Add constants for ILF support. + +2000-01-05 Nick Clifton + + * pe.h: Fix formatting of comments. + (IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define. + (IMAGE_FILE_LARGE_ADDRESS_AWARE): Define. + (IMAGE_FILE_16BIT_MACHINE): Define. + (IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define. + (IMAGE_FILE_UP_SYSTEM_ONLY): Define. + (IMAGE_FILE_MACHINE_UNKNOWN): Define. + (IMAGE_FILE_MACHINE_ALPHA): Define. + (IMAGE_FILE_MACHINE_ALPHA64): Define. + (IMAGE_FILE_MACHINE_I386): Define. + (IMAGE_FILE_MACHINE_IA64): Define. + (IMAGE_FILE_MACHINE_M68K): Define. + (IMAGE_FILE_MACHINE_MIPS16): Define. + (IMAGE_FILE_MACHINE_MIPSFPU): Define. + (IMAGE_FILE_MACHINE_MIPSFPU16): Define. + (IMAGE_FILE_MACHINE_POWERPC): Define. + (IMAGE_FILE_MACHINE_R3000): Define. + (IMAGE_FILE_MACHINE_R4000): Define. + (IMAGE_FILE_MACHINE_R10000): Define. + (IMAGE_FILE_MACHINE_SH3): Define. + (IMAGE_FILE_MACHINE_SH4): Define. + (IMAGE_FILE_MACHINE_THUMB): Define. + +1999-09-20 Alan Modra + + * internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and + R_RELWORD, and rewrite some R_* as decimal. + +1999-09-06 Donn Terry + + * internal.h (DTYPE): Define. + * pe.h (struct external_PEI_filehdr): Rename from + external_PE_filehdr. Define even if COFF_IMAGE_WITH_PE is not + defined. + +1999-07-17 Nick Clifton + + * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT. + +1999-06-21 Philip Blundell + + * arm.h (F_SOFTFLOAT): Define. + +1999-07-05 Nick Clifton + + * arm.h (F_ARM_5): Define. + +Wed Jun 2 18:08:18 1999 Richard Henderson + + * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. + +Mon May 17 13:35:35 1999 Stan Cox + + * arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, + F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish + F_ARM_2a, F_ARM_3M, F_ARM_4T. + +1999-05-15 Nick Clifton + + * mcore.h (IMAGE_REL_MCORE_RVA): Define. + +1999-04-21 Nick Clifton + + * mcore.h (GET_LINENO_LNNO): New macro. + (PUT_LINENO_LNNO): New macro. + +1999-04-08 Nick Clifton + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +Sun Dec 6 21:36:37 1998 Mark Elbrecht + + * internal.h (C_WEAKEXT): Define. + +Wed Jan 27 13:35:35 1999 Stan Cox + + * arm.h (F_PIC_INT, F_ARM_2, F_ARM_3, F_ARM_4, F_APCS26): + Changed values to avoid clashing with IMAGE_FILE_* coff header + flag values. + +Wed Apr 1 16:06:15 1998 Nick Clifton + + * internal.h: Document numbers associated with Thumb symbol + types. + +Fri Mar 27 17:16:57 1998 Ian Lance Taylor + + * internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long. + +Mon Feb 2 17:10:38 1998 Steve Haworth + + * tic30.h: New file. + +Fri Dec 12 11:49:07 1997 Fred Fish + + * tic80.h (R_MPPCR15W): New relocation type, for 15 bit PC relative + offsets. + +Tue Dec 2 10:21:40 1997 Nick Clifton + + * arm.h (COFFARM): New define. + +Mon Dec 1 20:24:18 1997 J"orn Rennecke + + * sh.h (R_SH_SWITCH8): New. + +Sat Nov 22 15:10:14 1997 Nick Clifton + + * internal.h (C_THUMBEXTFUNC, C_THUMBSTATFUNC): Constants to + define static and external functions. + + * arm.h: Add bits to support PIC and APCS-FLOAT type binaries, + when implemented. + +Fri Oct 3 14:25:17 1997 Fred Fish + + * tic80.h (R_PPL16B): Make constant uppercase for consistency. + +Tue Jul 22 18:18:58 1997 Robert Hoehne + + * go32exe.h: New file. + +Tue Jul 8 12:23:55 1997 Fred Fish + + * tic80.h (TIC80_TARGET_ID): Add define. + * internal.h (struct internal_filehdr): Add f_target_id field. + +Tue Jun 3 16:44:18 1997 Nick Clifton + + * internal.h: Add storage classes for Thumb symbols + +Mon May 26 14:07:55 1997 Ian Lance Taylor + + * tic80.h (R_PPL16B): Correct value. + +Tue May 13 10:21:14 1997 Nick Clifton + + * arm.h (constants): Added new flag bits F_APCS_26 and + F_APCS_SET for the f_flags field of the filehdr structure. Added new + flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store + information in the flags field of the internal_f structure used by BFD + routines. + +Sat May 3 08:24:59 1997 Fred Fish + + * internal.h (C_UEXT, C_STATLAB, C_EXTLAB, C_SYSTEM): + New storage classes for TIc80. + +Fri Apr 18 11:52:55 1997 Niklas Hallqvist + + * alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too. + (ALPHA_R_LITERALSLEAZY): Define. + * ecoff.h (ALPHA_MAGIC_BSD): Define. + +Wed Jan 29 11:31:51 1997 Ian Lance Taylor + + * i960.h (R_IPR13, R_ALIGN): Define. + +Mon Jan 27 13:34:30 1997 Ian Lance Taylor + + * internal.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): Move definitions + from here... + * i960.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): ...to here. + +Wed Jan 22 20:10:47 1997 Fred Fish + + * tic80.h (TIC80MAGIC): Renamed to TIC80_AOUTHDR_MAGIC. + +Fri Dec 27 22:05:45 1996 Fred Fish + + * tic80.h: New file for TIc80 support. + +Thu Dec 19 16:18:11 1996 Ian Lance Taylor + + * arm.h (_LIT): Define. + +Fri Jun 28 12:54:38 1996 Ian Lance Taylor + + * pe.h (FILHSZ): Define. + +Wed Jun 26 16:24:26 1996 Ian Lance Taylor + + * All files: Define FILHSZ, AOUTSZ, AOUTHDRSZ, SCNHSZ, SYMESZ, + AUXESZ, LINESZ, RELSZ as numeric constants rather than uses of + sizeof. Define AOUTHDRSZ in all files. + * pe.h (AOUTSZ): Define by adding to AOUTHDRSZ. + +Fri Jun 21 11:17:46 1996 Richard Henderson + + * alpha.h: Add declarations for relocation types added for Alpha + OSF/1 3.0. + +Tue Jun 18 16:04:29 1996 Jeffrey A. Law + + * h8300.h (H8300SMAGIC): Define. + (H8300SBADMAG): Define. + +Mon Jun 10 11:53:28 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_BCC_INV, R_JMP_DEL): New relocations for + relaxing in the H8/300 series. + +Thu May 16 15:49:22 1996 Ian Lance Taylor + + * sh.h (R_SH_CODE, R_SH_DATA, R_SH_LABEL): Define. + +Tue May 7 00:36:39 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_JMPL2): Renamed from R_JMPL_B8 to be + consistent with other similar relocs. + + * internal.h (H8/300 specific relocs): Add comments better + explaining what each reloc is used for. + (R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2. + (R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2. + (R_MOVL1, R_MOVL2): New relocs. + +Fri May 3 13:01:12 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_PCRWORD_B): Define for the h8300 relaxing + linker. + +Wed May 1 19:21:03 1996 Ian Lance Taylor + + * internal.h (SCNNMLEN): Define. + (struct internal_scnhdr): Use SCNNMLEN for s_name field. + +Fri Mar 29 13:41:25 1996 Ian Lance Taylor + + * pe.h: Define IMAGE_COMDAT codes. + +Wed Mar 27 17:29:42 1996 Ian Lance Taylor + + * arm.h (union external_auxent): Add x_checksum, x_associated, and + x_comdat fields to x_scn struct. + * i386.h (union external_auxent): Likewise. + * powerpc.h (union external_auxent): Likewise. + * internal.h (union internal_auxent): Likewise. + +Thu Mar 21 16:25:57 1996 David Mosberger-Tang + + * ecoff.h (struct ecoff_find_line): Add caching fields. + +Thu Mar 14 15:22:44 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_MEM_INDIRECT): New reloc for the h8300. + +Fri Feb 9 10:44:11 1996 Ian Lance Taylor + + * aux-coff.h: Rename from aux.h, to avoid problems on hapless DOS + systems which think that aux is a com port. + +Mon Feb 5 18:35:00 1996 Ian Lance Taylor + + * i960.h (F_I960HX): Define. + +Wed Jan 31 13:11:54 1996 Richard Henderson + + * aux.h: New file. + * internal.h, m68k.h: Protect against multiple inclusion. + +Wed Nov 22 13:48:39 1995 Ian Lance Taylor + + * ecoff.h (_RCONST, STYP_RCONST, RELOC_SECTION_RCONST): Define. + (NUM_RELOC_SECTIONS): Update. + * symconst.h (scRConst): Define. + +Tue Nov 14 18:54:29 1995 Ian Lance Taylor + + * internal.h (C_NT_WEAK): Define. + +Thu Nov 9 14:08:30 1995 Ian Lance Taylor + + * rs6000.h (STYP_OVRFLO): Define. + +Tue Nov 7 14:38:45 1995 Kim Knuttila + + * powerpc.h (IMAGE_NT_OPTIONAL_HDR_MAGIC): Added define. + * pe.h: Added defines for file level flags + +Mon Nov 6 17:28:01 1995 Harry Dolan + + * i860.h: New file, based on i386.h. + +Wed Nov 1 15:25:18 1995 Manfred Hollstein KS/EF4A 60/1F/110 #40283 + + * m68k.h (PAGEMAGICEXECSWAPPED): Define. + (PAGEMAGICPEXECSWAPPED): Define. + (PAGEMAGICPEXECTSHLIB): Define. + (PAGEMAGICPEXECPAGED): Define. + (_COMMENT): DEFINE. + * m88k.h (_COMMENT): Define. + +Wed Oct 18 18:36:19 1995 Geoffrey Noer + + * sym.h: #if 0'd out runtime_pdr struct because it chokes + Visual C++ and there aren't any references to it elsewhere in gdb. + +Mon Oct 16 11:12:24 1995 Ian Lance Taylor + + * rs6000.h (SMALL_AOUTSZ): Define. + + * internal.h (XMC_TD): Define. + +Tue Oct 10 18:41:03 1995 Ian Lance Taylor + + * internal.h (struct internal_aouthdr): Add o_cputype field. + * rs6000.h (AOUTHDR): Rename o_resv1 to o_cputype. + +Mon Oct 9 14:45:46 1995 Ian Lance Taylor + + * rs6000.h (AOUTHDR): Add o_maxdata field. Add comments. + (_PAD, _LOADER): Define. + (STYP_LOADER): Define. + * internal.h (struct internal_aouthdr): Add o_maxdata field. + +Thu Oct 5 10:02:57 1995 Ian Lance Taylor + + * ecoff.h: Define section name macros and STYP macros for various + Alpha sections: .got, .hash, .dynsym, .dynstr, .rel.dyn, .conflic, + .comment, .liblist, .dynamic. + +Wed Oct 4 10:56:35 1995 Kim Knuttila + + * pe.h: Moved DOSMAGIC and NT_SIGNATURE defines here + * powerpc.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + Also removed other unused defines (various MAGIC ones) + * i386.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * arm.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * apollo.h: removed unused DEFAULT_* defines + * alpha.h: removed unused DEFAULT_* defines + * h8500.h: removed unused DEFAULT_* defines + * h8300.h: removed unused DEFAULT_* defines + * i960.h: removed unused DEFAULT_* defines + * m88k.h: removed unused DEFAULT_* defines + * we32k.h: removed unused DEFAULT_* defines + * rs6000.h: removed unused DEFAULT_* defines + * mips.h: removed unused DEFAULT_* defines + * m68k.h: removed unused DEFAULT_* defines + * z8k.h: removed unused DEFAULT_* defines + * w65.h: removed unused DEFAULT_* defines + * sparc.h: removed unused DEFAULT_* defines + * sh.h: removed unused DEFAULT_* defines + +Fri Sep 29 08:40:08 1995 Kim Knuttila + + * powerpc.h: Reformatted to GNU coding conventions. + +Wed Sep 27 06:50:50 1995 Kim Knuttila + + * pe.h: added defines for more section characteristics + * powerpc.h (new file): base coff definitions for ppc PE + +Tue Sep 12 12:08:20 1995 Ian Lance Taylor + + * internal.h (struct internal_syment): Change n_numaux field from + char to unsigned char. + +Fri Sep 1 15:39:36 1995 Kazumoto Kojima + + * mips.h (struct rpdr_ext): Define. + +Thu Aug 31 16:51:50 1995 steve chamberlain + + * internal.h (internal_aouthdr, internal_filehdr): + don't indirect the pe stuff. + +Tue Aug 29 14:16:07 1995 steve chamberlain + + * i386.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Make the same + as 'the other' compiler. + * internal.h (NT_IMAGE_BASE): Deleted. + (NT_EXE_IMAGE_BASE, NT_DLL_IMAGE_BASE): New. + (PE_DEF_SECTION_ALIGNMENT, PE_DEF_FILE_ALIGNMENT): New. + (R_IMAGEBASE): New. + +Mon Aug 21 18:12:19 1995 steve chamberlain + + * internal.h: (internal_filehdr): Moved PE stuff into + internal_extra_pe_filehdr. + (internal_aouthdr): Moved PE stuff into + interanl_extra_pe_aouthdr. + +Mon Jul 24 14:05:39 1995 Ian Lance Taylor + + * internal.h: Move R_SH_* relocs from here... + * sh.h: ...to here. + (R_SH_SWITCH16, R_SH_SWITCH32): Define. + (R_SH_USES, R_SH_COUNT, R_SH_ALIGN): Define. + +Thu Jun 29 00:04:25 1995 Steve Chamberlain + + * internal.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Increase a lot. + +Tue May 16 15:08:20 1995 Ken Raeburn + + * internal.h (NT_subsystem, NT_stack_heap): Delete + +Tue May 16 15:08:20 1995 Ken Raeburn + + * internal.h (NT_subsystem, NT_stack_heap): Now extern. + +Sat May 13 10:14:08 1995 Steve Chamberlain + + * pe.h: New file. + * i386.h (NT_SECTION_ALIGNMENT, NT_FILE_ALIGNMENT, + NT_DEF_RESERVE, NT_DEF_COMMIT): New. + * internal.h (internal_filehdr): New fields for PE. + (IMAGE_DATA_DIRECTORY): New. + (internal_aouthdr): New fields for PE. + +Tue Feb 14 17:59:37 1995 Ian Lance Taylor + + * ecoff.h (struct ecoff_fdrtab_entry): Define. + (struct ecoff_find_line): Define. + +Sat Feb 4 14:38:03 1995 David Mosberger-Tang + + * sym.h (struct pdr): field "prof" added. + + * alpha.h (PDR_BITS1_PROF_*): added, macros for PDR_BITS*_RESERVED_* + updated accordingly. + +Sun Jan 15 18:38:33 1995 Steve Chamberlain + + * w65.h: New file. + +Wed Nov 23 22:43:38 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh.h (SH_ARCH_MAGIC_BIG, SH_ARCH_MAGIC_LITTLE): New. + (SHBADMAG): Changed to suit. + +Tue Jul 26 17:46:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960.h (F_I960JX): New macro. + +Wed Jul 6 00:48:57 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha.h: Add definitions for alpha file header flags, encoding + the object type of the file. + +Mon Jun 20 13:47:01 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * ecoff.h (ecoff_swap_tir_in): Remove declaration. + (ecoff_swap_tir_out): Likewise. + (ecoff_swap_rndx_in, ecoff_swap_rndx_out): Likewise. + (struct ecoff_debug_swap): Add new fields: swap_tir_in, + swap_rndx_in, swap_tir_out, swap_rndx_out, read_debug_info. + +Sun Jun 12 03:51:52 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * symconst.h: Pick up SGI define for stIndirect. + +Fri Apr 22 13:05:28 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO): Don't define. + (struct ecoff_reginfo): Don't define. + + * sh.h (SH_ARCH_MAGIC): Rename from SHMAGIC. SHMAGIC is used by + several targets to mean a shared library. + (SHBADMAG): Corresponding change. + +Thu Apr 14 13:00:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_BIG): Changed from 0x1e to 0x3e. + (RELOC_BITS3_TYPEHI_LITTLE): Define. + (RELOC_BITS3_TYPEHI_SH_LITTLE): Define. + (MIPS_R_PCREL16): Change value from 8 to 12 to match Irix 4. + (MIPS_R_RELHI): Define. + (MIPS_R_RELLO): Define. + (MIPS_R_SWITCH): Change value from 9 to 22. + +Thu Apr 7 14:19:35 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_SWITCH): Define. + +Thu Mar 31 19:28:33 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * internal.h (internal_aouthdr): Added comments for Apollo fields. + +Thu Mar 31 16:28:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (STYP_ECOFF_LIB): Define as used on Irix 4. + +Fri Mar 25 17:16:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_info): Add adjust field. + (struct ecoff_value_adjust): Define. + +Tue Mar 22 13:22:47 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_PCREL16): Define. + +Sat Feb 26 10:26:38 1994 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h: Add casts to avoid warnings from SVR4 cc. + +Mon Feb 21 09:48:46 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * sym.h (struct runtime_pdr): Make field adr bfd_vma, not unsigned + long. + (SYMR): Make field value bfd_vma, not long. + +Fri Feb 4 23:35:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * rs6000.h (STYP_DEBUG): Define. + +Wed Feb 2 14:31:37 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (union internal_auxent): Change x_csect.x_scnlen into + a union of a long and a pointer to a symbol. XCOFF sometimes uses + this field as a symbol index. + +Mon Jan 10 23:54:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (ecoff_debug_info): Remove fields line_end, + external_dnr_end, external_pdr_end, external_sym_end, + external_opt_end, external_aux_end, ss_end, external_fdr_end. + Replace ifdbase with ifdmap. + +Wed Jan 5 17:05:36 1994 Ken Raeburn (raeburn@deneb.cygnus.com) + + * ecoff.h (STYP_EXTENDESC, STYP_COMMENT, STYP_XDATA, STYP_PDATA): + Define. + +Wed Jan 5 16:58:24 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (NUM_RELOC_SECTIONS): Define. + +Tue Dec 21 09:24:56 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * sparc.h (struct external_reloc): Rename field r_addend to + r_offset. + +Sat Dec 11 16:12:32 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h (R_DISP7, R_SH_IMM16): New reloc types. + +Tue Nov 23 14:23:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Added *_end fields for all + the symbolic information pointers. + + * sym.h: Named the EXTR structure ecoff_extr. + +Fri Nov 19 08:21:18 1993 Ken Raeburn (raeburn@rover.cygnus.com) + + * sparc.h (RELSZ): Use correct size. + +Wed Nov 17 17:18:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (struct ecoff_debug_info): Define. + +Tue Nov 2 17:56:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Define. + +Thu Oct 28 17:07:50 1993 Stan Shebs (shebs@rtl.cygnus.com) + + * i386.h (I386LYNXMAGIC): Rename to LYNXCOFFMAGIC. + * m68k.h (LYNXCOFFMAGIC): Define. + * sparc.h: New file. + +Tue Oct 19 15:34:50 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha.h (external_aouthdr): Split four byte padding field into + two byte bldrev field and two byte padding field. + + * ecoff.h (_LITA, _PDATA, _XDATA, STYP_LITA): Defined. + +Wed Oct 13 15:52:34 1993 Ken Raeburn (raeburn@cygnus.com) + + Sun Oct 10 17:27:10 1993 Troy Rollo (troy@cbme.unsw.edu.au) + + * internal.h: Added o_sri, o_inlib and o_vid for Apollos as well + as R_DIR16. + + * apollo.h: New file + +Mon Oct 11 17:16:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO, struct ecoff_reginfo): Define. + +Tue Oct 5 10:52:53 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * rs6000.h: Change non-ASCII characters in comment to octal + escapes. + +Tue Sep 28 03:27:04 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * ecoff.h (_FINI, STYP_ECOFF_FINI): Add to support .fini section. + +Fri Sep 24 11:53:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + * ecoff.h: Define MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + +Thu Sep 23 21:07:14 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + * ecoff.h: Define MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + +Thu Sep 16 20:27:21 1993 Jim Kingdon (kingdon@cirdan.cygnus.com) + + * sym.h, symconst.h: Add comment stating these files are not part + of GDB, GAS, etc. In 1991, when we asked rms whether we could + include these files in GDB (although they are copyrighted by + someone besides the FSF), he said it was OK if they were not + considered part of GDB. + +Fri Sep 10 17:40:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_PUT_ANY): Cast val argument to bfd_vma. + + * alpha.c (external_aouthdr): Need four bytes of padding between + vstamp and tsize. + +Tue Sep 7 14:20:43 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_GET_ANY, AUX_PUT_ANY): Changed to reflect further + change in bfd swapping routine names. + +Tue Sep 7 10:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * ecoff.h (AUX_GET_ANY): Change name of _do_getb32 to reflect bfd + changes. + +Fri Aug 13 14:30:32 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h (RELOC_SECTION_NONE): Define. + +Thu Aug 12 11:24:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h (struct external_reloc): Add r_symndx field. + (RELSZ): Correct. + (RELOC_BITS*): Correct. + (ALPHA_R_*): Define. + * ecoff.h (RELOC_SECTION_{XDATA,PDATA,FINI,LITA,ABS}): Define. + (r_extern): Undefine. + * internal.h (struct internal_reloc): Make r_vaddr bfd_vma rather + than long. Add r_extern field. + + * alpha.h (PDR_BITS*): Define. + * sym.h (PDR): Give correct names to new fields. + + * ecoff.h: Moved MIPS reloc definitions from here... + * mips.h: to here. + +Mon Aug 2 16:37:14 1993 Stu Grossman (grossman at cygnus.com) + + * i386.h: Add Lynx magic number. + +Tue Aug 3 11:17:53 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h: Corrected external symbolic debugging structures to + match actual usage. + * internal.h (internal_filehdr, internal_aouthdr, + internal_scnhdr): Changed type of some fields to bfd_vma so they + can hold 64 bits. + * sym.h (HDRR, FDR, PDR, EXTR): Likewise. + (PDR): Added new fields found on Alpha. + * symconst.h (magicSym2): Define; new value found on Alpha. + + * ecoff.h: New file. + * alpha.h, mips.h: Moved common information into ecoff.h. Moved + external structure definitions in from ecoff-ext.h. + * ecoff-ext.h: Removed; information now in alpha.h and mips.h. + +Sun Jul 18 21:43:59 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * i386.h: Recognize I386PTXMAGIC. + +Fri Jul 16 09:54:35 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (MIPS_AOUT_{OZ}MAGIC): Renamed from {OZ}MAGIC. + +Thu Jul 15 12:23:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k.h (union external_auxent): Move x_fcn back inside x_fcnary. + ({GET,PUT}_FCN_{LNNOPTR,ENDNDX}): Adjust accordingly. + +Sun Jul 11 18:00:18 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k.h: Define MC68KBCSMAGIC. + +Thu Jun 10 11:46:28 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (_INIT, STYP_MIPS_INIT): Define (used on Irix4). + (STYP_OTHER_LOAD): Define as STYP_MIPS_INIT. + +Wed Jun 9 15:09:09 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (OMAGIC): Define. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * h8300.h: New magic number. + * internal.h: New relocations. + +Mon Apr 26 18:04:47 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h, sh.h: Support for SH. + +Sat Apr 24 21:34:59 1993 Jim Kingdon (kingdon@cygnus.com) + + * a29k.h: Define _LIT. + +Fri Apr 23 18:41:23 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha.h: New file. + +Thu Apr 8 12:36:34 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (C_SHADOW, C_VERSION): Copied in from m88k.h. + * m88k.h, i386.h, we32k.h: Don't define all the storage classes; + they're already in internal.h. + +Wed Apr 7 11:51:24 1993 Jim Kingdon (kingdon@cygnus.com) + + * internal.h: Change n_sclass to unsigned char. + Change C_EFCN to 0xff, change RS/6000 dbx symbols + to no longer be signed. + +Fri Mar 19 14:52:56 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: Add H8/500 reloc types. + +Wed Mar 17 09:46:03 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_PUT_ANY): Don't use void values in branches of + conditional expression. + +Thu Mar 4 14:12:06 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_GET_*): Rewrote to use new macro AUX_GET_ANY. + (AUX_PUT_*): New macros corresponding to the AUX_GET macros. + (ecoff_swap_tir_out): Added prototype. + + * mips.h (N_BTMASK, N_TMASK, N_BTSHFT, N_TSHIFT): Define; these + are needed to interpret gcc debugging output. + +Tue Feb 9 07:43:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * we32k.h (BTYPE, ISPTR, ISFCN, ISARY, DECREF): Removed + more definitions duplicated in internal.h. + +Wed Feb 3 09:18:24 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_*): Correct for big endian machines. + +Mon Jan 25 11:35:51 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (internal_aouthdr): Added additional fields used only + by MIPS ECOFF. + +Thu Jan 21 10:28:38 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (AOUTHDR): Added additional fields used by ECOFF. + +Tue Jan 19 12:21:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h (N_*, T_*, DT_*): Removed still more definitions + duplicated in internal.h. + + * mips.h (RELOC_SECTION_*, ECOFF_R_*): Defined constants for ECOFF + relocs. + +Fri Jan 15 18:17:00 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for new ECOFF swapping functions. + (opt_ext): New structure. + * mips.h (ZMAGIC): Defined to be 0413. + (_LIB): Defined to be ".lib" + (external_reloc): MIPS ECOFF relocs are only 8 bytes. Added + macros to aid in swapping. + +Fri Jan 8 16:19:26 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for ECOFF swapping functions. + * internal.h (internal_scnhdr): Always provide s_align field, not + just on i960. + (internal_reloc): Always provide r_size field, not just on + RS/6000. + * mips.h (_RDATA, _SDATA, _SBSS, _LIT4, _LIT8, STYP_RDATA, + STYP_SDATA, STYP_SBSS, STYP_LIT4, STYP_LIT8): Defined. + (CODE_MASK, MIPS_IS_STAB, MIPS_MARK_STAB, MIPS_UNMARK_STAB, + STABS_SYMBOL): Moved in from gdb/mipsread.c. + +Wed Jan 6 14:01:46 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h: removed STYP_* defines, since they duplicated + those in internal.h. + +Tue Dec 29 15:40:07 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: define I386AIXMAGIC for Danbury AIX PS/2 compiler. + +Sat Dec 12 16:07:57 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: don't define BTYPE, ISPTR, ISFCN, ISARY, DECREF: they + are defined in internal.h. + +Thu Nov 12 09:52:01 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: (internal_reloc): r_offset is now a long. + * z8k.h: slight comment enhancement + +Wed Sep 30 07:46:08 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: changed z8k reloc types + +Fri Aug 28 10:16:31 1992 Brendan Kehoe (brendan@cygnus.com) + + * we32k.h: new file + +Thu Aug 27 13:00:01 1992 Brendan Kehoe (brendan@cygnus.com) + + * symconst.h: comment out cruft at the end of #endif + +Tue Aug 25 15:06:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added #define for STYP_LIT, removed from a29k and + h8300. + + * z8k.h: added z8000 support + +Thu Jul 16 16:32:00 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added R_RELLONG_NEG reloc type + +Fri Jun 12 20:11:04 1992 John Gilmore (gnu at cygnus.com) + + * symconst.h: Fix unterminated comment. + +Wed Jun 10 07:57:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * i386.h: a.out magic numbers from + mohring@informatik.tu-muenchen.de + +Mon Jun 8 20:13:33 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h, mips.h: Use unsigned chars everywhere. + (Suggested by Antti Miettinen.) + +Tue Apr 14 15:18:44 1992 John Gilmore (gnu at cygnus.com) + + * sym.h: Add comments. + * symconst.h: Merge with Fred's changes. + +Tue Apr 14 14:30:05 1992 Fred Fish (fnf@cygnus.com) + + * symconst.h: Pick up SGI defines for stStruct, stUnion, stEnum, + langCplusplus, and langCplusplusV2. + +Thu Apr 2 19:47:43 1992 John Gilmore (gnu at cygnus.com) + + * sym.h, symconst.h: MIPS has provided redistributable versions + of these files. Thanks! + * ecoff-ext.h: Add weakext bit to match new sym.h. + +Fri Mar 6 00:10:46 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: Add relative file descriptors. + +Thu Feb 27 11:53:04 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: New file for external (in-file) form of ecoff + symbol structures. + +Thu Feb 6 11:33:32 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * h8300.h: made the external_lineno l_lnno field 4 bytes wide. + andded GET/PUT_LINENO_LNNO macros + +Sat Nov 30 20:38:35 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * a29k.h, h8300.h, i386.h, i960.h, internal.h, m68k.h, m88k.h, + mips.h, rs6000.h: Move from above coff-.h. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/coff/alpha.h b/external/gpl3/gdb/dist/include/coff/alpha.h new file mode 100644 index 000000000000..81516892a050 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/alpha.h @@ -0,0 +1,386 @@ +/* ECOFF support on Alpha machines. + coff/ecoff.h must be included before this file. + + Copyright 2001, 2005, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + unsigned char f_magic[2]; /* magic number */ + unsigned char f_nscns[2]; /* number of sections */ + unsigned char f_timdat[4]; /* time & date stamp */ + unsigned char f_symptr[8]; /* file pointer to symtab */ + unsigned char f_nsyms[4]; /* number of symtab entries */ + unsigned char f_opthdr[2]; /* sizeof(optional hdr) */ + unsigned char f_flags[2]; /* flags */ +}; + +/* Magic numbers are defined in coff/ecoff.h. */ +#define ALPHA_ECOFF_BADMAG(x) \ + ((x).f_magic != ALPHA_MAGIC && (x).f_magic != ALPHA_MAGIC_BSD) + +#define ALPHA_ECOFF_COMPRESSEDMAG(x) \ + ((x).f_magic == ALPHA_MAGIC_COMPRESSED) + +/* The object type is encoded in the f_flags. */ +#define F_ALPHA_OBJECT_TYPE_MASK 0x3000 +#define F_ALPHA_NO_SHARED 0x1000 +#define F_ALPHA_SHARABLE 0x2000 +#define F_ALPHA_CALL_SHARED 0x3000 + +#define FILHDR struct external_filehdr +#define FILHSZ 24 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char bldrev[2]; /* ?? */ + unsigned char padding[2]; /* pad to quadword boundary */ + unsigned char tsize[8]; /* text size in bytes */ + unsigned char dsize[8]; /* initialized data " " */ + unsigned char bsize[8]; /* uninitialized data " " */ + unsigned char entry[8]; /* entry pt. */ + unsigned char text_start[8]; /* base of text used for this file */ + unsigned char data_start[8]; /* base of data used for this file */ + unsigned char bss_start[8]; /* base of bss used for this file */ + unsigned char gprmask[4]; /* bitmask of general registers used */ + unsigned char fprmask[4]; /* bitmask of floating point registers used */ + unsigned char gp_value[8]; /* value for gp register */ +} AOUTHDR; + +/* compute size of a header */ + +#define AOUTSZ 80 +#define AOUTHDRSZ 80 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + unsigned char s_name[8]; /* section name */ + unsigned char s_paddr[8]; /* physical address, aliased s_nlib */ + unsigned char s_vaddr[8]; /* virtual address */ + unsigned char s_size[8]; /* section size */ + unsigned char s_scnptr[8]; /* file ptr to raw data for section */ + unsigned char s_relptr[8]; /* file ptr to relocation */ + unsigned char s_lnnoptr[8]; /* file ptr to line numbers */ + unsigned char s_nreloc[2]; /* number of relocation entries */ + unsigned char s_nlnno[2]; /* number of line number entries*/ + unsigned char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 64 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + unsigned char r_vaddr[8]; + unsigned char r_symndx[4]; + unsigned char r_bits[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* Constants to unpack the r_bits field. The Alpha seems to always be + little endian, so I haven't bothered to define big endian variants + of these. */ + +#define RELOC_BITS0_TYPE_LITTLE 0xff +#define RELOC_BITS0_TYPE_SH_LITTLE 0 + +#define RELOC_BITS1_EXTERN_LITTLE 0x01 + +#define RELOC_BITS1_OFFSET_LITTLE 0x7e +#define RELOC_BITS1_OFFSET_SH_LITTLE 1 + +#define RELOC_BITS1_RESERVED_LITTLE 0x80 +#define RELOC_BITS1_RESERVED_SH_LITTLE 7 +#define RELOC_BITS2_RESERVED_LITTLE 0xff +#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 +#define RELOC_BITS3_RESERVED_LITTLE 0x03 +#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 + +#define RELOC_BITS3_SIZE_LITTLE 0xfc +#define RELOC_BITS3_SIZE_SH_LITTLE 2 + +/* The r_type field in a reloc is one of the following values. */ +#define ALPHA_R_IGNORE 0 +#define ALPHA_R_REFLONG 1 +#define ALPHA_R_REFQUAD 2 +#define ALPHA_R_GPREL32 3 +#define ALPHA_R_LITERAL 4 +#define ALPHA_R_LITUSE 5 +#define ALPHA_R_GPDISP 6 +#define ALPHA_R_BRADDR 7 +#define ALPHA_R_HINT 8 +#define ALPHA_R_SREL16 9 +#define ALPHA_R_SREL32 10 +#define ALPHA_R_SREL64 11 +#define ALPHA_R_OP_PUSH 12 +#define ALPHA_R_OP_STORE 13 +#define ALPHA_R_OP_PSUB 14 +#define ALPHA_R_OP_PRSHIFT 15 +#define ALPHA_R_GPVALUE 16 +#define ALPHA_R_GPRELHIGH 17 +#define ALPHA_R_GPRELLOW 18 +#define ALPHA_R_IMMED 19 + +/* Overloaded reloc value used by Net- and OpenBSD. */ +#define ALPHA_R_LITERALSLEAZY 17 + +/* With ALPHA_R_LITUSE, the r_size field is one of the following values. */ +#define ALPHA_R_LU_BASE 1 +#define ALPHA_R_LU_BYTOFF 2 +#define ALPHA_R_LU_JSR 3 + +/* With ALPHA_R_IMMED, the r_size field is one of the following values. */ +#define ALPHA_R_IMMED_GP_16 1 +#define ALPHA_R_IMMED_GP_HI32 2 +#define ALPHA_R_IMMED_SCN_HI32 3 +#define ALPHA_R_IMMED_BR_HI32 4 +#define ALPHA_R_IMMED_LO32 5 + +/********************** SYMBOLIC INFORMATION **********************/ + +/* Written by John Gilmore. */ + +/* ECOFF uses COFF-like section structures, but its own symbol format. + This file defines the symbol format in fields whose size and alignment + will not vary on different host systems. */ + +/* File header as a set of bytes */ + +struct hdr_ext +{ + unsigned char h_magic[2]; + unsigned char h_vstamp[2]; + unsigned char h_ilineMax[4]; + unsigned char h_idnMax[4]; + unsigned char h_ipdMax[4]; + unsigned char h_isymMax[4]; + unsigned char h_ioptMax[4]; + unsigned char h_iauxMax[4]; + unsigned char h_issMax[4]; + unsigned char h_issExtMax[4]; + unsigned char h_ifdMax[4]; + unsigned char h_crfd[4]; + unsigned char h_iextMax[4]; + unsigned char h_cbLine[8]; + unsigned char h_cbLineOffset[8]; + unsigned char h_cbDnOffset[8]; + unsigned char h_cbPdOffset[8]; + unsigned char h_cbSymOffset[8]; + unsigned char h_cbOptOffset[8]; + unsigned char h_cbAuxOffset[8]; + unsigned char h_cbSsOffset[8]; + unsigned char h_cbSsExtOffset[8]; + unsigned char h_cbFdOffset[8]; + unsigned char h_cbRfdOffset[8]; + unsigned char h_cbExtOffset[8]; +}; + +/* File descriptor external record */ + +struct fdr_ext +{ + unsigned char f_adr[8]; + unsigned char f_cbLineOffset[8]; + unsigned char f_cbLine[8]; + unsigned char f_cbSs[8]; + unsigned char f_rss[4]; + unsigned char f_issBase[4]; + unsigned char f_isymBase[4]; + unsigned char f_csym[4]; + unsigned char f_ilineBase[4]; + unsigned char f_cline[4]; + unsigned char f_ioptBase[4]; + unsigned char f_copt[4]; + unsigned char f_ipdFirst[4]; + unsigned char f_cpd[4]; + unsigned char f_iauxBase[4]; + unsigned char f_caux[4]; + unsigned char f_rfdBase[4]; + unsigned char f_crfd[4]; + unsigned char f_bits1[1]; + unsigned char f_bits2[3]; + unsigned char f_padding[4]; +}; + +#define FDR_BITS1_LANG_BIG 0xF8 +#define FDR_BITS1_LANG_SH_BIG 3 +#define FDR_BITS1_LANG_LITTLE 0x1F +#define FDR_BITS1_LANG_SH_LITTLE 0 + +#define FDR_BITS1_FMERGE_BIG 0x04 +#define FDR_BITS1_FMERGE_LITTLE 0x20 + +#define FDR_BITS1_FREADIN_BIG 0x02 +#define FDR_BITS1_FREADIN_LITTLE 0x40 + +#define FDR_BITS1_FBIGENDIAN_BIG 0x01 +#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 + +#define FDR_BITS2_GLEVEL_BIG 0xC0 +#define FDR_BITS2_GLEVEL_SH_BIG 6 +#define FDR_BITS2_GLEVEL_LITTLE 0x03 +#define FDR_BITS2_GLEVEL_SH_LITTLE 0 + +/* We ignore the `reserved' field in bits2. */ + +/* Procedure descriptor external record */ + +struct pdr_ext { + unsigned char p_adr[8]; + unsigned char p_cbLineOffset[8]; + unsigned char p_isym[4]; + unsigned char p_iline[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_iopt[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_lnLow[4]; + unsigned char p_lnHigh[4]; + unsigned char p_gp_prologue[1]; + unsigned char p_bits1[1]; + unsigned char p_bits2[1]; + unsigned char p_localoff[1]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; +}; + +#define PDR_BITS1_GP_USED_BIG 0x80 +#define PDR_BITS1_REG_FRAME_BIG 0x40 +#define PDR_BITS1_PROF_BIG 0x20 +#define PDR_BITS1_RESERVED_BIG 0x1f +#define PDR_BITS1_RESERVED_SH_LEFT_BIG 8 +#define PDR_BITS2_RESERVED_BIG 0xff +#define PDR_BITS2_RESERVED_SH_BIG 0 + +#define PDR_BITS1_GP_USED_LITTLE 0x01 +#define PDR_BITS1_REG_FRAME_LITTLE 0x02 +#define PDR_BITS1_PROF_LITTLE 0x04 +#define PDR_BITS1_RESERVED_LITTLE 0xf8 +#define PDR_BITS1_RESERVED_SH_LITTLE 3 +#define PDR_BITS2_RESERVED_LITTLE 0xff +#define PDR_BITS2_RESERVED_SH_LEFT_LITTLE 5 + +/* Line numbers */ + +struct line_ext { + unsigned char l_line[4]; +}; + +/* Symbol external record */ + +struct sym_ext { + unsigned char s_value[8]; + unsigned char s_iss[4]; + unsigned char s_bits1[1]; + unsigned char s_bits2[1]; + unsigned char s_bits3[1]; + unsigned char s_bits4[1]; +}; + +#define SYM_BITS1_ST_BIG 0xFC +#define SYM_BITS1_ST_SH_BIG 2 +#define SYM_BITS1_ST_LITTLE 0x3F +#define SYM_BITS1_ST_SH_LITTLE 0 + +#define SYM_BITS1_SC_BIG 0x03 +#define SYM_BITS1_SC_SH_LEFT_BIG 3 +#define SYM_BITS1_SC_LITTLE 0xC0 +#define SYM_BITS1_SC_SH_LITTLE 6 + +#define SYM_BITS2_SC_BIG 0xE0 +#define SYM_BITS2_SC_SH_BIG 5 +#define SYM_BITS2_SC_LITTLE 0x07 +#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 + +#define SYM_BITS2_RESERVED_BIG 0x10 +#define SYM_BITS2_RESERVED_LITTLE 0x08 + +#define SYM_BITS2_INDEX_BIG 0x0F +#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 +#define SYM_BITS2_INDEX_LITTLE 0xF0 +#define SYM_BITS2_INDEX_SH_LITTLE 4 + +#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 +#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 + +#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 +#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 + +/* External symbol external record */ + +struct ext_ext { + struct sym_ext es_asym; + unsigned char es_bits1[1]; + unsigned char es_bits2[3]; + unsigned char es_ifd[4]; +}; + +#define EXT_BITS1_JMPTBL_BIG 0x80 +#define EXT_BITS1_JMPTBL_LITTLE 0x01 + +#define EXT_BITS1_COBOL_MAIN_BIG 0x40 +#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 + +#define EXT_BITS1_WEAKEXT_BIG 0x20 +#define EXT_BITS1_WEAKEXT_LITTLE 0x04 + +/* Dense numbers external record */ + +struct dnr_ext { + unsigned char d_rfd[4]; + unsigned char d_index[4]; +}; + +/* Relative file descriptor */ + +struct rfd_ext { + unsigned char rfd[4]; +}; + +/* Optimizer symbol external record */ + +struct opt_ext { + unsigned char o_bits1[1]; + unsigned char o_bits2[1]; + unsigned char o_bits3[1]; + unsigned char o_bits4[1]; + struct rndx_ext o_rndx; + unsigned char o_offset[4]; +}; + +#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 +#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 + +#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 +#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 + +#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 +#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 diff --git a/external/gpl3/gdb/dist/include/coff/apollo.h b/external/gpl3/gdb/dist/include/coff/apollo.h new file mode 100644 index 000000000000..1d4802f119e0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/apollo.h @@ -0,0 +1,125 @@ +/* coff information for Apollo M68K + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* Apollo 68000-based machines have a different magic number. This comes + * from /usr/include/apollo/filehdr.h + */ +#define APOLLOM68KMAGIC 0627 + +#define OMAGIC M68MAGIC +#define M68KBADMAG(x) (((x).f_magic!=MC68MAGIC) && ((x).f_magic!=MC68KWRMAGIC) && ((x).f_magic!=MC68TVMAGIC) && \ + ((x).f_magic!=MC68KROMAGIC) && ((x).f_magic!=MC68KPGMAGIC) && ((x).f_magic!=M68MAGIC) && ((x).f_magic!=M68TVMAGIC) && \ + ((x).f_magic!=APOLLOM68KMAGIC) ) + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char o_sri[4]; /* Apollo specific - .sri data pointer */ + char o_inlib[4]; /* Apollo specific - .inlib data pointer */ + char vid[8]; /* Apollo specific - 64 bit version ID */ +} +AOUTHDR; + +#define APOLLO_COFF_VERSION_NUMBER 1 /* the value of the aouthdr magic */ +#define AOUTHDRSZ 44 +#define AOUTSZ 44 + +/* Apollo allowa for larger section names by allowing + them to be in the string table. */ + +/* If s_zeores is all zeroes, s_offset gives the real + location of the name in the string table. */ + +#define s_zeroes section_name.s_name +#define s_offset (section_name.s_name+4) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" +#define _LINES ".lines" +#define _BLOCKS ".blocks" +#define _SRI ".sri" /* Static Resource Information (systype, + et al.) */ +#define _MIR ".mir" /* Module Information Records */ +#define _APTV ".aptv" /* Apollo-style transfer vectors. */ +#define _INLIB ".inlib" /* Shared Library information */ +#define _RWDI ".rwdi" /* Read/write data initialization directives for + compressed sections */ +#define _UNWIND ".unwind" /* Stack unwind information */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif + +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +/* Apollo specific STYP flags */ + +#define STYP_RELOCATED_NOT_LOADED 0x00010000 /* Section is relocated normally during linking, but need + not be loaded during program execution */ +#define STYP_DEBUG 0x00020000 /* debug section */ +#define STYP_OVERLAY 0x00040000 /* Section is overlayed */ +#define STYP_INSTRUCTION 0x00200000 /* Section contains executable code */ + +#define STYP_ZERO 0x00800000 /* Section is initialized to zero */ +#define STYP_INSTALLED 0x02000000 /* Section should be installable in KGT */ +#define STYP_LOOK_INSTALLED 0x04000000 /* Look for section in KGT */ +#define STYP_SECALIGN1 0x08000000 /* Specially aligned section */ +#define STYP_SECALIGN2 0x10000000 /* " " " */ +#define STYP_COMPRESSED 0x20000000 /* No section data per se (s_scnptr = 0), but there are + initialization directives for it in .rwdi section + (used in conjunction with STYP_BSS) */ diff --git a/external/gpl3/gdb/dist/include/coff/arm.h b/external/gpl3/gdb/dist/include/coff/arm.h new file mode 100644 index 000000000000..9c3400539790 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/arm.h @@ -0,0 +1,128 @@ +/* ARM COFF support for BFD. + Copyright 1998, 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#define COFFARM 1 + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_INTERWORK file supports switching between ARM and Thumb instruction sets + F_INTERWORK_SET the F_INTERWORK bit is valid + F_APCS_FLOAT code passes float arguments in float registers + F_PIC code is reentrant/position-independent + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + F_APCS_26 file uses 26 bit ARM Procedure Calling Standard + F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised + F_SOFT_FLOAT code does not use floating point instructions. */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_INTERWORK (0x0010) +#define F_INTERWORK_SET (0x0020) +#define F_APCS_FLOAT (0x0040) +#undef F_AR16WR +#define F_PIC (0x0080) +#define F_AR32WR (0x0100) +#define F_APCS_26 (0x0400) +#define F_APCS_SET (0x0800) +#define F_SOFT_FLOAT (0x2000) +#define F_VFP_FLOAT (0x4000) + +/* Bits stored in flags field of the internal_f structure */ + +#define F_INTERWORK (0x0010) +#define F_APCS_FLOAT (0x0040) +#define F_PIC (0x0080) +#define F_APCS26 (0x1000) +#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400) +#define F_ARM_2 (0x0400) +#define F_ARM_2a (0x0800) +#define F_ARM_3 (0x0c00) +#define F_ARM_3M (0x4000) +#define F_ARM_4 (0x4400) +#define F_ARM_4T (0x4800) +#define F_ARM_5 (0x4c00) + +/* + ARMMAGIC ought to encoded the procesor type, + but it is too late to change it now, instead + the flags field of the internal_f structure + is used as shown above. + + XXX - NC 5/6/97. */ + +#define ARMMAGIC 0xa00 /* I just made this up */ + +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC)) + +#define ARMPEMAGIC 0x1c0 +#define THUMBPEMAGIC 0x1c2 + +#undef ARMBADMAG +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC)) + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/* We use the .rdata section to hold read only data. */ +#define _LIT ".rdata" + +/********************** RELOCATION DIRECTIVES **********************/ +#ifdef ARM_WINCE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +#else +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 +#endif + +#define ARM_NOTE_SECTION ".note" diff --git a/external/gpl3/gdb/dist/include/coff/aux-coff.h b/external/gpl3/gdb/dist/include/coff/aux-coff.h new file mode 100644 index 000000000000..de7979a6ac3a --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/aux-coff.h @@ -0,0 +1,49 @@ +/* Modifications of internal.h and m68k.h needed by A/UX + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. + + Suggested by Ian Lance Taylor */ + +#ifndef GNU_COFF_AUX_H +#define GNU_COFF_AUX_H 1 + +#include "coff/internal.h" +#include "coff/m68k.h" + +/* Section contains 64-byte padded pathnames of shared libraries */ +#undef STYP_LIB +#define STYP_LIB 0x200 + +/* Section contains shared library initialization code */ +#undef STYP_INIT +#define STYP_INIT 0x400 + +/* Section contains .ident information */ +#undef STYP_IDENT +#define STYP_IDENT 0x800 + +/* Section types used by bfd and gas not defined (directly) by A/UX */ +#undef STYP_OVER +#define STYP_OVER 0 +#undef STYP_INFO +#define STYP_INFO STYP_IDENT + +/* Traditional name of the section tagged with STYP_LIB */ +#define _LIB ".lib" + +#endif /* GNU_COFF_AUX_H */ diff --git a/external/gpl3/gdb/dist/include/coff/ecoff.h b/external/gpl3/gdb/dist/include/coff/ecoff.h new file mode 100644 index 000000000000..a7991a998b60 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/ecoff.h @@ -0,0 +1,411 @@ +/* Generic ECOFF support. + This does not include symbol information, found in sym.h and + symconst.h. + + Copyright 2001, 2002, 2003, 2004, 2005, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef ECOFF_H +#define ECOFF_H + +/* Mips magic numbers used in filehdr. MIPS_MAGIC_LITTLE is used on + little endian machines. MIPS_MAGIC_BIG is used on big endian + machines. Where is MIPS_MAGIC_1 from? */ +#define MIPS_MAGIC_1 0x0180 +#define MIPS_MAGIC_LITTLE 0x0162 +#define MIPS_MAGIC_BIG 0x0160 + +/* These are the magic numbers used for MIPS code compiled at ISA + level 2. */ +#define MIPS_MAGIC_LITTLE2 0x0166 +#define MIPS_MAGIC_BIG2 0x0163 + +/* These are the magic numbers used for MIPS code compiled at ISA + level 3. */ +#define MIPS_MAGIC_LITTLE3 0x142 +#define MIPS_MAGIC_BIG3 0x140 + +/* Alpha magic numbers used in filehdr. */ +#define ALPHA_MAGIC 0x183 +#define ALPHA_MAGIC_BSD 0x185 +/* A compressed version of an ALPHA_MAGIC file created by DEC's tools. */ +#define ALPHA_MAGIC_COMPRESSED 0x188 + +/* Magic numbers used in a.out header. */ +#define ECOFF_AOUT_OMAGIC 0407 /* not demand paged (ld -N). */ +#define ECOFF_AOUT_ZMAGIC 0413 /* demand load format, eg normal ld output */ + +/* Names of special sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _RDATA ".rdata" +#define _SDATA ".sdata" +#define _SBSS ".sbss" +#define _LITA ".lita" +#define _LIT4 ".lit4" +#define _LIT8 ".lit8" +#define _LIB ".lib" +#define _INIT ".init" +#define _FINI ".fini" +#define _PDATA ".pdata" +#define _XDATA ".xdata" +#define _GOT ".got" +#define _HASH ".hash" +#define _DYNSYM ".dynsym" +#define _DYNSTR ".dynstr" +#define _RELDYN ".rel.dyn" +#define _CONFLIC ".conflic" +#define _COMMENT ".comment" +#define _LIBLIST ".liblist" +#define _DYNAMIC ".dynamic" +#define _RCONST ".rconst" + +/* ECOFF uses some additional section flags. */ +#define STYP_RDATA 0x100 +#define STYP_SDATA 0x200 +#define STYP_SBSS 0x400 +#define STYP_GOT 0x1000 +#define STYP_DYNAMIC 0x2000 +#define STYP_DYNSYM 0x4000 +#define STYP_RELDYN 0x8000 +#define STYP_DYNSTR 0x10000 +#define STYP_HASH 0x20000 +#define STYP_LIBLIST 0x40000 +#define STYP_CONFLIC 0x100000 +#define STYP_ECOFF_FINI 0x1000000 +#define STYP_EXTENDESC 0x2000000 /* 0x02FFF000 bits => scn type, rest clr */ +#define STYP_LITA 0x4000000 +#define STYP_LIT8 0x8000000 +#define STYP_LIT4 0x10000000 +#define STYP_ECOFF_LIB 0x40000000 +#define STYP_ECOFF_INIT 0x80000000 +#define STYP_OTHER_LOAD (STYP_ECOFF_INIT | STYP_ECOFF_FINI) + +/* extended section types */ +#define STYP_COMMENT 0x2100000 +#define STYP_RCONST 0x2200000 +#define STYP_XDATA 0x2400000 +#define STYP_PDATA 0x2800000 + +/* The linker needs a section to hold small common variables while + linking. There is no convenient way to create it when the linker + needs it, so we always create one for each BFD. We then avoid + writing it out. */ +#define SCOMMON ".scommon" + +/* If the extern bit in a reloc is 1, then r_symndx is an index into + the external symbol table. If the extern bit is 0, then r_symndx + indicates a section, and is one of the following values. */ +#define RELOC_SECTION_NONE 0 +#define RELOC_SECTION_TEXT 1 +#define RELOC_SECTION_RDATA 2 +#define RELOC_SECTION_DATA 3 +#define RELOC_SECTION_SDATA 4 +#define RELOC_SECTION_SBSS 5 +#define RELOC_SECTION_BSS 6 +#define RELOC_SECTION_INIT 7 +#define RELOC_SECTION_LIT8 8 +#define RELOC_SECTION_LIT4 9 +#define RELOC_SECTION_XDATA 10 +#define RELOC_SECTION_PDATA 11 +#define RELOC_SECTION_FINI 12 +#define RELOC_SECTION_LITA 13 +#define RELOC_SECTION_ABS 14 +#define RELOC_SECTION_RCONST 15 + +#define NUM_RELOC_SECTIONS 16 + +/********************** STABS **********************/ + +/* gcc uses mips-tfile to output type information in special stabs + entries. These must match the corresponding definition in + gcc/config/mips.h. At some point, these should probably go into a + shared include file, but currently gcc and gdb do not share any + directories. */ +#define CODE_MASK 0x8F300 +#define ECOFF_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) +#define ECOFF_MARK_STAB(code) ((code)+CODE_MASK) +#define ECOFF_UNMARK_STAB(code) ((code)-CODE_MASK) +#define STABS_SYMBOL "@stabs" + +/********************** COFF **********************/ + +/* gcc also uses mips-tfile to output COFF debugging information. + These are the values it uses when outputting the .type directive. + These should also be in a shared include file. */ +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +/********************** AUX **********************/ + +/* The auxiliary type information is the same on all known ECOFF + targets. I can't see any reason that it would ever change, so I am + going to gamble and define the external structures here, in the + target independent ECOFF header file. The internal forms are + defined in coff/sym.h, which was originally donated by MIPS + Computer Systems. */ + +/* Type information external record */ + +struct tir_ext { + unsigned char t_bits1[1]; + unsigned char t_tq45[1]; + unsigned char t_tq01[1]; + unsigned char t_tq23[1]; +}; + +#define TIR_BITS1_FBITFIELD_BIG ((unsigned int) 0x80) +#define TIR_BITS1_FBITFIELD_LITTLE ((unsigned int) 0x01) + +#define TIR_BITS1_CONTINUED_BIG ((unsigned int) 0x40) +#define TIR_BITS1_CONTINUED_LITTLE ((unsigned int) 0x02) + +#define TIR_BITS1_BT_BIG ((unsigned int) 0x3F) +#define TIR_BITS1_BT_SH_BIG 0 +#define TIR_BITS1_BT_LITTLE ((unsigned int) 0xFC) +#define TIR_BITS1_BT_SH_LITTLE 2 + +#define TIR_BITS_TQ4_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ4_SH_BIG 4 +#define TIR_BITS_TQ5_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ5_SH_BIG 0 +#define TIR_BITS_TQ4_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ4_SH_LITTLE 0 +#define TIR_BITS_TQ5_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ5_SH_LITTLE 4 + +#define TIR_BITS_TQ0_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ0_SH_BIG 4 +#define TIR_BITS_TQ1_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ1_SH_BIG 0 +#define TIR_BITS_TQ0_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ0_SH_LITTLE 0 +#define TIR_BITS_TQ1_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ1_SH_LITTLE 4 + +#define TIR_BITS_TQ2_BIG ((unsigned int) 0xF0) +#define TIR_BITS_TQ2_SH_BIG 4 +#define TIR_BITS_TQ3_BIG ((unsigned int) 0x0F) +#define TIR_BITS_TQ3_SH_BIG 0 +#define TIR_BITS_TQ2_LITTLE ((unsigned int) 0x0F) +#define TIR_BITS_TQ2_SH_LITTLE 0 +#define TIR_BITS_TQ3_LITTLE ((unsigned int) 0xF0) +#define TIR_BITS_TQ3_SH_LITTLE 4 + +/* Relative symbol external record */ + +struct rndx_ext { + unsigned char r_bits[4]; +}; + +#define RNDX_BITS0_RFD_SH_LEFT_BIG 4 +#define RNDX_BITS1_RFD_BIG ((unsigned int) 0xF0) +#define RNDX_BITS1_RFD_SH_BIG 4 + +#define RNDX_BITS0_RFD_SH_LEFT_LITTLE 0 +#define RNDX_BITS1_RFD_LITTLE ((unsigned int) 0x0F) +#define RNDX_BITS1_RFD_SH_LEFT_LITTLE 8 + +#define RNDX_BITS1_INDEX_BIG ((unsigned int) 0x0F) +#define RNDX_BITS1_INDEX_SH_LEFT_BIG 16 +#define RNDX_BITS2_INDEX_SH_LEFT_BIG 8 +#define RNDX_BITS3_INDEX_SH_LEFT_BIG 0 + +#define RNDX_BITS1_INDEX_LITTLE ((unsigned int) 0xF0) +#define RNDX_BITS1_INDEX_SH_LITTLE 4 +#define RNDX_BITS2_INDEX_SH_LEFT_LITTLE 4 +#define RNDX_BITS3_INDEX_SH_LEFT_LITTLE 12 + +/* Auxiliary symbol information external record */ + +union aux_ext { + struct tir_ext a_ti; + struct rndx_ext a_rndx; + unsigned char a_dnLow[4]; + unsigned char a_dnHigh[4]; + unsigned char a_isym[4]; + unsigned char a_iss[4]; + unsigned char a_width[4]; + unsigned char a_count[4]; +}; + +#define AUX_GET_ANY(bigend, ax, field) \ + ((bigend) ? bfd_getb32 ((ax)->field) : bfd_getl32 ((ax)->field)) + +#define AUX_GET_DNLOW(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_dnLow) +#define AUX_GET_DNHIGH(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_dnHigh) +#define AUX_GET_ISYM(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_isym) +#define AUX_GET_ISS(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_iss) +#define AUX_GET_WIDTH(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_width) +#define AUX_GET_COUNT(bigend, ax) AUX_GET_ANY ((bigend), (ax), a_count) + +#define AUX_PUT_ANY(bigend, val, ax, field) \ + ((bigend) \ + ? (bfd_putb32 ((bfd_vma) (val), (ax)->field), 0) \ + : (bfd_putl32 ((bfd_vma) (val), (ax)->field), 0)) + +#define AUX_PUT_DNLOW(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_dnLow) +#define AUX_PUT_DNHIGH(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_dnHigh) +#define AUX_PUT_ISYM(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_isym) +#define AUX_PUT_ISS(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_iss) +#define AUX_PUT_WIDTH(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_width) +#define AUX_PUT_COUNT(bigend, val, ax) \ + AUX_PUT_ANY ((bigend), (val), (ax), a_count) + +/********************** SYMBOLS **********************/ + +/* For efficiency, gdb deals directly with the unswapped symbolic + information (that way it only takes the time to swap information + that it really needs to read). gdb originally retrieved the + information directly from the BFD backend information, but that + strategy, besides being sort of ugly, does not work for MIPS ELF, + which also uses ECOFF debugging information. This structure holds + pointers to the (mostly) unswapped symbolic information. */ + +struct ecoff_debug_info +{ + /* The swapped ECOFF symbolic header. */ + HDRR symbolic_header; + + /* Pointers to the unswapped symbolic information. Note that the + pointers to external structures point to different sorts of + information on different ECOFF targets. The ecoff_debug_swap + structure provides the sizes of the structures and the functions + needed to swap the information in and out. These pointers are + all pointers to arrays, not single structures. They will be NULL + if there are no instances of the relevant structure. These + fields are also used by the assembler to output ECOFF debugging + information. */ + unsigned char *line; + void *external_dnr; /* struct dnr_ext */ + void *external_pdr; /* struct pdr_ext */ + void *external_sym; /* struct sym_ext */ + void *external_opt; /* struct opt_ext */ + union aux_ext *external_aux; + char *ss; + char *ssext; + void *external_fdr; /* struct fdr_ext */ + void *external_rfd; /* struct rfd_ext */ + void *external_ext; /* struct ext_ext */ + + /* These fields are used when linking. They may disappear at some + point. */ + char *ssext_end; + void *external_ext_end; + + /* When linking, this field holds a mapping from the input FDR + numbers to the output numbers, and is used when writing out the + external symbols. It is NULL if no mapping is required. */ + RFDT *ifdmap; + + /* The swapped FDR information. Currently this is never NULL, but + code using this structure should probably double-check in case + this changes in the future. This is a pointer to an array, not a + single structure. */ + FDR *fdr; +}; + +/* These structures are used by the ECOFF find_nearest_line function. */ + +struct ecoff_fdrtab_entry +{ + /* Base address in .text of this FDR. */ + bfd_vma base_addr; + FDR *fdr; +}; + +struct ecoff_find_line +{ + /* Allocated memory to hold function and file names. */ + char *find_buffer; + + /* FDR table, sorted by address: */ + long fdrtab_len; + struct ecoff_fdrtab_entry *fdrtab; + + /* Cache entry for most recently found line information. The sect + field is NULL if this cache does not contain valid information. */ + struct + { + asection *sect; + bfd_vma start; + bfd_vma stop; + const char *filename; + const char *functionname; + unsigned int line_num; + } cache; +}; + +/********************** SWAPPING **********************/ + +/* The generic ECOFF code needs to be able to swap debugging + information in and out in the specific format used by a particular + ECOFF implementation. This structure provides the information + needed to do this. */ + +struct ecoff_debug_swap +{ + /* Symbol table magic number. */ + int sym_magic; + /* Alignment of debugging information. E.g., 4. */ + bfd_size_type debug_align; + /* Sizes of external symbolic information. */ + bfd_size_type external_hdr_size; + bfd_size_type external_dnr_size; + bfd_size_type external_pdr_size; + bfd_size_type external_sym_size; + bfd_size_type external_opt_size; + bfd_size_type external_fdr_size; + bfd_size_type external_rfd_size; + bfd_size_type external_ext_size; + /* Functions to swap in external symbolic data. */ + void (*swap_hdr_in) (bfd *, void *, HDRR *); + void (*swap_dnr_in) (bfd *, void *, DNR *); + void (*swap_pdr_in) (bfd *, void *, PDR *); + void (*swap_sym_in) (bfd *, void *, SYMR *); + void (*swap_opt_in) (bfd *, void *, OPTR *); + void (*swap_fdr_in) (bfd *, void *, FDR *); + void (*swap_rfd_in) (bfd *, void *, RFDT *); + void (*swap_ext_in) (bfd *, void *, EXTR *); + void (*swap_tir_in) (int, const struct tir_ext *, TIR *); + void (*swap_rndx_in) (int, const struct rndx_ext *, RNDXR *); + /* Functions to swap out external symbolic data. */ + void (*swap_hdr_out) (bfd *, const HDRR *, void *); + void (*swap_dnr_out) (bfd *, const DNR *, void *); + void (*swap_pdr_out) (bfd *, const PDR *, void *); + void (*swap_sym_out) (bfd *, const SYMR *, void *); + void (*swap_opt_out) (bfd *, const OPTR *, void *); + void (*swap_fdr_out) (bfd *, const FDR *, void *); + void (*swap_rfd_out) (bfd *, const RFDT *, void *); + void (*swap_ext_out) (bfd *, const EXTR *, void *); + void (*swap_tir_out) (int, const TIR *, struct tir_ext *); + void (*swap_rndx_out) (int, const RNDXR *, struct rndx_ext *); + /* Function to read symbol data and set up pointers in + ecoff_debug_info structure. The section argument is used for + ELF, not straight ECOFF. */ + bfd_boolean (*read_debug_info) (bfd *, asection *, struct ecoff_debug_info *); +}; + +#endif /* ! defined (ECOFF_H) */ diff --git a/external/gpl3/gdb/dist/include/coff/external.h b/external/gpl3/gdb/dist/include/coff/external.h new file mode 100644 index 000000000000..4bf594d3db8e --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/external.h @@ -0,0 +1,269 @@ +/* external.h -- External COFF structures + + Copyright 2001, 2006, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef COFF_EXTERNAL_H +#define COFF_EXTERNAL_H + +#ifndef DO_NOT_DEFINE_FILHDR +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + }; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 +#endif + +#ifndef DO_NOT_DEFINE_AOUTHDR +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr + { + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + } ATTRIBUTE_PACKED +AOUTHDR; + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + +typedef struct external_aouthdr64 +{ + char magic[2]; /* Type of file. */ + char vstamp[2]; /* Version stamp. */ + char tsize[4]; /* Text size in bytes, padded to FW bdry*/ + char dsize[4]; /* Initialized data " ". */ + char bsize[4]; /* Uninitialized data " ". */ + char entry[4]; /* Entry pt. */ + char text_start[4]; /* Base of text used for this file. */ +} +AOUTHDR64; +#define AOUTHDRSZ64 24 + +#endif /* not DO_NOT_DEFINE_AOUTHDR */ + +#ifndef DO_NOT_DEFINE_SCNHDR +/********************** SECTION HEADER **********************/ + +struct external_scnhdr + { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ + }; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections. */ + +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" +#define _LIB ".lib" +#endif /* not DO_NOT_DEFINE_SCNHDR */ + +#ifndef DO_NOT_DEFINE_LINENO + +/********************** LINE NUMBERS **********************/ + +#ifndef L_LNNO_SIZE +#error L_LNNO_SIZE needs to be defined +#endif + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[L_LNNO_SIZE]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ (4 + L_LNNO_SIZE) + +#if L_LNNO_SIZE == 4 +#define GET_LINENO_LNNO(abfd, ext) H_GET_32 (abfd, (ext->l_lnno)) +#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_32 (abfd, val, (ext->l_lnno)) +#endif +#if L_LNNO_SIZE == 2 +#define GET_LINENO_LNNO(abfd, ext) H_GET_16 (abfd, (ext->l_lnno)) +#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_16 (abfd, val, (ext->l_lnno)) +#endif + +#endif /* not DO_NOT_DEFINE_LINENO */ + +#ifndef DO_NOT_DEFINE_SYMENT +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#ifndef E_FILNMLEN +#define E_FILNMLEN 14 +#endif +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +} ATTRIBUTE_PACKED ; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +#ifndef N_BTMASK +#define N_BTMASK 0xf +#endif + +#ifndef N_TMASK +#define N_TMASK 0x30 +#endif + +#ifndef N_BTSHFT +#define N_BTSHFT 4 +#endif + +#ifndef N_TSHIFT +#define N_TSHIFT 2 +#endif + +#endif /* not DO_NOT_DEFINE_SYMENT */ + +#ifndef DO_NOT_DEFINE_AUXENT + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize[4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ +#ifdef INCLUDE_COMDAT_FIELDS_IN_AUXENT + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ +#endif + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +} ATTRIBUTE_PACKED ; + +#define AUXENT union external_auxent +#define AUXESZ 18 + +#define _ETEXT "etext" + +#endif /* not DO_NOT_DEFINE_AUXENT */ + +#endif /* COFF_EXTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/coff/go32exe.h b/external/gpl3/gdb/dist/include/coff/go32exe.h new file mode 100644 index 000000000000..a2ca6cd7e77d --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/go32exe.h @@ -0,0 +1,36 @@ +/* COFF information for PC running go32. + + Copyright 2001, 2005, 2009, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +struct external_filehdr_go32_exe + { + char stub[GO32_STUBSIZE]; /* the stub to load the image */ + /* the standard COFF header */ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + }; + +#undef FILHDR +#define FILHDR struct external_filehdr_go32_exe +#undef FILHSZ +#define FILHSZ GO32_STUBSIZE+20 diff --git a/external/gpl3/gdb/dist/include/coff/h8300.h b/external/gpl3/gdb/dist/include/coff/h8300.h new file mode 100644 index 000000000000..4de6602ee84d --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/h8300.h @@ -0,0 +1,55 @@ +/* coff information for Renesas H8/300 and H8/300-H + + Copyright 2001, 2003, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8300MAGIC 0x8300 +#define H8300HMAGIC 0x8301 +#define H8300SMAGIC 0x8302 +#define H8300HNMAGIC 0x8303 +#define H8300SNMAGIC 0x8304 + +#define H8300BADMAG(x) (((x).f_magic != H8300MAGIC)) +#define H8300HBADMAG(x) (((x).f_magic != H8300HMAGIC)) +#define H8300SBADMAG(x) (((x).f_magic != H8300SMAGIC)) +#define H8300HNBADMAG(x) (((x).f_magic != H8300HNMAGIC)) +#define H8300SNBADMAG(x) (((x).f_magic != H8300SNMAGIC)) + +/* Relocation directives. */ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/external/gpl3/gdb/dist/include/coff/h8500.h b/external/gpl3/gdb/dist/include/coff/h8500.h new file mode 100644 index 000000000000..56097f86e312 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/h8500.h @@ -0,0 +1,47 @@ +/* coff information for Renesas H8/500 + + Copyright 2001, 2003, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8500MAGIC 0x8500 + +#define H8500BADMAG(x) ((0xffff && ((x).f_magic) != H8500MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/external/gpl3/gdb/dist/include/coff/i386.h b/external/gpl3/gdb/dist/include/coff/i386.h new file mode 100644 index 000000000000..61e723ab789b --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/i386.h @@ -0,0 +1,74 @@ +/* coff information for Intel 386/486. + + Copyright 2001, 2009, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define COFF_PAGE_SIZE 0x1000 + +/* Bits for f_flags: + F_RELFLG Relocation info stripped from file + F_EXEC File is executable (no unresolved external references) + F_LNNO Line numbers stripped from file + F_LSYMS Local symbols stripped from file + F_AR32WR File has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +#define I386MAGIC 0x14c +#define I386PTXMAGIC 0x154 +#define I386AIXMAGIC 0x175 + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC 0415 + +#define I386BADMAG(x) ( ((x).f_magic != I386MAGIC) \ + && (x).f_magic != I386AIXMAGIC \ + && (x).f_magic != I386PTXMAGIC \ + && (x).f_magic != LYNXCOFFMAGIC) + +#define OMAGIC 0404 /* Object files, eg as output. */ +#define ZMAGIC 0413 /* Demand load format, eg normal ld output. */ +#define STMAGIC 0401 /* Target shlib. */ +#define SHMAGIC 0443 /* Host shlib. */ + +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/* Relocation directives. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/external/gpl3/gdb/dist/include/coff/i860.h b/external/gpl3/gdb/dist/include/coff/i860.h new file mode 100644 index 000000000000..7de3961b2f08 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/i860.h @@ -0,0 +1,87 @@ +/* COFF information for the Intel i860. + + Copyright 2001, 2003, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file was hacked from i386.h [dolan@ssd.intel.com] */ + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +#define I860MAGIC 0x14d + +#define I860BADMAG(x) ((x).f_magic != I860MAGIC) + +#undef AOUTSZ +#define AOUTSZ 36 + +/* FIXME: What are the a.out magic numbers? */ + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* The relocation directory entry types. + PAIR : The low half that follows relates to the preceeding HIGH[ADJ]. + HIGH : The high half of a 32-bit constant. + LOWn : The low half, insn bits 15..(n-1), 2^n-byte aligned. + SPLITn : The low half, insn bits 20..16 and 10..(n-1), 2^n-byte aligned. + HIGHADJ: Similar to HIGH, but with adjustment. + BRADDR : 26-bit branch displacement. + + Note: The Intel assembler manual lists LOW4 as one of the + relocation types, but it appears to be useless for the i860. + We will recognize it anyway, just in case it actually appears in + any object files. */ + +enum { + COFF860_R_PAIR = 0x1c, + COFF860_R_HIGH = 0x1e, + COFF860_R_LOW0 = 0x1f, + COFF860_R_LOW1 = 0x20, + COFF860_R_LOW2 = 0x21, + COFF860_R_LOW3 = 0x22, + COFF860_R_LOW4 = 0x23, + COFF860_R_SPLIT0 = 0x24, + COFF860_R_SPLIT1 = 0x25, + COFF860_R_SPLIT2 = 0x26, + COFF860_R_HIGHADJ = 0x27, + COFF860_R_BRADDR = 0x28 +}; + diff --git a/external/gpl3/gdb/dist/include/coff/i960.h b/external/gpl3/gdb/dist/include/coff/i960.h new file mode 100644 index 000000000000..2bf42adcf0e7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/i960.h @@ -0,0 +1,320 @@ +/* coff information for 80960. Origins: Intel corp, natch. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* NOTE: Tagentries (cf TAGBITS) are no longer used by the 960 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define OMAGIC (0407) /* old impure format. data immediately + follows text. both sections are rw. */ +#define NMAGIC (0410) /* split i&d, read-only text */ + +/* +* Intel 80960 (I960) processor flags. +* F_I960TYPE == mask for processor type field. +*/ + +#define F_I960TYPE (0xf000) +#define F_I960CORE (0x1000) +#define F_I960KB (0x2000) +#define F_I960SB (0x2000) +#define F_I960MC (0x3000) +#define F_I960XA (0x4000) +#define F_I960CA (0x5000) +#define F_I960KA (0x6000) +#define F_I960SA (0x6000) +#define F_I960JX (0x7000) +#define F_I960HX (0x8000) + + +/** i80960 Magic Numbers +*/ + +#define I960ROMAGIC (0x160) /* read-only text segments */ +#define I960RWMAGIC (0x161) /* read-write text segments */ + +#define I960BADMAG(x) (((x).f_magic!=I960ROMAGIC) && ((x).f_magic!=I960RWMAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + unsigned long phys_addr; + unsigned long bitarray; +} TAGBITS; + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char tagentries[4]; /* number of tag entries to follow */ +} +AOUTHDR; + +/* return a pointer to the tag bits array */ + +#define TAGPTR(aout) ((TAGBITS *) (&(aout.tagentries)+1)) + +/* compute size of a header */ + +/*#define AOUTSZ(aout) (sizeof(AOUTHDR)+(aout.tagentries*sizeof(TAGBITS)))*/ +#define AOUTSZ 32 +#define AOUTHDRSZ 32 + + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_align[4]; /* section alignment */ +}; + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[2]; /* line number */ + char padding[2]; /* force alignment */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 8 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + + char e_value[4]; + char e_scnum[2]; + char e_flags[2]; + char e_type[4]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK (0x1f) +#define N_TMASK (0x60) +#define N_BTSHFT (5) +#define N_TSHIFT (2) + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize[4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + /****************************************** + * I960-specific *2nd* aux. entry formats + ******************************************/ + struct + { + /* This is a very old typo that keeps getting propagated. */ +#define x_stdindx x_stindx + char x_stindx[4]; /* sys. table entry */ + } x_sc; /* system call entry */ + + struct + { + char x_balntry[4]; /* BAL entry point */ + } x_bal; /* BAL-callable function */ + + struct + { + char x_timestamp[4]; /* time stamp */ + char x_idstring[20]; /* producer identity string */ + + } x_ident; /* Producer ident info */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 24 +#define AUXENT union external_auxent +#define AUXESZ 24 + +# define _ETEXT "_etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char pad[2]; +}; + +/* r_type values for the i960. */ + +/* The i960 uses R_RELLONG, which is defined in internal.h as 0x11. + It is an absolute 32 bit relocation. */ + +#define R_IPRMED (0x19) /* 24-bit ip-relative relocation */ +#define R_OPTCALL (0x1b) /* 32-bit optimizable call (leafproc/sysproc) */ +#define R_OPTCALLX (0x1c) /* 64-bit optimizable call (leafproc/sysproc) */ + +/* The following relocation types are defined use by relaxing linkers, + which convert 32 bit calls (which require a 64 bit instruction) + into 24 bit calls (which require a 32 bit instruction) when + possible. It will be possible whenever the target of the call is + within a 24 bit range of the call instruction. + + It is always safe to ignore these relocations. They only serve to + mark points which the relaxing linker will have to consider. The + assembler must ensure that the correct code is generated even if + the relocations are ignored. In particular, this means that the + R_IPR13 relocation may not appear with an external symbol. */ + +#define R_IPR13 (0x1d) /* 13 bit ip-relative branch */ +#define R_ALIGN (0x1e) /* alignment marker. This has no + associated symbol. Instead, the + r_symndx field indicates the + require alignment at this point in + the file. It must be a power of 2. */ + +#define RELOC struct external_reloc +#define RELSZ 12 + diff --git a/external/gpl3/gdb/dist/include/coff/ia64.h b/external/gpl3/gdb/dist/include/coff/ia64.h new file mode 100644 index 000000000000..2ee626863e22 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/ia64.h @@ -0,0 +1,89 @@ +/* coff information for HP/Intel IA-64. + + Copyright 2000, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define IA64MAGIC 0x200 + +#define IA64BADMAG(x) (((x).f_magic != IA64MAGIC)) + +/* Bits for f_flags: + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (no unresolved external references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +/********************** AOUT "OPTIONAL HEADER" **********************/ +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ +#ifndef BFD64 + char data_start[4]; /* base of data used for this file */ +#endif +} +AOUTHDR; + +#define PE32MAGIC 0x10b /* 32-bit image */ +#define PE32PMAGIC 0x20b /* 32-bit image inside 64-bit address space */ + +#define PE32PBADMAG(x) (((x).f_magic != PE32PMAGIC)) + +#define AOUTSZ 108 +#define AOUTHDRSZ 108 + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/external/gpl3/gdb/dist/include/coff/internal.h b/external/gpl3/gdb/dist/include/coff/internal.h new file mode 100644 index 000000000000..f52bfbb7ba97 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/internal.h @@ -0,0 +1,828 @@ +/* Internal format of COFF object file data structures, for GNU BFD. + This file is part of BFD, the Binary File Descriptor library. + + Copyright 1999, 2000, 2001, 2002, 2003, 2004. 2005, 2006, 2007, 2009, + 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef GNU_COFF_INTERNAL_H +#define GNU_COFF_INTERNAL_H 1 + +/* First, make "signed char" work, even on old compilers. */ +#ifndef signed +#ifndef __STDC__ +#define signed /**/ +#endif +#endif + +/********************** FILE HEADER **********************/ + +/* extra stuff in a PE header. */ + +struct internal_extra_pe_filehdr +{ + /* DOS header data follows for PE stuff */ + unsigned short e_magic; /* Magic number, 0x5a4d */ + unsigned short e_cblp; /* Bytes on last page of file, 0x90 */ + unsigned short e_cp; /* Pages in file, 0x3 */ + unsigned short e_crlc; /* Relocations, 0x0 */ + unsigned short e_cparhdr; /* Size of header in paragraphs, 0x4 */ + unsigned short e_minalloc; /* Minimum extra paragraphs needed, 0x0 */ + unsigned short e_maxalloc; /* Maximum extra paragraphs needed, 0xFFFF */ + unsigned short e_ss; /* Initial (relative) SS value, 0x0 */ + unsigned short e_sp; /* Initial SP value, 0xb8 */ + unsigned short e_csum; /* Checksum, 0x0 */ + unsigned short e_ip; /* Initial IP value, 0x0 */ + unsigned short e_cs; /* Initial (relative) CS value, 0x0 */ + unsigned short e_lfarlc; /* File address of relocation table, 0x40 */ + unsigned short e_ovno; /* Overlay number, 0x0 */ + unsigned short e_res[4]; /* Reserved words, all 0x0 */ + unsigned short e_oemid; /* OEM identifier (for e_oeminfo), 0x0 */ + unsigned short e_oeminfo; /* OEM information; e_oemid specific, 0x0 */ + unsigned short e_res2[10]; /* Reserved words, all 0x0 */ + bfd_vma e_lfanew; /* File address of new exe header, 0x80 */ + unsigned long dos_message[16]; /* text which always follows dos header */ + bfd_vma nt_signature; /* required NT signature, 0x4550 */ +}; + +#define GO32_STUBSIZE 2048 + +struct internal_filehdr +{ + struct internal_extra_pe_filehdr pe; + + /* coff-stgo32 EXE stub header before BFD tdata has been allocated. + Its data is kept in INTERNAL_FILEHDR.GO32STUB afterwards. + + F_GO32STUB is set iff go32stub contains a valid data. Artifical headers + created in BFD have no pre-set go32stub. */ + char go32stub[GO32_STUBSIZE]; + + /* Standard coff internal info. */ + unsigned short f_magic; /* magic number */ + unsigned short f_nscns; /* number of sections */ + long f_timdat; /* time & date stamp */ + bfd_vma f_symptr; /* file pointer to symtab */ + long f_nsyms; /* number of symtab entries */ + unsigned short f_opthdr; /* sizeof(optional hdr) */ + unsigned short f_flags; /* flags */ + unsigned short f_target_id; /* (TI COFF specific) */ +}; + + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR16WR file is 16-bit little-endian + F_AR32WR file is 32-bit little-endian + F_AR32W file is 32-bit big-endian + F_DYNLOAD rs/6000 aix: dynamically loadable w/imports & exports + F_SHROBJ rs/6000 aix: file is a shared object + F_DLL PE format DLL + F_GO32STUB Field go32stub contains valid data. */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_AR16WR (0x0080) +#define F_AR32WR (0x0100) +#define F_AR32W (0x0200) +#define F_DYNLOAD (0x1000) +#define F_SHROBJ (0x2000) +#define F_DLL (0x2000) +#define F_GO32STUB (0x4000) + +/* Extra structure which is used in the optional header. */ +typedef struct _IMAGE_DATA_DIRECTORY +{ + bfd_vma VirtualAddress; + long Size; +} IMAGE_DATA_DIRECTORY; +#define PE_EXPORT_TABLE 0 +#define PE_IMPORT_TABLE 1 +#define PE_RESOURCE_TABLE 2 +#define PE_EXCEPTION_TABLE 3 +#define PE_CERTIFICATE_TABLE 4 +#define PE_BASE_RELOCATION_TABLE 5 +#define PE_DEBUG_DATA 6 +#define PE_ARCHITECTURE 7 +#define PE_GLOBAL_PTR 8 +#define PE_TLS_TABLE 9 +#define PE_LOAD_CONFIG_TABLE 10 +#define PE_BOUND_IMPORT_TABLE 11 +#define PE_IMPORT_ADDRESS_TABLE 12 +#define PE_DELAY_IMPORT_DESCRIPTOR 13 +#define PE_CLR_RUNTIME_HEADER 14 +/* DataDirectory[15] is currently reserved, so no define. */ +#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16 + +/* Default image base for NT. */ +#define NT_EXE_IMAGE_BASE 0x400000 +#define NT_DLL_IMAGE_BASE 0x10000000 + +/* Default image base for BeOS. */ +#define BEOS_EXE_IMAGE_BASE 0x80000000 +#define BEOS_DLL_IMAGE_BASE 0x10000000 + +/* Extra stuff in a PE aouthdr */ + +#define PE_DEF_SECTION_ALIGNMENT 0x1000 +#ifndef PE_DEF_FILE_ALIGNMENT +# define PE_DEF_FILE_ALIGNMENT 0x200 +#endif + +struct internal_extra_pe_aouthdr +{ + /* FIXME: The following entries are in AOUTHDR. But they aren't + available internally in bfd. We add them here so that objdump + can dump them. */ + /* The state of the image file */ + short Magic; + /* Linker major version number */ + char MajorLinkerVersion; + /* Linker minor version number */ + char MinorLinkerVersion; + /* Total size of all code sections */ + long SizeOfCode; + /* Total size of all initialized data sections */ + long SizeOfInitializedData; + /* Total size of all uninitialized data sections */ + long SizeOfUninitializedData; + /* Address of entry point relative to image base. */ + bfd_vma AddressOfEntryPoint; + /* Address of the first code section relative to image base. */ + bfd_vma BaseOfCode; + /* Address of the first data section relative to image base. */ + bfd_vma BaseOfData; + + /* PE stuff */ + bfd_vma ImageBase; /* address of specific location in memory that + file is located, NT default 0x10000 */ + + bfd_vma SectionAlignment; /* section alignment default 0x1000 */ + bfd_vma FileAlignment; /* file alignment default 0x200 */ + short MajorOperatingSystemVersion; /* minimum version of the operating */ + short MinorOperatingSystemVersion; /* system req'd for exe, default to 1*/ + short MajorImageVersion; /* user defineable field to store version of */ + short MinorImageVersion; /* exe or dll being created, default to 0 */ + short MajorSubsystemVersion; /* minimum subsystem version required to */ + short MinorSubsystemVersion; /* run exe; default to 3.1 */ + long Reserved1; /* seems to be 0 */ + long SizeOfImage; /* size of memory to allocate for prog */ + long SizeOfHeaders; /* size of PE header and section table */ + long CheckSum; /* set to 0 */ + short Subsystem; + + /* type of subsystem exe uses for user interface, + possible values: + 1 - NATIVE Doesn't require a subsystem + 2 - WINDOWS_GUI runs in Windows GUI subsystem + 3 - WINDOWS_CUI runs in Windows char sub. (console app) + 5 - OS2_CUI runs in OS/2 character subsystem + 7 - POSIX_CUI runs in Posix character subsystem */ + unsigned short DllCharacteristics; /* flags for DLL init */ + bfd_vma SizeOfStackReserve; /* amount of memory to reserve */ + bfd_vma SizeOfStackCommit; /* amount of memory initially committed for + initial thread's stack, default is 0x1000 */ + bfd_vma SizeOfHeapReserve; /* amount of virtual memory to reserve and */ + bfd_vma SizeOfHeapCommit; /* commit, don't know what to defaut it to */ + long LoaderFlags; /* can probably set to 0 */ + long NumberOfRvaAndSizes; /* number of entries in next entry, 16 */ + IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; +}; + +/********************** AOUT "OPTIONAL HEADER" **********************/ +struct internal_aouthdr +{ + short magic; /* type of file */ + short vstamp; /* version stamp */ + bfd_vma tsize; /* text size in bytes, padded to FW bdry*/ + bfd_vma dsize; /* initialized data " " */ + bfd_vma bsize; /* uninitialized data " " */ + bfd_vma entry; /* entry pt. */ + bfd_vma text_start; /* base of text used for this file */ + bfd_vma data_start; /* base of data used for this file */ + + /* i960 stuff */ + unsigned long tagentries; /* number of tag entries to follow */ + + /* RS/6000 stuff */ + bfd_vma o_toc; /* address of TOC */ + short o_snentry; /* section number for entry point */ + short o_sntext; /* section number for text */ + short o_sndata; /* section number for data */ + short o_sntoc; /* section number for toc */ + short o_snloader; /* section number for loader section */ + short o_snbss; /* section number for bss */ + short o_algntext; /* max alignment for text */ + short o_algndata; /* max alignment for data */ + short o_modtype; /* Module type field, 1R,RE,RO */ + short o_cputype; /* Encoded CPU type */ + bfd_vma o_maxstack; /* max stack size allowed. */ + bfd_vma o_maxdata; /* max data size allowed. */ + + /* ECOFF stuff */ + bfd_vma bss_start; /* Base of bss section. */ + bfd_vma gp_value; /* GP register value. */ + unsigned long gprmask; /* General registers used. */ + unsigned long cprmask[4]; /* Coprocessor registers used. */ + unsigned long fprmask; /* Floating pointer registers used. */ + + /* Apollo stuff */ + long o_inlib; /* inlib data */ + long o_sri; /* Static Resource Information */ + long vid[2]; /* Version id */ + + struct internal_extra_pe_aouthdr pe; +}; + +/********************** STORAGE CLASSES **********************/ + +/* This used to be defined as -1, but now n_sclass is unsigned. */ +#define C_EFCN 0xff /* physical end of function */ +#define C_NULL 0 +#define C_AUTO 1 /* automatic variable */ +#define C_EXT 2 /* external symbol */ +#define C_STAT 3 /* static */ +#define C_REG 4 /* register variable */ +#define C_EXTDEF 5 /* external definition */ +#define C_LABEL 6 /* label */ +#define C_ULABEL 7 /* undefined label */ +#define C_MOS 8 /* member of structure */ +#define C_ARG 9 /* function argument */ +#define C_STRTAG 10 /* structure tag */ +#define C_MOU 11 /* member of union */ +#define C_UNTAG 12 /* union tag */ +#define C_TPDEF 13 /* type definition */ +#define C_USTATIC 14 /* undefined static */ +#define C_ENTAG 15 /* enumeration tag */ +#define C_MOE 16 /* member of enumeration */ +#define C_REGPARM 17 /* register parameter */ +#define C_FIELD 18 /* bit field */ +#define C_AUTOARG 19 /* auto argument */ +#define C_LASTENT 20 /* dummy entry (end of block) */ +#define C_BLOCK 100 /* ".bb" or ".eb" */ +#define C_FCN 101 /* ".bf" or ".ef" */ +#define C_EOS 102 /* end of structure */ +#define C_FILE 103 /* file name */ +#define C_LINE 104 /* line # reformatted as symbol table entry */ +#define C_ALIAS 105 /* duplicate tag */ +#define C_HIDDEN 106 /* ext symbol in dmert public lib */ +#define C_WEAKEXT 127 /* weak symbol -- GNU extension. */ + +/* New storage classes for TI COFF */ +#define C_UEXT 19 /* Tentative external definition */ +#define C_STATLAB 20 /* Static load time label */ +#define C_EXTLAB 21 /* External load time label */ +#define C_SYSTEM 23 /* System Wide variable */ + +/* New storage classes for WINDOWS_NT */ +#define C_SECTION 104 /* section name */ +#define C_NT_WEAK 105 /* weak external */ + + /* New storage classes for 80960 */ + +/* C_LEAFPROC is obsolete. Use C_LEAFEXT or C_LEAFSTAT */ +#define C_LEAFPROC 108 /* Leaf procedure, "call" via BAL */ + +#define C_SCALL 107 /* Procedure reachable via system call */ +#define C_LEAFEXT 108 /* External leaf */ +#define C_LEAFSTAT 113 /* Static leaf */ +#define C_OPTVAR 109 /* Optimized variable */ +#define C_DEFINE 110 /* Preprocessor #define */ +#define C_PRAGMA 111 /* Advice to compiler or linker */ +#define C_SEGMENT 112 /* 80960 segment name */ + + /* Storage classes for m88k */ +#define C_SHADOW 107 /* shadow symbol */ +#define C_VERSION 108 /* coff version symbol */ + + /* New storage classes for RS/6000 */ +#define C_HIDEXT 107 /* Un-named external symbol */ +#define C_BINCL 108 /* Marks beginning of include file */ +#define C_EINCL 109 /* Marks ending of include file */ +#define C_AIX_WEAKEXT 111 /* AIX definition of C_WEAKEXT. */ + +#define C_NULL_VALUE 0x00de1e00 /* Value for a C_NULL deleted entry. */ + +#if defined _AIX52 || defined AIX_WEAK_SUPPORT +#undef C_WEAKEXT +#define C_WEAKEXT C_AIX_WEAKEXT +#endif + + /* storage classes for stab symbols for RS/6000 */ +#define C_GSYM (0x80) +#define C_LSYM (0x81) +#define C_PSYM (0x82) +#define C_RSYM (0x83) +#define C_RPSYM (0x84) +#define C_STSYM (0x85) +#define C_TCSYM (0x86) +#define C_BCOMM (0x87) +#define C_ECOML (0x88) +#define C_ECOMM (0x89) +#define C_DECL (0x8c) +#define C_ENTRY (0x8d) +#define C_FUN (0x8e) +#define C_BSTAT (0x8f) +#define C_ESTAT (0x90) + +/* Storage classes for Thumb symbols */ +#define C_THUMBEXT (128 + C_EXT) /* 130 */ +#define C_THUMBSTAT (128 + C_STAT) /* 131 */ +#define C_THUMBLABEL (128 + C_LABEL) /* 134 */ +#define C_THUMBEXTFUNC (C_THUMBEXT + 20) /* 150 */ +#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) /* 151 */ + +/* True if XCOFF symbols of class CLASS have auxillary csect information. */ +#define CSECT_SYM_P(CLASS) \ + ((CLASS) == C_EXT || (CLASS) == C_AIX_WEAKEXT || (CLASS) == C_HIDEXT) + +/********************** SECTION HEADER **********************/ + +#define SCNNMLEN (8) + +struct internal_scnhdr +{ + char s_name[SCNNMLEN]; /* section name */ + + /* Physical address, aliased s_nlib. + In the pei format, this field is the virtual section size + (the size of the section after being loaded int memory), + NOT the physical address. */ + bfd_vma s_paddr; + + bfd_vma s_vaddr; /* virtual address */ + bfd_vma s_size; /* section size */ + bfd_vma s_scnptr; /* file ptr to raw data for section */ + bfd_vma s_relptr; /* file ptr to relocation */ + bfd_vma s_lnnoptr; /* file ptr to line numbers */ + unsigned long s_nreloc; /* number of relocation entries */ + unsigned long s_nlnno; /* number of line number entries*/ + long s_flags; /* flags */ + long s_align; /* used on I960 */ + unsigned char s_page; /* TI COFF load page */ +}; + +/* s_flags "type". */ +#define STYP_REG (0x0000) /* "regular": allocated, relocated, loaded */ +#define STYP_DSECT (0x0001) /* "dummy": relocated only*/ +#define STYP_NOLOAD (0x0002) /* "noload": allocated, relocated, not loaded */ +#define STYP_GROUP (0x0004) /* "grouped": formed of input sections */ +#define STYP_PAD (0x0008) /* "padding": not allocated, not relocated, loaded */ +#define STYP_COPY (0x0010) /* "copy": for decision function used by field update; not allocated, not relocated, + loaded; reloc & lineno entries processed normally */ +#define STYP_TEXT (0x0020) /* section contains text only */ +#define S_SHRSEG (0x0020) /* In 3b Update files (output of ogen), sections which appear in SHARED segments of the Pfile + will have the S_SHRSEG flag set by ogen, to inform dufr that updating 1 copy of the proc. will + update all process invocations. */ +#define STYP_DATA (0x0040) /* section contains data only */ +#define STYP_BSS (0x0080) /* section contains bss only */ +#define S_NEWFCN (0x0100) /* In a minimal file or an update file, a new function (as compared with a replaced function) */ +#define STYP_INFO (0x0200) /* comment: not allocated not relocated, not loaded */ +#define STYP_OVER (0x0400) /* overlay: relocated not allocated or loaded */ +#define STYP_LIB (0x0800) /* for .lib: same as INFO */ +#define STYP_MERGE (0x2000) /* merge section -- combines with text, data or bss sections only */ +#define STYP_REVERSE_PAD (0x4000) /* section will be padded with no-op instructions + wherever padding is necessary and there is a + word of contiguous bytes beginning on a word + boundary. */ + +#define STYP_LIT 0x8020 /* Literal data (like STYP_TEXT) */ + + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ + +struct internal_lineno +{ + union + { + bfd_signed_vma l_symndx; /* function name symbol index, iff l_lnno == 0*/ + bfd_signed_vma l_paddr; /* (physical) address of line number */ + } l_addr; + unsigned long l_lnno; /* line number */ +}; + +/********************** SYMBOLS **********************/ + +#define SYMNMLEN 8 /* # characters in a symbol name */ +#define FILNMLEN 14 /* # characters in a file name */ +#define DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct internal_syment +{ + union + { + char _n_name[SYMNMLEN]; /* old COFF version */ + struct + { + bfd_hostptr_t _n_zeroes; /* new == 0 */ + bfd_hostptr_t _n_offset; /* offset into string table */ + } _n_n; + char *_n_nptr[2]; /* allows for overlaying */ + } _n; + bfd_vma n_value; /* value of symbol */ + short n_scnum; /* section number */ + unsigned short n_flags; /* copy of flags from filhdr */ + unsigned short n_type; /* type and derived type */ + unsigned char n_sclass; /* storage class */ + unsigned char n_numaux; /* number of aux. entries */ +}; + +#define n_name _n._n_name +#define n_zeroes _n._n_n._n_zeroes +#define n_offset _n._n_n._n_offset + +/* Relocatable symbols have number of the section in which they are defined, + or one of the following: */ + +#define N_UNDEF ((short)0) /* undefined symbol */ +#define N_ABS ((short)-1) /* value of symbol is absolute */ +#define N_DEBUG ((short)-2) /* debugging symbol -- value is meaningless */ +#define N_TV ((short)-3) /* indicates symbol needs preload transfer vector */ +#define P_TV ((short)-4) /* indicates symbol needs postload transfer vector*/ + +/* Type of a symbol, in low N bits of the word. */ + +#define T_NULL 0 +#define T_VOID 1 /* function argument (only used by compiler) */ +#define T_CHAR 2 /* character */ +#define T_SHORT 3 /* short integer */ +#define T_INT 4 /* integer */ +#define T_LONG 5 /* long integer */ +#define T_FLOAT 6 /* floating point */ +#define T_DOUBLE 7 /* double word */ +#define T_STRUCT 8 /* structure */ +#define T_UNION 9 /* union */ +#define T_ENUM 10 /* enumeration */ +#define T_MOE 11 /* member of enumeration*/ +#define T_UCHAR 12 /* unsigned character */ +#define T_USHORT 13 /* unsigned short */ +#define T_UINT 14 /* unsigned integer */ +#define T_ULONG 15 /* unsigned long */ +#define T_LNGDBL 16 /* long double */ + +/* Derived types, in n_type. */ + +#define DT_NON (0) /* no derived type */ +#define DT_PTR (1) /* pointer */ +#define DT_FCN (2) /* function */ +#define DT_ARY (3) /* array */ + +#define BTYPE(x) ((x) & N_BTMASK) +#define DTYPE(x) (((x) & N_TMASK) >> N_BTSHFT) + +#define ISPTR(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT)) +#define ISFCN(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_FCN << N_BTSHFT)) +#define ISARY(x) \ + (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_ARY << N_BTSHFT)) +#define ISTAG(x) \ + ((x) == C_STRTAG || (x) == C_UNTAG || (x) == C_ENTAG) +#define DECREF(x) \ + ((((x) >> N_TSHIFT) & ~ N_BTMASK) | ((x) & N_BTMASK)) + +union internal_auxent +{ + struct + { + + union + { + long l; /* str, un, or enum tag indx */ + struct coff_ptr_struct *p; + } x_tagndx; + + union + { + struct + { + unsigned short x_lnno; /* declaration line number */ + unsigned short x_size; /* str/union/array size */ + } x_lnsz; + long x_fsize; /* size of function */ + } x_misc; + + union + { + struct + { /* if ISFCN, tag, or .bb */ + bfd_signed_vma x_lnnoptr; /* ptr to fcn line # */ + union + { /* entry ndx past block end */ + long l; + struct coff_ptr_struct *p; + } x_endndx; + } x_fcn; + + struct + { /* if ISARY, up to 4 dimen. */ + unsigned short x_dimen[DIMNUM]; + } x_ary; + } x_fcnary; + + unsigned short x_tvndx; /* tv index */ + } x_sym; + + union + { + char x_fname[FILNMLEN]; + struct + { + long x_zeroes; + long x_offset; + } x_n; + } x_file; + + struct + { + long x_scnlen; /* section length */ + unsigned short x_nreloc; /* # relocation entries */ + unsigned short x_nlinno; /* # line numbers */ + unsigned long x_checksum; /* section COMDAT checksum for PE */ + unsigned short x_associated; /* COMDAT associated section index for PE */ + unsigned char x_comdat; /* COMDAT selection number for PE */ + } x_scn; + + struct + { + long x_tvfill; /* tv fill value */ + unsigned short x_tvlen; /* length of .tv */ + unsigned short x_tvran[2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + /****************************************** + * RS/6000-specific auxent - last auxent for every external symbol + ******************************************/ + struct + { + union + { /* csect length or enclosing csect */ + bfd_signed_vma l; + struct coff_ptr_struct *p; + } x_scnlen; + long x_parmhash; /* parm type hash index */ + unsigned short x_snhash; /* sect num with parm hash */ + unsigned char x_smtyp; /* symbol align and type */ + /* 0-4 - Log 2 of alignment */ + /* 5-7 - symbol type */ + unsigned char x_smclas; /* storage mapping class */ + long x_stab; /* dbx stab info index */ + unsigned short x_snstab; /* sect num with dbx stab */ + } x_csect; /* csect definition information */ + +/* x_smtyp values: */ + +#define SMTYP_ALIGN(x) ((x) >> 3) /* log2 of alignment */ +#define SMTYP_SMTYP(x) ((x) & 0x7) /* symbol type */ +/* Symbol type values: */ +#define XTY_ER 0 /* External reference */ +#define XTY_SD 1 /* Csect definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* .BSS */ +#define XTY_EM 4 /* Error message */ +#define XTY_US 5 /* "Reserved for internal use" */ + +/* x_smclas values: */ + +#define XMC_PR 0 /* Read-only program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Read-only debug dictionary table */ +#define XMC_TC 3 /* Read-write general TOC entry */ +#define XMC_UA 4 /* Read-write unclassified */ +#define XMC_RW 5 /* Read-write data */ +#define XMC_GL 6 /* Read-only global linkage */ +#define XMC_XO 7 /* Read-only extended operation */ +#define XMC_SV 8 /* Read-only supervisor call */ +#define XMC_BS 9 /* Read-write BSS */ +#define XMC_DS 10 /* Read-write descriptor csect */ +#define XMC_UC 11 /* Read-write unnamed Fortran common */ +#define XMC_TI 12 /* Read-only traceback index csect */ +#define XMC_TB 13 /* Read-only traceback table csect */ +/* 14 ??? */ +#define XMC_TC0 15 /* Read-write TOC anchor */ +#define XMC_TD 16 /* Read-write data in TOC */ + + /****************************************** + * I960-specific *2nd* aux. entry formats + ******************************************/ + struct + { + /* This is a very old typo that keeps getting propagated. */ +#define x_stdindx x_stindx + long x_stindx; /* sys. table entry */ + } x_sc; /* system call entry */ + + struct + { + unsigned long x_balntry; /* BAL entry point */ + } x_bal; /* BAL-callable function */ + + struct + { + unsigned long x_timestamp; /* time stamp */ + char x_idstring[20]; /* producer identity string */ + } x_ident; /* Producer ident info */ + +}; + +/********************** RELOCATION DIRECTIVES **********************/ + +struct internal_reloc +{ + bfd_vma r_vaddr; /* Virtual address of reference */ + long r_symndx; /* Index into symbol table */ + unsigned short r_type; /* Relocation type */ + unsigned char r_size; /* Used by RS/6000 and ECOFF */ + unsigned char r_extern; /* Used by ECOFF */ + unsigned long r_offset; /* Used by Alpha ECOFF, SPARC, others */ +}; + +/* X86-64 relocations. */ +#define R_AMD64_ABS 0 /* Reference is absolute, no relocation is necessary. */ +#define R_AMD64_DIR64 1 /* 64-bit address (VA). */ +#define R_AMD64_DIR32 2 /* 32-bit address (VA) R_DIR32. */ +#define R_AMD64_IMAGEBASE 3 /* 32-bit absolute ref w/o base R_IMAGEBASE. */ +#define R_AMD64_PCRLONG 4 /* 32-bit relative address from byte following reloc R_PCRLONG. */ +#define R_AMD64_PCRLONG_1 5 /* 32-bit relative address from byte distance 1 from reloc. */ +#define R_AMD64_PCRLONG_2 6 /* 32-bit relative address from byte distance 2 from reloc. */ +#define R_AMD64_PCRLONG_3 7 /* 32-bit relative address from byte distance 3 from reloc. */ +#define R_AMD64_PCRLONG_4 8 /* 32-bit relative address from byte distance 4 from reloc. */ +#define R_AMD64_PCRLONG_5 9 /* 32-bit relative address from byte distance 5 from reloc. */ +#define R_AMD64_SECTION 10 /* Section index. */ +#define R_AMD64_SECREL 11 /* 32 bit offset from base of section containing target R_SECREL. */ +#define R_AMD64_SECREL7 12 /* 7 bit unsigned offset from base of section containing target. */ +#define R_AMD64_TOKEN 13 /* 32 bit metadata token. */ +#define R_AMD64_PCRQUAD 14 /* Pseude PC64 relocation - Note: not specified by MS/AMD but need for gas pc-relative 64bit wide relocation generated by ELF. */ + +/* i386 Relocations. */ + +#define R_DIR16 1 +#define R_REL24 5 +#define R_DIR32 6 +#define R_IMAGEBASE 7 +#define R_SECREL32 11 +#define R_RELBYTE 15 +#define R_RELWORD 16 +#define R_RELLONG 17 +#define R_PCRBYTE 18 +#define R_PCRWORD 19 +#define R_PCRLONG 20 +#define R_PCR24 21 +#define R_IPRSHORT 24 +#define R_IPRLONG 26 +#define R_GETSEG 29 +#define R_GETPA 30 +#define R_TAGWORD 31 +#define R_JUMPTARG 32 /* strange 29k 00xx00xx reloc */ +#define R_PARTLS16 32 +#define R_PARTMS8 33 + +#define R_PCR16L 128 +#define R_PCR26L 129 +#define R_VRT16 130 +#define R_HVRT16 131 +#define R_LVRT16 132 +#define R_VRT32 133 + + +/* This reloc identifies mov.b instructions with a 16bit absolute + address. The linker tries to turn insns with this reloc into + an absolute 8-bit address. */ +#define R_MOV16B1 0x41 + +/* This reloc identifies mov.b instructions which had a 16bit + absolute address which have been shortened into a 8-bit + absolute address. */ +#define R_MOV16B2 0x42 + +/* This reloc identifies jmp insns with a 16bit target address; + the linker tries to turn these insns into bra insns with + an 8bit pc-relative target. */ +#define R_JMP1 0x43 + +/* This reloc identifies a bra with an 8-bit pc-relative + target that was formerly a jmp insn with a 16bit target. */ +#define R_JMP2 0x44 + +/* ??? */ +#define R_RELLONG_NEG 0x45 + +/* This reloc identifies jmp insns with a 24bit target address; + the linker tries to turn these insns into bra insns with + an 8bit pc-relative target. */ +#define R_JMPL1 0x46 + +/* This reloc identifies a bra with an 8-bit pc-relative + target that was formerly a jmp insn with a 24bit target. */ +#define R_JMPL2 0x47 + +/* This reloc identifies mov.b instructions with a 24bit absolute + address. The linker tries to turn insns with this reloc into + an absolute 8-bit address. */ + +#define R_MOV24B1 0x48 + +/* This reloc identifies mov.b instructions which had a 24bit + absolute address which have been shortened into a 8-bit + absolute address. */ +#define R_MOV24B2 0x49 + +/* An h8300 memory indirect jump/call. Forces the address of the jump/call + target into the function vector (in page zero), and the address of the + vector entry to be placed in the jump/call instruction. */ +#define R_MEM_INDIRECT 0x4a + +/* This reloc identifies a 16bit pc-relative branch target which was + shortened into an 8bit pc-relative branch target. */ +#define R_PCRWORD_B 0x4b + +/* This reloc identifies mov.[wl] instructions with a 32/24 bit + absolute address; the linker may turn this into a mov.[wl] + insn with a 16bit absolute address. */ +#define R_MOVL1 0x4c + +/* This reloc identifies mov.[wl] insns which formerly had + a 32/24bit absolute address and now have a 16bit absolute address. */ +#define R_MOVL2 0x4d + +/* This reloc identifies a bCC:8 which will have it's condition + inverted and its target redirected to the target of the branch + in the following insn. */ +#define R_BCC_INV 0x4e + +/* This reloc identifies a jmp instruction that has been deleted. */ +#define R_JMP_DEL 0x4f + +/* Z8k modes */ +#define R_IMM16 0x01 /* 16 bit abs */ +#define R_JR 0x02 /* jr 8 bit disp */ +#define R_IMM4L 0x23 /* low nibble */ +#define R_IMM8 0x22 /* 8 bit abs */ +#define R_IMM32 R_RELLONG /* 32 bit abs */ +#define R_CALL R_DA /* Absolute address which could be a callr */ +#define R_JP R_DA /* Absolute address which could be a jp */ +#define R_REL16 0x04 /* 16 bit PC rel */ +#define R_CALLR 0x05 /* callr 12 bit disp */ +#define R_SEG 0x10 /* set if in segmented mode */ +#define R_IMM4H 0x24 /* high nibble */ +#define R_DISP7 0x25 /* djnz displacement */ + +/* Z80 modes */ +#define R_OFF8 0x32 /* 8 bit signed abs, for (i[xy]+d) */ +#define R_IMM24 0x33 /* 24 bit abs */ +/* R_JR, R_IMM8, R_IMM16, R_IMM32 - as for Z8k */ + +/* H8500 modes */ + +#define R_H8500_IMM8 1 /* 8 bit immediate */ +#define R_H8500_IMM16 2 /* 16 bit immediate */ +#define R_H8500_PCREL8 3 /* 8 bit pcrel */ +#define R_H8500_PCREL16 4 /* 16 bit pcrel */ +#define R_H8500_HIGH8 5 /* high 8 bits of 24 bit address */ +#define R_H8500_LOW16 7 /* low 16 bits of 24 bit immediate */ +#define R_H8500_IMM24 6 /* 24 bit immediate */ +#define R_H8500_IMM32 8 /* 32 bit immediate */ +#define R_H8500_HIGH16 9 /* high 16 bits of 32 bit immediate */ + +/* W65 modes */ + +#define R_W65_ABS8 1 /* addr & 0xff */ +#define R_W65_ABS16 2 /* addr & 0xffff */ +#define R_W65_ABS24 3 /* addr & 0xffffff */ + +#define R_W65_ABS8S8 4 /* (addr >> 8) & 0xff */ +#define R_W65_ABS8S16 5 /* (addr >> 16) & 0xff */ + +#define R_W65_ABS16S8 6 /* (addr >> 8) & 0ffff */ +#define R_W65_ABS16S16 7 /* (addr >> 16) & 0ffff */ + +#define R_W65_PCR8 8 +#define R_W65_PCR16 9 + +#define R_W65_DP 10 /* direct page 8 bits only */ + +#endif /* GNU_COFF_INTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/coff/m68k.h b/external/gpl3/gdb/dist/include/coff/m68k.h new file mode 100644 index 000000000000..c00c5a941662 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/m68k.h @@ -0,0 +1,82 @@ +/* coff information for M68K + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef GNU_COFF_M68K_H +#define GNU_COFF_M68K_H 1 + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* This is the magic of the Bull dpx/2 */ +#define MC68KBCSMAGIC 0526 + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC 0415 + +#define OMAGIC M68MAGIC + +/* This intentionally does not include MC68KBCSMAGIC; it only includes + magic numbers which imply that names do not have underscores. */ +#define M68KBADMAG(x) (((x).f_magic != MC68MAGIC) \ + && ((x).f_magic != MC68KWRMAGIC) \ + && ((x).f_magic != MC68TVMAGIC) \ + && ((x).f_magic != MC68KROMAGIC) \ + && ((x).f_magic != MC68KPGMAGIC) \ + && ((x).f_magic != M68MAGIC) \ + && ((x).f_magic != M68TVMAGIC) \ + && ((x).f_magic != LYNXCOFFMAGIC)) + +/* Magic numbers for the a.out header. */ + +#define PAGEMAGICEXECSWAPPED 0407 /* executable (swapped) */ +#define PAGEMAGICPEXECSWAPPED 0410 /* pure executable (swapped) */ +#define PAGEMAGICPEXECTSHLIB 0443 /* pure executable (target shared library) */ +#define PAGEMAGICPEXECPAGED 0413 /* pure executable (paged) */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +#endif /* GNU_COFF_M68K_H */ diff --git a/external/gpl3/gdb/dist/include/coff/m88k.h b/external/gpl3/gdb/dist/include/coff/m88k.h new file mode 100644 index 000000000000..8e1b3c930066 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/m88k.h @@ -0,0 +1,197 @@ +/* coff information for 88k bcs + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 4 +#define DO_NOT_DEFINE_SYMENT +#define DO_NOT_DEFINE_AUXENT +#include "coff/external.h" + +#define MC88MAGIC 0540 /* 88k BCS executable */ +#define MC88DMAGIC 0541 /* DG/UX executable */ +#define MC88OMAGIC 0555 /* Object file */ + +#define MC88BADMAG(x) (((x).f_magic != MC88MAGIC) \ + && ((x).f_magic != MC88DMAGIC) \ + && ((x).f_magic != MC88OMAGIC)) + +#define PAGEMAGIC3 0414 /* Split i&d, zero mapped */ +#define PAGEMAGICBCS 0413 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK 017 +#define N_TMASK 060 +#define N_BTSHFT 4 +#define N_TSHIFT 2 + +/* Note that this isn't the same shape as other coffs */ +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + /* 4 */ + + union + { + char x_fsize[4]; /* size of function */ + + struct + { + char x_lnno[4]; /* declaration line number */ + char x_size[4]; /* str/union/array size */ + } x_lnsz; + + } x_misc; + + /* 12 */ + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + /* 20 */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[4]; /* # relocation entries */ + char x_nlinno[4]; /* # line numbers */ + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define GET_LNSZ_SIZE(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_LNSZ_LNNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_LNNO(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_SCN_NRELOC(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nreloc) +#define GET_SCN_NLINNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nlinno) +#define PUT_SCN_NRELOC(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_scn.x_nreloc) +#define PUT_SCN_NLINNO(abfd, in, ext) \ + H_PUT_32 (abfd,in, ext->x_scn.x_nlinno) + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +#define NO_TVNDX diff --git a/external/gpl3/gdb/dist/include/coff/mcore.h b/external/gpl3/gdb/dist/include/coff/mcore.h new file mode 100644 index 000000000000..60dbfb272d15 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/mcore.h @@ -0,0 +1,72 @@ +/* Motorola MCore support for BFD. + Copyright 1999, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MCore COFF/PE ABI. */ + +#ifndef _COFF_MORE_H +#define _COFF_MORE_H + +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +#define MCOREMAGIC 0xb00 /* I just made this up */ + +#define MCOREBADMAG(x) (((x).f_magic != MCOREMAGIC)) + +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +#define IMAGE_REL_MCORE_ABSOLUTE 0x0000 +#define IMAGE_REL_MCORE_ADDR32 0x0001 +#define IMAGE_REL_MCORE_PCREL_IMM8BY4 0x0002 +#define IMAGE_REL_MCORE_PCREL_IMM11BY2 0x0003 +#define IMAGE_REL_MCORE_PCREL_IMM4BY2 0x0004 +#define IMAGE_REL_MCORE_PCREL_32 0x0005 +#define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2 0x0006 +#define IMAGE_REL_MCORE_RVA 0x0007 + +#define PEMCORE + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* From winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +/* Define some NT default values. */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +struct external_reloc +{ + char r_vaddr [4]; + char r_symndx [4]; + char r_type [2]; + char r_offset [4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#endif /* __COFF_MCORE_H */ diff --git a/external/gpl3/gdb/dist/include/coff/mips.h b/external/gpl3/gdb/dist/include/coff/mips.h new file mode 100644 index 000000000000..f1c243b6da2f --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/mips.h @@ -0,0 +1,344 @@ +/* ECOFF support on MIPS machines. + coff/ecoff.h must be included before this file. + + Copyright 1999, 2004, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* Magic numbers are defined in coff/ecoff.h. */ +#define MIPS_ECOFF_BADMAG(x) (((x).f_magic!=MIPS_MAGIC_1) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE) &&\ + ((x).f_magic!=MIPS_MAGIC_BIG) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE2) && \ + ((x).f_magic!=MIPS_MAGIC_BIG2) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE3) && \ + ((x).f_magic!=MIPS_MAGIC_BIG3)) + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct external_aouthdr +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char tsize[4]; /* text size in bytes, padded to FW bdry*/ + unsigned char dsize[4]; /* initialized data " " */ + unsigned char bsize[4]; /* uninitialized data " " */ + unsigned char entry[4]; /* entry pt. */ + unsigned char text_start[4]; /* base of text used for this file */ + unsigned char data_start[4]; /* base of data used for this file */ + unsigned char bss_start[4]; /* base of bss used for this file */ + unsigned char gprmask[4]; /* ?? */ + unsigned char cprmask[4][4]; /* ?? */ + unsigned char gp_value[4]; /* value for gp register */ +} AOUTHDR; + +/* compute size of a header */ + +#define AOUTSZ 56 +#define AOUTHDRSZ 56 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc + { + unsigned char r_vaddr[4]; + unsigned char r_bits[4]; + }; + +#define RELOC struct external_reloc +#define RELSZ 8 + +/* MIPS ECOFF uses a packed 8 byte format for relocs. These constants + are used to unpack the r_bits field. */ + +#define RELOC_BITS0_SYMNDX_SH_LEFT_BIG 16 +#define RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE 0 + +#define RELOC_BITS1_SYMNDX_SH_LEFT_BIG 8 +#define RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE 8 + +#define RELOC_BITS2_SYMNDX_SH_LEFT_BIG 0 +#define RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE 16 + +/* Originally, ECOFF used four bits for the reloc type and had three + reserved bits. Irix 4 added another bit for the reloc type, which + was easy because it was big endian and one of the spare bits became + the new most significant bit. To make this also work for little + endian ECOFF, we need to wrap one of the reserved bits around to + become the most significant bit of the reloc type. */ +#define RELOC_BITS3_TYPE_BIG 0x3E +#define RELOC_BITS3_TYPE_SH_BIG 1 +#define RELOC_BITS3_TYPE_LITTLE 0x78 +#define RELOC_BITS3_TYPE_SH_LITTLE 3 +#define RELOC_BITS3_TYPEHI_LITTLE 0x04 +#define RELOC_BITS3_TYPEHI_SH_LITTLE 2 + +#define RELOC_BITS3_EXTERN_BIG 0x01 +#define RELOC_BITS3_EXTERN_LITTLE 0x80 + +/* The r_type field in a reloc is one of the following values. I + don't know if any other values can appear. These seem to be all + that occur in the Ultrix 4.2 libraries. */ +#define MIPS_R_IGNORE 0 +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 + +/* FIXME: This relocation is used (internally only) to represent branches + when assembling. It should never appear in output files, and + be removed. (It used to be used for embedded-PIC support.) */ +#define MIPS_R_PCREL16 12 + +/********************** STABS **********************/ + +#define MIPS_IS_STAB ECOFF_IS_STAB +#define MIPS_MARK_STAB ECOFF_MARK_STAB +#define MIPS_UNMARK_STAB ECOFF_UNMARK_STAB + +/********************** SYMBOLIC INFORMATION **********************/ + +/* Written by John Gilmore. */ + +/* ECOFF uses COFF-like section structures, but its own symbol format. + This file defines the symbol format in fields whose size and alignment + will not vary on different host systems. */ + +/* File header as a set of bytes */ + +struct hdr_ext +{ + unsigned char h_magic[2]; + unsigned char h_vstamp[2]; + unsigned char h_ilineMax[4]; + unsigned char h_cbLine[4]; + unsigned char h_cbLineOffset[4]; + unsigned char h_idnMax[4]; + unsigned char h_cbDnOffset[4]; + unsigned char h_ipdMax[4]; + unsigned char h_cbPdOffset[4]; + unsigned char h_isymMax[4]; + unsigned char h_cbSymOffset[4]; + unsigned char h_ioptMax[4]; + unsigned char h_cbOptOffset[4]; + unsigned char h_iauxMax[4]; + unsigned char h_cbAuxOffset[4]; + unsigned char h_issMax[4]; + unsigned char h_cbSsOffset[4]; + unsigned char h_issExtMax[4]; + unsigned char h_cbSsExtOffset[4]; + unsigned char h_ifdMax[4]; + unsigned char h_cbFdOffset[4]; + unsigned char h_crfd[4]; + unsigned char h_cbRfdOffset[4]; + unsigned char h_iextMax[4]; + unsigned char h_cbExtOffset[4]; +}; + +/* File descriptor external record */ + +struct fdr_ext +{ + unsigned char f_adr[4]; + unsigned char f_rss[4]; + unsigned char f_issBase[4]; + unsigned char f_cbSs[4]; + unsigned char f_isymBase[4]; + unsigned char f_csym[4]; + unsigned char f_ilineBase[4]; + unsigned char f_cline[4]; + unsigned char f_ioptBase[4]; + unsigned char f_copt[4]; + unsigned char f_ipdFirst[2]; + unsigned char f_cpd[2]; + unsigned char f_iauxBase[4]; + unsigned char f_caux[4]; + unsigned char f_rfdBase[4]; + unsigned char f_crfd[4]; + unsigned char f_bits1[1]; + unsigned char f_bits2[3]; + unsigned char f_cbLineOffset[4]; + unsigned char f_cbLine[4]; +}; + +#define FDR_BITS1_LANG_BIG 0xF8 +#define FDR_BITS1_LANG_SH_BIG 3 +#define FDR_BITS1_LANG_LITTLE 0x1F +#define FDR_BITS1_LANG_SH_LITTLE 0 + +#define FDR_BITS1_FMERGE_BIG 0x04 +#define FDR_BITS1_FMERGE_LITTLE 0x20 + +#define FDR_BITS1_FREADIN_BIG 0x02 +#define FDR_BITS1_FREADIN_LITTLE 0x40 + +#define FDR_BITS1_FBIGENDIAN_BIG 0x01 +#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 + +#define FDR_BITS2_GLEVEL_BIG 0xC0 +#define FDR_BITS2_GLEVEL_SH_BIG 6 +#define FDR_BITS2_GLEVEL_LITTLE 0x03 +#define FDR_BITS2_GLEVEL_SH_LITTLE 0 + +/* We ignore the `reserved' field in bits2. */ + +/* Procedure descriptor external record */ + +struct pdr_ext +{ + unsigned char p_adr[4]; + unsigned char p_isym[4]; + unsigned char p_iline[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_iopt[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_lnLow[4]; + unsigned char p_lnHigh[4]; + unsigned char p_cbLineOffset[4]; +}; + +/* Runtime procedure table */ + +struct rpdr_ext +{ + unsigned char p_adr[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_irpss[4]; + unsigned char p_reserved[4]; + unsigned char p_exception_info[4]; +}; + +/* Line numbers */ + +struct line_ext +{ + unsigned char l_line[4]; +}; + +/* Symbol external record */ + +struct sym_ext +{ + unsigned char s_iss[4]; + unsigned char s_value[4]; + unsigned char s_bits1[1]; + unsigned char s_bits2[1]; + unsigned char s_bits3[1]; + unsigned char s_bits4[1]; +}; + +#define SYM_BITS1_ST_BIG 0xFC +#define SYM_BITS1_ST_SH_BIG 2 +#define SYM_BITS1_ST_LITTLE 0x3F +#define SYM_BITS1_ST_SH_LITTLE 0 + +#define SYM_BITS1_SC_BIG 0x03 +#define SYM_BITS1_SC_SH_LEFT_BIG 3 +#define SYM_BITS1_SC_LITTLE 0xC0 +#define SYM_BITS1_SC_SH_LITTLE 6 + +#define SYM_BITS2_SC_BIG 0xE0 +#define SYM_BITS2_SC_SH_BIG 5 +#define SYM_BITS2_SC_LITTLE 0x07 +#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 + +#define SYM_BITS2_RESERVED_BIG 0x10 +#define SYM_BITS2_RESERVED_LITTLE 0x08 + +#define SYM_BITS2_INDEX_BIG 0x0F +#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 +#define SYM_BITS2_INDEX_LITTLE 0xF0 +#define SYM_BITS2_INDEX_SH_LITTLE 4 + +#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 +#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 + +#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 +#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 + +/* External symbol external record */ + +struct ext_ext +{ + unsigned char es_bits1[1]; + unsigned char es_bits2[1]; + unsigned char es_ifd[2]; + struct sym_ext es_asym; +}; + +#define EXT_BITS1_JMPTBL_BIG 0x80 +#define EXT_BITS1_JMPTBL_LITTLE 0x01 + +#define EXT_BITS1_COBOL_MAIN_BIG 0x40 +#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 + +#define EXT_BITS1_WEAKEXT_BIG 0x20 +#define EXT_BITS1_WEAKEXT_LITTLE 0x04 + +/* Dense numbers external record */ + +struct dnr_ext +{ + unsigned char d_rfd[4]; + unsigned char d_index[4]; +}; + +/* Relative file descriptor */ + +struct rfd_ext +{ + unsigned char rfd[4]; +}; + +/* Optimizer symbol external record */ + +struct opt_ext +{ + unsigned char o_bits1[1]; + unsigned char o_bits2[1]; + unsigned char o_bits3[1]; + unsigned char o_bits4[1]; + struct rndx_ext o_rndx; + unsigned char o_offset[4]; +}; + +#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 +#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 + +#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 +#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 + +#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 +#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 diff --git a/external/gpl3/gdb/dist/include/coff/mipspe.h b/external/gpl3/gdb/dist/include/coff/mipspe.h new file mode 100644 index 000000000000..f1a0d439f2de --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/mipspe.h @@ -0,0 +1,67 @@ +/* coff information for Windows CE with MIPS VR4111 + + Copyright 2000, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define MIPS_ARCH_MAGIC_WINCE 0x0166 /* Windows CE - little endian */ +#define MIPS_PE_MAGIC 0x010b + +#define MIPSBADMAG(x) ((x).f_magic != MIPS_ARCH_MAGIC_WINCE) + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* MIPS PE relocation types. */ + +#define MIPS_R_ABSOLUTE 0 /* ignored */ +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 /* PAIR follows */ +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 /* same as GPREL */ +#define MIPS_R_SECTION 10 +#define MIPS_R_SECREL 11 +#define MIPS_R_SECRELLO 12 +#define MIPS_R_SECRELHI 13 /* PAIR follows */ +#define MIPS_R_RVA 34 /* 0x22 */ +#define MIPS_R_PAIR 37 /* 0x25 - symndx is really a signed 16-bit addend */ diff --git a/external/gpl3/gdb/dist/include/coff/or32.h b/external/gpl3/gdb/dist/include/coff/or32.h new file mode 100644 index 000000000000..9be7887ad96e --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/or32.h @@ -0,0 +1,288 @@ +/* COFF specification for OpenRISC 1000. + Copyright (C) 1993-2000, 2002, 2010 Free Software Foundation, Inc. + Contributed by David Wood @ New York University. + Modified by Johan Rydberg, + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef OR32 +# define OR32 +#endif + +/* File Header and related definitions. */ +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/* Magic numbers for OpenRISC 1000. As it is know we use the + numbers for Am29000. + + (AT&T will assign the "real" magic number). */ +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB). */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB). */ + +#define OR32_MAGIC_BIG SIPFBOMAGIC +#define OR32_MAGIC_LITTLE SIPRBOMAGIC +#define OR32BADMAG(x) (((x).f_magic!=OR32_MAGIC_BIG) && \ + ((x).f_magic!=OR32_MAGIC_LITTLE)) + +#define OMAGIC OR32_MAGIC_BIG + +/* Optional (a.out) header. */ +typedef struct external_aouthdr +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry */ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +/* aouthdr magic numbers. */ +#define NMAGIC 0410 /* separate i/d executable. */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text). */ + +#define _ETEXT "_etext" + +/* Section header and related definitions. */ +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections: */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _LIT ".lit" + +/* Section types - with additional section type for global + registers which will be relocatable for the OpenRISC 1000. + + In instances where it is necessary for a linker to produce an + output file which contains text or data not based at virtual + address 0, e.g. for a ROM, then the linker should accept + address base information as command input and use PAD sections + to skip over unused addresses. */ +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ + +/* Relocation information declaration and related definitions: */ +struct external_reloc +{ + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* Relocation types for the OpenRISC 1000: */ + +#define R_ABS 0 /* reference is absolute */ +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* + NOTE: + All the "I" forms refer to 29000 instruction formats. The linker is + expected to know how the numeric information is split and/or aligned + within the instruction word(s). R_BYTE works for instructions, too. + + If the parameter to a CONSTH instruction is a relocatable type, two + relocation records are written. The first has an r_type of R_IHIHALF + (33 octal) and a normal r_vaddr and r_symndx. The second relocation + record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which + is redundant), and an r_symndx containing the 32-bit constant offset + to the relocation instead of the actual symbol table index. This + second record is always written, even if the constant offset is zero. + The constant fields of the instruction are set to zero. */ + +/* Line number entry declaration and related definitions: */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } + l_addr; + + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 /* sizeof (LINENO) */ + +/* Symbol entry declaration and related definitions: */ +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + struct + { + char e_zeroes[4]; + char e_offset[4]; + } + e; + } + e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +/* Storage class definitions - new classes for global registers: */ +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ + +/* Derived symbol mask/shifts: */ +#define N_BTMASK (0xf) +#define N_BTSHFT (4) +#define N_TMASK (0x30) +#define N_TSHIFT (2) + +/* Auxiliary symbol table entry declaration and related + definitions. */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } + x_lnsz; + + char x_fsize[4]; /* size of function */ + } + x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } + x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } + x_ary; + } + x_fcnary; + + char x_tvndx[2]; /* tv index */ + } + x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } + x_n; + } + x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } + x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } + x_tv; /* info about .tv section + (in auxent of symbol .tv)) */ +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 diff --git a/external/gpl3/gdb/dist/include/coff/pe.h b/external/gpl3/gdb/dist/include/coff/pe.h new file mode 100644 index 000000000000..601a68e8f113 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/pe.h @@ -0,0 +1,512 @@ +/* pe.h - PE COFF header information + + Copyright 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ +#ifndef _PE_H +#define _PE_H + +/* NT specific file attributes. */ +#define IMAGE_FILE_RELOCS_STRIPPED 0x0001 +#define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 +#define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 +#define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +#define IMAGE_FILE_16BIT_MACHINE 0x0040 +#define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 +#define IMAGE_FILE_32BIT_MACHINE 0x0100 +#define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 +#define IMAGE_FILE_NET_RUN_FROM_SWAP 0x0800 +#define IMAGE_FILE_SYSTEM 0x1000 +#define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 +#define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 + +/* DllCharacteristics flag bits. The inconsistent naming may seem + odd, but that is how they are defined in the PE specification. */ +#define IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE 0x0040 +#define IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY 0x0080 +#define IMAGE_DLL_CHARACTERISTICS_NX_COMPAT 0x0100 +#define IMAGE_DLLCHARACTERISTICS_NO_ISOLATION 0x0200 +#define IMAGE_DLLCHARACTERISTICS_NO_SEH 0x0400 +#define IMAGE_DLLCHARACTERISTICS_NO_BIND 0x0800 +#define IMAGE_DLLCHARACTERISTICS_WDM_DRIVER 0x2000 +#define IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE 0x8000 + +/* Additional flags to be set for section headers to allow the NT loader to + read and write to the section data (to replace the addresses of data in + dlls for one thing); also to execute the section in .text's case. */ +#define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 +#define IMAGE_SCN_MEM_EXECUTE 0x20000000 +#define IMAGE_SCN_MEM_READ 0x40000000 +#define IMAGE_SCN_MEM_WRITE 0x80000000 + +/* Section characteristics added for ppc-nt. */ + +#define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* Reserved. */ + +#define IMAGE_SCN_CNT_CODE 0x00000020 /* Section contains code. */ +#define IMAGE_SCN_CNT_INITIALIZED_DATA 0x00000040 /* Section contains initialized data. */ +#define IMAGE_SCN_CNT_UNINITIALIZED_DATA 0x00000080 /* Section contains uninitialized data. */ + +#define IMAGE_SCN_LNK_OTHER 0x00000100 /* Reserved. */ +#define IMAGE_SCN_LNK_INFO 0x00000200 /* Section contains comments or some other type of information. */ +#define IMAGE_SCN_LNK_REMOVE 0x00000800 /* Section contents will not become part of image. */ +#define IMAGE_SCN_LNK_COMDAT 0x00001000 /* Section contents comdat. */ + +#define IMAGE_SCN_MEM_FARDATA 0x00008000 + +#define IMAGE_SCN_MEM_PURGEABLE 0x00020000 +#define IMAGE_SCN_MEM_16BIT 0x00020000 +#define IMAGE_SCN_MEM_LOCKED 0x00040000 +#define IMAGE_SCN_MEM_PRELOAD 0x00080000 + +/* Bit position in the s_flags field where the alignment values start. */ +#define IMAGE_SCN_ALIGN_POWER_BIT_POS 20 +#define IMAGE_SCN_ALIGN_POWER_BIT_MASK 0x00f00000 +#define IMAGE_SCN_ALIGN_POWER_NUM(val) \ + (((val) >> IMAGE_SCN_ALIGN_POWER_BIT_POS) - 1) +#define IMAGE_SCN_ALIGN_POWER_CONST(val) \ + (((val) + 1) << IMAGE_SCN_ALIGN_POWER_BIT_POS) + +#define IMAGE_SCN_ALIGN_1BYTES IMAGE_SCN_ALIGN_POWER_CONST (0) +#define IMAGE_SCN_ALIGN_2BYTES IMAGE_SCN_ALIGN_POWER_CONST (1) +#define IMAGE_SCN_ALIGN_4BYTES IMAGE_SCN_ALIGN_POWER_CONST (2) +#define IMAGE_SCN_ALIGN_8BYTES IMAGE_SCN_ALIGN_POWER_CONST (3) +/* Default alignment if no others are specified. */ +#define IMAGE_SCN_ALIGN_16BYTES IMAGE_SCN_ALIGN_POWER_CONST (4) +#define IMAGE_SCN_ALIGN_32BYTES IMAGE_SCN_ALIGN_POWER_CONST (5) +#define IMAGE_SCN_ALIGN_64BYTES IMAGE_SCN_ALIGN_POWER_CONST (6) +#define IMAGE_SCN_ALIGN_128BYTES IMAGE_SCN_ALIGN_POWER_CONST (7) +#define IMAGE_SCN_ALIGN_256BYTES IMAGE_SCN_ALIGN_POWER_CONST (8) +#define IMAGE_SCN_ALIGN_512BYTES IMAGE_SCN_ALIGN_POWER_CONST (9) +#define IMAGE_SCN_ALIGN_1024BYTES IMAGE_SCN_ALIGN_POWER_CONST (10) +#define IMAGE_SCN_ALIGN_2048BYTES IMAGE_SCN_ALIGN_POWER_CONST (11) +#define IMAGE_SCN_ALIGN_4096BYTES IMAGE_SCN_ALIGN_POWER_CONST (12) +#define IMAGE_SCN_ALIGN_8192BYTES IMAGE_SCN_ALIGN_POWER_CONST (13) + +/* Encode alignment power into IMAGE_SCN_ALIGN bits of s_flags */ +#define COFF_ENCODE_ALIGNMENT(SECTION, ALIGNMENT_POWER) \ + ((SECTION).s_flags |= IMAGE_SCN_ALIGN_POWER_CONST ((ALIGNMENT_POWER))) + +#define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* Section contains extended relocations. */ +#define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* Section is not cachable. */ +#define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* Section is not pageable. */ +#define IMAGE_SCN_MEM_SHARED 0x10000000 /* Section is shareable. */ + +/* COMDAT selection codes. */ + +#define IMAGE_COMDAT_SELECT_NODUPLICATES (1) /* Warn if duplicates. */ +#define IMAGE_COMDAT_SELECT_ANY (2) /* No warning. */ +#define IMAGE_COMDAT_SELECT_SAME_SIZE (3) /* Warn if different size. */ +#define IMAGE_COMDAT_SELECT_EXACT_MATCH (4) /* Warn if different. */ +#define IMAGE_COMDAT_SELECT_ASSOCIATIVE (5) /* Base on other section. */ + +/* Machine numbers. */ + +#define IMAGE_FILE_MACHINE_UNKNOWN 0x0000 +#define IMAGE_FILE_MACHINE_ALPHA 0x0184 +#define IMAGE_FILE_MACHINE_ALPHA64 0x0284 +#define IMAGE_FILE_MACHINE_AM33 0x01d3 +#define IMAGE_FILE_MACHINE_AMD64 0x8664 +#define IMAGE_FILE_MACHINE_ARM 0x01c0 +#define IMAGE_FILE_MACHINE_AXP64 IMAGE_FILE_MACHINE_ALPHA64 +#define IMAGE_FILE_MACHINE_CEE 0xc0ee +#define IMAGE_FILE_MACHINE_CEF 0x0cef +#define IMAGE_FILE_MACHINE_EBC 0x0ebc +#define IMAGE_FILE_MACHINE_I386 0x014c +#define IMAGE_FILE_MACHINE_IA64 0x0200 +#define IMAGE_FILE_MACHINE_M32R 0x9041 +#define IMAGE_FILE_MACHINE_M68K 0x0268 +#define IMAGE_FILE_MACHINE_MIPS16 0x0266 +#define IMAGE_FILE_MACHINE_MIPSFPU 0x0366 +#define IMAGE_FILE_MACHINE_MIPSFPU16 0x0466 +#define IMAGE_FILE_MACHINE_POWERPC 0x01f0 +#define IMAGE_FILE_MACHINE_POWERPCFP 0x01f1 +#define IMAGE_FILE_MACHINE_R10000 0x0168 +#define IMAGE_FILE_MACHINE_R3000 0x0162 +#define IMAGE_FILE_MACHINE_R4000 0x0166 +#define IMAGE_FILE_MACHINE_SH3 0x01a2 +#define IMAGE_FILE_MACHINE_SH3DSP 0x01a3 +#define IMAGE_FILE_MACHINE_SH3E 0x01a4 +#define IMAGE_FILE_MACHINE_SH4 0x01a6 +#define IMAGE_FILE_MACHINE_SH5 0x01a8 +#define IMAGE_FILE_MACHINE_THUMB 0x01c2 +#define IMAGE_FILE_MACHINE_TRICORE 0x0520 +#define IMAGE_FILE_MACHINE_WCEMIPSV2 0x0169 +#define IMAGE_FILE_MACHINE_AMD64 0x8664 + +#define IMAGE_SUBSYSTEM_UNKNOWN 0 +#define IMAGE_SUBSYSTEM_NATIVE 1 +#define IMAGE_SUBSYSTEM_WINDOWS_GUI 2 +#define IMAGE_SUBSYSTEM_WINDOWS_CUI 3 +#define IMAGE_SUBSYSTEM_POSIX_CUI 7 +#define IMAGE_SUBSYSTEM_WINDOWS_CE_GUI 9 +#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 +#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 +#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 +#define IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13 +#define IMAGE_SUBSYSTEM_XBOX 14 + +/* Magic values that are true for all dos/nt implementations. */ +#define DOSMAGIC 0x5a4d +#define NT_SIGNATURE 0x00004550 + +/* NT allows long filenames, we want to accommodate this. + This may break some of the bfd functions. */ +#undef FILNMLEN +#define FILNMLEN 18 /* # characters in a file name. */ + +struct external_PEI_DOS_hdr +{ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ +}; + +struct external_PEI_IMAGE_hdr +{ + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ +}; + +struct external_PEI_filehdr +{ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ + + /* Note: additional bytes may be inserted before the signature. Use + the e_lfanew field to find the actual location of the NT signature. */ + + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ +}; + +#ifdef COFF_IMAGE_WITH_PE + +/* The filehdr is only weird in images. */ + +#undef FILHDR +#define FILHDR struct external_PEI_filehdr +#undef FILHSZ +#define FILHSZ 152 + +#endif /* COFF_IMAGE_WITH_PE */ + +/* 32-bit PE a.out header: */ + +typedef struct +{ + AOUTHDR standard; + + /* NT extra fields; see internal.h for descriptions. */ + char ImageBase[4]; + char SectionAlignment[4]; + char FileAlignment[4]; + char MajorOperatingSystemVersion[2]; + char MinorOperatingSystemVersion[2]; + char MajorImageVersion[2]; + char MinorImageVersion[2]; + char MajorSubsystemVersion[2]; + char MinorSubsystemVersion[2]; + char Reserved1[4]; + char SizeOfImage[4]; + char SizeOfHeaders[4]; + char CheckSum[4]; + char Subsystem[2]; + char DllCharacteristics[2]; + char SizeOfStackReserve[4]; + char SizeOfStackCommit[4]; + char SizeOfHeapReserve[4]; + char SizeOfHeapCommit[4]; + char LoaderFlags[4]; + char NumberOfRvaAndSizes[4]; + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ +} PEAOUTHDR; + +#undef AOUTSZ +#define AOUTSZ (AOUTHDRSZ + 196) + +/* Like PEAOUTHDR, except that the "standard" member has no BaseOfData + (aka data_start) member and that some of the members are 8 instead + of just 4 bytes long. */ +typedef struct +{ +#ifdef AOUTHDRSZ64 + AOUTHDR64 standard; +#else + AOUTHDR standard; +#endif + /* NT extra fields; see internal.h for descriptions. */ + char ImageBase[8]; + char SectionAlignment[4]; + char FileAlignment[4]; + char MajorOperatingSystemVersion[2]; + char MinorOperatingSystemVersion[2]; + char MajorImageVersion[2]; + char MinorImageVersion[2]; + char MajorSubsystemVersion[2]; + char MinorSubsystemVersion[2]; + char Reserved1[4]; + char SizeOfImage[4]; + char SizeOfHeaders[4]; + char CheckSum[4]; + char Subsystem[2]; + char DllCharacteristics[2]; + char SizeOfStackReserve[8]; + char SizeOfStackCommit[8]; + char SizeOfHeapReserve[8]; + char SizeOfHeapCommit[8]; + char LoaderFlags[4]; + char NumberOfRvaAndSizes[4]; + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ +} PEPAOUTHDR; + +#ifdef AOUTHDRSZ64 +#define PEPAOUTSZ (AOUTHDRSZ64 + 196 + 5 * 4) /* = 240 */ +#else +#define PEPAOUTSZ 240 +#endif + +#undef E_FILNMLEN +#define E_FILNMLEN 18 /* # characters in a file name. */ + +/* Import Tyoes fot ILF format object files.. */ +#define IMPORT_CODE 0 +#define IMPORT_DATA 1 +#define IMPORT_CONST 2 + +/* Import Name Tyoes for ILF format object files. */ +#define IMPORT_ORDINAL 0 +#define IMPORT_NAME 1 +#define IMPORT_NAME_NOPREFIX 2 +#define IMPORT_NAME_UNDECORATE 3 + +/* Weak external characteristics. */ +#define IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1 +#define IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2 +#define IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3 + +/* .pdata/.xdata defines and structures for x64 PE+ for exception handling. */ + +/* .pdata in exception directory. */ + +struct pex64_runtime_function +{ + bfd_vma rva_BeginAddress; + bfd_vma rva_EndAddress; + bfd_vma rva_UnwindData; + unsigned int isChained : 1; +}; + +struct external_pex64_runtime_function +{ + bfd_byte rva_BeginAddress[4]; + bfd_byte rva_EndAddress[4]; + bfd_byte rva_UnwindData[4]; +}; + +/* If the lowest significant bit is set for rva_UnwindData RVA, it + means that the unified RVA points to another pex64_runtime_function + that this entry shares the unwind_info block with. */ +#define PEX64_IS_RUNTIME_FUNCTION_CHAINED(PTR_RTF) \ + (((PTR_RTF)->rva_UnwindData & 1) != 0) +#define PEX64_GET_UNWINDDATA_UNIFIED_RVA(PTR_RTF) \ + ((PTR_RTF)->rva_UnwindData & ~1) + +/* The unwind codes. */ +#define UWOP_PUSH_NONVOL 0 +#define UWOP_ALLOC_LARGE 1 +#define UWOP_ALLOC_SMALL 2 +#define UWOP_SET_FPREG 3 +#define UWOP_SAVE_NONVOL 4 +#define UWOP_SAVE_NONVOL_FAR 5 +#define UWOP_SAVE_XMM 6 +#define UWOP_SAVE_XMM_FAR 7 +#define UWOP_SAVE_XMM128 8 +#define UWOP_SAVE_XMM128_FAR 9 +#define UWOP_PUSH_MACHFRAME 10 + +struct pex64_unwind_code +{ + bfd_vma prologue_offset; + /* Contains Frame offset, or frame allocation size. */ + bfd_vma frame_addr; + unsigned int uwop_code : 4; + /* xmm, mm, or standard register from 0 - 15. */ + unsigned int reg : 4; + /* Used for UWOP_PUSH_MACHFRAME to indicate optional errorcode stack + argument. */ + unsigned int has_errorcode : 1; +}; + +struct external_pex64_unwind_code +{ + bfd_byte dta[2]; +}; + +#define PEX64_UNWCODE_CODE(VAL) ((VAL) & 0xf) +#define PEX64_UNWCODE_INFO(VAL) (((VAL) >> 4) & 0xf) + +/* The unwind info. */ +#define UNW_FLAG_NHANDLER 0 +#define UNW_FLAG_EHANDLER 1 +#define UNW_FLAG_UHANDLER 2 +#define UNW_FLAG_FHANDLER 3 +#define UNW_FLAG_CHAININFO 4 + +#define UNW_FLAG_MASK 0x1f + +struct pex64_unwind_info +{ + bfd_vma SizeOfBlock; + bfd_byte Version; /* Values from 0 up to 7 are possible. */ + bfd_byte Flags; /* Values from 0 up to 31 are possible. */ + bfd_vma SizeOfPrologue; + bfd_vma CountOfCodes; /* Amount of pex64_unwind_code elements. */ + /* 0 = CFA, 1..15 are index of integer registers. */ + unsigned int FrameRegister : 4; + bfd_vma FrameOffset; + bfd_vma sizeofUnwindCodes; + bfd_byte *rawUnwindCodes; + /* Valid for UNW_FLAG_EHANDLER and UNW_FLAG_UHANDLER. */ + bfd_vma CountOfScopes; + bfd_byte *rawScopeEntries; + bfd_vma rva_ExceptionHandler; /* UNW_EHANDLER. */ + bfd_vma rva_TerminationHandler; /* UNW_FLAG_UHANDLER. */ + bfd_vma rva_FrameHandler; /* UNW_FLAG_FHANDLER. */ + bfd_vma FrameHandlerArgument; /* UNW_FLAG_FHANDLER. */ + bfd_vma rva_FunctionEntry; /* UNW_FLAG_CHAININFO. */ +}; + +struct external_pex64_unwind_info +{ + bfd_byte Version_Flags; + bfd_byte SizeOfPrologue; + bfd_byte CountOfCodes; + bfd_byte FrameRegisterOffset; + /* external_pex64_unwind_code array. */ + /* bfd_byte handler[4]; */ + /* Optional language specific data. */ +}; + +struct external_pex64_scope +{ + bfd_vma Count; +}; + +struct pex64_scope +{ + bfd_byte Count[4]; +}; + +struct pex64_scope_entry +{ + bfd_vma rva_BeginAddress; + bfd_vma rva_EndAddress; + bfd_vma rva_HandlerAddress; + bfd_vma rva_JumpAddress; +}; +#define PEX64_SCOPE_ENTRY_SIZE 16 + +struct external_pex64_scope_entry +{ + bfd_byte rva_BeginAddress[4]; + bfd_byte rva_EndAddress[4]; + bfd_byte rva_HandlerAddress[4]; + bfd_byte rva_JumpAddress[4]; +}; + +#define PEX64_UWI_VERSION(VAL) ((VAL) & 7) +#define PEX64_UWI_FLAGS(VAL) (((VAL) >> 3) & 0x1f) +#define PEX64_UWI_FRAMEREG(VAL) ((VAL) & 0xf) +#define PEX64_UWI_FRAMEOFF(VAL) (((VAL) >> 4) & 0xf) +#define PEX64_UWI_SIZEOF_UWCODE_ARRAY(VAL) \ + ((((VAL) + 1) & ~1) * 2) + +#define PEX64_OFFSET_TO_UNWIND_CODE 0x4 + +#define PEX64_OFFSET_TO_HANDLER_RVA (COUNTOFUNWINDCODES) \ + (PEX64_OFFSET_TO_UNWIND_CODE + \ + PEX64_UWI_SIZEOF_UWCODE_ARRAY(COUNTOFUNWINDCODES)) + +#define PEX64_OFFSET_TO_SCOPE_COUNT(COUNTOFUNWINDCODES) \ + (PEX64_OFFSET_TO_HANDLER_RVA(COUNTOFUNWINDCODES) + 4) + +#define PEX64_SCOPE_ENTRY(COUNTOFUNWINDCODES, IDX) \ + (PEX64_OFFSET_TO_SCOPE_COUNT(COUNTOFUNWINDCODES) + \ + PEX64_SCOPE_ENTRY_SIZE * (IDX)) + +#endif /* _PE_H */ diff --git a/external/gpl3/gdb/dist/include/coff/powerpc.h b/external/gpl3/gdb/dist/include/coff/powerpc.h new file mode 100644 index 000000000000..eba473091fbd --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/powerpc.h @@ -0,0 +1,59 @@ +/* Basic coff information for the PowerPC + Based on coff/rs6000.h, coff/i386.h and others. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. + + Initial release: Kim Knuttila (krk@cygnus.com) */ +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +/* extra NT defines */ +#define PPCMAGIC 0760 /* peeked on aa PowerPC Windows NT box */ +#define DOSMAGIC 0x5a4d /* from arm.h, i386.h */ +#define NT_SIGNATURE 0x00004550 /* from arm.h, i386.h */ + +/* from winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +#define PPCBADMAG(x) ((x).f_magic != PPCMAGIC) + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/external/gpl3/gdb/dist/include/coff/rs6000.h b/external/gpl3/gdb/dist/include/coff/rs6000.h new file mode 100644 index 000000000000..4d431df29826 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/rs6000.h @@ -0,0 +1,278 @@ +/* IBM RS/6000 "XCOFF" file definitions for BFD. + Copyright (C) 1990, 1991, 2001, 2010 Free Software Foundation, Inc. + Written by Mimi Phuong-Thao Vo of IBM + and John Gilmore of Cygnus Support. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + + /* IBM RS/6000 */ +#define U802WRMAGIC 0730 /* writeable text segments **chh** */ +#define U802ROMAGIC 0735 /* readonly sharable text segments */ +#define U802TOCMAGIC 0737 /* readonly text segments and TOC */ + +#define BADMAG(x) \ + ((x).f_magic != U802ROMAGIC && (x).f_magic != U802WRMAGIC && \ + (x).f_magic != U802TOCMAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char tsize[4]; /* text size in bytes, padded to FW bdry */ + unsigned char dsize[4]; /* initialized data " " */ + unsigned char bsize[4]; /* uninitialized data " " */ + unsigned char entry[4]; /* entry pt. */ + unsigned char text_start[4]; /* base of text used for this file */ + unsigned char data_start[4]; /* base of data used for this file */ + unsigned char o_toc[4]; /* address of TOC */ + unsigned char o_snentry[2]; /* section number of entry point */ + unsigned char o_sntext[2]; /* section number of .text section */ + unsigned char o_sndata[2]; /* section number of .data section */ + unsigned char o_sntoc[2]; /* section number of TOC */ + unsigned char o_snloader[2]; /* section number of .loader section */ + unsigned char o_snbss[2]; /* section number of .bss section */ + unsigned char o_algntext[2]; /* .text alignment */ + unsigned char o_algndata[2]; /* .data alignment */ + unsigned char o_modtype[2]; /* module type (??) */ + unsigned char o_cputype[2]; /* cpu type */ + unsigned char o_maxstack[4]; /* max stack size (??) */ + unsigned char o_maxdata[4]; /* max data size (??) */ + unsigned char o_resv2[12]; /* reserved */ +} +AOUTHDR; + +#define AOUTSZ 72 +#define SMALL_AOUTSZ (28) +#define AOUTHDRSZ 72 + +/********************** SECTION HEADER **********************/ + + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + struct { + unsigned char x_scnlen[4]; + unsigned char x_parmhash[4]; + unsigned char x_snhash[2]; + unsigned char x_smtyp[1]; + unsigned char x_smclas[1]; + unsigned char x_stab[4]; + unsigned char x_snstab[2]; + } x_csect; + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 +#define DBXMASK 0x80 /* for dbx storage mask */ +#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK) + + + +/********************** RELOCATION DIRECTIVES **********************/ + + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_size[1]; + char r_type[1]; +}; + + +#define RELOC struct external_reloc +#define RELSZ 10 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct external_ldhdr +{ + bfd_byte l_version[4]; + bfd_byte l_nsyms[4]; + bfd_byte l_nreloc[4]; + bfd_byte l_istlen[4]; + bfd_byte l_nimpid[4]; + bfd_byte l_impoff[4]; + bfd_byte l_stlen[4]; + bfd_byte l_stoff[4]; +}; + +#define LDHDRSZ (8 * 4) + +struct external_ldsym +{ + union + { + bfd_byte _l_name[SYMNMLEN]; + struct + { + bfd_byte _l_zeroes[4]; + bfd_byte _l_offset[4]; + } _l_l; + } _l; + bfd_byte l_value[4]; + bfd_byte l_scnum[2]; + bfd_byte l_smtype[1]; + bfd_byte l_smclas[1]; + bfd_byte l_ifile[4]; + bfd_byte l_parm[4]; +}; + +#define LDSYMSZ (8 + 3 * 4 + 2 + 2) + +struct external_ldrel +{ + bfd_byte l_vaddr[4]; + bfd_byte l_symndx[4]; + bfd_byte l_rtype[2]; + bfd_byte l_rsecnm[2]; +}; + +#define LDRELSZ (2 * 4 + 2 * 2) diff --git a/external/gpl3/gdb/dist/include/coff/rs6k64.h b/external/gpl3/gdb/dist/include/coff/rs6k64.h new file mode 100644 index 000000000000..516758bb1e67 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/rs6k64.h @@ -0,0 +1,261 @@ +/* IBM RS/6000 "XCOFF64" file definitions for BFD. + Copyright (C) 2000, 2001, 2002, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[8]; /* file pointer to symtab */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_nsyms[4]; /* number of symtab entries */ +}; + +/* IBM RS/6000. */ +#define U803XTOCMAGIC 0757 /* Aix 4.3 64-bit XCOFF */ +#define U64_TOCMAGIC 0767 /* AIX 5+ 64-bit XCOFF */ +#define BADMAG(x) ((x).f_magic != U803XTOCMAGIC && (x).f_magic != U64_TOCMAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 24 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char o_debugger[4]; /* reserved */ + unsigned char text_start[8]; /* base of text used for this file */ + unsigned char data_start[8]; /* base of data used for this file */ + unsigned char o_toc[8]; /* address of TOC */ + unsigned char o_snentry[2]; /* section number of entry point */ + unsigned char o_sntext[2]; /* section number of .text section */ + unsigned char o_sndata[2]; /* section number of .data section */ + unsigned char o_sntoc[2]; /* section number of TOC */ + unsigned char o_snloader[2]; /* section number of .loader section */ + unsigned char o_snbss[2]; /* section number of .bss section */ + unsigned char o_algntext[2]; /* .text alignment */ + unsigned char o_algndata[2]; /* .data alignment */ + unsigned char o_modtype[2]; /* module type (??) */ + unsigned char o_cputype[2]; /* cpu type */ + unsigned char o_resv2[4]; /* reserved */ + unsigned char tsize[8]; /* text size bytes, padded to FW bdry */ + unsigned char dsize[8]; /* initialized data " " */ + unsigned char bsize[8]; /* uninitialized data " " */ + unsigned char entry[8]; /* entry pt. */ + unsigned char o_maxstack[8]; /* max stack size (??) */ + unsigned char o_maxdata[8]; /* max data size (??) */ + unsigned char o_resv3[16]; /* reserved */ +} +AOUTHDR; + +#define AOUTSZ 120 +#define SMALL_AOUTSZ (0) +#define AOUTHDRSZ 72 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[8]; /* physical address, aliased s_nlib */ + char s_vaddr[8]; /* virtual address */ + char s_size[8]; /* section size */ + char s_scnptr[8]; /* file ptr to raw data for section */ + char s_relptr[8]; /* file ptr to relocation */ + char s_lnnoptr[8]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_pad[4]; /* padding */ +}; + +#define SCNHDR struct external_scnhdr + +#define SCNHSZ 72 + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ + +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[8]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[4]; /* line number */ +}; + +#define LINENO struct external_lineno + +#define LINESZ 12 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + char e_value[8]; + char e_offset[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct { + union { + struct { + char x_lnno[4]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + struct { + char x_lnnoptr[8];/* ptr to fcn line */ + char x_fsize[4]; /* size of function */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + } x_fcnary; + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + char x_pad[6]; + unsigned char x_ftype[1]; + unsigned char x_resv[2]; + } x_n; + } x_file; + + struct { + char x_exptr[8]; + char x_fsize[4]; + char x_endndx[4]; + char x_pad[1]; + } x_except; + + struct { + unsigned char x_scnlen_lo[4]; + unsigned char x_parmhash[4]; + unsigned char x_snhash[2]; + unsigned char x_smtyp[1]; + unsigned char x_smclas[1]; + unsigned char x_scnlen_hi[4]; + unsigned char x_pad[1]; + } x_csect; + + struct { + char x_pad[17]; + char x_auxtype[1]; + } x_auxtype; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 +#define DBXMASK 0x80 /* for dbx storage mask */ +#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK) + +/* Values for auxtype field in XCOFF64, taken from AIX 4.3 sym.h. */ +#define _AUX_EXCEPT 255 +#define _AUX_FCN 254 +#define _AUX_SYM 253 +#define _AUX_FILE 252 +#define _AUX_CSECT 251 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[8]; + char r_symndx[4]; + char r_size[1]; + char r_type[1]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#define DEFAULT_DATA_SECTION_ALIGNMENT 4 +#define DEFAULT_BSS_SECTION_ALIGNMENT 4 +#define DEFAULT_TEXT_SECTION_ALIGNMENT 4 +/* For new sections we havn't heard of before */ +#define DEFAULT_SECTION_ALIGNMENT 4 + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct external_ldhdr +{ + bfd_byte l_version[4]; + bfd_byte l_nsyms[4]; + bfd_byte l_nreloc[4]; + bfd_byte l_istlen[4]; + bfd_byte l_nimpid[4]; + bfd_byte l_stlen[4]; + bfd_byte l_impoff[8]; + bfd_byte l_stoff[8]; + bfd_byte l_symoff[8]; + bfd_byte l_rldoff[8]; +}; +#define LDHDRSZ (56) + +struct external_ldsym +{ + bfd_byte l_value[8]; + bfd_byte l_offset[4]; + bfd_byte l_scnum[2]; + bfd_byte l_smtype[1]; + bfd_byte l_smclas[1]; + bfd_byte l_ifile[4]; + bfd_byte l_parm[4]; +}; + +#define LDSYMSZ (24) + +struct external_ldrel +{ + bfd_byte l_vaddr[8]; + bfd_byte l_rtype[2]; + bfd_byte l_rsecnm[2]; + bfd_byte l_symndx[4]; +}; + +#define LDRELSZ (16) diff --git a/external/gpl3/gdb/dist/include/coff/sh.h b/external/gpl3/gdb/dist/include/coff/sh.h new file mode 100644 index 000000000000..bf131046961c --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/sh.h @@ -0,0 +1,148 @@ +/* coff information for Renesas SH + + Copyright 2000, 2003, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifdef COFF_WITH_PE +#define L_LNNO_SIZE 2 +#else +#define L_LNNO_SIZE 4 +#endif +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#include "coff/external.h" + +#define SH_ARCH_MAGIC_BIG 0x0500 +#define SH_ARCH_MAGIC_LITTLE 0x0550 /* Little endian SH */ +#define SH_ARCH_MAGIC_WINCE 0x01a2 /* Windows CE - little endian */ +#define SH_PE_MAGIC 0x010b + +#define SHBADMAG(x) \ + (((x).f_magic != SH_ARCH_MAGIC_BIG) && \ + ((x).f_magic != SH_ARCH_MAGIC_WINCE) && \ + ((x).f_magic != SH_ARCH_MAGIC_LITTLE)) + +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +#ifndef COFF_WITH_PE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; +#else +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; +#endif + +#define RELOC struct external_reloc +#ifdef COFF_WITH_PE +#define RELSZ 10 +#else +#define RELSZ 16 +#endif + +/* SH relocation types. Not all of these are actually used. */ + +#define R_SH_UNUSED 0 /* only used internally */ +#define R_SH_IMM32CE 2 /* 32 bit immediate for WinCE */ +#define R_SH_PCREL8 3 /* 8 bit pcrel */ +#define R_SH_PCREL16 4 /* 16 bit pcrel */ +#define R_SH_HIGH8 5 /* high 8 bits of 24 bit address */ +#define R_SH_LOW16 7 /* low 16 bits of 24 bit immediate */ +#define R_SH_IMM24 6 /* 24 bit immediate */ +#define R_SH_PCDISP8BY4 9 /* PC rel 8 bits *4 +ve */ +#define R_SH_PCDISP8BY2 10 /* PC rel 8 bits *2 +ve */ +#define R_SH_PCDISP8 11 /* 8 bit branch */ +#define R_SH_PCDISP 12 /* 12 bit branch */ +#define R_SH_IMM32 14 /* 32 bit immediate */ +#define R_SH_IMM8 16 /* 8 bit immediate */ +#define R_SH_IMAGEBASE 16 /* Windows CE */ +#define R_SH_IMM8BY2 17 /* 8 bit immediate *2 */ +#define R_SH_IMM8BY4 18 /* 8 bit immediate *4 */ +#define R_SH_IMM4 19 /* 4 bit immediate */ +#define R_SH_IMM4BY2 20 /* 4 bit immediate *2 */ +#define R_SH_IMM4BY4 21 /* 4 bit immediate *4 */ +#define R_SH_PCRELIMM8BY2 22 /* PC rel 8 bits *2 unsigned */ +#define R_SH_PCRELIMM8BY4 23 /* PC rel 8 bits *4 unsigned */ +#define R_SH_IMM16 24 /* 16 bit immediate */ + +/* The switch table reloc types are used for relaxing. They are + generated for expressions such as + .word L1 - L2 + The r_offset field holds the difference between the reloc address + and L2. */ +#define R_SH_SWITCH8 33 /* 8 bit switch table entry */ +#define R_SH_SWITCH16 25 /* 16 bit switch table entry */ +#define R_SH_SWITCH32 26 /* 32 bit switch table entry */ + +/* The USES reloc type is used for relaxing. The compiler will + generate .uses pseudo-ops when it finds a function call which it + can relax. The r_offset field of the USES reloc holds the PC + relative offset to the instruction which loads the register used in + the function call. */ +#define R_SH_USES 27 /* .uses pseudo-op */ + +/* The COUNT reloc type is used for relaxing. The assembler will + generate COUNT relocs for addresses referred to by the register + loads associated with USES relocs. The r_offset field of the COUNT + reloc holds the number of times the address is referenced in the + object file. */ +#define R_SH_COUNT 28 /* Count of constant pool uses */ + +/* The ALIGN reloc type is used for relaxing. The r_offset field is + the power of two to which subsequent portions of the object file + must be aligned. */ +#define R_SH_ALIGN 29 /* .align pseudo-op */ + +/* The CODE and DATA reloc types are used for aligning load and store + instructions. The assembler will generate a CODE reloc before a + block of instructions. It will generate a DATA reloc before data. + A section should be processed assuming it contains data, unless a + CODE reloc is seen. The only relevant pieces of information in the + CODE and DATA relocs are the section and the address. The symbol + and offset are meaningless. */ +#define R_SH_CODE 30 /* start of code */ +#define R_SH_DATA 31 /* start of data */ + +/* The LABEL reloc type is used for aligning load and store + instructions. The assembler will generate a LABEL reloc for each + label within a block of instructions. This permits the linker to + avoid swapping instructions which are the targets of branches. */ +#define R_SH_LABEL 32 /* label */ + +/* NB: R_SH_SWITCH8 is 33 */ + +#define R_SH_LOOP_START 34 +#define R_SH_LOOP_END 35 diff --git a/external/gpl3/gdb/dist/include/coff/sparc.h b/external/gpl3/gdb/dist/include/coff/sparc.h new file mode 100644 index 000000000000..fa94c5f795ac --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/sparc.h @@ -0,0 +1,156 @@ +/* coff information for Sparc. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is an amalgamation of several standard include files that + define coff format, such as filehdr.h, aouthdr.h, and so forth. In + addition, all datatypes have been translated into character arrays of + (presumed) equivalent size. This is necessary so that this file can + be used with different systems while still yielding the same results. */ + +#define L_LNNO_SIZE 2 +#define DO_NOT_DEFINE_SYMENT +#define DO_NOT_DEFINE_AUXENT +#include "coff/external.h" + +#define F_RELFLG (0x0001) /* relocation info stripped */ +#define F_EXEC (0x0002) /* file is executable */ +#define F_LNNO (0x0004) /* line numbers stripped */ +#define F_LSYMS (0x0008) /* local symbols stripped */ + +#define SPARCMAGIC (0540) + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC (0415) + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* More names of "special" sections. */ + +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN (8) /* # characters in a symbol name */ +#define E_FILNMLEN (14) /* # characters in a file name */ +#define E_DIMNUM (4) /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; +#if 0 /* of doubtful value */ + char e_nptr[2][4]; + struct { + char e_leading_zero[1]; + char e_dbx_type[1]; + char e_dbx_desc[2]; + } e_dbx; +#endif + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char padding[2]; +}; + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* .tv section info (in auxent of sym .tv)) */ + + char x_fill[20]; /* forces to 20-byte size */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_spare[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/external/gpl3/gdb/dist/include/coff/sym.h b/external/gpl3/gdb/dist/include/coff/sym.h new file mode 100644 index 000000000000..76204af59adc --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/sym.h @@ -0,0 +1,484 @@ +/* Declarations of internal format of MIPS ECOFF symbols. + Originally contributed by MIPS Computer Systems and Third Eye Software. + Changes contributed by Cygnus Support are in the public domain. + + This file is just aggregated with the files that make up the GNU + release; it is not considered part of GAS, GDB, or other GNU + programs. */ + +/* + * |-----------------------------------------------------------| + * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.| + * | MIPS Computer Systems, Inc. grants reproduction and use | + * | rights to all parties, PROVIDED that this comment is | + * | maintained in the copy. | + * |-----------------------------------------------------------| + */ +#ifndef _SYM_H +#define _SYM_H + +/* (C) Copyright 1984 by Third Eye Software, Inc. + * + * Third Eye Software, Inc. grants reproduction and use rights to + * all parties, PROVIDED that this comment is maintained in the copy. + * + * Third Eye makes no claims about the applicability of this + * symbol table to a particular use. + */ + +/* + * This file contains the definition of the Third Eye Symbol Table. + * + * Symbols are assumed to be in 'encounter order' - i.e. the order that + * the things they represent were encountered by the compiler/assembler/loader. + * EXCEPT for globals! These are assumed to be bunched together, + * probably right after the last 'normal' symbol. Globals ARE sorted + * in ascending order. + * + * ----------------------------------------------------------------------- + * A brief word about Third Eye naming/use conventions: + * + * All arrays and index's are 0 based. + * All "ifooMax" values are the highest legal value PLUS ONE. This makes + * them good for allocating arrays, etc. All checks are "ifoo < ifooMax". + * + * "isym" Index into the SYMbol table. + * "ipd" Index into the Procedure Descriptor array. + * "ifd" Index into the File Descriptor array. + * "iss" Index into String Space. + * "cb" Count of Bytes. + * "rgPd" array whose domain is "0..ipdMax-1" and RanGe is PDR. + * "rgFd" array whose domain is "0..ifdMax-1" and RanGe is FDR. + */ + + +/* + * Symbolic Header (HDR) structure. + * As long as all the pointers are set correctly, + * we don't care WHAT order the various sections come out in! + * + * A file produced solely for the use of CDB will probably NOT have + * any instructions or data areas in it, as these are available + * in the original. + */ + +typedef struct { + short magic; /* to verify validity of the table */ + short vstamp; /* version stamp */ + long ilineMax; /* number of line number entries */ + bfd_vma cbLine; /* number of bytes for line number entries */ + bfd_vma cbLineOffset; /* offset to start of line number entries*/ + long idnMax; /* max index into dense number table */ + bfd_vma cbDnOffset; /* offset to start dense number table */ + long ipdMax; /* number of procedures */ + bfd_vma cbPdOffset; /* offset to procedure descriptor table */ + long isymMax; /* number of local symbols */ + bfd_vma cbSymOffset; /* offset to start of local symbols*/ + long ioptMax; /* max index into optimization symbol entries */ + bfd_vma cbOptOffset; /* offset to optimization symbol entries */ + long iauxMax; /* number of auxillary symbol entries */ + bfd_vma cbAuxOffset; /* offset to start of auxillary symbol entries*/ + long issMax; /* max index into local strings */ + bfd_vma cbSsOffset; /* offset to start of local strings */ + long issExtMax; /* max index into external strings */ + bfd_vma cbSsExtOffset; /* offset to start of external strings */ + long ifdMax; /* number of file descriptor entries */ + bfd_vma cbFdOffset; /* offset to file descriptor table */ + long crfd; /* number of relative file descriptor entries */ + bfd_vma cbRfdOffset; /* offset to relative file descriptor table */ + long iextMax; /* max index into external symbols */ + bfd_vma cbExtOffset; /* offset to start of external symbol entries*/ + /* If you add machine dependent fields, add them here */ + } HDRR, *pHDRR; +#define cbHDRR sizeof(HDRR) +#define hdrNil ((pHDRR)0) + +/* + * The FDR and PDR structures speed mapping of address <-> name. + * They are sorted in ascending memory order and are kept in + * memory by CDB at runtime. + */ + +/* + * File Descriptor + * + * There is one of these for EVERY FILE, whether compiled with + * full debugging symbols or not. The name of a file should be + * the path name given to the compiler. This allows the user + * to simply specify the names of the directories where the COMPILES + * were done, and we will be able to find their files. + * A field whose comment starts with "R - " indicates that it will be + * setup at runtime. + */ +typedef struct fdr { + bfd_vma adr; /* memory address of beginning of file */ + long rss; /* file name (of source, if known) */ + long issBase; /* file's string space */ + bfd_vma cbSs; /* number of bytes in the ss */ + long isymBase; /* beginning of symbols */ + long csym; /* count file's of symbols */ + long ilineBase; /* file's line symbols */ + long cline; /* count of file's line symbols */ + long ioptBase; /* file's optimization entries */ + long copt; /* count of file's optimization entries */ + unsigned short ipdFirst;/* start of procedures for this file */ + short cpd; /* count of procedures for this file */ + long iauxBase; /* file's auxiliary entries */ + long caux; /* count of file's auxiliary entries */ + long rfdBase; /* index into the file indirect table */ + long crfd; /* count file indirect entries */ + unsigned lang: 5; /* language for this file */ + unsigned fMerge : 1; /* whether this file can be merged */ + unsigned fReadin : 1; /* true if it was read in (not just created) */ + unsigned fBigendian : 1;/* if set, was compiled on big endian machine */ + /* aux's will be in compile host's sex */ + unsigned glevel : 2; /* level this file was compiled with */ + unsigned reserved : 22; /* reserved for future use */ + bfd_vma cbLineOffset; /* byte offset from header for this file ln's */ + bfd_vma cbLine; /* size of lines for this file */ + } FDR, *pFDR; +#define cbFDR sizeof(FDR) +#define fdNil ((pFDR)0) +#define ifdNil -1 +#define ifdTemp 0 +#define ilnNil -1 + + +/* + * Procedure Descriptor + * + * There is one of these for EVERY TEXT LABEL. + * If a procedure is in a file with full symbols, then isym + * will point to the PROC symbols, else it will point to the + * global symbol for the label. + */ + +typedef struct pdr { + bfd_vma adr; /* memory address of start of procedure */ + long isym; /* start of local symbol entries */ + long iline; /* start of line number entries*/ + long regmask; /* save register mask */ + long regoffset; /* save register offset */ + long iopt; /* start of optimization symbol entries*/ + long fregmask; /* save floating point register mask */ + long fregoffset; /* save floating point register offset */ + long frameoffset; /* frame size */ + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + long lnLow; /* lowest line in the procedure */ + long lnHigh; /* highest line in the procedure */ + bfd_vma cbLineOffset; /* byte offset for this procedure from the fd base */ + /* These fields are new for 64 bit ECOFF. */ + unsigned gp_prologue : 8; /* byte size of GP prologue */ + unsigned gp_used : 1; /* true if the procedure uses GP */ + unsigned reg_frame : 1; /* true if register frame procedure */ + unsigned prof : 1; /* true if compiled with -pg */ + unsigned reserved : 13; /* reserved: must be zero */ + unsigned localoff : 8; /* offset of local variables from vfp */ + } PDR, *pPDR; +#define cbPDR sizeof(PDR) +#define pdNil ((pPDR) 0) +#define ipdNil -1 + +/* + * The structure of the runtime procedure descriptor created by the loader + * for use by the static exception system. + */ +/* + * If 0'd out because exception_info chokes Visual C++ and because there + * don't seem to be any references to this structure elsewhere in gdb. + */ +#if 0 +typedef struct runtime_pdr { + bfd_vma adr; /* memory address of start of procedure */ + long regmask; /* save register mask */ + long regoffset; /* save register offset */ + long fregmask; /* save floating point register mask */ + long fregoffset; /* save floating point register offset */ + long frameoffset; /* frame size */ + short framereg; /* frame pointer register */ + short pcreg; /* offset or reg of return pc */ + long irpss; /* index into the runtime string table */ + long reserved; + struct exception_info *exception_info;/* pointer to exception array */ +} RPDR, *pRPDR; +#define cbRPDR sizeof(RPDR) +#define rpdNil ((pRPDR) 0) +#endif + +/* + * Line Numbers + * + * Line Numbers are segregated from the normal symbols because they + * are [1] smaller , [2] are of no interest to your + * average loader, and [3] are never needed in the middle of normal + * scanning and therefore slow things down. + * + * By definition, the first LINER for any given procedure will have + * the first line of a procedure and represent the first address. + */ + +typedef long LINER, *pLINER; +#define lineNil ((pLINER)0) +#define cbLINER sizeof(LINER) +#define ilineNil -1 + + + +/* + * The Symbol Structure (GFW, to those who Know!) + */ + +typedef struct { + long iss; /* index into String Space of name */ + bfd_vma value; /* value of symbol */ + unsigned st : 6; /* symbol type */ + unsigned sc : 5; /* storage class - text, data, etc */ + unsigned reserved : 1; /* reserved */ + unsigned index : 20; /* index into sym/aux table */ + } SYMR, *pSYMR; +#define symNil ((pSYMR)0) +#define cbSYMR sizeof(SYMR) +#define isymNil -1 +#define indexNil 0xfffff +#define issNil -1 +#define issNull 0 + + +/* The following converts a memory resident string to an iss. + * This hack is recognized in SbFIss, in sym.c of the debugger. + */ +#define IssFSb(sb) (0x80000000 | ((unsigned long)(sb))) + +/* E X T E R N A L S Y M B O L R E C O R D + * + * Same as the SYMR except it contains file context to determine where + * the index is. + */ +typedef struct ecoff_extr { + unsigned jmptbl:1; /* symbol is a jump table entry for shlibs */ + unsigned cobol_main:1; /* symbol is a cobol main procedure */ + unsigned weakext:1; /* symbol is weak external */ + unsigned reserved:13; /* reserved for future use */ + int ifd; /* where the iss and index fields point into */ + SYMR asym; /* symbol for the external */ + } EXTR, *pEXTR; +#define extNil ((pEXTR)0) +#define cbEXTR sizeof(EXTR) + + +/* A U X I L L A R Y T Y P E I N F O R M A T I O N */ + +/* + * Type Information Record + */ +typedef struct { + unsigned fBitfield : 1; /* set if bit width is specified */ + unsigned continued : 1; /* indicates additional TQ info in next AUX */ + unsigned bt : 6; /* basic type */ + unsigned tq4 : 4; + unsigned tq5 : 4; + /* ---- 16 bit boundary ---- */ + unsigned tq0 : 4; + unsigned tq1 : 4; /* 6 type qualifiers - tqPtr, etc. */ + unsigned tq2 : 4; + unsigned tq3 : 4; + } TIR, *pTIR; +#define cbTIR sizeof(TIR) +#define tiNil ((pTIR)0) +#define itqMax 6 + +/* + * Relative symbol record + * + * If the rfd field is 4095, the index field indexes into the global symbol + * table. + */ + +typedef struct { + unsigned rfd : 12; /* index into the file indirect table */ + unsigned index : 20; /* index int sym/aux/iss tables */ + } RNDXR, *pRNDXR; +#define cbRNDXR sizeof(RNDXR) +#define rndxNil ((pRNDXR)0) + +/* dense numbers or sometimes called block numbers are stored in this type, + * a rfd of 0xffffffff is an index into the global table. + */ +typedef struct { + unsigned long rfd; /* index into the file table */ + unsigned long index; /* index int sym/aux/iss tables */ + } DNR, *pDNR; +#define cbDNR sizeof(DNR) +#define dnNil ((pDNR)0) + + + +/* + * Auxillary information occurs only if needed. + * It ALWAYS occurs in this order when present. + + isymMac used by stProc only + TIR type info + TIR additional TQ info (if first TIR was not enough) + rndx if (bt == btStruct,btUnion,btEnum,btSet,btRange, + btTypedef): + rsym.index == iaux for btSet or btRange + else rsym.index == isym + dimLow btRange, btSet + dimMac btRange, btSet + rndx0 As many as there are tq arrays + dimLow0 + dimHigh0 + ... + rndxMax-1 + dimLowMax-1 + dimHighMax-1 + width in bits if (bit field), width in bits. + */ +#define cAuxMax (6 + (idimMax*3)) + +/* a union of all possible info in the AUX universe */ +typedef union { + TIR ti; /* type information record */ + RNDXR rndx; /* relative index into symbol table */ + long dnLow; /* low dimension */ + long dnHigh; /* high dimension */ + long isym; /* symbol table index (end of proc) */ + long iss; /* index into string space (not used) */ + long width; /* width for non-default sized struc fields */ + long count; /* count of ranges for variant arm */ + } AUXU, *pAUXU; +#define cbAUXU sizeof(AUXU) +#define auxNil ((pAUXU)0) +#define iauxNil -1 + + +/* + * Optimization symbols + * + * Optimization symbols contain some overlap information with the normal + * symbol table. In particular, the proc information + * is somewhat redundant but necessary to easily find the other information + * present. + * + * All of the offsets are relative to the beginning of the last otProc + */ + +typedef struct { + unsigned ot: 8; /* optimization type */ + unsigned value: 24; /* address where we are moving it to */ + RNDXR rndx; /* points to a symbol or opt entry */ + unsigned long offset; /* relative offset this occured */ + } OPTR, *pOPTR; +#define optNil ((pOPTR) 0) +#define cbOPTR sizeof(OPTR) +#define ioptNil -1 + +/* + * File Indirect + * + * When a symbol is referenced across files the following procedure is used: + * 1) use the file index to get the File indirect entry. + * 2) use the file indirect entry to get the File descriptor. + * 3) add the sym index to the base of that file's sym table + * + */ + +typedef long RFDT, *pRFDT; +#define cbRFDT sizeof(RFDT) +#define rfdNil -1 + +/* + * The file indirect table in the mips loader is known as an array of FITs. + * This is done to keep the code in the loader readable in the area where + * these tables are merged. Note this is only a name change. + */ +typedef long FIT, *pFIT; +#define cbFIT sizeof(FIT) +#define ifiNil -1 +#define fiNil ((pFIT) 0) + +#ifdef _LANGUAGE_PASCAL +#define ifdNil -1 +#define ilnNil -1 +#define ipdNil -1 +#define ilineNil -1 +#define isymNil -1 +#define indexNil 16#fffff +#define issNil -1 +#define issNull 0 +#define itqMax 6 +#define iauxNil -1 +#define ioptNil -1 +#define rfdNil -1 +#define ifiNil -1 +#endif /* _LANGUAGE_PASCAL */ + + +/* Dense numbers + * + * Rather than use file index, symbol index pairs to represent symbols + * and globals, we use dense number so that they can be easily embeded + * in intermediate code and the programs that process them can + * use direct access tabls instead of hash table (which would be + * necesary otherwise because of the sparse name space caused by + * file index, symbol index pairs. Dense number are represented + * by RNDXRs. + */ + +/* + * The following table defines the meaning of each SYM field as + * a function of the "st". (scD/B == scData OR scBss) + * + * Note: the value "isymMac" is used by symbols that have the concept + * of enclosing a block of related information. This value is the + * isym of the first symbol AFTER the end associated with the primary + * symbol. For example if a procedure was at isym==90 and had an + * isymMac==155, the associated end would be at isym==154, and the + * symbol at 155 would probably (although not necessarily) be the + * symbol for the next procedure. This allows rapid skipping over + * internal information of various sorts. "stEnd"s ALWAYS have the + * isym of the primary symbol that started the block. + * + +ST SC VALUE INDEX +-------- ------ -------- ------ +stFile scText address isymMac +stLabel scText address --- +stGlobal scD/B address iaux +stStatic scD/B address iaux +stParam scAbs offset iaux +stLocal scAbs offset iaux +stProc scText address iaux (isymMac is first AUX) +stStaticProc scText address iaux (isymMac is first AUX) + +stMember scNil ordinal --- (if member of enum) + (mipsread thinks the case below has a bit, not byte, offset.) +stMember scNil byte offset iaux (if member of struct/union) +stMember scBits bit offset iaux (bit field spec) + +stBlock scText address isymMac (text block) + (the code seems to think that rather than scNil, we see scInfo for + the two cases below.) +stBlock scNil cb isymMac (struct/union member define) +stBlock scNil cMembers isymMac (enum member define) + + (New types added by SGI to simplify things:) +stStruct scInfo cb isymMac (struct type define) +stUnion scInfo cb isymMac (union type define) +stEnum scInfo cMembers isymMac (enum type define) + +stEnd scText address isymStart +stEnd scNil ------- isymStart (struct/union/enum) + +stTypedef scNil ------- iaux +stRegReloc sc??? value old register number +stForward sc??? new address isym to original symbol + +stConstant scInfo value --- (scalar) +stConstant scInfo iss --- (complex, e.g. string) + + * + */ +#endif diff --git a/external/gpl3/gdb/dist/include/coff/symconst.h b/external/gpl3/gdb/dist/include/coff/symconst.h new file mode 100644 index 000000000000..ac62ba22247b --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/symconst.h @@ -0,0 +1,184 @@ +/* Declarations of constants for internal format of MIPS ECOFF symbols. + Originally contributed by MIPS Computer Systems and Third Eye Software. + Changes contributed by Cygnus Support are in the public domain. + + This file is just aggregated with the files that make up the GNU + release; it is not considered part of GAS, GDB, or other GNU + programs. */ + +/* + * |-----------------------------------------------------------| + * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.| + * | MIPS Computer Systems, Inc. grants reproduction and use | + * | rights to all parties, PROVIDED that this comment is | + * | maintained in the copy. | + * |-----------------------------------------------------------| + */ + +/* (C) Copyright 1984 by Third Eye Software, Inc. + * + * Third Eye Software, Inc. grants reproduction and use rights to + * all parties, PROVIDED that this comment is maintained in the copy. + * + * Third Eye makes no claims about the applicability of this + * symbol table to a particular use. + */ + +/* glevels for field in FDR */ +#define GLEVEL_0 2 +#define GLEVEL_1 1 +#define GLEVEL_2 0 /* for upward compat reasons. */ +#define GLEVEL_3 3 + +/* magic number fo symheader */ +#define magicSym 0x7009 +/* The Alpha uses this value instead, for some reason. */ +#define magicSym2 0x1992 + +/* Language codes */ +#define langC 0 +#define langPascal 1 +#define langFortran 2 +#define langAssembler 3 /* one Assembley inst might map to many mach */ +#define langMachine 4 +#define langNil 5 +#define langAda 6 +#define langPl1 7 +#define langCobol 8 +#define langStdc 9 /* FIXME: Collides with SGI langCplusplus */ +#define langCplusplus 9 /* FIXME: Collides with langStdc */ +#define langCplusplusV2 10 /* SGI addition */ +#define langMax 11 /* maximum allowed 32 -- 5 bits */ + +/* The following are value definitions for the fields in the SYMR */ + +/* + * Storage Classes + */ + +#define scNil 0 +#define scText 1 /* text symbol */ +#define scData 2 /* initialized data symbol */ +#define scBss 3 /* un-initialized data symbol */ +#define scRegister 4 /* value of symbol is register number */ +#define scAbs 5 /* value of symbol is absolute */ +#define scUndefined 6 /* who knows? */ +#define scCdbLocal 7 /* variable's value is IN se->va.?? */ +#define scBits 8 /* this is a bit field */ +#define scCdbSystem 9 /* variable's value is IN CDB's address space */ +#define scDbx 9 /* overlap dbx internal use */ +#define scRegImage 10 /* register value saved on stack */ +#define scInfo 11 /* symbol contains debugger information */ +#define scUserStruct 12 /* address in struct user for current process */ +#define scSData 13 /* load time only small data */ +#define scSBss 14 /* load time only small common */ +#define scRData 15 /* load time only read only data */ +#define scVar 16 /* Var parameter (fortran,pascal) */ +#define scCommon 17 /* common variable */ +#define scSCommon 18 /* small common */ +#define scVarRegister 19 /* Var parameter in a register */ +#define scVariant 20 /* Variant record */ +#define scSUndefined 21 /* small undefined(external) data */ +#define scInit 22 /* .init section symbol */ +#define scBasedVar 23 /* Fortran or PL/1 ptr based var */ +#define scXData 24 /* exception handling data */ +#define scPData 25 /* Procedure section */ +#define scFini 26 /* .fini section */ +#define scRConst 27 /* .rconst section */ +#define scMax 32 + + +/* + * Symbol Types + */ + +#define stNil 0 /* Nuthin' special */ +#define stGlobal 1 /* external symbol */ +#define stStatic 2 /* static */ +#define stParam 3 /* procedure argument */ +#define stLocal 4 /* local variable */ +#define stLabel 5 /* label */ +#define stProc 6 /* " " Procedure */ +#define stBlock 7 /* beginnning of block */ +#define stEnd 8 /* end (of anything) */ +#define stMember 9 /* member (of anything - struct/union/enum */ +#define stTypedef 10 /* type definition */ +#define stFile 11 /* file name */ +#define stRegReloc 12 /* register relocation */ +#define stForward 13 /* forwarding address */ +#define stStaticProc 14 /* load time only static procs */ +#define stConstant 15 /* const */ +#define stStaParam 16 /* Fortran static parameters */ + /* These new symbol types have been recently added to SGI machines. */ +#define stStruct 26 /* Beginning of block defining a struct type */ +#define stUnion 27 /* Beginning of block defining a union type */ +#define stEnum 28 /* Beginning of block defining an enum type */ +#define stIndirect 34 /* Indirect type specification */ + /* Pseudo-symbols - internal to debugger */ +#define stStr 60 /* string */ +#define stNumber 61 /* pure number (ie. 4 NOR 2+2) */ +#define stExpr 62 /* 2+2 vs. 4 */ +#define stType 63 /* post-coersion SER */ +#define stMax 64 + +/* definitions for fields in TIR */ + +/* type qualifiers for ti.tq0 -> ti.(itqMax-1) */ +#define tqNil 0 /* bt is what you see */ +#define tqPtr 1 /* pointer */ +#define tqProc 2 /* procedure */ +#define tqArray 3 /* duh */ +#define tqFar 4 /* longer addressing - 8086/8 land */ +#define tqVol 5 /* volatile */ +#define tqConst 6 /* const */ +#define tqMax 8 + +/* basic types as seen in ti.bt */ +#define btNil 0 /* undefined (also, enum members) */ +#define btAdr 1 /* address - integer same size as pointer */ +#define btChar 2 /* character */ +#define btUChar 3 /* unsigned character */ +#define btShort 4 /* short */ +#define btUShort 5 /* unsigned short */ +#define btInt 6 /* int */ +#define btUInt 7 /* unsigned int */ +#define btLong 8 /* long */ +#define btULong 9 /* unsigned long */ +#define btFloat 10 /* float (real) */ +#define btDouble 11 /* Double (real) */ +#define btStruct 12 /* Structure (Record) */ +#define btUnion 13 /* Union (variant) */ +#define btEnum 14 /* Enumerated */ +#define btTypedef 15 /* defined via a typedef, isymRef points */ +#define btRange 16 /* subrange of int */ +#define btSet 17 /* pascal sets */ +#define btComplex 18 /* fortran complex */ +#define btDComplex 19 /* fortran double complex */ +#define btIndirect 20 /* forward or unnamed typedef */ +#define btFixedDec 21 /* Fixed Decimal */ +#define btFloatDec 22 /* Float Decimal */ +#define btString 23 /* Varying Length Character String */ +#define btBit 24 /* Aligned Bit String */ +#define btPicture 25 /* Picture */ +#define btVoid 26 /* void */ +#define btLongLong 27 /* long long */ +#define btULongLong 28 /* unsigned long long */ +#define btLong64 30 /* long (64-bit) */ +#define btULong64 31 /* unsigned long (64-bit) */ +#define btLongLong64 32 /* long long (64-bit) */ +#define btULongLong64 33 /* unsigned long long (64-bit) */ +#define btAdr64 34 /* address (64-bit) */ +#define btInt64 35 /* int (64-bit) */ +#define btUInt64 36 /* unsigned int (64-bit) */ +#define btMax 64 + +#if (_MFG == _MIPS) +/* optimization type codes */ +#define otNil 0 +#define otReg 1 /* move var to reg */ +#define otBlock 2 /* begin basic block */ +#define otProc 3 /* procedure */ +#define otInline 4 /* inline procedure */ +#define otEnd 5 /* whatever you started */ +#define otMax 6 /* KEEP UP TO DATE */ +#endif /* (_MFG == _MIPS) */ diff --git a/external/gpl3/gdb/dist/include/coff/ti.h b/external/gpl3/gdb/dist/include/coff/ti.h new file mode 100644 index 000000000000..61010a210868 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/ti.h @@ -0,0 +1,558 @@ +/* COFF information for TI COFF support. Definitions in this file should be + customized in a target-specific file, and then this file included (see + tic54x.h for an example). + + Copyright 2000, 2001, 2002, 2003, 2005, 2008, 2009, 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef COFF_TI_H +#define COFF_TI_H + +/* Note "coff/external.h is not used because TI adds extra fields to the structures. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2]; /* magic no. (TI COFF-specific) */ + }; + +/* COFF0 has magic number in f_magic, and omits f_target_id from the file + header; for later versions, f_magic is 0xC1 for COFF1 and 0xC2 for COFF2 + and the target-specific magic number is found in f_target_id */ + +#define TICOFF0MAGIC TI_TARGET_ID +#define TICOFF1MAGIC 0x00C1 +#define TICOFF2MAGIC 0x00C2 +#define TICOFF_AOUT_MAGIC 0x0108 /* magic number in optional header */ +#define TICOFF 1 /* customize coffcode.h */ + +/* The target_id field changes depending on the particular CPU target */ +/* for COFF0, the target id appeared in f_magic, where COFFX magic is now */ +#ifndef TI_TARGET_ID +#error "TI_TARGET_ID needs to be defined for your CPU" +#endif + +/* Which bfd_arch to use... */ +#ifndef TICOFF_TARGET_ARCH +#error "TICOFF_TARGET_ARCH needs to be defined for your CPU" +#endif + +#ifndef TICOFF_TARGET_MACHINE_GET +#define TICOFF_TARGET_MACHINE_GET(FLAGS) 0 +#endif + +#ifndef TICOFF_TARGET_MACHINE_SET +#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) +#endif + +/* Default to COFF2 for file output */ +#ifndef TICOFF_DEFAULT_MAGIC +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC +#endif + +/* This value is made available in the rare case where a bfd is unavailable */ +#ifndef OCTETS_PER_BYTE_POWER +#error "OCTETS_PER_BYTE_POWER not defined for this CPU" +#else +#define OCTETS_PER_BYTE (1<>8)&0xF) + +#define COFF0_P(ABFD) (bfd_coff_filhsz(ABFD) == FILHSZ_V0) +#define COFF2_P(ABFD) (bfd_coff_scnhsz(ABFD) != SCNHSZ_V01) + +#define COFF0_BADMAG(x) ((x).f_magic != TICOFF0MAGIC) +#define COFF1_BADMAG(x) ((x).f_magic != TICOFF1MAGIC || (x).f_target_id != TI_TARGET_ID) +#define COFF2_BADMAG(x) ((x).f_magic != TICOFF2MAGIC || (x).f_target_id != TI_TARGET_ID) + +/* we need to read/write an extra field in the coff file header */ +#ifndef COFF_ADJUST_FILEHDR_IN_POST +#define COFF_ADJUST_FILEHDR_IN_POST(abfd, src, dst) \ + do \ + { \ + if (!COFF0_P (abfd)) \ + ((struct internal_filehdr *)(dst))->f_target_id = \ + H_GET_16 (abfd, ((FILHDR *)(src))->f_target_id); \ + } \ + while (0) +#endif + +#ifndef COFF_ADJUST_FILEHDR_OUT_POST +#define COFF_ADJUST_FILEHDR_OUT_POST(abfd, src, dst) \ + do \ + { \ + if (!COFF0_P (abfd)) \ + H_PUT_16 (abfd, ((struct internal_filehdr *)(src))->f_target_id, \ + ((FILHDR *)(dst))->f_target_id); \ + } \ + while (0) +#endif + +#define FILHDR struct external_filehdr +#define FILHSZ 22 +#define FILHSZ_V0 20 /* COFF0 omits target_id field */ + +/* File header flags */ +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_VERS (0x0010) /* TMS320C4x code */ +/* F_LSYMS needs to be redefined in your source file */ +#define F_LSYMS_TICOFF (0x0010) /* normal COFF is 0x8 */ + +#define F_10 0x00 /* file built for TMS320C1x devices */ +#define F_20 0x10 /* file built for TMS320C2x devices */ +#define F_25 0x20 /* file built for TMS320C2x/C5x devices */ +#define F_LENDIAN 0x0100 /* 16 bits/word, LSB first */ +#define F_SYMMERGE 0x1000 /* duplicate symbols were removed */ + +/********************** OPTIONAL HEADER **********************/ + + +typedef struct +{ + char magic[2]; /* type of file (0x108) */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + +/********************** SECTION HEADER **********************/ +/* COFF0, COFF1 */ +struct external_scnhdr_v01 { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved */ + char s_page[1]; /* section page number (LOAD) */ +}; + +/* COFF2 */ +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_reserved[2]; /* reserved */ + char s_page[2]; /* section page number (LOAD) */ +}; + +/* + * Special section flags + */ + +/* TI COFF defines these flags; + STYP_CLINK: the section should be excluded from the final + linker output if there are no references found to any symbol in the section + STYP_BLOCK: the section should be blocked, i.e. if the section would cross + a page boundary, it is started at a page boundary instead. + TI COFF puts the section alignment power of two in the section flags + e.g. 2**N is alignment, flags |= (N & 0xF) << 8 +*/ +#define STYP_CLINK (0x4000) +#define STYP_BLOCK (0x1000) +#define STYP_ALIGN (0x0F00) /* TI COFF stores section alignment here */ + +#define SCNHDR_V01 struct external_scnhdr_v01 +#define SCNHDR struct external_scnhdr +#define SCNHSZ_V01 40 /* for v0 and v1 */ +#define SCNHSZ 48 + +/* COFF2 changes the offsets and sizes of these fields + Assume we're dealing with the COFF2 scnhdr structure, and adjust + accordingly. Note: The GNU C versions of some of these macros + are necessary in order to avoid compile time warnings triggered + gcc's array bounds checking. The PUT_SCNHDR_PAGE macro also has + the advantage on not evaluating LOC twice. */ + +#define GET_SCNHDR_NRELOC(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, LOC)) +#define PUT_SCNHDR_NRELOC(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, LOC)) +#ifdef __GNUC__ +#define GET_SCNHDR_NLNNO(ABFD, LOC) \ + ({ \ + int nlnno; \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + nlnno = H_GET_32 (ABFD, ptr); \ + else \ + nlnno = H_GET_16 (ABFD, ptr - 2); \ + nlnno; \ + }) +#define PUT_SCNHDR_NLNNO(ABFD, VAL, LOC) \ + do \ + { \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + H_PUT_32 (ABFD, VAL, ptr); \ + else \ + H_PUT_16 (ABFD, VAL, ptr - 2); \ + } \ + while (0) +#define GET_SCNHDR_FLAGS(ABFD, LOC) \ + ({ \ + int flags; \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + flags = H_GET_32 (ABFD, ptr); \ + else \ + flags = H_GET_16 (ABFD, ptr - 4); \ + flags; \ + }) +#define PUT_SCNHDR_FLAGS(ABFD, VAL, LOC) \ + do \ + { \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + H_PUT_32 (ABFD, VAL, ptr); \ + else \ + H_PUT_16 (ABFD, VAL, ptr - 4); \ + } \ + while (0) +#define GET_SCNHDR_PAGE(ABFD, LOC) \ + ({ \ + unsigned page; \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + page = H_GET_16 (ABFD, ptr); \ + else \ + page = (unsigned) H_GET_8 (ABFD, ptr - 7); \ + page; \ + }) +/* On output, make sure that the "reserved" field is zero. */ +#define PUT_SCNHDR_PAGE(ABFD, VAL, LOC) \ + do \ + { \ + char * ptr = (LOC); \ + if (COFF2_P (ABFD)) \ + H_PUT_16 (ABFD, VAL, ptr); \ + else \ + { \ + H_PUT_8 (ABFD, VAL, ptr - 7); \ + H_PUT_8 (ABFD, 0, ptr - 8); \ + } \ + } \ + while (0) +#else +#define GET_SCNHDR_NLNNO(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 2)) +#define PUT_SCNHDR_NLNNO(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 2)) +#define GET_SCNHDR_FLAGS(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 4)) +#define PUT_SCNHDR_FLAGS(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 4)) +#define GET_SCNHDR_PAGE(ABFD, LOC) \ + (COFF2_P (ABFD) ? H_GET_16 (ABFD, LOC) : (unsigned) H_GET_8 (ABFD, (LOC) - 7)) +/* On output, make sure that the "reserved" field is zero. */ +#define PUT_SCNHDR_PAGE(ABFD, VAL, LOC) \ + (COFF2_P (ABFD) \ + ? H_PUT_16 (ABFD, VAL, LOC) \ + : H_PUT_8 (ABFD, VAL, (LOC) - 7), H_PUT_8 (ABFD, 0, (LOC) - 8)) +#endif + + +/* TI COFF stores section size as number of bytes (address units, not octets), + so adjust to be number of octets, which is what BFD expects */ +#define GET_SCNHDR_SIZE(ABFD, SZP) \ + (H_GET_32 (ABFD, SZP) * bfd_octets_per_byte (ABFD)) +#define PUT_SCNHDR_SIZE(ABFD, SZ, SZP) \ + H_PUT_32 (ABFD, (SZ) / bfd_octets_per_byte (ABFD), SZP) + +#define COFF_ADJUST_SCNHDR_IN_POST(ABFD, EXT, INT) \ + do \ + { \ + ((struct internal_scnhdr *)(INT))->s_page = \ + GET_SCNHDR_PAGE (ABFD, ((SCNHDR *)(EXT))->s_page); \ + } \ + while (0) + +/* The entire scnhdr may not be assigned. + Ensure that everything is initialized. */ +#define COFF_ADJUST_SCNHDR_OUT_PRE(ABFD, INT, EXT) \ + do \ + { \ + memset((EXT), 0, sizeof (SCNHDR)); \ + } \ + while (0) + +/* The line number and reloc overflow checking in coff_swap_scnhdr_out in + coffswap.h doesn't use PUT_X for s_nlnno and s_nreloc. + Due to different sized v0/v1/v2 section headers, we have to re-write these + fields. + */ +#define COFF_ADJUST_SCNHDR_OUT_POST(ABFD, INT, EXT) \ + do \ + { \ + PUT_SCNHDR_NLNNO (ABFD, ((struct internal_scnhdr *)(INT))->s_nlnno, \ + ((SCNHDR *)(EXT))->s_nlnno); \ + PUT_SCNHDR_NRELOC (ABFD, ((struct internal_scnhdr *)(INT))->s_nreloc,\ + ((SCNHDR *)(EXT))->s_nreloc); \ + PUT_SCNHDR_FLAGS (ABFD, ((struct internal_scnhdr *)(INT))->s_flags, \ + ((SCNHDR *)(EXT))->s_flags); \ + PUT_SCNHDR_PAGE (ABFD, ((struct internal_scnhdr *)(INT))->s_page, \ + ((SCNHDR *)(EXT))->s_page); \ + } \ + while (0) + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" /* initialized C data */ +#define _SCONST ".const" /* constants */ +#define _SWITCH ".switch" /* switch tables */ +#define _STACK ".stack" /* C stack */ +#define _SYSMEM ".sysmem" /* used for malloc et al. syscalls */ + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +/* NOTE: this is what a local label looks like in assembly source; what it + looks like in COFF output is undefined */ +#define TICOFF_LOCAL_LABEL_P(NAME) \ +((NAME[0] == '$' && NAME[1] >= '0' && NAME[1] <= '9' && NAME[2] == '\0') \ + || NAME[strlen(NAME)-1] == '?') + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + +/* section lengths are in target bytes (not host bytes) */ +#define GET_SCN_SCNLEN(ABFD, EXT) \ + (H_GET_32 (ABFD, (EXT)->x_scn.x_scnlen) * bfd_octets_per_byte (ABFD)) +#define PUT_SCN_SCNLEN(ABFD, INT, EXT) \ + H_PUT_32 (ABFD, (INT) / bfd_octets_per_byte (ABFD), (EXT)->x_scn.x_scnlen) + +/* lnsz size is in bits in COFF file, in bytes in BFD */ +#define GET_LNSZ_SIZE(abfd, ext) \ + (H_GET_16 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) / (in_class != C_FIELD ? 8 : 1)) + +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + H_PUT_16 (abfd, ((in_class != C_FIELD) ? (in) * 8 : (in)), \ + ext->x_sym.x_misc.x_lnsz.x_size) + +/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes + Also put the load page flag of the section into the symbol value if it's an + address. */ +#ifndef NEEDS_PAGE +#define NEEDS_PAGE(X) 0 +#define PAGE_MASK 0 +#endif +#define COFF_ADJUST_SYM_IN_POST(ABFD, EXT, INT) \ + do \ + { \ + struct internal_syment *dst = (struct internal_syment *)(INT); \ + if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU) \ + dst->n_value /= 8; \ + else if (NEEDS_PAGE (dst->n_sclass)) { \ + asection *scn = coff_section_from_bfd_index (abfd, dst->n_scnum); \ + dst->n_value |= (scn->lma & PAGE_MASK); \ + } \ + } \ + while (0) + +#define COFF_ADJUST_SYM_OUT_POST(ABFD, INT, EXT) \ + do \ + { \ + struct internal_syment *src = (struct internal_syment *)(INT); \ + SYMENT *dst = (SYMENT *)(EXT); \ + if (src->n_sclass == C_MOU || src->n_sclass == C_MOS) \ + H_PUT_32 (abfd, src->n_value * 8, dst->e_value); \ + else if (NEEDS_PAGE (src->n_sclass)) { \ + H_PUT_32 (abfd, src->n_value &= ~PAGE_MASK, dst->e_value); \ + } \ + } \ + while (0) + +/* Detect section-relative absolute symbols so they get flagged with a sym + index of -1. +*/ +#define SECTION_RELATIVE_ABSOLUTE_SYMBOL_P(RELOC, SECT) \ + ((*(RELOC)->sym_ptr_ptr)->section->output_section == (SECT) \ + && (RELOC)->howto->name[0] == 'A') + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc_v0 +{ + char r_vaddr[4]; + char r_symndx[2]; + char r_reserved[2]; + char r_type[2]; +}; + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; /* extended pmad byte for COFF2 */ + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ_V0 10 /* FIXME -- coffcode.h needs fixing */ +#define RELSZ 12 /* for COFF1/2 */ + +/* various relocation types. */ +#define R_ABS 0x0000 /* no relocation */ +#define R_REL13 0x002A /* 13-bit direct reference (???) */ +#define R_PARTLS7 0x0028 /* 7 LSBs of an address */ +#define R_PARTMS9 0x0029 /* 9MSBs of an address */ +#define R_EXTWORD 0x002B /* 23-bit direct reference */ +#define R_EXTWORD16 0x002C /* 16-bit direct reference to 23-bit addr*/ +#define R_EXTWORDMS7 0x002D /* upper 7 bits of 23-bit address */ + +#endif /* COFF_TI_H */ diff --git a/external/gpl3/gdb/dist/include/coff/tic30.h b/external/gpl3/gdb/dist/include/coff/tic30.h new file mode 100644 index 000000000000..4f7776a430fd --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/tic30.h @@ -0,0 +1,51 @@ +/* coff information for Texas Instruments TMS320C3X + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define TIC30MAGIC 0xC000 + +#define TIC30BADMAG(x) (((x).f_magic != TIC30MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* TMS320C30 relocation types. */ + +#define R_TIC30_ABS16 0x100 /* 16 bit absolute. */ +#define R_TIC30_ABS24 0x101 /* 24 bit absolute. */ +#define R_TIC30_ABS32 0x102 /* 32 bit absolute. */ +#define R_TIC30_LDP 0x103 /* LDP bits 23-16 to 7-0. */ +#define R_TIC30_PC16 0x104 /* 16 bit pc relative. */ diff --git a/external/gpl3/gdb/dist/include/coff/tic4x.h b/external/gpl3/gdb/dist/include/coff/tic4x.h new file mode 100644 index 000000000000..1eb3e26bfc11 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/tic4x.h @@ -0,0 +1,47 @@ +/* TI COFF information for Texas Instruments TMS320C4X/C3X. + This file customizes the settings in coff/ti.h. + + Copyright 2002, 2003, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef COFF_TIC4X_H +#define COFF_TIC4X_H + +#define TIC4X_TARGET_ID 0x0093 +/* Octets per byte, as a power of two. */ +#define TI_TARGET_ID TIC4X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 2 +/* Add to howto to get absolute/sect-relative version. */ +#define HOWTO_BANK 6 +#define TICOFF_TARGET_ARCH bfd_arch_tic4x +/* We use COFF2. */ +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC + +#define TICOFF_TARGET_MACHINE_GET(FLAGS) \ + (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x) + +#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \ + do \ + { \ + if ((MACHINE) == bfd_mach_tic4x) \ + *(FLAGSP) |= F_VERS; \ + } \ + while (0) + +#include "coff/ti.h" + +#endif /* COFF_TIC4X_H */ diff --git a/external/gpl3/gdb/dist/include/coff/tic54x.h b/external/gpl3/gdb/dist/include/coff/tic54x.h new file mode 100644 index 000000000000..c61f1f20d0dc --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/tic54x.h @@ -0,0 +1,60 @@ +/* TI COFF information for Texas Instruments TMS320C54X. + This file customizes the settings in coff/ti.h. + + Copyright 2000, 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef COFF_TIC54X_H +#define COFF_TIC54X_H + +#define TIC54X_TARGET_ID 0x98 +#define TIC54XALGMAGIC 0x009B /* c54x algebraic assembler output */ +#define TIC5X_TARGET_ID 0x92 +#define TI_TARGET_ID TIC54X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 1 /* octets per byte, as a power of two */ +#define HOWTO_BANK 6 /* add to howto to get absolute/sect-relative version */ +#define TICOFF_TARGET_ARCH bfd_arch_tic54x +#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */ + +/* Page macros + + The first GDB port requires flags in its remote memory access commands to + distinguish between data/prog space. Hopefully we can make this go away + eventually. Stuff the page in the upper bits of a 32-bit address, since + the c5x family only uses 16 or 23 bits. + + c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has + 23-bit program addresses. Make sure the page flags don't interfere. + These flags are used by GDB to identify the destination page for + addresses. +*/ + +/* Recognized load pages (by common convention). */ +#define PG_PROG 0x0 /* PROG page */ +#define PG_DATA 0x1 /* DATA page */ +#define PG_IO 0x2 /* I/O page */ + +/** Indicate whether the given storage class requires a page flag. */ +#define NEEDS_PAGE(X) ((X)==C_EXT) +#define PAGE_MASK 0xFF000000 +#define ADDR_MASK 0x00FFFFFF +#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24) +#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF) + +#include "coff/ti.h" + +#endif /* COFF_TIC54X_H */ diff --git a/external/gpl3/gdb/dist/include/coff/tic80.h b/external/gpl3/gdb/dist/include/coff/tic80.h new file mode 100644 index 000000000000..44f873ef32d1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/tic80.h @@ -0,0 +1,123 @@ +/* coff information for TI TMS320C80 (MVP) + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DO_NOT_DEFINE_FILHDR +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2];/* target id (TIc80 specific) */ +}; + +#define TIC80_ARCH_MAGIC 0x0C1 /* Goes in the file header magic number field */ +#define TIC80_TARGET_ID 0x95 /* Goes in the target id field */ + +#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 22 + +#define TIC80_AOUTHDR_MAGIC 0x108 /* Goes in the optional file header magic number field */ + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved (TIc80 specific) */ + char s_mempage[1]; /* memory page number (TIc80) */ +}; + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" +#define _CONST ".const" +#define _SWITCH ".switch" +#define _STACK ".stack" +#define _SYSMEM ".sysmem" + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* FIXME - need to correlate external_auxent with + TIc80 Code Generation Tools User's Guide, CG:A-25 */ + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +/* TIc80 relocation types. */ + +#define R_ABS 0x00 /* Absolute address - no relocation */ +#define R_RELLONGX 0x11 /* PP: 32 bits, direct */ +#define R_PPBASE 0x34 /* PP: Global base address type */ +#define R_PPLBASE 0x35 /* PP: Local base address type */ +#define R_PP15 0x38 /* PP: Global 15 bit offset */ +#define R_PP15W 0x39 /* PP: Global 15 bit offset divided by 4 */ +#define R_PP15H 0x3A /* PP: Global 15 bit offset divided by 2 */ +#define R_PP16B 0x3B /* PP: Global 16 bit offset for bytes */ +#define R_PPL15 0x3C /* PP: Local 15 bit offset */ +#define R_PPL15W 0x3D /* PP: Local 15 bit offset divided by 4 */ +#define R_PPL15H 0x3E /* PP: Local 15 bit offset divided by 2 */ +#define R_PPL16B 0x3F /* PP: Local 16 bit offset for bytes */ +#define R_PPN15 0x40 /* PP: Global 15 bit negative offset */ +#define R_PPN15W 0x41 /* PP: Global 15 bit negative offset divided by 4 */ +#define R_PPN15H 0x42 /* PP: Global 15 bit negative offset divided by 2 */ +#define R_PPN16B 0x43 /* PP: Global 16 bit negative byte offset */ +#define R_PPLN15 0x44 /* PP: Local 15 bit negative offset */ +#define R_PPLN15W 0x45 /* PP: Local 15 bit negative offset divided by 4 */ +#define R_PPLN15H 0x46 /* PP: Local 15 bit negative offset divided by 2 */ +#define R_PPLN16B 0x47 /* PP: Local 16 bit negative byte offset */ +#define R_MPPCR15W 0x4E /* MP: 15 bit PC-relative divided by 4 */ +#define R_MPPCR 0x4F /* MP: 32 bit PC-relative divided by 4 */ diff --git a/external/gpl3/gdb/dist/include/coff/w65.h b/external/gpl3/gdb/dist/include/coff/w65.h new file mode 100644 index 000000000000..31d9609300c6 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/w65.h @@ -0,0 +1,47 @@ +/* coff information for WDC 65816 + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define W65MAGIC 0x6500 + +#define W65BADMAG(x) (((x).f_magic != W65MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the w65 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/external/gpl3/gdb/dist/include/coff/we32k.h b/external/gpl3/gdb/dist/include/coff/we32k.h new file mode 100644 index 000000000000..3787dd27b25c --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/we32k.h @@ -0,0 +1,62 @@ +/* coff information for we32k + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_BM32B (0020000) +#define F_BM32MAU (0040000) + +#define WE32KMAGIC 0x170 /* we32k sans transfer vector */ +#define FBOMAGIC 0x170 /* we32k sans transfer vector */ +#define MTVMAGIC 0x171 /* we32k with transfer vector */ +#define RBOMAGIC 0x172 /* reserved */ +#define WE32KBADMAG(x) ( ((x).f_magic != WE32KMAGIC) \ + && ((x).f_magic != FBOMAGIC) \ + && ((x).f_magic != RBOMAGIC) \ + && ((x).f_magic != MTVMAGIC)) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/external/gpl3/gdb/dist/include/coff/x86_64.h b/external/gpl3/gdb/dist/include/coff/x86_64.h new file mode 100644 index 000000000000..fcd44c8e89e2 --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/x86_64.h @@ -0,0 +1,57 @@ +/* COFF information for AMD 64. + Copyright 2006, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. + + Written by Kai Tietz, OneVision Software GmbH&CoKg. */ + +#define L_LNNO_SIZE 2 +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT + +#include "coff/external.h" + +#define COFF_PAGE_SIZE 0x1000 + +#define AMD64MAGIC 0x8664 + +#define AMD64BADMAG(x) ((x).f_magic != AMD64MAGIC) +#define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b + +#define OMAGIC 0404 /* Object files, eg as output. */ +#define ZMAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC /* Demand load format, eg normal ld output 0x10b. */ +#define STMAGIC 0401 /* Target shlib. */ +#define SHMAGIC 0443 /* Host shlib. */ + +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h. */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/* Relocation directives. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 diff --git a/external/gpl3/gdb/dist/include/coff/xcoff.h b/external/gpl3/gdb/dist/include/coff/xcoff.h new file mode 100644 index 000000000000..dd157d32f29a --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/xcoff.h @@ -0,0 +1,596 @@ +/* Internal format of XCOFF object file data structures for BFD. + + Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, + 2009, 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor , Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _INTERNAL_XCOFF_H +#define _INTERNAL_XCOFF_H + +/* Linker */ + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _PAD ".pad" +#define _LOADER ".loader" +#define _EXCEPT ".except" +#define _TYPCHK ".typchk" + +/* XCOFF uses a special .loader section with type STYP_LOADER. */ +#define STYP_LOADER 0x1000 + +/* XCOFF uses a special .debug section with type STYP_DEBUG. */ +#define STYP_DEBUG 0x2000 + +/* XCOFF handles line number or relocation overflow by creating + another section header with STYP_OVRFLO set. */ +#define STYP_OVRFLO 0x8000 + +/* Specifies an exception section. A section of this type provides + information to identify the reason that a trap or ececptin occured within + and executable object program */ +#define STYP_EXCEPT 0x0100 + +/* Specifies a type check section. A section of this type contains parameter + argument type check strings used by the AIX binder. */ +#define STYP_TYPCHK 0x4000 + +#define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */ +#define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */ +#define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */ + +/* XCOFF relocation types. + The relocations are described in the function + xcoff[64]_ppc_relocate_section in coff64-rs6000.c and coff-rs6000.c */ + +#define R_POS (0x00) +#define R_NEG (0x01) +#define R_REL (0x02) +#define R_TOC (0x03) +#define R_RTB (0x04) +#define R_GL (0x05) +#define R_TCL (0x06) +#define R_BA (0x08) +#define R_BR (0x0a) +#define R_RL (0x0c) +#define R_RLA (0x0d) +#define R_REF (0x0f) +#define R_TRL (0x12) +#define R_TRLA (0x13) +#define R_RRTBI (0x14) +#define R_RRTBA (0x15) +#define R_CAI (0x16) +#define R_CREL (0x17) +#define R_RBA (0x18) +#define R_RBAC (0x19) +#define R_RBR (0x1a) +#define R_RBRC (0x1b) + +/* Storage class #defines, from /usr/include/storclass.h that are not already + defined in internal.h */ + +/* Comment string in .info section */ +#define C_INFO 110 + +/* Auxillary Symbol Entries */ + +/* x_smtyp values: */ +#define SMTYP_ALIGN(x) ((x) >> 3) /* log2 of alignment */ +#define SMTYP_SMTYP(x) ((x) & 0x7) /* symbol type */ +/* Symbol type values: */ +#define XTY_ER 0 /* External reference */ +#define XTY_SD 1 /* Csect definition */ +#define XTY_LD 2 /* Label definition */ +#define XTY_CM 3 /* .BSS */ +#define XTY_EM 4 /* Error message */ +#define XTY_US 5 /* "Reserved for internal use" */ + +/* x_smclas values: */ +#define XMC_PR 0 /* Read-only program code */ +#define XMC_RO 1 /* Read-only constant */ +#define XMC_DB 2 /* Read-only debug dictionary table */ +#define XMC_TC 3 /* Read-write general TOC entry */ +#define XMC_UA 4 /* Read-write unclassified */ +#define XMC_RW 5 /* Read-write data */ +#define XMC_GL 6 /* Read-only global linkage */ +#define XMC_XO 7 /* Read-only extended operation */ +#define XMC_SV 8 /* Read-only supervisor call */ +#define XMC_BS 9 /* Read-write BSS */ +#define XMC_DS 10 /* Read-write descriptor csect */ +#define XMC_UC 11 /* Read-write unnamed Fortran common */ +#define XMC_TI 12 /* Read-only traceback index csect */ +#define XMC_TB 13 /* Read-only traceback table csect */ +/* 14 ??? */ +#define XMC_TC0 15 /* Read-write TOC anchor */ +#define XMC_TD 16 /* Read-write data in TOC */ +#define XMC_SV64 17 /* Read-only 64 bit supervisor call */ +#define XMC_SV3264 18 /* Read-only 32 or 64 bit supervisor call */ + +/* The ldhdr structure. This appears at the start of the .loader + section. */ + +struct internal_ldhdr +{ + /* The version number: + 1 : 32 bit + 2 : 64 bit */ + unsigned long l_version; + + /* The number of symbol table entries. */ + bfd_size_type l_nsyms; + + /* The number of relocation table entries. */ + bfd_size_type l_nreloc; + + /* The length of the import file string table. */ + bfd_size_type l_istlen; + + /* The number of import files. */ + bfd_size_type l_nimpid; + + /* The offset from the start of the .loader section to the first + entry in the import file table. */ + bfd_size_type l_impoff; + + /* The length of the string table. */ + bfd_size_type l_stlen; + + /* The offset from the start of the .loader section to the first + entry in the string table. */ + bfd_size_type l_stoff; + + /* The offset to start of the symbol table, only in XCOFF64 */ + bfd_vma l_symoff; + + /* The offset to the start of the relocation table, only in XCOFF64 */ + bfd_vma l_rldoff; +}; + +/* The ldsym structure. This is used to represent a symbol in the + .loader section. */ + +struct internal_ldsym +{ + union + { + /* The symbol name if <= SYMNMLEN characters. */ + char _l_name[SYMNMLEN]; + struct + { + /* Zero if the symbol name is more than SYMNMLEN characters. */ + long _l_zeroes; + + /* The offset in the string table if the symbol name is more + than SYMNMLEN characters. */ + long _l_offset; + } + _l_l; + } + _l; + + /* The symbol value. */ + bfd_vma l_value; + + /* The symbol section number. */ + short l_scnum; + + /* The symbol type and flags. */ + char l_smtype; + + /* The symbol storage class. */ + char l_smclas; + + /* The import file ID. */ + bfd_size_type l_ifile; + + /* Offset to the parameter type check string. */ + bfd_size_type l_parm; +}; + +/* These flags are for the l_smtype field (the lower three bits are an + XTY_* value). */ + +/* Imported symbol. */ +#define L_IMPORT (0x40) +/* Entry point. */ +#define L_ENTRY (0x20) +/* Exported symbol. */ +#define L_EXPORT (0x10) +/* Weak symbol. */ +#define L_WEAK (0x08) + +/* The ldrel structure. This is used to represent a reloc in the + .loader section. */ + +struct internal_ldrel +{ + /* The reloc address. */ + bfd_vma l_vaddr; + + /* The symbol table index in the .loader section symbol table. */ + bfd_size_type l_symndx; + + /* The relocation type and size. */ + short l_rtype; + + /* The section number this relocation applies to. */ + short l_rsecnm; +}; + +/* An entry in the XCOFF linker hash table. */ +struct xcoff_link_hash_entry +{ + struct bfd_link_hash_entry root; + + /* Symbol index in output file. Set to -1 initially. Set to -2 if + there is a reloc against this symbol. */ + long indx; + + /* If we have created a TOC entry for this symbol, this is the .tc + section which holds it. */ + asection *toc_section; + + union + { + /* If we have created a TOC entry (the XCOFF_SET_TOC flag is + set), this is the offset in toc_section. */ + bfd_vma toc_offset; + + /* If the TOC entry comes from an input file, this is set to the + symbol index of the C_HIDEXT XMC_TC or XMC_TD symbol. */ + long toc_indx; + } + u; + + /* If this symbol is a function entry point which is called, this + field holds a pointer to the function descriptor. If this symbol + is a function descriptor, this field holds a pointer to the + function entry point. */ + struct xcoff_link_hash_entry *descriptor; + + /* The .loader symbol table entry, if there is one. */ + struct internal_ldsym *ldsym; + + /* If XCOFF_BUILT_LDSYM is set, this is the .loader symbol table + index. If XCOFF_BUILD_LDSYM is clear, and XCOFF_IMPORT is set, + this is the l_ifile value. */ + long ldindx; + + /* Some linker flags. */ + unsigned long flags; + + /* The storage mapping class. */ + unsigned char smclas; +}; + +/* Flags for xcoff_link_hash_entry. */ + +/* Symbol is referenced by a regular object. */ +#define XCOFF_REF_REGULAR 0x00000001 +/* Symbol is defined by a regular object. */ +#define XCOFF_DEF_REGULAR 0x00000002 +/* Symbol is defined by a dynamic object. */ +#define XCOFF_DEF_DYNAMIC 0x00000004 +/* Symbol is used in a reloc being copied into the .loader section. */ +#define XCOFF_LDREL 0x00000008 +/* Symbol is the entry point. */ +#define XCOFF_ENTRY 0x00000010 +/* Symbol is for a function and is the target of a relocation. + The relocation may or may not be a branch-type relocation. */ +#define XCOFF_CALLED 0x00000020 +/* Symbol needs the TOC entry filled in. */ +#define XCOFF_SET_TOC 0x00000040 +/* Symbol is implicitly or explicitly imported. */ +#define XCOFF_IMPORT 0x00000080 +/* Symbol is explicitly exported. */ +#define XCOFF_EXPORT 0x00000100 +/* Symbol has been processed by xcoff_build_ldsyms. */ +#define XCOFF_BUILT_LDSYM 0x00000200 +/* Symbol is mentioned by a section which was not garbage collected. */ +#define XCOFF_MARK 0x00000400 +/* Symbol size is recorded in size_list list from hash table. */ +#define XCOFF_HAS_SIZE 0x00000800 +/* Symbol is a function descriptor. */ +#define XCOFF_DESCRIPTOR 0x00001000 +/* Multiple definitions have been for the symbol. */ +#define XCOFF_MULTIPLY_DEFINED 0x00002000 +/* Symbol is the __rtinit symbol. */ +#define XCOFF_RTINIT 0x00004000 +/* Symbol is an imported 32 bit syscall. */ +#define XCOFF_SYSCALL32 0x00008000 +/* Symbol is an imported 64 bit syscall. */ +#define XCOFF_SYSCALL64 0x00010000 +/* Symbol was not explicitly defined by the time it was marked. */ +#define XCOFF_WAS_UNDEFINED 0x00020000 +/* We have assigned an output XCOFF entry to this symbol. */ +#define XCOFF_ALLOCATED 0x00040000 + +/* The XCOFF linker hash table. */ + +#define XCOFF_NUMBER_OF_SPECIAL_SECTIONS 6 +#define XCOFF_SPECIAL_SECTION_TEXT 0 +#define XCOFF_SPECIAL_SECTION_ETEXT 1 +#define XCOFF_SPECIAL_SECTION_DATA 2 +#define XCOFF_SPECIAL_SECTION_EDATA 3 +#define XCOFF_SPECIAL_SECTION_END 4 +#define XCOFF_SPECIAL_SECTION_END2 5 + +/* These flags indicate which of -bexpall and -bexpfull are in effect. */ +#define XCOFF_EXPALL 1 +#define XCOFF_EXPFULL 2 + +/* This structure is used to pass information through + xcoff_link_hash_traverse. */ + +struct xcoff_loader_info +{ + /* Set if a problem occurred. */ + bfd_boolean failed; + + /* Output BFD. */ + bfd *output_bfd; + + /* Link information structure. */ + struct bfd_link_info *info; + + /* A mask of XCOFF_EXPALL and XCOFF_EXPFULL flags. */ + unsigned int auto_export_flags; + + /* Number of ldsym structures. */ + size_t ldsym_count; + + /* Size of string table. */ + size_t string_size; + + /* String table. */ + char *strings; + + /* Allocated size of string table. */ + size_t string_alc; +}; + +/* In case we're on a 32-bit machine, construct a 64-bit "-1" value + from smaller values. Start with zero, widen, *then* decrement. */ +#define MINUS_ONE (((bfd_vma) 0) - 1) + +/* __rtinit, from /usr/include/rtinit.h. */ +struct __rtinit +{ + /* Pointer to runtime linker. + XXX: Is the parameter really void? */ + int (*rtl) (void); + + /* Offset to array of init functions, 0 if none. */ + int init_offset; + + /* Offset to array of fini functions, 0 if none. */ + int fini_offset; + + /* Size of __RTINIT_DESCRIPTOR. This value should be used instead of + sizeof(__RTINIT_DESCRIPTOR). */ + int __rtinit_descriptor_size; +}; + +#define RTINIT_DESCRIPTOR_SIZE (12) + +struct __rtinit_descriptor +{ + /* Init/fini function. */ + int f; + + /* Offset, relative to the start of the __rtinit symbol, to name of the + function. */ + + int name_offset; + + /* Flags */ + unsigned char flags; +}; + +/* Archive */ + +#define XCOFFARMAG "\012" +#define XCOFFARMAGBIG "\012" +#define SXCOFFARMAG 8 + +/* The size of the ascii archive elements */ +#define XCOFFARMAG_ELEMENT_SIZE 12 +#define XCOFFARMAGBIG_ELEMENT_SIZE 20 + +/* This terminates an XCOFF archive member name. */ + +#define XCOFFARFMAG "`\012" +#define SXCOFFARFMAG 2 + +/* XCOFF archives start with this (printable) structure. */ + +struct xcoff_ar_file_hdr +{ + /* Magic string. */ + char magic[SXCOFFARMAG]; + + /* Offset of the member table (decimal ASCII string). */ + char memoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the global symbol table (decimal ASCII string). */ + char symoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the first member in the archive (decimal ASCII string). */ + char firstmemoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the last member in the archive (decimal ASCII string). */ + char lastmemoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* Offset of the first member on the free list (decimal ASCII + string). */ + char freeoff[XCOFFARMAG_ELEMENT_SIZE]; +}; + +#define SIZEOF_AR_FILE_HDR (SXCOFFARMAG + 5 * XCOFFARMAG_ELEMENT_SIZE) + +/* This is the equivalent data structure for the big archive format. */ + +struct xcoff_ar_file_hdr_big +{ + /* Magic string. */ + char magic[SXCOFFARMAG]; + + /* Offset of the member table (decimal ASCII string). */ + char memoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the global symbol table for 32-bit objects (decimal ASCII + string). */ + char symoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the global symbol table for 64-bit objects (decimal ASCII + string). */ + char symoff64[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the first member in the archive (decimal ASCII string). */ + char firstmemoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the last member in the archive (decimal ASCII string). */ + char lastmemoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* Offset of the first member on the free list (decimal ASCII + string). */ + char freeoff[XCOFFARMAGBIG_ELEMENT_SIZE]; +}; + +#define SIZEOF_AR_FILE_HDR_BIG (SXCOFFARMAG + 6 * XCOFFARMAGBIG_ELEMENT_SIZE) + +/* Each XCOFF archive member starts with this (printable) structure. */ + +struct xcoff_ar_hdr +{ + /* File size not including the header (decimal ASCII string). */ + char size[XCOFFARMAG_ELEMENT_SIZE]; + + /* File offset of next archive member (decimal ASCII string). */ + char nextoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* File offset of previous archive member (decimal ASCII string). */ + char prevoff[XCOFFARMAG_ELEMENT_SIZE]; + + /* File mtime (decimal ASCII string). */ + char date[12]; + + /* File UID (decimal ASCII string). */ + char uid[12]; + + /* File GID (decimal ASCII string). */ + char gid[12]; + + /* File mode (octal ASCII string). */ + char mode[12]; + + /* Length of file name (decimal ASCII string). */ + char namlen[4]; + + /* This structure is followed by the file name. The length of the + name is given in the namlen field. If the length of the name is + odd, the name is followed by a null byte. The name and optional + null byte are followed by XCOFFARFMAG, which is not included in + namlen. The contents of the archive member follow; the number of + bytes is given in the size field. */ +}; + +#define SIZEOF_AR_HDR (3 * XCOFFARMAG_ELEMENT_SIZE + 4 * 12 + 4) + +/* The equivalent for the big archive format. */ + +struct xcoff_ar_hdr_big +{ + /* File size not including the header (decimal ASCII string). */ + char size[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File offset of next archive member (decimal ASCII string). */ + char nextoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File offset of previous archive member (decimal ASCII string). */ + char prevoff[XCOFFARMAGBIG_ELEMENT_SIZE]; + + /* File mtime (decimal ASCII string). */ + char date[12]; + + /* File UID (decimal ASCII string). */ + char uid[12]; + + /* File GID (decimal ASCII string). */ + char gid[12]; + + /* File mode (octal ASCII string). */ + char mode[12]; + + /* Length of file name (decimal ASCII string). */ + char namlen[4]; + + /* This structure is followed by the file name. The length of the + name is given in the namlen field. If the length of the name is + odd, the name is followed by a null byte. The name and optional + null byte are followed by XCOFFARFMAG, which is not included in + namlen. The contents of the archive member follow; the number of + bytes is given in the size field. */ +}; + +#define SIZEOF_AR_HDR_BIG (3 * XCOFFARMAGBIG_ELEMENT_SIZE + 4 * 12 + 4) + +/* We often have to distinguish between the old and big file format. + Make it a bit cleaner. We can use `xcoff_ardata' here because the + `hdr' member has the same size and position in both formats. + is the default format, return TRUE even when xcoff_ardata is + NULL. */ +#ifndef SMALL_ARCHIVE +/* Creates big archives by default */ +#define xcoff_big_format_p(abfd) \ + ((NULL != bfd_ardata (abfd) && NULL == xcoff_ardata (abfd)) || \ + ((NULL != bfd_ardata (abfd)) && \ + (NULL != xcoff_ardata (abfd)) && \ + (xcoff_ardata (abfd)->magic[1] == 'b'))) +#else +/* Creates small archives by default. */ +#define xcoff_big_format_p(abfd) \ + (((NULL != bfd_ardata (abfd)) && \ + (NULL != xcoff_ardata (abfd)) && \ + (xcoff_ardata (abfd)->magic[1] == 'b'))) +#endif + +/* We store a copy of the xcoff_ar_file_hdr in the tdata field of the + artdata structure. Similar for the big archive. */ +#define xcoff_ardata(abfd) \ + ((struct xcoff_ar_file_hdr *) bfd_ardata (abfd)->tdata) +#define xcoff_ardata_big(abfd) \ + ((struct xcoff_ar_file_hdr_big *) bfd_ardata (abfd)->tdata) + +/* We store a copy of the xcoff_ar_hdr in the arelt_data field of an + archive element. Similar for the big archive. */ +#define arch_eltdata(bfd) ((struct areltdata *) ((bfd)->arelt_data)) +#define arch_xhdr(bfd) \ + ((struct xcoff_ar_hdr *) arch_eltdata (bfd)->arch_header) +#define arch_xhdr_big(bfd) \ + ((struct xcoff_ar_hdr_big *) arch_eltdata (bfd)->arch_header) + +/* True if symbols of class CLASS are external. */ +#define EXTERN_SYM_P(CLASS) \ + ((CLASS) == C_EXT || (CLASS) == C_AIX_WEAKEXT) + +#endif /* _INTERNAL_XCOFF_H */ diff --git a/external/gpl3/gdb/dist/include/coff/z80.h b/external/gpl3/gdb/dist/include/coff/z80.h new file mode 100644 index 000000000000..712af054139c --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/z80.h @@ -0,0 +1,60 @@ +/* coff information for Zilog Z80 + Copyright 2005, 2010 Free Software Foundation, Inc. + Contributed by Arnold Metselaar + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* z80 backend does not use dots in section names. */ +#undef _TEXT +#define _TEXT "text" +#undef _DATA +#define _DATA "data" +#undef _BSS +#define _BSS "bss" + +/* Type of cpu is stored in flags. */ +#define F_MACHMASK 0xF000 + +/* Z80 COFF encodes the section alignment in the section header flags */ +#define COFF_ALIGN_IN_SECTION_HEADER 1 +#define COFF_ALIGN_IN_S_FLAGS 1 +#define F_ALGNMASK 0x0F00 +/* requires a power-of-two argument */ +#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8)) +/* result is a power of two */ +#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF) + +#define Z80MAGIC 0x805A + +#define Z80BADMAG(x) (((x).f_magic != Z80MAGIC)) + +/* Relocation directives. */ + +/* This format actually has more bits than we need. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 diff --git a/external/gpl3/gdb/dist/include/coff/z8k.h b/external/gpl3/gdb/dist/include/coff/z8k.h new file mode 100644 index 000000000000..5eef86d4fc2e --- /dev/null +++ b/external/gpl3/gdb/dist/include/coff/z8k.h @@ -0,0 +1,49 @@ +/* coff information for Zilog Z800N + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* Type of cpu is stored in flags */ +#define F_Z8001 0x1000 +#define F_Z8002 0x2000 +#define F_MACHMASK 0xf000 + +#define Z8KMAGIC 0x8000 + +#define Z8KBADMAG(x) (((x).f_magic != Z8KMAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/external/gpl3/gdb/dist/include/demangle.h b/external/gpl3/gdb/dist/include/demangle.h new file mode 100644 index 000000000000..53f6c54f5246 --- /dev/null +++ b/external/gpl3/gdb/dist/include/demangle.h @@ -0,0 +1,644 @@ +/* Defs for interface to demanglers. + Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, + 2003, 2004, 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + In addition to the permissions in the GNU Library General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file into + combinations with other programs, and to distribute those + combinations without any restriction coming from the use of this + file. (The Library Public License restrictions do apply in other + respects; for example, they cover modification of the file, and + distribution when not linked into a combined executable.) + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + + +#if !defined (DEMANGLE_H) +#define DEMANGLE_H + +#include "libiberty.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Options passed to cplus_demangle (in 2nd parameter). */ + +#define DMGL_NO_OPTS 0 /* For readability... */ +#define DMGL_PARAMS (1 << 0) /* Include function args */ +#define DMGL_ANSI (1 << 1) /* Include const, volatile, etc */ +#define DMGL_JAVA (1 << 2) /* Demangle as Java rather than C++. */ +#define DMGL_VERBOSE (1 << 3) /* Include implementation details. */ +#define DMGL_TYPES (1 << 4) /* Also try to demangle type encodings. */ +#define DMGL_RET_POSTFIX (1 << 5) /* Print function return types (when + present) after function signature. + It applies only to the toplevel + function type. */ +#define DMGL_RET_DROP (1 << 6) /* Suppress printing function return + types, even if present. It applies + only to the toplevel function type. + */ + +#define DMGL_AUTO (1 << 8) +#define DMGL_GNU (1 << 9) +#define DMGL_LUCID (1 << 10) +#define DMGL_ARM (1 << 11) +#define DMGL_HP (1 << 12) /* For the HP aCC compiler; + same as ARM except for + template arguments, etc. */ +#define DMGL_EDG (1 << 13) +#define DMGL_GNU_V3 (1 << 14) +#define DMGL_GNAT (1 << 15) + +/* If none of these are set, use 'current_demangling_style' as the default. */ +#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT) + +/* Enumeration of possible demangling styles. + + Lucid and ARM styles are still kept logically distinct, even though + they now both behave identically. The resulting style is actual the + union of both. I.E. either style recognizes both "__pt__" and "__rf__" + for operator "->", even though the first is lucid style and the second + is ARM style. (FIXME?) */ + +extern enum demangling_styles +{ + no_demangling = -1, + unknown_demangling = 0, + auto_demangling = DMGL_AUTO, + gnu_demangling = DMGL_GNU, + lucid_demangling = DMGL_LUCID, + arm_demangling = DMGL_ARM, + hp_demangling = DMGL_HP, + edg_demangling = DMGL_EDG, + gnu_v3_demangling = DMGL_GNU_V3, + java_demangling = DMGL_JAVA, + gnat_demangling = DMGL_GNAT +} current_demangling_style; + +/* Define string names for the various demangling styles. */ + +#define NO_DEMANGLING_STYLE_STRING "none" +#define AUTO_DEMANGLING_STYLE_STRING "auto" +#define GNU_DEMANGLING_STYLE_STRING "gnu" +#define LUCID_DEMANGLING_STYLE_STRING "lucid" +#define ARM_DEMANGLING_STYLE_STRING "arm" +#define HP_DEMANGLING_STYLE_STRING "hp" +#define EDG_DEMANGLING_STYLE_STRING "edg" +#define GNU_V3_DEMANGLING_STYLE_STRING "gnu-v3" +#define JAVA_DEMANGLING_STYLE_STRING "java" +#define GNAT_DEMANGLING_STYLE_STRING "gnat" + +/* Some macros to test what demangling style is active. */ + +#define CURRENT_DEMANGLING_STYLE current_demangling_style +#define AUTO_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_AUTO) +#define GNU_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU) +#define LUCID_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_LUCID) +#define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM) +#define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP) +#define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG) +#define GNU_V3_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_V3) +#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA) +#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT) + +/* Provide information about the available demangle styles. This code is + pulled from gdb into libiberty because it is useful to binutils also. */ + +extern const struct demangler_engine +{ + const char *const demangling_style_name; + const enum demangling_styles demangling_style; + const char *const demangling_style_doc; +} libiberty_demanglers[]; + +extern char * +cplus_demangle (const char *mangled, int options); + +extern int +cplus_demangle_opname (const char *opname, char *result, int options); + +extern const char * +cplus_mangle_opname (const char *opname, int options); + +/* Note: This sets global state. FIXME if you care about multi-threading. */ + +extern void +set_cplus_marker_for_demangling (int ch); + +extern enum demangling_styles +cplus_demangle_set_style (enum demangling_styles style); + +extern enum demangling_styles +cplus_demangle_name_to_style (const char *name); + +/* Callback typedef for allocation-less demangler interfaces. */ +typedef void (*demangle_callbackref) (const char *, size_t, void *); + +/* V3 ABI demangling entry points, defined in cp-demangle.c. Callback + variants return non-zero on success, zero on error. char* variants + return a string allocated by malloc on success, NULL on error. */ +extern int +cplus_demangle_v3_callback (const char *mangled, int options, + demangle_callbackref callback, void *opaque); + +extern char* +cplus_demangle_v3 (const char *mangled, int options); + +extern int +java_demangle_v3_callback (const char *mangled, + demangle_callbackref callback, void *opaque); + +extern char* +java_demangle_v3 (const char *mangled); + +char * +ada_demangle (const char *mangled, int options); + +enum gnu_v3_ctor_kinds { + gnu_v3_complete_object_ctor = 1, + gnu_v3_base_object_ctor, + gnu_v3_complete_object_allocating_ctor +}; + +/* Return non-zero iff NAME is the mangled form of a constructor name + in the G++ V3 ABI demangling style. Specifically, return an `enum + gnu_v3_ctor_kinds' value indicating what kind of constructor + it is. */ +extern enum gnu_v3_ctor_kinds + is_gnu_v3_mangled_ctor (const char *name); + + +enum gnu_v3_dtor_kinds { + gnu_v3_deleting_dtor = 1, + gnu_v3_complete_object_dtor, + gnu_v3_base_object_dtor +}; + +/* Return non-zero iff NAME is the mangled form of a destructor name + in the G++ V3 ABI demangling style. Specifically, return an `enum + gnu_v3_dtor_kinds' value, indicating what kind of destructor + it is. */ +extern enum gnu_v3_dtor_kinds + is_gnu_v3_mangled_dtor (const char *name); + +/* The V3 demangler works in two passes. The first pass builds a tree + representation of the mangled name, and the second pass turns the + tree representation into a demangled string. Here we define an + interface to permit a caller to build their own tree + representation, which they can pass to the demangler to get a + demangled string. This can be used to canonicalize user input into + something which the demangler might output. It could also be used + by other demanglers in the future. */ + +/* These are the component types which may be found in the tree. Many + component types have one or two subtrees, referred to as left and + right (a component type with only one subtree puts it in the left + subtree). */ + +enum demangle_component_type +{ + /* A name, with a length and a pointer to a string. */ + DEMANGLE_COMPONENT_NAME, + /* A qualified name. The left subtree is a class or namespace or + some such thing, and the right subtree is a name qualified by + that class. */ + DEMANGLE_COMPONENT_QUAL_NAME, + /* A local name. The left subtree describes a function, and the + right subtree is a name which is local to that function. */ + DEMANGLE_COMPONENT_LOCAL_NAME, + /* A typed name. The left subtree is a name, and the right subtree + describes that name as a function. */ + DEMANGLE_COMPONENT_TYPED_NAME, + /* A template. The left subtree is a template name, and the right + subtree is a template argument list. */ + DEMANGLE_COMPONENT_TEMPLATE, + /* A template parameter. This holds a number, which is the template + parameter index. */ + DEMANGLE_COMPONENT_TEMPLATE_PARAM, + /* A function parameter. This holds a number, which is the index. */ + DEMANGLE_COMPONENT_FUNCTION_PARAM, + /* A constructor. This holds a name and the kind of + constructor. */ + DEMANGLE_COMPONENT_CTOR, + /* A destructor. This holds a name and the kind of destructor. */ + DEMANGLE_COMPONENT_DTOR, + /* A vtable. This has one subtree, the type for which this is a + vtable. */ + DEMANGLE_COMPONENT_VTABLE, + /* A VTT structure. This has one subtree, the type for which this + is a VTT. */ + DEMANGLE_COMPONENT_VTT, + /* A construction vtable. The left subtree is the type for which + this is a vtable, and the right subtree is the derived type for + which this vtable is built. */ + DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE, + /* A typeinfo structure. This has one subtree, the type for which + this is the tpeinfo structure. */ + DEMANGLE_COMPONENT_TYPEINFO, + /* A typeinfo name. This has one subtree, the type for which this + is the typeinfo name. */ + DEMANGLE_COMPONENT_TYPEINFO_NAME, + /* A typeinfo function. This has one subtree, the type for which + this is the tpyeinfo function. */ + DEMANGLE_COMPONENT_TYPEINFO_FN, + /* A thunk. This has one subtree, the name for which this is a + thunk. */ + DEMANGLE_COMPONENT_THUNK, + /* A virtual thunk. This has one subtree, the name for which this + is a virtual thunk. */ + DEMANGLE_COMPONENT_VIRTUAL_THUNK, + /* A covariant thunk. This has one subtree, the name for which this + is a covariant thunk. */ + DEMANGLE_COMPONENT_COVARIANT_THUNK, + /* A Java class. This has one subtree, the type. */ + DEMANGLE_COMPONENT_JAVA_CLASS, + /* A guard variable. This has one subtree, the name for which this + is a guard variable. */ + DEMANGLE_COMPONENT_GUARD, + /* A reference temporary. This has one subtree, the name for which + this is a temporary. */ + DEMANGLE_COMPONENT_REFTEMP, + /* A hidden alias. This has one subtree, the encoding for which it + is providing alternative linkage. */ + DEMANGLE_COMPONENT_HIDDEN_ALIAS, + /* A standard substitution. This holds the name of the + substitution. */ + DEMANGLE_COMPONENT_SUB_STD, + /* The restrict qualifier. The one subtree is the type which is + being qualified. */ + DEMANGLE_COMPONENT_RESTRICT, + /* The volatile qualifier. The one subtree is the type which is + being qualified. */ + DEMANGLE_COMPONENT_VOLATILE, + /* The const qualifier. The one subtree is the type which is being + qualified. */ + DEMANGLE_COMPONENT_CONST, + /* The restrict qualifier modifying a member function. The one + subtree is the type which is being qualified. */ + DEMANGLE_COMPONENT_RESTRICT_THIS, + /* The volatile qualifier modifying a member function. The one + subtree is the type which is being qualified. */ + DEMANGLE_COMPONENT_VOLATILE_THIS, + /* The const qualifier modifying a member function. The one subtree + is the type which is being qualified. */ + DEMANGLE_COMPONENT_CONST_THIS, + /* A vendor qualifier. The left subtree is the type which is being + qualified, and the right subtree is the name of the + qualifier. */ + DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL, + /* A pointer. The one subtree is the type which is being pointed + to. */ + DEMANGLE_COMPONENT_POINTER, + /* A reference. The one subtree is the type which is being + referenced. */ + DEMANGLE_COMPONENT_REFERENCE, + /* C++0x: An rvalue reference. The one subtree is the type which is + being referenced. */ + DEMANGLE_COMPONENT_RVALUE_REFERENCE, + /* A complex type. The one subtree is the base type. */ + DEMANGLE_COMPONENT_COMPLEX, + /* An imaginary type. The one subtree is the base type. */ + DEMANGLE_COMPONENT_IMAGINARY, + /* A builtin type. This holds the builtin type information. */ + DEMANGLE_COMPONENT_BUILTIN_TYPE, + /* A vendor's builtin type. This holds the name of the type. */ + DEMANGLE_COMPONENT_VENDOR_TYPE, + /* A function type. The left subtree is the return type. The right + subtree is a list of ARGLIST nodes. Either or both may be + NULL. */ + DEMANGLE_COMPONENT_FUNCTION_TYPE, + /* An array type. The left subtree is the dimension, which may be + NULL, or a string (represented as DEMANGLE_COMPONENT_NAME), or an + expression. The right subtree is the element type. */ + DEMANGLE_COMPONENT_ARRAY_TYPE, + /* A pointer to member type. The left subtree is the class type, + and the right subtree is the member type. CV-qualifiers appear + on the latter. */ + DEMANGLE_COMPONENT_PTRMEM_TYPE, + /* A fixed-point type. */ + DEMANGLE_COMPONENT_FIXED_TYPE, + /* A vector type. The left subtree is the number of elements, + the right subtree is the element type. */ + DEMANGLE_COMPONENT_VECTOR_TYPE, + /* An argument list. The left subtree is the current argument, and + the right subtree is either NULL or another ARGLIST node. */ + DEMANGLE_COMPONENT_ARGLIST, + /* A template argument list. The left subtree is the current + template argument, and the right subtree is either NULL or + another TEMPLATE_ARGLIST node. */ + DEMANGLE_COMPONENT_TEMPLATE_ARGLIST, + /* An operator. This holds information about a standard + operator. */ + DEMANGLE_COMPONENT_OPERATOR, + /* An extended operator. This holds the number of arguments, and + the name of the extended operator. */ + DEMANGLE_COMPONENT_EXTENDED_OPERATOR, + /* A typecast, represented as a unary operator. The one subtree is + the type to which the argument should be cast. */ + DEMANGLE_COMPONENT_CAST, + /* A unary expression. The left subtree is the operator, and the + right subtree is the single argument. */ + DEMANGLE_COMPONENT_UNARY, + /* A binary expression. The left subtree is the operator, and the + right subtree is a BINARY_ARGS. */ + DEMANGLE_COMPONENT_BINARY, + /* Arguments to a binary expression. The left subtree is the first + argument, and the right subtree is the second argument. */ + DEMANGLE_COMPONENT_BINARY_ARGS, + /* A trinary expression. The left subtree is the operator, and the + right subtree is a TRINARY_ARG1. */ + DEMANGLE_COMPONENT_TRINARY, + /* Arguments to a trinary expression. The left subtree is the first + argument, and the right subtree is a TRINARY_ARG2. */ + DEMANGLE_COMPONENT_TRINARY_ARG1, + /* More arguments to a trinary expression. The left subtree is the + second argument, and the right subtree is the third argument. */ + DEMANGLE_COMPONENT_TRINARY_ARG2, + /* A literal. The left subtree is the type, and the right subtree + is the value, represented as a DEMANGLE_COMPONENT_NAME. */ + DEMANGLE_COMPONENT_LITERAL, + /* A negative literal. Like LITERAL, but the value is negated. + This is a minor hack: the NAME used for LITERAL points directly + to the mangled string, but since negative numbers are mangled + using 'n' instead of '-', we want a way to indicate a negative + number which involves neither modifying the mangled string nor + allocating a new copy of the literal in memory. */ + DEMANGLE_COMPONENT_LITERAL_NEG, + /* A libgcj compiled resource. The left subtree is the name of the + resource. */ + DEMANGLE_COMPONENT_JAVA_RESOURCE, + /* A name formed by the concatenation of two parts. The left + subtree is the first part and the right subtree the second. */ + DEMANGLE_COMPONENT_COMPOUND_NAME, + /* A name formed by a single character. */ + DEMANGLE_COMPONENT_CHARACTER, + /* A number. */ + DEMANGLE_COMPONENT_NUMBER, + /* A decltype type. */ + DEMANGLE_COMPONENT_DECLTYPE, + /* Global constructors keyed to name. */ + DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS, + /* Global destructors keyed to name. */ + DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS, + /* A lambda closure type. */ + DEMANGLE_COMPONENT_LAMBDA, + /* A default argument scope. */ + DEMANGLE_COMPONENT_DEFAULT_ARG, + /* An unnamed type. */ + DEMANGLE_COMPONENT_UNNAMED_TYPE, + /* A pack expansion. */ + DEMANGLE_COMPONENT_PACK_EXPANSION +}; + +/* Types which are only used internally. */ + +struct demangle_operator_info; +struct demangle_builtin_type_info; + +/* A node in the tree representation is an instance of a struct + demangle_component. Note that the field names of the struct are + not well protected against macros defined by the file including + this one. We can fix this if it ever becomes a problem. */ + +struct demangle_component +{ + /* The type of this component. */ + enum demangle_component_type type; + + union + { + /* For DEMANGLE_COMPONENT_NAME. */ + struct + { + /* A pointer to the name (which need not NULL terminated) and + its length. */ + const char *s; + int len; + } s_name; + + /* For DEMANGLE_COMPONENT_OPERATOR. */ + struct + { + /* Operator. */ + const struct demangle_operator_info *op; + } s_operator; + + /* For DEMANGLE_COMPONENT_EXTENDED_OPERATOR. */ + struct + { + /* Number of arguments. */ + int args; + /* Name. */ + struct demangle_component *name; + } s_extended_operator; + + /* For DEMANGLE_COMPONENT_FIXED_TYPE. */ + struct + { + /* The length, indicated by a C integer type name. */ + struct demangle_component *length; + /* _Accum or _Fract? */ + short accum; + /* Saturating or not? */ + short sat; + } s_fixed; + + /* For DEMANGLE_COMPONENT_CTOR. */ + struct + { + /* Kind of constructor. */ + enum gnu_v3_ctor_kinds kind; + /* Name. */ + struct demangle_component *name; + } s_ctor; + + /* For DEMANGLE_COMPONENT_DTOR. */ + struct + { + /* Kind of destructor. */ + enum gnu_v3_dtor_kinds kind; + /* Name. */ + struct demangle_component *name; + } s_dtor; + + /* For DEMANGLE_COMPONENT_BUILTIN_TYPE. */ + struct + { + /* Builtin type. */ + const struct demangle_builtin_type_info *type; + } s_builtin; + + /* For DEMANGLE_COMPONENT_SUB_STD. */ + struct + { + /* Standard substitution string. */ + const char* string; + /* Length of string. */ + int len; + } s_string; + + /* For DEMANGLE_COMPONENT_*_PARAM. */ + struct + { + /* Parameter index. */ + long number; + } s_number; + + /* For DEMANGLE_COMPONENT_CHARACTER. */ + struct + { + int character; + } s_character; + + /* For other types. */ + struct + { + /* Left (or only) subtree. */ + struct demangle_component *left; + /* Right subtree. */ + struct demangle_component *right; + } s_binary; + + struct + { + /* subtree, same place as d_left. */ + struct demangle_component *sub; + /* integer. */ + int num; + } s_unary_num; + + } u; +}; + +/* People building mangled trees are expected to allocate instances of + struct demangle_component themselves. They can then call one of + the following functions to fill them in. */ + +/* Fill in most component types with a left subtree and a right + subtree. Returns non-zero on success, zero on failure, such as an + unrecognized or inappropriate component type. */ + +extern int +cplus_demangle_fill_component (struct demangle_component *fill, + enum demangle_component_type, + struct demangle_component *left, + struct demangle_component *right); + +/* Fill in a DEMANGLE_COMPONENT_NAME. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_name (struct demangle_component *fill, + const char *, int); + +/* Fill in a DEMANGLE_COMPONENT_BUILTIN_TYPE, using the name of the + builtin type (e.g., "int", etc.). Returns non-zero on success, + zero if the type is not recognized. */ + +extern int +cplus_demangle_fill_builtin_type (struct demangle_component *fill, + const char *type_name); + +/* Fill in a DEMANGLE_COMPONENT_OPERATOR, using the name of the + operator and the number of arguments which it takes (the latter is + used to disambiguate operators which can be both binary and unary, + such as '-'). Returns non-zero on success, zero if the operator is + not recognized. */ + +extern int +cplus_demangle_fill_operator (struct demangle_component *fill, + const char *opname, int args); + +/* Fill in a DEMANGLE_COMPONENT_EXTENDED_OPERATOR, providing the + number of arguments and the name. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_extended_operator (struct demangle_component *fill, + int numargs, + struct demangle_component *nm); + +/* Fill in a DEMANGLE_COMPONENT_CTOR. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_ctor (struct demangle_component *fill, + enum gnu_v3_ctor_kinds kind, + struct demangle_component *name); + +/* Fill in a DEMANGLE_COMPONENT_DTOR. Returns non-zero on success, + zero for bad arguments. */ + +extern int +cplus_demangle_fill_dtor (struct demangle_component *fill, + enum gnu_v3_dtor_kinds kind, + struct demangle_component *name); + +/* This function translates a mangled name into a struct + demangle_component tree. The first argument is the mangled name. + The second argument is DMGL_* options. This returns a pointer to a + tree on success, or NULL on failure. On success, the third + argument is set to a block of memory allocated by malloc. This + block should be passed to free when the tree is no longer + needed. */ + +extern struct demangle_component * +cplus_demangle_v3_components (const char *mangled, int options, void **mem); + +/* This function takes a struct demangle_component tree and returns + the corresponding demangled string. The first argument is DMGL_* + options. The second is the tree to demangle. The third is a guess + at the length of the demangled string, used to initially allocate + the return buffer. The fourth is a pointer to a size_t. On + success, this function returns a buffer allocated by malloc(), and + sets the size_t pointed to by the fourth argument to the size of + the allocated buffer (not the length of the returned string). On + failure, this function returns NULL, and sets the size_t pointed to + by the fourth argument to 0 for an invalid tree, or to 1 for a + memory allocation error. */ + +extern char * +cplus_demangle_print (int options, + const struct demangle_component *tree, + int estimated_length, + size_t *p_allocated_size); + +/* This function takes a struct demangle_component tree and passes back + a demangled string in one or more calls to a callback function. + The first argument is DMGL_* options. The second is the tree to + demangle. The third is a pointer to a callback function; on each call + this receives an element of the demangled string, its length, and an + opaque value. The fourth is the opaque value passed to the callback. + The callback is called once or more to return the full demangled + string. The demangled element string is always nul-terminated, though + its length is also provided for convenience. In contrast to + cplus_demangle_print(), this function does not allocate heap memory + to grow output strings (except perhaps where alloca() is implemented + by malloc()), and so is normally safe for use where the heap has been + corrupted. On success, this function returns 1; on failure, 0. */ + +extern int +cplus_demangle_print_callback (int options, + const struct demangle_component *tree, + demangle_callbackref callback, void *opaque); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* DEMANGLE_H */ diff --git a/external/gpl3/gdb/dist/include/dis-asm.h b/external/gpl3/gdb/dist/include/dis-asm.h new file mode 100644 index 000000000000..63366d9e5577 --- /dev/null +++ b/external/gpl3/gdb/dist/include/dis-asm.h @@ -0,0 +1,368 @@ +/* Interface between the opcode library and its callers. + + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Written by Cygnus Support, 1993. + + The opcode library (libopcodes.a) provides instruction decoders for + a large variety of instruction sets, callable with an identical + interface, for making instruction-processing programs more independent + of the instruction set being processed. */ + +#ifndef DIS_ASM_H +#define DIS_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "bfd.h" + + typedef int (*fprintf_ftype) (void *, const char*, ...) /*ATTRIBUTE_FPTR_PRINTF_2*/; + +enum dis_insn_type +{ + dis_noninsn, /* Not a valid instruction. */ + dis_nonbranch, /* Not a branch instruction. */ + dis_branch, /* Unconditional branch. */ + dis_condbranch, /* Conditional branch. */ + dis_jsr, /* Jump to subroutine. */ + dis_condjsr, /* Conditional jump to subroutine. */ + dis_dref, /* Data reference instruction. */ + dis_dref2 /* Two data references in instruction. */ +}; + +/* This struct is passed into the instruction decoding routine, + and is passed back out into each callback. The various fields are used + for conveying information from your main routine into your callbacks, + for passing information into the instruction decoders (such as the + addresses of the callback functions), or for passing information + back from the instruction decoders to their callers. + + It must be initialized before it is first passed; this can be done + by hand, or using one of the initialization macros below. */ + +typedef struct disassemble_info +{ + fprintf_ftype fprintf_func; + void *stream; + void *application_data; + + /* Target description. We could replace this with a pointer to the bfd, + but that would require one. There currently isn't any such requirement + so to avoid introducing one we record these explicitly. */ + /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ + enum bfd_flavour flavour; + /* The bfd_arch value. */ + enum bfd_architecture arch; + /* The bfd_mach value. */ + unsigned long mach; + /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ + enum bfd_endian endian; + /* Endianness of code, for mixed-endian situations such as ARM BE8. */ + enum bfd_endian endian_code; + /* An arch/mach-specific bitmask of selected instruction subsets, mainly + for processors with run-time-switchable instruction sets. The default, + zero, means that there is no constraint. CGEN-based opcodes ports + may use ISA_foo masks. */ + void *insn_sets; + + /* Some targets need information about the current section to accurately + display insns. If this is NULL, the target disassembler function + will have to make its best guess. */ + asection *section; + + /* An array of pointers to symbols either at the location being disassembled + or at the start of the function being disassembled. The array is sorted + so that the first symbol is intended to be the one used. The others are + present for any misc. purposes. This is not set reliably, but if it is + not NULL, it is correct. */ + asymbol **symbols; + /* Number of symbols in array. */ + int num_symbols; + + /* Symbol table provided for targets that want to look at it. This is + used on Arm to find mapping symbols and determine Arm/Thumb code. */ + asymbol **symtab; + int symtab_pos; + int symtab_size; + + /* For use by the disassembler. + The top 16 bits are reserved for public use (and are documented here). + The bottom 16 bits are for the internal use of the disassembler. */ + unsigned long flags; + /* Set if the disassembler has determined that there are one or more + relocations associated with the instruction being disassembled. */ +#define INSN_HAS_RELOC (1 << 31) + /* Set if the user has requested the disassembly of data as well as code. */ +#define DISASSEMBLE_DATA (1 << 30) + /* Set if the user has specifically set the machine type encoded in the + mach field of this structure. */ +#define USER_SPECIFIED_MACHINE_TYPE (1 << 29) + + /* Use internally by the target specific disassembly code. */ + void *private_data; + + /* Function used to get bytes to disassemble. MEMADDR is the + address of the stuff to be disassembled, MYADDR is the address to + put the bytes in, and LENGTH is the number of bytes to read. + INFO is a pointer to this struct. + Returns an errno value or 0 for success. */ + int (*read_memory_func) + (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *dinfo); + + /* Function which should be called if we get an error that we can't + recover from. STATUS is the errno value from read_memory_func and + MEMADDR is the address that we were trying to read. INFO is a + pointer to this struct. */ + void (*memory_error_func) + (int status, bfd_vma memaddr, struct disassemble_info *dinfo); + + /* Function called to print ADDR. */ + void (*print_address_func) + (bfd_vma addr, struct disassemble_info *dinfo); + + /* Function called to determine if there is a symbol at the given ADDR. + If there is, the function returns 1, otherwise it returns 0. + This is used by ports which support an overlay manager where + the overlay number is held in the top part of an address. In + some circumstances we want to include the overlay number in the + address, (normally because there is a symbol associated with + that address), but sometimes we want to mask out the overlay bits. */ + int (* symbol_at_address_func) + (bfd_vma addr, struct disassemble_info *dinfo); + + /* Function called to check if a SYMBOL is can be displayed to the user. + This is used by some ports that want to hide special symbols when + displaying debugging outout. */ + bfd_boolean (* symbol_is_valid) + (asymbol *, struct disassemble_info *dinfo); + + /* These are for buffer_read_memory. */ + bfd_byte *buffer; + bfd_vma buffer_vma; + unsigned int buffer_length; + + /* This variable may be set by the instruction decoder. It suggests + the number of bytes objdump should display on a single line. If + the instruction decoder sets this, it should always set it to + the same value in order to get reasonable looking output. */ + int bytes_per_line; + + /* The next two variables control the way objdump displays the raw data. */ + /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ + /* output will look like this: + 00: 00000000 00000000 + with the chunks displayed according to "display_endian". */ + int bytes_per_chunk; + enum bfd_endian display_endian; + + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ + unsigned int octets_per_byte; + + /* The number of zeroes we want to see at the end of a section before we + start skipping them. */ + unsigned int skip_zeroes; + + /* The number of zeroes to skip at the end of a section. If the number + of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES, + they will be disassembled. If there are fewer than + SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic + attempt to avoid disassembling zeroes inserted by section + alignment. */ + unsigned int skip_zeroes_at_end; + + /* Whether the disassembler always needs the relocations. */ + bfd_boolean disassembler_needs_relocs; + + /* Results from instruction decoders. Not all decoders yet support + this information. This info is set each time an instruction is + decoded, and is only valid for the last such instruction. + + To determine whether this decoder supports this information, set + insn_info_valid to 0, decode an instruction, then check it. */ + + char insn_info_valid; /* Branch info has been set. */ + char branch_delay_insns; /* How many sequential insn's will run before + a branch takes effect. (0 = normal) */ + char data_size; /* Size of data reference in insn, in bytes */ + enum dis_insn_type insn_type; /* Type of instruction */ + bfd_vma target; /* Target address of branch or dref, if known; + zero if unknown. */ + bfd_vma target2; /* Second target address for dref2 */ + + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + +} disassemble_info; + + +/* Standard disassemblers. Disassemble one instruction at the given + target address. Return number of octets processed. */ +typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); + +extern int print_insn_alpha (bfd_vma, disassemble_info *); +extern int print_insn_avr (bfd_vma, disassemble_info *); +extern int print_insn_bfin (bfd_vma, disassemble_info *); +extern int print_insn_big_arm (bfd_vma, disassemble_info *); +extern int print_insn_big_mips (bfd_vma, disassemble_info *); +extern int print_insn_big_or32 (bfd_vma, disassemble_info *); +extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_big_score (bfd_vma, disassemble_info *); +extern int print_insn_cr16 (bfd_vma, disassemble_info *); +extern int print_insn_crx (bfd_vma, disassemble_info *); +extern int print_insn_d10v (bfd_vma, disassemble_info *); +extern int print_insn_d30v (bfd_vma, disassemble_info *); +extern int print_insn_dlx (bfd_vma, disassemble_info *); +extern int print_insn_fr30 (bfd_vma, disassemble_info *); +extern int print_insn_frv (bfd_vma, disassemble_info *); +extern int print_insn_h8300 (bfd_vma, disassemble_info *); +extern int print_insn_h8300h (bfd_vma, disassemble_info *); +extern int print_insn_h8300s (bfd_vma, disassemble_info *); +extern int print_insn_h8500 (bfd_vma, disassemble_info *); +extern int print_insn_hppa (bfd_vma, disassemble_info *); +extern int print_insn_i370 (bfd_vma, disassemble_info *); +extern int print_insn_i386 (bfd_vma, disassemble_info *); +extern int print_insn_i386_att (bfd_vma, disassemble_info *); +extern int print_insn_i386_intel (bfd_vma, disassemble_info *); +extern int print_insn_i860 (bfd_vma, disassemble_info *); +extern int print_insn_i960 (bfd_vma, disassemble_info *); +extern int print_insn_ia64 (bfd_vma, disassemble_info *); +extern int print_insn_ip2k (bfd_vma, disassemble_info *); +extern int print_insn_iq2000 (bfd_vma, disassemble_info *); +extern int print_insn_little_arm (bfd_vma, disassemble_info *); +extern int print_insn_little_mips (bfd_vma, disassemble_info *); +extern int print_insn_little_or32 (bfd_vma, disassemble_info *); +extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_little_score (bfd_vma, disassemble_info *); +extern int print_insn_lm32 (bfd_vma, disassemble_info *); +extern int print_insn_m32c (bfd_vma, disassemble_info *); +extern int print_insn_m32r (bfd_vma, disassemble_info *); +extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); +extern int print_insn_m68k (bfd_vma, disassemble_info *); +extern int print_insn_m88k (bfd_vma, disassemble_info *); +extern int print_insn_mcore (bfd_vma, disassemble_info *); +extern int print_insn_mep (bfd_vma, disassemble_info *); +extern int print_insn_microblaze (bfd_vma, disassemble_info *); +extern int print_insn_mmix (bfd_vma, disassemble_info *); +extern int print_insn_mn10200 (bfd_vma, disassemble_info *); +extern int print_insn_mn10300 (bfd_vma, disassemble_info *); +extern int print_insn_moxie (bfd_vma, disassemble_info *); +extern int print_insn_msp430 (bfd_vma, disassemble_info *); +extern int print_insn_mt (bfd_vma, disassemble_info *); +extern int print_insn_ns32k (bfd_vma, disassemble_info *); +extern int print_insn_openrisc (bfd_vma, disassemble_info *); +extern int print_insn_pdp11 (bfd_vma, disassemble_info *); +extern int print_insn_pj (bfd_vma, disassemble_info *); +extern int print_insn_rs6000 (bfd_vma, disassemble_info *); +extern int print_insn_s390 (bfd_vma, disassemble_info *); +extern int print_insn_sh (bfd_vma, disassemble_info *); +extern int print_insn_sh64 (bfd_vma, disassemble_info *); +extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); +extern int print_insn_sparc (bfd_vma, disassemble_info *); +extern int print_insn_spu (bfd_vma, disassemble_info *); +extern int print_insn_tic30 (bfd_vma, disassemble_info *); +extern int print_insn_tic4x (bfd_vma, disassemble_info *); +extern int print_insn_tic54x (bfd_vma, disassemble_info *); +extern int print_insn_tic6x (bfd_vma, disassemble_info *); +extern int print_insn_tic80 (bfd_vma, disassemble_info *); +extern int print_insn_v850 (bfd_vma, disassemble_info *); +extern int print_insn_vax (bfd_vma, disassemble_info *); +extern int print_insn_w65 (bfd_vma, disassemble_info *); +extern int print_insn_xc16x (bfd_vma, disassemble_info *); +extern int print_insn_xstormy16 (bfd_vma, disassemble_info *); +extern int print_insn_xtensa (bfd_vma, disassemble_info *); +extern int print_insn_z80 (bfd_vma, disassemble_info *); +extern int print_insn_z8001 (bfd_vma, disassemble_info *); +extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern int print_insn_rx (bfd_vma, disassemble_info *); + +extern disassembler_ftype arc_get_disassembler (void *); +extern disassembler_ftype cris_get_disassembler (bfd *); + +extern void print_i386_disassembler_options (FILE *); +extern void print_mips_disassembler_options (FILE *); +extern void print_ppc_disassembler_options (FILE *); +extern void print_arm_disassembler_options (FILE *); +extern void parse_arm_disassembler_option (char *); +extern void print_s390_disassembler_options (FILE *); +extern int get_arm_regname_num_options (void); +extern int set_arm_regname_option (int); +extern int get_arm_regnames (int, const char **, const char **, const char *const **); +extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); + +/* Fetch the disassembler for a given BFD, if that support is available. */ +extern disassembler_ftype disassembler (bfd *); + +/* Amend the disassemble_info structure as necessary for the target architecture. + Should only be called after initialising the info->arch field. */ +extern void disassemble_init_for_target (struct disassemble_info * dinfo); + +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage (FILE *); + + +/* This block of definitions is for particular callers who read instructions + into a buffer before calling the instruction decoder. */ + +/* Here is a function which callers may wish to use for read_memory_func. + It gets bytes from a buffer. */ +extern int buffer_read_memory + (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *); + +/* This function goes with buffer_read_memory. + It prints a message using info->fprintf_func and info->stream. */ +extern void perror_memory (int, bfd_vma, struct disassemble_info *); + + +/* Just print the address in hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ +extern void generic_print_address + (bfd_vma, struct disassemble_info *); + +/* Always true. */ +extern int generic_symbol_at_address + (bfd_vma, struct disassemble_info *); + +/* Also always true. */ +extern bfd_boolean generic_symbol_is_valid + (asymbol *, struct disassemble_info *); + +/* Method to initialize a disassemble_info struct. This should be + called by all applications creating such a struct. */ +extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream, + fprintf_ftype fprintf_func); + +/* For compatibility with existing code. */ +#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) +#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC)) + + +#ifdef __cplusplus +} +#endif + +#endif /* ! defined (DIS_ASM_H) */ diff --git a/external/gpl3/gdb/dist/include/dwarf2.h b/external/gpl3/gdb/dist/include/dwarf2.h new file mode 100644 index 000000000000..44b4328de5a3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/dwarf2.h @@ -0,0 +1,897 @@ +/* Declarations and definitions of codes relating to the DWARF2 and + DWARF3 symbolic debugging information formats. + Copyright (C) 1992, 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002, + 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + Written by Gary Funck (gary@intrepid.com) The Ada Joint Program + Office (AJPO), Florida State University and Silicon Graphics Inc. + provided support for this effort -- June 21, 1995. + + Derived from the DWARF 1 implementation written by Ron Guilmette + (rfg@netcom.com), November 1990. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +/* This file is derived from the DWARF specification (a public document) + Revision 2.0.0 (July 27, 1993) developed by the UNIX International + Programming Languages Special Interest Group (UI/PLSIG) and distributed + by UNIX International. Copies of this specification are available from + UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054. + + This file also now contains definitions from the DWARF 3 specification + published Dec 20, 2005, available from: http://dwarf.freestandards.org. */ + +/* This file is shared between GCC and GDB, and should not contain + prototypes. */ + +#ifndef _DWARF2_H +#define _DWARF2_H + +/* Tag names and codes. */ +enum dwarf_tag + { + DW_TAG_padding = 0x00, + DW_TAG_array_type = 0x01, + DW_TAG_class_type = 0x02, + DW_TAG_entry_point = 0x03, + DW_TAG_enumeration_type = 0x04, + DW_TAG_formal_parameter = 0x05, + DW_TAG_imported_declaration = 0x08, + DW_TAG_label = 0x0a, + DW_TAG_lexical_block = 0x0b, + DW_TAG_member = 0x0d, + DW_TAG_pointer_type = 0x0f, + DW_TAG_reference_type = 0x10, + DW_TAG_compile_unit = 0x11, + DW_TAG_string_type = 0x12, + DW_TAG_structure_type = 0x13, + DW_TAG_subroutine_type = 0x15, + DW_TAG_typedef = 0x16, + DW_TAG_union_type = 0x17, + DW_TAG_unspecified_parameters = 0x18, + DW_TAG_variant = 0x19, + DW_TAG_common_block = 0x1a, + DW_TAG_common_inclusion = 0x1b, + DW_TAG_inheritance = 0x1c, + DW_TAG_inlined_subroutine = 0x1d, + DW_TAG_module = 0x1e, + DW_TAG_ptr_to_member_type = 0x1f, + DW_TAG_set_type = 0x20, + DW_TAG_subrange_type = 0x21, + DW_TAG_with_stmt = 0x22, + DW_TAG_access_declaration = 0x23, + DW_TAG_base_type = 0x24, + DW_TAG_catch_block = 0x25, + DW_TAG_const_type = 0x26, + DW_TAG_constant = 0x27, + DW_TAG_enumerator = 0x28, + DW_TAG_file_type = 0x29, + DW_TAG_friend = 0x2a, + DW_TAG_namelist = 0x2b, + DW_TAG_namelist_item = 0x2c, + DW_TAG_packed_type = 0x2d, + DW_TAG_subprogram = 0x2e, + DW_TAG_template_type_param = 0x2f, + DW_TAG_template_value_param = 0x30, + DW_TAG_thrown_type = 0x31, + DW_TAG_try_block = 0x32, + DW_TAG_variant_part = 0x33, + DW_TAG_variable = 0x34, + DW_TAG_volatile_type = 0x35, + /* DWARF 3. */ + DW_TAG_dwarf_procedure = 0x36, + DW_TAG_restrict_type = 0x37, + DW_TAG_interface_type = 0x38, + DW_TAG_namespace = 0x39, + DW_TAG_imported_module = 0x3a, + DW_TAG_unspecified_type = 0x3b, + DW_TAG_partial_unit = 0x3c, + DW_TAG_imported_unit = 0x3d, + DW_TAG_condition = 0x3f, + DW_TAG_shared_type = 0x40, + /* DWARF 4. */ + DW_TAG_type_unit = 0x41, + DW_TAG_rvalue_reference_type = 0x42, + DW_TAG_template_alias = 0x43, + + DW_TAG_lo_user = 0x4080, + DW_TAG_hi_user = 0xffff, + + /* SGI/MIPS Extensions. */ + DW_TAG_MIPS_loop = 0x4081, + + /* HP extensions. See: ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz . */ + DW_TAG_HP_array_descriptor = 0x4090, + DW_TAG_HP_Bliss_field = 0x4091, + DW_TAG_HP_Bliss_field_set = 0x4092, + + /* GNU extensions. */ + DW_TAG_format_label = 0x4101, /* For FORTRAN 77 and Fortran 90. */ + DW_TAG_function_template = 0x4102, /* For C++. */ + DW_TAG_class_template = 0x4103, /* For C++. */ + DW_TAG_GNU_BINCL = 0x4104, + DW_TAG_GNU_EINCL = 0x4105, + /* Template template parameter. + See http://gcc.gnu.org/wiki/TemplateParmsDwarf . */ + DW_TAG_GNU_template_template_param = 0x4106, + + /* Template parameter pack extension, specified at + http://wiki.dwarfstd.org/index.php?title=C%2B%2B0x:_Variadic_templates + The values of these two TAGS are in the DW_TAG_GNU_* space until the tags + are properly part of DWARF 5. */ + DW_TAG_GNU_template_parameter_pack = 0x4107, + DW_TAG_GNU_formal_parameter_pack = 0x4108, + /* The GNU call site extension, specified at + http://www.dwarfstd.org/ShowIssue.php?issue=100909.2&type=open . + The values of these two TAGS are in the DW_TAG_GNU_* space until the tags + are properly part of DWARF 5. */ + DW_TAG_GNU_call_site = 0x4109, + DW_TAG_GNU_call_site_parameter = 0x410a, + /* Extensions for UPC. See: http://upc.gwu.edu/~upc. */ + DW_TAG_upc_shared_type = 0x8765, + DW_TAG_upc_strict_type = 0x8766, + DW_TAG_upc_relaxed_type = 0x8767, + /* PGI (STMicroelectronics) extensions. No documentation available. */ + DW_TAG_PGI_kanji_type = 0xA000, + DW_TAG_PGI_interface_block = 0xA020 + }; + +/* Flag that tells whether entry has a child or not. */ +#define DW_children_no 0 +#define DW_children_yes 1 + +/* Form names and codes. */ +enum dwarf_form + { + DW_FORM_addr = 0x01, + DW_FORM_block2 = 0x03, + DW_FORM_block4 = 0x04, + DW_FORM_data2 = 0x05, + DW_FORM_data4 = 0x06, + DW_FORM_data8 = 0x07, + DW_FORM_string = 0x08, + DW_FORM_block = 0x09, + DW_FORM_block1 = 0x0a, + DW_FORM_data1 = 0x0b, + DW_FORM_flag = 0x0c, + DW_FORM_sdata = 0x0d, + DW_FORM_strp = 0x0e, + DW_FORM_udata = 0x0f, + DW_FORM_ref_addr = 0x10, + DW_FORM_ref1 = 0x11, + DW_FORM_ref2 = 0x12, + DW_FORM_ref4 = 0x13, + DW_FORM_ref8 = 0x14, + DW_FORM_ref_udata = 0x15, + DW_FORM_indirect = 0x16, + /* DWARF 4. */ + DW_FORM_sec_offset = 0x17, + DW_FORM_exprloc = 0x18, + DW_FORM_flag_present = 0x19, + DW_FORM_ref_sig8 = 0x20 + }; + +/* Attribute names and codes. */ +enum dwarf_attribute + { + DW_AT_sibling = 0x01, + DW_AT_location = 0x02, + DW_AT_name = 0x03, + DW_AT_ordering = 0x09, + DW_AT_subscr_data = 0x0a, + DW_AT_byte_size = 0x0b, + DW_AT_bit_offset = 0x0c, + DW_AT_bit_size = 0x0d, + DW_AT_element_list = 0x0f, + DW_AT_stmt_list = 0x10, + DW_AT_low_pc = 0x11, + DW_AT_high_pc = 0x12, + DW_AT_language = 0x13, + DW_AT_member = 0x14, + DW_AT_discr = 0x15, + DW_AT_discr_value = 0x16, + DW_AT_visibility = 0x17, + DW_AT_import = 0x18, + DW_AT_string_length = 0x19, + DW_AT_common_reference = 0x1a, + DW_AT_comp_dir = 0x1b, + DW_AT_const_value = 0x1c, + DW_AT_containing_type = 0x1d, + DW_AT_default_value = 0x1e, + DW_AT_inline = 0x20, + DW_AT_is_optional = 0x21, + DW_AT_lower_bound = 0x22, + DW_AT_producer = 0x25, + DW_AT_prototyped = 0x27, + DW_AT_return_addr = 0x2a, + DW_AT_start_scope = 0x2c, + DW_AT_bit_stride = 0x2e, +#define DW_AT_stride_size DW_AT_bit_stride /* Note: The use of DW_AT_stride_size is deprecated. */ + DW_AT_upper_bound = 0x2f, + DW_AT_abstract_origin = 0x31, + DW_AT_accessibility = 0x32, + DW_AT_address_class = 0x33, + DW_AT_artificial = 0x34, + DW_AT_base_types = 0x35, + DW_AT_calling_convention = 0x36, + DW_AT_count = 0x37, + DW_AT_data_member_location = 0x38, + DW_AT_decl_column = 0x39, + DW_AT_decl_file = 0x3a, + DW_AT_decl_line = 0x3b, + DW_AT_declaration = 0x3c, + DW_AT_discr_list = 0x3d, + DW_AT_encoding = 0x3e, + DW_AT_external = 0x3f, + DW_AT_frame_base = 0x40, + DW_AT_friend = 0x41, + DW_AT_identifier_case = 0x42, + DW_AT_macro_info = 0x43, + DW_AT_namelist_items = 0x44, + DW_AT_priority = 0x45, + DW_AT_segment = 0x46, + DW_AT_specification = 0x47, + DW_AT_static_link = 0x48, + DW_AT_type = 0x49, + DW_AT_use_location = 0x4a, + DW_AT_variable_parameter = 0x4b, + DW_AT_virtuality = 0x4c, + DW_AT_vtable_elem_location = 0x4d, + /* DWARF 3 values. */ + DW_AT_allocated = 0x4e, + DW_AT_associated = 0x4f, + DW_AT_data_location = 0x50, + DW_AT_byte_stride = 0x51, +#define DW_AT_stride DW_AT_byte_stride /* Note: The use of DW_AT_stride is deprecated. */ + DW_AT_entry_pc = 0x52, + DW_AT_use_UTF8 = 0x53, + DW_AT_extension = 0x54, + DW_AT_ranges = 0x55, + DW_AT_trampoline = 0x56, + DW_AT_call_column = 0x57, + DW_AT_call_file = 0x58, + DW_AT_call_line = 0x59, + DW_AT_description = 0x5a, + DW_AT_binary_scale = 0x5b, + DW_AT_decimal_scale = 0x5c, + DW_AT_small = 0x5d, + DW_AT_decimal_sign = 0x5e, + DW_AT_digit_count = 0x5f, + DW_AT_picture_string = 0x60, + DW_AT_mutable = 0x61, + DW_AT_threads_scaled = 0x62, + DW_AT_explicit = 0x63, + DW_AT_object_pointer = 0x64, + DW_AT_endianity = 0x65, + DW_AT_elemental = 0x66, + DW_AT_pure = 0x67, + DW_AT_recursive = 0x68, + /* DWARF 4. */ + DW_AT_signature = 0x69, + DW_AT_main_subprogram = 0x6a, + DW_AT_data_bit_offset = 0x6b, + DW_AT_const_expr = 0x6c, + DW_AT_enum_class = 0x6d, + DW_AT_linkage_name = 0x6e, + + DW_AT_lo_user = 0x2000, /* Implementation-defined range start. */ + DW_AT_hi_user = 0x3fff, /* Implementation-defined range end. */ + + /* SGI/MIPS extensions. */ + DW_AT_MIPS_fde = 0x2001, + DW_AT_MIPS_loop_begin = 0x2002, + DW_AT_MIPS_tail_loop_begin = 0x2003, + DW_AT_MIPS_epilog_begin = 0x2004, + DW_AT_MIPS_loop_unroll_factor = 0x2005, + DW_AT_MIPS_software_pipeline_depth = 0x2006, + DW_AT_MIPS_linkage_name = 0x2007, + DW_AT_MIPS_stride = 0x2008, + DW_AT_MIPS_abstract_name = 0x2009, + DW_AT_MIPS_clone_origin = 0x200a, + DW_AT_MIPS_has_inlines = 0x200b, + /* HP extensions. */ + DW_AT_HP_block_index = 0x2000, + DW_AT_HP_unmodifiable = 0x2001, /* Same as DW_AT_MIPS_fde. */ + DW_AT_HP_prologue = 0x2005, /* Same as DW_AT_MIPS_loop_unroll. */ + DW_AT_HP_epilogue = 0x2008, /* Same as DW_AT_MIPS_stride. */ + DW_AT_HP_actuals_stmt_list = 0x2010, + DW_AT_HP_proc_per_section = 0x2011, + DW_AT_HP_raw_data_ptr = 0x2012, + DW_AT_HP_pass_by_reference = 0x2013, + DW_AT_HP_opt_level = 0x2014, + DW_AT_HP_prof_version_id = 0x2015, + DW_AT_HP_opt_flags = 0x2016, + DW_AT_HP_cold_region_low_pc = 0x2017, + DW_AT_HP_cold_region_high_pc = 0x2018, + DW_AT_HP_all_variables_modifiable = 0x2019, + DW_AT_HP_linkage_name = 0x201a, + DW_AT_HP_prof_flags = 0x201b, /* In comp unit of procs_info for -g. */ + DW_AT_HP_unit_name = 0x201f, + DW_AT_HP_unit_size = 0x2020, + DW_AT_HP_widened_byte_size = 0x2021, + DW_AT_HP_definition_points = 0x2022, + DW_AT_HP_default_location = 0x2023, + DW_AT_HP_is_result_param = 0x2029, + + /* GNU extensions. */ + DW_AT_sf_names = 0x2101, + DW_AT_src_info = 0x2102, + DW_AT_mac_info = 0x2103, + DW_AT_src_coords = 0x2104, + DW_AT_body_begin = 0x2105, + DW_AT_body_end = 0x2106, + DW_AT_GNU_vector = 0x2107, + /* Thread-safety annotations. + See http://gcc.gnu.org/wiki/ThreadSafetyAnnotation . */ + DW_AT_GNU_guarded_by = 0x2108, + DW_AT_GNU_pt_guarded_by = 0x2109, + DW_AT_GNU_guarded = 0x210a, + DW_AT_GNU_pt_guarded = 0x210b, + DW_AT_GNU_locks_excluded = 0x210c, + DW_AT_GNU_exclusive_locks_required = 0x210d, + DW_AT_GNU_shared_locks_required = 0x210e, + /* One-definition rule violation detection. + See http://gcc.gnu.org/wiki/DwarfSeparateTypeInfo . */ + DW_AT_GNU_odr_signature = 0x210f, + /* Template template argument name. + See http://gcc.gnu.org/wiki/TemplateParmsDwarf . */ + DW_AT_GNU_template_name = 0x2110, + /* The GNU call site extension. + See http://www.dwarfstd.org/ShowIssue.php?issue=100909.2&type=open . */ + DW_AT_GNU_call_site_value = 0x2111, + DW_AT_GNU_call_site_data_value = 0x2112, + DW_AT_GNU_call_site_target = 0x2113, + DW_AT_GNU_call_site_target_clobbered = 0x2114, + DW_AT_GNU_tail_call = 0x2115, + DW_AT_GNU_all_tail_call_sites = 0x2116, + DW_AT_GNU_all_call_sites = 0x2117, + DW_AT_GNU_all_source_call_sites = 0x2118, + /* VMS extensions. */ + DW_AT_VMS_rtnbeg_pd_address = 0x2201, + /* GNAT extensions. */ + /* GNAT descriptive type. + See http://gcc.gnu.org/wiki/DW_AT_GNAT_descriptive_type . */ + DW_AT_use_GNAT_descriptive_type = 0x2301, + DW_AT_GNAT_descriptive_type = 0x2302, + /* UPC extension. */ + DW_AT_upc_threads_scaled = 0x3210, + /* PGI (STMicroelectronics) extensions. */ + DW_AT_PGI_lbase = 0x3a00, + DW_AT_PGI_soffset = 0x3a01, + DW_AT_PGI_lstride = 0x3a02 + }; + +/* Location atom names and codes. */ +enum dwarf_location_atom + { + DW_OP_addr = 0x03, + DW_OP_deref = 0x06, + DW_OP_const1u = 0x08, + DW_OP_const1s = 0x09, + DW_OP_const2u = 0x0a, + DW_OP_const2s = 0x0b, + DW_OP_const4u = 0x0c, + DW_OP_const4s = 0x0d, + DW_OP_const8u = 0x0e, + DW_OP_const8s = 0x0f, + DW_OP_constu = 0x10, + DW_OP_consts = 0x11, + DW_OP_dup = 0x12, + DW_OP_drop = 0x13, + DW_OP_over = 0x14, + DW_OP_pick = 0x15, + DW_OP_swap = 0x16, + DW_OP_rot = 0x17, + DW_OP_xderef = 0x18, + DW_OP_abs = 0x19, + DW_OP_and = 0x1a, + DW_OP_div = 0x1b, + DW_OP_minus = 0x1c, + DW_OP_mod = 0x1d, + DW_OP_mul = 0x1e, + DW_OP_neg = 0x1f, + DW_OP_not = 0x20, + DW_OP_or = 0x21, + DW_OP_plus = 0x22, + DW_OP_plus_uconst = 0x23, + DW_OP_shl = 0x24, + DW_OP_shr = 0x25, + DW_OP_shra = 0x26, + DW_OP_xor = 0x27, + DW_OP_bra = 0x28, + DW_OP_eq = 0x29, + DW_OP_ge = 0x2a, + DW_OP_gt = 0x2b, + DW_OP_le = 0x2c, + DW_OP_lt = 0x2d, + DW_OP_ne = 0x2e, + DW_OP_skip = 0x2f, + DW_OP_lit0 = 0x30, + DW_OP_lit1 = 0x31, + DW_OP_lit2 = 0x32, + DW_OP_lit3 = 0x33, + DW_OP_lit4 = 0x34, + DW_OP_lit5 = 0x35, + DW_OP_lit6 = 0x36, + DW_OP_lit7 = 0x37, + DW_OP_lit8 = 0x38, + DW_OP_lit9 = 0x39, + DW_OP_lit10 = 0x3a, + DW_OP_lit11 = 0x3b, + DW_OP_lit12 = 0x3c, + DW_OP_lit13 = 0x3d, + DW_OP_lit14 = 0x3e, + DW_OP_lit15 = 0x3f, + DW_OP_lit16 = 0x40, + DW_OP_lit17 = 0x41, + DW_OP_lit18 = 0x42, + DW_OP_lit19 = 0x43, + DW_OP_lit20 = 0x44, + DW_OP_lit21 = 0x45, + DW_OP_lit22 = 0x46, + DW_OP_lit23 = 0x47, + DW_OP_lit24 = 0x48, + DW_OP_lit25 = 0x49, + DW_OP_lit26 = 0x4a, + DW_OP_lit27 = 0x4b, + DW_OP_lit28 = 0x4c, + DW_OP_lit29 = 0x4d, + DW_OP_lit30 = 0x4e, + DW_OP_lit31 = 0x4f, + DW_OP_reg0 = 0x50, + DW_OP_reg1 = 0x51, + DW_OP_reg2 = 0x52, + DW_OP_reg3 = 0x53, + DW_OP_reg4 = 0x54, + DW_OP_reg5 = 0x55, + DW_OP_reg6 = 0x56, + DW_OP_reg7 = 0x57, + DW_OP_reg8 = 0x58, + DW_OP_reg9 = 0x59, + DW_OP_reg10 = 0x5a, + DW_OP_reg11 = 0x5b, + DW_OP_reg12 = 0x5c, + DW_OP_reg13 = 0x5d, + DW_OP_reg14 = 0x5e, + DW_OP_reg15 = 0x5f, + DW_OP_reg16 = 0x60, + DW_OP_reg17 = 0x61, + DW_OP_reg18 = 0x62, + DW_OP_reg19 = 0x63, + DW_OP_reg20 = 0x64, + DW_OP_reg21 = 0x65, + DW_OP_reg22 = 0x66, + DW_OP_reg23 = 0x67, + DW_OP_reg24 = 0x68, + DW_OP_reg25 = 0x69, + DW_OP_reg26 = 0x6a, + DW_OP_reg27 = 0x6b, + DW_OP_reg28 = 0x6c, + DW_OP_reg29 = 0x6d, + DW_OP_reg30 = 0x6e, + DW_OP_reg31 = 0x6f, + DW_OP_breg0 = 0x70, + DW_OP_breg1 = 0x71, + DW_OP_breg2 = 0x72, + DW_OP_breg3 = 0x73, + DW_OP_breg4 = 0x74, + DW_OP_breg5 = 0x75, + DW_OP_breg6 = 0x76, + DW_OP_breg7 = 0x77, + DW_OP_breg8 = 0x78, + DW_OP_breg9 = 0x79, + DW_OP_breg10 = 0x7a, + DW_OP_breg11 = 0x7b, + DW_OP_breg12 = 0x7c, + DW_OP_breg13 = 0x7d, + DW_OP_breg14 = 0x7e, + DW_OP_breg15 = 0x7f, + DW_OP_breg16 = 0x80, + DW_OP_breg17 = 0x81, + DW_OP_breg18 = 0x82, + DW_OP_breg19 = 0x83, + DW_OP_breg20 = 0x84, + DW_OP_breg21 = 0x85, + DW_OP_breg22 = 0x86, + DW_OP_breg23 = 0x87, + DW_OP_breg24 = 0x88, + DW_OP_breg25 = 0x89, + DW_OP_breg26 = 0x8a, + DW_OP_breg27 = 0x8b, + DW_OP_breg28 = 0x8c, + DW_OP_breg29 = 0x8d, + DW_OP_breg30 = 0x8e, + DW_OP_breg31 = 0x8f, + DW_OP_regx = 0x90, + DW_OP_fbreg = 0x91, + DW_OP_bregx = 0x92, + DW_OP_piece = 0x93, + DW_OP_deref_size = 0x94, + DW_OP_xderef_size = 0x95, + DW_OP_nop = 0x96, + /* DWARF 3 extensions. */ + DW_OP_push_object_address = 0x97, + DW_OP_call2 = 0x98, + DW_OP_call4 = 0x99, + DW_OP_call_ref = 0x9a, + DW_OP_form_tls_address = 0x9b, + DW_OP_call_frame_cfa = 0x9c, + DW_OP_bit_piece = 0x9d, + + /* DWARF 4 extensions. */ + DW_OP_implicit_value = 0x9e, + DW_OP_stack_value = 0x9f, + + DW_OP_lo_user = 0xe0, /* Implementation-defined range start. */ + DW_OP_hi_user = 0xff, /* Implementation-defined range end. */ + + /* GNU extensions. */ + DW_OP_GNU_push_tls_address = 0xe0, + /* The following is for marking variables that are uninitialized. */ + DW_OP_GNU_uninit = 0xf0, + DW_OP_GNU_encoded_addr = 0xf1, + /* The GNU implicit pointer extension. + See http://www.dwarfstd.org/ShowIssue.php?issue=100831.1&type=open . */ + DW_OP_GNU_implicit_pointer = 0xf2, + /* The GNU entry value extension. + See http://www.dwarfstd.org/ShowIssue.php?issue=100909.1&type=open . */ + DW_OP_GNU_entry_value = 0xf3, + /* HP extensions. */ + DW_OP_HP_unknown = 0xe0, /* Ouch, the same as GNU_push_tls_address. */ + DW_OP_HP_is_value = 0xe1, + DW_OP_HP_fltconst4 = 0xe2, + DW_OP_HP_fltconst8 = 0xe3, + DW_OP_HP_mod_range = 0xe4, + DW_OP_HP_unmod_range = 0xe5, + DW_OP_HP_tls = 0xe6, + /* PGI (STMicroelectronics) extensions. */ + DW_OP_PGI_omp_thread_num = 0xf8 + }; + +/* Type encodings. */ +enum dwarf_type + { + DW_ATE_void = 0x0, + DW_ATE_address = 0x1, + DW_ATE_boolean = 0x2, + DW_ATE_complex_float = 0x3, + DW_ATE_float = 0x4, + DW_ATE_signed = 0x5, + DW_ATE_signed_char = 0x6, + DW_ATE_unsigned = 0x7, + DW_ATE_unsigned_char = 0x8, + /* DWARF 3. */ + DW_ATE_imaginary_float = 0x9, + DW_ATE_packed_decimal = 0xa, + DW_ATE_numeric_string = 0xb, + DW_ATE_edited = 0xc, + DW_ATE_signed_fixed = 0xd, + DW_ATE_unsigned_fixed = 0xe, + DW_ATE_decimal_float = 0xf, + /* DWARF 4. */ + DW_ATE_UTF = 0x10, + + DW_ATE_lo_user = 0x80, + DW_ATE_hi_user = 0xff, + + /* HP extensions. */ + DW_ATE_HP_float80 = 0x80, /* Floating-point (80 bit). */ + DW_ATE_HP_complex_float80 = 0x81, /* Complex floating-point (80 bit). */ + DW_ATE_HP_float128 = 0x82, /* Floating-point (128 bit). */ + DW_ATE_HP_complex_float128 = 0x83, /* Complex fp (128 bit). */ + DW_ATE_HP_floathpintel = 0x84, /* Floating-point (82 bit IA64). */ + DW_ATE_HP_imaginary_float80 = 0x85, + DW_ATE_HP_imaginary_float128 = 0x86, + DW_ATE_HP_VAX_float = 0x88, /* F or G floating. */ + DW_ATE_HP_VAX_float_d = 0x89, /* D floating. */ + DW_ATE_HP_packed_decimal = 0x8a, /* Cobol. */ + DW_ATE_HP_zoned_decimal = 0x8b, /* Cobol. */ + DW_ATE_HP_edited = 0x8c, /* Cobol. */ + DW_ATE_HP_signed_fixed = 0x8d, /* Cobol. */ + DW_ATE_HP_unsigned_fixed = 0x8e, /* Cobol. */ + DW_ATE_HP_VAX_complex_float = 0x8f, /* F or G floating complex. */ + DW_ATE_HP_VAX_complex_float_d = 0x90 /* D floating complex. */ + }; + +/* Decimal sign encodings. */ +enum dwarf_decimal_sign_encoding + { + /* DWARF 3. */ + DW_DS_unsigned = 0x01, + DW_DS_leading_overpunch = 0x02, + DW_DS_trailing_overpunch = 0x03, + DW_DS_leading_separate = 0x04, + DW_DS_trailing_separate = 0x05 + }; + +/* Endianity encodings. */ +enum dwarf_endianity_encoding + { + /* DWARF 3. */ + DW_END_default = 0x00, + DW_END_big = 0x01, + DW_END_little = 0x02, + + DW_END_lo_user = 0x40, + DW_END_hi_user = 0xff + }; + +/* Array ordering names and codes. */ +enum dwarf_array_dim_ordering + { + DW_ORD_row_major = 0, + DW_ORD_col_major = 1 + }; + +/* Access attribute. */ +enum dwarf_access_attribute + { + DW_ACCESS_public = 1, + DW_ACCESS_protected = 2, + DW_ACCESS_private = 3 + }; + +/* Visibility. */ +enum dwarf_visibility_attribute + { + DW_VIS_local = 1, + DW_VIS_exported = 2, + DW_VIS_qualified = 3 + }; + +/* Virtuality. */ +enum dwarf_virtuality_attribute + { + DW_VIRTUALITY_none = 0, + DW_VIRTUALITY_virtual = 1, + DW_VIRTUALITY_pure_virtual = 2 + }; + +/* Case sensitivity. */ +enum dwarf_id_case + { + DW_ID_case_sensitive = 0, + DW_ID_up_case = 1, + DW_ID_down_case = 2, + DW_ID_case_insensitive = 3 + }; + +/* Calling convention. */ +enum dwarf_calling_convention + { + DW_CC_normal = 0x1, + DW_CC_program = 0x2, + DW_CC_nocall = 0x3, + + DW_CC_lo_user = 0x40, + DW_CC_hi_user = 0xff, + + DW_CC_GNU_renesas_sh = 0x40, + DW_CC_GNU_borland_fastcall_i386 = 0x41, + + /* This DW_CC_ value is not currently generated by any toolchain. It is + used internally to GDB to indicate OpenCL C functions that have been + compiled with the IBM XL C for OpenCL compiler and use a non-platform + calling convention for passing OpenCL C vector types. This value may + be changed freely as long as it does not conflict with any other DW_CC_ + value defined here. */ + DW_CC_GDB_IBM_OpenCL = 0xff + }; + +/* Inline attribute. */ +enum dwarf_inline_attribute + { + DW_INL_not_inlined = 0, + DW_INL_inlined = 1, + DW_INL_declared_not_inlined = 2, + DW_INL_declared_inlined = 3 + }; + +/* Discriminant lists. */ +enum dwarf_discrim_list + { + DW_DSC_label = 0, + DW_DSC_range = 1 + }; + +/* Line number opcodes. */ +enum dwarf_line_number_ops + { + DW_LNS_extended_op = 0, + DW_LNS_copy = 1, + DW_LNS_advance_pc = 2, + DW_LNS_advance_line = 3, + DW_LNS_set_file = 4, + DW_LNS_set_column = 5, + DW_LNS_negate_stmt = 6, + DW_LNS_set_basic_block = 7, + DW_LNS_const_add_pc = 8, + DW_LNS_fixed_advance_pc = 9, + /* DWARF 3. */ + DW_LNS_set_prologue_end = 10, + DW_LNS_set_epilogue_begin = 11, + DW_LNS_set_isa = 12 + }; + +/* Line number extended opcodes. */ +enum dwarf_line_number_x_ops + { + DW_LNE_end_sequence = 1, + DW_LNE_set_address = 2, + DW_LNE_define_file = 3, + DW_LNE_set_discriminator = 4, + /* HP extensions. */ + DW_LNE_HP_negate_is_UV_update = 0x11, + DW_LNE_HP_push_context = 0x12, + DW_LNE_HP_pop_context = 0x13, + DW_LNE_HP_set_file_line_column = 0x14, + DW_LNE_HP_set_routine_name = 0x15, + DW_LNE_HP_set_sequence = 0x16, + DW_LNE_HP_negate_post_semantics = 0x17, + DW_LNE_HP_negate_function_exit = 0x18, + DW_LNE_HP_negate_front_end_logical = 0x19, + DW_LNE_HP_define_proc = 0x20, + DW_LNE_HP_source_file_correlation = 0x80, + + DW_LNE_lo_user = 0x80, + DW_LNE_hi_user = 0xff + }; + +/* Sub-opcodes for DW_LNE_HP_source_file_correlation. */ +enum dwarf_line_number_hp_sfc_ops + { + DW_LNE_HP_SFC_formfeed = 1, + DW_LNE_HP_SFC_set_listing_line = 2, + DW_LNE_HP_SFC_associate = 3 + }; + +/* Call frame information. */ +enum dwarf_call_frame_info + { + DW_CFA_advance_loc = 0x40, + DW_CFA_offset = 0x80, + DW_CFA_restore = 0xc0, + DW_CFA_nop = 0x00, + DW_CFA_set_loc = 0x01, + DW_CFA_advance_loc1 = 0x02, + DW_CFA_advance_loc2 = 0x03, + DW_CFA_advance_loc4 = 0x04, + DW_CFA_offset_extended = 0x05, + DW_CFA_restore_extended = 0x06, + DW_CFA_undefined = 0x07, + DW_CFA_same_value = 0x08, + DW_CFA_register = 0x09, + DW_CFA_remember_state = 0x0a, + DW_CFA_restore_state = 0x0b, + DW_CFA_def_cfa = 0x0c, + DW_CFA_def_cfa_register = 0x0d, + DW_CFA_def_cfa_offset = 0x0e, + /* DWARF 3. */ + DW_CFA_def_cfa_expression = 0x0f, + DW_CFA_expression = 0x10, + DW_CFA_offset_extended_sf = 0x11, + DW_CFA_def_cfa_sf = 0x12, + DW_CFA_def_cfa_offset_sf = 0x13, + DW_CFA_val_offset = 0x14, + DW_CFA_val_offset_sf = 0x15, + DW_CFA_val_expression = 0x16, + + DW_CFA_lo_user = 0x1c, + DW_CFA_hi_user = 0x3f, + + /* SGI/MIPS specific. */ + DW_CFA_MIPS_advance_loc8 = 0x1d, + /* GNU extensions. */ + DW_CFA_GNU_window_save = 0x2d, + DW_CFA_GNU_args_size = 0x2e, + DW_CFA_GNU_negative_offset_extended = 0x2f + }; + +#define DW_CIE_ID 0xffffffff +#define DW64_CIE_ID 0xffffffffffffffffULL +#define DW_CIE_VERSION 1 + +#define DW_CFA_extended 0 + +#define DW_CHILDREN_no 0x00 +#define DW_CHILDREN_yes 0x01 + +#define DW_ADDR_none 0 + +/* Source language names and codes. */ +enum dwarf_source_language + { + DW_LANG_C89 = 0x0001, + DW_LANG_C = 0x0002, + DW_LANG_Ada83 = 0x0003, + DW_LANG_C_plus_plus = 0x0004, + DW_LANG_Cobol74 = 0x0005, + DW_LANG_Cobol85 = 0x0006, + DW_LANG_Fortran77 = 0x0007, + DW_LANG_Fortran90 = 0x0008, + DW_LANG_Pascal83 = 0x0009, + DW_LANG_Modula2 = 0x000a, + /* DWARF 3. */ + DW_LANG_Java = 0x000b, + DW_LANG_C99 = 0x000c, + DW_LANG_Ada95 = 0x000d, + DW_LANG_Fortran95 = 0x000e, + DW_LANG_PLI = 0x000f, + DW_LANG_ObjC = 0x0010, + DW_LANG_ObjC_plus_plus = 0x0011, + DW_LANG_UPC = 0x0012, + DW_LANG_D = 0x0013, + /* DWARF 4. */ + DW_LANG_Python = 0x0014, + /* DWARF 5. */ + DW_LANG_Go = 0x0016, + + DW_LANG_lo_user = 0x8000, /* Implementation-defined range start. */ + DW_LANG_hi_user = 0xffff, /* Implementation-defined range start. */ + + /* MIPS. */ + DW_LANG_Mips_Assembler = 0x8001, + /* UPC. */ + DW_LANG_Upc = 0x8765, + /* HP extensions. */ + DW_LANG_HP_Bliss = 0x8003, + DW_LANG_HP_Basic91 = 0x8004, + DW_LANG_HP_Pascal91 = 0x8005, + DW_LANG_HP_IMacro = 0x8006, + DW_LANG_HP_Assembler = 0x8007 + }; + +/* Names and codes for macro information. */ +enum dwarf_macinfo_record_type + { + DW_MACINFO_define = 1, + DW_MACINFO_undef = 2, + DW_MACINFO_start_file = 3, + DW_MACINFO_end_file = 4, + DW_MACINFO_vendor_ext = 255 + }; + +/* @@@ For use with GNU frame unwind information. */ + +#define DW_EH_PE_absptr 0x00 +#define DW_EH_PE_omit 0xff + +#define DW_EH_PE_uleb128 0x01 +#define DW_EH_PE_udata2 0x02 +#define DW_EH_PE_udata4 0x03 +#define DW_EH_PE_udata8 0x04 +#define DW_EH_PE_sleb128 0x09 +#define DW_EH_PE_sdata2 0x0A +#define DW_EH_PE_sdata4 0x0B +#define DW_EH_PE_sdata8 0x0C +#define DW_EH_PE_signed 0x08 + +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_textrel 0x20 +#define DW_EH_PE_datarel 0x30 +#define DW_EH_PE_funcrel 0x40 +#define DW_EH_PE_aligned 0x50 + +#define DW_EH_PE_indirect 0x80 + +#endif /* _DWARF2_H */ diff --git a/external/gpl3/gdb/dist/include/dyn-string.h b/external/gpl3/gdb/dist/include/dyn-string.h new file mode 100644 index 000000000000..2b147271e5f8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/dyn-string.h @@ -0,0 +1,73 @@ +/* An abstract string datatype. + Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005, 2009 + Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef DYN_STRING_H +#define DYN_STRING_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct dyn_string +{ + int allocated; /* The amount of space allocated for the string. */ + int length; /* The actual length of the string. */ + char *s; /* The string itself, NUL-terminated. */ +}* dyn_string_t; + +/* The length STR, in bytes, not including the terminating NUL. */ +#define dyn_string_length(STR) \ + ((STR)->length) + +/* The NTBS in which the contents of STR are stored. */ +#define dyn_string_buf(STR) \ + ((STR)->s) + +/* Compare DS1 to DS2 with strcmp. */ +#define dyn_string_compare(DS1, DS2) \ + (strcmp ((DS1)->s, (DS2)->s)) + + +extern int dyn_string_init (struct dyn_string *, int); +extern dyn_string_t dyn_string_new (int); +extern void dyn_string_delete (dyn_string_t); +extern char *dyn_string_release (dyn_string_t); +extern dyn_string_t dyn_string_resize (dyn_string_t, int); +extern void dyn_string_clear (dyn_string_t); +extern int dyn_string_copy (dyn_string_t, dyn_string_t); +extern int dyn_string_copy_cstr (dyn_string_t, const char *); +extern int dyn_string_prepend (dyn_string_t, dyn_string_t); +extern int dyn_string_prepend_cstr (dyn_string_t, const char *); +extern int dyn_string_insert (dyn_string_t, int, dyn_string_t); +extern int dyn_string_insert_cstr (dyn_string_t, int, const char *); +extern int dyn_string_insert_char (dyn_string_t, int, int); +extern int dyn_string_append (dyn_string_t, dyn_string_t); +extern int dyn_string_append_cstr (dyn_string_t, const char *); +extern int dyn_string_append_char (dyn_string_t, int); +extern int dyn_string_substring (dyn_string_t, dyn_string_t, int, int); +extern int dyn_string_eq (dyn_string_t, dyn_string_t); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined (DYN_STRING_H) */ diff --git a/external/gpl3/gdb/dist/include/elf/ChangeLog b/external/gpl3/gdb/dist/include/elf/ChangeLog new file mode 100644 index 000000000000..752730eca209 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ChangeLog @@ -0,0 +1,1437 @@ +2011-03-31 Bernd Schmidt + + * tic6x.h (R_C6000_JUMP_SPLOT, R_C6000_EHTYPE, + R_C6000_PCR_H16, R_C6000_PCR_L16): New relocs. + (SHN_TIC6X_SCOMMON): Define. + +2011-03-31 Tristan Gingold + + * ia64.h (Elf64_External_VMS_Note): New struct. + (NT_VMS_MHD, NT_VMS_LNM, NT_VMS_SRC, NT_VMS_TITLE, NT_VMS_EIDC) + (NT_VMS_FPMODE, NT_VMS_LINKTIME, NT_VMS_IMGNAM, NT_VMS_IMGID) + (NT_VMS_LINKID, NT_VMS_IMGBID, NT_VMS_GSTNAM, NT_VMS_ORIG_DYN) + (NT_VMS_PATCHTIME) New macros. + +2011-03-14 Richard Sandiford + + * arm.h (R_ARM_IRELATIVE): New relocation. + +2011-03-14 Richard Sandiford + + * internal.h (elf_internal_sym): Add st_target_internal. + * arm.h (arm_st_branch_type): New enum. + (ARM_SYM_BRANCH_TYPE): New macro. + +2011-03-10 Nick Clifton + + * common.h (EM_V850): V850s now supplied by Renesas. + +2011-02-25 Alan Modra + + PR 12516 + * internal.h (ELF_SECTION_IN_SEGMENT_1): Don't match zero size + sections at start or end of PT_DYNAMIC. + +2011-01-10 Nathan Sidwell + Glauber de Oliveira Costa + + * arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL, + R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New + relocations. + +2010-11-11 Mingming Sun + + * mips.h (E_MIPS_MACH_LS3A): Defined. + +2010-11-02 Joseph Myers + + * tic6x-attrs.h (Tag_ABI_wchar_t, Tag_ABI_stack_align_needed, + Tag_ABI_stack_align_preserved, Tag_ABI_PID, Tag_ABI_PIC, + Tag_ABI_array_object_alignment, + Tag_ABI_array_object_align_expected, Tag_ABI_conformance): Define. + +2010-10-29 Joseph Myers + + * tic6x-attrs.h (Tag_ABI_compatibility): Define. + +2010-10-29 Bernd Schmidt + Joseph Myers + + * tic6x-attrs.h (Tag_ABI_DSBT): New. + +2010-10-21 Joseph Myers + + * tic6x-attrs.h (Tag_C6XABI_Tag_CPU_arch): Change to Tag_ISA, + value 4. + * tic6x.h (Values for Tag_C6XABI_Tag_CPU_arch): Rename for + attribute renaming. + +2010-07-23 Naveen.H.S + Ina Pandit + + * v850.h: Add support for V850E2 and V850E2V3. + (v850_reloc_type): Update the newly added relocations + +2010-07-20 Alan Modra + + * internal.h (ELF_TBSS_SPECIAL): New macro, extracted from.. + (ELF_SECTION_SIZE): ..here. + (ELF_SECTION_IN_SEGMENT_1): Add "strict" arg. + (ELF_SECTION_IN_SEGMENT_STRICT): New macro. + +2010-06-25 Alan Modra + + * ppc64.h (R_PPC64_LO_DS_OPT): Define. + +2010-06-15 Joseph Myers + + * tic6x-attrs.h: New. + * tic6x.h: Include elf/tic6x-attrs.h for attribute table. + (C6XABI_Tag_CPU_arch_none, C6XABI_Tag_CPU_arch_C62X, + C6XABI_Tag_CPU_arch_C67X, C6XABI_Tag_CPU_arch_C67XP, + C6XABI_Tag_CPU_arch_C64X, C6XABI_Tag_CPU_arch_C64XP, + C6XABI_Tag_CPU_arch_C674X): Define. + +2010-06-11 Tristan Gingold + + * ia64.h (EF_IA_64_VMS_COMCOD, EF_IA_64_VMS_COMCOD_SUCCESS) + (EF_IA_64_VMS_COMCOD_WARNING, EF_IA_64_VMS_COMCOD_ERROR) + (EF_IA_64_VMS_COMCOD_ABORT, EF_IA_64_VMS_LINKAGES): Define. + (VMS_LF_CALL_DEBUG, VMS_LF_NOP0BUFS, VMS_LF_P0IMAGE) + (VMS_LF_MKTHREADS, VMS_LF_UPCALLS, VMS_LF_IMGSTA) + (VMS_LF_INITIALIZE, VMS_LF_MAIN, VMS_LF_EXE_INIT) + (VMS_LF_TBK_IN_IMG, VMS_LF_DBG_IN_IMG, VMS_LF_TBK_IN_DSF) + (VMS_LF_DBG_IN_DSF, VMS_LF_SIGNATURES, VMS_LF_REL_SEG_OFF): Define. + (VMS_STO_VISIBILITY, VMS_ST_VISIBILITY, VMS_STO_FUNC_TYPE) + (VMS_ST_FUNC_TYPE, VMS_SFT_CODE_ADDR, VMS_SFT_SYMV_IDX) + (VMS_SFT_FD, VMS_SFT_RESERVE, VMS_STO_LINKAGE, VMS_ST_LINKAGE) + (VMS_STL_IGNORE, VMS_STL_RESERVE, VMS_STL_STD, VMS_STL_LNK): Define. + (Elf64_External_VMS_IMAGE_FIXUP): New declaration. + (Elf64_External_VMS_IMAGE_RELA): Ditto. + (R_IA64_VMS_DIR8, R_IA64_VMS_DIR16LSB, R_IA64_VMS_CALL_SIGNATURE) + (R_IA64_VMS_EXECLET_FUNC, R_IA64_VMS_EXECLET_DATA, R_IA64_VMS_FIX8) + (R_IA64_VMS_FIX16, R_IA64_VMS_FIX32, R_IA64_VMS_FIX64) + (R_IA64_VMS_FIXFD, R_IA64_VMS_ACC_LOAD, R_IA64_VMS_ACC_ADD) + (R_IA64_VMS_ACC_SUB, R_IA64_VMS_ACC_MUL, R_IA64_VMS_ACC_DIV) + (R_IA64_VMS_ACC_AND, R_IA64_VMS_ACC_IOR, R_IA64_VMS_ACC_EOR) + (R_IA64_VMS_ACC_ASH, R_IA64_VMS_ACC_STO8, R_IA64_VMS_ACC_STO16LSH) + (R_IA64_VMS_ACC_STO32LSH, R_IA64_VMS_ACC_STO64LSH): New. + +2010-05-25 Daniel Jacobowitz + Joseph Myers + Andrew Stubbs + + * sh.h (EF_SH_PIC, EF_SH_FDPIC): Define. + (R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New. Adjust + other invalid ranges. + (R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20) + (R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC) + (R_SH_FUNCDESC_VALUE): New. + +2010-05-18 H.J. Lu + + PR gas/11600 + * common.h (SHF_EXCLUDE): New. + + * i370.h (SHF_EXCLUDE): Removed. + * or32.h (SHF_EXCLUDE): Likewise. + * ppc.h (SHF_EXCLUDE): Likewise. + * sparc.h (SHF_EXCLUDE): Likewise. + +2010-04-23 Alan Modra + + * internal.h (ELF_SECTION_SIZE): Protect macro args with parentheses. + Invert logic to clarify test for .tbss. + (ELF_IS_SECTION_IN_SEGMENT): Rename to.. + (ELF_SECTION_IN_SEGMENT_1): ..this. Add check_vma param. Protect + macro args with parentheses. + (ELF_SECTION_IN_SEGMENT): Define. + (ELF_IS_SECTION_IN_SEGMENT_FILE): Delete. + (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Delete. + +2010-04-15 Matthew Gretton-Dann + + * arm.h (Tag_FP_arch, Tag_ABI_align_needed, Tag_ABI_align_preserved, + Tag_FP_HP_extension): Add new ABI attribute tags. + +2010-04-15 Nick Clifton + + * alpha.h: Update copyright notice to use GPLv3. + * arc.h: Likewise. + * arm.h: Likewise. + * avr.h: Likewise. + * bfin.h: Likewise. + * common.h: Likewise. + * cr16.h: Likewise. + * cr16c.h: Likewise. + * cris.h: Likewise. + * crx.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * dlx.h: Likewise. + * dwarf.h: Likewise. + * external.h: Likewise. + * fr30.h: Likewise. + * frv.h: Likewise. + * h8.h: Likewise. + * hppa.h: Likewise. + * i370.h: Likewise. + * i386.h: Likewise. + * i860.h: Likewise. + * i960.h: Likewise. + * ia64.h: Likewise. + * internal.h: Likewise. + * ip2k.h: Likewise. + * iq2000.h: Likewise. + * lm32.h: Likewise. + * m32c.h: Likewise. + * m32r.h: Likewise. + * m68hc11.h: Likewise. + * m68k.h: Likewise. + * mcore.h: Likewise. + * mep.h: Likewise. + * microblaze.h: Likewise. + * mips.h: Likewise. + * mmix.h: Likewise. + * mn10200.h: Likewise. + * moxie.h: Likewise. + * msp430.h: Likewise. + * mt.h: Likewise. + * openrisc.h: Likewise. + * or32.h: Likewise. + * pj.h: Likewise. + * ppc.h: Likewise. + * ppc64.h: Likewise. + * reloc-macros.h: Likewise. + * rx.h: Likewise. + * s390.h: Likewise. + * sh.h: Likewise. + * sparc.h: Likewise. + * spu.h: Likewise. + * v850.h: Likewise. + * vax.h: Likewise. + * vxworks.h: Likewise. + * x86-64.h: Likewise. + * xc16x.h: Likewise. + * xstormy16.h: Likewise. + * xtensa.h: Likewise. + +2010-04-08 David Stubbs + + * internal.h (ELF_IS_SECTION_IN_SEGMENT): PT_PHDR program headers + cannot contain any sections. + +2010-03-25 Joseph Myers + + * common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define. + * tic6x.h: New. + +2010-03-05 Rainer Orth + + * common.h (VER_FLG_*): Document. + (VER_FLG_INFO): Define. + +2010-02-23 Andrew Zabolotny + + PR binutils/11297 + * avr.h: (R_AVR_8): New relocation number. + +2010-02-18 Matthew Gretton-Dann + + * arm.h (Tag_MPextension_use): Renumber. + (Tag_DIV_use): Add. + (Tag_MPextension_use_legacy): Likewise. + +2010-02-09 Michael Holzheu + + * common.h (NT_S390_TIMER, NT_S390_TODCMP, NT_S390_TODPREG, + NT_S390_CTRS and NT_S390_PREFIX): Define. + +2010-02-08 David S. Miller + + * sparc.h (R_SPARC_JMP_IREL, R_SPARC_IRELATIVE): Define. + +2010-02-02 H.J. Lu + + * common.h (NT_386_XSTATE): New. + +2010-01-21 Andreas Krebbel + + * s390.h (EF_S390_HIGH_GPRS): Added macro definition. + +2010-01-19 Daisuke Hatayama + + * common.h (PN_XNUM): Define. + +2009-12-18 Ulrich Weigand + + * common.h (NT_S390_HIGH_GPRS): Define. + +2009-12-17 Alan Modra + + * ppc.h (R_PPC_RELAX32, R_PPC_RELAX32PC, R_PPC_RELAX32_PLT, + R_PPC_RELAX32PC_PLT): Delete. + (R_PPC_RELAX, R_PPC_RELAX_PLT, R_PPC_RELAX_PLTREL24): Define. + +2009-11-28 Joseph Myers + + * common.h (ELFOSABI_FENIXOS, EM_TI_C6000, EM_TI_C2000, + EM_TI_C5500, EM_CUDA): Define. + (EM_res140, EM_res141, EM_res142): Remove. + +2009-11-17 Paul Brook + Daniel Jacobowitz + + * arm.h (TAG_CPU_ARCH_V7E_M): Define. + +2009-09-29 DJ Delorie + + * rx.h: New file. + +2009-09-21 Alan Modra + + * ppc.h (DT_PPC_TLSOPT): Define. + * ppc64.h (DT_PPC64_TLSOPT): Define. + +2009-08-10 Daniel Gutson + + * arm.h: (SHT_ARM_DEBUGOVERLAY): New define. + (SHT_ARM_OVERLAYSECTION): New define. + +2006-08-09 Bernd Schmidt + + From Mike Frysinger + * bfin.h (R_BFIN_UNUSED, R_BFIN_PCREL5M2, R_BFIN_UNUSED1, + R_BFIN_PCREL10, R_BFIN_PCREL12_JUMP, R_BFIN_RIMM16, + R_BFIN_LUIMM16, R_BFIN_HUIMM16, R_BFIN_PCREL12_JUMP_S, + R_BFIN_PCREL24_JUMP_X, R_BFIN_PCREL24, R_BFIN_UNUSEDB, + R_BFIN_UNUSEDC, R_BFIN_PCREL24_JUMP_L, R_BFIN_PCREL24_CALL_X, + R_BFIN_VAR_EQ_SYMB, R_BFIN_BYTE_DATA, R_BFIN_BYTE2_DATA, + R_BFIN_BYTE4_DATA, R_BFIN_PCREL11, R_BFIN_PUSH, R_BFIN_CONST, + R_BFIN_ADD, R_BFIN_SUB, R_BFIN_MULT, R_BFIN_DIV, R_BFIN_MOD, + R_BFIN_LSHIFT, R_BFIN_RSHIFT, R_BFIN_AND, R_BFIN_OR, R_BFIN_XOR, + R_BFIN_LAND, R_BFIN_LOR, R_BFIN_LEN, R_BFIN_NEG, R_BFIN_COMP, + R_BFIN_PAGE, R_BFIN_HWPAGE, R_BFIN_ADDR, R_BFIN_PLTPLC, + R_BFIN_GOT, R_BFIN_MAX): Renamed from R_unused0, R_pcrel5ms, + R_unused1, R_pcrel10, R_pcrel12_jump, R_rimm16, R_luimm16, + R_huimm16, R_pcrel12_jump_s, R_pcrel24_jump_x, R_pcrel24, + R_unusedb, R_unusedc, R_pcrel24_jump_l, R_pcrel24_call_x, + R_var_eq_symb, R_byte_data, R_byte2_data, R_byte4_data, R_pcrel11, + R_push, R_const, R_add, R_sub, R_mult, R_div, R_mod, R_lshift, + R_rshift, R_and, R_or, R_xor, R_land, R_lor, R_len, R_neg, R_comp, + R_page, R_hwpage, R_addr, R_pltpc, R_got. + +2009-08-09 Michael Eager + + * elf/common.h: Define EM_resnnn reserved values. Add EM_AVR32, + EM_STM8, EM_TILE64, EM_TILEPRO. Change EM_MICROBLAZE. + +2009-08-06 Michael Eager + + * elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD. + * elf/microblaze.h: New reloc definitions. + +2009-07-30 Alan Modra + + * ppc64.h: Add R_PPC64_JMP_IREL, R_PPC64_REL16, R_PPC64_REL16_LO, + R_PPC64_REL16_HI, R_PPC64_REL16_HA. + +2009-07-25 H.J. Lu + + * common.h (EM_L1OM): New. + +2009-07-24 Trevor Smigiel + Alan Modra + + * spu.h (R_SPU_ADD_PIC): New. + +2009-07-23 Ulrich Drepper + + * common.h (STB_GNU_UNIQUE): Define. + +2009-07-10 Tom Tromey + + * dwarf2.h: Move to `..'. + +2009-07-10 H.J. Lu + + * dwarf2.h: Just include ../dwarf2.h. + +2009-07-10 Alan Modra + + * ppc.h (R_PPC_IRELATIVE): Add. + (R_PPC_RELAX32, R_PPC_RELAX32PC, + R_PPC_RELAX32_PLT, R_PPC_RELAX32PC_PLT): Renumber. + * ppc64.h (R_PPC64_IRELATIVE): Add. + +2009-07-03 Jakub Jelinek + + * dwarf2.h (enum dwarf_location_atom): Add DW_OP_implicit_value + and DW_OP_stack_value. + +2009-06-22 Alan Modra + + * ppc.h (R_PPC_RELAX*): Define as enum. + +2009-06-11 Anthony Green + + * moxie.h (R_MOXIE_PCREL10): New. + +2009-06-01 H.J. Lu + + PR ld/10205 + * i386.h (R_386_IRELATIVE): New. + * x86-64.h (R_X86_64_IRELATIVE): Likewise. + +2009-05-27 H.J. Lu + + * common.h: Update comments for dynamic tag ranges. + +2009-04-30 DJ Delorie + + * mep.h (EF_MEP_COP_*): New. + (EF_MEP_ALL_FLAGS): Add them. + +2009-04-30 Nick Clifton + + * common.h (STT_GNU_IFUNC): Define. + +2009-04-24 Cary Coutant + + * dwarf2.h (DW_LNE_set_discriminator): New enum value. + +2009-04-15 Anthony Green + + * common.h (EM_MOXIE): Define. + * moxie.h: New file. + +2009-04-07 DJ Delorie + + * mep.h (EF_MEP_CPU_C5): New. + +2009-04-01 H.J. Lu + + * common.h (EM_INTEL178): Removed. + (EM_INTEL179): Likewise. + (EM_ETPU): New. + (EM_SLE9X): Likewise. + (EM_INTEL181): Likewise. + (EM_INTEL182): Likewise. + +2009-03-31 H.J. Lu + + * common.h (EM_INTEL178): New. + (EM_INTEL179): Likewise. + (EM_INTEL180): Likewise. + +2009-03-20 Mikolaj Zalewski + + * common.h (SHT_GNU_INCREMENTAL_INPUTS): Define. + +2009-03-14 Mark Kettenis + + * common.h (NT_OPENBSD_PROCINFO, NT_OPENBSD_AUXV) + (NT_OPENBSD_REGS, NT_OPENBSD_FPREGS, NT_OPENBSD_XFPREGS) + (NT_OPENBSD_WCOOKIE): New defines. + +2009-03-16 Jan Kratochvil + + * common.h (AT_RANDOM): Define. + +2009-03-04 Alan Modra + + * ppc.h (R_PPC_TLSGD, R_PPC_TLSLD): Add new relocs. + * ppc64.h (R_PPC64_TLSGD, R_PPC64_TLSLD): Add new relocs. + +2009-03-02 Qinwei + + * score.h (RELOC_NUMBER): Add R_SCORE_IMM32. + * common.h (EM_SCORE_OLD): Define. + +2009-02-23 H.J. Lu + + * common.h (STB_LOPROC): Replace Application-specific with + Processor-specific in comments. + (STB_HIPROC): Likewise. + (STT_LOPROC): Likewise. + (STT_HIPROC): Likewise. + +2009-02-03 Sandip Matte + + * mips.h (E_MIPS_MACH_XLR): Define. + +2009-02-03 Maxim Kuvyrkov + + * m68k.h: Map TLS relocations to numbers. + +2009-01-15 Andrew Stubbs + Julian Brown + + * arm.h (TAG_CPU_ARCH_V6_M, TAG_CPU_ARCH_V6S_M): New defines. + (MAX_TAG_CPU_ARCH, TAG_CPU_ARCH_V4T_PLUS_V6_M): New defines. + (Tag_NEON_arch): Rename to Tag_Advanced_SIMD_arch to match ARM ABI + version 2.07. + (Tag_undefined39, Tag_nodefaults): New enum values. + (Tag_also_compatible_with, Tag_T2EE_use): Likewise. + (Tag_conformance, Tag_Virtualization_use): Likewise. + (Tag_undefined69, Tag_MPextension_use): Likewise. + +2009-01-15 Douglas B Rupp + + * ia64.h (SHT_IA_64_VMS_DISPLAY_NAME_INFO, EF_IA_64_ARCHVER_1): + New macros. Minor reformatting. + +2008-12-23 Jon Beniston + + * lm32.h: New file. + +2008-12-23 Nick Clifton + + * commmon.h (STT_IFUNC): Delete. + +2008-12-20 Hans-Peter Nilsson + + * cris.h (R_CRIS_32_IE): New relocation. + +2008-12-03 Nick Clifton + + * common.h (STT_IFUNC): Define. + +2008-11-27 M R Swami Reddy + + * cr16.h (R_CR16_GOT_REGREL20, R_CR16_GOTC_REGREL20 and + R_CR16_GLOB_DAT): New relocations. + +2008-11-25 Hans-Peter Nilsson + + * cris.h (R_CRIS_32_TPREL): Correct comment. + (R_CRIS_DTPMOD): Open up for use elsewhere than the fourth GOT entry. + +2008-11-18 Catherine Moore + + * arm.h (Tag_ABI_FP_16bit_format): Define. + +2008-11-14 Nathan Sidwell + + * internal.h (struct elf_segment_map): Add header_size field. + +2008-10-13 Ulrich Weigand + + * common.h (AT_BASE_PLATFORM, AT_EXECFN): Define. + +2008-10-10 Nathan Froyd + + * ppc.h: Add Tag_GNU_Power_ABI_Struct_Return. + +2008-10-04 Hans-Peter Nilsson + + * cris.h (R_CRIS_32_GOT_GD, R_CRIS_16_GOT_GD, R_CRIS_32_GD) + (R_CRIS_DTP, R_CRIS_32_DTPREL, R_CRIS_16_DTPREL, R_CRIS_DTPMOD) + (R_CRIS_32_GOT_TPREL, R_CRIS_16_GOT_TPREL, R_CRIS_32_TPREL) + (R_CRIS_16_TPREL): New relocations. + +2008-08-20 Bob Wilson + + * xtensa.h (R_XTENSA_TLSDESC_FN, R_XTENSA_TLSDESC_ARG) + (R_XTENSA_TLS_DTPOFF, R_XTENSA_TLS_TPOFF, R_XTENSA_TLS_FUNC) + (R_XTENSA_TLS_ARG, R_XTENSA_TLS_CALL): New. + +2008-08-08 Richard Sandiford + Daniel Jacobowitz + Catherine Moore + Mark Shinwell + + * mips.h (STO_MIPS_PLT, ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT) + (STO_MIPS_PIC, DT_MIPS_PLTGOT, DT_MIPS_RWPLT): New macros. + +2008-08-04 Markus Weiss + + * common.h (ELFOSABI_AROS): Update comment. + +2008-07-26 Michael Eager + + * ppc.h: Add description of single-precision. + +2008-07-21 Luis Machado + + * common.h: Define NT_PPC_VSX. + +2008-07-10 Richard Sandiford + + * mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. + +2008-06-18 M R Swami Reddy + + * common.h (EM_CR16): Correct value. + (EM_CR16): Rename to EM_CR16_OLD. + +2008-06-12 DJ Delorie + + * common.h (EM_M32C_NEW): Rename to EM_M32C. + (EM_M32C): Rename to EM_M32C_OLD. + +2008-06-12 Joseph Myers + + * common.h: Update e_machine table. + +2008-06-09 Takashi Yoshii + + * sh.h (EF_SH_BFD_TABLE): Set bfd_mach_sh for EF_SH_UNKNOWN. + +2008-06-09 Joseph Myers + + * common.h: Change registry@caldera.com to registry@sco.com. + +2008-05-21 Nick Clifton + + * reloc-macros.h: Add a comment about the use of the + END_RELOC_NUMBERS symbol as a sentinel value. + +2008-05-15 Christophe Lyon + + * arm.h (END_RELOC_NUMBERS): Provide a maximum value. + +2008-04-16 David S. Miller + + * elf/sparc.h (R_SPARC_GOTDATA_HIX22, + R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22, + R_SPARC_GOTDATA_OP_LOX10, R_SPARC_GOTDATA_OP, + R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_SIZE64): New relocs. + +2008-03-24 Ian Lance Taylor + + * common.h (NT_GNU_GOLD_VERSION): Define. + +2008-03-13 Alan Modra + + * internal.h (Elf_Internal_Shdr): Change sh_link and sh_info from + unsigned long to unsigned int. Change sh_addralign to bfd_vma. + Order struct as for external version. + +2008-03-12 Alan Modra + + PR 5900 + * common.h (SHN_BAD): Delete. + (SHN_LORESERVE .. SHN_HIRESERVE): Move to.. + * external.h: ..here. + * internal.h (SHN_LORESERVE, SHN_HIRESERVE): Define. + (SHN_LOPROC, SHN_HIPROC, SHN_LOOS, SHN_HIOS): Define. + (SHN_ABS, SHN_COMMON, SHN_XINDEX, SHN_BAD): Define. + +2008-03-12 Alan Modra + + * cr16c.h (SHN_CR16C_FCOMMON): Define using SHN_LORESERVE. + (SHN_CR16C_NCOMMON): Likewise. + * hppa.h (SHN_PARISC_ANSI_COMMON): Likewise. + (SHN_PARISC_HUGE_COMMON): Likewise. + * ia64.h (SHN_IA_64_ANSI_COMMON): Likewise. + (SHN_IA_64_VMS_SYMVEC): Define using SHN_LOOS. + * m32r.h (SHN_M32R_SCOMMON): Define using SHN_LORESERVE. + * mips.h (SHN_MIPS_ACOMMON, SHN_MIPS_TEXT): Likewise. + (SHN_MIPS_DATA, SHN_MIPS_SCOMMON, SHN_MIPS_SUNDEFINED): Likewise. + * score.h (SHN_SCORE_TEXT, SHN_SCORE_DATA): Likewise. + (SHN_SCORE_SCOMMON): Likewise. + * sparc.h (SHN_BEFORE, SHN_AFTER): Likewise. + * v850.h (SHN_V850_SCOMMON, SHN_V850_TCOMMON): Likewise. + (SHN_V850_ZCOMMON): Likewise. + * x86-64.h (SHN_X86_64_LCOMMON): Likewise. + +2008-03-03 Pallavi Tambay + + * dwarf2.h: (enum dwarf_location_atom): Add new DW_OP: + DW_OP_PGI_omp_thread_num. + +2008-02-04 Adam Nemet + + * mips.h: Update copyright. + (E_MIPS_MACH_OCTEON): New macro. + +2008-01-30 Tristan Gingold + + Add OpenVMS extensions. + * ia64.h (SHF_IA_64_VMS_GLOBAL, SHF_IA_64_VMS_OVERLAID) + (SHF_IA_64_VMS_SHARED, SHF_IA_64_VMS_VECTOR) + (SHF_IA_64_VMS_ALLOC_64BIT, SHF_IA_64_VMS_PROTECTED) + (SHT_IA_64_VMS_TRACE, SHT_IA_64_VMS_TIE_SIGNATURES) + (SHT_IA_64_VMS_DEBUG, SHT_IA_64_VMS_DEBUG_STR) + (SHT_IA_64_VMS_LINKAGES, SHT_IA_64_VMS_SYMBOL_VECTOR) + (SHT_IA_64_VMS_FIXUP, DT_IA_64_VMS_SUBTYPE) + (DT_IA_64_VMS_IMGIOCNT, DT_IA_64_VMS_LNKFLAGS) + (DT_IA_64_VMS_VIR_MEM_BLK_SIZ, DT_IA_64_VMS_IDENT) + (DT_IA_64_VMS_NEEDED_IDENT, DT_IA_64_VMS_IMG_RELA_CNT) + (DT_IA_64_VMS_SEG_RELA_CNT, DT_IA_64_VMS_FIXUP_RELA_CNT) + (DT_IA_64_VMS_FIXUP_NEEDED, DT_IA_64_VMS_SYMVEC_CNT) + (DT_IA_64_VMS_XLATED, DT_IA_64_VMS_STACKSIZE) + (DT_IA_64_VMS_UNWINDSZ, DT_IA_64_VMS_UNWIND_CODSEG) + (DT_IA_64_VMS_UNWIND_INFOSEG, DT_IA_64_VMS_LINKTIME) + (DT_IA_64_VMS_SEG_NO, DT_IA_64_VMS_SYMVEC_OFFSET) + (DT_IA_64_VMS_SYMVEC_SEG, DT_IA_64_VMS_UNWIND_OFFSET) + (DT_IA_64_VMS_UNWIND_SEG, DT_IA_64_VMS_STRTAB_OFFSET) + (DT_IA_64_VMS_SYSVER_OFFSET, DT_IA_64_VMS_IMG_RELA_OFF) + (DT_IA_64_VMS_SEG_RELA_OFF, DT_IA_64_VMS_FIXUP_RELA_OFF) + (DT_IA_64_VMS_PLTGOT_OFFSET, DT_IA_64_VMS_PLTGOT_SEG) + (DT_IA_64_VMS_FPMODE, SHN_IA_64_VMS_SYMVEC): Define + +2008-01-16 Mark Kettenis + + * common.h (AT_SUN_AUXFLAGS): Define. + +2007-12-11 Daniel Jacobowitz + + * dwarf2.h (DW_AT_hi_user): Correct value. + +2007-12-07 Bob Wilson + + * xtensa.h (R_XTENSA_32_PCREL): New. + +2007-11-29 Mark Shinwell + + * mips.h (E_MIPS_MACH_LS2E): New. + (E_MIPS_MACH_LS2F): New. + +2007-11-28 Nathan Sidwell + + * internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with + segments at the end of memory. + +2007-11-17 Thiemo Seufer + + * mips.h (Tag_GNU_MIPS_ABI_FP): Mention -mips32r2 -mfp64 variant + in comment. + +2007-11-16 Nick Clifton + + * dwarf2.h: Mention the location of the DWARF3 spec on the web. + (DW_AT_stride_size): Rename to DW_AT_bit_stride. + (DW_AT_stride): Rename to DW_AT_byte_stride. + +2007-11-08 Nathan Sidwell + + * vxworks.h: New. + +2007-10-30 Nick Clifton + + * mn10300.h (R_MN10300_ALIGN): Define. + +2007-10-25 Daniel Jacobowitz + + * ppc.h (Tag_GNU_Power_ABI_Vector): New. + +2007-10-19 Nick Clifton + + * mn10300.h: Add R_MN10300_SYM_DIFF reloc. + +2007-10-18 Roland McGrath + + * common.h (NT_PPC_VMX): New macro. + +2007-10-01 M R Swami Reddy + + * cr16.h: Updated with new relocaction macros. + +2007-09-17 H.J. Lu + + PR binutils/3281 + PR binutils/5037 + * internal.h (elf_segment_map): Add p_size and p_size_valid. + (ELF_IS_SECTION_IN_SEGMENT): Allow SHF_TLS sections in + PT_GNU_RELRO segments. + +2007-09-11 Nathan Sidwell + + * m68k.h (EF_M68K_CF_ISA_C_NODIV): New. + +2007-08-25 Ulrich Weigand + + * common.h (NT_SPU): Define. + +2007-08-16 H.J. Lu + + * common.h: Revert last change. + +2007-08-16 H.J. Lu + + * common.h (PT_GNU_STACK): Renamed to ... + (PT_GNU_ATTR): This. + (PT_GNU_STACK): New. Make an alias of PT_GNU_ATTR. + +2007-07-09 Roland McGrath + + * common.h (NT_GNU_HWCAP, NT_GNU_BUILD_ID): New macros. + +2007-06-29 Joseph Myers + + * ppc.h (Tag_GNU_Power_ABI_FP): Define. + +2007-06-29 Joseph Myers + + * mips.h (Tag_GNU_MIPS_ABI_FP): Define. + +2007-06-29 Joseph Myers + + * arm.h (elf32_arm_add_eabi_attr_int, + elf32_arm_add_eabi_attr_string, elf32_arm_add_eabi_attr_compat, + elf32_arm_get_eabi_attr_int, elf32_arm_set_eabi_attr_contents, + elf32_arm_eabi_attr_size, Tag_NULL, Tag_File, Tag_Section, + Tag_Symbol, Tag_compatibility): Remove. + * common.h (SHT_GNU_ATTRIBUTES): Define. + +2007-06-29 M R Swami Reddy + + * common.h (EM_CR16): New entry for CR16 cpu. + * cr16.h: New file. + +2007-06-11 Sterling Augustine + Bob Wilson + + * xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to... + (XTENSA_PROP_NO_TRANSFORM): ...this. + +2007-05-18 Caroline Tice + + * dwarf2.h: (enum dwarf_location_atom): Add new DW_OP, + DW_OP_GNU_uninit. + +2007-05-12 Alan Modra + + * spu.h (R_SPU_ADDR16X): Define. + (R_SPU_PPU32, R_SPU_PPU64): Renumber. + +2007-05-11 Alan Modra + + * spu.h (R_SPU_PPU32, R_SPU_PPU64): Define. + +2007-05-02 Alan Modra + + * internal.h (ELF_IS_SECTION_IN_SEGMENT): Check both file offset + and vma for appropriate sections. + +2007-04-26 Jan Beulich + + * common.h (DT_ENCODING): Correct value (back to spec mandated + value). + +2007-03-08 Alan Modra + + * v850.h (V850_OTHER_TDA_BYTE): Delete. + (V850_OTHER_SDA, V850_OTHER_ZDA, V850_OTHER_TDA): Assign bits + that don't clash with visibility bits. + +2007-03-07 Alan Modra + + * common.h (ELF_ST_VISIBILITY): Comment typo fix. + +2007-02-05 Dave Brolley + Richard Sandiford + Richard Henderson + DJ Delorie + Ben Elliston + + * mep.h: New file. + * common.h (EM_CYGNUS_MEP): Define. + +2007-02-15 Dave Brolley + + From Graydon Hoare : + * common.h (STT_RELC, STT_SRELC, R_RELC): New macros. + +2007-01-08 Kazu Hirata + + * m68k.h (EF_M68K_FIDO): New. + (EF_M68K_ARCH_MASK): OR EF_M68K_FIDO. + (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove. + +2006-12-25 Kazu Hirata + + * m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New. + +2006-12-19 Kazu Hirata + + * m68k.h (EF_M68K_ARCH_MASK): New. + +2006-12-19 Nathan Sidwell + + * internal.h (struct elf_segment_map): Add p_vaddr_offset field. + +2006-12-07 Kazu Hirata + + * m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A_NODIV, + EF_M68K_ISA_A, EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B_NOUSP, + EF_M68K_ISA_B, EF_M68K_ISA_C, EF_M68K_MAC_MASK, EF_M68K_MAC, + EF_M68K_EMAC, EF_M68K_EMAC_B, EF_M68K_FLOAT): Rename to + EF_M68K_CF_ISA_MASK, EF_M68K_CF_ISA_A_NODIV, EF_M68K_CF_ISA_A, + EF_M68K_CF_ISA_A_PLUS, EF_M68K_CF_ISA_B_NOUSP, + EF_M68K_CF_ISA_B, EF_M68K_CF_ISA_C, EF_M68K_CF_MAC_MASK, + EF_M68K_CF_MAC, EF_M68K_CF_EMAC, EF_M68K_CF_EMAC_B, + EF_M68K_CF_FLOAT, respectively. + +2006-12-05 Michael Tautschnig + Nick Clifton + + * external.h (struct Elf_External_Versym): Use ATTRIBUTE_PACKED. + +2006-10-28 Richard Sandiford + + * mips.h (R_MIPS_GLOB_DAT): Define + (R_MIPS_max): Bump by 1. + +2006-10-25 Trevor Smigiel + Yukishige Shibata + Nobuhisa Fujinami + Takeaki Fukuoka + Alan Modra + + * common.h (EM_SPU): Define. + * spu.h: New file. + +2006-10-19 Mei Ligang + + * score.h (EF_SCORE_PIC): Redefine EF_SCORE_PIC as 0x80000000. + (EF_SCORE_FIXDEP): Redefine EF_SCORE_FIXDEP as 0x40000000. + (EF_SCORE_HASENTRY): Delete. + +2006-10-17 Mark Shinwell + + * arm.h: Define TAG_CPU_ARCH_* constants. + +2006-09-17 Mei Ligang + + * score.h: New file. + * common.h: Add Score machine number. + +2006-07-10 Jakub Jelinek + + * common.h (SHT_GNU_HASH, DT_GNU_HASH): Define. + +2006-05-31 H.J. Lu + + * internal.h (ELF_SECTION_SIZE): New. + (ELF_IS_SECTION_IN_SEGMENT): Likewise. + (ELF_IS_SECTION_IN_SEGMENT_FILE): Updated. + (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise. + +2006-05-27 H.J. Lu + + * internal.h (struct elf_segment_map): Add p_align and p_align_valid. + +2006-05-24 Carlos O'Donell + Randolph Chung + * hppa.h (R_PARISC_TLS_GD21L, R_PARISC_TLS_GD14R, R_PARISC_TLS_GDCALL, + R_PARISC_TLS_LDM21L, R_PARISC_TLS_LDM14R, R_PARISC_TLS_LDMCALL, + R_PARISC_TLS_LDO21L, R_PARISC_TLS_LDO14R, R_PARISC_TLS_DTPMOD32, + R_PARISC_TLS_DTPMOD64, R_PARISC_TLS_DTPOFF32, R_PARISC_TLS_DTPOFF64): + New TLS relocs. + (R_PARISC_TLS_LE21L, R_PARISC_TLS_LE14R, R_PARISC_TLS_IE21L, + R_PARISC_TLS_IE14R, R_PARISC_TLS_TPREL32, R_PARISC_TLS_TPREL64): + Define TLS relocs using existing equivalents. + +2006-05-24 Bjoern Haase + + * avr.h: Add E_AVR_MACH_AVR6, R_AVR_LO8_LDI_GS and R_AVR_HI8_LDI_GS. + +2006-03-25 Bernd Schmidt + + * bfin.h (R_BFIN_GOT17M4, R_BFIN_GOTHI, R_BFIN_GOTLO, + R_BFIN_FUNCDESC, R_BFIN_FUNCDESC_GOT17M4, R_BFIN_FUNCDESC_GOTHI, + R_BFIN_FUNCDESC_GOTLO, R_BFIN_FUNCDESC_VALUE, + R_BFIN_FUNCDESC_GOTOFF17M4, R_BFIN_FUNCDESC_GOTOFFHI, + R_BFIN_FUNCDESC_GOTOFFLO, R_BFIN_GOTOFF17M4, R_BFIN_GOTOFFHI, + R_BFIN_GOTOFFLO): New relocs. + (EF_BFIN_PIC, EF_BFIN_FDPIC, EF_BFIN_PIC_FLAGS): New macros. + +2006-03-23 Michael Matz + + * x86-64.h: Add the new relocations with their official + numbers. + +2006-03-22 Richard Sandiford + Daniel Jacobowitz + Phil Edwards + Zack Weinberg + Mark Mitchell + Nathan Sidwell + + * mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs. + +2006-03-19 John David Anglin + + * hppa.h (SHF_HP_TLS, SHF_HP_NEAR_SHARED, SHF_HP_FAR_SHARED, + SHF_HP_COMDAT, SHF_HP_CONST, SHN_TLS_COMMON, SHN_NS_COMMON, + SHN_NS_UNDEF, SHN_FS_UNDEF, SHN_HP_EXTERN, SHN_HP_EXTHINT, + SHN_HP_UNDEF_BIND_IMM, SHT_HP_OVLBITS, SHT_HP_DLKM, SHT_HP_COMDAT, + SHT_HP_OBJDICT, SHT_HP_ANNOT, STB_HP_ALIAS): Define. + +2006-03-10 Paul Brook + + * arm.h (EF_ARM_EABI_VER5): Define. + +2006-03-06 Nathan Sidwell + + * m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A, + EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_ISA_C): Adjust. + (EF_M68K_ISA_A_NODIV, EF_M68K_ISA_B_NOUSP): New. + (EF_M68K_HW_DIV, EF_M68K_USP): Remove. + (EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_FLOAT): Adjust. + (EF_M68K_EMAC_B): New. + +2006-03-03 Bjoern Haase + + * avr.h (R_AVR_MS8_LDI,R_AVR_MS8_LDI_NEG): Add. + (EF_AVR_LINKRELAX_PREPARED): Add. + +2006-03-02 Ben Elliston + + Import from the GCC tree: + 2006-03-01 Jakub Jelinek + + * dwarf2.h (DW_TAG_condition, DW_TAG_shared_type): New constants + from DWARF 3. + (DW_AT_description, DW_AT_binary_scale, DW_AT_decimal_scale, + DW_AT_small, DW_AT_decimal_sign, DW_AT_digit_count, + DW_AT_picture_string, DW_AT_mutable, DW_AT_threads_scaled, + DW_AT_explicit, DW_AT_object_pointer, DW_AT_endianity, + DW_AT_elemental, DW_AT_pure, DW_AT_recursive): New. + (DW_OP_form_tls_address, DW_OP_call_frame_cfa, DW_OP_bit_piece): New. + (DW_ATE_packed_decimal, DW_ATE_numeric_string, DW_ATE_edited, + DW_ATE_signed_fixed, DW_ATE_unsigned_fixed): New. + (DW_DS_unsigned, DW_DS_leading_overpunch, DW_DS_trailing_overpunch, + DW_DS_leading_separate, DW_DS_trailing_separate): New. + (DW_END_default, DW_END_big, DW_END_little): New. + (DW_END_lo_user, DW_END_hi_user): Define. + (DW_LNE_lo_user, DW_LNE_hi_user): Define. + (DW_CFA_val_offset, DW_CFA_val_offset_sf, DW_CFA_val_expression): New. + (DW_LANG_PLI, DW_LANG_ObjC, DW_LANG_ObjC_plus_plus, DW_LANG_UPC, + DW_LANG_D): New. + +2006-02-06 Steve Ellcey + + * ia64.h (SHF_IA_64_HP_TLS): New. + +2006-02-24 DJ Delorie + + * m32c.h: Add relax relocs. + +2006-02-17 Shrirang Khisti + Anil Paranjape + Shilin Shakti + + * common.h (EM_XC16X): New entry for xc16x cpu. + Sort other EM_* numbers into numerical order. + * xc16x.h: New file. + +2006-02-10 H.J. Lu + + PR binutils/2258 + * internal.h (ELF_IS_SECTION_IN_SEGMENT_FILE): New. + (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise. + +2006-02-07 Nathan Sidwell + + * m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ... + (EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here. + (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS, + EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC, + EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New. + +2006-02-06 Steve Ellcey + + * ia64.h (SHF_IA_64_HP_TLS): New. + +2006-01-18 Alexandre Oliva + + Introduce TLS descriptors for i386 and x86_64. + * common.h (DT_TLSDESC_GOT, DT_TLSDESC_PLT): New. + * i386.h (R_386_TLS_GOTDESC, R_386_TLS_DESC_CALL, R_386_TLS_DESC): + New. + * x86-64.h (R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL, + R_X86_64_TLSDESC): New. + +2006-01-09 Mike Frysinger : + + * common.h (EM_ALTERA_NIOS2, EM_NIOS32) Define. + +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * common.h (EM_MT): Renamed. + * mt.h: Rename relocs, cpu & other defines. + +2005-12-12 Nathan Sidwell + + * mt.h: Renamed from ms1.h + +2005-12-12 Paul Brook + + * arm.h (elf32_arm_get_eabi_attr_int): Add prototype. + +2005-11-11 Nick Clifton + + PR 1150 + * mips.h (STO_OPTIONAL): Define. + (ELF_MIPS_IS_OPTIONAL): Define. + +2005-11-07 Nathan Sidwell + + Add ms2. + * ms1.h (EF_MS1_CPU_MS2): New. + +2005-11-06 John David Anglin + + * hppa.h (R_PARISC_DIR64WR, R_PARISC_DIR64DR): Remove relocs. + +2005-09-30 Catherine Moore + + * bfin.h: New file. + * common.h (EM_BLACKFIN): Define. + +2005-10-08 Paul Brook + + * arm.h: Add prototypes for BFD object attribute routines. + +2005-09-09 Richard Earnshaw + + * arm.h (SHT_ARM_PREEMPTMAP, SHT_ARM_ATTRIBUTES): New defines. + +2005-08-09 John David Anglin + + * hppa.h (SHT_PARISC_DLKM, SHF_PARISC_WEAKORDER, PT_PARISC_WEAKORDER): + New defines. + +2005-08-04 John David Anglin + + * hppa.h (PF_HP_CODE, PF_HP_MODIFY, PF_HP_LAZYSWAP): Revise defines. + (PF_HP_CODE_DEPR, PF_HP_MODIFY_DEPR, PF_HP_LAZYSWAP_DEPR): New + deprecated defines. + (DT_HP_EPLTREL, DT_HP_EPLTRELSZ, DT_HP_FILTERED, DT_HP_FILTER_TLS, + DT_HP_COMPAT_FILTERED, DT_HP_LAZYLOAD, DT_HP_BIND_NOW_COUNT, DT_PLT, + DT_PLT_SIZE, DT_DLT, DT_DLT_SIZE, DT_HP_BIND_DEPTH_FIRST, DT_HP_GST, + DT_HP_SHLIB_FIXED, DT_HP_MERGE_SHLIB_SEG, DT_HP_NODELETE, DT_HP_GROUP, + DT_HP_PROTECT_LINKAGE_TABLE, PT_HP_OPT_ANNOT, PT_HP_HSL_ANNOT, + PT_HP_STACK, PT_HP_CORE_UTSNAME, NT_HP_COMPILER, NT_HP_COPYRIGHT, + NT_HP_VERSION, NT_HP_SRCFILE_INFO, NT_HP_LINKER, NT_HP_INSTRUMENTED, + NT_HP_UX_OPTIONS): Define. + +2005-07-25 DJ Delorie + + * m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16. + +2005-07-25 Jan Hubicka + + * x86-64.h (SHN_X86_64_LCOMMON): New. + (SHF_X86_64_LARGE): New. + +2005-07-20 Kazuhiro Inaoka + + * m32r.h (R_M32R_REL32): Added. + +2005-07-18 Ben Elliston + + * dwarf2.h (enum dwarf_type): Remove DW_AT_GNU_decimal_float. + Replace with DW_ATE_decimal_float (now in DWARF 3). + +2005-07-14 Jim Blandy + + Add support for Renesas M32C and M16C. + * common.h (EM_M32C): New machine number. + * m32c.h: New file. + +2005-06-17 Jakub Jelinek + + * external.h (GRP_ENTRY_SIZE): Define. + +2005-06-17 Jan Beulich + + * x86-64.h (elf_x86_64_reloc_type): Adjust comment for + R_X86_64_GOTPCREL. Add R_X86_64_PC64, R_X86_64_GOTOFF64, and + R_X86_64_GOTPC32. + +2005-06-07 Aldy Hernandez + Michael Snyder + Stan Cox + + * common.h (EM_MS1): Define. + + * ms1.h: New file. + +2005-05-31 Richard Henderson + + * alpha.h (LITUSE_ALPHA_JSRDIRECT): New. + +2005-05-29 Richard Henderson + + * alpha.h (DT_ALPHA_PLTRO): New. + +2005-05-19 Ben Elliston + + * dwarf2.h (enum dwarf_type): Assign DW_ATE_GNU_decimal_float from + the user-defined encoding space pending inclusion in the standard. + +2005-05-18 Zack Weinberg + + * arm.h: Make all #ifndef OLD_ARM_ABI blocks + unconditional, delete all #ifdef OLD_ARM_ABI blocks. + +2005-05-17 Zack Weinberg + + * arm.h: Import complete list of official relocation names + and numbers from AAELF. Define FAKE_RELOCs for old names. + Remove a few old names no longer used anywhere. + +2005-05-14 Alan Modra + + * ppc.h (DT_PPC_GOT): Rename from DT_PPC_GLINK. + +2005-05-11 Alan Modra + + * ppc.h (R_PPC_RELAX32, R_PPC_RELAX32PC, R_PPC_RELAX32_PLT, + R_PPC_RELAX32PC_PLT) Adjust. + (R_PPC_REL16, R_PPC_REL16_LO, R_PPC_REL16_HI, R_PPC_REL16_HA): Define. + (DT_PPC_GLINK): Define. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + alpha.h, arc.h, arm.h, avr.h, common.h, cr16c.h, cris.h, crx.h, + d10v.h, d30v.h, dlx.h, dwarf.h, dwarf2.h, external.h, fr30.h, + frv.h, h8.h, hppa.h, i370.h, i386.h, i860.h, i960.h, ia64.h, + internal.h, ip2k.h, iq2000.h, m32r.h, m68hc11.h, m68k.h, mcore.h, + mips.h, mmix.h, mn10200.h, mn10300.h, msp430.h, openrisc.h, + or32.h, pj.h, ppc.h, ppc64.h, reloc-macros.h, s390.h, sh.h, + sparc.h, v850.h, vax.h, x86-64.h, xstormy16.h, xtensa.h + +2005-04-13 H.J. Lu + + Moved from ../ChangeLog + + 2004-10-27 Richard Earnshaw + * arm.h: Add R_ARM_CALL and R_ARM_JUMP32. + + 2004-10-12 Paul Brook + * arm.h (EF_ARM_EABI_VER4): Define. + + 2004-10-08 Daniel Jacobowitz + + * common.h (PT_SUNW_EH_FRAME): Define. + * x86-64.h (SHT_X86_64_UNWIND): Define. + + 2004-10-07 Bob Wilson + * xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32, + R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations. + (XTENSA_PROP_SEC_NAME): Define. + (property_table_entry): Add flags field. + (XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define. + + 2004-09-17 Paul Brook + * arm.h: Remove R_ARM_STKCHK and R_ARM_THM_STKCHK. + Add R_ARM_TARGET2, R_ARM_PREL31, R_ARM_GOT_ABS, R_ARM_GOT_PREL, + R_ARM_GOT_BREL12, R_ARM_GOTOFF12 and R_ARM_GOTRELAX. + + 2004-09-13 Paul Brook + * arm.h: Rename RELABS to TARGET1. + + 2004-05-11 Jakub Jelinek + * common.h (PT_GNU_EH_FRAME, PT_GNU_STACK): Add comments. + (PT_GNU_RELRO): Define. + +2005-03-29 Daniel Jacobowitz + Phil Blundell + + * arm.h: Add TLS relocations. + +2005-03-23 Ben Elliston + + * dwarf.h: Merge with GCC's dwarf.h. + +2005-03-18 C Jaipraash + + * m68k.h (EF_CFV4E): Define. + +2005-03-17 Paul Brook + Dan Jacobowitz + Mark Mitchell + + * arm.h (PT_ARM_EXIDX): Define. + +2005-03-02 Daniel Jacobowitz + Joseph Myers + + * mips.h: Define MIPS TLS relocations. + +2005-02-15 Nigel Stephens + Maciej W. Rozycki + + * mips.h (R_MIPS16_GOT16): New reloc code. + (R_MIPS16_CALL16): Likewise. + (R_MIPS16_HI16): Likewise. + (R_MIPS16_LO16): Likewise. + (R_MIPS16_min): New fake reloc code. + (R_MIPS16_max): Likewise. + +2005-02-11 Maciej W. Rozycki + + * mips.h (R_MIPS_max): Use FAKE_RELOC to define. + +2005-01-25 Alexandre Oliva + + 2004-12-10 Alexandre Oliva + * frv.h: Add R_FRV_TLSMOFF. + 2004-11-10 Alexandre Oliva + * frv.h: Add TLS relocations. + +2005-01-17 Nick Clifton + + * sh.h (EF_SH2A_SH4_NOFPU, EF_SH2A_SH3_NOFPU, EF_SH2A_SH4, + EF_SH2A_SH3E): New flags. + (EF_SH_BFD_TABLE): Add these new flags to the table. + +2005-01-12 Alan Modra + + * ppc.h (R_PPC_RELAX32_PLT, R_PPC_RELAX32PC_PLT): Define. + (R_PPC_RELAX32, R_PPC_RELAX32PC): Adjust value. + +2004-12-22 Klaus Rudolph + + * avr.h (R_AVR_LDI, R_AVR_6, R_AVR_6_ADIW): New relocs. + +2004-12-16 Richard Sandiford + + * v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc. + +2004-12-09 Ian Lance Taylor + + * mips.h (E_MIPS_MACH_9000): Define. + +2004-11-04 Hans-Peter Nilsson + + * cris.h (EF_CRIS_VARIANT_MASK, EF_CRIS_VARIANT_ANY_V0_V10) + (EF_CRIS_VARIANT_V32, EF_CRIS_VARIANT_COMMON_V10_V32): New + macros. + +2004-10-06 Eric Christopher + + * dwarf2.h: Sync with gcc dwarf2.h. Fix typo. + +2004-10-01 Paul Brook + + * arm.h (SHT_ARM_EXIDX): Define. + (ELF_STRING_ARM_unwind, ELF_STRING_ARM_unwind, + ELF_STRING_ARM_unwind_once, ELF_STRING_ARM_unwind_info_once): + Define. + +2004-08-25 Dmitry Diky + + * msp430.h: Add new relocs. + +2004-08-12 H.J. Lu + + * i386.h (R_386_USED_BY_INTEL_200): New. + +2004-07-29 Alexandre Oliva + + Introduce SH2a support. + 2004-02-18 Corinna Vinschen + * sh.h (EF_SH2A_NOFPU): New. + 2003-12-01 Michael Snyder + * sh.h (EF_SH2A): New. + +2004-07-27 Tomer Levi + + * crx.h: Add BFD_RELOC_CRX_SWITCH8, BFD_RELOC_CRX_SWITCH16, + BFD_RELOC_CRX_SWITCH32. + +2004-07-06 Tomer Levi + + * common.h (EM_CRX): Define. + * crx.h: New file. + +2004-06-25 Kazuhiro Inaoka + + * m32r.h: Add defintions of R_M32R_GOTOFF_HI_ULO, + R_M32R_GOTOFF_HI_SLO and R_M32R_GOTOFF_LO. + +2004-06-19 Alan Modra + + * common.h (ELF64_R_INFO): Warning fix. + +2004-06-14 Chris Demetriou + + * mips.h (R_MIPS_PC32): Add back (undoing removal on 2004-04-24), + with an updated comment. + +2004-05-28 Andrew Stubbs + + * sh.h (EF_SH_HAS_DSP): Remove. + (EF_SH_HAS_FP): Remove. + (EF_SH_MERGE_MACH): Remove. + (EF_SH4_NOFPU): Convert to decimal. + (EF_SH4A_NOFPU): Likewise. + (EF_SH4_NOMMU_NOFPU): Likewise. + (EF_SH3_NOMMU): Add new macro. + (EF_SH_BFD_TABLE): Likewise. + (sh_find_elf_flags): Add prototype. + (sh_elf_get_flags_from_mach): Likewise. + +2004-04-24 Chris Demetriou + + * mips.h (R_MIPS_PC32, R_MIPS_PC64, R_MIPS_GNU_REL_LO16) + (R_MIPS_GNU_REL_HI16): Remove. + (R_MIPS_GNU_REL16_S2): Update comment. + +2004-30-30 Galit Heller + Tomer Levi + + * common.h (EM_CR): Define. + * cr16c.h: New file. + +2004-03-23 Paul Brook + + * arm.h (EF_ERM_BE8, EF_ARM_LE8, EF_ARM_EABI_VER3): Add. + +2003-03-03 Andrew Stubbs + + * sh.h: Add EF_SH4_NOMMU_NOFPU. + +2004-03-01 Richard Sandiford + + * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define. + +2004-01-28 Roland McGrath + + * common.h (AT_SECURE): New macro. + +2004-01-21 Roland McGrath + + * common.h (AT_SUN_UID, AT_SUN_RUID, AT_SUN_GID): New macros. + (AT_SUN_RGID, AT_SUN_LDELF, AT_SUN_LDSHDR, AT_SUN_LDNAME, + AT_SUN_LPAGESZ, AT_SUN_PLATFORM, AT_SUN_HWCAP, AT_SUN_IFLUSH, + AT_SUN_CPU, AT_SUN_EMUL_ENTRY, AT_SUN_EMUL_EXECFD, + AT_SUN_EXECNAME) AT_SUN_MMU, AT_SUN_LDDATA): Likewise. + +2004-01-17 Mark Kettenis + + * common.h (NT_OPENBSD_IDENT): Define. + +2004-01-06 Alexandre Oliva + + 2003-09-18 Alexandre Oliva + * frv.h (EF_FRV_FDPIC): New macro. + (EF_FRV_PIC_FLAGS): Adjust. + 2003-08-08 Alexandre Oliva + * frv.h (R_FRV_FUNCDESC_VALUE, R_FRV_FUNCDESC_GOTOFF12, + R_FRV_FUNCDESC_GOTOFFLO, R_FRV_FUNCDESC_GOTOFFHI, R_FRV_GOTOFF12, + R_FRV_GOTOFFLO, R_FRV_GOTOFFHI): New. + 2003-08-04 Alexandre Oliva + * frv.h (R_FRV_GOT12, R_FRV_GOTHI, R_FRV_GOTLO, R_FRV_FUNCDESC, + R_FRV_FUNCDESC_GOT12, R_FRV_FUNCDESC_GOTHI, R_FRV_FUNCDESC_GOTLO): + New. + + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/elf/ChangeLog-9103 b/external/gpl3/gdb/dist/include/elf/ChangeLog-9103 new file mode 100644 index 000000000000..93632ef80eb9 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ChangeLog-9103 @@ -0,0 +1,1948 @@ +2005-04-13 H.J. Lu + + Moved from ../ChangeLog + + 2003-10-14 Bob Wilson + * xtensa.h: Formatting. Fix comments about property section + names for linkonce sections. + + 2003-05-23 Jakub Jelinek + * common.h (PT_GNU_STACK): Define. + + 2003-01-25 Jakub Jelinek + * sparc.h: Add TLS relocs. Move R_SPARC_REV32 to 252. + + 2002-09-26 Jakub Jelinek + * x86-64.h: Add TLS relocs. + + 2002-09-19 Jakub Jelinek + * i386.h (R_386_TLS_TPOFF, R_386_TLS_IE, R_386_TLS_GOTIE): + Define. + + 2002-07-10 Jakub Jelinek + * common.h (SHT_GNU_LIBLIST, DT_GNU_PRELINKED, + DT_GNU_CONFLICT*, DT_GNU_LIBLIST*): Define. + + 2002-05-31 Michal Ludvig + * dwarf2.h (DW_CFA_low_user, DW_CFA_high_user): Renamed + to DW_CFA_lo_user, DW_CFA_hi_user respectively. + + 2002-05-23 Jakub Jelinek + * common.h (PT_TLS, SHF_TLS, STT_TLS, DF_STATIC_TLS): Define. + * ia64.h (R_IA64_LTOFF_TPREL22): Renamed from R_IA64_LTOFF_TP22. + * i386.h: Add TLS relocs. + +2003-12-19 Kazuhiro Inaoka + + * m32r.h : Added m32r-linux and PIC support. Add new ABI that + uses RELA. + (R_M32R_16_RELA, R_M32R_32_RELA, R_M32R_24_RELA, + R_M32R_10_PCREL_RELA, R_M32R_18_PCREL_RELA, + R_M32R_26_PCREL_RELA, R_M32R_HI16_ULO_RELA, + R_M32R_HI16_SLO_RELA, R_M32R_LO16_RELA, + R_M32R_SDA16_RELA, R_M32R_RELA_GNU_VTINHERIT, + R_M32R_RELA_GNU_VTENTRY, R_M32R_GOT24, + R_M32R_26_PLTREL, R_M32R_COPY, R_M32R_GLOB_DAT, + R_M32R_JMP_SLOT, R_M32R_RELATIVE, R_M32R_GOTOFF, + R_M32R_GOTPC24, R_M32R_GOT16_HI_ULO, + R_M32R_GOT16_HI_SLO, R_M32R_GOT16_LO, + R_M32R_GOTPC_HI_ULO, R_M32R_GOTPC_HI_SLO, + R_M32R_GOTPC_LO): New relocs. + +2003-12-06 Alan Modra + + From Jan Beulich + * common.h (DT_HIOS): Correct value. + +2003-12-03 Kazuhiro Inaoka + + * m32r.h: Add new machine type m32r2 and instruction modes. + +2003-11-06 Alan Modra + + * ppc.h (R_PPC_RELAX32PC): Define. + +2003-10-22 Alexandre Oliva , + Michael Snyder + + * sh.h (EF_SH4A, EF_SH4AL_DSP, EF_SH4_NOFPU, EF_SH4A_NOFPU): New. + (EF_SH_MERGE_MACH): Combine them. + +2003-10-18 Hans-Peter Nilsson + + * mmix.h (R_MMIX_PUSHJ_STUBBABLE): New reloc number. + (_bfd_mmix_before_linker_allocation): Rename from + _bfd_mmix_prepare_linker_allocated_gregs. + (_bfd_mmix_after_linker_allocation): Rename from + _bfd_mmix_finalize_linker_allocated_gregs. + +2003-10-06 Dave Brolley + + * frv.h (EF_FRV_CPU_FR550): New macro. + +2003-09-30 Chris Demetriou + + * mips.h (E_MIPS_ARCH_64R2): New define. + +2003-09-23 DJ Delorie + + * sh.h (R_SH_SWITCH8, R_SH_GNU_VTINHERIT, R_SH_GNU_VTENTRY, + R_SH_LOOP_START,R_SH_LOOP_END): Move to "reserved" spaces. + (R_SH_DIR16, R_SH_DIR8, R_SH_DIR8UL, R_SH_DIR8UW, R_SH_DIR8U, + R_SH_DIR8SW, R_SH_DIR8S, R_SH_DIR4UL, R_SH_DIR4UW, R_SH_DIR4U, + R_SH_PSHA, R_SH_PSHL): New. + +2003-09-11 James Cownie + + * dwarf2.h: Add HP dwarf extensions from their hacked gdb + header files (ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz). + +2003-09-04 Nick Clifton + + * v850.h (E_V850E1_ARCH): Define. + +2003-08-21 James Cownie + + * dwarf2.h: Add PGI dwarf extensions. + +2003-08-08 Dmitry Diky + + * msp430.h: Add xW42 and xE42 parts. Sort MPU list according to + gcc order. + +2003-08-07 Alan Modra + + * reloc-macros.h (START_RELOC_NUMBERS) : Remove PARAMS macro. Use + C90 function definition. Formatting. + (RELOC_NUMBER): Remove !__STDC__ code. + +2003-07-28 Eric Christopher + + * ppc.h (R_PPC_RELAX32): New. Fake relocation. + +2003-07-25 H.J. Lu + + * v850.h (SHF_V850_GPREL): New. + (SHF_V850_EPREL): Likewise. + (SHF_V850_R0REL): Likewise. + +2003-07-09 Alexandre Oliva + + 2001-05-16 Alexandre Oliva + * mn10300.h: Introduce GOTPC16, GOTOFF24, GOTOFF16 and + PLT16, and rename GOTPC to GOTPC32 and GOTOFF to GOTOFF32. + Renumbered all relocs. + 2001-04-12 Alexandre Oliva + * mn10300.h (R_MN10300_GOTPC, R_MN10300_GOTOFF, + R_MN10300_PLT32, R_MN10300_GOT32, R_MN10300_GOT24, + R_MN10300_GOT16, R_MN10300_COPY, R_MN10300_GLOB_DAT, + R_MN10300_JMP_SLOT, R_MN10300_RELATIVE): New relocs. + +2003-07-09 Alexandre Oliva + + 2000-04-01 Alexandre Oliva + * mn10300.h (E_MN10300_MACH_AM33_2): Renamed from + E_MN10300_MACH_AM332. + 2000-03-31 Alexandre Oliva + * mn10300.h (E_MN10300_MACH_AM332): Defined. + +2003-07-01 Martin Schwidefsky + + * s390.h (elf_s390_reloc_type): Add long displacement relocations + R_390_20, R_390_GOT20, R_390_GOTPLT20 and R_390_TLS_GOTIE20. + +2003-06-29 Andreas Jaeger + + * mmix.h: Convert to ISO C90 prototypes. + * mips.h: Likewise. + +2003-06-13 Robert Millan + + * common.h (GNU_ABI_TAG_NETBSD): New tag. + (GNU_ABI_TAG_FREEBSD): New tag. + +2003-06-10 Richard Sandiford + + * h8.h (E_H8_MACH_H8300SXN): New flag. + +2003-06-03 Nick Clifton + + * v850.h (R_V850_32): Rename to R_V850_ABS32. + Add R_V850_REL32. + +2003-05-15 Roland McGrath + + * common.h (NT_AUXV, AT_*): New macros. + * external.h (Elf32_External_Auxv, Elf64_External_Auxv): New types. + * internal.h (Elf_Internal_Auxv): New type. + +2003-05-14 Michael Snyder + From Bernd Schmidt + * h8.h (E_H8_MACH_H8300SX): New. + +2003-04-24 Dhananjay Deshpande + + * h8.h (E_H8_MACH_H8300HN, E_H8_MACH_H8300SN): New + +2003-04-23 J"orn Rennecke + + * common.h (EM_SH): Amend comment to refer to SuperH. + +2003-04-22 Kazuhiro Inaoka + + * common.h: Replace references to Mitsubishi M32R with + references to Renesas M32R. + +2003-04-15 Rohit Kumar Srivastava + + * common.h: Replace occurrances of 'Hitachi' with 'Renesas'. + +2003-04-01 Bob Wilson + + * common.h (EM_XTENSA_OLD): Define. + * xtensa.h: New file. + +2003-04-01 Nick Clifton + + * arm.h (ARM_NOTE_SECTION): Include .gnu in the string. + +2003-03-25 Stan Cox + Nick Clifton + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm.h (ARM_NOTE_SECTION): Define. + +2003-03-03 J"orn Rennecke + + * sh.h (EF_SH_MERGE_MACH): Make sure SH2E & SH3/SH3E merge to SH3E, + and SH2E & SH4 merge to SH4, not SH2E. + +2003-02-21 Ian Wienand + + * ia64.h (SHT_IA_64_LOPSREG, SHT_IA_64_HIPSREG, + SHT_IA_64_PRIORITY_INIT): Define. + +2003-02-18 Alan Modra + + * ppc64.h (IS_PPC64_TLS_RELOC): Rename from IS_TLS_RELOC. + + * ppc.h: Replace DTPMOD64, TPREL64, DTPREL64 with DTPMOD32 etc. + (IS_PPC_TLS_RELOC): Define. + +2003-02-10 Nick Clifton + + * arm.h (EF_ARM_MAVERICK_FLOAT): Define. + +2003-02-05 Alan Modra + + * ppc.h: Add TLS relocs. Format. + * ppc64.h: Likewise. + +2003-01-27 Alexandre Oliva + + * mips.h (EF_MIPS_XGOT): Define. + +2003-01-24 Martin Schwidefsky + + * s390.h: Add s390 TLS relocations. + +2003-01-23 Nick Clifton + + * Add sh2e support: + + 2002-04-02 Alexandre Oliva + + * sh.h (EF_SH_MERGE_MACH): Handle SH2E. + + 2002-04-02 Elena Zannoni + + * sh.h (EF_SH2E): New. + +2003-01-23 Alan Modra + + * sh.h: Split out various bits to bfd/elf32-sh64.h. + +2003-01-20 Martin Schwidefsky + + * s390.h: Rename R_390_GOTOFF to R_390_GOTOFF32. Add new gotoff, + gotplt and pltoff relocations. + +2003-01-17 Alan Modra + + * common.h: Formatting, typo fixes. + (DT_ENCODING): Correct value. + +2003-01-17 Fabio Alemagna + + * common.h (ELFOSABI_AROS): Define. + (ELFOSABI_OPENVMS): Likewise. + (ELFOSABI_NSK): Likewise. + +2003-01-16 Alan Modra + + * ppc.h: Split out ppc64 definitions to.. + * pcc64.h: ..here. New file. + (R_PPC64_REL30): Rename from R_PPC64_ADDR30. + +2003-01-13 Dmitry Diky + + * elf/common.h (EM_MSP430): Change e_machine value to officially + assigned. + +2003-01-02 Ben Elliston + + * common.h (EM_IQ2000): Define. + * iq2000.h: New file. + +2002-12-30 Chris Demetriou + + * mips.h (E_MIPS_ARCH_32R2): New define. + +2002-12-24 Dmitry Diky + + * common.h: Define msp430 machine numbers. + * msp430.h: New file. Define msp430 relocs. + +2002-12-20 DJ Delorie + + * xstormy16.h: Add XSTORMY16_12. + +2002-12-16 Andrew MacLeod + + * xstormy16.h (START_RELOC_NUMBERS) Add relocation numbers + for R_XSTORMY16_LO16 and R_XSTORMY16_HI16. + +2002-12-10 James Cownie + + * dwarf2.h (DW_TAG_upc_shared_type, DW_TAG_upc_strict_type, + DW_TAG_upc_relaxed_type, DW_AT_upc_threads_scaled, DW_LANG_Upc): + Define. + +2002-12-01 Stephane Carrez + + * m68hc11.h (EF_M68HC12_MACH, EF_M68HCS12_MACH): Define. + (EF_M68HC11_MACH_MASK, EF_M68HC11_MACH): Define. + (EF_M68HC11_MERGE_MACH, EF_M68HC11_CAN_MERGE_MACH): Define. + +2002-11-30 Alan Modra + + * mmix.h: Replace boolean with bfd_boolean. + * sh.h: Likewise. + +2002-11-28 Alan Modra + + * internal.h (elf32_internal_ehdr, Elf32_Internal_Ehdr, + elf64_internal_ehdr, Elf64_Internal_Ehdr, elf32_internal_phdr, + Elf32_Internal_Phdr, elf64_internal_phdr, Elf64_Internal_Phdr, + elf32_internal_shdr, Elf32_Internal_Shdr, elf64_internal_shdr, + Elf64_Internal_Shdr, elf32_internal_sym, elf64_internal_sym, + Elf32_Internal_Sym, Elf64_Internal_Sym, Elf32_Internal_Note, + elf32_internal_note, elf32_internal_rel, Elf32_Internal_Rel, + elf64_internal_rel, Elf64_Internal_Rel, elf32_internal_rela, + elf64_internal_rela, Elf32_Internal_Rela, Elf64_Internal_Rela, + elf32_internal_dyn, elf64_internal_dyn, Elf32_Internal_Dyn, + Elf64_Internal_Dyn, elf32_internal_verdef, elf64_internal_verdef, + elf32_internal_verdaux, elf64_internal_verdaux, elf32_internal_verneed, + elf64_internal_verneed, elf32_internal_vernaux, elf64_internal_vernaux, + elf32_internal_versym, elf64_internal_versym, Elf32_Internal_Verdef, + Elf64_Internal_Verdef, Elf32_Internal_Verdaux, Elf64_Internal_Verdaux, + Elf32_Internal_Verneed, Elf64_Internal_Verneed, Elf32_Internal_Vernaux, + Elf64_Internal_Vernaux, Elf32_Internal_Versym, Elf64_Internal_Versym, + Elf32_Internal_Syminfo, Elf64_Internal_Syminfo): Delete. + (Elf_Internal_Rel): Delete. + +2002-10-11 Kaz Kojima + + * sh.h: Add SH TLS relocs. + +2002-09-30 Gavin Romig-Koch + Ken Raeburn + Aldy Hernandez + Eric Christopher + Richard Sandiford + + * mips.h (E_MIPS_MACH_4120, E_MIPS_MACH_5400, E_MIPS_MACH_5500): New. + +2002-09-12 Roland McGrath + + * dwarf2.h: Updates from GCC version of thie file: + (enum dwarf_location_atom): DW_OP_calli -> DW_OP_call_ref. + Add DW_OP_GNU_push_tls_address. + (DW_OP_lo_user): Change to 0xe0. + +2002-08-28 Catherine Moore + + * v850.h (R_V850_LONGCALL, R_V850_ALIGN, + R_V850_LONGJUMP): New relocations. + +2002-08-15 Alan Modra + + * i370.h: Define relocs using reloc-macros.h. + +2002-08-13 Stephane Carrez + + * m68hc11.h (E_M68HC12_BANKS, E_M68HC11_I32, E_M68HC11_F64, + EF_M68HC11_ABI): Define for ABI specification. + (STO_M68HC12_FAR, STO_M68HC12_INTERRUPT): Symbol flags for + linker and debugger. + (R_M68HC11_24, R_M68HC11_LO16, R_M68HC11_PAGE): New relocs. + (R_M68HC11_RL_JUMP, R_M68HC11_RL_GROUP): New reloc for linker + relaxation. + +2002-07-15 Denis Chertykov + Frank Ch. Eigler + Ben Elliston + Alan Lehotsky + John Healy + Graham Stott + Jeff Johnston + + * common.h (EM_IP2K): New macro. + (EM_IP2K_OLD): New macro. + * ip2k.h: New file. + +2002-07-01 Matt Thomas + + * vax.h: Rename EF_* to EF_VAX_*. + +2002-06-18 Dave Brolley + + From Catherine Moore, Michael Meissner, Dave Brolley: + * common.h (EM_CYGNUS_FRV): New macro. + * frv.h: New file. + +2002-06-06 Lars Brinkhoff + + * common.h: Change registry@sco.com to registry@caldera.com. + (EM_PDP10, EM_PDP11): Define. + +2002-06-04 Jason Thorpe + + * sh.h (_bfd_sh64_crange_qsort_cmpb, _bfd_sh64_crange_qsort_cmpl) + (_bfd_sh64_crange_bsearch_cmpb, _bfd_sh64_crange_bsearch_cmpl): New + prototypes. + +2002-06-01 Richard Henderson + + * alpha.h (LITUSE_ALPHA_ADDR, LITUSE_ALPHA_BASE, LITUSE_ALPHA_BYTOFF, + LITUSE_ALPHA_JSR, LITUSE_ALPHA_TLSGD, LITUSE_ALPHA_TLSLDM): New. + +2002-05-30 Richard Henderson + + * alpha.h (R_ALPHA_TLSGD, R_ALPHA_TLSLDM, R_ALPHA_DTPMOD64, + R_ALPHA_GOTDTPREL, R_ALPHA_DTPREL64, R_ALPHA_DTPRELHI, + R_ALPHA_DTPRELLO, R_ALPHA_DTPREL16, R_ALPHA_GOTTPREL, R_ALPHA_TPREL64, + R_ALPHA_TPRELHI, R_ALPHA_TPRELLO, R_ALPHA_TPREL16): New. + +2002-05-29 Matt Thomas + + * vax.h: New file + +2002-05-28 Kuang Hwa Lin + + * common.h (EM_DLX): Define. + * dlx.h: New file. + +2002-05-08 Jason Thorpe + + * common.h (NT_GNU_ABI_TAG): Define. + (GNU_ABI_TAG_LINUX): Define. + (GNU_ABI_TAG_HURD): Define. + (GNU_ABI_TAG_SOLARIS): Define. + (NT_NETBSD_IDENT): Define. + (NT_FREEBSD_ABI_TAG): Define. + +2002-04-24 Elena Zannoni + + * dwarf2.h: Add DW_AT_GNU_vector. + +2002-02-13 Matt Fredette + + * m68k.h (EF_M68000): Define. + +2002-02-12 Alan Modra + + * ppc.h (DT_PPC64_OPD, DT_PPC64_OPDSZ): Define. + +2002-02-09 Richard Henderson + + * alpha.h (R_ALPHA_BRSGP): New. + +2002-02-08 Alexandre Oliva + + Contribute sh64-elf. + 2002-01-23 Alexandre Oliva + * sh.h (R_SH_GOTPLT32, R_SH_GOT_LOW16, R_SH_GOT_MEDLOW16, + R_SH_GOT_MEDHI16, R_SH_GOT_HI16, R_SH_GOTPLT_LOW16, + R_SH_GOTPLT_MEDLOW16, R_SH_GOTPLT_MEDHI16, R_SH_GOTPLT_HI16, + R_SH_PLT_LOW16, R_SH_PLT_MEDLOW16, R_SH_PLT_MEDHI16, + R_SH_PLT_HI16, R_SH_GOTOFF_LOW16, R_SH_GOTOFF_MEDLOW16, + R_SH_GOTOFF_MEDHI16, R_SH_GOTOFF_HI16, R_SH_GOTPC_LOW16, + R_SH_GOTPC_MEDLOW16, R_SH_GOTPC_MEDHI16, R_SH_GOTPC_HI16, + R_SH_GOT10BY4, R_SH_GOTPLT10BY4, R_SH_GOT10BY8, + R_SH_GOTPLT10BY8, R_SH_COPY64, R_SH_GLOB_DAT64, R_SH_JMP_SLOT64, + R_SH_RELATIVE64): New relocs. + (R_SH_FIRST_INVALID_RELOC_4): Adjust. + 2001-05-16 Alexandre Oliva + * sh.h: Renumbered and renamed some SH5 relocations to match + official numbers and names; moved unmaching ones to the range + 0xf2-0xff. + 2001-01-06 Hans-Peter Nilsson + * sh.h (sh64_get_contents_type): Declare. + (sh64_address_is_shmedia): Likewise. + 2000-12-30 Hans-Peter Nilsson + * sh.h (sh64_elf_crange): New type. + (struct sh64_section_data): New. + (sh64_elf_section_data): New macro. + (EF_SH5): Rename back from EF_SH64. + 2000-12-18 Hans-Peter Nilsson + * sh.h (SHF_SH5_ISA32_MIXED, SHT_SH5_CR_SORTED, + SH64_CRANGES_SECTION_NAME, SH64_CRANGE_SIZE, + SH64_CRANGE_CR_ADDR_OFFSET, SH64_CRANGE_CR_SIZE_OFFSET, + SH64_CRANGE_CR_TYPE_OFFSET): New macros. + 2000-12-12 Hans-Peter Nilsson + * sh.h (EF_SH64): Don't define EF_SH64_ABI64. + 2000-11-27 Hans-Peter Nilsson + * sh.h (EF_SH64_32BIT_ABI, EF_SH64_64BIT_ABI): Delete. + (EF_SH64_ABI64): New. + 2000-11-23 Hans-Peter Nilsson + * sh.h (EF_SH64): Rename from EF_SH5. + (EF_SH64_32BIT_ABI): New. + (EF_SH64_64BIT_ABI): New. + (R_SH_PT_16, R_SH_SHMEDIA_CODE + R_SH_IMMU5, R_SH_IMMS6, R_SH_IMMU6, R_SH_IMMS10, R_SH_IMMS10BY2, + R_SH_IMMS10BY4, R_SH_IMMS10BY8, R_SH_IMMS16, R_SH_IMMU16, + R_SH_IMM_LOW16, R_SH_IMM_LOW16_PCREL, R_SH_IMM_MEDLOW16, + R_SH_IMM_MEDLOW16_PCREL, R_SH_IMM_MEDHI16, R_SH_IMM_MEDHI16_PCREL, + R_SH_IMM_HI16, R_SH_IMM_HI16_PCREL, R_SH_64, R_SH_64_PCREL): New + relocs. + 2000-09-01 Ben Elliston + * sh.h (EF_SH5): Define. + +2002-02-01 Hans-Peter Nilsson + + * mmix.h: Tweak comments. + (MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME): New. + [BFD_ARCH_SIZE] (_bfd_mmix_prepare_linker_allocated_gregs, + _bfd_mmix_finalize_linker_allocated_gregs, + _bfd_mmix_check_all_relocs): Provide prototypes. + +2002-01-31 Ivan Guzvinec + + * or32.h: New file. + * common.h: Add support for or32 targets. + +2002-01-28 Jason Merrill + + * dwarf2.h: Sync with gcc version. + +2002-01-16 Alan Modra + + * ppc.h (DT_PPC64_GLINK): Define. + +2002-01-15 Richard Earnshaw + + * arm.h (F_VFP_FLOAT, EF_ARM_VFP_FLOAT): Define. + +2002-01-09 Jason Thorpe + + * common.h: Update copyright years. + (NT_NETBSDCORE_PROCINFO): Define. + (NT_NETBSDCORE_FIRSTMACH): Define. + +2002-01-06 Steve Ellcey + + * ia64.h (ELF_STRING_ia64_unwind_hdr): New Macro for HP-UX. + (SHT_IA_64_HP_OPT_ANOT): Ditto + (PT_IA_64_HP_OPT_ANOT): Ditto + (PT_IA_64_HP_HSL_ANOT): Ditto + (PT_IA_64_HP_STACK): Ditto + (SHN_IA_64_ANSI_COMMON): Ditto + +2001-12-17 Alan Modra + + * external.h (Elf_External_Sym_Shndx): Declare. + * internal.h (struct elf_internal_sym ): Make it an + unsigned int. + * common.h (SHN_BAD): Define. + +2001-12-13 Jakub Jelinek + + * common.h (PT_GNU_EH_FRAME): Define. + +2001-12-11 Alan Modra + + * common.h (SHN_XINDEX): Comment typo fix. + * internal.h (Elf_Internal_Ehdr): Change existing "unsigned short" + size, count and index fields to "unsigned int". + +2001-12-07 Geoffrey Keating + Richard Henderson + + * common.h (EM_XSTORMY16): Define. + * xstormy16.h: New file. + +2001-11-15 Alan Modra + + * common.h (NT_ARCH): Define. Remove incorrect comment. + +2001-11-11 Geoffrey Keating + + * dwarf2.h (dwarf_line_number_ops): Add DWARF 3 opcodes. + +2001-10-30 Hans-Peter Nilsson + + * mmix.h: New file. + +2001-10-23 Alan Modra + + * internal.h: White space changes to keep lines under 80 chars. + +2001-10-16 Jeff Holcomb + + * internal.h (elf_internal_shdr): Make contents a unsigned char *. + +2001-09-18 Alan Modra + + * internal.h (elf_internal_rela): Make r_addend a bfd_vma. + +2001-09-13 Alexandre Oliva + + * common.h (EM_OPENRISC_OLD): Renamed the old EM_OPENRISC entry. + +2001-09-12 Alexandre Oliva + + * common.h (EM_AVR_OLD): Renamed from... + (EM_AVR): this, redefined as in the current ELF standard. + (EM_PJ_OLD): Renamed from... + (EM_PJ): this, redefined as in the current ELF standard. + (EM_R30, EM_D10V, EM_D30V, EM_V850, EM_M32R, EM_MN10300, + EM_MN10200, EM_OPENRISC, EM_ARC_A5, EM_XTENSA): Defined as in + the current ELF standard. + (EM_CYGNUS_ARC): Removed, unused for a long time. + +2001-09-04 Richard Henderson + + * alpha.h (R_ALPHA_OP*, R_ALPHA_IMMED*, R_ALPHA_GPVALUE): Remove. + (R_ALPHA_GPREL16): Rename from R_ALPHA_IMMED_GP_16. + +2001-08-30 Eric Christopher + + * mips.h: Remove E_MIPS_MACH_MIPS32_4K. + +2001-08-29 Jeff Law + + * h8.h (EF_H8_MACH): New mask for encoded machine type. + (E_H8_MACH_H8300, E_H8_MACH_H8300H, E_H8_MACH_H8300S): New + machine types. + +2001-08-26 J"orn Rennecke + + * h8.h: New file. + +2001-08-27 Staffan Ulfberg + + * ppc.h: Add relocs from the 64-bit PowerPC ELF ABI revision 1.2. + +2001-06-30 Daniel Berlin + + * dwarf2.h: Remerge with gcc version, + including all new DWARF 2.1 extensions. + +2001-06-29 James Cownie + + * dwarf2.h: Add DWARF 2.1 attribues. + +2001-06-15 Per Bothner + + * dwarf2.h: Partial merge with gcc version. + (enum dwarf_descrim_list): Fix typo -> dwarf_discrim_list. + (DW_LANG_Java): Use value from dwarf 2.1 draft (also used in gcc). + +2001-05-15 Ralf Baechle + + * common.h: Remove definition of EM_MIPS_RS4_BE. The constant was + never in active use and is used otherwise by the ABI. + +2001-05-11 Jakub Jelinek + + * ia64.h (ELF_STRING_ia64_unwind_once): Define. + (ELF_STRING_ia64_unwind_info_once): Define. + +2001-05-07 Thiemo Seufer + + * external.h: Fix typo. + * mips.h: Add/Extend many comments with reference to the MIPS ELF64 + spec v. 2.4, available at e.g. + ftp://oss.sgi.com/pub/linux/mips/doc/ABI/ELF64.ps. + (EF_MIPS_UCODE): Define. + (EF_MIPS_OPTIONS_FIRST): Define. + (EF_MIPS_ARCH_ASE): Define. + (EF_MIPS_ARCH_ASE_MDMX): Define. + (EF_MIPS_ARCH_ASE_M16): Define. + (SHF_MIPS_ADDR): Renamed SHF_MIPS_ADDR32. + (SHF_MIPS_STRING): Renamed SHF_MIPS_ADDR64. + (SHF_MIPS_NODUPES): Define. + (ELF64_MIPS_R_SSYM): New MIPS ELF 64 relocation info access macro. + (ELF64_MIPS_R_TYPE3): Likewise. + (ELF64_MIPS_R_TYPE2): Likewise. + (ELF64_MIPS_R_TYPE): Likewise. + (OHW_R10KLDL): Define. + +2001-04-24 Todd Fries + + * sparc.h: Fix typo. + +2001-04-20 Johan Rydberg + + * openrisc.h: New file. + * common.h (EM_OPENRISC): New constant. + +2001-04-23 Bo Thorsen + + * x86-64.h: Add vtable support. + +2001-03-23 Nick Clifton + + * mips.h: Remove extraneous whitespace. + +2001-03-22 Hans-Peter Nilsson + + * cris.h: Add leading comment about PC-relative location. + (R_CRIS_COPY, R_CRIS_GLOB_DAT, R_CRIS_JUMP_SLOT, R_CRIS_RELATIVE, + R_CRIS_16_GOT, R_CRIS_32_GOT, R_CRIS_16_GOTPLT, R_CRIS_32_GOTPLT, + R_CRIS_32_GOTREL, R_CRIS_32_PLT_GOTREL, R_CRIS_32_PLT_PCREL): + New relocs. + +2001-02-27 Philip Blundell + + * arm.h: Add new definitions from ARM document SWS ESPC 0003 B-01. + (EF_PIC, et al.): Rename to EF_ARM_xx. + +2001-02-09 Martin Schwidefsky + + * common.h: Add linux target for S/390. + * s390.h: New file. + +2001-01-11 Peter Targett + + * arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7, + E_ARC_MACH_ARC8): New definitions for cpu types. + + * common.h (EM_ARC): Change comment. + +2000-12-12 Nick Clifton + + * mips.h: Fix formatting. + +2000-12-11 Jeffrey A Law (law@cygnus.com) + + * hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux + compatibility. + +2000-10-16 Chris Demetriou + + * mips.h (E_MIPS_ARCH_32): New constant. + (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the + former with the latter. + + * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions. + + * mips.h (E_MIPS_MACH_SB1): New constant. + +2000-11-30 Jan Hubicka + + * common.h (EM_X86_64): New macro. + * x86-64.h: New file. + +2000-11-27 Hans-Peter Nilsson + + * common.h (e_machine numbers): Clarify comments to describe how + EM_* constants are assigned. Move EM_PJ from official section to + ad-hoc section. + (EM_CRIS): Correct comment to match official description. + (EM_MMIX): Ditto. + +2000-11-22 Nick Clifton + + * common.h (EM_JAVELIN): New machine number. + (EM_FIREPATH): New machine number. + (EM_ZSP): New machine number. + (EM_MMIX): New machine number. + (EM_HUANY): New machine number. + (EM_PRISM): New machine number. + (SHT_GROUP): New section type. + (SHT_SYMTAB_SHNDX): New section type. + (SHF_GROUP): New section flag. + (SHN_XINDEX): New section index. + (GRP_COMDAT): New section group flag. + +2000-11-20 H.J. Lu + + * common.h (ELFOSABI_MONTEREY): Renamed to ... + (ELFOSABI_AIX): This. + +2000-11-16 Richard Henderson + + Update relocations per August psABI docs. + * ia64.h (R_IA64_SEGBASE): Remove. + (R_IA64_LTV*): Renumber to 0x74 to 0x77. + (R_IA64_EPLTMSB, R_IA64_EPLTLSB): Remove. + (R_IA64_TPREL14, R_IA64_TPREL64I): New. + (R_IA64_DTPMOD*): New. + (R_IA64_DTPREL*): New. + +2000-09-29 Hans-Peter Nilsson + + * cris.h (EF_CRIS_UNDERSCORE): New. + +2000-09-27 Alan Modra + + * hppa.h (R_PARISC_DIR14F): Add. + +2000-09-14 Alexandre Oliva + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change + numbers to the range from 160 to 167. + (R_SH_FIRST_INVALID_RELOC): Adjust. + (R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2): + New relocs to fill in the gap. + +2000-09-13 Anders Norlander + + * mips.h (E_MIPS_MACH_4K): New define. + +2000-09-05 Alan Modra + + * hppa.h: Fix a comment. + (R_PARISC_PCREL12F): Define. + (R_PARISC_GNU_VTENTRY): Define. + (R_PARISC_GNU_VTINHERIT): Define. + +2000-09-01 Alexandre Oliva + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): New relocs. + (R_SH_FIRST_INVALID_RELOC): Adjust. + +2000-08-14 Jim Wilson + + * ia64.h (EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP, + EF_IA_64_NOFUNCDESC_CONS_GP, EF_IA_64_ABSOLUTE): Define. + +2000-08-07 Nick Clifton + + * ppc.h: Remove spurious CYGNUS LOCAL comments. + * v850.h: Likewise. + +2000-07-22 Jason Eckhardt + + * i860.h: New file. + (elf_i860_reloc_type): Defined ELF32 i860 relocations. + +2000-07-20 Hans-Peter Nilsson + + common.h (EM_CRIS): New machine number. + cris.h: New file. + +2000-07-19 H.J. Lu + + * common.h (DF_1_NODEFLIB): Renamed from DF_1_NODEPLIB. + +2000-07-19 H.J. Lu + + * common.h (DT_CHECKSUM): Set to 0x6ffffdf8. + (DTF_1_CONFEXP): It is 0x00000002 as suspected. + +2000-07-19 H.J. Lu + + * common.h (DT_FEATURE): Renamed from DT_FEATURE_1. + (DT_CONFIG): New. From Solaris 8. + (DT_DEPAUDIT): Likewise. + (DT_AUDIT): Likewise. + (DT_PLTPAD): Likewise. + (DT_MOVETAB): Likewise. + (DF_1_NODEPLIB): Likewise. + (DF_1_NODUMP): Likewise. + (DF_1_CONLFAT): Likewise. + (DT_CHECKSUM): Likewise. FIXME. Check the value on Solaris 8. + (DTF_1_CONFEXP): Likewise. + +2000-07-18 H.J. Lu + + * common.h (DT_FLAGS_1): Renamed from DT_1_FLAGS. + +2000-07-12 Alan Modra + + * internal.h (struct elf_internal_sym): Update comment for st_other. + +2000-07-10 Alan Modra + + * hppa.h: Add comments to all the relocs. + +2000-06-26 Marek Michalkiewicz + + * avr.h (E_AVR_MACH_AVR5): Define. + +2000-06-18 Stephane Carrez + + * m68hc11.h: New file, definitions for the Motorola 68hc11. + +2000-06-06 Alan Modra + + * reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy + -1 valued enum. + (RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC): Append rather than + prepend comma. + (END_RELOC_NUMBERS): Give macro an arg to define as last enum. + + * alpha.h (R_ALPHA_max): Define via END_RELOC_NUMBERS rather than + with EMPTY_RELOC. + * arc.h (R_ARC_max): Likewise. + * avr.h (R_AVR_max): Likewise. + * fr30.h (R_FR30_max): Likewise. + * hppa.h (R_PARISC_UNIMPLEMENTED): Likewise. + * i960.h (R_960_max): Likewise. + * m32r.h (R_M32R_max): Likewise. + * m68k.h (R_68K_max): Likewise. + * mcore.h (R_MCORE_max): Likewise. + * mn10300.h (R_MN10300_MAX): Likewise. + * pj.h (R_PJ_max): Likewise. + * ppc.h (R_PPC_max): Likewise. + * sh.h (R_SH_max): Likewise. + * sparc.h (R_SPARC_max): Likewise. + * v850.h (R_V850_max): Likewise. + + * arm.h (R_ARM_max): Define via END_RELOC_NUMBERS. + * d10v.h (R_D10V_max): Likewise. + * d30v.h (R_D30V_max): Likewise. + * ia64.h (R_IA64_max): Likewise. + * mips.h (R_MIPS_maxext): Likewise. + * mn10200.h (R_MN10200_max): Likewise. + + * i386.h (R_386_max): Remove old RELOC_NUMBER definition, and + define via END_RELOC_NUMBERS. + +2000-06-03 Alan Modra + + * reloc-macros.h (START_RELOC_NUMBERS): Fix name clash for + !__STDC__ case. + (RELOC_NUMBER): Use ansi stringify if ALMOST_STDC defined. + +2000-05-22 Richard Henderson + + * ia64.h (R_IA64_PCREL60B, R_IA64_PCREL21BI): New. + (R_IA64_PCREL22, R_IA64_PCREL64I): New. + +2000-05-02 H.J. Lu + + * common.h (ELFOSABI_NONE): Renamed from ELFOSABI_SYSV. + (ELFOSABI_MODESTO): Defined. + (ELFOSABI_OPENBSD): Likewise. + +2000-04-21 Richard Henderson + David Mosberger + + * ia64.h: New file. + +2000-04-14 H.J. Lu + + * common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64. + +2000-04-14 H.J. Lu + + * common.h (ELFOSABI_NETBSD): Defined. + (ELFOSABI_HURD): Likewise. + (ELFOSABI_SOLARIS): Likewise. + (ELFOSABI_MONTEREY): Likewise. + (ELFOSABI_IRIX): Likewise. + (ELFOSABI_FREEBSD): Likewise. + (ELFOSABI_TRUE64): Likewise. + +2000-04-07 Nick Clifton + + * arm-oabi.h: Delete. + * arm.h: Merge in definitions of old reloc numbers from + arm-oabi.h. + +2000-04-06 Nick Clifton + + * arm.h (EF_ARM_SYMSARESORTED): Define. + (EF_ARM_EABIMASK): Define. + (EF_ARM_EABI_VERSION): Define. + (EF_ARM_EABI_UNKNOWN): Define. + (EF_ARM_EABI_VER1): Define. + (PF_ARM_PI): Define. + (PF_ARM_ABS): Define. + +2000-04-05 J"orn Rennecke + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs. + +2000-03-27 Denis Chertykov + + * avr.h: New file. AVR ELF support for BFD. + * common.h: Add AVR magic number. + +2000-03-10 Geoffrey Keating + + * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. + +2000-02-23 Linas Vepstas + + * i370.h: New file. + +2000-02-22 Nick Clifton + + * common.h (ELF_ST_OTHER): Remove definition. + (ELF32_ST_OTHER): Remove definition. + (ELF64_ST_OTHER): Remove definition. + +2000-02-22 H.J. Lu + + * common.h (ELFOSABI_LINUX): Define. + +2000-02-17 J"orn Rennecke + + * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. + (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. + (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. + +2000-02-03 H.J. Lu + + * arm-oabi.h: Duplicate changes made to arm.h on Jan. 27, + 2000 by Thomas de Lellis . + +2000-01-27 Thomas de Lellis + + * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. + (STT_ARM_16BIT): New flag. Denotes a label that was defined in + Thumb block but was does not identify a function. + +2000-01-20 Nick Clifton + + * common.h (EM_MCORE): Fix spelling of Motorola. + * mcore.h (EM_MCORE): Fix spelling of Motorola. + +2000-01-13 Nick Clifton + + * common.h (EM_S370): Change comment - this is now the IBM + System/370. + (EM_IA_64): Change comment - this is now the IA-64. + +2000-01-11 Nick Clifton + + * common.h (DT_ENCODING): Fix definition of this value. + (DT_LOOS): Fix definition of this value. + (DT_HIOS): Fix definition of this value. + (OLD_DT_LOOS): Value of DT_LOOS before Oct 4, 1999 draft + of ELF spec changed it. + (OLD_DT_HIOS): Value of DT_HIOS before Oct 4, 1999 draft + of ELF spec changed it. + +2000-01-10 Egor Duda + + * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). + +1999-12-28 Nick Clifton + + * mips.h (STO_*): Redefine in terms of STV_* values now in + common.h. + +1999-12-27 Nick Clifton + + * common.h: Upgrade to match Oct4, 1999 Draft ELF ABI Spec. + (EM_MIPS_RS3_LE): New machine number. + (EM_RCE): New machine number. + (EM_MMA): New machine number. + (EM_PCP): New machine number. + (EM_NCPU): New machine number. + (EM_NDR1): New machine number. + (EM_STARCORE): New machine number. + (EM_ME16): New machine number. + (EM_ST100): New machine number. + (EM_TINYJ): New machine number. + (EM_FX66): New machine number. + (EM_ST9PLUS): New machine number. + (EM_ST7): New machine number. + (EM_68HC16): New machine number. + (EM_68HC11): New machine number. + (EM_68HC08): New machine number. + (EM_68HC05): New machine number. + (EM_SVX): New machine number. + (EM_VAX): New machine number. + (PF_MASKOS): Change value. + (SHT_INIT_ARRAY): New value for sh_type field. + (SHT_FINI_ARRAY): New value for sh_type field. + (SHT_PREINIT_ARRAY): New value for sh_type field. + (SHT_HIUSER): Change value. + (SHF_MERGE): New valye for sh_flags field. + (SHF_STRINGS): New valye for sh_flags field. + (SHF_INFO_LINK): New valye for sh_flags field. + (SHF_OS_NONCONFORMING): New valye for sh_flags field. + (SHF_MASKOS): Change value. + (ELF_ST_VISIBILITY): New macro. + (ELF_ST_OTHER): New macro. + (STT_COMMON): New symbol type. + (STV_DEFAULT): Value for symbol visibility. + (STV_INTERNAL): Value for symbol visibility. + (STV_HIDDEN): Value for symbol visibility. + (STV_PROTECTED): Value for symbol visibility. + (DT_RUNPATH): New dynamic section tag. + (DT_FLAGS): New dynamic section tag. + (DT_ENCODING): New dynamic section tag. + (DT_PREINIT_ARRAY): New dynamic section tag. + (DT_PREINIT_ARRAYSZ): New dynamic section tag. + (DT_LOPROC): New dynamic section tag index. + (DT_HIPROC): New dynamic section tag index. + (DF_ORIGIN): Value for dynamic section flag. + (DF_SYMBOLIC): Value for dynamic section flag. + (DF_TEXTREL): Value for dynamic section flag. + (DF_BIND_NOW): Value for dynamic section flag. + +1999-12-09 Fred Fish + + * i960.h (reloc-macros.h): Include using relative dir elf/. + * i386.h (reloc-macros.h): Include using relative dir elf/. + * hppa.h (reloc-macros.h): Include using relative dir elf/. + +1999-12-07 Jim Blandy + + * common.h (NT_PRXFPREG): New definition. + +Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (E_MN10300_MACH_AM33): Define. + +Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (PF_HP_PAGE_SIZE): Define. + (PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise. + (PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise. + +Mon Oct 4 17:42:38 1999 Doug Evans + + * m32r.h (E_M32RX_ARCH): Define. + +1999-09-15 Ulrich Drepper + + * hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL. + +1999-09-04 Steve Chamberlain + + * pj.h: New file. + * common.h (EM_PJ): Define. + +1999-09-02 Ulrich Drepper + + * hppa.h: Add HPUX specific symbol type definitions. + + * hppa.h: Add HPUX specific dynamic and program header table + specific definitions. + +1999-08-31 Scott Bambrough + + * common.h (NT_TASKSTRUCT): Define. + +1999-07-16 Jakub Jelinek + + * sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions + flag (as per SCD2.4.1). + +1999-07-16 Jakub Jelinek + + * sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not + ELF64_R_SYM bits. + +1999-06-21 Philip Blundell + + * arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define. + +1999-07-13 Andreas Schwab + + * m68k.h (EF_CPU32): Move definition inside multiple inclusion + guard. + +1999-07-08 Richard Henderson + + * sparc.h (ELF64_R_TYPE_DATA): Sign extend the value. + (ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data. + (DT_SPARC_PLTFMT): Delete. + Based on a patch from Jakub Jelinek. + +Mon Jun 21 16:36:02 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type. + +1999-06-10 Jakub Jelinek + + * sparc.h (R_SPARC_max_std): Define. + +Wed Jun 9 15:16:34 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Update with various changes from newest PA ELF + specifications. + +1999-06-03 Ian Lance Taylor + + * common.h (EM_PPC64): Define. + +1999-06-02 Stu Grossman + + * dwarf.h: Add LANG_JAVA. + * dwarf2.h: Add DW_LANG_Java. + +1999-05-29 Nick Clifton + + * common.h (ELFOSABI_ARM): Define. + +1999-05-28 Nick Clifton + + * reloc-macros.h: Update comment. + +1999-05-28 Ian Lance Taylor + + * i960.h: New file. + +1999-05-16 Nick Clifton + + * mcore.h (R_MCORE_COPY): Define. + (R_MCORE_GLOB_DAT): Define. + (R_MCORE_JUMP_SLOT): Define. + +1999-05-15 Nick Clifton + + * mcore.h (R_MCORE_RELATIVE): Define. + +1999-05-05 Catherine Moore + + * m68k.h (EF_CPU32): Define. + +1999-04-21 Nick Clifton + + * reloc-macros.h (START_RELOC_NUMBERS): Prepend an underscore to + fake reloc entry name (if possible), in order to avoid conflicts + with typedefs of the same name. + +1999-04-16 Gavin Romig-Koch + + * mips.h (EF_MIPS_32BITMODE): New. + +1999-04-08 Nick Clifton + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +1999-04-08 Nick Clifton + + * common.h: Add new constants defined in: "System V Application + Binary Interface - DRAFT - April 29, 1998" found at the web site: + http://www.sco.com/developer/gabi/contents.html + + (EM_MMA): Removed. Replaced with EM_MCORE as Motorolla own this + value. + +1999-03-31 Nick Clifton + + * reloc-macros.h: Fixed to not generate an enum with a trailing + comma. + +1999-03-16 Gavin Romig-Koch + + * mips.h (E_MIPS_MACH_5000): New. + +1999-03-10 Ulrich Drepper + + * common.h: Add definitions for a few more Solaris ELF extensions. + +Thu Feb 18 18:58:26 1999 Ian Lance Taylor + + * external.h: Only use attribute if __GNUC__ is defined. + +1999-02-17 Nick Clifton + + Patch submitted by: Scott Bambrough + + * external.h: struct Elf_External_Versym must be packed on + ARM. Code uses sizeof(Elf_External_Versym) and assumes it is + equal to sizeof(char[2]). Reported by Jim Pick + +1999-02-02 Nick Clifton + + * dwarf2.h (DWARF2_External_ARange): New structure. + (DWARF2_Internal_ARange): New structure. + +Mon Feb 1 11:33:56 1999 Catherine Moore + + * arm.h: Renumber relocs to conform to standard. + (EF_NEW_ABI): Define. + (EF_OLD_ABI): Define. + * arm-oabi.h: New file. + +1999-01-28 Nick Clifton + + * fr30.h: Add R_FR30_GNU_VT{INHERIT,ENTRY} relocs. + +1999-01-27 Nick Clifton + + * dwarf2.h: Add typedefs for structures found in dwarf2 sections. + +1998-12-16 Gavin Romig-Koch + + * mips.h (E_MIPS_MACH_4111): New. + +1998-12-15 Gavin Romig-Koch + + * mips.h (EF_MIPS_ABI,E_MIPS_ABI_O32,E_MIPS_ABI_O64, + E_MIPS_ABI_EABI32,E_MIPS_ABI_EABI64): + +1998-12-03 Nick Clifton + + * fr30.h: Add R_FR30_48 reloc. + +1998-12-02 Ulrich Drepper + + * mips.h: Add external data type for conflict section. + + * mips.h: Add more LL_* options from Irix 6.5. + + * mips.h: Add R_MIPS_JALR and adjust R_MIPS_max appropriately. + +Mon Nov 30 15:25:58 1998 J"orn Rennecke + + * sh.h (elf_sh_reloc_type): Add R_SH_FIRST_INVALID_RELOC, + R_SH_LAST_INVALID_RELOC, R_SH_SWITCH8 and R_SH_max. + +Tue Nov 10 15:12:28 1998 Nick Clifton + + * common.h (EM_CYGNUS_FR30): Reduce to a 16 bit value. + +Tue Nov 10 15:17:28 1998 Catherine Moore + + * d10v.h: Add vtable relocs. + +Wed Nov 4 15:56:50 1998 Nick Clifton + + * common.h (EM_CYGNUS_FR30): New machine number. + + * fr30.h: New file: Definitions for the FR30. + +Fri Oct 30 11:54:15 1998 Catherine Moore + + From Philip Blundell : + * arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC. + (EF_ALIGN8): New flag. + +Tue Oct 20 11:19:50 1998 Ian Lance Taylor + + * common.h (NT_LWPSTATUS): Close comment accidentally left open. + +Mon Oct 19 20:24:11 1998 Catherine Moore + + * sh.h: Add vtable relocs. + +Mon Oct 19 01:44:42 1998 Felix Lee + + * common.h (NT_PSTATUS, NT_FPREGS, NT_PSINFO, + NT_LWPSTATUS,NT_LWPSINFO): added. + * internal.h (Elf_Internal_Note): new structure members. + +Fri Oct 16 14:11:25 1998 Catherine Moore + + * m32r.h: Add vtable relocs. + +Tue Oct 6 09:22:22 1998 Catherine Moore + + * sparc.h: Add vtable relocs. + +Mon Oct 5 09:39:22 1998 Catherine Moore + + * v850.h: Add vtable relocs. + +Sun Oct 4 21:17:51 1998 Ian Lance Taylor + + * i386.h (R_386_max): Change from 252 to 24. + +Mon Sep 21 12:24:44 1998 Catherine Moore + + * i386.h: Change vtable reloc numbers. + +Sun Sep 20 00:54:22 1998 Andreas Schwab + + * m68k.h: Add vtable relocs and R_68K_max. + +Tue Sep 15 09:56:49 CDT 1998 Catherine Moore + + * arm.h: Add vtable relocs. + +Mon Aug 31 11:25:27 1998 Catherine Moore + + * arm.h: Define STT_ARM_TFUNC. Remove ST_THUMB_xxxx + definitions. + +Sat Aug 29 22:25:51 1998 Richard Henderson + + * i386.h: Add vtable relocs. + +1998-08-25 16:42 Ulrich Drepper + + * common.h: Add SYMINFO_* macros to access Elf*_Syminfo information. + + * external.h: Add Elf_External_Syminfo definition. + + * internal.h: Add Elf_Internal_Syminfo, Elf32_Internal_Syminfo, + and Elf64_Syminfo definitions. + +Sun Aug 9 20:26:49 CDT 1998 Catherine Moore + + * arm.h: Add ST_THUMB definitions. + +Wed Aug 5 15:52:35 1998 Nick Clifton + + * arm.h: Add ELF header flags to specify compile time optins: + EF_INTERWORK: New flag. + EF_APCS_26: New flag. + EF_APCS_FLOAT: New flag. + EF_PIC: New flag. + +1998-07-31 21:28 Ulrich Drepper + + * mips.h: Add missing RHF_* constants. + +Fri Jul 31 10:01:40 1998 Catherine Moore + + * arm.h: Add R_ARM_THM_PC9 relocation. + +1998-07-30 16:25 Ulrich Drepper + + * common.h: Add new DT_* entries and there flag macros from Solaris. + +Tue Jul 28 18:14:07 1998 Stan Cox + + * sparc.h: (R_SPARC_REV32): Added for little endian data e.g. sparc 86x. + +Fri Jul 24 11:22:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add R_MN10300_24 relocation. + +1998-07-24 Ulrich Drepper + + * mips.h: Add MIPS64 relocation names and values. + +Wed Jul 22 19:29:00 Catherine Moore + + * arm.h: Rename relocations. + +1998-07-22 Ulrich Drepper + + * ppc.h: Define enum as elf_ppc_reloc_type. + +Wed Jul 22 16:22:11 1998 Nick Clifton + + * reloc-macros.h: New file. Provides relocation macros: + START_RELOC_NUMBERS, RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC and + END_RELOC_NUMBERS used by other elf header files. + + * alpha.h: Use reloc-macros.h. + * arc.h: Use reloc-macros.h. + * arm.h: Use reloc-macros.h. + * d10v.h: Use reloc-macros.h. + * d30v.h: Use reloc-macros.h. + * hppa.h: Use reloc-macros.h. + * i386.h: Use reloc-macros.h. + * m32r.h: Use reloc-macros.h. + * m68k.h: Use reloc-macros.h. + * mips.h: Use reloc-macros.h. + * mn10200.h: Use reloc-macros.h. + * mn10300.h: Use reloc-macros.h. + * ppc.h: Use reloc-macros.h. + * sh.h: Use reloc-macros.h. + * sparc.h: Use reloc-macros.h. + * v850.h: Use reloc-macros.h. + +1998-07-22 13:07 Ulrich Drepper + + * mn10300.h: Rewrite relocation definition using macros. + * mips.h: Likewise. + * ppc.h: Likewise. + * alpha.h: Likewise. + * arm.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * m32r.h: Likewise. + * m68k.h: Likewise. + * mn10200.h: Likewise. + * sh.h: Likewise. + * sparc.h: Likewise. + +1998-07-21 13:07 Ulrich Drepper + + * arm.h: New file. + * d10v.h: New file. + * d30v.h: New file. + * i386.h: New file. + * m68k.h: New file. + * mn10200.h: New file. + * sh.h: New file. + + * mips.h: Add R_MIPS_* and SHT_MIPS_* entries. + + * mn10300.h: Add R_MN10300_* entries. + + * ppc.h: Add R_PPC_* entries. + +1998-07-20 07:11 Ulrich Drepper + + * mips.h: Add ODK_*, OEX_*, OPAD_*, OHW_*, and OGP_* constants. + Define Elf32_External_Lib. + +1998-07-19 15:24 Ulrich Drepper + + * mips.h (PT_MIPS_OPTIONS): New symbol. + Add lots of DT_MIPS_* symbols. + +Fri Jun 26 10:46:35 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: New file. + +Thu Jun 18 19:27:56 1998 Nick Clifton + + * common.h (EM_960, EM_V800, EM_FR20, EM_RH32, EM_MMA, + EM_OLD_ALPHA): Add these constants. + +Thu Jun 11 17:59:01 1998 Nick Clifton + + * common.h (EM_486, EM_S370): Add these constants. + +Tue Jun 9 09:35:29 1998 Nick Clifton + + * common.h (EM_ARM): Add this constant. + +Wed May 6 09:45:30 1998 Gavin Koch + + * mips.h (EF_MIPS_MACH,E_MIPS_MACH_*): Added. + +Sat Apr 25 18:35:06 1998 Richard Henderson + + * alpha.h (STO_ALPHA_NOPV, STO_ALPHA_STD_GPLOAD): New. + +Wed Apr 15 15:42:45 1998 Richard Henderson + + * common.h (EM_SPARC64): Move and rename to EM_OLD_SPARCV9. + (EM_SPARCV9): New. This is the official ABI name and number. + +Sat Feb 28 17:04:41 1998 Richard Henderson + + * alpha.h (EF_ALPHA_32BIT, EF_ALPHA_CANRELAX): New. + +Mon Dec 15 15:07:49 1997 Nick Clifton + + * m32r.h (EF_M32R_ARCH, E_M32R_ARCH): New flags to + specify machine architecture. + +Fri Dec 5 11:20:08 1997 Nick Clifton + + * v850.h: New constants: SHN_V850_SCOMMON, SHN_V850_TCOMMON, + SHN_V850_ZCOMMON, SHT_V850_SCOMMON, SHT_V850_TCOMMON, + SHT_V850_ZCOMMON to handle v850 common sections. + enum reloc_type renamed to v850_reloc_type to avoid name + conflict. + +Thu Oct 23 13:55:24 1997 Richard Henderson + + * sparc.h (enum elf_sparc_reloc_type): Add UA64 & UA16. + +Thu Oct 23 00:42:04 1997 Richard Henderson + + * sparc.h (DT_SPARC_REGISTER): New macro. + (DT_SPARC_PLTFMT): In support of old sparc64-linux .plts; will + go away soon. + +Tue Sep 30 13:26:58 1997 Doug Evans + + * sparc.h (EF_SPARC_HAL_R1, EF_SPARC_EXT_MASK): New macros. + (EF_SPARCV9_{MM,TSO,PSO,RMO}): New macros. + (SHN_BEFORE,SHN_AFTER): New macros. + (SHF_EXCLUDE,SHF_ORDERED): New macros. + (STT_REGISTER): New macro. + (R_SPARC_GLOB_JMP): Deleted, but slot reserved. + (R_SPARC_{DISP64,PLT64,HIX22,LOX10}): New relocations. + (R_SPARC_{H44,M44,L44,REGISTER}): New relocations. + (ELF64_R_TYPE_{DATA,ID,INFO}): New macros. + +Wed Sep 17 16:41:42 1997 Nick Clifton + + * v850.h: Add R_V850_CALLT_6_7_OFFSET and R_V850_CALLT_16_16_OFFSET. + +Tue Sep 16 14:16:17 1997 Nick Clifton + + * v850.h (reloc_type): Add R_V850_TDA_16_16_OFFSET. + +Wed Sep 3 15:11:14 1997 Richard Henderson + + * mips.h: Correct typo in comment. + +Wed Sep 3 11:25:57 1997 Nick Clifton + + * v850.h (reloc_type): Remove R_V850_16_PCREL. + +Tue Sep 2 17:41:05 1997 Nick Clifton + + * common.h: Remove magic number for V850E. + * common.h: Remove magic number for V850EA. + * v850.h: Add new flags for e_flags field in elf header. + +Mon Aug 25 16:06:47 1997 Nick Clifton + + * common.h (EM_CYGNUS_V850E): backend magic number for v850e. + * common.h (EM_CYGNUS_V850EA): backend magic number for v850ea. + +Mon Aug 18 11:05:23 1997 Nick Clifton + + * v850.h (reloc_type): Add 16 bit PC relative relocation. + +Fri Aug 15 05:10:09 1997 Doug Evans + + * arc.h (enum reloc): Move here from elf32-arc.c. + +Fri Aug 8 17:05:29 1997 Doug Evans + + * arc.h: New file. + * common.h (EM_CYGNUS_ARC): Define. + +Mon Jun 16 14:46:12 1997 Ian Lance Taylor + + * internal.h (Elf_Internal_Ehdr): Change e_phoff and e_shoff from + bfd_signed_vma to bfd_size_type, as they are not signed. + +Wed Mar 5 15:35:26 1997 Doug Evans + + * m32r.h (SHF_M32R_CAN_RELAX): Define. + +Mon Feb 24 17:49:01 1997 Ian Lance Taylor + + * external.h: Dump the 32/64 bit specific forms of the version + structures, and just define them as size independent. + + * common.h (VERSYM_HIDDEN, VERSYM_VERSION): Define. + +Fri Feb 21 13:00:34 1997 Doug Evans + + * m32r.h (enum reloc_type): Add R_M32R_SDA16. + (SHN_M32R_SCOMMON): Define. + +Wed Feb 19 15:35:31 1997 Ian Lance Taylor + + From Eric Youngdale : + * external.h, internal.h, common.h: Added new structures and + definitions for ELF versions. + +Tue Feb 18 17:40:36 1997 Martin M. Hunt + + * common.h (EM_CYGNUS_D30V): Define. + +Mon Jan 27 11:54:44 1997 Doug Evans + + * m32r.h (enum reloc_type): Add R_M32R_HI16_[SU]LO,R_M32R_LO16. + +Fri Jan 3 11:32:51 1997 Michael Meissner + + * v850.h (V850_OTHER_{TDA_BYTE,ERROR}): New bits for the st_other + field. + (SHN_V850_*): Remove v850 specific section indexes, which are not + needed. + (enum reloc_type): Move the v850 relocations here from + elf32-v850.c + +Thu Jan 2 19:30:23 1997 Michael Meissner + + * v850.h: New file, provide V850 specific definitions. + +Tue Dec 31 14:44:32 1996 Ian Lance Taylor + + * common.h (DT_AUXILIARY): Define. + (DT_FILTER): Define. + +Wed Dec 4 05:03:37 1996 Jason Merrill + + * dwarf2.h: Update. + +Tue Nov 26 10:44:47 1996 Ian Lance Taylor + + * mips.h (STO_MIPS16): Define. + +Tue Nov 12 15:45:42 1996 Martin M. Hunt + + * d10v.h: Remove empty file. + +Tue Oct 8 11:31:24 1996 Ian Lance Taylor + + * mips.h (EF_MIPS_ABI2): Define. + +Thu Oct 3 10:01:40 1996 Jeffrey A Law (law@cygnus.com) + + * common.h: Break mn10x00 support into mn10200 and mn10300. + +Wed Oct 2 21:26:43 1996 Jeffrey A Law (law@cygnus.com) + + * common.h (EM_CYGNUS_MN10x00): Define. + +Mon Sep 23 09:18:04 1996 Doug Evans + + * m32r.h: New file. + +Fri Aug 30 17:06:21 1996 Ian Lance Taylor + + * common.h (EM_SH): Define. + +Tue Aug 20 14:47:54 1996 J.T. Conklin + + * common.h (EM_CYGNUS_V850): Define. + +Mon Aug 19 10:59:10 1996 Doug Evans + + * common.h (EM_CYGNUS_M32R): Define. + +Mon Jul 22 18:59:55 1996 Ian Lance Taylor + + * mips.h (SHT_MIPS_IFACE, SHT_MIPS_CONTENT): Define. + (SHT_MIPS_SYMBOL_LIB): Define. + (SHF_MIPS_MERGE, SHF_MIPS_ADDR32, SHF_MIPS_ADDR64): Define. + (SHF_MIPS_NOSTRIP, SHF_MIPS_LOCAL, SHF_MIPS_NAMES): Define. + +Thu Jul 18 19:12:15 1996 Stan Shebs + + * dwarf2.h: New file. + +Jul 18 13:20:39 1996 Martin M. Hunt + + * common.h (EM_CYGNUS_D10V): Define. + * d10v.h: New file. + +Fri Jun 21 12:33:24 1996 Richard Henderson + + * alpha.h: New file. + * common.h (EM_ALPHA): Define. + +Fri May 31 17:28:05 1996 Ian Lance Taylor + + * mips.h (Elf_External_Options, Elf_Internal_Options): Define. + (bfd_mips_elf_swap_options_in): Declare. + (bfd_mips_elf_swap_options_out): Declare. + (ODK_*): Define. + (Elf64_External_RegInfo, Elf64_Internal_RegInfo): Define. + (bfd_mips_elf64_swap_reginfo_in): Declare. + (bfd_mips_elf64_swap_reginfo_out): Declare. + +Thu May 30 12:35:57 1996 Ian Lance Taylor + + * mips.h (E_MIPS_ARCH_4): Define. + +Wed May 29 15:35:33 1996 Ian Lance Taylor + + * mips.h (Elf64_Mips_External_Rel): Define. + (Elf64_Mips_Internal_Rel): Define. + (Elf64_Mips_External_Rela, Elf64_Mips_Internal_Rela): Define. + (RSS_*): Define. + +Mon Apr 22 18:26:30 1996 Doug Evans + + * sparc.h (R_SPARC_[56]): Always define. + +Mon Feb 19 01:55:56 1996 Doug Evans + + * sparc.h (R_SPARC_{PLT32,HIPLT22,LOPLT10,PCPLT32,PCPLT22, + PCPLT10,5,6}): Don't define ifdef SPARC64_OLD_RELOCS. + +Tue Feb 6 11:33:58 1996 Doug Evans + + * sparc.h (enum sparc_elf_reloc_type): Define. + +Wed Jan 17 09:09:16 1996 Doug Evans + + * common.h: Define EM_SPARC32PLUS. + * sparc.h: New file. + +Thu Jan 11 16:27:34 1996 Michael Meissner + + * ppc.h (SHF_EXCLUDE, SHT_ORDERED): New fields from the abi. + +Thu Nov 30 16:47:18 1995 Ian Lance Taylor + + * internal.h (struct elf_segment_map): Add includes_filehdr and + includes_phdrs fields. + +Tue Nov 28 16:58:10 1995 Ian Lance Taylor + + * internal.h (struct elf_segment_map): Define. + +Tue Oct 31 15:19:36 1995 Fred Fish + + * common.h, dwarf.h, external.h, hppa.h, internal.h, + mips.h, ppc.h: Protect against multiple inclusions. + +Thu Sep 21 13:51:58 1995 Michael Meissner + + * ppc.h (EF_PPC_RELOCATABLE_LIB): Add new flag bit. + +Fri Sep 1 15:32:17 1995 Kazumoto Kojima + + * mips.h: Add some definitions used on Irix 5. + +Tue Jun 20 10:18:28 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (CPU_PA_RISC1_0): Protect from redefinitions. + (CPU_PA_RISC1_1): Likewise. + +Wed Mar 8 18:14:37 1995 Michael Meissner + + * ppc.h: New file for PowerPC support. + +Tue Feb 14 13:59:13 1995 Michael Meissner + + * common.h (EM_PPC): Use offical value of 20, not 17. + (EM_PPC_OLD): Define this to be the old value of EM_PPC. + +Tue Jan 24 09:40:59 1995 Michael Meissner + + * common.h (EM_PPC): New macro, PowerPC machine id. + +Tue Jan 17 10:51:38 1995 Ian Lance Taylor + + * mips.h (SHT_MIPS_MSYM, SHT_MIPS_DWARF, SHT_MIPS_EVENTS): Define. + +Mon Oct 17 13:43:59 1994 Ian Lance Taylor + + * internal.h (Elf_Internal_Shdr): Remove rawdata and size fields. + Add bfd_section field. + +Tue May 24 16:11:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (Elf32_External_gptab): Define. + +Mon May 16 13:22:04 1994 Jeff Law (law@snake.cs.utah.edu) + + * common.h (EM_HPPA): Delete. + (EM_PARISC): Add. + * hppa.h: New file. + +Mon May 9 13:27:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (SHN_LORESERVE): Rename from SHN_LORESERV. + (ELF32_R_TYPE, ELF32_R_INFO): Don't rely on size of unsigned char. + (ELF64_R_TYPE): Don't rely on size of unsigned long. + +Mon Apr 25 15:53:09 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (Elf_Internal_Shdr): Use PTR, not void *. + +Fri Mar 11 00:34:59 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * mips.h (SHN_MIPS_TEXT, SHN_MIPS_DATA): Define. + +Sat Mar 5 14:08:54 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * internal.h: Remove Elf32_*, Elf64_* typedefs. These names + cause conflicts with system headers, e.g. link.h in gdb/solib.c. + Combine 32- and 64-bit versions of *_Internal_Dyn. + * common.h: Replace uses of Elf64_Word, Elf64_Xword typedefs + by their expansion. + * mips.h: Replace uses of Elf32_Word, Elf32_Sword, Elf32_Addr + typedefs by their expansion. Add DT_MIPS_RLD_MAP definition. + +Fri Feb 18 10:39:54 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (EM_CYGNUS_POWERPC): Define. This may be temporary, + depending upon how quickly I can find a real PowerPC ABI. + +Mon Feb 7 08:27:13 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT. + +Wed Feb 2 14:12:18 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * common.h: Add comments regarding value of EM_HPPA and how to + pick an unofficial value. + +Wed Nov 17 17:14:26 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (SHT_MIPS_OPTIONS): Define. + +Mon Nov 8 17:57:00 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Added some more MIPS ABI macro definitions. + +Wed Nov 3 22:07:17 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * common.h (EM_MIPS_RS4_BE): New macro. + +Tue Oct 12 07:28:18 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: New file. MIPS ABI specific information. + +Mon Jun 21 13:13:43 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * internal.h: Combined 32- and 64-bit versions of all structures + except *_Internal_Dyn. This will simply the assembler interface, + and some bfd code. + +Tue May 25 02:00:16 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * external.h, internal.h, common.h: Added 64-bit versions of some + structures and macros. Renamed old versions to put "32" in the + name. Some are unchanged. + +Thu Apr 29 12:12:20 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * common.h (EM_HPPA, NT_VERSION, STN_UNDEF, DT_*): New macros. + * external.h (Elf_External_Dyn): New type. + + * internal.h (Elf_Intenral_Shdr): New field `size'. + (Elf_Internal_Dyn): New type. + +Tue Apr 20 16:03:45 1993 Fred Fish (fnf@cygnus.com) + + * dwarf.h (LANG_CHILL): Change value to one randomly picked in + the user defined range, to reduce probability of collisions. + +Sun Nov 15 09:34:02 1992 Fred Fish (fnf@cygnus.com) + + * dwarf.h (AT_src_coords): Whitespace change only. + * dwarf.h (AT_body_begin, AT_body_end, LANG_MODULA2): + Add from latest gcc. + * dwarf.h (LANG_CHILL): Add as GNU extension. + +Sat Aug 1 13:46:53 1992 Fred Fish (fnf@cygnus.com) + + * dwarf.h: Replace with current version from gcc distribution. + +Fri Jun 19 19:05:09 1992 John Gilmore (gnu at cygnus.com) + + * internal.h: Add real struct tags to all the Type_Defs, so they + can be used in prototypes where the Type_Defs are not known. + +Fri Apr 3 20:58:58 1992 Mark Eichin (eichin at cygnus.com) + + * common.h: added ELF_R_{SYM,TYPE,INFO} for handling relocation + info + added EM_MIPS, and corrected value of EM_860 based on System V ABI + manual. + + * external.h: added Elf_External_{Rel,Rela}. + + * internal.h: added Elf_Internal_{Rel,Rela}. + added rawdata to Elf_Internal_Shdr. + +Sat Nov 30 20:43:59 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * common.h, dwarf.h, external.h, internal.h, ChangeLog; moved from + ../elf- + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/elf/alpha.h b/external/gpl3/gdb/dist/include/elf/alpha.h new file mode 100644 index 000000000000..f4fe566b0818 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/alpha.h @@ -0,0 +1,131 @@ +/* ALPHA ELF support for BFD. + Copyright 1996, 1998, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. + + By Eric Youngdale, . No processor supplement available + for this platform. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the ALPHA ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_ALPHA_H +#define _ELF_ALPHA_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* All addresses must be below 2GB. */ +#define EF_ALPHA_32BIT 0x00000001 + +/* All relocations needed for relaxation with code movement are present. */ +#define EF_ALPHA_CANRELAX 0x00000002 + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_ALPHA_GPREL 0x10000000 + +/* Section contains some sort of debugging information. The exact + format is unspecified. It's probably ECOFF symbols. */ +#define SHT_ALPHA_DEBUG 0x70000001 + +/* Section contains register usage information. */ +#define SHT_ALPHA_REGINFO 0x70000002 + +/* A section of type SHT_MIPS_REGINFO contains the following + structure. */ +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + long ri_gp_value; +} Elf64_RegInfo; + +/* Special values for the st_other field in the symbol table. */ + +#define STO_ALPHA_NOPV 0x80 +#define STO_ALPHA_STD_GPLOAD 0x88 + +/* Special values for Elf64_Dyn tag. */ +#define DT_ALPHA_PLTRO DT_LOPROC + +#include "elf/reloc-macros.h" + +/* Alpha relocs. */ +START_RELOC_NUMBERS (elf_alpha_reloc_type) + RELOC_NUMBER (R_ALPHA_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_ALPHA_REFLONG, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_ALPHA_REFQUAD, 2) /* Direct 64 bit */ + RELOC_NUMBER (R_ALPHA_GPREL32, 3) /* GP relative 32 bit */ + RELOC_NUMBER (R_ALPHA_LITERAL, 4) /* GP relative 16 bit w/optimization */ + RELOC_NUMBER (R_ALPHA_LITUSE, 5) /* Optimization hint for LITERAL */ + RELOC_NUMBER (R_ALPHA_GPDISP, 6) /* Add displacement to GP */ + RELOC_NUMBER (R_ALPHA_BRADDR, 7) /* PC+4 relative 23 bit shifted */ + RELOC_NUMBER (R_ALPHA_HINT, 8) /* PC+4 relative 16 bit shifted */ + RELOC_NUMBER (R_ALPHA_SREL16, 9) /* PC relative 16 bit */ + RELOC_NUMBER (R_ALPHA_SREL32, 10) /* PC relative 32 bit */ + RELOC_NUMBER (R_ALPHA_SREL64, 11) /* PC relative 64 bit */ + + /* Skip 12 - 16; deprecated ECOFF relocs. */ + + RELOC_NUMBER (R_ALPHA_GPRELHIGH, 17) /* GP relative 32 bit, high 16 bits */ + RELOC_NUMBER (R_ALPHA_GPRELLOW, 18) /* GP relative 32 bit, low 16 bits */ + RELOC_NUMBER (R_ALPHA_GPREL16, 19) /* GP relative 16 bit */ + + /* Skip 20 - 23; deprecated ECOFF relocs. */ + + /* These relocations are specific to shared libraries. */ + RELOC_NUMBER (R_ALPHA_COPY, 24) /* Copy symbol at runtime */ + RELOC_NUMBER (R_ALPHA_GLOB_DAT, 25) /* Create GOT entry */ + RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26) /* Create PLT entry */ + RELOC_NUMBER (R_ALPHA_RELATIVE, 27) /* Adjust by program base */ + + /* Like BRADDR, but assert that the source and target object file + share the same GP value, and adjust the target address for + STO_ALPHA_STD_GPLOAD. */ + RELOC_NUMBER (R_ALPHA_BRSGP, 28) + + /* Thread-Local Storage. */ + RELOC_NUMBER (R_ALPHA_TLSGD, 29) + RELOC_NUMBER (R_ALPHA_TLSLDM, 30) + RELOC_NUMBER (R_ALPHA_DTPMOD64, 31) + RELOC_NUMBER (R_ALPHA_GOTDTPREL, 32) + RELOC_NUMBER (R_ALPHA_DTPREL64, 33) + RELOC_NUMBER (R_ALPHA_DTPRELHI, 34) + RELOC_NUMBER (R_ALPHA_DTPRELLO, 35) + RELOC_NUMBER (R_ALPHA_DTPREL16, 36) + RELOC_NUMBER (R_ALPHA_GOTTPREL, 37) + RELOC_NUMBER (R_ALPHA_TPREL64, 38) + RELOC_NUMBER (R_ALPHA_TPRELHI, 39) + RELOC_NUMBER (R_ALPHA_TPRELLO, 40) + RELOC_NUMBER (R_ALPHA_TPREL16, 41) + +END_RELOC_NUMBERS (R_ALPHA_max) + +#define LITUSE_ALPHA_ADDR 0 +#define LITUSE_ALPHA_BASE 1 +#define LITUSE_ALPHA_BYTOFF 2 +#define LITUSE_ALPHA_JSR 3 +#define LITUSE_ALPHA_TLSGD 4 +#define LITUSE_ALPHA_TLSLDM 5 +#define LITUSE_ALPHA_JSRDIRECT 6 + +#endif /* _ELF_ALPHA_H */ diff --git a/external/gpl3/gdb/dist/include/elf/arc.h b/external/gpl3/gdb/dist/include/elf/arc.h new file mode 100644 index 000000000000..a07ed2e3ab5b --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/arc.h @@ -0,0 +1,57 @@ +/* ARC ELF support for BFD. + Copyright 1995, 1997, 1998, 2000, 2001, 2010 Free Software Foundation, Inc. + Contributed by Doug Evans, (dje@cygnus.com) + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the ARC ELF ABI. */ + +#ifndef _ELF_ARC_H +#define _ELF_ARC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_arc_reloc_type) + RELOC_NUMBER (R_ARC_NONE, 0) + RELOC_NUMBER (R_ARC_32, 1) + RELOC_NUMBER (R_ARC_B26, 2) + RELOC_NUMBER (R_ARC_B22_PCREL, 3) +END_RELOC_NUMBERS (R_ARC_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit ARC machine type field. */ + +#define EF_ARC_MACH 0x0000000f + +/* Various CPU types. */ + +#define E_ARC_MACH_ARC5 0 +#define E_ARC_MACH_ARC6 1 +#define E_ARC_MACH_ARC7 2 +#define E_ARC_MACH_ARC8 3 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */ + +/* File contains position independent code. */ + +#define EF_ARC_PIC 0x00000100 + +#endif /* _ELF_ARC_H */ diff --git a/external/gpl3/gdb/dist/include/elf/arm.h b/external/gpl3/gdb/dist/include/elf/arm.h new file mode 100644 index 000000000000..5b01835a74ad --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/arm.h @@ -0,0 +1,337 @@ +/* ARM ELF support for BFD. + Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_ARM_INTERWORK 0x04 +#define EF_ARM_APCS_26 0x08 +#define EF_ARM_APCS_FLOAT 0x10 +#define EF_ARM_PIC 0x20 +#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_ARM_NEW_ABI 0x80 +#define EF_ARM_OLD_ABI 0x100 +#define EF_ARM_SOFT_FLOAT 0x200 +#define EF_ARM_VFP_FLOAT 0x400 +#define EF_ARM_MAVERICK_FLOAT 0x800 + +/* Frame unwind information */ +#define PT_ARM_EXIDX (PT_LOPROC + 1) + +/* Other constants defined in the ARM ELF spec. version B-01. */ +#define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK. */ +#define EF_ARM_DYNSYMSUSESEGIDX 0x08 /* NB conflicts with EF_APCS26. */ +#define EF_ARM_MAPSYMSFIRST 0x10 /* NB conflicts with EF_APCS_FLOAT. */ +#define EF_ARM_EABIMASK 0xFF000000 + +/* Constants defined in AAELF. */ +#define EF_ARM_BE8 0x00800000 +#define EF_ARM_LE8 0x00400000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 +#define EF_ARM_EABI_VER3 0x03000000 +#define EF_ARM_EABI_VER4 0x04000000 +#define EF_ARM_EABI_VER5 0x05000000 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_ARM_INTERWORK +#define F_APCS26 EF_ARM_APCS_26 +#define F_APCS_FLOAT EF_ARM_APCS_FLOAT +#define F_PIC EF_ARM_PIC +#define F_SOFT_FLOAT EF_ARM_SOFT_FLOAT +#define F_VFP_FLOAT EF_ARM_VFP_FLOAT + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* Additional section types. */ +#define SHT_ARM_EXIDX 0x70000001 /* Section holds ARM unwind info. */ +#define SHT_ARM_PREEMPTMAP 0x70000002 /* Section pre-emption details. */ +#define SHT_ARM_ATTRIBUTES 0x70000003 /* Section holds attributes. */ +#define SHT_ARM_DEBUGOVERLAY 0x70000004 /* Section holds overlay debug info. */ +#define SHT_ARM_OVERLAYSECTION 0x70000005 /* Section holds GDB and overlay integration info. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ +#define PF_ARM_PI 0x20000000 /* Segment is position-independent. */ +#define PF_ARM_ABS 0x40000000 /* Segment must be loaded at its base address. */ + +/* Values for the Tag_CPU_arch EABI attribute. */ +#define TAG_CPU_ARCH_PRE_V4 0 +#define TAG_CPU_ARCH_V4 1 +#define TAG_CPU_ARCH_V4T 2 +#define TAG_CPU_ARCH_V5T 3 +#define TAG_CPU_ARCH_V5TE 4 +#define TAG_CPU_ARCH_V5TEJ 5 +#define TAG_CPU_ARCH_V6 6 +#define TAG_CPU_ARCH_V6KZ 7 +#define TAG_CPU_ARCH_V6T2 8 +#define TAG_CPU_ARCH_V6K 9 +#define TAG_CPU_ARCH_V7 10 +#define TAG_CPU_ARCH_V6_M 11 +#define TAG_CPU_ARCH_V6S_M 12 +#define TAG_CPU_ARCH_V7E_M 13 +#define MAX_TAG_CPU_ARCH 13 +/* Pseudo-architecture to allow objects to be compatible with the subset of + armv4t and armv6-m. This value should never be stored in object files. */ +#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1) + +/* Relocation types. */ + +START_RELOC_NUMBERS (elf_arm_reloc_type) +/* AAELF official names and numbers. */ + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) /* deprecated */ + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) + RELOC_NUMBER (R_ARM_LDR_PC_G0, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_CALL, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_BREL_ADJ, 12) + RELOC_NUMBER (R_ARM_TLS_DESC, 13) + RELOC_NUMBER (R_ARM_THM_SWI8, 14) /* obsolete */ + RELOC_NUMBER (R_ARM_XPC25, 15) /* obsolete */ + RELOC_NUMBER (R_ARM_THM_XPC22, 16) /* obsolete */ + RELOC_NUMBER (R_ARM_TLS_DTPMOD32, 17) + RELOC_NUMBER (R_ARM_TLS_DTPOFF32, 18) + RELOC_NUMBER (R_ARM_TLS_TPOFF32, 19) + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF32, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_BASE_PREL, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT_BREL, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* deprecated - 32 bit PLT address. */ + RELOC_NUMBER (R_ARM_CALL, 28) + RELOC_NUMBER (R_ARM_JUMP24, 29) + RELOC_NUMBER (R_ARM_THM_JUMP24, 30) + RELOC_NUMBER (R_ARM_BASE_ABS, 31) + RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32) /* obsolete */ + RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33) /* obsolete */ + RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34) /* obsolete */ + RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35) /* deprecated, should have _NC suffix */ + RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36) /* deprecated, should have _NC suffix */ + RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37) /* deprecated, should have _CK suffix */ + RELOC_NUMBER (R_ARM_TARGET1, 38) + RELOC_NUMBER (R_ARM_SBREL31, 39) /* deprecated */ + RELOC_NUMBER (R_ARM_V4BX, 40) + RELOC_NUMBER (R_ARM_TARGET2, 41) + RELOC_NUMBER (R_ARM_PREL31, 42) + RELOC_NUMBER (R_ARM_MOVW_ABS_NC, 43) + RELOC_NUMBER (R_ARM_MOVT_ABS, 44) + RELOC_NUMBER (R_ARM_MOVW_PREL_NC, 45) + RELOC_NUMBER (R_ARM_MOVT_PREL, 46) + RELOC_NUMBER (R_ARM_THM_MOVW_ABS_NC, 47) + RELOC_NUMBER (R_ARM_THM_MOVT_ABS, 48) + RELOC_NUMBER (R_ARM_THM_MOVW_PREL_NC, 49) + RELOC_NUMBER (R_ARM_THM_MOVT_PREL, 50) + RELOC_NUMBER (R_ARM_THM_JUMP19, 51) + RELOC_NUMBER (R_ARM_THM_JUMP6, 52) + RELOC_NUMBER (R_ARM_THM_ALU_PREL_11_0, 53) + RELOC_NUMBER (R_ARM_THM_PC12, 54) + RELOC_NUMBER (R_ARM_ABS32_NOI, 55) + RELOC_NUMBER (R_ARM_REL32_NOI, 56) + RELOC_NUMBER (R_ARM_ALU_PC_G0_NC, 57) + RELOC_NUMBER (R_ARM_ALU_PC_G0, 58) + RELOC_NUMBER (R_ARM_ALU_PC_G1_NC, 59) + RELOC_NUMBER (R_ARM_ALU_PC_G1, 60) + RELOC_NUMBER (R_ARM_ALU_PC_G2, 61) + RELOC_NUMBER (R_ARM_LDR_PC_G1, 62) + RELOC_NUMBER (R_ARM_LDR_PC_G2, 63) + RELOC_NUMBER (R_ARM_LDRS_PC_G0, 64) + RELOC_NUMBER (R_ARM_LDRS_PC_G1, 65) + RELOC_NUMBER (R_ARM_LDRS_PC_G2, 66) + RELOC_NUMBER (R_ARM_LDC_PC_G0, 67) + RELOC_NUMBER (R_ARM_LDC_PC_G1, 68) + RELOC_NUMBER (R_ARM_LDC_PC_G2, 69) + RELOC_NUMBER (R_ARM_ALU_SB_G0_NC, 70) + RELOC_NUMBER (R_ARM_ALU_SB_G0, 71) + RELOC_NUMBER (R_ARM_ALU_SB_G1_NC, 72) + RELOC_NUMBER (R_ARM_ALU_SB_G1, 73) + RELOC_NUMBER (R_ARM_ALU_SB_G2, 74) + RELOC_NUMBER (R_ARM_LDR_SB_G0, 75) + RELOC_NUMBER (R_ARM_LDR_SB_G1, 76) + RELOC_NUMBER (R_ARM_LDR_SB_G2, 77) + RELOC_NUMBER (R_ARM_LDRS_SB_G0, 78) + RELOC_NUMBER (R_ARM_LDRS_SB_G1, 79) + RELOC_NUMBER (R_ARM_LDRS_SB_G2, 80) + RELOC_NUMBER (R_ARM_LDC_SB_G0, 81) + RELOC_NUMBER (R_ARM_LDC_SB_G1, 82) + RELOC_NUMBER (R_ARM_LDC_SB_G2, 83) + RELOC_NUMBER (R_ARM_MOVW_BREL_NC, 84) + RELOC_NUMBER (R_ARM_MOVT_BREL, 85) + RELOC_NUMBER (R_ARM_MOVW_BREL, 86) + RELOC_NUMBER (R_ARM_THM_MOVW_BREL_NC, 87) + RELOC_NUMBER (R_ARM_THM_MOVT_BREL, 88) + RELOC_NUMBER (R_ARM_THM_MOVW_BREL, 89) + RELOC_NUMBER (R_ARM_TLS_GOTDESC, 90) + RELOC_NUMBER (R_ARM_TLS_CALL, 91) + RELOC_NUMBER (R_ARM_TLS_DESCSEQ, 92) + RELOC_NUMBER (R_ARM_THM_TLS_CALL, 93) + RELOC_NUMBER (R_ARM_PLT32_ABS, 94) + RELOC_NUMBER (R_ARM_GOT_ABS, 95) + RELOC_NUMBER (R_ARM_GOT_PREL, 96) + RELOC_NUMBER (R_ARM_GOT_BREL12, 97) + RELOC_NUMBER (R_ARM_GOTOFF12, 98) + RELOC_NUMBER (R_ARM_GOTRELAX, 99) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) /* deprecated - old C++ abi */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) /* deprecated - old C++ abi */ + RELOC_NUMBER (R_ARM_THM_JUMP11, 102) + RELOC_NUMBER (R_ARM_THM_JUMP8, 103) + RELOC_NUMBER (R_ARM_TLS_GD32, 104) + RELOC_NUMBER (R_ARM_TLS_LDM32, 105) + RELOC_NUMBER (R_ARM_TLS_LDO32, 106) + RELOC_NUMBER (R_ARM_TLS_IE32, 107) + RELOC_NUMBER (R_ARM_TLS_LE32, 108) + RELOC_NUMBER (R_ARM_TLS_LDO12, 109) + RELOC_NUMBER (R_ARM_TLS_LE12, 110) + RELOC_NUMBER (R_ARM_TLS_IE12GP, 111) + /* 112 - 127 private range */ + RELOC_NUMBER (R_ARM_ME_TOO, 128) /* obsolete */ + RELOC_NUMBER (R_ARM_THM_TLS_DESCSEQ ,129) + + RELOC_NUMBER (R_ARM_IRELATIVE, 160) + + /* Extensions? R=read-only? */ + RELOC_NUMBER (R_ARM_RXPC25, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) + + /* Unofficial names for some of the relocs. */ + FAKE_RELOC (R_ARM_GOTOFF, R_ARM_GOTOFF32) /* 32 bit offset to GOT. */ + FAKE_RELOC (R_ARM_THM_PC22, R_ARM_THM_CALL) + FAKE_RELOC (R_ARM_THM_PC11, R_ARM_THM_JUMP11) + FAKE_RELOC (R_ARM_THM_PC9, R_ARM_THM_JUMP8) + + /* Relocs with both a different name, and (apparently) different meaning in + GNU usage. */ + FAKE_RELOC (R_ARM_GOTPC, R_ARM_BASE_PREL) /* 32 bit PC relative offset to GOT. */ + FAKE_RELOC (R_ARM_GOT32, R_ARM_GOT_BREL) /* 32 bit GOT entry. */ + FAKE_RELOC (R_ARM_ROSEGREL32, R_ARM_SBREL31) /* ??? */ + FAKE_RELOC (R_ARM_AMP_VCALL9, R_ARM_BREL_ADJ) /* Thumb-something. Not used. */ + +END_RELOC_NUMBERS (R_ARM_max = 256) + +#ifdef BFD_ARCH_SIZE +/* EABI object attributes. */ + +enum +{ + /* 0-3 are generic. */ + Tag_CPU_raw_name = 4, + Tag_CPU_name, + Tag_CPU_arch, + Tag_CPU_arch_profile, + Tag_ARM_ISA_use, + Tag_THUMB_ISA_use, + Tag_FP_arch, + Tag_WMMX_arch, + Tag_Advanced_SIMD_arch, + Tag_PCS_config, + Tag_ABI_PCS_R9_use, + Tag_ABI_PCS_RW_data, + Tag_ABI_PCS_RO_data, + Tag_ABI_PCS_GOT_use, + Tag_ABI_PCS_wchar_t, + Tag_ABI_FP_rounding, + Tag_ABI_FP_denormal, + Tag_ABI_FP_exceptions, + Tag_ABI_FP_user_exceptions, + Tag_ABI_FP_number_model, + Tag_ABI_align_needed, + Tag_ABI_align_preserved, + Tag_ABI_enum_size, + Tag_ABI_HardFP_use, + Tag_ABI_VFP_args, + Tag_ABI_WMMX_args, + Tag_ABI_optimization_goals, + Tag_ABI_FP_optimization_goals, + /* 32 is generic (Tag_compatibility). */ + Tag_undefined33 = 33, + Tag_CPU_unaligned_access, + Tag_undefined35, + Tag_FP_HP_extension, + Tag_undefined37, + Tag_ABI_FP_16bit_format, + Tag_undefined39, + Tag_undefined40, + Tag_undefined41, + Tag_MPextension_use, + Tag_undefined_43, + Tag_DIV_use, + Tag_nodefaults = 64, + Tag_also_compatible_with, + Tag_T2EE_use, + Tag_conformance, + Tag_Virtualization_use, + Tag_undefined69, + Tag_MPextension_use_legacy, + + /* The following tags are legacy names for other tags. */ + Tag_VFP_arch = Tag_FP_arch, + Tag_ABI_align8_needed = Tag_ABI_align_needed, + Tag_ABI_align8_preserved = Tag_ABI_align_preserved, + Tag_VFP_HP_extension = Tag_FP_HP_extension +}; + +#endif + +/* The name of the note section used to identify arm variants. */ +#define ARM_NOTE_SECTION ".note.gnu.arm.ident" + +/* Special section names. */ +#define ELF_STRING_ARM_unwind ".ARM.exidx" +#define ELF_STRING_ARM_unwind_info ".ARM.extab" +#define ELF_STRING_ARM_unwind_once ".gnu.linkonce.armexidx." +#define ELF_STRING_ARM_unwind_info_once ".gnu.linkonce.armextab." + +enum arm_st_branch_type { + ST_BRANCH_TO_ARM, + ST_BRANCH_TO_THUMB, + ST_BRANCH_LONG +}; + +#define ARM_SYM_BRANCH_TYPE(SYM) \ + ((enum arm_st_branch_type) (SYM)->st_target_internal) + +#endif /* _ELF_ARM_H */ diff --git a/external/gpl3/gdb/dist/include/elf/avr.h b/external/gpl3/gdb/dist/include/elf/avr.h new file mode 100644 index 000000000000..11d43f96684f --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/avr.h @@ -0,0 +1,82 @@ +/* AVR ELF support for BFD. + Copyright 1999, 2000, 2004, 2006, 2010 Free Software Foundation, Inc. + Contributed by Denis Chertykov + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_AVR_H +#define _ELF_AVR_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_AVR_MACH 0x7F + +/* If bit #7 is set, it is assumed that the elf file uses local symbols + as reference for the relocations so that linker relaxation is possible. */ +#define EF_AVR_LINKRELAX_PREPARED 0x80 + +#define E_AVR_MACH_AVR1 1 +#define E_AVR_MACH_AVR2 2 +#define E_AVR_MACH_AVR25 25 +#define E_AVR_MACH_AVR3 3 +#define E_AVR_MACH_AVR31 31 +#define E_AVR_MACH_AVR35 35 +#define E_AVR_MACH_AVR4 4 +#define E_AVR_MACH_AVR5 5 +#define E_AVR_MACH_AVR51 51 +#define E_AVR_MACH_AVR6 6 +#define E_AVR_MACH_XMEGA1 101 +#define E_AVR_MACH_XMEGA2 102 +#define E_AVR_MACH_XMEGA3 103 +#define E_AVR_MACH_XMEGA4 104 +#define E_AVR_MACH_XMEGA5 105 +#define E_AVR_MACH_XMEGA6 106 +#define E_AVR_MACH_XMEGA7 107 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_avr_reloc_type) + RELOC_NUMBER (R_AVR_NONE, 0) + RELOC_NUMBER (R_AVR_32, 1) + RELOC_NUMBER (R_AVR_7_PCREL, 2) + RELOC_NUMBER (R_AVR_13_PCREL, 3) + RELOC_NUMBER (R_AVR_16, 4) + RELOC_NUMBER (R_AVR_16_PM, 5) + RELOC_NUMBER (R_AVR_LO8_LDI, 6) + RELOC_NUMBER (R_AVR_HI8_LDI, 7) + RELOC_NUMBER (R_AVR_HH8_LDI, 8) + RELOC_NUMBER (R_AVR_LO8_LDI_NEG, 9) + RELOC_NUMBER (R_AVR_HI8_LDI_NEG, 10) + RELOC_NUMBER (R_AVR_HH8_LDI_NEG, 11) + RELOC_NUMBER (R_AVR_LO8_LDI_PM, 12) + RELOC_NUMBER (R_AVR_HI8_LDI_PM, 13) + RELOC_NUMBER (R_AVR_HH8_LDI_PM, 14) + RELOC_NUMBER (R_AVR_LO8_LDI_PM_NEG, 15) + RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16) + RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17) + RELOC_NUMBER (R_AVR_CALL, 18) + RELOC_NUMBER (R_AVR_LDI, 19) + RELOC_NUMBER (R_AVR_6, 20) + RELOC_NUMBER (R_AVR_6_ADIW, 21) + RELOC_NUMBER (R_AVR_MS8_LDI, 22) + RELOC_NUMBER (R_AVR_MS8_LDI_NEG, 23) + RELOC_NUMBER (R_AVR_LO8_LDI_GS, 24) + RELOC_NUMBER (R_AVR_HI8_LDI_GS, 25) + RELOC_NUMBER (R_AVR_8, 26) +END_RELOC_NUMBERS (R_AVR_max) + +#endif /* _ELF_AVR_H */ diff --git a/external/gpl3/gdb/dist/include/elf/bfin.h b/external/gpl3/gdb/dist/include/elf/bfin.h new file mode 100644 index 000000000000..8d92906aab38 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/bfin.h @@ -0,0 +1,95 @@ +/* Blackfin ELF support for BFD. + Copyright (C) 2005, 2006, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_BFIN_H +#define _ELF_BFIN_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_bfin_reloc_type) + RELOC_NUMBER (R_BFIN_UNUSED0, 0x00) /* relocation type 0 is not defined */ + RELOC_NUMBER (R_BFIN_PCREL5M2, 0x01) /* LSETUP part a */ + RELOC_NUMBER (R_BFIN_UNUSED1, 0x02) /* relocation type 2 is not defined */ + RELOC_NUMBER (R_BFIN_PCREL10, 0x03) /* type 3, 0x00) if cc jump */ + RELOC_NUMBER (R_BFIN_PCREL12_JUMP, 0x04) /* type 4, 0x00) jump */ + RELOC_NUMBER (R_BFIN_RIMM16, 0x05) /* type 0x5, 0x00) rN = */ + RELOC_NUMBER (R_BFIN_LUIMM16, 0x06) /* # 0x6, 0x00) preg.l= Load imm 16 to lower half */ + RELOC_NUMBER (R_BFIN_HUIMM16, 0x07) /* # 0x7, 0x00) preg.h= Load imm 16 to upper half */ + RELOC_NUMBER (R_BFIN_PCREL12_JUMP_S, 0x08) /* # 0x8 jump.s */ + RELOC_NUMBER (R_BFIN_PCREL24_JUMP_X, 0x09) /* # 0x9 jump.x */ + RELOC_NUMBER (R_BFIN_PCREL24, 0x0a) /* # 0xa call , 0x00) not expandable */ + RELOC_NUMBER (R_BFIN_UNUSEDB, 0x0b) /* # 0xb not generated */ + RELOC_NUMBER (R_BFIN_UNUSEDC, 0x0c) /* # 0xc not used */ + RELOC_NUMBER (R_BFIN_PCREL24_JUMP_L, 0x0d) /* 0xd jump.l */ + RELOC_NUMBER (R_BFIN_PCREL24_CALL_X, 0x0e) /* 0xE, 0x00) call.x if is above 24 bit limit call through P1 */ + RELOC_NUMBER (R_BFIN_VAR_EQ_SYMB, 0x0f) /* 0xf, 0x00) linker should treat it same as 0x12 */ + RELOC_NUMBER (R_BFIN_BYTE_DATA, 0x10) /* 0x10, 0x00) .byte var = symbol */ + RELOC_NUMBER (R_BFIN_BYTE2_DATA, 0x11) /* 0x11, 0x00) .byte2 var = symbol */ + RELOC_NUMBER (R_BFIN_BYTE4_DATA, 0x12) /* 0x12, 0x00) .byte4 var = symbol and .var var=symbol */ + RELOC_NUMBER (R_BFIN_PCREL11, 0x13) /* 0x13, 0x00) lsetup part b */ + RELOC_NUMBER (R_BFIN_GOT17M4, 0x14) + RELOC_NUMBER (R_BFIN_GOTHI, 0x15) + RELOC_NUMBER (R_BFIN_GOTLO, 0x16) + RELOC_NUMBER (R_BFIN_FUNCDESC, 0x17) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOT17M4, 0x18) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOTHI, 0x19) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOTLO, 0x1a) + RELOC_NUMBER (R_BFIN_FUNCDESC_VALUE, 0x1b) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFF17M4, 0x1c) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFFHI, 0x1d) + RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFFLO, 0x1e) + RELOC_NUMBER (R_BFIN_GOTOFF17M4, 0x1f) + RELOC_NUMBER (R_BFIN_GOTOFFHI, 0x20) + RELOC_NUMBER (R_BFIN_GOTOFFLO, 0x21) + + RELOC_NUMBER (R_BFIN_PUSH, 0xE0) + RELOC_NUMBER (R_BFIN_CONST, 0xE1) + RELOC_NUMBER (R_BFIN_ADD, 0xE2) + RELOC_NUMBER (R_BFIN_SUB, 0xE3) + RELOC_NUMBER (R_BFIN_MULT, 0xE4) + RELOC_NUMBER (R_BFIN_DIV, 0xE5) + RELOC_NUMBER (R_BFIN_MOD, 0xE6) + RELOC_NUMBER (R_BFIN_LSHIFT, 0xE7) + RELOC_NUMBER (R_BFIN_RSHIFT, 0xE8) + RELOC_NUMBER (R_BFIN_AND, 0xE9) + RELOC_NUMBER (R_BFIN_OR, 0xEA) + RELOC_NUMBER (R_BFIN_XOR, 0xEB) + RELOC_NUMBER (R_BFIN_LAND, 0xEC) + RELOC_NUMBER (R_BFIN_LOR, 0xED) + RELOC_NUMBER (R_BFIN_LEN, 0xEE) + RELOC_NUMBER (R_BFIN_NEG, 0xEF) + RELOC_NUMBER (R_BFIN_COMP, 0xF0) + RELOC_NUMBER (R_BFIN_PAGE, 0xF1) + RELOC_NUMBER (R_BFIN_HWPAGE, 0xF2) + RELOC_NUMBER (R_BFIN_ADDR, 0xF3) + RELOC_NUMBER (R_BFIN_PLTPC, 0x40) /* PLT gnu only relocation */ + RELOC_NUMBER (R_BFIN_GOT, 0x41) /* GOT gnu only relocation */ + RELOC_NUMBER (R_BFIN_GNU_VTINHERIT, 0x42) /* C++, gnu only */ + RELOC_NUMBER (R_BFIN_GNU_VTENTRY, 0x43) /* C++, gnu only */ +END_RELOC_NUMBERS (R_BFIN_max) + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_BFIN_PIC 0x00000001 /* -fpic */ +#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */ + +#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */ +#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */ + +#define EF_BFIN_PIC_FLAGS (EF_BFIN_PIC | EF_BFIN_FDPIC) +#endif /* _ELF_BFIN_H */ diff --git a/external/gpl3/gdb/dist/include/elf/common.h b/external/gpl3/gdb/dist/include/elf/common.h new file mode 100644 index 000000000000..52ce9a51110a --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/common.h @@ -0,0 +1,946 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 + Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of ELF support for BFD, and contains the portions + that are common to both the internal and external representations. + For example, ELFMAG0 is the byte 0x7F in both the internal (in-memory) + and external (in-file) representations. */ + +#ifndef _ELF_COMMON_H +#define _ELF_COMMON_H + +/* Fields in e_ident[]. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7F /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +#define EI_CLASS 4 /* File class */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ + +#define EI_DATA 5 /* Data encoding */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ + +#define EI_VERSION 6 /* File version */ + +#define EI_OSABI 7 /* Operating System/ABI indication */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_HPUX 1 /* HP-UX operating system */ +#define ELFOSABI_NETBSD 2 /* NetBSD */ +#define ELFOSABI_LINUX 3 /* GNU/Linux */ +#define ELFOSABI_HURD 4 /* GNU/Hurd */ +#define ELFOSABI_SOLARIS 6 /* Solaris */ +#define ELFOSABI_AIX 7 /* AIX */ +#define ELFOSABI_IRIX 8 /* IRIX */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD */ +#define ELFOSABI_TRU64 10 /* TRU64 UNIX */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD */ +#define ELFOSABI_OPENVMS 13 /* OpenVMS */ +#define ELFOSABI_NSK 14 /* Hewlett-Packard Non-Stop Kernel */ +#define ELFOSABI_AROS 15 /* AROS */ +#define ELFOSABI_FENIXOS 16 /* FenixOS */ +#define ELFOSABI_C6000_ELFABI 64 /* Bare-metal TMS320C6000 */ +#define ELFOSABI_C6000_LINUX 65 /* Linux TMS320C6000 */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define EI_ABIVERSION 8 /* ABI version */ + +#define EI_PAD 9 /* Start of padding bytes */ + + +/* Values for e_type, which identifies the object file type. */ + +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* Relocatable file */ +#define ET_EXEC 2 /* Executable file */ +#define ET_DYN 3 /* Shared object file */ +#define ET_CORE 4 /* Core file */ +#define ET_LOOS 0xFE00 /* Operating system-specific */ +#define ET_HIOS 0xFEFF /* Operating system-specific */ +#define ET_LOPROC 0xFF00 /* Processor-specific */ +#define ET_HIPROC 0xFFFF /* Processor-specific */ + +/* Values for e_machine, which identifies the architecture. These numbers + are officially assigned by registry@sco.com. See below for a list of + ad-hoc numbers used during initial development. */ + +#define EM_NONE 0 /* No machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola m68k family */ +#define EM_88K 5 /* Motorola m88k family */ +#define EM_486 6 /* Intel 80486 *//* Reserved for future use */ +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian (Oct 4 1999 Draft) Deprecated */ +#define EM_res011 11 /* Reserved */ +#define EM_res012 12 /* Reserved */ +#define EM_res013 13 /* Reserved */ +#define EM_res014 14 /* Reserved */ +#define EM_PARISC 15 /* HPPA */ +#define EM_res016 16 /* Reserved */ +#define EM_VPP550 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ +#define EM_S390 22 /* IBM S/390 */ +#define EM_SPU 23 /* Sony/Toshiba/IBM SPU */ +#define EM_res024 24 /* Reserved */ +#define EM_res025 25 /* Reserved */ +#define EM_res026 26 /* Reserved */ +#define EM_res027 27 /* Reserved */ +#define EM_res028 28 /* Reserved */ +#define EM_res029 29 /* Reserved */ +#define EM_res030 30 /* Reserved */ +#define EM_res031 31 /* Reserved */ +#define EM_res032 32 /* Reserved */ +#define EM_res033 33 /* Reserved */ +#define EM_res034 34 /* Reserved */ +#define EM_res035 35 /* Reserved */ +#define EM_V800 36 /* NEC V800 series */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH32 */ +#define EM_MCORE 39 /* Motorola M*Core */ /* May also be taken by Fujitsu MMA */ +#define EM_RCE 39 /* Old name for MCore */ +#define EM_ARM 40 /* ARM */ +#define EM_OLD_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Renesas (formerly Hitachi) / SuperH SH */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit */ +#define EM_TRICORE 44 /* Siemens Tricore embedded processor */ +#define EM_ARC 45 /* ARC Cores */ +#define EM_H8_300 46 /* Renesas (formerly Hitachi) H8/300 */ +#define EM_H8_300H 47 /* Renesas (formerly Hitachi) H8/300H */ +#define EM_H8S 48 /* Renesas (formerly Hitachi) H8S */ +#define EM_H8_500 49 /* Renesas (formerly Hitachi) H8/500 */ +#define EM_IA_64 50 /* Intel IA-64 Processor */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu Multimedia Accelerator */ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embedded RISC processor */ +#define EM_NDR1 57 /* Denso NDR1 microprocesspr */ +#define EM_STARCORE 58 /* Motorola Star*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ embedded processor */ +#define EM_X86_64 62 /* Advanced Micro Devices X86-64 processor */ +#define EM_PDSP 63 /* Sony DSP Processor */ +#define EM_PDP10 64 /* Digital Equipment Corp. PDP-10 */ +#define EM_PDP11 65 /* Digital Equipment Corp. PDP-11 */ +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 bit microcontroller */ +#define EM_ST7 68 /* STMicroelectronics ST7 8-bit microcontroller */ +#define EM_68HC16 69 /* Motorola MC68HC16 Microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 Microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8-bit cpu */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded cpu */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP processor */ +#define EM_ZSP 79 /* LSI Logic's 16-bit DSP processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard's machine-independent format */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* Renesas V850 (formerly NEC V850) */ +#define EM_M32R 88 /* Renesas M32R (formerly Mitsubishi M32R) */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */ +#define EM_TMM_GPP 96 /* Thompson Multimedia General Purpose Processor */ +#define EM_NS32K 97 /* National Semiconductor 32000 series */ +#define EM_TPC 98 /* Tenor Network TPC processor */ +#define EM_SNP1K 99 /* Trebia SNP 1000 processor */ +#define EM_ST200 100 /* STMicroelectronics ST200 microcontroller */ +#define EM_IP2K 101 /* Ubicom IP2022 micro controller */ +#define EM_MAX 102 /* MAX Processor */ +#define EM_CR 103 /* National Semiconductor CompactRISC */ +#define EM_F2MC16 104 /* Fujitsu F2MC16 */ +#define EM_MSP430 105 /* TI msp430 micro controller */ +#define EM_BLACKFIN 106 /* ADI Blackfin */ +#define EM_SE_C33 107 /* S1C33 Family of Seiko Epson processors */ +#define EM_SEP 108 /* Sharp embedded microprocessor */ +#define EM_ARCA 109 /* Arca RISC Microprocessor */ +#define EM_UNICORE 110 /* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University */ +#define EM_EXCESS 111 /* eXcess: 16/32/64-bit configurable embedded CPU */ +#define EM_DXP 112 /* Icera Semiconductor Inc. Deep Execution Processor */ +#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ +#define EM_CRX 114 /* National Semiconductor CRX */ +#define EM_XGATE 115 /* Motorola XGATE embedded processor */ +#define EM_C166 116 /* Infineon C16x/XC16x processor */ +#define EM_M16C 117 /* Renesas M16C series microprocessors */ +#define EM_DSPIC30F 118 /* Microchip Technology dsPIC30F Digital Signal Controller */ +#define EM_CE 119 /* Freescale Communication Engine RISC core */ +#define EM_M32C 120 /* Renesas M32C series microprocessors */ +#define EM_res121 121 /* Reserved */ +#define EM_res122 122 /* Reserved */ +#define EM_res123 123 /* Reserved */ +#define EM_res124 124 /* Reserved */ +#define EM_res125 125 /* Reserved */ +#define EM_res126 126 /* Reserved */ +#define EM_res127 127 /* Reserved */ +#define EM_res128 128 /* Reserved */ +#define EM_res129 129 /* Reserved */ +#define EM_res130 130 /* Reserved */ +#define EM_TSK3000 131 /* Altium TSK3000 core */ +#define EM_RS08 132 /* Freescale RS08 embedded processor */ +#define EM_res133 133 /* Reserved */ +#define EM_ECOG2 134 /* Cyan Technology eCOG2 microprocessor */ +#define EM_SCORE 135 /* Sunplus Score */ +#define EM_SCORE7 135 /* Sunplus S+core7 RISC processor */ +#define EM_DSP24 136 /* New Japan Radio (NJR) 24-bit DSP Processor */ +#define EM_VIDEOCORE3 137 /* Broadcom VideoCore III processor */ +#define EM_LATTICEMICO32 138 /* RISC processor for Lattice FPGA architecture */ +#define EM_SE_C17 139 /* Seiko Epson C17 family */ +#define EM_TI_C6000 140 /* Texas Instruments TMS320C6000 DSP family */ +#define EM_TI_C2000 141 /* Texas Instruments TMS320C2000 DSP family */ +#define EM_TI_C5500 142 /* Texas Instruments TMS320C55x DSP family */ +#define EM_res143 143 /* Reserved */ +#define EM_res144 144 /* Reserved */ +#define EM_res145 145 /* Reserved */ +#define EM_res146 146 /* Reserved */ +#define EM_res147 147 /* Reserved */ +#define EM_res148 148 /* Reserved */ +#define EM_res149 149 /* Reserved */ +#define EM_res150 150 /* Reserved */ +#define EM_res151 151 /* Reserved */ +#define EM_res152 152 /* Reserved */ +#define EM_res153 153 /* Reserved */ +#define EM_res154 154 /* Reserved */ +#define EM_res155 155 /* Reserved */ +#define EM_res156 156 /* Reserved */ +#define EM_res157 157 /* Reserved */ +#define EM_res158 158 /* Reserved */ +#define EM_res159 159 /* Reserved */ +#define EM_MMDSP_PLUS 160 /* STMicroelectronics 64bit VLIW Data Signal Processor */ +#define EM_CYPRESS_M8C 161 /* Cypress M8C microprocessor */ +#define EM_R32C 162 /* Renesas R32C series microprocessors */ +#define EM_TRIMEDIA 163 /* NXP Semiconductors TriMedia architecture family */ +#define EM_QDSP6 164 /* QUALCOMM DSP6 Processor */ +#define EM_8051 165 /* Intel 8051 and variants */ +#define EM_STXP7X 166 /* STMicroelectronics STxP7x family */ +#define EM_NDS32 167 /* Andes Technology compact code size embedded RISC processor family */ +#define EM_ECOG1 168 /* Cyan Technology eCOG1X family */ +#define EM_ECOG1X 168 /* Cyan Technology eCOG1X family */ +#define EM_MAXQ30 169 /* Dallas Semiconductor MAXQ30 Core Micro-controllers */ +#define EM_XIMO16 170 /* New Japan Radio (NJR) 16-bit DSP Processor */ +#define EM_MANIK 171 /* M2000 Reconfigurable RISC Microprocessor */ +#define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */ +#define EM_RX 173 /* Renesas RX family */ +#define EM_METAG 174 /* Imagination Technologies META processor architecture */ +#define EM_MCST_ELBRUS 175 /* MCST Elbrus general purpose hardware architecture */ +#define EM_ECOG16 176 /* Cyan Technology eCOG16 family */ +#define EM_CR16 177 /* National Semiconductor CompactRISC 16-bit processor */ +#define EM_ETPU 178 /* Freescale Extended Time Processing Unit */ +#define EM_SLE9X 179 /* Infineon Technologies SLE9X core */ +#define EM_L1OM 180 /* Intel L1OM */ +#define EM_INTEL181 181 /* Reserved by Intel */ +#define EM_INTEL182 182 /* Reserved by Intel */ +#define EM_res183 183 /* Reserved by ARM */ +#define EM_res184 184 /* Reserved by ARM */ +#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family */ +#define EM_STM8 186 /* STMicroeletronics STM8 8-bit microcontroller */ +#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */ +#define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */ +#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ +#define EM_CUDA 190 /* NVIDIA CUDA architecture */ + +/* If it is necessary to assign new unofficial EM_* values, please pick large + random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision + with official or non-GNU unofficial values. + + NOTE: Do not just increment the most recent number by one. + Somebody else somewhere will do exactly the same thing, and you + will have a collision. Instead, pick a random number. + + Normally, each entity or maintainer responsible for a machine with an + unofficial e_machine number should eventually ask registry@sco.com for + an officially blessed number to be added to the list above. */ + +/* Old version of Sparc v9, from before the ABI; + This should be removed shortly. */ +#define EM_OLD_SPARCV9 11 + +/* Old version of PowerPC, this should be removed shortly. */ +#define EM_PPC_OLD 17 + +/* picoJava */ +#define EM_PJ_OLD 99 + +/* Old, unofficial value for National Semiconductor CompactRISC - CR16 */ +#define EM_CR16_OLD 115 + +/* AVR magic number. Written in the absense of an ABI. */ +#define EM_AVR_OLD 0x1057 + +/* MSP430 magic number. Written in the absense of everything. */ +#define EM_MSP430_OLD 0x1059 + +/* Morpho MT. Written in the absense of an ABI. */ +#define EM_MT 0x2530 + +/* FR30 magic number - no EABI available. */ +#define EM_CYGNUS_FR30 0x3330 + +/* OpenRISC magic number. Written in the absense of an ABI. */ +#define EM_OPENRISC_OLD 0x3426 + +/* DLX magic number. Written in the absense of an ABI. */ +#define EM_DLX 0x5aa5 + +/* FRV magic number - no EABI available??. */ +#define EM_CYGNUS_FRV 0x5441 + +/* Infineon Technologies 16-bit microcontroller with C166-V2 core. */ +#define EM_XC16X 0x4688 + +/* D10V backend magic number. Written in the absence of an ABI. */ +#define EM_CYGNUS_D10V 0x7650 + +/* D30V backend magic number. Written in the absence of an ABI. */ +#define EM_CYGNUS_D30V 0x7676 + +/* Ubicom IP2xxx; Written in the absense of an ABI. */ +#define EM_IP2K_OLD 0x8217 + +/* (Deprecated) Temporary number for the OpenRISC processor. */ +#define EM_OR32 0x8472 + +/* Cygnus PowerPC ELF backend. Written in the absence of an ABI. */ +#define EM_CYGNUS_POWERPC 0x9025 + +/* Alpha backend magic number. Written in the absence of an ABI. */ +#define EM_ALPHA 0x9026 + +/* Cygnus M32R ELF backend. Written in the absence of an ABI. */ +#define EM_CYGNUS_M32R 0x9041 + +/* V850 backend magic number. Written in the absense of an ABI. */ +#define EM_CYGNUS_V850 0x9080 + +/* old S/390 backend magic number. Written in the absence of an ABI. */ +#define EM_S390_OLD 0xa390 + +/* Old, unofficial value for Xtensa. */ +#define EM_XTENSA_OLD 0xabc7 + +#define EM_XSTORMY16 0xad45 + +/* mn10200 and mn10300 backend magic numbers. + Written in the absense of an ABI. */ +#define EM_CYGNUS_MN10300 0xbeef +#define EM_CYGNUS_MN10200 0xdead + +/* Renesas M32C and M16C. */ +#define EM_M32C_OLD 0xFEB0 + +/* Vitesse IQ2000. */ +#define EM_IQ2000 0xFEBA + +/* NIOS magic number - no EABI available. */ +#define EM_NIOS32 0xFEBB + +#define EM_CYGNUS_MEP 0xF00D /* Toshiba MeP */ + +#define EM_MOXIE 0xFEED /* Moxie */ + +/* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI. */ +#define EM_SCORE_OLD 95 + +#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */ + +/* See the above comment before you add a new EM_* value here. */ + +/* Values for e_version. */ + +#define EV_NONE 0 /* Invalid ELF version */ +#define EV_CURRENT 1 /* Current version */ + +/* Value for e_phnum. */ +#define PN_XNUM 0xffff /* Extended numbering */ + +/* Values for program header, p_type field. */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved, unspecified semantics */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_TLS 7 /* Thread local storage segment */ +#define PT_LOOS 0x60000000 /* OS-specific */ +#define PT_HIOS 0x6fffffff /* OS-specific */ +#define PT_LOPROC 0x70000000 /* Processor-specific */ +#define PT_HIPROC 0x7FFFFFFF /* Processor-specific */ + +#define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550) /* Frame unwind information */ +#define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME /* Solaris uses the same value */ +#define PT_GNU_STACK (PT_LOOS + 0x474e551) /* Stack flags */ +#define PT_GNU_RELRO (PT_LOOS + 0x474e552) /* Read-only after relocation */ + +/* Program segment permissions, in program header p_flags field. */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +/* #define PF_MASKOS 0x0F000000 *//* OS-specific reserved bits */ +#define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ +#define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ + +/* Values for section header, sh_type field. */ + +#define SHT_NULL 0 /* Section header table entry unused */ +#define SHT_PROGBITS 1 /* Program specific (private) data */ +#define SHT_SYMTAB 2 /* Link editing symbol table */ +#define SHT_STRTAB 3 /* A string table */ +#define SHT_RELA 4 /* Relocation entries with addends */ +#define SHT_HASH 5 /* A symbol hash table */ +#define SHT_DYNAMIC 6 /* Information for dynamic linking */ +#define SHT_NOTE 7 /* Information that marks file */ +#define SHT_NOBITS 8 /* Section occupies no space in file */ +#define SHT_REL 9 /* Relocation entries, no addends */ +#define SHT_SHLIB 10 /* Reserved, unspecified semantics */ +#define SHT_DYNSYM 11 /* Dynamic linking symbol table */ + +#define SHT_INIT_ARRAY 14 /* Array of ptrs to init functions */ +#define SHT_FINI_ARRAY 15 /* Array of ptrs to finish functions */ +#define SHT_PREINIT_ARRAY 16 /* Array of ptrs to pre-init funcs */ +#define SHT_GROUP 17 /* Section contains a section group */ +#define SHT_SYMTAB_SHNDX 18 /* Indicies for SHN_XINDEX entries */ + +#define SHT_LOOS 0x60000000 /* First of OS specific semantics */ +#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */ + +#define SHT_GNU_INCREMENTAL_INPUTS 0x6fff4700 /* incremental build data */ +#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes */ +#define SHT_GNU_HASH 0x6ffffff6 /* GNU style symbol hash table */ +#define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */ + +/* The next three section types are defined by Solaris, and are named + SHT_SUNW*. We use them in GNU code, so we also define SHT_GNU* + versions. */ +#define SHT_SUNW_verdef 0x6ffffffd /* Versions defined by file */ +#define SHT_SUNW_verneed 0x6ffffffe /* Versions needed by file */ +#define SHT_SUNW_versym 0x6fffffff /* Symbol versions */ + +#define SHT_GNU_verdef SHT_SUNW_verdef +#define SHT_GNU_verneed SHT_SUNW_verneed +#define SHT_GNU_versym SHT_SUNW_versym + +#define SHT_LOPROC 0x70000000 /* Processor-specific semantics, lo */ +#define SHT_HIPROC 0x7FFFFFFF /* Processor-specific semantics, hi */ +#define SHT_LOUSER 0x80000000 /* Application-specific semantics */ +/* #define SHT_HIUSER 0x8FFFFFFF *//* Application-specific semantics */ +#define SHT_HIUSER 0xFFFFFFFF /* New value, defined in Oct 4, 1999 Draft */ + +/* Values for section header, sh_flags field. */ + +#define SHF_WRITE (1 << 0) /* Writable data during execution */ +#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ +#define SHF_EXECINSTR (1 << 2) /* Executable machine instructions */ +#define SHF_MERGE (1 << 4) /* Data in this section can be merged */ +#define SHF_STRINGS (1 << 5) /* Contains null terminated character strings */ +#define SHF_INFO_LINK (1 << 6) /* sh_info holds section header table index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve section ordering when linking */ +#define SHF_OS_NONCONFORMING (1 << 8) /* OS specific processing required */ +#define SHF_GROUP (1 << 9) /* Member of a section group */ +#define SHF_TLS (1 << 10) /* Thread local storage section */ + +/* #define SHF_MASKOS 0x0F000000 *//* OS-specific semantics */ +#define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ +#define SHF_MASKPROC 0xF0000000 /* Processor-specific semantics */ + +/* This used to be implemented as a processor specific section flag. + We just make it generic. */ +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude + this section from executable + and shared library that it + builds when those objects + are not to be further + relocated. */ + +/* Values of note segment descriptor types for core files. */ + +#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ +#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task struct */ +#define NT_AUXV 6 /* Contains copy of Elfxx_auxv_t */ +#define NT_PRXFPREG 0x46e62b7f /* Contains a user_xfpregs_struct; */ + /* note name must be "LINUX". */ +#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ + /* note name must be "LINUX". */ +#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ + /* note name must be "LINUX". */ +#define NT_X86_XSTATE 0x202 /* x86 XSAVE extended state */ + /* note name must be "LINUX". */ +#define NT_S390_HIGH_GPRS 0x300 /* S/390 upper halves of GPRs */ + /* note name must be "LINUX". */ +#define NT_S390_TIMER 0x301 /* S390 timer */ + /* note name must be "LINUX". */ +#define NT_S390_TODCMP 0x302 /* S390 TOD clock comparator */ + /* note name must be "LINUX". */ +#define NT_S390_TODPREG 0x303 /* S390 TOD programmable register */ + /* note name must be "LINUX". */ +#define NT_S390_CTRS 0x304 /* S390 control registers */ + /* note name must be "LINUX". */ +#define NT_S390_PREFIX 0x305 /* S390 prefix register */ + /* note name must be "LINUX". */ + +/* Note segments for core files on dir-style procfs systems. */ + +#define NT_PSTATUS 10 /* Has a struct pstatus */ +#define NT_FPREGS 12 /* Has a struct fpregset */ +#define NT_PSINFO 13 /* Has a struct psinfo */ +#define NT_LWPSTATUS 16 /* Has a struct lwpstatus_t */ +#define NT_LWPSINFO 17 /* Has a struct lwpsinfo_t */ +#define NT_WIN32PSTATUS 18 /* Has a struct win32_pstatus */ + + +/* Note segments for core files on NetBSD systems. Note name + must start with "NetBSD-CORE". */ + +#define NT_NETBSDCORE_PROCINFO 1 /* Has a struct procinfo */ +#define NT_NETBSDCORE_FIRSTMACH 32 /* start of machdep note types */ + + +/* Note segments for core files on OpenBSD systems. Note name is + "OpenBSD". */ + +#define NT_OPENBSD_PROCINFO 10 +#define NT_OPENBSD_AUXV 11 +#define NT_OPENBSD_REGS 20 +#define NT_OPENBSD_FPREGS 21 +#define NT_OPENBSD_XFPREGS 22 +#define NT_OPENBSD_WCOOKIE 23 + + +/* Note segments for core files on SPU systems. Note name + must start with "SPU/". */ + +#define NT_SPU 1 + +/* Values of note segment descriptor types for object files. */ + +#define NT_VERSION 1 /* Contains a version string. */ +#define NT_ARCH 2 /* Contains an architecture string. */ + +/* Values for notes in non-core files using name "GNU". */ + +#define NT_GNU_ABI_TAG 1 +#define NT_GNU_HWCAP 2 /* Used by ld.so and kernel vDSO. */ +#define NT_GNU_BUILD_ID 3 /* Generated by ld --build-id. */ +#define NT_GNU_GOLD_VERSION 4 /* Generated by gold. */ + +/* Values used in GNU .note.ABI-tag notes (NT_GNU_ABI_TAG). */ +#define GNU_ABI_TAG_LINUX 0 +#define GNU_ABI_TAG_HURD 1 +#define GNU_ABI_TAG_SOLARIS 2 +#define GNU_ABI_TAG_FREEBSD 3 +#define GNU_ABI_TAG_NETBSD 4 + +/* Values for NetBSD .note.netbsd.ident notes. Note name is "NetBSD". */ + +#define NT_NETBSD_IDENT 1 + +/* Values for OpenBSD .note.openbsd.ident notes. Note name is "OpenBSD". */ + +#define NT_OPENBSD_IDENT 1 + +/* Values for FreeBSD .note.ABI-tag notes. Note name is "FreeBSD". */ + +#define NT_FREEBSD_ABI_TAG 1 + +/* These three macros disassemble and assemble a symbol table st_info field, + which contains the symbol binding and symbol type. The STB_ and STT_ + defines identify the binding and type. */ + +#define ELF_ST_BIND(val) (((unsigned int)(val)) >> 4) +#define ELF_ST_TYPE(val) ((val) & 0xF) +#define ELF_ST_INFO(bind,type) (((bind) << 4) + ((type) & 0xF)) + +/* The 64bit and 32bit versions of these macros are identical, but + the ELF spec defines them, so here they are. */ +#define ELF32_ST_BIND ELF_ST_BIND +#define ELF32_ST_TYPE ELF_ST_TYPE +#define ELF32_ST_INFO ELF_ST_INFO +#define ELF64_ST_BIND ELF_ST_BIND +#define ELF64_ST_TYPE ELF_ST_TYPE +#define ELF64_ST_INFO ELF_ST_INFO + +/* This macro disassembles and assembles a symbol's visibility into + the st_other field. The STV_ defines specify the actual visibility. */ + +#define ELF_ST_VISIBILITY(v) ((v) & 0x3) +/* The remaining bits in the st_other field are not currently used. + They should be set to zero. */ + +#define ELF32_ST_VISIBILITY ELF_ST_VISIBILITY +#define ELF64_ST_VISIBILITY ELF_ST_VISIBILITY + + +#define STN_UNDEF 0 /* Undefined symbol index */ + +#define STB_LOCAL 0 /* Symbol not visible outside obj */ +#define STB_GLOBAL 1 /* Symbol visible outside obj */ +#define STB_WEAK 2 /* Like globals, lower precedence */ +#define STB_LOOS 10 /* OS-specific semantics */ +#define STB_GNU_UNIQUE 10 /* Symbol is unique in namespace */ +#define STB_HIOS 12 /* OS-specific semantics */ +#define STB_LOPROC 13 /* Processor-specific semantics */ +#define STB_HIPROC 15 /* Processor-specific semantics */ + +#define STT_NOTYPE 0 /* Symbol type is unspecified */ +#define STT_OBJECT 1 /* Symbol is a data object */ +#define STT_FUNC 2 /* Symbol is a code object */ +#define STT_SECTION 3 /* Symbol associated with a section */ +#define STT_FILE 4 /* Symbol gives a file name */ +#define STT_COMMON 5 /* An uninitialised common block */ +#define STT_TLS 6 /* Thread local data object */ +#define STT_RELC 8 /* Complex relocation expression */ +#define STT_SRELC 9 /* Signed Complex relocation expression */ +#define STT_LOOS 10 /* OS-specific semantics */ +#define STT_GNU_IFUNC 10 /* Symbol is an indirect code object */ +#define STT_HIOS 12 /* OS-specific semantics */ +#define STT_LOPROC 13 /* Processor-specific semantics */ +#define STT_HIPROC 15 /* Processor-specific semantics */ + +/* The following constants control how a symbol may be accessed once it has + become part of an executable or shared library. */ + +#define STV_DEFAULT 0 /* Visibility is specified by binding type */ +#define STV_INTERNAL 1 /* OS specific version of STV_HIDDEN */ +#define STV_HIDDEN 2 /* Can only be seen inside currect component */ +#define STV_PROTECTED 3 /* Treat as STB_LOCAL inside current component */ + +/* Relocation info handling macros. */ + +#define ELF32_R_SYM(i) ((i) >> 8) +#define ELF32_R_TYPE(i) ((i) & 0xff) +#define ELF32_R_INFO(s,t) (((s) << 8) + ((t) & 0xff)) + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) +#define ELF64_R_INFO(s,t) (((bfd_vma) (s) << 31 << 1) + (bfd_vma) (t)) + +/* Dynamic section tags. */ + +#define DT_NULL 0 +#define DT_NEEDED 1 +#define DT_PLTRELSZ 2 +#define DT_PLTGOT 3 +#define DT_HASH 4 +#define DT_STRTAB 5 +#define DT_SYMTAB 6 +#define DT_RELA 7 +#define DT_RELASZ 8 +#define DT_RELAENT 9 +#define DT_STRSZ 10 +#define DT_SYMENT 11 +#define DT_INIT 12 +#define DT_FINI 13 +#define DT_SONAME 14 +#define DT_RPATH 15 +#define DT_SYMBOLIC 16 +#define DT_REL 17 +#define DT_RELSZ 18 +#define DT_RELENT 19 +#define DT_PLTREL 20 +#define DT_DEBUG 21 +#define DT_TEXTREL 22 +#define DT_JMPREL 23 +#define DT_BIND_NOW 24 +#define DT_INIT_ARRAY 25 +#define DT_FINI_ARRAY 26 +#define DT_INIT_ARRAYSZ 27 +#define DT_FINI_ARRAYSZ 28 +#define DT_RUNPATH 29 +#define DT_FLAGS 30 +#define DT_ENCODING 32 +#define DT_PREINIT_ARRAY 32 +#define DT_PREINIT_ARRAYSZ 33 + +/* Note, the Oct 4, 1999 draft of the ELF ABI changed the values + for DT_LOOS and DT_HIOS. Some implementations however, use + values outside of the new range (see below). */ +#define OLD_DT_LOOS 0x60000000 +#define DT_LOOS 0x6000000d +#define DT_HIOS 0x6ffff000 +#define OLD_DT_HIOS 0x6fffffff + +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* The next 2 dynamic tag ranges, integer value range (DT_VALRNGLO to + DT_VALRNGHI) and virtual address range (DT_ADDRRNGLO to DT_ADDRRNGHI), + are used on Solaris. We support them everywhere. Note these values + lie outside of the (new) range for OS specific values. This is a + deliberate special case and we maintain it for backwards compatability. + */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_GNU_PRELINKED 0x6ffffdf5 +#define DT_GNU_CONFLICTSZ 0x6ffffdf6 +#define DT_GNU_LIBLISTSZ 0x6ffffdf7 +#define DT_CHECKSUM 0x6ffffdf8 +#define DT_PLTPADSZ 0x6ffffdf9 +#define DT_MOVEENT 0x6ffffdfa +#define DT_MOVESZ 0x6ffffdfb +#define DT_FEATURE 0x6ffffdfc +#define DT_POSFLAG_1 0x6ffffdfd +#define DT_SYMINSZ 0x6ffffdfe +#define DT_SYMINENT 0x6ffffdff +#define DT_VALRNGHI 0x6ffffdff + +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_HASH 0x6ffffef5 +#define DT_TLSDESC_PLT 0x6ffffef6 +#define DT_TLSDESC_GOT 0x6ffffef7 +#define DT_GNU_CONFLICT 0x6ffffef8 +#define DT_GNU_LIBLIST 0x6ffffef9 +#define DT_CONFIG 0x6ffffefa +#define DT_DEPAUDIT 0x6ffffefb +#define DT_AUDIT 0x6ffffefc +#define DT_PLTPAD 0x6ffffefd +#define DT_MOVETAB 0x6ffffefe +#define DT_SYMINFO 0x6ffffeff +#define DT_ADDRRNGHI 0x6ffffeff + +#define DT_RELACOUNT 0x6ffffff9 +#define DT_RELCOUNT 0x6ffffffa +#define DT_FLAGS_1 0x6ffffffb +#define DT_VERDEF 0x6ffffffc +#define DT_VERDEFNUM 0x6ffffffd +#define DT_VERNEED 0x6ffffffe +#define DT_VERNEEDNUM 0x6fffffff + +/* This tag is a GNU extension to the Solaris version scheme. */ +#define DT_VERSYM 0x6ffffff0 + +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* These section tags are used on Solaris. We support them + everywhere, and hope they do not conflict. */ + +#define DT_AUXILIARY 0x7ffffffd +#define DT_USED 0x7ffffffe +#define DT_FILTER 0x7fffffff + + +/* Values used in DT_FEATURE .dynamic entry. */ +#define DTF_1_PARINIT 0x00000001 +/* From + + http://docs.sun.com:80/ab2/coll.45.13/LLM/@Ab2PageView/21165?Ab2Lang=C&Ab2Enc=iso-8859-1 + + DTF_1_CONFEXP is the same as DTF_1_PARINIT. It is a typo. The value + defined here is the same as the one in on Solaris 8. */ +#define DTF_1_CONFEXP 0x00000002 + +/* Flag values used in the DT_POSFLAG_1 .dynamic entry. */ +#define DF_P1_LAZYLOAD 0x00000001 +#define DF_P1_GROUPPERM 0x00000002 + +/* Flag value in in the DT_FLAGS_1 .dynamic entry. */ +#define DF_1_NOW 0x00000001 +#define DF_1_GLOBAL 0x00000002 +#define DF_1_GROUP 0x00000004 +#define DF_1_NODELETE 0x00000008 +#define DF_1_LOADFLTR 0x00000010 +#define DF_1_INITFIRST 0x00000020 +#define DF_1_NOOPEN 0x00000040 +#define DF_1_ORIGIN 0x00000080 +#define DF_1_DIRECT 0x00000100 +#define DF_1_TRANS 0x00000200 +#define DF_1_INTERPOSE 0x00000400 +#define DF_1_NODEFLIB 0x00000800 +#define DF_1_NODUMP 0x00001000 +#define DF_1_CONLFAT 0x00002000 + +/* Flag values for the DT_FLAGS entry. */ +#define DF_ORIGIN (1 << 0) +#define DF_SYMBOLIC (1 << 1) +#define DF_TEXTREL (1 << 2) +#define DF_BIND_NOW (1 << 3) +#define DF_STATIC_TLS (1 << 4) + +/* These constants are used for the version number of a Elf32_Verdef + structure. */ + +#define VER_DEF_NONE 0 +#define VER_DEF_CURRENT 1 + +/* These constants appear in the vd_flags field of a Elf32_Verdef + structure. + + Cf. the Solaris Linker and Libraries Guide, Ch. 7, Object File Format, + Versioning Sections, for a description: + + http://docs.sun.com/app/docs/doc/819-0690/chapter6-93046?l=en&a=view */ + +#define VER_FLG_BASE 0x1 +#define VER_FLG_WEAK 0x2 +#define VER_FLG_INFO 0x4 + +/* These special constants can be found in an Elf32_Versym field. */ + +#define VER_NDX_LOCAL 0 +#define VER_NDX_GLOBAL 1 + +/* These constants are used for the version number of a Elf32_Verneed + structure. */ + +#define VER_NEED_NONE 0 +#define VER_NEED_CURRENT 1 + +/* This flag appears in a Versym structure. It means that the symbol + is hidden, and is only visible with an explicit version number. + This is a GNU extension. */ + +#define VERSYM_HIDDEN 0x8000 + +/* This is the mask for the rest of the Versym information. */ + +#define VERSYM_VERSION 0x7fff + +/* This is a special token which appears as part of a symbol name. It + indictes that the rest of the name is actually the name of a + version node, and is not part of the actual name. This is a GNU + extension. For example, the symbol name `stat@ver2' is taken to + mean the symbol `stat' in version `ver2'. */ + +#define ELF_VER_CHR '@' + +/* Possible values for si_boundto. */ + +#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ + +/* Possible bitmasks for si_flags. */ + +#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ +#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy loaded */ + +/* Syminfo version values. */ + +#define SYMINFO_NONE 0 +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + +/* Section Group Flags. */ + +#define GRP_COMDAT 0x1 /* A COMDAT group */ + +/* Auxv a_type values. */ + +#define AT_NULL 0 /* End of vector */ +#define AT_IGNORE 1 /* Entry should be ignored */ +#define AT_EXECFD 2 /* File descriptor of program */ +#define AT_PHDR 3 /* Program headers for program */ +#define AT_PHENT 4 /* Size of program header entry */ +#define AT_PHNUM 5 /* Number of program headers */ +#define AT_PAGESZ 6 /* System page size */ +#define AT_BASE 7 /* Base address of interpreter */ +#define AT_FLAGS 8 /* Flags */ +#define AT_ENTRY 9 /* Entry point of program */ +#define AT_NOTELF 10 /* Program is not ELF */ +#define AT_UID 11 /* Real uid */ +#define AT_EUID 12 /* Effective uid */ +#define AT_GID 13 /* Real gid */ +#define AT_EGID 14 /* Effective gid */ +#define AT_CLKTCK 17 /* Frequency of times() */ +#define AT_PLATFORM 15 /* String identifying platform. */ +#define AT_HWCAP 16 /* Machine dependent hints about + processor capabilities. */ +#define AT_FPUCW 18 /* Used FPU control word. */ +#define AT_DCACHEBSIZE 19 /* Data cache block size. */ +#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ +#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ +#define AT_IGNOREPPC 22 /* Entry should be ignored */ +#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ +#define AT_BASE_PLATFORM 24 /* String identifying real platform, + may differ from AT_PLATFORM. */ +#define AT_RANDOM 25 /* Address of 16 random bytes. */ +#define AT_EXECFN 31 /* Filename of executable. */ +/* Pointer to the global system page used for system calls and other + nice things. */ +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 /* Pointer to ELF header of system-supplied DSO. */ + +#define AT_SUN_UID 2000 /* Effective user ID. */ +#define AT_SUN_RUID 2001 /* Real user ID. */ +#define AT_SUN_GID 2002 /* Effective group ID. */ +#define AT_SUN_RGID 2003 /* Real group ID. */ +#define AT_SUN_LDELF 2004 /* Dynamic linker's ELF header. */ +#define AT_SUN_LDSHDR 2005 /* Dynamic linker's section headers. */ +#define AT_SUN_LDNAME 2006 /* String giving name of dynamic linker. */ +#define AT_SUN_LPAGESZ 2007 /* Large pagesize. */ +#define AT_SUN_PLATFORM 2008 /* Platform name string. */ +#define AT_SUN_HWCAP 2009 /* Machine dependent hints about + processor capabilities. */ +#define AT_SUN_IFLUSH 2010 /* Should flush icache? */ +#define AT_SUN_CPU 2011 /* CPU name string. */ +#define AT_SUN_EMUL_ENTRY 2012 /* COFF entry point address. */ +#define AT_SUN_EMUL_EXECFD 2013 /* COFF executable file descriptor. */ +#define AT_SUN_EXECNAME 2014 /* Canonicalized file name given to execve. */ +#define AT_SUN_MMU 2015 /* String for name of MMU module. */ +#define AT_SUN_LDDATA 2016 /* Dynamic linker's data segment address. */ +#define AT_SUN_AUXFLAGS 2017 /* AF_SUN_ flags passed from the kernel. */ + + +#endif /* _ELF_COMMON_H */ diff --git a/external/gpl3/gdb/dist/include/elf/cr16.h b/external/gpl3/gdb/dist/include/elf/cr16.h new file mode 100644 index 000000000000..3278474865ff --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/cr16.h @@ -0,0 +1,62 @@ +/* CR16 ELF support for BFD. + Copyright 2007, 2010 Free Software Foundation, Inc. + Contributed by M R Swami Reddy. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CR16_H +#define _ELF_CR16_H + +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS(elf_cr16_reloc_type) + RELOC_NUMBER (R_CR16_NONE, 0) + RELOC_NUMBER (R_CR16_NUM8, 1) + RELOC_NUMBER (R_CR16_NUM16, 2) + RELOC_NUMBER (R_CR16_NUM32, 3) + RELOC_NUMBER (R_CR16_NUM32a, 4) + RELOC_NUMBER (R_CR16_REGREL4, 5) + RELOC_NUMBER (R_CR16_REGREL4a, 6) + RELOC_NUMBER (R_CR16_REGREL14, 7) + RELOC_NUMBER (R_CR16_REGREL14a, 8) + RELOC_NUMBER (R_CR16_REGREL16, 9) + RELOC_NUMBER (R_CR16_REGREL20, 10) + RELOC_NUMBER (R_CR16_REGREL20a, 11) + RELOC_NUMBER (R_CR16_ABS20, 12) + RELOC_NUMBER (R_CR16_ABS24, 13) + RELOC_NUMBER (R_CR16_IMM4, 14) + RELOC_NUMBER (R_CR16_IMM8, 15) + RELOC_NUMBER (R_CR16_IMM16, 16) + RELOC_NUMBER (R_CR16_IMM20, 17) + RELOC_NUMBER (R_CR16_IMM24, 18) + RELOC_NUMBER (R_CR16_IMM32, 19) + RELOC_NUMBER (R_CR16_IMM32a, 20) + RELOC_NUMBER (R_CR16_DISP4, 21) + RELOC_NUMBER (R_CR16_DISP8, 22) + RELOC_NUMBER (R_CR16_DISP16, 23) + RELOC_NUMBER (R_CR16_DISP24, 24) + RELOC_NUMBER (R_CR16_DISP24a, 25) + RELOC_NUMBER (R_CR16_SWITCH8, 26) + RELOC_NUMBER (R_CR16_SWITCH16, 27) + RELOC_NUMBER (R_CR16_SWITCH32, 28) + RELOC_NUMBER (R_CR16_GOT_REGREL20, 29) + RELOC_NUMBER (R_CR16_GOTC_REGREL20, 30) + RELOC_NUMBER (R_CR16_GLOB_DAT, 31) +END_RELOC_NUMBERS(R_CR16_MAX) + +#endif /* _ELF_CR16_H */ diff --git a/external/gpl3/gdb/dist/include/elf/cr16c.h b/external/gpl3/gdb/dist/include/elf/cr16c.h new file mode 100644 index 000000000000..dbefb0ab615b --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/cr16c.h @@ -0,0 +1,258 @@ +/* CR16C ELF support for BFD. + Copyright 2004, 2008, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CR16C_H +#define _ELF_CR16C_H + +#include "bfd.h" +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS (elf_cr16c_reloc_type) + RELOC_NUMBER (RINDEX_16C_NUM08, 0) + RELOC_NUMBER (RINDEX_16C_NUM08_C, 1) + RELOC_NUMBER (RINDEX_16C_NUM16, 2) + RELOC_NUMBER (RINDEX_16C_NUM16_C, 3) + RELOC_NUMBER (RINDEX_16C_NUM32, 4) + RELOC_NUMBER (RINDEX_16C_NUM32_C, 5) + RELOC_NUMBER (RINDEX_16C_DISP04, 6) + RELOC_NUMBER (RINDEX_16C_DISP04_C, 7) + RELOC_NUMBER (RINDEX_16C_DISP08, 8) + RELOC_NUMBER (RINDEX_16C_DISP08_C, 9) + RELOC_NUMBER (RINDEX_16C_DISP16, 10) + RELOC_NUMBER (RINDEX_16C_DISP16_C, 11) + RELOC_NUMBER (RINDEX_16C_DISP24, 12) + RELOC_NUMBER (RINDEX_16C_DISP24_C, 13) + RELOC_NUMBER (RINDEX_16C_DISP24a, 14) + RELOC_NUMBER (RINDEX_16C_DISP24a_C, 15) + RELOC_NUMBER (RINDEX_16C_REG04, 16) + RELOC_NUMBER (RINDEX_16C_REG04_C, 17) + RELOC_NUMBER (RINDEX_16C_REG04a, 18) + RELOC_NUMBER (RINDEX_16C_REG04a_C, 19) + RELOC_NUMBER (RINDEX_16C_REG14, 20) + RELOC_NUMBER (RINDEX_16C_REG14_C, 21) + RELOC_NUMBER (RINDEX_16C_REG16, 22) + RELOC_NUMBER (RINDEX_16C_REG16_C, 23) + RELOC_NUMBER (RINDEX_16C_REG20, 24) + RELOC_NUMBER (RINDEX_16C_REG20_C, 25) + RELOC_NUMBER (RINDEX_16C_ABS20, 26) + RELOC_NUMBER (RINDEX_16C_ABS20_C, 27) + RELOC_NUMBER (RINDEX_16C_ABS24, 28) + RELOC_NUMBER (RINDEX_16C_ABS24_C, 29) + RELOC_NUMBER (RINDEX_16C_IMM04, 30) + RELOC_NUMBER (RINDEX_16C_IMM04_C, 31) + RELOC_NUMBER (RINDEX_16C_IMM16, 32) + RELOC_NUMBER (RINDEX_16C_IMM16_C, 33) + RELOC_NUMBER (RINDEX_16C_IMM20, 34) + RELOC_NUMBER (RINDEX_16C_IMM20_C, 35) + RELOC_NUMBER (RINDEX_16C_IMM24, 36) + RELOC_NUMBER (RINDEX_16C_IMM24_C, 37) + RELOC_NUMBER (RINDEX_16C_IMM32, 38) + RELOC_NUMBER (RINDEX_16C_IMM32_C, 39) +END_RELOC_NUMBERS (RINDEX_16C_MAX) + +/* CR16C Relocation Types ('cr_reloc_type' entry in the reloc_map structure). + The relocation constant name is determined as follows : + + R_16C_[_C] + + Where : + + is one of the following: + NUM - R_NUMBER mnemonic, + DISP - R_16C_DISPL mnemonic, + REG - R_16C_REGREL mnemonic, + ABS - R_16C_ABS mnemonic, + IMM - R_16C_IMMED mnemonic, + stands for R_S_16C_ + _C means 'code label' and is only added when R_ADDRTYPE subfield + is of type R_CODE_ADDR. */ + +/* The table below shows what the hex digits in the definition of the + relocation type constants correspond to. + ------------------------------------------------------------------ + R_SIZESP R_FORMAT R_RELTO R_ADDRTYPE + ------------------------------------------------------------------ */ +/* R_S_16C_08 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM08 0X0001 + +/* R_S_16C_08 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM08_C 0X0006 + +/* R_S_16C_16 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM16 0X1001 + +/* R_S_16C_16 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM16_C 0X1006 + +/* R_S_16C_32 R_NUMBER R_ABS R_ADDRESS */ +#define R_16C_NUM32 0X2001 + +/* R_S_16C_32 R_NUMBER R_ABS R_CODE_ADDR */ +#define R_16C_NUM32_C 0X2006 + +/* R_S_16C_04 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP04 0X5411 + +/* R_S_16C_04 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP04_C 0X5416 + +/* R_S_16C_08 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP08 0X0411 + +/* R_S_16C_08 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP08_C 0X0416 + +/* R_S_16C_16 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP16 0X1411 + +/* R_S_16C_16 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP16_C 0X1416 + +/* R_S_16C_24 R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP24 0X7411 + +/* R_S_16C_24 R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP24_C 0X7416 + +/* R_S_16C_24a R_16C_DISPL R_PCREL R_ADDRESS */ +#define R_16C_DISP24a 0X6411 + +/* R_S_16C_24a R_16C_DISPL R_PCREL R_CODE_ADDR */ +#define R_16C_DISP24a_C 0X6416 + +/* R_S_16C_04 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG04 0X5201 + +/* R_S_16C_04 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG04_C 0X5206 + +/* R_S_16C_04_a R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG04a 0X4201 + +/* R_S_16C_04_a R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG04a_C 0X4206 + +/* R_S_16C_14 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG14 0X3201 + +/* R_S_16C_14 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG14_C 0X3206 + +/* R_S_16C_16 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG16 0X1201 + +/* R_S_16C_16 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG16_C 0X1206 + +/* R_S_16C_20 R_16C_REGREL R_ABS R_ADDRESS */ +#define R_16C_REG20 0X8201 + +/* R_S_16C_20 R_16C_REGREL R_ABS R_CODE_ADDR */ +#define R_16C_REG20_C 0X8206 + +/* R_S_16C_20 R_16C_ABS R_ABS R_ADDRESS */ +#define R_16C_ABS20 0X8101 + +/* R_S_16C_20 R_16C_ABS R_ABS R_CODE_ADDR */ +#define R_16C_ABS20_C 0X8106 + +/* R_S_16C_24 R_16C_ABS R_ABS R_ADDRESS */ +#define R_16C_ABS24 0X7101 + +/* R_S_16C_24 R_16C_ABS R_ABS R_CODE_ADDR */ +#define R_16C_ABS24_C 0X7106 + +/* R_S_16C_04 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM04 0X5301 + +/* R_S_16C_04 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM04_C 0X5306 + +/* R_S_16C_16 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM16 0X1301 + +/* R_S_16C_16 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM16_C 0X1306 + +/* R_S_16C_20 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM20 0X8301 + +/* R_S_16C_20 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM20_C 0X8306 + +/* R_S_16C_24 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM24 0X7301 + +/* R_S_16C_24 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM24_C 0X7306 + +/* R_S_16C_32 R_16C_IMMED R_ABS R_ADDRESS */ +#define R_16C_IMM32 0X2301 + +/* R_S_16C_32 R_16C_IMMED R_ABS R_CODE_ADDR */ +#define R_16C_IMM32_C 0X2306 + + +/* Relocation item type. */ +#define R_ADDRTYPE 0x000f +#define R_ADDRESS 0x0001 /* Take address of symbol. */ +#define R_CODE_ADDR 0x0006 /* Take address of symbol divided by 2. */ + +/* Relocation action. */ +#define R_RELTO 0x00f0 +#define R_ABS 0x0000 /* Keep symbol's address as such. */ +#define R_PCREL 0x0010 /* Subtract the pc address of hole. */ + +/* Relocation item data format. */ +#define R_FORMAT 0x0f00 +#define R_NUMBER 0x0000 /* Retain as two's complement value. */ +#define R_16C_DISPL 0x0400 /* CR16C displacement type. */ +#define R_16C_ABS 0x0100 /* CR16C absolute type. */ +#define R_16C_REGREL 0x0200 /* CR16C register-relative type. */ +#define R_16C_IMMED 0x0300 /* CR16C immediate type. */ + +/* Relocation item size. */ +#define R_SIZESP 0xf000 +#define R_S_16C_04 0x5000 +#define R_S_16C_04_a 0x4000 +#define R_S_16C_08 0x0000 +#define R_S_16C_14 0x3000 +#define R_S_16C_16 0x1000 +#define R_S_16C_20 0x8000 +#define R_S_16C_24_a 0x6000 +#define R_S_16C_24 0x7000 +#define R_S_16C_32 0x2000 + + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Far common symbol. */ +#define SHN_CR16C_FCOMMON SHN_LORESERVE +#define SHN_CR16C_NCOMMON (SHN_LORESERVE + 1) + +typedef struct reloc_map +{ + unsigned short cr_reloc_type; /* CR relocation type. */ + bfd_reloc_code_real_type bfd_reloc_enum; /* BFD relocation enum. */ +} RELOC_MAP; + +#endif /* _ELF_CR16C_H */ diff --git a/external/gpl3/gdb/dist/include/elf/cris.h b/external/gpl3/gdb/dist/include/elf/cris.h new file mode 100644 index 000000000000..5889a90d0812 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/cris.h @@ -0,0 +1,193 @@ +/* CRIS ELF support for BFD. + Copyright 2000, 2001, 2004, 2010 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CRIS_H +#define _ELF_CRIS_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_cris_reloc_type) + RELOC_NUMBER (R_CRIS_NONE, 0) + RELOC_NUMBER (R_CRIS_8, 1) + RELOC_NUMBER (R_CRIS_16, 2) + RELOC_NUMBER (R_CRIS_32, 3) + + /* The "PC" position is the location right after the relocation. */ + RELOC_NUMBER (R_CRIS_8_PCREL, 4) + RELOC_NUMBER (R_CRIS_16_PCREL, 5) + RELOC_NUMBER (R_CRIS_32_PCREL, 6) + + RELOC_NUMBER (R_CRIS_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_CRIS_GNU_VTENTRY, 8) + + /* Copy contents at dynlinking. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_COPY. */ + RELOC_NUMBER (R_CRIS_COPY, 9) + + /* Create GOT entry. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_GLOB_DAT. */ + RELOC_NUMBER (R_CRIS_GLOB_DAT, 10) + + /* Create PLT entry. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_JUMP_SLOT. */ + RELOC_NUMBER (R_CRIS_JUMP_SLOT, 11) + + /* Adjust by program base. Generated by the linker. + The BFD equivalent is BFD_RELOC_CRIS_RELATIVE. */ + RELOC_NUMBER (R_CRIS_RELATIVE, 12) + + /* A 16-bit offset to entry in GOT and request to create GOT entry for + that symbol. + The BFD equivalent is BFD_RELOC_CRIS_16_GOT. */ + RELOC_NUMBER (R_CRIS_16_GOT, 13) + + /* A 32-bit offset to entry in GOT and request to create GOT entry for + that symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOT. */ + RELOC_NUMBER (R_CRIS_32_GOT, 14) + + /* A 16-bit offset to entry in PLT part of GOT and request to create PLT + entry for that symbol. + The BFD equivalent is BFD_RELOC_CRIS_16_GOTPLT. */ + RELOC_NUMBER (R_CRIS_16_GOTPLT, 15) + + /* A 32-bit offset to entry in PLT part of GOT and request to create PLT + entry for that symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTPLT. */ + RELOC_NUMBER (R_CRIS_32_GOTPLT, 16) + + /* A 32-bit offset from GOT to (local) symbol: no GOT entry should be + necessary. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL. */ + RELOC_NUMBER (R_CRIS_32_GOTREL, 17) + + /* A 32-bit offset from GOT to entry for this symbol in PLT and request + to create PLT entry for symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL. */ + RELOC_NUMBER (R_CRIS_32_PLT_GOTREL, 18) + + /* A 32-bit offset from location after this relocation (addend specifies + offset) to entry for this symbol in PLT and request to create PLT + entry for symbol. + The BFD equivalent is BFD_RELOC_CRIS_32_PLT_PCREL. */ + RELOC_NUMBER (R_CRIS_32_PLT_PCREL, 19) + + /* An assembler-generated-only relocation, instructing the linker to + reserve two GOT slots, carrying the R_CRIS_DTP relocation for the + symbol (pointing to the first slot, the relocation fills in + both). The value is a 32-bit-value, relative to the start of the + GOT. Assembly syntax: "sym:GDGOTREL". */ + RELOC_NUMBER (R_CRIS_32_GOT_GD, 20) + + /* Similar to R_CRIS_32_GOT_GD, but the value is a 16-bit unsigned + number, limiting access to 65536/4 global symbols per module (or + 65536/8 thread variables; loosely speaking G*4+T*8 < 65536, where + T is the number of thread variables and G is the number of other + external global variables and functions). Assembly syntax: + "sym:GDGOTREL16". */ + RELOC_NUMBER (R_CRIS_16_GOT_GD, 21) + + /* Similar to R_CRIS_32_GOT_GD, but the value is the absolute + address of the GOT entry. Disallowed in DSOs created with + -shared. Assembly syntax: "sym:GD". */ + RELOC_NUMBER (R_CRIS_32_GD, 22) + + /* A linker-generated-only relocation, instructing the dynamic + linker to fill in the module ID and module-relative-TLS-block + offset of the symbol in question, used for GOT entries. Note + that this relocation instructs to fill in two 32-bit values. */ + RELOC_NUMBER (R_CRIS_DTP, 23) + + /* An assembler-generated-only relocation, instructing the linker to + reserve the first two GOT slots, and attach the R_CRIS_DTPMOD + relocation(*) for the module to the first slot, the second + containing zero. The value is 32 bits, the offset from the start + of the TLS block of the module to the thread-local symbol + mentioned in the relocation. This relocation must only be applied + to module-local symbols. Assembly syntax: "expr:DTPREL". */ + RELOC_NUMBER (R_CRIS_32_DTPREL, 24) + + /* Similar to R_CRIS_32_DTPREL, but the value is a 16-bit signed + number, limiting the size of thread-variables of the DSO to 32768 + bytes. (Note: matches both model 1 and 2 and allows use of addo.w + as the instruction where this relocation is used.) Assembly + syntax: "expr:DTPREL16". */ + RELOC_NUMBER (R_CRIS_16_DTPREL, 25) + + /* An assembler-generated-only relocation, instructing the linker to + reserve a GOT slot and attach the R_CRIS_32_TPREL relocation for + the symbol in question. The value is 32 bits, which is the + GOT-relative offset of the slot. Assembly syntax: + "sym:TPOFFGOT". */ + RELOC_NUMBER (R_CRIS_32_GOT_TPREL, 26) + + /* Similar to R_CRIS_32_TPREL, but the value is a 16-bit positive + number, limiting the number of thread- and global variables of + the DSO to 32768/4. Assembly syntax: "sym:TPOFFGOT16". */ + RELOC_NUMBER (R_CRIS_16_GOT_TPREL, 27) + + /* An assembler- and linker-generated relocation, instructing to + resolve the symbol in question yielding the TLS offset of the + thread variable, relative to the global TLS block. Not allowed + as input when generating a DSO. Assembly syntax: + "expr:TPOFF". */ + RELOC_NUMBER (R_CRIS_32_TPREL, 28) + + /* Similar to R_CRIS_32_TPREL, but only applicable to executables + compiled with -msmall-tls. Not allowed in a DSO. The value is a + 16-bit signed number, limiting the size of thread-variables of + the executable to 32768 bytes. (Note: being signed makes it match + both model 1 and 2 and allows use of addo.w as the instruction + where this relocation is applied.) Assembly syntax: + "expr:TPOFF16". */ + RELOC_NUMBER (R_CRIS_16_TPREL, 29) + + /* A linker-generated-only relocation, instructing the dynamic + linker to fill in the current module ID, used for GOT entries + (usually the fourth one). */ + RELOC_NUMBER (R_CRIS_DTPMOD, 30) + + /* Similar to R_CRIS_32_GOT_TPREL, but the value is the absolute + address of the GOT entry. Disallowed in DSOs created with + -shared. Assembly syntax: "sym:IE". */ + RELOC_NUMBER (R_CRIS_32_IE, 31) + + /* No other relocs must be visible outside the assembler. */ + +END_RELOC_NUMBERS (R_CRIS_max) + +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +/* This is a mask for different incompatible machine variants. */ +#define EF_CRIS_VARIANT_MASK 0x0000000e + +/* Variant 0; may contain v0..10 object. */ +#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 + +/* Variant 1; contains v32 object. */ +#define EF_CRIS_VARIANT_V32 0x00000002 + +/* Variant 2; contains object compatible with v32 and v10. */ +#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 + +#endif /* _ELF_CRIS_H */ diff --git a/external/gpl3/gdb/dist/include/elf/crx.h b/external/gpl3/gdb/dist/include/elf/crx.h new file mode 100644 index 000000000000..38428f297cee --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/crx.h @@ -0,0 +1,53 @@ +/* CRX ELF support for BFD. + Copyright 2004, 2010 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. + Updates, BFDizing, GNUifying and ELF support by Tomer Levi. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CRX_H +#define _ELF_CRX_H + +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS(elf_crx_reloc_type) + RELOC_NUMBER (R_CRX_NONE, 0) + RELOC_NUMBER (R_CRX_REL4, 1) + RELOC_NUMBER (R_CRX_REL8, 2) + RELOC_NUMBER (R_CRX_REL8_CMP, 3) + RELOC_NUMBER (R_CRX_REL16, 4) + RELOC_NUMBER (R_CRX_REL24, 5) + RELOC_NUMBER (R_CRX_REL32, 6) + RELOC_NUMBER (R_CRX_REGREL12, 7) + RELOC_NUMBER (R_CRX_REGREL22, 8) + RELOC_NUMBER (R_CRX_REGREL28, 9) + RELOC_NUMBER (R_CRX_REGREL32, 10) + RELOC_NUMBER (R_CRX_ABS16, 11) + RELOC_NUMBER (R_CRX_ABS32, 12) + RELOC_NUMBER (R_CRX_NUM8, 13) + RELOC_NUMBER (R_CRX_NUM16, 14) + RELOC_NUMBER (R_CRX_NUM32, 15) + RELOC_NUMBER (R_CRX_IMM16, 16) + RELOC_NUMBER (R_CRX_IMM32, 17) + RELOC_NUMBER (R_CRX_SWITCH8, 18) + RELOC_NUMBER (R_CRX_SWITCH16, 19) + RELOC_NUMBER (R_CRX_SWITCH32, 20) +END_RELOC_NUMBERS(R_CRX_MAX) + +#endif /* _ELF_CRX_H */ diff --git a/external/gpl3/gdb/dist/include/elf/d10v.h b/external/gpl3/gdb/dist/include/elf/d10v.h new file mode 100644 index 000000000000..5850b3740ad8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/d10v.h @@ -0,0 +1,38 @@ +/* d10v ELF support for BFD. + Copyright 1998, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_D10V_H +#define _ELF_D10V_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_d10v_reloc_type) + RELOC_NUMBER (R_D10V_NONE, 0) + RELOC_NUMBER (R_D10V_10_PCREL_R, 1) + RELOC_NUMBER (R_D10V_10_PCREL_L, 2) + RELOC_NUMBER (R_D10V_16, 3) + RELOC_NUMBER (R_D10V_18, 4) + RELOC_NUMBER (R_D10V_18_PCREL, 5) + RELOC_NUMBER (R_D10V_32, 6) + RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8) +END_RELOC_NUMBERS (R_D10V_max) + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/d30v.h b/external/gpl3/gdb/dist/include/elf/d30v.h new file mode 100644 index 000000000000..8174a40e0a8b --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/d30v.h @@ -0,0 +1,42 @@ +/* d30v ELF support for BFD. + Copyright 1998, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_D30V_H +#define _ELF_D30V_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_d30v_reloc_type) + RELOC_NUMBER (R_D30V_NONE, 0) + RELOC_NUMBER (R_D30V_6, 1) + RELOC_NUMBER (R_D30V_9_PCREL, 2) + RELOC_NUMBER (R_D30V_9_PCREL_R, 3) + RELOC_NUMBER (R_D30V_15, 4) + RELOC_NUMBER (R_D30V_15_PCREL, 5) + RELOC_NUMBER (R_D30V_15_PCREL_R, 6) + RELOC_NUMBER (R_D30V_21, 7) + RELOC_NUMBER (R_D30V_21_PCREL, 8) + RELOC_NUMBER (R_D30V_21_PCREL_R, 9) + RELOC_NUMBER (R_D30V_32, 10) + RELOC_NUMBER (R_D30V_32_PCREL, 11) + RELOC_NUMBER (R_D30V_32_NORMAL, 12) +END_RELOC_NUMBERS (R_D30V_max) + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/dlx.h b/external/gpl3/gdb/dist/include/elf/dlx.h new file mode 100644 index 000000000000..7d61633c2b96 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/dlx.h @@ -0,0 +1,53 @@ +/* DLX support for BFD. + Copyright 2002, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_DLX_H +#define _ELF_DLX_H + +#include "elf/reloc-macros.h" + +#if 0 +START_RELOC_NUMBERS (elf_dlx_reloc_type) + RELOC_NUMBER (R_DLX_NONE, 0) + RELOC_NUMBER (R_DLX_RELOC_16, 1) + RELOC_NUMBER (R_DLX_RELOC_26, 2) + RELOC_NUMBER (R_DLX_RELOC_32, 3) + RELOC_NUMBER (R_DLX_GNU_VTINHERIT, 4) + RELOC_NUMBER (R_DLX_GNU_VTENTRY, 5) + RELOC_NUMBER (R_DLX_RELOC_16_HI, 6) + RELOC_NUMBER (R_DLX_RELOC_16_LO, 7) + RELOC_NUMBER (R_DLX_RELOC_16_PCREL, 8) + RELOC_NUMBER (R_DLX_RELOC_26_PCREL, 9) +END_RELOC_NUMBERS (R_DLX_max) +#else +START_RELOC_NUMBERS (elf_dlx_reloc_type) + RELOC_NUMBER (R_DLX_NONE, 0) + RELOC_NUMBER (R_DLX_RELOC_8, 1) + RELOC_NUMBER (R_DLX_RELOC_16, 2) + RELOC_NUMBER (R_DLX_RELOC_32, 3) + RELOC_NUMBER (R_DLX_GNU_VTINHERIT, 4) + RELOC_NUMBER (R_DLX_GNU_VTENTRY, 5) + RELOC_NUMBER (R_DLX_RELOC_16_HI, 6) + RELOC_NUMBER (R_DLX_RELOC_16_LO, 7) + RELOC_NUMBER (R_DLX_RELOC_16_PCREL, 8) + RELOC_NUMBER (R_DLX_RELOC_26_PCREL, 9) +END_RELOC_NUMBERS (R_DLX_max) +#endif /* 0 */ + +#endif /* _ELF_DLX_H */ diff --git a/external/gpl3/gdb/dist/include/elf/dwarf.h b/external/gpl3/gdb/dist/include/elf/dwarf.h new file mode 100644 index 000000000000..c2e6a67e866d --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/dwarf.h @@ -0,0 +1,323 @@ +/* Declarations and definitions of codes relating to the DWARF symbolic + debugging information format. + + Written by Ron Guilmette (rfg@netcom.com) + + Copyright 1992, 1993, 1995, 1999, 2005, 2010 Free Software Foundation, Inc. + + This file is part of both GCC and the BFD library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* This file is derived from the DWARF specification (a public document) + Revision 1.0.1 (April 8, 1992) developed by the UNIX International + Programming Languages Special Interest Group (UI/PLSIG) and distributed + by UNIX International. Copies of this specification are available from + UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054. */ + +#ifndef _ELF_DWARF_H +#define _ELF_DWARF_H + +/* Tag names and codes. */ + +enum dwarf_tag { + TAG_padding = 0x0000, + TAG_array_type = 0x0001, + TAG_class_type = 0x0002, + TAG_entry_point = 0x0003, + TAG_enumeration_type = 0x0004, + TAG_formal_parameter = 0x0005, + TAG_global_subroutine = 0x0006, + TAG_global_variable = 0x0007, + /* 0x0008 -- reserved */ + /* 0x0009 -- reserved */ + TAG_label = 0x000a, + TAG_lexical_block = 0x000b, + TAG_local_variable = 0x000c, + TAG_member = 0x000d, + /* 0x000e -- reserved */ + TAG_pointer_type = 0x000f, + TAG_reference_type = 0x0010, + TAG_compile_unit = 0x0011, + TAG_string_type = 0x0012, + TAG_structure_type = 0x0013, + TAG_subroutine = 0x0014, + TAG_subroutine_type = 0x0015, + TAG_typedef = 0x0016, + TAG_union_type = 0x0017, + TAG_unspecified_parameters = 0x0018, + TAG_variant = 0x0019, + TAG_common_block = 0x001a, + TAG_common_inclusion = 0x001b, + TAG_inheritance = 0x001c, + TAG_inlined_subroutine = 0x001d, + TAG_module = 0x001e, + TAG_ptr_to_member_type = 0x001f, + TAG_set_type = 0x0020, + TAG_subrange_type = 0x0021, + TAG_with_stmt = 0x0022, + + /* GNU extensions */ + + TAG_format_label = 0x8000, /* for FORTRAN 77 and Fortran 90 */ + TAG_namelist = 0x8001, /* For Fortran 90 */ + TAG_function_template = 0x8002, /* for C++ */ + TAG_class_template = 0x8003 /* for C++ */ +}; + +#define TAG_lo_user 0x8000 /* implementation-defined range start */ +#define TAG_hi_user 0xffff /* implementation-defined range end */ +#define TAG_source_file TAG_compile_unit /* for backward compatibility */ + +/* Form names and codes. */ + +enum dwarf_form { + FORM_ADDR = 0x1, + FORM_REF = 0x2, + FORM_BLOCK2 = 0x3, + FORM_BLOCK4 = 0x4, + FORM_DATA2 = 0x5, + FORM_DATA4 = 0x6, + FORM_DATA8 = 0x7, + FORM_STRING = 0x8 +}; + +/* Attribute names and codes. */ + +enum dwarf_attribute { + AT_sibling = (0x0010|FORM_REF), + AT_location = (0x0020|FORM_BLOCK2), + AT_name = (0x0030|FORM_STRING), + AT_fund_type = (0x0050|FORM_DATA2), + AT_mod_fund_type = (0x0060|FORM_BLOCK2), + AT_user_def_type = (0x0070|FORM_REF), + AT_mod_u_d_type = (0x0080|FORM_BLOCK2), + AT_ordering = (0x0090|FORM_DATA2), + AT_subscr_data = (0x00a0|FORM_BLOCK2), + AT_byte_size = (0x00b0|FORM_DATA4), + AT_bit_offset = (0x00c0|FORM_DATA2), + AT_bit_size = (0x00d0|FORM_DATA4), + /* (0x00e0|FORM_xxxx) -- reserved */ + AT_element_list = (0x00f0|FORM_BLOCK4), + AT_stmt_list = (0x0100|FORM_DATA4), + AT_low_pc = (0x0110|FORM_ADDR), + AT_high_pc = (0x0120|FORM_ADDR), + AT_language = (0x0130|FORM_DATA4), + AT_member = (0x0140|FORM_REF), + AT_discr = (0x0150|FORM_REF), + AT_discr_value = (0x0160|FORM_BLOCK2), + /* (0x0170|FORM_xxxx) -- reserved */ + /* (0x0180|FORM_xxxx) -- reserved */ + AT_string_length = (0x0190|FORM_BLOCK2), + AT_common_reference = (0x01a0|FORM_REF), + AT_comp_dir = (0x01b0|FORM_STRING), + AT_const_value_string = (0x01c0|FORM_STRING), + AT_const_value_data2 = (0x01c0|FORM_DATA2), + AT_const_value_data4 = (0x01c0|FORM_DATA4), + AT_const_value_data8 = (0x01c0|FORM_DATA8), + AT_const_value_block2 = (0x01c0|FORM_BLOCK2), + AT_const_value_block4 = (0x01c0|FORM_BLOCK4), + AT_containing_type = (0x01d0|FORM_REF), + AT_default_value_addr = (0x01e0|FORM_ADDR), + AT_default_value_data2 = (0x01e0|FORM_DATA2), + AT_default_value_data4 = (0x01e0|FORM_DATA4), + AT_default_value_data8 = (0x01e0|FORM_DATA8), + AT_default_value_string = (0x01e0|FORM_STRING), + AT_friends = (0x01f0|FORM_BLOCK2), + AT_inline = (0x0200|FORM_STRING), + AT_is_optional = (0x0210|FORM_STRING), + AT_lower_bound_ref = (0x0220|FORM_REF), + AT_lower_bound_data2 = (0x0220|FORM_DATA2), + AT_lower_bound_data4 = (0x0220|FORM_DATA4), + AT_lower_bound_data8 = (0x0220|FORM_DATA8), + AT_private = (0x0240|FORM_STRING), + AT_producer = (0x0250|FORM_STRING), + AT_program = (0x0230|FORM_STRING), + AT_protected = (0x0260|FORM_STRING), + AT_prototyped = (0x0270|FORM_STRING), + AT_public = (0x0280|FORM_STRING), + AT_pure_virtual = (0x0290|FORM_STRING), + AT_return_addr = (0x02a0|FORM_BLOCK2), + AT_abstract_origin = (0x02b0|FORM_REF), + AT_start_scope = (0x02c0|FORM_DATA4), + AT_stride_size = (0x02e0|FORM_DATA4), + AT_upper_bound_ref = (0x02f0|FORM_REF), + AT_upper_bound_data2 = (0x02f0|FORM_DATA2), + AT_upper_bound_data4 = (0x02f0|FORM_DATA4), + AT_upper_bound_data8 = (0x02f0|FORM_DATA8), + AT_virtual = (0x0300|FORM_STRING), + + /* GNU extensions. */ + + AT_sf_names = (0x8000|FORM_DATA4), + AT_src_info = (0x8010|FORM_DATA4), + AT_mac_info = (0x8020|FORM_DATA4), + AT_src_coords = (0x8030|FORM_DATA4), + AT_body_begin = (0x8040|FORM_ADDR), + AT_body_end = (0x8050|FORM_ADDR) +}; + +#define AT_lo_user 0x2000 /* implementation-defined range start */ +#define AT_hi_user 0x3ff0 /* implementation-defined range end */ + +/* Location atom names and codes. */ + +enum dwarf_location_atom { + OP_REG = 0x01, + OP_BASEREG = 0x02, + OP_ADDR = 0x03, + OP_CONST = 0x04, + OP_DEREF2 = 0x05, + OP_DEREF4 = 0x06, + OP_ADD = 0x07, + + /* GNU extensions. */ + + OP_MULT = 0x80 +}; + +#define OP_LO_USER 0x80 /* implementation-defined range start */ +#define OP_HI_USER 0xff /* implementation-defined range end */ + +/* Fundamental type names and codes. */ + +enum dwarf_fundamental_type { + FT_char = 0x0001, + FT_signed_char = 0x0002, + FT_unsigned_char = 0x0003, + FT_short = 0x0004, + FT_signed_short = 0x0005, + FT_unsigned_short = 0x0006, + FT_integer = 0x0007, + FT_signed_integer = 0x0008, + FT_unsigned_integer = 0x0009, + FT_long = 0x000a, + FT_signed_long = 0x000b, + FT_unsigned_long = 0x000c, + FT_pointer = 0x000d, /* an alias for (void *) */ + FT_float = 0x000e, + FT_dbl_prec_float = 0x000f, + FT_ext_prec_float = 0x0010, /* breaks "classic" svr4 SDB */ + FT_complex = 0x0011, /* breaks "classic" svr4 SDB */ + FT_dbl_prec_complex = 0x0012, /* breaks "classic" svr4 SDB */ + /* 0x0013 -- reserved */ + FT_void = 0x0014, + FT_boolean = 0x0015, /* breaks "classic" svr4 SDB */ + FT_ext_prec_complex = 0x0016, /* breaks "classic" svr4 SDB */ + FT_label = 0x0017, + + /* GNU extensions + The low order byte must indicate the size (in bytes) for the type. + All of these types will probably break "classic" svr4 SDB. */ + + FT_long_long = 0x8008, + FT_signed_long_long = 0x8108, + FT_unsigned_long_long = 0x8208, + + FT_int8 = 0x9001, + FT_signed_int8 = 0x9101, + FT_unsigned_int8 = 0x9201, + FT_int16 = 0x9302, + FT_signed_int16 = 0x9402, + FT_unsigned_int16 = 0x9502, + FT_int32 = 0x9604, + FT_signed_int32 = 0x9704, + FT_unsigned_int32 = 0x9804, + FT_int64 = 0x9908, + FT_signed_int64 = 0x9a08, + FT_unsigned_int64 = 0x9b08, + FT_int128 = 0x9c10, + FT_signed_int128 = 0x9d10, + FT_unsigned_int128 = 0x9e10, + + FT_real32 = 0xa004, + FT_real64 = 0xa108, + FT_real96 = 0xa20c, + FT_real128 = 0xa310 +}; + +#define FT_lo_user 0x8000 /* implementation-defined range start */ +#define FT_hi_user 0xffff /* implementation defined range end */ + +/* Type modifier names and codes. */ + +enum dwarf_type_modifier { + MOD_pointer_to = 0x01, + MOD_reference_to = 0x02, + MOD_const = 0x03, + MOD_volatile = 0x04 +}; + +#define MOD_lo_user 0x80 /* implementation-defined range start */ +#define MOD_hi_user 0xff /* implementation-defined range end */ + +/* Array ordering names and codes. */ + +enum dwarf_array_dim_ordering { + ORD_row_major = 0, + ORD_col_major = 1 +}; + +/* Array subscript format names and codes. */ + +enum dwarf_subscr_data_formats { + FMT_FT_C_C = 0x0, + FMT_FT_C_X = 0x1, + FMT_FT_X_C = 0x2, + FMT_FT_X_X = 0x3, + FMT_UT_C_C = 0x4, + FMT_UT_C_X = 0x5, + FMT_UT_X_C = 0x6, + FMT_UT_X_X = 0x7, + FMT_ET = 0x8 +}; + +/* Derived from above for ease of use. */ + +#define FMT_CODE(_FUNDAMENTAL_TYPE_P, _LB_CONST_P, _UB_CONST_P) \ + (((_FUNDAMENTAL_TYPE_P) ? 0 : 4) \ + | ((_LB_CONST_P) ? 0 : 2) \ + | ((_UB_CONST_P) ? 0 : 1)) + +/* Source language names and codes. */ + +enum dwarf_source_language { + LANG_C89 = 0x00000001, + LANG_C = 0x00000002, + LANG_ADA83 = 0x00000003, + LANG_C_PLUS_PLUS = 0x00000004, + LANG_COBOL74 = 0x00000005, + LANG_COBOL85 = 0x00000006, + LANG_FORTRAN77 = 0x00000007, + LANG_FORTRAN90 = 0x00000008, + LANG_PASCAL83 = 0x00000009, + LANG_MODULA2 = 0x0000000a, + LANG_JAVA = 0x0000000b +}; + +#define LANG_lo_user 0x00008000 /* implementation-defined range start */ +#define LANG_hi_user 0x0000ffff /* implementation-defined range end */ + +/* Names and codes for GNU "macinfo" extension. */ + +enum dwarf_macinfo_record_type { + MACINFO_start = 's', + MACINFO_resume = 'r', + MACINFO_define = 'd', + MACINFO_undef = 'u' +}; + +#endif /* _ELF_DWARF_H */ diff --git a/external/gpl3/gdb/dist/include/elf/external.h b/external/gpl3/gdb/dist/include/elf/external.h new file mode 100644 index 000000000000..ef7724e94bc5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/external.h @@ -0,0 +1,288 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1995, 1997, 1998, 1999, 2001, 2003, 2005, + 2008, 2010 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of ELF support for BFD, and contains the portions + that describe how ELF is represented externally by the BFD library. + I.E. it describes the in-file representation of ELF. It requires + the elf/common.h file which contains the portions that are common to + both the internal and external representations. */ + +/* The 64-bit stuff is kind of random. Perhaps someone will publish a + spec someday. */ + +#ifndef _ELF_EXTERNAL_H +#define _ELF_EXTERNAL_H + +/* Special section indices, which may show up in st_shndx fields, among + other places. */ + +#define SHN_LORESERVE 0xFF00 /* Begin range of reserved indices */ +#define SHN_LOPROC 0xFF00 /* Begin range of appl-specific */ +#define SHN_HIPROC 0xFF1F /* End range of appl-specific */ +#define SHN_LOOS 0xFF20 /* OS specific semantics, lo */ +#define SHN_HIOS 0xFF3F /* OS specific semantics, hi */ +#define SHN_ABS 0xFFF1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xFFF2 /* Associated symbol is in common */ +#define SHN_XINDEX 0xFFFF /* Section index is held elsewhere */ +#define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ + +/* ELF Header (32-bit implementations) */ + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[4]; /* Entry point virtual address */ + unsigned char e_phoff[4]; /* Program header table file offset */ + unsigned char e_shoff[4]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf32_External_Ehdr; + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[8]; /* Entry point virtual address */ + unsigned char e_phoff[8]; /* Program header table file offset */ + unsigned char e_shoff[8]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf64_External_Ehdr; + +/* Program header */ + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_offset[4]; /* Segment file offset */ + unsigned char p_vaddr[4]; /* Segment virtual address */ + unsigned char p_paddr[4]; /* Segment physical address */ + unsigned char p_filesz[4]; /* Segment size in file */ + unsigned char p_memsz[4]; /* Segment size in memory */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_align[4]; /* Segment alignment, file & memory */ +} Elf32_External_Phdr; + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_offset[8]; /* Segment file offset */ + unsigned char p_vaddr[8]; /* Segment virtual address */ + unsigned char p_paddr[8]; /* Segment physical address */ + unsigned char p_filesz[8]; /* Segment size in file */ + unsigned char p_memsz[8]; /* Segment size in memory */ + unsigned char p_align[8]; /* Segment alignment, file & memory */ +} Elf64_External_Phdr; + +/* Section header */ + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[4]; /* Miscellaneous section attributes */ + unsigned char sh_addr[4]; /* Section virtual addr at execution */ + unsigned char sh_offset[4]; /* Section file offset */ + unsigned char sh_size[4]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[4]; /* Section alignment */ + unsigned char sh_entsize[4]; /* Entry size if section holds table */ +} Elf32_External_Shdr; + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[8]; /* Miscellaneous section attributes */ + unsigned char sh_addr[8]; /* Section virtual addr at execution */ + unsigned char sh_offset[8]; /* Section file offset */ + unsigned char sh_size[8]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[8]; /* Section alignment */ + unsigned char sh_entsize[8]; /* Entry size if section holds table */ +} Elf64_External_Shdr; + +/* Symbol table entry */ + +typedef struct { + unsigned char st_name[4]; /* Symbol name, index in string tbl */ + unsigned char st_value[4]; /* Value of the symbol */ + unsigned char st_size[4]; /* Associated symbol size */ + unsigned char st_info[1]; /* Type and binding attributes */ + unsigned char st_other[1]; /* No defined meaning, 0 */ + unsigned char st_shndx[2]; /* Associated section index */ +} Elf32_External_Sym; + +typedef struct { + unsigned char st_name[4]; /* Symbol name, index in string tbl */ + unsigned char st_info[1]; /* Type and binding attributes */ + unsigned char st_other[1]; /* No defined meaning, 0 */ + unsigned char st_shndx[2]; /* Associated section index */ + unsigned char st_value[8]; /* Value of the symbol */ + unsigned char st_size[8]; /* Associated symbol size */ +} Elf64_External_Sym; + +typedef struct { + unsigned char est_shndx[4]; /* Section index */ +} Elf_External_Sym_Shndx; + +/* Note segments */ + +typedef struct { + unsigned char namesz[4]; /* Size of entry's owner string */ + unsigned char descsz[4]; /* Size of the note descriptor */ + unsigned char type[4]; /* Interpretation of the descriptor */ + char name[1]; /* Start of the name+desc data */ +} Elf_External_Note; + +/* Relocation Entries */ +typedef struct { + unsigned char r_offset[4]; /* Location at which to apply the action */ + unsigned char r_info[4]; /* index and type of relocation */ +} Elf32_External_Rel; + +typedef struct { + unsigned char r_offset[4]; /* Location at which to apply the action */ + unsigned char r_info[4]; /* index and type of relocation */ + unsigned char r_addend[4]; /* Constant addend used to compute value */ +} Elf32_External_Rela; + +typedef struct { + unsigned char r_offset[8]; /* Location at which to apply the action */ + unsigned char r_info[8]; /* index and type of relocation */ +} Elf64_External_Rel; + +typedef struct { + unsigned char r_offset[8]; /* Location at which to apply the action */ + unsigned char r_info[8]; /* index and type of relocation */ + unsigned char r_addend[8]; /* Constant addend used to compute value */ +} Elf64_External_Rela; + +/* dynamic section structure */ + +typedef struct { + unsigned char d_tag[4]; /* entry tag value */ + union { + unsigned char d_val[4]; + unsigned char d_ptr[4]; + } d_un; +} Elf32_External_Dyn; + +typedef struct { + unsigned char d_tag[8]; /* entry tag value */ + union { + unsigned char d_val[8]; + unsigned char d_ptr[8]; + } d_un; +} Elf64_External_Dyn; + +/* The version structures are currently size independent. They are + named without a 32 or 64. If that ever changes, these structures + will need to be renamed. */ + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct { + unsigned char vd_version[2]; + unsigned char vd_flags[2]; + unsigned char vd_ndx[2]; + unsigned char vd_cnt[2]; + unsigned char vd_hash[4]; + unsigned char vd_aux[4]; + unsigned char vd_next[4]; +} Elf_External_Verdef; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct { + unsigned char vda_name[4]; + unsigned char vda_next[4]; +} Elf_External_Verdaux; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct { + unsigned char vn_version[2]; + unsigned char vn_cnt[2]; + unsigned char vn_file[4]; + unsigned char vn_aux[4]; + unsigned char vn_next[4]; +} Elf_External_Verneed; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct { + unsigned char vna_hash[4]; + unsigned char vna_flags[2]; + unsigned char vna_other[2]; + unsigned char vna_name[4]; + unsigned char vna_next[4]; +} Elf_External_Vernaux; + +/* This structure appears in a SHT_GNU_versym section. This is not a + standard ELF structure; ELF just uses Elf32_Half. */ + +typedef struct { + unsigned char vs_vers[2]; +} ATTRIBUTE_PACKED Elf_External_Versym; + +/* Structure for syminfo section. */ +typedef struct +{ + unsigned char si_boundto[2]; + unsigned char si_flags[2]; +} Elf_External_Syminfo; + + +/* This structure appears on the stack and in NT_AUXV core file notes. */ +typedef struct +{ + unsigned char a_type[4]; + unsigned char a_val[4]; +} Elf32_External_Auxv; + +typedef struct +{ + unsigned char a_type[8]; + unsigned char a_val[8]; +} Elf64_External_Auxv; + +/* Size of SHT_GROUP section entry. */ + +#define GRP_ENTRY_SIZE 4 + +#endif /* _ELF_EXTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/elf/fr30.h b/external/gpl3/gdb/dist/include/elf/fr30.h new file mode 100644 index 000000000000..918ac977f868 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/fr30.h @@ -0,0 +1,42 @@ +/* FR30 ELF support for BFD. + Copyright 1998, 1999, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_FR30_H +#define _ELF_FR30_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_fr30_reloc_type) + RELOC_NUMBER (R_FR30_NONE, 0) + RELOC_NUMBER (R_FR30_8, 1) + RELOC_NUMBER (R_FR30_20, 2) + RELOC_NUMBER (R_FR30_32, 3) + RELOC_NUMBER (R_FR30_48, 4) + RELOC_NUMBER (R_FR30_6_IN_4, 5) + RELOC_NUMBER (R_FR30_8_IN_8, 6) + RELOC_NUMBER (R_FR30_9_IN_8, 7) + RELOC_NUMBER (R_FR30_10_IN_8, 8) + RELOC_NUMBER (R_FR30_9_PCREL, 9) + RELOC_NUMBER (R_FR30_12_PCREL, 10) + RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12) +END_RELOC_NUMBERS (R_FR30_max) + +#endif /* _ELF_FR30_H */ diff --git a/external/gpl3/gdb/dist/include/elf/frv.h b/external/gpl3/gdb/dist/include/elf/frv.h new file mode 100644 index 000000000000..b79e51d0653a --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/frv.h @@ -0,0 +1,130 @@ +/* FRV ELF support for BFD. + Copyright (C) 2002, 2003, 2004, 2005, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_FRV_H +#define _ELF_FRV_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_frv_reloc_type) + RELOC_NUMBER (R_FRV_NONE, 0) + RELOC_NUMBER (R_FRV_32, 1) + RELOC_NUMBER (R_FRV_LABEL16, 2) + RELOC_NUMBER (R_FRV_LABEL24, 3) + RELOC_NUMBER (R_FRV_LO16, 4) + RELOC_NUMBER (R_FRV_HI16, 5) + RELOC_NUMBER (R_FRV_GPREL12, 6) + RELOC_NUMBER (R_FRV_GPRELU12, 7) + RELOC_NUMBER (R_FRV_GPREL32, 8) + RELOC_NUMBER (R_FRV_GPRELHI, 9) + RELOC_NUMBER (R_FRV_GPRELLO, 10) + RELOC_NUMBER (R_FRV_GOT12, 11) + RELOC_NUMBER (R_FRV_GOTHI, 12) + RELOC_NUMBER (R_FRV_GOTLO, 13) + RELOC_NUMBER (R_FRV_FUNCDESC, 14) + RELOC_NUMBER (R_FRV_FUNCDESC_GOT12, 15) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTHI, 16) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTLO, 17) + RELOC_NUMBER (R_FRV_FUNCDESC_VALUE, 18) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFF12, 19) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFHI, 20) + RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFLO, 21) + RELOC_NUMBER (R_FRV_GOTOFF12, 22) + RELOC_NUMBER (R_FRV_GOTOFFHI, 23) + RELOC_NUMBER (R_FRV_GOTOFFLO, 24) + RELOC_NUMBER (R_FRV_GETTLSOFF, 25) + RELOC_NUMBER (R_FRV_TLSDESC_VALUE, 26) + RELOC_NUMBER (R_FRV_GOTTLSDESC12, 27) + RELOC_NUMBER (R_FRV_GOTTLSDESCHI, 28) + RELOC_NUMBER (R_FRV_GOTTLSDESCLO, 29) + RELOC_NUMBER (R_FRV_TLSMOFF12, 30) + RELOC_NUMBER (R_FRV_TLSMOFFHI, 31) + RELOC_NUMBER (R_FRV_TLSMOFFLO, 32) + RELOC_NUMBER (R_FRV_GOTTLSOFF12, 33) + RELOC_NUMBER (R_FRV_GOTTLSOFFHI, 34) + RELOC_NUMBER (R_FRV_GOTTLSOFFLO, 35) + RELOC_NUMBER (R_FRV_TLSOFF, 36) + RELOC_NUMBER (R_FRV_TLSDESC_RELAX, 37) + RELOC_NUMBER (R_FRV_GETTLSOFF_RELAX, 38) + RELOC_NUMBER (R_FRV_TLSOFF_RELAX, 39) + RELOC_NUMBER (R_FRV_TLSMOFF, 40) + RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_FRV_max) + +/* Processor specific flags for the ELF header e_flags field. */ + /* gpr support */ +#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */ +#define EF_FRV_GPR_32 0x00000001 /* -mgpr-32 */ +#define EF_FRV_GPR_64 0x00000002 /* -mgpr-64 */ + + /* fpr support */ +#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */ +#define EF_FRV_FPR_32 0x00000004 /* -mfpr-32 */ +#define EF_FRV_FPR_64 0x00000008 /* -mfpr-64 */ +#define EF_FRV_FPR_NONE 0x0000000c /* -msoft-float */ + + /* double word support */ +#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */ +#define EF_FRV_DWORD_YES 0x00000010 /* use double word insns */ +#define EF_FRV_DWORD_NO 0x00000020 /* don't use double word insn*/ + +#define EF_FRV_DOUBLE 0x00000040 /* -mdouble */ +#define EF_FRV_MEDIA 0x00000080 /* -mmedia */ + +#define EF_FRV_PIC 0x00000100 /* -fpic */ +#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* used non pic safe relocs */ + +#define EF_FRV_MULADD 0x00000400 /* -mmuladd */ +#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */ +#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */ +#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */ +#define EF_FRV_NOPACK 0x00004000 /* -mnopack */ +#define EF_FRV_FDPIC 0x00008000 /* -mfdpic */ + +#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */ +#define EF_FRV_CPU_GENERIC 0x00000000 /* generic FRV */ +#define EF_FRV_CPU_FR500 0x01000000 /* FRV500 */ +#define EF_FRV_CPU_FR300 0x02000000 /* FRV300 */ +#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */ +#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */ +#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */ +#define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */ +#define EF_FRV_CPU_FR405 0x07000000 +#define EF_FRV_CPU_FR450 0x08000000 + + /* Mask of PIC related bits */ +#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \ + | EF_FRV_FDPIC) + + /* Mask of all flags */ +#define EF_FRV_ALL_FLAGS (EF_FRV_GPR_MASK | \ + EF_FRV_FPR_MASK | \ + EF_FRV_DWORD_MASK | \ + EF_FRV_DOUBLE | \ + EF_FRV_MEDIA | \ + EF_FRV_PIC_FLAGS | \ + EF_FRV_NON_PIC_RELOCS | \ + EF_FRV_MULADD | \ + EF_FRV_G0 | \ + EF_FRV_NOPACK | \ + EF_FRV_CPU_MASK) + +#endif /* _ELF_FRV_H */ diff --git a/external/gpl3/gdb/dist/include/elf/h8.h b/external/gpl3/gdb/dist/include/elf/h8.h new file mode 100644 index 000000000000..36aef6a254f8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/h8.h @@ -0,0 +1,100 @@ +/* H8300/h8500 ELF support for BFD. + Copyright 2001, 2003, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_H8_H +#define _ELF_H8_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 59..63 are GNU extensions. */ +START_RELOC_NUMBERS (elf_h8_reloc_type) + RELOC_NUMBER (R_H8_NONE, 0) + RELOC_NUMBER (R_H8_DIR32, 1) + RELOC_NUMBER (R_H8_DIR32_28, 2) + RELOC_NUMBER (R_H8_DIR32_24, 3) + RELOC_NUMBER (R_H8_DIR32_16, 4) + RELOC_NUMBER (R_H8_DIR32U, 6) + RELOC_NUMBER (R_H8_DIR32U_28, 7) + RELOC_NUMBER (R_H8_DIR32U_24, 8) + RELOC_NUMBER (R_H8_DIR32U_20, 9) + RELOC_NUMBER (R_H8_DIR32U_16, 10) + RELOC_NUMBER (R_H8_DIR24, 11) + RELOC_NUMBER (R_H8_DIR24_20, 12) + RELOC_NUMBER (R_H8_DIR24_16, 13) + RELOC_NUMBER (R_H8_DIR24U, 14) + RELOC_NUMBER (R_H8_DIR24U_20, 15) + RELOC_NUMBER (R_H8_DIR24U_16, 16) + RELOC_NUMBER (R_H8_DIR16, 17) + RELOC_NUMBER (R_H8_DIR16U, 18) + RELOC_NUMBER (R_H8_DIR16S_32, 19) + RELOC_NUMBER (R_H8_DIR16S_28, 20) + RELOC_NUMBER (R_H8_DIR16S_24, 21) + RELOC_NUMBER (R_H8_DIR16S_20, 22) + RELOC_NUMBER (R_H8_DIR16S, 23) + RELOC_NUMBER (R_H8_DIR8, 24) + RELOC_NUMBER (R_H8_DIR8U, 25) + RELOC_NUMBER (R_H8_DIR8Z_32, 26) + RELOC_NUMBER (R_H8_DIR8Z_28, 27) + RELOC_NUMBER (R_H8_DIR8Z_24, 28) + RELOC_NUMBER (R_H8_DIR8Z_20, 29) + RELOC_NUMBER (R_H8_DIR8Z_16, 30) + RELOC_NUMBER (R_H8_PCREL16, 31) + RELOC_NUMBER (R_H8_PCREL8, 32) + RELOC_NUMBER (R_H8_BPOS, 33) + FAKE_RELOC (R_H8_FIRST_INVALID_DIR_RELOC, 34) + FAKE_RELOC (R_H8_LAST_INVALID_DIR_RELOC, 58) + RELOC_NUMBER (R_H8_DIR16A8, 59) + RELOC_NUMBER (R_H8_DIR16R8, 60) + RELOC_NUMBER (R_H8_DIR24A8, 61) + RELOC_NUMBER (R_H8_DIR24R8, 62) + RELOC_NUMBER (R_H8_DIR32A16, 63) + RELOC_NUMBER (R_H8_ABS32, 65) + RELOC_NUMBER (R_H8_ABS32A16, 127) + RELOC_NUMBER (R_H8_SYM, 128) + RELOC_NUMBER (R_H8_OPneg, 129) + RELOC_NUMBER (R_H8_OPadd, 130) + RELOC_NUMBER (R_H8_OPsub, 131) + RELOC_NUMBER (R_H8_OPmul, 132) + RELOC_NUMBER (R_H8_OPdiv, 133) + RELOC_NUMBER (R_H8_OPshla, 134) + RELOC_NUMBER (R_H8_OPshra, 135) + RELOC_NUMBER (R_H8_OPsctsize, 136) + RELOC_NUMBER (R_H8_OPhword, 137) + RELOC_NUMBER (R_H8_OPlword, 138) + RELOC_NUMBER (R_H8_OPhigh, 139) + RELOC_NUMBER (R_H8_OPlow, 140) + RELOC_NUMBER (R_H8_OPscttop, 141) +END_RELOC_NUMBERS (R_H8_max) + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_H8_MACH 0x00FF0000 + +#define E_H8_MACH_H8300 0x00800000 +#define E_H8_MACH_H8300H 0x00810000 +#define E_H8_MACH_H8300S 0x00820000 +#define E_H8_MACH_H8300HN 0x00830000 +#define E_H8_MACH_H8300SN 0x00840000 +#define E_H8_MACH_H8300SX 0x00850000 +#define E_H8_MACH_H8300SXN 0x00860000 + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/hppa.h b/external/gpl3/gdb/dist/include/elf/hppa.h new file mode 100644 index 000000000000..8d3ea45f41f5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/hppa.h @@ -0,0 +1,635 @@ +/* HPPA ELF support for BFD. + Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2005, 2006, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the HPPA ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_HPPA_H +#define _ELF_HPPA_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Trap null address dereferences. */ +#define EF_PARISC_TRAPNIL 0x00010000 + +/* .PARISC.archext section is present. */ +#define EF_PARISC_EXT 0x00020000 + +/* Program expects little-endian mode. */ +#define EF_PARISC_LSB 0x00040000 + +/* Program expects wide mode. */ +#define EF_PARISC_WIDE 0x00080000 + +/* Do not allow kernel-assisted branch prediction. */ +#define EF_PARISC_NO_KABP 0x00100000 + +/* Allow lazy swap for dynamically allocated program segments. */ +#define EF_PARISC_LAZYSWAP 0x00400000 + +/* Architecture version */ +#define EF_PARISC_ARCH 0x0000ffff + +#define EFA_PARISC_1_0 0x020b +#define EFA_PARISC_1_1 0x0210 +#define EFA_PARISC_2_0 0x0214 + +/* Special section indices. */ +/* A symbol that has been declared as a tentative definition in an ANSI C + compilation. */ +#define SHN_PARISC_ANSI_COMMON SHN_LORESERVE + +/* A symbol that has been declared as a common block using the + huge memory model. */ +#define SHN_PARISC_HUGE_COMMON (SHN_LORESERVE + 1) + +/* Processor specific section types. */ + +/* Section contains product specific extension bits. */ +#define SHT_PARISC_EXT 0x70000000 + +/* Section contains unwind table entries. */ +#define SHT_PARISC_UNWIND 0x70000001 + +/* Section contains debug information for optimized code. */ +#define SHT_PARISC_DOC 0x70000002 + +/* Section contains code annotations. */ +#define SHT_PARISC_ANNOT 0x70000003 + +/* DLKM special section. */ +#define SHT_PARISC_DLKM 0x70000004 + +/* These are strictly for compatibility with the older elf32-hppa + implementation. Hopefully we can eliminate them in the future. */ +/* Optional section holding argument location/relocation info. */ +#define SHT_PARISC_SYMEXTN SHT_LOPROC + 8 + +/* Option section for linker stubs. */ +#define SHT_PARISC_STUBS SHT_LOPROC + 9 + +/* Processor specific section flags. */ + +/* Section contains code compiled for static branch prediction. */ +#define SHF_PARISC_SBP 0x80000000 + +/* Section should be allocated from from GP. */ +#define SHF_PARISC_HUGE 0x40000000 + +/* Section should go near GP. */ +#define SHF_PARISC_SHORT 0x20000000 + +/* Section is weak ordered. */ +#define SHF_PARISC_WEAKORDER 0x10000000 + +/* Identifies the entry point of a millicode routine. */ +#define STT_PARISC_MILLI 13 + +/* ELF/HPPA relocation types */ + +/* Note: PA-ELF is defined to use only RELA relocations. */ +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_hppa_reloc_type) +RELOC_NUMBER (R_PARISC_NONE, 0) /* No reloc */ + +/* Data / Inst. Format Relocation Expression */ + +RELOC_NUMBER (R_PARISC_DIR32, 1) +/* 32-bit word symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR21L, 2) +/* long immediate (7) LR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17R, 3) +/* branch external (19) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17F, 4) +/* branch external (19) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR14R, 6) +/* load/store (1) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14F, 7) +/* load/store (1) symbol, addend */ + +/* PC-relative relocation types + Typically used for calls. + Note PCREL17C and PCREL17F differ only in overflow handling. + PCREL17C never reports a relocation error. + + When supporting argument relocations, function calls must be + accompanied by parameter relocation information. This information is + carried in the ten high-order bits of the addend field. The remaining + 22 bits of of the addend field are sign-extended to form the Addend. + + Note the code to build argument relocations depends on the + addend being zero. A consequence of this limitation is GAS + can not perform relocation reductions for function symbols. */ + +RELOC_NUMBER (R_PARISC_PCREL12F, 8) +/* op & branch (17) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL32, 9) +/* 32-bit word symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL21L, 10) +/* long immediate (7) L(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17R, 11) +/* branch external (19) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17F, 12) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL17C, 13) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14R, 14) +/* load/store (1) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14F, 15) +/* load/store (1) symbol - PC - 8 + addend */ + + +/* DP-relative relocation types. */ +RELOC_NUMBER (R_PARISC_DPREL21L, 18) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14WR, 19) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14DR, 20) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14R, 22) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14F, 23) +/* load/store (1) symbol - GP + addend */ + + +/* Data linkage table (DLT) relocation types + + SOM DLT_REL fixup requests are used to for static data references + from position-independent code within shared libraries. They are + similar to the GOT relocation types in some SVR4 implementations. */ + +RELOC_NUMBER (R_PARISC_DLTREL21L, 26) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14R, 30) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14F, 31) +/* load/store (1) symbol - GP + addend */ + + +/* DLT indirect relocation types */ +RELOC_NUMBER (R_PARISC_DLTIND21L, 34) +/* long immediate (7) L(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14R, 38) +/* load/store (1) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14F, 39) +/* load/store (1) ltoff(symbol + addend) */ + + +/* Base relative relocation types. Ugh. These imply lots of state */ +RELOC_NUMBER (R_PARISC_SETBASE, 40) +/* none no reloc; base := sym */ + +RELOC_NUMBER (R_PARISC_SECREL32, 41) +/* 32-bit word symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL21L, 42) +/* long immediate (7) LR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17R, 43) +/* branch external (19) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17F, 44) +/* branch external (19) symbol - base + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14R, 46) +/* load/store (1) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14F, 47) +/* load/store (1) symbol - base, addend */ + + +/* Segment relative relocation types. */ +RELOC_NUMBER (R_PARISC_SEGBASE, 48) +/* none no relocation; SB := sym */ + +RELOC_NUMBER (R_PARISC_SEGREL32, 49) +/* 32-bit word symbol - SB + addend */ + + +/* Offsets from the PLT. */ +RELOC_NUMBER (R_PARISC_PLTOFF21L, 50) +/* long immediate (7) LR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14R, 54) +/* load/store (1) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14F, 55) +/* load/store (1) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR32, 57) +/* 32-bit word ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 58) +/* long immediate (7) L(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 62) +/* load/store (1) R(ltoff(fptr(symbol+addend))) */ + + +RELOC_NUMBER (R_PARISC_FPTR64, 64) +/* 64-bit doubleword fptr(symbol+addend) */ + + +/* Plabel relocation types. */ +RELOC_NUMBER (R_PARISC_PLABEL32, 65) +/* 32-bit word fptr(symbol) */ + +RELOC_NUMBER (R_PARISC_PLABEL21L, 66) +/* long immediate (7) L(fptr(symbol)) */ + +RELOC_NUMBER (R_PARISC_PLABEL14R, 70) +/* load/store (1) R(fptr(symbol)) */ + + +/* PCREL relocations. */ +RELOC_NUMBER (R_PARISC_PCREL64, 72) +/* 64-bit doubleword symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22C, 73) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22F, 74) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14WR, 75) +/* load/store mod. comp. (2) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14DR, 76) +/* load/store doubleword (3) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL16F, 77) +/* load/store (1) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16WF, 78) +/* load/store mod. comp. (2) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16DF, 79) +/* load/store doubleword (3) symbol - PC - 8 + addend */ + + +RELOC_NUMBER (R_PARISC_DIR64, 80) +/* 64-bit doubleword symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR14WR, 83) +/* load/store mod. comp. (2) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14DR, 84) +/* load/store doubleword (3) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR16F, 85) +/* load/store (1) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16WF, 86) +/* load/store mod. comp. (2) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16DF, 87) +/* load/store doubleword (3) symbol + addend */ + +RELOC_NUMBER (R_PARISC_GPREL64, 88) +/* 64-bit doubleword symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_DLTREL14WR, 91) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14DR, 92) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_GPREL16F, 93) +/* load/store (1) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16WF, 94) +/* load/store mod. comp. (2) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16DF, 95) +/* load/store doubleword (3) symbol - GP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF64, 96) +/* 64-bit doubleword ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_DLTIND14WR, 99) +/* load/store mod. comp. (2) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14DR, 100) +/* load/store doubleword (3) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF16F, 101) +/* load/store (1) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16WF, 102) +/* load/store mod. comp. (2) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16DF, 103) +/* load/store doubleword (3) ltoff(symbol + addend) */ + + +RELOC_NUMBER (R_PARISC_SECREL64, 104) +/* 64-bit doubleword symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14WR, 107) +/* load/store mod. comp. (2) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14DR, 108) +/* load/store doubleword (3) RR(symbol - base, addend) */ + + +RELOC_NUMBER (R_PARISC_SEGREL64, 112) +/* 64-bit doubleword symbol - SB + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF14WR, 115) +/* load/store mod. comp. (2) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14DR, 116) +/* load/store doubleword (3) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF16F, 117) +/* load/store (1) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16WF, 118) +/* load/store mod. comp. (2) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16DF, 119) +/* load/store doubleword (3) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR64, 120) +/* 64-bit doubleword ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123) +/* load/store mod. comp. (2) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124) +/* load/store doubleword (3) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F, 125) +/* load/store (1) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126) +/* load/store mod. comp. (2) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127) +/* load/store doubleword (3) ltoff(fptr(symbol+addend)) */ + + +RELOC_NUMBER (R_PARISC_COPY, 128) +/* data Dynamic relocations only */ + +RELOC_NUMBER (R_PARISC_IPLT, 129) +/* plt */ + +RELOC_NUMBER (R_PARISC_EPLT, 130) +/* plt */ + + +RELOC_NUMBER (R_PARISC_TPREL32, 153) +/* 32-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL21L, 154) +/* long immediate (7) LR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14R, 158) +/* load/store (1) RR(symbol - TP, addend) */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP21L, 162) +/* long immediate (7) L(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14R, 166) +/* load/store (1) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14F, 167) +/* load/store (1) ltoff(symbol - TP + addend) */ + + +RELOC_NUMBER (R_PARISC_TPREL64, 216) +/* 64-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL14WR, 219) +/* load/store mod. comp. (2) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14DR, 220) +/* load/store doubleword (3) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL16F, 221) +/* load/store (1) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16WF, 222) +/* load/store mod. comp. (2) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16DF, 223) +/* load/store doubleword (3) symbol - TP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP64, 224) +/* 64-bit doubleword ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14WR, 227) +/* load/store mod. comp. (2) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14DR, 228) +/* load/store doubleword (3) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16F, 229) +/* load/store (1) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16WF, 230) +/* load/store mod. comp. (2) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) +/* load/store doubleword (3) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_GNU_VTENTRY, 232) +RELOC_NUMBER (R_PARISC_GNU_VTINHERIT, 233) + +RELOC_NUMBER (R_PARISC_TLS_GD21L, 234) +RELOC_NUMBER (R_PARISC_TLS_GD14R, 235) +RELOC_NUMBER (R_PARISC_TLS_GDCALL, 236) +RELOC_NUMBER (R_PARISC_TLS_LDM21L, 237) +RELOC_NUMBER (R_PARISC_TLS_LDM14R, 238) +RELOC_NUMBER (R_PARISC_TLS_LDMCALL, 239) +RELOC_NUMBER (R_PARISC_TLS_LDO21L, 240) +RELOC_NUMBER (R_PARISC_TLS_LDO14R, 241) +RELOC_NUMBER (R_PARISC_TLS_DTPMOD32, 242) +RELOC_NUMBER (R_PARISC_TLS_DTPMOD64, 243) +RELOC_NUMBER (R_PARISC_TLS_DTPOFF32, 244) +RELOC_NUMBER (R_PARISC_TLS_DTPOFF64, 245) + +END_RELOC_NUMBERS (R_PARISC_UNIMPLEMENTED) + +#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L +#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R +#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L +#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R +#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 +#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 + +#ifndef RELOC_MACROS_GEN_FUNC +typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; +#endif + +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 +#define PT_PARISC_WEAKORDER 0x70000002 + +/* Flag bits in sh_flags of ElfXX_Shdr. */ +#define SHF_HP_TLS 0x01000000 +#define SHF_HP_NEAR_SHARED 0x02000000 +#define SHF_HP_FAR_SHARED 0x04000000 +#define SHF_HP_COMDAT 0x08000000 +#define SHF_HP_CONST 0x00800000 + +/* Reserved section header indices. */ +#define SHN_TLS_COMMON (SHN_LOOS + 0x0) +#define SHN_NS_COMMON (SHN_LOOS + 0x1) +#define SHN_FS_COMMON (SHN_LOOS + 0x2) +#define SHN_NS_UNDEF (SHN_LOOS + 0x3) +#define SHN_FS_UNDEF (SHN_LOOS + 0x4) +#define SHN_HP_EXTERN (SHN_LOOS + 0x5) +#define SHN_HP_EXTHINT (SHN_LOOS + 0x6) +#define SHN_HP_UNDEF_BIND_IMM (SHN_LOOS + 0x7) + +/* Values of sh_type in ElfXX_Shdr. */ +#define SHT_HP_OVLBITS (SHT_LOOS + 0x0) +#define SHT_HP_DLKM (SHT_LOOS + 0x1) +#define SHT_HP_COMDAT (SHT_LOOS + 0x2) +#define SHT_HP_OBJDICT (SHT_LOOS + 0x3) +#define SHT_HP_ANNOT (SHT_LOOS + 0x4) + +/* Flag bits in p_flags of ElfXX_Phdr. */ +#define PF_HP_CODE 0x00040000 +#define PF_HP_MODIFY 0x00080000 +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_LAZYSWAP 0x00800000 +#define PF_HP_CODE_DEPR 0x01000000 +#define PF_HP_MODIFY_DEPR 0x02000000 +#define PF_HP_LAZYSWAP_DEPR 0x04000000 +#define PF_PARISC_SBP 0x08000000 +#define PF_HP_SBP 0x08000000 + + +/* Processor specific dynamic array tags. */ + +/* Arggh. HP's tools define these symbols based on the + old value of DT_LOOS. So we must do the same to be + compatible. */ +#define DT_HP_LOAD_MAP (OLD_DT_LOOS + 0x0) +#define DT_HP_DLD_FLAGS (OLD_DT_LOOS + 0x1) +#define DT_HP_DLD_HOOK (OLD_DT_LOOS + 0x2) +#define DT_HP_UX10_INIT (OLD_DT_LOOS + 0x3) +#define DT_HP_UX10_INITSZ (OLD_DT_LOOS + 0x4) +#define DT_HP_PREINIT (OLD_DT_LOOS + 0x5) +#define DT_HP_PREINITSZ (OLD_DT_LOOS + 0x6) +#define DT_HP_NEEDED (OLD_DT_LOOS + 0x7) +#define DT_HP_TIME_STAMP (OLD_DT_LOOS + 0x8) +#define DT_HP_CHECKSUM (OLD_DT_LOOS + 0x9) +#define DT_HP_GST_SIZE (OLD_DT_LOOS + 0xa) +#define DT_HP_GST_VERSION (OLD_DT_LOOS + 0xb) +#define DT_HP_GST_HASHVAL (OLD_DT_LOOS + 0xc) +#define DT_HP_EPLTREL (OLD_DT_LOOS + 0xd) +#define DT_HP_EPLTRELSZ (OLD_DT_LOOS + 0xe) +#define DT_HP_FILTERED (OLD_DT_LOOS + 0xf) +#define DT_HP_FILTER_TLS (OLD_DT_LOOS + 0x10) +#define DT_HP_COMPAT_FILTERED (OLD_DT_LOOS + 0x11) +#define DT_HP_LAZYLOAD (OLD_DT_LOOS + 0x12) +#define DT_HP_BIND_NOW_COUNT (OLD_DT_LOOS + 0x13) +#define DT_PLT (OLD_DT_LOOS + 0x14) +#define DT_PLT_SIZE (OLD_DT_LOOS + 0x15) +#define DT_DLT (OLD_DT_LOOS + 0x16) +#define DT_DLT_SIZE (OLD_DT_LOOS + 0x17) + +/* Values for DT_HP_DLD_FLAGS. */ +#define DT_HP_DEBUG_PRIVATE 0x00001 /* Map text private */ +#define DT_HP_DEBUG_CALLBACK 0x00002 /* Callback */ +#define DT_HP_DEBUG_CALLBACK_BOR 0x00004 /* BOR callback */ +#define DT_HP_NO_ENVVAR 0x00008 /* No env var */ +#define DT_HP_BIND_NOW 0x00010 /* Bind now */ +#define DT_HP_BIND_NONFATAL 0x00020 /* Bind non-fatal */ +#define DT_HP_BIND_VERBOSE 0x00040 /* Bind verbose */ +#define DT_HP_BIND_RESTRICTED 0x00080 /* Bind restricted */ +#define DT_HP_BIND_SYMBOLIC 0x00100 /* Bind symbolic */ +#define DT_HP_RPATH_FIRST 0x00200 /* RPATH first */ +#define DT_HP_BIND_DEPTH_FIRST 0x00400 /* Bind depth-first */ +#define DT_HP_GST 0x00800 /* Dld global sym table */ +#define DT_HP_SHLIB_FIXED 0x01000 /* shared vtable support */ +#define DT_HP_MERGE_SHLIB_SEG 0x02000 /* merge shlib data segs */ +#define DT_HP_NODELETE 0x04000 /* never unload */ +#define DT_HP_GROUP 0x08000 /* bind only within group */ +#define DT_HP_PROTECT_LINKAGE_TABLE 0x10000 /* protected linkage table */ + +/* Program header extensions. */ +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) +#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) +#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) +#define PT_HP_STACK (PT_LOOS + 0x14) +#define PT_HP_CORE_UTSNAME (PT_LOOS + 0x15) + +/* Binding information. */ +#define STB_HP_ALIAS (STB_LOOS + 0x0) + +/* Additional symbol types. */ +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + +/* Note types. */ +#define NT_HP_COMPILER 1 +#define NT_HP_COPYRIGHT 2 +#define NT_HP_VERSION 3 +#define NT_HP_SRCFILE_INFO 4 +#define NT_HP_LINKER 5 +#define NT_HP_INSTRUMENTED 6 +#define NT_HP_UX_OPTIONS 7 + +#endif /* _ELF_HPPA_H */ diff --git a/external/gpl3/gdb/dist/include/elf/i370.h b/external/gpl3/gdb/dist/include/elf/i370.h new file mode 100644 index 000000000000..7b451ff9db21 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/i370.h @@ -0,0 +1,61 @@ +/* i370 ELF support for BFD. + Copyright 2000, 2002, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the i370 ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_I370_H +#define _ELF_I370_H + +#include "elf/reloc-macros.h" + +/* Processor specific section headers, sh_type field */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */ +#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */ + +/* i370 relocations + Note that there is really just one relocation that we currently + support (and only one that we seem to need, at the moment), and + that is the 31-bit address relocation. Note that the 370/390 + only supports a 31-bit (2GB) address space. */ + +START_RELOC_NUMBERS (i370_reloc_type) + RELOC_NUMBER (R_I370_NONE, 0) + RELOC_NUMBER (R_I370_ADDR31, 1) + RELOC_NUMBER (R_I370_ADDR32, 2) + RELOC_NUMBER (R_I370_ADDR16, 3) + RELOC_NUMBER (R_I370_REL31, 4) + RELOC_NUMBER (R_I370_REL32, 5) + RELOC_NUMBER (R_I370_ADDR12, 6) + RELOC_NUMBER (R_I370_REL12, 7) + RELOC_NUMBER (R_I370_ADDR8, 8) + RELOC_NUMBER (R_I370_REL8, 9) + RELOC_NUMBER (R_I370_COPY, 10) + RELOC_NUMBER (R_I370_RELATIVE, 11) +END_RELOC_NUMBERS (R_I370_max) + +#endif /* _ELF_I370_H */ diff --git a/external/gpl3/gdb/dist/include/elf/i386.h b/external/gpl3/gdb/dist/include/elf/i386.h new file mode 100644 index 000000000000..a12225faa254 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/i386.h @@ -0,0 +1,79 @@ +/* ix86 ELF support for BFD. + Copyright 1998, 1999, 2000, 2002, 2004, 2005, 2006, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_I386_H +#define _ELF_I386_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i386_reloc_type) + RELOC_NUMBER (R_386_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_386_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_386_PC32, 2) /* PC relative 32 bit */ + RELOC_NUMBER (R_386_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_386_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_386_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_386_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_386_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_386_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_386_GOTOFF, 9) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_386_GOTPC, 10) /* 32 bit PC relative offset to GOT */ + RELOC_NUMBER (R_386_32PLT, 11) /* Used by Sun */ + FAKE_RELOC (FIRST_INVALID_RELOC, 12) + FAKE_RELOC (LAST_INVALID_RELOC, 13) + RELOC_NUMBER (R_386_TLS_TPOFF,14) + RELOC_NUMBER (R_386_TLS_IE, 15) + RELOC_NUMBER (R_386_TLS_GOTIE,16) + RELOC_NUMBER (R_386_TLS_LE, 17) + RELOC_NUMBER (R_386_TLS_GD, 18) + RELOC_NUMBER (R_386_TLS_LDM, 19) + RELOC_NUMBER (R_386_16, 20) + RELOC_NUMBER (R_386_PC16, 21) + RELOC_NUMBER (R_386_8, 22) + RELOC_NUMBER (R_386_PC8, 23) + RELOC_NUMBER (R_386_TLS_GD_32, 24) + RELOC_NUMBER (R_386_TLS_GD_PUSH, 25) + RELOC_NUMBER (R_386_TLS_GD_CALL, 26) + RELOC_NUMBER (R_386_TLS_GD_POP, 27) + RELOC_NUMBER (R_386_TLS_LDM_32, 28) + RELOC_NUMBER (R_386_TLS_LDM_PUSH, 29) + RELOC_NUMBER (R_386_TLS_LDM_CALL, 30) + RELOC_NUMBER (R_386_TLS_LDM_POP, 31) + RELOC_NUMBER (R_386_TLS_LDO_32, 32) + RELOC_NUMBER (R_386_TLS_IE_32, 33) + RELOC_NUMBER (R_386_TLS_LE_32, 34) + RELOC_NUMBER (R_386_TLS_DTPMOD32, 35) + RELOC_NUMBER (R_386_TLS_DTPOFF32, 36) + RELOC_NUMBER (R_386_TLS_TPOFF32, 37) +/* 38 */ + RELOC_NUMBER (R_386_TLS_GOTDESC, 39) + RELOC_NUMBER (R_386_TLS_DESC_CALL,40) + RELOC_NUMBER (R_386_TLS_DESC, 41) + RELOC_NUMBER (R_386_IRELATIVE, 42) /* Adjust indirectly by program base */ + + /* Used by Intel. */ + RELOC_NUMBER (R_386_USED_BY_INTEL_200, 200) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_386_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_386_GNU_VTENTRY, 251) +END_RELOC_NUMBERS (R_386_max) + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/i860.h b/external/gpl3/gdb/dist/include/elf/i860.h new file mode 100644 index 000000000000..834c77660aa4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/i860.h @@ -0,0 +1,66 @@ +/* i860 ELF support for BFD. + Copyright 2000, 2010 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt . + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_I860_H +#define _ELF_I860_H + +/* Note: i860 ELF is defined to use only RELA relocations. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i860_reloc_type) + RELOC_NUMBER (R_860_NONE, 0x00) /* No reloc */ + RELOC_NUMBER (R_860_32, 0x01) /* S+A */ + RELOC_NUMBER (R_860_COPY, 0x02) /* No calculation */ + RELOC_NUMBER (R_860_GLOB_DAT, 0x03) /* S, Create GOT entry */ + RELOC_NUMBER (R_860_JUMP_SLOT, 0x04) /* S+A, Create PLT entry */ + RELOC_NUMBER (R_860_RELATIVE, 0x05) /* B+A, Adj by program base */ + RELOC_NUMBER (R_860_PC26, 0x30) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_PLT26, 0x31) /* (L+A-P) >> 2 */ + RELOC_NUMBER (R_860_PC16, 0x32) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_LOW0, 0x40) /* S+A */ + RELOC_NUMBER (R_860_SPLIT0, 0x42) /* S+A */ + RELOC_NUMBER (R_860_LOW1, 0x44) /* S+A */ + RELOC_NUMBER (R_860_SPLIT1, 0x46) /* S+A */ + RELOC_NUMBER (R_860_LOW2, 0x48) /* S+A */ + RELOC_NUMBER (R_860_SPLIT2, 0x4A) /* S+A */ + RELOC_NUMBER (R_860_LOW3, 0x4C) /* S+A */ + RELOC_NUMBER (R_860_LOGOT0, 0x50) /* G */ + RELOC_NUMBER (R_860_SPGOT0, 0x52) /* G */ + RELOC_NUMBER (R_860_LOGOT1, 0x54) /* G */ + RELOC_NUMBER (R_860_SPGOT1, 0x56) /* G */ + RELOC_NUMBER (R_860_LOGOTOFF0, 0x60) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF0, 0x62) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF1, 0x64) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF1, 0x66) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF2, 0x68) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C) /* O */ + RELOC_NUMBER (R_860_LOPC, 0x70) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_HIGHADJ, 0x80) /* hiadj(S+A) */ + RELOC_NUMBER (R_860_HAGOT, 0x90) /* hiadj(G) */ + RELOC_NUMBER (R_860_HAGOTOFF, 0xA0) /* hiadj(O) */ + RELOC_NUMBER (R_860_HAPC, 0xB0) /* hiadj((S+A-P) >> 2) */ + RELOC_NUMBER (R_860_HIGH, 0xC0) /* (S+A) >> 16 */ + RELOC_NUMBER (R_860_HIGOT, 0xD0) /* G >> 16 */ + RELOC_NUMBER (R_860_HIGOTOFF, 0xE0) /* O */ +END_RELOC_NUMBERS (R_860_max) + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/i960.h b/external/gpl3/gdb/dist/include/elf/i960.h new file mode 100644 index 000000000000..c319b3226a36 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/i960.h @@ -0,0 +1,37 @@ +/* Intel 960 ELF support for BFD. + Copyright 1999, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_I960_H +#define _ELF_I960_H + +#include "elf/reloc-macros.h" + + +START_RELOC_NUMBERS (elf_i960_reloc_type) + RELOC_NUMBER (R_960_NONE, 0) + RELOC_NUMBER (R_960_12, 1) + RELOC_NUMBER (R_960_32, 2) + RELOC_NUMBER (R_960_IP24, 3) + RELOC_NUMBER (R_960_SUB, 4) + RELOC_NUMBER (R_960_OPTCALL, 5) + RELOC_NUMBER (R_960_OPTCALLX, 6) + RELOC_NUMBER (R_960_OPTCALLXA, 7) +END_RELOC_NUMBERS (R_960_max) + +#endif /* _ELF_I960_H */ diff --git a/external/gpl3/gdb/dist/include/elf/ia64.h b/external/gpl3/gdb/dist/include/elf/ia64.h new file mode 100644 index 000000000000..5b621739426d --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ia64.h @@ -0,0 +1,400 @@ +/* IA-64 ELF support for BFD. + Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2008, 2009, 2010 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_IA64_H +#define _ELF_IA64_H + +/* Bits in the e_flags field of the Elf64_Ehdr: */ + +#define EF_IA_64_MASKOS 0x0000000f /* OS-specific flags. */ +#define EF_IA_64_ARCH 0xff000000 /* Arch. version mask. */ +#define EF_IA_64_ARCHVER_1 (1 << 24) /* Arch. version level 1 compat. */ + +/* ??? These four definitions are not part of the SVR4 ABI. + They were present in David's initial code drop, so it is probable + that they are used by HP/UX. */ +#define EF_IA_64_TRAPNIL (1 << 0) /* Trap NIL pointer dereferences. */ +#define EF_IA_64_EXT (1 << 2) /* Program uses arch. extensions. */ +#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian). */ +#define EFA_IA_64_EAS2_3 0x23000000 /* IA64 EAS 2.3. */ + +#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI. */ +/* Not used yet. */ +#define EF_IA_64_REDUCEDFP (1 << 5) /* Only FP6-FP11 used. */ +#define EF_IA_64_CONS_GP (1 << 6) /* gp as program wide constant. */ +#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptors. */ +/* Not used yet. */ +#define EF_IA_64_ABSOLUTE (1 << 8) /* Load at absolute addresses. */ + +/* OpenVMS speficic. */ +#define EF_IA_64_VMS_COMCOD 0x03 /* Completion code. */ +#define EF_IA_64_VMS_COMCOD_SUCCESS 0 +#define EF_IA_64_VMS_COMCOD_WARNING 1 +#define EF_IA_64_VMS_COMCOD_ERROR 2 +#define EF_IA_64_VMS_COMCOD_ABORT 3 +#define EF_IA_64_VMS_LINKAGES 0x04 /* Contains VMS linkages info. */ + +#define ELF_STRING_ia64_archext ".IA_64.archext" +#define ELF_STRING_ia64_pltoff ".IA_64.pltoff" +#define ELF_STRING_ia64_unwind ".IA_64.unwind" +#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info" +#define ELF_STRING_ia64_unwind_once ".gnu.linkonce.ia64unw." +#define ELF_STRING_ia64_unwind_info_once ".gnu.linkonce.ia64unwi." +/* .IA_64.unwind_hdr is only used by HP-UX. */ +#define ELF_STRING_ia64_unwind_hdr ".IA_64.unwind_hdr" + +/* Bits in the sh_flags field of Elf64_Shdr: */ + +#define SHF_IA_64_SHORT 0x10000000 /* Section near gp. */ +#define SHF_IA_64_NORECOV 0x20000000 /* Spec insns w/o recovery. */ + +#define SHF_IA_64_HP_TLS 0x01000000 /* HP specific TLS flag. */ + +#define SHF_IA_64_VMS_GLOBAL 0x0100000000ULL /* Global for clustering. */ +#define SHF_IA_64_VMS_OVERLAID 0x0200000000ULL /* To be overlaid. */ +#define SHF_IA_64_VMS_SHARED 0x0400000000ULL /* Shared btw processes. */ +#define SHF_IA_64_VMS_VECTOR 0x0800000000ULL /* Priv change mode vect. */ +#define SHF_IA_64_VMS_ALLOC_64BIT 0x1000000000ULL /* Allocate beyond 2GB. */ +#define SHF_IA_64_VMS_PROTECTED 0x2000000000ULL /* Export from sharable. */ + +/* Possible values for sh_type in Elf64_Shdr: */ + +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* Extension bits. */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* Unwind bits. */ +#define SHT_IA_64_LOPSREG (SHT_LOPROC + 0x8000000) +/* ABI says (SHT_LOPROC + 0xfffffff) but I think it's a typo -- this makes sense. */ +#define SHT_IA_64_HIPSREG (SHT_LOPROC + 0x8ffffff) +#define SHT_IA_64_PRIORITY_INIT (SHT_LOPROC + 0x9000000) + +/* SHT_IA_64_HP_OPT_ANOT is only generated by HPUX compilers for its + optimization annotation section. GCC does not generate it but we + want readelf to know what they are. Do not use two capital Ns in + annotate or sed will turn it into 32 or 64 during the build. */ +#define SHT_IA_64_HP_OPT_ANOT 0x60000004 + +/* OpenVMS section types. */ +/* The section contains PC-to-source correlation information for use by the + VMS RTL's traceback facility. */ +#define SHT_IA_64_VMS_TRACE 0x60000000 +/* The section contains routine signature information for use by the + translated image executive. */ +#define SHT_IA_64_VMS_TIE_SIGNATURES 0x60000001 +/* The section contains dwarf-3 information. */ +#define SHT_IA_64_VMS_DEBUG 0x60000002 +/* The section contains the dwarf-3 string table. */ +#define SHT_IA_64_VMS_DEBUG_STR 0x60000003 +/* The section contains linkage information to perform consistency checking + accross object modules. */ +#define SHT_IA_64_VMS_LINKAGES 0x60000004 +/* The section allows the symbol vector in an image to be location through + the section table. */ +#define SHT_IA_64_VMS_SYMBOL_VECTOR 0x60000005 +/* The section contains inter-image fixups. */ +#define SHT_IA_64_VMS_FIXUP 0x60000006 +/* The section contains unmangled name info. */ +#define SHT_IA_64_VMS_DISPLAY_NAME_INFO 0x60000007 + +/* Bits in the p_flags field of Elf64_Phdr: */ + +#define PF_IA_64_NORECOV 0x80000000 + +/* Possible values for p_type in Elf64_Phdr: */ + +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* Arch extension bits, */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* IA64 unwind bits. */ + +/* HP-UX specific values for p_type in Elf64_Phdr. + These values are currently just used to make + readelf more usable on HP-UX. */ + +#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) +#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) +#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) + +/* Possible values for d_tag in Elf64_Dyn: */ + +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) + +/* VMS specific values for d_tag in Elf64_Dyn: */ + +#define DT_IA_64_VMS_SUBTYPE (DT_LOOS + 0) +#define DT_IA_64_VMS_IMGIOCNT (DT_LOOS + 2) +#define DT_IA_64_VMS_LNKFLAGS (DT_LOOS + 8) +#define DT_IA_64_VMS_VIR_MEM_BLK_SIZ (DT_LOOS + 10) +#define DT_IA_64_VMS_IDENT (DT_LOOS + 12) +#define DT_IA_64_VMS_NEEDED_IDENT (DT_LOOS + 16) +#define DT_IA_64_VMS_IMG_RELA_CNT (DT_LOOS + 18) +#define DT_IA_64_VMS_SEG_RELA_CNT (DT_LOOS + 20) +#define DT_IA_64_VMS_FIXUP_RELA_CNT (DT_LOOS + 22) +#define DT_IA_64_VMS_FIXUP_NEEDED (DT_LOOS + 24) +#define DT_IA_64_VMS_SYMVEC_CNT (DT_LOOS + 26) +#define DT_IA_64_VMS_XLATED (DT_LOOS + 30) +#define DT_IA_64_VMS_STACKSIZE (DT_LOOS + 32) +#define DT_IA_64_VMS_UNWINDSZ (DT_LOOS + 34) +#define DT_IA_64_VMS_UNWIND_CODSEG (DT_LOOS + 36) +#define DT_IA_64_VMS_UNWIND_INFOSEG (DT_LOOS + 38) +#define DT_IA_64_VMS_LINKTIME (DT_LOOS + 40) +#define DT_IA_64_VMS_SEG_NO (DT_LOOS + 42) +#define DT_IA_64_VMS_SYMVEC_OFFSET (DT_LOOS + 44) +#define DT_IA_64_VMS_SYMVEC_SEG (DT_LOOS + 46) +#define DT_IA_64_VMS_UNWIND_OFFSET (DT_LOOS + 48) +#define DT_IA_64_VMS_UNWIND_SEG (DT_LOOS + 50) +#define DT_IA_64_VMS_STRTAB_OFFSET (DT_LOOS + 52) +#define DT_IA_64_VMS_SYSVER_OFFSET (DT_LOOS + 54) +#define DT_IA_64_VMS_IMG_RELA_OFF (DT_LOOS + 56) +#define DT_IA_64_VMS_SEG_RELA_OFF (DT_LOOS + 58) +#define DT_IA_64_VMS_FIXUP_RELA_OFF (DT_LOOS + 60) +#define DT_IA_64_VMS_PLTGOT_OFFSET (DT_LOOS + 62) +#define DT_IA_64_VMS_PLTGOT_SEG (DT_LOOS + 64) +#define DT_IA_64_VMS_FPMODE (DT_LOOS + 66) + +/* Values for DT_IA_64_LNKFLAGS. */ +#define VMS_LF_CALL_DEBUG 0x0001 /* Activate and call the debugger. */ +#define VMS_LF_NOP0BUFS 0x0002 /* RMS use of P0 for i/o disabled. */ +#define VMS_LF_P0IMAGE 0x0004 /* Image in P0 space only. */ +#define VMS_LF_MKTHREADS 0x0008 /* Multiple kernel threads enabled. */ +#define VMS_LF_UPCALLS 0x0010 /* Upcalls enabled. */ +#define VMS_LF_IMGSTA 0x0020 /* Use SYS$IMGSTA. */ +#define VMS_LF_INITIALIZE 0x0040 /* Image uses tfradr2. */ +#define VMS_LF_MAIN 0x0080 /* Image uses tfradr3. */ +#define VMS_LF_EXE_INIT 0x0200 /* Image uses tfradr4. */ +#define VMS_LF_TBK_IN_IMG 0x0400 /* Traceback records in image. */ +#define VMS_LF_DBG_IN_IMG 0x0800 /* Debug records in image. */ +#define VMS_LF_TBK_IN_DSF 0x1000 /* Traceback records in DSF. */ +#define VMS_LF_DBG_IN_DSF 0x2000 /* Debug records in DSF. */ +#define VMS_LF_SIGNATURES 0x4000 /* Signatures present. */ +#define VMS_LF_REL_SEG_OFF 0x8000 /* Maintain relative pos of seg. */ + +/* This section only used by HP-UX, The HP linker gives weak symbols + precedence over regular common symbols. We want common to override + weak. Using this common instead of SHN_COMMON does that. */ +#define SHN_IA_64_ANSI_COMMON SHN_LORESERVE + +/* This section is only used by OpenVMS. Symbol is defined in the symbol + vector (only possible for image files). */ +#define SHN_IA_64_VMS_SYMVEC SHN_LOOS + +/* OpenVMS IA64-specific symbol attributes. */ +#define VMS_STO_VISIBILITY 3 /* Alias of the standard field. */ +#define VMS_ST_VISIBILITY(o) ((o) & VMS_STO_VISIBILITY) +#define VMS_STO_FUNC_TYPE 0x30 /* Function type. */ +#define VMS_ST_FUNC_TYPE(o) (((o) & VMS_STO_FUNC_TYPE) >> 4) +# define VMS_SFT_CODE_ADDR 0 /* Symbol value is a code address. */ +# define VMS_SFT_SYMV_IDX 1 /* Symbol value is a symbol vector index. */ +# define VMS_SFT_FD 2 /* Symbol value is a function descriptor. */ +# define VMS_SFT_RESERVE 3 /* Reserved. */ +#define VMS_STO_LINKAGE 0xc0 +#define VMS_ST_LINKAGE(o) (((o) & VMS_STO_LINKAGE) >> 6) +# define VMS_STL_IGNORE 0 /* No associated linkage. */ +# define VMS_STL_RESERVE 1 +# define VMS_STL_STD 2 /* Standard linkage with return value. */ +# define VMS_STL_LNK 3 /* Explicit represented in .vms_linkages. */ + +/* OpenVMS specific fixup and relocation structures. */ + +typedef struct +{ + unsigned char fixup_offset[8]; + unsigned char type[4]; + unsigned char fixup_seg[4]; + unsigned char addend[8]; + unsigned char symvec_index[4]; + unsigned char data_type[4]; +} Elf64_External_VMS_IMAGE_FIXUP; + +typedef struct +{ + unsigned char rela_offset[8]; + unsigned char type[4]; + unsigned char rela_seg[4]; + unsigned char addend[8]; + unsigned char sym_offset[8]; + unsigned char sym_seg[4]; + unsigned char fill_1[4]; +} Elf64_External_VMS_IMAGE_RELA; + +/* Note segments. VMS is special as it uses 64-bit entries. */ + +typedef struct { + unsigned char namesz[8]; /* Size of entry's owner string */ + unsigned char descsz[8]; /* Size of the note descriptor */ + unsigned char type[8]; /* Interpretation of the descriptor */ + char name[1]; /* Start of the name+desc data */ +} Elf64_External_VMS_Note; + +#define NT_VMS_MHD 1 /* Object module name, version, and date/time. */ +#define NT_VMS_LNM 2 /* Language processor name. */ +#define NT_VMS_SRC 3 /* Source files. */ +#define NT_VMS_TITLE 4 /* Title text. */ +#define NT_VMS_EIDC 5 /* Entity ident consistency check. */ +#define NT_VMS_FPMODE 6 /* Whole program floating-point mode. */ +#define NT_VMS_LINKTIME 101 /* Date/time image was linked. */ +#define NT_VMS_IMGNAM 102 /* Image name string. */ +#define NT_VMS_IMGID 103 /* Image ident string. */ +#define NT_VMS_LINKID 104 /* Linker ident string. */ +#define NT_VMS_IMGBID 105 /* Image build ident string. */ +#define NT_VMS_GSTNAM 106 /* Global Symbol Table Name. */ +#define NT_VMS_ORIG_DYN 107 /* Original setting of dynamic data. */ +#define NT_VMS_PATCHTIME 108 /* Date/time of last patch. */ + +/* IA64-specific relocation types: */ + +/* Relocs apply to specific instructions within a bundle. The least + significant 2 bits of the address indicate which instruction in the + bundle the reloc refers to (0=first slot, 1=second slow, 2=third + slot, 3=undefined) and the remaining bits give the address of the + bundle (16 byte aligned). + + The top 5 bits of the reloc code specifies the expression type, the + low 3 bits the format of the data word being relocated. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_ia64_reloc_type) + RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */ + + RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */ + RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */ + RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */ + RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym+add), mov imm64 */ + + RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL60B, 0x48) /* @pcrel(sym+add), brl */ + RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym+add), chk.s */ + RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym+add), fchkf */ + RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB */ + + RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */ + RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */ + + RELOC_NUMBER (R_IA64_LTV32MSB, 0x74) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_LTV32LSB, 0x75) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_LTV64MSB, 0x76) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_LTV64LSB, 0x77) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL21BI, 0x79) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL22, 0x7a) /* @pcrel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_PCREL64I, 0x7b) /* @pcrel(sym+add), imm64 */ + + RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB */ + RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB */ + RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy */ + RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */ + RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */ + + RELOC_NUMBER (R_IA64_TPREL14, 0x91) /* @tprel(sym+add), add imm14 */ + RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* @tprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_TPREL64I, 0x93) /* @tprel(sym+add), add imm64 */ + RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_TPREL22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */ + + RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm22 */ + + RELOC_NUMBER (R_IA64_DTPREL14, 0xb1) /* @dtprel(sym+add), imm14 */ + RELOC_NUMBER (R_IA64_DTPREL22, 0xb2) /* @dtprel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3) /* @dtprel(sym+add), imm64 */ + RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm22 */ + + FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba) + + /* OpenVMS specific relocs. */ + RELOC_NUMBER (R_IA64_VMS_DIR8, 0x70000000) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_DIR16LSB, 0x70000001) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_CALL_SIGNATURE, 0x70000002) + RELOC_NUMBER (R_IA64_VMS_EXECLET_FUNC, 0x70000003) + RELOC_NUMBER (R_IA64_VMS_EXECLET_DATA, 0x70000004) + RELOC_NUMBER (R_IA64_VMS_FIX8, 0x70000005) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_FIX16, 0x70000006) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_FIX32, 0x70000007) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_FIX64, 0x70000008) /* S + A */ + RELOC_NUMBER (R_IA64_VMS_FIXFD, 0x70000009) + RELOC_NUMBER (R_IA64_VMS_ACC_LOAD, 0x7000000a) /* ACC = S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_ADD, 0x7000000b) /* ACC += S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_SUB, 0x7000000c) /* ACC -= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_MUL, 0x7000000d) /* ACC *= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_DIV, 0x7000000e) /* ACC /= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_AND, 0x7000000f) /* ACC &= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_IOR, 0x70000010) /* ACC |= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_EOR, 0x70000011) /* ACC ^= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_ASH, 0x70000012) /* ACC >>= S + A */ + RELOC_NUMBER (R_IA64_VMS_ACC_STO8, 0x70000014) /* ACC */ + RELOC_NUMBER (R_IA64_VMS_ACC_STO16LSH, 0x70000015) /* ACC */ + RELOC_NUMBER (R_IA64_VMS_ACC_STO32LSH, 0x70000016) /* ACC */ + RELOC_NUMBER (R_IA64_VMS_ACC_STO64LSH, 0x70000017) /* ACC */ +END_RELOC_NUMBERS (R_IA64_max) + +#endif /* _ELF_IA64_H */ diff --git a/external/gpl3/gdb/dist/include/elf/internal.h b/external/gpl3/gdb/dist/include/elf/internal.h new file mode 100644 index 000000000000..461503783040 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/internal.h @@ -0,0 +1,360 @@ +/* ELF support for BFD. + Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, + 2003, 2006, 2007, 2008, 2010, 2011 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support, from information published + in "UNIX System V Release 4, Programmers Guide: ANSI C and + Programming Support Tools". + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of ELF support for BFD, and contains the portions + that describe how ELF is represented internally in the BFD library. + I.E. it describes the in-memory representation of ELF. It requires + the elf-common.h file which contains the portions that are common to + both the internal and external representations. */ + +/* NOTE that these structures are not kept in the same order as they appear + in the object file. In some cases they've been reordered for more optimal + packing under various circumstances. */ + +#ifndef _ELF_INTERNAL_H +#define _ELF_INTERNAL_H + +/* Special section indices, which may show up in st_shndx fields, among + other places. */ + +#undef SHN_UNDEF +#undef SHN_LORESERVE +#undef SHN_LOPROC +#undef SHN_HIPROC +#undef SHN_LOOS +#undef SHN_HIOS +#undef SHN_ABS +#undef SHN_COMMON +#undef SHN_XINDEX +#undef SHN_HIRESERVE +#define SHN_UNDEF 0 /* Undefined section reference */ +#define SHN_LORESERVE (-0x100u) /* Begin range of reserved indices */ +#define SHN_LOPROC (-0x100u) /* Begin range of appl-specific */ +#define SHN_HIPROC (-0xE1u) /* End range of appl-specific */ +#define SHN_LOOS (-0xE0u) /* OS specific semantics, lo */ +#define SHN_HIOS (-0xC1u) /* OS specific semantics, hi */ +#define SHN_ABS (-0xFu) /* Associated symbol is absolute */ +#define SHN_COMMON (-0xEu) /* Associated symbol is in common */ +#define SHN_XINDEX (-0x1u) /* Section index is held elsewhere */ +#define SHN_HIRESERVE (-0x1u) /* End range of reserved indices */ +#define SHN_BAD (-0x101u) /* Used internally by bfd */ + +/* ELF Header */ + +#define EI_NIDENT 16 /* Size of e_ident[] */ + +typedef struct elf_internal_ehdr { + unsigned char e_ident[EI_NIDENT]; /* ELF "magic number" */ + bfd_vma e_entry; /* Entry point virtual address */ + bfd_size_type e_phoff; /* Program header table file offset */ + bfd_size_type e_shoff; /* Section header table file offset */ + unsigned long e_version; /* Identifies object file version */ + unsigned long e_flags; /* Processor-specific flags */ + unsigned short e_type; /* Identifies object file type */ + unsigned short e_machine; /* Specifies required architecture */ + unsigned int e_ehsize; /* ELF header size in bytes */ + unsigned int e_phentsize; /* Program header table entry size */ + unsigned int e_phnum; /* Program header table entry count */ + unsigned int e_shentsize; /* Section header table entry size */ + unsigned int e_shnum; /* Section header table entry count */ + unsigned int e_shstrndx; /* Section header string table index */ +} Elf_Internal_Ehdr; + +/* Program header */ + +struct elf_internal_phdr { + unsigned long p_type; /* Identifies program segment type */ + unsigned long p_flags; /* Segment flags */ + bfd_vma p_offset; /* Segment file offset */ + bfd_vma p_vaddr; /* Segment virtual address */ + bfd_vma p_paddr; /* Segment physical address */ + bfd_vma p_filesz; /* Segment size in file */ + bfd_vma p_memsz; /* Segment size in memory */ + bfd_vma p_align; /* Segment alignment, file & memory */ +}; + +typedef struct elf_internal_phdr Elf_Internal_Phdr; + +/* Section header */ + +typedef struct elf_internal_shdr { + unsigned int sh_name; /* Section name, index in string tbl */ + unsigned int sh_type; /* Type of section */ + bfd_vma sh_flags; /* Miscellaneous section attributes */ + bfd_vma sh_addr; /* Section virtual addr at execution */ + file_ptr sh_offset; /* Section file offset */ + bfd_size_type sh_size; /* Size of section in bytes */ + unsigned int sh_link; /* Index of another section */ + unsigned int sh_info; /* Additional section information */ + bfd_vma sh_addralign; /* Section alignment */ + bfd_size_type sh_entsize; /* Entry size if section holds table */ + + /* The internal rep also has some cached info associated with it. */ + asection * bfd_section; /* Associated BFD section. */ + unsigned char *contents; /* Section contents. */ +} Elf_Internal_Shdr; + +/* Symbol table entry */ + +struct elf_internal_sym { + bfd_vma st_value; /* Value of the symbol */ + bfd_vma st_size; /* Associated symbol size */ + unsigned long st_name; /* Symbol name, index in string tbl */ + unsigned char st_info; /* Type and binding attributes */ + unsigned char st_other; /* Visibilty, and target specific */ + unsigned char st_target_internal; /* Internal-only information */ + unsigned int st_shndx; /* Associated section index */ +}; + +typedef struct elf_internal_sym Elf_Internal_Sym; + +/* Note segments */ + +typedef struct elf_internal_note { + unsigned long namesz; /* Size of entry's owner string */ + unsigned long descsz; /* Size of the note descriptor */ + unsigned long type; /* Interpretation of the descriptor */ + char * namedata; /* Start of the name+desc data */ + char * descdata; /* Start of the desc data */ + bfd_vma descpos; /* File offset of the descdata */ +} Elf_Internal_Note; + +/* Relocation Entries */ + +typedef struct elf_internal_rela { + bfd_vma r_offset; /* Location at which to apply the action */ + bfd_vma r_info; /* Index and Type of relocation */ + bfd_vma r_addend; /* Constant addend used to compute value */ +} Elf_Internal_Rela; + +/* dynamic section structure */ + +typedef struct elf_internal_dyn { + /* This needs to support 64-bit values in elf64. */ + bfd_vma d_tag; /* entry tag value */ + union { + /* This needs to support 64-bit values in elf64. */ + bfd_vma d_val; + bfd_vma d_ptr; + } d_un; +} Elf_Internal_Dyn; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct elf_internal_verdef { + unsigned short vd_version; /* Version number of structure. */ + unsigned short vd_flags; /* Flags (VER_FLG_*). */ + unsigned short vd_ndx; /* Version index. */ + unsigned short vd_cnt; /* Number of verdaux entries. */ + unsigned long vd_hash; /* Hash of name. */ + unsigned long vd_aux; /* Offset to verdaux entries. */ + unsigned long vd_next; /* Offset to next verdef. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + bfd *vd_bfd; /* BFD. */ + const char *vd_nodename; /* Version name. */ + struct elf_internal_verdef *vd_nextdef; /* vd_next as pointer. */ + struct elf_internal_verdaux *vd_auxptr; /* vd_aux as pointer. */ + unsigned int vd_exp_refno; /* Used by the linker. */ +} Elf_Internal_Verdef; + +/* This structure appears in a SHT_GNU_verdef section. */ + +typedef struct elf_internal_verdaux { + unsigned long vda_name; /* String table offset of name. */ + unsigned long vda_next; /* Offset to next verdaux. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + const char *vda_nodename; /* vda_name as pointer. */ + struct elf_internal_verdaux *vda_nextptr; /* vda_next as pointer. */ +} Elf_Internal_Verdaux; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct elf_internal_verneed { + unsigned short vn_version; /* Version number of structure. */ + unsigned short vn_cnt; /* Number of vernaux entries. */ + unsigned long vn_file; /* String table offset of library name. */ + unsigned long vn_aux; /* Offset to vernaux entries. */ + unsigned long vn_next; /* Offset to next verneed. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + bfd *vn_bfd; /* BFD. */ + const char *vn_filename; /* vn_file as pointer. */ + struct elf_internal_vernaux *vn_auxptr; /* vn_aux as pointer. */ + struct elf_internal_verneed *vn_nextref; /* vn_nextref as pointer. */ +} Elf_Internal_Verneed; + +/* This structure appears in a SHT_GNU_verneed section. */ + +typedef struct elf_internal_vernaux { + unsigned long vna_hash; /* Hash of dependency name. */ + unsigned short vna_flags; /* Flags (VER_FLG_*). */ + unsigned short vna_other; /* Unused. */ + unsigned long vna_name; /* String table offset to version name. */ + unsigned long vna_next; /* Offset to next vernaux. */ + + /* These fields are set up when BFD reads in the structure. FIXME: + It would be cleaner to store these in a different structure. */ + const char *vna_nodename; /* vna_name as pointer. */ + struct elf_internal_vernaux *vna_nextptr; /* vna_next as pointer. */ +} Elf_Internal_Vernaux; + +/* This structure appears in a SHT_GNU_versym section. This is not a + standard ELF structure; ELF just uses Elf32_Half. */ + +typedef struct elf_internal_versym { + unsigned short vs_vers; +} Elf_Internal_Versym; + +/* Structure for syminfo section. */ +typedef struct +{ + unsigned short int si_boundto; + unsigned short int si_flags; +} Elf_Internal_Syminfo; + +/* This structure appears on the stack and in NT_AUXV core file notes. */ +typedef struct +{ + bfd_vma a_type; + bfd_vma a_val; +} Elf_Internal_Auxv; + + +/* This structure is used to describe how sections should be assigned + to program segments. */ + +struct elf_segment_map +{ + /* Next program segment. */ + struct elf_segment_map *next; + /* Program segment type. */ + unsigned long p_type; + /* Program segment flags. */ + unsigned long p_flags; + /* Program segment physical address. */ + bfd_vma p_paddr; + /* Program segment virtual address offset from section vma. */ + bfd_vma p_vaddr_offset; + /* Program segment alignment. */ + bfd_vma p_align; + /* Segment size in file and memory */ + bfd_vma p_size; + /* Required size of filehdr + phdrs, if non-zero */ + bfd_vma header_size; + /* Whether the p_flags field is valid; if not, the flags are based + on the section flags. */ + unsigned int p_flags_valid : 1; + /* Whether the p_paddr field is valid; if not, the physical address + is based on the section lma values. */ + unsigned int p_paddr_valid : 1; + /* Whether the p_align field is valid; if not, PT_LOAD segment + alignment is based on the default maximum page size. */ + unsigned int p_align_valid : 1; + /* Whether the p_size field is valid; if not, the size are based + on the section sizes. */ + unsigned int p_size_valid : 1; + /* Whether this segment includes the file header. */ + unsigned int includes_filehdr : 1; + /* Whether this segment includes the program headers. */ + unsigned int includes_phdrs : 1; + /* Number of sections (may be 0). */ + unsigned int count; + /* Sections. Actual number of elements is in count field. */ + asection *sections[1]; +}; + +/* .tbss is special. It doesn't contribute memory space to normal + segments and it doesn't take file space in normal segments. */ +#define ELF_TBSS_SPECIAL(sec_hdr, segment) \ + (((sec_hdr)->sh_flags & SHF_TLS) != 0 \ + && (sec_hdr)->sh_type == SHT_NOBITS \ + && (segment)->p_type != PT_TLS) + +#define ELF_SECTION_SIZE(sec_hdr, segment) \ + (ELF_TBSS_SPECIAL(sec_hdr, segment) ? 0 : (sec_hdr)->sh_size) + +/* Decide if the section SEC_HDR is in SEGMENT. If CHECK_VMA, then + VMAs are checked for alloc sections. If STRICT, then a zero size + section won't match at the end of a segment, unless the segment + is also zero size. Regardless of STRICT and CHECK_VMA, zero size + sections won't match at the start or end of PT_DYNAMIC, unless + PT_DYNAMIC is itself zero sized. */ +#define ELF_SECTION_IN_SEGMENT_1(sec_hdr, segment, check_vma, strict) \ + ((/* Only PT_LOAD, PT_GNU_RELRO and PT_TLS segments can contain \ + SHF_TLS sections. */ \ + ((((sec_hdr)->sh_flags & SHF_TLS) != 0) \ + && ((segment)->p_type == PT_TLS \ + || (segment)->p_type == PT_GNU_RELRO \ + || (segment)->p_type == PT_LOAD)) \ + /* PT_TLS segment contains only SHF_TLS sections, PT_PHDR no \ + sections at all. */ \ + || (((sec_hdr)->sh_flags & SHF_TLS) == 0 \ + && (segment)->p_type != PT_TLS \ + && (segment)->p_type != PT_PHDR)) \ + /* Any section besides one of type SHT_NOBITS must have file \ + offsets within the segment. */ \ + && ((sec_hdr)->sh_type == SHT_NOBITS \ + || ((bfd_vma) (sec_hdr)->sh_offset >= (segment)->p_offset \ + && (!(strict) \ + || ((sec_hdr)->sh_offset - (segment)->p_offset \ + <= (segment)->p_filesz - 1)) \ + && (((sec_hdr)->sh_offset - (segment)->p_offset \ + + ELF_SECTION_SIZE(sec_hdr, segment)) \ + <= (segment)->p_filesz))) \ + /* SHF_ALLOC sections must have VMAs within the segment. */ \ + && (!(check_vma) \ + || ((sec_hdr)->sh_flags & SHF_ALLOC) == 0 \ + || ((sec_hdr)->sh_addr >= (segment)->p_vaddr \ + && (!(strict) \ + || ((sec_hdr)->sh_addr - (segment)->p_vaddr \ + <= (segment)->p_memsz - 1)) \ + && (((sec_hdr)->sh_addr - (segment)->p_vaddr \ + + ELF_SECTION_SIZE(sec_hdr, segment)) \ + <= (segment)->p_memsz))) \ + /* No zero size sections at start or end of PT_DYNAMIC. */ \ + && ((segment)->p_type != PT_DYNAMIC \ + || (sec_hdr)->sh_size != 0 \ + || (segment)->p_memsz == 0 \ + || (((sec_hdr)->sh_type == SHT_NOBITS \ + || ((bfd_vma) (sec_hdr)->sh_offset > (segment)->p_offset \ + && ((sec_hdr)->sh_offset - (segment)->p_offset \ + < (segment)->p_filesz))) \ + && (((sec_hdr)->sh_flags & SHF_ALLOC) == 0 \ + || ((sec_hdr)->sh_addr > (segment)->p_vaddr \ + && ((sec_hdr)->sh_addr - (segment)->p_vaddr \ + < (segment)->p_memsz)))))) + +#define ELF_SECTION_IN_SEGMENT(sec_hdr, segment) \ + (ELF_SECTION_IN_SEGMENT_1 (sec_hdr, segment, 1, 0)) + +#define ELF_SECTION_IN_SEGMENT_STRICT(sec_hdr, segment) \ + (ELF_SECTION_IN_SEGMENT_1 (sec_hdr, segment, 1, 1)) + +#endif /* _ELF_INTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/elf/ip2k.h b/external/gpl3/gdb/dist/include/elf/ip2k.h new file mode 100644 index 000000000000..8b4f36ef34fe --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ip2k.h @@ -0,0 +1,62 @@ +/* IP2xxx ELF support for BFD. + Copyright (C) 2000, 2002, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_IP2K_H +#define _ELF_IP2K_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ip2k_reloc_type) + RELOC_NUMBER (R_IP2K_NONE, 0) + RELOC_NUMBER (R_IP2K_16, 1) + RELOC_NUMBER (R_IP2K_32, 2) + RELOC_NUMBER (R_IP2K_FR9, 3) + RELOC_NUMBER (R_IP2K_BANK, 4) + RELOC_NUMBER (R_IP2K_ADDR16CJP, 5) + RELOC_NUMBER (R_IP2K_PAGE3, 6) + RELOC_NUMBER (R_IP2K_LO8DATA, 7) + RELOC_NUMBER (R_IP2K_HI8DATA, 8) + RELOC_NUMBER (R_IP2K_LO8INSN, 9) + RELOC_NUMBER (R_IP2K_HI8INSN, 10) + RELOC_NUMBER (R_IP2K_PC_SKIP, 11) + RELOC_NUMBER (R_IP2K_TEXT, 12) + RELOC_NUMBER (R_IP2K_FR_OFFSET, 13) + RELOC_NUMBER (R_IP2K_EX8DATA, 14) +END_RELOC_NUMBERS(R_IP2K_max) + + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & IP2K_INSN_MASK) == IP2K_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32ip2k.sh'. */ +/* ??? Consider extending the _MASK values to include all the + intermediate bits that must be zero due to the limited physical + memory size on the IP2K. */ + +#define IP2K_DATA_MASK 0xff000000 +#define IP2K_DATA_VALUE 0x01000000 +#define IP2K_INSN_MASK 0xff000000 +#define IP2K_INSN_VALUE 0x02000000 + +/* The location of the memory mapped hardware stack. */ +#define IP2K_STACK_VALUE 0x0f000000 +#define IP2K_STACK_SIZE 0x20 + +#endif /* _ELF_IP2K_H */ diff --git a/external/gpl3/gdb/dist/include/elf/iq2000.h b/external/gpl3/gdb/dist/include/elf/iq2000.h new file mode 100644 index 000000000000..0f8e69714f07 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/iq2000.h @@ -0,0 +1,58 @@ +/* IQ2000 ELF support for BFD. + Copyright (C) 2002, 2003, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_IQ2000_H +#define _ELF_IQ2000_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_iq2000_reloc_type) + RELOC_NUMBER (R_IQ2000_NONE, 0) + RELOC_NUMBER (R_IQ2000_16, 1) + RELOC_NUMBER (R_IQ2000_32, 2) + RELOC_NUMBER (R_IQ2000_26, 3) + RELOC_NUMBER (R_IQ2000_PC16, 4) + RELOC_NUMBER (R_IQ2000_HI16, 5) + RELOC_NUMBER (R_IQ2000_LO16, 6) + RELOC_NUMBER (R_IQ2000_OFFSET_16, 7) + RELOC_NUMBER (R_IQ2000_OFFSET_21, 8) + RELOC_NUMBER (R_IQ2000_UHI16, 9) + RELOC_NUMBER (R_IQ2000_32_DEBUG, 10) + RELOC_NUMBER (R_IQ2000_GNU_VTINHERIT, 200) + RELOC_NUMBER (R_IQ2000_GNU_VTENTRY, 201) +END_RELOC_NUMBERS(R_IQ2000_max) + +#define EF_IQ2000_CPU_IQ2000 0x00000001 /* default */ +#define EF_IQ2000_CPU_IQ10 0x00000002 /* IQ10 */ +#define EF_IQ2000_CPU_MASK 0x00000003 /* specific cpu bits */ +#define EF_IQ2000_ALL_FLAGS (EF_IQ2000_CPU_MASK) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & IQ2000_INSN_MASK) == IQ2000_INSN_VALUE), and similarly + for the data space. */ + +#define IQ2000_DATA_MASK 0x80000000 +#define IQ2000_DATA_VALUE 0x00000000 +#define IQ2000_INSN_MASK 0x80000000 +#define IQ2000_INSN_VALUE 0x80000000 + + +#endif /* _ELF_IQ2000_H */ diff --git a/external/gpl3/gdb/dist/include/elf/lm32.h b/external/gpl3/gdb/dist/include/elf/lm32.h new file mode 100644 index 000000000000..6ed34ec49965 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/lm32.h @@ -0,0 +1,56 @@ +/* Lattice Mico32 ELF support for BFD. + Copyright 2008, 2010 Free Software Foundation, Inc. + Contributed by Jon Beniston + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_LM32_H +#define _ELF_LM32_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_lm32_reloc_type) + RELOC_NUMBER (R_LM32_NONE, 0) + RELOC_NUMBER (R_LM32_8, 1) + RELOC_NUMBER (R_LM32_16, 2) + RELOC_NUMBER (R_LM32_32, 3) + RELOC_NUMBER (R_LM32_HI16, 4) + RELOC_NUMBER (R_LM32_LO16, 5) + RELOC_NUMBER (R_LM32_GPREL16, 6) + RELOC_NUMBER (R_LM32_CALL, 7) + RELOC_NUMBER (R_LM32_BRANCH, 8) + RELOC_NUMBER (R_LM32_GNU_VTINHERIT, 9) + RELOC_NUMBER (R_LM32_GNU_VTENTRY, 10) + RELOC_NUMBER (R_LM32_16_GOT, 11) + RELOC_NUMBER (R_LM32_GOTOFF_HI16, 12) + RELOC_NUMBER (R_LM32_GOTOFF_LO16, 13) + RELOC_NUMBER (R_LM32_COPY, 14) + RELOC_NUMBER (R_LM32_GLOB_DAT, 15) + RELOC_NUMBER (R_LM32_JMP_SLOT, 16) + RELOC_NUMBER (R_LM32_RELATIVE, 17) +END_RELOC_NUMBERS (R_LM32_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_LM32_MACH 0x00000001 + +/* Various CPU types. */ + +#define E_LM32_MACH 0x1 + +#endif /* _ELF_LM32_H */ diff --git a/external/gpl3/gdb/dist/include/elf/m32c.h b/external/gpl3/gdb/dist/include/elf/m32c.h new file mode 100644 index 000000000000..29b80a679cd0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/m32c.h @@ -0,0 +1,67 @@ +/* M32C ELF support for BFD. + Copyright (C) 2004, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_M32C_H +#define _ELF_M32C_H + +#include "elf/reloc-macros.h" + + /* Relocations. */ + START_RELOC_NUMBERS (elf_m32c_reloc_type) + RELOC_NUMBER (R_M32C_NONE, 0) + RELOC_NUMBER (R_M32C_16, 1) + RELOC_NUMBER (R_M32C_24, 2) + RELOC_NUMBER (R_M32C_32, 3) + RELOC_NUMBER (R_M32C_8_PCREL, 4) + RELOC_NUMBER (R_M32C_16_PCREL, 5) + + /* 8 bit unsigned address, used for dsp8[a0] etc */ + RELOC_NUMBER (R_M32C_8, 6) + /* Bits 0..15 of an address, for SMOVF's A0, A1A0, etc. */ + RELOC_NUMBER (R_M32C_LO16, 7) + /* Bits 16..23 of an address, for SMOVF's R1H etc. */ + RELOC_NUMBER (R_M32C_HI8, 8) + /* Bits 16..31 of an address, for LDE's A1A0 etc. */ + RELOC_NUMBER (R_M32C_HI16, 9) + + /* These are relocs we need when relaxing. */ + /* Marks various jump opcodes. */ + RELOC_NUMBER (R_M32C_RL_JUMP, 10) + /* Marks standard one-address form. */ + RELOC_NUMBER (R_M32C_RL_1ADDR, 11) + /* Marks standard two-address form. */ + RELOC_NUMBER (R_M32C_RL_2ADDR, 12) + + END_RELOC_NUMBERS (R_M32C_max) + +#define EF_M32C_CPU_M16C 0x00000075 /* default */ +#define EF_M32C_CPU_M32C 0x00000078 /* m32c */ +#define EF_M32C_CPU_MASK 0x0000007F /* specific cpu bits */ +#define EF_M32C_ALL_FLAGS (EF_M32C_CPU_MASK) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & M16C_INSN_MASK) == M16C_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32m32c.sh'. */ +#define M32C_DATA_MASK 0xffc00000 +#define M32C_DATA_VALUE 0x00000000 +#define M32C_INSN_MASK 0xffc00000 +#define M32C_INSN_VALUE 0x00400000 + +#endif /* _ELF_M32C_H */ diff --git a/external/gpl3/gdb/dist/include/elf/m32r.h b/external/gpl3/gdb/dist/include/elf/m32r.h new file mode 100644 index 000000000000..7e06e3f3146a --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/m32r.h @@ -0,0 +1,123 @@ +/* M32R ELF support for BFD. + Copyright 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_M32R_H +#define _ELF_M32R_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_m32r_reloc_type) + RELOC_NUMBER (R_M32R_NONE, 0) + /* REL relocations */ + RELOC_NUMBER (R_M32R_16, 1) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_32, 2) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_24, 3) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_10_PCREL, 4) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_18_PCREL, 5) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_26_PCREL, 6) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_HI16_ULO, 7) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_HI16_SLO, 8) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_LO16, 9) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_SDA16, 10) /* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */ + RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12) /* For backwards compatibility. */ + + /* RELA relocations */ + RELOC_NUMBER (R_M32R_16_RELA, 33) + RELOC_NUMBER (R_M32R_32_RELA, 34) + RELOC_NUMBER (R_M32R_24_RELA, 35) + RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36) + RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37) + RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38) + RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39) + RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40) + RELOC_NUMBER (R_M32R_LO16_RELA, 41) + RELOC_NUMBER (R_M32R_SDA16_RELA, 42) + RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43) + RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44) + + RELOC_NUMBER (R_M32R_REL32, 45) + + RELOC_NUMBER (R_M32R_GOT24, 48) + RELOC_NUMBER (R_M32R_26_PLTREL, 49) + RELOC_NUMBER (R_M32R_COPY, 50) + RELOC_NUMBER (R_M32R_GLOB_DAT, 51) + RELOC_NUMBER (R_M32R_JMP_SLOT, 52) + RELOC_NUMBER (R_M32R_RELATIVE, 53) + RELOC_NUMBER (R_M32R_GOTOFF, 54) + RELOC_NUMBER (R_M32R_GOTPC24, 55) + RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56) + RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57) + RELOC_NUMBER (R_M32R_GOT16_LO, 58) + RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59) + RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60) + RELOC_NUMBER (R_M32R_GOTPC_LO, 61) + RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62) + RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63) + RELOC_NUMBER (R_M32R_GOTOFF_LO, 64) + +END_RELOC_NUMBERS (R_M32R_max) + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small common symbol. */ +#define SHN_M32R_SCOMMON SHN_LORESERVE + +/* Processor specific section flags. */ + +/* This section contains sufficient relocs to be relaxed. + When relaxing, even relocs of branch instructions the assembler could + complete must be present because relaxing may cause the branch target to + move. */ +#define SHF_M32R_CAN_RELAX 0x10000000 + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Two bit m32r architecture field. */ +#define EF_M32R_ARCH 0x30000000 + +/* m32r code. */ +#define E_M32R_ARCH 0x00000000 +/* m32rx code. */ +#define E_M32RX_ARCH 0x10000000 +/* m32r2 code. */ +#define E_M32R2_ARCH 0x20000000 + +/* 12 bit m32r new instructions field. */ +#define EF_M32R_INST 0x0FFF0000 +/* Parallel instructions. */ +#define E_M32R_HAS_PARALLEL 0x00010000 +/* Hidden instructions for m32rx: + jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz, + sc, snc. */ +#define E_M32R_HAS_HIDDEN_INST 0x00020000 +/* New bit instructions: + clrpsw, setpsw, bset, bclr, btst. */ +#define E_M32R_HAS_BIT_INST 0x00040000 +/* Floating point instructions. */ +#define E_M32R_HAS_FLOAT_INST 0x00080000 + +/* 4 bit m32r ignore to check field. */ +#define EF_M32R_IGNORE 0x0000000F + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/m68hc11.h b/external/gpl3/gdb/dist/include/elf/m68hc11.h new file mode 100644 index 000000000000..ca325d98191f --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/m68hc11.h @@ -0,0 +1,95 @@ +/* m68hc11 & m68hc12 ELF support for BFD. + Copyright 1999, 2000, 2001, 2002, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_M68HC11_H +#define _ELF_M68HC11_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68hc11_reloc_type) + RELOC_NUMBER (R_M68HC11_NONE, 0) + RELOC_NUMBER (R_M68HC11_8, 1) + RELOC_NUMBER (R_M68HC11_HI8, 2) + RELOC_NUMBER (R_M68HC11_LO8, 3) + RELOC_NUMBER (R_M68HC11_PCREL_8, 4) + RELOC_NUMBER (R_M68HC11_16, 5) + RELOC_NUMBER (R_M68HC11_32, 6) + RELOC_NUMBER (R_M68HC11_3B, 7) + RELOC_NUMBER (R_M68HC11_PCREL_16, 8) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9) + RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10) + + RELOC_NUMBER (R_M68HC11_24, 11) + RELOC_NUMBER (R_M68HC11_LO16, 12) + RELOC_NUMBER (R_M68HC11_PAGE, 13) + + /* GNU extension for linker relaxation. + Mark beginning of a jump instruction (any form). */ + RELOC_NUMBER (R_M68HC11_RL_JUMP, 20) + + /* Mark beginning of Gcc relaxation group instruction. */ + RELOC_NUMBER (R_M68HC11_RL_GROUP, 21) +END_RELOC_NUMBERS (R_M68HC11_max) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* ABI identification. */ +#define EF_M68HC11_ABI 0x00000000F + +/* Integers are 32-bit long. */ +#define E_M68HC11_I32 0x000000001 + +/* Doubles are 64-bit long. */ +#define E_M68HC11_F64 0x000000002 + +/* Uses 68HC12 memory banks. */ +#define E_M68HC12_BANKS 0x000000004 + +#define EF_M68HC11_MACH_MASK 0xF0 +#define EF_M68HC11_GENERIC 0x00 /* Generic 68HC12/backward compatibility. */ +#define EF_M68HC12_MACH 0x10 /* 68HC12 microcontroller. */ +#define EF_M68HCS12_MACH 0x20 /* 68HCS12 microcontroller. */ +#define EF_M68HC11_MACH(mach) ((mach) & EF_M68HC11_MACH_MASK) + +/* True if we can merge machines. A generic HC12 can work on any proc + but once we have specific code, merge is not possible. */ +#define EF_M68HC11_CAN_MERGE_MACH(mach1, mach2) \ + ((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \ + || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC) \ + || (EF_M68HC11_MACH (mach2) == EF_M68HC11_GENERIC)) + +#define EF_M68HC11_MERGE_MACH(mach1, mach2) \ + (((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \ + || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC)) ? \ + EF_M68HC11_MACH (mach2) : EF_M68HC11_MACH (mach1)) + + +/* Special values for the st_other field in the symbol table. These + are used for 68HC12 to identify far functions (must be called with + 'call' and returns with 'rtc'). */ +#define STO_M68HC12_FAR 0x80 + +/* Identify interrupt handlers. This is used by the debugger to + correctly compute the stack frame. */ +#define STO_M68HC12_INTERRUPT 0x40 + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/m68k.h b/external/gpl3/gdb/dist/include/elf/m68k.h new file mode 100644 index 000000000000..f6f37ccf43dc --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/m68k.h @@ -0,0 +1,102 @@ +/* MC68k ELF support for BFD. + Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_M68K_H +#define _ELF_M68K_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68k_reloc_type) + RELOC_NUMBER (R_68K_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_68K_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_68K_16, 2) /* Direct 16 bit */ + RELOC_NUMBER (R_68K_8, 3) /* Direct 8 bit */ + RELOC_NUMBER (R_68K_PC32, 4) /* PC relative 32 bit */ + RELOC_NUMBER (R_68K_PC16, 5) /* PC relative 16 bit */ + RELOC_NUMBER (R_68K_PC8, 6) /* PC relative 8 bit */ + RELOC_NUMBER (R_68K_GOT32, 7) /* 32 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT16, 8) /* 16 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT8, 9) /* 8 bit PC relative GOT entry */ + RELOC_NUMBER (R_68K_GOT32O, 10) /* 32 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT16O, 11) /* 16 bit GOT offset */ + RELOC_NUMBER (R_68K_GOT8O, 12) /* 8 bit GOT offset */ + RELOC_NUMBER (R_68K_PLT32, 13) /* 32 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT16, 14) /* 16 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT8, 15) /* 8 bit PC relative PLT address */ + RELOC_NUMBER (R_68K_PLT32O, 16) /* 32 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT16O, 17) /* 16 bit PLT offset */ + RELOC_NUMBER (R_68K_PLT8O, 18) /* 8 bit PLT offset */ + RELOC_NUMBER (R_68K_COPY, 19) /* Copy symbol at runtime */ + RELOC_NUMBER (R_68K_GLOB_DAT, 20) /* Create GOT entry */ + RELOC_NUMBER (R_68K_JMP_SLOT, 21) /* Create PLT entry */ + RELOC_NUMBER (R_68K_RELATIVE, 22) /* Adjust by program base */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_68K_GNU_VTENTRY, 24) + /* TLS static relocations. */ + RELOC_NUMBER (R_68K_TLS_GD32, 25) + RELOC_NUMBER (R_68K_TLS_GD16, 26) + RELOC_NUMBER (R_68K_TLS_GD8, 27) + RELOC_NUMBER (R_68K_TLS_LDM32, 28) + RELOC_NUMBER (R_68K_TLS_LDM16, 29) + RELOC_NUMBER (R_68K_TLS_LDM8, 30) + RELOC_NUMBER (R_68K_TLS_LDO32, 31) + RELOC_NUMBER (R_68K_TLS_LDO16, 32) + RELOC_NUMBER (R_68K_TLS_LDO8, 33) + RELOC_NUMBER (R_68K_TLS_IE32, 34) + RELOC_NUMBER (R_68K_TLS_IE16, 35) + RELOC_NUMBER (R_68K_TLS_IE8, 36) + RELOC_NUMBER (R_68K_TLS_LE32, 37) + RELOC_NUMBER (R_68K_TLS_LE16, 38) + RELOC_NUMBER (R_68K_TLS_LE8, 39) + RELOC_NUMBER (R_68K_TLS_DTPMOD32, 40) + RELOC_NUMBER (R_68K_TLS_DTPREL32, 41) + RELOC_NUMBER (R_68K_TLS_TPREL32, 42) +END_RELOC_NUMBERS (R_68K_max) + +/* We use the top 24 bits to encode information about the + architecture variant. */ +#define EF_M68K_CPU32 0x00810000 +#define EF_M68K_M68000 0x01000000 +#define EF_M68K_CFV4E 0x00008000 +#define EF_M68K_FIDO 0x02000000 +#define EF_M68K_ARCH_MASK \ + (EF_M68K_M68000 | EF_M68K_CPU32 | EF_M68K_CFV4E | EF_M68K_FIDO) + +/* We use the bottom 8 bits to encode information about the + coldfire variant. If we use any of these bits, the top 24 bits are + either 0 or EF_M68K_CFV4E. */ +#define EF_M68K_CF_ISA_MASK 0x0F /* Which ISA */ +#define EF_M68K_CF_ISA_A_NODIV 0x01 /* ISA A except for div */ +#define EF_M68K_CF_ISA_A 0x02 +#define EF_M68K_CF_ISA_A_PLUS 0x03 +#define EF_M68K_CF_ISA_B_NOUSP 0x04 /* ISA_B except for USP */ +#define EF_M68K_CF_ISA_B 0x05 +#define EF_M68K_CF_ISA_C 0x06 +#define EF_M68K_CF_ISA_C_NODIV 0x07 /* ISA C except for div */ +#define EF_M68K_CF_MAC_MASK 0x30 +#define EF_M68K_CF_MAC 0x10 /* MAC */ +#define EF_M68K_CF_EMAC 0x20 /* EMAC */ +#define EF_M68K_CF_EMAC_B 0x30 /* EMAC_B */ +#define EF_M68K_CF_FLOAT 0x40 /* Has float insns */ +#define EF_M68K_CF_MASK 0xFF + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/mcore.h b/external/gpl3/gdb/dist/include/elf/mcore.h new file mode 100644 index 000000000000..2745feebdc44 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mcore.h @@ -0,0 +1,47 @@ +/* Motorola MCore support for BFD. + Copyright 1995, 1999, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MCore ELF ABI. */ +#ifndef _ELF_MORE_H +#define _ELF_MORE_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mcore_reloc_type) + RELOC_NUMBER (R_MCORE_NONE, 0) + RELOC_NUMBER (R_MCORE_ADDR32, 1) + RELOC_NUMBER (R_MCORE_PCRELIMM8BY4, 2) + RELOC_NUMBER (R_MCORE_PCRELIMM11BY2, 3) + RELOC_NUMBER (R_MCORE_PCRELIMM4BY2, 4) + RELOC_NUMBER (R_MCORE_PCREL32, 5) + RELOC_NUMBER (R_MCORE_PCRELJSR_IMM11BY2, 6) + RELOC_NUMBER (R_MCORE_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MCORE_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MCORE_RELATIVE, 9) + RELOC_NUMBER (R_MCORE_COPY, 10) + RELOC_NUMBER (R_MCORE_GLOB_DAT, 11) + RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12) +END_RELOC_NUMBERS (R_MCORE_max) + +/* Section Attributes. */ +#define SHF_MCORE_NOREAD 0x80000000 + +#endif /* _ELF_MCORE_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mep.h b/external/gpl3/gdb/dist/include/elf/mep.h new file mode 100644 index 000000000000..b0e42adc3871 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mep.h @@ -0,0 +1,95 @@ +/* Toshiba MeP ELF support for BFD. + Copyright (C) 2001, 2004, 2005, 2007, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_MEP_H +#define _ELF_MEP_H + +/* Bits in the sh_flags field of Elf32_Shdr: */ + +#define SHF_MEP_VLIW 0x10000000 /* contains vliw code */ + +/* This bit is reserved by BFD for processor specific stuff. Name + it properly so that we can easily stay consistent elsewhere. */ +#define SEC_MEP_VLIW SEC_TIC54X_BLOCK + +#include "elf/reloc-macros.h" + +/* Note: The comments in this file are used by bfd/mep-relocs.pl to + build parts of bfd/elf32-mep.c. */ + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mep_reloc_type) + + /* These two must appear first so that they are not processed by bfd/mep-relocs.pl. */ + RELOC_NUMBER (R_MEP_NONE, 0) + RELOC_NUMBER (R_RELC, 1) + + RELOC_NUMBER (R_MEP_8, 2) /* 7654 3210 U */ + RELOC_NUMBER (R_MEP_16, 3) /* fedc ba98 7654 3210 U */ + RELOC_NUMBER (R_MEP_32, 4) /* vuts rqpo nmlk jihg fedc ba98 7654 3210 U */ + + RELOC_NUMBER (R_MEP_PCREL8A2, 5) /* ---- ---- 7654 321- S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL12A2, 6) /* ---- ba98 7654 321- S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL17A2, 7) /* ---- ---- ---- ---- gfed cba9 8765 4321 S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL24A2, 8) /* ---- -765 4321 ---- nmlk jihg fedc ba98 S PC-REL */ + RELOC_NUMBER (R_MEP_PCABS24A2, 9) /* ---- -765 4321 ---- nmlk jihg fedc ba98 U */ + + RELOC_NUMBER (R_MEP_LOW16, 10) /* ---- ---- ---- ---- fedc ba98 7654 3210 U no-overflow */ + RELOC_NUMBER (R_MEP_HI16U, 11) /* ---- ---- ---- ---- vuts rqpo nmlk jihg U no-overflow */ + RELOC_NUMBER (R_MEP_HI16S, 12) /* ---- ---- ---- ---- vuts rqpo nmlk jihg S no-overflow */ + RELOC_NUMBER (R_MEP_GPREL, 13) /* ---- ---- ---- ---- fedc ba98 7654 3210 S GP-REL*/ + RELOC_NUMBER (R_MEP_TPREL, 14) /* ---- ---- ---- ---- fedc ba98 7654 3210 S TP-REL*/ + + RELOC_NUMBER (R_MEP_TPREL7, 15) /* ---- ---- -654 3210 U TP-REL */ + RELOC_NUMBER (R_MEP_TPREL7A2, 16) /* ---- ---- -654 321- U TP-REL */ + RELOC_NUMBER (R_MEP_TPREL7A4, 17) /* ---- ---- -654 32-- U TP-REL */ + + RELOC_NUMBER (R_MEP_UIMM24, 18) /* ---- ---- 7654 3210 nmlk jihg fedc ba98 U */ + RELOC_NUMBER (R_MEP_ADDR24A4, 19) /* ---- ---- 7654 32-- nmlk jihg fedc ba98 U */ + + RELOC_NUMBER (R_MEP_GNU_VTINHERIT, 20) /* ---- ---- ---- ---- U no-overflow */ + RELOC_NUMBER (R_MEP_GNU_VTENTRY, 21) /* ---- ---- ---- ---- U no-overflow */ + +END_RELOC_NUMBERS(R_MEP_max) + +#define EF_MEP_CPU_MASK 0xff000000 /* specific cpu bits */ +#define EF_MEP_CPU_MEP 0x00000000 /* generic MEP */ +#define EF_MEP_CPU_C2 0x01000000 /* MEP c2 */ +#define EF_MEP_CPU_C3 0x02000000 /* MEP c3 */ +#define EF_MEP_CPU_C4 0x04000000 /* MEP c4 */ +/* 5..7 are reseved */ +#define EF_MEP_CPU_C5 0x08000000 /* MEP c5 */ +#define EF_MEP_CPU_H1 0x10000000 /* MEP h1 */ + +#define EF_MEP_COP_MASK 0x00ff0000 +#define EF_MEP_COP_NONE 0x00000000 +#define EF_MEP_COP_AVC 0x00010000 +#define EF_MEP_COP_AVC2 0x00020000 +#define EF_MEP_COP_FMAX 0x00030000 +/* 4..5 are reserved. */ +#define EF_MEP_COP_IVC2 0x00060000 + +#define EF_MEP_LIBRARY 0x00000100 /* Built as a library */ + +#define EF_MEP_INDEX_MASK 0x000000ff /* Configuration index */ + +#define EF_MEP_ALL_FLAGS 0xffff01ff + +#endif /* _ELF_MEP_H */ diff --git a/external/gpl3/gdb/dist/include/elf/microblaze.h b/external/gpl3/gdb/dist/include/elf/microblaze.h new file mode 100644 index 000000000000..d39223122707 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/microblaze.h @@ -0,0 +1,63 @@ +/* Xilinx MicroBlaze support for BFD. + + Copyright 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* This file holds definitions specific to the MICROBLAZE ELF ABI. */ + +#ifndef _ELF_MICROBLAZE_H +#define _ELF_MICROBLAZE_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_NONE, 0) + RELOC_NUMBER (R_MICROBLAZE_32, 1) + RELOC_NUMBER (R_MICROBLAZE_32_PCREL, 2) + RELOC_NUMBER (R_MICROBLAZE_64_PCREL, 3) + RELOC_NUMBER (R_MICROBLAZE_32_PCREL_LO, 4) + RELOC_NUMBER (R_MICROBLAZE_64, 5) + RELOC_NUMBER (R_MICROBLAZE_32_LO, 6) + RELOC_NUMBER (R_MICROBLAZE_SRO32, 7) + RELOC_NUMBER (R_MICROBLAZE_SRW32, 8) + RELOC_NUMBER (R_MICROBLAZE_64_NONE, 9) + RELOC_NUMBER (R_MICROBLAZE_32_SYM_OP_SYM, 10) + RELOC_NUMBER (R_MICROBLAZE_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_MICROBLAZE_GNU_VTENTRY, 12) + RELOC_NUMBER (R_MICROBLAZE_GOTPC_64, 13) /* PC-relative GOT offset. */ + RELOC_NUMBER (R_MICROBLAZE_GOT_64, 14) /* GOT entry offset. */ + RELOC_NUMBER (R_MICROBLAZE_PLT_64, 15) /* PLT offset (PC-relative). */ + RELOC_NUMBER (R_MICROBLAZE_REL, 16) /* Adjust by program base. */ + RELOC_NUMBER (R_MICROBLAZE_JUMP_SLOT, 17) /* Create PLT entry. */ + RELOC_NUMBER (R_MICROBLAZE_GLOB_DAT, 18) /* Create GOT entry. */ + RELOC_NUMBER (R_MICROBLAZE_GOTOFF_64, 19) /* Offset relative to GOT. */ + RELOC_NUMBER (R_MICROBLAZE_GOTOFF_32, 20) /* Offset relative to GOT. */ + RELOC_NUMBER (R_MICROBLAZE_COPY, 21) /* Runtime copy. */ + +END_RELOC_NUMBERS (R_MICROBLAZE_max) + +/* Global base address names. */ +#define RO_SDA_ANCHOR_NAME "_SDA2_BASE_" +#define RW_SDA_ANCHOR_NAME "_SDA_BASE_" + +/* Section Attributes. */ +#define SHF_MICROBLAZE_NOREAD 0x80000000 + +#endif /* _ELF_MICROBLAZE_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mips.h b/external/gpl3/gdb/dist/include/elf/mips.h new file mode 100644 index 000000000000..c60e8fe24ba3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mips.h @@ -0,0 +1,1049 @@ +/* MIPS ELF support for BFD. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, + 2003, 2004, 2005, 2008, 2009, 2010 + Free Software Foundation, Inc. + + By Ian Lance Taylor, Cygnus Support, , from + information in the System V Application Binary Interface, MIPS + Processor Supplement. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MIPS ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_MIPS_H +#define _ELF_MIPS_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_mips_reloc_type) + RELOC_NUMBER (R_MIPS_NONE, 0) + RELOC_NUMBER (R_MIPS_16, 1) + RELOC_NUMBER (R_MIPS_32, 2) /* In Elf 64: alias R_MIPS_ADD */ + RELOC_NUMBER (R_MIPS_REL32, 3) /* In Elf 64: alias R_MIPS_REL */ + RELOC_NUMBER (R_MIPS_26, 4) + RELOC_NUMBER (R_MIPS_HI16, 5) + RELOC_NUMBER (R_MIPS_LO16, 6) + RELOC_NUMBER (R_MIPS_GPREL16, 7) /* In Elf 64: alias R_MIPS_GPREL */ + RELOC_NUMBER (R_MIPS_LITERAL, 8) + RELOC_NUMBER (R_MIPS_GOT16, 9) /* In Elf 64: alias R_MIPS_GOT */ + RELOC_NUMBER (R_MIPS_PC16, 10) + RELOC_NUMBER (R_MIPS_CALL16, 11) /* In Elf 64: alias R_MIPS_CALL */ + RELOC_NUMBER (R_MIPS_GPREL32, 12) + /* The remaining relocs are defined on Irix, although they are not + in the MIPS ELF ABI. */ + RELOC_NUMBER (R_MIPS_UNUSED1, 13) + RELOC_NUMBER (R_MIPS_UNUSED2, 14) + RELOC_NUMBER (R_MIPS_UNUSED3, 15) + RELOC_NUMBER (R_MIPS_SHIFT5, 16) + RELOC_NUMBER (R_MIPS_SHIFT6, 17) + RELOC_NUMBER (R_MIPS_64, 18) + RELOC_NUMBER (R_MIPS_GOT_DISP, 19) + RELOC_NUMBER (R_MIPS_GOT_PAGE, 20) + RELOC_NUMBER (R_MIPS_GOT_OFST, 21) + RELOC_NUMBER (R_MIPS_GOT_HI16, 22) + RELOC_NUMBER (R_MIPS_GOT_LO16, 23) + RELOC_NUMBER (R_MIPS_SUB, 24) + RELOC_NUMBER (R_MIPS_INSERT_A, 25) + RELOC_NUMBER (R_MIPS_INSERT_B, 26) + RELOC_NUMBER (R_MIPS_DELETE, 27) + RELOC_NUMBER (R_MIPS_HIGHER, 28) + RELOC_NUMBER (R_MIPS_HIGHEST, 29) + RELOC_NUMBER (R_MIPS_CALL_HI16, 30) + RELOC_NUMBER (R_MIPS_CALL_LO16, 31) + RELOC_NUMBER (R_MIPS_SCN_DISP, 32) + RELOC_NUMBER (R_MIPS_REL16, 33) + RELOC_NUMBER (R_MIPS_ADD_IMMEDIATE, 34) + RELOC_NUMBER (R_MIPS_PJUMP, 35) + RELOC_NUMBER (R_MIPS_RELGOT, 36) + RELOC_NUMBER (R_MIPS_JALR, 37) + /* TLS relocations. */ + RELOC_NUMBER (R_MIPS_TLS_DTPMOD32, 38) + RELOC_NUMBER (R_MIPS_TLS_DTPREL32, 39) + RELOC_NUMBER (R_MIPS_TLS_DTPMOD64, 40) + RELOC_NUMBER (R_MIPS_TLS_DTPREL64, 41) + RELOC_NUMBER (R_MIPS_TLS_GD, 42) + RELOC_NUMBER (R_MIPS_TLS_LDM, 43) + RELOC_NUMBER (R_MIPS_TLS_DTPREL_HI16, 44) + RELOC_NUMBER (R_MIPS_TLS_DTPREL_LO16, 45) + RELOC_NUMBER (R_MIPS_TLS_GOTTPREL, 46) + RELOC_NUMBER (R_MIPS_TLS_TPREL32, 47) + RELOC_NUMBER (R_MIPS_TLS_TPREL64, 48) + RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49) + RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50) + RELOC_NUMBER (R_MIPS_GLOB_DAT, 51) + FAKE_RELOC (R_MIPS_max, 52) + /* These relocs are used for the mips16. */ + FAKE_RELOC (R_MIPS16_min, 100) + RELOC_NUMBER (R_MIPS16_26, 100) + RELOC_NUMBER (R_MIPS16_GPREL, 101) + RELOC_NUMBER (R_MIPS16_GOT16, 102) + RELOC_NUMBER (R_MIPS16_CALL16, 103) + RELOC_NUMBER (R_MIPS16_HI16, 104) + RELOC_NUMBER (R_MIPS16_LO16, 105) + FAKE_RELOC (R_MIPS16_max, 106) + /* These relocations are specific to VxWorks. */ + RELOC_NUMBER (R_MIPS_COPY, 126) + RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127) + /* This was a GNU extension used by embedded-PIC. It was co-opted by + mips-linux for exception-handling data. It is no longer used, but + should continue to be supported by the linker for backward + compatibility. (GCC stopped using it in May, 2004.) */ + RELOC_NUMBER (R_MIPS_PC32, 248) + /* FIXME: this relocation is used internally by gas. */ + RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254) +END_RELOC_NUMBERS (R_MIPS_maxext) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* At least one .noreorder directive appears in the source. */ +#define EF_MIPS_NOREORDER 0x00000001 + +/* File contains position independent code. */ +#define EF_MIPS_PIC 0x00000002 + +/* Code in file uses the standard calling sequence for calling + position independent code. */ +#define EF_MIPS_CPIC 0x00000004 + +/* ??? Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a. */ +#define EF_MIPS_XGOT 0x00000008 + +/* Code in file uses UCODE (obsolete) */ +#define EF_MIPS_UCODE 0x00000010 + +/* Code in file uses new ABI (-n32 on Irix 6). */ +#define EF_MIPS_ABI2 0x00000020 + +/* Process the .MIPS.options section first by ld */ +#define EF_MIPS_OPTIONS_FIRST 0x00000080 + +/* Architectural Extensions used by this file */ +#define EF_MIPS_ARCH_ASE 0x0f000000 + +/* Use MDMX multimedia extensions */ +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 + +/* Use MIPS-16 ISA extensions */ +#define EF_MIPS_ARCH_ASE_M16 0x04000000 + +/* Indicates code compiled for a 64-bit machine in 32-bit mode. + (regs are 32-bits wide.) */ +#define EF_MIPS_32BITMODE 0x00000100 + +/* Four bit MIPS architecture field. */ +#define EF_MIPS_ARCH 0xf0000000 + +/* -mips1 code. */ +#define E_MIPS_ARCH_1 0x00000000 + +/* -mips2 code. */ +#define E_MIPS_ARCH_2 0x10000000 + +/* -mips3 code. */ +#define E_MIPS_ARCH_3 0x20000000 + +/* -mips4 code. */ +#define E_MIPS_ARCH_4 0x30000000 + +/* -mips5 code. */ +#define E_MIPS_ARCH_5 0x40000000 + +/* -mips32 code. */ +#define E_MIPS_ARCH_32 0x50000000 + +/* -mips64 code. */ +#define E_MIPS_ARCH_64 0x60000000 + +/* -mips32r2 code. */ +#define E_MIPS_ARCH_32R2 0x70000000 + +/* -mips64r2 code. */ +#define E_MIPS_ARCH_64R2 0x80000000 + +/* The ABI of the file. Also see EF_MIPS_ABI2 above. */ +#define EF_MIPS_ABI 0x0000F000 + +/* The original o32 abi. */ +#define E_MIPS_ABI_O32 0x00001000 + +/* O32 extended to work on 64 bit architectures */ +#define E_MIPS_ABI_O64 0x00002000 + +/* EABI in 32 bit mode */ +#define E_MIPS_ABI_EABI32 0x00003000 + +/* EABI in 64 bit mode */ +#define E_MIPS_ABI_EABI64 0x00004000 + + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MIPS_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MIPS_MACH_3900 0x00810000 +#define E_MIPS_MACH_4010 0x00820000 +#define E_MIPS_MACH_4100 0x00830000 +#define E_MIPS_MACH_4650 0x00850000 +#define E_MIPS_MACH_4120 0x00870000 +#define E_MIPS_MACH_4111 0x00880000 +#define E_MIPS_MACH_SB1 0x008a0000 +#define E_MIPS_MACH_OCTEON 0x008b0000 +#define E_MIPS_MACH_XLR 0x008c0000 +#define E_MIPS_MACH_OCTEON2 0x008d0000 +#define E_MIPS_MACH_5400 0x00910000 +#define E_MIPS_MACH_5500 0x00980000 +#define E_MIPS_MACH_9000 0x00990000 +#define E_MIPS_MACH_LS2E 0x00A00000 +#define E_MIPS_MACH_LS2F 0x00A10000 +#define E_MIPS_MACH_LS3A 0x00A20000 + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Defined and allocated common symbol. Value is virtual address. If + relocated, alignment must be preserved. */ +#define SHN_MIPS_ACOMMON SHN_LORESERVE + +/* Defined and allocated text symbol. Value is virtual address. + Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */ +#define SHN_MIPS_TEXT (SHN_LORESERVE + 1) + +/* Defined and allocated data symbol. Value is virtual address. + Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */ +#define SHN_MIPS_DATA (SHN_LORESERVE + 2) + +/* Small common symbol. */ +#define SHN_MIPS_SCOMMON (SHN_LORESERVE + 3) + +/* Small undefined symbol. */ +#define SHN_MIPS_SUNDEFINED (SHN_LORESERVE + 4) + +/* Processor specific section types. */ + +/* Section contains the set of dynamic shared objects used when + statically linking. */ +#define SHT_MIPS_LIBLIST 0x70000000 + +/* I'm not sure what this is, but it's used on Irix 5. */ +#define SHT_MIPS_MSYM 0x70000001 + +/* Section contains list of symbols whose definitions conflict with + symbols defined in shared objects. */ +#define SHT_MIPS_CONFLICT 0x70000002 + +/* Section contains the global pointer table. */ +#define SHT_MIPS_GPTAB 0x70000003 + +/* Section contains microcode information. The exact format is + unspecified. */ +#define SHT_MIPS_UCODE 0x70000004 + +/* Section contains some sort of debugging information. The exact + format is unspecified. It's probably ECOFF symbols. */ +#define SHT_MIPS_DEBUG 0x70000005 + +/* Section contains register usage information. */ +#define SHT_MIPS_REGINFO 0x70000006 + +/* ??? */ +#define SHT_MIPS_PACKAGE 0x70000007 + +/* ??? */ +#define SHT_MIPS_PACKSYM 0x70000008 + +/* ??? */ +#define SHT_MIPS_RELD 0x70000009 + +/* Section contains interface information. */ +#define SHT_MIPS_IFACE 0x7000000b + +/* Section contains description of contents of another section. */ +#define SHT_MIPS_CONTENT 0x7000000c + +/* Section contains miscellaneous options. */ +#define SHT_MIPS_OPTIONS 0x7000000d + +/* ??? */ +#define SHT_MIPS_SHDR 0x70000010 + +/* ??? */ +#define SHT_MIPS_FDESC 0x70000011 + +/* ??? */ +#define SHT_MIPS_EXTSYM 0x70000012 + +/* ??? */ +#define SHT_MIPS_DENSE 0x70000013 + +/* ??? */ +#define SHT_MIPS_PDESC 0x70000014 + +/* ??? */ +#define SHT_MIPS_LOCSYM 0x70000015 + +/* ??? */ +#define SHT_MIPS_AUXSYM 0x70000016 + +/* ??? */ +#define SHT_MIPS_OPTSYM 0x70000017 + +/* ??? */ +#define SHT_MIPS_LOCSTR 0x70000018 + +/* ??? */ +#define SHT_MIPS_LINE 0x70000019 + +/* ??? */ +#define SHT_MIPS_RFDESC 0x7000001a + +/* Delta C++: symbol table */ +#define SHT_MIPS_DELTASYM 0x7000001b + +/* Delta C++: instance table */ +#define SHT_MIPS_DELTAINST 0x7000001c + +/* Delta C++: class table */ +#define SHT_MIPS_DELTACLASS 0x7000001d + +/* DWARF debugging section. */ +#define SHT_MIPS_DWARF 0x7000001e + +/* Delta C++: declarations */ +#define SHT_MIPS_DELTADECL 0x7000001f + +/* List of libraries the binary depends on. Includes a time stamp, version + number. */ +#define SHT_MIPS_SYMBOL_LIB 0x70000020 + +/* Events section. */ +#define SHT_MIPS_EVENTS 0x70000021 + +/* ??? */ +#define SHT_MIPS_TRANSLATE 0x70000022 + +/* Special pixie sections */ +#define SHT_MIPS_PIXIE 0x70000023 + +/* Address translation table (for debug info) */ +#define SHT_MIPS_XLATE 0x70000024 + +/* SGI internal address translation table (for debug info) */ +#define SHT_MIPS_XLATE_DEBUG 0x70000025 + +/* Intermediate code */ +#define SHT_MIPS_WHIRL 0x70000026 + +/* C++ exception handling region info */ +#define SHT_MIPS_EH_REGION 0x70000027 + +/* Obsolete address translation table (for debug info) */ +#define SHT_MIPS_XLATE_OLD 0x70000028 + +/* Runtime procedure descriptor table exception information (ucode) ??? */ +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + + +/* A section of type SHT_MIPS_LIBLIST contains an array of the + following structure. The sh_link field is the section index of the + string table. The sh_info field is the number of entries in the + section. */ +typedef struct +{ + /* String table index for name of shared object. */ + unsigned long l_name; + /* Time stamp. */ + unsigned long l_time_stamp; + /* Checksum of symbol names and common sizes. */ + unsigned long l_checksum; + /* String table index for version. */ + unsigned long l_version; + /* Flags. */ + unsigned long l_flags; +} Elf32_Lib; + +/* The external version of Elf32_Lib. */ +typedef struct +{ + unsigned char l_name[4]; + unsigned char l_time_stamp[4]; + unsigned char l_checksum[4]; + unsigned char l_version[4]; + unsigned char l_flags[4]; +} Elf32_External_Lib; + +/* The l_flags field of an Elf32_Lib structure may contain the + following flags. */ + +/* Require an exact match at runtime. */ +#define LL_EXACT_MATCH 0x00000001 + +/* Ignore version incompatibilities at runtime. */ +#define LL_IGNORE_INT_VER 0x00000002 + +/* Require matching minor version number. */ +#define LL_REQUIRE_MINOR 0x00000004 + +/* ??? */ +#define LL_EXPORTS 0x00000008 + +/* Delay loading of this library until really needed. */ +#define LL_DELAY_LOAD 0x00000010 + +/* ??? Delta C++ stuff ??? */ +#define LL_DELTA 0x00000020 + + +/* A section of type SHT_MIPS_CONFLICT is an array of indices into the + .dynsym section. Each element has the following type. */ +typedef unsigned long Elf32_Conflict; +typedef unsigned char Elf32_External_Conflict[4]; + +typedef unsigned long Elf64_Conflict; +typedef unsigned char Elf64_External_Conflict[8]; + +/* A section of type SHT_MIPS_GPTAB contains information about how + much GP space would be required for different -G arguments. This + information is only used so that the linker can provide informative + suggestions as to the best -G value to use. The sh_info field is + the index of the section for which this information applies. The + contents of the section are an array of the following union. The + first element uses the gt_header field. The remaining elements use + the gt_entry field. */ +typedef union +{ + struct + { + /* -G value actually used for this object file. */ + unsigned long gt_current_g_value; + /* Unused. */ + unsigned long gt_unused; + } gt_header; + struct + { + /* If this -G argument has been used... */ + unsigned long gt_g_value; + /* ...this many GP section bytes would be required. */ + unsigned long gt_bytes; + } gt_entry; +} Elf32_gptab; + +/* The external version of Elf32_gptab. */ + +typedef union +{ + struct + { + unsigned char gt_current_g_value[4]; + unsigned char gt_unused[4]; + } gt_header; + struct + { + unsigned char gt_g_value[4]; + unsigned char gt_bytes[4]; + } gt_entry; +} Elf32_External_gptab; + +/* A section of type SHT_MIPS_REGINFO contains the following + structure. */ +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + long ri_gp_value; +} Elf32_RegInfo; + +/* The external version of the Elf_RegInfo structure. */ +typedef struct +{ + unsigned char ri_gprmask[4]; + unsigned char ri_cprmask[4][4]; + unsigned char ri_gp_value[4]; +} Elf32_External_RegInfo; + +/* MIPS ELF .reginfo swapping routines. */ +extern void bfd_mips_elf32_swap_reginfo_in + (bfd *, const Elf32_External_RegInfo *, Elf32_RegInfo *); +extern void bfd_mips_elf32_swap_reginfo_out + (bfd *, const Elf32_RegInfo *, Elf32_External_RegInfo *); + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_MIPS_GPREL 0x10000000 + +/* This section should be merged. */ +#define SHF_MIPS_MERGE 0x20000000 + +/* This section contains address data of size implied by section + element size. */ +#define SHF_MIPS_ADDR 0x40000000 + +/* This section contains string data. */ +#define SHF_MIPS_STRING 0x80000000 + +/* This section may not be stripped. */ +#define SHF_MIPS_NOSTRIP 0x08000000 + +/* This section is local to threads. */ +#define SHF_MIPS_LOCAL 0x04000000 + +/* Linker should generate implicit weak names for this section. */ +#define SHF_MIPS_NAMES 0x02000000 + +/* Section contais text/data which may be replicated in other sections. + Linker should retain only one copy. */ +#define SHF_MIPS_NODUPES 0x01000000 + +/* Processor specific program header types. */ + +/* Register usage information. Identifies one .reginfo section. */ +#define PT_MIPS_REGINFO 0x70000000 + +/* Runtime procedure table. */ +#define PT_MIPS_RTPROC 0x70000001 + +/* .MIPS.options section. */ +#define PT_MIPS_OPTIONS 0x70000002 + +/* Processor specific dynamic array tags. */ + +/* 32 bit version number for runtime linker interface. */ +#define DT_MIPS_RLD_VERSION 0x70000001 + +/* Time stamp. */ +#define DT_MIPS_TIME_STAMP 0x70000002 + +/* Checksum of external strings and common sizes. */ +#define DT_MIPS_ICHECKSUM 0x70000003 + +/* Index of version string in string table. */ +#define DT_MIPS_IVERSION 0x70000004 + +/* 32 bits of flags. */ +#define DT_MIPS_FLAGS 0x70000005 + +/* Base address of the segment. */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 + +/* ??? */ +#define DT_MIPS_MSYM 0x70000007 + +/* Address of .conflict section. */ +#define DT_MIPS_CONFLICT 0x70000008 + +/* Address of .liblist section. */ +#define DT_MIPS_LIBLIST 0x70000009 + +/* Number of local global offset table entries. */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a + +/* Number of entries in the .conflict section. */ +#define DT_MIPS_CONFLICTNO 0x7000000b + +/* Number of entries in the .liblist section. */ +#define DT_MIPS_LIBLISTNO 0x70000010 + +/* Number of entries in the .dynsym section. */ +#define DT_MIPS_SYMTABNO 0x70000011 + +/* Index of first external dynamic symbol not referenced locally. */ +#define DT_MIPS_UNREFEXTNO 0x70000012 + +/* Index of first dynamic symbol in global offset table. */ +#define DT_MIPS_GOTSYM 0x70000013 + +/* Number of page table entries in global offset table. */ +#define DT_MIPS_HIPAGENO 0x70000014 + +/* Address of run time loader map, used for debugging. */ +#define DT_MIPS_RLD_MAP 0x70000016 + +/* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 + +/* Number of entries in DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 + +/* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 + +/* Number of entries in DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a + +/* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b + +/* Number of entries in DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c + +/* Delta symbols that Delta relocations refer to. */ +#define DT_MIPS_DELTA_SYM 0x7000001d + +/* Number of entries in DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e + +/* Delta symbols that hold class declarations. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 + +/* Number of entries in DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 + +/* Flags indicating information about C++ flavor. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 + +/* Pixie information (???). */ +#define DT_MIPS_PIXIE_INIT 0x70000023 + +/* Address of .MIPS.symlib */ +#define DT_MIPS_SYMBOL_LIB 0x70000024 + +/* The GOT index of the first PTE for a segment */ +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 + +/* The GOT index of the first PTE for a local symbol */ +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 + +/* The GOT index of the first PTE for a hidden symbol */ +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 + +/* The GOT index of the first PTE for a protected symbol */ +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 + +/* Address of `.MIPS.options'. */ +#define DT_MIPS_OPTIONS 0x70000029 + +/* Address of `.interface'. */ +#define DT_MIPS_INTERFACE 0x7000002a + +/* ??? */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b + +/* Size of the .interface section. */ +#define DT_MIPS_INTERFACE_SIZE 0x7000002c + +/* Size of rld_text_resolve function stored in the GOT. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d + +/* Default suffix of DSO to be added by rld on dlopen() calls. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e + +/* Size of compact relocation section (O32). */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f + +/* GP value for auxiliary GOTs. */ +#define DT_MIPS_GP_VALUE 0x70000030 + +/* Address of auxiliary .dynamic. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 + +/* Address of the base of the PLTGOT. */ +#define DT_MIPS_PLTGOT 0x70000032 + +/* Points to the base of a writable PLT. */ +#define DT_MIPS_RWPLT 0x70000034 + +/* Flags which may appear in a DT_MIPS_FLAGS entry. */ + +/* No flags. */ +#define RHF_NONE 0x00000000 + +/* Uses shortcut pointers. */ +#define RHF_QUICKSTART 0x00000001 + +/* Hash size is not a power of two. */ +#define RHF_NOTPOT 0x00000002 + +/* Ignore LD_LIBRARY_PATH. */ +#define RHS_NO_LIBRARY_REPLACEMENT 0x00000004 + +/* DSO address may not be relocated. */ +#define RHF_NO_MOVE 0x00000008 + +/* SGI specific features. */ +#define RHF_SGI_ONLY 0x00000010 + +/* Guarantee that .init will finish executing before any non-init + code in DSO is called. */ +#define RHF_GUARANTEE_INIT 0x00000020 + +/* Contains Delta C++ code. */ +#define RHF_DELTA_C_PLUS_PLUS 0x00000040 + +/* Guarantee that .init will start executing before any non-init + code in DSO is called. */ +#define RHF_GUARANTEE_START_INIT 0x00000080 + +/* Generated by pixie. */ +#define RHF_PIXIE 0x00000100 + +/* Delay-load DSO by default. */ +#define RHF_DEFAULT_DELAY_LOAD 0x00000200 + +/* Object may be requickstarted */ +#define RHF_REQUICKSTART 0x00000400 + +/* Object has been requickstarted */ +#define RHF_REQUICKSTARTED 0x00000800 + +/* Generated by cord. */ +#define RHF_CORD 0x00001000 + +/* Object contains no unresolved undef symbols. */ +#define RHF_NO_UNRES_UNDEF 0x00002000 + +/* Symbol table is in a safe order. */ +#define RHF_RLD_ORDER_SAFE 0x00004000 + +/* Special values for the st_other field in the symbol table. These + are used in an Irix 5 dynamic symbol table. */ + +#define STO_DEFAULT STV_DEFAULT +#define STO_INTERNAL STV_INTERNAL +#define STO_HIDDEN STV_HIDDEN +#define STO_PROTECTED STV_PROTECTED + +/* The MIPS psABI was updated in 2008 with support for PLTs and copy + relocs. There are therefore two types of nonzero SHN_UNDEF functions: + PLT entries and traditional MIPS lazy binding stubs. We mark the former + with STO_MIPS_PLT to distinguish them from the latter. */ +#define STO_MIPS_PLT 0x8 + +/* This value is used to mark PIC functions in an object that mixes + PIC and non-PIC. */ +#define STO_MIPS_PIC 0x20 +#define ELF_ST_IS_MIPS_PIC(OTHER) \ + (((OTHER) & ~ELF_ST_VISIBILITY (-1)) == STO_MIPS_PIC) +#define ELF_ST_SET_MIPS_PIC(OTHER) \ + (STO_MIPS_PIC | ELF_ST_VISIBILITY (OTHER)) + +/* This value is used for a mips16 .text symbol. */ +#define STO_MIPS16 0xf0 +#define ELF_ST_IS_MIPS16(OTHER) (((OTHER) & 0xf0) == STO_MIPS16) +#define ELF_ST_SET_MIPS16(OTHER) (((OTHER) & ~0xf0) | STO_MIPS16) + +/* This bit is used on Irix to indicate a symbol whose definition + is optional - if, at final link time, it cannot be found, no + error message should be produced. */ +#define STO_OPTIONAL (1 << 2) +/* A macro to examine the STO_OPTIONAL bit. */ +#define ELF_MIPS_IS_OPTIONAL(other) ((other) & STO_OPTIONAL) + +/* The 64-bit MIPS ELF ABI uses an unusual reloc format. Each + relocation entry specifies up to three actual relocations, all at + the same address. The first relocation which required a symbol + uses the symbol in the r_sym field. The second relocation which + requires a symbol uses the symbol in the r_ssym field. If all + three relocations require a symbol, the third one uses a zero + value. */ + +/* An entry in a 64 bit SHT_REL section. */ + +typedef struct +{ + /* Address of relocation. */ + unsigned char r_offset[8]; + /* Symbol index. */ + unsigned char r_sym[4]; + /* Special symbol. */ + unsigned char r_ssym[1]; + /* Third relocation. */ + unsigned char r_type3[1]; + /* Second relocation. */ + unsigned char r_type2[1]; + /* First relocation. */ + unsigned char r_type[1]; +} Elf64_Mips_External_Rel; + +typedef struct +{ + /* Address of relocation. */ + bfd_vma r_offset; + /* Symbol index. */ + unsigned long r_sym; + /* Special symbol. */ + unsigned char r_ssym; + /* Third relocation. */ + unsigned char r_type3; + /* Second relocation. */ + unsigned char r_type2; + /* First relocation. */ + unsigned char r_type; +} Elf64_Mips_Internal_Rel; + +/* An entry in a 64 bit SHT_RELA section. */ + +typedef struct +{ + /* Address of relocation. */ + unsigned char r_offset[8]; + /* Symbol index. */ + unsigned char r_sym[4]; + /* Special symbol. */ + unsigned char r_ssym[1]; + /* Third relocation. */ + unsigned char r_type3[1]; + /* Second relocation. */ + unsigned char r_type2[1]; + /* First relocation. */ + unsigned char r_type[1]; + /* Addend. */ + unsigned char r_addend[8]; +} Elf64_Mips_External_Rela; + +typedef struct +{ + /* Address of relocation. */ + bfd_vma r_offset; + /* Symbol index. */ + unsigned long r_sym; + /* Special symbol. */ + unsigned char r_ssym; + /* Third relocation. */ + unsigned char r_type3; + /* Second relocation. */ + unsigned char r_type2; + /* First relocation. */ + unsigned char r_type; + /* Addend. */ + bfd_signed_vma r_addend; +} Elf64_Mips_Internal_Rela; + +/* MIPS ELF 64 relocation info access macros. */ +#define ELF64_MIPS_R_SSYM(i) (((i) >> 24) & 0xff) +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff) +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff) +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff) + +/* Values found in the r_ssym field of a relocation entry. */ + +/* No relocation. */ +#define RSS_UNDEF 0 + +/* Value of GP. */ +#define RSS_GP 1 + +/* Value of GP in object being relocated. */ +#define RSS_GP0 2 + +/* Address of location being relocated. */ +#define RSS_LOC 3 + +/* A SHT_MIPS_OPTIONS section contains a series of options, each of + which starts with this header. */ + +typedef struct +{ + /* Type of option. */ + unsigned char kind[1]; + /* Size of option descriptor, including header. */ + unsigned char size[1]; + /* Section index of affected section, or 0 for global option. */ + unsigned char section[2]; + /* Information specific to this kind of option. */ + unsigned char info[4]; +} Elf_External_Options; + +typedef struct +{ + /* Type of option. */ + unsigned char kind; + /* Size of option descriptor, including header. */ + unsigned char size; + /* Section index of affected section, or 0 for global option. */ + unsigned short section; + /* Information specific to this kind of option. */ + unsigned long info; +} Elf_Internal_Options; + +/* MIPS ELF option header swapping routines. */ +extern void bfd_mips_elf_swap_options_in + (bfd *, const Elf_External_Options *, Elf_Internal_Options *); +extern void bfd_mips_elf_swap_options_out + (bfd *, const Elf_Internal_Options *, Elf_External_Options *); + +/* Values which may appear in the kind field of an Elf_Options + structure. */ + +/* Undefined. */ +#define ODK_NULL 0 + +/* Register usage and GP value. */ +#define ODK_REGINFO 1 + +/* Exception processing information. */ +#define ODK_EXCEPTIONS 2 + +/* Section padding information. */ +#define ODK_PAD 3 + +/* Hardware workarounds performed. */ +#define ODK_HWPATCH 4 + +/* Fill value used by the linker. */ +#define ODK_FILL 5 + +/* Reserved space for desktop tools. */ +#define ODK_TAGS 6 + +/* Hardware workarounds, AND bits when merging. */ +#define ODK_HWAND 7 + +/* Hardware workarounds, OR bits when merging. */ +#define ODK_HWOR 8 + +/* GP group to use for text/data sections. */ +#define ODK_GP_GROUP 9 + +/* ID information. */ +#define ODK_IDENT 10 + +/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_RegInfo + structure. In the 64 bit ABI, it is the following structure. The + info field of the options header is not used. */ + +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned char ri_gprmask[4]; + /* Padding. */ + unsigned char ri_pad[4]; + /* Mask of co-processor registers used. */ + unsigned char ri_cprmask[4][4]; + /* GP register value for this object file. */ + unsigned char ri_gp_value[8]; +} Elf64_External_RegInfo; + +typedef struct +{ + /* Mask of general purpose registers used. */ + unsigned long ri_gprmask; + /* Padding. */ + unsigned long ri_pad; + /* Mask of co-processor registers used. */ + unsigned long ri_cprmask[4]; + /* GP register value for this object file. */ + bfd_vma ri_gp_value; +} Elf64_Internal_RegInfo; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned char ms_hash_value[4]; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned char ms_info[4]; +} Elf32_External_Msym; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned long ms_hash_value; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned long ms_info; +} Elf32_Internal_Msym; + +#define ELF32_MS_REL_INDEX(i) ((i) >> 8) +#define ELF32_MS_FLAGS(i) (i) & 0xff) +#define ELF32_MS_INFO(r, f) (((r) << 8) + ((f) & 0xff)) + +/* MIPS ELF reginfo swapping routines. */ +extern void bfd_mips_elf64_swap_reginfo_in + (bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *); +extern void bfd_mips_elf64_swap_reginfo_out + (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); + +/* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ +#define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ +#define OEX_PAGE0 0x10000 /* Page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode. */ +#define OEX_FPDBUG 0x40000 /* Force precise floating-point + exceptions (debug mode). */ +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults. */ + +/* Masks of the FP exceptions for OEX_FPU_MIN and OEX_FPU_MAX. */ +#define OEX_FPU_INVAL 0x10 /* Invalid operation exception. */ +#define OEX_FPU_DIV0 0x08 /* Division by zero exception. */ +#define OEX_FPU_OFLO 0x04 /* Overflow exception. */ +#define OEX_FPU_UFLO 0x02 /* Underflow exception. */ +#define OEX_FPU_INEX 0x01 /* Inexact exception. */ + +/* Masks for the info word of an ODK_PAD descriptor. */ +#define OPAD_PREFIX 0x01 +#define OPAD_POSTFIX 0x02 +#define OPAD_SYMBOL 0x04 + +/* Masks for the info word of an ODK_HWPATCH descriptor. */ +#define OHW_R4KEOP 0x00000001 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x00000002 /* May need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x00000004 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x00000008 /* R5000 cvt.[ds].l bug + (clean == 1). */ +#define OHW_R10KLDL 0x00000010 /* Needs R10K misaligned + load patch. */ + +/* Masks for the info word of an ODK_IDENT/ODK_GP_GROUP descriptor. */ +#define OGP_GROUP 0x0000ffff /* GP group number. */ +#define OGP_SELF 0xffff0000 /* Self-contained GP groups. */ + +/* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA0_R4KEOP_CLEAN 0x00000002 + + +/* Object attribute tags. */ +enum +{ + /* 0-3 are generic. */ + Tag_GNU_MIPS_ABI_FP = 4, /* Value 1 for hard-float -mdouble-float, 2 + for hard-float -msingle-float, 3 for + soft-float, 4 for -mips32r2 -mfp64; 0 for + not tagged or not using any ABIs affected + by the differences. */ +}; + +#endif /* _ELF_MIPS_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mmix.h b/external/gpl3/gdb/dist/include/elf/mmix.h new file mode 100644 index 000000000000..6d15f7ae421c --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mmix.h @@ -0,0 +1,173 @@ +/* MMIX support for BFD. + Copyright 2001, 2002, 2003, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MMIX ELF ABI. */ + +#ifndef ELF_MMIX_H +#define ELF_MMIX_H + +#include "elf/reloc-macros.h" + +/* Relocations. See the reloc table in bfd/elf64-mmix.c for details. */ +START_RELOC_NUMBERS (elf_mmix_reloc_type) + RELOC_NUMBER (R_MMIX_NONE, 0) + + /* Standard absolute relocations. */ + RELOC_NUMBER (R_MMIX_8, 1) + RELOC_NUMBER (R_MMIX_16, 2) + RELOC_NUMBER (R_MMIX_24, 3) + RELOC_NUMBER (R_MMIX_32, 4) + RELOC_NUMBER (R_MMIX_64, 5) + + /* Standard relative relocations. */ + RELOC_NUMBER (R_MMIX_PC_8, 6) + RELOC_NUMBER (R_MMIX_PC_16, 7) + RELOC_NUMBER (R_MMIX_PC_24, 8) + RELOC_NUMBER (R_MMIX_PC_32, 9) + RELOC_NUMBER (R_MMIX_PC_64, 10) + + /* GNU extensions for C++ vtables. */ + RELOC_NUMBER (R_MMIX_GNU_VTINHERIT, 11) + RELOC_NUMBER (R_MMIX_GNU_VTENTRY, 12) + + /* A GETA instruction. */ + RELOC_NUMBER (R_MMIX_GETA, 13) + RELOC_NUMBER (R_MMIX_GETA_1, 14) + RELOC_NUMBER (R_MMIX_GETA_2, 15) + RELOC_NUMBER (R_MMIX_GETA_3, 16) + + /* A conditional branch instruction. */ + RELOC_NUMBER (R_MMIX_CBRANCH, 17) + RELOC_NUMBER (R_MMIX_CBRANCH_J, 18) + RELOC_NUMBER (R_MMIX_CBRANCH_1, 19) + RELOC_NUMBER (R_MMIX_CBRANCH_2, 20) + RELOC_NUMBER (R_MMIX_CBRANCH_3, 21) + + /* A PUSHJ instruction. */ + RELOC_NUMBER (R_MMIX_PUSHJ, 22) + RELOC_NUMBER (R_MMIX_PUSHJ_1, 23) + RELOC_NUMBER (R_MMIX_PUSHJ_2, 24) + RELOC_NUMBER (R_MMIX_PUSHJ_3, 25) + + /* A JMP instruction. */ + RELOC_NUMBER (R_MMIX_JMP, 26) + RELOC_NUMBER (R_MMIX_JMP_1, 27) + RELOC_NUMBER (R_MMIX_JMP_2, 28) + RELOC_NUMBER (R_MMIX_JMP_3, 29) + + /* A relative address such as in a GETA or a branch. */ + RELOC_NUMBER (R_MMIX_ADDR19, 30) + + /* A relative address such as in a JMP (only). */ + RELOC_NUMBER (R_MMIX_ADDR27, 31) + + /* A general register or a number 0..255. */ + RELOC_NUMBER (R_MMIX_REG_OR_BYTE, 32) + + /* A general register. */ + RELOC_NUMBER (R_MMIX_REG, 33) + + /* A global register and an offset, the global register (allocated at + link time) contents plus the offset made equivalent to the relocation + expression at link time. The relocation must point at the Y field of + an instruction. */ + RELOC_NUMBER (R_MMIX_BASE_PLUS_OFFSET, 34) + + /* A LOCAL assertion. */ + RELOC_NUMBER (R_MMIX_LOCAL, 35) + + /* A PUSHJ instruction, generating a stub if it does not reach. */ + RELOC_NUMBER (R_MMIX_PUSHJ_STUBBABLE, 36) +END_RELOC_NUMBERS (R_MMIX_max) + + +/* Section Attributes. */ +/* A section containing necessary information for relaxation. */ +#define SHF_MMIX_CANRELAX 0x80000000 + +/* Symbol attributes. */ +/* A symbol with this section-index is a register. */ +#define SHN_REGISTER SHN_LOPROC + +/* This section holds contents for each initialized register, at VMA + regno*8. A symbol relative to this section will be transformed to an + absolute symbol with the value corresponding to the register number at + final link time. A symbol with a value outside the inclusive range + 32*8 .. 254*8 is an error. It is highly recommended to only use an + upper bound of 253*8 or lower as specified in the (currently + unspecified) ABI. */ +#define MMIX_REG_CONTENTS_SECTION_NAME ".MMIX.reg_contents" + +/* At link time, a section by this name is created, expected to be + included in MMIX_REG_CONTENTS_SECTION_NAME in the output. */ +#define MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME \ + ".MMIX.reg_contents.linker_allocated" + +/* This is a faked section holding symbols with SHN_REGISTER. Don't + confuse it with MMIX_REG_CONTENTS_SECTION_NAME; this one has no + contents, just values. It is an error for a value in this section to + be outside the range 32..255 and it must never become an actual section + in an object file. */ +#define MMIX_REG_SECTION_NAME "*REG*" + +/* Appended with a number N=0..65535, this is a representation of the + mmixal "BSPEC N" ... "ESPEC" directive pair; the contents go into an + ELF section by name ".MMIX.spec_data.N". */ +#define MMIX_OTHER_SPEC_SECTION_PREFIX ".MMIX.spec_data." + +/* A section SECNAME is noted to start at "__.MMIX.start.SECNAME" by the + presence of this symbol. Currently only implemented for ".text" + through the symbol "__.MMIX.start..text". */ +#define MMIX_LOC_SECTION_START_SYMBOL_PREFIX "__.MMIX.start." + +/* This symbol is always a function. */ +#define MMIX_START_SYMBOL_NAME "Main" + + +/* We smuggle in a few MMO specifics here. We don't make a specific MMO + file, since we can't reasonably support MMO without ELF; we have to + include this file anyway. */ + +#define MMO_TEXT_SECTION_NAME ".text" +#define MMO_DATA_SECTION_NAME ".data" + +/* A definition for the flags we put in spec data in files. A copy of our + own of some flags to keep immune to BFD flag changes. See section.c of + 2001-07-18 for flag documentation. */ +#define MMO_SEC_ALLOC 0x001 +#define MMO_SEC_LOAD 0x002 +#define MMO_SEC_RELOC 0x004 +#define MMO_SEC_READONLY 0x010 +#define MMO_SEC_CODE 0x020 +#define MMO_SEC_DATA 0x040 +#define MMO_SEC_NEVER_LOAD 0x400 +#define MMO_SEC_IS_COMMON 0x8000 +#define MMO_SEC_DEBUGGING 0x10000 + +#ifdef BFD_ARCH_SIZE +extern bfd_boolean _bfd_mmix_before_linker_allocation + (bfd *, struct bfd_link_info *); +extern bfd_boolean _bfd_mmix_after_linker_allocation + (bfd *, struct bfd_link_info *); +extern bfd_boolean _bfd_mmix_check_all_relocs + (bfd *, struct bfd_link_info *); +#endif + +#endif /* ELF_MMIX_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mn10200.h b/external/gpl3/gdb/dist/include/elf/mn10200.h new file mode 100644 index 000000000000..24972b6890f1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mn10200.h @@ -0,0 +1,40 @@ +/* MN10200 ELF support for BFD. + Copyright 1998, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MN10200 ELF ABI. */ + +#ifndef _ELF_MN10200_H +#define _ELF_MN10200_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10200_reloc_type) + RELOC_NUMBER (R_MN10200_NONE, 0) + RELOC_NUMBER (R_MN10200_32, 1) + RELOC_NUMBER (R_MN10200_16, 2) + RELOC_NUMBER (R_MN10200_8, 3) + RELOC_NUMBER (R_MN10200_24, 4) + RELOC_NUMBER (R_MN10200_PCREL8, 5) + RELOC_NUMBER (R_MN10200_PCREL16, 6) + RELOC_NUMBER (R_MN10200_PCREL24, 7) +END_RELOC_NUMBERS (R_MN10200_max) + +#endif /* _ELF_MN10200_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mn10300.h b/external/gpl3/gdb/dist/include/elf/mn10300.h new file mode 100644 index 000000000000..444787b5f952 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mn10300.h @@ -0,0 +1,71 @@ +/* MN10300 ELF support for BFD. + Copyright 1998, 1999, 2000, 2003, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MN10300 ELF ABI. */ + +#ifndef _ELF_MN10300_H +#define _ELF_MN10300_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mn10300_reloc_type) + RELOC_NUMBER (R_MN10300_NONE, 0) + RELOC_NUMBER (R_MN10300_32, 1) + RELOC_NUMBER (R_MN10300_16, 2) + RELOC_NUMBER (R_MN10300_8, 3) + RELOC_NUMBER (R_MN10300_PCREL32, 4) + RELOC_NUMBER (R_MN10300_PCREL16, 5) + RELOC_NUMBER (R_MN10300_PCREL8, 6) + RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8) + RELOC_NUMBER (R_MN10300_24, 9) + RELOC_NUMBER (R_MN10300_GOTPC32, 10) + RELOC_NUMBER (R_MN10300_GOTPC16, 11) + RELOC_NUMBER (R_MN10300_GOTOFF32, 12) + RELOC_NUMBER (R_MN10300_GOTOFF24, 13) + RELOC_NUMBER (R_MN10300_GOTOFF16, 14) + RELOC_NUMBER (R_MN10300_PLT32, 15) + RELOC_NUMBER (R_MN10300_PLT16, 16) + RELOC_NUMBER (R_MN10300_GOT32, 17) + RELOC_NUMBER (R_MN10300_GOT24, 18) + RELOC_NUMBER (R_MN10300_GOT16, 19) + RELOC_NUMBER (R_MN10300_COPY, 20) + RELOC_NUMBER (R_MN10300_GLOB_DAT, 21) + RELOC_NUMBER (R_MN10300_JMP_SLOT, 22) + RELOC_NUMBER (R_MN10300_RELATIVE, 23) + RELOC_NUMBER (R_MN10300_SYM_DIFF, 33) + RELOC_NUMBER (R_MN10300_ALIGN, 34) +END_RELOC_NUMBERS (R_MN10300_MAX) + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MN10300_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MN10300_MACH_MN10300 0x00810000 +#define E_MN10300_MACH_AM33 0x00820000 +#define E_MN10300_MACH_AM33_2 0x00830000 +#endif /* _ELF_MN10300_H */ diff --git a/external/gpl3/gdb/dist/include/elf/moxie.h b/external/gpl3/gdb/dist/include/elf/moxie.h new file mode 100644 index 000000000000..0b3eb3810c20 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/moxie.h @@ -0,0 +1,32 @@ +/* moxie ELF support for BFD. + Copyright 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_MOXIE_H +#define _ELF_MOXIE_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_moxie_reloc_type) + RELOC_NUMBER (R_MOXIE_NONE, 0) + RELOC_NUMBER (R_MOXIE_32, 1) + RELOC_NUMBER (R_MOXIE_PCREL10, 2) +END_RELOC_NUMBERS (R_MOXIE_max) + +#endif /* _ELF_MOXIE_H */ diff --git a/external/gpl3/gdb/dist/include/elf/msp430.h b/external/gpl3/gdb/dist/include/elf/msp430.h new file mode 100644 index 000000000000..44f5c51a7043 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/msp430.h @@ -0,0 +1,58 @@ +/* MSP430 ELF support for BFD. + Copyright (C) 2002, 2003, 2004, 2010 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_MSP430_H +#define _ELF_MSP430_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_MSP430_MACH 0xff + +#define E_MSP430_MACH_MSP430x11 11 +#define E_MSP430_MACH_MSP430x11x1 110 +#define E_MSP430_MACH_MSP430x12 12 +#define E_MSP430_MACH_MSP430x13 13 +#define E_MSP430_MACH_MSP430x14 14 +#define E_MSP430_MACH_MSP430x15 15 +#define E_MSP430_MACH_MSP430x16 16 +#define E_MSP430_MACH_MSP430x31 31 +#define E_MSP430_MACH_MSP430x32 32 +#define E_MSP430_MACH_MSP430x33 33 +#define E_MSP430_MACH_MSP430x41 41 +#define E_MSP430_MACH_MSP430x42 42 +#define E_MSP430_MACH_MSP430x43 43 +#define E_MSP430_MACH_MSP430x44 44 + +/* Relocations. */ +START_RELOC_NUMBERS (elf_msp430_reloc_type) + RELOC_NUMBER (R_MSP430_NONE, 0) + RELOC_NUMBER (R_MSP430_32, 1) + RELOC_NUMBER (R_MSP430_10_PCREL, 2) + RELOC_NUMBER (R_MSP430_16, 3) + RELOC_NUMBER (R_MSP430_16_PCREL, 4) + RELOC_NUMBER (R_MSP430_16_BYTE, 5) + RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6) + RELOC_NUMBER (R_MSP430_2X_PCREL, 7) + RELOC_NUMBER (R_MSP430_RL_PCREL, 8) + +END_RELOC_NUMBERS (R_MSP430_max) + +#endif /* _ELF_MSP430_H */ diff --git a/external/gpl3/gdb/dist/include/elf/mt.h b/external/gpl3/gdb/dist/include/elf/mt.h new file mode 100644 index 000000000000..2bc09f42dcb1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/mt.h @@ -0,0 +1,46 @@ +/* MS1 ELF support for BFD. + Copyright (C) 2000, 2005, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_MT_H +#define _ELF_MT_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mt_reloc_type) + RELOC_NUMBER (R_MT_NONE, 0) + RELOC_NUMBER (R_MT_16, 1) + RELOC_NUMBER (R_MT_32, 2) + RELOC_NUMBER (R_MT_32_PCREL, 3) + RELOC_NUMBER (R_MT_PC16, 4) + RELOC_NUMBER (R_MT_HI16, 5) + RELOC_NUMBER (R_MT_LO16, 6) +END_RELOC_NUMBERS(R_MT_max) + +#define EF_MT_CPU_MRISC 0x00000001 /* default */ +#define EF_MT_CPU_MRISC2 0x00000002 /* MRISC2 */ +#define EF_MT_CPU_MS2 0x00000003 /* MS2 */ +#define EF_MT_CPU_MASK 0x00000003 /* specific cpu bits */ +#define EF_MT_ALL_FLAGS (EF_MT_CPU_MASK) + +/* The location of the memory mapped hardware stack. */ +#define MT_STACK_VALUE 0x0f000000 +#define MT_STACK_SIZE 0x20 + +#endif /* _ELF_MT_H */ diff --git a/external/gpl3/gdb/dist/include/elf/openrisc.h b/external/gpl3/gdb/dist/include/elf/openrisc.h new file mode 100644 index 000000000000..87969e8b87ef --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/openrisc.h @@ -0,0 +1,39 @@ +/* OpenRISC ELF support for BFD. + Copyright 2001, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_OPENRISC_H +#define _ELF_OPENRISC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_openrisc_reloc_type) + RELOC_NUMBER (R_OPENRISC_NONE, 0) + RELOC_NUMBER (R_OPENRISC_INSN_REL_26, 1) + RELOC_NUMBER (R_OPENRISC_INSN_ABS_26, 2) + RELOC_NUMBER (R_OPENRISC_LO_16_IN_INSN, 3) + RELOC_NUMBER (R_OPENRISC_HI_16_IN_INSN, 4) + RELOC_NUMBER (R_OPENRISC_8, 5) + RELOC_NUMBER (R_OPENRISC_16, 6) + RELOC_NUMBER (R_OPENRISC_32, 7) + RELOC_NUMBER (R_OPENRISC_GNU_VTINHERIT, 8) + RELOC_NUMBER (R_OPENRISC_GNU_VTENTRY, 9) +END_RELOC_NUMBERS (R_OPENRISC_max) + +#endif /* _ELF_OPENRISC_H */ diff --git a/external/gpl3/gdb/dist/include/elf/or32.h b/external/gpl3/gdb/dist/include/elf/or32.h new file mode 100644 index 000000000000..9f1c2f3f7e55 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/or32.h @@ -0,0 +1,56 @@ +/* OR1K ELF support for BFD. Derived from ppc.h. + Copyright (C) 2002, 2010 Free Software Foundation, Inc. + Contributed by Ivan Guzvinec + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_OR1K_H +#define _ELF_OR1K_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_or32_reloc_type) + RELOC_NUMBER (R_OR32_NONE, 0) + RELOC_NUMBER (R_OR32_32, 1) + RELOC_NUMBER (R_OR32_16, 2) + RELOC_NUMBER (R_OR32_8, 3) + RELOC_NUMBER (R_OR32_CONST, 4) + RELOC_NUMBER (R_OR32_CONSTH, 5) + RELOC_NUMBER (R_OR32_JUMPTARG, 6) + RELOC_NUMBER (R_OR32_GNU_VTENTRY, 7) + RELOC_NUMBER (R_OR32_GNU_VTINHERIT, 8) +END_RELOC_NUMBERS (R_OR32_max) + +/* Four bit OR32 machine type field. */ +#define EF_OR32_MACH 0x0000000f + +/* Various CPU types. */ +#define E_OR32_MACH_BASE 0x00000000 +#define E_OR32_MACH_UNUSED1 0x00000001 +#define E_OR32_MACH_UNUSED2 0x00000002 +#define E_OR32_MACH_UNUSED4 0x00000003 + +/* Processor specific section headers, sh_type field */ +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +#endif /* _ELF_OR1K_H */ diff --git a/external/gpl3/gdb/dist/include/elf/pj.h b/external/gpl3/gdb/dist/include/elf/pj.h new file mode 100644 index 000000000000..afd19e8dc71b --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/pj.h @@ -0,0 +1,44 @@ +/* picoJava ELF support for BFD. + Copyright 1999, 2000, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_PJ_H +#define _ELF_PJ_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ + +START_RELOC_NUMBERS (elf_pj_reloc_type) + RELOC_NUMBER (R_PJ_NONE, 0) + RELOC_NUMBER (R_PJ_DATA_DIR32, 1) + RELOC_NUMBER (R_PJ_CODE_REL32, 2) + RELOC_NUMBER (R_PJ_CODE_REL16, 3) + RELOC_NUMBER (R_PJ_CODE_DIR32, 6) + RELOC_NUMBER (R_PJ_CODE_DIR16, 7) + RELOC_NUMBER (R_PJ_CODE_LO16, 13) + RELOC_NUMBER (R_PJ_CODE_HI16, 14) + RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16) +END_RELOC_NUMBERS (R_PJ_max) + +#define EF_PICOJAVA_ARCH 0x0000000f +#define EF_PICOJAVA_NEWCALLS 0x00000010 +#define EF_PICOJAVA_GNUCALLS 0x00000020 /* The (currently) non standard GNU calling convention */ + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/ppc.h b/external/gpl3/gdb/dist/include/elf/ppc.h new file mode 100644 index 000000000000..688cb9b9d198 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ppc.h @@ -0,0 +1,198 @@ +/* PPC ELF support for BFD. + Copyright 1995, 1996, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2008, + 2009, 2010 Free Software Foundation, Inc. + + By Michael Meissner, Cygnus Support, , + from information in the System V Application Binary Interface, + PowerPC Processor Supplement and the PowerPC Embedded Application + Binary Interface (eabi). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the PPC ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_PPC_H +#define _ELF_PPC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc_reloc_type) + RELOC_NUMBER (R_PPC_NONE, 0) + RELOC_NUMBER (R_PPC_ADDR32, 1) + RELOC_NUMBER (R_PPC_ADDR24, 2) + RELOC_NUMBER (R_PPC_ADDR16, 3) + RELOC_NUMBER (R_PPC_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC_ADDR14, 7) + RELOC_NUMBER (R_PPC_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC_REL24, 10) + RELOC_NUMBER (R_PPC_REL14, 11) + RELOC_NUMBER (R_PPC_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC_GOT16, 14) + RELOC_NUMBER (R_PPC_GOT16_LO, 15) + RELOC_NUMBER (R_PPC_GOT16_HI, 16) + RELOC_NUMBER (R_PPC_GOT16_HA, 17) + RELOC_NUMBER (R_PPC_PLTREL24, 18) + RELOC_NUMBER (R_PPC_COPY, 19) + RELOC_NUMBER (R_PPC_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC_RELATIVE, 22) + RELOC_NUMBER (R_PPC_LOCAL24PC, 23) + RELOC_NUMBER (R_PPC_UADDR32, 24) + RELOC_NUMBER (R_PPC_UADDR16, 25) + RELOC_NUMBER (R_PPC_REL32, 26) + RELOC_NUMBER (R_PPC_PLT32, 27) + RELOC_NUMBER (R_PPC_PLTREL32, 28) + RELOC_NUMBER (R_PPC_PLT16_LO, 29) + RELOC_NUMBER (R_PPC_PLT16_HI, 30) + RELOC_NUMBER (R_PPC_PLT16_HA, 31) + RELOC_NUMBER (R_PPC_SDAREL16, 32) + RELOC_NUMBER (R_PPC_SECTOFF, 33) + RELOC_NUMBER (R_PPC_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC_SECTOFF_HA, 36) + RELOC_NUMBER (R_PPC_ADDR30, 37) + +#ifndef RELOC_MACROS_GEN_FUNC +/* Fake relocations for branch stubs, only used internally by ld. */ + RELOC_NUMBER (R_PPC_RELAX, 48) + RELOC_NUMBER (R_PPC_RELAX_PLT, 49) + RELOC_NUMBER (R_PPC_RELAX_PLTREL24, 50) +#endif + + /* Relocs added to support TLS. */ + RELOC_NUMBER (R_PPC_TLS, 67) + RELOC_NUMBER (R_PPC_DTPMOD32, 68) + RELOC_NUMBER (R_PPC_TPREL16, 69) + RELOC_NUMBER (R_PPC_TPREL16_LO, 70) + RELOC_NUMBER (R_PPC_TPREL16_HI, 71) + RELOC_NUMBER (R_PPC_TPREL16_HA, 72) + RELOC_NUMBER (R_PPC_TPREL32, 73) + RELOC_NUMBER (R_PPC_DTPREL16, 74) + RELOC_NUMBER (R_PPC_DTPREL16_LO, 75) + RELOC_NUMBER (R_PPC_DTPREL16_HI, 76) + RELOC_NUMBER (R_PPC_DTPREL16_HA, 77) + RELOC_NUMBER (R_PPC_DTPREL32, 78) + RELOC_NUMBER (R_PPC_GOT_TLSGD16, 79) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_LO, 80) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_HI, 81) + RELOC_NUMBER (R_PPC_GOT_TLSGD16_HA, 82) + RELOC_NUMBER (R_PPC_GOT_TLSLD16, 83) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_LO, 84) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_HI, 85) + RELOC_NUMBER (R_PPC_GOT_TLSLD16_HA, 86) + RELOC_NUMBER (R_PPC_GOT_TPREL16, 87) + RELOC_NUMBER (R_PPC_GOT_TPREL16_LO, 88) + RELOC_NUMBER (R_PPC_GOT_TPREL16_HI, 89) + RELOC_NUMBER (R_PPC_GOT_TPREL16_HA, 90) + RELOC_NUMBER (R_PPC_GOT_DTPREL16, 91) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_LO, 92) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_HI, 93) + RELOC_NUMBER (R_PPC_GOT_DTPREL16_HA, 94) + RELOC_NUMBER (R_PPC_TLSGD, 95) + RELOC_NUMBER (R_PPC_TLSLD, 96) + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ + RELOC_NUMBER (R_PPC_EMB_NADDR32, 101) + RELOC_NUMBER (R_PPC_EMB_NADDR16, 102) + RELOC_NUMBER (R_PPC_EMB_NADDR16_LO, 103) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HI, 104) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HA, 105) + RELOC_NUMBER (R_PPC_EMB_SDAI16, 106) + RELOC_NUMBER (R_PPC_EMB_SDA2I16, 107) + RELOC_NUMBER (R_PPC_EMB_SDA2REL, 108) + RELOC_NUMBER (R_PPC_EMB_SDA21, 109) + RELOC_NUMBER (R_PPC_EMB_MRKREF, 110) + RELOC_NUMBER (R_PPC_EMB_RELSEC16, 111) + RELOC_NUMBER (R_PPC_EMB_RELST_LO, 112) + RELOC_NUMBER (R_PPC_EMB_RELST_HI, 113) + RELOC_NUMBER (R_PPC_EMB_RELST_HA, 114) + RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115) + RELOC_NUMBER (R_PPC_EMB_RELSDA, 116) + +/* Support STT_GNU_IFUNC plt calls. */ + RELOC_NUMBER (R_PPC_IRELATIVE, 248) + +/* These are GNU extensions used in PIC code sequences. */ + RELOC_NUMBER (R_PPC_REL16, 249) + RELOC_NUMBER (R_PPC_REL16_LO, 250) + RELOC_NUMBER (R_PPC_REL16_HI, 251) + RELOC_NUMBER (R_PPC_REL16_HA, 252) + +/* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC_GNU_VTENTRY, 254) + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ + RELOC_NUMBER (R_PPC_TOC16, 255) + +END_RELOC_NUMBERS (R_PPC_max) + +#define IS_PPC_TLS_RELOC(R) \ + ((R) >= R_PPC_TLS && (R) <= R_PPC_GOT_DTPREL16_HA) + +/* Specify the value of _GLOBAL_OFFSET_TABLE_. */ +#define DT_PPC_GOT (DT_LOPROC) + +/* Specify that tls descriptors should be optimized. */ +#define DT_PPC_TLSOPT (DT_LOPROC + 1) + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag. */ + +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */ + +/* Processor specific section headers, sh_type field. */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +/* Object attribute tags. */ +enum +{ + /* 0-3 are generic. */ + Tag_GNU_Power_ABI_FP = 4, /* Value 1 for hard-float, 2 for + soft-float, 3 for single=precision + hard-float; 0 for not tagged or not + using any ABIs affected by the + differences. */ + + /* Value 1 for general purpose registers only, 2 for AltiVec + registers, 3 for SPE registers; 0 for not tagged or not using any + ABIs affected by the differences. */ + Tag_GNU_Power_ABI_Vector = 8, + + /* Value 1 for ABIs using r3/r4 for returning structures <= 8 bytes, + 2 for ABIs using memory; 0 for not tagged or not using any ABIs + affected by the differences. */ + Tag_GNU_Power_ABI_Struct_Return = 12 +}; + +#endif /* _ELF_PPC_H */ diff --git a/external/gpl3/gdb/dist/include/elf/ppc64.h b/external/gpl3/gdb/dist/include/elf/ppc64.h new file mode 100644 index 000000000000..a18edd68fcef --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/ppc64.h @@ -0,0 +1,176 @@ +/* PPC64 ELF support for BFD. + Copyright 2003, 2005, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_PPC64_H +#define _ELF_PPC64_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc64_reloc_type) + RELOC_NUMBER (R_PPC64_NONE, 0) + RELOC_NUMBER (R_PPC64_ADDR32, 1) + RELOC_NUMBER (R_PPC64_ADDR24, 2) + RELOC_NUMBER (R_PPC64_ADDR16, 3) + RELOC_NUMBER (R_PPC64_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC64_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC64_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC64_ADDR14, 7) + RELOC_NUMBER (R_PPC64_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC64_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC64_REL24, 10) + RELOC_NUMBER (R_PPC64_REL14, 11) + RELOC_NUMBER (R_PPC64_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC64_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC64_GOT16, 14) + RELOC_NUMBER (R_PPC64_GOT16_LO, 15) + RELOC_NUMBER (R_PPC64_GOT16_HI, 16) + RELOC_NUMBER (R_PPC64_GOT16_HA, 17) + /* 18 unused. 32-bit reloc is R_PPC_PLTREL24. */ + RELOC_NUMBER (R_PPC64_COPY, 19) + RELOC_NUMBER (R_PPC64_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC64_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC64_RELATIVE, 22) + /* 23 unused. 32-bit reloc is R_PPC_LOCAL24PC. */ + RELOC_NUMBER (R_PPC64_UADDR32, 24) + RELOC_NUMBER (R_PPC64_UADDR16, 25) + RELOC_NUMBER (R_PPC64_REL32, 26) + RELOC_NUMBER (R_PPC64_PLT32, 27) + RELOC_NUMBER (R_PPC64_PLTREL32, 28) + RELOC_NUMBER (R_PPC64_PLT16_LO, 29) + RELOC_NUMBER (R_PPC64_PLT16_HI, 30) + RELOC_NUMBER (R_PPC64_PLT16_HA, 31) + /* 32 unused. 32-bit reloc is R_PPC_SDAREL16. */ + RELOC_NUMBER (R_PPC64_SECTOFF, 33) + RELOC_NUMBER (R_PPC64_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC64_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC64_SECTOFF_HA, 36) + RELOC_NUMBER (R_PPC64_REL30, 37) + RELOC_NUMBER (R_PPC64_ADDR64, 38) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHER, 39) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA, 40) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST, 41) + RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA, 42) + RELOC_NUMBER (R_PPC64_UADDR64, 43) + RELOC_NUMBER (R_PPC64_REL64, 44) + RELOC_NUMBER (R_PPC64_PLT64, 45) + RELOC_NUMBER (R_PPC64_PLTREL64, 46) + RELOC_NUMBER (R_PPC64_TOC16, 47) + RELOC_NUMBER (R_PPC64_TOC16_LO, 48) + RELOC_NUMBER (R_PPC64_TOC16_HI, 49) + RELOC_NUMBER (R_PPC64_TOC16_HA, 50) + RELOC_NUMBER (R_PPC64_TOC, 51) + RELOC_NUMBER (R_PPC64_PLTGOT16, 52) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO, 53) + RELOC_NUMBER (R_PPC64_PLTGOT16_HI, 54) + RELOC_NUMBER (R_PPC64_PLTGOT16_HA, 55) + + /* The following relocs were added in the 64-bit PowerPC ELF ABI + revision 1.2. */ + RELOC_NUMBER (R_PPC64_ADDR16_DS, 56) + RELOC_NUMBER (R_PPC64_ADDR16_LO_DS, 57) + RELOC_NUMBER (R_PPC64_GOT16_DS, 58) + RELOC_NUMBER (R_PPC64_GOT16_LO_DS, 59) + RELOC_NUMBER (R_PPC64_PLT16_LO_DS, 60) + RELOC_NUMBER (R_PPC64_SECTOFF_DS, 61) + RELOC_NUMBER (R_PPC64_SECTOFF_LO_DS, 62) + RELOC_NUMBER (R_PPC64_TOC16_DS, 63) + RELOC_NUMBER (R_PPC64_TOC16_LO_DS, 64) + RELOC_NUMBER (R_PPC64_PLTGOT16_DS, 65) + RELOC_NUMBER (R_PPC64_PLTGOT16_LO_DS, 66) + + /* Relocs added to support TLS. PowerPC64 ELF ABI revision 1.5. */ + RELOC_NUMBER (R_PPC64_TLS, 67) + RELOC_NUMBER (R_PPC64_DTPMOD64, 68) + RELOC_NUMBER (R_PPC64_TPREL16, 69) + RELOC_NUMBER (R_PPC64_TPREL16_LO, 70) + RELOC_NUMBER (R_PPC64_TPREL16_HI, 71) + RELOC_NUMBER (R_PPC64_TPREL16_HA, 72) + RELOC_NUMBER (R_PPC64_TPREL64, 73) + RELOC_NUMBER (R_PPC64_DTPREL16, 74) + RELOC_NUMBER (R_PPC64_DTPREL16_LO, 75) + RELOC_NUMBER (R_PPC64_DTPREL16_HI, 76) + RELOC_NUMBER (R_PPC64_DTPREL16_HA, 77) + RELOC_NUMBER (R_PPC64_DTPREL64, 78) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16, 79) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_LO, 80) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HI, 81) + RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HA, 82) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16, 83) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_LO, 84) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HI, 85) + RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HA, 86) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_DS, 87) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_LO_DS, 88) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HI, 89) + RELOC_NUMBER (R_PPC64_GOT_TPREL16_HA, 90) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_DS, 91) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_LO_DS, 92) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HI, 93) + RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HA, 94) + RELOC_NUMBER (R_PPC64_TPREL16_DS, 95) + RELOC_NUMBER (R_PPC64_TPREL16_LO_DS, 96) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHER, 97) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHERA, 98) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHEST, 99) + RELOC_NUMBER (R_PPC64_TPREL16_HIGHESTA, 100) + RELOC_NUMBER (R_PPC64_DTPREL16_DS, 101) + RELOC_NUMBER (R_PPC64_DTPREL16_LO_DS, 102) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHER, 103) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHERA, 104) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHEST, 105) + RELOC_NUMBER (R_PPC64_DTPREL16_HIGHESTA, 106) + RELOC_NUMBER (R_PPC64_TLSGD, 107) + RELOC_NUMBER (R_PPC64_TLSLD, 108) + +#ifndef RELOC_MACROS_GEN_FUNC +/* Fake relocation only used internally by ld. */ + RELOC_NUMBER (R_PPC64_LO_DS_OPT, 128) +#endif +/* Support STT_GNU_IFUNC plt calls. */ + RELOC_NUMBER (R_PPC64_JMP_IREL, 247) + RELOC_NUMBER (R_PPC64_IRELATIVE, 248) + +/* These are GNU extensions used in PIC code sequences. */ + RELOC_NUMBER (R_PPC64_REL16, 249) + RELOC_NUMBER (R_PPC64_REL16_LO, 250) + RELOC_NUMBER (R_PPC64_REL16_HI, 251) + RELOC_NUMBER (R_PPC64_REL16_HA, 252) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC64_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC64_GNU_VTENTRY, 254) + +END_RELOC_NUMBERS (R_PPC64_max) + +#define IS_PPC64_TLS_RELOC(R) \ + ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA) + +/* Specify the start of the .glink section. */ +#define DT_PPC64_GLINK DT_LOPROC + +/* Specify the start and size of the .opd section. */ +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) + +/* Specify that tls descriptors should be optimized. */ +#define DT_PPC64_TLSOPT (DT_LOPROC + 3) + +#endif /* _ELF_PPC64_H */ diff --git a/external/gpl3/gdb/dist/include/elf/reloc-macros.h b/external/gpl3/gdb/dist/include/elf/reloc-macros.h new file mode 100644 index 000000000000..c0228a9916ea --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/reloc-macros.h @@ -0,0 +1,129 @@ +/* Generic relocation support for BFD. + Copyright 1998, 1999, 2000, 2003, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* These macros are used by the various *.h target specific header + files to either generate an enum containing all the known relocations + for that target, or if RELOC_MACROS_GEN_FUNC is defined, a recognition + function is generated instead. (This is used by binutils/readelf.c) + + Given a header file like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + EMPTY_RELOC (R_foo_good) + FAKE_RELOC (R_foo_illegal, 9) + END_RELOC_NUMBERS (R_foo_count) + + Then the following will be produced by default (ie if + RELOC_MACROS_GEN_FUNC is *not* defined). + + enum foo + { + R_foo_NONE = 0, + R_foo_32 = 1, + R_foo_good, + R_foo_illegal = 9, + R_foo_count + }; + + Note: The value of the symbol defined in the END_RELOC_NUMBERS + macro (R_foo_count in the case of the example above) will be + set to the value of the whichever *_RELOC macro preceeds it plus + one. Therefore if you intend to use the symbol as a sentinel for + the highest valid macro value you should make sure that the + preceeding *_RELOC macro is the highest valid number. ie a + declaration like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + FAKE_RELOC (R_foo_illegal, 9) + FAKE_RELOC (R_foo_synonym, 0) + END_RELOC_NUMBERS (R_foo_count) + + will result in R_foo_count having a value of 1 (R_foo_synonym + 1) + rather than 10 or 2 as might be expected. + + Alternatively you can assign a value to END_RELOC_NUMBERS symbol + explicitly, like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + FAKE_RELOC (R_foo_illegal, 9) + FAKE_RELOC (R_foo_synonym, 0) + END_RELOC_NUMBERS (R_foo_count = 2) + + If RELOC_MACROS_GEN_FUNC *is* defined, then instead the + following function will be generated: + + static const char *foo (unsigned long rtype); + static const char * + foo (unsigned long rtype) + { + switch (rtype) + { + case 0: return "R_foo_NONE"; + case 1: return "R_foo_32"; + default: return NULL; + } + } + */ + +#ifndef _RELOC_MACROS_H +#define _RELOC_MACROS_H + +#ifdef RELOC_MACROS_GEN_FUNC + +/* This function takes the relocation number and returns the + string version name of the name of that relocation. If + the relocation is not recognised, NULL is returned. */ + +#define START_RELOC_NUMBERS(name) \ +static const char *name (unsigned long rtype); \ +static const char * \ +name (unsigned long rtype) \ +{ \ + switch (rtype) \ + { + +#define RELOC_NUMBER(name, number) \ + case number: return #name; + +#define FAKE_RELOC(name, number) +#define EMPTY_RELOC(name) + +#define END_RELOC_NUMBERS(name) \ + default: return NULL; \ + } \ +} + + +#else /* Default to generating enum. */ + +#define START_RELOC_NUMBERS(name) enum name { +#define RELOC_NUMBER(name, number) name = number, +#define FAKE_RELOC(name, number) name = number, +#define EMPTY_RELOC(name) name, +#define END_RELOC_NUMBERS(name) name }; + +#endif + +#endif /* _RELOC_MACROS_H */ diff --git a/external/gpl3/gdb/dist/include/elf/rx.h b/external/gpl3/gdb/dist/include/elf/rx.h new file mode 100644 index 000000000000..e8794f35297f --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/rx.h @@ -0,0 +1,134 @@ +/* RX ELF support for BFD. + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_RX_H +#define _ELF_RX_H + +#include "elf/reloc-macros.h" + +/* Note that there are a few internal relocation types used by the + linker to do link-time relaxation. If you update this file, please + check elf32-rx.c to see if any of the internal relocations need to + be, er, relocated. */ + +/* Preliminary relocations. */ +START_RELOC_NUMBERS (elf_rx_reloc_type) + + RELOC_NUMBER (R_RX_NONE, 0x00) + /* These are for data, and are bi-endian. */ + RELOC_NUMBER (R_RX_DIR32, 0x01) /* Was: R_RX_32. */ + RELOC_NUMBER (R_RX_DIR24S, 0x02) /* Was: R_RX_24. */ + RELOC_NUMBER (R_RX_DIR16, 0x03) + RELOC_NUMBER (R_RX_DIR16U, 0x04) /* Was: R_RX_16_UNS. */ + RELOC_NUMBER (R_RX_DIR16S, 0x05) /* Was: R_RX_16. */ + RELOC_NUMBER (R_RX_DIR8, 0x06) + RELOC_NUMBER (R_RX_DIR8U, 0x07) /* Was: R_RX_8_UNS. */ + RELOC_NUMBER (R_RX_DIR8S, 0x08) /* Was: R_RX_8. */ + + /* Signed pc-relative values. */ + RELOC_NUMBER (R_RX_DIR24S_PCREL, 0x09) /* Was: R_RX_24_PCREL. */ + RELOC_NUMBER (R_RX_DIR16S_PCREL, 0x0a) /* Was: R_RX_16_PCREL. */ + RELOC_NUMBER (R_RX_DIR8S_PCREL, 0x0b) /* Was: R_RX_8_PCREL. */ + + /* These are for fields in the instructions. */ + RELOC_NUMBER (R_RX_DIR16UL, 0x0c) + RELOC_NUMBER (R_RX_DIR16UW, 0x0d) + RELOC_NUMBER (R_RX_DIR8UL, 0x0e) + RELOC_NUMBER (R_RX_DIR8UW, 0x0f) + RELOC_NUMBER (R_RX_DIR32_REV, 0x10) + RELOC_NUMBER (R_RX_DIR16_REV, 0x11) + RELOC_NUMBER (R_RX_DIR3U_PCREL, 0x12) + + /* These are extensions added by Red Hat. */ + RELOC_NUMBER (R_RX_RH_3_PCREL, 0x20) /* Like R_RX_DIR8S_PCREL but only 3-bits. */ + RELOC_NUMBER (R_RX_RH_16_OP, 0x21) /* Like R_RX_DIR16 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_OP, 0x22) /* Like R_RX_DIR24S but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_32_OP, 0x23) /* Like R_RX_DIR32 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_UNS, 0x24) /* Like R_RX_DIR24S but for unsigned values. */ + RELOC_NUMBER (R_RX_RH_8_NEG, 0x25) /* Like R_RX_DIR8 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_16_NEG, 0x26) /* Like R_RX_DIR16 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_24_NEG, 0x27) /* Like R_RX_DIR24S but -x is stored. */ + RELOC_NUMBER (R_RX_RH_32_NEG, 0x28) /* Like R_RX_DIR32 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_DIFF, 0x29) /* Subtract from a previous relocation. */ + RELOC_NUMBER (R_RX_RH_GPRELB, 0x2a) /* Byte value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELW, 0x2b) /* Word value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELL, 0x2c) /* Long value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_RELAX, 0x2d) /* Marks opcodes suitable for linker relaxation. */ + + /* These are for complex relocs. */ + RELOC_NUMBER (R_RX_ABS32, 0x41) + RELOC_NUMBER (R_RX_ABS24S, 0x42) + RELOC_NUMBER (R_RX_ABS16, 0x43) + RELOC_NUMBER (R_RX_ABS16U, 0x44) + RELOC_NUMBER (R_RX_ABS16S, 0x45) + RELOC_NUMBER (R_RX_ABS8, 0x46) + RELOC_NUMBER (R_RX_ABS8U, 0x47) + RELOC_NUMBER (R_RX_ABS8S, 0x48) + RELOC_NUMBER (R_RX_ABS24S_PCREL, 0x49) + RELOC_NUMBER (R_RX_ABS16S_PCREL, 0x4a) + RELOC_NUMBER (R_RX_ABS8S_PCREL, 0x4b) + RELOC_NUMBER (R_RX_ABS16UL, 0x4c) + RELOC_NUMBER (R_RX_ABS16UW, 0x4d) + RELOC_NUMBER (R_RX_ABS8UL, 0x4e) + RELOC_NUMBER (R_RX_ABS8UW, 0x4f) + RELOC_NUMBER (R_RX_ABS32_REV, 0x50) + RELOC_NUMBER (R_RX_ABS16_REV, 0x51) + + RELOC_NUMBER (R_RX_SYM, 0x80) + RELOC_NUMBER (R_RX_OPneg, 0x81) + RELOC_NUMBER (R_RX_OPadd, 0x82) + RELOC_NUMBER (R_RX_OPsub, 0x83) + RELOC_NUMBER (R_RX_OPmul, 0x84) + RELOC_NUMBER (R_RX_OPdiv, 0x85) + RELOC_NUMBER (R_RX_OPshla, 0x86) + RELOC_NUMBER (R_RX_OPshra, 0x87) + RELOC_NUMBER (R_RX_OPsctsize, 0x88) + RELOC_NUMBER (R_RX_OPscttop, 0x8d) + RELOC_NUMBER (R_RX_OPand, 0x90) + RELOC_NUMBER (R_RX_OPor, 0x91) + RELOC_NUMBER (R_RX_OPxor, 0x92) + RELOC_NUMBER (R_RX_OPnot, 0x93) + RELOC_NUMBER (R_RX_OPmod, 0x94) + RELOC_NUMBER (R_RX_OPromtop, 0x95) + RELOC_NUMBER (R_RX_OPramtop, 0x96) + +END_RELOC_NUMBERS (R_RX_max) + +#define EF_RX_CPU_RX 0x00000079 /* FIXME: correct value? */ +#define EF_RX_CPU_MASK 0x0000007F /* specific cpu bits. */ +#define EF_RX_ALL_FLAGS (EF_RX_CPU_MASK) + +/* Values for the e_flags field in the ELF header. */ +#define E_FLAG_RX_64BIT_DOUBLES (1 << 0) +#define E_FLAG_RX_DSP (1 << 1) /* Defined in the RX CPU Object file specification, but not explained. */ + +/* These define the addend field of R_RX_RH_RELAX relocations. */ +#define RX_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */ +#define RX_RELAXA_IMM12 0x00000020 /* Imm8/16/24/32 at bit offset 12. */ +#define RX_RELAXA_DSP4 0x00000040 /* Dsp0/8/16 at bit offset 4. */ +#define RX_RELAXA_DSP6 0x00000080 /* Dsp0/8/16 at bit offset 6. */ +#define RX_RELAXA_DSP14 0x00000100 /* Dsp0/8/16 at bit offset 14. */ +#define RX_RELAXA_BRA 0x00000200 /* Any type of branch (must be decoded). */ +#define RX_RELAXA_RNUM 0x0000000f /* Number of associated relocations. */ +/* These mark the place where alignment is requested, and the place where the filler bytes end. */ +#define RX_RELAXA_ALIGN 0x10000000 /* Start alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ELIGN 0x20000000 /* End alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ANUM 0x00ffffff /* Alignment amount, in bytes (i.e. .balign). */ + +#endif /* _ELF_RX_H */ diff --git a/external/gpl3/gdb/dist/include/elf/s390.h b/external/gpl3/gdb/dist/include/elf/s390.h new file mode 100644 index 000000000000..807b7e8e0869 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/s390.h @@ -0,0 +1,129 @@ +/* 390 ELF support for BFD. + Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. + Contributed by Carl B. Pedersen and Martin Schwidefsky. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef _ELF_390_H +#define _ELF_390_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Symbol types. */ + +#define STACK_REG 15 /* Global Stack reg */ +#define BACKL_REG 14 /* Global Backlink reg */ +#define BASE_REG 13 /* Global Base reg */ +#define GOT_REG 12 /* Holds addr of GOT */ + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_S390_HIGH_GPRS 0x00000001 + +/* Relocation types. */ + +START_RELOC_NUMBERS (elf_s390_reloc_type) + RELOC_NUMBER (R_390_NONE, 0) /* No reloc. */ + RELOC_NUMBER (R_390_8, 1) /* Direct 8 bit. */ + RELOC_NUMBER (R_390_12, 2) /* Direct 12 bit. */ + RELOC_NUMBER (R_390_16, 3) /* Direct 16 bit. */ + RELOC_NUMBER (R_390_32, 4) /* Direct 32 bit. */ + RELOC_NUMBER (R_390_PC32, 5) /* PC relative 32 bit. */ + RELOC_NUMBER (R_390_GOT12, 6) /* 12 bit GOT offset. */ + RELOC_NUMBER (R_390_GOT32, 7) /* 32 bit GOT offset. */ + RELOC_NUMBER (R_390_PLT32, 8) /* 32 bit PC relative PLT address. */ + RELOC_NUMBER (R_390_COPY, 9) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_390_GLOB_DAT, 10) /* Create GOT entry. */ + RELOC_NUMBER (R_390_JMP_SLOT, 11) /* Create PLT entry. */ + RELOC_NUMBER (R_390_RELATIVE, 12) /* Adjust by program base. */ + RELOC_NUMBER (R_390_GOTOFF32, 13) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTPC, 14) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_390_GOT16, 15) /* 16 bit GOT offset. */ + RELOC_NUMBER (R_390_PC16, 16) /* PC relative 16 bit. */ + RELOC_NUMBER (R_390_PC16DBL, 17) /* PC relative 16 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT16DBL, 18) /* 16 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_PC32DBL, 19) /* PC relative 32 bit shifted by 1. */ + RELOC_NUMBER (R_390_PLT32DBL, 20) /* 32 bit PC rel. PLT shifted by 1. */ + RELOC_NUMBER (R_390_GOTPCDBL, 21) /* 32 bit PC rel. GOT shifted by 1. */ + RELOC_NUMBER (R_390_64, 22) /* Direct 64 bit. */ + RELOC_NUMBER (R_390_PC64, 23) /* PC relative 64 bit. */ + RELOC_NUMBER (R_390_GOT64, 24) /* 64 bit GOT offset. */ + RELOC_NUMBER (R_390_PLT64, 25) /* 64 bit PC relative PLT address. */ + RELOC_NUMBER (R_390_GOTENT, 26) /* 32 bit PC rel. to GOT entry >> 1. */ + RELOC_NUMBER (R_390_GOTOFF16, 27) /* 16 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTOFF64, 28) /* 64 bit offset to GOT. */ + RELOC_NUMBER (R_390_GOTPLT12, 29) /* 12 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT16, 30) /* 16 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT32, 31) /* 32 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLT64, 32) /* 64 bit offset to jump slot. */ + RELOC_NUMBER (R_390_GOTPLTENT, 33) /* 32 bit rel. offset to jump slot. */ + RELOC_NUMBER (R_390_PLTOFF16, 34) /* 16 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_PLTOFF32, 35) /* 32 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_PLTOFF64, 36) /* 16 bit offset from GOT to PLT. */ + RELOC_NUMBER (R_390_TLS_LOAD, 37) /* Tag for load insn in TLS code. */ + RELOC_NUMBER (R_390_TLS_GDCALL, 38) /* Tag for function call in general + dynamic TLS code. */ + RELOC_NUMBER (R_390_TLS_LDCALL, 39) /* Tag for function call in local + dynamic TLS code. */ + RELOC_NUMBER (R_390_TLS_GD32, 40) /* Direct 32 bit for general dynamic + thread local data. */ + RELOC_NUMBER (R_390_TLS_GD64, 41) /* Direct 64 bit for general dynamic + thread local data. */ + RELOC_NUMBER (R_390_TLS_GOTIE12, 42)/* 12 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_GOTIE32, 43)/* 32 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_GOTIE64, 44)/* 64 bit GOT offset for static TLS + block offset. */ + RELOC_NUMBER (R_390_TLS_LDM32, 45) /* Direct 32 bit for local dynamic + thread local data in LD code. */ + RELOC_NUMBER (R_390_TLS_LDM64, 46) /* Direct 64 bit for local dynamic + thread local data in LD code. */ + RELOC_NUMBER (R_390_TLS_IE32, 47) /* 32 bit address of GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_IE64, 48) /* 64 bit address of GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_IEENT, 49) /* 32 bit rel. offset to GOT entry for + negated static TLS block offset. */ + RELOC_NUMBER (R_390_TLS_LE32, 50) /* 32 bit negated offset relative to + static TLS block. */ + RELOC_NUMBER (R_390_TLS_LE64, 51) /* 64 bit negated offset relative to + static TLS block. */ + RELOC_NUMBER (R_390_TLS_LDO32, 52) /* 32 bit offset relative to TLS + block. */ + RELOC_NUMBER (R_390_TLS_LDO64, 53) /* 64 bit offset relative to TLS + block. */ + RELOC_NUMBER (R_390_TLS_DTPMOD, 54) /* ID of module containing symbol. */ + RELOC_NUMBER (R_390_TLS_DTPOFF, 55) /* Offset in TLS block. */ + RELOC_NUMBER (R_390_TLS_TPOFF, 56) /* Negate offset in static TLS + block. */ + RELOC_NUMBER (R_390_20, 57) /* Direct 20 bit. */ + RELOC_NUMBER (R_390_GOT20, 58) /* 20 bit GOT offset. */ + RELOC_NUMBER (R_390_GOTPLT20, 59) /* 20 bit offset to jump slot. */ + RELOC_NUMBER (R_390_TLS_GOTIE20, 60)/* 20 bit GOT offset for statis TLS + block offset. */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_390_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_390_GNU_VTENTRY, 251) +END_RELOC_NUMBERS (R_390_max) + +#endif /* _ELF_390_H */ + + diff --git a/external/gpl3/gdb/dist/include/elf/score.h b/external/gpl3/gdb/dist/include/elf/score.h new file mode 100644 index 000000000000..8d9c026bb047 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/score.h @@ -0,0 +1,130 @@ +/* Score ELF support for BFD. + Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_SCORE_H +#define _ELF_SCORE_H + +#include "elf/reloc-macros.h" + +#define SCORE_SIMULATOR_ACTIVE 1 +#define OPC_PTMASK 0xc0000000 /* Parity-bit Mask. */ +#define OPC16_PTMASK 0x00008000 +/* The parity-bit denotes. */ +#define OPC_32 0xc0000000 /* Denotes 32b instruction, (default). */ +#define OPC_16 0x00000000 /* Denotes 16b instruction. */ +#define OPC_PE 0x8000 /* Denotes parallel-execution instructions. */ +#define GP_DISP_LABEL "_gp_disp" + +/* Processor specific flags for the ELF header e_flags field: */ +#define EF_SCORE_MACH 0xffff0000 +#define EF_OMIT_PIC_FIXDD 0x0fff0000 +#define E_SCORE_MACH_SCORE3 0x00030000 +#define E_SCORE_MACH_SCORE7 0x00070000 + +/* File contains position independent code. */ +#define EF_SCORE_PIC 0x80000000 + +/* Fix data dependency. */ +#define EF_SCORE_FIXDEP 0x40000000 + +/* Defined and allocated common symbol. Value is virtual address. If + relocated, alignment must be preserved. */ +#define SHN_SCORE_TEXT (SHN_LORESERVE + 1) +#define SHN_SCORE_DATA (SHN_LORESERVE + 2) +/* Small common symbol. */ +#define SHN_SCORE_SCOMMON (SHN_LORESERVE + 3) + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_SCORE_GPREL 0x10000000 + +/* This section should be merged. */ +#define SHF_SCORE_MERGE 0x20000000 + +/* This section contains address data of size implied by section + element size. */ +#define SHF_SCORE_ADDR 0x40000000 + +/* This section contains string data. */ +#define SHF_SCORE_STRING 0x80000000 + +/* This section may not be stripped. */ +#define SHF_SCORE_NOSTRIP 0x08000000 + +/* This section is local to threads. */ +#define SHF_SCORE_LOCAL 0x04000000 + +/* Linker should generate implicit weak names for this section. */ +#define SHF_SCORE_NAMES 0x02000000 + +/* Section contais text/data which may be replicated in other sections. + Linker should retain only one copy. */ +#define SHF_SCORE_NODUPES 0x01000000 + +/* Processor specific dynamic array tags. */ + +/* Base address of the segment. */ +#define DT_SCORE_BASE_ADDRESS 0x70000001 +/* Number of local global offset table entries. */ +#define DT_SCORE_LOCAL_GOTNO 0x70000002 +/* Number of entries in the .dynsym section. */ +#define DT_SCORE_SYMTABNO 0x70000003 +/* Index of first dynamic symbol in global offset table. */ +#define DT_SCORE_GOTSYM 0x70000004 +/* Index of first external dynamic symbol not referenced locally. */ +#define DT_SCORE_UNREFEXTNO 0x70000005 +/* Number of page table entries in global offset table. */ +#define DT_SCORE_HIPAGENO 0x70000006 + + +/* Processor specific section types. */ + + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_score_reloc_type) + RELOC_NUMBER (R_SCORE_NONE, 0) + RELOC_NUMBER (R_SCORE_HI16, 1) + RELOC_NUMBER (R_SCORE_LO16, 2) + RELOC_NUMBER (R_SCORE_BCMP, 3) + RELOC_NUMBER (R_SCORE_24, 4) + RELOC_NUMBER (R_SCORE_PC19, 5) + RELOC_NUMBER (R_SCORE16_11, 6) + RELOC_NUMBER (R_SCORE16_PC8, 7) + RELOC_NUMBER (R_SCORE_ABS32, 8) + RELOC_NUMBER (R_SCORE_ABS16, 9) + RELOC_NUMBER (R_SCORE_DUMMY2, 10) + RELOC_NUMBER (R_SCORE_GP15, 11) + RELOC_NUMBER (R_SCORE_GNU_VTINHERIT, 12) + RELOC_NUMBER (R_SCORE_GNU_VTENTRY, 13) + RELOC_NUMBER (R_SCORE_GOT15, 14) + RELOC_NUMBER (R_SCORE_GOT_LO16, 15) + RELOC_NUMBER (R_SCORE_CALL15, 16) + RELOC_NUMBER (R_SCORE_GPREL32, 17) + RELOC_NUMBER (R_SCORE_REL32, 18) + RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19) + RELOC_NUMBER (R_SCORE_IMM30, 20) + RELOC_NUMBER (R_SCORE_IMM32, 21) +END_RELOC_NUMBERS (R_SCORE_max) + +#endif /* _ELF_SCORE_H */ diff --git a/external/gpl3/gdb/dist/include/elf/sh.h b/external/gpl3/gdb/dist/include/elf/sh.h new file mode 100644 index 000000000000..c2bd50d2a87b --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/sh.h @@ -0,0 +1,250 @@ +/* SH ELF support for BFD. + Copyright 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_SH_H +#define _ELF_SH_H + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ +#define EF_SH1 1 +#define EF_SH2 2 +#define EF_SH3 3 +#define EF_SH_DSP 4 +#define EF_SH3_DSP 5 +#define EF_SH4AL_DSP 6 +#define EF_SH3E 8 +#define EF_SH4 9 +#define EF_SH2E 11 +#define EF_SH4A 12 +#define EF_SH2A 13 + +#define EF_SH4_NOFPU 16 +#define EF_SH4A_NOFPU 17 +#define EF_SH4_NOMMU_NOFPU 18 +#define EF_SH2A_NOFPU 19 +#define EF_SH3_NOMMU 20 + +#define EF_SH2A_SH4_NOFPU 21 +#define EF_SH2A_SH3_NOFPU 22 +#define EF_SH2A_SH4 23 +#define EF_SH2A_SH3E 24 + +/* This one can only mix in objects from other EF_SH5 objects. */ +#define EF_SH5 10 + +/* Define the mapping from ELF to bfd mach numbers. + bfd_mach_* are defined in bfd_in2.h (generated from + archures.c). */ +#define EF_SH_BFD_TABLE \ +/* EF_SH_UNKNOWN */ bfd_mach_sh , \ +/* EF_SH1 */ bfd_mach_sh , \ +/* EF_SH2 */ bfd_mach_sh2 , \ +/* EF_SH3 */ bfd_mach_sh3 , \ +/* EF_SH_DSP */ bfd_mach_sh_dsp , \ +/* EF_SH3_DSP */ bfd_mach_sh3_dsp , \ +/* EF_SHAL_DSP */ bfd_mach_sh4al_dsp , \ +/* 7 */ 0, \ +/* EF_SH3E */ bfd_mach_sh3e , \ +/* EF_SH4 */ bfd_mach_sh4 , \ +/* EF_SH5 */ 0, \ +/* EF_SH2E */ bfd_mach_sh2e , \ +/* EF_SH4A */ bfd_mach_sh4a , \ +/* EF_SH2A */ bfd_mach_sh2a , \ +/* 14, 15 */ 0, 0, \ +/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ +/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ +/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +/* EF_SH2A_NOFPU */ bfd_mach_sh2a_nofpu , \ +/* EF_SH3_NOMMU */ bfd_mach_sh3_nommu , \ +/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ +/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ +/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e + +/* Convert arch_sh* into EF_SH*. */ +int sh_find_elf_flags (unsigned int arch_set); + +/* Convert bfd_mach_* into EF_SH*. */ +int sh_elf_get_flags_from_mach (unsigned long mach); + +/* Other e_flags bits. */ + +#define EF_SH_PIC 0x100 /* Segments of an FDPIC binary may + be relocated independently. */ +#define EF_SH_FDPIC 0x8000 /* Uses the FDPIC ABI. */ + +/* Flags for the st_other symbol field. + Keep away from the STV_ visibility flags (bit 0..1). */ + +/* A reference to this symbol should by default add 1. */ +#define STO_SH5_ISA32 (1 << 2) + +/* Section contains only SHmedia code (no SHcompact code). */ +#define SHF_SH5_ISA32 0x40000000 + +/* Section contains both SHmedia and SHcompact code, and possibly also + constants. */ +#define SHF_SH5_ISA32_MIXED 0x20000000 + +/* If applied to a .cranges section, marks that the section is sorted by + increasing cr_addr values. */ +#define SHT_SH5_CR_SORTED 0x80000001 + +/* Symbol should be handled as DataLabel (attached to global SHN_UNDEF + symbols). */ +#define STT_DATALABEL STT_LOPROC + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 10-32 and 128-255 are GNU extensions. + 25..32 and 10 are used for relaxation. */ +START_RELOC_NUMBERS (elf_sh_reloc_type) + RELOC_NUMBER (R_SH_NONE, 0) + RELOC_NUMBER (R_SH_DIR32, 1) + RELOC_NUMBER (R_SH_REL32, 2) + RELOC_NUMBER (R_SH_DIR8WPN, 3) + RELOC_NUMBER (R_SH_IND12W, 4) + RELOC_NUMBER (R_SH_DIR8WPL, 5) + RELOC_NUMBER (R_SH_DIR8WPZ, 6) + RELOC_NUMBER (R_SH_DIR8BP, 7) + RELOC_NUMBER (R_SH_DIR8W, 8) + RELOC_NUMBER (R_SH_DIR8L, 9) + + RELOC_NUMBER (R_SH_LOOP_START, 10) + RELOC_NUMBER (R_SH_LOOP_END, 11) + + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC, 12) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC, 21) + + RELOC_NUMBER (R_SH_GNU_VTINHERIT, 22) + RELOC_NUMBER (R_SH_GNU_VTENTRY, 23) + RELOC_NUMBER (R_SH_SWITCH8, 24) + RELOC_NUMBER (R_SH_SWITCH16, 25) + RELOC_NUMBER (R_SH_SWITCH32, 26) + RELOC_NUMBER (R_SH_USES, 27) + RELOC_NUMBER (R_SH_COUNT, 28) + RELOC_NUMBER (R_SH_ALIGN, 29) + RELOC_NUMBER (R_SH_CODE, 30) + RELOC_NUMBER (R_SH_DATA, 31) + RELOC_NUMBER (R_SH_LABEL, 32) + + RELOC_NUMBER (R_SH_DIR16, 33) + RELOC_NUMBER (R_SH_DIR8, 34) + RELOC_NUMBER (R_SH_DIR8UL, 35) + RELOC_NUMBER (R_SH_DIR8UW, 36) + RELOC_NUMBER (R_SH_DIR8U, 37) + RELOC_NUMBER (R_SH_DIR8SW, 38) + RELOC_NUMBER (R_SH_DIR8S, 39) + RELOC_NUMBER (R_SH_DIR4UL, 40) + RELOC_NUMBER (R_SH_DIR4UW, 41) + RELOC_NUMBER (R_SH_DIR4U, 42) + RELOC_NUMBER (R_SH_PSHA, 43) + RELOC_NUMBER (R_SH_PSHL, 44) + RELOC_NUMBER (R_SH_DIR5U, 45) + RELOC_NUMBER (R_SH_DIR6U, 46) + RELOC_NUMBER (R_SH_DIR6S, 47) + RELOC_NUMBER (R_SH_DIR10S, 48) + RELOC_NUMBER (R_SH_DIR10SW, 49) + RELOC_NUMBER (R_SH_DIR10SL, 50) + RELOC_NUMBER (R_SH_DIR10SQ, 51) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_2, 52) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_2, 52) + RELOC_NUMBER (R_SH_DIR16S, 53) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_3, 54) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_3, 143) + RELOC_NUMBER (R_SH_TLS_GD_32, 144) + RELOC_NUMBER (R_SH_TLS_LD_32, 145) + RELOC_NUMBER (R_SH_TLS_LDO_32, 146) + RELOC_NUMBER (R_SH_TLS_IE_32, 147) + RELOC_NUMBER (R_SH_TLS_LE_32, 148) + RELOC_NUMBER (R_SH_TLS_DTPMOD32, 149) + RELOC_NUMBER (R_SH_TLS_DTPOFF32, 150) + RELOC_NUMBER (R_SH_TLS_TPOFF32, 151) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_4, 152) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_4, 159) + RELOC_NUMBER (R_SH_GOT32, 160) + RELOC_NUMBER (R_SH_PLT32, 161) + RELOC_NUMBER (R_SH_COPY, 162) + RELOC_NUMBER (R_SH_GLOB_DAT, 163) + RELOC_NUMBER (R_SH_JMP_SLOT, 164) + RELOC_NUMBER (R_SH_RELATIVE, 165) + RELOC_NUMBER (R_SH_GOTOFF, 166) + RELOC_NUMBER (R_SH_GOTPC, 167) + RELOC_NUMBER (R_SH_GOTPLT32, 168) + RELOC_NUMBER (R_SH_GOT_LOW16, 169) + RELOC_NUMBER (R_SH_GOT_MEDLOW16, 170) + RELOC_NUMBER (R_SH_GOT_MEDHI16, 171) + RELOC_NUMBER (R_SH_GOT_HI16, 172) + RELOC_NUMBER (R_SH_GOTPLT_LOW16, 173) + RELOC_NUMBER (R_SH_GOTPLT_MEDLOW16, 174) + RELOC_NUMBER (R_SH_GOTPLT_MEDHI16, 175) + RELOC_NUMBER (R_SH_GOTPLT_HI16, 176) + RELOC_NUMBER (R_SH_PLT_LOW16, 177) + RELOC_NUMBER (R_SH_PLT_MEDLOW16, 178) + RELOC_NUMBER (R_SH_PLT_MEDHI16, 179) + RELOC_NUMBER (R_SH_PLT_HI16, 180) + RELOC_NUMBER (R_SH_GOTOFF_LOW16, 181) + RELOC_NUMBER (R_SH_GOTOFF_MEDLOW16, 182) + RELOC_NUMBER (R_SH_GOTOFF_MEDHI16, 183) + RELOC_NUMBER (R_SH_GOTOFF_HI16, 184) + RELOC_NUMBER (R_SH_GOTPC_LOW16, 185) + RELOC_NUMBER (R_SH_GOTPC_MEDLOW16, 186) + RELOC_NUMBER (R_SH_GOTPC_MEDHI16, 187) + RELOC_NUMBER (R_SH_GOTPC_HI16, 188) + RELOC_NUMBER (R_SH_GOT10BY4, 189) + RELOC_NUMBER (R_SH_GOTPLT10BY4, 190) + RELOC_NUMBER (R_SH_GOT10BY8, 191) + RELOC_NUMBER (R_SH_GOTPLT10BY8, 192) + RELOC_NUMBER (R_SH_COPY64, 193) + RELOC_NUMBER (R_SH_GLOB_DAT64, 194) + RELOC_NUMBER (R_SH_JMP_SLOT64, 195) + RELOC_NUMBER (R_SH_RELATIVE64, 196) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_5, 197) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_5, 200) + RELOC_NUMBER (R_SH_GOT20, 201) + RELOC_NUMBER (R_SH_GOTOFF20, 202) + RELOC_NUMBER (R_SH_GOTFUNCDESC, 203) + RELOC_NUMBER (R_SH_GOTFUNCDESC20, 204) + RELOC_NUMBER (R_SH_GOTOFFFUNCDESC, 205) + RELOC_NUMBER (R_SH_GOTOFFFUNCDESC20, 206) + RELOC_NUMBER (R_SH_FUNCDESC, 207) + RELOC_NUMBER (R_SH_FUNCDESC_VALUE, 208) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_6, 209) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_6, 241) + RELOC_NUMBER (R_SH_SHMEDIA_CODE, 242) + RELOC_NUMBER (R_SH_PT_16, 243) + RELOC_NUMBER (R_SH_IMMS16, 244) + RELOC_NUMBER (R_SH_IMMU16, 245) + RELOC_NUMBER (R_SH_IMM_LOW16, 246) + RELOC_NUMBER (R_SH_IMM_LOW16_PCREL, 247) + RELOC_NUMBER (R_SH_IMM_MEDLOW16, 248) + RELOC_NUMBER (R_SH_IMM_MEDLOW16_PCREL, 249) + RELOC_NUMBER (R_SH_IMM_MEDHI16, 250) + RELOC_NUMBER (R_SH_IMM_MEDHI16_PCREL, 251) + RELOC_NUMBER (R_SH_IMM_HI16, 252) + RELOC_NUMBER (R_SH_IMM_HI16_PCREL, 253) + RELOC_NUMBER (R_SH_64, 254) + RELOC_NUMBER (R_SH_64_PCREL, 255) +END_RELOC_NUMBERS (R_SH_max) + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/sparc.h b/external/gpl3/gdb/dist/include/elf/sparc.h new file mode 100644 index 000000000000..4247151340fd --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/sparc.h @@ -0,0 +1,188 @@ +/* SPARC ELF support for BFD. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2008, 2010 + Free Software Foundation, Inc. + By Doug Evans, Cygnus Support, . + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_SPARC_H +#define _ELF_SPARC_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* These are defined by Sun. */ + +#define EF_SPARC_32PLUS_MASK 0xffff00 /* bits indicating V8+ type */ +#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ +#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ +#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ + +/* This name is used in the V9 ABI. */ +#define EF_SPARC_EXT_MASK 0xffff00 /* reserved for vendor extensions */ + +/* V9 memory models */ +#define EF_SPARCV9_MM 0x3 /* memory model mask */ +#define EF_SPARCV9_TSO 0x0 /* total store ordering */ +#define EF_SPARCV9_PSO 0x1 /* partial store ordering */ +#define EF_SPARCV9_RMO 0x2 /* relaxed store ordering */ + +/* Section indices. */ + +#define SHN_BEFORE SHN_LORESERVE /* Used with SHF_ORDERED and... */ +#define SHN_AFTER (SHN_LORESERVE + 1) /* SHF_LINK_ORDER section flags. */ + +/* Section flags. */ + +#define SHF_ORDERED 0x40000000 /* treat sh_link,sh_info specially */ + +/* Symbol types. */ + +#define STT_REGISTER 13 /* global reg reserved to app. */ + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_sparc_reloc_type) + RELOC_NUMBER (R_SPARC_NONE, 0) + RELOC_NUMBER (R_SPARC_8, 1) + RELOC_NUMBER (R_SPARC_16, 2) + RELOC_NUMBER (R_SPARC_32, 3) + RELOC_NUMBER (R_SPARC_DISP8, 4) + RELOC_NUMBER (R_SPARC_DISP16, 5) + RELOC_NUMBER (R_SPARC_DISP32, 6) + RELOC_NUMBER (R_SPARC_WDISP30, 7) + RELOC_NUMBER (R_SPARC_WDISP22, 8) + RELOC_NUMBER (R_SPARC_HI22, 9) + RELOC_NUMBER (R_SPARC_22, 10) + RELOC_NUMBER (R_SPARC_13, 11) + RELOC_NUMBER (R_SPARC_LO10, 12) + RELOC_NUMBER (R_SPARC_GOT10, 13) + RELOC_NUMBER (R_SPARC_GOT13, 14) + RELOC_NUMBER (R_SPARC_GOT22, 15) + RELOC_NUMBER (R_SPARC_PC10, 16) + RELOC_NUMBER (R_SPARC_PC22, 17) + RELOC_NUMBER (R_SPARC_WPLT30, 18) + RELOC_NUMBER (R_SPARC_COPY, 19) + RELOC_NUMBER (R_SPARC_GLOB_DAT, 20) + RELOC_NUMBER (R_SPARC_JMP_SLOT, 21) + RELOC_NUMBER (R_SPARC_RELATIVE, 22) + RELOC_NUMBER (R_SPARC_UA32, 23) + + /* ??? These 6 relocs are new but not currently used. For binary + compatibility in the sparc64-elf toolchain, we leave them out. + A non-binary upward compatible change is expected for sparc64-elf. */ +#ifndef SPARC64_OLD_RELOCS + /* ??? New relocs on the UltraSPARC. Not sure what they're for yet. */ + RELOC_NUMBER (R_SPARC_PLT32, 24) + RELOC_NUMBER (R_SPARC_HIPLT22, 25) + RELOC_NUMBER (R_SPARC_LOPLT10, 26) + RELOC_NUMBER (R_SPARC_PCPLT32, 27) + RELOC_NUMBER (R_SPARC_PCPLT22, 28) + RELOC_NUMBER (R_SPARC_PCPLT10, 29) +#endif + + /* v9 relocs */ + RELOC_NUMBER (R_SPARC_10, 30) + RELOC_NUMBER (R_SPARC_11, 31) + RELOC_NUMBER (R_SPARC_64, 32) + RELOC_NUMBER (R_SPARC_OLO10, 33) + RELOC_NUMBER (R_SPARC_HH22, 34) + RELOC_NUMBER (R_SPARC_HM10, 35) + RELOC_NUMBER (R_SPARC_LM22, 36) + RELOC_NUMBER (R_SPARC_PC_HH22, 37) + RELOC_NUMBER (R_SPARC_PC_HM10, 38) + RELOC_NUMBER (R_SPARC_PC_LM22, 39) + RELOC_NUMBER (R_SPARC_WDISP16, 40) + RELOC_NUMBER (R_SPARC_WDISP19, 41) + RELOC_NUMBER (R_SPARC_UNUSED_42, 42) + RELOC_NUMBER (R_SPARC_7, 43) + RELOC_NUMBER (R_SPARC_5, 44) + RELOC_NUMBER (R_SPARC_6, 45) + RELOC_NUMBER (R_SPARC_DISP64, 46) + RELOC_NUMBER (R_SPARC_PLT64, 47) + RELOC_NUMBER (R_SPARC_HIX22, 48) + RELOC_NUMBER (R_SPARC_LOX10, 49) + RELOC_NUMBER (R_SPARC_H44, 50) + RELOC_NUMBER (R_SPARC_M44, 51) + RELOC_NUMBER (R_SPARC_L44, 52) + RELOC_NUMBER (R_SPARC_REGISTER, 53) + RELOC_NUMBER (R_SPARC_UA64, 54) + RELOC_NUMBER (R_SPARC_UA16, 55) + + RELOC_NUMBER (R_SPARC_TLS_GD_HI22, 56) + RELOC_NUMBER (R_SPARC_TLS_GD_LO10, 57) + RELOC_NUMBER (R_SPARC_TLS_GD_ADD, 58) + RELOC_NUMBER (R_SPARC_TLS_GD_CALL, 59) + RELOC_NUMBER (R_SPARC_TLS_LDM_HI22, 60) + RELOC_NUMBER (R_SPARC_TLS_LDM_LO10, 61) + RELOC_NUMBER (R_SPARC_TLS_LDM_ADD, 62) + RELOC_NUMBER (R_SPARC_TLS_LDM_CALL, 63) + RELOC_NUMBER (R_SPARC_TLS_LDO_HIX22, 64) + RELOC_NUMBER (R_SPARC_TLS_LDO_LOX10, 65) + RELOC_NUMBER (R_SPARC_TLS_LDO_ADD, 66) + RELOC_NUMBER (R_SPARC_TLS_IE_HI22, 67) + RELOC_NUMBER (R_SPARC_TLS_IE_LO10, 68) + RELOC_NUMBER (R_SPARC_TLS_IE_LD, 69) + RELOC_NUMBER (R_SPARC_TLS_IE_LDX, 70) + RELOC_NUMBER (R_SPARC_TLS_IE_ADD, 71) + RELOC_NUMBER (R_SPARC_TLS_LE_HIX22, 72) + RELOC_NUMBER (R_SPARC_TLS_LE_LOX10, 73) + RELOC_NUMBER (R_SPARC_TLS_DTPMOD32, 74) + RELOC_NUMBER (R_SPARC_TLS_DTPMOD64, 75) + RELOC_NUMBER (R_SPARC_TLS_DTPOFF32, 76) + RELOC_NUMBER (R_SPARC_TLS_DTPOFF64, 77) + RELOC_NUMBER (R_SPARC_TLS_TPOFF32, 78) + RELOC_NUMBER (R_SPARC_TLS_TPOFF64, 79) + + RELOC_NUMBER (R_SPARC_GOTDATA_HIX22, 80) + RELOC_NUMBER (R_SPARC_GOTDATA_LOX10, 81) + RELOC_NUMBER (R_SPARC_GOTDATA_OP_HIX22, 82) + RELOC_NUMBER (R_SPARC_GOTDATA_OP_LOX10, 83) + RELOC_NUMBER (R_SPARC_GOTDATA_OP, 84) + + RELOC_NUMBER (R_SPARC_H34, 85) + RELOC_NUMBER (R_SPARC_SIZE32, 86) + RELOC_NUMBER (R_SPARC_SIZE64, 87) + + EMPTY_RELOC (R_SPARC_max_std) + + RELOC_NUMBER (R_SPARC_JMP_IREL, 248) + RELOC_NUMBER (R_SPARC_IRELATIVE, 249) + RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251) + RELOC_NUMBER (R_SPARC_REV32, 252) + +END_RELOC_NUMBERS (R_SPARC_max) + +/* Relocation macros. */ + +#define ELF64_R_TYPE_DATA(info) \ + (((bfd_signed_vma)(ELF64_R_TYPE(info) >> 8) ^ 0x800000) - 0x800000) +#define ELF64_R_TYPE_ID(info) \ + ((info) & 0xff) +#define ELF64_R_TYPE_INFO(data, type) \ + (((bfd_vma) ((data) & 0xffffff) << 8) | (bfd_vma) (type)) + +/* Values for Elf64_Dyn.d_tag. */ + +#define DT_SPARC_REGISTER 0x70000001 + +#endif /* _ELF_SPARC_H */ diff --git a/external/gpl3/gdb/dist/include/elf/spu.h b/external/gpl3/gdb/dist/include/elf/spu.h new file mode 100644 index 000000000000..0618ec8fcb1d --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/spu.h @@ -0,0 +1,61 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2007, 2009, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_SPU_H +#define _ELF_SPU_H + +#include "elf/reloc-macros.h" + +/* elf32-spu.c depends on these being consecutive. */ +START_RELOC_NUMBERS (elf_spu_reloc_type) + RELOC_NUMBER (R_SPU_NONE, 0) + RELOC_NUMBER (R_SPU_ADDR10, 1) + RELOC_NUMBER (R_SPU_ADDR16, 2) + RELOC_NUMBER (R_SPU_ADDR16_HI, 3) + RELOC_NUMBER (R_SPU_ADDR16_LO, 4) + RELOC_NUMBER (R_SPU_ADDR18, 5) + RELOC_NUMBER (R_SPU_ADDR32, 6) + RELOC_NUMBER (R_SPU_REL16, 7) + RELOC_NUMBER (R_SPU_ADDR7, 8) + RELOC_NUMBER (R_SPU_REL9, 9) + RELOC_NUMBER (R_SPU_REL9I, 10) + RELOC_NUMBER (R_SPU_ADDR10I, 11) + RELOC_NUMBER (R_SPU_ADDR16I, 12) + RELOC_NUMBER (R_SPU_REL32, 13) + RELOC_NUMBER (R_SPU_ADDR16X, 14) + RELOC_NUMBER (R_SPU_PPU32, 15) + RELOC_NUMBER (R_SPU_PPU64, 16) + RELOC_NUMBER (R_SPU_ADD_PIC, 17) +END_RELOC_NUMBERS (R_SPU_max) + +/* Program header extensions */ + +/* Mark a PT_LOAD segment as containing an overlay which should not + initially be loaded. */ +#define PF_OVERLAY (1 << 27) + +/* SPU Dynamic Object Information. */ +#define PT_SPU_INFO 0x70000000 + +/* SPU plugin information */ +#define SPU_PLUGIN_NAME "SPUNAME" +#define SPU_PTNOTE_SPUNAME ".note.spu_name" + +#endif /* _ELF_SPU_H */ diff --git a/external/gpl3/gdb/dist/include/elf/tic6x-attrs.h b/external/gpl3/gdb/dist/include/elf/tic6x-attrs.h new file mode 100644 index 000000000000..21ce1e4f5369 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/tic6x-attrs.h @@ -0,0 +1,35 @@ +/* TI C6X ELF attributes. + Copyright 2010 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Define the TAG macro before including this file; it takes a tag + name and value. */ + +TAG(Tag_ISA, 4) +TAG(Tag_ABI_wchar_t, 6) +TAG(Tag_ABI_stack_align_needed, 8) +TAG(Tag_ABI_stack_align_preserved, 10) +TAG(Tag_ABI_DSBT, 12) +TAG(Tag_ABI_PID, 14) +TAG(Tag_ABI_PIC, 16) +TAG(Tag_ABI_array_object_alignment, 18) +TAG(Tag_ABI_array_object_align_expected, 20) +TAG(Tag_ABI_compatibility, 32) +TAG(Tag_ABI_conformance, 67) diff --git a/external/gpl3/gdb/dist/include/elf/tic6x.h b/external/gpl3/gdb/dist/include/elf/tic6x.h new file mode 100644 index 000000000000..46f43c807071 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/tic6x.h @@ -0,0 +1,161 @@ +/* TI C6X ELF support for BFD. + Copyright 2010, 2011 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_TIC6X_H +#define _ELF_TIC6X_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_tic6x_reloc_type) + RELOC_NUMBER (R_C6000_NONE, 0) + RELOC_NUMBER (R_C6000_ABS32, 1) + RELOC_NUMBER (R_C6000_ABS16, 2) + RELOC_NUMBER (R_C6000_ABS8, 3) + RELOC_NUMBER (R_C6000_PCR_S21, 4) + RELOC_NUMBER (R_C6000_PCR_S12, 5) + RELOC_NUMBER (R_C6000_PCR_S10, 6) + RELOC_NUMBER (R_C6000_PCR_S7, 7) + RELOC_NUMBER (R_C6000_ABS_S16, 8) + RELOC_NUMBER (R_C6000_ABS_L16, 9) + RELOC_NUMBER (R_C6000_ABS_H16, 10) + RELOC_NUMBER (R_C6000_SBR_U15_B, 11) + RELOC_NUMBER (R_C6000_SBR_U15_H, 12) + RELOC_NUMBER (R_C6000_SBR_U15_W, 13) + RELOC_NUMBER (R_C6000_SBR_S16, 14) + RELOC_NUMBER (R_C6000_SBR_L16_B, 15) + RELOC_NUMBER (R_C6000_SBR_L16_H, 16) + RELOC_NUMBER (R_C6000_SBR_L16_W, 17) + RELOC_NUMBER (R_C6000_SBR_H16_B, 18) + RELOC_NUMBER (R_C6000_SBR_H16_H, 19) + RELOC_NUMBER (R_C6000_SBR_H16_W, 20) + RELOC_NUMBER (R_C6000_SBR_GOT_U15_W, 21) + RELOC_NUMBER (R_C6000_SBR_GOT_L16_W, 22) + RELOC_NUMBER (R_C6000_SBR_GOT_H16_W, 23) + RELOC_NUMBER (R_C6000_DSBT_INDEX, 24) + RELOC_NUMBER (R_C6000_PREL31, 25) + RELOC_NUMBER (R_C6000_COPY, 26) + RELOC_NUMBER (R_C6000_JUMP_SLOT, 27) + RELOC_NUMBER (R_C6000_EHTYPE, 28) + RELOC_NUMBER (R_C6000_PCR_H16, 29) + RELOC_NUMBER (R_C6000_PCR_L16, 30) + RELOC_NUMBER (R_C6000_ALIGN, 253) + RELOC_NUMBER (R_C6000_FPHEAD, 254) + RELOC_NUMBER (R_C6000_NOCMP, 255) +END_RELOC_NUMBERS (R_TIC6X_max) + +/* Processor-specific flags. */ + +/* File contains static relocation information. */ +#define EF_C6000_REL 0x1 + +/* Processor-specific section types. */ + +/* Unwind function table for stack unwinding. */ +#define SHT_C6000_UNWIND 0x70000001 + +/* DLL dynamic linking pre-emption map. */ +#define SHT_C6000_PREEMPTMAP 0x70000002 + +/* Object file compatibility attributes. */ +#define SHT_C6000_ATTRIBUTES 0x70000003 + +/* Intermediate code for link-time optimization. */ +#define SHT_TI_ICODE 0x7F000000 + +/* Symbolic cross reference information. */ +#define SHT_TI_XREF 0x7F000001 + +/* Reserved. */ +#define SHT_TI_HANDLER 0x7F000002 + +/* Compressed data for initializing C variables. */ +#define SHT_TI_INITINFO 0x7F000003 + +/* Extended program header attributes. */ +#define SHT_TI_PHATTRS 0x7F000004 + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small data area common symbol. */ +#define SHN_TIC6X_SCOMMON SHN_LORESERVE + +/* Processor-specific segment types. */ + +/* Extended Segment Attributes. */ +#define PT_C6000_PHATTR 0x70000000 + +/* Processor-specific dynamic tags. */ + +/* Undocumented. */ +#define DT_C6000_GSYM_OFFSET 0x6000000D + +/* Undocumented. */ +#define DT_C6000_GSTR_OFFSET 0x6000000F + +/* Statically linked base address of data segment. */ +#define DT_C6000_DSBT_BASE 0x70000000 + +/* Number of entries in this module's DSBT. */ +#define DT_C6000_DSBT_SIZE 0x70000001 + +/* Undocumented. */ +#define DT_C6000_PREEMPTMAP 0x70000002 + +/* The hard-coded DSBT index for this module, if any. */ +#define DT_C6000_DSBT_INDEX 0x70000003 + +/* Extended program header attributes. */ + +/* Terminate a segment. */ +#define PHA_NULL 0x0 + +/* Segment's address bound to the final address. */ +#define PHA_BOUND 0x1 + +/* Segment cannot be further relocated. */ +#define PHA_READONLY 0x2 + +/* Build attributes. */ +enum + { +#define TAG(tag, value) tag = value, +#include "elf/tic6x-attrs.h" +#undef TAG + Tag_C6XABI_last + }; + +/* Values for Tag_ISA. GNU-specific names; the ABI does not specify + names for these values. */ +enum + { + C6XABI_Tag_ISA_none = 0, + C6XABI_Tag_ISA_C62X = 1, + C6XABI_Tag_ISA_C67X = 3, + C6XABI_Tag_ISA_C67XP = 4, + C6XABI_Tag_ISA_C64X = 6, + C6XABI_Tag_ISA_C64XP = 7, + C6XABI_Tag_ISA_C674X = 8 + }; + +#endif /* _ELF_TIC6X_H */ diff --git a/external/gpl3/gdb/dist/include/elf/v850.h b/external/gpl3/gdb/dist/include/elf/v850.h new file mode 100644 index 000000000000..2a0e03ef8229 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/v850.h @@ -0,0 +1,151 @@ +/* V850 ELF support for BFD. + Copyright 1997, 1998, 2000, 2002, 2003, 2004, 2007, 2008, 2010 + Free Software Foundation, Inc. + Created by Michael Meissner, Cygnus Support + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the MIPS ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_V850_H +#define _ELF_V850_H + +/* Processor specific flags for the ELF header e_flags field. */ + +/* Four bit V850 architecture field. */ +#define EF_V850_ARCH 0xf0000000 + +/* v850 code. */ +#define E_V850_ARCH 0x00000000 + +/* v850e code. */ +#define E_V850E_ARCH 0x10000000 + +/* v850e1 code. */ +#define E_V850E1_ARCH 0x20000000 + +/* v850e2 code. */ +#define E_V850E2_ARCH 0x30000000 + +/* v850e2v3 code. */ +#define E_V850E2V3_ARCH 0x40000000 + +/* Flags for the st_other field. */ +#define V850_OTHER_SDA 0x10 /* Symbol had SDA relocations. */ +#define V850_OTHER_ZDA 0x20 /* Symbol had ZDA relocations. */ +#define V850_OTHER_TDA 0x40 /* Symbol had TDA relocations. */ +#define V850_OTHER_ERROR 0x80 /* Symbol had an error reported. */ + +/* V850 relocations. */ +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (v850_reloc_type) + RELOC_NUMBER (R_V850_NONE, 0) + RELOC_NUMBER (R_V850_9_PCREL, 1) + RELOC_NUMBER (R_V850_22_PCREL, 2) + RELOC_NUMBER (R_V850_HI16_S, 3) + RELOC_NUMBER (R_V850_HI16, 4) + RELOC_NUMBER (R_V850_LO16, 5) + RELOC_NUMBER (R_V850_ABS32, 6) + RELOC_NUMBER (R_V850_16, 7) + RELOC_NUMBER (R_V850_8, 8) + RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_SDA_15_16_OFFSET, 10) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_ZDA_16_16_OFFSET, 11) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_ZDA_15_16_OFFSET, 12) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_TDA_6_8_OFFSET, 13) /* For sst.w, sld.w */ + RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14) /* For sst.h, sld.h */ + RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15) /* For sst.b, sld.b */ + RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16) /* For set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17) /* For sld.hu */ + RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18) /* For sld.bu */ + RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19) /* For ld.bu */ + RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20) /* For ld.bu */ + RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21) /* For callt */ + RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22) /* For callt */ + RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_V850_GNU_VTENTRY, 24) + RELOC_NUMBER (R_V850_LONGCALL, 25) + RELOC_NUMBER (R_V850_LONGJUMP, 26) + RELOC_NUMBER (R_V850_ALIGN, 27) + RELOC_NUMBER (R_V850_REL32, 28) + RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29) /* For ld.bu */ + RELOC_NUMBER (R_V850_16_PCREL, 30) /* For loop */ + RELOC_NUMBER (R_V850_17_PCREL, 31) /* For br */ + RELOC_NUMBER (R_V850_23, 32) /* For 23bit ld.[w,h,hu,b,bu],st.[w,h,b] */ + RELOC_NUMBER (R_V850_32_PCREL, 33) /* For jr32, jarl32 */ + RELOC_NUMBER (R_V850_32_ABS, 34) /* For jmp32 */ + RELOC_NUMBER (R_V850_16_SPLIT_OFFSET, 35) /* For ld.bu */ + RELOC_NUMBER (R_V850_16_S1, 36) /* For ld.w, ld.h st.w st.h */ + RELOC_NUMBER (R_V850_LO16_S1, 37) /* For ld.w, ld.h st.w st.h */ + RELOC_NUMBER (R_V850_CALLT_15_16_OFFSET, 38) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER (R_V850_32_GOTPCREL, 39) /* GLOBAL_OFFSET_TABLE from pc */ + RELOC_NUMBER (R_V850_16_GOT, 40) /* GOT ENTRY from gp */ + RELOC_NUMBER (R_V850_32_GOT, 41) + RELOC_NUMBER (R_V850_22_PLT, 42) /* For jr */ + RELOC_NUMBER (R_V850_32_PLT, 43) /* For jr32 */ + RELOC_NUMBER (R_V850_COPY, 44) + RELOC_NUMBER (R_V850_GLOB_DAT, 45) + RELOC_NUMBER (R_V850_JMP_SLOT, 46) + RELOC_NUMBER (R_V850_RELATIVE, 47) + RELOC_NUMBER (R_V850_16_GOTOFF, 48) /* From gp */ + RELOC_NUMBER (R_V850_32_GOTOFF, 49) + RELOC_NUMBER (R_V850_CODE, 50) + RELOC_NUMBER (R_V850_DATA, 51) /* For loop */ + +END_RELOC_NUMBERS (R_V850_max) + + +/* Processor specific section indices. These sections do not actually + exist. Symbols with a st_shndx field corresponding to one of these + values have a special meaning. */ + +/* Small data area common symbol. */ +#define SHN_V850_SCOMMON SHN_LORESERVE + +/* Tiny data area common symbol. */ +#define SHN_V850_TCOMMON (SHN_LORESERVE + 1) + +/* Zero data area common symbol. */ +#define SHN_V850_ZCOMMON (SHN_LORESERVE + 2) + + +/* Processor specific section types. */ + +/* Section contains the .scommon data. */ +#define SHT_V850_SCOMMON 0x70000000 + +/* Section contains the .scommon data. */ +#define SHT_V850_TCOMMON 0x70000001 + +/* Section contains the .scommon data. */ +#define SHT_V850_ZCOMMON 0x70000002 + +/* Processor specific section flags. */ + +/* This section must be in the small data area (pointed to by GP). */ +#define SHF_V850_GPREL 0x10000000 + +/* This section must be in the tiny data area (pointed to by EP). */ +#define SHF_V850_EPREL 0x20000000 + +/* This section must be in the zero data area (pointed to by R0). */ +#define SHF_V850_R0REL 0x40000000 + +#endif /* _ELF_V850_H */ diff --git a/external/gpl3/gdb/dist/include/elf/vax.h b/external/gpl3/gdb/dist/include/elf/vax.h new file mode 100644 index 000000000000..e44c48e7bf09 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/vax.h @@ -0,0 +1,51 @@ +/* VAX ELF support for BFD. + Copyright (C) 2002, 2010 Free Software Foundation, Inc. + Contributed by Matt Thomas . + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_VAX_H +#define _ELF_VAX_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_vax_reloc_type) + RELOC_NUMBER (R_VAX_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_VAX_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_VAX_16, 2) /* Direct 16 bit */ + RELOC_NUMBER (R_VAX_8, 3) /* Direct 8 bit */ + RELOC_NUMBER (R_VAX_PC32, 4) /* PC relative 32 bit */ + RELOC_NUMBER (R_VAX_PC16, 5) /* PC relative 16 bit */ + RELOC_NUMBER (R_VAX_PC8, 6) /* PC relative 8 bit */ + RELOC_NUMBER (R_VAX_GOT32, 7) /* 32 bit PC relative GOT entry */ + RELOC_NUMBER (R_VAX_PLT32, 13) /* 32 bit PC relative PLT address */ + RELOC_NUMBER (R_VAX_COPY, 19) /* Copy symbol at runtime */ + RELOC_NUMBER (R_VAX_GLOB_DAT, 20) /* Create GOT entry */ + RELOC_NUMBER (R_VAX_JMP_SLOT, 21) /* Create PLT entry */ + RELOC_NUMBER (R_VAX_RELATIVE, 22) /* Adjust by program base */ + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_VAX_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_VAX_GNU_VTENTRY, 24) +END_RELOC_NUMBERS (R_VAX_max) + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_VAX_NONPIC 0x0001 /* Object contains non-PIC code */ +#define EF_VAX_DFLOAT 0x0100 /* Object contains D-Float insn. */ +#define EF_VAX_GFLOAT 0x0200 /* Object contains G-Float insn. */ + +#endif diff --git a/external/gpl3/gdb/dist/include/elf/vxworks.h b/external/gpl3/gdb/dist/include/elf/vxworks.h new file mode 100644 index 000000000000..f25f012951ff --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/vxworks.h @@ -0,0 +1,33 @@ +/* VxWorks ELF support for BFD. + Copyright 2007, 2010 + Free Software Foundation, Inc. + + Contributed by Nathan Sidwell + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _ELF_VXWORKS_H +#define _ELF_VXWORKS_H + +#define DT_VX_WRS_TLS_DATA_START 0x60000010 +#define DT_VX_WRS_TLS_DATA_SIZE 0x60000011 +#define DT_VX_WRS_TLS_DATA_ALIGN 0x60000015 +#define DT_VX_WRS_TLS_VARS_START 0x60000012 +#define DT_VX_WRS_TLS_VARS_SIZE 0x60000013 + +#endif /* _ELF_VXWORKS_H */ diff --git a/external/gpl3/gdb/dist/include/elf/x86-64.h b/external/gpl3/gdb/dist/include/elf/x86-64.h new file mode 100644 index 000000000000..56254d25f1d3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/x86-64.h @@ -0,0 +1,88 @@ +/* x86_64 ELF support for BFD. + Copyright (C) 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Jan Hubicka + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_X86_64_H +#define _ELF_X86_64_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_x86_64_reloc_type) + RELOC_NUMBER (R_X86_64_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_X86_64_64, 1) /* Direct 64 bit */ + RELOC_NUMBER (R_X86_64_PC32, 2) /* PC relative 32 bit signed */ + RELOC_NUMBER (R_X86_64_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_X86_64_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_X86_64_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_X86_64_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_X86_64_JUMP_SLOT,7) /* Create PLT entry */ + RELOC_NUMBER (R_X86_64_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_X86_64_GOTPCREL, 9) /* 32 bit signed pc relative + offset to GOT entry */ + RELOC_NUMBER (R_X86_64_32, 10) /* Direct 32 bit zero extended */ + RELOC_NUMBER (R_X86_64_32S, 11) /* Direct 32 bit sign extended */ + RELOC_NUMBER (R_X86_64_16, 12) /* Direct 16 bit zero extended */ + RELOC_NUMBER (R_X86_64_PC16, 13) /* 16 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_8, 14) /* Direct 8 bit sign extended */ + RELOC_NUMBER (R_X86_64_PC8, 15) /* 8 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_DTPMOD64, 16) /* ID of module containing symbol */ + RELOC_NUMBER (R_X86_64_DTPOFF64, 17) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_TPOFF64, 18) /* Offset in initial TLS block */ + RELOC_NUMBER (R_X86_64_TLSGD, 19) /* PC relative offset to GD GOT block */ + RELOC_NUMBER (R_X86_64_TLSLD, 20) /* PC relative offset to LD GOT block */ + RELOC_NUMBER (R_X86_64_DTPOFF32, 21) /* Offset in TLS block */ + RELOC_NUMBER (R_X86_64_GOTTPOFF, 22) /* PC relative offset to IE GOT entry */ + RELOC_NUMBER (R_X86_64_TPOFF32, 23) /* Offset in initial TLS block */ + RELOC_NUMBER (R_X86_64_PC64, 24) /* PC relative 64 bit */ + RELOC_NUMBER (R_X86_64_GOTOFF64, 25) /* 64 bit offset to GOT */ + RELOC_NUMBER (R_X86_64_GOTPC32, 26) /* 32 bit signed pc relative + offset to GOT */ + RELOC_NUMBER (R_X86_64_GOT64, 27) /* 64 bit GOT entry offset */ + RELOC_NUMBER (R_X86_64_GOTPCREL64, 28) /* 64 bit signed pc relative + offset to GOT entry */ + RELOC_NUMBER (R_X86_64_GOTPC64, 29) /* 64 bit signed pc relative + offset to GOT */ + RELOC_NUMBER (R_X86_64_GOTPLT64, 30) /* like GOT64, but indicates + that PLT entry is needed */ + RELOC_NUMBER (R_X86_64_PLTOFF64, 31) /* 64 bit GOT relative offset + to PLT entry */ + /* 32 .. 33 */ + RELOC_NUMBER (R_X86_64_GOTPC32_TLSDESC, 34) + /* 32 bit signed pc relative + offset to TLS descriptor + in the GOT. */ + RELOC_NUMBER (R_X86_64_TLSDESC_CALL, 35) /* Relaxable call through TLS + descriptor. */ + RELOC_NUMBER (R_X86_64_TLSDESC, 36) /* 2x64-bit TLS descriptor. */ + RELOC_NUMBER (R_X86_64_IRELATIVE, 37) /* Adjust indirectly by program base */ + RELOC_NUMBER (R_X86_64_GNU_VTINHERIT, 250) /* GNU C++ hack */ + RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251) /* GNU C++ hack */ +END_RELOC_NUMBERS (R_X86_64_max) + +/* Processor specific section types. */ + +#define SHT_X86_64_UNWIND 0x70000001 /* unwind information */ + +/* Like SHN_COMMON but the symbol will be allocated in the .lbss + section. */ +#define SHN_X86_64_LCOMMON (SHN_LORESERVE + 2) + +#define SHF_X86_64_LARGE 0x10000000 +#endif diff --git a/external/gpl3/gdb/dist/include/elf/xc16x.h b/external/gpl3/gdb/dist/include/elf/xc16x.h new file mode 100644 index 000000000000..b46d903524bb --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/xc16x.h @@ -0,0 +1,40 @@ +/* Infineon XC16X ELF support for BFD. + Copyright 2006, 2010 Free Software Foundation, Inc. + Contributed by KPIT Cummins Infosystems + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_XC16X_H +#define _ELF_XC16X_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xc16x_reloc_type) + RELOC_NUMBER (R_XC16X_NONE, 0) + RELOC_NUMBER (R_XC16X_ABS_8, 1) + RELOC_NUMBER (R_XC16X_ABS_16, 2) + RELOC_NUMBER (R_XC16X_ABS_32, 3) + RELOC_NUMBER (R_XC16X_8_PCREL, 4) + RELOC_NUMBER (R_XC16X_PAG, 5) + RELOC_NUMBER (R_XC16X_POF, 6) + RELOC_NUMBER (R_XC16X_SEG, 7) + RELOC_NUMBER (R_XC16X_SOF, 8) + +END_RELOC_NUMBERS (R_XC16X_max) + +#endif /* _ELF_XC16X_H */ diff --git a/external/gpl3/gdb/dist/include/elf/xstormy16.h b/external/gpl3/gdb/dist/include/elf/xstormy16.h new file mode 100644 index 000000000000..0ae0def86d30 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/xstormy16.h @@ -0,0 +1,57 @@ +/* XSTORMY16 ELF support for BFD. + Copyright (C) 2001, 2002, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_XSTORMY16_H +#define _ELF_XSTORMY16_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xstormy16_reloc_type) + RELOC_NUMBER (R_XSTORMY16_NONE, 0) + + RELOC_NUMBER (R_XSTORMY16_32, 1) + RELOC_NUMBER (R_XSTORMY16_16, 2) + RELOC_NUMBER (R_XSTORMY16_8, 3) + RELOC_NUMBER (R_XSTORMY16_PC32, 4) + RELOC_NUMBER (R_XSTORMY16_PC16, 5) + RELOC_NUMBER (R_XSTORMY16_PC8, 6) + + RELOC_NUMBER (R_XSTORMY16_REL_12, 7) + RELOC_NUMBER (R_XSTORMY16_24, 8) + RELOC_NUMBER (R_XSTORMY16_FPTR16, 9) + + RELOC_NUMBER (R_XSTORMY16_LO16, 10) + RELOC_NUMBER (R_XSTORMY16_HI16, 11) + RELOC_NUMBER (R_XSTORMY16_12, 12) + + RELOC_NUMBER (R_XSTORMY16_GNU_VTINHERIT, 128) + RELOC_NUMBER (R_XSTORMY16_GNU_VTENTRY, 129) +END_RELOC_NUMBERS (R_XSTORMY16_max) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & XSTORMY16_INSN_MASK) == XSTORMY16_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32xstormy16.sh'. */ +#define XSTORMY16_DATA_MASK 0xffc00000 +#define XSTORMY16_DATA_VALUE 0x00000000 +#define XSTORMY16_INSN_MASK 0xffc00000 +#define XSTORMY16_INSN_VALUE 0x00400000 + +#endif /* _ELF_XSTORMY16_H */ diff --git a/external/gpl3/gdb/dist/include/elf/xtensa.h b/external/gpl3/gdb/dist/include/elf/xtensa.h new file mode 100644 index 000000000000..0d35f7abc046 --- /dev/null +++ b/external/gpl3/gdb/dist/include/elf/xtensa.h @@ -0,0 +1,208 @@ +/* Xtensa ELF support for BFD. + Copyright 2003, 2004, 2007, 2008, 2010 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +/* This file holds definitions specific to the Xtensa ELF ABI. */ + +#ifndef _ELF_XTENSA_H +#define _ELF_XTENSA_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_xtensa_reloc_type) + RELOC_NUMBER (R_XTENSA_NONE, 0) + RELOC_NUMBER (R_XTENSA_32, 1) + RELOC_NUMBER (R_XTENSA_RTLD, 2) + RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3) + RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4) + RELOC_NUMBER (R_XTENSA_RELATIVE, 5) + RELOC_NUMBER (R_XTENSA_PLT, 6) + RELOC_NUMBER (R_XTENSA_OP0, 8) + RELOC_NUMBER (R_XTENSA_OP1, 9) + RELOC_NUMBER (R_XTENSA_OP2, 10) + RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11) + RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12) + RELOC_NUMBER (R_XTENSA_32_PCREL, 14) + RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15) + RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16) + RELOC_NUMBER (R_XTENSA_DIFF8, 17) + RELOC_NUMBER (R_XTENSA_DIFF16, 18) + RELOC_NUMBER (R_XTENSA_DIFF32, 19) + RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20) + RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21) + RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22) + RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23) + RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24) + RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25) + RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26) + RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27) + RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28) + RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29) + RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30) + RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31) + RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32) + RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33) + RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34) + RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35) + RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36) + RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37) + RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38) + RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39) + RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40) + RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41) + RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42) + RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43) + RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44) + RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45) + RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46) + RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47) + RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48) + RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49) + RELOC_NUMBER (R_XTENSA_TLSDESC_FN, 50) + RELOC_NUMBER (R_XTENSA_TLSDESC_ARG, 51) + RELOC_NUMBER (R_XTENSA_TLS_DTPOFF, 52) + RELOC_NUMBER (R_XTENSA_TLS_TPOFF, 53) + RELOC_NUMBER (R_XTENSA_TLS_FUNC, 54) + RELOC_NUMBER (R_XTENSA_TLS_ARG, 55) + RELOC_NUMBER (R_XTENSA_TLS_CALL, 56) +END_RELOC_NUMBERS (R_XTENSA_max) + +/* Processor-specific flags for the ELF header e_flags field. */ + +/* Four-bit Xtensa machine type field. */ +#define EF_XTENSA_MACH 0x0000000f + +/* Various CPU types. */ +#define E_XTENSA_MACH 0x00000000 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. + Highly unlikely, but what the heck. */ + +#define EF_XTENSA_XT_INSN 0x00000100 +#define EF_XTENSA_XT_LIT 0x00000200 + + +/* Processor-specific dynamic array tags. */ + +/* Offset of the table that records the GOT location(s). */ +#define DT_XTENSA_GOT_LOC_OFF 0x70000000 + +/* Number of entries in the GOT location table. */ +#define DT_XTENSA_GOT_LOC_SZ 0x70000001 + + +/* Definitions for instruction and literal property tables. The + tables for ".gnu.linkonce.*" sections are placed in the following + sections: + + instruction tables: .gnu.linkonce.x.* + literal tables: .gnu.linkonce.p.* +*/ + +#define XTENSA_INSN_SEC_NAME ".xt.insn" +#define XTENSA_LIT_SEC_NAME ".xt.lit" +#define XTENSA_PROP_SEC_NAME ".xt.prop" + +typedef struct property_table_entry_t +{ + bfd_vma address; + bfd_vma size; + flagword flags; +} property_table_entry; + +/* Flags in the property tables to specify whether blocks of memory are + literals, instructions, data, or unreachable. For instructions, + blocks that begin loop targets and branch targets are designated. + Blocks that do not allow density instructions, instruction reordering + or transformation are also specified. Finally, for branch targets, + branch target alignment priority is included. Alignment of the next + block is specified in the current block and the size of the current + block does not include any fill required to align to the next + block. */ + +#define XTENSA_PROP_LITERAL 0x00000001 +#define XTENSA_PROP_INSN 0x00000002 +#define XTENSA_PROP_DATA 0x00000004 +#define XTENSA_PROP_UNREACHABLE 0x00000008 +/* Instruction-only properties at beginning of code. */ +#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 +#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 +/* Instruction-only properties about code. */ +#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 +#define XTENSA_PROP_INSN_NO_REORDER 0x00000080 +/* Historically, NO_TRANSFORM was a property of instructions, + but it should apply to literals under certain circumstances. */ +#define XTENSA_PROP_NO_TRANSFORM 0x00000100 + +/* Branch target alignment information. This transmits information + to the linker optimization about the priority of aligning a + particular block for branch target alignment: None, low priority, + high priority, or required. These only need to be checked in + instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. + Common usage is: + + switch (GET_XTENSA_PROP_BT_ALIGN(flags)) + case XTENSA_PROP_BT_ALIGN_NONE: + case XTENSA_PROP_BT_ALIGN_LOW: + case XTENSA_PROP_BT_ALIGN_HIGH: + case XTENSA_PROP_BT_ALIGN_REQUIRE: +*/ +#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 + +/* No branch target alignment. */ +#define XTENSA_PROP_BT_ALIGN_NONE 0x0 +/* Low priority branch target alignment. */ +#define XTENSA_PROP_BT_ALIGN_LOW 0x1 +/* High priority branch target alignment. */ +#define XTENSA_PROP_BT_ALIGN_HIGH 0x2 +/* Required branch target alignment. */ +#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 + +#define GET_XTENSA_PROP_BT_ALIGN(flag) \ + (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) +#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ + (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ + (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) + +/* Alignment is specified in the block BEFORE the one that needs + alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to + get the required alignment specified as a power of 2. Use + SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required + alignment. Be careful of side effects since the SET will evaluate + flags twice. Also, note that the SIZE of a block in the property + table does not include the alignment size, so the alignment fill + must be calculated to determine if two blocks are contiguous. + TEXT_ALIGN is not currently implemented but is a placeholder for a + possible future implementation. */ + +#define XTENSA_PROP_ALIGN 0x00000800 + +#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 + +#define GET_XTENSA_PROP_ALIGNMENT(flag) \ + (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) +#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ + (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ + (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) + +#define XTENSA_PROP_INSN_ABSLIT 0x00020000 + +#endif /* _ELF_XTENSA_H */ diff --git a/external/gpl3/gdb/dist/include/fibheap.h b/external/gpl3/gdb/dist/include/fibheap.h new file mode 100644 index 000000000000..a3d09dd9db8d --- /dev/null +++ b/external/gpl3/gdb/dist/include/fibheap.h @@ -0,0 +1,95 @@ +/* A Fibonacci heap datatype. + Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2009 + Free Software Foundation, Inc. + Contributed by Daniel Berlin (dan@cgsoftware.com). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* Fibonacci heaps are somewhat complex, but, there's an article in + DDJ that explains them pretty well: + + http://www.ddj.com/articles/1997/9701/9701o/9701o.htm?topic=algoritms + + Introduction to algorithms by Corman and Rivest also goes over them. + + The original paper that introduced them is "Fibonacci heaps and their + uses in improved network optimization algorithms" by Tarjan and + Fredman (JACM 34(3), July 1987). + + Amortized and real worst case time for operations: + + ExtractMin: O(lg n) amortized. O(n) worst case. + DecreaseKey: O(1) amortized. O(lg n) worst case. + Insert: O(2) amortized. O(1) actual. + Union: O(1) amortized. O(1) actual. */ + +#ifndef _FIBHEAP_H_ +#define _FIBHEAP_H_ + +#include "ansidecl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef long fibheapkey_t; + +typedef struct fibheap +{ + size_t nodes; + struct fibnode *min; + struct fibnode *root; +} *fibheap_t; + +typedef struct fibnode +{ + struct fibnode *parent; + struct fibnode *child; + struct fibnode *left; + struct fibnode *right; + fibheapkey_t key; + void *data; +#if defined (__GNUC__) && (!defined (SIZEOF_INT) || SIZEOF_INT < 4) + __extension__ unsigned long int degree : 31; + __extension__ unsigned long int mark : 1; +#else + unsigned int degree : 31; + unsigned int mark : 1; +#endif +} *fibnode_t; + +extern fibheap_t fibheap_new (void); +extern fibnode_t fibheap_insert (fibheap_t, fibheapkey_t, void *); +extern int fibheap_empty (fibheap_t); +extern fibheapkey_t fibheap_min_key (fibheap_t); +extern fibheapkey_t fibheap_replace_key (fibheap_t, fibnode_t, + fibheapkey_t); +extern void *fibheap_replace_key_data (fibheap_t, fibnode_t, + fibheapkey_t, void *); +extern void *fibheap_extract_min (fibheap_t); +extern void *fibheap_min (fibheap_t); +extern void *fibheap_replace_data (fibheap_t, fibnode_t, void *); +extern void *fibheap_delete_node (fibheap_t, fibnode_t); +extern void fibheap_delete (fibheap_t); +extern fibheap_t fibheap_union (fibheap_t, fibheap_t); + +#ifdef __cplusplus +} +#endif + +#endif /* _FIBHEAP_H_ */ diff --git a/external/gpl3/gdb/dist/include/filenames.h b/external/gpl3/gdb/dist/include/filenames.h new file mode 100644 index 000000000000..d4955df661cf --- /dev/null +++ b/external/gpl3/gdb/dist/include/filenames.h @@ -0,0 +1,83 @@ +/* Macros for taking apart, interpreting and processing file names. + + These are here because some non-Posix (a.k.a. DOSish) systems have + drive letter brain-damage at the beginning of an absolute file name, + use forward- and back-slash in path names interchangeably, and + some of them have case-insensitive file names. + + Copyright 2000, 2001, 2007, 2010 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef FILENAMES_H +#define FILENAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__MSDOS__) || defined(_WIN32) || defined(__OS2__) || defined (__CYGWIN__) +# ifndef HAVE_DOS_BASED_FILE_SYSTEM +# define HAVE_DOS_BASED_FILE_SYSTEM 1 +# endif +# define HAS_DRIVE_SPEC(f) HAS_DOS_DRIVE_SPEC (f) +# define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c) +# define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f) +#else /* not DOSish */ +# define HAS_DRIVE_SPEC(f) (0) +# define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c) +# define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f) +#endif + +#define IS_DIR_SEPARATOR_1(dos_based, c) \ + (((c) == '/') \ + || (((c) == '\\') && (dos_based))) + +#define HAS_DRIVE_SPEC_1(dos_based, f) \ + ((f)[0] && ((f)[1] == ':') && (dos_based)) + +/* Remove the drive spec from F, assuming HAS_DRIVE_SPEC (f). + The result is a pointer to the remainder of F. */ +#define STRIP_DRIVE_SPEC(f) ((f) + 2) + +#define IS_DOS_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (1, c) +#define IS_DOS_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (1, f) +#define HAS_DOS_DRIVE_SPEC(f) HAS_DRIVE_SPEC_1 (1, f) + +#define IS_UNIX_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (0, c) +#define IS_UNIX_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (0, f) + +/* Note that when DOS_BASED is true, IS_ABSOLUTE_PATH accepts d:foo as + well, although it is only semi-absolute. This is because the users + of IS_ABSOLUTE_PATH want to know whether to prepend the current + working directory to a file name, which should not be done with a + name like d:foo. */ +#define IS_ABSOLUTE_PATH_1(dos_based, f) \ + (IS_DIR_SEPARATOR_1 (dos_based, (f)[0]) \ + || HAS_DRIVE_SPEC_1 (dos_based, f)) + +extern int filename_cmp (const char *s1, const char *s2); +#define FILENAME_CMP(s1, s2) filename_cmp(s1, s2) + +extern int filename_ncmp (const char *s1, const char *s2, + size_t n); + +#ifdef __cplusplus +} +#endif + +#endif /* FILENAMES_H */ diff --git a/external/gpl3/gdb/dist/include/floatformat.h b/external/gpl3/gdb/dist/include/floatformat.h new file mode 100644 index 000000000000..b5951644ea51 --- /dev/null +++ b/external/gpl3/gdb/dist/include/floatformat.h @@ -0,0 +1,151 @@ +/* IEEE floating point support declarations, for GDB, the GNU Debugger. + Copyright 1991, 1994, 1995, 1997, 2000, 2003, 2005, 2010 + Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#if !defined (FLOATFORMAT_H) +#define FLOATFORMAT_H 1 + +#include "ansidecl.h" + +/* A floatformat consists of a sign bit, an exponent and a mantissa. Once the + bytes are concatenated according to the byteorder flag, then each of those + fields is contiguous. We number the bits with 0 being the most significant + (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field + contains with the *_start and *_len fields. */ + +/* What is the order of the bytes? */ + +enum floatformat_byteorders { + /* Standard little endian byte order. + EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */ + floatformat_little, + + /* Standard big endian byte order. + EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */ + floatformat_big, + + /* Little endian byte order but big endian word order. + EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */ + floatformat_littlebyte_bigword, + + /* VAX byte order. Little endian byte order with 16-bit words. The + following example is an illustration of the byte order only; VAX + doesn't have a fully IEEE compliant floating-point format. + EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */ + floatformat_vax +}; + +enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no }; + +struct floatformat +{ + enum floatformat_byteorders byteorder; + unsigned int totalsize; /* Total size of number in bits */ + + /* Sign bit is always one bit long. 1 means negative, 0 means positive. */ + unsigned int sign_start; + + unsigned int exp_start; + unsigned int exp_len; + /* Bias added to a "true" exponent to form the biased exponent. It + is intentionally signed as, otherwize, -exp_bias can turn into a + very large number (e.g., given the exp_bias of 0x3fff and a 64 + bit long, the equation (long)(1 - exp_bias) evaluates to + 4294950914) instead of -16382). */ + int exp_bias; + /* Exponent value which indicates NaN. This is the actual value stored in + the float, not adjusted by the exp_bias. This usually consists of all + one bits. */ + unsigned int exp_nan; + + unsigned int man_start; + unsigned int man_len; + + /* Is the integer bit explicit or implicit? */ + enum floatformat_intbit intbit; + + /* Internal name for debugging. */ + const char *name; + + /* Validator method. */ + int (*is_valid) (const struct floatformat *fmt, const void *from); + + /* Is the format actually the sum of two smaller floating point + formats (IBM long double, as described in + gcc/config/rs6000/darwin-ldouble-format)? If so, this is the + smaller format in question, and the fields sign_start through + intbit describe the first half. If not, this is NULL. */ + const struct floatformat *split_half; +}; + +/* floatformats for IEEE single and double, big and little endian. */ + +extern const struct floatformat floatformat_ieee_half_big; +extern const struct floatformat floatformat_ieee_half_little; +extern const struct floatformat floatformat_ieee_single_big; +extern const struct floatformat floatformat_ieee_single_little; +extern const struct floatformat floatformat_ieee_double_big; +extern const struct floatformat floatformat_ieee_double_little; + +/* floatformat for ARM IEEE double, little endian bytes and big endian words */ + +extern const struct floatformat floatformat_ieee_double_littlebyte_bigword; + +/* floatformats for VAX. */ + +extern const struct floatformat floatformat_vax_f; +extern const struct floatformat floatformat_vax_d; +extern const struct floatformat floatformat_vax_g; + +/* floatformats for various extendeds. */ + +extern const struct floatformat floatformat_i387_ext; +extern const struct floatformat floatformat_m68881_ext; +extern const struct floatformat floatformat_i960_ext; +extern const struct floatformat floatformat_m88110_ext; +extern const struct floatformat floatformat_m88110_harris_ext; +extern const struct floatformat floatformat_arm_ext_big; +extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; +/* IA-64 Floating Point register spilt into memory. */ +extern const struct floatformat floatformat_ia64_spill_big; +extern const struct floatformat floatformat_ia64_spill_little; +extern const struct floatformat floatformat_ia64_quad_big; +extern const struct floatformat floatformat_ia64_quad_little; +/* IBM long double (double+double). */ +extern const struct floatformat floatformat_ibm_long_double; + +/* Convert from FMT to a double. + FROM is the address of the extended float. + Store the double in *TO. */ + +extern void +floatformat_to_double (const struct floatformat *, const void *, double *); + +/* The converse: convert the double *FROM to FMT + and store where TO points. */ + +extern void +floatformat_from_double (const struct floatformat *, const double *, void *); + +/* Return non-zero iff the data at FROM is a valid number in format FMT. */ + +extern int +floatformat_is_valid (const struct floatformat *fmt, const void *from); + +#endif /* defined (FLOATFORMAT_H) */ diff --git a/external/gpl3/gdb/dist/include/fnmatch.h b/external/gpl3/gdb/dist/include/fnmatch.h new file mode 100644 index 000000000000..5b9953ca3f52 --- /dev/null +++ b/external/gpl3/gdb/dist/include/fnmatch.h @@ -0,0 +1,70 @@ +/* Copyright 1991, 1992, 1993, 1996 Free Software Foundation, Inc. + +NOTE: The canonical source of this file is maintained with the GNU C Library. +Bugs can be reported to bug-glibc@prep.ai.mit.edu. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef _FNMATCH_H + +#define _FNMATCH_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__cplusplus) || (defined (__STDC__) && __STDC__) +#undef __P +#define __P(args) args +#else /* Not C++ or ANSI C. */ +#undef __P +#define __P(args) () +/* We can get away without defining `const' here only because in this file + it is used only inside the prototype for `fnmatch', which is elided in + non-ANSI C where `const' is problematical. */ +#endif /* C++ or ANSI C. */ + + +/* We #undef these before defining them because some losing systems + (HP-UX A.08.07 for example) define these in . */ +#undef FNM_PATHNAME +#undef FNM_NOESCAPE +#undef FNM_PERIOD + +/* Bits set in the FLAGS argument to `fnmatch'. */ +#define FNM_PATHNAME (1 << 0) /* No wildcard can ever match `/'. */ +#define FNM_NOESCAPE (1 << 1) /* Backslashes don't quote special chars. */ +#define FNM_PERIOD (1 << 2) /* Leading `.' is matched only explicitly. */ + +#if !defined (_POSIX_C_SOURCE) || _POSIX_C_SOURCE < 2 || defined (_GNU_SOURCE) +#define FNM_FILE_NAME FNM_PATHNAME /* Preferred GNU name. */ +#define FNM_LEADING_DIR (1 << 3) /* Ignore `/...' after a match. */ +#define FNM_CASEFOLD (1 << 4) /* Compare without regard to case. */ +#endif + +/* Value returned by `fnmatch' if STRING does not match PATTERN. */ +#define FNM_NOMATCH 1 + +/* Match STRING against the filename pattern PATTERN, + returning zero if it matches, FNM_NOMATCH if not. */ +extern int fnmatch __P ((const char *__pattern, const char *__string, + int __flags)); + +#ifdef __cplusplus +} +#endif + +#endif /* fnmatch.h */ diff --git a/external/gpl3/gdb/dist/include/fopen-bin.h b/external/gpl3/gdb/dist/include/fopen-bin.h new file mode 100644 index 000000000000..b868f63d46d1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/fopen-bin.h @@ -0,0 +1,27 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + [Update] + + This version is for "binary" systems, where text and binary files are + different. An example is Mess-Dose. Many Unix systems could also + cope with a "b" in the string, indicating binary files, but some reject this + (and thereby don't conform to ANSI C, but what else is new?). + + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "rb" +#define FOPEN_WB "wb" +#define FOPEN_AB "ab" +#define FOPEN_RUB "r+b" +#define FOPEN_WUB "w+b" +#define FOPEN_AUB "a+b" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/external/gpl3/gdb/dist/include/fopen-same.h b/external/gpl3/gdb/dist/include/fopen-same.h new file mode 100644 index 000000000000..0f37529d33e0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/fopen-same.h @@ -0,0 +1,27 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + [Update] + + This version is for "same" systems, where text and binary files are + the same. An example is Unix. Many Unix systems could also add a + "b" to the string, indicating binary files, but some reject this + (and thereby don't conform to ANSI C, but what else is new?). + + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "r" +#define FOPEN_WB "w" +#define FOPEN_AB "a" +#define FOPEN_RUB "r+" +#define FOPEN_WUB "w+" +#define FOPEN_AUB "a+" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/external/gpl3/gdb/dist/include/fopen-vms.h b/external/gpl3/gdb/dist/include/fopen-vms.h new file mode 100644 index 000000000000..453a13b175d1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/fopen-vms.h @@ -0,0 +1,24 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + [Update] + + This version is for VMS systems, where text and binary files are + different. + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "rb,rfm=udf,rat=none" +#define FOPEN_WB "wb,rfm=udf,rat=none" +#define FOPEN_AB "ab,rfm=udf,rat=none" +#define FOPEN_RUB "r+b,rfm=udf,rat=none" +#define FOPEN_WUB "w+b,rfm=udf,rat=none" +#define FOPEN_AUB "a+b,rfm=udf,rat=none" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/external/gpl3/gdb/dist/include/gdb/ChangeLog b/external/gpl3/gdb/dist/include/gdb/ChangeLog new file mode 100644 index 000000000000..8b31e114759d --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/ChangeLog @@ -0,0 +1,226 @@ +2011-03-05 Mike Frysinger + + * sim-bfin.h: New file. + +2011-01-11 Andrew Burgess + + * remote-sim.h (sim_store_register): Update the API + documentation for this function. + +2010-09-06 Pedro Alves + + * signals.def: Replace all ANY uses by SET with specific numbers. + * signals.h (ANY): Remove. + +2010-07-31 Jan Kratochvil + + * signals.h (enum target_signal): Move the content to signals.def. + Include it. + * signals.def: New file. + +2010-06-24 Kevin Buettner + + * sim-rx.h (sim_rx_regnum): Add sim_rx_acc_regnum. Adjust + register order. + +2010-04-13 Mike Frysinger + + * callback.h: Strip PARAMS from prototypes. + * remote-sim.h: Likewise. + +2010-04-13 Mike Frysinger + + * remote-sim.h (sim_write): Add const to buf arg. + +2009-11-24 DJ Delorie + + * sim-rx.h: New. + +2009-05-18 Jon Beniston + + * sim-lm32.h: New file. + +2009-01-07 Hans-Peter Nilsson + + * callback.h (struct host_callback_struct): Mark member error as + pointing to a noreturn function. + +2008-02-12 M Ranga Swami Reddy + + * sim-cr16.h: New file. + +2008-01-01 Daniel Jacobowitz + + Updated copyright notices for most files. + +2007-10-15 Daniel Jacobowitz + + * sim-ppc.h (sim_spr_register_name): New prototype. + +2007-10-11 Jesper Nilsson + + * callback.h (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add prototypes. + +2007-08-23 Joel Brobecker + + Switch the license of all .h files to GPLv3. + +2007-01-09 Daniel Jacobowitz + + Updated copyright notices for most files. + +2005-07-08 Ben Elliston + + * callback.h: Remove ANSI_PROTOTYPES conditional code. + +2005-01-28 Hans-Peter Nilsson + + * callback.h (struct host_callback_struct): New members pipe, + pipe_empty, pipe_nonempty, ispipe, pipe_buffer and + target_sizeof_int. + (CB_SYS_pipe): New macro. + + * callback.h: Include "bfd.h". + (struct host_callback_struct): New member target_endian. + (cb_store_target_endian): Declare. + +2004-12-15 Hans-Peter Nilsson + + * callback.h (CB_SYS_truncate, CB_SYS_ftruncate): New macros. + +2004-12-13 Hans-Peter Nilsson + + * callback.h (struct host_callback_struct): New member lstat. + (CB_SYS_lstat): New macro. + (CB_SYS_rename): New macro. + +2004-09-08 Michael Snyder + + Commited by Corinna Vinschen + * sim-sh.h: Add new sh2a banked registers. + +2004-08-04 Andrew Cagney + + * sim-ppc.h: Add extern "C" wrapper. + (enum sim_ppc_regnum): Add full list of SPRs. + +2004-08-04 Jim Blandy + + * sim-ppc.h: New file. + +2004-06-25 J"orn Rennecke + + * callback.h (host_callback_struct): Replace members fdopen and + alwaysopen with fd_buddy. + [sim/common: * callback.c: Changed all users. ] + +2003-10-31 Kevin Buettner + + * sim-frv.h: New file. + +2003-10-15 J"orn Rennecke + + * callback.h (struct host_callback_struct): New members ftruncate + and truncate. + +2003-06-10 Corinna Vinschen + + * gdb/fileio.h: New file. + +2003-05-07 Andrew Cagney + + * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. + (sim_d10v_translate_imap_addr): Add regcache parameter. + (sim_d10v_translate_dmap_addr): Ditto. + +2003-03-27 Nick Clifton + + * sim-arm.h (sim_arm_regs): Add iWMMXt registers. + +2003-03-20 Nick Clifton + + * sim-arm.h (sim_arm_regs): Add Maverick co-processor + registers. + +2003-02-27 Andrew Cagney + + * remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename + _bfd to bfd. + +2003-02-20 Andrew Cagney + + * remote-sim.h (SIM_RC): Delete unused SIM_RC_UNKNOWN_BREAKPOINT, + SIM_RC_INSUFFICIENT_RESOURCES and SIM_RC_DUPLICATE_BREAKPOINT. + (sim_set_breakpoint, sim_clear_breakpoint): Delete declarations. + (sim_clear_all_breakpoints, sim_enable_breakpoint): Ditto. + (sim_enable_all_breakpoints, sim_disable_breakpoint): Ditto. + (sim_disable_all_breakpoints): Ditto. + +2002-12-26 Kazu Hirata + + * sim-h8300.h: Remove ^M. + +2002-07-29 Andrey Volkov + + * sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_ + prefix. + +2002-07-23 Andrey Volkov + + * sim-h8300.h: New file. + +2002-07-17 Andrew Cagney + + * remote-sim.h: Update copyright. + (sim_set_callbacks, sim_size, sim_trace) + (sim_set_trace, sim_set_profile_size, sim_kill): Delete. Moved to + "sim/common/run-sim.h". + +Wed Jul 17 19:36:38 2002 J"orn Rennecke + + * sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp, + renumbering the sh-dsp registers to use distinct numbers. + +2002-06-15 Andrew Cagney + + * sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum. + +2002-06-12 Andrew Cagney + + * sim-arm.h: New file. + +2002-06-08 Andrew Cagney + + * callback.h: Copy to here from directory above. + * remote-sim.h: Copy to here from directory above. + +2002-06-01 Andrew Cagney + + * sim-d10v.h (sim_d10v_regs): Expand to include all registers. + Update copyright. + +2002-05-23 Andrew Cagney + + * sim-d10v.h: New file. Moved from include/sim-d10v.h. + +2002-05-10 Elena Zannoni + + * sim-sh.h: New file, for sh gdb<->sim interface. + +2002-05-09 Daniel Jacobowitz + + * signals.h: Update comments. + (enum target_signal): Remove conditional compilation around + Mach-specific signals. Move them to after TARGET_SIGNAL_DEFAULT. + +2002-03-10 Daniel Jacobowitz + + * signals.h: New file, from gdb/defs.h. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/gdb/callback.h b/external/gpl3/gdb/dist/include/gdb/callback.h new file mode 100644 index 000000000000..a1f79f94de4e --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/callback.h @@ -0,0 +1,330 @@ +/* Remote target system call callback support. + Copyright 1997, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* This interface isn't intended to be specific to any particular kind + of remote (hardware, simulator, whatever). As such, support for it + (e.g. sim/common/callback.c) should *not* live in the simulator source + tree, nor should it live in the gdb source tree. */ + +/* There are various ways to handle system calls: + + 1) Have a simulator intercept the appropriate trap instruction and + directly perform the system call on behalf of the target program. + This is the typical way of handling system calls for embedded targets. + [Handling system calls for embedded targets isn't that much of an + oxymoron as running compiler testsuites make use of the capability.] + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_USER. + + 2) Have a simulator emulate the hardware as much as possible. + If the program running on the real hardware communicates with some sort + of target manager, one would want to be able to run this program on the + simulator as well. + + This method of system call handling is done when STATE_ENVIRONMENT + is ENVIRONMENT_OPERATING. +*/ + +#ifndef CALLBACK_H +#define CALLBACK_H + +/* ??? The reason why we check for va_start here should be documented. */ + +#ifndef va_start +#include +#include +#endif +/* Needed for enum bfd_endian. */ +#include "bfd.h" + +/* Mapping of host/target values. */ +/* ??? For debugging purposes, one might want to add a string of the + name of the symbol. */ + +typedef struct { + int host_val; + int target_val; +} CB_TARGET_DEFS_MAP; + +#define MAX_CALLBACK_FDS 10 + +/* Forward decl for stat/fstat. */ +struct stat; + +typedef struct host_callback_struct host_callback; + +struct host_callback_struct +{ + int (*close) (host_callback *,int); + int (*get_errno) (host_callback *); + int (*isatty) (host_callback *, int); + int (*lseek) (host_callback *, int, long , int); + int (*open) (host_callback *, const char*, int mode); + int (*read) (host_callback *,int, char *, int); + int (*read_stdin) ( host_callback *, char *, int); + int (*rename) (host_callback *, const char *, const char *); + int (*system) (host_callback *, const char *); + long (*time) (host_callback *, long *); + int (*unlink) (host_callback *, const char *); + int (*write) (host_callback *,int, const char *, int); + int (*write_stdout) (host_callback *, const char *, int); + void (*flush_stdout) (host_callback *); + int (*write_stderr) (host_callback *, const char *, int); + void (*flush_stderr) (host_callback *); + int (*stat) (host_callback *, const char *, struct stat *); + int (*fstat) (host_callback *, int, struct stat *); + int (*lstat) (host_callback *, const char *, struct stat *); + int (*ftruncate) (host_callback *, int, long); + int (*truncate) (host_callback *, const char *, long); + int (*pipe) (host_callback *, int *); + + /* Called by the framework when a read call has emptied a pipe buffer. */ + void (*pipe_empty) (host_callback *, int read_fd, int write_fd); + + /* Called by the framework when a write call makes a pipe buffer + non-empty. */ + void (*pipe_nonempty) (host_callback *, int read_fd, int write_fd); + + /* When present, call to the client to give it the oportunity to + poll any io devices for a request to quit (indicated by a nonzero + return value). */ + int (*poll_quit) (host_callback *); + + /* Used when the target has gone away, so we can close open + handles and free memory etc etc. */ + int (*shutdown) (host_callback *); + int (*init) (host_callback *); + + /* depreciated, use vprintf_filtered - Talk to the user on a console. */ + void (*printf_filtered) (host_callback *, const char *, ...); + + /* Talk to the user on a console. */ + void (*vprintf_filtered) (host_callback *, const char *, va_list); + + /* Same as vprintf_filtered but to stderr. */ + void (*evprintf_filtered) (host_callback *, const char *, va_list); + + /* Print an error message and "exit". + In the case of gdb "exiting" means doing a longjmp back to the main + command loop. */ + void (*error) (host_callback *, const char *, ...) +#ifdef __GNUC__ + __attribute__ ((__noreturn__)) +#endif + ; + + int last_errno; /* host format */ + + int fdmap[MAX_CALLBACK_FDS]; + /* fd_buddy is used to contruct circular lists of target fds that point to + the same host fd. A uniquely mapped fd points to itself; for a closed + one, fd_buddy has the value -1. The host file descriptors for stdin / + stdout / stderr are never closed by the simulators, so they are put + in a special fd_buddy circular list which also has MAX_CALLBACK_FDS + as a member. */ + /* ??? We don't have a callback entry for dup, although it is trival to + implement now. */ + short fd_buddy[MAX_CALLBACK_FDS+1]; + + /* 0 = none, >0 = reader (index of writer), + <0 = writer (negative index of reader). + If abs (ispipe[N]) == N, then N is an end of a pipe whose other + end is closed. */ + short ispipe[MAX_CALLBACK_FDS]; + + /* A writer stores the buffer at its index. Consecutive writes + realloc the buffer and add to the size. The reader indicates the + read part in its .size, until it has consumed it all, at which + point it deallocates the buffer and zeroes out both sizes. */ + struct pipe_write_buffer + { + int size; + char *buffer; + } pipe_buffer[MAX_CALLBACK_FDS]; + + /* System call numbers. */ + CB_TARGET_DEFS_MAP *syscall_map; + /* Errno values. */ + CB_TARGET_DEFS_MAP *errno_map; + /* Flags to the open system call. */ + CB_TARGET_DEFS_MAP *open_map; + /* Signal numbers. */ + CB_TARGET_DEFS_MAP *signal_map; + /* Layout of `stat' struct. + The format is a series of "name,length" pairs separated by colons. + Empty space is indicated with a `name' of "space". + All padding must be explicitly mentioned. + Lengths are in bytes. If this needs to be extended to bits, + use "name.bits". + Example: "st_dev,4:st_ino,4:st_mode,4:..." */ + const char *stat_map; + + enum bfd_endian target_endian; + + /* Size of an "int" on the target (for syscalls whose ABI uses "int"). + This must include padding, and only padding-at-higher-address is + supported. For example, a 64-bit target with 32-bit int:s which + are padded to 64 bits when in an array, should supposedly set this + to 8. The default is 4 which matches ILP32 targets and 64-bit + targets with 32-bit ints and no padding. */ + int target_sizeof_int; + + /* Marker for those wanting to do sanity checks. + This should remain the last member of this struct to help catch + miscompilation errors. */ +#define HOST_CALLBACK_MAGIC 4705 /* teds constant */ + int magic; +}; + +extern host_callback default_callback; + +/* Canonical versions of system call numbers. + It's not intended to willy-nilly throw every system call ever heard + of in here. Only include those that have an important use. + ??? One can certainly start a discussion over the ones that are currently + here, but that will always be true. */ + +/* These are used by the ANSI C support of libc. */ +#define CB_SYS_exit 1 +#define CB_SYS_open 2 +#define CB_SYS_close 3 +#define CB_SYS_read 4 +#define CB_SYS_write 5 +#define CB_SYS_lseek 6 +#define CB_SYS_unlink 7 +#define CB_SYS_getpid 8 +#define CB_SYS_kill 9 +#define CB_SYS_fstat 10 +/*#define CB_SYS_sbrk 11 - not currently a system call, but reserved. */ + +/* ARGV support. */ +#define CB_SYS_argvlen 12 +#define CB_SYS_argv 13 + +/* These are extras added for one reason or another. */ +#define CB_SYS_chdir 14 +#define CB_SYS_stat 15 +#define CB_SYS_chmod 16 +#define CB_SYS_utime 17 +#define CB_SYS_time 18 + +/* More standard syscalls. */ +#define CB_SYS_lstat 19 +#define CB_SYS_rename 20 +#define CB_SYS_truncate 21 +#define CB_SYS_ftruncate 22 +#define CB_SYS_pipe 23 + +/* Struct use to pass and return information necessary to perform a + system call. */ +/* FIXME: Need to consider target word size. */ + +typedef struct cb_syscall { + /* The target's value of what system call to perform. */ + int func; + /* The arguments to the syscall. */ + long arg1, arg2, arg3, arg4; + + /* The result. */ + long result; + /* Some system calls have two results. */ + long result2; + /* The target's errno value, or 0 if success. + This is converted to the target's value with host_to_target_errno. */ + int errcode; + + /* Working space to be used by memory read/write callbacks. */ + PTR p1; + PTR p2; + long x1,x2; + + /* Callbacks for reading/writing memory (e.g. for read/write syscalls). + ??? long or unsigned long might be better to use for the `count' + argument here. We mimic sim_{read,write} for now. Be careful to + test any changes with -Wall -Werror, mixed signed comparisons + will get you. */ + int (*read_mem) (host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, char * /*buf*/, + int /*bytes*/); + int (*write_mem) (host_callback * /*cb*/, struct cb_syscall * /*sc*/, + unsigned long /*taddr*/, const char * /*buf*/, + int /*bytes*/); + + /* For sanity checking, should be last entry. */ + int magic; +} CB_SYSCALL; + +/* Magic number sanity checker. */ +#define CB_SYSCALL_MAGIC 0x12344321 + +/* Macro to initialize CB_SYSCALL. Called first, before filling in + any fields. */ +#define CB_SYSCALL_INIT(sc) \ +do { \ + memset ((sc), 0, sizeof (*(sc))); \ + (sc)->magic = CB_SYSCALL_MAGIC; \ +} while (0) + +/* Return codes for various interface routines. */ + +typedef enum { + CB_RC_OK = 0, + /* generic error */ + CB_RC_ERR, + /* either file not found or no read access */ + CB_RC_ACCESS, + CB_RC_NO_MEM +} CB_RC; + +/* Read in target values for system call numbers, errno values, signals. */ +CB_RC cb_read_target_syscall_maps (host_callback *, const char *); + +/* Translate target to host syscall function numbers. */ +int cb_target_to_host_syscall (host_callback *, int); + +/* Translate host to target errno value. */ +int cb_host_to_target_errno (host_callback *, int); + +/* Translate target to host open flags. */ +int cb_target_to_host_open (host_callback *, int); + +/* Translate target signal number to host. */ +int cb_target_to_host_signal (host_callback *, int); + +/* Translate host signal number to target. */ +int cb_host_to_target_signal (host_callback *, int); + +/* Translate host stat struct to target. + If stat struct ptr is NULL, just compute target stat struct size. + Result is size of target stat struct or 0 if error. */ +int cb_host_to_target_stat (host_callback *, const struct stat *, PTR); + +/* Translate a value to target endian. */ +void cb_store_target_endian (host_callback *, char *, int, long); + +/* Tests for special fds. */ +int cb_is_stdin (host_callback *, int); +int cb_is_stdout (host_callback *, int); +int cb_is_stderr (host_callback *, int); + +/* Perform a system call. */ +CB_RC cb_syscall (host_callback *, CB_SYSCALL *); + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/fileio.h b/external/gpl3/gdb/dist/include/gdb/fileio.h new file mode 100644 index 000000000000..fc447601416e --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/fileio.h @@ -0,0 +1,144 @@ +/* Hosted File I/O interface definitions, for GDB, the GNU Debugger. + + Copyright 2003, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef GDB_FILEIO_H_ +#define GDB_FILEIO_H_ + +/* The following flags are defined to be independent of the host + as well as the target side implementation of these constants. + All constants are defined with a leading FILEIO_ in the name + to allow the usage of these constants together with the + corresponding implementation dependent constants in one module. */ + +/* open(2) flags */ +#define FILEIO_O_RDONLY 0x0 +#define FILEIO_O_WRONLY 0x1 +#define FILEIO_O_RDWR 0x2 +#define FILEIO_O_APPEND 0x8 +#define FILEIO_O_CREAT 0x200 +#define FILEIO_O_TRUNC 0x400 +#define FILEIO_O_EXCL 0x800 +#define FILEIO_O_SUPPORTED (FILEIO_O_RDONLY | FILEIO_O_WRONLY| \ + FILEIO_O_RDWR | FILEIO_O_APPEND| \ + FILEIO_O_CREAT | FILEIO_O_TRUNC| \ + FILEIO_O_EXCL) + +/* mode_t bits */ +#define FILEIO_S_IFREG 0100000 +#define FILEIO_S_IFDIR 040000 +#define FILEIO_S_IFCHR 020000 +#define FILEIO_S_IRUSR 0400 +#define FILEIO_S_IWUSR 0200 +#define FILEIO_S_IXUSR 0100 +#define FILEIO_S_IRWXU 0700 +#define FILEIO_S_IRGRP 040 +#define FILEIO_S_IWGRP 020 +#define FILEIO_S_IXGRP 010 +#define FILEIO_S_IRWXG 070 +#define FILEIO_S_IROTH 04 +#define FILEIO_S_IWOTH 02 +#define FILEIO_S_IXOTH 01 +#define FILEIO_S_IRWXO 07 +#define FILEIO_S_SUPPORTED (FILEIO_S_IFREG|FILEIO_S_IFDIR| \ + FILEIO_S_IRWXU|FILEIO_S_IRWXG| \ + FILEIO_S_IRWXO) + +/* lseek(2) flags */ +#define FILEIO_SEEK_SET 0 +#define FILEIO_SEEK_CUR 1 +#define FILEIO_SEEK_END 2 + +/* errno values */ +#define FILEIO_EPERM 1 +#define FILEIO_ENOENT 2 +#define FILEIO_EINTR 4 +#define FILEIO_EIO 5 +#define FILEIO_EBADF 9 +#define FILEIO_EACCES 13 +#define FILEIO_EFAULT 14 +#define FILEIO_EBUSY 16 +#define FILEIO_EEXIST 17 +#define FILEIO_ENODEV 19 +#define FILEIO_ENOTDIR 20 +#define FILEIO_EISDIR 21 +#define FILEIO_EINVAL 22 +#define FILEIO_ENFILE 23 +#define FILEIO_EMFILE 24 +#define FILEIO_EFBIG 27 +#define FILEIO_ENOSPC 28 +#define FILEIO_ESPIPE 29 +#define FILEIO_EROFS 30 +#define FILEIO_ENOSYS 88 +#define FILEIO_ENAMETOOLONG 91 +#define FILEIO_EUNKNOWN 9999 + +/* limits */ +#define FILEIO_INT_MIN -2147483648L +#define FILEIO_INT_MAX 2147483647L +#define FILEIO_UINT_MAX 4294967295UL +#define FILEIO_LONG_MIN -9223372036854775808LL +#define FILEIO_LONG_MAX 9223372036854775807LL +#define FILEIO_ULONG_MAX 18446744073709551615ULL + +/* Integral types as used in protocol. */ +#if 0 +typedef __int32_t fio_int_t; +typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t; +typedef __int64_t fio_long_t; +typedef __uint64_t fio_ulong_t; +#endif + +#define FIO_INT_LEN 4 +#define FIO_UINT_LEN 4 +#define FIO_MODE_LEN 4 +#define FIO_TIME_LEN 4 +#define FIO_LONG_LEN 8 +#define FIO_ULONG_LEN 8 + +typedef char fio_int_t[FIO_INT_LEN]; +typedef char fio_uint_t[FIO_UINT_LEN]; +typedef char fio_mode_t[FIO_MODE_LEN]; +typedef char fio_time_t[FIO_TIME_LEN]; +typedef char fio_long_t[FIO_LONG_LEN]; +typedef char fio_ulong_t[FIO_ULONG_LEN]; + +/* Struct stat as used in protocol. For complete independence + of host/target systems, it's defined as an array with offsets + to the members. */ + +struct fio_stat { + fio_uint_t fst_dev; + fio_uint_t fst_ino; + fio_mode_t fst_mode; + fio_uint_t fst_nlink; + fio_uint_t fst_uid; + fio_uint_t fst_gid; + fio_uint_t fst_rdev; + fio_ulong_t fst_size; + fio_ulong_t fst_blksize; + fio_ulong_t fst_blocks; + fio_time_t fst_atime; + fio_time_t fst_mtime; + fio_time_t fst_ctime; +}; + +struct fio_timeval { + fio_time_t ftv_sec; + fio_long_t ftv_usec; +}; + +#endif /* GDB_FILEIO_H_ */ diff --git a/external/gpl3/gdb/dist/include/gdb/remote-sim.h b/external/gpl3/gdb/dist/include/gdb/remote-sim.h new file mode 100644 index 000000000000..a171cfda5b3e --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/remote-sim.h @@ -0,0 +1,283 @@ +/* This file defines the interface between the simulator and gdb. + + Copyright 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2007, 2008, 2009, 2010, + 2011 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (REMOTE_SIM_H) +#define REMOTE_SIM_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* This file is used when building stand-alone simulators, so isolate this + file from gdb. */ + +/* Pick up CORE_ADDR_TYPE if defined (from gdb), otherwise use same value as + gdb does (unsigned int - from defs.h). */ + +#ifndef CORE_ADDR_TYPE +typedef unsigned int SIM_ADDR; +#else +typedef CORE_ADDR_TYPE SIM_ADDR; +#endif + + +/* Semi-opaque type used as result of sim_open and passed back to all + other routines. "desc" is short for "descriptor". + It is up to each simulator to define `sim_state'. */ + +typedef struct sim_state *SIM_DESC; + + +/* Values for `kind' arg to sim_open. */ + +typedef enum { + SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */ + SIM_OPEN_DEBUG /* simulator used by debugger (gdb) */ +} SIM_OPEN_KIND; + + +/* Return codes from various functions. */ + +typedef enum { + SIM_RC_FAIL = 0, + SIM_RC_OK = 1 +} SIM_RC; + + +/* The bfd struct, as an opaque type. */ + +struct bfd; + + +/* Main simulator entry points. */ + + +/* Create a fully initialized simulator instance. + + (This function is called when the simulator is selected from the + gdb command line.) + + KIND specifies how the simulator shall be used. Currently there + are only two kinds: stand-alone and debug. + + CALLBACK specifies a standard host callback (defined in callback.h). + + ABFD, when non NULL, designates a target program. The program is + not loaded. + + ARGV is a standard ARGV pointer such as that passed from the + command line. The syntax of the argument list is is assumed to be + ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''. + The trailing TARGET-PROGRAM and args are only valid for a + stand-alone simulator. + + On success, the result is a non NULL descriptor that shall be + passed to the other sim_foo functions. While the simulator + configuration can be parameterized by (in decreasing precedence) + ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the + successful creation of the simulator shall not dependent on the + presence of any of these arguments/options. + + Hardware simulator: The created simulator shall be sufficiently + initialized to handle, with out restrictions any client requests + (including memory reads/writes, register fetch/stores and a + resume). + + Process simulator: that process is not created until a call to + sim_create_inferior. FIXME: What should the state of the simulator + be? */ + +SIM_DESC sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv); + + +/* Destory a simulator instance. + + QUITTING is non-zero if we cannot hang on errors. + + This may involve freeing target memory and closing any open files + and mmap'd areas. You cannot assume sim_kill has already been + called. */ + +void sim_close (SIM_DESC sd, int quitting); + + +/* Load program PROG into the simulators memory. + + If ABFD is non-NULL, the bfd for the file has already been opened. + The result is a return code indicating success. + + Hardware simulator: Normally, each program section is written into + memory according to that sections LMA using physical (direct) + addressing. The exception being systems, such as PPC/CHRP, which + support more complicated program loaders. A call to this function + should not effect the state of the processor registers. Multiple + calls to this function are permitted and have an accumulative + effect. + + Process simulator: Calls to this function may be ignored. + + FIXME: Most hardware simulators load the image at the VMA using + virtual addressing. + + FIXME: For some hardware targets, before a loaded program can be + executed, it requires the manipulation of VM registers and tables. + Such manipulation should probably (?) occure in + sim_create_inferior. */ + +SIM_RC sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty); + + +/* Prepare to run the simulated program. + + ABFD, if not NULL, provides initial processor state information. + ARGV and ENV, if non NULL, are NULL terminated lists of pointers. + + Hardware simulator: This function shall initialize the processor + registers to a known value. The program counter and possibly stack + pointer shall be set using information obtained from ABFD (or + hardware reset defaults). ARGV and ENV, dependant on the target + ABI, may be written to memory. + + Process simulator: After a call to this function, a new process + instance shall exist. The TEXT, DATA, BSS and stack regions shall + all be initialized, ARGV and ENV shall be written to process + address space (according to the applicable ABI) and the program + counter and stack pointer set accordingly. */ + +SIM_RC sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env); + + +/* Fetch LENGTH bytes of the simulated program's memory. Start fetch + at virtual address MEM and store in BUF. Result is number of bytes + read, or zero if error. */ + +int sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length); + + +/* Store LENGTH bytes from BUF into the simulated program's + memory. Store bytes starting at virtual address MEM. Result is + number of bytes write, or zero if error. */ + +int sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length); + + +/* Fetch register REGNO storing its raw (target endian) value in the + LENGTH byte buffer BUF. Return the actual size of the register or + zero if REGNO is not applicable. + + Legacy implementations ignore LENGTH and always return -1. + + If LENGTH does not match the size of REGNO no data is transfered + (the actual register size is still returned). */ + +int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length); + + +/* Store register REGNO from the raw (target endian) value in BUF. + + Return the actual size of the register, any size not equal to + LENGTH indicates the register was not updated correctly. + + Return a LENGTH of -1 to indicate the register was not updated + and an error has occurred. + + Return a LENGTH of 0 to indicate the register was not updated + but no error has occurred. */ + +int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length); + + +/* Print whatever statistics the simulator has collected. + + VERBOSE is currently unused and must always be zero. */ + +void sim_info (SIM_DESC sd, int verbose); + + +/* Run (or resume) the simulated program. + + STEP, when non-zero indicates that only a single simulator cycle + should be emulated. + + SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of + event (hardware interrupt, signal) to be delivered to the simulated + program. + + Hardware simulator: If the SIGRC value returned by + sim_stop_reason() is passed back to the simulator via SIGGNAL then + the hardware simulator shall correctly deliver the hardware event + indicated by that signal. If a value of zero is passed in then the + simulation will continue as if there were no outstanding signal. + The effect of any other SIGGNAL value is is implementation + dependant. + + Process simulator: If SIGRC is non-zero then the corresponding + signal is delivered to the simulated program and execution is then + continued. A zero SIGRC value indicates that the program should + continue as normal. */ + +void sim_resume (SIM_DESC sd, int step, int siggnal); + + +/* Asynchronous request to stop the simulation. + A nonzero return indicates that the simulator is able to handle + the request */ + +int sim_stop (SIM_DESC sd); + + +/* Fetch the REASON why the program stopped. + + SIM_EXITED: The program has terminated. SIGRC indicates the target + dependant exit status. + + SIM_STOPPED: The program has stopped. SIGRC uses the host's signal + numbering as a way of identifying the reaon: program interrupted by + user via a sim_stop request (SIGINT); a breakpoint instruction + (SIGTRAP); a completed single step (SIGTRAP); an internal error + condition (SIGABRT); an illegal instruction (SIGILL); Access to an + undefined memory region (SIGSEGV); Mis-aligned memory access + (SIGBUS). For some signals information in addition to the signal + number may be retained by the simulator (e.g. offending address), + that information is not directly accessable via this interface. + + SIM_SIGNALLED: The program has been terminated by a signal. The + simulator has encountered target code that causes the the program + to exit with signal SIGRC. + + SIM_RUNNING, SIM_POLLING: The return of one of these values + indicates a problem internal to the simulator. */ + +enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled }; + +void sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc); + + +/* Passthru for other commands that the simulator might support. + Simulators should be prepared to deal with any combination of NULL + or empty CMD. */ + +void sim_do_command (SIM_DESC sd, char *cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined (REMOTE_SIM_H) */ diff --git a/external/gpl3/gdb/dist/include/gdb/signals.def b/external/gpl3/gdb/dist/include/gdb/signals.def new file mode 100644 index 000000000000..7e08c9045a1f --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/signals.def @@ -0,0 +1,200 @@ +/* Target signal numbers for GDB and the GDB remote protocol. + Copyright 2010, 2011 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* Used some places (e.g. stop_signal) to record the concept that + there is no signal. */ +SET (TARGET_SIGNAL_0, 0, "0", "Signal 0") +#define TARGET_SIGNAL_FIRST TARGET_SIGNAL_0 +SET (TARGET_SIGNAL_HUP, 1, "SIGHUP", "Hangup") +SET (TARGET_SIGNAL_INT, 2, "SIGINT", "Interrupt") +SET (TARGET_SIGNAL_QUIT, 3, "SIGQUIT", "Quit") +SET (TARGET_SIGNAL_ILL, 4, "SIGILL", "Illegal instruction") +SET (TARGET_SIGNAL_TRAP, 5, "SIGTRAP", "Trace/breakpoint trap") +SET (TARGET_SIGNAL_ABRT, 6, "SIGABRT", "Aborted") +SET (TARGET_SIGNAL_EMT, 7, "SIGEMT", "Emulation trap") +SET (TARGET_SIGNAL_FPE, 8, "SIGFPE", "Arithmetic exception") +SET (TARGET_SIGNAL_KILL, 9, "SIGKILL", "Killed") +SET (TARGET_SIGNAL_BUS, 10, "SIGBUS", "Bus error") +SET (TARGET_SIGNAL_SEGV, 11, "SIGSEGV", "Segmentation fault") +SET (TARGET_SIGNAL_SYS, 12, "SIGSYS", "Bad system call") +SET (TARGET_SIGNAL_PIPE, 13, "SIGPIPE", "Broken pipe") +SET (TARGET_SIGNAL_ALRM, 14, "SIGALRM", "Alarm clock") +SET (TARGET_SIGNAL_TERM, 15, "SIGTERM", "Terminated") +SET (TARGET_SIGNAL_URG, 16, "SIGURG", "Urgent I/O condition") +SET (TARGET_SIGNAL_STOP, 17, "SIGSTOP", "Stopped (signal)") +SET (TARGET_SIGNAL_TSTP, 18, "SIGTSTP", "Stopped (user)") +SET (TARGET_SIGNAL_CONT, 19, "SIGCONT", "Continued") +SET (TARGET_SIGNAL_CHLD, 20, "SIGCHLD", "Child status changed") +SET (TARGET_SIGNAL_TTIN, 21, "SIGTTIN", "Stopped (tty input)") +SET (TARGET_SIGNAL_TTOU, 22, "SIGTTOU", "Stopped (tty output)") +SET (TARGET_SIGNAL_IO, 23, "SIGIO", "I/O possible") +SET (TARGET_SIGNAL_XCPU, 24, "SIGXCPU", "CPU time limit exceeded") +SET (TARGET_SIGNAL_XFSZ, 25, "SIGXFSZ", "File size limit exceeded") +SET (TARGET_SIGNAL_VTALRM, 26, "SIGVTALRM", "Virtual timer expired") +SET (TARGET_SIGNAL_PROF, 27, "SIGPROF", "Profiling timer expired") +SET (TARGET_SIGNAL_WINCH, 28, "SIGWINCH", "Window size changed") +SET (TARGET_SIGNAL_LOST, 29, "SIGLOST", "Resource lost") +SET (TARGET_SIGNAL_USR1, 30, "SIGUSR1", "User defined signal 1") +SET (TARGET_SIGNAL_USR2, 31, "SIGUSR2", "User defined signal 2") +SET (TARGET_SIGNAL_PWR, 32, "SIGPWR", "Power fail/restart") +/* Similar to SIGIO. Perhaps they should have the same number. */ +SET (TARGET_SIGNAL_POLL, 33, "SIGPOLL", "Pollable event occurred") +SET (TARGET_SIGNAL_WIND, 34, "SIGWIND", "SIGWIND") +SET (TARGET_SIGNAL_PHONE, 35, "SIGPHONE", "SIGPHONE") +SET (TARGET_SIGNAL_WAITING, 36, "SIGWAITING", "Process's LWPs are blocked") +SET (TARGET_SIGNAL_LWP, 37, "SIGLWP", "Signal LWP") +SET (TARGET_SIGNAL_DANGER, 38, "SIGDANGER", "Swap space dangerously low") +SET (TARGET_SIGNAL_GRANT, 39, "SIGGRANT", "Monitor mode granted") +SET (TARGET_SIGNAL_RETRACT, 40, "SIGRETRACT", + "Need to relinquish monitor mode") +SET (TARGET_SIGNAL_MSG, 41, "SIGMSG", "Monitor mode data available") +SET (TARGET_SIGNAL_SOUND, 42, "SIGSOUND", "Sound completed") +SET (TARGET_SIGNAL_SAK, 43, "SIGSAK", "Secure attention") +SET (TARGET_SIGNAL_PRIO, 44, "SIGPRIO", "SIGPRIO") +SET (TARGET_SIGNAL_REALTIME_33, 45, "SIG33", "Real-time event 33") +SET (TARGET_SIGNAL_REALTIME_34, 46, "SIG34", "Real-time event 34") +SET (TARGET_SIGNAL_REALTIME_35, 47, "SIG35", "Real-time event 35") +SET (TARGET_SIGNAL_REALTIME_36, 48, "SIG36", "Real-time event 36") +SET (TARGET_SIGNAL_REALTIME_37, 49, "SIG37", "Real-time event 37") +SET (TARGET_SIGNAL_REALTIME_38, 50, "SIG38", "Real-time event 38") +SET (TARGET_SIGNAL_REALTIME_39, 51, "SIG39", "Real-time event 39") +SET (TARGET_SIGNAL_REALTIME_40, 52, "SIG40", "Real-time event 40") +SET (TARGET_SIGNAL_REALTIME_41, 53, "SIG41", "Real-time event 41") +SET (TARGET_SIGNAL_REALTIME_42, 54, "SIG42", "Real-time event 42") +SET (TARGET_SIGNAL_REALTIME_43, 55, "SIG43", "Real-time event 43") +SET (TARGET_SIGNAL_REALTIME_44, 56, "SIG44", "Real-time event 44") +SET (TARGET_SIGNAL_REALTIME_45, 57, "SIG45", "Real-time event 45") +SET (TARGET_SIGNAL_REALTIME_46, 58, "SIG46", "Real-time event 46") +SET (TARGET_SIGNAL_REALTIME_47, 59, "SIG47", "Real-time event 47") +SET (TARGET_SIGNAL_REALTIME_48, 60, "SIG48", "Real-time event 48") +SET (TARGET_SIGNAL_REALTIME_49, 61, "SIG49", "Real-time event 49") +SET (TARGET_SIGNAL_REALTIME_50, 62, "SIG50", "Real-time event 50") +SET (TARGET_SIGNAL_REALTIME_51, 63, "SIG51", "Real-time event 51") +SET (TARGET_SIGNAL_REALTIME_52, 64, "SIG52", "Real-time event 52") +SET (TARGET_SIGNAL_REALTIME_53, 65, "SIG53", "Real-time event 53") +SET (TARGET_SIGNAL_REALTIME_54, 66, "SIG54", "Real-time event 54") +SET (TARGET_SIGNAL_REALTIME_55, 67, "SIG55", "Real-time event 55") +SET (TARGET_SIGNAL_REALTIME_56, 68, "SIG56", "Real-time event 56") +SET (TARGET_SIGNAL_REALTIME_57, 69, "SIG57", "Real-time event 57") +SET (TARGET_SIGNAL_REALTIME_58, 70, "SIG58", "Real-time event 58") +SET (TARGET_SIGNAL_REALTIME_59, 71, "SIG59", "Real-time event 59") +SET (TARGET_SIGNAL_REALTIME_60, 72, "SIG60", "Real-time event 60") +SET (TARGET_SIGNAL_REALTIME_61, 73, "SIG61", "Real-time event 61") +SET (TARGET_SIGNAL_REALTIME_62, 74, "SIG62", "Real-time event 62") +SET (TARGET_SIGNAL_REALTIME_63, 75, "SIG63", "Real-time event 63") + +/* Used internally by Solaris threads. See signal(5) on Solaris. */ +SET (TARGET_SIGNAL_CANCEL, 76, "SIGCANCEL", "LWP internal signal") + +/* Yes, this pains me, too. But LynxOS didn't have SIG32, and now + GNU/Linux does, and we can't disturb the numbering, since it's + part of the remote protocol. Note that in some GDB's + TARGET_SIGNAL_REALTIME_32 is number 76. */ +SET (TARGET_SIGNAL_REALTIME_32, 77, "SIG32", "Real-time event 32") +/* Yet another pain, IRIX 6 has SIG64. */ +SET (TARGET_SIGNAL_REALTIME_64, 78, "SIG64", "Real-time event 64") +/* Yet another pain, GNU/Linux MIPS might go up to 128. */ +SET (TARGET_SIGNAL_REALTIME_65, 79, "SIG65", "Real-time event 65") +SET (TARGET_SIGNAL_REALTIME_66, 80, "SIG66", "Real-time event 66") +SET (TARGET_SIGNAL_REALTIME_67, 81, "SIG67", "Real-time event 67") +SET (TARGET_SIGNAL_REALTIME_68, 82, "SIG68", "Real-time event 68") +SET (TARGET_SIGNAL_REALTIME_69, 83, "SIG69", "Real-time event 69") +SET (TARGET_SIGNAL_REALTIME_70, 84, "SIG70", "Real-time event 70") +SET (TARGET_SIGNAL_REALTIME_71, 85, "SIG71", "Real-time event 71") +SET (TARGET_SIGNAL_REALTIME_72, 86, "SIG72", "Real-time event 72") +SET (TARGET_SIGNAL_REALTIME_73, 87, "SIG73", "Real-time event 73") +SET (TARGET_SIGNAL_REALTIME_74, 88, "SIG74", "Real-time event 74") +SET (TARGET_SIGNAL_REALTIME_75, 89, "SIG75", "Real-time event 75") +SET (TARGET_SIGNAL_REALTIME_76, 90, "SIG76", "Real-time event 76") +SET (TARGET_SIGNAL_REALTIME_77, 91, "SIG77", "Real-time event 77") +SET (TARGET_SIGNAL_REALTIME_78, 92, "SIG78", "Real-time event 78") +SET (TARGET_SIGNAL_REALTIME_79, 93, "SIG79", "Real-time event 79") +SET (TARGET_SIGNAL_REALTIME_80, 94, "SIG80", "Real-time event 80") +SET (TARGET_SIGNAL_REALTIME_81, 95, "SIG81", "Real-time event 81") +SET (TARGET_SIGNAL_REALTIME_82, 96, "SIG82", "Real-time event 82") +SET (TARGET_SIGNAL_REALTIME_83, 97, "SIG83", "Real-time event 83") +SET (TARGET_SIGNAL_REALTIME_84, 98, "SIG84", "Real-time event 84") +SET (TARGET_SIGNAL_REALTIME_85, 99, "SIG85", "Real-time event 85") +SET (TARGET_SIGNAL_REALTIME_86, 100, "SIG86", "Real-time event 86") +SET (TARGET_SIGNAL_REALTIME_87, 101, "SIG87", "Real-time event 87") +SET (TARGET_SIGNAL_REALTIME_88, 102, "SIG88", "Real-time event 88") +SET (TARGET_SIGNAL_REALTIME_89, 103, "SIG89", "Real-time event 89") +SET (TARGET_SIGNAL_REALTIME_90, 104, "SIG90", "Real-time event 90") +SET (TARGET_SIGNAL_REALTIME_91, 105, "SIG91", "Real-time event 91") +SET (TARGET_SIGNAL_REALTIME_92, 106, "SIG92", "Real-time event 92") +SET (TARGET_SIGNAL_REALTIME_93, 107, "SIG93", "Real-time event 93") +SET (TARGET_SIGNAL_REALTIME_94, 108, "SIG94", "Real-time event 94") +SET (TARGET_SIGNAL_REALTIME_95, 109, "SIG95", "Real-time event 95") +SET (TARGET_SIGNAL_REALTIME_96, 110, "SIG96", "Real-time event 96") +SET (TARGET_SIGNAL_REALTIME_97, 111, "SIG97", "Real-time event 97") +SET (TARGET_SIGNAL_REALTIME_98, 112, "SIG98", "Real-time event 98") +SET (TARGET_SIGNAL_REALTIME_99, 113, "SIG99", "Real-time event 99") +SET (TARGET_SIGNAL_REALTIME_100, 114, "SIG100", "Real-time event 100") +SET (TARGET_SIGNAL_REALTIME_101, 115, "SIG101", "Real-time event 101") +SET (TARGET_SIGNAL_REALTIME_102, 116, "SIG102", "Real-time event 102") +SET (TARGET_SIGNAL_REALTIME_103, 117, "SIG103", "Real-time event 103") +SET (TARGET_SIGNAL_REALTIME_104, 118, "SIG104", "Real-time event 104") +SET (TARGET_SIGNAL_REALTIME_105, 119, "SIG105", "Real-time event 105") +SET (TARGET_SIGNAL_REALTIME_106, 120, "SIG106", "Real-time event 106") +SET (TARGET_SIGNAL_REALTIME_107, 121, "SIG107", "Real-time event 107") +SET (TARGET_SIGNAL_REALTIME_108, 122, "SIG108", "Real-time event 108") +SET (TARGET_SIGNAL_REALTIME_109, 123, "SIG109", "Real-time event 109") +SET (TARGET_SIGNAL_REALTIME_110, 124, "SIG110", "Real-time event 110") +SET (TARGET_SIGNAL_REALTIME_111, 125, "SIG111", "Real-time event 111") +SET (TARGET_SIGNAL_REALTIME_112, 126, "SIG112", "Real-time event 112") +SET (TARGET_SIGNAL_REALTIME_113, 127, "SIG113", "Real-time event 113") +SET (TARGET_SIGNAL_REALTIME_114, 128, "SIG114", "Real-time event 114") +SET (TARGET_SIGNAL_REALTIME_115, 129, "SIG115", "Real-time event 115") +SET (TARGET_SIGNAL_REALTIME_116, 130, "SIG116", "Real-time event 116") +SET (TARGET_SIGNAL_REALTIME_117, 131, "SIG117", "Real-time event 117") +SET (TARGET_SIGNAL_REALTIME_118, 132, "SIG118", "Real-time event 118") +SET (TARGET_SIGNAL_REALTIME_119, 133, "SIG119", "Real-time event 119") +SET (TARGET_SIGNAL_REALTIME_120, 134, "SIG120", "Real-time event 120") +SET (TARGET_SIGNAL_REALTIME_121, 135, "SIG121", "Real-time event 121") +SET (TARGET_SIGNAL_REALTIME_122, 136, "SIG122", "Real-time event 122") +SET (TARGET_SIGNAL_REALTIME_123, 137, "SIG123", "Real-time event 123") +SET (TARGET_SIGNAL_REALTIME_124, 138, "SIG124", "Real-time event 124") +SET (TARGET_SIGNAL_REALTIME_125, 139, "SIG125", "Real-time event 125") +SET (TARGET_SIGNAL_REALTIME_126, 140, "SIG126", "Real-time event 126") +SET (TARGET_SIGNAL_REALTIME_127, 141, "SIG127", "Real-time event 127") + +SET (TARGET_SIGNAL_INFO, 142, "SIGINFO", "Information request") + +/* Some signal we don't know about. */ +SET (TARGET_SIGNAL_UNKNOWN, 143, NULL, "Unknown signal") + +/* Use whatever signal we use when one is not specifically specified + (for passing to proceed and so on). */ +SET (TARGET_SIGNAL_DEFAULT, 144, NULL, + "Internal error: printing TARGET_SIGNAL_DEFAULT") + +/* Mach exceptions. In versions of GDB before 5.2, these were just before + TARGET_SIGNAL_INFO if you were compiling on a Mach host (and missing + otherwise). */ +SET (TARGET_EXC_BAD_ACCESS, 145, "EXC_BAD_ACCESS", "Could not access memory") +SET (TARGET_EXC_BAD_INSTRUCTION, 146, "EXC_BAD_INSTRUCTION", + "Illegal instruction/operand") +SET (TARGET_EXC_ARITHMETIC, 147, "EXC_ARITHMETIC", "Arithmetic exception") +SET (TARGET_EXC_EMULATION, 148, "EXC_EMULATION", "Emulation instruction") +SET (TARGET_EXC_SOFTWARE, 149, "EXC_SOFTWARE", "Software generated exception") +SET (TARGET_EXC_BREAKPOINT, 150, "EXC_BREAKPOINT", "Breakpoint") + +/* If you are adding a new signal, add it just above this comment. */ + +/* Last and unused enum value, for sizing arrays, etc. */ +SET (TARGET_SIGNAL_LAST, 151, NULL, "TARGET_SIGNAL_MAGIC") diff --git a/external/gpl3/gdb/dist/include/gdb/signals.h b/external/gpl3/gdb/dist/include/gdb/signals.h new file mode 100644 index 000000000000..73643974c87c --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/signals.h @@ -0,0 +1,60 @@ +/* Target signal numbers for GDB and the GDB remote protocol. + Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, + 1998, 1999, 2000, 2001, 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef GDB_SIGNALS_H +#define GDB_SIGNALS_H + +/* The numbering of these signals is chosen to match traditional unix + signals (insofar as various unices use the same numbers, anyway). + It is also the numbering of the GDB remote protocol. Other remote + protocols, if they use a different numbering, should make sure to + translate appropriately. + + Since these numbers have actually made it out into other software + (stubs, etc.), you mustn't disturb the assigned numbering. If you + need to add new signals here, add them to the end of the explicitly + numbered signals, at the comment marker. Add them unconditionally, + not within any #if or #ifdef. + + This is based strongly on Unix/POSIX signals for several reasons: + (1) This set of signals represents a widely-accepted attempt to + represent events of this sort in a portable fashion, (2) we want a + signal to make it from wait to child_wait to the user intact, (3) many + remote protocols use a similar encoding. However, it is + recognized that this set of signals has limitations (such as not + distinguishing between various kinds of SIGSEGV, or not + distinguishing hitting a breakpoint from finishing a single step). + So in the future we may get around this either by adding additional + signals for breakpoint, single-step, etc., or by adding signal + codes; the latter seems more in the spirit of what BSD, System V, + etc. are doing to address these issues. */ + +/* For an explanation of what each signal means, see + target_signal_to_string. */ + +enum target_signal + { +#define SET(symbol, constant, name, string) \ + symbol = constant, +#include "gdb/signals.def" +#undef SET + }; + +#endif /* #ifndef GDB_SIGNALS_H */ diff --git a/external/gpl3/gdb/dist/include/gdb/sim-arm.h b/external/gpl3/gdb/dist/include/gdb/sim-arm.h new file mode 100644 index 000000000000..3004d8c42930 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-arm.h @@ -0,0 +1,113 @@ +/* This file defines the interface between the Arm simulator and GDB. + + Copyright 2002, 2003, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_ARM_H) +#define SIM_ARM_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_arm_regs +{ + SIM_ARM_R0_REGNUM, + SIM_ARM_R1_REGNUM, + SIM_ARM_R2_REGNUM, + SIM_ARM_R3_REGNUM, + SIM_ARM_R4_REGNUM, + SIM_ARM_R5_REGNUM, + SIM_ARM_R6_REGNUM, + SIM_ARM_R7_REGNUM, + SIM_ARM_R8_REGNUM, + SIM_ARM_R9_REGNUM, + SIM_ARM_R10_REGNUM, + SIM_ARM_R11_REGNUM, + SIM_ARM_R12_REGNUM, + SIM_ARM_R13_REGNUM, + SIM_ARM_R14_REGNUM, + SIM_ARM_R15_REGNUM, /* PC */ + SIM_ARM_FP0_REGNUM, + SIM_ARM_FP1_REGNUM, + SIM_ARM_FP2_REGNUM, + SIM_ARM_FP3_REGNUM, + SIM_ARM_FP4_REGNUM, + SIM_ARM_FP5_REGNUM, + SIM_ARM_FP6_REGNUM, + SIM_ARM_FP7_REGNUM, + SIM_ARM_FPS_REGNUM, + SIM_ARM_PS_REGNUM, + SIM_ARM_MAVERIC_COP0R0_REGNUM, + SIM_ARM_MAVERIC_COP0R1_REGNUM, + SIM_ARM_MAVERIC_COP0R2_REGNUM, + SIM_ARM_MAVERIC_COP0R3_REGNUM, + SIM_ARM_MAVERIC_COP0R4_REGNUM, + SIM_ARM_MAVERIC_COP0R5_REGNUM, + SIM_ARM_MAVERIC_COP0R6_REGNUM, + SIM_ARM_MAVERIC_COP0R7_REGNUM, + SIM_ARM_MAVERIC_COP0R8_REGNUM, + SIM_ARM_MAVERIC_COP0R9_REGNUM, + SIM_ARM_MAVERIC_COP0R10_REGNUM, + SIM_ARM_MAVERIC_COP0R11_REGNUM, + SIM_ARM_MAVERIC_COP0R12_REGNUM, + SIM_ARM_MAVERIC_COP0R13_REGNUM, + SIM_ARM_MAVERIC_COP0R14_REGNUM, + SIM_ARM_MAVERIC_COP0R15_REGNUM, + SIM_ARM_MAVERIC_DSPSC_REGNUM, + SIM_ARM_IWMMXT_COP0R0_REGNUM, + SIM_ARM_IWMMXT_COP0R1_REGNUM, + SIM_ARM_IWMMXT_COP0R2_REGNUM, + SIM_ARM_IWMMXT_COP0R3_REGNUM, + SIM_ARM_IWMMXT_COP0R4_REGNUM, + SIM_ARM_IWMMXT_COP0R5_REGNUM, + SIM_ARM_IWMMXT_COP0R6_REGNUM, + SIM_ARM_IWMMXT_COP0R7_REGNUM, + SIM_ARM_IWMMXT_COP0R8_REGNUM, + SIM_ARM_IWMMXT_COP0R9_REGNUM, + SIM_ARM_IWMMXT_COP0R10_REGNUM, + SIM_ARM_IWMMXT_COP0R11_REGNUM, + SIM_ARM_IWMMXT_COP0R12_REGNUM, + SIM_ARM_IWMMXT_COP0R13_REGNUM, + SIM_ARM_IWMMXT_COP0R14_REGNUM, + SIM_ARM_IWMMXT_COP0R15_REGNUM, + SIM_ARM_IWMMXT_COP1R0_REGNUM, + SIM_ARM_IWMMXT_COP1R1_REGNUM, + SIM_ARM_IWMMXT_COP1R2_REGNUM, + SIM_ARM_IWMMXT_COP1R3_REGNUM, + SIM_ARM_IWMMXT_COP1R4_REGNUM, + SIM_ARM_IWMMXT_COP1R5_REGNUM, + SIM_ARM_IWMMXT_COP1R6_REGNUM, + SIM_ARM_IWMMXT_COP1R7_REGNUM, + SIM_ARM_IWMMXT_COP1R8_REGNUM, + SIM_ARM_IWMMXT_COP1R9_REGNUM, + SIM_ARM_IWMMXT_COP1R10_REGNUM, + SIM_ARM_IWMMXT_COP1R11_REGNUM, + SIM_ARM_IWMMXT_COP1R12_REGNUM, + SIM_ARM_IWMMXT_COP1R13_REGNUM, + SIM_ARM_IWMMXT_COP1R14_REGNUM, + SIM_ARM_IWMMXT_COP1R15_REGNUM +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/sim-bfin.h b/external/gpl3/gdb/dist/include/gdb/sim-bfin.h new file mode 100644 index 000000000000..3a006b882efc --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-bfin.h @@ -0,0 +1,82 @@ +/* This file defines the interface between the Blackfin simulator and GDB. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +enum sim_bfin_regnum { + SIM_BFIN_R0_REGNUM = 0, + SIM_BFIN_R1_REGNUM, + SIM_BFIN_R2_REGNUM, + SIM_BFIN_R3_REGNUM, + SIM_BFIN_R4_REGNUM, + SIM_BFIN_R5_REGNUM, + SIM_BFIN_R6_REGNUM, + SIM_BFIN_R7_REGNUM, + SIM_BFIN_P0_REGNUM, + SIM_BFIN_P1_REGNUM, + SIM_BFIN_P2_REGNUM, + SIM_BFIN_P3_REGNUM, + SIM_BFIN_P4_REGNUM, + SIM_BFIN_P5_REGNUM, + SIM_BFIN_SP_REGNUM, + SIM_BFIN_FP_REGNUM, + SIM_BFIN_I0_REGNUM, + SIM_BFIN_I1_REGNUM, + SIM_BFIN_I2_REGNUM, + SIM_BFIN_I3_REGNUM, + SIM_BFIN_M0_REGNUM, + SIM_BFIN_M1_REGNUM, + SIM_BFIN_M2_REGNUM, + SIM_BFIN_M3_REGNUM, + SIM_BFIN_B0_REGNUM, + SIM_BFIN_B1_REGNUM, + SIM_BFIN_B2_REGNUM, + SIM_BFIN_B3_REGNUM, + SIM_BFIN_L0_REGNUM, + SIM_BFIN_L1_REGNUM, + SIM_BFIN_L2_REGNUM, + SIM_BFIN_L3_REGNUM, + SIM_BFIN_A0_DOT_X_REGNUM, + SIM_BFIN_A0_DOT_W_REGNUM, + SIM_BFIN_A1_DOT_X_REGNUM, + SIM_BFIN_A1_DOT_W_REGNUM, + SIM_BFIN_ASTAT_REGNUM, + SIM_BFIN_RETS_REGNUM, + SIM_BFIN_LC0_REGNUM, + SIM_BFIN_LT0_REGNUM, + SIM_BFIN_LB0_REGNUM, + SIM_BFIN_LC1_REGNUM, + SIM_BFIN_LT1_REGNUM, + SIM_BFIN_LB1_REGNUM, + SIM_BFIN_CYCLES_REGNUM, + SIM_BFIN_CYCLES2_REGNUM, + SIM_BFIN_USP_REGNUM, + SIM_BFIN_SEQSTAT_REGNUM, + SIM_BFIN_SYSCFG_REGNUM, + SIM_BFIN_RETI_REGNUM, + SIM_BFIN_RETX_REGNUM, + SIM_BFIN_RETN_REGNUM, + SIM_BFIN_RETE_REGNUM, + SIM_BFIN_PC_REGNUM, + SIM_BFIN_CC_REGNUM, + SIM_BFIN_TEXT_ADDR, + SIM_BFIN_TEXT_END_ADDR, + SIM_BFIN_DATA_ADDR, + SIM_BFIN_IPEND_REGNUM +}; + diff --git a/external/gpl3/gdb/dist/include/gdb/sim-cr16.h b/external/gpl3/gdb/dist/include/gdb/sim-cr16.h new file mode 100644 index 000000000000..1e1c0dd0b4fc --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-cr16.h @@ -0,0 +1,106 @@ +/* This file defines the interface between the cr16 simulator and gdb. + + Copyright 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . */ + +#if !defined (SIM_CR16_H) +#define SIM_CR16_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum + { + SIM_CR16_MEMORY_UNIFIED = 0x00000000, + SIM_CR16_MEMORY_INSN = 0x10000000, + SIM_CR16_MEMORY_DATA = 0x10000000, + SIM_CR16_MEMORY_DMAP = 0x10000000, + SIM_CR16_MEMORY_IMAP = 0x10000000 + }; + +extern unsigned long sim_cr16_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_cr16_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*imap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_cr16_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr), + unsigned long (*imap_register) (void *regcache, int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum sim_cr16_regs +{ + SIM_CR16_R0_REGNUM, + SIM_CR16_R1_REGNUM, + SIM_CR16_R2_REGNUM, + SIM_CR16_R3_REGNUM, + SIM_CR16_R4_REGNUM, + SIM_CR16_R5_REGNUM, + SIM_CR16_R6_REGNUM, + SIM_CR16_R7_REGNUM, + SIM_CR16_R8_REGNUM, + SIM_CR16_R9_REGNUM, + SIM_CR16_R10_REGNUM, + SIM_CR16_R11_REGNUM, + SIM_CR16_R12_REGNUM, + SIM_CR16_R13_REGNUM, + SIM_CR16_R14_REGNUM, + SIM_CR16_R15_REGNUM, + + SIM_CR16_PC_REGNUM, + SIM_CR16_ISP_REGNUM, + SIM_CR16_USP_REGNUM, + SIM_CR16_INTBASE_REGNUM, + SIM_CR16_PSR_REGNUM, + SIM_CR16_CFG_REGNUM, + SIM_CR16_DBS_REGNUM, + SIM_CR16_DCR_REGNUM, + SIM_CR16_DSR_REGNUM, + SIM_CR16_CAR0_REGNUM, + SIM_CR16_CAR1_REGNUM +}; + +enum +{ + SIM_CR16_NR_R_REGS = 16, + SIM_CR16_NR_A_REGS = 2, + SIM_CR16_NR_IMAP_REGS = 2, + SIM_CR16_NR_DMAP_REGS = 4, + SIM_CR16_NR_CR_REGS = 11 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/sim-d10v.h b/external/gpl3/gdb/dist/include/gdb/sim-d10v.h new file mode 100644 index 000000000000..9f65191b0e9c --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-d10v.h @@ -0,0 +1,142 @@ +/* This file defines the interface between the d10v simulator and gdb. + + Copyright 1999, 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_D10V_H) +#define SIM_D10V_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* GDB interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + 0x10xxxxxx: Logical data address segment (DMAP translated memory) + 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) + + The remote d10v board interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + + The following translate a virtual DMAP/IMAP offset into a physical + memory segment assigning the translated address to PHYS. Since a + memory access may cross a page boundrary the number of bytes for + which the translation is applicable (or 0 for an invalid virtual + offset) is returned. */ + +enum + { + SIM_D10V_MEMORY_UNIFIED = 0x00000000, + SIM_D10V_MEMORY_INSN = 0x01000000, + SIM_D10V_MEMORY_DATA = 0x02000000, + SIM_D10V_MEMORY_DMAP = 0x10000000, + SIM_D10V_MEMORY_IMAP = 0x11000000 + }; + +extern unsigned long sim_d10v_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*imap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr), + unsigned long (*imap_register) (void *regcache, int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum sim_d10v_regs +{ + SIM_D10V_R0_REGNUM, + SIM_D10V_R1_REGNUM, + SIM_D10V_R2_REGNUM, + SIM_D10V_R3_REGNUM, + SIM_D10V_R4_REGNUM, + SIM_D10V_R5_REGNUM, + SIM_D10V_R6_REGNUM, + SIM_D10V_R7_REGNUM, + SIM_D10V_R8_REGNUM, + SIM_D10V_R9_REGNUM, + SIM_D10V_R10_REGNUM, + SIM_D10V_R11_REGNUM, + SIM_D10V_R12_REGNUM, + SIM_D10V_R13_REGNUM, + SIM_D10V_R14_REGNUM, + SIM_D10V_R15_REGNUM, + SIM_D10V_CR0_REGNUM, + SIM_D10V_CR1_REGNUM, + SIM_D10V_CR2_REGNUM, + SIM_D10V_CR3_REGNUM, + SIM_D10V_CR4_REGNUM, + SIM_D10V_CR5_REGNUM, + SIM_D10V_CR6_REGNUM, + SIM_D10V_CR7_REGNUM, + SIM_D10V_CR8_REGNUM, + SIM_D10V_CR9_REGNUM, + SIM_D10V_CR10_REGNUM, + SIM_D10V_CR11_REGNUM, + SIM_D10V_CR12_REGNUM, + SIM_D10V_CR13_REGNUM, + SIM_D10V_CR14_REGNUM, + SIM_D10V_CR15_REGNUM, + SIM_D10V_A0_REGNUM, + SIM_D10V_A1_REGNUM, + SIM_D10V_SPI_REGNUM, + SIM_D10V_SPU_REGNUM, + SIM_D10V_IMAP0_REGNUM, + SIM_D10V_IMAP1_REGNUM, + SIM_D10V_DMAP0_REGNUM, + SIM_D10V_DMAP1_REGNUM, + SIM_D10V_DMAP2_REGNUM, + SIM_D10V_DMAP3_REGNUM, + SIM_D10V_TS2_DMAP_REGNUM +}; + +enum +{ + SIM_D10V_NR_R_REGS = 16, + SIM_D10V_NR_A_REGS = 2, + SIM_D10V_NR_IMAP_REGS = 2, + SIM_D10V_NR_DMAP_REGS = 4, + SIM_D10V_NR_CR_REGS = 16 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/sim-frv.h b/external/gpl3/gdb/dist/include/gdb/sim-frv.h new file mode 100644 index 000000000000..fe206b2b056e --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-frv.h @@ -0,0 +1,51 @@ +/* This file defines the interface between the FR-V simulator and GDB. + + Copyright 2003, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_FRV_H) +#define SIM_FRV_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_frv_regs +{ + SIM_FRV_GR0_REGNUM = 0, + SIM_FRV_GR63_REGNUM = 63, + SIM_FRV_FR0_REGNUM = 64, + SIM_FRV_FR63_REGNUM = 127, + SIM_FRV_PC_REGNUM = 128, + + /* An FR-V architecture may have up to 4096 special purpose registers + (SPRs). In order to determine a specific constant used to access + a particular SPR, one of the H_SPR_ prefixed offsets defined in + opcodes/frv-desc.h should be added to SIM_FRV_SPR0_REGNUM. So, + for example, the number that GDB uses to fetch the link register + from the simulator is (SIM_FRV_SPR0_REGNUM + H_SPR_LR). */ + SIM_FRV_SPR0_REGNUM = 129, + SIM_FRV_SPR4095_REGNUM = SIM_FRV_SPR0_REGNUM + 4095 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/sim-h8300.h b/external/gpl3/gdb/dist/include/gdb/sim-h8300.h new file mode 100644 index 000000000000..bc1ab7b2e0b8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-h8300.h @@ -0,0 +1,78 @@ +/* This file defines the interface between the h8300 simulator and gdb. + Copyright (C) 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_H8300_H) +#define SIM_H8300_H + +#ifdef __cplusplus +extern "C" { //} +#endif + +/* The simulator makes use of the following register information. */ + + enum sim_h8300_regs + { + /* Registers common to all the H8 variants. */ + /* Start here: */ + SIM_H8300_R0_REGNUM, + SIM_H8300_R1_REGNUM, + SIM_H8300_R2_REGNUM, + SIM_H8300_R3_REGNUM, + SIM_H8300_R4_REGNUM, + SIM_H8300_R5_REGNUM, + SIM_H8300_R6_REGNUM, + SIM_H8300_R7_REGNUM, + + SIM_H8300_CCR_REGNUM, /* Contains processor status */ + SIM_H8300_PC_REGNUM, /* Contains program counter */ + /* End here */ + + SIM_H8300_EXR_REGNUM, /* Contains extended processor status + H8S and higher */ + SIM_H8300_MACL_REGNUM, /* Lower part of MAC register (26xx only)*/ + SIM_H8300_MACH_REGNUM, /* High part of MAC register (26xx only) */ + + SIM_H8300_CYCLE_REGNUM, + SIM_H8300_INST_REGNUM, + SIM_H8300_TICK_REGNUM + }; + + enum + { + SIM_H8300_ARG_FIRST_REGNUM = SIM_H8300_R0_REGNUM, /* first reg in which an arg + may be passed */ + SIM_H8300_ARG_LAST_REGNUM = SIM_H8300_R3_REGNUM, /* last reg in which an arg + may be passed */ + SIM_H8300_FP_REGNUM = SIM_H8300_R6_REGNUM, /* Contain address of executing + stack frame */ + SIM_H8300_SP_REGNUM = SIM_H8300_R7_REGNUM /* Contains address of top of stack */ + }; + + enum + { + SIM_H8300_NUM_COMMON_REGS = 10, + SIM_H8300_S_NUM_REGS = 13, + SIM_H8300_NUM_REGS = 16 + }; + +#ifdef __cplusplus +} +#endif + +#endif /* SIM_H8300_H */ diff --git a/external/gpl3/gdb/dist/include/gdb/sim-lm32.h b/external/gpl3/gdb/dist/include/gdb/sim-lm32.h new file mode 100644 index 000000000000..ad94a9f35f41 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-lm32.h @@ -0,0 +1,76 @@ +/* This file defines the interface between the LM32 simulator and GDB. + Contributed by Jon Beniston + + Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef SIM_LM32_H +#define SIM_LM32_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_lm32_regs +{ + SIM_LM32_R0_REGNUM, + SIM_LM32_R1_REGNUM, + SIM_LM32_R2_REGNUM, + SIM_LM32_R3_REGNUM, + SIM_LM32_R4_REGNUM, + SIM_LM32_R5_REGNUM, + SIM_LM32_R6_REGNUM, + SIM_LM32_R7_REGNUM, + SIM_LM32_R8_REGNUM, + SIM_LM32_R9_REGNUM, + SIM_LM32_R10_REGNUM, + SIM_LM32_R11_REGNUM, + SIM_LM32_R12_REGNUM, + SIM_LM32_R13_REGNUM, + SIM_LM32_R14_REGNUM, + SIM_LM32_R15_REGNUM, + SIM_LM32_R16_REGNUM, + SIM_LM32_R17_REGNUM, + SIM_LM32_R18_REGNUM, + SIM_LM32_R19_REGNUM, + SIM_LM32_R20_REGNUM, + SIM_LM32_R21_REGNUM, + SIM_LM32_R22_REGNUM, + SIM_LM32_R23_REGNUM, + SIM_LM32_R24_REGNUM, + SIM_LM32_R25_REGNUM, + SIM_LM32_GP_REGNUM, + SIM_LM32_FP_REGNUM, + SIM_LM32_SP_REGNUM, + SIM_LM32_RA_REGNUM, + SIM_LM32_BA_REGNUM, + SIM_LM32_EA_REGNUM, + SIM_LM32_PC_REGNUM, + SIM_LM32_EID_REGNUM, + SIM_LM32_EBA_REGNUM, + SIM_LM32_DEBA_REGNUM, + SIM_LM32_IE_REGNUM, + SIM_LM32_IM_REGNUM, + SIM_LM32_IP_REGNUM, + SIM_LM32_NUM_REGS +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdb/sim-m32c.h b/external/gpl3/gdb/dist/include/gdb/sim-m32c.h new file mode 100644 index 000000000000..2d742f496c0a --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-m32c.h @@ -0,0 +1,63 @@ +/* This file defines the interface between the m32c simulator and gdb. + Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef SIM_M32C_H +#define SIM_M32C_H + +enum m32c_sim_reg { + m32c_sim_reg_r0_bank0, + m32c_sim_reg_r1_bank0, + m32c_sim_reg_r2_bank0, + m32c_sim_reg_r3_bank0, + m32c_sim_reg_a0_bank0, + m32c_sim_reg_a1_bank0, + m32c_sim_reg_fb_bank0, + m32c_sim_reg_sb_bank0, + m32c_sim_reg_r0_bank1, + m32c_sim_reg_r1_bank1, + m32c_sim_reg_r2_bank1, + m32c_sim_reg_r3_bank1, + m32c_sim_reg_a0_bank1, + m32c_sim_reg_a1_bank1, + m32c_sim_reg_fb_bank1, + m32c_sim_reg_sb_bank1, + m32c_sim_reg_usp, + m32c_sim_reg_isp, + m32c_sim_reg_pc, + m32c_sim_reg_intb, + m32c_sim_reg_flg, + m32c_sim_reg_svf, + m32c_sim_reg_svp, + m32c_sim_reg_vct, + m32c_sim_reg_dmd0, + m32c_sim_reg_dmd1, + m32c_sim_reg_dct0, + m32c_sim_reg_dct1, + m32c_sim_reg_drc0, + m32c_sim_reg_drc1, + m32c_sim_reg_dma0, + m32c_sim_reg_dma1, + m32c_sim_reg_dsa0, + m32c_sim_reg_dsa1, + m32c_sim_reg_dra0, + m32c_sim_reg_dra1, + m32c_sim_reg_num_regs +}; + +#endif /* SIM_M32C_H */ diff --git a/external/gpl3/gdb/dist/include/gdb/sim-ppc.h b/external/gpl3/gdb/dist/include/gdb/sim-ppc.h new file mode 100644 index 000000000000..3b61a5d947d0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-ppc.h @@ -0,0 +1,773 @@ +/* sim-ppc.h --- interface between PowerPC simulator and GDB. + + Copyright 2004, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_PPC_H) +#define SIM_PPC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* The register access functions, sim_fetch_register and + sim_store_register, use the following numbering for PowerPC + registers. */ + +enum sim_ppc_regnum + { + /* General-purpose registers, r0 -- r31. */ + sim_ppc_r0_regnum, + sim_ppc_r1_regnum, + sim_ppc_r2_regnum, + sim_ppc_r3_regnum, + sim_ppc_r4_regnum, + sim_ppc_r5_regnum, + sim_ppc_r6_regnum, + sim_ppc_r7_regnum, + sim_ppc_r8_regnum, + sim_ppc_r9_regnum, + sim_ppc_r10_regnum, + sim_ppc_r11_regnum, + sim_ppc_r12_regnum, + sim_ppc_r13_regnum, + sim_ppc_r14_regnum, + sim_ppc_r15_regnum, + sim_ppc_r16_regnum, + sim_ppc_r17_regnum, + sim_ppc_r18_regnum, + sim_ppc_r19_regnum, + sim_ppc_r20_regnum, + sim_ppc_r21_regnum, + sim_ppc_r22_regnum, + sim_ppc_r23_regnum, + sim_ppc_r24_regnum, + sim_ppc_r25_regnum, + sim_ppc_r26_regnum, + sim_ppc_r27_regnum, + sim_ppc_r28_regnum, + sim_ppc_r29_regnum, + sim_ppc_r30_regnum, + sim_ppc_r31_regnum, + + /* Floating-point registers, f0 -- f31. */ + sim_ppc_f0_regnum, + sim_ppc_f1_regnum, + sim_ppc_f2_regnum, + sim_ppc_f3_regnum, + sim_ppc_f4_regnum, + sim_ppc_f5_regnum, + sim_ppc_f6_regnum, + sim_ppc_f7_regnum, + sim_ppc_f8_regnum, + sim_ppc_f9_regnum, + sim_ppc_f10_regnum, + sim_ppc_f11_regnum, + sim_ppc_f12_regnum, + sim_ppc_f13_regnum, + sim_ppc_f14_regnum, + sim_ppc_f15_regnum, + sim_ppc_f16_regnum, + sim_ppc_f17_regnum, + sim_ppc_f18_regnum, + sim_ppc_f19_regnum, + sim_ppc_f20_regnum, + sim_ppc_f21_regnum, + sim_ppc_f22_regnum, + sim_ppc_f23_regnum, + sim_ppc_f24_regnum, + sim_ppc_f25_regnum, + sim_ppc_f26_regnum, + sim_ppc_f27_regnum, + sim_ppc_f28_regnum, + sim_ppc_f29_regnum, + sim_ppc_f30_regnum, + sim_ppc_f31_regnum, + + /* Altivec vector registers, vr0 -- vr31. */ + sim_ppc_vr0_regnum, + sim_ppc_vr1_regnum, + sim_ppc_vr2_regnum, + sim_ppc_vr3_regnum, + sim_ppc_vr4_regnum, + sim_ppc_vr5_regnum, + sim_ppc_vr6_regnum, + sim_ppc_vr7_regnum, + sim_ppc_vr8_regnum, + sim_ppc_vr9_regnum, + sim_ppc_vr10_regnum, + sim_ppc_vr11_regnum, + sim_ppc_vr12_regnum, + sim_ppc_vr13_regnum, + sim_ppc_vr14_regnum, + sim_ppc_vr15_regnum, + sim_ppc_vr16_regnum, + sim_ppc_vr17_regnum, + sim_ppc_vr18_regnum, + sim_ppc_vr19_regnum, + sim_ppc_vr20_regnum, + sim_ppc_vr21_regnum, + sim_ppc_vr22_regnum, + sim_ppc_vr23_regnum, + sim_ppc_vr24_regnum, + sim_ppc_vr25_regnum, + sim_ppc_vr26_regnum, + sim_ppc_vr27_regnum, + sim_ppc_vr28_regnum, + sim_ppc_vr29_regnum, + sim_ppc_vr30_regnum, + sim_ppc_vr31_regnum, + + /* SPE APU GPR upper halves. These are the upper 32 bits of the + gprs; there is one upper-half register for each gpr, so it is + appropriate to use sim_ppc_num_gprs for iterating through + these. */ + sim_ppc_rh0_regnum, + sim_ppc_rh1_regnum, + sim_ppc_rh2_regnum, + sim_ppc_rh3_regnum, + sim_ppc_rh4_regnum, + sim_ppc_rh5_regnum, + sim_ppc_rh6_regnum, + sim_ppc_rh7_regnum, + sim_ppc_rh8_regnum, + sim_ppc_rh9_regnum, + sim_ppc_rh10_regnum, + sim_ppc_rh11_regnum, + sim_ppc_rh12_regnum, + sim_ppc_rh13_regnum, + sim_ppc_rh14_regnum, + sim_ppc_rh15_regnum, + sim_ppc_rh16_regnum, + sim_ppc_rh17_regnum, + sim_ppc_rh18_regnum, + sim_ppc_rh19_regnum, + sim_ppc_rh20_regnum, + sim_ppc_rh21_regnum, + sim_ppc_rh22_regnum, + sim_ppc_rh23_regnum, + sim_ppc_rh24_regnum, + sim_ppc_rh25_regnum, + sim_ppc_rh26_regnum, + sim_ppc_rh27_regnum, + sim_ppc_rh28_regnum, + sim_ppc_rh29_regnum, + sim_ppc_rh30_regnum, + sim_ppc_rh31_regnum, + + /* SPE APU GPR full registers. Each of these registers is the + 64-bit concatenation of a 32-bit GPR (providing the lower bits) + and a 32-bit upper-half register (providing the higher bits). + As for the upper-half registers, it is appropriate to use + sim_ppc_num_gprs with these. */ + sim_ppc_ev0_regnum, + sim_ppc_ev1_regnum, + sim_ppc_ev2_regnum, + sim_ppc_ev3_regnum, + sim_ppc_ev4_regnum, + sim_ppc_ev5_regnum, + sim_ppc_ev6_regnum, + sim_ppc_ev7_regnum, + sim_ppc_ev8_regnum, + sim_ppc_ev9_regnum, + sim_ppc_ev10_regnum, + sim_ppc_ev11_regnum, + sim_ppc_ev12_regnum, + sim_ppc_ev13_regnum, + sim_ppc_ev14_regnum, + sim_ppc_ev15_regnum, + sim_ppc_ev16_regnum, + sim_ppc_ev17_regnum, + sim_ppc_ev18_regnum, + sim_ppc_ev19_regnum, + sim_ppc_ev20_regnum, + sim_ppc_ev21_regnum, + sim_ppc_ev22_regnum, + sim_ppc_ev23_regnum, + sim_ppc_ev24_regnum, + sim_ppc_ev25_regnum, + sim_ppc_ev26_regnum, + sim_ppc_ev27_regnum, + sim_ppc_ev28_regnum, + sim_ppc_ev29_regnum, + sim_ppc_ev30_regnum, + sim_ppc_ev31_regnum, + + /* Segment registers, sr0 -- sr15. */ + sim_ppc_sr0_regnum, + sim_ppc_sr1_regnum, + sim_ppc_sr2_regnum, + sim_ppc_sr3_regnum, + sim_ppc_sr4_regnum, + sim_ppc_sr5_regnum, + sim_ppc_sr6_regnum, + sim_ppc_sr7_regnum, + sim_ppc_sr8_regnum, + sim_ppc_sr9_regnum, + sim_ppc_sr10_regnum, + sim_ppc_sr11_regnum, + sim_ppc_sr12_regnum, + sim_ppc_sr13_regnum, + sim_ppc_sr14_regnum, + sim_ppc_sr15_regnum, + + /* Miscellaneous --- but non-SPR --- registers. */ + sim_ppc_pc_regnum, + sim_ppc_ps_regnum, + sim_ppc_cr_regnum, + sim_ppc_fpscr_regnum, + sim_ppc_acc_regnum, + sim_ppc_vscr_regnum, + + /* Special-purpose registers. */ + sim_ppc_spr0_regnum, sim_ppc_spr1_regnum, + sim_ppc_spr2_regnum, sim_ppc_spr3_regnum, + sim_ppc_spr4_regnum, sim_ppc_spr5_regnum, + sim_ppc_spr6_regnum, sim_ppc_spr7_regnum, + sim_ppc_spr8_regnum, sim_ppc_spr9_regnum, + sim_ppc_spr10_regnum, sim_ppc_spr11_regnum, + sim_ppc_spr12_regnum, sim_ppc_spr13_regnum, + sim_ppc_spr14_regnum, sim_ppc_spr15_regnum, + sim_ppc_spr16_regnum, sim_ppc_spr17_regnum, + sim_ppc_spr18_regnum, sim_ppc_spr19_regnum, + sim_ppc_spr20_regnum, sim_ppc_spr21_regnum, + sim_ppc_spr22_regnum, sim_ppc_spr23_regnum, + sim_ppc_spr24_regnum, sim_ppc_spr25_regnum, + sim_ppc_spr26_regnum, sim_ppc_spr27_regnum, + sim_ppc_spr28_regnum, sim_ppc_spr29_regnum, + sim_ppc_spr30_regnum, sim_ppc_spr31_regnum, + sim_ppc_spr32_regnum, sim_ppc_spr33_regnum, + sim_ppc_spr34_regnum, sim_ppc_spr35_regnum, + sim_ppc_spr36_regnum, sim_ppc_spr37_regnum, + sim_ppc_spr38_regnum, sim_ppc_spr39_regnum, + sim_ppc_spr40_regnum, sim_ppc_spr41_regnum, + sim_ppc_spr42_regnum, sim_ppc_spr43_regnum, + sim_ppc_spr44_regnum, sim_ppc_spr45_regnum, + sim_ppc_spr46_regnum, sim_ppc_spr47_regnum, + sim_ppc_spr48_regnum, sim_ppc_spr49_regnum, + sim_ppc_spr50_regnum, sim_ppc_spr51_regnum, + sim_ppc_spr52_regnum, sim_ppc_spr53_regnum, + sim_ppc_spr54_regnum, sim_ppc_spr55_regnum, + sim_ppc_spr56_regnum, sim_ppc_spr57_regnum, + sim_ppc_spr58_regnum, sim_ppc_spr59_regnum, + sim_ppc_spr60_regnum, sim_ppc_spr61_regnum, + sim_ppc_spr62_regnum, sim_ppc_spr63_regnum, + sim_ppc_spr64_regnum, sim_ppc_spr65_regnum, + sim_ppc_spr66_regnum, sim_ppc_spr67_regnum, + sim_ppc_spr68_regnum, sim_ppc_spr69_regnum, + sim_ppc_spr70_regnum, sim_ppc_spr71_regnum, + sim_ppc_spr72_regnum, sim_ppc_spr73_regnum, + sim_ppc_spr74_regnum, sim_ppc_spr75_regnum, + sim_ppc_spr76_regnum, sim_ppc_spr77_regnum, + sim_ppc_spr78_regnum, sim_ppc_spr79_regnum, + sim_ppc_spr80_regnum, sim_ppc_spr81_regnum, + sim_ppc_spr82_regnum, sim_ppc_spr83_regnum, + sim_ppc_spr84_regnum, sim_ppc_spr85_regnum, + sim_ppc_spr86_regnum, sim_ppc_spr87_regnum, + sim_ppc_spr88_regnum, sim_ppc_spr89_regnum, + sim_ppc_spr90_regnum, sim_ppc_spr91_regnum, + sim_ppc_spr92_regnum, sim_ppc_spr93_regnum, + sim_ppc_spr94_regnum, sim_ppc_spr95_regnum, + sim_ppc_spr96_regnum, sim_ppc_spr97_regnum, + sim_ppc_spr98_regnum, sim_ppc_spr99_regnum, + sim_ppc_spr100_regnum, sim_ppc_spr101_regnum, + sim_ppc_spr102_regnum, sim_ppc_spr103_regnum, + sim_ppc_spr104_regnum, sim_ppc_spr105_regnum, + sim_ppc_spr106_regnum, sim_ppc_spr107_regnum, + sim_ppc_spr108_regnum, sim_ppc_spr109_regnum, + sim_ppc_spr110_regnum, sim_ppc_spr111_regnum, + sim_ppc_spr112_regnum, sim_ppc_spr113_regnum, + sim_ppc_spr114_regnum, sim_ppc_spr115_regnum, + sim_ppc_spr116_regnum, sim_ppc_spr117_regnum, + sim_ppc_spr118_regnum, sim_ppc_spr119_regnum, + sim_ppc_spr120_regnum, sim_ppc_spr121_regnum, + sim_ppc_spr122_regnum, sim_ppc_spr123_regnum, + sim_ppc_spr124_regnum, sim_ppc_spr125_regnum, + sim_ppc_spr126_regnum, sim_ppc_spr127_regnum, + sim_ppc_spr128_regnum, sim_ppc_spr129_regnum, + sim_ppc_spr130_regnum, sim_ppc_spr131_regnum, + sim_ppc_spr132_regnum, sim_ppc_spr133_regnum, + sim_ppc_spr134_regnum, sim_ppc_spr135_regnum, + sim_ppc_spr136_regnum, sim_ppc_spr137_regnum, + sim_ppc_spr138_regnum, sim_ppc_spr139_regnum, + sim_ppc_spr140_regnum, sim_ppc_spr141_regnum, + sim_ppc_spr142_regnum, sim_ppc_spr143_regnum, + sim_ppc_spr144_regnum, sim_ppc_spr145_regnum, + sim_ppc_spr146_regnum, sim_ppc_spr147_regnum, + sim_ppc_spr148_regnum, sim_ppc_spr149_regnum, + sim_ppc_spr150_regnum, sim_ppc_spr151_regnum, + sim_ppc_spr152_regnum, sim_ppc_spr153_regnum, + sim_ppc_spr154_regnum, sim_ppc_spr155_regnum, + sim_ppc_spr156_regnum, sim_ppc_spr157_regnum, + sim_ppc_spr158_regnum, sim_ppc_spr159_regnum, + sim_ppc_spr160_regnum, sim_ppc_spr161_regnum, + sim_ppc_spr162_regnum, sim_ppc_spr163_regnum, + sim_ppc_spr164_regnum, sim_ppc_spr165_regnum, + sim_ppc_spr166_regnum, sim_ppc_spr167_regnum, + sim_ppc_spr168_regnum, sim_ppc_spr169_regnum, + sim_ppc_spr170_regnum, sim_ppc_spr171_regnum, + sim_ppc_spr172_regnum, sim_ppc_spr173_regnum, + sim_ppc_spr174_regnum, sim_ppc_spr175_regnum, + sim_ppc_spr176_regnum, sim_ppc_spr177_regnum, + sim_ppc_spr178_regnum, sim_ppc_spr179_regnum, + sim_ppc_spr180_regnum, sim_ppc_spr181_regnum, + sim_ppc_spr182_regnum, sim_ppc_spr183_regnum, + sim_ppc_spr184_regnum, sim_ppc_spr185_regnum, + sim_ppc_spr186_regnum, sim_ppc_spr187_regnum, + sim_ppc_spr188_regnum, sim_ppc_spr189_regnum, + sim_ppc_spr190_regnum, sim_ppc_spr191_regnum, + sim_ppc_spr192_regnum, sim_ppc_spr193_regnum, + sim_ppc_spr194_regnum, sim_ppc_spr195_regnum, + sim_ppc_spr196_regnum, sim_ppc_spr197_regnum, + sim_ppc_spr198_regnum, sim_ppc_spr199_regnum, + sim_ppc_spr200_regnum, sim_ppc_spr201_regnum, + sim_ppc_spr202_regnum, sim_ppc_spr203_regnum, + sim_ppc_spr204_regnum, sim_ppc_spr205_regnum, + sim_ppc_spr206_regnum, sim_ppc_spr207_regnum, + sim_ppc_spr208_regnum, sim_ppc_spr209_regnum, + sim_ppc_spr210_regnum, sim_ppc_spr211_regnum, + sim_ppc_spr212_regnum, sim_ppc_spr213_regnum, + sim_ppc_spr214_regnum, sim_ppc_spr215_regnum, + sim_ppc_spr216_regnum, sim_ppc_spr217_regnum, + sim_ppc_spr218_regnum, sim_ppc_spr219_regnum, + sim_ppc_spr220_regnum, sim_ppc_spr221_regnum, + sim_ppc_spr222_regnum, sim_ppc_spr223_regnum, + sim_ppc_spr224_regnum, sim_ppc_spr225_regnum, + sim_ppc_spr226_regnum, sim_ppc_spr227_regnum, + sim_ppc_spr228_regnum, sim_ppc_spr229_regnum, + sim_ppc_spr230_regnum, sim_ppc_spr231_regnum, + sim_ppc_spr232_regnum, sim_ppc_spr233_regnum, + sim_ppc_spr234_regnum, sim_ppc_spr235_regnum, + sim_ppc_spr236_regnum, sim_ppc_spr237_regnum, + sim_ppc_spr238_regnum, sim_ppc_spr239_regnum, + sim_ppc_spr240_regnum, sim_ppc_spr241_regnum, + sim_ppc_spr242_regnum, sim_ppc_spr243_regnum, + sim_ppc_spr244_regnum, sim_ppc_spr245_regnum, + sim_ppc_spr246_regnum, sim_ppc_spr247_regnum, + sim_ppc_spr248_regnum, sim_ppc_spr249_regnum, + sim_ppc_spr250_regnum, sim_ppc_spr251_regnum, + sim_ppc_spr252_regnum, sim_ppc_spr253_regnum, + sim_ppc_spr254_regnum, sim_ppc_spr255_regnum, + sim_ppc_spr256_regnum, sim_ppc_spr257_regnum, + sim_ppc_spr258_regnum, sim_ppc_spr259_regnum, + sim_ppc_spr260_regnum, sim_ppc_spr261_regnum, + sim_ppc_spr262_regnum, sim_ppc_spr263_regnum, + sim_ppc_spr264_regnum, sim_ppc_spr265_regnum, + sim_ppc_spr266_regnum, sim_ppc_spr267_regnum, + sim_ppc_spr268_regnum, sim_ppc_spr269_regnum, + sim_ppc_spr270_regnum, sim_ppc_spr271_regnum, + sim_ppc_spr272_regnum, sim_ppc_spr273_regnum, + sim_ppc_spr274_regnum, sim_ppc_spr275_regnum, + sim_ppc_spr276_regnum, sim_ppc_spr277_regnum, + sim_ppc_spr278_regnum, sim_ppc_spr279_regnum, + sim_ppc_spr280_regnum, sim_ppc_spr281_regnum, + sim_ppc_spr282_regnum, sim_ppc_spr283_regnum, + sim_ppc_spr284_regnum, sim_ppc_spr285_regnum, + sim_ppc_spr286_regnum, sim_ppc_spr287_regnum, + sim_ppc_spr288_regnum, sim_ppc_spr289_regnum, + sim_ppc_spr290_regnum, sim_ppc_spr291_regnum, + sim_ppc_spr292_regnum, sim_ppc_spr293_regnum, + sim_ppc_spr294_regnum, sim_ppc_spr295_regnum, + sim_ppc_spr296_regnum, sim_ppc_spr297_regnum, + sim_ppc_spr298_regnum, sim_ppc_spr299_regnum, + sim_ppc_spr300_regnum, sim_ppc_spr301_regnum, + sim_ppc_spr302_regnum, sim_ppc_spr303_regnum, + sim_ppc_spr304_regnum, sim_ppc_spr305_regnum, + sim_ppc_spr306_regnum, sim_ppc_spr307_regnum, + sim_ppc_spr308_regnum, sim_ppc_spr309_regnum, + sim_ppc_spr310_regnum, sim_ppc_spr311_regnum, + sim_ppc_spr312_regnum, sim_ppc_spr313_regnum, + sim_ppc_spr314_regnum, sim_ppc_spr315_regnum, + sim_ppc_spr316_regnum, sim_ppc_spr317_regnum, + sim_ppc_spr318_regnum, sim_ppc_spr319_regnum, + sim_ppc_spr320_regnum, sim_ppc_spr321_regnum, + sim_ppc_spr322_regnum, sim_ppc_spr323_regnum, + sim_ppc_spr324_regnum, sim_ppc_spr325_regnum, + sim_ppc_spr326_regnum, sim_ppc_spr327_regnum, + sim_ppc_spr328_regnum, sim_ppc_spr329_regnum, + sim_ppc_spr330_regnum, sim_ppc_spr331_regnum, + sim_ppc_spr332_regnum, sim_ppc_spr333_regnum, + sim_ppc_spr334_regnum, sim_ppc_spr335_regnum, + sim_ppc_spr336_regnum, sim_ppc_spr337_regnum, + sim_ppc_spr338_regnum, sim_ppc_spr339_regnum, + sim_ppc_spr340_regnum, sim_ppc_spr341_regnum, + sim_ppc_spr342_regnum, sim_ppc_spr343_regnum, + sim_ppc_spr344_regnum, sim_ppc_spr345_regnum, + sim_ppc_spr346_regnum, sim_ppc_spr347_regnum, + sim_ppc_spr348_regnum, sim_ppc_spr349_regnum, + sim_ppc_spr350_regnum, sim_ppc_spr351_regnum, + sim_ppc_spr352_regnum, sim_ppc_spr353_regnum, + sim_ppc_spr354_regnum, sim_ppc_spr355_regnum, + sim_ppc_spr356_regnum, sim_ppc_spr357_regnum, + sim_ppc_spr358_regnum, sim_ppc_spr359_regnum, + sim_ppc_spr360_regnum, sim_ppc_spr361_regnum, + sim_ppc_spr362_regnum, sim_ppc_spr363_regnum, + sim_ppc_spr364_regnum, sim_ppc_spr365_regnum, + sim_ppc_spr366_regnum, sim_ppc_spr367_regnum, + sim_ppc_spr368_regnum, sim_ppc_spr369_regnum, + sim_ppc_spr370_regnum, sim_ppc_spr371_regnum, + sim_ppc_spr372_regnum, sim_ppc_spr373_regnum, + sim_ppc_spr374_regnum, sim_ppc_spr375_regnum, + sim_ppc_spr376_regnum, sim_ppc_spr377_regnum, + sim_ppc_spr378_regnum, sim_ppc_spr379_regnum, + sim_ppc_spr380_regnum, sim_ppc_spr381_regnum, + sim_ppc_spr382_regnum, sim_ppc_spr383_regnum, + sim_ppc_spr384_regnum, sim_ppc_spr385_regnum, + sim_ppc_spr386_regnum, sim_ppc_spr387_regnum, + sim_ppc_spr388_regnum, sim_ppc_spr389_regnum, + sim_ppc_spr390_regnum, sim_ppc_spr391_regnum, + sim_ppc_spr392_regnum, sim_ppc_spr393_regnum, + sim_ppc_spr394_regnum, sim_ppc_spr395_regnum, + sim_ppc_spr396_regnum, sim_ppc_spr397_regnum, + sim_ppc_spr398_regnum, sim_ppc_spr399_regnum, + sim_ppc_spr400_regnum, sim_ppc_spr401_regnum, + sim_ppc_spr402_regnum, sim_ppc_spr403_regnum, + sim_ppc_spr404_regnum, sim_ppc_spr405_regnum, + sim_ppc_spr406_regnum, sim_ppc_spr407_regnum, + sim_ppc_spr408_regnum, sim_ppc_spr409_regnum, + sim_ppc_spr410_regnum, sim_ppc_spr411_regnum, + sim_ppc_spr412_regnum, sim_ppc_spr413_regnum, + sim_ppc_spr414_regnum, sim_ppc_spr415_regnum, + sim_ppc_spr416_regnum, sim_ppc_spr417_regnum, + sim_ppc_spr418_regnum, sim_ppc_spr419_regnum, + sim_ppc_spr420_regnum, sim_ppc_spr421_regnum, + sim_ppc_spr422_regnum, sim_ppc_spr423_regnum, + sim_ppc_spr424_regnum, sim_ppc_spr425_regnum, + sim_ppc_spr426_regnum, sim_ppc_spr427_regnum, + sim_ppc_spr428_regnum, sim_ppc_spr429_regnum, + sim_ppc_spr430_regnum, sim_ppc_spr431_regnum, + sim_ppc_spr432_regnum, sim_ppc_spr433_regnum, + sim_ppc_spr434_regnum, sim_ppc_spr435_regnum, + sim_ppc_spr436_regnum, sim_ppc_spr437_regnum, + sim_ppc_spr438_regnum, sim_ppc_spr439_regnum, + sim_ppc_spr440_regnum, sim_ppc_spr441_regnum, + sim_ppc_spr442_regnum, sim_ppc_spr443_regnum, + sim_ppc_spr444_regnum, sim_ppc_spr445_regnum, + sim_ppc_spr446_regnum, sim_ppc_spr447_regnum, + sim_ppc_spr448_regnum, sim_ppc_spr449_regnum, + sim_ppc_spr450_regnum, sim_ppc_spr451_regnum, + sim_ppc_spr452_regnum, sim_ppc_spr453_regnum, + sim_ppc_spr454_regnum, sim_ppc_spr455_regnum, + sim_ppc_spr456_regnum, sim_ppc_spr457_regnum, + sim_ppc_spr458_regnum, sim_ppc_spr459_regnum, + sim_ppc_spr460_regnum, sim_ppc_spr461_regnum, + sim_ppc_spr462_regnum, sim_ppc_spr463_regnum, + sim_ppc_spr464_regnum, sim_ppc_spr465_regnum, + sim_ppc_spr466_regnum, sim_ppc_spr467_regnum, + sim_ppc_spr468_regnum, sim_ppc_spr469_regnum, + sim_ppc_spr470_regnum, sim_ppc_spr471_regnum, + sim_ppc_spr472_regnum, sim_ppc_spr473_regnum, + sim_ppc_spr474_regnum, sim_ppc_spr475_regnum, + sim_ppc_spr476_regnum, sim_ppc_spr477_regnum, + sim_ppc_spr478_regnum, sim_ppc_spr479_regnum, + sim_ppc_spr480_regnum, sim_ppc_spr481_regnum, + sim_ppc_spr482_regnum, sim_ppc_spr483_regnum, + sim_ppc_spr484_regnum, sim_ppc_spr485_regnum, + sim_ppc_spr486_regnum, sim_ppc_spr487_regnum, + sim_ppc_spr488_regnum, sim_ppc_spr489_regnum, + sim_ppc_spr490_regnum, sim_ppc_spr491_regnum, + sim_ppc_spr492_regnum, sim_ppc_spr493_regnum, + sim_ppc_spr494_regnum, sim_ppc_spr495_regnum, + sim_ppc_spr496_regnum, sim_ppc_spr497_regnum, + sim_ppc_spr498_regnum, sim_ppc_spr499_regnum, + sim_ppc_spr500_regnum, sim_ppc_spr501_regnum, + sim_ppc_spr502_regnum, sim_ppc_spr503_regnum, + sim_ppc_spr504_regnum, sim_ppc_spr505_regnum, + sim_ppc_spr506_regnum, sim_ppc_spr507_regnum, + sim_ppc_spr508_regnum, sim_ppc_spr509_regnum, + sim_ppc_spr510_regnum, sim_ppc_spr511_regnum, + sim_ppc_spr512_regnum, sim_ppc_spr513_regnum, + sim_ppc_spr514_regnum, sim_ppc_spr515_regnum, + sim_ppc_spr516_regnum, sim_ppc_spr517_regnum, + sim_ppc_spr518_regnum, sim_ppc_spr519_regnum, + sim_ppc_spr520_regnum, sim_ppc_spr521_regnum, + sim_ppc_spr522_regnum, sim_ppc_spr523_regnum, + sim_ppc_spr524_regnum, sim_ppc_spr525_regnum, + sim_ppc_spr526_regnum, sim_ppc_spr527_regnum, + sim_ppc_spr528_regnum, sim_ppc_spr529_regnum, + sim_ppc_spr530_regnum, sim_ppc_spr531_regnum, + sim_ppc_spr532_regnum, sim_ppc_spr533_regnum, + sim_ppc_spr534_regnum, sim_ppc_spr535_regnum, + sim_ppc_spr536_regnum, sim_ppc_spr537_regnum, + sim_ppc_spr538_regnum, sim_ppc_spr539_regnum, + sim_ppc_spr540_regnum, sim_ppc_spr541_regnum, + sim_ppc_spr542_regnum, sim_ppc_spr543_regnum, + sim_ppc_spr544_regnum, sim_ppc_spr545_regnum, + sim_ppc_spr546_regnum, sim_ppc_spr547_regnum, + sim_ppc_spr548_regnum, sim_ppc_spr549_regnum, + sim_ppc_spr550_regnum, sim_ppc_spr551_regnum, + sim_ppc_spr552_regnum, sim_ppc_spr553_regnum, + sim_ppc_spr554_regnum, sim_ppc_spr555_regnum, + sim_ppc_spr556_regnum, sim_ppc_spr557_regnum, + sim_ppc_spr558_regnum, sim_ppc_spr559_regnum, + sim_ppc_spr560_regnum, sim_ppc_spr561_regnum, + sim_ppc_spr562_regnum, sim_ppc_spr563_regnum, + sim_ppc_spr564_regnum, sim_ppc_spr565_regnum, + sim_ppc_spr566_regnum, sim_ppc_spr567_regnum, + sim_ppc_spr568_regnum, sim_ppc_spr569_regnum, + sim_ppc_spr570_regnum, sim_ppc_spr571_regnum, + sim_ppc_spr572_regnum, sim_ppc_spr573_regnum, + sim_ppc_spr574_regnum, sim_ppc_spr575_regnum, + sim_ppc_spr576_regnum, sim_ppc_spr577_regnum, + sim_ppc_spr578_regnum, sim_ppc_spr579_regnum, + sim_ppc_spr580_regnum, sim_ppc_spr581_regnum, + sim_ppc_spr582_regnum, sim_ppc_spr583_regnum, + sim_ppc_spr584_regnum, sim_ppc_spr585_regnum, + sim_ppc_spr586_regnum, sim_ppc_spr587_regnum, + sim_ppc_spr588_regnum, sim_ppc_spr589_regnum, + sim_ppc_spr590_regnum, sim_ppc_spr591_regnum, + sim_ppc_spr592_regnum, sim_ppc_spr593_regnum, + sim_ppc_spr594_regnum, sim_ppc_spr595_regnum, + sim_ppc_spr596_regnum, sim_ppc_spr597_regnum, + sim_ppc_spr598_regnum, sim_ppc_spr599_regnum, + sim_ppc_spr600_regnum, sim_ppc_spr601_regnum, + sim_ppc_spr602_regnum, sim_ppc_spr603_regnum, + sim_ppc_spr604_regnum, sim_ppc_spr605_regnum, + sim_ppc_spr606_regnum, sim_ppc_spr607_regnum, + sim_ppc_spr608_regnum, sim_ppc_spr609_regnum, + sim_ppc_spr610_regnum, sim_ppc_spr611_regnum, + sim_ppc_spr612_regnum, sim_ppc_spr613_regnum, + sim_ppc_spr614_regnum, sim_ppc_spr615_regnum, + sim_ppc_spr616_regnum, sim_ppc_spr617_regnum, + sim_ppc_spr618_regnum, sim_ppc_spr619_regnum, + sim_ppc_spr620_regnum, sim_ppc_spr621_regnum, + sim_ppc_spr622_regnum, sim_ppc_spr623_regnum, + sim_ppc_spr624_regnum, sim_ppc_spr625_regnum, + sim_ppc_spr626_regnum, sim_ppc_spr627_regnum, + sim_ppc_spr628_regnum, sim_ppc_spr629_regnum, + sim_ppc_spr630_regnum, sim_ppc_spr631_regnum, + sim_ppc_spr632_regnum, sim_ppc_spr633_regnum, + sim_ppc_spr634_regnum, sim_ppc_spr635_regnum, + sim_ppc_spr636_regnum, sim_ppc_spr637_regnum, + sim_ppc_spr638_regnum, sim_ppc_spr639_regnum, + sim_ppc_spr640_regnum, sim_ppc_spr641_regnum, + sim_ppc_spr642_regnum, sim_ppc_spr643_regnum, + sim_ppc_spr644_regnum, sim_ppc_spr645_regnum, + sim_ppc_spr646_regnum, sim_ppc_spr647_regnum, + sim_ppc_spr648_regnum, sim_ppc_spr649_regnum, + sim_ppc_spr650_regnum, sim_ppc_spr651_regnum, + sim_ppc_spr652_regnum, sim_ppc_spr653_regnum, + sim_ppc_spr654_regnum, sim_ppc_spr655_regnum, + sim_ppc_spr656_regnum, sim_ppc_spr657_regnum, + sim_ppc_spr658_regnum, sim_ppc_spr659_regnum, + sim_ppc_spr660_regnum, sim_ppc_spr661_regnum, + sim_ppc_spr662_regnum, sim_ppc_spr663_regnum, + sim_ppc_spr664_regnum, sim_ppc_spr665_regnum, + sim_ppc_spr666_regnum, sim_ppc_spr667_regnum, + sim_ppc_spr668_regnum, sim_ppc_spr669_regnum, + sim_ppc_spr670_regnum, sim_ppc_spr671_regnum, + sim_ppc_spr672_regnum, sim_ppc_spr673_regnum, + sim_ppc_spr674_regnum, sim_ppc_spr675_regnum, + sim_ppc_spr676_regnum, sim_ppc_spr677_regnum, + sim_ppc_spr678_regnum, sim_ppc_spr679_regnum, + sim_ppc_spr680_regnum, sim_ppc_spr681_regnum, + sim_ppc_spr682_regnum, sim_ppc_spr683_regnum, + sim_ppc_spr684_regnum, sim_ppc_spr685_regnum, + sim_ppc_spr686_regnum, sim_ppc_spr687_regnum, + sim_ppc_spr688_regnum, sim_ppc_spr689_regnum, + sim_ppc_spr690_regnum, sim_ppc_spr691_regnum, + sim_ppc_spr692_regnum, sim_ppc_spr693_regnum, + sim_ppc_spr694_regnum, sim_ppc_spr695_regnum, + sim_ppc_spr696_regnum, sim_ppc_spr697_regnum, + sim_ppc_spr698_regnum, sim_ppc_spr699_regnum, + sim_ppc_spr700_regnum, sim_ppc_spr701_regnum, + sim_ppc_spr702_regnum, sim_ppc_spr703_regnum, + sim_ppc_spr704_regnum, sim_ppc_spr705_regnum, + sim_ppc_spr706_regnum, sim_ppc_spr707_regnum, + sim_ppc_spr708_regnum, sim_ppc_spr709_regnum, + sim_ppc_spr710_regnum, sim_ppc_spr711_regnum, + sim_ppc_spr712_regnum, sim_ppc_spr713_regnum, + sim_ppc_spr714_regnum, sim_ppc_spr715_regnum, + sim_ppc_spr716_regnum, sim_ppc_spr717_regnum, + sim_ppc_spr718_regnum, sim_ppc_spr719_regnum, + sim_ppc_spr720_regnum, sim_ppc_spr721_regnum, + sim_ppc_spr722_regnum, sim_ppc_spr723_regnum, + sim_ppc_spr724_regnum, sim_ppc_spr725_regnum, + sim_ppc_spr726_regnum, sim_ppc_spr727_regnum, + sim_ppc_spr728_regnum, sim_ppc_spr729_regnum, + sim_ppc_spr730_regnum, sim_ppc_spr731_regnum, + sim_ppc_spr732_regnum, sim_ppc_spr733_regnum, + sim_ppc_spr734_regnum, sim_ppc_spr735_regnum, + sim_ppc_spr736_regnum, sim_ppc_spr737_regnum, + sim_ppc_spr738_regnum, sim_ppc_spr739_regnum, + sim_ppc_spr740_regnum, sim_ppc_spr741_regnum, + sim_ppc_spr742_regnum, sim_ppc_spr743_regnum, + sim_ppc_spr744_regnum, sim_ppc_spr745_regnum, + sim_ppc_spr746_regnum, sim_ppc_spr747_regnum, + sim_ppc_spr748_regnum, sim_ppc_spr749_regnum, + sim_ppc_spr750_regnum, sim_ppc_spr751_regnum, + sim_ppc_spr752_regnum, sim_ppc_spr753_regnum, + sim_ppc_spr754_regnum, sim_ppc_spr755_regnum, + sim_ppc_spr756_regnum, sim_ppc_spr757_regnum, + sim_ppc_spr758_regnum, sim_ppc_spr759_regnum, + sim_ppc_spr760_regnum, sim_ppc_spr761_regnum, + sim_ppc_spr762_regnum, sim_ppc_spr763_regnum, + sim_ppc_spr764_regnum, sim_ppc_spr765_regnum, + sim_ppc_spr766_regnum, sim_ppc_spr767_regnum, + sim_ppc_spr768_regnum, sim_ppc_spr769_regnum, + sim_ppc_spr770_regnum, sim_ppc_spr771_regnum, + sim_ppc_spr772_regnum, sim_ppc_spr773_regnum, + sim_ppc_spr774_regnum, sim_ppc_spr775_regnum, + sim_ppc_spr776_regnum, sim_ppc_spr777_regnum, + sim_ppc_spr778_regnum, sim_ppc_spr779_regnum, + sim_ppc_spr780_regnum, sim_ppc_spr781_regnum, + sim_ppc_spr782_regnum, sim_ppc_spr783_regnum, + sim_ppc_spr784_regnum, sim_ppc_spr785_regnum, + sim_ppc_spr786_regnum, sim_ppc_spr787_regnum, + sim_ppc_spr788_regnum, sim_ppc_spr789_regnum, + sim_ppc_spr790_regnum, sim_ppc_spr791_regnum, + sim_ppc_spr792_regnum, sim_ppc_spr793_regnum, + sim_ppc_spr794_regnum, sim_ppc_spr795_regnum, + sim_ppc_spr796_regnum, sim_ppc_spr797_regnum, + sim_ppc_spr798_regnum, sim_ppc_spr799_regnum, + sim_ppc_spr800_regnum, sim_ppc_spr801_regnum, + sim_ppc_spr802_regnum, sim_ppc_spr803_regnum, + sim_ppc_spr804_regnum, sim_ppc_spr805_regnum, + sim_ppc_spr806_regnum, sim_ppc_spr807_regnum, + sim_ppc_spr808_regnum, sim_ppc_spr809_regnum, + sim_ppc_spr810_regnum, sim_ppc_spr811_regnum, + sim_ppc_spr812_regnum, sim_ppc_spr813_regnum, + sim_ppc_spr814_regnum, sim_ppc_spr815_regnum, + sim_ppc_spr816_regnum, sim_ppc_spr817_regnum, + sim_ppc_spr818_regnum, sim_ppc_spr819_regnum, + sim_ppc_spr820_regnum, sim_ppc_spr821_regnum, + sim_ppc_spr822_regnum, sim_ppc_spr823_regnum, + sim_ppc_spr824_regnum, sim_ppc_spr825_regnum, + sim_ppc_spr826_regnum, sim_ppc_spr827_regnum, + sim_ppc_spr828_regnum, sim_ppc_spr829_regnum, + sim_ppc_spr830_regnum, sim_ppc_spr831_regnum, + sim_ppc_spr832_regnum, sim_ppc_spr833_regnum, + sim_ppc_spr834_regnum, sim_ppc_spr835_regnum, + sim_ppc_spr836_regnum, sim_ppc_spr837_regnum, + sim_ppc_spr838_regnum, sim_ppc_spr839_regnum, + sim_ppc_spr840_regnum, sim_ppc_spr841_regnum, + sim_ppc_spr842_regnum, sim_ppc_spr843_regnum, + sim_ppc_spr844_regnum, sim_ppc_spr845_regnum, + sim_ppc_spr846_regnum, sim_ppc_spr847_regnum, + sim_ppc_spr848_regnum, sim_ppc_spr849_regnum, + sim_ppc_spr850_regnum, sim_ppc_spr851_regnum, + sim_ppc_spr852_regnum, sim_ppc_spr853_regnum, + sim_ppc_spr854_regnum, sim_ppc_spr855_regnum, + sim_ppc_spr856_regnum, sim_ppc_spr857_regnum, + sim_ppc_spr858_regnum, sim_ppc_spr859_regnum, + sim_ppc_spr860_regnum, sim_ppc_spr861_regnum, + sim_ppc_spr862_regnum, sim_ppc_spr863_regnum, + sim_ppc_spr864_regnum, sim_ppc_spr865_regnum, + sim_ppc_spr866_regnum, sim_ppc_spr867_regnum, + sim_ppc_spr868_regnum, sim_ppc_spr869_regnum, + sim_ppc_spr870_regnum, sim_ppc_spr871_regnum, + sim_ppc_spr872_regnum, sim_ppc_spr873_regnum, + sim_ppc_spr874_regnum, sim_ppc_spr875_regnum, + sim_ppc_spr876_regnum, sim_ppc_spr877_regnum, + sim_ppc_spr878_regnum, sim_ppc_spr879_regnum, + sim_ppc_spr880_regnum, sim_ppc_spr881_regnum, + sim_ppc_spr882_regnum, sim_ppc_spr883_regnum, + sim_ppc_spr884_regnum, sim_ppc_spr885_regnum, + sim_ppc_spr886_regnum, sim_ppc_spr887_regnum, + sim_ppc_spr888_regnum, sim_ppc_spr889_regnum, + sim_ppc_spr890_regnum, sim_ppc_spr891_regnum, + sim_ppc_spr892_regnum, sim_ppc_spr893_regnum, + sim_ppc_spr894_regnum, sim_ppc_spr895_regnum, + sim_ppc_spr896_regnum, sim_ppc_spr897_regnum, + sim_ppc_spr898_regnum, sim_ppc_spr899_regnum, + sim_ppc_spr900_regnum, sim_ppc_spr901_regnum, + sim_ppc_spr902_regnum, sim_ppc_spr903_regnum, + sim_ppc_spr904_regnum, sim_ppc_spr905_regnum, + sim_ppc_spr906_regnum, sim_ppc_spr907_regnum, + sim_ppc_spr908_regnum, sim_ppc_spr909_regnum, + sim_ppc_spr910_regnum, sim_ppc_spr911_regnum, + sim_ppc_spr912_regnum, sim_ppc_spr913_regnum, + sim_ppc_spr914_regnum, sim_ppc_spr915_regnum, + sim_ppc_spr916_regnum, sim_ppc_spr917_regnum, + sim_ppc_spr918_regnum, sim_ppc_spr919_regnum, + sim_ppc_spr920_regnum, sim_ppc_spr921_regnum, + sim_ppc_spr922_regnum, sim_ppc_spr923_regnum, + sim_ppc_spr924_regnum, sim_ppc_spr925_regnum, + sim_ppc_spr926_regnum, sim_ppc_spr927_regnum, + sim_ppc_spr928_regnum, sim_ppc_spr929_regnum, + sim_ppc_spr930_regnum, sim_ppc_spr931_regnum, + sim_ppc_spr932_regnum, sim_ppc_spr933_regnum, + sim_ppc_spr934_regnum, sim_ppc_spr935_regnum, + sim_ppc_spr936_regnum, sim_ppc_spr937_regnum, + sim_ppc_spr938_regnum, sim_ppc_spr939_regnum, + sim_ppc_spr940_regnum, sim_ppc_spr941_regnum, + sim_ppc_spr942_regnum, sim_ppc_spr943_regnum, + sim_ppc_spr944_regnum, sim_ppc_spr945_regnum, + sim_ppc_spr946_regnum, sim_ppc_spr947_regnum, + sim_ppc_spr948_regnum, sim_ppc_spr949_regnum, + sim_ppc_spr950_regnum, sim_ppc_spr951_regnum, + sim_ppc_spr952_regnum, sim_ppc_spr953_regnum, + sim_ppc_spr954_regnum, sim_ppc_spr955_regnum, + sim_ppc_spr956_regnum, sim_ppc_spr957_regnum, + sim_ppc_spr958_regnum, sim_ppc_spr959_regnum, + sim_ppc_spr960_regnum, sim_ppc_spr961_regnum, + sim_ppc_spr962_regnum, sim_ppc_spr963_regnum, + sim_ppc_spr964_regnum, sim_ppc_spr965_regnum, + sim_ppc_spr966_regnum, sim_ppc_spr967_regnum, + sim_ppc_spr968_regnum, sim_ppc_spr969_regnum, + sim_ppc_spr970_regnum, sim_ppc_spr971_regnum, + sim_ppc_spr972_regnum, sim_ppc_spr973_regnum, + sim_ppc_spr974_regnum, sim_ppc_spr975_regnum, + sim_ppc_spr976_regnum, sim_ppc_spr977_regnum, + sim_ppc_spr978_regnum, sim_ppc_spr979_regnum, + sim_ppc_spr980_regnum, sim_ppc_spr981_regnum, + sim_ppc_spr982_regnum, sim_ppc_spr983_regnum, + sim_ppc_spr984_regnum, sim_ppc_spr985_regnum, + sim_ppc_spr986_regnum, sim_ppc_spr987_regnum, + sim_ppc_spr988_regnum, sim_ppc_spr989_regnum, + sim_ppc_spr990_regnum, sim_ppc_spr991_regnum, + sim_ppc_spr992_regnum, sim_ppc_spr993_regnum, + sim_ppc_spr994_regnum, sim_ppc_spr995_regnum, + sim_ppc_spr996_regnum, sim_ppc_spr997_regnum, + sim_ppc_spr998_regnum, sim_ppc_spr999_regnum, + sim_ppc_spr1000_regnum, sim_ppc_spr1001_regnum, + sim_ppc_spr1002_regnum, sim_ppc_spr1003_regnum, + sim_ppc_spr1004_regnum, sim_ppc_spr1005_regnum, + sim_ppc_spr1006_regnum, sim_ppc_spr1007_regnum, + sim_ppc_spr1008_regnum, sim_ppc_spr1009_regnum, + sim_ppc_spr1010_regnum, sim_ppc_spr1011_regnum, + sim_ppc_spr1012_regnum, sim_ppc_spr1013_regnum, + sim_ppc_spr1014_regnum, sim_ppc_spr1015_regnum, + sim_ppc_spr1016_regnum, sim_ppc_spr1017_regnum, + sim_ppc_spr1018_regnum, sim_ppc_spr1019_regnum, + sim_ppc_spr1020_regnum, sim_ppc_spr1021_regnum, + sim_ppc_spr1022_regnum, sim_ppc_spr1023_regnum + }; + + +/* Sizes of various register sets. */ +enum + { + sim_ppc_num_gprs = 32, + sim_ppc_num_fprs = 32, + sim_ppc_num_vrs = 32, + sim_ppc_num_srs = 16, + sim_ppc_num_sprs = 1024, + }; + + +/* Return the register name for the supplied SPR number if any, or + NULL if none. */ +extern const char *sim_spr_register_name (int); + +#ifdef __cplusplus +} +#endif + +#endif /* SIM_PPC_H */ diff --git a/external/gpl3/gdb/dist/include/gdb/sim-rx.h b/external/gpl3/gdb/dist/include/gdb/sim-rx.h new file mode 100644 index 000000000000..ac3ffe96db5e --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-rx.h @@ -0,0 +1,56 @@ +/* sim-rx.h --- interface between RX simulator and GDB. + + Copyright 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_RX_H) +#define SIM_RX_H + +enum sim_rx_regnum + { + sim_rx_r0_regnum, + sim_rx_r1_regnum, + sim_rx_r2_regnum, + sim_rx_r3_regnum, + sim_rx_r4_regnum, + sim_rx_r5_regnum, + sim_rx_r6_regnum, + sim_rx_r7_regnum, + sim_rx_r8_regnum, + sim_rx_r9_regnum, + sim_rx_r10_regnum, + sim_rx_r11_regnum, + sim_rx_r12_regnum, + sim_rx_r13_regnum, + sim_rx_r14_regnum, + sim_rx_r15_regnum, + sim_rx_usp_regnum, + sim_rx_isp_regnum, + sim_rx_ps_regnum, + sim_rx_pc_regnum, + sim_rx_intb_regnum, + sim_rx_bpsw_regnum, + sim_rx_bpc_regnum, + sim_rx_fintv_regnum, + sim_rx_fpsw_regnum, + sim_rx_acc_regnum, + sim_rx_num_regs + }; + +#endif /* SIM_RX_H */ diff --git a/external/gpl3/gdb/dist/include/gdb/sim-sh.h b/external/gpl3/gdb/dist/include/gdb/sim-sh.h new file mode 100644 index 000000000000..6c08d2d231b8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdb/sim-sh.h @@ -0,0 +1,170 @@ +/* This file defines the interface between the sh simulator and gdb. + Copyright (C) 2000, 2002, 2004, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#if !defined (SIM_SH_H) +#define SIM_SH_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* The simulator makes use of the following register information. */ + +enum +{ + SIM_SH_R0_REGNUM = 0, + SIM_SH_R1_REGNUM, + SIM_SH_R2_REGNUM, + SIM_SH_R3_REGNUM, + SIM_SH_R4_REGNUM, + SIM_SH_R5_REGNUM, + SIM_SH_R6_REGNUM, + SIM_SH_R7_REGNUM, + SIM_SH_R8_REGNUM, + SIM_SH_R9_REGNUM, + SIM_SH_R10_REGNUM, + SIM_SH_R11_REGNUM, + SIM_SH_R12_REGNUM, + SIM_SH_R13_REGNUM, + SIM_SH_R14_REGNUM, + SIM_SH_R15_REGNUM, + SIM_SH_PC_REGNUM, + SIM_SH_PR_REGNUM, + SIM_SH_GBR_REGNUM, + SIM_SH_VBR_REGNUM, + SIM_SH_MACH_REGNUM, + SIM_SH_MACL_REGNUM, + SIM_SH_SR_REGNUM, + SIM_SH_FPUL_REGNUM, + SIM_SH_FPSCR_REGNUM, + SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ + SIM_SH_FR1_REGNUM, + SIM_SH_FR2_REGNUM, + SIM_SH_FR3_REGNUM, + SIM_SH_FR4_REGNUM, + SIM_SH_FR5_REGNUM, + SIM_SH_FR6_REGNUM, + SIM_SH_FR7_REGNUM, + SIM_SH_FR8_REGNUM, + SIM_SH_FR9_REGNUM, + SIM_SH_FR10_REGNUM, + SIM_SH_FR11_REGNUM, + SIM_SH_FR12_REGNUM, + SIM_SH_FR13_REGNUM, + SIM_SH_FR14_REGNUM, + SIM_SH_FR15_REGNUM, + SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ + SIM_SH_R1_BANK0_REGNUM, + SIM_SH_R2_BANK0_REGNUM, + SIM_SH_R3_BANK0_REGNUM, + SIM_SH_R4_BANK0_REGNUM, + SIM_SH_R5_BANK0_REGNUM, + SIM_SH_R6_BANK0_REGNUM, + SIM_SH_R7_BANK0_REGNUM, + SIM_SH_R0_BANK1_REGNUM, + SIM_SH_R1_BANK1_REGNUM, + SIM_SH_R2_BANK1_REGNUM, + SIM_SH_R3_BANK1_REGNUM, + SIM_SH_R4_BANK1_REGNUM, + SIM_SH_R5_BANK1_REGNUM, + SIM_SH_R6_BANK1_REGNUM, + SIM_SH_R7_BANK1_REGNUM, + SIM_SH_XF0_REGNUM, + SIM_SH_XF1_REGNUM, + SIM_SH_XF2_REGNUM, + SIM_SH_XF3_REGNUM, + SIM_SH_XF4_REGNUM, + SIM_SH_XF5_REGNUM, + SIM_SH_XF6_REGNUM, + SIM_SH_XF7_REGNUM, + SIM_SH_XF8_REGNUM, + SIM_SH_XF9_REGNUM, + SIM_SH_XF10_REGNUM, + SIM_SH_XF11_REGNUM, + SIM_SH_XF12_REGNUM, + SIM_SH_XF13_REGNUM, + SIM_SH_XF14_REGNUM, + SIM_SH_XF15_REGNUM, + SIM_SH_SGR_REGNUM, + SIM_SH_DBR_REGNUM, + SIM_SH4_NUM_REGS, /* 77 */ + + /* sh[3]-dsp */ + SIM_SH_DSR_REGNUM, + SIM_SH_A0G_REGNUM, + SIM_SH_A0_REGNUM, + SIM_SH_A1G_REGNUM, + SIM_SH_A1_REGNUM, + SIM_SH_M0_REGNUM, + SIM_SH_M1_REGNUM, + SIM_SH_X0_REGNUM, + SIM_SH_X1_REGNUM, + SIM_SH_Y0_REGNUM, + SIM_SH_Y1_REGNUM, + SIM_SH_MOD_REGNUM, + SIM_SH_RS_REGNUM, + SIM_SH_RE_REGNUM, + SIM_SH_R0_BANK_REGNUM, + SIM_SH_R1_BANK_REGNUM, + SIM_SH_R2_BANK_REGNUM, + SIM_SH_R3_BANK_REGNUM, + SIM_SH_R4_BANK_REGNUM, + SIM_SH_R5_BANK_REGNUM, + SIM_SH_R6_BANK_REGNUM, + SIM_SH_R7_BANK_REGNUM, + /* 109..127: room for expansion. */ + SIM_SH_TBR_REGNUM, + SIM_SH_IBNR_REGNUM, + SIM_SH_IBCR_REGNUM, + SIM_SH_BANK_REGNUM, + SIM_SH_BANK_MACL_REGNUM, + SIM_SH_BANK_GBR_REGNUM, + SIM_SH_BANK_PR_REGNUM, + SIM_SH_BANK_IVN_REGNUM, + SIM_SH_BANK_MACH_REGNUM +}; + +enum +{ + SIM_SH64_R0_REGNUM = 0, + SIM_SH64_SP_REGNUM = 15, + SIM_SH64_PC_REGNUM = 64, + SIM_SH64_SR_REGNUM = 65, + SIM_SH64_SSR_REGNUM = 66, + SIM_SH64_SPC_REGNUM = 67, + SIM_SH64_TR0_REGNUM = 68, + SIM_SH64_FPCSR_REGNUM = 76, + SIM_SH64_FR0_REGNUM = 77 +}; + +enum +{ + SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ + SIM_SH64_NR_R_REGS = 64, /* number of general registers */ + SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ + SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/gdbm.h b/external/gpl3/gdb/dist/include/gdbm.h new file mode 100644 index 000000000000..d2a600639347 --- /dev/null +++ b/external/gpl3/gdb/dist/include/gdbm.h @@ -0,0 +1,91 @@ +/* GNU DBM - DataBase Manager include file + Copyright 1989, 1991 Free Software Foundation, Inc. + Written by Philip A. Nelson. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* You may contact the author by: + e-mail: phil@wwu.edu + us-mail: Philip A. Nelson + Computer Science Department + Western Washington University + Bellingham, WA 98226 + phone: (206) 676-3035 + +*************************************************************************/ + +/* Parameters to gdbm_open for READERS, WRITERS, and WRITERS who + can create the database. */ +#define GDBM_READER 0 +#define GDBM_WRITER 1 +#define GDBM_WRCREAT 2 +#define GDBM_NEWDB 3 + +/* Parameters to gdbm_store for simple insertion or replacement. */ +#define GDBM_INSERT 0 +#define GDBM_REPLACE 1 + + +/* The data and key structure. This structure is defined for compatibility. */ +typedef struct { + char *dptr; + int dsize; + } datum; + + +/* The file information header. This is good enough for most applications. */ +typedef struct {int dummy[10];} *GDBM_FILE; + + +/* These are the routines! */ + +extern GDBM_FILE gdbm_open (); + +extern void gdbm_close (); + +extern datum gdbm_fetch (); + +extern int gdbm_store (); + +extern int gdbm_delete (); + +extern datum gdbm_firstkey (); + +extern datum gdbm_nextkey (); + +extern int gdbm_reorganize (); + + +/* gdbm sends back the following error codes in the variable gdbm_errno. */ +typedef enum { NO_ERROR, + MALLOC_ERROR, + BLOCK_SIZE_ERROR, + FILE_OPEN_ERROR, + FILE_WRITE_ERROR, + FILE_SEEK_ERROR, + FILE_READ_ERROR, + BAD_MAGIC_NUMBER, + EMPTY_DATABASE, + CANT_BE_READER, + CANT_BE_WRITER, + READER_CANT_RECOVER, + READER_CANT_DELETE, + READER_CANT_STORE, + READER_CANT_REORGANIZE, + UNKNOWN_UPDATE, + ITEM_NOT_FOUND, + REORGANIZE_FAILED, + CANNOT_REPLACE} + gdbm_error; diff --git a/external/gpl3/gdb/dist/include/getopt.h b/external/gpl3/gdb/dist/include/getopt.h new file mode 100644 index 000000000000..5421cabed822 --- /dev/null +++ b/external/gpl3/gdb/dist/include/getopt.h @@ -0,0 +1,144 @@ +/* Declarations for getopt. + Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, + 2002 Free Software Foundation, Inc. + + NOTE: The canonical source of this file is maintained with the GNU C Library. + Bugs can be reported to bug-glibc@gnu.org. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +#ifndef _GETOPT_H +#define _GETOPT_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +extern char *optarg; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns -1, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +extern int optind; + +/* Callers store zero here to inhibit the error message `getopt' prints + for unrecognized options. */ + +extern int opterr; + +/* Set to an option character which was unrecognized. */ + +extern int optopt; + +/* Describe the long-named options requested by the application. + The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector + of `struct option' terminated by an element containing a name which is + zero. + + The field `has_arg' is: + no_argument (or 0) if the option does not take an argument, + required_argument (or 1) if the option requires an argument, + optional_argument (or 2) if the option takes an optional argument. + + If the field `flag' is not NULL, it points to a variable that is set + to the value given in the field `val' when the option is found, but + left unchanged if the option is not found. + + To have a long-named option do something other than set an `int' to + a compiled-in constant, such as set a value from `optarg', set the + option's `flag' field to zero and its `val' field to a nonzero + value (the equivalent single-letter option character, if there is + one). For long options that have a zero `flag' field, `getopt' + returns the contents of the `val' field. */ + +struct option +{ +#if defined (__STDC__) && __STDC__ + const char *name; +#else + char *name; +#endif + /* has_arg can't be an enum because some compilers complain about + type mismatches in all the code that assumes it is an int. */ + int has_arg; + int *flag; + int val; +}; + +/* Names for the values of the `has_arg' field of `struct option'. */ + +#define no_argument 0 +#define required_argument 1 +#define optional_argument 2 + +#if defined (__STDC__) && __STDC__ +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if !HAVE_DECL_GETOPT +#if defined (__GNU_LIBRARY__) || defined (HAVE_DECL_GETOPT) +/* Many other libraries have conflicting prototypes for getopt, with + differences in the consts, in unistd.h. To avoid compilation + errors, only prototype getopt for the GNU C library. */ +extern int getopt (int argc, char *const *argv, const char *shortopts); +#else +#ifndef __cplusplus +extern int getopt (); +#endif /* __cplusplus */ +#endif +#endif /* !HAVE_DECL_GETOPT */ + +extern int getopt_long (int argc, char *const *argv, const char *shortopts, + const struct option *longopts, int *longind); +extern int getopt_long_only (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind); + +/* Internal only. Users should not call this directly. */ +extern int _getopt_internal (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind, + int long_only); +#else /* not __STDC__ */ +extern int getopt (); +extern int getopt_long (); +extern int getopt_long_only (); + +extern int _getopt_internal (); +#endif /* __STDC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* getopt.h */ diff --git a/external/gpl3/gdb/dist/include/hashtab.h b/external/gpl3/gdb/dist/include/hashtab.h new file mode 100644 index 000000000000..4bb65d6c7a2b --- /dev/null +++ b/external/gpl3/gdb/dist/include/hashtab.h @@ -0,0 +1,209 @@ +/* An expandable hash tables datatype. + Copyright (C) 1999, 2000, 2002, 2003, 2004, 2005, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Vladimir Makarov (vmakarov@cygnus.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* This package implements basic hash table functionality. It is possible + to search for an entry, create an entry and destroy an entry. + + Elements in the table are generic pointers. + + The size of the table is not fixed; if the occupancy of the table + grows too high the hash table will be expanded. + + The abstract data implementation is based on generalized Algorithm D + from Knuth's book "The art of computer programming". Hash table is + expanded by creation of new hash table and transferring elements from + the old table to the new table. */ + +#ifndef __HASHTAB_H__ +#define __HASHTAB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +#ifndef GTY +#define GTY(X) +#endif + +/* The type for a hash code. */ +typedef unsigned int hashval_t; + +/* Callback function pointer types. */ + +/* Calculate hash of a table entry. */ +typedef hashval_t (*htab_hash) (const void *); + +/* Compare a table entry with a possible entry. The entry already in + the table always comes first, so the second element can be of a + different type (but in this case htab_find and htab_find_slot + cannot be used; instead the variants that accept a hash value + must be used). */ +typedef int (*htab_eq) (const void *, const void *); + +/* Cleanup function called whenever a live element is removed from + the hash table. */ +typedef void (*htab_del) (void *); + +/* Function called by htab_traverse for each live element. The first + arg is the slot of the element (which can be passed to htab_clear_slot + if desired), the second arg is the auxiliary pointer handed to + htab_traverse. Return 1 to continue scan, 0 to stop. */ +typedef int (*htab_trav) (void **, void *); + +/* Memory-allocation function, with the same functionality as calloc(). + Iff it returns NULL, the hash table implementation will pass an error + code back to the user, so if your code doesn't handle errors, + best if you use xcalloc instead. */ +typedef void *(*htab_alloc) (size_t, size_t); + +/* We also need a free() routine. */ +typedef void (*htab_free) (void *); + +/* Memory allocation and deallocation; variants which take an extra + argument. */ +typedef void *(*htab_alloc_with_arg) (void *, size_t, size_t); +typedef void (*htab_free_with_arg) (void *, void *); + +/* This macro defines reserved value for empty table entry. */ + +#define HTAB_EMPTY_ENTRY ((PTR) 0) + +/* This macro defines reserved value for table entry which contained + a deleted element. */ + +#define HTAB_DELETED_ENTRY ((PTR) 1) + +/* Hash tables are of the following type. The structure + (implementation) of this type is not needed for using the hash + tables. All work with hash table should be executed only through + functions mentioned below. The size of this structure is subject to + change. */ + +struct GTY(()) htab { + /* Pointer to hash function. */ + htab_hash hash_f; + + /* Pointer to comparison function. */ + htab_eq eq_f; + + /* Pointer to cleanup function. */ + htab_del del_f; + + /* Table itself. */ + void ** GTY ((use_param, length ("%h.size"))) entries; + + /* Current size (in entries) of the hash table. */ + size_t size; + + /* Current number of elements including also deleted elements. */ + size_t n_elements; + + /* Current number of deleted elements in the table. */ + size_t n_deleted; + + /* The following member is used for debugging. Its value is number + of all calls of `htab_find_slot' for the hash table. */ + unsigned int searches; + + /* The following member is used for debugging. Its value is number + of collisions fixed for time of work with the hash table. */ + unsigned int collisions; + + /* Pointers to allocate/free functions. */ + htab_alloc alloc_f; + htab_free free_f; + + /* Alternate allocate/free functions, which take an extra argument. */ + void * GTY((skip)) alloc_arg; + htab_alloc_with_arg alloc_with_arg_f; + htab_free_with_arg free_with_arg_f; + + /* Current size (in entries) of the hash table, as an index into the + table of primes. */ + unsigned int size_prime_index; +}; + +typedef struct htab *htab_t; + +/* An enum saying whether we insert into the hash table or not. */ +enum insert_option {NO_INSERT, INSERT}; + +/* The prototypes of the package functions. */ + +extern htab_t htab_create_alloc (size_t, htab_hash, + htab_eq, htab_del, + htab_alloc, htab_free); + +extern htab_t htab_create_alloc_ex (size_t, htab_hash, + htab_eq, htab_del, + void *, htab_alloc_with_arg, + htab_free_with_arg); + +extern htab_t htab_create_typed_alloc (size_t, htab_hash, htab_eq, htab_del, + htab_alloc, htab_alloc, htab_free); + +/* Backward-compatibility functions. */ +extern htab_t htab_create (size_t, htab_hash, htab_eq, htab_del); +extern htab_t htab_try_create (size_t, htab_hash, htab_eq, htab_del); + +extern void htab_set_functions_ex (htab_t, htab_hash, + htab_eq, htab_del, + void *, htab_alloc_with_arg, + htab_free_with_arg); + +extern void htab_delete (htab_t); +extern void htab_empty (htab_t); + +extern void * htab_find (htab_t, const void *); +extern void ** htab_find_slot (htab_t, const void *, enum insert_option); +extern void * htab_find_with_hash (htab_t, const void *, hashval_t); +extern void ** htab_find_slot_with_hash (htab_t, const void *, + hashval_t, enum insert_option); +extern void htab_clear_slot (htab_t, void **); +extern void htab_remove_elt (htab_t, void *); +extern void htab_remove_elt_with_hash (htab_t, void *, hashval_t); + +extern void htab_traverse (htab_t, htab_trav, void *); +extern void htab_traverse_noresize (htab_t, htab_trav, void *); + +extern size_t htab_size (htab_t); +extern size_t htab_elements (htab_t); +extern double htab_collisions (htab_t); + +/* A hash function for pointers. */ +extern htab_hash htab_hash_pointer; + +/* An equality function for pointers. */ +extern htab_eq htab_eq_pointer; + +/* A hash function for null-terminated strings. */ +extern hashval_t htab_hash_string (const void *); + +/* An iterative hash function for arbitrary data. */ +extern hashval_t iterative_hash (const void *, size_t, hashval_t); +/* Shorthand for hashing something with an intrinsic size. */ +#define iterative_hash_object(OB,INIT) iterative_hash (&OB, sizeof (OB), INIT) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __HASHTAB_H */ diff --git a/external/gpl3/gdb/dist/include/hp-symtab.h b/external/gpl3/gdb/dist/include/hp-symtab.h new file mode 100644 index 000000000000..e944e9091620 --- /dev/null +++ b/external/gpl3/gdb/dist/include/hp-symtab.h @@ -0,0 +1,1867 @@ +/* Definitions and structures for reading debug symbols from the + native HP C compiler. + + Written by the Center for Software Science at the University of Utah + and by Cygnus Support. + + Copyright 1994, 1995, 1998, 1999, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef HP_SYMTAB_INCLUDED +#define HP_SYMTAB_INCLUDED + +/* General information: + + This header file defines and describes only the data structures + necessary to read debug symbols produced by the HP C compiler, + HP ANSI C++ compiler, and HP FORTRAN 90 compiler using the + SOM object file format. + (For a full description of the debug format, ftp hpux-symtab.h from + jaguar.cs.utah.edu:/dist). + + Additional notes (Rich Title) + This file is a reverse-engineered version of a file called + "symtab.h" which exists internal to HP's Computer Languages Organization + in /CLO/Components/DDE/obj/som/symtab.h. Because HP's version of + the file is copyrighted and not distributed, it is necessary for + GDB to use the reverse-engineered version that follows. + Work was done by Cygnus to reverse-engineer the C subset of symtab.h. + The WDB project has extended this to also contain the C++ + symbol definitions, the F90 symbol definitions, + and the DOC (debugging-optimized-code) symbol definitions. + In some cases (the C++ symbol definitions) + I have added internal documentation here that + goes beyond what is supplied in HP's symtab.h. If we someday + unify these files again, the extra comments should be merged back + into HP's symtab.h. + + ------------------------------------------------------------------- + + Debug symbols are contained entirely within an unloadable space called + $DEBUG$. $DEBUG$ contains several subspaces which group related + debug symbols. + + $GNTT$ contains information for global variables, types and contants. + + $LNTT$ contains information for procedures (including nesting), scoping + information, local variables, types, and constants. + + $SLT$ contains source line information so that code addresses may be + mapped to source lines. + + $VT$ contains various strings and constants for named objects (variables, + typedefs, functions, etc). Strings are stored as null-terminated character + lists. Constants always begin on word boundaries. The first byte of + the VT must be zero (a null string). + + $XT$ is not currently used by GDB. + + Many structures within the subspaces point to other structures within + the same subspace, or to structures within a different subspace. These + pointers are represented as a structure index from the beginning of + the appropriate subspace. */ + +/* Used to describe where a constant is stored. */ +enum location_type +{ + LOCATION_IMMEDIATE, + LOCATION_PTR, + LOCATION_VT, +}; + +/* Languages supported by this debug format. Within the data structures + this type is limited to 4 bits for a maximum of 16 languages. */ +enum hp_language +{ + HP_LANGUAGE_UNKNOWN, + HP_LANGUAGE_C, + HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_F77 = HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_PASCAL, + HP_LANGUAGE_MODCAL, + HP_LANGUAGE_COBOL, + HP_LANGUAGE_BASIC, + HP_LANGUAGE_ADA, + HP_LANGUAGE_CPLUSPLUS, + HP_LANGUAGE_DMPASCAL +}; + + +/* Basic data types available in this debug format. Within the data + structures this type is limited to 5 bits for a maximum of 32 basic + data types. */ +enum hp_type +{ + HP_TYPE_UNDEFINED, /* 0 */ + HP_TYPE_BOOLEAN, /* 1 */ + HP_TYPE_CHAR, /* 2 */ + HP_TYPE_INT, /* 3 */ + HP_TYPE_UNSIGNED_INT, /* 4 */ + HP_TYPE_REAL, /* 5 */ + HP_TYPE_COMPLEX, /* 6 */ + HP_TYPE_STRING200, /* 7 */ + HP_TYPE_LONGSTRING200, /* 8 */ + HP_TYPE_TEXT, /* 9 */ + HP_TYPE_FLABEL, /* 10 */ + HP_TYPE_FTN_STRING_SPEC, /* 11 */ + HP_TYPE_MOD_STRING_SPEC, /* 12 */ + HP_TYPE_PACKED_DECIMAL, /* 13 */ + HP_TYPE_REAL_3000, /* 14 */ + HP_TYPE_MOD_STRING_3000, /* 15 */ + HP_TYPE_ANYPOINTER, /* 16 */ + HP_TYPE_GLOBAL_ANYPOINTER, /* 17 */ + HP_TYPE_LOCAL_ANYPOINTER, /* 18 */ + HP_TYPE_COMPLEXS3000, /* 19 */ + HP_TYPE_FTN_STRING_S300_COMPAT, /* 20 */ + HP_TYPE_FTN_STRING_VAX_COMPAT, /* 21 */ + HP_TYPE_BOOLEAN_S300_COMPAT, /* 22 */ + HP_TYPE_BOOLEAN_VAX_COMPAT, /* 23 */ + HP_TYPE_WIDE_CHAR, /* 24 */ + HP_TYPE_LONG, /* 25 */ + HP_TYPE_UNSIGNED_LONG, /* 26 */ + HP_TYPE_DOUBLE, /* 27 */ + HP_TYPE_TEMPLATE_ARG, /* 28 */ + HP_TYPE_VOID /* 29 */ +}; + +/* An immediate name and type table entry. + + extension and immediate will always be one. + global will always be zero. + hp_type is the basic type this entry describes. + bitlength is the length in bits for the basic type. */ +struct dnttp_immediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int type: 5; + unsigned int bitlength: 24; +}; + +/* A nonimmediate name and type table entry. + + extension will always be one. + immediate will always be zero. + if global is zero, this entry points into the LNTT + if global is one, this entry points into the GNTT + index is the index within the GNTT or LNTT for this entry. */ +struct dnttp_nonimmediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int index: 29; +}; + +/* A pointer to an entry in the GNTT and LNTT tables. It has two + forms depending on the type being described. + + The immediate form is used for simple entries and is one + word. + + The nonimmediate form is used for complex entries and contains + an index into the LNTT or GNTT which describes the entire type. + + If a dnttpointer is -1, then it is a NIL entry. */ + +#define DNTTNIL (-1) +typedef union dnttpointer +{ + struct dnttp_immediate dntti; + struct dnttp_nonimmediate dnttp; + int word; +} dnttpointer; + +/* An index into the source line table. As with dnttpointers, a sltpointer + of -1 indicates a NIL entry. */ +#define SLTNIL (-1) +typedef int sltpointer; + +/* Index into DOC (= "Debugging Optimized Code") line table. */ +#define LTNIL (-1) +typedef int ltpointer; + +/* Index into context table. */ +#define CTXTNIL (-1) +typedef int ctxtpointer; + +/* Unsigned byte offset into the VT. */ +typedef unsigned int vtpointer; + +/* A DNTT entry (used within the GNTT and LNTT). + + DNTT entries are variable sized objects, but are always a multiple + of 3 words (we call each group of 3 words a "block"). + + The first bit in each block is an extension bit. This bit is zero + for the first block of a DNTT entry. If the entry requires more + than one block, then this bit is set to one in all blocks after + the first one. */ + +/* Each DNTT entry describes a particular debug symbol (beginning of + a source file, a function, variables, structures, etc. + + The type of the DNTT entry is stored in the "kind" field within the + DNTT entry itself. */ + +enum dntt_entry_type +{ + DNTT_TYPE_NIL = -1, + DNTT_TYPE_SRCFILE, + DNTT_TYPE_MODULE, + DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BEGIN, + DNTT_TYPE_END, + DNTT_TYPE_IMPORT, + DNTT_TYPE_LABEL, + DNTT_TYPE_FPARAM, + DNTT_TYPE_SVAR, + DNTT_TYPE_DVAR, + DNTT_TYPE_HOLE1, + DNTT_TYPE_CONST, + DNTT_TYPE_TYPEDEF, + DNTT_TYPE_TAGDEF, + DNTT_TYPE_POINTER, + DNTT_TYPE_ENUM, + DNTT_TYPE_MEMENUM, + DNTT_TYPE_SET, + DNTT_TYPE_SUBRANGE, + DNTT_TYPE_ARRAY, + DNTT_TYPE_STRUCT, + DNTT_TYPE_UNION, + DNTT_TYPE_FIELD, + DNTT_TYPE_VARIANT, + DNTT_TYPE_FILE, + DNTT_TYPE_FUNCTYPE, + DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, + DNTT_TYPE_COBSTRUCT, + DNTT_TYPE_XREF, + DNTT_TYPE_SA, + DNTT_TYPE_MACRO, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_CLASS_SCOPE, + DNTT_TYPE_REFERENCE, + DNTT_TYPE_PTRMEM, + DNTT_TYPE_PTRMEMFUNC, + DNTT_TYPE_CLASS, + DNTT_TYPE_GENFIELD, + DNTT_TYPE_VFUNC, + DNTT_TYPE_MEMACCESS, + DNTT_TYPE_INHERITANCE, + DNTT_TYPE_FRIEND_CLASS, + DNTT_TYPE_FRIEND_FUNC, + DNTT_TYPE_MODIFIER, + DNTT_TYPE_OBJECT_ID, + DNTT_TYPE_MEMFUNC, + DNTT_TYPE_TEMPLATE, + DNTT_TYPE_TEMPLATE_ARG, + DNTT_TYPE_FUNC_TEMPLATE, + DNTT_TYPE_LINK, + DNTT_TYPE_DYN_ARRAY_DESC, + DNTT_TYPE_DESC_SUBRANGE, + DNTT_TYPE_BEGIN_EXT, + DNTT_TYPE_INLN, + DNTT_TYPE_INLN_LIST, + DNTT_TYPE_ALIAS, + DNTT_TYPE_DOC_FUNCTION, + DNTT_TYPE_DOC_MEMFUNC, + DNTT_TYPE_MAX +}; + +/* DNTT_TYPE_SRCFILE: + + One DNTT_TYPE_SRCFILE symbol is output for the start of each source + file and at the begin and end of an included file. A DNTT_TYPE_SRCFILE + entry is also output before each DNTT_TYPE_FUNC symbol so that debuggers + can determine what file a function was defined in. + + LANGUAGE describes the source file's language. + + NAME points to an VT entry providing the source file's name. + + Note the name used for DNTT_TYPE_SRCFILE entries are exactly as seen + by the compiler (ie they may be relative or absolute). C include files + via <> inclusion must use absolute paths. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_srcfile +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_SRCFILE */ + unsigned int language: 4; + unsigned int unused: 17; + vtpointer name; + sltpointer address; +}; + +/* DNTT_TYPE_MODULE: + + A DNTT_TYPE_MODULE symbol is emitted for the start of a pascal + module or C source file. A module indicates a compilation unit + for name-scoping purposes; in that regard there should be + a 1-1 correspondence between GDB "symtab"'s and MODULE symbol records. + + Each DNTT_TYPE_MODULE must have an associated DNTT_TYPE_END symbol. + + NAME points to a VT entry providing the module's name. Note C + source files are considered nameless modules. + + ALIAS point to a VT entry providing a secondary name. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_module +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_MODULE */ + unsigned int unused: 21; + vtpointer name; + vtpointer alias; + dnttpointer unused2; + sltpointer address; +}; + +/* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_MEMFUNC: + + A DNTT_TYPE_FUNCTION symbol is emitted for each function definition; + a DNTT_TYPE_ENTRY symbols is used for secondary entry points. Both + symbols used the dntt_type_function structure. + A DNTT_TYPE_BLOCKDATA symbol is emitted ...? + A DNTT_TYPE_MEMFUNC symbol is emitted for inlined member functions (C++). + + Each of DNTT_TYPE_FUNCTION must have a matching DNTT_TYPE_END. + + GLOBAL is nonzero if the function has global scope. + + LANGUAGE describes the function's source language. + + OPT_LEVEL describes the optimization level the function was compiled + with. + + VARARGS is nonzero if the function uses varargs. + + NAME points to a VT entry providing the function's name. + + ALIAS points to a VT entry providing a secondary name for the function. + + FIRSTPARAM points to a LNTT entry which describes the parameter list. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + ENTRYADDR is the memory address corresponding the function's entry point + + RETVAL points to a LNTT entry describing the function's return value. + + LOWADDR is the lowest memory address associated with this function. + + HIADDR is the highest memory address associated with this function. */ + +struct dntt_type_function +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA + or DNTT_TYPE_MEMFUNC */ + unsigned int global: 1; + unsigned int language: 4; + unsigned int nest_level: 5; + unsigned int opt_level: 2; + unsigned int varargs: 1; + unsigned int lang_info: 4; + unsigned int inlined: 1; + unsigned int localalloc: 1; + unsigned int expansion: 1; + unsigned int unused: 1; + vtpointer name; + vtpointer alias; + dnttpointer firstparam; + sltpointer address; + CORE_ADDR entryaddr; + dnttpointer retval; + CORE_ADDR lowaddr; + CORE_ADDR hiaddr; +}; + +/* DNTT_TYPE_BEGIN: + + A DNTT_TYPE_BEGIN symbol is emitted to begin a new nested scope. + Every DNTT_TYPE_BEGIN symbol must have a matching DNTT_TYPE_END symbol. + + CLASSFLAG is nonzero if this is the beginning of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_begin +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classflag: 1; + unsigned int unused: 20; + sltpointer address; +}; + +/* DNTT_TYPE_END: + + A DNTT_TYPE_END symbol is emitted when closing a scope started by + a DNTT_TYPE_MODULE, DNTT_TYPE_FUNCTION, DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, DNTT_TYPE_BEGIN, and DNTT_TYPE_CLASS_SCOPE symbols. + + ENDKIND describes what type of scope the DNTT_TYPE_END is closing + (one of the above 6 kinds). + + CLASSFLAG is nonzero if this is the end of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + BEGINSCOPE points to the LNTT entry which opened the scope. */ + +struct dntt_type_end +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int endkind: 10; + unsigned int classflag: 1; + unsigned int unused: 10; + sltpointer address; + dnttpointer beginscope; +}; + +/* DNTT_TYPE_IMPORT is unused by GDB. */ +/* DNTT_TYPE_LABEL is unused by GDB. */ + +/* DNTT_TYPE_FPARAM: + + A DNTT_TYPE_FPARAM symbol is emitted for a function argument. When + chained together the symbols represent an argument list for a function. + + REGPARAM is nonzero if this parameter was passed in a register. + + INDIRECT is nonzero if this parameter is a pointer to the parameter + (pass by reference or pass by value for large items). + + LONGADDR is nonzero if the parameter is a 64bit pointer. + + NAME is a pointer into the VT for the parameter's name. + + LOCATION describes where the parameter is stored. Depending on the + parameter type LOCATION could be a register number, or an offset + from the stack pointer. + + TYPE points to a NTT entry describing the type of this parameter. + + NEXTPARAM points to the LNTT entry describing the next parameter. */ + +struct dntt_type_fparam +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int regparam: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int copyparam: 1; + unsigned int dflt: 1; + unsigned int doc_ranges: 1; + unsigned int misc_kind: 1; + unsigned int unused: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + dnttpointer nextparam; + int misc; +}; + +/* DNTT_TYPE_SVAR: + + A DNTT_TYPE_SVAR is emitted to describe a variable in static storage. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + LONGADDR is nonzero if the variable is in long pointer space. + + STATICMEM is nonzero if the variable is a member of a class. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_svar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int staticmem: 1; + unsigned int a_union: 1; + unsigned int unused1: 1; + unsigned int thread_specific: 1; + unsigned int unused2: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_DVAR: + + A DNTT_TYPE_DVAR is emitted to describe automatic variables and variables + held in registers. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + REGVAR is nonzero if the variable is in a register. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address or register number for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_dvar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int regvar: 1; + unsigned int a_union: 1; + unsigned int unused: 17; + vtpointer name; + int location; + dnttpointer type; + unsigned int offset; +}; + +/* DNTT_TYPE_CONST: + + A DNTT_TYPE_CONST symbol is emitted for program constants. + + GLOBAL is nonzero if the constant has global scope. + + INDIRECT is nonzero if the constant is a pointer to an object. + + LOCATION_TYPE describes where to find the constant's value + (in the VT, memory, or embedded in an instruction). + + CLASSMEM is nonzero if the constant is a member of a class. + + NAME is a pointer into the VT for the constant's name. + + LOCATION provides the memory address, register number or pointer + into the VT for the constant's value. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_const +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int location_type: 3; + unsigned int classmem: 1; + unsigned int unused: 15; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_TYPEDEF and DNTT_TYPE_TAGDEF: + + The same structure is used to describe typedefs and tagdefs. + + DNTT_TYPE_TYPEDEFS are associated with C "typedefs". + + DNTT_TYPE_TAGDEFs are associated with C "struct", "union", and "enum" + tags, which may have the same name as a typedef in the same scope. + Also they are associated with C++ "class" tags, which implicitly have + the same name as the class type. + + GLOBAL is nonzero if the typedef/tagdef has global scope. + + TYPEINFO is used to determine if full type information is available + for a tag. (usually 1, but can be zero for opaque types in C). + + NAME is a pointer into the VT for the constant's name. + + TYPE points to the underlying type for the typedef/tagdef in the + GNTT or LNTT. */ + +struct dntt_type_type +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_TYPEDEF or + DNTT_TYPE_TAGDEF. */ + unsigned int global: 1; + unsigned int typeinfo: 1; + unsigned int unused: 19; + vtpointer name; + dnttpointer type; /* Underlying type, which for TAGDEF's may be + DNTT_TYPE_STRUCT, DNTT_TYPE_UNION, + DNTT_TYPE_ENUM, or DNTT_TYPE_CLASS. + For TYPEDEF's other underlying types + are also possible. */ +}; + +/* DNTT_TYPE_POINTER: + + Used to describe a pointer to an underlying type. + + POINTSTO is a pointer into the GNTT or LNTT for the type which this + pointer points to. + + BITLENGTH is the length of the pointer (not the underlying type). */ + +struct dntt_type_pointer +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer pointsto; + unsigned int bitlength; +}; + + +/* DNTT_TYPE_ENUM: + + Used to describe enumerated types. + + FIRSTMEM is a pointer to a DNTT_TYPE_MEMENUM in the GNTT/LNTT which + describes the first member (and contains a pointer to the chain of + members). + + BITLENGTH is the number of bits used to hold the values of the enum's + members. */ + +struct dntt_type_enum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstmem; + unsigned int bitlength; +}; + +/* DNTT_TYPE_MEMENUM + + Used to describe members of an enumerated type. + + CLASSMEM is nonzero if this member is part of a class. + + NAME points into the VT for the name of this member. + + VALUE is the value of this enumeration member. + + NEXTMEM points to the next DNTT_TYPE_MEMENUM in the chain. */ + +struct dntt_type_memenum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classmem: 1; + unsigned int unused: 20; + vtpointer name; + unsigned int value; + dnttpointer nextmem; +}; + +/* DNTT_TYPE_SET + + Used to describe PASCAL "set" type. + + DECLARATION describes the bitpacking of the set. + + SUBTYPE points to a DNTT entry describing the type of the members. + + BITLENGTH is the size of the set. */ + +struct dntt_type_set +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_SUBRANGE + + Used to describe subrange type. + + DYN_LOW describes the lower bound of the subrange: + + 00 for a constant lower bound (found in LOWBOUND). + + 01 for a dynamic lower bound with the lower bound found in the + memory address pointed to by LOWBOUND. + + 10 for a dynamic lower bound described by an variable found in the + DNTT/LNTT (LOWBOUND would be a pointer into the DNTT/LNTT). + + DYN_HIGH is similar to DYN_LOW, except it describes the upper bound. + + SUBTYPE points to the type of the subrange. + + BITLENGTH is the length in bits needed to describe the subrange's + values. */ + +struct dntt_type_subrange +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int unused: 17; + int lowbound; + int highbound; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_ARRAY + + Used to describe an array type. + + DECLARATION describes the bit packing used in the array. + + ARRAYISBYTES is nonzero if the field in arraylength describes the + length in bytes rather than in bits. A value of zero is used to + describe an array with size 2**32. + + ELEMISBYTES is nonzero if the length if each element in the array + is describes in bytes rather than bits. A value of zero is used + to an element with size 2**32. + + ELEMORDER is nonzero if the elements are indexed in increasing order. + + JUSTIFIED if the elements are left justified to index zero. + + ARRAYLENGTH is the length of the array. + + INDEXTYPE is a DNTT pointer to the type used to index the array. + + ELEMTYPE is a DNTT pointer to the type for the array elements. + + ELEMLENGTH is the length of each element in the array (including + any padding). + + Multi-dimensional arrays are represented by ELEMTYPE pointing to + another DNTT_TYPE_ARRAY. */ + +struct dntt_type_array +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int arrayisbytes: 1; + unsigned int elemisbytes: 1; + unsigned int elemorder: 1; + unsigned int justified: 1; + unsigned int unused: 11; + unsigned int arraylength; + dnttpointer indextype; + dnttpointer elemtype; + unsigned int elemlength; +}; + +/* DNTT_TYPE_STRUCT + + DNTT_TYPE_STRUCT is used to describe a C structure. + + DECLARATION describes the bitpacking used. + + FIRSTFIELD is a DNTT pointer to the first field of the structure + (each field contains a pointer to the next field, walk the list + to access all fields of the structure). + + VARTAGFIELD and VARLIST are used for Pascal variant records. + + BITLENGTH is the size of the structure in bits. */ + +struct dntt_type_struct +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer firstfield; + dnttpointer vartagfield; + dnttpointer varlist; + unsigned int bitlength; +}; + +/* DNTT_TYPE_UNION + + DNTT_TYPE_UNION is used to describe a C union. + + FIRSTFIELD is a DNTT pointer to the beginning of the field chain. + + BITLENGTH is the size of the union in bits. */ + +struct dntt_type_union +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstfield; + unsigned int bitlength; +}; + +/* DNTT_TYPE_FIELD + + DNTT_TYPE_FIELD describes one field in a structure or union + or C++ class. + + VISIBILITY is used to describe the visibility of the field + (for c++. public = 0, protected = 1, private = 2). + + A_UNION is nonzero if this field is a member of an anonymous union. + + STATICMEM is nonzero if this field is a static member of a template. + + NAME is a pointer into the VT for the name of the field. + + BITOFFSET gives the offset of this field in bits from the beginning + of the structure or union this field is a member of. + + TYPE is a DNTT pointer to the type describing this field. + + BITLENGTH is the size of the entry in bits. + + NEXTFIELD is a DNTT pointer to the next field in the chain. */ + +struct dntt_type_field +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int visibility: 2; + unsigned int a_union: 1; + unsigned int staticmem: 1; + unsigned int unused: 17; + vtpointer name; + unsigned int bitoffset; + dnttpointer type; + unsigned int bitlength; + dnttpointer nextfield; +}; + +/* DNTT_TYPE_VARIANT is unused by GDB. */ +/* DNTT_TYPE_FILE is unused by GDB. */ + +/* DNTT_TYPE_FUNCTYPE + + I think this is used to describe a function type (e.g., would + be emitted as part of a function-pointer description). + + VARARGS is nonzero if this function uses varargs. + + FIRSTPARAM is a DNTT pointer to the first entry in the parameter + chain. + + RETVAL is a DNTT pointer to the type of the return value. */ + +struct dntt_type_functype +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int varargs: 1; + unsigned int info: 4; + unsigned int unused: 16; + unsigned int bitlength; + dnttpointer firstparam; + dnttpointer retval; +}; + +/* DNTT_TYPE_WITH is emitted by C++ to indicate "with" scoping semantics. + (Probably also emitted by PASCAL to support "with"...). + + C++ example: Say "memfunc" is a method of class "c", and say + "m" is a data member of class "c". Then from within "memfunc", + it is legal to reference "m" directly (e.g. you don't have to + say "this->m". The symbol table indicates + this by emitting a DNTT_TYPE_WITH symbol within the function "memfunc", + pointing to the type symbol for class "c". + + In GDB, this symbol record is unnecessary, + because GDB's symbol lookup algorithm + infers the "with" semantics when it sees a "this" argument to the member + function. So GDB can safely ignore the DNTT_TYPE_WITH record. + + A DNTT_TYPE_WITH has a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_with +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_WITH */ + unsigned int addrtype: 2; /* 0 => STATTYPE */ + /* 1 => DYNTYPE */ + /* 2 => REGTYPE */ + unsigned int indirect: 1; /* 1 => pointer to object */ + unsigned int longaddr: 1; /* 1 => in long pointer space */ + unsigned int nestlevel: 6; /* # of nesting levels back */ + unsigned int doc_ranges: 1; /* 1 => location is range list */ + unsigned int unused: 10; + long location; /* where stored (allocated) */ + sltpointer address; + dnttpointer type; /* type of with expression */ + vtpointer name; /* name of with expression */ + unsigned long offset; /* byte offset from location */ +}; + +/* DNTT_TYPE_COMMON is unsupported by GDB. */ +/* A DNTT_TYPE_COMMON symbol must have a matching DNTT_TYPE_END symbol */ + +/* DNTT_TYPE_COBSTRUCT is unsupported by GDB. */ +/* DNTT_TYPE_XREF is unsupported by GDB. */ +/* DNTT_TYPE_SA is unsupported by GDB. */ +/* DNTT_TYPE_MACRO is unsupported by GDB */ + +/* DNTT_TYPE_BLOCKDATA has the same structure as DNTT_TYPE_FUNCTION */ + +/* The following are the C++ specific SOM records */ + +/* The purpose of the DNTT_TYPE_CLASS_SCOPE is to bracket C++ methods + and indicate the method name belongs in the "class scope" rather + than in the module they are being defined in. For example: + + class c { + ... + void memfunc(); // member function + }; + + void c::memfunc() // definition of class c's "memfunc" + { + ... + } + + main() + { + ... + } + + In the above, the name "memfunc" is not directly visible from "main". + I.e., you have to say "break c::memfunc". + If it were a normal function (not a method), it would be visible + via the simple "break memfunc". Since "memfunc" otherwise looks + like a normal FUNCTION in the symbol table, the bracketing + CLASS_SCOPE is what is used to indicate it is really a method. + + + A DNTT_TYPE_CLASS_SCOPE symbol must have a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_class_scope +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS_SCOPE. */ + unsigned int unused: 21; + sltpointer address ; /* Pointer to SLT entry. */ + dnttpointer type ; /* Pointer to class type DNTT. */ +}; + +/* C++ reference parameter. + The structure of this record is the same as DNTT_TYPE_POINTER - + refer to struct dntt_type_pointer. */ + +/* The next two describe C++ pointer-to-data-member type, and + pointer-to-member-function type, respectively. + DNTT_TYPE_PTRMEM and DNTT_TYPE_PTRMEMFUNC have the same structure. */ + +struct dntt_type_ptrmem +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEM. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +struct dntt_type_ptrmemfunc +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEMFUNC. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +/* The DNTT_TYPE_CLASS symbol is emitted to describe a class type. + "memberlist" points to a chained list of FIELD or GENFIELD records + indicating the class members. "parentlist" points to a chained list + of INHERITANCE records indicating classes from which we inherit + fields. */ + +struct dntt_type_class +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS. */ + unsigned int abstract: 1; /* Is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct. */ + unsigned int expansion: 1; /* 1=template expansion. */ + unsigned int unused: 17; + dnttpointer memberlist ; /* Ptr to chain of [GEN]FIELDs. */ + unsigned long vtbl_loc ; /* Offset in obj of ptr to vtbl. */ + dnttpointer parentlist ; /* Ptr to K_INHERITANCE list. */ + unsigned long bitlength ; /* Total at this level. */ + dnttpointer identlist ; /* Ptr to chain of class ident's. */ + dnttpointer friendlist ; /* Ptr to K_FRIEND list. */ + dnttpointer templateptr ; /* Ptr to template. */ + dnttpointer nextexp ; /* Ptr to next expansion. */ +}; + +/* Class members are indicated via either the FIELD record (for + data members, same as for C struct fields), or by the GENFIELD record + (for member functions). */ + +struct dntt_type_genfield +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_GENFIELD. */ + unsigned int visibility: 2; /* Pub = 0, prot = 1, priv = 2. */ + unsigned int a_union: 1; /* 1 => anonymous union member. */ + unsigned int unused: 18; + dnttpointer field ; /* Pointer to field or qualifier. */ + dnttpointer nextfield ; /* Pointer to next field. */ +}; + +/* C++ virtual functions. */ + +struct dntt_type_vfunc +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_VFUNC */ + unsigned int pure: 1; /* pure virtual function ? */ + unsigned int unused: 20; + dnttpointer funcptr ; /* points to FUNCTION symbol */ + unsigned long vtbl_offset ; /* offset into vtbl for virtual */ +}; + +/* Not precisely sure what this is intended for - DDE ignores it. */ + +struct dntt_type_memaccess +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MEMACCESS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to base class */ + dnttpointer field ; /* pointer field */ +}; + +/* The DNTT_TYPE_INHERITANCE record describes derived classes. + In particular, the "parentlist" field of the CLASS record points + to a list of INHERITANCE records for classes from which we + inherit members. */ + +struct dntt_type_inheritance +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_INHERITANCE */ + unsigned int Virtual: 1; /* virtual base class ? */ + unsigned int visibility: 2; /* pub = 0, prot = 1, priv = 2 */ + unsigned int unused: 18; + dnttpointer classname ; /* first parent class, if any */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_INHERITANCE */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* C++ "friend" classes ... */ + +struct dntt_type_friend_class +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_CLASS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ +}; + +struct dntt_type_friend_func +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_FUNC */ + unsigned int unused: 21; + dnttpointer funcptr ; /* pointer to function */ + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* DDE appears to ignore the DNTT_TYPE_MODIFIER record. + It could perhaps be used to give better "ptype" output in GDB; + otherwise it is probably safe for GDB to ignore it also. */ + +struct dntt_type_modifier +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MODIFIER */ + unsigned int m_const: 1; /* const */ + unsigned int m_static: 1; /* static */ + unsigned int m_void: 1; /* void */ + unsigned int m_volatile: 1; /* volatile */ + unsigned int m_duplicate: 1; /* duplicate */ + unsigned int unused: 16; + dnttpointer type ; /* subtype */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* I'm not sure what this was intended for - DDE ignores it. */ + +struct dntt_type_object_id +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_OBJECT_ID */ + unsigned int indirect: 1; /* Is object_ident addr of addr? */ + unsigned int unused: 20; + unsigned long object_ident ; /* object identifier */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_OBJECT_ID */ + unsigned long segoffset ; /* for linker fixup */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* No separate dntt_type_memfunc; same as dntt_type_func */ + +/* Symbol records to support templates. These only get used + in DDE's "describe" output (like GDB's "ptype"). */ + +/* The TEMPLATE record is the header for a template-class. + Like the CLASS record, a TEMPLATE record has a memberlist that + points to a list of template members. It also has an arglist + pointing to a list of TEMPLATE_ARG records. */ + +struct dntt_type_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPLATE */ + unsigned int abstract: 1; /* is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct */ + unsigned int unused: 18; + dnttpointer memberlist ; /* ptr to chain of K_[GEN]FIELDs */ + long unused2 ; /* offset in obj of ptr to vtbl */ + dnttpointer parentlist ; /* ptr to K_INHERITANCE list */ + unsigned long bitlength ; /* total at this level */ + dnttpointer identlist ; /* ptr to chain of class ident's */ + dnttpointer friendlist ; /* ptr to K_FRIEND list */ + dnttpointer arglist ; /* ptr to argument list */ + dnttpointer expansions ; /* ptr to expansion list */ +}; + +/* Template-class arguments are a list of TEMPL_ARG records + chained together. The "name" field is the name of the formal. + E.g.: + + template class q { ... }; + + Then "T" is the name of the formal argument. */ + +struct dntt_type_templ_arg +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPL_ARG */ + unsigned int usagetype: 1; /* 0 type-name 1 expression */ + unsigned int unused: 20; + vtpointer name ; /* name of argument */ + dnttpointer type ; /* for non type arguments */ + dnttpointer nextarg ; /* Next argument if any */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* FUNC_TEMPLATE records are sort of like FUNCTION, but are emitted + for template member functions. E.g., + + template class q + { + ... + void f(); + ... + }; + + Within the list of FIELDs/GENFIELDs defining the member list + of the template "q", "f" would appear as a FUNC_TEMPLATE. + We'll also see instances of FUNCTION "f" records for each + instantiation of the template. */ + +struct dntt_type_func_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FUNC_TEMPLATE */ + unsigned int public: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int unused: 2; + vtpointer name ; /* name of function */ + vtpointer alias ; /* alternate name, if any */ + dnttpointer firstparam ; /* first FPARAM, if any */ + dnttpointer retval ; /* return type, if any */ + dnttpointer arglist ; /* ptr to argument list */ +}; + +/* LINK is apparently intended to link together function template + definitions with their instantiations. However, it is not clear + why this would be needed, except to provide the information on + a "ptype" command. And as far as I can tell, aCC does not + generate this record. */ + +struct dntt_type_link +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_LINK */ + unsigned int linkKind: 4; /* always LINK_UNKNOWN */ + unsigned int unused: 17; + long future1 ; /* expansion */ + dnttpointer ptr1 ; /* link from template */ + dnttpointer ptr2 ; /* to expansion */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* end of C++ specific SOM's. */ + +/* DNTT_TYPE_DYN_ARRAY_DESC is unused by GDB */ +/* DNTT_TYPE_DESC_SUBRANGE is unused by GDB */ +/* DNTT_TYPE_BEGIN_EXT is unused by GDB */ +/* DNTT_TYPE_INLN is unused by GDB */ +/* DNTT_TYPE_INLN_LIST is unused by GDB */ +/* DNTT_TYPE_ALIAS is unused by GDB */ + +struct dntt_type_doc_function +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* K_DOC_FUNCTION or */ + /* K_DOC_MEMFUNC */ + unsigned int global: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int expansion: 1; /* 1 = function expansion */ + unsigned int doc_clone: 1; + vtpointer name; /* name of function */ + vtpointer alias; /* alternate name, if any */ + dnttpointer firstparam; /* first FPARAM, if any */ + sltpointer address; /* code and text locations */ + CORE_ADDR entryaddr; /* address of entry point */ + dnttpointer retval; /* return type, if any */ + CORE_ADDR lowaddr; /* lowest address of function */ + CORE_ADDR hiaddr; /* highest address of function */ + dnttpointer inline_list; /* pointer to first inline */ + ltpointer lt_offset; /* start of frag/cp line table */ + ctxtpointer ctxt_offset; /* start of context table for this routine */ +}; + +/* DNTT_TYPE_DOC_MEMFUNC is unused by GDB */ + +/* DNTT_TYPE_GENERIC and DNTT_TYPE_BLOCK are convience structures + so we can examine a DNTT entry in a generic fashion. */ +struct dntt_type_generic +{ + unsigned int word[9]; +}; + +struct dntt_type_block +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + unsigned int word[2]; +}; + +/* One entry in a DNTT (either the LNTT or GNTT). + This is a union of the above 60 or so structure definitions. */ + +union dnttentry +{ + struct dntt_type_srcfile dsfile; + struct dntt_type_module dmodule; + struct dntt_type_function dfunc; + struct dntt_type_function dentry; + struct dntt_type_begin dbegin; + struct dntt_type_end dend; + struct dntt_type_fparam dfparam; + struct dntt_type_svar dsvar; + struct dntt_type_dvar ddvar; + struct dntt_type_const dconst; + struct dntt_type_type dtype; + struct dntt_type_type dtag; + struct dntt_type_pointer dptr; + struct dntt_type_enum denum; + struct dntt_type_memenum dmember; + struct dntt_type_set dset; + struct dntt_type_subrange dsubr; + struct dntt_type_array darray; + struct dntt_type_struct dstruct; + struct dntt_type_union dunion; + struct dntt_type_field dfield; + struct dntt_type_functype dfunctype; + struct dntt_type_with dwith; + struct dntt_type_function dblockdata; + struct dntt_type_class_scope dclass_scope; + struct dntt_type_pointer dreference; + struct dntt_type_ptrmem dptrmem; + struct dntt_type_ptrmemfunc dptrmemfunc; + struct dntt_type_class dclass; + struct dntt_type_genfield dgenfield; + struct dntt_type_vfunc dvfunc; + struct dntt_type_memaccess dmemaccess; + struct dntt_type_inheritance dinheritance; + struct dntt_type_friend_class dfriend_class; + struct dntt_type_friend_func dfriend_func; + struct dntt_type_modifier dmodifier; + struct dntt_type_object_id dobject_id; + struct dntt_type_template dtemplate; + struct dntt_type_templ_arg dtempl_arg; + struct dntt_type_func_template dfunc_template; + struct dntt_type_link dlink; + struct dntt_type_doc_function ddocfunc; + struct dntt_type_generic dgeneric; + struct dntt_type_block dblock; +}; + +/* Source line entry types. */ +enum slttype +{ + SLT_NORMAL, + SLT_SRCFILE, + SLT_MODULE, + SLT_FUNCTION, + SLT_ENTRY, + SLT_BEGIN, + SLT_END, + SLT_WITH, + SLT_EXIT, + SLT_ASSIST, + SLT_MARKER, + SLT_CLASS_SCOPE, + SLT_INLN, + SLT_NORMAL_OFFSET, +}; + +/* A normal source line entry. Simply provides a mapping of a source + line number to a code address. + + SLTDESC will always be SLT_NORMAL or SLT_EXIT. */ + +struct slt_normal +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + CORE_ADDR address; +}; + +struct slt_normal_off +{ + unsigned int sltdesc: 4; + unsigned int offset: 6; + unsigned int line: 22; + CORE_ADDR address; +}; + +/* A special source line entry. Provides a mapping of a declaration + to a line number. These entries point back into the DNTT which + references them. */ + +struct slt_special +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + dnttpointer backptr; +}; + +/* Used to describe nesting. + + For nested languages, an slt_assist entry must follow each SLT_FUNC + entry in the SLT. The address field will point forward to the + first slt_normal entry within the function's scope. */ + +struct slt_assist +{ + unsigned int sltdesc: 4; + unsigned int unused: 28; + sltpointer address; +}; + +struct slt_generic +{ + unsigned int word[2]; +}; + +union sltentry +{ + struct slt_normal snorm; + struct slt_normal_off snormoff; + struct slt_special sspec; + struct slt_assist sasst; + struct slt_generic sgeneric; +}; + +/* $LINES$ declarations + This is the line table used for optimized code, which is only present + in the new $PROGRAM_INFO$ debug space. */ + +#define DST_LN_ESCAPE_FLAG1 15 +#define DST_LN_ESCAPE_FLAG2 14 +#define DST_LN_CTX_SPEC1 13 +#define DST_LN_CTX_SPEC2 12 + +/* Escape function codes: */ + +typedef enum +{ + dst_ln_pad, /* pad byte */ + dst_ln_escape_1, /* reserved */ + dst_ln_dpc1_dln1, /* 1 byte line delta, 1 byte pc delta */ + dst_ln_dpc2_dln2, /* 2 bytes line delta, 2 bytes pc delta */ + dst_ln_pc4_ln4, /* 4 bytes ABSOLUTE line number, 4 bytes ABSOLUTE pc */ + dst_ln_dpc0_dln1, /* 1 byte line delta, pc delta = 0 */ + dst_ln_ln_off_1, /* statement escape, stmt # = 1 (2nd stmt on line) */ + dst_ln_ln_off, /* statement escape, stmt # = next byte */ + dst_ln_entry, /* entry escape, next byte is entry number */ + dst_ln_exit, /* exit escape */ + dst_ln_stmt_end, /* gap escape, 4 bytes pc delta */ + dst_ln_stmt_cp, /* current stmt is a critical point */ + dst_ln_escape_12, /* reserved */ + dst_ln_escape_13, /* this is an exception site record */ + dst_ln_nxt_byte, /* next byte contains the real escape code */ + dst_ln_end, /* end escape, final entry follows */ + dst_ln_escape1_END_OF_ENUM +} +dst_ln_escape1_t; + +typedef enum +{ + dst_ln_ctx_1, /* next byte describes context switch with 5-bit */ + /* index into the image table and 3-bit run length. */ + /* If run length is 0, end with another cxt specifier or ctx_end */ + dst_ln_ctx_2, /* next 2 bytes switch context: 13 bit index, 3 bit run length */ + dst_ln_ctx_4, /* next 4 bytes switch context: 29 bit index, 3 bit run length */ + dst_ln_ctx_end, /* end current context */ + dst_ln_col_run_1, /* next byte is column position of start of next statement, */ + /* following byte is length of statement */ + dst_ln_col_run_2, /* next 2 bytes is column position of start of next statement, */ + /* following 2 bytes is length of statement */ + dst_ln_init_base1, /* next 4 bytes are absolute PC, followed by 1 byte of line number */ + dst_ln_init_base2, /* next 4 bytes are absolute PC, followed by 2 bytes of line number */ + dst_ln_init_base3, /* next 4 bytes are absolute PC, followed by 3 bytes of line number */ + dst_ln_escape2_END_OF_ENUM +} +dst_ln_escape2_t; + +typedef union +{ + struct + { + unsigned int pc_delta : 4; /* 4 bit pc delta */ + int ln_delta : 4; /* 4 bit line number delta */ + } + delta; + + struct + { + unsigned int esc_flag : 4; /* alias for pc_delta */ + unsigned int esc_code : 4; /* escape function code (dst_ln_escape1_t, or ...2_t */ + } + esc; + + struct + { + unsigned int esc_flag : 4; /* dst_ln_ctx_spec1, or dst_ln_ctx_spec2 */ + unsigned int run_length : 2; + unsigned int ctx_index : 2; /* ...spec2 contains index; ...spec1, index - 4 */ + } + ctx_spec; + + char sdata; /* signed data byte */ + unsigned char udata; /* unsigned data byte */ +} +dst_ln_entry_t, + * dst_ln_entry_ptr_t; + +/* Warning: although the above union occupies only 1 byte the compiler treats + it as having size 2 (the minimum size of a struct). Therefore a sequence of + dst_ln_entry_t's cannot be described as an array, and walking through such a + sequence requires convoluted code such as + ln_ptr = (dst_ln_entry_ptr_t) (char*) ln_ptr + 1 + We regret the inconvenience. */ + +/* Structure for interpreting the byte following a dst_ln_ctx1 entry. */ +typedef struct +{ + unsigned int ctx1_index : 5; /* 5 bit index into context table */ + unsigned int ctx1_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx1_t, + *dst_ln_ctx1_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx2 entry. */ +typedef struct +{ + unsigned int ctx2_index : 13; /* 13 bit index into context table */ + unsigned int ctx2_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx2_t, + *dst_ln_ctx2_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx4 entry. */ +typedef struct +{ + unsigned int ctx4_index : 29; /* 29 bit index into context table */ + unsigned int ctx4_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx4_t, + *dst_ln_ctx4_ptr_t; + + +/* PXDB definitions. + + PXDB is a post-processor which takes the executable file + and massages the debug information so that the debugger may + start up and run more efficiently. Some of the tasks + performed by PXDB are: + + o Remove duplicate global type and variable information + from the GNTT, + + o Append the GNTT onto the end of the LNTT and place both + back in the LNTT section, + + o Build quick look-up tables (description follows) for + files, procedures, modules, and paragraphs (for Cobol), + placing these in the GNTT section, + + o Reconstruct the header appearing in the header section + to access this information. + + The "quick look-up" tables are in the $GNTT$ sub-space, in + the following order: + + Procedures -sorted by address + Source files -sorted by address (of the + generated code from routines) + Modules -sorted by address + Classes - + Address Alias -sorted by index + Object IDs -sorted by object identifier + + Most quick entries have (0-based) indices into the LNTT tables to + the full entries for the item it describes. + + The post-PXDB header is in the $HEADER$ sub-space. Alas, it + occurs in different forms, depending on the optimization level + in the compilation step and whether PXDB was run or not. The + worst part is the forms aren't self-describing, so we'll have + to grovel in the bits to figure out what kind we're looking at + (see hp_get_header in hp-psymtab-read.c). */ + +/* PXDB versions. */ + +#define PXDB_VERSION_CPLUSPLUS 1 +#define PXDB_VERSION_7_4 2 +#define PXDB_VERSION_CPP_30 3 +#define PXDB_VERSION_DDE_3_2A 4 +#define PXDB_VERSION_DDE_3_2 5 +#define PXDB_VERSION_DDE_4_0 6 + +#define PXDB_VERSION_2_1 1 + +/* Header version for the case that there is no DOC info + but the executable has been processed by pxdb (the easy + case, from "cc -g"). */ + +typedef struct PXDB_struct +{ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare:12; + short version; /* pxdb header version */ + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} PXDB_header, *PXDB_header_ptr; + +/* Header version for the case that there is no DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct XDB_header_struct +{ + long gntt_length; + long lntt_length; + long slt_length; + long vt_length; + long xt_length; +} XDB_header; + +/* Header version for the case that there is DOC info and the + executable has been processed by pxdb. */ + +typedef struct DOC_info_PXDB_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header */ + unsigned int version: 8; /* version of pxdb see defines + PXDB_VERSION_* in this file. */ + unsigned int reserved_for_flags: 16;/* for future use; -- must be + set to zero. */ + unsigned int has_aux_pd_table: 1; /* $GNTT$ has aux PD table */ + unsigned int has_expr_table: 1; /* space has $EXPR$ */ + unsigned int has_range_table: 1; /* space has $RANGE$ */ + unsigned int has_context_table: 1; /* space has $SRC_CTXT$ */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ + subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset + subspace for line table mapping. */ + /* The following fields are the same as those in the PXDB_header in $DEBUG$ */ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare : 28; + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} DOC_info_PXDB_header; + +/* Header version for the case that there is DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct DOC_info_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header*/ + unsigned int version: 8; /* version of debug/header + format. For 10.0 the value + will be 1. For "Davis" the value is 2. */ + unsigned int reserved_for_flags: 18; /* for future use; -- must be set to zero. */ + unsigned int has_range_table: 1; /* space contains a $RANGE$ subspace for variable ranges. */ + unsigned int has_context_table: 1; /* space contains a $CTXT$ subspace for context/inline table. */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset subspace for line table mapping. */ + + long gntt_length; /* same as old header */ + long lntt_length; /* same as old header */ + long slt_length; /* same as old header */ + long vt_length; /* same as old header */ + long xt_length; /* same as old header */ + long ctxt_length; /* present only if version >= 2 */ + long range_length; /* present only if version >= 2 */ + long expr_length; /* present only if version >= 2 */ + +} DOC_info_header; + +typedef union GenericDebugHeader_union +{ + PXDB_header no_doc; + DOC_info_PXDB_header doc; + XDB_header no_pxdb_no_doc; + DOC_info_header no_pxdb_doc; +} GenericDebugHeader; + + +/* Procedure Descriptor: + An element of the procedure quick look-up table. */ + +typedef struct quick_procedure +{ + long isym; /* 0-based index of first symbol + for procedure in $LNTT$, + i.e. the procedure itself. */ + CORE_ADDR adrStart; /* memory adr of start of proc */ + CORE_ADDR adrEnd; /* memory adr of end of proc */ + char *sbAlias; /* alias name of procedure */ + char *sbProc; /* real name of procedure */ + CORE_ADDR adrBp; /* address of entry breakpoint */ + CORE_ADDR adrExitBp; /* address of exit breakpoint */ + int icd; /* member of this class (index) */ + unsigned int ipd; /* index of template for this */ + /* function (index) */ + unsigned int unused: 5; + unsigned int no_lt_offset: 1;/* no entry in lt_offset table */ + unsigned int fTemplate: 1; /* function template */ + unsigned int fExpansion: 1; /* function expansion */ + unsigned int linked : 1; /* linked with other expansions */ + unsigned int duplicate: 1; /* clone of another procedure */ + unsigned int overloaded:1; /* overloaded function */ + unsigned int member: 1; /* class member function */ + unsigned int constructor:1; /* constructor function */ + unsigned int destructor:1; /* destructor function */ + unsigned int Static: 1; /* static function */ + unsigned int Virtual: 1; /* virtual function */ + unsigned int constant: 1; /* constant function */ + unsigned int pure: 1; /* pure (virtual) function */ + unsigned int language: 4; /* procedure's language */ + unsigned int inlined: 1; /* function has been inlined */ + unsigned int Operator: 1; /* operator function */ + unsigned int stub: 1; /* bodyless function */ + unsigned int optimize: 2; /* optimization level */ + unsigned int level: 5; /* nesting level (top=0) */ +} quick_procedure_entry, *quick_procedure_entry_ptr; + +/* Source File Descriptor: + An element of the source file quick look-up table. */ + +typedef struct quick_source +{ + long isym; /* 0-based index in $LNTT$ of + first symbol for this file. */ + CORE_ADDR adrStart; /* mem adr of start of file's code */ + CORE_ADDR adrEnd; /* mem adr of end of file's code */ + char *sbFile; /* name of source file */ + unsigned int fHasDecl: 1; /* do we have a .d file? */ + unsigned int fWarned: 1; /* have warned about age problems? */ + unsigned int fSrcfile: 1; /* 0 => include 1=> source */ + unsigned short ilnMac; /* lines in file (0 if don't know) */ + int ipd; /* 0-based index of first procedure + in this file, in the quick + look-up table of procedures. */ + unsigned int *rgLn; /* line pointer array, if any */ +} quick_file_entry, *quick_file_entry_ptr; + +/* Module Descriptor: + An element of the module quick reference table. */ + +typedef struct quick_module +{ + long isym; /* 0-based index of first + symbol for module. */ + CORE_ADDR adrStart; /* adr of start of mod. */ + CORE_ADDR adrEnd; /* adr of end of mod. */ + char *sbAlias; /* alias name of module */ + char *sbMod; /* real name of module */ + unsigned int imports: 1; /* module have any imports? */ + unsigned int vars_in_front: 1; /* module globals in front? */ + unsigned int vars_in_gaps: 1; /* module globals in gaps? */ + unsigned int language: 4; /* type of language */ + unsigned int unused : 25; + unsigned int unused2; /* space for future stuff */ +} quick_module_entry, *quick_module_entry_ptr; + +/* Auxiliary Procedure Descriptor: + An element of the auxiliary procedure quick look-up table. */ + +typedef struct quick_aux_procedure +{ + long isym_inln; /* start on inline list for proc */ + long spare; +} quick_aux_procedure_entry, *quick_aux_procedure_entry_ptr; + +/* Paragraph Descriptor: + An element of the paragraph quick look-up table. */ + +typedef struct quick_paragraph +{ + long isym; /* first symbol for label (index) */ + CORE_ADDR adrStart; /* memory adr of start of label */ + CORE_ADDR adrEnd; /* memory adr of end of label */ + char *sbLab; /* name of label */ + unsigned int inst; /* Used in xdb to store inst @ bp */ + unsigned int sect: 1; /* true = section, false = parag. */ + unsigned int unused: 31; /* future use */ +} quick_paragraph_entry, *quick_paragraph_entry_ptr; + +/* Class Descriptor: + An element of the class quick look-up table. */ + +typedef struct quick_class +{ + char *sbClass; /* name of class */ + long isym; /* class symbol (tag) */ + unsigned int type : 2; /* 0=class, 1=union, 2=struct */ + unsigned int fTemplate : 1;/* class template */ + unsigned int expansion : 1;/* template expansion */ + unsigned int unused :28; + sltpointer lowscope; /* beginning of defined scope */ + sltpointer hiscope; /* end of defined scope */ +} quick_class_entry, *quick_class_entry_ptr; + +/* Address Alias Entry + An element of the address alias quick look-up table. */ + +typedef struct quick_alias +{ + CORE_ADDR low; + CORE_ADDR high; + int index; + unsigned int unused : 31; + unsigned int alternate : 1; /* alternate unnamed aliases? */ +} quick_alias_entry, *quick_alias_entry_ptr; + +/* Object Identification Entry + An element of the object identification quick look-up table. */ + +typedef struct quick_obj_ID +{ + CORE_ADDR obj_ident; /* class identifier */ + long isym; /* class symbol */ + long offset; /* offset to object start */ +} quick_obj_ID_entry, *quick_obj_ID_entry_ptr; + +#endif /* HP_SYMTAB_INCLUDED */ diff --git a/external/gpl3/gdb/dist/include/ieee.h b/external/gpl3/gdb/dist/include/ieee.h new file mode 100644 index 000000000000..72fcad420f9f --- /dev/null +++ b/external/gpl3/gdb/dist/include/ieee.h @@ -0,0 +1,165 @@ +/* IEEE Standard 695-1980 "Universal Format for Object Modules" header file + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Contributed by Cygnus Support. */ + +#define N_W_VARIABLES 8 +#define Module_Beginning 0xe0 + +typedef struct ieee_module + { + char *processor; + char *module_name; + } +ieee_module_begin_type; + +#define Address_Descriptor 0xec +typedef struct ieee_address + { + bfd_vma number_of_bits_mau; + bfd_vma number_of_maus_in_address; + + unsigned char byte_order; +#define IEEE_LITTLE 0xcc +#define IEEE_BIG 0xcd + } +ieee_address_descriptor_type; + +typedef union ieee_w_variable + { + file_ptr offset[N_W_VARIABLES]; + + struct + { + file_ptr extension_record; + file_ptr environmental_record; + file_ptr section_part; + file_ptr external_part; + file_ptr debug_information_part; + file_ptr data_part; + file_ptr trailer_part; + file_ptr me_record; + } + r; + } +ieee_w_variable_type; + +typedef enum ieee_record + { + ieee_number_start_enum = 0x00, + ieee_number_end_enum=0x7f, + ieee_number_repeat_start_enum = 0x80, + ieee_number_repeat_end_enum = 0x88, + ieee_number_repeat_4_enum = 0x84, + ieee_number_repeat_3_enum = 0x83, + ieee_number_repeat_2_enum = 0x82, + ieee_number_repeat_1_enum = 0x81, + ieee_module_beginning_enum = 0xe0, + ieee_module_end_enum = 0xe1, + ieee_extension_length_1_enum = 0xde, + ieee_extension_length_2_enum = 0xdf, + ieee_section_type_enum = 0xe6, + ieee_section_alignment_enum = 0xe7, + ieee_external_symbol_enum = 0xe8, + ieee_comma = 0x90, + ieee_external_reference_enum = 0xe9, + ieee_set_current_section_enum = 0xe5, + ieee_address_descriptor_enum = 0xec, + ieee_load_constant_bytes_enum = 0xed, + ieee_load_with_relocation_enum = 0xe4, + + ieee_variable_A_enum = 0xc1, + ieee_variable_B_enum = 0xc2, + ieee_variable_C_enum = 0xc3, + ieee_variable_D_enum = 0xc4, + ieee_variable_E_enum = 0xc5, + ieee_variable_F_enum = 0xc6, + ieee_variable_G_enum = 0xc7, + ieee_variable_H_enum = 0xc8, + ieee_variable_I_enum = 0xc9, + ieee_variable_J_enum = 0xca, + ieee_variable_K_enum = 0xcb, + ieee_variable_L_enum = 0xcc, + ieee_variable_M_enum = 0xcd, + ieee_variable_N_enum = 0xce, + ieee_variable_O_enum = 0xcf, + ieee_variable_P_enum = 0xd0, + ieee_variable_Q_enum = 0xd1, + ieee_variable_R_enum = 0xd2, + ieee_variable_S_enum = 0xd3, + ieee_variable_T_enum = 0xd4, + ieee_variable_U_enum = 0xd5, + ieee_variable_V_enum = 0xd6, + ieee_variable_W_enum = 0xd7, + ieee_variable_X_enum = 0xd8, + ieee_variable_Y_enum = 0xd9, + ieee_variable_Z_enum = 0xda, + ieee_function_plus_enum = 0xa5, + ieee_function_minus_enum = 0xa6, + ieee_function_signed_open_b_enum = 0xba, + ieee_function_signed_close_b_enum = 0xbb, + + ieee_function_unsigned_open_b_enum = 0xbc, + ieee_function_unsigned_close_b_enum = 0xbd, + + ieee_function_either_open_b_enum = 0xbe, + ieee_function_either_close_b_enum = 0xbf, + ieee_record_seperator_enum = 0xdb, + + ieee_e2_first_byte_enum = 0xe2, + ieee_section_size_enum = 0xe2d3, + ieee_physical_region_size_enum = 0xe2c1, + ieee_region_base_address_enum = 0xe2c2, + ieee_mau_size_enum = 0xe2c6, + ieee_m_value_enum = 0xe2cd, + ieee_section_base_address_enum = 0xe2cc, + ieee_asn_record_enum = 0xe2ce, + ieee_section_offset_enum = 0xe2d2, + ieee_value_starting_address_enum = 0xe2c7, + ieee_assign_value_to_variable_enum = 0xe2d7, + ieee_set_current_pc_enum = 0xe2d0, + ieee_value_record_enum = 0xe2c9, + ieee_nn_record = 0xf0, + ieee_at_record_enum = 0xf1, + ieee_ty_record_enum = 0xf2, + ieee_attribute_record_enum = 0xf1c9, + ieee_atn_record_enum = 0xf1ce, + ieee_external_reference_info_record_enum = 0xf1d8, + ieee_weak_external_reference_enum= 0xf4, + ieee_repeat_data_enum = 0xf7, + ieee_bb_record_enum = 0xf8, + ieee_be_record_enum = 0xf9 + } +ieee_record_enum_type; + +typedef struct ieee_section + { + unsigned int section_index; + unsigned int section_type; + char * section_name; + unsigned int parent_section_index; + unsigned int sibling_section_index; + unsigned int context_index; + } +ieee_section_type; + +#define IEEE_REFERENCE_BASE 11 +#define IEEE_PUBLIC_BASE 32 +#define IEEE_SECTION_NUMBER_BASE 1 + diff --git a/external/gpl3/gdb/dist/include/libiberty.h b/external/gpl3/gdb/dist/include/libiberty.h new file mode 100644 index 000000000000..1cc7250bf3c9 --- /dev/null +++ b/external/gpl3/gdb/dist/include/libiberty.h @@ -0,0 +1,679 @@ +/* Function declarations for libiberty. + + Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, + 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + + Note - certain prototypes declared in this header file are for + functions whoes implementation copyright does not belong to the + FSF. Those prototypes are present in this file for reference + purposes only and their presence in this file should not construed + as an indication of ownership by the FSF of the implementation of + those functions in any way or form whatsoever. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Written by Cygnus Support, 1994. + + The libiberty library provides a number of functions which are + missing on some operating systems. We do not declare those here, + to avoid conflicts with the system header files on operating + systems that do support those functions. In this file we only + declare those functions which are specific to libiberty. */ + +#ifndef LIBIBERTY_H +#define LIBIBERTY_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ansidecl.h" + +/* Get a definition for size_t. */ +#include +/* Get a definition for va_list. */ +#include + +#include + +/* If the OS supports it, ensure that the supplied stream is setup to + avoid any multi-threaded locking. Otherwise leave the FILE pointer + unchanged. If the stream is NULL do nothing. */ + +extern void unlock_stream (FILE *); + +/* If the OS supports it, ensure that the standard I/O streams, stdin, + stdout and stderr are setup to avoid any multi-threaded locking. + Otherwise do nothing. */ + +extern void unlock_std_streams (void); + +/* Open and return a FILE pointer. If the OS supports it, ensure that + the stream is setup to avoid any multi-threaded locking. Otherwise + return the FILE pointer unchanged. */ + +extern FILE *fopen_unlocked (const char *, const char *); +extern FILE *fdopen_unlocked (int, const char *); +extern FILE *freopen_unlocked (const char *, const char *, FILE *); + +/* Build an argument vector from a string. Allocates memory using + malloc. Use freeargv to free the vector. */ + +extern char **buildargv (const char *) ATTRIBUTE_MALLOC; + +/* Free a vector returned by buildargv. */ + +extern void freeargv (char **); + +/* Duplicate an argument vector. Allocates memory using malloc. Use + freeargv to free the vector. */ + +extern char **dupargv (char **) ATTRIBUTE_MALLOC; + +/* Expand "@file" arguments in argv. */ + +extern void expandargv PARAMS ((int *, char ***)); + +/* Write argv to an @-file, inserting necessary quoting. */ + +extern int writeargv PARAMS ((char **, FILE *)); + +/* Return the last component of a path name. Note that we can't use a + prototype here because the parameter is declared inconsistently + across different systems, sometimes as "char *" and sometimes as + "const char *" */ + +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if !HAVE_DECL_BASENAME +#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (__MINGW32__) || defined (HAVE_DECL_BASENAME) +extern char *basename (const char *); +#else +/* Do not allow basename to be used if there is no prototype seen. We + either need to use the above prototype or have one from + autoconf which would result in HAVE_DECL_BASENAME being set. */ +#define basename basename_cannot_be_used_without_a_prototype +#endif +#endif + +/* A well-defined basename () that is always compiled in. */ + +extern const char *lbasename (const char *); + +/* Same, but assumes DOS semantics (drive name, backslash is also a + dir separator) regardless of host. */ + +extern const char *dos_lbasename (const char *); + +/* Same, but assumes Unix semantics (absolute paths always start with + a slash, only forward slash is accepted as dir separator) + regardless of host. */ + +extern const char *unix_lbasename (const char *); + +/* A well-defined realpath () that is always compiled in. */ + +extern char *lrealpath (const char *); + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using xmalloc. */ + +extern char *concat (const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using xmalloc. The first argument is + not one of the strings to be concatenated, but if not NULL is a + pointer to be freed after the new string is created, similar to the + way xrealloc works. */ + +extern char *reconcat (char *, const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_SENTINEL; + +/* Determine the length of concatenating an arbitrary number of + strings. You must pass NULL as the last argument of this function, + to terminate the list of strings. */ + +extern unsigned long concat_length (const char *, ...) ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings into a SUPPLIED area of + memory. You must pass NULL as the last argument of this function, + to terminate the list of strings. The supplied memory is assumed + to be large enough. */ + +extern char *concat_copy (char *, const char *, ...) ATTRIBUTE_SENTINEL; + +/* Concatenate an arbitrary number of strings into a GLOBAL area of + memory. You must pass NULL as the last argument of this function, + to terminate the list of strings. The supplied memory is assumed + to be large enough. */ + +extern char *concat_copy2 (const char *, ...) ATTRIBUTE_SENTINEL; + +/* This is the global area used by concat_copy2. */ + +extern char *libiberty_concat_ptr; + +/* Concatenate an arbitrary number of strings. You must pass NULL as + the last argument of this function, to terminate the list of + strings. Allocates memory using alloca. The arguments are + evaluated twice! */ +#define ACONCAT(ACONCAT_PARAMS) \ + (libiberty_concat_ptr = (char *) alloca (concat_length ACONCAT_PARAMS + 1), \ + concat_copy2 ACONCAT_PARAMS) + +/* Check whether two file descriptors refer to the same file. */ + +extern int fdmatch (int fd1, int fd2); + +/* Return the position of the first bit set in the argument. */ +/* Prototypes vary from system to system, so we only provide a + prototype on systems where we know that we need it. */ +#if defined (HAVE_DECL_FFS) && !HAVE_DECL_FFS +extern int ffs(int); +#endif + +/* Get the working directory. The result is cached, so don't call + chdir() between calls to getpwd(). */ + +extern char * getpwd (void); + +/* Get the current time. */ +/* Prototypes vary from system to system, so we only provide a + prototype on systems where we know that we need it. */ +#ifdef __MINGW32__ +/* Forward declaration to avoid #include . */ +struct timeval; +extern int gettimeofday (struct timeval *, void *); +#endif + +/* Get the amount of time the process has run, in microseconds. */ + +extern long get_run_time (void); + +/* Generate a relocated path to some installation directory. Allocates + return value using malloc. */ + +extern char *make_relative_prefix (const char *, const char *, + const char *) ATTRIBUTE_MALLOC; + +/* Generate a relocated path to some installation directory without + attempting to follow any soft links. Allocates + return value using malloc. */ + +extern char *make_relative_prefix_ignore_links (const char *, const char *, + const char *) ATTRIBUTE_MALLOC; + +/* Choose a temporary directory to use for scratch files. */ + +extern char *choose_temp_base (void) ATTRIBUTE_MALLOC; + +/* Return a temporary file name or NULL if unable to create one. */ + +extern char *make_temp_file (const char *) ATTRIBUTE_MALLOC; + +/* Remove a link to a file unless it is special. */ + +extern int unlink_if_ordinary (const char *); + +/* Allocate memory filled with spaces. Allocates using malloc. */ + +extern const char *spaces (int count); + +/* Return the maximum error number for which strerror will return a + string. */ + +extern int errno_max (void); + +/* Return the name of an errno value (e.g., strerrno (EINVAL) returns + "EINVAL"). */ + +extern const char *strerrno (int); + +/* Given the name of an errno value, return the value. */ + +extern int strtoerrno (const char *); + +/* ANSI's strerror(), but more robust. */ + +extern char *xstrerror (int); + +/* Return the maximum signal number for which strsignal will return a + string. */ + +extern int signo_max (void); + +/* Return a signal message string for a signal number + (e.g., strsignal (SIGHUP) returns something like "Hangup"). */ +/* This is commented out as it can conflict with one in system headers. + We still document its existence though. */ + +/*extern const char *strsignal (int);*/ + +/* Return the name of a signal number (e.g., strsigno (SIGHUP) returns + "SIGHUP"). */ + +extern const char *strsigno (int); + +/* Given the name of a signal, return its number. */ + +extern int strtosigno (const char *); + +/* Register a function to be run by xexit. Returns 0 on success. */ + +extern int xatexit (void (*fn) (void)); + +/* Exit, calling all the functions registered with xatexit. */ + +extern void xexit (int status) ATTRIBUTE_NORETURN; + +/* Set the program name used by xmalloc. */ + +extern void xmalloc_set_program_name (const char *); + +/* Report an allocation failure. */ +extern void xmalloc_failed (size_t) ATTRIBUTE_NORETURN; + +/* Allocate memory without fail. If malloc fails, this will print a + message to stderr (using the name set by xmalloc_set_program_name, + if any) and then call xexit. */ + +extern void *xmalloc (size_t) ATTRIBUTE_MALLOC; + +/* Reallocate memory without fail. This works like xmalloc. Note, + realloc type functions are not suitable for attribute malloc since + they may return the same address across multiple calls. */ + +extern void *xrealloc (void *, size_t); + +/* Allocate memory without fail and set it to zero. This works like + xmalloc. */ + +extern void *xcalloc (size_t, size_t) ATTRIBUTE_MALLOC; + +/* Copy a string into a memory buffer without fail. */ + +extern char *xstrdup (const char *) ATTRIBUTE_MALLOC; + +/* Copy at most N characters from string into a buffer without fail. */ + +extern char *xstrndup (const char *, size_t) ATTRIBUTE_MALLOC; + +/* Copy an existing memory buffer to a new memory buffer without fail. */ + +extern void *xmemdup (const void *, size_t, size_t) ATTRIBUTE_MALLOC; + +/* Physical memory routines. Return values are in BYTES. */ +extern double physmem_total (void); +extern double physmem_available (void); + +/* Compute the 32-bit CRC of a block of memory. */ +extern unsigned int xcrc32 (const unsigned char *, int, unsigned int); + +/* These macros provide a K&R/C89/C++-friendly way of allocating structures + with nice encapsulation. The XDELETE*() macros are technically + superfluous, but provided here for symmetry. Using them consistently + makes it easier to update client code to use different allocators such + as new/delete and new[]/delete[]. */ + +/* Scalar allocators. */ + +#define XALLOCA(T) ((T *) alloca (sizeof (T))) +#define XNEW(T) ((T *) xmalloc (sizeof (T))) +#define XCNEW(T) ((T *) xcalloc (1, sizeof (T))) +#define XDUP(T, P) ((T *) xmemdup ((P), sizeof (T), sizeof (T))) +#define XDELETE(P) free ((void*) (P)) + +/* Array allocators. */ + +#define XALLOCAVEC(T, N) ((T *) alloca (sizeof (T) * (N))) +#define XNEWVEC(T, N) ((T *) xmalloc (sizeof (T) * (N))) +#define XCNEWVEC(T, N) ((T *) xcalloc ((N), sizeof (T))) +#define XDUPVEC(T, P, N) ((T *) xmemdup ((P), sizeof (T) * (N), sizeof (T) * (N))) +#define XRESIZEVEC(T, P, N) ((T *) xrealloc ((void *) (P), sizeof (T) * (N))) +#define XDELETEVEC(P) free ((void*) (P)) + +/* Allocators for variable-sized structures and raw buffers. */ + +#define XALLOCAVAR(T, S) ((T *) alloca ((S))) +#define XNEWVAR(T, S) ((T *) xmalloc ((S))) +#define XCNEWVAR(T, S) ((T *) xcalloc (1, (S))) +#define XDUPVAR(T, P, S1, S2) ((T *) xmemdup ((P), (S1), (S2))) +#define XRESIZEVAR(T, P, S) ((T *) xrealloc ((P), (S))) + +/* Type-safe obstack allocator. */ + +#define XOBNEW(O, T) ((T *) obstack_alloc ((O), sizeof (T))) +#define XOBNEWVEC(O, T, N) ((T *) obstack_alloc ((O), sizeof (T) * (N))) +#define XOBNEWVAR(O, T, S) ((T *) obstack_alloc ((O), (S))) +#define XOBFINISH(O, T) ((T) obstack_finish ((O))) + +/* hex character manipulation routines */ + +#define _hex_array_size 256 +#define _hex_bad 99 +extern const unsigned char _hex_value[_hex_array_size]; +extern void hex_init (void); +#define hex_p(c) (hex_value (c) != _hex_bad) +/* If you change this, note well: Some code relies on side effects in + the argument being performed exactly once. */ +#define hex_value(c) ((unsigned int) _hex_value[(unsigned char) (c)]) + +/* Flags for pex_init. These are bits to be or'ed together. */ + +/* Record subprocess times, if possible. */ +#define PEX_RECORD_TIMES 0x1 + +/* Use pipes for communication between processes, if possible. */ +#define PEX_USE_PIPES 0x2 + +/* Save files used for communication between processes. */ +#define PEX_SAVE_TEMPS 0x4 + +/* Prepare to execute one or more programs, with standard output of + each program fed to standard input of the next. + FLAGS As above. + PNAME The name of the program to report in error messages. + TEMPBASE A base name to use for temporary files; may be NULL to + use a random name. + Returns NULL on error. */ + +extern struct pex_obj *pex_init (int flags, const char *pname, + const char *tempbase); + +/* Flags for pex_run. These are bits to be or'ed together. */ + +/* Last program in pipeline. Standard output of program goes to + OUTNAME, or, if OUTNAME is NULL, to standard output of caller. Do + not set this if you want to call pex_read_output. After this is + set, pex_run may no longer be called with the same struct + pex_obj. */ +#define PEX_LAST 0x1 + +/* Search for program in executable search path. */ +#define PEX_SEARCH 0x2 + +/* OUTNAME is a suffix. */ +#define PEX_SUFFIX 0x4 + +/* Send program's standard error to standard output. */ +#define PEX_STDERR_TO_STDOUT 0x8 + +/* Input file should be opened in binary mode. This flag is ignored + on Unix. */ +#define PEX_BINARY_INPUT 0x10 + +/* Output file should be opened in binary mode. This flag is ignored + on Unix. For proper behaviour PEX_BINARY_INPUT and + PEX_BINARY_OUTPUT have to match appropriately--i.e., a call using + PEX_BINARY_OUTPUT should be followed by a call using + PEX_BINARY_INPUT. */ +#define PEX_BINARY_OUTPUT 0x20 + +/* Capture stderr to a pipe. The output can be read by + calling pex_read_err and reading from the returned + FILE object. This flag may be specified only for + the last program in a pipeline. + + This flag is supported only on Unix and Windows. */ +#define PEX_STDERR_TO_PIPE 0x40 + +/* Capture stderr in binary mode. This flag is ignored + on Unix. */ +#define PEX_BINARY_ERROR 0x80 + + +/* Execute one program. Returns NULL on success. On error returns an + error string (typically just the name of a system call); the error + string is statically allocated. + + OBJ Returned by pex_init. + + FLAGS As above. + + EXECUTABLE The program to execute. + + ARGV NULL terminated array of arguments to pass to the program. + + OUTNAME Sets the output file name as follows: + + PEX_SUFFIX set (OUTNAME may not be NULL): + TEMPBASE parameter to pex_init not NULL: + Output file name is the concatenation of TEMPBASE + and OUTNAME. + TEMPBASE is NULL: + Output file name is a random file name ending in + OUTNAME. + PEX_SUFFIX not set: + OUTNAME not NULL: + Output file name is OUTNAME. + OUTNAME NULL, TEMPBASE not NULL: + Output file name is randomly chosen using + TEMPBASE. + OUTNAME NULL, TEMPBASE NULL: + Output file name is randomly chosen. + + If PEX_LAST is not set, the output file name is the + name to use for a temporary file holding stdout, if + any (there will not be a file if PEX_USE_PIPES is set + and the system supports pipes). If a file is used, it + will be removed when no longer needed unless + PEX_SAVE_TEMPS is set. + + If PEX_LAST is set, and OUTNAME is not NULL, standard + output is written to the output file name. The file + will not be removed. If PEX_LAST and PEX_SUFFIX are + both set, TEMPBASE may not be NULL. + + ERRNAME If not NULL, this is the name of a file to which + standard error is written. If NULL, standard error of + the program is standard error of the caller. + + ERR On an error return, *ERR is set to an errno value, or + to 0 if there is no relevant errno. +*/ + +extern const char *pex_run (struct pex_obj *obj, int flags, + const char *executable, char * const *argv, + const char *outname, const char *errname, + int *err); + +/* As for pex_run (), but takes an extra parameter to enable the + environment for the child process to be specified. + + ENV The environment for the child process, specified as + an array of character pointers. Each element of the + array should point to a string of the form VAR=VALUE, + with the exception of the last element which must be + a null pointer. +*/ + +extern const char *pex_run_in_environment (struct pex_obj *obj, int flags, + const char *executable, + char * const *argv, + char * const *env, + const char *outname, + const char *errname, int *err); + +/* Return a stream for a temporary file to pass to the first program + in the pipeline as input. The file name is chosen as for pex_run. + pex_run closes the file automatically; don't close it yourself. */ + +extern FILE *pex_input_file (struct pex_obj *obj, int flags, + const char *in_name); + +/* Return a stream for a pipe connected to the standard input of the + first program in the pipeline. You must have passed + `PEX_USE_PIPES' to `pex_init'. Close the returned stream + yourself. */ + +extern FILE *pex_input_pipe (struct pex_obj *obj, int binary); + +/* Read the standard output of the last program to be executed. + pex_run can not be called after this. BINARY should be non-zero if + the file should be opened in binary mode; this is ignored on Unix. + Returns NULL on error. Don't call fclose on the returned FILE; it + will be closed by pex_free. */ + +extern FILE *pex_read_output (struct pex_obj *, int binary); + +/* Read the standard error of the last program to be executed. + pex_run can not be called after this. BINARY should be non-zero if + the file should be opened in binary mode; this is ignored on Unix. + Returns NULL on error. Don't call fclose on the returned FILE; it + will be closed by pex_free. */ + +extern FILE *pex_read_err (struct pex_obj *, int binary); + +/* Return exit status of all programs in VECTOR. COUNT indicates the + size of VECTOR. The status codes in the vector are in the order of + the calls to pex_run. Returns 0 on error, 1 on success. */ + +extern int pex_get_status (struct pex_obj *, int count, int *vector); + +/* Return times of all programs in VECTOR. COUNT indicates the size + of VECTOR. struct pex_time is really just struct timeval, but that + is not portable to all systems. Returns 0 on error, 1 on + success. */ + +struct pex_time +{ + unsigned long user_seconds; + unsigned long user_microseconds; + unsigned long system_seconds; + unsigned long system_microseconds; +}; + +extern int pex_get_times (struct pex_obj *, int count, + struct pex_time *vector); + +/* Clean up a pex_obj. If you have not called pex_get_times or + pex_get_status, this will try to kill the subprocesses. */ + +extern void pex_free (struct pex_obj *); + +/* Just execute one program. Return value is as for pex_run. + FLAGS Combination of PEX_SEARCH and PEX_STDERR_TO_STDOUT. + EXECUTABLE As for pex_run. + ARGV As for pex_run. + PNAME As for pex_init. + OUTNAME As for pex_run when PEX_LAST is set. + ERRNAME As for pex_run. + STATUS Set to exit status on success. + ERR As for pex_run. +*/ + +extern const char *pex_one (int flags, const char *executable, + char * const *argv, const char *pname, + const char *outname, const char *errname, + int *status, int *err); + +/* pexecute and pwait are the old pexecute interface, still here for + backward compatibility. Don't use these for new code. Instead, + use pex_init/pex_run/pex_get_status/pex_free, or pex_one. */ + +/* Definitions used by the pexecute routine. */ + +#define PEXECUTE_FIRST 1 +#define PEXECUTE_LAST 2 +#define PEXECUTE_ONE (PEXECUTE_FIRST + PEXECUTE_LAST) +#define PEXECUTE_SEARCH 4 +#define PEXECUTE_VERBOSE 8 + +/* Execute a program. */ + +extern int pexecute (const char *, char * const *, const char *, + const char *, char **, char **, int); + +/* Wait for pexecute to finish. */ + +extern int pwait (int, int *, int); + +#if !HAVE_DECL_ASPRINTF +/* Like sprintf but provides a pointer to malloc'd storage, which must + be freed by the caller. */ + +extern int asprintf (char **, const char *, ...) ATTRIBUTE_PRINTF_2; +#endif + +#if !HAVE_DECL_VASPRINTF +/* Like vsprintf but provides a pointer to malloc'd storage, which + must be freed by the caller. */ + +extern int vasprintf (char **, const char *, va_list) ATTRIBUTE_PRINTF(2,0); +#endif + +#if defined(HAVE_DECL_SNPRINTF) && !HAVE_DECL_SNPRINTF +/* Like sprintf but prints at most N characters. */ +extern int snprintf (char *, size_t, const char *, ...) ATTRIBUTE_PRINTF_3; +#endif + +#if defined(HAVE_DECL_VSNPRINTF) && !HAVE_DECL_VSNPRINTF +/* Like vsprintf but prints at most N characters. */ +extern int vsnprintf (char *, size_t, const char *, va_list) ATTRIBUTE_PRINTF(3,0); +#endif + +#if defined(HAVE_DECL_STRVERSCMP) && !HAVE_DECL_STRVERSCMP +/* Compare version strings. */ +extern int strverscmp (const char *, const char *); +#endif + +/* Set the title of a process */ +extern void setproctitle (const char *name, ...); + +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) + +/* Drastically simplified alloca configurator. If we're using GCC, + we use __builtin_alloca; otherwise we use the C alloca. The C + alloca is always available. You can override GCC by defining + USE_C_ALLOCA yourself. The canonical autoconf macro C_ALLOCA is + also set/unset as it is often used to indicate whether code needs + to call alloca(0). */ +extern void *C_alloca (size_t) ATTRIBUTE_MALLOC; +#undef alloca +#if GCC_VERSION >= 2000 && !defined USE_C_ALLOCA +# define alloca(x) __builtin_alloca(x) +# undef C_ALLOCA +# define ASTRDUP(X) \ + (__extension__ ({ const char *const libiberty_optr = (X); \ + const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \ + char *const libiberty_nptr = (char *const) alloca (libiberty_len); \ + (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); })) +#else +# define alloca(x) C_alloca(x) +# undef USE_C_ALLOCA +# define USE_C_ALLOCA 1 +# undef C_ALLOCA +# define C_ALLOCA 1 +extern const char *libiberty_optr; +extern char *libiberty_nptr; +extern unsigned long libiberty_len; +# define ASTRDUP(X) \ + (libiberty_optr = (X), \ + libiberty_len = strlen (libiberty_optr) + 1, \ + libiberty_nptr = (char *) alloca (libiberty_len), \ + (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len)) +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* ! defined (LIBIBERTY_H) */ diff --git a/external/gpl3/gdb/dist/include/lto-symtab.h b/external/gpl3/gdb/dist/include/lto-symtab.h new file mode 100644 index 000000000000..9312c5d9d33a --- /dev/null +++ b/external/gpl3/gdb/dist/include/lto-symtab.h @@ -0,0 +1,41 @@ +/* Data types used in the IL symbol table. + Copyright (C) 2009 Free Software Foundation, Inc. + Contributed by Rafael Espindola + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef GCC_LTO_SYMTAB_H +#define GCC_LTO_SYMTAB_H + +enum gcc_plugin_symbol_kind + { + GCCPK_DEF, + GCCPK_WEAKDEF, + GCCPK_UNDEF, + GCCPK_WEAKUNDEF, + GCCPK_COMMON + }; + +enum gcc_plugin_symbol_visibility + { + GCCPV_DEFAULT, + GCCPV_PROTECTED, + GCCPV_INTERNAL, + GCCPV_HIDDEN + }; + +#endif /* GCC_LTO_SYMTAB_H */ diff --git a/external/gpl3/gdb/dist/include/md5.h b/external/gpl3/gdb/dist/include/md5.h new file mode 100644 index 000000000000..b3ff4e14538d --- /dev/null +++ b/external/gpl3/gdb/dist/include/md5.h @@ -0,0 +1,149 @@ +/* md5.h - Declaration of functions and data types used for MD5 sum + computing library functions. + Copyright 1995, 1996, 2000 Free Software Foundation, Inc. + NOTE: The canonical source of this file is maintained with the GNU C + Library. Bugs can be reported to bug-glibc@prep.ai.mit.edu. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _MD5_H +#define _MD5_H 1 + +#include + +#if defined HAVE_LIMITS_H || _LIBC +# include +#endif + +#include "ansidecl.h" + +/* The following contortions are an attempt to use the C preprocessor + to determine an unsigned integral type that is 32 bits wide. An + alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but + doing that would require that the configure script compile and *run* + the resulting executable. Locally running cross-compiled executables + is usually not possible. */ + +#ifdef _LIBC +# include +typedef u_int32_t md5_uint32; +typedef uintptr_t md5_uintptr; +#else +# define INT_MAX_32_BITS 2147483647 + +/* If UINT_MAX isn't defined, assume it's a 32-bit type. + This should be valid for all systems GNU cares about because + that doesn't include 16-bit systems, and only modern systems + (that certainly have ) have 64+-bit integral types. */ + +# ifndef INT_MAX +# define INT_MAX INT_MAX_32_BITS +# endif + +# if INT_MAX == INT_MAX_32_BITS + typedef unsigned int md5_uint32; +# else +# if SHRT_MAX == INT_MAX_32_BITS + typedef unsigned short md5_uint32; +# else +# if LONG_MAX == INT_MAX_32_BITS + typedef unsigned long md5_uint32; +# else + /* The following line is intended to evoke an error. + Using #error is not portable enough. */ + "Cannot determine unsigned 32-bit data type." +# endif +# endif +# endif +/* We have to make a guess about the integer type equivalent in size + to pointers which should always be correct. */ +typedef unsigned long int md5_uintptr; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Structure to save state of computation between the single steps. */ +struct md5_ctx +{ + md5_uint32 A; + md5_uint32 B; + md5_uint32 C; + md5_uint32 D; + + md5_uint32 total[2]; + md5_uint32 buflen; + char buffer[128] ATTRIBUTE_ALIGNED_ALIGNOF(md5_uint32); +}; + +/* + * The following three functions are build up the low level used in + * the functions `md5_stream' and `md5_buffer'. + */ + +/* Initialize structure containing state of computation. + (RFC 1321, 3.3: Step 3) */ +extern void md5_init_ctx (struct md5_ctx *ctx); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is necessary that LEN is a multiple of 64!!! */ +extern void md5_process_block (const void *buffer, size_t len, + struct md5_ctx *ctx); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is NOT required that LEN is a multiple of 64. */ +extern void md5_process_bytes (const void *buffer, size_t len, + struct md5_ctx *ctx); + +/* Process the remaining bytes in the buffer and put result from CTX + in first 16 bytes following RESBUF. The result is always in little + endian byte order, so that a byte-wise output yields to the wanted + ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_finish_ctx (struct md5_ctx *ctx, void *resbuf); + + +/* Put result from CTX in first 16 bytes following RESBUF. The result is + always in little endian byte order, so that a byte-wise output yields + to the wanted ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_read_ctx (const struct md5_ctx *ctx, void *resbuf); + + +/* Compute MD5 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 16 bytes + beginning at RESBLOCK. */ +extern int md5_stream (FILE *stream, void *resblock); + +/* Compute MD5 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +extern void *md5_buffer (const char *buffer, size_t len, void *resblock); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/nlm/ChangeLog b/external/gpl3/gdb/dist/include/nlm/ChangeLog new file mode 100644 index 000000000000..e5ad952be94e --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/ChangeLog @@ -0,0 +1,110 @@ +2010-04-15 Nick Clifton + + * alpha-ext.h: Update copyright notice to use GPLv3. + * common.h: Likewise. + * external.h: Likewise. + * i386-ext.h: Likewise. + * internal.h: Likewise. + * ppc-ext.h: Likewise. + * sparc32-ext.h: Likewise. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + alpha-ext.h, common.h, external.h, i386-ext.h, internal.h, + ppc-ext.h, sparc32-ext.h + +2003-08-07 Alan Modra + + * internal.h (Nlm_Internal_Custom_Header): Replace PTR with void *. + +2001-10-02 Alan Modra + + * common.h (NLM_CAT, NLM_CAT3): Don't define. + (NLM_CAT4): Update conditions under which this is defined. Document + why CONCAT4 can't be used. + +1994-05-06 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (nlmNAME(External_Custom_Header)): Add length, + dataOffset, and dataStamp field. + (nlmNAME(External_Cygnus_Ext_Header)): Remove. + * internal.h (Nlm_Internal_Custom_Header): Add hdrLength, + dataOffset, dataStamp and hdr fields. + +1994-04-22 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (struct nlmNAME(external_cygnus_ext_header)): Rename + from nlmNAME(external_cygnus_section_header). Change stamp field + to 8 bytes. Add bytes field. + * internal.h (nlm_internal_cygnus_ext_header): Rename from + nlm_internal_cygnus_section_header. Change stamp field to 8 + bytes. + +1994-04-21 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_cygnus_section_header): Define. + * external.h (struct nlmNAME(external_cygnus_section_header): + Define. + +1994-04-20 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_custom_header): Remove + debugRecOffset and debugRecLength fields. Add data field. + * external.h (struct nlmNAME(external_custom_header)): Remove + debugRecOffset and debugRecLength fields. + +1994-02-07 Jim Kingdon (kingdon@lioth.cygnus.com) + + * internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT. + +1993-12-02 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha-ext.h: New file describing formats of information in Alpha + NetWare files. + * common.h: Define some non-external Alpha information. + +1993-11-17 Sean Eric Fagan (sef@cygnus.com) + + * external.h: Don't define external_fixed_header here. + * i386-ext.h, sparc32-ext.h: New header files to define + external_fixed_header for particular CPU's. + +1993-10-27 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (Nlm_Internal_Extended_Header): Added fields + sharedDebugRecordOffset and sharedDebugRecordCount. + * external.h (NlmNAME(External_Extended_Header)): Likewise. + + * common.h (NLM_SIGNATURE): Do not define (it's different for each + backend). + +1993-08-31 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h: Change length fields of type char to type unsigned + char. + +1993-07-31 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (NLM_HIBIT, NLM_HEADER_VERSION): Define. + +1993-07-22 Fred Fish (fnf@deneb.cygnus.com) + + * common.h (NLM_CAT*, NLM_ARCH_SIZE, NLM_TARGET_LONG_SIZE, + NLM_TARGET_ADDRESS_SIZE, NLM_NAME, NlmNAME, nlmNAME): New + macros. + * external.h (TARGET_LONG_SIZE, TARGET_ADDRESS_SIZE): Remove + macros, convert usages to NLM_ equivalents. + * external.h: Use nlmNAME and NlmNAME macros to derive both + 32 and 64 bit versions. + +1993-07-20 Fred Fish (fnf@deneb.cygnus.com) + + * (common.h, external.h, internal.h): New files for NLM/NetWare + support. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/nlm/alpha-ext.h b/external/gpl3/gdb/dist/include/nlm/alpha-ext.h new file mode 100644 index 000000000000..7dc65688f20e --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/alpha-ext.h @@ -0,0 +1,167 @@ +/* Alpha NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2005, 2010 Free Software Foundation, Inc. + By Ian Lance Taylor, Cygnus Support + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* An Alpha NLM starts with an instance of this structure. */ + +struct nlm32_alpha_external_prefix_header +{ + /* Magic number. Must be NLM32_ALPHA_MAGIC. */ + unsigned char magic[4]; + /* Format descriptor. Current value is 2. */ + unsigned char format[4]; + /* Size of prefix header. */ + unsigned char size[4]; + /* Padding. */ + unsigned char pad1[4]; + /* More fields may be added later, supposedly. */ +}; + +/* The external format of an Alpha NLM reloc. This is the same as an + Alpha ECOFF reloc. */ + +struct nlm32_alpha_external_reloc +{ + unsigned char r_vaddr[8]; + unsigned char r_symndx[4]; + unsigned char r_bits[4]; +}; + +/* Constants to unpack the r_bits field of a reloc. */ + +#define RELOC_BITS0_TYPE_LITTLE 0xff +#define RELOC_BITS0_TYPE_SH_LITTLE 0 + +#define RELOC_BITS1_EXTERN_LITTLE 0x01 + +#define RELOC_BITS1_OFFSET_LITTLE 0x7e +#define RELOC_BITS1_OFFSET_SH_LITTLE 1 + +#define RELOC_BITS1_RESERVED_LITTLE 0x80 +#define RELOC_BITS1_RESERVED_SH_LITTLE 7 +#define RELOC_BITS2_RESERVED_LITTLE 0xff +#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 +#define RELOC_BITS3_RESERVED_LITTLE 0x03 +#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 + +#define RELOC_BITS3_SIZE_LITTLE 0xfc +#define RELOC_BITS3_SIZE_SH_LITTLE 2 + +/* The external format of the fixed header. */ + +typedef struct nlm32_alpha_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_alpha_External_Fixed_Header; diff --git a/external/gpl3/gdb/dist/include/nlm/common.h b/external/gpl3/gdb/dist/include/nlm/common.h new file mode 100644 index 000000000000..fcd290e0c7a2 --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/common.h @@ -0,0 +1,123 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2001, 2005, 2010 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of NLM support for BFD, and contains the portions + that are common to both the internal and external representations. */ + +/* If NLM_ARCH_SIZE is not defined, default to 32. NLM_ARCH_SIZE is + optionally defined by the application. */ + +#ifndef NLM_ARCH_SIZE +# define NLM_ARCH_SIZE 32 +#endif + +/* Due to horrible details of ANSI macro expansion, we can't use CONCAT4 + for NLM_NAME. CONCAT2 is used in BFD_JUMP_TABLE macros, and some of + them will expand to tokens that themselves are macros defined in terms + of NLM_NAME. If NLM_NAME were defined using CONCAT4 (which is itself + defined in bfd-in.h using CONCAT2), ANSI preprocessor rules say that + the CONCAT2 within NLM_NAME should not be expanded. + So use another name. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#ifdef SABER +#define NLM_CAT4(a,b,c,d) a##b##c##d +#else +/* This hack is to avoid a problem with some strict ANSI C preprocessors. + The problem is, "32_" is not a valid preprocessing token, and we don't + want extra underscores (e.g., "nlm_32_"). The NLM_XCAT2 macro will + cause the inner CAT2 macros to be evaluated first, producing + still-valid pp-tokens. Then the final concatenation can be done. */ +#define NLM_CAT2(a,b) a##b +#define NLM_XCAT2(a,b) NLM_CAT2(a,b) +#define NLM_CAT4(a,b,c,d) NLM_XCAT2(NLM_CAT2(a,b),NLM_CAT2(c,d)) +#endif +#else +#define NLM_CAT4(a,b,c,d) a/**/b/**/c/**/d +#endif + +#if NLM_ARCH_SIZE == 32 +# define NLM_TARGET_LONG_SIZE 4 +# define NLM_TARGET_ADDRESS_SIZE 4 +# define NLM_NAME(x,y) NLM_CAT4(x,32,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 31) +#endif +#if NLM_ARCH_SIZE == 64 +# define NLM_TARGET_LONG_SIZE 8 +# define NLM_TARGET_ADDRESS_SIZE 8 +# define NLM_NAME(x,y) NLM_CAT4(x,64,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 63) +#endif + +#define NlmNAME(X) NLM_NAME(Nlm,X) +#define nlmNAME(X) NLM_NAME(nlm,X) + +/* Give names to things that should not change. */ + +#define NLM_MAX_DESCRIPTION_LENGTH 127 +#define NLM_MAX_SCREEN_NAME_LENGTH 71 +#define NLM_MAX_THREAD_NAME_LENGTH 71 +#define NLM_MAX_COPYRIGHT_MESSAGE_LENGTH 255 +#define NLM_OTHER_DATA_LENGTH 400 /* FIXME */ +#define NLM_OLD_THREAD_NAME_LENGTH 5 +#define NLM_SIGNATURE_SIZE 24 +#define NLM_HEADER_VERSION 4 +#define NLM_MODULE_NAME_SIZE 14 +#define NLM_DEFAULT_STACKSIZE (8 * 1024) + +/* Alpha information. This should probably be in a separate Alpha + header file, but it can't go in alpha-ext.h because some of it is + needed by nlmconv.c. */ + +/* Magic number in Alpha prefix header. */ +#define NLM32_ALPHA_MAGIC (0x83561840) + +/* The r_type field in an Alpha reloc is one of the following values. */ +#define ALPHA_R_IGNORE 0 +#define ALPHA_R_REFLONG 1 +#define ALPHA_R_REFQUAD 2 +#define ALPHA_R_GPREL32 3 +#define ALPHA_R_LITERAL 4 +#define ALPHA_R_LITUSE 5 +#define ALPHA_R_GPDISP 6 +#define ALPHA_R_BRADDR 7 +#define ALPHA_R_HINT 8 +#define ALPHA_R_SREL16 9 +#define ALPHA_R_SREL32 10 +#define ALPHA_R_SREL64 11 +#define ALPHA_R_OP_PUSH 12 +#define ALPHA_R_OP_STORE 13 +#define ALPHA_R_OP_PSUB 14 +#define ALPHA_R_OP_PRSHIFT 15 +#define ALPHA_R_GPVALUE 16 +#define ALPHA_R_NW_RELOC 250 + +/* A local reloc, other than ALPHA_R_GPDISP or ALPHA_R_IGNORE, must be + against one of these symbol indices. */ +#define ALPHA_RELOC_SECTION_TEXT 1 +#define ALPHA_RELOC_SECTION_DATA 3 + +/* An ALPHA_R_NW_RELOC has one of these values in the size field. If + it is SETGP, the r_vaddr field holds the GP value to use. If it is + LITA, the r_vaddr field holds the address of the .lita section and + the r_symndx field holds the size of the .lita section. */ +#define ALPHA_R_NW_RELOC_SETGP 1 +#define ALPHA_R_NW_RELOC_LITA 2 diff --git a/external/gpl3/gdb/dist/include/nlm/external.h b/external/gpl3/gdb/dist/include/nlm/external.h new file mode 100644 index 000000000000..eebd1cca9253 --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/external.h @@ -0,0 +1,172 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994, 2005, 2010 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented externally by the BFD library. + I.E. it describes the in-file representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. + + Note that an NLM header consists of three parts: + + (1) A fixed length header that has specific fields of known length, + at specific offsets in the file. + + (2) A variable length header that has specific fields in a specific + order, but some fields may be variable length. + + (3) A auxiliary header that has various optional fields in no specific + order. There is no way to identify the end of the auxiliary headers + except by finding a header without a recognized 'stamp'. + + The exact format of the fixed length header unfortunately varies + from one NLM target to another, due to padding. Each target + defines the correct external format in a separate header file. */ + +/* NLM Header. */ + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlmNAME(external_version_header) +{ + + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + + unsigned char majorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char minorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char revision[NLM_TARGET_LONG_SIZE]; + + unsigned char year[NLM_TARGET_LONG_SIZE]; + + unsigned char month[NLM_TARGET_LONG_SIZE]; + + unsigned char day[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Version_Header); + + +typedef struct nlmNAME(external_copyright_header) +{ + + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + + char stamp[10]; + + unsigned char copyrightMessageLength[1]; + + /* There is a variable length field here called 'copyrightMessage' + that is the length specified by copyrightMessageLength. */ + +} NlmNAME(External_Copyright_Header); + + +typedef struct nlmNAME(external_extended_header) +{ + + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + + char stamp[8]; + + unsigned char languageID[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char messageCount[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedInitializationOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char SharedExitProcedureOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char productID[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved0[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved1[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved2[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved3[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved4[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved5[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Extended_Header); + + +typedef struct nlmNAME(external_custom_header) +{ + + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + + /* Length of this header. */ + unsigned char length[NLM_TARGET_LONG_SIZE]; + + /* Offset to data. */ + unsigned char dataOffset[NLM_TARGET_LONG_SIZE]; + + /* Length of data. */ + unsigned char dataLength[NLM_TARGET_LONG_SIZE]; + + /* Stamp for this customer header--we recognize "CyGnUsEx". */ + char dataStamp[8]; + +} NlmNAME(External_Custom_Header); diff --git a/external/gpl3/gdb/dist/include/nlm/i386-ext.h b/external/gpl3/gdb/dist/include/nlm/i386-ext.h new file mode 100644 index 000000000000..4de8b340d412 --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/i386-ext.h @@ -0,0 +1,117 @@ +/* i386 NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2005, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_i386_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_i386_External_Fixed_Header; diff --git a/external/gpl3/gdb/dist/include/nlm/internal.h b/external/gpl3/gdb/dist/include/nlm/internal.h new file mode 100644 index 000000000000..51e1f00e9809 --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/internal.h @@ -0,0 +1,309 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994, 2003, 2005, 2010 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented internally in the BFD library. + I.E. it describes the in-memory representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. */ + +#if 0 + +/* Types used by various structures, functions, etc. */ + +typedef unsigned long Nlm32_Addr; /* Unsigned program address */ +typedef unsigned long Nlm32_Off; /* Unsigned file offset */ +typedef long Nlm32_Sword; /* Signed large integer */ +typedef unsigned long Nlm32_Word; /* Unsigned large integer */ +typedef unsigned short Nlm32_Half; /* Unsigned medium integer */ +typedef unsigned char Nlm32_Char; /* Unsigned tiny integer */ + +#ifdef BFD_HOST_64_BIT +typedef unsigned BFD_HOST_64_BIT Nlm64_Addr; +typedef unsigned BFD_HOST_64_BIT Nlm64_Off; +typedef BFD_HOST_64_BIT Nlm64_Sxword; +typedef unsigned BFD_HOST_64_BIT Nlm64_Xword; +#endif +typedef long Nlm64_Sword; +typedef unsigned long Nlm64_Word; +typedef unsigned short Nlm64_Half; + +#endif /* 0 */ + +/* This structure contains the internal form of the portion of the NLM + header that is fixed length. */ + +typedef struct nlm_internal_fixed_header +{ + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + char signature[NLM_SIGNATURE_SIZE]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + long version; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension. The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + char moduleName[NLM_MODULE_NAME_SIZE]; + + /* The byte offset of the code image from the start of the file. */ + + file_ptr codeImageOffset; + + /* The size of the code image, in bytes. */ + + bfd_size_type codeImageSize; + + /* The byte offset of the data image from the start of the file. */ + + file_ptr dataImageOffset; + + /* The size of the data image, in bytes. */ + + bfd_size_type dataImageSize; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + bfd_size_type uninitializedDataSize; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. */ + + file_ptr customDataOffset; + + /* The size of the custom data, in bytes. */ + + bfd_size_type customDataSize; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + file_ptr moduleDependencyOffset; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + long numberOfModuleDependencies; + + /* The byte offset of the relocation fixup data from the start of the file */ + + file_ptr relocationFixupOffset; + long numberOfRelocationFixups; + file_ptr externalReferencesOffset; + long numberOfExternalReferences; + file_ptr publicsOffset; + long numberOfPublics; + file_ptr debugInfoOffset; + long numberOfDebugRecords; + file_ptr codeStartOffset; + file_ptr exitProcedureOffset; + file_ptr checkUnloadProcedureOffset; + long moduleType; + long flags; +} Nlm_Internal_Fixed_Header; + +#define nlm32_internal_fixed_header nlm_internal_fixed_header +#define Nlm32_Internal_Fixed_Header Nlm_Internal_Fixed_Header +#define nlm64_internal_fixed_header nlm_internal_fixed_header +#define Nlm64_Internal_Fixed_Header Nlm_Internal_Fixed_Header + +/* This structure contains the portions of the NLM header that are either + variable in size in the external representation, or else are not at a + fixed offset relative to the start of the NLM header due to preceding + variable sized fields. + + Note that all the fields must exist in the external header, and in + the order used here (the same order is used in the internal form + for consistency, not out of necessity). */ + +typedef struct nlm_internal_variable_header +{ + + /* The descriptionLength field contains the length of the text in + descriptionText, excluding the null terminator. The descriptionText + field contains the NLM description obtained from the DESCRIPTION + keyword in NLMLINK plus the null byte terminator. The descriptionText + can be up to NLM_MAX_DESCRIPTION_LENGTH characters. */ + + unsigned char descriptionLength; + char descriptionText[NLM_MAX_DESCRIPTION_LENGTH + 1]; + + /* The stackSize field contains the size of the stack in bytes, as + specified by the STACK or STACKSIZE keyword in NLMLINK. If no size + is specified, the default is NLM_DEFAULT_STACKSIZE. */ + + long stackSize; + + /* The reserved field is included only for completeness. It should contain + zero. */ + + long reserved; + + /* This field is fixed length, should contain " LONG" (note leading + space), and is unused. */ + + char oldThreadName[NLM_OLD_THREAD_NAME_LENGTH]; + + /* The screenNameLength field contains the length of the actual text stored + in the screenName field, excluding the null byte terminator. The + screenName field contains the screen name as specified by the SCREENNAME + keyword in NLMLINK, and can be up to NLM_MAX_SCREEN_NAME_LENGTH + characters. */ + + unsigned char screenNameLength; + char screenName[NLM_MAX_SCREEN_NAME_LENGTH + 1]; + + /* The threadNameLength field contains the length of the actual text stored + in the threadName field, excluding the null byte terminator. The + threadName field contains the thread name as specified by the THREADNAME + keyword in NLMLINK, and can be up to NLM_MAX_THREAD_NAME_LENGTH + characters. */ + + unsigned char threadNameLength; + char threadName[NLM_MAX_THREAD_NAME_LENGTH + 1]; + +} Nlm_Internal_Variable_Header; + +#define nlm32_internal_variable_header nlm_internal_variable_header +#define Nlm32_Internal_Variable_Header Nlm_Internal_Variable_Header +#define nlm64_internal_variable_header nlm_internal_variable_header +#define Nlm64_Internal_Variable_Header Nlm_Internal_Variable_Header + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlm_internal_version_header +{ + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + long majorVersion; + long minorVersion; + long revision; + long year; + long month; + long day; +} Nlm_Internal_Version_Header; + +#define nlm32_internal_version_header nlm_internal_version_header +#define Nlm32_Internal_Version_Header Nlm_Internal_Version_Header +#define nlm64_internal_version_header nlm_internal_version_header +#define Nlm64_Internal_Version_Header Nlm_Internal_Version_Header + +typedef struct nlm_internal_copyright_header +{ + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + char stamp[10]; + unsigned char copyrightMessageLength; + char copyrightMessage[NLM_MAX_COPYRIGHT_MESSAGE_LENGTH]; +} Nlm_Internal_Copyright_Header; + +#define nlm32_internal_copyright_header nlm_internal_copyright_header +#define Nlm32_Internal_Copyright_Header Nlm_Internal_Copyright_Header +#define nlm64_internal_copyright_header nlm_internal_copyright_header +#define Nlm64_Internal_Copyright_Header Nlm_Internal_Copyright_Header + +typedef struct nlm_internal_extended_header +{ + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + char stamp[8]; + long languageID; + file_ptr messageFileOffset; + bfd_size_type messageFileLength; + long messageCount; + file_ptr helpFileOffset; + bfd_size_type helpFileLength; + file_ptr RPCDataOffset; + bfd_size_type RPCDataLength; + file_ptr sharedCodeOffset; + bfd_size_type sharedCodeLength; + file_ptr sharedDataOffset; + bfd_size_type sharedDataLength; + file_ptr sharedRelocationFixupOffset; + long sharedRelocationFixupCount; + file_ptr sharedExternalReferenceOffset; + long sharedExternalReferenceCount; + file_ptr sharedPublicsOffset; + long sharedPublicsCount; + file_ptr sharedDebugRecordOffset; + long sharedDebugRecordCount; + bfd_vma SharedInitializationOffset; + bfd_vma SharedExitProcedureOffset; + long productID; + long reserved0; + long reserved1; + long reserved2; + long reserved3; + long reserved4; + long reserved5; +} Nlm_Internal_Extended_Header; + +#define nlm32_internal_extended_header nlm_internal_extended_header +#define Nlm32_Internal_Extended_Header Nlm_Internal_Extended_Header +#define nlm64_internal_extended_header nlm_internal_extended_header +#define Nlm64_Internal_Extended_Header Nlm_Internal_Extended_Header + +/* The format of a custom header as stored internally is different + from the external format. This is how we store a custom header + which we do not recognize. */ + +typedef struct nlm_internal_custom_header +{ + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + bfd_size_type hdrLength; + file_ptr dataOffset; + bfd_size_type dataLength; + char dataStamp[8]; + void *hdr; +} Nlm_Internal_Custom_Header; + +#define nlm32_internal_custom_header nlm_internal_custom_header +#define Nlm32_Internal_Custom_Header Nlm_Internal_Custom_Header +#define nlm64_internal_custom_header nlm_internal_custom_header +#define Nlm64_Internal_Custom_Header Nlm_Internal_Custom_Header + +/* The internal Cygnus header is written out externally as a custom + header. We don't try to replicate that structure here. */ + +typedef struct nlm_internal_cygnus_ext_header +{ + /* The header is recognized by "CyGnUsEx" in the stamp field. */ + char stamp[8]; + /* File location of debugging information. */ + file_ptr offset; + /* Length of debugging information. */ + bfd_size_type length; +} Nlm_Internal_Cygnus_Ext_Header; + +#define nlm32_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm32_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header +#define nlm64_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm64_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header diff --git a/external/gpl3/gdb/dist/include/nlm/ppc-ext.h b/external/gpl3/gdb/dist/include/nlm/ppc-ext.h new file mode 100644 index 000000000000..026984b85d07 --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/ppc-ext.h @@ -0,0 +1,164 @@ +/* PowerPC NLM (NetWare Loadable Module) support for BFD. + Copyright (C) 1994, 2005, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifdef OLDFORMAT + +/* The format of a PowerPC NLM changed. These structures are only + used in the old format. */ + +/* A PowerPC NLM starts with an instance of this structure. */ + +struct nlm32_powerpc_external_prefix_header +{ + /* Signature. Must be "AppleNLM". */ + char signature[8]; + /* Version number. Current value is 1. */ + unsigned char headerVersion[4]; + /* ??. Should be set to 0. */ + unsigned char origins[4]; + /* File creation date in standard Unix time format (seconds since + 1/1/70). */ + unsigned char date[4]; +}; + +#define NLM32_POWERPC_SIGNATURE "AppleNLM" +#define NLM32_POWERPC_HEADER_VERSION 1 + +/* The external format of a PowerPC NLM reloc. This is the same as an + XCOFF dynamic reloc. */ + +struct nlm32_powerpc_external_reloc +{ + /* Address. */ + unsigned char l_vaddr[4]; + /* Symbol table index. This is 0 for .text and 1 for .data. 2 + means .bss, but I don't know if it is used. In XCOFF, larger + numbers are indices into the dynamic symbol table, but they are + presumably not used in an NLM. */ + unsigned char l_symndx[4]; + /* Relocation type. */ + unsigned char l_rtype[2]; + /* Section number being relocated. */ + unsigned char l_rsecnm[2]; +}; + +#endif /* OLDFORMAT */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_powerpc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_powerpc_External_Fixed_Header; diff --git a/external/gpl3/gdb/dist/include/nlm/sparc32-ext.h b/external/gpl3/gdb/dist/include/nlm/sparc32-ext.h new file mode 100644 index 000000000000..a5c78e34baea --- /dev/null +++ b/external/gpl3/gdb/dist/include/nlm/sparc32-ext.h @@ -0,0 +1,121 @@ +/* SPARC NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2005, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_sparc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_sparc_External_Fixed_Header; diff --git a/external/gpl3/gdb/dist/include/oasys.h b/external/gpl3/gdb/dist/include/oasys.h new file mode 100644 index 000000000000..92d5c266f3dd --- /dev/null +++ b/external/gpl3/gdb/dist/include/oasys.h @@ -0,0 +1,192 @@ +/* Oasys object format header file for BFD. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Contributed by Cygnus Support. */ + +#define OASYS_MAX_SEC_COUNT 16 +/* **** */ + +typedef struct oasys_archive_header + { + unsigned int version; + char create_date[12]; + char revision_date[12]; + unsigned int mod_count; + file_ptr mod_tbl_offset; + unsigned int sym_tbl_size; + unsigned int sym_count; + file_ptr sym_tbl_offset; + unsigned int xref_count; + file_ptr xref_lst_offset; + } +oasys_archive_header_type; + +typedef struct oasys_extarchive_header + { + bfd_byte version[4]; + bfd_byte create_date[12]; + bfd_byte revision_date[12]; + bfd_byte mod_count[4]; + bfd_byte mod_tbl_offset[4]; + bfd_byte sym_tbl_size[4]; + bfd_byte sym_count[4]; + bfd_byte sym_tbl_offset[4]; + bfd_byte xref_count[4]; + bfd_byte xref_lst_offset[4]; + } +oasys_extarchive_header_type; + +typedef struct oasys_module_table + { + int mod_number; + char mod_date[12]; + unsigned int mod_size; + unsigned int dep_count; + unsigned int depee_count; + file_ptr file_offset; + unsigned int sect_count; + char *module_name; + unsigned int module_name_size; + } +oasys_module_table_type; + +typedef struct oasys_extmodule_table_a + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name[32]; + } +oasys_extmodule_table_type_a_type; + +typedef struct oasys_extmodule_table_b + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name_length[4]; + } +oasys_extmodule_table_type_b_type; + +typedef enum oasys_record + { + oasys_record_is_end_enum = 0, + oasys_record_is_data_enum = 1, + oasys_record_is_symbol_enum = 2, + oasys_record_is_header_enum = 3, + oasys_record_is_named_section_enum = 4, + oasys_record_is_com_enum = 5, + oasys_record_is_debug_enum = 6, + oasys_record_is_section_enum = 7, + oasys_record_is_debug_file_enum = 8, + oasys_record_is_module_enum = 9, + oasys_record_is_local_enum = 10 + } +oasys_record_enum_type; + +typedef struct oasys_record_header + { + unsigned char length; + unsigned char check_sum; + unsigned char type; + unsigned char fill; + } +oasys_record_header_type; + +typedef struct oasys_data_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte addr[4]; + /* maximum total size of data record is 255 bytes */ + bfd_byte data[246]; + } +oasys_data_record_type; + +typedef struct oasys_header_record + { + oasys_record_header_type header; + unsigned char version_number; + unsigned char rev_number; + char module_name[26-6]; + char description[64-26]; + } +oasys_header_record_type; + +#define OASYS_VERSION_NUMBER 0 +#define OASYS_REV_NUMBER 0 + +typedef struct oasys_symbol_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte refno[2]; + char name[64]; + } +oasys_symbol_record_type; + +#define RELOCATION_PCREL_BIT 0x80 +#define RELOCATION_32BIT_BIT 0x40 +#define RELOCATION_TYPE_BITS 0x30 +#define RELOCATION_TYPE_ABS 0x00 +#define RELOCATION_TYPE_REL 0x10 +#define RELOCATION_TYPE_UND 0x20 +#define RELOCATION_TYPE_COM 0x30 +#define RELOCATION_SECT_BITS 0x0f + +typedef struct oasys_section_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte vma[4]; + bfd_byte fill[3]; + } +oasys_section_record_type; + +typedef struct oasys_end_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte entry[4]; + bfd_byte fill[2]; + bfd_byte zero; + } +oasys_end_record_type; + +typedef union oasys_record_union + { + oasys_record_header_type header; + oasys_data_record_type data; + oasys_section_record_type section; + oasys_symbol_record_type symbol; + oasys_header_record_type first; + oasys_end_record_type end; + bfd_byte pad[256]; + } +oasys_record_union_type; diff --git a/external/gpl3/gdb/dist/include/objalloc.h b/external/gpl3/gdb/dist/include/objalloc.h new file mode 100644 index 000000000000..36772d17b50d --- /dev/null +++ b/external/gpl3/gdb/dist/include/objalloc.h @@ -0,0 +1,115 @@ +/* objalloc.h -- routines to allocate memory for objects + Copyright 1997, 2001 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Solutions. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef OBJALLOC_H +#define OBJALLOC_H + +#include "ansidecl.h" + +/* These routines allocate space for an object. The assumption is + that the object will want to allocate space as it goes along, but + will never want to free any particular block. There is a function + to free a block, which also frees all more recently allocated + blocks. There is also a function to free all the allocated space. + + This is essentially a specialization of obstacks. The main + difference is that a block may not be allocated a bit at a time. + Another difference is that these routines are always built on top + of malloc, and always pass an malloc failure back to the caller, + unlike more recent versions of obstacks. */ + +/* This is what an objalloc structure looks like. Callers should not + refer to these fields, nor should they allocate these structure + themselves. Instead, they should only create them via + objalloc_init, and only access them via the functions and macros + listed below. The structure is only defined here so that we can + access it via macros. */ + +struct objalloc +{ + char *current_ptr; + unsigned int current_space; + void *chunks; +}; + +/* Work out the required alignment. */ + +struct objalloc_align { char x; double d; }; + +#if defined (__STDC__) && __STDC__ +#ifndef offsetof +#include +#endif +#endif +#ifndef offsetof +#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER) +#endif +#define OBJALLOC_ALIGN offsetof (struct objalloc_align, d) + +/* Create an objalloc structure. Returns NULL if malloc fails. */ + +extern struct objalloc *objalloc_create (void); + +/* Allocate space from an objalloc structure. Returns NULL if malloc + fails. */ + +extern void *_objalloc_alloc (struct objalloc *, unsigned long); + +/* The macro version of objalloc_alloc. We only define this if using + gcc, because otherwise we would have to evaluate the arguments + multiple times, or use a temporary field as obstack.h does. */ + +#if defined (__GNUC__) && defined (__STDC__) && __STDC__ + +/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and + does not implement __extension__. But that compiler doesn't define + __GNUC_MINOR__. */ +#if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) +#define __extension__ +#endif + +#define objalloc_alloc(o, l) \ + __extension__ \ + ({ struct objalloc *__o = (o); \ + unsigned long __len = (l); \ + if (__len == 0) \ + __len = 1; \ + __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); \ + (__len <= __o->current_space \ + ? (__o->current_ptr += __len, \ + __o->current_space -= __len, \ + (void *) (__o->current_ptr - __len)) \ + : _objalloc_alloc (__o, __len)); }) + +#else /* ! __GNUC__ */ + +#define objalloc_alloc(o, l) _objalloc_alloc ((o), (l)) + +#endif /* ! __GNUC__ */ + +/* Free an entire objalloc structure. */ + +extern void objalloc_free (struct objalloc *); + +/* Free a block allocated by objalloc_alloc. This also frees all more + recently allocated blocks. */ + +extern void objalloc_free_block (struct objalloc *, void *); + +#endif /* OBJALLOC_H */ diff --git a/external/gpl3/gdb/dist/include/obstack.h b/external/gpl3/gdb/dist/include/obstack.h new file mode 100644 index 000000000000..4aec3a484e2c --- /dev/null +++ b/external/gpl3/gdb/dist/include/obstack.h @@ -0,0 +1,545 @@ +/* obstack.h - object stack macros + Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, + 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008 + Free Software Foundation, Inc. + + + NOTE: The canonical source of this file is maintained with the GNU C Library. + Bugs can be reported to bug-glibc@gnu.org. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +/* Summary: + +All the apparent functions defined here are macros. The idea +is that you would use these pre-tested macros to solve a +very specific set of problems, and they would run fast. +Caution: no side-effects in arguments please!! They may be +evaluated MANY times!! + +These macros operate a stack of objects. Each object starts life +small, and may grow to maturity. (Consider building a word syllable +by syllable.) An object can move while it is growing. Once it has +been "finished" it never changes address again. So the "top of the +stack" is typically an immature growing object, while the rest of the +stack is of mature, fixed size and fixed address objects. + +These routines grab large chunks of memory, using a function you +supply, called `obstack_chunk_alloc'. On occasion, they free chunks, +by calling `obstack_chunk_free'. You must define them and declare +them before using any obstack macros. + +Each independent stack is represented by a `struct obstack'. +Each of the obstack macros expects a pointer to such a structure +as the first argument. + +One motivation for this package is the problem of growing char strings +in symbol tables. Unless you are "fascist pig with a read-only mind" +--Gosper's immortal quote from HAKMEM item 154, out of context--you +would not like to put any arbitrary upper limit on the length of your +symbols. + +In practice this often means you will build many short symbols and a +few long symbols. At the time you are reading a symbol you don't know +how long it is. One traditional method is to read a symbol into a +buffer, realloc()ating the buffer every time you try to read a symbol +that is longer than the buffer. This is beaut, but you still will +want to copy the symbol from the buffer to a more permanent +symbol-table entry say about half the time. + +With obstacks, you can work differently. Use one obstack for all symbol +names. As you read a symbol, grow the name in the obstack gradually. +When the name is complete, finalize it. Then, if the symbol exists already, +free the newly read name. + +The way we do this is to take a large chunk, allocating memory from +low addresses. When you want to build a symbol in the chunk you just +add chars above the current "high water mark" in the chunk. When you +have finished adding chars, because you got to the end of the symbol, +you know how long the chars are, and you can create a new object. +Mostly the chars will not burst over the highest address of the chunk, +because you would typically expect a chunk to be (say) 100 times as +long as an average object. + +In case that isn't clear, when we have enough chars to make up +the object, THEY ARE ALREADY CONTIGUOUS IN THE CHUNK (guaranteed) +so we just point to it where it lies. No moving of chars is +needed and this is the second win: potentially long strings need +never be explicitly shuffled. Once an object is formed, it does not +change its address during its lifetime. + +When the chars burst over a chunk boundary, we allocate a larger +chunk, and then copy the partly formed object from the end of the old +chunk to the beginning of the new larger chunk. We then carry on +accreting characters to the end of the object as we normally would. + +A special macro is provided to add a single char at a time to a +growing object. This allows the use of register variables, which +break the ordinary 'growth' macro. + +Summary: + We allocate large chunks. + We carve out one object at a time from the current chunk. + Once carved, an object never moves. + We are free to append data of any size to the currently + growing object. + Exactly one object is growing in an obstack at any one time. + You can run one obstack per control block. + You may have as many control blocks as you dare. + Because of the way we do it, you can `unwind' an obstack + back to a previous state. (You may remove objects much + as you would with a stack.) +*/ + + +/* Don't do the contents of this file more than once. */ + +#ifndef _OBSTACK_H +#define _OBSTACK_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* We use subtraction of (char *) 0 instead of casting to int + because on word-addressable machines a simple cast to int + may ignore the byte-within-word field of the pointer. */ + +#ifndef __PTR_TO_INT +# define __PTR_TO_INT(P) ((P) - (char *) 0) +#endif + +#ifndef __INT_TO_PTR +# define __INT_TO_PTR(P) ((P) + (char *) 0) +#endif + +/* We need the type of the resulting object. If __PTRDIFF_TYPE__ is + defined, as with GNU C, use that; that way we don't pollute the + namespace with 's symbols. Otherwise, if is + available, include it and use ptrdiff_t. In traditional C, long is + the best that we can do. */ + +#ifdef __PTRDIFF_TYPE__ +# define PTR_INT_TYPE __PTRDIFF_TYPE__ +#else +# ifdef HAVE_STDDEF_H +# include +# define PTR_INT_TYPE ptrdiff_t +# else +# define PTR_INT_TYPE long +# endif +#endif + +#if defined _LIBC || defined HAVE_STRING_H +# include +# define _obstack_memcpy(To, From, N) memcpy ((To), (From), (N)) +#else +# ifdef memcpy +# define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N)) +# else +# define _obstack_memcpy(To, From, N) bcopy ((char *)(From), (To), (N)) +# endif +#endif + +struct _obstack_chunk /* Lives at front of each chunk. */ +{ + char *limit; /* 1 past end of this chunk */ + struct _obstack_chunk *prev; /* address of prior chunk or NULL */ + char contents[4]; /* objects begin here */ +}; + +struct obstack /* control current object in current chunk */ +{ + long chunk_size; /* preferred size to allocate chunks in */ + struct _obstack_chunk *chunk; /* address of current struct obstack_chunk */ + char *object_base; /* address of object we are building */ + char *next_free; /* where to add next char to current object */ + char *chunk_limit; /* address of char after current chunk */ + PTR_INT_TYPE temp; /* Temporary for some macros. */ + int alignment_mask; /* Mask of alignment for each object. */ + /* These prototypes vary based on `use_extra_arg', and we use + casts to the prototypeless function type in all assignments, + but having prototypes here quiets -Wstrict-prototypes. */ + struct _obstack_chunk *(*chunkfun) (void *, long); + void (*freefun) (void *, struct _obstack_chunk *); + void *extra_arg; /* first arg for chunk alloc/dealloc funcs */ + unsigned use_extra_arg:1; /* chunk alloc/dealloc funcs take extra arg */ + unsigned maybe_empty_object:1;/* There is a possibility that the current + chunk contains a zero-length object. This + prevents freeing the chunk if we allocate + a bigger chunk to replace it. */ + unsigned alloc_failed:1; /* No longer used, as we now call the failed + handler on error, but retained for binary + compatibility. */ +}; + +/* Declare the external functions we use; they are in obstack.c. */ + +extern void _obstack_newchunk (struct obstack *, int); +extern void _obstack_free (struct obstack *, void *); +extern int _obstack_begin (struct obstack *, int, int, + void *(*) (long), void (*) (void *)); +extern int _obstack_begin_1 (struct obstack *, int, int, + void *(*) (void *, long), + void (*) (void *, void *), void *); +extern int _obstack_memory_used (struct obstack *); + +/* Do the function-declarations after the structs + but before defining the macros. */ + +void obstack_init (struct obstack *obstack); + +void * obstack_alloc (struct obstack *obstack, int size); + +void * obstack_copy (struct obstack *obstack, void *address, int size); +void * obstack_copy0 (struct obstack *obstack, void *address, int size); + +void obstack_free (struct obstack *obstack, void *block); + +void obstack_blank (struct obstack *obstack, int size); + +void obstack_grow (struct obstack *obstack, void *data, int size); +void obstack_grow0 (struct obstack *obstack, void *data, int size); + +void obstack_1grow (struct obstack *obstack, int data_char); +void obstack_ptr_grow (struct obstack *obstack, void *data); +void obstack_int_grow (struct obstack *obstack, int data); + +void * obstack_finish (struct obstack *obstack); + +int obstack_object_size (struct obstack *obstack); + +int obstack_room (struct obstack *obstack); +void obstack_make_room (struct obstack *obstack, int size); +void obstack_1grow_fast (struct obstack *obstack, int data_char); +void obstack_ptr_grow_fast (struct obstack *obstack, void *data); +void obstack_int_grow_fast (struct obstack *obstack, int data); +void obstack_blank_fast (struct obstack *obstack, int size); + +void * obstack_base (struct obstack *obstack); +void * obstack_next_free (struct obstack *obstack); +int obstack_alignment_mask (struct obstack *obstack); +int obstack_chunk_size (struct obstack *obstack); +int obstack_memory_used (struct obstack *obstack); + +/* Error handler called when `obstack_chunk_alloc' failed to allocate + more memory. This can be set to a user defined function. The + default action is to print a message and abort. */ +extern void (*obstack_alloc_failed_handler) (void); + +/* Exit value used when `print_and_abort' is used. */ +extern int obstack_exit_failure; + +/* Pointer to beginning of object being allocated or to be allocated next. + Note that this might not be the final address of the object + because a new chunk might be needed to hold the final size. */ + +#define obstack_base(h) ((h)->object_base) + +/* Size for allocating ordinary chunks. */ + +#define obstack_chunk_size(h) ((h)->chunk_size) + +/* Pointer to next byte not yet allocated in current chunk. */ + +#define obstack_next_free(h) ((h)->next_free) + +/* Mask specifying low bits that should be clear in address of an object. */ + +#define obstack_alignment_mask(h) ((h)->alignment_mask) + +/* To prevent prototype warnings provide complete argument list in + standard C version. */ +# define obstack_init(h) \ + _obstack_begin ((h), 0, 0, \ + (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) + +# define obstack_begin(h, size) \ + _obstack_begin ((h), (size), 0, \ + (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) + +# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ + _obstack_begin ((h), (size), (alignment), \ + (void *(*) (long)) (chunkfun), (void (*) (void *)) (freefun)) + +# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ + _obstack_begin_1 ((h), (size), (alignment), \ + (void *(*) (void *, long)) (chunkfun), \ + (void (*) (void *, void *)) (freefun), (arg)) + +# define obstack_chunkfun(h, newchunkfun) \ + ((h) -> chunkfun = (struct _obstack_chunk *(*)(void *, long)) (newchunkfun)) + +# define obstack_freefun(h, newfreefun) \ + ((h) -> freefun = (void (*)(void *, struct _obstack_chunk *)) (newfreefun)) + +#define obstack_1grow_fast(h,achar) (*((h)->next_free)++ = (achar)) + +#define obstack_blank_fast(h,n) ((h)->next_free += (n)) + +#define obstack_memory_used(h) _obstack_memory_used (h) + +#if defined __GNUC__ && defined __STDC__ && __STDC__ +/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and + does not implement __extension__. But that compiler doesn't define + __GNUC_MINOR__. */ +# if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) +# define __extension__ +# endif + +/* For GNU C, if not -traditional, + we can define these macros to compute all args only once + without using a global variable. + Also, we can avoid using the `temp' slot, to make faster code. */ + +# define obstack_object_size(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->next_free - __o->object_base); }) + +# define obstack_room(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (unsigned) (__o->chunk_limit - __o->next_free); }) + +# define obstack_make_room(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->chunk_limit - __o->next_free < __len) \ + _obstack_newchunk (__o, __len); \ + (void) 0; }) + +# define obstack_empty_p(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (__o->chunk->prev == 0 && __o->next_free - __o->chunk->contents == 0); }) + +# define obstack_grow(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->next_free + __len > __o->chunk_limit) \ + _obstack_newchunk (__o, __len); \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ + (void) 0; }) + +# define obstack_grow0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->next_free + __len + 1 > __o->chunk_limit) \ + _obstack_newchunk (__o, __len + 1); \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ + *(__o->next_free)++ = 0; \ + (void) 0; }) + +# define obstack_1grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + 1 > __o->chunk_limit) \ + _obstack_newchunk (__o, 1); \ + obstack_1grow_fast (__o, datum); \ + (void) 0; }) + +/* These assume that the obstack alignment is good enough for pointers or ints, + and that the data added so far to the current object + shares that much alignment. */ + +# define obstack_ptr_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + sizeof (void *) > __o->chunk_limit) \ + _obstack_newchunk (__o, sizeof (void *)); \ + obstack_ptr_grow_fast (__o, datum); }) + +# define obstack_int_grow(OBSTACK,datum) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + if (__o->next_free + sizeof (int) > __o->chunk_limit) \ + _obstack_newchunk (__o, sizeof (int)); \ + obstack_int_grow_fast (__o, datum); }) + +# define obstack_ptr_grow_fast(OBSTACK,aptr) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + *(const void **) __o1->next_free = (aptr); \ + __o1->next_free += sizeof (const void *); \ + (void) 0; }) + +# define obstack_int_grow_fast(OBSTACK,aint) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + *(int *) __o1->next_free = (aint); \ + __o1->next_free += sizeof (int); \ + (void) 0; }) + +# define obstack_blank(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->chunk_limit - __o->next_free < __len) \ + _obstack_newchunk (__o, __len); \ + obstack_blank_fast (__o, __len); \ + (void) 0; }) + +# define obstack_alloc(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_blank (__h, (length)); \ + obstack_finish (__h); }) + +# define obstack_copy(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow (__h, (where), (length)); \ + obstack_finish (__h); }) + +# define obstack_copy0(OBSTACK,where,length) \ +__extension__ \ +({ struct obstack *__h = (OBSTACK); \ + obstack_grow0 (__h, (where), (length)); \ + obstack_finish (__h); }) + +/* The local variable is named __o1 to avoid a name conflict + when obstack_blank is called. */ +# define obstack_finish(OBSTACK) \ +__extension__ \ +({ struct obstack *__o1 = (OBSTACK); \ + void *value; \ + value = (void *) __o1->object_base; \ + if (__o1->next_free == value) \ + __o1->maybe_empty_object = 1; \ + __o1->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\ + & ~ (__o1->alignment_mask)); \ + if (__o1->next_free - (char *)__o1->chunk \ + > __o1->chunk_limit - (char *)__o1->chunk) \ + __o1->next_free = __o1->chunk_limit; \ + __o1->object_base = __o1->next_free; \ + value; }) + +# define obstack_free(OBSTACK, OBJ) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + void *__obj = (void *) (OBJ); \ + if (__obj > (void *)__o->chunk && __obj < (void *)__o->chunk_limit) \ + __o->next_free = __o->object_base = (char *) __obj; \ + else (obstack_free) (__o, __obj); }) + +#else /* not __GNUC__ or not __STDC__ */ + +# define obstack_object_size(h) \ + (unsigned) ((h)->next_free - (h)->object_base) + +# define obstack_room(h) \ + (unsigned) ((h)->chunk_limit - (h)->next_free) + +# define obstack_empty_p(h) \ + ((h)->chunk->prev == 0 && (h)->next_free - (h)->chunk->contents == 0) + +/* Note that the call to _obstack_newchunk is enclosed in (..., 0) + so that we can avoid having void expressions + in the arms of the conditional expression. + Casting the third operand to void was tried before, + but some compilers won't accept it. */ + +# define obstack_make_room(h,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0)) + +# define obstack_grow(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ + (h)->next_free += (h)->temp) + +# define obstack_grow0(h,where,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp + 1), 0) : 0), \ + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ + (h)->next_free += (h)->temp, \ + *((h)->next_free)++ = 0) + +# define obstack_1grow(h,datum) \ +( (((h)->next_free + 1 > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), 1), 0) : 0), \ + obstack_1grow_fast (h, datum)) + +# define obstack_ptr_grow(h,datum) \ +( (((h)->next_free + sizeof (char *) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (char *)), 0) : 0), \ + obstack_ptr_grow_fast (h, datum)) + +# define obstack_int_grow(h,datum) \ +( (((h)->next_free + sizeof (int) > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), sizeof (int)), 0) : 0), \ + obstack_int_grow_fast (h, datum)) + +# define obstack_ptr_grow_fast(h,aptr) \ + (((const void **) ((h)->next_free += sizeof (void *)))[-1] = (aptr)) + +# define obstack_int_grow_fast(h,aint) \ + (((int *) ((h)->next_free += sizeof (int)))[-1] = (aptr)) + +# define obstack_blank(h,length) \ +( (h)->temp = (length), \ + (((h)->chunk_limit - (h)->next_free < (h)->temp) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ + obstack_blank_fast (h, (h)->temp)) + +# define obstack_alloc(h,length) \ + (obstack_blank ((h), (length)), obstack_finish ((h))) + +# define obstack_copy(h,where,length) \ + (obstack_grow ((h), (where), (length)), obstack_finish ((h))) + +# define obstack_copy0(h,where,length) \ + (obstack_grow0 ((h), (where), (length)), obstack_finish ((h))) + +# define obstack_finish(h) \ +( ((h)->next_free == (h)->object_base \ + ? (((h)->maybe_empty_object = 1), 0) \ + : 0), \ + (h)->temp = __PTR_TO_INT ((h)->object_base), \ + (h)->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT ((h)->next_free)+(h)->alignment_mask) \ + & ~ ((h)->alignment_mask)), \ + (((h)->next_free - (char *) (h)->chunk \ + > (h)->chunk_limit - (char *) (h)->chunk) \ + ? ((h)->next_free = (h)->chunk_limit) : 0), \ + (h)->object_base = (h)->next_free, \ + (void *) __INT_TO_PTR ((h)->temp)) + +# define obstack_free(h,obj) \ +( (h)->temp = (char *) (obj) - (char *) (h)->chunk, \ + (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ + ? (int) ((h)->next_free = (h)->object_base \ + = (h)->temp + (char *) (h)->chunk) \ + : (((obstack_free) ((h), (h)->temp + (char *) (h)->chunk), 0), 0))) + +#endif /* not __GNUC__ or not __STDC__ */ + +#ifdef __cplusplus +} /* C++ */ +#endif + +#endif /* obstack.h */ diff --git a/external/gpl3/gdb/dist/include/opcode/ChangeLog b/external/gpl3/gdb/dist/include/opcode/ChangeLog new file mode 100644 index 000000000000..fe8506931ef4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/ChangeLog @@ -0,0 +1,1191 @@ +2011-03-22 Eric B. Weddington + + * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): + New instruction set flags. + (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. + +2011-02-28 Maciej W. Rozycki + + * mips.h (M_PREF_AB): New enum value. + +2011-02-12 Mike Frysinger + + * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, + M_IU): Define. + (is_macmod_pmove, is_macmod_hmove): New functions. + +2011-02-11 Mike Frysinger + + * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. + +2011-02-04 Bernd Schmidt + + * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. + * tic6x.h (TIC6X_INSN_ATOMIC): Remove. + +2010-12-31 John David Anglin + + PR gas/11395 + * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit + "bb" entries. + +2010-12-26 John David Anglin + + PR gas/11395 + * hppa.h: Clear "d" bit in "add" and "sub" patterns. + +2010-12-18 Richard Sandiford + + * mips.h: Update commentary after last commit. + +2010-12-18 Mingjie Xing + + * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) + (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) + (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. + +2010-11-23 Richard Sandiford + + * mips.h: Fix previous commit. + +2010-11-23 Maciej W. Rozycki + + * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. + (INSN_LOONGSON_3A): Clear bit 31. + +2010-11-15 Matthew Gretton-Dann + + PR gas/12198 + * arm.h (ARM_AEXT_V6M_ONLY): New define. + (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. + (ARM_ARCH_V6M_ONLY): New define. + +2010-11-11 Mingming Sun + + * mips.h (INSN_LOONGSON_3A): Defined. + (CPU_LOONGSON_3A): Defined. + (OPCODE_IS_MEMBER): Add LOONGSON_3A. + +2010-10-09 Matt Rice + + * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. + (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. + +2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_VIRT): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... + (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization + Extensions. + +2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_AEXT_ADIV): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. + +2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_OS): New define. + (ARM_AEXT_V6SM): Likewise. + (ARM_ARCH_V6SM): Likewise. + +2010-09-23 Matthew Gretton-Dann + + * arm.h (ARM_EXT_MP): Add. + (ARM_ARCH_V7A_MP): Likewise. + +2010-09-22 Mike Frysinger + + * bfin.h: Declare pseudoChr structs/defines. + +2010-09-21 Mike Frysinger + + * bfin.h: Strip trailing whitespace. + +2010-07-29 DJ Delorie + + * rx.h (RX_Operand_Type): Add TwoReg. + (RX_Opcode_ID): Remove ediv and ediv2. + +2010-07-27 DJ Delorie + + * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. + +2010-07-23 Naveen.H.S + Ina Pandit + + * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, + PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and + PROCESSOR_V850E2_ALL. + Remove PROCESSOR_V850EA support. + (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, + V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, + V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, + V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, + V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and + V850_OPERAND_PERCENT. + Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and + V850_NOT_R0. + Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP + and V850E_PUSH_POP + +2010-07-06 Maciej W. Rozycki + + * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. + (MIPS16_INSN_BRANCH): Rename to... + (MIPS16_INSN_COND_BRANCH): ... this. + +2010-07-03 Alan Modra + + * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. + Renumber other PPC_OPCODE defines. + +2010-07-03 Alan Modra + + * ppc.h (PPC_OPCODE_COMMON): Expand comment. + +2010-06-29 Alan Modra + + * maxq.h: Delete file. + +2010-06-14 Sebastian Andrzej Siewior + + * ppc.h (PPC_OPCODE_E500): Define. + +2010-05-26 Catherine Moore + + * opcode/mips.h (INSN_MIPS16): Remove. + +2010-04-21 Joseph Myers + + * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. + +2010-04-15 Nick Clifton + + * alpha.h: Update copyright notice to use GPLv3. + * arc.h: Likewise. + * arm.h: Likewise. + * avr.h: Likewise. + * bfin.h: Likewise. + * cgen.h: Likewise. + * convex.h: Likewise. + * cr16.h: Likewise. + * cris.h: Likewise. + * crx.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * dlx.h: Likewise. + * h8300.h: Likewise. + * hppa.h: Likewise. + * i370.h: Likewise. + * i386.h: Likewise. + * i860.h: Likewise. + * i960.h: Likewise. + * ia64.h: Likewise. + * m68hc11.h: Likewise. + * m68k.h: Likewise. + * m88k.h: Likewise. + * maxq.h: Likewise. + * mips.h: Likewise. + * mmix.h: Likewise. + * mn10200.h: Likewise. + * mn10300.h: Likewise. + * msp430.h: Likewise. + * np1.h: Likewise. + * ns32k.h: Likewise. + * or32.h: Likewise. + * pdp11.h: Likewise. + * pj.h: Likewise. + * pn.h: Likewise. + * ppc.h: Likewise. + * pyr.h: Likewise. + * rx.h: Likewise. + * s390.h: Likewise. + * score-datadep.h: Likewise. + * score-inst.h: Likewise. + * sparc.h: Likewise. + * spu-insns.h: Likewise. + * spu.h: Likewise. + * tic30.h: Likewise. + * tic4x.h: Likewise. + * tic54x.h: Likewise. + * tic80.h: Likewise. + * v850.h: Likewise. + * vax.h: Likewise. + +2010-03-25 Joseph Myers + + * tic6x-control-registers.h, tic6x-insn-formats.h, + tic6x-opcode-table.h, tic6x.h: New. + +2010-02-25 Wu Zhangjin + + * mips.h: (LOONGSON2F_NOP_INSN): New macro. + +2010-02-08 Philipp Tomsich + + * opcode/ppc.h (PPC_OPCODE_TITAN): Define. + +2010-01-14 H.J. Lu + + * ia64.h (ia64_find_opcode): Remove argument name. + (ia64_find_next_opcode): Likewise. + (ia64_dis_opcode): Likewise. + (ia64_free_opcode): Likewise. + (ia64_find_dependency): Likewise. + +2009-11-22 Doug Evans + + * cgen.h: Include bfd_stdint.h. + (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. + +2009-11-18 Paul Brook + + * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. + +2009-11-17 Paul Brook + Daniel Jacobowitz + + * arm.h (ARM_EXT_V6_DSP): Define. + (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. + (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. + +2009-11-04 DJ Delorie + + * rx.h (rx_decode_opcode) (mvtipl): Add. + (mvtcp, mvfcp, opecp): Remove. + +2009-11-02 Paul Brook + + * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, + FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. + (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, + FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, + FPU_ARCH_NEON_VFP_V4): Define. + +2009-10-23 Doug Evans + + * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. + * cgen.h: Update. Improve multi-inclusion macro name. + +2009-10-02 Peter Bergner + + * ppc.h (PPC_OPCODE_476): Define. + +2009-10-01 Peter Bergner + + * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. + +2009-09-29 DJ Delorie + + * rx.h: New file. + +2009-09-22 Peter Bergner + + * ppc.h (ppc_cpu_t): Typedef to uint64_t. + +2009-09-21 Ben Elliston + + * ppc.h (PPC_OPCODE_PPCA2): New. + +2009-09-05 Martin Thuresson + + * ia64.h (struct ia64_operand): Renamed member class to op_class. + +2009-08-29 Martin Thuresson + + * tic30.h (template): Rename type template to + insn_template. Updated code to use new name. + * tic54x.h (template): Rename type template to + insn_template. + +2009-08-20 Nick Hudson + + * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. + +2009-06-11 Anthony Green + + * moxie.h (MOXIE_F3_PCREL): Define. + (moxie_form3_opc_info): Grow. + +2009-06-06 Anthony Green + + * moxie.h (MOXIE_F1_M): Define. + +2009-04-15 Anthony Green + + * moxie.h: Created. + +2009-04-06 DJ Delorie + + * h8300.h: Add relaxation attributes to MOVA opcodes. + +2009-03-10 Alan Modra + + * ppc.h (ppc_parse_cpu): Declare. + +2009-03-02 Qinwei + + * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 + and _IMM11 for mbitclr and mbitset. + * score-datadep.h: Update dependency information. + +2009-02-26 Peter Bergner + + * ppc.h (PPC_OPCODE_POWER7): New. + +2009-02-06 Doug Evans + + * i386.h: Add comment regarding sse* insns and prefixes. + +2009-02-03 Sandip Matte + + * mips.h (INSN_XLR): Define. + (INSN_CHIP_MASK): Update. + (CPU_XLR): Define. + (OPCODE_IS_MEMBER): Update. + (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. + +2009-01-28 Doug Evans + + * opcode/i386.h: Add multiple inclusion protection. + (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) + (EDI_REG_NUM): New macros. + (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. + (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. + (REX_PREFIX_P): New macro. + +2009-01-09 Peter Bergner + + * ppc.h (struct powerpc_opcode): New field "deprecated". + (PPC_OPCODE_NOPOWER4): Delete. + +2008-11-28 Joshua Kinard + + * mips.h: Define CPU_R14000, CPU_R16000. + (OPCODE_IS_MEMBER): Include R14000, R16000 in test. + +2008-11-18 Catherine Moore + + * arm.h (FPU_NEON_FP16): New. + (FPU_ARCH_NEON_FP16): New. + +2008-11-06 Chao-ying Fu + + * mips.h: Doucument '1' for 5-bit sync type. + +2008-08-28 H.J. Lu + + * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update + IA64_RS_CR. + +2008-08-01 Peter Bergner + + * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. + +2008-07-30 Michael J. Eager + + * ppc.h (PPC_OPCODE_405): Define. + (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. + +2008-06-13 Peter Bergner + + * ppc.h (ppc_cpu_t): New typedef. + (struct powerpc_opcode ): Use it. + (struct powerpc_operand ): Likewise. + (struct powerpc_macro ): Likewise. + +2008-06-12 Adam Nemet + + * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. + Update comment before MIPS16 field descriptors to mention MIPS16. + (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for + BBIT. + (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): + New bit masks and shift counts for cins and exts. + + * mips.h: Document new field descriptors +Q. + (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. + +2008-04-28 Adam Nemet + + * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. + +2008-04-14 Edmar Wienskoski + + * ppc.h: (PPC_OPCODE_E500MC): New. + +2008-04-03 H.J. Lu + + * i386.h (MAX_OPERANDS): Set to 5. + (MAX_MNEM_SIZE): Changed to 20. + +2008-03-28 Eric B. Weddington + + * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. + +2008-03-09 Paul Brook + + * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. + +2008-03-04 Paul Brook + + * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. + (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. + (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. + +2008-02-27 Denis Vlasenko + Nick Clifton + + PR 3134 + * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction + with a 32-bit displacement but without the top bit of the 4th byte + set. + +2008-02-18 M R Swami Reddy + + * cr16.h (cr16_num_optab): Declared. + +2008-02-14 Hakan Ardo + + PR gas/2626 + * avr.h (AVR_ISA_2xxe): Define. + +2008-02-04 Adam Nemet + + * mips.h: Update copyright. + (INSN_CHIP_MASK): New macro. + (INSN_OCTEON): New macro. + (CPU_OCTEON): New macro. + (OPCODE_IS_MEMBER): Handle Octeon instructions. + +2008-01-23 Eric B. Weddington + + * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. + +2008-01-03 Eric B. Weddington + + * avr.h (AVR_ISA_USB162): Add new opcode set. + (AVR_ISA_AVR3): Likewise. + +2007-11-29 Mark Shinwell + + * mips.h (INSN_LOONGSON_2E): New. + (INSN_LOONGSON_2F): New. + (CPU_LOONGSON_2E): New. + (CPU_LOONGSON_2F): New. + (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. + +2007-11-29 Mark Shinwell + + * mips.h (INSN_ISA*): Redefine certain values as an + enumeration. Update comments. + (mips_isa_table): New. + (ISA_MIPS*): Redefine to match enumeration. + (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* + values. + +2007-08-08 Ben Elliston + + * ppc.h (PPC_OPCODE_PPCPS): New. + +2007-07-03 Nathan Sidwell + + * m68k.h: Document j K & E. + +2007-06-29 M R Swami Reddy + + * cr16.h: New file for CR16 target. + +2007-05-02 Alan Modra + + * ppc.h (PPC_OPERAND_PLUS1): Update comment. + +2007-04-23 Nathan Sidwell + + * m68k.h (mcfisa_c): New. + (mcfusp, mcf_mask): Adjust. + +2007-04-20 Alan Modra + + * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". + (num_powerpc_operands): Declare. + (PPC_OPERAND_SIGNED et al): Redefine as hex. + (PPC_OPERAND_PLUS1): Define. + +2007-03-21 H.J. Lu + + * i386.h (REX_MODE64): Renamed to ... + (REX_W): This. + (REX_EXTX): Renamed to ... + (REX_R): This. + (REX_EXTY): Renamed to ... + (REX_X): This. + (REX_EXTZ): Renamed to ... + (REX_B): This. + +2007-03-15 H.J. Lu + + * i386.h: Add entries from config/tc-i386.h and move tables + to opcodes/i386-opc.h. + +2007-03-13 H.J. Lu + + * i386.h (FloatDR): Removed. + (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. + +2007-03-01 Alan Modra + + * spu-insns.h: Add soma double-float insns. + +2007-02-20 Thiemo Seufer + Chao-Ying Fu + + * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. + (INSN_DSPR2): Add flag for DSP R2 instructions. + (M_BALIGN): New macro. + +2007-02-14 Alan Modra + + * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm + and Seg3ShortFrom with Shortform. + +2007-02-11 H.J. Lu + + PR gas/4027 + * i386.h (i386_optab): Put the real "test" before the pseudo + one. + +2007-01-08 Kazu Hirata + + * m68k.h (m68010up): OR fido_a. + +2006-12-25 Kazu Hirata + + * m68k.h (fido_a): New. + +2006-12-24 Kazu Hirata + + * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, + mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined + values. + +2006-11-08 H.J. Lu + + * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. + +2006-10-31 Mei Ligang + + * score-inst.h (enum score_insn_type): Add Insn_internal. + +2006-10-25 Trevor Smigiel + Yukishige Shibata + Nobuhisa Fujinami + Takeaki Fukuoka + Alan Modra + + * spu-insns.h: New file. + * spu.h: New file. + +2006-10-24 Andrew Pinski + + * ppc.h (PPC_OPCODE_CELL): Define. + +2006-10-23 Dwarakanath Rajagopal + + * i386.h : Modify opcode to support for the change in POPCNT opcode + in amdfam10 architecture. + +2006-09-28 H.J. Lu + + * i386.h: Replace CpuMNI with CpuSSSE3. + +2006-09-26 Mark Shinwell + Joseph Myers + Ian Lance Taylor + Ben Elliston + + * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. + +2006-09-17 Mei Ligang + + * score-datadep.h: New file. + * score-inst.h: New file. + +2006-07-14 H.J. Lu + + * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, + movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, + movdq2q and movq2dq. + +2006-07-10 Dwarakanath Rajagopal + Michael Meissner + + * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). + +2006-06-12 H.J. Lu + + * i386.h (i386_optab): Add "nop" with memory reference. + +2006-06-12 H.J. Lu + + * i386.h (i386_optab): Update comment for 64bit NOP. + +2006-06-06 Ben Elliston + Anton Blanchard + + * ppc.h (PPC_OPCODE_POWER6): Define. + Adjust whitespace. + +2006-06-05 Thiemo Seufer + + * mips.h: Improve description of MT flags. + +2006-05-25 Richard Sandiford + + * m68k.h (mcf_mask): Define. + +2006-05-05 Thiemo Seufer + David Ung + + * mips.h (enum): Add macro M_CACHE_AB. + +2006-05-04 Thiemo Seufer + Nigel Stephens + David Ung + + * mips.h: Add INSN_SMARTMIPS define. + +2006-04-30 Thiemo Seufer + David Ung + + * mips.h: Defines udi bits and masks. Add description of + characters which may appear in the args field of udi + instructions. + +2006-04-26 Thiemo Seufer + + * mips.h: Improve comments describing the bitfield instruction + fields. + +2006-04-26 Julian Brown + + * arm.h (FPU_VFP_EXT_V3): Define constant. + (FPU_NEON_EXT_V1): Likewise. + (FPU_VFP_HARD): Update. + (FPU_VFP_V3): Define macro. + (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. + +2006-04-07 Joerg Wunsch + + * avr.h (AVR_ISA_PWMx): New. + +2006-03-28 Nathan Sidwell + + * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, + cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, + cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, + cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, + cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. + +2006-03-10 Paul Brook + + * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. + +2006-03-04 John David Anglin + + * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come + first. Correct mask of bb "B" opcode. + +2006-02-27 H.J. Lu + + * i386.h (i386_optab): Support Intel Merom New Instructions. + +2006-02-24 Paul Brook + + * arm.h: Add V7 feature bits. + +2006-02-23 H.J. Lu + + * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. + +2006-01-31 Paul Brook + Richard Earnshaw + + * arm.h: Use ARM_CPU_FEATURE. + (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. + (arm_feature_set): Change to a structure. + (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, + ARM_FEATURE): New macros. + +2005-12-07 Hans-Peter Nilsson + + * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) + (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. + (ADD_PC_INCR_OPCODE): Don't define. + +2005-12-06 H.J. Lu + + PR gas/1874 + * i386.h (i386_optab): Add 64bit support for monitor and mwait. + +2005-11-14 David Ung + + * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore + instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for + save/restore encoding of the args field. + +2005-10-28 Dave Brolley + + Contribute the following changes: + 2005-02-16 Dave Brolley + + * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename + cgen_isa_mask_* to cgen_bitset_*. + * cgen.h: Likewise. + + 2003-10-21 Richard Sandiford + + * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. + (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". + (CGEN_CPU_TABLE): Make isas a ponter. + + 2003-09-29 Dave Brolley + + * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. + (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. + (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. + + 2002-12-13 Dave Brolley + + * cgen.h (symcat.h): #include it. + (cgen-bitset.h): #include it. + (CGEN_ATTR_VALUE_TYPE): Now a union. + (CGEN_ATTR_VALUE): Reference macros generated in opcodes/-desc.h. + (CGEN_ATTR_ENTRY): 'value' now unsigned. + (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). + * cgen-bitset.h: New file. + +2005-09-30 Catherine Moore + + * bfin.h: New file. + +2005-10-24 Jan Beulich + + * ia64.h (enum ia64_opnd): Move memory operand out of set of + indirect operands. + +2005-10-16 John David Anglin + + * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. + Add FLAG_STRICT to pa10 ftest opcode. + +2005-10-12 John David Anglin + + * hppa.h (pa_opcodes): Remove lha entries. + +2005-10-08 John David Anglin + + * hppa.h (FLAG_STRICT): Revise comment. + (pa_opcode): Revise ordering rules. Add/move strict pa10 variants + before corresponding pa11 opcodes. Add strict pa10 register-immediate + entries for "fdc". + +2005-09-30 Catherine Moore + + * bfin.h: New file. + +2005-09-24 John David Anglin + + * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. + +2005-09-06 Chao-ying Fu + + * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, + OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New + define. + Document !, $, *, &, g, +t, +T operand formats for MT instructions. + (INSN_ASE_MASK): Update to include INSN_MT. + (INSN_MT): New define for MT ASE. + +2005-08-25 Chao-ying Fu + + * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, + OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, + OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, + OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, + OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. + Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP + instructions. + (INSN_DSP): New define for DSP ASE. + +2005-08-18 Alan Modra + + * a29k.h: Delete. + +2005-08-15 Daniel Jacobowitz + + * ppc.h (PPC_OPCODE_E300): Define. + +2005-08-12 Martin Schwidefsky + + * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. + +2005-07-28 John David Anglin + + PR gas/336 + * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb + and pitlb. + +2005-07-27 Jan Beulich + + * i386.h (i386_optab): Add comment to movd. Use LongMem for all + movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. + Add movq-s as 64-bit variants of movd-s. + +2005-07-18 John David Anglin + + * hppa.h: Fix punctuation in comment. + + * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for + implicit space-register addressing. Set space-register bits on opcodes + using implicit space-register addressing. Add various missing pa20 + long-immediate opcodes. Remove various opcodes using implicit 3-bit + space-register addressing. Use "fE" instead of "fe" in various + fstw opcodes. + +2005-07-18 Jan Beulich + + * i386.h (i386_optab): Operands of aam and aad are unsigned. + +2007-07-15 H.J. Lu + + * i386.h (i386_optab): Support Intel VMX Instructions. + +2005-07-10 John David Anglin + + * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. + +2005-07-05 Jan Beulich + + * i386.h (i386_optab): Add new insns. + +2005-07-01 Nick Clifton + + * sparc.h: Add typedefs to structure declarations. + +2005-06-20 H.J. Lu + + PR 1013 + * i386.h (i386_optab): Update comments for 64bit addressing on + mov. Allow 64bit addressing for mov and movq. + +2005-06-11 John David Anglin + + * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, + respectively, in various floating-point load and store patterns. + +2005-05-23 John David Anglin + + * hppa.h (FLAG_STRICT): Correct comment. + (pa_opcodes): Update load and store entries to allow both PA 1.X and + PA 2.0 mneumonics when equivalent. Entries with cache control + completers now require PA 1.1. Adjust whitespace. + +2005-05-19 Anton Blanchard + + * ppc.h (PPC_OPCODE_POWER5): Define. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, + crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, + i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, + mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, + pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, + tic54x.h, tic80.h, v850.h, vax.h + +2005-05-09 Jan Beulich + + * i386.h (i386_optab): Add ht and hnt. + +2005-04-18 Mark Kettenis + + * i386.h: Insert hyphens into selected VIA PadLock extensions. + Add xcrypt-ctr. Provide aliases without hyphens. + +2005-04-13 H.J. Lu + + Moved from ../ChangeLog + + 2005-04-12 Paul Brook + * m88k.h: Rename psr macros to avoid conflicts. + + 2005-03-12 Zack Weinberg + * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. + Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, + and ARM_ARCH_V6ZKT2. + + 2004-11-29 Tomer Levi + * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. + Remove redundant instruction types. + (struct argument): X_op - new field. + (struct cst4_entry): Remove. + (no_op_insn): Declare. + + 2004-11-05 Tomer Levi + * crx.h (enum argtype): Rename types, remove unused types. + + 2004-10-27 Tomer Levi + * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. + (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. + (enum operand_type): Rearrange operands, edit comments. + replace us with ui for unsigned immediate. + replace d with disps/dispu/dispe for signed/unsigned/escaped + displacements (respectively). + replace rbase_ridx_scl2_dispu with rindex_disps for register index. + (instruction type): Add NO_TYPE_INS. + (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. + (operand_entry): New field - 'flags'. + (operand flags): New. + + 2004-10-21 Tomer Levi + * crx.h (operand_type): Remove redundant types i3, i4, + i5, i8, i12. + Add new unsigned immediate types us3, us4, us5, us16. + +2005-04-12 Mark Kettenis + + * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and + adjust them accordingly. + +2005-04-01 Jan Beulich + + * i386.h (i386_optab): Add rdtscp. + +2005-03-29 H.J. Lu + + * i386.h (i386_optab): Don't allow the `l' suffix for moving + between memory and segment register. Allow movq for moving between + general-purpose register and segment register. + +2005-02-09 Jan Beulich + + PR gas/707 + * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and + FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and + fnstsw. + +2006-02-07 Nathan Sidwell + + * m68k.h (m68008, m68ec030, m68882): Remove. + (m68k_mask): New. + (cpu_m68k, cpu_cf): New. + (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, + mcf5470, mcf5480): Rename to cpu_. Add m680x0 variants. + +2005-01-25 Alexandre Oliva + + 2004-11-10 Alexandre Oliva + * cgen.h (enum cgen_parse_operand_type): Add + CGEN_PARSE_OPERAND_SYMBOLIC. + +2005-01-21 Fred Fish + + * mips.h: Change INSN_ALIAS to INSN2_ALIAS. + Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. + Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. + +2005-01-19 Fred Fish + + * mips.h (struct mips_opcode): Add new pinfo2 member. + (INSN_ALIAS): New define for opcode table entries that are + specific instances of another entry, such as 'move' for an 'or' + with a zero operand. + (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. + (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. + +2004-12-09 Ian Lance Taylor + + * mips.h (CPU_RM9000): Define. + (OPCODE_IS_MEMBER): Handle CPU_RM9000. + +2004-11-25 Jan Beulich + + * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves + to/from test registers are illegal in 64-bit mode. Add missing + NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix + (previously one had to explicitly encode a rex64 prefix). Re-enable + lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings + support it there. Add cmpxchg16b as per Intel's 64-bit documentation. + +2004-11-23 Jan Beulich + + * i386.h (i386_optab): paddq and psubq, even in their MMX form, are + available only with SSE2. Change the MMX additions introduced by SSE + and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A + instructions by their now designated identifier (since combining i686 + and 3DNow! does not really imply 3DNow!A). + +2004-11-19 Alan Modra + + * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, + struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. + +2004-11-08 Inderpreet Singh + Vineet Sharma + + * maxq.h: New file: Disassembly information for the maxq port. + +2004-11-05 H.J. Lu + + * i386.h (i386_optab): Put back "movzb". + +2004-11-04 Hans-Peter Nilsson + + * cris.h (enum cris_insn_version_usage): Tweak formatting and + comments. Remove member cris_ver_sim. Add members + cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, + cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. + (struct cris_support_reg, struct cris_cond15): New types. + (cris_conds15): Declare. + (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) + (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) + (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. + (NOP_Z_BITS): Define in terms of NOP_OPCODE. + (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and + SIZE_FIELD_UNSIGNED. + +2004-11-04 Jan Beulich + + * i386.h (sldx_Suf): Remove. + (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. + (q_FP): Define, implying no REX64. + (x_FP, sl_FP): Imply FloatMF. + (i386_optab): Split reg and mem forms of moving from segment registers + so that the memory forms can ignore the 16-/32-bit operand size + distinction. Adjust a few others for Intel mode. Remove *FP uses from + all non-floating-point instructions. Unite 32- and 64-bit forms of + movsx, movzx, and movd. Adjust floating point operations for the above + changes to the *FP macros. Add DefaultSize to floating point control + insns operating on larger memory ranges. Remove left over comments + hinting at certain insns being Intel-syntax ones where the ones + actually meant are already gone. + +2004-10-07 Tomer Levi + + * crx.h: Add COPS_REG_INS - Coprocessor Special register + instruction type. + +2004-09-30 Paul Brook + + * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. + (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. + +2004-09-11 Theodore A. Roth + + * avr.h: Add support for + atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. + +2004-09-09 Segher Boessenkool + + * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. + +2004-08-24 Dmitry Diky + + * msp430.h (msp430_opc): Add new instructions. + (msp430_rcodes): Declare new instructions. + (msp430_hcodes): Likewise.. + +2004-08-13 Nick Clifton + + PR/301 + * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX + processors. + +2004-08-30 Michal Ludvig + + * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. + +2004-07-22 H.J. Lu + + * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. + +2004-07-21 Jan Beulich + + * i386.h: Adjust instruction descriptions to better match the + specification. + +2004-07-16 Richard Earnshaw + + * arm.h: Remove all old content. Replace with architecture defines + from gas/config/tc-arm.c. + +2004-07-09 Andreas Schwab + + * m68k.h: Fix comment. + +2004-07-07 Tomer Levi + + * crx.h: New file. + +2004-06-24 Alan Modra + + * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. + +2004-05-24 Peter Barada + + * m68k.h: Add 'size' to m68k_opcode. + +2004-05-05 Peter Barada + + * m68k.h: Switch from ColdFire chip name to core variant. + +2004-04-22 Peter Barada + + * m68k.h: Add mcfmac/mcfemac definitions. Update operand + descriptions for new EMAC cases. + Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly + handle Motorola MAC syntax. + Allow disassembly of ColdFire V4e object files. + +2004-03-16 Alan Modra + + * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. + +2004-03-12 Jakub Jelinek + + * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + +2004-03-12 Michal Ludvig + + * i386.h (i386_optab): Added xstore as an alias for xstorerng. + +2004-03-12 Michal Ludvig + + * i386.h (i386_optab): Added xstore/xcrypt insns. + +2004-02-09 Anil Paranjpe + + * h8300.h (32bit ldc/stc): Add relaxing support. + +2004-01-12 Anil Paranjpe + + * h8300.h (BITOP): Pass MEMRELAX flag. + +2004-01-09 Anil Paranjpe + + * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 + except for the H8S. + +For older changes see ChangeLog-9103 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/opcode/ChangeLog-9103 b/external/gpl3/gdb/dist/include/opcode/ChangeLog-9103 new file mode 100644 index 000000000000..9a04bf5f5c7e --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/ChangeLog-9103 @@ -0,0 +1,3121 @@ +2005-04-13 H.J. Lu + + 2003-11-18 Maciej W. Rozycki + * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. + + 2003-04-04 Svein E. Seldal + * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x + + 2002-11-16 Klee Dienes + * m88k.h (INSTAB): Remove 'next' field. + (instruction): Remove definition; replace with extern declaration + and mark as const. + + 2002-08-28 Michael Hayes + * tic4x.h: New file. + + 2002-07-25 Richard Sandiford + * mips.h (CPU_R2000): Remove. + +2003-10-21 Peter Barada + Bernardo Innocenti + + * m68k.h: Add MCFv4/MCF5528x support. + +2003-10-19 Hans-Peter Nilsson + + * mmix.h (JMP_INSN_BYTE): Define. + +2003-09-30 Chris Demetriou + + * mips.h: Document +E, +F, +G, +H, and +I operand types. + Update documentation of I, +B and +C operand types. + (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. + (M_DEXT, M_DINS): New enum values. + +2003-09-04 Nick Clifton + + * v850.h (PROCESSOR_V850E1): Define. + +2003-08-19 Alan Modra + + * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other + PPC_OPCODE_* defines. + +2003-08-16 Jason Eckhardt + + * i860.h (fmov.ds): Expand as famov.ds. + (fmov.sd): Expand as famov.sd. + (pfmov.ds): Expand as pfamov.ds. + +2003-08-07 Michael Meissner + + * cgen.h: Remove PARAM macro usage in all prototypes. + (CGEN_EXTRACT_INFO): Use void * instead of PTR. + (cgen_print_fn): Ditto. + (CGEN_HW_ENTRY): Ditto. + (CGEN_MAYBE_MULTI_IFLD): Ditto. + (struct cgen_insn): Ditto. + (CGEN_CPU_TABLE): Ditto. + +2003-08-07 Alan Modra + + * alpha.h: Remove PARAMS macro. + * arc.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * i370.h: Likewise. + * or32.h: Likewise. + * pj.h: Likewise. + * ppc.h: Likewise. + * sparc.h: Likewise. + * tic80.h: Likewise. + * v850.h: Likewise. + +2003-07-18 Michael Snyder + + * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. + +2003-07-15 Richard Sandiford + + * mips.h (CPU_RM7000): New macro. + (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. + +2003-07-09 Alexandre Oliva + + 2000-04-01 Alexandre Oliva + * mn10300.h (AM33_2): Renamed from AM33. + 2000-03-31 Alexandre Oliva + * mn10300.h (AM332, FMT_D3): Defined. + (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. + (MN10300_OPERAND_FPCR): Likewise. + +2003-07-01 Martin Schwidefsky + + * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. + +2003-06-25 Richard Sandiford + + * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. + (IMM8U, IMM8U_NS): Define. + (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. + +2003-06-25 Richard Sandiford + + * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and + mov.l ERs,@(dd:32,ERd) entries. + +2003-06-23 H.J. Lu + + * i386.h (i386_optab): Support Intel Precott New Instructions. + +2003-06-10 Gary Hade + + * ppc.h (PPC_OPERAND_DQ): Define. + +2003-06-10 Richard Sandiford + + * h8300.h (IMM4_NS, IMM8_NS): New. + (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. + Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. + +2003-06-03 Michael Snyder + + * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H. + (ldc): Split ccr ops from exr ops (which are only available + on H8S or H8SX). + (stc): Ditto. + (andc, orc, xorc): Ditto. + (ldmac, stmac, clrmac, mac): Change access to AV_H8S. + +2003-06-03 Michael Snyder + and Bernd Schmidt + and Alexandre Oliva + * h8300.h: Add support for h8300sx instruction set. + +2003-05-23 Jason Eckhardt + + * i860.h (expand_type): Add XP_ONLY. + (scyc.b): New XP instruction. + (ldio.l): Likewise. + (ldio.s): Likewise. + (ldio.b): Likewise. + (ldint.l): Likewise. + (ldint.s): Likewise. + (ldint.b): Likewise. + (stio.l): Likewise. + (stio.s): Likewise. + (stio.b): Likewise. + (pfld.q): Likewise. + +2003-05-20 Jason Eckhardt + + * i860.h (flush): Set lower 3 bits properly and use 'L' + for the immediate operand type instead of 'i'. + +2003-05-20 Jason Eckhardt + + * i860.h (fzchks): Both S and R bits must be set. + (pfzchks): Likewise. + (faddp): Likewise. + (pfaddp): Likewise. + (fix.ss): Remove (invalid instruction). + (pfix.ss): Likewise. + (ftrunc.ss): Likewise. + (pftrunc.ss): Likewise. + +2003-05-18 Jason Eckhardt + + * i860.h (form, pform): Add missing .dd suffix. + +2003-05-13 Stephane Carrez + + * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 + +2003-04-07 Michael Snyder + + * h8300.h (ldc/stc): Fix up src/dst swaps. + +2003-04-09 J. Grant + + * mips.h: Correct comment typo. + +2003-03-21 Martin Schwidefsky + + * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val. + (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH. + (s390_opcode): Remove architecture. Add modes and min_cpu. + +2003-03-17 D.Venkatasubramanian + + * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line + processing. + +2003-02-21 Noida D.Venkatasubramanian + + * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32. + +2003-01-23 Alan Modra + + * m68hc11.h (cpu6812s): Define. + +2003-01-07 Chris Demetriou + + * mips.h: Fix missing space in comment. + (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) + (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right + by four bits. + +2003-01-02 Chris Demetriou + + * mips.h: Update copyright years to include 2002 (which had + been missed previously) and 2003. Make comments about "+A", + "+B", and "+C" operand types more descriptive. + +2002-12-31 Chris Demetriou + + * mips.h: Note that the "+D" operand type name is now used. + +2002-12-30 Chris Demetriou + + * mips.h: Document "+" as the start of two-character operand + type names, and add new "K", "+A", "+B", and "+C" operand types. + (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) + (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New + defines. + +2002-12-24 Dmitry Diky + + * msp430.h: New file. Defines msp430 opcodes. + +2002-12-30 D.Venkatasubramanian + + * h8300.h: Added some more pseudo opcodes for system call + processing. + +2002-12-19 Chris Demetriou + + * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) + (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) + (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) + (OP_OP_SDC2, OP_OP_SDC3): Define. + +2002-12-16 Alan Modra + + * hppa.h (completer_chars): #if 0 out. + + * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and + "default_args". + (struct not_wot): Constify "args". + (struct not): Constify "name". + (numopcodes): Delete. + (endop): Delete. + +2002-12-13 Alan Modra + + * pj.h (pj_opc_info_t): Add union. + +2002-12-04 David Mosberger + + * ia64.h: Fix copyright message. + (IA64_OPND_AR_CSD): New operand kind. + +2002-12-03 Richard Henderson + + * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. + +2002-12-03 Alan Modra + + * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. + Constify "leaf" and "multi". + +2002-11-19 Klee Dienes + + * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' + fields. + (h8_opcodes). Modify initializer and initializer macros to no + longer initialize the removed fields. + +2002-11-19 Svein E. Seldal + + * tic4x.h (c4x_insts): Fixed LDHI constraint + +2002-11-18 Klee Dienes + + * h8300.h (h8_opcode): Remove 'length' field. + (h8_opcodes): Mark as 'const' (both the declaration and + definition). Modify initializer and initializer macros to no + longer initialize the length field. + +2002-11-18 Klee Dienes + + * arc.h (arc_ext_opcodes): Declare as extern. + (arc_ext_operands): Declare as extern. + * i860.h (i860_opcodes): Declare as const. + +2002-11-18 Svein E. Seldal + + * tic4x.h: File reordering. Added enhanced opcodes. + +2002-11-16 Svein E. Seldal + + * tic4x.h: Major rewrite of entire file. Define instruction + classes, and put each instruction into a class. + +2002-11-11 Svein E. Seldal + + * tic4x.h: Added new opcodes and corrected some bugs. Add support + for new DSP types. + +2002-10-14 Alan Modra + + * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. + +2002-09-30 Gavin Romig-Koch + Ken Raeburn + Aldy Hernandez + Eric Christopher + Richard Sandiford + + * mips.h: Update comment for new opcodes. + (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. + (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. + (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. + (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. + (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. + Don't match CPU_R4111 with INSN_4100. + +2002-08-19 Elena Zannoni + + From matthew green + + * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 + instructions. + (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, + PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the + e500x2 Integer select, branch locking, performance monitor, + cache locking and machine check APUs, respectively. + (PPC_OPCODE_EFS): New opcode type for efs* instructions. + (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. + +2002-08-13 Stephane Carrez + + * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. + (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, + M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 + memory banks. + (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. + +2002-07-09 Thiemo Seufer + + * mips.h (INSN_MIPS16): New define. + +2002-07-08 Alan Modra + + * i386.h: Remove IgnoreSize from movsx and movzx. + +2002-06-08 Alan Modra + + * a29k.h: Replace CONST with const. + (CONST): Don't define. + * convex.h: Replace CONST with const. + (CONST): Don't define. + * dlx.h: Replace CONST with const. + * or32.h (CONST): Don't define. + +2002-05-30 Chris G. Demetriou + + * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) + (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) + (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) + (INSN_MDMX): New constants, for MDMX support. + (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. + +2002-05-28 Kuang Hwa Lin + + * dlx.h: New file. + +2002-05-25 Alan Modra + + * ia64.h: Use #include "" instead of <> for local header files. + * sparc.h: Likewise. + +2002-05-22 Thiemo Seufer + + * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. + +2002-05-17 Andrey Volkov + + * h8300.h: Corrected defs of all control regs + and eepmov instr. + +2002-04-11 Alan Modra + + * i386.h: Add intel mode cmpsd and movsd. + Put them before SSE2 insns, so that rep prefix works. + +2002-03-15 Chris G. Demetriou + + * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D + instructions. + (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks + may be passed along with the ISA bitmask. + +2002-03-05 Paul Koning + + * pdp11.h: Add format codes for float instruction formats. + +2002-02-25 Alan Modra + + * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. + +Mon Feb 18 17:31:48 CET 2002 Jan Hubicka + + * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. + +Mon Feb 11 12:53:19 CET 2002 Jan Hubicka + + * i386.h (push,pop): Allow 16bit operands in 64bit mode. + (xchg): Fix. + (in, out): Disable 64bit operands. + (call, jmp): Avoid REX prefixes. + (jcxz): Prohibit in 64bit mode + (jrcxz, loop): Add 64bit variants. + (movq): Fix patterns. + (movmskps, pextrw, pinstrw): Add 64bit variants. + +2002-01-31 Ivan Guzvinec + + * or32.h: New file. + +2002-01-22 Graydon Hoare + + * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. + (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. + +2002-01-21 Thomas Klausner + + * h8300.h: Comment typo fix. + +2002-01-03 matthew green + + * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. + (PPC_OPCODE_BOOKE64): Likewise. + +Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) + + * hppa.h (call, ret): Move to end of table. + (addb, addib): PA2.0 variants should have been PA2.0W. + (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler + happy. + (fldw, fldd, fstw, fstd, bb): Likewise. + (short loads/stores): Tweak format specifier slightly to keep + disassembler happy. + (indexed loads/stores): Likewise. + (absolute loads/stores): Likewise. + +2001-12-04 Alexandre Oliva + + * d10v.h (OPERAND_NOSP): New macro. + +2001-11-29 Alexandre Oliva + + * d10v.h (OPERAND_SP): New macro. + +2001-11-15 Alan Modra + + * ppc.h (struct powerpc_operand ): Add dialect param. + +2001-11-11 Timothy Wall + + * tic54x.h: Revise opcode layout; don't really need a separate + structure for parallel opcodes. + +2001-11-13 Zack Weinberg + Alan Modra + + * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to + accept WordReg. + +2001-11-04 Chris Demetriou + + * mips.h (OPCODE_IS_MEMBER): Remove extra space. + +2001-10-30 Hans-Peter Nilsson + + * mmix.h: New file. + +2001-10-18 Chris Demetriou + + * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end + of the expression, to make source code merging easier. + +2001-10-17 Chris Demetriou + + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + +2001-10-17 matthew green + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + +2001-10-12 matthew green + + * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New + opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 + instructions, respectively. + +2001-09-27 Nick Clifton + + * v850.h: Remove spurious comment. + +2001-09-21 Nick Clifton + + * h8300.h: Fix compile time warning messages + +2001-09-04 Richard Henderson + + * alpha.h (struct alpha_operand): Pack elements into bitfields. + +2001-08-31 Eric Christopher + + * mips.h: Remove CPU_MIPS32_4K. + +2001-08-27 Torbjorn Granlund + + * ppc.h (PPC_OPERAND_DS): Define. + +2001-08-25 Andreas Jaeger + + * d30v.h: Fix declaration of reg_name_cnt. + + * d10v.h: Fix declaration of d10v_reg_name_cnt. + + * arc.h: Add prototypes from opcodes/arc-opc.c. + +2001-08-16 Thiemo Seufer + + * mips.h (INSN_10000): Define. + (OPCODE_IS_MEMBER): Check for INSN_10000. + +2001-08-10 Alan Modra + + * ppc.h: Revert 2001-08-08. + +2001-08-10 Richard Sandiford + + * mips.h (INSN_GP32): Remove. + (OPCODE_IS_MEMBER): Remove gp32 parameter. + (M_MOVE): New macro identifier. + +2001-08-08 Alan Modra + + 1999-10-25 Torbjorn Granlund + * ppc.h (struct powerpc_operand): New field `reloc'. + +2001-08-01 Aldy Hernandez + + * mips.h (INSN_ISA_MASK): Nuke bits 12-15. + +2001-07-12 Jeff Johnston + + * cgen.h (CGEN_INSN): Add regex support. + (build_insn_regex): Declare. + +2001-07-11 Frank Ch. Eigler + + * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. + (cgen_cpu_desc): Ditto. + +2001-07-07 Ben Elliston + + * m88k.h: Clean up and reformat. Remove unused code. + +2001-06-14 Geoffrey Keating + + * cgen.h (cgen_keyword): Add nonalpha_chars field. + +2001-05-23 Thiemo Seufer + + * mips.h (CPU_R12000): Define. + +2001-05-23 John Healy + + * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. + +2001-05-15 Thiemo Seufer + + * mips.h (INSN_ISA_MASK): Define. + +2001-05-12 Alan Modra + + * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, + not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, + and use InvMem as these insns must have register operands. + +2001-05-04 Alan Modra + + * i386.h (i386_optab): Move InvMem to first operand of pmovmskb + and pextrw to swap reg/rm assignments. + +2001-04-05 Hans-Peter Nilsson + + * cris.h (enum cris_insn_version_usage): Correct comment for + cris_ver_v3p. + +2001-03-24 Alan Modra + + * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". + Add InvMem to first operand of "maskmovdqu". + +2001-03-22 Hans-Peter Nilsson + + * cris.h (ADD_PC_INCR_OPCODE): New macro. + +2001-03-21 Kazu Hirata + + * h8300.h: Fix formatting. + +2001-03-22 Alan Modra + + * i386.h (i386_optab): Add paddq, psubq. + +2001-03-19 Alan Modra + + * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. + +2001-02-28 Igor Shevlyakov + + * m68k.h: new defines for Coldfire V4. Update mcf to know + about mcf5407. + +2001-02-18 lars brinkhoff + + * pdp11.h: New file. + +2001-02-12 Jan Hubicka + + * i386.h (i386_optab): SSE integer converison instructions have + 64bit versions on x86-64. + +2001-02-10 Nick Clifton + + * mips.h: Remove extraneous whitespace. Formating change to allow + for future contribution. + +2001-02-09 Martin Schwidefsky + + * s390.h: New file. + +2001-02-02 Patrick Macdonald + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. + (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. + (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. + +2001-01-24 Karsten Keil + + * i386.h (i386_optab): Fix swapgs + +2001-01-14 Alan Modra + + * hppa.h: Describe new '<' and '>' operand types, and tidy + existing comments. + (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. + Remove duplicate "ldw j(s,b),x". Sort some entries. + +2001-01-13 Jan Hubicka + + * i386.h (i386_optab): Fix pusha and ret templates. + +2001-01-11 Peter Targett + + * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New + definitions for masking cpu type. + (arc_ext_operand_value) New structure for storing extended + operands. + (ARC_OPERAND_*) Flags for operand values. + +2001-01-10 Jan Hubicka + + * i386.h (pinsrw): Add. + (pshufw): Remove. + (cvttpd2dq): Fix operands. + (cvttps2dq): Likewise. + (movq2q): Rename to movdq2q. + +2001-01-10 Richard Schaal + + * i386.h: Correct movnti instruction. + +2001-01-09 Jeff Johnston + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number + of operands (unsigned char or unsigned short). + (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. + (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. + +2001-01-05 Jan Hubicka + + * i386.h (i386_optab): Make [sml]fence template to use immext field. + +2001-01-03 Jan Hubicka + + * i386.h (i386_optab): Fix 64bit pushf template; Add instructions + introduced by Pentium4 + +2000-12-30 Jan Hubicka + + * i386.h (i386_optab): Add "rex*" instructions; + add swapgs; disable jmp/call far direct instructions for + 64bit mode; add syscall and sysret; disable registers for 0xc6 + template. Add 'q' suffixes to extendable instructions, disable + obsolete instructions, add new sign/zero extension ones. + (i386_regtab): Add extended registers. + (*Suf): Add No_qSuf. + (q_Suf, wlq_Suf, bwlq_Suf): New. + +2000-12-20 Jan Hubicka + + * i386.h (i386_optab): Replace "Imm" with "EncImm". + (i386_regtab): Add flags field. + +2000-12-12 Nick Clifton + + * mips.h: Fix formatting. + +2000-12-01 Chris Demetriou + + mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. + (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old + OP_*_SYSCALL definitions. + (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as + 19 bit wait codes. + (MIPS operand specifier comments): Remove 'm', add 'U' and + 'J', and update the meaning of 'B' so that it's more general. + + * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, + INSN_ISA5): Renumber, redefine to mean the ISA at which the + instruction was added. + (INSN_ISA32): New constant. + (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): + Renumber to avoid new and/or renumbered INSN_* constants. + (INSN_MIPS32): Delete. + (ISA_UNKNOWN): New constant to indicate unknown ISA. + (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, + ISA_MIPS32): New constants, defined to be the mask of INSN_* + constants available at that ISA level. + (CPU_UNKNOWN): New constant to indicate unknown CPU. + (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, + define it with a unique value. + (OPCODE_IS_MEMBER): Update for new ISA membership-related + constant meanings. + + * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New + definitions. + + * mips.h (CPU_SB1): New constant. + +2000-10-20 Jakub Jelinek + + * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. + Note that '3' is used for siam operand. + +2000-09-22 Jim Wilson + + * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. + +2000-09-13 Anders Norlander + + * mips.h: Use defines instead of hard-coded processor numbers. + (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, + CPU_4KC, CPU_4KM, CPU_4KP): Define.. + (OPCODE_IS_MEMBER): Use new defines. + (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_CODE20, OP_SH_CODE20): Define. + Add 'P' to used characters. + Use 'H' for coprocessor select field. + Use 'm' for 20 bit breakpoint code. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + +2000-09-05 Alan Modra + + * hppa.h: Mention cz completer. + +2000-08-16 Jim Wilson + + * ia64.h (IA64_OPCODE_POSTINC): New. + +2000-08-15 H.J. Lu + + * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the + IgnoreSize change. + +2000-08-08 Jason Eckhardt + + * i860.h: Small formatting adjustments. + +2000-07-29 Marek Michalkiewicz + + * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. + Move related opcodes closer to each other. + Minor changes in comments, list undefined opcodes. + +2000-07-26 Dave Brolley + + * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. + +2000-07-22 Jason Eckhardt + + * i860.h (btne, bte, bla): Changed these opcodes + to use sbroff ('r') instead of split16 ('s'). + (J, K, L, M): New operand types for 16-bit aligned fields. + (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to + use I, J, K, L, M instead of just I. + (T, U): New operand types for split 16-bit aligned fields. + (st.x): Changed these opcodes to use S, T, U instead of just S. + (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not + exist on the i860. + (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. + (pfeq.ss, pfeq.dd): New opcodes. + (st.s): Fixed incorrect mask bits. + (fmlow): Fixed incorrect mask bits. + (fzchkl, pfzchkl): Fixed incorrect mask bits. + (faddz, pfaddz): Fixed incorrect mask bits. + (form, pform): Fixed incorrect mask bits. + (pfld.l): Fixed incorrect mask bits. + (fst.q): Fixed incorrect mask bits. + (all floating point opcodes): Fixed incorrect mask bits for + handling of dual bit. + +2000-07-20 Hans-Peter Nilsson + + cris.h: New file. + +2000-06-26 Marek Michalkiewicz + + * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. + (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. + (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. + (AVR_ISA_M83): Define for ATmega83, ATmega85. + (espm): Remove, because ESPM removed in databook update. + (eicall, eijmp): Move to the end of opcode table. + +2000-06-18 Stephane Carrez + + * m68hc11.h: New file for support of Motorola 68hc11. + +Fri Jun 9 21:51:50 2000 Denis Chertykov + + * avr.h: clr,lsl,rol, ... moved after add,adc, ... + +Wed Jun 7 21:39:54 2000 Denis Chertykov + + * avr.h: New file with AVR opcodes. + +Wed Apr 12 17:11:20 2000 Donald Lindsay + + * d10v.h: added ALONE attribute for d10v_opcode.exec_type. + +2000-05-23 Maciej W. Rozycki + + * i386.h: Allow d suffix on iret, and add DefaultSize modifier. + +2000-05-17 Maciej W. Rozycki + + * i386.h: Use sl_FP, not sl_Suf for fild. + +2000-05-16 Frank Ch. Eigler + + * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that + it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. + (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds + CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. + +2000-05-13 Alan Modra , + + * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. + +2000-05-13 Alan Modra , + Alexander Sokolov + + * i386.h (i386_optab): Add cpu_flags for all instructions. + +2000-05-13 Alan Modra + + From Gavin Romig-Koch + * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. + +2000-05-04 Timothy Wall + + * tic54x.h: New. + +2000-05-03 J.T. Conklin + + * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. + (PPC_OPERAND_VR): New operand flag for vector registers. + +2000-05-01 Kazu Hirata + + * h8300.h (EOP): Add missing initializer. + +Fri Apr 21 15:03:37 2000 Jason Eckhardt + + * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode + forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). + New operand types l,y,&,fe,fE,fx added to support above forms. + (pa_opcodes): Replaced usage of 'x' as source/target for + floating point double-word loads/stores with 'fx'. + +Fri Apr 21 13:20:53 2000 Richard Henderson + David Mosberger + Timothy Wall + Jim Wilson + + * ia64.h: New file. + +2000-03-27 Nick Clifton + + * d30v.h (SHORT_A1): Fix value. + (SHORT_AR): Renumber so that it is at the end of the list of short + instructions, not the end of the list of long instructions. + +2000-03-26 Alan Modra + + * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the + problem isn't really specific to Unixware. + (OLDGCC_COMPAT): Define. + (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with + destination %st(0). + Fix lots of comments. + +2000-03-02 J"orn Rennecke + + * d30v.h: + (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. + (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. + (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. + (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. + (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. + (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. + (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. + +2000-02-25 Alan Modra + + * i386.h (fild, fistp): Change intel d_Suf form to fildd and + fistpd without suffix. + +2000-02-24 Nick Clifton + + * cgen.h (cgen_cpu_desc): Rename field 'flags' to + 'signed_overflow_ok_p'. + Delete prototypes for cgen_set_flags() and cgen_get_flags(). + +2000-02-24 Andrew Haley + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + (CGEN_CPU_TABLE): flags: new field. + Add prototypes for new functions. + +2000-02-24 Alan Modra + + * i386.h: Add some more UNIXWARE_COMPAT comments. + +2000-02-23 Linas Vepstas + + * i370.h: New file. + +2000-02-22 Chandra Chavva + + * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation + cannot be combined in parallel with ADD/SUBppp. + +2000-02-22 Andrew Haley + + * mips.h: (OPCODE_IS_MEMBER): Add comment. + +1999-12-30 Andrew Haley + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines + whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit + insns. + +2000-01-15 Alan Modra + + * i386.h: Qualify intel mode far call and jmp with x_Suf. + +1999-12-27 Alan Modra + + * i386.h: Add JumpAbsolute qualifier to all non-intel mode + indirect jumps and calls. Add FF/3 call for intel mode. + +Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add new operand types. Add new instruction formats. + +Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" + instruction. + +1999-11-18 Gavin Romig-Koch + + * mips.h (INSN_ISA5): New. + +1999-11-01 Gavin Romig-Koch + + * mips.h (OPCODE_IS_MEMBER): New. + +1999-10-29 Nick Clifton + + * d30v.h (SHORT_AR): Define. + +1999-10-18 Michael Meissner + + * alpha.h (alpha_num_opcodes): Convert to unsigned. + (alpha_num_operands): Ditto. + +Sun Oct 10 01:46:56 1999 Jerry Quinn + + * hppa.h (pa_opcodes): Add load and store cache control to + instructions. Add ordered access load and store. + + * hppa.h (pa_opcode): Add new entries for addb and addib. + + * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. + + * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. + +Thu Oct 7 00:12:25 MDT 1999 Diego Novillo + + * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. + +Thu Sep 23 07:08:38 1999 Jerry Quinn + + * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" + and "be" using completer prefixes. + + * hppa.h (pa_opcodes): Add initializers to silence compiler. + + * hppa.h: Update comments about character usage. + +Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning + up the new fstw & bve instructions. + +Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store + instructions. + + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + + * hppa.h (pa_opcodes): Add long offset double word load/store + instructions. + + * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and + stores. + + * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. + + * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. + + * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. + + * hppa.h (pa_opcodes): Add new syntax "be" instructions. + + * hppa.h (pa_opcodes): Note use of 'M' and 'L'. + + * hppa.h (pa_opcodes): Add support for "b,l". + + * hppa.h (pa_opcodes): Add support for "b,gate". + +Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Use 'fX' for first register operand + in xmpyu. + + * hppa.h (pa_opcodes): Fix mask for probe and probei. + + * hppa.h (pa_opcodes): Fix mask for depwi. + +Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as + an explicit output argument. + +Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. + Add a few PA2.0 loads and store variants. + +1999-09-04 Steve Chamberlain + + * pj.h: New file. + +1999-08-29 Alan Modra + + * i386.h (i386_regtab): Move %st to top of table, and split off + other fp reg entries. + (i386_float_regtab): To here. + +Sat Aug 28 00:25:25 1999 Jerry Quinn + + * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args + by 'f'. + + * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. + Add supporting args. + + * hppa.h: Document new completers and args. + * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, + uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 + extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions + pmenb and pmdis. + + * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, + hshr, hsub, mixh, mixw, permh. + + * hppa.h (pa_opcodes): Change completers in instructions to + use 'c' prefix. + + * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, + hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. + + * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, + fnegabs to use 'I' instead of 'F'. + +1999-08-21 Alan Modra + + * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. + Document pf2iw and pi2fw as athlon insns. Remove pswapw. + Alphabetically sort PIII insns. + +Wed Aug 18 18:14:40 1999 Doug Evans + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + +Fri Aug 6 09:46:35 1999 Jerry Quinn + + * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, + and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. + + * hppa.h: Document 64 bit condition completers. + +Thu Aug 5 16:56:07 1999 Jerry Quinn + + * hppa.h (pa_opcodes): Change condition args to use '?' prefix. + +1999-08-04 Alan Modra + + * i386.h (i386_optab): Add DefaultSize modifier to all insns + that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, + sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. + +Wed Jul 28 02:04:24 1999 Jerry Quinn + Jeff Law + + * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". + + * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. + + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. + +1999-07-13 Alan Modra + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn + Jeff Law + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford + +Sat May 8 23:27:35 1999 Richard Henderson + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + +1999-04-14 Doug Evans + + * cgen.h (CGEN_ATTR): Delete member num_nonbools. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_MASK): Number booleans starting at 0. + (CGEN_ATTR_VALUE): Update. + (CGEN_INSN_ATTR): Update. + +Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 + instructions. + +Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bb, bvb): Tweak opcode/mask. + + +1999-03-22 Doug Evans + + * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. + (struct cgen_cpu_desc): Rename member mach to machs. New member isas. + New members word_bitsize,default_insn_bitsize,base_insn-bitsize, + min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. + Delete member max_insn_size. + (enum cgen_cpu_open_arg): New enum. + (cpu_open): Update prototype. + (cpu_open_1): Declare. + (cgen_set_cpu): Delete. + +1999-03-11 Doug Evans + + * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. + (CGEN_OPERAND_NIL): New macro. + (CGEN_OPERAND): New member `type'. + (@arch@_cgen_operand_table): Delete decl. + (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. + (CGEN_OPERAND_TABLE): New struct. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. + (CGEN_OPINST): Pointer to operand table entry replaced with enum. + (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', + now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to + {get,set}_{int,vma}_operand. + (@arch@_cgen_cpu_open): New arg `isa'. + (cgen_set_cpu): Ditto. + +Fri Feb 26 02:36:45 1999 Richard Henderson + + * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. + +1999-02-25 Doug Evans + + * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. + (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to + enum cgen_hw_type. + (CGEN_HW_TABLE): New struct. + (hw_table): Delete declaration. + (CGEN_OPERAND): Change member hw to hw_type, change type from pointer + to table entry to enum. + (CGEN_OPINST): Ditto. + (CGEN_CPU_TABLE): Change member hw_list to hw_table. + +Sat Feb 13 14:13:44 1999 Richard Henderson + + * alpha.h (AXP_OPCODE_EV6): New. + (AXP_OPCODE_NOPAL): Include it. + +1999-02-09 Doug Evans + + * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. + All uses updated. New members int_insn_p, max_insn_size, + parse_operand,insert_operand,extract_operand,print_operand, + sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, + get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, + extract_handlers,print_handlers. + (CGEN_ATTR): Change type of num_nonbools to unsigned int. + (CGEN_ATTR_BOOL_OFFSET): New macro. + (CGEN_ATTR_MASK): Subtract it to compute bit number. + (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. + (cgen_opcode_handler): Renamed from cgen_base. + (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. + (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, + all uses updated. + (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. + (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. + (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. + (CGEN_OPCODE,CGEN_IBASE): New types. + (CGEN_INSN): Rewrite. + (CGEN_{ASM,DIS}_HASH*): Delete. + (init_opcode_table,init_ibld_table): Declare. + (CGEN_INSN_ATTR): New type. + +Mon Feb 1 21:09:14 1999 Catherine Moore + + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. + (x_FP, d_FP, dls_FP, sldx_FP): Define. + Change *Suf definitions to include x and d suffixes. + (movsx): Use w_Suf and b_Suf. + (movzx): Likewise. + (movs): Use bwld_Suf. + (fld): Change ordering. Use sld_FP. + (fild): Add Intel Syntax equivalent of fildq. + (fst): Use sld_FP. + (fist): Use sld_FP. + (fstp): Use sld_FP. Add x_FP version. + (fistp): LLongMem version for Intel Syntax. + (fcom, fcomp): Use sld_FP. + (fadd, fiadd, fsub): Use sld_FP. + (fsubr): Use sld_FP. + (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. + +1999-01-27 Doug Evans + + * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, + CGEN_MODE_UINT. + +1999-01-16 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bv): Fix mask. + +1999-01-05 Doug Evans + + * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. + (CGEN_ATTR): Use it. + (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. + (CGEN_ATTR_TABLE): New member dfault. + +1998-12-30 Gavin Romig-Koch + + * mips.h (MIPS16_INSN_BRANCH): New. + +Wed Dec 9 10:38:48 1998 David Taylor + + The following is part of a change made by Edith Epstein + as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. + + * hppa.h (completer_chars): list of chars to not put a space + after. + +Sun Dec 6 13:21:34 1998 Ian Lance Taylor + + * i386.h (i386_optab): Permit w suffix on processor control and + status word instructions. + +1998-11-30 Doug Evans + + * cgen.h (struct cgen_hw_entry): Delete const on attrs member. + (struct cgen_keyword_entry): Ditto. + (struct cgen_operand): Ditto. + (CGEN_IFLD): New typedef, with associated access macros. + (CGEN_IFMT): New typedef, with associated access macros. + (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. + (CGEN_IVALUE): New typedef. + (struct cgen_insn): Delete const on syntax,attrs members. + `format' now points to format data. Type of `value' is now + CGEN_IVALUE. + (struct cgen_opcode_table): New member ifld_table. + +1998-11-18 Doug Evans + + * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. + (CGEN_OPERAND_INSTANCE): New member `attrs'. + (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. + (cgen_dis_lookup_insn): Update type of `base_insn' arg. + (cgen_opcode_table): Update type of dis_hash fn. + (extract_operand): Update type of `insn_value' arg. + +Thu Oct 29 11:38:36 1998 Doug Evans + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. + +Tue Oct 27 08:57:59 1998 Gavin Romig-Koch + + * mips.h (INSN_MULT): Added. + +Tue Oct 20 11:31:34 1998 Alan Modra + + * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. + +Mon Oct 19 12:50:00 1998 Doug Evans + + * cgen.h (CGEN_INSN_INT): New typedef. + (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. + (CGEN_INSN_BYTES): Renamed from cgen_insn_t. + (CGEN_INSN_BYTES_PTR): New typedef. + (CGEN_EXTRACT_INFO): New typedef. + (cgen_insert_fn,cgen_extract_fn): Update. + (cgen_opcode_table): New member `insn_endian'. + (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. + (insert_operand,extract_operand): Update. + (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. + +Fri Oct 9 13:38:13 1998 Doug Evans + + * cgen.h (CGEN_ATTR_BOOLS): New macro. + (struct CGEN_HW_ENTRY): New member `attrs'. + (CGEN_HW_ATTR): New macro. + (struct CGEN_OPERAND_INSTANCE): New member `name'. + (CGEN_INSN_INVALID_P): New macro. + +Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add "fid". + +Sun Oct 4 21:00:00 1998 Alan Modra + + From Robert Andrew Dale + * i386.h (i386_optab): Add AMD 3DNow! instructions. + (AMD_3DNOW_OPCODE): Define. + +Tue Sep 22 17:53:47 1998 Nick Clifton + + * d30v.h (EITHER_BUT_PREFER_MU): Define. + +Mon Aug 10 14:09:38 1998 Doug Evans + + * cgen.h (cgen_insn): #if 0 out element `cdx'. + +Mon Aug 3 12:21:57 1998 Doug Evans + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen.h (CGEN_OPCODE_DESC): New type. + (all fns): New first arg of opcode table descriptor. + (cgen_set_parse_operand_fn): Add prototype. + (cgen_current_machine,cgen_current_endian): Delete. + (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, + parse_operand_fn,asm_hash_table,asm_hash_table_entries, + dis_hash_table,dis_hash_table_entries. + (opcode_open,opcode_close): Add prototypes. + + * cgen.h (cgen_insn): New element `cdx'. + +Thu Jul 30 21:44:25 1998 Frank Ch. Eigler + + * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. + +Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "no_match_operands" field for instructions. + (MN10300_MAX_OPERANDS): Define. + +Fri Jul 24 11:44:24 1998 Doug Evans + + * cgen.h (cgen_macro_insn_count): Declare. + +Tue Jul 21 13:12:13 1998 Doug Evans + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. + (cgen_insert_fn,cgen_extract_fn): New arg `pc'. + (get_operand,put_operand): Replaced with get_{int,vma}_operand, + set_{int,vma}_operand. + +Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "machine" field for instructions. + (MN103, AM30): Define machine types. + +Fri Jun 19 16:09:09 1998 Alan Modra + + * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. + +1998-06-18 Ulrich Drepper + + * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. + +Sat Jun 13 11:31:35 1998 Alan Modra + + * i386.h (i386_optab): Add general form of aad and aam. Add ud2a + and ud2b. + (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just + those that happen to be implemented on pentiums. + +Tue Jun 9 12:16:01 1998 Alan Modra + + * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, + IgnoreDataSize to IgnoreSize. Flag address and data size prefixes + with Size16|IgnoreSize or Size32|IgnoreSize. + +Mon Jun 8 12:15:52 1998 Alan Modra + + * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. + (REPE): Rename to REPE_PREFIX_OPCODE. + (i386_regtab_end): Remove. + (i386_prefixtab, i386_prefixtab_end): Remove. + (i386_optab): Use NULL as sentinel rather than "" to suit rewrite + of md_begin. + (MAX_OPCODE_SIZE): Define. + (i386_optab_end): Remove. + (sl_Suf): Define. + (sl_FP): Use sl_Suf. + + * i386.h (i386_optab): Allow 16 bit displacement for `mov + mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 + bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, + data32, dword, and adword prefixes. + (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index + regs. + +Fri Jun 5 23:42:43 1998 Alan Modra + + * i386.h (i386_regtab): Remove BaseIndex modifier from esp. + + * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with + register operands, because this is a common idiom. Flag them with + a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, + fdivrp because gcc erroneously generates them. Also flag with a + warning. + + * i386.h: Add suffix modifiers to most insns, and tighter operand + checks in some cases. Fix a number of UnixWare compatibility + issues with float insns. Merge some floating point opcodes, using + new FloatMF modifier. + (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for + consistency. + + * i386.h: Change occurence of ShortformW to W|ShortForm. Add + IgnoreDataSize where appropriate. + +Wed Jun 3 18:28:45 1998 Alan Modra + + * i386.h: (one_byte_segment_defaults): Remove. + (two_byte_segment_defaults): Remove. + (i386_regtab): Add BaseIndex to 32 bit regs reg_type. + +Fri May 15 15:59:04 1998 Doug Evans + + * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): Declare. + +Thu May 7 09:27:58 1998 Frank Ch. Eigler + + * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower + ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" + +Thu May 7 02:14:08 1998 Doug Evans + + * cgen.h (cgen_asm_init_parse): Delete. + (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. + (cgen_asm_record_register,cgen_asm_finish_insn): Delete. + +Mon Apr 27 10:13:11 1998 Doug Evans + + * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. + (cgen_asm_finish_insn): Update prototype. + (cgen_insn): New members num, data. + (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, + dis_hash, dis_hash_table_size moved to ... + (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. + All uses updated. New members asm_hash_p, dis_hash_p. + (CGEN_MINSN_EXPANSION): New struct. + (cgen_expand_macro_insn): Declare. + (cgen_macro_insn_count): Declare. + (get_insn_operands): Update prototype. + (lookup_get_insn_operands): Declare. + +Tue Apr 21 17:11:32 1998 Alan Modra + + * i386.h (i386_optab): Change iclrKludge and imulKludge to + regKludge. Add operands types for string instructions. + +Mon Apr 20 14:40:29 1998 Tom Tromey + + * i386.h (X): Renamed from `Z_' to preserve formatting of opcode + table. + +Sun Apr 19 13:54:06 1998 Tom Tromey + + * i386.h (Z_): Renamed from `_' to avoid clash with common alias + for `gettext'. + +Fri Apr 3 12:04:48 1998 Alan Modra + + * i386.h: Remove NoModrm flag from all insns: it's never checked. + Add IsString flag to string instructions. + (IS_STRING): Don't define. + (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. + (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. + (SS_PREFIX_OPCODE): Define. + +Mon Mar 30 21:31:56 1998 Ian Lance Taylor + + * i386.h: Revert March 24 patch; no more LinearAddress. + +Mon Mar 30 10:25:54 1998 Alan Modra + + * i386.h (i386_optab): Remove fwait (9b) from all floating point + instructions, and instead add FWait opcode modifier. Add short + form of fldenv and fstenv. + (FWAIT_OPCODE): Define. + + * i386.h (i386_optab): Change second operand constraint of `mov + sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to + allow legal instructions such as `movl %gs,%esi' + +Fri Mar 27 18:30:52 1998 Ian Lance Taylor + + * h8300.h: Various changes to fully bracket initializers. + +Tue Mar 24 18:32:47 1998 H.J. Lu + + * i386.h: Set LinearAddress for lidt and lgdt. + +Mon Mar 2 10:44:07 1998 Doug Evans + + * cgen.h (CGEN_BOOL_ATTR): New macro. + +Thu Feb 26 15:54:31 1998 Michael Meissner + + * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. + +Mon Feb 23 10:38:21 1998 Doug Evans + + * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. + (cgen_insn): Record syntax and format entries here, rather than + separately. + +Tue Feb 17 21:42:56 1998 Nick Clifton + + * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. + +Tue Feb 17 16:00:56 1998 Doug Evans + + * cgen.h (cgen_insert_fn): Change type of result to const char *. + (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. + (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. + +Thu Feb 12 18:30:41 1998 Doug Evans + + * cgen.h (lookup_insn): New argument alias_p. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke + +Fix rac to accept only a0: + * d10v.h (OPERAND_ACC): Split into: + (OPERAND_ACC0, OPERAND_ACC1) . + (OPERAND_GPR): Define. + +Wed Feb 11 17:31:53 1998 Doug Evans + + * cgen.h (CGEN_FIELDS): Define here. + (CGEN_HW_ENTRY): New member `type'. + (hw_list): Delete decl. + (enum cgen_mode): Declare. + (CGEN_OPERAND): New member `hw'. + (enum cgen_operand_instance_type): Declare. + (CGEN_OPERAND_INSTANCE): New type. + (CGEN_INSN): New member `operands'. + (CGEN_OPCODE_DATA): Make hw_list const. + (get_insn_operands,lookup_insn): Add prototypes for. + +Tue Feb 3 17:11:23 1998 Doug Evans + + * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. + (CGEN_HW_ENTRY): Move `next' entry to end of struct. + (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. + (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. + +Mon Feb 2 19:19:15 1998 Ian Lance Taylor + + * cgen.h: Correct typo in comment end marker. + +Mon Feb 2 17:10:38 1998 Steve Haworth + + * tic30.h: New file. + +Thu Jan 22 17:54:56 1998 Nick Clifton + + * cgen.h: Add prototypes for cgen_save_fixups(), + cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype + of cgen_asm_finish_insn() to return a char *. + +Wed Jan 14 17:21:43 1998 Nick Clifton + + * cgen.h: Formatting changes to improve readability. + +Mon Jan 12 11:37:36 1998 Doug Evans + + * cgen.h (*): Clean up pass over `struct foo' usage. + (CGEN_ATTR): Make unsigned char. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_{ENTRY,TABLE}): New types. + (cgen_base): Move member `attrs' to cgen_insn. + (CGEN_KEYWORD): New member `null_entry'. + (CGEN_{SYNTAX,FORMAT}): New types. + (cgen_insn): Format and syntax separated from each other. + +Tue Dec 16 15:15:52 1997 Michael Meissner + + * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for + 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make + flags_{used,set} long. + (d30v_operand): Make flags field long. + +Mon Dec 1 12:24:44 1997 Andreas Schwab + + * m68k.h: Fix comment describing operand types. + +Sun Nov 23 22:31:27 1997 Michael Meissner + + * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move + everything else after down. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke + + * d10v.h (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + +Thu Nov 13 11:04:24 1997 Gavin Koch + + * mips.h (struct mips_opcode): Changed comments to reflect new + field usage. + +Fri Oct 24 22:36:20 1997 Ken Raeburn + + * mips.h: Added to comments a quick-ref list of all assigned + operand type characters. + (OP_{MASK,SH}_PERFREG): New macros. + +Wed Oct 22 17:28:33 1997 Richard Henderson + + * sparc.h: Add '_' and '/' for v9a asr's. + Patch from David Miller + +Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) + + * h8300.h: Bit ops with absolute addresses not in the 8 bit + area are not available in the base model (H8/300). + +Thu Sep 25 13:03:41 1997 Ian Lance Taylor + + * m68k.h: Remove documentation of ` operand specifier. + +Wed Sep 24 19:00:34 1997 Ian Lance Taylor + + * m68k.h: Document q and v operand specifiers. + +Mon Sep 15 18:28:37 1997 Nick Clifton + + * v850.h (struct v850_opcode): Add processors field. + (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. + (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. + (PROCESSOR_V850EA): New bit constants. + +Mon Sep 15 11:29:43 1997 Ken Raeburn + + Merge changes from Martin Hunt: + + * d30v.h: Allow up to 64 control registers. Add + SHORT_A5S format. + + * d30v.h (LONG_Db): New form for delayed branches. + + * d30v.h: (LONG_Db): New form for repeati. + + * d30v.h (SHORT_D2B): New form. + + * d30v.h (SHORT_A2): New form. + + * d30v.h (OPERAND_2REG): Add new operand to indicate 2 + registers are used. Needed for VLIW optimization. + +Mon Sep 8 14:05:45 1997 Doug Evans + + * cgen.h: Move assembler interface section + up so cgen_parse_operand_result is defined for cgen_parse_address. + (cgen_parse_address): Update prototype. + +Tue Sep 2 15:32:32 1997 Nick Clifton + + * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. + +Tue Aug 26 12:21:52 1997 Ian Lance Taylor + + * i386.h (two_byte_segment_defaults): Correct base register 5 in + modes 1 and 2 to be ss rather than ds. From Gabriel Paubert + . + + * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert + . + + * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert + . + + * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). + (JUMP_ON_ECX_ZERO): Remove commented out macro. + +Fri Aug 22 10:38:29 1997 Nick Clifton + + * v850.h (V850_NOT_R0): New flag. + +Mon Aug 18 11:05:58 1997 Nick Clifton + + * v850.h (struct v850_opcode): Remove flags field. + +Wed Aug 13 18:45:48 1997 Nick Clifton + + * v850.h (struct v850_opcode): Add flags field. + (struct v850_operand): Extend meaning of 'bits' and 'shift' + fields. + (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. + (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. + +Fri Aug 8 16:58:42 1997 Doug Evans + + * arc.h: New file. + +Thu Jul 24 21:16:58 1997 Doug Evans + + * sparc.h (sparc_opcodes): Declare as const. + +Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) + + * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn + uses single or double precision floating point resources. + (INSN_NO_ISA, INSN_ISA1): Define. + (cpu specific INSN macros): Tweak into bitmasks outside the range + of INSN_ISA field. + +Mon Jun 16 14:10:00 1997 H.J. Lu + + * i386.h: Fix pand opcode. + +Mon Jun 2 11:35:09 1997 Gavin Koch + + * mips.h: Widen INSN_ISA and move it to a more convenient + bit position. Add INSN_3900. + +Tue May 20 11:25:29 1997 Gavin Koch + + * mips.h (struct mips_opcode): added new field membership. + +Mon May 12 16:26:50 1997 H.J. Lu + + * i386.h (movd): only Reg32 is allowed. + + * i386.h: add fcomp and ud2. From Wayne Scott + . + +Mon May 5 17:16:21 1997 Ian Lance Taylor + + * i386.h: Add MMX instructions. + +Mon May 5 12:45:19 1997 H.J. Lu + + * i386.h: Remove W modifier from conditional move instructions. + +Mon Apr 14 14:56:58 1997 Ian Lance Taylor + + * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp + with no arguments to match that generated by the UnixWare + assembler. + +Thu Apr 10 14:35:00 1997 Doug Evans + + * cgen.h (_cgen_assemble_insn): New arg for errmsg. + (cgen_parse_operand_fn): Declare. + (cgen_init_parse_operand): Declare. + (cgen_parse_operand): Renamed from cgen_asm_parse_operand, + new argument `want'. + (enum cgen_parse_operand_result): Renamed from cgen_asm_result. + (enum cgen_parse_operand_type): New enum. + +Sat Apr 5 13:14:05 1997 Ian Lance Taylor + + * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases. + +Fri Apr 4 11:46:11 1997 Doug Evans + + * cgen.h: New file. + +Fri Apr 4 14:02:32 1997 Ian Lance Taylor + + * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and + fdivrp. + +Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h (extract): Make unsigned. + +Mon Mar 24 14:38:15 1997 Ian Lance Taylor + + * i386.h: Add iclr. + +Thu Mar 20 19:49:10 1997 Ian Lance Taylor + + * i386.h: Change DW to W for cmpxchg and xadd, since they don't + take a direction bit. + +Sat Mar 15 19:03:29 1997 H.J. Lu + + * sparc.h (sparc_opcode_lookup_arch): Use full prototype. + +Fri Mar 14 15:22:01 1997 Ian Lance Taylor + + * sparc.h: Include . Update function declarations to + use prototypes, and to use const when appropriate. + +Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_RELAX): Define. + +Mon Feb 24 15:15:56 1997 Martin M. Hunt + + * d10v.h: Change pre_defined_registers to + d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. + +Sat Feb 22 21:25:00 1997 Dawn Perchik + + * mips.h: Add macros for cop0, cop1 cop2 and cop3. + Change mips_opcodes from const array to a pointer, + and change bfd_mips_num_opcodes from const int to int, + so that we can increase the size of the mips opcodes table + dynamically. + +Fri Feb 21 16:34:18 1997 Martin M. Hunt + + * d30v.h (FLAG_X): Remove unused flag. + +Tue Feb 18 17:37:20 1997 Martin M. Hunt + + * d30v.h: New file. + +Fri Feb 14 13:16:15 1997 Fred Fish + + * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. + (PDS_VALUE): Macro to access value field of predefined symbols. + (tic80_next_predefined_symbol): Add prototype. + +Mon Feb 10 10:32:17 1997 Fred Fish + + * tic80.h (tic80_symbol_to_value): Change prototype to match + change in function, added class parameter. + +Thu Feb 6 17:30:15 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 + endmask fields, which are somewhat weird in that 0 and 32 are + treated exactly the same. + +Thu Jan 30 13:46:18 1997 Fred Fish + + * tic80.h: Change all the OPERAND defines to use the form (1 << X) + rather than a constant that is 2**X. Reorder them to put bits for + operands that have symbolic names in the upper bits, so they can + be packed into an int where the lower bits contain the value that + corresponds to that symbolic name. + (predefined_symbo): Add struct. + (tic80_predefined_symbols): Declare array of translations. + (tic80_num_predefined_symbols): Declare size of that array. + (tic80_value_to_symbol): Declare function. + (tic80_symbol_to_value): Declare function. + +Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200.h (MN10200_OPERAND_RELAX): Define. + +Sat Jan 18 15:18:59 1997 Fred Fish + + * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot + be the destination register. + +Thu Jan 16 20:48:55 1997 Fred Fish + + * tic80.h (struct tic80_opcode): Change "format" field to "flags". + (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. + (TIC80_VECTOR): Define a flag bit for the flags. This one means + that the opcode can have two vector instructions in a single + 32 bit word and we have to encode/decode both. + +Tue Jan 14 19:37:09 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_PCREL): Renamed from + TIC80_OPERAND_RELATIVE for PC relative. + (TIC80_OPERAND_BASEREL): New flag bit for register + base relative. + +Mon Jan 13 15:56:38 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. + +Mon Jan 6 10:51:15 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional + ":s" modifier for scaling. + +Sun Jan 5 12:12:19 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". + (TIC80_OPERAND_M_LI): Ditto + +Sat Jan 4 19:02:44 1997 Fred Fish + + * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. + (TIC80_OPERAND_CC): New define for condition code operand. + (TIC80_OPERAND_CR): New define for control register operand. + +Fri Jan 3 16:22:23 1997 Fred Fish + + * tic80.h (struct tic80_opcode): Name changed. + (struct tic80_opcode): Remove format field. + (struct tic80_operand): Add insertion and extraction functions. + (TIC80_OPERAND_*): Remove old bogus values, start adding new + correct ones. + (FMT_*): Ditto. + +Tue Dec 31 15:05:41 1996 Michael Meissner + + * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust + type IV instruction offsets. + +Fri Dec 27 22:23:10 1996 Fred Fish + + * tic80.h: New file. + +Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200.h (MN10200_OPERAND_NOCHECK): Define. + +Sat Dec 14 10:48:31 1996 Fred Fish + + * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. + * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. + * v850.h: Fix comment, v850_operand not powerpc_operand. + +Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200.h: Flesh out structures and definitions needed by + the mn10200 assembler & disassembler. + +Tue Nov 26 10:46:56 1996 Ian Lance Taylor + + * mips.h: Add mips16 definitions. + +Mon Nov 25 17:56:54 1996 J.T. Conklin + + * m68k.h: Document new <, >, m, n, o and p operand specifiers. + +Wed Nov 20 10:59:41 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_PCREL): Define. + (MN10300_OPERAND_MEMADDR): Define. + +Tue Nov 19 13:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_REG_LIST): Define. + +Wed Nov 6 13:41:08 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_SPLIT): Define. + +Tue Nov 5 13:26:12 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_EXTENDED): Define. + +Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_REPEATED): Define. + +Fri Nov 1 10:31:02 1996 Richard Henderson + + * alpha.h: Don't include "bfd.h"; private relocation types are now + negative to minimize problems with shared libraries. Organize + instruction subsets by AMASK extensions and PALcode + implementation. + (struct alpha_operand): Move flags slot for better packing. + +Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_RELAX): New operand flag. + +Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (FMT_*): Move operand format definitions + here. + +Tue Oct 8 14:48:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (MN10300_OPERAND_PAREN): Define. + +Mon Oct 7 16:52:11 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (mn10300_opcode): Add "format" field. + (MN10300_OPERAND_*): Define. + +Thu Oct 3 10:33:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00.h: Delete. + * mn10200.h, mn10300.h: New files. + +Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00.h: New file. + +Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850.h: Add new flag to indicate this instruction uses a PC + displacement. + +Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (stmac): Add missing instruction. + +Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (v850_opcode): Remove "size" field. Add "memop" + field. + +Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) + + * v850.h (V850_OPERAND_EP): Define. + + * v850.h (v850_opcode): Add size field. + +Thu Aug 22 16:51:25 1996 J.T. Conklin + + * v850.h (v850_operands): Add insert and extract fields, pointers + to functions used to handle unusual operand encoding. + (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, + V850_OPERAND_SIGNED): Defined. + +Wed Aug 21 17:45:10 1996 J.T. Conklin + + * v850.h (v850_operands): Add flags field. + (OPERAND_REG, OPERAND_NUM): Defined. + +Tue Aug 20 14:52:02 1996 J.T. Conklin + + * v850.h: New file. + +Fri Aug 16 14:44:15 1996 James G. Smith + + * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, + OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, + OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, + OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, + OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): + Defined. + +Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept + a 3 bit space id instead of a 2 bit space id. + +Thu Aug 15 13:11:46 1996 Martin M. Hunt + + * d10v.h: Add some additional defines to support the + assembler in determining which operations can be done in parallel. + +Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (SN): Define. + (eepmov.b): Renamed from "eepmov" + (nop, bpt, rte, rts, sleep, clrmac): These have no size associated + with them. + +Fri Jul 26 11:47:10 1996 Martin M. Hunt + + * d10v.h (OPERAND_SHIFT): New operand flag. + +Thu Jul 25 12:06:22 1996 Martin M. Hunt + + * d10v.h: Changes for divs, parallel-only instructions, and + signed numbers. + +Mon Jul 22 11:21:15 1996 Martin M. Hunt + + * d10v.h (pd_reg): Define. Putting the definition here allows + the assembler and disassembler to share the same struct. + +Mon Jul 22 12:15:25 1996 Ian Lance Taylor + + * i960.h (i960_opcodes): "halt" takes an argument. From Stephen + Williams . + +Wed Jul 17 14:46:38 1996 Martin M. Hunt + + * d10v.h: New file. + +Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (band, bclr): Force high bit of immediate nibble to zero. + +Wed Jul 3 14:30:12 1996 J.T. Conklin + + * m68k.h (mcf5200): New macro. + Document names of coldfire control registers. + +Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (SRC_IN_DST): Define. + + * h8300.h (UNOP3): Mark the register operand in this insn + as a source operand, not a destination operand. + (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references. + (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark + register operand with SRC_IN_DST. + +Fri Jun 21 13:52:17 1996 Richard Henderson + + * alpha.h: New file. + +Thu Jun 20 15:02:57 1996 Ian Lance Taylor + + * rs6k.h: Remove obsolete file. + +Wed Jun 19 15:29:38 1996 Ian Lance Taylor + + * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp, + fdivp, and fdivrp. Add ffreep. + +Tue Jun 18 16:06:00 1996 Jeffrey A. Law + + * h8300.h: Reorder various #defines for readability. + (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define. + (BITOP): Accept additional (unused) argument. All callers changed. + (EBITOP): Likewise. + (O_LAST): Bump. + (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. + + * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. + (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. + (BITOP, EBITOP): Handle new H8/S addressing modes for + bit insns. + (UNOP3): Handle new shift/rotate insns on the H8/S. + (insns using exr): New instructions. + (tas, mac, ldmac, clrmac, ldm, stm): New instructions. + +Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (add.l): Undo Apr 5th change. The manual I had + was incorrect. + +Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (START): Remove. + (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w + and mov.l insns that can be relaxed. + +Tue Apr 30 18:30:58 1996 Ian Lance Taylor + + * i386.h: Remove Abs32 from lcall. + +Mon Apr 22 17:09:23 1996 Doug Evans + + * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro. + (SLCPOP): New macro. + Mark X,Y opcode letters as in use. + +Thu Apr 11 17:28:18 1996 Ian Lance Taylor + + * sparc.h (F_FLOAT, F_FBR): Define. + +Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com) + + * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV + from all insns. + (ABS8SRC,ABS8DST): Add ABS8MEM. + (add.l): Fix reg+reg variant. + (eepmov.w): Renamed from eepmovw. + (ldc,stc): Fix many cases. + +Sun Mar 31 13:30:03 1996 Doug Evans + + * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro. + +Thu Mar 7 15:08:23 1996 Doug Evans + + * sparc.h (O): Mark operand letter as in use. + +Tue Feb 20 20:46:21 1996 Doug Evans + + * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. + Mark operand letters uU as in use. + +Mon Feb 19 01:59:08 1996 Doug Evans + + * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET. + (sparc_opcode_arch): Delete member `conflicts'. Add `supported'. + (SPARC_OPCODE_SUPPORTED): New macro. + (SPARC_OPCODE_CONFLICT_P): Rewrite. + (F_NOTV9): Delete. + +Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com) + + * sparc.h (sparc_opcode_lookup_arch) Make return type in + declaration consistent with return type in definition. + +Wed Feb 14 18:14:11 1996 Alan Modra + + * i386.h (i386_optab): Remove Data32 from pushf and popf. + +Thu Feb 8 14:27:21 1996 James Carlson + + * i386.h (i386_regtab): Add 80486 test registers. + +Mon Feb 5 18:35:46 1996 Ian Lance Taylor + + * i960.h (I_HX): Define. + (i960_opcodes): Add HX instruction. + +Mon Jan 29 12:43:39 1996 Ken Raeburn + + * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw, + and fclex. + +Wed Jan 24 22:36:59 1996 Doug Evans + + * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. + (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. + (bfd_* defines): Delete. + (sparc_opcode_archs): Replaces architecture_pname. + (sparc_opcode_lookup_arch): Declare. + (NUMOPCODES): Delete. + +Mon Jan 22 08:24:32 1996 Doug Evans + + * sparc.h (enum sparc_architecture): Add v9a. + (ARCHITECTURES_CONFLICT_P): Update. + +Thu Dec 28 13:27:53 1995 John Hassey + + * i386.h: Added Pentium Pro instructions. + +Thu Nov 2 22:59:22 1995 Ian Lance Taylor + + * m68k.h: Document new 'W' operand place. + +Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add lci and syncdma instructions. + +Mon Oct 23 11:09:16 1995 James G. Smith + + * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific + instructions. + +Mon Oct 16 10:28:15 1995 Michael Meissner + + * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for + assembler's -mcom and -many switches. + +Wed Oct 11 16:56:33 1995 Ken Raeburn + + * i386.h: Fix cmpxchg8b extension opcode description. + +Thu Oct 5 18:03:36 1995 Ken Raeburn + + * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b, + and register cr4. + +Tue Sep 19 15:26:43 1995 Ian Lance Taylor + + * m68k.h: Change comment: split type P into types 0, 1 and 2. + +Wed Aug 30 13:50:55 1995 Doug Evans + + * sparc.h (sparc_{encode,decode}_prefetch): Declare. + +Tue Aug 29 15:34:58 1995 Doug Evans + + * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare. + +Wed Aug 2 18:32:19 1995 Ian Lance Taylor + + * m68kmri.h: Remove. + + * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the + declarations. Remove F_ALIAS and flag field of struct + m68k_opcode. Change arch field of struct m68k_opcode to unsigned + int. Make name and args fields of struct m68k_opcode const. + +Wed Aug 2 08:16:46 1995 Doug Evans + + * sparc.h (F_NOTV9): Define. + +Tue Jul 11 14:20:42 1995 Jeff Spiegel + + * mips.h (INSN_4010): Define. + +Wed Jun 21 18:49:51 1995 Ken Raeburn + + * m68k.h (TBL1): Reverse sense of "round" argument in result. + + Changes from Andreas Schwab : + * m68k.h: Fix argument descriptions of coprocessor + instructions to allow only alterable operands where appropriate. + [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. + (m68k_opcode_aliases): Add more aliases. + +Fri Apr 14 22:15:34 1995 Ken Raeburn + + * m68k.h: Added explcitly short-sized conditional branches, and a + bunch of aliases (fmov*, ftest*, tdivul) to support gcc's + svr4-based configurations. + +Mon Mar 13 21:30:01 1995 Ken Raeburn + + Mon Feb 27 08:36:39 1995 Bryan Ford + * i386.h: added missing Data16/Data32 flags to a few instructions. + +Wed Mar 8 15:19:53 1995 Ian Lance Taylor + + * mips.h (OP_MASK_FR, OP_SH_FR): Define. + (OP_MASK_BCC, OP_SH_BCC): Define. + (OP_MASK_PREFX, OP_SH_PREFX): Define. + (OP_MASK_CCC, OP_SH_CCC): Define. + (INSN_READ_FPR_R): Define. + (INSN_RFE): Delete. + +Wed Mar 8 03:13:23 1995 Ken Raeburn + + * m68k.h (enum m68k_architecture): Deleted. + (struct m68k_opcode_alias): New type. + (m68k_opcodes): Now const. Deleted opcode aliases with exactly + matching constraints, values and flags. As a side effect of this, + the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far + as I know were never used, now may need re-examining. + (numopcodes): Now const. + (m68k_opcode_aliases, numaliases): New variables. + (endop): Deleted. + [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and + m68k_opcode_aliases; update declaration of m68k_opcodes. + +Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (delay_type): Delete unused enumeration. + (pa_opcode): Replace unused delayed field with an architecture + field. + (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1. + +Fri Mar 3 16:10:24 1995 Ian Lance Taylor + + * mips.h (INSN_ISA4): Define. + +Fri Feb 24 19:13:37 1995 Ian Lance Taylor + + * mips.h (M_DLA_AB, M_DLI): Define. + +Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa.h (fstwx): Fix single-bit error. + +Wed Feb 15 12:19:52 1995 Ian Lance Taylor + + * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. + +Mon Feb 6 10:35:23 1995 J.T. Conklin + + * i386.h: added cpuid instruction , and dr[0-7] aliases for the + debug registers. From Charles Hannum (mycroft@netbsd.org). + +Mon Feb 6 03:31:54 1995 Ken Raeburn + + Changes from Bryan Ford for 16-bit + i386 support: + * i386.h (MOV_AX_DISP32): New macro. + (i386_optab): Added Data16 and Data32 as needed. Added "w" forms + of several call/return instructions. + (ADDR_PREFIX_OPCODE): New macro. + +Mon Jan 23 16:45:43 1995 Ken Raeburn + + Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu) + + * vax.h (struct vot_wot, field `args'): Make it pointer to const + char. + (struct vot, field `name'): ditto. + +Thu Jan 19 14:47:53 1995 Ken Raeburn + + * vax.h: Supply and properly group all values in end sentinel. + +Tue Jan 17 10:55:30 1995 Ian Lance Taylor + + * mips.h (INSN_ISA, INSN_4650): Define. + +Wed Oct 19 13:34:17 1994 Ian Lance Taylor + + * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On + systems with a separate instruction and data cache, such as the + 29040, these instructions take an optional argument. + +Wed Sep 14 17:44:20 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with + INSN_TRAP. + +Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips.h (INSN_STORE_MEMORY): Define. + +Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc.h: Document new operand type 'x'. + +Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960.h (I_CX2): New instruction category. It includes + instructions available on Cx and Jx processors. + (I_JX): New instruction category, for JX-only instructions. + (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added + Jx-only instructions, in I_JX category. + +Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * ns32k.h (endop): Made pointer const too. + +Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * ns32k.h: Drop Q operand type as there is no correct use + for it. Add I and Z operand types which allow better checking. + +Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * h8300.h (xor.l) :fix bit pattern. + (L_2): New size of operand. + (trapa): Use it. + +Fri Jun 10 16:38:11 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68k.h: Move "trap" before "tpcc" to change disassembly. + +Fri Jun 3 15:57:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc.h: Include v9 definitions. + +Thu Jun 2 12:23:17 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * m68k.h (m68060): Defined. + (m68040up, mfloat, mmmu): Include it. + (struct m68k_opcode): Widen `arch' field. + (m68k_opcodes): Updated for M68060. Removed comments that were + instructions commented out by "JF" years ago. + +Thu Apr 28 18:31:14 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and + add a one-bit `flags' field. + (F_ALIAS): New macro. + +Wed Apr 27 11:29:52 1994 Steve Chamberlain (sac@cygnus.com) + + * h8300.h (dec, inc): Get encoding right. + +Mon Apr 4 13:12:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (struct powerpc_operand): Removed signedp field; just use + a flag instead. + (PPC_OPERAND_SIGNED): Define. + (PPC_OPERAND_SIGNOPT): Define. + +Thu Mar 31 19:34:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size + prefix is 0x66, not 0x67. Patch from H.J. Lu (hlu@nynexst.com). + +Thu Mar 3 15:51:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h: Reverse last change. It'll be handled in gas instead. + +Thu Feb 24 15:29:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (sar): Disabled the two-operand Imm1 form, since it was + slower on the 486 and used the implicit shift count despite the + explicit operand. The one-operand form is still available to get + the shorter form with the implicit shift count. + +Thu Feb 17 12:27:52 1994 Torbjorn Granlund (tege@mexican.cygnus.com) + + * hppa.h: Fix typo in fstws arg string. + +Wed Feb 9 21:23:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (struct powerpc_opcode): Make operands field unsigned. + +Mon Feb 7 19:14:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (PPC_OPCODE_601): Define. + +Fri Feb 4 23:43:50 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h (addb): Use '@' for addb and addib pseudo ops. + (so we can determine valid completers for both addb and addb[tf].) + + * hppa.h (xmpyu): No floating point format specifier for the + xmpyu instruction. + +Fri Feb 4 23:36:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h (PPC_OPERAND_NEXT): Define. + (PPC_OPERAND_NEGATIVE): Change value to make room for above. + (struct powerpc_macro): Define. + (powerpc_macros, powerpc_num_macros): Declare. + +Fri Jan 21 19:13:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc.h: New file. Header file for PowerPC opcode table. + +Mon Jan 17 00:14:23 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: More minor template fixes for sfu and copr (to allow + for easier disassembly). + + * hppa.h: Fix templates for all the sfu and copr instructions. + +Wed Dec 15 15:12:42 1993 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i386.h (push): Permit Imm16 operand too. + +Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8300.h (andc): Exists in base arch. + +Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * From Hisashi MINAMINO + * hppa.h: #undef NONE to avoid conflict with hiux include files. + +Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: Add FP quadword store instructions. + +Wed Nov 17 17:13:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: (M_J_A): Added. + (M_LA): Removed. + +Mon Nov 8 12:12:47 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon + . + +Sun Nov 7 00:30:11 1993 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa.h: Immediate field in probei instructions is unsigned, + not low-sign extended. + +Wed Nov 3 10:30:00 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00. + +Tue Nov 2 12:41:30 1993 Ken Raeburn (raeburn@rover.cygnus.com) + + * i386.h: Add "fxch" without operand. + +Mon Nov 1 18:13:03 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added. + +Sat Oct 2 22:26:11 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa.h: Add gfw and gfr to the opcode table. + +Wed Sep 29 16:23:00 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k.h: extended to handle m88110. + +Tue Sep 28 19:19:08 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa.h (be, ble): Use operand type 'z' to denote absolute branch + addresses. + +Tue Sep 14 14:04:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960.h (i960_opcodes): Properly bracket initializers. + +Mon Sep 13 12:50:52 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k.h (BOFLAG): rewrite to avoid nested comment. + +Mon Sep 13 15:46:06 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68k.h (two): Protect second argument with parentheses. + +Fri Sep 10 16:29:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * i386.h (i386_optab): Added new instruction "rsm" (for i386sl). + Deleted old in/out instructions in "#if 0" section. + +Thu Sep 9 17:42:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h (i386_optab): Properly bracket initializers. + +Wed Aug 25 13:50:56 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From + Jeff Law, law@cs.utah.edu). + +Mon Aug 23 16:55:03 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * i386.h (lcall): Accept Imm32 operand also. + +Mon Aug 23 12:43:11 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (M_ABSU): Removed (absolute value of unsigned number??). + (M_DABS): Added. + +Thu Aug 19 15:08:37 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (INSN_*): Changed values. Removed unused definitions. + Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split + INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and + INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into + INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY. + (M_*): Added new values for r6000 and r4000 macros. + (ANY_DELAY): Removed. + +Wed Aug 18 15:37:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Added M_LI_S and M_LI_SS. + +Tue Aug 17 07:08:08 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300.h: Get some rare mov.bs correct. + +Thu Aug 5 09:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc.h: Don't define const ourself; rely on ansidecl.h having + been included. + +Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com) + + * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark + jump instructions, for use in disassemblers. + +Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * m88k.h: Make bitfields just unsigned, not unsigned long or + unsigned short. + +Wed Jul 21 11:55:31 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa.h: New argument type 'y'. Use in various float instructions. + +Mon Jul 19 17:17:03 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa.h (break): First immediate field is unsigned. + + * hppa.h: Add rfir instruction. + +Sun Jul 18 16:28:08 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * mips.h: Split the actual table out into ../../opcodes/mips-opc.c. + +Fri Jul 16 09:59:29 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: Reworked the hazard information somewhat, and fixed some + bugs in the instruction hazard descriptions. + +Thu Jul 15 12:42:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k.h: Corrected a couple of opcodes. + +Tue Jul 6 15:17:35 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h: Replaced with version from Ralph Campbell and OSF. The + new version includes instruction hazard information, but is + otherwise reasonably similar. + +Thu Jul 1 20:36:17 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l). + +Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) + + Patches from Jeff Law, law@cs.utah.edu: + * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. + Make the tables be the same for the following instructions: + "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", + "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", + "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", + "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", + "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", + "fcmp", and "ftest". + + * hppa.h: Make new and old tables the same for "break", "mtctl", + "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub". + Fix typo in last patch. Collapse several #ifdefs into a + single #ifdef. + + * hppa.h: Delete remaining OLD_TABLE code. Bring some + of the comments up-to-date. + + * hppa.h: Update "free list" of letters and update + comments describing each letter's function. + +Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300.h: Lots of little fixes for the h8/300h. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * h8300.h: Lots of new opcodes. + +Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300.h: checkpoint, includes H8/300-H opcodes. + +Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) + + * Patches from Jeffrey Law . + * hppa.h: Rework single precision FP + instructions so that they correctly disassemble code + PA1.1 code. + +Thu May 27 19:21:22 1993 Bruce Bauman (boot@osf.org) + + * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from + mov to allow instructions like mov ss,xyz(ecx) to assemble. + +Tue May 25 00:39:40 1993 Ken Raeburn (raeburn@cygnus.com) + + * hppa.h: Use new version from Utah if OLD_TABLE isn't defined; + gdb will define it for now. + +Mon May 24 15:20:06 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * sparc.h: Don't end enumerator list with comma. + +Fri May 14 15:15:50 1993 Ian Lance Taylor (ian@cygnus.com) + + * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): + * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define. + ("bc2t"): Correct typo. + ("[ls]wc[023]"): Use T rather than t. + ("c[0123]"): Define general coprocessor instructions. + +Mon May 10 06:02:25 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * m68k.h: Move split point for gcc compilation more towards + middle. + +Fri Apr 9 13:26:16 1993 Jim Kingdon (kingdon@cygnus.com) + + * rs6k.h: Clean up instructions for primary opcode 19 (many were + simply wrong, ics, rfi, & rfsvc were missing). + Add "a" to opr_ext for "bb". Doc fix. + +Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com) + + * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com). + * mips.h: Add casts, to suppress warnings about shifting too much. + * m68k.h: Document the placement code '9'. + +Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) + + * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which + allows callers to break up the large initialized struct full of + opcodes into two half-sized ones. This permits GCC to compile + this module, since it takes exponential space for initializers. + (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. + +Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com) + + * a29k.h: Remove RCS crud, update GPL to v2, update copyrights. + * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all + initialized structs in it. + +Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com) + + Delta 88 changes inspired by Carl Greco, : + * m88k.h (PMEM): Avoid previous definition from . + (AND): Change to AND_ to avoid ansidecl.h `AND' conflict. + +Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com) + + * mips.h: document "i" and "j" operands correctly. + +Thu Jan 7 15:58:13 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h: Removed endianness dependency. + +Sun Jan 3 14:13:35 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8300.h: include info on number of cycles per instruction. + +Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com) + + * hppa.h: Move handy aliases to the front. Fix masks for extract + and deposit instructions. + +Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: accept shld and shrd both with and without the shift + count argument, which is always %cl. + +Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com) + + * i386.h (i386_optab_end, i386_regtab_end): Now const. + (one_byte_segment_defaults, two_byte_segment_defaults, + i386_prefixtab_end): Ditto. + +Mon Nov 23 10:47:25 1992 Ken Raeburn (raeburn@cygnus.com) + + * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand) + for operand 2; from John Carr, jfc@dsg.dec.com. + +Wed Nov 4 07:36:49 1992 Ken Raeburn (raeburn@cygnus.com) + + * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions + always use 16-bit offsets. Makes calculated-size jump tables + feasible. + +Fri Oct 16 22:52:43 1992 Ken Raeburn (raeburn@cygnus.com) + + * i386.h: Fix one-operand forms of in* and out* patterns. + +Tue Sep 22 14:08:14 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * m68k.h: Added CPU32 support. + +Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com) + + * mips.h (break): Disassemble the argument. Patch from + jonathan@cs.stanford.edu (Jonathan Stone). + +Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com) + + * m68k.h: merged Motorola and MIT syntax. + +Thu Sep 3 09:33:22 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68k.h (pmove): make the tests less strict, the 68k book is + wrong. + +Tue Aug 25 23:25:19 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * m68k.h (m68ec030): Defined as alias for 68030. + (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" + for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use + them. Tightened description of "fmovex" to distinguish it from + some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned + up descriptions that claimed versions were available for chips not + supporting them. Added "pmovefd". + +Mon Aug 24 12:04:51 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68k.h: fix where the . goes in divull + +Wed Aug 19 11:22:24 1992 Ian Lance Taylor (ian@cygnus.com) + + * m68k.h: the cas2 instruction is supposed to be written with + indirection on the last two operands, which can be either data or + address registers. Added a new operand type 'r' which accepts + either register type. Added new cases for cas2l and cas2w which + use them. Corrected masks for cas2 which failed to recognize use + of address register. + +Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com) + + * m68k.h: Merged in patches (mostly m68040-specific) from + Colin Smith . + + * m68k.h: Merged m68kmri.h and m68k.h (using the former as a + base). Also cleaned up duplicates, re-ordered instructions for + the sake of dis-assembling (so aliases come after standard names). + * m68kmri.h: Now just defines some macros, and #includes m68k.h. + +Wed Aug 12 16:38:15 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in + all missing .s + +Mon Aug 10 23:22:33 1992 Ken Raeburn (raeburn@cygnus.com) + + * sparc.h: Moved tables to BFD library. + + * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc. + +Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com) + + * h8300.h: Finish filling in all the holes in the opcode table, + so that the Lucid C compiler can digest this as well... + +Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com) + + * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases. + Fix opcodes on various sizes of fild/fist instructions + (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix). + Use tabs to indent for comments. Fixes suggested by Minh Tran-Le. + +Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com) + + * h8300.h: Fill in all the holes in the opcode table so that the + losing HPUX C compiler can digest this... + +Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com) + + * mips.h: Fix decoding of coprocessor instructions, somewhat. + (Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.) + +Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com) + + * sparc.h: Add new architecture variant sparclite; add its scan + and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro. + +Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com) + + * mips.h: Add some more opcode synonyms (from Frank Yellin, + fy@lucid.com). + +Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com) + + * rs6k.h: New version from IBM (Metin). + +Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com) + + * rs6k.h: Fix incorrect extended opcode for instructions `fm' + and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).) + +Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com) + + * rs6k.h: Move from ../../gdb/rs6k-opcode.h. + +Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com) + + * m68k.h (one, two): Cast macro args to unsigned to suppress + complaints from compiler and lint about integer overflow during + shift. + +Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com) + + * sparc.h (OP): Avoid signed overflow when shifting to high order bit. + +Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com) + + * mips.h: Make bitfield layout depend on the HOST compiler, + not on the TARGET system. + +Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com) + + * i386.h: added inb, inw, outb, outw opcodes, added att syntax for + scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le + . + +Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * h8300.h: turned op_type enum into #define list + +Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com) + + * sparc.h: Remove "cypress" architecture. Remove "fitox" and + similar instructions -- they've been renamed to "fitoq", etc. + REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong + number of arguments. + * h8300.h: Remove extra ; which produces compiler warning. + +Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com) + + * sparc.h: fix opcode for tsubcctv. + +Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com) + + * sparc.h: fba and cba are now aliases for fb and cb respectively. + +Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com) + + * sparc.h (nop): Made the 'lose' field be even tighter, + so only a standard 'nop' is disassembled as a nop. + +Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com) + + * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is + disassembled as a nop. + +Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) + + * m68k.h, sparc.h: ANSIfy enums. + +Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * sparc.h: fix a typo. + +Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, + m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, + vax.h: Renamed from ../-opcode.h. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/include/opcode/alpha.h b/external/gpl3/gdb/dist/include/opcode/alpha.h new file mode 100644 index 000000000000..2c0d4f6cc740 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/alpha.h @@ -0,0 +1,238 @@ +/* alpha.h -- Header file for Alpha opcode table + Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc. + Contributed by Richard Henderson , + patterned after the PPC opcode table written by Ian Lance Taylor. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef OPCODE_ALPHA_H +#define OPCODE_ALPHA_H + +/* The opcode table is an array of struct alpha_opcode. */ + +struct alpha_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned mask; + + /* One bit flags for the opcode. These are primarily used to + indicate specific processors and environments support the + instructions. The defined values are listed below. */ + unsigned flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[4]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct alpha_opcode alpha_opcodes[]; +extern const unsigned alpha_num_opcodes; + +/* Values defined for the flags field of a struct alpha_opcode. */ + +/* CPU Availability */ +#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ +#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ +#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ +#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ +#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ +#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ +#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ + +#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) + +/* A macro to extract the major opcode from an instruction. */ +#define AXP_OP(i) (((i) >> 26) & 0x3F) + +/* The total number of major opcodes. */ +#define AXP_NOPS 0x40 + + +/* The operands table is an array of struct alpha_operand. */ + +struct alpha_operand +{ + /* The number of bits in the operand. */ + unsigned int bits : 5; + + /* How far the operand is left shifted in the instruction. */ + unsigned int shift : 5; + + /* The default relocation type for this operand. */ + signed int default_reloc : 16; + + /* One bit syntax flags. */ + unsigned int flags : 16; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned (*insert) (unsigned instruction, int op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & AXP_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + int (*extract) (unsigned instruction, int *invalid); +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the alpha_opcodes table. */ + +extern const struct alpha_operand alpha_operands[]; +extern const unsigned alpha_num_operands; + +/* Values defined for the flags field of a struct alpha_operand. */ + +/* Mask for selecting the type for typecheck purposes */ +#define AXP_OPERAND_TYPECHECK_MASK \ + (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ + AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ + AXP_OPERAND_UNSIGNED) + +/* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics, for which two operands fields + are identical. The assembler should call the insert function with + any op value. The disassembler should call the extract function, + ignore the return value, and check the value placed in the invalid + argument. */ +#define AXP_OPERAND_FAKE 01 + +/* The operand should be wrapped in parentheses rather than separated + from the previous by a comma. This is used for the load and store + instructions which want their operands to look like "Ra,disp(Rb)". */ +#define AXP_OPERAND_PARENS 02 + +/* Used in combination with PARENS, this supresses the supression of + the comma. This is used for "jmp Ra,(Rb),hint". */ +#define AXP_OPERAND_COMMA 04 + +/* This operand names an integer register. */ +#define AXP_OPERAND_IR 010 + +/* This operand names a floating point register. */ +#define AXP_OPERAND_FPR 020 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define AXP_OPERAND_RELATIVE 040 + +/* This operand takes signed values. */ +#define AXP_OPERAND_SIGNED 0100 + +/* This operand takes unsigned values. This exists primarily so that + a flags value of 0 can be treated as end-of-arguments. */ +#define AXP_OPERAND_UNSIGNED 0200 + +/* Supress overflow detection on this field. This is used for hints. */ +#define AXP_OPERAND_NOOVERFLOW 0400 + +/* Mask for optional argument default value. */ +#define AXP_OPERAND_OPTIONAL_MASK 07000 + +/* This operand defaults to zero. This is used for jump hints. */ +#define AXP_OPERAND_DEFAULT_ZERO 01000 + +/* This operand should default to the first (real) operand and is used + in conjunction with AXP_OPERAND_OPTIONAL. This allows + "and $0,3,$0" to be written as "and $0,3", etc. I don't like + it, but it's what DEC does. */ +#define AXP_OPERAND_DEFAULT_FIRST 02000 + +/* Similarly, this operand should default to the second (real) operand. + This allows "negl $0" instead of "negl $0,$0". */ +#define AXP_OPERAND_DEFAULT_SECOND 04000 + + +/* Register common names */ + +#define AXP_REG_V0 0 +#define AXP_REG_T0 1 +#define AXP_REG_T1 2 +#define AXP_REG_T2 3 +#define AXP_REG_T3 4 +#define AXP_REG_T4 5 +#define AXP_REG_T5 6 +#define AXP_REG_T6 7 +#define AXP_REG_T7 8 +#define AXP_REG_S0 9 +#define AXP_REG_S1 10 +#define AXP_REG_S2 11 +#define AXP_REG_S3 12 +#define AXP_REG_S4 13 +#define AXP_REG_S5 14 +#define AXP_REG_FP 15 +#define AXP_REG_A0 16 +#define AXP_REG_A1 17 +#define AXP_REG_A2 18 +#define AXP_REG_A3 19 +#define AXP_REG_A4 20 +#define AXP_REG_A5 21 +#define AXP_REG_T8 22 +#define AXP_REG_T9 23 +#define AXP_REG_T10 24 +#define AXP_REG_T11 25 +#define AXP_REG_RA 26 +#define AXP_REG_PV 27 +#define AXP_REG_T12 27 +#define AXP_REG_AT 28 +#define AXP_REG_GP 29 +#define AXP_REG_SP 30 +#define AXP_REG_ZERO 31 + +#endif /* OPCODE_ALPHA_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/arc.h b/external/gpl3/gdb/dist/include/opcode/arc.h new file mode 100644 index 000000000000..695fec1ea8c8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/arc.h @@ -0,0 +1,322 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and + the GNU Binutils. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* List of the various cpu types. + The tables currently use bit masks to say whether the instruction or + whatever is supported by a particular cpu. This lets us have one entry + apply to several cpus. + + The `base' cpu must be 0. The cpu type is treated independently of + endianness. The complete `mach' number includes endianness. + These values are internal to opcodes/bfd/binutils/gas. */ +#define ARC_MACH_5 0 +#define ARC_MACH_6 1 +#define ARC_MACH_7 2 +#define ARC_MACH_8 4 + +/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ +#define ARC_MACH_BIG 16 + +/* Mask of number of bits necessary to record cpu type. */ +#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) + +/* Mask of number of bits necessary to record cpu type + endianness. */ +#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) + +/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ + +typedef unsigned int arc_insn; + +struct arc_opcode { + char *syntax; /* syntax of insn */ + unsigned long mask, value; /* recognize insn if (op&mask) == value */ + int flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) + +/* Return MACH number, given flag bits. */ +#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* First opcode flag bit available after machine mask. */ +#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) + +/* This insn is a conditional branch. */ +#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) +#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) +#define SYNTAX_LENGTH (SYNTAX_3OP ) +#define SYNTAX_2OP (SYNTAX_3OP << 1) +#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) +#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) +#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) + +#define I(x) (((x) & 31) << 27) +#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) +#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) +#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) +#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ + +/* These values are used to optimize assembly and disassembly. Each insn + is on a list of related insns (same first letter for assembly, same + insn code for disassembly). */ + + struct arc_opcode *next_asm; /* Next instr to try during assembly. */ + struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ + +/* Macros to create the hash values for the lists. */ +#define ARC_HASH_OPCODE(string) \ + ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) +#define ARC_HASH_ICODE(insn) \ + ((unsigned int) (insn) >> 27) + + /* Macros to access `next_asm', `next_dis' so users needn't care about the + underlying mechanism. */ +#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) +#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) +}; + +/* this is an "insert at front" linked list per Metaware spec + that new definitions override older ones. */ +extern struct arc_opcode *arc_ext_opcodes; + +struct arc_operand_value { + char *name; /* eg: "eq" */ + short value; /* eg: 1 */ + unsigned char type; /* index into `arc_operands' */ + unsigned char flags; /* various flag bits */ + +/* Values for `flags'. */ + +/* Return CPU number, given flag bits. */ +#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* Return MACH number, given flag bits. */ +#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) +}; + +struct arc_ext_operand_value { + struct arc_ext_operand_value *next; + struct arc_operand_value operand; +}; + +extern struct arc_ext_operand_value *arc_ext_operands; + +struct arc_operand { +/* One of the insn format chars. */ + unsigned char fmt; + +/* The number of bits in the operand (may be unused for a modifier). */ + unsigned char bits; + +/* How far the operand is left shifted in the instruction, or + the modifier's flag bit (may be unused for a modifier. */ + unsigned char shift; + +/* Various flag bits. */ + int flags; + +/* Values for `flags'. */ + +/* This operand is a suffix to the opcode. */ +#define ARC_OPERAND_SUFFIX 1 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_RELATIVE_BRANCH 2 + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ABSOLUTE_BRANCH 4 + +/* This operand is an address. The disassembler + prints these symbolically if possible. */ +#define ARC_OPERAND_ADDRESS 8 + +/* This operand is a long immediate value. */ +#define ARC_OPERAND_LIMM 0x10 + +/* This operand takes signed values. */ +#define ARC_OPERAND_SIGNED 0x20 + +/* This operand takes signed values, but also accepts a full positive + range of values. That is, if bits is 16, it takes any value from + -0x8000 to 0xffff. */ +#define ARC_OPERAND_SIGNOPT 0x40 + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define ARC_OPERAND_NEGATIVE 0x80 + +/* This operand doesn't really exist. The program uses these operands + in special ways. */ +#define ARC_OPERAND_FAKE 0x100 + +/* separate flags operand for j and jl instructions */ +#define ARC_OPERAND_JUMPFLAGS 0x200 + +/* allow warnings and errors to be issued after call to insert_xxxxxx */ +#define ARC_OPERAND_WARN 0x400 +#define ARC_OPERAND_ERROR 0x800 + +/* this is a load operand */ +#define ARC_OPERAND_LOAD 0x8000 + +/* this is a store operand */ +#define ARC_OPERAND_STORE 0x10000 + +/* Modifier values. */ +/* A dot is required before a suffix. Eg: .le */ +#define ARC_MOD_DOT 0x1000 + +/* A normal register is allowed (not used, but here for completeness). */ +#define ARC_MOD_REG 0x2000 + +/* An auxiliary register name is expected. */ +#define ARC_MOD_AUXREG 0x4000 + +/* Sum of all ARC_MOD_XXX bits. */ +#define ARC_MOD_BITS 0x7000 + +/* Non-zero if the operand type is really a modifier. */ +#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) + +/* enforce read/write only register restrictions */ +#define ARC_REGISTER_READONLY 0x01 +#define ARC_REGISTER_WRITEONLY 0x02 +#define ARC_REGISTER_NOSHORT_CUT 0x04 + +/* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (p & ((1 << o->bits) - 1)) << o->shift; + (I is the instruction which we are filling in, O is a pointer to + this structure, and OP is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged. + + REG is non-NULL when inserting a register value. */ + + arc_insn (*insert) + (arc_insn insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value *reg, long value, const char **errmsg); + +/* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & ARC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (I is the instruction, O is a pointer to this structure, and OP + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. + + INSN is a pointer to an array of two `arc_insn's. The first element is + the insn, the second is the limm if present. + + Operands that have a printable form like registers and suffixes have + their struct arc_operand_value pointer stored in OPVAL. */ + + long (*extract) + (arc_insn *insn, const struct arc_operand *operand, int mods, + const struct arc_operand_value **opval, int *invalid); +}; + +/* Bits that say what version of cpu we have. These should be passed to + arc_init_opcode_tables. At present, all there is is the cpu type. */ + +/* CPU number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) +/* MACH number, given value passed to `arc_init_opcode_tables'. */ +#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) + +/* Special register values: */ +#define ARC_REG_SHIMM_UPDATE 61 +#define ARC_REG_SHIMM 63 +#define ARC_REG_LIMM 62 + +/* Non-zero if REG is a constant marker. */ +#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) + +/* Positions and masks of various fields: */ +#define ARC_SHIFT_REGA 21 +#define ARC_SHIFT_REGB 15 +#define ARC_SHIFT_REGC 9 +#define ARC_MASK_REG 63 + +/* Delay slot types. */ +#define ARC_DELAY_NONE 0 /* no delay slot */ +#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ +#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ + +/* Non-zero if X will fit in a signed 9 bit field. */ +#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) + +extern const struct arc_operand arc_operands[]; +extern const int arc_operand_count; +extern struct arc_opcode arc_opcodes[]; +extern const int arc_opcodes_count; +extern const struct arc_operand_value arc_suffixes[]; +extern const int arc_suffixes_count; +extern const struct arc_operand_value arc_reg_names[]; +extern const int arc_reg_names_count; +extern unsigned char arc_operand_map[]; + +/* Utility fns in arc-opc.c. */ +int arc_get_opcode_mach (int, int); + +/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ +void arc_opcode_init_tables (int); +void arc_opcode_init_insert (void); +void arc_opcode_init_extract (void); +const struct arc_opcode *arc_opcode_lookup_asm (const char *); +const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); +int arc_opcode_limm_p (long *); +const struct arc_operand_value *arc_opcode_lookup_suffix + (const struct arc_operand *type, int value); +int arc_opcode_supported (const struct arc_opcode *); +int arc_opval_supported (const struct arc_operand_value *); +int arc_limm_fixup_adjust (arc_insn); +int arc_insn_is_j (arc_insn); +int arc_insn_not_jl (arc_insn); +int arc_operand_type (int); +struct arc_operand_value *get_ext_suffix (char *); +int arc_get_noshortcut_flag (void); diff --git a/external/gpl3/gdb/dist/include/opcode/arm.h b/external/gpl3/gdb/dist/include/opcode/arm.h new file mode 100644 index 000000000000..50bc726a60fc --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/arm.h @@ -0,0 +1,259 @@ +/* ARM assembler/disassembler support. + Copyright 2004, 2010 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, or (at + your option) any later version. + + GDB and GAS are distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING3. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The following bitmasks control CPU extensions: */ +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ +#define ARM_EXT_V4T 0x00000040 /* Thumb. */ +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ +#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ +#define ARM_EXT_V6 0x00001000 /* ARM V6. */ +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ +/* 0x00004000 Was ARM V6Z. */ +#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ +#define ARM_EXT_DIV 0x00010000 /* Integer division. */ +/* The 'M' in Arm V7M stands for Microcontroller. + On earlier architecture variants it stands for Multiply. */ +#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ +#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ +#define ARM_EXT_V7 0x00080000 /* Arm V7. */ +#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ +#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ +#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ +#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ +#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ +#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ +#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), + not in v7-M. */ +#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ +#define ARM_EXT_SEC 0x10000000 /* Security extensions. */ +#define ARM_EXT_OS 0x20000000 /* OS Extensions. */ +#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM + state. */ +#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ + +/* Co-processor space extensions. */ +#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ +#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ +#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ + +#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ +#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ +#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ +#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ +#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ +#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ +#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ +#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ +#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ +#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ +#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ +#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ +#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ +#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ +#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ + +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add + three more to cover cores prior to ARM6. Finally, there are cores which + implement further extensions in the co-processor space. */ +#define ARM_AEXT_V1 ARM_EXT_V1 +#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) +#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) +#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) +#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) +#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) +#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) +#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) +#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) +#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) +#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) +#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) +#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) +#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) +#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) +#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) +#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) +#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC) +#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ + | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ + | ARM_EXT_V6_DSP ) +#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) +#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) +#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) +#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) +#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) +#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) +#define ARM_AEXT_NOTM \ + (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ + | ARM_EXT_V6_DSP ) +#define ARM_AEXT_V6M_ONLY \ + ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) +#define ARM_AEXT_V6M \ + ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) +#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) +#define ARM_AEXT_V7M \ + ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ + & ~(ARM_AEXT_NOTM)) +#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) +#define ARM_AEXT_V7EM \ + (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) + +/* Processors with specific extensions in the co-processor space. */ +#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) +#define ARM_ARCH_IWMMXT \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) +#define ARM_ARCH_IWMMXT2 \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) + +#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) +#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) +#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) +#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) +#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) +#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) +#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) +#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) +#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) +#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ + | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ + | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) +#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) + +/* Deprecated */ +#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) + +#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) +#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) + +#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) +#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) +#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) +#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) +#define FPU_ARCH_VFP_V3D16_FP16 \ + ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) +#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) +#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) +#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) +#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) +#define FPU_ARCH_NEON_FP16 \ + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) +#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) +#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) +#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) +#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) +#define FPU_ARCH_NEON_VFP_V4 \ + ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) + +#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) + +#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) + +#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) +#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) +#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) +#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) +#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) +#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) +#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) +#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) +#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) +#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) +#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) +#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) +#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) +#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) +#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) +#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) +#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) +#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) +#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) +#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) +#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) +#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) +#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) +#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) +#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) +#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) +#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) +#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) +#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) +#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) +#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) + +/* Some useful combinations: */ +#define ARM_ARCH_NONE ARM_FEATURE (0, 0) +#define FPU_NONE ARM_FEATURE (0, 0) +#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ +#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) +#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) +/* v7-a+sec. */ +#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) +/* v7-a+mp+sec. */ +#define ARM_ARCH_V7A_MP_SEC \ + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ + 0) +/* v7-a+idiv+mp+sec+virt. */ +#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \ + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \ + | ARM_EXT_DIV | ARM_EXT_ADIV \ + | ARM_EXT_VIRT, 0) +/* Features that are present in v6M and v6S-M but not other v6 cores. */ +#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) + +/* There are too many feature bits to fit in a single word, so use a + structure. For simplicity we put all core features in one word and + everything else in the other. */ +typedef struct +{ + unsigned long core; + unsigned long coproc; +} arm_feature_set; + +#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ + (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) + +#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ + do { \ + (TARG).core = (F1).core | (F2).core; \ + (TARG).coproc = (F1).coproc | (F2).coproc; \ + } while (0) + +#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ + do { \ + (TARG).core = (F1).core &~ (F2).core; \ + (TARG).coproc = (F1).coproc &~ (F2).coproc; \ + } while (0) + +#define ARM_FEATURE(core, coproc) {(core), (coproc)} diff --git a/external/gpl3/gdb/dist/include/opcode/avr.h b/external/gpl3/gdb/dist/include/opcode/avr.h new file mode 100644 index 000000000000..c754234bd6a2 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/avr.h @@ -0,0 +1,294 @@ +/* Opcode table for the Atmel AVR micro controllers. + + Copyright 2000, 2001, 2004, 2006, 2008, 2010 Free Software Foundation, Inc. + Contributed by Denis Chertykov + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define AVR_ISA_1200 0x0001 /* In the beginning there was ... */ +#define AVR_ISA_LPM 0x0002 /* device has LPM */ +#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ +#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ +#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL + supported, no 8K wrap on RJMP and RCALL) */ +#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ +#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ +#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ +#define AVR_ISA_SPM 0x0200 /* device can program itself */ +#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ +#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ +#define AVR_ISA_MOVW 0x1000 /* device has MOVW */ +#define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ +#define AVR_ISA_DES 0x4000 /* device has DES */ + +#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) +#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) +/* For the attiny26 which is missing LPM Rd,Z+. */ +#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) +#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) +#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ + AVR_ISA_SPM | AVR_ISA_BRK) +#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) +#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK) +#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) +#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) +#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) +#define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) +#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) + +#define AVR_ISA_AVR1 AVR_ISA_TINY1 +#define AVR_ISA_AVR2 AVR_ISA_2xxx +#define AVR_ISA_AVR25 AVR_ISA_TINY2 +#define AVR_ISA_AVR3 AVR_ISA_M603 +#define AVR_ISA_AVR31 AVR_ISA_M103 +#define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK) +#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35) +#define AVR_ISA_AVR4 AVR_ISA_PWMx +#define AVR_ISA_AVR5 AVR_ISA_M323 +#define AVR_ISA_AVR51 AVR_ISA_M128 +#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \ + AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \ + AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ + AVR_ISA_SPM | AVR_ISA_BRK | AVR_ISA_EIND | \ + AVR_ISA_MOVW) + +#define REGISTER_P(x) ((x) == 'r' \ + || (x) == 'd' \ + || (x) == 'w' \ + || (x) == 'a' \ + || (x) == 'v') + +/* Undefined combination of operands - does the register + operand overlap with pre-decremented or post-incremented + pointer register (like ld r31,Z+)? */ +#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ + ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ + ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ + ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) + +/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ +#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ + ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) + +/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as + `ld r,b' or `st b,r' respectively - next opcode entry)? */ +#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) + +/* constraint letters + r - any register + d - `ldi' register (r16-r31) + v - `movw' even register (r0, r2, ..., r28, r30) + a - `fmul' register (r16-r23) + w - `adiw' register (r24,r26,r28,r30) + e - pointer registers (X,Y,Z) + b - base pointer register and displacement ([YZ]+disp) + z - Z pointer register (for [e]lpm Rd,Z[+]) + M - immediate value from 0 to 255 + n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible + s - immediate value from 0 to 7 + P - Port address value from 0 to 63. (in, out) + p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) + K - immediate value from 0 to 63 (used in `adiw', `sbiw') + i - immediate value + l - signed pc relative offset from -64 to 63 + L - signed pc relative offset from -2048 to 2047 + h - absolute code address (call, jmp) + S - immediate value from 0 to 7 (S = s << 4) + E - immediate value from 0 to 15, shifted left by 4 (des) + ? - use this opcode entry if no parameters, else use next opcode entry + + Order is important - some binary opcodes have more than one name, + the disassembler will only see the first match. + + Remaining undefined opcodes (1699 total - some of them might work + as normal instructions if not all of the bits are decoded): + + 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) + "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] + "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 + "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7] + "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 + "1001010x001x1001" (4) 0x9[45][23]9 + "1001010x01xx1001" (8) 0x9[45][4-7]9 + "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 + "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b + "10010101001x1000" (2) 0x95[23]8 + "1001010101xx1000" (4) 0x95[4-7]8 + "1001010110111000" (1) 0x95b8 + "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) + "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] + */ + +AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) +AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) +AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) +AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) +AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) +AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) +AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) + +AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) +AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) +AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) +AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) +AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) +AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) +AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) +AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) + + /* Same as {cl,se}[chinstvz] above. */ +AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) + +AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) +AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) + +AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) +AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) +AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) +AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) + +AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) +AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) +AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) +AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) +AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) +AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) +AVR_INSN (spm, "?", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) +AVR_INSN (spm, "z", "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8) + +AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) +AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) +AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) +AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) +AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) +AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) +AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) +AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) +AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) + + /* Shorthand for {eor,add,adc,and} r,r above. */ +AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) + +AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + /*XXX special case*/ +AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + +AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) +AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) + +AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) +AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) + +AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) +AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) +AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) + +AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) +AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) +AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) +AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) + +AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) +AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) + +AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) +AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) + +AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) +AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) +AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) +AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) + +AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) +AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) +AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) +AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) +AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) +AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) +AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) +AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) +AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) +AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) +AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) +AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) +AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) +AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) + + /* Same as br?? above. */ +AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) + +AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) +AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) + +AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) +AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) + +AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) +AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) +AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) +AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) +AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) +AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) +AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) +AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) +AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) +AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) + + /* Known to be decoded as `nop' by the old core. */ +AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) +AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) +AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) +AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) +AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) +AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) + +AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) +AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) + + /* Special case for b+0, `e' must be next entry after `b', + b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ +AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) +AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) +AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) +AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) + + /* These are for devices that don't exist yet + (>128K program memory, PC = EIND:Z). */ +AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) +AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) + +/* DES instruction for encryption and decryption */ +AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) + diff --git a/external/gpl3/gdb/dist/include/opcode/bfin.h b/external/gpl3/gdb/dist/include/opcode/bfin.h new file mode 100755 index 000000000000..730f63c24c52 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/bfin.h @@ -0,0 +1,1755 @@ +/* bfin.h -- Header file for ADI Blackfin opcode table + Copyright 2005, 2010, 2011 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef OPCODE_BFIN_H +#define OPCODE_BFIN_H + +/* Common to all DSP32 instructions. */ +#define BIT_MULTI_INS 0x0800 + +/* This just sets the multi instruction bit of a DSP32 instruction. */ +#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS; + + +/* DSP instructions (32 bit) */ + +/* mmod field. */ +#define M_S2RND 1 +#define M_T 2 +#define M_W32 3 +#define M_FU 4 +#define M_TFU 6 +#define M_IS 8 +#define M_ISS2 9 +#define M_IH 11 +#define M_IU 12 + +static inline int is_macmod_pmove(int x) +{ + return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND) + || (x == M_ISS2) || (x == M_IU); +} + +static inline int is_macmod_hmove(int x) +{ + return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T) + || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH); +} + +/* dsp32mac ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| +|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst; + int mask_dst; + int bits_h10; + int mask_h10; + int bits_h00; + int mask_h00; + int bits_op0; + int mask_op0; + int bits_w0; + int mask_w0; + int bits_h11; + int mask_h11; + int bits_h01; + int mask_h01; + int bits_op1; + int mask_op1; + int bits_w1; + int mask_w1; + int bits_P; + int mask_P; + int bits_MM; + int mask_MM; + int bits_mmod; + int mask_mmod; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Mac; + +#define DSP32Mac_opcode 0xc0000000 +#define DSP32Mac_src1_bits 0 +#define DSP32Mac_src1_mask 0x7 +#define DSP32Mac_src0_bits 3 +#define DSP32Mac_src0_mask 0x7 +#define DSP32Mac_dst_bits 6 +#define DSP32Mac_dst_mask 0x7 +#define DSP32Mac_h10_bits 9 +#define DSP32Mac_h10_mask 0x1 +#define DSP32Mac_h00_bits 10 +#define DSP32Mac_h00_mask 0x1 +#define DSP32Mac_op0_bits 11 +#define DSP32Mac_op0_mask 0x3 +#define DSP32Mac_w0_bits 13 +#define DSP32Mac_w0_mask 0x1 +#define DSP32Mac_h11_bits 14 +#define DSP32Mac_h11_mask 0x1 +#define DSP32Mac_h01_bits 15 +#define DSP32Mac_h01_mask 0x1 +#define DSP32Mac_op1_bits 16 +#define DSP32Mac_op1_mask 0x3 +#define DSP32Mac_w1_bits 18 +#define DSP32Mac_w1_mask 0x1 +#define DSP32Mac_p_bits 19 +#define DSP32Mac_p_mask 0x1 +#define DSP32Mac_MM_bits 20 +#define DSP32Mac_MM_mask 0x1 +#define DSP32Mac_mmod_bits 21 +#define DSP32Mac_mmod_mask 0xf +#define DSP32Mac_code2_bits 25 +#define DSP32Mac_code2_mask 0x3 +#define DSP32Mac_M_bits 27 +#define DSP32Mac_M_mask 0x1 +#define DSP32Mac_code_bits 28 +#define DSP32Mac_code_mask 0xf + +#define init_DSP32Mac \ +{ \ + DSP32Mac_opcode, \ + DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ + DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ + DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ + DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ + DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ + DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ + DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ + DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ + DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ + DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ + DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ + DSP32Mac_p_bits, DSP32Mac_p_mask, \ + DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ + DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ + DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ + DSP32Mac_M_bits, DSP32Mac_M_mask, \ + DSP32Mac_code_bits, DSP32Mac_code_mask \ +}; + +/* dsp32mult ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| +|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......| ++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+ +*/ + +typedef DSP32Mac DSP32Mult; +#define DSP32Mult_opcode 0xc2000000 + +#define init_DSP32Mult \ +{ \ + DSP32Mult_opcode, \ + DSP32Mac_src1_bits, DSP32Mac_src1_mask, \ + DSP32Mac_src0_bits, DSP32Mac_src0_mask, \ + DSP32Mac_dst_bits, DSP32Mac_dst_mask, \ + DSP32Mac_h10_bits, DSP32Mac_h10_mask, \ + DSP32Mac_h00_bits, DSP32Mac_h00_mask, \ + DSP32Mac_op0_bits, DSP32Mac_op0_mask, \ + DSP32Mac_w0_bits, DSP32Mac_w0_mask, \ + DSP32Mac_h11_bits, DSP32Mac_h11_mask, \ + DSP32Mac_h01_bits, DSP32Mac_h01_mask, \ + DSP32Mac_op1_bits, DSP32Mac_op1_mask, \ + DSP32Mac_w1_bits, DSP32Mac_w1_mask, \ + DSP32Mac_p_bits, DSP32Mac_p_mask, \ + DSP32Mac_MM_bits, DSP32Mac_MM_mask, \ + DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \ + DSP32Mac_code2_bits, DSP32Mac_code2_mask, \ + DSP32Mac_M_bits, DSP32Mac_M_mask, \ + DSP32Mac_code_bits, DSP32Mac_code_mask \ +}; + +/* dsp32alu ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| +|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst1; + int mask_dst1; + int bits_dst0; + int mask_dst0; + int bits_x; + int mask_x; + int bits_s; + int mask_s; + int bits_aop; + int mask_aop; + int bits_aopcde; + int mask_aopcde; + int bits_HL; + int mask_HL; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Alu; + +#define DSP32Alu_opcode 0xc4000000 +#define DSP32Alu_src1_bits 0 +#define DSP32Alu_src1_mask 0x7 +#define DSP32Alu_src0_bits 3 +#define DSP32Alu_src0_mask 0x7 +#define DSP32Alu_dst1_bits 6 +#define DSP32Alu_dst1_mask 0x7 +#define DSP32Alu_dst0_bits 9 +#define DSP32Alu_dst0_mask 0x7 +#define DSP32Alu_x_bits 12 +#define DSP32Alu_x_mask 0x1 +#define DSP32Alu_s_bits 13 +#define DSP32Alu_s_mask 0x1 +#define DSP32Alu_aop_bits 14 +#define DSP32Alu_aop_mask 0x3 +#define DSP32Alu_aopcde_bits 16 +#define DSP32Alu_aopcde_mask 0x1f +#define DSP32Alu_HL_bits 21 +#define DSP32Alu_HL_mask 0x1 +#define DSP32Alu_dontcare_bits 22 +#define DSP32Alu_dontcare_mask 0x7 +#define DSP32Alu_code2_bits 25 +#define DSP32Alu_code2_mask 0x3 +#define DSP32Alu_M_bits 27 +#define DSP32Alu_M_mask 0x1 +#define DSP32Alu_code_bits 28 +#define DSP32Alu_code_mask 0xf + +#define init_DSP32Alu \ +{ \ + DSP32Alu_opcode, \ + DSP32Alu_src1_bits, DSP32Alu_src1_mask, \ + DSP32Alu_src0_bits, DSP32Alu_src0_mask, \ + DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \ + DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \ + DSP32Alu_x_bits, DSP32Alu_x_mask, \ + DSP32Alu_s_bits, DSP32Alu_s_mask, \ + DSP32Alu_aop_bits, DSP32Alu_aop_mask, \ + DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \ + DSP32Alu_HL_bits, DSP32Alu_HL_mask, \ + DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \ + DSP32Alu_code2_bits, DSP32Alu_code2_mask, \ + DSP32Alu_M_bits, DSP32Alu_M_mask, \ + DSP32Alu_code_bits, DSP32Alu_code_mask \ +}; + +/* dsp32shift ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| +|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_src0; + int mask_src0; + int bits_dst1; + int mask_dst1; + int bits_dst0; + int mask_dst0; + int bits_HLs; + int mask_HLs; + int bits_sop; + int mask_sop; + int bits_sopcde; + int mask_sopcde; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32Shift; + +#define DSP32Shift_opcode 0xc6000000 +#define DSP32Shift_src1_bits 0 +#define DSP32Shift_src1_mask 0x7 +#define DSP32Shift_src0_bits 3 +#define DSP32Shift_src0_mask 0x7 +#define DSP32Shift_dst1_bits 6 +#define DSP32Shift_dst1_mask 0x7 +#define DSP32Shift_dst0_bits 9 +#define DSP32Shift_dst0_mask 0x7 +#define DSP32Shift_HLs_bits 12 +#define DSP32Shift_HLs_mask 0x3 +#define DSP32Shift_sop_bits 14 +#define DSP32Shift_sop_mask 0x3 +#define DSP32Shift_sopcde_bits 16 +#define DSP32Shift_sopcde_mask 0x1f +#define DSP32Shift_dontcare_bits 21 +#define DSP32Shift_dontcare_mask 0x3 +#define DSP32Shift_code2_bits 23 +#define DSP32Shift_code2_mask 0xf +#define DSP32Shift_M_bits 27 +#define DSP32Shift_M_mask 0x1 +#define DSP32Shift_code_bits 28 +#define DSP32Shift_code_mask 0xf + +#define init_DSP32Shift \ +{ \ + DSP32Shift_opcode, \ + DSP32Shift_src1_bits, DSP32Shift_src1_mask, \ + DSP32Shift_src0_bits, DSP32Shift_src0_mask, \ + DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \ + DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \ + DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \ + DSP32Shift_sop_bits, DSP32Shift_sop_mask, \ + DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \ + DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \ + DSP32Shift_code2_bits, DSP32Shift_code2_mask, \ + DSP32Shift_M_bits, DSP32Shift_M_mask, \ + DSP32Shift_code_bits, DSP32Shift_code_mask \ +}; + +/* dsp32shiftimm ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| +|.sop...|.HLs...|.dst0......|.immag.................|.src1......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_src1; + int mask_src1; + int bits_immag; + int mask_immag; + int bits_dst0; + int mask_dst0; + int bits_HLs; + int mask_HLs; + int bits_sop; + int mask_sop; + int bits_sopcde; + int mask_sopcde; + int bits_dontcare; + int mask_dontcare; + int bits_code2; + int mask_code2; + int bits_M; + int mask_M; + int bits_code; + int mask_code; +} DSP32ShiftImm; + +#define DSP32ShiftImm_opcode 0xc6800000 +#define DSP32ShiftImm_src1_bits 0 +#define DSP32ShiftImm_src1_mask 0x7 +#define DSP32ShiftImm_immag_bits 3 +#define DSP32ShiftImm_immag_mask 0x3f +#define DSP32ShiftImm_dst0_bits 9 +#define DSP32ShiftImm_dst0_mask 0x7 +#define DSP32ShiftImm_HLs_bits 12 +#define DSP32ShiftImm_HLs_mask 0x3 +#define DSP32ShiftImm_sop_bits 14 +#define DSP32ShiftImm_sop_mask 0x3 +#define DSP32ShiftImm_sopcde_bits 16 +#define DSP32ShiftImm_sopcde_mask 0x1f +#define DSP32ShiftImm_dontcare_bits 21 +#define DSP32ShiftImm_dontcare_mask 0x3 +#define DSP32ShiftImm_code2_bits 23 +#define DSP32ShiftImm_code2_mask 0xf +#define DSP32ShiftImm_M_bits 27 +#define DSP32ShiftImm_M_mask 0x1 +#define DSP32ShiftImm_code_bits 28 +#define DSP32ShiftImm_code_mask 0xf + +#define init_DSP32ShiftImm \ +{ \ + DSP32ShiftImm_opcode, \ + DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \ + DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \ + DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \ + DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \ + DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \ + DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \ + DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \ + DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \ + DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \ + DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \ +}; + +/* LOAD / STORE */ + +/* LDSTidxI ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| +|.offset........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_offset; + int mask_offset; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_sz; + int mask_sz; + int bits_Z; + int mask_Z; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTidxI; + +#define LDSTidxI_opcode 0xe4000000 +#define LDSTidxI_offset_bits 0 +#define LDSTidxI_offset_mask 0xffff +#define LDSTidxI_reg_bits 16 +#define LDSTidxI_reg_mask 0x7 +#define LDSTidxI_ptr_bits 19 +#define LDSTidxI_ptr_mask 0x7 +#define LDSTidxI_sz_bits 22 +#define LDSTidxI_sz_mask 0x3 +#define LDSTidxI_Z_bits 24 +#define LDSTidxI_Z_mask 0x1 +#define LDSTidxI_W_bits 25 +#define LDSTidxI_W_mask 0x1 +#define LDSTidxI_code_bits 26 +#define LDSTidxI_code_mask 0x3f + +#define init_LDSTidxI \ +{ \ + LDSTidxI_opcode, \ + LDSTidxI_offset_bits, LDSTidxI_offset_mask, \ + LDSTidxI_reg_bits, LDSTidxI_reg_mask, \ + LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \ + LDSTidxI_sz_bits, LDSTidxI_sz_mask, \ + LDSTidxI_Z_bits, LDSTidxI_Z_mask, \ + LDSTidxI_W_bits, LDSTidxI_W_mask, \ + LDSTidxI_code_bits, LDSTidxI_code_mask \ +}; + + +/* LDST ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_Z; + int mask_Z; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_sz; + int mask_sz; + int bits_code; + int mask_code; +} LDST; + +#define LDST_opcode 0x9000 +#define LDST_reg_bits 0 +#define LDST_reg_mask 0x7 +#define LDST_ptr_bits 3 +#define LDST_ptr_mask 0x7 +#define LDST_Z_bits 6 +#define LDST_Z_mask 0x1 +#define LDST_aop_bits 7 +#define LDST_aop_mask 0x3 +#define LDST_W_bits 9 +#define LDST_W_mask 0x1 +#define LDST_sz_bits 10 +#define LDST_sz_mask 0x3 +#define LDST_code_bits 12 +#define LDST_code_mask 0xf + +#define init_LDST \ +{ \ + LDST_opcode, \ + LDST_reg_bits, LDST_reg_mask, \ + LDST_ptr_bits, LDST_ptr_mask, \ + LDST_Z_bits, LDST_Z_mask, \ + LDST_aop_bits, LDST_aop_mask, \ + LDST_W_bits, LDST_W_mask, \ + LDST_sz_bits, LDST_sz_mask, \ + LDST_code_bits, LDST_code_mask \ +}; + +/* LDSTii ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_ptr; + int mask_ptr; + int bits_offset; + int mask_offset; + int bits_op; + int mask_op; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTii; + +#define LDSTii_opcode 0xa000 +#define LDSTii_reg_bit 0 +#define LDSTii_reg_mask 0x7 +#define LDSTii_ptr_bit 3 +#define LDSTii_ptr_mask 0x7 +#define LDSTii_offset_bit 6 +#define LDSTii_offset_mask 0xf +#define LDSTii_op_bit 10 +#define LDSTii_op_mask 0x3 +#define LDSTii_W_bit 12 +#define LDSTii_W_mask 0x1 +#define LDSTii_code_bit 13 +#define LDSTii_code_mask 0x7 + +#define init_LDSTii \ +{ \ + LDSTii_opcode, \ + LDSTii_reg_bit, LDSTii_reg_mask, \ + LDSTii_ptr_bit, LDSTii_ptr_mask, \ + LDSTii_offset_bit, LDSTii_offset_mask, \ + LDSTii_op_bit, LDSTii_op_mask, \ + LDSTii_W_bit, LDSTii_W_mask, \ + LDSTii_code_bit, LDSTii_code_mask \ +}; + + +/* LDSTiiFP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_offset; + int mask_offset; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTiiFP; + +#define LDSTiiFP_opcode 0xb800 +#define LDSTiiFP_reg_bits 0 +#define LDSTiiFP_reg_mask 0xf +#define LDSTiiFP_offset_bits 4 +#define LDSTiiFP_offset_mask 0x1f +#define LDSTiiFP_W_bits 9 +#define LDSTiiFP_W_mask 0x1 +#define LDSTiiFP_code_bits 10 +#define LDSTiiFP_code_mask 0x3f + +#define init_LDSTiiFP \ +{ \ + LDSTiiFP_opcode, \ + LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \ + LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \ + LDSTiiFP_W_bits, LDSTiiFP_W_mask, \ + LDSTiiFP_code_bits, LDSTiiFP_code_mask \ +}; + +/* dspLDST ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_i; + int mask_i; + int bits_m; + int mask_m; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} DspLDST; + +#define DspLDST_opcode 0x9c00 +#define DspLDST_reg_bits 0 +#define DspLDST_reg_mask 0x7 +#define DspLDST_i_bits 3 +#define DspLDST_i_mask 0x3 +#define DspLDST_m_bits 5 +#define DspLDST_m_mask 0x3 +#define DspLDST_aop_bits 7 +#define DspLDST_aop_mask 0x3 +#define DspLDST_W_bits 9 +#define DspLDST_W_mask 0x1 +#define DspLDST_code_bits 10 +#define DspLDST_code_mask 0x3f + +#define init_DspLDST \ +{ \ + DspLDST_opcode, \ + DspLDST_reg_bits, DspLDST_reg_mask, \ + DspLDST_i_bits, DspLDST_i_mask, \ + DspLDST_m_bits, DspLDST_m_mask, \ + DspLDST_aop_bits, DspLDST_aop_mask, \ + DspLDST_W_bits, DspLDST_W_mask, \ + DspLDST_code_bits, DspLDST_code_mask \ +}; + + +/* LDSTpmod ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_ptr; + int mask_ptr; + int bits_idx; + int mask_idx; + int bits_reg; + int mask_reg; + int bits_aop; + int mask_aop; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} LDSTpmod; + +#define LDSTpmod_opcode 0x8000 +#define LDSTpmod_ptr_bits 0 +#define LDSTpmod_ptr_mask 0x7 +#define LDSTpmod_idx_bits 3 +#define LDSTpmod_idx_mask 0x7 +#define LDSTpmod_reg_bits 6 +#define LDSTpmod_reg_mask 0x7 +#define LDSTpmod_aop_bits 9 +#define LDSTpmod_aop_mask 0x3 +#define LDSTpmod_W_bits 11 +#define LDSTpmod_W_mask 0x1 +#define LDSTpmod_code_bits 12 +#define LDSTpmod_code_mask 0xf + +#define init_LDSTpmod \ +{ \ + LDSTpmod_opcode, \ + LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \ + LDSTpmod_idx_bits, LDSTpmod_idx_mask, \ + LDSTpmod_reg_bits, LDSTpmod_reg_mask, \ + LDSTpmod_aop_bits, LDSTpmod_aop_mask, \ + LDSTpmod_W_bits, LDSTpmod_W_mask, \ + LDSTpmod_code_bits, LDSTpmod_code_mask \ +}; + + +/* LOGI2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} LOGI2op; + +#define LOGI2op_opcode 0x4800 +#define LOGI2op_dst_bits 0 +#define LOGI2op_dst_mask 0x7 +#define LOGI2op_src_bits 3 +#define LOGI2op_src_mask 0x1f +#define LOGI2op_opc_bits 8 +#define LOGI2op_opc_mask 0x7 +#define LOGI2op_code_bits 11 +#define LOGI2op_code_mask 0x1f + +#define init_LOGI2op \ +{ \ + LOGI2op_opcode, \ + LOGI2op_dst_bits, LOGI2op_dst_mask, \ + LOGI2op_src_bits, LOGI2op_src_mask, \ + LOGI2op_opc_bits, LOGI2op_opc_mask, \ + LOGI2op_code_bits, LOGI2op_code_mask \ +}; + + +/* ALU2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} ALU2op; + +#define ALU2op_opcode 0x4000 +#define ALU2op_dst_bits 0 +#define ALU2op_dst_mask 0x7 +#define ALU2op_src_bits 3 +#define ALU2op_src_mask 0x7 +#define ALU2op_opc_bits 6 +#define ALU2op_opc_mask 0xf +#define ALU2op_code_bits 10 +#define ALU2op_code_mask 0x3f + +#define init_ALU2op \ +{ \ + ALU2op_opcode, \ + ALU2op_dst_bits, ALU2op_dst_mask, \ + ALU2op_src_bits, ALU2op_src_mask, \ + ALU2op_opc_bits, ALU2op_opc_mask, \ + ALU2op_code_bits, ALU2op_code_mask \ +}; + + +/* BRCC ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_offset; + int mask_offset; + int bits_B; + int mask_B; + int bits_T; + int mask_T; + int bits_code; + int mask_code; +} BRCC; + +#define BRCC_opcode 0x1000 +#define BRCC_offset_bits 0 +#define BRCC_offset_mask 0x3ff +#define BRCC_B_bits 10 +#define BRCC_B_mask 0x1 +#define BRCC_T_bits 11 +#define BRCC_T_mask 0x1 +#define BRCC_code_bits 12 +#define BRCC_code_mask 0xf + +#define init_BRCC \ +{ \ + BRCC_opcode, \ + BRCC_offset_bits, BRCC_offset_mask, \ + BRCC_B_bits, BRCC_B_mask, \ + BRCC_T_bits, BRCC_T_mask, \ + BRCC_code_bits, BRCC_code_mask \ +}; + + +/* UJUMP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 1 | 0 |.offset........................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_offset; + int mask_offset; + int bits_code; + int mask_code; +} UJump; + +#define UJump_opcode 0x2000 +#define UJump_offset_bits 0 +#define UJump_offset_mask 0xfff +#define UJump_code_bits 12 +#define UJump_code_mask 0xf + +#define init_UJump \ +{ \ + UJump_opcode, \ + UJump_offset_bits, UJump_offset_mask, \ + UJump_code_bits, UJump_code_mask \ +}; + + +/* ProgCtrl ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_poprnd; + int mask_poprnd; + int bits_prgfunc; + int mask_prgfunc; + int bits_code; + int mask_code; +} ProgCtrl; + +#define ProgCtrl_opcode 0x0000 +#define ProgCtrl_poprnd_bits 0 +#define ProgCtrl_poprnd_mask 0xf +#define ProgCtrl_prgfunc_bits 4 +#define ProgCtrl_prgfunc_mask 0xf +#define ProgCtrl_code_bits 8 +#define ProgCtrl_code_mask 0xff + +#define init_ProgCtrl \ +{ \ + ProgCtrl_opcode, \ + ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \ + ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \ + ProgCtrl_code_bits, ProgCtrl_code_mask \ +}; + +/* CALLa ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| +|.lsw...........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + + +typedef struct +{ + unsigned long opcode; + int bits_addr; + int mask_addr; + int bits_S; + int mask_S; + int bits_code; + int mask_code; +} CALLa; + +#define CALLa_opcode 0xe2000000 +#define CALLa_addr_bits 0 +#define CALLa_addr_mask 0xffffff +#define CALLa_S_bits 24 +#define CALLa_S_mask 0x1 +#define CALLa_code_bits 25 +#define CALLa_code_mask 0x7f + +#define init_CALLa \ +{ \ + CALLa_opcode, \ + CALLa_addr_bits, CALLa_addr_mask, \ + CALLa_S_bits, CALLa_S_mask, \ + CALLa_code_bits, CALLa_code_mask \ +}; + + +/* pseudoDEBUG ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_fn; + int mask_fn; + int bits_code; + int mask_code; +} PseudoDbg; + +#define PseudoDbg_opcode 0xf800 +#define PseudoDbg_reg_bits 0 +#define PseudoDbg_reg_mask 0x7 +#define PseudoDbg_grp_bits 3 +#define PseudoDbg_grp_mask 0x7 +#define PseudoDbg_fn_bits 6 +#define PseudoDbg_fn_mask 0x3 +#define PseudoDbg_code_bits 8 +#define PseudoDbg_code_mask 0xff + +#define init_PseudoDbg \ +{ \ + PseudoDbg_opcode, \ + PseudoDbg_reg_bits, PseudoDbg_reg_mask, \ + PseudoDbg_grp_bits, PseudoDbg_grp_mask, \ + PseudoDbg_fn_bits, PseudoDbg_fn_mask, \ + PseudoDbg_code_bits, PseudoDbg_code_mask \ +}; + +/* PseudoDbg_assert ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| +|.expected......................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_expected; + int mask_expected; + int bits_regtest; + int mask_regtest; + int bits_grp; + int mask_grp; + int bits_dbgop; + int mask_dbgop; + int bits_dontcare; + int mask_dontcare; + int bits_code; + int mask_code; +} PseudoDbg_Assert; + +#define PseudoDbg_Assert_opcode 0xf0000000 +#define PseudoDbg_Assert_expected_bits 0 +#define PseudoDbg_Assert_expected_mask 0xffff +#define PseudoDbg_Assert_regtest_bits 16 +#define PseudoDbg_Assert_regtest_mask 0x7 +#define PseudoDbg_Assert_grp_bits 19 +#define PseudoDbg_Assert_grp_mask 0x7 +#define PseudoDbg_Assert_dbgop_bits 22 +#define PseudoDbg_Assert_dbgop_mask 0x3 +#define PseudoDbg_Assert_dontcare_bits 24 +#define PseudoDbg_Assert_dontcare_mask 0x7 +#define PseudoDbg_Assert_code_bits 27 +#define PseudoDbg_Assert_code_mask 0x1f + +#define init_PseudoDbg_Assert \ +{ \ + PseudoDbg_Assert_opcode, \ + PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \ + PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \ + PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \ + PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \ + PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \ + PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \ +}; + +/* pseudoChr ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_ch; + int mask_ch; + int bits_code; + int mask_code; +} PseudoChr; + +#define PseudoChr_opcode 0xf900 +#define PseudoChr_ch_bits 0 +#define PseudoChr_ch_mask 0xff +#define PseudoChr_code_bits 8 +#define PseudoChr_code_mask 0xff + +#define init_PseudoChr \ +{ \ + PseudoChr_opcode, \ + PseudoChr_ch_bits, PseudoChr_ch_mask, \ + PseudoChr_code_bits, PseudoChr_code_mask \ +}; + +/* CaCTRL ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_op; + int mask_op; + int bits_a; + int mask_a; + int bits_code; + int mask_code; +} CaCTRL; + +#define CaCTRL_opcode 0x0240 +#define CaCTRL_reg_bits 0 +#define CaCTRL_reg_mask 0x7 +#define CaCTRL_op_bits 3 +#define CaCTRL_op_mask 0x3 +#define CaCTRL_a_bits 5 +#define CaCTRL_a_mask 0x1 +#define CaCTRL_code_bits 6 +#define CaCTRL_code_mask 0x3fff + +#define init_CaCTRL \ +{ \ + CaCTRL_opcode, \ + CaCTRL_reg_bits, CaCTRL_reg_mask, \ + CaCTRL_op_bits, CaCTRL_op_mask, \ + CaCTRL_a_bits, CaCTRL_a_mask, \ + CaCTRL_code_bits, CaCTRL_code_mask \ +}; + +/* PushPopMultiple ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_pr; + int mask_pr; + int bits_dr; + int mask_dr; + int bits_W; + int mask_W; + int bits_p; + int mask_p; + int bits_d; + int mask_d; + int bits_code; + int mask_code; +} PushPopMultiple; + +#define PushPopMultiple_opcode 0x0400 +#define PushPopMultiple_pr_bits 0 +#define PushPopMultiple_pr_mask 0x7 +#define PushPopMultiple_dr_bits 3 +#define PushPopMultiple_dr_mask 0x7 +#define PushPopMultiple_W_bits 6 +#define PushPopMultiple_W_mask 0x1 +#define PushPopMultiple_p_bits 7 +#define PushPopMultiple_p_mask 0x1 +#define PushPopMultiple_d_bits 8 +#define PushPopMultiple_d_mask 0x1 +#define PushPopMultiple_code_bits 8 +#define PushPopMultiple_code_mask 0x1 + +#define init_PushPopMultiple \ +{ \ + PushPopMultiple_opcode, \ + PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \ + PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \ + PushPopMultiple_W_bits, PushPopMultiple_W_mask, \ + PushPopMultiple_p_bits, PushPopMultiple_p_mask, \ + PushPopMultiple_d_bits, PushPopMultiple_d_mask, \ + PushPopMultiple_code_bits, PushPopMultiple_code_mask \ +}; + +/* PushPopReg ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_W; + int mask_W; + int bits_code; + int mask_code; +} PushPopReg; + +#define PushPopReg_opcode 0x0100 +#define PushPopReg_reg_bits 0 +#define PushPopReg_reg_mask 0x7 +#define PushPopReg_grp_bits 3 +#define PushPopReg_grp_mask 0x7 +#define PushPopReg_W_bits 6 +#define PushPopReg_W_mask 0x1 +#define PushPopReg_code_bits 7 +#define PushPopReg_code_mask 0x1ff + +#define init_PushPopReg \ +{ \ + PushPopReg_opcode, \ + PushPopReg_reg_bits, PushPopReg_reg_mask, \ + PushPopReg_grp_bits, PushPopReg_grp_mask, \ + PushPopReg_W_bits, PushPopReg_W_mask, \ + PushPopReg_code_bits, PushPopReg_code_mask, \ +}; + +/* linkage ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| +|.framesize.....................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_framesize; + int mask_framesize; + int bits_R; + int mask_R; + int bits_code; + int mask_code; +} Linkage; + +#define Linkage_opcode 0xe8000000 +#define Linkage_framesize_bits 0 +#define Linkage_framesize_mask 0xffff +#define Linkage_R_bits 16 +#define Linkage_R_mask 0x1 +#define Linkage_code_bits 17 +#define Linkage_code_mask 0x7fff + +#define init_Linkage \ +{ \ + Linkage_opcode, \ + Linkage_framesize_bits, Linkage_framesize_mask, \ + Linkage_R_bits, Linkage_R_mask, \ + Linkage_code_bits, Linkage_code_mask \ +}; + +/* LoopSetup ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| +|.reg...........| - | - |.eoffset...............................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_eoffset; + int mask_eoffset; + int bits_dontcare; + int mask_dontcare; + int bits_reg; + int mask_reg; + int bits_soffset; + int mask_soffset; + int bits_c; + int mask_c; + int bits_rop; + int mask_rop; + int bits_code; + int mask_code; +} LoopSetup; + +#define LoopSetup_opcode 0xe0800000 +#define LoopSetup_eoffset_bits 0 +#define LoopSetup_eoffset_mask 0x3ff +#define LoopSetup_dontcare_bits 10 +#define LoopSetup_dontcare_mask 0x3 +#define LoopSetup_reg_bits 12 +#define LoopSetup_reg_mask 0xf +#define LoopSetup_soffset_bits 16 +#define LoopSetup_soffset_mask 0xf +#define LoopSetup_c_bits 20 +#define LoopSetup_c_mask 0x1 +#define LoopSetup_rop_bits 21 +#define LoopSetup_rop_mask 0x3 +#define LoopSetup_code_bits 23 +#define LoopSetup_code_mask 0x1ff + +#define init_LoopSetup \ +{ \ + LoopSetup_opcode, \ + LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \ + LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \ + LoopSetup_reg_bits, LoopSetup_reg_mask, \ + LoopSetup_soffset_bits, LoopSetup_soffset_mask, \ + LoopSetup_c_bits, LoopSetup_c_mask, \ + LoopSetup_rop_bits, LoopSetup_rop_mask, \ + LoopSetup_code_bits, LoopSetup_code_mask \ +}; + +/* LDIMMhalf ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| +|.hword.........................................................| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned long opcode; + int bits_hword; + int mask_hword; + int bits_reg; + int mask_reg; + int bits_grp; + int mask_grp; + int bits_S; + int mask_S; + int bits_H; + int mask_H; + int bits_Z; + int mask_Z; + int bits_code; + int mask_code; +} LDIMMhalf; + +#define LDIMMhalf_opcode 0xe1000000 +#define LDIMMhalf_hword_bits 0 +#define LDIMMhalf_hword_mask 0xffff +#define LDIMMhalf_reg_bits 16 +#define LDIMMhalf_reg_mask 0x7 +#define LDIMMhalf_grp_bits 19 +#define LDIMMhalf_grp_mask 0x3 +#define LDIMMhalf_S_bits 21 +#define LDIMMhalf_S_mask 0x1 +#define LDIMMhalf_H_bits 22 +#define LDIMMhalf_H_mask 0x1 +#define LDIMMhalf_Z_bits 23 +#define LDIMMhalf_Z_mask 0x1 +#define LDIMMhalf_code_bits 24 +#define LDIMMhalf_code_mask 0xff + +#define init_LDIMMhalf \ +{ \ + LDIMMhalf_opcode, \ + LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \ + LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \ + LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \ + LDIMMhalf_S_bits, LDIMMhalf_S_mask, \ + LDIMMhalf_H_bits, LDIMMhalf_H_mask, \ + LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \ + LDIMMhalf_code_bits, LDIMMhalf_code_mask \ +}; + + +/* CC2dreg ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_reg; + int mask_reg; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} CC2dreg; + +#define CC2dreg_opcode 0x0200 +#define CC2dreg_reg_bits 0 +#define CC2dreg_reg_mask 0x7 +#define CC2dreg_op_bits 3 +#define CC2dreg_op_mask 0x3 +#define CC2dreg_code_bits 5 +#define CC2dreg_code_mask 0x7fff + +#define init_CC2dreg \ +{ \ + CC2dreg_opcode, \ + CC2dreg_reg_bits, CC2dreg_reg_mask, \ + CC2dreg_op_bits, CC2dreg_op_mask, \ + CC2dreg_code_bits, CC2dreg_code_mask \ +}; + + +/* PTR2op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} PTR2op; + +#define PTR2op_opcode 0x4400 +#define PTR2op_dst_bits 0 +#define PTR2op_dst_mask 0x7 +#define PTR2op_src_bits 3 +#define PTR2op_src_mask 0x7 +#define PTR2op_opc_bits 6 +#define PTR2op_opc_mask 0x7 +#define PTR2op_code_bits 9 +#define PTR2op_code_mask 0x7f + +#define init_PTR2op \ +{ \ + PTR2op_opcode, \ + PTR2op_dst_bits, PTR2op_dst_mask, \ + PTR2op_src_bits, PTR2op_src_mask, \ + PTR2op_opc_bits, PTR2op_opc_mask, \ + PTR2op_code_bits, PTR2op_code_mask \ +}; + + +/* COMP3op ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src0; + int mask_src0; + int bits_src1; + int mask_src1; + int bits_dst; + int mask_dst; + int bits_opc; + int mask_opc; + int bits_code; + int mask_code; +} COMP3op; + +#define COMP3op_opcode 0x5000 +#define COMP3op_src0_bits 0 +#define COMP3op_src0_mask 0x7 +#define COMP3op_src1_bits 3 +#define COMP3op_src1_mask 0x7 +#define COMP3op_dst_bits 6 +#define COMP3op_dst_mask 0x7 +#define COMP3op_opc_bits 9 +#define COMP3op_opc_mask 0x7 +#define COMP3op_code_bits 12 +#define COMP3op_code_mask 0xf + +#define init_COMP3op \ +{ \ + COMP3op_opcode, \ + COMP3op_src0_bits, COMP3op_src0_mask, \ + COMP3op_src1_bits, COMP3op_src1_mask, \ + COMP3op_dst_bits, COMP3op_dst_mask, \ + COMP3op_opc_bits, COMP3op_opc_mask, \ + COMP3op_code_bits, COMP3op_code_mask \ +}; + +/* ccMV ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src; + int mask_src; + int bits_dst; + int mask_dst; + int bits_s; + int mask_s; + int bits_d; + int mask_d; + int bits_T; + int mask_T; + int bits_code; + int mask_code; +} CCmv; + +#define CCmv_opcode 0x0600 +#define CCmv_src_bits 0 +#define CCmv_src_mask 0x7 +#define CCmv_dst_bits 3 +#define CCmv_dst_mask 0x7 +#define CCmv_s_bits 6 +#define CCmv_s_mask 0x1 +#define CCmv_d_bits 7 +#define CCmv_d_mask 0x1 +#define CCmv_T_bits 8 +#define CCmv_T_mask 0x1 +#define CCmv_code_bits 9 +#define CCmv_code_mask 0x7f + +#define init_CCmv \ +{ \ + CCmv_opcode, \ + CCmv_src_bits, CCmv_src_mask, \ + CCmv_dst_bits, CCmv_dst_mask, \ + CCmv_s_bits, CCmv_s_mask, \ + CCmv_d_bits, CCmv_d_mask, \ + CCmv_T_bits, CCmv_T_mask, \ + CCmv_code_bits, CCmv_code_mask \ +}; + + +/* CCflag ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_x; + int mask_x; + int bits_y; + int mask_y; + int bits_G; + int mask_G; + int bits_opc; + int mask_opc; + int bits_I; + int mask_I; + int bits_code; + int mask_code; +} CCflag; + +#define CCflag_opcode 0x0800 +#define CCflag_x_bits 0 +#define CCflag_x_mask 0x7 +#define CCflag_y_bits 3 +#define CCflag_y_mask 0x7 +#define CCflag_G_bits 6 +#define CCflag_G_mask 0x1 +#define CCflag_opc_bits 7 +#define CCflag_opc_mask 0x7 +#define CCflag_I_bits 10 +#define CCflag_I_mask 0x1 +#define CCflag_code_bits 11 +#define CCflag_code_mask 0x1f + +#define init_CCflag \ +{ \ + CCflag_opcode, \ + CCflag_x_bits, CCflag_x_mask, \ + CCflag_y_bits, CCflag_y_mask, \ + CCflag_G_bits, CCflag_G_mask, \ + CCflag_opc_bits, CCflag_opc_mask, \ + CCflag_I_bits, CCflag_I_mask, \ + CCflag_code_bits, CCflag_code_mask, \ +}; + + +/* CC2stat ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_cbit; + int mask_cbit; + int bits_op; + int mask_op; + int bits_D; + int mask_D; + int bits_code; + int mask_code; +} CC2stat; + +#define CC2stat_opcode 0x0300 +#define CC2stat_cbit_bits 0 +#define CC2stat_cbit_mask 0x1f +#define CC2stat_op_bits 5 +#define CC2stat_op_mask 0x3 +#define CC2stat_D_bits 7 +#define CC2stat_D_mask 0x1 +#define CC2stat_code_bits 8 +#define CC2stat_code_mask 0xff + +#define init_CC2stat \ +{ \ + CC2stat_opcode, \ + CC2stat_cbit_bits, CC2stat_cbit_mask, \ + CC2stat_op_bits, CC2stat_op_mask, \ + CC2stat_D_bits, CC2stat_D_mask, \ + CC2stat_code_bits, CC2stat_code_mask \ +}; + + +/* REGMV ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_src; + int mask_src; + int bits_dst; + int mask_dst; + int bits_gs; + int mask_gs; + int bits_gd; + int mask_gd; + int bits_code; + int mask_code; +} RegMv; + +#define RegMv_opcode 0x3000 +#define RegMv_src_bits 0 +#define RegMv_src_mask 0x7 +#define RegMv_dst_bits 3 +#define RegMv_dst_mask 0x7 +#define RegMv_gs_bits 6 +#define RegMv_gs_mask 0x7 +#define RegMv_gd_bits 9 +#define RegMv_gd_mask 0x7 +#define RegMv_code_bits 12 +#define RegMv_code_mask 0xf + +#define init_RegMv \ +{ \ + RegMv_opcode, \ + RegMv_src_bits, RegMv_src_mask, \ + RegMv_dst_bits, RegMv_dst_mask, \ + RegMv_gs_bits, RegMv_gs_mask, \ + RegMv_gd_bits, RegMv_gd_mask, \ + RegMv_code_bits, RegMv_code_mask \ +}; + + +/* COMPI2opD ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_dst; + int mask_dst; + int bits_src; + int mask_src; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} COMPI2opD; + +#define COMPI2opD_opcode 0x6000 +#define COMPI2opD_dst_bits 0 +#define COMPI2opD_dst_mask 0x7 +#define COMPI2opD_src_bits 3 +#define COMPI2opD_src_mask 0x7f +#define COMPI2opD_op_bits 10 +#define COMPI2opD_op_mask 0x1 +#define COMPI2opD_code_bits 11 +#define COMPI2opD_code_mask 0x1f + +#define init_COMPI2opD \ +{ \ + COMPI2opD_opcode, \ + COMPI2opD_dst_bits, COMPI2opD_dst_mask, \ + COMPI2opD_src_bits, COMPI2opD_src_mask, \ + COMPI2opD_op_bits, COMPI2opD_op_mask, \ + COMPI2opD_code_bits, COMPI2opD_code_mask \ +}; + +/* COMPI2opP ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef COMPI2opD COMPI2opP; + +#define COMPI2opP_opcode 0x6800 +#define COMPI2opP_dst_bits 0 +#define COMPI2opP_dst_mask 0x7 +#define COMPI2opP_src_bits 3 +#define COMPI2opP_src_mask 0x7f +#define COMPI2opP_op_bits 10 +#define COMPI2opP_op_mask 0x1 +#define COMPI2opP_code_bits 11 +#define COMPI2opP_code_mask 0x1f + +#define init_COMPI2opP \ +{ \ + COMPI2opP_opcode, \ + COMPI2opP_dst_bits, COMPI2opP_dst_mask, \ + COMPI2opP_src_bits, COMPI2opP_src_mask, \ + COMPI2opP_op_bits, COMPI2opP_op_mask, \ + COMPI2opP_code_bits, COMPI2opP_code_mask \ +}; + + +/* dagMODim ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_i; + int mask_i; + int bits_m; + int mask_m; + int bits_op; + int mask_op; + int bits_code2; + int mask_code2; + int bits_br; + int mask_br; + int bits_code; + int mask_code; +} DagMODim; + +#define DagMODim_opcode 0x9e60 +#define DagMODim_i_bits 0 +#define DagMODim_i_mask 0x3 +#define DagMODim_m_bits 2 +#define DagMODim_m_mask 0x3 +#define DagMODim_op_bits 4 +#define DagMODim_op_mask 0x1 +#define DagMODim_code2_bits 5 +#define DagMODim_code2_mask 0x3 +#define DagMODim_br_bits 7 +#define DagMODim_br_mask 0x1 +#define DagMODim_code_bits 8 +#define DagMODim_code_mask 0xff + +#define init_DagMODim \ +{ \ + DagMODim_opcode, \ + DagMODim_i_bits, DagMODim_i_mask, \ + DagMODim_m_bits, DagMODim_m_mask, \ + DagMODim_op_bits, DagMODim_op_mask, \ + DagMODim_code2_bits, DagMODim_code2_mask, \ + DagMODim_br_bits, DagMODim_br_mask, \ + DagMODim_code_bits, DagMODim_code_mask \ +}; + +/* dagMODik ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| ++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ +*/ + +typedef struct +{ + unsigned short opcode; + int bits_i; + int mask_i; + int bits_op; + int mask_op; + int bits_code; + int mask_code; +} DagMODik; + +#define DagMODik_opcode 0x9f60 +#define DagMODik_i_bits 0 +#define DagMODik_i_mask 0x3 +#define DagMODik_op_bits 2 +#define DagMODik_op_mask 0x3 +#define DagMODik_code_bits 3 +#define DagMODik_code_mask 0xfff + +#define init_DagMODik \ +{ \ + DagMODik_opcode, \ + DagMODik_i_bits, DagMODik_i_mask, \ + DagMODik_op_bits, DagMODik_op_mask, \ + DagMODik_code_bits, DagMODik_code_mask \ +}; + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/cgen.h b/external/gpl3/gdb/dist/include/opcode/cgen.h new file mode 100644 index 000000000000..b7e82d4dd93a --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/cgen.h @@ -0,0 +1,1480 @@ +/* Header file for targets using CGEN: Cpu tools GENerator. + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of GDB, the GNU debugger, and the GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef OPCODE_CGEN_H +#define OPCODE_CGEN_H + +#include "symcat.h" +#include "cgen/bitset.h" + +/* ??? IWBN to replace bfd in the name. */ +#include "bfd_stdint.h" + +/* ??? This file requires bfd.h but only to get bfd_vma. + Seems like an awful lot to require just to get such a fundamental type. + Perhaps the definition of bfd_vma can be moved outside of bfd.h. + Or perhaps one could duplicate its definition in another file. + Until such time, this file conditionally compiles definitions that require + bfd_vma using __BFD_H_SEEN__. */ + +/* Enums must be defined before they can be used. + Allow them to be used in struct definitions, even though the enum must + be defined elsewhere. + If CGEN_ARCH isn't defined, this file is being included by something other + than -desc.h. */ + +/* Prepend the arch name, defined in -desc.h, and _cgen_ to symbol S. + The lack of spaces in the arg list is important for non-stdc systems. + This file is included by -desc.h. + It can be included independently of -desc.h, in which case the arch + dependent portions will be declared as "unknown_cgen_foo". */ + +#ifndef CGEN_SYM +#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) +#endif + +/* This file contains the static (unchanging) pieces and as much other stuff + as we can reasonably put here. It's generally cleaner to put stuff here + rather than having it machine generated if possible. */ + +/* The assembler syntax is made up of expressions (duh...). + At the lowest level the values are mnemonics, register names, numbers, etc. + Above that are subexpressions, if any (an example might be the + "effective address" in m68k cpus). Subexpressions are wip. + At the second highest level are the insns themselves. Above that are + pseudo-insns, synthetic insns, and macros, if any. */ + +/* Lots of cpu's have a fixed insn size, or one which rarely changes, + and it's generally easier to handle these by treating the insn as an + integer type, rather than an array of characters. So we allow targets + to control this. When an integer type the value is in host byte order, + when an array of characters the value is in target byte order. */ + +typedef unsigned int CGEN_INSN_INT; +typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */ +typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */ + +#if CGEN_INT_INSN_P +typedef CGEN_INSN_INT CGEN_INSN_BYTES; +typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; +#else +typedef unsigned char *CGEN_INSN_BYTES; +typedef unsigned char *CGEN_INSN_BYTES_PTR; +#endif + +#ifdef __GNUC__ +#define CGEN_INLINE __inline__ +#else +#define CGEN_INLINE +#endif + +enum cgen_endian +{ + CGEN_ENDIAN_UNKNOWN, + CGEN_ENDIAN_LITTLE, + CGEN_ENDIAN_BIG +}; + +/* Forward decl. */ + +typedef struct cgen_insn CGEN_INSN; + +/* Opaque pointer version for use by external world. */ + +typedef struct cgen_cpu_desc *CGEN_CPU_DESC; + +/* Attributes. + Attributes are used to describe various random things associated with + an object (ifield, hardware, operand, insn, whatever) and are specified + as name/value pairs. + Integer attributes computed at compile time are currently all that's + supported, though adding string attributes and run-time computation is + straightforward. Integer attribute values are always host int's + (signed or unsigned). For portability, this means 32 bits. + Integer attributes are further categorized as boolean, bitset, integer, + and enum types. Boolean attributes appear frequently enough that they're + recorded in one host int. This limits the maximum number of boolean + attributes to 32, though that's a *lot* of attributes. */ + +/* Type of attribute values. */ + +typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; +typedef int CGEN_ATTR_VALUE_ENUM_TYPE; +typedef union +{ + CGEN_ATTR_VALUE_BITSET_TYPE bitset; + CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; +} CGEN_ATTR_VALUE_TYPE; + +/* Struct to record attribute information. */ + +typedef struct +{ + /* Boolean attributes. */ + unsigned int bool_; + /* Non-boolean integer attributes. */ + CGEN_ATTR_VALUE_TYPE nonbool[1]; +} CGEN_ATTR; + +/* Define a structure member for attributes with N non-boolean entries. + There is no maximum number of non-boolean attributes. + There is a maximum of 32 boolean attributes (since they are all recorded + in one host int). */ + +#define CGEN_ATTR_TYPE(n) \ +struct { unsigned int bool_; \ + CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } + +/* Return the boolean attributes. */ + +#define CGEN_ATTR_BOOLS(a) ((a)->bool_) + +/* Non-boolean attribute numbers are offset by this much. */ + +#define CGEN_ATTR_NBOOL_OFFSET 32 + +/* Given a boolean attribute number, return its mask. */ + +#define CGEN_ATTR_MASK(attr) (1 << (attr)) + +/* Return the value of boolean attribute ATTR in ATTRS. */ + +#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) + +/* Return value of attribute ATTR in ATTR_TABLE for OBJ. + OBJ is a pointer to the entity that has the attributes + (??? not used at present but is reserved for future purposes - eventually + the goal is to allow recording attributes in source form and computing + them lazily at runtime, not sure of the details yet). */ + +#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ +((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ + ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ + : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) +#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ + ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) + +/* Attribute name/value tables. + These are used to assist parsing of descriptions at run-time. */ + +typedef struct +{ + const char * name; + unsigned value; +} CGEN_ATTR_ENTRY; + +/* For each domain (ifld,hw,operand,insn), list of attributes. */ + +typedef struct +{ + const char * name; + const CGEN_ATTR_ENTRY * dfault; + const CGEN_ATTR_ENTRY * vals; +} CGEN_ATTR_TABLE; + +/* Instruction set variants. */ + +typedef struct { + const char *name; + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; +} CGEN_ISA; + +/* Machine variants. */ + +typedef struct { + const char *name; + /* The argument to bfd_arch_info->scan. */ + const char *bfd_name; + /* one of enum mach_attr */ + int num; + /* parameter from mach->cpu */ + unsigned int insn_chunk_bitsize; +} CGEN_MACH; + +/* Parse result (also extraction result). + + The result of parsing an insn is stored here. + To generate the actual insn, this is passed to the insert handler. + When printing an insn, the result of extraction is stored here. + To print the insn, this is passed to the print handler. + + It is machine generated so we don't define it here, + but we do need a forward decl for the handler fns. + + There is one member for each possible field in the insn. + The type depends on the field. + Also recorded here is the computed length of the insn for architectures + where it varies. +*/ + +typedef struct cgen_fields CGEN_FIELDS; + +/* Total length of the insn, as recorded in the `fields' struct. */ +/* ??? The field insert handler has lots of opportunities for optimization + if it ever gets inlined. On architectures where insns all have the same + size, may wish to detect that and make this macro a constant - to allow + further optimizations. */ + +#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) + +/* Extraction support for variable length insn sets. */ + +/* When disassembling we don't know the number of bytes to read at the start. + So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest + are read when needed. This struct controls this. It is basically the + disassemble_info stuff, except that we provide a cache for values already + read (since bytes can typically be read several times to fetch multiple + operands that may be in them), and that extraction of fields is needed + in contexts other than disassembly. */ + +typedef struct { + /* A pointer to the disassemble_info struct. + We don't require dis-asm.h so we use void * for the type here. + If NULL, BYTES is full of valid data (VALID == -1). */ + void *dis_info; + /* Points to a working buffer of sufficient size. */ + unsigned char *insn_bytes; + /* Mask of bytes that are valid in INSN_BYTES. */ + unsigned int valid; +} CGEN_EXTRACT_INFO; + +/* Associated with each insn or expression is a set of "handlers" for + performing operations like parsing, printing, etc. These require a bfd_vma + value to be passed around but we don't want all applications to need bfd.h. + So this stuff is only provided if bfd.h has been included. */ + +/* Parse handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + STRP is a pointer to a pointer to the text being parsed. + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + If the expression is successfully parsed, *STRP is updated. + If not it is left alone. + The result is NULL if success or an error message. */ +typedef const char * (cgen_parse_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + const char **strp_, CGEN_FIELDS *fields_); + +/* Insert handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + FIELDS is a pointer to a cgen_fields struct from which the values + are fetched. + INSNP is a pointer to a buffer in which to place the insn. + PC is the pc value of the insn. + The result is an error message or NULL if success. */ + +#ifdef __BFD_H_SEEN__ +typedef const char * (cgen_insert_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, + bfd_vma pc_); +#else +typedef const char * (cgen_insert_fn) (); +#endif + +/* Extract handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + The second argument is a pointer to a struct controlling extraction + (only used for variable length insns). + EX_INFO is a pointer to a struct for controlling reading of further + bytes for the insn. + BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + PC is the pc value of the insn. + The result is the length of the insn in bits or zero if not recognized. */ + +#ifdef __BFD_H_SEEN__ +typedef int (cgen_extract_fn) + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, + CGEN_FIELDS *fields_, bfd_vma pc_); +#else +typedef int (cgen_extract_fn) (); +#endif + +/* Print handler. + CD is a cpu table descriptor. + INFO is a pointer to the disassembly info. + Eg: disassemble_info. It's defined as `PTR' so this file can be included + without dis-asm.h. + INSN is a pointer to a struct describing the insn being printed. + FIELDS is a pointer to a cgen_fields struct. + PC is the pc value of the insn. + LEN is the length of the insn, in bits. */ + +#ifdef __BFD_H_SEEN__ +typedef void (cgen_print_fn) + (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, bfd_vma pc_, int len_); +#else +typedef void (cgen_print_fn) (); +#endif + +/* Parse/insert/extract/print handlers. + + Indices into the handler tables. + We could use pointers here instead, but 90% of them are generally identical + and that's a lot of redundant data. Making these unsigned char indices + into tables of pointers saves a bit of space. + Using indices also keeps assembler code out of the disassembler and + vice versa. */ + +struct cgen_opcode_handler +{ + unsigned char parse, insert, extract, print; +}; + +/* Assembler interface. + + The interface to the assembler is intended to be clean in the sense that + libopcodes.a is a standalone entity and could be used with any assembler. + Not that one would necessarily want to do that but rather that it helps + keep a clean interface. The interface will obviously be slanted towards + GAS, but at least it's a start. + ??? Note that one possible user of the assembler besides GAS is GDB. + + Parsing is controlled by the assembler which calls + CGEN_SYM (assemble_insn). If it can parse and build the entire insn + it doesn't call back to the assembler. If it needs/wants to call back + to the assembler, cgen_parse_operand_fn is called which can either + + - return a number to be inserted in the insn + - return a "register" value to be inserted + (the register might not be a register per pe) + - queue the argument and return a marker saying the expression has been + queued (eg: a fix-up) + - return an error message indicating the expression wasn't recognizable + + The result is an error message or NULL for success. + The parsed value is stored in the bfd_vma *. */ + +/* Values for indicating what the caller wants. */ + +enum cgen_parse_operand_type +{ + CGEN_PARSE_OPERAND_INIT, + CGEN_PARSE_OPERAND_INTEGER, + CGEN_PARSE_OPERAND_ADDRESS, + CGEN_PARSE_OPERAND_SYMBOLIC +}; + +/* Values for indicating what was parsed. */ + +enum cgen_parse_operand_result +{ + CGEN_PARSE_OPERAND_RESULT_NUMBER, + CGEN_PARSE_OPERAND_RESULT_REGISTER, + CGEN_PARSE_OPERAND_RESULT_QUEUED, + CGEN_PARSE_OPERAND_RESULT_ERROR +}; + +#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ +typedef const char * (cgen_parse_operand_fn) + (CGEN_CPU_DESC, + enum cgen_parse_operand_type, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); +#else +typedef const char * (cgen_parse_operand_fn) (); +#endif + +/* Set the cgen_parse_operand_fn callback. */ + +extern void cgen_set_parse_operand_fn + (CGEN_CPU_DESC, cgen_parse_operand_fn); + +/* Called before trying to match a table entry with the insn. */ + +extern void cgen_init_parse_operand (CGEN_CPU_DESC); + +/* Operand values (keywords, integers, symbols, etc.) */ + +/* Types of assembler elements. */ + +enum cgen_asm_type +{ + CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX +}; + +#ifndef CGEN_ARCH +enum cgen_hw_type { CGEN_HW_MAX }; +#endif + +/* List of hardware elements. */ + +typedef struct +{ + char *name; + enum cgen_hw_type type; + /* There is currently no example where both index specs and value specs + are required, so for now both are clumped under "asm_data". */ + enum cgen_asm_type asm_type; + void *asm_data; +#ifndef CGEN_HW_NBOOL_ATTRS +#define CGEN_HW_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; +#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) +} CGEN_HW_ENTRY; + +/* Return value of attribute ATTR in HW. */ + +#define CGEN_HW_ATTR_VALUE(hw, attr) \ +CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) + +/* Table of hardware elements for selected mach, computed at runtime. + enum cgen_hw_type is an index into this table (specifically `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_HW_ENTRY *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_HW_ENTRY **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_HW_TABLE; + +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name + (CGEN_CPU_DESC, const char *); +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num + (CGEN_CPU_DESC, unsigned int); + +/* This struct is used to describe things like register names, etc. */ + +typedef struct cgen_keyword_entry +{ + /* Name (as in register name). */ + char * name; + + /* Value (as in register number). + The value cannot be -1 as that is used to indicate "not found". + IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ + int value; + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ + /* ??? Moving this last should be done by treating keywords like insn lists + and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ + /* FIXME: Not used yet. */ +#ifndef CGEN_KEYWORD_NBOOL_ATTRS +#define CGEN_KEYWORD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; + + /* ??? Putting these here means compiled in entries can't be const. + Not a really big deal, but something to consider. */ + /* Next name hash table entry. */ + struct cgen_keyword_entry *next_name; + /* Next value hash table entry. */ + struct cgen_keyword_entry *next_value; +} CGEN_KEYWORD_ENTRY; + +/* Top level struct for describing a set of related keywords + (e.g. register names). + + This struct supports run-time entry of new values, and hashed lookups. */ + +typedef struct cgen_keyword +{ + /* Pointer to initial [compiled in] values. */ + CGEN_KEYWORD_ENTRY *init_entries; + + /* Number of entries in `init_entries'. */ + unsigned int num_init_entries; + + /* Hash table used for name lookup. */ + CGEN_KEYWORD_ENTRY **name_hash_table; + + /* Hash table used for value lookup. */ + CGEN_KEYWORD_ENTRY **value_hash_table; + + /* Number of entries in the hash_tables. */ + unsigned int hash_table_size; + + /* Pointer to null keyword "" entry if present. */ + const CGEN_KEYWORD_ENTRY *null_entry; + + /* String containing non-alphanumeric characters used + in keywords. + At present, the highest number of entries used is 1. */ + char nonalpha_chars[8]; +} CGEN_KEYWORD; + +/* Structure used for searching. */ + +typedef struct +{ + /* Table being searched. */ + const CGEN_KEYWORD *table; + + /* Specification of what is being searched for. */ + const char *spec; + + /* Current index in hash table. */ + unsigned int current_hash; + + /* Current element in current hash chain. */ + CGEN_KEYWORD_ENTRY *current_entry; +} CGEN_KEYWORD_SEARCH; + +/* Lookup a keyword from its name. */ + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name + (CGEN_KEYWORD *, const char *); + +/* Lookup a keyword from its value. */ + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value + (CGEN_KEYWORD *, int); + +/* Add a keyword. */ + +void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); + +/* Keyword searching. + This can be used to retrieve every keyword, or a subset. */ + +CGEN_KEYWORD_SEARCH cgen_keyword_search_init + (CGEN_KEYWORD *, const char *); +const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next + (CGEN_KEYWORD_SEARCH *); + +/* Operand value support routines. */ + +extern const char *cgen_parse_keyword + (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); +#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ +extern const char *cgen_parse_signed_integer + (CGEN_CPU_DESC, const char **, int, long *); +extern const char *cgen_parse_unsigned_integer + (CGEN_CPU_DESC, const char **, int, unsigned long *); +extern const char *cgen_parse_address + (CGEN_CPU_DESC, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *); +extern const char *cgen_validate_signed_integer + (long, long, long); +extern const char *cgen_validate_unsigned_integer + (unsigned long, unsigned long, unsigned long); +#endif + +/* Operand modes. */ + +/* ??? This duplicates the values in arch.h. Revisit. + These however need the CGEN_ prefix [as does everything in this file]. */ +/* ??? Targets may need to add their own modes so we may wish to move this + to -opc.h, or add a hook. */ + +enum cgen_mode { + CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ + CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, + CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, + CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, + CGEN_MODE_TARGET_MAX, + CGEN_MODE_INT, CGEN_MODE_UINT, + CGEN_MODE_MAX +}; + +/* FIXME: Until simulator is updated. */ + +#define CGEN_MODE_VM CGEN_MODE_VOID + +/* Operands. */ + +#ifndef CGEN_ARCH +enum cgen_operand_type { CGEN_OPERAND_MAX }; +#endif + +/* "nil" indicator for the operand instance table */ +#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX + +/* A tree of these structs represents the multi-ifield + structure of an operand's hw-index value, if it exists. */ + +struct cgen_ifld; + +typedef struct cgen_maybe_multi_ifield +{ + int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); + n: indexed by array of more cgen_maybe_multi_ifields. */ + union + { + const void *p; + const struct cgen_maybe_multi_ifield * multi; + const struct cgen_ifld * leaf; + } val; +} +CGEN_MAYBE_MULTI_IFLD; + +/* This struct defines each entry in the operand table. */ + +typedef struct +{ + /* Name as it appears in the syntax string. */ + char *name; + + /* Operand type. */ + enum cgen_operand_type type; + + /* The hardware element associated with this operand. */ + enum cgen_hw_type hw_type; + + /* FIXME: We don't yet record ifield definitions, which we should. + When we do it might make sense to delete start/length (since they will + be duplicated in the ifield's definition) and replace them with a + pointer to the ifield entry. */ + + /* Bit position. + This is just a hint, and may be unused in more complex operands. + May be unused for a modifier. */ + unsigned char start; + + /* The number of bits in the operand. + This is just a hint, and may be unused in more complex operands. + May be unused for a modifier. */ + unsigned char length; + + /* The (possibly-multi) ifield used as an index for this operand, if it + is indexed by a field at all. This substitutes / extends the start and + length fields above, but unsure at this time whether they are used + anywhere. */ + CGEN_MAYBE_MULTI_IFLD index_fields; +#if 0 /* ??? Interesting idea but relocs tend to get too complicated, + and ABI dependent, for simple table lookups to work. */ + /* Ideally this would be the internal (external?) reloc type. */ + int reloc_type; +#endif + + /* Attributes. + This should, but technically needn't, appear last. It is a variable sized + array in that one architecture may have 1 nonbool attribute and another + may have more. Having this last means the non-architecture specific code + needn't care, now or tomorrow. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ +#ifndef CGEN_OPERAND_NBOOL_ATTRS +#define CGEN_OPERAND_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; +#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) +} CGEN_OPERAND; + +/* Return value of attribute ATTR in OPERAND. */ + +#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ +CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) + +/* Table of operands for selected mach/isa, computed at runtime. + enum cgen_operand_type is an index into this table (specifically + `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_OPERAND *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_OPERAND **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_OPERAND_TABLE; + +extern const CGEN_OPERAND * cgen_operand_lookup_by_name + (CGEN_CPU_DESC, const char *); +extern const CGEN_OPERAND * cgen_operand_lookup_by_num + (CGEN_CPU_DESC, int); + +/* Instruction operand instances. + + For each instruction, a list of the hardware elements that are read and + written are recorded. */ + +/* The type of the instance. */ + +enum cgen_opinst_type { + /* End of table marker. */ + CGEN_OPINST_END = 0, + CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT +}; + +typedef struct +{ + /* Input or output indicator. */ + enum cgen_opinst_type type; + + /* Name of operand. */ + const char *name; + + /* The hardware element referenced. */ + enum cgen_hw_type hw_type; + + /* The mode in which the operand is being used. */ + enum cgen_mode mode; + + /* The operand table entry CGEN_OPERAND_NIL if there is none + (i.e. an explicit hardware reference). */ + enum cgen_operand_type op_type; + + /* If `operand' is "nil", the index (e.g. into array of registers). */ + int index; + + /* Attributes. + ??? This perhaps should be a real attribute struct but there's + no current need, so we save a bit of space and just have a set of + flags. The interface is such that this can easily be made attributes + should it prove useful. */ + unsigned int attrs; +#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) +/* Return value of attribute ATTR in OPINST. */ +#define CGEN_OPINST_ATTR(opinst, attr) \ +((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) +/* Operand is conditionally referenced (read/written). */ +#define CGEN_OPINST_COND_REF 1 +} CGEN_OPINST; + +/* Syntax string. + + Each insn format and subexpression has one of these. + + The syntax "string" consists of characters (n > 0 && n < 128), and operand + values (n >= 128), and is terminated by 0. Operand values are 128 + index + into the operand table. The operand table doesn't exist in C, per se, as + the data is recorded in the parse/insert/extract/print switch statements. */ + +/* This should be at least as large as necessary for any target. */ +#define CGEN_MAX_SYNTAX_ELEMENTS 48 + +/* A target may know its own precise maximum. Assert that it falls below + the above limit. */ +#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS +#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS +#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" +#endif +#endif + +typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; + +typedef struct +{ + CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; +} CGEN_SYNTAX; + +#define CGEN_SYNTAX_STRING(syn) (syn->syntax) +#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) +#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) +#define CGEN_SYNTAX_FIELD(c) ((c) - 128) +#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) + +/* ??? I can't currently think of any case where the mnemonic doesn't come + first [and if one ever doesn't building the hash tables will be tricky]. + However, we treat mnemonics as just another operand of the instruction. + A value of 1 means "this is where the mnemonic appears". 1 isn't + special other than it's a non-printable ASCII char. */ + +#define CGEN_SYNTAX_MNEMONIC 1 +#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) + +/* Instruction fields. + + ??? We currently don't allow adding fields at run-time. + Easy to fix when needed. */ + +typedef struct cgen_ifld { + /* Enum of ifield. */ + int num; +#define CGEN_IFLD_NUM(f) ((f)->num) + + /* Name of the field, distinguishes it from all other fields. */ + const char *name; +#define CGEN_IFLD_NAME(f) ((f)->name) + + /* Default offset, in bits, from the start of the insn to the word + containing the field. */ + int word_offset; +#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) + + /* Default length of the word containing the field. */ + int word_size; +#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) + + /* Default starting bit number. + Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ + int start; +#define CGEN_IFLD_START(f) ((f)->start) + + /* Length of the field, in bits. */ + int length; +#define CGEN_IFLD_LENGTH(f) ((f)->length) + +#ifndef CGEN_IFLD_NBOOL_ATTRS +#define CGEN_IFLD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; +#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) +} CGEN_IFLD; + +/* Return value of attribute ATTR in IFLD. */ +#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ +CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) + +/* Instruction data. */ + +/* Instruction formats. + + Instructions are grouped by format. Associated with an instruction is its + format. Each insn's opcode table entry contains a format table entry. + ??? There is usually very few formats compared with the number of insns, + so one can reduce the size of the opcode table by recording the format table + as a separate entity. Given that we currently don't, format table entries + are also distinguished by their operands. This increases the size of the + table, but reduces the number of tables. It's all minutiae anyway so it + doesn't really matter [at this point in time]. + + ??? Support for variable length ISA's is wip. */ + +/* Accompanying each iformat description is a list of its fields. */ + +typedef struct { + const CGEN_IFLD *ifld; +#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) +} CGEN_IFMT_IFLD; + +/* This should be at least as large as necessary for any target. */ +#define CGEN_MAX_IFMT_OPERANDS 16 + +/* A target may know its own precise maximum. Assert that it falls below + the above limit. */ +#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS +#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS +#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" +#endif +#endif + + +typedef struct +{ + /* Length that MASK and VALUE have been calculated to + [VALUE is recorded elsewhere]. + Normally it is base_insn_bitsize. On [V]LIW architectures where the base + insn size may be larger than the size of an insn, this field is less than + base_insn_bitsize. */ + unsigned char mask_length; +#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) + + /* Total length of instruction, in bits. */ + unsigned char length; +#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) + + /* Mask to apply to the first MASK_LENGTH bits. + Each insn's value is stored with the insn. + The first step in recognizing an insn for disassembly is + (opcode & mask) == value. */ + CGEN_INSN_INT mask; +#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) + + /* Instruction fields. + +1 for trailing NULL. */ + CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; +#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) +} CGEN_IFMT; + +/* Instruction values. */ + +typedef struct +{ + /* The opcode portion of the base insn. */ + CGEN_INSN_INT base_value; + +#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS + /* Extra opcode values beyond base_value. */ + unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; +#endif +} CGEN_IVALUE; + +/* Instruction opcode table. + This contains the syntax and format data of an instruction. */ + +/* ??? Some ports already have an opcode table yet still need to use the rest + of what cgen_insn has. Plus keeping the opcode data with the operand + instance data can create a pretty big file. So we keep them separately. + Not sure this is a good idea in the long run. */ + +typedef struct +{ + /* Indices into parse/insert/extract/print handler tables. */ + struct cgen_opcode_handler handlers; +#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) + + /* Syntax string. */ + CGEN_SYNTAX syntax; +#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) + + /* Format entry. */ + const CGEN_IFMT *format; +#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) +#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) + + /* Instruction opcode value. */ + CGEN_IVALUE value; +#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) +#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) +#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) +} CGEN_OPCODE; + +/* Instruction attributes. + This is made a published type as applications can cache a pointer to + the attributes for speed. */ + +#ifndef CGEN_INSN_NBOOL_ATTRS +#define CGEN_INSN_NBOOL_ATTRS 1 +#endif +typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; + +/* Enum of architecture independent attributes. */ + +#ifndef CGEN_ARCH +/* ??? Numbers here are recorded in two places. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS = 0 +} CGEN_INSN_ATTR; +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) +#endif + +/* This struct defines each entry in the instruction table. */ + +typedef struct +{ + /* Each real instruction is enumerated. */ + /* ??? This may go away in time. */ + int num; +#define CGEN_INSN_NUM(insn) ((insn)->base->num) + + /* Name of entry (that distinguishes it from all other entries). */ + /* ??? If mnemonics have operands, try to print full mnemonic. */ + const char *name; +#define CGEN_INSN_NAME(insn) ((insn)->base->name) + + /* Mnemonic. This is used when parsing and printing the insn. + In the case of insns that have operands on the mnemonics, this is + only the constant part. E.g. for conditional execution of an `add' insn, + where the full mnemonic is addeq, addne, etc., and the condition is + treated as an operand, this is only "add". */ + const char *mnemonic; +#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) + + /* Total length of instruction, in bits. */ + int bitsize; +#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) + +#if 0 /* ??? Disabled for now as there is a problem with embedded newlines + and the table is already pretty big. Should perhaps be moved + to a file of its own. */ + /* Semantics, as RTL. */ + /* ??? Plain text or bytecodes? */ + /* ??? Note that the operand instance table could be computed at run-time + if we parse this and cache the results. Something to eventually do. */ + const char *rtx; +#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) +#endif + + /* Attributes. + This must appear last. It is a variable sized array in that one + architecture may have 1 nonbool attribute and another may have more. + Having this last means the non-architecture specific code needn't + care. The goal is to eventually record attributes in their raw form, + evaluate them at run-time, and cache the values, so this worry will go + away anyway. */ + CGEN_INSN_ATTR_TYPE attrs; +#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) +/* Return value of attribute ATTR in INSN. */ +#define CGEN_INSN_ATTR_VALUE(insn, attr) \ +CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ + CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +} CGEN_IBASE; + +/* Return non-zero if INSN is the "invalid" insn marker. */ + +#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) + +/* Main struct contain instruction information. + BASE is always present, the rest is present only if asked for. */ + +struct cgen_insn +{ + /* ??? May be of use to put a type indicator here. + Then this struct could different info for different classes of insns. */ + /* ??? A speedup can be had by moving `base' into this struct. + Maybe later. */ + const CGEN_IBASE *base; + const CGEN_OPCODE *opcode; + const CGEN_OPINST *opinst; + + /* Regex to disambiguate overloaded opcodes */ + void *rx; +#define CGEN_INSN_RX(insn) ((insn)->rx) +#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) +}; + +/* Instruction lists. + This is used for adding new entries and for creating the hash lists. */ + +typedef struct cgen_insn_list +{ + struct cgen_insn_list *next; + const CGEN_INSN *insn; +} CGEN_INSN_LIST; + +/* Table of instructions. */ + +typedef struct +{ + const CGEN_INSN *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + unsigned int num_init_entries; + CGEN_INSN_LIST *new_entries; +} CGEN_INSN_TABLE; + +/* Return number of instructions. This includes any added at run-time. */ + +extern int cgen_insn_count (CGEN_CPU_DESC); +extern int cgen_macro_insn_count (CGEN_CPU_DESC); + +/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ + +/* Fetch INSN's operand instance table. */ +/* ??? Doesn't handle insns added at runtime. */ +#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) + +/* Return INSN's opcode table entry. */ +#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) + +/* Return INSN's handler data. */ +#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) + +/* Return INSN's syntax. */ +#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) + +/* Return size of base mask in bits. */ +#define CGEN_INSN_MASK_BITSIZE(insn) \ + CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) + +/* Return mask of base part of INSN. */ +#define CGEN_INSN_BASE_MASK(insn) \ + CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) + +/* Return value of base part of INSN. */ +#define CGEN_INSN_BASE_VALUE(insn) \ + CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) + +/* Macro instructions. + Macro insns aren't real insns, they map to one or more real insns. + E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or + some such. + + Macro insns can expand to nothing (e.g. a nop that is optimized away). + This is useful in multi-insn macros that build a constant in a register. + Of course this isn't the default behaviour and must be explicitly enabled. + + Assembly of macro-insns is relatively straightforward. Disassembly isn't. + However, disassembly of at least some kinds of macro insns is important + in order that the disassembled code preserve the readability of the original + insn. What is attempted here is to disassemble all "simple" macro-insns, + where "simple" is currently defined to mean "expands to one real insn". + + Simple macro-insns are handled specially. They are emitted as ALIAS's + of real insns. This simplifies their handling since there's usually more + of them than any other kind of macro-insn, and proper disassembly of them + falls out for free. */ + +/* For each macro-insn there may be multiple expansion possibilities, + depending on the arguments. This structure is accessed via the `data' + member of CGEN_INSN. */ + +typedef struct cgen_minsn_expansion { + /* Function to do the expansion. + If the expansion fails (e.g. "no match") NULL is returned. + Space for the expansion is obtained with malloc. + It is up to the caller to free it. */ + const char * (* fn) + (const struct cgen_minsn_expansion *, + const char *, const char **, int *, + CGEN_OPERAND **); +#define CGEN_MIEXPN_FN(ex) ((ex)->fn) + + /* Instruction(s) the macro expands to. + The format of STR is defined by FN. + It is typically the assembly code of the real insn, but it could also be + the original Scheme expression or a tokenized form of it (with FN being + an appropriate interpreter). */ + const char * str; +#define CGEN_MIEXPN_STR(ex) ((ex)->str) +} CGEN_MINSN_EXPANSION; + +/* Normal expander. + When supported, this function will convert the input string to another + string and the parser will be invoked recursively. The output string + may contain further macro invocations. */ + +extern const char * cgen_expand_macro_insn + (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, + const char *, const char **, int *, CGEN_OPERAND **); + +/* The assembler insn table is hashed based on some function of the mnemonic + (the actually hashing done is up to the target, but we provide a few + examples like the first letter or a function of the entire mnemonic). */ + +extern CGEN_INSN_LIST * cgen_asm_lookup_insn + (CGEN_CPU_DESC, const char *); +#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) +#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) + +/* The disassembler insn table is hashed based on some function of machine + instruction (the actually hashing done is up to the target). */ + +extern CGEN_INSN_LIST * cgen_dis_lookup_insn + (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); +/* FIXME: delete these two */ +#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) +#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) + +/* The CPU description. + A copy of this is created when the cpu table is "opened". + All global state information is recorded here. + Access macros are provided for "public" members. */ + +typedef struct cgen_cpu_desc +{ + /* Bitmap of selected machine(s) (a la BFD machine number). */ + int machs; + + /* Bitmap of selected isa(s). */ + CGEN_BITSET *isas; +#define CGEN_CPU_ISAS(cd) ((cd)->isas) + + /* Current endian. */ + enum cgen_endian endian; +#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) + + /* Current insn endian. */ + enum cgen_endian insn_endian; +#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) + + /* Word size (in bits). */ + /* ??? Or maybe maximum word size - might we ever need to allow a cpu table + to be opened for both sparc32/sparc64? + ??? Another alternative is to create a table of selected machs and + lazily fetch the data from there. */ + unsigned int word_bitsize; + + /* Instruction chunk size (in bits), for purposes of endianness + conversion. */ + unsigned int insn_chunk_bitsize; + + /* Indicator if sizes are unknown. + This is used by default_insn_bitsize,base_insn_bitsize if there is a + difference between the selected isa's. */ +#define CGEN_SIZE_UNKNOWN 65535 + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; + + /* Instruction set variants. */ + const CGEN_ISA *isa_table; + + /* Machine variants. */ + const CGEN_MACH *mach_table; + + /* Hardware elements. */ + CGEN_HW_TABLE hw_table; + + /* Instruction fields. */ + const CGEN_IFLD *ifld_table; + + /* Operands. */ + CGEN_OPERAND_TABLE operand_table; + + /* Main instruction table. */ + CGEN_INSN_TABLE insn_table; +#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) + + /* Macro instructions are defined separately and are combined with real + insns during hash table computation. */ + CGEN_INSN_TABLE macro_insn_table; + + /* Copy of CGEN_INT_INSN_P. */ + int int_insn_p; + + /* Called to rebuild the tables after something has changed. */ + void (*rebuild_tables) (CGEN_CPU_DESC); + + /* Operand parser callback. */ + cgen_parse_operand_fn * parse_operand_fn; + + /* Parse/insert/extract/print cover fns for operands. */ + const char * (*parse_operand) + (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); +#ifdef __BFD_H_SEEN__ + const char * (*insert_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, + CGEN_INSN_BYTES_PTR, bfd_vma pc_); + int (*extract_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *fields_, bfd_vma pc_); + void (*print_operand) + (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, + void const *attrs_, bfd_vma pc_, int length_); +#else + const char * (*insert_operand) (); + int (*extract_operand) (); + void (*print_operand) (); +#endif +#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) +#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) +#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) +#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) + + /* Size of CGEN_FIELDS struct. */ + unsigned int sizeof_fields; +#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) + + /* Set the bitsize field. */ + void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); +#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) + + /* CGEN_FIELDS accessors. */ + int (*get_int_operand) + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); + void (*set_int_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); +#ifdef __BFD_H_SEEN__ + bfd_vma (*get_vma_operand) + (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); + void (*set_vma_operand) + (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); +#else + long (*get_vma_operand) (); + void (*set_vma_operand) (); +#endif +#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) +#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) +#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) +#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) + + /* Instruction parse/insert/extract/print handlers. */ + /* FIXME: make these types uppercase. */ + cgen_parse_fn * const *parse_handlers; + cgen_insert_fn * const *insert_handlers; + cgen_extract_fn * const *extract_handlers; + cgen_print_fn * const *print_handlers; +#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) +#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) +#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) +#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) + + /* Return non-zero if insn should be added to hash table. */ + int (* asm_hash_p) (const CGEN_INSN *); + + /* Assembler hash function. */ + unsigned int (* asm_hash) (const char *); + + /* Number of entries in assembler hash table. */ + unsigned int asm_hash_size; + + /* Return non-zero if insn should be added to hash table. */ + int (* dis_hash_p) (const CGEN_INSN *); + + /* Disassembler hash function. */ + unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); + + /* Number of entries in disassembler hash table. */ + unsigned int dis_hash_size; + + /* Assembler instruction hash table. */ + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; + + /* Disassembler instruction hash table. */ + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; + + /* This field could be turned into a bitfield if room for other flags is needed. */ + unsigned int signed_overflow_ok_p; + +} CGEN_CPU_TABLE; + +/* wip */ +#ifndef CGEN_WORD_ENDIAN +#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) +#endif +#ifndef CGEN_INSN_WORD_ENDIAN +#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) +#endif + +/* Prototypes of major functions. */ +/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. + Not the init fns though, as that would drag in things that mightn't be + used and might not even exist. */ + +/* Argument types to cpu_open. */ + +enum cgen_cpu_open_arg { + CGEN_CPU_OPEN_END, + /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_ISAS, + /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_MACHS, + /* Select machine, arg is mach's bfd name. + Multiple machines can be specified by repeated use. */ + CGEN_CPU_OPEN_BFDMACH, + /* Select endian, arg is CGEN_ENDIAN_*. */ + CGEN_CPU_OPEN_ENDIAN +}; + +/* Open a cpu descriptor table for use. + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); + +/* Cover fn to handle simple case. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) + (const char *mach_name_, enum cgen_endian endian_); + +/* Close it. */ + +extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); + +/* Initialize the opcode table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); + +/* build the insn selection regex. + called by init_opcode_table */ + +extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); + +/* Initialize the ibld table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); + +/* Initialize an cpu table for assembler or disassembler use. + These must be called immediately after cpu_open. */ + +extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); +extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); + +/* Initialize the operand instance table for use. */ + +extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); + +/* Assemble an instruction. */ + +extern const CGEN_INSN * CGEN_SYM (assemble_insn) + (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, + CGEN_INSN_BYTES_PTR, char **); + +extern const CGEN_KEYWORD CGEN_SYM (operand_mach); +extern int CGEN_SYM (get_mach) (const char *); + +/* Operand index computation. */ +extern const CGEN_INSN * cgen_lookup_insn + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, CGEN_FIELDS *fields_, int alias_p_); +extern void cgen_get_insn_operands + (CGEN_CPU_DESC, const CGEN_INSN * insn_, + const CGEN_FIELDS *fields_, int *indices_); +extern const CGEN_INSN * cgen_lookup_get_insn_operands + (CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, int *indices_, CGEN_FIELDS *fields_); + +/* Cover fns to bfd_get/set. */ + +extern CGEN_INSN_INT cgen_get_insn_value + (CGEN_CPU_DESC, unsigned char *, int); +extern void cgen_put_insn_value + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); + +/* Read in a cpu description file. + ??? For future concerns, including adding instructions to the assembler/ + disassembler at run-time. */ + +extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); + +/* Allow signed overflow of instruction fields. */ +extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); + +/* Generate an error message if a signed field in an instruction overflows. */ +extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); + +/* Will an error message be generated if a signed field in an instruction overflows ? */ +extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); + +#endif /* OPCODE_CGEN_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/convex.h b/external/gpl3/gdb/dist/include/opcode/convex.h new file mode 100644 index 000000000000..4643f5e06970 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/convex.h @@ -0,0 +1,1708 @@ +/* Information for instruction disassembly on the Convex. + Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define xxx 0 +#define rrr 1 +#define rr 2 +#define rxr 3 +#define r 4 +#define nops 5 +#define nr 6 +#define pcrel 7 +#define lr 8 +#define rxl 9 +#define rlr 10 +#define rrl 11 +#define iml 12 +#define imr 13 +#define a1r 14 +#define a1l 15 +#define a2r 16 +#define a2l 17 +#define a3 18 +#define a4 19 +#define a5 20 +#define V 1 +#define S 2 +#define VM 3 +#define A 4 +#define VL 5 +#define VS 6 +#define VLS 7 +#define PSW 8 +/* Prevent an error during "make depend". */ +#if !defined (PC) +#define PC 9 +#endif +#define ITR 10 +#define VV 11 +#define ITSR 12 +#define TOC 13 +#define CIR 14 +#define TTR 15 +#define VMU 16 +#define VML 17 +#define ICR 18 +#define TCPU 19 +#define CPUID 20 +#define TID 21 + +const char *op[] = { + "", + "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", + "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", + "vm", + "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", + "vl", + "vs", + "vls", + "psw", + "pc", + "itr", + "vv", + "itsr", + "toc", + "cir", + "ttr", + "vmu", + "vml", + "icr", + "tcpu", + "cpuid", + "tid", +}; + +const struct formstr format0[] = { + {0,0,rrr,V,S,S}, /* mov */ + {0,0,rrr,S,S,V}, /* mov */ + {1,1,rrr,V,V,V}, /* merg.t */ + {2,1,rrr,V,V,V}, /* mask.t */ + {1,2,rrr,V,S,V}, /* merg.f */ + {2,2,rrr,V,S,V}, /* mask.f */ + {1,1,rrr,V,S,V}, /* merg.t */ + {2,1,rrr,V,S,V}, /* mask.t */ + {3,3,rrr,V,V,V}, /* mul.s */ + {3,4,rrr,V,V,V}, /* mul.d */ + {4,3,rrr,V,V,V}, /* div.s */ + {4,4,rrr,V,V,V}, /* div.d */ + {3,3,rrr,V,S,V}, /* mul.s */ + {3,4,rrr,V,S,V}, /* mul.d */ + {4,3,rrr,V,S,V}, /* div.s */ + {4,4,rrr,V,S,V}, /* div.d */ + {5,0,rrr,V,V,V}, /* and */ + {6,0,rrr,V,V,V}, /* or */ + {7,0,rrr,V,V,V}, /* xor */ + {8,0,rrr,V,V,V}, /* shf */ + {5,0,rrr,V,S,V}, /* and */ + {6,0,rrr,V,S,V}, /* or */ + {7,0,rrr,V,S,V}, /* xor */ + {8,0,rrr,V,S,V}, /* shf */ + {9,3,rrr,V,V,V}, /* add.s */ + {9,4,rrr,V,V,V}, /* add.d */ + {10,3,rrr,V,V,V}, /* sub.s */ + {10,4,rrr,V,V,V}, /* sub.d */ + {9,3,rrr,V,S,V}, /* add.s */ + {9,4,rrr,V,S,V}, /* add.d */ + {10,3,rrr,V,S,V}, /* sub.s */ + {10,4,rrr,V,S,V}, /* sub.d */ + {9,5,rrr,V,V,V}, /* add.b */ + {9,6,rrr,V,V,V}, /* add.h */ + {9,7,rrr,V,V,V}, /* add.w */ + {9,8,rrr,V,V,V}, /* add.l */ + {9,5,rrr,V,S,V}, /* add.b */ + {9,6,rrr,V,S,V}, /* add.h */ + {9,7,rrr,V,S,V}, /* add.w */ + {9,8,rrr,V,S,V}, /* add.l */ + {10,5,rrr,V,V,V}, /* sub.b */ + {10,6,rrr,V,V,V}, /* sub.h */ + {10,7,rrr,V,V,V}, /* sub.w */ + {10,8,rrr,V,V,V}, /* sub.l */ + {10,5,rrr,V,S,V}, /* sub.b */ + {10,6,rrr,V,S,V}, /* sub.h */ + {10,7,rrr,V,S,V}, /* sub.w */ + {10,8,rrr,V,S,V}, /* sub.l */ + {3,5,rrr,V,V,V}, /* mul.b */ + {3,6,rrr,V,V,V}, /* mul.h */ + {3,7,rrr,V,V,V}, /* mul.w */ + {3,8,rrr,V,V,V}, /* mul.l */ + {3,5,rrr,V,S,V}, /* mul.b */ + {3,6,rrr,V,S,V}, /* mul.h */ + {3,7,rrr,V,S,V}, /* mul.w */ + {3,8,rrr,V,S,V}, /* mul.l */ + {4,5,rrr,V,V,V}, /* div.b */ + {4,6,rrr,V,V,V}, /* div.h */ + {4,7,rrr,V,V,V}, /* div.w */ + {4,8,rrr,V,V,V}, /* div.l */ + {4,5,rrr,V,S,V}, /* div.b */ + {4,6,rrr,V,S,V}, /* div.h */ + {4,7,rrr,V,S,V}, /* div.w */ + {4,8,rrr,V,S,V}, /* div.l */ +}; + +const struct formstr format1[] = { + {11,0,xxx,0,0,0}, /* exit */ + {12,0,a3,0,0,0}, /* jmp */ + {13,2,a3,0,0,0}, /* jmpi.f */ + {13,1,a3,0,0,0}, /* jmpi.t */ + {14,2,a3,0,0,0}, /* jmpa.f */ + {14,1,a3,0,0,0}, /* jmpa.t */ + {15,2,a3,0,0,0}, /* jmps.f */ + {15,1,a3,0,0,0}, /* jmps.t */ + {16,0,a3,0,0,0}, /* tac */ + {17,0,a1r,A,0,0}, /* ldea */ + {18,8,a1l,VLS,0,0}, /* ld.l */ + {18,9,a1l,VM,0,0}, /* ld.x */ + {19,0,a3,0,0,0}, /* tas */ + {20,0,a3,0,0,0}, /* pshea */ + {21,8,a2l,VLS,0,0}, /* st.l */ + {21,9,a2l,VM,0,0}, /* st.x */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {22,0,a3,0,0,0}, /* call */ + {23,0,a3,0,0,0}, /* calls */ + {24,0,a3,0,0,0}, /* callq */ + {25,0,a1r,A,0,0}, /* pfork */ + {26,5,a2r,S,0,0}, /* ste.b */ + {26,6,a2r,S,0,0}, /* ste.h */ + {26,7,a2r,S,0,0}, /* ste.w */ + {26,8,a2r,S,0,0}, /* ste.l */ + {18,5,a1r,A,0,0}, /* ld.b */ + {18,6,a1r,A,0,0}, /* ld.h */ + {18,7,a1r,A,0,0}, /* ld.w */ + {27,7,a1r,A,0,0}, /* incr.w */ + {21,5,a2r,A,0,0}, /* st.b */ + {21,6,a2r,A,0,0}, /* st.h */ + {21,7,a2r,A,0,0}, /* st.w */ + {27,8,a1r,S,0,0}, /* incr.l */ + {18,5,a1r,S,0,0}, /* ld.b */ + {18,6,a1r,S,0,0}, /* ld.h */ + {18,7,a1r,S,0,0}, /* ld.w */ + {18,8,a1r,S,0,0}, /* ld.l */ + {21,5,a2r,S,0,0}, /* st.b */ + {21,6,a2r,S,0,0}, /* st.h */ + {21,7,a2r,S,0,0}, /* st.w */ + {21,8,a2r,S,0,0}, /* st.l */ + {18,5,a1r,V,0,0}, /* ld.b */ + {18,6,a1r,V,0,0}, /* ld.h */ + {18,7,a1r,V,0,0}, /* ld.w */ + {18,8,a1r,V,0,0}, /* ld.l */ + {21,5,a2r,V,0,0}, /* st.b */ + {21,6,a2r,V,0,0}, /* st.h */ + {21,7,a2r,V,0,0}, /* st.w */ + {21,8,a2r,V,0,0}, /* st.l */ +}; + +const struct formstr format2[] = { + {28,5,rr,A,A,0}, /* cvtw.b */ + {28,6,rr,A,A,0}, /* cvtw.h */ + {29,7,rr,A,A,0}, /* cvtb.w */ + {30,7,rr,A,A,0}, /* cvth.w */ + {28,5,rr,S,S,0}, /* cvtw.b */ + {28,6,rr,S,S,0}, /* cvtw.h */ + {29,7,rr,S,S,0}, /* cvtb.w */ + {30,7,rr,S,S,0}, /* cvth.w */ + {28,3,rr,S,S,0}, /* cvtw.s */ + {31,7,rr,S,S,0}, /* cvts.w */ + {32,3,rr,S,S,0}, /* cvtd.s */ + {31,4,rr,S,S,0}, /* cvts.d */ + {31,8,rr,S,S,0}, /* cvts.l */ + {32,8,rr,S,S,0}, /* cvtd.l */ + {33,3,rr,S,S,0}, /* cvtl.s */ + {33,4,rr,S,S,0}, /* cvtl.d */ + {34,0,rr,A,A,0}, /* ldpa */ + {8,0,nr,A,0,0}, /* shf */ + {18,6,nr,A,0,0}, /* ld.h */ + {18,7,nr,A,0,0}, /* ld.w */ + {33,7,rr,S,S,0}, /* cvtl.w */ + {28,8,rr,S,S,0}, /* cvtw.l */ + {35,1,rr,S,S,0}, /* plc.t */ + {36,0,rr,S,S,0}, /* tzc */ + {37,6,rr,A,A,0}, /* eq.h */ + {37,7,rr,A,A,0}, /* eq.w */ + {37,6,nr,A,0,0}, /* eq.h */ + {37,7,nr,A,0,0}, /* eq.w */ + {37,5,rr,S,S,0}, /* eq.b */ + {37,6,rr,S,S,0}, /* eq.h */ + {37,7,rr,S,S,0}, /* eq.w */ + {37,8,rr,S,S,0}, /* eq.l */ + {38,6,rr,A,A,0}, /* leu.h */ + {38,7,rr,A,A,0}, /* leu.w */ + {38,6,nr,A,0,0}, /* leu.h */ + {38,7,nr,A,0,0}, /* leu.w */ + {38,5,rr,S,S,0}, /* leu.b */ + {38,6,rr,S,S,0}, /* leu.h */ + {38,7,rr,S,S,0}, /* leu.w */ + {38,8,rr,S,S,0}, /* leu.l */ + {39,6,rr,A,A,0}, /* ltu.h */ + {39,7,rr,A,A,0}, /* ltu.w */ + {39,6,nr,A,0,0}, /* ltu.h */ + {39,7,nr,A,0,0}, /* ltu.w */ + {39,5,rr,S,S,0}, /* ltu.b */ + {39,6,rr,S,S,0}, /* ltu.h */ + {39,7,rr,S,S,0}, /* ltu.w */ + {39,8,rr,S,S,0}, /* ltu.l */ + {40,6,rr,A,A,0}, /* le.h */ + {40,7,rr,A,A,0}, /* le.w */ + {40,6,nr,A,0,0}, /* le.h */ + {40,7,nr,A,0,0}, /* le.w */ + {40,5,rr,S,S,0}, /* le.b */ + {40,6,rr,S,S,0}, /* le.h */ + {40,7,rr,S,S,0}, /* le.w */ + {40,8,rr,S,S,0}, /* le.l */ + {41,6,rr,A,A,0}, /* lt.h */ + {41,7,rr,A,A,0}, /* lt.w */ + {41,6,nr,A,0,0}, /* lt.h */ + {41,7,nr,A,0,0}, /* lt.w */ + {41,5,rr,S,S,0}, /* lt.b */ + {41,6,rr,S,S,0}, /* lt.h */ + {41,7,rr,S,S,0}, /* lt.w */ + {41,8,rr,S,S,0}, /* lt.l */ + {9,7,rr,S,A,0}, /* add.w */ + {8,0,rr,A,A,0}, /* shf */ + {0,0,rr,A,A,0}, /* mov */ + {0,0,rr,S,A,0}, /* mov */ + {0,7,rr,S,S,0}, /* mov.w */ + {8,0,rr,S,S,0}, /* shf */ + {0,0,rr,S,S,0}, /* mov */ + {0,0,rr,A,S,0}, /* mov */ + {5,0,rr,A,A,0}, /* and */ + {6,0,rr,A,A,0}, /* or */ + {7,0,rr,A,A,0}, /* xor */ + {42,0,rr,A,A,0}, /* not */ + {5,0,rr,S,S,0}, /* and */ + {6,0,rr,S,S,0}, /* or */ + {7,0,rr,S,S,0}, /* xor */ + {42,0,rr,S,S,0}, /* not */ + {40,3,rr,S,S,0}, /* le.s */ + {40,4,rr,S,S,0}, /* le.d */ + {41,3,rr,S,S,0}, /* lt.s */ + {41,4,rr,S,S,0}, /* lt.d */ + {9,3,rr,S,S,0}, /* add.s */ + {9,4,rr,S,S,0}, /* add.d */ + {10,3,rr,S,S,0}, /* sub.s */ + {10,4,rr,S,S,0}, /* sub.d */ + {37,3,rr,S,S,0}, /* eq.s */ + {37,4,rr,S,S,0}, /* eq.d */ + {43,6,rr,A,A,0}, /* neg.h */ + {43,7,rr,A,A,0}, /* neg.w */ + {3,3,rr,S,S,0}, /* mul.s */ + {3,4,rr,S,S,0}, /* mul.d */ + {4,3,rr,S,S,0}, /* div.s */ + {4,4,rr,S,S,0}, /* div.d */ + {9,6,rr,A,A,0}, /* add.h */ + {9,7,rr,A,A,0}, /* add.w */ + {9,6,nr,A,0,0}, /* add.h */ + {9,7,nr,A,0,0}, /* add.w */ + {9,5,rr,S,S,0}, /* add.b */ + {9,6,rr,S,S,0}, /* add.h */ + {9,7,rr,S,S,0}, /* add.w */ + {9,8,rr,S,S,0}, /* add.l */ + {10,6,rr,A,A,0}, /* sub.h */ + {10,7,rr,A,A,0}, /* sub.w */ + {10,6,nr,A,0,0}, /* sub.h */ + {10,7,nr,A,0,0}, /* sub.w */ + {10,5,rr,S,S,0}, /* sub.b */ + {10,6,rr,S,S,0}, /* sub.h */ + {10,7,rr,S,S,0}, /* sub.w */ + {10,8,rr,S,S,0}, /* sub.l */ + {3,6,rr,A,A,0}, /* mul.h */ + {3,7,rr,A,A,0}, /* mul.w */ + {3,6,nr,A,0,0}, /* mul.h */ + {3,7,nr,A,0,0}, /* mul.w */ + {3,5,rr,S,S,0}, /* mul.b */ + {3,6,rr,S,S,0}, /* mul.h */ + {3,7,rr,S,S,0}, /* mul.w */ + {3,8,rr,S,S,0}, /* mul.l */ + {4,6,rr,A,A,0}, /* div.h */ + {4,7,rr,A,A,0}, /* div.w */ + {4,6,nr,A,0,0}, /* div.h */ + {4,7,nr,A,0,0}, /* div.w */ + {4,5,rr,S,S,0}, /* div.b */ + {4,6,rr,S,S,0}, /* div.h */ + {4,7,rr,S,S,0}, /* div.w */ + {4,8,rr,S,S,0}, /* div.l */ +}; + +const struct formstr format3[] = { + {32,3,rr,V,V,0}, /* cvtd.s */ + {31,4,rr,V,V,0}, /* cvts.d */ + {33,4,rr,V,V,0}, /* cvtl.d */ + {32,8,rr,V,V,0}, /* cvtd.l */ + {0,0,rrl,S,S,VM}, /* mov */ + {0,0,rlr,S,VM,S}, /* mov */ + {0,0,0,0,0,0}, + {44,0,rr,S,S,0}, /* lop */ + {36,0,rr,V,V,0}, /* tzc */ + {44,0,rr,V,V,0}, /* lop */ + {0,0,0,0,0,0}, + {42,0,rr,V,V,0}, /* not */ + {8,0,rr,S,V,0}, /* shf */ + {35,1,rr,V,V,0}, /* plc.t */ + {45,2,rr,V,V,0}, /* cprs.f */ + {45,1,rr,V,V,0}, /* cprs.t */ + {37,3,rr,V,V,0}, /* eq.s */ + {37,4,rr,V,V,0}, /* eq.d */ + {43,3,rr,V,V,0}, /* neg.s */ + {43,4,rr,V,V,0}, /* neg.d */ + {37,3,rr,S,V,0}, /* eq.s */ + {37,4,rr,S,V,0}, /* eq.d */ + {43,3,rr,S,S,0}, /* neg.s */ + {43,4,rr,S,S,0}, /* neg.d */ + {40,3,rr,V,V,0}, /* le.s */ + {40,4,rr,V,V,0}, /* le.d */ + {41,3,rr,V,V,0}, /* lt.s */ + {41,4,rr,V,V,0}, /* lt.d */ + {40,3,rr,S,V,0}, /* le.s */ + {40,4,rr,S,V,0}, /* le.d */ + {41,3,rr,S,V,0}, /* lt.s */ + {41,4,rr,S,V,0}, /* lt.d */ + {37,5,rr,V,V,0}, /* eq.b */ + {37,6,rr,V,V,0}, /* eq.h */ + {37,7,rr,V,V,0}, /* eq.w */ + {37,8,rr,V,V,0}, /* eq.l */ + {37,5,rr,S,V,0}, /* eq.b */ + {37,6,rr,S,V,0}, /* eq.h */ + {37,7,rr,S,V,0}, /* eq.w */ + {37,8,rr,S,V,0}, /* eq.l */ + {40,5,rr,V,V,0}, /* le.b */ + {40,6,rr,V,V,0}, /* le.h */ + {40,7,rr,V,V,0}, /* le.w */ + {40,8,rr,V,V,0}, /* le.l */ + {40,5,rr,S,V,0}, /* le.b */ + {40,6,rr,S,V,0}, /* le.h */ + {40,7,rr,S,V,0}, /* le.w */ + {40,8,rr,S,V,0}, /* le.l */ + {41,5,rr,V,V,0}, /* lt.b */ + {41,6,rr,V,V,0}, /* lt.h */ + {41,7,rr,V,V,0}, /* lt.w */ + {41,8,rr,V,V,0}, /* lt.l */ + {41,5,rr,S,V,0}, /* lt.b */ + {41,6,rr,S,V,0}, /* lt.h */ + {41,7,rr,S,V,0}, /* lt.w */ + {41,8,rr,S,V,0}, /* lt.l */ + {43,5,rr,V,V,0}, /* neg.b */ + {43,6,rr,V,V,0}, /* neg.h */ + {43,7,rr,V,V,0}, /* neg.w */ + {43,8,rr,V,V,0}, /* neg.l */ + {43,5,rr,S,S,0}, /* neg.b */ + {43,6,rr,S,S,0}, /* neg.h */ + {43,7,rr,S,S,0}, /* neg.w */ + {43,8,rr,S,S,0}, /* neg.l */ +}; + +const struct formstr format4[] = { + {46,0,nops,0,0,0}, /* nop */ + {47,0,pcrel,0,0,0}, /* br */ + {48,2,pcrel,0,0,0}, /* bri.f */ + {48,1,pcrel,0,0,0}, /* bri.t */ + {49,2,pcrel,0,0,0}, /* bra.f */ + {49,1,pcrel,0,0,0}, /* bra.t */ + {50,2,pcrel,0,0,0}, /* brs.f */ + {50,1,pcrel,0,0,0}, /* brs.t */ +}; + +const struct formstr format5[] = { + {51,5,rr,V,V,0}, /* ldvi.b */ + {51,6,rr,V,V,0}, /* ldvi.h */ + {51,7,rr,V,V,0}, /* ldvi.w */ + {51,8,rr,V,V,0}, /* ldvi.l */ + {28,3,rr,V,V,0}, /* cvtw.s */ + {31,7,rr,V,V,0}, /* cvts.w */ + {28,8,rr,V,V,0}, /* cvtw.l */ + {33,7,rr,V,V,0}, /* cvtl.w */ + {52,5,rxr,V,V,0}, /* stvi.b */ + {52,6,rxr,V,V,0}, /* stvi.h */ + {52,7,rxr,V,V,0}, /* stvi.w */ + {52,8,rxr,V,V,0}, /* stvi.l */ + {52,5,rxr,S,V,0}, /* stvi.b */ + {52,6,rxr,S,V,0}, /* stvi.h */ + {52,7,rxr,S,V,0}, /* stvi.w */ + {52,8,rxr,S,V,0}, /* stvi.l */ +}; + +const struct formstr format6[] = { + {53,0,r,A,0,0}, /* ldsdr */ + {54,0,r,A,0,0}, /* ldkdr */ + {55,3,r,S,0,0}, /* ln.s */ + {55,4,r,S,0,0}, /* ln.d */ + {56,0,nops,0,0,0}, /* patu */ + {57,0,r,A,0,0}, /* pate */ + {58,0,nops,0,0,0}, /* pich */ + {59,0,nops,0,0,0}, /* plch */ + {0,0,lr,PSW,A,0}, /* mov */ + {0,0,rxl,A,PSW,0}, /* mov */ + {0,0,lr,PC,A,0}, /* mov */ + {60,0,r,S,0,0}, /* idle */ + {0,0,lr,ITR,S,0}, /* mov */ + {0,0,rxl,S,ITR,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,rxl,S,ITSR,0}, /* mov */ + {61,0,nops,0,0,0}, /* rtnq */ + {62,0,nops,0,0,0}, /* cfork */ + {63,0,nops,0,0,0}, /* rtn */ + {64,0,nops,0,0,0}, /* wfork */ + {65,0,nops,0,0,0}, /* join */ + {66,0,nops,0,0,0}, /* rtnc */ + {67,3,r,S,0,0}, /* exp.s */ + {67,4,r,S,0,0}, /* exp.d */ + {68,3,r,S,0,0}, /* sin.s */ + {68,4,r,S,0,0}, /* sin.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {69,3,r,S,0,0}, /* cos.s */ + {69,4,r,S,0,0}, /* cos.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {70,7,r,A,0,0}, /* psh.w */ + {0,0,0,0,0,0}, + {71,7,r,A,0,0}, /* pop.w */ + {0,0,0,0,0,0}, + {70,7,r,S,0,0}, /* psh.w */ + {70,8,r,S,0,0}, /* psh.l */ + {71,7,r,S,0,0}, /* pop.w */ + {71,8,r,S,0,0}, /* pop.l */ + {72,0,nops,0,0,0}, /* eni */ + {73,0,nops,0,0,0}, /* dsi */ + {74,0,nops,0,0,0}, /* bkpt */ + {75,0,nops,0,0,0}, /* msync */ + {76,0,r,S,0,0}, /* mski */ + {77,0,r,S,0,0}, /* xmti */ + {0,0,rxl,S,VV,0}, /* mov */ + {78,0,nops,0,0,0}, /* tstvv */ + {0,0,lr,VS,A,0}, /* mov */ + {0,0,rxl,A,VS,0}, /* mov */ + {0,0,lr,VL,A,0}, /* mov */ + {0,0,rxl,A,VL,0}, /* mov */ + {0,7,lr,VS,S,0}, /* mov.w */ + {0,7,rxl,S,VS,0}, /* mov.w */ + {0,7,lr,VL,S,0}, /* mov.w */ + {0,7,rxl,S,VL,0}, /* mov.w */ + {79,0,r,A,0,0}, /* diag */ + {80,0,nops,0,0,0}, /* pbkpt */ + {81,3,r,S,0,0}, /* sqrt.s */ + {81,4,r,S,0,0}, /* sqrt.d */ + {82,0,nops,0,0,0}, /* casr */ + {0,0,0,0,0,0}, + {83,3,r,S,0,0}, /* atan.s */ + {83,4,r,S,0,0}, /* atan.d */ +}; + +const struct formstr format7[] = { + {84,5,r,V,0,0}, /* sum.b */ + {84,6,r,V,0,0}, /* sum.h */ + {84,7,r,V,0,0}, /* sum.w */ + {84,8,r,V,0,0}, /* sum.l */ + {85,0,r,V,0,0}, /* all */ + {86,0,r,V,0,0}, /* any */ + {87,0,r,V,0,0}, /* parity */ + {0,0,0,0,0,0}, + {88,5,r,V,0,0}, /* max.b */ + {88,6,r,V,0,0}, /* max.h */ + {88,7,r,V,0,0}, /* max.w */ + {88,8,r,V,0,0}, /* max.l */ + {89,5,r,V,0,0}, /* min.b */ + {89,6,r,V,0,0}, /* min.h */ + {89,7,r,V,0,0}, /* min.w */ + {89,8,r,V,0,0}, /* min.l */ + {84,3,r,V,0,0}, /* sum.s */ + {84,4,r,V,0,0}, /* sum.d */ + {90,3,r,V,0,0}, /* prod.s */ + {90,4,r,V,0,0}, /* prod.d */ + {88,3,r,V,0,0}, /* max.s */ + {88,4,r,V,0,0}, /* max.d */ + {89,3,r,V,0,0}, /* min.s */ + {89,4,r,V,0,0}, /* min.d */ + {90,5,r,V,0,0}, /* prod.b */ + {90,6,r,V,0,0}, /* prod.h */ + {90,7,r,V,0,0}, /* prod.w */ + {90,8,r,V,0,0}, /* prod.l */ + {35,2,lr,VM,S,0}, /* plc.f */ + {35,1,lr,VM,S,0}, /* plc.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr formatx[] = { + {0,0,0,0,0,0}, +}; + +const struct formstr format1a[] = { + {91,0,imr,A,0,0}, /* halt */ + {92,0,a4,0,0,0}, /* sysc */ + {18,6,imr,A,0,0}, /* ld.h */ + {18,7,imr,A,0,0}, /* ld.w */ + {5,0,imr,A,0,0}, /* and */ + {6,0,imr,A,0,0}, /* or */ + {7,0,imr,A,0,0}, /* xor */ + {8,0,imr,A,0,0}, /* shf */ + {9,6,imr,A,0,0}, /* add.h */ + {9,7,imr,A,0,0}, /* add.w */ + {10,6,imr,A,0,0}, /* sub.h */ + {10,7,imr,A,0,0}, /* sub.w */ + {3,6,imr,A,0,0}, /* mul.h */ + {3,7,imr,A,0,0}, /* mul.w */ + {4,6,imr,A,0,0}, /* div.h */ + {4,7,imr,A,0,0}, /* div.w */ + {18,7,iml,VL,0,0}, /* ld.w */ + {18,7,iml,VS,0,0}, /* ld.w */ + {0,0,0,0,0,0}, + {8,7,imr,S,0,0}, /* shf.w */ + {93,0,a5,0,0,0}, /* trap */ + {0,0,0,0,0,0}, + {37,6,imr,A,0,0}, /* eq.h */ + {37,7,imr,A,0,0}, /* eq.w */ + {38,6,imr,A,0,0}, /* leu.h */ + {38,7,imr,A,0,0}, /* leu.w */ + {39,6,imr,A,0,0}, /* ltu.h */ + {39,7,imr,A,0,0}, /* ltu.w */ + {40,6,imr,A,0,0}, /* le.h */ + {40,7,imr,A,0,0}, /* le.w */ + {41,6,imr,A,0,0}, /* lt.h */ + {41,7,imr,A,0,0}, /* lt.w */ +}; + +const struct formstr format1b[] = { + {18,4,imr,S,0,0}, /* ld.d */ + {18,10,imr,S,0,0}, /* ld.u */ + {18,8,imr,S,0,0}, /* ld.l */ + {18,7,imr,S,0,0}, /* ld.w */ + {5,0,imr,S,0,0}, /* and */ + {6,0,imr,S,0,0}, /* or */ + {7,0,imr,S,0,0}, /* xor */ + {8,0,imr,S,0,0}, /* shf */ + {9,6,imr,S,0,0}, /* add.h */ + {9,7,imr,S,0,0}, /* add.w */ + {10,6,imr,S,0,0}, /* sub.h */ + {10,7,imr,S,0,0}, /* sub.w */ + {3,6,imr,S,0,0}, /* mul.h */ + {3,7,imr,S,0,0}, /* mul.w */ + {4,6,imr,S,0,0}, /* div.h */ + {4,7,imr,S,0,0}, /* div.w */ + {9,3,imr,S,0,0}, /* add.s */ + {10,3,imr,S,0,0}, /* sub.s */ + {3,3,imr,S,0,0}, /* mul.s */ + {4,3,imr,S,0,0}, /* div.s */ + {40,3,imr,S,0,0}, /* le.s */ + {41,3,imr,S,0,0}, /* lt.s */ + {37,6,imr,S,0,0}, /* eq.h */ + {37,7,imr,S,0,0}, /* eq.w */ + {38,6,imr,S,0,0}, /* leu.h */ + {38,7,imr,S,0,0}, /* leu.w */ + {39,6,imr,S,0,0}, /* ltu.h */ + {39,7,imr,S,0,0}, /* ltu.w */ + {40,6,imr,S,0,0}, /* le.h */ + {40,7,imr,S,0,0}, /* le.w */ + {41,6,imr,S,0,0}, /* lt.h */ + {41,7,imr,S,0,0}, /* lt.w */ +}; + +const struct formstr e0_format0[] = { + {10,3,rrr,S,V,V}, /* sub.s */ + {10,4,rrr,S,V,V}, /* sub.d */ + {4,3,rrr,S,V,V}, /* div.s */ + {4,4,rrr,S,V,V}, /* div.d */ + {10,11,rrr,S,V,V}, /* sub.s.f */ + {10,12,rrr,S,V,V}, /* sub.d.f */ + {4,11,rrr,S,V,V}, /* div.s.f */ + {4,12,rrr,S,V,V}, /* div.d.f */ + {3,11,rrr,V,V,V}, /* mul.s.f */ + {3,12,rrr,V,V,V}, /* mul.d.f */ + {4,11,rrr,V,V,V}, /* div.s.f */ + {4,12,rrr,V,V,V}, /* div.d.f */ + {3,11,rrr,V,S,V}, /* mul.s.f */ + {3,12,rrr,V,S,V}, /* mul.d.f */ + {4,11,rrr,V,S,V}, /* div.s.f */ + {4,12,rrr,V,S,V}, /* div.d.f */ + {5,2,rrr,V,V,V}, /* and.f */ + {6,2,rrr,V,V,V}, /* or.f */ + {7,2,rrr,V,V,V}, /* xor.f */ + {8,2,rrr,V,V,V}, /* shf.f */ + {5,2,rrr,V,S,V}, /* and.f */ + {6,2,rrr,V,S,V}, /* or.f */ + {7,2,rrr,V,S,V}, /* xor.f */ + {8,2,rrr,V,S,V}, /* shf.f */ + {9,11,rrr,V,V,V}, /* add.s.f */ + {9,12,rrr,V,V,V}, /* add.d.f */ + {10,11,rrr,V,V,V}, /* sub.s.f */ + {10,12,rrr,V,V,V}, /* sub.d.f */ + {9,11,rrr,V,S,V}, /* add.s.f */ + {9,12,rrr,V,S,V}, /* add.d.f */ + {10,11,rrr,V,S,V}, /* sub.s.f */ + {10,12,rrr,V,S,V}, /* sub.d.f */ + {9,13,rrr,V,V,V}, /* add.b.f */ + {9,14,rrr,V,V,V}, /* add.h.f */ + {9,15,rrr,V,V,V}, /* add.w.f */ + {9,16,rrr,V,V,V}, /* add.l.f */ + {9,13,rrr,V,S,V}, /* add.b.f */ + {9,14,rrr,V,S,V}, /* add.h.f */ + {9,15,rrr,V,S,V}, /* add.w.f */ + {9,16,rrr,V,S,V}, /* add.l.f */ + {10,13,rrr,V,V,V}, /* sub.b.f */ + {10,14,rrr,V,V,V}, /* sub.h.f */ + {10,15,rrr,V,V,V}, /* sub.w.f */ + {10,16,rrr,V,V,V}, /* sub.l.f */ + {10,13,rrr,V,S,V}, /* sub.b.f */ + {10,14,rrr,V,S,V}, /* sub.h.f */ + {10,15,rrr,V,S,V}, /* sub.w.f */ + {10,16,rrr,V,S,V}, /* sub.l.f */ + {3,13,rrr,V,V,V}, /* mul.b.f */ + {3,14,rrr,V,V,V}, /* mul.h.f */ + {3,15,rrr,V,V,V}, /* mul.w.f */ + {3,16,rrr,V,V,V}, /* mul.l.f */ + {3,13,rrr,V,S,V}, /* mul.b.f */ + {3,14,rrr,V,S,V}, /* mul.h.f */ + {3,15,rrr,V,S,V}, /* mul.w.f */ + {3,16,rrr,V,S,V}, /* mul.l.f */ + {4,13,rrr,V,V,V}, /* div.b.f */ + {4,14,rrr,V,V,V}, /* div.h.f */ + {4,15,rrr,V,V,V}, /* div.w.f */ + {4,16,rrr,V,V,V}, /* div.l.f */ + {4,13,rrr,V,S,V}, /* div.b.f */ + {4,14,rrr,V,S,V}, /* div.h.f */ + {4,15,rrr,V,S,V}, /* div.w.f */ + {4,16,rrr,V,S,V}, /* div.l.f */ +}; + +const struct formstr e0_format1[] = { + {0,0,0,0,0,0}, + {94,0,a3,0,0,0}, /* tst */ + {95,0,a3,0,0,0}, /* lck */ + {96,0,a3,0,0,0}, /* ulk */ + {17,0,a1r,S,0,0}, /* ldea */ + {97,0,a1r,A,0,0}, /* spawn */ + {98,0,a1r,A,0,0}, /* ldcmr */ + {99,0,a2r,A,0,0}, /* stcmr */ + {100,0,a1r,A,0,0}, /* popr */ + {101,0,a2r,A,0,0}, /* pshr */ + {102,7,a1r,A,0,0}, /* rcvr.w */ + {103,7,a2r,A,0,0}, /* matm.w */ + {104,7,a2r,A,0,0}, /* sndr.w */ + {104,8,a2r,S,0,0}, /* sndr.l */ + {102,8,a1r,S,0,0}, /* rcvr.l */ + {103,8,a2r,S,0,0}, /* matm.l */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {105,7,a2r,A,0,0}, /* putr.w */ + {105,8,a2r,S,0,0}, /* putr.l */ + {106,7,a1r,A,0,0}, /* getr.w */ + {106,8,a1r,S,0,0}, /* getr.l */ + {26,13,a2r,S,0,0}, /* ste.b.f */ + {26,14,a2r,S,0,0}, /* ste.h.f */ + {26,15,a2r,S,0,0}, /* ste.w.f */ + {26,16,a2r,S,0,0}, /* ste.l.f */ + {107,7,a2r,A,0,0}, /* matr.w */ + {108,7,a2r,A,0,0}, /* mat.w */ + {109,7,a1r,A,0,0}, /* get.w */ + {110,7,a1r,A,0,0}, /* rcv.w */ + {0,0,0,0,0,0}, + {111,7,a1r,A,0,0}, /* inc.w */ + {112,7,a2r,A,0,0}, /* put.w */ + {113,7,a2r,A,0,0}, /* snd.w */ + {107,8,a2r,S,0,0}, /* matr.l */ + {108,8,a2r,S,0,0}, /* mat.l */ + {109,8,a1r,S,0,0}, /* get.l */ + {110,8,a1r,S,0,0}, /* rcv.l */ + {0,0,0,0,0,0}, + {111,8,a1r,S,0,0}, /* inc.l */ + {112,8,a2r,S,0,0}, /* put.l */ + {113,8,a2r,S,0,0}, /* snd.l */ + {18,13,a1r,V,0,0}, /* ld.b.f */ + {18,14,a1r,V,0,0}, /* ld.h.f */ + {18,15,a1r,V,0,0}, /* ld.w.f */ + {18,16,a1r,V,0,0}, /* ld.l.f */ + {21,13,a2r,V,0,0}, /* st.b.f */ + {21,14,a2r,V,0,0}, /* st.h.f */ + {21,15,a2r,V,0,0}, /* st.w.f */ + {21,16,a2r,V,0,0}, /* st.l.f */ +}; + +const struct formstr e0_format2[] = { + {28,5,rr,V,V,0}, /* cvtw.b */ + {28,6,rr,V,V,0}, /* cvtw.h */ + {29,7,rr,V,V,0}, /* cvtb.w */ + {30,7,rr,V,V,0}, /* cvth.w */ + {28,13,rr,V,V,0}, /* cvtw.b.f */ + {28,14,rr,V,V,0}, /* cvtw.h.f */ + {29,15,rr,V,V,0}, /* cvtb.w.f */ + {30,15,rr,V,V,0}, /* cvth.w.f */ + {31,8,rr,V,V,0}, /* cvts.l */ + {32,7,rr,V,V,0}, /* cvtd.w */ + {33,3,rr,V,V,0}, /* cvtl.s */ + {28,4,rr,V,V,0}, /* cvtw.d */ + {31,16,rr,V,V,0}, /* cvts.l.f */ + {32,15,rr,V,V,0}, /* cvtd.w.f */ + {33,11,rr,V,V,0}, /* cvtl.s.f */ + {28,12,rr,V,V,0}, /* cvtw.d.f */ + {114,0,rr,S,S,0}, /* enal */ + {8,7,rr,S,S,0}, /* shf.w */ + {115,0,rr,S,S,0}, /* enag */ + {0,0,0,0,0,0}, + {28,4,rr,S,S,0}, /* cvtw.d */ + {32,7,rr,S,S,0}, /* cvtd.w */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,3,rr,S,S,0}, /* frint.s */ + {116,4,rr,S,S,0}, /* frint.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,3,rr,V,V,0}, /* frint.s */ + {116,4,rr,V,V,0}, /* frint.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,11,rr,V,V,0}, /* frint.s.f */ + {116,12,rr,V,V,0}, /* frint.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,3,rr,V,V,0}, /* sqrt.s */ + {81,4,rr,V,V,0}, /* sqrt.d */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,11,rr,V,V,0}, /* sqrt.s.f */ + {81,12,rr,V,V,0}, /* sqrt.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format3[] = { + {32,11,rr,V,V,0}, /* cvtd.s.f */ + {31,12,rr,V,V,0}, /* cvts.d.f */ + {33,12,rr,V,V,0}, /* cvtl.d.f */ + {32,16,rr,V,V,0}, /* cvtd.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {36,2,rr,V,V,0}, /* tzc.f */ + {44,2,rr,V,V,0}, /* lop.f */ + {117,2,rr,V,V,0}, /* xpnd.f */ + {42,2,rr,V,V,0}, /* not.f */ + {8,2,rr,S,V,0}, /* shf.f */ + {35,17,rr,V,V,0}, /* plc.t.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {37,11,rr,V,V,0}, /* eq.s.f */ + {37,12,rr,V,V,0}, /* eq.d.f */ + {43,11,rr,V,V,0}, /* neg.s.f */ + {43,12,rr,V,V,0}, /* neg.d.f */ + {37,11,rr,S,V,0}, /* eq.s.f */ + {37,12,rr,S,V,0}, /* eq.d.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {40,11,rr,V,V,0}, /* le.s.f */ + {40,12,rr,V,V,0}, /* le.d.f */ + {41,11,rr,V,V,0}, /* lt.s.f */ + {41,12,rr,V,V,0}, /* lt.d.f */ + {40,11,rr,S,V,0}, /* le.s.f */ + {40,12,rr,S,V,0}, /* le.d.f */ + {41,11,rr,S,V,0}, /* lt.s.f */ + {41,12,rr,S,V,0}, /* lt.d.f */ + {37,13,rr,V,V,0}, /* eq.b.f */ + {37,14,rr,V,V,0}, /* eq.h.f */ + {37,15,rr,V,V,0}, /* eq.w.f */ + {37,16,rr,V,V,0}, /* eq.l.f */ + {37,13,rr,S,V,0}, /* eq.b.f */ + {37,14,rr,S,V,0}, /* eq.h.f */ + {37,15,rr,S,V,0}, /* eq.w.f */ + {37,16,rr,S,V,0}, /* eq.l.f */ + {40,13,rr,V,V,0}, /* le.b.f */ + {40,14,rr,V,V,0}, /* le.h.f */ + {40,15,rr,V,V,0}, /* le.w.f */ + {40,16,rr,V,V,0}, /* le.l.f */ + {40,13,rr,S,V,0}, /* le.b.f */ + {40,14,rr,S,V,0}, /* le.h.f */ + {40,15,rr,S,V,0}, /* le.w.f */ + {40,16,rr,S,V,0}, /* le.l.f */ + {41,13,rr,V,V,0}, /* lt.b.f */ + {41,14,rr,V,V,0}, /* lt.h.f */ + {41,15,rr,V,V,0}, /* lt.w.f */ + {41,16,rr,V,V,0}, /* lt.l.f */ + {41,13,rr,S,V,0}, /* lt.b.f */ + {41,14,rr,S,V,0}, /* lt.h.f */ + {41,15,rr,S,V,0}, /* lt.w.f */ + {41,16,rr,S,V,0}, /* lt.l.f */ + {43,13,rr,V,V,0}, /* neg.b.f */ + {43,14,rr,V,V,0}, /* neg.h.f */ + {43,15,rr,V,V,0}, /* neg.w.f */ + {43,16,rr,V,V,0}, /* neg.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format4[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format5[] = { + {51,13,rr,V,V,0}, /* ldvi.b.f */ + {51,14,rr,V,V,0}, /* ldvi.h.f */ + {51,15,rr,V,V,0}, /* ldvi.w.f */ + {51,16,rr,V,V,0}, /* ldvi.l.f */ + {28,11,rr,V,V,0}, /* cvtw.s.f */ + {31,15,rr,V,V,0}, /* cvts.w.f */ + {28,16,rr,V,V,0}, /* cvtw.l.f */ + {33,15,rr,V,V,0}, /* cvtl.w.f */ + {52,13,rxr,V,V,0}, /* stvi.b.f */ + {52,14,rxr,V,V,0}, /* stvi.h.f */ + {52,15,rxr,V,V,0}, /* stvi.w.f */ + {52,16,rxr,V,V,0}, /* stvi.l.f */ + {52,13,rxr,S,V,0}, /* stvi.b.f */ + {52,14,rxr,S,V,0}, /* stvi.h.f */ + {52,15,rxr,S,V,0}, /* stvi.w.f */ + {52,16,rxr,S,V,0}, /* stvi.l.f */ +}; + +const struct formstr e0_format6[] = { + {0,0,rxl,S,CIR,0}, /* mov */ + {0,0,lr,CIR,S,0}, /* mov */ + {0,0,lr,TOC,S,0}, /* mov */ + {0,0,lr,CPUID,S,0}, /* mov */ + {0,0,rxl,S,TTR,0}, /* mov */ + {0,0,lr,TTR,S,0}, /* mov */ + {118,0,nops,0,0,0}, /* ctrsl */ + {119,0,nops,0,0,0}, /* ctrsg */ + {0,0,rxl,S,VMU,0}, /* mov */ + {0,0,lr,VMU,S,0}, /* mov */ + {0,0,rxl,S,VML,0}, /* mov */ + {0,0,lr,VML,S,0}, /* mov */ + {0,0,rxl,S,ICR,0}, /* mov */ + {0,0,lr,ICR,S,0}, /* mov */ + {0,0,rxl,S,TCPU,0}, /* mov */ + {0,0,lr,TCPU,S,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {120,0,nops,0,0,0}, /* stop */ + {0,0,0,0,0,0}, + {0,0,rxl,S,TID,0}, /* mov */ + {0,0,lr,TID,S,0}, /* mov */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e0_format7[] = { + {84,13,r,V,0,0}, /* sum.b.f */ + {84,14,r,V,0,0}, /* sum.h.f */ + {84,15,r,V,0,0}, /* sum.w.f */ + {84,16,r,V,0,0}, /* sum.l.f */ + {85,2,r,V,0,0}, /* all.f */ + {86,2,r,V,0,0}, /* any.f */ + {87,2,r,V,0,0}, /* parity.f */ + {0,0,0,0,0,0}, + {88,13,r,V,0,0}, /* max.b.f */ + {88,14,r,V,0,0}, /* max.h.f */ + {88,15,r,V,0,0}, /* max.w.f */ + {88,16,r,V,0,0}, /* max.l.f */ + {89,13,r,V,0,0}, /* min.b.f */ + {89,14,r,V,0,0}, /* min.h.f */ + {89,15,r,V,0,0}, /* min.w.f */ + {89,16,r,V,0,0}, /* min.l.f */ + {84,11,r,V,0,0}, /* sum.s.f */ + {84,12,r,V,0,0}, /* sum.d.f */ + {90,11,r,V,0,0}, /* prod.s.f */ + {90,12,r,V,0,0}, /* prod.d.f */ + {88,11,r,V,0,0}, /* max.s.f */ + {88,12,r,V,0,0}, /* max.d.f */ + {89,11,r,V,0,0}, /* min.s.f */ + {89,12,r,V,0,0}, /* min.d.f */ + {90,13,r,V,0,0}, /* prod.b.f */ + {90,14,r,V,0,0}, /* prod.h.f */ + {90,15,r,V,0,0}, /* prod.w.f */ + {90,16,r,V,0,0}, /* prod.l.f */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format0[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {10,18,rrr,S,V,V}, /* sub.s.t */ + {10,19,rrr,S,V,V}, /* sub.d.t */ + {4,18,rrr,S,V,V}, /* div.s.t */ + {4,19,rrr,S,V,V}, /* div.d.t */ + {3,18,rrr,V,V,V}, /* mul.s.t */ + {3,19,rrr,V,V,V}, /* mul.d.t */ + {4,18,rrr,V,V,V}, /* div.s.t */ + {4,19,rrr,V,V,V}, /* div.d.t */ + {3,18,rrr,V,S,V}, /* mul.s.t */ + {3,19,rrr,V,S,V}, /* mul.d.t */ + {4,18,rrr,V,S,V}, /* div.s.t */ + {4,19,rrr,V,S,V}, /* div.d.t */ + {5,1,rrr,V,V,V}, /* and.t */ + {6,1,rrr,V,V,V}, /* or.t */ + {7,1,rrr,V,V,V}, /* xor.t */ + {8,1,rrr,V,V,V}, /* shf.t */ + {5,1,rrr,V,S,V}, /* and.t */ + {6,1,rrr,V,S,V}, /* or.t */ + {7,1,rrr,V,S,V}, /* xor.t */ + {8,1,rrr,V,S,V}, /* shf.t */ + {9,18,rrr,V,V,V}, /* add.s.t */ + {9,19,rrr,V,V,V}, /* add.d.t */ + {10,18,rrr,V,V,V}, /* sub.s.t */ + {10,19,rrr,V,V,V}, /* sub.d.t */ + {9,18,rrr,V,S,V}, /* add.s.t */ + {9,19,rrr,V,S,V}, /* add.d.t */ + {10,18,rrr,V,S,V}, /* sub.s.t */ + {10,19,rrr,V,S,V}, /* sub.d.t */ + {9,20,rrr,V,V,V}, /* add.b.t */ + {9,21,rrr,V,V,V}, /* add.h.t */ + {9,22,rrr,V,V,V}, /* add.w.t */ + {9,23,rrr,V,V,V}, /* add.l.t */ + {9,20,rrr,V,S,V}, /* add.b.t */ + {9,21,rrr,V,S,V}, /* add.h.t */ + {9,22,rrr,V,S,V}, /* add.w.t */ + {9,23,rrr,V,S,V}, /* add.l.t */ + {10,20,rrr,V,V,V}, /* sub.b.t */ + {10,21,rrr,V,V,V}, /* sub.h.t */ + {10,22,rrr,V,V,V}, /* sub.w.t */ + {10,23,rrr,V,V,V}, /* sub.l.t */ + {10,20,rrr,V,S,V}, /* sub.b.t */ + {10,21,rrr,V,S,V}, /* sub.h.t */ + {10,22,rrr,V,S,V}, /* sub.w.t */ + {10,23,rrr,V,S,V}, /* sub.l.t */ + {3,20,rrr,V,V,V}, /* mul.b.t */ + {3,21,rrr,V,V,V}, /* mul.h.t */ + {3,22,rrr,V,V,V}, /* mul.w.t */ + {3,23,rrr,V,V,V}, /* mul.l.t */ + {3,20,rrr,V,S,V}, /* mul.b.t */ + {3,21,rrr,V,S,V}, /* mul.h.t */ + {3,22,rrr,V,S,V}, /* mul.w.t */ + {3,23,rrr,V,S,V}, /* mul.l.t */ + {4,20,rrr,V,V,V}, /* div.b.t */ + {4,21,rrr,V,V,V}, /* div.h.t */ + {4,22,rrr,V,V,V}, /* div.w.t */ + {4,23,rrr,V,V,V}, /* div.l.t */ + {4,20,rrr,V,S,V}, /* div.b.t */ + {4,21,rrr,V,S,V}, /* div.h.t */ + {4,22,rrr,V,S,V}, /* div.w.t */ + {4,23,rrr,V,S,V}, /* div.l.t */ +}; + +const struct formstr e1_format1[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {26,20,a2r,S,0,0}, /* ste.b.t */ + {26,21,a2r,S,0,0}, /* ste.h.t */ + {26,22,a2r,S,0,0}, /* ste.w.t */ + {26,23,a2r,S,0,0}, /* ste.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {18,20,a1r,V,0,0}, /* ld.b.t */ + {18,21,a1r,V,0,0}, /* ld.h.t */ + {18,22,a1r,V,0,0}, /* ld.w.t */ + {18,23,a1r,V,0,0}, /* ld.l.t */ + {21,20,a2r,V,0,0}, /* st.b.t */ + {21,21,a2r,V,0,0}, /* st.h.t */ + {21,22,a2r,V,0,0}, /* st.w.t */ + {21,23,a2r,V,0,0}, /* st.l.t */ +}; + +const struct formstr e1_format2[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {28,20,rr,V,V,0}, /* cvtw.b.t */ + {28,21,rr,V,V,0}, /* cvtw.h.t */ + {29,22,rr,V,V,0}, /* cvtb.w.t */ + {30,22,rr,V,V,0}, /* cvth.w.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {31,23,rr,V,V,0}, /* cvts.l.t */ + {32,22,rr,V,V,0}, /* cvtd.w.t */ + {33,18,rr,V,V,0}, /* cvtl.s.t */ + {28,19,rr,V,V,0}, /* cvtw.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {116,18,rr,V,V,0}, /* frint.s.t */ + {116,19,rr,V,V,0}, /* frint.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {81,18,rr,V,V,0}, /* sqrt.s.t */ + {81,19,rr,V,V,0}, /* sqrt.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format3[] = { + {32,18,rr,V,V,0}, /* cvtd.s.t */ + {31,19,rr,V,V,0}, /* cvts.d.t */ + {33,19,rr,V,V,0}, /* cvtl.d.t */ + {32,23,rr,V,V,0}, /* cvtd.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {36,1,rr,V,V,0}, /* tzc.t */ + {44,1,rr,V,V,0}, /* lop.t */ + {117,1,rr,V,V,0}, /* xpnd.t */ + {42,1,rr,V,V,0}, /* not.t */ + {8,1,rr,S,V,0}, /* shf.t */ + {35,24,rr,V,V,0}, /* plc.t.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {37,18,rr,V,V,0}, /* eq.s.t */ + {37,19,rr,V,V,0}, /* eq.d.t */ + {43,18,rr,V,V,0}, /* neg.s.t */ + {43,19,rr,V,V,0}, /* neg.d.t */ + {37,18,rr,S,V,0}, /* eq.s.t */ + {37,19,rr,S,V,0}, /* eq.d.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {40,18,rr,V,V,0}, /* le.s.t */ + {40,19,rr,V,V,0}, /* le.d.t */ + {41,18,rr,V,V,0}, /* lt.s.t */ + {41,19,rr,V,V,0}, /* lt.d.t */ + {40,18,rr,S,V,0}, /* le.s.t */ + {40,19,rr,S,V,0}, /* le.d.t */ + {41,18,rr,S,V,0}, /* lt.s.t */ + {41,19,rr,S,V,0}, /* lt.d.t */ + {37,20,rr,V,V,0}, /* eq.b.t */ + {37,21,rr,V,V,0}, /* eq.h.t */ + {37,22,rr,V,V,0}, /* eq.w.t */ + {37,23,rr,V,V,0}, /* eq.l.t */ + {37,20,rr,S,V,0}, /* eq.b.t */ + {37,21,rr,S,V,0}, /* eq.h.t */ + {37,22,rr,S,V,0}, /* eq.w.t */ + {37,23,rr,S,V,0}, /* eq.l.t */ + {40,20,rr,V,V,0}, /* le.b.t */ + {40,21,rr,V,V,0}, /* le.h.t */ + {40,22,rr,V,V,0}, /* le.w.t */ + {40,23,rr,V,V,0}, /* le.l.t */ + {40,20,rr,S,V,0}, /* le.b.t */ + {40,21,rr,S,V,0}, /* le.h.t */ + {40,22,rr,S,V,0}, /* le.w.t */ + {40,23,rr,S,V,0}, /* le.l.t */ + {41,20,rr,V,V,0}, /* lt.b.t */ + {41,21,rr,V,V,0}, /* lt.h.t */ + {41,22,rr,V,V,0}, /* lt.w.t */ + {41,23,rr,V,V,0}, /* lt.l.t */ + {41,20,rr,S,V,0}, /* lt.b.t */ + {41,21,rr,S,V,0}, /* lt.h.t */ + {41,22,rr,S,V,0}, /* lt.w.t */ + {41,23,rr,S,V,0}, /* lt.l.t */ + {43,20,rr,V,V,0}, /* neg.b.t */ + {43,21,rr,V,V,0}, /* neg.h.t */ + {43,22,rr,V,V,0}, /* neg.w.t */ + {43,23,rr,V,V,0}, /* neg.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format4[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format5[] = { + {51,20,rr,V,V,0}, /* ldvi.b.t */ + {51,21,rr,V,V,0}, /* ldvi.h.t */ + {51,22,rr,V,V,0}, /* ldvi.w.t */ + {51,23,rr,V,V,0}, /* ldvi.l.t */ + {28,18,rr,V,V,0}, /* cvtw.s.t */ + {31,22,rr,V,V,0}, /* cvts.w.t */ + {28,23,rr,V,V,0}, /* cvtw.l.t */ + {33,22,rr,V,V,0}, /* cvtl.w.t */ + {52,20,rxr,V,V,0}, /* stvi.b.t */ + {52,21,rxr,V,V,0}, /* stvi.h.t */ + {52,22,rxr,V,V,0}, /* stvi.w.t */ + {52,23,rxr,V,V,0}, /* stvi.l.t */ + {52,20,rxr,S,V,0}, /* stvi.b.t */ + {52,21,rxr,S,V,0}, /* stvi.h.t */ + {52,22,rxr,S,V,0}, /* stvi.w.t */ + {52,23,rxr,S,V,0}, /* stvi.l.t */ +}; + +const struct formstr e1_format6[] = { + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +const struct formstr e1_format7[] = { + {84,20,r,V,0,0}, /* sum.b.t */ + {84,21,r,V,0,0}, /* sum.h.t */ + {84,22,r,V,0,0}, /* sum.w.t */ + {84,23,r,V,0,0}, /* sum.l.t */ + {85,1,r,V,0,0}, /* all.t */ + {86,1,r,V,0,0}, /* any.t */ + {87,1,r,V,0,0}, /* parity.t */ + {0,0,0,0,0,0}, + {88,20,r,V,0,0}, /* max.b.t */ + {88,21,r,V,0,0}, /* max.h.t */ + {88,22,r,V,0,0}, /* max.w.t */ + {88,23,r,V,0,0}, /* max.l.t */ + {89,20,r,V,0,0}, /* min.b.t */ + {89,21,r,V,0,0}, /* min.h.t */ + {89,22,r,V,0,0}, /* min.w.t */ + {89,23,r,V,0,0}, /* min.l.t */ + {84,18,r,V,0,0}, /* sum.s.t */ + {84,19,r,V,0,0}, /* sum.d.t */ + {90,18,r,V,0,0}, /* prod.s.t */ + {90,19,r,V,0,0}, /* prod.d.t */ + {88,18,r,V,0,0}, /* max.s.t */ + {88,19,r,V,0,0}, /* max.d.t */ + {89,18,r,V,0,0}, /* min.s.t */ + {89,19,r,V,0,0}, /* min.d.t */ + {90,20,r,V,0,0}, /* prod.b.t */ + {90,21,r,V,0,0}, /* prod.h.t */ + {90,22,r,V,0,0}, /* prod.w.t */ + {90,23,r,V,0,0}, /* prod.l.t */ + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, + {0,0,0,0,0,0}, +}; + +char *lop[] = { + "mov", /* 0 */ + "merg", /* 1 */ + "mask", /* 2 */ + "mul", /* 3 */ + "div", /* 4 */ + "and", /* 5 */ + "or", /* 6 */ + "xor", /* 7 */ + "shf", /* 8 */ + "add", /* 9 */ + "sub", /* 10 */ + "exit", /* 11 */ + "jmp", /* 12 */ + "jmpi", /* 13 */ + "jmpa", /* 14 */ + "jmps", /* 15 */ + "tac", /* 16 */ + "ldea", /* 17 */ + "ld", /* 18 */ + "tas", /* 19 */ + "pshea", /* 20 */ + "st", /* 21 */ + "call", /* 22 */ + "calls", /* 23 */ + "callq", /* 24 */ + "pfork", /* 25 */ + "ste", /* 26 */ + "incr", /* 27 */ + "cvtw", /* 28 */ + "cvtb", /* 29 */ + "cvth", /* 30 */ + "cvts", /* 31 */ + "cvtd", /* 32 */ + "cvtl", /* 33 */ + "ldpa", /* 34 */ + "plc", /* 35 */ + "tzc", /* 36 */ + "eq", /* 37 */ + "leu", /* 38 */ + "ltu", /* 39 */ + "le", /* 40 */ + "lt", /* 41 */ + "not", /* 42 */ + "neg", /* 43 */ + "lop", /* 44 */ + "cprs", /* 45 */ + "nop", /* 46 */ + "br", /* 47 */ + "bri", /* 48 */ + "bra", /* 49 */ + "brs", /* 50 */ + "ldvi", /* 51 */ + "stvi", /* 52 */ + "ldsdr", /* 53 */ + "ldkdr", /* 54 */ + "ln", /* 55 */ + "patu", /* 56 */ + "pate", /* 57 */ + "pich", /* 58 */ + "plch", /* 59 */ + "idle", /* 60 */ + "rtnq", /* 61 */ + "cfork", /* 62 */ + "rtn", /* 63 */ + "wfork", /* 64 */ + "join", /* 65 */ + "rtnc", /* 66 */ + "exp", /* 67 */ + "sin", /* 68 */ + "cos", /* 69 */ + "psh", /* 70 */ + "pop", /* 71 */ + "eni", /* 72 */ + "dsi", /* 73 */ + "bkpt", /* 74 */ + "msync", /* 75 */ + "mski", /* 76 */ + "xmti", /* 77 */ + "tstvv", /* 78 */ + "diag", /* 79 */ + "pbkpt", /* 80 */ + "sqrt", /* 81 */ + "casr", /* 82 */ + "atan", /* 83 */ + "sum", /* 84 */ + "all", /* 85 */ + "any", /* 86 */ + "parity", /* 87 */ + "max", /* 88 */ + "min", /* 89 */ + "prod", /* 90 */ + "halt", /* 91 */ + "sysc", /* 92 */ + "trap", /* 93 */ + "tst", /* 94 */ + "lck", /* 95 */ + "ulk", /* 96 */ + "spawn", /* 97 */ + "ldcmr", /* 98 */ + "stcmr", /* 99 */ + "popr", /* 100 */ + "pshr", /* 101 */ + "rcvr", /* 102 */ + "matm", /* 103 */ + "sndr", /* 104 */ + "putr", /* 105 */ + "getr", /* 106 */ + "matr", /* 107 */ + "mat", /* 108 */ + "get", /* 109 */ + "rcv", /* 110 */ + "inc", /* 111 */ + "put", /* 112 */ + "snd", /* 113 */ + "enal", /* 114 */ + "enag", /* 115 */ + "frint", /* 116 */ + "xpnd", /* 117 */ + "ctrsl", /* 118 */ + "ctrsg", /* 119 */ + "stop", /* 120 */ +}; + +char *rop[] = { + "", /* 0 */ + ".t", /* 1 */ + ".f", /* 2 */ + ".s", /* 3 */ + ".d", /* 4 */ + ".b", /* 5 */ + ".h", /* 6 */ + ".w", /* 7 */ + ".l", /* 8 */ + ".x", /* 9 */ + ".u", /* 10 */ + ".s.f", /* 11 */ + ".d.f", /* 12 */ + ".b.f", /* 13 */ + ".h.f", /* 14 */ + ".w.f", /* 15 */ + ".l.f", /* 16 */ + ".t.f", /* 17 */ + ".s.t", /* 18 */ + ".d.t", /* 19 */ + ".b.t", /* 20 */ + ".h.t", /* 21 */ + ".w.t", /* 22 */ + ".l.t", /* 23 */ + ".t.t", /* 24 */ +}; diff --git a/external/gpl3/gdb/dist/include/opcode/cr16.h b/external/gpl3/gdb/dist/include/opcode/cr16.h new file mode 100644 index 000000000000..2d322882e4c7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/cr16.h @@ -0,0 +1,438 @@ +/* cr16.h -- Header file for CR16 opcode and register tables. + Copyright 2007, 2008, 2010 Free Software Foundation, Inc. + Contributed by M R Swami Reddy + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _CR16_H_ +#define _CR16_H_ + +/* CR16 core Registers : + The enums are used as indices to CR16 registers table (cr16_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 16-bit general purpose registers. */ + r0, r1, r2, r3, + r4, r5, r6, r7, + r8, r9, r10, r11, + r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, + + /* 32-bit general purpose registers. */ + r12 = 12, r13 = 13, r14 = 14, r15 = 15, + era = 14, sp = 15, RA, + + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CR16 processor registers and special registers : + The enums are used as indices to CR16 processor registers table + (cr16_pregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* processor registers. */ + dbs = MAX_REG, + dsr, dcrl, dcrh, + car0l, car0h, car1l, car1h, + cfg, psr, intbasel, intbaseh, + ispl, isph, uspl, usph, + dcr = dcrl, + car0 = car0l, + car1 = car1l, + intbase = intbasel, + isp = ispl, + usp = uspl, + /* Not a processor register. */ + nullpregister = usph + 1, + MAX_PREG + } +preg; + +/* CR16 Register types. */ + +typedef enum + { + CR16_R_REGTYPE, /* r */ + CR16_RP_REGTYPE, /* reg pair */ + CR16_P_REGTYPE /* Processor register */ + } +reg_type; + +/* CR16 argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + rp - register pair + c - constant + i - immediate + idxr - index with register + idxrp - index with register pair + rbase - register base + rpbase - register pair base + pr - processor register */ + +typedef enum + { + arg_r, + arg_c, + arg_cr, + arg_crp, + arg_ic, + arg_icr, + arg_idxr, + arg_idxrp, + arg_rbase, + arg_rpbase, + arg_rp, + arg_pr, + arg_prp, + arg_cc, + arg_ra, + /* Not an argument. */ + nullargs + } +argtype; + +/* CR16 operand types:The operand types correspond to instructions operands.*/ + +typedef enum + { + dummy, + /* N-bit signed immediate. */ + imm3, imm4, imm5, imm6, imm16, imm20, imm32, + /* N-bit unsigned immediate. */ + uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, + /* N-bit signed displacement. */ + disps5, disps17, disps25, + /* N-bit unsigned displacement. */ + dispe9, + /* N-bit absolute address. */ + abs20, abs24, + /* Register relative. */ + rra, rbase, rbase_disps20, rbase_dispe20, + /* Register pair relative. */ + rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, + rpbase_disps20, rpbase_dispe20, + /* Register index. */ + rindex7_abs20, rindex8_abs20, + /* Register pair index. */ + rpindex_disps0, rpindex_disps14, rpindex_disps20, + /* register. */ + regr, + /* register pair. */ + regp, + /* processor register. */ + pregr, + /* processor register 32 bit. */ + pregrp, + /* condition code - 4 bit. */ + cc, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CR16 instruction types. */ + +#define NO_TYPE_INS 0 +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define SHIFT_INS 5 +#define BRANCH_NEQ_INS 6 +#define LD_STOR_INS_INC 7 +#define STOR_IMM_INS 8 +#define CSTBIT_INS 9 + +/* Maximum value supported for instruction types. */ +#define CR16_INS_MAX (1 << 4) +/* Mask to record an instruction type. */ +#define CR16_INS_MASK (CR16_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CR16_INS_MAX + +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (1 << 5) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (1 << 9) /* 0xF0F00000 */ +#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 11) /* 0xFFF00F00 */ +#define FMT_4 (1 << 12) /* 0xFFF0F000 */ +#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ +#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 14) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 15) + + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 17) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 18) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OP_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OP_SIGNED (1 << 1) +/* Operand must be a negative number. */ +#define OP_NEG (1 << 2) +/* A special load/stor 4-bit unsigned displacement operand. */ +#define OP_DEC (1 << 3) +/* Operand must be an even number. */ +#define OP_EVEN (1 << 4) +/* Operand is shifted right. */ +#define OP_SHIFT (1 << 5) +/* Operand is shifted right and decremented. */ +#define OP_SHIFT_DEC (1 << 6) +/* Operand has reserved escape sequences. */ +#define OP_ESC (1 << 7) +/* Operand must be a ABS20 number. */ +#define OP_ABS20 (1 << 8) +/* Operand must be a ABS24 number. */ +#define OP_ABS24 (1 << 9) +/* Operand has reserved escape sequences type 1. */ +#define OP_ESC1 (1 << 10) + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; /* ie opcode */ + /* Match size (in bits). */ + /* MASK: if( (i & match_bits) == match ) then match */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Register pair register. */ + reg rp; + /* Index register. */ + reg i_r; + /* Processor register. */ + preg pr; + /* Processor register. 32 bit */ + preg prp; + /* Constant/immediate/absolute value. */ + long constant; + /* CC code. */ + unsigned int cc; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* The type of the expression. */ + unsigned char X_op; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CR16-assembler. */ +#ifdef TC_CR16 + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CR16 */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + /* One bit syntax flags. */ + int flags; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* processor register. */ + preg preg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* CR16 opcode table. */ +extern const inst cr16_instruction[]; +extern const unsigned int cr16_num_opcodes; +#define NUMOPCODES cr16_num_opcodes + +/* CR16 operands table. */ +extern const operand_entry cr16_optab[]; +extern const unsigned int cr16_num_optab; + +/* CR16 registers table. */ +extern const reg_entry cr16_regtab[]; +extern const unsigned int cr16_num_regs; +#define NUMREGS cr16_num_regs + +/* CR16 register pair table. */ +extern const reg_entry cr16_regptab[]; +extern const unsigned int cr16_num_regps; +#define NUMREGPS cr16_num_regps + +/* CR16 processor registers table. */ +extern const reg_entry cr16_pregtab[]; +extern const unsigned int cr16_num_pregs; +#define NUMPREGS cr16_num_pregs + +/* CR16 processor registers - 32 bit table. */ +extern const reg_entry cr16_pregptab[]; +extern const unsigned int cr16_num_pregps; +#define NUMPREGPS cr16_num_pregps + +/* CR16 trap/interrupt table. */ +extern const trap_entry cr16_traps[]; +extern const unsigned int cr16_num_traps; +#define NUMTRAPS cr16_num_traps + +/* CR16 CC - codes bit table. */ +extern const char * cr16_b_cond_tab[]; +extern const unsigned int cr16_num_cc; +#define NUMCC cr16_num_cc; + + +/* Table of instructions with no operands. */ +extern const char * cr16_no_op_insn[]; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CR16_INS_TYPE (instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp (instruction->mnemonic, MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + + +/* Utility macros for string comparison. */ +#define streq(a, b) (strcmp (a, b) == 0) +#define strneq(a, b, c) (strncmp (a, b, c) == 0) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; + +#endif /* _CR16_H_ */ diff --git a/external/gpl3/gdb/dist/include/opcode/cris.h b/external/gpl3/gdb/dist/include/opcode/cris.h new file mode 100644 index 000000000000..e57a8825c0cc --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/cris.h @@ -0,0 +1,367 @@ +/* cris.h -- Header file for CRIS opcode and register tables. + Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Updated, BFDized and GNUified by Hans-Peter Nilsson. + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef __CRIS_H_INCLUDED_ +#define __CRIS_H_INCLUDED_ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + + +/* Registers. */ +#define MAX_REG (15) +#define REG_SP (14) +#define REG_PC (15) + +/* CPU version control of disassembly and assembly of instructions. + May affect how the instruction is assembled, at least the size of + immediate operands. */ +enum cris_insn_version_usage +{ + /* Any version. */ + cris_ver_version_all=0, + + /* Indeterminate (intended for disassembly only, or obsolete). */ + cris_ver_warning, + + /* Only for v0..3 (Etrax 1..4). */ + cris_ver_v0_3, + + /* Only for v3 or higher (ETRAX 4 and beyond). */ + cris_ver_v3p, + + /* Only for v8 (Etrax 100). */ + cris_ver_v8, + + /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ + cris_ver_v8p, + + /* Only for v0..10. FIXME: Not sure what to do with this. */ + cris_ver_sim_v0_10, + + /* Only for v0..10. */ + cris_ver_v0_10, + + /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ + cris_ver_v3_10, + + /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ + cris_ver_v8_10, + + /* Only for v10 (ETRAX 100 LX) and same series. */ + cris_ver_v10, + + /* Only for v10 (ETRAX 100 LX) and same series. */ + cris_ver_v10p, + + /* Only for v32 or higher (codename GUINNESS). + Of course some or all these of may change to cris_ver_v32p if/when + there's a new revision. */ + cris_ver_v32p +}; + + +/* Special registers. */ +struct cris_spec_reg +{ + const char *const name; + unsigned int number; + + /* The size of the register. */ + unsigned int reg_size; + + /* What CPU version the special register of that name is implemented + in. If cris_ver_warning, emit an unimplemented-warning. */ + enum cris_insn_version_usage applicable_version; + + /* There might be a specific warning for using a special register + here. */ + const char *const warning; +}; +extern const struct cris_spec_reg cris_spec_regs[]; + + +/* Support registers (kind of special too, but not named as such). */ +struct cris_support_reg +{ + const char *const name; + unsigned int number; +}; +extern const struct cris_support_reg cris_support_regs[]; + +struct cris_cond15 +{ + /* The name of the condition. */ + const char *const name; + + /* What CPU version this condition name applies to. */ + enum cris_insn_version_usage applicable_version; +}; +extern const struct cris_cond15 cris_conds15[]; + +/* Opcode-dependent constants. */ +#define AUTOINCR_BIT (0x04) + +/* Prefixes. */ +#define BDAP_QUICK_OPCODE (0x0100) +#define BDAP_QUICK_Z_BITS (0x0e00) + +#define BIAP_OPCODE (0x0540) +#define BIAP_Z_BITS (0x0a80) + +#define DIP_OPCODE (0x0970) +#define DIP_Z_BITS (0xf280) + +#define BDAP_INDIR_LOW (0x40) +#define BDAP_INDIR_LOW_Z (0x80) +#define BDAP_INDIR_HIGH (0x09) +#define BDAP_INDIR_HIGH_Z (0x02) + +#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) +#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) +#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) +#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) + +/* No prefix must have this code for its "match" bits in the + opcode-table. "BCC .+2" will do nicely. */ +#define NO_CRIS_PREFIX 0 + +/* Definitions for condition codes. */ +#define CC_CC 0x0 +#define CC_HS 0x0 +#define CC_CS 0x1 +#define CC_LO 0x1 +#define CC_NE 0x2 +#define CC_EQ 0x3 +#define CC_VC 0x4 +#define CC_VS 0x5 +#define CC_PL 0x6 +#define CC_MI 0x7 +#define CC_LS 0x8 +#define CC_HI 0x9 +#define CC_GE 0xA +#define CC_LT 0xB +#define CC_GT 0xC +#define CC_LE 0xD +#define CC_A 0xE +#define CC_EXT 0xF + +/* A table of strings "cc", "cs"... indexed with condition code + values as above. */ +extern const char *const cris_cc_strings[]; + +/* Bcc quick. */ +#define BRANCH_QUICK_LOW (0) +#define BRANCH_QUICK_HIGH (0) +#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) +#define BRANCH_QUICK_Z_BITS (0x0F00) + +/* BA quick. */ +#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) +#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) + +/* Bcc [PC+]. */ +#define BRANCH_PC_LOW (0xFF) +#define BRANCH_INCR_HIGH (0x0D) +#define BA_PC_INCR_OPCODE \ + ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) + +/* Jump. */ +/* Note that old versions generated special register 8 (in high bits) + and not-that-old versions recognized it as a jump-instruction. + That opcode now belongs to JUMPU. */ +#define JUMP_INDIR_OPCODE (0x0930) +#define JUMP_INDIR_Z_BITS (0xf2c0) +#define JUMP_PC_INCR_OPCODE \ + (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) + +#define MOVE_M_TO_PREG_OPCODE 0x0a30 +#define MOVE_M_TO_PREG_ZBITS 0x01c0 + +/* BDAP.D N,PC. */ +#define MOVE_PC_INCR_OPCODE_PREFIX \ + (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4)) +#define MOVE_PC_INCR_OPCODE_SUFFIX \ + (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8)) + +#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) + +/* BA DWORD (V32). */ +#define BA_DWORD_OPCODE (0x0EBF) + +/* Nop. */ +#define NOP_OPCODE (0x050F) +#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) + +#define NOP_OPCODE_V32 (0x05B0) +#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) + +/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect + registers or flags. Unfortunately shuts off interrupts for one cycle + for < v32, but there doesn't seem to be any alternative without that + effect. */ +#define NOP_OPCODE_COMMON (0x630) +#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) + +/* LAPC.D */ +#define LAPC_DWORD_OPCODE (0x0D7F) +#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) + +/* Structure of an opcode table entry. */ +enum cris_imm_oprnd_size_type +{ + /* No size is applicable. */ + SIZE_NONE, + + /* Always 32 bits. */ + SIZE_FIX_32, + + /* Indicated by size of special register. */ + SIZE_SPEC_REG, + + /* Indicated by size field, signed. */ + SIZE_FIELD_SIGNED, + + /* Indicated by size field, unsigned. */ + SIZE_FIELD_UNSIGNED, + + /* Indicated by size field, no sign implied. */ + SIZE_FIELD +}; + +/* For GDB. FIXME: Is this the best way to handle opcode + interpretation? */ +enum cris_op_type +{ + cris_not_implemented_op = 0, + cris_abs_op, + cris_addi_op, + cris_asr_op, + cris_asrq_op, + cris_ax_ei_setf_op, + cris_bdap_prefix, + cris_biap_prefix, + cris_break_op, + cris_btst_nop_op, + cris_clearf_di_op, + cris_dip_prefix, + cris_dstep_logshift_mstep_neg_not_op, + cris_eight_bit_offset_branch_op, + cris_move_mem_to_reg_movem_op, + cris_move_reg_to_mem_movem_op, + cris_move_to_preg_op, + cris_muls_op, + cris_mulu_op, + cris_none_reg_mode_add_sub_cmp_and_or_move_op, + cris_none_reg_mode_clear_test_op, + cris_none_reg_mode_jump_op, + cris_none_reg_mode_move_from_preg_op, + cris_quick_mode_add_sub_op, + cris_quick_mode_and_cmp_move_or_op, + cris_quick_mode_bdap_prefix, + cris_reg_mode_add_sub_cmp_and_or_move_op, + cris_reg_mode_clear_op, + cris_reg_mode_jump_op, + cris_reg_mode_move_from_preg_op, + cris_reg_mode_test_op, + cris_scc_op, + cris_sixteen_bit_offset_branch_op, + cris_three_operand_add_sub_cmp_and_or_op, + cris_three_operand_bound_op, + cris_two_operand_bound_op, + cris_xor_op +}; + +struct cris_opcode +{ + /* The name of the insn. */ + const char *name; + + /* Bits that must be 1 for a match. */ + unsigned int match; + + /* Bits that must be 0 for a match. */ + unsigned int lose; + + /* See the table in "opcodes/cris-opc.c". */ + const char *args; + + /* Nonzero if this is a delayed branch instruction. */ + char delayed; + + /* Size of immediate operands. */ + enum cris_imm_oprnd_size_type imm_oprnd_size; + + /* Indicates which version this insn was first implemented in. */ + enum cris_insn_version_usage applicable_version; + + /* What kind of operation this is. */ + enum cris_op_type op; +}; +extern const struct cris_opcode cris_opcodes[]; + + +/* These macros are for the target-specific flags in disassemble_info + used at disassembly. */ + +/* This insn accesses memory. This flag is more trustworthy than + checking insn_type for "dis_dref" which does not work for + e.g. "JSR [foo]". */ +#define CRIS_DIS_FLAG_MEMREF (1 << 0) + +/* The "target" field holds a register number. */ +#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) + +/* The "target2" field holds a register number; add it to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) + +/* Yet another add-on: the register in "target2" must be multiplied + by 2 before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) + +/* Yet another add-on: the register in "target2" must be multiplied + by 4 (mutually exclusive with .._MULT2). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) + +/* The register in "target2" is an indirect memory reference (of the + register there), add to "target". Assumed size is dword (mutually + exclusive with .._MULT[24]). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) + +#endif /* __CRIS_H_INCLUDED_ */ + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/external/gpl3/gdb/dist/include/opcode/crx.h b/external/gpl3/gdb/dist/include/opcode/crx.h new file mode 100644 index 000000000000..5c484bf26bca --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/crx.h @@ -0,0 +1,419 @@ +/* crx.h -- Header file for CRX opcode and register tables. + Copyright 2004, 2010 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. + Updates, BFDizing, GNUifying and ELF support by Tomer Levi. + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _CRX_H_ +#define _CRX_H_ + +/* CRX core/debug Registers : + The enums are used as indices to CRX registers table (crx_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 32-bit general purpose registers. */ + r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, + r10, r11, r12, r13, r14, r15, ra, sp, + /* 32-bit user registers. */ + u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, + u10, u11, u12, u13, u14, u15, ura, usp, + /* hi and lo registers. */ + hi, lo, + /* hi and lo user registers. */ + uhi, ulo, + /* Processor Status Register. */ + psr, + /* Interrupt Base Register. */ + intbase, + /* Interrupt Stack Pointer Register. */ + isp, + /* Configuration Register. */ + cfg, + /* Coprocessor Configuration Register. */ + cpcfg, + /* Coprocessor Enable Register. */ + cen, + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CRX Coprocessor registers and special registers : + The enums are used as indices to CRX coprocessor registers table + (crx_copregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* Coprocessor registers. */ + c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, + c9, c10, c11, c12, c13, c14, c15, + /* Coprocessor special registers. */ + cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, + cs9, cs10, cs11, cs12, cs13, cs14, cs15, + /* Not a Coprocessor register. */ + nullcopregister, + MAX_COPREG + } +copreg; + +/* CRX Register types. */ + +typedef enum + { + CRX_R_REGTYPE, /* r */ + CRX_U_REGTYPE, /* u */ + CRX_C_REGTYPE, /* c */ + CRX_CS_REGTYPE, /* cs */ + CRX_CFG_REGTYPE /* configuration register */ + } +reg_type; + +/* CRX argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + c - constant + i - immediate + idxr - index register + rbase - register base + s - star ('*') + copr - coprocessor register + copsr - coprocessor special register. */ + +typedef enum + { + arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, + arg_idxr, arg_rbase, arg_copr, arg_copsr, + /* Not an argument. */ + nullargs + } +argtype; + +/* CRX operand types : + The operand types correspond to instructions operands. */ + +typedef enum + { + dummy, + /* 4-bit encoded constant. */ + cst4, + /* N-bit immediate. */ + i16, i32, + /* N-bit unsigned immediate. */ + ui3, ui4, ui5, ui16, + /* N-bit signed displacement. */ + disps9, disps17, disps25, disps32, + /* N-bit unsigned displacement. */ + dispu5, + /* N-bit escaped displacement. */ + dispe9, + /* N-bit absolute address. */ + abs16, abs32, + /* Register relative. */ + rbase, rbase_dispu4, + rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, + /* Register index. */ + rindex_disps6, rindex_disps22, + /* 4-bit genaral-purpose register specifier. */ + regr, + /* 8-bit register address space. */ + regr8, + /* coprocessor register. */ + copregr, + /* coprocessor special register. */ + copsregr, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CRX instruction types. */ + +#define NO_TYPE_INS 0 +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define CMPBR_INS 5 +#define SHIFT_INS 6 +#define BRANCH_NEQ_INS 7 +#define LD_STOR_INS_INC 8 +#define STOR_IMM_INS 9 +#define CSTBIT_INS 10 +#define COP_BRANCH_INS 11 +#define COP_REG_INS 12 +#define COPS_REG_INS 13 +#define DCR_BRANCH_INS 14 + +/* Maximum value supported for instruction types. */ +#define CRX_INS_MAX (1 << 4) +/* Mask to record an instruction type. */ +#define CRX_INS_MASK (CRX_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CRX_INS_MAX +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (1 << 5) + +/* Kind of displacement map used DISPU[BWD]4. */ +#define DISPUB4 (1 << 6) +#define DISPUW4 (1 << 7) +#define DISPUD4 (1 << 8) +#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (1 << 9) /* 0xF0F00000 */ +#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 11) /* 0xFFF00F00 */ +#define FMT_4 (1 << 12) /* 0xFFF0F000 */ +#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ +#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 14) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 15) + +/* Indicates that instruction can perfom a cst4 mapping. */ +#define CST4MAP (1 << 16) + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 17) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 18) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OP_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OP_SIGNED (1 << 1) +/* A special arithmetic 4-bit constant operand. */ +#define OP_CST4 (1 << 2) +/* A special load/stor 4-bit unsigned displacement operand. */ +#define OP_DISPU4 (1 << 3) +/* Operand must be an even number. */ +#define OP_EVEN (1 << 4) +/* Operand is shifted right. */ +#define OP_SHIFT (1 << 5) +/* Operand is shifted right and decremented. */ +#define OP_SHIFT_DEC (1 << 6) +/* Operand has reserved escape sequences. */ +#define OP_ESC (1 << 7) +/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ +#define OP_UPPER_64KB (1 << 8) + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; + /* Match size (in bits). */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Index register. */ + reg i_r; + /* Coprocessor register. */ + copreg cr; + /* Constant/immediate/absolute value. */ + long constant; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* The type of the expression. */ + unsigned char X_op; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CRX-assembler. */ +#ifdef TC_CRX + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CRX */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + /* One bit syntax flags. */ + int flags; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* Coprocessor register. */ + copreg copreg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* Structure to hold a cst4 operand mapping. */ + +/* CRX opcode table. */ +extern const inst crx_instruction[]; +extern const int crx_num_opcodes; +#define NUMOPCODES crx_num_opcodes + +/* CRX operands table. */ +extern const operand_entry crx_optab[]; + +/* CRX registers table. */ +extern const reg_entry crx_regtab[]; +extern const int crx_num_regs; +#define NUMREGS crx_num_regs + +/* CRX coprocessor registers table. */ +extern const reg_entry crx_copregtab[]; +extern const int crx_num_copregs; +#define NUMCOPREGS crx_num_copregs + +/* CRX trap/interrupt table. */ +extern const trap_entry crx_traps[]; +extern const int crx_num_traps; +#define NUMTRAPS crx_num_traps + +/* cst4 operand mapping. */ +extern const long cst4_map[]; +extern const int cst4_maps; + +/* Table of instructions with no operands. */ +extern const char* no_op_insn[]; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CRX_INS_TYPE(instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp(instruction->mnemonic,MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; + +#endif /* _CRX_H_ */ diff --git a/external/gpl3/gdb/dist/include/opcode/d10v.h b/external/gpl3/gdb/dist/include/opcode/d10v.h new file mode 100644 index 000000000000..d0e115fab202 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/d10v.h @@ -0,0 +1,209 @@ +/* d10v.h -- Header file for D10V opcode table + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010 + Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef D10V_H +#define D10V_H + +/* Format Specifier */ +#define FM00 0 +#define FM01 0x40000000 +#define FM10 0x80000000 +#define FM11 0xC0000000 + +#define NOP 0x5e00 +#define OPCODE_DIVS 0x14002800 + +/* The opcode table is an array of struct d10v_opcode. */ + +struct d10v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode format */ + int format; + + /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ +#define SHORT_OPCODE 1 +#define LONG_OPCODE 8 +#define SHORT_2 1 /* short with 2 operands */ +#define SHORT_B 3 /* short with 8-bit branch */ +#define LONG_B 8 /* long with 16-bit branch */ +#define LONG_L 10 /* long with 3 operands */ +#define LONG_R 12 /* reserved */ + + /* just a placeholder for variable-length instructions */ + /* for example, "bra" will be a fake for "bra.s" and bra.l" */ + /* which will immediately follow in the opcode table. */ +#define OPCODE_FAKE 32 + + /* the number of cycles */ + int cycles; + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define BOTH 3 + + /* execution type; parallel or sequential */ + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + int exec_type; +#define PARONLY 1 /* parallel only */ +#define SEQ 2 /* must be sequential */ +#define PAR 4 /* may be parallel */ +#define BRANCH_LINK 8 /* subroutine call. must be aligned */ +#define RMEM 16 /* reads memory */ +#define WMEM 32 /* writes memory */ +#define RF0 64 /* reads f0 */ +#define WF0 128 /* modifies f0 */ +#define WCAR 256 /* write Carry */ +#define BRANCH 512 /* branch, no link */ +#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ + + /* the opcode */ + long opcode; + + /* mask. if( (i & mask) == opcode ) then match */ + long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct d10v_opcode d10v_opcodes[]; +extern const int d10v_num_opcodes; + +/* The operands table is an array of struct d10v_operand. */ +struct d10v_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the d10v_opcodes table. */ + +extern const struct d10v_operand d10v_operands[]; + +/* Values defined for the flags field of a struct d10v_operand. */ + +/* the operand must be an even number */ +#define OPERAND_EVEN (1) + +/* the operand must be an odd number */ +#define OPERAND_ODD (2) + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (4) + +/* number or symbol */ +#define OPERAND_NUM (8) + +/* address or label */ +#define OPERAND_ADDR (0x10) + +/* register */ +#define OPERAND_REG (0x20) + +/* postincrement + */ +#define OPERAND_PLUS (0x40) + +/* postdecrement - */ +#define OPERAND_MINUS (0x80) + +/* @ */ +#define OPERAND_ATSIGN (0x100) + +/* @( */ +#define OPERAND_ATPAR (0x200) + +/* accumulator 0 */ +#define OPERAND_ACC0 (0x400) + +/* accumulator 1 */ +#define OPERAND_ACC1 (0x800) + +/* f0 / f1 flag register */ +#define OPERAND_FFLAG (0x1000) + +/* c flag register */ +#define OPERAND_CFLAG (0x2000) + +/* control register */ +#define OPERAND_CONTROL (0x4000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x8000) + +/* signed number */ +#define OPERAND_SIGNED (0x10000) + +/* special accumulator shifts need a 4-bit number */ +/* 1 <= x <= 16 */ +#define OPERAND_SHIFT (0x20000) + +/* general purpose register */ +#define OPERAND_GPR (0x40000) + +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) + +/* Pre-decrement is only supported for SP. */ +#define OPERAND_SP (0x100000) + +/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and + unlike OPERAND_SP, this flag doesn't prevent the instruction from + matching, it only fails validation later on. */ +#define OPERAND_NOSP (0x200000) + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg d10v_predefined_registers[]; +int d10v_reg_name_cnt (void); + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D10V_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/d30v.h b/external/gpl3/gdb/dist/include/opcode/d30v.h new file mode 100644 index 000000000000..62c041da967b --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/d30v.h @@ -0,0 +1,288 @@ +/* d30v.h -- Header file for D30V opcode table + Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010 + Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef D30V_H +#define D30V_H + +#define NOP 0x00F00000 + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg pre_defined_registers[]; +int reg_name_cnt (void); + +/* the number of control registers */ +#define MAX_CONTROL_REG 64 + +/* define the format specifiers */ +#define FM00 0 +#define FM01 0x80000000 +#define FM10 0x8000000000000000LL +#define FM11 0x8000000080000000LL + +/* define the opcode classes */ +#define BRA 0 +#define LOGIC 1 +#define IMEM 2 +#define IALU1 4 +#define IALU2 5 + +/* define the execution condition codes */ +#define ECC_AL 0 /* ALways (default) */ +#define ECC_TX 1 /* F0=True, F1=Don't care */ +#define ECC_FX 2 /* F0=False, F1=Don't care */ +#define ECC_XT 3 /* F0=Don't care, F1=True */ +#define ECC_XF 4 /* F0=Don't care, F1=False */ +#define ECC_TT 5 /* F0=True, F1=True */ +#define ECC_TF 6 /* F0=True, F1=False */ +#define ECC_RESERVED 7 /* reserved */ +#define ECC_MAX ECC_RESERVED + +extern const char *d30v_ecc_names[]; + +/* condition code table for CMP and CMPU */ +extern const char *d30v_cc_names[]; + +/* The opcode table is an array of struct d30v_opcode. */ +struct d30v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode */ + int op1; /* first part, "IALU1" for example */ + int op2; /* the rest of the opcode */ + + /* opcode format(s). These numbers correspond to entries */ + /* in the d30v_format_table */ + unsigned char format[4]; + +#define SHORT_M 1 +#define SHORT_M2 5 /* for ld2w and st2w */ +#define SHORT_A 9 +#define SHORT_B1 11 +#define SHORT_B2 12 +#define SHORT_B2r 13 +#define SHORT_B3 14 +#define SHORT_B3r 16 +#define SHORT_B3b 18 +#define SHORT_B3br 20 +#define SHORT_D1r 22 +#define SHORT_D2 24 +#define SHORT_D2r 26 +#define SHORT_D2Br 28 +#define SHORT_U 30 /* unary SHORT_A. ABS for example */ +#define SHORT_F 31 /* SHORT_A with flag registers */ +#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 35 /* for trap instruction */ +#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 38 /* special form for CMPcc */ +#define SHORT_CMPU 40 /* special form for CMPUcc */ +#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 48 +#define SHORT_MODDEC 49 +#define SHORT_C1 50 +#define SHORT_C2 51 +#define SHORT_UF 52 +#define SHORT_A2 53 +#define SHORT_NONE 55 /* no operands */ +#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ +#define LONG 57 +#define LONG_U 58 /* unary LONG */ +#define LONG_Ur 59 /* LONG pc-relative */ +#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ +#define LONG_M 61 /* Memory long for ldb, stb */ +#define LONG_M2 62 /* Memory long for ld2w, st2w */ +#define LONG_2 63 /* LONG with 2 operands; jmptnz */ +#define LONG_2r 64 /* LONG with 2 operands; bratnz */ +#define LONG_2b 65 /* LONG_2 with modifier of 3 */ +#define LONG_2br 66 /* LONG_2r with modifier of 3 */ +#define LONG_D 67 /* for DJMPI */ +#define LONG_Dr 68 /* for DBRAI */ +#define LONG_Dbr 69 /* for repeati */ + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define EITHER_BUT_PREFER_MU 3 + + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + long flags_used; + long flags_set; +#define FLAG_0 (1L<<0) +#define FLAG_1 (1L<<1) +#define FLAG_2 (1L<<2) +#define FLAG_3 (1L<<3) +#define FLAG_4 (1L<<4) /* S (saturation) */ +#define FLAG_5 (1L<<5) /* V (overflow) */ +#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ +#define FLAG_7 (1L<<7) /* C (carry/borrow) */ +#define FLAG_SM (1L<<8) /* SM (stack mode) */ +#define FLAG_RP (1L<<9) /* RP (repeat enable) */ +#define FLAG_CONTROL (1L<<10) /* control registers */ +#define FLAG_A0 (1L<<11) /* A0 */ +#define FLAG_A1 (1L<<12) /* A1 */ +#define FLAG_JMP (1L<<13) /* instruction is a branch */ +#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ +#define FLAG_MEM (1L<<15) /* reads/writes memory */ +#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation + New meaning: operation cannot be + combined in parallel with ADD/SUBppp. */ +#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ +#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ +#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ +#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ +#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ +#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) +#define FLAG_C FLAG_7 +#define FLAG_ALL (FLAG_0 | \ + FLAG_1 | \ + FLAG_2 | \ + FLAG_3 | \ + FLAG_4 | \ + FLAG_5 | \ + FLAG_6 | \ + FLAG_7 | \ + FLAG_SM | \ + FLAG_RP | \ + FLAG_CONTROL) + + int reloc_flag; +#define RELOC_PCREL 1 +#define RELOC_ABS 2 +}; + +extern const struct d30v_opcode d30v_opcode_table[]; +extern const int d30v_num_opcodes; + +/* The operands table is an array of struct d30v_operand. */ +struct d30v_operand +{ + /* the length of the field */ + int length; + + /* The number of significant bits in the operand. */ + int bits; + + /* position relative to Ra */ + int position; + + /* syntax flags. */ + long flags; +}; +extern const struct d30v_operand d30v_operand_table[]; + +/* Values defined for the flags field of a struct d30v_operand. */ + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (1) + +/* number or symbol */ +#define OPERAND_NUM (2) + +/* address or label */ +#define OPERAND_ADDR (4) + +/* register */ +#define OPERAND_REG (8) + +/* postincrement + */ +#define OPERAND_PLUS (0x10) + +/* postdecrement - */ +#define OPERAND_MINUS (0x20) + +/* signed number */ +#define OPERAND_SIGNED (0x40) + +/* this operand must be shifted left by 3 */ +#define OPERAND_SHIFT (0x80) + +/* flag register */ +#define OPERAND_FLAG (0x100) + +/* control register */ +#define OPERAND_CONTROL (0x200) + +/* accumulator */ +#define OPERAND_ACC (0x400) + +/* @ */ +#define OPERAND_ATSIGN (0x800) + +/* @( */ +#define OPERAND_ATPAR (0x1000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x2000) + +/* this operand changes the instruction name */ +/* for example, CPMcc, CMPUcc */ +#define OPERAND_NAME (0x4000) + +/* fake operand for mvtsys and mvfsys */ +#define OPERAND_SPECIAL (0x8000) + +/* let the optimizer know that two registers are affected */ +#define OPERAND_2REG (0x10000) + +/* This operand is pc-relative. Note that repeati can have two immediate + operands, one of which is pcrel, the other (the IMM6U one) is not. */ +#define OPERAND_PCREL (0x20000) + +/* The format table is an array of struct d30v_format. */ +struct d30v_format +{ + int form; /* SHORT_A, LONG, etc */ + int modifier; /* two bit modifier following opcode */ + unsigned char operands[5]; +}; +extern const struct d30v_format d30v_format_table[]; + + +/* an instruction is defined by an opcode and a format */ +/* for example, "add" has one opcode, but three different */ +/* formats, 2 SHORT_A forms and a LONG form. */ +struct d30v_insn +{ + struct d30v_opcode *op; /* pointer to an entry in the opcode table */ + struct d30v_format *form; /* pointer to an entry in the format table */ + int ecc; /* execution condition code */ +}; + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D30V_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/dlx.h b/external/gpl3/gdb/dist/include/opcode/dlx.h new file mode 100644 index 000000000000..54dadd07277f --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/dlx.h @@ -0,0 +1,283 @@ +/* Table of opcodes for the DLX microprocess. + Copyright 2002, 2010 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. + + Initially created by Kuang Hwa Lin, 2002. */ + +/* Following are the function codes for the Special OP (ALU). */ +#define ALUOP 0x00000000 +#define SPECIALOP 0x00000000 + +#define NOPF 0x00000000 +#define SLLF 0x00000004 +#define SRLF 0x00000006 +#define SRAF 0x00000007 + +#define SEQUF 0x00000010 +#define SNEUF 0x00000011 +#define SLTUF 0x00000012 +#define SGTUF 0x00000013 +#define SLEUF 0x00000014 +#define SGEUF 0x00000015 + +#define ADDF 0x00000020 +#define ADDUF 0x00000021 +#define SUBF 0x00000022 +#define SUBUF 0x00000023 +#define ANDF 0x00000024 +#define ORF 0x00000025 +#define XORF 0x00000026 + +#define SEQF 0x00000028 +#define SNEF 0x00000029 +#define SLTF 0x0000002A +#define SGTF 0x0000002B +#define SLEF 0x0000002C +#define SGEF 0x0000002D + /* Following special functions was not mentioned in the + Hennessy's book but was implemented in the RTL. */ +#define MVTSF 0x00000030 +#define MVFSF 0x00000031 +#define BSWAPF 0x00000032 +#define LUTF 0x00000033 +/* Following special functions was mentioned in the + Hennessy's book but was not implemented in the RTL. */ +#define MULTF 0x00000005 +#define MULTUF 0x00000006 +#define DIVF 0x00000007 +#define DIVUF 0x00000008 + + +/* Following are the rest of the OPcodes: + JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) + ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) + ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) + RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) + BREAKOP= (0x014 << 26) + SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) + SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) + LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) + LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) + LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), + SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) + SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) + SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ +#define JOP 0x08000000 +#define JALOP 0x0c000000 +#define BEQOP 0x10000000 +#define BNEOP 0x14000000 + +#define ADDIOP 0x20000000 +#define ADDUIOP 0x24000000 +#define SUBIOP 0x28000000 +#define SUBUIOP 0x2c000000 +#define ANDIOP 0x30000000 +#define ORIOP 0x34000000 +#define XORIOP 0x38000000 +#define LHIOP 0x3c000000 +#define RFEOP 0x40000000 +#define TRAPOP 0x44000000 +#define JROP 0x48000000 +#define JALROP 0x4c000000 +#define BREAKOP 0x50000000 + +#define SEQIOP 0x60000000 +#define SNEIOP 0x64000000 +#define SLTIOP 0x68000000 +#define SGTIOP 0x6c000000 +#define SLEIOP 0x70000000 +#define SGEIOP 0x74000000 + +#define LBOP 0x80000000 +#define LHOP 0x84000000 +#define LWOP 0x8c000000 +#define LBUOP 0x90000000 +#define LHUOP 0x94000000 +#define LDSTBU +#define LDSTHU +#define SBOP 0xa0000000 +#define SHOP 0xa4000000 +#define SWOP 0xac000000 +#define LDST + +#define SEQUIOP 0xc0000000 +#define SNEUIOP 0xc4000000 +#define SLTUIOP 0xc8000000 +#define SGTUIOP 0xcc000000 +#define SLEUIOP 0xd0000000 +#define SGEUIOP 0xd4000000 + +#define SLLIOP 0xd8000000 +#define SRLIOP 0xdc000000 +#define SRAIOP 0xe0000000 + +/* Following 3 ops was added to provide the MP atonmic operation. */ +#define LSBUOP 0x98000000 +#define LSHUOP 0x9c000000 +#define LSWOP 0xb0000000 + +/* Following opcode was defined in the Hennessy's book as + "normal" opcode but was implemented in the RTL as special + functions. */ +#if 0 +#define MVTSOP 0x50000000 +#define MVFSOP 0x54000000 +#endif + +struct dlx_opcode +{ + /* Name of the instruction. */ + char *name; + + /* Opcode word. */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a rs1 The register number is in bits 21-25 of the instruction. + b rs2/rd The register number is in bits 16-20 of the instruction. + c rd. The register number is in bits 11-15 of the instruction. + f FUNC bits 0-10 of the instruction. + i An immediate operand is in bits 0-16 of the instruction. 0 extended + I An immediate operand is in bits 0-16 of the instruction. sign extended + d An 16 bit PC relative displacement. + D An immediate operand is in bits 0-25 of the instruction. + N No opperands needed, for nops. + P it can be a register or a 16 bit operand. */ + char *args; +}; + +static const struct dlx_opcode dlx_opcodes[] = + { + /* Arithmetic and Logic R-TYPE instructions. */ + { "nop", (ALUOP|NOPF), "N" }, /* NOP */ + { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ + { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ + { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ + { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ + { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ + { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ + { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ + { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ + { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ + { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ + { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ + { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ + { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ + { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ + { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ + { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ + { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ + { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ + { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ + { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ + { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ + { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ + { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ + { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ + { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ + { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ + { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ + { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ + { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ + { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ + + /* Arithmetic and Logical Immediate I-TYPE instructions. */ + { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ + { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ + { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ + { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ + { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ + { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ + { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ + { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ + { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ + { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ + { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ + { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ + { "slti", SLTIOP, "b,a,i" }, /* Set if less */ + { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ + { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ + { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ + { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ + { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ + { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ + { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ + { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ + { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ + /* Macros for I type instructions. */ + { "mov", ADDIOP, "b,P" }, /* a move macro */ + { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ + +#if 0 + /* Move special. */ + { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ + { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ +#endif + + /* Load high Immediate I-TYPE instruction. */ + { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ + { "lui", LHIOP, "b,i" }, /* Load High Immediate */ + { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ + + /* LOAD/STORE BYTE 8 bits I-TYPE. */ + { "lb", LBOP, "b,a,I" }, /* Load Byte */ + { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ + { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ + { "sb", SBOP, "b,a,I" }, /* Store Byte */ + + /* LOAD/STORE HALFWORD 16 bits. */ + { "lh", LHOP, "b,a,I" }, /* Load Halfword */ + { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ + { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ + { "sh", SHOP, "b,a,I" }, /* Store Halfword */ + + /* LOAD/STORE WORD 32 bits. */ + { "lw", LWOP, "b,a,I" }, /* Load Word */ + { "sw", SWOP, "b,a,I" }, /* Store Word */ + { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ + + /* Branch PC-relative, 16 bits offset. */ + { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ + { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ + + /* Jumps Trap and RFE J-TYPE. */ + { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ + { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ + { "break", BREAKOP, "D" }, /* break to OS */ + { "trap" , TRAPOP, "D" }, /* TRAP to OS */ + { "rfe", RFEOP, "N" }, /* Return From Exception */ + /* Macros. */ + { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ + + /* Jumps Trap and RFE I-TYPE. */ + { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ + /* Macros. */ + { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + + { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. + This lets code examine entry i + 1 without + checking if we've run off the end of the table. */ + }; + +const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/external/gpl3/gdb/dist/include/opcode/h8300.h b/external/gpl3/gdb/dist/include/opcode/h8300.h new file mode 100644 index 000000000000..81b1c089410b --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/h8300.h @@ -0,0 +1,1894 @@ +/* Opcode table for the H8/300 + Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002, + 2003, 2004, 2005, 2008, 2009, 2010 + Free Software Foundation, Inc. + Written by Steve Chamberlain . + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* Instructions are stored as a sequence of nibbles. + If the nibble has value 15 or less than the representation is complete. + Otherwise, we record what it contains with several flags. */ + +typedef int op_type; + +enum h8_flags +{ + L_2 = 0x10, + L_3 = 0x20, + /* 3 bit constant, zero not accepted. */ + L_3NZ = 0x30, + L_4 = 0x40, + L_5 = 0x50, + L_8 = 0x60, + L_8U = 0x70, + L_16 = 0x80, + L_16U = 0x90, + L_24 = 0xA0, + L_32 = 0xB0, + L_P = 0xC0, + + /* Mask to isolate the L_x size bits. */ + SIZE = 0xF0, + + REG = 0x0100, + ABS = 0x0200, + MEMIND = 0x0300, + IMM = 0x0400, + DISP = 0x0500, + IND = 0x0600, + POSTINC = 0x0700, + POSTDEC = 0x0800, + PREINC = 0x0900, + PREDEC = 0x0A00, + PCREL = 0x0B00, + KBIT = 0x0C00, + DBIT = 0x0D00, + CONST_2 = 0x0E00, + CONST_4 = 0x0F00, + CONST_8 = 0x1000, + CONST_16 = 0x1100, + INDEXB = 0x1200, + INDEXW = 0x1300, + INDEXL = 0x1400, + PCIDXB = 0x1500, + PCIDXW = 0x1600, + PCIDXL = 0x1700, + VECIND = 0x1800, + LOWREG = 0x1900, + DATA = 0x2000, + + /* Synonyms. */ + INC = POSTINC, + DEC = PREDEC, + /* Control Registers. */ + CCR = 0x4000, + EXR = 0x4100, + MACH = 0x4200, + MACL = 0x4300, + RESERV1 = 0x4400, + RESERV2 = 0x4500, + VBR = 0x4600, + SBR = 0x4700, + MACREG = 0x4800, + CCR_EXR = 0x4900, + VBR_SBR = 0x4A00, + CC_EX_VB_SB = 0x4B00, + RESERV3 = 0x4C00, + RESERV4 = 0x4D00, + RESERV5 = 0x4E00, + RESERV6 = 0x4F00, + + /* Mask to isolate the addressing mode bits (REG .. PREDEC). */ + MODE = 0x7F00, + + CTRL = 0x4000, + + NO_SYMBOLS = 0x8000, + SRC = 0x10000, + DST = 0x20000, + OP3 = 0x40000, + MEMRELAX = 0x80000, /* Move insn which may relax. */ + + DISPREG = 0x100000, + IGNORE = 0x200000, + ABSJMP = 0x400000, + + B00 = 0x800000, /* Bit 0 must be low. */ + B01 = 0x1000000, /* Bit 0 must be high. */ + B10 = 0x2000000, /* Bit 1 must be low. */ + B11 = 0x4000000, /* Bit 1 must be high. */ + B20 = 0x8000000, /* Bit 2 must be low. */ + B21 = 0x10000000, /* Bit 2 must be high. */ + B30 = 0x20000000, /* Bit 3 must be low. */ + B31 = 0x40000000, /* Bit 3 must be high. */ + E = 0x80000000, /* End of nibble sequence. */ + + /* Immediates smaller than 8 bits are always unsigned. */ + IMM3 = IMM | L_3, + IMM4 = IMM | L_4, + IMM5 = IMM | L_5, + IMM3NZ = IMM | L_3NZ, + IMM2 = IMM | L_2, + + IMM8 = IMM | SRC | L_8, + IMM8U = IMM | SRC | L_8U, + IMM16 = IMM | SRC | L_16, + IMM16U = IMM | SRC | L_16U, + IMM32 = IMM | SRC | L_32, + + IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, + IMM4_NS = IMM4 | NO_SYMBOLS, + IMM8U_NS = IMM8U | NO_SYMBOLS, + IMM16U_NS = IMM16U | NO_SYMBOLS, + + RD8 = DST | L_8 | REG, + RD16 = DST | L_16 | REG, + RD32 = DST | L_32 | REG, + R3_8 = OP3 | L_8 | REG, + R3_16 = OP3 | L_16 | REG, + R3_32 = OP3 | L_32 | REG, + RS8 = SRC | L_8 | REG, + RS16 = SRC | L_16 | REG, + RS32 = SRC | L_32 | REG, + + RSP = SRC | L_P | REG, + RDP = DST | L_P | REG, + + PCREL8 = PCREL | L_8, + PCREL16 = PCREL | L_16, + + OP3PCREL8 = OP3 | PCREL | L_8, + OP3PCREL16 = OP3 | PCREL | L_16, + + INDEXB16 = INDEXB | L_16, + INDEXW16 = INDEXW | L_16, + INDEXL16 = INDEXL | L_16, + INDEXB16D = INDEXB | L_16 | DST, + INDEXW16D = INDEXW | L_16 | DST, + INDEXL16D = INDEXL | L_16 | DST, + + INDEXB32 = INDEXB | L_32, + INDEXW32 = INDEXW | L_32, + INDEXL32 = INDEXL | L_32, + INDEXB32D = INDEXB | L_32 | DST, + INDEXW32D = INDEXW | L_32 | DST, + INDEXL32D = INDEXL | L_32 | DST, + + DISP2SRC = DISP | L_2 | SRC, + DISP16SRC = DISP | L_16 | SRC, + DISP32SRC = DISP | L_32 | SRC, + + DISP2DST = DISP | L_2 | DST, + DISP16DST = DISP | L_16 | DST, + DISP32DST = DISP | L_32 | DST, + + DSTDISPREG = DST | DISPREG, + SRCDISPREG = SRC | DISPREG, + + ABS8SRC = SRC | ABS | L_8, + ABS16SRC = SRC | ABS | L_16U, + ABS24SRC = SRC | ABS | L_24, + ABS32SRC = SRC | ABS | L_32, + + ABS8DST = DST | ABS | L_8, + ABS16DST = DST | ABS | L_16U, + ABS24DST = DST | ABS | L_24, + ABS32DST = DST | ABS | L_32, + + ABS8OP3 = OP3 | ABS | L_8, + ABS16OP3 = OP3 | ABS | L_16U, + ABS24OP3 = OP3 | ABS | L_24, + ABS32OP3 = OP3 | ABS | L_32, + + RDDEC = DST | DEC, + RSINC = SRC | INC, + RDINC = DST | INC, + + RSPOSTINC = SRC | POSTINC, + RDPOSTINC = DST | POSTINC, + RSPREINC = SRC | PREINC, + RDPREINC = DST | PREINC, + RSPOSTDEC = SRC | POSTDEC, + RDPOSTDEC = DST | POSTDEC, + RSPREDEC = SRC | PREDEC, + RDPREDEC = DST | PREDEC, + + RSIND = SRC | IND, + RDIND = DST | IND, + R3_IND = OP3 | IND, + +#define MS32 (SRC | L_32 | MACREG) +#define MD32 (DST | L_32 | MACREG) + +#if 1 + OR8 = RS8, /* ??? OR as in One Register. */ + OR16 = RS16, + OR32 = RS32, +#else + OR8 = RD8, + OR16 = RD16, + OR32 = RD32 +#endif +}; + +enum ctrlreg +{ + C_CCR = 0, + C_EXR = 1, + C_MACH = 2, + C_MACL = 3, + C_VBR = 6, + C_SBR = 7 +}; + +enum {MAX_CODE_NIBBLES = 33}; + +struct code +{ + op_type nib[MAX_CODE_NIBBLES]; +}; + +struct arg +{ + op_type nib[3]; +}; + +/* Availability of instructions on processor models. */ +enum h8_model +{ + AV_H8, + AV_H8H, + AV_H8S, + AV_H8SX +}; + +struct h8_opcode +{ + int how; + enum h8_model available; + int time; + char *name; + struct arg args; + struct code data; +}; + +#ifdef DEFINE_TABLE + +#define DATA2 DATA, DATA +#define DATA3 DATA, DATA, DATA +#define DATA5 DATA, DATA, DATA, DATA, DATA +#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA + +#define IMM8LIST IMM8, DATA +#define IMM16LIST IMM16, DATA3 +#define IMM16ULIST IMM16U, DATA3 +#define IMM24LIST IMM24, DATA5 +#define IMM32LIST IMM32, DATA7 + +#define DISP16LIST DISP | L_16, DATA3 +#define DISP24LIST DISP | L_24, DATA5 +#define DISP32LIST DISP | L_32, DATA7 + +#define ABS8LIST ABS | L_8, DATA +#define ABS16LIST ABS | L_16U, DATA3 +#define ABS24LIST ABS | L_24, DATA5 +#define ABS32LIST ABS | L_32, DATA7 + +#define DSTABS8LIST DST | ABS | L_8, DATA +#define DSTABS16LIST DST | ABS | L_16U, DATA3 +#define DSTABS24LIST DST | ABS | L_24, DATA5 +#define DSTABS32LIST DST | ABS | L_32, DATA7 + +#define OP3ABS8LIST OP3 | ABS | L_8, DATA +#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 +#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 +#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 + +#define DSTDISP16LIST DST | DISP | L_16, DATA3 +#define DSTDISP24LIST DST | DISP | L_24, DATA5 +#define DSTDISP32LIST DST | DISP | L_32, DATA7 + +#define A16LIST L_16, DATA3 +#define A24LIST L_24, DATA5 +#define A32LIST L_32, DATA7 + +/* Extended Operand Prefixes: */ + +#define PREFIX_010 0x0, 0x1, 0x0 +#define PREFIX_015 0x0, 0x1, 0x5 +#define PREFIX_017 0x0, 0x1, 0x7 + +#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 +#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC +#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 +#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 +#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 +#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 +#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 +#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 +#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 +#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 +#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 +#define PREFIX_010A 0x0, 0x1, 0x0, 0xa +#define PREFIX_010D 0x0, 0x1, 0x0, 0xd +#define PREFIX_010E 0x0, 0x1, 0x0, 0xe + +#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 +#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC +#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 +#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 +#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 +#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 +#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 +#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 +#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 +#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 +#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 +#define PREFIX_015A 0x0, 0x1, 0x5, 0xa +#define PREFIX_015D 0x0, 0x1, 0x5, 0xd +#define PREFIX_015E 0x0, 0x1, 0x5, 0xe +#define PREFIX_015F 0x0, 0x1, 0x5, 0xf + +#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 +#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC +#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST +#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 +#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 +#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 +#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 +#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 +#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 +#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 +#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 +#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 +#define PREFIX_017A 0x0, 0x1, 0x7, 0xa +#define PREFIX_017D 0x0, 0x1, 0x7, 0xd +#define PREFIX_017E 0x0, 0x1, 0x7, 0xe +#define PREFIX_017F 0x0, 0x1, 0x7, 0xf + +#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 +#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 +#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 +#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 + +#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 +#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 +#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 +#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 + +#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 +#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 +#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 +#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 + +#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 +#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 +#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 +#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 + +#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 +#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 +#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc + + +/* Source standard fragment: */ +#define FROM_IND 0, RSIND +#define FROM_POSTINC 8, RSPOSTINC +#define FROM_POSTDEC 10, RSPOSTDEC +#define FROM_PREINC 9, RSPREINC +#define FROM_PREDEC 11, RSPREDEC +#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG +#define FROM_DISP16 12, B30 | DISPREG +#define FROM_DISP32 12, B31 | DISPREG +#define FROM_DISP16B 13, B30 | DISPREG +#define FROM_DISP16W 14, B30 | DISPREG +#define FROM_DISP16L 15, B30 | DISPREG +#define FROM_DISP32B 13, B31 | DISPREG +#define FROM_DISP32W 14, B31 | DISPREG +#define FROM_DISP32L 15, B31 | DISPREG +#define FROM_ABS16 4, B30 | IGNORE +#define FROM_ABS32 4, B31 | IGNORE + +/* Destination standard fragment: */ +#define TO_IND 0, RDIND +#define TO_IND_MOV 0, RDIND | B30 +#define TO_POSTINC 8, RDPOSTINC +#define TO_POSTINC_MOV 8, RDPOSTINC | B30 +#define TO_POSTDEC 10, RDPOSTDEC +#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 +#define TO_PREINC 9, RDPREINC +#define TO_PREINC_MOV 9, RDPREINC | B30 +#define TO_PREDEC 11, RDPREDEC +#define TO_PREDEC_MOV 11, RDPREDEC | B30 +#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG +#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 +#define TO_DISP16 12, B30 | DSTDISPREG +#define TO_DISP32 12, B31 | DSTDISPREG +#define TO_DISP16B 13, B30 | DSTDISPREG +#define TO_DISP16W 14, B30 | DSTDISPREG +#define TO_DISP16L 15, B30 | DSTDISPREG +#define TO_DISP32B 13, B31 | DSTDISPREG +#define TO_DISP32W 14, B31 | DSTDISPREG +#define TO_DISP32L 15, B31 | DSTDISPREG +#define TO_ABS16 4, B30 | IGNORE +#define TO_ABS32 4, B31 | IGNORE + +/* Source fragment for three-word instruction: */ +#define TFROM_IND 6, 9, B30 | RSIND, 12 +#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 +#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST +#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 +#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 +#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 +#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST +#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST +#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST + +/* Source fragment for three-word instruction: */ +#define TFROM_IND_B 6, 8, B30 | RSIND, 12 +#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST + +#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 +#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 +#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 +#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 +#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST + +#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST +#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST + +/* Extended Operand Class Expanders: */ + +#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} + +#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} + +#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} + +#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} + +#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} + +#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} + +/* Expansion macros for two-word (plus data) instructions. */ + +/* Expansion from one source to "standard" destinations. */ +#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from one destination to "standard" sources. */ +#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} + +/* Expansion from immediate source to "standard" destinations. */ +#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} + +/* Expansion from abs/disp source to "standard" destinations. */ +#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from ind source to "standard" destinations. */ +#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} + +/* Expansion macros for three word (plus data) instructions. */ + +#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} + +#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} + + +#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) + + +#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) + +#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) + + +/* Use the expansion macros to fill out the opcode table. */ + +#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} + +#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} + +#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} + +#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} + +#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} + +#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} + +#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} + +#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} + +#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} + + +#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ + EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_FROM_IND8 (CODE, NAME, OP4), \ + EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS32_B (CODE, NAME, OP4) + +#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ + EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ + EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_FROM_IND16 (CODE, NAME, OP3), \ + EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS32_W (CODE, NAME, OP3) + +#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ + {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ + EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ + EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ + EXPAND_FROM_REG32 (CODE, NAME, OP1), \ + EXPAND_TO_REG32 (CODE, NAME, OP1), \ + EXPAND_STD_MATRIX_L (CODE, NAME, OP1) + + +/* Old expanders: */ + +#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ + {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ + {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} + +#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} + +#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define WTWOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} + +#define BRANCH(code, name, op) \ + {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ + {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} + + +#define UNOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} + +#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} + +#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST +#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC + +#define O(op, size) (op * 4 + size) +#define OP_SIZE(HOW) (HOW % 4) +#define OP_KIND(HOW) (HOW / 4) + +enum h8_asm_codes +{ + O_RECOMPILE = 0, + O_ADD, + O_ADDX, + O_AND, + O_BAND, + O_BRA, + O_BRAB, + O_BRAW, + O_BRAL, + O_BRAS, + O_BRABC, + O_BRABS, + O_BSRBC, + O_BSRBS, + O_BRN, + O_BHI, + O_BLS, + O_BCC, + O_BCS, + O_BNE, + O_BVC, + O_BVS, + O_BPL, + O_BMI, + O_BGE, + O_BLT, + O_BGT, + O_BLE, + O_ANDC, + O_BEQ, + O_BCLR, + O_BCLREQ, + O_BCLRNE, + O_BSETEQ, + O_BSETNE, + O_BFLD, + O_BFST, + O_BIAND, + O_BILD, + O_BIOR, + O_BIXOR, + O_BIST, + O_BISTZ, + O_BLD, + O_BNOT, + O_BOR, + O_BSET, + O_BSR, + O_BXOR, + O_CMP, + O_DAA, + O_DAS, + O_DEC, + O_DIVU, + O_DIVS, + O_DIVXU, + O_DIVXS, + O_INC, + O_LDC, + O_MOV, + O_MOVAB, + O_MOVAW, + O_MOVAL, + O_MOVMD, + O_MOVSD, + O_OR, + O_ROTL, + O_ROTR, + O_ROTXL, + O_ROTXR, + O_BPT, + O_SHAL, + O_SHAR, + O_SHLL, + O_SHLR, + O_SUB, + O_SUBS, + O_TRAPA, + O_XOR, + O_XORC, + O_BST, + O_BSTZ, + O_BTST, + O_EEPMOV, + O_EXTS, + O_EXTU, + O_JMP, + O_JSR, + O_MULU, + O_MULUU, + O_MULS, + O_MULSU, + O_MULXU, + O_MULXS, + O_NOP, + O_NOT, + O_ORC, + O_RTE, + O_RTEL, + O_STC, + O_SUBX, + O_NEG, + O_RTS, + O_RTSL, + O_SLEEP, + O_ILL, + O_ADDS, + O_SYSCALL, + O_TAS, + O_CLRMAC, + O_LDMAC, + O_MAC, + O_LDM, + O_STM, + O_STMAC, + O_LAST, + /* Change made for System Call processing. */ + O_SYS_CREAT, + O_SYS_OPEN, + O_SYS_READ, + O_SYS_WRITE, + O_SYS_LSEEK, + O_SYS_CLOSE, + O_SYS_STAT, + O_SYS_FSTAT, +/* Space reserved for future file I/O system calls. */ + O_SYS_CMDLINE + /* End of System Call specific Changes. */ +}; + +enum h8_size +{ + SB = 0, + SW = 1, + SL = 2, + SN = 3 +}; + + +/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. + Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ + +struct h8_opcode h8_opcodes[] = +{ + {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), + + {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), + + {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), + + {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, + + {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), + + {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), + + {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), + + {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, + {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, + + BRANCH (O (O_BRA, SB), "bra", 0x0), + + {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, + {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, + {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, + + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, + + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + BRANCH (O (O_BRA, SB), "bt", 0x0), + BRANCH (O (O_BRN, SB), "brn", 0x1), + BRANCH (O (O_BRN, SB), "bf", 0x1), + BRANCH (O (O_BHI, SB), "bhi", 0x2), + BRANCH (O (O_BLS, SB), "bls", 0x3), + BRANCH (O (O_BCC, SB), "bcc", 0x4), + BRANCH (O (O_BCC, SB), "bhs", 0x4), + BRANCH (O (O_BCS, SB), "bcs", 0x5), + BRANCH (O (O_BCS, SB), "blo", 0x5), + BRANCH (O (O_BNE, SB), "bne", 0x6), + BRANCH (O (O_BEQ, SB), "beq", 0x7), + BRANCH (O (O_BVC, SB), "bvc", 0x8), + BRANCH (O (O_BVS, SB), "bvs", 0x9), + BRANCH (O (O_BPL, SB), "bpl", 0xA), + BRANCH (O (O_BMI, SB), "bmi", 0xB), + BRANCH (O (O_BGE, SB), "bge", 0xC), + BRANCH (O (O_BLT, SB), "blt", 0xD), + BRANCH (O (O_BGT, SB), "bgt", 0xE), + BRANCH (O (O_BLE, SB), "ble", 0xF), + + EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + + EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, + + /* Because the assembler treats SRC, DST and OP3 as ordinals, + I must designate the second argument, an immediate value, as DST. + May God have mercy on my soul. */ + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, + {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, + {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, + {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, + + {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), + + {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), + + {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, + {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), + + UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), + UNOP (O (O_DAS, SB), "das", 0x1, 0xF), + UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), + + {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, + {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, + + EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), + EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), + EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), + EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), + EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), + EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), + + UNOP (O (O_INC, SB), "inc", 0x0, 0xA), + + {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, + {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, + + {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, + {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, + {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, + + {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + + {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, + + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, + MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, + MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, + MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), + + {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, + MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), + MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), + + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, + + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), + + {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, + + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, + + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), + +#define DO_MOVA1(TYPE, OP0, OP1) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}} + +#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}} + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}}, + + DO_MOVA1 (RDIND, 0x0, B30 | RDIND), + DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), + DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), + DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), + DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), + DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), + DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), + DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), + DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), + DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), + DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST), + DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), + DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), + DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST), + DO_MOVA2 (ABS16DST, 0x4, 0x0, MEMRELAX | DSTABS16LIST), + DO_MOVA2 (ABS32DST, 0x4, 0x8, MEMRELAX | DSTABS32LIST), + + {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, + {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, + + {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, + {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, + {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, + {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, + + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, + + {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), + EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), + EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), + + {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, + + EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), + EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), + EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), + + {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), + + {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), + + {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), + + {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, + {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, + + {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, + {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), + EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), + + + {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, + {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, + {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, + {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, + {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), + + EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), + + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), + + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), + + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), + + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), + + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), + + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, + + {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, + {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, + + + EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), + + {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), + + {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), + + {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, + + {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, + {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, + + {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), + + {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), + + {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), + + {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, + {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, + + {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, + {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, + {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, + {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, + {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, + {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, + {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} +}; +#else +extern const struct h8_opcode h8_opcodes[]; +#endif + diff --git a/external/gpl3/gdb/dist/include/opcode/hppa.h b/external/gpl3/gdb/dist/include/opcode/hppa.h new file mode 100644 index 000000000000..907320644979 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/hppa.h @@ -0,0 +1,1092 @@ +/* Table of opcodes for the PA-RISC. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, + 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010 + Free Software Foundation, Inc. + + Contributed by the Center for Software Science at the + University of Utah (pa-gdb-bugs@cs.utah.edu). + + This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ + +/* There are two kinds of delay slot nullification: normal which is + * controled by the nullification bit, and conditional, which depends + * on the direction of the branch and its success or failure. + * + * NONE is unfortunately #defined in the hiux system include files. + * #undef it away. + */ +#undef NONE +struct pa_opcode +{ + const char *name; + unsigned long int match; /* Bits that must be set... */ + unsigned long int mask; /* ... in these bits. */ + char *args; + enum pa_arch arch; + char flags; +}; + +/* Enables strict matching. Opcodes with match errors are skipped + when this bit is set. */ +#define FLAG_STRICT 0x1 + +/* + All hppa opcodes are 32 bits. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character for each operand of + the instruction. Characters used as a prefix allow any second character to + be used without conflicting with the main operand characters. + + Bit positions in this description follow HP usage of lsb = 31, + "at" is lsb of field. + + In the args field, the following characters must match exactly: + + '+,() ' + + In the args field, the following characters are unused: + + ' " - / 34 6789:; ' + '@ C M [\] ' + '` e g } ' + + Here are all the characters: + + ' !"#$%&'()*+-,./0123456789:;<=>?' + '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' + '`abcdefghijklmnopqrstuvwxyz{|}~ ' + +Kinds of operands: + x integer register field at 15. + b integer register field at 10. + t integer register field at 31. + a integer register field at 10 and 15 (for PERMH) + 5 5 bit immediate at 15. + s 2 bit space specifier at 17. + S 3 bit space specifier at 18. + V 5 bit immediate value at 31 + i 11 bit immediate value at 31 + j 14 bit immediate value at 31 + k 21 bit immediate value at 31 + l 16 bit immediate value at 31 (wide mode only, unusual encoding). + n nullification for branch instructions + N nullification for spop and copr instructions + w 12 bit branch displacement + W 17 bit branch displacement (PC relative) + X 22 bit branch displacement (PC relative) + z 17 bit branch displacement (just a number, not an address) + +Also these: + + . 2 bit shift amount at 25 + * 4 bit shift amount at 25 + p 5 bit shift count at 26 (to support the SHD instruction) encoded as + 31-p + ~ 6 bit shift count at 20,22:26 encoded as 63-~. + P 5 bit bit position at 26 + q 6 bit bit position at 20,22:26 + T 5 bit field length at 31 (encoded as 32-T) + % 6 bit field length at 23,27:31 (variable extract/deposit) + | 6 bit field length at 19,27:31 (fixed extract/deposit) + A 13 bit immediate at 18 (to support the BREAK instruction) + ^ like b, but describes a control register + ! sar (cr11) register + D 26 bit immediate at 31 (to support the DIAG instruction) + $ 9 bit immediate at 28 (to support POPBTS) + + v 3 bit Special Function Unit identifier at 25 + O 20 bit Special Function Unit operation split between 15 bits at 20 + and 5 bits at 31 + o 15 bit Special Function Unit operation at 20 + 2 22 bit Special Function Unit operation split between 17 bits at 20 + and 5 bits at 31 + 1 15 bit Special Function Unit operation split between 10 bits at 20 + and 5 bits at 31 + 0 10 bit Special Function Unit operation split between 5 bits at 20 + and 5 bits at 31 + u 3 bit coprocessor unit identifier at 25 + F Source Floating Point Operand Format Completer encoded 2 bits at 20 + I Source Floating Point Operand Format Completer encoded 1 bits at 20 + (for 0xe format FP instructions) + G Destination Floating Point Operand Format Completer encoded 2 bits at 18 + H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' + (very similar to 'F') + + r 5 bit immediate value at 31 (for the break instruction) + (very similar to V above, except the value is unsigned instead of + low_sign_ext) + R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) + (same as r above, except the value is in a different location) + U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) + Q 5 bit immediate value at 10 (a bit position specified in + the bb instruction. It's the same as r above, except the + value is in a different location) + B 5 bit immediate value at 10 (a bit position specified in + the bb instruction. Similar to Q, but 64 bit handling is + different. + Z %r1 -- implicit target of addil instruction. + L ,%r2 completer for new syntax branch + { Source format completer for fcnv + _ Destination format completer for fcnv + h cbit for fcmp + = gfx tests for ftest + d 14 bit offset for single precision FP long load/store. + # 14 bit offset for double precision FP load long/store. + J Yet another 14 bit offset for load/store with ma,mb completers. + K Yet another 14 bit offset for load/store with ma,mb completers. + y 16 bit offset for word aligned load/store (PA2.0 wide). + & 16 bit offset for dword aligned load/store (PA2.0 wide). + < 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + > 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + Y %sr0,%r31 -- implicit target of be,l instruction. + @ implicit immediate value of 0 + +Completer operands all have 'c' as the prefix: + + cx indexed load and store completer. + cX indexed load and store completer. Like cx, but emits a space + after in disassembler. + cm short load and store completer. + cM short load and store completer. Like cm, but emits a space + after in disassembler. + cq long load and store completer (like cm, but inserted into a + different location in the target instruction). + cs store bytes short completer. + cA store bytes short completer. Like cs, but emits a space + after in disassembler. + ce long load/store completer for LDW/STW with a different encoding + than the others + cc load cache control hint + cd load and clear cache control hint + cC store cache control hint + co ordered access + + cp branch link and push completer + cP branch pop completer + cl branch link completer + cg branch gate completer + + cw read/write completer for PROBE + cW wide completer for MFCTL + cL local processor completer for cache control + cZ System Control Completer (to support LPA, LHA, etc.) + + ci correction completer for DCOR + ca add completer + cy 32 bit add carry completer + cY 64 bit add carry completer + cv signed overflow trap completer + ct trap on condition completer for ADDI, SUB + cT trap on condition completer for UADDCM + cb 32 bit borrow completer for SUB + cB 64 bit borrow completer for SUB + + ch left/right half completer + cH signed/unsigned saturation completer + cS signed/unsigned completer at 21 + cz zero/sign extension completer. + c* permutation completer + +Condition operands all have '?' as the prefix: + + ?f Floating point compare conditions (encoded as 5 bits at 31) + + ?a add conditions + ?A 64 bit add conditions + ?@ add branch conditions followed by nullify + ?d non-negated add branch conditions + ?D negated add branch conditions + ?w wide mode non-negated add branch conditions + ?W wide mode negated add branch conditions + + ?s compare/subtract conditions + ?S 64 bit compare/subtract conditions + ?t non-negated compare and branch conditions + ?n 32 bit compare and branch conditions followed by nullify + ?N 64 bit compare and branch conditions followed by nullify + ?Q 64 bit compare and branch conditions for CMPIB instruction + + ?l logical conditions + ?L 64 bit logical conditions + + ?b branch on bit conditions + ?B 64 bit branch on bit conditions + + ?x shift/extract/deposit conditions + ?X 64 bit shift/extract/deposit conditions + ?y shift/extract/deposit conditions followed by nullify for conditional + branches + + ?u unit conditions + ?U 64 bit unit conditions + +Floating point registers all have 'f' as a prefix: + + ft target register at 31 + fT target register with L/R halves at 31 + fa operand 1 register at 10 + fA operand 1 register with L/R halves at 10 + fX Same as fA, except prints a space before register during disasm + fb operand 2 register at 15 + fB operand 2 register with L/R halves at 15 + fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. + fE Same as fe, except prints a space before register during disasm. + fx target register at 15 (only for PA 2.0 long format FLDD/FSTD). + +Float registers for fmpyadd and fmpysub: + + fi mult operand 1 register at 10 + fj mult operand 2 register at 15 + fk mult target register at 20 + fl add/sub operand register at 25 + fm add/sub target register at 31 + +*/ + + +#if 0 +/* List of characters not to put a space after. Note that + "," is included, as the "spopN" operations use literal + commas in their completer sections. */ +static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; +#endif + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic be + consecutive. If they aren't, the assembler will bomb at runtime. + + * Immediate fields use pa_get_absolute_expression to parse the + string. It will generate a "bad expression" error if passed + a register name. Thus, register index variants of an opcode + need to precede immediate variants. + + * The disassembler does not care about the order of the opcodes + except in cases where implicit addressing is used. + + Here are the rules for ordering the opcodes of a mnemonic: + + 1) Opcodes with FLAG_STRICT should precede opcodes without + FLAG_STRICT. + + 2) Opcodes with FLAG_STRICT should be ordered as follows: + register index opcodes, short immediate opcodes, and finally + long immediate opcodes. When both pa10 and pa11 variants + of the same opcode are available, the pa10 opcode should + come first for correct architectural promotion. + + 3) When implicit addressing is available for an opcode, the + implicit opcode should precede the explicit opcode. + + 4) Opcodes without FLAG_STRICT should be ordered as follows: + register index opcodes, long immediate opcodes, and finally + short immediate opcodes. */ + +static const struct pa_opcode pa_opcodes[] = +{ + +/* Pseudo-instructions. */ + +{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ + +{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, +{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, +{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, +{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, +{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ + +/* Loads and Stores for integer registers. */ + +{ "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, +{ "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, +{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, +{ "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, +{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, +{ "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, +{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, +{ "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, +{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, + +/* Immediate instructions. */ +{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, + +/* Branching instructions. */ +{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, +{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, +{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ +{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, +{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, +{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, +{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, +{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, +{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, +{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, +{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0}, +{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, +{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, + +/* Computation Instructions. */ + +{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, +{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, +{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, +{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, +{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, +{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, +{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, +{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, +{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, +{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, + +/* Subword Operation Instructions. */ + +{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, +{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, +{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, +{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, + + +/* Extract and Deposit Instructions. */ + +{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, +{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, +{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, +{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, +{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, +{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, +{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, +{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, +{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, +{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, +{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, +{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, +{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, +{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, +{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, +{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, +{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, +{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, + +/* System Control Instructions. */ + +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, +{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, +{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, +{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, +{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, +{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa11, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa11, 0}, +{ "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, FLAG_STRICT}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, FLAG_STRICT}, +{ "fdc", 0x04003280, 0xfc00ffff, "5(b)", pa20, FLAG_STRICT}, +{ "fdc", 0x04003280, 0xfc003fff, "5(s,b)", pa20, FLAG_STRICT}, +{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fic", 0x040013c0, 0xfc00dfdf, "cZx(b)", pa20, FLAG_STRICT}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, +{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, + +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, +{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, +{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, +{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, +{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, + +/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either + the Timex FPU or the Mustang ERS (not sure which) manual. */ +{ "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, + +/* Floating Point Coprocessor Instructions. */ + +{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, +{ "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, +{ "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, +{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, FLAG_STRICT}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, +{ "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, +{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, FLAG_STRICT}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, +{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, +{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, FLAG_STRICT}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, +{ "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, +{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, FLAG_STRICT}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, +{ "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT}, +{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, FLAG_STRICT}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, +{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, +{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, +{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, +{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10, FLAG_STRICT}, +{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, +{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, +{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, + +/* Performance Monitor Instructions. */ + +{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, +{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, + +/* Assist Instructions. */ + +{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, +{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, +{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, +{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, +{ "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, +{ "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, +{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, +{ "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, +{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, + +/* More pseudo instructions which must follow the main table. */ +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + +}; + +#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) + +/* SKV 12/18/92. Added some denotations for various operands. */ + +#define PA_IMM11_AT_31 'i' +#define PA_IMM14_AT_31 'j' +#define PA_IMM21_AT_31 'k' +#define PA_DISP12 'w' +#define PA_DISP17 'W' + +#define N_HPPA_OPERAND_FORMATS 5 diff --git a/external/gpl3/gdb/dist/include/opcode/i370.h b/external/gpl3/gdb/dist/include/opcode/i370.h new file mode 100644 index 000000000000..e3b7166d2920 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/i370.h @@ -0,0 +1,267 @@ +/* i370.h -- Header file for S/390 opcode table + Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010 + Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support, Linas Vepstas + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef I370_H +#define I370_H + +/* The opcode table is an array of struct i370_opcode. */ +typedef union +{ + unsigned int i[2]; + unsigned short s[4]; + unsigned char b[8]; +} i370_insn_t; + +struct i370_opcode +{ + /* The opcode name. */ + const char *name; + + /* the length of the instruction */ + char len; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + i370_insn_t opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + i370_insn_t mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct i370_opcode i370_opcodes[]; +extern const int i370_num_opcodes; + +/* Values defined for the flags field of a struct i370_opcode. */ + +/* Opcode is defined for the original 360 architecture. */ +#define I370_OPCODE_360 (0x01) + +/* Opcode is defined for the 370 architecture. */ +#define I370_OPCODE_370 (0x02) + +/* Opcode is defined for the 370-XA architecture. */ +#define I370_OPCODE_370_XA (0x04) + +/* Opcode is defined for the ESA/370 architecture. */ +#define I370_OPCODE_ESA370 (0x08) + +/* Opcode is defined for the ESA/390 architecture. */ +#define I370_OPCODE_ESA390 (0x10) + +/* Opcode is defined for the ESA/390 w/ BFP facility. */ +#define I370_OPCODE_ESA390_BF (0x20) + +/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ +#define I370_OPCODE_ESA390_BS (0x40) + +/* Opcode is defined for the ESA/390 w/ checksum facility. */ +#define I370_OPCODE_ESA390_CK (0x80) + +/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ +#define I370_OPCODE_ESA390_CM (0x100) + +/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ +#define I370_OPCODE_ESA390_FX (0x200) + +/* Opcode is defined for the ESA/390 w/ HFP facility. */ +#define I370_OPCODE_ESA390_HX (0x400) + +/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ +#define I370_OPCODE_ESA390_IR (0x800) + +/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ +#define I370_OPCODE_ESA390_MI (0x1000) + +/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ +#define I370_OPCODE_ESA390_PC (0x2000) + +/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ +#define I370_OPCODE_ESA390_PL (0x4000) + +/* Opcode is defined for the ESA/390 w/ square-root facility. */ +#define I370_OPCODE_ESA390_QR (0x8000) + +/* Opcode is defined for the ESA/390 w/ resume-program facility. */ +#define I370_OPCODE_ESA390_RP (0x10000) + +/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ +#define I370_OPCODE_ESA390_SA (0x20000) + +/* Opcode is defined for the ESA/390 w/ subspace group facility. */ +#define I370_OPCODE_ESA390_SG (0x40000) + +/* Opcode is defined for the ESA/390 w/ string facility. */ +#define I370_OPCODE_ESA390_SR (0x80000) + +/* Opcode is defined for the ESA/390 w/ trap facility. */ +#define I370_OPCODE_ESA390_TR (0x100000) + +#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) + + +/* The operands table is an array of struct i370_operand. */ + +struct i370_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + i370_insn_t (*insert) + (i370_insn_t instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & I370_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (i370_insn_t instruction, int *invalid); + + /* One bit syntax flags. */ + unsigned long flags; + + /* name -- handy for debugging, otherwise pointless */ + char * name; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the i370_opcodes table. */ + +extern const struct i370_operand i370_operands[]; + +/* Values defined for the flags field of a struct i370_operand. */ + +/* This operand should be wrapped in parentheses rather than + separated from the previous by a comma. This is used for S, RS and + SS form instructions which want their operands to look like + reg,displacement(basereg) */ +#define I370_OPERAND_SBASE (0x01) + +/* This operand is a base register. It may or may not appear next + to an index register, i.e. either of the two forms + reg,displacement(basereg) + reg,displacement(index,basereg) */ +#define I370_OPERAND_BASE (0x02) + +/* This pair of operands should be wrapped in parentheses rather than + separated from the last by a comma. This is used for the RX form + instructions which want their operands to look like + reg,displacement(index,basereg) */ +#define I370_OPERAND_INDEX (0x04) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define I370_OPERAND_GPR (0x08) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define I370_OPERAND_FPR (0x10) + +/* This operand is a displacement. */ +#define I370_OPERAND_RELATIVE (0x20) + +/* This operand is a length, such as that in SS form instructions. */ +#define I370_OPERAND_LENGTH (0x40) + +/* This operand is optional, and is zero if omitted. This is used for + the optional B2 field in the shift-left, shift-right instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define I370_OPERAND_OPTIONAL (0x80) + + +/* Define some misc macros. We keep them with the operands table + for simplicity. The macro table is an array of struct i370_macro. */ + +struct i370_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct i370_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct i370_macro i370_macros[]; +extern const int i370_num_macros; + + +#endif /* I370_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/i386.h b/external/gpl3/gdb/dist/include/opcode/i386.h new file mode 100644 index 000000000000..b635334e41dd --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/i386.h @@ -0,0 +1,145 @@ +/* opcode/i386.h -- Intel 80386 opcode macros + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived + ix86 Unix assemblers, generate floating point instructions with + reversed source and destination registers in certain cases. + Unfortunately, gcc and possibly many other programs use this + reversed syntax, so we're stuck with it. + + eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but + `fsub %st,%st(3)' results in st(3) = st - st(3), rather than + the expected st(3) = st(3) - st + + This happens with all the non-commutative arithmetic floating point + operations with two register operands, where the source register is + %st, and destination register is %st(i). + + The affected opcode map is dceX, dcfX, deeX, defX. */ + +#ifndef OPCODE_I386_H +#define OPCODE_I386_H + +#ifndef SYSV386_COMPAT +/* Set non-zero for broken, compatible instructions. Set to zero for + non-broken opcodes at your peril. gcc generates SystemV/386 + compatible instructions. */ +#define SYSV386_COMPAT 1 +#endif +#ifndef OLDGCC_COMPAT +/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could + generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands + reversed. */ +#define OLDGCC_COMPAT SYSV386_COMPAT +#endif + +#define MOV_AX_DISP32 0xa0 +#define POP_SEG_SHORT 0x07 +#define JUMP_PC_RELATIVE 0xeb +#define INT_OPCODE 0xcd +#define INT3_OPCODE 0xcc +/* The opcode for the fwait instruction, which disassembler treats as a + prefix when it can. */ +#define FWAIT_OPCODE 0x9b + +/* Instruction prefixes. + NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as + part of the opcode. Other prefixes may still appear between them + and the 0x0f part of the opcode. */ +#define ADDR_PREFIX_OPCODE 0x67 +#define DATA_PREFIX_OPCODE 0x66 +#define LOCK_PREFIX_OPCODE 0xf0 +#define CS_PREFIX_OPCODE 0x2e +#define DS_PREFIX_OPCODE 0x3e +#define ES_PREFIX_OPCODE 0x26 +#define FS_PREFIX_OPCODE 0x64 +#define GS_PREFIX_OPCODE 0x65 +#define SS_PREFIX_OPCODE 0x36 +#define REPNE_PREFIX_OPCODE 0xf2 +#define REPE_PREFIX_OPCODE 0xf3 + +#define TWO_BYTE_OPCODE_ESCAPE 0x0f +#define NOP_OPCODE (char) 0x90 + +/* register numbers */ +#define EAX_REG_NUM 0 +#define ECX_REG_NUM 1 +#define EDX_REG_NUM 2 +#define EBX_REG_NUM 3 +#define ESP_REG_NUM 4 +#define EBP_REG_NUM 5 +#define ESI_REG_NUM 6 +#define EDI_REG_NUM 7 + +/* modrm_byte.regmem for twobyte escape */ +#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM +/* index_base_byte.index for no index register addressing */ +#define NO_INDEX_REGISTER ESP_REG_NUM +/* index_base_byte.base for no base register addressing */ +#define NO_BASE_REGISTER EBP_REG_NUM +#define NO_BASE_REGISTER_16 6 + +/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ +#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ +#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) + +/* Extract fields from the mod/rm byte. */ +#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) +#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) +#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) + +/* Extract fields from the sib byte. */ +#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) +#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) +#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) + +/* x86-64 extension prefix. */ +#define REX_OPCODE 0x40 + +/* Non-zero if OPCODE is the rex prefix. */ +#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) + +/* Indicates 64 bit operand size. */ +#define REX_W 8 +/* High extension to reg field of modrm byte. */ +#define REX_R 4 +/* High extension to SIB index field. */ +#define REX_X 2 +/* High extension to base field of modrm or SIB, or reg field of opcode. */ +#define REX_B 1 + +/* max operands per insn */ +#define MAX_OPERANDS 5 + +/* max immediates per insn (lcall, ljmp, insertq, extrq) */ +#define MAX_IMMEDIATE_OPERANDS 2 + +/* max memory refs per insn (string ops) */ +#define MAX_MEMORY_OPERANDS 2 + +/* max size of insn mnemonics. */ +#define MAX_MNEM_SIZE 20 + +/* max size of register name in insn mnemonics. */ +#define MAX_REG_NAME_SIZE 8 + +#endif /* OPCODE_I386_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/i860.h b/external/gpl3/gdb/dist/include/opcode/i860.h new file mode 100644 index 000000000000..7f4aafd9c2c6 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/i860.h @@ -0,0 +1,507 @@ +/* Table of opcodes for the i860. + Copyright 1989, 1991, 2000, 2002, 2003, 2010 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* Structure of an opcode table entry. */ +struct i860_opcode +{ + /* The opcode name. */ + const char *name; + + /* Bits that must be set. */ + unsigned long match; + + /* Bits that must not be set. */ + unsigned long lose; + + const char *args; + + /* Nonzero if this is a possible expand-instruction. */ + char expand; +}; + + +enum expand_type +{ + E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY +}; + + +/* All i860 opcodes are 32 bits, except for the pseudo-instructions + and the operations utilizing a 32-bit address expression, an + unsigned 32-bit constant, or a signed 32-bit constant. + These opcodes are expanded into a two-instruction sequence for + any situation where the immediate operand does not fit in 32 bits. + In the case of the add and subtract operations the expansion is + to a three-instruction sequence (ex: orh, or, adds). In cases + where the address is to be relocated, the instruction is + expanded to handle the worse case, this could be optimized at + the final link if the actual address were known. + + The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. + These instructions are implemented as a one or two instruction + sequence of other operations. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 src1 integer register. + 2 src2 integer register. + d dest register. + c ctrlreg control register. + i 16 bit immediate. + I 16 bit immediate, aligned 2^0. (ld.b) + J 16 bit immediate, aligned 2^1. (ld.s) + K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) + L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) + M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) + 5 5 bit immediate. + l lbroff 26 bit PC relative immediate. + r sbroff 16 bit PC relative immediate. + s split 16 bit immediate. + S split 16 bit immediate, aligned 2^0. (st.b) + T split 16 bit immediate, aligned 2^1. (st.s) + U split 16 bit immediate, aligned 2^2. (st.l) + e src1 floating point register. + f src2 floating point register. + g dest floating point register. */ + + +/* The order of the opcodes in this table is significant. The assembler + requires that all instances of the same mnemonic must be consecutive. + If they aren't, the assembler will not function properly. + + The order of opcodes does not affect the disassembler. */ + +static const struct i860_opcode i860_opcodes[] = +{ +/* REG-Format Instructions. */ +{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ +{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ +{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ +{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ +{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ +{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ +{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ + +{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ +{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ +{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ +{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ + +{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ + +{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ +{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ +{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ +{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ +{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ +{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ +{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ +{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ +{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ +{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ +{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ +{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ + +{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ +{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ +{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ +{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ +{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ +{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ +{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ +{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ +{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ +{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ +{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ +{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ + +{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ +{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ +{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ +{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ +{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ +{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ + +{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ +{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ + +{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ +{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ +{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ +{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ +{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ +{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ +{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ +{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ + +{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ +{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ +{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ +{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ +{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ +{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ +{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ + +{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ +{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ +{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ +{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ + +{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ + +{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ +{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ + +{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ +{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ +{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ +{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ +{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ +{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ +{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ +{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ +{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ +{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ +{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ +{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ + +{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ +{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ +{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ +{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ +{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ +{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ + +/* Core Escape Instruction Format */ +{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ +{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ +{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ +{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ +{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ +{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ +{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ +{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ +{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ +{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ +{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ +{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ +{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ +{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ + +/* CTRL-Format Instructions */ +{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ +{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ +{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ +{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ +{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ +{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ + +/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ +{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, +{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, +{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, +{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, +{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, +{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, +{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, +{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, +{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, +{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, +{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, +{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, +{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, +{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, +{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, +{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, +{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, +{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, +{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, +{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, +{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, +{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, +{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, +{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, +{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, +{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, +{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, +{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, +{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, +{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, +{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, +{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, +{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, +{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, +{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, +{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, +{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, +{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, +{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, +{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, +{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, +{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, +{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, +{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, +{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, +{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, +{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, +{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ +{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, +{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, +{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, +{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, +{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, +{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, +{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, +{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, +{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, +{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, +{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, +{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, +{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, +{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, +{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, +{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, +{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, +{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, +{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, +{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, +{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, +{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, +{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, +{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, +{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, +{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, +{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, +{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, +{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, +{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, +{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, +{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, +{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, +{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, +{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, +{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, +{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, +{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, +{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, +{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, +{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, +{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, +{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, +{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, +{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, +{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, +{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, +{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ +{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, +{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, +{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, +{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, +{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, +{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, +{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, +{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, +{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, +{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, +{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, +{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, +{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, +{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, +{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, +{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, +{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, +{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, +{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, +{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, +{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, +{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, +{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, +{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, +{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, +{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, +{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, +{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, +{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, +{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, +{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, +{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, +{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, +{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, +{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, +{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, +{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, +{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, +{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, +{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, +{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, +{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, +{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, +{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, +{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ +{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, +{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, +{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, +{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, +{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, +{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, +{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, +{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, +{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, +{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, +{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, +{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, +{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, +{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, +{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, +{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, +{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, +{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, +{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, +{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, +{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, +{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, +{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, +{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, +{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, +{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, +{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, +{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, +{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, +{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, +{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, +{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, +{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, +{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, +{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, +{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, +{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, +{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, +{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, +{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, +{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, +{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, +{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, +{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, +{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, + +{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ +{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ +{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ +{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ +{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ +{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ +{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ +{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ +{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ +{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ +{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ +{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ +{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ + +/* Floating point pseudo-instructions. */ +{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ +{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ +{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ +{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ +{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ +{ 0, 0, 0, 0, 0 }, + +}; + +#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) + + diff --git a/external/gpl3/gdb/dist/include/opcode/i960.h b/external/gpl3/gdb/dist/include/opcode/i960.h new file mode 100644 index 000000000000..dc0e78f88a15 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/i960.h @@ -0,0 +1,525 @@ +/* Basic 80960 instruction formats. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* The 'COJ' instructions are actually COBR instructions with the 'b' in + the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if + necessary: if the displacement will not fit in 13 bits, the assembler will + replace them with the corresponding compare and branch instructions. + + All of the 'MEMn' instructions are the same format; the 'n' in the name + indicates the default index scale factor (the size of the datum operated on). + + The FBRA formats are not actually an instruction format. They are the + "convenience directives" for branching on floating-point comparisons, + each of which generates 2 instructions (a 'bno' and one other branch). + + The CALLJ format is not actually an instruction format. It indicates that + the instruction generated (a CTRL-format 'call') should have its relocation + specially flagged for link-time replacement with a 'bal' or 'calls' if + appropriate. */ + +#define CTRL 0 +#define COBR 1 +#define COJ 2 +#define REG 3 +#define MEM1 4 +#define MEM2 5 +#define MEM4 6 +#define MEM8 7 +#define MEM12 8 +#define MEM16 9 +#define FBRA 10 +#define CALLJ 11 + +/* Masks for the mode bits in REG format instructions */ +#define M1 0x0800 +#define M2 0x1000 +#define M3 0x2000 + +/* Generate the 12-bit opcode for a REG format instruction by placing the + * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits + * 7-10. + */ + +#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) + +/* Generate a template for a REG format instruction: place the opcode bits + * in the appropriate fields and OR in mode bits for the operands that will not + * be used. I.e., + * set m1=1, if src1 will not be used + * set m2=1, if src2 will not be used + * set m3=1, if dst will not be used + * + * Setting the "unused" mode bits to 1 speeds up instruction execution(!). + * The information is also useful to us because some 1-operand REG instructions + * use the src1 field, others the dst field; and some 2-operand REG instructions + * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. + */ +#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ +#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ +#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ +#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ +#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ +#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ + +/* DESCRIPTOR BYTES FOR REGISTER OPERANDS + * + * Interpret names as follows: + * R: global or local register only + * RS: global, local, or (if target allows) special-function register only + * RL: global or local register, or integer literal + * RSL: global, local, or (if target allows) special-function register; + * or integer literal + * F: global, local, or floating-point register + * FL: global, local, or floating-point register; or literal (including + * floating point) + * + * A number appended to a name indicates that registers must be aligned, + * as follows: + * 2: register number must be multiple of 2 + * 4: register number must be multiple of 4 + */ + +#define SFR 0x10 /* Mask for the "sfr-OK" bit */ +#define LIT 0x08 /* Mask for the "literal-OK" bit */ +#define FP 0x04 /* Mask for "floating-point-OK" bit */ + +/* This macro ors the bits together. Note that 'align' is a mask + * for the low 0, 1, or 2 bits of the register number, as appropriate. + */ +#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) + +#define R OP( 0, 0, 0, 0 ) +#define RS OP( 0, 0, 0, SFR ) +#define RL OP( 0, LIT, 0, 0 ) +#define RSL OP( 0, LIT, 0, SFR ) +#define F OP( 0, 0, FP, 0 ) +#define FL OP( 0, LIT, FP, 0 ) +#define R2 OP( 1, 0, 0, 0 ) +#define RL2 OP( 1, LIT, 0, 0 ) +#define F2 OP( 1, 0, FP, 0 ) +#define FL2 OP( 1, LIT, FP, 0 ) +#define R4 OP( 3, 0, 0, 0 ) +#define RL4 OP( 3, LIT, 0, 0 ) +#define F4 OP( 3, 0, FP, 0 ) +#define FL4 OP( 3, LIT, FP, 0 ) + +#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ + +/* Macros to extract info from the register operand descriptor byte 'od'. + */ +#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ +#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ +#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ +#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) + /* TRUE if reg #n is properly aligned */ +#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ + +/* Description of a single i80960 instruction */ +struct i960_opcode { + long opcode; /* 32 bits, constant fields filled in, rest zeroed */ + char *name; /* Assembler mnemonic */ + short iclass; /* Class: see #defines below */ + char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ + char num_ops; /* Number of operands */ + char operand[3];/* Operand descriptors; same order as assembler instr */ +}; + +/* Classes of 960 intructions: + * - each instruction falls into one class. + * - each target architecture supports one or more classes. + * + * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). + */ +#define I_BASE 0x01 /* 80960 base instruction set */ +#define I_CX 0x02 /* 80960Cx instruction */ +#define I_DEC 0x04 /* Decimal instruction */ +#define I_FP 0x08 /* Floating point instruction */ +#define I_KX 0x10 /* 80960Kx instruction */ +#define I_MIL 0x20 /* Military instruction */ +#define I_CASIM 0x40 /* CA simulator instruction */ +#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ +#define I_JX 0x100 /* Jx/Hx instruction */ +#define I_HX 0x200 /* Hx instructions */ + +/****************************************************************************** + * + * TABLE OF i960 INSTRUCTION DESCRIPTIONS + * + ******************************************************************************/ + +const struct i960_opcode i960_opcodes[] = { + + /* if a CTRL instruction has an operand, it's always a displacement */ + + /* callj default=='call' */ + { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, + { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bf same as bno */ + { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bru same as bno */ + { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brg same as bg */ + { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bre same as be */ + { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brge same as bge */ + { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brl same as bl */ + { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brlg same as bne */ + { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brle same as ble */ + { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bt same as bo */ + { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bro same as bo */ + { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultf same as faultno */ + { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultt syn for faulto */ + { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, + + { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, + + /* If a COBR (or COJ) has 3 operands, the last one is always a + * displacement and does not appear explicitly in the table. + */ + + { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, + + { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, + { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, + { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, + { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, + { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, + { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, + { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, + { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, + { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, + { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, + + { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, + { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, + { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, + { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, + { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, + { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, + { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, + { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, + + /* Floating-point instructions */ + + { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, + { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, + { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, + { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, + { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, + { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, + { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, + { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, + { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, + { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + + /* These are the floating point branch instructions. Each actually + * generates 2 branch instructions: the first a CTRL instruction with + * the indicated opcode, and the second a 'bno'. + */ + + { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, + + + /* Decimal instructions */ + + { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, + + + /* KX extensions */ + + { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, + { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, + + + /* MC extensions */ + + { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, + { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, + { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, + { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, + { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, + + + /* CX extensions */ + + { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, + { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, + { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, + + + /* Jx extensions. */ + { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, + + { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, + + { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, + { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, + + /* Hx extensions. */ + { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, + + /* END OF TABLE */ + + { 0, NULL, 0, 0, 0, { 0, 0, 0 } } +}; + + /* end of i960-opcode.h */ diff --git a/external/gpl3/gdb/dist/include/opcode/ia64.h b/external/gpl3/gdb/dist/include/opcode/ia64.h new file mode 100644 index 000000000000..4285377f7ba7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/ia64.h @@ -0,0 +1,413 @@ +/* ia64.h -- Header file for ia64 opcode table + Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef opcode_ia64_h +#define opcode_ia64_h + +#include + +#include "bfd.h" + + +typedef BFD_HOST_U_64_BIT ia64_insn; + +enum ia64_insn_type + { + IA64_TYPE_NIL = 0, /* illegal type */ + IA64_TYPE_A, /* integer alu (I- or M-unit) */ + IA64_TYPE_I, /* non-alu integer (I-unit) */ + IA64_TYPE_M, /* memory (M-unit) */ + IA64_TYPE_B, /* branch (B-unit) */ + IA64_TYPE_F, /* floating-point (F-unit) */ + IA64_TYPE_X, /* long encoding (X-unit) */ + IA64_TYPE_DYN, /* Dynamic opcode */ + IA64_NUM_TYPES + }; + +enum ia64_unit + { + IA64_UNIT_NIL = 0, /* illegal unit */ + IA64_UNIT_I, /* integer unit */ + IA64_UNIT_M, /* memory unit */ + IA64_UNIT_B, /* branching unit */ + IA64_UNIT_F, /* floating-point unit */ + IA64_UNIT_L, /* long "unit" */ + IA64_UNIT_X, /* may be integer or branch unit */ + IA64_NUM_UNITS + }; + +/* Changes to this enumeration must be propagated to the operand table in + bfd/cpu-ia64-opc.c + */ +enum ia64_opnd + { + IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ + + /* constants */ + IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ + IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ + IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ + IA64_OPND_C1, /* the constant 1 */ + IA64_OPND_C8, /* the constant 8 */ + IA64_OPND_C16, /* the constant 16 */ + IA64_OPND_GR0, /* gr0 */ + IA64_OPND_IP, /* instruction pointer (ip) */ + IA64_OPND_PR, /* predicate register (pr) */ + IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ + IA64_OPND_PSR, /* processor status register (psr) */ + IA64_OPND_PSR_L, /* processor status register L (psr.l) */ + IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ + + /* register operands: */ + IA64_OPND_AR3, /* third application register # (bits 20-26) */ + IA64_OPND_B1, /* branch register # (bits 6-8) */ + IA64_OPND_B2, /* branch register # (bits 13-15) */ + IA64_OPND_CR3, /* third control register # (bits 20-26) */ + IA64_OPND_F1, /* first floating-point register # */ + IA64_OPND_F2, /* second floating-point register # */ + IA64_OPND_F3, /* third floating-point register # */ + IA64_OPND_F4, /* fourth floating-point register # */ + IA64_OPND_P1, /* first predicate # */ + IA64_OPND_P2, /* second predicate # */ + IA64_OPND_R1, /* first register # */ + IA64_OPND_R2, /* second register # */ + IA64_OPND_R3, /* third register # */ + IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + + /* memory operands: */ + IA64_OPND_MR3, /* memory at addr of third register # */ + + /* indirect operands: */ + IA64_OPND_CPUID_R3, /* cpuid[reg] */ + IA64_OPND_DBR_R3, /* dbr[reg] */ + IA64_OPND_DTR_R3, /* dtr[reg] */ + IA64_OPND_ITR_R3, /* itr[reg] */ + IA64_OPND_IBR_R3, /* ibr[reg] */ + IA64_OPND_MSR_R3, /* msr[reg] */ + IA64_OPND_PKR_R3, /* pkr[reg] */ + IA64_OPND_PMC_R3, /* pmc[reg] */ + IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_RR_R3, /* rr[reg] */ + + /* immediate operands: */ + IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ + IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ + IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ + IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ + IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ + IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ + IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ + IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ + IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ + IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ + IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ + IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ + IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ + IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ + IA64_OPND_SOF, /* 8-bit stack frame size */ + IA64_OPND_SOL, /* 8-bit size of locals */ + IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ + IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ + IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ + IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ + IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ + IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ + IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ + IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ + IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ + IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ + IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ + IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ + IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ + IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ + IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ + IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ + IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ + IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ + IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ + IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ + IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ + IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ + IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ + IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ + IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ + IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ + }; + +enum ia64_dependency_mode +{ + IA64_DV_RAW, + IA64_DV_WAW, + IA64_DV_WAR, +}; + +enum ia64_dependency_semantics +{ + IA64_DVS_NONE, + IA64_DVS_IMPLIED, + IA64_DVS_IMPLIEDF, + IA64_DVS_DATA, + IA64_DVS_INSTR, + IA64_DVS_SPECIFIC, + IA64_DVS_STOP, + IA64_DVS_OTHER, +}; + +enum ia64_resource_specifier +{ + IA64_RS_ANY, + IA64_RS_AR_K, + IA64_RS_AR_UNAT, + IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ + IA64_RS_ARb, /* 48-63, 112-127 */ + IA64_RS_BR, + IA64_RS_CFM, + IA64_RS_CPUID, + IA64_RS_CR_IIB, + IA64_RS_CR_IRR, + IA64_RS_CR_LRR, + IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ + IA64_RS_DBR, + IA64_RS_FR, + IA64_RS_FRb, + IA64_RS_GR0, + IA64_RS_GR, + IA64_RS_IBR, + IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ + IA64_RS_MSR, + IA64_RS_PKR, + IA64_RS_PMC, + IA64_RS_PMD, + IA64_RS_PR, /* non-rotating, 1-15 */ + IA64_RS_PRr, /* rotating, 16-62 */ + IA64_RS_PR63, + IA64_RS_RR, + + IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ + IA64_RS_CRX, /* CRs not in RS_CR */ + IA64_RS_PSR, /* PSR bits */ + IA64_RS_RSE, /* implementation-specific RSE resources */ + IA64_RS_AR_FPSR, +}; + +enum ia64_rse_resource +{ + IA64_RSE_N_STACKED_PHYS, + IA64_RSE_BOF, + IA64_RSE_STORE_REG, + IA64_RSE_LOAD_REG, + IA64_RSE_BSPLOAD, + IA64_RSE_RNATBITINDEX, + IA64_RSE_CFLE, + IA64_RSE_NDIRTY, +}; + +/* Information about a given resource dependency */ +struct ia64_dependency +{ + /* Name of the resource */ + const char *name; + /* Does this dependency need further specification? */ + enum ia64_resource_specifier specifier; + /* Mode of dependency */ + enum ia64_dependency_mode mode; + /* Dependency semantics */ + enum ia64_dependency_semantics semantics; + /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ +#define REG_NONE (-1) + int regindex; + /* Special info on semantics */ + const char *info; +}; + +/* Two arrays of indexes into the ia64_dependency table. + chks are dependencies to check for conflicts when an opcode is + encountered; regs are dependencies to register (mark as used) when an + opcode is used. chks correspond to readers (RAW) or writers (WAW or + WAR) of a resource, while regs correspond to writers (RAW or WAW) and + readers (WAR) of a resource. */ +struct ia64_opcode_dependency +{ + int nchks; + const unsigned short *chks; + int nregs; + const unsigned short *regs; +}; + +/* encode/extract the note/index for a dependency */ +#define RDEP(N,X) (((N)<<11)|(X)) +#define NOTE(X) (((X)>>11)&0x1F) +#define DEP(X) ((X)&0x7FF) + +/* A template descriptor describes the execution units that are active + for each of the three slots. It also specifies the location of + instruction group boundaries that may be present between two slots. */ +struct ia64_templ_desc + { + int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ + enum ia64_unit exec_unit[3]; + const char *name; + }; + +/* The opcode table is an array of struct ia64_opcode. */ + +struct ia64_opcode + { + /* The opcode name. */ + const char *name; + + /* The type of the instruction: */ + enum ia64_insn_type type; + + /* Number of output operands: */ + int num_outputs; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + ia64_insn opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + ia64_insn mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + enum ia64_opnd operands[5]; + + /* One bit flags for the opcode. These are primarily used to + indicate specific processors and environments support the + instructions. The defined values are listed below. */ + unsigned int flags; + + /* Used by ia64_find_next_opcode (). */ + short ent_index; + + /* Opcode dependencies. */ + const struct ia64_opcode_dependency *dependencies; + }; + +/* Values defined for the flags field of a struct ia64_opcode. */ + +#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ +#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ +#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ +#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ +#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ +#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ +#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ +#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ +#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ +#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ +#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ + +/* A macro to extract the major opcode from an instruction. */ +#define IA64_OP(i) (((i) >> 37) & 0xf) + +enum ia64_operand_class + { + IA64_OPND_CLASS_CST, /* constant */ + IA64_OPND_CLASS_REG, /* register */ + IA64_OPND_CLASS_IND, /* indirect register */ + IA64_OPND_CLASS_ABS, /* absolute value */ + IA64_OPND_CLASS_REL, /* IP-relative value */ + }; + +/* The operands table is an array of struct ia64_operand. */ + +struct ia64_operand +{ + enum ia64_operand_class op_class; + + /* Set VALUE as the operand bits for the operand of type SELF in the + instruction pointed to by CODE. If an error occurs, *CODE is not + modified and the returned string describes the cause of the + error. If no error occurs, NULL is returned. */ + const char *(*insert) (const struct ia64_operand *self, ia64_insn value, + ia64_insn *code); + + /* Extract the operand bits for an operand of type SELF from + instruction CODE store them in *VALUE. If an error occurs, the + cause of the error is described by the string returned. If no + error occurs, NULL is returned. */ + const char *(*extract) (const struct ia64_operand *self, ia64_insn code, + ia64_insn *value); + + /* A string whose meaning depends on the operand class. */ + + const char *str; + + struct bit_field + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + } + field[4]; /* no operand has more than this many bit-fields */ + + unsigned int flags; + + const char *desc; /* brief description */ +}; + +/* Values defined for the flags field of a struct ia64_operand. */ + +/* Disassemble as signed decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) +/* Disassemble as unsigned decimal (instead of hex): */ +#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) + +extern const struct ia64_templ_desc ia64_templ_desc[16]; + +/* The tables are sorted by major opcode number and are otherwise in + the order in which the disassembler should consider instructions. */ +extern struct ia64_opcode ia64_opcodes_a[]; +extern struct ia64_opcode ia64_opcodes_i[]; +extern struct ia64_opcode ia64_opcodes_m[]; +extern struct ia64_opcode ia64_opcodes_b[]; +extern struct ia64_opcode ia64_opcodes_f[]; +extern struct ia64_opcode ia64_opcodes_d[]; + + +extern struct ia64_opcode *ia64_find_opcode (const char *); +extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); + +extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, + enum ia64_insn_type); + +extern void ia64_free_opcode (struct ia64_opcode *); +extern const struct ia64_dependency *ia64_find_dependency (int); + +/* To avoid circular library dependencies, this array is implemented + in bfd/cpu-ia64-opc.c: */ +extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; + +#endif /* opcode_ia64_h */ diff --git a/external/gpl3/gdb/dist/include/opcode/m68hc11.h b/external/gpl3/gdb/dist/include/opcode/m68hc11.h new file mode 100644 index 000000000000..83f5a9a651a1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/m68hc11.h @@ -0,0 +1,428 @@ +/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table + Copyright 1999, 2000, 2002, 2003, 2010 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _OPCODE_M68HC11_H +#define _OPCODE_M68HC11_H + +/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ +#define M6811_S_BIT 0x80 /* Stop disable */ +#define M6811_X_BIT 0x40 /* X-interrupt mask */ +#define M6811_H_BIT 0x20 /* Half carry flag */ +#define M6811_I_BIT 0x10 /* I-interrupt mask */ +#define M6811_N_BIT 0x08 /* Negative */ +#define M6811_Z_BIT 0x04 /* Zero */ +#define M6811_V_BIT 0x02 /* Overflow */ +#define M6811_C_BIT 0x01 /* Carry */ + +/* 68HC11 register address offsets (range 0..0x3F or 0..64). + The absolute address of the I/O register depends on the setting + of the M6811_INIT register. At init time, the I/O registers are + mapped at 0x1000. Address of registers is then: + + 0x1000 + M6811_xxx +*/ +#define M6811_PORTA 0x00 /* Port A register */ +#define M6811__RES1 0x01 /* Unused/Reserved */ +#define M6811_PIOC 0x02 /* Parallel I/O Control register */ +#define M6811_PORTC 0x03 /* Port C register */ +#define M6811_PORTB 0x04 /* Port B register */ +#define M6811_PORTCL 0x05 /* Alternate latched port C */ +#define M6811__RES6 0x06 /* Unused/Reserved */ +#define M6811_DDRC 0x07 /* Data direction register for port C */ +#define M6811_PORTD 0x08 /* Port D register */ +#define M6811_DDRD 0x09 /* Data direction register for port D */ +#define M6811_PORTE 0x0A /* Port E input register */ +#define M6811_CFORC 0x0B /* Compare Force Register */ +#define M6811_OC1M 0x0C /* OC1 Action Mask register */ +#define M6811_OC1D 0x0D /* OC1 Action Data register */ +#define M6811_TCTN 0x0E /* Timer Counter Register */ +#define M6811_TCTN_H 0x0E /* " " " High part */ +#define M6811_TCTN_L 0x0F /* " " " Low part */ +#define M6811_TIC1 0x10 /* Input capture 1 register */ +#define M6811_TIC1_H 0x10 /* " " " High part */ +#define M6811_TIC1_L 0x11 /* " " " Low part */ +#define M6811_TIC2 0x12 /* Input capture 2 register */ +#define M6811_TIC2_H 0x12 /* " " " High part */ +#define M6811_TIC2_L 0x13 /* " " " Low part */ +#define M6811_TIC3 0x14 /* Input capture 3 register */ +#define M6811_TIC3_H 0x14 /* " " " High part */ +#define M6811_TIC3_L 0x15 /* " " " Low part */ +#define M6811_TOC1 0x16 /* Output Compare 1 register */ +#define M6811_TOC1_H 0x16 /* " " " High part */ +#define M6811_TOC1_L 0x17 /* " " " Low part */ +#define M6811_TOC2 0x18 /* Output Compare 2 register */ +#define M6811_TOC2_H 0x18 /* " " " High part */ +#define M6811_TOC2_L 0x19 /* " " " Low part */ +#define M6811_TOC3 0x1A /* Output Compare 3 register */ +#define M6811_TOC3_H 0x1A /* " " " High part */ +#define M6811_TOC3_L 0x1B /* " " " Low part */ +#define M6811_TOC4 0x1C /* Output Compare 4 register */ +#define M6811_TOC4_H 0x1C /* " " " High part */ +#define M6811_TOC4_L 0x1D /* " " " Low part */ +#define M6811_TOC5 0x1E /* Output Compare 5 register */ +#define M6811_TOC5_H 0x1E /* " " " High part */ +#define M6811_TOC5_L 0x1F /* " " " Low part */ +#define M6811_TCTL1 0x20 /* Timer Control register 1 */ +#define M6811_TCTL2 0x21 /* Timer Control register 2 */ +#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ +#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ +#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ +#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ +#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ +#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ +#define M6811_SPCR 0x28 /* SPI Control register */ +#define M6811_SPSR 0x29 /* SPI Status register */ +#define M6811_SPDR 0x2A /* SPI Data register */ +#define M6811_BAUD 0x2B /* SCI Baud register */ +#define M6811_SCCR1 0x2C /* SCI Control register 1 */ +#define M6811_SCCR2 0x2D /* SCI Control register 2 */ +#define M6811_SCSR 0x2E /* SCI Status register */ +#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ +#define M6811_ADCTL 0x30 /* A/D Control register */ +#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ +#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ +#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ +#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ +#define M6811__RES35 0x35 +#define M6811__RES36 0x36 +#define M6811__RES37 0x37 +#define M6811__RES38 0x38 +#define M6811_OPTION 0x39 /* System Configuration Options */ +#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ +#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ +#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ +#define M6811_INIT 0x3D /* Ram and I/O mapping register */ +#define M6811_TEST1 0x3E /* Factory test control register */ +#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ + + +/* Flags of the CONFIG register (in EEPROM). */ +#define M6811_NOSEC 0x08 /* Security mode disable */ +#define M6811_NOCOP 0x04 /* COP system disable */ +#define M6811_ROMON 0x02 /* Enable on-chip rom */ +#define M6811_EEON 0x01 /* Enable on-chip eeprom */ + +/* Flags of the PPROG register. */ +#define M6811_BYTE 0x10 /* Byte mode */ +#define M6811_ROW 0x08 /* Row mode */ +#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ +#define M6811_EELAT 0x02 /* EEPROM Latch Control */ +#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ + +/* Flags of the PIOC register. */ +#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ +#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ +#define M6811_CWOM 0x20 /* Port C Wire OR mode */ +#define M6811_HNDS 0x10 /* Handshake mode */ +#define M6811_OIN 0x08 /* Output or Input handshaking */ +#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ +#define M6811_EGA 0x02 /* Active Edge for Strobe A */ +#define M6811_INVB 0x01 /* Invert Strobe B */ + +/* Flags of the SCCR1 register. */ +#define M6811_R8 0x80 /* Receive Data bit 8 */ +#define M6811_T8 0x40 /* Transmit data bit 8 */ +#define M6811__SCCR1_5 0x20 /* Unused */ +#define M6811_M 0x10 /* SCI Character length */ +#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ + +/* Flags of the SCCR2 register. */ +#define M6811_TIE 0x80 /* Transmit Interrupt enable */ +#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ +#define M6811_RIE 0x20 /* Receive Interrupt Enable */ +#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ +#define M6811_TE 0x08 /* Transmit Enable */ +#define M6811_RE 0x04 /* Receive Enable */ +#define M6811_RWU 0x02 /* Receiver Wake Up */ +#define M6811_SBK 0x01 /* Send Break */ + +/* Flags of the SCSR register. */ +#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ +#define M6811_TC 0x40 /* Transmit Complete */ +#define M6811_RDRF 0x20 /* Receive Data Register Full */ +#define M6811_IDLE 0x10 /* Idle Line Detect */ +#define M6811_OR 0x08 /* Overrun Error */ +#define M6811_NF 0x04 /* Noise Flag */ +#define M6811_FE 0x02 /* Framing Error */ +#define M6811__SCSR_0 0x01 /* Unused */ + +/* Flags of the BAUD register. */ +#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ +#define M6811__BAUD_6 0x40 /* Not used */ +#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ +#define M6811_SCP0 0x10 +#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ +#define M6811_SCR2 0x04 /* SCI Baud rate select */ +#define M6811_SCR1 0x02 +#define M6811_SCR0 0x01 + +#define M6811_BAUD_DIV_1 (0) +#define M6811_BAUD_DIV_3 (M6811_SCP0) +#define M6811_BAUD_DIV_4 (M6811_SCP1) +#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) + +/* Flags of the SPCR register. */ +#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ +#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ +#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ +#define M6811_MSTR 0x10 /* Master Mode Select */ +#define M6811_CPOL 0x08 /* Clock Polarity */ +#define M6811_CPHA 0x04 /* Clock Phase */ +#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ +#define M6811_SPR0 0x01 + +/* Flags of the SPSR register. */ +#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ +#define M6811_WCOL 0x40 /* Write Collision */ +#define M6811_MODF 0x10 /* Mode Fault */ + +/* Flags of the ADCTL register. */ +#define M6811_CCF 0x80 /* Conversions Complete Flag */ +#define M6811_SCAN 0x20 /* Continuous Scan Control */ +#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ +#define M6811_CD 0x08 /* Channel Select D */ +#define M6811_CC 0x04 /* C */ +#define M6811_CB 0x02 /* B */ +#define M6811_CA 0x01 /* A */ + +/* Flags of the CFORC register. */ +#define M6811_FOC1 0x80 /* Force Output Compare 1 */ +#define M6811_FOC2 0x40 /* 2 */ +#define M6811_FOC3 0x20 /* 3 */ +#define M6811_FOC4 0x10 /* 4 */ +#define M6811_FOC5 0x08 /* 5 */ + +/* Flags of the OC1M register. */ +#define M6811_OC1M7 0x80 /* Output Compare 7 */ +#define M6811_OC1M6 0x40 /* 6 */ +#define M6811_OC1M5 0x20 /* 5 */ +#define M6811_OC1M4 0x10 /* 4 */ +#define M6811_OC1M3 0x08 /* 3 */ + +/* Flags of the OC1D register. */ +#define M6811_OC1D7 0x80 +#define M6811_OC1D6 0x40 +#define M6811_OC1D5 0x20 +#define M6811_OC1D4 0x10 +#define M6811_OC1D3 0x08 + +/* Flags of the TCTL1 register. */ +#define M6811_OM2 0x80 /* Output Mode 2 */ +#define M6811_OL2 0x40 /* Output Level 2 */ +#define M6811_OM3 0x20 +#define M6811_OL3 0x10 +#define M6811_OM4 0x08 +#define M6811_OL4 0x04 +#define M6811_OM5 0x02 +#define M6811_OL5 0x01 + +/* Flags of the TCTL2 register. */ +#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ +#define M6811_EDG1A 0x10 +#define M6811_EDG2B 0x08 /* Input 2 */ +#define M6811_EDG2A 0x04 +#define M6811_EDG3B 0x02 /* Input 3 */ +#define M6811_EDG3A 0x01 + +/* Flags of the TMSK1 register. */ +#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ +#define M6811_OC2I 0x40 /* 2 */ +#define M6811_OC3I 0x20 /* 3 */ +#define M6811_OC4I 0x10 /* 4 */ +#define M6811_OC5I 0x08 /* 5 */ +#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ +#define M6811_IC2I 0x02 /* 2 */ +#define M6811_IC3I 0x01 /* 3 */ + +/* Flags of the TFLG1 register. */ +#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ +#define M6811_OC2F 0x40 /* 2 */ +#define M6811_OC3F 0x20 /* 3 */ +#define M6811_OC4F 0x10 /* 4 */ +#define M6811_OC5F 0x08 /* 5 */ +#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ +#define M6811_IC2F 0x02 /* 2 */ +#define M6811_IC3F 0x01 /* 3 */ + +/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ +#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ +#define M6811_RTII 0x40 /* RTI Interrupt Enable */ +#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ +#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ +#define M6811_PR1 0x02 /* Timer prescaler */ +#define M6811_PR0 0x01 /* Timer prescaler */ +#define M6811_TPR_1 0x00 /* " " prescale div 1 */ +#define M6811_TPR_4 0x01 /* " " prescale div 4 */ +#define M6811_TPR_8 0x02 /* " " prescale div 8 */ +#define M6811_TPR_16 0x03 /* " " prescale div 16 */ + +/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ +#define M6811_TOF 0x80 /* Timer overflow bit */ +#define M6811_RTIF 0x40 /* Read time interrupt flag */ +#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ +#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ + +/* Flags of Pulse Accumulator Control Register (PACTL). */ +#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ +#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ +#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ +#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ +#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ +#define M6811_RTR0 0x01 /* " " " " */ + +/* Flags of the Options register. */ +#define M6811_ADPU 0x80 /* A/D Powerup */ +#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ +#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ +#define M6811_DLY 0x10 /* Stop exit turn on delay */ +#define M6811_CME 0x08 /* Clock Monitor enable */ +#define M6811_CR1 0x02 /* COP timer rate select */ +#define M6811_CR0 0x01 /* COP timer rate select */ + +/* Flags of the HPRIO register. */ +#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ +#define M6811_SMOD 0x40 /* Special Mode */ +#define M6811_MDA 0x20 /* Mode Select A */ +#define M6811_IRV 0x10 /* Internal Read Visibility */ +#define M6811_PSEL3 0x08 /* Priority Select */ +#define M6811_PSEL2 0x04 +#define M6811_PSEL1 0x02 +#define M6811_PSEL0 0x01 + +/* Some insns used by gas to turn relative branches into absolute ones. */ +#define M6811_BRA 0x20 +#define M6811_JMP 0x7e +#define M6811_BSR 0x8d +#define M6811_JSR 0xbd +#define M6812_JMP 0x06 +#define M6812_BSR 0x07 +#define M6812_JSR 0x16 + +/* Instruction code pages. Code page 1 is the default. */ +/*#define M6811_OPCODE_PAGE1 0x00*/ +#define M6811_OPCODE_PAGE2 0x18 +#define M6811_OPCODE_PAGE3 0x1A +#define M6811_OPCODE_PAGE4 0xCD + + +/* 68HC11 operands formats as stored in the m6811_opcode table. These + flags do not correspond to anything in the 68HC11 or 68HC12. + They are only used by GAS to recognize operands. */ +#define M6811_OP_NONE 0 /* No operand */ +#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: * */ +#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: # */ +#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: # */ +#define M6811_OP_IND16 0x0008 /* Indirect abs: */ +#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ +#define M6812_OP_REG 0x0020 /* Register operand 1 */ +#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ + +#define M6811_OP_IX 0x0080 /* Indirect IX: ,x */ +#define M6811_OP_IY 0x0100 /* Indirect IY: ,y */ +#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ +#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ +#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ +#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ +#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ +#define M6812_OP_PAGE 0x4000 /* Page number */ +#define M6811_OP_MASK 0x07FFF +#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ +#define M6811_OP_BITMASK 0x00010000 /* Bitmask: # */ +#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: */ +#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: */ +#define M6811_OP_PAGE1 0x0000 +#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ +#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ +#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ +#define M6811_MAX_OPERANDS 3 /* Max operands: brset */ + +#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ +#define M6812_ACC_IND 0x00800000 /* [D,r] */ +#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ +#define M6812_PRE_DEC 0x02000000 /* n,-r */ +#define M6812_POST_INC 0x04000000 /* n,r+ */ +#define M6812_POST_DEC 0x08000000 /* n,r- */ +#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ +#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ +#define M6812_OP_IDX_P2 0x40000000 + +/* Markers to identify some instructions. */ +#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ +#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ +#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ + +#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ +#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ +#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ +#define M6812_OP_TBCC_MARKER 0x01000000 + +#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ + +#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ +#define M6811_OP_LOW_ADDR 0x02000000 + +#define M68HC12_BANK_VIRT 0x010000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff + + +/* CPU identification. */ +#define cpu6811 0x01 +#define cpu6812 0x02 +#define cpu6812s 0x04 + +/* The opcode table is an array of struct m68hc11_opcode. */ +struct m68hc11_opcode { + const char* name; /* Op-code name */ + long format; + unsigned char size; + unsigned char opcode; + unsigned char cycles_low; + unsigned char cycles_high; + unsigned char set_flags_mask; + unsigned char clr_flags_mask; + unsigned char chg_flags_mask; + unsigned char arch; +}; + +/* Alias definition for 68HC12. */ +struct m68hc12_opcode_alias +{ + const char* name; + const char* translation; + unsigned char size; + unsigned char code1; + unsigned char code2; +}; + +/* The opcode table. The table contains all the opcodes (all pages). + You can't rely on the order. */ +extern const struct m68hc11_opcode m68hc11_opcodes[]; +extern const int m68hc11_num_opcodes; + +/* Alias table for 68HC12. It translates some 68HC11 insn which are not + implemented in 68HC12 but have equivalent translations. */ +extern const struct m68hc12_opcode_alias m68hc12_alias[]; +extern const int m68hc12_num_alias; + +#endif /* _OPCODE_M68HC11_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/m68k.h b/external/gpl3/gdb/dist/include/opcode/m68k.h new file mode 100644 index 000000000000..f7bd8b450e1c --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/m68k.h @@ -0,0 +1,378 @@ +/* Opcode table header for m680[01234]0/m6888[12]/m68851. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, + 2003, 2004, 2006, 2010 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* These are used as bit flags for the arch field in the m68k_opcode + structure. */ +#define _m68k_undef 0 +#define m68000 0x001 +#define m68010 0x002 +#define m68020 0x004 +#define m68030 0x008 +#define m68040 0x010 +#define m68060 0x020 +#define m68881 0x040 +#define m68851 0x080 +#define cpu32 0x100 /* e.g., 68332 */ +#define fido_a 0x200 +#define m68k_mask 0x3ff + +#define mcfmac 0x400 /* ColdFire MAC. */ +#define mcfemac 0x800 /* ColdFire EMAC. */ +#define cfloat 0x1000 /* ColdFire FPU. */ +#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */ + +#define mcfisa_a 0x4000 /* ColdFire ISA_A. */ +#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */ +#define mcfisa_b 0x10000 /* ColdFire ISA_B. */ +#define mcfisa_c 0x20000 /* ColdFire ISA_C. */ +#define mcfusp 0x40000 /* ColdFire USP instructions. */ +#define mcf_mask 0x7e400 + +/* Handy aliases. */ +#define m68040up (m68040 | m68060) +#define m68030up (m68030 | m68040up) +#define m68020up (m68020 | m68030up) +#define m68010up (m68010 | cpu32 | fido_a | m68020up) +#define m68000up (m68000 | m68010up) + +#define mfloat (m68881 | m68040 | m68060) +#define mmmu (m68851 | m68030 | m68040 | m68060) + +/* The structure used to hold information for an opcode. */ + +struct m68k_opcode +{ + /* The opcode name. */ + const char *name; + /* The pseudo-size of the instruction(in bytes). Used to determine + number of bytes necessary to disassemble the instruction. */ + unsigned int size; + /* The opcode itself. */ + unsigned long opcode; + /* The mask used by the disassembler. */ + unsigned long match; + /* The arguments. */ + const char *args; + /* The architectures which support this opcode. */ + unsigned int arch; +}; + +/* The structure used to hold information for an opcode alias. */ + +struct m68k_opcode_alias +{ + /* The alias name. */ + const char *alias; + /* The instruction for which this is an alias. */ + const char *primary; +}; + +/* We store four bytes of opcode for all opcodes because that is the + most any of them need. The actual length of an instruction is + always at least 2 bytes, and is as much longer as necessary to hold + the operands it has. + + The match field is a mask saying which bits must match particular + opcode in order for an instruction to be an instance of that + opcode. + + The args field is a string containing two characters for each + operand of the instruction. The first specifies the kind of + operand; the second, the place it is stored. + + If the first char of args is '.', it indicates that the opcode is + two words. This is only necessary when the match field does not + have any bits set in the second opcode word. Such a '.' is skipped + for operand processing. */ + +/* Kinds of operands: + Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+- + + D data register only. Stored as 3 bits. + A address register only. Stored as 3 bits. + a address register indirect only. Stored as 3 bits. + R either kind of register. Stored as 4 bits. + r either kind of register indirect only. Stored as 4 bits. + At the moment, used only for cas2 instruction. + F floating point coprocessor register only. Stored as 3 bits. + O an offset (or width): immediate data 0-31 or data register. + Stored as 6 bits in special format for BF... insns. + + autoincrement only. Stored as 3 bits (number of the address register). + - autodecrement only. Stored as 3 bits (number of the address register). + Q quick immediate data. Stored as 3 bits. + This matches an immediate operand only when value is in range 1 .. 8. + M moveq immediate data. Stored as 8 bits. + This matches an immediate operand only when value is in range -128..127 + T trap vector immediate data. Stored as 4 bits. + + k K-factor for fmove.p instruction. Stored as a 7-bit constant or + a three bit register offset, depending on the field type. + + # immediate data. Stored in special places (b, w or l) + which say how many bits to store. + ^ immediate data for floating point instructions. Special places + are offset by 2 bytes from '#'... + B pc-relative address, converted to an offset + that is treated as immediate data. + d displacement and register. Stores the register as 3 bits + and stores the displacement in the entire second word. + + C the CCR. No need to store it; this is just for filtering validity. + S the SR. No need to store, just as with CCR. + U the USP. No need to store, just as with CCR. + E the MAC ACC. No need to store, just as with CCR. + e the EMAC ACC[0123]. + G the MAC/EMAC MACSR. No need to store, just as with CCR. + g the EMAC ACCEXT{01,23}. + H the MASK. No need to store, just as with CCR. + i the MAC/EMAC scale factor. + + I Coprocessor ID. Not printed if 1. The Coprocessor ID is always + extracted from the 'd' field of word one, which means that an extended + coprocessor opcode can be skipped using the 'i' place, if needed. + + s System Control register for the floating point coprocessor. + + J Misc register for movec instruction, stored in 'j' format. + Possible values: + 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] + 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] + 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] + 0x003 TC MMU Translation Control [60, 40] + 0x004 ITT0 Instruction Transparent + Translation reg 0 [60, 40] + 0x005 ITT1 Instruction Transparent + Translation reg 1 [60, 40] + 0x006 DTT0 Data Transparent + Translation reg 0 [60, 40] + 0x007 DTT1 Data Transparent + Translation reg 1 [60, 40] + 0x008 BUSCR Bus Control Register [60] + 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] + 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] + 0x802 CAAR Cache Address Register [ 30, 20] + 0x803 MSP Master Stack Pointer [ 40, 30, 20] + 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] + 0x805 MMUSR MMU Status reg [ 40] + 0x806 URP User Root Pointer [60, 40] + 0x807 SRP Supervisor Root Pointer [60, 40] + 0x808 PCR Processor Configuration reg [60] + 0xC00 ROMBAR ROM Base Address Register [520X] + 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] + 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] + 0xC0F MBAR0 RAM Base Address Register 0 [520X] + 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] + 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] + + L Register list of the type d0-d7/a0-a7 etc. + (New! Improved! Can also hold fp0-fp7, as well!) + The assembler tries to see if the registers match the insn by + looking at where the insn wants them stored. + + l Register list like L, but with all the bits reversed. + Used for going the other way. . . + + c cache identifier which may be "nc" for no cache, "ic" + for instruction cache, "dc" for data cache, or "bc" + for both caches. Used in cinv and cpush. Always + stored in position "d". + + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + + The remainder are all stored as 6 bits using an address mode and a + register number; they differ in which addressing modes they match. + + * all (modes 0-6,7.0-4) + ~ alterable memory (modes 2-6,7.0,7.1) + (not 0,1,7.2-4) + % alterable (modes 0-6,7.0,7.1) + (not 7.2-4) + ; data (modes 0,2-6,7.0-4) + (not 1) + @ data, but not immediate (modes 0,2-6,7.0-3) + (not 1,7.4) + ! control (modes 2,5,6,7.0-3) + (not 0,1,3,4,7.4) + & alterable control (modes 2,5,6,7.0,7.1) + (not 0,1,3,4,7.2-4) + $ alterable data (modes 0,2-6,7.0,7.1) + (not 1,7.2-4) + ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) + (not 1,3,4,7.2-4) + / control, or data register (modes 0,2,5,6,7.0-3) + (not 1,3,4,7.4) + > *save operands (modes 2,4,5,6,7.0,7.1) + (not 0,1,3,7.2-4) + < *restore operands (modes 2,3,5,6,7.0-3) + (not 0,1,4,7.4) + + coldfire move operands: + m (modes 0-4) + n (modes 5,7.2) + o (modes 6,7.0,7.1,7.3,7.4) + p (modes 0-5) + + coldfire bset/bclr/btst/mulsl/mulul operands: + q (modes 0,2-5) + v (modes 0,2-5,7.0,7.1) + b (modes 0,2-5,7.2) + w (modes 2-5,7.2) + y (modes 2,5) + z (modes 2,5,7.2) + x mov3q immediate operand. + j coprocessor ET operand. + K coprocessor command number. + 4 (modes 2,3,4,5) + */ + +/* For the 68851: */ +/* I didn't use much imagination in choosing the + following codes, so many of them aren't very + mnemonic. -rab + + 0 32 bit pmmu register + Possible values: + 000 TC Translation Control Register (68030, 68851) + + 1 16 bit pmmu register + 111 AC Access Control (68851) + + 2 8 bit pmmu register + 100 CAL Current Access Level (68851) + 101 VAL Validate Access Level (68851) + 110 SCC Stack Change Control (68851) + + 3 68030-only pmmu registers (32 bit) + 010 TT0 Transparent Translation reg 0 + (aka Access Control reg 0 -- AC0 -- on 68ec030) + 011 TT1 Transparent Translation reg 1 + (aka Access Control reg 1 -- AC1 -- on 68ec030) + + W wide pmmu registers + Possible values: + 001 DRP Dma Root Pointer (68851) + 010 SRP Supervisor Root Pointer (68030, 68851) + 011 CRP Cpu Root Pointer (68030, 68851) + + f function code register (68030, 68851) + 0 SFC + 1 DFC + + V VAL register only (68851) + + X BADx, BACx (16 bit) + 100 BAD Breakpoint Acknowledge Data (68851) + 101 BAC Breakpoint Acknowledge Control (68851) + + Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) + Z PCSR (68851) + + | memory (modes 2-6, 7.*) + + t address test level (68030 only) + Stored as 3 bits, range 0-7. + Also used for breakpoint instruction now. + +*/ + +/* Places to put an operand, for non-general operands: + Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ + + s source, low bits of first word. + d dest, shifted 9 in first word + 1 second word, shifted 12 + 2 second word, shifted 6 + 3 second word, shifted 0 + 4 third word, shifted 12 + 5 third word, shifted 6 + 6 third word, shifted 0 + 7 second word, shifted 7 + 8 second word, shifted 10 + 9 second word, shifted 5 + E second word, shifted 9 + D store in both place 1 and place 3; for divul and divsl. + B first word, low byte, for branch displacements + W second word (entire), for branch displacements + L second and third words (entire), for branch displacements + (also overloaded for move16) + b second word, low byte + w second word (entire) [variable word/long branch offset for dbra] + W second word (entire) (must be signed 16 bit value) + l second and third word (entire) + g variable branch offset for bra and similar instructions. + The place to store depends on the magnitude of offset. + t store in both place 7 and place 8; for floating point operations + c branch offset for cpBcc operations. + The place to store is word two if bit six of word one is zero, + and words two and three if bit six of word one is one. + i Increment by two, to skip over coprocessor extended operands. Only + works with the 'I' format. + k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. + Also used for dynamic fmovem instruction. + C floating point coprocessor constant - 7 bits. Also used for static + K-factors... + j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word + + Places to put operand, for general operands: + d destination, shifted 6 bits in first word + b source, at low bit of first word, and immediate uses one byte + w source, at low bit of first word, and immediate uses two bytes + l source, at low bit of first word, and immediate uses four bytes + s source, at low bit of first word. + Used sometimes in contexts where immediate is not allowed anyway. + f single precision float, low bit of 1st word, immediate uses 4 bytes + F double precision float, low bit of 1st word, immediate uses 8 bytes + x extended precision float, low bit of 1st word, immediate uses 12 bytes + p packed float, low bit of 1st word, immediate uses 12 bytes + G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) + H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) + F EMAC ACCx + f EMAC ACCy + I MAC/EMAC scale factor + / Like 's', but set 2nd word, bit 5 if trailing_ampersand set + ] first word, bit 10 +*/ + +extern const struct m68k_opcode m68k_opcodes[]; +extern const struct m68k_opcode_alias m68k_opcode_aliases[]; + +extern const int m68k_numopcodes, m68k_numaliases; + +/* end of m68k-opcode.h */ diff --git a/external/gpl3/gdb/dist/include/opcode/m88k.h b/external/gpl3/gdb/dist/include/opcode/m88k.h new file mode 100644 index 000000000000..739c0e90af88 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/m88k.h @@ -0,0 +1,455 @@ +/* Table of opcodes for the Motorola M88k family. + Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010 + Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* + * Disassembler Instruction Table + * + * The first field of the table is the opcode field. If an opcode + * is specified which has any non-opcode bits on, a system error + * will occur when the system attempts the install it into the + * instruction table. The second parameter is a pointer to the + * instruction mnemonic. Each operand is specified by offset, width, + * and type. The offset is the bit number of the least significant + * bit of the operand with bit 0 being the least significant bit of + * the instruction. The width is the number of bits used to specify + * the operand. The type specifies the output format to be used for + * the operand. The valid formats are: register, register indirect, + * hex constant, and bit field specification. The last field is a + * pointer to the next instruction in the linked list. These pointers + * are initialized by init_disasm(). + * + * Revision History + * + * Revision 1.0 11/08/85 Creation date + * 1.1 02/05/86 Updated instruction mnemonic table MD + * 1.2 06/16/86 Updated SIM_FLAGS for floating point + * 1.3 09/20/86 Updated for new encoding + * 05/11/89 R. Trawick adapted from Motorola disassembler + */ + +#include + +/* Define the number of bits in the primary opcode field of the instruction, + the destination field, the source 1 and source 2 fields. */ + +/* Size of opcode field. */ +#define OP 8 + +/* Size of destination. */ +#define DEST 6 + +/* Size of source1. */ +#define SOURCE1 6 + +/* Size of source2. */ +#define SOURCE2 6 + +/* Number of registers. */ +#define REGs 32 + +/* Type definitions. */ + +typedef unsigned int UINT; +#define WORD long +#define FLAG unsigned +#define STATE short + +/* The next four equates define the priorities that the various classes + * of instructions have regarding writing results back into registers and + * signalling exceptions. */ + +/* PMEM is also defined in on Delta 88's. Sigh! */ +#undef PMEM + +/* Integer priority. */ +#define PINT 0 + +/* Floating point priority. */ +#define PFLT 1 + +/* Memory priority. */ +#define PMEM 2 + +/* Not applicable, instruction doesn't write to regs. */ +#define NA 3 + +/* Highest of these priorities. */ +#define HIPRI 3 + +/* The instruction registers are an artificial mechanism to speed up + * simulator execution. In the real processor, an instruction register + * is 32 bits wide. In the simulator, the 32 bit instruction is kept in + * a structure field called rawop, and the instruction is partially decoded, + * and split into various fields and flags which make up the other fields + * of the structure. + * The partial decode is done when the instructions are initially loaded + * into simulator memory. The simulator code memory is not an array of + * 32 bit words, but is an array of instruction register structures. + * Yes this wastes memory, but it executes much quicker. + */ + +struct IR_FIELDS +{ + unsigned op:OP, + dest: DEST, + src1: SOURCE1, + src2: SOURCE2; + int ltncy, + extime, + /* Writeback priority. */ + wb_pri; + /* Immediate size. */ + unsigned imm_flags:2, + /* Register source 1 used. */ + rs1_used:1, + /* Register source 2 used. */ + rs2_used:1, + /* Register source/dest. used. */ + rsd_used:1, + /* Complement. */ + c_flag:1, + /* Upper half word. */ + u_flag:1, + /* Execute next. */ + n_flag:1, + /* Uses writeback slot. */ + wb_flag:1, + /* Dest size. */ + dest_64:1, + /* Source 1 size. */ + s1_64:1, + /* Source 2 size. */ + s2_64:1, + scale_flag:1, + /* Scaled register. */ + brk_flg:1; +}; + +struct mem_segs +{ + /* Pointer (returned by calloc) to segment. */ + struct mem_wrd *seg; + + /* Base load address from file headers. */ + unsigned long baseaddr; + + /* Ending address of segment. */ + unsigned long endaddr; + + /* Segment control flags (none defined). */ + int flags; +}; + +#define MAXSEGS (10) /* max number of segment allowed */ +#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ + +#if 0 +#define BRK_RD (0x01) /* break on memory read */ +#define BRK_WR (0x02) /* break on memory write */ +#define BRK_EXEC (0x04) /* break on execution */ +#define BRK_CNT (0x08) /* break on terminal count */ +#endif + +struct mem_wrd +{ + /* Simulator instruction break down. */ + struct IR_FIELDS opcode; + union { + /* Memory element break down. */ + unsigned long l; + unsigned short s[2]; + unsigned char c[4]; + } mem; +}; + +/* Size of each 32 bit memory model. */ +#define MEMWRDSIZE (sizeof (struct mem_wrd)) + +extern struct mem_segs memory[]; +extern struct PROCESSOR m78000; + +struct PROCESSOR +{ + unsigned WORD + /* Execute instruction pointer. */ + ip, + /* Vector base register. */ + vbr, + /* Processor status register. */ + psr; + + /* Source 1. */ + WORD S1bus, + /* Source 2. */ + S2bus, + /* Destination. */ + Dbus, + /* Data address bus. */ + DAbus, + ALU, + /* Data registers. */ + Regs[REGs], + /* Max clocks before reg is available. */ + time_left[REGs], + /* Writeback priority of reg. */ + wb_pri[REGs], + /* Integer unit control regs. */ + SFU0_regs[REGs], + /* Floating point control regs. */ + SFU1_regs[REGs], + Scoreboard[REGs], + Vbr; + unsigned WORD scoreboard, + Psw, + Tpsw; + /* Waiting for a jump instruction. */ + FLAG jump_pending:1; +}; + +/* Size of immediate field. */ + +#define i26bit 1 +#define i16bit 2 +#define i10bit 3 + +/* Definitions for fields in psr. */ + +#define psr_mode 31 +#define psr_rbo 30 +#define psr_ser 29 +#define psr_carry 28 +#define psr_sf7m 11 +#define psr_sf6m 10 +#define psr_sf5m 9 +#define psr_sf4m 8 +#define psr_sf3m 7 +#define psr_sf2m 6 +#define psr_sf1m 5 +#define psr_mam 4 +#define psr_inm 3 +#define psr_exm 2 +#define psr_trm 1 +#define psr_ovfm 0 + +/* The 1 clock operations. */ + +#define ADDU 1 +#define ADDC 2 +#define ADDUC 3 +#define ADD 4 + +#define SUBU ADD+1 +#define SUBB ADD+2 +#define SUBUB ADD+3 +#define SUB ADD+4 + +#define AND_ ADD+5 +#define OR ADD+6 +#define XOR ADD+7 +#define CMP ADD+8 + +/* Loads. */ + +#define LDAB CMP+1 +#define LDAH CMP+2 +#define LDA CMP+3 +#define LDAD CMP+4 + +#define LDB LDAD+1 +#define LDH LDAD+2 +#define LD LDAD+3 +#define LDD LDAD+4 +#define LDBU LDAD+5 +#define LDHU LDAD+6 + +/* Stores. */ + +#define STB LDHU+1 +#define STH LDHU+2 +#define ST LDHU+3 +#define STD LDHU+4 + +/* Exchange. */ + +#define XMEMBU LDHU+5 +#define XMEM LDHU+6 + +/* Branches. */ + +#define JSR STD+1 +#define BSR STD+2 +#define BR STD+3 +#define JMP STD+4 +#define BB1 STD+5 +#define BB0 STD+6 +#define RTN STD+7 +#define BCND STD+8 + +/* Traps. */ + +#define TB1 BCND+1 +#define TB0 BCND+2 +#define TCND BCND+3 +#define RTE BCND+4 +#define TBND BCND+5 + +/* Misc. */ + +#define MUL TBND + 1 +#define DIV MUL +2 +#define DIVU MUL +3 +#define MASK MUL +4 +#define FF0 MUL +5 +#define FF1 MUL +6 +#define CLR MUL +7 +#define SET MUL +8 +#define EXT MUL +9 +#define EXTU MUL +10 +#define MAK MUL +11 +#define ROT MUL +12 + +/* Control register manipulations. */ + +#define LDCR ROT +1 +#define STCR ROT +2 +#define XCR ROT +3 + +#define FLDCR ROT +4 +#define FSTCR ROT +5 +#define FXCR ROT +6 + +#define NOP XCR +1 + +/* Floating point instructions. */ + +#define FADD NOP +1 +#define FSUB NOP +2 +#define FMUL NOP +3 +#define FDIV NOP +4 +#define FSQRT NOP +5 +#define FCMP NOP +6 +#define FIP NOP +7 +#define FLT NOP +8 +#define INT NOP +9 +#define NINT NOP +10 +#define TRNC NOP +11 +#define FLDC NOP +12 +#define FSTC NOP +13 +#define FXC NOP +14 + +#define UEXT(src,off,wid) \ + ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) + +#define SEXT(src,off,wid) \ + (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) + +#define MAKE(src,off,wid) \ + ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) + +#define opword(n) (unsigned long) (memaddr->mem.l) + +/* Constants and masks. */ + +#define SFU0 0x80000000 +#define SFU1 0x84000000 +#define SFU7 0x9c000000 +#define RRI10 0xf0000000 +#define RRR 0xf4000000 +#define SFUMASK 0xfc00ffe0 +#define RRRMASK 0xfc00ffe0 +#define RRI10MASK 0xfc00fc00 +#define DEFMASK 0xfc000000 +#define CTRL 0x0000f000 +#define CTRLMASK 0xfc00f800 + +/* Operands types. */ + +enum operand_type +{ + HEX = 1, + REG = 2, + CONT = 3, + IND = 3, + BF = 4, + /* Scaled register. */ + REGSC = 5, + /* Control register. */ + CRREG = 6, + /* Floating point control register. */ + FCRREG = 7, + PCREL = 8, + CONDMASK = 9, + /* Extended register. */ + XREG = 10, + /* Decimal. */ + DEC = 11 +}; + +/* Hashing specification. */ + +#define HASHVAL 79 + +/* Structure templates. */ + +typedef struct +{ + unsigned int offset; + unsigned int width; + enum operand_type type; +} OPSPEC; + +struct SIM_FLAGS +{ + int ltncy, /* latency (max number of clocks needed to execute). */ + extime, /* execution time (min number of clocks needed to execute). */ + wb_pri; /* writeback slot priority. */ + unsigned op:OP, /* simulator version of opcode. */ + imm_flags:2, /* 10,16 or 26 bit immediate flags. */ + rs1_used:1, /* register source 1 used. */ + rs2_used:1, /* register source 2 used. */ + rsd_used:1, /* register source/dest used. */ + c_flag:1, /* complement. */ + u_flag:1, /* upper half word. */ + n_flag:1, /* execute next. */ + wb_flag:1, /* uses writeback slot. */ + dest_64:1, /* double precision dest. */ + s1_64:1, /* double precision source 1. */ + s2_64:1, /* double precision source 2. */ + scale_flag:1; /* register is scaled. */ +}; + +typedef struct INSTRUCTAB { + unsigned int opcode; + char *mnemonic; + OPSPEC op1,op2,op3; + struct SIM_FLAGS flgs; +} INSTAB; + + +#define NO_OPERAND {0,0,0} + +extern const INSTAB instructions[]; + +/* + * Local Variables: + * fill-column: 131 + * End: + */ diff --git a/external/gpl3/gdb/dist/include/opcode/mips.h b/external/gpl3/gdb/dist/include/opcode/mips.h new file mode 100644 index 000000000000..0685baba09dd --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/mips.h @@ -0,0 +1,1153 @@ +/* mips.h. Mips opcode list for GDB, the GNU debugger. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, + 2003, 2004, 2005, 2008, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _MIPS_H_ +#define _MIPS_H_ + +/* These are bit masks and shift counts to use to access the various + fields of an instruction. To retrieve the X field of an + instruction, use the expression + (i >> OP_SH_X) & OP_MASK_X + To set the same field (to j), use + i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) + + Make sure you use fields that are appropriate for the instruction, + of course. + + The 'i' format uses OP, RS, RT and IMMEDIATE. + + The 'j' format uses OP and TARGET. + + The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. + + The 'b' format uses OP, RS, RT and DELTA. + + The floating point 'i' format uses OP, RS, RT and IMMEDIATE. + + The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. + + A breakpoint instruction uses OP, CODE and SPEC (10 bits of the + breakpoint instruction are not defined; Kane says the breakpoint + code field in BREAK is 20 bits; yet MIPS assemblers and debuggers + only use ten bits). An optional two-operand form of break/sdbbp + allows the lower ten bits to be set too, and MIPS32 and later + architectures allow 20 bits to be set with a signal operand + (using CODE20). + + The syscall instruction uses CODE20. + + The general coprocessor instructions use COPZ. */ + +#define OP_MASK_OP 0x3f +#define OP_SH_OP 26 +#define OP_MASK_RS 0x1f +#define OP_SH_RS 21 +#define OP_MASK_FR 0x1f +#define OP_SH_FR 21 +#define OP_MASK_FMT 0x1f +#define OP_SH_FMT 21 +#define OP_MASK_BCC 0x7 +#define OP_SH_BCC 18 +#define OP_MASK_CODE 0x3ff +#define OP_SH_CODE 16 +#define OP_MASK_CODE2 0x3ff +#define OP_SH_CODE2 6 +#define OP_MASK_RT 0x1f +#define OP_SH_RT 16 +#define OP_MASK_FT 0x1f +#define OP_SH_FT 16 +#define OP_MASK_CACHE 0x1f +#define OP_SH_CACHE 16 +#define OP_MASK_RD 0x1f +#define OP_SH_RD 11 +#define OP_MASK_FS 0x1f +#define OP_SH_FS 11 +#define OP_MASK_PREFX 0x1f +#define OP_SH_PREFX 11 +#define OP_MASK_CCC 0x7 +#define OP_SH_CCC 8 +#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ +#define OP_SH_CODE20 6 +#define OP_MASK_SHAMT 0x1f +#define OP_SH_SHAMT 6 +#define OP_MASK_FD 0x1f +#define OP_SH_FD 6 +#define OP_MASK_TARGET 0x3ffffff +#define OP_SH_TARGET 0 +#define OP_MASK_COPZ 0x1ffffff +#define OP_SH_COPZ 0 +#define OP_MASK_IMMEDIATE 0xffff +#define OP_SH_IMMEDIATE 0 +#define OP_MASK_DELTA 0xffff +#define OP_SH_DELTA 0 +#define OP_MASK_FUNCT 0x3f +#define OP_SH_FUNCT 0 +#define OP_MASK_SPEC 0x3f +#define OP_SH_SPEC 0 +#define OP_SH_LOCC 8 /* FP condition code. */ +#define OP_SH_HICC 18 /* FP condition code. */ +#define OP_MASK_CC 0x7 +#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ +#define OP_MASK_COP1NORM 0x1 /* a single bit. */ +#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ +#define OP_MASK_COP1SPEC 0xf +#define OP_MASK_COP1SCLR 0x4 +#define OP_MASK_COP1CMP 0x3 +#define OP_SH_COP1CMP 4 +#define OP_SH_FORMAT 21 /* FP short format field. */ +#define OP_MASK_FORMAT 0x7 +#define OP_SH_TRUE 16 +#define OP_MASK_TRUE 0x1 +#define OP_SH_GE 17 +#define OP_MASK_GE 0x01 +#define OP_SH_UNSIGNED 16 +#define OP_MASK_UNSIGNED 0x1 +#define OP_SH_HINT 16 +#define OP_MASK_HINT 0x1f +#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ +#define OP_MASK_MMI 0x3f +#define OP_SH_MMISUB 6 +#define OP_MASK_MMISUB 0x1f +#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ +#define OP_SH_PERFREG 1 +#define OP_SH_SEL 0 /* Coprocessor select field. */ +#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ +#define OP_SH_CODE19 6 /* 19 bit wait code. */ +#define OP_MASK_CODE19 0x7ffff +#define OP_SH_ALN 21 +#define OP_MASK_ALN 0x7 +#define OP_SH_VSEL 21 +#define OP_MASK_VSEL 0x1f +#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, + but 0x8-0xf don't select bytes. */ +#define OP_SH_VECBYTE 22 +#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ +#define OP_SH_VECALIGN 21 +#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ +#define OP_SH_INSMSB 11 +#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ +#define OP_SH_EXTMSBD 11 + +/* MIPS DSP ASE */ +#define OP_SH_DSPACC 11 +#define OP_MASK_DSPACC 0x3 +#define OP_SH_DSPACC_S 21 +#define OP_MASK_DSPACC_S 0x3 +#define OP_SH_DSPSFT 20 +#define OP_MASK_DSPSFT 0x3f +#define OP_SH_DSPSFT_7 19 +#define OP_MASK_DSPSFT_7 0x7f +#define OP_SH_SA3 21 +#define OP_MASK_SA3 0x7 +#define OP_SH_SA4 21 +#define OP_MASK_SA4 0xf +#define OP_SH_IMM8 16 +#define OP_MASK_IMM8 0xff +#define OP_SH_IMM10 16 +#define OP_MASK_IMM10 0x3ff +#define OP_SH_WRDSP 11 +#define OP_MASK_WRDSP 0x3f +#define OP_SH_RDDSP 16 +#define OP_MASK_RDDSP 0x3f +#define OP_SH_BP 11 +#define OP_MASK_BP 0x3 + +/* MIPS MT ASE */ +#define OP_SH_MT_U 5 +#define OP_MASK_MT_U 0x1 +#define OP_SH_MT_H 4 +#define OP_MASK_MT_H 0x1 +#define OP_SH_MTACC_T 18 +#define OP_MASK_MTACC_T 0x3 +#define OP_SH_MTACC_D 13 +#define OP_MASK_MTACC_D 0x3 + +#define OP_OP_COP0 0x10 +#define OP_OP_COP1 0x11 +#define OP_OP_COP2 0x12 +#define OP_OP_COP3 0x13 +#define OP_OP_LWC1 0x31 +#define OP_OP_LWC2 0x32 +#define OP_OP_LWC3 0x33 /* a.k.a. pref */ +#define OP_OP_LDC1 0x35 +#define OP_OP_LDC2 0x36 +#define OP_OP_LDC3 0x37 /* a.k.a. ld */ +#define OP_OP_SWC1 0x39 +#define OP_OP_SWC2 0x3a +#define OP_OP_SWC3 0x3b +#define OP_OP_SDC1 0x3d +#define OP_OP_SDC2 0x3e +#define OP_OP_SDC3 0x3f /* a.k.a. sd */ + +/* Values in the 'VSEL' field. */ +#define MDMX_FMTSEL_IMM_QH 0x1d +#define MDMX_FMTSEL_IMM_OB 0x1e +#define MDMX_FMTSEL_VEC_QH 0x15 +#define MDMX_FMTSEL_VEC_OB 0x16 + +/* UDI */ +#define OP_SH_UDI1 6 +#define OP_MASK_UDI1 0x1f +#define OP_SH_UDI2 6 +#define OP_MASK_UDI2 0x3ff +#define OP_SH_UDI3 6 +#define OP_MASK_UDI3 0x7fff +#define OP_SH_UDI4 6 +#define OP_MASK_UDI4 0xfffff + +/* Octeon */ +#define OP_SH_BBITIND 16 +#define OP_MASK_BBITIND 0x1f +#define OP_SH_CINSPOS 6 +#define OP_MASK_CINSPOS 0x1f +#define OP_SH_CINSLM1 11 +#define OP_MASK_CINSLM1 0x1f +#define OP_SH_SEQI 6 +#define OP_MASK_SEQI 0x3ff + +/* Loongson */ +#define OP_SH_OFFSET_A 6 +#define OP_MASK_OFFSET_A 0xff +#define OP_SH_OFFSET_B 3 +#define OP_MASK_OFFSET_B 0xff +#define OP_SH_OFFSET_C 6 +#define OP_MASK_OFFSET_C 0x1ff +#define OP_SH_RZ 0 +#define OP_MASK_RZ 0x1f +#define OP_SH_FZ 0 +#define OP_MASK_FZ 0x1f + +/* This structure holds information for a particular instruction. */ + +struct mips_opcode +{ + /* The name of the instruction. */ + const char *name; + /* A string describing the arguments for this instruction. */ + const char *args; + /* The basic opcode for the instruction. When assembling, this + opcode is modified by the arguments to produce the actual opcode + that is used. If pinfo is INSN_MACRO, then this is 0. */ + unsigned long match; + /* If pinfo is not INSN_MACRO, then this is a bit mask for the + relevant portions of the opcode when disassembling. If the + actual opcode anded with the match field equals the opcode field, + then we have found the correct instruction. If pinfo is + INSN_MACRO, then this field is the macro identifier. */ + unsigned long mask; + /* For a macro, this is INSN_MACRO. Otherwise, it is a collection + of bits describing the instruction, notably any relevant hazard + information. */ + unsigned long pinfo; + /* A collection of additional bits describing the instruction. */ + unsigned long pinfo2; + /* A collection of bits describing the instruction sets of which this + instruction or macro is a member. */ + unsigned long membership; +}; + +/* These are the characters which may appear in the args field of an + instruction. They appear in the order in which the fields appear + when the instruction is used. Commas and parentheses in the args + string are ignored when assembling, and written into the output + when disassembling. + + Each of these characters corresponds to a mask field defined above. + + "1" 5 bit sync type (OP_*_SHAMT) + "<" 5 bit shift amount (OP_*_SHAMT) + ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) + "a" 26 bit target address (OP_*_TARGET) + "b" 5 bit base register (OP_*_RS) + "c" 10 bit breakpoint code (OP_*_CODE) + "d" 5 bit destination register specifier (OP_*_RD) + "h" 5 bit prefx hint (OP_*_PREFX) + "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) + "j" 16 bit signed immediate (OP_*_DELTA) + "k" 5 bit cache opcode in target register position (OP_*_CACHE) + Also used for immediate operands in vr5400 vector insns. + "o" 16 bit signed offset (OP_*_DELTA) + "p" 16 bit PC relative branch target address (OP_*_DELTA) + "q" 10 bit extra breakpoint code (OP_*_CODE2) + "r" 5 bit same register used as both source and target (OP_*_RS) + "s" 5 bit source register specifier (OP_*_RS) + "t" 5 bit target register (OP_*_RT) + "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) + "v" 5 bit same register used as both source and destination (OP_*_RS) + "w" 5 bit same register used as both target and destination (OP_*_RT) + "U" 5 bit same destination register in both OP_*_RD and OP_*_RT + (used by clo and clz) + "C" 25 bit coprocessor function code (OP_*_COPZ) + "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) + "J" 19 bit wait function code (OP_*_CODE19) + "x" accept and ignore register name + "z" must be zero register + "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) + "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes + LSB (OP_*_SHAMT). + Enforces: 0 <= pos < 32. + "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + + Floating point instructions: + "D" 5 bit destination register (OP_*_FD) + "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) + "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) + "S" 5 bit fs source 1 register (OP_*_FS) + "T" 5 bit ft source 2 register (OP_*_FT) + "R" 5 bit fr source 3 register (OP_*_FR) + "V" 5 bit same register used as floating source and destination (OP_*_FS) + "W" 5 bit same register used as floating target and destination (OP_*_FT) + + Coprocessor instructions: + "E" 5 bit target register (OP_*_RT) + "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) + "P" 5 bit performance-monitor register (OP_*_PERFREG) + "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) + see also "k" above + "+D" Combined destination register ("G") and sel ("H") for CP0 ops, + for pretty-printing in disassembly only. + + Macro instructions: + "A" General 32 bit expression + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). + "F" 64 bit floating point constant in .rdata + "L" 64 bit floating point constant in .lit8 + "f" 32 bit floating point constant + "l" 32 bit floating point constant in .lit4 + + MDMX instruction operands (note that while these use the FP register + fields, they accept both $fN and $vN names for the registers): + "O" MDMX alignment offset (OP_*_ALN) + "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" MDMX destination register (OP_*_FD) + "Y" MDMX source register (OP_*_FS) + "Z" MDMX source register (OP_*_FT) + + DSP ASE usage: + "2" 2 bit unsigned immediate for byte align (OP_*_BP) + "3" 3 bit unsigned immediate (OP_*_SA3) + "4" 4 bit unsigned immediate (OP_*_SA4) + "5" 8 bit unsigned immediate (OP_*_IMM8) + "6" 5 bit unsigned immediate (OP_*_RS) + "7" 2 bit dsp accumulator register (OP_*_DSPACC) + "8" 6 bit unsigned immediate (OP_*_WRDSP) + "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) + "0" 6 bit signed immediate (OP_*_DSPSFT) + ":" 7 bit signed immediate (OP_*_DSPSFT_7) + "'" 6 bit unsigned immediate (OP_*_RDDSP) + "@" 10 bit signed immediate (OP_*_IMM10) + + MT ASE usage: + "!" 1 bit usermode flag (OP_*_MT_U) + "$" 1 bit load high flag (OP_*_MT_H) + "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) + "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) + "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) + "+t" 5 bit coprocessor 0 destination register (OP_*_RT) + "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only + + UDI immediates: + "+1" UDI immediate bits 6-10 + "+2" UDI immediate bits 6-15 + "+3" UDI immediate bits 6-20 + "+4" UDI immediate bits 6-25 + + Octeon: + "+x" Bit index field of bbit. Enforces: 0 <= index < 32. + "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, + otherwise skips to next candidate. + "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. + "+P" Position field of cins/exts aliasing cins32/exts32. Matches if + 32 <= pos < 64, otherwise skips to next candidate. + "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. + "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32. + "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing + cint32/exts32. Enforces non-negative value and that + pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous + position field is "+p" or "+P". + + Loongson-3A: + "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) + "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) + "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) + "+z" 5-bit rz register (OP_*_RZ) + "+Z" 5-bit fz register (OP_*_FZ) + + Other: + "()" parens surrounding optional value + "," separates operands + "[]" brackets around index for vector-op scalar operand specifier (vr5400) + "+" Start of extension sequence. + + Characters used so far, for quick reference when adding more: + "1234567890" + "%[]<>(),+:'@!$*&" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ" + "abcdefghijklopqrstuvwxz" + + Extension character sequences used so far ("+" followed by the + following), for quick reference when adding more: + "1234" + "ABCDEFGHIPQSTXZ" + "abcpstxz" +*/ + +/* These are the bits which may be set in the pinfo field of an + instructions, if it is not equal to INSN_MACRO. */ + +/* Modifies the general purpose register in OP_*_RD. */ +#define INSN_WRITE_GPR_D 0x00000001 +/* Modifies the general purpose register in OP_*_RT. */ +#define INSN_WRITE_GPR_T 0x00000002 +/* Modifies general purpose register 31. */ +#define INSN_WRITE_GPR_31 0x00000004 +/* Modifies the floating point register in OP_*_FD. */ +#define INSN_WRITE_FPR_D 0x00000008 +/* Modifies the floating point register in OP_*_FS. */ +#define INSN_WRITE_FPR_S 0x00000010 +/* Modifies the floating point register in OP_*_FT. */ +#define INSN_WRITE_FPR_T 0x00000020 +/* Reads the general purpose register in OP_*_RS. */ +#define INSN_READ_GPR_S 0x00000040 +/* Reads the general purpose register in OP_*_RT. */ +#define INSN_READ_GPR_T 0x00000080 +/* Reads the floating point register in OP_*_FS. */ +#define INSN_READ_FPR_S 0x00000100 +/* Reads the floating point register in OP_*_FT. */ +#define INSN_READ_FPR_T 0x00000200 +/* Reads the floating point register in OP_*_FR. */ +#define INSN_READ_FPR_R 0x00000400 +/* Modifies coprocessor condition code. */ +#define INSN_WRITE_COND_CODE 0x00000800 +/* Reads coprocessor condition code. */ +#define INSN_READ_COND_CODE 0x00001000 +/* TLB operation. */ +#define INSN_TLB 0x00002000 +/* Reads coprocessor register other than floating point register. */ +#define INSN_COP 0x00004000 +/* Instruction loads value from memory, requiring delay. */ +#define INSN_LOAD_MEMORY_DELAY 0x00008000 +/* Instruction loads value from coprocessor, requiring delay. */ +#define INSN_LOAD_COPROC_DELAY 0x00010000 +/* Instruction has unconditional branch delay slot. */ +#define INSN_UNCOND_BRANCH_DELAY 0x00020000 +/* Instruction has conditional branch delay slot. */ +#define INSN_COND_BRANCH_DELAY 0x00040000 +/* Conditional branch likely: if branch not taken, insn nullified. */ +#define INSN_COND_BRANCH_LIKELY 0x00080000 +/* Moves to coprocessor register, requiring delay. */ +#define INSN_COPROC_MOVE_DELAY 0x00100000 +/* Loads coprocessor register from memory, requiring delay. */ +#define INSN_COPROC_MEMORY_DELAY 0x00200000 +/* Reads the HI register. */ +#define INSN_READ_HI 0x00400000 +/* Reads the LO register. */ +#define INSN_READ_LO 0x00800000 +/* Modifies the HI register. */ +#define INSN_WRITE_HI 0x01000000 +/* Modifies the LO register. */ +#define INSN_WRITE_LO 0x02000000 +/* Takes a trap (easier to keep out of delay slot). */ +#define INSN_TRAP 0x04000000 +/* Instruction stores value into memory. */ +#define INSN_STORE_MEMORY 0x08000000 +/* Instruction uses single precision floating point. */ +#define FP_S 0x10000000 +/* Instruction uses double precision floating point. */ +#define FP_D 0x20000000 +/* Instruction is part of the tx39's integer multiply family. */ +#define INSN_MULT 0x40000000 +/* Instruction synchronize shared memory. */ +#define INSN_SYNC 0x80000000 +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + +/* These are the bits which may be set in the pinfo2 field of an + instruction. */ + +/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ +#define INSN2_ALIAS 0x00000001 +/* Instruction reads MDMX accumulator. */ +#define INSN2_READ_MDMX_ACC 0x00000002 +/* Instruction writes MDMX accumulator. */ +#define INSN2_WRITE_MDMX_ACC 0x00000004 +/* Macro uses single-precision floating-point instructions. This should + only be set for macros. For instructions, FP_S in pinfo carries the + same information. */ +#define INSN2_M_FP_S 0x00000008 +/* Macro uses double-precision floating-point instructions. This should + only be set for macros. For instructions, FP_D in pinfo carries the + same information. */ +#define INSN2_M_FP_D 0x00000010 +/* Modifies the general purpose register in OP_*_RZ. */ +#define INSN2_WRITE_GPR_Z 0x00000020 +/* Modifies the floating point register in OP_*_FZ. */ +#define INSN2_WRITE_FPR_Z 0x00000040 +/* Reads the general purpose register in OP_*_RZ. */ +#define INSN2_READ_GPR_Z 0x00000080 +/* Reads the floating point register in OP_*_FZ. */ +#define INSN2_READ_FPR_Z 0x00000100 +/* Reads the general purpose register in OP_*_RD. */ +#define INSN2_READ_GPR_D 0x00000200 + + +/* Masks used to mark instructions to indicate which MIPS ISA level + they were introduced in. INSN_ISA_MASK masks an enumeration that + specifies the base ISA level(s). The remainder of a 32-bit + word constructed using these macros is a bitmask of the remaining + INSN_* values below. */ + +#define INSN_ISA_MASK 0x0000000ful + +/* We cannot start at zero due to ISA_UNKNOWN below. */ +#define INSN_ISA1 1 +#define INSN_ISA2 2 +#define INSN_ISA3 3 +#define INSN_ISA4 4 +#define INSN_ISA5 5 +#define INSN_ISA32 6 +#define INSN_ISA32R2 7 +#define INSN_ISA64 8 +#define INSN_ISA64R2 9 +/* Below this point the INSN_* values correspond to combinations of ISAs. + They are only for use in the opcodes table to indicate membership of + a combination of ISAs that cannot be expressed using the usual inclusion + ordering on the above INSN_* values. */ +#define INSN_ISA3_32 10 +#define INSN_ISA3_32R2 11 +#define INSN_ISA4_32 12 +#define INSN_ISA4_32R2 13 +#define INSN_ISA5_32R2 14 + +/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through + INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, + this table describes whether at least one of the ISAs described by X + is/are implemented by ISA Y. (Think of Y as the ISA level supported by + a particular core and X as the ISA level(s) at which a certain instruction + is defined.) The ISA(s) described by X is/are implemented by Y iff + (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 + is non-zero. */ +static const unsigned int mips_isa_table[] = + { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; + +/* Masks used for Chip specific instructions. */ +#define INSN_CHIP_MASK 0xc3ff0c20 + +/* Cavium Networks Octeon instructions. */ +#define INSN_OCTEON 0x00000800 + +/* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x3c00f000 + +/* DSP ASE */ +#define INSN_DSP 0x00001000 +#define INSN_DSP64 0x00002000 + +/* 0x00004000 is unused. */ + +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00008000 + +/* MIPS R4650 instruction. */ +#define INSN_4650 0x00010000 +/* LSI R4010 instruction. */ +#define INSN_4010 0x00020000 +/* NEC VR4100 instruction. */ +#define INSN_4100 0x00040000 +/* Toshiba R3900 instruction. */ +#define INSN_3900 0x00080000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 +/* Broadcom SB-1 instruction. */ +#define INSN_SB1 0x00200000 +/* NEC VR4111/VR4181 instruction. */ +#define INSN_4111 0x00400000 +/* NEC VR4120 instruction. */ +#define INSN_4120 0x00800000 +/* NEC VR5400 instruction. */ +#define INSN_5400 0x01000000 +/* NEC VR5500 instruction. */ +#define INSN_5500 0x02000000 + +/* MDMX ASE */ +#define INSN_MDMX 0x04000000 +/* MT ASE */ +#define INSN_MT 0x08000000 +/* SmartMIPS ASE */ +#define INSN_SMARTMIPS 0x10000000 +/* DSP R2 ASE */ +#define INSN_DSPR2 0x20000000 +/* ST Microelectronics Loongson 2E. */ +#define INSN_LOONGSON_2E 0x40000000 +/* ST Microelectronics Loongson 2F. */ +#define INSN_LOONGSON_2F 0x80000000 +/* Loongson 3A. */ +#define INSN_LOONGSON_3A 0x00000400 +/* RMI Xlr instruction */ +#define INSN_XLR 0x00000020 + +/* MIPS ISA defines, use instead of hardcoding ISA level. */ + +#define ISA_UNKNOWN 0 /* Gas internal use. */ +#define ISA_MIPS1 INSN_ISA1 +#define ISA_MIPS2 INSN_ISA2 +#define ISA_MIPS3 INSN_ISA3 +#define ISA_MIPS4 INSN_ISA4 +#define ISA_MIPS5 INSN_ISA5 + +#define ISA_MIPS32 INSN_ISA32 +#define ISA_MIPS64 INSN_ISA64 + +#define ISA_MIPS32R2 INSN_ISA32R2 +#define ISA_MIPS64R2 INSN_ISA64R2 + + +/* CPU defines, use instead of hardcoding processor number. Keep this + in sync with bfd/archures.c in order for machine selection to work. */ +#define CPU_UNKNOWN 0 /* Gas internal use. */ +#define CPU_R3000 3000 +#define CPU_R3900 3900 +#define CPU_R4000 4000 +#define CPU_R4010 4010 +#define CPU_VR4100 4100 +#define CPU_R4111 4111 +#define CPU_VR4120 4120 +#define CPU_R4300 4300 +#define CPU_R4400 4400 +#define CPU_R4600 4600 +#define CPU_R4650 4650 +#define CPU_R5000 5000 +#define CPU_VR5400 5400 +#define CPU_VR5500 5500 +#define CPU_R6000 6000 +#define CPU_RM7000 7000 +#define CPU_R8000 8000 +#define CPU_RM9000 9000 +#define CPU_R10000 10000 +#define CPU_R12000 12000 +#define CPU_R14000 14000 +#define CPU_R16000 16000 +#define CPU_MIPS16 16 +#define CPU_MIPS32 32 +#define CPU_MIPS32R2 33 +#define CPU_MIPS5 5 +#define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 +#define CPU_SB1 12310201 /* octal 'SB', 01. */ +#define CPU_LOONGSON_2E 3001 +#define CPU_LOONGSON_2F 3002 +#define CPU_LOONGSON_3A 3003 +#define CPU_OCTEON 6501 +#define CPU_XLR 887682 /* decimal 'XLR' */ + +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ + (((isa & INSN_ISA_MASK) != 0 \ + && ((insn)->membership & INSN_ISA_MASK) != 0 \ + && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ + (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ + || ((isa & ~INSN_ISA_MASK) \ + & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ + || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \ + || cpu == CPU_R16000) \ + && ((insn)->membership & INSN_10000) != 0) \ + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || (cpu == CPU_LOONGSON_2E \ + && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ + || (cpu == CPU_LOONGSON_2F \ + && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ + || (cpu == CPU_LOONGSON_3A \ + && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ + || (cpu == CPU_OCTEON \ + && ((insn)->membership & INSN_OCTEON) != 0) \ + || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ + || 0) /* Please keep this term for easier source merging. */ + +/* This is a list of macro expanded instructions. + + _I appended means immediate + _A appended means address + _AB appended means address with base register + _D appended means 64 bit floating point constant + _S appended means 32 bit floating point constant. */ + +enum +{ + M_ABS, + M_ADD_I, + M_ADDU_I, + M_AND_I, + M_BALIGN, + M_BEQ, + M_BEQ_I, + M_BEQL_I, + M_BGE, + M_BGEL, + M_BGE_I, + M_BGEL_I, + M_BGEU, + M_BGEUL, + M_BGEU_I, + M_BGEUL_I, + M_BGT, + M_BGTL, + M_BGT_I, + M_BGTL_I, + M_BGTU, + M_BGTUL, + M_BGTU_I, + M_BGTUL_I, + M_BLE, + M_BLEL, + M_BLE_I, + M_BLEL_I, + M_BLEU, + M_BLEUL, + M_BLEU_I, + M_BLEUL_I, + M_BLT, + M_BLTL, + M_BLT_I, + M_BLTL_I, + M_BLTU, + M_BLTUL, + M_BLTU_I, + M_BLTUL_I, + M_BNE, + M_BNE_I, + M_BNEL_I, + M_CACHE_AB, + M_DABS, + M_DADD_I, + M_DADDU_I, + M_DDIV_3, + M_DDIV_3I, + M_DDIVU_3, + M_DDIVU_3I, + M_DEXT, + M_DINS, + M_DIV_3, + M_DIV_3I, + M_DIVU_3, + M_DIVU_3I, + M_DLA_AB, + M_DLCA_AB, + M_DLI, + M_DMUL, + M_DMUL_I, + M_DMULO, + M_DMULO_I, + M_DMULOU, + M_DMULOU_I, + M_DREM_3, + M_DREM_3I, + M_DREMU_3, + M_DREMU_3I, + M_DSUB_I, + M_DSUBU_I, + M_DSUBU_I_2, + M_J_A, + M_JAL_1, + M_JAL_2, + M_JAL_A, + M_L_DOB, + M_L_DAB, + M_LA_AB, + M_LB_A, + M_LB_AB, + M_LBU_A, + M_LBU_AB, + M_LCA_AB, + M_LD_A, + M_LD_OB, + M_LD_AB, + M_LDC1_AB, + M_LDC2_AB, + M_LDC3_AB, + M_LDL_AB, + M_LDR_AB, + M_LH_A, + M_LH_AB, + M_LHU_A, + M_LHU_AB, + M_LI, + M_LI_D, + M_LI_DD, + M_LI_S, + M_LI_SS, + M_LL_AB, + M_LLD_AB, + M_LS_A, + M_LW_A, + M_LW_AB, + M_LWC0_A, + M_LWC0_AB, + M_LWC1_A, + M_LWC1_AB, + M_LWC2_A, + M_LWC2_AB, + M_LWC3_A, + M_LWC3_AB, + M_LWL_A, + M_LWL_AB, + M_LWR_A, + M_LWR_AB, + M_LWU_AB, + M_MSGSND, + M_MSGLD, + M_MSGLD_T, + M_MSGWAIT, + M_MSGWAIT_T, + M_MOVE, + M_MUL, + M_MUL_I, + M_MULO, + M_MULO_I, + M_MULOU, + M_MULOU_I, + M_NOR_I, + M_OR_I, + M_PREF_AB, + M_REM_3, + M_REM_3I, + M_REMU_3, + M_REMU_3I, + M_DROL, + M_ROL, + M_DROL_I, + M_ROL_I, + M_DROR, + M_ROR, + M_DROR_I, + M_ROR_I, + M_S_DA, + M_S_DOB, + M_S_DAB, + M_S_S, + M_SC_AB, + M_SCD_AB, + M_SD_A, + M_SD_OB, + M_SD_AB, + M_SDC1_AB, + M_SDC2_AB, + M_SDC3_AB, + M_SDL_AB, + M_SDR_AB, + M_SEQ, + M_SEQ_I, + M_SGE, + M_SGE_I, + M_SGEU, + M_SGEU_I, + M_SGT, + M_SGT_I, + M_SGTU, + M_SGTU_I, + M_SLE, + M_SLE_I, + M_SLEU, + M_SLEU_I, + M_SLT_I, + M_SLTU_I, + M_SNE, + M_SNE_I, + M_SB_A, + M_SB_AB, + M_SH_A, + M_SH_AB, + M_SW_A, + M_SW_AB, + M_SWC0_A, + M_SWC0_AB, + M_SWC1_A, + M_SWC1_AB, + M_SWC2_A, + M_SWC2_AB, + M_SWC3_A, + M_SWC3_AB, + M_SWL_A, + M_SWL_AB, + M_SWR_A, + M_SWR_AB, + M_SUB_I, + M_SUBU_I, + M_SUBU_I_2, + M_TEQ_I, + M_TGE_I, + M_TGEU_I, + M_TLT_I, + M_TLTU_I, + M_TNE_I, + M_TRUNCWD, + M_TRUNCWS, + M_ULD, + M_ULD_A, + M_ULH, + M_ULH_A, + M_ULHU, + M_ULHU_A, + M_ULW, + M_ULW_A, + M_USH, + M_USH_A, + M_USW, + M_USW_A, + M_USD, + M_USD_A, + M_XOR_I, + M_COP0, + M_COP1, + M_COP2, + M_COP3, + M_NUM_MACROS +}; + + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Many instructions are short hand for other instructions (i.e., The + jal instruction is short for jalr ). */ + +extern const struct mips_opcode mips_builtin_opcodes[]; +extern const int bfd_mips_num_builtin_opcodes; +extern struct mips_opcode *mips_opcodes; +extern int bfd_mips_num_opcodes; +#define NUMOPCODES bfd_mips_num_opcodes + + +/* The rest of this file adds definitions for the mips16 TinyRISC + processor. */ + +/* These are the bitmasks and shift counts used for the different + fields in the instruction formats. Other than OP, no masks are + provided for the fixed portions of an instruction, since they are + not needed. + + The I format uses IMM11. + + The RI format uses RX and IMM8. + + The RR format uses RX, and RY. + + The RRI format uses RX, RY, and IMM5. + + The RRR format uses RX, RY, and RZ. + + The RRI_A format uses RX, RY, and IMM4. + + The SHIFT format uses RX, RY, and SHAMT. + + The I8 format uses IMM8. + + The I8_MOVR32 format uses RY and REGR32. + + The IR_MOV32R format uses REG32R and MOV32Z. + + The I64 format uses IMM8. + + The RI64 format uses RY and IMM5. + */ + +#define MIPS16OP_MASK_OP 0x1f +#define MIPS16OP_SH_OP 11 +#define MIPS16OP_MASK_IMM11 0x7ff +#define MIPS16OP_SH_IMM11 0 +#define MIPS16OP_MASK_RX 0x7 +#define MIPS16OP_SH_RX 8 +#define MIPS16OP_MASK_IMM8 0xff +#define MIPS16OP_SH_IMM8 0 +#define MIPS16OP_MASK_RY 0x7 +#define MIPS16OP_SH_RY 5 +#define MIPS16OP_MASK_IMM5 0x1f +#define MIPS16OP_SH_IMM5 0 +#define MIPS16OP_MASK_RZ 0x7 +#define MIPS16OP_SH_RZ 2 +#define MIPS16OP_MASK_IMM4 0xf +#define MIPS16OP_SH_IMM4 0 +#define MIPS16OP_MASK_REGR32 0x1f +#define MIPS16OP_SH_REGR32 0 +#define MIPS16OP_MASK_REG32R 0x1f +#define MIPS16OP_SH_REG32R 3 +#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) +#define MIPS16OP_MASK_MOVE32Z 0x7 +#define MIPS16OP_SH_MOVE32Z 0 +#define MIPS16OP_MASK_IMM6 0x3f +#define MIPS16OP_SH_IMM6 5 + +/* These are the characters which may appears in the args field of a MIPS16 + instruction. They appear in the order in which the fields appear when the + instruction is used. Commas and parentheses in the args string are ignored + when assembling, and written into the output when disassembling. + + "y" 3 bit register (MIPS16OP_*_RY) + "x" 3 bit register (MIPS16OP_*_RX) + "z" 3 bit register (MIPS16OP_*_RZ) + "Z" 3 bit register (MIPS16OP_*_MOVE32Z) + "v" 3 bit same register as source and destination (MIPS16OP_*_RX) + "w" 3 bit same register as source and destination (MIPS16OP_*_RY) + "0" zero register ($0) + "S" stack pointer ($sp or $29) + "P" program counter + "R" return address register ($ra or $31) + "X" 5 bit MIPS register (MIPS16OP_*_REGR32) + "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) + "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) + "a" 26 bit jump address + "e" 11 bit extension value + "l" register list for entry instruction + "L" register list for exit instruction + + The remaining codes may be extended. Except as otherwise noted, + the full extended operand is a 16 bit signed value. + "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) + ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) + "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) + "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) + "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) + "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) + "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) + "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) + "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) + "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) + "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) + "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) + "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) + "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) + "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) + "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) + "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) + "q" 11 bit branch address (MIPS16OP_*_IMM11) + "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) + "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) + "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) + "m" 7 bit register list for save instruction (18 bit extended) + "M" 7 bit register list for restore instruction (18 bit extended) + */ + +/* Save/restore encoding for the args field when all 4 registers are + either saved as arguments or saved/restored as statics. */ +#define MIPS16_ALL_ARGS 0xe +#define MIPS16_ALL_STATICS 0xb + +/* For the mips16, we use the same opcode table format and a few of + the same flags. However, most of the flags are different. */ + +/* Modifies the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_WRITE_X 0x00000001 +/* Modifies the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_WRITE_Y 0x00000002 +/* Modifies the register in MIPS16OP_*_RZ. */ +#define MIPS16_INSN_WRITE_Z 0x00000004 +/* Modifies the T ($24) register. */ +#define MIPS16_INSN_WRITE_T 0x00000008 +/* Modifies the SP ($29) register. */ +#define MIPS16_INSN_WRITE_SP 0x00000010 +/* Modifies the RA ($31) register. */ +#define MIPS16_INSN_WRITE_31 0x00000020 +/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ +#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 +/* Reads the register in MIPS16OP_*_RX. */ +#define MIPS16_INSN_READ_X 0x00000080 +/* Reads the register in MIPS16OP_*_RY. */ +#define MIPS16_INSN_READ_Y 0x00000100 +/* Reads the register in MIPS16OP_*_MOVE32Z. */ +#define MIPS16_INSN_READ_Z 0x00000200 +/* Reads the T ($24) register. */ +#define MIPS16_INSN_READ_T 0x00000400 +/* Reads the SP ($29) register. */ +#define MIPS16_INSN_READ_SP 0x00000800 +/* Reads the RA ($31) register. */ +#define MIPS16_INSN_READ_31 0x00001000 +/* Reads the program counter. */ +#define MIPS16_INSN_READ_PC 0x00002000 +/* Reads the general purpose register in MIPS16OP_*_REGR32. */ +#define MIPS16_INSN_READ_GPR_X 0x00004000 +/* Is an unconditional branch insn. */ +#define MIPS16_INSN_UNCOND_BRANCH 0x00008000 +/* Is a conditional branch insn. */ +#define MIPS16_INSN_COND_BRANCH 0x00010000 + +/* The following flags have the same value for the mips16 opcode + table: + INSN_UNCOND_BRANCH_DELAY + INSN_COND_BRANCH_DELAY + INSN_COND_BRANCH_LIKELY (never used) + INSN_READ_HI + INSN_READ_LO + INSN_WRITE_HI + INSN_WRITE_LO + INSN_TRAP + INSN_ISA3 + */ + +extern const struct mips_opcode mips16_opcodes[]; +extern const int bfd_mips16_num_opcodes; + +/* A NOP insn impemented as "or at,at,zero". + Used to implement -mfix-loongson2f. */ +#define LOONGSON2F_NOP_INSN 0x00200825 + +#endif /* _MIPS_H_ */ diff --git a/external/gpl3/gdb/dist/include/opcode/mmix.h b/external/gpl3/gdb/dist/include/opcode/mmix.h new file mode 100644 index 000000000000..f931545d6700 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/mmix.h @@ -0,0 +1,187 @@ +/* mmix.h -- Header file for MMIX opcode table + Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* We could have just a char*[] table indexed by the register number, but + that would not allow for synonyms. The table is terminated with an + entry with a NULL name. */ +struct mmix_spec_reg +{ + const char *name; + unsigned int number; +}; + +/* General indication of the type of instruction. */ +enum mmix_insn_type + { + mmix_type_pseudo, + mmix_type_normal, + mmix_type_branch, + mmix_type_condbranch, + mmix_type_memaccess_octa, + mmix_type_memaccess_tetra, + mmix_type_memaccess_wyde, + mmix_type_memaccess_byte, + mmix_type_memaccess_block, + mmix_type_jsr + }; + +/* Type of operands an instruction takes. Use when parsing assembly code + and disassembling. */ +enum mmix_operands_type + { + mmix_operands_none = 0, + + /* All operands are registers: "$X,$Y,$Z". */ + mmix_operands_regs, + + /* "$X,YZ", like SETH. */ + mmix_operands_reg_yz, + + /* The regular "$X,$Y,$Z|Z". + The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is + assumed. */ + mmix_operands_regs_z_opt, + + /* The regular "$X,$Y,$Z|Z". */ + mmix_operands_regs_z, + + /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ + mmix_operands_jmp, + + /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an + integer. */ + mmix_operands_pushgo, + + /* Two registers or a register and a byte, like FLOT, possibly with + rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ + mmix_operands_roundregs_z, + + /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ + mmix_operands_pop, + + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + mmix_operands_roundregs, + + /* "XYZ", like SYNC. */ + mmix_operands_sync, + + /* "X,$Y,$Z|Z", like SYNCD. */ + mmix_operands_x_regs_z, + + /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ + mmix_operands_neg, + + /* "$X,Address, like GETA or branches. */ + mmix_operands_regaddr, + + /* "$X|X,Address, like PUSHJ. */ + mmix_operands_pushj, + + /* "$X,spec_reg"; GET. */ + mmix_operands_get, + + /* "spec_reg,$Z|Z"; PUT. */ + mmix_operands_put, + + /* Two registers, "$X,$Y". */ + mmix_operands_set, + + /* "$X,0"; SAVE. */ + mmix_operands_save, + + /* "0,$Z"; UNSAVE. */ + mmix_operands_unsave, + + /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three + operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ + mmix_operands_xyz_opt, + + /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted + and will then be assumed zero. */ + mmix_operands_resume, + + /* These are specials to handle that pseudo-directives are specified + like ordinary insns when being mmixal-compatible. They signify the + specific pseudo-directive rather than the operands type. */ + + /* LOC. */ + mmix_operands_loc, + + /* PREFIX. */ + mmix_operands_prefix, + + /* BYTE. */ + mmix_operands_byte, + + /* WYDE. */ + mmix_operands_wyde, + + /* TETRA. */ + mmix_operands_tetra, + + /* OCTA. */ + mmix_operands_octa, + + /* LOCAL. */ + mmix_operands_local, + + /* BSPEC. */ + mmix_operands_bspec, + + /* ESPEC. */ + mmix_operands_espec, + }; + +struct mmix_opcode + { + const char *name; + unsigned long match; + unsigned long lose; + enum mmix_operands_type operands; + + /* This is used by the disassembly function. */ + enum mmix_insn_type type; + }; + +/* Declare the actual tables. */ +extern const struct mmix_opcode mmix_opcodes[]; + +/* This one is terminated with an entry with a NULL name. */ +extern const struct mmix_spec_reg mmix_spec_regs[]; + +/* Some insn values we use when padding and synthesizing address loads. */ +#define IMM_OFFSET_BIT 1 +#define COND_INV_BIT 0x8 +#define PRED_INV_BIT 0x10 + +#define PUSHGO_INSN_BYTE 0xbe +#define GO_INSN_BYTE 0x9e +#define SETL_INSN_BYTE 0xe3 +#define INCML_INSN_BYTE 0xe6 +#define INCMH_INSN_BYTE 0xe5 +#define INCH_INSN_BYTE 0xe4 +#define SWYM_INSN_BYTE 0xfd +#define JMP_INSN_BYTE 0xf0 + +/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) + global registers. */ +#define MAX_GREGS 223 diff --git a/external/gpl3/gdb/dist/include/opcode/mn10200.h b/external/gpl3/gdb/dist/include/opcode/mn10200.h new file mode 100644 index 000000000000..b597d7b4bf70 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/mn10200.h @@ -0,0 +1,111 @@ +/* mn10200.h -- Header file for Matsushita 10200 opcode table + Copyright 1996, 1997, 2010 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef MN10200_H +#define MN10200_H + +/* The opcode table is an array of struct mn10200_opcode. */ + +struct mn10200_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* The format of this opcode. */ + unsigned char format; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10200_opcode mn10200_opcodes[]; +extern const int mn10200_num_opcodes; + + +/* The operands table is an array of struct mn10200_operand. */ + +struct mn10200_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10200_opcodes table. */ + +extern const struct mn10200_operand mn10200_operands[]; + +/* Values defined for the flags field of a struct mn10200_operand. */ +#define MN10200_OPERAND_DREG 0x1 + +#define MN10200_OPERAND_AREG 0x2 + +#define MN10200_OPERAND_PSW 0x4 + +#define MN10200_OPERAND_MDR 0x8 + +#define MN10200_OPERAND_SIGNED 0x10 + +#define MN10200_OPERAND_PROMOTE 0x20 + +#define MN10200_OPERAND_PAREN 0x40 + +#define MN10200_OPERAND_REPEATED 0x80 + +#define MN10200_OPERAND_EXTENDED 0x100 + +#define MN10200_OPERAND_NOCHECK 0x200 + +#define MN10200_OPERAND_PCREL 0x400 + +#define MN10200_OPERAND_MEMADDR 0x800 + +#define MN10200_OPERAND_RELAX 0x1000 + +#define FMT_1 1 +#define FMT_2 2 +#define FMT_3 3 +#define FMT_4 4 +#define FMT_5 5 +#define FMT_6 6 +#define FMT_7 7 +#endif /* MN10200_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/mn10300.h b/external/gpl3/gdb/dist/include/opcode/mn10300.h new file mode 100644 index 000000000000..16a139bce5d6 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/mn10300.h @@ -0,0 +1,170 @@ +/* mn10300.h -- Header file for Matsushita 10300 opcode table + Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef MN10300_H +#define MN10300_H + +/* The opcode table is an array of struct mn10300_opcode. */ + +#define MN10300_MAX_OPERANDS 8 +struct mn10300_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* A bitmask. For each operand, nonzero if it must not have the same + register specification as all other operands with a nonzero bit in + this flag. ie 0x81 would indicate that operands 7 and 0 must not + match. Note that we count operands from left to right as they appear + in the operands specification below. */ + unsigned int no_match_operands; + + /* The format of this opcode. */ + unsigned char format; + + /* Bitmask indicating what cpu variants this opcode is available on. + We assume mn10300 base opcodes are available everywhere, so we only + have to note opcodes which are available on other variants. */ + unsigned int machine; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[MN10300_MAX_OPERANDS]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10300_opcode mn10300_opcodes[]; +extern const int mn10300_num_opcodes; + + +/* The operands table is an array of struct mn10300_operand. */ + +struct mn10300_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10300_opcodes table. */ + +extern const struct mn10300_operand mn10300_operands[]; + +/* Values defined for the flags field of a struct mn10300_operand. */ +#define MN10300_OPERAND_DREG 0x1 + +#define MN10300_OPERAND_AREG 0x2 + +#define MN10300_OPERAND_SP 0x4 + +#define MN10300_OPERAND_PSW 0x8 + +#define MN10300_OPERAND_MDR 0x10 + +#define MN10300_OPERAND_SIGNED 0x20 + +#define MN10300_OPERAND_PROMOTE 0x40 + +#define MN10300_OPERAND_PAREN 0x80 + +#define MN10300_OPERAND_REPEATED 0x100 + +#define MN10300_OPERAND_EXTENDED 0x200 + +#define MN10300_OPERAND_SPLIT 0x400 + +#define MN10300_OPERAND_REG_LIST 0x800 + +#define MN10300_OPERAND_PCREL 0x1000 + +#define MN10300_OPERAND_MEMADDR 0x2000 + +#define MN10300_OPERAND_RELAX 0x4000 + +#define MN10300_OPERAND_USP 0x8000 + +#define MN10300_OPERAND_SSP 0x10000 + +#define MN10300_OPERAND_MSP 0x20000 + +#define MN10300_OPERAND_PC 0x40000 + +#define MN10300_OPERAND_EPSW 0x80000 + +#define MN10300_OPERAND_RREG 0x100000 + +#define MN10300_OPERAND_XRREG 0x200000 + +#define MN10300_OPERAND_PLUS 0x400000 + +#define MN10300_OPERAND_24BIT 0x800000 + +#define MN10300_OPERAND_FSREG 0x1000000 + +#define MN10300_OPERAND_FDREG 0x2000000 + +#define MN10300_OPERAND_FPCR 0x4000000 + +/* Opcode Formats. */ +#define FMT_S0 1 +#define FMT_S1 2 +#define FMT_S2 3 +#define FMT_S4 4 +#define FMT_S6 5 +#define FMT_D0 6 +#define FMT_D1 7 +#define FMT_D2 8 +#define FMT_D4 9 +#define FMT_D5 10 +#define FMT_D6 11 +#define FMT_D7 12 +#define FMT_D8 13 +#define FMT_D9 14 +#define FMT_D10 15 +#define FMT_D3 16 + +/* Variants of the mn10300 which have additional opcodes. */ +#define MN103 300 +#define AM30 300 + +#define AM33 330 +#define AM33_2 332 + +#endif /* MN10300_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/moxie.h b/external/gpl3/gdb/dist/include/opcode/moxie.h new file mode 100644 index 000000000000..e2bc374f0443 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/moxie.h @@ -0,0 +1,72 @@ +/* Definitions for decoding the moxie opcode table. + Copyright 2009 Free Software Foundation, Inc. + Contributed by Anthony Green (green@moxielogic.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* Form 1 instructions come in different flavors: + + Some have no arguments (MOXIE_F1_NARG) + Some only use the A operand (MOXIE_F1_A) + Some use A and B registers (MOXIE_F1_AB) + Some use A and consume a 4 byte immediate value (MOXIE_F1_A4) + Some use just a 4 byte immediate value (MOXIE_F1_4) + Some use just a 4 byte memory address (MOXIE_F1_M) + Some use B and an indirect A (MOXIE_F1_AiB) + Some use A and an indirect B (MOXIE_F1_ABi) + Some consume a 4 byte immediate value and use X (MOXIE_F1_4A) + Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4) + Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4) + + Form 2 instructions also come in different flavors: + + Some have no arguments (MOXIE_F2_NARG) + Some use the A register and an 8-bit value (MOXIE_F2_A8V) + + Form 3 instructions also come in different flavors: + + Some have no arguments (MOXIE_F3_NARG) + Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */ + +#define MOXIE_F1_NARG 0x100 +#define MOXIE_F1_A 0x101 +#define MOXIE_F1_AB 0x102 +/* #define MOXIE_F1_ABC 0x103 */ +#define MOXIE_F1_A4 0x104 +#define MOXIE_F1_4 0x105 +#define MOXIE_F1_AiB 0x106 +#define MOXIE_F1_ABi 0x107 +#define MOXIE_F1_4A 0x108 +#define MOXIE_F1_AiB4 0x109 +#define MOXIE_F1_ABi4 0x10a +#define MOXIE_F1_M 0x10b + +#define MOXIE_F2_NARG 0x200 +#define MOXIE_F2_A8V 0x201 + +#define MOXIE_F3_NARG 0x300 +#define MOXIE_F3_PCREL 0x301 + +typedef struct moxie_opc_info_t +{ + short opcode; + unsigned itype; + const char * name; +} moxie_opc_info_t; + +extern const moxie_opc_info_t moxie_form1_opc_info[64]; +extern const moxie_opc_info_t moxie_form2_opc_info[4]; +extern const moxie_opc_info_t moxie_form3_opc_info[16]; diff --git a/external/gpl3/gdb/dist/include/opcode/msp430.h b/external/gpl3/gdb/dist/include/opcode/msp430.h new file mode 100644 index 000000000000..d3bf130ee098 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/msp430.h @@ -0,0 +1,126 @@ +/* Opcode table for the TI MSP430 microcontrollers + + Copyright 2002, 2004, 2010 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef __MSP430_H_ +#define __MSP430_H_ + +struct msp430_operand_s +{ + int ol; /* Operand length words. */ + int am; /* Addr mode. */ + int reg; /* Register. */ + int mode; /* Pperand mode. */ +#define OP_REG 0 +#define OP_EXP 1 +#ifndef DASM_SECTION + expressionS exp; +#endif +}; + +#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ + +struct msp430_opcode_s +{ + char *name; + int fmt; + int insn_opnumb; + int bin_opcode; + int bin_mask; +}; + +#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } + +static struct msp430_opcode_s msp430_opcodes[] = +{ + MSP_INSN (and, 1, 2, 0xf000, 0xf000), + MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), + MSP_INSN (xor, 1, 2, 0xe000, 0xf000), + MSP_INSN (setz, 0, 0, 0xd322, 0xffff), + MSP_INSN (setc, 0, 0, 0xd312, 0xffff), + MSP_INSN (eint, 0, 0, 0xd232, 0xffff), + MSP_INSN (setn, 0, 0, 0xd222, 0xffff), + MSP_INSN (bis, 1, 2, 0xd000, 0xf000), + MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), + MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), + MSP_INSN (dint, 0, 0, 0xc232, 0xffff), + MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), + MSP_INSN (bic, 1, 2, 0xc000, 0xf000), + MSP_INSN (bit, 1, 2, 0xb000, 0xf000), + MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), + MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), + MSP_INSN (tst, 0, 1, 0x9300, 0xff30), + MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), + MSP_INSN (decd, 0, 1, 0x8320, 0xff30), + MSP_INSN (dec, 0, 1, 0x8310, 0xff30), + MSP_INSN (sub, 1, 2, 0x8000, 0xf000), + MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), + MSP_INSN (subc, 1, 2, 0x7000, 0xf000), + MSP_INSN (adc, 0, 1, 0x6300, 0xff30), + MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), + MSP_INSN (addc, 1, 2, 0x6000, 0xf000), + MSP_INSN (incd, 0, 1, 0x5320, 0xff30), + MSP_INSN (inc, 0, 1, 0x5310, 0xff30), + MSP_INSN (rla, 0, 2, 0x5000, 0xf000), + MSP_INSN (add, 1, 2, 0x5000, 0xf000), + MSP_INSN (nop, 0, 0, 0x4303, 0xffff), + MSP_INSN (clr, 0, 1, 0x4300, 0xff30), + MSP_INSN (ret, 0, 0, 0x4130, 0xff30), + MSP_INSN (pop, 0, 1, 0x4130, 0xff30), + MSP_INSN (br, 0, 3, 0x4000, 0xf000), + MSP_INSN (mov, 1, 2, 0x4000, 0xf000), + MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), + MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), + MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), + MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), + MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), + MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), + MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), + MSP_INSN (call, 2, 1, 0x1280, 0xffc0), + MSP_INSN (push, 2, 1, 0x1200, 0xff80), + MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), + MSP_INSN (rra, 2, 1, 0x1100, 0xff80), + MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), + MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), + /* Simple polymorphs. */ + MSP_INSN (beq, 4, 0, 0, 0xffff), + MSP_INSN (bne, 4, 1, 0, 0xffff), + MSP_INSN (blt, 4, 2, 0, 0xffff), + MSP_INSN (bltu, 4, 3, 0, 0xffff), + MSP_INSN (bge, 4, 4, 0, 0xffff), + MSP_INSN (bgeu, 4, 5, 0, 0xffff), + MSP_INSN (bltn, 4, 6, 0, 0xffff), + MSP_INSN (jump, 4, 7, 0, 0xffff), + /* Long polymorphs. */ + MSP_INSN (bgt, 5, 0, 0, 0xffff), + MSP_INSN (bgtu, 5, 1, 0, 0xffff), + MSP_INSN (bleu, 5, 2, 0, 0xffff), + MSP_INSN (ble, 5, 3, 0, 0xffff), + + /* End of instruction set. */ + { NULL, 0, 0, 0, 0 } +}; + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/np1.h b/external/gpl3/gdb/dist/include/opcode/np1.h new file mode 100644 index 000000000000..6dadafde0db5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/np1.h @@ -0,0 +1,421 @@ +/* Print GOULD NPL instructions for GDB, the GNU debugger. + Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. + + This file is part of GDB. + + GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... */ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. */ +struct gld_opcode gld_opcodes[] = +{ +{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, +{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, +{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, +{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, +{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, +{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, +{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, +{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, +{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, + +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, +{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, +{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, +{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, + +{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, +{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, +{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, +{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, +{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, +{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, +{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, +{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, +{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, +{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, +{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, + +{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, +{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, +{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, +{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, +{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, +{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, +{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, +{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, +{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, +{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, +{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, +{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, +{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, +{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, +{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, +{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, +{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, +{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, +{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, +{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, +{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, +{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, +{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, + +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, +{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, + +{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, +{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, +{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, +{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, +{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, +{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, + +{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, +{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, +{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, +{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, + +{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, +{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, +{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, +{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, +{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, + +{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, +{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, +{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, +{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, +{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, +{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, + +{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, +{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, + +{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, +{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, +{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, + +{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, +{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, +{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, +{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, +{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, +{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, +{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, +{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, +{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, +{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, + +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, +{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, + +{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, +{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, +{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, +{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, +{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, +{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, +{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, +{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, +{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, +{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, +{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, +{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, +{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, +{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, + +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, + +{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, +{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, +{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, +{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, + +{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, +{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, +{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, +{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, +{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, +{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, +{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, +{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, +{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, +{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, +{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, +{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, + +{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, +{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, +{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, +{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, +{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, +{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, +{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, +{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, +{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, +{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, +{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, +{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, +{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, +{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, +{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, +{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, +{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, +{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, +{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, +{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, +{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, +{ "break", 0x28090000, 0xfc0f0000, "", 2 }, +{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, +{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, +{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, +{ "block", 0x04060000, 0xfc0f0000, "", 2 }, +{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, +{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, +{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, +{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, +{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, +{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, +{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, +{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, +{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, +{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, +{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, +{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, +{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, +{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, + +{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, +{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, +{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, + +{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, +{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, +{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, +{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, +{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, +{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, +{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/external/gpl3/gdb/dist/include/opcode/ns32k.h b/external/gpl3/gdb/dist/include/opcode/ns32k.h new file mode 100644 index 000000000000..34c42f87593f --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/ns32k.h @@ -0,0 +1,487 @@ +/* ns32k-opcode.h -- Opcode table for National Semi 32k processor + Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifdef SEQUENT_COMPATABILITY +#define DEF_MODEC 20 +#define DEF_MODEL 21 +#endif + +#ifndef DEF_MODEC +#define DEF_MODEC 20 +#endif + +#ifndef DEF_MODEL +#define DEF_MODEL 20 +#endif +/* + After deciding the instruction entry (via hash.c) the instruction parser + will try to match the operands after the instruction to the required set + given in the entry operandfield. Every operand will result in a change in + the opcode or the addition of data to the opcode. + The operands in the source instruction are checked for inconsistent + semantics. + + F : 32 bit float general form + L : 64 bit float " + B : byte " + W : word " + D : double-word " + A : double-word gen-address-form ie no regs, no immediate + I : integer writeable gen int except immediate (A + reg) + Z : floating writeable gen float except immediate (Z + freg) + d : displacement + b : displacement - pc relative addressing acb + p : displacement - pc relative addressing br bcond bsr cxp + q : quick + i : immediate (8 bits) + This is not a standard ns32k operandtype, it is used to build + instructions like svc arg1,arg2 + Svc is the instruction SuperVisorCall and is sometimes used to + call OS-routines from usermode. Some args might be handy! + r : register number (3 bits) + O : setcfg instruction optionslist + C : cinv instruction optionslist + S : stringinstruction optionslist + U : registerlist save,enter + u : registerlist restore,exit + M : mmu register + P : cpu register + g : 3:rd operand of inss or exts instruction + G : 4:th operand of inss or exts instruction + Those operands are encoded in the same byte. + This byte is placed last in the instruction. + f : operand of sfsr + H : sequent-hack for bsr (Warning) + +column 1 instructions + 2 number of bits in opcode. + 3 number of bits in opcode explicitly + determined by the instruction type. + 4 opcodeseed, the number we build our opcode + from. + 5 operandtypes, used by operandparser. + 6 size in bytes of immediate +*/ +struct ns32k_opcode { + const char *name; + unsigned char opcode_id_size; /* not used by the assembler */ + unsigned char opcode_size; + unsigned long opcode_seed; + const char *operands; + unsigned char im_size; /* not used by dissassembler */ + const char *default_args; /* default to those args when none given */ + char default_modec; /* default to this addr-mode when ambigous + ie when the argument of a general addr-mode + is a plain constant */ + char default_model; /* is a plain label */ +}; + +#ifdef comment +/* This section was from the gdb version of this file. */ + +#ifndef ns32k_opcodeT +#define ns32k_opcodeT int +#endif /* no ns32k_opcodeT */ + +struct not_wot /* ns32k opcode table: wot to do with this */ + /* particular opcode */ +{ + int obits; /* number of opcode bits */ + int ibits; /* number of instruction bits */ + ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ + const char *args; /* how to compile said opcode */ +}; + +struct not /* ns32k opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct not_wot detail; /* rest of opcode table [datum] */ +}; + +/* Instructions look like this: + + basic instruction--1, 2, or 3 bytes + index byte for operand A, if operand A is indexed--1 byte + index byte for operand B, if operand B is indexed--1 byte + addressing extension for operand A + addressing extension for operand B + implied operands + + Operand A is the operand listed first in the following opcode table. + Operand B is the operand listed second in the following opcode table. + All instructions have at most 2 general operands, so this is enough. + The implied operands are associated with operands other than A and B. + + Each operand has a digit and a letter. + + The digit gives the position in the assembly language. The letter, + one of the following, tells us what kind of operand it is. */ + +/* F : 32 bit float + * L : 64 bit float + * B : byte + * W : word + * D : double-word + * I : integer not immediate + * Z : floating not immediate + * d : displacement + * q : quick + * i : immediate (8 bits) + * r : register number (3 bits) + * p : displacement - pc relative addressing +*/ + + +#endif /* comment */ + +static const struct ns32k_opcode ns32k_opcodes[]= +{ + { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, + { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, + { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, + { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, + { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, + { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, + { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, + { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, + { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, + { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, + { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, + { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, + { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, + { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, + { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, + { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, + { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, + { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, + { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, + { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, + { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, +#ifdef SEQUENT_COMPATABILITY + { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, +#else + { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, +#endif + { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, + { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, + { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, + { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, + { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, + { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, + { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, + { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, +#ifdef NS32K_SVC_IMMED_OPERANDS + { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ +#else + { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, +#endif + { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, + { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, +}; + +#define MAX_ARGS 4 +#define ARG_LEN 50 + diff --git a/external/gpl3/gdb/dist/include/opcode/or32.h b/external/gpl3/gdb/dist/include/opcode/or32.h new file mode 100644 index 000000000000..153d91ec42f1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/or32.h @@ -0,0 +1,181 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002, 2003, 2010 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#define MAX_GPRS 32 +#define PAGE_SIZE 4096 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +struct or32_letter +{ + char letter; + int sign; + /* int reloc; relocation per letter ?? */ +}; + +/* Main instruction specification array. */ +struct or32_opcode +{ + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand. + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused). */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + void (*exec) (void); + unsigned int flags; +}; + +#define OPTYPE_LAST (0x80000000) +#define OPTYPE_OP (0x40000000) +#define OPTYPE_REG (0x20000000) +#define OPTYPE_SIG (0x10000000) +#define OPTYPE_DIS (0x08000000) +#define OPTYPE_DST (0x04000000) +#define OPTYPE_SBIT (0x00001F00) +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct +{ + unsigned long type; + unsigned long data; +} **op_start; + +#ifdef HAS_EXECUTION +extern void l_invalid (void); +extern void l_sfne (void); +extern void l_bf (void); +extern void l_add (void); +extern void l_sw (void); +extern void l_sb (void); +extern void l_sh (void); +extern void l_lwz (void); +extern void l_lbs (void); +extern void l_lbz (void); +extern void l_lhs (void); +extern void l_lhz (void); +extern void l_movhi (void); +extern void l_and (void); +extern void l_or (void); +extern void l_xor (void); +extern void l_sub (void); +extern void l_mul (void); +extern void l_div (void); +extern void l_divu (void); +extern void l_sll (void); +extern void l_sra (void); +extern void l_srl (void); +extern void l_j (void); +extern void l_jal (void); +extern void l_jalr (void); +extern void l_jr (void); +extern void l_rfe (void); +extern void l_nop (void); +extern void l_bnf (void); +extern void l_sfeq (void); +extern void l_sfgts (void); +extern void l_sfges (void); +extern void l_sflts (void); +extern void l_sfles (void); +extern void l_sfgtu (void); +extern void l_sfgeu (void); +extern void l_sfltu (void); +extern void l_sfleu (void); +extern void l_mtspr (void); +extern void l_mfspr (void); +extern void l_sys (void); +extern void l_trap (void); /* CZ 21/06/01. */ +extern void l_macrc (void); +extern void l_mac (void); +extern void l_msb (void); +extern void l_invalid (void); +extern void l_cust1 (void); +extern void l_cust2 (void); +extern void l_cust3 (void); +extern void l_cust4 (void); +#endif +extern void l_none (void); + +extern const struct or32_letter or32_letters[]; + +extern const struct or32_opcode or32_opcodes[]; + +extern const unsigned int or32_num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len (int); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed (char); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range (char); + +/* MM: Returns index of given instruction name. */ +extern int insn_index (char *); + +/* MM: Returns instruction name from index. */ +extern const char *insn_name (int); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata (void); + +/* MM: Destructs FSM. */ +extern void destruct_automata (void); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode (unsigned int); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn (unsigned long); + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/pdp11.h b/external/gpl3/gdb/dist/include/opcode/pdp11.h new file mode 100644 index 000000000000..24e13b25ae56 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/pdp11.h @@ -0,0 +1,84 @@ +/* PDP-11 opcde list. + Copyright 2001, 2002, 2010 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GDB and GAS are distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* PDP-11 opcode types. */ + +#define PDP11_OPCODE_NO_OPS 0 +#define PDP11_OPCODE_REG 1 /* register */ +#define PDP11_OPCODE_OP 2 /* generic operand */ +#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ +#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, + reversed syntax */ +#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float + operand */ +#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ +#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ +#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative + displacement */ +#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ +#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ +#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ +#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ +#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu + accumulator */ +#define PDP11_OPCODE_FOP 14 /* generic float operand */ +#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int + operand */ +#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu + accumulator */ + +/* + * PDP-11 instruction set extensions. + * + * Please keep the numbers low, as they are used as indices into + * an array. + */ + +#define PDP11_NONE 0 /* not in instruction set */ +#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ +#define PDP11_CSM 2 /* commercial instruction set */ +#define PDP11_CIS 3 /* commercial instruction set */ +#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ +#define PDP11_FIS 5 /* KEV11 floating-point instructions */ +#define PDP11_FPP 6 /* FP-11 floating-point instructions */ +#define PDP11_LEIS 7 /* limited extended instruction set + (11/40 etc) */ +#define PDP11_MFPT 8 /* move from processor type */ +#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, + wrtlck */ +#define PDP11_MXPS 10 /* move from/to processor status */ +#define PDP11_SPL 11 /* set priority level */ +#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ +#define PDP11_EXT_NUM 13 /* total number of extension types */ + +struct pdp11_opcode +{ + const char *name; + int opcode; + int mask; + int type; + int extension; +}; + +extern const struct pdp11_opcode pdp11_opcodes[]; +extern const struct pdp11_opcode pdp11_aliases[]; +extern const int pdp11_num_opcodes, pdp11_num_aliases; + +/* end of pdp11.h */ diff --git a/external/gpl3/gdb/dist/include/opcode/pj.h b/external/gpl3/gdb/dist/include/opcode/pj.h new file mode 100644 index 000000000000..e6ffacc4ba39 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/pj.h @@ -0,0 +1,49 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct pj_opc_info_t +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + union { + const char *name; + void (*func) (struct pj_opc_info_t *, char *); + } u; +} pj_opc_info_t; diff --git a/external/gpl3/gdb/dist/include/opcode/pn.h b/external/gpl3/gdb/dist/include/opcode/pn.h new file mode 100644 index 000000000000..6674030c4fd1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/pn.h @@ -0,0 +1,283 @@ +/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. + Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. + + This file is part of GDB. + + GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +struct gld_opcode +{ + char *name; + unsigned long opcode; + unsigned long mask; + char *args; + int length; +}; + +/* We store four bytes of opcode for all opcodes because that + is the most any of them need. The actual length of an instruction + is always at least 2 bytes, and at most four. The length of the + instruction is based on the opcode. + + The mask component is a mask saying which bits must match + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing characters + that are used to format the arguments to the instruction. */ + +/* Kinds of operands: + r Register in first field + R Register in second field + b Base register in first field + B Base register in second field + v Vector register in first field + V Vector register in first field + A Optional address register (base register) + X Optional index register + I Immediate data (16bits signed) + O Offset field (16bits signed) + h Offset field (15bits signed) + d Offset field (14bits signed) + S Shift count field + + any other characters are printed as is... +*/ + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ +struct gld_opcode gld_opcodes[] = +{ +{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, +{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, +{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, +{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, +{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, +{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, +{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, +{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, +{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, +{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, +{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, +{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, +{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, +{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, +{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, +{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, +{ "bei", 0x00060000, 0xffff0000, "", 2 }, +{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, +{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, +{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, +{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, +{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, +{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, +{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, +{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, +{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, +{ "call", 0x28080000, 0xfc0f0000, "", 2 }, +{ "callm", 0x5c080000, 0xff880000, "", 4 }, +{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, +{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, +{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, +{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, +{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, +{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, +{ "cea", 0x000f0000, 0xffff0000, "", 2 }, +{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, +{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, +{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, +{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, +{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, +{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, +{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, +{ "dae", 0x000e0000, 0xffff0000, "", 2 }, +{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, +{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, +{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, +{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, +{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, +{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, +{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "eae", 0x00080000, 0xffff0000, "", 2 }, +{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, +{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, +{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, +{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, +{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, +{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, +{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, +{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, +{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, +{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, +{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, +{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, +{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, +{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, +{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, +{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, +{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, +{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, +{ "halt", 0x00000000, 0xffff0000, "", 2 }, +{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, +{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, +{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, +{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, +{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, +{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, +{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, +{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, +{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, +{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, +{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, +{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, +{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, +{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, +{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, +{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, +{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, +{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, +{ "nop", 0x00020000, 0xffff0000, "", 2 }, +{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, +{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, +{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, +{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, +{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, +{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, +{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, +{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, +{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, +{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, +{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, +{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, +{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, +{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, +{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, +{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, +{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, +{ "sea", 0x000d0000, 0xffff0000, "", 2 }, +{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, +{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, +{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, +{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, +{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, +{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, +{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, +{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, +{ "smc", 0x04070000, 0xfc070000, "", 2 }, +{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, +{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, +{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, +{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, +{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, +{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, +{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, +{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, +{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, +{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, +{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, +{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, +{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, +{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, +{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, +{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, +{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, +{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, +{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, +{ "svc", 0xc8060000, 0xffff0000, "", 4 }, +{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, +{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, +{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, +{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, +{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, +{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, +{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, +{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, +{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, +{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, +{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, +{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, +{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, +{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, +{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, +{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, +{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, +{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, +{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, +{ "uei", 0x00070000, 0xffff0000, "", 2 }, +{ "wait", 0x00010000, 0xffff0000, "", 2 }, +{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, +{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, +{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, +{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, +{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, +{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, +{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, +{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, +{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, +{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, +{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, +{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, +}; + +int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); + +struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / + sizeof(gld_opcodes[0]); diff --git a/external/gpl3/gdb/dist/include/opcode/ppc.h b/external/gpl3/gdb/dist/include/opcode/ppc.h new file mode 100644 index 000000000000..a0119dc0a9a3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/ppc.h @@ -0,0 +1,365 @@ +/* ppc.h -- Header file for PowerPC opcode table + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, + 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef PPC_H +#define PPC_H + +#include "bfd_stdint.h" + +typedef uint64_t ppc_cpu_t; + +/* The opcode table is an array of struct powerpc_opcode. */ + +struct powerpc_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + ppc_cpu_t flags; + + /* One bit flags for the opcode. These are used to indicate which + specific processors no longer support the instructions. The defined + values are listed below. */ + ppc_cpu_t deprecated; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct powerpc_opcode powerpc_opcodes[]; +extern const int powerpc_num_opcodes; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* Opcode is defined for the PowerPC architecture. */ +#define PPC_OPCODE_PPC 1 + +/* Opcode is defined for the POWER (RS/6000) architecture. */ +#define PPC_OPCODE_POWER 2 + +/* Opcode is defined for the POWER2 (Rios 2) architecture. */ +#define PPC_OPCODE_POWER2 4 + +/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 + is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, + but it also supports many additional POWER instructions. */ +#define PPC_OPCODE_601 8 + +/* Opcode is supported in both the Power and PowerPC architectures + (ie, compiler's -mcpu=common or assembler's -mcom). More than just + the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER + and PPC_OPCODE_POWER2 because many instructions changed mnemonics + between POWER and POWERPC. */ +#define PPC_OPCODE_COMMON 0x10 + +/* Opcode is supported for any Power or PowerPC platform (this is + for the assembler's -many option, and it eliminates duplicates). */ +#define PPC_OPCODE_ANY 0x20 + +/* Opcode is only defined on 64 bit architectures. */ +#define PPC_OPCODE_64 0x40 + +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE 0x80 + +/* Opcode is supported by Altivec Vector Unit */ +#define PPC_OPCODE_ALTIVEC 0x100 + +/* Opcode is supported by PowerPC 403 processor. */ +#define PPC_OPCODE_403 0x200 + +/* Opcode is supported by PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE 0x400 + +/* Opcode is supported by PowerPC 440 processor. */ +#define PPC_OPCODE_440 0x800 + +/* Opcode is only supported by Power4 architecture. */ +#define PPC_OPCODE_POWER4 0x1000 + +/* Opcode is only supported by Power7 architecture. */ +#define PPC_OPCODE_POWER7 0x2000 + +/* Opcode is only supported by e500x2 Core. */ +#define PPC_OPCODE_SPE 0x4000 + +/* Opcode is supported by e500x2 Integer select APU. */ +#define PPC_OPCODE_ISEL 0x8000 + +/* Opcode is an e500 SPE floating point instruction. */ +#define PPC_OPCODE_EFS 0x10000 + +/* Opcode is supported by branch locking APU. */ +#define PPC_OPCODE_BRLOCK 0x20000 + +/* Opcode is supported by performance monitor APU. */ +#define PPC_OPCODE_PMR 0x40000 + +/* Opcode is supported by cache locking APU. */ +#define PPC_OPCODE_CACHELCK 0x80000 + +/* Opcode is supported by machine check APU. */ +#define PPC_OPCODE_RFMCI 0x100000 + +/* Opcode is only supported by Power5 architecture. */ +#define PPC_OPCODE_POWER5 0x200000 + +/* Opcode is supported by PowerPC e300 family. */ +#define PPC_OPCODE_E300 0x400000 + +/* Opcode is only supported by Power6 architecture. */ +#define PPC_OPCODE_POWER6 0x800000 + +/* Opcode is only supported by PowerPC Cell family. */ +#define PPC_OPCODE_CELL 0x1000000 + +/* Opcode is supported by CPUs with paired singles support. */ +#define PPC_OPCODE_PPCPS 0x2000000 + +/* Opcode is supported by Power E500MC */ +#define PPC_OPCODE_E500MC 0x4000000 + +/* Opcode is supported by PowerPC 405 processor. */ +#define PPC_OPCODE_405 0x8000000 + +/* Opcode is supported by Vector-Scalar (VSX) Unit */ +#define PPC_OPCODE_VSX 0x10000000 + +/* Opcode is supported by A2. */ +#define PPC_OPCODE_A2 0x20000000 + +/* Opcode is supported by PowerPC 476 processor. */ +#define PPC_OPCODE_476 0x40000000 + +/* Opcode is supported by AppliedMicro Titan core */ +#define PPC_OPCODE_TITAN 0x80000000 + +/* Opcode which is supported by the e500 family */ +#define PPC_OPCODE_E500 0x100000000ull + +/* A macro to extract the major opcode from an instruction. */ +#define PPC_OP(i) (((i) >> 26) & 0x3f) + +/* The operands table is an array of struct powerpc_operand. */ + +struct powerpc_operand +{ + /* A bitmask of bits in the operand. */ + unsigned int bitm; + + /* How far the operand is left shifted in the instruction. + -1 to indicate that BITM and SHIFT cannot be used to determine + where the operand goes in the insn. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & o->bitm) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the operand value). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (*insert) + (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = (i >> o->shift) & o->bitm; + if ((o->flags & PPC_OPERAND_SIGNED) != 0) + sign_extend (op); + (i is the instruction, o is a pointer to this structure, and op + is the result). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); + + /* One bit syntax flags. */ + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct powerpc_operand powerpc_operands[]; +extern const unsigned int num_powerpc_operands; + +/* Values defined for the flags field of a struct powerpc_operand. */ + +/* This operand takes signed values. */ +#define PPC_OPERAND_SIGNED (0x1) + +/* This operand takes signed values, but also accepts a full positive + range of values when running in 32 bit mode. That is, if bits is + 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, + this flag is ignored. */ +#define PPC_OPERAND_SIGNOPT (0x2) + +/* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics such as mr, for which two + operands fields are identical. The assembler should call the + insert function with any op value. The disassembler should call + the extract function, ignore the return value, and check the value + placed in the valid argument. */ +#define PPC_OPERAND_FAKE (0x4) + +/* The next operand should be wrapped in parentheses rather than + separated from this one by a comma. This is used for the load and + store instructions which want their operands to look like + reg,displacement(reg) + */ +#define PPC_OPERAND_PARENS (0x8) + +/* This operand may use the symbolic names for the CR fields, which + are + lt 0 gt 1 eq 2 so 3 un 3 + cr0 0 cr1 1 cr2 2 cr3 3 + cr4 4 cr5 5 cr6 6 cr7 7 + These may be combined arithmetically, as in cr2*4+gt. These are + only supported on the PowerPC, not the POWER. */ +#define PPC_OPERAND_CR (0x10) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define PPC_OPERAND_GPR (0x20) + +/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ +#define PPC_OPERAND_GPR_0 (0x40) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define PPC_OPERAND_FPR (0x80) + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_RELATIVE (0x100) + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_ABSOLUTE (0x200) + +/* This operand is optional, and is zero if omitted. This is used for + example, in the optional BF field in the comparison instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define PPC_OPERAND_OPTIONAL (0x400) + +/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand + is omitted, then for the next operand use this operand value plus + 1, ignoring the next operand field for the opcode. This wretched + hack is needed because the Power rotate instructions can take + either 4 or 5 operands. The disassembler should print this operand + out regardless of the PPC_OPERAND_OPTIONAL field. */ +#define PPC_OPERAND_NEXT (0x800) + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define PPC_OPERAND_NEGATIVE (0x1000) + +/* This operand names a vector unit register. The disassembler + prints these with a leading 'v'. */ +#define PPC_OPERAND_VR (0x2000) + +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (0x4000) + +/* This operand is for the DQ field in a DQ form instruction. */ +#define PPC_OPERAND_DQ (0x8000) + +/* Valid range of operand is 0..n rather than 0..n-1. */ +#define PPC_OPERAND_PLUS1 (0x10000) + +/* Xilinx APU and FSL related operands */ +#define PPC_OPERAND_FSL (0x20000) +#define PPC_OPERAND_FCR (0x40000) +#define PPC_OPERAND_UDI (0x80000) + +/* This operand names a vector-scalar unit register. The disassembler + prints these with a leading 'vs'. */ +#define PPC_OPERAND_VSR (0x100000) + +/* The POWER and PowerPC assemblers use a few macros. We keep them + with the operands table for simplicity. The macro table is an + array of struct powerpc_macro. */ + +struct powerpc_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct powerpc_opcode flags field. */ + ppc_cpu_t flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct powerpc_macro powerpc_macros[]; +extern const int powerpc_num_macros; + +extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, const char *); + +#endif /* PPC_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/pyr.h b/external/gpl3/gdb/dist/include/opcode/pyr.h new file mode 100644 index 000000000000..2fffd946213b --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/pyr.h @@ -0,0 +1,305 @@ +/* pyramid.opcode.h -- gdb initial attempt. + + Copyright 2001, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* pyramid opcode table: wot to do with this + particular opcode */ + +struct pyr_datum +{ + char nargs; + char * args; /* how to compile said opcode */ + unsigned long mask; /* Bit vector: which operand modes are valid + for this opcode */ + unsigned char code; /* op-code (always 6(?) bits */ +}; + +typedef struct pyr_insn_format +{ + unsigned int mode :4; + unsigned int operator :8; + unsigned int index_scale :2; + unsigned int index_reg :6; + unsigned int operand_1 :6; + unsigned int operand_2:6; +} pyr_insn_format; + + +/* We store four bytes of opcode for all opcodes. + Pyramid is sufficiently RISCy that: + - insns are always an integral number of words; + - the length of any insn can be told from the first word of + the insn. (ie, if there are zero, one, or two words of + immediate operand/offset). + + + The args component is a string containing two characters for each + operand of the instruction. The first specifies the kind of operand; + the second, the place it is stored. */ + +/* Kinds of operands: + mask assembler syntax description + 0x0001: movw Rn,Rn register to register + 0x0002: movw K,Rn quick immediate to register + 0x0004: movw I,Rn long immediate to register + 0x0008: movw (Rn),Rn register indirect to register + movw (Rn)[x],Rn register indirect to register + 0x0010: movw I(Rn),Rn offset register indirect to register + movw I(Rn)[x],Rn offset register indirect, indexed, to register + + 0x0020: movw Rn,(Rn) register to register indirect + 0x0040: movw K,(Rn) quick immediate to register indirect + 0x0080: movw I,(Rn) long immediate to register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + + 0x0400: movw Rn,I(Rn) register to register indirect+offset + 0x0800: movw K,I(Rn) quick immediate to register indirect+offset + 0x1000: movw I,I(Rn) long immediate to register indirect+offset + 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset + 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect + +offset + 0x0000: (irregular) ??? + + + Each insn has a four-bit field encoding the type(s) of its operands. +*/ + +/* Some common combinations + */ + +/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ +#define GEN_TO_REG (31) + +#define UNKNOWN ((unsigned long)-1) +#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) + +#define CONVERT (1|8|0x10|0x20|0x200) + +#define K_TO_REG (2) +#define I_TO_REG (4) +#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) +#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ + +struct pyr_opcode /* pyr opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct pyr_datum datum; /* rest of opcode table [datum] */ +}; + +#define pyr_how args +#define pyr_nargs nargs +#define pyr_mask mask +#define pyr_name name + +struct pyr_opcode pyr_opcodes[] = +{ + {"movb", { 2, "", UNKNOWN, 0x11}, }, + {"movh", { 2, "", UNKNOWN, 0x12} }, + {"movw", { 2, "", ANY, 0x10} }, + {"movl", { 2, "", ANY, 0x13} }, + {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, + {"mnegf", { 2, "", 0x1, 0x15} }, + {"mnegd", { 2, "", 0x1, 0x16} }, + {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, + {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, + {"mabsf", { 2, "", 0x1, 0x19} }, + {"mabsd", { 2, "", 0x1, 0x1a} }, + {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, + {"mtstf", { 2, "", 0x1, 0x1d} }, + {"mtstd", { 2, "", 0x1, 0x1e} }, + {"mova", { 2, "", 0x8|0x10, 0x1f} }, + {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, + {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, + /* 2 insns out of order here */ + {"movbl", { 2, "", 1, 0x4f} }, + {"filbl", { 2, "", 1, 0x4e} }, + + {"cvtbw", { 2, "", CONVERT, 0x22} }, + {"cvthw", { 2, "", CONVERT, 0x23} }, + {"cvtwb", { 2, "", CONVERT, 0x24} }, + {"cvtwh", { 2, "", CONVERT, 0x25} }, + {"cvtwf", { 2, "", CONVERT, 0x26} }, + {"cvtwd", { 2, "", CONVERT, 0x27} }, + {"cvtfw", { 2, "", CONVERT, 0x28} }, + {"cvtfd", { 2, "", CONVERT, 0x29} }, + {"cvtdw", { 2, "", CONVERT, 0x2a} }, + {"cvtdf", { 2, "", CONVERT, 0x2b} }, + + {"addw", { 2, "", GEN_TO_REG, 0x40} }, + {"addwc", { 2, "", GEN_TO_REG, 0x41} }, + {"subw", { 2, "", GEN_TO_REG, 0x42} }, + {"subwb", { 2, "", GEN_TO_REG, 0x43} }, + {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, + {"mulw", { 2, "", GEN_TO_REG, 0x45} }, + {"emul", { 2, "", GEN_TO_REG, 0x47} }, + {"umulw", { 2, "", GEN_TO_REG, 0x46} }, + {"divw", { 2, "", GEN_TO_REG, 0x48} }, + {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, + {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, + {"udivw", { 2, "", GEN_TO_REG, 0x49} }, + {"modw", { 2, "", GEN_TO_REG, 0x4c} }, + {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, + + + {"addf", { 2, "", 1, 0x50} }, + {"addd", { 2, "", 1, 0x51} }, + {"subf", { 2, "", 1, 0x52} }, + {"subd", { 2, "", 1, 0x53} }, + {"mulf", { 2, "", 1, 0x56} }, + {"muld", { 2, "", 1, 0x57} }, + {"divf", { 2, "", 1, 0x58} }, + {"divd", { 2, "", 1, 0x59} }, + + + {"cmpb", { 2, "", UNKNOWN, 0x61} }, + {"cmph", { 2, "", UNKNOWN, 0x62} }, + {"cmpw", { 2, "", UNKNOWN, 0x60} }, + {"ucmpb", { 2, "", UNKNOWN, 0x66} }, + /* WHY no "ucmph"??? */ + {"ucmpw", { 2, "", UNKNOWN, 0x65} }, + {"xchw", { 2, "", UNKNOWN, 0x0f} }, + + + {"andw", { 2, "", GEN_TO_REG, 0x30} }, + {"orw", { 2, "", GEN_TO_REG, 0x31} }, + {"xorw", { 2, "", GEN_TO_REG, 0x32} }, + {"bicw", { 2, "", GEN_TO_REG, 0x33} }, + {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, + {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, + {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, + {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, + {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, + {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, + {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, + + /* push and pop insns are "going away next release". */ + {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, + {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, + {"pusha", { 2, "", (0x8|0x10), 0x0e} }, + + {"bitsw", { 2, "", UNKNOWN, 0x35} }, + {"bitcw", { 2, "", UNKNOWN, 0x36} }, + /* some kind of ibra/dbra insns??*/ + {"icmpw", { 2, "", UNKNOWN, 0x67} }, + {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ + {"acmpw", { 2, "", 1, 0x6b} }, + + /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op + insn with a 2nd op of tr14. The assembler will have to grok this. */ + {"call", { 2, "", GEN_TO_REG, 0x04} }, + {"call", { 1, "", GEN_TO_REG, 0x04} }, + + {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ + /* Ret is usually written as a 0-op insn, but gets disassembled as a + 1-op insn. The operand is always tr15. */ + {"ret", { 0, "", UNKNOWN, 0x09} }, + {"ret", { 1, "", UNKNOWN, 0x09} }, + {"adsf", { 2, "", (1|2|4), 0x08} }, + {"retd", { 2, "", UNKNOWN, 0x0a} }, + {"btc", { 2, "", UNKNOWN, 0x01} }, + {"bfc", { 2, "", UNKNOWN, 0x02} }, + /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ + {"jump", { 1, "", UNKNOWN, 0x00} }, + {"btp", { 2, "", UNKNOWN, 0xf00} }, + /* read control-stack pointer is another 1-or-2 operand insn. */ + {"rcsp", { 2, "", UNKNOWN, 0x01f} }, + {"rcsp", { 1, "", UNKNOWN, 0x01f} } +}; + +/* end: pyramid.opcode.h */ +/* One day I will have to take the time to find out what operands + are valid for these insns, and guess at what they mean. + + I can't imagine what the "I???" insns (iglob, etc) do. + + the arithmetic-sounding insns ending in "p" sound awfully like BCD + arithmetic insns: + dshlp -> Decimal SHift Left Packed + dshrp -> Decimal SHift Right Packed + and cvtlp would be convert long to packed. + I have no idea how the operands are interpreted; but having them be + a long register with (address, length) of an in-memory packed BCD operand + would not be surprising. + They are unlikely to be a packed bcd string: 64 bits of long give + is only 15 digits+sign, which isn't enough for COBOL. + */ +#if 0 + {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ + /* The OSx Operating System Porting Guide claims SSL does things + with tr12 (a register reserved to it) to do with static block-structure + references. SSL=Set Static Link? It's "Going away next release". */ + {"ssl", { 2, "", UNKNOWN, 0x00} }, + {"ccmps", { 2, "", UNKNOWN, 0x00} }, + {"lcd", { 2, "", UNKNOWN, 0x00} }, + {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ + {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ + {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ + {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ + {"ldti", { 2, "", UNKNOWN, 0x00} }, + {"ldb", { 2, "", UNKNOWN, 0x00} }, + {"stp", { 2, "", UNKNOWN, 0x00} }, + {"stti", { 2, "", UNKNOWN, 0x00} }, + {"stb", { 2, "", UNKNOWN, 0x00} }, + {"stu", { 2, "", UNKNOWN, 0x00} }, + {"addp", { 2, "", UNKNOWN, 0x00} }, + {"subp", { 2, "", UNKNOWN, 0x00} }, + {"mulp", { 2, "", UNKNOWN, 0x00} }, + {"divp", { 2, "", UNKNOWN, 0x00} }, + {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ + {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ + {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ + {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ + {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ + {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ + {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ + {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ + {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ + {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ + {"cmovs", { 2, "", UNKNOWN, 0x00} }, + {"rsubw", { 2, "", UNKNOWN, 0x00} }, + {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ + {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ + {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ + {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ + {"callr", { 2, "", UNKNOWN, 0x00} }, + {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ + {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ + {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ + {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ + {"ssi", { 2, "", UNKNOWN, 0x00} }, + {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ + {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ + {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ + {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ + {"flic", { 2, "", UNKNOWN, 0x00} }, + {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ + {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ + {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ + {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ + {"lamst", { 2, "", UNKNOWN, 0x00} }, + {"tio", { 2, "", UNKNOWN, 0x00} }, +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/rx.h b/external/gpl3/gdb/dist/include/opcode/rx.h new file mode 100644 index 000000000000..aa85fe4a9163 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/rx.h @@ -0,0 +1,215 @@ +/* Opcode decoder for the Renesas RX + Copyright 2008, 2009, 2010 + Free Software Foundation, Inc. + Written by DJ Delorie + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* The RX decoder in libopcodes is used by the simulator, gdb's + analyzer, and the disassembler. Given an opcode data source, + it decodes the next opcode into the following structures. */ + +typedef enum +{ + RX_AnySize = 0, + RX_Byte, /* undefined extension */ + RX_UByte, + RX_SByte, + RX_Word, /* undefined extension */ + RX_UWord, + RX_SWord, + RX_3Byte, + RX_Long, +} RX_Size; + +typedef enum +{ + RX_Operand_None, + RX_Operand_Immediate, /* #addend */ + RX_Operand_Register, /* Rn */ + RX_Operand_Indirect, /* [Rn + addend] */ + RX_Operand_Postinc, /* [Rn+] */ + RX_Operand_Predec, /* [-Rn] */ + RX_Operand_Condition, /* eq, gtu, etc */ + RX_Operand_Flag, /* [UIOSZC] */ + RX_Operand_TwoReg, /* [Rn + scale*R2] */ +} RX_Operand_Type; + +typedef enum +{ + RXO_unknown, + RXO_mov, /* d = s (signed) */ + RXO_movbi, /* d = [s,s2] (signed) */ + RXO_movbir, /* [s,s2] = d (signed) */ + RXO_pushm, /* s..s2 */ + RXO_popm, /* s..s2 */ + RXO_xchg, /* s <-> d */ + RXO_stcc, /* d = s if cond(s2) */ + RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */ + + /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note + that d may be "None". */ + RXO_and, + RXO_or, + RXO_xor, + RXO_add, + RXO_sub, + RXO_mul, + RXO_div, + RXO_divu, + RXO_shll, + RXO_shar, + RXO_shlr, + + RXO_adc, /* d = d + s + carry */ + RXO_sbb, /* d = d - s - ~carry */ + RXO_abs, /* d = |s| */ + RXO_max, /* d = max(d,s) */ + RXO_min, /* d = min(d,s) */ + RXO_emul, /* d:64 = d:32 * s */ + RXO_emulu, /* d:64 = d:32 * s (unsigned) */ + + RXO_rolc, /* d <<= 1 through carry */ + RXO_rorc, /* d >>= 1 through carry*/ + RXO_rotl, /* d <<= #s without carry */ + RXO_rotr, /* d >>= #s without carry*/ + RXO_revw, /* d = revw(s) */ + RXO_revl, /* d = revl(s) */ + RXO_branch, /* pc = d if cond(s) */ + RXO_branchrel,/* pc += d if cond(s) */ + RXO_jsr, /* pc = d */ + RXO_jsrrel, /* pc += d */ + RXO_rts, + RXO_nop, + RXO_nop2, + RXO_nop3, + + RXO_scmpu, + RXO_smovu, + RXO_smovb, + RXO_suntil, + RXO_swhile, + RXO_smovf, + RXO_sstr, + + RXO_rmpa, + RXO_mulhi, + RXO_mullo, + RXO_machi, + RXO_maclo, + RXO_mvtachi, + RXO_mvtaclo, + RXO_mvfachi, + RXO_mvfacmi, + RXO_mvfaclo, + RXO_racw, + + RXO_sat, /* sat(d) */ + RXO_satr, + + RXO_fadd, /* d op= s */ + RXO_fcmp, + RXO_fsub, + RXO_ftoi, + RXO_fmul, + RXO_fdiv, + RXO_round, + RXO_itof, + + RXO_bset, /* d |= (1< = cond(s2) */ + + RXO_clrpsw, /* flag index in d */ + RXO_setpsw, /* flag index in d */ + RXO_mvtipl, /* new IPL in s */ + + RXO_rtfi, + RXO_rte, + RXO_rtd, /* undocumented */ + RXO_brk, + RXO_dbt, /* undocumented */ + RXO_int, /* vector id in s */ + RXO_stop, + RXO_wait, + + RXO_sccnd, /* d = cond(s) ? 1 : 0 */ +} RX_Opcode_ID; + +/* Condition bitpatterns, as registers. */ +#define RXC_eq 0 +#define RXC_z 0 +#define RXC_ne 1 +#define RXC_nz 1 +#define RXC_c 2 +#define RXC_nc 3 +#define RXC_gtu 4 +#define RXC_leu 5 +#define RXC_pz 6 +#define RXC_n 7 +#define RXC_ge 8 +#define RXC_lt 9 +#define RXC_gt 10 +#define RXC_le 11 +#define RXC_o 12 +#define RXC_no 13 +#define RXC_always 14 +#define RXC_never 15 + +typedef struct +{ + RX_Operand_Type type; + int reg; + int addend; + RX_Size size; +} RX_Opcode_Operand; + +typedef struct +{ + RX_Opcode_ID id; + int n_bytes; + int prefix; + char * syntax; + RX_Size size; + /* By convention, these are destination, source1, source2. */ + RX_Opcode_Operand op[3]; + + /* The logic here is: + newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s) + Only the O, S, Z, and C flags are affected. */ + char flags_0; /* This also clears out flags-to-be-set. */ + char flags_1; + char flags_s; +} RX_Opcode_Decoded; + +/* Within the syntax, %c-style format specifiers are as follows: + + %% = '%' character + %0 = operand[0] (destination) + %1 = operand[1] (source) + %2 = operand[2] (2nd source) + %s = operation size (b/w/l) + %SN = operand size [N] (N=0,1,2) + %aN = op[N] as an address (N=0,1,2) + + Register numbers 0..15 are general registers. 16..31 are control + registers. 32..47 are condition codes. */ + +int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *); diff --git a/external/gpl3/gdb/dist/include/opcode/s390.h b/external/gpl3/gdb/dist/include/opcode/s390.h new file mode 100644 index 000000000000..2cbe5f53d60c --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/s390.h @@ -0,0 +1,150 @@ +/* s390.h -- Header file for S390 opcode table + Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990, + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC, + S390_OPCODE_Z10, + S390_OPCODE_Z196, + S390_OPCODE_MAXCPU + }; + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name. */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of execution modes this opcode is available for. */ + unsigned int modes; + + /* First cpu this opcode is available for. */ + enum s390_opcode_cpu_val min_cpu; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +/* This operand is optional. Only a single operand at the end of + the instruction may be optional. */ +#define S390_OPERAND_OPTIONAL 0x400 + + #endif /* S390_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/score-datadep.h b/external/gpl3/gdb/dist/include/opcode/score-datadep.h new file mode 100644 index 000000000000..10ddf32f67fb --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/score-datadep.h @@ -0,0 +1,65 @@ +/* score-datadep.h -- Score Instructions data dependency table + Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING3. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifndef SCORE_DATA_DEPENDENCY_H +#define SCORE_DATA_DEPENDENCY_H + +#define INSN_NAME_LEN 16 + +enum insn_type_for_dependency +{ + D_mtcr, + D_all_insn +}; + +struct insn_to_dependency +{ + char *insn_name; + enum insn_type_for_dependency type; +}; + +struct data_dependency +{ + enum insn_type_for_dependency pre_insn_type; + char pre_reg[6]; + enum insn_type_for_dependency cur_insn_type; + char cur_reg[6]; + int bubblenum_7; + int bubblenum_3; + int warn_or_error; /* warning - 0; error - 1 */ +}; + +static const struct insn_to_dependency insn_to_dependency_table[] = +{ + /* move spectial instruction. */ + {"mtcr", D_mtcr}, +}; + +static const struct data_dependency data_dependency_table[] = +{ + /* Status regiser. */ + {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0}, +}; + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/score-inst.h b/external/gpl3/gdb/dist/include/opcode/score-inst.h new file mode 100644 index 000000000000..ecb18da2a918 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/score-inst.h @@ -0,0 +1,236 @@ +/* score-inst.h -- Score Instructions Table + Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING3. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef SCORE_INST_H +#define SCORE_INST_H + +#define LDST_UNALIGN_MASK 0x0000007f +#define UA_LCB 0x00000060 +#define UA_LCW 0x00000062 +#define UA_LCE 0x00000066 +#define UA_SCB 0x00000068 +#define UA_SCW 0x0000006a +#define UA_SCE 0x0000006e +#define UA_LL 0x0000000c +#define UA_SC 0x0000000e +#define LDST16_RR_MASK 0x0000000f +#define N16_LW 8 +#define N16_LH 9 +#define N16_POP 10 +#define N16_LBU 11 +#define N16_SW 12 +#define N16_SH 13 +#define N16_PUSH 14 +#define N16_SB 15 +#define LDST16_RI_MASK 0x7007 +#define N16_LWP 0x7000 +#define N16_LHP 0x7001 +#define N16_LBUP 0x7003 +#define N16_SWP 0x7004 +#define N16_SHP 0x7005 +#define N16_SBP 0x7007 +#define N16_LIU 0x5000 + +#define OPC_PSEUDOLDST_MASK 0x00000007 + +enum +{ + INSN_LW = 0, + INSN_LH = 1, + INSN_LHU = 2, + INSN_LB = 3, + INSN_SW = 4, + INSN_SH = 5, + INSN_LBU = 6, + INSN_SB = 7, +}; + +/* Sub opcdoe opcode. */ +enum +{ + INSN16_LBU = 11, + INSN16_LH = 9, + INSN16_LW = 8, + INSN16_SB = 15, + INSN16_SH = 13, + INSN16_SW = 12, +}; + +enum +{ + LDST_NOUPDATE = 0, + LDST_PRE = 1, + LDST_POST = 2, +}; + +enum score_insn_type +{ + Rd_I4, + Rd_I5, + Rd_rvalueBP_I5, + Rd_lvalueBP_I5, + Rd_Rs_I5, + x_Rs_I5, + x_I5_x, + Rd_I8, + Rd_Rs_I14, + I15, + Rd_I16, + Rd_I30, + Rd_I32, + Rd_rvalueRs_SI10, + Rd_lvalueRs_SI10, + Rd_rvalueRs_preSI12, + Rd_rvalueRs_postSI12, + Rd_lvalueRs_preSI12, + Rd_lvalueRs_postSI12, + Rd_Rs_SI14, + Rd_rvalueRs_SI15, + Rd_lvalueRs_SI15, + Rd_SI5, + Rd_SI6, + Rd_SI16, + PC_DISP8div2, + PC_DISP11div2, + PC_DISP19div2, + PC_DISP24div2, + Rd_Rs_Rs, + x_Rs_x, + x_Rs_Rs, + Rd_Rs_x, + Rd_x_Rs, + Rd_x_x, + Rd_Rs, + Rd_HighRs, + Rd_lvalueRs, + Rd_rvalueRs, + Rd_lvalue32Rs, + Rd_rvalue32Rs, + x_Rs, + NO_OPD, + NO16_OPD, + OP5_rvalueRs_SI15, + I5_Rs_Rs_I5_OP5, + x_rvalueRs_post4, + Rd_rvalueRs_post4, + Rd_x_I5, + Rd_lvalueRs_post4, + x_lvalueRs_post4, + Rd_LowRs, + Rd_Rs_Rs_imm, + Insn_Type_PCE, + Insn_Type_SYN, + Insn_GP, + Insn_PIC, + Insn_internal, + Insn_BCMP, + Ra_I9_I5, +}; + +enum score_data_type +{ + _IMM4 = 0, + _IMM5, + _IMM8, + _IMM14, + _IMM15, + _IMM16, + _SIMM10 = 6, + _SIMM12, + _SIMM14, + _SIMM15, + _SIMM16, + _SIMM14_NEG = 11, + _IMM16_NEG, + _SIMM16_NEG, + _IMM20, + _IMM25, + _DISP8div2 = 16, + _DISP11div2, + _DISP19div2, + _DISP24div2, + _VALUE, + _VALUE_HI16, + _VALUE_LO16, + _VALUE_LDST_LO16 = 23, + _SIMM16_LA, + _IMM5_RSHIFT_1, + _IMM5_RSHIFT_2, + _SIMM16_LA_POS, + _IMM5_RANGE_8_31, + _IMM10_RSHIFT_2, + _GP_IMM15 = 30, + _GP_IMM14 = 31, + _SIMM16_pic = 42, /* Index in score_df_range. */ + _IMM16_LO16_pic = 43, + _IMM16_pic = 44, + + _SIMM5 = 45, + _SIMM6 = 46, + _IMM32 = 47, + _SIMM32 = 48, + _IMM11 = 49, + _IMM5_MULTI_LOAD = 50, +}; + +#define REG_TMP 1 + +#define OP_REG_TYPE (1 << 6) +#define OP_IMM_TYPE (1 << 7) +#define OP_SH_REGD (OP_REG_TYPE |20) +#define OP_SH_REGS1 (OP_REG_TYPE |15) +#define OP_SH_REGS2 (OP_REG_TYPE |10) +#define OP_SH_I (OP_IMM_TYPE | 1) +#define OP_SH_RI15 (OP_IMM_TYPE | 0) +#define OP_SH_I12 (OP_IMM_TYPE | 3) +#define OP_SH_DISP24 (OP_IMM_TYPE | 1) +#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) +#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) +#define OP_SH_I5 (OP_IMM_TYPE |10) +#define OP_SH_I10 (OP_IMM_TYPE | 5) +#define OP_SH_COPID (OP_IMM_TYPE | 5) +#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) +#define OP_SH_I15 (OP_IMM_TYPE |10) + +#define OP16_SH_REGD (OP_REG_TYPE | 8) +#define OP16_SH_REGS1 (OP_REG_TYPE | 4) +#define OP16_SH_I45 (OP_IMM_TYPE | 3) +#define OP16_SH_I8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) + +enum insn_class +{ + INSN_CLASS_16, + INSN_CLASS_32, + INSN_CLASS_48, + INSN_CLASS_PCE, + INSN_CLASS_SYN +}; + +/* s3_s7: Globals for both tc-score.c and elf32-score.c. */ +extern int score3; +extern int score7; + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/sparc.h b/external/gpl3/gdb/dist/include/opcode/sparc.h new file mode 100644 index 000000000000..0d6511c2a6b1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/sparc.h @@ -0,0 +1,237 @@ +/* Definitions for opcode table for the sparc. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, + 2003, 2005, 2010 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and + the GNU Binutils. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#include "ansidecl.h" + +/* The SPARC opcode table (and other related data) is defined in + the opcodes library in sparc-opc.c. If you change anything here, make + sure you fix up that file, and vice versa. */ + + /* FIXME-someday: perhaps the ,a's and such should be embedded in the + instruction's name rather than the args. This would make gas faster, pinsn + slower, but would mess up some macros a bit. xoxorich. */ + +/* List of instruction sets variations. + These values are such that each element is either a superset of a + preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P + returns non-zero. + The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. + Don't change this without updating sparc-opc.c. */ + +enum sparc_opcode_arch_val +{ + SPARC_OPCODE_ARCH_V6 = 0, + SPARC_OPCODE_ARCH_V7, + SPARC_OPCODE_ARCH_V8, + SPARC_OPCODE_ARCH_SPARCLET, + SPARC_OPCODE_ARCH_SPARCLITE, + /* V9 variants must appear last. */ + SPARC_OPCODE_ARCH_V9, + SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ + SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ + SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ +}; + +/* The highest architecture in the table. */ +#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) + +/* Given an enum sparc_opcode_arch_val, return the bitmask to use in + insn encoding/decoding. */ +#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) + +/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ +#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) + +/* Table of cpu variants. */ + +typedef struct sparc_opcode_arch +{ + const char *name; + /* Mask of sparc_opcode_arch_val's supported. + EG: For v7 this would be + (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). + These are short's because sparc_opcode.architecture is. */ + short supported; +} sparc_opcode_arch; + +extern const struct sparc_opcode_arch sparc_opcode_archs[]; + +/* Given architecture name, look up it's sparc_opcode_arch_val value. */ +extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); + +/* Return the bitmask of supported architectures for ARCH. */ +#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) + +/* Non-zero if ARCH1 conflicts with ARCH2. + IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ +#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ + (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH1)) \ + && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH2))) + +/* Structure of an opcode table entry. */ + +typedef struct sparc_opcode +{ + const char *name; + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ + const char *args; + /* This was called "delayed" in versions before the flags. */ + char flags; + short architecture; /* Bitmask of sparc_opcode_arch_val's. */ +} sparc_opcode; + +#define F_DELAYED 1 /* Delayed branch. */ +#define F_ALIAS 2 /* Alias for a "real" instruction. */ +#define F_UNBR 4 /* Unconditional branch. */ +#define F_CONDBR 8 /* Conditional branch. */ +#define F_JSR 16 /* Subroutine call. */ +#define F_FLOAT 32 /* Floating point instruction (not a branch). */ +#define F_FBR 64 /* Floating point branch. */ +/* FIXME: Add F_ANACHRONISTIC flag for v9. */ + +/* All sparc opcodes are 32 bits, except for the `set' instruction (really a + macro), which is 64 bits. It is handled as a special case. + + The match component is a mask saying which bits must match a particular + opcode in order for an instruction to be an instance of that opcode. + + The args component is a string containing one character for each operand of the + instruction. + + Kinds of operands: + # Number used by optimizer. It is ignored. + 1 rs1 register. + 2 rs2 register. + d rd register. + e frs1 floating point register. + v frs1 floating point register (double/even). + V frs1 floating point register (quad/multiple of 4). + f frs2 floating point register. + B frs2 floating point register (double/even). + R frs2 floating point register (quad/multiple of 4). + g frsd floating point register. + H frsd floating point register (double/even). + J frsd floating point register (quad/multiple of 4). + b crs1 coprocessor register + c crs2 coprocessor register + D crsd coprocessor register + m alternate space register (asr) in rd + M alternate space register (asr) in rs1 + h 22 high bits. + X 5 bit unsigned immediate + Y 6 bit unsigned immediate + 3 SIAM mode (3 bits). (v9b) + K MEMBAR mask (7 bits). (v9) + j 10 bit Immediate. (v9) + I 11 bit Immediate. (v9) + i 13 bit Immediate. + n 22 bit immediate. + k 2+14 bit PC relative immediate. (v9) + G 19 bit PC relative immediate. (v9) + l 22 bit PC relative immediate. + L 30 bit PC relative immediate. + a Annul. The annul bit is set. + A Alternate address space. Stored as 8 bits. + C Coprocessor state register. + F floating point state register. + p Processor state register. + N Branch predict clear ",pn" (v9) + T Branch predict set ",pt" (v9) + z %icc. (v9) + Z %xcc. (v9) + q Floating point queue. + r Single register that is both rs1 and rd. + O Single register that is both rs2 and rd. + Q Coprocessor queue. + S Special case. + t Trap base register. + w Window invalid mask register. + y Y register. + u sparclet coprocessor registers in rd position + U sparclet coprocessor registers in rs1 position + E %ccr. (v9) + s %fprs. (v9) + P %pc. (v9) + W %tick. (v9) + o %asi. (v9) + 6 %fcc0. (v9) + 7 %fcc1. (v9) + 8 %fcc2. (v9) + 9 %fcc3. (v9) + ! Privileged Register in rd (v9) + ? Privileged Register in rs1 (v9) + * Prefetch function constant. (v9) + x OPF field (v9 impdep). + 0 32/64 bit immediate for set or setx (v9) insns + _ Ancillary state register in rd (v9a) + / Ancillary state register in rs1 (v9a) + + The following chars are unused: (note: ,[] are used as punctuation) + [45]. */ + +#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ +#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ +#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ +#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ +#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ +#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ +#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ +#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ +#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ +#define F1(x) (OP (x)) +#define DISP30(x) ((x) & 0x3fffffff) +#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ +#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ +#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ +#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ +#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ +#define ASI_RS2(x) (SIMM13 (x)) +#define MEMBAR(x) ((x) & 0x7f) +#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ + +#define ANNUL (1 << 29) +#define BPRED (1 << 19) /* V9. */ +#define IMMED F3I (1) +#define RD_G0 RD (~0) +#define RS1_G0 RS1 (~0) +#define RS2_G0 RS2 (~0) + +extern const struct sparc_opcode sparc_opcodes[]; +extern const int sparc_num_opcodes; + +extern int sparc_encode_asi (const char *); +extern const char *sparc_decode_asi (int); +extern int sparc_encode_membar (const char *); +extern const char *sparc_decode_membar (int); +extern int sparc_encode_prefetch (const char *); +extern const char *sparc_decode_prefetch (int); +extern int sparc_encode_sparclet_cpreg (const char *); +extern const char *sparc_decode_sparclet_cpreg (int); + +/* Local Variables: + fill-column: 131 + comment-column: 0 + End: */ + diff --git a/external/gpl3/gdb/dist/include/opcode/spu-insns.h b/external/gpl3/gdb/dist/include/opcode/spu-insns.h new file mode 100644 index 000000000000..d6c260aaeeff --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/spu-insns.h @@ -0,0 +1,417 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2007, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* SPU Opcode Table + +-=-=-= FORMAT =-=-=- + + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ +RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT | + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ + 0 3 1 1 2 3 0 1 1 2 3 + 0 7 4 1 0 7 4 1 + + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ +RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT | + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ + 0 9 1 2 3 0 7 1 2 3 + 7 4 1 7 4 1 + + +----------+-----------------+-------+ +--------+-------------------+-------+ +RI16 | op | I16 | RT | RI18 | op | I18 | RT | + +----------+-----------------+-------+ +--------+-------------------+-------+ + 0 8 2 3 0 6 2 3 + 4 1 4 1 + + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ +RR | op | RB | RA | RT | LBT | op |RO| I16 | RO | + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ + 0 1 1 2 3 0 6 8 2 3 + 0 7 4 1 4 1 + + +------------+----+--+-------+-------+ + LBTI | op | // |RO| RA | RO | + +------------+----+--+-------+-------+ + 0 1 1 1 2 3 + 0 5 7 4 1 + +-=-=-= OPCODE =-=-=- + +OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this +case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700, +since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000. + +-=-=-= ASM_FORMAT =-=-=- + +RRR category RI7 category + ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4 + ASM_RI7 mnemonic RT, RA, I7 + +RI8 category RI10 category + ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10 + ASM_RI10 mnemonic RT, RA, R10 + ASM_RI10IDX mnemonic RT, I10(RA) + +RI16 category RI18 category + ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18 + ASM_RI16 mnemonic RT, I16 + ASM_RI16W mnemonic RT, I16W + +RR category LBT category + ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg + ASM_MTSPR mnemonic SA, RT + ASM_NOOP mnemonic LBTI category + ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA + ASM_RAB mnemonic RA, RB + ASM_RDCH mnemonic RT, CA + ASM_RR mnemonic RT, RA, RB + ASM_RT mnemonic RT + ASM_RTA mnemonic RT, RA + ASM_WRCH mnemonic CA, RT + +Note that RRR instructions have the names for RC and RT reversed from +what's in the ISA, in order to put RT in the same position it appears +for other formats. + +-=-=-= DEPENDENCY =-=-=- + +DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target. +The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits. +If the digit is 0, this means the corresponding register is not used in the instruction. +If the digit is 1, this means the corresponding register is used as a source in the instruction. +If the digit is 2, this means the corresponding register is used as a target in the instruction. +If the digit is 3, this means the corresponding register is used as both source and target in the instruction. +For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are +used as sources and RT is the target. + +-=-=-= PIPE =-=-=- + +This field shows which execution pipe is used for the instruction + +pipe0 execution pipelines: + FP6 SP floating pipeline + FP7 integer operations executed in SP floating pipeline + FPD DP floating pipeline + FX2 FXU pipeline + FX3 Rotate/Shift pipeline + FXB Byte pipeline + NOP No pipeline + +pipe1 execution pipelines: + BR Branch pipeline + LNOP No pipeline + LS Load/Store pipeline + SHUF Shuffle pipeline + SPR SPR/CH pipeline + +*/ + +#define _A0() {0} +#define _A1(a) {1,a} +#define _A2(a,b) {2,a,b} +#define _A3(a,b,c) {3,a,b,c} +#define _A4(a,b,c,d) {4,a,b,c,d} + +/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */ +/* 0[RC][RB][RA][RT] */ +/* 1:src, 2:target */ + +APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ +APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ +APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ +APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ +APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */ +APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */ +APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */ +APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ +APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ +APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ +APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ +APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ +APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ +APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ +APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ +APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ +APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */ +APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */ +APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ +APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ +APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */ +APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */ +APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ +APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ +APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */ +APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ +APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ +APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ +APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<I10) */ +APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */ +APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */ +APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */ +APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */ +APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */ +APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */ +APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ +APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ +APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ +APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ +APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ +APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ +APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ +APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ +APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<RB) */ +APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ +APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ +APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA>16 */ +APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ +APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ +APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<RB) */ +APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */ +APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */ + +#undef _A0 +#undef _A1 +#undef _A2 +#undef _A3 +#undef _A4 diff --git a/external/gpl3/gdb/dist/include/opcode/spu.h b/external/gpl3/gdb/dist/include/opcode/spu.h new file mode 100644 index 000000000000..c6468303bc0d --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/spu.h @@ -0,0 +1,125 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2010 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* These two enums are from rel_apu/common/spu_asm_format.h */ +/* definition of instruction format */ +typedef enum { + RRR, + RI18, + RI16, + RI10, + RI8, + RI7, + RR, + LBT, + LBTI, + IDATA, + UNKNOWN_IFORMAT +} spu_iformat; + +/* These values describe assembly instruction arguments. They indicate + * how to encode, range checking and which relocation to use. */ +typedef enum { + A_T, /* register at pos 0 */ + A_A, /* register at pos 7 */ + A_B, /* register at pos 14 */ + A_C, /* register at pos 21 */ + A_S, /* special purpose register at pos 7 */ + A_H, /* channel register at pos 7 */ + A_P, /* parenthesis, this has to separate regs from immediates */ + A_S3, + A_S6, + A_S7N, + A_S7, + A_U7A, + A_U7B, + A_S10B, + A_S10, + A_S11, + A_S11I, + A_S14, + A_S16, + A_S18, + A_R18, + A_U3, + A_U5, + A_U6, + A_U7, + A_U14, + A_X16, + A_U18, + A_MAX +} spu_aformat; + +enum spu_insns { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB + M_SPU_MAX +}; + +struct spu_opcode +{ + spu_iformat insn_type; + unsigned int opcode; + char *mnemonic; + int arg[5]; +}; + +#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) +#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) + +#define DECODE_INSN_RT(insn) (insn & 0x7f) +#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) +#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) +#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) + +#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) +#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) + +/* For branching, immediate loads, hbr and lqa/stqa. */ +#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) +#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) + +/* for stop */ +#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) + +/* For ila */ +#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) +#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) + +/* For rotate and shift and generate control mask */ +#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) +#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) + +/* For float <-> int conversion */ +#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) +#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) + +/* For hbr */ +#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) + diff --git a/external/gpl3/gdb/dist/include/opcode/tahoe.h b/external/gpl3/gdb/dist/include/opcode/tahoe.h new file mode 100644 index 000000000000..b5cee249ee44 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tahoe.h @@ -0,0 +1,213 @@ +/* + * Ported by the State University of New York at Buffalo by the Distributed + * Computer Systems Lab, Department of Computer Science, 1991. + */ + +#ifndef tahoe_opcodeT +#define tahoe_opcodeT int +#endif /* no tahoe_opcodeT */ + +struct vot_wot /* tahoe opcode table: wot to do with this */ + /* particular opcode */ +{ + char * args; /* how to compile said opcode */ + tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* tahoe opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "sinf", {"", 0x05 } }, +{ "ldf", {"rl", 0x06 } }, +{ "ldd", {"rq", 0x07 } }, +{ "addb2", {"rbmb", 0x08 } }, +{ "movb", {"rbwb", 0x09 } }, +{ "addw2", {"rwmw", 0x0a } }, +{ "movw", {"rwww", 0x0b } }, +{ "addl2", {"rlml", 0x0c } }, +{ "movl", {"rlwl", 0x0d } }, +{ "bbs", {"rlvlbw", 0x0e } }, +{ "nop", {"", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "brw", {"bw", 0x13 } }, +{ "cosf", {"", 0x15 } }, +{ "lnf", {"rl", 0x16 } }, +{ "lnd", {"rq", 0x17 } }, +{ "addb3", {"rbrbwb", 0x18 } }, +{ "cmpb", {"rbwb", 0x19 } }, +{ "addw3", {"rwrwww", 0x1a } }, +{ "cmpw", {"rwww", 0x1b } }, +{ "addl3", {"rlrlwl", 0x1c } }, +{ "cmpl", {"rlwl", 0x1d } }, +{ "bbc", {"rlvlbw", 0x1e } }, +{ "rei", {"", 0x20 } }, +{ "bneq", {"bb", 0x21 } }, +{ "bnequ", {"bb", 0x21 } }, +{ "cvtwl", {"rwwl", 0x23 } }, +{ "stf", {"wl", 0x26 } }, +{ "std", {"wq", 0x27 } }, +{ "subb2", {"rbmb", 0x28 } }, +{ "mcomb", {"rbwb", 0x29 } }, +{ "subw2", {"rwmw", 0x2a } }, +{ "mcomw", {"rwww", 0x2b } }, +{ "subl2", {"rlml", 0x2c } }, +{ "mcoml", {"rlwl", 0x2d } }, +{ "emul", {"rlrlrlwq", 0x2e } }, +{ "aoblss", {"rlmlbw", 0x2f } }, +{ "bpt", {"", 0x30 } }, +{ "beql", {"bb", 0x31 } }, +{ "beqlu", {"bb", 0x31 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "logf", {"", 0x35 } }, +{ "cmpf", {"rl", 0x36 } }, +{ "cmpd", {"rq", 0x37 } }, +{ "subb3", {"rbrbwb", 0x38 } }, +{ "bitb", {"rbrb", 0x39 } }, +{ "subw3", {"rwrwww", 0x3a } }, +{ "bitw", {"rwrw", 0x3b } }, +{ "subl3", {"rlrlwl", 0x3c } }, +{ "bitl", {"rlrl", 0x3d } }, +{ "ediv", {"rlrqwlwl", 0x3e } }, +{ "aobleq", {"rlmlbw", 0x3f } }, +{ "ret", {"", 0x40 } }, +{ "bgtr", {"bb", 0x41 } }, +{ "sqrtf", {"", 0x45 } }, +{ "cmpf2", {"rl", 0x46 } }, +{ "cmpd2", {"rqrq", 0x47 } }, +{ "shll", {"rbrlwl", 0x48 } }, +{ "clrb", {"wb", 0x49 } }, +{ "shlq", {"rbrqwq", 0x4a } }, +{ "clrw", {"ww", 0x4b } }, +{ "mull2", {"rlml", 0x4c } }, +{ "clrl", {"wl", 0x4d } }, +{ "shal", {"rbrlwl", 0x4e } }, +{ "bleq", {"bb", 0x51 } }, +{ "expf", {"", 0x55 } }, +{ "tstf", {"", 0x56 } }, +{ "tstd", {"", 0x57 } }, +{ "shrl", {"rbrlwl", 0x58 } }, +{ "tstb", {"rb", 0x59 } }, +{ "shrq", {"rbrqwq", 0x5a } }, +{ "tstw", {"rw", 0x5b } }, +{ "mull3", {"rlrlwl", 0x5c } }, +{ "tstl", {"rl", 0x5d } }, +{ "shar", {"rbrlwl", 0x5e } }, +{ "bbssi", {"rlmlbw", 0x5f } }, +{ "ldpctx", {"", 0x60 } }, +{ "pushd", {"", 0x67 } }, +{ "incb", {"mb", 0x69 } }, +{ "incw", {"mw", 0x6b } }, +{ "divl2", {"rlml", 0x6c } }, +{ "incl", {"ml", 0x6d } }, +{ "cvtlb", {"rlwb", 0x6f } }, +{ "svpctx", {"", 0x70 } }, +{ "jmp", {"ab", 0x71 } }, +{ "cvlf", {"rl", 0x76 } }, +{ "cvld", {"rl", 0x77 } }, +{ "decb", {"mb", 0x79 } }, +{ "decw", {"mw", 0x7b } }, +{ "divl3", {"rlrlwl", 0x7c } }, +{ "decl", {"ml", 0x7d } }, +{ "cvtlw", {"rlww", 0x7f } }, +{ "bgeq", {"bb", 0x81 } }, +{ "movs2", {"abab", 0x82 } }, +{ "cvfl", {"wl", 0x86 } }, +{ "cvdl", {"wl", 0x87 } }, +{ "orb2", {"rbmb", 0x88 } }, +{ "cvtbl", {"rbwl", 0x89 } }, +{ "orw2", {"rwmw", 0x8a } }, +{ "bispsw", {"rw", 0x8b } }, +{ "orl2", {"rlml", 0x8c } }, +{ "adwc", {"rlml", 0x8d } }, +{ "adda", {"rlml", 0x8e } }, +{ "blss", {"bb", 0x91 } }, +{ "cmps2", {"abab", 0x92 } }, +{ "ldfd", {"rl", 0x97 } }, +{ "orb3", {"rbrbwb", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "orw3", {"rwrwww", 0x9a } }, +{ "bicpsw", {"rw", 0x9b } }, +{ "orl3", {"rlrlwl", 0x9c } }, +{ "sbwc", {"rlml", 0x9d } }, +{ "suba", {"rlml", 0x9e } }, +{ "bgtru", {"bb", 0xa1 } }, +{ "cvdf", {"", 0xa6 } }, +{ "andb2", {"rbmb", 0xa8 } }, +{ "movzbl", {"rbwl", 0xa9 } }, +{ "andw2", {"rwmw", 0xaa } }, +{ "loadr", {"rwal", 0xab } }, +{ "andl2", {"rlml", 0xac } }, +{ "mtpr", {"rlrl", 0xad } }, +{ "ffs", {"rlwl", 0xae } }, +{ "blequ", {"bb", 0xb1 } }, +{ "negf", {"", 0xb6 } }, +{ "negd", {"", 0xb7 } }, +{ "andb3", {"rbrbwb", 0xb8 } }, +{ "movzbw", {"rbww", 0xb9 } }, +{ "andw3", {"rwrwww", 0xba } }, +{ "storer", {"rwal", 0xbb } }, +{ "andl3", {"rlrlwl", 0xbc } }, +{ "mfpr", {"rlwl", 0xbd } }, +{ "ffc", {"rlwl", 0xbe } }, +{ "calls", {"rbab", 0xbf } }, +{ "prober", {"rbabrl", 0xc0 } }, +{ "bvc", {"bb", 0xc1 } }, +{ "movs3", {"ababrw", 0xc2 } }, +{ "movzwl", {"rwwl", 0xc3 } }, +{ "addf", {"rl", 0xc6 } }, +{ "addd", {"rq", 0xc7 } }, +{ "xorb2", {"rbmb", 0xc8 } }, +{ "movob", {"rbwb", 0xc9 } }, +{ "xorw2", {"rwmw", 0xca } }, +{ "movow", {"rwww", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "movpsl", {"wl", 0xcd } }, +{ "kcall", {"rw", 0xcf } }, +{ "probew", {"rbabrl", 0xd0 } }, +{ "bvs", {"bb", 0xd1 } }, +{ "cmps3", {"ababrw", 0xd2 } }, +{ "subf", {"rq", 0xd6 } }, +{ "subd", {"rq", 0xd7 } }, +{ "xorb3", {"rbrbwb", 0xd8 } }, +{ "pushb", {"rb", 0xd9 } }, +{ "xorw3", {"rwrwww", 0xda } }, +{ "pushw", {"rw", 0xdb } }, +{ "xorl3", {"rlrlwl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "insque", {"abab", 0xe0 } }, +{ "bcs", {"bb", 0xe1 } }, +{ "bgequ", {"bb", 0xe1 } }, +{ "mulf", {"rq", 0xe6 } }, +{ "muld", {"rq", 0xe7 } }, +{ "mnegb", {"rbwb", 0xe8 } }, +{ "movab", {"abwl", 0xe9 } }, +{ "mnegw", {"rwww", 0xea } }, +{ "movaw", {"awwl", 0xeb } }, +{ "mnegl", {"rlwl", 0xec } }, +{ "moval", {"alwl", 0xed } }, +{ "remque", {"ab", 0xf0 } }, +{ "bcc", {"bb", 0xf1 } }, +{ "blssu", {"bb", 0xf1 } }, +{ "divf", {"rq", 0xf6 } }, +{ "divd", {"rq", 0xf7 } }, +{ "movblk", {"alalrw", 0xf8 } }, +{ "pushab", {"ab", 0xf9 } }, +{ "pushaw", {"aw", 0xfb } }, +{ "casel", {"rlrlrl", 0xfc } }, +{ "pushal", {"al", 0xfd } }, +{ "callf", {"rbab", 0xfe } }, +{ "" , "" } /* empty is end sentinel */ + +}; diff --git a/external/gpl3/gdb/dist/include/opcode/tic30.h b/external/gpl3/gdb/dist/include/opcode/tic30.h new file mode 100644 index 000000000000..3f4d30715241 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic30.h @@ -0,0 +1,691 @@ +/* tic30.h -- Header file for TI TMS320C30 opcode table + Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a + header file. */ + +#ifndef _TMS320_H_ +#define _TMS320_H_ + +struct _register +{ + char *name; + unsigned char opcode; + unsigned char regtype; +}; + +typedef struct _register reg; + +#define REG_Rn 0x01 +#define REG_ARn 0x02 +#define REG_DP 0x03 +#define REG_OTHER 0x04 + +static const reg tic30_regtab[] = { + { "r0", 0x00, REG_Rn }, + { "r1", 0x01, REG_Rn }, + { "r2", 0x02, REG_Rn }, + { "r3", 0x03, REG_Rn }, + { "r4", 0x04, REG_Rn }, + { "r5", 0x05, REG_Rn }, + { "r6", 0x06, REG_Rn }, + { "r7", 0x07, REG_Rn }, + { "ar0",0x08, REG_ARn }, + { "ar1",0x09, REG_ARn }, + { "ar2",0x0A, REG_ARn }, + { "ar3",0x0B, REG_ARn }, + { "ar4",0x0C, REG_ARn }, + { "ar5",0x0D, REG_ARn }, + { "ar6",0x0E, REG_ARn }, + { "ar7",0x0F, REG_ARn }, + { "dp", 0x10, REG_DP }, + { "ir0",0x11, REG_OTHER }, + { "ir1",0x12, REG_OTHER }, + { "bk", 0x13, REG_OTHER }, + { "sp", 0x14, REG_OTHER }, + { "st", 0x15, REG_OTHER }, + { "ie", 0x16, REG_OTHER }, + { "if", 0x17, REG_OTHER }, + { "iof",0x18, REG_OTHER }, + { "rs", 0x19, REG_OTHER }, + { "re", 0x1A, REG_OTHER }, + { "rc", 0x1B, REG_OTHER }, + { "R0", 0x00, REG_Rn }, + { "R1", 0x01, REG_Rn }, + { "R2", 0x02, REG_Rn }, + { "R3", 0x03, REG_Rn }, + { "R4", 0x04, REG_Rn }, + { "R5", 0x05, REG_Rn }, + { "R6", 0x06, REG_Rn }, + { "R7", 0x07, REG_Rn }, + { "AR0",0x08, REG_ARn }, + { "AR1",0x09, REG_ARn }, + { "AR2",0x0A, REG_ARn }, + { "AR3",0x0B, REG_ARn }, + { "AR4",0x0C, REG_ARn }, + { "AR5",0x0D, REG_ARn }, + { "AR6",0x0E, REG_ARn }, + { "AR7",0x0F, REG_ARn }, + { "DP", 0x10, REG_DP }, + { "IR0",0x11, REG_OTHER }, + { "IR1",0x12, REG_OTHER }, + { "BK", 0x13, REG_OTHER }, + { "SP", 0x14, REG_OTHER }, + { "ST", 0x15, REG_OTHER }, + { "IE", 0x16, REG_OTHER }, + { "IF", 0x17, REG_OTHER }, + { "IOF",0x18, REG_OTHER }, + { "RS", 0x19, REG_OTHER }, + { "RE", 0x1A, REG_OTHER }, + { "RC", 0x1B, REG_OTHER }, + { "", 0, 0 } +}; + +static const reg *const tic30_regtab_end + = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); + +/* Indirect Addressing Modes Modification Fields */ +/* Indirect Addressing with Displacement */ +#define PreDisp_Add 0x00 +#define PreDisp_Sub 0x01 +#define PreDisp_Add_Mod 0x02 +#define PreDisp_Sub_Mod 0x03 +#define PostDisp_Add_Mod 0x04 +#define PostDisp_Sub_Mod 0x05 +#define PostDisp_Add_Circ 0x06 +#define PostDisp_Sub_Circ 0x07 +/* Indirect Addressing with Index Register IR0 */ +#define PreIR0_Add 0x08 +#define PreIR0_Sub 0x09 +#define PreIR0_Add_Mod 0x0A +#define PreIR0_Sub_Mod 0x0B +#define PostIR0_Add_Mod 0x0C +#define PostIR0_Sub_Mod 0x0D +#define PostIR0_Add_Circ 0x0E +#define PostIR0_Sub_Circ 0x0F +/* Indirect Addressing with Index Register IR1 */ +#define PreIR1_Add 0x10 +#define PreIR1_Sub 0x11 +#define PreIR1_Add_Mod 0x12 +#define PreIR1_Sub_Mod 0x13 +#define PostIR1_Add_Mod 0x14 +#define PostIR1_Sub_Mod 0x15 +#define PostIR1_Add_Circ 0x16 +#define PostIR1_Sub_Circ 0x17 +/* Indirect Addressing (Special Cases) */ +#define IndirectOnly 0x18 +#define PostIR0_Add_BitRev 0x19 + +typedef struct { + char *syntax; + unsigned char modfield; + unsigned char displacement; +} ind_addr_type; + +#define IMPLIED_DISP 0x01 +#define DISP_REQUIRED 0x02 +#define NO_DISP 0x03 + +static const ind_addr_type tic30_indaddr_tab[] = { + { "*+ar", PreDisp_Add, IMPLIED_DISP }, + { "*-ar", PreDisp_Sub, IMPLIED_DISP }, + { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, + { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, + { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, + { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, + { "*+ar()", PreDisp_Add, DISP_REQUIRED }, + { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, + { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, + { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, + { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, + { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, + { "*+ar(ir0)", PreIR0_Add, NO_DISP }, + { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, + { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, + { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, + { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, + { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, + { "*+ar(ir1)", PreIR1_Add, NO_DISP }, + { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, + { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, + { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, + { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, + { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, + { "*ar", IndirectOnly, NO_DISP }, + { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, + { "", 0,0 } +}; + +static const ind_addr_type *const tic30_indaddrtab_end + = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); + +/* Possible operand types */ +/* Register types */ +#define Rn 0x0001 +#define ARn 0x0002 +#define DPReg 0x0004 +#define OtherReg 0x0008 +/* Addressing mode types */ +#define Direct 0x0010 +#define Indirect 0x0020 +#define Imm16 0x0040 +#define Disp 0x0080 +#define Imm24 0x0100 +#define Abs24 0x0200 +/* 3 operand addressing mode types */ +#define op3T1 0x0400 +#define op3T2 0x0800 +/* Interrupt vector */ +#define IVector 0x1000 +/* Not required */ +#define NotReq 0x2000 + +#define GAddr1 Rn | Direct | Indirect | Imm16 +#define GAddr2 GAddr1 | AllReg +#define TAddr1 op3T1 | Rn | Indirect +#define TAddr2 op3T2 | Rn | Indirect +#define Reg Rn | ARn +#define AllReg Reg | DPReg | OtherReg + +typedef struct _template +{ + char *name; + unsigned int operands; /* how many operands */ + unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define AddressMode 0x00600000 +#define PCRel 0x02000000 +#define StackOp 0x001F0000 +#define Rotate StackOp + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; + /* This defines the number type of an immediate argument to an instruction. */ + int imm_arg_type; +#define Imm_None 0 +#define Imm_Float 1 +#define Imm_SInt 2 +#define Imm_UInt 3 +} +insn_template; + +static const insn_template tic30_optab[] = { + { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, + { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, + { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, + { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, + { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, + { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, + { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, + { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, + { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, + { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ + { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, + { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, + { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, + { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, + { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, + { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, + { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, + { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, + { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, + { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, + { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, + { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, + { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, + { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, + { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, + { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, + { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, + { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, + { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, + { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, + { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, + { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, + { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, + { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, + { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, + { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, + { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, + { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, + { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, + { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, + { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, + { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, + { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } +}; + +static const insn_template *const tic30_optab_end = + tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); + +typedef struct { + char *name; + unsigned int operands_1; + unsigned int operands_2; + unsigned int base_opcode; + unsigned int operand_types[2][3]; + /* Which operand fits into which part of the final opcode word. */ + int oporder; +} partemplate; + +/* oporder defines - not very descriptive. */ +#define OO_4op1 0 +#define OO_4op2 1 +#define OO_4op3 2 +#define OO_5op1 3 +#define OO_5op2 4 +#define OO_PField 5 + +static const partemplate tic30_paroptab[] = { + { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } +}; + +static const partemplate *const tic30_paroptab_end = + tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); + +#endif diff --git a/external/gpl3/gdb/dist/include/opcode/tic4x.h b/external/gpl3/gdb/dist/include/opcode/tic4x.h new file mode 100644 index 000000000000..6f16fcb404ee --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic4x.h @@ -0,0 +1,1079 @@ +/* Table of opcodes for the Texas Instruments TMS320C[34]X family. + + Copyright (C) 2002, 2003, 2010 Free Software Foundation. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) +#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44) + +/* Define some bitfield extraction/insertion macros. */ +#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) +#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) +#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) +#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) +#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) + +/* Define register numbers. */ +typedef enum + { + REG_R0, REG_R1, REG_R2, REG_R3, + REG_R4, REG_R5, REG_R6, REG_R7, + REG_AR0, REG_AR1, REG_AR2, REG_AR3, + REG_AR4, REG_AR5, REG_AR6, REG_AR7, + REG_DP, REG_IR0, REG_IR1, REG_BK, + REG_SP, REG_ST, REG_DIE, REG_IIE, + REG_IIF, REG_RS, REG_RE, REG_RC, + REG_R8, REG_R9, REG_R10, REG_R11, + REG_IVTP, REG_TVTP + } +c4x_reg_t; + +/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ + +#define REG_IE REG_DIE /* C3x only */ +#define REG_IF REG_IIE /* C3x only */ +#define REG_IOF REG_IIF /* C3x only */ + +#define TIC3X_REG_MAX REG_RC +#define TIC4X_REG_MAX REG_TVTP + +/* Register table size including C4x expansion regs. */ +#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) + +struct tic4x_register +{ + char * name; + unsigned long regno; +}; + +typedef struct tic4x_register tic4x_register_t; + +/* We could store register synonyms here. */ +static const tic4x_register_t tic3x_registers[] = +{ + {"f0", REG_R0}, + {"r0", REG_R0}, + {"f1", REG_R1}, + {"r1", REG_R1}, + {"f2", REG_R2}, + {"r2", REG_R2}, + {"f3", REG_R3}, + {"r3", REG_R3}, + {"f4", REG_R4}, + {"r4", REG_R4}, + {"f5", REG_R5}, + {"r5", REG_R5}, + {"f6", REG_R6}, + {"r6", REG_R6}, + {"f7", REG_R7}, + {"r7", REG_R7}, + {"ar0", REG_AR0}, + {"ar1", REG_AR1}, + {"ar2", REG_AR2}, + {"ar3", REG_AR3}, + {"ar4", REG_AR4}, + {"ar5", REG_AR5}, + {"ar6", REG_AR6}, + {"ar7", REG_AR7}, + {"dp", REG_DP}, + {"ir0", REG_IR0}, + {"ir1", REG_IR1}, + {"bk", REG_BK}, + {"sp", REG_SP}, + {"st", REG_ST}, + {"ie", REG_IE}, + {"if", REG_IF}, + {"iof", REG_IOF}, + {"rs", REG_RS}, + {"re", REG_RE}, + {"rc", REG_RC}, + {"", 0} +}; + +const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); + +/* Define C4x registers in addition to C3x registers. */ +static const tic4x_register_t tic4x_registers[] = +{ + {"die", REG_DIE}, /* Clobbers C3x REG_IE */ + {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ + {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ + {"f8", REG_R8}, + {"r8", REG_R8}, + {"f9", REG_R9}, + {"r9", REG_R9}, + {"f10", REG_R10}, + {"r10", REG_R10}, + {"f11", REG_R11}, + {"r11", REG_R11}, + {"ivtp", REG_IVTP}, + {"tvtp", REG_TVTP}, + {"", 0} +}; + +const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); + +struct tic4x_cond +{ + char * name; + unsigned long cond; +}; + +typedef struct tic4x_cond tic4x_cond_t; + +/* Define conditional branch/load suffixes. Put desired form for + disassembler last. */ +static const tic4x_cond_t tic4x_conds[] = +{ + { "u", 0x00 }, + { "c", 0x01 }, { "lo", 0x01 }, + { "ls", 0x02 }, + { "hi", 0x03 }, + { "nc", 0x04 }, { "hs", 0x04 }, + { "z", 0x05 }, { "eq", 0x05 }, + { "nz", 0x06 }, { "ne", 0x06 }, + { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, + { "le", 0x08 }, + { "p", 0x09 }, { "gt", 0x09 }, + { "nn", 0x0a }, { "ge", 0x0a }, + { "nv", 0x0c }, + { "v", 0x0d }, + { "nuf", 0x0e }, + { "uf", 0x0f }, + { "nlv", 0x10 }, + { "lv", 0x11 }, + { "nluf", 0x12 }, + { "luf", 0x13 }, + { "zuf", 0x14 }, + /* Dummy entry, not included in num_conds. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); + +struct tic4x_indirect +{ + char * name; + unsigned long modn; +}; + +typedef struct tic4x_indirect tic4x_indirect_t; + +/* Define indirect addressing modes where: + d displacement (signed) + y ir0 + z ir1 */ + +static const tic4x_indirect_t tic4x_indirects[] = +{ + { "*+a(d)", 0x00 }, + { "*-a(d)", 0x01 }, + { "*++a(d)", 0x02 }, + { "*--a(d)", 0x03 }, + { "*a++(d)", 0x04 }, + { "*a--(d)", 0x05 }, + { "*a++(d)%", 0x06 }, + { "*a--(d)%", 0x07 }, + { "*+a(y)", 0x08 }, + { "*-a(y)", 0x09 }, + { "*++a(y)", 0x0a }, + { "*--a(y)", 0x0b }, + { "*a++(y)", 0x0c }, + { "*a--(y)", 0x0d }, + { "*a++(y)%", 0x0e }, + { "*a--(y)%", 0x0f }, + { "*+a(z)", 0x10 }, + { "*-a(z)", 0x11 }, + { "*++a(z)", 0x12 }, + { "*--a(z)", 0x13 }, + { "*a++(z)", 0x14 }, + { "*a--(z)", 0x15 }, + { "*a++(z)%", 0x16 }, + { "*a--(z)%", 0x17 }, + { "*a", 0x18 }, + { "*a++(y)b", 0x19 }, + /* Dummy entry, not included in num_indirects. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +#define TIC3X_MODN_MAX 0x19 + +const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); + +/* Instruction template. */ +struct tic4x_inst +{ + char * name; + unsigned long opcode; + unsigned long opmask; + char * args; + unsigned long oplevel; +}; + +typedef struct tic4x_inst tic4x_inst_t; + +/* Opcode infix + B condition 16--20 U,C,Z,LO,HI, etc. + C condition 23--27 U,C,Z,LO,HI, etc. + + Arguments + , required arg follows + ; optional arg follows + + Argument types bits [classes] - example + ----------------------------------------------------------- + * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0) + # direct (for LDP) 0--15 [Z] - @start, start + @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start + A address register 22--24 [D] - AR0, AR7 + B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x) + C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5) + E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1 + G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + H register (0-7) 18--16 [LS,M,P,Q] - R0, R7 + I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5 + J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + j indirect (enhanced) 8--15 [M] - *+AR0(1), R5 + K register 19--21 [LL,M,Q,QC] - R0, R7 + L register 22--24 [LL,LS,P,Q,QC] - R0, R7 + M register (R2,R3) 22--22 [M] R2, R3 + N register (R0,R1) 23--23 [M] R0, R1 + O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5) + P displacement (PC Rel) 0--15 [D,J,JS] - @start, start + Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP + q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11 + R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP + r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11 + S short int immediate 0--15 [A,AB,AY,BI] - -5, 5 + T integer (C4x) 16--20 [Z] - -5, 12 + U unsigned integer 0--15 [AU,A3] - 0, 65535 + V vector (C4x: 0--8) 0--4 [Z] - 25, 7 + W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5 + X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP + Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0 + Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP +*/ + +#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ +#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */ + +/* Define the instruction level */ +#define OP_C3X 0x1 /* C30 support - supported by all */ +#define OP_C4X 0x2 /* C40 support - C40, C44 */ +#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type + I and J is enhanced in these classes - C31>=6.0, + C32>=2.0, C33 */ +#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0, + LC31, C31>=5.0, C32 */ +#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0, + C32, C33, C40>=5.0, C44 */ + +/* The following class definition is a classification scheme for + putting instructions with similar type of arguments together. It + simplifies the op-code definitions significantly, as we then only + need to use the class macroes for 95% of the DSP's opcodes. +*/ + +/* A: General 2-operand integer operations + Syntax: src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, + SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, + MBn, MHn, MPYSHI, MPYUHI +*/ +#define A_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,R", level } + +/* AB: General 2-operand integer operation with condition + Syntax: c src, dst + c = Condition + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 1/0 - LDIc +*/ +#define AB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \ + { name, opcode|0x40600000, 0xf0600000, "S,R", level } + +/* AU: General 2-operand unsigned integer operation + Syntax: src, dst + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + dst = Register (R) + Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn +*/ +#define AU_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "U,R", level } + +/* AF: General 2-operand float to integer operation + Syntax: src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register (R) + Instr: 1/0 - FIX +*/ +#define AF_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,R", level } + +/* A2: Limited 1-operand (integer) operation + Syntax: src + src = Register (Q), Indirect (*), None + Instr: 1/0 - NOP +*/ +#define A2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*", level }, \ + { name, opcode|0x00000000, 0xffe00000, "" , level } + +/* A3: General 1-operand unsigned integer operation + Syntax: src + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + Instr: 1/0 - RPTS +*/ +#define A3_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffff0000, "Q", level }, \ + { name, opcode|0x00200000, 0xffff0000, "@", level }, \ + { name, opcode|0x00400000, 0xffff0000, "*", level }, \ + { name, opcode|0x00600000, 0xffff0000, "U", level } + +/* A6: Limited 2-operand integer operation + Syntax: src, dst + src = Direct (@), Indirect (*) + dst = Register (R) + Instr: 1/1 - LDII, C4x: SIGI +*/ +#define A6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level } + +/* A7: Limited 2-operand integer store operation + Syntax: src, dst + src = Register (R) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STI, STII +*/ +#define A7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "R,*", level } + +/* AY: General 2-operand signed address load operation + Syntax: src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Address register - ARx, IRx, DP, BK, SP (Y) + Instr: 0/1 - C4x: LDA + Note: Q and Y should *never* be the same register +*/ +#define AY_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,Y", level } + +/* B: General 2-operand float operation + Syntax: src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, + SUBF, SUBRF, C4x: RSQRF, TOIEEE +*/ +#define B_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BA: General 2-operand integer to float operation + Syntax: src, dst + src = Register (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 0/1 - C4x: CRCPF +*/ +#define BA_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BB: General 2-operand conditional float operation + Syntax: c src, dst + c = Condition + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 1/0 - LDFc +*/ +#define BB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \ + { name, opcode|0x40600000, 0xf0600000, "F,r", level } + +/* BI: General 2-operand integer to float operation (yet different to BA) + Syntax: src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register 0-11 (r) + Instr: 1/0 - FLOAT +*/ +#define BI_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,r", level } + +/* B6: Limited 2-operand float operation + Syntax: src, dst + src = Direct (@), Indirect (*) + dst = Register 0-11 (r) + Instr: 1/1 - LDFI, C4x: FRIEEE +*/ +#define B6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level } + +/* B7: Limited 2-operand float store operation + Syntax: src, dst + src = Register 0-11 (r) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STF, STFI +*/ +#define B7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "r,*", level } + +/* D: Decrement and brach operations + Syntax: c ARn, dst + c = condition + ARn = AR register 0-7 (A) + dst = Register (Q), PC-relative (P) + Instr: 2/0 - DBc, DBcD + Alias: +*/ +#define D_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \ + { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name2, opcode|0x02000000, 0xfe200000, "A,P", level } + +/* I: General branch operations + Syntax: dst + dst = Address (B) + Instr: 3/1 - BR, BRD, CALL, C4x: LAJ +*/ + +/* I2: General branch operations (C4x addition) + Syntax: dst + dst = Address (B), C4x: Register (Q) + Instr: 2/0 - RPTB, RPTBD +*/ + +/* J: General conditional branch operations + Syntax: c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc + Alias: +*/ +#define J_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name1, opcode|0x02000000, 0xffe00000, "P", level }, \ + { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name2, opcode|0x02000000, 0xffe00000, "P", level } + +/* JS: General conditional branch operations + Syntax: c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 1/1 - CALLc, C4X: LAJc +*/ + +/* LL: Load-load parallell operation + Syntax: src2, dst2 || src1, dst1 + src1 = Indirect 0,1,IR0,IR1 (J) + dst1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: Register (i) + dst2 = Register 0-7 (L) + Instr: 2/0 - LDF||LDF, LDI||LDI + Alias: i||i, i1||i2, i2||i1 +*/ +#define LL_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level } + +/* LS: Store-store parallell operation + Syntax: src2, dst2 || src1, dst1 + src1 = Register 0-7 (H) + dst1 = Indirect 0,1,IR0,IR1 (J) + src2 = Register 0-7 (L) + dst2 = Indirect 0,1,IR0,IR1, ENH: register (i) + Instr: 2/0 - STF||STF, STI||STI + Alias: i||i, i1||i2, i2||i1. +*/ +#define LS_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level } + +/* M: General multiply and add/sub operations + Syntax: src3,src4,dst1 || src2,src1,dst2 [00] - Manual + src3,src1,dst1 || src2,src4,dst2 [01] - Manual + src1,src3,dst1 || src2,src4,dst2 [01] + src1,src2,dst1 || src4,src3,dst2 [02] - Manual + src3,src1,dst1 || src4,src2,dst2 [03] - Manual + src1,src3,dst1 || src4,src2,dst2 [03] + src1 = Register 0-7 (K) + src2 = Register 0-7 (H) + src3 = Indirect 0,1,IR0,IR1, ENH: register (j) + src4 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-1 (N) + dst2 = Register 2-3 (M) + Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 + Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 +*/ +#define M_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level } + +/* P: General 2-operand operation with parallell store + Syntax: src2, dst1 || src3, dst2 + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, + LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, + TOIEEE||STF + Alias: a||b, b||a +*/ +#define P_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \ + { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level } + +/* Q: General 3-operand operation with parallell store + Syntax: src1, src2, dst1 || src3, dst2 + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define Q_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level } + +/* QC: General commutative 3-operand operation with parallell store + Syntax: src2, src1, dst1 || src3, dst2 + src1, src2, dst1 || src3, dst2 - Manual + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, + OR3||STI, XOR3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define QC_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level } + +/* R: General register integer operation + Syntax: dst + dst = Register (R) + Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC +*/ +#define R_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "R", level } + +/* RF: General register float operation + Syntax: dst + dst = Register 0-11 (r) + Instr: 2/0 - POPF, PUSHF +*/ +#define RF_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "r", level } + +/* S: General 3-operand float operation + Syntax: src2, src1, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 1/0 - SUBF3 + Alias: i, i3 +*/ +#define S_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* SC: General commutative 3-operand float operation + Syntax: src2, src1, dst - Manual + src1, src2, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 2/0 - ADDF3, MPYF3 + Alias: i, i3 +*/ +#define SC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* S2: General 3-operand float operation with 2 args + Syntax: src2, src1 + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPF3 + Alias: i, i3 +*/ +#define S2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T: General 3-operand integer operand + Syntax: src2, src1, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 + Alias: i, i3 +*/ +#define T_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* TC: General commutative 3-operand integer operation + Syntax: src2, src1, dst + src1, src2, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI + Alias: i, i3 +*/ +#define TC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* T2: General 3-operand integer operation with 2 args + Syntax: src2, src1 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPI3 + Alias: i, i3 +*/ +#define T2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T2C: General commutative 3-operand integer operation with 2 args + Syntax: src2, src1 - Manual + src1, src2 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) + Instr: 1/0 - TSTB3 + Alias: i, i3 +*/ +#define T2C_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* Z: Misc operations with or without arguments + Syntax: ,... + Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, + TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK +*/ + + +/* Define tic4x opcodes for assembler and disassembler. */ +static const tic4x_inst_t tic4x_insts[] = +{ + /* Put synonyms after the desired forms in table so that they get + overwritten in the lookup table. The disassembler will thus + print the `proper' mnemonics. Note that the disassembler + only decodes the 11 MSBs, so instructions like ldp @0x500 will + be printed as ldiu 5, dp. Note that with parallel instructions, + the second part is executed before the first part, unless + the sti1||sti2 form is used. We also allow sti2||sti1 + which is equivalent to the default sti||sti form. + */ + B_CLASS_INSN( "absf", 0x00000000, OP_C3X ), + P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ), + A_CLASS_INSN( "absi", 0x00800000, OP_C3X ), + P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ), + A_CLASS_INSN( "addc", 0x01000000, OP_C3X ), + TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ), + B_CLASS_INSN( "addf", 0x01800000, OP_C3X ), + SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ), + QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ), + A_CLASS_INSN( "addi", 0x02000000, OP_C3X ), + TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ), + QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ), + AU_CLASS_INSN( "and", 0x02800000, OP_C3X ), + TC_CLASS_INSN( "and", 0x01800000, OP_C3X ), + QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ), + AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ), + T_CLASS_INSN( "andn", 0x02000000, OP_C3X ), + A_CLASS_INSN( "ash", 0x03800000, OP_C3X ), + T_CLASS_INSN( "ash", 0x02800000, OP_C3X ), + Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ), + J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ), + J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ), + J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ), + J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ), + { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */ + { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */ + B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ), + S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ), + A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ), + T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ), + D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ), + D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ), + AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ), + P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ), + BI_CLASS_INSN( "float", 0x05800000, OP_C3X ), + P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ), + B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ), + P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ), + { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */ + { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */ + { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */ + { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */ + { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */ + { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */ + { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ), + A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ), + A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ), + A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ), + AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ), + AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ), + AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ), + AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ), + AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ), + B_CLASS_INSN( "lde", 0x06800000, OP_C3X ), + { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */ + B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ), + LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ), + P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ), + BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ), + B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ), + { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */ + { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ), + LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ), + P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ), + AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ), + A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ), + { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */ + B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ), + { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */ + { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ), + A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ), + AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ), + AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ), + { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ), + T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ), + Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ), + A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ), + A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ), + A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ), + A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ), + A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ), + A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ), + A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ), + A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ), + { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ), + A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ), + A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ), + A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ), + A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ), + A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ), + A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ), + A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ), + B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ), + SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ), + M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ), + QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ), + M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ), + A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ), + TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ), + QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ), + A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ), + TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ), + A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ), + TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ), + A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ), + B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ), + P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ), + A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ), + P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ), + A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ), + B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ), + AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ), + P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ), + AU_CLASS_INSN( "or", 0x10000000, OP_C3X ), + TC_CLASS_INSN( "or", 0x05800000, OP_C3X ), + QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ), + R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ), + RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ), + R_CLASS_INSN( "push", 0x0f200000, OP_C3X ), + RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ), + BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ), + { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */ + { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */ + { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */ + { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */ + B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ), + R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ), + R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ), + R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ), + R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ), + { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */ + { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ), + B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ), + { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ), + B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ), + LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ), + B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ), + A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ), + { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */ + { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */ + LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ), + A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ), + { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */ + { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "subb", 0x16800000, OP_C3X ), + T_CLASS_INSN( "subb", 0x06000000, OP_C3X ), + A_CLASS_INSN( "subc", 0x17000000, OP_C3X ), + B_CLASS_INSN( "subf", 0x17800000, OP_C3X ), + S_CLASS_INSN( "subf", 0x06800000, OP_C3X ), + Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ), + A_CLASS_INSN( "subi", 0x18000000, OP_C3X ), + T_CLASS_INSN( "subi", 0x07000000, OP_C3X ), + Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ), + A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ), + B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ), + A_CLASS_INSN( "subri", 0x19800000, OP_C3X ), + { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ), + P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ), + { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */ + { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */ + AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ), + T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ), + AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ), + TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), + QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), + + /* Dummy entry, not included in tic4x_num_insts. This + lets code examine entry i + 1 without checking + if we've run off the end of the table. */ + { "", 0x0, 0x00, "", 0 } +}; + +const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1); diff --git a/external/gpl3/gdb/dist/include/opcode/tic54x.h b/external/gpl3/gdb/dist/include/opcode/tic54x.h new file mode 100644 index 000000000000..f468714eefd9 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic54x.h @@ -0,0 +1,163 @@ +/* tic54x.h -- Header file for TI TMS320C54X opcode table + Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc. + Written by Timothy Wall (twall@cygnus.com) + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef _opcode_tic54x_h_ +#define _opcode_tic54x_h_ + +typedef struct _symbol +{ + const char *name; + unsigned short value; +} symbol; + +enum optype { + OPT = 0x8000, + OP_None = 0x0, + + OP_Xmem, /* AR3 or AR4, indirect */ + OP_Ymem, /* AR3 or AR4, indirect */ + OP_pmad, /* PROG mem, direct */ + OP_dmad, /* DATA mem, direct */ + OP_Smem, + OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ + OP_MMR, + OP_PA, + OP_Sind, + OP_xpmad, + OP_xpmad_ms7, + OP_MMRX, + OP_MMRY, + + OP_SRC1, /* src accumulator in bit 8 */ + OP_SRC, /* src accumulator in bit 9 */ + OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ + OP_DST, /* dst accumulator in bit 8 */ + OP_ARX, /* arX in bits 0-3 */ + OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ + OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ + OP_B, /* ACC B only */ + OP_A, /* ACC A only */ + + OP_lk, /* 16-bit immediate, '#' optional */ + OP_TS, + OP_k8, /* -128 <= k <= 128 */ + OP_16, /* literal "16" */ + OP_BITC, /* 0 to 16 */ + OP_CC, /* condition code */ + OP_CC2, /* 4-bit condition code */ + OP_CC3, /* 2-bit condition code */ + OP_123, /* 1, 2, or 3 */ + OP_031, /* 0-31, numeric */ + OP_k5, /* 0 to 31 */ + OP_k8u, /* 0 to 255 */ + OP_ASM, /* "ASM" */ + OP_T, /* "T" */ + OP_DP, /* "DP" */ + OP_ARP, /* "ARP" */ + OP_k3, /* 0-7 */ + OP_lku, /* 0 to 65535 */ + OP_N, /* 0/1 or ST0/ST1 */ + OP_SBIT, /* status bit or 0-15 */ + OP_12, /* one or two */ + OP_k9, /* 9 bits of data page (DP) address */ + OP_TRN, /* "TRN" */ + +}; + +typedef struct _template +{ + /* The opcode mnemonic */ + const char *name; + unsigned int words; /* insn size in words */ + int minops, maxops; /* min/max operand count */ + /* The significant bits in the opcode. Other bits are zero. + Instructions with more than 16 bits of opcode store the rest in the upper + 16 bits. + */ + unsigned short opcode; +#define INDIRECT(OP) ((OP)&0x80) +#define MOD(OP) (((OP)>>3)&0xF) +#define ARF(OP) ((OP)&0x7) +#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) +#define SRC(OP) ((OP)&0x200) +#define DST(OP) ((OP)&0x100) +#define SRC1(OP) ((OP)&0x100) +#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) +#define SHFT(OP) ((OP)&0xF) +#define ARX(OP) ((OP)&0x7) +#define XMEM(OP) (((OP)&0x00F0)>>4) +#define YMEM(OP) ((OP)&0x000F) +#define XMOD(C) (((C)&0xC)>>2) +#define XARX(C) (((C)&0x3)+2) +#define CC3(OP) (((OP)>>8)&0x3) +#define SBIT(OP) ((OP)&0xF) +#define MMR(OP) ((OP)&0x7F) +#define MMRX(OP) ((((OP)>>4)&0xF)+16) +#define MMRY(OP) (((OP)&0xF)+16) + +#define OPTYPE(X) ((X)&~OPT) + + /* Ones in this mask indicate which bits must match the opcode field. + Zeroes indicate don't care bits (operands and/or opcode options) */ + unsigned short mask; + + /* An array of operand codes (at most 4 operands) */ +#define MAX_OPERANDS 4 + enum optype operand_types[MAX_OPERANDS]; + + /* Special purpose flags (e.g. branch type, parallel, delay, etc) + */ + unsigned short flags; +#define B_NEXT 0 /* normal execution, next insn is next address */ +#define B_BRANCH 1 /* next insn is in opcode */ +#define B_RET 2 /* next insn is on stack */ +#define B_BACC 3 /* next insn is in acc */ +#define B_REPEAT 4 /* next insn repeats */ +#define FL_BMASK 0x07 + +#define FL_DELAY 0x10 /* instruction uses delay slots */ +#define FL_EXT 0x20 /* instruction takes two words */ +#define FL_FAR 0x40 /* far mode addressing */ +#define FL_LP 0x80 /* LP-only instruction */ +#define FL_NR 0x100 /* no repeat allowed */ +#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ + +#define FL_PAR 0x400 /* Parallel instruction. */ + + unsigned short opcode2, mask2; /* some insns have an extended opcode */ + + const char* parname; + enum optype paroperand_types[MAX_OPERANDS]; + +} insn_template; + +extern const insn_template tic54x_unknown_opcode; +extern const insn_template tic54x_optab[]; +extern const insn_template tic54x_paroptab[]; +extern const symbol mmregs[], regs[]; +extern const symbol condition_codes[], cc2_codes[], status_bits[]; +extern const symbol cc3_codes[]; +extern const char *misc_symbols[]; +struct disassemble_info; +extern const insn_template* tic54x_get_insn (struct disassemble_info *, + bfd_vma, unsigned short, int *); + +#endif /* _opcode_tic54x_h_ */ diff --git a/external/gpl3/gdb/dist/include/opcode/tic6x-control-registers.h b/external/gpl3/gdb/dist/include/opcode/tic6x-control-registers.h new file mode 100644 index 000000000000..b4387779aad7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic6x-control-registers.h @@ -0,0 +1,56 @@ +/* TI C6X control register information. + Copyright 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Define the CTRL macro before including this file; it takes as + arguments the fields from tic6x_ctrl (defined in tic6x.h). The + control register name is given as an identifier; the isa_variants + field without the leading TIC6X_INSN_; the rw field without the + leading tic6x_rw_. */ + +CTRL(amr, C62X, read_write, 0x0, 0x10) +CTRL(csr, C62X, read_write, 0x1, 0x10) +CTRL(dnum, C64XP, read, 0x11, 0x1f) +CTRL(ecr, C64XP, write, 0x1d, 0x1f) +CTRL(efr, C64XP, read, 0x1d, 0x1f) +CTRL(fadcr, C67X, read_write, 0x12, 0x1f) +CTRL(faucr, C67X, read_write, 0x13, 0x1f) +CTRL(fmcr, C67X, read_write, 0x14, 0x1f) +CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f) +CTRL(gplya, C64XP, read_write, 0x16, 0x1f) +CTRL(gplyb, C64XP, read_write, 0x17, 0x1f) +CTRL(icr, C62X, write, 0x3, 0x10) +CTRL(ier, C62X, read_write, 0x4, 0x10) +CTRL(ierr, C64XP, read_write, 0x1f, 0x1f) +CTRL(ifr, C62X, read, 0x2, 0x1d) +CTRL(ilc, C64XP, read_write, 0xd, 0x1f) +CTRL(irp, C62X, read_write, 0x6, 0x10) +CTRL(isr, C62X, write, 0x2, 0x10) +CTRL(istp, C62X, read_write, 0x5, 0x10) +CTRL(itsr, C64XP, read_write, 0x1b, 0x1f) +CTRL(nrp, C62X, read_write, 0x7, 0x10) +CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f) +CTRL(pce1, C62X, read, 0x10, 0xf) +CTRL(rep, C64XP, read_write, 0xf, 0x1f) +CTRL(rilc, C64XP, read_write, 0xe, 0x1f) +CTRL(ssr, C64XP, read_write, 0x15, 0x1f) +CTRL(tsch, C64XP, read, 0xb, 0x1f) +/* Contrary to Table 3-26 in SPRUFE8, this register is read-write, as + documented in section 2.9.13. */ +CTRL(tscl, C64XP, read_write, 0xa, 0x1f) +CTRL(tsr, C64XP, read_write, 0x1a, 0x1f) diff --git a/external/gpl3/gdb/dist/include/opcode/tic6x-insn-formats.h b/external/gpl3/gdb/dist/include/opcode/tic6x-insn-formats.h new file mode 100644 index 000000000000..8ce2418ec9b4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic6x-insn-formats.h @@ -0,0 +1,198 @@ +/* TI C6X instruction format information. + Copyright 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Define the FMT macro before including this file; it takes a name + and the fields from tic6x_insn_format (defined in tic6x.h). */ + +#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) } +#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1) +#define CFLDS2(a, b) 5, { CFLDS, a, b } +#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c } +#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d } +#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e } +#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f } +#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g } +#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h } +#define NFLDS FLD(p, 0, 1) +#define NFLDS1(a) 2, { NFLDS, a } +#define NFLDS2(a, b) 3, { NFLDS, a, b } +#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c } +#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e } +#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f } +#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g } + +/* These are in the order from SPRUFE8, appendices C-H. */ + +/* Appendix C 32-bit formats. */ + +FMT(d_1_or_2_src, 32, 0x40, 0x7c, + CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5), + FLD(dst, 23, 5))) +FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c, + CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +FMT(d_load_store, 32, 0x4, 0xc, + CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1), + FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5), + FLD(srcdst, 23, 5))) +/* The nonaligned loads and stores have the formats shown in the + individual instruction descriptions; the appendix is incorrect. */ +FMT(d_load_nonaligned, 32, 0x124, 0x17c, + CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5), + FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4))) +FMT(d_store_nonaligned, 32, 0x174, 0x17c, + CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5), + FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4))) +FMT(d_load_store_long, 32, 0xc, 0xc, + CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15), + FLD(dst, 23, 5))) +FMT(d_adda_long, 32, 0x1000000c, 0xf000000c, + NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15), + FLD(dst, 23, 5))) + +/* Appendix C 16-bit formats will go here. */ + +/* Appendix D 32-bit formats. */ + +FMT(l_1_or_2_src, 32, 0x18, 0x1c, + CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c, + NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +FMT(l_unary, 32, 0x358, 0xffc, + CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), + FLD(dst, 23, 5))) + +/* Appendix D 16-bit formats will go here. */ + +/* Appendix E 32-bit formats. */ + +FMT(m_compound, 32, 0x30, 0x83c, + CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c, + NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +/* Contrary to SPRUFE8, this does have predicate fields. */ +FMT(m_unary, 32, 0xf0, 0xffc, + CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), + FLD(dst, 23, 5))) + +/* M-unit formats missing from Appendix E. */ +FMT(m_mpy, 32, 0x0, 0x7c, + CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) + +/* Appendix E 16-bit formats will go here. */ + +/* Appendix F 32-bit formats. */ + +FMT(s_1_or_2_src, 32, 0x20, 0x3c, + CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23 ,5))) +FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c, + CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) +FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c, + NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1))) +FMT(s_unary, 32, 0xf20, 0xffc, + CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5), + FLD(dst, 23, 5))) +FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c, + CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21))) +FMT(s_call_imm_nop, 32, 0x10, 0xe000007c, + NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1))) +FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc, + CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12))) +FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc, + CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5))) +FMT(s_branch, 32, 0x360, 0xf83effc, + CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5))) +FMT(s_mvk, 32, 0x28, 0x3c, + CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5))) +FMT(s_field, 32, 0x8, 0x3c, + CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5), + FLD(src2, 18, 5), FLD(dst, 23, 5))) + +/* S-unit formats missing from Appendix F. */ +FMT(s_addk, 32, 0x50, 0x7c, + CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5))) +FMT(s_addkpc, 32, 0x160, 0x1ffc, + CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5))) +FMT(s_b_irp, 32, 0x1800e0, 0x7feffc, + CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5))) +FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc, + CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5))) +FMT(s_bdec, 32, 0x1020, 0x1ffc, + CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5))) +FMT(s_bpos, 32, 0x20, 0x1ffc, + CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5))) + +/* Appendix F 16-bit formats will go here. */ + +/* Appendix G 16-bit formats will go here. */ + +/* Appendix H 32-bit formats. */ + +FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc, + CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5))) +/* Corrected relative to Appendix H. */ +FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc, + NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4))) + +/* No-unit formats missing from Appendix H (given the NOP and IDLE + correction). */ +FMT(nfu_dint, 32, 0x10004000, 0xfffffffc, + NFLDS1(FLD(s, 1, 1))) +FMT(nfu_rint, 32, 0x10006000, 0xfffffffc, + NFLDS1(FLD(s, 1, 1))) +FMT(nfu_swe, 32, 0x10000000, 0xfffffffc, + NFLDS1(FLD(s, 1, 1))) +FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc, + NFLDS1(FLD(s, 1, 1))) +/* Although formally covered by the loop buffer format, the fields in + that format are not useful for all such instructions and not all + instructions can be predicated. */ +FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc, + NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6))) +FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc, + NFLDS1(FLD(s, 1, 1))) +FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc, + NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8))) + +/* Appendix H 16-bit formats will go here. */ + +#undef FLD +#undef CFLDS +#undef CFLDS2 +#undef CFLDS3 +#undef CFLDS4 +#undef CFLDS5 +#undef CFLDS6 +#undef CFLDS7 +#undef CFLDS8 +#undef NFLDS +#undef NFLDS1 +#undef NFLDS2 +#undef NFLDS3 +#undef NFLDS5 +#undef NFLDS6 +#undef NFLDS7 diff --git a/external/gpl3/gdb/dist/include/opcode/tic6x-opcode-table.h b/external/gpl3/gdb/dist/include/opcode/tic6x-opcode-table.h new file mode 100644 index 000000000000..bd22558cef23 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic6x-opcode-table.h @@ -0,0 +1,2549 @@ +/* TI C6X opcode table. + Copyright 2010, 2011 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Define the INSN macro before including this file; it takes as + arguments the fields from tic6x_opcode (defined in tic6x.h). The + name is given as an identifier; the subsequent four operands should + have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_" + and "TIC6X_INSN_", respectively, prepended to them by the macro + definition. Also define INSNE, which has a second argument that + goes after tic6x_opcode_NAME_ to form the enumeration value for + this instruction, where the value otherwise formed from the name, + functional unit and format is ambiguous, but otherwise has the same + arguments as INSN. */ + +#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X +#define tic6x_insn_format_nfu_s_branch_nop_cst \ + tic6x_insn_format_s_branch_nop_cst +#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src +#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) } +#define FIX(id, val) RAN(id, val, val) +#define FIX0() 0, { { 0, 0, 0 } } +#define FIX1(a) 1, { a } +#define FIX2(a, b) 2, { a, b } +#define FIX3(a, b, c) 3, { a, b, c } +#define FIX4(a, b, c, d) 4, { a, b, c, d } +#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } } +#define OP1(a) 1, { a } +#define OP2(a, b) 2, { a, b } +#define OP3(a, b, c) 3, { a, b, c } +#define OP4(a, b, c, d) 4, { a, b, c, d } +#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 } +#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 } +#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 } +#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 } +#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 } +#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 } +#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 } +#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 } +#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 } +#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 } +#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 } +#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 } +#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 } +#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 } +#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 } +#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 } +#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 } +#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 } +#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 } +#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } +#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } +#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } +#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 } +#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } +#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } +#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } +#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 } +#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 } +#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 } +#define ENC(id, meth, op) { \ + CONCAT2(tic6x_field_,id), \ + CONCAT2(tic6x_coding_,meth), \ + op \ + } +#define ENC0() 0, { { 0, 0, 0 } } +#define ENC1(a) 1, { a } +#define ENC2(a, b) 2, { a, b } +#define ENC3(a, b, c) 3, { a, b, c } +#define ENC4(a, b, c, d) 4, { a, b, c, d } +#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e } +#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f } +#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g } + +INSN(abs, l, unary, 1cycle, C62X, 0, + FIX1(FIX(op, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGL1, OWREGL1), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(abs2, l, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x4)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREGD12), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(abssp, s, unary, 1cycle, C67X, 0, + FIX1(FIX(op, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x23)), + OP3(ORREG1, ORXREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x21)), + OP3(ORXREG1, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x2)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x20), FIX(x, 0)), + OP3(OACST, ORREGL1, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x7)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x6)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x10)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x12)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0xa)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0xb)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, scst, 1), ENC(dst, reg, 2))) + +INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x30)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x32)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 3)), + OP3(ORAREG1, OLCST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1), + ENC(dst, reg, 2))) + +INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3c)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X, + TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3d)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x34)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x36)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 5)), + OP3(ORAREG1, OLCST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1), + ENC(dst, reg, 2))) + +INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x38)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x3a)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 7)), + OP3(ORAREG1, OLCST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1), + ENC(dst, reg, 2))) + +INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0, + FIX1(FIX(op, 0x18)), + OP3(ORREGD12, ORXREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0, + FIX1(FIX(op, 0x72)), + OP3(ORREGD12, ORXREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) + +INSN(addkpc, s, addkpc, 1cycle, C64X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY, + FIX1(FIX(s, 1)), + OP3(OLCST, OWREG1, OACST), + ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2))) + +INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0, + FIX1(FIX(op, 0x10)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0, + FIX1(FIX(op, 0x70)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0xc)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0xd)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x2b)), + OP3(ORREG1, ORXREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x29)), + OP3(ORXREG1, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x5)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x4)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x65)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x7b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x7a)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x1f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x1e)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x6)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x7)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x7c)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x6)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(avg2, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x13)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(avgu4, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x12)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP1(OLCST), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY, + FIX1(FIX(s, 1)), + OP1(ORXREG1), + ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) +INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORIRP1), + ENC0()) +INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORNRP1), + ENC0()) + +INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OLCST, ORWREG1), + ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1))) + +INSN(bitc4, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1e)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(bitr, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1f)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(bnop, s, branch_nop_cst, branch, C64X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX0(), + OP2(OLCST, OACST), + ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) +INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP, + FIX1(FIX(s, 0)), + OP2(OLCST, OACST), + ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) +INSN(bnop, s, branch_nop_reg, branch, C64X, + TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP, + FIX1(FIX(s, 1)), + OP2(ORXREG1, OACST), + ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) + +INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS, + FIX0(), + OP2(OLCST, ORREG1), + ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1))) + +INSN(call, s, ext_branch_cond_imm, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, + FIX0(), + OP1(OLCST), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +INSN(call, s, branch, branch, C62X, + TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, + FIX1(FIX(s, 1)), + OP1(ORXREG1), + ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) +INSN(call, s, b_irp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORIRP1), + ENC0()) +INSN(call, s, b_nrp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORNRP1), + ENC0()) + +INSN(callnop, s, branch_nop_cst, branch, C64X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, + FIX0(), + OP2(OLCST, OACST), + ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) +INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, + FIX1(FIX(s, 0)), + OP2(OLCST, OACST), + ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1))) +INSN(callnop, s, branch_nop_reg, branch, C64X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL, + FIX1(FIX(s, 1)), + OP2(ORXREG1, OACST), + ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1))) + +INSN(callp, s, call_imm_nop, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP, + FIX1(FIX(z, 1)), + OP2(OLCST, OWRETREG1), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) + +INSN(callret, s, ext_branch_cond_imm, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, + FIX0(), + OP1(OLCST), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +INSN(callret, s, branch, branch, C62X, + TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, + FIX1(FIX(s, 1)), + OP1(ORXREG1), + ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) +INSN(callret, s, b_irp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORIRP1), + ENC0()) +INSN(callret, s, b_nrp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORNRP1), + ENC0()) + +INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), + ENC(cstb, ucst, 2), ENC(dst, reg, 3))) +INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x3f)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x53)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x52)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x51)), + OP3(ORXREG1, ORREGL1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x50), FIX(x, 0)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1d)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1c)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0, + FIX1(FIX(op, 0x28)), + OP3(ORREGD12, ORXREGD12, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0, + FIX1(FIX(op, 0x38)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x47)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x46)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x45)), + OP3(ORXREG1, ORREGL1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x44), FIX(x, 0)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x57)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x56)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x55)), + OP3(ORREGL1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x54), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), + ENC(dst, reg, 2))) + +INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x14)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0, + FIX1(FIX(op, 0x29)), + OP3(ORREGD12, ORXREGD12, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0, + FIX1(FIX(op, 0x39)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x4f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a + 5-bit unsigned constant operand on C64X and above. */ +INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0, + FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x4d)), + OP3(ORXREG1, ORREGL1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x15)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x57)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x56)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x55)), + OP3(ORXREG1, ORREGL1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x54), FIX(x, 0)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x47)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x46)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x45)), + OP3(ORREGL1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x44), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0), + ENC(dst, reg, 2))) + +INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x14)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0, + FIX1(FIX(op, 0x2a)), + OP3(ORREGD12, ORXREGD12, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0, + FIX1(FIX(op, 0x3a)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x5f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0, + FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x5d)), + OP3(ORXREG1, ORREGL1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) +INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)), + OP3(OACST, ORREGL1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x15)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0xa)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0xb)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0xc)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(cmtl, d, 1_or_2_src, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, + FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)), + OP2(ORMEMDW, OWDREG5), + ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x18)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x17)), + OP3(ORREGD1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x15)), + OP3(ORREGD1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x16)), + OP3(ORREGD1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x14)), + OP3(ORREGD1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(deal, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1d)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(dint, nfu, dint, 1cycle, C64XP, 0, + FIX1(FIX(s, 0)), + OP0(), + ENC0()) + +INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0, + FIX1(FIX(op, 0xb)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0xc)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0xb)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpn2, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x9)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x7)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x7)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(dotprsu2, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0xd)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0xd)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpsu4, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x2)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(dotpu4, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x6)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x34)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x33)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREG4), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREG4), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREG4), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x1)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), + ENC(cstb, ucst, 2), ENC(dst, reg, 3))) +INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x2f)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x0)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), + ENC(cstb, ucst, 2), ENC(dst, reg, 3))) +INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x2b)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x1f), FIX(x, 0)), + OP3(ORREG1, ORREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +/* This instruction can be predicated as usual; SPRUFE8 is incorrect + where it shows the "z" field as fixed to 1. */ +INSN(gmpy4, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x11)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP, + FIX2(FIX(s, 0), FIX(op, 0xf)), + OP0(), + ENC0()) + +INSN(intdp, l, 1_or_2_src, intdp, C67X, 0, + FIX2(FIX(op, 0x39), FIX(src1, 0)), + OP2(ORXREG1, OWREGD45), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0, + FIX2(FIX(op, 0x3b), FIX(src1, 0)), + OP2(ORXREG1, OWREGD45), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0, + FIX2(FIX(op, 0x4a), FIX(src1, 0)), + OP2(ORXREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0, + FIX2(FIX(op, 0x49), FIX(src1, 0)), + OP2(ORXREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(ldb, d, load_store, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 2), FIX(r, 0)), + OP2(ORMEMSB, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) +INSN(ldb, d, load_store_long, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 2)), + OP2(ORMEMLB, OWDREG5), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), + ENC(dst, reg, 1))) + +INSN(ldbu, d, load_store, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 1), FIX(r, 0)), + OP2(ORMEMSB, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) +INSN(ldbu, d, load_store_long, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 1)), + OP2(ORMEMLB, OWDREG5), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0), + ENC(dst, reg, 1))) + +INSN(lddw, d, load_store, load, C64X_AND_C67X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 6), FIX(r, 1)), + OP2(ORMEMSD, OWDREGD5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) + +INSN(ldh, d, load_store, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 4), FIX(r, 0)), + OP2(ORMEMSH, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) +INSN(ldh, d, load_store_long, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 4)), + OP2(ORMEMLH, OWDREG5), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), + ENC(dst, reg, 1))) + +INSN(ldhu, d, load_store, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 0), FIX(r, 0)), + OP2(ORMEMSH, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) +INSN(ldhu, d, load_store_long, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0)), + OP2(ORMEMLH, OWDREG5), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0), + ENC(dst, reg, 1))) + +INSN(ldndw, d, load_nonaligned, load, C64X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, + FIX0(), + OP2(ORMEMND, OWDREGD5), + ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0), + ENC(sc, scaled, 0), ENC(dst, reg_shift, 1))) + +INSN(ldnw, d, load_store, load, C64X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, + FIX2(FIX(op, 3), FIX(r, 1)), + OP2(ORMEMSW, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) + +INSN(ldw, d, load_store, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 6), FIX(r, 0)), + OP2(ORMEMSW, OWDREG5), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0), + ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0), + ENC(srcdst, reg, 1))) +INSN(ldw, d, load_store_long, load, C62X, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 6)), + OP2(ORMEMLW, OWDREG5), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0), + ENC(dst, reg, 1))) + +INSN(ll, d, 1_or_2_src, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, + FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)), + OP2(ORMEMDW, OWDREG5), + ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x6b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x6a)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x42)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0, + FIX1(FIX(op, 0xd)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x43)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x41)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0, + FIX1(FIX(op, 0xc)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x48)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x19)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x18)), + OP3(OACST, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x0e), FIX(x, 0)), + OP3(ORREGD1234, ORREGD1324, OWREGD910), + ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), + ENC(dst, reg, 2))) + +INSN(mpyh, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x01)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhi, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x14)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhir, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x10)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhl, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x09)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhlu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x0f)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhslu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x0b)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhsu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x03)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x07)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhuls, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x0d)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyhus, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x05)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0, + FIX1(FIX(op, 0x04)), + OP3(ORREG14, ORXREG14, OWREG9), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0, + FIX1(FIX(op, 0x06)), + OP3(OACST, ORXREG14, OWREG9), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0, + FIX1(FIX(op, 0x08)), + OP3(ORREG14, ORXREG14, OWREGD910), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0, + FIX1(FIX(op, 0x0c)), + OP3(OACST, ORXREG14, OWREGD910), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x14)), + OP3(ORXREG1, ORREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x10)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x15)), + OP3(ORXREG1, ORREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x0e)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(mpylh, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x11)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpylhu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x17)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyli, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x15)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpylir, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x0e)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpylshu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x13)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyluhs, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x15)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpysp, m, mpy, 4cycle, C67X, 0, + FIX1(FIX(op, 0x1c)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and + C67X+. */ +INSN(mpyspdp, m, compound, mpyspdp, C67X, 0, + FIX1(FIX(op, 0x16)), + OP3(ORREG12, ORXREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0, + FIX1(FIX(op, 0x17)), + OP3(ORREG1, ORXREG1, OWREGD45), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x1b)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x1e)), + OP3(OACST, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpysu4, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x05)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyu, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x1f)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyu4, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x04)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyus, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x1d)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x05)), + OP3(ORXREG1, ORREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(mpy2, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x00)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x0f)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x10)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x14)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpy32su, m, mpy, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x16)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpy32u, m, compound, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x18)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(mpy32us, m, compound, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x19)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +/* "or" forms of "mv" are preferred over "add" forms when available + because "or" uses less power. However, 40-bit moves are only + available through "add", and before C64X D-unit moves are only + available through "add" (without cross paths being available). */ +INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x7e), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGL1, OWREGL1), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) +INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x1a), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0), + FIX2(FIX(op, 0x12), FIX(src1, 0)), + OP2(ORREG1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) +INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 0x3), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS, + FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)), + OP2(ORCREG1, OWREG1), + ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1))) +INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY, + FIX2(FIX(s, 1), FIX(op, 0x0e)), + OP2(ORXREG1, OWCREG1), + ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1), + ENC(dst, crlo, 1))) + +INSN(mvd, m, unary, 4cycle, C64X, 0, + FIX1(FIX(op, 0x1a)), + OP2(ORXREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(h, 0)), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1))) +INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(x, 0), FIX(op, 0x05)), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1))) +INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x00), FIX(src2, 0)), + OP2(OACST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1))) + +INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(h, 1)), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1))) + +INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX1(FIX(h, 1)), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1))) + +INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX1(FIX(h, 0)), + OP2(OLCST, OWREG1), + ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1))) + +INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x16), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x06), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x24), FIX(src1, 0)), + OP2(ORREGL1, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(nop, nfu, nop_idle, nop, C62X, 0, + FIX2(FIX(s, 0), RAN(op, 0, 8)), + OP1(OACST), + ENC1(ENC(op, ucst_minus_one, 0))) +INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(s, 0), FIX(op, 0)), + OP0(), + ENC0()) + +INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX2(FIX(op, 0x63), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGL1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0xf), FIX(src1, 0x1f)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x3)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x7f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x7e)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x1b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x1a)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0xf)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1e)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x9)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x69)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1c)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x8)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x10)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x68)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREGD12), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0, + FIX2(FIX(op, 0x3d), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(ret, s, ext_branch_cond_imm, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, + FIX0(), + OP1(OLCST), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) +INSN(ret, s, branch, branch, C62X, + TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, + FIX1(FIX(s, 1)), + OP1(ORXREG1), + ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0))) +INSN(ret, s, b_irp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORIRP1), + ENC0()) +INSN(ret, s, b_nrp, branch, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, + FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)), + OP1(ORNRP1), + ENC0()) + +INSN(retp, s, call_imm_nop, branch, C64XP, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN, + FIX1(FIX(z, 1)), + OP2(OLCST, OWRETREG1), + ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0))) + +INSN(rint, nfu, rint, 1cycle, C64XP, 0, + FIX1(FIX(s, 0)), + OP0(), + ENC0()) + +INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1d)), + OP3(ORXREG1, ORREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1e)), + OP3(ORXREG1, OACST, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) + +INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX2(FIX(op, 0xb), FIX(z, 1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGD1, OWREGD12), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0, + FIX2(FIX(op, 0x3e), FIX(src1, 0)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x13)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x31)), + OP3(ORXREG1, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x12)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x30)), + OP3(OACST, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x20)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x0)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0e)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x0f)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x1)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x3)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)), + OP2(ORREGL1, OWREG1), + ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1))) + +INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2)), + OP4(ORREG1, OACST, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1), + ENC(cstb, ucst, 2), ENC(dst, reg, 3))) +INSN(set, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x3b)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSN(shfl, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1c)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x36)), + OP3(ORREG1, ORXREG1, OWREGD1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x33)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x31), FIX(x, 0)), + OP3(ORREGL1, ORREG1, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x13)), + OP3(ORXREG1, ORREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x32)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) +INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x30), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x12)), + OP3(ORXREG1, OACST, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) + +INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x61)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x9)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x37)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x35), FIX(x, 0)), + OP3(ORREGL1, ORREG1, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x36)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) +INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x34), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x7)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x18)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) + +INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x62)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0xa)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x27)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x25), FIX(x, 0)), + OP3(ORREGL1, ORREG1, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x26)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) +INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x24), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x8)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x19)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) + +INSN(sl, d, 1_or_2_src, store, C64XP, + TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS, + FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)), + OP2(ORDREG1, OWMEMDW), + ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1))) + +INSN(smpy, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x1a)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(smpyh, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x02)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(smpyhl, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x0a)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(smpylh, m, mpy, 1616_m, C62X, 0, + FIX1(FIX(op, 0x12)), + OP3(ORREG1, ORXREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(smpy2, m, compound, 4cycle, C64X, 0, + FIX1(FIX(op, 0x01)), + OP3(ORREG1, ORXREG1, OWREGD4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +/* Contrary to SPRUFE8, this is the correct operand order for this + instruction. */ +INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x19)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x2)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x4)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0, + FIX2(FIX(op, 0x02), FIX(src1, 0)), + OP2(ORXREG1, OWREGD12), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0, + FIX2(FIX(op, 0x0a), FIX(src1, 0)), + OP2(ORXREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, + FIX1(FIX(s, 0)), + OP2(OACST, OACST), + ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1))) +INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO, + FIX2(FIX(s, 0), FIX(fstgfcyc, 0)), + OP0(), + ENC0()) + +INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL, + FIX1(FIX(s, 0)), + OP0(), + ENC0()) + +INSN(sploop, nfu, loop_buffer, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, + FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)), + OP1(OACST), + ENC1(ENC(cstb, ucst_minus_one, 0))) + +INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, + FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)), + OP1(OACST), + ENC1(ENC(cstb, ucst_minus_one, 0))) + +INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP, + TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP, + FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)), + OP1(OACST), + ENC1(ENC(cstb, ucst_minus_one, 0))) + +/* Contrary to SPRUFE8, this is the correct encoding for this + instruction. */ +INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, + FIX2(FIX(s, 0), FIX(op, 0x8)), + OP1(OFULIST), + ENC1(ENC(mask, spmask, 0))) + +INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK, + FIX2(FIX(s, 0), FIX(op, 0x9)), + OP1(OFULIST), + ENC1(ENC(mask, spmask, 0))) + +INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0, + FIX2(FIX(op, 0x0b), FIX(src1, 0)), + OP2(ORXREG1, OWREG4), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x23)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x22)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, ucst, 1), ENC(dst, reg, 2))) + +INSN(sshvl, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1c)), + OP3(ORXREG1, ORREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +/* Contrary to SPRUFE8, this is the correct encoding for this + instruction. */ +INSN(sshvr, m, compound, 1616_m, C64X, 0, + FIX1(FIX(op, 0x1a)), + OP3(ORXREG1, ORREG1, OWREG2), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x0f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x1f)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x0e)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x2c)), + OP3(OACST, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0, + FIX1(FIX(op, 0x64)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(stb, d, load_store, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 3), FIX(r, 0)), + OP2(ORDREG1, OWMEMSB), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), + ENC(srcdst, reg, 0))) +INSN(stb, d, load_store_long, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 3)), + OP2(ORDREG1, OWMEMLB), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1), + ENC(dst, reg, 0))) + +INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 4), FIX(r, 1)), + OP2(ORDREGD1, OWMEMSD), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), + ENC(srcdst, reg, 0))) + +INSN(sth, d, load_store, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 5), FIX(r, 0)), + OP2(ORDREG1, OWMEMSH), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), + ENC(srcdst, reg, 0))) +INSN(sth, d, load_store_long, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 5)), + OP2(ORDREG1, OWMEMLH), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1), + ENC(dst, reg, 0))) + +INSN(stndw, d, store_nonaligned, store, C64X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, + FIX0(), + OP2(ORDREGD1, OWMEMND), + ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1), + ENC(sc, scaled, 1), ENC(src, reg_shift, 0))) + +INSN(stnw, d, load_store, store, C64X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED, + FIX2(FIX(op, 5), FIX(r, 1)), + OP2(ORDREG1, OWMEMSW), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), + ENC(srcdst, reg, 0))) + +INSN(stw, d, load_store, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX2(FIX(op, 7), FIX(r, 0)), + OP2(ORDREG1, OWMEMSW), + ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1), + ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1), + ENC(srcdst, reg, 0))) +INSN(stw, d, load_store_long, store, C62X, + TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 7)), + OP2(ORDREG1, OWMEMLW), + ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1), + ENC(dst, reg, 0))) + +INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x07)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x17)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x27)), + OP3(ORREG1, ORXREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x37)), + OP3(ORXREG1, ORREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x06)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x24)), + OP3(OACST, ORREGL1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x2)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x20), FIX(x, 0)), + OP3(ORREGL1, OACST, OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0), + ENC(dst, reg, 2))) +INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x17)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x16)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +/* Contrary to SPRUFE8, this is the correct encoding for this + instruction; this instruction can be predicated. */ +INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x5)), + OP3(ORXREG1, ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) +INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO, + FIX1(FIX(op, 0x6)), + OP3(ORXREG1, OACST, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1), + ENC(src2, reg, 0), ENC(dst, reg, 2))) +INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x11)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x13)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) +INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0xc)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x31)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x33)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x5a)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x35)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x37)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x39)), + OP3(ORREG1, ORREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1), + ENC(dst, reg, 2))) +INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS, + FIX1(FIX(op, 0x3b)), + OP3(ORREG1, OACST, OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1), + ENC(dst, reg, 2))) + +INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x4b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x19)), + OP3(ORREGD12, ORXREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x1d)), + OP3(ORXREGD12, ORREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP, + TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x73)), + OP3(ORREGD12, ORXREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP, + TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x77)), + OP3(ORXREGD12, ORREGD12, OWREGD67), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x11)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x15)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP, + TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x71)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP, + TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x75)), + OP3(ORXREG1, ORREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(src1, reg, 1), ENC(dst, reg, 2))) + +INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1), + FIX1(FIX(op, 0x2f)), + OP3(ORREG1, ORXREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x3f)), + OP3(ORXREG1, ORREG1, OWREGL1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x04)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x11)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x5)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0x66)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x1b), FIX(x, 0)), + OP2(ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 0), ENC(dst, reg, 1))) +INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS, + FIX2(FIX(op, 0x10), FIX(x, 0)), + OP2(ORREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 0), ENC(dst, reg, 1))) + +/* Contrary to SPRUFE8, this is the correct encoding for this + instruction. */ +INSN(swap4, l, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x1)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(swe, nfu, swe, 1cycle, C64XP, 0, + FIX1(FIX(s, 0)), + OP0(), + ENC0()) + +INSN(swenr, nfu, swenr, 1cycle, C64XP, 0, + FIX1(FIX(s, 0)), + OP0(), + ENC0()) + +INSN(unpkhu4, l, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x03)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSN(unpkhu4, s, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x03)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(unpklu4, l, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x02)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) +INSN(unpklu4, s, unary, 1cycle, C64X, 0, + FIX1(FIX(op, 0x02)), + OP2(ORXREG1, OWREG1), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x6f)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x6e)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x0b)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0, + FIX1(FIX(op, 0x0a)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0xe)), + OP3(ORREG1, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) +INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0, + FIX1(FIX(op, 0xf)), + OP3(OACST, ORXREG1, OWREG1), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0, + FIX1(FIX(op, 0x1b)), + OP3(ORREG1, ORXREG1, OWREG4), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) + +INSN(xpnd2, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x19)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(xpnd4, m, unary, 1616_m, C64X, 0, + FIX1(FIX(op, 0x18)), + OP2(ORXREG1, OWREG2), + ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0), + ENC(dst, reg, 1))) + +INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX2(FIX(h, 0), FIX(cst, 0)), + OP1(OWREG1), + ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) +INSN(zero, l, unary, 1cycle, C64X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), + FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)), + OP1(OWREG1), + ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) +INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), + FIX2(FIX(op, 0x07), FIX(x, 0)), + OP1(OWREG1), + ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0), + ENC(dst, reg, 0))) +INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO, + FIX2(FIX(op, 0x27), FIX(x, 0)), + OP1(OWREGL1), + ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0), + ENC(dst, reg, 0))) +INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1), + FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)), + OP1(OWREG1), + ENC2(ENC(s, fu, 0), ENC(dst, reg, 0))) +INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, + TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0), + FIX1(FIX(op, 0x11)), + OP1(OWREG1), + ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0), + ENC(dst, reg, 0))) + +#undef TIC6X_INSN_C64X_AND_C67X +#undef tic6x_insn_format_nfu_s_branch_nop_cst +#undef tic6x_insn_format_s_l_1_or_2_src +#undef RAN +#undef FIX +#undef FIX0 +#undef FIX1 +#undef FIX2 +#undef FIX3 +#undef FIX4 +#undef OP0 +#undef OP1 +#undef OP2 +#undef OP3 +#undef OP4 +#undef OACST +#undef OLCST +#undef OFULIST +#undef ORIRP1 +#undef ORNRP1 +#undef OWREG1 +#undef OWRETREG1 +#undef ORREG1 +#undef ORDREG1 +#undef ORWREG1 +#undef ORAREG1 +#undef ORXREG1 +#undef ORREG12 +#undef ORREG14 +#undef ORXREG14 +#undef OWREG2 +#undef OWREG4 +#undef OWREG9 +#undef OWDREG5 +#undef OWREGL1 +#undef ORREGL1 +#undef OWREGD1 +#undef OWREGD12 +#undef OWREGD4 +#undef ORREGD1 +#undef OWREGD45 +#undef OWREGD67 +#undef ORDREGD1 +#undef OWDREGD5 +#undef ORREGD12 +#undef ORXREGD12 +#undef ORREGD1234 +#undef ORREGD1324 +#undef OWREGD910 +#undef ORCREG1 +#undef OWCREG1 +#undef ORMEMDW +#undef OWMEMDW +#undef ORMEMSB +#undef OWMEMSB +#undef ORMEMLB +#undef OWMEMLB +#undef ORMEMSH +#undef OWMEMSH +#undef ORMEMLH +#undef OWMEMLH +#undef ORMEMSW +#undef OWMEMSW +#undef ORMEMLW +#undef OWMEMLW +#undef ORMEMSD +#undef OWMEMSD +#undef ORMEMND +#undef OWMEMND +#undef ENC +#undef ENC0 +#undef ENC1 +#undef ENC2 +#undef ENC3 +#undef ENC4 +#undef ENC5 +#undef ENC6 +#undef ENC7 diff --git a/external/gpl3/gdb/dist/include/opcode/tic6x.h b/external/gpl3/gdb/dist/include/opcode/tic6x.h new file mode 100644 index 000000000000..2a7a2463d545 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic6x.h @@ -0,0 +1,613 @@ +/* TI C6X opcode information. + Copyright 2010, 2011 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef OPCODE_TIC6X_H +#define OPCODE_TIC6X_H + +#include "bfd.h" +#include "symcat.h" + +/* A field in an instruction format. The names are based on those + used in the architecture manuals. */ +typedef enum + { + tic6x_field_baseR, + tic6x_field_creg, + tic6x_field_cst, + tic6x_field_csta, + tic6x_field_cstb, + tic6x_field_dst, + tic6x_field_fstgfcyc, + tic6x_field_h, + tic6x_field_mask, + tic6x_field_mode, + tic6x_field_offsetR, + tic6x_field_op, + tic6x_field_p, + tic6x_field_r, + tic6x_field_s, + tic6x_field_sc, + tic6x_field_src, + tic6x_field_src1, + tic6x_field_src2, + tic6x_field_srcdst, + tic6x_field_x, + tic6x_field_y, + tic6x_field_z + } tic6x_insn_field_id; + +typedef struct +{ + /* The name used to reference the field. */ + tic6x_insn_field_id field_id; + + /* The least-significant bit position in the field. */ + unsigned short low_pos; + + /* The number of bits in the field. */ + unsigned short width; +} tic6x_insn_field; + +/* Maximum number of variable fields in an instruction format. */ +#define TIC6X_MAX_INSN_FIELDS 11 + +/* A particular instruction format. */ +typedef struct +{ + /* How many bits in the instruction. */ + unsigned int num_bits; + + /* Constant bits in the instruction. */ + unsigned int cst_bits; + + /* Mask matching those bits. */ + unsigned int mask; + + /* The number of instruction fields. */ + unsigned int num_fields; + + /* Descriptions of instruction fields. */ + tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS]; +} tic6x_insn_format; + +/* An index into the table of instruction formats. */ +typedef enum + { +#define FMT(name, num_bits, cst_bits, mask, fields) \ + CONCAT2(tic6x_insn_format_, name), +#include "tic6x-insn-formats.h" +#undef FMT + tic6x_insn_format_max + } tic6x_insn_format_id; + +/* The table itself. */ +extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max]; + +/* If instruction format FMT has a field FIELD, return a pointer to + the description of that field; otherwise return NULL. */ + +const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt, + tic6x_insn_field_id field); + +/* Description of a field (in an instruction format) whose value is + fixed, or constrained to be in a particular range, in a particular + opcode. */ +typedef struct +{ + /* The name of the field. */ + tic6x_insn_field_id field_id; + + /* The least value of the field in this instruction. */ + unsigned int min_val; + + /* The greatest value of the field in this instruction. */ + unsigned int max_val; +} tic6x_fixed_field; + +/* Bit-masks for defining instructions present on some subset of + processors; each indicates an instruction present on that processor + and those that are supersets of it. The options passed to the + assembler determine a bit-mask ANDed with the bit-mask indicating + when the instruction was added to determine whether the instruction + is enabled. */ +#define TIC6X_INSN_C62X 0x0001 +#define TIC6X_INSN_C64X 0x0002 +#define TIC6X_INSN_C64XP 0x0004 +#define TIC6X_INSN_C67X 0x0008 +#define TIC6X_INSN_C67XP 0x0010 +#define TIC6X_INSN_C674X 0x0020 + +/* Flags with further information about an opcode table entry. */ + +/* Only used by the assembler, not the disassembler. */ +#define TIC6X_FLAG_MACRO 0x0001 + +/* Must be first in its execute packet. */ +#define TIC6X_FLAG_FIRST 0x0002 + +/* Multi-cycle NOP (not used for the NOP n instruction itself, which + is only a multicycle NOP if n > 1). */ +#define TIC6X_FLAG_MCNOP 0x0004 + +/* Cannot be in parallel with a multi-cycle NOP. */ +#define TIC6X_FLAG_NO_MCNOP 0x0008 + +/* Load instruction. */ +#define TIC6X_FLAG_LOAD 0x0010 + +/* Store instruction. */ +#define TIC6X_FLAG_STORE 0x0020 + +/* Unaligned memory operation. */ +#define TIC6X_FLAG_UNALIGNED 0x0040 + +/* Only on side B. */ +#define TIC6X_FLAG_SIDE_B_ONLY 0x0080 + +/* Only on data path T2. */ +#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100 + +/* Does not support cross paths. */ +#define TIC6X_FLAG_NO_CROSS 0x0200 + +/* Annotate this branch instruction as a call. */ +#define TIC6X_FLAG_CALL 0x0400 + +/* Annotate this branch instruction as a return. */ +#define TIC6X_FLAG_RETURN 0x0800 + +/* This instruction starts a software pipelined loop. */ +#define TIC6X_FLAG_SPLOOP 0x1000 + +/* This instruction ends a software pipelined loop. */ +#define TIC6X_FLAG_SPKERNEL 0x2000 + +/* This instruction takes a list of functional units as parameters; + although described as having one parameter, the number may be 0 to + 8. */ +#define TIC6X_FLAG_SPMASK 0x4000 + +/* When more than one opcode matches the assembly source, prefer the + one with the highest value for this bit-field. If two opcode table + entries can match the same syntactic form, they must have different + values here. */ +#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15) +#define TIC6X_FLAG_PREFER(n) ((n) << 15) +#define TIC6X_NUM_PREFER 2 + +/* Maximum number of fixed fields for a particular opcode. */ +#define TIC6X_MAX_FIXED_FIELDS 4 + +/* Maximum number of operands in the opcode table for a particular + opcode. */ +#define TIC6X_MAX_OPERANDS 4 + +/* Maximum number of operands in the source code for a particular + opcode (different from the number in the opcode table for SPMASK + and SPMASKR). */ +#define TIC6X_MAX_SOURCE_OPERANDS 8 + +/* Maximum number of variable fields for a particular opcode. */ +#define TIC6X_MAX_VAR_FIELDS 7 + +/* Which functional units an opcode uses. This only describes the + basic choice of D, L, M, S or no functional unit; other fields are + used to describe further restrictions (instructions only operating + on one side), use of cross paths and load/store instructions using + one side for the address and the other side for the source or + destination register. */ +typedef enum + { + tic6x_func_unit_d, + tic6x_func_unit_l, + tic6x_func_unit_m, + tic6x_func_unit_s, + tic6x_func_unit_nfu + } tic6x_func_unit_base; + +/* Possible forms of source operand. */ +typedef enum + { + /* An assembly-time constant. */ + tic6x_operand_asm_const, + /* A link-time constant. */ + tic6x_operand_link_const, + /* A register, from the same side as the functional unit + selected. */ + tic6x_operand_reg, + /* A register, that is from the other side if a cross path is + used. */ + tic6x_operand_xreg, + /* A register, that is from the side of the data path + selected. */ + tic6x_operand_dreg, + /* An address register usable with 15-bit offsets (B14 or B15). + This is from the same side as the functional unit if a cross + path is not used, and the other side if a cross path is + used. */ + tic6x_operand_areg, + /* A return address register (A3 or B3), from the same side as the + functional unit selected. */ + tic6x_operand_retreg, + /* A register pair, from the same side as the functional unit + selected. */ + tic6x_operand_regpair, + /* A register pair, that is from the other side if a cross path is + used. */ + tic6x_operand_xregpair, + /* A register pair, from the side of the data path selected. */ + tic6x_operand_dregpair, + /* The literal string "irp" (case-insensitive). */ + tic6x_operand_irp, + /* The literal string "nrp" (case-insensitive). */ + tic6x_operand_nrp, + /* A control register. */ + tic6x_operand_ctrl, + /* A memory reference (base and offset registers from the side of + the functional unit selected), using either unsigned 5-bit + constant or register offset, if any offset; register offsets + cannot use unscaled () syntax. */ + tic6x_operand_mem_short, + /* A memory reference (base and offset registers from the side of + the functional unit selected), using either unsigned 5-bit + constant or register offset, if any offset; register offsets + can use unscaled () syntax (for LDNDW and STNDW). */ + tic6x_operand_mem_ndw, + /* A memory reference using 15-bit link-time constant offset + relative to B14 or B15. */ + tic6x_operand_mem_long, + /* A memory reference that only dereferences a register with no + further adjustments (*REG), that register being from the side + of the functional unit selected. */ + tic6x_operand_mem_deref, + /* A functional unit name or a list thereof (for SPMASK and + SPMASKR). */ + tic6x_operand_func_unit + } tic6x_operand_form; + +/* Whether something is, or can be, read or written. */ +typedef enum + { + tic6x_rw_none, + tic6x_rw_read, + tic6x_rw_write, + tic6x_rw_read_write + } tic6x_rw; + +/* Description of a source operand and how it is used. */ +typedef struct +{ + /* The syntactic form of the operand. */ + tic6x_operand_form form; + + /* For non-constant operands, the size in bytes (1, 2, 4, 5 or + 8). Ignored for constant operands. */ + unsigned int size; + + /* Whether the operand is read, written or both. In addition to the + operations described here, address registers are read on cycle 1 + regardless of when the memory operand is read or written, and may + be modified as described by the addressing mode, and control + registers may be implicitly read by some instructions. There are + also some special cases not fully described by this + structure. + + - For mpydp, the low part of src2 is read on cycles 1 and 3 but + not 2, and the high part on cycles 2 and 4 but not 3. + + - The swap2 pseudo-operation maps to packlh2, reading the first + operand of swap2 twice. */ + tic6x_rw rw; + + /* The first and last cycles (1 for E1, etc.) at which the operand, + or the low part for two-register operands, is read or + written. */ + unsigned short low_first; + unsigned short low_last; + + /* Likewise, for the high part. */ + unsigned short high_first; + unsigned short high_last; +} tic6x_operand_info; + +/* Ways of converting an operand or functional unit specifier to a + field value. */ +typedef enum + { + /* Store an unsigned assembly-time constant (which must fit) in + the field. */ + tic6x_coding_ucst, + /* Store a signed constant (which must fit) in the field. This + may be used both for assembly-time constants and for link-time + constants. */ + tic6x_coding_scst, + /* Subtract one from an unsigned assembly-time constant (which + must be strictly positive before the subtraction) and store the + value (which must fit) in the field. */ + tic6x_coding_ucst_minus_one, + /* Negate a signed assembly-time constant, and store the result of + negation (which must fit) in the field. Used only for + pseudo-operations. */ + tic6x_coding_scst_negate, + /* Store an unsigned link-time constant, implicitly DP-relative + and counting in bytes, in the field. For expression operands, + assembly-time constants are encoded as-is. For memory + reference operands, the offset is encoded as-is if [] syntax is + used and shifted if () is used. */ + tic6x_coding_ulcst_dpr_byte, + /* Store an unsigned link-time constant, implicitly DP-relative + and counting in half-words, in the field. For expression + operands, assembly-time constants are encoded as-is. For + memory reference operands, the offset is encoded as-is if [] + syntax is used and shifted if () is used. */ + tic6x_coding_ulcst_dpr_half, + /* Store an unsigned link-time constant, implicitly DP-relative + and counting in words, in the field. For expression operands, + assembly-time constants are encoded as-is. For memory + reference operands, the offset is encoded as-is if [] syntax is + used and shifted if () is used. */ + tic6x_coding_ulcst_dpr_word, + /* Store the low 16 bits of a link-time constant in the field; + considered unsigned for disassembly. */ + tic6x_coding_lcst_low16, + /* Store the high 16 bits of a link-time constant in the field; + considered unsigned for disassembly. */ + tic6x_coding_lcst_high16, + /* Store a signed PC-relative value (address of label minus + address of fetch packet containing the current instruction, + counted in words) in the field. */ + tic6x_coding_pcrel, + /* Likewise, but counting in half-words if in a header-based fetch + packet. */ + tic6x_coding_pcrel_half, + /* Encode the register number (even number for a register pair) in + the field. When applied to a memory reference, encode the base + register. */ + tic6x_coding_reg, + /* Store 0 for register B14, 1 for register B15. When applied to + a memory reference, encode the base register. */ + tic6x_coding_areg, + /* Store the low part of a control register address. */ + tic6x_coding_crlo, + /* Store the high part of a control register address. */ + tic6x_coding_crhi, + /* Encode the even register number for a register pair, shifted + right by one bit. */ + tic6x_coding_reg_shift, + /* Store either the offset register or the 5-bit unsigned offset + for a memory reference. If an offset uses the unscaled () + form, which is only permitted with constants, it is scaled + according to the access size of the operand before being + stored. */ + tic6x_coding_mem_offset, + /* Store either the offset register or the 5-bit unsigned offset + for a memory reference, but with no scaling applied to the + offset (for nonaligned doubleword operations). */ + tic6x_coding_mem_offset_noscale, + /* Store the addressing mode for a memory reference. */ + tic6x_coding_mem_mode, + /* Store whether a memory reference is scaled. */ + tic6x_coding_scaled, + /* Store the stage in an SPKERNEL instruction in the upper part of + the field. */ + tic6x_coding_fstg, + /* Store the cycle in an SPKERNEL instruction in the lower part of + the field. */ + tic6x_coding_fcyc, + /* Store the mask bits for functional units in the field in an + SPMASK or SPMASKR instruction. */ + tic6x_coding_spmask, + /* Store the number of a register that is unused, or minimally + used, in this execute packet. The number must be the same for + all uses of this coding in a single instruction, but may be + different for different instructions in the execute packet. + This is for the "zero" pseudo-operation. This is not safe when + reads may occur from instructions in previous execute packets; + in such cases the programmer or compiler should use explicit + "sub" instructions for those cases of "zero" that cannot be + implemented as "mvk" for the processor specified. */ + tic6x_coding_reg_unused, + /* Store 1 if the functional unit used is on side B, 0 for side + A. */ + tic6x_coding_fu, + /* Store 1 if the data path used (source register for store, + destination for load) is on side B, 0 for side A. */ + tic6x_coding_data_fu, + /* Store 1 if the cross path is being used, 0 otherwise. */ + tic6x_coding_xpath + } tic6x_coding_method; + +/* How to generate the value of a particular field. */ +typedef struct +{ + /* The name of the field. */ + tic6x_insn_field_id field_id; + + /* How it is encoded. */ + tic6x_coding_method coding_method; + + /* Source operand number, if any. */ + unsigned int operand_num; +} tic6x_coding_field; + +/* Types of instruction for pipeline purposes. The type determines + functional unit and cross path latency (when the same functional + unit can be used by other instructions, when the same cross path + can be used by other instructions). */ +typedef enum + { + tic6x_pipeline_nop, + tic6x_pipeline_1cycle, + tic6x_pipeline_1616_m, + tic6x_pipeline_store, + tic6x_pipeline_mul_ext, + tic6x_pipeline_load, + tic6x_pipeline_branch, + tic6x_pipeline_2cycle_dp, + tic6x_pipeline_4cycle, + tic6x_pipeline_intdp, + tic6x_pipeline_dpcmp, + tic6x_pipeline_addsubdp, + tic6x_pipeline_mpyi, + tic6x_pipeline_mpyid, + tic6x_pipeline_mpydp, + tic6x_pipeline_mpyspdp, + tic6x_pipeline_mpysp2dp + } tic6x_pipeline_type; + +/* Description of a control register. */ +typedef struct +{ + /* The name of the register. */ + const char *name; + + /* Which ISA variants include this control register. */ + unsigned short isa_variants; + + /* Whether it can be read, written or both (in supervisor mode). + Some registers use the same address, but different names, for + reading and writing. */ + tic6x_rw rw; + + /* crlo value for this register. */ + unsigned int crlo; + + /* Mask that, ANDed with the crhi value in the instruction, must be + 0. 0 is always generated when generating code. */ + unsigned int crhi_mask; +} tic6x_ctrl; + +/* An index into the table of control registers. */ +typedef enum + { +#define CTRL(name, isa, rw, crlo, crhi_mask) \ + CONCAT2(tic6x_ctrl_,name), +#include "tic6x-control-registers.h" +#undef CTRL + tic6x_ctrl_max + } tic6x_ctrl_id; + +/* The table itself. */ +extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max]; + +/* An entry in the opcode table. */ +typedef struct +{ + /* The name of the instruction. */ + const char *name; + + /* Functional unit used by this instruction (basic information). */ + tic6x_func_unit_base func_unit; + + /* The format of this instruction. */ + tic6x_insn_format_id format; + + /* The pipeline type of this instruction. */ + tic6x_pipeline_type type; + + /* Which ISA variants include this instruction. */ + unsigned short isa_variants; + + /* Flags for this instruction. */ + unsigned short flags; + + /* Number of fixed fields, or fields with restricted value ranges, + for this instruction. */ + unsigned int num_fixed_fields; + + /* Values of fields fixed for this instruction. */ + tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS]; + + /* The number of operands in the source form of this + instruction. */ + unsigned int num_operands; + + /* Information about individual operands. */ + tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS]; + + /* The number of variable fields for this instruction with encoding + instructions explicitly given. */ + unsigned int num_variable_fields; + + /* How fields (other than ones with fixed value) are computed from + the source operands and functional unit specifiers. In addition + to fields specified here: + + - creg, if present, is set from the predicate, along with z which + must be present if creg is present. + + - p, if present (on all non-compact instructions), is set from + the parallel bars. + */ + tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS]; +} tic6x_opcode; + +/* An index into the table of opcodes. */ +typedef enum + { +#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \ + CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), +#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ + CONCAT4(tic6x_opcode_,name,_,e), +#include "tic6x-opcode-table.h" +#undef INSN +#undef INSNE + tic6x_opcode_max + } tic6x_opcode_id; + +/* The table itself. */ +extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max]; + +/* A linked list of opcodes. */ +typedef struct tic6x_opcode_list_tag +{ + tic6x_opcode_id id; + struct tic6x_opcode_list_tag *next; +} tic6x_opcode_list; + +/* The information from a fetch packet header. */ +typedef struct +{ + /* The header itself. */ + unsigned int header; + + /* Whether each word uses compact instructions. */ + bfd_boolean word_compact[7]; + + /* Whether loads are protected. */ + bfd_boolean prot; + + /* Whether instructions use the high register set. */ + bfd_boolean rs; + + /* Data size. */ + unsigned int dsz; + + /* Whether compact instructions in the S unit are decoded as + branches. */ + bfd_boolean br; + + /* Whether compact instructions saturate. */ + bfd_boolean sat; + + /* P-bits. */ + bfd_boolean p_bits[14]; +} tic6x_fetch_packet_header; + +#endif /* OPCODE_TIC6X_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/tic80.h b/external/gpl3/gdb/dist/include/opcode/tic80.h new file mode 100644 index 000000000000..43c84be574f5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/tic80.h @@ -0,0 +1,283 @@ +/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table + Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc. + Written by Fred Fish (fnf@cygnus.com), Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef TIC80_H +#define TIC80_H + +/* The opcode table is an array of struct tic80_opcode. */ + +struct tic80_opcode +{ + /* The opcode name. */ + + const char *name; + + /* The opcode itself. Those bits which will be filled in with operands + are zeroes. */ + + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a mask + containing ones indicating those bits which must match the opcode + field, and zeroes indicating those bits which need not match (and are + presumably filled in by operands). */ + + unsigned long mask; + + /* Special purpose flags for this opcode. */ + + unsigned char flags; + + /* An array of operand codes. Each code is an index into the operand + table. They appear in the order which the operands must appear in + assembly code, and are terminated by a zero. FIXME: Adjust size to + match actual requirements when TIc80 support is complete */ + + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise in + the order in which the disassembler should consider instructions. + FIXME: This isn't currently true. */ + +extern const struct tic80_opcode tic80_opcodes[]; +extern const int tic80_num_opcodes; + + +/* The operands table is an array of struct tic80_operand. */ + +struct tic80_operand +{ + /* The number of bits in the operand. */ + + int bits; + + /* How far the operand is left shifted in the instruction. */ + + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + + unsigned long (*insert) + (unsigned long instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & TIC80_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + + long (*extract) (unsigned long instruction, int *invalid); + + /* One bit syntax flags. */ + + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the tic80_opcodes table. */ + +extern const struct tic80_operand tic80_operands[]; + + +/* Values defined for the flags field of a struct tic80_operand. + + Note that flags for all predefined symbols, such as the general purpose + registers (ex: r10), control registers (ex: FPST), condition codes (ex: + eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be + or'd into an int where the lower bits contain the actual numeric value + that correponds to this predefined symbol. This way a single int can + contain both the value of the symbol and it's type. + */ + +/* This operand must be an even register number. Floating point numbers + for example are stored in even/odd register pairs. */ + +#define TIC80_OPERAND_EVEN (1 << 0) + +/* This operand must be an odd register number and must be one greater than + the register number of the previous operand. I.E. the second register in + an even/odd register pair. */ + +#define TIC80_OPERAND_ODD (1 << 1) + +/* This operand takes signed values. */ + +#define TIC80_OPERAND_SIGNED (1 << 2) + +/* This operand may be either a predefined constant name or a numeric value. + An example would be a condition code like "eq0.b" which has the numeric + value 0x2. */ + +#define TIC80_OPERAND_NUM (1 << 3) + +/* This operand should be wrapped in parentheses rather than separated + from the previous one by a comma. This is used for various + instructions, like the load and store instructions, which want + their operands to look like "displacement(reg)" */ + +#define TIC80_OPERAND_PARENS (1 << 4) + +/* This operand is a PC relative branch offset. The disassembler prints + these symbolically if possible. Note that the offsets are taken as word + offsets. */ + +#define TIC80_OPERAND_PCREL (1 << 5) + +/* This flag is a hint to the disassembler for using hex as the prefered + printing format, even for small positive or negative immediate values. + Normally values in the range -999 to 999 are printed as signed decimal + values and other values are printed in hex. */ + +#define TIC80_OPERAND_BITFIELD (1 << 6) + +/* This operand may have a ":m" modifier specified by bit 17 in a short + immediate form instruction. */ + +#define TIC80_OPERAND_M_SI (1 << 7) + +/* This operand may have a ":m" modifier specified by bit 15 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_M_LI (1 << 8) + +/* This operand may have a ":s" modifier specified in bit 11 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_SCALED (1 << 9) + +/* This operand is a floating point value */ + +#define TIC80_OPERAND_FLOAT (1 << 10) + +/* This operand is an byte offset from a base relocation. The lower + two bits of the final relocated address are ignored when the value is + written to the program counter. */ + +#define TIC80_OPERAND_BASEREL (1 << 11) + +/* This operand is an "endmask" field for a shift instruction. + It is treated special in that it can have values of 0-32, + where 0 and 32 result in the same instruction. The assembler + must be able to accept both endmask values. This disassembler + has no way of knowing from the instruction which value was + given at assembly time, so it just uses '0'. */ + +#define TIC80_OPERAND_ENDMASK (1 << 12) + +/* This operand is one of the 32 general purpose registers. + The disassembler prints these with a leading 'r'. */ + +#define TIC80_OPERAND_GPR (1 << 27) + +/* This operand is a floating point accumulator register. + The disassembler prints these with a leading 'a'. */ + +#define TIC80_OPERAND_FPA ( 1 << 28) + +/* This operand is a control register number, either numeric or + symbolic (like "EIF", "EPC", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CR (1 << 29) + +/* This operand is a condition code, either numeric or + symbolic (like "eq0.b", "ne0.w", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CC (1 << 30) + +/* This operand is a bit number, either numeric or + symbolic (like "eq.b", "or.f", etc). + The disassembler prints these symbolically. + Note that they appear in the instruction in 1's complement relative + to the values given in the manual. */ + +#define TIC80_OPERAND_BITNUM (1 << 31) + +/* This mask is used to strip operand bits from an int that contains + both operand bits and a numeric value in the lsbs. */ + +#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) + + +/* Flag bits for the struct tic80_opcode flags field. */ + +#define TIC80_VECTOR 01 /* Is a vector instruction */ +#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ + + +/* The opcodes library contains a table that allows translation from predefined + symbol names to numeric values, and vice versa. */ + +/* Structure to hold information about predefined symbols. */ + +struct predefined_symbol +{ + char *name; /* name to recognize */ + int value; +}; + +#define PDS_NAME(pdsp) ((pdsp) -> name) +#define PDS_VALUE(pdsp) ((pdsp) -> value) + +/* Translation array. */ +extern const struct predefined_symbol tic80_predefined_symbols[]; +/* How many members in the array. */ +extern const int tic80_num_predefined_symbols; + +/* Translate value to symbolic name. */ +const char *tic80_value_to_symbol (int val, int class); + +/* Translate symbolic name to value. */ +int tic80_symbol_to_value (char *name, int class); + +const struct predefined_symbol *tic80_next_predefined_symbol + (const struct predefined_symbol *); + +#endif /* TIC80_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/v850.h b/external/gpl3/gdb/dist/include/opcode/v850.h new file mode 100644 index 000000000000..59033059179d --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/v850.h @@ -0,0 +1,207 @@ +/* v850.h -- Header file for NEC V850 opcode table + Copyright 1996, 1997, 2001, 2003, 2010 Free Software Foundation, Inc. + Written by J.T. Conklin, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef V850_H +#define V850_H + +/* The opcode table is an array of struct v850_opcode. */ + +struct v850_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; + + /* Target processor(s). A bit field of processors which support + this instruction. Note a bit field is used as some instructions + are available on multiple, different processor types, whereas + other instructions are only available on one specific type. */ + unsigned int processors; +}; + +/* Values for the processors field in the v850_opcode structure. */ +#define PROCESSOR_MASK 0x1f +#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */ +#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */ +#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ +#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */ +#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ +#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */ +#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */ +#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */ +#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */ +#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */ +#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set)) + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct v850_opcode v850_opcodes[]; +extern const int v850_num_opcodes; + + +/* The operands table is an array of struct v850_operand. */ + +struct v850_operand +{ + /* The number of bits in the operand. */ + /* If this value is -1 then the operand's bits are in a discontinous + distribution in the instruction. */ + int bits; + + /* (bits >= 0): How far the operand is left shifted in the instruction. */ + /* (bits == -1): Bit mask of the bits in the operand. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (* insert) + (unsigned long instruction, long op, const char ** errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); + if (o->flags & V850_OPERAND_SIGNED) + op = (op << (32 - o->bits)) >> (32 - o->bits); + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + unsigned long (* extract) (unsigned long instruction, int * invalid); + + /* One bit syntax flags. */ + int flags; + + int default_reloc; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the v850_opcodes table. */ + +extern const struct v850_operand v850_operands[]; + +/* Values defined for the flags field of a struct v850_operand. */ + +/* This operand names a general purpose register. */ +#define V850_OPERAND_REG 0x01 + +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x02 + +/* This operand names a system register. */ +#define V850_OPERAND_SRG 0x04 + +/* Prologue eilogue type instruction, V850E specific. */ +#define V850E_OPERAND_REG_LIST 0x08 + +/* This operand names a condition code used in the setf instruction. */ +#define V850_OPERAND_CC 0x10 + +#define V850_OPERAND_FLOAT_CC 0x20 + +/* This operand names a vector purpose register. */ +#define V850_OPERAND_VREG 0x40 + +/* 16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16 0x80 + +/* hi16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16HI 0x100 + +/* 23 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE23 0x200 + +/* 32 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE32 0x400 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?). */ +#define V850_OPERAND_RELAX 0x800 + +/* This operand takes signed values. */ +#define V850_OPERAND_SIGNED 0x1000 + +/* This operand is a displacement. */ +#define V850_OPERAND_DISP 0x2000 + +/* This operand is a PC displacement. */ +#define V850_PCREL 0x4000 + +/* The register specified must be even number. */ +#define V850_REG_EVEN 0x8000 + +/* The register specified must not be r0. */ +#define V850_NOT_R0 0x20000 + +/* The register specified must not be 0. */ +#define V850_NOT_IMM0 0x40000 + +/* The condition code must not be SA CONDITION. */ +#define V850_NOT_SA 0x80000 + +/* The operand has '!' prefix. */ +#define V850_OPERAND_BANG 0x100000 + +/* The operand has '%' prefix. */ +#define V850_OPERAND_PERCENT 0x200000 + +extern int v850_msg_is_out_of_range (const char * msg); + +#endif /* V850_H */ diff --git a/external/gpl3/gdb/dist/include/opcode/vax.h b/external/gpl3/gdb/dist/include/opcode/vax.h new file mode 100644 index 000000000000..f5cdd24397f5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/opcode/vax.h @@ -0,0 +1,383 @@ +/* Vax opcde list. + Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GDB and GAS are distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifndef vax_opcodeT +#define vax_opcodeT int +#endif /* no vax_opcodeT */ + +struct vot_wot /* vax opcode table: wot to do with this */ + /* particular opcode */ +{ + const char *args; /* how to compile said opcode */ + vax_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* vax opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static const struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "nop", {"", 0x01 } }, +{ "rei", {"", 0x02 } }, +{ "bpt", {"", 0x03 } }, +{ "ret", {"", 0x04 } }, +{ "rsb", {"", 0x05 } }, +{ "ldpctx", {"", 0x06 } }, +{ "svpctx", {"", 0x07 } }, +{ "cvtps", {"rwabrwab", 0x08 } }, +{ "cvtsp", {"rwabrwab", 0x09 } }, +{ "index", {"rlrlrlrlrlwl", 0x0a } }, +{ "crc", {"abrlrwab", 0x0b } }, +{ "prober", {"rbrwab", 0x0c } }, +{ "probew", {"rbrwab", 0x0d } }, +{ "insque", {"abab", 0x0e } }, +{ "remque", {"abwl", 0x0f } }, +{ "bsbb", {"bb", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "bneq", {"bb", 0x12 } }, +{ "bnequ", {"bb", 0x12 } }, +{ "beql", {"bb", 0x13 } }, +{ "beqlu", {"bb", 0x13 } }, +{ "bgtr", {"bb", 0x14 } }, +{ "bleq", {"bb", 0x15 } }, +{ "jsb", {"ab", 0x16 } }, +{ "jmp", {"ab", 0x17 } }, +{ "bgeq", {"bb", 0x18 } }, +{ "blss", {"bb", 0x19 } }, +{ "bgtru", {"bb", 0x1a } }, +{ "blequ", {"bb", 0x1b } }, +{ "bvc", {"bb", 0x1c } }, +{ "bvs", {"bb", 0x1d } }, +{ "bcc", {"bb", 0x1e } }, +{ "bgequ", {"bb", 0x1e } }, +{ "blssu", {"bb", 0x1f } }, +{ "bcs", {"bb", 0x1f } }, +{ "addp4", {"rwabrwab", 0x20 } }, +{ "addp6", {"rwabrwabrwab", 0x21 } }, +{ "subp4", {"rwabrwab", 0x22 } }, +{ "subp6", {"rwabrwabrwab", 0x23 } }, +{ "cvtpt", {"rwababrwab", 0x24 } }, +{ "mulp", {"rwabrwabrwab", 0x25 } }, +{ "cvttp", {"rwababrwab", 0x26 } }, +{ "divp", {"rwabrwabrwab", 0x27 } }, +{ "movc3", {"rwabab", 0x28 } }, +{ "cmpc3", {"rwabab", 0x29 } }, +{ "scanc", {"rwababrb", 0x2a } }, +{ "spanc", {"rwababrb", 0x2b } }, +{ "movc5", {"rwabrbrwab", 0x2c } }, +{ "cmpc5", {"rwabrbrwab", 0x2d } }, +{ "movtc", {"rwabrbabrwab", 0x2e } }, +{ "movtuc", {"rwabrbabrwab", 0x2f } }, +{ "bsbw", {"bw", 0x30 } }, +{ "brw", {"bw", 0x31 } }, +{ "cvtwl", {"rwwl", 0x32 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "movp", {"rwabab", 0x34 } }, +{ "cmpp3", {"rwabab", 0x35 } }, +{ "cvtpl", {"rwabwl", 0x36 } }, +{ "cmpp4", {"rwabrwab", 0x37 } }, +{ "editpc", {"rwababab", 0x38 } }, +{ "matchc", {"rwabrwab", 0x39 } }, +{ "locc", {"rbrwab", 0x3a } }, +{ "skpc", {"rbrwab", 0x3b } }, +{ "movzwl", {"rwwl", 0x3c } }, +{ "acbw", {"rwrwmwbw", 0x3d } }, +{ "movaw", {"awwl", 0x3e } }, +{ "pushaw", {"aw", 0x3f } }, +{ "addf2", {"rfmf", 0x40 } }, +{ "addf3", {"rfrfwf", 0x41 } }, +{ "subf2", {"rfmf", 0x42 } }, +{ "subf3", {"rfrfwf", 0x43 } }, +{ "mulf2", {"rfmf", 0x44 } }, +{ "mulf3", {"rfrfwf", 0x45 } }, +{ "divf2", {"rfmf", 0x46 } }, +{ "divf3", {"rfrfwf", 0x47 } }, +{ "cvtfb", {"rfwb", 0x48 } }, +{ "cvtfw", {"rfww", 0x49 } }, +{ "cvtfl", {"rfwl", 0x4a } }, +{ "cvtrfl", {"rfwl", 0x4b } }, +{ "cvtbf", {"rbwf", 0x4c } }, +{ "cvtwf", {"rwwf", 0x4d } }, +{ "cvtlf", {"rlwf", 0x4e } }, +{ "acbf", {"rfrfmfbw", 0x4f } }, +{ "movf", {"rfwf", 0x50 } }, +{ "cmpf", {"rfrf", 0x51 } }, +{ "mnegf", {"rfwf", 0x52 } }, +{ "tstf", {"rf", 0x53 } }, +{ "emodf", {"rfrbrfwlwf", 0x54 } }, +{ "polyf", {"rfrwab", 0x55 } }, +{ "cvtfd", {"rfwd", 0x56 } }, + /* opcode 57 is not defined yet */ +{ "adawi", {"rwmw", 0x58 } }, + /* opcode 59 is not defined yet */ + /* opcode 5a is not defined yet */ + /* opcode 5b is not defined yet */ +{ "insqhi", {"abaq", 0x5c } }, +{ "insqti", {"abaq", 0x5d } }, +{ "remqhi", {"aqwl", 0x5e } }, +{ "remqti", {"aqwl", 0x5f } }, +{ "addd2", {"rdmd", 0x60 } }, +{ "addd3", {"rdrdwd", 0x61 } }, +{ "subd2", {"rdmd", 0x62 } }, +{ "subd3", {"rdrdwd", 0x63 } }, +{ "muld2", {"rdmd", 0x64 } }, +{ "muld3", {"rdrdwd", 0x65 } }, +{ "divd2", {"rdmd", 0x66 } }, +{ "divd3", {"rdrdwd", 0x67 } }, +{ "cvtdb", {"rdwb", 0x68 } }, +{ "cvtdw", {"rdww", 0x69 } }, +{ "cvtdl", {"rdwl", 0x6a } }, +{ "cvtrdl", {"rdwl", 0x6b } }, +{ "cvtbd", {"rbwd", 0x6c } }, +{ "cvtwd", {"rwwd", 0x6d } }, +{ "cvtld", {"rlwd", 0x6e } }, +{ "acbd", {"rdrdmdbw", 0x6f } }, +{ "movd", {"rdwd", 0x70 } }, +{ "cmpd", {"rdrd", 0x71 } }, +{ "mnegd", {"rdwd", 0x72 } }, +{ "tstd", {"rd", 0x73 } }, +{ "emodd", {"rdrbrdwlwd", 0x74 } }, +{ "polyd", {"rdrwab", 0x75 } }, +{ "cvtdf", {"rdwf", 0x76 } }, + /* opcode 77 is not defined yet */ +{ "ashl", {"rbrlwl", 0x78 } }, +{ "ashq", {"rbrqwq", 0x79 } }, +{ "emul", {"rlrlrlwq", 0x7a } }, +{ "ediv", {"rlrqwlwl", 0x7b } }, +{ "clrd", {"wd", 0x7c } }, +{ "clrg", {"wg", 0x7c } }, +{ "clrq", {"wd", 0x7c } }, +{ "movq", {"rqwq", 0x7d } }, +{ "movaq", {"aqwl", 0x7e } }, +{ "movad", {"adwl", 0x7e } }, +{ "pushaq", {"aq", 0x7f } }, +{ "pushad", {"ad", 0x7f } }, +{ "addb2", {"rbmb", 0x80 } }, +{ "addb3", {"rbrbwb", 0x81 } }, +{ "subb2", {"rbmb", 0x82 } }, +{ "subb3", {"rbrbwb", 0x83 } }, +{ "mulb2", {"rbmb", 0x84 } }, +{ "mulb3", {"rbrbwb", 0x85 } }, +{ "divb2", {"rbmb", 0x86 } }, +{ "divb3", {"rbrbwb", 0x87 } }, +{ "bisb2", {"rbmb", 0x88 } }, +{ "bisb3", {"rbrbwb", 0x89 } }, +{ "bicb2", {"rbmb", 0x8a } }, +{ "bicb3", {"rbrbwb", 0x8b } }, +{ "xorb2", {"rbmb", 0x8c } }, +{ "xorb3", {"rbrbwb", 0x8d } }, +{ "mnegb", {"rbwb", 0x8e } }, +{ "caseb", {"rbrbrb", 0x8f } }, +{ "movb", {"rbwb", 0x90 } }, +{ "cmpb", {"rbrb", 0x91 } }, +{ "mcomb", {"rbwb", 0x92 } }, +{ "bitb", {"rbrb", 0x93 } }, +{ "clrb", {"wb", 0x94 } }, +{ "tstb", {"rb", 0x95 } }, +{ "incb", {"mb", 0x96 } }, +{ "decb", {"mb", 0x97 } }, +{ "cvtbl", {"rbwl", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "movzbl", {"rbwl", 0x9a } }, +{ "movzbw", {"rbww", 0x9b } }, +{ "rotl", {"rbrlwl", 0x9c } }, +{ "acbb", {"rbrbmbbw", 0x9d } }, +{ "movab", {"abwl", 0x9e } }, +{ "pushab", {"ab", 0x9f } }, +{ "addw2", {"rwmw", 0xa0 } }, +{ "addw3", {"rwrwww", 0xa1 } }, +{ "subw2", {"rwmw", 0xa2 } }, +{ "subw3", {"rwrwww", 0xa3 } }, +{ "mulw2", {"rwmw", 0xa4 } }, +{ "mulw3", {"rwrwww", 0xa5 } }, +{ "divw2", {"rwmw", 0xa6 } }, +{ "divw3", {"rwrwww", 0xa7 } }, +{ "bisw2", {"rwmw", 0xa8 } }, +{ "bisw3", {"rwrwww", 0xa9 } }, +{ "bicw2", {"rwmw", 0xaa } }, +{ "bicw3", {"rwrwww", 0xab } }, +{ "xorw2", {"rwmw", 0xac } }, +{ "xorw3", {"rwrwww", 0xad } }, +{ "mnegw", {"rwww", 0xae } }, +{ "casew", {"rwrwrw", 0xaf } }, +{ "movw", {"rwww", 0xb0 } }, +{ "cmpw", {"rwrw", 0xb1 } }, +{ "mcomw", {"rwww", 0xb2 } }, +{ "bitw", {"rwrw", 0xb3 } }, +{ "clrw", {"ww", 0xb4 } }, +{ "tstw", {"rw", 0xb5 } }, +{ "incw", {"mw", 0xb6 } }, +{ "decw", {"mw", 0xb7 } }, +{ "bispsw", {"rw", 0xb8 } }, +{ "bicpsw", {"rw", 0xb9 } }, +{ "popr", {"rw", 0xba } }, +{ "pushr", {"rw", 0xbb } }, +{ "chmk", {"rw", 0xbc } }, +{ "chme", {"rw", 0xbd } }, +{ "chms", {"rw", 0xbe } }, +{ "chmu", {"rw", 0xbf } }, +{ "addl2", {"rlml", 0xc0 } }, +{ "addl3", {"rlrlwl", 0xc1 } }, +{ "subl2", {"rlml", 0xc2 } }, +{ "subl3", {"rlrlwl", 0xc3 } }, +{ "mull2", {"rlml", 0xc4 } }, +{ "mull3", {"rlrlwl", 0xc5 } }, +{ "divl2", {"rlml", 0xc6 } }, +{ "divl3", {"rlrlwl", 0xc7 } }, +{ "bisl2", {"rlml", 0xc8 } }, +{ "bisl3", {"rlrlwl", 0xc9 } }, +{ "bicl2", {"rlml", 0xca } }, +{ "bicl3", {"rlrlwl", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "xorl3", {"rlrlwl", 0xcd } }, +{ "mnegl", {"rlwl", 0xce } }, +{ "casel", {"rlrlrl", 0xcf } }, +{ "movl", {"rlwl", 0xd0 } }, +{ "cmpl", {"rlrl", 0xd1 } }, +{ "mcoml", {"rlwl", 0xd2 } }, +{ "bitl", {"rlrl", 0xd3 } }, +{ "clrf", {"wf", 0xd4 } }, +{ "clrl", {"wl", 0xd4 } }, +{ "tstl", {"rl", 0xd5 } }, +{ "incl", {"ml", 0xd6 } }, +{ "decl", {"ml", 0xd7 } }, +{ "adwc", {"rlml", 0xd8 } }, +{ "sbwc", {"rlml", 0xd9 } }, +{ "mtpr", {"rlrl", 0xda } }, +{ "mfpr", {"rlwl", 0xdb } }, +{ "movpsl", {"wl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "moval", {"alwl", 0xde } }, +{ "movaf", {"afwl", 0xde } }, +{ "pushal", {"al", 0xdf } }, +{ "pushaf", {"af", 0xdf } }, +{ "bbs", {"rlvbbb", 0xe0 } }, +{ "bbc", {"rlvbbb", 0xe1 } }, +{ "bbss", {"rlvbbb", 0xe2 } }, +{ "bbcs", {"rlvbbb", 0xe3 } }, +{ "bbsc", {"rlvbbb", 0xe4 } }, +{ "bbcc", {"rlvbbb", 0xe5 } }, +{ "bbssi", {"rlvbbb", 0xe6 } }, +{ "bbcci", {"rlvbbb", 0xe7 } }, +{ "blbs", {"rlbb", 0xe8 } }, +{ "blbc", {"rlbb", 0xe9 } }, +{ "ffs", {"rlrbvbwl", 0xea } }, +{ "ffc", {"rlrbvbwl", 0xeb } }, +{ "cmpv", {"rlrbvbrl", 0xec } }, +{ "cmpzv", {"rlrbvbrl", 0xed } }, +{ "extv", {"rlrbvbwl", 0xee } }, +{ "extzv", {"rlrbvbwl", 0xef } }, +{ "insv", {"rlrlrbvb", 0xf0 } }, +{ "acbl", {"rlrlmlbw", 0xf1 } }, +{ "aoblss", {"rlmlbb", 0xf2 } }, +{ "aobleq", {"rlmlbb", 0xf3 } }, +{ "sobgeq", {"mlbb", 0xf4 } }, +{ "sobgtr", {"mlbb", 0xf5 } }, +{ "cvtlb", {"rlwb", 0xf6 } }, +{ "cvtlw", {"rlww", 0xf7 } }, +{ "ashp", {"rbrwabrbrwab", 0xf8 } }, +{ "cvtlp", {"rlrwab", 0xf9 } }, +{ "callg", {"abab", 0xfa } }, +{ "calls", {"rlab", 0xfb } }, +{ "xfc", {"", 0xfc } }, + /* undefined opcodes here */ +{ "cvtdh", {"rdwh", 0x32fd } }, +{ "cvtgf", {"rgwh", 0x33fd } }, +{ "addg2", {"rgmg", 0x40fd } }, +{ "addg3", {"rgrgwg", 0x41fd } }, +{ "subg2", {"rgmg", 0x42fd } }, +{ "subg3", {"rgrgwg", 0x43fd } }, +{ "mulg2", {"rgmg", 0x44fd } }, +{ "mulg3", {"rgrgwg", 0x45fd } }, +{ "divg2", {"rgmg", 0x46fd } }, +{ "divg3", {"rgrgwg", 0x47fd } }, +{ "cvtgb", {"rgwb", 0x48fd } }, +{ "cvtgw", {"rgww", 0x49fd } }, +{ "cvtgl", {"rgwl", 0x4afd } }, +{ "cvtrgl", {"rgwl", 0x4bfd } }, +{ "cvtbg", {"rbwg", 0x4cfd } }, +{ "cvtwg", {"rwwg", 0x4dfd } }, +{ "cvtlg", {"rlwg", 0x4efd } }, +{ "acbg", {"rgrgmgbw", 0x4ffd } }, +{ "movg", {"rgwg", 0x50fd } }, +{ "cmpg", {"rgrg", 0x51fd } }, +{ "mnegg", {"rgwg", 0x52fd } }, +{ "tstg", {"rg", 0x53fd } }, +{ "emodg", {"rgrwrgwlwg", 0x54fd } }, +{ "polyg", {"rgrwab", 0x55fd } }, +{ "cvtgh", {"rgwh", 0x56fd } }, + /* undefined opcodes here */ +{ "addh2", {"rhmh", 0x60fd } }, +{ "addh3", {"rhrhwh", 0x61fd } }, +{ "subh2", {"rhmh", 0x62fd } }, +{ "subh3", {"rhrhwh", 0x63fd } }, +{ "mulh2", {"rhmh", 0x64fd } }, +{ "mulh3", {"rhrhwh", 0x65fd } }, +{ "divh2", {"rhmh", 0x66fd } }, +{ "divh3", {"rhrhwh", 0x67fd } }, +{ "cvthb", {"rhwb", 0x68fd } }, +{ "cvthw", {"rhww", 0x69fd } }, +{ "cvthl", {"rhwl", 0x6afd } }, +{ "cvtrhl", {"rhwl", 0x6bfd } }, +{ "cvtbh", {"rbwh", 0x6cfd } }, +{ "cvtwh", {"rwwh", 0x6dfd } }, +{ "cvtlh", {"rlwh", 0x6efd } }, +{ "acbh", {"rhrhmhbw", 0x6ffd } }, +{ "movh", {"rhwh", 0x70fd } }, +{ "cmph", {"rhrh", 0x71fd } }, +{ "mnegh", {"rhwh", 0x72fd } }, +{ "tsth", {"rh", 0x73fd } }, +{ "emodh", {"rhrwrhwlwh", 0x74fd } }, +{ "polyh", {"rhrwab", 0x75fd } }, +{ "cvthg", {"rhwg", 0x76fd } }, + /* undefined opcodes here */ +{ "clrh", {"wh", 0x7cfd } }, +{ "clro", {"wo", 0x7cfd } }, +{ "movo", {"rowo", 0x7dfd } }, +{ "movah", {"ahwl", 0x7efd } }, +{ "movao", {"aowl", 0x7efd } }, +{ "pushah", {"ah", 0x7ffd } }, +{ "pushao", {"ao", 0x7ffd } }, + /* undefined opcodes here */ +{ "cvtfh", {"rfwh", 0x98fd } }, +{ "cvtfg", {"rfwg", 0x99fd } }, + /* undefined opcodes here */ +{ "cvthf", {"rhwf", 0xf6fd } }, +{ "cvthd", {"rhwd", 0xf7fd } }, + /* undefined opcodes here */ +{ "bugl", {"rl", 0xfdff } }, +{ "bugw", {"rw", 0xfeff } }, + /* undefined opcodes here */ + +{ "", {"", 0} } /* empty is end sentinel */ + +}; /* votstrs */ + +/* end: vax.opcode.h */ diff --git a/external/gpl3/gdb/dist/include/os9k.h b/external/gpl3/gdb/dist/include/os9k.h new file mode 100644 index 000000000000..e8baee17f1f5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/os9k.h @@ -0,0 +1,181 @@ +/* os9k.h - OS-9000 i386 module header definitions + Copyright 2000 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#if !defined(_MODULE_H) +#define _MODULE_H + +#define _MPF386 + +/* Size of common header less parity field. */ +#define N_M_PARITY (sizeof(mh_com)-sizeof(unisgned short)) +#define OLD_M_PARITY 46 +#define M_PARITY N_M_PARITY + +#ifdef _MPF68K +#define MODSYNC 0x4afc /* Module header sync code for 680x0 processors. */ +#endif + +#ifdef _MPF386 +#define MODSYNC 0x4afc /* Module header sync code for 80386 processors. */ +#endif + +#define MODREV 1 /* Module format revision 1. */ +#define CRCCON 0x800063 /* CRC polynomial constant. */ + +/* Module access permission values. */ +#define MP_OWNER_READ 0x0001 +#define MP_OWNER_WRITE 0x0002 +#define MP_OWNER_EXEC 0x0004 +#define MP_GROUP_READ 0x0010 +#define MP_GROUP_WRITE 0x0020 +#define MP_GROUP_EXEC 0x0040 +#define MP_WORLD_READ 0x0100 +#define MP_WORLD_WRITE 0x0200 +#define MP_WORLD_EXEC 0x0400 +#define MP_WORLD_ACCESS 0x0777 +#define MP_OWNER_MASK 0x000f +#define MP_GROUP_MASK 0x00f0 +#define MP_WORLD_MASK 0x0f00 +#define MP_SYSTM_MASK 0xf000 + +/* Module Type/Language values. */ +#define MT_ANY 0 +#define MT_PROGRAM 0x0001 +#define MT_SUBROUT 0x0002 +#define MT_MULTI 0x0003 +#define MT_DATA 0x0004 +#define MT_TRAPLIB 0x000b +#define MT_SYSTEM 0x000c +#define MT_FILEMAN 0x000d +#define MT_DEVDRVR 0x000e +#define MT_DEVDESC 0x000f +#define MT_MASK 0xff00 + +#define ML_ANY 0 +#define ML_OBJECT 1 +#define ML_ICODE 2 +#define ML_PCODE 3 +#define ML_CCODE 4 +#define ML_CBLCODE 5 +#define ML_FRTNCODE 6 +#define ML_MASK 0x00ff + +#define mktypelang(type, lang) (((type) << 8) | (lang)) + +/* Module Attribute values. */ +#define MA_REENT 0x80 +#define MA_GHOST 0x40 +#define MA_SUPER 0x20 +#define MA_MASK 0xff00 +#define MR_MASK 0x00ff + +#define mkattrevs(attr, revs) (((attr) << 8) | (revs)) + +#define m_user m_owner.grp_usr.usr +#define m_group m_owner.grp_usr.grp +#define m_group_user m_owner.group_user + +/* Macro definitions for accessing module header fields. */ +#define MODNAME(mod) ((u_char*)((u_char*)mod + ((Mh_com)mod)->m_name)) +#if 0 +/* Appears not to be used, and the u_int32 typedef is gone (because it + conflicted with a Mach header. */ +#define MODSIZE(mod) ((u_int32)((Mh_com)mod)->m_size) +#endif /* 0 */ +#define MHCOM_BYTES_SIZE 80 +#define N_BADMAG(a) (((a).a_info) != MODSYNC) + +typedef struct mh_com +{ + /* Sync bytes ($4afc). */ + unsigned char m_sync[2]; + unsigned char m_sysrev[2]; /* System revision check value. */ + unsigned char m_size[4]; /* Module size. */ + unsigned char m_owner[4]; /* Group/user id. */ + unsigned char m_name[4]; /* Offset to module name. */ + unsigned char m_access[2]; /* Access permissions. */ + unsigned char m_tylan[2]; /* Type/lang. */ + unsigned char m_attrev[2]; /* Rev/attr. */ + unsigned char m_edit[2]; /* Edition. */ + unsigned char m_needs[4]; /* Module hardware requirements flags. (reserved). */ + unsigned char m_usage[4]; /* Comment string offset. */ + unsigned char m_symbol[4]; /* Symbol table offset. */ + unsigned char m_exec[4]; /* Offset to execution entry point. */ + unsigned char m_excpt[4]; /* Offset to exception entry point. */ + unsigned char m_data[4]; /* Data storage requirement. */ + unsigned char m_stack[4]; /* Stack size. */ + unsigned char m_idata[4]; /* Offset to initialized data. */ + unsigned char m_idref[4]; /* Offset to data reference lists. */ + unsigned char m_init[4]; /* Initialization routine offset. */ + unsigned char m_term[4]; /* Termination routine offset. */ + unsigned char m_ident[2]; /* Ident code for ident program. */ + char m_spare[8]; /* Reserved bytes. */ + unsigned char m_parity[2]; /* Header parity. */ +} mh_com,*Mh_com; + +/* Executable memory module. */ +typedef mh_com *Mh_exec,mh_exec; + +/* Data memory module. */ +typedef mh_com *Mh_data,mh_data; + +/* File manager memory module. */ +typedef mh_com *Mh_fman,mh_fman; + +/* Device driver module. */ +typedef mh_com *Mh_drvr,mh_drvr; + +/* Trap handler module. */ +typedef mh_com mh_trap, *Mh_trap; + +/* Device descriptor module. */ +typedef mh_com *Mh_dev,mh_dev; + +/* Configuration module. */ +typedef mh_com *Mh_config, mh_config; + +#if 0 + +#if !defined(_MODDIR_H) +/* Go get _os_fmod (and others). */ +#include +#endif + +error_code _os_crc (void *, u_int32, int *); +error_code _os_datmod (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_data **); +error_code _os_get_moddir (void *, u_int32 *); +error_code _os_initdata (mh_com *, void *); +error_code _os_link (char **, mh_com **, void **, u_int16 *, u_int16 *); +error_code _os_linkm (mh_com *, void **, u_int16 *, u_int16 *); +error_code _os_load (char *, mh_com **, void **, u_int32, u_int16 *, u_int16 *, u_int32); +error_code _os_mkmodule (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_com **, u_int32); +error_code _os_modaddr (void *, mh_com **); +error_code _os_setcrc (mh_com *); +error_code _os_slink (u_int32, char *, void **, void **, mh_com **); +error_code _os_slinkm (u_int32, mh_com *, void **, void **); +error_code _os_unlink (mh_com *); +error_code _os_unload (char *, u_int32); +error_code _os_tlink (u_int32, char *, void **, mh_trap **, void *, u_int32); +error_code _os_tlinkm (u_int32, mh_com *, void **, void *, u_int32); +error_code _os_iodel (mh_com *); +error_code _os_vmodul (mh_com *, mh_com *, u_int32); +#endif /* 0 */ + +#endif diff --git a/external/gpl3/gdb/dist/include/partition.h b/external/gpl3/gdb/dist/include/partition.h new file mode 100644 index 000000000000..d8b554f8f9a1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/partition.h @@ -0,0 +1,82 @@ +/* List implementation of a partition of consecutive integers. + Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* This package implements a partition of consecutive integers. The + elements are partitioned into classes. Each class is represented + by one of its elements, the canonical element, which is chosen + arbitrarily from elements in the class. The principal operations + on a partition are FIND, which takes an element, determines its + class, and returns the canonical element for that class, and UNION, + which unites the two classes that contain two given elements into a + single class. + + The list implementation used here provides constant-time finds. By + storing the size of each class with the class's canonical element, + it is able to perform unions over all the classes in the partition + in O (N log N) time. */ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" +#include + +struct partition_elem +{ + /* The canonical element that represents the class containing this + element. */ + int class_element; + /* The next element in this class. Elements in each class form a + circular list. */ + struct partition_elem* next; + /* The number of elements in this class. Valid only if this is the + canonical element for its class. */ + unsigned class_count; +}; + +typedef struct partition_def +{ + /* The number of elements in this partition. */ + int num_elements; + /* The elements in the partition. */ + struct partition_elem elements[1]; +} *partition; + +extern partition partition_new (int); +extern void partition_delete (partition); +extern int partition_union (partition, int, int); +extern void partition_print (partition, FILE*); + +/* Returns the canonical element corresponding to the class containing + ELEMENT__ in PARTITION__. */ + +#define partition_find(partition__, element__) \ + ((partition__)->elements[(element__)].class_element) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _PARTITION_H */ diff --git a/external/gpl3/gdb/dist/include/plugin-api.h b/external/gpl3/gdb/dist/include/plugin-api.h new file mode 100644 index 000000000000..7450a9e3838f --- /dev/null +++ b/external/gpl3/gdb/dist/include/plugin-api.h @@ -0,0 +1,314 @@ +/* plugin-api.h -- External linker plugin API. */ + +/* Copyright 2009, 2010 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file defines the interface for writing a linker plugin, which is + described at < http://gcc.gnu.org/wiki/whopr/driver >. */ + +#ifndef PLUGIN_API_H +#define PLUGIN_API_H + +#ifdef HAVE_STDINT_H +#include +#elif defined(HAVE_INTTYPES_H) +#include +#endif +#include +#if !defined(HAVE_STDINT_H) && !defined(HAVE_INTTYPES_H) && \ + !defined(UINT64_MAX) && !defined(uint64_t) +#error can not find uint64_t type +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Status code returned by most API routines. */ + +enum ld_plugin_status +{ + LDPS_OK = 0, + LDPS_NO_SYMS, /* Attempt to get symbols that haven't been added. */ + LDPS_BAD_HANDLE, /* No claimed object associated with given handle. */ + LDPS_ERR + /* Additional Error codes TBD. */ +}; + +/* The version of the API specification. */ + +enum ld_plugin_api_version +{ + LD_PLUGIN_API_VERSION = 1 +}; + +/* The type of output file being generated by the linker. */ + +enum ld_plugin_output_file_type +{ + LDPO_REL, + LDPO_EXEC, + LDPO_DYN +}; + +/* An input file managed by the plugin library. */ + +struct ld_plugin_input_file +{ + const char *name; + int fd; + off_t offset; + off_t filesize; + void *handle; +}; + +/* A symbol belonging to an input file managed by the plugin library. */ + +struct ld_plugin_symbol +{ + char *name; + char *version; + int def; + int visibility; + uint64_t size; + char *comdat_key; + int resolution; +}; + +/* Whether the symbol is a definition, reference, or common, weak or not. */ + +enum ld_plugin_symbol_kind +{ + LDPK_DEF, + LDPK_WEAKDEF, + LDPK_UNDEF, + LDPK_WEAKUNDEF, + LDPK_COMMON +}; + +/* The visibility of the symbol. */ + +enum ld_plugin_symbol_visibility +{ + LDPV_DEFAULT, + LDPV_PROTECTED, + LDPV_INTERNAL, + LDPV_HIDDEN +}; + +/* How a symbol is resolved. */ + +enum ld_plugin_symbol_resolution +{ + LDPR_UNKNOWN = 0, + + /* Symbol is still undefined at this point. */ + LDPR_UNDEF, + + /* This is the prevailing definition of the symbol, with references from + regular object code. */ + LDPR_PREVAILING_DEF, + + /* This is the prevailing definition of the symbol, with no + references from regular objects. It is only referenced from IR + code. */ + LDPR_PREVAILING_DEF_IRONLY, + + /* This definition was pre-empted by a definition in a regular + object file. */ + LDPR_PREEMPTED_REG, + + /* This definition was pre-empted by a definition in another IR file. */ + LDPR_PREEMPTED_IR, + + /* This symbol was resolved by a definition in another IR file. */ + LDPR_RESOLVED_IR, + + /* This symbol was resolved by a definition in a regular object + linked into the main executable. */ + LDPR_RESOLVED_EXEC, + + /* This symbol was resolved by a definition in a shared object. */ + LDPR_RESOLVED_DYN +}; + +/* The plugin library's "claim file" handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_claim_file_handler) ( + const struct ld_plugin_input_file *file, int *claimed); + +/* The plugin library's "all symbols read" handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_all_symbols_read_handler) (void); + +/* The plugin library's cleanup handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_cleanup_handler) (void); + +/* The linker's interface for registering the "claim file" handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_register_claim_file) (ld_plugin_claim_file_handler handler); + +/* The linker's interface for registering the "all symbols read" handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_register_all_symbols_read) ( + ld_plugin_all_symbols_read_handler handler); + +/* The linker's interface for registering the cleanup handler. */ + +typedef +enum ld_plugin_status +(*ld_plugin_register_cleanup) (ld_plugin_cleanup_handler handler); + +/* The linker's interface for adding symbols from a claimed input file. */ + +typedef +enum ld_plugin_status +(*ld_plugin_add_symbols) (void *handle, int nsyms, + const struct ld_plugin_symbol *syms); + +/* The linker's interface for getting the input file information with + an open (possibly re-opened) file descriptor. */ + +typedef +enum ld_plugin_status +(*ld_plugin_get_input_file) (const void *handle, + struct ld_plugin_input_file *file); + +typedef +enum ld_plugin_status +(*ld_plugin_get_view) (const void *handle, const void **viewp); + +/* The linker's interface for releasing the input file. */ + +typedef +enum ld_plugin_status +(*ld_plugin_release_input_file) (const void *handle); + +/* The linker's interface for retrieving symbol resolution information. */ + +typedef +enum ld_plugin_status +(*ld_plugin_get_symbols) (const void *handle, int nsyms, + struct ld_plugin_symbol *syms); + +/* The linker's interface for adding a compiled input file. */ + +typedef +enum ld_plugin_status +(*ld_plugin_add_input_file) (const char *pathname); + +/* The linker's interface for adding a library that should be searched. */ + +typedef +enum ld_plugin_status +(*ld_plugin_add_input_library) (const char *libname); + +/* The linker's interface for adding a library path that should be searched. */ + +typedef +enum ld_plugin_status +(*ld_plugin_set_extra_library_path) (const char *path); + +/* The linker's interface for issuing a warning or error message. */ + +typedef +enum ld_plugin_status +(*ld_plugin_message) (int level, const char *format, ...); + +enum ld_plugin_level +{ + LDPL_INFO, + LDPL_WARNING, + LDPL_ERROR, + LDPL_FATAL +}; + +/* Values for the tv_tag field of the transfer vector. */ + +enum ld_plugin_tag +{ + LDPT_NULL = 0, + LDPT_API_VERSION, + LDPT_GOLD_VERSION, + LDPT_LINKER_OUTPUT, + LDPT_OPTION, + LDPT_REGISTER_CLAIM_FILE_HOOK, + LDPT_REGISTER_ALL_SYMBOLS_READ_HOOK, + LDPT_REGISTER_CLEANUP_HOOK, + LDPT_ADD_SYMBOLS, + LDPT_GET_SYMBOLS, + LDPT_ADD_INPUT_FILE, + LDPT_MESSAGE, + LDPT_GET_INPUT_FILE, + LDPT_RELEASE_INPUT_FILE, + LDPT_ADD_INPUT_LIBRARY, + LDPT_OUTPUT_NAME, + LDPT_SET_EXTRA_LIBRARY_PATH, + LDPT_GNU_LD_VERSION, + LDPT_GET_VIEW +}; + +/* The plugin transfer vector. */ + +struct ld_plugin_tv +{ + enum ld_plugin_tag tv_tag; + union + { + int tv_val; + const char *tv_string; + ld_plugin_register_claim_file tv_register_claim_file; + ld_plugin_register_all_symbols_read tv_register_all_symbols_read; + ld_plugin_register_cleanup tv_register_cleanup; + ld_plugin_add_symbols tv_add_symbols; + ld_plugin_get_symbols tv_get_symbols; + ld_plugin_add_input_file tv_add_input_file; + ld_plugin_message tv_message; + ld_plugin_get_input_file tv_get_input_file; + ld_plugin_get_view tv_get_view; + ld_plugin_release_input_file tv_release_input_file; + ld_plugin_add_input_library tv_add_input_library; + ld_plugin_set_extra_library_path tv_set_extra_library_path; + } tv_u; +}; + +/* The plugin library's "onload" entry point. */ + +typedef +enum ld_plugin_status +(*ld_plugin_onload) (struct ld_plugin_tv *tv); + +#ifdef __cplusplus +} +#endif + +#endif /* !defined(PLUGIN_API_H) */ diff --git a/external/gpl3/gdb/dist/include/progress.h b/external/gpl3/gdb/dist/include/progress.h new file mode 100644 index 000000000000..80ffbe24a86e --- /dev/null +++ b/external/gpl3/gdb/dist/include/progress.h @@ -0,0 +1,38 @@ +/* Default definitions for progress macros. + Copyright 1994, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* The default definitions below are intended to be replaced by real + definitions, if building the tools for an interactive programming + environment. */ + +#ifndef _PROGRESS_H +#define _PROGRESS_H + +#ifndef START_PROGRESS +#define START_PROGRESS(STR,N) +#endif + +#ifndef PROGRESS +#define PROGRESS(X) +#endif + +#ifndef END_PROGRESS +#define END_PROGRESS(STR) +#endif + +#endif /* _PROGRESS_H */ diff --git a/external/gpl3/gdb/dist/include/safe-ctype.h b/external/gpl3/gdb/dist/include/safe-ctype.h new file mode 100644 index 000000000000..0266bf1aa269 --- /dev/null +++ b/external/gpl3/gdb/dist/include/safe-ctype.h @@ -0,0 +1,150 @@ +/* replacement macros. + + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by Zack Weinberg . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* This is a compatible replacement of the standard C library's + with the following properties: + + - Implements all isxxx() macros required by C99. + - Also implements some character classes useful when + parsing C-like languages. + - Does not change behavior depending on the current locale. + - Behaves properly for all values in the range of a signed or + unsigned char. + + To avoid conflicts, this header defines the isxxx functions in upper + case, e.g. ISALPHA not isalpha. */ + +#ifndef SAFE_CTYPE_H +#define SAFE_CTYPE_H + +/* Determine host character set. */ +#define HOST_CHARSET_UNKNOWN 0 +#define HOST_CHARSET_ASCII 1 +#define HOST_CHARSET_EBCDIC 2 + +#if '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \ + && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21 +# define HOST_CHARSET HOST_CHARSET_ASCII +#else +# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \ + && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A +# define HOST_CHARSET HOST_CHARSET_EBCDIC +# else +# define HOST_CHARSET HOST_CHARSET_UNKNOWN +# endif +#endif + +/* Categories. */ + +enum { + /* In C99 */ + _sch_isblank = 0x0001, /* space \t */ + _sch_iscntrl = 0x0002, /* nonprinting characters */ + _sch_isdigit = 0x0004, /* 0-9 */ + _sch_islower = 0x0008, /* a-z */ + _sch_isprint = 0x0010, /* any printing character including ' ' */ + _sch_ispunct = 0x0020, /* all punctuation */ + _sch_isspace = 0x0040, /* space \t \n \r \f \v */ + _sch_isupper = 0x0080, /* A-Z */ + _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */ + + /* Extra categories useful to cpplib. */ + _sch_isidst = 0x0200, /* A-Za-z_ */ + _sch_isvsp = 0x0400, /* \n \r */ + _sch_isnvsp = 0x0800, /* space \t \f \v \0 */ + + /* Combinations of the above. */ + _sch_isalpha = _sch_isupper|_sch_islower, /* A-Za-z */ + _sch_isalnum = _sch_isalpha|_sch_isdigit, /* A-Za-z0-9 */ + _sch_isidnum = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */ + _sch_isgraph = _sch_isalnum|_sch_ispunct, /* isprint and not space */ + _sch_iscppsp = _sch_isvsp|_sch_isnvsp, /* isspace + \0 */ + _sch_isbasic = _sch_isprint|_sch_iscppsp /* basic charset of ISO C + (plus ` and @) */ +}; + +/* Character classification. */ +extern const unsigned short _sch_istable[256]; + +#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit)) + +#define ISALPHA(c) _sch_test(c, _sch_isalpha) +#define ISALNUM(c) _sch_test(c, _sch_isalnum) +#define ISBLANK(c) _sch_test(c, _sch_isblank) +#define ISCNTRL(c) _sch_test(c, _sch_iscntrl) +#define ISDIGIT(c) _sch_test(c, _sch_isdigit) +#define ISGRAPH(c) _sch_test(c, _sch_isgraph) +#define ISLOWER(c) _sch_test(c, _sch_islower) +#define ISPRINT(c) _sch_test(c, _sch_isprint) +#define ISPUNCT(c) _sch_test(c, _sch_ispunct) +#define ISSPACE(c) _sch_test(c, _sch_isspace) +#define ISUPPER(c) _sch_test(c, _sch_isupper) +#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit) + +#define ISIDNUM(c) _sch_test(c, _sch_isidnum) +#define ISIDST(c) _sch_test(c, _sch_isidst) +#define IS_ISOBASIC(c) _sch_test(c, _sch_isbasic) +#define IS_VSPACE(c) _sch_test(c, _sch_isvsp) +#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp) +#define IS_SPACE_OR_NUL(c) _sch_test(c, _sch_iscppsp) + +/* Character transformation. */ +extern const unsigned char _sch_toupper[256]; +extern const unsigned char _sch_tolower[256]; +#define TOUPPER(c) _sch_toupper[(c) & 0xff] +#define TOLOWER(c) _sch_tolower[(c) & 0xff] + +/* Prevent the users of safe-ctype.h from accidently using the routines + from ctype.h. Initially, the approach was to produce an error when + detecting that ctype.h has been included. But this was causing + trouble as ctype.h might get indirectly included as a result of + including another system header (for instance gnulib's stdint.h). + So we include ctype.h here and then immediately redefine its macros. */ + +#include +#undef isalpha +#define isalpha(c) do_not_use_isalpha_with_safe_ctype +#undef isalnum +#define isalnum(c) do_not_use_isalnum_with_safe_ctype +#undef iscntrl +#define iscntrl(c) do_not_use_iscntrl_with_safe_ctype +#undef isdigit +#define isdigit(c) do_not_use_isdigit_with_safe_ctype +#undef isgraph +#define isgraph(c) do_not_use_isgraph_with_safe_ctype +#undef islower +#define islower(c) do_not_use_islower_with_safe_ctype +#undef isprint +#define isprint(c) do_not_use_isprint_with_safe_ctype +#undef ispunct +#define ispunct(c) do_not_use_ispunct_with_safe_ctype +#undef isspace +#define isspace(c) do_not_use_isspace_with_safe_ctype +#undef isupper +#define isupper(c) do_not_use_isupper_with_safe_ctype +#undef isxdigit +#define isxdigit(c) do_not_use_isxdigit_with_safe_ctype +#undef toupper +#define toupper(c) do_not_use_toupper_with_safe_ctype +#undef tolower +#define tolower(c) do_not_use_tolower_with_safe_ctype + +#endif /* SAFE_CTYPE_H */ diff --git a/external/gpl3/gdb/dist/include/sha1.h b/external/gpl3/gdb/dist/include/sha1.h new file mode 100644 index 000000000000..5473f91f412b --- /dev/null +++ b/external/gpl3/gdb/dist/include/sha1.h @@ -0,0 +1,141 @@ +/* Declarations of functions and data types used for SHA1 sum + library functions. + Copyright (C) 2000, 2001, 2003, 2005, 2006, 2008, 2010 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef SHA1_H +# define SHA1_H 1 + +#include + +#if defined HAVE_LIMITS_H || _LIBC +# include +#endif + +#include "ansidecl.h" + +/* The following contortions are an attempt to use the C preprocessor + to determine an unsigned integral type that is 32 bits wide. An + alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but + doing that would require that the configure script compile and *run* + the resulting executable. Locally running cross-compiled executables + is usually not possible. */ + +#ifdef _LIBC +# include +typedef u_int32_t sha1_uint32; +typedef uintptr_t sha1_uintptr; +#else +# define INT_MAX_32_BITS 2147483647 + +/* If UINT_MAX isn't defined, assume it's a 32-bit type. + This should be valid for all systems GNU cares about because + that doesn't include 16-bit systems, and only modern systems + (that certainly have ) have 64+-bit integral types. */ + +# ifndef INT_MAX +# define INT_MAX INT_MAX_32_BITS +# endif + +# if INT_MAX == INT_MAX_32_BITS + typedef unsigned int sha1_uint32; +# else +# if SHRT_MAX == INT_MAX_32_BITS + typedef unsigned short sha1_uint32; +# else +# if LONG_MAX == INT_MAX_32_BITS + typedef unsigned long sha1_uint32; +# else + /* The following line is intended to evoke an error. + Using #error is not portable enough. */ + "Cannot determine unsigned 32-bit data type." +# endif +# endif +# endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Structure to save state of computation between the single steps. */ +struct sha1_ctx +{ + sha1_uint32 A; + sha1_uint32 B; + sha1_uint32 C; + sha1_uint32 D; + sha1_uint32 E; + + sha1_uint32 total[2]; + sha1_uint32 buflen; + sha1_uint32 buffer[32]; +}; + + +/* Initialize structure containing state of computation. */ +extern void sha1_init_ctx (struct sha1_ctx *ctx); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is necessary that LEN is a multiple of 64!!! */ +extern void sha1_process_block (const void *buffer, size_t len, + struct sha1_ctx *ctx); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is NOT required that LEN is a multiple of 64. */ +extern void sha1_process_bytes (const void *buffer, size_t len, + struct sha1_ctx *ctx); + +/* Process the remaining bytes in the buffer and put result from CTX + in first 20 bytes following RESBUF. The result is always in little + endian byte order, so that a byte-wise output yields to the wanted + ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF be correctly + aligned for a 32 bits value. */ +extern void *sha1_finish_ctx (struct sha1_ctx *ctx, void *resbuf); + + +/* Put result from CTX in first 20 bytes following RESBUF. The result is + always in little endian byte order, so that a byte-wise output yields + to the wanted ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *sha1_read_ctx (const struct sha1_ctx *ctx, void *resbuf); + + +/* Compute SHA1 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 20 bytes + beginning at RESBLOCK. */ +extern int sha1_stream (FILE *stream, void *resblock); + +/* Compute SHA1 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +extern void *sha1_buffer (const char *buffer, size_t len, void *resblock); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/simple-object.h b/external/gpl3/gdb/dist/include/simple-object.h new file mode 100644 index 000000000000..c4786757a1e7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/simple-object.h @@ -0,0 +1,204 @@ +/* simple-object.h -- simple routines to read and write object files + Copyright 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Google. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef SIMPLE_OBJECT_H +#define SIMPLE_OBJECT_H + +#include +#include + +#ifdef HAVE_UNISTD_H +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* This header file provides four types with associated functions. + They are used to read and write object files. This is a minimal + interface, intended to support the needs of gcc without bringing in + all the power and complexity of BFD. */ + +/* The type simple_object_read * is used to read an existing object + file. */ + +typedef struct simple_object_read_struct simple_object_read; + +/* Create an simple_object_read given DESCRIPTOR, an open file + descriptor, and OFFSET, an offset within the file. The offset is + for use with archives, and should be 0 for an ordinary object file. + The descriptor must remain open until done with the returned + simple_object_read. SEGMENT_NAME is used on Mach-O and is required + on that platform: it means to only look at sections within the + segment with that name. It is ignored for other object file + formats. On error, this function returns NULL, and sets *ERRMSG to + an error string and sets *ERR to an errno value or 0 if there is no + relevant errno. */ + +extern simple_object_read * +simple_object_start_read (int descriptor, off_t offset, + const char *segment_name, const char **errmsg, + int *err); + +/* Call PFN for each section in SIMPLE_OBJECT, passing it the section + name, offset within the file of the section contents, and length of + the section contents. The offset within the file is relative to + the offset passed to simple_object_start_read. The DATA argument + to simple_object_find_sections is passed on to PFN. If PFN returns + 0, the loop is stopped and simple_object_find_sections returns. If + PFN returns non-zero, the loop continues. On success this returns + NULL. On error it returns an error string, and sets *ERR to an + errno value or 0 if there is no relevant errno. */ + +extern const char * +simple_object_find_sections (simple_object_read *simple_object, + int (*pfn) (void *data, const char *, + off_t offset, off_t length), + void *data, + int *err); + +/* Look for the section NAME in SIMPLE_OBJECT. This returns + information for the first section NAME in SIMPLE_OBJECT. Note that + calling this multiple times is inefficient; use + simple_object_find_sections instead. + + If found, return 1 and set *OFFSET to the offset in the file of the + section contents and set *LENGTH to the length of the section + contents. *OFFSET will be relative to the offset passed to + simple_object_start_read. + + If the section is not found, and no error occurs, return 0 and set + *ERRMSG to NULL. + + If an error occurs, return 0, set *ERRMSG to an error message, and + set *ERR to an errno value or 0 if there is no relevant errno. */ + +extern int +simple_object_find_section (simple_object_read *simple_object, + const char *name, off_t *offset, off_t *length, + const char **errmsg, int *err); + +/* Release all resources associated with SIMPLE_OBJECT. This does not + close the file descriptor. */ + +extern void +simple_object_release_read (simple_object_read *); + +/* The type simple_object_attributes holds the attributes of an object + file that matter for creating a file or ensuring that two files are + compatible. This is a set of magic numbers. */ + +typedef struct simple_object_attributes_struct simple_object_attributes; + +/* Fetch the attributes of SIMPLE_OBJECT. This information will + persist until simple_object_attributes_release is called, even if + SIMPLE_OBJECT is closed. On error this returns NULL, sets *ERRMSG + to an error message, and sets *ERR to an errno value or 0 if there + isn't one. */ + +extern simple_object_attributes * +simple_object_fetch_attributes (simple_object_read *simple_object, + const char **errmsg, int *err); + +/* Merge the FROM attributes into TO. If two objects with these + attributes could be linked together without error, returns NULL. + Otherwise, returns an error message, and sets *ERR to an errno + value or 0 if there isn't one. */ + +extern const char * +simple_object_attributes_merge (simple_object_attributes *to, + simple_object_attributes *from, + int *err); + +/* Release all resources associated with ATTRS. */ + +extern void +simple_object_release_attributes (simple_object_attributes *attrs); + +/* The type simple_object_write is used to create a new object file. */ + +typedef struct simple_object_write_struct simple_object_write; + +/* Start creating a new object file which is like ATTRS. You must + fetch attribute information from an existing object file before you + can create a new one. There is currently no support for creating + an object file de novo. The segment name is only used on Mach-O, + where it is required. It means that all sections are created + within that segment. It is ignored for other object file formats. + On error this function returns NULL, sets *ERRMSG to an error + message, and sets *ERR to an errno value or 0 if there isn't + one. */ + +extern simple_object_write * +simple_object_start_write (simple_object_attributes *attrs, + const char *segment_name, + const char **errmsg, int *err); + +/* The type simple_object_write_section is a handle for a section + which is being written. */ + +typedef struct simple_object_write_section_struct simple_object_write_section; + +/* Add a section to SIMPLE_OBJECT. NAME is the name of the new + section. ALIGN is the required alignment expressed as the number + of required low-order 0 bits (e.g., 2 for alignment to a 32-bit + boundary). The section is created as containing data, readable, + not writable, not executable, not loaded at runtime. On error this + returns NULL, sets *ERRMSG to an error message, and sets *ERR to an + errno value or 0 if there isn't one. */ + +extern simple_object_write_section * +simple_object_write_create_section (simple_object_write *simple_object, + const char *name, unsigned int align, + const char **errmsg, int *err); + +/* Add data BUFFER/SIZE to SECTION in SIMPLE_OBJECT. If COPY is + non-zero, the data will be copied into memory if necessary. If + COPY is zero, BUFFER must persist until SIMPLE_OBJECT is released. + On success this returns NULL. On error this returns an error + message, and sets *ERR to an errno value or 0 if there isn't + one. */ + +extern const char * +simple_object_write_add_data (simple_object_write *simple_object, + simple_object_write_section *section, + const void *buffer, size_t size, + int copy, int *err); + +/* Write the complete object file to DESCRIPTOR, an open file + descriptor. This returns NULL on success. On error this returns + an error message, and sets *ERR to an errno value or 0 if there + isn't one. */ + +extern const char * +simple_object_write_to_file (simple_object_write *simple_object, + int descriptor, int *err); + +/* Release all resources associated with SIMPLE_OBJECT, including any + simple_object_write_section's that may have been created. */ + +extern void +simple_object_release_write (simple_object_write *); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/external/gpl3/gdb/dist/include/som/ChangeLog b/external/gpl3/gdb/dist/include/som/ChangeLog new file mode 100644 index 000000000000..f55a417268f8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/ChangeLog @@ -0,0 +1,7 @@ +2010-06-10 Tristan Gingold + + * aout.h: New file. + * clock.h: Likewise. + * lst.h: Likewise. + * reloc.h: Likewise. + * internal.h: Likewise. diff --git a/external/gpl3/gdb/dist/include/som/aout.h b/external/gpl3/gdb/dist/include/som/aout.h new file mode 100644 index 000000000000..c3845edf630d --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/aout.h @@ -0,0 +1,249 @@ +/* SOM a.out definitions for BFD. + Copyright 2010 Free Software Foundation, Inc. + Contributed by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _SOM_AOUT_H +#define _SOM_AOUT_H + +#include "clock.h" + +/* Note: SOM uses bit-field in its structure. All you need to know is: + - CPUs supported by SOM (hppa) are big-endian, + - the MSB is numbered 0. */ + +struct som_external_header +{ + unsigned char system_id[2]; + unsigned char a_magic[2]; + unsigned char version_id[4]; + struct som_external_clock file_time; + unsigned char entry_space[4]; + unsigned char entry_subspace[4]; + unsigned char entry_offset[4]; + unsigned char aux_header_location[4]; + unsigned char aux_header_size[4]; + unsigned char som_length[4]; + unsigned char presumed_dp[4]; + unsigned char space_location[4]; + unsigned char space_total[4]; + unsigned char subspace_location[4]; + unsigned char subspace_total[4]; + unsigned char loader_fixup_location[4]; + unsigned char loader_fixup_total[4]; + unsigned char space_strings_location[4]; + unsigned char space_strings_size[4]; + unsigned char init_array_location[4]; + unsigned char init_array_total[4]; + unsigned char compiler_location[4]; + unsigned char compiler_total[4]; + unsigned char symbol_location[4]; + unsigned char symbol_total[4]; + unsigned char fixup_request_location[4]; + unsigned char fixup_request_total[4]; + unsigned char symbol_strings_location[4]; + unsigned char symbol_strings_size[4]; + unsigned char unloadable_sp_location[4]; + unsigned char unloadable_sp_size[4]; + unsigned char checksum[4]; +}; + +#define OLD_VERSION_ID 85082112 +#define NEW_VERSION_ID 87102412 + +#define EXECLIBMAGIC 0x0104 +#define RELOC_MAGIC 0x0106 +#define EXEC_MAGIC 0x0107 +#define SHARE_MAGIC 0x0108 +#define SHMEM_MAGIC 0x0109 +#define DEMAND_MAGIC 0x010b +#define DL_MAGIC 0x010d +#define SHL_MAGIC 0x010e + +struct som_external_aux_id +{ + unsigned char flags[4]; + unsigned char length[4]; +}; + +/* Aux id types. */ +#define VERSION_AUX_ID 6 +#define COPYRIGHT_AUX_ID 9 + +/* Aux id flags. */ +#define SOM_AUX_ID_MANDATORY (1 << 31) +#define SOM_AUX_ID_COPY (1 << 30) +#define SOM_AUX_ID_APPEND (1 << 29) +#define SOM_AUX_ID_IGNORE (1 << 28) +#define SOM_AUX_ID_TYPE_SH 0 +#define SOM_AUX_ID_TYPE_MASK 0xffff + +struct som_external_string_auxhdr +{ + struct som_external_aux_id header_id; + + /* Length of the string, without the NUL. */ + unsigned char string_length[4]; + + /* The string. */ +}; + +struct som_external_exec_auxhdr +{ + struct som_external_aux_id som_auxhdr; + + unsigned char exec_tsize[4]; + unsigned char exec_tmem[4]; + unsigned char exec_tfile[4]; + unsigned char exec_dsize[4]; + unsigned char exec_dmem[4]; + unsigned char exec_dfile[4]; + unsigned char exec_bsize[4]; + unsigned char exec_entry[4]; + unsigned char exec_flags[4]; + unsigned char exec_bfill[4]; +}; + +#define AUX_HDR_SIZE sizeof (struct som_external_exec_auxhdr) + +struct som_external_space_dictionary_record +{ + unsigned char name[4]; + unsigned char flags[4]; + unsigned char space_number[4]; + unsigned char subspace_index[4]; + unsigned char subspace_quantity[4]; + unsigned char loader_fix_index[4]; + unsigned char loader_fix_quantity[4]; + unsigned char init_pointer_index[4]; + unsigned char init_pointer_quantity[4]; +}; + +#define SOM_SPACE_IS_LOADABLE (1 << 31) +#define SOM_SPACE_IS_DEFINED (1 << 30) +#define SOM_SPACE_IS_PRIVATE (1 << 29) +#define SOM_SPACE_HAS_INTERMEDIATE_CODE (1 << 28) +#define SOM_SPACE_IS_TSPECIFIC (1 << 27) +#define SOM_SPACE_SORT_KEY_SH 8 +#define SOM_SPACE_SORT_KEY_MASK 0xff + +struct som_external_subspace_dictionary_record +{ + unsigned char space_index[4]; + unsigned char flags[4]; + unsigned char file_loc_init_value[4]; + unsigned char initialization_length[4]; + unsigned char subspace_start[4]; + unsigned char subspace_length[4]; + unsigned char alignment[4]; + unsigned char name[4]; + unsigned char fixup_request_index[4]; + unsigned char fixup_request_quantity[4]; +}; + +#define SOM_SUBSPACE_ACCESS_CONTROL_BITS_SH 25 +#define SOM_SUBSPACE_ACCESS_CONTROL_BITS_MASK 0x7f +#define SOM_SUBSPACE_MEMORY_RESIDENT (1 << 24) +#define SOM_SUBSPACE_DUP_COMMON (1 << 23) +#define SOM_SUBSPACE_IS_COMMON (1 << 22) +#define SOM_SUBSPACE_IS_LOADABLE (1 << 21) +#define SOM_SUBSPACE_QUADRANT_SH 19 +#define SOM_SUBSPACE_QUADRANT_MASK 0x3 +#define SOM_SUBSPACE_INITIALLY_FROZEN (1 << 18) +#define SOM_SUBSPACE_IS_FIRST (1 << 17) +#define SOM_SUBSPACE_CODE_ONLY (1 << 16) +#define SOM_SUBSPACE_SORT_KEY_SH 8 +#define SOM_SUBSPACE_SORT_KEY_MASK 0xff +#define SOM_SUBSPACE_REPLICATE_INIT (1 << 7) +#define SOM_SUBSPACE_CONTINUATION (1 << 6) +#define SOM_SUBSPACE_IS_TSPECIFIC (1 << 5) +#define SOM_SUBSPACE_IS_COMDAT (1 << 4) + +struct som_external_compilation_unit +{ + unsigned char name[4]; + unsigned char language_name[4]; + unsigned char product_id[4]; + unsigned char version_id[4]; + unsigned char flags[4]; + struct som_external_clock compile_time; + struct som_external_clock source_time; +}; + +struct som_external_symbol_dictionary_record +{ + unsigned char flags[4]; + unsigned char name[4]; + unsigned char qualifier_name[4]; + unsigned char info[4]; + unsigned char symbol_value[4]; +}; + +/* Flags fields. */ +#define SOM_SYMBOL_HIDDEN (1 << 31) +#define SOM_SYMBOL_SECONDARY_DEF (1 << 30) +#define SOM_SYMBOL_TYPE_SH 24 +#define SOM_SYMBOL_TYPE_MASK 0x3f +#define SOM_SYMBOL_SCOPE_SH 20 +#define SOM_SYMBOL_SCOPE_MASK 0xf +#define SOM_SYMBOL_CHECK_LEVEL_SH 17 +#define SOM_SYMBOL_CHECK_LEVEL_MASK 0x7 +#define SOM_SYMBOL_MUST_QUALIFY (1 << 16) +#define SOM_SYMBOL_INITIALLY_FROZEN (1 << 15) +#define SOM_SYMBOL_MEMORY_RESIDENT (1 << 14) +#define SOM_SYMBOL_IS_COMMON (1 << 13) +#define SOM_SYMBOL_DUP_COMMON (1 << 12) +#define SOM_SYMBOL_XLEAST_SH 10 +#define SOM_SYMBOL_XLEAT_MASK 0x3 +#define SOM_SYMBOL_ARG_RELOC_SH 0 +#define SOM_SYMBOL_ARG_RELOC_MASK 0x3ff + +/* Info fields. */ +#define SOM_SYMBOL_HAS_LONG_RETURN (1 << 31) +#define SOM_SYMBOL_NO_RELOCATION (1 << 30) +#define SOM_SYMBOL_IS_COMDAT (1 << 29) +#define SOM_SYMBOL_SYMBOL_INFO_SH 0 +#define SOM_SYMBOL_SYMBOL_INFO_MASK 0xffffff + +/* Symbol type definition. */ +#define ST_NULL 0 +#define ST_ABSOLUTE 1 +#define ST_DATA 2 +#define ST_CODE 3 +#define ST_PRI_PROG 4 +#define ST_SEC_PROG 5 +#define ST_ENTRY 6 +#define ST_STORAGE 7 +#define ST_STUB 8 +#define ST_MODULE 9 +#define ST_SYM_EXT 10 +#define ST_ARG_EXT 11 +#define ST_MILLICODE 12 +#define ST_PLABEL 13 +#define ST_OCT_DIS 14 +#define ST_MILLI_EXT 15 +#define ST_TSTORAGE 16 +#define ST_COMDAT 17 + +/* Symbol scope. */ +#define SS_UNSAT 0 +#define SS_EXTERNAL 1 +#define SS_LOCAL 2 +#define SS_UNIVERSAL 3 + +#endif /* _SOM_AOUT_H */ diff --git a/external/gpl3/gdb/dist/include/som/clock.h b/external/gpl3/gdb/dist/include/som/clock.h new file mode 100644 index 000000000000..e2a7ba6d4f2c --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/clock.h @@ -0,0 +1,30 @@ +/* SOM clock definition for BFD. + Copyright 2010 Free Software Foundation, Inc. + Contributed by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _SOM_CLOCK_H +#define _SOM_CLOCK_H + +struct som_external_clock +{ + unsigned char secs[4]; + unsigned char nanosecs[4]; +}; + +#endif /* _SOM_CLOCK_H */ diff --git a/external/gpl3/gdb/dist/include/som/internal.h b/external/gpl3/gdb/dist/include/som/internal.h new file mode 100644 index 000000000000..e3889fb59bce --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/internal.h @@ -0,0 +1,206 @@ +/* SOM internal definitions for BFD. + Copyright 2010 Free Software Foundation, Inc. + Contributed by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _SOM_INTERNAL_H +#define _SOM_INTERNAL_H + +struct som_clock +{ + unsigned int secs; + unsigned int nanosecs; +}; + +struct som_header +{ + unsigned short system_id; + unsigned short a_magic; + unsigned int version_id; + struct som_clock file_time; + unsigned int entry_space; + unsigned int entry_subspace; + unsigned int entry_offset; + unsigned int aux_header_location; + unsigned int aux_header_size; + unsigned int som_length; + unsigned int presumed_dp; + unsigned int space_location; + unsigned int space_total; + unsigned int subspace_location; + unsigned int subspace_total; + unsigned int loader_fixup_location; + unsigned int loader_fixup_total; + unsigned int space_strings_location; + unsigned int space_strings_size; + unsigned int init_array_location; + unsigned int init_array_total; + unsigned int compiler_location; + unsigned int compiler_total; + unsigned int symbol_location; + unsigned int symbol_total; + unsigned int fixup_request_location; + unsigned int fixup_request_total; + unsigned int symbol_strings_location; + unsigned int symbol_strings_size; + unsigned int unloadable_sp_location; + unsigned int unloadable_sp_size; + unsigned int checksum; +}; + +struct som_aux_id +{ + unsigned int mandatory : 1; + unsigned int copy : 1; + unsigned int append : 1; + unsigned int ignore : 1; + unsigned int reserved : 12; + + /* Header type. */ + unsigned int type : 16; + + /* Length of the header in bytes, without the two word identifier. */ + unsigned int length; +}; + +/* Generic auxiliary string header. */ +struct som_string_auxhdr +{ + struct som_aux_id header_id; + + /* Length of the string, without the NUL. */ + unsigned int string_length; + + /* The string. */ + char string[1]; +}; + +struct som_name_pt +{ + char *name; + unsigned int strx; +}; + +struct som_compilation_unit +{ + /* Source file that produced the SOM. */ + struct som_name_pt name; + + /* Name of the language used when creating this SOM. */ + struct som_name_pt language_name; + + /* Identificaton of the compiler. */ + struct som_name_pt product_id; + + /* Version id of the compiler. */ + struct som_name_pt version_id; + + unsigned int flags; + struct som_clock compile_time; + struct som_clock source_time; +}; + +struct som_exec_auxhdr +{ + struct som_aux_id som_auxhdr; + + long exec_tsize; + long exec_tmem; + long exec_tfile; + long exec_dsize; + long exec_dmem; + long exec_dfile; + long exec_bsize; + long exec_entry; + long exec_flags; + long exec_bfill; +}; + +struct som_space_dictionary_record +{ + unsigned int name; + unsigned int is_loadable : 1; + unsigned int is_defined : 1; + unsigned int is_private : 1; + unsigned int has_intermediate_code : 1; + unsigned int is_tspecific : 1; + unsigned int reserved : 11; + unsigned int sort_key : 8; + unsigned int reserved2 : 8; + int space_number; + int subspace_index; + unsigned int subspace_quantity; + int loader_fix_index; + unsigned int loader_fix_quantity; + int init_pointer_index; + unsigned int init_pointer_quantity; +}; + +struct som_subspace_dictionary_record +{ + int space_index; + unsigned int access_control_bits : 7; + unsigned int memory_resident : 1; + unsigned int dup_common : 1; + unsigned int is_common : 1; + unsigned int is_loadable : 1; + unsigned int quadrant : 2; + unsigned int initially_frozen : 1; + unsigned int is_first : 1; + unsigned int code_only : 1; + unsigned int sort_key : 8; + unsigned int replicate_init : 1; + unsigned int continuation : 1; + unsigned int is_tspecific : 1; + unsigned int is_comdat : 1; + unsigned int reserved : 4; + int file_loc_init_value; + unsigned int initialization_length; + unsigned int subspace_start; + unsigned int subspace_length; + unsigned int reserved2 : 5; + unsigned int alignment : 27; + unsigned int name; + int fixup_request_index; + unsigned int fixup_request_quantity; +}; + +struct som_lst_header +{ + unsigned short system_id; + unsigned short a_magic; + unsigned int version_id; + struct som_clock file_time; + unsigned int hash_loc; + unsigned int hash_size; + unsigned int module_count; + unsigned int module_limit; + unsigned int dir_loc; + unsigned int export_loc; + unsigned int export_count; + unsigned int import_loc; + unsigned int aux_loc; + unsigned int aux_size; + unsigned int string_loc; + unsigned int string_size; + unsigned int free_list; + unsigned int file_end; + unsigned int checksum; +}; + +#endif /* _SOM_INTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/som/lst.h b/external/gpl3/gdb/dist/include/som/lst.h new file mode 100644 index 000000000000..6088b47c4663 --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/lst.h @@ -0,0 +1,93 @@ +/* SOM lst definitions for BFD. + Copyright 2010 Free Software Foundation, Inc. + Contributed by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _SOM_LST_H +#define _SOM_LST_H + +#include "clock.h" + +/* See 4.2 Libraray Symbol Table Header Record. */ +struct som_external_lst_header +{ + unsigned char system_id[2]; + unsigned char a_magic[2]; + unsigned char version_id[4]; + struct som_external_clock file_time; + unsigned char hash_loc[4]; + unsigned char hash_size[4]; + unsigned char module_count[4]; + unsigned char module_limit[4]; + unsigned char dir_loc[4]; + unsigned char export_loc[4]; + unsigned char export_count[4]; + unsigned char import_loc[4]; + unsigned char aux_loc[4]; + unsigned char aux_size[4]; + unsigned char string_loc[4]; + unsigned char string_size[4]; + unsigned char free_list[4]; + unsigned char file_end[4]; + unsigned char checksum[4]; +}; + +#define VERSION_ID 85082112 +#define LIBMAGIC 0x0619 +#define LIBMAGIC_EXEC 0x0104 + +struct som_external_lst_symbol_record +{ + unsigned char flags[4]; + unsigned char name[4]; + unsigned char qualifier_name[4]; + unsigned char symbol_info[4]; + unsigned char symbol_value[4]; + unsigned char symbol_descriptor[4]; + unsigned char reserved; + unsigned char max_num_args; + unsigned char min_num_args; + unsigned char num_args; + unsigned char som_index[4]; + unsigned char symbol_key[4]; + unsigned char next_entry[4]; +}; + +/* Fields of flags. */ +#define LST_SYMBOL_HIDDEN (1 << 31) +#define LST_SYMBOL_SECONDARY_DEF (1 << 30) +#define LST_SYMBOL_SYMBOL_TYPE_SH 24 +#define LST_SYMBOL_SYMBOL_SCOPE_SH 20 +#define LST_SYMBOL_CHECK_LEVEL_SH 17 +#define LST_SYMBOL_MUST_QUALIFY (1 << 16) +#define LST_SYMBOL_INITIALY_FROZEN (1 << 15) +#define LST_SYMBOL_MEMORY_RESIDENT (1 << 14) +#define LST_SYMBOL_IS_COMMON (1 << 13) +#define LST_SYMBOL_DUP_COMMON (1 << 12) +#define LST_SYMBOL_XLEAST_SH 10 +#define LST_SYMBOL_ARG_RELOC_SH 0 + +/* According to 4.3.2 SOM Directory. */ + +struct som_external_som_entry +{ + unsigned char location[4]; + unsigned char length[4]; +}; + +#endif /* _SOM_LST_H */ diff --git a/external/gpl3/gdb/dist/include/som/reloc.h b/external/gpl3/gdb/dist/include/som/reloc.h new file mode 100644 index 000000000000..417b5ee1abda --- /dev/null +++ b/external/gpl3/gdb/dist/include/som/reloc.h @@ -0,0 +1,79 @@ +/* SOM relocation definitions for BFD. + Copyright 2010 Free Software Foundation, Inc. + Contributed by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _SOM_RELOC_H +#define _SOM_RELOC_H + +#define R_NO_RELOCATION 0 +#define R_ZEROES 0x20 +#define R_UNINIT 0x22 +#define R_RELOCATION 0x24 +#define R_DATA_ONE_SYMBOL 0x25 +#define R_DATA_PLABEL 0x27 +#define R_SPACE_REF 0x29 +#define R_REPEATED_INIT 0x2a +#define R_PCREL_CALL 0x30 +#define R_SHORT_PCREL_MODE 0x3e +#define R_LONG_PCREL_MODE 0x3f +#define R_ABS_CALL 0x40 +#define R_DP_RELATIVE 0x50 +#define R_DATA_GPREL 0x72 +#define R_INDIRECT_CALL 0x76 +#define R_PLT_REL 0x77 +#define R_DLT_REL 0x78 +#define R_CODE_ONE_SYMBOL 0x80 +#define R_MILLI_REL 0xae +#define R_CODE_PLABEL 0xb0 +#define R_BREAKPOINT 0xb2 +#define R_ENTRY 0xb3 +#define R_ALT_ENTRY 0xb5 +#define R_EXIT 0xb6 +#define R_BEGIN_TRY 0xb7 +#define R_END_TRY 0xb8 +#define R_BEGIN_BRTAB 0xbb +#define R_END_BRTAB 0xbc +#define R_STATEMENT 0xbd +#define R_DATA_EXPR 0xc0 +#define R_CODE_EXPR 0xc1 +#define R_FSEL 0xc2 +#define R_LSEL 0xc3 +#define R_RSEL 0xc4 +#define R_N_MODE 0xc5 +#define R_S_MODE 0xc6 +#define R_D_MODE 0xc7 +#define R_R_MODE 0xc8 +#define R_DATA_OVERRIDE 0xc9 +#define R_TRANSLATED 0xce +#define R_AUX_UNWIND 0xcf +#define R_COMP1 0xd0 +#define R_COMP2 0xd1 +#define R_COMP3 0xd2 +#define R_PREV_FIXUP 0xd3 +#define R_SEC_STMT 0xd7 +#define R_N0SEL 0xd8 +#define R_N1SEL 0xd9 +#define R_LINETAB 0xda +#define R_LINETAB_ESC 0xdb +#define R_LTP_OVERRIDE 0xdc +#define R_COMMENT 0xdd +#define R_TP_OVERRIDE 0xde +#define R_RESERVED 0xdf + +#endif /* _SOM_RELOC_H */ diff --git a/external/gpl3/gdb/dist/include/sort.h b/external/gpl3/gdb/dist/include/sort.h new file mode 100644 index 000000000000..582af81623b8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/sort.h @@ -0,0 +1,48 @@ +/* Sorting algorithms. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + Contributed by Mark Mitchell . + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef SORT_H +#define SORT_H + +#include /* For size_t */ +#ifdef __STDC__ +#include +#endif /* __STDC__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +/* Sort an array of pointers. */ + +extern void sort_pointers (size_t, void **, void **); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SORT_H */ + + + + diff --git a/external/gpl3/gdb/dist/include/splay-tree.h b/external/gpl3/gdb/dist/include/splay-tree.h new file mode 100644 index 000000000000..480b2c43e7d4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/splay-tree.h @@ -0,0 +1,168 @@ +/* A splay-tree datatype. + Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* For an easily readable description of splay-trees, see: + + Lewis, Harry R. and Denenberg, Larry. Data Structures and Their + Algorithms. Harper-Collins, Inc. 1991. + + The major feature of splay trees is that all basic tree operations + are amortized O(log n) time for a tree with n nodes. */ + +#ifndef _SPLAY_TREE_H +#define _SPLAY_TREE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ansidecl.h" + +#ifndef _WIN64 + typedef unsigned long int libi_uhostptr_t; + typedef long int libi_shostptr_t; +#else +#ifdef __GNUC__ + __extension__ +#endif + typedef unsigned long long libi_uhostptr_t; +#ifdef __GNUC__ + __extension__ +#endif + typedef long long libi_shostptr_t; +#endif + +#ifndef GTY +#define GTY(X) +#endif + +/* Use typedefs for the key and data types to facilitate changing + these types, if necessary. These types should be sufficiently wide + that any pointer or scalar can be cast to these types, and then + cast back, without loss of precision. */ +typedef libi_uhostptr_t splay_tree_key; +typedef libi_uhostptr_t splay_tree_value; + +/* Forward declaration for a node in the tree. */ +typedef struct splay_tree_node_s *splay_tree_node; + +/* The type of a function which compares two splay-tree keys. The + function should return values as for qsort. */ +typedef int (*splay_tree_compare_fn) (splay_tree_key, splay_tree_key); + +/* The type of a function used to deallocate any resources associated + with the key. */ +typedef void (*splay_tree_delete_key_fn) (splay_tree_key); + +/* The type of a function used to deallocate any resources associated + with the value. */ +typedef void (*splay_tree_delete_value_fn) (splay_tree_value); + +/* The type of a function used to iterate over the tree. */ +typedef int (*splay_tree_foreach_fn) (splay_tree_node, void*); + +/* The type of a function used to allocate memory for tree root and + node structures. The first argument is the number of bytes needed; + the second is a data pointer the splay tree functions pass through + to the allocator. This function must never return zero. */ +typedef void *(*splay_tree_allocate_fn) (int, void *); + +/* The type of a function used to free memory allocated using the + corresponding splay_tree_allocate_fn. The first argument is the + memory to be freed; the latter is a data pointer the splay tree + functions pass through to the freer. */ +typedef void (*splay_tree_deallocate_fn) (void *, void *); + +/* The nodes in the splay tree. */ +struct GTY(()) splay_tree_node_s { + /* The key. */ + splay_tree_key GTY ((use_param1)) key; + + /* The value. */ + splay_tree_value GTY ((use_param2)) value; + + /* The left and right children, respectively. */ + splay_tree_node GTY ((use_params)) left; + splay_tree_node GTY ((use_params)) right; +}; + +/* The splay tree itself. */ +struct GTY(()) splay_tree_s { + /* The root of the tree. */ + splay_tree_node GTY ((use_params)) root; + + /* The comparision function. */ + splay_tree_compare_fn comp; + + /* The deallocate-key function. NULL if no cleanup is necessary. */ + splay_tree_delete_key_fn delete_key; + + /* The deallocate-value function. NULL if no cleanup is necessary. */ + splay_tree_delete_value_fn delete_value; + + /* Node allocate function. Takes allocate_data as a parameter. */ + splay_tree_allocate_fn allocate; + + /* Free function for nodes and trees. Takes allocate_data as a parameter. */ + splay_tree_deallocate_fn deallocate; + + /* Parameter for allocate/free functions. */ + void * GTY((skip)) allocate_data; +}; + +typedef struct splay_tree_s *splay_tree; + +extern splay_tree splay_tree_new (splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn); +extern splay_tree splay_tree_new_with_allocator (splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn, + splay_tree_allocate_fn, + splay_tree_deallocate_fn, + void *); +extern splay_tree splay_tree_new_typed_alloc (splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn, + splay_tree_allocate_fn, + splay_tree_allocate_fn, + splay_tree_deallocate_fn, + void *); +extern void splay_tree_delete (splay_tree); +extern splay_tree_node splay_tree_insert (splay_tree, + splay_tree_key, + splay_tree_value); +extern void splay_tree_remove (splay_tree, splay_tree_key); +extern splay_tree_node splay_tree_lookup (splay_tree, splay_tree_key); +extern splay_tree_node splay_tree_predecessor (splay_tree, splay_tree_key); +extern splay_tree_node splay_tree_successor (splay_tree, splay_tree_key); +extern splay_tree_node splay_tree_max (splay_tree); +extern splay_tree_node splay_tree_min (splay_tree); +extern int splay_tree_foreach (splay_tree, splay_tree_foreach_fn, void*); +extern int splay_tree_compare_ints (splay_tree_key, splay_tree_key); +extern int splay_tree_compare_pointers (splay_tree_key, splay_tree_key); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _SPLAY_TREE_H */ diff --git a/external/gpl3/gdb/dist/include/symcat.h b/external/gpl3/gdb/dist/include/symcat.h new file mode 100644 index 000000000000..b46128796be4 --- /dev/null +++ b/external/gpl3/gdb/dist/include/symcat.h @@ -0,0 +1,55 @@ +/* Symbol concatenation utilities. + + Copyright (C) 1998, 2000, 2010 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef SYM_CAT_H +#define SYM_CAT_H + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CONCAT2(a,b) a##b +#define CONCAT3(a,b,c) a##b##c +#define CONCAT4(a,b,c,d) a##b##c##d +#define CONCAT5(a,b,c,d,e) a##b##c##d##e +#define CONCAT6(a,b,c,d,e,f) a##b##c##d##e##f +#define STRINGX(s) #s +#else +/* Note one should never pass extra whitespace to the CONCATn macros, + e.g. CONCAT2(foo, bar) because traditonal C will keep the space between + the two labels instead of concatenating them. Instead, make sure to + write CONCAT2(foo,bar). */ +#define CONCAT2(a,b) a/**/b +#define CONCAT3(a,b,c) a/**/b/**/c +#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d +#define CONCAT5(a,b,c,d,e) a/**/b/**/c/**/d/**/e +#define CONCAT6(a,b,c,d,e,f) a/**/b/**/c/**/d/**/e/**/f +#define STRINGX(s) "s" +#endif + +#define XCONCAT2(a,b) CONCAT2(a,b) +#define XCONCAT3(a,b,c) CONCAT3(a,b,c) +#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d) +#define XCONCAT5(a,b,c,d,e) CONCAT5(a,b,c,d,e) +#define XCONCAT6(a,b,c,d,e,f) CONCAT6(a,b,c,d,e,f) + +/* Note the layer of indirection here is typically used to allow + stringification of the expansion of macros. I.e. "#define foo + bar", "XSTRING(foo)", to yield "bar". Be aware that this only + works for __STDC__, not for traditional C which will still resolve + to "foo". */ +#define XSTRING(s) STRINGX(s) + +#endif /* SYM_CAT_H */ diff --git a/external/gpl3/gdb/dist/include/vms/ChangeLog b/external/gpl3/gdb/dist/include/vms/ChangeLog new file mode 100644 index 000000000000..788d8d80c556 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/ChangeLog @@ -0,0 +1,70 @@ +2010-05-27 Tristan Gingold + + * lbr.h: Improve comments. + +2010-05-17 Tristan Gingold + + * eidc.h: New file. + * esgps.h: New file. + +2010-05-03 Tristan Gingold + + * dmt.h: Improve comments. + +2010-04-30 Tristan Gingold + + * lbr.h (struct vms_kbn): New structure. + +2010-04-30 Tristan Gingold + + * lbr.h (LBR__C_TYP_ISHSTB): Added. + (LHD_SANEID4): Renamed to ... + (LHD_SANEID6): ... this. + (LBR_MAJORID, LBR_ELFMAJORID): New macros. + (struct vms_rfa): New structure. + (struct vms_idxdef): Renamed to ... + (struct vms_idx): ... this. + (struct vms_idxdef2): Renamed to ... + (struct vms_elfidx): ... this. + (ELFIDX__WEAK, ELFIDX__GROUP, ELFIDX__LISTRFA, ELFIDX__SYMESC): New + macros. + (struct vms_lhs, struct vms_lns): New structures. + (struct vms_mhd): Add missing fields. + (MHD__C_MHDLEN): New macro. + +2010-03-31 Tristan Gingold + + * dcx.h: New file. + * dsc.h: New file. + * esdfm.h: New file. + * esdfv.h: New file. + * internal.h: New file. + * lbr.h: New file. + * prt.h: New file. + * shl.h (struct vms_shl): Add comments. + * esrf.h (ESRF__B_NAMLNG): New macro. + * esdf.h (ESDF__B_NAMLNG): New macro. + * emh.h: Add macros for fields maximum value. + * eisd.h (EISD__M_PROTECT): Fix typo in comment. + Add macros for offsets, version, section type and match control. + Merge vms_eisd_ext into vms_eisd. + * eihvn.h (EIHVN__MULTI_PROCESSING_BIT, EIHVN__GALAXY_BIT): Added. + * eihs.h: Remove blank line. + * eihd.h (struct vms_eihd): Add comments, add image subtype names. + * eiha.h (struct vms_eiha): Add inishr and inishr_h fields. + * eiaf.h (struct vms_eiaf): Fix base_va size. + * egsy.h: Add comments. + * egsd.h: Remove blank line. + * egps.h: Add flag names. + * eeom.h (EEOM__M_WKTFR): Added. + * dst.h (DST__K_CXX): Added, and reident languages. + (DST__K_SRC_INCRLNUM_B): Added. + Indent and order pcline commands. + Add record begin/end, enumerations, type specification, value + specification, label, discontinue range definitions. + +2010-02-17 Tristan Gingold + + * dmt.h, dst.h, eeom.h, egps.h, egsd.h, egst.h, egsy.h: New Files. + * eiaf.h, eicp.h, eiha.h, eihd.h, eihi.h, eihs.h, eihvn.h: Ditto. + * eisd.h, emh.h, eobjrec.h, esdf.h, esrf.h, etir.h, shl.h: Ditto. diff --git a/external/gpl3/gdb/dist/include/vms/dcx.h b/external/gpl3/gdb/dist/include/vms/dcx.h new file mode 100644 index 000000000000..b6f373ab5d3d --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/dcx.h @@ -0,0 +1,50 @@ +/* Alpha VMS external format for DeCompression. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_DCX_H +#define _VMS_DCX_H + +struct vms_dcxmap +{ + unsigned char size[4]; + unsigned char version[2]; + + unsigned char pad[2]; + unsigned char sanity[4]; + unsigned char flags[4]; + unsigned char nsubs[2]; + unsigned char sub0[2]; +}; + +struct vms_dcxsbm +{ + unsigned char size[2]; + unsigned char min_char; + unsigned char max_char; + unsigned char escape; + unsigned char flags_bits; + unsigned char flags[2]; + unsigned char nodes[2]; + unsigned char next[2]; +}; + +#endif /* _VMS_DCX_H */ diff --git a/external/gpl3/gdb/dist/include/vms/dmt.h b/external/gpl3/gdb/dist/include/vms/dmt.h new file mode 100644 index 000000000000..f2aad6e99be5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/dmt.h @@ -0,0 +1,48 @@ +/* Alpha VMS external format of Debug Module Table. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_DMT_H +#define _VMS_DMT_H + +struct vms_dmt_header +{ + /* Offset in the DST of the module. */ + unsigned char modbeg[4]; + + /* Size of the DST chunk for this module. */ + unsigned char size[4]; + + /* Number of psect for this module. */ + unsigned char psect_count[2]; + + unsigned char mbz[2]; +}; + +struct vms_dmt_psect +{ + /* Address of the psect. */ + unsigned char start[4]; + + /* Length of the psect. */ + unsigned char length[4]; +}; +#endif /* _VMS_DMT_H */ diff --git a/external/gpl3/gdb/dist/include/vms/dsc.h b/external/gpl3/gdb/dist/include/vms/dsc.h new file mode 100644 index 000000000000..5a1b0e238a85 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/dsc.h @@ -0,0 +1,129 @@ +/* Alpha VMS external format of Descriptors. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_DSC_H +#define _VMS_DSC_H + +/* Descriptors. */ +#define DSC__K_DTYPE_Z 0 /* Unspecified. */ +#define DSC__K_DTYPE_V 1 /* Bit. */ +#define DSC__K_DTYPE_BU 2 /* Byte logical. */ +#define DSC__K_DTYPE_WU 3 /* Word logical. */ +#define DSC__K_DTYPE_LU 4 /* Longword logical. */ +#define DSC__K_DTYPE_QU 5 /* Quadword logical. */ +#define DSC__K_DTYPE_B 6 /* Byte integer. */ +#define DSC__K_DTYPE_W 7 /* Word integer. */ +#define DSC__K_DTYPE_L 8 /* Longword integer. */ +#define DSC__K_DTYPE_Q 9 /* Quadword integer. */ +#define DSC__K_DTYPE_F 10 /* Single-precision floating. */ +#define DSC__K_DTYPE_D 11 /* Double-precision floating. */ +#define DSC__K_DTYPE_FC 12 /* Complex. */ +#define DSC__K_DTYPE_DC 13 /* Double-precision Complex. */ +#define DSC__K_DTYPE_T 14 /* ASCII text string. */ +#define DSC__K_DTYPE_NU 15 /* Numeric string, unsigned. */ +#define DSC__K_DTYPE_NL 16 /* Numeric string, left separate sign. */ +#define DSC__K_DTYPE_NLO 17 /* Numeric string, left overpunched sign. */ +#define DSC__K_DTYPE_NR 18 /* Numeric string, right separate sign. */ +#define DSC__K_DTYPE_NRO 19 /* Numeric string, right overpunched sign. */ +#define DSC__K_DTYPE_NZ 20 /* Numeric string, zoned sign. */ +#define DSC__K_DTYPE_P 21 /* Packed decimal string. */ +#define DSC__K_DTYPE_ZI 22 /* Sequence of instructions. */ +#define DSC__K_DTYPE_ZEM 23 /* Procedure entry mask. */ +#define DSC__K_DTYPE_DSC 24 /* Descriptor, used for arrays of dyn strings. */ +#define DSC__K_DTYPE_OU 25 /* Octaword logical. */ +#define DSC__K_DTYPE_O 26 /* Octaword integer. */ +#define DSC__K_DTYPE_G 27 /* Double precision G floating, 64 bit. */ +#define DSC__K_DTYPE_H 28 /* Quadruple precision floating, 128 bit. */ +#define DSC__K_DTYPE_GC 29 /* Double precision complex, G floating. */ +#define DSC__K_DTYPE_HC 30 /* Quadruple precision complex, H floating. */ +#define DSC__K_DTYPE_CIT 31 /* COBOL intermediate temporary. */ +#define DSC__K_DTYPE_BPV 32 /* Bound Procedure Value. */ +#define DSC__K_DTYPE_BLV 33 /* Bound Label Value. */ +#define DSC__K_DTYPE_VU 34 /* Bit Unaligned. */ +#define DSC__K_DTYPE_ADT 35 /* Absolute Date-Time. */ +#define DSC__K_DTYPE_VT 37 /* Varying Text. */ +#define DSC__K_DTYPE_T2 38 /* 16-bit char. */ +#define DSC__K_DTYPE_VT2 39 /* 16-bit varying char. */ + +#define DSC__K_CLASS_S 1 /* Fixed-length scalar/string. */ +#define DSC__K_CLASS_D 2 /* Dynamic string. */ +#define DSC__K_CLASS_V 3 /* Reserved. */ +#define DSC__K_CLASS_A 4 /* Contiguous array. */ +#define DSC__K_CLASS_P 5 /* Procedure argument descriptor. */ +#define DSC__K_CLASS_PI 6 /* Procedure incarnation descriptor. */ +#define DSC__K_CLASS_J 7 /* Reserved. */ +#define DSC__K_CLASS_JI 8 /* Obsolete. */ +#define DSC__K_CLASS_SD 9 /* Decimal (scalar) string. */ +#define DSC__K_CLASS_NCA 10 /* Non-contiguous array. */ +#define DSC__K_CLASS_VS 11 /* Varying string. */ +#define DSC__K_CLASS_VSA 12 /* Varying string array. */ +#define DSC__K_CLASS_UBS 13 /* Unaligned bit string. */ +#define DSC__K_CLASS_UBA 14 /* Unaligned bit array. */ +#define DSC__K_CLASS_SB 15 /* String with bounds. */ +#define DSC__K_CLASS_UBSB 16 /* Unaligned bit string with bounds. */ + +/* Common part. */ + +struct vms_dsc +{ + unsigned char length[2]; + unsigned char dtype; + unsigned char bclass; + unsigned char pointer[4]; +}; + +struct vms_dsc64 +{ + unsigned char mbo[2]; + unsigned char dtype; + unsigned char bclass; + unsigned char mbmo[4]; + unsigned char length[8]; + unsigned char pointer[8]; +}; + +struct vms_dsc_nca +{ + unsigned char length[2]; + unsigned char dtype; + unsigned char bclass; + unsigned char pointer[4]; + + unsigned char scale; + unsigned char digits; + unsigned char aflags; + unsigned char dimct; + + unsigned char arsize[4]; + unsigned char a0[4]; +}; + +struct vms_dsc_ubs +{ + unsigned char length[2]; + unsigned char dtype; + unsigned char bclass; + unsigned char base[4]; + unsigned char pos[4]; +}; + +#endif /* _VMS_DSC_H */ diff --git a/external/gpl3/gdb/dist/include/vms/dst.h b/external/gpl3/gdb/dist/include/vms/dst.h new file mode 100644 index 000000000000..231d39708705 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/dst.h @@ -0,0 +1,274 @@ +/* Alpha VMS external format of Debug Symbol Table. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_DST_H +#define _VMS_DST_H + +/* Also available in vms freeware v5.0 debug/alpha_dstrecrds.sdl. */ + +struct vms_dst_header +{ + /* Length. */ + unsigned char length[2]; + + /* Type. */ + unsigned char type[2]; +}; + +/* Beginning of module. */ +#define DST__K_MODBEG 188 + +/* Some well known languages. */ +#define DST__K_MACRO 0 +#define DST__K_BLISS 2 +#define DST__K_C 7 +#define DST__K_ADA 9 +#define DST__K_CXX 15 + +struct vms_dst_modbeg +{ + unsigned char flags; + unsigned char unused; + unsigned char language[4]; + unsigned char major[2]; + unsigned char minor[2]; + /* Module name ASCIC. */ + /* Ident name ASCIC. */ +}; + +/* Routine begin. */ +#define DST__K_RTNBEG 190 + +struct vms_dst_rtnbeg +{ + unsigned char flags; + + /* Address of the code. */ + unsigned char address[4]; + + /* Procedure descriptor address. */ + unsigned char pd_address[4]; + + /* Name: ASCIC */ +}; + +/* Line number. */ +#define DST__K_LINE_NUM 185 + +struct vms_dst_pcline +{ + unsigned char pcline_command; + unsigned char field[4]; +}; + +#define DST__K_DELTA_PC_W 1 +#define DST__K_INCR_LINUM 2 +#define DST__K_INCR_LINUM_W 3 +#define DST__K_SET_LINUM_INCR 4 +#define DST__K_SET_LINUM_INCR_W 5 +#define DST__K_RESET_LINUM_INCR 6 +#define DST__K_BEG_STMT_MODE 7 +#define DST__K_END_STMT_MODE 8 +#define DST__K_SET_LINUM 9 +#define DST__K_SET_PC 10 +#define DST__K_SET_PC_W 11 +#define DST__K_SET_PC_L 12 +#define DST__K_SET_STMTNUM 13 +#define DST__K_TERM 14 +#define DST__K_TERM_W 15 +#define DST__K_SET_ABS_PC 16 +#define DST__K_DELTA_PC_L 17 +#define DST__K_INCR_LINUM_L 18 +#define DST__K_SET_LINUM_B 19 +#define DST__K_SET_LINUM_L 20 +#define DST__K_TERM_L 21 + +/* Routine end. */ +#define DST__K_RTNEND 191 + +struct vms_dst_rtnend +{ + unsigned char unused; + unsigned char size[4]; +}; + +/* Prologue. */ +#define DST__K_PROLOG 162 + +struct vms_dst_prolog +{ + unsigned char bkpt_addr[4]; +}; + +/* Epilog. */ +#define DST__K_EPILOG 127 + +struct vms_dst_epilog +{ + unsigned char flags; + unsigned char count[4]; +}; + +/* Module end. */ +#define DST__K_MODEND 189 + +/* Block begin. */ +#define DST__K_BLKBEG 176 + +struct vms_dst_blkbeg +{ + unsigned char unused; + unsigned char address[4]; + /* Name ASCIC. */ +}; + +/* Block end. */ +#define DST__K_BLKEND 177 + +struct vms_dst_blkend +{ + unsigned char unused; + unsigned char size[4]; +}; + +/* Source correlation. */ +#define DST__K_SOURCE 155 + +#define DST__K_SRC_DECLFILE 1 +#define DST__K_SRC_SETFILE 2 +#define DST__K_SRC_SETREC_L 3 +#define DST__K_SRC_SETREC_W 4 +#define DST__K_SRC_SETLNUM_L 5 +#define DST__K_SRC_SETLNUM_W 6 +#define DST__K_SRC_INCRLNUM_B 7 +#define DST__K_SRC_DEFLINES_W 10 +#define DST__K_SRC_DEFLINES_B 11 +#define DST__K_SRC_FORMFEED 16 + +struct vms_dst_src_decl_src +{ + unsigned char length; + unsigned char flags; + unsigned char fileid[2]; + unsigned char rms_cdt[8]; + unsigned char rms_ebk[4]; + unsigned char rms_ffb[2]; + unsigned char rms_rfo; + /* Filename ASCIC. */ +}; + +/* Record begin. */ +#define DST__K_RECBEG 171 + +struct vms_dst_recbeg +{ + unsigned char vflags; + unsigned char value[4]; + /* Filename ASCIC. */ +}; + +/* Record end. */ +#define DST__K_RECEND 172 + +/* Enumeration begin. */ +#define DST__K_ENUMBEG 165 + +/* Enumeration element. */ +#define DST__K_ENUMELT 164 + +/* Enumeration end. */ +#define DST__K_ENUMEND 166 + +/* Separate type specification. */ +#define DST__K_SEPTYP 163 + +/* Type specification. */ +#define DST__K_TYPSPEC 175 + +#define DST__K_TS_ATOM 1 /* Atomic. */ +#define DST__K_TS_DSC 2 /* VMS Standard descriptor. */ +#define DST__K_TS_IND 3 /* Indirect. */ +#define DST__K_TS_TPTR 4 /* Typed pointer. */ +#define DST__K_TS_PTR 5 /* Pointer. */ +#define DST__K_TS_PIC 6 /* Pictured. */ +#define DST__K_TS_ARRAY 7 +#define DST__K_TS_SET 8 +#define DST__K_TS_SUBRANGE 9 /* Subrange. */ +#define DST__K_TS_ADA_DSC 10 /* Ada descriptor. */ +#define DST__K_TS_FILE 11 +#define DST__K_TS_AREA 12 /* Area (PL/I). */ +#define DST__K_TS_OFFSET 13 /* Offset (PL/I). */ +#define DST__K_TS_NOV_LENG 14 /* Novel Length. */ +#define DST__K_TS_IND_TSPEC 15 /* Internal to debugger. */ +#define DST__K_TS_SELF_REL_LABEL 16 /* Self-relative label (PL/I). */ +#define DST__K_TS_RFA 17 /* (Basic). */ +#define DST__K_TS_TASK 18 /* (Ada). */ +#define DST__K_TS_ADA_ARRAY 19 +#define DST__K_TS_XMOD_IND 20 /* Cross-module indirect type spec. */ +#define DST__K_TS_CONSTRAINED 21 /* (Ada). */ +#define DST__K_TS_MAYBE_CONSTR 22 /* Might-be-constrained (Ada). */ +#define DST__K_TS_DYN_LOV_LENG 23 +#define DST__K_TS_TPTR_D 24 /* Typed pointer to descriptor. */ +#define DST__K_TS_SCAN_TREE 25 +#define DST__K_TS_SCAN_TREEPTR 26 +#define DST__K_TS_INCOMPLETE 27 +#define DST__K_TS_BLISS_BLOCK 28 +#define DST__K_TS_TPTR_64 29 +#define DST__K_TS_PTR_64 30 +#define DST__K_TS_REF 31 /* C++ referenced type. */ +#define DST__K_TS_REF_64 32 + +/* Value Specification. */ +#define DST__K_VFLAGS_NOVAL 128 /* No value. */ +#define DST__K_VFLAGS_NOTACTIVE 248 /* Not active at current PC. */ +#define DST__K_VFLAGS_UNALLOC 249 /* Not allocated. */ +#define DST__K_VFLAGS_DSC 250 /* Descriptor format. */ +#define DST__K_VFLAGS_TVS 251 /* Trailing value spec. */ +#define DST__K_VS_FOLLOWS 253 /* Value specification follow. */ +#define DST__K_VFLAGS_BITOFFS 255 /* Value is a bit offset. */ + +/* Vflags fields. */ +#define DST__K_VALKIND_MASK 0x03 +#define DST__K_INDIR 0x04 +#define DST__K_DISP 0x08 +#define DST__K_REGNUM_MASK 0xf0 +#define DST__K_REGNUM_SHIFT 4 + +#define DST__K_VALKIND_LITERAL 0 +#define DST__K_VALKIND_ADDR 1 +#define DST__K_VALKIND_DESC 2 +#define DST__K_VALKIND_REG 3 + +/* Label. */ +#define DST__K_LABEL 187 + +struct vms_dst_label +{ + unsigned char unused; + + unsigned char value[4]; + unsigned char name[1]; +}; + +/* Discontiguous range. */ +#define DST__K_DIS_RANGE 118 +#endif /* _VMS_DST_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eeom.h b/external/gpl3/gdb/dist/include/vms/eeom.h new file mode 100644 index 000000000000..807e44855e4a --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eeom.h @@ -0,0 +1,62 @@ +/* Alpha VMS external format of Extended End Of Module. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EEOM_H +#define _VMS_EEOM_H + +/* Completion flags. */ +#define EEOM__C_SUCCESS 0 +#define EEOM__C_WARNING 1 +#define EEOM__C_ERROR 2 +#define EEOM__C_ABORT 3 + +struct vms_eeom +{ + /* Record type. */ + unsigned char rectyp[2]; + + /* Record size. */ + unsigned char size[2]; + + /* Number of conditional linkage pairs. */ + unsigned char total_lps[4]; + + /* Completion code. */ + unsigned char comcod[2]; + + + /* Transfer address flags. */ + unsigned char tfrflg; + + /* Pad for alignment. */ + unsigned char temp; + + /* Psect of transfer address. */ + unsigned char psindx[4]; + + /* Transfer address. */ + unsigned char tfradr[8]; +}; + +#define EEOM__M_WKTFR (1 << 0) /* Transfer address is weak. */ + +#endif /* _VMS_EEOM_H */ diff --git a/external/gpl3/gdb/dist/include/vms/egps.h b/external/gpl3/gdb/dist/include/vms/egps.h new file mode 100644 index 000000000000..e92df810b04f --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/egps.h @@ -0,0 +1,64 @@ +/* Alpha VMS external format of Extended Program Section Definition. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EGPS_H +#define _VMS_EGPS_H + +struct vms_egps +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char gsdsiz[2]; + + /* Psect alignment. */ + unsigned char align; + + /* Pad for alignment. */ + unsigned char temp; + + unsigned char flags[2]; + + /* Length of this contribution. */ + unsigned char alloc[4]; + + /* Name. */ + unsigned char namlng; + unsigned char name[31]; +}; + +#define EGPS__V_PIC (1 << 0) /* Not meaningful. */ +#define EGPS__V_LIB (1 << 1) /* Defined in a shareable image. */ +#define EGPS__V_OVR (1 << 2) /* Overlaid contribution. */ +#define EGPS__V_REL (1 << 3) /* Relocatable. */ +#define EGPS__V_GBL (1 << 4) /* Global. */ +#define EGPS__V_SHR (1 << 5) /* Shareable. */ +#define EGPS__V_EXE (1 << 6) /* Executable. */ +#define EGPS__V_RD (1 << 7) /* Readable. */ +#define EGPS__V_WRT (1 << 8) /* Writable. */ +#define EGPS__V_VEC (1 << 9) /* Change mode dispatch or message vectors. */ +#define EGPS__V_NOMOD (1 << 10) /* Demand-zero. */ +#define EGPS__V_COM (1 << 11) /* Conditional storage. */ +#define EGPS__V_ALLOC_64BIT (1 << 12) /* Allocated in 64-bit space. */ + +#endif /* _VMS_EGPS_H */ diff --git a/external/gpl3/gdb/dist/include/vms/egsd.h b/external/gpl3/gdb/dist/include/vms/egsd.h new file mode 100644 index 000000000000..f9be3981aa8a --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/egsd.h @@ -0,0 +1,60 @@ +/* Alpha VMS external format of Extended Global Symbol Directory. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EGSD_H +#define _VMS_EGSD_H + +#define EGSD__K_ENTRIES 2 /* Offset to first entry in record. */ +#define EGSD__C_ENTRIES 2 /* Offset to first entry in record. */ +#define EGSD__C_PSC 0 /* Psect definition. */ +#define EGSD__C_SYM 1 /* Symbol specification. */ +#define EGSD__C_IDC 2 /* Random entity check. */ +#define EGSD__C_SPSC 5 /* Shareable image psect definition. */ +#define EGSD__C_SYMV 6 /* Vectored (dual-valued) versions of SYM. */ +#define EGSD__C_SYMM 7 /* Masked versions of SYM. */ +#define EGSD__C_SYMG 8 /* EGST - gst version of SYM. */ +#define EGSD__C_MAXRECTYP 8 /* Maximum entry type defined. */ + +struct vms_egsd +{ + /* Record type. */ + unsigned char rectyp[2]; + + /* Record size. */ + unsigned char recsiz[2]; + + /* Padding for alignment. */ + unsigned char alignlw[4]; + + /* Followed by egsd entries. */ +}; + +struct vms_egsd_entry +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char gsdsiz[2]; +}; + +#endif /* _VMS_EGSD_H */ diff --git a/external/gpl3/gdb/dist/include/vms/egst.h b/external/gpl3/gdb/dist/include/vms/egst.h new file mode 100644 index 000000000000..d4244842e228 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/egst.h @@ -0,0 +1,39 @@ +/* Alpha VMS external format of Extended Global Symbol Definition. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EGST_H +#define _VMS_EGST_H + +struct vms_egst +{ + struct vms_egsy header; + + unsigned char value[8]; + unsigned char lp_1[8]; + unsigned char lp_2[8]; + + unsigned char psindx[4]; + unsigned char namlng; + unsigned char name[31]; +}; + +#endif /* _VMS_EGST_H */ diff --git a/external/gpl3/gdb/dist/include/vms/egsy.h b/external/gpl3/gdb/dist/include/vms/egsy.h new file mode 100644 index 000000000000..dd36ab218c6a --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/egsy.h @@ -0,0 +1,54 @@ +/* Alpha VMS external format of Extended Global Symbol. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EGSY_H +#define _VMS_EGSY_H + +#define EGSY__W_FLAGS 6 + +#define EGSY__V_WEAK 0x0001 /* Weak symbol definition. */ +#define EGSY__V_DEF 0x0002 /* Symbol definition. */ +#define EGSY__V_UNI 0x0004 /* Reserved. */ +#define EGSY__V_REL 0x0008 /* Relocatable (vs absolute). */ +#define EGSY__V_COMM 0x0010 /* Conditional symbol def. */ +#define EGSY__V_VECEP 0x0020 /* Reserved. */ +#define EGSY__V_NORM 0x0040 /* Normal procedure definition. */ +#define EGSY__V_QUAD_VAL 0x0080 /* Value exceed 32 bits. */ + +struct vms_egsy +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char gsdsiz[2]; + + /* Data type. */ + unsigned char datyp; + + /* Pad for alignment. */ + unsigned char temp; + + unsigned char flags[2]; +}; + +#endif /* _VMS_EGSY_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eiaf.h b/external/gpl3/gdb/dist/include/vms/eiaf.h new file mode 100644 index 000000000000..c3c39884c230 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eiaf.h @@ -0,0 +1,80 @@ +/* Alpha VMS external format of Extended Image Activator Fixup section. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIAF_H +#define _VMS_EIAF_H + +struct vms_eiaf +{ + /* Version. */ + unsigned char majorid[4]; + unsigned char minorid[4]; + + /* Link for image activator use. */ + unsigned char iaflink[8]; + + /* Link for sharable image fixups. */ + unsigned char fixuplnk[8]; + + /* Size of EIAF fixed part. */ + unsigned char size[4]; + + /* Flags. */ + unsigned char flags[4]; + + /* Offsets to quadword and longword relocation fixup data. */ + unsigned char qrelfixoff[4]; + unsigned char lrelfixoff[4]; + + /* Offsets to quardword and longword .address fixup data. */ + unsigned char qdotadroff[4]; + unsigned char ldotadroff[4]; + + /* Offset to code address fixup data. */ + unsigned char codeadroff[4]; + + /* Offset to linkage part fixup data. */ + unsigned char lpfixoff[4]; + + /* Offset to isect change protection data. */ + unsigned char chgprtoff[4]; + + /* Offset to shareable image list. */ + unsigned char shlstoff[4]; + + /* Number of shareable images. */ + unsigned char shrimgcnt[4]; + + /* Number of extra shareable images allowed. */ + unsigned char shlextra[4]; + + /* Permanent shareable image context. */ + unsigned char permctx[4]; + + /* Base address of the image itself. */ + unsigned char base_va[4]; + + /* Offset to linkage pair with procedure signature fixups. */ + unsigned char lppsbfixoff[4]; +}; + +#endif /* _VMS_EIAF_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eicp.h b/external/gpl3/gdb/dist/include/vms/eicp.h new file mode 100644 index 000000000000..9c769f7687ff --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eicp.h @@ -0,0 +1,38 @@ +/* Alpha VMS external format of Extended Image section Change Protection. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EICP_H +#define _VMS_EICP_H + +struct vms_eicp +{ + /* Start of section. */ + unsigned char baseva[8]; + + /* Size in bytes of the image section. */ + unsigned char size[4]; + + /* New protections. */ + unsigned char newprt[4]; +}; + +#endif /* _VMS_EICP_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eidc.h b/external/gpl3/gdb/dist/include/vms/eidc.h new file mode 100644 index 000000000000..987e8c24e0a2 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eidc.h @@ -0,0 +1,49 @@ +/* Alpha VMS external format of Ident Consistency check. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIDC_H +#define _VMS_EIDC_H + +struct vms_eidc +{ + /* Record type. */ + unsigned char rectyp[2]; + + /* Record size. */ + unsigned char recsiz[2]; + + unsigned char flags[4]; + + /* Entity name (ASCIC). */ + /* Object name (ASCIC). */ + /* Ident string (ASCIC or binary BINIDENT set). */ + unsigned char name[1]; +}; + +/* Fields of flags. */ +#define EIDC__V_BINIDENT (1 << 0) /* Ident is a longword. */ +#define EIDC__V_IDMATCH_SH 1 /* Ident match control. */ +#define EIDC__V_IDMATCH_MASK 3 +#define EIDC__V_ERRSEV_SH 3 /* Error severity. */ +#define EIDC__V_ERRSEV_MASK 7 + +#endif /* _VMS_EIDC_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eiha.h b/external/gpl3/gdb/dist/include/vms/eiha.h new file mode 100644 index 000000000000..5965ef97920c --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eiha.h @@ -0,0 +1,54 @@ +/* Alpha VMS external format of Extended Image Activation. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIHA_H +#define _VMS_EIHA_H + +struct vms_eiha +{ + /* Size of the struct. */ + unsigned char size[4]; + + unsigned char spare[4]; + + /* First transfer address. */ + unsigned char tfradr1[4]; + unsigned char tfradr1_h[4]; + + /* Second. */ + unsigned char tfradr2[4]; + unsigned char tfradr2_h[4]; + + /* Third. */ + unsigned char tfradr3[4]; + unsigned char tfradr3_h[4]; + + /* Fourth (must be 0). */ + unsigned char tfradr4[4]; + unsigned char tfradr4_h[4]; + + /* Shared image initialization (only if EIHD__V_INISHR is set). */ + unsigned char inishr[4]; + unsigned char inishr_h[4]; +}; + +#endif /* _VMS_EIHA_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eihd.h b/external/gpl3/gdb/dist/include/vms/eihd.h new file mode 100644 index 000000000000..fdb3a6ec7478 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eihd.h @@ -0,0 +1,145 @@ +/* Alpha VMS external format of Extended Image Header. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIHD_H +#define _VMS_EIHD_H + +/* Extended Image Header (eihd) structure. */ +struct vms_eihd +{ + /* Version of this EIHD. */ + unsigned char majorid[4]; + unsigned char minorid[4]; + + /* Size in bytes of the header. */ + unsigned char size[4]; + + /* Byte offset to ISD (Image Section Descriptors) list. */ + unsigned char isdoff[4]; + + /* Byte offset to activation data (off=16). */ + unsigned char activoff[4]; + + /* Byte offset to symbol table and debugging data. */ + unsigned char symdbgoff[4]; + + /* Byte offset to image ident. */ + unsigned char imgidoff[4]; + + /* Byte offset to patch data. */ + unsigned char patchoff[4]; + + /* RVA of fixup info (off=32). */ + unsigned char iafva[8]; + + /* RVA of symbol vector. */ + unsigned char symvva[8]; + + /* Byte offset to version number array (off=48). */ + unsigned char version_array_off[4]; + + /* Image type. */ + unsigned char imgtype[4]; + + /* Image subtype. */ + unsigned char subtype[4]; + + /* Size in bytes of image I/O section requested. */ + unsigned char imgiocnt[4]; + + /* Nbr of channels requested (off=64). */ + unsigned char iochancnt[4]; + + /* Requested privilege mask. */ + unsigned char privreqs[8]; + + /* Number of header diskblocks. */ + unsigned char hdrblkcnt[4]; + + /* Linker produced image flags. */ + unsigned char lnkflags[4]; + + /* GBL SEC ident value for linkable image. */ + unsigned char ident[4]; + + /* SYS$K_VERSION or 0 if not linked with exec. */ + unsigned char sysver[4]; + + /* Linker match control. */ + unsigned char matchctl; + unsigned char fill_1[3]; + + /* Size of the symbol vector in bytes. */ + unsigned char symvect_size[4]; + + /* Value of /BPAGE. */ + unsigned char virt_mem_block_size[4]; + + /* Byte offset to extended fixup data. */ + unsigned char ext_fixup_off[4]; + + /* Byte offset to no_optimize psect table. */ + unsigned char noopt_psect_off[4]; + + unsigned char fill_2[398]; + + /* CODE identifies image type to MOM. */ + unsigned char alias[2]; +}; + +#define EIHD__K_MAJORID 3 /* Major id constant */ +#define EIHD__K_MINORID 0 /* Minor id constant */ + +/* Image type. */ +#define EIHD__K_EXE 1 /* Executable image */ +#define EIHD__K_LIM 2 /* Linkable image. */ + +/* Image subtype. */ +#define EIHD__C_NATIVE 0 /* Alpha native image. */ +#define EIHD__C_CLI 1 /* Image is a CLI, run LOGINOUT. */ + +/* Linker image flags. */ +#define EIHD__M_LNKDEBUG 0x0001 /* Full debugging requested. */ +#define EIHD__M_LNKNOTFR 0x0002 /* No first transfer address. */ +#define EIHD__M_NOP0BUFS 0x0004 /* No RMS use of P0 for image I/O. */ +#define EIHD__M_PICIMG 0x0008 /* PIC image. */ +#define EIHD__M_P0IMAGE 0x0010 /* P0 only image. */ +#define EIHD__M_DBGDMT 0x0020 /* Image header has dmt fields. */ +#define EIHD__M_INISHR 0x0040 /* Transfer array contains LNISHR. */ +#define EIHD__M_XLATED 0x0080 /* Translated image. */ +#define EIHD__M_BIND_CODE_SEC 0x0100 /* EXE sect can be put into S0. */ +#define EIHD__M_BIND_DATA_SEC 0x0200 /* DATA sect can be put into S0. */ +#define EIHD__M_MKTHREADS 0x0400 /* Multiple kernel threads. */ +#define EIHD__M_UPCALLS 0x0800 /* Upcalls enabled. */ +#define EIHD__M_OMV_READY 0x1000 /* Can be processed by OMV. */ +#define EIHD__M_EXT_BIND_SECT 0x2000 /* May be moved, using ext fixups. */ + +/* Offsets of some fields. */ +#define EIHD__L_SIZE 8 +#define EIHD__L_ISDOFF 12 +#define EIHD__L_SYMDBGOFF 20 +#define EIHD__Q_SYMVVA 40 +#define EIHD__L_IMGTYPE 52 + +#define EIHD__C_LENGTH 104 + +#endif /* _VMS_EIHD_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eihi.h b/external/gpl3/gdb/dist/include/vms/eihi.h new file mode 100644 index 000000000000..97d3d895883e --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eihi.h @@ -0,0 +1,50 @@ +/* Alpha VMS external format of Extended Image Identification. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIHI_H +#define _VMS_EIHI_H + +#define EIHI__K_MAJORID 1 +#define EIHI__K_MINORID 2 + +struct vms_eihi +{ + unsigned char majorid[4]; + unsigned char minorid[4]; + + /* Time when this image was linked. */ + unsigned char linktime[8]; + + /* Image name. */ + unsigned char imgnam[40]; + + /* Image ident. */ + unsigned char imgid[16]; + + /* Linker ident. */ + unsigned char linkid[16]; + + /* Image build ident. */ + unsigned char imgbid[16]; +}; + +#endif /* _VMS_EIHI_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eihs.h b/external/gpl3/gdb/dist/include/vms/eihs.h new file mode 100644 index 000000000000..cf048b13d34d --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eihs.h @@ -0,0 +1,62 @@ +/* Alpha VMS external format of Extended Image Symbols and debug table. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIHS_H +#define _VMS_EIHS_H + +#define EIHS__K_MAJORID 1 +#define EIHS__K_MINORID 1 + +struct vms_eihs +{ + unsigned char majorid[4]; + unsigned char minorid[4]; + + /* Debug symbol table virtual block number (vbn). */ + unsigned char dstvbn[4]; + + /* Debug symbol table size. */ + unsigned char dstsize[4]; + + /* Global symbol table vbn. */ + unsigned char gstvbn[4]; + + /* Global symtol table size. */ + unsigned char gstsize[4]; + + /* Debug module table vbn. */ + unsigned char dmtvbn[4]; + + /* Debug module table size. */ + unsigned char dmtsize[4]; +}; + +/* Various offsets. */ + +#define EIHS__L_DSTVBN 8 +#define EIHS__L_DSTSIZE 12 +#define EIHS__L_GSTVBN 16 +#define EIHS__L_GSTSIZE 20 +#define EIHS__L_DMTVBN 24 +#define EIHS__L_DMTBYTES 28 + +#endif /* _VMS_EIHS_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eihvn.h b/external/gpl3/gdb/dist/include/vms/eihvn.h new file mode 100644 index 000000000000..07f9eeed28c7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eihvn.h @@ -0,0 +1,58 @@ +/* Alpha VMS external format of Extended Image Header Version. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EIHVN_H +#define _VMS_EIHVN_H + +struct vms_eihvn +{ + unsigned char subsystem_mask[4]; +}; + +struct vms_eihvn_subversion +{ + unsigned char minor[2]; + unsigned char major[2]; +}; + +#define EIHVN__BASE_IMAGE_BIT 0 +#define EIHVN__MEMORY_MANAGEMENT_BIT 1 +#define EIHVN__IO_BIT 2 +#define EIHVN__FILES_VOLUMES_BIT 3 +#define EIHVN__PROCESS_SCHED_BIT 4 +#define EIHVN__SYSGEN_BIT 5 +#define EIHVN__CLUSTERS_LOCKMGR_BIT 6 +#define EIHVN__LOGICAL_NAMES_BIT 7 +#define EIHVN__SECURITY_BIT 8 +#define EIHVN__IMAGE_ACTIVATOR_BIT 9 +#define EIHVN__NETWORKS_BIT 10 +#define EIHVN__COUNTERS_BIT 11 +#define EIHVN__STABLE_BIT 12 +#define EIHVN__MISC_BIT 13 +#define EIHVN__CPU_BIT 14 +#define EIHVN__VOLATILE_BIT 15 +#define EIHVN__SHELL_BIT 16 +#define EIHVN__POSIX_BIT 17 +#define EIHVN__MULTI_PROCESSING_BIT 18 +#define EIHVN__GALAXY_BIT 19 + +#endif /* _VMS_EIHVN_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eisd.h b/external/gpl3/gdb/dist/include/vms/eisd.h new file mode 100644 index 000000000000..7579e72b8296 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eisd.h @@ -0,0 +1,118 @@ +/* Alpha VMS external format of Extended Image Section Descriptor. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EISD_H +#define _VMS_EISD_H + +/* Flags. */ +#define EISD__M_GBL 0x0001 /* Global. */ +#define EISD__M_CRF 0x0002 /* Copy on reference. */ +#define EISD__M_DZRO 0x0004 /* Demand zero page. */ +#define EISD__M_WRT 0x0008 /* Writable. */ +#define EISD__M_INITALCODE 0x0010 /* Part of initialization code. */ +#define EISD__M_BASED 0x0020 /* Isect is based. */ +#define EISD__M_FIXUPVEC 0x0040 /* Isect is fixup section. */ +#define EISD__M_RESIDENT 0x0080 /* Isect is memory resident. */ +#define EISD__M_VECTOR 0x0100 /* Vector contained in isect. */ +#define EISD__M_PROTECT 0x0200 /* Isect is protected. */ +#define EISD__M_LASTCLU 0x0400 /* Last cluster. */ +#define EISD__M_EXE 0x0800 /* Code isect. */ +#define EISD__M_NONSHRADR 0x1000 /* Contains non-shareable data. */ +#define EISD__M_QUAD_LENGTH 0x2000 /* Quad length field valid. */ +#define EISD__M_ALLOC_64BIT 0x4000 /* Allocate 64-bit space. */ + +#define EISD__K_LEN 36 +#define EISD__K_LENEND 12 /* For end marker or next block. */ +#define EISD__K_MAXLENGLBL 84 + +#define EISD__K_GBLNAMLEN 44 /* Size of the field. */ + +struct vms_eisd +{ + unsigned char majorid[4]; + unsigned char minorid[4]; + + /* Size (in bytes) of this eisd. */ + unsigned char eisdsize[4]; + + /* Size (in bytes) of the section. */ + unsigned char secsize[4]; + + /* Virtual address of the section. */ + unsigned char virt_addr[8]; + + /* Flags. */ + unsigned char flags[4]; + + /* Base virtual block number. */ + unsigned char vbn[4]; + + /* Page fault cluster. */ + unsigned char pfc; + + /* Linker match control. */ + unsigned char matchctl; + + /* Section type. */ + unsigned char type; + + unsigned char fill_1; + + /* End of structure for normal records. */ + + /* Ident for global section. */ + unsigned char ident[4]; + + /* Global name ascic. First 8 bytes are quad length field. */ + unsigned char gblnam[EISD__K_GBLNAMLEN]; +}; + +/* Versions. */ +#define EISD__K_MAJORID 1 +#define EISD__K_MINORID 1 + +/* Match control. */ +#define EISD__K_MATALL 0 /* Match always. */ +#define EISD__K_MATEQU 1 /* Match if equal. */ +#define EISD__K_MATLEQ 2 /* Match if less or equal. */ +#define EISD__K_MATNEV 3 /* Match never. */ + +/* Section type. */ +#define EISD__K_NORMAL 0 /* Normal program image section. */ +#define EISD__K_SHRFXD 1 /* Shareable fixed section. */ +#define EISD__K_PRVFXD 2 /* Private fixed section. */ +#define EISD__K_SHRPIC 3 /* Shareable pic section. */ +#define EISD__K_PRVPIC 4 /* Private PIC section. */ +#define EISD__K_USRSTACK 253 /* User stack section. */ + +/* EISD offsets. */ + +#define EISD__L_EISDSIZE 8 +#define EISD__L_SECSIZE 12 +#define EISD__Q_VIR_ADDR 16 +#define EISD__L_FLAGS 24 +#define EISD__L_VBN 28 +#define EISD__R_CONTROL 32 +#define EISD__L_IDENT 36 +#define EISD__T_GBLNAM 40 + +#endif /* _VMS_EISD_H */ diff --git a/external/gpl3/gdb/dist/include/vms/emh.h b/external/gpl3/gdb/dist/include/vms/emh.h new file mode 100644 index 000000000000..973d71ea6cf6 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/emh.h @@ -0,0 +1,79 @@ +/* Alpha VMS external format of Extended Module Header. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EMH_H +#define _VMS_EMH_H + +#define EMH__C_MHD 0 /* Main header record. */ +#define EMH__C_LNM 1 /* Language name and version. */ +#define EMH__C_SRC 2 /* Source file specification. */ +#define EMH__C_TTL 3 /* Title text of module. */ +#define EMH__C_CPR 4 /* Copyright notice. */ +#define EMH__C_MTC 5 /* Maintenance status. */ +#define EMH__C_GTX 6 /* General text. */ +#define EMH__C_MAXHDRTYP 6 /* Maximum allowable type. */ + +struct vms_emh_common +{ + /* Record type. */ + unsigned char rectyp[2]; + + /* Record size. */ + unsigned char size[2]; + + /* Subtype. */ + unsigned char subtyp[2]; +}; + +struct vms_emh_mhd +{ + struct vms_emh_common common; + + unsigned char strlvl; + + unsigned char temp; + + unsigned char arch1[4]; + unsigned char arch2[4]; + + unsigned char recsiz[4]; + + /* Module name: ASCIC. */ + /* Module version: ASCIC. */ + /* Compile data: ASCIC. */ +}; + +#define EOBJ__C_MAXRECSIZ 8192 /* Maximum legal record size. */ +#define EOBJ__C_STRLVL 2 /* Structure level. */ +#define EOBJ__C_SYMSIZ 64 /* Maximum symbol length. */ +#define EOBJ__C_SECSIZ 31 /* Maximum section name length. */ +#define EOBJ__C_STOREPLIM -1 /* Maximum repeat count on store commands. */ +#define EOBJ__C_PSCALILIM 16 /* Maximum p-sect alignment. */ + +struct vms_emh_lnm +{ + struct vms_emh_common common; + + /* Language processor name: ASCII. */ +}; + +#endif /* _VMS_EMH_H */ diff --git a/external/gpl3/gdb/dist/include/vms/eobjrec.h b/external/gpl3/gdb/dist/include/vms/eobjrec.h new file mode 100644 index 000000000000..985fda782144 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/eobjrec.h @@ -0,0 +1,48 @@ +/* Alpha VMS external format of Extended Object Records. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_EOBJREC_H +#define _VMS_EOBJREC_H + +#define EOBJ__C_EMH 8 /* EVAX mdule header record. */ +#define EOBJ__C_EEOM 9 /* EVAX ed of module record. */ +#define EOBJ__C_EGSD 10 /* EVAX gobal symbol definition record. */ +#define EOBJ__C_ETIR 11 /* EVAX txt information record. */ +#define EOBJ__C_EDBG 12 /* EVAX Dbugger information record. */ +#define EOBJ__C_ETBT 13 /* EVAX Taceback information record. */ +#define EOBJ__C_MAXRECTYP 13 /* EVAX Lst assigned record type. */ + +struct vms_eobjrec +{ + /* Record type. */ + unsigned char rectyp[2]; + + /* Record size. */ + unsigned char size[2]; + +#if 0 + /* Record subtype. */ + unsigned char subtyp[2]; +#endif +}; + +#endif /* _VMS_EOBJREC_H */ diff --git a/external/gpl3/gdb/dist/include/vms/esdf.h b/external/gpl3/gdb/dist/include/vms/esdf.h new file mode 100644 index 000000000000..79ee3d61091a --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/esdf.h @@ -0,0 +1,41 @@ +/* Alpha VMS external format of Extended GSD Global Symbol Definition. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ESDF_H +#define _VMS_ESDF_H + +struct vms_esdf +{ + struct vms_egsy header; + + unsigned char value[8]; + unsigned char code_address[8]; + unsigned char ca_psindx[4]; + + unsigned char psindx[4]; + unsigned char namlng; + unsigned char name[31]; +}; + +#define ESDF__B_NAMLNG 32 + +#endif /* _VMS_ESDF_H */ diff --git a/external/gpl3/gdb/dist/include/vms/esdfm.h b/external/gpl3/gdb/dist/include/vms/esdfm.h new file mode 100644 index 000000000000..e00e44a13450 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/esdfm.h @@ -0,0 +1,49 @@ +/* Alpha VMS external format of Extended Symbol Definition for version Mask. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ESDFM_H +#define _VMS_ESDFM_H + +struct vms_esdfm +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char size[2]; + + /* Data type. */ + unsigned char datyp; + + /* Pad for alignment. */ + unsigned char temp; + + unsigned char flags[2]; + + unsigned char value[8]; + unsigned char psindx[4]; + unsigned char version_mask[4]; + unsigned char namlng; + unsigned char name[31]; +}; + +#endif /* _VMS_ESDFM_H */ diff --git a/external/gpl3/gdb/dist/include/vms/esdfv.h b/external/gpl3/gdb/dist/include/vms/esdfv.h new file mode 100644 index 000000000000..fae0dbc1867b --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/esdfv.h @@ -0,0 +1,49 @@ +/* Alpha VMS external format of Extended Symbol Def for Vectored symbols. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ESDFV_H +#define _VMS_ESDFV_H + +struct vms_esdfv +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char size[2]; + + /* Data type. */ + unsigned char datyp; + + /* Pad for alignment. */ + unsigned char temp; + + unsigned char flags[2]; + + unsigned char value[8]; + unsigned char psindx[4]; + unsigned char vector[4]; + unsigned char namlng; + unsigned char name[31]; +}; + +#endif /* _VMS_ESDFV_H */ diff --git a/external/gpl3/gdb/dist/include/vms/esgps.h b/external/gpl3/gdb/dist/include/vms/esgps.h new file mode 100644 index 000000000000..e668a8748abe --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/esgps.h @@ -0,0 +1,72 @@ +/* Alpha VMS external format of Extended Shared Program Section Definition. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ESGPS_H +#define _VMS_ESGPS_H + +struct vms_esgps +{ + /* Entry type. */ + unsigned char gsdtyp[2]; + + /* Length of the entry. */ + unsigned char gsdsiz[2]; + + /* Psect alignment. */ + unsigned char align; + + /* Pad for alignment. */ + unsigned char temp; + + unsigned char flags[2]; + + /* Length of this contribution. */ + unsigned char alloc[4]; + + /* Image offset of the psect. */ + unsigned char base[4]; + + /* Symbol vector offset. */ + unsigned char value[8]; + + /* Name. */ + unsigned char namlng; + unsigned char name[31]; +}; + +/* These are the same as EGPS flags. */ + +#define ESGPS__V_PIC (1 << 0) /* Not meaningful. */ +#define ESGPS__V_LIB (1 << 1) /* Defined in a shareable image. */ +#define ESGPS__V_OVR (1 << 2) /* Overlaid contribution. */ +#define ESGPS__V_REL (1 << 3) /* Relocatable. */ +#define ESGPS__V_GBL (1 << 4) /* Global. */ +#define ESGPS__V_SHR (1 << 5) /* Shareable. */ +#define ESGPS__V_EXE (1 << 6) /* Executable. */ +#define ESGPS__V_RD (1 << 7) /* Readable. */ +#define ESGPS__V_WRT (1 << 8) /* Writable. */ +#define ESGPS__V_VEC (1 << 9) /* Change mode dispatch or message vectors. */ +#define ESGPS__V_NOMOD (1 << 10) /* Demand-zero. */ +#define ESGPS__V_COM (1 << 11) /* Conditional storage. */ +#define ESGPS__V_ALLOC_64BIT (1 << 12) /* Allocated in 64-bit space. */ + +#endif /* _VMS_ESGPS_H */ diff --git a/external/gpl3/gdb/dist/include/vms/esrf.h b/external/gpl3/gdb/dist/include/vms/esrf.h new file mode 100644 index 000000000000..291250c96fc1 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/esrf.h @@ -0,0 +1,36 @@ +/* Alpha VMS external format of Extended GSD Global Symbol Reference. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ESRF_H +#define _VMS_ESRF_H + +struct vms_esrf +{ + struct vms_egsy header; + + unsigned char namlng; + unsigned char name[31]; +}; + +#define ESRF__B_NAMLNG 8 + +#endif /* _VMS_ESRF_H */ diff --git a/external/gpl3/gdb/dist/include/vms/etir.h b/external/gpl3/gdb/dist/include/vms/etir.h new file mode 100644 index 000000000000..4d922dc3e8d3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/etir.h @@ -0,0 +1,114 @@ +/* Alpha VMS external format of Extended Text Information and Relocation. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_ETIR_H +#define _VMS_ETIR_H + +#define ETIR__C_MINSTACOD 0 /* Minimum stack code. */ +#define ETIR__C_STA_GBL 0 /* Stack global symbol value. */ +#define ETIR__C_STA_LW 1 /* Stack longword. */ +#define ETIR__C_STA_QW 2 /* Stack quadword. */ +#define ETIR__C_STA_PQ 3 /* Stack psect base + quadword off. */ +#define ETIR__C_STA_LI 4 /* Stack literal. */ +#define ETIR__C_STA_MOD 5 /* Stack module. */ +#define ETIR__C_STA_CKARG 6 /* Check Arguments. */ +#define ETIR__C_MAXSTACOD 6 /* Maximum stack code. */ + +#define ETIR__C_MINSTOCOD 50 /* Minimum store code. */ +#define ETIR__C_STO_B 50 /* Store byte. */ +#define ETIR__C_STO_W 51 /* Store word. */ +#define ETIR__C_STO_LW 52 /* Store longword. */ +#define ETIR__C_STO_QW 53 /* Store quadword. */ +#define ETIR__C_STO_IMMR 54 /* Store immediate Repeated. */ +#define ETIR__C_STO_GBL 55 /* Store global. */ +#define ETIR__C_STO_CA 56 /* Store code address. */ +#define ETIR__C_STO_RB 57 /* Store relative branch. */ +#define ETIR__C_STO_AB 58 /* Store absolute branch. */ +#define ETIR__C_STO_OFF 59 /* Store offset within psect. */ +#define ETIR__C_STO_IMM 61 /* Store immediate. */ +#define ETIR__C_STO_GBL_LW 62 /* Store global Longword. */ +#define ETIR__C_STO_LP_PSB 63 /* STO_LP_PSB not valid in level 2 use STC_LP_PSB. */ +#define ETIR__C_STO_HINT_GBL 64 /* Store 14 bit HINT at global address. */ +#define ETIR__C_STO_HINT_PS 65 /* Store 14 bit HINT at psect + offset */ +#define ETIR__C_MAXSTOCOD 65 /* Maximum store code. */ + +/* Operate codes. */ +#define ETIR__C_MINOPRCOD 100 /* Minimum operate code. */ +#define ETIR__C_OPR_NOP 100 /* No-op. */ +#define ETIR__C_OPR_ADD 101 /* Add. */ +#define ETIR__C_OPR_SUB 102 /* Subtract. */ +#define ETIR__C_OPR_MUL 103 /* Multiply. */ +#define ETIR__C_OPR_DIV 104 /* Divide. */ +#define ETIR__C_OPR_AND 105 /* Logical AND. */ +#define ETIR__C_OPR_IOR 106 /* Logical inclusive OR. */ +#define ETIR__C_OPR_EOR 107 /* Logical exclusive OR. */ +#define ETIR__C_OPR_NEG 108 /* Negate. */ +#define ETIR__C_OPR_COM 109 /* Complement. */ +#define ETIR__C_OPR_INSV 110 /* Insert bit field. */ +#define ETIR__C_OPR_ASH 111 /* Arithmetic shift. */ +#define ETIR__C_OPR_USH 112 /* Unsigned shift. */ +#define ETIR__C_OPR_ROT 113 /* Rotate. */ +#define ETIR__C_OPR_SEL 114 /* Select one of 3 long on top of stack. */ +#define ETIR__C_OPR_REDEF 115 /* Redefine this symbol after pass 2. */ +#define ETIR__C_OPR_DFLIT 116 /* Define a literal. */ +#define ETIR__C_MAXOPRCOD 116 /* Maximum operate code. */ + +/* Control codes. */ +#define ETIR__C_MINCTLCOD 150 /* Minimum control code. */ +#define ETIR__C_CTL_SETRB 150 /* Set relocation base. */ +#define ETIR__C_CTL_AUGRB 151 /* Augment relocation base. */ +#define ETIR__C_CTL_DFLOC 152 /* Define debug location. */ +#define ETIR__C_CTL_STLOC 153 /* Set debug location. */ +#define ETIR__C_CTL_STKDL 154 /* Stack debug location. */ +#define ETIR__C_MAXCTLCOD 154 /* Maximum control code. */ + +/* Store-conditional (STC) codes. */ +#define ETIR__C_MINSTCCOD 200 /* Minimum store-conditional code. */ +#define ETIR__C_STC_LP 200 /* STC Linkage Pair. */ +#define ETIR__C_STC_LP_PSB 201 /* STC Linkage Pair with Proc Signature. */ +#define ETIR__C_STC_GBL 202 /* STC Address at global address. */ +#define ETIR__C_STC_GCA 203 /* STC Code Address at global address. */ +#define ETIR__C_STC_PS 204 /* STC Address at psect + offset. */ +#define ETIR__C_STC_NOP_GBL 205 /* STC NOP at address of global. */ +#define ETIR__C_STC_NOP_PS 206 /* STC NOP at pect + offset. */ +#define ETIR__C_STC_BSR_GBL 207 /* STC BSR at global address. */ +#define ETIR__C_STC_BSR_PS 208 /* STC BSR at pect + offset. */ +#define ETIR__C_STC_LDA_GBL 209 /* STC LDA at global address. */ +#define ETIR__C_STC_LDA_PS 210 /* STC LDA at psect + offset. */ +#define ETIR__C_STC_BOH_GBL 211 /* STC BSR or Hint at global address. */ +#define ETIR__C_STC_BOH_PS 212 /* STC BSR or Hint at pect + offset. */ +#define ETIR__C_STC_NBH_GBL 213 /* STC NOP,BSR or HINT at global address. */ +#define ETIR__C_STC_NBH_PS 214 /* STC NOP,BSR or HINT at psect + offset. */ +#define ETIR__C_MAXSTCCOD 214 /* Maximum store-conditional code. */ + +#define ETIR__C_HEADER_SIZE 4 /* Size of the header of a command */ + +struct vms_etir +{ + /* Commands. See above. */ + unsigned char rectyp[2]; + + /* Size (including this header). */ + unsigned char size[2]; +}; + +#endif /* _VMS_ETIR_H */ diff --git a/external/gpl3/gdb/dist/include/vms/internal.h b/external/gpl3/gdb/dist/include/vms/internal.h new file mode 100644 index 000000000000..1c8c472451e3 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/internal.h @@ -0,0 +1,63 @@ +/* Alpha VMS internal format. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_INTERNAL_H +#define _VMS_INTERNAL_H + +struct vms_internal_eisd +{ + unsigned int majorid; /* Version. */ + unsigned int minorid; + unsigned int eisdsize; /* Size (in bytes) of this eisd. */ + unsigned int secsize; /* Size (in bytes) of the section. */ + bfd_vma virt_addr; /* Virtual address of the section. */ + unsigned int flags; /* Flags. */ + unsigned int vbn; /* Base virtual block number. */ + unsigned char pfc; /* Page fault cluster. */ + unsigned char matchctl; /* Linker match control. */ + unsigned char type; /* Section type. */ +}; + +struct vms_internal_gbl_eisd +{ + struct vms_internal_eisd common; + + unsigned int ident; /* Ident for global section. */ + unsigned char gblnam[44]; /* Global name ascic. */ +}; + +struct vms_internal_eisd_map +{ + /* Next eisd in the list. */ + struct vms_internal_eisd_map *next; + + /* Offset in output file. */ + file_ptr file_pos; + + union + { + struct vms_internal_eisd eisd; + struct vms_internal_gbl_eisd gbl_eisd; + } u; +}; + +#endif /* _VMS_INTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/vms/lbr.h b/external/gpl3/gdb/dist/include/vms/lbr.h new file mode 100644 index 000000000000..bdb436aa70a7 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/lbr.h @@ -0,0 +1,329 @@ +/* Alpha VMS external format of Libraries. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_LBR_H +#define _VMS_LBR_H + +/* Libray HeaDer. */ + +/* Magic numbers. Should match the major version. */ + +#define LHD_SANEID_DCX 319232342 +#define LHD_SANEID3 233579905 +#define LHD_SANEID6 233579911 + +/* Library type. */ +#define LBR__C_TYP_UNK 0 /* Unknown / unspecified. */ +#define LBR__C_TYP_OBJ 1 /* Vax object. */ +#define LBR__C_TYP_MLB 2 /* Macro. */ +#define LBR__C_TYP_HLP 3 /* Help. */ +#define LBR__C_TYP_TXT 4 /* Text. */ +#define LBR__C_TYP_SHSTB 5 /* Vax shareable image. */ +#define LBR__C_TYP_NCS 6 /* NCS. */ +#define LBR__C_TYP_EOBJ 7 /* Alpha object. */ +#define LBR__C_TYP_ESHSTB 8 /* Alpha shareable image. */ +#define LBR__C_TYP_IOBJ 9 /* IA-64 object. */ +#define LBR__C_TYP_ISHSTB 10 /* IA-64 shareable image. */ + +struct vms_lhd +{ + /* Type of the library. See above. */ + unsigned char type; + + /* Number of indexes. Generally 1, 2 for object libraries. */ + unsigned char nindex; + + unsigned char fill_1[2]; + + /* Sanity Id. */ + unsigned char sanity[4]; + + /* Version. */ + unsigned char majorid[2]; + unsigned char minorid[2]; + + /* Tool name. */ + unsigned char lbrver[32]; + + /* Create time. */ + unsigned char credat[8]; + + /* Update time. */ + unsigned char updtim[8]; + + /* Size of the MHD. */ + unsigned char mhdusz; + + unsigned char idxblkf[2]; /* Unused. */ + unsigned char fill_2; + unsigned char closerror[2]; + + unsigned char spareword[2]; + + /* First free block, and number of free blocks. */ + unsigned char freevbn[4]; + unsigned char freeblk[4]; + + unsigned char nextrfa[6]; + unsigned char nextvbn[4]; + + /* Free pre-allocated index block. */ + unsigned char freidxblk[4]; + unsigned char freeidx[4]; + + /* Highest pre-allocated index block and in use. */ + unsigned char hipreal[4]; + unsigned char hiprusd[4]; + + /* Number of index blocks in use. */ + unsigned char idxblks[4]; + + /* Number of index entries. */ + unsigned char idxcnt[4]; + + /* Number of modules entries. */ + unsigned char modcnt[4]; + + unsigned char fill_3[2]; + + /* Number of module headers. */ + unsigned char modhdrs[4]; + + /* Overhead index pointers. */ + unsigned char idxovh[4]; + + /* Update history records. */ + unsigned char maxluhrec[2]; + unsigned char numluhrec[2]; + unsigned char begluhrfa[6]; + unsigned char endluhrfa[6]; + + /* DCX map. */ + unsigned char dcxmapvbn[4]; + + unsigned char fill_4[4 * 13]; +}; + +/* Known major ids. */ +#define LBR_MAJORID 3 /* Alpha libraries. */ +#define LBR_ELFMAJORID 6 /* Elf libraries (new index, new data). */ + +/* Offset of the first IDD. */ +#define LHD_IDXDESC 196 + +/* InDex Description. */ +struct vms_idd +{ + unsigned char flags[2]; + + /* Max length of the key. */ + unsigned char keylen[2]; + + /* First index block. */ + unsigned char vbn[4]; +}; + +/* IDD flags. */ +#define IDD__FLAGS_ASCII 1 +#define IDD__FLAGS_LOCKED 2 +#define IDD__FLAGS_VARLENIDX 4 +#define IDD__FLAGS_NOCASECMP 8 +#define IDD__FLAGS_NOCASENTR 16 +#define IDD__FLAGS_UPCASNTRY 32 + +#define IDD_LENGTH 8 + +/* Index block. */ +#define INDEXDEF__LENGTH 512 +#define INDEXDEF__BLKSIZ 500 + +struct vms_indexdef +{ + /* Number of bytes used. */ + unsigned char used[2]; + + /* VBN of the parent. */ + unsigned char parent[4]; + + unsigned char fill_1[6]; + + /* The key field contains vms_idx/vms_elfidx structures, which are + simply a key (= a string) and a rfa. */ + unsigned char keys[INDEXDEF__BLKSIZ]; +}; + +/* An offset in a file. */ + +struct vms_rfa +{ + /* Logical block number, 1 based. + 0 means that the field is absent. Block size is 512. */ + unsigned char vbn[4]; + + /* Offset within the block. */ + unsigned char offset[2]; +}; + +/* Index keys. For version 3. */ + +struct vms_idx +{ + /* Offset from the start of the vbn, so minimum should be + DATA__DATA (ie 6). */ + struct vms_rfa rfa; + + unsigned char keylen; + /* The length of this field is in fact keylen. */ + unsigned char keyname[256]; +}; + +/* Index keys, for version 4 and later. */ + +struct vms_elfidx +{ + struct vms_rfa rfa; + + unsigned char keylen[2]; + unsigned char flags; + unsigned char keyname[256]; +}; + +/* Flags of elfidx. */ + +#define ELFIDX__WEAK 0x01 /* Weak symbol. */ +#define ELFIDX__GROUP 0x02 /* Group symbol. */ +#define ELFIDX__LISTRFA 0x04 /* RFA field points to an LHS. */ +#define ELFIDX__SYMESC 0x08 /* Long symbol. */ + +#define RFADEF__C_INDEX 0xffff + +/* List head structure. That's what is pointed by rfa when LISTRFA flag + is set in elfidx. */ + +struct vms_lhs +{ + struct vms_rfa ng_g_rfa; /* Non-group global. */ + struct vms_rfa ng_wk_rfa; /* Non-group weak. */ + struct vms_rfa g_g_rfa; /* Group global. */ + struct vms_rfa g_wk_rfa; /* Group weak. */ + unsigned char flags; +}; + +/* List node structure. Fields of LHS point to this structure. */ + +struct vms_lns +{ + /* Next node in the list. */ + struct vms_rfa nxtrfa; + + /* Module associated with the key. */ + struct vms_rfa modrfa; +}; + +struct vms_datadef +{ + /* Number of records in this block. */ + unsigned char recs; + unsigned char fill_1; + + /* Next vbn. */ + unsigned char link[4]; + + /* Data. The first word is the record length, followed by record + data and a possible pad byte so that record length is always aligned. */ + unsigned char data[506]; +}; +#define DATA__LENGTH 512 +#define DATA__DATA 6 + +/* Key name block. This is used for keys longer than 128 bytes. */ + +struct vms_kbn +{ + /* Length of the key chunk. */ + unsigned char keylen[2]; + + /* RFA of the next chunk. */ + struct vms_rfa rfa; + + /* Followed by the key chunk. */ +}; + +/* Module header. */ +struct vms_mhd +{ + /* Fixed part. */ + unsigned char lbrflag; + unsigned char id; + unsigned char fill_1[2]; + unsigned char refcnt[4]; + unsigned char datim[8]; + + unsigned char objstat; + /* Ident or GSMATCH. */ + unsigned char objidlng; + unsigned char objid[31]; + + unsigned char pad1[3]; + unsigned char otherefcnt[4]; + unsigned char modsize[4]; + unsigned char pad2[4]; +}; + +#define MHD__C_MHDID 0xad /* Value for id. */ +#define MHD__C_MHDLEN 16 /* Fixed part length. */ +#define MHD__C_USRDAT 16 + +/* Flags for objstat. */ +#define MHD__M_SELSRC 0x1 /* Selective search. */ +#define MHD__M_OBJTIR 0x2 +#define MHD__M_WKSYM 0x4 + +struct vms_luh +{ + unsigned char nxtluhblk[4]; + unsigned char spare[2]; + unsigned char data[506]; +}; + +struct vms_luhdef +{ + unsigned char rechdr[2]; + unsigned char reclen[2]; +}; +#define LUH__RECHDRLEN 4 +#define LUH__RECHDRMRK 0xabba +#define LUH__DATAFLDLEN 506 + +/* Entry in the history. */ + +struct vms_leh +{ + unsigned char date[8]; + unsigned char nbr_units[2]; + unsigned char action[2]; /* 1: delete, 2: insert, 3: replaced. */ + unsigned char idlen; + /* username + modules... */ +}; + +#endif /* _VMS_LBR_H */ diff --git a/external/gpl3/gdb/dist/include/vms/prt.h b/external/gpl3/gdb/dist/include/vms/prt.h new file mode 100644 index 000000000000..8b8d27b56454 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/prt.h @@ -0,0 +1,43 @@ +/* Alpha VMS external format of Protection values. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_PRT_H +#define _VMS_PRT_H + +#define PRT__C_NA 0 /* No access. */ +#define PRT__C_RESERVED 1 +#define PRT__C_KW 2 /* Kernel RW. */ +#define PRT__C_KR 3 /* Kernel RO. */ +#define PRT__C_UW 4 /* User RW. */ +#define PRT__C_EW 5 /* Executive RW. */ +#define PRT__C_ERKW 6 /* Executive RO, Kernel RW. */ +#define PRT__C_ER 7 /* Executive RO. */ +#define PRT__C_SW 8 /* Supervisor RW. */ +#define PRT__C_SREW 9 /* Supervisor RO, Executive RW. */ +#define PRT__C_SRKW 10 /* Supervisor RO, Kernel RW. */ +#define PRT__C_SR 11 /* Supervisor RO. */ +#define PRT__C_URSW 12 /* User RO, Supervisor RW. */ +#define PRT__C_UREW 13 /* User RO, Executive RW. */ +#define PRT__C_URKW 14 /* User RO, Kernel RW. */ +#define PRT__C_UR 15 /* User RO. */ + +#endif /* _VMS_PRT_H */ diff --git a/external/gpl3/gdb/dist/include/vms/shl.h b/external/gpl3/gdb/dist/include/vms/shl.h new file mode 100644 index 000000000000..d1d9fae92dc8 --- /dev/null +++ b/external/gpl3/gdb/dist/include/vms/shl.h @@ -0,0 +1,55 @@ +/* Alpha VMS external format of Shareable image List. + + Copyright 2010 Free Software Foundation, Inc. + Written by Tristan Gingold , AdaCore. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _VMS_SHL_H +#define _VMS_SHL_H + +struct vms_shl +{ + /* Base address of this shareable image. */ + unsigned char baseva[4]; + + /* Point in SHL shareable image to SHL in executable image. */ + unsigned char shlptr[4]; + + /* GSMATCH. */ + unsigned char ident[4]; + + /* Permanent shareable image context. */ + unsigned char permctx[4]; + + /* Size of this structure. */ + unsigned char size; + + unsigned char fill_1[2]; + + /* Flags. */ + unsigned char flags; + + /* Address of the image control block (in memory). */ + unsigned char icb[4]; + + /* Image name. ASCIC. */ + unsigned char imgnam[40]; +}; + +#endif /* _VMS_SHL_H */ diff --git a/external/gpl3/gdb/dist/include/xregex.h b/external/gpl3/gdb/dist/include/xregex.h new file mode 100644 index 000000000000..645195bbceb5 --- /dev/null +++ b/external/gpl3/gdb/dist/include/xregex.h @@ -0,0 +1,28 @@ +/* This file redefines all regex external names before including + a renamed copy of glibc's regex.h. */ + +#ifndef _XREGEX_H +#define _XREGEX_H 1 + +# define regfree xregfree +# define regexec xregexec +# define regcomp xregcomp +# define regerror xregerror +# define re_set_registers xre_set_registers +# define re_match_2 xre_match_2 +# define re_match xre_match +# define re_search xre_search +# define re_compile_pattern xre_compile_pattern +# define re_set_syntax xre_set_syntax +# define re_search_2 xre_search_2 +# define re_compile_fastmap xre_compile_fastmap +# define re_syntax_options xre_syntax_options +# define re_max_failures xre_max_failures + +# define _REGEX_RE_COMP +# define re_comp xre_comp +# define re_exec xre_exec + +#include "xregex2.h" + +#endif /* xregex.h */ diff --git a/external/gpl3/gdb/dist/include/xregex2.h b/external/gpl3/gdb/dist/include/xregex2.h new file mode 100644 index 000000000000..d3d0da14a987 --- /dev/null +++ b/external/gpl3/gdb/dist/include/xregex2.h @@ -0,0 +1,565 @@ +/* Definitions for data structures and routines for the regular + expression library, version 0.12. + + Copyright (C) 1985, 1989, 1990, 1991, 1992, 1993, 1995, 1996, 1997, + 1998, 2000, 2005 Free Software Foundation, Inc. + + This file is part of the GNU C Library. Its master source is NOT part of + the C library, however. The master source lives in /gd/gnu/lib. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. */ + +#ifndef _REGEX_H +#define _REGEX_H 1 + +/* Allow the use in C++ code. */ +#ifdef __cplusplus +extern "C" { +#endif + +/* POSIX says that must be included (by the caller) before + . */ + +#if !defined _POSIX_C_SOURCE && !defined _POSIX_SOURCE && defined VMS +/* VMS doesn't have `size_t' in , even though POSIX says it + should be there. */ +# include +#endif + +/* The following two types have to be signed and unsigned integer type + wide enough to hold a value of a pointer. For most ANSI compilers + ptrdiff_t and size_t should be likely OK. Still size of these two + types is 2 for Microsoft C. Ugh... */ +typedef long int s_reg_t; +typedef unsigned long int active_reg_t; + +/* The following bits are used to determine the regexp syntax we + recognize. The set/not-set meanings are chosen so that Emacs syntax + remains the value 0. The bits are given in alphabetical order, and + the definitions shifted by one from the previous bit; thus, when we + add or remove a bit, only one other definition need change. */ +typedef unsigned long int reg_syntax_t; + +/* If this bit is not set, then \ inside a bracket expression is literal. + If set, then such a \ quotes the following character. */ +#define RE_BACKSLASH_ESCAPE_IN_LISTS ((unsigned long int) 1) + +/* If this bit is not set, then + and ? are operators, and \+ and \? are + literals. + If set, then \+ and \? are operators and + and ? are literals. */ +#define RE_BK_PLUS_QM (RE_BACKSLASH_ESCAPE_IN_LISTS << 1) + +/* If this bit is set, then character classes are supported. They are: + [:alpha:], [:upper:], [:lower:], [:digit:], [:alnum:], [:xdigit:], + [:space:], [:print:], [:punct:], [:graph:], and [:cntrl:]. + If not set, then character classes are not supported. */ +#define RE_CHAR_CLASSES (RE_BK_PLUS_QM << 1) + +/* If this bit is set, then ^ and $ are always anchors (outside bracket + expressions, of course). + If this bit is not set, then it depends: + ^ is an anchor if it is at the beginning of a regular + expression or after an open-group or an alternation operator; + $ is an anchor if it is at the end of a regular expression, or + before a close-group or an alternation operator. + + This bit could be (re)combined with RE_CONTEXT_INDEP_OPS, because + POSIX draft 11.2 says that * etc. in leading positions is undefined. + We already implemented a previous draft which made those constructs + invalid, though, so we haven't changed the code back. */ +#define RE_CONTEXT_INDEP_ANCHORS (RE_CHAR_CLASSES << 1) + +/* If this bit is set, then special characters are always special + regardless of where they are in the pattern. + If this bit is not set, then special characters are special only in + some contexts; otherwise they are ordinary. Specifically, + * + ? and intervals are only special when not after the beginning, + open-group, or alternation operator. */ +#define RE_CONTEXT_INDEP_OPS (RE_CONTEXT_INDEP_ANCHORS << 1) + +/* If this bit is set, then *, +, ?, and { cannot be first in an re or + immediately after an alternation or begin-group operator. */ +#define RE_CONTEXT_INVALID_OPS (RE_CONTEXT_INDEP_OPS << 1) + +/* If this bit is set, then . matches newline. + If not set, then it doesn't. */ +#define RE_DOT_NEWLINE (RE_CONTEXT_INVALID_OPS << 1) + +/* If this bit is set, then . doesn't match NUL. + If not set, then it does. */ +#define RE_DOT_NOT_NULL (RE_DOT_NEWLINE << 1) + +/* If this bit is set, nonmatching lists [^...] do not match newline. + If not set, they do. */ +#define RE_HAT_LISTS_NOT_NEWLINE (RE_DOT_NOT_NULL << 1) + +/* If this bit is set, either \{...\} or {...} defines an + interval, depending on RE_NO_BK_BRACES. + If not set, \{, \}, {, and } are literals. */ +#define RE_INTERVALS (RE_HAT_LISTS_NOT_NEWLINE << 1) + +/* If this bit is set, +, ? and | aren't recognized as operators. + If not set, they are. */ +#define RE_LIMITED_OPS (RE_INTERVALS << 1) + +/* If this bit is set, newline is an alternation operator. + If not set, newline is literal. */ +#define RE_NEWLINE_ALT (RE_LIMITED_OPS << 1) + +/* If this bit is set, then `{...}' defines an interval, and \{ and \} + are literals. + If not set, then `\{...\}' defines an interval. */ +#define RE_NO_BK_BRACES (RE_NEWLINE_ALT << 1) + +/* If this bit is set, (...) defines a group, and \( and \) are literals. + If not set, \(...\) defines a group, and ( and ) are literals. */ +#define RE_NO_BK_PARENS (RE_NO_BK_BRACES << 1) + +/* If this bit is set, then \ matches . + If not set, then \ is a back-reference. */ +#define RE_NO_BK_REFS (RE_NO_BK_PARENS << 1) + +/* If this bit is set, then | is an alternation operator, and \| is literal. + If not set, then \| is an alternation operator, and | is literal. */ +#define RE_NO_BK_VBAR (RE_NO_BK_REFS << 1) + +/* If this bit is set, then an ending range point collating higher + than the starting range point, as in [z-a], is invalid. + If not set, then when ending range point collates higher than the + starting range point, the range is ignored. */ +#define RE_NO_EMPTY_RANGES (RE_NO_BK_VBAR << 1) + +/* If this bit is set, then an unmatched ) is ordinary. + If not set, then an unmatched ) is invalid. */ +#define RE_UNMATCHED_RIGHT_PAREN_ORD (RE_NO_EMPTY_RANGES << 1) + +/* If this bit is set, succeed as soon as we match the whole pattern, + without further backtracking. */ +#define RE_NO_POSIX_BACKTRACKING (RE_UNMATCHED_RIGHT_PAREN_ORD << 1) + +/* If this bit is set, do not process the GNU regex operators. + If not set, then the GNU regex operators are recognized. */ +#define RE_NO_GNU_OPS (RE_NO_POSIX_BACKTRACKING << 1) + +/* If this bit is set, turn on internal regex debugging. + If not set, and debugging was on, turn it off. + This only works if regex.c is compiled -DDEBUG. + We define this bit always, so that all that's needed to turn on + debugging is to recompile regex.c; the calling code can always have + this bit set, and it won't affect anything in the normal case. */ +#define RE_DEBUG (RE_NO_GNU_OPS << 1) + +/* If this bit is set, a syntactically invalid interval is treated as + a string of ordinary characters. For example, the ERE 'a{1' is + treated as 'a\{1'. */ +#define RE_INVALID_INTERVAL_ORD (RE_DEBUG << 1) + +/* This global variable defines the particular regexp syntax to use (for + some interfaces). When a regexp is compiled, the syntax used is + stored in the pattern buffer, so changing this does not affect + already-compiled regexps. */ +extern reg_syntax_t re_syntax_options; + +/* Define combinations of the above bits for the standard possibilities. + (The [[[ comments delimit what gets put into the Texinfo file, so + don't delete them!) */ +/* [[[begin syntaxes]]] */ +#define RE_SYNTAX_EMACS 0 + +#define RE_SYNTAX_AWK \ + (RE_BACKSLASH_ESCAPE_IN_LISTS | RE_DOT_NOT_NULL \ + | RE_NO_BK_PARENS | RE_NO_BK_REFS \ + | RE_NO_BK_VBAR | RE_NO_EMPTY_RANGES \ + | RE_DOT_NEWLINE | RE_CONTEXT_INDEP_ANCHORS \ + | RE_UNMATCHED_RIGHT_PAREN_ORD | RE_NO_GNU_OPS) + +#define RE_SYNTAX_GNU_AWK \ + ((RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS | RE_DEBUG) \ + & ~(RE_DOT_NOT_NULL | RE_INTERVALS | RE_CONTEXT_INDEP_OPS)) + +#define RE_SYNTAX_POSIX_AWK \ + (RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS \ + | RE_INTERVALS | RE_NO_GNU_OPS) + +#define RE_SYNTAX_GREP \ + (RE_BK_PLUS_QM | RE_CHAR_CLASSES \ + | RE_HAT_LISTS_NOT_NEWLINE | RE_INTERVALS \ + | RE_NEWLINE_ALT) + +#define RE_SYNTAX_EGREP \ + (RE_CHAR_CLASSES | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INDEP_OPS | RE_HAT_LISTS_NOT_NEWLINE \ + | RE_NEWLINE_ALT | RE_NO_BK_PARENS \ + | RE_NO_BK_VBAR) + +#define RE_SYNTAX_POSIX_EGREP \ + (RE_SYNTAX_EGREP | RE_INTERVALS | RE_NO_BK_BRACES \ + | RE_INVALID_INTERVAL_ORD) + +/* P1003.2/D11.2, section 4.20.7.1, lines 5078ff. */ +#define RE_SYNTAX_ED RE_SYNTAX_POSIX_BASIC + +#define RE_SYNTAX_SED RE_SYNTAX_POSIX_BASIC + +/* Syntax bits common to both basic and extended POSIX regex syntax. */ +#define _RE_SYNTAX_POSIX_COMMON \ + (RE_CHAR_CLASSES | RE_DOT_NEWLINE | RE_DOT_NOT_NULL \ + | RE_INTERVALS | RE_NO_EMPTY_RANGES) + +#define RE_SYNTAX_POSIX_BASIC \ + (_RE_SYNTAX_POSIX_COMMON | RE_BK_PLUS_QM) + +/* Differs from ..._POSIX_BASIC only in that RE_BK_PLUS_QM becomes + RE_LIMITED_OPS, i.e., \? \+ \| are not recognized. Actually, this + isn't minimal, since other operators, such as \`, aren't disabled. */ +#define RE_SYNTAX_POSIX_MINIMAL_BASIC \ + (_RE_SYNTAX_POSIX_COMMON | RE_LIMITED_OPS) + +#define RE_SYNTAX_POSIX_EXTENDED \ + (_RE_SYNTAX_POSIX_COMMON | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INDEP_OPS | RE_NO_BK_BRACES \ + | RE_NO_BK_PARENS | RE_NO_BK_VBAR \ + | RE_CONTEXT_INVALID_OPS | RE_UNMATCHED_RIGHT_PAREN_ORD) + +/* Differs from ..._POSIX_EXTENDED in that RE_CONTEXT_INDEP_OPS is + removed and RE_NO_BK_REFS is added. */ +#define RE_SYNTAX_POSIX_MINIMAL_EXTENDED \ + (_RE_SYNTAX_POSIX_COMMON | RE_CONTEXT_INDEP_ANCHORS \ + | RE_CONTEXT_INVALID_OPS | RE_NO_BK_BRACES \ + | RE_NO_BK_PARENS | RE_NO_BK_REFS \ + | RE_NO_BK_VBAR | RE_UNMATCHED_RIGHT_PAREN_ORD) +/* [[[end syntaxes]]] */ + +/* Maximum number of duplicates an interval can allow. Some systems + (erroneously) define this in other header files, but we want our + value, so remove any previous define. */ +#ifdef RE_DUP_MAX +# undef RE_DUP_MAX +#endif +/* If sizeof(int) == 2, then ((1 << 15) - 1) overflows. */ +#define RE_DUP_MAX (0x7fff) + + +/* POSIX `cflags' bits (i.e., information for `regcomp'). */ + +/* If this bit is set, then use extended regular expression syntax. + If not set, then use basic regular expression syntax. */ +#define REG_EXTENDED 1 + +/* If this bit is set, then ignore case when matching. + If not set, then case is significant. */ +#define REG_ICASE (REG_EXTENDED << 1) + +/* If this bit is set, then anchors do not match at newline + characters in the string. + If not set, then anchors do match at newlines. */ +#define REG_NEWLINE (REG_ICASE << 1) + +/* If this bit is set, then report only success or fail in regexec. + If not set, then returns differ between not matching and errors. */ +#define REG_NOSUB (REG_NEWLINE << 1) + + +/* POSIX `eflags' bits (i.e., information for regexec). */ + +/* If this bit is set, then the beginning-of-line operator doesn't match + the beginning of the string (presumably because it's not the + beginning of a line). + If not set, then the beginning-of-line operator does match the + beginning of the string. */ +#define REG_NOTBOL 1 + +/* Like REG_NOTBOL, except for the end-of-line. */ +#define REG_NOTEOL (1 << 1) + + +/* If any error codes are removed, changed, or added, update the + `re_error_msg' table in regex.c. */ +typedef enum +{ +#ifdef _XOPEN_SOURCE + REG_ENOSYS = -1, /* This will never happen for this implementation. */ +#endif + + REG_NOERROR = 0, /* Success. */ + REG_NOMATCH, /* Didn't find a match (for regexec). */ + + /* POSIX regcomp return error codes. (In the order listed in the + standard.) */ + REG_BADPAT, /* Invalid pattern. */ + REG_ECOLLATE, /* Not implemented. */ + REG_ECTYPE, /* Invalid character class name. */ + REG_EESCAPE, /* Trailing backslash. */ + REG_ESUBREG, /* Invalid back reference. */ + REG_EBRACK, /* Unmatched left bracket. */ + REG_EPAREN, /* Parenthesis imbalance. */ + REG_EBRACE, /* Unmatched \{. */ + REG_BADBR, /* Invalid contents of \{\}. */ + REG_ERANGE, /* Invalid range end. */ + REG_ESPACE, /* Ran out of memory. */ + REG_BADRPT, /* No preceding re for repetition op. */ + + /* Error codes we've added. */ + REG_EEND, /* Premature end. */ + REG_ESIZE, /* Compiled pattern bigger than 2^16 bytes. */ + REG_ERPAREN /* Unmatched ) or \); not returned from regcomp. */ +} reg_errcode_t; + +/* This data structure represents a compiled pattern. Before calling + the pattern compiler, the fields `buffer', `allocated', `fastmap', + `translate', and `no_sub' can be set. After the pattern has been + compiled, the `re_nsub' field is available. All other fields are + private to the regex routines. */ + +#ifndef RE_TRANSLATE_TYPE +# define RE_TRANSLATE_TYPE char * +#endif + +struct re_pattern_buffer +{ +/* [[[begin pattern_buffer]]] */ + /* Space that holds the compiled pattern. It is declared as + `unsigned char *' because its elements are + sometimes used as array indexes. */ + unsigned char *buffer; + + /* Number of bytes to which `buffer' points. */ + unsigned long int allocated; + + /* Number of bytes actually used in `buffer'. */ + unsigned long int used; + + /* Syntax setting with which the pattern was compiled. */ + reg_syntax_t syntax; + + /* Pointer to a fastmap, if any, otherwise zero. re_search uses + the fastmap, if there is one, to skip over impossible + starting points for matches. */ + char *fastmap; + + /* Either a translate table to apply to all characters before + comparing them, or zero for no translation. The translation + is applied to a pattern when it is compiled and to a string + when it is matched. */ + RE_TRANSLATE_TYPE translate; + + /* Number of subexpressions found by the compiler. */ + size_t re_nsub; + + /* Zero if this pattern cannot match the empty string, one else. + Well, in truth it's used only in `re_search_2', to see + whether or not we should use the fastmap, so we don't set + this absolutely perfectly; see `re_compile_fastmap' (the + `duplicate' case). */ + unsigned can_be_null : 1; + + /* If REGS_UNALLOCATED, allocate space in the `regs' structure + for `max (RE_NREGS, re_nsub + 1)' groups. + If REGS_REALLOCATE, reallocate space if necessary. + If REGS_FIXED, use what's there. */ +#define REGS_UNALLOCATED 0 +#define REGS_REALLOCATE 1 +#define REGS_FIXED 2 + unsigned regs_allocated : 2; + + /* Set to zero when `regex_compile' compiles a pattern; set to one + by `re_compile_fastmap' if it updates the fastmap. */ + unsigned fastmap_accurate : 1; + + /* If set, `re_match_2' does not return information about + subexpressions. */ + unsigned no_sub : 1; + + /* If set, a beginning-of-line anchor doesn't match at the + beginning of the string. */ + unsigned not_bol : 1; + + /* Similarly for an end-of-line anchor. */ + unsigned not_eol : 1; + + /* If true, an anchor at a newline matches. */ + unsigned newline_anchor : 1; + +/* [[[end pattern_buffer]]] */ +}; + +typedef struct re_pattern_buffer regex_t; + +/* Type for byte offsets within the string. POSIX mandates this. */ +typedef int regoff_t; + + +/* This is the structure we store register match data in. See + regex.texinfo for a full description of what registers match. */ +struct re_registers +{ + unsigned num_regs; + regoff_t *start; + regoff_t *end; +}; + + +/* If `regs_allocated' is REGS_UNALLOCATED in the pattern buffer, + `re_match_2' returns information about at least this many registers + the first time a `regs' structure is passed. */ +#ifndef RE_NREGS +# define RE_NREGS 30 +#endif + + +/* POSIX specification for registers. Aside from the different names than + `re_registers', POSIX uses an array of structures, instead of a + structure of arrays. */ +typedef struct +{ + regoff_t rm_so; /* Byte offset from string's start to substring's start. */ + regoff_t rm_eo; /* Byte offset from string's start to substring's end. */ +} regmatch_t; + +/* Declarations for routines. */ + +/* To avoid duplicating every routine declaration -- once with a + prototype (if we are ANSI), and once without (if we aren't) -- we + use the following macro to declare argument types. This + unfortunately clutters up the declarations a bit, but I think it's + worth it. */ + +/* Sets the current default syntax to SYNTAX, and return the old syntax. + You can also simply assign to the `re_syntax_options' variable. */ +extern reg_syntax_t re_set_syntax (reg_syntax_t syntax); + +/* Compile the regular expression PATTERN, with length LENGTH + and syntax given by the global `re_syntax_options', into the buffer + BUFFER. Return NULL if successful, and an error string if not. */ +extern const char *re_compile_pattern (const char *pattern, size_t length, + struct re_pattern_buffer *buffer); + + +/* Compile a fastmap for the compiled pattern in BUFFER; used to + accelerate searches. Return 0 if successful and -2 if was an + internal error. */ +extern int re_compile_fastmap (struct re_pattern_buffer *buffer); + + +/* Search in the string STRING (with length LENGTH) for the pattern + compiled into BUFFER. Start searching at position START, for RANGE + characters. Return the starting position of the match, -1 for no + match, or -2 for an internal error. Also return register + information in REGS (if REGS and BUFFER->no_sub are nonzero). */ +extern int re_search (struct re_pattern_buffer *buffer, const char *string, + int length, int start, int range, + struct re_registers *regs); + + +/* Like `re_search', but search in the concatenation of STRING1 and + STRING2. Also, stop searching at index START + STOP. */ +extern int re_search_2 (struct re_pattern_buffer *buffer, const char *string1, + int length1, const char *string2, int length2, + int start, int range, struct re_registers *regs, + int stop); + + +/* Like `re_search', but return how many characters in STRING the regexp + in BUFFER matched, starting at position START. */ +extern int re_match (struct re_pattern_buffer *buffer, const char *string, + int length, int start, struct re_registers *regs); + + +/* Relates to `re_match' as `re_search_2' relates to `re_search'. */ +extern int re_match_2 (struct re_pattern_buffer *buffer, const char *string1, + int length1, const char *string2, int length2, + int start, struct re_registers *regs, int stop); + + +/* Set REGS to hold NUM_REGS registers, storing them in STARTS and + ENDS. Subsequent matches using BUFFER and REGS will use this memory + for recording register information. STARTS and ENDS must be + allocated with malloc, and must each be at least `NUM_REGS * sizeof + (regoff_t)' bytes long. + + If NUM_REGS == 0, then subsequent matches should allocate their own + register data. + + Unless this function is called, the first search or match using + PATTERN_BUFFER will allocate its own register data, without + freeing the old data. */ +extern void re_set_registers (struct re_pattern_buffer *buffer, + struct re_registers *regs, + unsigned num_regs, regoff_t *starts, + regoff_t *ends); + +#if defined _REGEX_RE_COMP || defined _LIBC +# ifndef _CRAY +/* 4.2 bsd compatibility. */ +extern char *re_comp (const char *); +extern int re_exec (const char *); +# endif +#endif + +/* GCC 2.95 and later have "__restrict"; C99 compilers have + "restrict", and "configure" may have defined "restrict". */ +#ifndef __restrict +# if ! (2 < __GNUC__ || (2 == __GNUC__ && 95 <= __GNUC_MINOR__)) +# if defined restrict || 199901L <= __STDC_VERSION__ +# define __restrict restrict +# else +# define __restrict +# endif +# endif +#endif + +/* GCC 3.1 and later support declaring arrays as non-overlapping + using the syntax array_name[restrict] */ +#ifndef __restrict_arr +# if ! (3 < __GNUC__ || (3 == __GNUC__ && 1 <= __GNUC_MINOR__)) || defined (__GNUG__) +# define __restrict_arr +# else +# define __restrict_arr __restrict +# endif +#endif + +/* POSIX compatibility. */ +extern int regcomp (regex_t *__restrict __preg, + const char *__restrict __pattern, + int __cflags); + +#if (__GNUC__) +__extension__ +#endif +extern int regexec (const regex_t *__restrict __preg, + const char *__restrict __string, size_t __nmatch, + regmatch_t __pmatch[__restrict_arr], + int __eflags); + +extern size_t regerror (int __errcode, const regex_t *__preg, + char *__errbuf, size_t __errbuf_size); + +extern void regfree (regex_t *__preg); + + +#ifdef __cplusplus +} +#endif /* C++ */ + +#endif /* regex.h */ + +/* +Local variables: +make-backup-files: t +version-control: t +trim-versions-without-asking: nil +End: +*/ diff --git a/external/gpl3/gdb/dist/include/xtensa-config.h b/external/gpl3/gdb/dist/include/xtensa-config.h new file mode 100644 index 000000000000..30f4f41a2ac2 --- /dev/null +++ b/external/gpl3/gdb/dist/include/xtensa-config.h @@ -0,0 +1,177 @@ +/* Xtensa configuration settings. + Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 + Free Software Foundation, Inc. + Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 1 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XSHAL_USE_ABSOLUTE_LITERALS +#define XSHAL_USE_ABSOLUTE_LITERALS 0 + +#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 1 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 1 + +#undef XCHAL_HAVE_MUL32_HIGH +#define XCHAL_HAVE_MUL32_HIGH 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 1 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 1 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 1 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_THREADPTR +#define XCHAL_HAVE_THREADPTR 1 + +#undef XCHAL_HAVE_RELEASE_SYNC +#define XCHAL_HAVE_RELEASE_SYNC 1 + +#undef XCHAL_HAVE_S32C1I +#define XCHAL_HAVE_S32C1I 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 0 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_DFP_accel +#define XCHAL_HAVE_DFP_accel 0 +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + +#undef XCHAL_NUM_AREGS +#define XCHAL_NUM_AREGS 32 + +#undef XCHAL_HAVE_WIDE_BRANCHES +#define XCHAL_HAVE_WIDE_BRANCHES 0 + +#undef XCHAL_HAVE_PREDICTED_BRANCHES +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 16384 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 16384 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 32 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 32 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 5 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 5 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 1 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 1 + +#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 6 + + +#undef XCHAL_MAX_INSTRUCTION_SIZE +#define XCHAL_MAX_INSTRUCTION_SIZE 3 + +#undef XCHAL_INST_FETCH_WIDTH +#define XCHAL_INST_FETCH_WIDTH 4 + + +#undef XSHAL_ABI +#undef XTHAL_ABI_WINDOWED +#undef XTHAL_ABI_CALL0 +#define XSHAL_ABI XTHAL_ABI_WINDOWED +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + +#endif /* !XTENSA_CONFIG_H */ diff --git a/external/gpl3/gdb/dist/include/xtensa-isa-internal.h b/external/gpl3/gdb/dist/include/xtensa-isa-internal.h new file mode 100644 index 000000000000..6c727366bb5a --- /dev/null +++ b/external/gpl3/gdb/dist/include/xtensa-isa-internal.h @@ -0,0 +1,234 @@ +/* Internal definitions for configurable Xtensa ISA support. + Copyright 2003, 2004, 2005, 2008, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +#ifndef XTENSA_ISA_INTERNAL_H +#define XTENSA_ISA_INTERNAL_H + +/* Flags. */ + +#define XTENSA_OPERAND_IS_REGISTER 0x00000001 +#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002 +#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004 +#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008 + +#define XTENSA_OPCODE_IS_BRANCH 0x00000001 +#define XTENSA_OPCODE_IS_JUMP 0x00000002 +#define XTENSA_OPCODE_IS_LOOP 0x00000004 +#define XTENSA_OPCODE_IS_CALL 0x00000008 + +#define XTENSA_STATE_IS_EXPORTED 0x00000001 +#define XTENSA_STATE_IS_SHARED_OR 0x00000002 + +#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001 + +/* Function pointer typedefs */ +typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf); +typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf); +typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf); +typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf); +typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32); +typedef int (*xtensa_immed_decode_fn) (uint32 *); +typedef int (*xtensa_immed_encode_fn) (uint32 *); +typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32); +typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32); +typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf); +typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf); +typedef int (*xtensa_length_decode_fn) (const unsigned char *); + +typedef struct xtensa_format_internal_struct +{ + const char *name; /* Instruction format name. */ + int length; /* Instruction length in bytes. */ + xtensa_format_encode_fn encode_fn; + int num_slots; + int *slot_id; /* Array[num_slots] of slot IDs. */ +} xtensa_format_internal; + +typedef struct xtensa_slot_internal_struct +{ + const char *name; /* Not necessarily unique. */ + const char *format; + int position; + xtensa_get_slot_fn get_fn; + xtensa_set_slot_fn set_fn; + xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */ + xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */ + xtensa_opcode_decode_fn opcode_decode_fn; + const char *nop_name; +} xtensa_slot_internal; + +typedef struct xtensa_operand_internal_struct +{ + const char *name; + int field_id; + xtensa_regfile regfile; /* Register file. */ + int num_regs; /* Usually 1; 2 for reg pairs, etc. */ + uint32 flags; /* See XTENSA_OPERAND_* flags. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + +typedef struct xtensa_arg_internal_struct +{ + union { + int operand_id; /* For normal operands. */ + xtensa_state state; /* For stateOperands. */ + } u; + char inout; /* Direction: 'i', 'o', or 'm'. */ +} xtensa_arg_internal; + +typedef struct xtensa_iclass_internal_struct +{ + int num_operands; /* Size of "operands" array. */ + xtensa_arg_internal *operands; /* Array[num_operands]. */ + + int num_stateOperands; /* Size of "stateOperands" array. */ + xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */ + + int num_interfaceOperands; /* Size of "interfaceOperands". */ + xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */ +} xtensa_iclass_internal; + +typedef struct xtensa_opcode_internal_struct +{ + const char *name; /* Opcode mnemonic. */ + int iclass_id; /* Iclass for this opcode. */ + uint32 flags; /* See XTENSA_OPCODE_* flags. */ + xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */ + int num_funcUnit_uses; /* Number of funcUnit_use entries. */ + xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */ +} xtensa_opcode_internal; + +typedef struct xtensa_regfile_internal_struct +{ + const char *name; /* Full name of the regfile. */ + const char *shortname; /* Abbreviated name. */ + xtensa_regfile parent; /* View parent (or identity). */ + int num_bits; /* Width of the registers. */ + int num_entries; /* Number of registers. */ +} xtensa_regfile_internal; + +typedef struct xtensa_interface_internal_struct +{ + const char *name; /* Interface name. */ + int num_bits; /* Width of the interface. */ + uint32 flags; /* See XTENSA_INTERFACE_* flags. */ + int class_id; /* Class of related interfaces. */ + char inout; /* "i" or "o". */ +} xtensa_interface_internal; + +typedef struct xtensa_funcUnit_internal_struct +{ + const char *name; /* Functional unit name. */ + int num_copies; /* Number of instances. */ +} xtensa_funcUnit_internal; + +typedef struct xtensa_state_internal_struct +{ + const char *name; /* State name. */ + int num_bits; /* Number of state bits. */ + uint32 flags; /* See XTENSA_STATE_* flags. */ +} xtensa_state_internal; + +typedef struct xtensa_sysreg_internal_struct +{ + const char *name; /* Register name. */ + int number; /* Register number. */ + int is_user; /* Non-zero if a "user register". */ +} xtensa_sysreg_internal; + +typedef struct xtensa_lookup_entry_struct +{ + const char *key; + union + { + xtensa_opcode opcode; /* Internal opcode number. */ + xtensa_sysreg sysreg; /* Internal sysreg number. */ + xtensa_state state; /* Internal state number. */ + xtensa_interface intf; /* Internal interface number. */ + xtensa_funcUnit fun; /* Internal funcUnit number. */ + } u; +} xtensa_lookup_entry; + +typedef struct xtensa_isa_internal_struct +{ + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + + int num_formats; + xtensa_format_internal *formats; + xtensa_format_decode_fn format_decode_fn; + xtensa_length_decode_fn length_decode_fn; + + int num_slots; + xtensa_slot_internal *slots; + + int num_fields; + + int num_operands; + xtensa_operand_internal *operands; + + int num_iclasses; + xtensa_iclass_internal *iclasses; + + int num_opcodes; + xtensa_opcode_internal *opcodes; + xtensa_lookup_entry *opname_lookup_table; + + int num_regfiles; + xtensa_regfile_internal *regfiles; + + int num_states; + xtensa_state_internal *states; + xtensa_lookup_entry *state_lookup_table; + + int num_sysregs; + xtensa_sysreg_internal *sysregs; + xtensa_lookup_entry *sysreg_lookup_table; + + /* The current Xtensa ISA only supports 256 of each kind of sysreg so + we can get away with implementing lookups with tables indexed by + the register numbers. If we ever allow larger sysreg numbers, this + may have to be reimplemented. The first entry in the following + arrays corresponds to "special" registers and the second to "user" + registers. */ + int max_sysreg_num[2]; + xtensa_sysreg *sysreg_table[2]; + + int num_interfaces; + xtensa_interface_internal *interfaces; + xtensa_lookup_entry *interface_lookup_table; + + int num_funcUnits; + xtensa_funcUnit_internal *funcUnits; + xtensa_lookup_entry *funcUnit_lookup_table; + +} xtensa_isa_internal; + +extern int xtensa_isa_name_compare (const void *, const void *); + +extern xtensa_isa_status xtisa_errno; +extern char xtisa_error_msg[]; + +#endif /* !XTENSA_ISA_INTERNAL_H */ diff --git a/external/gpl3/gdb/dist/include/xtensa-isa.h b/external/gpl3/gdb/dist/include/xtensa-isa.h new file mode 100644 index 000000000000..c3c740da42f0 --- /dev/null +++ b/external/gpl3/gdb/dist/include/xtensa-isa.h @@ -0,0 +1,813 @@ +/* Interface definition for configurable Xtensa ISA support. + Copyright 2003, 2004, 2005, 2006, 2008, 2010 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Version number: This is intended to help support code that works with + versions of this library from multiple Xtensa releases. */ + +#define XTENSA_ISA_VERSION 7000 + +#ifndef uint32 +#define uint32 unsigned int +#endif + +/* This file defines the interface to the Xtensa ISA library. This + library contains most of the ISA-specific information for a + particular Xtensa processor. For example, the set of valid + instructions, their opcode encodings and operand fields are all + included here. + + This interface basically defines a number of abstract data types. + + . an instruction buffer - for holding the raw instruction bits + . ISA info - information about the ISA as a whole + . instruction formats - instruction size and slot structure + . opcodes - information about individual instructions + . operands - information about register and immediate instruction operands + . stateOperands - information about processor state instruction operands + . interfaceOperands - information about interface instruction operands + . register files - register file information + . processor states - internal processor state information + . system registers - "special registers" and "user registers" + . interfaces - TIE interfaces that are external to the processor + . functional units - TIE shared functions + + The interface defines a set of functions to access each data type. + With the exception of the instruction buffer, the internal + representations of the data structures are hidden. All accesses must + be made through the functions defined here. */ + +typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa; + + +/* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are + represented here using sequential integers beginning with 0. The + specific values are only fixed for a particular instantiation of an + xtensa_isa structure, so these values should only be used + internally. */ + +typedef int xtensa_opcode; +typedef int xtensa_format; +typedef int xtensa_regfile; +typedef int xtensa_state; +typedef int xtensa_sysreg; +typedef int xtensa_interface; +typedef int xtensa_funcUnit; + + +/* Define a unique value for undefined items. */ + +#define XTENSA_UNDEFINED -1 + + +/* Overview of using this interface to decode/encode instructions: + + Each Xtensa instruction is associated with a particular instruction + format, where the format defines a fixed number of slots for + operations. The formats for the core Xtensa ISA have only one slot, + but FLIX instructions may have multiple slots. Within each slot, + there is a single opcode and some number of associated operands. + + The encoding and decoding functions operate on instruction buffers, + not on the raw bytes of the instructions. The same instruction + buffer data structure is used for both entire instructions and + individual slots in those instructions -- the contents of a slot need + to be extracted from or inserted into the buffer for the instruction + as a whole. + + Decoding an instruction involves first finding the format, which + identifies the number of slots, and then decoding each slot + separately. A slot is decoded by finding the opcode and then using + the opcode to determine how many operands there are. For example: + + xtensa_insnbuf_from_chars + xtensa_format_decode + for each slot { + xtensa_format_get_slot + xtensa_opcode_decode + for each operand { + xtensa_operand_get_field + xtensa_operand_decode + } + } + + Encoding an instruction is roughly the same procedure in reverse: + + xtensa_format_encode + for each slot { + xtensa_opcode_encode + for each operand { + xtensa_operand_encode + xtensa_operand_set_field + } + xtensa_format_set_slot + } + xtensa_insnbuf_to_chars +*/ + + +/* Error handling. */ + +/* Error codes. The code for the most recent error condition can be + retrieved with the "errno" function. For any result other than + xtensa_isa_ok, an error message containing additional information + about the problem can be retrieved using the "error_msg" function. + The error messages are stored in an internal buffer, which should + not be freed and may be overwritten by subsequent operations. */ + +typedef enum xtensa_isa_status_enum +{ + xtensa_isa_ok = 0, + xtensa_isa_bad_format, + xtensa_isa_bad_slot, + xtensa_isa_bad_opcode, + xtensa_isa_bad_operand, + xtensa_isa_bad_field, + xtensa_isa_bad_iclass, + xtensa_isa_bad_regfile, + xtensa_isa_bad_sysreg, + xtensa_isa_bad_state, + xtensa_isa_bad_interface, + xtensa_isa_bad_funcUnit, + xtensa_isa_wrong_slot, + xtensa_isa_no_field, + xtensa_isa_out_of_memory, + xtensa_isa_buffer_overflow, + xtensa_isa_internal_error, + xtensa_isa_bad_value +} xtensa_isa_status; + +extern xtensa_isa_status +xtensa_isa_errno (xtensa_isa isa); + +extern char * +xtensa_isa_error_msg (xtensa_isa isa); + + + +/* Instruction buffers. */ + +typedef uint32 xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + + +/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */ + +extern int +xtensa_insnbuf_size (xtensa_isa isa); + + +/* Allocate an xtensa_insnbuf of the right size. */ + +extern xtensa_insnbuf +xtensa_insnbuf_alloc (xtensa_isa isa); + + +/* Release an xtensa_insnbuf. */ + +extern void +xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf); + + +/* Conversion between raw memory (char arrays) and our internal + instruction representation. This is complicated by the Xtensa ISA's + variable instruction lengths. When converting to chars, the buffer + must contain a valid instruction so we know how many bytes to copy; + thus, the "to_chars" function returns the number of bytes copied or + XTENSA_UNDEFINED on error. The "from_chars" function first reads the + minimal number of bytes required to decode the instruction length and + then proceeds to copy the entire instruction into the buffer; if the + memory does not contain a valid instruction, it copies the maximum + number of bytes required for the longest Xtensa instruction. The + "num_chars" argument may be used to limit the number of bytes that + can be read or written. Otherwise, if "num_chars" is zero, the + functions may read or write past the end of the code. */ + +extern int +xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn, + unsigned char *cp, int num_chars); + +extern void +xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn, + const unsigned char *cp, int num_chars); + + + +/* ISA information. */ + +/* Initialize the ISA information. */ + +extern xtensa_isa +xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p); + + +/* Deallocate an xtensa_isa structure. */ + +extern void +xtensa_isa_free (xtensa_isa isa); + + +/* Get the maximum instruction size in bytes. */ + +extern int +xtensa_isa_maxlength (xtensa_isa isa); + + +/* Decode the length in bytes of an instruction in raw memory (not an + insnbuf). This function reads only the minimal number of bytes + required to decode the instruction length. Returns + XTENSA_UNDEFINED on error. */ + +extern int +xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp); + + +/* Get the number of stages in the processor's pipeline. The pipeline + stage values returned by other functions in this library will range + from 0 to N-1, where N is the value returned by this function. + Note that the stage numbers used here may not correspond to the + actual processor hardware, e.g., the hardware may have additional + stages before stage 0. Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_isa_num_pipe_stages (xtensa_isa isa); + + +/* Get the number of various entities that are defined for this processor. */ + +extern int +xtensa_isa_num_formats (xtensa_isa isa); + +extern int +xtensa_isa_num_opcodes (xtensa_isa isa); + +extern int +xtensa_isa_num_regfiles (xtensa_isa isa); + +extern int +xtensa_isa_num_states (xtensa_isa isa); + +extern int +xtensa_isa_num_sysregs (xtensa_isa isa); + +extern int +xtensa_isa_num_interfaces (xtensa_isa isa); + +extern int +xtensa_isa_num_funcUnits (xtensa_isa isa); + + + +/* Instruction formats. */ + +/* Get the name of a format. Returns null on error. */ + +extern const char * +xtensa_format_name (xtensa_isa isa, xtensa_format fmt); + + +/* Given a format name, return the format number. Returns + XTENSA_UNDEFINED if the name is not a valid format. */ + +extern xtensa_format +xtensa_format_lookup (xtensa_isa isa, const char *fmtname); + + +/* Decode the instruction format from a binary instruction buffer. + Returns XTENSA_UNDEFINED if the format is not recognized. */ + +extern xtensa_format +xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn); + + +/* Set the instruction format field(s) in a binary instruction buffer. + All the other fields are set to zero. Returns non-zero on error. */ + +extern int +xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn); + + +/* Find the length (in bytes) of an instruction. Returns + XTENSA_UNDEFINED on error. */ + +extern int +xtensa_format_length (xtensa_isa isa, xtensa_format fmt); + + +/* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED + on error. */ + +extern int +xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt); + + +/* Get the opcode for a no-op in a particular slot. + Returns XTENSA_UNDEFINED on error. */ + +extern xtensa_opcode +xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot); + + +/* Get the bits for a specified slot out of an insnbuf for the + instruction as a whole and put them into an insnbuf for that one + slot, and do the opposite to set a slot. Return non-zero on error. */ + +extern int +xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf); + +extern int +xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf); + + + +/* Opcode information. */ + +/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + the name is not a valid opcode mnemonic. */ + +extern xtensa_opcode +xtensa_opcode_lookup (xtensa_isa isa, const char *opname); + + +/* Decode the opcode for one instruction slot from a binary instruction + buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is + illegal. */ + +extern xtensa_opcode +xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf); + + +/* Set the opcode field(s) for an instruction slot. All other fields + in the slot are set to zero. Returns non-zero if the opcode cannot + be encoded. */ + +extern int +xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc); + + +/* Get the mnemonic name for an opcode. Returns null on error. */ + +extern const char * +xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc); + + +/* Check various properties of opcodes. These functions return 0 if + the condition is false, 1 if the condition is true, and + XTENSA_UNDEFINED on error. The instructions are classified as + follows: + + branch: conditional branch; may fall through to next instruction (B*) + jump: unconditional branch (J, JX, RET*, RF*) + loop: zero-overhead loop (LOOP*) + call: unconditional call; control returns to next instruction (CALL*) + + For the opcodes that affect control flow in some way, the branch + target may be specified by an immediate operand or it may be an + address stored in a register. You can distinguish these by + checking if the instruction has a PC-relative immediate + operand. */ + +extern int +xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc); + +extern int +xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc); + +extern int +xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc); + +extern int +xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc); + + +/* Find the number of ordinary operands, state operands, and interface + operands for an instruction. These return XTENSA_UNDEFINED on + error. */ + +extern int +xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc); + +extern int +xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc); + +extern int +xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc); + + +/* Get functional unit usage requirements for an opcode. Each "use" + is identified by a pair. The + "num_funcUnit_uses" function returns the number of these "uses" or + XTENSA_UNDEFINED on error. The "funcUnit_use" function returns + a pointer to a "use" pair or null on error. */ + +typedef struct xtensa_funcUnit_use_struct +{ + xtensa_funcUnit unit; + int stage; +} xtensa_funcUnit_use; + +extern int +xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc); + +extern xtensa_funcUnit_use * +xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u); + + + +/* Operand information. */ + +/* Get the name of an operand. Returns null on error. */ + +extern const char * +xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Some operands are "invisible", i.e., not explicitly specified in + assembly language. When assembling an instruction, you need not set + the values of invisible operands, since they are either hardwired or + derived from other field values. The values of invisible operands + can be examined in the same way as other operands, but remember that + an invisible operand may get its value from another visible one, so + the entire instruction must be available before examining the + invisible operand values. This function returns 1 if an operand is + visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note + that whether an operand is visible is orthogonal to whether it is + "implicit", i.e., whether it is encoded in a field in the + instruction. */ + +extern int +xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Check if an operand is an input ('i'), output ('o'), or inout ('m') + operand. Note: The output operand of a conditional assignment + (e.g., movnez) appears here as an inout ('m') even if it is declared + in the TIE code as an output ('o'); this allows the compiler to + properly handle register allocation for conditional assignments. + Returns 0 on error. */ + +extern char +xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Get and set the raw (encoded) value of the field for the specified + operand. The "set" function does not check if the value fits in the + field; that is done by the "encode" function below. Both of these + functions return non-zero on error, e.g., if the field is not defined + for the specified slot. */ + +extern int +xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32 *valp); + +extern int +xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32 val); + + +/* Encode and decode operands. The raw bits in the operand field may + be encoded in a variety of different ways. These functions hide + the details of that encoding. The result values are returned through + the argument pointer. The return value is non-zero on error. */ + +extern int +xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32 *valp); + +extern int +xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32 *valp); + + +/* An operand may be either a register operand or an immediate of some + sort (e.g., PC-relative or not). The "is_register" function returns + 0 if the operand is an immediate, 1 if it is a register, and + XTENSA_UNDEFINED on error. The "regfile" function returns the + regfile for a register operand, or XTENSA_UNDEFINED on error. */ + +extern int +xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd); + +extern xtensa_regfile +xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Register operands may span multiple consecutive registers, e.g., a + 64-bit data type may occupy two 32-bit registers. Only the first + register is encoded in the operand field. This function specifies + the number of consecutive registers occupied by this operand. For + non-register operands, the return value is undefined. Returns + XTENSA_UNDEFINED on error. */ + +extern int +xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Some register operands do not completely identify the register being + accessed. For example, the operand value may be added to an internal + state value. By definition, this implies that the corresponding + regfile is not allocatable. Unknown registers should generally be + treated with worst-case assumptions. The function returns 0 if the + register value is unknown, 1 if known, and XTENSA_UNDEFINED on + error. */ + +extern int +xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* Check if an immediate operand is PC-relative. Returns 0 for register + operands and non-PC-relative immediates, 1 for PC-relative + immediates, and XTENSA_UNDEFINED on error. */ + +extern int +xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* For PC-relative offset operands, the interpretation of the offset may + vary between opcodes, e.g., is it relative to the current PC or that + of the next instruction? The following functions are defined to + perform PC-relative relocations and to undo them (as in the + disassembler). The "do_reloc" function takes the desired address + value and the PC of the current instruction and sets the value to the + corresponding PC-relative offset (which can then be encoded and + stored into the operand field). The "undo_reloc" function takes the + unencoded offset value and the current PC and sets the value to the + appropriate address. The return values are non-zero on error. Note + that these functions do not replace the encode/decode functions; the + operands must be encoded/decoded separately and the encode functions + are responsible for detecting invalid operand values. */ + +extern int +xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32 *valp, uint32 pc); + +extern int +xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32 *valp, uint32 pc); + + + +/* State Operands. */ + +/* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED + on error. */ + +extern xtensa_state +xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp); + + +/* Check if a state operand is an input ('i'), output ('o'), or inout + ('m') operand. Returns 0 on error. */ + +extern char +xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp); + + + +/* Interface Operands. */ + +/* Get the external interface accessed by an interface operand. + Returns XTENSA_UNDEFINED on error. */ + +extern xtensa_interface +xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc, + int ifOp); + + + +/* Register Files. */ + +/* Regfiles include both "real" regfiles and "views", where a view + allows a group of adjacent registers in a real "parent" regfile to be + viewed as a single register. A regfile view has all the same + properties as its parent except for its (long) name, bit width, number + of entries, and default ctype. You can use the parent function to + distinguish these two classes. */ + +/* Look up a regfile by either its name or its abbreviated "short name". + Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function + ignores "view" regfiles since they always have the same shortname as + their parents. */ + +extern xtensa_regfile +xtensa_regfile_lookup (xtensa_isa isa, const char *name); + +extern xtensa_regfile +xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname); + + +/* Get the name or abbreviated "short name" of a regfile. + Returns null on error. */ + +extern const char * +xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf); + +extern const char * +xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf); + + +/* Get the parent regfile of a "view" regfile. If the regfile is not a + view, the result is the same as the input parameter. Returns + XTENSA_UNDEFINED on error. */ + +extern xtensa_regfile +xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf); + + +/* Get the bit width of a regfile or regfile view. + Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf); + + +/* Get the number of regfile entries. Returns XTENSA_UNDEFINED on + error. */ + +extern int +xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf); + + + +/* Processor States. */ + +/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */ + +extern xtensa_state +xtensa_state_lookup (xtensa_isa isa, const char *name); + + +/* Get the name for a processor state. Returns null on error. */ + +extern const char * +xtensa_state_name (xtensa_isa isa, xtensa_state st); + + +/* Get the bit width for a processor state. + Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_state_num_bits (xtensa_isa isa, xtensa_state st); + + +/* Check if a state is exported from the processor core. Returns 0 if + the condition is false, 1 if the condition is true, and + XTENSA_UNDEFINED on error. */ + +extern int +xtensa_state_is_exported (xtensa_isa isa, xtensa_state st); + + +/* Check for a "shared_or" state. Returns 0 if the condition is false, + 1 if the condition is true, and XTENSA_UNDEFINED on error. */ + +extern int +xtensa_state_is_shared_or (xtensa_isa isa, xtensa_state st); + + + +/* Sysregs ("special registers" and "user registers"). */ + +/* Look up a register by its number and whether it is a "user register" + or a "special register". Returns XTENSA_UNDEFINED if the sysreg does + not exist. */ + +extern xtensa_sysreg +xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user); + + +/* Check if there exists a sysreg with a given name. + If not, this function returns XTENSA_UNDEFINED. */ + +extern xtensa_sysreg +xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name); + + +/* Get the name of a sysreg. Returns null on error. */ + +extern const char * +xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg); + + +/* Get the register number. Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg); + + +/* Check if a sysreg is a "special register" or a "user register". + Returns 0 for special registers, 1 for user registers and + XTENSA_UNDEFINED on error. */ + +extern int +xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg); + + + +/* Interfaces. */ + +/* Find an interface by name. The return value is XTENSA_UNDEFINED if + the specified interface is not found. */ + +extern xtensa_interface +xtensa_interface_lookup (xtensa_isa isa, const char *ifname); + + +/* Get the name of an interface. Returns null on error. */ + +extern const char * +xtensa_interface_name (xtensa_isa isa, xtensa_interface intf); + + +/* Get the bit width for an interface. + Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf); + + +/* Check if an interface is an input ('i') or output ('o') with respect + to the Xtensa processor core. Returns 0 on error. */ + +extern char +xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf); + + +/* Check if accessing an interface has potential side effects. + Currently "data" interfaces have side effects and "control" + interfaces do not. Returns 1 if there are side effects, 0 if not, + and XTENSA_UNDEFINED on error. */ + +extern int +xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf); + + +/* Some interfaces may be related such that accessing one interface + has side effects on a set of related interfaces. The interfaces + are partitioned into equivalence classes of related interfaces, and + each class is assigned a unique identifier number. This function + returns the class identifier for an interface, or XTENSA_UNDEFINED + on error. These identifiers can be compared to determine if two + interfaces are related; the specific values of the identifiers have + no particular meaning otherwise. */ + +extern int +xtensa_interface_class_id (xtensa_isa isa, xtensa_interface intf); + + + +/* Functional Units. */ + +/* Find a functional unit by name. The return value is XTENSA_UNDEFINED if + the specified unit is not found. */ + +extern xtensa_funcUnit +xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname); + + +/* Get the name of a functional unit. Returns null on error. */ + +extern const char * +xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun); + + +/* Functional units may be replicated. See how many instances of a + particular function unit exist. Returns XTENSA_UNDEFINED on error. */ + +extern int +xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun); + + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ diff --git a/external/gpl3/gdb/dist/libiberty/.gitignore b/external/gpl3/gdb/dist/libiberty/.gitignore new file mode 100644 index 000000000000..ca2fba5cc3b6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/.gitignore @@ -0,0 +1,2 @@ +/required-list +/xhost-mkfrag diff --git a/external/gpl3/gdb/dist/libiberty/COPYING.LIB b/external/gpl3/gdb/dist/libiberty/COPYING.LIB new file mode 100644 index 000000000000..ae23fcfda2da --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/COPYING.LIB @@ -0,0 +1,504 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 2.1, February 1999 + + Copyright (C) 1991, 1999 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +[This is the first released version of the Lesser GPL. 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See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! + + diff --git a/external/gpl3/gdb/dist/libiberty/ChangeLog b/external/gpl3/gdb/dist/libiberty/ChangeLog new file mode 100644 index 000000000000..f2b6ed409930 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/ChangeLog @@ -0,0 +1,8402 @@ +2011-07-02 Jan Kratochvil + + PR debug/49408 + * cp-demangle.c (d_print_comp): Suppress argument list for function + references by the '&' unary operator. Keep also already processed + variant without the argument list. Suppress argument list types for + function call used in an expression. + * testsuite/demangle-expected: Fix excessive argument list types in + `test for typed function in decltype'. New testcase for no argument + list types printed. 3 new testcases for function references by the + '&' unary operator.. + +2011-07-02 Jan Kratochvil + + * cp-demangle.c (d_print_comp) : + Suppress d_print_mod for DMGL_RET_POSTFIX. + * testsuite/demangle-expected: New testcases for --ret-postfix. + +2011-07-02 Jan Kratochvil + + * cp-demangle.c (d_print_comp) : Do + not pass DMGL_RET_POSTFIX or DMGL_RET_DROP. Support DMGL_RET_DROP. + * testsuite/demangle-expected: New testcases for --ret-drop. + * testsuite/test-demangle.c: Document --ret-drop in a comment. + (main): New variable ret_drop, fill it, call cplus_demangle with it. + +2011-07-02 Jan Kratochvil + + * cp-demangle.c (struct d_print_info): Remove field options. + (d_print_init): Remove parameter options. + (cplus_demangle_print_callback): Update all the callers. + (d_print_comp, d_print_mod_list, d_print_mod, d_print_function_type) + (d_print_array_type, d_print_expr_op, d_print_cast, d_print_subexpr): + Add parameter options, update all the callers. + +2011-03-31 Tristan Gingold + + * makefile.vms (OBJS): Add filename_cmp.obj + +2011-02-28 Kai Tietz + + * filename_cmp.c (filename_ncmp): New function. + * functions.texi: Regenerated. + +2011-02-03 Ralf Wildenhues + + * splay-tree.c: Escape wrapping newlines in texinfo markup + with '@', to fix function declaration output rendering. + * gather-docs: Relax and improve macro name matching to actually + match all current names and to allow input line wrapping. + * bsearch.c, concat.c, crc32.c, fnmatch.txh, fopen_unlocked.c, + hashtab.c, insque.c, make-relative-prefix.c, memchr.c, memcmp.c, + memcpy.c, memmem.c, memmove.c, mempcpy.c, memset.c, + pexecute.txh, random.c, setenv.c, setproctitle.c, + simple-object.txh, snprintf.c, stpncpy.c, strncmp.c, strtod.c, + strtol.c, vasprintf.c, vprintf.c, vsnprintf.c, xmemdup.c: + Wrap long texinfo input lines. + * functions.texi: Regenerate. + +2011-01-18 Mike Frysinger + + * .gitignore: New file. + +2010-12-08 Doug Evans + + * splay-tree.c (splay_tree_foreach_helper): Remove arg `sp', + all callers updated. Rewrite to be non-recursive. + +2010-11-29 Rainer Orth + + * setproctitle.c [HAVE_SYS_PRCTL_H]: Include . + +2010-11-20 Anthony Green + + * configure.ac: Turn PR_SET_NAME link test into a test for + sys/prctl.h. + * configure, config.in: Rebuilt. + * setproctitle.c: Test for HAVE_SYS_PRCTL_H. + (setproctitle) Test for PR_SET_NAME definition. + +2010-11-20 Ralf Wildenhues + + PR other/46202 + * Makefile.in (install-strip): New phony target. + (install): Also mark as phony. + +2010-11-16 Ian Lance Taylor + + * simple-object.c (simple_object_attributes_merge): Rename from + simple_object_attributes_compare. Call merge field. + * simple-object-common.h (struct simple_object_functions): Rename + attributes_compare field to attribute_merge. + * simple-object-elf.c (EM_SPARC): Define. + (EM_SPARC32PLUS): Define. + (simple_object_elf_attributes_merge): Renamed from + simple_object_elf_attributes_compare. Permit EM_SPARC and + EM_SPARC32PLUS objects to be merged. + (simple_object_elf_functions): Update function name. + * simple-object-coff.c (simple_object_coff_attributes_merge): + Rename from simple_object_coff_attributes_compare. + (simple_object_coff_functions): Update function name. + * simple-object-mach-o.c (simple_object_mach_o_attributes_merge): + Renamed from simple_object_mach_o_attributes_compare. + (simple_object_mach_o_functions): Update function name. + +2010-11-16 H.J. Lu + + PR other/42670 + PR binutils/11137 + * cp-demangle.c (d_make_demangle_mangled_name): New. + (d_demangle_callback): Use it on DCT_GLOBAL_XTORS. + + * testsuite/demangle-expected: Updated. + +2010-11-14 Kai Tietz + + * simple-object-coff.c (simple_object_coff_read_strtab): Fix reading + offset. + +2010-11-12 Ian Lance Taylor + + PR other/46332 + * cp-demangle.c (d_print_function_type): Don't print parentheses + if there are no modifiers to print. + * testsuite/demangle-expected: Tweak one test case, add another. + +2010-11-04 Richard Henderson + + * configure.ac (AC_CHECK_HEADERS): Add process.h. + (checkfuncs): Add dup3, spawnve, spawnvpe; sort the list. + (AC_CHECK_FUNCS): Add dup3, spawnve, spawnvpe. + * configure, config.in: Rebuild. + * pex-unix.c [HAVE_SPAWNVE] (pex_unix_exec_child): New function. + [HAVE_SPAWNVE] (save_and_install_fd, restore_fd): New functions. + +2010-11-02 Ian Lance Taylor + Dave Korn + Iain Sandoe + + * simple-object.c: New file. + * simple-object-common.h: New file. + * simple-object-elf.c: New file. + * simple-object-mach-o.c: New file. + * simple-object-coff.c: New file. + * simple-object.txh: New file. + * configure.ac: Add AC_TYPE_SSIZE_T. + * Makefile.in: Rebuild dependencies. + (CFILES): Add simple-object.c, simple-object-coff, + simple-object-elf.c, and simple-object-mach-o.c. + (REQUIRED_OFILES): Add corresponding object files. + * configure: Rebuild. + * config.in: Rebuild. + * functions.texi: Rebuild. + +2010-10-29 Ian Lance Taylor + + * setproctitle.c: Add space after function name in @deftypefn + comment. + * functions.texi: Rebuild. + +2010-10-26 Ralf Wildenhues + + * aclocal.m4 (AC_LANG_FUNC_LINK_TRY(C)): Delete. + * configure: Regenerate. + +2010-10-07 Andi Kleen + + * configure: Regenerate. + * configure.ac: Turn PR_SET_NAME check into link check. + +2010-10-06 Andi Kleen + + * Makefile.in (CFILES): Add setproctitle. + (CONFIGURED_OFILES): Add setproctitle. + (setproctitle): Add rule. + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Add checks for prctl PR_SET_NAME and setproctitle. + * setproctitle.c: Add file. + * functions.texi: Regenerate. + +2010-09-22 Tristan Gingold + + * cplus-dem.c (ada_demangle): Add comments. + Handle stream and controlled type operations. + Decoding of some uppercase letters moved before separators. + * testsuite/demangle-expected: Add tests. + +2010-09-10 James Lyon + + http://sourceware.org/bugzilla/show_bug.cgi?id=11572 + * cp-demangle.c (d_find_pack): Add case for + DEMANGLE_COMPONENT_LAMBDA. + * testsuite/demangle-expected: Add regression test. + +2010-09-08 Tristan Gingold + + PR 44001 + * maint-tool (missing): Fix pattern for object file. + (deps): Use $(objext) for object extension. + * Makefile.in (objext): New variable. + Replace all occurences of .o with .$(objext) + Regenerate with maint-deps + * configure.ac (pexecute): Set to the basename. + * configure: Regenerate. + +2010-08-20 Maciej W. Rozycki + + * pex-common.c (pex_read_err): Set stderr_pipe to -1 if a + corresponding stream has been opened. + (pex_free): Close pipe file descriptors corresponding to child's + stdout and stderr before waiting. + +2010-08-13 Nick Clifton + + * argv.c (expandargv): Limit the number of times that response + files are opened in order to prevent infinite recursion. + +2010-07-21 Pascal Obry + + * make-temp-file.c (choose_tmpdir): Append a dot to P_tmpdir if needed. + +2010-07-06 Ken Werner + + * floatformat.c (floatformat_ieee_half_big): New variable. + (floatformat_ieee_half_little): Likewise. + +2010-06-14 Gerald Pfeifer + + * libiberty.texi: Remove reference to GCC 3 and 2001 (thrice). + Update copyright years. + Move to GFDL 1.3. + +2010-06-10 Jakub Jelinek + + PR other/43838 + * cp-demangle.c (struct d_print_info): Add flush_count field. + (d_print_init): Initialize it to 0. + (d_print_flush): Increment it. + (d_print_comp): If needed flush before appending ", ". Only + decrement dpi->len if no flushes happened during the recursive + call. + * testsuite/demangle-expected: Add a test for this. + +2010-06-08 Laurynas Biveinis + + * splay-tree.c: Update copyright years. + (splay_tree_new_typed_alloc): New. + (splay_tree_new_with_allocator): Use it. + + * hashtab.c: Update copyright years. + (htab_create_typed_alloc): New. + (htab_create_alloc): Use it. + + * functions.texi: Regenerate. + +2010-06-03 Joern Rennecke + Ralf Wildenhues + + PR bootstrap/42798 + * configure.ac: Check for declaration of 'basename(char *)'. + * configure: Regenerate. + +2010-05-26 Kai Tietz + + * testsuite/demangle-expected: Add tests for __int128 + and unsigned __int128 types. + +2010-05-06 Magnus Fromreide + Jason Merrill + + * cp-demangle.c (cplus_demangle_builtin_types): Add nullptr. + (cplus_demangle_type): Handle nullptr. + * testsuite/demangle-expected: Test it. + +2010-04-23 Pedro Alves + + * lbasename.c (lbasename): Split into ... + (unix_lbasename, dos_basename): ... these. + (lbasename): ... and reimplement on top of them. + * Makefile.in (lbasename.o): Add dependency on + $(INCDIR)/filenames.h. + +2010-04-07 Jakub Jelinek + + * regex.c (byte_re_match_2_internal): Avoid set but not used + warning. + +2010-03-22 Jason Merrill + + * cp-demangle.c (d_print_mod): Use () rather than [] for vectors. + +2010-03-01 Ralf Wildenhues + + * Makefile.in (all): Do not use exec. + +2010-02-04 Tom Tromey + + * testsuite/demangle-expected: Add missing --format=gnu-v3. + +2010-02-03 Jason Merrill + + * cp-demangle.c (d_expression): Handle dependent operator name. + + PR c++/12909 + * cp-demangle.c (d_number_component, d_vector_type): New. + (cplus_demangle_type, d_print_comp, d_print_mod): Handle vectors. + +2010-01-25 Ian Lance Taylor + + * cp-demangle.c (cplus_demangle_type): Check for invalid type + after "DF". + * testsuite/demangle-expected: Add test. + +2010-01-20 Jason Merrill + + PR c++/42338 + * cp-demangle.c (d_print_comp): Fix array index printing. + +2010-01-11 Tristan Gingold + + * cplus-dem.c (ada_demangle): Remove prototype. + (grow_vect): Removed. + (ada_demangle): Rewritten. + (cplus_demangle): Fix indentation. + * testsuite/demangle-expected: Add tests for Ada. + +2010-01-09 Ian Lance Taylor + + PR other/42230 + * cp-demangle.c (d_demangle): Return dgs.alc on success. + +2010-01-04 Nobuhiro Iwamatsu + + PR target/42316 + * configure.ac (PICFLAG): Use -fPIC on SH hosts. + * configure: Regenerate. + +2009-12-07 Doug Evans + + * pex-unix.c (pex_unix_exec_child): Save/restore environ. + +2009-11-26 Ben Elliston + + * configure.ac (AC_CHECK_FUNCS): Sort into alphabetic order. + * configure: Regenerate. + +2009-11-25 Ben Elliston + + * functions.texi: Rebuild. + +2009-11-25 Manuel Lopez-Ibanez + Ben Elliston + + * README: Mention changes to Makefile.in and functions.texi. + * gather-docs: Mention 'make stamp-functions' in the header. + +2009-11-23 Ben Elliston + Ian Lance Taylor + + * pex-unix.c (pex_child_error): Improve warning avoidance by + checking the results of write(3) and exiting with -2 if any write + returns a negative value. + +2009-11-22 Steve Ward + + * dyn-string.c (dyn_string_append_char): Fix typo in comment. + +2009-11-20 Ben Elliston + + * pex-unix.c (pex_child_error): Define writeerr macro to avoid + unused result warnings from write(3) calls. Undefine writeerr + after all uses. + +2009-10-08 Daniel Gutson + Daniel Jacobowitz + Pedro Alves + + libiberty/ + * argv.c (consume_whitespace): New function. + (only_whitespace): New function. + (buildargv): Always use ISSPACE by calling consume_whitespace. + (expandargv): Skip empty files. Do not stop at the first empty + argument (calling only_whitespace).. + * testsuite/test-expandargv.c: (test_data): Test empty lines + and empty arguments. + (run_tests): Fix false positives due to shorter arguments. + +2009-09-30 Martin Thuresson + + * regex.c (byte_re_match_2_internal): Split declaration and + assignment to avoid -Wc++-compat warning due to goto. + +2009-09-29 Jason Merrill + + * Makefile.in: Enable demangle target. + * cp-demangle.c (d_lambda, d_unnamed_type, d_make_default_arg): New. + (d_name, d_prefix, d_unqualified_name, d_local_name): Handle lambdas. + (d_parmlist): Factor out from d_bare_function_type. + (d_compact_number): Factor out from d_template_param and d_expression. + (d_append_num): Factor out from d_print_comp. + (d_print_comp, d_print_mod_list): Handle lambdas. + * testsuite/demangle-expected: Add lambda tests. + +2009-09-23 Matthew Gingell + + * cplus-dem.c (ada_demangle): Ensure demangled is freed. + +2009-09-22 Ozkan Sezer + + * choose-temp.c: Include unistd.h for mingw targets. + +2009-09-16 Rainer Orth + + * hashtab.c [HAVE_INTTYPES_H]: Include . + +2009-09-15 Tristan Gingold + + * config.h-vms (intptr_t): Define to compile hashtab.c + +2009-09-04 Ozkan Sezer + + PR target/39065 + * configure.ac: Replace AC_CHECK_TYPE() for intptr_t and uintptr_t + with AC_TYPE_INTPTR_T and AC_TYPE_UINTPTR_T. + * config.in: Regenerated. + * configure: Regenerated. + +2009-09-03 Ozkan Sezer + + PR target/39065 + * configure.ac: Also check for intptr_t. + * config.h.in: Regenerated. + * configure: Regenerated. + * hashtab.c (hash_pointer): Cast the pointer argument to intptr_t + instead of of long. + +2009-09-02 Tristan Gingold + + * vmsbuild.com: Removed as unused and superceeded by makefile.vms. + * makefile.vms: Ported to Itanium VMS. Remove useless targets and + dependencies. Remove unused FORMAT variable. + * configure.com: New file to create build.com DCL script for + Itanium VMS or Alpha VMS. + +2009-08-24 Ralf Wildenhues + + * configure.ac (AC_PREREQ): Bump to 2.64. + +2009-08-23 H.J. Lu + + PR ld/10536 + * Makefile.in (install-html-recursive): Removed. + +2009-08-22 Ralf Wildenhues + + * config.in: Regenerate. + * configure: Regenerate. + +2009-07-30 Ralf Wildenhues + + * Makefile.in (AUTOCONF, configure_deps): New variables. + ($(srcdir)/configure): New rule, active only in maintainer mode. + +2009-07-29 Douglas B Rupp + + * make-temp-file.c (choose_tmpdir): Try standard temp logical on VMS. + +2009-07-27 Douglas B Rupp + + * pex-unix.c (vfork): Remove VMS specific definition (get from header + file instead). + (to_ptr32): New function. + (pex_unix_exec_child): Use it. + +2009-07-24 Ian Lance Taylor + + PR bootstrap/40854 + * crc32.c (xcrc32): Rename from crc32. + +2009-07-24 Ian Lance Taylor + + * crc32.c: New file. + * Makefile.in: Rebuild dependencies. + (CFILES): Add crc32.c. + (REQUIRED_OFILES): Add ./crc32.o. + * functions.texi: Rebuild. + +2009-07-17 Jan Kratochvil + + * cp-demangle.c (d_print_comp ) + (d_print_comp ) + (d_make_comp + + * hashtab.c (htab_traverse): Don't call htab_expand for + nearly empty hashtabs with sizes 7, 13 or 31. + +2009-06-16 Nick Clifton + + PR 10197 + * testsuite/test-demangle.c: Rename getline to get_line to avoid + conflicts with system function of the same name. + +2009-05-30 Eli Zaretskii + + * snprintf.c: Doc fix. + + * vsnprintf.c: Doc fix. + +2009-05-29 Kai Tietz + + * pex-win32.c (pex_win32_fdopenr): Set INHERIT to false. + +2009-05-29 Michael Matz + + * fibheap.c (fibheap_replace_key_data): Make sure we don't early + out when forcing the minimum. + (fibheap_delete_node): Assert that we managed to force the minimum. + +2009-05-25 Tristan Gingold + + * config.h-vms: Rewritten. Define configure macros. + Use DEC-C builtin alloca. + + * makefile.vms (OBJS): Update list. + (OPT): New variable. + (CFLAGS): Update compilation flags. + (libiberty.olb): Do not depend on alloca-conf.h anymore. + +2009-05-19 Ian Lance Taylor + Ben Elliston + + * cp-demangle.c (cplus_demangle_fill_ctor): Fix logic bug. + (cplus_demangle_fill_dtor): Likewise. + +2009-05-17 Julian Brown + + * pex-win32.c (pex_win32_exec_child): Fix logic to avoid closing + standard handles (stdin, stdout, stderr) in parent. + +2009-04-29 Julian Brown + + * pex-win32.c (pex_win32_pipe): Add _O_NOINHERIT. + (pex_win32_exec_child): Ensure each process has only one handle open + on pipe endpoints. Close standard input after creating child for + symmetry with standard output/standard error. + +2009-04-25 Eli Zaretskii + + * Makefile.in (needed-list): Target removed (not used in GCC + 3.0 and later). All references deleted. + (mostlyclean): Remove references to needed.awk and needed2.awk. + +2009-04-14 Eli Zaretskii + + * configure.ac (setobjs, msdosdjgpp): Move a-priori setting of + existing and required library functions to with_target_subdir + section, so that the native build does detect them at configure + time. + * configure: Regenerated. + +2009-04-13 Ozkan Sezer + + PR target/39397 + * pex-common.h (struct pex_obj): Store pid values as pid_t, + not as long (members *children and (*wait)) + * pex-common.c (pex_run_in_environment): Likewise. + * pex-win32.c (pex_win32_wait): Return pid_t and properly check + returned pid value. + * pex-djgpp.c (pex_djgpp_wait): Return pid_t. + * pex-msdos.c (pex_msdos_wait): Likewise. + +2009-04-07 Arnaud Patard + + * libiberty/configure.ac: Fix Linux/MIPS matching rule. + * libiberty/configure: Regenerate. + +2009-03-27 Ian Lance Taylor + + * memmem.c: New file, from gnulib. + * configure.ac: Add memmem to list of functions provided if they + are not available on the host. + * Makefile.in: Rebuild dependencies. + (CFILES): Add memmem.c. + (CONFIGURED_OFILES): Add memmem.o. + * configure, config.in, functions.texi: Rebuild. + +2009-03-23 Jason Merrill + + * cp-demangle.c (d_expression): Handle pack expansion. + (d_find_pack): Handle DEMANGLE_COMPONENT_FUNCTION_PARAM. + (d_print_subexpr): Don't wrap function parms in (). + (d_print_comp) [DEMANGLE_COMPONENT_PACK_EXPANSION]: Handle + not finding a pack. + +2009-03-17 Jason Merrill + + * cp-demangle.c (d_make_function_param): new fn. + (cplus_demangle_mangled_name): Work around abi v2 bug. + (d_expr_primary): Likewise. + (cplus_demangle_operators): Add alignof ops. + (d_expression): Handle function parameters and conversions + with other than 1 operand. + (d_print_comp): Handle function parameters. Fix bug with + function used in type of function. + * testsuite/demangle-expected: Update tests. + +2009-02-21 Mark Mitchell + + * make-temp-file.c (): Include on Windows. + (choose_tmpdir): On Windows, use GetTempPath. + +2009-01-18 Dave Korn + + * configure.ac (funcs, vars, checkfuncs): Don't munge on Cygwin, + as it no longer shares libiberty object files. + * configure: Regenerated. + +2009-01-07 Jason Merrill + + * cp-demangle.c (d_expression): Remove mangling for zero-op casts. + +2009-01-06 Ben Elliston + + * cp-demangle.c (cplus_demangle_type): Return NULL if the + character following a 'D' cannot be recognised. + +2008-12-18 Jason Merrill + + PR c++/38561 + * cp-demangle.c (d_expression, d_print_comp): Revert + cast changes. + +2008-12-17 Jason Merrill + + * cp-demangle.c (d_expression): Handle rvalue stubs too. + [DEMANGLE_COMPONENT_CAST]: Update mangling. + (d_print_comp): Avoid extra ", " with empty template argument packs. + Remove handling for obsolete T() mangling. + +2008-12-10 Jason Merrill + + * cp-demangle.c (cplus_demangle_type): Support fixed-point types. + (d_print_comp, d_dump): Likewise. + +2008-10-22 Daniel Jacobowitz + + * Makefile.in (CPPFLAGS): Define. + (FLAGS_TO_PASS, COMPILE.c): Add CPPFLAGS. + +2008-10-15 Paolo Bonzini + + PR bootstrap/37137 + * Makefile.in (LIBCFLAGS): Remove. + (FLAGS_TO_PASS): Don't mention it. + (COMPILE.c, MULTIOSDIR): Replace it with CFLAGS. + +2008-10-08 David Edelsohn + + * xstrdup.c: Include after "config.h" + +2008-10-07 Jan Kratochvil + + * configure.ac: Call AC_SYS_LARGEFILE. + * config.in: Regenerated. + * configure: Likewise. + +2008-10-06 Jason Merrill + + * cp-demangle.c (struct d_print_info): Add pack_index. + (d_dump): Add DEMANGLE_COMPONENT_PACK_EXPANSION. + (d_make_comp): Likewise. DEMANGLE_COMPONENT_ARGLIST and + DEMANGLE_COMPONENT_TEMPLATE_ARGLIST can have two null args. + (cplus_demangle_builtin_types): Add char16/32_t. + (cplus_demangle_type): Recognize them. + (d_template_args): Handle empty argument packs. + (d_template_arg): Handle argument packs. + (d_expression): Handle dependent name. + (d_index_template_argument): New fn. + (d_lookup_template_argument): New fn. + (d_find_pack, d_pack_length): New fn. + (d_print_subexpr): Split out... + (d_print_comp): ...from here. Use d_*_template_argument. + Handle empty arg lists. Support pack expansions. + * cp-demangle.h (D_BUILTIN_TYPE_COUNT): Increase to 32. + +2008-09-09 Jason Merrill + + * cp-demangle.c (d_dump): Handle DEMANGLE_COMPONENT_DECLTYPE. + (d_make_comp): Likewise. + (cplus_demangle_type): Handle decltype and DFP types. + (cplus_demangle_operators): Call operator takes 2 args. + (cplus_demangle_builtin_types): Add DFP types. + (d_exprlist): New fn. + (d_expression): Handle parm placeholders, T() and calls. + (d_print_comp): Handle decltype, T() and calls. + * testsuite/demangle-expected: Test the above. + +2008-08-07 Aaron W. LaFramboise + + * pex-win32.c (argv_to_argc): New function. + (spawn_script): Duplicate argv before calling win32_spawn. + +2008-07-31 Jakub Jelinek + + * mkstemps.c (mkstemps): Keep looping even for EISDIR. + +2008-07-31 Denys Vlasenko + + * mkstemps.c (mkstemps): If open failed with errno other than + EEXIST, return immediately. + * make-temp-file.c: Include errno.h. + (make_temp_file): If mkstemps failed, print an error message + before aborting. + +2008-07-24 Ralf Wildenhues + + * maint-tool (deps): Output config.h instead of stamp-h. + * Makefile.in: Rebuild deps. + (maintainer-clean-subdir): Depend on stamp-h rather than config.h. + Reverts 2007-07-11 change. + +2008-06-19 Eric Blake + + Adjust strsignal to POSIX 200x prototype. + * strsignal.c (strsignal): Remove const. + +2008-06-17 Ralf Wildenhues + + * configure: Regenerate. + +2008-06-15 Ralf Wildenhues + + * libiberty.texi: Expand TABs, drop indentation outside examples. + * obstacks.texi: Likewise. + +2008-04-21 Aurelien Jarno + + * libiberty/configure.ac: use -fPIC on Linux/MIPS hosts. + * libiberty/configure: Regenerate. + +2008-04-18 Kris Van Hees + + * testsuite/demangle-expected: Added tests for char16_t and char32_t. + +2008-04-18 Paolo Bonzini + + PR bootstrap/35457 + * aclocal.m4: Add override.m4. + * configure: Regenerate. + +2008-03-31 Ian Lance Taylor + + * cp-demangle.c (d_substitution): Correct overflow check to avoid + -fstrict-overflow optimizations. + +2008-03-27 Paolo Bonzini + + * configure.ac (frags): Don't set, use frag instead. + (PICFLAG): Set here and substitute. + * Makefile.in (PICFLAG): Substitute from autoconf. + * configure: Regenerate. + +2008-03-24 Ian Lance Taylor + + * sha1.c: New file, from gnulib. + * Makefile.in: Rebuild dependencies. + (CFILES): Add sha1.c. + (REQUIRED_OFILES): Add sha1.o. + +2008-03-24 Doug Evans + + * make-relative-prefix.c (make_relative_prefix_1): Handle NULL + return from strdup. + +2008-03-12 Seongbae Park + + * cplus-dem.c (malloc, realloc): Use void * instead of char * + as return type. + +2008-03-11 Nick Clifton + + * md5.c (md5_process_bytes): Do not assume that memcpy will + provide a return value. + +2008-02-19 Ben Elliston + + PR other/12618 + * testsuite/Makefile.in (mostlyclean): Remove any core file. + +2008-01-26 David Daney + + * cp-demangle.c (d_dump): Handle DEMANGLE_COMPONENT_JAVA_RESOURCE, + DEMANGLE_COMPONENT_COMPOUND_NAME, and + DEMANGLE_COMPONENT_CHARACTER cases. + (d_make_comp): Handle DEMANGLE_COMPONENT_COMPOUND_NAME and + DEMANGLE_COMPONENT_JAVA_RESOURCE cases. + (d_make_character): New function. + (d_java_resource): Same. + (d_special_name): Handle "Gr" case. + (d_print_comp): Handle DEMANGLE_COMPONENT_JAVA_RESOURCE, + DEMANGLE_COMPONENT_COMPOUND_NAME, and + DEMANGLE_COMPONENT_CHARACTER cases. + * testsuite/demangle-expected: Add test for java resource name + mangling. + +2008-01-23 Thiago Jung Bauermann + + * cplus-dem.c (demangle_function_name): Changed to return value + indicating if a name was correctly demangled. + (iterate_demangle_function): Use demangle_function_name return + value. + +2008-01-19 Manuel Lopez-Ibanez + + PR other/33768 + * splay-tree.c (rotate_left): Fix minor typo in comment. + (rotate_right): Likewise. + +2007-11-12 Joseph Myers + + * floatformat.c (floatformat_ibm_long_double_is_valid): Fix + compiler warnings. + (floatformat_ibm_long_double): Use + floatformat_ibm_long_double_is_valid. + +2007-11-07 Joseph Myers + Daniel Jacobowitz + + * floatformat.c (mant_bits_set): New. + (floatformat_to_double): Use it. Note no special handling of + split formats. + (floatformat_from_double): Note no special handing of split + formats. + (floatformat_ibm_long_double_is_valid, + floatformat_ibm_long_double): New. + (floatformat_ieee_single_big, floatformat_ieee_single_little, + floatformat_ieee_double_big, floatformat_ieee_double_little, + floatformat_ieee_double_littlebyte_bigword, floatformat_vax_f, + floatformat_vax_d, floatformat_vax_g, floatformat_i387_ext, + floatformat_m68881_ext, floatformat_i960_ext, + floatformat_m88110_ext, floatformat_m88110_harris_ext, + floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword, + floatformat_ia64_spill_big, floatformat_ia64_spill_little, + floatformat_ia64_quad_big, floatformat_ia64_quad_little): Update + for addition of split_half field. + +2007-09-06 Tom Tromey + + * pexecute.txh (pex_free): Document process killing. + +2007-08-31 Douglas Gregor + + * cp-demangle.c (d_dump): Handle + DEMANGLE_COMPONENT_RVALUE_REFERENCE. + (d_make_comp): Ditto. + (cplus_demangle_type): Ditto. + (d_print_comp): Ditto. + (d_print_mod): Ditto. + (d_print_function_type): Ditto. + +2007-08-24 Kai Tietz + + * pex-common.h: (pex_funcs): Retyped wait and exec_child to pid_t. + * pex-djgpp.c: Likewise. + * pex-msdos.c: Likewise. + * pex-unix.c: Likewise. + * pex-win32.c: Likewise. + +2007-08-17 Michael Snyder + + * make-relative-prefix.c (make_relative_prefix_1): Resource leaks. + +2007-08-03 Michael Snyder + + * make-relative-prefix.c (make_relative_prefix_1): Fix resource + leak. + +2007-07-31 Michael Snyder + + * cp-demangle.c (d_print_comp): Guard against null. + +2007-07-25 Ben Elliston + + * Makefile.in (CFILES): Remove ternary.c. + (REQUIRED_OFILES): Remove ./ternary.o. + (INSTALLED_HEADERS): Remove ternary.h. + (ternary.o): Remove. + * ternary.c: Remove. + +2007-07-23 DJ Delorie + + * argv.c (writeargv): Fix typo in inline documentation. + * functions.texi: Regenerate. + +2007-07-17 DJ Delorie + + * configure.ac (target_header_dir, msdosdjgpp): Remove duplicate + gettimeofday entry. + * configure: Likewise. + +2007-07-11 Alexandre Oliva + + * maint-tool (deps): Output stamp-h instead of config.h. + * Makefile.in: Rebuild deps. + (maintainer-clean-subdir): Depend on stamp-h rather than config.h. + +2007-07-02 Simon Baldwin + + * argv.c (writeargv): Removed declaration of unused variable. + +2007-06-14 Paolo Bonzini + + * configure.ac: Use ACX_PROG_CC_ALMOST_PEDANTIC too. + * configure: Regenerate. + +2007-06-14 Paolo Bonzini + + * aclocal.m4: Include config/warnings.m4. + * configure.ac: Use ACX_PROG_CC_WARNING_OPTS. + * configure: Regenerate. + +2007-06-07 Geoffrey Keating + + * configure.ac: Non-default multilibs can be cross compilations. + * configure: Regenerate + +2007-05-07 Nathan Froyd + + * argv.c (writeargv): New function. + +2007-05-05 Geoffrey Keating + + * cp-demangle.c (d_name): Detect local-source-name. + (d_prefix): Likewise. + (d_unqualified_name): Implement local-source-name. + +2007-05-03 Joel Brobecker + + * filename_cmp.c: Replace include of ctype.h by include of + safe-ctype.h. + (filename_cmp): Use TOLOWER instead of tolower for conversions + that are locale-independent. + * Makefile.in (filename_cmp.o): Add dependency on safe-ctype.h. + +2007-04-11 Thomas Neumann tneumann@users.sourceforge.net + + * argv.c: Use ANSI C declarations. + * make-relative-prefix.c: Likewise. + +2007-04-06 Joel Brobecker + + * filename_cmp.c (filename_cmp): Improve documentation. + +2007-04-02 Andreas Schwab + + * filename_cmp.c: Include "config.h". + +2007-03-29 Joel Brobecker + + * filename_cmp.c: New file. + * Makefile.in (CFILES): Add filename_cmp.c. + (REQUIRED_OFILES): Add filename_cmp.o + (filename_cmp.o): New rule. + * functions.texi: Regenerate. + +2007-03-15 Geoffrey Keating + + * cp-demangle.c (d_encoding): Exit early on error. + (d_pointer_to_member_type): Exit early if cplus_demangle_type + returns NULL. + (cplus_demangle_type): Likewise. + * testsuite/demangle-expected: New testcase. + +2007-03-01 Brooks Moses + + * Makefile.in: Add install-pdf target as copied from + automake v1.10 rules. + * testsuite/Makefile.in: Add dummy install-pdf target. + +2007-03-01 Peter Breitenlohner + Eric Botcazou + + PR other/16513 + * Makefile.in: Install library under $(MULTIOSDIR), not $(MULTISUBDIR). + Install headers in multilib independent location. + +2007-02-26 DJ Delorie + + * configure.ac: add djgpp-specific results, so we don't have to + link during a cross compilation. + * configure: Regenerated. + +2007-01-31 Ralf Wildenhues + + * hex.c: Fix typo. + * choose-temp.c: Likewise. + * functions.texi: Regenerate. + +2007-01-31 Vladimir Prus + + * pex-common.h (struct pex_obj): New fields + stderr_pipe and read_err. + * pex-common.c (pex_init_common): Initialize + stderr_pipe. + (pex_run_in_environment): Add error checking + for PEX_STDERR_TO_PIPE. Create a pipe + for stderr if necessary. + (pex_read_err): New. + (pex_free): Close read_err. + * pexecute.txh: Document changes. + * functions.texi: Regenerated. + +2007-01-31 Ben Elliston + + * strsignal.c (psignal): Change type of signo to int. + * functions.texi: Regenerate. + +2007-01-29 Simon Baldwin + + * cp-demangle.h (cplus_demangle_operators): External definition + suppressed if not building for libstdc++. + * cp-demangle.c (__gcclibcxx_demangle_callback): Augmented interface + to demangling, provides a malloc-less version of __cxa_demangle. + (cplus_demangle_print_callback): Public callback version of + cplus_demangle_print. + (struct d_growable_string): New growable string structure. + (d_growable_string_init): New function, provides support for + growable strings separate from print info. + (d_growable_string_resize): Likewise. + (d_growable_string_append_buffer): Likewise. + (d_growable_string_callback_adapter):): Likewise. + (d_print_init): New print info initialization function. + (d_print_error): Macro replace by inline function. + (d_print_saw_error): Likewise. + (d_append_char): Likewise. + (d_append_buffer): Likewise. + (d_append_string): New inline function, replaces the + d_append_string_constant macro. + (d_flush_buffer): New function, flushes buffer to callback. + (d_demangle_callback, is_ctor_or_dtor): Malloc-based fallback + for unsupported dynamic arrays replaced by alloca(). + (d_demangle): Return string length estimating removed. + (d_dump): Moved error case handling from call site into function. + (d_print_resize): Function removed. + (d_print_append_char): Likewise. + (d_print_append_buffer): Likewise. + (d_print_error): Likewise. + (d_print_comp): Added special case handling for Java arrays. + (java_demangle_v3): Removed string post-processing for Java arrays, + now replaced by special case handling in d_print_comp. + (cplus_demangle_v3_callback): Augmented interface to demangling, + provides a malloc-less version of cplus_demangle_v3. + (java_demangle_v3_callback): Augmented interface to demangling, + provides a malloc-less version of java_demangle_v3. + +2007-01-12 Ben Elliston + + * pex-unix.c (writeerr): Cast write result to void. + + * choose-temp.c (choose_temp_base): Check the result of the call + to mktemp rather than testing the length of the modified string. + +2006-12-20 Geoffrey Keating + + * cp-demangle.h: Add comment explaining what to do to avoid + overrunning string. + (d_check_char): New. + (d_next_char): Don't advance past trailing '\0'. + * cp-demangle.c (cplus_demangle_mangled_name): Use d_check_char. + (d_nested_name): Likewise. + (d_special_name): Likewise. + (d_call_offset): Likewise. + (d_function_type): Likewise. + (d_array_type): Likewise. + (d_pointer_to_member_type): Likewise. + (d_template_param): Likewise. + (d_template_args): Likewise. + (d_template_arg): Likewise. + (d_expr_primary): Likewise. + (d_local_name): Likewise. + (d_substitution): Likewise. + (d_ctor_dtor_name): Use d_advance rather than d_next_char. + * testsuite/test-demangle.c: Include sys/mman.h. + (MAP_ANONYMOUS): Define. + (protect_end): New. + (main): Use protect_end. + * testsuite/demangle-expected: Add testcases for overrunning + the end of the string. + +2006-11-30 Andrew Stubbs + J"orn Rennecke + + PR driver/29931 + * make-relative-prefix.c (make_relative_prefix_1): New function, + broken out of make_relative_prefix. Make link resolution dependent + on new parameter. + (make_relative_prefix): Use make_relative_prefix_1. + (make_relative_prefix_ignore_links): New function. + +2006-11-08 Vladimir Prus + + * pex-win32.c (no_suffixes): Remove. + (std_suffixes): Add "" as first element. + (find_executable): Remove detection of already-present + extension. Try all suffixes in std_suffixes. + +2006-11-07 Julian Brown + + * floatformat.c (get_field): Fix segfault with little-endian word + order on 64-bit hosts. + (put_field): Likewise. + (min): Move definition. + +2006-10-26 Danny Smith + + pex-win32.c (argv_to_cmdline): Replace xmalloc with XNEWVEC. + (find_executable): Likewise. + (win32_spawn): Cast alloca return to (char**). + Replace malloc with XNEWVEC. + bcopy.c (bcopy): Add explict casts in assignments. + +2006-10-25 Ben Elliston + + * pexecute.txh: Wrap pexecute's "flag" argument with @var {..}. + +2006-10-10 Brooks Moses + + * Makefile.in: Added "pdf", "libiberty.pdf" target support. + * testsuite/Makefile.in: Added empty "pdf" target. + +2006-09-22 Ian Lance Taylor + + PR other/29176 + * cp-demangle.c (d_substitution): Check for overflow when + computing substitution index. + +2006-08-30 Corinna Vinschen + + * configure.ac: Add case for Mingw as host. + * configure: Regenerate. + +2006-08-27 Ian Lance Taylor + + PR driver/27622 + * pex-common.h (struct pex_funcs): Add toclose parameter to + exec_child field. + * pex-common.c (pex_run_in_environment): Pass toclose to + exec_child. + * pex-djgpp.c (pex_djgpp_exec_child): Add toclose parameter. + * pex-unix.c (pex_unix_exec_child): Likewise. + * pex-msdos.c (pex_msdos_exec_child): Likewise. + * pex-win32.c (pex_win32_exec_child): Likewise. + + PR other/28797 + * cp-demangle.c (d_pointer_to_member_type): Do add a substitution + for a qualified member which is not a function. + * testsuite/demangle-expected: Add test case. + +2006-07-27 Jan Hubicka + + PR rtl-optimization/28071 + * hashtab.c (htab_empty): Clear out n_deleted/n_elements; + downsize the hashtable. + +2006-07-04 Peter O'Gorman + + * Makefile.in: chmod 644 before ranlib during install. + +2006-06-02 Mark Shinwell + + * pex-unix.c (pex_unix_exec_child): Insert cast when assigning + to environ. + +2006-06-01 Mark Shinwell + + * pex-common.c: New function pex_run_in_environment. + * pex-common.h: Add environment parameter to exec_child. + * pex-msdos.c: Add environment parameter to pex_msdos_exec_child. + * pex-djgpp.c: Add environment parameter to pex_djgpp_exec_child. + (pex_djgpp_exec_child): Pass environment to child process. + * pex-unix.c: Add environment parameter to pex_unix_exec_child. + (pex_unix_exec_child): Pass environment to child process. + * pex-win32.c: Add environment parameter to pex_win32_exec_child. + New function env_compare for comparing VAR=VALUE pairs. + (win32_spawn): Assemble environment block and pass to CreateProcess. + (spawn_script): Pass environment through to win32_spawn. + (pex_win32_exec_child): Pass environment through to spawn_script and + win32_spawn. + * functions.texi: Regenerate. + * pexecute.txh: Document pex_run_in_environment. + +2006-05-28 Mark Shinwell + + * mkstemps.c: Open temporary files in binary mode. + +2006-05-12 Anton Blanchard + + * cplus-dem.c (demangle_fund_type): Ensure buf is large enough to + hold "int%u_t". + +2006-04-24 Julian Brown + + * floatformat.c (floatformat_to_double): Fix (biased) exponent=0 case. + +2006-03-29 Jim Blandy + + * pex-common.c (pex_input_file, pex_input_pipe): New functions. + (pex_init_common): Initialize obj->input_file. + (pex_run): Close any file opened by pex_input_file. + * pexecute.txh (pex_input_file, pex_input_pipe): New docs. + * pex-common.h (struct pex_obj): New field input_file. + (struct pex_funcs): New function ptr fdopenw. + * pex-unix.c (pex_unix_fdopenw): New function. + (funcs): List it as our fdopenw function. + * pex-win32.c (pex_win32_fdopenw): New function. + (funcs): List it as our fdopenw function. + * pex-djgpp.c (funcs): Leave fdopenw null. + * pex-msdos (funcs): Same. + * functions.texi: Regenerated. + +2006-04-10 Jim Blandy + + * pex-common.c (temp_file): New function, containing guts of + pex-style temporary file name generation. + (pex_run): Use it. + +2006-04-06 Carlos O'Donell + + * Makefile.in: Add install-html, install-html-am, and + install-html-recursive targets. Define mkdir_p and + NORMAL_INSTALL. + * configure.ac: AC_SUBST datarootdir, docdir, htmldir. + * configure: Regenerate. + * testsuite/Makefile.in: Add install-html and html targets. + +2006-03-31 Mark Mitchell + + * pex-win32.c (): Include. + (fix_argv): Remove. + (argv_to_cmdline): New function. + (std_suffixes): New variable. + (no_suffixes): Likewise. + (find_executable): New function. + (win32_spawn): Likewise. + (spawn_script): Use win32_spawn instead of _spawnv[p]. + (pex_win32_exec_child): Replace MSVCRT calls with Win32 API calls. + (pex_win32_wait): Likewise. + +2006-03-24 Jim Blandy + + * pex-common.c (pex_run): Simplify output name handling. + +2006-03-12 Jim Blandy + + * pex-common.h (struct pex_obj): Doc fixes. + +2006-03-11 Jim Blandy + + * functions.texi: Regenerate. + +2006-02-21 Ben Elliston + + * pexecute.c (pwait): Syntax fix for previous change. + +2006-02-17 Uttam Pawar + + * pexecute.c (pwait): Free vector pointer. + * partition.c (partition_print): Free class_elements pointer. + +2006-02-11 Roger Sayle + R. Scott Bailey + Bill Northcott + + PR bootstrap/16787 + * floatformat.c: Include where available. + (NAN): Use value of DBL_QNAN if defined, and NAN isn't. + +2006-01-29 Gabriel Dos Reis + + * configure.ac: Add -Wc++-compat to ac_libibety_warn_cflags where + supported. + * configure: Regenerated. + +2006-01-20 Carlos O'Donell + + * testsuite/Makefile.in: Add test-expandargv test. + * testsuite/test-expandargv.c: New test. + * argv.c (expandargv): Check for errors with ferror, + rather than just by looking at return value from fread. + +2005-12-17 Gabriel Dos Reis + + * floatformat.c (floatformat_i387_ext_is_valid): Use explicit cast + to convert from "from". + (floatformat_to_double): Likewise. + (floatformat_from_double): Use explicit cast to convert from "to". + +2005-12-10 Terry Laurenzo + + PR java/9861 + * cp-demangle.c (d_bare_function_type): Recognize new 'J' qualifer + and include return type when found. + (d_print_comp)[DEMANGLE_COMPONENT_FUNCTION_TYPE]: Add + conditional logic to change printing order of return type.when + the DMGL_RET_POSTFIX option is present. + (java_demangle_v3): Add DMGL_RET_POSTFIX option to d_demangle + call. + * testsuite/test-demangle.c (main): Recognize option --ret-postfix + * testsuite/demangle-expected: Test cases to verify extended encoding. + Updated comment to document --ret-postfix option. + +2005-11-06 Richard Guenther + + * splay-tree.c (rotate_left): New function. + (rotate_right): Likewise. + (splay_tree_splay_helper): Remove. + (splay_tree_splay): Re-implement. + +2005-10-31 Mark Kettenis + + * floatformat.c (floatformat_vax_aingle, floatformat_vax_double): + New variables. + +2005-10-07 Mark Mitchell + + * at-file.texi: Fix typo. + +2005-10-03 Mark Mitchell + + * at-file.texi: New file. + +2005-09-27 Mark Mitchell + + * argv.c (expandargv): Do not use xmalloc_failed. + +2005-09-26 Mark Mitchell + + * argv.c (safe-ctype.h): Include it. + (ISBLANK): Remove. + (stdio.h): Include. + (buildargv): Use ISSPACE instead of ISBLANK. + (expandargv): New function. + * Makefile.in: Regenerated. + +2005-09-14 Christopher Faylor + + * pex-win32.c: Include "windows.h". + (backslashify): New function. + (fix_argv): Use backslashify to convert path to windows format. + Allocate one more place in new argv for potential executable from '#!' + parsing. + (tack_on_executable): New function. Conditional on USE_MINGW_MSYS + (openkey): Ditto. + (mingw_rootify): Ditto. + (msys_rootify): Ditto. + (spawn_script): New function. + (pex_win32_exec_child): Save translated argv in newargv. Pass to + spawn_script if spawnv* fails. + (main): New function. Conditional on MAIN. Useful for testing. + +2005-08-17 Mark Kettenis + + * floatformat.c (floatformat_always_valid): Change type of last + argument to `void *'. + (floatformat_i387_ext_is_valid): Likewise. + (floatformat_to_double): Change type of second argument to `const + void *'. + (floatformat_from_double): Change type of last argument to `void + *'. + (floatformat_is_valid): Change type of last argument to `const + void *'. + (ieee_test): Remove redundant casts. + +2005-08-17 Kelley Cook + + * strverscmp.c: Update FSF address. + * testsuite/Makefile.in: Likewise. + * testsuite/test-demangle.c: Likewise. + * testsuite/test-pexecute.c: Likewise. + +2005-07-23 Kaveh R. Ghazi + + * getopt.c: Include ansidecl.h before system headers. + +2005-07-22 Ben Elliston + + * getopt.c: Include "ansidecl.h". + (_getopt_initialize): Mark argc and argv parameters as unused. + +2005-07-22 Ben Elliston + + * regex.c (regcomp): Change type of `i' from unsigned to int. + +2005-07-22 Ben Elliston + + Recover patch lost in the sourceware repository: + 2005-07-09 Ben Elliston + * memcpy.c: Remove ANSI_PROTOTYPES conditional code. + * memmove.c: Likewise. + * objalloc.c: Likewise. + +2005-07-22 Ben Elliston + + * configure.ac: Check for a getopt(3) declaration. + * configure, config.in: Regenerate. + +2005-07-15 Ben Elliston + + * regex.c (TRANSLATE): Cast rhs of ternary expression to char. + +2005-07-12 Ben Elliston + + * floatformat.c (floatformat_to_double): Add a comment about a + potential source of warnings when compiling this file. + +2005-07-12 Ben Elliston + + * pexecute.c (pexecute): Cast string litrals to char *. + * regex.c (re_comp): Cast a call to gettext() to char *. + +2005-07-07 Kelley Cook + + * config.table: Delete file. Move former contents into ... + * configure.ac: ... here and escape any brackets for m4. + * Makefile.in (config.status): Remove dependency on config.table. + * configure: Regenerate. + +2005-07-07 Kelley Cook + + * config.in: Regenerate for 6/20 change. + +2005-07-03 Steve Ellcey + + PR other/13906 + * md5.c (md5_process_bytes): Check alignment. + +2005-07-01 Ian Lance Taylor + + PR other/22268 + * cp-demangle.c (d_expr_primary): Don't run off the end of the + string while looking for the end of a literal value. + * testsuite/demangle-expected: Add test case. + +2005-06-30 Daniel Berlin + + * hashtab.c (EMPTY_ENTRY): Moved and renamed. + (DELETED_ENTRY): Ditto. + +2005-06-20 Geoffrey Keating + + * strverscmp.c: New. + * Makefile.in (CFILES): Add strverscmp.c. + (CONFIGURED_OFILES): Add strverscmp.o. + (strverscmp.o): New rule. + (stamp-functions): Add $(srcdir) to files in source directory. + * configure.ac (funcs): Add strverscmp. + (AC_CHECK_FUNCS): Add strverscmp. + * configure: Regenerate. + * functions.texi: Regenerate. + +2005-05-28 Eli Zaretskii + + * configure.ac: Add snprintf and vsnprintf to AC_CHEK_DECLS. + * config.in, configure: Regenerate. + +2005-05-25 Richard Henderson + + * cp-demangle.c (d_dump): Handle DEMANGLE_COMPONENT_HIDDEN_ALIAS. + (d_make_comp, d_print_comp): Likewise. + (d_special_name): Generate one. + * testsuite/demangle-expected: Add a hidden alias test. + +2005-05-24 Gabriel Dos Reis + + * configure.ac: Check declarations for calloc(), getenv(), + malloc(), realloc() and sbrk(). + * config.in: Regenerate. + * configure: Likewise. + + * alloca.c (C_alloca): Change "new" to "new_storage". Use XNEWVEC + instead of xmalloc. + * choose-temp.c (choose_temp_base): Use XNEWVEC instea od xmalloc. + * concat.c (liiberty_concat_ptr): Surround definition with an + extern "C" block, if __cplusplus. + (concat): Use XNEWVEC instead of xmalloc. + (reconcat): Likewise. + * cp-demangle.c (struct d_print_template): Rename member + "template" to "template_decl". Adjust use throughout the file. + (d_print_resize): Properly cast return value of realloc(). + (cplus_demangle_print): Same for malloc(). + (d_demangle): Likewise. + * cp-demint.c (cplus_demangle_fill_builtin_type): Rename parameter + "typename" to "type_name". + * cplus-dem.c (grow_vect): Use XRESIZEVEC instead of xrealloc(). + (work_stuff_copy_to_from): Use XNEWVEC insteand of xmalloc(). + (demangle_template_value_parm): Likewise. + (demangle_template): Likewise. + (recursively_demangle): Likewise. + (do_hpacc_template_literal): Likewise. + (do_arg): Likewise. + (remember_type): Likewise. + (remember_Ktype): Likewise. + (register_Btype): Likewise. + (string_need): Use XRESIZEVEC instead of xrealloc(). + * dyn-string.c (dyn_string_init): Use XNEWVEC. + (dyn_string_new): Use XNEW. + (dyn_string_resize): Use XRESIZEVEC. + * fnmatch.c (fnmatch): Rename local variable "not" to "negate". + * getopt.c (getenv): Declare only if !__cplusplus and !getenv. + Otherwise include . + (exchange): Cast return value of malloc(). + * hashtab.c (htab_size): Define as both macro and non-inline + function. + (htab_elements): Likewise. + * getpwd.c (getpwd): Use XNEWVEC. + (htab_create_alloc_ex): Use C90 prototype-style. + * lrealpath.c (lrealpath): Appropriately cast return value of + malloc(). + * make-relative-prefix.c (save_string): Likewise. + * make-temp-file.c (try_dir): Rename from "try". Adjust use in + the file. + (choose_tmpdir): Use XNEWVEC. + * mkstemps.c (mkstemps): Rename parameter "template" to "pattern". + * pex-common.c (pex_init_common): Use XNEW. + (pex_add_remove): Use XRESIZEVEC. + (pex_run): Likewise. + (pex_get_status_and_time): Likewise. + * pex-djgpp.c (pex_djgpp_exec_child): Likewise. + * pex-msdos.c (pex_init): Use XNEW. + (pex_msdos_exec_child): Likewise. + (pex_msdos_exec_child): Use XRESIZEVEC. + * pex-unix.c (pex_wait): Use XNEW. + * pex-win32.c (fix_argv): Use XNEWVEC. + * pexecute.c (pwait): Likewise. + * setenv.c (setenv): Properly cast return value of malloc(). + * sigsetmask.c (sigsetmask): Rename local variables "old" and + "new" to "old_sig" and "new_sig". + * sort.c (main): Use XNEWVEC. + * spaces.c (spaces): Cast return value of malloc(). + * strndup.c (strndup): Likewise. + * ternary.c (ternary_insert): Use XNEW. + * xmalloc.c (malloc, realloc, calloc, sbrk): Surround declaration + with an extern "C" block if __cplusplus. + * xstrdup.c (xstrdup): Cast return value of memcpy(). + * xstrerror.c (strerror): Enclose declaration in an extern "C" + block if __cplusplus. + * xstrndup.c (xstrndup): Use XNEW. Cast return value of memcpy(). + +2005-05-16 Andreas Jaeger + + * getpwd.c: Remove unneeded prototype getcwd and move getwd so + that it's only declared if needed. + + * getopt1.c: Change order of includes so that __GNU_LIBRARY__ is + defined. + +2005-05-15 Andreas Jaeger + + * functions.texi: Regenerated. + +2005-05-15 Eli Zaretskii + + * pexecute.txh: Enclose multi-word data types in @deftypefn in + braces. Minor wording fixes. Use --- for em-dash. Use + @enumerate in enumerated lists. + + * fopen_unlocked.c: Enclose multi-word data types in @deftypefn in + braces. + +2005-05-11 Eli Zaretskii + + * pex-djgpp.c: Include string.h, fcntl.h, unistd.h, and + sys/stat.h. + (pex_init): Fix last argument to pex_init_common. + (pex_djgpp_exec_child): Remove leading underscore from _open, + _dup, _dup2, _close, and _spawnv/_spawnvp. Replace `program', + which is undeclared, with `executable', which was unused. Remove + unused variable `e'. Fix casting of last arg to spawnv/spawnvp. + (pex_djgpp_wait): Declare arguments with ATTRIBUTE_UNUSED. + +2005-05-11 Paul Brook + + * Makefile.in: Regenerate dependencies. + +2005-05-10 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + COPYING.LIB, Makefile.in, _doprnt.c, argv.c, asprintf.c, + choose-temp.c, clock.c, concat.c, copying-lib.texi, cp-demangle.c, + cp-demangle.h, cp-demint.c, cplus-dem.c, dyn-string.c, fdmatch.c, + fibheap.c, floatformat.c, fnmatch.c, fopen_unlocked.c, + gather-docs, getopt.c, getopt1.c, getruntime.c, hashtab.c, hex.c, + lbasename.c, lrealpath.c, maint-tool, make-relative-prefix.c, + make-temp-file.c, md5.c, mempcpy.c, mkstemps.c, objalloc.c, + obstack.c, partition.c, pex-common.c, pex-common.h, pex-djgpp.c, + pex-msdos.c, pex-one.c, pex-unix.c, pex-win32.c, pexecute.c, + physmem.c, putenv.c, regex.c, safe-ctype.c, setenv.c, snprintf.c, + sort.c, spaces.c, splay-tree.c, stpcpy.c, stpncpy.c, strndup.c, + strtod.c, ternary.c, unlink-if-ordinary.c, vasprintf.c, + vsnprintf.c, vsprintf.c, xexit.c, xmalloc.c, xstrndup.c + +2005-05-06 Kelley Cook + + * aclocal.m4 (AC_DEFINE_NOAUTOHEADER): Remove. + * configure.ac: Replace any AC_DEFINE_NOAUTOHEADER with AC_DEFINE. + * configure: Regenerate. + +2005-05-06 Kelley Cook + + * configure.ac: Use AC_C_BIGENDIAN instead of AC_C_BIGENDIAN_CROSS. + Use AC_CHECK_SIZEOF instead of AC_COMPILE_CHECK_SIZEOF. + * aclocal.m4: Don't include accross.m4. + * configure, config.in: Regenerate. + +2005-04-25 Kaveh R. Ghazi + + * fopen_unlocked.c (unlock_std_streams): New. + + * functions.texi: Regenerate. + +2005-04-16 Kaveh R. Ghazi + + * fopen_unlocked.c (unlock_stream): New. + Consolidate unlocking code into a helper function. + + * functions.texi: Regenerate. + +2005-04-13 Gabriel Dos Reis + + * asprintf.c: Include config.h. + * basename.c: Likewise. + * fdmatch.c: Likewise. + * hex.c: Likewise. + * lbasename.c: Likewise. + * spaces.c: Likewise. + * xatexit.c:Likewise. + * configure.ac: Do check declarations for basename, ffs, asprintf + and vasprintf for real. + * configure: Regenerate. + +2005-04-13 Gabriel Dos Reis + + * argv.c (dupargv): Allocate space of argv[argc], not + sizeof(char *) of that amount. Cast result to char *. + +2005-04-12 Gabriel Dos Reis + + * regex.c (wcs_re_match_2_internal, byte_re_match_2_internal): + Replace not with negate. + +2005-04-12 Gabriel Dos Reis + + * configure.ac: Check declarations for basename, ffs, asprintf, + vasprintf. + * configure: Regenerate. + * config.in: Likewise. + +2005-04-11 Kaveh R. Ghazi + + * Makefile.in (CFILES): Add fopen_unlocked.c. + (REQUIRED_OFILES): Add ./fopen_unlocked.o. + Regenerate dependencies. + + * configure.ac: Check for stdio_ext.h and __fsetlocking. + + * fopen_unlocked.c: New file. + + * functions.texi, configure, config.in: Regenerate. + +2005-04-04 Ian Lance Taylor + + * testsuite/test-pexecute.c (TEST_PEX_RUN): Move variable + declaration before statement. + +2005-04-02 Kaveh R. Ghazi + + * bcmp.c: Fix warnings and implement using memcmp. + * bcopy.c: Fix warnings. + * bzero.c: Fix warnings and implement using memset. + + * configure.ac (ac_libiberty_warn_cflags): Add -Wwrite-strings + -Wstrict-prototypes. + * configure, config.in: Regenerate. + + * bsearch.c, index.c, rindex.c, strstr.c, strtol.c, waitpid.c: Fix + warnings and reconcile interfaces with relevant standards. + +2005-04-02 Ian Lance Taylor + + * cp-demangle.c: Update copyright. + +2005-03-31 Joseph S. Myers + + * gettimeofday.c: Add "Supplemental" to @deftypefn. + * functions.texi: Regenerate. + +2005-03-28 Ian Lance Taylor + + * pex-common.c: New file. + * pex-one.c: New file. + * pexecute.c: New file. + * pex-common.h: Include . + (struct pex_obj): Define. + (struct pex_funcs): Define. + (pex_init_common): Declare. + * pex-unix.c: Rewrite. + * pex-win32.c: Rewrite. + * pex-djgpp.c: Rewrite. + * pex-msdos.c: Rewrite. + * testsuite/text-pexecute.c: New file. + * pexecute.txh: Rewrite. + * configure.ac: Check for wait3 and wait4. Set CHECK to + really-check rather than check-cplus-dem. + * functions.texi: Rebuild. + * Makefile.in: Rebuild dependencies. + (CFILES): Add pexecute.c, pex-common.c, pex-one.c. + (REQUIRED_OFILES): Add pexecute.o, pex-common.o, pex-one.o. + * testsuite/Makefile.in (really-check): New target. + (check-pexecute, test-pexecute): New targets. + * configure: Rebuild. + +2005-03-28 Mark Kettenis + + * unlink-if-ordinary.c: Include . + +2005-03-27 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 7/n. + * regex.c (PARAMS): Remove definition. + (PREFIX): Unconditionaly define using ISO C ## operator. + (init_syntax_once, extract_number, extract_number_and_incr, + print_fastmap, print_partial_compiled_pattern, + print_compiled_pattern, print_double_string, printchar, + convert_mbs_to_wcs, re_set_syntax, regex_grow_registers, + regex_compile, store_op1, store_op2, insert_op1, insert_op2, + at_begline_loc_p, at_endline_p, group_in_compile_stack, + insert_space, wcs_compile_range, byte_compile_range, + truncate_wchar, re_compile_fastmap, re_compile_fastmap, + re_set_registers, re_search, re_search_2, re_search_3, re_match, + re_match_2, count_mbs_length, wcs_re_match_2_internal, + byte_re_match_2_internal, group_match_null_string_p, + alt_match_null_string_p, common_op_match_null_string_p, + bcmp_translate, re_compile_pattern, re_comp, re_exec, regcomp, + regexec, regerror, regfree): Use ISO C prototype style. + * partition.c: (elem_compare): Likewise. + * cp-demangle.c (print_usage): Likewise. + +2005-03-27 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 5/n. + * random.c (srandom, initstate, setstate, random): Use ISO C + prototypes. + * putenv.c (putenv): Likewise. + * physmem.c (physmem_available, physmem_total, main): Likewise. + * pex-win32.c (fix_argv, pexecute, pwait): Likewise. + * pex-unix.c (pexecute, pwait): Likewise. + * pex-msdos.c (pexecute, pwait): Likewise. + * pex-djgpp.c (pexecute, pwait): Likewise. + * partition.c (partition_new, partition_delete, partition_union) + (elem_compare, partition_print): Likewise. + * obstack.c (_obstack_begin, _obstack_begin_1, _obstack_newchunk, + _obstack_allocated_p, _obstack_free, obstack_free, + _obstack_memory_used, print_and_abort, obstack_next_free, + obstack_object_size, obstack_base): Likewise. Remove codes + predicated on !defined(__STDC__). + * objalloc.c (objalloc_create, _objalloc_alloc, objalloc_free, + objalloc_free_block): Use ISO C prototypes. + * mkstemps.c (mkstemps): Likewise. + * memset.c (memset): Likewise. + * mempcpy.c (mempcpy): Likewise. + * rename.c (rename): Likewise. + * rindex.c (rindex): Likewise. + * setenv.c (setenv, unsetenv): Likewise. + * sigsetmask.c (sigsetmask): Likewise. + * snprintf.c (snprintf): Likewise. + * sort.c (sort_pointers, xmalloc): Likewise. + * spaces.c (spaces): Likewise. + * splay-tree.c (splay_tree_delete_helper, + splay_tree_splay_helper, splay_tree_splay, + splay_tree_foreach_helper, splay_tree_xmalloc_allocate, + splay_tree_new, splay_tree_xmalloc_allocate, + splay_tree_new_with_allocator, splay_tree_delete, + splay_tree_insert, splay_tree_remove, splay_tree_lookup, + splay_tree_max, splay_tree_min, splay_tree_predecessor, + splay_tree_successor, splay_tree_foreach, + splay_tree_compare_ints, splay_tree_compare_pointers): Likewise. + * stpcpy.c (stpcpy): Likewise. + * stpncpy.c (stpncpy): Likewise. + * strcasecmp.c (strcasecmp): Likewise. + * strchr.c (strchr): Likewise. + * strdup.c (strdup): Likewise. + +2005-03-27 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 6/n. + * strerror.c (init_error_tables, errno_max, strerror, strerrno, + strtoerrno, main): Use ISO C prototype style. + * strncasecmp.c (strncasecmp): Likewise. + * strncmp.c (strncmp): Likewise. + * strndup.c (strndup): Likewise. + * strrchr.c (strrchr): Likewise. + * strsignal.c (init_signal_tables, signo_max, strsignal, + strsigno, strtosigno, psignal, main): Likewise. + * strstr.c (strstr): Likewise. + * strtod.c (strtod, atof): Likewise. + * strtol.c (strtol): Likewise. + * strtoul.c (strtoul): Likewise. + * ternary.c (ternary_insert, ternary_cleanup, ternary_search, + ternary_recursivesearch): Likewise. + * tmpnam.c (tmpnam): Likewise. + * unlink-if-ordinary.c (unlink_if_ordinary): Likewise. + * vasprintf.c (int_vasprintf, vasprintf, checkit, main): Likewise. + * vfork.c (vfork): Likewise. + * vfprintf.c (vfprintf): Likewise. + * vprintf.c (vprintf): Likewise. + * vsnprintf.c (vsnprintf, checkit, main): Likewise. + * vsprintf.c (vsprintf): Likewise. + * waitpid.c (waitpid): Likewise. + * xatexit.c (xatexit, xatexit_cleanup): Likewise. + * xexit.c (xexit): Likewise. + * xmalloc.c (xmalloc_set_program_name, xmalloc_failed, xmalloc, + xcalloc, xrealloc): Likewise. + * xmemdup.c (xmemdup): Likewise. + * xstrdup.c (xstrdup): Likewise. + * xstrerror.c (xstrerror): Likewise. + * xstrndup.c (xstrndup): Likewise. + +2005-03-27 Andreas Jaeger + + * configure.ac (ac_c_preproc_warn_flag): Remove -Wtraditional + flags. + * configure: Regenerated. + +2005-03-27 Gabriel Dos Reis + + * getopt1.c (getopt_long_only): Fix thinko. + +2005-03-27 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 4/n. + * hashtab.c (higher_prime_index, hash_pointer, eq_pointer, + htab_size, htab_elements, htab_mod_1, htab_mod, htab_mod_m2, + htab_create_alloc, htab_set_functions_ex, htab_create, + htab_try_create, htab_delete, htab_empty, + find_empty_slot_for_expand, htab_expand, htab_find_with_hash, + htab_find, htab_find_slot_with_hash, htab_find_slot, + htab_remove_elt, htab_remove_elt_with_hash, htab_clear_slot, + htab_traverse_noresize, htab_traverse, htab_collisions, + htab_hash_string, iterative_hash): Use ISO C prototype. + * hex.c (hex_init): Likewise. + * index.c (index): Likewise. + * insque.c (insque, remque): Likewise. + * lbasename.c (lbasename): Likewise. + * lrealpath.c (lrealpath): Likewise. + * make-relative-prefix.c (save_string, split_directories, + free_split_directories, make_relative_prefix): Likewise. + * make-temp-file.c (try, choose_tmpdir, make_temp_file): Likewise. + * md5.c (md5_init_ctx, md5_read_ctx, md5_finish_ctx, md5_stream, + md5_buffer, md5_process_bytes, md5_process_block): Likewise. + * memchr.c (memchr): Likewise. + * memcpy.c (memcpy): Likewise. + * memmove.c (memmove): Likewise. + * gettimeofday.c (gettimeofday): Likewise. + * getruntime.c (get_run_time): Likewise. + * getpwd.c (getpwd, getpwd): Likewise. + * getpagesize.c (getpagesize): Likewise. + * getopt1.c (getopt_long, getopt_long_only, main): Likewise. + * getopt.c (my_index, exchange, _getopt_initialize, + _getopt_internal, getopt, main): Likewise. + * getcwd.c (getcwd): Likewise. + * fnmatch.c (fnmatch): Likewise. + * floatformat.c (floatformat_always_valid, + floatformat_i387_ext_is_valid, get_field, floatformat_to_double, + put_field, floatformat_from_double, floatformat_is_valid, + ieee_test, main): Likewise. + * fibheap.c (fibheap_new, fibnode_new, fibheap_compare, + fibheap_comp_data, fibheap_insert, fibheap_min, fibheap_min_key, + fibheap_union, fibheap_extract_min, fibheap_replace_key_data, + fibheap_replace_key, fibheap_replace_data, fibheap_delete_node, + fibheap_delete, fibheap_empty, fibheap_extr_min_node, + fibheap_ins_root, fibheap_rem_root, fibheap_consolidate, + fibheap_link, fibheap_cut, fibheap_cascading_cut, + fibnode_insert_after, fibnode_remove): Likewise. + * ffs.c (ffs): Likewise. + * fdmatch.c (fdmatch): Likewise. + * dyn-string.c (dyn_string_init, dyn_string_new, + dyn_string_delete, dyn_string_release, dyn_string_resize, + dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_insert_char, + dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring, dyn_string_eq): + Likewise. + +2005-03-27 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 3/n. + * cplus-dem.c (set_cplus_marker_for_demangling, consume_count, + consume_count_with_underscores, code_for_qualifier, + qualifier_string, demangle_qualifier, cplus_demangle_opname, + cplus_mangle_opname, cplus_demangle_set_style, + cplus_demangle_name_to_style, cplus_demangle, grow_vect, + ada_demangle, internal_cplus_demangle, squangle_mop_up, + work_stuff_copy_to_from, delete_non_B_K_work_stuff, + delete_work_stuff, mop_up, demangle_signature, + demangle_method_args, demangle_template_template_parm, + demangle_expression, demangle_integral_value, + demangle_real_value, demangle_template_value_parm, + demangle_template, arm_pt, demangle_arm_hp_template, + demangle_class_name, demangle_class, iterate_demangle_function, + demangle_prefix, gnu_special, recursively_demangle, arm_special, + demangle_qualified, get_count, do_type, demangle_fund_type, + do_hpacc_template_const_value, do_hpacc_template_literal, + snarf_numeric_literal, do_arg, remember_type, remember_Ktype, + register_Btype, remember_Btype, forget_B_and_K_types, + forget_types, demangle_args, demangle_nested_args, + demangle_function_name, string_need, string_delete, string_init, + string_clear, string_empty, string_append, string_appends, + string_appendn, string_prepend, string_prepends, string_prependn, + string_append_template_idx): Use ISO C prootype style. + * cp-demint.c (cplus_demangle_fill_component, + cplus_demangle_fill_builtin_type, cplus_demangle_fill_operator, + cplus_demangle_v3_components): Likewise. + +2005-03-26 Gabriel Dos Reis + + Convert libiberty to use ISO C prototype style 2/n. + * cp-demangle.h: Remove uses of PARAMS. + * cp-demangle.c: Likewise. + (d_dump, cplus_demangle_fill_name, + cplus_demangle_fill_extended_operator, cplus_demangle_fill_ctor, + cplus_demangle_fill_dtor, d_make_empty, d_make_comp, d_make_name, + d_make_builtin_type, d_make_operator, d_make_extended_operator, + d_make_ctor, d_make_dtor, d_make_template_param, d_make_sub, + cplus_demangle_mangled_name, has_return_type, + is_ctor_dtor_or_conversion, d_encoding, d_name, d_nested_name, + d_prefix, d_unqualified_name, d_source_name, d_number, + d_identifier, d_operator_name, d_special_name, d_call_offset, + d_ctor_dtor_name, cplus_demangle_type, d_cv_qualifiers, + d_function_type, d_bare_function_type, d_class_enum_type, + d_array_type, d_pointer_to_member_type, d_template_param, + d_template_args, d_template_arg, d_expression, d_expr_primary, + d_local_name, d_discriminator, d_add_substitution, + d_substitution, d_print_resize, d_print_append_char, + d_print_append_buffer, d_print_error, cplus_demangle_print, + d_print_comp, d_print_java_identifier, d_print_mod_list, + d_print_mod, d_print_function_type, d_print_array_type, + d_print_expr_op, d_print_cast, cplus_demangle_init_info, + d_demangle, __cxa_demangle, cplus_demangle_v3, java_demangle_v3, + is_ctor_or_dtor, is_gnu_v3_mangled_ctor, is_gnu_v3_mangled_dtor, + print_usage, main): + +2005-03-26 Gabriel Dos Reis + + Convert libiberty to ISO C prototype style 1/n. + * _doprnt.c: Remove conditional #include on + ANSI_PROTOTYPES as the latter is always assumed. + (_doprnt, checkit, main): Use ISO C prototype. + * alloca.c (find_stack_direction, C_alloca): Use ISO C prototype. + * argv.c: Remove conditional #includes on ANSI_PROTOTYPES. + (dupargv, freeargv, buildargv, main): Use ISO C prototype. + * atexit.c (atexit): Likewise + * asprintf.c: Remove conditional include on ANSI_PROTOTYPES. + (asprintf): Use ISO C prototype. + * basename.c (basename): Likewise + * bcmp.c (bcmp): Likewise. + * bcopy.c (bcopy): Likewise. + * bzero.c (bzero): Likewise. + * bsearch.c (bsearch): Likewise. Improve const-correctness. + * choose-temp.c (choose_temp_base): Likewise. + * calloc.c: Remove conditional #include on ANSI_PROTOTYPES. + (calloc): Use ISO C prototype. + * clock.c (clock): Likewise. + * concat.c: Remove conditional #include on ANSI_PROTOTYPES. + (vconcat_length, vconcat_copy, concat_length, concat_copy, + concat_copy2, concat, reconcat, main): Use ISO C prototype. + * copysign.c (copysign): Likewise. + +2005-03-24 Kaveh R. Ghazi + + * Makefile.in (CFILES): Add strndup.c and xstrndup.c. + (REQUIRED_OFILES): Add xstrndup.o. + (CONFIGURED_OFILES): Add strndup.o. + Regenerate dependencies. + + * configure.ac (funcs, AC_CHECK_FUNCS): Add strndup. + + * strndup.c, xstrndup.c: New. + + * config.in, configure, functions.texi: Regenerate. + +2005-03-24 Kaveh R. Ghazi + + * xmemdup.c, xstrdup.c: Expose the tail call. + +2005-03-09 Mark Mitchell + + * configure.ac (funcs): Add gettimeofday. + * configure: Regenerated. + * gettimeofday.c: New file. + * Makefile.in (CFILES): Add gettimeofday. + (CONFIGURED_OFILES): Add gettimeofday.o. + (./gettimeofday.o): New rule. + +2005-03-09 Ian Lance Taylor + + * pex-os2.c: Remove. + * configure.ac: Remove *-*-os2-emx* case when setting pexecute. + * Makefile.in (CFILES): Remove pex-os2.c. + (CONFIGURED_OFILES): Remove pex-os2.o. + (pex-os2.o): Remove target. + * configure: Rebuild. + +2005-03-07 Ian Lance Taylor + + * mpw-config.in: Remove. + * mpw-make.sed: Remove. + * mpw.c: Remove. + * Makefile.in (CFILES): Remove pex-mpw.c. + (CONFIGURED_OFILES): Remove pex-mpw.o. + (mpw.o, pex-mpw.o): Remove targets. + * maint-tool (undoc): Remove reference to mpw.c. + +2005-03-06 DJ Delorie + + * configure.ac (target_header_dir): vfork is a stub under djgpp. + * configure: Regenerated. + +2005-03-01 Jan Beulich + + * Makefile.in (CFILES): Add unlink-if-ordinary.c + (REQUIRED_OFILES): Add unlink-if-ordinary.o. + Add dependencies and rule for unlink-if-ordinary.o. + * unlink-if-ordinary.c: New. + +2005-03-01 Ben Elliston + + * hashtab.c (htab_find_slot_with_hash): Make function + documentation clearer. + +2005-02-13 Jason Merrill + + * cp-demangle.c (__cxa_demangle): Change resolution of ambiguous + arguments. + +2005-01-11 Tobias Schl"uter + + * hex.c (hex_value): Group 'unsigned int' together to get correct + markup. + * functions.texi: Regenerated. + +2004-12-27 H.J. Lu + + * Makefile.in: Undo to 2004-12-17. + * aclocal.m4: Likewise. + * config.table: Likewise. + * configure.ac: Likewise. + * maint-tool: Likewise. + * configure: Likewise. + +2004-12-19 H.J. Lu + + PR bootstrap/19072 + * Makefile.in (enable_shared): New substitute. + (LTTARGETLIB): New. + (PREFIXTARGETLIB): New. + (LTTESTLIB): New. + (PREFIXTESTLIB): New. + (CCLD): New. + (LINK): New. + ($(TARGETLIB)): Use $(LINK) to create libraries and create + targets by hand. + ($(TESTLIB)): Likewise. + (mostlyclean): Don't remove .libs. Remove the libtool object + directory. + + * config.table (enable_shared): Removed. + + * configure.ac (enable_static): Set to yes. + (AC_PROG_LIBTOOL): Removed. + (AM_DISABLE_SHARED): Uncommented. + (AM_PROG_LIBTOOL): Likewise. + (LIBOBJS): Add `./' to avoid VPATH. + (LTLIBOBJS): Likewise. + (enable_shared): Substitute. + * configure: Regenerated. + +2004-12-18 H.J. Lu + + * Makefile.in (top_builddir): Set to `.'. + (OUTPUT_OPTION): Removed. + (LIBTOOL): New. + (LTLIBOBJS): New. + (EXTRA_LTOFILES): New. + (FLAGS_TO_PASS): Add EXTRA_LTOFILES. + (all): Remove stamp-picdir. + (LTCOMPILE): New. + (.c.lo): New rule. + (REQUIRED_LTOFILES): New. + (CONFIGURED_LTOFILES): New. + ($(TARGETLIB)): Check .libs for PIC object files. Depend on + $(REQUIRED_LTOFILES) $(EXTRA_LTOFILES) $(LTLIBOBJS). + (stamp-picdir): Completely removed. + (maint-missing): Pass $(REQUIRED_LTOFILES) + $(CONFIGURED_LTOFILES) instead of (REQUIRED_OFILES) + $(CONFIGURED_OFILES) + (maint-buildall): Depend on $(REQUIRED_LTOFILES) + $(CONFIGURED_LTOFILES). + (mostlyclean): Also remove *.lo .libs. + Run "make maint-deps". + + * aclocal.m4: Include ../libtool.m4. + + * config.table: Don't check --enable-shared. + + * configure.ac (AC_PROG_LIBTOOL): Add. + (AC_PROG_CC_C_O): Removed. + (OUTPUT_OPTION): Removed. + (NO_MINUS_C_MINUS_O): Removed. + (ltpexecute): New substitute. + (LIBOBJS): Cleanup. + * configure: Regenerated. + + * maint-tool: Updated for .lo/libtool. + +2004-12-11 Ben Elliston + + * configure.ac: Invoke AC_CHECK_SIZEOF for sizeof (int). + * configure: Regenerate. + * config.in: Likewise. + +2004-12-07 DJ Delorie + + * splay-tree.c (splay_tree_delete_helper): Redesign the logic so + that recursion (and thus large stack space) is not needed. + +2004-11-29 Matt Kraai + + * pex-unix.c: Fix the spelling of longjmp. + +2004-11-23 Ian Lance Taylor + + PR other/18623 + * cp-demangle.c (d_call_offset): Remove useless local variables + offset and virtual_offset. + * cplus-dem.c (ada_demangle): Remove useless local variable + at_start_name. + (demangle_template): Remove useless local variable start. + +2004-11-19 Roger Sayle + + * objalloc.c, strsignal.c, xstrerror.c: Include "config.h" before + "ansidecl.h" to avoid redeclaration errors with native compilers. + * regex.c: Protect config.h from multiple inclusion. + +2004-11-12 Mike Stump + + * Makefile.in (libiberty.html): Fix html generation. + +2004-09-08 Adam Nemet + + * vasprintf.c: Accept __va_copy in addition to va_copy. + +2004-09-03 Paolo Bonzini + + * configure: Regenerate. + +2004-09-02 Paolo Bonzini + + * configure.ac: Do not enable multilibs for build-side libiberty. + +2004-06-29 Danny Smith + + * lrealpath.c (lrealpath): Add _WIN32 support. + +2004-06-28 Zack Weinberg + + * cp-demangle.h: Declare cplus_demangle_operators, + cplus_demangle_builtin_types, cplus_demangle_mangled_name, and + cplus_demangle_type as static if IN_GLIBCPP_V3. + +2004-06-28 Ian Lance Taylor + + PR other/16240 + * cp-demangle.c (d_expr_primary): Check for a failure return from + cplus_demangle_type. + * testsuite/demangle-expected: Add test case. + +2004-05-31 Danny Smith + + * pex-win32.c (fix_argv): Expand comment. + +2004-05-25 Daniel Jacobowitz + + * Makefile.in: Add .NOEXPORT. + +2004-04-29 Douglas B Rupp + + * mkstemps.c (mkstemps) [VMS]: Remove special open option. Update + copyright. + +2004-04-26 Maciej W. Rozycki + + * configure.ac (UNSIGNED_64BIT_TYPE): Unquote the definition. + * configure: Regenerate. + +2004-04-22 Richard Henderson + + * hashtab.c: Include limits.h, stdint.h, ansidecl.h. + (CHAR_BIT): Provide default. + (struct prime_ent, prime_tab): New. + (higher_prime_index): Rename from higher_prime_number, return index. + (htab_mod_1): New. + (htab_mod, htab_mod_m2): Use it. + (htab_create_alloc, htab_create_alloc_ex): Store prime index. + (htab_expand): Likewise. + * configure.ac: Check for stdint.h. + (UNSIGNED_64BIT_TYPE): New define and checks to fill it in. + * config.in, configure: Rebuild. + +2004-04-13 Ian Lance Taylor + + * strerror.c: Include config.h, and redefine sys_nerr and + sys_errlist, before including ansidecl.h and libiberty.h. + +2004-04-13 Jeff Law + + * hashtab.c (htab_remove_elt_with_hash): New function. + (htab_remove_elt): Implement in terms of htab_remove_elt_with_hash. + +2004-03-31 Richard Henderson + + * hashtab.c (htab_size): Move to top of file; mark inline. + (htab_elements): Likewise. + (htab_mod, htab_mod_m2): New. + (htab_delete): Refactor htab->size and htab->entries. + (htab_empty): Likewise. + (find_empty_slot_for_expand): Use htab_size, htab_mod, htab_mod_m2. + (htab_find_with_hash, htab_find_slot_with_hash): Likewise. + (htab_clear_slot): Use htab_size, htab_elements. + (htab_traverse_noresize, htab_traverse): Likewise. + +2004-03-17 Ian Lance Taylor + + * pex-unix.c (pexecute): Use vfork instead of fork, with + appropriate changes to make this safe. + * pex-common.h (STDERR_FILE_NO): Define. + + * Makefile.in: Clean up REQUIRED_OFILES and CONFIGURED_OFILES for + an 80 column screen. Run maint-deps. + +2004-03-09 Kelley Cook + + * configure.ac: Bump version to 2.59. Apply suggested autoupdates. + * acconfig.h: Delete redundant file. + * config.in: Regenerate. + * configure: Regenerate. + +2004-03-09 Hans-Peter Nilsson + + * configure: Regenerate for config/accross.m4 correction. + +2004-03-07 Andreas Jaeger + + * testsuite/test-demangle.c: Include and for + prototypes. + (main): Initialize style. + +2004-02-24 Ian Lance Taylor + + * cp-demangle.h (enum d_builtin_type_print): Add D_PRINT_UNSIGNED, + D_PRINT_UNSIGNED_LONG, D_PRINT_LONG_LONG, + D_PRINT_UNSIGNED_LONG_LONG, D_PRINT_FLOAT. + * cp-demangle.c (cplus_demangle_builtin_types): Change char and + short types to D_PRINT_DEFAULT. Change other integer types to use + new D_PRINT_* values where appropriate. Change float types to + D_PRINT_FLOAT. + (d_print_comp) [LITERAL, LITERAL_NEG]: Handle new D_PRINT_* + values. + * testsuite/demangle-expected: Adjust two test cases. + + * cp-demangle.c (d_print_function_type): Print a space before the + parenthesis around the function type in more cases. + * testsuite/demangle-expected: Adjust one test case. + + * cp-demangle.c (d_print_comp) [UNARY]: Don't emit extra + parentheses around a cast. + * testsuite/demangle-expected: Adjust two test cases to match new + output. + + * cp-demangle.c (__cxa_demangle): Pass DMGL_PARAMS to d_demangle. + + * cp-demangle.c (d_print_comp) [RESTRICT, VOLATILE, CONST]: Don't + push more than one of the same CV-qualifier on the top of the + stack. + (d_print_comp) [ARRAY_TYPE]: If the array itself is CV-qualified, + move the CV-qualifiers to apply to the element type instead. + (d_print_array_type): When checking the modifiers, keep looking + past ones which have been printed already. + * testsuite/demangle-expected: Add three test cases. + +2004-02-23 Ian Lance Taylor + + * cp-demangle.c (__cxa_demangle): Adjust last patch to handle + empty string correctly. + + * cp-demangle.c (__cxa_demangle): It is not an error if status is + not NULL. It is an error if the mangled name is the same as a + built-in type name. + (main): If IN_GLIBCPP_V3 is defined, test __cxa_demangle rather + than cplus_demangle_v3. + + * dyn-string.c: Remove test of IN_LIBGCC2 and IN_GLIBCPP_V3 and + the associated #define of RETURN_ON_ALLOCATION_FAILURE. + +2004-02-16 Matt Kraai + + * regex.c: Include . + (regcomp): Cast i to int. + (regerror): Add ATTRIBUTE_UNUSED to parameter preg. + +2004-01-25 Ian Lance Taylor + + * configure.ac: Add m4_pattern_allow(LIBOBJS). + * configure: Regenerate. + +2004-01-22 DJ Delorie + + * Makefile.in: Convert to ./ throughout. Rebuild dependencies + with explicit build rules. + (VPATH): Remove. + (.c.o): Poison. + * configure.ac (pexecute, LIBOBJS): Add ./ . + * maint-tool: Build dependencies with explicit rules. + +2004-01-15 Kazu Hirata + + * strdup.c (strdup): Constify the argument. + +2004-01-14 Loren J. Rittle + + * Makefile.in (distclean): Remove config.cache. + +2004-01-13 Daniel Jacobowitz + + * cp-demangle.c (d_make_comp): DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE + takes two parameters. + * cp-demint.c (cplus_demangle_fill_component): Likewise. + +2004-01-12 Ian Lance Taylor + + * cp-demangle.c: Include "cp-demangle.h". If IN_GLIBCPP_V3 is + defined, rename some functions which are to become static via + #define. + (CP_STATIC_IF_GLIBCPP_V3): Define. + (struct d_operator_info): Move definition to cp-demangle.h, and + rename to demangle_operator_info. Change all uses. + (enum d_builtin_type_print): Move definition to cp-demangle.h. + (struct d_builtin_type_info): Move definition to cp-demangle.h, + and rename to demangle_builtin_type_info. Change all uses. + (enum d_comp_type): Move definition to include/demangle.h, and + rename to demangle_component_type, and change all enums to start + with DEMANGLE_COMPONENT_ instead of D_. Change all uses. + (struct d_comp): Move definition to include/demangle.h, and rename + to demangle_component. Change all uses. + (struct d_info): Move definition to cp-demangle.h. + (cplus_demangle_fill_name): New function. + (cplus_demangle_fill_extended_operator): New function. + (cplus_demangle_fill_ctor): New function. + (cplus_demangle_fill_dtor): New function. + (d_make_empty): Remove type parameter. Change all callers. + (d_make_name): Use cplus_demangle_fill_name. + (d_make_extended_operator): Use + cplus_demangle_fill_extended_operator. + (d_make_ctor): Use cplus_demangle_fill_ctor. + (d_make_dtor): Use cplus_demangle_fill_dtor. + (cplus_demangle_mangled_name): Rename from d_mangled_name. Make + non-static by default. Change all callers. + (cplus_demangle_operators): Rename from d_operators. Change all + uses. Make non-static by default. Add sentinel at end of array. + (d_operator_name): Adjust initialization of high for new sentinel + in cplus_demangle_operators. + (cplus_demangle_builtin_types): Rename from d_builtin_types. + Change all uses. Make non-static by default. Change initializer + to use D_BUILTIN_TYPE_COUNT instead of magic number 26. + (cplus_demangle_type): Rename from d_type. Make non-static by + default. Change all callers. + (cplus_demangle_init_info): Rename from d_init_info. Make + non-static by default. Change all callers. + * cp-demangle.h: New file. + * cp-demint.c: New file. + * Makefile.in: Rebuild dependencies. + (CFILES): Add cp-demint.c. + (REQUIRED_OFILES): Add cp-demint.o. + +2004-01-09 Kelley Cook + + * configure.in: Rename file to ... + * configure.ac: ... this. + * Makefile.in: Update a comment for above change. + * README: Likewise. + * config.in: Regenerate. + +2004-01-02 Ian Lance Taylor + + * cp-demangle.c (d_encoding): When DMGL_PARAMS is not set, strip + CV-qualifiers from D_COMP_LOCAL_NAME right subtree. + * cplus-dem.c (demangle_arm_hp_template): Set DMGL_PARAMS when + demangling template parameters. + * testsuite/test-demangle.c (fail): New static function. + (main): Support new options in input file: --no-params, + --is-v3-ctor, and --is-v3-dtor. + * testsuite/demangle-expected: Add --no-params to most tests, and + add the correct result when parameters are not demangled. Add + some simple tests for V3 constructor/destructor recognition. + +2003-12-25 Kaveh R. Ghazi + + * cp-demangle.c (is_ctor_or_dtor): Fix error in last change. + +2003-12-22 Daniel Jacobowitz + + PR debug/13272 + * Makefile.in (lbasename.o): Depend on filenames.h. + * lbasename.c: Include "filenames.h" instead of defining + its macros locally. + +2003-12-22 Ian Lance Taylor + + * cp-demangle.c (CP_DYNAMIC_ARRAYS): Define if compiler supports + dynamic arrays. + (struct d_operator_info): Add len field. + (struct d_builtin_type_info): Add len and java_len fields. + (struct d_standard_sub_info): Add simple_len, full_len, and + set_last_name_len fields. + (struct d_comp): Add len field to s_string. + (struct d_info): Add send, did_subs, and expansion fields. + (d_append_string_constant): Define. + (d_append_string): Remove. Change all users to use + d_append_string_constant or d_append_buffer instead. + (d_make_sub): Add len parameter. Change all callers. + (d_name): Increase expansion when substituting std::. + (d_unqualified_name): Increase expansion for an operator. + (d_number): Don't use multiplication for negative numbers. + (d_identifier): Make sure there are enough characters in the + string for the specified length. Adjust expansion for an + anonymous namespace. + (d_operators): Initialize len field. + (d_special_name, d_ctor_dtor_name): Increase expansion. + (d_builtin_types): Initialize len and java_len fields. + (d_type): Increase expansion for a builtin type. + (d_cv_qualifiers): Increase expansion for each qualifier. + (d_bare_function_type): Decrease expansion when removing single + void parameter. + (d_template_param): Increment did_subs. + (d_expression): Increase expansion for an operator. + (d_expr_primary): Decrease expansion for a type we will print + specially. + (standard_subs): Initialize new fields. + (d_substitution): Increment did_subs when doing a normal + substitution. Increase expansion for a special substitution. + (d_print): Add estimate parameter. Change all callers. + (d_print_comp) [D_COMP_NAME]: Handle C++ case inline. + (d_print_comp) [D_COMP_BINARY]: Use length to avoid strcmp call. + (d_print_java_identifier): Rename from d_print_identifier. Handle + only Java case. Change caller. + (d_init_info): Change return type to void. Change all callers. + Initialize send, did_subs, and expansion fields. Do not + initialize comps and subs fields. + (d_demangle): Ifdef CP_DYNAMIC_ARRAYS, allocate comps and subs + arrays on stack. Make an estimate of the length of the demangled + name. Ifdef CP_DEMANGLE_DEBUG, print estimation failures. + (is_ctor_or_dtor): Ifdef CP_DYNAMIC_ARRAYS, allocate comps and + subs arrays on stack. + +2003-12-20 Ian Lance Taylor + + * cp-demangle.c (d_identifier): In Java mode, skip an optional '$' + after the identifier. + * testsuite/demangle-expected: Add test case. + +2003-12-19 Ian Lance Taylor + + Fix for PR c++/13447: + * cp-demangle.c (enum d_comp_type): Add D_COMP_LOCAL_NAME. + (d_dump, d_make_comp): Handle D_COMP_LOCAL_NAME. + (is_ctor_dtor_or_conversion): Handle D_COMP_LOCAL_NAME like + D_COMP_QUAL_NAME. + (is_ctor_or_dtor): Likewise. + (d_local_name): Use D_COMP_LOCAL_NAME rather than + D_COMP_QUAL_NAME. + (d_print_comp) [D_COMP_LOCAL_NAME]: New. + (d_prinT_comp) [D_COMP_TYPED_NAME]: If the left tree is + D_COMP_LOCAL_NAME, pull any qualifiers off its right subtree. + (d_print_mod_list): Handle D_COMP_LOCAL_NAME. + * testsuite/demangle-expected: Add two test cases. + + * cp-demangle.c (d_print_function_type): Clear the global modifier + list when printing the modifiers, not just when printing the + function parameters. + * testsuite/demangle-expected: Add two test cases. + +2003-12-15 Ian Lance Taylor + + * cp-demangle.c (d_print_function_type): Print the function + parameters with no modifiers. + * testsuite/demangle-expected: Add test case. + + * cp-demangle.c (d_demangle): If DMGL_PARAMS is not set, don't + expect that we've read the entire string. + (is_ctor_or_dtor): Don't expect that we've read the entire + string--reverse patch of 2003-11-29. + +2003-12-15 Brendan Kehoe + + * libiberty/Makefile.in (floatformat.o): Add dependency on + config.h to accompany change of 2003-12-03. + +2003-12-15 Ian Lance Taylor + + Fix handling of constructor/destructor of standard substitution: + * cp-demangle.c (struct d_standard_sub_info): Define. + (d_substitution): Add prefix argument. Change all callers. + Rework handling of standard substitutions to print full name when + qualifying a constructor/destructor, or when DMGL_VERBOSE is set. + * testsuite/demangle-expected: Add test case. + + Fix handling of negative literal constants: + * cp-demangle.c (enum d_comp_type): Add D_COMP_LITERAL_NEG. + (d_dump, d_make_comp): Handle D_COMP_LITERAL_NEG. + (d_expr_primary): Use D_COMP_LITERAL_NEG for a negative number. + (d_print_comp): Handle D_COMP_LITERAL_NEG. + * testsuite/demangle-expected: Add test case. + +2003-12-04 Ian Lance Taylor + + * cp-demangle.c (IS_UPPER, IS_LOWER): Define. + (d_last_char): Define new macro. + (d_make_name): Reject an empty name. + (d_prefix, d_unqualified_name, d_type): Use new IS_* macros. + (d_substitution, d_print_identifier): Likewise. + (d_print_comp) [D_COMP_OPERATOR]: Likewise. + (d_print_comp) [D_COMP_TEMPLATE]: Use new d_last_char macro. + (d_print_mod) Use new d_last_char macro. + (d_print_cast): Use new d_last_char macro. + (is_ctor_or_dtor): Don't leak memory. + + Fix handling of member function modifiers: + * cp-demangle.c (enum d_comp_type): Add D_COMP_RESTRICT_THIS, + D_COMP_VOLATILE_THIS, and D_COMP_CONST_THIS. + (d_dump): Dump new d_comp_type values. + (d_make_comp): Accept new d_comp_type values. + (has_return_type): Only accept _THIS variants of qualifiers. + (d_encoding): Without DMGL_PARAMS, only remove _THIS variants of + qualifiers. + (d_cv_qualifiers): Add member_fn parameter. Change all callers. + (d_print_comp) [D_COMP_TYPED_NAME]: Rather than removing + qualifiers and printing them at the end, add _THIS qualifiers to + the modifier list. + (d_print_comp) [D_COMP_*_THIS]: New cases. + (d_print_comp) [D_COMP_PTRMEM_TYPE]: Remove special handling of + qualifiers. + (d_print_mod_list): Add suffix parameter. Change all callers. + Keep walking the list even if the current modifier has been + printed. + (d_print_mod): Handle new _THIS qualifiers. + (d_print_function_type): Handle new _THIS qualifiers when deciding + whether to print a parenthesis. Put a space before the + parenthesis in some cases. Call d_print_mod_list again at the + end, passing suffix as 1. + (is_ctor_or_dtor): Look for new _THIS qualifiers. + * testsuite/demangle-expected: Add test case. + + Fix for PR gcc/13304: + * cp-demangle.c (d_print_comp) [D_COMP_TEMPLATE]: If the character + before the '<' is itself a '<', insert a space. + (d_print_cast): Likewise. + * testsuite/demangle-expected: Add test case. + + Fix for PR gcc/13244: + * cp-demangle.c (d_print_comp) [D_COMP_BINARY]: Wrap an expression + which uses the '>' operator in an extra layer of parens. + * testsuite/demangle-expected: Add test case. + +2003-12-03 Ian Lance Taylor + + * floatformat.c: Include "config.h" and if available. + (INFINITY, NAN): Define if not defined by . + (floatformat_to_double): Handle NaN, infinity, and denormalized + numbers. + (floatformat_from_double): Likewise. + (ieee_test): In debugging code, use little endian rather than big + endian. Correct tests to handle NaN and to check correct sign of + zero. Omit m68k extended test. + (main): Add more debugging cases. + +2003-11-29 Ian Lance Taylor + + * cp-demangle.c (d_demangle): Only return success if we consumed + the entire demangled string. + (is_ctor_or_dtor): Likewise. + + * testsuite/demangle-expected: Revert one part of 2003-06-26 patch + to restore expected result of EDG test case to original expected + result. + +2003-11-26 Ian Lance Taylor + + * cp-demangle.c (struct d_print_mod): Add templates field. + (d_make_builtin_type): Check for NULL type. + (d_make_extended_operator): Check for NULL name. + (d_make_ctor, d_make_dtor): Likewise. + (d_mangled_name): Add top_level parameter. Change all callers. + (d_encoding): If DMGL_PARAMS is not set, strip off initial + CV-qualifiers. + (d_type): Check some return values we rely on. + (d_bare_function_type, d_array_type): Likewise. + (d_pointer_to_member_type, d_template_args): Likewise. + (d_add_substitution): Fail if argument is NULL. + (d_print_resize): Check whether buf is NULL. + (d_print_comp): Save current templates list with each modifier. + Don't pass the modifier list down when printing a template. + (d_print_cast): Don't pass the modifier list down when printing a + template. + (d_print_mod_list): Temporarily set templates list while printing + a modifier. + (d_print_mod): Check that buf is not NULL before using it. + (d_print_function_type): Print parens if there is no modifier. + (d_init_info): Permit as many substitutions as there are + characters in the mangled name. + * testsuite/demangle-expected: Add two new test cases. + +2003-11-25 Ian Lance Taylor + + * cp-demangle.c (java_demangle_v3): Pass DMGL_PARAMS to + d_demangle. + +2003-11-22 Ian Lance Taylor + + * cp-demangle.c (d_encoding): Add top_level parameter. Change all + callers. + (print_usage): Display new -p option. + (long_options): Add --no-params. + (main): Accept and handle -p. + +2003-11-21 Ian Lance Taylor + + * cp-demangle.c (has_return_type): Skip qualifiers when checking + whether we have a template. + * testsuite/demangle-expected: Add four new tests. + +2003-11-20 Ian Lance Taylor + + * testsuite/demangle-expected: Minor changes to match output of + new demangler: adjust whitespace in four tests, and change order + of qualifiers in one test. + + * cp-demangle.c: Complete rewrite. + +2003-11-19 Mark Mitchell + + * cp-demangle.c (demangle_type): Correct thinko in substitution + processing. + +2003-11-18 Ian Lance Taylor + + * cp-demangle.c (demangle_operator_name): Remove space before + "sizeof". + (demangle_type_ptr): Put qualifiers in the right place. Handle + qualifiers in pointer to member specially. + (demangle_type): Handle qualifiers for pointer or reference + specially. Handle function type. + (demangle_local_name): Save and restore caret around demangling of + initial encoding. + + * testsuite/test-demangle.c (main): Don't pass DMGL_VERBOSE to + cplus_demangle. + + * testsuite/Makefile.in (test-demangle): Depend upon libiberty.a. + +2003-10-31 Andreas Jaeger + + * floatformat.c (floatformat_always_valid): Add unused attribute. + +2003-10-30 Josef Zlomek + + Jan Hubicka + * vasprintf.c (int_vasprintf): Pass va_list by value. + Use va_copy for copying va_list. + (vasprintf): Pass va_list by value. + +2003-10-30 Josef Zlomek + + * hashtab.c (htab_find_slot_with_hash): Decrease n_deleted + instead of increasing n_elements when inserting to deleted slot. + +2003-10-20 J. Brobecker + + * cplus-dem.c (demangle_template): Register a new Btype only + when needed. + * testsuite/demangle-expected: Add a new test. + +2003-10-16 H.J. Lu + + * testsuite/demangle-expected: Update the expected output of + _GLOBAL__I__Z2fnv. + +2003-10-02 Daniel Jacobowitz + + * strerror.c: Revert last change. Declare static sys_nerr + and sys_errlist using different names. + +2003-10-01 Daniel Jacobowitz + + * strerror.c: Don't provide or reference sys_errlist if + strerror is available. + +2003-10-01 H.J. Lu + + * configure.in: Check if $MAKEINFO is missing. + * configure: Regenerated. + +2003-09-24 Daniel Jacobowitz + + * configure.in: Use AC_PROG_CPP_WERROR. + * configure: Regenerated. + +2003-09-22 Andrew Cagney + + * floatformat.c (floatformat_i387_ext_is_valid): New function. + (floatformat_always_valid): New function. + (floatformat_i387_ext): Initialize new "is_valid" field to + "floatformat_i387_ext_is_valid". + (floatformat_ieee_single_little): Initialize "is_valid" field to + floatformat_always_valid. + (floatformat_ieee_double_big): Ditto. + (floatformat_ieee_double_little): Ditto. + (floatformat_ieee_double_little): Ditto. + (floatformat_ieee_double_littlebyte_bigword): Ditto. + (floatformat_i960_ext): Ditto. + (floatformat_m88110_ext): Ditto. + (floatformat_m88110_harris_ext): Ditto. + (floatformat_arm_ext_big): Ditto. + (floatformat_arm_ext_littlebyte_bigword): Ditto. + (floatformat_ia64_spill_big): Ditto. + (floatformat_ia64_spill_little): Ditto. + (floatformat_ia64_quad_big): Ditto. + (floatformat_ia64_quad_little): Ditto. + (floatformat_ia64_quad_little): Ditto. + (floatformat_is_valid): Call "is_valid". + +2003-09-15 Andrew Cagney + + * floatformat.c (get_field): Make "data" constant. + (floatformat_is_valid, floatformat_to_double): Make "from" + constant, fix casts. + (floatformat_from_double): Make "from" constant. + +2003-09-15 Daniel Jacobowitz + + * floatformat.c (floatformat_is_valid): New function. + (get_field, put_field): Correct comments. + +2003-09-06 Josef Zlomek + + * fibheap.c (fibheap_replace_key_data): Change type of OKEY to + FIBHEAPKEY_T. + +2003-09-02 John David Anglin + + PR bootstrap/12100 + * aclocal.m4 (AC_LANG_FUNC_LINK_TRY): Define. + * configure: Rebuilt. + +2003-08-27 Daniel Jacobowitz + + * aclocal.m4: Include acx.m4 and no-executables.m4. + (libiberty_AC_FUNC_STRNCMP): Use AC_LIBOBJ. + (LIB_AC_PROG_CC): Remove. + * configure.in: Update AC_PREREQ to 2.57. Use GCC_NO_EXECUTABLES. + Use AC_PROG_CC and set ac_libiberty_warn_cflags instead of using + LIB_AC_PROG_CC. Use AC_LIBOBJ. Call AC_ISC_POSIX later, only if + performing link tests. + * configure: Regenerated. + +2003-08-12 Nathanael Nerode + + * cp-demangle.c: Clarify what package(s) this is part of. + +2003-07-05 Danny Smith + + * pex-win32.c (pexecute): Mark parameters this_pname and + temp_base as unused. Remove unused variables retries, + sleep_interval. Initialize org_stdin, org_stdout. + (pwait): Mark parameter flags as unused. + +2003-07-02 Danny Smith + + * pex-win32.c (fix_argv): Ensure that the executable pathname + uses Win32 backslashes. + (pexecute): Cast away constness when assigning *errmsg_arg. + +2003-06-26 H.J. Lu + + * testsuite/demangle-expected: Add more GNU V3 testcases. + +2003-06-22 Zack Weinberg + + * safe-ctype.c: Use HOST_CHARSET_ASCII and HOST_CHARSET_EBCDIC, + not HC_ASCII and HC_EBCDIC. + Add documentation in form expected by gather-docs. + * hex.c: Use HOST_CHARSET, not hand-coded check of character set. + * Makefile.in, functions.texi: Regenerate. + +2003-06-21 Zack Weinberg + + * safe-ctype.c: Separate out EOF==-1 check. Use HOST_CHARSET + for charset determination. + +2003-06-19 Dara Hazeghi + + * configure.in: Add check for malloc.h needed by + m68k for function free(). + * configure: Regenerated. + * config.in: Add HAVE_MALLOC_H. + * hashtab.c: include malloc.h were available for + free(). + +2003-06-09 Albert Chin-A-Young + + PR bootstrap/10974 + * physmem.c: Update comment. + * configure.in: Modify test for _system_configuration for older + AIX systems. + + * config.in, configure: Regenerated. + +2003-06-05 John David Anglin + + PR other/10810 + * test-demangle.c (getline): Fix fence-post error. + +2003-06-03 Nick Clifton + + * asprintf.c: Change comment to note that -1 is returned upon + error. + * vasprintf.c: Likewise. + (vasprintf): Return -1 upon error. + * functions.texi: Document changes to asprintf and vasprintf. + +2003-05-19 Kelley Cook + + * config.table: Accept i[345867]86 variant. + +2003-05-15 Jim Blandy + + * hex.c (_hex_value): Make this unsigned. + (hex_value): Update documentation for new return type. hex_value + now expands to an unsigned int expression, to avoid unexpected + sign extension when we store it in a bfd_vma, which is larger than + int on some platforms. + * functions.texi: Regenerated. + +2003-05-07 Josef Zlomek + + * splay-tree.c (splay_tree_predecessor): Fix comment. + (splay_tree_successor): Fix comment. + +2003-05-07 Jason Merrill + + * hashtab.c (iterative_hash): New fn. + * configure.in: Add AC_C_BIGENDIAN_CROSS. + * aclocal.m4: Include accross.m4. + * configure, config.in: Regenerate. + +2003-05-04 Kaveh R. Ghazi + + * configure.in (AC_CHECK_FUNCS): Don't make multiple calls. + * configure: Regenerate. + +2003-05-03 Carlo Wood + + * cp-demangle.c: Fix typo in "char_traints" string-literal. + +2003-04-22 Kaveh R. Ghazi + + * vsnprintf.c (vsnprintf): Don't pad string with extra nulls. + (main): Test that we don't write too much data. + +2003-04-16 Kaveh R. Ghazi + + * configure.in (funcs, AC_CHECK_FUNCS): Add snprintf and + vsnprintf. + * snprintf.c, vsnprintf.c: New files. + * Makefile.in (CFILES): Add snprintf.c and vsnprintf.c. + (CONFIGURED_OFILES): Add snprintf.o and vsnprintf.o. + Regenerate dependencies. + + * functions.texi, configure, config.in: Regenerated. + +2003-04-15 Kaveh R. Ghazi + + * mempcpy.c, stpcpy.c, stpncpy.c: New files. + * configure.in (funcs, AC_CHECK_FUNCS): Add mempcpy, stpcpy + and stpncpy. + * Makefile.in (CFILES): Add mempcpy.c, stpcpy.c and stpncpy.c. + (CONFIGURED_OFILES): Add mempcpy.o, stpcpy.o and stpncpy.o. + Regenerate dependencies. + + * functions.texi, configure, config.in: Regenerated. + +2003-04-15 Kaveh R. Ghazi + + * argv.c: Fix comments. + * calloc.c: Don't unnecessarily include "libiberty.h". + (bzero): Add prototype. + * floatformat.c: Include "ansidecl.h", rely on ANSI_PROTOTYPES. + * getcwd.c (getcwd): Use standard definition to avoid conflicts + with system headers. + * hashtab.c (htab_traverse): Delete unused variables. + * rename.c: Include "ansidecl.h". + (rename): Use standard definition to avoid conflicts with system + headers. + * strsignal.c: Rely on ANSI_PROTOTYPES. + * strstr.c: Check GNUC >= 2, not GNUC == 2. + * vfprintf.c: Include "ansidecl.h", rely on ANSI_PROTOTYPES. + * vprintf.c: Include "ansidecl.h" earlier, rely on + ANSI_PROTOTYPES. + * vsprintf.c: Include "ansidecl.h" earlier, rely on + ANSI_PROTOTYPES and possibly include . + + * Makefile.in: Regenerate dependencies. + +2003-04-15 DJ Delorie + + * maint-tool (deps): Scan for headers in $srcdir also. + +2003-04-15 Kaveh R. Ghazi + + PR target/10338 + PR bootstrap/10198 + PR bootstrap/10140 + * getopt.c (exchange, _getopt_initialize): Use mempcpy not + __mempcpy. + * regex.c (regerror): Likewise. + +2003-04-14 Roger Sayle + + * argv.c: Use ANSI_PROTOTYPES instead of __STDC__. + * memchr.c: Likewise. + * strcasecmp.c: Likewise. + * strncasecmp.c: Likewise. + * strncmp.c: Likewise. + * xatexit.c: Likewise. + * xmalloc.c: Likewise. + + * copysign.c: Use traditional function declaration instead of DEFUN. + * sigsetmask.c: Likewise. + + * memcmp.c: Both of the above, ANSI_PROTOTYPES and DEFUN. + * memset.c: Likewise. + + * memcpy.c: ANSI_PROTOTYPES, DEFUN and prototype bcopy. + * memmove.c: Likewise. + +2003-04-14 Roger Sayle + + * strdup.c (strdup): Tweak implementation to use memcpy. + +2003-04-14 Kaveh R. Ghazi + + * configure.in (HAVE_UINTPTR_T): Always define. + * configure: Regenerated. + +2003-03-23 Alexandre Oliva + + * Makefile.in (MULTIOSDIR): New macro. Use $(CC) $(LIBCFLAGS) + instead of $$CC alone. + (install_to_tooldir): Use it. + +2003-17-03 Jan Hubicka + + * hashtab.c (htab_traverse_noresize): Break out from ... + * hashtab.c (htab_traverse): ... here. + +2003-12-03 Jan Hubicka + + * hashtab.c (htab_expand): Fix warning. + + * hashtab.c (htab_expand): Compute the size of hashtable based + on the number of elements actually used. + (htab_traverse): Call htab_expand when table is too empty. + +2003-03-11 Carlo Wood + + * cplus-dem.c (demangle_integral_value): Correction to reflect + patch of 2002-01-10 in order to also make negative multi-digits + without leading underscore work. + +2003-03-03 Mark Mitchell + + * cplus-dem.c: Add license exception to copyright notice. + +2003-02-27 Kaveh R. Ghazi + + * physmem.c: Formatting changes from upstream. + +2003-02-24 Danny Smith + + * physmem.c (physmem_total): Add _WIN32 support. + (physmem_available): Likewise. + +2003-02-24 Rainer Orth + + * physmem.c (physmem_total) [HAVE_GETSYSINFO]: Test for + GSI_PHYSMEM. + (physmem_available) [HAVE_TABLE]: Test for TBL_VMSTATS. + +2003-02-22 Kaveh R. Ghazi + + * configure.in: Check for sys/systemcfg.h and + _system_configuration. + * physmem.c: Add support for AIX. Tweek formatting as per + upstream coreutils beta. + +2003-02-22 Kaveh R. Ghazi + Richard Earnshaw + Geoffrey Keating + + * configure.in: Check for sys/sysctl.h and sysctl. + * physmem.c: Add support for *bsd and darwin. + * Makefile.in: Generate depedency for physmem.o. + +2003-02-21 Rainer Orth + + * physmem.c (physmem_total) [HAVE_GETSYSINFO]: Use getsysinfo on + Tru64 UNIX. + (physmem_available) [HAVE_TABLE && HAVE_SYS_TABLE_H]: Use table on + Tru64 UNIX. + + * configure.in (AC_CHECK_HEADERS): Check for sys/sysinfo.h, + machine/hal_sysinfo.h, sys/table.h. + (checkfuncs, AC_CHECKFUNCS): Check for getsysinfo, table. + * configure, config.in: Regenerate. + +2003-02-21 Kaveh R. Ghazi + + * configure.in: Check for sys/sysmp.h and sysmp. + * physmem.c: Pull upstream copy, add support for irix6. + + * config.in, configure: Regenerated. + +2003-02-21 Kaveh R. Ghazi + + * physmem.c (physmem_total, physmem_available): De-ANSI-fy. + * configure.in (AC_CHECK_FUNCS): Add pstat_getstatic and + pstat_getdynamic. + +2003-02-20 Kaveh R. Ghazi + + * Makefile.in (CFILES): Add physmem.c. + (REQUIRED_OFILES): Add physmem.o. + * configure.in: Check for sys/pstat.h. + (checkfuncs): Add pstat_getstatic and pstat_getdynamic. + * physmem.c: New file, copied from textutils. + + * config.in, configure: Regenerated. + +2003-02-20 Daniel Jacobowitz + + * Makefile.in (CFILES): Add lrealpath.c. + (REQUIRED_OFILES): Add lrealpath.o. + (lrealpath.o): Add rule. + * aclocal.m4 (libiberty_NEED_DECLARATION): Add. + * configure.in: Add realpath and canonicalize_file_name to + checkfuncs and AC_CHECK_FUNCS. Use libiberty_NEED_DECLARATION + for canonicalize_file_name. + * lrealpath.c: New file. + * make-relative-prefix.c: Update documentation. + (make_relative_prefix): Simplify. Use lbasename and lrealpath. + * config.in: Regenerated. + * configure: Regenerated. + * functions.texi: Regenerated. + +2003-02-20 jmc + + * cplus_dem.c: Fix typo: intializes -> initializes. + +2003-02-20 Alexandre Oliva + + * configure.in: Propagate ORIGINAL_LD_FOR_MULTILIBS to + config.status. + * configure: Rebuilt. + +2003-02-13 Daniel Jacobowitz + + Fix PR c++/7612. + * cplus-dem.c (demangle_signature): Call string_delete. + Remove extra string_init. + (demangle_arm_hp_template): Call string_delete instead of + string_clear. Add missing string_delete call. + (demangle_qualified): Add missing string_delete call. + (do_type): Remove unused variable btype. Add missing string_delete + call. Call string_delete instead of string_clear. + (demangle_fund_type): Move variable btype inside of the switch + statement. Add missing string_delete call. + (do_arg): Call string_delete instead of string_clear. Remove extra + string_init. + (demangle_nested_args): Free work->previous_argument. + +2003-02-12 Kaveh R. Ghazi + + * acconfig.h: New file. Add uintptr_t. + * config.in: Regenerated. + +2003-02-04 Joseph S. Myers + + * libiberty.texi: Update to GFDL 1.2. + +2003-01-30 Christian Cornelssen + + * Makefile.in (libiberty_topdir): New subst. + (mkinstalldirs): Redefine in terms of the above. + * configure.in: AC_SUBST it. + * configure: Regenerate. + +2003-01-28 Christian Cornelssen + + * Makefile.in (all-subdir, check-subdir, installcheck-subdir) + (info-subdir, install-info-subdir, clean-info-subdir) + (dvi-subdir, install-subdir, etags-subdir, mostlyclean-subdir) + (clean-subdir, distclean-subdir, maintainer-clean-subdir): + Pass $(FLAGS_TO_PASS). + +2003-01-27 Alexandre Oliva + + * Makefile.in (install_to_tooldir): Instead of $(MULTISUBDIR), use + /`$$CC -print-multi-os-directory`. + +2003-01-26 Daniel Jacobowitz + + * hashtab.c (htab_create_alloc_ex): New function. + (hatab_set_functions_ex): New function. + (htab_delete, htab_expand): Support alternate allocation functions. + +2003-01-24 Christopher Faylor + + * configure.in: Remove special pex-cygwin consideration. + * configure: Regenerate. + * pex-cygwin.c: Remove. + * Makefile.in: Remove pex-cygwin.[co] lines. + +2003-01-24 Zack Weinberg + + * Makefile.in (CFILES): Add pex-*.c. + (REQUIRED_OFILES): Change pexecute.o to @pexecute@ + (CONFIGURED_OFILES): Add pex-*.o. + (TEXIFILES): Add pexecute.txh. + (pexecute.o): Delete rule. + (pex-cygwin.o, pex-djgpp.o, pex-mpw.o, pex-msdos.o, pex-os2.o, + pex-unix.o, pex-win32.o): New rules. + * configure.in: Change AC_INIT argument to xmalloc.c. + Compute appropriate pexecute implementation and substitute it + as @pexecute@. + + * pexecute.c: Split up into... + * pex-cygwin.c, pex-djgpp.c, pex-mpw.c, pex-msdos.c, pex-os2.c, + pex-unix.c, pex-win32.c, pex-common.h, pexecute.txh: ... these + new files. + + * functions.texi: Regenerate. + * configure: Regenerate. + +2003-01-20 Josef Zlomek + + * hashtab.c (htab_expand): Fix allocation of new entries. + +2003-01-09 Christian Cornelssen + + * Makefile.in (FLAGS_TO_PASS): Also pass DESTDIR. + + * Makefile.in (install_to_libdir, install_to_tooldir): Add a + mkinstalldirs command. + +2002-12-04 Danny Smith + + * make-relative-prefix.c (HAVE_HOST_EXECUTABLE_SUFFIX): + Define for hosts with HOST_EXECUTABLE_SUFFIX. + +2002-11-24 Nick Clifton + + * make-relative-prefix.c (make_relative_prefix): Ensure return + string is empty before using strcat to construct it. + +2002-11-22 Daniel Jacobowitz + + * Makefile.in: Add make-relative-prefix.c. + * make-relative-prefix.c: New file. + * functions.texi: Rebuilt. + +2002-11-16 Jakub Jelinek + + * md5.c (md5_process_block): Avoid `function-like macro "F{G,H,I}" must be + used with arguments in traditional C' warnings. + +2002-10-16 Jakub Jelinek + + * config.table: Use mh-s390pic for s390x too. + +2002-10-06 Andreas Jaeger + + * libiberty/cplus-dem.c (ada_demangle): Get rid of unneeded + variable and of strict-aliasing warning. + (grow_vect): Use char as first parameter. + +2002-09-22 Kaveh R. Ghazi + + * Makefile.in (all): Fix multilib parallel build. + +2002-09-19 John David Anglin + + * cp-demangle.c (demangling_new): Cast 0 to enum. + (demangle_char): Cast return of strdup to char *. + (is_gnu_v3_mangled_ctor): Cast 0 to enum. + (is_gnu_v3_mangled_dtor): Likewise. + * cplus-dem.c (grow_vect): Cast return of xrealloc to void *. + (work_stuff_copy_to_from): Cast return of xmalloc to char **. + * fibheap.c (fibnode_new): Cast return of xcalloc to fibnode_t. + * md5.c (md5_process_bytes): Cast results back to const void *. + (md5_process_block): Add cast to const md5_uint32 *. + * regex.c (re_compile_fastmap): Cast enum to UCHAR_T. + * safe-ctype.c (L, XL, U, XU, D, P, _, C, Z, M, V, T, S): Add cast to + unsigned short. + * splay-tree.c (splay_tree_xmalloc_allocate): Cast return of xmalloc + to void *. + * vasprintf.c (int_vasprintf): Cast return of malloc to char *. + +2002-09-19 Nick Clifton + + * README: Update email addresses for bugs and patches. + +2002-09-10 Mike Stump + + * splay-tree.c (splay_tree_successor): Fix comments. + +2002-09-11 Zack Weinberg + + * cplus-dem.c: Code under #ifdef MAIN moved to gcc/cp/cxxfilt.c. + * testsuite/Makefile.in: Adjust for test-demangle. + * testsuite/regress-demangle: Deleted. + * testsuite/test-demangle.c: New file. + * testsuite/demangle-expected: Change \$ to $ throughout, now that + this file is not being read by a shell script. + +2002-09-05 Roger Sayle + + * regex.c: Only use "#pragma alloca" on AIX when not using gcc. + +2002-08-07 DJ Delorie + + * regex.c (re_error_msgid): Just use a simple array of strings. + (re_compile_pattern): Compensate. + (re_comp): Likewise. + (re_comp): Likewise. + (regerror): Likewise. + +2002-07-29 Neil Booth + + * cplus-dem.c (PREPEND_BLANK): Remove. + +2002-07-10 Jason Merrill + + * cp-demangle.c (demangle_identifier): Support extended Unicode + characters. + +2002-07-08 Kaveh R. Ghazi + + * cp-demangle.c (demangle_v3_with_details): Wrap in + !defined IN_GLIBCPP_V3. + +2002-07-01 Mark Mitchell + + * cp-demangle.c (demangle_operator_name): Add type_arg parameter. + Set it for the "st" operator. + (demangle_expression): Handle expressions with types as arguments. + +2002-06-30 Douglas Rupp + + * configure.in (OUTPUT_OPTION,NO_MINUS_C_MINUS_O): Configure. + * Makefile.in (OUTPUT_OPTION): Use. + +2002-06-22 Peter Breitenlohner + + * Makefile.in (install_to_libdir): Add $(DESTDIR). + (install_to_tooldir): Likewise. + +2002-06-17 Douglas Rupp + + * lbasename.c: Add 2002 to copyright. + (IS_DIR_SEPARATOR): Remove VMS junk. + +2002-06-05 Geoffrey Keating + + * hashtab.c (htab_create): New stub function for backward + compatibility. + (htab_try_create): Likewise. + +2002-06-03 Geoffrey Keating + + * hashtab.c (htab_create): Delete. + (htab_try_create): Delete. + (htab_create_alloc): New. + (htab_delete): Support user-specified memory allocation. + (htab_expand): Likewise. + +2002-05-22 Roman Lechtchinsky + + * configure.in: Fix typo in the code checking for sys_errlist. + * configure: Regenerated. + +2002-05-13 Andreas Schwab + + * config.table: Use mh-x86pic also for x86-64. + +2002-05-08 Alexandre Oliva + + * configure.in (ORIGINAL_LD_FOR_MULTILIBS): Preserve LD at + script entry, and set LD to it when configuring multilibs. + * configure: Rebuilt. + +2002-05-07 Mark Mitchell + + * configure.in (AC_TYPE_PID_T): Use it. + * configure: Regenerated. + * getruntime.c: Include . + * waitpid.c: Likewise. Use pid_t, not int, as the type of "pid". + +2002-04-09 Richard Henderson + + * hashtab.c (higher_prime_number): Use 7 as minimum. + (find_empty_slot_for_expand): Don't compute hash2 unless needed. + (htab_find_slot_with_hash): Likewise. + +2002-04-01 Phil Edwards + + * cp-demangle.c (__cxa_demangle): Also protect with IN_GLIBCPP_V3. + (is_gnu_v3_mangled_ctor, is_gnu_v3_mangled_ctor): Conditionally + not compile if IN_GLIBCPP_V3 defined. + * dyn-string.c: Also allow IN_GLIBCPP_V3 to change allocation scheme. + +2002-03-30 Bryce McKinlay + + * cp-demangle.c (java_demangle_v3): Don't try to release "demangled" + if it is NULL. + +2002-03-27 DJ Delorie + + * hex.c: Add documentation. + (_hex_value): Provide non-ASCII empty table. + (hex_init): Initialize the non-ASCII table. + * functions.texi: Regenerate. + +2002-03-27 Mark Mitchell + + * dyn-string.c: Add libgcc exception to copyright notice. + +2002-03-26 H.J. Lu (hjl@gnu.org) + + * config.table: Support --with-build-subdir. + * configure.in: Likewise. + * configure: Rebuild. + +2002-03-18 Stuart Griffith + + * strtod.c (strtod): Increment 8 chars, not 7, when `infinity' + seen. + +2002-03-12 Mark Mitchell + + * cp-demangle.c: Add libgcc exception to cp-demangle.c copyright + notice. + +2002-03-11 Douglas B Rupp + + * xatexit.c [VMS]: Include stdlib.h and unixlib.h. + +2002-03-06 Jim Blandy + + * splay-tree.c (splay_tree_xmalloc_allocate, + splay_tree_xmalloc_deallocate): Use K&R-style definitions, not + prototyped definitions. Mark `data' arguments as unused. + +2002-03-06 Andrew Cagney + + * floatformat.c (floatformat_arm_ext_big): Delete definition. + +2002-03-04 Phil Edwards + + * configure.in: Add --enable-install-libiberty option. + * Makefile.in (INSTALLED_HEADERS): New variable. + (install_to_libdir): Possibly also copy headers. + * configure: Regenerated. + +2002-03-04 Neil Booth + + * xmalloc.c (xmalloc_fail): Clarify error message further. + +2002-03-03 Neil Booth + + * xmalloc.c (xmalloc_fail): Clarify error message. + +2002-02-22 Jim Blandy + + * splay-tree.c (splay_tree_xmalloc_allocate, + splay_tree_xmalloc_deallocate): New functions. + (splay_tree_new): Call splay_tree_new_with_allocator, passing the + above functions and a dummy data pointer. + (splay_tree_new_with_allocator): New function. + (splay_tree_delete_helper, splay_tree_delete, splay_tree_insert, + splay_tree_remove): Use the splay tree's allocation and + deallocation functions. + +2002-02-19 Scott Snyder + + * testsuite/demangle-expected: Add test case for infinite loop in + demangler. + * cplus-dem.c (demangle_arm_hp_template): Stop trying to demangle + if do_type() doesn't make any progress --- prevents an infinite + loop. + +2002-02-18 Carlo Wood + + PR c++/5390 + * cplus-dem.c (demangle_integral_value): Accept multi-digit + numbers that do not start with an underscore; This is needed + for integer template parameters. This doesn't break anything + because multi-digit numbers are never followed by a digit. + * testsuite/demangle-expected: Corrected all mangled test + cases with multi-digit template parameters: g++ 2.95.x does + not generate underscores around these parameters. + +2002-02-05 Jason Merrill + + * cplus-dem.c (flags): Add DMGL_VERBOSE + (cplus_demangle_v3_p): Remove. + (demangle_it): Add DMGL_TYPES to passed flags. + * cp-demangle.c (cplus_demangle_v3_all): Remove. + (cplus_demangle_v3_type): Remove. + (cplus_demangle_v3): Add options parm. + +2002-02-02 H.J. Lu (hjl@gnu.org) + + * cp-demangle.c (cp_demangle_type): Do not protect with + IN_LIBGCC2. + (cplus_demangle_v3_all): New. + (cplus_demangle_v3): Call cplus_demangle_v3_all. + (cplus_demangle_v3_type): Call cplus_demangle_v3_all. + + * cplus-dem.c (cplus_demangle_v3_p): New function pointer. + Initialized to cplus_demangle_v3. + (cplus_demangle_with_style): Call cplus_demangle_v3_p instead + of cplus_demangle_v3. + (main): Set cplus_demangle_v3_p to cplus_demangle_v3_type for + command line symbol. + + * testsuite/regress-demangle: Pass the mangled name at the + command line. + +2002-02-01 H.J. Lu + + * cp-demangle.c (cp_demangle_type): Call demangling_new with + DMGL_GNU_V3. + +2002-01-31 Phil Edwards + + * cp-demangle.c: Revert yesterday's change. + +2002-01-31 Adam Megacz + + * gcc/libiberty/configure.in: Treat mingw the same as cywin + wrt HAVE_SYS_ERRLIST. + +2002-01-30 Phil Edwards + + * cp-demangle.c (cp_demangle_type): Do not protect with IN_LIBGCC2. + (cplus_demangle_v3): Mimic __cxa_demangle and fall back on + cp_demangle_type. + * testsuite/demangle-expected: New gnu-v3 test. + +2002-01-22 Momchil Velikov + + * configure.in (variable detection): Use arrays of unspecified + size instead of plain integers. + +2002-01-18 DJ Delorie + + * Makefile.in (TESTLIB): New. This library is for future + testsuites. + (CFILES, REQUIRED_OFILES, CONFIGURED_OFILES): Re-alphabetize, + break down by letter. + (REQUIRED_OFILES): List long-to-compile files first. + (maint-deps): New, target for updating dependencies. + (dependencies): Update. + * maint-tool: Add dependency-generating option. + * configure.in: Check for _doprnt even if we're not providing it. + * configure: Regenerate. + + * _doprnt.c: Modifications to allow compiling on any platform. + * copysign.c: Likewise. + * putenv.c: Likewise. + * setenv.c: Likewise. + * vsprintf.c: Likewise. + +2002-01-15 Douglas B Rupp + + * mkstemps.c (mkstemps): On VMS, open temp file with option + that causes it to be deleted when closed. + +2002-01-02 Kaveh R. Ghazi + + * cp-demangle.c (long_options): Const-ify. + * cplus-dem.c (long_options): Likewise. + + * cplus-dem.c (mystrstr): Delete. All callers changed to use + strstr instead. + +2001-12-31 Ira Ruben + + * aclocal.m4 (libiberty_AC_FUNC_STRNCMP): Use anon mmap as 2nd try. + * configure: Regenerated. + +2001-12-24 Douglas B. Rupp + + * configure.in (uintptr_t): Use AC_CHECK_TYPE. + * configure: Regenerated. + +2001-12-12 Craig Rodrigues + + PR other/2719 + * cplus-dem.c (consume_count): Treat negative count as an error. + * testsuite/demangle-expected: Added testcase. + +Tue Dec 11 07:08:57 2001 Douglas B. Rupp + + * configure.in: Hardcode that vfork works on VMS host. + * configure: Regenerated. + +2001-12-06 Richard Henderson + + * cplus-dem.c (libiberty_demanglers): Add no_demangling case. + (cplus_demangle): Support no_demangling. + +2001-11-27 Zack Weinberg + + * _doprnt.c: Moved here from gcc/doprint.c. Adjust to build + in libiberty context. Fix typo in leading comment. + * configure.in: Fix various AC_DEFINEs so autoheader works. + If any of vprintf, vsprintf, vfprintf is missing from libc, + then AC_REPLACE_FUNCS(_doprnt). + +2001-11-26 DJ Delorie + Daniel Jacobowitz + + * Makefile.in (stamp-h): Depend on Makefile for proper + serialization. + (*-subdir): Depend on config.h for proper serialization. + +2001-11-26 DJ Delorie + + * configure.in: Check for alloca.h (for regex.c and putenv.c). + * configure: Regenerate. + * config.h: Add HAVE_ALLOCA_H. + +2001-11-16 Kaveh R. Ghazi + + * regex.c: Check defined(__STDC__) || defined(ALMOST_STDC) || + defined(HAVE_STRINGIZE) to determine whether ISO CPP token pasting + is available. + +Thu Nov 15 11:06:25 2001 Jeffrey A Law (law@cygnus.com) + + * config.in (HAVE_UINTPTR_T): Provide autoconf stub. + * configure.in (HAVE_UINTPTR_T): Test for system defining + uintptr_t and define HAVE_UINTPTR_T appropriately. + * regex.c (uintptr_t): Do not provide a definition if the + system provided one. + + * regex.c (PREFIX): Provide an alternate definition for + non-ANSI/ISO compilers. + (ARG_PREFIX): Likewise. + +2001-11-12 Jim Meyering + + * obstack.c (_): Honor the setting of ENABLE_NLS. Otherwise, + this code would end up calling gettext even in packages built + with --disable-nls. + * getopt.c (_): Likewise. + * regex.c (_): Likewise. + +2001-11-03 Alan Modra + + * configure.in: Cope with missing makeinfo. + * configure: Regenerate. + +2001-10-22 Kaveh R. Ghazi + + * hex.c (hex_init): Provide empty stub. + + * hex.c (hex_init): Delete. + (_hex_value): Const-ify and initialize at compile-time. + +2001-10-19 H.J. Lu + + * Makefile.in ($(TARGETLIB)): Also generate pic/$(TARGETLIB) if + necessary. + +2001-10-17 DJ Delorie + + * argv.c, asprintf.c, choose-temp.c, concat.c, cplus-dem.c, + ffs.c, fnmatch.txh, getruntime.c, make-temp-file.c, + mkstemps.c, pexecute.c, random.c, strsignal.c, vasprintf.c: + Improve manual formatting. + * functions.texi: Regenerate. + +2001-10-15 DJ Delorie + + * Makefile.in (TEXIFILES): Add fnmatch.txh. + (maint-undoc): New. + maint-tool: Add "undoc" tool. + * alloca.c, argv.c, asprintf.c, choose-temp.c, concat.c, + fdmatch.c, ffs.c, getruntime.c, insque.c, lbasename.c, + make-temp-file.c, mkstemps.c, pexecute.c, random.c, spaces.c, + strerror.s, strsignal.c, strtol.c, vasprintf.c: Add or update + documentation. + * fnmatch.txh: New. + * functions.texi: Regenerate. + +2001-10-10 Joseph S. Myers + + * bcmp.c, setenv.c: Use "nonzero" instead of "non-zero". + * strtod.c: Use "ISO C" instead of "ANSI C". + * functions.texi: Regenerate. + +2001-10-07 Joseph S. Myers + + * alloca.c, clock.c, getcwd.c, getpagesize.c, getpwd.c, index.c, + libiberty.texi, memchr.c, putenv.c, rindex.c, strchr.c, strdup.c, + strerror.c, strrchr.c, strstr.c, strtod.c, tmpnam.c, vfork.c, + xatexit.c, xmalloc.c, xstrerror.c: Improve manual formatting. Fix + spelling. Give names to function arguments in documentation. Use + (void) prototypes in documentation. + * functions.texi: Regenerate. + +2001-10-07 Kaveh R. Ghazi + + * argv.c (buildargv, tests, main): Const-ify. + * cp-demangle.c (operator_code): Likewise. + * cplus-dem.c (optable, libiberty_demanglers, + cplus_demangle_set_style, cplus_demangle_name_to_style, + print_demangler_list): Likewise. + * hashtab.c (higher_prime_number): Likewise. + * strcasecmp.c (charmap): Likewise. + * strerror.c (error_info, strerror, main): Likewise. + * strncasecmp.c (charmap): Likewise. + * strsignal.c (signal_info): Likewise. + +2001-09-29 DJ Delorie + + * configure: Regenerate. + +2001-09-28 Kaveh R. Ghazi + + * concat.c: Include stdlib.h. + +2001-09-27 Eli Zaretskii + + * libiberty.texi: (Top level): Add syncodeindex pg. Add + @dircategory and @direntry directives. Add @finalout. + (many nodes): Lose the next,prev,up pointers on the @nide line. + (Using, Supplemental Functions, Replacement Functions): Fix + markup. + (Functions): Move around, to allow makeinfo to build the manual + without next,prev,up pointers in thye node lines. + (Licenses): Fix typos. + + * index.c, rindex.c, strchr.c, strerror.c, strrchr.c, strstr.c, + strtol.c, xatexit.c, xexit.c, xmalloc.c: Fix spelling and markup. + * functions.texi: Regenerate. + + * copying-lib.texi: Lose the next,prev,up pointers on the @node + line. + +2001-09-27 DJ Delorie + + * configure.in: Don't use in-tree texinfo, because libiberty must + be built before it. Check for makeinfo version 4 or higher. + * functions.texi: Regenerate. + +2001-09-20 DJ Delorie + Phil Edwards + + * configure.in (MAKEINFO, PERL): Detect these. + (--enable-maintainer-mode): Add. + * configure: Regenerate. + * Makefile.in (MAKEINFO, PERL): Define. + (libiberty.info, libiberty.dvi, libiberty.html): New. + (CFILES): Add bsearch.c. + (CONFIGURED_OFILES): New, list of objects configure might add. + (maint-missing, maint-buildall): New, for maintainers only. + (clean, mostlyclean): Add info/dvi/html files. + * libiberty.texi, copying-lib.texi, obstacks.texi, functions.texi: New. + * gather-docs: New, for maintainers. + * maint-tool: New, for maintainers. + * alloca.c, atexit.c, basename.c, bcmp.c, bcopy.c, bsearch.c, + bzero.c, calloc.c, clock.c, configure.in, configure, getcwd.c, + getpagesize.c, getpwd.c, index.c, memchr.c, memcmp.c, memcpy.c, + memmove.c, memset.c, putenv.c, rename.c, rindex.c, setenv.c, + sigsetmask.c, strcasecmp.c, strchr.c, strdup.c, strerror.c, + strncasecmp.c, strncmp.c, strrchr.c, strstr.c, strtod.c, strtol.c, + tmpnam.c, vfork.c, vprintf.c, waitpid.c, xatexit.c, xexit.c, + xmalloc.c, xmemdup.c, xstrdup.c, xstrerror.c: Add or update + documentation. + +2001-09-25 Kaveh R. Ghazi + + * concat.c (reconcat): Fix for traditional C. + +2001-09-24 Kaveh R. Ghazi + + * concat.c (reconcat): New function. + +2001-09-17 Kaveh R. Ghazi + + * concat.c (vconcat_length, vconcat_copy, concat_length, + concat_copy, concat_copy2): New functions. + (concat): Use vconcat_length/vconcat_copy. + + * alloca.c (libiberty_optr, libiberty_nptr, libiberty_len): + Define. + +2001-09-04 Kaveh R. Ghazi + + * asprintf.c: Don't define USE_STDARG. Use VPARAMS, VA_OPEN, + VA_FIXEDARG & VA_CLOSE. + + * vasprintf.c: Check HAVE_STRING_H when including string.h. + (checkit): Delete redundant prototype. Add ATTRIBUTE_PRINTF_1. + Use VA_OPEN, VA_FIXEDARG & VA_CLOSE. Free allocated string. + +2001-08-27 Kaveh R. Ghazi + + * concat.c (concat): Use VPARAMS, VA_OPEN, VA_FIXEDARG & VA_CLOSE. + +2001-08-23 Ulrich Drepper + + * regex.c (truncate_wchar): Use wcrtomb not wctomb. + +2001-08-23 Ulrich Drepper + + * posix/regex.c [_LIBC] (convert_mbs_to_wcs): Use __mbrtowc + instead of mbrtowc. + [_LIBC]: Use __iswctype instead of iswctype, __wcslen instead of + wcslen, and __wcscoll instead of wcscoll. + +2001-08-22 Matt Kraai + + * fibheap.c (fibheap_init, fibnode_init): Remove. + (fibheap_new, fibnode_new): Use xcalloc to allocate and + initialize memory. + (fibheap_insert): Remove check for node allocation failure. + +2001-08-21 Richard Henderson + + * Makefile.in (fibheap.o): Depend on config.h. + * fibheap.c: Tidy formatting. Use config.h.` Rearrange some + functions for inlining. + +Tue Aug 21 12:35:04 2001 Christopher Faylor + + * configure.in: Need to set HAVE_SYS_ERRLIST and HAVE_SYS_NERR whenever + hosting on cygwin. + * configure: Regenerate. + +2001-08-20 Andrew Cagney + + * floatformat.c (floatformat_m88110_ext): Remove #ifdef + HARRIS_FLOAT_FORMAT. + (floatformat_ia64_spill_little, floatformat_ia64_quad_little) + (floatformat_ia64_spill_big, floatformat_ia64_quad_big) + (floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword) + (floatformat_m88110_harris_ext): New float formats. + +2001-08-20 Daniel Berlin + + * fibheap.c: New file. Fibonacci heap. + + * Makefile.in (CFILES): Add fibheap.c. + (REQUIRED_OFILES): Add fibheap.o. + (fibheap.o): Add dependencies for fibheap.o. + +2001-08-17 Christopher Faylor + + * configure.in: Always set HAVE_SYS_ERRLIST when targetting cygwin. + * configure: Regenerate. + +2001-08-16 Richard Henderson + + * hashtab.c (htab_hash_string): New. + +2001-08-13 Andrew Cagney + + * floatformat.c (floatformat_ieee_double_littlebyte_bigword): Fix + name. + +2001-08-12 Isamu Hasegawa + + * regex.c (wcs_regex_compile): Use appropriate string + to compare with collating element. + Fix the padding for the alignment. + +2001-08-10 Andrew Cagney + + * lbasename.c (lbasename): Change function definition to return a + const char pointer. + +2001-08-07 Jason Merrill + + * cp-demangle.c (demangle_special_name): "GR" -> "reference temporary + for". + +2001-08-03 Richard Henderson + + * Makefile.in (concat.o): Depend on config.h. + +2001-07-30 Andreas Jaeger + + * concat.c: Include "config.h". + +2001-07-30 Andreas Jaeger + + * regex.c: Declare wcs functions only if compiling with + MBS_SUPPORT. + Don't use #elif for traditional C. + +2001-07-23 Ulrich Drepper + + * regex.c: Revamp memory allocation for WCHAR functions to + not use too much stack. + +2001-07-30 Andreas Jaeger + + * regex.c: Declare wcs functions only if compiling with + MBS_SUPPORT. + Don't use #elif for traditional C. + +2001-07-25 Daniel Jacobowitz + + * Makefile.in (regex.o): Add dependency on config.h. + +2001-07-18 Andreas Schwab + + * regex.c (WORDCHAR_P) [WCHAR]: Also return true for the + underscore character. + +2001-07-18 Ulrich Drepper + + * regex.c: Limit string length printed in debug messages to 100 + chars. + +2001-07-18 Andreas Jaeger + + * regex.c: Place under LGPL version 2.1. + +2001-07-10 Jeff Johnston + + * Makefile.in: Add support for regex code. + * regex.c: New file. + +2001-07-05 Mark Klein + + * Makefile.in: Add ffs.c dependency. + * configure.in: Add ffs.c. + * ffs.c: New file. + +2001-06-18 Richard Henderson + + * concat.c: Include . + +2001-06-11 Loren J. Rittle + + bootstrap/3106 + * strerror.c (sys_nerr): Hide the OS header version. + * strsignal.c (sys_nsig): Likewise. + +2001-06-10 Richard Henderson + + * concat.c: Include string.h. Fix int vs size_t usage. + Simplify the iteration loops. Use memcpy. + +2001-05-16 Matt Kraai + + * partition.c: Fix misspelling of `implementation'. + +2001-05-09 Thiemo Seufer + + * md5.c (md5_init_ctx): Declare constants as unsigned. + (md5_process_block): Likewise. + +2001-05-07 Zack Weinberg + + * cp-demangle.c (demangle_v3_with_details, + is_gnu_v3_mangled_ctor, is_gnu_v3_mangled_dtor): Use K+R style + function definition. + * ternary.c: Use K+R style function definitions. Use PTR, not + void *. Make arguments constant where possible. + +2001-05-07 Mark Mitchell + + * splay-tree.h (splay_tree_max): New function. + (splay_tree_min): Likewise. + +2001-04-15 Daniel Berlin + + * ternary.c: New file - Ternary search tree implementation. + + * Makefile.in: Add ternary.o, and ternary.c dependencies. + +2001-04-03 Zack Weinberg + + * make-temp-file.c (try): Inline. + +2001-02-28 Richard Henderson + + * Makefile.in (make-temp-file.o): Depend on config.h. + +2001-03-27 Kaveh R. Ghazi + + * memchr.c (memchr): Adjust condition to avoid infinite loop. + +2001-03-23 Jakub Jelinek + + * cp-demangle.c (demangle_discriminator): `_0' is discriminator #1, + `_' not followed by a digit is invalid. + +2001-03-22 Jim Blandy + + * cp-demangle.c (string_list_delete): Use dyn_string_delete + instead of free, to free the contents as well as the string + structure. + +2001-03-21 Zack Weinberg + + * make-temp-file.c: Always default DIR_SEPARATOR to '/'. + Don't default P_tmpdir to anything. Try /var/tmp before + /usr/tmp. + +2001-03-20 Zack Weinberg + + * choose-temp.c: Split off make_temp_file, and the code + duplicated between it and choose_temp_base, into... + * make-temp-file.c: ... here; new file. + + * Makefile.in (CFILES): Add make-temp-file.c. + (REQUIRED_OFILES): Add make-temp-file.o. + +2001-03-20 Jim Blandy + + * cp-demangle.c (struct demangling_def): New fields: + is_constructor and is_destructor. + (demangling_new): Initialize them. + (demangle_ctor_dtor_name): Set them, if we detect a constructor + or destructor. + (demangle_v3_with_details, is_gnu_v3_mangled_ctor, + is_gnu_v3_mangled_dtor): New functions. + +2001-03-20 Jason Merrill + + * cplus-dem.c (main): Skip initial $. + +2001-03-15 Michael Meissner + + * hashtab.c (higher_prime_number): Silence warning that 4294967291 + might be a signed integer under pre-ISO C systems. + +2001-03-10 Neil Booth + John David Anglin + + * libiberty/lbasename.c: New file. + * libiberty/Makefile.in: Update for lbasename. + +2001-03-06 Zack Weinberg + + * aclocal.m4 (libiberty_AC_FUNC_C_ALLOCA): New. + * configure.in: Replace all alloca logic with a simple use of + the above new macro. + * config.table: Kill *-*-beos* entry. + * config/mh-beos: Delete. + * configure, config.in: Regenerate. + + * Makefile.in (ALLOCA, HFILES): Kill. + (REQUIRED_OFILES): Add alloca.o. + (alloca.o): Depend on libiberty.h. + (argv.o): Don't depend on alloca-conf.h. + * alloca-conf.h: Delete. + * alloca.c: Include libiberty.h. Kill all #ifdef emacs + blocks. Provide the C alloca unconditionally. Use PTR where + appropriate. Make i00afunc static. + * argv.c: Don't include alloca-conf.h. + +2001-03-04 John David Anglin + + * cplus-dem.c (main): Cast enum style to int. + +2001-02-16 Loren J. Rittle + + * cplus-dem.c (main): Initialize style. + +2001-02-02 Phil Edwards + + * COPYING.LIB: Update to LGPL 2.1 from the FSF. + +2001-01-31 Bryce McKinlay + + Add support for Java demangling under the v3 ABI: + * cp-demangle.c (NAMESPACE_SEPARATOR): New define. + (struct demangling_def): Add `style' field. + (demangling_new): New parameter `style'. Set it in demangling_t. + (demangle_prefix): Use NAMESPACE_SEPARATOR. + (demangle_type_ptr): Don't emit pointer symbol if doing Java output. + (cp_demangle): New parameter `style'. Pass it to demangling_new(). + (main): Call cp_demangle with extra parameter. + (java_demangle_v3): New function. + (java_builtin_type_names): New. Table of primitive type names used + for Java demangling. + (demangle_builtin_type): Look up in java_builtin_type_names if doing + Java output. + * cplus-dem.c (cplus_demangle): Use java_demangle_v3 to do Java + demangling. + (long_options): Remove obsolete `java' option. + (main): Remove explicit handling of `java' option. Instead, pass style + parameter in cplus_demangle flags as gdb does. + * testsuite/demangle.expected: Add some Java test cases. + +2000-12-29 DJ Delorie + + * fnmatch.c: Make the note about the origins of this file more + accurate, at least until we can sync with glibc. + * getopt.c: Ditto. + * getopt1.c: Ditto. + * md5.c: Ditto. + * obstack.c: Ditto. + +2000-12-26 Michael Sokolov + + * bsearch.c: New file. + * configure.in (funcs): Add bsearch. + (AC_CHECK_FUNCS): Likewise. + * configure, config.in: Regenerate. + +2000-12-13 Michael Sokolov + + * safe-ctype.c: #include "ansidecl.h". + * strtod.c: Likewise. + +2000-12-13 Michael Sokolov + + * strtoul.c: Include safe-ctype.h, not ctype.h. + +2000-12-07 Zack Weinberg + + * safe-ctype.c: New file. + * Makefile.in (CFILES): Add safe-ctype.c. + (REQUIRED_OFILES): Add safe-ctype.o. + + * argv.c: Define ISBLANK and use it, not isspace. + * basename.c, cplus-dem.c, fnmatch.c, pexecute.c, strtod.c, + strtol.c, strtoul.c: Include safe-ctype.h, not ctype.h. Use + uppercase ctype macros. Don't test ISUPPER(c)/ISLOWER(c) + before calling TOLOWER(c)/TOUPPER(c). + +2000-12-07 Mike Stump + + * Makefile.in (distclean): When cleaning, remove testsuite. + +2000-12-05 Jason Merrill + + * cp-demangle.c (cplus_demangle_v3): Check that it's a v3 mangled + name before allocating the dyn_string. + +2000-12-04 Jason Merrill + + * cp-demangle.c: s/new_abi/v3/. + * cplus-dem.c: Likewise. + (current_demangling_style): Now auto_demangling. + (cplus_demangle): Try v3 demangling if AUTO_DEMANGLING. + (main): Use standard symbol chars for auto_demangling. + +2000-11-26 Mark Mitchell + + * hashtab.c (higher_prime_number): Use a table, rather than a + seive, to find the next prime. + +2000-11-22 H.J. Lu + + * cplus-dem.c (main): Handle gnat_demangling. + +2000-11-22 Zack Weinberg + + * aclocal.m4 (LIB_AC_PROG_CC): Moved here from configure.in. + (AC_DEFINE_NOAUTOHEADER): New - work around bug in autoheader. + * configure.in: Call AC_C_INLINE and AC_C_CONST. Use three + argument form of AC_DEFINE in dummy definitions block. Use + AC_DEFINE_NOAUTOHEADER for real definitions of things defined + in dummy block. Preload cache variables instead of bypassing + tests, where possible. + * acconfig.h: Removed. + + * xmalloc.c (xmalloc_failed): New function, does error + reporting on failed allocation. + (xmalloc, xcalloc, xrealloc): Use it. + +2000-11-21 Hans-Peter Nilsson + + * cplus-dem.c (cplus_demangle): Fix formatting. + (grow_vect): Ditto. + (ada_demangle): Ditto. + (internal_cplus_demangle): Ditto. + (mop_up): Ditto. + +2000-11-21 H.J. Lu + + * cplus-dem.c (main): Handle java_demangling. + +2000-11-19 Kaveh R. Ghazi + + * cplus-dem.c (grow_vect): Prototype. + (ada_demangle): Cast the arg of ctype macros to unsigned char. + +2000-11-15 Hans-Peter Nilsson + + * cplus-dem.c (ada_demangle): Add back ATTRIBUTE_UNUSED for + parameter `option'. + +2000-11-15 Kenneth Block + + * cplus-dem.c: Eliminate use of DEFUN, it is obsolete and cannot + be used in GCC. + +2000-11-15 Kenneth Block + + * cplus-dem.c: Add gnat demangler. Add java to demangle style + list. + +2000-11-04 Hans-Peter Nilsson + + * hashtab.c (htab_expand): Change to return int. Use calloc or + xcalloc depending on htab->return_allocation_failure. Return zero + if calloc fails. + (htab_create): Update comment to cover memory allocation. + (htab_try_create): New. + (htab_find_slot_with_hash): Return NULL if htab_expand fails. + Update comment to cover this. + +2000-11-03 Hans-Peter Nilsson + + * hashtab.c: Change void * to PTR where necessary. + (htab_create, htab_expand): Correct formatting of comment before + function. + +2000-10-22 Alex Samuel + + * cp-demangle.c (string_list_def): Add caret_position and comments. + (result_caret_pos): New macro. + (result_append_string): Rename to... + (result_add_string): ... this, and insert at caret position. + Rename throughout. + (result_append): Rename to... + (result_add): ... this, and insert at caret position. Rename + throughout. + (result_append_char): Rename to... + (result_add_char): ... this, and insert at caret position. Rename + throughout. + (result_append_space): Remove. + (string_list_new): Initialize caret position. + (result_add_separated_char): Use caret position. + (result_get_caret): New funtion. + (result_set_caret): Likewise. + (result_shift_caret): Likewise. + (result_previous_char_is_space): Likewise. + (substitution_start): Use caret position. + (substitution_add): Likewise. + (demangling_new): Initialize caret position. + (demangle_encoding): Use caret position. + (demanglin_nested_name): Put CV qualifiers after name. + (demangle_type_ptr): Use switch statement. Handle pointers to + arrays. Don't use result_append_space. Use caret position. + (demangle_type): Emit CV qualifiers after underlying type. Adjust + call to demangle_array_type. + (demangle_array_type): Add parameter to handle pointers to arrays. + +2000-10-01 Mark Mitchell + + * splay-tree.c (splay_tree_insert): Fix formatting. + +2000-09-16 Mark Mitchell + + * splay-tree.c (splay_tree_predecessor): Fix typo in comment. + +2000-09-14 Michael Sokolov + + * splay-tree.c: #include . + +2000-09-14 Hans-Peter Nilsson + + * testsuite/demangle-expected: Add two tests for anonymous + namespaces. + * cplus-dem.c (gnu_special): Handle anonymous namespaces. + +2000-09-10 Mark Mitchell + + * splay-tree.c (splay_tree_predecessor): New function. + (splay_tree_successor): Likewise. + +2000-09-10 Hans-Peter Nilsson + + * testsuite/demangle-expected: Add four tests for type_info + mangling. + * cplus-dem.c (gnu_special): Use do_type, not demangle_fund_type, + for a non-template non-qualified type_info function or node. + +2000-09-08 Alex Samuel + + * cp-demangle.c: Fix copyright banner. + +2000-09-07 Michael Sokolov + + * md5.c: #include "ansidecl.h". + +2000-09-06 Alex Samuel + + * cp-demangle.c (status_allocation_failed): Rearrange whitespace. + (demangle_type): Handle substitution candidates correctly in the + face of special substitutions. + +2000-09-05 Alex Samuel + + * cp-demangle.c (demangle_encoding): Rename variable. + (demangle_name): Rename parameter. Handle return type + suppression. + (demangle_nested_name): Rename parameter. + (demangle_prefix): Likewise. Change return type suppression. + (demangle_unqualified_name): Add parameter. Flag constructors and + conversion operators. + (demangle_special_name): Fix comment. + (demangle_type): Rename variable. + (demangle_bare_function_type): Check for missing return type and + parameter. + (demangle_class_enum_type): Rename parameter. + (demangle_discriminator): Fix misspelling in comment. + +2000-08-31 DJ Delorie + + * configure.in (Cygwin): special case cygwin only when we're + building cygwin, not when we're hosting cygwin. + +2000-09-04 Alex Samuel + + * cp-demangle.c (demangle_template_arg): Eat an `E' after an + . + +2000-09-04 Alex Samuel + + * cp-demangle.c (demangle_type_ptr): Increment position past + pointer and reference characters. + +2000-09-04 Alex Samuel + + * cp-demangle.c (demangle_nv_offset): New function. + (demangle_v_offset): Likewise. + (demangle_call_offset): Likewise. + (demangle_special_name): Update thunk demangling to comply with + ABI changes. + +2000-09-03 Alex Samuel + + * cp-demangle.c (ANONYMOUS_NAMESPACE_PREFIX): New macro. + (substitution_def): Remove template_parm_number. + (NOT_TEMPLATE_PARM): Remove. + (result_insert_string): New macro. + (result_insert): Likewise. + (result_insert_char): Likewise. + (substitution_add): Remove last parameter. Don't store template + parm number. + (BFT_NO_RETURN_TYPE): Define as NULL. + (demangle_encoding): Adjust call to demangle_bare_function_type. + (demangle_name): Adjust substitution. Adjust call to + substitution_add. + (demangle_prefix): Adjust call to substitution_add. + (demangle_identifier): Handle anonymous namespaces. + (demangle_operator_name): Change demangling of vendor-extended + operator to match ABI changes. + (demangle_type_ptr): Change parameters. Make recursive. Handle + substitutions here. + (demangle_type): Adjust calls to demangle_template_param, + substitution_add, and demangle_type_ptr. Fix substitution of + templated types. + (demangle_function_type): Change parameter to a pointer. + (demangle_bare_function_type): Likewise. Adjust insertion point. + (demangle_template_param): Remove last parameter. + (demangle_expr_primary): Remove unused variable. Adjust call to + demangle_template_param. + (is_mangled_char): Accept `$' and `.'. + * cplus-dem.c (gnu_new_abi_symbol_characters): Add '$' and '.'. + * dyn-string.c (dyn_string_insert_char): New function. + +2000-08-31 Hans-Peter Nilsson + + * testsuite/demangle-expected: Add nine tests for + underscore-after-number followed by five tests for name-signature + delimiter. + +2000-08-28 Richard Henderson + + * Makefile.in (md5.o): Depend on config.h. + +2000-08-28 Jason Merrill + + * Makefile.in (REQUIRED_OFILES): Add md5.o. + (CFILES): Add md5.c. + * md5.c: New file. + +2000-08-27 Alex Samuel + + * cp-demangle.c (demangle_name): Initialize template_p in local + name case. Don't re-add substitutions as candidates. + (demangle_nested_name): Use . + (demangle_prefix): Likewise. Don't add template names as + substitution candidates twice, or re-add a substitution or the + last prefix component. + (demangle_local_name): Adjust output format. + +2000-08-25 Alex Samuel + + * cp-demangle.c (result_add_separated_char): Change parameter to + int. + (substitution_add): Don't check for duplicates. Check if + previously allocated size is zero. + (demangle_name): Remove duplicate check for std substitution. + Clear template flag appropriately. + (demangle_prefix): Remove argument to demangle_substitution. + Don't check that template flag is already set. + (demangle_operator_name): Add pt operator. + (demangle_type): Don't treat r as built-in type. Remove argument + to demangle_substitution. Fix substitution candidate mechanics. + Handle s. Improve comments. + (demangle_template_param): Don't handle template arg lists here. + (demangle_substitution): Remove parameter. + (print_usage): Remove extra fprintf option. + +2000-08-24 Greg McGary + + * libiberty/random.c (end_ptr): Revert previous change. + +2000-08-24 Greg McGary + + * libiberty/cplus-dem.c (cplus_demangle_opname, cplus_mangle_opname, + demangle_expression, demangle_function_name): Use ARRAY_SIZE. + * libiberty/random.c (end_ptr): Likewise. + +2000-08-23 Alex Samuel + + * cp-demangle.c (result_close_template_list): Remove function. + (result_add_separated_char): New function. + (result_open_template_list): New macro. + (result_close_template_list): Likewise. + (demangle_prefix): Don't set template_p if the + prefix ends with a ctor name. + (demangle_type_ptr): Remove duplicate RETURN_IF_ERROR. + (demangle_type): Check for template args after substitution. + (demangle_template_args): Use result_open_template_list. + +2000-08-02 Zack Weinberg + + * pexecute.c: Don't use vfork. Initialize 'pid' before retry loop. + +2000-07-26 Dave Pitts + + * config/mh-openedition.h: Added -DLE370 definition. + +2000-07-26 Mark Elbrecht + + * pexecute.c (pexecute) [__MSDOS__]: Change __GO32__ to + __DJGPP__. Use P_WAIT instead of constant in the spawnv* call. + Cast program to 'char *' in errmsg_arg assignment. + (PWAIT_ERROR): Define. + (pwait): Use PWAIT_ERROR. Adjust DJGPP's status code to conform + to DJGPP's WIF* macros. + +2000-07-27 RodneyBrown + Jeff Law + + * getcwd.c: Include string.h, stdlib.h for prototypes + + * Makefile.in (rename.o, waitpid.o): Depend on config.h + * rename.c: Include config.h, unistd.h + * waitpid.c: Include config.h, sys/wait.h + +2000-07-24 Hans-Peter Nilsson + + * cplus-dem.c (work_stuff_copy_to_from): New. + (delete_non_B_K_work_stuff): New. + (delete_work_stuff): New. + (mop_up): Break out work_stuff partly destruction to + delete_non_B_K_work_stuff. + (iterate_demangle_function): New. + (demangle_prefix): Call iterate_demangle_function instead of + demangle_function_name. Leave handling of name-signature + __-delimiters to iterate_demangle_function. + (demangle_integral_value): Strip an optional + following underscore cautiously. Handle negative numbers. + +2000-07-24 Daniel Berlin + + * cplus-dem.c (demangle_signature): Change if (GNU_DEMANGLING) to + if (AUTO_DEMANGLING || GNU_DEMANGLING) + +2000-07-21 Alex Samuel + + * cp-demangle.c (demangle_ctor_dtor_name): Remove not-in-charge + allocating ctor mangling. + (demangle_array_type): Handle empty and non-constant array length. + +2000-07-23 Michael Sokolov + Jeff Law + + * configure.in (AC_CHECK_HEADERS): Add time.h. + (AC_HEADER_TIME): Add check. + * configure, config.in: Regenerate. + * getruntime.c: Portably #include and/or . + + * configure.in (AC_CHECK_HEADERS): Add limits.h. + * configure, config.in: Regenerate. + * sort.c: Portably #include and/or . + * strtol.c, strtoul.c: #include "config.h". Portably #include + and/or . + * Makefile.in (strtol.o, strtoul.o): Update dependencies. + + * aclocal.m4 (libiberty_AC_DECLARE_ERRNO): New macro. + * configure.in (libiberty_AC_DECLARE_ERRNO): Add check. + * configure, config.in: Regenerate. + * pexecute.c, strtol.c, strtoul.c: Declare errno if necessary. + + * cp-demangle.c, mkstemps.c: #include . + +2000-07-21 Mike Stump + + * Makefile.in (xexit.o): Add dependency for config.h in xexit.c. + * (vasprintf.o): Add dependency for config.h in vasprintf.c. + +2000-07-21 Kaveh R. Ghazi + + * cp-demangle.c (cp_demangle_type): Wrap in IN_LIBGCC2. + + * setenv.c (setenv): Initialize variable `ep'. + + * sigsetmask.c (abort): Prototype. + + * vasprintf.c: Include config.h. Check ANSI_PROTOTYPES, not + __STDC__ for stdarg.h include. + (int_vasprintf): Prototype. + (checkit): Prototype. Use VPARAMS/ANSI_PROTOTYPES/VA_START in + definition. Cast `global_total_width' in comparison. + (main): Prototype. Return a value. + + * vfork.c (fork): Prototype. + + * xexit.c: Include config.h. + +2000-07-20 Joseph S. Myers + + * cplus-dem.c (demangle_fund_type): Make 'dec' an unsigned int, + and print it with %u. + +2000-07-17 Hans-Peter Nilsson + + * testsuite/regress-demangle (failed test): Show result and + expected output. + +2000-07-07 Andrew Haley + + * cplus-dem.c (main): fflush() after emitting last char before + waiting for input. + +2000-06-28 Alex Samuel + + * cp-demangle.c (demangle_encoding): Accept no substitutions. + (demangle_name): Handle followed by + . + (demangle_type): Follow special substitutions with + + (demangle_subtitution): Set template_p for special substitutions. + (main): Fix typos. + +2000-06-27 Alex Samuel + + * cp-demangle.c (demangle_special_name): Swap base and derived + class when demangling construction vtables. + +2000-06-21 Alex Samuel + + * cp-demangle.c: Don't include ctype.h. + (IS_DIGIT): New macro. + (IS_ALPHA): Likewise. Use IS_DIGIT and IS_ALPHA throughout + instead of isdigit and isalpanum. + (demangling_def): Make name and next const pointers. + (STATUS_ALLOCATION_FAILED): New status code. + (dyn_string_append_space): Handle failure in + dyn_string_append_char. + (int_to_dyn_string): Likewise. Change return value to status_t. + (string_list_new): Handle failure of dyn_string_init. + (result_close_template_list): Change return type to status_t. + Handle failure in dyn_string_append. + (result_push): Change return value to status_t. Handle failure in + string_list_new. Handle failure of result_push throughout. + (substitution_add): Change return value to status_t. Handle + dyn_string failures. Handle failure of substitution_add + throughout. + (template_arg_list_new): Return NULL on allocation failure. + (result_append_string): Return STATUS_ALLOCATION_FAILED on error. + Handle error result throughout. + (result_append): Likewise. + (result_append_char): Likewise. + (result_append_space): Likewise. + (demangling_new): Make argument a const pointer. Handle + allocation failures. + (demangle_template_args): Handle failure in template_arg_list_new + and result_close_template_list. + (demangle_discriminator): Return if int_to_dyn_string fails. + (cp_demangle): Likewise. + (cp_demangle_type): New function. + (cplus_demangle_new_abi): Don't call dyn_string_delete. Abort on + memory allocation failure. + (main): Likewise. + * dyn-string.c (RETURN_ON_ALLOCATION_FAILURE): Define if + IN_LIBGCC2. + (dyn_string_init): Change return value to int. Handle + RETURN_ON_ALLOCATION_FAILURE case. + (dyn_string_new): Handle RETURN_ON_ALLOCATION_FAILURE case. + (dyn_string_release): Delete the dyn_string. + (dyn_string_resize): Handle RETURN_ON_ALLOCATION_FAILURE case. + (dyn_string_copy): Change return type to int. + (dyn_string_copy_cstr): Likewise. + (dyn_string_prepend): Likewise. + (dyn_string_prepend_cstr): Likewise. + (dyn_string_insert): Likewise. + (dyn_string_insert_cstr): Likewise. + (dyn_string_append): Likewise. + (dyn_string_append_cstr): Likewise. + (dyn_string_append_char): Likewise. + (dyn_string_substring): Likewise. + +2000-06-09 Zack Weinberg + + * cp-demangle.c (demangle_operator_name): Add spaces before + names beginning with a letter: delete, delete[], new, new[], + sizeof. + (demangle_special_name): Handle TF and TJ . + +Thu Jun 8 18:52:24 2000 Philippe De Muyter + + * cp-demangle.c (template_arg_list_new): Revert previous PARAMS patch. + +Thu Jun 8 09:25:54 2000 Philippe De Muyter + + * cp-demangle.c (stdio.h): File included unconditionaly. + (template_arg_list_new): Parameter list is PARAMS ((void)), not (). + * dyn-string.c (stdio.h): File included. + * partition.c (partition_print): No `&' needed to take the address of + a function. + +2000-06-07 Kaveh R. Ghazi + + * configure.in (ac_libiberty_warn_cflags): Add -pedantic. + + * choose-temp.c (try, choose_temp_base, make_temp_file): Constify. + + * cp-demangle.c (demangle_char): Change parameter from char to int. + (demangle_expression, demangle_expr_primary): Remove extra + semi-colon in prototype. + + * dyn-string.c (dyn_string_append_char): Change parameter from + char to int. + + * memcmp.c (memcmp): Constify. + + * mkstemps.c (gcc_uint64_t): Mark GNUC `long long' case with + __extension__. + + * partition.c (elem_compare): Prototype. Don't cast away + const-ness. + + * setenv.c (setenv): Use braces to avoid ambiguous `else'. + +2000-06-07 Kaveh R. Ghazi + + * Makefile.in (cp-demangle.o): Depend on $(INCDIR)/demangle.h. + + * cp-demangle.c: Include demangle.h. + (template_arg_list_new): DeANSIfy. + (cp_demangle): Make static and add prototype. + (operator_code, operators): Constify. + (demangle_operator_name): Likewise for variables `p1', `p2' and `p'. + +2000-06-05 Alex Samuel + + * cp-demangle.c (demangle_prefix): Cast argument to isdigit to + unsigned char. + (demangle_unqualified_name): Likewise. + (demangle_number_literally): Likewise. + (demangle_type): Likewise. + (demangle_substitution): Likewise. + (is_mangled_char): Likewise, for isalnum. + +2000-06-04 Alex Samuel + + * Makefile.in (CFILES): Add cp-demangle.c and dyn-string.c. + (REQUIRED_OFILES): Add cp-demangle.o and dyn-string.o. + (cp-demangle.o): New dependency. + (dyn-string.o): Likewise. + + * dyn-string.c: Move here from gcc/dyn-string.c. Add new functions. + + * cplus-dem.c (libiberty_demanglers): Add initializer for new-ABI + demangler. + (cplus_demangle): Call cplus_demangle_new_abi if in new-ABI + demangling mode. + (gnu_new_abi_symbol_characters): New function. + (main): Use gnu_new_abi_symbol_characters. * cp-demangle.c: New + file. + * cp-demangle.c: New file. + +Tue May 30 16:45:25 2000 Andrew Cagney + + * floatformat.c: Add name to each floatformat field. + +Tue May 30 15:07:52 2000 Jeffrey A Law (law@cygnus.com) + + * Makefile.in (objalloc.o): Depend on config.h + +2000-05-29 Zack Weinberg + + * hashtab.c, partition.c, sort.c, xmemdup.c: Include string.h + if HAVE_STRING_H. + * pexecute.c, xexit.c: Include stdlib.h if HAVE_STDLIB_H. + * objalloc.c: Include config.h. Include stdlib.h and don't + declare malloc or free if HAVE_STDLIB_H. + * strerror.c, strsignal.c: Include stdlib.h if HAVE_STDLIB_H, + else declare malloc without prototype. Include string.h if + HAVE_STRING_H, else declare memset without prototype. Don't + include stddef.h. + +2000-05-23 Mike Stump + + * Makefile.in (xmalloc.o): Add dependency for config.h, fixes make + -j3. + +2000-05-18 J. David Anglin + + * xmalloc.c: Include config.h for HAVE_SBRK definition. + +2000-05-16 Horst von Brand + + * hashtab.c (hash_pointer): Delete low-order bits which are + probably zero, also eliminate a warning on alpha. + +2000-05-15 David Edelsohn + + * Makefile.in: Change "pic" to depend on $(PICFLAG), not + on $(enable_shared). + +2000-05-10 Jakub Jelinek + + * config.table: Use mh-sparcpic for sparc*-*-*. + +2000-05-08 Nick Clifton + + * Makefile.in (CFILES): Add strncmp.c. + (NEEDED): Add strncmp. + +2000-05-04 Kaveh R. Ghazi + + * cplus-dem.c (cplus_demangle_opname, demangle_function_name): + Cast the arguments to `islower' to `unsigned char'. + (print_demangler_list): Prototype. + +Thu May 4 17:14:41 2000 Philippe De Muyter + + * sort.c (UCHAR_MAX): Provide fallback definition. + +2000-04-29 Alexandre Oliva + + * Makefile.in (maintainer-clean-subdir): Fix handling of empty + SUBDIRS. + +2000-04-28 Kenneth Block + Jason Merrill + + * cplus-dem.c (libiberty_demanglers): New table for demangle styles. + (cplus_demangle_set_style): New function for setting style. + (cplus_demangle_name_to_style): New function to translate name. + +2000-04-27 Kaveh R. Ghazi + + * aclocal.m4: New file with new test libiberty_AC_FUNC_STRNCMP. + + * configure.in (AC_CHECK_HEADERS): Add sys/mman.h fcntl.h. + (libiberty_AC_FUNC_STRNCMP): Invoke. + + * strncmp.c: New file. + +Thu Apr 27 16:58:43 MET DST 2000 Jan Hubicka + + * hashtab.c (htab_expand): Add prototype. + (find_empty_slot_for_expand): Likewise. + +2000-04-24 Kaveh R. Ghazi + + * hashtab.c (hash_pointer, eq_pointer): Make definition static to + match prototype. + (htab_expand): Cast the return value of xcalloc. + +2000-04-24 Mark Mitchell + + * hashtab.c (hash_pointer): New function. + (eq_pointer): Likewise. + (htab_hash_pointer): New variable. + (htab_eq_pointer): Likewise. + +2000-04-23 Mark Mitchell + + * sort.c (sort_pointers): Fix endianness bugs. + + * sort.c: New file. + * Makefile.in (CFILES): Add sort.c + (REQUIRED_OFILES): Add sort.o. + (sort.o): New target. + +2000-04-21 Michael Sokolov + + * Makefile.in (*-subdir): Revamp slightly to avoid losing on + 4.3BSD systems. + +Tue Apr 18 16:23:31 2000 Richard Kenner + + * hashtab.c: Various minor cleanups. + (htab_find_slot_with_hash): INSERT is now enum insert_option. + (htab_find_slot): Likewise. + +2000-04-16 Dave Pitts + + * cplus-dem.c (cplus_demangle_opname): Changed to use islower. + +2000-04-05 Richard Henderson + + * splay-tree.c (splay_tree_remove): New. + +2000-03-30 Mark Mitchell + + * hashtab.c (find_empty_slot_for_expand): Use hashval_t for hash + codes. + (htab_find_with_hash): Likewise. + (htab_find_slot_with_hash): Likewise. + +2000-03-29 Zack Weinberg + + * hashtab.c (htab_find_with_hash): Avoid calculating hash2 + unless it will be used. Rearrange loop for better + optimization. + (higher_prime_number): Add static prototype. + +Thu Mar 16 01:33:58 2000 Jeffrey A Law (law@cygnus.com) + + * Makefile.in (partition.o): Depend on config.h + +2000-03-14 Bernd Schmidt + + * hashtab.c (find_empty_slot_for_expand): New function. + (htab_expand): Use it instead of htab_find_slot. + (htab_find_with_hash): Renamed from htab_find; now accepts extra + argument HASH. + (htab_find_slot_with_hash): Likewise for htab_find_slot. + (htab_find): New wrapper function. + (htab_find_slot): Likewise. + (htab_traverse): Pass slot, not entry, to called function. + +2000-03-09 Alex Samuel + + * Makefile.in (CFILES): Add partition.c. + (REQUIRED_OFILES): Add partition.o. + (partition.o): New rule. + * partition.c: New file. + +2000-03-09 Zack Weinberg + + * hashtab.c (htab_create): Set del_f. + (htab_delete, htab_empty, htab_remove_elt, htab_clear_slot): + Use it. + +2000-03-08 Zack Weinberg + + * hashtab.c: Remove debugging variables (all_searches, + all_collisions, all_expansions). Delete + all_hash_table_collisions. + (create_hash_table, delete_hash_table, empty_hash_table, + find_hash_table_entry, remove_element_from_hash_table_entry, + clear_hash_table_slot, traverse_hash_table, hash_table_size, + hash_table_elements_number, hash_table_collisions): Rename to: + htab_create, htab_delete, htab_empty, htab_find_slot, + htab_remove_elt, htab_clear_slot, htab_traverse, htab_size, + htab_elements, htab_collisions. + (htab_find): New function, handles common case where you don't + plan to add or delete an entry. + (htab_expand): Don't create a whole new table, just a new + entry vector. + (htab_find_slot): Simplify logic. + +1999-08-03 Ian Lance Taylor + + * floatformat.c: Add casts to avoid signed/unsigned warnings. + * pexecute.c: Add ATTRIBUTE_UNUSED as needed on Unix. + + * Makefile.in (install_to_libdir): Change $(TARGETLIB).n to + $(TARGETLIB)n so it works on MSDOS. + (install_to_tooldir): Likewise. + +1999-07-21 Ian Lance Taylor + + From Mark Elbrecht: + * makefile.dos: Remove; obsolete. + * configure.bat: Remove; obsolete. + +1999-07-11 Ian Lance Taylor + + * splay-tree.c (splay_tree_insert): Add initialization to avoid + warning. + +2000-01-04 Mumit Khan + + * pexecute.c: Conditionally include string.h. + (fix_argv): Handle embedded whitespace in args for Mingw32. + +2000-01-04 Kaveh R. Ghazi + + * configure.in (ac_libiberty_warn_cflags): Turn on warnings if + we're using gcc. + + * Makefile.in (COMPILE.c): Add @ac_libiberty_warn_cflags@ + +1999-12-27 Geoff Keating + + * vasprintf.c (int_vasprintf): Don't re-read the format character + as this mishandles strings like '%%s'. + +1999-12-05 Mark Mitchell + + * splay-tree.c (splay_tree_new): Use struct splay_tree_node_s + rather than struct splay_tree_node. + (splay_tree_insert): Use struct splay_tree_s rather than struct + splay_tree. + +Sun Nov 28 00:59:39 1999 Philippe De Muyter + + * hashtab.c (sys/types.h): File included. + +1999-11-22 Jason Merrill + + * strtoul.c, strtol.c, random.c: Remove advertising clause from + BSD license, pursuant with + + ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change + +Wed Nov 10 09:42:39 1999 Jeffrey A Law (law@cygnus.com) + + * hashtab.c: Include stdio.h. + +Mon Nov 8 09:23:41 1999 Jeffrey A Law (law@cygnus.com) + + * hashtab.c (traverse_hash_table): Protect prototype with PARAMS. + +Tue Nov 2 03:23:13 1999 Philippe De Muyter + + * xstrdup (sys/types.h): Include this file. + +1999-10-28 Nathan Sidwell + + * Makefile.in (SUBDIRS): New macro. + (mostlyclean, clean, distclean, maintainer-clean): Adjust to + avoid multiple subdirectory cleaning. + (*-subdir): Use SUBDIRS. + +1999-10-25 Jim Kingdon + + * cplus-dem.c: Move declarations of standard_symbol_characters and + hp_symbol_characters inside #ifdef MAIN to avoid compiler + warnings. + +1999-10-23 08:51 -0700 Zack Weinberg + + * hashtab.c (find_hash_table_entry): When returning a + DELETED_ENTRY slot, change it to EMPTY_ENTRY first. + (clear_hash_table_slot): New function which deletes an entry + by its position in the table, not its value. + (traverse_hash_table): New function which calls a hook + function for every live entry in the table. + +1999-10-19 Mark Mitchell + + * cplus-dem.c (INTBUF_SIZE): New macro. + (string_append_template_idx): New function. + (demangle_expression): Likewise. + (demangle_integral_value): Use it. + (demangle_real_value): New function, split out from ... + (demangle_template_value_parm): ... here. Use + string_append_template_idx. Use demangle_real_value. + (demangle_template): Use string_append_template_idx. + (demangle_qualified): Use consume_count_with_underscores. + (get_count): Tweak formatting. + (do_type): Use string_append_template_idx. + +1999-10-18 Kaveh R. Ghazi + + * calloc.c: Add a public domain notice. + +Mon Oct 18 02:30:47 1999 Philippe De Muyter + + * setenv.c (sys/types.h, stdio.h): Include those files unconditionaly. + +Fri Oct 15 01:47:51 1999 Vladimir Makarov + + * Makefile.in (CFILES): Add hashtab.c + (REQUIRED_OFILES): Add hashtab.o + (hashtab.o): Add dependencies. + * hashtab.c: New file + +Wed Oct 13 01:16:47 1999 Mumit Khan + + * basename.c (DIR_SEPARATOR): New macro. + (DIR_SEPARATOR_2): Likewise. + (HAVE_DOS_BASED_FILESYSTEM): Likewise. + (IS_DIR_SEPARATOR): Likewise. + (main): Handle MSDOS style pathname. + +1999-10-11 Mark Mitchell + + * cplus-dem.c (do_type): Handle pointer to member types whose + enclosing classes have namespace scope. + +Sun Oct 10 01:23:50 1999 Marc Espie + + * config.table: Provide a backup shell for executing move-if-change. + +1999-10-02 Mark Mitchell + + * xmalloc.c (xmalloc): Fix spelling error. + (xcalloc, xrealloc): Likewise. + +1999-10-02 Kaveh R. Ghazi + + * cplus-dem.c (fancy_abort, demangle_integral_value, + demangle_arm_hp_template, recursively_demangle, + standard_symbol_characters, hp_symbol_characters, main): Add prototype. + (program_name, program_version, fatal): Constify a char*. + (usage, fatal): Mark with ATTRIBUTE_NORETURN. + (main): Call return, not exit. + +1999-09-25 Kaveh R. Ghazi + + * choose-temp.c: Remove obsolete comment about gcc. + (make_temp_file): Constify a char*. + +Wed Sep 8 20:03:28 1999 Kaveh R. Ghazi + + * xmemdup.c: Include sys/types.h. + +1999-09-07 Jeff Garzik + + * xmemdup.c: New xmemdup function. + * Makefile.in, makefile.vms, vmsbuild.com: Use xmemdup.[co]. + +Tue Sep 7 23:32:18 1999 Linas Vepstas + + * config.table: Add openedition target. + * config/mh-openedition: New file. + +Thu Sep 2 01:36:12 1999 Marc Espie + + * pexecute.c (pexecute): Fill in temp_base when needed. + +1999-08-31 Richard Henderson + + * getpwd.c: Check HAVE_GETCWD before defining it away. + +1999-08-30 Kaveh R. Ghazi + + * Makefile.in (CFILES): Add calloc.c and getpwd.c. + (REQUIRED_OFILES): Add getpwd.o. + (getpwd.o): Add target. + + * configure.in (AC_PREREQ): Bump to 2.13. + (AC_CHECK_HEADERS): Add check for . + + * getpwd.c: New file, moved here from gcc. + +1999-08-25 Kaveh R. Ghazi + + * cplus-dem.c (gnu_special): Cast a `size_t' to `long' when + comparing against a signed quantity. + (arm_special): Likewise. + (demangle_fund_type): Likewise. + (do_hpacc_template_const_value): Mark parameter `work' with + ATTRIBUTE_UNUSED. + (main): Constify variable `valid_symbols'. + +Tue Aug 24 02:50:45 1999 Philippe De Muyter + + * strtoul.c (strtoul): Add parentheses around && within ||. + +Fri Aug 6 23:32:29 1999 Daniel Jacobowitz + + * Makefile.in (FLAGS_TO_PASS): Include prefix, exec_prefix, + libdir, libsubdir and tooldir. + +1999-08-01 Mark Mitchell + + * splay-tree.c (splay_tree_insert): Return the new node. + +1999-07-14 Richard Henderson + + * argv.c: Include stdlib.h and string.h instead of + prototyping directly. + * choose-temp.c: Conditionally include string.h. + +1999-07-12 Jason Merrill + + * Makefile.in (NEEDED): Add bcmp, bcopy, bzero. + +1999-07-11 Ian Lance Taylor + + * splay-tree.c (splay_tree_insert): Add initialization to avoid + warning. + +1999-07-07 Jason Merrill + + * Makefile.in (needed-list): Only include stuff we actually need + for libstdc++. + +1999-06-21 Andreas Schwab + + * configure.in (checkfuncs): Add gettimeofday. + * config.in, configure: Regenerated. + +Mon Jun 21 05:56:01 1999 Mumit Khan + + * configure.in (*-*-uwin*): UWIN has sys_{errlist,nerr} even if + the test fails. + * configure: Regenerate. + +1999-06-10 Mike Stump + + * Makefile.in (setenv.o): Add config.h dep for setenv.o to fix + parallel builds. + +1999-05-28 Kaveh R. Ghazi + + * putenv.c: Include ansidecl.h to define `const'. + * setenv.c: Likewise. + +Wed May 26 03:58:20 1999 "Melissa O'Neill" + + * Makefile.in (CFILES): Add putenv.c and setenv.c. + * configure.in (funcs): Add putenv and setenv. + (AC_CHECK_FUNCS): Check for putenv and setenv. + * configure: Rebuilt. + * putenv.c setenv.c: New files. + + * getcwd.c (getcwd): If pathname is NULL, then obtain SIZE + bytes of space using malloc. + +Mon May 17 01:42:34 1999 Stu Grossman + + * cplus-dem.c (demangle_fund_type (near 'I' case)): Don't advance + the *mangled pointer beyond the end of the string. Clean up code to + match prevailing coding style. + +1999-05-13 Michael Hayes + + * tmpnam.c (L_tmpnam): Fix typo. + +Thu May 13 01:14:46 1999 Marc Espie + + * cplus-dem.c (standard_symbol_characters): Renamed from + standard_symbol_alphabet. No longer modify TABLE. + (hp_symbol_characters): Renamed from hp_symbol_alphabet. No longer + modify TABLE. + (main): Corresponding changes. Use strchr to determine if a + character is valid. + +1999-05-11 Jim Blandy + + * cplus-dem.c (main): Use table lookup to distinguish identifier + characters from non-identifier characters. + (standard_symbol_alphabet, hp_symbol_alphabet): New functions. + +Thu May 6 20:34:42 1999 Fred Fish + + * configure.in (sys/resource.h): Add to AC_CHECK_HEADERS list. + * getruntime.c: Only attempt to include sys/resource.h and + use getrusage if both HAVE_GETRUSAGE and HAVE_SYS_RESOURCE_H + are defined. + +Mon Apr 26 01:36:06 1999 Donn Terry (donn@interix.com) + + * configure.in (alloca detection): Handle alloca directly for interix. + * configure: Rebuilt. + +Sun Apr 25 01:18:21 1999 Mumit Khan + + * choose-temp.c (DIR_SEPARATOR): Use '\\' only for native windows32. + +1999-04-20 Jim Blandy + + Fix from Dale Hawkins: + * cplus-dem.c (mop_up): Set typevec_size to zero, so it'll be + reallocated properly if we use it again. + + * cplus-dem.c (demangle_fund_type): Check for buffer overrun. Be + stricter about syntax. Always null-terminate string. + +Thu Apr 15 23:00:55 1999 Mumit Khan + + * configure.in (checkfuncs): Check for sbrk. + * config.in: Rebuilt. + * configure: Likewise. + * xmalloc.c: Use HAVE_SBRK instead of the host specific definitions. + +1999-04-12 Jim Blandy + + Fix from Marcus Daniels: + * cplus-dem.c (demangle_fund_type): Don't run off the end of the + identifier looking for another underscore. + +Sun Apr 11 23:20:59 1999 Mumit Khan + + * pexecute.c: Change all references to __UWIN__ to _UWIN. + * xmalloc.c: Likewise. + (xcalloc): UWIN has sbrk. + (xrealloc): Fix guard macro. + +1999-04-11 Richard Henderson + + * alloca-conf.h (alloca) [C_ALLOCA]: Don't use Gcc builtin + or . + * clock.c (GNU_HZ): New definition. + (clock): Use it. + * getruntime.c: Likewise. + + * config.table: Use mh-beos. + * config/mh-beos: New file. + +1999-04-11 Mark Mitchell + + * cplus-dem.c (demangle_template_value_parm): Handle + pointers-to-members. + (do_type): Handle template parameters as qualifiers. + +1999-04-01 Jim Blandy + + * cplus-dem.c: Attempt to handle overflows in counts with some + semblance of grace. + (consume_count): Detect overflows. Return -1 to indicate errors, + instead of zero. + (demangle_template_value_parm, demangle_template): Handle change + to consume_count's return convention. + +1999-04-05 Tom Tromey + + * testsuite/regress-demangle: New file. + * testsuite/demangle-expected: New file. + + * Makefile.in (all, check, installcheck, info, install-info, + clean-info, dvi, install, etags, tags, mostlyclean, clean, + distclean, maintainer-clean, realclean): Depend on corresponding + `-subdir' target. + (all-subdir check-subdir installcheck-subdir info-subdir + install-info-subdir clean-info-subdir dvi-subdir + install-info-subdir etags-subdir mostlyclean-subdir clean-subdir + distclean-subdir maintainer-clean-subdir): New target. + * testsuite/Makefile.in: New file. + * configure: Rebuilt. + * configure.in: Create testsuite/Makefile. + +1999-04-02 Mark Mitchell + + * splay-tree.h (splay_tree_compare_pointers): Define. + +1999-03-30 Mark Mitchell + + * splay-tree.c (splay_tree_compare_ints): Define. + +1999-03-30 Tom Tromey + + * cplus-dem.c (consume_count): If `count' wraps, return 0 and + don't advance input pointer. + (demangle_class_name): If consume_count didn't find a count, do + nothing. Don't bother with `strlen' sanity check; consume_count + does it for us. + +1999-03-16 Stan Shebs + + From Art Haas : + * cplus-dem.c (demangle_prefix): Don't grab all the '__' strings + when doing arm or hp style. + (demangle_nested_args): Decr forgetting_types field when done. + +Thu Mar 11 01:22:58 1999 Mumit Khan + + * pexecute.c (__CYGWIN32__): Rename to + (__CYGWIN__): this. + * xmalloc.c: Likewise. + + Changes to support i386-pc-uwin. + * configure.in (*-*-uwin*): Workaround for vfork bug. + * configure: Regenerate. + * pexecute.c (pexecute): Be like standard Unix. + (pwait): Likewise. + * xmalloc.c (first_break): Define. + (xmalloc_set_program_name): Use. + (xmalloc): Use. + +Thu Mar 11 01:07:55 1999 Franz Sirl + + * config.table: Cleanup and add mh-*pic handling for alpha, arm, powerpc + +Sun Feb 28 22:30:44 1999 Geoffrey Noer + + * config.table: Check cygwin*, not cygwin32*. + +Tue Feb 9 16:39:01 1999 Dave Brolley + + * Makefile.in: Change mkstemp -> mkstemps. + +Tue Feb 9 01:12:27 1999 Marc Espie + + * Makefile.in (REQUIRED_OFILES): remove mkstemp.o + * configure.in (funcs): Check for and conditionally add mkstemps to + the list of functions libiberty will provide. + * configure: Rebuilt. + +Wed Feb 3 00:01:15 1999 Mumit Khan + + * clock.c (HZ): Define in terms of (ISO C) CLOCKS_PER_SEC on + platforms that don't have HZ. + * getruntime.c (HZ): Likewise. + +Sat Jan 30 13:28:04 1999 Richard Henderson + + * Makefile.in (xstrdup.o): Depend on config.h. + +Wed Jan 13 07:26:44 1999 H.J. Lu (hjl@gnu.org) + + * cplus-dem.c (mop_up): Set work->previous_argument to NULL after + freeing it. + +Wed Jan 13 14:16:36 1999 Kaveh R. Ghazi + + * xstrdup.c (xstrdup): Switch from strcpy to memcpy for speed. + +Tue Jan 5 15:58:29 1999 Elena Zannoni + + * Makefile.in (CFILES): fix typo, splay-tree.c instead of + splay-tree.o. + +1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) + + * configure.in: Require autoconf 2.12.1 or higher. + +1998-12-30 Michael Meissner + + * random.c (NULL): Don't redefine NULL if it is already defined. + +Tue Dec 22 09:43:35 1998 Kaveh R. Ghazi + + * argv.c (buildargv): Cast the result of alloca in assignment. + + * choose-temp.c: Include stdlib.h. + + * cplus-dem.c (demangle_arm_pt): Remove unused prototype. + (snarf_numeric_literal): Constify first parameter. + (code_for_qualifier): Avoid a gcc extension, make the parameter an + int, not a char. + (demangle_qualifier): Likewise. + (demangle_signature): Cast the argument of a ctype function to + unsigned char. + (arm_pt): Add parens around assignment used as truth value. + (demangle_arm_hp_template): Constify variable `args'. + (do_hpacc_template_const_value): Cast the argument of a ctype + function to unsigned char. + (do_hpacc_template_literal): Remove unused variable `i'. + (snarf_numeric_literal): Constify parameter `args'. + Cast the argument of a ctype function to unsigned char. + + * floatformat.c (floatformat_to_double): Add explicit braces to + avoid ambiguous `else'. + + * fnmatch.c (fnmatch): Change type of variables `c', `c1', + `cstart' and `cend' to unsigned char. Cast the argument of macro + `FOLD', which uses ctype functions, to unsigned char. + + * objalloc.c (free): Add prototype. + +Sun Dec 20 16:03:46 1998 Hans-Peter Nilsson + + * Makefile.in (CFILES): Fix typo: splay-tree.c, not splay-tree.o + +Fri Dec 18 17:50:18 1998 David Taylor + + * cplus-dem.c (demangle_arm_pt): remove declaration -- function + doesn't exist. + (do_hpacc_template_literal): remove unused variable `i'. + +Fri Dec 18 16:11:43 EST 1998 Andrew MacLeod + + * cplus-dem.c (demangle_fund_type): Process CV and u codes before + bumping the pointer we read from. Also prepend these codes, + as we do in other places. + +1998-12-18 Nick Clifton + + * cplus-dem.c (demangle_arm_hp_template): Make variable 'args' be + 'const char *' in order to match its usage when calling siblings. + (snarf_numeric_literal): Make first arg 'const char **' in order + to match usage. + +Mon Dec 14 09:55:50 1998 Kaveh R. Ghazi + + * choose-temp.c: Don't check IN_GCC anymore. + + * floatformat.c (floatformat_from_double): Use `const', not `CONST'. + * memchr.c (memchr): Likewise. + * memcpy.c (memcpy): Likewise. + * memmove.c (memmove): Likewise. + + * mkstemp.c: Don't check IN_GCC anymore. + * pexecute.c: Likewise. + * splay-tree.c: Likewise. + + * strchr.c (strchr): Use `const', not `CONST'. + * strrchr.c (strrchr): Likewise. + * strtol.c (strtol): Likewise. + * strtoul.c (strtoul): Likewise. + +Fri Dec 4 13:51:04 1998 David Taylor + Elena Zannoni + Stan Shebs + Edith Epstein + Andres MacLeod + Satish Pai + + * HP aCC demangling support. + * cplus-dem.c + (main): Remove default to HP style demangling, set to EDG + demangling correctly when -edg specified; set the demangling style + when user specifies 'edg'. Set strip_underscore to + prepends_underscore, if not HPUXHPPA. Set + current_demangling_style to hp_demangling if HPUXHPPA. Set + current demangling style correctly if the switch is hp. Read + label correctly also in the HP style case. + (work_stuff): add temp_start field; add field for volatile member + function. + (arm_pt): handle ARM_DEMANGLING and EDG_DEMANGLING styles; HP + style for this case is the same as ARM. + (demangle_args): handle EDG_DEMANGLING style; support HP style. + (demangle_arm_hp_template): new function. (It was + demangle_arm_pt.); check and set value of temp_start field in + multiple places. Also, when ceching for end of template args, + check to see if at end of static member of template class. + (demangle_class): new local variable : save_class_name_end Don't + include template args in string defining class. + (demangle_class_name): use demangel_arm_hp_template. + (demangle_function_name): handle case where demangling style is + HP_DEMANGLING and currently point at an 'X' in the mangled name. + Handle EDG_DEMANGLING style. Handle constructor and destructor + ops for HP style. + (demangle_prefix): handle EDG_DEMANGLING and ARM_DEMANGLING + styles. global destructor and constructor for HP style are same + as for ARM style. Same for local variables. + (demangle_qualified): handle EDG_DEMANGLING style. + (demangle_signature): add case for volatile member function. For + cases '1' - '9' : initialize the temp_start field to -1 and handle + the EDG_DEMANGLING style. for case 'F' : handle EDG_DEMANGLING + and AUTO_DEMANGLING styles. If expecting a function and managed + to demangle the funct args, then handle the LUCID_DEMANGLING, + ARM_DEMANGLING, and EDG_DEMANGLING styles. Add case for local + class name after "Lnnn_ in HP style case. HP style too needs to + forget types. _nnn is OK for HP style, so don't report failure. + (do_hpacc_template_const_value): new function. Handle template's + value param for HP/aCC. + (do_hpacc_template_literal): new function. Handle a template's + literal parameter for HP aCC. + (recursively_demangle): new function + (snarf_numeric_literal): new function. + (usage): add 'edg' to the list of demangling styles; add hp switch + to message. + +Sat Nov 28 17:25:22 1998 Christopher Faylor + + * pexecute.c: Remove obsolete ifdefed cygwin code. + +Fri Nov 27 13:26:06 1998 Kaveh R. Ghazi + + * choose-temp.c: Always include libiberty.h. Avoid redundancies. + * cplus-dem.c: Likewise. Conform to libiberty.h. + * pexecute.c: Likewise. + * splay-tree.c: Likewise. + +1998-11-25 Mike Stump + + * Makefile.in (splay-tree.o): Add config.h dependency. + +Mon Nov 23 16:59:49 1998 Kaveh R. Ghazi + + * configure.in: Use AC_PREREQ(2.12.1). + +1998-11-16 Benjamin Kosnik + + * cplus-dem.c (demangle_fund_type): Add demangling for C9x types. + +Thu Nov 19 22:15:50 1998 Jeffrey A Law (law@cygnus.com) + + * mpw.c (mpw_access): Add missing parens. + +Thu Nov 19 12:59:21 1998 Kaveh R. Ghazi + + * configure.in: Call AC_HEADER_SYS_WAIT. + + * pexecute.c: Include sys/wait.h when !IN_GCC. + +Thu Nov 19 14:38:20 1998 Geoffrey Noer + + * pexecute.c: revert back to checking old Cygwin + preprocessor symbol until some time has passed. + +Wed Nov 18 08:52:26 1998 Christopher Faylor + + * pexecute.c: Reorganize WIN32 case to accomodate Cygwin + since it will now support similar constructs. + +Fri Nov 13 19:18:05 1998 Kaveh R. Ghazi + + * configure.in: Check for calloc. + + * calloc.c: New file. + + * xmalloc.c (xcalloc): New function. + +Fri Nov 13 08:51:46 EST 1998 Andrew MacLeod + + *cplus-dem.c (demangle_prefix): Use the last "__" + in the mangled name when looking for the signature. This allows + template names to begin with "__". + +1998-11-08 Mark Mitchell + + * cplus-dem.c (type_kind_t): Add tk_reference. + (demangle_template_value_parm): Handle it. + (do_type): Use it for references, instead of tk_pointer. + + * cplus-dem.c (demangle_template_value_parm): Use cplus_demangle, + not internal_cplus_demangle. + +Sat Nov 7 16:02:10 1998 Kaveh R. Ghazi + + * choose-temp.c: Don't include gansidecl.h. + * mkstemp.c: Likewise. + * pexecute.c: Likewise. + +Mon Nov 2 15:05:33 1998 Geoffrey Noer + + * configure.in: detect cygwin* instead of cygwin32* + * configure: regenerate + +Mon Nov 2 10:22:01 1998 Kaveh R. Ghazi + + * pexecute.c: Check HAVE_CONFIG_H, not IN_GCC, when determining + whether to include config.h. Possibly include unistd.h in the + !IN_GCC case. Define VFORK_STRING as a printable function call + for error messages (either "vfork" or "fork".) If HAVE_VFORK_H is + defined, include vfork.h. If VMS is defined, define vfork() + appropriately. Remove vfork check on USG, we're using autoconf. + (pexecute): Set `errmsg_fmt' to VFORK_STRING instead of checking + locally what string to use. + +1998-10-26 Mark Mitchell + + * splay-tree.c: Tweak include directives to make sure declarations of + xmalloc and free are available. + +1998-10-25 Mark Mitchell + + * cplus-dem.c (gnu_special): Fix handling of virtual tables in + anonymous namespaces. + +1998-10-23 Mark Mitchell + + * cplus-dem.c (work_stuff): Replace const_type and volatile_type + with type_quals. + (TYPE_UNQUALIFIED): New macro. + (TYPE_QUAL_CONST): Likewise. + (TYPE_QUAL_VOLATILE): Likewise. + (TYPE_QUAL_RESTRICT): Likewise. + (code_for_qualifier): New function. + (qualifier_string): Likewise. + (demangle_qualifier): Likewise. + (internal_cplus_demangle): Use them. + (demangle_signature): Likewise. + (demangle_template_value_parm): Likewise. + (do_type): Likewise. + (demangle_fund_type)): Likewise. + +Thu Oct 22 19:58:43 1998 Kaveh R. Ghazi + + * splay-tree.c (splay_tree_foreach_helper): Make definition static + to match prototype. + +1998-10-21 Mark Mitchell + + * splay-tree.c: New file. + * Makefile.in (CFILES): Add it. + (REQUIRED_OFILES): Likewise. + (splay-tree.o): Add dependencies. + +Tue Oct 20 12:29:02 1998 Andreas Schwab + + * cplus-dem.c (demangle_qualified): Fix off-by-one when checking + range of 'K' index. + +Thu Oct 15 18:51:12 1998 Kaveh R. Ghazi + + * choose-temp.c: Prototype mkstemps() when IN_GCC. + + * cplus-dem.c (consume_count): Cast argument of ctype macro to + `unsigned char'. + (cplus_demangle_opname): Cast the result of `strlen' to (int) when + comparing against one. + (cplus_mangle_opname): Likewise. + (demangle_integral_value): Cast argument of ctype macro to + `unsigned char'. + (demangle_template_value_parm): Likewise. + (demangle_template): Initialize variable `bindex'. Cast the + result of `strlen' to (int) when comparing against one. Remove + unused variable `start_of_value_parm'. + (demangle_class_name): Cast the result of `strlen' to (int) when + comparing against one. + (demangle_prefix): Cast argument of ctype macro to `unsigned char'. + (gnu_special): Likewise. Cast the result of `strlen' to (int) + when comparing against one. + (demangle_qualified): Cast argument of ctype macro to `unsigned char'. + (get_count): Likewise. + (do_type): Likewise. Cast the result of `strlen' to (int) when + comparing against one. + (demangle_fund_type): Cast argument of ctype macro to `unsigned char'. + (demangle_function_name): Cast the result of `strlen' to (int) + when comparing against one. + + * mkstemp.c (mkstemps): Cast variable `len' to (int) when + comparing against one. + +Tue Oct 13 23:51:51 1998 Jeffrey A Law (law@cygnus.com) + + * mkstemp.c: Check HAVE_SYS_TIME_H before including sys/time.h + * configure.in (AC_CHECK_HEADERS): Check for sys/time.h too. + * config.in, configure: Rebuilt. + + * getopt.c: Check HAVE_STRINGS_H before including strings.h. + * configure.in (AC_CHECK_HEADERS): Check for strings.h too. + * config.in, configure: Rebuilt. + +Mon Oct 12 19:15:59 1998 Geoffrey Noer + + * configure.in: in comment, call AC_EXEEXT instead of AM_EXEEXT + +Sun Oct 11 17:36:06 1998 Michael Tiemann + + * Makefile.in (cplus-dem.o, obstack.o): Depend upon config.h. + +Thu Oct 8 23:42:08 1998 Jeffrey A Law (law@cygnus.com) + + * Merge egcs & devo libiberty. + +1998-09-08 Martin von Löwis + + * cplus-dem.c (demangle_arm_pt): Demangle anonymous namespaces. + +Mon Sep 7 23:29:01 1998 Kaveh R. Ghazi + + * mkstemp.c: Include config.h even when not IN_GCC. Wrap header + inclusions inside HAVE_*_H macros. Include ansidecl.h when not + IN_GCC. + + * vasprintf.c: Include stdarg.h/varargs.h first. + + * vprintf.c: Likewise. + +Sat Sep 5 03:24:49 1998 Jeffrey A Law (law@cygnus.com) + + * pexecute.c: Updates from gcc. Copy in gcc has been removed. This + is the canonical copy. Define ISSPACE if !IN_GCC. + * alloca.c, vfprintf.c, choose-temp.c, mkstemp.c, getopt.c: Similarly. + * getopt1.c, obstack.c: Similarly. + * Makefile.in: Build mkstemp.o + +Tue Sep 1 23:12:47 1998 Christopher Faylor + + * configure.in: Include asprintf in list of functions known not + to be in newlib. + * configure: Rebuild. + +Wed Aug 19 14:05:01 1998 Mumit Khan + + * cplus-dem.c (work_stuff): Add dllimported. + (demangled_prefix): Mark symbols imported from PE DLL. + (internal_cplus_demangled): Handle. + +1998-08-17 Jason Merrill + + * cplus-dem.c (do_type): Fix simple array handling. If we fail, + stay failed. + +Mon Aug 17 10:40:34 1998 Kaveh R. Ghazi + + * cplus-dem.c: Include config.h if it exists. Also, only + prototype malloc/realloc if we can't get stdlib.h. + +Sat Aug 15 16:15:01 1998 Ian Lance Taylor + + * configure.in: Switch back to checking --with-target-subdir when + deciding whether to check for newlib, undoing part of July 15 + change. + * configure: Rebuild. + +Thu Aug 13 16:47:38 1998 Mark Mitchell + + * cplus-dem.c (type_kind_t): New type. + (demangle_template_value_parm): Add type_kind_t parameter. Rely + on this paramter, rather than demangling the type again. + (demangle_integral_value): Pass tk_integral. + (demangle_template_: Pass the value returned from do_type. + (do_type): Return a type_kind_t. Pass tk_integral to + demangle_template_value_parm for array bounds. + (demangle_fund_type): Likewise. + + Also incorporate from GCC version: + + Tue Jul 21 13:28:19 1998 Jason Merrill + + * cplus-dem.c (do_type): Use demangle_template_value_parm for arrays. + +Thu Aug 13 16:47:38 1998 Kaveh R. Ghazi + + * cplus-dem.c (demangle_nested_args): Make function definition + static to match the prototype. + +Tue Jul 28 11:33:09 1998 Mark Mitchell + + * cplus-dem.c (type_kind_t): New type. + (demangle_template_value_parm): Add type_kind_t parameter. Rely + on this paramter, rather than demangling the type again. + (demangle_integral_value): Pass tk_integral. + (demangle_template_: Pass the value returned from do_type. + (do_type): Return a type_kind_t. Pass tk_integral to + demangle_template_value_parm for array bounds. + (demangle_fund_type): Likewise. + + Also incorporate from GCC version: + + Tue Jul 21 13:28:19 1998 Jason Merrill + + * cplus-dem.c (do_type): Use demangle_template_value_parm for arrays. + +Mon Jul 27 12:16:08 1998 Ian Lance Taylor + + * Makefile.in (ALLOCA): New variable. + ($(TARGETLIB)): Add $(ALLOCA) to library. + (needed-list): Add $(ALLOCA). + ($(ALLOCA)): Depend upon stamp-picdir. + +Sun Jul 19 08:23:17 1998 Kaveh R. Ghazi + + * cplus-dem.c (demangle_nested_args): Make function definition + static to match the prototype. + +Wed Jul 15 00:12:58 1998 Ian Lance Taylor + + * configure.in: Check --with-cross-host rather than + --with-target-subdir when deciding whether build uses a cross + compiler, and when deciding where to install the library. + * configure: Rebuild. + +Sun Jul 12 01:27:05 1998 Jason Merrill + + * cplus-dem.c (demangle_nested_args): Return a value. + +Sat Jul 11 16:19:48 1998 Mark Mitchell + + * cplus-dem.c (string): Move definition before work_stuff. + (work_stuff): Add volatile_type, forgetting_types, + previous_argument, and nrepeats fields. + (SCOPE_STRING): New macro. + (demangle_template): Add `remember' parameter. Add comment. + Register the `B' code type here, if remembering. Tidy. Fix crash + on NULL tmpl_argvec. Be consistent with use of tname/trawname. + (demangle_nested_args): New function. + (internal_cplus_demangle): Handle volatile-qualified member + functions. + (mop_up): Delete the previous_argument string if present. + (demangle_signature): Tidy. Handle volatile-qualified member + functions. Handle back-references using the `B' code. Use extra + parameter to demangle_template and SCOPE_STRING where appropriate. + (demangle_template_value_parm): Fix thinko; 'B' is not an integral + code. + (demangle_class): Use SCOPE_STRING. + (gnu_special): Pass additional argument to demangle_template. + Use SCOPE_STRING. + (demangle_qualified): Save qualified types for later + back-references. Handle constructors and destructors for template + types correctly. + (do_type): Tidy. Use SCOPE_STRING. Pass extra argument to + demangle_template. Use demangled_nested_args. Don't remember + qualified types here; that's now done in demangle_qualified. + Similarly for templates. + (do_arg): Improve commment. Handle 'n' repeat code. + (remember_type): Check forgetting_types. + (demangle_args): Deal with 'n' repeat codes. Tidy. + +Thu Jul 2 16:26:24 1998 Ian Lance Taylor + + * config.table: Only use mh-fbsd21 on *-*-freebsd2.2.[012], not on + *-*-freebsd2.2.*. From Dmitrij Tejblum . + +Mon Jun 15 16:29:01 1998 Ian Lance Taylor + + * configure.in (setobjs): Correct quoting error in cygwin32 case. + From Chris Faylor . + +Mon Jun 1 13:47:55 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.c: Update to latest FSF version. + +Mon Jun 1 14:17:36 1998 Mike Stump + + * Makefile.in: Add a dependency on stamp-picdir for the + objects, so that we can do a parallel build. + +Sat May 30 22:17:13 1998 Mumit Khan + + * configure.in (checkfuncs): Add missing "'". + +Fri May 29 12:40:41 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.c (_obstack_memory_used): Elide this function if we're + on a system with GNU libc. + +Tue May 26 18:28:43 1998 Ian Lance Taylor + + * Makefile.in (distclean): Remove config.log. + +Tue May 26 15:01:52 1998 Andreas Schwab + + * Makefile.in (distclean): Don't remove alloca-conf.h. + +Fri May 22 01:38:07 1998 Hans-Peter Nilsson + + * cplus-dem.c (MBUF_SIZE): Bumped from 512 to 32767. + +1998-05-21 Mark Mitchell + + * cplus-dem.c (do_type): Handle volatile qualification. + +1998-05-21 Manfred Hollstein + + * configure.in: Check for unistd.h as well. + * configure: Rebuild. + * config.in: Rebuild. + * getpagesize.c (GNU_OUR_PAGESIZE): Use sysconf only if _SC_PAGESIZE + is defined in unistd.h. Reformat conditional block for easier reading. + + * config.table (shared): Default to no if ${enable_shared} + is unset or empty; this logic is used by the toplevel + configure scripts, too. + +Sat May 16 14:01:26 1998 Jeffrey A Law (law@cygnus.com) + + * config.table: Add line to set enable_shared in the Makefile + as needed. + +Wed May 13 14:24:38 1998 Kaveh R. Ghazi + + * cplus-dem.c (squangle_mop_up): Change return type to void. + (internal_cplus_demangle): Remove unused parameter `options'. + All callers changed. + (cplus_demangle_opname): Remove function wide variable `int i' and + replace with `size_t i' at each location where it is used. + (cplus_mangle_opname): change type of `i' from int to size_t. + +Wed May 13 13:39:38 1998 Ian Lance Taylor + + * alloca-conf.h: Include config.h. Check HAVE_ALLOCA_H rather + than sparc or sun. + * Makefile.in (argv.o): Depend upon config.h and alloca-conf.h. + +Fri May 8 00:23:51 1998 Ian Lance Taylor + + * configure.in: Set libiberty_topdir correctly when srcdir is + "." and with_target_subdir is not set. + * configure: Rebuild. + +Thu May 7 13:01:44 1998 Ian Lance Taylor + + * configure.in: Add *-*-mingw32* case. + * configure: Rebuild. + +Wed May 6 11:33:51 1998 Ian Lance Taylor + + * config.table: Never use a PIC file for *-*-cygwin32*. + + * Makefile.in (config.status): Depend upon config.table. + + * configure.in: On a cygwin32 host, always compile random, and + don't test for sys_siglist, strsignal, or psignal. + * configure: Rebuild. + + * clock.c: Check HAVE_SYS_PARAM_H rather than NO_SYS_PARAM_H. + * getcwd.c: Likewise. + * getpagesize.c: Likewise. + * getruntime.c: Likewise. + +Tue May 5 18:08:32 1998 Ian Lance Taylor + + Use autoconf tests rather than the old dummy.c test: + * configure.in: Add AC_ARG_WITH calls for --with-target-subdir and + --with-newlib. Add AC_CONFIG_HEADER. Use AC_REPLACE_FUNCS for + most functions. Add special cases to handle newlib and VxWorks. + Remove target_makefile_frag. Create stamp-h in AC_OUTPUT if + CONFIG_HEADERS is set. Only call config-ml.in in AC_OUTPUT if + CONFIG_FILES is set; set ac_file before calling it. + * config.table (arm-*-riscix*, *-*-cygwin32): Remove. + (*-*-hpux*, *-*-hiux*, *-*-irix4*, *-*-solaris2*): Remove. + (*-*-sysv4*, *-*-go32, *-*-vxworks5*, *-*-vxworks): Remove + (i[3456]-*-mingw32*): Remove. + * Makefile.in (ERRORS_CC, CONFIG_H, NEEDED_LIST): Remove. + (LIBOBJS): New variable. + (HOST_OFILES, DO_ALSO, STAGESTUFF): Remove. + (all): Depend upon needed-list. Don't check RULE1. + (@target_makefile_frag@): Remove. + (COMPILE.c): Include @DEFS@. + (HFILES): Add alloca-conf.h. + (REQUIRED_OFILES): Remove basename.o. + ($(TARGETLIB)): New target. + (stamp-needed, lneeded-list, needed.awk, stamp-config): Remove. + (lconfig.h, needed2.awk, dummy.o, errors): Remove. + (needed-list, config.h): Rewrite. + (RULE1, $(RULE1), RULE2, $(RULE2)): Remove. + (.always.): Remove. + (Makefile): Set CONFIG_FILES and CONFIG_HEADERS. + (stamp-h): New target. + (atexit.o, clock.o, getcwd.o, getpagesize.o): New targets. + (basename.o): Don't depend upon config.h. + (getruntime.o): Depend upon config.h. + * atexit.c: Include config.h. Check HAVE_ON_EXIT rather than + NEED_on_exit. + * basename.c: Don't include config.h. Don't check NEED_basename. + * clock.c: Include config.h. + * getcwd.c: Likewise. + * getpagesize.c: Likewise. + * getruntime.c: Likewise. Fix checks which set HAVE_GETRUSAGE and + HAVE_TIMES. + * strerror.c: Change uses of NEED_sys_errlist to + HAVE_SYS_ERRLIST. Likewise for NEED_strerror and HAVE_STRERROR. + * strsignal.c: Likewise for NEED_sys_siglist and HAVE_SYS_SIGLIST, + and for NEED_strsignal and HAVE_STRSIGNAL and for NEED_psignal and + HAVE_PSIGNAL. + * acconfig.h: New file. + * dummy.c: Remove. + * functions.def: Remove. + * config/mh-cxux7 (HDEFINES): Remove -DHAVE_SYSCONF. + * config/mh-windows (HDEFINES): Remove. + * config/mh-cygwin32: Remove. + * config/mh-go32: Remove. + * config/mh-irix4: Remove. + * config/mh-riscix: Remove. + * config/mh-sysv4: Remove. + * config/mt-mingw32: Remove. + * config/mt-vxworks5: Remove. + * config.in: New file, generated using autoheader. + * configure: Rebuild. + +Mon May 4 13:00:28 1998 Ian Lance Taylor + + * configure.in: Rewrite to use autoconf. + * configure: Generate using autoconf. + * config/mh-a68bsd: Remove. + * config/mh-apollo68: Remove. + * config/mh-hpbsd: Remove. + * config/mh-ncr3000: Remove. + * config/mh-sysv: Remove. + * config/mh-aix (RANLIB, INSTALL): Don't define. + * config/mh-cxux7 (RANLIB, INSTALL): Don't define. + * config/mh-irix4 (CC, RANLIB, INSTALL): Don't define. + * config/mh-sysv4 (RANLIB, INSTALL): Don't define. + * config.table: Change config_shell to CONFIG_SHELL, and use + libiberty_topdir to find move-if-change. + (m68k-apollo-bsd*, m68k-apollo-sysv*): Remove. + (i[3456]86-ncr-sysv4*, *-*-dgux*, hppa*-hp-bsd*): Remove. + (*-*-irix*, *-*-m88kbcs*, *-*-sysv*): Remove. + * Makefile.in (srcdir): Set to @srcdir@. + (VPATH): Likewise. + (prefix, exec_prefix, bindir, libdir): Set to autoconf variables. + (SHELL, INSTALL, INSTALL_PROGRAM, INSTALL_DATA): Likewise. + (CC, CFLAGS, RANLIB)): Likewise. + (datadir, man*dir, infodir, includedir, MAKEINFO): Remove. + (target_makefile_frag, host_makefile_frag): Add substitutions. + (INSTALL_DEST): Set to @INSTALL_DEST@. + (Makefile): Depend upon config.status. Don't depend upon + $(host_makefile_frag) or $(target_makefile_frag). + (config.status): New target. + +Sun May 3 17:58:49 1998 Ian Lance Taylor + + * config/mt-sunos4: Remove. Should be handled by --with-headers + and --with-libraries options at top level. + * config.table: Never use mt-sunos4. + + * alloca-conf.h: New file, combining alloca-norm.h and + alloca-botch.h. + * alloca-norm.h: Remove. + * alloca-botch.h: Remove. + * configure.in: Set shell variables files and links to empty. + * config.table: Don't set shell variable files. + * configure.bat: Don't create alloca-conf.h. + * makefile.vms: Likewise. + * mpw-config.in: Likewise. + * vmsbuild.com: Likewise. + +Fri May 1 11:41:42 1998 Ian Lance Taylor + + * Makefile.in ($(HOST_OFILES) $(REQUIRED_OFILES)): Remove old + target depending upon config.h. + (alloca.o): Add target depending upon config.h + (basename.o, choose-temp.o, fnmatch.o): Likewise. + (getopt.o, getopt1.o, pexecute.o, strerror.o): Likewise. + (strsignal.o, xstrerror.o): Likewise. + +Fri May 1 04:26:25 1998 Peter Schauer + + * cplus-dem.c (cplus_demangle_opname): Initialize work. + +Mon Apr 27 15:53:30 EDT 1998 Andrew MacLeod + + * cplus-dem.c (demangle_qualified): Replace missing else. + +Sun Apr 26 15:38:50 1998 Andreas Schwab + + * cplus-dem.c (gnu_special): Fix off-by-one bug when checking the + length in the name of a virtual table. + +Wed Apr 22 10:53:49 EDT 1998 Andrew MacLeod + + * cplus-dem.c (struct work stuff): Add field for B and K mangle codes. + (cplus_demangle_opname): Call mop_up_squangle. + (cplus_demangle): Initialize squangle info, then call + internal_cplus_demangle. (Most code moved there as well) + (internal_cplus_demangle): New function, performs most of what use + to be done in cplus_demangle, but is only called with this file. + (squangle_mop_up): New function to clean up B and K code data. + (mop_up): set pointers to NULL after freeing. + (demangle_signature, demangle_template, demangle_class): Add + switch elements to handle K and B codes. + (demangle_prefix, gnu_special, demangle_qualified): Add + code to handle K and B codes. + (do_type, demangle_fund_type): Handle B and K codes. + (remember_Ktype): New function to store K info. + (register_Btype, remember_Btype): New functions for B codes. + (forget_B_and_K_types): New function to destroy B and K info. + +Fri Apr 10 01:49:10 1998 Jeffrey A Law (law@cygnus.com) + + * COPYING.LIB, choose-temp.c, cplus-dem.c: Sync with egcs & gcc. + +Thu Mar 5 09:23:28 1998 Manfred Hollstein + + * config.table: Make locating frag files failsafe even for the + special case if configuring and building in srcdir. + +Mon Feb 23 14:33:15 1998 Ian Lance Taylor + + * choose-temp.c: Fix handling of sys/file.h to work in libiberty. + +Sun Feb 22 18:03:23 1998 Jeffrey A Law (law@cygnus.com) + + * choose-temp.c: Sync with copy in gcc. + +Thu Feb 12 16:29:49 1998 Ian Lance Taylor + + * getopt.c: Update to latest FSF version. + * getopt1.c: Likewise. + +Tue Feb 10 16:58:33 1998 Stan Shebs + + * cplus-dem.c (gnu_special): Don't get confused by . + strings that are not actually lengths. + +Fri Feb 6 01:35:17 1998 Manfred Hollstein + + * Makefile.in (FLAGS_TO_PASS): Don't pass PICFLAG. + (.c.o): Check value of enable_shared, not PICFLAG. + (stamp-picdir): Dito. + +Thu Feb 5 18:48:56 1998 Geoffrey Noer + + * config/mh-cygwin32: remove vasprintf.o from EXTRA_OFILES + since it gets built automatically + +Sun Feb 1 02:52:32 1998 Mike Stump + + * config.table (vxworks configs): Default to VxWorks 5.x, as that is + the currently shipping OS. + +Tue Jan 27 16:08:20 1998 Pat Rankin + + * vmsbuild.com [REQUIRE_OFILES]: Synchronized with Makefile.in: + Add fnmatch.o and objalloc.o; remove vasprintf.o. + [config.h]: Define NEED_strsignal. + +Mon Jan 19 12:20:01 1998 Ian Lance Taylor + + * functions.def: Correct argument types for strerror and + strsignal. Reported by Alex Gutman . + +Sun Jan 18 15:57:28 1998 Michael Snyder + + * vasprintf.c (int_vasprintf): Increase buffer size for float/double + values. + +Sat Jan 17 22:28:38 1998 Mumit Khan + J.J. VanderHeijden + + Add mingw32 support. + * pexecute.c (pexecute): New function for mingw32. Supports pipes. + (pwait): New function for mingw32. + + * config.table (i[3456]86-*-mingw32*): Support for i386-mingw32. + * config/mt-mingw32: New file. + * xmalloc.c (first_break): Not used for mingw32. + (xmalloc_set_program_name): Don't use sbrk on mingw32. + (xmalloc): Likewise. + (xrealloc): Likewise. + +Sat Jan 17 22:28:05 1998 Jeffrey A Law (law@cygnus.com) + + * choose-temp.c: Sync with gcc version. + +Tue Jan 13 18:34:39 1998 Jim Wilson + + * Makefile.in (install_to_libdir, install_to_tooldir): Add MULTISUBDIR + to all filenames in libdir and tooldir. + (distclean): Do MULTICLEAN before deleting Makefile. + (stamp-needed, stamp-config): Add MULTISRCTOP to + pathname for move-if-change. + +Thu Dec 4 17:25:19 1997 Jeffrey A Law (law@cygnus.com) + + * strsignal.c (sys_nsig): Try NSIG and _NSIG. + +Wed Nov 19 13:37:06 1997 Michael Meissner + + * alloca-norm.h (alloca, GCC case): Don't redefine alloca if it + was already defined previously. + +Mon Nov 10 12:48:03 1997 Philippe De Muyter + + * Makefile.in (INSTALL): Use ../install-sh, not install. + +Tue Oct 28 23:41:15 1997 Judy Goldberg + + * Makefile.in (CFILES): Add pexecute.c. + +Wed Oct 15 19:13:48 1997 Ian Lance Taylor + + * asprintf.c: Consistently use either stdarg or varargs. + +Tue Oct 14 12:01:00 1997 Mark Mitchell + + * cplus-dem.c (demangle_signature): Don't look for return types on + constructors. Handle member template constructors. + +Fri Oct 3 17:53:30 1997 Ian Lance Taylor + + * README: Fix configuration instructions. + +Mon Sep 29 12:28:41 1997 Ian Lance Taylor + + * pexecute.c: Update to current version from /gd/gnu/lib: + + Mon Sep 29 12:27:59 1997 Ian Lance Taylor + + * pexecute.c: Use spawn if __CYGWIN32__. + + 1997-08-08 Paul Eggert + + * pexecute.c: Include "config.h" first, as per autoconf manual. + + Fri Jun 27 15:20:29 1997 Scott Christley + + * pexecute.c (fix_argv): New function. + (pexecute): Win32 but not Cygwin32 needs its arguments fixed. + Add underscore to cwait function call. + +Sun Sep 28 12:00:52 1997 Mark Mitchell + + * cplus-dem.c (demangle_template): Add new parameter. Handle new + template-function mangling. + (consume_count_with_underscores): New function. + (demangle_signature): Handle new name-mangling scheme. + +Wed Sep 24 00:31:59 1997 Felix Lee + + * asprintf.c: stdarg.h when ALMOST_STDC + * config/mh-windows (EXTRA_OFILES): add asprintf.o and + strncasecmp.o. + +Thu Aug 28 14:27:15 1997 Andrew Cagney + + * vasprintf.c (vasprintf): Allow for _BSD_VA_LIST_. + + * config.table: Add case for FreeBSD 2.1 and 2.2, needs mh-fbsd21. + + * config/mh-fbsd21 (EXTRA_OFILES): Force vasprintf.o + +Wed Sep 10 12:43:10 1997 Jason Merrill + + * cplus-dem.c (demangle_fund_type): Change "complex" to "__complex". + +Fri Sep 5 16:34:42 1997 Andrew Cagney + + * asprintf.c (asprintf): New file. + * Makefile.in (CFILES): Add asprintf.c + * functions.def: Ditto. + +Thu Aug 28 18:53:34 1997 Andrew Cagney + + * argv.c (dupargv): New function, duplicate an argument vector. + +Tue Aug 19 20:28:45 1997 Geoffrey Noer + + * config/mh-cygwin32: also build random.o + +Tue Aug 19 17:10:56 1997 Jason Merrill + + * cplus-dem.c: Add 'extern' to prepends_underscore. + +Wed Jul 30 11:42:19 1997 Per Bothner + + * cplus-dem.c: Various changes to produce Java output when passed + DMGL_JAVA. Thus "::" becomes "." and "JArray" becomes "Foo[]". + (main): Support --java and -j flags to set DMGL_JAVA. + +Tue Jul 22 19:05:23 1997 Robert Hoehne + + * config/mh-go32 (CC, AR, RANLIB): Don't define. + +Tue Jul 22 17:49:54 1997 Ian Lance Taylor + + * Makefile.in (REQUIRED_OFILES): Add pexecute.o. + (pexecute.o): New target. + + * Makefile.in (stamp-needed): New target, replacing needed-list. + (needed-list): Just depend upon stamp-needed. + (stamp-config): New target, replacing config.h. + (config.h): Just depend upon stamp-config. + (mostlyclean): Remove stamp-*. + +Thu Jun 12 11:00:18 1997 Angela Marie Thomas (angela@cygnus.com) + + * Makefile.in (FLAGS_TO_PASS): pass INSTALL, INSTALL_PROGRAM and + INSTALL_DATA for multilibbed installs + +Tue Jun 3 13:21:05 1997 Doug Evans + + Tue Dec 10 09:44:57 1996 Paul Eggert + + * choose-temp.c (choose_temp_base): Don't dump core if TMPDIR is empty. + + * choose-temp.c (try): Insist that temp dir be searchable. + + Wed Oct 23 17:36:39 1996 Doug Rupp (rupp@gnat.com) + + * choose-temp.c (choose_temp_base): On VMS, use proper syntax + for current directory. + + Sat Feb 15 19:03:48 1997 Geoffrey Noer (noer@cygnus.com) + + * pexecute.c: Remove special cases for cygwin32. + (pwait): Remove local definition of `pid'. + + Tue Nov 12 18:26:15 1996 Doug Rupp (rupp@gnat.com) + + * pexecute.c (vfork): Supply new definition for VMS. + (pwait): Use waitpid instead of wait for VMS. + +Tue May 20 14:02:20 1997 Brendan Kehoe + + * cplus-dem.c (do_type): Handle `J'. + (demangle_fund_type): Print "complex" for it. + +Wed Apr 30 12:15:45 1997 Jason Merrill + + * configure.in: Don't turn on multilib here. + +Mon Apr 28 19:04:31 1997 Michael Snyder + + * obstack.c: move _obstack_memory_used outside of ifdef. Cannot be + elided; needed by gdb and not present in libc. + +Thu Apr 24 19:33:47 1997 Ian Lance Taylor + + * Makefile.in (clean): Remove tmpmulti.out. + +Tue Apr 22 10:25:15 1997 Fred Fish + + * floatformat.c (floatformat_ieee_double_littlebyte_bigword): + Add new floatformat, mainly for ARM doubles. + +Mon Apr 14 12:11:16 1997 Ian Lance Taylor + + * config.table: Use ${config_shell} with ${moveifchange}. From + Thomas Graichen . + +Fri Apr 4 03:09:24 1997 Ulrich Drepper + + * configure.in: Enable multilibing by default. + Update multilib template to read config-ml.in. + +Tue Apr 1 16:26:39 1997 Klaus Kaempf + + * makefile.vms: Add objalloc. + +Mon Mar 31 23:57:51 1997 H.J. Lu + + * cplus-dem.c (demangle_it): Add prototype declaration. + (usage, fatal): Likewise. + + * xexit.c (_xexit_cleanup): Add prototype. + + * strerror.c (init_error_tables): Declare. + +Fri Mar 28 11:43:20 1997 H.J. Lu + + * functions.def: Add DEF of vasprintf, and DEFFUNC of strsignal. + * strsignal.c: Only define strsignal if NEED_strsignal. + * Makefile.in (REQUIRED_OFILES): Remove vasprintf.o. + * configure.in: Add NEED_strsignal to xconfig.h. Add vasprintf.o + to xneeded-list. + * config/mh-cygwin32 (HDEFINES): Add -DNEED_strsignal. + (EXTRA_OFILES): Define to vasprintf.o. + * config/mh-windows (HDEFINES): Add -DNEED_strsignal. + (EXTRA_OFILES): Add vasprintf.o. + * config/mt-vxworks5 (vxconfig.h): Define NEED_strsignal. + (vxneeded-list): Add vasprintf.o. + +Thu Mar 20 17:02:09 1997 Ian Lance Taylor + + * objalloc.c: Include . + +Mon Mar 17 19:23:11 1997 Ian Lance Taylor + + * objalloc.c: New file. + * Makefile.in (CFILES): Add objalloc.c + (REQUIRED_OFILES): Add objalloc.o. + (objalloc.o): New target. + +Sat Mar 15 18:49:41 1997 Ian Lance Taylor + + * obstack.c: Update to current FSF version. + +Fri Mar 14 14:18:47 1997 Ian Lance Taylor + + * cplus-dem.c: Add prototypes for all static functions. + (mystrstr): Make static. Make arguments and result const. + (cplus_match): Remove; not used. + +Tue Mar 11 14:20:31 1997 Brendan Kehoe + + * cplus-dem.c (gnu_special): Call demangled_fund_type for other + __t* symbols. + +Tue Mar 11 15:41:21 1997 H.J. Lu + + * spaces.c: Declare malloc and free properly. + * strsignal.c (init_signal_tables): Add prototype. + * xatexit.c (_xexit_cleanup): Add parameter declarations. + +Wed Feb 19 15:43:24 1997 Brendan Kehoe + + * Makefile.in (lneeded-list): If alloca.o is needed, xexit.o is + also required because of xmalloc.o. + +Fri Feb 14 13:43:38 1997 Ian Lance Taylor + + * strsignal.c: Unconditionally redefine sys_siglist around the + inclusion of the system header files. + +Thu Feb 13 22:01:04 1997 Klaus Kaempf + + * makefile.vms: Remove 8 bit characters. Update to latest + gcc release. + +Tue Feb 4 11:52:19 1997 Ian Lance Taylor + + * strsignal.c: Use NEED_sys_siglist instead of + LOSING_SYS_SIGLIST. + * config.table: Don't use mh-lynxos. + * config/mh-lynxos: Remove. + +Thu Jan 16 14:51:03 1997 Bob Manson + + * cplus-dem.c: Fix indenting; make identical to the copy + in GCC. + (do_type, case 'M'): Check for a template as well as a class. + +Thu Dec 19 13:51:33 1996 Brendan Kehoe + + * config/mt-vxworks5 (vxneeded-list): Remove sigsetmask.o, since + vxworks 5.[0-3] all have sigsetmask in them; the one provided by + libiberty is incorrect, as well. + +Mon Dec 2 15:03:42 1996 Michael Meissner + + * alloca.c (alloca): When compiled with an ANSI/ISO compiler, + alloca takes a size_t argument, not just unsigned. + +Mon Nov 18 15:42:08 1996 Jason Merrill + + * cplus-dem.c: Note that this file also lives in GCC. + +Mon Nov 18 15:19:00 1996 Dawn Perchik + + * alloca.c: Remove include of libiberty.h for hpux. + * argv.c: Replace defs from libiberty.h. + * spaces.c: Put back externs from removed from libiberty.h. + * vasprintf.c: Remove include of libiberty.h for hpux. + +Mon Nov 18 14:08:00 1996 Dawn Perchik + + * cplus-dem.c: Checking in again; last checkin filed due to sticky tag. + +Wed Nov 13 08:22:00 1996 Dawn Perchik + + * cplus-dem.c: Revert last two commits due to conflicts with + hpux system headers. + +Wed Nov 13 08:22:00 1996 Dawn Perchik + + * alloca.c, argv.c, spaces.c, strcasecmp.c, vasprintf.c, vprintf.c: + Revert last commit due to conflicts with hpux system headers. + +Wed Nov 13 10:36:50 1996 Michael Meissner + + * cplus-dem.c (x{m,re}alloc): Make declarations compatibile with + libiberty.h when compiled with a standard compiler. + +Tue Nov 12 16:31:00 1996 Dawn Perchik + + * alloca.c: Include libiberty.h for definition of xmalloc. + Don't redefine NULL. + * argv.c: Move prototypes to libiberty.h. + * cplus-dem.c: Include libiberty.h for definition of xmalloc. + Don't redefine NULL. + Use casts to eliminate compiler warnings. + * spaces.c: Remove prototypes for malloc and free which are + already in libibrty.h. + * strcasecmp.c: Use casts to eliminate compiler warnings. + * vasprintf.c: Include libiberty.h for definition of malloc. + Don't redefine NULL. + * vprintf.c: Include stdarg.h if __STDC__. + +Fri Oct 11 15:42:12 1996 Stu Grossman (grossman@critters.cygnus.com) + + * config/mh-windows: Add strcasecmp.o to EXTRA_OFILES. + +Fri Oct 11 11:16:31 1996 Stan Shebs + + * mpw.c (mpwify_filename): Rewrite to simplify, and to handle + upward components correctly. + +Tue Oct 8 08:55:34 1996 Stu Grossman (grossman@critters.cygnus.com) + + * config.table, config/mh-windows: Add support for building under + MSVC (the Microsoft build environment). + +Mon Oct 7 10:50:27 1996 Ian Lance Taylor + + * fnmatch.c: Undef const if not __STDC__. + +Thu Oct 3 13:46:39 1996 Ian Lance Taylor + + * fnmatch.c: New file. + * Makefile.in (CFILES): Add fnmatch.c. + (REQUIRED_OFILES): Add fnmatch.o. + (fnmatch.o): New target. + +Wed Sep 18 14:49:13 1996 Jason Merrill + + * cplus-dem.c (demangle_template): Fix handling of address args. + (gnu_special): Handle type_info stuff. + +Fri Sep 13 17:52:55 1996 Stan Shebs + + * mpw.c (DebugPI): Make settable from the env var DEBUG_PATHNAMES. + (mpwify_filename): Handle "::/" case. + +Thu Sep 12 13:30:40 1996 Geoffrey Noer + + * config/mh-cygwin32: new file (need -DNEED_basename and + -DNEED_sys_siglist for native NT rebuilding) + * config.table (*-*-cygwin32): new entry + * choose-temp.c: bring in sync with gcc (revert Aug 17 change) + +Thu Aug 29 16:48:45 1996 Michael Meissner + + * config.table (i[345]86-*-*): Recognize i686 for pentium pro. + +Tue Aug 27 13:47:58 1996 Stan Shebs + + * pexecute.c (pexecute) [MPW]: Remove old bogus code that + messed with arguments that included a '/', add escape chars + to double quotes, remove const decl from arg that Mac + compilers don't seem to like. + +Sat Aug 17 04:44:27 1996 Geoffrey Noer + + * pexecute.c: Update test for win32 (&& ! cygwin32). + * choose-temp.c: fix WIN32 preprocessor defines + +Thu Aug 15 12:26:48 1996 Stan Shebs + + * mpw-make.sed: Add @DASH_C_FLAG@ and @SEGMENT_FLAG({Default})@ + to editing of default makefile rule. + +Sun Aug 11 21:03:27 1996 Stu Grossman (grossman@critters.cygnus.com) + + * alloca-norm.h: Include if _WIN32. + * argv.c: Include non-prototyped decls for malloc and string + functions if ! _WIN32 or if __GNUC__. + +Thu Aug 8 12:42:40 1996 Klaus Kaempf + + * config.h-vms: New file. + * makefile.vms: Use it. + +Wed Aug 7 17:16:12 1996 Stu Grossman (grossman@critters.cygnus.com) + + * getopt.c (_getopt_internal): If argc is 0, just return (before + we reference *argv and segfault). + +Mon Aug 5 01:29:08 1996 Jason Merrill + + * Makefile.in (distclean): Add multilib.out. + +Thu Jul 18 17:40:55 1996 Ian Lance Taylor + + * alloca-norm.h: Change #ifdef sparc to #if defined (sparc) && + defined (sun). From Andrew Gierth . + +Mon Jul 1 13:40:44 1996 Ken Raeburn + + Tue May 28 15:29:03 1996 Pat Rankin + + * vmsbuild.com (REQUIRD_OFILES): Add choose-temp.o and xstrdup.o. + + Thu Jan 25 18:20:04 1996 Pat Rankin + + * vmsbuild.com: Changes to handle DEFFUNC(on_exit). + (do_ofiles): Allow nonexistent source file in pass 3. + (chk_deffunc): New routine. + +Tue Jun 25 19:24:43 1996 Doug Evans + + * pexecute.c (PEXECUTE_VERBOSE): Define. + (MPW pexecute): Check flags & PEXECUTE_VERBOSE instead of verbose_flag. + +Tue Jun 25 23:11:48 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (docdir): Removed. + +Tue Jun 25 23:01:07 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (oldincludedir): Removed. + +Tue Jun 25 22:50:07 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (datadir): Set to $(prefix)/share. + +Thu Jun 20 21:17:52 1996 Ian Lance Taylor + + * cplus-dem.c (demangle_arm_pt): Reindent. Avoid endless loop by + checking for errors from do_type. + +Tue Jun 18 14:36:19 1996 Klaus Kaempf + + * makefile.vms: New file. + * xmalloc.c: If VMS, include and rather + than declaring malloc, realloc, and sbrk. + +Mon Jun 10 13:17:17 1996 Doug Evans + + * pexecute.c: New file. + +Wed Jun 5 16:57:45 1996 Richard Henderson + + * xmalloc.c: Declare sbrk. + +Sat May 4 05:08:45 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alloca-norm.h: Add SPARCworks cc compatible __builtin_alloca + declaration. + +Mon Apr 22 18:41:49 1996 Ian Lance Taylor + + * xstrerror.c: Include . + +Sun Apr 21 11:55:12 1996 Doug Evans + + * Makefile.in (CFILES): Add atexit.c. + +Sun Apr 21 09:50:09 1996 Stephen L Moshier (moshier@world.std.com) + + * choose-temp.c: Include sys/types.h before sys/file.h for sco3.2v5. + +Wed Apr 17 11:17:55 1996 Doug Evans + + * choose-temp.c: Don't #include sys/file.h ifdef NO_SYS_FILE_H. + #include + * config/mt-vxworks5 (HDEFINES): Define NO_SYS_FILE_H. + +Tue Apr 16 11:27:16 1996 Jeffrey A Law (law@cygnus.com) + + * Makefile.in (lneeded-list): If alloca.o is needed, so is xmalloc.o. + Reverts Feb 8, 1995 change. + +Mon Apr 15 12:53:26 1996 Doug Evans + + * choose-temp.c: New file. + * Makefile.in (CFILES): Add choose-temp.c. + (REQUIRED_OFILES): Add choose-temp.o. + +Sat Apr 13 14:19:30 1996 Stu Grossman (grossman@critters.cygnus.com) + + * floatformat.c (floatformat_to_double): Don't bias exponent when + handling zero's, denorms or NaNs. + +Thu Apr 11 13:36:56 1996 Stu Grossman (grossman@critters.cygnus.com) + + * floatformat.c (floatformat_to_double): Fix bugs with handling + numbers with fractions < 32 bits. + +Mon Apr 8 14:48:34 1996 Ian Lance Taylor + + * config.table: Permit --enable-shared to specify a list of + directories. + +Tue Mar 19 22:02:07 1996 Jason Merrill + + * cplus-dem.c (demangle_template): Fix for non-mangled pointer + arguments. + +Fri Mar 8 17:24:18 1996 Ian Lance Taylor + + * configure.in: If srcdir is `.' and with_target_subdir is not + `.', then set MULTISRCTOP before calling config-ml.in. + +Thu Mar 7 13:37:10 1996 Stan Shebs + + * mpw.c (mpw_open): Add debugging output option. + +Wed Mar 6 17:36:03 1996 Jason Merrill + + * cplus-dem.c (demangle_template): Fix for address-of-extern arguments. + +Tue Feb 27 12:00:50 1996 Raymond Jou + + * mpw.c (mpwify_filename): Change 6 to 5 in + strncmp (unixname, "/tmp/", 5). + +Tue Feb 20 10:55:53 1996 Ian Lance Taylor + + * cplus-dem.c (demangle_template): Initialize is_bool. Correctly + handle 0 as a pointer value parameter. + +Mon Feb 5 16:41:44 1996 Ian Lance Taylor + + * Makefile.in (all): Depend upon required-list. + (required-list): New target. + (clean): Remove required-list. + +Wed Jan 31 10:19:41 1996 Steve Chamberlain + + * win32.c: Deleted. + * config.table (i386-*-win32): Deleted. + * config/mh-i386win32: Deleted. + +Thu Jan 18 11:34:17 1996 Ian Lance Taylor + + * cplus-dem.c (cplus_demangle_opname): Change opname parameter to + const char *. + (cplus_mangle_opname): Change return type and opname parameter to + const char *. Don't cast return value. + +Tue Jan 16 12:13:11 1996 Stan Shebs + + * mpw.c: Include Timer.h, in order to get m68k Microseconds trap + definition. + +Wed Jan 3 13:15:04 1996 Fred Fish + + * obstack.c: Update copyright to 1996. + (_obstack_memory_used): Define new function. Called via + obstack_memory_used macro. + +Thu Dec 28 11:39:40 1995 Ian Lance Taylor + + * xstrdup.c: New file. + * Makefile.in (CFILES): Add xstrdup.c. + (REQUIRED_OFILES): Add xstrdup.o. + (xstrdup.o): New target. + +Mon Dec 11 18:18:52 1995 Mike Stump + + * atexit.c: New stub to provide atexit on systems that have + on_exit, like SunOS 4.1.x systems. + * functions.def (on_exit, atexit): Ditto. + +Mon Dec 11 15:42:14 1995 Stan Shebs + + * mpw.c (mpw_abort): Remove decl. + (mpw_access): Move debugging printf. + +Sat Dec 2 01:25:23 1995 Ian Lance Taylor + + * config.table: Consistently use ${host} rather than ${xhost} or + ${target}. + * configure.in: Don't bother to set ${xhost} before calling + config.table. + +Tue Nov 28 14:16:57 1995 Brendan Kehoe + + * Makefile.in (.c.o): Use test instead of the left bracket, to + avoid problems with some versions of make. + +Tue Nov 28 11:45:17 1995 Stan Shebs + + * mpw-make.sed: Fix INCDIR edit to work with Nov 14 change. + +Tue Nov 21 11:26:34 1995 Fred Fish + + * config/mh-hpux: Remove. It was only used to define EXTRA_OFILES, + which was set to just alloca.o, which is now automatically marked + as needed by the autoconfiguration process. + +Tue Nov 21 14:15:06 1995 Ian Lance Taylor + + * config.table: Check ${with_cross_host} rather than comparing + ${host} and ${target}. + +Thu Nov 16 14:34:42 1995 Ian Lance Taylor + + * configure.in: If with_target_subdir is empty, set xhost to + ${host} rather than ${target} before calling config.table. + +Tue Nov 14 01:38:30 1995 Doug Evans + + * Makefile.in (MULTITOP): Deleted. + (MULTISRCTOP, MULTIBUILDTOP): New. + (FLAGS_TO_PASS): Delete INCDIR. + (INCDIR): Add $(MULTISRCTOP). + (install_to_libdir): Add $(MULTISUBDIR). Call $(MULTIDO). + * configure.in: Delete call to cfg-ml-com.in. Call config-ml.in + instead of cfg-ml-pos.in. + (cross-compile check): Change to test for with_target_subdir. + (EXTRA_LINKS): Delete. + +Sun Nov 12 12:13:04 1995 Stan Shebs + + * mpw-make.sed: Add getpagesize.c.o to needed-list. + * mpw.c [USE_MW_HEADERS]: Conditionalize compiling of + functions that are supplied by Metrowerks libraries. + (fstat): Clean up descriptor->pointer conversion code. + (InstallConsole, etc): Empty definitions, for when linking + with SIOUX. + +Sun Nov 5 19:25:27 1995 Per Bothner + + * Makefile.in (FLAGS_TO_PASS): Also pass PICFLAGS. + (.c.o): Stylistic change. + +Thu Nov 2 12:06:29 1995 Ian Lance Taylor + + * strtol.c, strtoul.c: Don't include . From + phdm@info.ucl.ac.be (Philippe De Muyter). + +Wed Nov 1 11:59:36 1995 Ian Lance Taylor + + * configure.in: Correct sed call. + +Mon Oct 30 13:03:45 1995 Per Bothner + + * configure.in: Clean up / simplify for native. + + * configure.in: Merge in stuff from ../xiberty/configure.in. + * Makefile.in (CC): Add definition (so it can be overrridden + by ../configure). + +Tue Oct 24 17:57:27 1995 Stan Shebs + + * mpw-make.sed: Leave strerror.c.o in standard list of functions. + * mpw.c (R_OK, ENOENT, EACCESS, ENOSYS): Remove. + (link): Remove useless definition with error return. + (last_microseconds, warn_if_spin_delay, record_for_spin_delay): + Use UnsignedWide type for microsecond counts. + +Thu Oct 19 10:52:07 1995 Michael Meissner + + * memcmp.c (memcmp): Argument types are const void *, not void + *const. + + * strncasecmp.c (strncasecmp): Include ansidecl.h/stdarg.h, not + sys/types.h. + * strcasecmp.c (strcasecmp): Ditto. + +Tue Oct 10 11:03:24 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + +Tue Sep 26 15:06:46 1995 Stan Shebs + + * Makefile.in (HFILES): Add default empty definition. + * mpw-config.in (config.h): Only update if changed. + * mpw-make.in: Remove. + * mpw-make.sed: New file, edits Makefile.in into MPW makefile. + * mpw.c: Remove semi-clone of strerror code. + (sys_nerr, sys_errlist): Define here. + (Microseconds): Only define as A-line trap if m68k Mac. + +Wed Sep 20 12:53:32 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for distclean. + +Mon Aug 28 19:47:52 1995 Per Bothner + + * config.table: For host, generalize rs6000-ibm-aix* + to *-ibm-aix* so we also include powerpc. + +Tue Aug 22 03:18:05 1995 Ken Raeburn + + Fri Jun 16 18:35:40 1995 Pat Rankin (rankin@eql.caltech.edu) + + * xstrerror.c: New file. + * Makefile.in, vmsbuild.com: Compile it. + +Mon Jul 31 12:16:32 1995 steve chamberlain + + * config.table (i386-*-win32): New. + +Fri Jul 21 11:35:52 1995 Doug Evans + + * Makefile.in (MULTITOP): New variable. + (MULTIDIRS, MULTISUBDIR, MULTIDO, MULTICLEAN): Likewise. + (all): Add multilib support. + (install_to_tooldir, *clean): Likewise. + +Mon Jul 10 11:47:27 1995 Ken Raeburn + + * makefile.dos (OBJS): Add hex.o. From DJ Delorie. + +Fri Jun 30 17:28:59 1995 Pat Rankin (rankin@eql.caltech.edu) + + * vmsbuild.com: create "new-lib.olb", build libiberty under that + name, and then make it become "liberty.olb" when done, so that an + incomplete build attempt never leaves behind something which looks + like a complete library. + +Thu Jun 29 00:22:02 1995 Steve Chamberlain + + * config/mh-i386pe: New file for PE hosts. + * config.table: Understand PE hosts. + +Wed Jun 28 19:13:23 1995 Jason Merrill + + * cplus-dem.c: Update from gcc. + + * argv.c, dummy.c: If __STDC__, #include "alloca-conf.h" after + . + * alloca-norm.h: If __STDC__, declare alloca with its parameter. + +Thu Jun 22 18:57:47 1995 Stan Shebs + + * mpw-make.in (ALL_CFLAGS): Define NEED_basename. + * mpw.c: Only test DebugPI once whenever printing debug info. + (mpwify_filename): If filename is /tmp/foo, change it into :_foo, + also fix to not write on input filename buffer. + (mpw_access): Use stat() instead of open(), works for directories + as well as files. + +Mon Jun 19 00:33:22 1995 Jason Merrill + + * Makefile.in: Massage broken shells that require 'else true'. + +Sat Jun 17 23:21:58 1995 Fred Fish + + * alloca-norm.h: Declare alloca as type "PTR" to match functions.def. + Declare __builtin_alloca in the sparc case, as argv.c did. + * argv.c: Replace inline version of alloca-norm.h at start of file with + a #include of alloca-conf.h. Precede it with an include of ansidecl.h + because alloca-norm.h needs to declare alloca as "PTR". + +Mon Jun 12 14:24:26 1995 Steve Chamberlain + + * win32.c: New file. + +Fri Jun 9 15:16:14 1995 Jason Merrill + + * dummy.c: #include "alloca-conf.h". + +Wed Jun 7 11:46:23 1995 Jason Merrill + + * Makefile.in (mostlyclean): Remove stamp-picdir. + (clean): Don't. + +Mon Jun 5 18:46:06 1995 Jason Merrill + + * config.table (frags): Use toplevel pic frags. + + * Makefile.in (PICFLAG): New macro. + (all): Depend on stamp-picdir. + (needed-list): Ditto. + (.c.o): Also build pic object. + (stamp-picdir): New rule. + (mostlyclean): Remove pic. + (clean): Remove stamp-picdir. + +Fri Mar 24 16:55:48 1995 Pat Rankin (rankin@eql.caltech.edu) + + * vmsbuild.com (config.h): Add `#define NEED_basename'. + +Tue May 23 10:12:46 1995 Per Bothner + + * clock.c, getopt.c, strtod.c, vsprintf.c: Change from using LGPL + to libio-style copyright. + * getpagesize.c: Remove FSF copyright. + +Sat May 20 12:30:23 1995 Ken Raeburn + + Added improved VMS support from Pat Rankin: + + Fri Mar 17 18:40:36 1995 Pat Rankin (rankin@eql.caltech.edu) + + * vmsbuild.com: new file. + + * getpagesize.c (getpagesize): implement for VMS; + * strerror.c (strerror, strerrno, strtoerrno): add rudimentary + support for EVMSERR. + +Thu May 18 17:01:42 1995 Ken Raeburn + + Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * floatformat.c (floatformat_arm_ext): Define. + +Tue May 16 13:30:59 1995 Per Bothner + + * basename.c, bcmp.c, getcwd.c, insque.c, rename.c, sigsetmask.c, + strerror.c, strsignal.c: Remove FSF copyright. + * sigsetmask.c: #include - seems to be needed by ISC. + +Mon May 15 19:53:17 1995 Per Bothner + + * bcopy.c, bzero.c, memcmp.c, memcpy.c, memset.c, strchr.c, + strrchr.c, strstr.c, vfork.c: Remove FSF Copyright, because this + might contaminate libstdc++ with the LGPL. (OK'd by RMS 11 Oct 94.) + * strchr.c, strrchr.c: Add cast to suppress const warning. + +Thu May 4 14:36:42 1995 Jason Merrill + + * cplus-dem.c: Use const instead of CONST. Don't include + ansidecl.h directly. + +Wed Apr 19 01:30:27 1995 Jason Merrill + + * cplus-dem.c: Don't include libiberty.h. Do declare xmalloc and + xrealloc. + (-DMAIN): Don't rely on an externally-defined version number; + instead, require the version number to be defined as a + preprocessor macro. Handle the RS/6000 leading dot. Define + xmalloc, xrealloc and fatal. Don't strip a leading underscore + if we couldn't demangle the word. + +Tue Apr 4 13:03:51 1995 Stan Shebs + + (Old mpw.c change descriptions retained for informational value.) + * mpw.c (warning_threshold): Default to .4 sec. + (overflow_count, current_progress): New globals. + (warn_if_spin_delay): Include current progress type, + such as program name, in message. + (mpw_start_progress): Set current_progress variable from arg. + (mpw_end_progress): Report spin delays by power-of-two-size + buckets instead of constant-size buckets. + + * mpw.c: Clean up formatting, types, returns, etc. + (ENOSYS): Define. + (mpw_fread, mpw_fwrite): Define. + (sleep): Define correctly. + + * mpw.c: New code to implement cursor spinning support. + (umask): New function. + (mpw_fopen, mpw_fseek, stat, fstat): Call PROGRESS. + + * mpw.c (mpw_basename, mpw_mixed_basename): New functions, find + basenames for MPW and MPW/Unix filenames. + (mpw_special_init): New function, calls Macsbug if desired. + + * mpw.c: Add GPL notice. + (mpwify_filename): Add more transformations. + (mpw_fopen): Call mpwify_filename on file names. + (rename): Remove. + (chdir, getcwd): Add simple definitions. + + * mpw.c: Random cleanups, remove unused code bits. + Added copy of strerror.c for gcc's use. + (stat, fstat, _stat): New versions based on Guido van Rossum code. + + * mpw.c (mpw_fseek): Make it work correctly when doing SEEK_CUR. + + * mpw.c (stat): Remove hack definition, get from sys/stat.h. + (fork, vfork, etc): Print error messages if called. + (getrusage, sbrk, environ, isatty, link, utime, mkdir, rmdir, + rename, chown): Define. + + * mpw-config.in: New file, MPW version of configure.in. + * mpw-make.in: New file, MPW version of Makefile.in. + * mpw.c: New file, MPW compatibility routines. + +Fri Mar 24 14:10:30 1995 Jim Kingdon (kingdon@lioth.cygnus.com) + + * basename.c: Include config.h before checking for NEED_basename. + +Thu Mar 23 19:09:54 1995 Jason Merrill + + * functions.def: Add DEFFUNC for basename. + + * basename.c: Only define basename if NEED_basename. + +Thu Mar 16 13:36:05 1995 Jason Merrill + + * config.table: Fix --enable-shared logic for native builds. + +Mon Mar 13 11:05:11 1995 Jason Merrill + + * cplus-dem.c (demangle_template): Demangle bool literals properly. + +Mon Mar 6 23:57:28 1995 Stu Grossman (grossman@cygnus.com) + + * strtol.c strtoul.c: Replace these with less buggy versions from + NetBSD. (strtoul in particular couldn't handle base 16.) + +Wed Mar 1 15:59:01 1995 Ian Lance Taylor + + * config/mt-vxworks5 (HDEFINES): Define NO_SYS_PARAM_H. + + * clock.c: If NO_SYS_PARAM_H is defined, don't include + . + * getcwd.c, getpagesize.c, getruntime.c: Likewise. + +Fri Feb 17 15:40:55 1995 Ian Lance Taylor + + * getruntime.c (get_run_time): Don't assume that CLOCKS_PER_SEC is + a number; ANSI appears to permit any expression, including a + function call. + + * config.table (*-*-vxworks5*): Use mt-vxworks5 when configuring + xiberty. + * config/mt-vxworks5: New file. + +Thu Feb 9 14:19:45 1995 Ian Lance Taylor + + * basename.c (basename): Change argument to be const. + +Wed Feb 8 18:06:52 1995 Jason Merrill + + * Makefile.in (lneeded-list): Don't worry about xmalloc. + +Sun Jan 15 00:40:36 1995 Jeff Law (law@snake.cs.utah.edu) + + * Makefile.in (distclean): Delete xhost-mkfrag. + +Thu Jan 12 16:54:18 1995 Jason Merrill + + * Makefile.in (lneeded-list): If alloca.o is needed, so is xmalloc.o. + +Wed Jan 11 22:39:56 1995 Ken Raeburn + + * hex.c: New file. + * Makefile.in (REQUIRED_OFILES, CFILES): List it. + (hex.o): Add dependencies. + + * cplus-dem.c (demangle_prefix): For GNU style constructor and + destructor names, try demangling the remainder of the string. + +Wed Dec 28 00:49:15 1994 Ian Lance Taylor + + * vasprintf.c (int_vasprintf): New static function. + (vasprintf): Use int_vasprintf. Removes assumption that va_list + is assignment compatible. + +Sat Nov 5 19:29:12 1994 Jason Merrill (jason@phydeaux.cygnus.com) + + * Makefile.in (LIBCFLAGS): New variable. + (FLAGS_TO_PASS): Pass it. + (.c.o): Use it. + +Thu Nov 3 19:09:47 1994 Ken Raeburn + + * getopt.c, getopt1.c: Do compile these functions under Linux, + since many native versions are based on glibc but are buggy. + +Mon Oct 24 15:16:46 1994 Per Bothner + + * vasprintf.c: Make 'format' arg be const, to avoid a mismatch + with prototype in GNU libc. Support stdarg.h as well as varargs.h. + +Tue Oct 11 17:48:27 1994 Jason Merrill (jason@phydeaux.cygnus.com) + + * Makefile.in (REQUIRED_OFILES): Add vasprintf.o. + * functions.def: Remove vasprintf. + +Wed Sep 14 17:04:55 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * xmalloc.c (first_break): New static variable. + (xmalloc_set_program_name): Record sbrk (0) in first_break. + (xmalloc): If memory allocation fails, try to report how much + memory was allocated by the program up to this point. + (xrealloc): Likewise. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * Makefile.in (ERRORS_CC): New variable, defaulted to $(CC). Use it + when linking dummy. + * config.table: Add host RISCiX Makefile frag. + * config/mh-riscix: New file. + +Thu Aug 25 17:29:44 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * Makefile.in (FLAGS_TO_PASS): Define. + ($(RULE1)): Use $(FLAGS_TO_PASS). + +Wed Aug 24 17:08:47 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * vasprintf.c: Include . + (vasprintf): Add casts to void for va_arg to avoid gcc warnings. + * xatexit.c: Declare malloc. + +Fri Aug 19 15:29:12 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_args): Fix a bug in previous patch (the + one below). + +Thu Aug 18 14:37:14 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle args): Handle ARM repeat encoding where + the type index is greater than 9. + +Wed Aug 17 16:13:49 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_qualified): accept optional '_' between + qualified name. This is baecause the template name may end with + numeric and can mixed up with the length of next qualified name. + +Wed Aug 3 05:52:14 1994 D. V. Henkel-Wallace (gumby@cygnus.com) + + * config/mt-sunos4: Use our standard location for cross-includes + and cross-libs when the target is also a "host" environment (ie no + newlib; includes and such don't belong to us). This is specific + to the Cygnus Support environment. + +Tue Aug 2 15:25:12 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_template): demangle as xxx<'Q'> not + xxx. + +Mon Aug 1 17:02:48 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (main): flush stdout to make pipe work. + +Sat Jul 16 12:56:32 1994 Stan Shebs (shebs@andros.cygnus.com) + + * config.table (*-*-cxux7*): Recognize. + * floatformat.c (floatformat_m88110_ext) [HARRIS_FLOAT_FORMAT]: + Harris-specific float format. + * config/mh-cxux7: New file. + +Wed Jun 29 00:26:17 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * cplus-dem.c (demangle_template): Make sure that the result of + consume_count doesn't index beyond the end of the string. + +Mon Jun 20 23:54:37 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * cplus-dem.c (gnu_special): Handle vtable mangling of gcc-2.4.5 and + earlier. Improve test for new vtable mangling. Change output back + to `virtual table'. + +Mon Jun 20 11:37:30 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * obstack.c: Always compile this code, even if using the GNU + library. Avoids problems with relatively recent binary + incompatibility. + +Thu Jun 16 17:54:01 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * cplus-dem.c: Include libiberty.h. + (xmalloc, xrealloc, free): Don't declare. + (strstr): Don't declare parameters. + (xmalloc, xrealloc): Don't define. + (long_options): Add no-strip-underscores. + (main): Call xmalloc_set_program_name. Pass n in short options to + getopt_long. Handle option 'n' to not strip underscores. + (usage): Mention -n and --no-strip-underscores. + +Sun Jun 12 01:37:09 1994 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c (demangle_template): Separate consecutive >'s with a + space. + (gnu_special): Demangle template and qualified names in a vtable name. + +Fri May 27 12:27:52 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + From gas-2.3 and binutils-2.4 net releases: + + Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) + + * makefile.dos: [new] Makefile for dos/go32 + * configure.bat: update for latest files + * msdos.c: remove some functions now in libc.a + +Fri May 20 18:53:32 1994 Per Bothner (bothner@kalessin.cygnus.com) + + * cplus-dem.c (gnu_special): Recognize thunks, as well as + the new naming style for vtables (when -fvtable-thunks). + +Wed May 18 13:34:06 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * Makefile.in (XTRAFLAGS): Don't define. + (.c.o, dummy.o): Don't use XTRAFLAGS. + ($(RULE1)): Don't pass XTRAFLAGS down in recursive call. + +Fri May 13 16:02:12 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * vasprintf.c: New file. + * Makefile.in, functions.def: Add it. + +Fri May 13 16:20:28 1994 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c (demangle_fund_type): Grok bool. + +Fri May 6 14:44:21 1994 Steve Chamberlain (sac@cygnus.com) + + * config.table: Add go32 + * config/mh-go32: New template. + +Fri May 6 11:01:59 1994 D. V. Henkel-Wallace (gumby@rtl.cygnus.com) + + * config.table, config/mt-sunos4: config for when sun4 is cross target. + +Mon Apr 11 00:54:33 1994 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * getopt.c [not __GNU_LIBRARY__] [__GCC__] [not __STDC__]: + Declare strlen to return int. Don't include stddef.h. + +Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) + + * getopt.c: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. + +Thu Apr 14 14:00:56 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_signature): Fix a bug in template function + type numbering. + +Wed Apr 13 17:23:03 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_signature): Fix template function with arm + style argument type number, Tn. + +Wed Apr 13 17:11:15 1994 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c (optable): Add new[] and delete[]. + +Fri Apr 8 11:21:42 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * argv.c (buildargv): Don't produce empty argument just because + there is trailing whitespace. + +Wed Apr 6 11:42:14 1994 Kung Hsu (kung@mexican.cygnus.com) + + * cplus-dem.c (demangle_template): fix 'Q' qualified name bug. + Handle 'p' same as 'P'. + * cplus-dem.c (do_type): Handle 'p' same as 'P'. + +Sat Mar 26 12:00:13 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * floatformat.c (get_field, put_field): Fix off by one error in + little endian case. + +Thu Mar 24 10:40:19 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * floatformat.c (floatformat_from_double): Pass unsigned char *, + not char *, to put_field. + +Fri Mar 18 12:34:33 1994 Per Bothner (bothner@kalessin.cygnus.com) + + * memmove.c: Re-wrote; placed in public domain. + +Wed Mar 16 10:33:07 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * cplus-dem.c (demangle_prefix): If ARM demangling, don't treat + __Q* as a constructor. + +Mon Mar 14 12:26:02 1994 Ian Lance Taylor (ian@cygnus.com) + + * ieee-float.c: Removed; no longer used. + * Makefile.in: Changed accordingly. + +Mon Mar 7 12:28:17 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * floatformat.c (get_field): Removed unused local variable i. + (put_field): Removed unused local variable i. + +Sun Feb 27 21:50:11 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * floatformat.c: New file, intended to replace ieee-float.c. + * Makefile.in: Change accordingly. + +Thu Feb 24 11:51:12 1994 David J. Mackenzie (djm@rtl.cygnus.com) + + * getopt.c: Remove #ifdef GETOPT_COMPAT and #if 0 code. + (_getopt_initialize): New function, broken out of _getopt_internal. + (_getopt_internal): + If long_only and the ARGV-element has the form "-f", where f is + a valid short option, don't consider it an abbreviated form of + a long option that starts with f. Otherwise there would be no + way to give the -f short option. + +Thu Feb 10 14:44:16 1994 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * getopt.c [not __GNU_LIBRARY__] [__GNUC__] [not IN_GCC]: + Test just __STDC__, not emacs. + +Wed Feb 9 00:14:00 1994 Richard Stallman (rms@mole.gnu.ai.mit.edu) + + * getopt.c [not __GNU_LIBRARY__] [__GNUC__] [not IN_GCC] + [emacs] [not __STDC__]: Don't include stddef.h. Don't declare strlen. + +Fri Dec 24 19:43:00 1993 Noah Friedman (friedman@nutrimat.gnu.ai.mit.edu) + + * getopt.c (_NO_PROTO): Define before config.h is included. + +Mon Sep 20 15:59:03 1993 Roland McGrath (roland@churchy.gnu.ai.mit.edu) + + * getopt.c, getopt1.c [emacs || CONFIG_BROKETS]: Include + only under these, else "config.h". + +Thu Aug 12 18:16:49 1993 Roland McGrath (roland@churchy.gnu.ai.mit.edu) + + * getopt.c, getopt1.c [HAVE_CONFIG_H]: Include + instead of "config.h". + +Sun Feb 20 17:17:01 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * concat.c: Check ANSI_PROTOTYPES rather than __STDC__ to decide + whether to use prototypes or not. + * strerror.c (const): Never undefine; let ansidecl.h handle it. + * strsignal.c (const): Likewise. + +Thu Feb 17 13:27:35 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * xatexit.c (_xexit_cleanup): Declare as extern; don't initialize. + Merging common and initialized variables need not be supported by + ANSI C compilers. + (xatexit): Initialize _xexit_cleanup if not already set. + * xexit.c: Comment fix. + +Wed Feb 16 01:15:36 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * xmalloc.c: Don't declare xexit; it's declared in libiberty.h. + (xrealloc): If oldmem is NULL, allocate with malloc, rather than + assuming that realloc works correctly. + +Tue Feb 15 09:26:16 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * concat.c, ieee-float.c: Replace inclusion of + with explicit function declarations, as recommended by Ian Taylor. + +Sat Feb 12 10:31:11 1994 David J. Mackenzie (djm@rtl.cygnus.com) + + * xmalloc.c (xmalloc, xrealloc): Use PTR and size_t throughout. + (malloc, realloc): Declare. + +Thu Feb 10 17:08:19 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * argv.c, basename.c: Include ansidecl.h and libiberty.h. + * concat.c, fdmatch.c, getruntime.c, spaces.c: Likewise. + * strerror.c, strsignal.c, xatexit.c, xexit.c: Likewise. + * xmalloc.c: Likewise. + * concat.c: Don't declare xmalloc. If __STDC__, use + macros, not macros. + * spaces.c (spaces): Make return type const. Don't crash if + malloc returns NULL. + * strerror.c (struct error_info): Make name and msg fields const. + (error_names): Make const. + (strerrno): Make const. + (strtoerrno): Make argument const. + * strsignal.c (struct signal_info): Make name and msg fields + const. + (signal_names, sys_siglist): Make const. + (strsignal, strsigno): Make const. + (strtosigno): Make argument const. + * xatexit.c: Declare parameter types. + * xmalloc.c (name): Make const. + (xmalloc_set_program_name): Make argument const. + * Makefile.in (INCDIR): Define. + (.c.o): Use $(INCDIR). + (dummy.o): Likewise. + (argv.o, basename.o): New targets; depend on libiberty.h. + (concat.o, fdmatch.o, getruntime.o, spaces.o): Likewise. + (strerror.o, strsignal.o, xatexit.o, xexit.o): Likewise. + (xmalloc.o): Likewise. + (cplus-dem.o): New target; depend on demangle.h. + (getopt.o, getopt1.o): New targets; depend on getopt.h. + (ieee-float.o): New target; depend on ieee-float.h. + (obstack.o): New target; depend on obstack.h. + +Tue Feb 8 05:29:08 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + Handle obstack_chunk_alloc returning NULL. This allows + obstacks to be used by libraries, without forcing them + to call exit or longjmp. + * obstack.c (_obstack_begin, _obstack_begin_1, _obstack_newchunk): + If CALL_CHUNKFUN returns NULL, set alloc_failed, else clear it. + (_obstack_begin, _obstack_begin_1): Return 1 if successful, 0 if not. + +Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * concat.c, ieee-float.c: Include . + +Sun Feb 6 21:28:46 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * xmalloc.c (xmalloc_set_program_name): New function. + (xmalloc, xrealloc): Include the name in the error message, if set. + + * Replace atexit.c with xatexit.c. + * Makefile.in (CFILES), functions.def: Change references. + +Sat Feb 5 14:02:32 1994 Stan Shebs (shebs@andros.cygnus.com) + + * getruntime.c (get_run_time): Use getrusage or times if + HAVE_GETRUSAGE or HAVE_TIMES are defined. + +Fri Feb 4 15:49:38 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * atexit.c: New file. + * Makefile.in (CFILES), functions.def: Add it. + * xexit.c: New file. + * Makefile.in (CFILES, REQUIRED_OFILES): Add it. + * xmalloc.c (xmalloc, xrealloc): Call xexit instead of exit. + Change request for 0 bytes into request for 1 byte. + +Wed Feb 2 11:36:49 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * xmalloc.c (xmalloc, xrealloc): Print size using %lu, and cast to + unsigned long, to avoid warnings. + +Fri Jan 28 17:49:06 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * dummy.c: Don't include time.h ever; always define clock_t as + "unsigned long". Until gcc/fixincludes ensures that clock_t + exists, __STDC__ isn't a sufficient test. And if clock() doesn't + exist, clock_t probably doesn't either. + +Mon Jan 24 11:52:31 1994 Stan Shebs (shebs@andros.cygnus.com) + + * clock.c, getruntime.c: New files. + * Makefile.in: Add to file lists. + * functions.def (clock): Add to list. + * dummy.c (time.h): Add if __STDC__. + (clock_t): #define as "unsigned long" if not __STDC__. + +Tue Jan 11 11:27:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * strtod.c: Declare atof. From edler@jan.ultra.nyu.edu (Jan + Edler). + +Tue Dec 28 14:17:30 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * Makefile.in (errors): Use CFLAGS as well as LDFLAGS when + linking. + +Fri Dec 17 12:26:07 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c (demangle_arm_pt): New function. Common code + for ARM template demangling. + * cplus-dem.c (demangle_class_name): Use demangle_arm_pt. + * cplus-dem.c (demangle_prefix): Likewise. + +Tue Nov 30 15:47:48 1993 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c (cplus_demangle_opname): Add CONST to please gcc. + +Sat Nov 27 11:05:50 1993 Fred Fish (fnf@cygnus.com) + + Merge changes from tom@basil.icce.rug.nl (Tom R.Hageman) + * strerror.c, strsignal.c: As a small space optimization, don't + include messages when they aren't actually used. + + Merge changes from takefive.co.at!joe (Josef Leherbauer) + * cplus-dem.c (demangle_prefix, demangle_function_name, + cplus_demangle_opname): Fixes for systems where cplus_marker + is something other than '$'. + +Fri Nov 26 13:51:11 1993 Per Bothner (bothner@kalessin.cygnus.com) + + * waitpid.c: Simple-minded approcimation to waitpid + using vanilla wait. + * functions.def, Makefile.in: Update accordingly, + +Thu Nov 18 18:01:15 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c(demangle_template): fix bug template instantiation + with value of user defined type. + +Wed Nov 17 18:30:21 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c(cplus_demangle_opname): add the subject new function + to support unified search of operator in class. + +Wed Nov 10 09:47:22 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + gcc -Wall lint: + * strtoul.c (strtoul): use "(digit = *s) != '\0'" not just + "digit = *s" as condition in while loop. + +Tue Nov 9 15:52:22 1993 Mark Eichin (eichin@cygnus.com) + + * Makefile.in: pass SHELL to recursive make + +Thu Nov 4 12:09:26 1993 Per Bothner (bothner@kalessin.cygnus.com) + + * vfprintf.c, vprintf.c, vsprintf.c: Make format arg + be (const char*), for ANSI (and gcc w/fixproto) consistency. + +Thu Nov 4 08:29:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * config.table: Make *-*-hiux* use mh-hpux. + +Fri Oct 22 07:53:15 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * config.table: Add * to end of all OS names. + +Tue Oct 19 17:12:01 1993 david d `zoo' zuhn (zoo@rtl.cygnus.com) + + * Makefile.in (lneeded-list): ensure that object file names are + not duplicated, as multiple instances of the same object file in + a library causes problems on some machines + +Mon Oct 18 21:59:28 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * strcasecmp.c, strncasecmp.c: Change u_char to unsigned char. + +Fri Oct 15 22:17:11 1993 david d `zoo' zuhn (zoo@rtl.cygnus.com) + + * strncasecmp.c: new file, implements strncasecmp + * strcasecmp.c: new file, implement strcasecmp + + * Makefile.in (CFILES): list these two new source files + + * functions.def: add strcasecmp and strncasecmp entries + +Fri Oct 15 14:53:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * strtoul.c (strtoul), strtol.c (strtol): Handle overflow + according to ANSI C. + +Thu Oct 14 16:34:19 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c: add support of ARM global constructor/destructor, + and 'G' for passing record or union in parameter. + +Wed Oct 13 13:36:19 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Fix comment to clarify that stuff in REQUIRED_OFILES + should not be in functions.def. + +Wed Oct 13 13:13:38 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * functions.def: Removed xmalloc. Stuff in REQUIRED_OFILES should + not be in functions.def. + +Mon Oct 4 18:26:39 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c: change globl constructor/destructor to proper name + +Tue Sep 28 18:11:07 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c: fix bug in constructor/destructor + +Tue Sep 28 16:20:49 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c: support both old and new _vt$... vtbl mangled names + +Fri Sep 24 19:07:16 1993 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c: Fix demangle_template prototype + +Fri Sep 24 17:32:55 1993 Kung Hsu (kung@cirdan.cygnus.com) + + * cplus-dem.c: fix template demangling + * cplus-dem.c: fix const type demangling + * cplus-dem.c: fix constructor/destructor, virtual table, + qualifier, global constructor/destructor demangling + +Wed Sep 1 23:13:11 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * strsignal.c, strerror.c: Use fully-bracketed initializer to + keep gcc -Wall happy. + +Fri Aug 27 10:30:09 1993 Jason Merrill (jason@deneb.cygnus.com) + + * cplus-dem.c (do_type): Add CONSTS to make gcc happy with last + patch. + +Fri Aug 27 11:24:54 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + Patch from Paul Flinders: + * cplus-dem.c (do_type): Deal with arrays. + +Tue Aug 24 14:23:50 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * cplus-dem.c (demangle_qualified: Deal with GNU format for more + than 9 classes. + +Wed Aug 18 19:50:29 1993 Jason Merrill (jason@deneb.cygnus.com) + + * Makefile.in (dummy.o): Redirect to /dev/null to avoid "variable + not initialized" warnings under HP/UX + +Sun Aug 15 20:42:40 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * strerror.c: Move include of stdio.h after sys_errlist #define. + Also remove NULL definition (stdio.h always defines NULL, so it + never did anything but clutter up the code). + +Sat Aug 14 14:21:49 1993 david d `zoo' zuhn (zoo@rtl.cygnus.com) + + * Makefile.in, functions.def: handle xmalloc.c + + * xmalloc.c: provide xmalloc and xrealloc functions + +Thu Aug 12 17:38:57 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * cplus-dem.c: Fix a comment. + +Sat Aug 7 13:56:35 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * getopt1.c: Declare const the way getopt.c does. + +Fri Aug 6 17:03:13 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * obstack.c, alloca.c: Update from FSF. + * getopt.c, getopt1.c: Update to current FSF version, which + doesn't use alloca. + +Tue Jul 27 14:03:57 1993 Brendan Kehoe (brendan@lisa.cygnus.com) + + * Makefile.in (demangle): Add the target with a message saying + where demangle went. + +Mon Jul 26 15:49:54 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Remove obsolete `demangle' target. + +Thu Jul 22 08:31:01 1993 Fred Fish (fnf@deneb.cygnus.com) + + * cplus-dem.c (arm_special): Apply patch from arg@lucid.com to + avoid infinite loop on vtbl symbols with disambiguating "junk" + tacked on the end. + +Mon Jul 19 14:10:37 1993 david d `zoo' zuhn (zoo@rtl.cygnus.com) + + * strsignal.c: work around some systems losing definitions of + sys_siglist + + * config/mh-lynxos: this system has a losing definition of + sys_siglist + + * config.table: use mh-lynxos for *-*-lynxos + +Mon Jul 19 17:08:52 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * config.table: Add support for HPPA BSD hosts. + + * config/mh-hpbsd: New file. + +Mon Jul 12 18:00:40 1993 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in (TAGS): make work when srcdir != objdir. + +Sun Jun 27 15:35:31 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * cplus-dem.c (main): Add long options, including --help and + --version. + (usage): New function from code in main. + +Tue Jun 22 11:37:38 1993 Per Bothner (bothner@deneb.cygnus.com) + + * config.table: New shell scipt, sourced by both ./configure,in + and ../xiberty/configure.in, to avoid maintainance lossages. + * configure.in and ../xiberty/configure.in: Use config.table. + + * configure.in: Don't use mh-aix for AIX 3.2, only for 3.1. + * configure.in: Map *-*-irix* (except irix4) to mh-sysv. + * ../xiberty/configure.in: Update from ./configure.in. + +Tue Jun 15 17:05:31 1993 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: remove parentdir support + +Wed May 26 12:59:09 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * cplus-dem.c (xrealloc): Match definition with prototype. + +Tue May 25 14:27:51 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * cplus-dem.c (demangle_prefix): Demangle cfront + local variables as an extension to ARM demangling. + +Fri May 21 09:53:57 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * ieee-float.c: Don't require pointers to double to be aligned. + +Tue May 18 17:12:10 1993 Fred Fish (fnf@cygnus.com) + + (merge changes from dlong@cse.ucsc.edu) + * cplus-dem.c (consume_count): Simplify. + * cplus-dem.c (arm_pt, demangle_class_name): New functions. + * cplus-dem.c (various): Calls to arm_pt, demangle_class_name. + + * cplus-dem.c (xmalloc, xrealloc, strstr): Make extern decls into + full prototypes. + * cplus-dem.c (free): Add prototype. + * cplus-dem.c (optable): Fully bracketize initializer. + +Fri May 14 17:13:05 1993 Per Bothner (bothner@cygnus.com) + + * cplus-dem.c: Whether initial underscores are stripped + depends on the external variable prepends_underscore + (which is generated by the binutils Makefile). + +Fri May 14 07:32:20 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * cplus-dem.c (mop_up, arm_special): Remove some unused variables. + +Tue May 4 20:31:59 1993 Fred Fish (fnf@cygnus.com) + + * cplus-dem.c (consume_count): Return zero if arg does not + start with digit, and don't consume any input. + +Tue May 4 08:10:28 1993 Jim Kingdon (kingdon@cygnus.com) + + * Makefile.in (demangle): Use ${srcdir} not $^. + + * strtod.c: New file, needed at least for BSD 4.3. + +Sun May 2 11:30:42 1993 Fred Fish (fnf@cygnus.com) + + * strsignal.c (sys_siglist): For ANSI compilations, type is + "const char *const". Also remove conditionalization on __STDC__ + since const is defined away for non-ANSI. + +Wed Apr 28 19:29:55 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * configure.in: Recognize *-*-hpux. + * config/mh-hpux: New file. + +Tue Apr 27 15:22:19 1993 Per Bothner (bothner@cygnus.com) + + * tmpnam.c: Added ANSI tmpnam() function. + * functions.def, Makefile.in: Update accordingly. + +Tue Apr 27 13:38:38 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * cplus-dem.c (demangle_function_name): Get the demangling of + stop__1A right. + +Fri Apr 16 23:48:24 1993 Jim Kingdon (kingdon at calvin) + + * cplus-dem.c: Declare strstr return type. + +Fri Mar 26 12:01:26 1993 Jim Kingdon (kingdon@cygnus.com) + + * strsignal.c: Add some AIX signals. + +Thu Mar 25 15:17:23 1993 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in (MAKEOVERRIDES): Define to be empty. + +Wed Mar 24 01:59:25 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: add installcheck & dvi targets + +Thu Mar 18 14:05:44 1993 Per Bothner (bothner@rtl.cygnus.com) + + * ieee-float.c: New file, moved from ../gdb (since it is + needed by ../opcode/m68k-dis.c). + +Tue Mar 2 17:47:31 1993 Fred Fish (fnf@cygnus.com) + + * cplus-dem.c: Replace all references to cfront with ARM. + +Fri Feb 26 00:17:07 1993 Per Bothner (bothner@rtl.cygnus.com) + + * cplus-dem.c: Fix main program (when compiled with -DMAIN) + to be more useful as a filter. + +Sat Feb 20 21:41:39 1993 Brendan Kehoe (brendan@lisa.cygnus.com) + + * Makefile.in (install_to_libdir, install_to_tooldir): Go into the + destination directory before running $(RANLIB), in case that + program tries to create a file in the current directory as part of + its work. + +Thu Feb 18 23:00:19 1993 John Gilmore (gnu@cygnus.com) + + * strsignal.c (sys_siglist): Remove yet another *%^&%&$# "const" + because BSD 4.4 lacks one. Isn't this fun? + +Thu Feb 18 11:24:25 1993 Fred Fish (fnf@cygnus.com) + + * cplus-dem.c (demangle_signature): Set func_done after + demangling a template. + * cplus-dem.c (demangle_template): Fix several small bugs + in demangling GNU style templates. + * cplus-dem.c (demangle_prefix): Fix for templates in GNU + style constructors. + * cplus-dem.c (gnu_special): Fix for templates in GNU style + static data members. + +Tue Feb 16 17:28:35 1993 Fred Fish (fnf@cygnus.com) + + * cplus-dem.c (demangle_signature): Modify to include type + modifiers like static and const in remembered types. + +Thu Feb 11 22:20:47 1993 Fred Fish (fnf@cygnus.com) + + * cplus-dem.c (demangled_qualified): Add new parameter that tells + whether to prepend or append the qualifiers. + * cplus-dem.c (string_prepends): Used now, remove #if 0. + * cplus-dem.c (demangle_signature): Call demangle_qualified + with prepending. + * cplus-dem.c (gnu_special): Recognize static data members that + use qualified names. + * cplus-dem.c (demangle_qualified): Accumulate qualifiers in a + temporary buffer and the prepend or append them to the result, + as specified by the new "append" flag. + * cplus-dem.c (do_type): Call demangled_qualified with + appending. + +Mon Dec 28 10:47:19 1992 Ken Raeburn (raeburn@cygnus.com) + + * strsignal.c (signal_table): Now const. + (init_signal_tables): Variable eip now points to const. + + * strerror.c (error_table): Now const. + (init_error_tables): Variable eip now points to const. + +Tue Dec 15 15:36:50 1992 Per Bothner (bothner@cygnus.com) + + * memchr.c (memchr): New (ANSI standard) function. + * Makefile.in, functions.def: Added memchr. + * Makefile.in (AR_FLAGS): Use rc instad of non-standard cq. + +Wed Dec 2 22:49:10 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * getopt.c: remove use of USG around , which never meant + anything anyway + + * config/mh-{aix,apollo68,ncr3000,sysv,sysv4}: removed definitions + of USG and USGr4 + +Thu Nov 19 03:09:33 1992 Brendan Kehoe (brendan@lisa.cygnus.com) + + * cplus-dem.c (demangle_fund_type): Recognize `w', a wide character; + it's now a type according to the ANSI X3J16 working paper; output + "wchar_t" for it. + (demangle_template): Accept `w' as an integral type. + (xmalloc, xrealloc): Use `char *', not `PTR'. Cast calls to their + counterparts malloc and realloc to `char *'. + (main): Exit with a 0 status. + * Makefile.in (demangle): Don't expect the user to define + DEMANGLE, instead force to be cplus-dem.c. Look in $(srcdir)/../include + for demangle.h. Pass it any HDEFINES or XTRAFLAGS. + +Wed Nov 18 18:56:20 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (AR_FLAGS): Avoid verbosity. + * config/mh-sysv4: Remove AR_FLAGS override, use INSTALL=cp, + replace USGr4 with HAVE_SYSCONF. + * config/mh-solaris: Remove; mh-sysv4 works now. + * getpagesize.c: Replace USGr4 with HAVE_SYSCONF. + * configure.in: Simplify host matching table, remove separate + solaris config file. + +Sun Nov 15 09:35:16 1992 Fred Fish (fnf@cygnus.com) + + * configure.in (i[34]86-*-solaris2*): Add, use mh-sysv4. + +Tue Nov 3 21:27:03 1992 Brendan Kehoe (brendan@cygnus.com) + + * cplus-dem.c (xmalloc, xrealloc): Add decls. + (remember_type): Don't cast xmalloc. + (string_need): Likewise; don't cast xrealloc either. + +Fri Oct 23 08:52:01 1992 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in, functions.defs, rename.c: added simple + implementation of rename, since some binutils programs use it. + +Thu Oct 15 15:18:22 1992 Per Bothner (bothner@cygnus.com) + + * strsignal.c: Add appropriate 'const' to sys_siglist + extern declaration (if __STDC__). (Needed for Linux.) + * strsignal.c (strsignal): Add cast to remove const-ness. + +Fri Oct 9 03:22:55 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (needed.awk, needed2.awk): Remove erroneous \'s + before "'s, diagnosed by BSD 4.4 awk. + +Thu Oct 8 15:25:12 1992 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in: create config.h and needed-list through $(CONFIG_H) + and $(NEEDED_LIST), to give some hooks for xiberty. + +Thu Oct 1 23:31:42 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use cpu-vendor-triple instead of nested cases + +Wed Sep 30 11:26:59 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in, argv.c, basename.c, bcmp.c, bcopy.c, bzero.c, + concat.c, cplus-dem.c, fdmatch.c, getcwd.c, getopt.c, getopt1.c, + getpagesize.c, insque.c, memcmp.c, memcpy.c, memmove.c, memset.c, + obstack.c, sigsetmask.c, spaces.c, strchr.c, strerror.c, + strrchr.c, strsignal.c, strstr.c, vfork.c, vsprintf.c: + Convert from using GPL to LGPL. + +Sat Sep 26 04:01:30 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (errors): Leave dummy.o and dummy around so that + we can see how the needed list was generated (it's sometimes wrong). + (mostlyclean): Remove them. + +Mon Sep 21 14:50:42 1992 Ian Lance Taylor (ian@cygnus.com) + + * getcwd.c: supply a default if MAXPATHLEN is not defined. + + * config/mh-irix4: set EXTRA_OFILES to alloca.o, from WRS. + +Wed Sep 9 12:41:48 1992 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in: Use XTRAFLAGS when compiling, so that xiberty works + when cross-compiling. + +Thu Sep 3 13:29:39 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * cplus-dem.c: (demangle_prefix): reduction in strength of strstr + as a time optimization. + + * cplus-dem.c (cplus_demangle): remove strpbrk test. Appears to + be more expensive than simply demangling. + + * cplus-dem.c (cplus_match): new function. + +Tue Sep 1 15:24:04 1992 Per Bothner (bothner@rtl.cygnus.com) + + * cplus-dem.c: #include , to define NULL. + Define current_demangling_style. + +Sun Aug 30 17:58:19 1992 Per Bothner (bothner@rtl.cygnus.com) + + * cplus-dem.c: New file, moved from ../gdb. + * cplus-dem.c (set_cplus_marker_for_demangling): New exported + function, to avoid compiling in target-dependency for CPLUS_MARKER. + * cplus-dem.c (cplus_demangle): Allow demangling style option + to be passed as a parameter, but using the global variable + current_demangling_style as a default. + * Makefile.in: Update for cplus-dem.c + +Sat Aug 29 10:44:09 1992 Fred Fish (fnf@cygnus.com) + + * obstack.c: Merge in comment changes from FSF version. Now + matches the FSF version exactly. + +Fri Aug 28 18:39:08 1992 John Gilmore (gnu@cygnus.com) + + * obstack.c (CALL_FREEFUN): Can't use ?: with void values (at + least on losing DECstations!); use if-then-else instead. + +Wed Aug 19 14:40:34 1992 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in: always create installation directories. + +Mon Aug 10 17:33:40 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: clean up definition of CFILES, more comments + +Sat Aug 8 23:10:59 1992 Fred Fish (fnf@cygnus.com) + + * getopt.c (my_index): Make first arg const to match strchr, + which it sometimes is remapped to. + +Sat Aug 1 13:48:50 1992 Fred Fish (fnf@cygnus.com) + + * obstack.c (DEFAULT_ALIGNMENT): Update to match FSF version. + * obstack.c (_obstack_begin): Initialize use_extra_arg. + * obstack.c (_obstack_begin_1): New, from FSF version. + +Mon Jul 20 21:07:58 1992 Fred Fish (fnf@cygnus.com) + + * obstack.c (CALL_CHECKFUN, CALL_FREEFUN): Use use_extra_arg and + extra_arg. + * obstack.c (_obstack_begin): Remove area_id and flags arguments + (previously added for mmalloc support, interface has changed). + Also convert flags usage to use use_extra_arg and maybe_empty_object. + +Fri Jul 10 00:41:53 1992 Fred Fish (fnf@cygnus.com) + + * argv.c: Move expandargv inline and eliminate static variables. + Rewrite to always allocate in powers of two. Fix to return an + argv with a single null string arg if passed a null string. + +Fri Jul 3 20:27:29 1992 Fred Fish (fnf@cygnus.com) + + * random.c, sigsetmask.c, strerror.c, strsignal.c: Remove + "(void)" casts from function calls where the return value is + ignored, in accordance with GNU coding standards. + +Mon Jun 29 10:54:19 1992 Fred Fish (fnf at cygnus.com) + + * bcopy.c, strerror.c, strsignal.c: Lint. + +Thu Jun 25 09:18:41 1992 K. Richard Pixley (rich@rtl.cygnus.com) + + * getopt.c: merge changes from make. + +Thu Jun 25 04:43:22 1992 John Gilmore (gnu at cygnus.com) + + * alloca.c: Incorporate fixes from gdb/alloca.c. + FIXME: Eventually move gdb's alloca configuration files here, + and remove gdb/alloca.c and its Makefile.in support. + +Tue Jun 23 21:56:30 1992 Fred Fish (fnf@cygnus.com) + + * dummy.c: Define NOTHING to /*nothing*/, change return type + of main to int and return zero. + * functions.def: Supply NOTHING as the fourth arg to macros + that don't have an explicit arg, to satisfy picky preprocessors. + +Wed Jun 17 18:13:58 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in: Clean up *clean rules, as per standards.texi. + +Tue Jun 16 16:11:59 1992 K. Richard Pixley (rich@rtl.cygnus.com) + + * getopt.c, getopt1.c: merged largely gratuitous, mostly + whitespace diffs from other prep distributions. + +Mon Jun 15 12:25:46 1992 Fred Fish (fnf@cygnus.com) + + * config/mh-ncr3000 (INSTALL): Don't use /usr/ucb/install, + it is broken on ncr 3000's. + +Mon Jun 15 01:03:26 1992 John Gilmore (gnu at cygnus.com) + + * sigsetmask.c: Rewrite. Old one was very confused about its + arguments and result. New one can't do much, but at least knows + what it can't do, and it's good enough for GDB's use. + +Sun Jun 14 15:17:40 1992 Stu Grossman (grossman at cygnus.com) + + * functions.def: Use proper prototype for strtoul. + +Fri Jun 12 19:22:40 1992 John Gilmore (gnu at cygnus.com) + + * Makefile.in: Add random.c. + * config/mh-*: Use "true" rather than "echo >/dev/null" for ranlib. + * configure.in: update solaris2 config. + +Wed Jun 10 16:31:29 1992 Fred Fish (fnf@cygnus.com) + + * random.c: Add for random() and srandom(). + * functions.def: Add random + +Tue Jun 9 17:27:18 1992 Fred Fish (fnf@cygnus.com) + + * config/{mh-ncr3000, mh-sysv4}: Add definition for INSTALL + using /usr/ucb/install. + +Mon Jun 1 13:20:17 1992 Per Bothner (bothner@rtl.cygnus.com) + + * strerror.c: Kludge to guard against a conflict with + possible declaration of sys_errlist in errno.h. + +Sun May 31 15:07:47 1992 Mark Eichin (eichin at cygnus.com) + + * configure.in, config/mh-solaris: add solaris2 config support. + +Fri May 29 17:23:23 1992 Per Bothner (bothner@rtl.cygnus.com) + + * sigsetmask.c: #ifdef out sigsetmask if SIG_SETMASK + is not defined (should be defined in signal.h, says Posix.). + +Mon May 18 17:35:04 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.c: merged changes from make-3.62.11. + +Fri May 8 14:53:07 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.c: merged changes from bison-1.18. + +Tue May 5 11:51:40 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in: Don't have $(EXTRA_OFILES) depend on config.h, + since that introduces a circular dependency. + ($(EXTRA_OFILES) are used to build config.h.) + + * strtoul.c: Fixes to handle non-decimal bases better. + +Wed Apr 22 09:27:51 1992 Fred Fish (fnf@cygnus.com) + + * config/mh-ncr3000: Replace MINUS_G with CFLAGS. + * Makefile.dos: Finish MINUS_G eradication. + * Makefile.in (CFILES): Add strsignal.c. + * Makefile.in (REQUIRED_OFILES): Add strerror.o strsignal.o + * Makefile.in (needed-list): Split creation of errors file to + separate make target. + * Makefile.in (config.h, needed2.awk, errors): New targets. + * Makefile.in (clean): Split to multiple lines, add needed2.awk + and config.h. + * dummy.c (DEFFUNC, DEFVAR): Add defines and undefs. + * functions.def (strerror): Remove from optional list. + * functions.def (sys_nerr, sys_errlist, sys_siglist): DEFVAR's + * functions.def (strerror, psignal): DEFFUNC's + * strerror.c: Rewrite from scratch to use sys_errlist only if + available, add errno_max(), add strerrno(), add strtoerrno(), + add test driver. + * strsignal.c: New file, signal equivalent to strerror.c. + Uses sys_siglist if available, defines signo_max(), strsignal(), + strsigno(), strtosigno(), psignal(), and test driver. + +Mon Apr 20 20:49:32 1992 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in: do not print recursion line. + + * Makefile.in: allow CFLAGS to be passed in from command line. + Removed MINUS_G. Default CFLAGS to -g. + +Mon Apr 20 12:57:46 1992 Per Bothner (bothner@rtl.cygnus.com) + + * config/mh-aix: New. EXTRA_OFILES lists copysign.o, + so libg++ users don't have to be inconvenienced by a + libc.a bug (libc.a needs copysign, but doesn't define it!). + * configure.in: Use config/mh-aix. + * strtoul.c: Handle '-' as required by ANSI. + Clean up radix handling. + * strstr.c: Fix buggy algorithm. + * Makefile.in: Change so that ${EXTRA_OFILES} is + appended to needed-list (which is used by libg++). + +Fri Apr 10 22:51:41 1992 Fred Fish (fnf@cygnus.com) + + * configure.in: Recognize new ncr3000 config. + * config/mh-ncr3000: New config file. + +Wed Apr 1 23:31:43 1992 John Gilmore (gnu at cygnus.com) + + * argv.c, dummy.c: Lint. + +Tue Mar 31 18:46:44 1992 Fred Fish (fnf@cygnus.com) + + * config/mh-sysv4: New config file. + * configure.in (host_makefile_frag): Set to config/mh-sysv4 for + host_os == sysv4. + * getpagesize.c: For SVR4, use sysconf(_SC_PAGESIZE) to get + pagesize. + +Sun Mar 29 12:26:42 1992 John Gilmore (gnu at cygnus.com) + + * getopt.c: Lint. + +Fri Mar 27 08:32:55 1992 Fred Fish (fnf@cygnus.com) + + * functions.def (alloca): Fix return type and args to avoid + type clash with gcc's builtin alloca. + +Tue Mar 24 23:33:42 1992 K. Richard Pixley (rich@cygnus.com) + + * configure.in, config/mh-irix4: irix4 support. + + * Makefile.in, functions.def, alloca.c: added alloca. + +Tue Mar 24 17:34:46 1992 Stu Grossman (grossman at cygnus.com) + + * obstack.c (CALL_FREEFUN): Make it compile on DECstations. + +Thu Mar 19 13:57:42 1992 Fred Fish (fnf@cygnus.com) + + * argv.c: Fix various external function definitions to be + correct in an ANSI compilation environment. + +Sat Mar 14 17:28:17 1992 Fred Fish (fnf@cygnus.com) + + * obstack.c: Changes to support calling mmalloc functions, + which take an additional argument over malloc functions. + +Fri Mar 6 22:01:10 1992 K. Richard Pixley (rich@cygnus.com) + + * added check target. + +Thu Feb 27 22:19:39 1992 Per Bothner (bothner@cygnus.com) + + * argv.c: #include alloca-conf.h (needed by AIX). + +Wed Feb 26 18:04:40 1992 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in, configure.in: removed traces of namesubdir, + -subdirs, $(subdir), $(unsubdir), some rcs triggers. Forced + copyrights to '92, changed some from Cygnus to FSF. + +Sat Feb 22 01:09:21 1992 Stu Grossman (grossman at cygnus.com) + + * argv.c: Check in Fred's version which fixes problems with + alloca(). + +Fri Feb 7 21:46:08 1992 Stu Grossman (grossman at cygnus.com) + + * makefile.dos: Remove NUL to keep patch from failing. + +Thu Jan 30 22:48:41 1992 Stu Grossman (grossman at cygnus.com) + + * getopt.c (_getopt_internal): Fix usage of enum has_arg. + +Mon Jan 20 18:53:23 1992 Stu Grossman (grossman at cygnus.com) + + * getopt.c, getopt1.c, ../include/getopt.h: Get latest versions. + +Sat Jan 18 16:53:01 1992 Fred Fish (fnf at cygnus.com) + + * argv.c: New file to build and destroy standard argument + vectors from a command string. + + * Makefile.in: Add argv.c and argv.o to appropriate macros. + +Fri Dec 20 12:12:57 1991 Fred Fish (fnf at cygnus.com) + + * configure.in: Change svr4 references to sysv4. + + * rindex.c: Declare return type of externally used function + strrchr(). + +Thu Dec 19 18:35:03 1991 John Gilmore (gnu at cygnus.com) + + * Makefile.in: Remove "***" in normal output, since Make produces + this on errors, and it's convenient to search for. + +Tue Dec 17 23:21:30 1991 Per Bothner (bothner at cygnus.com) + + * memcmp.c, memcpy.c, memmove.c, memset.c, strchr.c, strrchr.c: + New ANSI functions. The old non-ANSI functions (such as bcopy) + should be avoided. + * bcopy.c: Fix to correctly handle overlapping regions. + * index.c, rindex.c: Re-write in terms of strchr() and strrchr(). + * functions.def: Add the new functions. + * functions.def: Add 4th parameter to DEF macro, + an ansidecl.h-style prototype. + * dummy.c: Use expanded DEF macro to create a dummy function + call, with correct parameter types. (This avoids some + complaints from gcc about predefined builtins.) + + Move the functionality of config/mh-default into Makefile.in. + This avoid duplication, and simplifies things slightly. + * Makefile.in: Tweak so we don't need config/mh-default. + * README: Update. + * configure.in: No longer need config/mh-default. + * config/mh-default: Deleted. + * config/mh-sysv: Remove lines copied from old mh-default. + +Tue Dec 17 05:46:46 1991 John Gilmore (gnu at cygnus.com) + + * fdmatch.c (fdmatch): Don't compare st_rdev, which is for + 'mknod' device numbers. + +Mon Dec 16 12:25:34 1991 Fred Fish (fnf at cygnus.com) + + * fdmatch.c, Makefile.in: Add new function that takes two + open file descriptors and returns nonzero if they refer to + the same file, zero otherwise. (used in gdb) + +Wed Dec 11 17:40:39 1991 Steve Chamberlain (sac at rtl.cygnus.com) + From DJ: + * msdos.c: stub functions for dos. + * makefile.dos, configdj.bat: new. + * getopt.c: Don't include alloca-conf.h in a GO32 world. + + +Tue Dec 10 04:14:49 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: infodir belongs in datadir. + +Fri Dec 6 23:26:45 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: remove spaces following hyphens because bsd make + can't cope. added standards.text support. install using + INSTALL_DATA. + + * configure.in: remove commontargets as it is no longer a + recognized hook. + +Thu Dec 5 22:46:46 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: idestdir and ddestdir go away. Added copyrights + and shift gpl to v2. Added ChangeLog if it didn't exist. docdir + and mandir now keyed off datadir by default. + +Fri Nov 22 19:15:29 1991 John Gilmore (gnu at cygnus.com) + + * Makefile.in: find-needed.awk does not fit in 14 chars. + + * Makefile.in: Suppress error checking when compiling the test + program, because Ultrix make/sh aborts there due to a bug. + +Fri Nov 22 12:23:17 1991 Per Bothner (bothner at cygnus.com) + + * Makefile.in: Re-did how EXTRA_OFILES is used to be more useful. + * README: Explained how the auto-configuration works, + and how to add new files and/or configurations. + +Fri Nov 22 09:45:23 1991 John Gilmore (gnu at cygnus.com) + + * strtoul.c: Avoid defining ULONG_MAX if already defined; + cast a const char * to char * for pedants. + + * getopt.c: Only define "const" after local include files get to, + and only if they haven't defined it. + +Thu Nov 21 16:58:53 1991 John Gilmore (gnu at cygnus.com) + + * getcwd.c (remove getwd.c): GNU code should call getcwd(). We + emulate it with getwd() if available. This avoids callers having + to find a MAXPATHLEN or PATH_MAX value from somewhere. + * Makefile.in, functions.def: getwd->getcwd. + * configure.in: Use generic case for every system. + * config/mh-{delta88,mach,rs6000,svr4}: Remove. + * config/mh-sysv: Use default handling, just add -DUSG. + +Thu Nov 14 10:58:05 1991 Per Bothner (bothner at cygnus.com) + + * Makefile.in, config/mh-default: Re-do make magic + so that for the default ("automatic") mode we only + compile the files we actually need. Do this using + a recursive make: The top-level generates the list + of needed files (loosely, the ones missing in libc), + and then passes that list to the recursive make. + * config/mh-mach: Remove obsolete STRERROR-{C,O} macros. + +Tue Nov 12 19:10:57 1991 John Gilmore (gnu at cygnus.com) + + RS/6000 host support (grumble). + + * configure.in: Build alloca-conf.h file from alloca-norm.h + (everything else) or alloca-botch.h (rs/6000). + * Makefile.in: Include . on the include path. + * getopt.c: Use alloca-conf.h. + * alloca-norm.h: How to declare alloca on reasonable machines. + * alloca-botch.h: How to declare alloca on braindead machines. + +Tue Nov 12 09:21:48 1991 Fred Fish (fnf at cygnus.com) + + * concat.c : New file, like concat() in gdb but can take a + variable number of arguments rather than fixed at 3 args. For + now, client applications must supply an xmalloc(), which is a + front end function to malloc() that deals with out-of-memory + conditions. + + * Makefile.in: Add concat.c and concat.o to appropriate macros. + +Sat Nov 9 13:29:59 1991 Fred Fish (fnf at cygnus.com) + + * config/mh-svr4: Add sigsetmask to list of required functions. + +Sun Nov 3 11:57:56 1991 Per Bothner (bothner at cygnus.com) + + * vsprintf.c: New file. + * functions.def, Makefile.in: Add vsprintf. + +Sun Oct 27 16:31:22 1991 John Gilmore (gnu at cygnus.com) + + * configure.in, config/mh-rs6000: Add rs/6000 host support. + * Makefile.in: Compile with debug info. + +Fri Oct 25 17:01:12 1991 Per Bothner (bothner at cygnus.com) + + * Makefile.in, configure.in, and new files: dummy.c, functions.def, + config/mf-default: Added a default configuration mode, + which includes into libiberty.a functions that are "missing" in libc. + * strdup.c, vprintf.c, vfprintf.c: New files. + +Thu Oct 24 02:29:26 1991 Fred Fish (fnf at cygnus.com) + + * config/hmake-svr4: New file. + + * config/hmake-sysv: Add HOST_CFILES and HOST_OFILES. + + * basename.c, bcmp.c, bcopy.c, bzero.c, getpagesize.c getwd.c, + index.c, insque.c, rindex.c, spaces.c, strstr.c, vfork.c: New + files containing either portable C versions or emulations using + native library calls. + + * strerror.c: Add copyright, internal documentation, etc. + + * strtol.c: Replace hardwired hex constants with some more + portable macros. Remove illegal (according to gcc) cast. + + * strtoul.c: Replace hardwired hex constant with more portable + macro. + + * Makefile.in: Move TARGETLIB and CFLAGS where makefile fragments + can override them. Add new source and object file names to CFILES + and OFILES respectively. + + * configure.in: Add support for SVR4 makefile fragments. + +Tue Oct 22 19:00:23 1991 Steve Chamberlain (steve at cygnus.com) + + * Makefile.in: Move RANLIB, AR and AR_FLAGS to where they can be + over-ridden by config/hmake-* + * configure.in: added m88kcvs to sysv list + +Fri Oct 4 01:29:08 1991 John Gilmore (gnu at cygnus.com) + + * Makefile.in: Most hosts need strerror, but one or two don't, + and they override these definitions in the host-dependent makefile + fragment. + * config/hmake-mach: The odd man out on strerror -- it's supplied. + * strerror.c: New file. + + * strtol.c, strtoul.c: Add strtol to libiberty, since Mach lacks + it and bfd uses it. + * configure.in, Makefile.in, config/hmake-mach: Only configure + strtol & strotoul in on Mach. + +Tue Sep 3 06:36:23 1991 John Gilmore (gnu at cygint.cygnus.com) + + * obstack.c: Merge with latest FSF version. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/libiberty/Makefile.in b/external/gpl3/gdb/dist/libiberty/Makefile.in new file mode 100644 index 000000000000..ef35453c0310 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/Makefile.in @@ -0,0 +1,1242 @@ +# Makefile for the libiberty library. +# Originally written by K. Richard Pixley . +# +# Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, +# 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 +# Free Software Foundation +# +# This file is part of the libiberty library. +# Libiberty is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# Libiberty is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with libiberty; see the file COPYING.LIB. If not, +# write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +# Boston, MA 02110-1301, USA. + +libiberty_topdir = @libiberty_topdir@ +srcdir = @srcdir@ + +prefix = @prefix@ + +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +includedir = @includedir@ +target_header_dir = @target_header_dir@ +objext = @OBJEXT@ + +SHELL = @SHELL@ + +# Multilib support variables. +MULTISRCTOP = +MULTIBUILDTOP = +MULTIDIRS = +MULTISUBDIR = +MULTIDO = true +MULTICLEAN = true + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ +mkinstalldirs = $(SHELL) $(libiberty_topdir)/mkinstalldirs + +# Some compilers can't handle cc -c blah.c -o foo/blah.o. +OUTPUT_OPTION = @OUTPUT_OPTION@ + +AR = @AR@ +AR_FLAGS = rc + +CC = @CC@ +CFLAGS = @CFLAGS@ +CPPFLAGS = @CPPFLAGS@ +RANLIB = @RANLIB@ +MAKEINFO = @MAKEINFO@ +PERL = @PERL@ + +PICFLAG = @PICFLAG@ + +MAKEOVERRIDES = + +TARGETLIB = ./libiberty.a +TESTLIB = ./testlib.a + +LIBOBJS = @LIBOBJS@ + +# A configuration can specify extra .o files that should be included, +# even if they are in libc. (Perhaps the libc version is buggy.) +EXTRA_OFILES = + +# Flags to pass to a recursive make. +FLAGS_TO_PASS = \ + "AR=$(AR)" \ + "AR_FLAGS=$(AR_FLAGS)" \ + "CC=$(CC)" \ + "CFLAGS=$(CFLAGS)" \ + "CPPFLAGS=$(CPPFLAGS)" \ + "DESTDIR=$(DESTDIR)" \ + "EXTRA_OFILES=$(EXTRA_OFILES)" \ + "HDEFINES=$(HDEFINES)" \ + "INSTALL=$(INSTALL)" \ + "INSTALL_DATA=$(INSTALL_DATA)" \ + "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \ + "LDFLAGS=$(LDFLAGS)" \ + "LOADLIBES=$(LOADLIBES)" \ + "RANLIB=$(RANLIB)" \ + "SHELL=$(SHELL)" \ + "prefix=$(prefix)" \ + "exec_prefix=$(exec_prefix)" \ + "libdir=$(libdir)" \ + "libsubdir=$(libsubdir)" \ + "tooldir=$(tooldir)" + +# Subdirectories to recurse into. We need to override this during cleaning +SUBDIRS = testsuite + +# FIXME: add @BUILD_INFO@ once we're sure it works for everyone. +all: stamp-picdir $(TARGETLIB) required-list all-subdir + @: $(MAKE) ; $(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=all + +.PHONY: check installcheck +check: check-subdir +installcheck: installcheck-subdir + +@host_makefile_frag@ + +INCDIR=$(srcdir)/$(MULTISRCTOP)../include + +COMPILE.c = $(CC) -c @DEFS@ $(CFLAGS) $(CPPFLAGS) -I. -I$(INCDIR) $(HDEFINES) @ac_libiberty_warn_cflags@ + +# Just to make sure we don't use a built-in rule with VPATH +.c.$(objext): + false + +# NOTE: If you add new files to the library, add them to this list +# (alphabetical), and add them to REQUIRED_OFILES, or +# CONFIGURED_OFILES and funcs in configure.ac. Also run "make maint-deps" +# to build the new rules. +CFILES = alloca.c argv.c asprintf.c atexit.c \ + basename.c bcmp.c bcopy.c bsearch.c bzero.c \ + calloc.c choose-temp.c clock.c concat.c cp-demangle.c \ + cp-demint.c cplus-dem.c crc32.c \ + dyn-string.c \ + fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \ + fnmatch.c fopen_unlocked.c \ + getcwd.c getopt.c getopt1.c getpagesize.c getpwd.c getruntime.c \ + gettimeofday.c \ + hashtab.c hex.c \ + index.c insque.c \ + lbasename.c \ + lrealpath.c \ + make-relative-prefix.c \ + make-temp-file.c md5.c memchr.c memcmp.c memcpy.c memmem.c \ + memmove.c mempcpy.c memset.c mkstemps.c \ + objalloc.c obstack.c \ + partition.c pexecute.c \ + pex-common.c pex-djgpp.c pex-msdos.c pex-one.c \ + pex-unix.c pex-win32.c \ + physmem.c putenv.c \ + random.c regex.c rename.c rindex.c \ + safe-ctype.c setenv.c setproctitle.c sha1.c sigsetmask.c \ + simple-object.c simple-object-coff.c simple-object-elf.c \ + simple-object-mach-o.c \ + snprintf.c sort.c \ + spaces.c splay-tree.c stpcpy.c stpncpy.c strcasecmp.c \ + strchr.c strdup.c strerror.c strncasecmp.c strncmp.c \ + strrchr.c strsignal.c strstr.c strtod.c strtol.c strtoul.c \ + strndup.c strverscmp.c \ + tmpnam.c \ + unlink-if-ordinary.c \ + vasprintf.c vfork.c vfprintf.c vprintf.c vsnprintf.c vsprintf.c \ + waitpid.c \ + xatexit.c xexit.c xmalloc.c xmemdup.c xstrdup.c xstrerror.c \ + xstrndup.c + +# These are always included in the library. The first four are listed +# first and by compile time to optimize parallel builds. +REQUIRED_OFILES = \ + ./regex.$(objext) ./cplus-dem.$(objext) ./cp-demangle.$(objext) \ + ./md5.$(objext) ./sha1.$(objext) ./alloca.$(objext) \ + ./argv.$(objext) \ + ./choose-temp.$(objext) ./concat.$(objext) \ + ./cp-demint.$(objext) ./crc32.$(objext) ./dyn-string.$(objext) \ + ./fdmatch.$(objext) ./fibheap.$(objext) \ + ./filename_cmp.$(objext) ./floatformat.$(objext) \ + ./fnmatch.$(objext) ./fopen_unlocked.$(objext) \ + ./getopt.$(objext) ./getopt1.$(objext) ./getpwd.$(objext) \ + ./getruntime.$(objext) ./hashtab.$(objext) ./hex.$(objext) \ + ./lbasename.$(objext) ./lrealpath.$(objext) \ + ./make-relative-prefix.$(objext) ./make-temp-file.$(objext) \ + ./objalloc.$(objext) \ + ./obstack.$(objext) \ + ./partition.$(objext) ./pexecute.$(objext) ./physmem.$(objext) \ + ./pex-common.$(objext) ./pex-one.$(objext) \ + ./@pexecute@.$(objext) \ + ./safe-ctype.$(objext) \ + ./simple-object.$(objext) ./simple-object-coff.$(objext) \ + ./simple-object-elf.$(objext) ./simple-object-mach-o.$(objext) \ + ./sort.$(objext) ./spaces.$(objext) \ + ./splay-tree.$(objext) ./strerror.$(objext) \ + ./strsignal.$(objext) ./unlink-if-ordinary.$(objext) \ + ./xatexit.$(objext) ./xexit.$(objext) ./xmalloc.$(objext) \ + ./xmemdup.$(objext) ./xstrdup.$(objext) ./xstrerror.$(objext) \ + ./xstrndup.$(objext) + +# These are all the objects that configure may add to the library via +# $funcs or EXTRA_OFILES. This list exists here only for "make +# maint-missing" and "make check". +CONFIGURED_OFILES = ./asprintf.$(objext) ./atexit.$(objext) \ + ./basename.$(objext) ./bcmp.$(objext) ./bcopy.$(objext) \ + ./bsearch.$(objext) ./bzero.$(objext) \ + ./calloc.$(objext) ./clock.$(objext) ./copysign.$(objext) \ + ./_doprnt.$(objext) \ + ./ffs.$(objext) \ + ./getcwd.$(objext) ./getpagesize.$(objext) \ + ./gettimeofday.$(objext) \ + ./index.$(objext) ./insque.$(objext) \ + ./memchr.$(objext) ./memcmp.$(objext) ./memcpy.$(objext) \ + ./memmem.$(objext) ./memmove.$(objext) \ + ./mempcpy.$(objext) ./memset.$(objext) ./mkstemps.$(objext) \ + ./pex-djgpp.$(objext) ./pex-msdos.$(objext) \ + ./pex-unix.$(objext) ./pex-win32.$(objext) \ + ./putenv.$(objext) \ + ./random.$(objext) ./rename.$(objext) ./rindex.$(objext) \ + ./setenv.$(objext) \ + ./setproctitle.$(objext) \ + ./sigsetmask.$(objext) ./snprintf.$(objext) \ + ./stpcpy.$(objext) ./stpncpy.$(objext) ./strcasecmp.$(objext) \ + ./strchr.$(objext) ./strdup.$(objext) ./strncasecmp.$(objext) \ + ./strncmp.$(objext) ./strndup.$(objext) ./strrchr.$(objext) \ + ./strstr.$(objext) ./strtod.$(objext) ./strtol.$(objext) \ + ./strtoul.$(objext) ./strverscmp.$(objext) \ + ./tmpnam.$(objext) \ + ./vasprintf.$(objext) ./vfork.$(objext) ./vfprintf.$(objext) \ + ./vprintf.$(objext) ./vsnprintf.$(objext) ./vsprintf.$(objext) \ + ./waitpid.$(objext) + +# These files are installed if the library has been configured to do so. +INSTALLED_HEADERS = \ + $(INCDIR)/ansidecl.h \ + $(INCDIR)/demangle.h \ + $(INCDIR)/dyn-string.h \ + $(INCDIR)/fibheap.h \ + $(INCDIR)/floatformat.h \ + $(INCDIR)/hashtab.h \ + $(INCDIR)/libiberty.h \ + $(INCDIR)/objalloc.h \ + $(INCDIR)/partition.h \ + $(INCDIR)/safe-ctype.h \ + $(INCDIR)/sort.h \ + $(INCDIR)/splay-tree.h + +$(TARGETLIB): $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS) + -rm -f $(TARGETLIB) pic/$(TARGETLIB) + $(AR) $(AR_FLAGS) $(TARGETLIB) \ + $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS) + $(RANLIB) $(TARGETLIB) + if [ x"$(PICFLAG)" != x ]; then \ + cd pic; \ + $(AR) $(AR_FLAGS) $(TARGETLIB) \ + $(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS); \ + $(RANLIB) $(TARGETLIB); \ + cd ..; \ + else true; fi + +$(TESTLIB): $(REQUIRED_OFILES) $(CONFIGURED_OFILES) + -rm -f $(TESTLIB) + $(AR) $(AR_FLAGS) $(TESTLIB) \ + $(REQUIRED_OFILES) $(CONFIGURED_OFILES) + $(RANLIB) $(TESTLIB) + +info: libiberty.info info-subdir +install-info: install-info-subdir +clean-info: clean-info-subdir +dvi: libiberty.dvi dvi-subdir + +LIBIBERTY_PDFFILES = libiberty.pdf + +pdf: $(LIBIBERTY_PDFFILES) pdf-subdir + +.PHONY: install-pdf + +pdf__strip_dir = `echo $$p | sed -e 's|^.*/||'`; + +install-pdf: $(LIBIBERTY_PDFFILES) + @$(NORMAL_INSTALL) + test -z "$(pdfdir)" || $(mkinstalldirs) "$(DESTDIR)$(pdfdir)" + @list='$(LIBIBERTY_PDFFILES)'; for p in $$list; do \ + if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ + f=$(pdf__strip_dir) \ + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(pdfdir)/$$f'"; \ + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(pdfdir)/$$f"; \ + done + +# html, install-html targets +HTMLS = libiberty.html + +html: $(HTMLS) + +.PHONY: install-html install-html-am + +NORMAL_INSTALL = : +mkdir_p = mkdir -p -- + +html__strip_dir = `echo $$p | sed -e 's|^.*/||'`; + +install-html: install-html-am + +install-html-am: $(HTMLS) + @$(NORMAL_INSTALL) + test -z "$(htmldir)" || $(mkdir_p) "$(DESTDIR)$(htmldir)" + @list='$(HTMLS)'; for p in $$list; do \ + if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \ + f=$(html__strip_dir) \ + if test -d "$$d$$p"; then \ + echo " $(mkdir_p) '$(DESTDIR)$(htmldir)/$$f'"; \ + $(mkdir_p) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \ + echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \ + $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \ + else \ + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \ + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \ + fi; \ + done + +TEXISRC = \ + $(srcdir)/libiberty.texi \ + $(srcdir)/copying-lib.texi \ + $(srcdir)/obstacks.texi \ + $(srcdir)/functions.texi + +# Additional files that have texi snippets that need to be collected +# and sorted. Some are here because the sources are imported from +# elsewhere. Others represent headers in ../include. +TEXIFILES = fnmatch.txh pexecute.txh simple-object.txh + +libiberty.info : $(srcdir)/libiberty.texi $(TEXISRC) + $(MAKEINFO) -I$(srcdir) $(srcdir)/libiberty.texi + +libiberty.dvi : $(srcdir)/libiberty.texi $(TEXISRC) + texi2dvi $(srcdir)/libiberty.texi + +libiberty.pdf : $(srcdir)/libiberty.texi $(TEXISRC) + texi2pdf $(srcdir)/libiberty.texi + +libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC) + $(MAKEINFO) --no-split --html -I$(srcdir) -o $@ $< + +@MAINT@$(srcdir)/functions.texi : stamp-functions +@MAINT@ @true + +@MAINT@stamp-functions : $(CFILES:%=$(srcdir)/%) $(TEXIFILES:%=$(srcdir)/%) $(srcdir)/gather-docs Makefile +@MAINT@@HAVE_PERL@ $(PERL) $(srcdir)/gather-docs $(srcdir) $(srcdir)/functions.texi $(CFILES) $(TEXIFILES) +@MAINT@ echo stamp > stamp-functions + +INSTALL_DEST = @INSTALL_DEST@ +install: install_to_$(INSTALL_DEST) install-subdir +install-strip: install + +.PHONY: install install-strip + +# This is tricky. Even though CC in the Makefile contains +# multilib-specific flags, it's overridden by FLAGS_TO_PASS from the +# default multilib, so we have to take CFLAGS into account as well, +# since it will be passed the multilib flags. +MULTIOSDIR = `$(CC) $(CFLAGS) -print-multi-os-directory` +install_to_libdir: all + ${mkinstalldirs} $(DESTDIR)$(libdir)/$(MULTIOSDIR) + $(INSTALL_DATA) $(TARGETLIB) $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB)n + ( cd $(DESTDIR)$(libdir)/$(MULTIOSDIR) ; chmod 644 $(TARGETLIB)n ;$(RANLIB) $(TARGETLIB)n ) + mv -f $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB)n $(DESTDIR)$(libdir)/$(MULTIOSDIR)/$(TARGETLIB) + if test -n "${target_header_dir}"; then \ + case "${target_header_dir}" in \ + /*) thd=${target_header_dir};; \ + *) thd=${includedir}/${target_header_dir};; \ + esac; \ + ${mkinstalldirs} $(DESTDIR)$${thd}; \ + for h in ${INSTALLED_HEADERS}; do \ + ${INSTALL_DATA} $$h $(DESTDIR)$${thd}; \ + done; \ + fi + @$(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=install + +install_to_tooldir: all + ${mkinstalldirs} $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR) + $(INSTALL_DATA) $(TARGETLIB) $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB)n + ( cd $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR) ; chmod 644 $(TARGETLIB)n; $(RANLIB) $(TARGETLIB)n ) + mv -f $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB)n $(DESTDIR)$(tooldir)/lib/$(MULTIOSDIR)/$(TARGETLIB) + @$(MULTIDO) $(FLAGS_TO_PASS) multi-do DO=install + +# required-list was used when building a shared bfd/opcodes/libiberty +# library. I don't know if it used by anything currently. +required-list: Makefile + echo $(REQUIRED_OFILES) > required-list + +stamp-picdir: + if [ x"$(PICFLAG)" != x ] && [ ! -d pic ]; then \ + mkdir pic; \ + else true; fi + touch stamp-picdir + +.PHONY: all etags tags ls clean stage1 stage2 + +etags tags: TAGS etags-subdir + +TAGS: $(CFILES) + etags `for i in $(CFILES); do echo $(srcdir)/$$i ; done` + +# The standalone demangler (c++filt) has been moved to binutils. +# But make this target work anyway for demangler hacking. +demangle: $(ALL) $(srcdir)/cp-demangle.c + @echo "The standalone demangler, now named c++filt, is now" + @echo "a part of binutils." + $(CC) @DEFS@ $(CFLAGS) $(CPPFLAGS) -I. -I$(INCDIR) $(HDEFINES) \ + $(srcdir)/cp-demangle.c -DSTANDALONE_DEMANGLER $(TARGETLIB) -o $@ + +ls: + @echo Makefile $(CFILES) + +# Various targets for maintainers. + +maint-missing : + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) missing $(CFILES) $(REQUIRED_OFILES) $(CONFIGURED_OFILES) + +maint-buildall : $(REQUIRED_OFILES) $(CONFIGURED_OFILES) + @true + +maint-undoc : $(srcdir)/functions.texi + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) undoc + +maint-deps : + @$(PERL) $(srcdir)/maint-tool -s $(srcdir) deps $(INCDIR) + +# Need to deal with profiled libraries, too. + +# Cleaning has to be done carefully to ensure that we don't clean our SUBDIRS +# multiple times, hence our explicit recursion with an empty SUBDIRS. +mostlyclean: mostlyclean-subdir + -rm -rf *.$(objext) pic core errs \#* *.E a.out + -rm -f errors dummy config.h stamp-* + -rm -f $(CONFIG_H) stamp-picdir + -rm -f libiberty.aux libiberty.cp libiberty.cps libiberty.fn libiberty.ky + -rm -f libiberty.log libiberty.tmp libiberty.tps libiberty.pg + -rm -f libiberty.pgs libiberty.toc libiberty.tp libiberty.tpl libiberty.vr + -rm -f libtexi.stamp + @$(MULTICLEAN) multi-clean DO=mostlyclean +clean: clean-subdir + $(MAKE) SUBDIRS="" mostlyclean + -rm -f *.a required-list tmpmulti.out + -rm -f libiberty.dvi libiberty.pdf libiberty.info* libiberty.html + @$(MULTICLEAN) multi-clean DO=clean +distclean: distclean-subdir + $(MAKE) SUBDIRS="" clean + @$(MULTICLEAN) multi-clean DO=distclean + -rm -f *~ Makefile config.cache config.status xhost-mkfrag TAGS multilib.out + -rm -f config.log + -rmdir testsuite 2>/dev/null +maintainer-clean realclean: maintainer-clean-subdir + $(MAKE) SUBDIRS="" distclean + +force: + +Makefile: $(srcdir)/Makefile.in config.status + CONFIG_FILES=Makefile CONFIG_HEADERS= $(SHELL) ./config.status + +# Depending on Makefile makes sure that config.status has been re-run +# if needed. This prevents problems with parallel builds. +config.h: stamp-h ; @true +stamp-h: $(srcdir)/config.in config.status Makefile + CONFIG_FILES= CONFIG_HEADERS=config.h:$(srcdir)/config.in $(SHELL) ./config.status + +config.status: $(srcdir)/configure + $(SHELL) ./config.status --recheck + +AUTOCONF = autoconf +configure_deps = $(srcdir)/aclocal.m4 \ + $(srcdir)/../config/acx.m4 \ + $(srcdir)/../config/no-executables.m4 \ + $(srcdir)/../config/override.m4 \ + $(srcdir)/../config/warnings.m4 \ + +$(srcdir)/configure: @MAINT@ $(srcdir)/configure.ac $(configure_deps) + cd $(srcdir) && $(AUTOCONF) + +# Depending on config.h makes sure that config.status has been re-run +# if needed. This prevents problems with parallel builds, in case +# subdirectories need to run config.status also. +all-subdir check-subdir installcheck-subdir info-subdir \ +install-info-subdir clean-info-subdir dvi-subdir pdf-subdir install-subdir \ +etags-subdir mostlyclean-subdir clean-subdir distclean-subdir \ +maintainer-clean-subdir: config.h + @subdirs='$(SUBDIRS)'; \ + target=`echo $@ | sed -e 's/-subdir//'`; \ + for dir in $$subdirs ; do \ + cd $$dir && $(MAKE) $(FLAGS_TO_PASS) $$target; \ + done + +$(REQUIRED_OFILES) $(EXTRA_OFILES) $(LIBOBJS): stamp-picdir +$(CONFIGURED_OFILES): stamp-picdir + +# Don't export variables to the environment, in order to not confuse +# configure. +.NOEXPORT: + +# The dependencies in the remainder of this file are automatically +# generated by "make maint-deps". Manual edits will be lost. + +./_doprnt.$(objext): $(srcdir)/_doprnt.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/_doprnt.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/_doprnt.c $(OUTPUT_OPTION) + +./alloca.$(objext): $(srcdir)/alloca.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/alloca.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/alloca.c $(OUTPUT_OPTION) + +./argv.$(objext): $(srcdir)/argv.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/argv.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/argv.c $(OUTPUT_OPTION) + +./asprintf.$(objext): $(srcdir)/asprintf.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/asprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/asprintf.c $(OUTPUT_OPTION) + +./atexit.$(objext): $(srcdir)/atexit.c config.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/atexit.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/atexit.c $(OUTPUT_OPTION) + +./basename.$(objext): $(srcdir)/basename.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/basename.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/basename.c $(OUTPUT_OPTION) + +./bcmp.$(objext): $(srcdir)/bcmp.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/bcmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/bcmp.c $(OUTPUT_OPTION) + +./bcopy.$(objext): $(srcdir)/bcopy.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/bcopy.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/bcopy.c $(OUTPUT_OPTION) + +./bsearch.$(objext): $(srcdir)/bsearch.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/bsearch.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/bsearch.c $(OUTPUT_OPTION) + +./bzero.$(objext): $(srcdir)/bzero.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/bzero.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/bzero.c $(OUTPUT_OPTION) + +./calloc.$(objext): $(srcdir)/calloc.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/calloc.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/calloc.c $(OUTPUT_OPTION) + +./choose-temp.$(objext): $(srcdir)/choose-temp.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/choose-temp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/choose-temp.c $(OUTPUT_OPTION) + +./clock.$(objext): $(srcdir)/clock.c config.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/clock.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/clock.c $(OUTPUT_OPTION) + +./concat.$(objext): $(srcdir)/concat.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/concat.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/concat.c $(OUTPUT_OPTION) + +./copysign.$(objext): $(srcdir)/copysign.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/copysign.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/copysign.c $(OUTPUT_OPTION) + +./cp-demangle.$(objext): $(srcdir)/cp-demangle.c config.h $(INCDIR)/ansidecl.h \ + $(srcdir)/cp-demangle.h $(INCDIR)/demangle.h \ + $(INCDIR)/dyn-string.h $(INCDIR)/getopt.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/cp-demangle.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/cp-demangle.c $(OUTPUT_OPTION) + +./cp-demint.$(objext): $(srcdir)/cp-demint.c config.h $(INCDIR)/ansidecl.h \ + $(srcdir)/cp-demangle.h $(INCDIR)/demangle.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/cp-demint.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/cp-demint.c $(OUTPUT_OPTION) + +./cplus-dem.$(objext): $(srcdir)/cplus-dem.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/demangle.h $(INCDIR)/libiberty.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/cplus-dem.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/cplus-dem.c $(OUTPUT_OPTION) + +./crc32.$(objext): $(srcdir)/crc32.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/crc32.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/crc32.c $(OUTPUT_OPTION) + +./dyn-string.$(objext): $(srcdir)/dyn-string.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dyn-string.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/dyn-string.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/dyn-string.c $(OUTPUT_OPTION) + +./fdmatch.$(objext): $(srcdir)/fdmatch.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/fdmatch.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/fdmatch.c $(OUTPUT_OPTION) + +./ffs.$(objext): $(srcdir)/ffs.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/ffs.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/ffs.c $(OUTPUT_OPTION) + +./fibheap.$(objext): $(srcdir)/fibheap.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/fibheap.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/fibheap.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/fibheap.c $(OUTPUT_OPTION) + +./filename_cmp.$(objext): $(srcdir)/filename_cmp.c config.h $(INCDIR)/filenames.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/filename_cmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/filename_cmp.c $(OUTPUT_OPTION) + +./floatformat.$(objext): $(srcdir)/floatformat.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/floatformat.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/floatformat.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/floatformat.c $(OUTPUT_OPTION) + +./fnmatch.$(objext): $(srcdir)/fnmatch.c config.h $(INCDIR)/fnmatch.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/fnmatch.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/fnmatch.c $(OUTPUT_OPTION) + +./fopen_unlocked.$(objext): $(srcdir)/fopen_unlocked.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/fopen_unlocked.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/fopen_unlocked.c $(OUTPUT_OPTION) + +./getcwd.$(objext): $(srcdir)/getcwd.c config.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getcwd.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getcwd.c $(OUTPUT_OPTION) + +./getopt.$(objext): $(srcdir)/getopt.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/getopt.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getopt.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getopt.c $(OUTPUT_OPTION) + +./getopt1.$(objext): $(srcdir)/getopt1.c config.h $(INCDIR)/getopt.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getopt1.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getopt1.c $(OUTPUT_OPTION) + +./getpagesize.$(objext): $(srcdir)/getpagesize.c config.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getpagesize.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getpagesize.c $(OUTPUT_OPTION) + +./getpwd.$(objext): $(srcdir)/getpwd.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getpwd.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getpwd.c $(OUTPUT_OPTION) + +./getruntime.$(objext): $(srcdir)/getruntime.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/getruntime.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/getruntime.c $(OUTPUT_OPTION) + +./gettimeofday.$(objext): $(srcdir)/gettimeofday.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/gettimeofday.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/gettimeofday.c $(OUTPUT_OPTION) + +./hashtab.$(objext): $(srcdir)/hashtab.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/hashtab.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/hashtab.c $(OUTPUT_OPTION) + +./hex.$(objext): $(srcdir)/hex.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/hex.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/hex.c $(OUTPUT_OPTION) + +./index.$(objext): $(srcdir)/index.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/index.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/index.c $(OUTPUT_OPTION) + +./insque.$(objext): $(srcdir)/insque.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/insque.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/insque.c $(OUTPUT_OPTION) + +./lbasename.$(objext): $(srcdir)/lbasename.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/lbasename.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/lbasename.c $(OUTPUT_OPTION) + +./lrealpath.$(objext): $(srcdir)/lrealpath.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/lrealpath.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/lrealpath.c $(OUTPUT_OPTION) + +./make-relative-prefix.$(objext): $(srcdir)/make-relative-prefix.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/make-relative-prefix.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/make-relative-prefix.c $(OUTPUT_OPTION) + +./make-temp-file.$(objext): $(srcdir)/make-temp-file.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/make-temp-file.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/make-temp-file.c $(OUTPUT_OPTION) + +./md5.$(objext): $(srcdir)/md5.c config.h $(INCDIR)/ansidecl.h $(INCDIR)/md5.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/md5.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/md5.c $(OUTPUT_OPTION) + +./memchr.$(objext): $(srcdir)/memchr.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memchr.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memchr.c $(OUTPUT_OPTION) + +./memcmp.$(objext): $(srcdir)/memcmp.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memcmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memcmp.c $(OUTPUT_OPTION) + +./memcpy.$(objext): $(srcdir)/memcpy.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memcpy.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memcpy.c $(OUTPUT_OPTION) + +./memmem.$(objext): $(srcdir)/memmem.c config.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memmem.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memmem.c $(OUTPUT_OPTION) + +./memmove.$(objext): $(srcdir)/memmove.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memmove.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memmove.c $(OUTPUT_OPTION) + +./mempcpy.$(objext): $(srcdir)/mempcpy.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/mempcpy.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/mempcpy.c $(OUTPUT_OPTION) + +./memset.$(objext): $(srcdir)/memset.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/memset.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/memset.c $(OUTPUT_OPTION) + +./mkstemps.$(objext): $(srcdir)/mkstemps.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/mkstemps.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/mkstemps.c $(OUTPUT_OPTION) + +./msdos.$(objext): $(srcdir)/msdos.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/msdos.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/msdos.c $(OUTPUT_OPTION) + +./objalloc.$(objext): $(srcdir)/objalloc.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/objalloc.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/objalloc.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/objalloc.c $(OUTPUT_OPTION) + +./obstack.$(objext): $(srcdir)/obstack.c config.h $(INCDIR)/obstack.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/obstack.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/obstack.c $(OUTPUT_OPTION) + +./partition.$(objext): $(srcdir)/partition.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/partition.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/partition.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/partition.c $(OUTPUT_OPTION) + +./pex-common.$(objext): $(srcdir)/pex-common.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-common.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-common.c $(OUTPUT_OPTION) + +./pex-djgpp.$(objext): $(srcdir)/pex-djgpp.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-djgpp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-djgpp.c $(OUTPUT_OPTION) + +./pex-msdos.$(objext): $(srcdir)/pex-msdos.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-msdos.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-msdos.c $(OUTPUT_OPTION) + +./pex-one.$(objext): $(srcdir)/pex-one.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-one.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-one.c $(OUTPUT_OPTION) + +./pex-unix.$(objext): $(srcdir)/pex-unix.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-unix.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-unix.c $(OUTPUT_OPTION) + +./pex-win32.$(objext): $(srcdir)/pex-win32.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(srcdir)/pex-common.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pex-win32.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pex-win32.c $(OUTPUT_OPTION) + +./pexecute.$(objext): $(srcdir)/pexecute.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/pexecute.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/pexecute.c $(OUTPUT_OPTION) + +./physmem.$(objext): $(srcdir)/physmem.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/physmem.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/physmem.c $(OUTPUT_OPTION) + +./putenv.$(objext): $(srcdir)/putenv.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/putenv.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/putenv.c $(OUTPUT_OPTION) + +./random.$(objext): $(srcdir)/random.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/random.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/random.c $(OUTPUT_OPTION) + +./regex.$(objext): $(srcdir)/regex.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/regex.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/regex.c $(OUTPUT_OPTION) + +./rename.$(objext): $(srcdir)/rename.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/rename.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/rename.c $(OUTPUT_OPTION) + +./rindex.$(objext): $(srcdir)/rindex.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/rindex.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/rindex.c $(OUTPUT_OPTION) + +./safe-ctype.$(objext): $(srcdir)/safe-ctype.c $(INCDIR)/ansidecl.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/safe-ctype.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/safe-ctype.c $(OUTPUT_OPTION) + +./setenv.$(objext): $(srcdir)/setenv.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/setenv.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/setenv.c $(OUTPUT_OPTION) + +./setproctitle.$(objext): $(srcdir)/setproctitle.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/setproctitle.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/setproctitle.c $(OUTPUT_OPTION) + +./sha1.$(objext): $(srcdir)/sha1.c config.h $(INCDIR)/ansidecl.h $(INCDIR)/sha1.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/sha1.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/sha1.c $(OUTPUT_OPTION) + +./sigsetmask.$(objext): $(srcdir)/sigsetmask.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/sigsetmask.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/sigsetmask.c $(OUTPUT_OPTION) + +./simple-object-coff.$(objext): $(srcdir)/simple-object-coff.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-coff.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/simple-object-coff.c $(OUTPUT_OPTION) + +./simple-object-elf.$(objext): $(srcdir)/simple-object-elf.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-elf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/simple-object-elf.c $(OUTPUT_OPTION) + +./simple-object-mach-o.$(objext): $(srcdir)/simple-object-mach-o.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object-mach-o.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/simple-object-mach-o.c $(OUTPUT_OPTION) + +./simple-object.$(objext): $(srcdir)/simple-object.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ + $(srcdir)/simple-object-common.h $(INCDIR)/simple-object.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/simple-object.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/simple-object.c $(OUTPUT_OPTION) + +./snprintf.$(objext): $(srcdir)/snprintf.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/snprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/snprintf.c $(OUTPUT_OPTION) + +./sort.$(objext): $(srcdir)/sort.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/sort.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/sort.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/sort.c $(OUTPUT_OPTION) + +./spaces.$(objext): $(srcdir)/spaces.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/spaces.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/spaces.c $(OUTPUT_OPTION) + +./splay-tree.$(objext): $(srcdir)/splay-tree.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/splay-tree.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/splay-tree.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/splay-tree.c $(OUTPUT_OPTION) + +./stpcpy.$(objext): $(srcdir)/stpcpy.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/stpcpy.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/stpcpy.c $(OUTPUT_OPTION) + +./stpncpy.$(objext): $(srcdir)/stpncpy.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/stpncpy.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/stpncpy.c $(OUTPUT_OPTION) + +./strcasecmp.$(objext): $(srcdir)/strcasecmp.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strcasecmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strcasecmp.c $(OUTPUT_OPTION) + +./strchr.$(objext): $(srcdir)/strchr.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strchr.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strchr.c $(OUTPUT_OPTION) + +./strdup.$(objext): $(srcdir)/strdup.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strdup.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strdup.c $(OUTPUT_OPTION) + +./strerror.$(objext): $(srcdir)/strerror.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strerror.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strerror.c $(OUTPUT_OPTION) + +./strncasecmp.$(objext): $(srcdir)/strncasecmp.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strncasecmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strncasecmp.c $(OUTPUT_OPTION) + +./strncmp.$(objext): $(srcdir)/strncmp.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strncmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strncmp.c $(OUTPUT_OPTION) + +./strndup.$(objext): $(srcdir)/strndup.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strndup.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strndup.c $(OUTPUT_OPTION) + +./strrchr.$(objext): $(srcdir)/strrchr.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strrchr.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strrchr.c $(OUTPUT_OPTION) + +./strsignal.$(objext): $(srcdir)/strsignal.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strsignal.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strsignal.c $(OUTPUT_OPTION) + +./strstr.$(objext): $(srcdir)/strstr.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strstr.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strstr.c $(OUTPUT_OPTION) + +./strtod.$(objext): $(srcdir)/strtod.c $(INCDIR)/ansidecl.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtod.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strtod.c $(OUTPUT_OPTION) + +./strtol.$(objext): $(srcdir)/strtol.c config.h $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtol.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strtol.c $(OUTPUT_OPTION) + +./strtoul.$(objext): $(srcdir)/strtoul.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strtoul.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strtoul.c $(OUTPUT_OPTION) + +./strverscmp.$(objext): $(srcdir)/strverscmp.c $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/strverscmp.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/strverscmp.c $(OUTPUT_OPTION) + +./tmpnam.$(objext): $(srcdir)/tmpnam.c + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/tmpnam.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/tmpnam.c $(OUTPUT_OPTION) + +./unlink-if-ordinary.$(objext): $(srcdir)/unlink-if-ordinary.c config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/unlink-if-ordinary.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/unlink-if-ordinary.c $(OUTPUT_OPTION) + +./vasprintf.$(objext): $(srcdir)/vasprintf.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vasprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vasprintf.c $(OUTPUT_OPTION) + +./vfork.$(objext): $(srcdir)/vfork.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vfork.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vfork.c $(OUTPUT_OPTION) + +./vfprintf.$(objext): $(srcdir)/vfprintf.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vfprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vfprintf.c $(OUTPUT_OPTION) + +./vprintf.$(objext): $(srcdir)/vprintf.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vprintf.c $(OUTPUT_OPTION) + +./vsnprintf.$(objext): $(srcdir)/vsnprintf.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vsnprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vsnprintf.c $(OUTPUT_OPTION) + +./vsprintf.$(objext): $(srcdir)/vsprintf.c $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/vsprintf.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/vsprintf.c $(OUTPUT_OPTION) + +./waitpid.$(objext): $(srcdir)/waitpid.c config.h $(INCDIR)/ansidecl.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/waitpid.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/waitpid.c $(OUTPUT_OPTION) + +./xatexit.$(objext): $(srcdir)/xatexit.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xatexit.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xatexit.c $(OUTPUT_OPTION) + +./xexit.$(objext): $(srcdir)/xexit.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xexit.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xexit.c $(OUTPUT_OPTION) + +./xmalloc.$(objext): $(srcdir)/xmalloc.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xmalloc.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xmalloc.c $(OUTPUT_OPTION) + +./xmemdup.$(objext): $(srcdir)/xmemdup.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xmemdup.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xmemdup.c $(OUTPUT_OPTION) + +./xstrdup.$(objext): $(srcdir)/xstrdup.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrdup.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xstrdup.c $(OUTPUT_OPTION) + +./xstrerror.$(objext): $(srcdir)/xstrerror.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrerror.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xstrerror.c $(OUTPUT_OPTION) + +./xstrndup.$(objext): $(srcdir)/xstrndup.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/xstrndup.c -o pic/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/xstrndup.c $(OUTPUT_OPTION) + diff --git a/external/gpl3/gdb/dist/libiberty/README b/external/gpl3/gdb/dist/libiberty/README new file mode 100644 index 000000000000..9f1cc979e49b --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/README @@ -0,0 +1,72 @@ +This directory contains the -liberty library of free software. +It is a collection of subroutines used by various GNU programs. +Current members include: + + getopt -- get options from command line + obstack -- stacks of arbitrarily-sized objects + strerror -- error message strings corresponding to errno + strtol -- string-to-long conversion + strtoul -- string-to-unsigned-long conversion + +We expect many of the GNU subroutines that are floating around to +eventually arrive here. + +The library must be configured from the top source directory. Don't +try to run configure in this directory. Follow the configuration +instructions in ../README. + +Please report bugs to "gcc-bugs@gcc.gnu.org" and send fixes to +"gcc-patches@gcc.gnu.org". Thank you. + +ADDING A NEW FILE +================= + +There are two sets of files: Those that are "required" will be +included in the library for all configurations, while those +that are "optional" will be included in the library only if "needed." + +To add a new required file, edit Makefile.in to add the source file +name to CFILES and the object file to REQUIRED_OFILES. + +To add a new optional file, it must provide a single function, and the +name of the function must be the same as the name of the file. + + * Add the source file name to CFILES in Makefile.in and the object + file to CONFIGURED_OFILES. + + * Add the function to name to the funcs shell variable in + configure.ac. + + * Add the function to the AC_CHECK_FUNCS lists just after the + setting of the funcs shell variable. These AC_CHECK_FUNCS calls + are never executed; they are there to make autoheader work + better. + + * Consider the special cases of building libiberty; as of this + writing, the special cases are newlib and VxWorks. If a + particular special case provides the function, you do not need + to do anything. If it does not provide the function, add the + object file to LIBOBJS, and add the function name to the case + controlling whether to define HAVE_func. + +Finally, in the build directory of libiberty, configure with +"--enable-maintainer-mode", run "make maint-deps" to update +Makefile.in, and run 'make stamp-functions' to regenerate +functions.texi. + +The optional file you've added (e.g. getcwd.c) should compile and work +on all hosts where it is needed. It does not have to work or even +compile on hosts where it is not needed. + +ADDING A NEW CONFIGURATION +========================== + +On most hosts you should be able to use the scheme for automatically +figuring out which files are needed. In that case, you probably +don't need a special Makefile stub for that configuration. + +If the fully automatic scheme doesn't work, you may be able to get +by with defining EXTRA_OFILES in your Makefile stub. This is +a list of object file names that should be treated as required +for this configuration - they will be included in libiberty.a, +regardless of whatever might be in the C library. diff --git a/external/gpl3/gdb/dist/libiberty/_doprnt.c b/external/gpl3/gdb/dist/libiberty/_doprnt.c new file mode 100644 index 000000000000..ca97bc8c5d43 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/_doprnt.c @@ -0,0 +1,296 @@ +/* Provide a version of _doprnt in terms of fprintf. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Kaveh Ghazi (ghazi@caip.rutgers.edu) 3/29/98 + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "ansidecl.h" +#include "safe-ctype.h" + +#include +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +#undef _doprnt + +#ifdef HAVE__DOPRNT +#define TEST +#endif + +#ifdef TEST /* Make sure to use the internal one. */ +#define _doprnt my_doprnt +#endif + +#define COPY_VA_INT \ + do { \ + const int value = abs (va_arg (ap, int)); \ + char buf[32]; \ + ptr++; /* Go past the asterisk. */ \ + *sptr = '\0'; /* NULL terminate sptr. */ \ + sprintf(buf, "%d", value); \ + strcat(sptr, buf); \ + while (*sptr) sptr++; \ + } while (0) + +#define PRINT_CHAR(CHAR) \ + do { \ + putc(CHAR, stream); \ + ptr++; \ + total_printed++; \ + continue; \ + } while (0) + +#define PRINT_TYPE(TYPE) \ + do { \ + int result; \ + TYPE value = va_arg (ap, TYPE); \ + *sptr++ = *ptr++; /* Copy the type specifier. */ \ + *sptr = '\0'; /* NULL terminate sptr. */ \ + result = fprintf(stream, specifier, value); \ + if (result == -1) \ + return -1; \ + else \ + { \ + total_printed += result; \ + continue; \ + } \ + } while (0) + +int +_doprnt (const char *format, va_list ap, FILE *stream) +{ + const char * ptr = format; + char specifier[128]; + int total_printed = 0; + + while (*ptr != '\0') + { + if (*ptr != '%') /* While we have regular characters, print them. */ + PRINT_CHAR(*ptr); + else /* We got a format specifier! */ + { + char * sptr = specifier; + int wide_width = 0, short_width = 0; + + *sptr++ = *ptr++; /* Copy the % and move forward. */ + + while (strchr ("-+ #0", *ptr)) /* Move past flags. */ + *sptr++ = *ptr++; + + if (*ptr == '*') + COPY_VA_INT; + else + while (ISDIGIT(*ptr)) /* Handle explicit numeric value. */ + *sptr++ = *ptr++; + + if (*ptr == '.') + { + *sptr++ = *ptr++; /* Copy and go past the period. */ + if (*ptr == '*') + COPY_VA_INT; + else + while (ISDIGIT(*ptr)) /* Handle explicit numeric value. */ + *sptr++ = *ptr++; + } + while (strchr ("hlL", *ptr)) + { + switch (*ptr) + { + case 'h': + short_width = 1; + break; + case 'l': + wide_width++; + break; + case 'L': + wide_width = 2; + break; + default: + abort(); + } + *sptr++ = *ptr++; + } + + switch (*ptr) + { + case 'd': + case 'i': + case 'o': + case 'u': + case 'x': + case 'X': + case 'c': + { + /* Short values are promoted to int, so just copy it + as an int and trust the C library printf to cast it + to the right width. */ + if (short_width) + PRINT_TYPE(int); + else + { + switch (wide_width) + { + case 0: + PRINT_TYPE(int); + break; + case 1: + PRINT_TYPE(long); + break; + case 2: + default: +#if defined(__GNUC__) || defined(HAVE_LONG_LONG) + PRINT_TYPE(long long); +#else + PRINT_TYPE(long); /* Fake it and hope for the best. */ +#endif + break; + } /* End of switch (wide_width) */ + } /* End of else statement */ + } /* End of integer case */ + break; + case 'f': + case 'e': + case 'E': + case 'g': + case 'G': + { + if (wide_width == 0) + PRINT_TYPE(double); + else + { +#if defined(__GNUC__) || defined(HAVE_LONG_DOUBLE) + PRINT_TYPE(long double); +#else + PRINT_TYPE(double); /* Fake it and hope for the best. */ +#endif + } + } + break; + case 's': + PRINT_TYPE(char *); + break; + case 'p': + PRINT_TYPE(void *); + break; + case '%': + PRINT_CHAR('%'); + break; + default: + abort(); + } /* End of switch (*ptr) */ + } /* End of else statement */ + } + + return total_printed; +} + +#ifdef TEST + +#include +#ifndef M_PI +#define M_PI (3.1415926535897932385) +#endif + +#define RESULT(x) do \ +{ \ + int i = (x); \ + printf ("printed %d characters\n", i); \ + fflush(stdin); \ +} while (0) + +static int checkit (const char * format, ...) ATTRIBUTE_PRINTF_1; + +static int +checkit (const char* format, ...) +{ + int result; + VA_OPEN (args, format); + VA_FIXEDARG (args, char *, format); + + result = _doprnt (format, args, stdout); + VA_CLOSE (args); + + return result; +} + +int +main (void) +{ + RESULT(checkit ("<%d>\n", 0x12345678)); + RESULT(printf ("<%d>\n", 0x12345678)); + + RESULT(checkit ("<%200d>\n", 5)); + RESULT(printf ("<%200d>\n", 5)); + + RESULT(checkit ("<%.300d>\n", 6)); + RESULT(printf ("<%.300d>\n", 6)); + + RESULT(checkit ("<%100.150d>\n", 7)); + RESULT(printf ("<%100.150d>\n", 7)); + + RESULT(checkit ("<%s>\n", + "jjjjjjjjjiiiiiiiiiiiiiiioooooooooooooooooppppppppppppaa\n\ +777777777777777777333333333333366666666666622222222222777777777777733333")); + RESULT(printf ("<%s>\n", + "jjjjjjjjjiiiiiiiiiiiiiiioooooooooooooooooppppppppppppaa\n\ +777777777777777777333333333333366666666666622222222222777777777777733333")); + + RESULT(checkit ("<%f><%0+#f>%s%d%s>\n", + 1.0, 1.0, "foo", 77, "asdjffffffffffffffiiiiiiiiiiixxxxx")); + RESULT(printf ("<%f><%0+#f>%s%d%s>\n", + 1.0, 1.0, "foo", 77, "asdjffffffffffffffiiiiiiiiiiixxxxx")); + + RESULT(checkit ("<%4f><%.4f><%%><%4.4f>\n", M_PI, M_PI, M_PI)); + RESULT(printf ("<%4f><%.4f><%%><%4.4f>\n", M_PI, M_PI, M_PI)); + + RESULT(checkit ("<%*f><%.*f><%%><%*.*f>\n", 3, M_PI, 3, M_PI, 3, 3, M_PI)); + RESULT(printf ("<%*f><%.*f><%%><%*.*f>\n", 3, M_PI, 3, M_PI, 3, 3, M_PI)); + + RESULT(checkit ("<%d><%i><%o><%u><%x><%X><%c>\n", + 75, 75, 75, 75, 75, 75, 75)); + RESULT(printf ("<%d><%i><%o><%u><%x><%X><%c>\n", + 75, 75, 75, 75, 75, 75, 75)); + + RESULT(checkit ("<%d><%i><%o><%u><%x><%X><%c>\n", + 75, 75, 75, 75, 75, 75, 75)); + RESULT(printf ("<%d><%i><%o><%u><%x><%X><%c>\n", + 75, 75, 75, 75, 75, 75, 75)); + + RESULT(checkit ("Testing (hd) short: <%d><%ld><%hd><%hd><%d>\n", 123, (long)234, 345, 123456789, 456)); + RESULT(printf ("Testing (hd) short: <%d><%ld><%hd><%hd><%d>\n", 123, (long)234, 345, 123456789, 456)); + +#if defined(__GNUC__) || defined (HAVE_LONG_LONG) + RESULT(checkit ("Testing (lld) long long: <%d><%lld><%d>\n", 123, 234234234234234234LL, 345)); + RESULT(printf ("Testing (lld) long long: <%d><%lld><%d>\n", 123, 234234234234234234LL, 345)); + RESULT(checkit ("Testing (Ld) long long: <%d><%Ld><%d>\n", 123, 234234234234234234LL, 345)); + RESULT(printf ("Testing (Ld) long long: <%d><%Ld><%d>\n", 123, 234234234234234234LL, 345)); +#endif + +#if defined(__GNUC__) || defined (HAVE_LONG_DOUBLE) + RESULT(checkit ("Testing (Lf) long double: <%.20f><%.20Lf><%0+#.20f>\n", + 1.23456, 1.234567890123456789L, 1.23456)); + RESULT(printf ("Testing (Lf) long double: <%.20f><%.20Lf><%0+#.20f>\n", + 1.23456, 1.234567890123456789L, 1.23456)); +#endif + + return 0; +} +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/libiberty/aclocal.m4 b/external/gpl3/gdb/dist/libiberty/aclocal.m4 new file mode 100644 index 000000000000..f2091c9927e7 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/aclocal.m4 @@ -0,0 +1,174 @@ +sinclude(../config/acx.m4) +sinclude(../config/no-executables.m4) +sinclude(../config/override.m4) +sinclude(../config/warnings.m4) + +dnl See whether strncmp reads past the end of its string parameters. +dnl On some versions of SunOS4 at least, strncmp reads a word at a time +dnl but erroneously reads past the end of strings. This can cause +dnl a SEGV in some cases. +AC_DEFUN(libiberty_AC_FUNC_STRNCMP, +[AC_REQUIRE([AC_FUNC_MMAP]) +AC_CACHE_CHECK([for working strncmp], ac_cv_func_strncmp_works, +[AC_TRY_RUN([ +/* Test by Jim Wilson and Kaveh Ghazi. + Check whether strncmp reads past the end of its string parameters. */ +#include + +#ifdef HAVE_FCNTL_H +#include +#endif + +#ifdef HAVE_SYS_MMAN_H +#include +#endif + +#ifndef MAP_ANON +#ifdef MAP_ANONYMOUS +#define MAP_ANON MAP_ANONYMOUS +#else +#define MAP_ANON MAP_FILE +#endif +#endif + +#ifndef MAP_FILE +#define MAP_FILE 0 +#endif +#ifndef O_RDONLY +#define O_RDONLY 0 +#endif + +#define MAP_LEN 0x10000 + +main () +{ +#if defined(HAVE_MMAP) || defined(HAVE_MMAP_ANYWHERE) + char *p; + int dev_zero; + + dev_zero = open ("/dev/zero", O_RDONLY); + if (dev_zero < 0) + exit (1); + + p = (char *) mmap (0, MAP_LEN, PROT_READ|PROT_WRITE, + MAP_ANON|MAP_PRIVATE, dev_zero, 0); + if (p == (char *)-1) + p = (char *) mmap (0, MAP_LEN, PROT_READ|PROT_WRITE, + MAP_ANON|MAP_PRIVATE, -1, 0); + if (p == (char *)-1) + exit (2); + else + { + char *string = "__si_type_info"; + char *q = (char *) p + MAP_LEN - strlen (string) - 2; + char *r = (char *) p + 0xe; + + strcpy (q, string); + strcpy (r, string); + strncmp (r, q, 14); + } +#endif /* HAVE_MMAP || HAVE_MMAP_ANYWHERE */ + exit (0); +} +], ac_cv_func_strncmp_works=yes, ac_cv_func_strncmp_works=no, + ac_cv_func_strncmp_works=no) +rm -f core core.* *.core]) +if test $ac_cv_func_strncmp_works = no ; then + AC_LIBOBJ([strncmp]) +fi +]) + +dnl See if errno must be declared even when is included. +AC_DEFUN(libiberty_AC_DECLARE_ERRNO, +[AC_CACHE_CHECK(whether errno must be declared, libiberty_cv_declare_errno, +[AC_TRY_COMPILE( +[#include ], +[int x = errno;], +libiberty_cv_declare_errno=no, +libiberty_cv_declare_errno=yes)]) +if test $libiberty_cv_declare_errno = yes +then AC_DEFINE(NEED_DECLARATION_ERRNO, 1, + [Define if errno must be declared even when is included.]) +fi +]) + +dnl See whether we need a declaration for a function. +AC_DEFUN(libiberty_NEED_DECLARATION, +[AC_MSG_CHECKING([whether $1 must be declared]) +AC_CACHE_VAL(libiberty_cv_decl_needed_$1, +[AC_TRY_COMPILE([ +#include "confdefs.h" +#include +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif], +[char *(*pfn) = (char *(*)) $1], +libiberty_cv_decl_needed_$1=no, libiberty_cv_decl_needed_$1=yes)]) +AC_MSG_RESULT($libiberty_cv_decl_needed_$1) +if test $libiberty_cv_decl_needed_$1 = yes; then + AC_DEFINE([NEED_DECLARATION_]translit($1, [a-z], [A-Z]), 1, + [Define if $1 is not declared in system header files.]) +fi +])dnl + +# We always want a C version of alloca() compiled into libiberty, +# because native-compiler support for the real alloca is so !@#$% +# unreliable that GCC has decided to use it only when being compiled +# by GCC. This is the part of AC_FUNC_ALLOCA that calculates the +# information alloca.c needs. +AC_DEFUN(libiberty_AC_FUNC_C_ALLOCA, +[AC_CACHE_CHECK(whether alloca needs Cray hooks, ac_cv_os_cray, +[AC_EGREP_CPP(webecray, +[#if defined(CRAY) && ! defined(CRAY2) +webecray +#else +wenotbecray +#endif +], ac_cv_os_cray=yes, ac_cv_os_cray=no)]) +if test $ac_cv_os_cray = yes; then + for ac_func in _getb67 GETB67 getb67; do + AC_CHECK_FUNC($ac_func, + [AC_DEFINE_UNQUOTED(CRAY_STACKSEG_END, $ac_func, + [Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP + systems. This function is required for alloca.c support on those + systems.]) break]) + done +fi + +AC_CACHE_CHECK(stack direction for C alloca, ac_cv_c_stack_direction, +[AC_TRY_RUN([find_stack_direction () +{ + static char *addr = 0; + auto char dummy; + if (addr == 0) + { + addr = &dummy; + return find_stack_direction (); + } + else + return (&dummy > addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +}], + ac_cv_c_stack_direction=1, + ac_cv_c_stack_direction=-1, + ac_cv_c_stack_direction=0)]) +AC_DEFINE_UNQUOTED(STACK_DIRECTION, $ac_cv_c_stack_direction, + [Define if you know the direction of stack growth for your system; + otherwise it will be automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown]) +]) diff --git a/external/gpl3/gdb/dist/libiberty/alloca.c b/external/gpl3/gdb/dist/libiberty/alloca.c new file mode 100644 index 000000000000..9b2e9cb12b63 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/alloca.c @@ -0,0 +1,483 @@ +/* alloca.c -- allocate automatically reclaimed memory + (Mostly) portable public-domain implementation -- D A Gwyn + + This implementation of the PWB library alloca function, + which is used to allocate space off the run-time stack so + that it is automatically reclaimed upon procedure exit, + was inspired by discussions with J. Q. Johnson of Cornell. + J.Otto Tennant contributed the Cray support. + + There are some preprocessor constants that can + be defined when compiling for your specific system, for + improved efficiency; however, the defaults should be okay. + + The general concept of this implementation is to keep + track of all alloca-allocated blocks, and reclaim any + that are found to be deeper in the stack than the current + invocation. This heuristic does not reclaim storage as + soon as it becomes invalid, but it will do so eventually. + + As a special case, alloca(0) reclaims storage without + allocating any. It is a good idea to use alloca(0) in + your main control loop, etc. to force garbage collection. */ + +/* + +@deftypefn Replacement void* alloca (size_t @var{size}) + +This function allocates memory which will be automatically reclaimed +after the procedure exits. The @libib{} implementation does not free +the memory immediately but will do so eventually during subsequent +calls to this function. Memory is allocated using @code{xmalloc} under +normal circumstances. + +The header file @file{alloca-conf.h} can be used in conjunction with the +GNU Autoconf test @code{AC_FUNC_ALLOCA} to test for and properly make +available this function. The @code{AC_FUNC_ALLOCA} test requires that +client code use a block of preprocessor code to be safe (see the Autoconf +manual for more); this header incorporates that logic and more, including +the possibility of a GCC built-in function. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include + +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +/* These variables are used by the ASTRDUP implementation that relies + on C_alloca. */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +const char *libiberty_optr; +char *libiberty_nptr; +unsigned long libiberty_len; +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/* If your stack is a linked list of frames, you have to + provide an "address metric" ADDRESS_FUNCTION macro. */ + +#if defined (CRAY) && defined (CRAY_STACKSEG_END) +static long i00afunc (); +#define ADDRESS_FUNCTION(arg) (char *) i00afunc (&(arg)) +#else +#define ADDRESS_FUNCTION(arg) &(arg) +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/* Define STACK_DIRECTION if you know the direction of stack + growth for your system; otherwise it will be automatically + deduced at run-time. + + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ + +#ifndef STACK_DIRECTION +#define STACK_DIRECTION 0 /* Direction unknown. */ +#endif + +#if STACK_DIRECTION != 0 + +#define STACK_DIR STACK_DIRECTION /* Known at compile-time. */ + +#else /* STACK_DIRECTION == 0; need run-time code. */ + +static int stack_dir; /* 1 or -1 once known. */ +#define STACK_DIR stack_dir + +static void +find_stack_direction (void) +{ + static char *addr = NULL; /* Address of first `dummy', once known. */ + auto char dummy; /* To get stack address. */ + + if (addr == NULL) + { /* Initial entry. */ + addr = ADDRESS_FUNCTION (dummy); + + find_stack_direction (); /* Recurse once. */ + } + else + { + /* Second entry. */ + if (ADDRESS_FUNCTION (dummy) > addr) + stack_dir = 1; /* Stack grew upward. */ + else + stack_dir = -1; /* Stack grew downward. */ + } +} + +#endif /* STACK_DIRECTION == 0 */ + +/* An "alloca header" is used to: + (a) chain together all alloca'ed blocks; + (b) keep track of stack depth. + + It is very important that sizeof(header) agree with malloc + alignment chunk size. The following default should work okay. */ + +#ifndef ALIGN_SIZE +#define ALIGN_SIZE sizeof(double) +#endif + +typedef union hdr +{ + char align[ALIGN_SIZE]; /* To force sizeof(header). */ + struct + { + union hdr *next; /* For chaining headers. */ + char *deep; /* For stack depth measure. */ + } h; +} header; + +static header *last_alloca_header = NULL; /* -> last alloca header. */ + +/* Return a pointer to at least SIZE bytes of storage, + which will be automatically reclaimed upon exit from + the procedure that called alloca. Originally, this space + was supposed to be taken from the current stack frame of the + caller, but that method cannot be made to work for some + implementations of C, for example under Gould's UTX/32. */ + +/* @undocumented C_alloca */ + +PTR +C_alloca (size_t size) +{ + auto char probe; /* Probes stack depth: */ + register char *depth = ADDRESS_FUNCTION (probe); + +#if STACK_DIRECTION == 0 + if (STACK_DIR == 0) /* Unknown growth direction. */ + find_stack_direction (); +#endif + + /* Reclaim garbage, defined as all alloca'd storage that + was allocated from deeper in the stack than currently. */ + + { + register header *hp; /* Traverses linked list. */ + + for (hp = last_alloca_header; hp != NULL;) + if ((STACK_DIR > 0 && hp->h.deep > depth) + || (STACK_DIR < 0 && hp->h.deep < depth)) + { + register header *np = hp->h.next; + + free ((PTR) hp); /* Collect garbage. */ + + hp = np; /* -> next header. */ + } + else + break; /* Rest are not deeper. */ + + last_alloca_header = hp; /* -> last valid storage. */ + } + + if (size == 0) + return NULL; /* No allocation required. */ + + /* Allocate combined header + user data storage. */ + + { + register void *new_storage = XNEWVEC (char, sizeof (header) + size); + /* Address of header. */ + + if (new_storage == 0) + abort(); + + ((header *) new_storage)->h.next = last_alloca_header; + ((header *) new_storage)->h.deep = depth; + + last_alloca_header = (header *) new_storage; + + /* User storage begins just after header. */ + + return (PTR) ((char *) new_storage + sizeof (header)); + } +} + +#if defined (CRAY) && defined (CRAY_STACKSEG_END) + +#ifdef DEBUG_I00AFUNC +#include +#endif + +#ifndef CRAY_STACK +#define CRAY_STACK +#ifndef CRAY2 +/* Stack structures for CRAY-1, CRAY X-MP, and CRAY Y-MP */ +struct stack_control_header + { + long shgrow:32; /* Number of times stack has grown. */ + long shaseg:32; /* Size of increments to stack. */ + long shhwm:32; /* High water mark of stack. */ + long shsize:32; /* Current size of stack (all segments). */ + }; + +/* The stack segment linkage control information occurs at + the high-address end of a stack segment. (The stack + grows from low addresses to high addresses.) The initial + part of the stack segment linkage control information is + 0200 (octal) words. This provides for register storage + for the routine which overflows the stack. */ + +struct stack_segment_linkage + { + long ss[0200]; /* 0200 overflow words. */ + long sssize:32; /* Number of words in this segment. */ + long ssbase:32; /* Offset to stack base. */ + long:32; + long sspseg:32; /* Offset to linkage control of previous + segment of stack. */ + long:32; + long sstcpt:32; /* Pointer to task common address block. */ + long sscsnm; /* Private control structure number for + microtasking. */ + long ssusr1; /* Reserved for user. */ + long ssusr2; /* Reserved for user. */ + long sstpid; /* Process ID for pid based multi-tasking. */ + long ssgvup; /* Pointer to multitasking thread giveup. */ + long sscray[7]; /* Reserved for Cray Research. */ + long ssa0; + long ssa1; + long ssa2; + long ssa3; + long ssa4; + long ssa5; + long ssa6; + long ssa7; + long sss0; + long sss1; + long sss2; + long sss3; + long sss4; + long sss5; + long sss6; + long sss7; + }; + +#else /* CRAY2 */ +/* The following structure defines the vector of words + returned by the STKSTAT library routine. */ +struct stk_stat + { + long now; /* Current total stack size. */ + long maxc; /* Amount of contiguous space which would + be required to satisfy the maximum + stack demand to date. */ + long high_water; /* Stack high-water mark. */ + long overflows; /* Number of stack overflow ($STKOFEN) calls. */ + long hits; /* Number of internal buffer hits. */ + long extends; /* Number of block extensions. */ + long stko_mallocs; /* Block allocations by $STKOFEN. */ + long underflows; /* Number of stack underflow calls ($STKRETN). */ + long stko_free; /* Number of deallocations by $STKRETN. */ + long stkm_free; /* Number of deallocations by $STKMRET. */ + long segments; /* Current number of stack segments. */ + long maxs; /* Maximum number of stack segments so far. */ + long pad_size; /* Stack pad size. */ + long current_address; /* Current stack segment address. */ + long current_size; /* Current stack segment size. This + number is actually corrupted by STKSTAT to + include the fifteen word trailer area. */ + long initial_address; /* Address of initial segment. */ + long initial_size; /* Size of initial segment. */ + }; + +/* The following structure describes the data structure which trails + any stack segment. I think that the description in 'asdef' is + out of date. I only describe the parts that I am sure about. */ + +struct stk_trailer + { + long this_address; /* Address of this block. */ + long this_size; /* Size of this block (does not include + this trailer). */ + long unknown2; + long unknown3; + long link; /* Address of trailer block of previous + segment. */ + long unknown5; + long unknown6; + long unknown7; + long unknown8; + long unknown9; + long unknown10; + long unknown11; + long unknown12; + long unknown13; + long unknown14; + }; + +#endif /* CRAY2 */ +#endif /* not CRAY_STACK */ + +#ifdef CRAY2 +/* Determine a "stack measure" for an arbitrary ADDRESS. + I doubt that "lint" will like this much. */ + +static long +i00afunc (long *address) +{ + struct stk_stat status; + struct stk_trailer *trailer; + long *block, size; + long result = 0; + + /* We want to iterate through all of the segments. The first + step is to get the stack status structure. We could do this + more quickly and more directly, perhaps, by referencing the + $LM00 common block, but I know that this works. */ + + STKSTAT (&status); + + /* Set up the iteration. */ + + trailer = (struct stk_trailer *) (status.current_address + + status.current_size + - 15); + + /* There must be at least one stack segment. Therefore it is + a fatal error if "trailer" is null. */ + + if (trailer == 0) + abort (); + + /* Discard segments that do not contain our argument address. */ + + while (trailer != 0) + { + block = (long *) trailer->this_address; + size = trailer->this_size; + if (block == 0 || size == 0) + abort (); + trailer = (struct stk_trailer *) trailer->link; + if ((block <= address) && (address < (block + size))) + break; + } + + /* Set the result to the offset in this segment and add the sizes + of all predecessor segments. */ + + result = address - block; + + if (trailer == 0) + { + return result; + } + + do + { + if (trailer->this_size <= 0) + abort (); + result += trailer->this_size; + trailer = (struct stk_trailer *) trailer->link; + } + while (trailer != 0); + + /* We are done. Note that if you present a bogus address (one + not in any segment), you will get a different number back, formed + from subtracting the address of the first block. This is probably + not what you want. */ + + return (result); +} + +#else /* not CRAY2 */ +/* Stack address function for a CRAY-1, CRAY X-MP, or CRAY Y-MP. + Determine the number of the cell within the stack, + given the address of the cell. The purpose of this + routine is to linearize, in some sense, stack addresses + for alloca. */ + +static long +i00afunc (long address) +{ + long stkl = 0; + + long size, pseg, this_segment, stack; + long result = 0; + + struct stack_segment_linkage *ssptr; + + /* Register B67 contains the address of the end of the + current stack segment. If you (as a subprogram) store + your registers on the stack and find that you are past + the contents of B67, you have overflowed the segment. + + B67 also points to the stack segment linkage control + area, which is what we are really interested in. */ + + stkl = CRAY_STACKSEG_END (); + ssptr = (struct stack_segment_linkage *) stkl; + + /* If one subtracts 'size' from the end of the segment, + one has the address of the first word of the segment. + + If this is not the first segment, 'pseg' will be + nonzero. */ + + pseg = ssptr->sspseg; + size = ssptr->sssize; + + this_segment = stkl - size; + + /* It is possible that calling this routine itself caused + a stack overflow. Discard stack segments which do not + contain the target address. */ + + while (!(this_segment <= address && address <= stkl)) + { +#ifdef DEBUG_I00AFUNC + fprintf (stderr, "%011o %011o %011o\n", this_segment, address, stkl); +#endif + if (pseg == 0) + break; + stkl = stkl - pseg; + ssptr = (struct stack_segment_linkage *) stkl; + size = ssptr->sssize; + pseg = ssptr->sspseg; + this_segment = stkl - size; + } + + result = address - this_segment; + + /* If you subtract pseg from the current end of the stack, + you get the address of the previous stack segment's end. + This seems a little convoluted to me, but I'll bet you save + a cycle somewhere. */ + + while (pseg != 0) + { +#ifdef DEBUG_I00AFUNC + fprintf (stderr, "%011o %011o\n", pseg, size); +#endif + stkl = stkl - pseg; + ssptr = (struct stack_segment_linkage *) stkl; + size = ssptr->sssize; + pseg = ssptr->sspseg; + result += size; + } + return (result); +} + +#endif /* not CRAY2 */ +#endif /* CRAY */ diff --git a/external/gpl3/gdb/dist/libiberty/argv.c b/external/gpl3/gdb/dist/libiberty/argv.c new file mode 100644 index 000000000000..8476c8fda9e1 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/argv.c @@ -0,0 +1,544 @@ +/* Create and destroy argument vectors (argv's) + Copyright (C) 1992, 2001, 2010 Free Software Foundation, Inc. + Written by Fred Fish @ Cygnus Support + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + + +/* Create and destroy argument vectors. An argument vector is simply an + array of string pointers, terminated by a NULL pointer. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" + +/* Routines imported from standard C runtime libraries. */ + +#include +#include +#include +#include + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef EOS +#define EOS '\0' +#endif + +#define INITIAL_MAXARGC 8 /* Number of args + NULL in initial argv */ + + +/* + +@deftypefn Extension char** dupargv (char **@var{vector}) + +Duplicate an argument vector. Simply scans through @var{vector}, +duplicating each argument until the terminating @code{NULL} is found. +Returns a pointer to the argument vector if successful. Returns +@code{NULL} if there is insufficient memory to complete building the +argument vector. + +@end deftypefn + +*/ + +char ** +dupargv (char **argv) +{ + int argc; + char **copy; + + if (argv == NULL) + return NULL; + + /* the vector */ + for (argc = 0; argv[argc] != NULL; argc++); + copy = (char **) malloc ((argc + 1) * sizeof (char *)); + if (copy == NULL) + return NULL; + + /* the strings */ + for (argc = 0; argv[argc] != NULL; argc++) + { + int len = strlen (argv[argc]); + copy[argc] = (char *) malloc (len + 1); + if (copy[argc] == NULL) + { + freeargv (copy); + return NULL; + } + strcpy (copy[argc], argv[argc]); + } + copy[argc] = NULL; + return copy; +} + +/* + +@deftypefn Extension void freeargv (char **@var{vector}) + +Free an argument vector that was built using @code{buildargv}. Simply +scans through @var{vector}, freeing the memory for each argument until +the terminating @code{NULL} is found, and then frees @var{vector} +itself. + +@end deftypefn + +*/ + +void freeargv (char **vector) +{ + register char **scan; + + if (vector != NULL) + { + for (scan = vector; *scan != NULL; scan++) + { + free (*scan); + } + free (vector); + } +} + +static void +consume_whitespace (const char **input) +{ + while (ISSPACE (**input)) + { + (*input)++; + } +} + +static int +only_whitespace (const char* input) +{ + while (*input != EOS && ISSPACE (*input)) + input++; + + return (*input == EOS); +} + +/* + +@deftypefn Extension char** buildargv (char *@var{sp}) + +Given a pointer to a string, parse the string extracting fields +separated by whitespace and optionally enclosed within either single +or double quotes (which are stripped off), and build a vector of +pointers to copies of the string for each field. The input string +remains unchanged. The last element of the vector is followed by a +@code{NULL} element. + +All of the memory for the pointer array and copies of the string +is obtained from @code{malloc}. All of the memory can be returned to the +system with the single function call @code{freeargv}, which takes the +returned result of @code{buildargv}, as it's argument. + +Returns a pointer to the argument vector if successful. Returns +@code{NULL} if @var{sp} is @code{NULL} or if there is insufficient +memory to complete building the argument vector. + +If the input is a null string (as opposed to a @code{NULL} pointer), +then buildarg returns an argument vector that has one arg, a null +string. + +@end deftypefn + +The memory for the argv array is dynamically expanded as necessary. + +In order to provide a working buffer for extracting arguments into, +with appropriate stripping of quotes and translation of backslash +sequences, we allocate a working buffer at least as long as the input +string. This ensures that we always have enough space in which to +work, since the extracted arg is never larger than the input string. + +The argument vector is always kept terminated with a @code{NULL} arg +pointer, so it can be passed to @code{freeargv} at any time, or +returned, as appropriate. + +*/ + +char **buildargv (const char *input) +{ + char *arg; + char *copybuf; + int squote = 0; + int dquote = 0; + int bsquote = 0; + int argc = 0; + int maxargc = 0; + char **argv = NULL; + char **nargv; + + if (input != NULL) + { + copybuf = (char *) alloca (strlen (input) + 1); + /* Is a do{}while to always execute the loop once. Always return an + argv, even for null strings. See NOTES above, test case below. */ + do + { + /* Pick off argv[argc] */ + consume_whitespace (&input); + + if ((maxargc == 0) || (argc >= (maxargc - 1))) + { + /* argv needs initialization, or expansion */ + if (argv == NULL) + { + maxargc = INITIAL_MAXARGC; + nargv = (char **) malloc (maxargc * sizeof (char *)); + } + else + { + maxargc *= 2; + nargv = (char **) realloc (argv, maxargc * sizeof (char *)); + } + if (nargv == NULL) + { + if (argv != NULL) + { + freeargv (argv); + argv = NULL; + } + break; + } + argv = nargv; + argv[argc] = NULL; + } + /* Begin scanning arg */ + arg = copybuf; + while (*input != EOS) + { + if (ISSPACE (*input) && !squote && !dquote && !bsquote) + { + break; + } + else + { + if (bsquote) + { + bsquote = 0; + *arg++ = *input; + } + else if (*input == '\\') + { + bsquote = 1; + } + else if (squote) + { + if (*input == '\'') + { + squote = 0; + } + else + { + *arg++ = *input; + } + } + else if (dquote) + { + if (*input == '"') + { + dquote = 0; + } + else + { + *arg++ = *input; + } + } + else + { + if (*input == '\'') + { + squote = 1; + } + else if (*input == '"') + { + dquote = 1; + } + else + { + *arg++ = *input; + } + } + input++; + } + } + *arg = EOS; + argv[argc] = strdup (copybuf); + if (argv[argc] == NULL) + { + freeargv (argv); + argv = NULL; + break; + } + argc++; + argv[argc] = NULL; + + consume_whitespace (&input); + } + while (*input != EOS); + } + return (argv); +} + +/* + +@deftypefn Extension int writeargv (const char **@var{argv}, FILE *@var{file}) + +Write each member of ARGV, handling all necessary quoting, to the file +named by FILE, separated by whitespace. Return 0 on success, non-zero +if an error occurred while writing to FILE. + +@end deftypefn + +*/ + +int +writeargv (char **argv, FILE *f) +{ + int status = 0; + + if (f == NULL) + return 1; + + while (*argv != NULL) + { + const char *arg = *argv; + + while (*arg != EOS) + { + char c = *arg; + + if (ISSPACE(c) || c == '\\' || c == '\'' || c == '"') + if (EOF == fputc ('\\', f)) + { + status = 1; + goto done; + } + + if (EOF == fputc (c, f)) + { + status = 1; + goto done; + } + arg++; + } + + if (EOF == fputc ('\n', f)) + { + status = 1; + goto done; + } + argv++; + } + + done: + return status; +} + +/* + +@deftypefn Extension void expandargv (int *@var{argcp}, char ***@var{argvp}) + +The @var{argcp} and @code{argvp} arguments are pointers to the usual +@code{argc} and @code{argv} arguments to @code{main}. This function +looks for arguments that begin with the character @samp{@@}. Any such +arguments are interpreted as ``response files''. The contents of the +response file are interpreted as additional command line options. In +particular, the file is separated into whitespace-separated strings; +each such string is taken as a command-line option. The new options +are inserted in place of the option naming the response file, and +@code{*argcp} and @code{*argvp} will be updated. If the value of +@code{*argvp} is modified by this function, then the new value has +been dynamically allocated and can be deallocated by the caller with +@code{freeargv}. However, most callers will simply call +@code{expandargv} near the beginning of @code{main} and allow the +operating system to free the memory when the program exits. + +@end deftypefn + +*/ + +void +expandargv (int *argcp, char ***argvp) +{ + /* The argument we are currently processing. */ + int i = 0; + /* Non-zero if ***argvp has been dynamically allocated. */ + int argv_dynamic = 0; + /* Limit the number of response files that we parse in order + to prevent infinite recursion. */ + unsigned int iteration_limit = 2000; + /* Loop over the arguments, handling response files. We always skip + ARGVP[0], as that is the name of the program being run. */ + while (++i < *argcp) + { + /* The name of the response file. */ + const char *filename; + /* The response file. */ + FILE *f; + /* An upper bound on the number of characters in the response + file. */ + long pos; + /* The number of characters in the response file, when actually + read. */ + size_t len; + /* A dynamically allocated buffer used to hold options read from a + response file. */ + char *buffer; + /* Dynamically allocated storage for the options read from the + response file. */ + char **file_argv; + /* The number of options read from the response file, if any. */ + size_t file_argc; + /* We are only interested in options of the form "@file". */ + filename = (*argvp)[i]; + if (filename[0] != '@') + continue; + /* If we have iterated too many times then stop. */ + if (-- iteration_limit == 0) + { + fprintf (stderr, "%s: error: too many @-files encountered\n", (*argvp)[0]); + xexit (1); + } + /* Read the contents of the file. */ + f = fopen (++filename, "r"); + if (!f) + continue; + if (fseek (f, 0L, SEEK_END) == -1) + goto error; + pos = ftell (f); + if (pos == -1) + goto error; + if (fseek (f, 0L, SEEK_SET) == -1) + goto error; + buffer = (char *) xmalloc (pos * sizeof (char) + 1); + len = fread (buffer, sizeof (char), pos, f); + if (len != (size_t) pos + /* On Windows, fread may return a value smaller than POS, + due to CR/LF->CR translation when reading text files. + That does not in-and-of itself indicate failure. */ + && ferror (f)) + goto error; + /* Add a NUL terminator. */ + buffer[len] = '\0'; + /* If the file is empty or contains only whitespace, buildargv would + return a single empty argument. In this context we want no arguments, + instead. */ + if (only_whitespace (buffer)) + { + file_argv = (char **) xmalloc (sizeof (char *)); + file_argv[0] = NULL; + } + else + /* Parse the string. */ + file_argv = buildargv (buffer); + /* If *ARGVP is not already dynamically allocated, copy it. */ + if (!argv_dynamic) + { + *argvp = dupargv (*argvp); + if (!*argvp) + { + fputs ("\nout of memory\n", stderr); + xexit (1); + } + } + /* Count the number of arguments. */ + file_argc = 0; + while (file_argv[file_argc]) + ++file_argc; + /* Now, insert FILE_ARGV into ARGV. The "+1" below handles the + NULL terminator at the end of ARGV. */ + *argvp = ((char **) + xrealloc (*argvp, + (*argcp + file_argc + 1) * sizeof (char *))); + memmove (*argvp + i + file_argc, *argvp + i + 1, + (*argcp - i) * sizeof (char *)); + memcpy (*argvp + i, file_argv, file_argc * sizeof (char *)); + /* The original option has been replaced by all the new + options. */ + *argcp += file_argc - 1; + /* Free up memory allocated to process the response file. We do + not use freeargv because the individual options in FILE_ARGV + are now in the main ARGV. */ + free (file_argv); + free (buffer); + /* Rescan all of the arguments just read to support response + files that include other response files. */ + --i; + error: + /* We're all done with the file now. */ + fclose (f); + } +} + +#ifdef MAIN + +/* Simple little test driver. */ + +static const char *const tests[] = +{ + "a simple command line", + "arg 'foo' is single quoted", + "arg \"bar\" is double quoted", + "arg \"foo bar\" has embedded whitespace", + "arg 'Jack said \\'hi\\'' has single quotes", + "arg 'Jack said \\\"hi\\\"' has double quotes", + "a b c d e f g h i j k l m n o p q r s t u v w x y z 1 2 3 4 5 6 7 8 9", + + /* This should be expanded into only one argument. */ + "trailing-whitespace ", + + "", + NULL +}; + +int +main (void) +{ + char **argv; + const char *const *test; + char **targs; + + for (test = tests; *test != NULL; test++) + { + printf ("buildargv(\"%s\")\n", *test); + if ((argv = buildargv (*test)) == NULL) + { + printf ("failed!\n\n"); + } + else + { + for (targs = argv; *targs != NULL; targs++) + { + printf ("\t\"%s\"\n", *targs); + } + printf ("\n"); + } + freeargv (argv); + } + + return 0; +} + +#endif /* MAIN */ diff --git a/external/gpl3/gdb/dist/libiberty/asprintf.c b/external/gpl3/gdb/dist/libiberty/asprintf.c new file mode 100644 index 000000000000..3cf50526609a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/asprintf.c @@ -0,0 +1,56 @@ +/* Like sprintf but provides a pointer to malloc'd storage, which must + be freed by the caller. + Copyright (C) 1997, 2003 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" + +#include + +/* + +@deftypefn Extension int asprintf (char **@var{resptr}, const char *@var{format}, ...) + +Like @code{sprintf}, but instead of passing a pointer to a buffer, you +pass a pointer to a pointer. This function will compute the size of +the buffer needed, allocate memory with @code{malloc}, and store a +pointer to the allocated memory in @code{*@var{resptr}}. The value +returned is the same as @code{sprintf} would return. If memory could +not be allocated, minus one is returned and @code{NULL} is stored in +@code{*@var{resptr}}. + +@end deftypefn + +*/ + +int +asprintf (char **buf, const char *fmt, ...) +{ + int status; + VA_OPEN (ap, fmt); + VA_FIXEDARG (ap, char **, buf); + VA_FIXEDARG (ap, const char *, fmt); + status = vasprintf (buf, fmt, ap); + VA_CLOSE (ap); + return status; +} diff --git a/external/gpl3/gdb/dist/libiberty/at-file.texi b/external/gpl3/gdb/dist/libiberty/at-file.texi new file mode 100644 index 000000000000..080d1951d62d --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/at-file.texi @@ -0,0 +1,15 @@ +@c This file is designed to be included in manuals that use +@c expandargv. + +@item @@@var{file} +Read command-line options from @var{file}. The options read are +inserted in place of the original @@@var{file} option. If @var{file} +does not exist, or cannot be read, then the option will be treated +literally, and not removed. + +Options in @var{file} are separated by whitespace. A whitespace +character may be included in an option by surrounding the entire +option in either single or double quotes. Any character (including a +backslash) may be included by prefixing the character to be included +with a backslash. The @var{file} may itself contain additional +@@@var{file} options; any such options will be processed recursively. diff --git a/external/gpl3/gdb/dist/libiberty/atexit.c b/external/gpl3/gdb/dist/libiberty/atexit.c new file mode 100644 index 000000000000..e091f0139eed --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/atexit.c @@ -0,0 +1,27 @@ +/* Wrapper to implement ANSI C's atexit using SunOS's on_exit. */ +/* This function is in the public domain. --Mike Stump. */ + +/* + +@deftypefn Supplemental int atexit (void (*@var{f})()) + +Causes function @var{f} to be called at exit. Returns 0. + +@end deftypefn + +*/ + +#include "config.h" + +#ifdef HAVE_ON_EXIT + +int +atexit(void (*f)(void)) +{ + /* If the system doesn't provide a definition for atexit, use on_exit + if the system provides that. */ + on_exit (f, 0); + return 0; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/basename.c b/external/gpl3/gdb/dist/libiberty/basename.c new file mode 100644 index 000000000000..0f2c069f0ccf --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/basename.c @@ -0,0 +1,62 @@ +/* Return the basename of a pathname. + This file is in the public domain. */ + +/* + +@deftypefn Supplemental char* basename (const char *@var{name}) + +Returns a pointer to the last component of pathname @var{name}. +Behavior is undefined if the pathname ends in a directory separator. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#ifndef DIR_SEPARATOR +#define DIR_SEPARATOR '/' +#endif + +#if defined (_WIN32) || defined (__MSDOS__) || defined (__DJGPP__) || \ + defined (__OS2__) +#define HAVE_DOS_BASED_FILE_SYSTEM +#ifndef DIR_SEPARATOR_2 +#define DIR_SEPARATOR_2 '\\' +#endif +#endif + +/* Define IS_DIR_SEPARATOR. */ +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) +#else /* DIR_SEPARATOR_2 */ +# define IS_DIR_SEPARATOR(ch) \ + (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) +#endif /* DIR_SEPARATOR_2 */ + +char * +basename (const char *name) +{ + const char *base; + +#if defined (HAVE_DOS_BASED_FILE_SYSTEM) + /* Skip over the disk name in MSDOS pathnames. */ + if (ISALPHA (name[0]) && name[1] == ':') + name += 2; +#endif + + for (base = name; *name; name++) + { + if (IS_DIR_SEPARATOR (*name)) + { + base = name + 1; + } + } + return (char *) base; +} + diff --git a/external/gpl3/gdb/dist/libiberty/bcmp.c b/external/gpl3/gdb/dist/libiberty/bcmp.c new file mode 100644 index 000000000000..c639f9895bcf --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/bcmp.c @@ -0,0 +1,27 @@ +/* bcmp + This function is in the public domain. */ + +/* + +@deftypefn Supplemental int bcmp (char *@var{x}, char *@var{y}, int @var{count}) + +Compares the first @var{count} bytes of two areas of memory. Returns +zero if they are the same, nonzero otherwise. Returns zero if +@var{count} is zero. A nonzero result only indicates a difference, +it does not indicate any sorting order (say, by having a positive +result mean @var{x} sorts before @var{y}). + +@end deftypefn + +*/ + +#include + +extern int memcmp(const void *, const void *, size_t); + +int +bcmp (const void *s1, const void *s2, size_t count) +{ + return memcmp (s1, s2, count); +} + diff --git a/external/gpl3/gdb/dist/libiberty/bcopy.c b/external/gpl3/gdb/dist/libiberty/bcopy.c new file mode 100644 index 000000000000..f9b7a8acd5c7 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/bcopy.c @@ -0,0 +1,31 @@ +/* bcopy -- copy memory regions of arbitary length + +@deftypefn Supplemental void bcopy (char *@var{in}, char *@var{out}, int @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. The use of @code{bcopy} is deprecated in new programs. + +@end deftypefn + +*/ + +#include + +void +bcopy (const void *src, void *dest, size_t len) +{ + if (dest < src) + { + const char *firsts = (const char *) src; + char *firstd = (char *) dest; + while (len--) + *firstd++ = *firsts++; + } + else + { + const char *lasts = (const char *)src + (len-1); + char *lastd = (char *)dest + (len-1); + while (len--) + *lastd-- = *lasts--; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/bsearch.c b/external/gpl3/gdb/dist/libiberty/bsearch.c new file mode 100644 index 000000000000..35fad19977c2 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/bsearch.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 1990 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. [rescinded 22 July 1999] + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + +@deftypefn Supplemental void* bsearch (const void *@var{key}, @ + const void *@var{base}, size_t @var{nmemb}, size_t @var{size}, @ + int (*@var{compar})(const void *, const void *)) + +Performs a search over an array of @var{nmemb} elements pointed to by +@var{base} for a member that matches the object pointed to by @var{key}. +The size of each member is specified by @var{size}. The array contents +should be sorted in ascending order according to the @var{compar} +comparison function. This routine should take two arguments pointing to +the @var{key} and to an array member, in that order, and should return an +integer less than, equal to, or greater than zero if the @var{key} object +is respectively less than, matching, or greater than the array member. + +@end deftypefn + +*/ + +#include "config.h" +#include "ansidecl.h" +#include /* size_t */ +#include + +/* + * Perform a binary search. + * + * The code below is a bit sneaky. After a comparison fails, we + * divide the work in half by moving either left or right. If lim + * is odd, moving left simply involves halving lim: e.g., when lim + * is 5 we look at item 2, so we change lim to 2 so that we will + * look at items 0 & 1. If lim is even, the same applies. If lim + * is odd, moving right again involes halving lim, this time moving + * the base up one item past p: e.g., when lim is 5 we change base + * to item 3 and make lim 2 so that we will look at items 3 and 4. + * If lim is even, however, we have to shrink it by one before + * halving: e.g., when lim is 4, we still looked at item 2, so we + * have to make lim 3, then halve, obtaining 1, so that we will only + * look at item 3. + */ +void * +bsearch (register const void *key, const void *base0, + size_t nmemb, register size_t size, + register int (*compar)(const void *, const void *)) +{ + register const char *base = (const char *) base0; + register int lim, cmp; + register const void *p; + + for (lim = nmemb; lim != 0; lim >>= 1) { + p = base + (lim >> 1) * size; + cmp = (*compar)(key, p); + if (cmp == 0) + return (void *)p; + if (cmp > 0) { /* key > p: move right */ + base = (const char *)p + size; + lim--; + } /* else move left */ + } + return (NULL); +} diff --git a/external/gpl3/gdb/dist/libiberty/bzero.c b/external/gpl3/gdb/dist/libiberty/bzero.c new file mode 100644 index 000000000000..44ad73da4d6e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/bzero.c @@ -0,0 +1,23 @@ +/* Portable version of bzero for systems without it. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental void bzero (char *@var{mem}, int @var{count}) + +Zeros @var{count} bytes starting at @var{mem}. Use of this function +is deprecated in favor of @code{memset}. + +@end deftypefn + +*/ + +#include + +extern void *memset(void *, int, size_t); + +void +bzero (void *to, size_t count) +{ + memset (to, 0, count); +} diff --git a/external/gpl3/gdb/dist/libiberty/calloc.c b/external/gpl3/gdb/dist/libiberty/calloc.c new file mode 100644 index 000000000000..f4bd27b1cd2a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/calloc.c @@ -0,0 +1,34 @@ +/* calloc -- allocate memory which has been initialized to zero. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental void* calloc (size_t @var{nelem}, size_t @var{elsize}) + +Uses @code{malloc} to allocate storage for @var{nelem} objects of +@var{elsize} bytes each, then zeros the memory. + +@end deftypefn + +*/ + +#include "ansidecl.h" +#include + +/* For systems with larger pointers than ints, this must be declared. */ +PTR malloc (size_t); +void bzero (PTR, size_t); + +PTR +calloc (size_t nelem, size_t elsize) +{ + register PTR ptr; + + if (nelem == 0 || elsize == 0) + nelem = elsize = 1; + + ptr = malloc (nelem * elsize); + if (ptr) bzero (ptr, nelem * elsize); + + return ptr; +} diff --git a/external/gpl3/gdb/dist/libiberty/choose-temp.c b/external/gpl3/gdb/dist/libiberty/choose-temp.c new file mode 100644 index 000000000000..0a454cfa7ca1 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/choose-temp.c @@ -0,0 +1,75 @@ +/* Utility to pick a temporary filename prefix. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include /* May get P_tmpdir. */ +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +#include "libiberty.h" +extern char *choose_tmpdir (void); + +/* Name of temporary file. + mktemp requires 6 trailing X's. */ +#define TEMP_FILE "ccXXXXXX" +#define TEMP_FILE_LEN (sizeof(TEMP_FILE) - 1) + +/* + +@deftypefn Extension char* choose_temp_base (void) + +Return a prefix for temporary file names or @code{NULL} if unable to +find one. The current directory is chosen if all else fails so the +program is exited if a temporary directory can't be found (@code{mktemp} +fails). The buffer for the result is obtained with @code{xmalloc}. + +This function is provided for backwards compatibility only. Its use is +not recommended. + +@end deftypefn + +*/ + +char * +choose_temp_base (void) +{ + const char *base = choose_tmpdir (); + char *temp_filename; + int len; + + len = strlen (base); + temp_filename = XNEWVEC (char, len + TEMP_FILE_LEN + 1); + strcpy (temp_filename, base); + strcpy (temp_filename + len, TEMP_FILE); + + if (mktemp (temp_filename) == 0) + abort (); + return temp_filename; +} diff --git a/external/gpl3/gdb/dist/libiberty/clock.c b/external/gpl3/gdb/dist/libiberty/clock.c new file mode 100644 index 000000000000..07d902e8a160 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/clock.c @@ -0,0 +1,103 @@ +/* ANSI-compatible clock function. + Copyright (C) 1994, 1995, 1999 Free Software Foundation, Inc. + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental long clock (void) + +Returns an approximation of the CPU time used by the process as a +@code{clock_t}; divide this number by @samp{CLOCKS_PER_SEC} to get the +number of seconds used. + +@end deftypefn + +*/ + +#include "config.h" + +#ifdef HAVE_GETRUSAGE +#include +#include +#endif + +#ifdef HAVE_TIMES +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include +#endif + +#ifdef HAVE_UNISTD_H +#include +#endif + +#ifdef _SC_CLK_TCK +#define GNU_HZ sysconf(_SC_CLK_TCK) +#else +#ifdef HZ +#define GNU_HZ HZ +#else +#ifdef CLOCKS_PER_SEC +#define GNU_HZ CLOCKS_PER_SEC +#endif +#endif +#endif + +/* FIXME: should be able to declare as clock_t. */ + +long +clock (void) +{ +#ifdef HAVE_GETRUSAGE + struct rusage rusage; + + getrusage (0, &rusage); + return (rusage.ru_utime.tv_sec * 1000000 + rusage.ru_utime.tv_usec + + rusage.ru_stime.tv_sec * 1000000 + rusage.ru_stime.tv_usec); +#else +#ifdef HAVE_TIMES + struct tms tms; + + times (&tms); + return (tms.tms_utime + tms.tms_stime) * (1000000 / GNU_HZ); +#else +#ifdef VMS + struct + { + int proc_user_time; + int proc_system_time; + int child_user_time; + int child_system_time; + } vms_times; + + times (&vms_times); + return (vms_times.proc_user_time + vms_times.proc_system_time) * 10000; +#else + /* A fallback, if nothing else available. */ + return 0; +#endif /* VMS */ +#endif /* HAVE_TIMES */ +#endif /* HAVE_GETRUSAGE */ +} + diff --git a/external/gpl3/gdb/dist/libiberty/concat.c b/external/gpl3/gdb/dist/libiberty/concat.c new file mode 100644 index 000000000000..9779d5663b66 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/concat.c @@ -0,0 +1,234 @@ +/* Concatenate variable number of strings. + Copyright (C) 1991, 1994, 2001, 2011 Free Software Foundation, Inc. + Written by Fred Fish @ Cygnus Support + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + + +/* + +@deftypefn Extension char* concat (const char *@var{s1}, const char *@var{s2}, @ + @dots{}, @code{NULL}) + +Concatenate zero or more of strings and return the result in freshly +@code{xmalloc}ed memory. Returns @code{NULL} if insufficient memory is +available. The argument list is terminated by the first @code{NULL} +pointer encountered. Pointers to empty strings are ignored. + +@end deftypefn + +NOTES + + This function uses xmalloc() which is expected to be a front end + function to malloc() that deals with low memory situations. In + typical use, if malloc() returns NULL then xmalloc() diverts to an + error handler routine which never returns, and thus xmalloc will + never return a NULL pointer. If the client application wishes to + deal with low memory situations itself, it should supply an xmalloc + that just directly invokes malloc and blindly returns whatever + malloc returns. + +*/ + + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include /* size_t */ + +#include + +# if HAVE_STRING_H +# include +# else +# if HAVE_STRINGS_H +# include +# endif +# endif + +#if HAVE_STDLIB_H +#include +#endif + +static inline unsigned long vconcat_length (const char *, va_list); +static inline unsigned long +vconcat_length (const char *first, va_list args) +{ + unsigned long length = 0; + const char *arg; + + for (arg = first; arg ; arg = va_arg (args, const char *)) + length += strlen (arg); + + return length; +} + +static inline char * +vconcat_copy (char *dst, const char *first, va_list args) +{ + char *end = dst; + const char *arg; + + for (arg = first; arg ; arg = va_arg (args, const char *)) + { + unsigned long length = strlen (arg); + memcpy (end, arg, length); + end += length; + } + *end = '\000'; + + return dst; +} + +/* @undocumented concat_length */ + +unsigned long +concat_length (const char *first, ...) +{ + unsigned long length; + + VA_OPEN (args, first); + VA_FIXEDARG (args, const char *, first); + length = vconcat_length (first, args); + VA_CLOSE (args); + + return length; +} + +/* @undocumented concat_copy */ + +char * +concat_copy (char *dst, const char *first, ...) +{ + char *save_dst; + + VA_OPEN (args, first); + VA_FIXEDARG (args, char *, dst); + VA_FIXEDARG (args, const char *, first); + vconcat_copy (dst, first, args); + save_dst = dst; /* With K&R C, dst goes out of scope here. */ + VA_CLOSE (args); + + return save_dst; +} + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +char *libiberty_concat_ptr; +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/* @undocumented concat_copy2 */ + +char * +concat_copy2 (const char *first, ...) +{ + VA_OPEN (args, first); + VA_FIXEDARG (args, const char *, first); + vconcat_copy (libiberty_concat_ptr, first, args); + VA_CLOSE (args); + + return libiberty_concat_ptr; +} + +char * +concat (const char *first, ...) +{ + char *newstr; + + /* First compute the size of the result and get sufficient memory. */ + VA_OPEN (args, first); + VA_FIXEDARG (args, const char *, first); + newstr = XNEWVEC (char, vconcat_length (first, args) + 1); + VA_CLOSE (args); + + /* Now copy the individual pieces to the result string. */ + VA_OPEN (args, first); + VA_FIXEDARG (args, const char *, first); + vconcat_copy (newstr, first, args); + VA_CLOSE (args); + + return newstr; +} + +/* + +@deftypefn Extension char* reconcat (char *@var{optr}, const char *@var{s1}, @ + @dots{}, @code{NULL}) + +Same as @code{concat}, except that if @var{optr} is not @code{NULL} it +is freed after the string is created. This is intended to be useful +when you're extending an existing string or building up a string in a +loop: + +@example + str = reconcat (str, "pre-", str, NULL); +@end example + +@end deftypefn + +*/ + +char * +reconcat (char *optr, const char *first, ...) +{ + char *newstr; + + /* First compute the size of the result and get sufficient memory. */ + VA_OPEN (args, first); + VA_FIXEDARG (args, char *, optr); + VA_FIXEDARG (args, const char *, first); + newstr = XNEWVEC (char, vconcat_length (first, args) + 1); + VA_CLOSE (args); + + /* Now copy the individual pieces to the result string. */ + VA_OPEN (args, first); + VA_FIXEDARG (args, char *, optr); + VA_FIXEDARG (args, const char *, first); + vconcat_copy (newstr, first, args); + if (optr) /* Done before VA_CLOSE so optr stays in scope for K&R C. */ + free (optr); + VA_CLOSE (args); + + return newstr; +} + +#ifdef MAIN +#define NULLP (char *)0 + +/* Simple little test driver. */ + +#include + +int +main (void) +{ + printf ("\"\" = \"%s\"\n", concat (NULLP)); + printf ("\"a\" = \"%s\"\n", concat ("a", NULLP)); + printf ("\"ab\" = \"%s\"\n", concat ("a", "b", NULLP)); + printf ("\"abc\" = \"%s\"\n", concat ("a", "b", "c", NULLP)); + printf ("\"abcd\" = \"%s\"\n", concat ("ab", "cd", NULLP)); + printf ("\"abcde\" = \"%s\"\n", concat ("ab", "c", "de", NULLP)); + printf ("\"abcdef\" = \"%s\"\n", concat ("", "a", "", "bcd", "ef", NULLP)); + return 0; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/config.h-vms b/external/gpl3/gdb/dist/libiberty/config.h-vms new file mode 100644 index 000000000000..d923ecb3cf26 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config.h-vms @@ -0,0 +1,14 @@ +/* This is -*- C -*- */ +#define HAVE_STDLIB_H 1 +#define HAVE_UNISTD_H 1 +#define HAVE_STRING_H 1 +#define HAVE_SYS_STAT_H 1 +#define HAVE_SYS_TIME_H 1 + +/* intptr_t is defined in inttypes.h! */ +#define intptr_t __int64 + +/* Cheat: use vms builtin alloca. */ +#ifdef __DECC +#define C_alloca(x) __ALLOCA(x) +#endif diff --git a/external/gpl3/gdb/dist/libiberty/config.in b/external/gpl3/gdb/dist/libiberty/config.in new file mode 100644 index 000000000000..e4f1f1620e19 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config.in @@ -0,0 +1,490 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define if building universal (internal helper macro) */ +#undef AC_APPLE_UNIVERSAL_BUILD + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define to 1 if you have the header file. */ +#undef HAVE_ALLOCA_H + +/* Define to 1 if you have the `asprintf' function. */ +#undef HAVE_ASPRINTF + +/* Define to 1 if you have the `atexit' function. */ +#undef HAVE_ATEXIT + +/* Define to 1 if you have the `basename' function. */ +#undef HAVE_BASENAME + +/* Define to 1 if you have the `bcmp' function. */ +#undef HAVE_BCMP + +/* Define to 1 if you have the `bcopy' function. */ +#undef HAVE_BCOPY + +/* Define to 1 if you have the `bsearch' function. */ +#undef HAVE_BSEARCH + +/* Define to 1 if you have the `bzero' function. */ +#undef HAVE_BZERO + +/* Define to 1 if you have the `calloc' function. */ +#undef HAVE_CALLOC + +/* Define to 1 if you have the `canonicalize_file_name' function. */ +#undef HAVE_CANONICALIZE_FILE_NAME + +/* Define to 1 if you have the `clock' function. */ +#undef HAVE_CLOCK + +/* Define to 1 if you have the declaration of `asprintf', and to 0 if you + don't. */ +#undef HAVE_DECL_ASPRINTF + +/* Define to 1 if you have the declaration of `basename(char *)', and to 0 if + you don't. */ +#undef HAVE_DECL_BASENAME + +/* Define to 1 if you have the declaration of `calloc', and to 0 if you don't. + */ +#undef HAVE_DECL_CALLOC + +/* Define to 1 if you have the declaration of `ffs', and to 0 if you don't. */ +#undef HAVE_DECL_FFS + +/* Define to 1 if you have the declaration of `getenv', and to 0 if you don't. + */ +#undef HAVE_DECL_GETENV + +/* Define to 1 if you have the declaration of `getopt', and to 0 if you don't. + */ +#undef HAVE_DECL_GETOPT + +/* Define to 1 if you have the declaration of `malloc', and to 0 if you don't. + */ +#undef HAVE_DECL_MALLOC + +/* Define to 1 if you have the declaration of `realloc', and to 0 if you + don't. */ +#undef HAVE_DECL_REALLOC + +/* Define to 1 if you have the declaration of `sbrk', and to 0 if you don't. + */ +#undef HAVE_DECL_SBRK + +/* Define to 1 if you have the declaration of `snprintf', and to 0 if you + don't. */ +#undef HAVE_DECL_SNPRINTF + +/* Define to 1 if you have the declaration of `strverscmp', and to 0 if you + don't. */ +#undef HAVE_DECL_STRVERSCMP + +/* Define to 1 if you have the declaration of `vasprintf', and to 0 if you + don't. */ +#undef HAVE_DECL_VASPRINTF + +/* Define to 1 if you have the declaration of `vsnprintf', and to 0 if you + don't. */ +#undef HAVE_DECL_VSNPRINTF + +/* Define to 1 if you have the `dup3' function. */ +#undef HAVE_DUP3 + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the `ffs' function. */ +#undef HAVE_FFS + +/* Define to 1 if you have the `fork' function. */ +#undef HAVE_FORK + +/* Define to 1 if you have the `getcwd' function. */ +#undef HAVE_GETCWD + +/* Define to 1 if you have the `getpagesize' function. */ +#undef HAVE_GETPAGESIZE + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the `getsysinfo' function. */ +#undef HAVE_GETSYSINFO + +/* Define to 1 if you have the `gettimeofday' function. */ +#undef HAVE_GETTIMEOFDAY + +/* Define to 1 if you have the `index' function. */ +#undef HAVE_INDEX + +/* Define to 1 if you have the `insque' function. */ +#undef HAVE_INSQUE + +/* Define to 1 if the system has the type `intptr_t'. */ +#undef HAVE_INTPTR_T + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_MACHINE_HAL_SYSINFO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define to 1 if you have the `memchr' function. */ +#undef HAVE_MEMCHR + +/* Define to 1 if you have the `memcmp' function. */ +#undef HAVE_MEMCMP + +/* Define to 1 if you have the `memcpy' function. */ +#undef HAVE_MEMCPY + +/* Define to 1 if you have the `memmem' function. */ +#undef HAVE_MEMMEM + +/* Define to 1 if you have the `memmove' function. */ +#undef HAVE_MEMMOVE + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `memset' function. */ +#undef HAVE_MEMSET + +/* Define to 1 if you have the `mkstemps' function. */ +#undef HAVE_MKSTEMPS + +/* Define to 1 if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define to 1 if you have the `on_exit' function. */ +#undef HAVE_ON_EXIT + +/* Define to 1 if you have the header file. */ +#undef HAVE_PROCESS_H + +/* Define to 1 if you have the `psignal' function. */ +#undef HAVE_PSIGNAL + +/* Define to 1 if you have the `pstat_getdynamic' function. */ +#undef HAVE_PSTAT_GETDYNAMIC + +/* Define to 1 if you have the `pstat_getstatic' function. */ +#undef HAVE_PSTAT_GETSTATIC + +/* Define to 1 if you have the `putenv' function. */ +#undef HAVE_PUTENV + +/* Define to 1 if you have the `random' function. */ +#undef HAVE_RANDOM + +/* Define to 1 if you have the `realpath' function. */ +#undef HAVE_REALPATH + +/* Define to 1 if you have the `rename' function. */ +#undef HAVE_RENAME + +/* Define to 1 if you have the `rindex' function. */ +#undef HAVE_RINDEX + +/* Define to 1 if you have the `sbrk' function. */ +#undef HAVE_SBRK + +/* Define to 1 if you have the `setenv' function. */ +#undef HAVE_SETENV + +/* Define to 1 if you have the `setproctitle' function. */ +#undef HAVE_SETPROCTITLE + +/* Define to 1 if you have the `sigsetmask' function. */ +#undef HAVE_SIGSETMASK + +/* Define to 1 if you have the `snprintf' function. */ +#undef HAVE_SNPRINTF + +/* Define to 1 if you have the `spawnve' function. */ +#undef HAVE_SPAWNVE + +/* Define to 1 if you have the `spawnvpe' function. */ +#undef HAVE_SPAWNVPE + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDIO_EXT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the `stpcpy' function. */ +#undef HAVE_STPCPY + +/* Define to 1 if you have the `stpncpy' function. */ +#undef HAVE_STPNCPY + +/* Define to 1 if you have the `strcasecmp' function. */ +#undef HAVE_STRCASECMP + +/* Define to 1 if you have the `strchr' function. */ +#undef HAVE_STRCHR + +/* Define to 1 if you have the `strdup' function. */ +#undef HAVE_STRDUP + +/* Define to 1 if you have the `strerror' function. */ +#undef HAVE_STRERROR + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the `strncasecmp' function. */ +#undef HAVE_STRNCASECMP + +/* Define to 1 if you have the `strndup' function. */ +#undef HAVE_STRNDUP + +/* Define to 1 if you have the `strrchr' function. */ +#undef HAVE_STRRCHR + +/* Define to 1 if you have the `strsignal' function. */ +#undef HAVE_STRSIGNAL + +/* Define to 1 if you have the `strstr' function. */ +#undef HAVE_STRSTR + +/* Define to 1 if you have the `strtod' function. */ +#undef HAVE_STRTOD + +/* Define to 1 if you have the `strtol' function. */ +#undef HAVE_STRTOL + +/* Define to 1 if you have the `strtoul' function. */ +#undef HAVE_STRTOUL + +/* Define to 1 if you have the `strverscmp' function. */ +#undef HAVE_STRVERSCMP + +/* Define to 1 if you have the `sysconf' function. */ +#undef HAVE_SYSCONF + +/* Define to 1 if you have the `sysctl' function. */ +#undef HAVE_SYSCTL + +/* Define to 1 if you have the `sysmp' function. */ +#undef HAVE_SYSMP + +/* Define if you have the sys_errlist variable. */ +#undef HAVE_SYS_ERRLIST + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_FILE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_MMAN_H + +/* Define if you have the sys_nerr variable. */ +#undef HAVE_SYS_NERR + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_PRCTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_PSTAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define if you have the sys_siglist variable. */ +#undef HAVE_SYS_SIGLIST + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_SYSCTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_SYSINFO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_SYSMP_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_SYSTEMCFG_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TABLE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have that is POSIX.1 compatible. */ +#undef HAVE_SYS_WAIT_H + +/* Define to 1 if you have the `table' function. */ +#undef HAVE_TABLE + +/* Define to 1 if you have the `times' function. */ +#undef HAVE_TIMES + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the `tmpnam' function. */ +#undef HAVE_TMPNAM + +/* Define if you have the \`uintptr_t' type. */ +#undef HAVE_UINTPTR_T + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the `vasprintf' function. */ +#undef HAVE_VASPRINTF + +/* Define to 1 if you have the `vfork' function. */ +#undef HAVE_VFORK + +/* Define to 1 if you have the header file. */ +#undef HAVE_VFORK_H + +/* Define to 1 if you have the `vfprintf' function. */ +#undef HAVE_VFPRINTF + +/* Define to 1 if you have the `vprintf' function. */ +#undef HAVE_VPRINTF + +/* Define to 1 if you have the `vsprintf' function. */ +#undef HAVE_VSPRINTF + +/* Define to 1 if you have the `wait3' function. */ +#undef HAVE_WAIT3 + +/* Define to 1 if you have the `wait4' function. */ +#undef HAVE_WAIT4 + +/* Define to 1 if you have the `waitpid' function. */ +#undef HAVE_WAITPID + +/* Define to 1 if `fork' works. */ +#undef HAVE_WORKING_FORK + +/* Define to 1 if `vfork' works. */ +#undef HAVE_WORKING_VFORK + +/* Define to 1 if you have the `_doprnt' function. */ +#undef HAVE__DOPRNT + +/* Define if you have the _system_configuration variable. */ +#undef HAVE__SYSTEM_CONFIGURATION + +/* Define to 1 if you have the `__fsetlocking' function. */ +#undef HAVE___FSETLOCKING + +/* Define if canonicalize_file_name is not declared in system header files. */ +#undef NEED_DECLARATION_CANONICALIZE_FILE_NAME + +/* Define if errno must be declared even when is included. */ +#undef NEED_DECLARATION_ERRNO + +/* Define to 1 if your C compiler doesn't accept -c and -o together. */ +#undef NO_MINUS_C_MINUS_O + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* The size of `int', as computed by sizeof. */ +#undef SIZEOF_INT + +/* Define if you know the direction of stack growth for your system; otherwise + it will be automatically deduced at run-time. STACK_DIRECTION > 0 => grows + toward higher addresses STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown */ +#undef STACK_DIRECTION + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define to 1 if you can safely include both and . */ +#undef TIME_WITH_SYS_TIME + +/* Define to an unsigned 64-bit type available in the compiler. */ +#undef UNSIGNED_64BIT_TYPE + +/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most + significant byte first (like Motorola and SPARC, unlike Intel). */ +#if defined AC_APPLE_UNIVERSAL_BUILD +# if defined __BIG_ENDIAN__ +# define WORDS_BIGENDIAN 1 +# endif +#else +# ifndef WORDS_BIGENDIAN +# undef WORDS_BIGENDIAN +# endif +#endif + +/* Number of bits in a file offset, on hosts where this is settable. */ +#undef _FILE_OFFSET_BITS + +/* Define for large files, on AIX-style hosts. */ +#undef _LARGE_FILES + +/* Define to empty if `const' does not conform to ANSI C. */ +#undef const + +/* Define to `__inline__' or `__inline' if that's what the C compiler + calls it, or to nothing if 'inline' is not supported under any name. */ +#ifndef __cplusplus +#undef inline +#endif + +/* Define to the type of a signed integer type wide enough to hold a pointer, + if such a type exists, and if the system does not define it. */ +#undef intptr_t + +/* Define to `int' if does not define. */ +#undef pid_t + +/* Define to `int' if does not define. */ +#undef ssize_t + +/* Define to the type of an unsigned integer type wide enough to hold a + pointer, if such a type exists, and if the system does not define it. */ +#undef uintptr_t + +/* Define as `fork' if `vfork' does not work. */ +#undef vfork diff --git a/external/gpl3/gdb/dist/libiberty/config/mh-aix b/external/gpl3/gdb/dist/libiberty/config/mh-aix new file mode 100644 index 000000000000..6b645058fa9d --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config/mh-aix @@ -0,0 +1,9 @@ +# This file is only needed by AIX 3.1. +HDEFINES = -D__IEEE_BIG_ENDIAN + +# Most releases of AIX 3.1 include an incorrect internal version of copysign +# in libc.a for use by some libc public functions including modf. The public +# version of copysign in libm.a is usable. For the sake of libg++ (which +# uses modf), we add copysign here. Supposedly, this problem is fixed in AIX +# 3.1.8 and above, including all releases of AIX 3.2. +EXTRA_OFILES = copysign.o diff --git a/external/gpl3/gdb/dist/libiberty/config/mh-cxux7 b/external/gpl3/gdb/dist/libiberty/config/mh-cxux7 new file mode 100644 index 000000000000..a924b0853fcc --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config/mh-cxux7 @@ -0,0 +1 @@ +HDEFINES = -DHARRIS_FLOAT_FORMAT diff --git a/external/gpl3/gdb/dist/libiberty/config/mh-fbsd21 b/external/gpl3/gdb/dist/libiberty/config/mh-fbsd21 new file mode 100644 index 000000000000..1375a780bef9 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config/mh-fbsd21 @@ -0,0 +1 @@ +EXTRA_OFILES=vasprintf.o diff --git a/external/gpl3/gdb/dist/libiberty/config/mh-openedition b/external/gpl3/gdb/dist/libiberty/config/mh-openedition new file mode 100644 index 000000000000..8de8ed16cc09 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config/mh-openedition @@ -0,0 +1,3 @@ +HDEFINES = -D_ALL_SOURCE -DLE370 +CC=c89 + diff --git a/external/gpl3/gdb/dist/libiberty/config/mh-windows b/external/gpl3/gdb/dist/libiberty/config/mh-windows new file mode 100644 index 000000000000..3ff5f794e9f8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/config/mh-windows @@ -0,0 +1 @@ +EXTRA_OFILES=asprintf.o strcasecmp.o strncasecmp.o vasprintf.o diff --git a/external/gpl3/gdb/dist/libiberty/configure b/external/gpl3/gdb/dist/libiberty/configure new file mode 100755 index 000000000000..bdabe8d1a354 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/configure @@ -0,0 +1,8206 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. 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+ if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + return $ac_retval + +} # ac_fn_c_try_cpp + +# ac_fn_c_try_run LINENO +# ---------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes +# that executables *can* be run. +ac_fn_c_try_run () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { ac_try='./conftest$ac_exeext' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then : + ac_retval=0 +else + $as_echo "$as_me: program exited with status $ac_status" >&5 + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=$ac_status +fi + rm -rf conftest.dSYM conftest_ipa8_conftest.oo + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + return $ac_retval + +} # ac_fn_c_try_run + +# ac_fn_c_check_header_preproc LINENO HEADER VAR +# ---------------------------------------------- +# Tests whether HEADER is present, setting the cache variable VAR accordingly. +ac_fn_c_check_header_preproc () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <$2> +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f conftest.err conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_header_preproc + +# ac_fn_c_compute_int LINENO EXPR VAR INCLUDES +# -------------------------------------------- +# Tries to find the compile-time value of EXPR in a program that includes +# INCLUDES, setting VAR accordingly. Returns whether the value could be +# computed +ac_fn_c_compute_int () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + if test "$cross_compiling" = yes; then + # Depending upon the size, compute the lo and hi bounds. +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) >= 0)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_lo=0 ac_mid=0 + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) <= $ac_mid)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=$ac_mid; break +else + as_fn_arith $ac_mid + 1 && ac_lo=$as_val + if test $ac_lo -le $ac_mid; then + ac_lo= ac_hi= + break + fi + as_fn_arith 2 '*' $ac_mid + 1 && ac_mid=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + done +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) < 0)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=-1 ac_mid=-1 + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) >= $ac_mid)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_lo=$ac_mid; break +else + as_fn_arith '(' $ac_mid ')' - 1 && ac_hi=$as_val + if test $ac_mid -le $ac_hi; then + ac_lo= ac_hi= + break + fi + as_fn_arith 2 '*' $ac_mid && ac_mid=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + done +else + ac_lo= ac_hi= +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +# Binary search between lo and hi bounds. +while test "x$ac_lo" != "x$ac_hi"; do + as_fn_arith '(' $ac_hi - $ac_lo ')' / 2 + $ac_lo && ac_mid=$as_val + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +static int test_array [1 - 2 * !(($2) <= $ac_mid)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_hi=$ac_mid +else + as_fn_arith '(' $ac_mid ')' + 1 && ac_lo=$as_val +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +done +case $ac_lo in #(( +?*) eval "$3=\$ac_lo"; ac_retval=0 ;; +'') ac_retval=1 ;; +esac + else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +static long int longval () { return $2; } +static unsigned long int ulongval () { return $2; } +#include +#include +int +main () +{ + + FILE *f = fopen ("conftest.val", "w"); + if (! f) + return 1; + if (($2) < 0) + { + long int i = longval (); + if (i != ($2)) + return 1; + fprintf (f, "%ld", i); + } + else + { + unsigned long int i = ulongval (); + if (i != ($2)) + return 1; + fprintf (f, "%lu", i); + } + /* Do not output a trailing newline, as this causes \r\n confusion + on some platforms. */ + return ferror (f) || fclose (f) != 0; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + echo >>conftest.val; read $3 &5 +$as_echo_n "checking for $2... " >&6; } +if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + eval "$3=no" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +if (sizeof ($2)) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +int +main () +{ +if (sizeof (($2))) + return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + eval "$3=yes" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_type + +# ac_fn_c_try_link LINENO +# ----------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. +ac_fn_c_try_link () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext conftest$ac_exeext + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information + # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would + # interfere with the next link command; also delete a directory that is + # left behind by Apple's compiler. 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"$LINENO" 5 +fi +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +/* Define $2 to an innocuous variant, in case declares $2. + For example, HP-UX 11i declares gettimeofday. */ +#define $2 innocuous_$2 + +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char $2 (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +#undef $2 + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char $2 (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined __stub_$2 || defined __stub___$2 +choke me +#endif + +int +main () +{ +return $2 (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_func + +# ac_fn_c_check_decl LINENO SYMBOL VAR +# ------------------------------------ +# Tests whether SYMBOL is declared, setting cache variable VAR accordingly. +ac_fn_c_check_decl () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + as_decl_name=`echo $2|sed 's/ *(.*//'` + as_decl_use=`echo $2|sed -e 's/(/((/' -e 's/)/) 0&/' -e 's/,/) 0& (/g'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $as_decl_name is declared" >&5 +$as_echo_n "checking whether $as_decl_name is declared... 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"$ac_site_file" + fi +done + +if test -r "$cache_file"; then + # Some versions of bash will fail to source /dev/null (special + # files actually), so we avoid doing that. + if test -f "$cache_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +$as_echo "$as_me: loading cache $cache_file" >&6;} + case $cache_file in + [\\/]* | ?:[\\/]* ) . "$cache_file";; + *) . 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" >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Add --enable-multilib to configure. +# Default to --enable-multilib +# Check whether --enable-multilib was given. +if test "${enable_multilib+set}" = set; then : + enableval=$enable_multilib; case "$enableval" in + yes) multilib=yes ;; + no) multilib=no ;; + *) as_fn_error "bad value $enableval for multilib option" "$LINENO" 5 ;; + esac +else + multilib=yes +fi + + +# Even if the default multilib is not a cross compilation, +# it may be that some of the other multilibs are. +if test $cross_compiling = no && test $multilib = yes \ + && test "x${with_multisubdir}" != x ; then + cross_compiling=maybe +fi + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +# FIXME: Cleanup? +if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + gcc_no_link=no +else + gcc_no_link=yes +fi +if test x$gcc_no_link = xyes; then + # Setting cross_compile will disable run tests; it will + # also disable AC_CHECK_FILE but that's generally + # correct if we can't link. + cross_compiling=yes + EXEEXT= +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." 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For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." 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" >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +# Check whether --enable-largefile was given. +if test "${enable_largefile+set}" = set; then : + enableval=$enable_largefile; +fi + +if test "$enable_largefile" != no; then + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for special C compiler options needed for large files" >&5 +$as_echo_n "checking for special C compiler options needed for large files... " >&6; } +if test "${ac_cv_sys_largefile_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_sys_largefile_CC=no + if test "$GCC" != yes; then + ac_save_CC=$CC + while :; do + # IRIX 6.2 and later do not support large files by default, + # so use the C compiler's -n32 option if that helps. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + /* Check that off_t can represent 2**63 - 1 correctly. + We can't simply define LARGE_OFF_T to be 9223372036854775807, + since some C++ compilers masquerading as C compilers + incorrectly reject 9223372036854775807. */ +#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62)) + int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721 + && LARGE_OFF_T % 2147483647 == 1) + ? 1 : -1]; +int +main () +{ + + ; + return 0; +} +_ACEOF + if ac_fn_c_try_compile "$LINENO"; then : + break +fi +rm -f core conftest.err conftest.$ac_objext + CC="$CC -n32" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_sys_largefile_CC=' -n32'; break +fi +rm -f core conftest.err conftest.$ac_objext + break + done + CC=$ac_save_CC + rm -f conftest.$ac_ext + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sys_largefile_CC" >&5 +$as_echo "$ac_cv_sys_largefile_CC" >&6; } + if test "$ac_cv_sys_largefile_CC" != no; then + CC=$CC$ac_cv_sys_largefile_CC + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _FILE_OFFSET_BITS value needed for large files" >&5 +$as_echo_n "checking for _FILE_OFFSET_BITS value needed for large files... " >&6; } +if test "${ac_cv_sys_file_offset_bits+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + /* Check that off_t can represent 2**63 - 1 correctly. + We can't simply define LARGE_OFF_T to be 9223372036854775807, + since some C++ compilers masquerading as C compilers + incorrectly reject 9223372036854775807. */ +#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62)) + int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721 + && LARGE_OFF_T % 2147483647 == 1) + ? 1 : -1]; +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_sys_file_offset_bits=no; break +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#define _FILE_OFFSET_BITS 64 +#include + /* Check that off_t can represent 2**63 - 1 correctly. + We can't simply define LARGE_OFF_T to be 9223372036854775807, + since some C++ compilers masquerading as C compilers + incorrectly reject 9223372036854775807. */ +#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62)) + int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721 + && LARGE_OFF_T % 2147483647 == 1) + ? 1 : -1]; +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_sys_file_offset_bits=64; break +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_cv_sys_file_offset_bits=unknown + break +done +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sys_file_offset_bits" >&5 +$as_echo "$ac_cv_sys_file_offset_bits" >&6; } +case $ac_cv_sys_file_offset_bits in #( + no | unknown) ;; + *) +cat >>confdefs.h <<_ACEOF +#define _FILE_OFFSET_BITS $ac_cv_sys_file_offset_bits +_ACEOF +;; +esac +rm -rf conftest* + if test $ac_cv_sys_file_offset_bits = unknown; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _LARGE_FILES value needed for large files" >&5 +$as_echo_n "checking for _LARGE_FILES value needed for large files... " >&6; } +if test "${ac_cv_sys_large_files+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + while :; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + /* Check that off_t can represent 2**63 - 1 correctly. + We can't simply define LARGE_OFF_T to be 9223372036854775807, + since some C++ compilers masquerading as C compilers + incorrectly reject 9223372036854775807. */ +#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62)) + int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721 + && LARGE_OFF_T % 2147483647 == 1) + ? 1 : -1]; +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_sys_large_files=no; break +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#define _LARGE_FILES 1 +#include + /* Check that off_t can represent 2**63 - 1 correctly. + We can't simply define LARGE_OFF_T to be 9223372036854775807, + since some C++ compilers masquerading as C compilers + incorrectly reject 9223372036854775807. */ +#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62)) + int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721 + && LARGE_OFF_T % 2147483647 == 1) + ? 1 : -1]; +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_sys_large_files=1; break +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_cv_sys_large_files=unknown + break +done +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sys_large_files" >&5 +$as_echo "$ac_cv_sys_large_files" >&6; } +case $ac_cv_sys_large_files in #( + no | unknown) ;; + *) +cat >>confdefs.h <<_ACEOF +#define _LARGE_FILES $ac_cv_sys_large_files +_ACEOF +;; +esac +rm -rf conftest* + fi +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +ac_c_preproc_warn_flag=yes + +ac_libiberty_warn_cflags= +save_CFLAGS="$CFLAGS" +for option in -W -Wall -Wwrite-strings -Wc++-compat \ + -Wstrict-prototypes; do + as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh` + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5 +$as_echo_n "checking whether $CC supports $option... " >&6; } +if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + CFLAGS="$option" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_acx_Woption=yes" +else + eval "$as_acx_Woption=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +fi +eval ac_res=\$$as_acx_Woption + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then : + ac_libiberty_warn_cflags="$ac_libiberty_warn_cflags${ac_libiberty_warn_cflags:+ }$option" +fi + done +CFLAGS="$save_CFLAGS" + +if test "$GCC" = yes; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports -pedantic " >&5 +$as_echo_n "checking whether $CC supports -pedantic ... " >&6; } +if test "${acx_cv_prog_cc_pedantic_+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + save_CFLAGS="$CFLAGS" +CFLAGS="-pedantic " +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + acx_cv_prog_cc_pedantic_=yes +else + acx_cv_prog_cc_pedantic_=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +CFLAGS="$save_CFLAGS" +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $acx_cv_prog_cc_pedantic_" >&5 +$as_echo "$acx_cv_prog_cc_pedantic_" >&6; } +if test $acx_cv_prog_cc_pedantic_ = yes; then : + ac_libiberty_warn_cflags="$ac_libiberty_warn_cflags${ac_libiberty_warn_cflags:+ }-pedantic " +fi + +fi + + +if test "x$CC" != xcc; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC and cc understand -c and -o together" >&5 +$as_echo_n "checking whether $CC and cc understand -c and -o together... " >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether cc understands -c and -o together" >&5 +$as_echo_n "checking whether cc understands -c and -o together... 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" >&6; } +if test "${ac_cv_c_const+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +/* FIXME: Include the comments suggested by Paul. */ +#ifndef __cplusplus + /* Ultrix mips cc rejects this. */ + typedef int charset[2]; + const charset cs; + /* SunOS 4.1.1 cc rejects this. */ + char const *const *pcpcc; + char **ppc; + /* NEC SVR4.0.2 mips cc rejects this. */ + struct point {int x, y;}; + static struct point const zero = {0,0}; + /* AIX XL C 1.02.0.0 rejects this. + It does not let you subtract one const X* pointer from another in + an arm of an if-expression whose if-part is not a constant + expression */ + const char *g = "string"; + pcpcc = &g + (g ? g-g : 0); + /* HPUX 7.0 cc rejects these. */ + ++pcpcc; + ppc = (char**) pcpcc; + pcpcc = (char const *const *) ppc; + { /* SCO 3.2v4 cc rejects this. */ + char *t; + char const *s = 0 ? (char *) 0 : (char const *) 0; + + *t++ = 0; + if (s) return 0; + } + { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ + int x[] = {25, 17}; + const int *foo = &x[0]; + ++foo; + } + { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ + typedef const int *iptr; + iptr p = 0; + ++p; + } + { /* AIX XL C 1.02.0.0 rejects this saying + "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ + struct s { int j; const int *ap[3]; }; + struct s *b; b->j = 5; + } + { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; + if (!foo) return 0; + } + return !cs[0] && !zero.x; +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_const=yes +else + ac_cv_c_const=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_const" >&5 +$as_echo "$ac_cv_c_const" >&6; } +if test $ac_cv_c_const = no; then + +$as_echo "#define const /**/" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for inline" >&5 +$as_echo_n "checking for inline... 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" >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_preproc "$LINENO" "$ac_header" "$as_ac_Header" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 +$as_echo_n "checking whether byte ordering is bigendian... " >&6; } +if test "${ac_cv_c_bigendian+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_c_bigendian=unknown + # See if we're dealing with a universal compiler. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifndef __APPLE_CC__ + not a universal capable compiler + #endif + typedef int dummy; + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + + # Check for potential -arch flags. It is not universal unless + # there are at least two -arch flags with different values. + ac_arch= + ac_prev= + for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do + if test -n "$ac_prev"; then + case $ac_word in + i?86 | x86_64 | ppc | ppc64) + if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then + ac_arch=$ac_word + else + ac_cv_c_bigendian=universal + break + fi + ;; + esac + ac_prev= + elif test "x$ac_word" = "x-arch"; then + ac_prev=arch + fi + done +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test $ac_cv_c_bigendian = unknown; then + # See if sys/param.h defines the BYTE_ORDER macro. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \ + && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \ + && LITTLE_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if BYTE_ORDER != BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # See if defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris). + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to _BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#ifndef _BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # Compile a test program. + if test "$cross_compiling" = yes; then : + # Try to guess by grepping values from an object file. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +short int ascii_mm[] = + { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; + short int ascii_ii[] = + { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; + int use_ascii (int i) { + return ascii_mm[i] + ascii_ii[i]; + } + short int ebcdic_ii[] = + { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; + short int ebcdic_mm[] = + { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; + int use_ebcdic (int i) { + return ebcdic_mm[i] + ebcdic_ii[i]; + } + extern int foo; + +int +main () +{ +return use_ascii (foo) == use_ebcdic (foo); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then + ac_cv_c_bigendian=yes + fi + if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then + if test "$ac_cv_c_bigendian" = unknown; then + ac_cv_c_bigendian=no + else + # finding both strings is unlikely to happen, but who knows? + ac_cv_c_bigendian=unknown + fi + fi +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Are we little or big endian? From Harbison&Steele. */ + union + { + long int l; + char c[sizeof (long int)]; + } u; + u.l = 1; + return u.c[sizeof (long int) - 1] == 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_c_bigendian=no +else + ac_cv_c_bigendian=yes +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 +$as_echo "$ac_cv_c_bigendian" >&6; } + case $ac_cv_c_bigendian in #( + yes) + $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h +;; #( + no) + ;; #( + universal) + +$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h + + ;; #( + *) + as_fn_error "unknown endianness + presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;; + esac + + + + +ac_config_headers="$ac_config_headers config.h:config.in" + + + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Don't build the shared library for build. +if [ -n "${with_build_subdir}" ]; then + enable_shared=no +fi + +frag= +case "${host}" in + rs6000-ibm-aix3.1 | rs6000-ibm-aix) + frag=mh-aix ;; + *-*-cxux7*) frag=mh-cxux7 ;; + *-*-freebsd2.1.*) frag=mh-fbsd21 ;; + *-*-freebsd2.2.[012]) frag=mh-fbsd21 ;; + i370-*-opened*) frag=mh-openedition ;; + i[34567]86-*-windows*) frag=mh-windows ;; +esac + +if [ -n "${frag}" ]; then + frag=${libiberty_topdir}/libiberty/config/$frag +fi + +# If they didn't specify --enable-shared, don't generate shared libs. +case "${enable_shared}" in + yes) shared=yes ;; + no) shared=no ;; + "") shared=no ;; + *) shared=yes ;; +esac +if [ "${shared}" = "yes" ]; then + case "${host}" in + *-*-cygwin*) ;; + alpha*-*-linux*) PICFLAG=-fPIC ;; + arm*-*-*) PICFLAG=-fPIC ;; + hppa*-*-*) PICFLAG=-fPIC ;; + i370-*-*) PICFLAG=-fPIC ;; + ia64-*-*) PICFLAG=-fpic ;; + i[34567]86-*-* | x86_64-*-*) + PICFLAG=-fpic ;; + m68k-*-*) PICFLAG=-fpic ;; + mips*-*-linux*) PICFLAG=-fPIC ;; + powerpc*-*-aix*) ;; + powerpc*-*-*) PICFLAG=-fPIC ;; + sparc*-*-*) case "${CFLAGS}" in + *-fpic* ) PICFLAG=-fpic ;; + * ) PICFLAG=-fPIC ;; + esac ;; + s390*-*-*) PICFLAG=-fpic ;; + sh*-*-*) PICFLAG=-fPIC ;; + esac +fi + + +echo "# Warning: this fragment is automatically generated" > temp-frag + +if [ -n "${frag}" ] && [ -f "${frag}" ]; then + echo "Appending ${frag} to xhost-mkfrag" + echo "# Following fragment copied from ${frag}" >> temp-frag + cat ${frag} >> temp-frag +fi + +# record if we want to build shared libs. +if [ "${shared}" = "yes" ]; then + echo enable_shared = yes >> temp-frag +else + echo enable_shared = no >> temp-frag +fi + +frag=xhost-mkfrag +${CONFIG_SHELL-/bin/sh} ${libiberty_topdir}/move-if-change temp-frag xhost-mkfrag + +host_makefile_frag=${frag} + + +# It's OK to check for header files. Although the compiler may not be +# able to link anything, it had better be able to at least compile +# something. +for ac_header in sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h sys/prctl.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_preproc "$LINENO" "$ac_header" "$as_ac_Header" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for sys/wait.h that is POSIX.1 compatible" >&5 +$as_echo_n "checking for sys/wait.h that is POSIX.1 compatible... " >&6; } +if test "${ac_cv_header_sys_wait_h+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#ifndef WEXITSTATUS +# define WEXITSTATUS(stat_val) ((unsigned int) (stat_val) >> 8) +#endif +#ifndef WIFEXITED +# define WIFEXITED(stat_val) (((stat_val) & 255) == 0) +#endif + +int +main () +{ + int s; + wait (&s); + s = WIFEXITED (s) ? WEXITSTATUS (s) : 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_sys_wait_h=yes +else + ac_cv_header_sys_wait_h=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_sys_wait_h" >&5 +$as_echo "$ac_cv_header_sys_wait_h" >&6; } +if test $ac_cv_header_sys_wait_h = yes; then + +$as_echo "#define HAVE_SYS_WAIT_H 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether time.h and sys/time.h may both be included" >&5 +$as_echo_n "checking whether time.h and sys/time.h may both be included... " >&6; } +if test "${ac_cv_header_time+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include + +int +main () +{ +if ((struct tm *) 0) +return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_time=yes +else + ac_cv_header_time=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_time" >&5 +$as_echo "$ac_cv_header_time" >&6; } +if test $ac_cv_header_time = yes; then + +$as_echo "#define TIME_WITH_SYS_TIME 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether errno must be declared" >&5 +$as_echo_n "checking whether errno must be declared... " >&6; } +if test "${libiberty_cv_declare_errno+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +int x = errno; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + libiberty_cv_declare_errno=no +else + libiberty_cv_declare_errno=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libiberty_cv_declare_errno" >&5 +$as_echo "$libiberty_cv_declare_errno" >&6; } +if test $libiberty_cv_declare_errno = yes +then +$as_echo "#define NEED_DECLARATION_ERRNO 1" >>confdefs.h + +fi + + +# Determine the size of an int for struct fibnode. +# The cast to long int works around a bug in the HP C Compiler +# version HP92453-01 B.11.11.23709.GP, which incorrectly rejects +# declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'. +# This bug is HP SR number 8606223364. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking size of int" >&5 +$as_echo_n "checking size of int... " >&6; } +if test "${ac_cv_sizeof_int+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if ac_fn_c_compute_int "$LINENO" "(long int) (sizeof (int))" "ac_cv_sizeof_int" "$ac_includes_default"; then : + +else + if test "$ac_cv_type_int" = yes; then + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "cannot compute sizeof (int) +See \`config.log' for more details." "$LINENO" 5; }; } + else + ac_cv_sizeof_int=0 + fi +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sizeof_int" >&5 +$as_echo "$ac_cv_sizeof_int" >&6; } + + + +cat >>confdefs.h <<_ACEOF +#define SIZEOF_INT $ac_cv_sizeof_int +_ACEOF + + + +# Look for a 64-bit type. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a 64-bit type" >&5 +$as_echo_n "checking for a 64-bit type... " >&6; } +if test "${liberty_cv_uint64+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef HAVE_STDINT_H +#include +#endif +int +main () +{ +extern uint64_t foo; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + liberty_cv_uint64=uint64_t +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef HAVE_LIMITS_H +#include +#endif +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif +int +main () +{ +extern char foo[sizeof(long) * CHAR_BIT >= 64 ? 1 : -1]; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + liberty_cv_uint64="unsigned long" +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef HAVE_LIMITS_H +#include +#endif +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif +int +main () +{ +extern char foo[sizeof(long long) * CHAR_BIT >= 64 ? 1 : -1]; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + liberty_cv_uint64="unsigned long long" +else + liberty_cv_uint64=none +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $liberty_cv_uint64" >&5 +$as_echo "$liberty_cv_uint64" >&6; } +if test "$liberty_cv_uint64" != none; then + +cat >>confdefs.h <<_ACEOF +#define UNSIGNED_64BIT_TYPE $liberty_cv_uint64 +_ACEOF + +fi + + + ac_fn_c_check_type "$LINENO" "intptr_t" "ac_cv_type_intptr_t" "$ac_includes_default" +if test "x$ac_cv_type_intptr_t" = x""yes; then : + +$as_echo "#define HAVE_INTPTR_T 1" >>confdefs.h + +else + for ac_type in 'int' 'long int' 'long long int'; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ +static int test_array [1 - 2 * !(sizeof (void *) <= sizeof ($ac_type))]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +cat >>confdefs.h <<_ACEOF +#define intptr_t $ac_type +_ACEOF + + ac_type= +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + test -z "$ac_type" && break + done +fi + + + + ac_fn_c_check_type "$LINENO" "uintptr_t" "ac_cv_type_uintptr_t" "$ac_includes_default" +if test "x$ac_cv_type_uintptr_t" = x""yes; then : + +$as_echo "#define HAVE_UINTPTR_T 1" >>confdefs.h + +else + for ac_type in 'unsigned int' 'unsigned long int' \ + 'unsigned long long int'; do + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ +static int test_array [1 - 2 * !(sizeof (void *) <= sizeof ($ac_type))]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +cat >>confdefs.h <<_ACEOF +#define uintptr_t $ac_type +_ACEOF + + ac_type= +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + test -z "$ac_type" && break + done +fi + + +ac_fn_c_check_type "$LINENO" "ssize_t" "ac_cv_type_ssize_t" "$ac_includes_default" +if test "x$ac_cv_type_ssize_t" = x""yes; then : + +else + +cat >>confdefs.h <<_ACEOF +#define ssize_t int +_ACEOF + +fi + + +# Given the above check, we always have uintptr_t or a fallback +# definition. So define HAVE_UINTPTR_T in case any imported code +# relies on it. + +$as_echo "#define HAVE_UINTPTR_T 1" >>confdefs.h + + +ac_fn_c_check_type "$LINENO" "pid_t" "ac_cv_type_pid_t" "$ac_includes_default" +if test "x$ac_cv_type_pid_t" = x""yes; then : + +else + +cat >>confdefs.h <<_ACEOF +#define pid_t int +_ACEOF + +fi + + +# This is the list of functions which libiberty will provide if they +# are not available on the host. + +funcs="asprintf" +funcs="$funcs atexit" +funcs="$funcs basename" +funcs="$funcs bcmp" +funcs="$funcs bcopy" +funcs="$funcs bsearch" +funcs="$funcs bzero" +funcs="$funcs calloc" +funcs="$funcs clock" +funcs="$funcs ffs" +funcs="$funcs getcwd" +funcs="$funcs getpagesize" +funcs="$funcs gettimeofday" +funcs="$funcs index" +funcs="$funcs insque" +funcs="$funcs memchr" +funcs="$funcs memcmp" +funcs="$funcs memcpy" +funcs="$funcs memmem" +funcs="$funcs memmove" +funcs="$funcs mempcpy" +funcs="$funcs memset" +funcs="$funcs mkstemps" +funcs="$funcs putenv" +funcs="$funcs random" +funcs="$funcs rename" +funcs="$funcs rindex" +funcs="$funcs setenv" +funcs="$funcs snprintf" +funcs="$funcs sigsetmask" +funcs="$funcs stpcpy" +funcs="$funcs stpncpy" +funcs="$funcs strcasecmp" +funcs="$funcs strchr" +funcs="$funcs strdup" +funcs="$funcs strncasecmp" +funcs="$funcs strndup" +funcs="$funcs strrchr" +funcs="$funcs strstr" +funcs="$funcs strtod" +funcs="$funcs strtol" +funcs="$funcs strtoul" +funcs="$funcs strverscmp" +funcs="$funcs tmpnam" +funcs="$funcs vasprintf" +funcs="$funcs vfprintf" +funcs="$funcs vprintf" +funcs="$funcs vsnprintf" +funcs="$funcs vsprintf" +funcs="$funcs waitpid" +funcs="$funcs setproctitle" + +# Also in the old function.def file: alloca, vfork, getopt. + +vars="sys_errlist sys_nerr sys_siglist" + +checkfuncs="__fsetlocking canonicalize_file_name dup3 getrusage getsysinfo \ + gettimeofday on_exit psignal pstat_getdynamic pstat_getstatic realpath \ + sbrk spawnve spawnvpe strerror strsignal sysconf sysctl sysmp table \ + times wait3 wait4" + +# These are neither executed nor required, but they help keep +# autoheader happy without adding a bunch of text to acconfig.h. +if test "x" = "y"; then + for ac_func in asprintf atexit \ + basename bcmp bcopy bsearch bzero \ + calloc canonicalize_file_name clock \ + dup3 \ + ffs __fsetlocking \ + getcwd getpagesize getrusage getsysinfo gettimeofday \ + index insque \ + memchr memcmp memcpy memmem memmove memset mkstemps \ + on_exit \ + psignal pstat_getdynamic pstat_getstatic putenv \ + random realpath rename rindex \ + sbrk setenv setproctitle sigsetmask snprintf spawnve spawnvpe \ + stpcpy stpncpy strcasecmp strchr strdup \ + strerror strncasecmp strndup strrchr strsignal strstr strtod strtol \ + strtoul strverscmp sysconf sysctl sysmp \ + table times tmpnam \ + vasprintf vfprintf vprintf vsprintf \ + wait3 wait4 waitpid +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + ac_fn_c_check_decl "$LINENO" "basename(char *)" "ac_cv_have_decl_basename_char_p_" "$ac_includes_default" +if test "x$ac_cv_have_decl_basename_char_p_" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_BASENAME $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "ffs" "ac_cv_have_decl_ffs" "$ac_includes_default" +if test "x$ac_cv_have_decl_ffs" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_FFS $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "asprintf" "ac_cv_have_decl_asprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_asprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_ASPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "vasprintf" "ac_cv_have_decl_vasprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_vasprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_VASPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "snprintf" "ac_cv_have_decl_snprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_snprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_SNPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "vsnprintf" "ac_cv_have_decl_vsnprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_vsnprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_VSNPRINTF $ac_have_decl +_ACEOF + + +$as_echo "#define HAVE_SYS_ERRLIST 1" >>confdefs.h + + +$as_echo "#define HAVE_SYS_NERR 1" >>confdefs.h + + +$as_echo "#define HAVE_SYS_SIGLIST 1" >>confdefs.h + +fi + +# For each of these functions, if the host does not provide the +# function we want to put FN.o in LIBOBJS, and if the host does +# provide the function, we want to define HAVE_FN in config.h. + +setobjs= +CHECK= +target_header_dir= +if test -n "${with_target_subdir}"; then + + # We are being configured as a target library. AC_REPLACE_FUNCS + # may not work correctly, because the compiler may not be able to + # link executables. Note that we may still be being configured + # native. + + # If we are being configured for newlib, we know which functions + # newlib provide and which ones we will be expected to provide. + + if test "x${with_newlib}" = "xyes"; then + case " $LIBOBJS " in + *" asprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS asprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" basename.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS basename.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" insque.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS insque.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strdup.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strdup.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + ;; +esac + + + for f in $funcs; do + case "$f" in + asprintf | basename | insque | random | strdup | vasprintf) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >>confdefs.h <<_ACEOF +#define $n 1 +_ACEOF + + ;; + esac + done + + # newlib doesnt provide any of the variables in $vars, so we + # dont have to check them here. + + # Of the functions in $checkfuncs, newlib only has strerror. + $as_echo "#define HAVE_STRERROR 1" >>confdefs.h + + + setobjs=yes + + fi + + # If we are being configured for Mingw, we know which functions + # Mingw provides and which ones we will be expected to provide. + + case "${host}" in + *-*-mingw*) + case " $LIBOBJS " in + *" asprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS asprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" basename.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS basename.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" bcmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS bcmp.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" bcopy.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS bcopy.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" bzero.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS bzero.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" clock.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS clock.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" ffs.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS ffs.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" getpagesize.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS getpagesize.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" index.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS index.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" insque.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS insque.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" mempcpy.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS mempcpy.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" mkstemps.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS mkstemps.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" rindex.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS rindex.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" sigsetmask.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS sigsetmask.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" stpcpy.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS stpcpy.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" stpncpy.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS stpncpy.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strndup.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strndup.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strverscmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strverscmp.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" waitpid.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS waitpid.$ac_objext" + ;; +esac + + + for f in $funcs; do + case "$f" in + asprintf | basename | bcmp | bcopy | bzero | clock | ffs | getpagesize | index | insque | mempcpy | mkstemps | random | rindex | sigsetmask | stpcpy | stpncpy | strdup | strndup | strverscmp | vasprintf | waitpid) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >>confdefs.h <<_ACEOF +#define $n 1 +_ACEOF + + ;; + esac + done + + # Mingw doesnt provide any of the variables in $vars, so we + # dont have to check them here. + + # Of the functions in $checkfuncs, Mingw only has strerror. + $as_echo "#define HAVE_STRERROR 1" >>confdefs.h + + + setobjs=yes + ;; + + *-*-msdosdjgpp) + case " $LIBOBJS " in + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" vsnprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vsnprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" snprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS snprintf.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" asprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS asprintf.$ac_objext" + ;; +esac + + + for f in atexit basename bcmp bcopy bsearch bzero calloc clock ffs \ + getcwd getpagesize getrusage gettimeofday \ + index insque memchr memcmp memcpy memmove memset psignal \ + putenv random rename rindex sbrk setenv stpcpy strcasecmp \ + strchr strdup strerror strncasecmp strrchr strstr strtod \ + strtol strtoul sysconf times tmpnam vfprintf vprintf \ + vsprintf waitpid + do + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >>confdefs.h <<_ACEOF +#define $n 1 +_ACEOF + + done + + + setobjs=yes + ;; + + esac + + # We may wish to install the target headers somewhere. + # Check whether --enable-install-libiberty was given. +if test "${enable_install_libiberty+set}" = set; then : + enableval=$enable_install_libiberty; enable_install_libiberty=$enableval +else + enable_install_libiberty=no +fi + + # Option parsed, now set things appropriately. + case x"$enable_install_libiberty" in + xyes|x) + target_header_dir=libiberty + ;; + xno) + target_header_dir= + ;; + *) + # This could be sanity-checked in various ways... + target_header_dir="${enable_install_libiberty}" + ;; + esac + + +else + + # Not a target library, so we set things up to run the test suite. + CHECK=really-check + +fi + + + + +case "${host}" in + *-*-cygwin* | *-*-mingw*) + $as_echo "#define HAVE_SYS_ERRLIST 1" >>confdefs.h + + $as_echo "#define HAVE_SYS_NERR 1" >>confdefs.h + + ;; +esac + +if test -z "${setobjs}"; then + case "${host}" in + + *-*-vxworks*) + # Handle VxWorks configuration specially, since on VxWorks the + # libraries are actually on the target board, not in the file + # system. + case " $LIBOBJS " in + *" basename.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS basename.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" getpagesize.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS getpagesize.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" insque.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS insque.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strcasecmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strcasecmp.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strncasecmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strncasecmp.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" strdup.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strdup.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" vfork.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vfork.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" waitpid.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS waitpid.$ac_objext" + ;; +esac + + case " $LIBOBJS " in + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + ;; +esac + + for f in $funcs; do + case "$f" in + basename | getpagesize | insque | random | strcasecmp) + ;; + strncasecmp | strdup | vfork | waitpid | vasprintf) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >>confdefs.h <<_ACEOF +#define $n 1 +_ACEOF + + ;; + esac + done + + # VxWorks doesn't provide any of the variables in $vars, so we + # don't have to check them here. + + # Of the functions in $checkfuncs, VxWorks only has strerror. + $as_echo "#define HAVE_STRERROR 1" >>confdefs.h + + + setobjs=yes + ;; + + esac +fi + +if test -z "${setobjs}"; then + + case "${host}" in + + *-*-mingw32*) + # Under mingw32, sys_nerr and sys_errlist exist, but they are + # macros, so the test below won't find them. + libiberty_cv_var_sys_nerr=yes + libiberty_cv_var_sys_errlist=yes + ;; + + *-*-msdosdjgpp*) + # vfork and fork are stubs. + ac_cv_func_vfork_works=no + ;; + + *-*-uwin*) + # Under some versions of uwin, vfork is notoriously buggy and the test + # can hang configure; on other versions, vfork exists just as a stub. + # FIXME: This should be removed once vfork in uwin's runtime is fixed. + ac_cv_func_vfork_works=no + # Under uwin 2.0+, sys_nerr and sys_errlist exist, but they are + # macros (actually, these are imported from a DLL, but the end effect + # is the same), so the test below won't find them. + libiberty_cv_var_sys_nerr=yes + libiberty_cv_var_sys_errlist=yes + ;; + + *-*-*vms*) + # Under VMS, vfork works very different than on Unix. The standard test + # won't work, and it isn't easily adaptable. It makes more sense to + # just force it. + ac_cv_func_vfork_works=yes + ;; + + esac + + # We haven't set the list of objects yet. Use the standard autoconf + # tests. This will only work if the compiler works. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing strerror" >&5 +$as_echo_n "checking for library containing strerror... " >&6; } +if test "${ac_cv_search_strerror+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char strerror (); +int +main () +{ +return strerror (); + ; + return 0; +} +_ACEOF +for ac_lib in '' cposix; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if test x$gcc_no_link = xyes; then + as_fn_error "Link tests are not allowed after GCC_NO_EXECUTABLES." "$LINENO" 5 +fi +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_strerror=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_strerror+set}" = set; then : + break +fi +done +if test "${ac_cv_search_strerror+set}" = set; then : + +else + ac_cv_search_strerror=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_strerror" >&5 +$as_echo "$ac_cv_search_strerror" >&6; } +ac_res=$ac_cv_search_strerror +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + + for ac_func in $funcs +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +else + case " $LIBOBJS " in + *" $ac_func.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS $ac_func.$ac_objext" + ;; +esac + +fi +done + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether alloca needs Cray hooks" >&5 +$as_echo_n "checking whether alloca needs Cray hooks... " >&6; } +if test "${ac_cv_os_cray+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#if defined(CRAY) && ! defined(CRAY2) +webecray +#else +wenotbecray +#endif + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "webecray" >/dev/null 2>&1; then : + ac_cv_os_cray=yes +else + ac_cv_os_cray=no +fi +rm -f conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_os_cray" >&5 +$as_echo "$ac_cv_os_cray" >&6; } +if test $ac_cv_os_cray = yes; then + for ac_func in _getb67 GETB67 getb67; do + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define CRAY_STACKSEG_END $ac_func +_ACEOF + break +fi + + done +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking stack direction for C alloca" >&5 +$as_echo_n "checking stack direction for C alloca... " >&6; } +if test "${ac_cv_c_stack_direction+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_c_stack_direction=0 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +find_stack_direction () +{ + static char *addr = 0; + auto char dummy; + if (addr == 0) + { + addr = &dummy; + return find_stack_direction (); + } + else + return (&dummy > addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_c_stack_direction=1 +else + ac_cv_c_stack_direction=-1 +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_stack_direction" >&5 +$as_echo "$ac_cv_c_stack_direction" >&6; } + +cat >>confdefs.h <<_ACEOF +#define STACK_DIRECTION $ac_cv_c_stack_direction +_ACEOF + + + for ac_header in vfork.h +do : + ac_fn_c_check_header_preproc "$LINENO" "vfork.h" "ac_cv_header_vfork_h" +if test "x$ac_cv_header_vfork_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_VFORK_H 1 +_ACEOF + +fi +done + +for ac_func in fork vfork +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +if test "x$ac_cv_func_fork" = xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for working fork" >&5 +$as_echo_n "checking for working fork... " >&6; } +if test "${ac_cv_func_fork_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_func_fork_works=cross +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* By Ruediger Kuhlmann. */ + return fork () < 0; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_func_fork_works=yes +else + ac_cv_func_fork_works=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_fork_works" >&5 +$as_echo "$ac_cv_func_fork_works" >&6; } + +else + ac_cv_func_fork_works=$ac_cv_func_fork +fi +if test "x$ac_cv_func_fork_works" = xcross; then + case $host in + *-*-amigaos* | *-*-msdosdjgpp*) + # Override, as these systems have only a dummy fork() stub + ac_cv_func_fork_works=no + ;; + *) + ac_cv_func_fork_works=yes + ;; + esac + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: result $ac_cv_func_fork_works guessed because of cross compilation" >&5 +$as_echo "$as_me: WARNING: result $ac_cv_func_fork_works guessed because of cross compilation" >&2;} +fi +ac_cv_func_vfork_works=$ac_cv_func_vfork +if test "x$ac_cv_func_vfork" = xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for working vfork" >&5 +$as_echo_n "checking for working vfork... " >&6; } +if test "${ac_cv_func_vfork_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_func_vfork_works=cross +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +/* Thanks to Paul Eggert for this test. */ +$ac_includes_default +#include +#ifdef HAVE_VFORK_H +# include +#endif +/* On some sparc systems, changes by the child to local and incoming + argument registers are propagated back to the parent. The compiler + is told about this with #include , but some compilers + (e.g. gcc -O) don't grok . Test for this by using a + static variable whose address is put into a register that is + clobbered by the vfork. */ +static void +#ifdef __cplusplus +sparc_address_test (int arg) +# else +sparc_address_test (arg) int arg; +#endif +{ + static pid_t child; + if (!child) { + child = vfork (); + if (child < 0) { + perror ("vfork"); + _exit(2); + } + if (!child) { + arg = getpid(); + write(-1, "", 0); + _exit (arg); + } + } +} + +int +main () +{ + pid_t parent = getpid (); + pid_t child; + + sparc_address_test (0); + + child = vfork (); + + if (child == 0) { + /* Here is another test for sparc vfork register problems. This + test uses lots of local variables, at least as many local + variables as main has allocated so far including compiler + temporaries. 4 locals are enough for gcc 1.40.3 on a Solaris + 4.1.3 sparc, but we use 8 to be safe. A buggy compiler should + reuse the register of parent for one of the local variables, + since it will think that parent can't possibly be used any more + in this routine. Assigning to the local variable will thus + munge parent in the parent process. */ + pid_t + p = getpid(), p1 = getpid(), p2 = getpid(), p3 = getpid(), + p4 = getpid(), p5 = getpid(), p6 = getpid(), p7 = getpid(); + /* Convince the compiler that p..p7 are live; otherwise, it might + use the same hardware register for all 8 local variables. */ + if (p != p1 || p != p2 || p != p3 || p != p4 + || p != p5 || p != p6 || p != p7) + _exit(1); + + /* On some systems (e.g. IRIX 3.3), vfork doesn't separate parent + from child file descriptors. If the child closes a descriptor + before it execs or exits, this munges the parent's descriptor + as well. Test for this by closing stdout in the child. */ + _exit(close(fileno(stdout)) != 0); + } else { + int status; + struct stat st; + + while (wait(&status) != child) + ; + return ( + /* Was there some problem with vforking? */ + child < 0 + + /* Did the child fail? (This shouldn't happen.) */ + || status + + /* Did the vfork/compiler bug occur? */ + || parent != getpid() + + /* Did the file descriptor bug occur? */ + || fstat(fileno(stdout), &st) != 0 + ); + } +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_func_vfork_works=yes +else + ac_cv_func_vfork_works=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_vfork_works" >&5 +$as_echo "$ac_cv_func_vfork_works" >&6; } + +fi; +if test "x$ac_cv_func_fork_works" = xcross; then + ac_cv_func_vfork_works=$ac_cv_func_vfork + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&5 +$as_echo "$as_me: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&2;} +fi + +if test "x$ac_cv_func_vfork_works" = xyes; then + +$as_echo "#define HAVE_WORKING_VFORK 1" >>confdefs.h + +else + +$as_echo "#define vfork fork" >>confdefs.h + +fi +if test "x$ac_cv_func_fork_works" = xyes; then + +$as_echo "#define HAVE_WORKING_FORK 1" >>confdefs.h + +fi + + if test $ac_cv_func_vfork_works = no; then + case " $LIBOBJS " in + *" vfork.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vfork.$ac_objext" + ;; +esac + + fi + # We only need _doprnt if we might use it to implement v*printf. + if test $ac_cv_func_vprintf != yes \ + || test $ac_cv_func_vfprintf != yes \ + || test $ac_cv_func_vsprintf != yes; then + for ac_func in _doprnt +do : + ac_fn_c_check_func "$LINENO" "_doprnt" "ac_cv_func__doprnt" +if test "x$ac_cv_func__doprnt" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE__DOPRNT 1 +_ACEOF + +else + case " $LIBOBJS " in + *" $ac_func.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS $ac_func.$ac_objext" + ;; +esac + +fi +done + + + else + for ac_func in _doprnt +do : + ac_fn_c_check_func "$LINENO" "_doprnt" "ac_cv_func__doprnt" +if test "x$ac_cv_func__doprnt" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE__DOPRNT 1 +_ACEOF + +fi +done + + fi + + for v in $vars; do + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $v" >&5 +$as_echo_n "checking for $v... " >&6; } + if { as_var=libiberty_cv_var_$v; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + if test x$gcc_no_link = xyes; then + as_fn_error "Link tests are not allowed after GCC_NO_EXECUTABLES." "$LINENO" 5 +fi +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +int *p; +int +main () +{ +extern int $v []; p = $v; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "libiberty_cv_var_$v=yes" +else + eval "libiberty_cv_var_$v=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi + + if eval "test \"`echo '$libiberty_cv_var_'$v`\" = yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + n=HAVE_`echo $v | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >>confdefs.h <<_ACEOF +#define $n 1 +_ACEOF + + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + fi + done + + # special check for _system_configuration because AIX <4.3.2 do not + # contain the `physmem' member. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for external symbol _system_configuration" >&5 +$as_echo_n "checking for external symbol _system_configuration... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +double x = _system_configuration.physmem; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define HAVE__SYSTEM_CONFIGURATION 1" >>confdefs.h + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + + for ac_func in $checkfuncs +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + ac_fn_c_check_decl "$LINENO" "basename(char *)" "ac_cv_have_decl_basename_char_p_" "$ac_includes_default" +if test "x$ac_cv_have_decl_basename_char_p_" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_BASENAME $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "ffs" "ac_cv_have_decl_ffs" "$ac_includes_default" +if test "x$ac_cv_have_decl_ffs" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_FFS $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "asprintf" "ac_cv_have_decl_asprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_asprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_ASPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "vasprintf" "ac_cv_have_decl_vasprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_vasprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_VASPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "snprintf" "ac_cv_have_decl_snprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_snprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_SNPRINTF $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "vsnprintf" "ac_cv_have_decl_vsnprintf" "$ac_includes_default" +if test "x$ac_cv_have_decl_vsnprintf" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_VSNPRINTF $ac_have_decl +_ACEOF + + ac_fn_c_check_decl "$LINENO" "calloc" "ac_cv_have_decl_calloc" "$ac_includes_default" +if test "x$ac_cv_have_decl_calloc" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_CALLOC $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "getenv" "ac_cv_have_decl_getenv" "$ac_includes_default" +if test "x$ac_cv_have_decl_getenv" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_GETENV $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "getopt" "ac_cv_have_decl_getopt" "$ac_includes_default" +if test "x$ac_cv_have_decl_getopt" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_GETOPT $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "malloc" "ac_cv_have_decl_malloc" "$ac_includes_default" +if test "x$ac_cv_have_decl_malloc" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_MALLOC $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "realloc" "ac_cv_have_decl_realloc" "$ac_includes_default" +if test "x$ac_cv_have_decl_realloc" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_REALLOC $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "sbrk" "ac_cv_have_decl_sbrk" "$ac_includes_default" +if test "x$ac_cv_have_decl_sbrk" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_SBRK $ac_have_decl +_ACEOF + + ac_fn_c_check_decl "$LINENO" "strverscmp" "ac_cv_have_decl_strverscmp" "$ac_includes_default" +if test "x$ac_cv_have_decl_strverscmp" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_STRVERSCMP $ac_have_decl +_ACEOF + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether canonicalize_file_name must be declared" >&5 +$as_echo_n "checking whether canonicalize_file_name must be declared... " >&6; } +if test "${libiberty_cv_decl_needed_canonicalize_file_name+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include "confdefs.h" +#include +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +int +main () +{ +char *(*pfn) = (char *(*)) canonicalize_file_name + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + libiberty_cv_decl_needed_canonicalize_file_name=no +else + libiberty_cv_decl_needed_canonicalize_file_name=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libiberty_cv_decl_needed_canonicalize_file_name" >&5 +$as_echo "$libiberty_cv_decl_needed_canonicalize_file_name" >&6; } +if test $libiberty_cv_decl_needed_canonicalize_file_name = yes; then + +$as_echo "#define NEED_DECLARATION_CANONICALIZE_FILE_NAME 1" >>confdefs.h + +fi + +fi + +# Figure out which version of pexecute to use. +case "${host}" in + *-*-mingw* | *-*-winnt*) pexecute=pex-win32 ;; + *-*-msdosdjgpp*) pexecute=pex-djgpp ;; + *-*-msdos*) pexecute=pex-msdos ;; + *) pexecute=pex-unix ;; +esac + + +if test x$gcc_no_link = xyes; then + if test "x${ac_cv_func_mmap_fixed_mapped+set}" != xset; then + ac_cv_func_mmap_fixed_mapped=no + fi +fi +if test "x${ac_cv_func_mmap_fixed_mapped}" != xno; then + for ac_header in stdlib.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_preproc "$LINENO" "$ac_header" "$as_ac_Header" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +for ac_func in getpagesize +do : + ac_fn_c_check_func "$LINENO" "getpagesize" "ac_cv_func_getpagesize" +if test "x$ac_cv_func_getpagesize" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_GETPAGESIZE 1 +_ACEOF + +fi +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for working mmap" >&5 +$as_echo_n "checking for working mmap... " >&6; } +if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_func_mmap_fixed_mapped=no +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +/* malloc might have been renamed as rpl_malloc. */ +#undef malloc + +/* Thanks to Mike Haertel and Jim Avera for this test. + Here is a matrix of mmap possibilities: + mmap private not fixed + mmap private fixed at somewhere currently unmapped + mmap private fixed at somewhere already mapped + mmap shared not fixed + mmap shared fixed at somewhere currently unmapped + mmap shared fixed at somewhere already mapped + For private mappings, we should verify that changes cannot be read() + back from the file, nor mmap's back from the file at a different + address. (There have been systems where private was not correctly + implemented like the infamous i386 svr4.0, and systems where the + VM page cache was not coherent with the file system buffer cache + like early versions of FreeBSD and possibly contemporary NetBSD.) + For shared mappings, we should conversely verify that changes get + propagated back to all the places they're supposed to be. + + Grep wants private fixed already mapped. + The main things grep needs to know about mmap are: + * does it exist and is it safe to write into the mmap'd area + * how to use it (BSD variants) */ + +#include +#include + +#if !defined STDC_HEADERS && !defined HAVE_STDLIB_H +char *malloc (); +#endif + +/* This mess was copied from the GNU getpagesize.h. */ +#ifndef HAVE_GETPAGESIZE +/* Assume that all systems that can run configure have sys/param.h. */ +# ifndef HAVE_SYS_PARAM_H +# define HAVE_SYS_PARAM_H 1 +# endif + +# ifdef _SC_PAGESIZE +# define getpagesize() sysconf(_SC_PAGESIZE) +# else /* no _SC_PAGESIZE */ +# ifdef HAVE_SYS_PARAM_H +# include +# ifdef EXEC_PAGESIZE +# define getpagesize() EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define getpagesize() NBPG * CLSIZE +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* no CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define getpagesize() NBPC +# else /* no NBPC */ +# ifdef PAGESIZE +# define getpagesize() PAGESIZE +# endif /* PAGESIZE */ +# endif /* no NBPC */ +# endif /* no NBPG */ +# endif /* no EXEC_PAGESIZE */ +# else /* no HAVE_SYS_PARAM_H */ +# define getpagesize() 8192 /* punt totally */ +# endif /* no HAVE_SYS_PARAM_H */ +# endif /* no _SC_PAGESIZE */ + +#endif /* no HAVE_GETPAGESIZE */ + +int +main () +{ + char *data, *data2, *data3; + int i, pagesize; + int fd; + + pagesize = getpagesize (); + + /* First, make a file with some known garbage in it. */ + data = (char *) malloc (pagesize); + if (!data) + return 1; + for (i = 0; i < pagesize; ++i) + *(data + i) = rand (); + umask (0); + fd = creat ("conftest.mmap", 0600); + if (fd < 0) + return 1; + if (write (fd, data, pagesize) != pagesize) + return 1; + close (fd); + + /* Next, try to mmap the file at a fixed address which already has + something else allocated at it. If we can, also make sure that + we see the same garbage. */ + fd = open ("conftest.mmap", O_RDWR); + if (fd < 0) + return 1; + data2 = (char *) malloc (2 * pagesize); + if (!data2) + return 1; + data2 += (pagesize - ((long int) data2 & (pagesize - 1))) & (pagesize - 1); + if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_FIXED, fd, 0L)) + return 1; + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data2 + i)) + return 1; + + /* Finally, make sure that changes to the mapped area do not + percolate back to the file as seen by read(). (This is a bug on + some variants of i386 svr4.0.) */ + for (i = 0; i < pagesize; ++i) + *(data2 + i) = *(data2 + i) + 1; + data3 = (char *) malloc (pagesize); + if (!data3) + return 1; + if (read (fd, data3, pagesize) != pagesize) + return 1; + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data3 + i)) + return 1; + close (fd); + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_func_mmap_fixed_mapped=yes +else + ac_cv_func_mmap_fixed_mapped=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_mmap_fixed_mapped" >&5 +$as_echo "$ac_cv_func_mmap_fixed_mapped" >&6; } +if test $ac_cv_func_mmap_fixed_mapped = yes; then + +$as_echo "#define HAVE_MMAP 1" >>confdefs.h + +fi +rm -f conftest.mmap + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for working strncmp" >&5 +$as_echo_n "checking for working strncmp... " >&6; } +if test "${ac_cv_func_strncmp_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_func_strncmp_works=no +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Test by Jim Wilson and Kaveh Ghazi. + Check whether strncmp reads past the end of its string parameters. */ +#include + +#ifdef HAVE_FCNTL_H +#include +#endif + +#ifdef HAVE_SYS_MMAN_H +#include +#endif + +#ifndef MAP_ANON +#ifdef MAP_ANONYMOUS +#define MAP_ANON MAP_ANONYMOUS +#else +#define MAP_ANON MAP_FILE +#endif +#endif + +#ifndef MAP_FILE +#define MAP_FILE 0 +#endif +#ifndef O_RDONLY +#define O_RDONLY 0 +#endif + +#define MAP_LEN 0x10000 + +main () +{ +#if defined(HAVE_MMAP) || defined(HAVE_MMAP_ANYWHERE) + char *p; + int dev_zero; + + dev_zero = open ("/dev/zero", O_RDONLY); + if (dev_zero < 0) + exit (1); + + p = (char *) mmap (0, MAP_LEN, PROT_READ|PROT_WRITE, + MAP_ANON|MAP_PRIVATE, dev_zero, 0); + if (p == (char *)-1) + p = (char *) mmap (0, MAP_LEN, PROT_READ|PROT_WRITE, + MAP_ANON|MAP_PRIVATE, -1, 0); + if (p == (char *)-1) + exit (2); + else + { + char *string = "__si_type_info"; + char *q = (char *) p + MAP_LEN - strlen (string) - 2; + char *r = (char *) p + 0xe; + + strcpy (q, string); + strcpy (r, string); + strncmp (r, q, 14); + } +#endif /* HAVE_MMAP || HAVE_MMAP_ANYWHERE */ + exit (0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_func_strncmp_works=yes +else + ac_cv_func_strncmp_works=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +rm -f core core.* *.core +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_strncmp_works" >&5 +$as_echo "$ac_cv_func_strncmp_works" >&6; } +if test $ac_cv_func_strncmp_works = no ; then + case " $LIBOBJS " in + *" strncmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strncmp.$ac_objext" + ;; +esac + +fi + + +# Install a library built with a cross compiler in $(tooldir) rather +# than $(libdir). +if test -z "${with_cross_host}"; then + INSTALL_DEST=libdir +else + INSTALL_DEST=tooldir +fi + + + +L="" +for l in x $LIBOBJS; do + case $l in + x) ;; + *) L="$L ./$l" ;; + esac +done +LIBOBJS="$L" + + + + + +# We need multilib support, but only if configuring for the target. +ac_config_files="$ac_config_files Makefile testsuite/Makefile" + +ac_config_commands="$ac_config_commands default" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration commands: +$config_commands + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# +# INIT-COMMANDS +# +srcdir=${srcdir} +host=${host} +target=${target} +with_target_subdir=${with_target_subdir} +with_multisubdir=${with_multisubdir} +ac_configure_args="--enable-multilib ${ac_configure_args}" +CONFIG_SHELL=${CONFIG_SHELL-/bin/sh} +ORIGINAL_LD_FOR_MULTILIBS="${ORIGINAL_LD_FOR_MULTILIBS}" +libiberty_topdir=${libiberty_topdir} + + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "testsuite/Makefile") CONFIG_FILES="$CONFIG_FILES testsuite/Makefile" ;; + "default") CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + +if $AWK 'BEGIN { getline <"/dev/null" }' /dev/null; then + ac_cs_awk_getline=: + ac_cs_awk_pipe_init= + ac_cs_awk_read_file=' + while ((getline aline < (F[key])) > 0) + print(aline) + close(F[key])' + ac_cs_awk_pipe_fini= +else + ac_cs_awk_getline=false + ac_cs_awk_pipe_init="print \"cat <<'|#_!!_#|' &&\"" + ac_cs_awk_read_file=' + print "|#_!!_#|" + print "cat " F[key] " &&" + '$ac_cs_awk_pipe_init + # The final `:' finishes the AND list. + ac_cs_awk_pipe_fini='END { print "|#_!!_#|"; print ":" }' +fi +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + +# Create commands to substitute file output variables. +{ + echo "cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1" && + echo 'cat >>"\$tmp/subs1.awk" <<\\_ACAWK &&' && + echo "$ac_subst_files" | sed 's/.*/F["&"]="$&"/' && + echo "_ACAWK" && + echo "_ACEOF" +} >conf$$files.sh && +. ./conf$$files.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +rm -f conf$$files.sh + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + \$ac_cs_awk_pipe_init +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + if (nfields == 3 && !substed) { + key = field[2] + if (F[key] != "" && line ~ /^[ ]*@.*@[ ]*$/) { + \$ac_cs_awk_read_file + next + } + } + print line +} +\$ac_cs_awk_pipe_fini +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. Generated by config.status. */ + configure_input='Generated from '` + $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' + `' by configure.' + if test x"$ac_file" != x-; then + configure_input="$ac_file. $configure_input" + { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 +$as_echo "$as_me: creating $ac_file" >&6;} + fi + # Neutralize special characters interpreted by sed in replacement strings. + case $configure_input in #( + *\&* | *\|* | *\\* ) + ac_sed_conf_input=`$as_echo "$configure_input" | + sed 's/[\\\\&|]/\\\\&/g'`;; #( + *) ac_sed_conf_input=$configure_input;; + esac + + case $ac_tag in + *:-:* | *:-) cat >"$tmp/stdin" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 ;; + esac + ;; + esac + + ac_dir=`$as_dirname -- "$ac_file" || +$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$ac_file" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + as_dir="$ac_dir"; as_fn_mkdir_p + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + + case $ac_mode in + :F) + # + # CONFIG_FILE + # + + case $INSTALL in + [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;; + *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;; + esac +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# If the template does not know about datarootdir, expand it. +# FIXME: This hack should be removed a few years after 2.60. +ac_datarootdir_hack=; ac_datarootdir_seen= +ac_sed_dataroot=' +/datarootdir/ { + p + q +} +/@datadir@/p +/@docdir@/p +/@infodir@/p +/@localedir@/p +/@mandir@/p' +case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in +*datarootdir*) ac_datarootdir_seen=yes;; +*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 +$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_datarootdir_hack=' + s&@datadir@&$datadir&g + s&@docdir@&$docdir&g + s&@infodir@&$infodir&g + s&@localedir@&$localedir&g + s&@mandir@&$mandir&g + s&\\\${datarootdir}&$datarootdir&g' ;; +esac +_ACEOF + +# Neutralize VPATH when `$srcdir' = `.'. +# Shell code in configure.ac might set extrasub. +# FIXME: do we really want to maintain this feature? +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_sed_extra="$ac_vpsub +$extrasub +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +:t +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b +s|@configure_input@|$ac_sed_conf_input|;t t +s&@top_builddir@&$ac_top_builddir_sub&;t t +s&@top_build_prefix@&$ac_top_build_prefix&;t t +s&@srcdir@&$ac_srcdir&;t t +s&@abs_srcdir@&$ac_abs_srcdir&;t t +s&@top_srcdir@&$ac_top_srcdir&;t t +s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t +s&@builddir@&$ac_builddir&;t t +s&@abs_builddir@&$ac_abs_builddir&;t t +s&@abs_top_builddir@&$ac_abs_top_builddir&;t t +s&@INSTALL@&$ac_INSTALL&;t t +$ac_datarootdir_hack +" +eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | +if $ac_cs_awk_getline; then + $AWK -f "$tmp/subs.awk" +else + $AWK -f "$tmp/subs.awk" | $SHELL +fi >$tmp/out \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + +test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && + { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } && + { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } && + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "default":C) test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h +if test -n "$CONFIG_FILES"; then + if test -n "${with_target_subdir}"; then + # FIXME: We shouldn't need to set ac_file + ac_file=Makefile + LD="${ORIGINAL_LD_FOR_MULTILIBS}" + . ${libiberty_topdir}/config-ml.in + fi +fi ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/external/gpl3/gdb/dist/libiberty/configure.ac b/external/gpl3/gdb/dist/libiberty/configure.ac new file mode 100644 index 000000000000..9f1ff04938ec --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/configure.ac @@ -0,0 +1,734 @@ +dnl Process this file with autoconf to produce a configure script + +AC_PREREQ(2.64) +AC_INIT +AC_CONFIG_SRCDIR([xmalloc.c]) + +# This works around the fact that libtool configuration may change LD +# for this particular configuration, but some shells, instead of +# keeping the changes in LD private, export them just because LD is +# exported. We don't use libtool yet, but some day we might, so... +ORIGINAL_LD_FOR_MULTILIBS=$LD + +dnl We use these options to decide which functions to include. +AC_ARG_WITH(target-subdir, +[ --with-target-subdir=SUBDIR Configuring in a subdirectory for target]) +AC_ARG_WITH(build-subdir, +[ --with-build-subdir=SUBDIR Configuring in a subdirectory for build]) +AC_ARG_WITH(cross-host, +[ --with-cross-host=HOST Configuring with a cross compiler]) +AC_ARG_WITH(newlib, +[ --with-newlib Configuring with newlib]) + +if test "${srcdir}" = "."; then + if test -n "${with_build_subdir}"; then + libiberty_topdir="${srcdir}/../.." + with_target_subdir= + elif test -z "${with_target_subdir}"; then + libiberty_topdir="${srcdir}/.." + else + if test "${with_target_subdir}" != "."; then + libiberty_topdir="${srcdir}/${with_multisrctop}../.." + else + libiberty_topdir="${srcdir}/${with_multisrctop}.." + fi + fi +else + libiberty_topdir="${srcdir}/.." +fi +AC_SUBST(libiberty_topdir) +AC_CONFIG_AUX_DIR($libiberty_topdir) + +dnl Very limited version of automake's enable-maintainer-mode + +AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles]) + dnl maintainer-mode is disabled by default + AC_ARG_ENABLE(maintainer-mode, +[ --enable-maintainer-mode + enable make rules and dependencies not useful + (and sometimes confusing) to the casual installer], + maintainer_mode=$enableval, + maintainer_mode=no) + +AC_MSG_RESULT($maintainer_mode) + +if test "$maintainer_mode" = "yes"; then + MAINT='' + NOTMAINT='#' +else + MAINT='#' + NOTMAINT='' +fi +AC_SUBST(MAINT)dnl +AC_SUBST(NOTMAINT)dnl + +# Do we have a single-tree copy of texinfo? Even if we do, we can't +# rely on it - libiberty is built before texinfo. +AC_CHECK_PROG(MAKEINFO, makeinfo, makeinfo, ) +if test "x$MAKEINFO" = "x"; then + MAKEINFO="@echo makeinfo missing; true" + BUILD_INFO= +else + BUILD_INFO=info + case "$MAKEINFO" in + */missing\ makeinfo*) + BUILD_INFO= + AC_MSG_WARN([ +*** Makeinfo is missing. Info documentation will not be built.]) + ;; + *) + case x"`$MAKEINFO --version | grep 'GNU texinfo'`" in + x*\ [[1-3]].* ) + MAKEINFO="@echo $MAKEINFO is too old, 4.0 or newer required; true" + BUILD_INFO= + AC_MSG_WARN([ +*** Makeinfo is too old. Info documentation will not be built.]) + ;; + esac + ;; + esac +fi +AC_SUBST(MAKEINFO) +AC_SUBST(BUILD_INFO) + +AC_CHECK_PROG(PERL, perl, perl, ) +if test x"$PERL" = x""; then + HAVE_PERL='#' +else + HAVE_PERL='' +fi +AC_SUBST(HAVE_PERL) + +AC_CANONICAL_HOST + +dnl When we start using automake: +dnl AM_INIT_AUTOMAKE(libiberty, 1.0) + +dnl These must be called before AM_PROG_LIBTOOL, because it may want +dnl to call AC_CHECK_PROG. +AC_CHECK_TOOL(AR, ar) +AC_CHECK_TOOL(RANLIB, ranlib, :) + +dnl When switching to automake, replace the following with AM_ENABLE_MULTILIB. +# Add --enable-multilib to configure. +# Default to --enable-multilib +AC_ARG_ENABLE(multilib, +[ --enable-multilib build many library versions (default)], +[case "$enableval" in + yes) multilib=yes ;; + no) multilib=no ;; + *) AC_MSG_ERROR([bad value $enableval for multilib option]) ;; + esac], + [multilib=yes]) + +# Even if the default multilib is not a cross compilation, +# it may be that some of the other multilibs are. +if test $cross_compiling = no && test $multilib = yes \ + && test "x${with_multisubdir}" != x ; then + cross_compiling=maybe +fi + +GCC_NO_EXECUTABLES +AC_PROG_CC +AC_SYS_LARGEFILE +AC_PROG_CPP_WERROR + +ACX_PROG_CC_WARNING_OPTS([-W -Wall -Wwrite-strings -Wc++-compat \ + -Wstrict-prototypes], [ac_libiberty_warn_cflags]) +ACX_PROG_CC_WARNING_ALMOST_PEDANTIC([], [ac_libiberty_warn_cflags]) + +AC_PROG_CC_C_O +# autoconf is lame and doesn't give us any substitution variable for this. +if eval "test \"`echo '$ac_cv_prog_cc_'${ac_cc}_c_o`\" = no"; then + NO_MINUS_C_MINUS_O=yes +else + OUTPUT_OPTION='-o $@' +fi +AC_SUBST(NO_MINUS_C_MINUS_O) +AC_SUBST(OUTPUT_OPTION) + +AC_C_CONST +AC_C_INLINE +AC_C_BIGENDIAN + +dnl When we start using libtool: +dnl Default to a non shared library. This may be overridden by the +dnl configure option --enable-shared. +dnl AM_DISABLE_SHARED + +dnl When we start using libtool: +dnl AM_PROG_LIBTOOL + +dnl When we start using automake: +dnl AM_CONFIG_HEADER(config.h:config.in) +AC_CONFIG_HEADER(config.h:config.in) + +dnl When we start using automake: +dnl AM_MAINTAINER_MODE +dnl AC_EXEEXT + +dnl When we start using automake: +dnl AM_PROG_INSTALL +AC_PROG_INSTALL + +# Don't build the shared library for build. +if [[ -n "${with_build_subdir}" ]]; then + enable_shared=no +fi + +frag= +case "${host}" in + rs6000-ibm-aix3.1 | rs6000-ibm-aix) + frag=mh-aix ;; + *-*-cxux7*) frag=mh-cxux7 ;; + *-*-freebsd2.1.*) frag=mh-fbsd21 ;; + *-*-freebsd2.2.[[012]]) frag=mh-fbsd21 ;; + i370-*-opened*) frag=mh-openedition ;; + i[[34567]]86-*-windows*) frag=mh-windows ;; +esac + +if [[ -n "${frag}" ]]; then + frag=${libiberty_topdir}/libiberty/config/$frag +fi + +# If they didn't specify --enable-shared, don't generate shared libs. +case "${enable_shared}" in + yes) shared=yes ;; + no) shared=no ;; + "") shared=no ;; + *) shared=yes ;; +esac +if [[ "${shared}" = "yes" ]]; then + case "${host}" in + *-*-cygwin*) ;; + alpha*-*-linux*) PICFLAG=-fPIC ;; + arm*-*-*) PICFLAG=-fPIC ;; + hppa*-*-*) PICFLAG=-fPIC ;; + i370-*-*) PICFLAG=-fPIC ;; + ia64-*-*) PICFLAG=-fpic ;; + i[[34567]]86-*-* | x86_64-*-*) + PICFLAG=-fpic ;; + m68k-*-*) PICFLAG=-fpic ;; + mips*-*-linux*) PICFLAG=-fPIC ;; + powerpc*-*-aix*) ;; + powerpc*-*-*) PICFLAG=-fPIC ;; + sparc*-*-*) case "${CFLAGS}" in + *-fpic* ) PICFLAG=-fpic ;; + * ) PICFLAG=-fPIC ;; + esac ;; + s390*-*-*) PICFLAG=-fpic ;; + sh*-*-*) PICFLAG=-fPIC ;; + esac +fi +AC_SUBST(PICFLAG) + +echo "# Warning: this fragment is automatically generated" > temp-frag + +if [[ -n "${frag}" ]] && [[ -f "${frag}" ]]; then + echo "Appending ${frag} to xhost-mkfrag" + echo "# Following fragment copied from ${frag}" >> temp-frag + cat ${frag} >> temp-frag +fi + +# record if we want to build shared libs. +if [[ "${shared}" = "yes" ]]; then + echo enable_shared = yes >> temp-frag +else + echo enable_shared = no >> temp-frag +fi + +frag=xhost-mkfrag +${CONFIG_SHELL-/bin/sh} ${libiberty_topdir}/move-if-change temp-frag xhost-mkfrag + +host_makefile_frag=${frag} +AC_SUBST_FILE(host_makefile_frag) + +# It's OK to check for header files. Although the compiler may not be +# able to link anything, it had better be able to at least compile +# something. +AC_CHECK_HEADERS(sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h sys/prctl.h) +AC_HEADER_SYS_WAIT +AC_HEADER_TIME + +libiberty_AC_DECLARE_ERRNO + +# Determine the size of an int for struct fibnode. +AC_CHECK_SIZEOF([int]) + +# Look for a 64-bit type. +AC_MSG_CHECKING([for a 64-bit type]) +AC_CACHE_VAL(liberty_cv_uint64, +[AC_TRY_COMPILE( +[#ifdef HAVE_STDINT_H +#include +#endif], +[extern uint64_t foo;], +liberty_cv_uint64=uint64_t, +[AC_TRY_COMPILE( +[#ifdef HAVE_LIMITS_H +#include +#endif +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif], +[extern char foo[sizeof(long) * CHAR_BIT >= 64 ? 1 : -1];], +liberty_cv_uint64="unsigned long", +[AC_TRY_COMPILE( +[#ifdef HAVE_LIMITS_H +#include +#endif +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif], +[extern char foo[sizeof(long long) * CHAR_BIT >= 64 ? 1 : -1];], +liberty_cv_uint64="unsigned long long", liberty_cv_uint64=none)])])]) +AC_MSG_RESULT($liberty_cv_uint64) +if test "$liberty_cv_uint64" != none; then + AC_DEFINE_UNQUOTED(UNSIGNED_64BIT_TYPE, $liberty_cv_uint64, + [Define to an unsigned 64-bit type available in the compiler.]) +fi + +AC_TYPE_INTPTR_T +AC_TYPE_UINTPTR_T +AC_TYPE_SSIZE_T + +# Given the above check, we always have uintptr_t or a fallback +# definition. So define HAVE_UINTPTR_T in case any imported code +# relies on it. +AC_DEFINE(HAVE_UINTPTR_T, 1, [Define if you have the \`uintptr_t' type.]) + +AC_TYPE_PID_T + +# This is the list of functions which libiberty will provide if they +# are not available on the host. + +funcs="asprintf" +funcs="$funcs atexit" +funcs="$funcs basename" +funcs="$funcs bcmp" +funcs="$funcs bcopy" +funcs="$funcs bsearch" +funcs="$funcs bzero" +funcs="$funcs calloc" +funcs="$funcs clock" +funcs="$funcs ffs" +funcs="$funcs getcwd" +funcs="$funcs getpagesize" +funcs="$funcs gettimeofday" +funcs="$funcs index" +funcs="$funcs insque" +funcs="$funcs memchr" +funcs="$funcs memcmp" +funcs="$funcs memcpy" +funcs="$funcs memmem" +funcs="$funcs memmove" +funcs="$funcs mempcpy" +funcs="$funcs memset" +funcs="$funcs mkstemps" +funcs="$funcs putenv" +funcs="$funcs random" +funcs="$funcs rename" +funcs="$funcs rindex" +funcs="$funcs setenv" +funcs="$funcs snprintf" +funcs="$funcs sigsetmask" +funcs="$funcs stpcpy" +funcs="$funcs stpncpy" +funcs="$funcs strcasecmp" +funcs="$funcs strchr" +funcs="$funcs strdup" +funcs="$funcs strncasecmp" +funcs="$funcs strndup" +funcs="$funcs strrchr" +funcs="$funcs strstr" +funcs="$funcs strtod" +funcs="$funcs strtol" +funcs="$funcs strtoul" +funcs="$funcs strverscmp" +funcs="$funcs tmpnam" +funcs="$funcs vasprintf" +funcs="$funcs vfprintf" +funcs="$funcs vprintf" +funcs="$funcs vsnprintf" +funcs="$funcs vsprintf" +funcs="$funcs waitpid" +funcs="$funcs setproctitle" + +# Also in the old function.def file: alloca, vfork, getopt. + +vars="sys_errlist sys_nerr sys_siglist" + +checkfuncs="__fsetlocking canonicalize_file_name dup3 getrusage getsysinfo \ + gettimeofday on_exit psignal pstat_getdynamic pstat_getstatic realpath \ + sbrk spawnve spawnvpe strerror strsignal sysconf sysctl sysmp table \ + times wait3 wait4" + +# These are neither executed nor required, but they help keep +# autoheader happy without adding a bunch of text to acconfig.h. +if test "x" = "y"; then + AC_CHECK_FUNCS(asprintf atexit \ + basename bcmp bcopy bsearch bzero \ + calloc canonicalize_file_name clock \ + dup3 \ + ffs __fsetlocking \ + getcwd getpagesize getrusage getsysinfo gettimeofday \ + index insque \ + memchr memcmp memcpy memmem memmove memset mkstemps \ + on_exit \ + psignal pstat_getdynamic pstat_getstatic putenv \ + random realpath rename rindex \ + sbrk setenv setproctitle sigsetmask snprintf spawnve spawnvpe \ + stpcpy stpncpy strcasecmp strchr strdup \ + strerror strncasecmp strndup strrchr strsignal strstr strtod strtol \ + strtoul strverscmp sysconf sysctl sysmp \ + table times tmpnam \ + vasprintf vfprintf vprintf vsprintf \ + wait3 wait4 waitpid) + AC_CHECK_DECLS([basename(char *), ffs, asprintf, vasprintf, snprintf, vsnprintf]) + AC_DEFINE(HAVE_SYS_ERRLIST, 1, [Define if you have the sys_errlist variable.]) + AC_DEFINE(HAVE_SYS_NERR, 1, [Define if you have the sys_nerr variable.]) + AC_DEFINE(HAVE_SYS_SIGLIST, 1, [Define if you have the sys_siglist variable.]) +fi + +# For each of these functions, if the host does not provide the +# function we want to put FN.o in LIBOBJS, and if the host does +# provide the function, we want to define HAVE_FN in config.h. + +setobjs= +CHECK= +target_header_dir= +if test -n "${with_target_subdir}"; then + + # We are being configured as a target library. AC_REPLACE_FUNCS + # may not work correctly, because the compiler may not be able to + # link executables. Note that we may still be being configured + # native. + + # If we are being configured for newlib, we know which functions + # newlib provide and which ones we will be expected to provide. + + if test "x${with_newlib}" = "xyes"; then + AC_LIBOBJ([asprintf]) + AC_LIBOBJ([basename]) + AC_LIBOBJ([insque]) + AC_LIBOBJ([random]) + AC_LIBOBJ([strdup]) + AC_LIBOBJ([vasprintf]) + + for f in $funcs; do + case "$f" in + asprintf | basename | insque | random | strdup | vasprintf) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + AC_DEFINE_UNQUOTED($n) + ;; + esac + done + + # newlib doesnt provide any of the variables in $vars, so we + # dont have to check them here. + + # Of the functions in $checkfuncs, newlib only has strerror. + AC_DEFINE(HAVE_STRERROR) + + setobjs=yes + + fi + + # If we are being configured for Mingw, we know which functions + # Mingw provides and which ones we will be expected to provide. + + case "${host}" in + *-*-mingw*) + AC_LIBOBJ([asprintf]) + AC_LIBOBJ([basename]) + AC_LIBOBJ([bcmp]) + AC_LIBOBJ([bcopy]) + AC_LIBOBJ([bzero]) + AC_LIBOBJ([clock]) + AC_LIBOBJ([ffs]) + AC_LIBOBJ([getpagesize]) + AC_LIBOBJ([index]) + AC_LIBOBJ([insque]) + AC_LIBOBJ([mempcpy]) + AC_LIBOBJ([mkstemps]) + AC_LIBOBJ([random]) + AC_LIBOBJ([rindex]) + AC_LIBOBJ([sigsetmask]) + AC_LIBOBJ([stpcpy]) + AC_LIBOBJ([stpncpy]) + AC_LIBOBJ([strndup]) + AC_LIBOBJ([strverscmp]) + AC_LIBOBJ([vasprintf]) + AC_LIBOBJ([waitpid]) + + for f in $funcs; do + case "$f" in + asprintf | basename | bcmp | bcopy | bzero | clock | ffs | getpagesize | index | insque | mempcpy | mkstemps | random | rindex | sigsetmask | stpcpy | stpncpy | strdup | strndup | strverscmp | vasprintf | waitpid) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + AC_DEFINE_UNQUOTED($n) + ;; + esac + done + + # Mingw doesnt provide any of the variables in $vars, so we + # dont have to check them here. + + # Of the functions in $checkfuncs, Mingw only has strerror. + AC_DEFINE(HAVE_STRERROR) + + setobjs=yes + ;; + + *-*-msdosdjgpp) + AC_LIBOBJ([vasprintf]) + AC_LIBOBJ([vsnprintf]) + AC_LIBOBJ([snprintf]) + AC_LIBOBJ([asprintf]) + + for f in atexit basename bcmp bcopy bsearch bzero calloc clock ffs \ + getcwd getpagesize getrusage gettimeofday \ + index insque memchr memcmp memcpy memmove memset psignal \ + putenv random rename rindex sbrk setenv stpcpy strcasecmp \ + strchr strdup strerror strncasecmp strrchr strstr strtod \ + strtol strtoul sysconf times tmpnam vfprintf vprintf \ + vsprintf waitpid + do + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + AC_DEFINE_UNQUOTED($n) + done + + + setobjs=yes + ;; + + esac + + # We may wish to install the target headers somewhere. + AC_ARG_ENABLE(install-libiberty, + [ --enable-install-libiberty Install headers for end users], + enable_install_libiberty=$enableval, + enable_install_libiberty=no)dnl + + # Option parsed, now set things appropriately. + case x"$enable_install_libiberty" in + xyes|x) + target_header_dir=libiberty + ;; + xno) + target_header_dir= + ;; + *) + # This could be sanity-checked in various ways... + target_header_dir="${enable_install_libiberty}" + ;; + esac + + +else + + # Not a target library, so we set things up to run the test suite. + CHECK=really-check + +fi + +AC_SUBST(CHECK) +AC_SUBST(target_header_dir) + +case "${host}" in + *-*-cygwin* | *-*-mingw*) + AC_DEFINE(HAVE_SYS_ERRLIST) + AC_DEFINE(HAVE_SYS_NERR) + ;; +esac + +if test -z "${setobjs}"; then + case "${host}" in + + *-*-vxworks*) + # Handle VxWorks configuration specially, since on VxWorks the + # libraries are actually on the target board, not in the file + # system. + AC_LIBOBJ([basename]) + AC_LIBOBJ([getpagesize]) + AC_LIBOBJ([insque]) + AC_LIBOBJ([random]) + AC_LIBOBJ([strcasecmp]) + AC_LIBOBJ([strncasecmp]) + AC_LIBOBJ([strdup]) + AC_LIBOBJ([vfork]) + AC_LIBOBJ([waitpid]) + AC_LIBOBJ([vasprintf]) + for f in $funcs; do + case "$f" in + basename | getpagesize | insque | random | strcasecmp) + ;; + strncasecmp | strdup | vfork | waitpid | vasprintf) + ;; + *) + n=HAVE_`echo $f | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + AC_DEFINE_UNQUOTED($n) + ;; + esac + done + + # VxWorks doesn't provide any of the variables in $vars, so we + # don't have to check them here. + + # Of the functions in $checkfuncs, VxWorks only has strerror. + AC_DEFINE(HAVE_STRERROR) + + setobjs=yes + ;; + + esac +fi + +if test -z "${setobjs}"; then + + case "${host}" in + + *-*-mingw32*) + # Under mingw32, sys_nerr and sys_errlist exist, but they are + # macros, so the test below won't find them. + libiberty_cv_var_sys_nerr=yes + libiberty_cv_var_sys_errlist=yes + ;; + + *-*-msdosdjgpp*) + # vfork and fork are stubs. + ac_cv_func_vfork_works=no + ;; + + *-*-uwin*) + # Under some versions of uwin, vfork is notoriously buggy and the test + # can hang configure; on other versions, vfork exists just as a stub. + # FIXME: This should be removed once vfork in uwin's runtime is fixed. + ac_cv_func_vfork_works=no + # Under uwin 2.0+, sys_nerr and sys_errlist exist, but they are + # macros (actually, these are imported from a DLL, but the end effect + # is the same), so the test below won't find them. + libiberty_cv_var_sys_nerr=yes + libiberty_cv_var_sys_errlist=yes + ;; + + *-*-*vms*) + # Under VMS, vfork works very different than on Unix. The standard test + # won't work, and it isn't easily adaptable. It makes more sense to + # just force it. + ac_cv_func_vfork_works=yes + ;; + + esac + + # We haven't set the list of objects yet. Use the standard autoconf + # tests. This will only work if the compiler works. + AC_ISC_POSIX + AC_REPLACE_FUNCS($funcs) + libiberty_AC_FUNC_C_ALLOCA + AC_FUNC_FORK + if test $ac_cv_func_vfork_works = no; then + AC_LIBOBJ([vfork]) + fi + # We only need _doprnt if we might use it to implement v*printf. + if test $ac_cv_func_vprintf != yes \ + || test $ac_cv_func_vfprintf != yes \ + || test $ac_cv_func_vsprintf != yes; then + AC_REPLACE_FUNCS(_doprnt) + else + AC_CHECK_FUNCS(_doprnt) + fi + + for v in $vars; do + AC_MSG_CHECKING([for $v]) + AC_CACHE_VAL(libiberty_cv_var_$v, + [AC_LINK_IFELSE([AC_LANG_PROGRAM([[int *p;]],[[extern int $v []; p = $v;]])], + [eval "libiberty_cv_var_$v=yes"], + [eval "libiberty_cv_var_$v=no"])]) + if eval "test \"`echo '$libiberty_cv_var_'$v`\" = yes"; then + AC_MSG_RESULT(yes) + n=HAVE_`echo $v | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + AC_DEFINE_UNQUOTED($n) + else + AC_MSG_RESULT(no) + fi + done + + # special check for _system_configuration because AIX <4.3.2 do not + # contain the `physmem' member. + AC_MSG_CHECKING([for external symbol _system_configuration]) + AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include ]], + [[double x = _system_configuration.physmem;]])], + [AC_MSG_RESULT([yes]) + AC_DEFINE(HAVE__SYSTEM_CONFIGURATION, 1, + [Define if you have the _system_configuration variable.])], + [AC_MSG_RESULT([no])]) + + AC_CHECK_FUNCS($checkfuncs) + AC_CHECK_DECLS([basename(char *), ffs, asprintf, vasprintf, snprintf, vsnprintf]) + AC_CHECK_DECLS([calloc, getenv, getopt, malloc, realloc, sbrk]) + AC_CHECK_DECLS([strverscmp]) + libiberty_NEED_DECLARATION(canonicalize_file_name) +fi + +# Figure out which version of pexecute to use. +case "${host}" in + *-*-mingw* | *-*-winnt*) pexecute=pex-win32 ;; + *-*-msdosdjgpp*) pexecute=pex-djgpp ;; + *-*-msdos*) pexecute=pex-msdos ;; + *) pexecute=pex-unix ;; +esac +AC_SUBST(pexecute) + +libiberty_AC_FUNC_STRNCMP + +# Install a library built with a cross compiler in $(tooldir) rather +# than $(libdir). +if test -z "${with_cross_host}"; then + INSTALL_DEST=libdir +else + INSTALL_DEST=tooldir +fi +AC_SUBST(INSTALL_DEST) + +m4_pattern_allow(LIBOBJS) +L="" +for l in x $LIBOBJS; do + case $l in + x) ;; + *) L="$L ./$l" ;; + esac +done +LIBOBJS="$L" + +dnl Required by html and install-html +AC_SUBST(datarootdir) +AC_SUBST(docdir) +AC_SUBST(htmldir) + +# We need multilib support, but only if configuring for the target. +AC_CONFIG_FILES([Makefile testsuite/Makefile]) +AC_CONFIG_COMMANDS([default], + [[test -z "$CONFIG_HEADERS" || echo timestamp > stamp-h +if test -n "$CONFIG_FILES"; then + if test -n "${with_target_subdir}"; then + # FIXME: We shouldn't need to set ac_file + ac_file=Makefile + LD="${ORIGINAL_LD_FOR_MULTILIBS}" + . ${libiberty_topdir}/config-ml.in + fi +fi]], +[[srcdir=${srcdir} +host=${host} +target=${target} +with_target_subdir=${with_target_subdir} +with_multisubdir=${with_multisubdir} +ac_configure_args="--enable-multilib ${ac_configure_args}" +CONFIG_SHELL=${CONFIG_SHELL-/bin/sh} +ORIGINAL_LD_FOR_MULTILIBS="${ORIGINAL_LD_FOR_MULTILIBS}" +libiberty_topdir=${libiberty_topdir} +]]) +AC_OUTPUT diff --git a/external/gpl3/gdb/dist/libiberty/configure.com b/external/gpl3/gdb/dist/libiberty/configure.com new file mode 100644 index 000000000000..030182914f74 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/configure.com @@ -0,0 +1,38 @@ +$! +$! This file configures the libiberty library for use with openVMS. +$! +$! We do not use the configure script, since we do not have /bin/sh +$! to execute it. +$! +$! Written by Tristan Gingold (gingold@adacore.com) +$! +$! +$! +$ copy config.h-vms config.h +$! +$ write sys$output "Generate libiberty build.com" +$! +$ create build.com +$DECK +$ FILES="getopt,obstack,xexit,xmalloc,hex,getopt1,cplus-dem,cp-demangle,"+- + "cp-demint,asprintf,vasprintf,mkstemps,concat,getruntime,getpagesize,"+- + "getpwd,xstrerror,xmemdup,xstrdup,xatexit,choose-temp,fnmatch,objalloc,"+- + "safe-ctype,hashtab,lbasename,argv,lrealpath,make-temp-file,"+- + "stpcpy,unlink-if-ordinary" +$ OPT="/noopt/debug/warnings=disable=(missingreturn)" +$ CFLAGS=OPT + "/include=([],[-.include])/name=(as_is,shortened)" +- + "/define=(HAVE_CONFIG_H=1)" +- + "/prefix=(all,exc=(""getopt"",""optarg"",""optopt"",""optind"",""opterr""))" +$ write sys$output "CFLAGS=",CFLAGS +$ NUM = 0 +$ LOOP: +$ F = F$ELEMENT(NUM,",",FILES) +$ IF F.EQS."," THEN GOTO END +$ write sys$output "Compiling ", F, ".c" +$ cc 'CFLAGS 'F.c +$ NUM = NUM + 1 +$ GOTO LOOP +$ END: +$ purge +$ lib/create libiberty 'FILES +$EOD diff --git a/external/gpl3/gdb/dist/libiberty/copying-lib.texi b/external/gpl3/gdb/dist/libiberty/copying-lib.texi new file mode 100644 index 000000000000..79e1038783d5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/copying-lib.texi @@ -0,0 +1,565 @@ +@node Library Copying +@appendixsec GNU LESSER GENERAL PUBLIC LICENSE + +@cindex LGPL, Lesser General Public License +@center Version 2.1, February 1999 + +@display +Copyright @copyright{} 1991, 1999 Free Software Foundation, Inc. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. + +[This is the first released version of the Lesser GPL. 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Here is a sample; alter the names: + +@smallexample +Yoyodyne, Inc., hereby disclaims all copyright interest in the library +`Frob' (a library for tweaking knobs) written by James Random Hacker. + +@var{signature of Ty Coon}, 1 April 1990 +Ty Coon, President of Vice +@end smallexample + +That's all there is to it! diff --git a/external/gpl3/gdb/dist/libiberty/copysign.c b/external/gpl3/gdb/dist/libiberty/copysign.c new file mode 100644 index 000000000000..6793f22e8cca --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/copysign.c @@ -0,0 +1,154 @@ +#include + +#ifdef __IEEE_BIG_ENDIAN + +typedef union +{ + double value; + struct + { + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int fraction0:4; + unsigned int fraction1:16; + unsigned int fraction2:16; + unsigned int fraction3:16; + + } number; + struct + { + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int quiet:1; + unsigned int function0:3; + unsigned int function1:16; + unsigned int function2:16; + unsigned int function3:16; + } nan; + struct + { + unsigned long msw; + unsigned long lsw; + } parts; + long aslong[2]; +} __ieee_double_shape_type; + +#endif + +#ifdef __IEEE_LITTLE_ENDIAN + +typedef union +{ + double value; + struct + { +#ifdef __SMALL_BITFIELDS + unsigned int fraction3:16; + unsigned int fraction2:16; + unsigned int fraction1:16; + unsigned int fraction0: 4; +#else + unsigned int fraction1:32; + unsigned int fraction0:20; +#endif + unsigned int exponent :11; + unsigned int sign : 1; + } number; + struct + { +#ifdef __SMALL_BITFIELDS + unsigned int function3:16; + unsigned int function2:16; + unsigned int function1:16; + unsigned int function0:3; +#else + unsigned int function1:32; + unsigned int function0:19; +#endif + unsigned int quiet:1; + unsigned int exponent: 11; + unsigned int sign : 1; + } nan; + struct + { + unsigned long lsw; + unsigned long msw; + } parts; + + long aslong[2]; + +} __ieee_double_shape_type; + +#endif + +#ifdef __IEEE_BIG_ENDIAN +typedef union +{ + float value; + struct + { + unsigned int sign : 1; + unsigned int exponent: 8; + unsigned int fraction0: 7; + unsigned int fraction1: 16; + } number; + struct + { + unsigned int sign:1; + unsigned int exponent:8; + unsigned int quiet:1; + unsigned int function0:6; + unsigned int function1:16; + } nan; + long p1; + +} __ieee_float_shape_type; +#endif + +#ifdef __IEEE_LITTLE_ENDIAN +typedef union +{ + float value; + struct + { + unsigned int fraction0: 7; + unsigned int fraction1: 16; + unsigned int exponent: 8; + unsigned int sign : 1; + } number; + struct + { + unsigned int function1:16; + unsigned int function0:6; + unsigned int quiet:1; + unsigned int exponent:8; + unsigned int sign:1; + } nan; + long p1; + +} __ieee_float_shape_type; +#endif + +#if defined(__IEEE_BIG_ENDIAN) || defined(__IEEE_LITTLE_ENDIAN) + +double +copysign (double x, double y) +{ + __ieee_double_shape_type a,b; + b.value = y; + a.value = x; + a.number.sign =b.number.sign; + return a.value; +} + +#else + +double +copysign (double x, double y) +{ + if ((x < 0 && y > 0) || (x > 0 && y < 0)) + return -x; + return x; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/cp-demangle.c b/external/gpl3/gdb/dist/libiberty/cp-demangle.c new file mode 100644 index 000000000000..2ca835e8884f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/cp-demangle.c @@ -0,0 +1,5408 @@ +/* Demangler for g++ V3 ABI. + Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 + Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of the libiberty library, which is part of GCC. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combined + executable.) + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +/* This code implements a demangler for the g++ V3 ABI. The ABI is + described on this web page: + http://www.codesourcery.com/cxx-abi/abi.html#mangling + + This code was written while looking at the demangler written by + Alex Samuel . + + This code first pulls the mangled name apart into a list of + components, and then walks the list generating the demangled + name. + + This file will normally define the following functions, q.v.: + char *cplus_demangle_v3(const char *mangled, int options) + char *java_demangle_v3(const char *mangled) + int cplus_demangle_v3_callback(const char *mangled, int options, + demangle_callbackref callback) + int java_demangle_v3_callback(const char *mangled, + demangle_callbackref callback) + enum gnu_v3_ctor_kinds is_gnu_v3_mangled_ctor (const char *name) + enum gnu_v3_dtor_kinds is_gnu_v3_mangled_dtor (const char *name) + + Also, the interface to the component list is public, and defined in + demangle.h. The interface consists of these types, which are + defined in demangle.h: + enum demangle_component_type + struct demangle_component + demangle_callbackref + and these functions defined in this file: + cplus_demangle_fill_name + cplus_demangle_fill_extended_operator + cplus_demangle_fill_ctor + cplus_demangle_fill_dtor + cplus_demangle_print + cplus_demangle_print_callback + and other functions defined in the file cp-demint.c. + + This file also defines some other functions and variables which are + only to be used by the file cp-demint.c. + + Preprocessor macros you can define while compiling this file: + + IN_LIBGCC2 + If defined, this file defines the following functions, q.v.: + char *__cxa_demangle (const char *mangled, char *buf, size_t *len, + int *status) + int __gcclibcxx_demangle_callback (const char *, + void (*) + (const char *, size_t, void *), + void *) + instead of cplus_demangle_v3[_callback]() and + java_demangle_v3[_callback](). + + IN_GLIBCPP_V3 + If defined, this file defines only __cxa_demangle() and + __gcclibcxx_demangle_callback(), and no other publically visible + functions or variables. + + STANDALONE_DEMANGLER + If defined, this file defines a main() function which demangles + any arguments, or, if none, demangles stdin. + + CP_DEMANGLE_DEBUG + If defined, turns on debugging mode, which prints information on + stdout about the mangled string. This is not generally useful. +*/ + +#if defined (_AIX) && !defined (__GNUC__) + #pragma alloca +#endif + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_ALLOCA_H +# include +#else +# ifndef alloca +# ifdef __GNUC__ +# define alloca __builtin_alloca +# else +extern char *alloca (); +# endif /* __GNUC__ */ +# endif /* alloca */ +#endif /* HAVE_ALLOCA_H */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "demangle.h" +#include "cp-demangle.h" + +/* If IN_GLIBCPP_V3 is defined, some functions are made static. We + also rename them via #define to avoid compiler errors when the + static definition conflicts with the extern declaration in a header + file. */ +#ifdef IN_GLIBCPP_V3 + +#define CP_STATIC_IF_GLIBCPP_V3 static + +#define cplus_demangle_fill_name d_fill_name +static int d_fill_name (struct demangle_component *, const char *, int); + +#define cplus_demangle_fill_extended_operator d_fill_extended_operator +static int +d_fill_extended_operator (struct demangle_component *, int, + struct demangle_component *); + +#define cplus_demangle_fill_ctor d_fill_ctor +static int +d_fill_ctor (struct demangle_component *, enum gnu_v3_ctor_kinds, + struct demangle_component *); + +#define cplus_demangle_fill_dtor d_fill_dtor +static int +d_fill_dtor (struct demangle_component *, enum gnu_v3_dtor_kinds, + struct demangle_component *); + +#define cplus_demangle_mangled_name d_mangled_name +static struct demangle_component *d_mangled_name (struct d_info *, int); + +#define cplus_demangle_type d_type +static struct demangle_component *d_type (struct d_info *); + +#define cplus_demangle_print d_print +static char *d_print (int, const struct demangle_component *, int, size_t *); + +#define cplus_demangle_print_callback d_print_callback +static int d_print_callback (int, const struct demangle_component *, + demangle_callbackref, void *); + +#define cplus_demangle_init_info d_init_info +static void d_init_info (const char *, int, size_t, struct d_info *); + +#else /* ! defined(IN_GLIBCPP_V3) */ +#define CP_STATIC_IF_GLIBCPP_V3 +#endif /* ! defined(IN_GLIBCPP_V3) */ + +/* See if the compiler supports dynamic arrays. */ + +#ifdef __GNUC__ +#define CP_DYNAMIC_ARRAYS +#else +#ifdef __STDC__ +#ifdef __STDC_VERSION__ +#if __STDC_VERSION__ >= 199901L +#define CP_DYNAMIC_ARRAYS +#endif /* __STDC__VERSION >= 199901L */ +#endif /* defined (__STDC_VERSION__) */ +#endif /* defined (__STDC__) */ +#endif /* ! defined (__GNUC__) */ + +/* We avoid pulling in the ctype tables, to prevent pulling in + additional unresolved symbols when this code is used in a library. + FIXME: Is this really a valid reason? This comes from the original + V3 demangler code. + + As of this writing this file has the following undefined references + when compiled with -DIN_GLIBCPP_V3: realloc, free, memcpy, strcpy, + strcat, strlen. */ + +#define IS_DIGIT(c) ((c) >= '0' && (c) <= '9') +#define IS_UPPER(c) ((c) >= 'A' && (c) <= 'Z') +#define IS_LOWER(c) ((c) >= 'a' && (c) <= 'z') + +/* The prefix prepended by GCC to an identifier represnting the + anonymous namespace. */ +#define ANONYMOUS_NAMESPACE_PREFIX "_GLOBAL_" +#define ANONYMOUS_NAMESPACE_PREFIX_LEN \ + (sizeof (ANONYMOUS_NAMESPACE_PREFIX) - 1) + +/* Information we keep for the standard substitutions. */ + +struct d_standard_sub_info +{ + /* The code for this substitution. */ + char code; + /* The simple string it expands to. */ + const char *simple_expansion; + /* The length of the simple expansion. */ + int simple_len; + /* The results of a full, verbose, expansion. This is used when + qualifying a constructor/destructor, or when in verbose mode. */ + const char *full_expansion; + /* The length of the full expansion. */ + int full_len; + /* What to set the last_name field of d_info to; NULL if we should + not set it. This is only relevant when qualifying a + constructor/destructor. */ + const char *set_last_name; + /* The length of set_last_name. */ + int set_last_name_len; +}; + +/* Accessors for subtrees of struct demangle_component. */ + +#define d_left(dc) ((dc)->u.s_binary.left) +#define d_right(dc) ((dc)->u.s_binary.right) + +/* A list of templates. This is used while printing. */ + +struct d_print_template +{ + /* Next template on the list. */ + struct d_print_template *next; + /* This template. */ + const struct demangle_component *template_decl; +}; + +/* A list of type modifiers. This is used while printing. */ + +struct d_print_mod +{ + /* Next modifier on the list. These are in the reverse of the order + in which they appeared in the mangled string. */ + struct d_print_mod *next; + /* The modifier. */ + const struct demangle_component *mod; + /* Whether this modifier was printed. */ + int printed; + /* The list of templates which applies to this modifier. */ + struct d_print_template *templates; +}; + +/* We use these structures to hold information during printing. */ + +struct d_growable_string +{ + /* Buffer holding the result. */ + char *buf; + /* Current length of data in buffer. */ + size_t len; + /* Allocated size of buffer. */ + size_t alc; + /* Set to 1 if we had a memory allocation failure. */ + int allocation_failure; +}; + +enum { D_PRINT_BUFFER_LENGTH = 256 }; +struct d_print_info +{ + /* Fixed-length allocated buffer for demangled data, flushed to the + callback with a NUL termination once full. */ + char buf[D_PRINT_BUFFER_LENGTH]; + /* Current length of data in buffer. */ + size_t len; + /* The last character printed, saved individually so that it survives + any buffer flush. */ + char last_char; + /* Callback function to handle demangled buffer flush. */ + demangle_callbackref callback; + /* Opaque callback argument. */ + void *opaque; + /* The current list of templates, if any. */ + struct d_print_template *templates; + /* The current list of modifiers (e.g., pointer, reference, etc.), + if any. */ + struct d_print_mod *modifiers; + /* Set to 1 if we saw a demangling error. */ + int demangle_failure; + /* The current index into any template argument packs we are using + for printing. */ + int pack_index; + /* Number of d_print_flush calls so far. */ + unsigned long int flush_count; +}; + +#ifdef CP_DEMANGLE_DEBUG +static void d_dump (struct demangle_component *, int); +#endif + +static struct demangle_component * +d_make_empty (struct d_info *); + +static struct demangle_component * +d_make_comp (struct d_info *, enum demangle_component_type, + struct demangle_component *, + struct demangle_component *); + +static struct demangle_component * +d_make_name (struct d_info *, const char *, int); + +static struct demangle_component * +d_make_demangle_mangled_name (struct d_info *, const char *); + +static struct demangle_component * +d_make_builtin_type (struct d_info *, + const struct demangle_builtin_type_info *); + +static struct demangle_component * +d_make_operator (struct d_info *, + const struct demangle_operator_info *); + +static struct demangle_component * +d_make_extended_operator (struct d_info *, int, + struct demangle_component *); + +static struct demangle_component * +d_make_ctor (struct d_info *, enum gnu_v3_ctor_kinds, + struct demangle_component *); + +static struct demangle_component * +d_make_dtor (struct d_info *, enum gnu_v3_dtor_kinds, + struct demangle_component *); + +static struct demangle_component * +d_make_template_param (struct d_info *, long); + +static struct demangle_component * +d_make_sub (struct d_info *, const char *, int); + +static int +has_return_type (struct demangle_component *); + +static int +is_ctor_dtor_or_conversion (struct demangle_component *); + +static struct demangle_component *d_encoding (struct d_info *, int); + +static struct demangle_component *d_name (struct d_info *); + +static struct demangle_component *d_nested_name (struct d_info *); + +static struct demangle_component *d_prefix (struct d_info *); + +static struct demangle_component *d_unqualified_name (struct d_info *); + +static struct demangle_component *d_source_name (struct d_info *); + +static long d_number (struct d_info *); + +static struct demangle_component *d_identifier (struct d_info *, int); + +static struct demangle_component *d_operator_name (struct d_info *); + +static struct demangle_component *d_special_name (struct d_info *); + +static int d_call_offset (struct d_info *, int); + +static struct demangle_component *d_ctor_dtor_name (struct d_info *); + +static struct demangle_component ** +d_cv_qualifiers (struct d_info *, struct demangle_component **, int); + +static struct demangle_component * +d_function_type (struct d_info *); + +static struct demangle_component * +d_bare_function_type (struct d_info *, int); + +static struct demangle_component * +d_class_enum_type (struct d_info *); + +static struct demangle_component *d_array_type (struct d_info *); + +static struct demangle_component *d_vector_type (struct d_info *); + +static struct demangle_component * +d_pointer_to_member_type (struct d_info *); + +static struct demangle_component * +d_template_param (struct d_info *); + +static struct demangle_component *d_template_args (struct d_info *); + +static struct demangle_component * +d_template_arg (struct d_info *); + +static struct demangle_component *d_expression (struct d_info *); + +static struct demangle_component *d_expr_primary (struct d_info *); + +static struct demangle_component *d_local_name (struct d_info *); + +static int d_discriminator (struct d_info *); + +static struct demangle_component *d_lambda (struct d_info *); + +static struct demangle_component *d_unnamed_type (struct d_info *); + +static int +d_add_substitution (struct d_info *, struct demangle_component *); + +static struct demangle_component *d_substitution (struct d_info *, int); + +static void d_growable_string_init (struct d_growable_string *, size_t); + +static inline void +d_growable_string_resize (struct d_growable_string *, size_t); + +static inline void +d_growable_string_append_buffer (struct d_growable_string *, + const char *, size_t); +static void +d_growable_string_callback_adapter (const char *, size_t, void *); + +static void +d_print_init (struct d_print_info *, demangle_callbackref, void *); + +static inline void d_print_error (struct d_print_info *); + +static inline int d_print_saw_error (struct d_print_info *); + +static inline void d_print_flush (struct d_print_info *); + +static inline void d_append_char (struct d_print_info *, char); + +static inline void d_append_buffer (struct d_print_info *, + const char *, size_t); + +static inline void d_append_string (struct d_print_info *, const char *); + +static inline char d_last_char (struct d_print_info *); + +static void +d_print_comp (struct d_print_info *, int, const struct demangle_component *); + +static void +d_print_java_identifier (struct d_print_info *, const char *, int); + +static void +d_print_mod_list (struct d_print_info *, int, struct d_print_mod *, int); + +static void +d_print_mod (struct d_print_info *, int, const struct demangle_component *); + +static void +d_print_function_type (struct d_print_info *, int, + const struct demangle_component *, + struct d_print_mod *); + +static void +d_print_array_type (struct d_print_info *, int, + const struct demangle_component *, + struct d_print_mod *); + +static void +d_print_expr_op (struct d_print_info *, int, const struct demangle_component *); + +static void +d_print_cast (struct d_print_info *, int, const struct demangle_component *); + +static int d_demangle_callback (const char *, int, + demangle_callbackref, void *); +static char *d_demangle (const char *, int, size_t *); + +#ifdef CP_DEMANGLE_DEBUG + +static void +d_dump (struct demangle_component *dc, int indent) +{ + int i; + + if (dc == NULL) + { + if (indent == 0) + printf ("failed demangling\n"); + return; + } + + for (i = 0; i < indent; ++i) + putchar (' '); + + switch (dc->type) + { + case DEMANGLE_COMPONENT_NAME: + printf ("name '%.*s'\n", dc->u.s_name.len, dc->u.s_name.s); + return; + case DEMANGLE_COMPONENT_TEMPLATE_PARAM: + printf ("template parameter %ld\n", dc->u.s_number.number); + return; + case DEMANGLE_COMPONENT_CTOR: + printf ("constructor %d\n", (int) dc->u.s_ctor.kind); + d_dump (dc->u.s_ctor.name, indent + 2); + return; + case DEMANGLE_COMPONENT_DTOR: + printf ("destructor %d\n", (int) dc->u.s_dtor.kind); + d_dump (dc->u.s_dtor.name, indent + 2); + return; + case DEMANGLE_COMPONENT_SUB_STD: + printf ("standard substitution %s\n", dc->u.s_string.string); + return; + case DEMANGLE_COMPONENT_BUILTIN_TYPE: + printf ("builtin type %s\n", dc->u.s_builtin.type->name); + return; + case DEMANGLE_COMPONENT_OPERATOR: + printf ("operator %s\n", dc->u.s_operator.op->name); + return; + case DEMANGLE_COMPONENT_EXTENDED_OPERATOR: + printf ("extended operator with %d args\n", + dc->u.s_extended_operator.args); + d_dump (dc->u.s_extended_operator.name, indent + 2); + return; + + case DEMANGLE_COMPONENT_QUAL_NAME: + printf ("qualified name\n"); + break; + case DEMANGLE_COMPONENT_LOCAL_NAME: + printf ("local name\n"); + break; + case DEMANGLE_COMPONENT_TYPED_NAME: + printf ("typed name\n"); + break; + case DEMANGLE_COMPONENT_TEMPLATE: + printf ("template\n"); + break; + case DEMANGLE_COMPONENT_VTABLE: + printf ("vtable\n"); + break; + case DEMANGLE_COMPONENT_VTT: + printf ("VTT\n"); + break; + case DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE: + printf ("construction vtable\n"); + break; + case DEMANGLE_COMPONENT_TYPEINFO: + printf ("typeinfo\n"); + break; + case DEMANGLE_COMPONENT_TYPEINFO_NAME: + printf ("typeinfo name\n"); + break; + case DEMANGLE_COMPONENT_TYPEINFO_FN: + printf ("typeinfo function\n"); + break; + case DEMANGLE_COMPONENT_THUNK: + printf ("thunk\n"); + break; + case DEMANGLE_COMPONENT_VIRTUAL_THUNK: + printf ("virtual thunk\n"); + break; + case DEMANGLE_COMPONENT_COVARIANT_THUNK: + printf ("covariant thunk\n"); + break; + case DEMANGLE_COMPONENT_JAVA_CLASS: + printf ("java class\n"); + break; + case DEMANGLE_COMPONENT_GUARD: + printf ("guard\n"); + break; + case DEMANGLE_COMPONENT_REFTEMP: + printf ("reference temporary\n"); + break; + case DEMANGLE_COMPONENT_HIDDEN_ALIAS: + printf ("hidden alias\n"); + break; + case DEMANGLE_COMPONENT_RESTRICT: + printf ("restrict\n"); + break; + case DEMANGLE_COMPONENT_VOLATILE: + printf ("volatile\n"); + break; + case DEMANGLE_COMPONENT_CONST: + printf ("const\n"); + break; + case DEMANGLE_COMPONENT_RESTRICT_THIS: + printf ("restrict this\n"); + break; + case DEMANGLE_COMPONENT_VOLATILE_THIS: + printf ("volatile this\n"); + break; + case DEMANGLE_COMPONENT_CONST_THIS: + printf ("const this\n"); + break; + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + printf ("vendor type qualifier\n"); + break; + case DEMANGLE_COMPONENT_POINTER: + printf ("pointer\n"); + break; + case DEMANGLE_COMPONENT_REFERENCE: + printf ("reference\n"); + break; + case DEMANGLE_COMPONENT_RVALUE_REFERENCE: + printf ("rvalue reference\n"); + break; + case DEMANGLE_COMPONENT_COMPLEX: + printf ("complex\n"); + break; + case DEMANGLE_COMPONENT_IMAGINARY: + printf ("imaginary\n"); + break; + case DEMANGLE_COMPONENT_VENDOR_TYPE: + printf ("vendor type\n"); + break; + case DEMANGLE_COMPONENT_FUNCTION_TYPE: + printf ("function type\n"); + break; + case DEMANGLE_COMPONENT_ARRAY_TYPE: + printf ("array type\n"); + break; + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + printf ("pointer to member type\n"); + break; + case DEMANGLE_COMPONENT_FIXED_TYPE: + printf ("fixed-point type\n"); + break; + case DEMANGLE_COMPONENT_ARGLIST: + printf ("argument list\n"); + break; + case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST: + printf ("template argument list\n"); + break; + case DEMANGLE_COMPONENT_CAST: + printf ("cast\n"); + break; + case DEMANGLE_COMPONENT_UNARY: + printf ("unary operator\n"); + break; + case DEMANGLE_COMPONENT_BINARY: + printf ("binary operator\n"); + break; + case DEMANGLE_COMPONENT_BINARY_ARGS: + printf ("binary operator arguments\n"); + break; + case DEMANGLE_COMPONENT_TRINARY: + printf ("trinary operator\n"); + break; + case DEMANGLE_COMPONENT_TRINARY_ARG1: + printf ("trinary operator arguments 1\n"); + break; + case DEMANGLE_COMPONENT_TRINARY_ARG2: + printf ("trinary operator arguments 1\n"); + break; + case DEMANGLE_COMPONENT_LITERAL: + printf ("literal\n"); + break; + case DEMANGLE_COMPONENT_LITERAL_NEG: + printf ("negative literal\n"); + break; + case DEMANGLE_COMPONENT_JAVA_RESOURCE: + printf ("java resource\n"); + break; + case DEMANGLE_COMPONENT_COMPOUND_NAME: + printf ("compound name\n"); + break; + case DEMANGLE_COMPONENT_CHARACTER: + printf ("character '%c'\n", dc->u.s_character.character); + return; + case DEMANGLE_COMPONENT_DECLTYPE: + printf ("decltype\n"); + break; + case DEMANGLE_COMPONENT_PACK_EXPANSION: + printf ("pack expansion\n"); + break; + } + + d_dump (d_left (dc), indent + 2); + d_dump (d_right (dc), indent + 2); +} + +#endif /* CP_DEMANGLE_DEBUG */ + +/* Fill in a DEMANGLE_COMPONENT_NAME. */ + +CP_STATIC_IF_GLIBCPP_V3 +int +cplus_demangle_fill_name (struct demangle_component *p, const char *s, int len) +{ + if (p == NULL || s == NULL || len == 0) + return 0; + p->type = DEMANGLE_COMPONENT_NAME; + p->u.s_name.s = s; + p->u.s_name.len = len; + return 1; +} + +/* Fill in a DEMANGLE_COMPONENT_EXTENDED_OPERATOR. */ + +CP_STATIC_IF_GLIBCPP_V3 +int +cplus_demangle_fill_extended_operator (struct demangle_component *p, int args, + struct demangle_component *name) +{ + if (p == NULL || args < 0 || name == NULL) + return 0; + p->type = DEMANGLE_COMPONENT_EXTENDED_OPERATOR; + p->u.s_extended_operator.args = args; + p->u.s_extended_operator.name = name; + return 1; +} + +/* Fill in a DEMANGLE_COMPONENT_CTOR. */ + +CP_STATIC_IF_GLIBCPP_V3 +int +cplus_demangle_fill_ctor (struct demangle_component *p, + enum gnu_v3_ctor_kinds kind, + struct demangle_component *name) +{ + if (p == NULL + || name == NULL + || (int) kind < gnu_v3_complete_object_ctor + || (int) kind > gnu_v3_complete_object_allocating_ctor) + return 0; + p->type = DEMANGLE_COMPONENT_CTOR; + p->u.s_ctor.kind = kind; + p->u.s_ctor.name = name; + return 1; +} + +/* Fill in a DEMANGLE_COMPONENT_DTOR. */ + +CP_STATIC_IF_GLIBCPP_V3 +int +cplus_demangle_fill_dtor (struct demangle_component *p, + enum gnu_v3_dtor_kinds kind, + struct demangle_component *name) +{ + if (p == NULL + || name == NULL + || (int) kind < gnu_v3_deleting_dtor + || (int) kind > gnu_v3_base_object_dtor) + return 0; + p->type = DEMANGLE_COMPONENT_DTOR; + p->u.s_dtor.kind = kind; + p->u.s_dtor.name = name; + return 1; +} + +/* Add a new component. */ + +static struct demangle_component * +d_make_empty (struct d_info *di) +{ + struct demangle_component *p; + + if (di->next_comp >= di->num_comps) + return NULL; + p = &di->comps[di->next_comp]; + ++di->next_comp; + return p; +} + +/* Add a new generic component. */ + +static struct demangle_component * +d_make_comp (struct d_info *di, enum demangle_component_type type, + struct demangle_component *left, + struct demangle_component *right) +{ + struct demangle_component *p; + + /* We check for errors here. A typical error would be a NULL return + from a subroutine. We catch those here, and return NULL + upward. */ + switch (type) + { + /* These types require two parameters. */ + case DEMANGLE_COMPONENT_QUAL_NAME: + case DEMANGLE_COMPONENT_LOCAL_NAME: + case DEMANGLE_COMPONENT_TYPED_NAME: + case DEMANGLE_COMPONENT_TEMPLATE: + case DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE: + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + case DEMANGLE_COMPONENT_UNARY: + case DEMANGLE_COMPONENT_BINARY: + case DEMANGLE_COMPONENT_BINARY_ARGS: + case DEMANGLE_COMPONENT_TRINARY: + case DEMANGLE_COMPONENT_TRINARY_ARG1: + case DEMANGLE_COMPONENT_TRINARY_ARG2: + case DEMANGLE_COMPONENT_LITERAL: + case DEMANGLE_COMPONENT_LITERAL_NEG: + case DEMANGLE_COMPONENT_COMPOUND_NAME: + case DEMANGLE_COMPONENT_VECTOR_TYPE: + if (left == NULL || right == NULL) + return NULL; + break; + + /* These types only require one parameter. */ + case DEMANGLE_COMPONENT_VTABLE: + case DEMANGLE_COMPONENT_VTT: + case DEMANGLE_COMPONENT_TYPEINFO: + case DEMANGLE_COMPONENT_TYPEINFO_NAME: + case DEMANGLE_COMPONENT_TYPEINFO_FN: + case DEMANGLE_COMPONENT_THUNK: + case DEMANGLE_COMPONENT_VIRTUAL_THUNK: + case DEMANGLE_COMPONENT_COVARIANT_THUNK: + case DEMANGLE_COMPONENT_JAVA_CLASS: + case DEMANGLE_COMPONENT_GUARD: + case DEMANGLE_COMPONENT_REFTEMP: + case DEMANGLE_COMPONENT_HIDDEN_ALIAS: + case DEMANGLE_COMPONENT_POINTER: + case DEMANGLE_COMPONENT_REFERENCE: + case DEMANGLE_COMPONENT_RVALUE_REFERENCE: + case DEMANGLE_COMPONENT_COMPLEX: + case DEMANGLE_COMPONENT_IMAGINARY: + case DEMANGLE_COMPONENT_VENDOR_TYPE: + case DEMANGLE_COMPONENT_CAST: + case DEMANGLE_COMPONENT_JAVA_RESOURCE: + case DEMANGLE_COMPONENT_DECLTYPE: + case DEMANGLE_COMPONENT_PACK_EXPANSION: + case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS: + case DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS: + if (left == NULL) + return NULL; + break; + + /* This needs a right parameter, but the left parameter can be + empty. */ + case DEMANGLE_COMPONENT_ARRAY_TYPE: + if (right == NULL) + return NULL; + break; + + /* These are allowed to have no parameters--in some cases they + will be filled in later. */ + case DEMANGLE_COMPONENT_FUNCTION_TYPE: + case DEMANGLE_COMPONENT_RESTRICT: + case DEMANGLE_COMPONENT_VOLATILE: + case DEMANGLE_COMPONENT_CONST: + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + case DEMANGLE_COMPONENT_ARGLIST: + case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST: + break; + + /* Other types should not be seen here. */ + default: + return NULL; + } + + p = d_make_empty (di); + if (p != NULL) + { + p->type = type; + p->u.s_binary.left = left; + p->u.s_binary.right = right; + } + return p; +} + +/* Add a new demangle mangled name component. */ + +static struct demangle_component * +d_make_demangle_mangled_name (struct d_info *di, const char *s) +{ + if (d_peek_char (di) != '_' || d_peek_next_char (di) != 'Z') + return d_make_name (di, s, strlen (s)); + d_advance (di, 2); + return d_encoding (di, 0); +} + +/* Add a new name component. */ + +static struct demangle_component * +d_make_name (struct d_info *di, const char *s, int len) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (! cplus_demangle_fill_name (p, s, len)) + return NULL; + return p; +} + +/* Add a new builtin type component. */ + +static struct demangle_component * +d_make_builtin_type (struct d_info *di, + const struct demangle_builtin_type_info *type) +{ + struct demangle_component *p; + + if (type == NULL) + return NULL; + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_BUILTIN_TYPE; + p->u.s_builtin.type = type; + } + return p; +} + +/* Add a new operator component. */ + +static struct demangle_component * +d_make_operator (struct d_info *di, const struct demangle_operator_info *op) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_OPERATOR; + p->u.s_operator.op = op; + } + return p; +} + +/* Add a new extended operator component. */ + +static struct demangle_component * +d_make_extended_operator (struct d_info *di, int args, + struct demangle_component *name) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (! cplus_demangle_fill_extended_operator (p, args, name)) + return NULL; + return p; +} + +static struct demangle_component * +d_make_default_arg (struct d_info *di, int num, + struct demangle_component *sub) +{ + struct demangle_component *p = d_make_empty (di); + if (p) + { + p->type = DEMANGLE_COMPONENT_DEFAULT_ARG; + p->u.s_unary_num.num = num; + p->u.s_unary_num.sub = sub; + } + return p; +} + +/* Add a new constructor component. */ + +static struct demangle_component * +d_make_ctor (struct d_info *di, enum gnu_v3_ctor_kinds kind, + struct demangle_component *name) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (! cplus_demangle_fill_ctor (p, kind, name)) + return NULL; + return p; +} + +/* Add a new destructor component. */ + +static struct demangle_component * +d_make_dtor (struct d_info *di, enum gnu_v3_dtor_kinds kind, + struct demangle_component *name) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (! cplus_demangle_fill_dtor (p, kind, name)) + return NULL; + return p; +} + +/* Add a new template parameter. */ + +static struct demangle_component * +d_make_template_param (struct d_info *di, long i) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_TEMPLATE_PARAM; + p->u.s_number.number = i; + } + return p; +} + +/* Add a new function parameter. */ + +static struct demangle_component * +d_make_function_param (struct d_info *di, long i) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_FUNCTION_PARAM; + p->u.s_number.number = i; + } + return p; +} + +/* Add a new standard substitution component. */ + +static struct demangle_component * +d_make_sub (struct d_info *di, const char *name, int len) +{ + struct demangle_component *p; + + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_SUB_STD; + p->u.s_string.string = name; + p->u.s_string.len = len; + } + return p; +} + +/* ::= _Z + + TOP_LEVEL is non-zero when called at the top level. */ + +CP_STATIC_IF_GLIBCPP_V3 +struct demangle_component * +cplus_demangle_mangled_name (struct d_info *di, int top_level) +{ + if (! d_check_char (di, '_') + /* Allow missing _ if not at toplevel to work around a + bug in G++ abi-version=2 mangling; see the comment in + write_template_arg. */ + && top_level) + return NULL; + if (! d_check_char (di, 'Z')) + return NULL; + return d_encoding (di, top_level); +} + +/* Return whether a function should have a return type. The argument + is the function name, which may be qualified in various ways. The + rules are that template functions have return types with some + exceptions, function types which are not part of a function name + mangling have return types with some exceptions, and non-template + function names do not have return types. The exceptions are that + constructors, destructors, and conversion operators do not have + return types. */ + +static int +has_return_type (struct demangle_component *dc) +{ + if (dc == NULL) + return 0; + switch (dc->type) + { + default: + return 0; + case DEMANGLE_COMPONENT_TEMPLATE: + return ! is_ctor_dtor_or_conversion (d_left (dc)); + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + return has_return_type (d_left (dc)); + } +} + +/* Return whether a name is a constructor, a destructor, or a + conversion operator. */ + +static int +is_ctor_dtor_or_conversion (struct demangle_component *dc) +{ + if (dc == NULL) + return 0; + switch (dc->type) + { + default: + return 0; + case DEMANGLE_COMPONENT_QUAL_NAME: + case DEMANGLE_COMPONENT_LOCAL_NAME: + return is_ctor_dtor_or_conversion (d_right (dc)); + case DEMANGLE_COMPONENT_CTOR: + case DEMANGLE_COMPONENT_DTOR: + case DEMANGLE_COMPONENT_CAST: + return 1; + } +} + +/* ::= <(function) name> + ::= <(data) name> + ::= + + TOP_LEVEL is non-zero when called at the top level, in which case + if DMGL_PARAMS is not set we do not demangle the function + parameters. We only set this at the top level, because otherwise + we would not correctly demangle names in local scopes. */ + +static struct demangle_component * +d_encoding (struct d_info *di, int top_level) +{ + char peek = d_peek_char (di); + + if (peek == 'G' || peek == 'T') + return d_special_name (di); + else + { + struct demangle_component *dc; + + dc = d_name (di); + + if (dc != NULL && top_level && (di->options & DMGL_PARAMS) == 0) + { + /* Strip off any initial CV-qualifiers, as they really apply + to the `this' parameter, and they were not output by the + v2 demangler without DMGL_PARAMS. */ + while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS + || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS + || dc->type == DEMANGLE_COMPONENT_CONST_THIS) + dc = d_left (dc); + + /* If the top level is a DEMANGLE_COMPONENT_LOCAL_NAME, then + there may be CV-qualifiers on its right argument which + really apply here; this happens when parsing a class + which is local to a function. */ + if (dc->type == DEMANGLE_COMPONENT_LOCAL_NAME) + { + struct demangle_component *dcr; + + dcr = d_right (dc); + while (dcr->type == DEMANGLE_COMPONENT_RESTRICT_THIS + || dcr->type == DEMANGLE_COMPONENT_VOLATILE_THIS + || dcr->type == DEMANGLE_COMPONENT_CONST_THIS) + dcr = d_left (dcr); + dc->u.s_binary.right = dcr; + } + + return dc; + } + + peek = d_peek_char (di); + if (dc == NULL || peek == '\0' || peek == 'E') + return dc; + return d_make_comp (di, DEMANGLE_COMPONENT_TYPED_NAME, dc, + d_bare_function_type (di, has_return_type (dc))); + } +} + +/* ::= + ::= + ::= + ::= + + ::= + ::= St + + ::= + ::= +*/ + +static struct demangle_component * +d_name (struct d_info *di) +{ + char peek = d_peek_char (di); + struct demangle_component *dc; + + switch (peek) + { + case 'N': + return d_nested_name (di); + + case 'Z': + return d_local_name (di); + + case 'L': + case 'U': + return d_unqualified_name (di); + + case 'S': + { + int subst; + + if (d_peek_next_char (di) != 't') + { + dc = d_substitution (di, 0); + subst = 1; + } + else + { + d_advance (di, 2); + dc = d_make_comp (di, DEMANGLE_COMPONENT_QUAL_NAME, + d_make_name (di, "std", 3), + d_unqualified_name (di)); + di->expansion += 3; + subst = 0; + } + + if (d_peek_char (di) != 'I') + { + /* The grammar does not permit this case to occur if we + called d_substitution() above (i.e., subst == 1). We + don't bother to check. */ + } + else + { + /* This is , which means that we just saw + , which is a substitution + candidate if we didn't just get it from a + substitution. */ + if (! subst) + { + if (! d_add_substitution (di, dc)) + return NULL; + } + dc = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, dc, + d_template_args (di)); + } + + return dc; + } + + default: + dc = d_unqualified_name (di); + if (d_peek_char (di) == 'I') + { + /* This is , which means that we just saw + , which is a substitution + candidate. */ + if (! d_add_substitution (di, dc)) + return NULL; + dc = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, dc, + d_template_args (di)); + } + return dc; + } +} + +/* ::= N [] E + ::= N [] E +*/ + +static struct demangle_component * +d_nested_name (struct d_info *di) +{ + struct demangle_component *ret; + struct demangle_component **pret; + + if (! d_check_char (di, 'N')) + return NULL; + + pret = d_cv_qualifiers (di, &ret, 1); + if (pret == NULL) + return NULL; + + *pret = d_prefix (di); + if (*pret == NULL) + return NULL; + + if (! d_check_char (di, 'E')) + return NULL; + + return ret; +} + +/* ::= + ::= + ::= + ::= + ::= + + ::= <(template) unqualified-name> + ::= + ::= +*/ + +static struct demangle_component * +d_prefix (struct d_info *di) +{ + struct demangle_component *ret = NULL; + + while (1) + { + char peek; + enum demangle_component_type comb_type; + struct demangle_component *dc; + + peek = d_peek_char (di); + if (peek == '\0') + return NULL; + + /* The older code accepts a here, but I don't see + that in the grammar. The older code does not accept a + here. */ + + comb_type = DEMANGLE_COMPONENT_QUAL_NAME; + if (IS_DIGIT (peek) + || IS_LOWER (peek) + || peek == 'C' + || peek == 'D' + || peek == 'U' + || peek == 'L') + dc = d_unqualified_name (di); + else if (peek == 'S') + dc = d_substitution (di, 1); + else if (peek == 'I') + { + if (ret == NULL) + return NULL; + comb_type = DEMANGLE_COMPONENT_TEMPLATE; + dc = d_template_args (di); + } + else if (peek == 'T') + dc = d_template_param (di); + else if (peek == 'E') + return ret; + else if (peek == 'M') + { + /* Initializer scope for a lambda. We don't need to represent + this; the normal code will just treat the variable as a type + scope, which gives appropriate output. */ + if (ret == NULL) + return NULL; + d_advance (di, 1); + continue; + } + else + return NULL; + + if (ret == NULL) + ret = dc; + else + ret = d_make_comp (di, comb_type, ret, dc); + + if (peek != 'S' && d_peek_char (di) != 'E') + { + if (! d_add_substitution (di, ret)) + return NULL; + } + } +} + +/* ::= + ::= + ::= + ::= + + ::= L +*/ + +static struct demangle_component * +d_unqualified_name (struct d_info *di) +{ + char peek; + + peek = d_peek_char (di); + if (IS_DIGIT (peek)) + return d_source_name (di); + else if (IS_LOWER (peek)) + { + struct demangle_component *ret; + + ret = d_operator_name (di); + if (ret != NULL && ret->type == DEMANGLE_COMPONENT_OPERATOR) + di->expansion += sizeof "operator" + ret->u.s_operator.op->len - 2; + return ret; + } + else if (peek == 'C' || peek == 'D') + return d_ctor_dtor_name (di); + else if (peek == 'L') + { + struct demangle_component * ret; + + d_advance (di, 1); + + ret = d_source_name (di); + if (ret == NULL) + return NULL; + if (! d_discriminator (di)) + return NULL; + return ret; + } + else if (peek == 'U') + { + switch (d_peek_next_char (di)) + { + case 'l': + return d_lambda (di); + case 't': + return d_unnamed_type (di); + default: + return NULL; + } + } + else + return NULL; +} + +/* ::= <(positive length) number> */ + +static struct demangle_component * +d_source_name (struct d_info *di) +{ + long len; + struct demangle_component *ret; + + len = d_number (di); + if (len <= 0) + return NULL; + ret = d_identifier (di, len); + di->last_name = ret; + return ret; +} + +/* number ::= [n] <(non-negative decimal integer)> */ + +static long +d_number (struct d_info *di) +{ + int negative; + char peek; + long ret; + + negative = 0; + peek = d_peek_char (di); + if (peek == 'n') + { + negative = 1; + d_advance (di, 1); + peek = d_peek_char (di); + } + + ret = 0; + while (1) + { + if (! IS_DIGIT (peek)) + { + if (negative) + ret = - ret; + return ret; + } + ret = ret * 10 + peek - '0'; + d_advance (di, 1); + peek = d_peek_char (di); + } +} + +/* Like d_number, but returns a demangle_component. */ + +static struct demangle_component * +d_number_component (struct d_info *di) +{ + struct demangle_component *ret = d_make_empty (di); + if (ret) + { + ret->type = DEMANGLE_COMPONENT_NUMBER; + ret->u.s_number.number = d_number (di); + } + return ret; +} + +/* identifier ::= <(unqualified source code identifier)> */ + +static struct demangle_component * +d_identifier (struct d_info *di, int len) +{ + const char *name; + + name = d_str (di); + + if (di->send - name < len) + return NULL; + + d_advance (di, len); + + /* A Java mangled name may have a trailing '$' if it is a C++ + keyword. This '$' is not included in the length count. We just + ignore the '$'. */ + if ((di->options & DMGL_JAVA) != 0 + && d_peek_char (di) == '$') + d_advance (di, 1); + + /* Look for something which looks like a gcc encoding of an + anonymous namespace, and replace it with a more user friendly + name. */ + if (len >= (int) ANONYMOUS_NAMESPACE_PREFIX_LEN + 2 + && memcmp (name, ANONYMOUS_NAMESPACE_PREFIX, + ANONYMOUS_NAMESPACE_PREFIX_LEN) == 0) + { + const char *s; + + s = name + ANONYMOUS_NAMESPACE_PREFIX_LEN; + if ((*s == '.' || *s == '_' || *s == '$') + && s[1] == 'N') + { + di->expansion -= len - sizeof "(anonymous namespace)"; + return d_make_name (di, "(anonymous namespace)", + sizeof "(anonymous namespace)" - 1); + } + } + + return d_make_name (di, name, len); +} + +/* operator_name ::= many different two character encodings. + ::= cv + ::= v +*/ + +#define NL(s) s, (sizeof s) - 1 + +CP_STATIC_IF_GLIBCPP_V3 +const struct demangle_operator_info cplus_demangle_operators[] = +{ + { "aN", NL ("&="), 2 }, + { "aS", NL ("="), 2 }, + { "aa", NL ("&&"), 2 }, + { "ad", NL ("&"), 1 }, + { "an", NL ("&"), 2 }, + { "cl", NL ("()"), 2 }, + { "cm", NL (","), 2 }, + { "co", NL ("~"), 1 }, + { "dV", NL ("/="), 2 }, + { "da", NL ("delete[]"), 1 }, + { "de", NL ("*"), 1 }, + { "dl", NL ("delete"), 1 }, + { "dt", NL ("."), 2 }, + { "dv", NL ("/"), 2 }, + { "eO", NL ("^="), 2 }, + { "eo", NL ("^"), 2 }, + { "eq", NL ("=="), 2 }, + { "ge", NL (">="), 2 }, + { "gt", NL (">"), 2 }, + { "ix", NL ("[]"), 2 }, + { "lS", NL ("<<="), 2 }, + { "le", NL ("<="), 2 }, + { "ls", NL ("<<"), 2 }, + { "lt", NL ("<"), 2 }, + { "mI", NL ("-="), 2 }, + { "mL", NL ("*="), 2 }, + { "mi", NL ("-"), 2 }, + { "ml", NL ("*"), 2 }, + { "mm", NL ("--"), 1 }, + { "na", NL ("new[]"), 1 }, + { "ne", NL ("!="), 2 }, + { "ng", NL ("-"), 1 }, + { "nt", NL ("!"), 1 }, + { "nw", NL ("new"), 1 }, + { "oR", NL ("|="), 2 }, + { "oo", NL ("||"), 2 }, + { "or", NL ("|"), 2 }, + { "pL", NL ("+="), 2 }, + { "pl", NL ("+"), 2 }, + { "pm", NL ("->*"), 2 }, + { "pp", NL ("++"), 1 }, + { "ps", NL ("+"), 1 }, + { "pt", NL ("->"), 2 }, + { "qu", NL ("?"), 3 }, + { "rM", NL ("%="), 2 }, + { "rS", NL (">>="), 2 }, + { "rm", NL ("%"), 2 }, + { "rs", NL (">>"), 2 }, + { "st", NL ("sizeof "), 1 }, + { "sz", NL ("sizeof "), 1 }, + { "at", NL ("alignof "), 1 }, + { "az", NL ("alignof "), 1 }, + { NULL, NULL, 0, 0 } +}; + +static struct demangle_component * +d_operator_name (struct d_info *di) +{ + char c1; + char c2; + + c1 = d_next_char (di); + c2 = d_next_char (di); + if (c1 == 'v' && IS_DIGIT (c2)) + return d_make_extended_operator (di, c2 - '0', d_source_name (di)); + else if (c1 == 'c' && c2 == 'v') + return d_make_comp (di, DEMANGLE_COMPONENT_CAST, + cplus_demangle_type (di), NULL); + else + { + /* LOW is the inclusive lower bound. */ + int low = 0; + /* HIGH is the exclusive upper bound. We subtract one to ignore + the sentinel at the end of the array. */ + int high = ((sizeof (cplus_demangle_operators) + / sizeof (cplus_demangle_operators[0])) + - 1); + + while (1) + { + int i; + const struct demangle_operator_info *p; + + i = low + (high - low) / 2; + p = cplus_demangle_operators + i; + + if (c1 == p->code[0] && c2 == p->code[1]) + return d_make_operator (di, p); + + if (c1 < p->code[0] || (c1 == p->code[0] && c2 < p->code[1])) + high = i; + else + low = i + 1; + if (low == high) + return NULL; + } + } +} + +static struct demangle_component * +d_make_character (struct d_info *di, int c) +{ + struct demangle_component *p; + p = d_make_empty (di); + if (p != NULL) + { + p->type = DEMANGLE_COMPONENT_CHARACTER; + p->u.s_character.character = c; + } + return p; +} + +static struct demangle_component * +d_java_resource (struct d_info *di) +{ + struct demangle_component *p = NULL; + struct demangle_component *next = NULL; + long len, i; + char c; + const char *str; + + len = d_number (di); + if (len <= 1) + return NULL; + + /* Eat the leading '_'. */ + if (d_next_char (di) != '_') + return NULL; + len--; + + str = d_str (di); + i = 0; + + while (len > 0) + { + c = str[i]; + if (!c) + return NULL; + + /* Each chunk is either a '$' escape... */ + if (c == '$') + { + i++; + switch (str[i++]) + { + case 'S': + c = '/'; + break; + case '_': + c = '.'; + break; + case '$': + c = '$'; + break; + default: + return NULL; + } + next = d_make_character (di, c); + d_advance (di, i); + str = d_str (di); + len -= i; + i = 0; + if (next == NULL) + return NULL; + } + /* ... or a sequence of characters. */ + else + { + while (i < len && str[i] && str[i] != '$') + i++; + + next = d_make_name (di, str, i); + d_advance (di, i); + str = d_str (di); + len -= i; + i = 0; + if (next == NULL) + return NULL; + } + + if (p == NULL) + p = next; + else + { + p = d_make_comp (di, DEMANGLE_COMPONENT_COMPOUND_NAME, p, next); + if (p == NULL) + return NULL; + } + } + + p = d_make_comp (di, DEMANGLE_COMPONENT_JAVA_RESOURCE, p, NULL); + + return p; +} + +/* ::= TV + ::= TT + ::= TI + ::= TS + ::= GV <(object) name> + ::= T <(base) encoding> + ::= Tc <(base) encoding> + Also g++ extensions: + ::= TC <(offset) number> _ <(base) type> + ::= TF + ::= TJ + ::= GR + ::= GA + ::= Gr +*/ + +static struct demangle_component * +d_special_name (struct d_info *di) +{ + di->expansion += 20; + if (d_check_char (di, 'T')) + { + switch (d_next_char (di)) + { + case 'V': + di->expansion -= 5; + return d_make_comp (di, DEMANGLE_COMPONENT_VTABLE, + cplus_demangle_type (di), NULL); + case 'T': + di->expansion -= 10; + return d_make_comp (di, DEMANGLE_COMPONENT_VTT, + cplus_demangle_type (di), NULL); + case 'I': + return d_make_comp (di, DEMANGLE_COMPONENT_TYPEINFO, + cplus_demangle_type (di), NULL); + case 'S': + return d_make_comp (di, DEMANGLE_COMPONENT_TYPEINFO_NAME, + cplus_demangle_type (di), NULL); + + case 'h': + if (! d_call_offset (di, 'h')) + return NULL; + return d_make_comp (di, DEMANGLE_COMPONENT_THUNK, + d_encoding (di, 0), NULL); + + case 'v': + if (! d_call_offset (di, 'v')) + return NULL; + return d_make_comp (di, DEMANGLE_COMPONENT_VIRTUAL_THUNK, + d_encoding (di, 0), NULL); + + case 'c': + if (! d_call_offset (di, '\0')) + return NULL; + if (! d_call_offset (di, '\0')) + return NULL; + return d_make_comp (di, DEMANGLE_COMPONENT_COVARIANT_THUNK, + d_encoding (di, 0), NULL); + + case 'C': + { + struct demangle_component *derived_type; + long offset; + struct demangle_component *base_type; + + derived_type = cplus_demangle_type (di); + offset = d_number (di); + if (offset < 0) + return NULL; + if (! d_check_char (di, '_')) + return NULL; + base_type = cplus_demangle_type (di); + /* We don't display the offset. FIXME: We should display + it in verbose mode. */ + di->expansion += 5; + return d_make_comp (di, DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE, + base_type, derived_type); + } + + case 'F': + return d_make_comp (di, DEMANGLE_COMPONENT_TYPEINFO_FN, + cplus_demangle_type (di), NULL); + case 'J': + return d_make_comp (di, DEMANGLE_COMPONENT_JAVA_CLASS, + cplus_demangle_type (di), NULL); + + default: + return NULL; + } + } + else if (d_check_char (di, 'G')) + { + switch (d_next_char (di)) + { + case 'V': + return d_make_comp (di, DEMANGLE_COMPONENT_GUARD, d_name (di), NULL); + + case 'R': + return d_make_comp (di, DEMANGLE_COMPONENT_REFTEMP, d_name (di), + NULL); + + case 'A': + return d_make_comp (di, DEMANGLE_COMPONENT_HIDDEN_ALIAS, + d_encoding (di, 0), NULL); + + case 'r': + return d_java_resource (di); + + default: + return NULL; + } + } + else + return NULL; +} + +/* ::= h _ + ::= v _ + + ::= <(offset) number> + + ::= <(offset) number> _ <(virtual offset) number> + + The C parameter, if not '\0', is a character we just read which is + the start of the . + + We don't display the offset information anywhere. FIXME: We should + display it in verbose mode. */ + +static int +d_call_offset (struct d_info *di, int c) +{ + if (c == '\0') + c = d_next_char (di); + + if (c == 'h') + d_number (di); + else if (c == 'v') + { + d_number (di); + if (! d_check_char (di, '_')) + return 0; + d_number (di); + } + else + return 0; + + if (! d_check_char (di, '_')) + return 0; + + return 1; +} + +/* ::= C1 + ::= C2 + ::= C3 + ::= D0 + ::= D1 + ::= D2 +*/ + +static struct demangle_component * +d_ctor_dtor_name (struct d_info *di) +{ + if (di->last_name != NULL) + { + if (di->last_name->type == DEMANGLE_COMPONENT_NAME) + di->expansion += di->last_name->u.s_name.len; + else if (di->last_name->type == DEMANGLE_COMPONENT_SUB_STD) + di->expansion += di->last_name->u.s_string.len; + } + switch (d_peek_char (di)) + { + case 'C': + { + enum gnu_v3_ctor_kinds kind; + + switch (d_peek_next_char (di)) + { + case '1': + kind = gnu_v3_complete_object_ctor; + break; + case '2': + kind = gnu_v3_base_object_ctor; + break; + case '3': + kind = gnu_v3_complete_object_allocating_ctor; + break; + default: + return NULL; + } + d_advance (di, 2); + return d_make_ctor (di, kind, di->last_name); + } + + case 'D': + { + enum gnu_v3_dtor_kinds kind; + + switch (d_peek_next_char (di)) + { + case '0': + kind = gnu_v3_deleting_dtor; + break; + case '1': + kind = gnu_v3_complete_object_dtor; + break; + case '2': + kind = gnu_v3_base_object_dtor; + break; + default: + return NULL; + } + d_advance (di, 2); + return d_make_dtor (di, kind, di->last_name); + } + + default: + return NULL; + } +} + +/* ::= + ::= + ::= + ::= + ::= + ::= + ::= + ::= + ::= + ::= P + ::= R + ::= O (C++0x) + ::= C + ::= G + ::= U + + ::= various one letter codes + ::= u +*/ + +CP_STATIC_IF_GLIBCPP_V3 +const struct demangle_builtin_type_info +cplus_demangle_builtin_types[D_BUILTIN_TYPE_COUNT] = +{ + /* a */ { NL ("signed char"), NL ("signed char"), D_PRINT_DEFAULT }, + /* b */ { NL ("bool"), NL ("boolean"), D_PRINT_BOOL }, + /* c */ { NL ("char"), NL ("byte"), D_PRINT_DEFAULT }, + /* d */ { NL ("double"), NL ("double"), D_PRINT_FLOAT }, + /* e */ { NL ("long double"), NL ("long double"), D_PRINT_FLOAT }, + /* f */ { NL ("float"), NL ("float"), D_PRINT_FLOAT }, + /* g */ { NL ("__float128"), NL ("__float128"), D_PRINT_FLOAT }, + /* h */ { NL ("unsigned char"), NL ("unsigned char"), D_PRINT_DEFAULT }, + /* i */ { NL ("int"), NL ("int"), D_PRINT_INT }, + /* j */ { NL ("unsigned int"), NL ("unsigned"), D_PRINT_UNSIGNED }, + /* k */ { NULL, 0, NULL, 0, D_PRINT_DEFAULT }, + /* l */ { NL ("long"), NL ("long"), D_PRINT_LONG }, + /* m */ { NL ("unsigned long"), NL ("unsigned long"), D_PRINT_UNSIGNED_LONG }, + /* n */ { NL ("__int128"), NL ("__int128"), D_PRINT_DEFAULT }, + /* o */ { NL ("unsigned __int128"), NL ("unsigned __int128"), + D_PRINT_DEFAULT }, + /* p */ { NULL, 0, NULL, 0, D_PRINT_DEFAULT }, + /* q */ { NULL, 0, NULL, 0, D_PRINT_DEFAULT }, + /* r */ { NULL, 0, NULL, 0, D_PRINT_DEFAULT }, + /* s */ { NL ("short"), NL ("short"), D_PRINT_DEFAULT }, + /* t */ { NL ("unsigned short"), NL ("unsigned short"), D_PRINT_DEFAULT }, + /* u */ { NULL, 0, NULL, 0, D_PRINT_DEFAULT }, + /* v */ { NL ("void"), NL ("void"), D_PRINT_VOID }, + /* w */ { NL ("wchar_t"), NL ("char"), D_PRINT_DEFAULT }, + /* x */ { NL ("long long"), NL ("long"), D_PRINT_LONG_LONG }, + /* y */ { NL ("unsigned long long"), NL ("unsigned long long"), + D_PRINT_UNSIGNED_LONG_LONG }, + /* z */ { NL ("..."), NL ("..."), D_PRINT_DEFAULT }, + /* 26 */ { NL ("decimal32"), NL ("decimal32"), D_PRINT_DEFAULT }, + /* 27 */ { NL ("decimal64"), NL ("decimal64"), D_PRINT_DEFAULT }, + /* 28 */ { NL ("decimal128"), NL ("decimal128"), D_PRINT_DEFAULT }, + /* 29 */ { NL ("half"), NL ("half"), D_PRINT_FLOAT }, + /* 30 */ { NL ("char16_t"), NL ("char16_t"), D_PRINT_DEFAULT }, + /* 31 */ { NL ("char32_t"), NL ("char32_t"), D_PRINT_DEFAULT }, + /* 32 */ { NL ("decltype(nullptr)"), NL ("decltype(nullptr)"), + D_PRINT_DEFAULT }, +}; + +CP_STATIC_IF_GLIBCPP_V3 +struct demangle_component * +cplus_demangle_type (struct d_info *di) +{ + char peek; + struct demangle_component *ret; + int can_subst; + + /* The ABI specifies that when CV-qualifiers are used, the base type + is substitutable, and the fully qualified type is substitutable, + but the base type with a strict subset of the CV-qualifiers is + not substitutable. The natural recursive implementation of the + CV-qualifiers would cause subsets to be substitutable, so instead + we pull them all off now. + + FIXME: The ABI says that order-insensitive vendor qualifiers + should be handled in the same way, but we have no way to tell + which vendor qualifiers are order-insensitive and which are + order-sensitive. So we just assume that they are all + order-sensitive. g++ 3.4 supports only one vendor qualifier, + __vector, and it treats it as order-sensitive when mangling + names. */ + + peek = d_peek_char (di); + if (peek == 'r' || peek == 'V' || peek == 'K') + { + struct demangle_component **pret; + + pret = d_cv_qualifiers (di, &ret, 0); + if (pret == NULL) + return NULL; + *pret = cplus_demangle_type (di); + if (! *pret || ! d_add_substitution (di, ret)) + return NULL; + return ret; + } + + can_subst = 1; + + switch (peek) + { + case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'g': + case 'h': case 'i': case 'j': case 'l': case 'm': case 'n': + case 'o': case 's': case 't': + case 'v': case 'w': case 'x': case 'y': case 'z': + ret = d_make_builtin_type (di, + &cplus_demangle_builtin_types[peek - 'a']); + di->expansion += ret->u.s_builtin.type->len; + can_subst = 0; + d_advance (di, 1); + break; + + case 'u': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_VENDOR_TYPE, + d_source_name (di), NULL); + break; + + case 'F': + ret = d_function_type (di); + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + case 'N': + case 'Z': + ret = d_class_enum_type (di); + break; + + case 'A': + ret = d_array_type (di); + break; + + case 'M': + ret = d_pointer_to_member_type (di); + break; + + case 'T': + ret = d_template_param (di); + if (d_peek_char (di) == 'I') + { + /* This is . The + part is a substitution + candidate. */ + if (! d_add_substitution (di, ret)) + return NULL; + ret = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, ret, + d_template_args (di)); + } + break; + + case 'S': + /* If this is a special substitution, then it is the start of + . */ + { + char peek_next; + + peek_next = d_peek_next_char (di); + if (IS_DIGIT (peek_next) + || peek_next == '_' + || IS_UPPER (peek_next)) + { + ret = d_substitution (di, 0); + /* The substituted name may have been a template name and + may be followed by tepmlate args. */ + if (d_peek_char (di) == 'I') + ret = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, ret, + d_template_args (di)); + else + can_subst = 0; + } + else + { + ret = d_class_enum_type (di); + /* If the substitution was a complete type, then it is not + a new substitution candidate. However, if the + substitution was followed by template arguments, then + the whole thing is a substitution candidate. */ + if (ret != NULL && ret->type == DEMANGLE_COMPONENT_SUB_STD) + can_subst = 0; + } + } + break; + + case 'O': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_RVALUE_REFERENCE, + cplus_demangle_type (di), NULL); + break; + + case 'P': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_POINTER, + cplus_demangle_type (di), NULL); + break; + + case 'R': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_REFERENCE, + cplus_demangle_type (di), NULL); + break; + + case 'C': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_COMPLEX, + cplus_demangle_type (di), NULL); + break; + + case 'G': + d_advance (di, 1); + ret = d_make_comp (di, DEMANGLE_COMPONENT_IMAGINARY, + cplus_demangle_type (di), NULL); + break; + + case 'U': + d_advance (di, 1); + ret = d_source_name (di); + ret = d_make_comp (di, DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL, + cplus_demangle_type (di), ret); + break; + + case 'D': + can_subst = 0; + d_advance (di, 1); + peek = d_next_char (di); + switch (peek) + { + case 'T': + case 't': + /* decltype (expression) */ + ret = d_make_comp (di, DEMANGLE_COMPONENT_DECLTYPE, + d_expression (di), NULL); + if (ret && d_next_char (di) != 'E') + ret = NULL; + break; + + case 'p': + /* Pack expansion. */ + ret = d_make_comp (di, DEMANGLE_COMPONENT_PACK_EXPANSION, + cplus_demangle_type (di), NULL); + break; + + case 'f': + /* 32-bit decimal floating point */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[26]); + di->expansion += ret->u.s_builtin.type->len; + break; + case 'd': + /* 64-bit DFP */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[27]); + di->expansion += ret->u.s_builtin.type->len; + break; + case 'e': + /* 128-bit DFP */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[28]); + di->expansion += ret->u.s_builtin.type->len; + break; + case 'h': + /* 16-bit half-precision FP */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[29]); + di->expansion += ret->u.s_builtin.type->len; + break; + case 's': + /* char16_t */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[30]); + di->expansion += ret->u.s_builtin.type->len; + break; + case 'i': + /* char32_t */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[31]); + di->expansion += ret->u.s_builtin.type->len; + break; + + case 'F': + /* Fixed point types. DF */ + ret = d_make_empty (di); + ret->type = DEMANGLE_COMPONENT_FIXED_TYPE; + if ((ret->u.s_fixed.accum = IS_DIGIT (d_peek_char (di)))) + /* For demangling we don't care about the bits. */ + d_number (di); + ret->u.s_fixed.length = cplus_demangle_type (di); + if (ret->u.s_fixed.length == NULL) + return NULL; + d_number (di); + peek = d_next_char (di); + ret->u.s_fixed.sat = (peek == 's'); + break; + + case 'v': + ret = d_vector_type (di); + break; + + case 'n': + /* decltype(nullptr) */ + ret = d_make_builtin_type (di, &cplus_demangle_builtin_types[32]); + di->expansion += ret->u.s_builtin.type->len; + break; + + default: + return NULL; + } + break; + + default: + return NULL; + } + + if (can_subst) + { + if (! d_add_substitution (di, ret)) + return NULL; + } + + return ret; +} + +/* ::= [r] [V] [K] */ + +static struct demangle_component ** +d_cv_qualifiers (struct d_info *di, + struct demangle_component **pret, int member_fn) +{ + char peek; + + peek = d_peek_char (di); + while (peek == 'r' || peek == 'V' || peek == 'K') + { + enum demangle_component_type t; + + d_advance (di, 1); + if (peek == 'r') + { + t = (member_fn + ? DEMANGLE_COMPONENT_RESTRICT_THIS + : DEMANGLE_COMPONENT_RESTRICT); + di->expansion += sizeof "restrict"; + } + else if (peek == 'V') + { + t = (member_fn + ? DEMANGLE_COMPONENT_VOLATILE_THIS + : DEMANGLE_COMPONENT_VOLATILE); + di->expansion += sizeof "volatile"; + } + else + { + t = (member_fn + ? DEMANGLE_COMPONENT_CONST_THIS + : DEMANGLE_COMPONENT_CONST); + di->expansion += sizeof "const"; + } + + *pret = d_make_comp (di, t, NULL, NULL); + if (*pret == NULL) + return NULL; + pret = &d_left (*pret); + + peek = d_peek_char (di); + } + + return pret; +} + +/* ::= F [Y] E */ + +static struct demangle_component * +d_function_type (struct d_info *di) +{ + struct demangle_component *ret; + + if (! d_check_char (di, 'F')) + return NULL; + if (d_peek_char (di) == 'Y') + { + /* Function has C linkage. We don't print this information. + FIXME: We should print it in verbose mode. */ + d_advance (di, 1); + } + ret = d_bare_function_type (di, 1); + if (! d_check_char (di, 'E')) + return NULL; + return ret; +} + +/* + */ + +static struct demangle_component * +d_parmlist (struct d_info *di) +{ + struct demangle_component *tl; + struct demangle_component **ptl; + + tl = NULL; + ptl = &tl; + while (1) + { + struct demangle_component *type; + + char peek = d_peek_char (di); + if (peek == '\0' || peek == 'E') + break; + type = cplus_demangle_type (di); + if (type == NULL) + return NULL; + *ptl = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, type, NULL); + if (*ptl == NULL) + return NULL; + ptl = &d_right (*ptl); + } + + /* There should be at least one parameter type besides the optional + return type. A function which takes no arguments will have a + single parameter type void. */ + if (tl == NULL) + return NULL; + + /* If we have a single parameter type void, omit it. */ + if (d_right (tl) == NULL + && d_left (tl)->type == DEMANGLE_COMPONENT_BUILTIN_TYPE + && d_left (tl)->u.s_builtin.type->print == D_PRINT_VOID) + { + di->expansion -= d_left (tl)->u.s_builtin.type->len; + d_left (tl) = NULL; + } + + return tl; +} + +/* ::= [J]+ */ + +static struct demangle_component * +d_bare_function_type (struct d_info *di, int has_return_type) +{ + struct demangle_component *return_type; + struct demangle_component *tl; + char peek; + + /* Detect special qualifier indicating that the first argument + is the return type. */ + peek = d_peek_char (di); + if (peek == 'J') + { + d_advance (di, 1); + has_return_type = 1; + } + + if (has_return_type) + { + return_type = cplus_demangle_type (di); + if (return_type == NULL) + return NULL; + } + else + return_type = NULL; + + tl = d_parmlist (di); + if (tl == NULL) + return NULL; + + return d_make_comp (di, DEMANGLE_COMPONENT_FUNCTION_TYPE, + return_type, tl); +} + +/* ::= */ + +static struct demangle_component * +d_class_enum_type (struct d_info *di) +{ + return d_name (di); +} + +/* ::= A <(positive dimension) number> _ <(element) type> + ::= A [<(dimension) expression>] _ <(element) type> +*/ + +static struct demangle_component * +d_array_type (struct d_info *di) +{ + char peek; + struct demangle_component *dim; + + if (! d_check_char (di, 'A')) + return NULL; + + peek = d_peek_char (di); + if (peek == '_') + dim = NULL; + else if (IS_DIGIT (peek)) + { + const char *s; + + s = d_str (di); + do + { + d_advance (di, 1); + peek = d_peek_char (di); + } + while (IS_DIGIT (peek)); + dim = d_make_name (di, s, d_str (di) - s); + if (dim == NULL) + return NULL; + } + else + { + dim = d_expression (di); + if (dim == NULL) + return NULL; + } + + if (! d_check_char (di, '_')) + return NULL; + + return d_make_comp (di, DEMANGLE_COMPONENT_ARRAY_TYPE, dim, + cplus_demangle_type (di)); +} + +/* ::= Dv _ + ::= Dv _ _ */ + +static struct demangle_component * +d_vector_type (struct d_info *di) +{ + char peek; + struct demangle_component *dim; + + peek = d_peek_char (di); + if (peek == '_') + { + d_advance (di, 1); + dim = d_expression (di); + } + else + dim = d_number_component (di); + + if (dim == NULL) + return NULL; + + if (! d_check_char (di, '_')) + return NULL; + + return d_make_comp (di, DEMANGLE_COMPONENT_VECTOR_TYPE, dim, + cplus_demangle_type (di)); +} + +/* ::= M <(class) type> <(member) type> */ + +static struct demangle_component * +d_pointer_to_member_type (struct d_info *di) +{ + struct demangle_component *cl; + struct demangle_component *mem; + struct demangle_component **pmem; + + if (! d_check_char (di, 'M')) + return NULL; + + cl = cplus_demangle_type (di); + + /* The ABI specifies that any type can be a substitution source, and + that M is followed by two types, and that when a CV-qualified + type is seen both the base type and the CV-qualified types are + substitution sources. The ABI also specifies that for a pointer + to a CV-qualified member function, the qualifiers are attached to + the second type. Given the grammar, a plain reading of the ABI + suggests that both the CV-qualified member function and the + non-qualified member function are substitution sources. However, + g++ does not work that way. g++ treats only the CV-qualified + member function as a substitution source. FIXME. So to work + with g++, we need to pull off the CV-qualifiers here, in order to + avoid calling add_substitution() in cplus_demangle_type(). But + for a CV-qualified member which is not a function, g++ does + follow the ABI, so we need to handle that case here by calling + d_add_substitution ourselves. */ + + pmem = d_cv_qualifiers (di, &mem, 1); + if (pmem == NULL) + return NULL; + *pmem = cplus_demangle_type (di); + if (*pmem == NULL) + return NULL; + + if (pmem != &mem && (*pmem)->type != DEMANGLE_COMPONENT_FUNCTION_TYPE) + { + if (! d_add_substitution (di, mem)) + return NULL; + } + + return d_make_comp (di, DEMANGLE_COMPONENT_PTRMEM_TYPE, cl, mem); +} + +/* _ */ + +static long +d_compact_number (struct d_info *di) +{ + long num; + if (d_peek_char (di) == '_') + num = 0; + else if (d_peek_char (di) == 'n') + return -1; + else + num = d_number (di) + 1; + + if (! d_check_char (di, '_')) + return -1; + return num; +} + +/* ::= T_ + ::= T <(parameter-2 non-negative) number> _ +*/ + +static struct demangle_component * +d_template_param (struct d_info *di) +{ + long param; + + if (! d_check_char (di, 'T')) + return NULL; + + param = d_compact_number (di); + if (param < 0) + return NULL; + + ++di->did_subs; + + return d_make_template_param (di, param); +} + +/* ::= I + E */ + +static struct demangle_component * +d_template_args (struct d_info *di) +{ + struct demangle_component *hold_last_name; + struct demangle_component *al; + struct demangle_component **pal; + + /* Preserve the last name we saw--don't let the template arguments + clobber it, as that would give us the wrong name for a subsequent + constructor or destructor. */ + hold_last_name = di->last_name; + + if (! d_check_char (di, 'I')) + return NULL; + + if (d_peek_char (di) == 'E') + { + /* An argument pack can be empty. */ + d_advance (di, 1); + return d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE_ARGLIST, NULL, NULL); + } + + al = NULL; + pal = &al; + while (1) + { + struct demangle_component *a; + + a = d_template_arg (di); + if (a == NULL) + return NULL; + + *pal = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE_ARGLIST, a, NULL); + if (*pal == NULL) + return NULL; + pal = &d_right (*pal); + + if (d_peek_char (di) == 'E') + { + d_advance (di, 1); + break; + } + } + + di->last_name = hold_last_name; + + return al; +} + +/* ::= + ::= X E + ::= +*/ + +static struct demangle_component * +d_template_arg (struct d_info *di) +{ + struct demangle_component *ret; + + switch (d_peek_char (di)) + { + case 'X': + d_advance (di, 1); + ret = d_expression (di); + if (! d_check_char (di, 'E')) + return NULL; + return ret; + + case 'L': + return d_expr_primary (di); + + case 'I': + /* An argument pack. */ + return d_template_args (di); + + default: + return cplus_demangle_type (di); + } +} + +/* Subroutine of ::= cl + E */ + +static struct demangle_component * +d_exprlist (struct d_info *di) +{ + struct demangle_component *list = NULL; + struct demangle_component **p = &list; + + if (d_peek_char (di) == 'E') + { + d_advance (di, 1); + return d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, NULL, NULL); + } + + while (1) + { + struct demangle_component *arg = d_expression (di); + if (arg == NULL) + return NULL; + + *p = d_make_comp (di, DEMANGLE_COMPONENT_ARGLIST, arg, NULL); + if (*p == NULL) + return NULL; + p = &d_right (*p); + + if (d_peek_char (di) == 'E') + { + d_advance (di, 1); + break; + } + } + + return list; +} + +/* ::= <(unary) operator-name> + ::= <(binary) operator-name> + ::= <(trinary) operator-name> + ::= cl + E + ::= st + ::= + ::= sr + ::= sr + ::= +*/ + +static struct demangle_component * +d_expression (struct d_info *di) +{ + char peek; + + peek = d_peek_char (di); + if (peek == 'L') + return d_expr_primary (di); + else if (peek == 'T') + return d_template_param (di); + else if (peek == 's' && d_peek_next_char (di) == 'r') + { + struct demangle_component *type; + struct demangle_component *name; + + d_advance (di, 2); + type = cplus_demangle_type (di); + name = d_unqualified_name (di); + if (d_peek_char (di) != 'I') + return d_make_comp (di, DEMANGLE_COMPONENT_QUAL_NAME, type, name); + else + return d_make_comp (di, DEMANGLE_COMPONENT_QUAL_NAME, type, + d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, name, + d_template_args (di))); + } + else if (peek == 's' && d_peek_next_char (di) == 'p') + { + d_advance (di, 2); + return d_make_comp (di, DEMANGLE_COMPONENT_PACK_EXPANSION, + d_expression (di), NULL); + } + else if (peek == 'f' && d_peek_next_char (di) == 'p') + { + /* Function parameter used in a late-specified return type. */ + int index; + d_advance (di, 2); + index = d_compact_number (di); + if (index < 0) + return NULL; + + return d_make_function_param (di, index); + } + else if (IS_DIGIT (peek) + || (peek == 'o' && d_peek_next_char (di) == 'n')) + { + /* We can get an unqualified name as an expression in the case of + a dependent function call, i.e. decltype(f(t)). */ + struct demangle_component *name; + + if (peek == 'o') + /* operator-function-id, i.e. operator+(t). */ + d_advance (di, 2); + + name = d_unqualified_name (di); + if (name == NULL) + return NULL; + if (d_peek_char (di) == 'I') + return d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, name, + d_template_args (di)); + else + return name; + } + else + { + struct demangle_component *op; + int args; + + op = d_operator_name (di); + if (op == NULL) + return NULL; + + if (op->type == DEMANGLE_COMPONENT_OPERATOR) + di->expansion += op->u.s_operator.op->len - 2; + + if (op->type == DEMANGLE_COMPONENT_OPERATOR + && strcmp (op->u.s_operator.op->code, "st") == 0) + return d_make_comp (di, DEMANGLE_COMPONENT_UNARY, op, + cplus_demangle_type (di)); + + switch (op->type) + { + default: + return NULL; + case DEMANGLE_COMPONENT_OPERATOR: + args = op->u.s_operator.op->args; + break; + case DEMANGLE_COMPONENT_EXTENDED_OPERATOR: + args = op->u.s_extended_operator.args; + break; + case DEMANGLE_COMPONENT_CAST: + args = 1; + break; + } + + switch (args) + { + case 1: + { + struct demangle_component *operand; + if (op->type == DEMANGLE_COMPONENT_CAST + && d_check_char (di, '_')) + operand = d_exprlist (di); + else + operand = d_expression (di); + return d_make_comp (di, DEMANGLE_COMPONENT_UNARY, op, + operand); + } + case 2: + { + struct demangle_component *left; + struct demangle_component *right; + const char *code = op->u.s_operator.op->code; + + left = d_expression (di); + if (!strcmp (code, "cl")) + right = d_exprlist (di); + else if (!strcmp (code, "dt") || !strcmp (code, "pt")) + { + right = d_unqualified_name (di); + if (d_peek_char (di) == 'I') + right = d_make_comp (di, DEMANGLE_COMPONENT_TEMPLATE, + right, d_template_args (di)); + } + else + right = d_expression (di); + + return d_make_comp (di, DEMANGLE_COMPONENT_BINARY, op, + d_make_comp (di, + DEMANGLE_COMPONENT_BINARY_ARGS, + left, right)); + } + case 3: + { + struct demangle_component *first; + struct demangle_component *second; + + first = d_expression (di); + second = d_expression (di); + return d_make_comp (di, DEMANGLE_COMPONENT_TRINARY, op, + d_make_comp (di, + DEMANGLE_COMPONENT_TRINARY_ARG1, + first, + d_make_comp (di, + DEMANGLE_COMPONENT_TRINARY_ARG2, + second, + d_expression (di)))); + } + default: + return NULL; + } + } +} + +/* ::= L <(value) number> E + ::= L <(value) float> E + ::= L E +*/ + +static struct demangle_component * +d_expr_primary (struct d_info *di) +{ + struct demangle_component *ret; + + if (! d_check_char (di, 'L')) + return NULL; + if (d_peek_char (di) == '_' + /* Workaround for G++ bug; see comment in write_template_arg. */ + || d_peek_char (di) == 'Z') + ret = cplus_demangle_mangled_name (di, 0); + else + { + struct demangle_component *type; + enum demangle_component_type t; + const char *s; + + type = cplus_demangle_type (di); + if (type == NULL) + return NULL; + + /* If we have a type we know how to print, we aren't going to + print the type name itself. */ + if (type->type == DEMANGLE_COMPONENT_BUILTIN_TYPE + && type->u.s_builtin.type->print != D_PRINT_DEFAULT) + di->expansion -= type->u.s_builtin.type->len; + + /* Rather than try to interpret the literal value, we just + collect it as a string. Note that it's possible to have a + floating point literal here. The ABI specifies that the + format of such literals is machine independent. That's fine, + but what's not fine is that versions of g++ up to 3.2 with + -fabi-version=1 used upper case letters in the hex constant, + and dumped out gcc's internal representation. That makes it + hard to tell where the constant ends, and hard to dump the + constant in any readable form anyhow. We don't attempt to + handle these cases. */ + + t = DEMANGLE_COMPONENT_LITERAL; + if (d_peek_char (di) == 'n') + { + t = DEMANGLE_COMPONENT_LITERAL_NEG; + d_advance (di, 1); + } + s = d_str (di); + while (d_peek_char (di) != 'E') + { + if (d_peek_char (di) == '\0') + return NULL; + d_advance (di, 1); + } + ret = d_make_comp (di, t, type, d_make_name (di, s, d_str (di) - s)); + } + if (! d_check_char (di, 'E')) + return NULL; + return ret; +} + +/* ::= Z <(function) encoding> E <(entity) name> [] + ::= Z <(function) encoding> E s [] +*/ + +static struct demangle_component * +d_local_name (struct d_info *di) +{ + struct demangle_component *function; + + if (! d_check_char (di, 'Z')) + return NULL; + + function = d_encoding (di, 0); + + if (! d_check_char (di, 'E')) + return NULL; + + if (d_peek_char (di) == 's') + { + d_advance (di, 1); + if (! d_discriminator (di)) + return NULL; + return d_make_comp (di, DEMANGLE_COMPONENT_LOCAL_NAME, function, + d_make_name (di, "string literal", + sizeof "string literal" - 1)); + } + else + { + struct demangle_component *name; + int num = -1; + + if (d_peek_char (di) == 'd') + { + /* Default argument scope: d _. */ + d_advance (di, 1); + num = d_compact_number (di); + if (num < 0) + return NULL; + } + + name = d_name (di); + if (name) + switch (name->type) + { + /* Lambdas and unnamed types have internal discriminators. */ + case DEMANGLE_COMPONENT_LAMBDA: + case DEMANGLE_COMPONENT_UNNAMED_TYPE: + break; + default: + if (! d_discriminator (di)) + return NULL; + } + if (num >= 0) + name = d_make_default_arg (di, num, name); + return d_make_comp (di, DEMANGLE_COMPONENT_LOCAL_NAME, function, name); + } +} + +/* ::= _ <(non-negative) number> + + We demangle the discriminator, but we don't print it out. FIXME: + We should print it out in verbose mode. */ + +static int +d_discriminator (struct d_info *di) +{ + long discrim; + + if (d_peek_char (di) != '_') + return 1; + d_advance (di, 1); + discrim = d_number (di); + if (discrim < 0) + return 0; + return 1; +} + +/* ::= Ul E [ ] _ */ + +static struct demangle_component * +d_lambda (struct d_info *di) +{ + struct demangle_component *tl; + struct demangle_component *ret; + int num; + + if (! d_check_char (di, 'U')) + return NULL; + if (! d_check_char (di, 'l')) + return NULL; + + tl = d_parmlist (di); + if (tl == NULL) + return NULL; + + if (! d_check_char (di, 'E')) + return NULL; + + num = d_compact_number (di); + if (num < 0) + return NULL; + + ret = d_make_empty (di); + if (ret) + { + ret->type = DEMANGLE_COMPONENT_LAMBDA; + ret->u.s_unary_num.sub = tl; + ret->u.s_unary_num.num = num; + } + + if (! d_add_substitution (di, ret)) + return NULL; + + return ret; +} + +/* ::= Ut [ ] _ */ + +static struct demangle_component * +d_unnamed_type (struct d_info *di) +{ + struct demangle_component *ret; + long num; + + if (! d_check_char (di, 'U')) + return NULL; + if (! d_check_char (di, 't')) + return NULL; + + num = d_compact_number (di); + if (num < 0) + return NULL; + + ret = d_make_empty (di); + if (ret) + { + ret->type = DEMANGLE_COMPONENT_UNNAMED_TYPE; + ret->u.s_number.number = num; + } + + if (! d_add_substitution (di, ret)) + return NULL; + + return ret; +} + +/* Add a new substitution. */ + +static int +d_add_substitution (struct d_info *di, struct demangle_component *dc) +{ + if (dc == NULL) + return 0; + if (di->next_sub >= di->num_subs) + return 0; + di->subs[di->next_sub] = dc; + ++di->next_sub; + return 1; +} + +/* ::= S _ + ::= S_ + ::= St + ::= Sa + ::= Sb + ::= Ss + ::= Si + ::= So + ::= Sd + + If PREFIX is non-zero, then this type is being used as a prefix in + a qualified name. In this case, for the standard substitutions, we + need to check whether we are being used as a prefix for a + constructor or destructor, and return a full template name. + Otherwise we will get something like std::iostream::~iostream() + which does not correspond particularly well to any function which + actually appears in the source. +*/ + +static const struct d_standard_sub_info standard_subs[] = +{ + { 't', NL ("std"), + NL ("std"), + NULL, 0 }, + { 'a', NL ("std::allocator"), + NL ("std::allocator"), + NL ("allocator") }, + { 'b', NL ("std::basic_string"), + NL ("std::basic_string"), + NL ("basic_string") }, + { 's', NL ("std::string"), + NL ("std::basic_string, std::allocator >"), + NL ("basic_string") }, + { 'i', NL ("std::istream"), + NL ("std::basic_istream >"), + NL ("basic_istream") }, + { 'o', NL ("std::ostream"), + NL ("std::basic_ostream >"), + NL ("basic_ostream") }, + { 'd', NL ("std::iostream"), + NL ("std::basic_iostream >"), + NL ("basic_iostream") } +}; + +static struct demangle_component * +d_substitution (struct d_info *di, int prefix) +{ + char c; + + if (! d_check_char (di, 'S')) + return NULL; + + c = d_next_char (di); + if (c == '_' || IS_DIGIT (c) || IS_UPPER (c)) + { + unsigned int id; + + id = 0; + if (c != '_') + { + do + { + unsigned int new_id; + + if (IS_DIGIT (c)) + new_id = id * 36 + c - '0'; + else if (IS_UPPER (c)) + new_id = id * 36 + c - 'A' + 10; + else + return NULL; + if (new_id < id) + return NULL; + id = new_id; + c = d_next_char (di); + } + while (c != '_'); + + ++id; + } + + if (id >= (unsigned int) di->next_sub) + return NULL; + + ++di->did_subs; + + return di->subs[id]; + } + else + { + int verbose; + const struct d_standard_sub_info *p; + const struct d_standard_sub_info *pend; + + verbose = (di->options & DMGL_VERBOSE) != 0; + if (! verbose && prefix) + { + char peek; + + peek = d_peek_char (di); + if (peek == 'C' || peek == 'D') + verbose = 1; + } + + pend = (&standard_subs[0] + + sizeof standard_subs / sizeof standard_subs[0]); + for (p = &standard_subs[0]; p < pend; ++p) + { + if (c == p->code) + { + const char *s; + int len; + + if (p->set_last_name != NULL) + di->last_name = d_make_sub (di, p->set_last_name, + p->set_last_name_len); + if (verbose) + { + s = p->full_expansion; + len = p->full_len; + } + else + { + s = p->simple_expansion; + len = p->simple_len; + } + di->expansion += len; + return d_make_sub (di, s, len); + } + } + + return NULL; + } +} + +/* Initialize a growable string. */ + +static void +d_growable_string_init (struct d_growable_string *dgs, size_t estimate) +{ + dgs->buf = NULL; + dgs->len = 0; + dgs->alc = 0; + dgs->allocation_failure = 0; + + if (estimate > 0) + d_growable_string_resize (dgs, estimate); +} + +/* Grow a growable string to a given size. */ + +static inline void +d_growable_string_resize (struct d_growable_string *dgs, size_t need) +{ + size_t newalc; + char *newbuf; + + if (dgs->allocation_failure) + return; + + /* Start allocation at two bytes to avoid any possibility of confusion + with the special value of 1 used as a return in *palc to indicate + allocation failures. */ + newalc = dgs->alc > 0 ? dgs->alc : 2; + while (newalc < need) + newalc <<= 1; + + newbuf = (char *) realloc (dgs->buf, newalc); + if (newbuf == NULL) + { + free (dgs->buf); + dgs->buf = NULL; + dgs->len = 0; + dgs->alc = 0; + dgs->allocation_failure = 1; + return; + } + dgs->buf = newbuf; + dgs->alc = newalc; +} + +/* Append a buffer to a growable string. */ + +static inline void +d_growable_string_append_buffer (struct d_growable_string *dgs, + const char *s, size_t l) +{ + size_t need; + + need = dgs->len + l + 1; + if (need > dgs->alc) + d_growable_string_resize (dgs, need); + + if (dgs->allocation_failure) + return; + + memcpy (dgs->buf + dgs->len, s, l); + dgs->buf[dgs->len + l] = '\0'; + dgs->len += l; +} + +/* Bridge growable strings to the callback mechanism. */ + +static void +d_growable_string_callback_adapter (const char *s, size_t l, void *opaque) +{ + struct d_growable_string *dgs = (struct d_growable_string*) opaque; + + d_growable_string_append_buffer (dgs, s, l); +} + +/* Initialize a print information structure. */ + +static void +d_print_init (struct d_print_info *dpi, demangle_callbackref callback, + void *opaque) +{ + dpi->len = 0; + dpi->last_char = '\0'; + dpi->templates = NULL; + dpi->modifiers = NULL; + dpi->flush_count = 0; + + dpi->callback = callback; + dpi->opaque = opaque; + + dpi->demangle_failure = 0; +} + +/* Indicate that an error occurred during printing, and test for error. */ + +static inline void +d_print_error (struct d_print_info *dpi) +{ + dpi->demangle_failure = 1; +} + +static inline int +d_print_saw_error (struct d_print_info *dpi) +{ + return dpi->demangle_failure != 0; +} + +/* Flush buffered characters to the callback. */ + +static inline void +d_print_flush (struct d_print_info *dpi) +{ + dpi->buf[dpi->len] = '\0'; + dpi->callback (dpi->buf, dpi->len, dpi->opaque); + dpi->len = 0; + dpi->flush_count++; +} + +/* Append characters and buffers for printing. */ + +static inline void +d_append_char (struct d_print_info *dpi, char c) +{ + if (dpi->len == sizeof (dpi->buf) - 1) + d_print_flush (dpi); + + dpi->buf[dpi->len++] = c; + dpi->last_char = c; +} + +static inline void +d_append_buffer (struct d_print_info *dpi, const char *s, size_t l) +{ + size_t i; + + for (i = 0; i < l; i++) + d_append_char (dpi, s[i]); +} + +static inline void +d_append_string (struct d_print_info *dpi, const char *s) +{ + d_append_buffer (dpi, s, strlen (s)); +} + +static inline void +d_append_num (struct d_print_info *dpi, long l) +{ + char buf[25]; + sprintf (buf,"%ld", l); + d_append_string (dpi, buf); +} + +static inline char +d_last_char (struct d_print_info *dpi) +{ + return dpi->last_char; +} + +/* Turn components into a human readable string. OPTIONS is the + options bits passed to the demangler. DC is the tree to print. + CALLBACK is a function to call to flush demangled string segments + as they fill the intermediate buffer, and OPAQUE is a generalized + callback argument. On success, this returns 1. On failure, + it returns 0, indicating a bad parse. It does not use heap + memory to build an output string, so cannot encounter memory + allocation failure. */ + +CP_STATIC_IF_GLIBCPP_V3 +int +cplus_demangle_print_callback (int options, + const struct demangle_component *dc, + demangle_callbackref callback, void *opaque) +{ + struct d_print_info dpi; + + d_print_init (&dpi, callback, opaque); + + d_print_comp (&dpi, options, dc); + + d_print_flush (&dpi); + + return ! d_print_saw_error (&dpi); +} + +/* Turn components into a human readable string. OPTIONS is the + options bits passed to the demangler. DC is the tree to print. + ESTIMATE is a guess at the length of the result. This returns a + string allocated by malloc, or NULL on error. On success, this + sets *PALC to the size of the allocated buffer. On failure, this + sets *PALC to 0 for a bad parse, or to 1 for a memory allocation + failure. */ + +CP_STATIC_IF_GLIBCPP_V3 +char * +cplus_demangle_print (int options, const struct demangle_component *dc, + int estimate, size_t *palc) +{ + struct d_growable_string dgs; + + d_growable_string_init (&dgs, estimate); + + if (! cplus_demangle_print_callback (options, dc, + d_growable_string_callback_adapter, + &dgs)) + { + free (dgs.buf); + *palc = 0; + return NULL; + } + + *palc = dgs.allocation_failure ? 1 : dgs.alc; + return dgs.buf; +} + +/* Returns the I'th element of the template arglist ARGS, or NULL on + failure. */ + +static struct demangle_component * +d_index_template_argument (struct demangle_component *args, int i) +{ + struct demangle_component *a; + + for (a = args; + a != NULL; + a = d_right (a)) + { + if (a->type != DEMANGLE_COMPONENT_TEMPLATE_ARGLIST) + return NULL; + if (i <= 0) + break; + --i; + } + if (i != 0 || a == NULL) + return NULL; + + return d_left (a); +} + +/* Returns the template argument from the current context indicated by DC, + which is a DEMANGLE_COMPONENT_TEMPLATE_PARAM, or NULL. */ + +static struct demangle_component * +d_lookup_template_argument (struct d_print_info *dpi, + const struct demangle_component *dc) +{ + if (dpi->templates == NULL) + { + d_print_error (dpi); + return NULL; + } + + return d_index_template_argument + (d_right (dpi->templates->template_decl), + dc->u.s_number.number); +} + +/* Returns a template argument pack used in DC (any will do), or NULL. */ + +static struct demangle_component * +d_find_pack (struct d_print_info *dpi, + const struct demangle_component *dc) +{ + struct demangle_component *a; + if (dc == NULL) + return NULL; + + switch (dc->type) + { + case DEMANGLE_COMPONENT_TEMPLATE_PARAM: + a = d_lookup_template_argument (dpi, dc); + if (a && a->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST) + return a; + return NULL; + + case DEMANGLE_COMPONENT_PACK_EXPANSION: + return NULL; + + case DEMANGLE_COMPONENT_LAMBDA: + case DEMANGLE_COMPONENT_NAME: + case DEMANGLE_COMPONENT_OPERATOR: + case DEMANGLE_COMPONENT_BUILTIN_TYPE: + case DEMANGLE_COMPONENT_SUB_STD: + case DEMANGLE_COMPONENT_CHARACTER: + case DEMANGLE_COMPONENT_FUNCTION_PARAM: + return NULL; + + case DEMANGLE_COMPONENT_EXTENDED_OPERATOR: + return d_find_pack (dpi, dc->u.s_extended_operator.name); + case DEMANGLE_COMPONENT_CTOR: + return d_find_pack (dpi, dc->u.s_ctor.name); + case DEMANGLE_COMPONENT_DTOR: + return d_find_pack (dpi, dc->u.s_dtor.name); + + default: + a = d_find_pack (dpi, d_left (dc)); + if (a) + return a; + return d_find_pack (dpi, d_right (dc)); + } +} + +/* Returns the length of the template argument pack DC. */ + +static int +d_pack_length (const struct demangle_component *dc) +{ + int count = 0; + while (dc && dc->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST + && d_left (dc) != NULL) + { + ++count; + dc = d_right (dc); + } + return count; +} + +/* DC is a component of a mangled expression. Print it, wrapped in parens + if needed. */ + +static void +d_print_subexpr (struct d_print_info *dpi, int options, + const struct demangle_component *dc) +{ + int simple = 0; + if (dc->type == DEMANGLE_COMPONENT_NAME + || dc->type == DEMANGLE_COMPONENT_FUNCTION_PARAM) + simple = 1; + if (!simple) + d_append_char (dpi, '('); + d_print_comp (dpi, options, dc); + if (!simple) + d_append_char (dpi, ')'); +} + +/* Subroutine to handle components. */ + +static void +d_print_comp (struct d_print_info *dpi, int options, + const struct demangle_component *dc) +{ + if (dc == NULL) + { + d_print_error (dpi); + return; + } + if (d_print_saw_error (dpi)) + return; + + switch (dc->type) + { + case DEMANGLE_COMPONENT_NAME: + if ((options & DMGL_JAVA) == 0) + d_append_buffer (dpi, dc->u.s_name.s, dc->u.s_name.len); + else + d_print_java_identifier (dpi, dc->u.s_name.s, dc->u.s_name.len); + return; + + case DEMANGLE_COMPONENT_QUAL_NAME: + case DEMANGLE_COMPONENT_LOCAL_NAME: + d_print_comp (dpi, options, d_left (dc)); + if ((options & DMGL_JAVA) == 0) + d_append_string (dpi, "::"); + else + d_append_char (dpi, '.'); + d_print_comp (dpi, options, d_right (dc)); + return; + + case DEMANGLE_COMPONENT_TYPED_NAME: + { + struct d_print_mod *hold_modifiers; + struct demangle_component *typed_name; + struct d_print_mod adpm[4]; + unsigned int i; + struct d_print_template dpt; + + /* Pass the name down to the type so that it can be printed in + the right place for the type. We also have to pass down + any CV-qualifiers, which apply to the this parameter. */ + hold_modifiers = dpi->modifiers; + dpi->modifiers = 0; + i = 0; + typed_name = d_left (dc); + while (typed_name != NULL) + { + if (i >= sizeof adpm / sizeof adpm[0]) + { + d_print_error (dpi); + return; + } + + adpm[i].next = dpi->modifiers; + dpi->modifiers = &adpm[i]; + adpm[i].mod = typed_name; + adpm[i].printed = 0; + adpm[i].templates = dpi->templates; + ++i; + + if (typed_name->type != DEMANGLE_COMPONENT_RESTRICT_THIS + && typed_name->type != DEMANGLE_COMPONENT_VOLATILE_THIS + && typed_name->type != DEMANGLE_COMPONENT_CONST_THIS) + break; + + typed_name = d_left (typed_name); + } + + if (typed_name == NULL) + { + d_print_error (dpi); + return; + } + + /* If typed_name is a template, then it applies to the + function type as well. */ + if (typed_name->type == DEMANGLE_COMPONENT_TEMPLATE) + { + dpt.next = dpi->templates; + dpi->templates = &dpt; + dpt.template_decl = typed_name; + } + + /* If typed_name is a DEMANGLE_COMPONENT_LOCAL_NAME, then + there may be CV-qualifiers on its right argument which + really apply here; this happens when parsing a class which + is local to a function. */ + if (typed_name->type == DEMANGLE_COMPONENT_LOCAL_NAME) + { + struct demangle_component *local_name; + + local_name = d_right (typed_name); + if (local_name->type == DEMANGLE_COMPONENT_DEFAULT_ARG) + local_name = local_name->u.s_unary_num.sub; + while (local_name->type == DEMANGLE_COMPONENT_RESTRICT_THIS + || local_name->type == DEMANGLE_COMPONENT_VOLATILE_THIS + || local_name->type == DEMANGLE_COMPONENT_CONST_THIS) + { + if (i >= sizeof adpm / sizeof adpm[0]) + { + d_print_error (dpi); + return; + } + + adpm[i] = adpm[i - 1]; + adpm[i].next = &adpm[i - 1]; + dpi->modifiers = &adpm[i]; + + adpm[i - 1].mod = local_name; + adpm[i - 1].printed = 0; + adpm[i - 1].templates = dpi->templates; + ++i; + + local_name = d_left (local_name); + } + } + + d_print_comp (dpi, options, d_right (dc)); + + if (typed_name->type == DEMANGLE_COMPONENT_TEMPLATE) + dpi->templates = dpt.next; + + /* If the modifiers didn't get printed by the type, print them + now. */ + while (i > 0) + { + --i; + if (! adpm[i].printed) + { + d_append_char (dpi, ' '); + d_print_mod (dpi, options, adpm[i].mod); + } + } + + dpi->modifiers = hold_modifiers; + + return; + } + + case DEMANGLE_COMPONENT_TEMPLATE: + { + struct d_print_mod *hold_dpm; + struct demangle_component *dcl; + + /* Don't push modifiers into a template definition. Doing so + could give the wrong definition for a template argument. + Instead, treat the template essentially as a name. */ + + hold_dpm = dpi->modifiers; + dpi->modifiers = NULL; + + dcl = d_left (dc); + + if ((options & DMGL_JAVA) != 0 + && dcl->type == DEMANGLE_COMPONENT_NAME + && dcl->u.s_name.len == 6 + && strncmp (dcl->u.s_name.s, "JArray", 6) == 0) + { + /* Special-case Java arrays, so that JArray appears + instead as TYPE[]. */ + + d_print_comp (dpi, options, d_right (dc)); + d_append_string (dpi, "[]"); + } + else + { + d_print_comp (dpi, options, dcl); + if (d_last_char (dpi) == '<') + d_append_char (dpi, ' '); + d_append_char (dpi, '<'); + d_print_comp (dpi, options, d_right (dc)); + /* Avoid generating two consecutive '>' characters, to avoid + the C++ syntactic ambiguity. */ + if (d_last_char (dpi) == '>') + d_append_char (dpi, ' '); + d_append_char (dpi, '>'); + } + + dpi->modifiers = hold_dpm; + + return; + } + + case DEMANGLE_COMPONENT_TEMPLATE_PARAM: + { + struct d_print_template *hold_dpt; + struct demangle_component *a = d_lookup_template_argument (dpi, dc); + + if (a && a->type == DEMANGLE_COMPONENT_TEMPLATE_ARGLIST) + a = d_index_template_argument (a, dpi->pack_index); + + if (a == NULL) + { + d_print_error (dpi); + return; + } + + /* While processing this parameter, we need to pop the list of + templates. This is because the template parameter may + itself be a reference to a parameter of an outer + template. */ + + hold_dpt = dpi->templates; + dpi->templates = hold_dpt->next; + + d_print_comp (dpi, options, a); + + dpi->templates = hold_dpt; + + return; + } + + case DEMANGLE_COMPONENT_CTOR: + d_print_comp (dpi, options, dc->u.s_ctor.name); + return; + + case DEMANGLE_COMPONENT_DTOR: + d_append_char (dpi, '~'); + d_print_comp (dpi, options, dc->u.s_dtor.name); + return; + + case DEMANGLE_COMPONENT_VTABLE: + d_append_string (dpi, "vtable for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_VTT: + d_append_string (dpi, "VTT for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE: + d_append_string (dpi, "construction vtable for "); + d_print_comp (dpi, options, d_left (dc)); + d_append_string (dpi, "-in-"); + d_print_comp (dpi, options, d_right (dc)); + return; + + case DEMANGLE_COMPONENT_TYPEINFO: + d_append_string (dpi, "typeinfo for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_TYPEINFO_NAME: + d_append_string (dpi, "typeinfo name for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_TYPEINFO_FN: + d_append_string (dpi, "typeinfo fn for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_THUNK: + d_append_string (dpi, "non-virtual thunk to "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_VIRTUAL_THUNK: + d_append_string (dpi, "virtual thunk to "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_COVARIANT_THUNK: + d_append_string (dpi, "covariant return thunk to "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_JAVA_CLASS: + d_append_string (dpi, "java Class for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_GUARD: + d_append_string (dpi, "guard variable for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_REFTEMP: + d_append_string (dpi, "reference temporary for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_HIDDEN_ALIAS: + d_append_string (dpi, "hidden alias for "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_SUB_STD: + d_append_buffer (dpi, dc->u.s_string.string, dc->u.s_string.len); + return; + + case DEMANGLE_COMPONENT_RESTRICT: + case DEMANGLE_COMPONENT_VOLATILE: + case DEMANGLE_COMPONENT_CONST: + { + struct d_print_mod *pdpm; + + /* When printing arrays, it's possible to have cases where the + same CV-qualifier gets pushed on the stack multiple times. + We only need to print it once. */ + + for (pdpm = dpi->modifiers; pdpm != NULL; pdpm = pdpm->next) + { + if (! pdpm->printed) + { + if (pdpm->mod->type != DEMANGLE_COMPONENT_RESTRICT + && pdpm->mod->type != DEMANGLE_COMPONENT_VOLATILE + && pdpm->mod->type != DEMANGLE_COMPONENT_CONST) + break; + if (pdpm->mod->type == dc->type) + { + d_print_comp (dpi, options, d_left (dc)); + return; + } + } + } + } + /* Fall through. */ + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + case DEMANGLE_COMPONENT_POINTER: + case DEMANGLE_COMPONENT_REFERENCE: + case DEMANGLE_COMPONENT_RVALUE_REFERENCE: + case DEMANGLE_COMPONENT_COMPLEX: + case DEMANGLE_COMPONENT_IMAGINARY: + { + /* We keep a list of modifiers on the stack. */ + struct d_print_mod dpm; + + dpm.next = dpi->modifiers; + dpi->modifiers = &dpm; + dpm.mod = dc; + dpm.printed = 0; + dpm.templates = dpi->templates; + + d_print_comp (dpi, options, d_left (dc)); + + /* If the modifier didn't get printed by the type, print it + now. */ + if (! dpm.printed) + d_print_mod (dpi, options, dc); + + dpi->modifiers = dpm.next; + + return; + } + + case DEMANGLE_COMPONENT_BUILTIN_TYPE: + if ((options & DMGL_JAVA) == 0) + d_append_buffer (dpi, dc->u.s_builtin.type->name, + dc->u.s_builtin.type->len); + else + d_append_buffer (dpi, dc->u.s_builtin.type->java_name, + dc->u.s_builtin.type->java_len); + return; + + case DEMANGLE_COMPONENT_VENDOR_TYPE: + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_FUNCTION_TYPE: + { + if ((options & DMGL_RET_POSTFIX) != 0) + d_print_function_type (dpi, + options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP), + dc, dpi->modifiers); + + /* Print return type if present */ + if (d_left (dc) != NULL && (options & DMGL_RET_POSTFIX) != 0) + d_print_comp (dpi, options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP), + d_left (dc)); + else if (d_left (dc) != NULL && (options & DMGL_RET_DROP) == 0) + { + struct d_print_mod dpm; + + /* We must pass this type down as a modifier in order to + print it in the right location. */ + dpm.next = dpi->modifiers; + dpi->modifiers = &dpm; + dpm.mod = dc; + dpm.printed = 0; + dpm.templates = dpi->templates; + + d_print_comp (dpi, options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP), + d_left (dc)); + + dpi->modifiers = dpm.next; + + if (dpm.printed) + return; + + /* In standard prefix notation, there is a space between the + return type and the function signature. */ + if ((options & DMGL_RET_POSTFIX) == 0) + d_append_char (dpi, ' '); + } + + if ((options & DMGL_RET_POSTFIX) == 0) + d_print_function_type (dpi, + options & ~(DMGL_RET_POSTFIX | DMGL_RET_DROP), + dc, dpi->modifiers); + + return; + } + + case DEMANGLE_COMPONENT_ARRAY_TYPE: + { + struct d_print_mod *hold_modifiers; + struct d_print_mod adpm[4]; + unsigned int i; + struct d_print_mod *pdpm; + + /* We must pass this type down as a modifier in order to print + multi-dimensional arrays correctly. If the array itself is + CV-qualified, we act as though the element type were + CV-qualified. We do this by copying the modifiers down + rather than fiddling pointers, so that we don't wind up + with a d_print_mod higher on the stack pointing into our + stack frame after we return. */ + + hold_modifiers = dpi->modifiers; + + adpm[0].next = hold_modifiers; + dpi->modifiers = &adpm[0]; + adpm[0].mod = dc; + adpm[0].printed = 0; + adpm[0].templates = dpi->templates; + + i = 1; + pdpm = hold_modifiers; + while (pdpm != NULL + && (pdpm->mod->type == DEMANGLE_COMPONENT_RESTRICT + || pdpm->mod->type == DEMANGLE_COMPONENT_VOLATILE + || pdpm->mod->type == DEMANGLE_COMPONENT_CONST)) + { + if (! pdpm->printed) + { + if (i >= sizeof adpm / sizeof adpm[0]) + { + d_print_error (dpi); + return; + } + + adpm[i] = *pdpm; + adpm[i].next = dpi->modifiers; + dpi->modifiers = &adpm[i]; + pdpm->printed = 1; + ++i; + } + + pdpm = pdpm->next; + } + + d_print_comp (dpi, options, d_right (dc)); + + dpi->modifiers = hold_modifiers; + + if (adpm[0].printed) + return; + + while (i > 1) + { + --i; + d_print_mod (dpi, options, adpm[i].mod); + } + + d_print_array_type (dpi, options, dc, dpi->modifiers); + + return; + } + + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + case DEMANGLE_COMPONENT_VECTOR_TYPE: + { + struct d_print_mod dpm; + + dpm.next = dpi->modifiers; + dpi->modifiers = &dpm; + dpm.mod = dc; + dpm.printed = 0; + dpm.templates = dpi->templates; + + d_print_comp (dpi, options, d_right (dc)); + + /* If the modifier didn't get printed by the type, print it + now. */ + if (! dpm.printed) + d_print_mod (dpi, options, dc); + + dpi->modifiers = dpm.next; + + return; + } + + case DEMANGLE_COMPONENT_FIXED_TYPE: + if (dc->u.s_fixed.sat) + d_append_string (dpi, "_Sat "); + /* Don't print "int _Accum". */ + if (dc->u.s_fixed.length->u.s_builtin.type + != &cplus_demangle_builtin_types['i'-'a']) + { + d_print_comp (dpi, options, dc->u.s_fixed.length); + d_append_char (dpi, ' '); + } + if (dc->u.s_fixed.accum) + d_append_string (dpi, "_Accum"); + else + d_append_string (dpi, "_Fract"); + return; + + case DEMANGLE_COMPONENT_ARGLIST: + case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST: + if (d_left (dc) != NULL) + d_print_comp (dpi, options, d_left (dc)); + if (d_right (dc) != NULL) + { + size_t len; + unsigned long int flush_count; + /* Make sure ", " isn't flushed by d_append_string, otherwise + dpi->len -= 2 wouldn't work. */ + if (dpi->len >= sizeof (dpi->buf) - 2) + d_print_flush (dpi); + d_append_string (dpi, ", "); + len = dpi->len; + flush_count = dpi->flush_count; + d_print_comp (dpi, options, d_right (dc)); + /* If that didn't print anything (which can happen with empty + template argument packs), remove the comma and space. */ + if (dpi->flush_count == flush_count && dpi->len == len) + dpi->len -= 2; + } + return; + + case DEMANGLE_COMPONENT_OPERATOR: + { + char c; + + d_append_string (dpi, "operator"); + c = dc->u.s_operator.op->name[0]; + if (IS_LOWER (c)) + d_append_char (dpi, ' '); + d_append_buffer (dpi, dc->u.s_operator.op->name, + dc->u.s_operator.op->len); + return; + } + + case DEMANGLE_COMPONENT_EXTENDED_OPERATOR: + d_append_string (dpi, "operator "); + d_print_comp (dpi, options, dc->u.s_extended_operator.name); + return; + + case DEMANGLE_COMPONENT_CAST: + d_append_string (dpi, "operator "); + d_print_cast (dpi, options, dc); + return; + + case DEMANGLE_COMPONENT_UNARY: + if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR + && d_left (dc)->u.s_operator.op->len == 1 + && d_left (dc)->u.s_operator.op->name[0] == '&' + && d_right (dc)->type == DEMANGLE_COMPONENT_TYPED_NAME + && d_left (d_right (dc))->type == DEMANGLE_COMPONENT_QUAL_NAME + && d_right (d_right (dc))->type == DEMANGLE_COMPONENT_FUNCTION_TYPE) + { + /* Address of a function (therefore in an expression context) must + have its argument list suppressed. + + unary operator ... dc + operator & ... d_left (dc) + typed name ... d_right (dc) + qualified name ... d_left (d_right (dc)) + + function type ... d_right (d_right (dc)) + argument list + */ + + d_print_expr_op (dpi, options, d_left (dc)); + d_print_comp (dpi, options, d_left (d_right (dc))); + return; + } + else if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR + && d_left (dc)->u.s_operator.op->len == 1 + && d_left (dc)->u.s_operator.op->name[0] == '&' + && d_right (dc)->type == DEMANGLE_COMPONENT_QUAL_NAME) + { + /* Keep also already processed variant without the argument list. + + unary operator ... dc + operator & ... d_left (dc) + qualified name ... d_right (dc) + */ + + d_print_expr_op (dpi, options, d_left (dc)); + d_print_comp (dpi, options, d_right (dc)); + return; + } + else if (d_left (dc)->type != DEMANGLE_COMPONENT_CAST) + d_print_expr_op (dpi, options, d_left (dc)); + else + { + d_append_char (dpi, '('); + d_print_cast (dpi, options, d_left (dc)); + d_append_char (dpi, ')'); + } + d_print_subexpr (dpi, options, d_right (dc)); + return; + + case DEMANGLE_COMPONENT_BINARY: + if (d_right (dc)->type != DEMANGLE_COMPONENT_BINARY_ARGS) + { + d_print_error (dpi); + return; + } + + /* We wrap an expression which uses the greater-than operator in + an extra layer of parens so that it does not get confused + with the '>' which ends the template parameters. */ + if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR + && d_left (dc)->u.s_operator.op->len == 1 + && d_left (dc)->u.s_operator.op->name[0] == '>') + d_append_char (dpi, '('); + + if (strcmp (d_left (dc)->u.s_operator.op->code, "cl") == 0 + && d_left (d_right (dc))->type == DEMANGLE_COMPONENT_TYPED_NAME) + { + /* Function call used in an expression should not have printed types + of the function arguments. Values of the function arguments still + get printed below. */ + + const struct demangle_component *func = d_left (d_right (dc)); + + if (d_right (func)->type != DEMANGLE_COMPONENT_FUNCTION_TYPE) + d_print_error (dpi); + d_print_subexpr (dpi, options, d_left (func)); + } + else + d_print_subexpr (dpi, options, d_left (d_right (dc))); + if (strcmp (d_left (dc)->u.s_operator.op->code, "ix") == 0) + { + d_append_char (dpi, '['); + d_print_comp (dpi, options, d_right (d_right (dc))); + d_append_char (dpi, ']'); + } + else + { + if (strcmp (d_left (dc)->u.s_operator.op->code, "cl") != 0) + d_print_expr_op (dpi, options, d_left (dc)); + d_print_subexpr (dpi, options, d_right (d_right (dc))); + } + + if (d_left (dc)->type == DEMANGLE_COMPONENT_OPERATOR + && d_left (dc)->u.s_operator.op->len == 1 + && d_left (dc)->u.s_operator.op->name[0] == '>') + d_append_char (dpi, ')'); + + return; + + case DEMANGLE_COMPONENT_BINARY_ARGS: + /* We should only see this as part of DEMANGLE_COMPONENT_BINARY. */ + d_print_error (dpi); + return; + + case DEMANGLE_COMPONENT_TRINARY: + if (d_right (dc)->type != DEMANGLE_COMPONENT_TRINARY_ARG1 + || d_right (d_right (dc))->type != DEMANGLE_COMPONENT_TRINARY_ARG2) + { + d_print_error (dpi); + return; + } + d_print_subexpr (dpi, options, d_left (d_right (dc))); + d_print_expr_op (dpi, options, d_left (dc)); + d_print_subexpr (dpi, options, d_left (d_right (d_right (dc)))); + d_append_string (dpi, " : "); + d_print_subexpr (dpi, options, d_right (d_right (d_right (dc)))); + return; + + case DEMANGLE_COMPONENT_TRINARY_ARG1: + case DEMANGLE_COMPONENT_TRINARY_ARG2: + /* We should only see these are part of DEMANGLE_COMPONENT_TRINARY. */ + d_print_error (dpi); + return; + + case DEMANGLE_COMPONENT_LITERAL: + case DEMANGLE_COMPONENT_LITERAL_NEG: + { + enum d_builtin_type_print tp; + + /* For some builtin types, produce simpler output. */ + tp = D_PRINT_DEFAULT; + if (d_left (dc)->type == DEMANGLE_COMPONENT_BUILTIN_TYPE) + { + tp = d_left (dc)->u.s_builtin.type->print; + switch (tp) + { + case D_PRINT_INT: + case D_PRINT_UNSIGNED: + case D_PRINT_LONG: + case D_PRINT_UNSIGNED_LONG: + case D_PRINT_LONG_LONG: + case D_PRINT_UNSIGNED_LONG_LONG: + if (d_right (dc)->type == DEMANGLE_COMPONENT_NAME) + { + if (dc->type == DEMANGLE_COMPONENT_LITERAL_NEG) + d_append_char (dpi, '-'); + d_print_comp (dpi, options, d_right (dc)); + switch (tp) + { + default: + break; + case D_PRINT_UNSIGNED: + d_append_char (dpi, 'u'); + break; + case D_PRINT_LONG: + d_append_char (dpi, 'l'); + break; + case D_PRINT_UNSIGNED_LONG: + d_append_string (dpi, "ul"); + break; + case D_PRINT_LONG_LONG: + d_append_string (dpi, "ll"); + break; + case D_PRINT_UNSIGNED_LONG_LONG: + d_append_string (dpi, "ull"); + break; + } + return; + } + break; + + case D_PRINT_BOOL: + if (d_right (dc)->type == DEMANGLE_COMPONENT_NAME + && d_right (dc)->u.s_name.len == 1 + && dc->type == DEMANGLE_COMPONENT_LITERAL) + { + switch (d_right (dc)->u.s_name.s[0]) + { + case '0': + d_append_string (dpi, "false"); + return; + case '1': + d_append_string (dpi, "true"); + return; + default: + break; + } + } + break; + + default: + break; + } + } + + d_append_char (dpi, '('); + d_print_comp (dpi, options, d_left (dc)); + d_append_char (dpi, ')'); + if (dc->type == DEMANGLE_COMPONENT_LITERAL_NEG) + d_append_char (dpi, '-'); + if (tp == D_PRINT_FLOAT) + d_append_char (dpi, '['); + d_print_comp (dpi, options, d_right (dc)); + if (tp == D_PRINT_FLOAT) + d_append_char (dpi, ']'); + } + return; + + case DEMANGLE_COMPONENT_NUMBER: + d_append_num (dpi, dc->u.s_number.number); + return; + + case DEMANGLE_COMPONENT_JAVA_RESOURCE: + d_append_string (dpi, "java resource "); + d_print_comp (dpi, options, d_left (dc)); + return; + + case DEMANGLE_COMPONENT_COMPOUND_NAME: + d_print_comp (dpi, options, d_left (dc)); + d_print_comp (dpi, options, d_right (dc)); + return; + + case DEMANGLE_COMPONENT_CHARACTER: + d_append_char (dpi, dc->u.s_character.character); + return; + + case DEMANGLE_COMPONENT_DECLTYPE: + d_append_string (dpi, "decltype ("); + d_print_comp (dpi, options, d_left (dc)); + d_append_char (dpi, ')'); + return; + + case DEMANGLE_COMPONENT_PACK_EXPANSION: + { + int len; + int i; + struct demangle_component *a = d_find_pack (dpi, d_left (dc)); + if (a == NULL) + { + /* d_find_pack won't find anything if the only packs involved + in this expansion are function parameter packs; in that + case, just print the pattern and "...". */ + d_print_subexpr (dpi, options, d_left (dc)); + d_append_string (dpi, "..."); + return; + } + + len = d_pack_length (a); + dc = d_left (dc); + for (i = 0; i < len; ++i) + { + dpi->pack_index = i; + d_print_comp (dpi, options, dc); + if (i < len-1) + d_append_string (dpi, ", "); + } + } + return; + + case DEMANGLE_COMPONENT_FUNCTION_PARAM: + d_append_string (dpi, "{parm#"); + d_append_num (dpi, dc->u.s_number.number + 1); + d_append_char (dpi, '}'); + return; + + case DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS: + d_append_string (dpi, "global constructors keyed to "); + d_print_comp (dpi, options, dc->u.s_binary.left); + return; + + case DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS: + d_append_string (dpi, "global destructors keyed to "); + d_print_comp (dpi, options, dc->u.s_binary.left); + return; + + case DEMANGLE_COMPONENT_LAMBDA: + d_append_string (dpi, "{lambda("); + d_print_comp (dpi, options, dc->u.s_unary_num.sub); + d_append_string (dpi, ")#"); + d_append_num (dpi, dc->u.s_unary_num.num + 1); + d_append_char (dpi, '}'); + return; + + case DEMANGLE_COMPONENT_UNNAMED_TYPE: + d_append_string (dpi, "{unnamed type#"); + d_append_num (dpi, dc->u.s_number.number + 1); + d_append_char (dpi, '}'); + return; + + default: + d_print_error (dpi); + return; + } +} + +/* Print a Java dentifier. For Java we try to handle encoded extended + Unicode characters. The C++ ABI doesn't mention Unicode encoding, + so we don't it for C++. Characters are encoded as + __U+_. */ + +static void +d_print_java_identifier (struct d_print_info *dpi, const char *name, int len) +{ + const char *p; + const char *end; + + end = name + len; + for (p = name; p < end; ++p) + { + if (end - p > 3 + && p[0] == '_' + && p[1] == '_' + && p[2] == 'U') + { + unsigned long c; + const char *q; + + c = 0; + for (q = p + 3; q < end; ++q) + { + int dig; + + if (IS_DIGIT (*q)) + dig = *q - '0'; + else if (*q >= 'A' && *q <= 'F') + dig = *q - 'A' + 10; + else if (*q >= 'a' && *q <= 'f') + dig = *q - 'a' + 10; + else + break; + + c = c * 16 + dig; + } + /* If the Unicode character is larger than 256, we don't try + to deal with it here. FIXME. */ + if (q < end && *q == '_' && c < 256) + { + d_append_char (dpi, c); + p = q; + continue; + } + } + + d_append_char (dpi, *p); + } +} + +/* Print a list of modifiers. SUFFIX is 1 if we are printing + qualifiers on this after printing a function. */ + +static void +d_print_mod_list (struct d_print_info *dpi, int options, + struct d_print_mod *mods, int suffix) +{ + struct d_print_template *hold_dpt; + + if (mods == NULL || d_print_saw_error (dpi)) + return; + + if (mods->printed + || (! suffix + && (mods->mod->type == DEMANGLE_COMPONENT_RESTRICT_THIS + || mods->mod->type == DEMANGLE_COMPONENT_VOLATILE_THIS + || mods->mod->type == DEMANGLE_COMPONENT_CONST_THIS))) + { + d_print_mod_list (dpi, options, mods->next, suffix); + return; + } + + mods->printed = 1; + + hold_dpt = dpi->templates; + dpi->templates = mods->templates; + + if (mods->mod->type == DEMANGLE_COMPONENT_FUNCTION_TYPE) + { + d_print_function_type (dpi, options, mods->mod, mods->next); + dpi->templates = hold_dpt; + return; + } + else if (mods->mod->type == DEMANGLE_COMPONENT_ARRAY_TYPE) + { + d_print_array_type (dpi, options, mods->mod, mods->next); + dpi->templates = hold_dpt; + return; + } + else if (mods->mod->type == DEMANGLE_COMPONENT_LOCAL_NAME) + { + struct d_print_mod *hold_modifiers; + struct demangle_component *dc; + + /* When this is on the modifier stack, we have pulled any + qualifiers off the right argument already. Otherwise, we + print it as usual, but don't let the left argument see any + modifiers. */ + + hold_modifiers = dpi->modifiers; + dpi->modifiers = NULL; + d_print_comp (dpi, options, d_left (mods->mod)); + dpi->modifiers = hold_modifiers; + + if ((options & DMGL_JAVA) == 0) + d_append_string (dpi, "::"); + else + d_append_char (dpi, '.'); + + dc = d_right (mods->mod); + + if (dc->type == DEMANGLE_COMPONENT_DEFAULT_ARG) + { + d_append_string (dpi, "{default arg#"); + d_append_num (dpi, dc->u.s_unary_num.num + 1); + d_append_string (dpi, "}::"); + dc = dc->u.s_unary_num.sub; + } + + while (dc->type == DEMANGLE_COMPONENT_RESTRICT_THIS + || dc->type == DEMANGLE_COMPONENT_VOLATILE_THIS + || dc->type == DEMANGLE_COMPONENT_CONST_THIS) + dc = d_left (dc); + + d_print_comp (dpi, options, dc); + + dpi->templates = hold_dpt; + return; + } + + d_print_mod (dpi, options, mods->mod); + + dpi->templates = hold_dpt; + + d_print_mod_list (dpi, options, mods->next, suffix); +} + +/* Print a modifier. */ + +static void +d_print_mod (struct d_print_info *dpi, int options, + const struct demangle_component *mod) +{ + switch (mod->type) + { + case DEMANGLE_COMPONENT_RESTRICT: + case DEMANGLE_COMPONENT_RESTRICT_THIS: + d_append_string (dpi, " restrict"); + return; + case DEMANGLE_COMPONENT_VOLATILE: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + d_append_string (dpi, " volatile"); + return; + case DEMANGLE_COMPONENT_CONST: + case DEMANGLE_COMPONENT_CONST_THIS: + d_append_string (dpi, " const"); + return; + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + d_append_char (dpi, ' '); + d_print_comp (dpi, options, d_right (mod)); + return; + case DEMANGLE_COMPONENT_POINTER: + /* There is no pointer symbol in Java. */ + if ((options & DMGL_JAVA) == 0) + d_append_char (dpi, '*'); + return; + case DEMANGLE_COMPONENT_REFERENCE: + d_append_char (dpi, '&'); + return; + case DEMANGLE_COMPONENT_RVALUE_REFERENCE: + d_append_string (dpi, "&&"); + return; + case DEMANGLE_COMPONENT_COMPLEX: + d_append_string (dpi, "complex "); + return; + case DEMANGLE_COMPONENT_IMAGINARY: + d_append_string (dpi, "imaginary "); + return; + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + if (d_last_char (dpi) != '(') + d_append_char (dpi, ' '); + d_print_comp (dpi, options, d_left (mod)); + d_append_string (dpi, "::*"); + return; + case DEMANGLE_COMPONENT_TYPED_NAME: + d_print_comp (dpi, options, d_left (mod)); + return; + case DEMANGLE_COMPONENT_VECTOR_TYPE: + d_append_string (dpi, " __vector("); + d_print_comp (dpi, options, d_left (mod)); + d_append_char (dpi, ')'); + return; + + default: + /* Otherwise, we have something that won't go back on the + modifier stack, so we can just print it. */ + d_print_comp (dpi, options, mod); + return; + } +} + +/* Print a function type, except for the return type. */ + +static void +d_print_function_type (struct d_print_info *dpi, int options, + const struct demangle_component *dc, + struct d_print_mod *mods) +{ + int need_paren; + int need_space; + struct d_print_mod *p; + struct d_print_mod *hold_modifiers; + + need_paren = 0; + need_space = 0; + for (p = mods; p != NULL; p = p->next) + { + if (p->printed) + break; + + switch (p->mod->type) + { + case DEMANGLE_COMPONENT_POINTER: + case DEMANGLE_COMPONENT_REFERENCE: + case DEMANGLE_COMPONENT_RVALUE_REFERENCE: + need_paren = 1; + break; + case DEMANGLE_COMPONENT_RESTRICT: + case DEMANGLE_COMPONENT_VOLATILE: + case DEMANGLE_COMPONENT_CONST: + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + case DEMANGLE_COMPONENT_COMPLEX: + case DEMANGLE_COMPONENT_IMAGINARY: + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + need_space = 1; + need_paren = 1; + break; + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + break; + default: + break; + } + if (need_paren) + break; + } + + if (need_paren) + { + if (! need_space) + { + if (d_last_char (dpi) != '(' + && d_last_char (dpi) != '*') + need_space = 1; + } + if (need_space && d_last_char (dpi) != ' ') + d_append_char (dpi, ' '); + d_append_char (dpi, '('); + } + + hold_modifiers = dpi->modifiers; + dpi->modifiers = NULL; + + d_print_mod_list (dpi, options, mods, 0); + + if (need_paren) + d_append_char (dpi, ')'); + + d_append_char (dpi, '('); + + if (d_right (dc) != NULL) + d_print_comp (dpi, options, d_right (dc)); + + d_append_char (dpi, ')'); + + d_print_mod_list (dpi, options, mods, 1); + + dpi->modifiers = hold_modifiers; +} + +/* Print an array type, except for the element type. */ + +static void +d_print_array_type (struct d_print_info *dpi, int options, + const struct demangle_component *dc, + struct d_print_mod *mods) +{ + int need_space; + + need_space = 1; + if (mods != NULL) + { + int need_paren; + struct d_print_mod *p; + + need_paren = 0; + for (p = mods; p != NULL; p = p->next) + { + if (! p->printed) + { + if (p->mod->type == DEMANGLE_COMPONENT_ARRAY_TYPE) + { + need_space = 0; + break; + } + else + { + need_paren = 1; + need_space = 1; + break; + } + } + } + + if (need_paren) + d_append_string (dpi, " ("); + + d_print_mod_list (dpi, options, mods, 0); + + if (need_paren) + d_append_char (dpi, ')'); + } + + if (need_space) + d_append_char (dpi, ' '); + + d_append_char (dpi, '['); + + if (d_left (dc) != NULL) + d_print_comp (dpi, options, d_left (dc)); + + d_append_char (dpi, ']'); +} + +/* Print an operator in an expression. */ + +static void +d_print_expr_op (struct d_print_info *dpi, int options, + const struct demangle_component *dc) +{ + if (dc->type == DEMANGLE_COMPONENT_OPERATOR) + d_append_buffer (dpi, dc->u.s_operator.op->name, + dc->u.s_operator.op->len); + else + d_print_comp (dpi, options, dc); +} + +/* Print a cast. */ + +static void +d_print_cast (struct d_print_info *dpi, int options, + const struct demangle_component *dc) +{ + if (d_left (dc)->type != DEMANGLE_COMPONENT_TEMPLATE) + d_print_comp (dpi, options, d_left (dc)); + else + { + struct d_print_mod *hold_dpm; + struct d_print_template dpt; + + /* It appears that for a templated cast operator, we need to put + the template parameters in scope for the operator name, but + not for the parameters. The effect is that we need to handle + the template printing here. */ + + hold_dpm = dpi->modifiers; + dpi->modifiers = NULL; + + dpt.next = dpi->templates; + dpi->templates = &dpt; + dpt.template_decl = d_left (dc); + + d_print_comp (dpi, options, d_left (d_left (dc))); + + dpi->templates = dpt.next; + + if (d_last_char (dpi) == '<') + d_append_char (dpi, ' '); + d_append_char (dpi, '<'); + d_print_comp (dpi, options, d_right (d_left (dc))); + /* Avoid generating two consecutive '>' characters, to avoid + the C++ syntactic ambiguity. */ + if (d_last_char (dpi) == '>') + d_append_char (dpi, ' '); + d_append_char (dpi, '>'); + + dpi->modifiers = hold_dpm; + } +} + +/* Initialize the information structure we use to pass around + information. */ + +CP_STATIC_IF_GLIBCPP_V3 +void +cplus_demangle_init_info (const char *mangled, int options, size_t len, + struct d_info *di) +{ + di->s = mangled; + di->send = mangled + len; + di->options = options; + + di->n = mangled; + + /* We can not need more components than twice the number of chars in + the mangled string. Most components correspond directly to + chars, but the ARGLIST types are exceptions. */ + di->num_comps = 2 * len; + di->next_comp = 0; + + /* Similarly, we can not need more substitutions than there are + chars in the mangled string. */ + di->num_subs = len; + di->next_sub = 0; + di->did_subs = 0; + + di->last_name = NULL; + + di->expansion = 0; +} + +/* Internal implementation for the demangler. If MANGLED is a g++ v3 ABI + mangled name, return strings in repeated callback giving the demangled + name. OPTIONS is the usual libiberty demangler options. On success, + this returns 1. On failure, returns 0. */ + +static int +d_demangle_callback (const char *mangled, int options, + demangle_callbackref callback, void *opaque) +{ + enum + { + DCT_TYPE, + DCT_MANGLED, + DCT_GLOBAL_CTORS, + DCT_GLOBAL_DTORS + } + type; + struct d_info di; + struct demangle_component *dc; + int status; + + if (mangled[0] == '_' && mangled[1] == 'Z') + type = DCT_MANGLED; + else if (strncmp (mangled, "_GLOBAL_", 8) == 0 + && (mangled[8] == '.' || mangled[8] == '_' || mangled[8] == '$') + && (mangled[9] == 'D' || mangled[9] == 'I') + && mangled[10] == '_') + type = mangled[9] == 'I' ? DCT_GLOBAL_CTORS : DCT_GLOBAL_DTORS; + else + { + if ((options & DMGL_TYPES) == 0) + return 0; + type = DCT_TYPE; + } + + cplus_demangle_init_info (mangled, options, strlen (mangled), &di); + + { +#ifdef CP_DYNAMIC_ARRAYS + __extension__ struct demangle_component comps[di.num_comps]; + __extension__ struct demangle_component *subs[di.num_subs]; + + di.comps = comps; + di.subs = subs; +#else + di.comps = alloca (di.num_comps * sizeof (*di.comps)); + di.subs = alloca (di.num_subs * sizeof (*di.subs)); +#endif + + switch (type) + { + case DCT_TYPE: + dc = cplus_demangle_type (&di); + break; + case DCT_MANGLED: + dc = cplus_demangle_mangled_name (&di, 1); + break; + case DCT_GLOBAL_CTORS: + case DCT_GLOBAL_DTORS: + d_advance (&di, 11); + dc = d_make_comp (&di, + (type == DCT_GLOBAL_CTORS + ? DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS + : DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS), + d_make_demangle_mangled_name (&di, d_str (&di)), + NULL); + d_advance (&di, strlen (d_str (&di))); + break; + } + + /* If DMGL_PARAMS is set, then if we didn't consume the entire + mangled string, then we didn't successfully demangle it. If + DMGL_PARAMS is not set, we didn't look at the trailing + parameters. */ + if (((options & DMGL_PARAMS) != 0) && d_peek_char (&di) != '\0') + dc = NULL; + +#ifdef CP_DEMANGLE_DEBUG + d_dump (dc, 0); +#endif + + status = (dc != NULL) + ? cplus_demangle_print_callback (options, dc, callback, opaque) + : 0; + } + + return status; +} + +/* Entry point for the demangler. If MANGLED is a g++ v3 ABI mangled + name, return a buffer allocated with malloc holding the demangled + name. OPTIONS is the usual libiberty demangler options. On + success, this sets *PALC to the allocated size of the returned + buffer. On failure, this sets *PALC to 0 for a bad name, or 1 for + a memory allocation failure, and returns NULL. */ + +static char * +d_demangle (const char *mangled, int options, size_t *palc) +{ + struct d_growable_string dgs; + int status; + + d_growable_string_init (&dgs, 0); + + status = d_demangle_callback (mangled, options, + d_growable_string_callback_adapter, &dgs); + if (status == 0) + { + free (dgs.buf); + *palc = 0; + return NULL; + } + + *palc = dgs.allocation_failure ? 1 : dgs.alc; + return dgs.buf; +} + +#if defined(IN_LIBGCC2) || defined(IN_GLIBCPP_V3) + +extern char *__cxa_demangle (const char *, char *, size_t *, int *); + +/* ia64 ABI-mandated entry point in the C++ runtime library for + performing demangling. MANGLED_NAME is a NUL-terminated character + string containing the name to be demangled. + + OUTPUT_BUFFER is a region of memory, allocated with malloc, of + *LENGTH bytes, into which the demangled name is stored. If + OUTPUT_BUFFER is not long enough, it is expanded using realloc. + OUTPUT_BUFFER may instead be NULL; in that case, the demangled name + is placed in a region of memory allocated with malloc. + + If LENGTH is non-NULL, the length of the buffer containing the + demangled name, is placed in *LENGTH. + + The return value is a pointer to the start of the NUL-terminated + demangled name, or NULL if the demangling fails. The caller is + responsible for deallocating this memory using free. + + *STATUS is set to one of the following values: + 0: The demangling operation succeeded. + -1: A memory allocation failure occurred. + -2: MANGLED_NAME is not a valid name under the C++ ABI mangling rules. + -3: One of the arguments is invalid. + + The demangling is performed using the C++ ABI mangling rules, with + GNU extensions. */ + +char * +__cxa_demangle (const char *mangled_name, char *output_buffer, + size_t *length, int *status) +{ + char *demangled; + size_t alc; + + if (mangled_name == NULL) + { + if (status != NULL) + *status = -3; + return NULL; + } + + if (output_buffer != NULL && length == NULL) + { + if (status != NULL) + *status = -3; + return NULL; + } + + demangled = d_demangle (mangled_name, DMGL_PARAMS | DMGL_TYPES, &alc); + + if (demangled == NULL) + { + if (status != NULL) + { + if (alc == 1) + *status = -1; + else + *status = -2; + } + return NULL; + } + + if (output_buffer == NULL) + { + if (length != NULL) + *length = alc; + } + else + { + if (strlen (demangled) < *length) + { + strcpy (output_buffer, demangled); + free (demangled); + demangled = output_buffer; + } + else + { + free (output_buffer); + *length = alc; + } + } + + if (status != NULL) + *status = 0; + + return demangled; +} + +extern int __gcclibcxx_demangle_callback (const char *, + void (*) + (const char *, size_t, void *), + void *); + +/* Alternative, allocationless entry point in the C++ runtime library + for performing demangling. MANGLED_NAME is a NUL-terminated character + string containing the name to be demangled. + + CALLBACK is a callback function, called with demangled string + segments as demangling progresses; it is called at least once, + but may be called more than once. OPAQUE is a generalized pointer + used as a callback argument. + + The return code is one of the following values, equivalent to + the STATUS values of __cxa_demangle() (excluding -1, since this + function performs no memory allocations): + 0: The demangling operation succeeded. + -2: MANGLED_NAME is not a valid name under the C++ ABI mangling rules. + -3: One of the arguments is invalid. + + The demangling is performed using the C++ ABI mangling rules, with + GNU extensions. */ + +int +__gcclibcxx_demangle_callback (const char *mangled_name, + void (*callback) (const char *, size_t, void *), + void *opaque) +{ + int status; + + if (mangled_name == NULL || callback == NULL) + return -3; + + status = d_demangle_callback (mangled_name, DMGL_PARAMS | DMGL_TYPES, + callback, opaque); + if (status == 0) + return -2; + + return 0; +} + +#else /* ! (IN_LIBGCC2 || IN_GLIBCPP_V3) */ + +/* Entry point for libiberty demangler. If MANGLED is a g++ v3 ABI + mangled name, return a buffer allocated with malloc holding the + demangled name. Otherwise, return NULL. */ + +char * +cplus_demangle_v3 (const char *mangled, int options) +{ + size_t alc; + + return d_demangle (mangled, options, &alc); +} + +int +cplus_demangle_v3_callback (const char *mangled, int options, + demangle_callbackref callback, void *opaque) +{ + return d_demangle_callback (mangled, options, callback, opaque); +} + +/* Demangle a Java symbol. Java uses a subset of the V3 ABI C++ mangling + conventions, but the output formatting is a little different. + This instructs the C++ demangler not to emit pointer characters ("*"), to + use Java's namespace separator symbol ("." instead of "::"), and to output + JArray as TYPE[]. */ + +char * +java_demangle_v3 (const char *mangled) +{ + size_t alc; + + return d_demangle (mangled, DMGL_JAVA | DMGL_PARAMS | DMGL_RET_POSTFIX, &alc); +} + +int +java_demangle_v3_callback (const char *mangled, + demangle_callbackref callback, void *opaque) +{ + return d_demangle_callback (mangled, + DMGL_JAVA | DMGL_PARAMS | DMGL_RET_POSTFIX, + callback, opaque); +} + +#endif /* IN_LIBGCC2 || IN_GLIBCPP_V3 */ + +#ifndef IN_GLIBCPP_V3 + +/* Demangle a string in order to find out whether it is a constructor + or destructor. Return non-zero on success. Set *CTOR_KIND and + *DTOR_KIND appropriately. */ + +static int +is_ctor_or_dtor (const char *mangled, + enum gnu_v3_ctor_kinds *ctor_kind, + enum gnu_v3_dtor_kinds *dtor_kind) +{ + struct d_info di; + struct demangle_component *dc; + int ret; + + *ctor_kind = (enum gnu_v3_ctor_kinds) 0; + *dtor_kind = (enum gnu_v3_dtor_kinds) 0; + + cplus_demangle_init_info (mangled, DMGL_GNU_V3, strlen (mangled), &di); + + { +#ifdef CP_DYNAMIC_ARRAYS + __extension__ struct demangle_component comps[di.num_comps]; + __extension__ struct demangle_component *subs[di.num_subs]; + + di.comps = comps; + di.subs = subs; +#else + di.comps = alloca (di.num_comps * sizeof (*di.comps)); + di.subs = alloca (di.num_subs * sizeof (*di.subs)); +#endif + + dc = cplus_demangle_mangled_name (&di, 1); + + /* Note that because we did not pass DMGL_PARAMS, we don't expect + to demangle the entire string. */ + + ret = 0; + while (dc != NULL) + { + switch (dc->type) + { + default: + dc = NULL; + break; + case DEMANGLE_COMPONENT_TYPED_NAME: + case DEMANGLE_COMPONENT_TEMPLATE: + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + dc = d_left (dc); + break; + case DEMANGLE_COMPONENT_QUAL_NAME: + case DEMANGLE_COMPONENT_LOCAL_NAME: + dc = d_right (dc); + break; + case DEMANGLE_COMPONENT_CTOR: + *ctor_kind = dc->u.s_ctor.kind; + ret = 1; + dc = NULL; + break; + case DEMANGLE_COMPONENT_DTOR: + *dtor_kind = dc->u.s_dtor.kind; + ret = 1; + dc = NULL; + break; + } + } + } + + return ret; +} + +/* Return whether NAME is the mangled form of a g++ V3 ABI constructor + name. A non-zero return indicates the type of constructor. */ + +enum gnu_v3_ctor_kinds +is_gnu_v3_mangled_ctor (const char *name) +{ + enum gnu_v3_ctor_kinds ctor_kind; + enum gnu_v3_dtor_kinds dtor_kind; + + if (! is_ctor_or_dtor (name, &ctor_kind, &dtor_kind)) + return (enum gnu_v3_ctor_kinds) 0; + return ctor_kind; +} + + +/* Return whether NAME is the mangled form of a g++ V3 ABI destructor + name. A non-zero return indicates the type of destructor. */ + +enum gnu_v3_dtor_kinds +is_gnu_v3_mangled_dtor (const char *name) +{ + enum gnu_v3_ctor_kinds ctor_kind; + enum gnu_v3_dtor_kinds dtor_kind; + + if (! is_ctor_or_dtor (name, &ctor_kind, &dtor_kind)) + return (enum gnu_v3_dtor_kinds) 0; + return dtor_kind; +} + +#endif /* IN_GLIBCPP_V3 */ + +#ifdef STANDALONE_DEMANGLER + +#include "getopt.h" +#include "dyn-string.h" + +static void print_usage (FILE* fp, int exit_value); + +#define IS_ALPHA(CHAR) \ + (((CHAR) >= 'a' && (CHAR) <= 'z') \ + || ((CHAR) >= 'A' && (CHAR) <= 'Z')) + +/* Non-zero if CHAR is a character than can occur in a mangled name. */ +#define is_mangled_char(CHAR) \ + (IS_ALPHA (CHAR) || IS_DIGIT (CHAR) \ + || (CHAR) == '_' || (CHAR) == '.' || (CHAR) == '$') + +/* The name of this program, as invoked. */ +const char* program_name; + +/* Prints usage summary to FP and then exits with EXIT_VALUE. */ + +static void +print_usage (FILE* fp, int exit_value) +{ + fprintf (fp, "Usage: %s [options] [names ...]\n", program_name); + fprintf (fp, "Options:\n"); + fprintf (fp, " -h,--help Display this message.\n"); + fprintf (fp, " -p,--no-params Don't display function parameters\n"); + fprintf (fp, " -v,--verbose Produce verbose demanglings.\n"); + fprintf (fp, "If names are provided, they are demangled. Otherwise filters standard input.\n"); + + exit (exit_value); +} + +/* Option specification for getopt_long. */ +static const struct option long_options[] = +{ + { "help", no_argument, NULL, 'h' }, + { "no-params", no_argument, NULL, 'p' }, + { "verbose", no_argument, NULL, 'v' }, + { NULL, no_argument, NULL, 0 }, +}; + +/* Main entry for a demangling filter executable. It will demangle + its command line arguments, if any. If none are provided, it will + filter stdin to stdout, replacing any recognized mangled C++ names + with their demangled equivalents. */ + +int +main (int argc, char *argv[]) +{ + int i; + int opt_char; + int options = DMGL_PARAMS | DMGL_ANSI | DMGL_TYPES; + + /* Use the program name of this program, as invoked. */ + program_name = argv[0]; + + /* Parse options. */ + do + { + opt_char = getopt_long (argc, argv, "hpv", long_options, NULL); + switch (opt_char) + { + case '?': /* Unrecognized option. */ + print_usage (stderr, 1); + break; + + case 'h': + print_usage (stdout, 0); + break; + + case 'p': + options &= ~ DMGL_PARAMS; + break; + + case 'v': + options |= DMGL_VERBOSE; + break; + } + } + while (opt_char != -1); + + if (optind == argc) + /* No command line arguments were provided. Filter stdin. */ + { + dyn_string_t mangled = dyn_string_new (3); + char *s; + + /* Read all of input. */ + while (!feof (stdin)) + { + char c; + + /* Pile characters into mangled until we hit one that can't + occur in a mangled name. */ + c = getchar (); + while (!feof (stdin) && is_mangled_char (c)) + { + dyn_string_append_char (mangled, c); + if (feof (stdin)) + break; + c = getchar (); + } + + if (dyn_string_length (mangled) > 0) + { +#ifdef IN_GLIBCPP_V3 + s = __cxa_demangle (dyn_string_buf (mangled), NULL, NULL, NULL); +#else + s = cplus_demangle_v3 (dyn_string_buf (mangled), options); +#endif + + if (s != NULL) + { + fputs (s, stdout); + free (s); + } + else + { + /* It might not have been a mangled name. Print the + original text. */ + fputs (dyn_string_buf (mangled), stdout); + } + + dyn_string_clear (mangled); + } + + /* If we haven't hit EOF yet, we've read one character that + can't occur in a mangled name, so print it out. */ + if (!feof (stdin)) + putchar (c); + } + + dyn_string_delete (mangled); + } + else + /* Demangle command line arguments. */ + { + /* Loop over command line arguments. */ + for (i = optind; i < argc; ++i) + { + char *s; +#ifdef IN_GLIBCPP_V3 + int status; +#endif + + /* Attempt to demangle. */ +#ifdef IN_GLIBCPP_V3 + s = __cxa_demangle (argv[i], NULL, NULL, &status); +#else + s = cplus_demangle_v3 (argv[i], options); +#endif + + /* If it worked, print the demangled name. */ + if (s != NULL) + { + printf ("%s\n", s); + free (s); + } + else + { +#ifdef IN_GLIBCPP_V3 + fprintf (stderr, "Failed: %s (status %d)\n", argv[i], status); +#else + fprintf (stderr, "Failed: %s\n", argv[i]); +#endif + } + } + } + + return 0; +} + +#endif /* STANDALONE_DEMANGLER */ diff --git a/external/gpl3/gdb/dist/libiberty/cp-demangle.h b/external/gpl3/gdb/dist/libiberty/cp-demangle.h new file mode 100644 index 000000000000..ae635beb4cc7 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/cp-demangle.h @@ -0,0 +1,169 @@ +/* Internal demangler interface for g++ V3 ABI. + Copyright (C) 2003, 2004, 2005, 2006, 2007, 2010 + Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of the libiberty library, which is part of GCC. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combined + executable.) + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +/* This file provides some definitions shared by cp-demangle.c and + cp-demint.c. It should not be included by any other files. */ + +/* Information we keep for operators. */ + +struct demangle_operator_info +{ + /* Mangled name. */ + const char *code; + /* Real name. */ + const char *name; + /* Length of real name. */ + int len; + /* Number of arguments. */ + int args; +}; + +/* How to print the value of a builtin type. */ + +enum d_builtin_type_print +{ + /* Print as (type)val. */ + D_PRINT_DEFAULT, + /* Print as integer. */ + D_PRINT_INT, + /* Print as unsigned integer, with trailing "u". */ + D_PRINT_UNSIGNED, + /* Print as long, with trailing "l". */ + D_PRINT_LONG, + /* Print as unsigned long, with trailing "ul". */ + D_PRINT_UNSIGNED_LONG, + /* Print as long long, with trailing "ll". */ + D_PRINT_LONG_LONG, + /* Print as unsigned long long, with trailing "ull". */ + D_PRINT_UNSIGNED_LONG_LONG, + /* Print as bool. */ + D_PRINT_BOOL, + /* Print as float--put value in square brackets. */ + D_PRINT_FLOAT, + /* Print in usual way, but here to detect void. */ + D_PRINT_VOID +}; + +/* Information we keep for a builtin type. */ + +struct demangle_builtin_type_info +{ + /* Type name. */ + const char *name; + /* Length of type name. */ + int len; + /* Type name when using Java. */ + const char *java_name; + /* Length of java name. */ + int java_len; + /* How to print a value of this type. */ + enum d_builtin_type_print print; +}; + +/* The information structure we pass around. */ + +struct d_info +{ + /* The string we are demangling. */ + const char *s; + /* The end of the string we are demangling. */ + const char *send; + /* The options passed to the demangler. */ + int options; + /* The next character in the string to consider. */ + const char *n; + /* The array of components. */ + struct demangle_component *comps; + /* The index of the next available component. */ + int next_comp; + /* The number of available component structures. */ + int num_comps; + /* The array of substitutions. */ + struct demangle_component **subs; + /* The index of the next substitution. */ + int next_sub; + /* The number of available entries in the subs array. */ + int num_subs; + /* The number of substitutions which we actually made from the subs + array, plus the number of template parameter references we + saw. */ + int did_subs; + /* The last name we saw, for constructors and destructors. */ + struct demangle_component *last_name; + /* A running total of the length of large expansions from the + mangled name to the demangled name, such as standard + substitutions and builtin types. */ + int expansion; +}; + +/* To avoid running past the ending '\0', don't: + - call d_peek_next_char if d_peek_char returned '\0' + - call d_advance with an 'i' that is too large + - call d_check_char(di, '\0') + Everything else is safe. */ +#define d_peek_char(di) (*((di)->n)) +#define d_peek_next_char(di) ((di)->n[1]) +#define d_advance(di, i) ((di)->n += (i)) +#define d_check_char(di, c) (d_peek_char(di) == c ? ((di)->n++, 1) : 0) +#define d_next_char(di) (d_peek_char(di) == '\0' ? '\0' : *((di)->n++)) +#define d_str(di) ((di)->n) + +/* Functions and arrays in cp-demangle.c which are referenced by + functions in cp-demint.c. */ +#ifdef IN_GLIBCPP_V3 +#define CP_STATIC_IF_GLIBCPP_V3 static +#else +#define CP_STATIC_IF_GLIBCPP_V3 extern +#endif + +#ifndef IN_GLIBCPP_V3 +extern const struct demangle_operator_info cplus_demangle_operators[]; +#endif + +#define D_BUILTIN_TYPE_COUNT (33) + +CP_STATIC_IF_GLIBCPP_V3 +const struct demangle_builtin_type_info +cplus_demangle_builtin_types[D_BUILTIN_TYPE_COUNT]; + +CP_STATIC_IF_GLIBCPP_V3 +struct demangle_component * +cplus_demangle_mangled_name (struct d_info *, int); + +CP_STATIC_IF_GLIBCPP_V3 +struct demangle_component * +cplus_demangle_type (struct d_info *); + +extern void +cplus_demangle_init_info (const char *, int, size_t, struct d_info *); + +/* cp-demangle.c needs to define this a little differently */ +#undef CP_STATIC_IF_GLIBCPP_V3 diff --git a/external/gpl3/gdb/dist/libiberty/cp-demint.c b/external/gpl3/gdb/dist/libiberty/cp-demint.c new file mode 100644 index 000000000000..2e8f8d2d0579 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/cp-demint.c @@ -0,0 +1,234 @@ +/* Demangler component interface functions. + Copyright (C) 2004 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of the libiberty library, which is part of GCC. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combined + executable.) + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +/* This file implements a few interface functions which are provided + for use with struct demangle_component trees. These functions are + declared in demangle.h. These functions are closely tied to the + demangler code in cp-demangle.c, and other interface functions can + be found in that file. We put these functions in a separate file + because they are not needed by the demangler, and so we avoid + having them pulled in by programs which only need the + demangler. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +#include "ansidecl.h" +#include "libiberty.h" +#include "demangle.h" +#include "cp-demangle.h" + +/* Fill in most component types. */ + +int +cplus_demangle_fill_component (struct demangle_component *p, + enum demangle_component_type type, + struct demangle_component *left, + struct demangle_component *right) +{ + if (p == NULL) + return 0; + switch (type) + { + case DEMANGLE_COMPONENT_QUAL_NAME: + case DEMANGLE_COMPONENT_LOCAL_NAME: + case DEMANGLE_COMPONENT_TYPED_NAME: + case DEMANGLE_COMPONENT_TEMPLATE: + case DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE: + case DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL: + case DEMANGLE_COMPONENT_FUNCTION_TYPE: + case DEMANGLE_COMPONENT_ARRAY_TYPE: + case DEMANGLE_COMPONENT_PTRMEM_TYPE: + case DEMANGLE_COMPONENT_ARGLIST: + case DEMANGLE_COMPONENT_TEMPLATE_ARGLIST: + case DEMANGLE_COMPONENT_UNARY: + case DEMANGLE_COMPONENT_BINARY: + case DEMANGLE_COMPONENT_BINARY_ARGS: + case DEMANGLE_COMPONENT_TRINARY: + case DEMANGLE_COMPONENT_TRINARY_ARG1: + case DEMANGLE_COMPONENT_TRINARY_ARG2: + case DEMANGLE_COMPONENT_LITERAL: + case DEMANGLE_COMPONENT_LITERAL_NEG: + break; + + /* These component types only have one subtree. */ + case DEMANGLE_COMPONENT_VTABLE: + case DEMANGLE_COMPONENT_VTT: + case DEMANGLE_COMPONENT_TYPEINFO: + case DEMANGLE_COMPONENT_TYPEINFO_NAME: + case DEMANGLE_COMPONENT_TYPEINFO_FN: + case DEMANGLE_COMPONENT_THUNK: + case DEMANGLE_COMPONENT_VIRTUAL_THUNK: + case DEMANGLE_COMPONENT_COVARIANT_THUNK: + case DEMANGLE_COMPONENT_JAVA_CLASS: + case DEMANGLE_COMPONENT_GUARD: + case DEMANGLE_COMPONENT_REFTEMP: + case DEMANGLE_COMPONENT_RESTRICT: + case DEMANGLE_COMPONENT_VOLATILE: + case DEMANGLE_COMPONENT_CONST: + case DEMANGLE_COMPONENT_RESTRICT_THIS: + case DEMANGLE_COMPONENT_VOLATILE_THIS: + case DEMANGLE_COMPONENT_CONST_THIS: + case DEMANGLE_COMPONENT_POINTER: + case DEMANGLE_COMPONENT_REFERENCE: + case DEMANGLE_COMPONENT_COMPLEX: + case DEMANGLE_COMPONENT_IMAGINARY: + case DEMANGLE_COMPONENT_VENDOR_TYPE: + case DEMANGLE_COMPONENT_CAST: + if (right != NULL) + return 0; + break; + + default: + /* Other types do not use subtrees. */ + return 0; + } + + p->type = type; + p->u.s_binary.left = left; + p->u.s_binary.right = right; + + return 1; +} + +/* Fill in a DEMANGLE_COMPONENT_BUILTIN_TYPE. */ + +int +cplus_demangle_fill_builtin_type (struct demangle_component *p, + const char *type_name) +{ + int len; + unsigned int i; + + if (p == NULL || type_name == NULL) + return 0; + len = strlen (type_name); + for (i = 0; i < D_BUILTIN_TYPE_COUNT; ++i) + { + if (len == cplus_demangle_builtin_types[i].len + && strcmp (type_name, cplus_demangle_builtin_types[i].name) == 0) + { + p->type = DEMANGLE_COMPONENT_BUILTIN_TYPE; + p->u.s_builtin.type = &cplus_demangle_builtin_types[i]; + return 1; + } + } + return 0; +} + +/* Fill in a DEMANGLE_COMPONENT_OPERATOR. */ + +int +cplus_demangle_fill_operator (struct demangle_component *p, + const char *opname, int args) +{ + int len; + unsigned int i; + + if (p == NULL || opname == NULL) + return 0; + len = strlen (opname); + for (i = 0; cplus_demangle_operators[i].name != NULL; ++i) + { + if (len == cplus_demangle_operators[i].len + && args == cplus_demangle_operators[i].args + && strcmp (opname, cplus_demangle_operators[i].name) == 0) + { + p->type = DEMANGLE_COMPONENT_OPERATOR; + p->u.s_operator.op = &cplus_demangle_operators[i]; + return 1; + } + } + return 0; +} + +/* Translate a mangled name into components. */ + +struct demangle_component * +cplus_demangle_v3_components (const char *mangled, int options, void **mem) +{ + size_t len; + int type; + struct d_info di; + struct demangle_component *dc; + + len = strlen (mangled); + + if (mangled[0] == '_' && mangled[1] == 'Z') + type = 0; + else + { + if ((options & DMGL_TYPES) == 0) + return NULL; + type = 1; + } + + cplus_demangle_init_info (mangled, options, len, &di); + + di.comps = ((struct demangle_component *) + malloc (di.num_comps * sizeof (struct demangle_component))); + di.subs = ((struct demangle_component **) + malloc (di.num_subs * sizeof (struct demangle_component *))); + if (di.comps == NULL || di.subs == NULL) + { + if (di.comps != NULL) + free (di.comps); + if (di.subs != NULL) + free (di.subs); + return NULL; + } + + if (! type) + dc = cplus_demangle_mangled_name (&di, 1); + else + dc = cplus_demangle_type (&di); + + /* If DMGL_PARAMS is set, then if we didn't consume the entire + mangled string, then we didn't successfully demangle it. */ + if ((options & DMGL_PARAMS) != 0 && d_peek_char (&di) != '\0') + dc = NULL; + + free (di.subs); + + if (dc != NULL) + *mem = di.comps; + else + free (di.comps); + + return dc; +} diff --git a/external/gpl3/gdb/dist/libiberty/cplus-dem.c b/external/gpl3/gdb/dist/libiberty/cplus-dem.c new file mode 100644 index 000000000000..84f94b6a8de6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/cplus-dem.c @@ -0,0 +1,4863 @@ +/* Demangler for GNU C++ + Copyright 1989, 1991, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003, 2004, 2010 Free Software Foundation, Inc. + Written by James Clark (jjc@jclark.uucp) + Rewritten by Fred Fish (fnf@cygnus.com) for ARM and Lucid demangling + Modified by Satish Pai (pai@apollo.hp.com) for HP demangling + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +In addition to the permissions in the GNU Library General Public +License, the Free Software Foundation gives you unlimited permission +to link the compiled version of this file into combinations with other +programs, and to distribute those combinations without any restriction +coming from the use of this file. (The Library Public License +restrictions do apply in other respects; for example, they cover +modification of the file, and distribution when not linked into a +combined executable.) + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* This file exports two functions; cplus_mangle_opname and cplus_demangle. + + This file imports xmalloc and xrealloc, which are like malloc and + realloc except that they generate a fatal error if there is no + available memory. */ + +/* This file lives in both GCC and libiberty. When making changes, please + try not to break either. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "safe-ctype.h" + +#include +#include +#include + +#ifdef HAVE_STDLIB_H +#include +#else +void * malloc (); +void * realloc (); +#endif + +#include +#undef CURRENT_DEMANGLING_STYLE +#define CURRENT_DEMANGLING_STYLE work->options + +#include "libiberty.h" + +#define min(X,Y) (((X) < (Y)) ? (X) : (Y)) + +/* A value at least one greater than the maximum number of characters + that will be output when using the `%d' format with `printf'. */ +#define INTBUF_SIZE 32 + +extern void fancy_abort (void) ATTRIBUTE_NORETURN; + +/* In order to allow a single demangler executable to demangle strings + using various common values of CPLUS_MARKER, as well as any specific + one set at compile time, we maintain a string containing all the + commonly used ones, and check to see if the marker we are looking for + is in that string. CPLUS_MARKER is usually '$' on systems where the + assembler can deal with that. Where the assembler can't, it's usually + '.' (but on many systems '.' is used for other things). We put the + current defined CPLUS_MARKER first (which defaults to '$'), followed + by the next most common value, followed by an explicit '$' in case + the value of CPLUS_MARKER is not '$'. + + We could avoid this if we could just get g++ to tell us what the actual + cplus marker character is as part of the debug information, perhaps by + ensuring that it is the character that terminates the gcc_compiled + marker symbol (FIXME). */ + +#if !defined (CPLUS_MARKER) +#define CPLUS_MARKER '$' +#endif + +enum demangling_styles current_demangling_style = auto_demangling; + +static char cplus_markers[] = { CPLUS_MARKER, '.', '$', '\0' }; + +static char char_str[2] = { '\000', '\000' }; + +void +set_cplus_marker_for_demangling (int ch) +{ + cplus_markers[0] = ch; +} + +typedef struct string /* Beware: these aren't required to be */ +{ /* '\0' terminated. */ + char *b; /* pointer to start of string */ + char *p; /* pointer after last character */ + char *e; /* pointer after end of allocated space */ +} string; + +/* Stuff that is shared between sub-routines. + Using a shared structure allows cplus_demangle to be reentrant. */ + +struct work_stuff +{ + int options; + char **typevec; + char **ktypevec; + char **btypevec; + int numk; + int numb; + int ksize; + int bsize; + int ntypes; + int typevec_size; + int constructor; + int destructor; + int static_type; /* A static member function */ + int temp_start; /* index in demangled to start of template args */ + int type_quals; /* The type qualifiers. */ + int dllimported; /* Symbol imported from a PE DLL */ + char **tmpl_argvec; /* Template function arguments. */ + int ntmpl_args; /* The number of template function arguments. */ + int forgetting_types; /* Nonzero if we are not remembering the types + we see. */ + string* previous_argument; /* The last function argument demangled. */ + int nrepeats; /* The number of times to repeat the previous + argument. */ +}; + +#define PRINT_ANSI_QUALIFIERS (work -> options & DMGL_ANSI) +#define PRINT_ARG_TYPES (work -> options & DMGL_PARAMS) + +static const struct optable +{ + const char *const in; + const char *const out; + const int flags; +} optable[] = { + {"nw", " new", DMGL_ANSI}, /* new (1.92, ansi) */ + {"dl", " delete", DMGL_ANSI}, /* new (1.92, ansi) */ + {"new", " new", 0}, /* old (1.91, and 1.x) */ + {"delete", " delete", 0}, /* old (1.91, and 1.x) */ + {"vn", " new []", DMGL_ANSI}, /* GNU, pending ansi */ + {"vd", " delete []", DMGL_ANSI}, /* GNU, pending ansi */ + {"as", "=", DMGL_ANSI}, /* ansi */ + {"ne", "!=", DMGL_ANSI}, /* old, ansi */ + {"eq", "==", DMGL_ANSI}, /* old, ansi */ + {"ge", ">=", DMGL_ANSI}, /* old, ansi */ + {"gt", ">", DMGL_ANSI}, /* old, ansi */ + {"le", "<=", DMGL_ANSI}, /* old, ansi */ + {"lt", "<", DMGL_ANSI}, /* old, ansi */ + {"plus", "+", 0}, /* old */ + {"pl", "+", DMGL_ANSI}, /* ansi */ + {"apl", "+=", DMGL_ANSI}, /* ansi */ + {"minus", "-", 0}, /* old */ + {"mi", "-", DMGL_ANSI}, /* ansi */ + {"ami", "-=", DMGL_ANSI}, /* ansi */ + {"mult", "*", 0}, /* old */ + {"ml", "*", DMGL_ANSI}, /* ansi */ + {"amu", "*=", DMGL_ANSI}, /* ansi (ARM/Lucid) */ + {"aml", "*=", DMGL_ANSI}, /* ansi (GNU/g++) */ + {"convert", "+", 0}, /* old (unary +) */ + {"negate", "-", 0}, /* old (unary -) */ + {"trunc_mod", "%", 0}, /* old */ + {"md", "%", DMGL_ANSI}, /* ansi */ + {"amd", "%=", DMGL_ANSI}, /* ansi */ + {"trunc_div", "/", 0}, /* old */ + {"dv", "/", DMGL_ANSI}, /* ansi */ + {"adv", "/=", DMGL_ANSI}, /* ansi */ + {"truth_andif", "&&", 0}, /* old */ + {"aa", "&&", DMGL_ANSI}, /* ansi */ + {"truth_orif", "||", 0}, /* old */ + {"oo", "||", DMGL_ANSI}, /* ansi */ + {"truth_not", "!", 0}, /* old */ + {"nt", "!", DMGL_ANSI}, /* ansi */ + {"postincrement","++", 0}, /* old */ + {"pp", "++", DMGL_ANSI}, /* ansi */ + {"postdecrement","--", 0}, /* old */ + {"mm", "--", DMGL_ANSI}, /* ansi */ + {"bit_ior", "|", 0}, /* old */ + {"or", "|", DMGL_ANSI}, /* ansi */ + {"aor", "|=", DMGL_ANSI}, /* ansi */ + {"bit_xor", "^", 0}, /* old */ + {"er", "^", DMGL_ANSI}, /* ansi */ + {"aer", "^=", DMGL_ANSI}, /* ansi */ + {"bit_and", "&", 0}, /* old */ + {"ad", "&", DMGL_ANSI}, /* ansi */ + {"aad", "&=", DMGL_ANSI}, /* ansi */ + {"bit_not", "~", 0}, /* old */ + {"co", "~", DMGL_ANSI}, /* ansi */ + {"call", "()", 0}, /* old */ + {"cl", "()", DMGL_ANSI}, /* ansi */ + {"alshift", "<<", 0}, /* old */ + {"ls", "<<", DMGL_ANSI}, /* ansi */ + {"als", "<<=", DMGL_ANSI}, /* ansi */ + {"arshift", ">>", 0}, /* old */ + {"rs", ">>", DMGL_ANSI}, /* ansi */ + {"ars", ">>=", DMGL_ANSI}, /* ansi */ + {"component", "->", 0}, /* old */ + {"pt", "->", DMGL_ANSI}, /* ansi; Lucid C++ form */ + {"rf", "->", DMGL_ANSI}, /* ansi; ARM/GNU form */ + {"indirect", "*", 0}, /* old */ + {"method_call", "->()", 0}, /* old */ + {"addr", "&", 0}, /* old (unary &) */ + {"array", "[]", 0}, /* old */ + {"vc", "[]", DMGL_ANSI}, /* ansi */ + {"compound", ", ", 0}, /* old */ + {"cm", ", ", DMGL_ANSI}, /* ansi */ + {"cond", "?:", 0}, /* old */ + {"cn", "?:", DMGL_ANSI}, /* pseudo-ansi */ + {"max", ">?", 0}, /* old */ + {"mx", ">?", DMGL_ANSI}, /* pseudo-ansi */ + {"min", "*", DMGL_ANSI}, /* ansi */ + {"sz", "sizeof ", DMGL_ANSI} /* pseudo-ansi */ +}; + +/* These values are used to indicate the various type varieties. + They are all non-zero so that they can be used as `success' + values. */ +typedef enum type_kind_t +{ + tk_none, + tk_pointer, + tk_reference, + tk_integral, + tk_bool, + tk_char, + tk_real +} type_kind_t; + +const struct demangler_engine libiberty_demanglers[] = +{ + { + NO_DEMANGLING_STYLE_STRING, + no_demangling, + "Demangling disabled" + } + , + { + AUTO_DEMANGLING_STYLE_STRING, + auto_demangling, + "Automatic selection based on executable" + } + , + { + GNU_DEMANGLING_STYLE_STRING, + gnu_demangling, + "GNU (g++) style demangling" + } + , + { + LUCID_DEMANGLING_STYLE_STRING, + lucid_demangling, + "Lucid (lcc) style demangling" + } + , + { + ARM_DEMANGLING_STYLE_STRING, + arm_demangling, + "ARM style demangling" + } + , + { + HP_DEMANGLING_STYLE_STRING, + hp_demangling, + "HP (aCC) style demangling" + } + , + { + EDG_DEMANGLING_STYLE_STRING, + edg_demangling, + "EDG style demangling" + } + , + { + GNU_V3_DEMANGLING_STYLE_STRING, + gnu_v3_demangling, + "GNU (g++) V3 ABI-style demangling" + } + , + { + JAVA_DEMANGLING_STYLE_STRING, + java_demangling, + "Java style demangling" + } + , + { + GNAT_DEMANGLING_STYLE_STRING, + gnat_demangling, + "GNAT style demangling" + } + , + { + NULL, unknown_demangling, NULL + } +}; + +#define STRING_EMPTY(str) ((str) -> b == (str) -> p) +#define APPEND_BLANK(str) {if (!STRING_EMPTY(str)) \ + string_append(str, " ");} +#define LEN_STRING(str) ( (STRING_EMPTY(str))?0:((str)->p - (str)->b)) + +/* The scope separator appropriate for the language being demangled. */ + +#define SCOPE_STRING(work) ((work->options & DMGL_JAVA) ? "." : "::") + +#define ARM_VTABLE_STRING "__vtbl__" /* Lucid/ARM virtual table prefix */ +#define ARM_VTABLE_STRLEN 8 /* strlen (ARM_VTABLE_STRING) */ + +/* Prototypes for local functions */ + +static void delete_work_stuff (struct work_stuff *); + +static void delete_non_B_K_work_stuff (struct work_stuff *); + +static char *mop_up (struct work_stuff *, string *, int); + +static void squangle_mop_up (struct work_stuff *); + +static void work_stuff_copy_to_from (struct work_stuff *, struct work_stuff *); + +#if 0 +static int +demangle_method_args (struct work_stuff *, const char **, string *); +#endif + +static char * +internal_cplus_demangle (struct work_stuff *, const char *); + +static int +demangle_template_template_parm (struct work_stuff *work, + const char **, string *); + +static int +demangle_template (struct work_stuff *work, const char **, string *, + string *, int, int); + +static int +arm_pt (struct work_stuff *, const char *, int, const char **, + const char **); + +static int +demangle_class_name (struct work_stuff *, const char **, string *); + +static int +demangle_qualified (struct work_stuff *, const char **, string *, + int, int); + +static int demangle_class (struct work_stuff *, const char **, string *); + +static int demangle_fund_type (struct work_stuff *, const char **, string *); + +static int demangle_signature (struct work_stuff *, const char **, string *); + +static int demangle_prefix (struct work_stuff *, const char **, string *); + +static int gnu_special (struct work_stuff *, const char **, string *); + +static int arm_special (const char **, string *); + +static void string_need (string *, int); + +static void string_delete (string *); + +static void +string_init (string *); + +static void string_clear (string *); + +#if 0 +static int string_empty (string *); +#endif + +static void string_append (string *, const char *); + +static void string_appends (string *, string *); + +static void string_appendn (string *, const char *, int); + +static void string_prepend (string *, const char *); + +static void string_prependn (string *, const char *, int); + +static void string_append_template_idx (string *, int); + +static int get_count (const char **, int *); + +static int consume_count (const char **); + +static int consume_count_with_underscores (const char**); + +static int demangle_args (struct work_stuff *, const char **, string *); + +static int demangle_nested_args (struct work_stuff*, const char**, string*); + +static int do_type (struct work_stuff *, const char **, string *); + +static int do_arg (struct work_stuff *, const char **, string *); + +static int +demangle_function_name (struct work_stuff *, const char **, string *, + const char *); + +static int +iterate_demangle_function (struct work_stuff *, + const char **, string *, const char *); + +static void remember_type (struct work_stuff *, const char *, int); + +static void remember_Btype (struct work_stuff *, const char *, int, int); + +static int register_Btype (struct work_stuff *); + +static void remember_Ktype (struct work_stuff *, const char *, int); + +static void forget_types (struct work_stuff *); + +static void forget_B_and_K_types (struct work_stuff *); + +static void string_prepends (string *, string *); + +static int +demangle_template_value_parm (struct work_stuff*, const char**, + string*, type_kind_t); + +static int +do_hpacc_template_const_value (struct work_stuff *, const char **, string *); + +static int +do_hpacc_template_literal (struct work_stuff *, const char **, string *); + +static int snarf_numeric_literal (const char **, string *); + +/* There is a TYPE_QUAL value for each type qualifier. They can be + combined by bitwise-or to form the complete set of qualifiers for a + type. */ + +#define TYPE_UNQUALIFIED 0x0 +#define TYPE_QUAL_CONST 0x1 +#define TYPE_QUAL_VOLATILE 0x2 +#define TYPE_QUAL_RESTRICT 0x4 + +static int code_for_qualifier (int); + +static const char* qualifier_string (int); + +static const char* demangle_qualifier (int); + +static int demangle_expression (struct work_stuff *, const char **, string *, + type_kind_t); + +static int +demangle_integral_value (struct work_stuff *, const char **, string *); + +static int +demangle_real_value (struct work_stuff *, const char **, string *); + +static void +demangle_arm_hp_template (struct work_stuff *, const char **, int, string *); + +static void +recursively_demangle (struct work_stuff *, const char **, string *, int); + +/* Translate count to integer, consuming tokens in the process. + Conversion terminates on the first non-digit character. + + Trying to consume something that isn't a count results in no + consumption of input and a return of -1. + + Overflow consumes the rest of the digits, and returns -1. */ + +static int +consume_count (const char **type) +{ + int count = 0; + + if (! ISDIGIT ((unsigned char)**type)) + return -1; + + while (ISDIGIT ((unsigned char)**type)) + { + count *= 10; + + /* Check for overflow. + We assume that count is represented using two's-complement; + no power of two is divisible by ten, so if an overflow occurs + when multiplying by ten, the result will not be a multiple of + ten. */ + if ((count % 10) != 0) + { + while (ISDIGIT ((unsigned char) **type)) + (*type)++; + return -1; + } + + count += **type - '0'; + (*type)++; + } + + if (count < 0) + count = -1; + + return (count); +} + + +/* Like consume_count, but for counts that are preceded and followed + by '_' if they are greater than 10. Also, -1 is returned for + failure, since 0 can be a valid value. */ + +static int +consume_count_with_underscores (const char **mangled) +{ + int idx; + + if (**mangled == '_') + { + (*mangled)++; + if (!ISDIGIT ((unsigned char)**mangled)) + return -1; + + idx = consume_count (mangled); + if (**mangled != '_') + /* The trailing underscore was missing. */ + return -1; + + (*mangled)++; + } + else + { + if (**mangled < '0' || **mangled > '9') + return -1; + + idx = **mangled - '0'; + (*mangled)++; + } + + return idx; +} + +/* C is the code for a type-qualifier. Return the TYPE_QUAL + corresponding to this qualifier. */ + +static int +code_for_qualifier (int c) +{ + switch (c) + { + case 'C': + return TYPE_QUAL_CONST; + + case 'V': + return TYPE_QUAL_VOLATILE; + + case 'u': + return TYPE_QUAL_RESTRICT; + + default: + break; + } + + /* C was an invalid qualifier. */ + abort (); +} + +/* Return the string corresponding to the qualifiers given by + TYPE_QUALS. */ + +static const char* +qualifier_string (int type_quals) +{ + switch (type_quals) + { + case TYPE_UNQUALIFIED: + return ""; + + case TYPE_QUAL_CONST: + return "const"; + + case TYPE_QUAL_VOLATILE: + return "volatile"; + + case TYPE_QUAL_RESTRICT: + return "__restrict"; + + case TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE: + return "const volatile"; + + case TYPE_QUAL_CONST | TYPE_QUAL_RESTRICT: + return "const __restrict"; + + case TYPE_QUAL_VOLATILE | TYPE_QUAL_RESTRICT: + return "volatile __restrict"; + + case TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE | TYPE_QUAL_RESTRICT: + return "const volatile __restrict"; + + default: + break; + } + + /* TYPE_QUALS was an invalid qualifier set. */ + abort (); +} + +/* C is the code for a type-qualifier. Return the string + corresponding to this qualifier. This function should only be + called with a valid qualifier code. */ + +static const char* +demangle_qualifier (int c) +{ + return qualifier_string (code_for_qualifier (c)); +} + +int +cplus_demangle_opname (const char *opname, char *result, int options) +{ + int len, len1, ret; + string type; + struct work_stuff work[1]; + const char *tem; + + len = strlen(opname); + result[0] = '\0'; + ret = 0; + memset ((char *) work, 0, sizeof (work)); + work->options = options; + + if (opname[0] == '_' && opname[1] == '_' + && opname[2] == 'o' && opname[3] == 'p') + { + /* ANSI. */ + /* type conversion operator. */ + tem = opname + 4; + if (do_type (work, &tem, &type)) + { + strcat (result, "operator "); + strncat (result, type.b, type.p - type.b); + string_delete (&type); + ret = 1; + } + } + else if (opname[0] == '_' && opname[1] == '_' + && ISLOWER((unsigned char)opname[2]) + && ISLOWER((unsigned char)opname[3])) + { + if (opname[4] == '\0') + { + /* Operator. */ + size_t i; + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + if (strlen (optable[i].in) == 2 + && memcmp (optable[i].in, opname + 2, 2) == 0) + { + strcat (result, "operator"); + strcat (result, optable[i].out); + ret = 1; + break; + } + } + } + else + { + if (opname[2] == 'a' && opname[5] == '\0') + { + /* Assignment. */ + size_t i; + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + if (strlen (optable[i].in) == 3 + && memcmp (optable[i].in, opname + 2, 3) == 0) + { + strcat (result, "operator"); + strcat (result, optable[i].out); + ret = 1; + break; + } + } + } + } + } + else if (len >= 3 + && opname[0] == 'o' + && opname[1] == 'p' + && strchr (cplus_markers, opname[2]) != NULL) + { + /* see if it's an assignment expression */ + if (len >= 10 /* op$assign_ */ + && memcmp (opname + 3, "assign_", 7) == 0) + { + size_t i; + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + len1 = len - 10; + if ((int) strlen (optable[i].in) == len1 + && memcmp (optable[i].in, opname + 10, len1) == 0) + { + strcat (result, "operator"); + strcat (result, optable[i].out); + strcat (result, "="); + ret = 1; + break; + } + } + } + else + { + size_t i; + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + len1 = len - 3; + if ((int) strlen (optable[i].in) == len1 + && memcmp (optable[i].in, opname + 3, len1) == 0) + { + strcat (result, "operator"); + strcat (result, optable[i].out); + ret = 1; + break; + } + } + } + } + else if (len >= 5 && memcmp (opname, "type", 4) == 0 + && strchr (cplus_markers, opname[4]) != NULL) + { + /* type conversion operator */ + tem = opname + 5; + if (do_type (work, &tem, &type)) + { + strcat (result, "operator "); + strncat (result, type.b, type.p - type.b); + string_delete (&type); + ret = 1; + } + } + squangle_mop_up (work); + return ret; + +} + +/* Takes operator name as e.g. "++" and returns mangled + operator name (e.g. "postincrement_expr"), or NULL if not found. + + If OPTIONS & DMGL_ANSI == 1, return the ANSI name; + if OPTIONS & DMGL_ANSI == 0, return the old GNU name. */ + +const char * +cplus_mangle_opname (const char *opname, int options) +{ + size_t i; + int len; + + len = strlen (opname); + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + if ((int) strlen (optable[i].out) == len + && (options & DMGL_ANSI) == (optable[i].flags & DMGL_ANSI) + && memcmp (optable[i].out, opname, len) == 0) + return optable[i].in; + } + return (0); +} + +/* Add a routine to set the demangling style to be sure it is valid and + allow for any demangler initialization that maybe necessary. */ + +enum demangling_styles +cplus_demangle_set_style (enum demangling_styles style) +{ + const struct demangler_engine *demangler = libiberty_demanglers; + + for (; demangler->demangling_style != unknown_demangling; ++demangler) + if (style == demangler->demangling_style) + { + current_demangling_style = style; + return current_demangling_style; + } + + return unknown_demangling; +} + +/* Do string name to style translation */ + +enum demangling_styles +cplus_demangle_name_to_style (const char *name) +{ + const struct demangler_engine *demangler = libiberty_demanglers; + + for (; demangler->demangling_style != unknown_demangling; ++demangler) + if (strcmp (name, demangler->demangling_style_name) == 0) + return demangler->demangling_style; + + return unknown_demangling; +} + +/* char *cplus_demangle (const char *mangled, int options) + + If MANGLED is a mangled function name produced by GNU C++, then + a pointer to a @code{malloc}ed string giving a C++ representation + of the name will be returned; otherwise NULL will be returned. + It is the caller's responsibility to free the string which + is returned. + + The OPTIONS arg may contain one or more of the following bits: + + DMGL_ANSI ANSI qualifiers such as `const' and `void' are + included. + DMGL_PARAMS Function parameters are included. + + For example, + + cplus_demangle ("foo__1Ai", DMGL_PARAMS) => "A::foo(int)" + cplus_demangle ("foo__1Ai", DMGL_PARAMS | DMGL_ANSI) => "A::foo(int)" + cplus_demangle ("foo__1Ai", 0) => "A::foo" + + cplus_demangle ("foo__1Afe", DMGL_PARAMS) => "A::foo(float,...)" + cplus_demangle ("foo__1Afe", DMGL_PARAMS | DMGL_ANSI)=> "A::foo(float,...)" + cplus_demangle ("foo__1Afe", 0) => "A::foo" + + Note that any leading underscores, or other such characters prepended by + the compilation system, are presumed to have already been stripped from + MANGLED. */ + +char * +cplus_demangle (const char *mangled, int options) +{ + char *ret; + struct work_stuff work[1]; + + if (current_demangling_style == no_demangling) + return xstrdup (mangled); + + memset ((char *) work, 0, sizeof (work)); + work->options = options; + if ((work->options & DMGL_STYLE_MASK) == 0) + work->options |= (int) current_demangling_style & DMGL_STYLE_MASK; + + /* The V3 ABI demangling is implemented elsewhere. */ + if (GNU_V3_DEMANGLING || AUTO_DEMANGLING) + { + ret = cplus_demangle_v3 (mangled, work->options); + if (ret || GNU_V3_DEMANGLING) + return ret; + } + + if (JAVA_DEMANGLING) + { + ret = java_demangle_v3 (mangled); + if (ret) + return ret; + } + + if (GNAT_DEMANGLING) + return ada_demangle (mangled, options); + + ret = internal_cplus_demangle (work, mangled); + squangle_mop_up (work); + return (ret); +} + +/* Demangle ada names. The encoding is documented in gcc/ada/exp_dbug.ads. */ + +char * +ada_demangle (const char *mangled, int option ATTRIBUTE_UNUSED) +{ + int len0; + const char* p; + char *d; + char *demangled; + + /* Discard leading _ada_, which is used for library level subprograms. */ + if (strncmp (mangled, "_ada_", 5) == 0) + mangled += 5; + + /* All ada unit names are lower-case. */ + if (!ISLOWER (mangled[0])) + goto unknown; + + /* Most of the demangling will trivially remove chars. Operator names + may add one char but because they are always preceeded by '__' which is + replaced by '.', they eventually never expand the size. + A few special names such as '___elabs' add a few chars (at most 7), but + they occur only once. */ + len0 = strlen (mangled) + 7 + 1; + demangled = XNEWVEC (char, len0); + + d = demangled; + p = mangled; + while (1) + { + /* An entity names is expected. */ + if (ISLOWER (*p)) + { + /* An identifier, which is always lower case. */ + do + *d++ = *p++; + while (ISLOWER(*p) || ISDIGIT (*p) + || (p[0] == '_' && (ISLOWER (p[1]) || ISDIGIT (p[1])))); + } + else if (p[0] == 'O') + { + /* An operator name. */ + static const char * const operators[][2] = + {{"Oabs", "abs"}, {"Oand", "and"}, {"Omod", "mod"}, + {"Onot", "not"}, {"Oor", "or"}, {"Orem", "rem"}, + {"Oxor", "xor"}, {"Oeq", "="}, {"One", "/="}, + {"Olt", "<"}, {"Ole", "<="}, {"Ogt", ">"}, + {"Oge", ">="}, {"Oadd", "+"}, {"Osubtract", "-"}, + {"Oconcat", "&"}, {"Omultiply", "*"}, {"Odivide", "/"}, + {"Oexpon", "**"}, {NULL, NULL}}; + int k; + + for (k = 0; operators[k][0] != NULL; k++) + { + size_t slen = strlen (operators[k][0]); + if (strncmp (p, operators[k][0], slen) == 0) + { + p += slen; + slen = strlen (operators[k][1]); + *d++ = '"'; + memcpy (d, operators[k][1], slen); + d += slen; + *d++ = '"'; + break; + } + } + /* Operator not found. */ + if (operators[k][0] == NULL) + goto unknown; + } + else + { + /* Not a GNAT encoding. */ + goto unknown; + } + + /* The name can be directly followed by some uppercase letters. */ + if (p[0] == 'T' && p[1] == 'K') + { + /* Task stuff. */ + if (p[2] == 'B' && p[3] == 0) + { + /* Subprogram for task body. */ + break; + } + else if (p[2] == '_' && p[3] == '_') + { + /* Inner declarations in a task. */ + p += 4; + *d++ = '.'; + continue; + } + else + goto unknown; + } + if (p[0] == 'E' && p[1] == 0) + { + /* Exception name. */ + goto unknown; + } + if ((p[0] == 'P' || p[0] == 'N') && p[1] == 0) + { + /* Protected type subprogram. */ + break; + } + if ((*p == 'N' || *p == 'S') && p[1] == 0) + { + /* Enumerated type name table. */ + goto unknown; + } + if (p[0] == 'X') + { + /* Body nested. */ + p++; + while (p[0] == 'n' || p[0] == 'b') + p++; + } + if (p[0] == 'S' && p[1] != 0 && (p[2] == '_' || p[2] == 0)) + { + /* Stream operations. */ + const char *name; + switch (p[1]) + { + case 'R': + name = "'Read"; + break; + case 'W': + name = "'Write"; + break; + case 'I': + name = "'Input"; + break; + case 'O': + name = "'Output"; + break; + default: + goto unknown; + } + p += 2; + strcpy (d, name); + d += strlen (name); + } + else if (p[0] == 'D') + { + /* Controlled type operation. */ + const char *name; + switch (p[1]) + { + case 'F': + name = ".Finalize"; + break; + case 'A': + name = ".Adjust"; + break; + default: + goto unknown; + } + strcpy (d, name); + d += strlen (name); + break; + } + + if (p[0] == '_') + { + /* Separator. */ + if (p[1] == '_') + { + /* Standard separator. Handled first. */ + p += 2; + + if (ISDIGIT (*p)) + { + /* Overloading number. */ + do + p++; + while (ISDIGIT (*p) || (p[0] == '_' && ISDIGIT (p[1]))); + if (*p == 'X') + { + p++; + while (p[0] == 'n' || p[0] == 'b') + p++; + } + } + else if (p[0] == '_' && p[1] != '_') + { + /* Special names. */ + static const char * const special[][2] = { + { "_elabb", "'Elab_Body" }, + { "_elabs", "'Elab_Spec" }, + { "_size", "'Size" }, + { "_alignment", "'Alignment" }, + { "_assign", ".\":=\"" }, + { NULL, NULL } + }; + int k; + + for (k = 0; special[k][0] != NULL; k++) + { + size_t slen = strlen (special[k][0]); + if (strncmp (p, special[k][0], slen) == 0) + { + p += slen; + slen = strlen (special[k][1]); + memcpy (d, special[k][1], slen); + d += slen; + break; + } + } + if (special[k][0] != NULL) + break; + else + goto unknown; + } + else + { + *d++ = '.'; + continue; + } + } + else if (p[1] == 'B' || p[1] == 'E') + { + /* Entry Body or barrier Evaluation. */ + p += 2; + while (ISDIGIT (*p)) + p++; + if (p[0] == 's' && p[1] == 0) + break; + else + goto unknown; + } + else + goto unknown; + } + + if (p[0] == '.' && ISDIGIT (p[1])) + { + /* Nested subprogram. */ + p += 2; + while (ISDIGIT (*p)) + p++; + } + if (*p == 0) + { + /* End of mangled name. */ + break; + } + else + goto unknown; + } + *d = 0; + return demangled; + + unknown: + len0 = strlen (mangled); + demangled = XNEWVEC (char, len0 + 3); + + if (mangled[0] == '<') + strcpy (demangled, mangled); + else + sprintf (demangled, "<%s>", mangled); + + return demangled; +} + +/* This function performs most of what cplus_demangle use to do, but + to be able to demangle a name with a B, K or n code, we need to + have a longer term memory of what types have been seen. The original + now initializes and cleans up the squangle code info, while internal + calls go directly to this routine to avoid resetting that info. */ + +static char * +internal_cplus_demangle (struct work_stuff *work, const char *mangled) +{ + + string decl; + int success = 0; + char *demangled = NULL; + int s1, s2, s3, s4; + s1 = work->constructor; + s2 = work->destructor; + s3 = work->static_type; + s4 = work->type_quals; + work->constructor = work->destructor = 0; + work->type_quals = TYPE_UNQUALIFIED; + work->dllimported = 0; + + if ((mangled != NULL) && (*mangled != '\0')) + { + string_init (&decl); + + /* First check to see if gnu style demangling is active and if the + string to be demangled contains a CPLUS_MARKER. If so, attempt to + recognize one of the gnu special forms rather than looking for a + standard prefix. In particular, don't worry about whether there + is a "__" string in the mangled string. Consider "_$_5__foo" for + example. */ + + if ((AUTO_DEMANGLING || GNU_DEMANGLING)) + { + success = gnu_special (work, &mangled, &decl); + } + if (!success) + { + success = demangle_prefix (work, &mangled, &decl); + } + if (success && (*mangled != '\0')) + { + success = demangle_signature (work, &mangled, &decl); + } + if (work->constructor == 2) + { + string_prepend (&decl, "global constructors keyed to "); + work->constructor = 0; + } + else if (work->destructor == 2) + { + string_prepend (&decl, "global destructors keyed to "); + work->destructor = 0; + } + else if (work->dllimported == 1) + { + string_prepend (&decl, "import stub for "); + work->dllimported = 0; + } + demangled = mop_up (work, &decl, success); + } + work->constructor = s1; + work->destructor = s2; + work->static_type = s3; + work->type_quals = s4; + return demangled; +} + + +/* Clear out and squangling related storage */ +static void +squangle_mop_up (struct work_stuff *work) +{ + /* clean up the B and K type mangling types. */ + forget_B_and_K_types (work); + if (work -> btypevec != NULL) + { + free ((char *) work -> btypevec); + } + if (work -> ktypevec != NULL) + { + free ((char *) work -> ktypevec); + } +} + + +/* Copy the work state and storage. */ + +static void +work_stuff_copy_to_from (struct work_stuff *to, struct work_stuff *from) +{ + int i; + + delete_work_stuff (to); + + /* Shallow-copy scalars. */ + memcpy (to, from, sizeof (*to)); + + /* Deep-copy dynamic storage. */ + if (from->typevec_size) + to->typevec = XNEWVEC (char *, from->typevec_size); + + for (i = 0; i < from->ntypes; i++) + { + int len = strlen (from->typevec[i]) + 1; + + to->typevec[i] = XNEWVEC (char, len); + memcpy (to->typevec[i], from->typevec[i], len); + } + + if (from->ksize) + to->ktypevec = XNEWVEC (char *, from->ksize); + + for (i = 0; i < from->numk; i++) + { + int len = strlen (from->ktypevec[i]) + 1; + + to->ktypevec[i] = XNEWVEC (char, len); + memcpy (to->ktypevec[i], from->ktypevec[i], len); + } + + if (from->bsize) + to->btypevec = XNEWVEC (char *, from->bsize); + + for (i = 0; i < from->numb; i++) + { + int len = strlen (from->btypevec[i]) + 1; + + to->btypevec[i] = XNEWVEC (char , len); + memcpy (to->btypevec[i], from->btypevec[i], len); + } + + if (from->ntmpl_args) + to->tmpl_argvec = XNEWVEC (char *, from->ntmpl_args); + + for (i = 0; i < from->ntmpl_args; i++) + { + int len = strlen (from->tmpl_argvec[i]) + 1; + + to->tmpl_argvec[i] = XNEWVEC (char, len); + memcpy (to->tmpl_argvec[i], from->tmpl_argvec[i], len); + } + + if (from->previous_argument) + { + to->previous_argument = XNEW (string); + string_init (to->previous_argument); + string_appends (to->previous_argument, from->previous_argument); + } +} + + +/* Delete dynamic stuff in work_stuff that is not to be re-used. */ + +static void +delete_non_B_K_work_stuff (struct work_stuff *work) +{ + /* Discard the remembered types, if any. */ + + forget_types (work); + if (work -> typevec != NULL) + { + free ((char *) work -> typevec); + work -> typevec = NULL; + work -> typevec_size = 0; + } + if (work->tmpl_argvec) + { + int i; + + for (i = 0; i < work->ntmpl_args; i++) + if (work->tmpl_argvec[i]) + free ((char*) work->tmpl_argvec[i]); + + free ((char*) work->tmpl_argvec); + work->tmpl_argvec = NULL; + } + if (work->previous_argument) + { + string_delete (work->previous_argument); + free ((char*) work->previous_argument); + work->previous_argument = NULL; + } +} + + +/* Delete all dynamic storage in work_stuff. */ +static void +delete_work_stuff (struct work_stuff *work) +{ + delete_non_B_K_work_stuff (work); + squangle_mop_up (work); +} + + +/* Clear out any mangled storage */ + +static char * +mop_up (struct work_stuff *work, string *declp, int success) +{ + char *demangled = NULL; + + delete_non_B_K_work_stuff (work); + + /* If demangling was successful, ensure that the demangled string is null + terminated and return it. Otherwise, free the demangling decl. */ + + if (!success) + { + string_delete (declp); + } + else + { + string_appendn (declp, "", 1); + demangled = declp->b; + } + return (demangled); +} + +/* + +LOCAL FUNCTION + + demangle_signature -- demangle the signature part of a mangled name + +SYNOPSIS + + static int + demangle_signature (struct work_stuff *work, const char **mangled, + string *declp); + +DESCRIPTION + + Consume and demangle the signature portion of the mangled name. + + DECLP is the string where demangled output is being built. At + entry it contains the demangled root name from the mangled name + prefix. I.E. either a demangled operator name or the root function + name. In some special cases, it may contain nothing. + + *MANGLED points to the current unconsumed location in the mangled + name. As tokens are consumed and demangling is performed, the + pointer is updated to continuously point at the next token to + be consumed. + + Demangling GNU style mangled names is nasty because there is no + explicit token that marks the start of the outermost function + argument list. */ + +static int +demangle_signature (struct work_stuff *work, + const char **mangled, string *declp) +{ + int success = 1; + int func_done = 0; + int expect_func = 0; + int expect_return_type = 0; + const char *oldmangled = NULL; + string trawname; + string tname; + + while (success && (**mangled != '\0')) + { + switch (**mangled) + { + case 'Q': + oldmangled = *mangled; + success = demangle_qualified (work, mangled, declp, 1, 0); + if (success) + remember_type (work, oldmangled, *mangled - oldmangled); + if (AUTO_DEMANGLING || GNU_DEMANGLING) + expect_func = 1; + oldmangled = NULL; + break; + + case 'K': + oldmangled = *mangled; + success = demangle_qualified (work, mangled, declp, 1, 0); + if (AUTO_DEMANGLING || GNU_DEMANGLING) + { + expect_func = 1; + } + oldmangled = NULL; + break; + + case 'S': + /* Static member function */ + if (oldmangled == NULL) + { + oldmangled = *mangled; + } + (*mangled)++; + work -> static_type = 1; + break; + + case 'C': + case 'V': + case 'u': + work->type_quals |= code_for_qualifier (**mangled); + + /* a qualified member function */ + if (oldmangled == NULL) + oldmangled = *mangled; + (*mangled)++; + break; + + case 'L': + /* Local class name follows after "Lnnn_" */ + if (HP_DEMANGLING) + { + while (**mangled && (**mangled != '_')) + (*mangled)++; + if (!**mangled) + success = 0; + else + (*mangled)++; + } + else + success = 0; + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + if (oldmangled == NULL) + { + oldmangled = *mangled; + } + work->temp_start = -1; /* uppermost call to demangle_class */ + success = demangle_class (work, mangled, declp); + if (success) + { + remember_type (work, oldmangled, *mangled - oldmangled); + } + if (AUTO_DEMANGLING || GNU_DEMANGLING || EDG_DEMANGLING) + { + /* EDG and others will have the "F", so we let the loop cycle + if we are looking at one. */ + if (**mangled != 'F') + expect_func = 1; + } + oldmangled = NULL; + break; + + case 'B': + { + string s; + success = do_type (work, mangled, &s); + if (success) + { + string_append (&s, SCOPE_STRING (work)); + string_prepends (declp, &s); + string_delete (&s); + } + oldmangled = NULL; + expect_func = 1; + } + break; + + case 'F': + /* Function */ + /* ARM/HP style demangling includes a specific 'F' character after + the class name. For GNU style, it is just implied. So we can + safely just consume any 'F' at this point and be compatible + with either style. */ + + oldmangled = NULL; + func_done = 1; + (*mangled)++; + + /* For lucid/ARM/HP style we have to forget any types we might + have remembered up to this point, since they were not argument + types. GNU style considers all types seen as available for + back references. See comment in demangle_args() */ + + if (LUCID_DEMANGLING || ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) + { + forget_types (work); + } + success = demangle_args (work, mangled, declp); + /* After picking off the function args, we expect to either + find the function return type (preceded by an '_') or the + end of the string. */ + if (success && (AUTO_DEMANGLING || EDG_DEMANGLING) && **mangled == '_') + { + ++(*mangled); + /* At this level, we do not care about the return type. */ + success = do_type (work, mangled, &tname); + string_delete (&tname); + } + + break; + + case 't': + /* G++ Template */ + string_init(&trawname); + string_init(&tname); + if (oldmangled == NULL) + { + oldmangled = *mangled; + } + success = demangle_template (work, mangled, &tname, + &trawname, 1, 1); + if (success) + { + remember_type (work, oldmangled, *mangled - oldmangled); + } + string_append (&tname, SCOPE_STRING (work)); + + string_prepends(declp, &tname); + if (work -> destructor & 1) + { + string_prepend (&trawname, "~"); + string_appends (declp, &trawname); + work->destructor -= 1; + } + if ((work->constructor & 1) || (work->destructor & 1)) + { + string_appends (declp, &trawname); + work->constructor -= 1; + } + string_delete(&trawname); + string_delete(&tname); + oldmangled = NULL; + expect_func = 1; + break; + + case '_': + if ((AUTO_DEMANGLING || GNU_DEMANGLING) && expect_return_type) + { + /* Read the return type. */ + string return_type; + + (*mangled)++; + success = do_type (work, mangled, &return_type); + APPEND_BLANK (&return_type); + + string_prepends (declp, &return_type); + string_delete (&return_type); + break; + } + else + /* At the outermost level, we cannot have a return type specified, + so if we run into another '_' at this point we are dealing with + a mangled name that is either bogus, or has been mangled by + some algorithm we don't know how to deal with. So just + reject the entire demangling. */ + /* However, "_nnn" is an expected suffix for alternate entry point + numbered nnn for a function, with HP aCC, so skip over that + without reporting failure. pai/1997-09-04 */ + if (HP_DEMANGLING) + { + (*mangled)++; + while (**mangled && ISDIGIT ((unsigned char)**mangled)) + (*mangled)++; + } + else + success = 0; + break; + + case 'H': + if (AUTO_DEMANGLING || GNU_DEMANGLING) + { + /* A G++ template function. Read the template arguments. */ + success = demangle_template (work, mangled, declp, 0, 0, + 0); + if (!(work->constructor & 1)) + expect_return_type = 1; + (*mangled)++; + break; + } + else + /* fall through */ + {;} + + default: + if (AUTO_DEMANGLING || GNU_DEMANGLING) + { + /* Assume we have stumbled onto the first outermost function + argument token, and start processing args. */ + func_done = 1; + success = demangle_args (work, mangled, declp); + } + else + { + /* Non-GNU demanglers use a specific token to mark the start + of the outermost function argument tokens. Typically 'F', + for ARM/HP-demangling, for example. So if we find something + we are not prepared for, it must be an error. */ + success = 0; + } + break; + } + /* + if (AUTO_DEMANGLING || GNU_DEMANGLING) + */ + { + if (success && expect_func) + { + func_done = 1; + if (LUCID_DEMANGLING || ARM_DEMANGLING || EDG_DEMANGLING) + { + forget_types (work); + } + success = demangle_args (work, mangled, declp); + /* Since template include the mangling of their return types, + we must set expect_func to 0 so that we don't try do + demangle more arguments the next time we get here. */ + expect_func = 0; + } + } + } + if (success && !func_done) + { + if (AUTO_DEMANGLING || GNU_DEMANGLING) + { + /* With GNU style demangling, bar__3foo is 'foo::bar(void)', and + bar__3fooi is 'foo::bar(int)'. We get here when we find the + first case, and need to ensure that the '(void)' gets added to + the current declp. Note that with ARM/HP, the first case + represents the name of a static data member 'foo::bar', + which is in the current declp, so we leave it alone. */ + success = demangle_args (work, mangled, declp); + } + } + if (success && PRINT_ARG_TYPES) + { + if (work->static_type) + string_append (declp, " static"); + if (work->type_quals != TYPE_UNQUALIFIED) + { + APPEND_BLANK (declp); + string_append (declp, qualifier_string (work->type_quals)); + } + } + + return (success); +} + +#if 0 + +static int +demangle_method_args (struct work_stuff *work, const char **mangled, + string *declp) +{ + int success = 0; + + if (work -> static_type) + { + string_append (declp, *mangled + 1); + *mangled += strlen (*mangled); + success = 1; + } + else + { + success = demangle_args (work, mangled, declp); + } + return (success); +} + +#endif + +static int +demangle_template_template_parm (struct work_stuff *work, + const char **mangled, string *tname) +{ + int i; + int r; + int need_comma = 0; + int success = 1; + string temp; + + string_append (tname, "template <"); + /* get size of template parameter list */ + if (get_count (mangled, &r)) + { + for (i = 0; i < r; i++) + { + if (need_comma) + { + string_append (tname, ", "); + } + + /* Z for type parameters */ + if (**mangled == 'Z') + { + (*mangled)++; + string_append (tname, "class"); + } + /* z for template parameters */ + else if (**mangled == 'z') + { + (*mangled)++; + success = + demangle_template_template_parm (work, mangled, tname); + if (!success) + { + break; + } + } + else + { + /* temp is initialized in do_type */ + success = do_type (work, mangled, &temp); + if (success) + { + string_appends (tname, &temp); + } + string_delete(&temp); + if (!success) + { + break; + } + } + need_comma = 1; + } + + } + if (tname->p[-1] == '>') + string_append (tname, " "); + string_append (tname, "> class"); + return (success); +} + +static int +demangle_expression (struct work_stuff *work, const char **mangled, + string *s, type_kind_t tk) +{ + int need_operator = 0; + int success; + + success = 1; + string_appendn (s, "(", 1); + (*mangled)++; + while (success && **mangled != 'W' && **mangled != '\0') + { + if (need_operator) + { + size_t i; + size_t len; + + success = 0; + + len = strlen (*mangled); + + for (i = 0; i < ARRAY_SIZE (optable); ++i) + { + size_t l = strlen (optable[i].in); + + if (l <= len + && memcmp (optable[i].in, *mangled, l) == 0) + { + string_appendn (s, " ", 1); + string_append (s, optable[i].out); + string_appendn (s, " ", 1); + success = 1; + (*mangled) += l; + break; + } + } + + if (!success) + break; + } + else + need_operator = 1; + + success = demangle_template_value_parm (work, mangled, s, tk); + } + + if (**mangled != 'W') + success = 0; + else + { + string_appendn (s, ")", 1); + (*mangled)++; + } + + return success; +} + +static int +demangle_integral_value (struct work_stuff *work, + const char **mangled, string *s) +{ + int success; + + if (**mangled == 'E') + success = demangle_expression (work, mangled, s, tk_integral); + else if (**mangled == 'Q' || **mangled == 'K') + success = demangle_qualified (work, mangled, s, 0, 1); + else + { + int value; + + /* By default, we let the number decide whether we shall consume an + underscore. */ + int multidigit_without_leading_underscore = 0; + int leave_following_underscore = 0; + + success = 0; + + if (**mangled == '_') + { + if (mangled[0][1] == 'm') + { + /* Since consume_count_with_underscores does not handle the + `m'-prefix we must do it here, using consume_count and + adjusting underscores: we have to consume the underscore + matching the prepended one. */ + multidigit_without_leading_underscore = 1; + string_appendn (s, "-", 1); + (*mangled) += 2; + } + else + { + /* Do not consume a following underscore; + consume_count_with_underscores will consume what + should be consumed. */ + leave_following_underscore = 1; + } + } + else + { + /* Negative numbers are indicated with a leading `m'. */ + if (**mangled == 'm') + { + string_appendn (s, "-", 1); + (*mangled)++; + } + /* Since consume_count_with_underscores does not handle + multi-digit numbers that do not start with an underscore, + and this number can be an integer template parameter, + we have to call consume_count. */ + multidigit_without_leading_underscore = 1; + /* These multi-digit numbers never end on an underscore, + so if there is one then don't eat it. */ + leave_following_underscore = 1; + } + + /* We must call consume_count if we expect to remove a trailing + underscore, since consume_count_with_underscores expects + the leading underscore (that we consumed) if it is to handle + multi-digit numbers. */ + if (multidigit_without_leading_underscore) + value = consume_count (mangled); + else + value = consume_count_with_underscores (mangled); + + if (value != -1) + { + char buf[INTBUF_SIZE]; + sprintf (buf, "%d", value); + string_append (s, buf); + + /* Numbers not otherwise delimited, might have an underscore + appended as a delimeter, which we should skip. + + ??? This used to always remove a following underscore, which + is wrong. If other (arbitrary) cases are followed by an + underscore, we need to do something more radical. */ + + if ((value > 9 || multidigit_without_leading_underscore) + && ! leave_following_underscore + && **mangled == '_') + (*mangled)++; + + /* All is well. */ + success = 1; + } + } + + return success; +} + +/* Demangle the real value in MANGLED. */ + +static int +demangle_real_value (struct work_stuff *work, + const char **mangled, string *s) +{ + if (**mangled == 'E') + return demangle_expression (work, mangled, s, tk_real); + + if (**mangled == 'm') + { + string_appendn (s, "-", 1); + (*mangled)++; + } + while (ISDIGIT ((unsigned char)**mangled)) + { + string_appendn (s, *mangled, 1); + (*mangled)++; + } + if (**mangled == '.') /* fraction */ + { + string_appendn (s, ".", 1); + (*mangled)++; + while (ISDIGIT ((unsigned char)**mangled)) + { + string_appendn (s, *mangled, 1); + (*mangled)++; + } + } + if (**mangled == 'e') /* exponent */ + { + string_appendn (s, "e", 1); + (*mangled)++; + while (ISDIGIT ((unsigned char)**mangled)) + { + string_appendn (s, *mangled, 1); + (*mangled)++; + } + } + + return 1; +} + +static int +demangle_template_value_parm (struct work_stuff *work, const char **mangled, + string *s, type_kind_t tk) +{ + int success = 1; + + if (**mangled == 'Y') + { + /* The next argument is a template parameter. */ + int idx; + + (*mangled)++; + idx = consume_count_with_underscores (mangled); + if (idx == -1 + || (work->tmpl_argvec && idx >= work->ntmpl_args) + || consume_count_with_underscores (mangled) == -1) + return -1; + if (work->tmpl_argvec) + string_append (s, work->tmpl_argvec[idx]); + else + string_append_template_idx (s, idx); + } + else if (tk == tk_integral) + success = demangle_integral_value (work, mangled, s); + else if (tk == tk_char) + { + char tmp[2]; + int val; + if (**mangled == 'm') + { + string_appendn (s, "-", 1); + (*mangled)++; + } + string_appendn (s, "'", 1); + val = consume_count(mangled); + if (val <= 0) + success = 0; + else + { + tmp[0] = (char)val; + tmp[1] = '\0'; + string_appendn (s, &tmp[0], 1); + string_appendn (s, "'", 1); + } + } + else if (tk == tk_bool) + { + int val = consume_count (mangled); + if (val == 0) + string_appendn (s, "false", 5); + else if (val == 1) + string_appendn (s, "true", 4); + else + success = 0; + } + else if (tk == tk_real) + success = demangle_real_value (work, mangled, s); + else if (tk == tk_pointer || tk == tk_reference) + { + if (**mangled == 'Q') + success = demangle_qualified (work, mangled, s, + /*isfuncname=*/0, + /*append=*/1); + else + { + int symbol_len = consume_count (mangled); + if (symbol_len == -1) + return -1; + if (symbol_len == 0) + string_appendn (s, "0", 1); + else + { + char *p = XNEWVEC (char, symbol_len + 1), *q; + strncpy (p, *mangled, symbol_len); + p [symbol_len] = '\0'; + /* We use cplus_demangle here, rather than + internal_cplus_demangle, because the name of the entity + mangled here does not make use of any of the squangling + or type-code information we have built up thus far; it is + mangled independently. */ + q = cplus_demangle (p, work->options); + if (tk == tk_pointer) + string_appendn (s, "&", 1); + /* FIXME: Pointer-to-member constants should get a + qualifying class name here. */ + if (q) + { + string_append (s, q); + free (q); + } + else + string_append (s, p); + free (p); + } + *mangled += symbol_len; + } + } + + return success; +} + +/* Demangle the template name in MANGLED. The full name of the + template (e.g., S) is placed in TNAME. The name without the + template parameters (e.g. S) is placed in TRAWNAME if TRAWNAME is + non-NULL. If IS_TYPE is nonzero, this template is a type template, + not a function template. If both IS_TYPE and REMEMBER are nonzero, + the template is remembered in the list of back-referenceable + types. */ + +static int +demangle_template (struct work_stuff *work, const char **mangled, + string *tname, string *trawname, + int is_type, int remember) +{ + int i; + int r; + int need_comma = 0; + int success = 0; + int is_java_array = 0; + string temp; + + (*mangled)++; + if (is_type) + { + /* get template name */ + if (**mangled == 'z') + { + int idx; + (*mangled)++; + (*mangled)++; + + idx = consume_count_with_underscores (mangled); + if (idx == -1 + || (work->tmpl_argvec && idx >= work->ntmpl_args) + || consume_count_with_underscores (mangled) == -1) + return (0); + + if (work->tmpl_argvec) + { + string_append (tname, work->tmpl_argvec[idx]); + if (trawname) + string_append (trawname, work->tmpl_argvec[idx]); + } + else + { + string_append_template_idx (tname, idx); + if (trawname) + string_append_template_idx (trawname, idx); + } + } + else + { + if ((r = consume_count (mangled)) <= 0 + || (int) strlen (*mangled) < r) + { + return (0); + } + is_java_array = (work -> options & DMGL_JAVA) + && strncmp (*mangled, "JArray1Z", 8) == 0; + if (! is_java_array) + { + string_appendn (tname, *mangled, r); + } + if (trawname) + string_appendn (trawname, *mangled, r); + *mangled += r; + } + } + if (!is_java_array) + string_append (tname, "<"); + /* get size of template parameter list */ + if (!get_count (mangled, &r)) + { + return (0); + } + if (!is_type) + { + /* Create an array for saving the template argument values. */ + work->tmpl_argvec = XNEWVEC (char *, r); + work->ntmpl_args = r; + for (i = 0; i < r; i++) + work->tmpl_argvec[i] = 0; + } + for (i = 0; i < r; i++) + { + if (need_comma) + { + string_append (tname, ", "); + } + /* Z for type parameters */ + if (**mangled == 'Z') + { + (*mangled)++; + /* temp is initialized in do_type */ + success = do_type (work, mangled, &temp); + if (success) + { + string_appends (tname, &temp); + + if (!is_type) + { + /* Save the template argument. */ + int len = temp.p - temp.b; + work->tmpl_argvec[i] = XNEWVEC (char, len + 1); + memcpy (work->tmpl_argvec[i], temp.b, len); + work->tmpl_argvec[i][len] = '\0'; + } + } + string_delete(&temp); + if (!success) + { + break; + } + } + /* z for template parameters */ + else if (**mangled == 'z') + { + int r2; + (*mangled)++; + success = demangle_template_template_parm (work, mangled, tname); + + if (success + && (r2 = consume_count (mangled)) > 0 + && (int) strlen (*mangled) >= r2) + { + string_append (tname, " "); + string_appendn (tname, *mangled, r2); + if (!is_type) + { + /* Save the template argument. */ + int len = r2; + work->tmpl_argvec[i] = XNEWVEC (char, len + 1); + memcpy (work->tmpl_argvec[i], *mangled, len); + work->tmpl_argvec[i][len] = '\0'; + } + *mangled += r2; + } + if (!success) + { + break; + } + } + else + { + string param; + string* s; + + /* otherwise, value parameter */ + + /* temp is initialized in do_type */ + success = do_type (work, mangled, &temp); + string_delete(&temp); + if (!success) + break; + + if (!is_type) + { + s = ¶m; + string_init (s); + } + else + s = tname; + + success = demangle_template_value_parm (work, mangled, s, + (type_kind_t) success); + + if (!success) + { + if (!is_type) + string_delete (s); + success = 0; + break; + } + + if (!is_type) + { + int len = s->p - s->b; + work->tmpl_argvec[i] = XNEWVEC (char, len + 1); + memcpy (work->tmpl_argvec[i], s->b, len); + work->tmpl_argvec[i][len] = '\0'; + + string_appends (tname, s); + string_delete (s); + } + } + need_comma = 1; + } + if (is_java_array) + { + string_append (tname, "[]"); + } + else + { + if (tname->p[-1] == '>') + string_append (tname, " "); + string_append (tname, ">"); + } + + if (is_type && remember) + { + const int bindex = register_Btype (work); + remember_Btype (work, tname->b, LEN_STRING (tname), bindex); + } + + /* + if (work -> static_type) + { + string_append (declp, *mangled + 1); + *mangled += strlen (*mangled); + success = 1; + } + else + { + success = demangle_args (work, mangled, declp); + } + } + */ + return (success); +} + +static int +arm_pt (struct work_stuff *work, const char *mangled, + int n, const char **anchor, const char **args) +{ + /* Check if ARM template with "__pt__" in it ("parameterized type") */ + /* Allow HP also here, because HP's cfront compiler follows ARM to some extent */ + if ((ARM_DEMANGLING || HP_DEMANGLING) && (*anchor = strstr (mangled, "__pt__"))) + { + int len; + *args = *anchor + 6; + len = consume_count (args); + if (len == -1) + return 0; + if (*args + len == mangled + n && **args == '_') + { + ++*args; + return 1; + } + } + if (AUTO_DEMANGLING || EDG_DEMANGLING) + { + if ((*anchor = strstr (mangled, "__tm__")) + || (*anchor = strstr (mangled, "__ps__")) + || (*anchor = strstr (mangled, "__pt__"))) + { + int len; + *args = *anchor + 6; + len = consume_count (args); + if (len == -1) + return 0; + if (*args + len == mangled + n && **args == '_') + { + ++*args; + return 1; + } + } + else if ((*anchor = strstr (mangled, "__S"))) + { + int len; + *args = *anchor + 3; + len = consume_count (args); + if (len == -1) + return 0; + if (*args + len == mangled + n && **args == '_') + { + ++*args; + return 1; + } + } + } + + return 0; +} + +static void +demangle_arm_hp_template (struct work_stuff *work, const char **mangled, + int n, string *declp) +{ + const char *p; + const char *args; + const char *e = *mangled + n; + string arg; + + /* Check for HP aCC template spec: classXt1t2 where t1, t2 are + template args */ + if (HP_DEMANGLING && ((*mangled)[n] == 'X')) + { + char *start_spec_args = NULL; + int hold_options; + + /* First check for and omit template specialization pseudo-arguments, + such as in "Spec<#1,#1.*>" */ + start_spec_args = strchr (*mangled, '<'); + if (start_spec_args && (start_spec_args - *mangled < n)) + string_appendn (declp, *mangled, start_spec_args - *mangled); + else + string_appendn (declp, *mangled, n); + (*mangled) += n + 1; + string_init (&arg); + if (work->temp_start == -1) /* non-recursive call */ + work->temp_start = declp->p - declp->b; + + /* We want to unconditionally demangle parameter types in + template parameters. */ + hold_options = work->options; + work->options |= DMGL_PARAMS; + + string_append (declp, "<"); + while (1) + { + string_delete (&arg); + switch (**mangled) + { + case 'T': + /* 'T' signals a type parameter */ + (*mangled)++; + if (!do_type (work, mangled, &arg)) + goto hpacc_template_args_done; + break; + + case 'U': + case 'S': + /* 'U' or 'S' signals an integral value */ + if (!do_hpacc_template_const_value (work, mangled, &arg)) + goto hpacc_template_args_done; + break; + + case 'A': + /* 'A' signals a named constant expression (literal) */ + if (!do_hpacc_template_literal (work, mangled, &arg)) + goto hpacc_template_args_done; + break; + + default: + /* Today, 1997-09-03, we have only the above types + of template parameters */ + /* FIXME: maybe this should fail and return null */ + goto hpacc_template_args_done; + } + string_appends (declp, &arg); + /* Check if we're at the end of template args. + 0 if at end of static member of template class, + _ if done with template args for a function */ + if ((**mangled == '\000') || (**mangled == '_')) + break; + else + string_append (declp, ","); + } + hpacc_template_args_done: + string_append (declp, ">"); + string_delete (&arg); + if (**mangled == '_') + (*mangled)++; + work->options = hold_options; + return; + } + /* ARM template? (Also handles HP cfront extensions) */ + else if (arm_pt (work, *mangled, n, &p, &args)) + { + int hold_options; + string type_str; + + string_init (&arg); + string_appendn (declp, *mangled, p - *mangled); + if (work->temp_start == -1) /* non-recursive call */ + work->temp_start = declp->p - declp->b; + + /* We want to unconditionally demangle parameter types in + template parameters. */ + hold_options = work->options; + work->options |= DMGL_PARAMS; + + string_append (declp, "<"); + /* should do error checking here */ + while (args < e) { + string_delete (&arg); + + /* Check for type or literal here */ + switch (*args) + { + /* HP cfront extensions to ARM for template args */ + /* spec: Xt1Lv1 where t1 is a type, v1 is a literal value */ + /* FIXME: We handle only numeric literals for HP cfront */ + case 'X': + /* A typed constant value follows */ + args++; + if (!do_type (work, &args, &type_str)) + goto cfront_template_args_done; + string_append (&arg, "("); + string_appends (&arg, &type_str); + string_delete (&type_str); + string_append (&arg, ")"); + if (*args != 'L') + goto cfront_template_args_done; + args++; + /* Now snarf a literal value following 'L' */ + if (!snarf_numeric_literal (&args, &arg)) + goto cfront_template_args_done; + break; + + case 'L': + /* Snarf a literal following 'L' */ + args++; + if (!snarf_numeric_literal (&args, &arg)) + goto cfront_template_args_done; + break; + default: + /* Not handling other HP cfront stuff */ + { + const char* old_args = args; + if (!do_type (work, &args, &arg)) + goto cfront_template_args_done; + + /* Fail if we didn't make any progress: prevent infinite loop. */ + if (args == old_args) + { + work->options = hold_options; + return; + } + } + } + string_appends (declp, &arg); + string_append (declp, ","); + } + cfront_template_args_done: + string_delete (&arg); + if (args >= e) + --declp->p; /* remove extra comma */ + string_append (declp, ">"); + work->options = hold_options; + } + else if (n>10 && strncmp (*mangled, "_GLOBAL_", 8) == 0 + && (*mangled)[9] == 'N' + && (*mangled)[8] == (*mangled)[10] + && strchr (cplus_markers, (*mangled)[8])) + { + /* A member of the anonymous namespace. */ + string_append (declp, "{anonymous}"); + } + else + { + if (work->temp_start == -1) /* non-recursive call only */ + work->temp_start = 0; /* disable in recursive calls */ + string_appendn (declp, *mangled, n); + } + *mangled += n; +} + +/* Extract a class name, possibly a template with arguments, from the + mangled string; qualifiers, local class indicators, etc. have + already been dealt with */ + +static int +demangle_class_name (struct work_stuff *work, const char **mangled, + string *declp) +{ + int n; + int success = 0; + + n = consume_count (mangled); + if (n == -1) + return 0; + if ((int) strlen (*mangled) >= n) + { + demangle_arm_hp_template (work, mangled, n, declp); + success = 1; + } + + return (success); +} + +/* + +LOCAL FUNCTION + + demangle_class -- demangle a mangled class sequence + +SYNOPSIS + + static int + demangle_class (struct work_stuff *work, const char **mangled, + strint *declp) + +DESCRIPTION + + DECLP points to the buffer into which demangling is being done. + + *MANGLED points to the current token to be demangled. On input, + it points to a mangled class (I.E. "3foo", "13verylongclass", etc.) + On exit, it points to the next token after the mangled class on + success, or the first unconsumed token on failure. + + If the CONSTRUCTOR or DESTRUCTOR flags are set in WORK, then + we are demangling a constructor or destructor. In this case + we prepend "class::class" or "class::~class" to DECLP. + + Otherwise, we prepend "class::" to the current DECLP. + + Reset the constructor/destructor flags once they have been + "consumed". This allows demangle_class to be called later during + the same demangling, to do normal class demangling. + + Returns 1 if demangling is successful, 0 otherwise. + +*/ + +static int +demangle_class (struct work_stuff *work, const char **mangled, string *declp) +{ + int success = 0; + int btype; + string class_name; + char *save_class_name_end = 0; + + string_init (&class_name); + btype = register_Btype (work); + if (demangle_class_name (work, mangled, &class_name)) + { + save_class_name_end = class_name.p; + if ((work->constructor & 1) || (work->destructor & 1)) + { + /* adjust so we don't include template args */ + if (work->temp_start && (work->temp_start != -1)) + { + class_name.p = class_name.b + work->temp_start; + } + string_prepends (declp, &class_name); + if (work -> destructor & 1) + { + string_prepend (declp, "~"); + work -> destructor -= 1; + } + else + { + work -> constructor -= 1; + } + } + class_name.p = save_class_name_end; + remember_Ktype (work, class_name.b, LEN_STRING(&class_name)); + remember_Btype (work, class_name.b, LEN_STRING(&class_name), btype); + string_prepend (declp, SCOPE_STRING (work)); + string_prepends (declp, &class_name); + success = 1; + } + string_delete (&class_name); + return (success); +} + + +/* Called when there's a "__" in the mangled name, with `scan' pointing to + the rightmost guess. + + Find the correct "__"-sequence where the function name ends and the + signature starts, which is ambiguous with GNU mangling. + Call demangle_signature here, so we can make sure we found the right + one; *mangled will be consumed so caller will not make further calls to + demangle_signature. */ + +static int +iterate_demangle_function (struct work_stuff *work, const char **mangled, + string *declp, const char *scan) +{ + const char *mangle_init = *mangled; + int success = 0; + string decl_init; + struct work_stuff work_init; + + if (*(scan + 2) == '\0') + return 0; + + /* Do not iterate for some demangling modes, or if there's only one + "__"-sequence. This is the normal case. */ + if (ARM_DEMANGLING || LUCID_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING + || strstr (scan + 2, "__") == NULL) + return demangle_function_name (work, mangled, declp, scan); + + /* Save state so we can restart if the guess at the correct "__" was + wrong. */ + string_init (&decl_init); + string_appends (&decl_init, declp); + memset (&work_init, 0, sizeof work_init); + work_stuff_copy_to_from (&work_init, work); + + /* Iterate over occurrences of __, allowing names and types to have a + "__" sequence in them. We must start with the first (not the last) + occurrence, since "__" most often occur between independent mangled + parts, hence starting at the last occurence inside a signature + might get us a "successful" demangling of the signature. */ + + while (scan[2]) + { + if (demangle_function_name (work, mangled, declp, scan)) + { + success = demangle_signature (work, mangled, declp); + if (success) + break; + } + + /* Reset demangle state for the next round. */ + *mangled = mangle_init; + string_clear (declp); + string_appends (declp, &decl_init); + work_stuff_copy_to_from (work, &work_init); + + /* Leave this underscore-sequence. */ + scan += 2; + + /* Scan for the next "__" sequence. */ + while (*scan && (scan[0] != '_' || scan[1] != '_')) + scan++; + + /* Move to last "__" in this sequence. */ + while (*scan && *scan == '_') + scan++; + scan -= 2; + } + + /* Delete saved state. */ + delete_work_stuff (&work_init); + string_delete (&decl_init); + + return success; +} + +/* + +LOCAL FUNCTION + + demangle_prefix -- consume the mangled name prefix and find signature + +SYNOPSIS + + static int + demangle_prefix (struct work_stuff *work, const char **mangled, + string *declp); + +DESCRIPTION + + Consume and demangle the prefix of the mangled name. + While processing the function name root, arrange to call + demangle_signature if the root is ambiguous. + + DECLP points to the string buffer into which demangled output is + placed. On entry, the buffer is empty. On exit it contains + the root function name, the demangled operator name, or in some + special cases either nothing or the completely demangled result. + + MANGLED points to the current pointer into the mangled name. As each + token of the mangled name is consumed, it is updated. Upon entry + the current mangled name pointer points to the first character of + the mangled name. Upon exit, it should point to the first character + of the signature if demangling was successful, or to the first + unconsumed character if demangling of the prefix was unsuccessful. + + Returns 1 on success, 0 otherwise. + */ + +static int +demangle_prefix (struct work_stuff *work, const char **mangled, + string *declp) +{ + int success = 1; + const char *scan; + int i; + + if (strlen(*mangled) > 6 + && (strncmp(*mangled, "_imp__", 6) == 0 + || strncmp(*mangled, "__imp_", 6) == 0)) + { + /* it's a symbol imported from a PE dynamic library. Check for both + new style prefix _imp__ and legacy __imp_ used by older versions + of dlltool. */ + (*mangled) += 6; + work->dllimported = 1; + } + else if (strlen(*mangled) >= 11 && strncmp(*mangled, "_GLOBAL_", 8) == 0) + { + char *marker = strchr (cplus_markers, (*mangled)[8]); + if (marker != NULL && *marker == (*mangled)[10]) + { + if ((*mangled)[9] == 'D') + { + /* it's a GNU global destructor to be executed at program exit */ + (*mangled) += 11; + work->destructor = 2; + if (gnu_special (work, mangled, declp)) + return success; + } + else if ((*mangled)[9] == 'I') + { + /* it's a GNU global constructor to be executed at program init */ + (*mangled) += 11; + work->constructor = 2; + if (gnu_special (work, mangled, declp)) + return success; + } + } + } + else if ((ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) && strncmp(*mangled, "__std__", 7) == 0) + { + /* it's a ARM global destructor to be executed at program exit */ + (*mangled) += 7; + work->destructor = 2; + } + else if ((ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) && strncmp(*mangled, "__sti__", 7) == 0) + { + /* it's a ARM global constructor to be executed at program initial */ + (*mangled) += 7; + work->constructor = 2; + } + + /* This block of code is a reduction in strength time optimization + of: + scan = strstr (*mangled, "__"); */ + + { + scan = *mangled; + + do { + scan = strchr (scan, '_'); + } while (scan != NULL && *++scan != '_'); + + if (scan != NULL) --scan; + } + + if (scan != NULL) + { + /* We found a sequence of two or more '_', ensure that we start at + the last pair in the sequence. */ + i = strspn (scan, "_"); + if (i > 2) + { + scan += (i - 2); + } + } + + if (scan == NULL) + { + success = 0; + } + else if (work -> static_type) + { + if (!ISDIGIT ((unsigned char)scan[0]) && (scan[0] != 't')) + { + success = 0; + } + } + else if ((scan == *mangled) + && (ISDIGIT ((unsigned char)scan[2]) || (scan[2] == 'Q') + || (scan[2] == 't') || (scan[2] == 'K') || (scan[2] == 'H'))) + { + /* The ARM says nothing about the mangling of local variables. + But cfront mangles local variables by prepending __ + to them. As an extension to ARM demangling we handle this case. */ + if ((LUCID_DEMANGLING || ARM_DEMANGLING || HP_DEMANGLING) + && ISDIGIT ((unsigned char)scan[2])) + { + *mangled = scan + 2; + consume_count (mangled); + string_append (declp, *mangled); + *mangled += strlen (*mangled); + success = 1; + } + else + { + /* A GNU style constructor starts with __[0-9Qt]. But cfront uses + names like __Q2_3foo3bar for nested type names. So don't accept + this style of constructor for cfront demangling. A GNU + style member-template constructor starts with 'H'. */ + if (!(LUCID_DEMANGLING || ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING)) + work -> constructor += 1; + *mangled = scan + 2; + } + } + else if (ARM_DEMANGLING && scan[2] == 'p' && scan[3] == 't') + { + /* Cfront-style parameterized type. Handled later as a signature. */ + success = 1; + + /* ARM template? */ + demangle_arm_hp_template (work, mangled, strlen (*mangled), declp); + } + else if (EDG_DEMANGLING && ((scan[2] == 't' && scan[3] == 'm') + || (scan[2] == 'p' && scan[3] == 's') + || (scan[2] == 'p' && scan[3] == 't'))) + { + /* EDG-style parameterized type. Handled later as a signature. */ + success = 1; + + /* EDG template? */ + demangle_arm_hp_template (work, mangled, strlen (*mangled), declp); + } + else if ((scan == *mangled) && !ISDIGIT ((unsigned char)scan[2]) + && (scan[2] != 't')) + { + /* Mangled name starts with "__". Skip over any leading '_' characters, + then find the next "__" that separates the prefix from the signature. + */ + if (!(ARM_DEMANGLING || LUCID_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) + || (arm_special (mangled, declp) == 0)) + { + while (*scan == '_') + { + scan++; + } + if ((scan = strstr (scan, "__")) == NULL || (*(scan + 2) == '\0')) + { + /* No separator (I.E. "__not_mangled"), or empty signature + (I.E. "__not_mangled_either__") */ + success = 0; + } + else + return iterate_demangle_function (work, mangled, declp, scan); + } + } + else if (*(scan + 2) != '\0') + { + /* Mangled name does not start with "__" but does have one somewhere + in there with non empty stuff after it. Looks like a global + function name. Iterate over all "__":s until the right + one is found. */ + return iterate_demangle_function (work, mangled, declp, scan); + } + else + { + /* Doesn't look like a mangled name */ + success = 0; + } + + if (!success && (work->constructor == 2 || work->destructor == 2)) + { + string_append (declp, *mangled); + *mangled += strlen (*mangled); + success = 1; + } + return (success); +} + +/* + +LOCAL FUNCTION + + gnu_special -- special handling of gnu mangled strings + +SYNOPSIS + + static int + gnu_special (struct work_stuff *work, const char **mangled, + string *declp); + + +DESCRIPTION + + Process some special GNU style mangling forms that don't fit + the normal pattern. For example: + + _$_3foo (destructor for class foo) + _vt$foo (foo virtual table) + _vt$foo$bar (foo::bar virtual table) + __vt_foo (foo virtual table, new style with thunks) + _3foo$varname (static data member) + _Q22rs2tu$vw (static data member) + __t6vector1Zii (constructor with template) + __thunk_4__$_7ostream (virtual function thunk) + */ + +static int +gnu_special (struct work_stuff *work, const char **mangled, string *declp) +{ + int n; + int success = 1; + const char *p; + + if ((*mangled)[0] == '_' + && strchr (cplus_markers, (*mangled)[1]) != NULL + && (*mangled)[2] == '_') + { + /* Found a GNU style destructor, get past "__" */ + (*mangled) += 3; + work -> destructor += 1; + } + else if ((*mangled)[0] == '_' + && (((*mangled)[1] == '_' + && (*mangled)[2] == 'v' + && (*mangled)[3] == 't' + && (*mangled)[4] == '_') + || ((*mangled)[1] == 'v' + && (*mangled)[2] == 't' + && strchr (cplus_markers, (*mangled)[3]) != NULL))) + { + /* Found a GNU style virtual table, get past "_vt" + and create the decl. Note that we consume the entire mangled + input string, which means that demangle_signature has no work + to do. */ + if ((*mangled)[2] == 'v') + (*mangled) += 5; /* New style, with thunks: "__vt_" */ + else + (*mangled) += 4; /* Old style, no thunks: "_vt" */ + while (**mangled != '\0') + { + switch (**mangled) + { + case 'Q': + case 'K': + success = demangle_qualified (work, mangled, declp, 0, 1); + break; + case 't': + success = demangle_template (work, mangled, declp, 0, 1, + 1); + break; + default: + if (ISDIGIT((unsigned char)*mangled[0])) + { + n = consume_count(mangled); + /* We may be seeing a too-large size, or else a + "." indicating a static local symbol. In + any case, declare victory and move on; *don't* try + to use n to allocate. */ + if (n > (int) strlen (*mangled)) + { + success = 1; + break; + } + } + else + { + n = strcspn (*mangled, cplus_markers); + } + string_appendn (declp, *mangled, n); + (*mangled) += n; + } + + p = strpbrk (*mangled, cplus_markers); + if (success && ((p == NULL) || (p == *mangled))) + { + if (p != NULL) + { + string_append (declp, SCOPE_STRING (work)); + (*mangled)++; + } + } + else + { + success = 0; + break; + } + } + if (success) + string_append (declp, " virtual table"); + } + else if ((*mangled)[0] == '_' + && (strchr("0123456789Qt", (*mangled)[1]) != NULL) + && (p = strpbrk (*mangled, cplus_markers)) != NULL) + { + /* static data member, "_3foo$varname" for example */ + (*mangled)++; + switch (**mangled) + { + case 'Q': + case 'K': + success = demangle_qualified (work, mangled, declp, 0, 1); + break; + case 't': + success = demangle_template (work, mangled, declp, 0, 1, 1); + break; + default: + n = consume_count (mangled); + if (n < 0 || n > (long) strlen (*mangled)) + { + success = 0; + break; + } + + if (n > 10 && strncmp (*mangled, "_GLOBAL_", 8) == 0 + && (*mangled)[9] == 'N' + && (*mangled)[8] == (*mangled)[10] + && strchr (cplus_markers, (*mangled)[8])) + { + /* A member of the anonymous namespace. There's information + about what identifier or filename it was keyed to, but + it's just there to make the mangled name unique; we just + step over it. */ + string_append (declp, "{anonymous}"); + (*mangled) += n; + + /* Now p points to the marker before the N, so we need to + update it to the first marker after what we consumed. */ + p = strpbrk (*mangled, cplus_markers); + break; + } + + string_appendn (declp, *mangled, n); + (*mangled) += n; + } + if (success && (p == *mangled)) + { + /* Consumed everything up to the cplus_marker, append the + variable name. */ + (*mangled)++; + string_append (declp, SCOPE_STRING (work)); + n = strlen (*mangled); + string_appendn (declp, *mangled, n); + (*mangled) += n; + } + else + { + success = 0; + } + } + else if (strncmp (*mangled, "__thunk_", 8) == 0) + { + int delta; + + (*mangled) += 8; + delta = consume_count (mangled); + if (delta == -1) + success = 0; + else + { + char *method = internal_cplus_demangle (work, ++*mangled); + + if (method) + { + char buf[50]; + sprintf (buf, "virtual function thunk (delta:%d) for ", -delta); + string_append (declp, buf); + string_append (declp, method); + free (method); + n = strlen (*mangled); + (*mangled) += n; + } + else + { + success = 0; + } + } + } + else if (strncmp (*mangled, "__t", 3) == 0 + && ((*mangled)[3] == 'i' || (*mangled)[3] == 'f')) + { + p = (*mangled)[3] == 'i' ? " type_info node" : " type_info function"; + (*mangled) += 4; + switch (**mangled) + { + case 'Q': + case 'K': + success = demangle_qualified (work, mangled, declp, 0, 1); + break; + case 't': + success = demangle_template (work, mangled, declp, 0, 1, 1); + break; + default: + success = do_type (work, mangled, declp); + break; + } + if (success && **mangled != '\0') + success = 0; + if (success) + string_append (declp, p); + } + else + { + success = 0; + } + return (success); +} + +static void +recursively_demangle(struct work_stuff *work, const char **mangled, + string *result, int namelength) +{ + char * recurse = (char *)NULL; + char * recurse_dem = (char *)NULL; + + recurse = XNEWVEC (char, namelength + 1); + memcpy (recurse, *mangled, namelength); + recurse[namelength] = '\000'; + + recurse_dem = cplus_demangle (recurse, work->options); + + if (recurse_dem) + { + string_append (result, recurse_dem); + free (recurse_dem); + } + else + { + string_appendn (result, *mangled, namelength); + } + free (recurse); + *mangled += namelength; +} + +/* + +LOCAL FUNCTION + + arm_special -- special handling of ARM/lucid mangled strings + +SYNOPSIS + + static int + arm_special (const char **mangled, + string *declp); + + +DESCRIPTION + + Process some special ARM style mangling forms that don't fit + the normal pattern. For example: + + __vtbl__3foo (foo virtual table) + __vtbl__3foo__3bar (bar::foo virtual table) + + */ + +static int +arm_special (const char **mangled, string *declp) +{ + int n; + int success = 1; + const char *scan; + + if (strncmp (*mangled, ARM_VTABLE_STRING, ARM_VTABLE_STRLEN) == 0) + { + /* Found a ARM style virtual table, get past ARM_VTABLE_STRING + and create the decl. Note that we consume the entire mangled + input string, which means that demangle_signature has no work + to do. */ + scan = *mangled + ARM_VTABLE_STRLEN; + while (*scan != '\0') /* first check it can be demangled */ + { + n = consume_count (&scan); + if (n == -1) + { + return (0); /* no good */ + } + scan += n; + if (scan[0] == '_' && scan[1] == '_') + { + scan += 2; + } + } + (*mangled) += ARM_VTABLE_STRLEN; + while (**mangled != '\0') + { + n = consume_count (mangled); + if (n == -1 + || n > (long) strlen (*mangled)) + return 0; + string_prependn (declp, *mangled, n); + (*mangled) += n; + if ((*mangled)[0] == '_' && (*mangled)[1] == '_') + { + string_prepend (declp, "::"); + (*mangled) += 2; + } + } + string_append (declp, " virtual table"); + } + else + { + success = 0; + } + return (success); +} + +/* + +LOCAL FUNCTION + + demangle_qualified -- demangle 'Q' qualified name strings + +SYNOPSIS + + static int + demangle_qualified (struct work_stuff *, const char *mangled, + string *result, int isfuncname, int append); + +DESCRIPTION + + Demangle a qualified name, such as "Q25Outer5Inner" which is + the mangled form of "Outer::Inner". The demangled output is + prepended or appended to the result string according to the + state of the append flag. + + If isfuncname is nonzero, then the qualified name we are building + is going to be used as a member function name, so if it is a + constructor or destructor function, append an appropriate + constructor or destructor name. I.E. for the above example, + the result for use as a constructor is "Outer::Inner::Inner" + and the result for use as a destructor is "Outer::Inner::~Inner". + +BUGS + + Numeric conversion is ASCII dependent (FIXME). + + */ + +static int +demangle_qualified (struct work_stuff *work, const char **mangled, + string *result, int isfuncname, int append) +{ + int qualifiers = 0; + int success = 1; + char num[2]; + string temp; + string last_name; + int bindex = register_Btype (work); + + /* We only make use of ISFUNCNAME if the entity is a constructor or + destructor. */ + isfuncname = (isfuncname + && ((work->constructor & 1) || (work->destructor & 1))); + + string_init (&temp); + string_init (&last_name); + + if ((*mangled)[0] == 'K') + { + /* Squangling qualified name reuse */ + int idx; + (*mangled)++; + idx = consume_count_with_underscores (mangled); + if (idx == -1 || idx >= work -> numk) + success = 0; + else + string_append (&temp, work -> ktypevec[idx]); + } + else + switch ((*mangled)[1]) + { + case '_': + /* GNU mangled name with more than 9 classes. The count is preceded + by an underscore (to distinguish it from the <= 9 case) and followed + by an underscore. */ + (*mangled)++; + qualifiers = consume_count_with_underscores (mangled); + if (qualifiers == -1) + success = 0; + break; + + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + /* The count is in a single digit. */ + num[0] = (*mangled)[1]; + num[1] = '\0'; + qualifiers = atoi (num); + + /* If there is an underscore after the digit, skip it. This is + said to be for ARM-qualified names, but the ARM makes no + mention of such an underscore. Perhaps cfront uses one. */ + if ((*mangled)[2] == '_') + { + (*mangled)++; + } + (*mangled) += 2; + break; + + case '0': + default: + success = 0; + } + + if (!success) + return success; + + /* Pick off the names and collect them in the temp buffer in the order + in which they are found, separated by '::'. */ + + while (qualifiers-- > 0) + { + int remember_K = 1; + string_clear (&last_name); + + if (*mangled[0] == '_') + (*mangled)++; + + if (*mangled[0] == 't') + { + /* Here we always append to TEMP since we will want to use + the template name without the template parameters as a + constructor or destructor name. The appropriate + (parameter-less) value is returned by demangle_template + in LAST_NAME. We do not remember the template type here, + in order to match the G++ mangling algorithm. */ + success = demangle_template(work, mangled, &temp, + &last_name, 1, 0); + if (!success) + break; + } + else if (*mangled[0] == 'K') + { + int idx; + (*mangled)++; + idx = consume_count_with_underscores (mangled); + if (idx == -1 || idx >= work->numk) + success = 0; + else + string_append (&temp, work->ktypevec[idx]); + remember_K = 0; + + if (!success) break; + } + else + { + if (EDG_DEMANGLING) + { + int namelength; + /* Now recursively demangle the qualifier + * This is necessary to deal with templates in + * mangling styles like EDG */ + namelength = consume_count (mangled); + if (namelength == -1) + { + success = 0; + break; + } + recursively_demangle(work, mangled, &temp, namelength); + } + else + { + string_delete (&last_name); + success = do_type (work, mangled, &last_name); + if (!success) + break; + string_appends (&temp, &last_name); + } + } + + if (remember_K) + remember_Ktype (work, temp.b, LEN_STRING (&temp)); + + if (qualifiers > 0) + string_append (&temp, SCOPE_STRING (work)); + } + + remember_Btype (work, temp.b, LEN_STRING (&temp), bindex); + + /* If we are using the result as a function name, we need to append + the appropriate '::' separated constructor or destructor name. + We do this here because this is the most convenient place, where + we already have a pointer to the name and the length of the name. */ + + if (isfuncname) + { + string_append (&temp, SCOPE_STRING (work)); + if (work -> destructor & 1) + string_append (&temp, "~"); + string_appends (&temp, &last_name); + } + + /* Now either prepend the temp buffer to the result, or append it, + depending upon the state of the append flag. */ + + if (append) + string_appends (result, &temp); + else + { + if (!STRING_EMPTY (result)) + string_append (&temp, SCOPE_STRING (work)); + string_prepends (result, &temp); + } + + string_delete (&last_name); + string_delete (&temp); + return (success); +} + +/* + +LOCAL FUNCTION + + get_count -- convert an ascii count to integer, consuming tokens + +SYNOPSIS + + static int + get_count (const char **type, int *count) + +DESCRIPTION + + Assume that *type points at a count in a mangled name; set + *count to its value, and set *type to the next character after + the count. There are some weird rules in effect here. + + If *type does not point at a string of digits, return zero. + + If *type points at a string of digits followed by an + underscore, set *count to their value as an integer, advance + *type to point *after the underscore, and return 1. + + If *type points at a string of digits not followed by an + underscore, consume only the first digit. Set *count to its + value as an integer, leave *type pointing after that digit, + and return 1. + + The excuse for this odd behavior: in the ARM and HP demangling + styles, a type can be followed by a repeat count of the form + `Nxy', where: + + `x' is a single digit specifying how many additional copies + of the type to append to the argument list, and + + `y' is one or more digits, specifying the zero-based index of + the first repeated argument in the list. Yes, as you're + unmangling the name you can figure this out yourself, but + it's there anyway. + + So, for example, in `bar__3fooFPiN51', the first argument is a + pointer to an integer (`Pi'), and then the next five arguments + are the same (`N5'), and the first repeat is the function's + second argument (`1'). +*/ + +static int +get_count (const char **type, int *count) +{ + const char *p; + int n; + + if (!ISDIGIT ((unsigned char)**type)) + return (0); + else + { + *count = **type - '0'; + (*type)++; + if (ISDIGIT ((unsigned char)**type)) + { + p = *type; + n = *count; + do + { + n *= 10; + n += *p - '0'; + p++; + } + while (ISDIGIT ((unsigned char)*p)); + if (*p == '_') + { + *type = p + 1; + *count = n; + } + } + } + return (1); +} + +/* RESULT will be initialised here; it will be freed on failure. The + value returned is really a type_kind_t. */ + +static int +do_type (struct work_stuff *work, const char **mangled, string *result) +{ + int n; + int done; + int success; + string decl; + const char *remembered_type; + int type_quals; + type_kind_t tk = tk_none; + + string_init (&decl); + string_init (result); + + done = 0; + success = 1; + while (success && !done) + { + int member; + switch (**mangled) + { + + /* A pointer type */ + case 'P': + case 'p': + (*mangled)++; + if (! (work -> options & DMGL_JAVA)) + string_prepend (&decl, "*"); + if (tk == tk_none) + tk = tk_pointer; + break; + + /* A reference type */ + case 'R': + (*mangled)++; + string_prepend (&decl, "&"); + if (tk == tk_none) + tk = tk_reference; + break; + + /* An array */ + case 'A': + { + ++(*mangled); + if (!STRING_EMPTY (&decl) + && (decl.b[0] == '*' || decl.b[0] == '&')) + { + string_prepend (&decl, "("); + string_append (&decl, ")"); + } + string_append (&decl, "["); + if (**mangled != '_') + success = demangle_template_value_parm (work, mangled, &decl, + tk_integral); + if (**mangled == '_') + ++(*mangled); + string_append (&decl, "]"); + break; + } + + /* A back reference to a previously seen type */ + case 'T': + (*mangled)++; + if (!get_count (mangled, &n) || n >= work -> ntypes) + { + success = 0; + } + else + { + remembered_type = work -> typevec[n]; + mangled = &remembered_type; + } + break; + + /* A function */ + case 'F': + (*mangled)++; + if (!STRING_EMPTY (&decl) + && (decl.b[0] == '*' || decl.b[0] == '&')) + { + string_prepend (&decl, "("); + string_append (&decl, ")"); + } + /* After picking off the function args, we expect to either find the + function return type (preceded by an '_') or the end of the + string. */ + if (!demangle_nested_args (work, mangled, &decl) + || (**mangled != '_' && **mangled != '\0')) + { + success = 0; + break; + } + if (success && (**mangled == '_')) + (*mangled)++; + break; + + case 'M': + case 'O': + { + type_quals = TYPE_UNQUALIFIED; + + member = **mangled == 'M'; + (*mangled)++; + + string_append (&decl, ")"); + + /* We don't need to prepend `::' for a qualified name; + demangle_qualified will do that for us. */ + if (**mangled != 'Q') + string_prepend (&decl, SCOPE_STRING (work)); + + if (ISDIGIT ((unsigned char)**mangled)) + { + n = consume_count (mangled); + if (n == -1 + || (int) strlen (*mangled) < n) + { + success = 0; + break; + } + string_prependn (&decl, *mangled, n); + *mangled += n; + } + else if (**mangled == 'X' || **mangled == 'Y') + { + string temp; + do_type (work, mangled, &temp); + string_prepends (&decl, &temp); + string_delete (&temp); + } + else if (**mangled == 't') + { + string temp; + string_init (&temp); + success = demangle_template (work, mangled, &temp, + NULL, 1, 1); + if (success) + { + string_prependn (&decl, temp.b, temp.p - temp.b); + string_delete (&temp); + } + else + break; + } + else if (**mangled == 'Q') + { + success = demangle_qualified (work, mangled, &decl, + /*isfuncnam=*/0, + /*append=*/0); + if (!success) + break; + } + else + { + success = 0; + break; + } + + string_prepend (&decl, "("); + if (member) + { + switch (**mangled) + { + case 'C': + case 'V': + case 'u': + type_quals |= code_for_qualifier (**mangled); + (*mangled)++; + break; + + default: + break; + } + + if (*(*mangled)++ != 'F') + { + success = 0; + break; + } + } + if ((member && !demangle_nested_args (work, mangled, &decl)) + || **mangled != '_') + { + success = 0; + break; + } + (*mangled)++; + if (! PRINT_ANSI_QUALIFIERS) + { + break; + } + if (type_quals != TYPE_UNQUALIFIED) + { + APPEND_BLANK (&decl); + string_append (&decl, qualifier_string (type_quals)); + } + break; + } + case 'G': + (*mangled)++; + break; + + case 'C': + case 'V': + case 'u': + if (PRINT_ANSI_QUALIFIERS) + { + if (!STRING_EMPTY (&decl)) + string_prepend (&decl, " "); + + string_prepend (&decl, demangle_qualifier (**mangled)); + } + (*mangled)++; + break; + /* + } + */ + + /* fall through */ + default: + done = 1; + break; + } + } + + if (success) switch (**mangled) + { + /* A qualified name, such as "Outer::Inner". */ + case 'Q': + case 'K': + { + success = demangle_qualified (work, mangled, result, 0, 1); + break; + } + + /* A back reference to a previously seen squangled type */ + case 'B': + (*mangled)++; + if (!get_count (mangled, &n) || n >= work -> numb) + success = 0; + else + string_append (result, work->btypevec[n]); + break; + + case 'X': + case 'Y': + /* A template parm. We substitute the corresponding argument. */ + { + int idx; + + (*mangled)++; + idx = consume_count_with_underscores (mangled); + + if (idx == -1 + || (work->tmpl_argvec && idx >= work->ntmpl_args) + || consume_count_with_underscores (mangled) == -1) + { + success = 0; + break; + } + + if (work->tmpl_argvec) + string_append (result, work->tmpl_argvec[idx]); + else + string_append_template_idx (result, idx); + + success = 1; + } + break; + + default: + success = demangle_fund_type (work, mangled, result); + if (tk == tk_none) + tk = (type_kind_t) success; + break; + } + + if (success) + { + if (!STRING_EMPTY (&decl)) + { + string_append (result, " "); + string_appends (result, &decl); + } + } + else + string_delete (result); + string_delete (&decl); + + if (success) + /* Assume an integral type, if we're not sure. */ + return (int) ((tk == tk_none) ? tk_integral : tk); + else + return 0; +} + +/* Given a pointer to a type string that represents a fundamental type + argument (int, long, unsigned int, etc) in TYPE, a pointer to the + string in which the demangled output is being built in RESULT, and + the WORK structure, decode the types and add them to the result. + + For example: + + "Ci" => "const int" + "Sl" => "signed long" + "CUs" => "const unsigned short" + + The value returned is really a type_kind_t. */ + +static int +demangle_fund_type (struct work_stuff *work, + const char **mangled, string *result) +{ + int done = 0; + int success = 1; + char buf[INTBUF_SIZE + 5 /* 'int%u_t' */]; + unsigned int dec = 0; + type_kind_t tk = tk_integral; + + /* First pick off any type qualifiers. There can be more than one. */ + + while (!done) + { + switch (**mangled) + { + case 'C': + case 'V': + case 'u': + if (PRINT_ANSI_QUALIFIERS) + { + if (!STRING_EMPTY (result)) + string_prepend (result, " "); + string_prepend (result, demangle_qualifier (**mangled)); + } + (*mangled)++; + break; + case 'U': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "unsigned"); + break; + case 'S': /* signed char only */ + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "signed"); + break; + case 'J': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "__complex"); + break; + default: + done = 1; + break; + } + } + + /* Now pick off the fundamental type. There can be only one. */ + + switch (**mangled) + { + case '\0': + case '_': + break; + case 'v': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "void"); + break; + case 'x': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "long long"); + break; + case 'l': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "long"); + break; + case 'i': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "int"); + break; + case 's': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "short"); + break; + case 'b': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "bool"); + tk = tk_bool; + break; + case 'c': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "char"); + tk = tk_char; + break; + case 'w': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "wchar_t"); + tk = tk_char; + break; + case 'r': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "long double"); + tk = tk_real; + break; + case 'd': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "double"); + tk = tk_real; + break; + case 'f': + (*mangled)++; + APPEND_BLANK (result); + string_append (result, "float"); + tk = tk_real; + break; + case 'G': + (*mangled)++; + if (!ISDIGIT ((unsigned char)**mangled)) + { + success = 0; + break; + } + case 'I': + (*mangled)++; + if (**mangled == '_') + { + int i; + (*mangled)++; + for (i = 0; + i < (long) sizeof (buf) - 1 && **mangled && **mangled != '_'; + (*mangled)++, i++) + buf[i] = **mangled; + if (**mangled != '_') + { + success = 0; + break; + } + buf[i] = '\0'; + (*mangled)++; + } + else + { + strncpy (buf, *mangled, 2); + buf[2] = '\0'; + *mangled += min (strlen (*mangled), 2); + } + sscanf (buf, "%x", &dec); + sprintf (buf, "int%u_t", dec); + APPEND_BLANK (result); + string_append (result, buf); + break; + + /* fall through */ + /* An explicit type, such as "6mytype" or "7integer" */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bindex = register_Btype (work); + string btype; + string_init (&btype); + if (demangle_class_name (work, mangled, &btype)) { + remember_Btype (work, btype.b, LEN_STRING (&btype), bindex); + APPEND_BLANK (result); + string_appends (result, &btype); + } + else + success = 0; + string_delete (&btype); + break; + } + case 't': + { + string btype; + string_init (&btype); + success = demangle_template (work, mangled, &btype, 0, 1, 1); + string_appends (result, &btype); + string_delete (&btype); + break; + } + default: + success = 0; + break; + } + + return success ? ((int) tk) : 0; +} + + +/* Handle a template's value parameter for HP aCC (extension from ARM) + **mangled points to 'S' or 'U' */ + +static int +do_hpacc_template_const_value (struct work_stuff *work ATTRIBUTE_UNUSED, + const char **mangled, string *result) +{ + int unsigned_const; + + if (**mangled != 'U' && **mangled != 'S') + return 0; + + unsigned_const = (**mangled == 'U'); + + (*mangled)++; + + switch (**mangled) + { + case 'N': + string_append (result, "-"); + /* fall through */ + case 'P': + (*mangled)++; + break; + case 'M': + /* special case for -2^31 */ + string_append (result, "-2147483648"); + (*mangled)++; + return 1; + default: + return 0; + } + + /* We have to be looking at an integer now */ + if (!(ISDIGIT ((unsigned char)**mangled))) + return 0; + + /* We only deal with integral values for template + parameters -- so it's OK to look only for digits */ + while (ISDIGIT ((unsigned char)**mangled)) + { + char_str[0] = **mangled; + string_append (result, char_str); + (*mangled)++; + } + + if (unsigned_const) + string_append (result, "U"); + + /* FIXME? Some day we may have 64-bit (or larger :-) ) constants + with L or LL suffixes. pai/1997-09-03 */ + + return 1; /* success */ +} + +/* Handle a template's literal parameter for HP aCC (extension from ARM) + **mangled is pointing to the 'A' */ + +static int +do_hpacc_template_literal (struct work_stuff *work, const char **mangled, + string *result) +{ + int literal_len = 0; + char * recurse; + char * recurse_dem; + + if (**mangled != 'A') + return 0; + + (*mangled)++; + + literal_len = consume_count (mangled); + + if (literal_len <= 0) + return 0; + + /* Literal parameters are names of arrays, functions, etc. and the + canonical representation uses the address operator */ + string_append (result, "&"); + + /* Now recursively demangle the literal name */ + recurse = XNEWVEC (char, literal_len + 1); + memcpy (recurse, *mangled, literal_len); + recurse[literal_len] = '\000'; + + recurse_dem = cplus_demangle (recurse, work->options); + + if (recurse_dem) + { + string_append (result, recurse_dem); + free (recurse_dem); + } + else + { + string_appendn (result, *mangled, literal_len); + } + (*mangled) += literal_len; + free (recurse); + + return 1; +} + +static int +snarf_numeric_literal (const char **args, string *arg) +{ + if (**args == '-') + { + char_str[0] = '-'; + string_append (arg, char_str); + (*args)++; + } + else if (**args == '+') + (*args)++; + + if (!ISDIGIT ((unsigned char)**args)) + return 0; + + while (ISDIGIT ((unsigned char)**args)) + { + char_str[0] = **args; + string_append (arg, char_str); + (*args)++; + } + + return 1; +} + +/* Demangle the next argument, given by MANGLED into RESULT, which + *should be an uninitialized* string. It will be initialized here, + and free'd should anything go wrong. */ + +static int +do_arg (struct work_stuff *work, const char **mangled, string *result) +{ + /* Remember where we started so that we can record the type, for + non-squangling type remembering. */ + const char *start = *mangled; + + string_init (result); + + if (work->nrepeats > 0) + { + --work->nrepeats; + + if (work->previous_argument == 0) + return 0; + + /* We want to reissue the previous type in this argument list. */ + string_appends (result, work->previous_argument); + return 1; + } + + if (**mangled == 'n') + { + /* A squangling-style repeat. */ + (*mangled)++; + work->nrepeats = consume_count(mangled); + + if (work->nrepeats <= 0) + /* This was not a repeat count after all. */ + return 0; + + if (work->nrepeats > 9) + { + if (**mangled != '_') + /* The repeat count should be followed by an '_' in this + case. */ + return 0; + else + (*mangled)++; + } + + /* Now, the repeat is all set up. */ + return do_arg (work, mangled, result); + } + + /* Save the result in WORK->previous_argument so that we can find it + if it's repeated. Note that saving START is not good enough: we + do not want to add additional types to the back-referenceable + type vector when processing a repeated type. */ + if (work->previous_argument) + string_delete (work->previous_argument); + else + work->previous_argument = XNEW (string); + + if (!do_type (work, mangled, work->previous_argument)) + return 0; + + string_appends (result, work->previous_argument); + + remember_type (work, start, *mangled - start); + return 1; +} + +static void +remember_type (struct work_stuff *work, const char *start, int len) +{ + char *tem; + + if (work->forgetting_types) + return; + + if (work -> ntypes >= work -> typevec_size) + { + if (work -> typevec_size == 0) + { + work -> typevec_size = 3; + work -> typevec = XNEWVEC (char *, work->typevec_size); + } + else + { + work -> typevec_size *= 2; + work -> typevec + = XRESIZEVEC (char *, work->typevec, work->typevec_size); + } + } + tem = XNEWVEC (char, len + 1); + memcpy (tem, start, len); + tem[len] = '\0'; + work -> typevec[work -> ntypes++] = tem; +} + + +/* Remember a K type class qualifier. */ +static void +remember_Ktype (struct work_stuff *work, const char *start, int len) +{ + char *tem; + + if (work -> numk >= work -> ksize) + { + if (work -> ksize == 0) + { + work -> ksize = 5; + work -> ktypevec = XNEWVEC (char *, work->ksize); + } + else + { + work -> ksize *= 2; + work -> ktypevec + = XRESIZEVEC (char *, work->ktypevec, work->ksize); + } + } + tem = XNEWVEC (char, len + 1); + memcpy (tem, start, len); + tem[len] = '\0'; + work -> ktypevec[work -> numk++] = tem; +} + +/* Register a B code, and get an index for it. B codes are registered + as they are seen, rather than as they are completed, so map > + registers map > as B0, and temp as B1 */ + +static int +register_Btype (struct work_stuff *work) +{ + int ret; + + if (work -> numb >= work -> bsize) + { + if (work -> bsize == 0) + { + work -> bsize = 5; + work -> btypevec = XNEWVEC (char *, work->bsize); + } + else + { + work -> bsize *= 2; + work -> btypevec + = XRESIZEVEC (char *, work->btypevec, work->bsize); + } + } + ret = work -> numb++; + work -> btypevec[ret] = NULL; + return(ret); +} + +/* Store a value into a previously registered B code type. */ + +static void +remember_Btype (struct work_stuff *work, const char *start, + int len, int index) +{ + char *tem; + + tem = XNEWVEC (char, len + 1); + memcpy (tem, start, len); + tem[len] = '\0'; + work -> btypevec[index] = tem; +} + +/* Lose all the info related to B and K type codes. */ +static void +forget_B_and_K_types (struct work_stuff *work) +{ + int i; + + while (work -> numk > 0) + { + i = --(work -> numk); + if (work -> ktypevec[i] != NULL) + { + free (work -> ktypevec[i]); + work -> ktypevec[i] = NULL; + } + } + + while (work -> numb > 0) + { + i = --(work -> numb); + if (work -> btypevec[i] != NULL) + { + free (work -> btypevec[i]); + work -> btypevec[i] = NULL; + } + } +} +/* Forget the remembered types, but not the type vector itself. */ + +static void +forget_types (struct work_stuff *work) +{ + int i; + + while (work -> ntypes > 0) + { + i = --(work -> ntypes); + if (work -> typevec[i] != NULL) + { + free (work -> typevec[i]); + work -> typevec[i] = NULL; + } + } +} + +/* Process the argument list part of the signature, after any class spec + has been consumed, as well as the first 'F' character (if any). For + example: + + "__als__3fooRT0" => process "RT0" + "complexfunc5__FPFPc_PFl_i" => process "PFPc_PFl_i" + + DECLP must be already initialised, usually non-empty. It won't be freed + on failure. + + Note that g++ differs significantly from ARM and lucid style mangling + with regards to references to previously seen types. For example, given + the source fragment: + + class foo { + public: + foo::foo (int, foo &ia, int, foo &ib, int, foo &ic); + }; + + foo::foo (int, foo &ia, int, foo &ib, int, foo &ic) { ia = ib = ic; } + void foo (int, foo &ia, int, foo &ib, int, foo &ic) { ia = ib = ic; } + + g++ produces the names: + + __3fooiRT0iT2iT2 + foo__FiR3fooiT1iT1 + + while lcc (and presumably other ARM style compilers as well) produces: + + foo__FiR3fooT1T2T1T2 + __ct__3fooFiR3fooT1T2T1T2 + + Note that g++ bases its type numbers starting at zero and counts all + previously seen types, while lucid/ARM bases its type numbers starting + at one and only considers types after it has seen the 'F' character + indicating the start of the function args. For lucid/ARM style, we + account for this difference by discarding any previously seen types when + we see the 'F' character, and subtracting one from the type number + reference. + + */ + +static int +demangle_args (struct work_stuff *work, const char **mangled, + string *declp) +{ + string arg; + int need_comma = 0; + int r; + int t; + const char *tem; + char temptype; + + if (PRINT_ARG_TYPES) + { + string_append (declp, "("); + if (**mangled == '\0') + { + string_append (declp, "void"); + } + } + + while ((**mangled != '_' && **mangled != '\0' && **mangled != 'e') + || work->nrepeats > 0) + { + if ((**mangled == 'N') || (**mangled == 'T')) + { + temptype = *(*mangled)++; + + if (temptype == 'N') + { + if (!get_count (mangled, &r)) + { + return (0); + } + } + else + { + r = 1; + } + if ((HP_DEMANGLING || ARM_DEMANGLING || EDG_DEMANGLING) && work -> ntypes >= 10) + { + /* If we have 10 or more types we might have more than a 1 digit + index so we'll have to consume the whole count here. This + will lose if the next thing is a type name preceded by a + count but it's impossible to demangle that case properly + anyway. Eg if we already have 12 types is T12Pc "(..., type1, + Pc, ...)" or "(..., type12, char *, ...)" */ + if ((t = consume_count(mangled)) <= 0) + { + return (0); + } + } + else + { + if (!get_count (mangled, &t)) + { + return (0); + } + } + if (LUCID_DEMANGLING || ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) + { + t--; + } + /* Validate the type index. Protect against illegal indices from + malformed type strings. */ + if ((t < 0) || (t >= work -> ntypes)) + { + return (0); + } + while (work->nrepeats > 0 || --r >= 0) + { + tem = work -> typevec[t]; + if (need_comma && PRINT_ARG_TYPES) + { + string_append (declp, ", "); + } + if (!do_arg (work, &tem, &arg)) + { + return (0); + } + if (PRINT_ARG_TYPES) + { + string_appends (declp, &arg); + } + string_delete (&arg); + need_comma = 1; + } + } + else + { + if (need_comma && PRINT_ARG_TYPES) + string_append (declp, ", "); + if (!do_arg (work, mangled, &arg)) + return (0); + if (PRINT_ARG_TYPES) + string_appends (declp, &arg); + string_delete (&arg); + need_comma = 1; + } + } + + if (**mangled == 'e') + { + (*mangled)++; + if (PRINT_ARG_TYPES) + { + if (need_comma) + { + string_append (declp, ","); + } + string_append (declp, "..."); + } + } + + if (PRINT_ARG_TYPES) + { + string_append (declp, ")"); + } + return (1); +} + +/* Like demangle_args, but for demangling the argument lists of function + and method pointers or references, not top-level declarations. */ + +static int +demangle_nested_args (struct work_stuff *work, const char **mangled, + string *declp) +{ + string* saved_previous_argument; + int result; + int saved_nrepeats; + + /* The G++ name-mangling algorithm does not remember types on nested + argument lists, unless -fsquangling is used, and in that case the + type vector updated by remember_type is not used. So, we turn + off remembering of types here. */ + ++work->forgetting_types; + + /* For the repeat codes used with -fsquangling, we must keep track of + the last argument. */ + saved_previous_argument = work->previous_argument; + saved_nrepeats = work->nrepeats; + work->previous_argument = 0; + work->nrepeats = 0; + + /* Actually demangle the arguments. */ + result = demangle_args (work, mangled, declp); + + /* Restore the previous_argument field. */ + if (work->previous_argument) + { + string_delete (work->previous_argument); + free ((char *) work->previous_argument); + } + work->previous_argument = saved_previous_argument; + --work->forgetting_types; + work->nrepeats = saved_nrepeats; + + return result; +} + +/* Returns 1 if a valid function name was found or 0 otherwise. */ + +static int +demangle_function_name (struct work_stuff *work, const char **mangled, + string *declp, const char *scan) +{ + size_t i; + string type; + const char *tem; + + string_appendn (declp, (*mangled), scan - (*mangled)); + string_need (declp, 1); + *(declp -> p) = '\0'; + + /* Consume the function name, including the "__" separating the name + from the signature. We are guaranteed that SCAN points to the + separator. */ + + (*mangled) = scan + 2; + /* We may be looking at an instantiation of a template function: + foo__Xt1t2_Ft3t4, where t1, t2, ... are template arguments and a + following _F marks the start of the function arguments. Handle + the template arguments first. */ + + if (HP_DEMANGLING && (**mangled == 'X')) + { + demangle_arm_hp_template (work, mangled, 0, declp); + /* This leaves MANGLED pointing to the 'F' marking func args */ + } + + if (LUCID_DEMANGLING || ARM_DEMANGLING || HP_DEMANGLING || EDG_DEMANGLING) + { + + /* See if we have an ARM style constructor or destructor operator. + If so, then just record it, clear the decl, and return. + We can't build the actual constructor/destructor decl until later, + when we recover the class name from the signature. */ + + if (strcmp (declp -> b, "__ct") == 0) + { + work -> constructor += 1; + string_clear (declp); + return 1; + } + else if (strcmp (declp -> b, "__dt") == 0) + { + work -> destructor += 1; + string_clear (declp); + return 1; + } + } + + if (declp->p - declp->b >= 3 + && declp->b[0] == 'o' + && declp->b[1] == 'p' + && strchr (cplus_markers, declp->b[2]) != NULL) + { + /* see if it's an assignment expression */ + if (declp->p - declp->b >= 10 /* op$assign_ */ + && memcmp (declp->b + 3, "assign_", 7) == 0) + { + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + int len = declp->p - declp->b - 10; + if ((int) strlen (optable[i].in) == len + && memcmp (optable[i].in, declp->b + 10, len) == 0) + { + string_clear (declp); + string_append (declp, "operator"); + string_append (declp, optable[i].out); + string_append (declp, "="); + break; + } + } + } + else + { + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + int len = declp->p - declp->b - 3; + if ((int) strlen (optable[i].in) == len + && memcmp (optable[i].in, declp->b + 3, len) == 0) + { + string_clear (declp); + string_append (declp, "operator"); + string_append (declp, optable[i].out); + break; + } + } + } + } + else if (declp->p - declp->b >= 5 && memcmp (declp->b, "type", 4) == 0 + && strchr (cplus_markers, declp->b[4]) != NULL) + { + /* type conversion operator */ + tem = declp->b + 5; + if (do_type (work, &tem, &type)) + { + string_clear (declp); + string_append (declp, "operator "); + string_appends (declp, &type); + string_delete (&type); + } + } + else if (declp->b[0] == '_' && declp->b[1] == '_' + && declp->b[2] == 'o' && declp->b[3] == 'p') + { + /* ANSI. */ + /* type conversion operator. */ + tem = declp->b + 4; + if (do_type (work, &tem, &type)) + { + string_clear (declp); + string_append (declp, "operator "); + string_appends (declp, &type); + string_delete (&type); + } + } + else if (declp->b[0] == '_' && declp->b[1] == '_' + && ISLOWER((unsigned char)declp->b[2]) + && ISLOWER((unsigned char)declp->b[3])) + { + if (declp->b[4] == '\0') + { + /* Operator. */ + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + if (strlen (optable[i].in) == 2 + && memcmp (optable[i].in, declp->b + 2, 2) == 0) + { + string_clear (declp); + string_append (declp, "operator"); + string_append (declp, optable[i].out); + break; + } + } + } + else + { + if (declp->b[2] == 'a' && declp->b[5] == '\0') + { + /* Assignment. */ + for (i = 0; i < ARRAY_SIZE (optable); i++) + { + if (strlen (optable[i].in) == 3 + && memcmp (optable[i].in, declp->b + 2, 3) == 0) + { + string_clear (declp); + string_append (declp, "operator"); + string_append (declp, optable[i].out); + break; + } + } + } + } + } + + /* If a function name was obtained but it's not valid, we were not + successful. */ + if (LEN_STRING (declp) == 1 && declp->b[0] == '.') + return 0; + else + return 1; +} + +/* a mini string-handling package */ + +static void +string_need (string *s, int n) +{ + int tem; + + if (s->b == NULL) + { + if (n < 32) + { + n = 32; + } + s->p = s->b = XNEWVEC (char, n); + s->e = s->b + n; + } + else if (s->e - s->p < n) + { + tem = s->p - s->b; + n += tem; + n *= 2; + s->b = XRESIZEVEC (char, s->b, n); + s->p = s->b + tem; + s->e = s->b + n; + } +} + +static void +string_delete (string *s) +{ + if (s->b != NULL) + { + free (s->b); + s->b = s->e = s->p = NULL; + } +} + +static void +string_init (string *s) +{ + s->b = s->p = s->e = NULL; +} + +static void +string_clear (string *s) +{ + s->p = s->b; +} + +#if 0 + +static int +string_empty (string *s) +{ + return (s->b == s->p); +} + +#endif + +static void +string_append (string *p, const char *s) +{ + int n; + if (s == NULL || *s == '\0') + return; + n = strlen (s); + string_need (p, n); + memcpy (p->p, s, n); + p->p += n; +} + +static void +string_appends (string *p, string *s) +{ + int n; + + if (s->b != s->p) + { + n = s->p - s->b; + string_need (p, n); + memcpy (p->p, s->b, n); + p->p += n; + } +} + +static void +string_appendn (string *p, const char *s, int n) +{ + if (n != 0) + { + string_need (p, n); + memcpy (p->p, s, n); + p->p += n; + } +} + +static void +string_prepend (string *p, const char *s) +{ + if (s != NULL && *s != '\0') + { + string_prependn (p, s, strlen (s)); + } +} + +static void +string_prepends (string *p, string *s) +{ + if (s->b != s->p) + { + string_prependn (p, s->b, s->p - s->b); + } +} + +static void +string_prependn (string *p, const char *s, int n) +{ + char *q; + + if (n != 0) + { + string_need (p, n); + for (q = p->p - 1; q >= p->b; q--) + { + q[n] = q[0]; + } + memcpy (p->b, s, n); + p->p += n; + } +} + +static void +string_append_template_idx (string *s, int idx) +{ + char buf[INTBUF_SIZE + 1 /* 'T' */]; + sprintf(buf, "T%d", idx); + string_append (s, buf); +} diff --git a/external/gpl3/gdb/dist/libiberty/crc32.c b/external/gpl3/gdb/dist/libiberty/crc32.c new file mode 100644 index 000000000000..12d9be07cfd6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/crc32.c @@ -0,0 +1,181 @@ +/* crc32.c + Copyright (C) 2009, 2011 Free Software Foundation, Inc. + + This file is part of the libiberty library. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combined + executable.) + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "libiberty.h" + +/* This table was generated by the following program. This matches + what gdb does. + + #include + + int + main () + { + int i, j; + unsigned int c; + int table[256]; + + for (i = 0; i < 256; i++) + { + for (c = i << 24, j = 8; j > 0; --j) + c = c & 0x80000000 ? (c << 1) ^ 0x04c11db7 : (c << 1); + table[i] = c; + } + + printf ("static const unsigned int crc32_table[] =\n{\n"); + for (i = 0; i < 256; i += 4) + { + printf (" 0x%08x, 0x%08x, 0x%08x, 0x%08x", + table[i + 0], table[i + 1], table[i + 2], table[i + 3]); + if (i + 4 < 256) + putchar (','); + putchar ('\n'); + } + printf ("};\n"); + return 0; + } + + For more information on CRC, see, e.g., + http://www.ross.net/crc/download/crc_v3.txt. */ + +static const unsigned int crc32_table[] = +{ + 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, + 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, + 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, + 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, + 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, + 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, + 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, + 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, + 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, + 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, + 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, + 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, + 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, + 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, + 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, + 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, + 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, + 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, + 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, + 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff, + 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, + 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, + 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, + 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, + 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, + 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, + 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, + 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, + 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, + 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, + 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, + 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, + 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +}; + +/* + +@deftypefn Extension {unsigned int} crc32 (const unsigned char *@var{buf}, @ + int @var{len}, unsigned int @var{init}) + +Compute the 32-bit CRC of @var{buf} which has length @var{len}. The +starting value is @var{init}; this may be used to compute the CRC of +data split across multiple buffers by passing the return value of each +call as the @var{init} parameter of the next. + +This is intended to match the CRC used by the @command{gdb} remote +protocol for the @samp{qCRC} command. In order to get the same +results as gdb for a block of data, you must pass the first CRC +parameter as @code{0xffffffff}. + +This CRC can be specified as: + + Width : 32 + Poly : 0x04c11db7 + Init : parameter, typically 0xffffffff + RefIn : false + RefOut : false + XorOut : 0 + +This differs from the "standard" CRC-32 algorithm in that the values +are not reflected, and there is no final XOR value. These differences +make it easy to compose the values of multiple blocks. + +@end deftypefn + +*/ + +unsigned int +xcrc32 (const unsigned char *buf, int len, unsigned int init) +{ + unsigned int crc = init; + while (len--) + { + crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buf) & 255]; + buf++; + } + return crc; +} diff --git a/external/gpl3/gdb/dist/libiberty/dyn-string.c b/external/gpl3/gdb/dist/libiberty/dyn-string.c new file mode 100644 index 000000000000..faa8d9477117 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/dyn-string.c @@ -0,0 +1,397 @@ +/* An abstract string datatype. + Copyright (C) 1998, 1999, 2000, 2002, 2004 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combined +executable.) + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "libiberty.h" +#include "dyn-string.h" + +/* Performs in-place initialization of a dyn_string struct. This + function can be used with a dyn_string struct on the stack or + embedded in another object. The contents of of the string itself + are still dynamically allocated. The string initially is capable + of holding at least SPACE characeters, including the terminating + NUL. If SPACE is 0, it will silently be increated to 1. + + If RETURN_ON_ALLOCATION_FAILURE is defined and memory allocation + fails, returns 0. Otherwise returns 1. */ + +int +dyn_string_init (struct dyn_string *ds_struct_ptr, int space) +{ + /* We need at least one byte in which to store the terminating NUL. */ + if (space == 0) + space = 1; + +#ifdef RETURN_ON_ALLOCATION_FAILURE + ds_struct_ptr->s = (char *) malloc (space); + if (ds_struct_ptr->s == NULL) + return 0; +#else + ds_struct_ptr->s = XNEWVEC (char, space); +#endif + ds_struct_ptr->allocated = space; + ds_struct_ptr->length = 0; + ds_struct_ptr->s[0] = '\0'; + + return 1; +} + +/* Create a new dynamic string capable of holding at least SPACE + characters, including the terminating NUL. If SPACE is 0, it will + be silently increased to 1. If RETURN_ON_ALLOCATION_FAILURE is + defined and memory allocation fails, returns NULL. Otherwise + returns the newly allocated string. */ + +dyn_string_t +dyn_string_new (int space) +{ + dyn_string_t result; +#ifdef RETURN_ON_ALLOCATION_FAILURE + result = (dyn_string_t) malloc (sizeof (struct dyn_string)); + if (result == NULL) + return NULL; + if (!dyn_string_init (result, space)) + { + free (result); + return NULL; + } +#else + result = XNEW (struct dyn_string); + dyn_string_init (result, space); +#endif + return result; +} + +/* Free the memory used by DS. */ + +void +dyn_string_delete (dyn_string_t ds) +{ + free (ds->s); + free (ds); +} + +/* Returns the contents of DS in a buffer allocated with malloc. It + is the caller's responsibility to deallocate the buffer using free. + DS is then set to the empty string. Deletes DS itself. */ + +char* +dyn_string_release (dyn_string_t ds) +{ + /* Store the old buffer. */ + char* result = ds->s; + /* The buffer is no longer owned by DS. */ + ds->s = NULL; + /* Delete DS. */ + free (ds); + /* Return the old buffer. */ + return result; +} + +/* Increase the capacity of DS so it can hold at least SPACE + characters, plus the terminating NUL. This function will not (at + present) reduce the capacity of DS. Returns DS on success. + + If RETURN_ON_ALLOCATION_FAILURE is defined and a memory allocation + operation fails, deletes DS and returns NULL. */ + +dyn_string_t +dyn_string_resize (dyn_string_t ds, int space) +{ + int new_allocated = ds->allocated; + + /* Increase SPACE to hold the NUL termination. */ + ++space; + + /* Increase allocation by factors of two. */ + while (space > new_allocated) + new_allocated *= 2; + + if (new_allocated != ds->allocated) + { + ds->allocated = new_allocated; + /* We actually need more space. */ +#ifdef RETURN_ON_ALLOCATION_FAILURE + ds->s = (char *) realloc (ds->s, ds->allocated); + if (ds->s == NULL) + { + free (ds); + return NULL; + } +#else + ds->s = XRESIZEVEC (char, ds->s, ds->allocated); +#endif + } + + return ds; +} + +/* Sets the contents of DS to the empty string. */ + +void +dyn_string_clear (dyn_string_t ds) +{ + /* A dyn_string always has room for at least the NUL terminator. */ + ds->s[0] = '\0'; + ds->length = 0; +} + +/* Makes the contents of DEST the same as the contents of SRC. DEST + and SRC must be distinct. Returns 1 on success. On failure, if + RETURN_ON_ALLOCATION_FAILURE, deletes DEST and returns 0. */ + +int +dyn_string_copy (dyn_string_t dest, dyn_string_t src) +{ + if (dest == src) + abort (); + + /* Make room in DEST. */ + if (dyn_string_resize (dest, src->length) == NULL) + return 0; + /* Copy DEST into SRC. */ + strcpy (dest->s, src->s); + /* Update the size of DEST. */ + dest->length = src->length; + return 1; +} + +/* Copies SRC, a NUL-terminated string, into DEST. Returns 1 on + success. On failure, if RETURN_ON_ALLOCATION_FAILURE, deletes DEST + and returns 0. */ + +int +dyn_string_copy_cstr (dyn_string_t dest, const char *src) +{ + int length = strlen (src); + /* Make room in DEST. */ + if (dyn_string_resize (dest, length) == NULL) + return 0; + /* Copy DEST into SRC. */ + strcpy (dest->s, src); + /* Update the size of DEST. */ + dest->length = length; + return 1; +} + +/* Inserts SRC at the beginning of DEST. DEST is expanded as + necessary. SRC and DEST must be distinct. Returns 1 on success. + On failure, if RETURN_ON_ALLOCATION_FAILURE, deletes DEST and + returns 0. */ + +int +dyn_string_prepend (dyn_string_t dest, dyn_string_t src) +{ + return dyn_string_insert (dest, 0, src); +} + +/* Inserts SRC, a NUL-terminated string, at the beginning of DEST. + DEST is expanded as necessary. Returns 1 on success. On failure, + if RETURN_ON_ALLOCATION_FAILURE, deletes DEST and returns 0. */ + +int +dyn_string_prepend_cstr (dyn_string_t dest, const char *src) +{ + return dyn_string_insert_cstr (dest, 0, src); +} + +/* Inserts SRC into DEST starting at position POS. DEST is expanded + as necessary. SRC and DEST must be distinct. Returns 1 on + success. On failure, if RETURN_ON_ALLOCATION_FAILURE, deletes DEST + and returns 0. */ + +int +dyn_string_insert (dyn_string_t dest, int pos, dyn_string_t src) +{ + int i; + + if (src == dest) + abort (); + + if (dyn_string_resize (dest, dest->length + src->length) == NULL) + return 0; + /* Make room for the insertion. Be sure to copy the NUL. */ + for (i = dest->length; i >= pos; --i) + dest->s[i + src->length] = dest->s[i]; + /* Splice in the new stuff. */ + strncpy (dest->s + pos, src->s, src->length); + /* Compute the new length. */ + dest->length += src->length; + return 1; +} + +/* Inserts SRC, a NUL-terminated string, into DEST starting at + position POS. DEST is expanded as necessary. Returns 1 on + success. On failure, RETURN_ON_ALLOCATION_FAILURE, deletes DEST + and returns 0. */ + +int +dyn_string_insert_cstr (dyn_string_t dest, int pos, const char *src) +{ + int i; + int length = strlen (src); + + if (dyn_string_resize (dest, dest->length + length) == NULL) + return 0; + /* Make room for the insertion. Be sure to copy the NUL. */ + for (i = dest->length; i >= pos; --i) + dest->s[i + length] = dest->s[i]; + /* Splice in the new stuff. */ + strncpy (dest->s + pos, src, length); + /* Compute the new length. */ + dest->length += length; + return 1; +} + +/* Inserts character C into DEST starting at position POS. DEST is + expanded as necessary. Returns 1 on success. On failure, + RETURN_ON_ALLOCATION_FAILURE, deletes DEST and returns 0. */ + +int +dyn_string_insert_char (dyn_string_t dest, int pos, int c) +{ + int i; + + if (dyn_string_resize (dest, dest->length + 1) == NULL) + return 0; + /* Make room for the insertion. Be sure to copy the NUL. */ + for (i = dest->length; i >= pos; --i) + dest->s[i + 1] = dest->s[i]; + /* Add the new character. */ + dest->s[pos] = c; + /* Compute the new length. */ + ++dest->length; + return 1; +} + +/* Append S to DS, resizing DS if necessary. Returns 1 on success. + On failure, if RETURN_ON_ALLOCATION_FAILURE, deletes DEST and + returns 0. */ + +int +dyn_string_append (dyn_string_t dest, dyn_string_t s) +{ + if (dyn_string_resize (dest, dest->length + s->length) == 0) + return 0; + strcpy (dest->s + dest->length, s->s); + dest->length += s->length; + return 1; +} + +/* Append the NUL-terminated string S to DS, resizing DS if necessary. + Returns 1 on success. On failure, if RETURN_ON_ALLOCATION_FAILURE, + deletes DEST and returns 0. */ + +int +dyn_string_append_cstr (dyn_string_t dest, const char *s) +{ + int len = strlen (s); + + /* The new length is the old length plus the size of our string, plus + one for the null at the end. */ + if (dyn_string_resize (dest, dest->length + len) == NULL) + return 0; + strcpy (dest->s + dest->length, s); + dest->length += len; + return 1; +} + +/* Appends C to the end of DEST. Returns 1 on success. On failure, + if RETURN_ON_ALLOCATION_FAILURE, deletes DEST and returns 0. */ + +int +dyn_string_append_char (dyn_string_t dest, int c) +{ + /* Make room for the extra character. */ + if (dyn_string_resize (dest, dest->length + 1) == NULL) + return 0; + /* Append the character; it will overwrite the old NUL. */ + dest->s[dest->length] = c; + /* Add a new NUL at the end. */ + dest->s[dest->length + 1] = '\0'; + /* Update the length. */ + ++(dest->length); + return 1; +} + +/* Sets the contents of DEST to the substring of SRC starting at START + and ending before END. START must be less than or equal to END, + and both must be between zero and the length of SRC, inclusive. + Returns 1 on success. On failure, if RETURN_ON_ALLOCATION_FAILURE, + deletes DEST and returns 0. */ + +int +dyn_string_substring (dyn_string_t dest, dyn_string_t src, + int start, int end) +{ + int i; + int length = end - start; + + if (start > end || start > src->length || end > src->length) + abort (); + + /* Make room for the substring. */ + if (dyn_string_resize (dest, length) == NULL) + return 0; + /* Copy the characters in the substring, */ + for (i = length; --i >= 0; ) + dest->s[i] = src->s[start + i]; + /* NUL-terimate the result. */ + dest->s[length] = '\0'; + /* Record the length of the substring. */ + dest->length = length; + + return 1; +} + +/* Returns non-zero if DS1 and DS2 have the same contents. */ + +int +dyn_string_eq (dyn_string_t ds1, dyn_string_t ds2) +{ + /* If DS1 and DS2 have different lengths, they must not be the same. */ + if (ds1->length != ds2->length) + return 0; + else + return !strcmp (ds1->s, ds2->s); +} diff --git a/external/gpl3/gdb/dist/libiberty/fdmatch.c b/external/gpl3/gdb/dist/libiberty/fdmatch.c new file mode 100644 index 000000000000..f613cb3c01ea --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/fdmatch.c @@ -0,0 +1,68 @@ +/* Compare two open file descriptors to see if they refer to the same file. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + + +/* + +@deftypefn Extension int fdmatch (int @var{fd1}, int @var{fd2}) + +Check to see if two open file descriptors refer to the same file. +This is useful, for example, when we have an open file descriptor for +an unnamed file, and the name of a file that we believe to correspond +to that fd. This can happen when we are exec'd with an already open +file (@code{stdout} for example) or from the SVR4 @file{/proc} calls +that return open file descriptors for mapped address spaces. All we +have to do is open the file by name and check the two file descriptors +for a match, which is done by comparing major and minor device numbers +and inode numbers. + +@end deftypefn + +BUGS + + (FIXME: does this work for networks?) + It works for NFS, which assigns a device number to each mount. + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include +#include + +int fdmatch (int fd1, int fd2) +{ + struct stat sbuf1; + struct stat sbuf2; + + if ((fstat (fd1, &sbuf1) == 0) && + (fstat (fd2, &sbuf2) == 0) && + (sbuf1.st_dev == sbuf2.st_dev) && + (sbuf1.st_ino == sbuf2.st_ino)) + { + return (1); + } + else + { + return (0); + } +} diff --git a/external/gpl3/gdb/dist/libiberty/ffs.c b/external/gpl3/gdb/dist/libiberty/ffs.c new file mode 100644 index 000000000000..603cbe8ed994 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/ffs.c @@ -0,0 +1,26 @@ +/* ffs -- Find the first bit set in the parameter + +@deftypefn Supplemental int ffs (int @var{valu}) + +Find the first (least significant) bit set in @var{valu}. Bits are +numbered from right to left, starting with bit 1 (corresponding to the +value 1). If @var{valu} is zero, zero is returned. + +@end deftypefn + +*/ + +int +ffs (register int valu) +{ + register int bit; + + if (valu == 0) + return 0; + + for (bit = 1; !(valu & 1); bit++) + valu >>= 1; + + return bit; +} + diff --git a/external/gpl3/gdb/dist/libiberty/fibheap.c b/external/gpl3/gdb/dist/libiberty/fibheap.c new file mode 100644 index 000000000000..a37ee4ef270a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/fibheap.c @@ -0,0 +1,486 @@ +/* A Fibonacci heap datatype. + Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Contributed by Daniel Berlin (dan@cgsoftware.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#include "libiberty.h" +#include "fibheap.h" + + +#define FIBHEAPKEY_MIN LONG_MIN + +static void fibheap_ins_root (fibheap_t, fibnode_t); +static void fibheap_rem_root (fibheap_t, fibnode_t); +static void fibheap_consolidate (fibheap_t); +static void fibheap_link (fibheap_t, fibnode_t, fibnode_t); +static void fibheap_cut (fibheap_t, fibnode_t, fibnode_t); +static void fibheap_cascading_cut (fibheap_t, fibnode_t); +static fibnode_t fibheap_extr_min_node (fibheap_t); +static int fibheap_compare (fibheap_t, fibnode_t, fibnode_t); +static int fibheap_comp_data (fibheap_t, fibheapkey_t, void *, fibnode_t); +static fibnode_t fibnode_new (void); +static void fibnode_insert_after (fibnode_t, fibnode_t); +#define fibnode_insert_before(a, b) fibnode_insert_after (a->left, b) +static fibnode_t fibnode_remove (fibnode_t); + + +/* Create a new fibonacci heap. */ +fibheap_t +fibheap_new (void) +{ + return (fibheap_t) xcalloc (1, sizeof (struct fibheap)); +} + +/* Create a new fibonacci heap node. */ +static fibnode_t +fibnode_new (void) +{ + fibnode_t node; + + node = (fibnode_t) xcalloc (1, sizeof *node); + node->left = node; + node->right = node; + + return node; +} + +static inline int +fibheap_compare (fibheap_t heap ATTRIBUTE_UNUSED, fibnode_t a, fibnode_t b) +{ + if (a->key < b->key) + return -1; + if (a->key > b->key) + return 1; + return 0; +} + +static inline int +fibheap_comp_data (fibheap_t heap, fibheapkey_t key, void *data, fibnode_t b) +{ + struct fibnode a; + + a.key = key; + a.data = data; + + return fibheap_compare (heap, &a, b); +} + +/* Insert DATA, with priority KEY, into HEAP. */ +fibnode_t +fibheap_insert (fibheap_t heap, fibheapkey_t key, void *data) +{ + fibnode_t node; + + /* Create the new node. */ + node = fibnode_new (); + + /* Set the node's data. */ + node->data = data; + node->key = key; + + /* Insert it into the root list. */ + fibheap_ins_root (heap, node); + + /* If their was no minimum, or this key is less than the min, + it's the new min. */ + if (heap->min == NULL || node->key < heap->min->key) + heap->min = node; + + heap->nodes++; + + return node; +} + +/* Return the data of the minimum node (if we know it). */ +void * +fibheap_min (fibheap_t heap) +{ + /* If there is no min, we can't easily return it. */ + if (heap->min == NULL) + return NULL; + return heap->min->data; +} + +/* Return the key of the minimum node (if we know it). */ +fibheapkey_t +fibheap_min_key (fibheap_t heap) +{ + /* If there is no min, we can't easily return it. */ + if (heap->min == NULL) + return 0; + return heap->min->key; +} + +/* Union HEAPA and HEAPB into a new heap. */ +fibheap_t +fibheap_union (fibheap_t heapa, fibheap_t heapb) +{ + fibnode_t a_root, b_root, temp; + + /* If one of the heaps is empty, the union is just the other heap. */ + if ((a_root = heapa->root) == NULL) + { + free (heapa); + return heapb; + } + if ((b_root = heapb->root) == NULL) + { + free (heapb); + return heapa; + } + + /* Merge them to the next nodes on the opposite chain. */ + a_root->left->right = b_root; + b_root->left->right = a_root; + temp = a_root->left; + a_root->left = b_root->left; + b_root->left = temp; + heapa->nodes += heapb->nodes; + + /* And set the new minimum, if it's changed. */ + if (fibheap_compare (heapa, heapb->min, heapa->min) < 0) + heapa->min = heapb->min; + + free (heapb); + return heapa; +} + +/* Extract the data of the minimum node from HEAP. */ +void * +fibheap_extract_min (fibheap_t heap) +{ + fibnode_t z; + void *ret = NULL; + + /* If we don't have a min set, it means we have no nodes. */ + if (heap->min != NULL) + { + /* Otherwise, extract the min node, free the node, and return the + node's data. */ + z = fibheap_extr_min_node (heap); + ret = z->data; + free (z); + } + + return ret; +} + +/* Replace both the KEY and the DATA associated with NODE. */ +void * +fibheap_replace_key_data (fibheap_t heap, fibnode_t node, + fibheapkey_t key, void *data) +{ + void *odata; + fibheapkey_t okey; + fibnode_t y; + + /* If we wanted to, we could actually do a real increase by redeleting and + inserting. However, this would require O (log n) time. So just bail out + for now. */ + if (fibheap_comp_data (heap, key, data, node) > 0) + return NULL; + + odata = node->data; + okey = node->key; + node->data = data; + node->key = key; + y = node->parent; + + /* Short-circuit if the key is the same, as we then don't have to + do anything. Except if we're trying to force the new node to + be the new minimum for delete. */ + if (okey == key && okey != FIBHEAPKEY_MIN) + return odata; + + /* These two compares are specifically <= 0 to make sure that in the case + of equality, a node we replaced the data on, becomes the new min. This + is needed so that delete's call to extractmin gets the right node. */ + if (y != NULL && fibheap_compare (heap, node, y) <= 0) + { + fibheap_cut (heap, node, y); + fibheap_cascading_cut (heap, y); + } + + if (fibheap_compare (heap, node, heap->min) <= 0) + heap->min = node; + + return odata; +} + +/* Replace the DATA associated with NODE. */ +void * +fibheap_replace_data (fibheap_t heap, fibnode_t node, void *data) +{ + return fibheap_replace_key_data (heap, node, node->key, data); +} + +/* Replace the KEY associated with NODE. */ +fibheapkey_t +fibheap_replace_key (fibheap_t heap, fibnode_t node, fibheapkey_t key) +{ + int okey = node->key; + fibheap_replace_key_data (heap, node, key, node->data); + return okey; +} + +/* Delete NODE from HEAP. */ +void * +fibheap_delete_node (fibheap_t heap, fibnode_t node) +{ + void *ret = node->data; + + /* To perform delete, we just make it the min key, and extract. */ + fibheap_replace_key (heap, node, FIBHEAPKEY_MIN); + if (node != heap->min) + { + fprintf (stderr, "Can't force minimum on fibheap.\n"); + abort (); + } + fibheap_extract_min (heap); + + return ret; +} + +/* Delete HEAP. */ +void +fibheap_delete (fibheap_t heap) +{ + while (heap->min != NULL) + free (fibheap_extr_min_node (heap)); + + free (heap); +} + +/* Determine if HEAP is empty. */ +int +fibheap_empty (fibheap_t heap) +{ + return heap->nodes == 0; +} + +/* Extract the minimum node of the heap. */ +static fibnode_t +fibheap_extr_min_node (fibheap_t heap) +{ + fibnode_t ret = heap->min; + fibnode_t x, y, orig; + + /* Attach the child list of the minimum node to the root list of the heap. + If there is no child list, we don't do squat. */ + for (x = ret->child, orig = NULL; x != orig && x != NULL; x = y) + { + if (orig == NULL) + orig = x; + y = x->right; + x->parent = NULL; + fibheap_ins_root (heap, x); + } + + /* Remove the old root. */ + fibheap_rem_root (heap, ret); + heap->nodes--; + + /* If we are left with no nodes, then the min is NULL. */ + if (heap->nodes == 0) + heap->min = NULL; + else + { + /* Otherwise, consolidate to find new minimum, as well as do the reorg + work that needs to be done. */ + heap->min = ret->right; + fibheap_consolidate (heap); + } + + return ret; +} + +/* Insert NODE into the root list of HEAP. */ +static void +fibheap_ins_root (fibheap_t heap, fibnode_t node) +{ + /* If the heap is currently empty, the new node becomes the singleton + circular root list. */ + if (heap->root == NULL) + { + heap->root = node; + node->left = node; + node->right = node; + return; + } + + /* Otherwise, insert it in the circular root list between the root + and it's right node. */ + fibnode_insert_after (heap->root, node); +} + +/* Remove NODE from the rootlist of HEAP. */ +static void +fibheap_rem_root (fibheap_t heap, fibnode_t node) +{ + if (node->left == node) + heap->root = NULL; + else + heap->root = fibnode_remove (node); +} + +/* Consolidate the heap. */ +static void +fibheap_consolidate (fibheap_t heap) +{ + fibnode_t a[1 + 8 * sizeof (long)]; + fibnode_t w; + fibnode_t y; + fibnode_t x; + int i; + int d; + int D; + + D = 1 + 8 * sizeof (long); + + memset (a, 0, sizeof (fibnode_t) * D); + + while ((w = heap->root) != NULL) + { + x = w; + fibheap_rem_root (heap, w); + d = x->degree; + while (a[d] != NULL) + { + y = a[d]; + if (fibheap_compare (heap, x, y) > 0) + { + fibnode_t temp; + temp = x; + x = y; + y = temp; + } + fibheap_link (heap, y, x); + a[d] = NULL; + d++; + } + a[d] = x; + } + heap->min = NULL; + for (i = 0; i < D; i++) + if (a[i] != NULL) + { + fibheap_ins_root (heap, a[i]); + if (heap->min == NULL || fibheap_compare (heap, a[i], heap->min) < 0) + heap->min = a[i]; + } +} + +/* Make NODE a child of PARENT. */ +static void +fibheap_link (fibheap_t heap ATTRIBUTE_UNUSED, + fibnode_t node, fibnode_t parent) +{ + if (parent->child == NULL) + parent->child = node; + else + fibnode_insert_before (parent->child, node); + node->parent = parent; + parent->degree++; + node->mark = 0; +} + +/* Remove NODE from PARENT's child list. */ +static void +fibheap_cut (fibheap_t heap, fibnode_t node, fibnode_t parent) +{ + fibnode_remove (node); + parent->degree--; + fibheap_ins_root (heap, node); + node->parent = NULL; + node->mark = 0; +} + +static void +fibheap_cascading_cut (fibheap_t heap, fibnode_t y) +{ + fibnode_t z; + + while ((z = y->parent) != NULL) + { + if (y->mark == 0) + { + y->mark = 1; + return; + } + else + { + fibheap_cut (heap, y, z); + y = z; + } + } +} + +static void +fibnode_insert_after (fibnode_t a, fibnode_t b) +{ + if (a == a->right) + { + a->right = b; + a->left = b; + b->right = a; + b->left = a; + } + else + { + b->right = a->right; + a->right->left = b; + a->right = b; + b->left = a; + } +} + +static fibnode_t +fibnode_remove (fibnode_t node) +{ + fibnode_t ret; + + if (node == node->left) + ret = NULL; + else + ret = node->left; + + if (node->parent != NULL && node->parent->child == node) + node->parent->child = ret; + + node->right->left = node->left; + node->left->right = node->right; + + node->parent = NULL; + node->left = node; + node->right = node; + + return ret; +} diff --git a/external/gpl3/gdb/dist/libiberty/filename_cmp.c b/external/gpl3/gdb/dist/libiberty/filename_cmp.c new file mode 100644 index 000000000000..0eed12086bfe --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/filename_cmp.c @@ -0,0 +1,127 @@ +/* File name comparison routine. + + Copyright (C) 2007 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#include "filenames.h" +#include "safe-ctype.h" + +/* + +@deftypefn Extension int filename_cmp (const char *@var{s1}, const char *@var{s2}) + +Return zero if the two file names @var{s1} and @var{s2} are equivalent. +If not equivalent, the returned value is similar to what @code{strcmp} +would return. In other words, it returns a negative value if @var{s1} +is less than @var{s2}, or a positive value if @var{s2} is greater than +@var{s2}. + +This function does not normalize file names. As a result, this function +will treat filenames that are spelled differently as different even in +the case when the two filenames point to the same underlying file. +However, it does handle the fact that on DOS-like file systems, forward +and backward slashes are equal. + +@end deftypefn + +*/ + +int +filename_cmp (const char *s1, const char *s2) +{ +#ifndef HAVE_DOS_BASED_FILE_SYSTEM + return strcmp(s1, s2); +#else + for (;;) + { + int c1 = TOLOWER (*s1); + int c2 = TOLOWER (*s2); + + /* On DOS-based file systems, the '/' and the '\' are equivalent. */ + if (c1 == '/') + c1 = '\\'; + if (c2 == '/') + c2 = '\\'; + + if (c1 != c2) + return (c1 - c2); + + if (c1 == '\0') + return 0; + + s1++; + s2++; + } +#endif +} + +/* + +@deftypefn Extension int filename_ncmp (const char *@var{s1}, const char *@var{s2}, size_t @var{n}) + +Return zero if the two file names @var{s1} and @var{s2} are equivalent +in range @var{n}. +If not equivalent, the returned value is similar to what @code{strncmp} +would return. In other words, it returns a negative value if @var{s1} +is less than @var{s2}, or a positive value if @var{s2} is greater than +@var{s2}. + +This function does not normalize file names. As a result, this function +will treat filenames that are spelled differently as different even in +the case when the two filenames point to the same underlying file. +However, it does handle the fact that on DOS-like file systems, forward +and backward slashes are equal. + +@end deftypefn + +*/ + +int +filename_ncmp (const char *s1, const char *s2, size_t n) +{ +#ifndef HAVE_DOS_BASED_FILE_SYSTEM + return strncmp(s1, s2, n); +#else + if (!n) + return 0; + for (; n > 0; --n) + { + int c1 = TOLOWER (*s1); + int c2 = TOLOWER (*s2); + + /* On DOS-based file systems, the '/' and the '\' are equivalent. */ + if (c1 == '/') + c1 = '\\'; + if (c2 == '/') + c2 = '\\'; + + if (c1 == '\0' || c1 != c2) + return (c1 - c2); + + s1++; + s2++; + } + return 0; +#endif +} diff --git a/external/gpl3/gdb/dist/libiberty/floatformat.c b/external/gpl3/gdb/dist/libiberty/floatformat.c new file mode 100644 index 000000000000..1116c63117dc --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/floatformat.c @@ -0,0 +1,775 @@ +/* IEEE floating point support routines, for GDB, the GNU Debugger. + Copyright 1991, 1994, 1999, 2000, 2003, 2005, 2006, 2010 + Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* This is needed to pick up the NAN macro on some systems. */ +#define _GNU_SOURCE + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#ifdef HAVE_STRING_H +#include +#endif + +/* On some platforms, provides DBL_QNAN. */ +#ifdef STDC_HEADERS +#include +#endif + +#include "ansidecl.h" +#include "libiberty.h" +#include "floatformat.h" + +#ifndef INFINITY +#ifdef HUGE_VAL +#define INFINITY HUGE_VAL +#else +#define INFINITY (1.0 / 0.0) +#endif +#endif + +#ifndef NAN +#ifdef DBL_QNAN +#define NAN DBL_QNAN +#else +#define NAN (0.0 / 0.0) +#endif +#endif + +static int mant_bits_set (const struct floatformat *, const unsigned char *); +static unsigned long get_field (const unsigned char *, + enum floatformat_byteorders, + unsigned int, + unsigned int, + unsigned int); +static int floatformat_always_valid (const struct floatformat *fmt, + const void *from); + +static int +floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED, + const void *from ATTRIBUTE_UNUSED) +{ + return 1; +} + +/* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not + going to bother with trying to muck around with whether it is defined in + a system header, what we do if not, etc. */ +#define FLOATFORMAT_CHAR_BIT 8 + +/* floatformats for IEEE half, single and double, big and little endian. */ +const struct floatformat floatformat_ieee_half_big = +{ + floatformat_big, 16, 0, 1, 5, 15, 31, 6, 10, + floatformat_intbit_no, + "floatformat_ieee_half_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ieee_half_little = +{ + floatformat_little, 16, 0, 1, 5, 15, 31, 6, 10, + floatformat_intbit_no, + "floatformat_ieee_half_little", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ieee_single_big = +{ + floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23, + floatformat_intbit_no, + "floatformat_ieee_single_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ieee_single_little = +{ + floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23, + floatformat_intbit_no, + "floatformat_ieee_single_little", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ieee_double_big = +{ + floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52, + floatformat_intbit_no, + "floatformat_ieee_double_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ieee_double_little = +{ + floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52, + floatformat_intbit_no, + "floatformat_ieee_double_little", + floatformat_always_valid, + NULL +}; + +/* floatformat for IEEE double, little endian byte order, with big endian word + ordering, as on the ARM. */ + +const struct floatformat floatformat_ieee_double_littlebyte_bigword = +{ + floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52, + floatformat_intbit_no, + "floatformat_ieee_double_littlebyte_bigword", + floatformat_always_valid, + NULL +}; + +/* floatformat for VAX. Not quite IEEE, but close enough. */ + +const struct floatformat floatformat_vax_f = +{ + floatformat_vax, 32, 0, 1, 8, 129, 0, 9, 23, + floatformat_intbit_no, + "floatformat_vax_f", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_vax_d = +{ + floatformat_vax, 64, 0, 1, 8, 129, 0, 9, 55, + floatformat_intbit_no, + "floatformat_vax_d", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_vax_g = +{ + floatformat_vax, 64, 0, 1, 11, 1025, 0, 12, 52, + floatformat_intbit_no, + "floatformat_vax_g", + floatformat_always_valid, + NULL +}; + +static int floatformat_i387_ext_is_valid (const struct floatformat *fmt, + const void *from); + +static int +floatformat_i387_ext_is_valid (const struct floatformat *fmt, const void *from) +{ + /* In the i387 double-extended format, if the exponent is all ones, + then the integer bit must be set. If the exponent is neither 0 + nor ~0, the intbit must also be set. Only if the exponent is + zero can it be zero, and then it must be zero. */ + unsigned long exponent, int_bit; + const unsigned char *ufrom = (const unsigned char *) from; + + exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, + fmt->exp_start, fmt->exp_len); + int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize, + fmt->man_start, 1); + + if ((exponent == 0) != (int_bit == 0)) + return 0; + else + return 1; +} + +const struct floatformat floatformat_i387_ext = +{ + floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, + floatformat_intbit_yes, + "floatformat_i387_ext", + floatformat_i387_ext_is_valid, + NULL +}; +const struct floatformat floatformat_m68881_ext = +{ + /* Note that the bits from 16 to 31 are unused. */ + floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64, + floatformat_intbit_yes, + "floatformat_m68881_ext", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_i960_ext = +{ + /* Note that the bits from 0 to 15 are unused. */ + floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64, + floatformat_intbit_yes, + "floatformat_i960_ext", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_m88110_ext = +{ + floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, + floatformat_intbit_yes, + "floatformat_m88110_ext", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_m88110_harris_ext = +{ + /* Harris uses raw format 128 bytes long, but the number is just an ieee + double, and the last 64 bits are wasted. */ + floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52, + floatformat_intbit_no, + "floatformat_m88110_ext_harris", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_arm_ext_big = +{ + /* Bits 1 to 16 are unused. */ + floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, + floatformat_intbit_yes, + "floatformat_arm_ext_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_arm_ext_littlebyte_bigword = +{ + /* Bits 1 to 16 are unused. */ + floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, + floatformat_intbit_yes, + "floatformat_arm_ext_littlebyte_bigword", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ia64_spill_big = +{ + floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, + floatformat_intbit_yes, + "floatformat_ia64_spill_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ia64_spill_little = +{ + floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, + floatformat_intbit_yes, + "floatformat_ia64_spill_little", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ia64_quad_big = +{ + floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, + floatformat_intbit_no, + "floatformat_ia64_quad_big", + floatformat_always_valid, + NULL +}; +const struct floatformat floatformat_ia64_quad_little = +{ + floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, + floatformat_intbit_no, + "floatformat_ia64_quad_little", + floatformat_always_valid, + NULL +}; + +static int +floatformat_ibm_long_double_is_valid (const struct floatformat *fmt, + const void *from) +{ + const unsigned char *ufrom = (const unsigned char *) from; + const struct floatformat *hfmt = fmt->split_half; + long top_exp, bot_exp; + int top_nan = 0; + + top_exp = get_field (ufrom, hfmt->byteorder, hfmt->totalsize, + hfmt->exp_start, hfmt->exp_len); + bot_exp = get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize, + hfmt->exp_start, hfmt->exp_len); + + if ((unsigned long) top_exp == hfmt->exp_nan) + top_nan = mant_bits_set (hfmt, ufrom); + + /* A NaN is valid with any low part. */ + if (top_nan) + return 1; + + /* An infinity, zero or denormal requires low part 0 (positive or + negative). */ + if ((unsigned long) top_exp == hfmt->exp_nan || top_exp == 0) + { + if (bot_exp != 0) + return 0; + + return !mant_bits_set (hfmt, ufrom + 8); + } + + /* The top part is now a finite normal value. The long double value + is the sum of the two parts, and the top part must equal the + result of rounding the long double value to nearest double. Thus + the bottom part must be <= 0.5ulp of the top part in absolute + value, and if it is < 0.5ulp then the long double is definitely + valid. */ + if (bot_exp < top_exp - 53) + return 1; + if (bot_exp > top_exp - 53 && bot_exp != 0) + return 0; + if (bot_exp == 0) + { + /* The bottom part is 0 or denormal. Determine which, and if + denormal the first two set bits. */ + int first_bit = -1, second_bit = -1, cur_bit; + for (cur_bit = 0; (unsigned int) cur_bit < hfmt->man_len; cur_bit++) + if (get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize, + hfmt->man_start + cur_bit, 1)) + { + if (first_bit == -1) + first_bit = cur_bit; + else + { + second_bit = cur_bit; + break; + } + } + /* Bottom part 0 is OK. */ + if (first_bit == -1) + return 1; + /* The real exponent of the bottom part is -first_bit. */ + if (-first_bit < top_exp - 53) + return 1; + if (-first_bit > top_exp - 53) + return 0; + /* The bottom part is at least 0.5ulp of the top part. For this + to be OK, the bottom part must be exactly 0.5ulp (i.e. no + more bits set) and the top part must have last bit 0. */ + if (second_bit != -1) + return 0; + return !get_field (ufrom, hfmt->byteorder, hfmt->totalsize, + hfmt->man_start + hfmt->man_len - 1, 1); + } + else + { + /* The bottom part is at least 0.5ulp of the top part. For this + to be OK, it must be exactly 0.5ulp (i.e. no explicit bits + set) and the top part must have last bit 0. */ + if (get_field (ufrom, hfmt->byteorder, hfmt->totalsize, + hfmt->man_start + hfmt->man_len - 1, 1)) + return 0; + return !mant_bits_set (hfmt, ufrom + 8); + } +} + +const struct floatformat floatformat_ibm_long_double = +{ + floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, + floatformat_intbit_no, + "floatformat_ibm_long_double", + floatformat_ibm_long_double_is_valid, + &floatformat_ieee_double_big +}; + + +#ifndef min +#define min(a, b) ((a) < (b) ? (a) : (b)) +#endif + +/* Return 1 if any bits are explicitly set in the mantissa of UFROM, + format FMT, 0 otherwise. */ +static int +mant_bits_set (const struct floatformat *fmt, const unsigned char *ufrom) +{ + unsigned int mant_bits, mant_off; + int mant_bits_left; + + mant_off = fmt->man_start; + mant_bits_left = fmt->man_len; + while (mant_bits_left > 0) + { + mant_bits = min (mant_bits_left, 32); + + if (get_field (ufrom, fmt->byteorder, fmt->totalsize, + mant_off, mant_bits) != 0) + return 1; + + mant_off += mant_bits; + mant_bits_left -= mant_bits; + } + return 0; +} + +/* Extract a field which starts at START and is LEN bits long. DATA and + TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */ +static unsigned long +get_field (const unsigned char *data, enum floatformat_byteorders order, + unsigned int total_len, unsigned int start, unsigned int len) +{ + unsigned long result = 0; + unsigned int cur_byte; + int lo_bit, hi_bit, cur_bitshift = 0; + int nextbyte = (order == floatformat_little) ? 1 : -1; + + /* Start is in big-endian bit order! Fix that first. */ + start = total_len - (start + len); + + /* Start at the least significant part of the field. */ + if (order == floatformat_little) + cur_byte = start / FLOATFORMAT_CHAR_BIT; + else + cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT; + + lo_bit = start % FLOATFORMAT_CHAR_BIT; + hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT); + + do + { + unsigned int shifted = *(data + cur_byte) >> lo_bit; + unsigned int bits = hi_bit - lo_bit; + unsigned int mask = (1 << bits) - 1; + result |= (shifted & mask) << cur_bitshift; + len -= bits; + cur_bitshift += bits; + cur_byte += nextbyte; + lo_bit = 0; + hi_bit = min (len, FLOATFORMAT_CHAR_BIT); + } + while (len != 0); + + return result; +} + +/* Convert from FMT to a double. + FROM is the address of the extended float. + Store the double in *TO. */ + +void +floatformat_to_double (const struct floatformat *fmt, + const void *from, double *to) +{ + const unsigned char *ufrom = (const unsigned char *) from; + double dto; + long exponent; + unsigned long mant; + unsigned int mant_bits, mant_off; + int mant_bits_left; + int special_exponent; /* It's a NaN, denorm or zero */ + + /* Split values are not handled specially, since the top half has + the correctly rounded double value (in the only supported case of + split values). */ + + exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, + fmt->exp_start, fmt->exp_len); + + /* If the exponent indicates a NaN, we don't have information to + decide what to do. So we handle it like IEEE, except that we + don't try to preserve the type of NaN. FIXME. */ + if ((unsigned long) exponent == fmt->exp_nan) + { + int nan = mant_bits_set (fmt, ufrom); + + /* On certain systems (such as GNU/Linux), the use of the + INFINITY macro below may generate a warning that can not be + silenced due to a bug in GCC (PR preprocessor/11931). The + preprocessor fails to recognise the __extension__ keyword in + conjunction with the GNU/C99 extension for hexadecimal + floating point constants and will issue a warning when + compiling with -pedantic. */ + if (nan) + dto = NAN; + else + dto = INFINITY; + + if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) + dto = -dto; + + *to = dto; + + return; + } + + mant_bits_left = fmt->man_len; + mant_off = fmt->man_start; + dto = 0.0; + + special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan; + + /* Don't bias zero's, denorms or NaNs. */ + if (!special_exponent) + exponent -= fmt->exp_bias; + + /* Build the result algebraically. Might go infinite, underflow, etc; + who cares. */ + + /* If this format uses a hidden bit, explicitly add it in now. Otherwise, + increment the exponent by one to account for the integer bit. */ + + if (!special_exponent) + { + if (fmt->intbit == floatformat_intbit_no) + dto = ldexp (1.0, exponent); + else + exponent++; + } + + while (mant_bits_left > 0) + { + mant_bits = min (mant_bits_left, 32); + + mant = get_field (ufrom, fmt->byteorder, fmt->totalsize, + mant_off, mant_bits); + + /* Handle denormalized numbers. FIXME: What should we do for + non-IEEE formats? */ + if (special_exponent && exponent == 0 && mant != 0) + dto += ldexp ((double)mant, + (- fmt->exp_bias + - mant_bits + - (mant_off - fmt->man_start) + + 1)); + else + dto += ldexp ((double)mant, exponent - mant_bits); + if (exponent != 0) + exponent -= mant_bits; + mant_off += mant_bits; + mant_bits_left -= mant_bits; + } + + /* Negate it if negative. */ + if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) + dto = -dto; + *to = dto; +} + +static void put_field (unsigned char *, enum floatformat_byteorders, + unsigned int, + unsigned int, + unsigned int, + unsigned long); + +/* Set a field which starts at START and is LEN bits long. DATA and + TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */ +static void +put_field (unsigned char *data, enum floatformat_byteorders order, + unsigned int total_len, unsigned int start, unsigned int len, + unsigned long stuff_to_put) +{ + unsigned int cur_byte; + int lo_bit, hi_bit; + int nextbyte = (order == floatformat_little) ? 1 : -1; + + /* Start is in big-endian bit order! Fix that first. */ + start = total_len - (start + len); + + /* Start at the least significant part of the field. */ + if (order == floatformat_little) + cur_byte = start / FLOATFORMAT_CHAR_BIT; + else + cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT; + + lo_bit = start % FLOATFORMAT_CHAR_BIT; + hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT); + + do + { + unsigned char *byte_ptr = data + cur_byte; + unsigned int bits = hi_bit - lo_bit; + unsigned int mask = ((1 << bits) - 1) << lo_bit; + *byte_ptr = (*byte_ptr & ~mask) | ((stuff_to_put << lo_bit) & mask); + stuff_to_put >>= bits; + len -= bits; + cur_byte += nextbyte; + lo_bit = 0; + hi_bit = min (len, FLOATFORMAT_CHAR_BIT); + } + while (len != 0); +} + +/* The converse: convert the double *FROM to an extended float + and store where TO points. Neither FROM nor TO have any alignment + restrictions. */ + +void +floatformat_from_double (const struct floatformat *fmt, + const double *from, void *to) +{ + double dfrom; + int exponent; + double mant; + unsigned int mant_bits, mant_off; + int mant_bits_left; + unsigned char *uto = (unsigned char *) to; + + dfrom = *from; + memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT); + + /* Split values are not handled specially, since a bottom half of + zero is correct for any value representable as double (in the + only supported case of split values). */ + + /* If negative, set the sign bit. */ + if (dfrom < 0) + { + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1); + dfrom = -dfrom; + } + + if (dfrom == 0) + { + /* 0.0. */ + return; + } + + if (dfrom != dfrom) + { + /* NaN. */ + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, + fmt->exp_len, fmt->exp_nan); + /* Be sure it's not infinity, but NaN value is irrelevant. */ + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start, + 32, 1); + return; + } + + if (dfrom + dfrom == dfrom) + { + /* This can only happen for an infinite value (or zero, which we + already handled above). */ + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, + fmt->exp_len, fmt->exp_nan); + return; + } + + mant = frexp (dfrom, &exponent); + if (exponent + fmt->exp_bias - 1 > 0) + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, + fmt->exp_len, exponent + fmt->exp_bias - 1); + else + { + /* Handle a denormalized number. FIXME: What should we do for + non-IEEE formats? */ + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, + fmt->exp_len, 0); + mant = ldexp (mant, exponent + fmt->exp_bias - 1); + } + + mant_bits_left = fmt->man_len; + mant_off = fmt->man_start; + while (mant_bits_left > 0) + { + unsigned long mant_long; + mant_bits = mant_bits_left < 32 ? mant_bits_left : 32; + + mant *= 4294967296.0; + mant_long = (unsigned long)mant; + mant -= mant_long; + + /* If the integer bit is implicit, and we are not creating a + denormalized number, then we need to discard it. */ + if ((unsigned int) mant_bits_left == fmt->man_len + && fmt->intbit == floatformat_intbit_no + && exponent + fmt->exp_bias - 1 > 0) + { + mant_long &= 0x7fffffff; + mant_bits -= 1; + } + else if (mant_bits < 32) + { + /* The bits we want are in the most significant MANT_BITS bits of + mant_long. Move them to the least significant. */ + mant_long >>= 32 - mant_bits; + } + + put_field (uto, fmt->byteorder, fmt->totalsize, + mant_off, mant_bits, mant_long); + mant_off += mant_bits; + mant_bits_left -= mant_bits; + } +} + +/* Return non-zero iff the data at FROM is a valid number in format FMT. */ + +int +floatformat_is_valid (const struct floatformat *fmt, const void *from) +{ + return fmt->is_valid (fmt, from); +} + + +#ifdef IEEE_DEBUG + +#include + +/* This is to be run on a host which uses IEEE floating point. */ + +void +ieee_test (double n) +{ + double result; + + floatformat_to_double (&floatformat_ieee_double_little, &n, &result); + if ((n != result && (! isnan (n) || ! isnan (result))) + || (n < 0 && result >= 0) + || (n >= 0 && result < 0)) + printf ("Differ(to): %.20g -> %.20g\n", n, result); + + floatformat_from_double (&floatformat_ieee_double_little, &n, &result); + if ((n != result && (! isnan (n) || ! isnan (result))) + || (n < 0 && result >= 0) + || (n >= 0 && result < 0)) + printf ("Differ(from): %.20g -> %.20g\n", n, result); + +#if 0 + { + char exten[16]; + + floatformat_from_double (&floatformat_m68881_ext, &n, exten); + floatformat_to_double (&floatformat_m68881_ext, exten, &result); + if (n != result) + printf ("Differ(to+from): %.20g -> %.20g\n", n, result); + } +#endif + +#if IEEE_DEBUG > 1 + /* This is to be run on a host which uses 68881 format. */ + { + long double ex = *(long double *)exten; + if (ex != n) + printf ("Differ(from vs. extended): %.20g\n", n); + } +#endif +} + +int +main (void) +{ + ieee_test (0.0); + ieee_test (0.5); + ieee_test (256.0); + ieee_test (0.12345); + ieee_test (234235.78907234); + ieee_test (-512.0); + ieee_test (-0.004321); + ieee_test (1.2E-70); + ieee_test (1.2E-316); + ieee_test (4.9406564584124654E-324); + ieee_test (- 4.9406564584124654E-324); + ieee_test (- 0.0); + ieee_test (- INFINITY); + ieee_test (- NAN); + ieee_test (INFINITY); + ieee_test (NAN); + return 0; +} +#endif diff --git a/external/gpl3/gdb/dist/libiberty/fnmatch.c b/external/gpl3/gdb/dist/libiberty/fnmatch.c new file mode 100644 index 000000000000..fc897be2c6f7 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/fnmatch.c @@ -0,0 +1,220 @@ +/* Copyright (C) 1991, 1992, 1993 Free Software Foundation, Inc. + +NOTE: This source is derived from an old version taken from the GNU C +Library (glibc). + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#if defined (CONFIG_BROKETS) +/* We use instead of "config.h" so that a compilation + using -I. -I$srcdir will use ./config.h rather than $srcdir/config.h + (which it would do because it found this file in $srcdir). */ +#include +#else +#include "config.h" +#endif +#endif + + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + +/* This code to undef const added in libiberty. */ +#ifndef __STDC__ +/* This is a separate conditional since some stdc systems + reject `defined (const)'. */ +#ifndef const +#define const +#endif +#endif + +#include +#include +#include + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#if defined (_LIBC) || !defined (__GNU_LIBRARY__) + + +#if !defined(__GNU_LIBRARY__) && !defined(STDC_HEADERS) +extern int errno; +#endif + +/* Match STRING against the filename pattern PATTERN, returning zero if + it matches, nonzero if not. */ +int +fnmatch (const char *pattern, const char *string, int flags) +{ + register const char *p = pattern, *n = string; + register unsigned char c; + +#define FOLD(c) ((flags & FNM_CASEFOLD) ? TOLOWER (c) : (c)) + + while ((c = *p++) != '\0') + { + c = FOLD (c); + + switch (c) + { + case '?': + if (*n == '\0') + return FNM_NOMATCH; + else if ((flags & FNM_FILE_NAME) && *n == '/') + return FNM_NOMATCH; + else if ((flags & FNM_PERIOD) && *n == '.' && + (n == string || ((flags & FNM_FILE_NAME) && n[-1] == '/'))) + return FNM_NOMATCH; + break; + + case '\\': + if (!(flags & FNM_NOESCAPE)) + { + c = *p++; + c = FOLD (c); + } + if (FOLD ((unsigned char)*n) != c) + return FNM_NOMATCH; + break; + + case '*': + if ((flags & FNM_PERIOD) && *n == '.' && + (n == string || ((flags & FNM_FILE_NAME) && n[-1] == '/'))) + return FNM_NOMATCH; + + for (c = *p++; c == '?' || c == '*'; c = *p++, ++n) + if (((flags & FNM_FILE_NAME) && *n == '/') || + (c == '?' && *n == '\0')) + return FNM_NOMATCH; + + if (c == '\0') + return 0; + + { + unsigned char c1 = (!(flags & FNM_NOESCAPE) && c == '\\') ? *p : c; + c1 = FOLD (c1); + for (--p; *n != '\0'; ++n) + if ((c == '[' || FOLD ((unsigned char)*n) == c1) && + fnmatch (p, n, flags & ~FNM_PERIOD) == 0) + return 0; + return FNM_NOMATCH; + } + + case '[': + { + /* Nonzero if the sense of the character class is inverted. */ + register int negate; + + if (*n == '\0') + return FNM_NOMATCH; + + if ((flags & FNM_PERIOD) && *n == '.' && + (n == string || ((flags & FNM_FILE_NAME) && n[-1] == '/'))) + return FNM_NOMATCH; + + negate = (*p == '!' || *p == '^'); + if (negate) + ++p; + + c = *p++; + for (;;) + { + register unsigned char cstart = c, cend = c; + + if (!(flags & FNM_NOESCAPE) && c == '\\') + cstart = cend = *p++; + + cstart = cend = FOLD (cstart); + + if (c == '\0') + /* [ (unterminated) loses. */ + return FNM_NOMATCH; + + c = *p++; + c = FOLD (c); + + if ((flags & FNM_FILE_NAME) && c == '/') + /* [/] can never match. */ + return FNM_NOMATCH; + + if (c == '-' && *p != ']') + { + cend = *p++; + if (!(flags & FNM_NOESCAPE) && cend == '\\') + cend = *p++; + if (cend == '\0') + return FNM_NOMATCH; + cend = FOLD (cend); + + c = *p++; + } + + if (FOLD ((unsigned char)*n) >= cstart + && FOLD ((unsigned char)*n) <= cend) + goto matched; + + if (c == ']') + break; + } + if (!negate) + return FNM_NOMATCH; + break; + + matched:; + /* Skip the rest of the [...] that already matched. */ + while (c != ']') + { + if (c == '\0') + /* [... (unterminated) loses. */ + return FNM_NOMATCH; + + c = *p++; + if (!(flags & FNM_NOESCAPE) && c == '\\') + /* XXX 1003.2d11 is unclear if this is right. */ + ++p; + } + if (negate) + return FNM_NOMATCH; + } + break; + + default: + if (c != FOLD ((unsigned char)*n)) + return FNM_NOMATCH; + } + + ++n; + } + + if (*n == '\0') + return 0; + + if ((flags & FNM_LEADING_DIR) && *n == '/') + /* The FNM_LEADING_DIR flag says that "foo*" matches "foobar/frobozz". */ + return 0; + + return FNM_NOMATCH; +} + +#endif /* _LIBC or not __GNU_LIBRARY__. */ diff --git a/external/gpl3/gdb/dist/libiberty/fnmatch.txh b/external/gpl3/gdb/dist/libiberty/fnmatch.txh new file mode 100644 index 000000000000..b5a93734bf2a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/fnmatch.txh @@ -0,0 +1,49 @@ +@deftypefn Replacement int fnmatch (const char *@var{pattern}, @ + const char *@var{string}, int @var{flags}) + +Matches @var{string} against @var{pattern}, returning zero if it +matches, @code{FNM_NOMATCH} if not. @var{pattern} may contain the +wildcards @code{?} to match any one character, @code{*} to match any +zero or more characters, or a set of alternate characters in square +brackets, like @samp{[a-gt8]}, which match one character (@code{a} +through @code{g}, or @code{t}, or @code{8}, in this example) if that one +character is in the set. A set may be inverted (i.e., match anything +except what's in the set) by giving @code{^} or @code{!} as the first +character in the set. To include those characters in the set, list them +as anything other than the first character of the set. To include a +dash in the set, list it last in the set. A backslash character makes +the following character not special, so for example you could match +against a literal asterisk with @samp{\*}. To match a literal +backslash, use @samp{\\}. + +@code{flags} controls various aspects of the matching process, and is a +boolean OR of zero or more of the following values (defined in +@code{}): + +@table @code + +@item FNM_PATHNAME +@itemx FNM_FILE_NAME +@var{string} is assumed to be a path name. No wildcard will ever match +@code{/}. + +@item FNM_NOESCAPE +Do not interpret backslashes as quoting the following special character. + +@item FNM_PERIOD +A leading period (at the beginning of @var{string}, or if +@code{FNM_PATHNAME} after a slash) is not matched by @code{*} or +@code{?} but must be matched explicitly. + +@item FNM_LEADING_DIR +Means that @var{string} also matches @var{pattern} if some initial part +of @var{string} matches, and is followed by @code{/} and zero or more +characters. For example, @samp{foo*} would match either @samp{foobar} +or @samp{foobar/grill}. + +@item FNM_CASEFOLD +Ignores case when performing the comparison. + +@end table + +@end deftypefn diff --git a/external/gpl3/gdb/dist/libiberty/fopen_unlocked.c b/external/gpl3/gdb/dist/libiberty/fopen_unlocked.c new file mode 100644 index 000000000000..d1f78c462441 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/fopen_unlocked.c @@ -0,0 +1,129 @@ +/* Implement fopen_unlocked and related functions. + Copyright (C) 2005, 2011 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Extension void unlock_stream (FILE * @var{stream}) + +If the OS supports it, ensure that the supplied stream is setup to +avoid any multi-threaded locking. Otherwise leave the @code{FILE} +pointer unchanged. If the @var{stream} is @code{NULL} do nothing. + +@end deftypefn + +@deftypefn Extension void unlock_std_streams (void) + +If the OS supports it, ensure that the standard I/O streams, +@code{stdin}, @code{stdout} and @code{stderr} are setup to avoid any +multi-threaded locking. Otherwise do nothing. + +@end deftypefn + +@deftypefn Extension {FILE *} fopen_unlocked (const char *@var{path}, @ + const char * @var{mode}) + +Opens and returns a @code{FILE} pointer via @code{fopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +@deftypefn Extension {FILE *} fdopen_unlocked (int @var{fildes}, @ + const char * @var{mode}) + +Opens and returns a @code{FILE} pointer via @code{fdopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +@deftypefn Extension {FILE *} freopen_unlocked (const char * @var{path}, @ + const char * @var{mode}, FILE * @var{stream}) + +Opens and returns a @code{FILE} pointer via @code{freopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#ifdef HAVE_STDIO_EXT_H +#include +#endif + +#include "libiberty.h" + +/* This is an inline helper function to consolidate attempts to unlock + a stream. */ + +static inline void +unlock_1 (FILE *const fp ATTRIBUTE_UNUSED) +{ +#if defined(HAVE___FSETLOCKING) && defined(FSETLOCKING_BYCALLER) + if (fp) + __fsetlocking (fp, FSETLOCKING_BYCALLER); +#endif +} + +void +unlock_stream (FILE *fp) +{ + unlock_1 (fp); +} + +void +unlock_std_streams (void) +{ + unlock_1 (stdin); + unlock_1 (stdout); + unlock_1 (stderr); +} + +FILE * +fopen_unlocked (const char *path, const char *mode) +{ + FILE *const fp = fopen (path, mode); + unlock_1 (fp); + return fp; +} + +FILE * +fdopen_unlocked (int fildes, const char *mode) +{ + FILE *const fp = fdopen (fildes, mode); + unlock_1 (fp); + return fp; +} + +FILE * +freopen_unlocked (const char *path, const char *mode, FILE *stream) +{ + FILE *const fp = freopen (path, mode, stream); + unlock_1 (fp); + return fp; +} diff --git a/external/gpl3/gdb/dist/libiberty/functions.texi b/external/gpl3/gdb/dist/libiberty/functions.texi new file mode 100644 index 000000000000..c9df186be0f8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/functions.texi @@ -0,0 +1,1940 @@ +@c Automatically generated from *.c and others (the comments before +@c each entry tell you which file and where in that file). DO NOT EDIT! +@c Edit the *.c files, configure with --enable-maintainer-mode, +@c run 'make stamp-functions' and gather-docs will build a new copy. + +@c alloca.c:26 +@deftypefn Replacement void* alloca (size_t @var{size}) + +This function allocates memory which will be automatically reclaimed +after the procedure exits. The @libib{} implementation does not free +the memory immediately but will do so eventually during subsequent +calls to this function. Memory is allocated using @code{xmalloc} under +normal circumstances. + +The header file @file{alloca-conf.h} can be used in conjunction with the +GNU Autoconf test @code{AC_FUNC_ALLOCA} to test for and properly make +available this function. The @code{AC_FUNC_ALLOCA} test requires that +client code use a block of preprocessor code to be safe (see the Autoconf +manual for more); this header incorporates that logic and more, including +the possibility of a GCC built-in function. + +@end deftypefn + +@c asprintf.c:32 +@deftypefn Extension int asprintf (char **@var{resptr}, const char *@var{format}, ...) + +Like @code{sprintf}, but instead of passing a pointer to a buffer, you +pass a pointer to a pointer. This function will compute the size of +the buffer needed, allocate memory with @code{malloc}, and store a +pointer to the allocated memory in @code{*@var{resptr}}. The value +returned is the same as @code{sprintf} would return. If memory could +not be allocated, minus one is returned and @code{NULL} is stored in +@code{*@var{resptr}}. + +@end deftypefn + +@c atexit.c:6 +@deftypefn Supplemental int atexit (void (*@var{f})()) + +Causes function @var{f} to be called at exit. Returns 0. + +@end deftypefn + +@c basename.c:6 +@deftypefn Supplemental char* basename (const char *@var{name}) + +Returns a pointer to the last component of pathname @var{name}. +Behavior is undefined if the pathname ends in a directory separator. + +@end deftypefn + +@c bcmp.c:6 +@deftypefn Supplemental int bcmp (char *@var{x}, char *@var{y}, int @var{count}) + +Compares the first @var{count} bytes of two areas of memory. Returns +zero if they are the same, nonzero otherwise. Returns zero if +@var{count} is zero. A nonzero result only indicates a difference, +it does not indicate any sorting order (say, by having a positive +result mean @var{x} sorts before @var{y}). + +@end deftypefn + +@c bcopy.c:3 +@deftypefn Supplemental void bcopy (char *@var{in}, char *@var{out}, int @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. The use of @code{bcopy} is deprecated in new programs. + +@end deftypefn + +@c bsearch.c:33 +@deftypefn Supplemental void* bsearch (const void *@var{key}, @ + const void *@var{base}, size_t @var{nmemb}, size_t @var{size}, @ + int (*@var{compar})(const void *, const void *)) + +Performs a search over an array of @var{nmemb} elements pointed to by +@var{base} for a member that matches the object pointed to by @var{key}. +The size of each member is specified by @var{size}. The array contents +should be sorted in ascending order according to the @var{compar} +comparison function. This routine should take two arguments pointing to +the @var{key} and to an array member, in that order, and should return an +integer less than, equal to, or greater than zero if the @var{key} object +is respectively less than, matching, or greater than the array member. + +@end deftypefn + +@c argv.c:142 +@deftypefn Extension char** buildargv (char *@var{sp}) + +Given a pointer to a string, parse the string extracting fields +separated by whitespace and optionally enclosed within either single +or double quotes (which are stripped off), and build a vector of +pointers to copies of the string for each field. The input string +remains unchanged. The last element of the vector is followed by a +@code{NULL} element. + +All of the memory for the pointer array and copies of the string +is obtained from @code{malloc}. All of the memory can be returned to the +system with the single function call @code{freeargv}, which takes the +returned result of @code{buildargv}, as it's argument. + +Returns a pointer to the argument vector if successful. Returns +@code{NULL} if @var{sp} is @code{NULL} or if there is insufficient +memory to complete building the argument vector. + +If the input is a null string (as opposed to a @code{NULL} pointer), +then buildarg returns an argument vector that has one arg, a null +string. + +@end deftypefn + +@c bzero.c:6 +@deftypefn Supplemental void bzero (char *@var{mem}, int @var{count}) + +Zeros @var{count} bytes starting at @var{mem}. Use of this function +is deprecated in favor of @code{memset}. + +@end deftypefn + +@c calloc.c:6 +@deftypefn Supplemental void* calloc (size_t @var{nelem}, size_t @var{elsize}) + +Uses @code{malloc} to allocate storage for @var{nelem} objects of +@var{elsize} bytes each, then zeros the memory. + +@end deftypefn + +@c choose-temp.c:46 +@deftypefn Extension char* choose_temp_base (void) + +Return a prefix for temporary file names or @code{NULL} if unable to +find one. The current directory is chosen if all else fails so the +program is exited if a temporary directory can't be found (@code{mktemp} +fails). The buffer for the result is obtained with @code{xmalloc}. + +This function is provided for backwards compatibility only. Its use is +not recommended. + +@end deftypefn + +@c make-temp-file.c:96 +@deftypefn Replacement char* choose_tmpdir () + +Returns a pointer to a directory path suitable for creating temporary +files in. + +@end deftypefn + +@c clock.c:27 +@deftypefn Supplemental long clock (void) + +Returns an approximation of the CPU time used by the process as a +@code{clock_t}; divide this number by @samp{CLOCKS_PER_SEC} to get the +number of seconds used. + +@end deftypefn + +@c concat.c:24 +@deftypefn Extension char* concat (const char *@var{s1}, const char *@var{s2}, @ + @dots{}, @code{NULL}) + +Concatenate zero or more of strings and return the result in freshly +@code{xmalloc}ed memory. Returns @code{NULL} if insufficient memory is +available. The argument list is terminated by the first @code{NULL} +pointer encountered. Pointers to empty strings are ignored. + +@end deftypefn + +@c crc32.c:141 +@deftypefn Extension {unsigned int} crc32 (const unsigned char *@var{buf}, @ + int @var{len}, unsigned int @var{init}) + +Compute the 32-bit CRC of @var{buf} which has length @var{len}. The +starting value is @var{init}; this may be used to compute the CRC of +data split across multiple buffers by passing the return value of each +call as the @var{init} parameter of the next. + +This is intended to match the CRC used by the @command{gdb} remote +protocol for the @samp{qCRC} command. In order to get the same +results as gdb for a block of data, you must pass the first CRC +parameter as @code{0xffffffff}. + +This CRC can be specified as: + + Width : 32 + Poly : 0x04c11db7 + Init : parameter, typically 0xffffffff + RefIn : false + RefOut : false + XorOut : 0 + +This differs from the "standard" CRC-32 algorithm in that the values +are not reflected, and there is no final XOR value. These differences +make it easy to compose the values of multiple blocks. + +@end deftypefn + +@c argv.c:52 +@deftypefn Extension char** dupargv (char **@var{vector}) + +Duplicate an argument vector. Simply scans through @var{vector}, +duplicating each argument until the terminating @code{NULL} is found. +Returns a pointer to the argument vector if successful. Returns +@code{NULL} if there is insufficient memory to complete building the +argument vector. + +@end deftypefn + +@c strerror.c:567 +@deftypefn Extension int errno_max (void) + +Returns the maximum @code{errno} value for which a corresponding +symbolic name or message is available. Note that in the case where we +use the @code{sys_errlist} supplied by the system, it is possible for +there to be more symbolic names than messages, or vice versa. In +fact, the manual page for @code{perror(3C)} explicitly warns that one +should check the size of the table (@code{sys_nerr}) before indexing +it, since new error codes may be added to the system before they are +added to the table. Thus @code{sys_nerr} might be smaller than value +implied by the largest @code{errno} value defined in @code{}. + +We return the maximum value that can be used to obtain a meaningful +symbolic name or message. + +@end deftypefn + +@c argv.c:361 +@deftypefn Extension void expandargv (int *@var{argcp}, char ***@var{argvp}) + +The @var{argcp} and @code{argvp} arguments are pointers to the usual +@code{argc} and @code{argv} arguments to @code{main}. This function +looks for arguments that begin with the character @samp{@@}. Any such +arguments are interpreted as ``response files''. The contents of the +response file are interpreted as additional command line options. In +particular, the file is separated into whitespace-separated strings; +each such string is taken as a command-line option. The new options +are inserted in place of the option naming the response file, and +@code{*argcp} and @code{*argvp} will be updated. If the value of +@code{*argvp} is modified by this function, then the new value has +been dynamically allocated and can be deallocated by the caller with +@code{freeargv}. However, most callers will simply call +@code{expandargv} near the beginning of @code{main} and allow the +operating system to free the memory when the program exits. + +@end deftypefn + +@c fdmatch.c:23 +@deftypefn Extension int fdmatch (int @var{fd1}, int @var{fd2}) + +Check to see if two open file descriptors refer to the same file. +This is useful, for example, when we have an open file descriptor for +an unnamed file, and the name of a file that we believe to correspond +to that fd. This can happen when we are exec'd with an already open +file (@code{stdout} for example) or from the SVR4 @file{/proc} calls +that return open file descriptors for mapped address spaces. All we +have to do is open the file by name and check the two file descriptors +for a match, which is done by comparing major and minor device numbers +and inode numbers. + +@end deftypefn + +@c fopen_unlocked.c:49 +@deftypefn Extension {FILE *} fdopen_unlocked (int @var{fildes}, @ + const char * @var{mode}) + +Opens and returns a @code{FILE} pointer via @code{fdopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +@c ffs.c:3 +@deftypefn Supplemental int ffs (int @var{valu}) + +Find the first (least significant) bit set in @var{valu}. Bits are +numbered from right to left, starting with bit 1 (corresponding to the +value 1). If @var{valu} is zero, zero is returned. + +@end deftypefn + +@c filename_cmp.c:32 +@deftypefn Extension int filename_cmp (const char *@var{s1}, const char *@var{s2}) + +Return zero if the two file names @var{s1} and @var{s2} are equivalent. +If not equivalent, the returned value is similar to what @code{strcmp} +would return. In other words, it returns a negative value if @var{s1} +is less than @var{s2}, or a positive value if @var{s2} is greater than +@var{s2}. + +This function does not normalize file names. As a result, this function +will treat filenames that are spelled differently as different even in +the case when the two filenames point to the same underlying file. +However, it does handle the fact that on DOS-like file systems, forward +and backward slashes are equal. + +@end deftypefn + +@c filename_cmp.c:81 +@deftypefn Extension int filename_ncmp (const char *@var{s1}, const char *@var{s2}, size_t @var{n}) + +Return zero if the two file names @var{s1} and @var{s2} are equivalent +in range @var{n}. +If not equivalent, the returned value is similar to what @code{strncmp} +would return. In other words, it returns a negative value if @var{s1} +is less than @var{s2}, or a positive value if @var{s2} is greater than +@var{s2}. + +This function does not normalize file names. As a result, this function +will treat filenames that are spelled differently as different even in +the case when the two filenames point to the same underlying file. +However, it does handle the fact that on DOS-like file systems, forward +and backward slashes are equal. + +@end deftypefn + +@c fnmatch.txh:1 +@deftypefn Replacement int fnmatch (const char *@var{pattern}, @ + const char *@var{string}, int @var{flags}) + +Matches @var{string} against @var{pattern}, returning zero if it +matches, @code{FNM_NOMATCH} if not. @var{pattern} may contain the +wildcards @code{?} to match any one character, @code{*} to match any +zero or more characters, or a set of alternate characters in square +brackets, like @samp{[a-gt8]}, which match one character (@code{a} +through @code{g}, or @code{t}, or @code{8}, in this example) if that one +character is in the set. A set may be inverted (i.e., match anything +except what's in the set) by giving @code{^} or @code{!} as the first +character in the set. To include those characters in the set, list them +as anything other than the first character of the set. To include a +dash in the set, list it last in the set. A backslash character makes +the following character not special, so for example you could match +against a literal asterisk with @samp{\*}. To match a literal +backslash, use @samp{\\}. + +@code{flags} controls various aspects of the matching process, and is a +boolean OR of zero or more of the following values (defined in +@code{}): + +@table @code + +@item FNM_PATHNAME +@itemx FNM_FILE_NAME +@var{string} is assumed to be a path name. No wildcard will ever match +@code{/}. + +@item FNM_NOESCAPE +Do not interpret backslashes as quoting the following special character. + +@item FNM_PERIOD +A leading period (at the beginning of @var{string}, or if +@code{FNM_PATHNAME} after a slash) is not matched by @code{*} or +@code{?} but must be matched explicitly. + +@item FNM_LEADING_DIR +Means that @var{string} also matches @var{pattern} if some initial part +of @var{string} matches, and is followed by @code{/} and zero or more +characters. For example, @samp{foo*} would match either @samp{foobar} +or @samp{foobar/grill}. + +@item FNM_CASEFOLD +Ignores case when performing the comparison. + +@end table + +@end deftypefn + +@c fopen_unlocked.c:39 +@deftypefn Extension {FILE *} fopen_unlocked (const char *@var{path}, @ + const char * @var{mode}) + +Opens and returns a @code{FILE} pointer via @code{fopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +@c argv.c:97 +@deftypefn Extension void freeargv (char **@var{vector}) + +Free an argument vector that was built using @code{buildargv}. Simply +scans through @var{vector}, freeing the memory for each argument until +the terminating @code{NULL} is found, and then frees @var{vector} +itself. + +@end deftypefn + +@c fopen_unlocked.c:59 +@deftypefn Extension {FILE *} freopen_unlocked (const char * @var{path}, @ + const char * @var{mode}, FILE * @var{stream}) + +Opens and returns a @code{FILE} pointer via @code{freopen}. If the +operating system supports it, ensure that the stream is setup to avoid +any multi-threaded locking. Otherwise return the @code{FILE} pointer +unchanged. + +@end deftypefn + +@c getruntime.c:82 +@deftypefn Replacement long get_run_time (void) + +Returns the time used so far, in microseconds. If possible, this is +the time used by this process, else it is the elapsed time since the +process started. + +@end deftypefn + +@c getcwd.c:6 +@deftypefn Supplemental char* getcwd (char *@var{pathname}, int @var{len}) + +Copy the absolute pathname for the current working directory into +@var{pathname}, which is assumed to point to a buffer of at least +@var{len} bytes, and return a pointer to the buffer. If the current +directory's path doesn't fit in @var{len} characters, the result is +@code{NULL} and @code{errno} is set. If @var{pathname} is a null pointer, +@code{getcwd} will obtain @var{len} bytes of space using +@code{malloc}. + +@end deftypefn + +@c getpagesize.c:5 +@deftypefn Supplemental int getpagesize (void) + +Returns the number of bytes in a page of memory. This is the +granularity of many of the system memory management routines. No +guarantee is made as to whether or not it is the same as the basic +memory management hardware page size. + +@end deftypefn + +@c getpwd.c:5 +@deftypefn Supplemental char* getpwd (void) + +Returns the current working directory. This implementation caches the +result on the assumption that the process will not call @code{chdir} +between calls to @code{getpwd}. + +@end deftypefn + +@c gettimeofday.c:12 +@deftypefn Supplemental int gettimeofday (struct timeval *@var{tp}, void *@var{tz}) + +Writes the current time to @var{tp}. This implementation requires +that @var{tz} be NULL. Returns 0 on success, -1 on failure. + +@end deftypefn + +@c hex.c:33 +@deftypefn Extension void hex_init (void) + +Initializes the array mapping the current character set to +corresponding hex values. This function must be called before any +call to @code{hex_p} or @code{hex_value}. If you fail to call it, a +default ASCII-based table will normally be used on ASCII systems. + +@end deftypefn + +@c hex.c:42 +@deftypefn Extension int hex_p (int @var{c}) + +Evaluates to non-zero if the given character is a valid hex character, +or zero if it is not. Note that the value you pass will be cast to +@code{unsigned char} within the macro. + +@end deftypefn + +@c hex.c:50 +@deftypefn Extension {unsigned int} hex_value (int @var{c}) + +Returns the numeric equivalent of the given character when interpreted +as a hexadecimal digit. The result is undefined if you pass an +invalid hex digit. Note that the value you pass will be cast to +@code{unsigned char} within the macro. + +The @code{hex_value} macro returns @code{unsigned int}, rather than +signed @code{int}, to make it easier to use in parsing addresses from +hex dump files: a signed @code{int} would be sign-extended when +converted to a wider unsigned type --- like @code{bfd_vma}, on some +systems. + +@end deftypefn + +@c safe-ctype.c:25 +@defvr Extension HOST_CHARSET +This macro indicates the basic character set and encoding used by the +host: more precisely, the encoding used for character constants in +preprocessor @samp{#if} statements (the C "execution character set"). +It is defined by @file{safe-ctype.h}, and will be an integer constant +with one of the following values: + +@ftable @code +@item HOST_CHARSET_UNKNOWN +The host character set is unknown - that is, not one of the next two +possibilities. + +@item HOST_CHARSET_ASCII +The host character set is ASCII. + +@item HOST_CHARSET_EBCDIC +The host character set is some variant of EBCDIC. (Only one of the +nineteen EBCDIC varying characters is tested; exercise caution.) +@end ftable +@end defvr + +@c hashtab.c:336 +@deftypefn Supplemental htab_t htab_create_typed_alloc (size_t @var{size}, @ +htab_hash @var{hash_f}, htab_eq @var{eq_f}, htab_del @var{del_f}, @ +htab_alloc @var{alloc_tab_f}, htab_alloc @var{alloc_f}, @ +htab_free @var{free_f}) + +This function creates a hash table that uses two different allocators +@var{alloc_tab_f} and @var{alloc_f} to use for allocating the table itself +and its entries respectively. This is useful when variables of different +types need to be allocated with different allocators. + +The created hash table is slightly larger than @var{size} and it is +initially empty (all the hash table entries are @code{HTAB_EMPTY_ENTRY}). +The function returns the created hash table, or @code{NULL} if memory +allocation fails. + +@end deftypefn + +@c index.c:5 +@deftypefn Supplemental char* index (char *@var{s}, int @var{c}) + +Returns a pointer to the first occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. The use of @code{index} is +deprecated in new programs in favor of @code{strchr}. + +@end deftypefn + +@c insque.c:6 +@deftypefn Supplemental void insque (struct qelem *@var{elem}, @ + struct qelem *@var{pred}) +@deftypefnx Supplemental void remque (struct qelem *@var{elem}) + +Routines to manipulate queues built from doubly linked lists. The +@code{insque} routine inserts @var{elem} in the queue immediately +after @var{pred}. The @code{remque} routine removes @var{elem} from +its containing queue. These routines expect to be passed pointers to +structures which have as their first members a forward pointer and a +back pointer, like this prototype (although no prototype is provided): + +@example +struct qelem @{ + struct qelem *q_forw; + struct qelem *q_back; + char q_data[]; +@}; +@end example + +@end deftypefn + +@c safe-ctype.c:46 +@deffn Extension ISALPHA (@var{c}) +@deffnx Extension ISALNUM (@var{c}) +@deffnx Extension ISBLANK (@var{c}) +@deffnx Extension ISCNTRL (@var{c}) +@deffnx Extension ISDIGIT (@var{c}) +@deffnx Extension ISGRAPH (@var{c}) +@deffnx Extension ISLOWER (@var{c}) +@deffnx Extension ISPRINT (@var{c}) +@deffnx Extension ISPUNCT (@var{c}) +@deffnx Extension ISSPACE (@var{c}) +@deffnx Extension ISUPPER (@var{c}) +@deffnx Extension ISXDIGIT (@var{c}) + +These twelve macros are defined by @file{safe-ctype.h}. Each has the +same meaning as the corresponding macro (with name in lowercase) +defined by the standard header @file{ctype.h}. For example, +@code{ISALPHA} returns true for alphabetic characters and false for +others. However, there are two differences between these macros and +those provided by @file{ctype.h}: + +@itemize @bullet +@item These macros are guaranteed to have well-defined behavior for all +values representable by @code{signed char} and @code{unsigned char}, and +for @code{EOF}. + +@item These macros ignore the current locale; they are true for these +fixed sets of characters: +@multitable {@code{XDIGIT}} {yada yada yada yada yada yada yada yada} +@item @code{ALPHA} @tab @kbd{A-Za-z} +@item @code{ALNUM} @tab @kbd{A-Za-z0-9} +@item @code{BLANK} @tab @kbd{space tab} +@item @code{CNTRL} @tab @code{!PRINT} +@item @code{DIGIT} @tab @kbd{0-9} +@item @code{GRAPH} @tab @code{ALNUM || PUNCT} +@item @code{LOWER} @tab @kbd{a-z} +@item @code{PRINT} @tab @code{GRAPH ||} @kbd{space} +@item @code{PUNCT} @tab @kbd{`~!@@#$%^&*()_-=+[@{]@}\|;:'",<.>/?} +@item @code{SPACE} @tab @kbd{space tab \n \r \f \v} +@item @code{UPPER} @tab @kbd{A-Z} +@item @code{XDIGIT} @tab @kbd{0-9A-Fa-f} +@end multitable + +Note that, if the host character set is ASCII or a superset thereof, +all these macros will return false for all values of @code{char} outside +the range of 7-bit ASCII. In particular, both ISPRINT and ISCNTRL return +false for characters with numeric values from 128 to 255. +@end itemize +@end deffn + +@c safe-ctype.c:95 +@deffn Extension ISIDNUM (@var{c}) +@deffnx Extension ISIDST (@var{c}) +@deffnx Extension IS_VSPACE (@var{c}) +@deffnx Extension IS_NVSPACE (@var{c}) +@deffnx Extension IS_SPACE_OR_NUL (@var{c}) +@deffnx Extension IS_ISOBASIC (@var{c}) +These six macros are defined by @file{safe-ctype.h} and provide +additional character classes which are useful when doing lexical +analysis of C or similar languages. They are true for the following +sets of characters: + +@multitable {@code{SPACE_OR_NUL}} {yada yada yada yada yada yada yada yada} +@item @code{IDNUM} @tab @kbd{A-Za-z0-9_} +@item @code{IDST} @tab @kbd{A-Za-z_} +@item @code{VSPACE} @tab @kbd{\r \n} +@item @code{NVSPACE} @tab @kbd{space tab \f \v \0} +@item @code{SPACE_OR_NUL} @tab @code{VSPACE || NVSPACE} +@item @code{ISOBASIC} @tab @code{VSPACE || NVSPACE || PRINT} +@end multitable +@end deffn + +@c lbasename.c:23 +@deftypefn Replacement {const char*} lbasename (const char *@var{name}) + +Given a pointer to a string containing a typical pathname +(@samp{/usr/src/cmd/ls/ls.c} for example), returns a pointer to the +last component of the pathname (@samp{ls.c} in this case). The +returned pointer is guaranteed to lie within the original +string. This latter fact is not true of many vendor C +libraries, which return special strings or modify the passed +strings for particular input. + +In particular, the empty string returns the same empty string, +and a path ending in @code{/} returns the empty string after it. + +@end deftypefn + +@c lrealpath.c:25 +@deftypefn Replacement {const char*} lrealpath (const char *@var{name}) + +Given a pointer to a string containing a pathname, returns a canonical +version of the filename. Symlinks will be resolved, and ``.'' and ``..'' +components will be simplified. The returned value will be allocated using +@code{malloc}, or @code{NULL} will be returned on a memory allocation error. + +@end deftypefn + +@c make-relative-prefix.c:24 +@deftypefn Extension {const char*} make_relative_prefix (const char *@var{progname}, @ + const char *@var{bin_prefix}, const char *@var{prefix}) + +Given three paths @var{progname}, @var{bin_prefix}, @var{prefix}, +return the path that is in the same position relative to +@var{progname}'s directory as @var{prefix} is relative to +@var{bin_prefix}. That is, a string starting with the directory +portion of @var{progname}, followed by a relative pathname of the +difference between @var{bin_prefix} and @var{prefix}. + +If @var{progname} does not contain any directory separators, +@code{make_relative_prefix} will search @env{PATH} to find a program +named @var{progname}. Also, if @var{progname} is a symbolic link, +the symbolic link will be resolved. + +For example, if @var{bin_prefix} is @code{/alpha/beta/gamma/gcc/delta}, +@var{prefix} is @code{/alpha/beta/gamma/omega/}, and @var{progname} is +@code{/red/green/blue/gcc}, then this function will return +@code{/red/green/blue/../../omega/}. + +The return value is normally allocated via @code{malloc}. If no +relative prefix can be found, return @code{NULL}. + +@end deftypefn + +@c make-temp-file.c:174 +@deftypefn Replacement char* make_temp_file (const char *@var{suffix}) + +Return a temporary file name (as a string) or @code{NULL} if unable to +create one. @var{suffix} is a suffix to append to the file name. The +string is @code{malloc}ed, and the temporary file has been created. + +@end deftypefn + +@c memchr.c:3 +@deftypefn Supplemental void* memchr (const void *@var{s}, int @var{c}, @ + size_t @var{n}) + +This function searches memory starting at @code{*@var{s}} for the +character @var{c}. The search only ends with the first occurrence of +@var{c}, or after @var{length} characters; in particular, a null +character does not terminate the search. If the character @var{c} is +found within @var{length} characters of @code{*@var{s}}, a pointer +to the character is returned. If @var{c} is not found, then @code{NULL} is +returned. + +@end deftypefn + +@c memcmp.c:6 +@deftypefn Supplemental int memcmp (const void *@var{x}, const void *@var{y}, @ + size_t @var{count}) + +Compares the first @var{count} bytes of two areas of memory. Returns +zero if they are the same, a value less than zero if @var{x} is +lexically less than @var{y}, or a value greater than zero if @var{x} +is lexically greater than @var{y}. Note that lexical order is determined +as if comparing unsigned char arrays. + +@end deftypefn + +@c memcpy.c:6 +@deftypefn Supplemental void* memcpy (void *@var{out}, const void *@var{in}, @ + size_t @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. Returns a pointer to @var{out}. + +@end deftypefn + +@c memmem.c:20 +@deftypefn Supplemental void* memmem (const void *@var{haystack}, @ + size_t @var{haystack_len} const void *@var{needle}, size_t @var{needle_len}) + +Returns a pointer to the first occurrence of @var{needle} (length +@var{needle_len}) in @var{haystack} (length @var{haystack_len}). +Returns @code{NULL} if not found. + +@end deftypefn + +@c memmove.c:6 +@deftypefn Supplemental void* memmove (void *@var{from}, const void *@var{to}, @ + size_t @var{count}) + +Copies @var{count} bytes from memory area @var{from} to memory area +@var{to}, returning a pointer to @var{to}. + +@end deftypefn + +@c mempcpy.c:23 +@deftypefn Supplemental void* mempcpy (void *@var{out}, const void *@var{in}, @ + size_t @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. Returns a pointer to @var{out} + @var{length}. + +@end deftypefn + +@c memset.c:6 +@deftypefn Supplemental void* memset (void *@var{s}, int @var{c}, @ + size_t @var{count}) + +Sets the first @var{count} bytes of @var{s} to the constant byte +@var{c}, returning a pointer to @var{s}. + +@end deftypefn + +@c mkstemps.c:58 +@deftypefn Replacement int mkstemps (char *@var{pattern}, int @var{suffix_len}) + +Generate a unique temporary file name from @var{pattern}. +@var{pattern} has the form: + +@example + @var{path}/ccXXXXXX@var{suffix} +@end example + +@var{suffix_len} tells us how long @var{suffix} is (it can be zero +length). The last six characters of @var{pattern} before @var{suffix} +must be @samp{XXXXXX}; they are replaced with a string that makes the +filename unique. Returns a file descriptor open on the file for +reading and writing. + +@end deftypefn + +@c pexecute.txh:278 +@deftypefn Extension void pex_free (struct pex_obj @var{obj}) + +Clean up and free all data associated with @var{obj}. If you have not +yet called @code{pex_get_times} or @code{pex_get_status}, this will +try to kill the subprocesses. + +@end deftypefn + +@c pexecute.txh:251 +@deftypefn Extension int pex_get_status (struct pex_obj *@var{obj}, @ + int @var{count}, int *@var{vector}) + +Returns the exit status of all programs run using @var{obj}. +@var{count} is the number of results expected. The results will be +placed into @var{vector}. The results are in the order of the calls +to @code{pex_run}. Returns 0 on error, 1 on success. + +@end deftypefn + +@c pexecute.txh:261 +@deftypefn Extension int pex_get_times (struct pex_obj *@var{obj}, @ + int @var{count}, struct pex_time *@var{vector}) + +Returns the process execution times of all programs run using +@var{obj}. @var{count} is the number of results expected. The +results will be placed into @var{vector}. The results are in the +order of the calls to @code{pex_run}. Returns 0 on error, 1 on +success. + +@code{struct pex_time} has the following fields of the type +@code{unsigned long}: @code{user_seconds}, +@code{user_microseconds}, @code{system_seconds}, +@code{system_microseconds}. On systems which do not support reporting +process times, all the fields will be set to @code{0}. + +@end deftypefn + +@c pexecute.txh:2 +@deftypefn Extension {struct pex_obj *} pex_init (int @var{flags}, @ + const char *@var{pname}, const char *@var{tempbase}) + +Prepare to execute one or more programs, with standard output of each +program fed to standard input of the next. This is a system +independent interface to execute a pipeline. + +@var{flags} is a bitwise combination of the following: + +@table @code + +@vindex PEX_RECORD_TIMES +@item PEX_RECORD_TIMES +Record subprocess times if possible. + +@vindex PEX_USE_PIPES +@item PEX_USE_PIPES +Use pipes for communication between processes, if possible. + +@vindex PEX_SAVE_TEMPS +@item PEX_SAVE_TEMPS +Don't delete temporary files used for communication between +processes. + +@end table + +@var{pname} is the name of program to be executed, used in error +messages. @var{tempbase} is a base name to use for any required +temporary files; it may be @code{NULL} to use a randomly chosen name. + +@end deftypefn + +@c pexecute.txh:161 +@deftypefn Extension {FILE *} pex_input_file (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{in_name}) + +Return a stream for a temporary file to pass to the first program in +the pipeline as input. + +The name of the input file is chosen according to the same rules +@code{pex_run} uses to choose output file names, based on +@var{in_name}, @var{obj} and the @code{PEX_SUFFIX} bit in @var{flags}. + +Don't call @code{fclose} on the returned stream; the first call to +@code{pex_run} closes it automatically. + +If @var{flags} includes @code{PEX_BINARY_OUTPUT}, open the stream in +binary mode; otherwise, open it in the default mode. Including +@code{PEX_BINARY_OUTPUT} in @var{flags} has no effect on Unix. +@end deftypefn + +@c pexecute.txh:179 +@deftypefn Extension {FILE *} pex_input_pipe (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Return a stream @var{fp} for a pipe connected to the standard input of +the first program in the pipeline; @var{fp} is opened for writing. +You must have passed @code{PEX_USE_PIPES} to the @code{pex_init} call +that returned @var{obj}. + +You must close @var{fp} using @code{fclose} yourself when you have +finished writing data to the pipeline. + +The file descriptor underlying @var{fp} is marked not to be inherited +by child processes. + +On systems that do not support pipes, this function returns +@code{NULL}, and sets @code{errno} to @code{EINVAL}. If you would +like to write code that is portable to all systems the @code{pex} +functions support, consider using @code{pex_input_file} instead. + +There are two opportunities for deadlock using +@code{pex_input_pipe}: + +@itemize @bullet +@item +Most systems' pipes can buffer only a fixed amount of data; a process +that writes to a full pipe blocks. Thus, if you write to @file{fp} +before starting the first process, you run the risk of blocking when +there is no child process yet to read the data and allow you to +continue. @code{pex_input_pipe} makes no promises about the +size of the pipe's buffer, so if you need to write any data at all +before starting the first process in the pipeline, consider using +@code{pex_input_file} instead. + +@item +Using @code{pex_input_pipe} and @code{pex_read_output} together +may also cause deadlock. If the output pipe fills up, so that each +program in the pipeline is waiting for the next to read more data, and +you fill the input pipe by writing more data to @var{fp}, then there +is no way to make progress: the only process that could read data from +the output pipe is you, but you are blocked on the input pipe. + +@end itemize + +@end deftypefn + +@c pexecute.txh:286 +@deftypefn Extension {const char *} pex_one (int @var{flags}, @ + const char *@var{executable}, char * const *@var{argv}, @ + const char *@var{pname}, const char *@var{outname}, const char *@var{errname}, @ + int *@var{status}, int *@var{err}) + +An interface to permit the easy execution of a +single program. The return value and most of the parameters are as +for a call to @code{pex_run}. @var{flags} is restricted to a +combination of @code{PEX_SEARCH}, @code{PEX_STDERR_TO_STDOUT}, and +@code{PEX_BINARY_OUTPUT}. @var{outname} is interpreted as if +@code{PEX_LAST} were set. On a successful return, @code{*@var{status}} will +be set to the exit status of the program. + +@end deftypefn + +@c pexecute.txh:237 +@deftypefn Extension {FILE *} pex_read_err (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Returns a @code{FILE} pointer which may be used to read the standard +error of the last program in the pipeline. When this is used, +@code{PEX_LAST} should not be used in a call to @code{pex_run}. After +this is called, @code{pex_run} may no longer be called with the same +@var{obj}. @var{binary} should be non-zero if the file should be +opened in binary mode. Don't call @code{fclose} on the returned file; +it will be closed by @code{pex_free}. + +@end deftypefn + +@c pexecute.txh:224 +@deftypefn Extension {FILE *} pex_read_output (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Returns a @code{FILE} pointer which may be used to read the standard +output of the last program in the pipeline. When this is used, +@code{PEX_LAST} should not be used in a call to @code{pex_run}. After +this is called, @code{pex_run} may no longer be called with the same +@var{obj}. @var{binary} should be non-zero if the file should be +opened in binary mode. Don't call @code{fclose} on the returned file; +it will be closed by @code{pex_free}. + +@end deftypefn + +@c pexecute.txh:34 +@deftypefn Extension {const char *} pex_run (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{executable}, char * const *@var{argv}, @ + const char *@var{outname}, const char *@var{errname}, int *@var{err}) + +Execute one program in a pipeline. On success this returns +@code{NULL}. On failure it returns an error message, a statically +allocated string. + +@var{obj} is returned by a previous call to @code{pex_init}. + +@var{flags} is a bitwise combination of the following: + +@table @code + +@vindex PEX_LAST +@item PEX_LAST +This must be set on the last program in the pipeline. In particular, +it should be set when executing a single program. The standard output +of the program will be sent to @var{outname}, or, if @var{outname} is +@code{NULL}, to the standard output of the calling program. Do @emph{not} +set this bit if you want to call @code{pex_read_output} +(described below). After a call to @code{pex_run} with this bit set, +@var{pex_run} may no longer be called with the same @var{obj}. + +@vindex PEX_SEARCH +@item PEX_SEARCH +Search for the program using the user's executable search path. + +@vindex PEX_SUFFIX +@item PEX_SUFFIX +@var{outname} is a suffix. See the description of @var{outname}, +below. + +@vindex PEX_STDERR_TO_STDOUT +@item PEX_STDERR_TO_STDOUT +Send the program's standard error to standard output, if possible. + +@vindex PEX_BINARY_INPUT +@vindex PEX_BINARY_OUTPUT +@vindex PEX_BINARY_ERROR +@item PEX_BINARY_INPUT +@itemx PEX_BINARY_OUTPUT +@itemx PEX_BINARY_ERROR +The standard input (output or error) of the program should be read (written) in +binary mode rather than text mode. These flags are ignored on systems +which do not distinguish binary mode and text mode, such as Unix. For +proper behavior these flags should match appropriately---a call to +@code{pex_run} using @code{PEX_BINARY_OUTPUT} should be followed by a +call using @code{PEX_BINARY_INPUT}. + +@vindex PEX_STDERR_TO_PIPE +@item PEX_STDERR_TO_PIPE +Send the program's standard error to a pipe, if possible. This flag +cannot be specified together with @code{PEX_STDERR_TO_STDOUT}. This +flag can be specified only on the last program in pipeline. + +@end table + +@var{executable} is the program to execute. @var{argv} is the set of +arguments to pass to the program; normally @code{@var{argv}[0]} will +be a copy of @var{executable}. + +@var{outname} is used to set the name of the file to use for standard +output. There are two cases in which no output file will be used: + +@enumerate +@item +if @code{PEX_LAST} is not set in @var{flags}, and @code{PEX_USE_PIPES} +was set in the call to @code{pex_init}, and the system supports pipes + +@item +if @code{PEX_LAST} is set in @var{flags}, and @var{outname} is +@code{NULL} +@end enumerate + +@noindent +Otherwise the code will use a file to hold standard +output. If @code{PEX_LAST} is not set, this file is considered to be +a temporary file, and it will be removed when no longer needed, unless +@code{PEX_SAVE_TEMPS} was set in the call to @code{pex_init}. + +There are two cases to consider when setting the name of the file to +hold standard output. + +@enumerate +@item +@code{PEX_SUFFIX} is set in @var{flags}. In this case +@var{outname} may not be @code{NULL}. If the @var{tempbase} parameter +to @code{pex_init} was not @code{NULL}, then the output file name is +the concatenation of @var{tempbase} and @var{outname}. If +@var{tempbase} was @code{NULL}, then the output file name is a random +file name ending in @var{outname}. + +@item +@code{PEX_SUFFIX} was not set in @var{flags}. In this +case, if @var{outname} is not @code{NULL}, it is used as the output +file name. If @var{outname} is @code{NULL}, and @var{tempbase} was +not NULL, the output file name is randomly chosen using +@var{tempbase}. Otherwise the output file name is chosen completely +at random. +@end enumerate + +@var{errname} is the file name to use for standard error output. If +it is @code{NULL}, standard error is the same as the caller's. +Otherwise, standard error is written to the named file. + +On an error return, the code sets @code{*@var{err}} to an @code{errno} +value, or to 0 if there is no relevant @code{errno}. + +@end deftypefn + +@c pexecute.txh:145 +@deftypefn Extension {const char *} pex_run_in_environment (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{executable}, char * const *@var{argv}, @ + char * const *@var{env}, int @var{env_size}, const char *@var{outname}, @ + const char *@var{errname}, int *@var{err}) + +Execute one program in a pipeline, permitting the environment for the +program to be specified. Behaviour and parameters not listed below are +as for @code{pex_run}. + +@var{env} is the environment for the child process, specified as an array of +character pointers. Each element of the array should point to a string of the +form @code{VAR=VALUE}, with the exception of the last element that must be +@code{NULL}. + +@end deftypefn + +@c pexecute.txh:301 +@deftypefn Extension int pexecute (const char *@var{program}, @ + char * const *@var{argv}, const char *@var{this_pname}, @ + const char *@var{temp_base}, char **@var{errmsg_fmt}, @ + char **@var{errmsg_arg}, int @var{flags}) + +This is the old interface to execute one or more programs. It is +still supported for compatibility purposes, but is no longer +documented. + +@end deftypefn + +@c strsignal.c:541 +@deftypefn Supplemental void psignal (int @var{signo}, char *@var{message}) + +Print @var{message} to the standard error, followed by a colon, +followed by the description of the signal specified by @var{signo}, +followed by a newline. + +@end deftypefn + +@c putenv.c:21 +@deftypefn Supplemental int putenv (const char *@var{string}) + +Uses @code{setenv} or @code{unsetenv} to put @var{string} into +the environment or remove it. If @var{string} is of the form +@samp{name=value} the string is added; if no @samp{=} is present the +name is unset/removed. + +@end deftypefn + +@c pexecute.txh:312 +@deftypefn Extension int pwait (int @var{pid}, int *@var{status}, int @var{flags}) + +Another part of the old execution interface. + +@end deftypefn + +@c random.c:39 +@deftypefn Supplement {long int} random (void) +@deftypefnx Supplement void srandom (unsigned int @var{seed}) +@deftypefnx Supplement void* initstate (unsigned int @var{seed}, @ + void *@var{arg_state}, unsigned long @var{n}) +@deftypefnx Supplement void* setstate (void *@var{arg_state}) + +Random number functions. @code{random} returns a random number in the +range 0 to @code{LONG_MAX}. @code{srandom} initializes the random +number generator to some starting point determined by @var{seed} +(else, the values returned by @code{random} are always the same for each +run of the program). @code{initstate} and @code{setstate} allow fine-grained +control over the state of the random number generator. + +@end deftypefn + +@c concat.c:174 +@deftypefn Extension char* reconcat (char *@var{optr}, const char *@var{s1}, @ + @dots{}, @code{NULL}) + +Same as @code{concat}, except that if @var{optr} is not @code{NULL} it +is freed after the string is created. This is intended to be useful +when you're extending an existing string or building up a string in a +loop: + +@example + str = reconcat (str, "pre-", str, NULL); +@end example + +@end deftypefn + +@c rename.c:6 +@deftypefn Supplemental int rename (const char *@var{old}, const char *@var{new}) + +Renames a file from @var{old} to @var{new}. If @var{new} already +exists, it is removed. + +@end deftypefn + +@c rindex.c:5 +@deftypefn Supplemental char* rindex (const char *@var{s}, int @var{c}) + +Returns a pointer to the last occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. The use of @code{rindex} is +deprecated in new programs in favor of @code{strrchr}. + +@end deftypefn + +@c setenv.c:23 +@deftypefn Supplemental int setenv (const char *@var{name}, @ + const char *@var{value}, int @var{overwrite}) +@deftypefnx Supplemental void unsetenv (const char *@var{name}) + +@code{setenv} adds @var{name} to the environment with value +@var{value}. If the name was already present in the environment, +the new value will be stored only if @var{overwrite} is nonzero. +The companion @code{unsetenv} function removes @var{name} from the +environment. This implementation is not safe for multithreaded code. + +@end deftypefn + +@c setproctitle.c:31 +@deftypefn Supplemental void setproctitle (const char *@var{fmt}, ...) + +Set the title of a process to @var{fmt}. va args not supported for now, +but defined for compatibility with BSD. + +@end deftypefn + +@c strsignal.c:348 +@deftypefn Extension int signo_max (void) + +Returns the maximum signal value for which a corresponding symbolic +name or message is available. Note that in the case where we use the +@code{sys_siglist} supplied by the system, it is possible for there to +be more symbolic names than messages, or vice versa. In fact, the +manual page for @code{psignal(3b)} explicitly warns that one should +check the size of the table (@code{NSIG}) before indexing it, since +new signal codes may be added to the system before they are added to +the table. Thus @code{NSIG} might be smaller than value implied by +the largest signo value defined in @code{}. + +We return the maximum value that can be used to obtain a meaningful +symbolic name or message. + +@end deftypefn + +@c sigsetmask.c:8 +@deftypefn Supplemental int sigsetmask (int @var{set}) + +Sets the signal mask to the one provided in @var{set} and returns +the old mask (which, for libiberty's implementation, will always +be the value @code{1}). + +@end deftypefn + +@c simple-object.txh:96 +@deftypefn Extension {const char *} simple_object_attributes_compare @ + (simple_object_attributes *@var{attrs1}, simple_object_attributes *@var{attrs2}, @ + int *@var{err}) + +Compare @var{attrs1} and @var{attrs2}. If they could be linked +together without error, return @code{NULL}. Otherwise, return an +error message and set @code{*@var{err}} to an errno value or @code{0} +if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:81 +@deftypefn Extension {simple_object_attributes *} simple_object_fetch_attributes @ + (simple_object_read *@var{simple_object}, const char **@var{errmsg}, int *@var{err}) + +Fetch the attributes of @var{simple_object}. The attributes are +internal information such as the format of the object file, or the +architecture it was compiled for. This information will persist until +@code{simple_object_attributes_release} is called, even if +@var{simple_object} itself is released. + +On error this returns @code{NULL}, sets @code{*@var{errmsg}} to an +error message, and sets @code{*@var{err}} to an errno value or +@code{0} if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:49 +@deftypefn Extension {int} simple_object_find_section @ + (simple_object_read *@var{simple_object} off_t *@var{offset}, @ + off_t *@var{length}, const char **@var{errmsg}, int *@var{err}) + +Look for the section @var{name} in @var{simple_object}. This returns +information for the first section with that name. + +If found, return 1 and set @code{*@var{offset}} to the offset in the +file of the section contents and set @code{*@var{length}} to the +length of the section contents. The value in @code{*@var{offset}} +will be relative to the offset passed to +@code{simple_object_open_read}. + +If the section is not found, and no error occurs, +@code{simple_object_find_section} returns @code{0} and set +@code{*@var{errmsg}} to @code{NULL}. + +If an error occurs, @code{simple_object_find_section} returns +@code{0}, sets @code{*@var{errmsg}} to an error message, and sets +@code{*@var{err}} to an errno value or @code{0} if there is no +relevant errno. + +@end deftypefn + +@c simple-object.txh:27 +@deftypefn Extension {const char *} simple_object_find_sections @ + (simple_object_read *@var{simple_object}, int (*@var{pfn}) (void *@var{data}, @ + const char *@var{name}, off_t @var{offset}, off_t @var{length}), @ + void *@var{data}, int *@var{err}) + +This function calls @var{pfn} for each section in @var{simple_object}. +It calls @var{pfn} with the section name, the offset within the file +of the section contents, and the length of the section contents. The +offset within the file is relative to the offset passed to +@code{simple_object_open_read}. The @var{data} argument to this +function is passed along to @var{pfn}. + +If @var{pfn} returns @code{0}, the loop over the sections stops and +@code{simple_object_find_sections} returns. If @var{pfn} returns some +other value, the loop continues. + +On success @code{simple_object_find_sections} returns. On error it +returns an error string, and sets @code{*@var{err}} to an errno value +or @code{0} if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:2 +@deftypefn Extension {simple_object_read *} simple_object_open_read @ + (int @var{descriptor}, off_t @var{offset}, const char *{segment_name}, @ + const char **@var{errmsg}, int *@var{err}) + +Opens an object file for reading. Creates and returns an +@code{simple_object_read} pointer which may be passed to other +functions to extract data from the object file. + +@var{descriptor} holds a file descriptor which permits reading. + +@var{offset} is the offset into the file; this will be @code{0} in the +normal case, but may be a different value when reading an object file +in an archive file. + +@var{segment_name} is only used with the Mach-O file format used on +Darwin aka Mac OS X. It is required on that platform, and means to +only look at sections within the segment with that name. The +parameter is ignored on other systems. + +If an error occurs, this functions returns @code{NULL} and sets +@code{*@var{errmsg}} to an error string and sets @code{*@var{err}} to +an errno value or @code{0} if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:107 +@deftypefn Extension {void} simple_object_release_attributes @ + (simple_object_attributes *@var{attrs}) + +Release all resources associated with @var{attrs}. + +@end deftypefn + +@c simple-object.txh:73 +@deftypefn Extension {void} simple_object_release_read @ + (simple_object_read *@var{simple_object}) + +Release all resources associated with @var{simple_object}. This does +not close the file descriptor. + +@end deftypefn + +@c simple-object.txh:184 +@deftypefn Extension {void} simple_object_release_write @ + (simple_object_write *@var{simple_object}) + +Release all resources associated with @var{simple_object}. + +@end deftypefn + +@c simple-object.txh:114 +@deftypefn Extension {simple_object_write *} simple_object_start_write @ + (simple_object_attributes @var{attrs}, const char *@var{segment_name}, @ + const char **@var{errmsg}, int *@var{err}) + +Start creating a new object file using the object file format +described in @var{attrs}. You must fetch attribute information from +an existing object file before you can create a new one. There is +currently no support for creating an object file de novo. + +@var{segment_name} is only used with Mach-O as found on Darwin aka Mac +OS X. The parameter is required on that target. It means that all +sections are created within the named segment. It is ignored for +other object file formats. + +On error @code{simple_object_start_write} returns @code{NULL}, sets +@code{*@var{ERRMSG}} to an error message, and sets @code{*@var{err}} +to an errno value or @code{0} if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:153 +@deftypefn Extension {const char *} simple_object_write_add_data @ + (simple_object_write *@var{simple_object}, @ + simple_object_write_section *@var{section}, const void *@var{buffer}, @ + size_t @var{size}, int @var{copy}, int *@var{err}) + +Add data @var{buffer}/@var{size} to @var{section} in +@var{simple_object}. If @var{copy} is non-zero, the data will be +copied into memory if necessary. If @var{copy} is zero, @var{buffer} +must persist until @code{simple_object_write_to_file} is called. is +released. + +On success this returns @code{NULL}. On error this returns an error +message, and sets @code{*@var{err}} to an errno value or 0 if there is +no relevant erro. + +@end deftypefn + +@c simple-object.txh:134 +@deftypefn Extension {simple_object_write_section *} simple_object_write_create_section @ + (simple_object_write *@var{simple_object}, const char *@var{name}, @ + unsigned int @var{align}, const char **@var{errmsg}, int *@var{err}) + +Add a section to @var{simple_object}. @var{name} is the name of the +new section. @var{align} is the required alignment expressed as the +number of required low-order 0 bits (e.g., 2 for alignment to a 32-bit +boundary). + +The section is created as containing data, readable, not writable, not +executable, not loaded at runtime. The section is not written to the +file until @code{simple_object_write_to_file} is called. + +On error this returns @code{NULL}, sets @code{*@var{errmsg}} to an +error message, and sets @code{*@var{err}} to an errno value or +@code{0} if there is no relevant errno. + +@end deftypefn + +@c simple-object.txh:170 +@deftypefn Extension {const char *} simple_object_write_to_file @ + (simple_object_write *@var{simple_object}, int @var{descriptor}, int *@var{err}) + +Write the complete object file to @var{descriptor}, an open file +descriptor. This writes out all the data accumulated by calls to +@code{simple_object_write_create_section} and +@var{simple_object_write_add_data}. + +This returns @code{NULL} on success. On error this returns an error +message and sets @code{*@var{err}} to an errno value or @code{0} if +there is no relevant errno. + +@end deftypefn + +@c snprintf.c:28 +@deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, @ + const char *@var{format}, ...) + +This function is similar to @code{sprintf}, but it will write to +@var{buf} at most @code{@var{n}-1} bytes of text, followed by a +terminating null byte, for a total of @var{n} bytes. +On error the return value is -1, otherwise it returns the number of +bytes, not including the terminating null byte, that would have been +written had @var{n} been sufficiently large, regardless of the actual +value of @var{n}. Note some pre-C99 system libraries do not implement +this correctly so users cannot generally rely on the return value if +the system version of this function is used. + +@end deftypefn + +@c spaces.c:22 +@deftypefn Extension char* spaces (int @var{count}) + +Returns a pointer to a memory region filled with the specified +number of spaces and null terminated. The returned pointer is +valid until at least the next call. + +@end deftypefn + +@c splay-tree.c:303 +@deftypefn Supplemental splay_tree splay_tree_new_with_typed_alloc @ +(splay_tree_compare_fn @var{compare_fn}, @ +splay_tree_delete_key_fn @var{delete_key_fn}, @ +splay_tree_delete_value_fn @var{delete_value_fn}, @ +splay_tree_allocate_fn @var{tree_allocate_fn}, @ +splay_tree_allocate_fn @var{node_allocate_fn}, @ +splay_tree_deallocate_fn @var{deallocate_fn}, @ +void * @var{allocate_data}) + +This function creates a splay tree that uses two different allocators +@var{tree_allocate_fn} and @var{node_allocate_fn} to use for allocating the +tree itself and its nodes respectively. This is useful when variables of +different types need to be allocated with different allocators. + +The splay tree will use @var{compare_fn} to compare nodes, +@var{delete_key_fn} to deallocate keys, and @var{delete_value_fn} to +deallocate values. + +@end deftypefn + +@c stpcpy.c:23 +@deftypefn Supplemental char* stpcpy (char *@var{dst}, const char *@var{src}) + +Copies the string @var{src} into @var{dst}. Returns a pointer to +@var{dst} + strlen(@var{src}). + +@end deftypefn + +@c stpncpy.c:23 +@deftypefn Supplemental char* stpncpy (char *@var{dst}, const char *@var{src}, @ + size_t @var{len}) + +Copies the string @var{src} into @var{dst}, copying exactly @var{len} +and padding with zeros if necessary. If @var{len} < strlen(@var{src}) +then return @var{dst} + @var{len}, otherwise returns @var{dst} + +strlen(@var{src}). + +@end deftypefn + +@c strcasecmp.c:15 +@deftypefn Supplemental int strcasecmp (const char *@var{s1}, const char *@var{s2}) + +A case-insensitive @code{strcmp}. + +@end deftypefn + +@c strchr.c:6 +@deftypefn Supplemental char* strchr (const char *@var{s}, int @var{c}) + +Returns a pointer to the first occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. If @var{c} is itself the +null character, the results are undefined. + +@end deftypefn + +@c strdup.c:3 +@deftypefn Supplemental char* strdup (const char *@var{s}) + +Returns a pointer to a copy of @var{s} in memory obtained from +@code{malloc}, or @code{NULL} if insufficient memory was available. + +@end deftypefn + +@c strerror.c:670 +@deftypefn Replacement {const char*} strerrno (int @var{errnum}) + +Given an error number returned from a system call (typically returned +in @code{errno}), returns a pointer to a string containing the +symbolic name of that error number, as found in @code{}. + +If the supplied error number is within the valid range of indices for +symbolic names, but no name is available for the particular error +number, then returns the string @samp{Error @var{num}}, where @var{num} +is the error number. + +If the supplied error number is not within the range of valid +indices, then returns @code{NULL}. + +The contents of the location pointed to are only guaranteed to be +valid until the next call to @code{strerrno}. + +@end deftypefn + +@c strerror.c:603 +@deftypefn Supplemental char* strerror (int @var{errnoval}) + +Maps an @code{errno} number to an error message string, the contents +of which are implementation defined. On systems which have the +external variables @code{sys_nerr} and @code{sys_errlist}, these +strings will be the same as the ones used by @code{perror}. + +If the supplied error number is within the valid range of indices for +the @code{sys_errlist}, but no message is available for the particular +error number, then returns the string @samp{Error @var{num}}, where +@var{num} is the error number. + +If the supplied error number is not a valid index into +@code{sys_errlist}, returns @code{NULL}. + +The returned string is only guaranteed to be valid only until the +next call to @code{strerror}. + +@end deftypefn + +@c strncasecmp.c:15 +@deftypefn Supplemental int strncasecmp (const char *@var{s1}, const char *@var{s2}) + +A case-insensitive @code{strncmp}. + +@end deftypefn + +@c strncmp.c:6 +@deftypefn Supplemental int strncmp (const char *@var{s1}, @ + const char *@var{s2}, size_t @var{n}) + +Compares the first @var{n} bytes of two strings, returning a value as +@code{strcmp}. + +@end deftypefn + +@c strndup.c:23 +@deftypefn Extension char* strndup (const char *@var{s}, size_t @var{n}) + +Returns a pointer to a copy of @var{s} with at most @var{n} characters +in memory obtained from @code{malloc}, or @code{NULL} if insufficient +memory was available. The result is always NUL terminated. + +@end deftypefn + +@c strrchr.c:6 +@deftypefn Supplemental char* strrchr (const char *@var{s}, int @var{c}) + +Returns a pointer to the last occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. If @var{c} is itself the +null character, the results are undefined. + +@end deftypefn + +@c strsignal.c:383 +@deftypefn Supplemental {const char *} strsignal (int @var{signo}) + +Maps an signal number to an signal message string, the contents of +which are implementation defined. On systems which have the external +variable @code{sys_siglist}, these strings will be the same as the +ones used by @code{psignal()}. + +If the supplied signal number is within the valid range of indices for +the @code{sys_siglist}, but no message is available for the particular +signal number, then returns the string @samp{Signal @var{num}}, where +@var{num} is the signal number. + +If the supplied signal number is not a valid index into +@code{sys_siglist}, returns @code{NULL}. + +The returned string is only guaranteed to be valid only until the next +call to @code{strsignal}. + +@end deftypefn + +@c strsignal.c:448 +@deftypefn Extension {const char*} strsigno (int @var{signo}) + +Given an signal number, returns a pointer to a string containing the +symbolic name of that signal number, as found in @code{}. + +If the supplied signal number is within the valid range of indices for +symbolic names, but no name is available for the particular signal +number, then returns the string @samp{Signal @var{num}}, where +@var{num} is the signal number. + +If the supplied signal number is not within the range of valid +indices, then returns @code{NULL}. + +The contents of the location pointed to are only guaranteed to be +valid until the next call to @code{strsigno}. + +@end deftypefn + +@c strstr.c:6 +@deftypefn Supplemental char* strstr (const char *@var{string}, const char *@var{sub}) + +This function searches for the substring @var{sub} in the string +@var{string}, not including the terminating null characters. A pointer +to the first occurrence of @var{sub} is returned, or @code{NULL} if the +substring is absent. If @var{sub} points to a string with zero +length, the function returns @var{string}. + +@end deftypefn + +@c strtod.c:27 +@deftypefn Supplemental double strtod (const char *@var{string}, @ + char **@var{endptr}) + +This ISO C function converts the initial portion of @var{string} to a +@code{double}. If @var{endptr} is not @code{NULL}, a pointer to the +character after the last character used in the conversion is stored in +the location referenced by @var{endptr}. If no conversion is +performed, zero is returned and the value of @var{string} is stored in +the location referenced by @var{endptr}. + +@end deftypefn + +@c strerror.c:729 +@deftypefn Extension int strtoerrno (const char *@var{name}) + +Given the symbolic name of a error number (e.g., @code{EACCES}), map it +to an errno value. If no translation is found, returns 0. + +@end deftypefn + +@c strtol.c:33 +@deftypefn Supplemental {long int} strtol (const char *@var{string}, @ + char **@var{endptr}, int @var{base}) +@deftypefnx Supplemental {unsigned long int} strtoul (const char *@var{string}, @ + char **@var{endptr}, int @var{base}) + +The @code{strtol} function converts the string in @var{string} to a +long integer value according to the given @var{base}, which must be +between 2 and 36 inclusive, or be the special value 0. If @var{base} +is 0, @code{strtol} will look for the prefixes @code{0} and @code{0x} +to indicate bases 8 and 16, respectively, else default to base 10. +When the base is 16 (either explicitly or implicitly), a prefix of +@code{0x} is allowed. The handling of @var{endptr} is as that of +@code{strtod} above. The @code{strtoul} function is the same, except +that the converted value is unsigned. + +@end deftypefn + +@c strsignal.c:502 +@deftypefn Extension int strtosigno (const char *@var{name}) + +Given the symbolic name of a signal, map it to a signal number. If no +translation is found, returns 0. + +@end deftypefn + +@c strverscmp.c:25 +@deftypefun int strverscmp (const char *@var{s1}, const char *@var{s2}) +The @code{strverscmp} function compares the string @var{s1} against +@var{s2}, considering them as holding indices/version numbers. Return +value follows the same conventions as found in the @code{strverscmp} +function. In fact, if @var{s1} and @var{s2} contain no digits, +@code{strverscmp} behaves like @code{strcmp}. + +Basically, we compare strings normally (character by character), until +we find a digit in each string - then we enter a special comparison +mode, where each sequence of digits is taken as a whole. If we reach the +end of these two parts without noticing a difference, we return to the +standard comparison mode. There are two types of numeric parts: +"integral" and "fractional" (those begin with a '0'). The types +of the numeric parts affect the way we sort them: + +@itemize @bullet +@item +integral/integral: we compare values as you would expect. + +@item +fractional/integral: the fractional part is less than the integral one. +Again, no surprise. + +@item +fractional/fractional: the things become a bit more complex. +If the common prefix contains only leading zeroes, the longest part is less +than the other one; else the comparison behaves normally. +@end itemize + +@smallexample +strverscmp ("no digit", "no digit") + @result{} 0 // @r{same behavior as strcmp.} +strverscmp ("item#99", "item#100") + @result{} <0 // @r{same prefix, but 99 < 100.} +strverscmp ("alpha1", "alpha001") + @result{} >0 // @r{fractional part inferior to integral one.} +strverscmp ("part1_f012", "part1_f01") + @result{} >0 // @r{two fractional parts.} +strverscmp ("foo.009", "foo.0") + @result{} <0 // @r{idem, but with leading zeroes only.} +@end smallexample + +This function is especially useful when dealing with filename sorting, +because filenames frequently hold indices/version numbers. +@end deftypefun + +@c tmpnam.c:3 +@deftypefn Supplemental char* tmpnam (char *@var{s}) + +This function attempts to create a name for a temporary file, which +will be a valid file name yet not exist when @code{tmpnam} checks for +it. @var{s} must point to a buffer of at least @code{L_tmpnam} bytes, +or be @code{NULL}. Use of this function creates a security risk, and it must +not be used in new projects. Use @code{mkstemp} instead. + +@end deftypefn + +@c unlink-if-ordinary.c:27 +@deftypefn Supplemental int unlink_if_ordinary (const char*) + +Unlinks the named file, unless it is special (e.g. a device file). +Returns 0 when the file was unlinked, a negative value (and errno set) when +there was an error deleting the file, and a positive value if no attempt +was made to unlink the file because it is special. + +@end deftypefn + +@c fopen_unlocked.c:31 +@deftypefn Extension void unlock_std_streams (void) + +If the OS supports it, ensure that the standard I/O streams, +@code{stdin}, @code{stdout} and @code{stderr} are setup to avoid any +multi-threaded locking. Otherwise do nothing. + +@end deftypefn + +@c fopen_unlocked.c:23 +@deftypefn Extension void unlock_stream (FILE * @var{stream}) + +If the OS supports it, ensure that the supplied stream is setup to +avoid any multi-threaded locking. Otherwise leave the @code{FILE} +pointer unchanged. If the @var{stream} is @code{NULL} do nothing. + +@end deftypefn + +@c vasprintf.c:47 +@deftypefn Extension int vasprintf (char **@var{resptr}, @ + const char *@var{format}, va_list @var{args}) + +Like @code{vsprintf}, but instead of passing a pointer to a buffer, +you pass a pointer to a pointer. This function will compute the size +of the buffer needed, allocate memory with @code{malloc}, and store a +pointer to the allocated memory in @code{*@var{resptr}}. The value +returned is the same as @code{vsprintf} would return. If memory could +not be allocated, minus one is returned and @code{NULL} is stored in +@code{*@var{resptr}}. + +@end deftypefn + +@c vfork.c:6 +@deftypefn Supplemental int vfork (void) + +Emulates @code{vfork} by calling @code{fork} and returning its value. + +@end deftypefn + +@c vprintf.c:3 +@deftypefn Supplemental int vprintf (const char *@var{format}, va_list @var{ap}) +@deftypefnx Supplemental int vfprintf (FILE *@var{stream}, @ + const char *@var{format}, va_list @var{ap}) +@deftypefnx Supplemental int vsprintf (char *@var{str}, @ + const char *@var{format}, va_list @var{ap}) + +These functions are the same as @code{printf}, @code{fprintf}, and +@code{sprintf}, respectively, except that they are called with a +@code{va_list} instead of a variable number of arguments. Note that +they do not call @code{va_end}; this is the application's +responsibility. In @libib{} they are implemented in terms of the +nonstandard but common function @code{_doprnt}. + +@end deftypefn + +@c vsnprintf.c:28 +@deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, @ + const char *@var{format}, va_list @var{ap}) + +This function is similar to @code{vsprintf}, but it will write to +@var{buf} at most @code{@var{n}-1} bytes of text, followed by a +terminating null byte, for a total of @var{n} bytes. On error the +return value is -1, otherwise it returns the number of characters that +would have been printed had @var{n} been sufficiently large, +regardless of the actual value of @var{n}. Note some pre-C99 system +libraries do not implement this correctly so users cannot generally +rely on the return value if the system version of this function is +used. + +@end deftypefn + +@c waitpid.c:3 +@deftypefn Supplemental int waitpid (int @var{pid}, int *@var{status}, int) + +This is a wrapper around the @code{wait} function. Any ``special'' +values of @var{pid} depend on your implementation of @code{wait}, as +does the return value. The third argument is unused in @libib{}. + +@end deftypefn + +@c argv.c:306 +@deftypefn Extension int writeargv (const char **@var{argv}, FILE *@var{file}) + +Write each member of ARGV, handling all necessary quoting, to the file +named by FILE, separated by whitespace. Return 0 on success, non-zero +if an error occurred while writing to FILE. + +@end deftypefn + +@c xatexit.c:11 +@deftypefun int xatexit (void (*@var{fn}) (void)) + +Behaves as the standard @code{atexit} function, but with no limit on +the number of registered functions. Returns 0 on success, or @minus{}1 on +failure. If you use @code{xatexit} to register functions, you must use +@code{xexit} to terminate your program. + +@end deftypefun + +@c xmalloc.c:38 +@deftypefn Replacement void* xcalloc (size_t @var{nelem}, size_t @var{elsize}) + +Allocate memory without fail, and set it to zero. This routine functions +like @code{calloc}, but will behave the same as @code{xmalloc} if memory +cannot be found. + +@end deftypefn + +@c xexit.c:22 +@deftypefn Replacement void xexit (int @var{code}) + +Terminates the program. If any functions have been registered with +the @code{xatexit} replacement function, they will be called first. +Termination is handled via the system's normal @code{exit} call. + +@end deftypefn + +@c xmalloc.c:22 +@deftypefn Replacement void* xmalloc (size_t) + +Allocate memory without fail. If @code{malloc} fails, this will print +a message to @code{stderr} (using the name set by +@code{xmalloc_set_program_name}, +if any) and then call @code{xexit}. Note that it is therefore safe for +a program to contain @code{#define malloc xmalloc} in its source. + +@end deftypefn + +@c xmalloc.c:53 +@deftypefn Replacement void xmalloc_failed (size_t) + +This function is not meant to be called by client code, and is listed +here for completeness only. If any of the allocation routines fail, this +function will be called to print an error message and terminate execution. + +@end deftypefn + +@c xmalloc.c:46 +@deftypefn Replacement void xmalloc_set_program_name (const char *@var{name}) + +You can use this to set the name of the program used by +@code{xmalloc_failed} when printing a failure message. + +@end deftypefn + +@c xmemdup.c:7 +@deftypefn Replacement void* xmemdup (void *@var{input}, @ + size_t @var{copy_size}, size_t @var{alloc_size}) + +Duplicates a region of memory without fail. First, @var{alloc_size} bytes +are allocated, then @var{copy_size} bytes from @var{input} are copied into +it, and the new memory is returned. If fewer bytes are copied than were +allocated, the remaining memory is zeroed. + +@end deftypefn + +@c xmalloc.c:32 +@deftypefn Replacement void* xrealloc (void *@var{ptr}, size_t @var{size}) +Reallocate memory without fail. This routine functions like @code{realloc}, +but will behave the same as @code{xmalloc} if memory cannot be found. + +@end deftypefn + +@c xstrdup.c:7 +@deftypefn Replacement char* xstrdup (const char *@var{s}) + +Duplicates a character string without fail, using @code{xmalloc} to +obtain memory. + +@end deftypefn + +@c xstrerror.c:7 +@deftypefn Replacement char* xstrerror (int @var{errnum}) + +Behaves exactly like the standard @code{strerror} function, but +will never return a @code{NULL} pointer. + +@end deftypefn + +@c xstrndup.c:23 +@deftypefn Replacement char* xstrndup (const char *@var{s}, size_t @var{n}) + +Returns a pointer to a copy of @var{s} with at most @var{n} characters +without fail, using @code{xmalloc} to obtain memory. The result is +always NUL terminated. + +@end deftypefn + + diff --git a/external/gpl3/gdb/dist/libiberty/gather-docs b/external/gpl3/gdb/dist/libiberty/gather-docs new file mode 100644 index 000000000000..2f1f3b1f699e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/gather-docs @@ -0,0 +1,128 @@ +#!/usr/bin/perl +# -*- perl -*- + +# Copyright (C) 2001, 2009, 2011 +# Free Software Foundation +# +# This file is part of the libiberty library. +# Libiberty is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# Libiberty is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with libiberty; see the file COPYING.LIB. If not, +# write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +# Boston, MA 02110-1301, USA. +# +# Originally written by DJ Delorie + + + +# This program looks for texinfo snippets in source files and other +# files, and builds per-category files with entries sorted in +# alphabetical order. + +# The syntax it looks for is lines starting with '@def' in *.c and +# other files (see TEXIFILES in Makefile.in). Entries are terminated +# at the next @def* (which begins a new entry) or, for C files, a line +# that begins with '*/' without leading spaces (this assumes that the +# texinfo snippet is within a C-style /* */ comment). + +# + + + +if ($ARGV[0] eq "-v") { + $verbose = 1; + shift; +} + +$srcdir = shift; +$outfile = shift; + +if ($outfile !~ /\S/ || ! -f "$srcdir/Makefile.in" ) { + print STDERR "Usage: gather-docs [-v] srcdir outfile.txi [files with snippets in them ...]\n"; + exit 1; +} + +$errors = 0; + +for $in (@ARGV) { + + if (!open(IN, "$srcdir/$in")) { + print STDERR "Cannot open $srcdir/$in for reading: $!\n"; + $errors ++; + + } else { + $first = 1; + $pertinent = 0; + $man_mode = 0; + $line = 0; + + while () { + $line ++; + $pertinent = 1 if /^\@def[a-z]*[a-wyz] /; + $pertinent = 0 if /^\*\//; + next unless $pertinent; + + if (/^\@def[a-z]*[a-wyz] /) { + + ($name) = m/[^\(]* ([^\( \t\r\n\@]+) *(\(|\@?$)/; + $name =~ s/[ ]*\@?$//; + $key = $name; + $key =~ tr/A-Z/a-z/; + $key =~ s/[^a-z0-9]+/ /g; + $name{$key} = $node; + $lines{$key} = ''; + $src_file{$key} = $in; + $src_line{$key} = $line; + print "\nReading $in :" if $verbose && $first; + $first = 0; + print " $name" if $verbose; + $node_lines{$key} .= $_; + + } else { + $node_lines{$key} .= $_; + } + + $pertinent = 0 if /^\@end def/; + } + close (IN); + } +} + +print "\n" if $verbose; +exit $errors if $errors; + +if (!open (OUT, "> $outfile")) { + print STDERR "Cannot open $outfile for writing: $!\n"; + $errors ++; + next; +} +print "Writing $outfile\n" if $verbose; + +print OUT "\@c Automatically generated from *.c and others (the comments before\n"; +print OUT "\@c each entry tell you which file and where in that file). DO NOT EDIT!\n"; +print OUT "\@c Edit the *.c files, configure with --enable-maintainer-mode,\n"; +print OUT "\@c run 'make stamp-functions' and gather-docs will build a new copy.\n\n"; + +for $key (sort keys %name) { + print OUT "\@c $src_file{$key}:$src_line{$key}\n"; + print OUT $node_lines{$key}; + print OUT "\n"; +} + +if (! print OUT "\n") { + print STDERR "Disk full writing $srcdir/$cat.texi\n"; + $errors ++; +} + +close (OUT); + +exit $errors; diff --git a/external/gpl3/gdb/dist/libiberty/getcwd.c b/external/gpl3/gdb/dist/libiberty/getcwd.c new file mode 100644 index 000000000000..28f26eb179ff --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getcwd.c @@ -0,0 +1,62 @@ +/* Emulate getcwd using getwd. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental char* getcwd (char *@var{pathname}, int @var{len}) + +Copy the absolute pathname for the current working directory into +@var{pathname}, which is assumed to point to a buffer of at least +@var{len} bytes, and return a pointer to the buffer. If the current +directory's path doesn't fit in @var{len} characters, the result is +@code{NULL} and @code{errno} is set. If @var{pathname} is a null pointer, +@code{getcwd} will obtain @var{len} bytes of space using +@code{malloc}. + +@end deftypefn + +*/ + +#include "config.h" + +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +extern char *getwd (); +extern int errno; + +#ifndef MAXPATHLEN +#define MAXPATHLEN 1024 +#endif + +char * +getcwd (char *buf, size_t len) +{ + char ourbuf[MAXPATHLEN]; + char *result; + + result = getwd (ourbuf); + if (result) { + if (strlen (ourbuf) >= len) { + errno = ERANGE; + return 0; + } + if (!buf) { + buf = (char*)malloc(len); + if (!buf) { + errno = ENOMEM; + return 0; + } + } + strcpy (buf, ourbuf); + } + return buf; +} diff --git a/external/gpl3/gdb/dist/libiberty/getopt.c b/external/gpl3/gdb/dist/libiberty/getopt.c new file mode 100644 index 000000000000..d9c3532ce113 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getopt.c @@ -0,0 +1,1052 @@ +/* Getopt for GNU. + NOTE: getopt is now part of the C library, so if you don't know what + "Keep this file name-space clean" means, talk to drepper@gnu.org + before changing it! + + Copyright (C) 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, + 1996, 1997, 1998, 2005 Free Software Foundation, Inc. + + NOTE: This source is derived from an old version taken from the GNU C + Library (glibc). + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +/* This tells Alpha OSF/1 not to define a getopt prototype in . + Ditto for AIX 3.2 and . */ +#ifndef _NO_PROTO +# define _NO_PROTO +#endif + +#ifdef HAVE_CONFIG_H +# include +#endif + +#if !defined __STDC__ || !__STDC__ +/* This is a separate conditional since some stdc systems + reject `defined (const)'. */ +# ifndef const +# define const +# endif +#endif + +#include "ansidecl.h" +#include + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#define GETOPT_INTERFACE_VERSION 2 +#if !defined _LIBC && defined __GLIBC__ && __GLIBC__ >= 2 +# include +# if _GNU_GETOPT_INTERFACE_VERSION == GETOPT_INTERFACE_VERSION +# define ELIDE_CODE +# endif +#endif + +#ifndef ELIDE_CODE + + +/* This needs to come after some library #include + to get __GNU_LIBRARY__ defined. */ +#ifdef __GNU_LIBRARY__ +/* Don't include stdlib.h for non-GNU C libraries because some of them + contain conflicting prototypes for getopt. */ +# include +# include +#endif /* GNU C library. */ + +#ifdef VMS +# include +# if HAVE_STRING_H - 0 +# include +# endif +#endif + +#ifndef _ +/* This is for other GNU distributions with internationalized messages. + When compiling libc, the _ macro is predefined. */ +# if (HAVE_LIBINTL_H && ENABLE_NLS) || defined _LIBC +# include +# define _(msgid) gettext (msgid) +# else +# define _(msgid) (msgid) +# endif +#endif + +/* This version of `getopt' appears to the caller like standard Unix `getopt' + but it behaves differently for the user, since it allows the user + to intersperse the options with the other arguments. + + As `getopt' works, it permutes the elements of ARGV so that, + when it is done, all the options precede everything else. Thus + all application programs are extended to handle flexible argument order. + + Setting the environment variable POSIXLY_CORRECT disables permutation. + Then the behavior is completely standard. + + GNU application programs can use a third alternative mode in which + they can distinguish the relative order of options and other arguments. */ + +#include "getopt.h" + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +char *optarg = NULL; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns -1, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +/* 1003.2 says this must be 1 before any call. */ +int optind = 1; + +/* Formerly, initialization of getopt depended on optind==0, which + causes problems with re-calling getopt as programs generally don't + know that. */ + +int __getopt_initialized = 0; + +/* The next char to be scanned in the option-element + in which the last option character we returned was found. + This allows us to pick up the scan where we left off. + + If this is zero, or a null string, it means resume the scan + by advancing to the next ARGV-element. */ + +static char *nextchar; + +/* Callers store zero here to inhibit the error message + for unrecognized options. */ + +int opterr = 1; + +/* Set to an option character which was unrecognized. + This must be initialized on some systems to avoid linking in the + system's own getopt implementation. */ + +int optopt = '?'; + +/* Describe how to deal with options that follow non-option ARGV-elements. + + If the caller did not specify anything, + the default is REQUIRE_ORDER if the environment variable + POSIXLY_CORRECT is defined, PERMUTE otherwise. + + REQUIRE_ORDER means don't recognize them as options; + stop option processing when the first non-option is seen. + This is what Unix does. + This mode of operation is selected by either setting the environment + variable POSIXLY_CORRECT, or using `+' as the first character + of the list of option characters. + + PERMUTE is the default. We permute the contents of ARGV as we scan, + so that eventually all the non-options are at the end. This allows options + to be given in any order, even with programs that were not written to + expect this. + + RETURN_IN_ORDER is an option available to programs that were written + to expect options and other ARGV-elements in any order and that care about + the ordering of the two. We describe each non-option ARGV-element + as if it were the argument of an option with character code 1. + Using `-' as the first character of the list of option characters + selects this mode of operation. + + The special argument `--' forces an end of option-scanning regardless + of the value of `ordering'. In the case of RETURN_IN_ORDER, only + `--' can cause `getopt' to return -1 with `optind' != ARGC. */ + +static enum +{ + REQUIRE_ORDER, PERMUTE, RETURN_IN_ORDER +} ordering; + +/* Value of POSIXLY_CORRECT environment variable. */ +static char *posixly_correct; + +#ifdef __GNU_LIBRARY__ +/* We want to avoid inclusion of string.h with non-GNU libraries + because there are many ways it can cause trouble. + On some systems, it contains special magic macros that don't work + in GCC. */ +# include +# define my_index strchr +#else + +# if HAVE_STRING_H +# include +# else +# if HAVE_STRINGS_H +# include +# endif +# endif + +/* Avoid depending on library functions or files + whose names are inconsistent. */ + +#if HAVE_STDLIB_H && HAVE_DECL_GETENV +# include +#elif !defined(getenv) +# ifdef __cplusplus +extern "C" { +# endif /* __cplusplus */ +extern char *getenv (const char *); +# ifdef __cplusplus +} +# endif /* __cplusplus */ +#endif + +static char * +my_index (const char *str, int chr) +{ + while (*str) + { + if (*str == chr) + return (char *) str; + str++; + } + return 0; +} + +/* If using GCC, we can safely declare strlen this way. + If not using GCC, it is ok not to declare it. */ +#ifdef __GNUC__ +/* Note that Motorola Delta 68k R3V7 comes with GCC but not stddef.h. + That was relevant to code that was here before. */ +# if (!defined __STDC__ || !__STDC__) && !defined strlen +/* gcc with -traditional declares the built-in strlen to return int, + and has done so at least since version 2.4.5. -- rms. */ +extern int strlen (const char *); +# endif /* not __STDC__ */ +#endif /* __GNUC__ */ + +#endif /* not __GNU_LIBRARY__ */ + +/* Handle permutation of arguments. */ + +/* Describe the part of ARGV that contains non-options that have + been skipped. `first_nonopt' is the index in ARGV of the first of them; + `last_nonopt' is the index after the last of them. */ + +static int first_nonopt; +static int last_nonopt; + +#ifdef _LIBC +/* Bash 2.0 gives us an environment variable containing flags + indicating ARGV elements that should not be considered arguments. */ + +/* Defined in getopt_init.c */ +extern char *__getopt_nonoption_flags; + +static int nonoption_flags_max_len; +static int nonoption_flags_len; + +static int original_argc; +static char *const *original_argv; + +/* Make sure the environment variable bash 2.0 puts in the environment + is valid for the getopt call we must make sure that the ARGV passed + to getopt is that one passed to the process. */ +static void +__attribute__ ((unused)) +store_args_and_env (int argc, char *const *argv) +{ + /* XXX This is no good solution. We should rather copy the args so + that we can compare them later. But we must not use malloc(3). */ + original_argc = argc; + original_argv = argv; +} +# ifdef text_set_element +text_set_element (__libc_subinit, store_args_and_env); +# endif /* text_set_element */ + +# define SWAP_FLAGS(ch1, ch2) \ + if (nonoption_flags_len > 0) \ + { \ + char __tmp = __getopt_nonoption_flags[ch1]; \ + __getopt_nonoption_flags[ch1] = __getopt_nonoption_flags[ch2]; \ + __getopt_nonoption_flags[ch2] = __tmp; \ + } +#else /* !_LIBC */ +# define SWAP_FLAGS(ch1, ch2) +#endif /* _LIBC */ + +/* Exchange two adjacent subsequences of ARGV. + One subsequence is elements [first_nonopt,last_nonopt) + which contains all the non-options that have been skipped so far. + The other is elements [last_nonopt,optind), which contains all + the options processed since those non-options were skipped. + + `first_nonopt' and `last_nonopt' are relocated so that they describe + the new indices of the non-options in ARGV after they are moved. */ + +#if defined __STDC__ && __STDC__ +static void exchange (char **); +#endif + +static void +exchange (char **argv) +{ + int bottom = first_nonopt; + int middle = last_nonopt; + int top = optind; + char *tem; + + /* Exchange the shorter segment with the far end of the longer segment. + That puts the shorter segment into the right place. + It leaves the longer segment in the right place overall, + but it consists of two parts that need to be swapped next. */ + +#ifdef _LIBC + /* First make sure the handling of the `__getopt_nonoption_flags' + string can work normally. Our top argument must be in the range + of the string. */ + if (nonoption_flags_len > 0 && top >= nonoption_flags_max_len) + { + /* We must extend the array. The user plays games with us and + presents new arguments. */ + char *new_str = (char *) malloc (top + 1); + if (new_str == NULL) + nonoption_flags_len = nonoption_flags_max_len = 0; + else + { + memset (mempcpy (new_str, __getopt_nonoption_flags, + nonoption_flags_max_len), + '\0', top + 1 - nonoption_flags_max_len); + nonoption_flags_max_len = top + 1; + __getopt_nonoption_flags = new_str; + } + } +#endif + + while (top > middle && middle > bottom) + { + if (top - middle > middle - bottom) + { + /* Bottom segment is the short one. */ + int len = middle - bottom; + register int i; + + /* Swap it with the top part of the top segment. */ + for (i = 0; i < len; i++) + { + tem = argv[bottom + i]; + argv[bottom + i] = argv[top - (middle - bottom) + i]; + argv[top - (middle - bottom) + i] = tem; + SWAP_FLAGS (bottom + i, top - (middle - bottom) + i); + } + /* Exclude the moved bottom segment from further swapping. */ + top -= len; + } + else + { + /* Top segment is the short one. */ + int len = top - middle; + register int i; + + /* Swap it with the bottom part of the bottom segment. */ + for (i = 0; i < len; i++) + { + tem = argv[bottom + i]; + argv[bottom + i] = argv[middle + i]; + argv[middle + i] = tem; + SWAP_FLAGS (bottom + i, middle + i); + } + /* Exclude the moved top segment from further swapping. */ + bottom += len; + } + } + + /* Update records for the slots the non-options now occupy. */ + + first_nonopt += (optind - last_nonopt); + last_nonopt = optind; +} + +/* Initialize the internal data when the first call is made. */ + +#if defined __STDC__ && __STDC__ +static const char *_getopt_initialize (int, char *const *, const char *); +#endif +static const char * +_getopt_initialize (int argc ATTRIBUTE_UNUSED, + char *const *argv ATTRIBUTE_UNUSED, + const char *optstring) +{ + /* Start processing options with ARGV-element 1 (since ARGV-element 0 + is the program name); the sequence of previously skipped + non-option ARGV-elements is empty. */ + + first_nonopt = last_nonopt = optind; + + nextchar = NULL; + + posixly_correct = getenv ("POSIXLY_CORRECT"); + + /* Determine how to handle the ordering of options and nonoptions. */ + + if (optstring[0] == '-') + { + ordering = RETURN_IN_ORDER; + ++optstring; + } + else if (optstring[0] == '+') + { + ordering = REQUIRE_ORDER; + ++optstring; + } + else if (posixly_correct != NULL) + ordering = REQUIRE_ORDER; + else + ordering = PERMUTE; + +#ifdef _LIBC + if (posixly_correct == NULL + && argc == original_argc && argv == original_argv) + { + if (nonoption_flags_max_len == 0) + { + if (__getopt_nonoption_flags == NULL + || __getopt_nonoption_flags[0] == '\0') + nonoption_flags_max_len = -1; + else + { + const char *orig_str = __getopt_nonoption_flags; + int len = nonoption_flags_max_len = strlen (orig_str); + if (nonoption_flags_max_len < argc) + nonoption_flags_max_len = argc; + __getopt_nonoption_flags = + (char *) malloc (nonoption_flags_max_len); + if (__getopt_nonoption_flags == NULL) + nonoption_flags_max_len = -1; + else + memset (mempcpy (__getopt_nonoption_flags, orig_str, len), + '\0', nonoption_flags_max_len - len); + } + } + nonoption_flags_len = nonoption_flags_max_len; + } + else + nonoption_flags_len = 0; +#endif + + return optstring; +} + +/* Scan elements of ARGV (whose length is ARGC) for option characters + given in OPTSTRING. + + If an element of ARGV starts with '-', and is not exactly "-" or "--", + then it is an option element. The characters of this element + (aside from the initial '-') are option characters. If `getopt' + is called repeatedly, it returns successively each of the option characters + from each of the option elements. + + If `getopt' finds another option character, it returns that character, + updating `optind' and `nextchar' so that the next call to `getopt' can + resume the scan with the following option character or ARGV-element. + + If there are no more option characters, `getopt' returns -1. + Then `optind' is the index in ARGV of the first ARGV-element + that is not an option. (The ARGV-elements have been permuted + so that those that are not options now come last.) + + OPTSTRING is a string containing the legitimate option characters. + If an option character is seen that is not listed in OPTSTRING, + return '?' after printing an error message. If you set `opterr' to + zero, the error message is suppressed but we still return '?'. + + If a char in OPTSTRING is followed by a colon, that means it wants an arg, + so the following text in the same ARGV-element, or the text of the following + ARGV-element, is returned in `optarg'. Two colons mean an option that + wants an optional arg; if there is text in the current ARGV-element, + it is returned in `optarg', otherwise `optarg' is set to zero. + + If OPTSTRING starts with `-' or `+', it requests different methods of + handling the non-option ARGV-elements. + See the comments about RETURN_IN_ORDER and REQUIRE_ORDER, above. + + Long-named options begin with `--' instead of `-'. + Their names may be abbreviated as long as the abbreviation is unique + or is an exact match for some defined option. If they have an + argument, it follows the option name in the same ARGV-element, separated + from the option name by a `=', or else the in next ARGV-element. + When `getopt' finds a long-named option, it returns 0 if that option's + `flag' field is nonzero, the value of the option's `val' field + if the `flag' field is zero. + + The elements of ARGV aren't really const, because we permute them. + But we pretend they're const in the prototype to be compatible + with other systems. + + LONGOPTS is a vector of `struct option' terminated by an + element containing a name which is zero. + + LONGIND returns the index in LONGOPT of the long-named option found. + It is only valid when a long-named option has been found by the most + recent call. + + If LONG_ONLY is nonzero, '-' as well as '--' can introduce + long-named options. */ + +int +_getopt_internal (int argc, char *const *argv, const char *optstring, + const struct option *longopts, + int *longind, int long_only) +{ + optarg = NULL; + + if (optind == 0 || !__getopt_initialized) + { + if (optind == 0) + optind = 1; /* Don't scan ARGV[0], the program name. */ + optstring = _getopt_initialize (argc, argv, optstring); + __getopt_initialized = 1; + } + + /* Test whether ARGV[optind] points to a non-option argument. + Either it does not have option syntax, or there is an environment flag + from the shell indicating it is not an option. The later information + is only used when the used in the GNU libc. */ +#ifdef _LIBC +# define NONOPTION_P (argv[optind][0] != '-' || argv[optind][1] == '\0' \ + || (optind < nonoption_flags_len \ + && __getopt_nonoption_flags[optind] == '1')) +#else +# define NONOPTION_P (argv[optind][0] != '-' || argv[optind][1] == '\0') +#endif + + if (nextchar == NULL || *nextchar == '\0') + { + /* Advance to the next ARGV-element. */ + + /* Give FIRST_NONOPT & LAST_NONOPT rational values if OPTIND has been + moved back by the user (who may also have changed the arguments). */ + if (last_nonopt > optind) + last_nonopt = optind; + if (first_nonopt > optind) + first_nonopt = optind; + + if (ordering == PERMUTE) + { + /* If we have just processed some options following some non-options, + exchange them so that the options come first. */ + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange ((char **) argv); + else if (last_nonopt != optind) + first_nonopt = optind; + + /* Skip any additional non-options + and extend the range of non-options previously skipped. */ + + while (optind < argc && NONOPTION_P) + optind++; + last_nonopt = optind; + } + + /* The special ARGV-element `--' means premature end of options. + Skip it like a null option, + then exchange with previous non-options as if it were an option, + then skip everything else like a non-option. */ + + if (optind != argc && !strcmp (argv[optind], "--")) + { + optind++; + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange ((char **) argv); + else if (first_nonopt == last_nonopt) + first_nonopt = optind; + last_nonopt = argc; + + optind = argc; + } + + /* If we have done all the ARGV-elements, stop the scan + and back over any non-options that we skipped and permuted. */ + + if (optind == argc) + { + /* Set the next-arg-index to point at the non-options + that we previously skipped, so the caller will digest them. */ + if (first_nonopt != last_nonopt) + optind = first_nonopt; + return -1; + } + + /* If we have come to a non-option and did not permute it, + either stop the scan or describe it to the caller and pass it by. */ + + if (NONOPTION_P) + { + if (ordering == REQUIRE_ORDER) + return -1; + optarg = argv[optind++]; + return 1; + } + + /* We have found another option-ARGV-element. + Skip the initial punctuation. */ + + nextchar = (argv[optind] + 1 + + (longopts != NULL && argv[optind][1] == '-')); + } + + /* Decode the current option-ARGV-element. */ + + /* Check whether the ARGV-element is a long option. + + If long_only and the ARGV-element has the form "-f", where f is + a valid short option, don't consider it an abbreviated form of + a long option that starts with f. Otherwise there would be no + way to give the -f short option. + + On the other hand, if there's a long option "fubar" and + the ARGV-element is "-fu", do consider that an abbreviation of + the long option, just like "--fu", and not "-f" with arg "u". + + This distinction seems to be the most useful approach. */ + + if (longopts != NULL + && (argv[optind][1] == '-' + || (long_only && (argv[optind][2] || !my_index (optstring, argv[optind][1]))))) + { + char *nameend; + const struct option *p; + const struct option *pfound = NULL; + int exact = 0; + int ambig = 0; + int indfound = -1; + int option_index; + + for (nameend = nextchar; *nameend && *nameend != '='; nameend++) + /* Do nothing. */ ; + + /* Test all long options for either exact match + or abbreviated matches. */ + for (p = longopts, option_index = 0; p->name; p++, option_index++) + if (!strncmp (p->name, nextchar, nameend - nextchar)) + { + if ((unsigned int) (nameend - nextchar) + == (unsigned int) strlen (p->name)) + { + /* Exact match found. */ + pfound = p; + indfound = option_index; + exact = 1; + break; + } + else if (pfound == NULL) + { + /* First nonexact match found. */ + pfound = p; + indfound = option_index; + } + else + /* Second or later nonexact match found. */ + ambig = 1; + } + + if (ambig && !exact) + { + if (opterr) + fprintf (stderr, _("%s: option `%s' is ambiguous\n"), + argv[0], argv[optind]); + nextchar += strlen (nextchar); + optind++; + optopt = 0; + return '?'; + } + + if (pfound != NULL) + { + option_index = indfound; + optind++; + if (*nameend) + { + /* Don't test has_arg with >, because some C compilers don't + allow it to be used on enums. */ + if (pfound->has_arg) + optarg = nameend + 1; + else + { + if (opterr) + { + if (argv[optind - 1][1] == '-') + /* --option */ + fprintf (stderr, + _("%s: option `--%s' doesn't allow an argument\n"), + argv[0], pfound->name); + else + /* +option or -option */ + fprintf (stderr, + _("%s: option `%c%s' doesn't allow an argument\n"), + argv[0], argv[optind - 1][0], pfound->name); + + nextchar += strlen (nextchar); + + optopt = pfound->val; + return '?'; + } + } + } + else if (pfound->has_arg == 1) + { + if (optind < argc) + optarg = argv[optind++]; + else + { + if (opterr) + fprintf (stderr, + _("%s: option `%s' requires an argument\n"), + argv[0], argv[optind - 1]); + nextchar += strlen (nextchar); + optopt = pfound->val; + return optstring[0] == ':' ? ':' : '?'; + } + } + nextchar += strlen (nextchar); + if (longind != NULL) + *longind = option_index; + if (pfound->flag) + { + *(pfound->flag) = pfound->val; + return 0; + } + return pfound->val; + } + + /* Can't find it as a long option. If this is not getopt_long_only, + or the option starts with '--' or is not a valid short + option, then it's an error. + Otherwise interpret it as a short option. */ + if (!long_only || argv[optind][1] == '-' + || my_index (optstring, *nextchar) == NULL) + { + if (opterr) + { + if (argv[optind][1] == '-') + /* --option */ + fprintf (stderr, _("%s: unrecognized option `--%s'\n"), + argv[0], nextchar); + else + /* +option or -option */ + fprintf (stderr, _("%s: unrecognized option `%c%s'\n"), + argv[0], argv[optind][0], nextchar); + } + nextchar = (char *) ""; + optind++; + optopt = 0; + return '?'; + } + } + + /* Look at and handle the next short option-character. */ + + { + char c = *nextchar++; + char *temp = my_index (optstring, c); + + /* Increment `optind' when we start to process its last character. */ + if (*nextchar == '\0') + ++optind; + + if (temp == NULL || c == ':') + { + if (opterr) + { + if (posixly_correct) + /* 1003.2 specifies the format of this message. */ + fprintf (stderr, _("%s: illegal option -- %c\n"), + argv[0], c); + else + fprintf (stderr, _("%s: invalid option -- %c\n"), + argv[0], c); + } + optopt = c; + return '?'; + } + /* Convenience. Treat POSIX -W foo same as long option --foo */ + if (temp[0] == 'W' && temp[1] == ';') + { + char *nameend; + const struct option *p; + const struct option *pfound = NULL; + int exact = 0; + int ambig = 0; + int indfound = 0; + int option_index; + + /* This is an option that requires an argument. */ + if (*nextchar != '\0') + { + optarg = nextchar; + /* If we end this ARGV-element by taking the rest as an arg, + we must advance to the next element now. */ + optind++; + } + else if (optind == argc) + { + if (opterr) + { + /* 1003.2 specifies the format of this message. */ + fprintf (stderr, _("%s: option requires an argument -- %c\n"), + argv[0], c); + } + optopt = c; + if (optstring[0] == ':') + c = ':'; + else + c = '?'; + return c; + } + else + /* We already incremented `optind' once; + increment it again when taking next ARGV-elt as argument. */ + optarg = argv[optind++]; + + /* optarg is now the argument, see if it's in the + table of longopts. */ + + for (nextchar = nameend = optarg; *nameend && *nameend != '='; nameend++) + /* Do nothing. */ ; + + /* Test all long options for either exact match + or abbreviated matches. */ + for (p = longopts, option_index = 0; p->name; p++, option_index++) + if (!strncmp (p->name, nextchar, nameend - nextchar)) + { + if ((unsigned int) (nameend - nextchar) == strlen (p->name)) + { + /* Exact match found. */ + pfound = p; + indfound = option_index; + exact = 1; + break; + } + else if (pfound == NULL) + { + /* First nonexact match found. */ + pfound = p; + indfound = option_index; + } + else + /* Second or later nonexact match found. */ + ambig = 1; + } + if (ambig && !exact) + { + if (opterr) + fprintf (stderr, _("%s: option `-W %s' is ambiguous\n"), + argv[0], argv[optind]); + nextchar += strlen (nextchar); + optind++; + return '?'; + } + if (pfound != NULL) + { + option_index = indfound; + if (*nameend) + { + /* Don't test has_arg with >, because some C compilers don't + allow it to be used on enums. */ + if (pfound->has_arg) + optarg = nameend + 1; + else + { + if (opterr) + fprintf (stderr, _("\ +%s: option `-W %s' doesn't allow an argument\n"), + argv[0], pfound->name); + + nextchar += strlen (nextchar); + return '?'; + } + } + else if (pfound->has_arg == 1) + { + if (optind < argc) + optarg = argv[optind++]; + else + { + if (opterr) + fprintf (stderr, + _("%s: option `%s' requires an argument\n"), + argv[0], argv[optind - 1]); + nextchar += strlen (nextchar); + return optstring[0] == ':' ? ':' : '?'; + } + } + nextchar += strlen (nextchar); + if (longind != NULL) + *longind = option_index; + if (pfound->flag) + { + *(pfound->flag) = pfound->val; + return 0; + } + return pfound->val; + } + nextchar = NULL; + return 'W'; /* Let the application handle it. */ + } + if (temp[1] == ':') + { + if (temp[2] == ':') + { + /* This is an option that accepts an argument optionally. */ + if (*nextchar != '\0') + { + optarg = nextchar; + optind++; + } + else + optarg = NULL; + nextchar = NULL; + } + else + { + /* This is an option that requires an argument. */ + if (*nextchar != '\0') + { + optarg = nextchar; + /* If we end this ARGV-element by taking the rest as an arg, + we must advance to the next element now. */ + optind++; + } + else if (optind == argc) + { + if (opterr) + { + /* 1003.2 specifies the format of this message. */ + fprintf (stderr, + _("%s: option requires an argument -- %c\n"), + argv[0], c); + } + optopt = c; + if (optstring[0] == ':') + c = ':'; + else + c = '?'; + } + else + /* We already incremented `optind' once; + increment it again when taking next ARGV-elt as argument. */ + optarg = argv[optind++]; + nextchar = NULL; + } + } + return c; + } +} + +int +getopt (int argc, char *const *argv, const char *optstring) +{ + return _getopt_internal (argc, argv, optstring, + (const struct option *) 0, + (int *) 0, + 0); +} + +#endif /* Not ELIDE_CODE. */ + +#ifdef TEST + +/* Compile with -DTEST to make an executable for use in testing + the above definition of `getopt'. */ + +int +main (int argc, char **argv) +{ + int c; + int digit_optind = 0; + + while (1) + { + int this_option_optind = optind ? optind : 1; + + c = getopt (argc, argv, "abc:d:0123456789"); + if (c == -1) + break; + + switch (c) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (digit_optind != 0 && digit_optind != this_option_optind) + printf ("digits occur in two different argv-elements.\n"); + digit_optind = this_option_optind; + printf ("option %c\n", c); + break; + + case 'a': + printf ("option a\n"); + break; + + case 'b': + printf ("option b\n"); + break; + + case 'c': + printf ("option c with value `%s'\n", optarg); + break; + + case '?': + break; + + default: + printf ("?? getopt returned character code 0%o ??\n", c); + } + } + + if (optind < argc) + { + printf ("non-option ARGV-elements: "); + while (optind < argc) + printf ("%s ", argv[optind++]); + printf ("\n"); + } + + exit (0); +} + +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/libiberty/getopt1.c b/external/gpl3/gdb/dist/libiberty/getopt1.c new file mode 100644 index 000000000000..255b1445637f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getopt1.c @@ -0,0 +1,180 @@ +/* getopt_long and getopt_long_only entry points for GNU getopt. + Copyright (C) 1987,88,89,90,91,92,93,94,96,97,98,2005 + Free Software Foundation, Inc. + + NOTE: This source is derived from an old version taken from the GNU C + Library (glibc). + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#if !defined __STDC__ || !__STDC__ +/* This is a separate conditional since some stdc systems + reject `defined (const)'. */ +#ifndef const +#define const +#endif +#endif + +#include + +#include "getopt.h" + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#define GETOPT_INTERFACE_VERSION 2 +#if !defined _LIBC && defined __GLIBC__ && __GLIBC__ >= 2 +#include +#if _GNU_GETOPT_INTERFACE_VERSION == GETOPT_INTERFACE_VERSION +#define ELIDE_CODE +#endif +#endif + +#ifndef ELIDE_CODE + + +/* This needs to come after some library #include + to get __GNU_LIBRARY__ defined. */ +#ifdef __GNU_LIBRARY__ +#include +#endif + +#ifndef NULL +#define NULL 0 +#endif + +int +getopt_long (int argc, char *const *argv, const char *options, + const struct option *long_options, int *opt_index) +{ + return _getopt_internal (argc, argv, options, long_options, opt_index, 0); +} + +/* Like getopt_long, but '-' as well as '--' can indicate a long option. + If an option that starts with '-' (not '--') doesn't match a long option, + but does match a short option, it is parsed as a short option + instead. */ + +int +getopt_long_only (int argc, char *const *argv, const char *options, + const struct option *long_options, int *opt_index) +{ + return _getopt_internal (argc, argv, options, long_options, opt_index, 1); +} + + +#endif /* Not ELIDE_CODE. */ + +#ifdef TEST + +#include + +int +main (int argc, char **argv) +{ + int c; + int digit_optind = 0; + + while (1) + { + int this_option_optind = optind ? optind : 1; + int option_index = 0; + static struct option long_options[] = + { + {"add", 1, 0, 0}, + {"append", 0, 0, 0}, + {"delete", 1, 0, 0}, + {"verbose", 0, 0, 0}, + {"create", 0, 0, 0}, + {"file", 1, 0, 0}, + {0, 0, 0, 0} + }; + + c = getopt_long (argc, argv, "abc:d:0123456789", + long_options, &option_index); + if (c == -1) + break; + + switch (c) + { + case 0: + printf ("option %s", long_options[option_index].name); + if (optarg) + printf (" with arg %s", optarg); + printf ("\n"); + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (digit_optind != 0 && digit_optind != this_option_optind) + printf ("digits occur in two different argv-elements.\n"); + digit_optind = this_option_optind; + printf ("option %c\n", c); + break; + + case 'a': + printf ("option a\n"); + break; + + case 'b': + printf ("option b\n"); + break; + + case 'c': + printf ("option c with value `%s'\n", optarg); + break; + + case 'd': + printf ("option d with value `%s'\n", optarg); + break; + + case '?': + break; + + default: + printf ("?? getopt returned character code 0%o ??\n", c); + } + } + + if (optind < argc) + { + printf ("non-option ARGV-elements: "); + while (optind < argc) + printf ("%s ", argv[optind++]); + printf ("\n"); + } + + exit (0); +} + +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/libiberty/getpagesize.c b/external/gpl3/gdb/dist/libiberty/getpagesize.c new file mode 100644 index 000000000000..1c3a26304eae --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getpagesize.c @@ -0,0 +1,90 @@ +/* Emulation of getpagesize() for systems that need it. */ + +/* + +@deftypefn Supplemental int getpagesize (void) + +Returns the number of bytes in a page of memory. This is the +granularity of many of the system memory management routines. No +guarantee is made as to whether or not it is the same as the basic +memory management hardware page size. + +@end deftypefn + +BUGS + + Is intended as a reasonable replacement for systems where this + is not provided as a system call. The value of 4096 may or may + not be correct for the systems where it is returned as the default + value. + +*/ + +#ifndef VMS + +#include "config.h" + +#include +#ifdef HAVE_SYS_PARAM_H +#include +#endif + +#undef GNU_OUR_PAGESIZE +#if defined (HAVE_SYSCONF) && defined (HAVE_UNISTD_H) +#include +#ifdef _SC_PAGESIZE +#define GNU_OUR_PAGESIZE sysconf(_SC_PAGESIZE) +#endif +#endif + +#ifndef GNU_OUR_PAGESIZE +# ifdef PAGESIZE +# define GNU_OUR_PAGESIZE PAGESIZE +# else /* no PAGESIZE */ +# ifdef EXEC_PAGESIZE +# define GNU_OUR_PAGESIZE EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define GNU_OUR_PAGESIZE (NBPG * CLSIZE) +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define GNU_OUR_PAGESIZE NBPC +# else /* no NBPC */ +# define GNU_OUR_PAGESIZE 4096 /* Just punt and use reasonable value */ +# endif /* NBPC */ +# endif /* NBPG */ +# endif /* EXEC_PAGESIZE */ +# endif /* PAGESIZE */ +#endif /* GNU_OUR_PAGESIZE */ + +int +getpagesize (void) +{ + return (GNU_OUR_PAGESIZE); +} + +#else /* VMS */ + +#if 0 /* older distributions of gcc-vms are missing */ +#include +#endif +#ifndef SYI$_PAGE_SIZE /* VMS V5.4 and earlier didn't have this yet */ +#define SYI$_PAGE_SIZE 4452 +#endif +extern unsigned long lib$getsyi(const unsigned short *,...); + +int getpagesize (void) +{ + long pagsiz = 0L; + unsigned short itmcod = SYI$_PAGE_SIZE; + + (void) lib$getsyi (&itmcod, (void *) &pagsiz); + if (pagsiz == 0L) + pagsiz = 512L; /* VAX default */ + return (int) pagsiz; +} + +#endif /* VMS */ diff --git a/external/gpl3/gdb/dist/libiberty/getpwd.c b/external/gpl3/gdb/dist/libiberty/getpwd.c new file mode 100644 index 000000000000..fa5c132fd6b6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getpwd.c @@ -0,0 +1,128 @@ +/* getpwd.c - get the working directory */ + +/* + +@deftypefn Supplemental char* getpwd (void) + +Returns the current working directory. This implementation caches the +result on the assumption that the process will not call @code{chdir} +between calls to @code{getpwd}. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#include +#ifndef errno +extern int errno; +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#if HAVE_SYS_STAT_H +#include +#endif +#if HAVE_LIMITS_H +#include +#endif + +#include "libiberty.h" + +/* Virtually every UN*X system now in common use (except for pre-4.3-tahoe + BSD systems) now provides getcwd as called for by POSIX. Allow for + the few exceptions to the general rule here. */ + +#if !defined(HAVE_GETCWD) && defined(HAVE_GETWD) +/* Prototype in case the system headers doesn't provide it. */ +extern char *getwd (); +#define getcwd(buf,len) getwd(buf) +#endif + +#ifdef MAXPATHLEN +#define GUESSPATHLEN (MAXPATHLEN + 1) +#else +#define GUESSPATHLEN 100 +#endif + +#if !(defined (VMS) || (defined(_WIN32) && !defined(__CYGWIN__))) + +/* Get the working directory. Use the PWD environment variable if it's + set correctly, since this is faster and gives more uniform answers + to the user. Yield the working directory if successful; otherwise, + yield 0 and set errno. */ + +char * +getpwd (void) +{ + static char *pwd; + static int failure_errno; + + char *p = pwd; + size_t s; + struct stat dotstat, pwdstat; + + if (!p && !(errno = failure_errno)) + { + if (! ((p = getenv ("PWD")) != 0 + && *p == '/' + && stat (p, &pwdstat) == 0 + && stat (".", &dotstat) == 0 + && dotstat.st_ino == pwdstat.st_ino + && dotstat.st_dev == pwdstat.st_dev)) + + /* The shortcut didn't work. Try the slow, ``sure'' way. */ + for (s = GUESSPATHLEN; !getcwd (p = XNEWVEC (char, s), s); s *= 2) + { + int e = errno; + free (p); +#ifdef ERANGE + if (e != ERANGE) +#endif + { + errno = failure_errno = e; + p = 0; + break; + } + } + + /* Cache the result. This assumes that the program does + not invoke chdir between calls to getpwd. */ + pwd = p; + } + return p; +} + +#else /* VMS || _WIN32 && !__CYGWIN__ */ + +#ifndef MAXPATHLEN +#define MAXPATHLEN 255 +#endif + +char * +getpwd (void) +{ + static char *pwd = 0; + + if (!pwd) + pwd = getcwd (XNEWVEC (char, MAXPATHLEN + 1), MAXPATHLEN + 1 +#ifdef VMS + , 0 +#endif + ); + return pwd; +} + +#endif /* VMS || _WIN32 && !__CYGWIN__ */ diff --git a/external/gpl3/gdb/dist/libiberty/getruntime.c b/external/gpl3/gdb/dist/libiberty/getruntime.c new file mode 100644 index 000000000000..82f3d2e41858 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/getruntime.c @@ -0,0 +1,116 @@ +/* Return time used so far, in microseconds. + Copyright (C) 1994, 1999, 2002 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" + +#include "ansidecl.h" +#include "libiberty.h" + +/* On some systems (such as WindISS), you must include + to get the definition of "time_t" before you include . */ +#include + +/* There are several ways to get elapsed execution time; unfortunately no + single way is available for all host systems, nor are there reliable + ways to find out which way is correct for a given host. */ + +#ifdef TIME_WITH_SYS_TIME +# include +# include +#else +# if HAVE_SYS_TIME_H +# include +# else +# ifdef HAVE_TIME_H +# include +# endif +# endif +#endif + +#if defined (HAVE_GETRUSAGE) && defined (HAVE_SYS_RESOURCE_H) +#include +#endif + +#ifdef HAVE_TIMES +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include +#endif + +#ifdef HAVE_UNISTD_H +#include +#endif + +/* This is a fallback; if wrong, it will likely make obviously wrong + results. */ + +#ifndef CLOCKS_PER_SEC +#define CLOCKS_PER_SEC 1 +#endif + +#ifdef _SC_CLK_TCK +#define GNU_HZ sysconf(_SC_CLK_TCK) +#else +#ifdef HZ +#define GNU_HZ HZ +#else +#ifdef CLOCKS_PER_SEC +#define GNU_HZ CLOCKS_PER_SEC +#endif +#endif +#endif + +/* + +@deftypefn Replacement long get_run_time (void) + +Returns the time used so far, in microseconds. If possible, this is +the time used by this process, else it is the elapsed time since the +process started. + +@end deftypefn + +*/ + +long +get_run_time (void) +{ +#if defined (HAVE_GETRUSAGE) && defined (HAVE_SYS_RESOURCE_H) + struct rusage rusage; + + getrusage (0, &rusage); + return (rusage.ru_utime.tv_sec * 1000000 + rusage.ru_utime.tv_usec + + rusage.ru_stime.tv_sec * 1000000 + rusage.ru_stime.tv_usec); +#else /* ! HAVE_GETRUSAGE */ +#ifdef HAVE_TIMES + struct tms tms; + + times (&tms); + return (tms.tms_utime + tms.tms_stime) * (1000000 / GNU_HZ); +#else /* ! HAVE_TIMES */ + /* Fall back on clock and hope it's correctly implemented. */ + const long clocks_per_sec = CLOCKS_PER_SEC; + if (clocks_per_sec <= 1000000) + return clock () * (1000000 / clocks_per_sec); + else + return clock () / clocks_per_sec; +#endif /* HAVE_TIMES */ +#endif /* HAVE_GETRUSAGE */ +} diff --git a/external/gpl3/gdb/dist/libiberty/gettimeofday.c b/external/gpl3/gdb/dist/libiberty/gettimeofday.c new file mode 100644 index 000000000000..fca16794028e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/gettimeofday.c @@ -0,0 +1,30 @@ +#include "config.h" +#include "libiberty.h" +#ifdef HAVE_TIME_H +#include +#endif +#ifdef HAVE_SYS_TIME_H +#include +#endif + +/* + +@deftypefn Supplemental int gettimeofday (struct timeval *@var{tp}, void *@var{tz}) + +Writes the current time to @var{tp}. This implementation requires +that @var{tz} be NULL. Returns 0 on success, -1 on failure. + +@end deftypefn + +*/ + +int +gettimeofday (struct timeval *tp, void *tz) +{ + if (tz) + abort (); + tp->tv_usec = 0; + if (time (&tp->tv_sec) == (time_t) -1) + return -1; + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/hashtab.c b/external/gpl3/gdb/dist/libiberty/hashtab.c new file mode 100644 index 000000000000..dfaec0f31aee --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/hashtab.c @@ -0,0 +1,990 @@ +/* An expandable hash tables datatype. + Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Vladimir Makarov (vmakarov@cygnus.com). + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* This package implements basic hash table functionality. It is possible + to search for an entry, create an entry and destroy an entry. + + Elements in the table are generic pointers. + + The size of the table is not fixed; if the occupancy of the table + grows too high the hash table will be expanded. + + The abstract data implementation is based on generalized Algorithm D + from Knuth's book "The art of computer programming". Hash table is + expanded by creation of new hash table and transferring elements from + the old table to the new table. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_MALLOC_H +#include +#endif +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_INTTYPES_H +#include +#endif +#ifdef HAVE_STDINT_H +#include +#endif + +#include + +#include "libiberty.h" +#include "ansidecl.h" +#include "hashtab.h" + +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif + +static unsigned int higher_prime_index (unsigned long); +static hashval_t htab_mod_1 (hashval_t, hashval_t, hashval_t, int); +static hashval_t htab_mod (hashval_t, htab_t); +static hashval_t htab_mod_m2 (hashval_t, htab_t); +static hashval_t hash_pointer (const void *); +static int eq_pointer (const void *, const void *); +static int htab_expand (htab_t); +static PTR *find_empty_slot_for_expand (htab_t, hashval_t); + +/* At some point, we could make these be NULL, and modify the + hash-table routines to handle NULL specially; that would avoid + function-call overhead for the common case of hashing pointers. */ +htab_hash htab_hash_pointer = hash_pointer; +htab_eq htab_eq_pointer = eq_pointer; + +/* Table of primes and multiplicative inverses. + + Note that these are not minimally reduced inverses. Unlike when generating + code to divide by a constant, we want to be able to use the same algorithm + all the time. All of these inverses (are implied to) have bit 32 set. + + For the record, here's the function that computed the table; it's a + vastly simplified version of the function of the same name from gcc. */ + +#if 0 +unsigned int +ceil_log2 (unsigned int x) +{ + int i; + for (i = 31; i >= 0 ; --i) + if (x > (1u << i)) + return i+1; + abort (); +} + +unsigned int +choose_multiplier (unsigned int d, unsigned int *mlp, unsigned char *shiftp) +{ + unsigned long long mhigh; + double nx; + int lgup, post_shift; + int pow, pow2; + int n = 32, precision = 32; + + lgup = ceil_log2 (d); + pow = n + lgup; + pow2 = n + lgup - precision; + + nx = ldexp (1.0, pow) + ldexp (1.0, pow2); + mhigh = nx / d; + + *shiftp = lgup - 1; + *mlp = mhigh; + return mhigh >> 32; +} +#endif + +struct prime_ent +{ + hashval_t prime; + hashval_t inv; + hashval_t inv_m2; /* inverse of prime-2 */ + hashval_t shift; +}; + +static struct prime_ent const prime_tab[] = { + { 7, 0x24924925, 0x9999999b, 2 }, + { 13, 0x3b13b13c, 0x745d1747, 3 }, + { 31, 0x08421085, 0x1a7b9612, 4 }, + { 61, 0x0c9714fc, 0x15b1e5f8, 5 }, + { 127, 0x02040811, 0x0624dd30, 6 }, + { 251, 0x05197f7e, 0x073260a5, 7 }, + { 509, 0x01824366, 0x02864fc8, 8 }, + { 1021, 0x00c0906d, 0x014191f7, 9 }, + { 2039, 0x0121456f, 0x0161e69e, 10 }, + { 4093, 0x00300902, 0x00501908, 11 }, + { 8191, 0x00080041, 0x00180241, 12 }, + { 16381, 0x000c0091, 0x00140191, 13 }, + { 32749, 0x002605a5, 0x002a06e6, 14 }, + { 65521, 0x000f00e2, 0x00110122, 15 }, + { 131071, 0x00008001, 0x00018003, 16 }, + { 262139, 0x00014002, 0x0001c004, 17 }, + { 524287, 0x00002001, 0x00006001, 18 }, + { 1048573, 0x00003001, 0x00005001, 19 }, + { 2097143, 0x00004801, 0x00005801, 20 }, + { 4194301, 0x00000c01, 0x00001401, 21 }, + { 8388593, 0x00001e01, 0x00002201, 22 }, + { 16777213, 0x00000301, 0x00000501, 23 }, + { 33554393, 0x00001381, 0x00001481, 24 }, + { 67108859, 0x00000141, 0x000001c1, 25 }, + { 134217689, 0x000004e1, 0x00000521, 26 }, + { 268435399, 0x00000391, 0x000003b1, 27 }, + { 536870909, 0x00000019, 0x00000029, 28 }, + { 1073741789, 0x0000008d, 0x00000095, 29 }, + { 2147483647, 0x00000003, 0x00000007, 30 }, + /* Avoid "decimal constant so large it is unsigned" for 4294967291. */ + { 0xfffffffb, 0x00000006, 0x00000008, 31 } +}; + +/* The following function returns an index into the above table of the + nearest prime number which is greater than N, and near a power of two. */ + +static unsigned int +higher_prime_index (unsigned long n) +{ + unsigned int low = 0; + unsigned int high = sizeof(prime_tab) / sizeof(prime_tab[0]); + + while (low != high) + { + unsigned int mid = low + (high - low) / 2; + if (n > prime_tab[mid].prime) + low = mid + 1; + else + high = mid; + } + + /* If we've run out of primes, abort. */ + if (n > prime_tab[low].prime) + { + fprintf (stderr, "Cannot find prime bigger than %lu\n", n); + abort (); + } + + return low; +} + +/* Returns a hash code for P. */ + +static hashval_t +hash_pointer (const PTR p) +{ + return (hashval_t) ((intptr_t)p >> 3); +} + +/* Returns non-zero if P1 and P2 are equal. */ + +static int +eq_pointer (const PTR p1, const PTR p2) +{ + return p1 == p2; +} + + +/* The parens around the function names in the next two definitions + are essential in order to prevent macro expansions of the name. + The bodies, however, are expanded as expected, so they are not + recursive definitions. */ + +/* Return the current size of given hash table. */ + +#define htab_size(htab) ((htab)->size) + +size_t +(htab_size) (htab_t htab) +{ + return htab_size (htab); +} + +/* Return the current number of elements in given hash table. */ + +#define htab_elements(htab) ((htab)->n_elements - (htab)->n_deleted) + +size_t +(htab_elements) (htab_t htab) +{ + return htab_elements (htab); +} + +/* Return X % Y. */ + +static inline hashval_t +htab_mod_1 (hashval_t x, hashval_t y, hashval_t inv, int shift) +{ + /* The multiplicative inverses computed above are for 32-bit types, and + requires that we be able to compute a highpart multiply. */ +#ifdef UNSIGNED_64BIT_TYPE + __extension__ typedef UNSIGNED_64BIT_TYPE ull; + if (sizeof (hashval_t) * CHAR_BIT <= 32) + { + hashval_t t1, t2, t3, t4, q, r; + + t1 = ((ull)x * inv) >> 32; + t2 = x - t1; + t3 = t2 >> 1; + t4 = t1 + t3; + q = t4 >> shift; + r = x - (q * y); + + return r; + } +#endif + + /* Otherwise just use the native division routines. */ + return x % y; +} + +/* Compute the primary hash for HASH given HTAB's current size. */ + +static inline hashval_t +htab_mod (hashval_t hash, htab_t htab) +{ + const struct prime_ent *p = &prime_tab[htab->size_prime_index]; + return htab_mod_1 (hash, p->prime, p->inv, p->shift); +} + +/* Compute the secondary hash for HASH given HTAB's current size. */ + +static inline hashval_t +htab_mod_m2 (hashval_t hash, htab_t htab) +{ + const struct prime_ent *p = &prime_tab[htab->size_prime_index]; + return 1 + htab_mod_1 (hash, p->prime - 2, p->inv_m2, p->shift); +} + +/* This function creates table with length slightly longer than given + source length. Created hash table is initiated as empty (all the + hash table entries are HTAB_EMPTY_ENTRY). The function returns the + created hash table, or NULL if memory allocation fails. */ + +htab_t +htab_create_alloc (size_t size, htab_hash hash_f, htab_eq eq_f, + htab_del del_f, htab_alloc alloc_f, htab_free free_f) +{ + return htab_create_typed_alloc (size, hash_f, eq_f, del_f, alloc_f, alloc_f, + free_f); +} + +/* As above, but uses the variants of ALLOC_F and FREE_F which accept + an extra argument. */ + +htab_t +htab_create_alloc_ex (size_t size, htab_hash hash_f, htab_eq eq_f, + htab_del del_f, void *alloc_arg, + htab_alloc_with_arg alloc_f, + htab_free_with_arg free_f) +{ + htab_t result; + unsigned int size_prime_index; + + size_prime_index = higher_prime_index (size); + size = prime_tab[size_prime_index].prime; + + result = (htab_t) (*alloc_f) (alloc_arg, 1, sizeof (struct htab)); + if (result == NULL) + return NULL; + result->entries = (PTR *) (*alloc_f) (alloc_arg, size, sizeof (PTR)); + if (result->entries == NULL) + { + if (free_f != NULL) + (*free_f) (alloc_arg, result); + return NULL; + } + result->size = size; + result->size_prime_index = size_prime_index; + result->hash_f = hash_f; + result->eq_f = eq_f; + result->del_f = del_f; + result->alloc_arg = alloc_arg; + result->alloc_with_arg_f = alloc_f; + result->free_with_arg_f = free_f; + return result; +} + +/* + +@deftypefn Supplemental htab_t htab_create_typed_alloc (size_t @var{size}, @ +htab_hash @var{hash_f}, htab_eq @var{eq_f}, htab_del @var{del_f}, @ +htab_alloc @var{alloc_tab_f}, htab_alloc @var{alloc_f}, @ +htab_free @var{free_f}) + +This function creates a hash table that uses two different allocators +@var{alloc_tab_f} and @var{alloc_f} to use for allocating the table itself +and its entries respectively. This is useful when variables of different +types need to be allocated with different allocators. + +The created hash table is slightly larger than @var{size} and it is +initially empty (all the hash table entries are @code{HTAB_EMPTY_ENTRY}). +The function returns the created hash table, or @code{NULL} if memory +allocation fails. + +@end deftypefn + +*/ + +htab_t +htab_create_typed_alloc (size_t size, htab_hash hash_f, htab_eq eq_f, + htab_del del_f, htab_alloc alloc_tab_f, + htab_alloc alloc_f, htab_free free_f) +{ + htab_t result; + unsigned int size_prime_index; + + size_prime_index = higher_prime_index (size); + size = prime_tab[size_prime_index].prime; + + result = (htab_t) (*alloc_tab_f) (1, sizeof (struct htab)); + if (result == NULL) + return NULL; + result->entries = (PTR *) (*alloc_f) (size, sizeof (PTR)); + if (result->entries == NULL) + { + if (free_f != NULL) + (*free_f) (result); + return NULL; + } + result->size = size; + result->size_prime_index = size_prime_index; + result->hash_f = hash_f; + result->eq_f = eq_f; + result->del_f = del_f; + result->alloc_f = alloc_f; + result->free_f = free_f; + return result; +} + + +/* Update the function pointers and allocation parameter in the htab_t. */ + +void +htab_set_functions_ex (htab_t htab, htab_hash hash_f, htab_eq eq_f, + htab_del del_f, PTR alloc_arg, + htab_alloc_with_arg alloc_f, htab_free_with_arg free_f) +{ + htab->hash_f = hash_f; + htab->eq_f = eq_f; + htab->del_f = del_f; + htab->alloc_arg = alloc_arg; + htab->alloc_with_arg_f = alloc_f; + htab->free_with_arg_f = free_f; +} + +/* These functions exist solely for backward compatibility. */ + +#undef htab_create +htab_t +htab_create (size_t size, htab_hash hash_f, htab_eq eq_f, htab_del del_f) +{ + return htab_create_alloc (size, hash_f, eq_f, del_f, xcalloc, free); +} + +htab_t +htab_try_create (size_t size, htab_hash hash_f, htab_eq eq_f, htab_del del_f) +{ + return htab_create_alloc (size, hash_f, eq_f, del_f, calloc, free); +} + +/* This function frees all memory allocated for given hash table. + Naturally the hash table must already exist. */ + +void +htab_delete (htab_t htab) +{ + size_t size = htab_size (htab); + PTR *entries = htab->entries; + int i; + + if (htab->del_f) + for (i = size - 1; i >= 0; i--) + if (entries[i] != HTAB_EMPTY_ENTRY && entries[i] != HTAB_DELETED_ENTRY) + (*htab->del_f) (entries[i]); + + if (htab->free_f != NULL) + { + (*htab->free_f) (entries); + (*htab->free_f) (htab); + } + else if (htab->free_with_arg_f != NULL) + { + (*htab->free_with_arg_f) (htab->alloc_arg, entries); + (*htab->free_with_arg_f) (htab->alloc_arg, htab); + } +} + +/* This function clears all entries in the given hash table. */ + +void +htab_empty (htab_t htab) +{ + size_t size = htab_size (htab); + PTR *entries = htab->entries; + int i; + + if (htab->del_f) + for (i = size - 1; i >= 0; i--) + if (entries[i] != HTAB_EMPTY_ENTRY && entries[i] != HTAB_DELETED_ENTRY) + (*htab->del_f) (entries[i]); + + /* Instead of clearing megabyte, downsize the table. */ + if (size > 1024*1024 / sizeof (PTR)) + { + int nindex = higher_prime_index (1024 / sizeof (PTR)); + int nsize = prime_tab[nindex].prime; + + if (htab->free_f != NULL) + (*htab->free_f) (htab->entries); + else if (htab->free_with_arg_f != NULL) + (*htab->free_with_arg_f) (htab->alloc_arg, htab->entries); + if (htab->alloc_with_arg_f != NULL) + htab->entries = (PTR *) (*htab->alloc_with_arg_f) (htab->alloc_arg, nsize, + sizeof (PTR *)); + else + htab->entries = (PTR *) (*htab->alloc_f) (nsize, sizeof (PTR *)); + htab->size = nsize; + htab->size_prime_index = nindex; + } + else + memset (entries, 0, size * sizeof (PTR)); + htab->n_deleted = 0; + htab->n_elements = 0; +} + +/* Similar to htab_find_slot, but without several unwanted side effects: + - Does not call htab->eq_f when it finds an existing entry. + - Does not change the count of elements/searches/collisions in the + hash table. + This function also assumes there are no deleted entries in the table. + HASH is the hash value for the element to be inserted. */ + +static PTR * +find_empty_slot_for_expand (htab_t htab, hashval_t hash) +{ + hashval_t index = htab_mod (hash, htab); + size_t size = htab_size (htab); + PTR *slot = htab->entries + index; + hashval_t hash2; + + if (*slot == HTAB_EMPTY_ENTRY) + return slot; + else if (*slot == HTAB_DELETED_ENTRY) + abort (); + + hash2 = htab_mod_m2 (hash, htab); + for (;;) + { + index += hash2; + if (index >= size) + index -= size; + + slot = htab->entries + index; + if (*slot == HTAB_EMPTY_ENTRY) + return slot; + else if (*slot == HTAB_DELETED_ENTRY) + abort (); + } +} + +/* The following function changes size of memory allocated for the + entries and repeatedly inserts the table elements. The occupancy + of the table after the call will be about 50%. Naturally the hash + table must already exist. Remember also that the place of the + table entries is changed. If memory allocation failures are allowed, + this function will return zero, indicating that the table could not be + expanded. If all goes well, it will return a non-zero value. */ + +static int +htab_expand (htab_t htab) +{ + PTR *oentries; + PTR *olimit; + PTR *p; + PTR *nentries; + size_t nsize, osize, elts; + unsigned int oindex, nindex; + + oentries = htab->entries; + oindex = htab->size_prime_index; + osize = htab->size; + olimit = oentries + osize; + elts = htab_elements (htab); + + /* Resize only when table after removal of unused elements is either + too full or too empty. */ + if (elts * 2 > osize || (elts * 8 < osize && osize > 32)) + { + nindex = higher_prime_index (elts * 2); + nsize = prime_tab[nindex].prime; + } + else + { + nindex = oindex; + nsize = osize; + } + + if (htab->alloc_with_arg_f != NULL) + nentries = (PTR *) (*htab->alloc_with_arg_f) (htab->alloc_arg, nsize, + sizeof (PTR *)); + else + nentries = (PTR *) (*htab->alloc_f) (nsize, sizeof (PTR *)); + if (nentries == NULL) + return 0; + htab->entries = nentries; + htab->size = nsize; + htab->size_prime_index = nindex; + htab->n_elements -= htab->n_deleted; + htab->n_deleted = 0; + + p = oentries; + do + { + PTR x = *p; + + if (x != HTAB_EMPTY_ENTRY && x != HTAB_DELETED_ENTRY) + { + PTR *q = find_empty_slot_for_expand (htab, (*htab->hash_f) (x)); + + *q = x; + } + + p++; + } + while (p < olimit); + + if (htab->free_f != NULL) + (*htab->free_f) (oentries); + else if (htab->free_with_arg_f != NULL) + (*htab->free_with_arg_f) (htab->alloc_arg, oentries); + return 1; +} + +/* This function searches for a hash table entry equal to the given + element. It cannot be used to insert or delete an element. */ + +PTR +htab_find_with_hash (htab_t htab, const PTR element, hashval_t hash) +{ + hashval_t index, hash2; + size_t size; + PTR entry; + + htab->searches++; + size = htab_size (htab); + index = htab_mod (hash, htab); + + entry = htab->entries[index]; + if (entry == HTAB_EMPTY_ENTRY + || (entry != HTAB_DELETED_ENTRY && (*htab->eq_f) (entry, element))) + return entry; + + hash2 = htab_mod_m2 (hash, htab); + for (;;) + { + htab->collisions++; + index += hash2; + if (index >= size) + index -= size; + + entry = htab->entries[index]; + if (entry == HTAB_EMPTY_ENTRY + || (entry != HTAB_DELETED_ENTRY && (*htab->eq_f) (entry, element))) + return entry; + } +} + +/* Like htab_find_slot_with_hash, but compute the hash value from the + element. */ + +PTR +htab_find (htab_t htab, const PTR element) +{ + return htab_find_with_hash (htab, element, (*htab->hash_f) (element)); +} + +/* This function searches for a hash table slot containing an entry + equal to the given element. To delete an entry, call this with + insert=NO_INSERT, then call htab_clear_slot on the slot returned + (possibly after doing some checks). To insert an entry, call this + with insert=INSERT, then write the value you want into the returned + slot. When inserting an entry, NULL may be returned if memory + allocation fails. */ + +PTR * +htab_find_slot_with_hash (htab_t htab, const PTR element, + hashval_t hash, enum insert_option insert) +{ + PTR *first_deleted_slot; + hashval_t index, hash2; + size_t size; + PTR entry; + + size = htab_size (htab); + if (insert == INSERT && size * 3 <= htab->n_elements * 4) + { + if (htab_expand (htab) == 0) + return NULL; + size = htab_size (htab); + } + + index = htab_mod (hash, htab); + + htab->searches++; + first_deleted_slot = NULL; + + entry = htab->entries[index]; + if (entry == HTAB_EMPTY_ENTRY) + goto empty_entry; + else if (entry == HTAB_DELETED_ENTRY) + first_deleted_slot = &htab->entries[index]; + else if ((*htab->eq_f) (entry, element)) + return &htab->entries[index]; + + hash2 = htab_mod_m2 (hash, htab); + for (;;) + { + htab->collisions++; + index += hash2; + if (index >= size) + index -= size; + + entry = htab->entries[index]; + if (entry == HTAB_EMPTY_ENTRY) + goto empty_entry; + else if (entry == HTAB_DELETED_ENTRY) + { + if (!first_deleted_slot) + first_deleted_slot = &htab->entries[index]; + } + else if ((*htab->eq_f) (entry, element)) + return &htab->entries[index]; + } + + empty_entry: + if (insert == NO_INSERT) + return NULL; + + if (first_deleted_slot) + { + htab->n_deleted--; + *first_deleted_slot = HTAB_EMPTY_ENTRY; + return first_deleted_slot; + } + + htab->n_elements++; + return &htab->entries[index]; +} + +/* Like htab_find_slot_with_hash, but compute the hash value from the + element. */ + +PTR * +htab_find_slot (htab_t htab, const PTR element, enum insert_option insert) +{ + return htab_find_slot_with_hash (htab, element, (*htab->hash_f) (element), + insert); +} + +/* This function deletes an element with the given value from hash + table (the hash is computed from the element). If there is no matching + element in the hash table, this function does nothing. */ + +void +htab_remove_elt (htab_t htab, PTR element) +{ + htab_remove_elt_with_hash (htab, element, (*htab->hash_f) (element)); +} + + +/* This function deletes an element with the given value from hash + table. If there is no matching element in the hash table, this + function does nothing. */ + +void +htab_remove_elt_with_hash (htab_t htab, PTR element, hashval_t hash) +{ + PTR *slot; + + slot = htab_find_slot_with_hash (htab, element, hash, NO_INSERT); + if (*slot == HTAB_EMPTY_ENTRY) + return; + + if (htab->del_f) + (*htab->del_f) (*slot); + + *slot = HTAB_DELETED_ENTRY; + htab->n_deleted++; +} + +/* This function clears a specified slot in a hash table. It is + useful when you've already done the lookup and don't want to do it + again. */ + +void +htab_clear_slot (htab_t htab, PTR *slot) +{ + if (slot < htab->entries || slot >= htab->entries + htab_size (htab) + || *slot == HTAB_EMPTY_ENTRY || *slot == HTAB_DELETED_ENTRY) + abort (); + + if (htab->del_f) + (*htab->del_f) (*slot); + + *slot = HTAB_DELETED_ENTRY; + htab->n_deleted++; +} + +/* This function scans over the entire hash table calling + CALLBACK for each live entry. If CALLBACK returns false, + the iteration stops. INFO is passed as CALLBACK's second + argument. */ + +void +htab_traverse_noresize (htab_t htab, htab_trav callback, PTR info) +{ + PTR *slot; + PTR *limit; + + slot = htab->entries; + limit = slot + htab_size (htab); + + do + { + PTR x = *slot; + + if (x != HTAB_EMPTY_ENTRY && x != HTAB_DELETED_ENTRY) + if (!(*callback) (slot, info)) + break; + } + while (++slot < limit); +} + +/* Like htab_traverse_noresize, but does resize the table when it is + too empty to improve effectivity of subsequent calls. */ + +void +htab_traverse (htab_t htab, htab_trav callback, PTR info) +{ + size_t size = htab_size (htab); + if (htab_elements (htab) * 8 < size && size > 32) + htab_expand (htab); + + htab_traverse_noresize (htab, callback, info); +} + +/* Return the fraction of fixed collisions during all work with given + hash table. */ + +double +htab_collisions (htab_t htab) +{ + if (htab->searches == 0) + return 0.0; + + return (double) htab->collisions / (double) htab->searches; +} + +/* Hash P as a null-terminated string. + + Copied from gcc/hashtable.c. Zack had the following to say with respect + to applicability, though note that unlike hashtable.c, this hash table + implementation re-hashes rather than chain buckets. + + http://gcc.gnu.org/ml/gcc-patches/2001-08/msg01021.html + From: Zack Weinberg + Date: Fri, 17 Aug 2001 02:15:56 -0400 + + I got it by extracting all the identifiers from all the source code + I had lying around in mid-1999, and testing many recurrences of + the form "H_n = H_{n-1} * K + c_n * L + M" where K, L, M were either + prime numbers or the appropriate identity. This was the best one. + I don't remember exactly what constituted "best", except I was + looking at bucket-length distributions mostly. + + So it should be very good at hashing identifiers, but might not be + as good at arbitrary strings. + + I'll add that it thoroughly trounces the hash functions recommended + for this use at http://burtleburtle.net/bob/hash/index.html, both + on speed and bucket distribution. I haven't tried it against the + function they just started using for Perl's hashes. */ + +hashval_t +htab_hash_string (const PTR p) +{ + const unsigned char *str = (const unsigned char *) p; + hashval_t r = 0; + unsigned char c; + + while ((c = *str++) != 0) + r = r * 67 + c - 113; + + return r; +} + +/* DERIVED FROM: +-------------------------------------------------------------------- +lookup2.c, by Bob Jenkins, December 1996, Public Domain. +hash(), hash2(), hash3, and mix() are externally useful functions. +Routines to test the hash are included if SELF_TEST is defined. +You can use this free for any purpose. It has no warranty. +-------------------------------------------------------------------- +*/ + +/* +-------------------------------------------------------------------- +mix -- mix 3 32-bit values reversibly. +For every delta with one or two bit set, and the deltas of all three + high bits or all three low bits, whether the original value of a,b,c + is almost all zero or is uniformly distributed, +* If mix() is run forward or backward, at least 32 bits in a,b,c + have at least 1/4 probability of changing. +* If mix() is run forward, every bit of c will change between 1/3 and + 2/3 of the time. (Well, 22/100 and 78/100 for some 2-bit deltas.) +mix() was built out of 36 single-cycle latency instructions in a + structure that could supported 2x parallelism, like so: + a -= b; + a -= c; x = (c>>13); + b -= c; a ^= x; + b -= a; x = (a<<8); + c -= a; b ^= x; + c -= b; x = (b>>13); + ... + Unfortunately, superscalar Pentiums and Sparcs can't take advantage + of that parallelism. They've also turned some of those single-cycle + latency instructions into multi-cycle latency instructions. Still, + this is the fastest good hash I could find. There were about 2^^68 + to choose from. I only looked at a billion or so. +-------------------------------------------------------------------- +*/ +/* same, but slower, works on systems that might have 8 byte hashval_t's */ +#define mix(a,b,c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<< 8); \ + c -= a; c -= b; c ^= ((b&0xffffffff)>>13); \ + a -= b; a -= c; a ^= ((c&0xffffffff)>>12); \ + b -= c; b -= a; b = (b ^ (a<<16)) & 0xffffffff; \ + c -= a; c -= b; c = (c ^ (b>> 5)) & 0xffffffff; \ + a -= b; a -= c; a = (a ^ (c>> 3)) & 0xffffffff; \ + b -= c; b -= a; b = (b ^ (a<<10)) & 0xffffffff; \ + c -= a; c -= b; c = (c ^ (b>>15)) & 0xffffffff; \ +} + +/* +-------------------------------------------------------------------- +hash() -- hash a variable-length key into a 32-bit value + k : the key (the unaligned variable-length array of bytes) + len : the length of the key, counting by bytes + level : can be any 4-byte value +Returns a 32-bit value. Every bit of the key affects every bit of +the return value. Every 1-bit and 2-bit delta achieves avalanche. +About 36+6len instructions. + +The best hash table sizes are powers of 2. There is no need to do +mod a prime (mod is sooo slow!). If you need less than 32 bits, +use a bitmask. For example, if you need only 10 bits, do + h = (h & hashmask(10)); +In which case, the hash table should have hashsize(10) elements. + +If you are hashing n strings (ub1 **)k, do it like this: + for (i=0, h=0; i= 12) /* aligned */ + { + a += *(hashval_t *)(k+0); + b += *(hashval_t *)(k+4); + c += *(hashval_t *)(k+8); + mix(a,b,c); + k += 12; len -= 12; + } + else /* unaligned */ +#endif + while (len >= 12) + { + a += (k[0] +((hashval_t)k[1]<<8) +((hashval_t)k[2]<<16) +((hashval_t)k[3]<<24)); + b += (k[4] +((hashval_t)k[5]<<8) +((hashval_t)k[6]<<16) +((hashval_t)k[7]<<24)); + c += (k[8] +((hashval_t)k[9]<<8) +((hashval_t)k[10]<<16)+((hashval_t)k[11]<<24)); + mix(a,b,c); + k += 12; len -= 12; + } + + /*------------------------------------- handle the last 11 bytes */ + c += length; + switch(len) /* all the case statements fall through */ + { + case 11: c+=((hashval_t)k[10]<<24); + case 10: c+=((hashval_t)k[9]<<16); + case 9 : c+=((hashval_t)k[8]<<8); + /* the first byte of c is reserved for the length */ + case 8 : b+=((hashval_t)k[7]<<24); + case 7 : b+=((hashval_t)k[6]<<16); + case 6 : b+=((hashval_t)k[5]<<8); + case 5 : b+=k[4]; + case 4 : a+=((hashval_t)k[3]<<24); + case 3 : a+=((hashval_t)k[2]<<16); + case 2 : a+=((hashval_t)k[1]<<8); + case 1 : a+=k[0]; + /* case 0: nothing left to add */ + } + mix(a,b,c); + /*-------------------------------------------- report the result */ + return c; +} diff --git a/external/gpl3/gdb/dist/libiberty/hex.c b/external/gpl3/gdb/dist/libiberty/hex.c new file mode 100644 index 000000000000..5eeafdbd1586 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/hex.c @@ -0,0 +1,192 @@ +/* Hex character manipulation support. + Copyright (C) 1995, 2001 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include /* for EOF */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "libiberty.h" +#include "safe-ctype.h" /* for HOST_CHARSET_ASCII */ + +#if EOF != -1 + #error "hex.c requires EOF == -1" +#endif + +/* + +@deftypefn Extension void hex_init (void) + +Initializes the array mapping the current character set to +corresponding hex values. This function must be called before any +call to @code{hex_p} or @code{hex_value}. If you fail to call it, a +default ASCII-based table will normally be used on ASCII systems. + +@end deftypefn + +@deftypefn Extension int hex_p (int @var{c}) + +Evaluates to non-zero if the given character is a valid hex character, +or zero if it is not. Note that the value you pass will be cast to +@code{unsigned char} within the macro. + +@end deftypefn + +@deftypefn Extension {unsigned int} hex_value (int @var{c}) + +Returns the numeric equivalent of the given character when interpreted +as a hexadecimal digit. The result is undefined if you pass an +invalid hex digit. Note that the value you pass will be cast to +@code{unsigned char} within the macro. + +The @code{hex_value} macro returns @code{unsigned int}, rather than +signed @code{int}, to make it easier to use in parsing addresses from +hex dump files: a signed @code{int} would be sign-extended when +converted to a wider unsigned type --- like @code{bfd_vma}, on some +systems. + +@end deftypefn + +@undocumented _hex_array_size +@undocumented _hex_bad +@undocumented _hex_value + +*/ + + +/* Are we ASCII? */ +#if HOST_CHARSET == HOST_CHARSET_ASCII + +const unsigned char _hex_value[_hex_array_size] = +{ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* NUL SOH STX ETX */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* EOT ENQ ACK BEL */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* BS HT LF VT */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* FF CR SO SI */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* DLE DC1 DC2 DC3 */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* DC4 NAK SYN ETB */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* CAN EM SUB ESC */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* FS GS RS US */ + + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* SP ! " # */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* $ % & ' */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* ( ) * + */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* , - . / */ + 0, 1, 2, 3, /* 0 1 2 3 */ + 4, 5, 6, 7, /* 4 5 6 7 */ + 8, 9, _hex_bad, _hex_bad, /* 8 9 : ; */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* < = > ? */ + + _hex_bad, 10, 11, 12, /* @ A B C */ + 13, 14, 15, _hex_bad, /* D E F G */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* H I J K */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* L M N O */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* P Q R S */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* T U V W */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* X Y Z [ */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* \ ] ^ _ */ + + _hex_bad, 10, 11, 12, /* ` a b c */ + 13, 14, 15, _hex_bad, /* d e f g */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* h i j k */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* l m n o */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* p q r s */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* t u v w */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* x y z { */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, /* | } ~ DEL */ + + /* The high half of unsigned char, all values are _hex_bad. */ + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, + _hex_bad, _hex_bad, _hex_bad, _hex_bad, +}; +#define HEX_TABLE_INITIALIZED + +#else + +unsigned char _hex_value[_hex_array_size]; + +#endif /* not ASCII */ + +void +hex_init (void) +{ +#ifndef HEX_TABLE_INITIALIZED + int i; + + for (i=0; i<_hex_array_size; i++) + { + switch (i) + { + case '0': _hex_value[i] = 0; break; + case '1': _hex_value[i] = 1; break; + case '2': _hex_value[i] = 2; break; + case '3': _hex_value[i] = 3; break; + case '4': _hex_value[i] = 4; break; + case '5': _hex_value[i] = 5; break; + case '6': _hex_value[i] = 6; break; + case '7': _hex_value[i] = 7; break; + case '8': _hex_value[i] = 8; break; + case '9': _hex_value[i] = 9; break; + + case 'a': case 'A': _hex_value[i] = 10; break; + case 'b': case 'B': _hex_value[i] = 11; break; + case 'c': case 'C': _hex_value[i] = 12; break; + case 'd': case 'D': _hex_value[i] = 13; break; + case 'e': case 'E': _hex_value[i] = 14; break; + case 'f': case 'F': _hex_value[i] = 15; break; + + default: + _hex_value[i] = _hex_bad; + break; + } + } +#endif +} diff --git a/external/gpl3/gdb/dist/libiberty/index.c b/external/gpl3/gdb/dist/libiberty/index.c new file mode 100644 index 000000000000..acd0a45fc029 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/index.c @@ -0,0 +1,21 @@ +/* Stub implementation of (obsolete) index(). */ + +/* + +@deftypefn Supplemental char* index (char *@var{s}, int @var{c}) + +Returns a pointer to the first occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. The use of @code{index} is +deprecated in new programs in favor of @code{strchr}. + +@end deftypefn + +*/ + +extern char * strchr(const char *, int); + +char * +index (const char *s, int c) +{ + return strchr (s, c); +} diff --git a/external/gpl3/gdb/dist/libiberty/insque.c b/external/gpl3/gdb/dist/libiberty/insque.c new file mode 100644 index 000000000000..fd02357bb239 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/insque.c @@ -0,0 +1,51 @@ +/* insque(3C) routines + This file is in the public domain. */ + +/* + +@deftypefn Supplemental void insque (struct qelem *@var{elem}, @ + struct qelem *@var{pred}) +@deftypefnx Supplemental void remque (struct qelem *@var{elem}) + +Routines to manipulate queues built from doubly linked lists. The +@code{insque} routine inserts @var{elem} in the queue immediately +after @var{pred}. The @code{remque} routine removes @var{elem} from +its containing queue. These routines expect to be passed pointers to +structures which have as their first members a forward pointer and a +back pointer, like this prototype (although no prototype is provided): + +@example +struct qelem @{ + struct qelem *q_forw; + struct qelem *q_back; + char q_data[]; +@}; +@end example + +@end deftypefn + +*/ + + +struct qelem { + struct qelem *q_forw; + struct qelem *q_back; +}; + + +void +insque (struct qelem *elem, struct qelem *pred) +{ + elem -> q_forw = pred -> q_forw; + pred -> q_forw -> q_back = elem; + elem -> q_back = pred; + pred -> q_forw = elem; +} + + +void +remque (struct qelem *elem) +{ + elem -> q_forw -> q_back = elem -> q_back; + elem -> q_back -> q_forw = elem -> q_forw; +} diff --git a/external/gpl3/gdb/dist/libiberty/lbasename.c b/external/gpl3/gdb/dist/libiberty/lbasename.c new file mode 100644 index 000000000000..87c50faad403 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/lbasename.c @@ -0,0 +1,84 @@ +/* Libiberty basename. Like basename, but is not overridden by the + system C library. + Copyright (C) 2001, 2002, 2010 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Replacement {const char*} lbasename (const char *@var{name}) + +Given a pointer to a string containing a typical pathname +(@samp{/usr/src/cmd/ls/ls.c} for example), returns a pointer to the +last component of the pathname (@samp{ls.c} in this case). The +returned pointer is guaranteed to lie within the original +string. This latter fact is not true of many vendor C +libraries, which return special strings or modify the passed +strings for particular input. + +In particular, the empty string returns the same empty string, +and a path ending in @code{/} returns the empty string after it. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "filenames.h" + +const char * +unix_lbasename (const char *name) +{ + const char *base; + + for (base = name; *name; name++) + if (IS_UNIX_DIR_SEPARATOR (*name)) + base = name + 1; + + return base; +} + +const char * +dos_lbasename (const char *name) +{ + const char *base; + + /* Skip over a possible disk name. */ + if (ISALPHA (name[0]) && name[1] == ':') + name += 2; + + for (base = name; *name; name++) + if (IS_DOS_DIR_SEPARATOR (*name)) + base = name + 1; + + return base; +} + +const char * +lbasename (const char *name) +{ +#if defined (HAVE_DOS_BASED_FILE_SYSTEM) + return dos_lbasename (name); +#else + return unix_lbasename (name); +#endif +} diff --git a/external/gpl3/gdb/dist/libiberty/libiberty.texi b/external/gpl3/gdb/dist/libiberty/libiberty.texi new file mode 100644 index 000000000000..74f70d2bd5af --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/libiberty.texi @@ -0,0 +1,318 @@ +\input texinfo @c -*-texinfo-*- +@c %**start of header +@setfilename libiberty.info +@settitle @sc{gnu} libiberty +@c %**end of header + +@syncodeindex fn cp +@syncodeindex vr cp +@syncodeindex pg cp + +@finalout +@c %**end of header + +@dircategory GNU libraries +@direntry +* Libiberty: (libiberty). Library of utility functions which + are missing or broken on some systems. +@end direntry + +@macro libib +@code{libiberty} +@end macro + +@ifinfo +This manual describes the GNU @libib library of utility subroutines. + +Copyright @copyright{} 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, +2009, 2010 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 + or any later version published by the Free Software Foundation; + with no Invariant Sections, with no Front-Cover Texts, and with no + Back-Cover Texts. A copy of the license is included in the + section entitled ``GNU Free Documentation License''. + +@ignore +Permission is granted to process this file through TeX and print the +results, provided the printed document carries a copying permission +notice identical to this one except for the removal of this paragraph +(this paragraph not being relevant to the printed manual). + +@end ignore +@end ifinfo + + +@titlepage +@title @sc{gnu} libiberty +@author Phil Edwards et al. +@page + + +@vskip 0pt plus 1filll +Copyright @copyright{} 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, +2009, 2010 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 + or any later version published by the Free Software Foundation; + with no Invariant Sections, with no Front-Cover Texts, and with no + Back-Cover Texts. A copy of the license is included in the + section entitled ``GNU Free Documentation License''. + +@end titlepage +@contents +@page + +@ifnottex +@node Top,Using,, +@top Introduction + +The @libib{} library is a collection of subroutines used by various +GNU programs. It is available under the Library General Public +License; for more information, see @ref{Library Copying}. + +@end ifnottex + +@menu +* Using:: How to use libiberty in your code. + +* Overview:: Overview of available function groups. + +* Functions:: Available functions, macros, and global variables. + +* Obstacks:: Object Stacks. + +* Licenses:: The various licenses under which libiberty sources are + distributed. + +* Index:: Index of functions and categories. +@end menu + +@node Using +@chapter Using +@cindex using libiberty +@cindex libiberty usage +@cindex how to use + +@c THIS SECTION IS CRAP AND NEEDS REWRITING BADLY. + +To date, @libib{} is generally not installed on its own. It has evolved +over years but does not have its own version number nor release schedule. + +Possibly the easiest way to use @libib{} in your projects is to drop the +@libib{} code into your project's sources, and to build the library along +with your own sources; the library would then be linked in at the end. This +prevents any possible version mismatches with other copies of libiberty +elsewhere on the system. + +Passing @option{--enable-install-libiberty} to the @command{configure} +script when building @libib{} causes the header files and archive library +to be installed when @kbd{make install} is run. This option also takes +an (optional) argument to specify the installation location, in the same +manner as @option{--prefix}. + +For your own projects, an approach which offers stability and flexibility +is to include @libib{} with your code, but allow the end user to optionally +choose to use a previously-installed version instead. In this way the +user may choose (for example) to install @libib{} as part of GCC, and use +that version for all software built with that compiler. (This approach +has proven useful with software using the GNU @code{readline} library.) + +Making use of @libib{} code usually requires that you include one or more +header files from the @libib{} distribution. (They will be named as +necessary in the function descriptions.) At link time, you will need to +add @option{-liberty} to your link command invocation. + + +@node Overview +@chapter Overview + +Functions contained in @libib{} can be divided into three general categories. + + +@menu +* Supplemental Functions:: Providing functions which don't exist + on older operating systems. + +* Replacement Functions:: These functions are sometimes buggy or + unpredictable on some operating systems. + +* Extensions:: Functions which provide useful extensions + or safety wrappers around existing code. +@end menu + +@node Supplemental Functions +@section Supplemental Functions +@cindex supplemental functions +@cindex functions, supplemental +@cindex functions, missing + +Certain operating systems do not provide functions which have since +become standardized, or at least common. For example, the Single +Unix Specification Version 2 requires that the @code{basename} +function be provided, but an OS which predates that specification +might not have this function. This should not prevent well-written +code from running on such a system. + +Similarly, some functions exist only among a particular ``flavor'' +or ``family'' of operating systems. As an example, the @code{bzero} +function is often not present on systems outside the BSD-derived +family of systems. + +Many such functions are provided in @libib{}. They are quickly +listed here with little description, as systems which lack them +become less and less common. Each function @var{foo} is implemented +in @file{@var{foo}.c} but not declared in any @libib{} header file; more +comments and caveats for each function's implementation are often +available in the source file. Generally, the function can simply +be declared as @code{extern}. + + + +@node Replacement Functions +@section Replacement Functions +@cindex replacement functions +@cindex functions, replacement + +Some functions have extremely limited implementations on different +platforms. Other functions are tedious to use correctly; for example, +proper use of @code{malloc} calls for the return value to be checked and +appropriate action taken if memory has been exhausted. A group of +``replacement functions'' is available in @libib{} to address these issues +for some of the most commonly used subroutines. + +All of these functions are declared in the @file{libiberty.h} header +file. Many of the implementations will use preprocessor macros set by +GNU Autoconf, if you decide to make use of that program. Some of these +functions may call one another. + + +@menu +* Memory Allocation:: Testing and handling failed memory + requests automatically. +* Exit Handlers:: Calling routines on program exit. +* Error Reporting:: Mapping errno and signal numbers to + more useful string formats. +@end menu + +@node Memory Allocation +@subsection Memory Allocation +@cindex memory allocation + +The functions beginning with the letter @samp{x} are wrappers around +standard functions; the functions provided by the system environment +are called and their results checked before the results are passed back +to client code. If the standard functions fail, these wrappers will +terminate the program. Thus, these versions can be used with impunity. + + +@node Exit Handlers +@subsection Exit Handlers +@cindex exit handlers + +The existence and implementation of the @code{atexit} routine varies +amongst the flavors of Unix. @libib{} provides an unvarying dependable +implementation via @code{xatexit} and @code{xexit}. + + +@node Error Reporting +@subsection Error Reporting +@cindex error reporting + +These are a set of routines to facilitate programming with the system +@code{errno} interface. The @libib{} source file @file{strerror.c} +contains a good deal of documentation for these functions. + +@c signal stuff + + +@node Extensions +@section Extensions +@cindex extensions +@cindex functions, extension + +@libib{} includes additional functionality above and beyond standard +functions, which has proven generically useful in GNU programs, such as +obstacks and regex. These functions are often copied from other +projects as they gain popularity, and are included here to provide a +central location from which to use, maintain, and distribute them. + +@menu +* Obstacks:: Stacks of arbitrary objects. +@end menu + +@c This is generated from the glibc manual using a make-obstacks-texi.sh +@c script of Phil's. Hope it's accurate. +@include obstacks.texi + +@node Functions +@chapter Function, Variable, and Macro Listing. +@include functions.texi + +@node Licenses +@appendix Licenses + +@menu + +* Library Copying:: The GNU Library General Public License +* BSD:: Regents of the University of California + +@end menu + +@c This takes care of Library Copying. It is the copying-lib.texi from the +@c GNU web site, with its @node line altered to make makeinfo shut up. +@include copying-lib.texi + +@page +@node BSD +@appendixsec BSD + +Copyright @copyright{} 1990 Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +@enumerate + +@item +Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + +@item +Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +@item +[rescinded 22 July 1999] + +@item +Neither the name of the University nor the names of its contributors +may be used to endorse or promote products derived from this software +without specific prior written permission. + +@end enumerate + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +@node Index +@unnumbered Index + +@printindex cp + +@bye + diff --git a/external/gpl3/gdb/dist/libiberty/lrealpath.c b/external/gpl3/gdb/dist/libiberty/lrealpath.c new file mode 100644 index 000000000000..b27c8de990e9 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/lrealpath.c @@ -0,0 +1,157 @@ +/* Libiberty realpath. Like realpath, but more consistent behavior. + Based on gdb_realpath from GDB. + + Copyright 2003 Free Software Foundation, Inc. + + This file is part of the libiberty library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Replacement {const char*} lrealpath (const char *@var{name}) + +Given a pointer to a string containing a pathname, returns a canonical +version of the filename. Symlinks will be resolved, and ``.'' and ``..'' +components will be simplified. The returned value will be allocated using +@code{malloc}, or @code{NULL} will be returned on a memory allocation error. + +@end deftypefn + +*/ + +#include "config.h" +#include "ansidecl.h" +#include "libiberty.h" + +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +/* On GNU libc systems the declaration is only visible with _GNU_SOURCE. */ +#if defined(HAVE_CANONICALIZE_FILE_NAME) \ + && defined(NEED_DECLARATION_CANONICALIZE_FILE_NAME) +extern char *canonicalize_file_name (const char *); +#endif + +#if defined(HAVE_REALPATH) +# if defined (PATH_MAX) +# define REALPATH_LIMIT PATH_MAX +# else +# if defined (MAXPATHLEN) +# define REALPATH_LIMIT MAXPATHLEN +# endif +# endif +#else + /* cygwin has realpath, so it won't get here. */ +# if defined (_WIN32) +# define WIN32_LEAN_AND_MEAN +# include /* for GetFullPathName */ +# endif +#endif + +char * +lrealpath (const char *filename) +{ + /* Method 1: The system has a compile time upper bound on a filename + path. Use that and realpath() to canonicalize the name. This is + the most common case. Note that, if there isn't a compile time + upper bound, you want to avoid realpath() at all costs. */ +#if defined(REALPATH_LIMIT) + { + char buf[REALPATH_LIMIT]; + const char *rp = realpath (filename, buf); + if (rp == NULL) + rp = filename; + return strdup (rp); + } +#endif /* REALPATH_LIMIT */ + + /* Method 2: The host system (i.e., GNU) has the function + canonicalize_file_name() which malloc's a chunk of memory and + returns that, use that. */ +#if defined(HAVE_CANONICALIZE_FILE_NAME) + { + char *rp = canonicalize_file_name (filename); + if (rp == NULL) + return strdup (filename); + else + return rp; + } +#endif + + /* Method 3: Now we're getting desperate! The system doesn't have a + compile time buffer size and no alternative function. Query the + OS, using pathconf(), for the buffer limit. Care is needed + though, some systems do not limit PATH_MAX (return -1 for + pathconf()) making it impossible to pass a correctly sized buffer + to realpath() (it could always overflow). On those systems, we + skip this. */ +#if defined (HAVE_REALPATH) && defined (HAVE_UNISTD_H) + { + /* Find out the max path size. */ + long path_max = pathconf ("/", _PC_PATH_MAX); + if (path_max > 0) + { + /* PATH_MAX is bounded. */ + char *buf, *rp, *ret; + buf = (char *) malloc (path_max); + if (buf == NULL) + return NULL; + rp = realpath (filename, buf); + ret = strdup (rp ? rp : filename); + free (buf); + return ret; + } + } +#endif + + /* The MS Windows method. If we don't have realpath, we assume we + don't have symlinks and just canonicalize to a Windows absolute + path. GetFullPath converts ../ and ./ in relative paths to + absolute paths, filling in current drive if one is not given + or using the current directory of a specified drive (eg, "E:foo"). + It also converts all forward slashes to back slashes. */ +#if defined (_WIN32) + { + char buf[MAX_PATH]; + char* basename; + DWORD len = GetFullPathName (filename, MAX_PATH, buf, &basename); + if (len == 0 || len > MAX_PATH - 1) + return strdup (filename); + else + { + /* The file system is case-preserving but case-insensitive, + Canonicalize to lowercase, using the codepage associated + with the process locale. */ + CharLowerBuff (buf, len); + return strdup (buf); + } + } +#endif + + /* This system is a lost cause, just duplicate the filename. */ + return strdup (filename); +} diff --git a/external/gpl3/gdb/dist/libiberty/maint-tool b/external/gpl3/gdb/dist/libiberty/maint-tool new file mode 100644 index 000000000000..36b92034f33c --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/maint-tool @@ -0,0 +1,296 @@ +#!/usr/bin/perl +# -*- perl -*- + +# Copyright (C) 2001, 2007, 2010 +# Free Software Foundation +# +# This file is part of the libiberty library. +# Libiberty is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# Libiberty is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with libiberty; see the file COPYING.LIB. If not, +# write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +# Boston, MA 02110-1301, USA. +# +# Originally written by DJ Delorie + + +# This is a trivial script which checks the lists of C and O files in +# the Makefile for consistency. + +$mode = shift; +$srcdir = "."; + +if ($mode eq "-s") { + $srcdir = shift; + $mode = shift; +} + +&missing() if $mode eq "missing"; +&undoc() if $mode eq "undoc"; +&deps() if $mode eq "deps"; + +exit 0; + +format STDOUT = +^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<~ +$out + ^<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<~~ +$out +. + +###################################################################### + +sub missing { + + opendir(S, $srcdir); + while ($f = readdir S) { + $have{$f} = 1; + } + closedir(S); + opendir(S, "."); + while ($f = readdir S) { + $have{$f} = 1; + } + closedir(S); + + for $a (@ARGV) { + $listed{$a} = 1; + $have{$a} = 0; + } + + for $f (sort keys %have) { + next unless $have{$f}; + if ($f =~ /\.c$/) { + print "S $f\n"; + } + } + for $f (sort keys %listed) { + if ($f =~ /(.*)\.c$/) { + $base = $1; + if (! $listed{"./$base.o"}) { + print "O $f\n"; + } + } + } +} + +###################################################################### + +sub undoc { + + opendir(S, $srcdir); + while ($file = readdir S) { + if ($file =~ /\.texi$/) { + open(T, "$srcdir/$file"); + while () { + if (/^\@deftype[^\(]* ([^\s\(]+) *\(/) { + $documented{$1} = 1; + } + } + close(T); + } + if ($file =~ /\.c$/) { + open(C, "$srcdir/$file"); + while () { + if (/\@undocumented (\S+)/) { + $documented{$1} = 1; + } + if (/^static /) { + if (! /[\(;]/) { + s/[\r\n]+$/ /; + $_ .= ; + } + while ($_ =~ /\([^\)]*$/) { + s/[\r\n]+$/ /; + $_ .= ; + } + } + s/ VPARAMS([ \(])/$1/; + s/PREFIX\(([^\)]*)\)/byte_$1/; + if (/^static [^\(]* ([^\s\(]+) *\(.*\)$/) { + $documented{$1} = 1; + } + } + } + } + closedir(D); + + # $out = join(' ', sort keys %documented); + # write; + # print "\n"; + + system "etags $srcdir/*.c $srcdir/../include/*.h"; + open(TAGS, "TAGS"); + while () { + s/[\r\n]+$//; + if (/^\014$/) { + $filename = ; + $filename =~ s/[\r\n]+$//; + $filename =~ s/,\d+$//; + $filename =~ s@.*[/\\]@@; + next; + } + if ($filename =~ /\.c$/ ) { + next unless /^[_a-zA-Z]/; + } else { + next unless /^\# *define/; + s/\# *define *//; + } + + s/ VPARAMS//; + s/ *\177.*//; + s/,$//; + s/DEFUN\(//; + s/\(//; + + next if /^static /; + next if /\s/; + next if /^_/; + next if $documented{$_}; + next if /_H_?$/; + + if ($seen_in{$_} ne $filename) { + $saw{$_} ++; + } + $seen_in{$_} = $filename; + } + + for $k (keys %saw) { + delete $saw{$k} if $saw{$k} > 1; + } + + for $k (sort keys %saw) { + $fromfile{$seen_in{$k}} .= " " if $fromfile{$seen_in{$k}}; + $fromfile{$seen_in{$k}} .= $k; + } + + for $f (sort keys %fromfile) { + $out = "$f: $fromfile{$f}"; + write; + } +} + +###################################################################### + +sub deps_for { + my($f) = @_; + my(%d); + open(F, $f); + %d = (); + while () { + if (/^#\s*include\s+["<](.*)[">]/) { + $d{$1} = 1; + } + } + close(F); + return keys %d; +} + +sub canonicalize { + my ($p) = @_; + 0 while $p =~ s@/\./@/@g; + 0 while $p =~ s@^\./@@g; + 0 while $p =~ s@/[^/]+/\.\./@/@g; + return $p; +} + +sub locals_first { + my ($a,$b) = @_; + return -1 if $a eq "config.h"; + return 1 if $b eq "config.h"; + return $a cmp $b; +} + +sub deps { + + $crule = "\tif [ x\"\$(PICFLAG)\" != x ]; then \\\n"; + $crule .= "\t \$(COMPILE.c) \$(PICFLAG) \$< -o pic/\$@; \\\n"; + $crule .= "\telse true; fi\n"; + $crule .= "\t\$(COMPILE.c) \$< \$(OUTPUT_OPTION)\n"; + $crule .= "\n"; + + $incdir = shift @ARGV; + + opendir(INC, $incdir); + while ($f = readdir INC) { + next unless $f =~ /\.h$/; + $mine{$f} = "\$(INCDIR)/$f"; + $deps{$f} = join(' ', &deps_for("$incdir/$f")); + } + $mine{'config.h'} = "config.h"; + + opendir(INC, $srcdir); + while ($f = readdir INC) { + next unless $f =~ /\.h$/; + $mine{$f} = "\$(srcdir)/$f"; + $deps{$f} = join(' ', &deps_for("$srcdir/$f")); + } + $mine{'config.h'} = "config.h"; + + open(IN, "$srcdir/Makefile.in"); + open(OUT, ">$srcdir/Makefile.tmp"); + while () { + last if /remainder of this file/; + print OUT; + } + print OUT "# The dependencies in the remainder of this file are automatically\n"; + print OUT "# generated by \"make maint-deps\". Manual edits will be lost.\n\n"; + + opendir(S, $srcdir); + for $f (sort readdir S) { + if ($f =~ /\.c$/) { + + %scanned = (); + @pending = &deps_for("$srcdir/$f"); + while (@pending) { + @tmp = @pending; + @pending = (); + for $p (@tmp) { + next unless $mine{$p}; + if (!$scanned{$p}) { + push(@pending, split(' ', $deps{$p})); + $scanned{$p} = 1; + } + } + } + @deps = sort { &locals_first($a,$b) } keys %scanned; + $obj = $f; + $obj =~ s/\.c$/.\$(objext)/; + $obj = "./$obj:"; + if ($#deps >= 0) { + print OUT "$obj \$(srcdir)/$f"; + $len = length("$obj $f"); + for $dt (@deps) { + $d = $mine{$dt}; + if ($len + length($d) > 70) { + printf OUT " \\\n\t$d"; + $len = 8 + length($d); + } else { + print OUT " $d"; + $len += length($d) + 1; + } + } + print OUT "\n"; + } else { + print OUT "$obj \$(srcdir)/$f\n"; + } + $c = $crule; + $c =~ s@\$\<@\$\(srcdir\)\/$f@g; + print OUT $c; + } + } + closedir(S); + close(IN); + close(OUT); + + rename("$srcdir/Makefile.tmp", "$srcdir/Makefile.in"); +} diff --git a/external/gpl3/gdb/dist/libiberty/make-relative-prefix.c b/external/gpl3/gdb/dist/libiberty/make-relative-prefix.c new file mode 100644 index 000000000000..4553a7109d82 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/make-relative-prefix.c @@ -0,0 +1,413 @@ +/* Relative (relocatable) prefix support. + Copyright (C) 1987, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, + 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc. + +This file is part of libiberty. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to the Free +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA +02110-1301, USA. */ + +/* + +@deftypefn Extension {const char*} make_relative_prefix (const char *@var{progname}, @ + const char *@var{bin_prefix}, const char *@var{prefix}) + +Given three paths @var{progname}, @var{bin_prefix}, @var{prefix}, +return the path that is in the same position relative to +@var{progname}'s directory as @var{prefix} is relative to +@var{bin_prefix}. That is, a string starting with the directory +portion of @var{progname}, followed by a relative pathname of the +difference between @var{bin_prefix} and @var{prefix}. + +If @var{progname} does not contain any directory separators, +@code{make_relative_prefix} will search @env{PATH} to find a program +named @var{progname}. Also, if @var{progname} is a symbolic link, +the symbolic link will be resolved. + +For example, if @var{bin_prefix} is @code{/alpha/beta/gamma/gcc/delta}, +@var{prefix} is @code{/alpha/beta/gamma/omega/}, and @var{progname} is +@code{/red/green/blue/gcc}, then this function will return +@code{/red/green/blue/../../omega/}. + +The return value is normally allocated via @code{malloc}. If no +relative prefix can be found, return @code{NULL}. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif + +#include + +#include "ansidecl.h" +#include "libiberty.h" + +#ifndef R_OK +#define R_OK 4 +#define W_OK 2 +#define X_OK 1 +#endif + +#ifndef DIR_SEPARATOR +# define DIR_SEPARATOR '/' +#endif + +#if defined (_WIN32) || defined (__MSDOS__) \ + || defined (__DJGPP__) || defined (__OS2__) +# define HAVE_DOS_BASED_FILE_SYSTEM +# define HAVE_HOST_EXECUTABLE_SUFFIX +# define HOST_EXECUTABLE_SUFFIX ".exe" +# ifndef DIR_SEPARATOR_2 +# define DIR_SEPARATOR_2 '\\' +# endif +# define PATH_SEPARATOR ';' +#else +# define PATH_SEPARATOR ':' +#endif + +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) +#else +# define IS_DIR_SEPARATOR(ch) \ + (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) +#endif + +#define DIR_UP ".." + +static char *save_string (const char *, int); +static char **split_directories (const char *, int *); +static void free_split_directories (char **); + +static char * +save_string (const char *s, int len) +{ + char *result = (char *) malloc (len + 1); + + memcpy (result, s, len); + result[len] = 0; + return result; +} + +/* Split a filename into component directories. */ + +static char ** +split_directories (const char *name, int *ptr_num_dirs) +{ + int num_dirs = 0; + char **dirs; + const char *p, *q; + int ch; + + /* Count the number of directories. Special case MSDOS disk names as part + of the initial directory. */ + p = name; +#ifdef HAVE_DOS_BASED_FILE_SYSTEM + if (name[1] == ':' && IS_DIR_SEPARATOR (name[2])) + { + p += 3; + num_dirs++; + } +#endif /* HAVE_DOS_BASED_FILE_SYSTEM */ + + while ((ch = *p++) != '\0') + { + if (IS_DIR_SEPARATOR (ch)) + { + num_dirs++; + while (IS_DIR_SEPARATOR (*p)) + p++; + } + } + + dirs = (char **) malloc (sizeof (char *) * (num_dirs + 2)); + if (dirs == NULL) + return NULL; + + /* Now copy the directory parts. */ + num_dirs = 0; + p = name; +#ifdef HAVE_DOS_BASED_FILE_SYSTEM + if (name[1] == ':' && IS_DIR_SEPARATOR (name[2])) + { + dirs[num_dirs++] = save_string (p, 3); + if (dirs[num_dirs - 1] == NULL) + { + free (dirs); + return NULL; + } + p += 3; + } +#endif /* HAVE_DOS_BASED_FILE_SYSTEM */ + + q = p; + while ((ch = *p++) != '\0') + { + if (IS_DIR_SEPARATOR (ch)) + { + while (IS_DIR_SEPARATOR (*p)) + p++; + + dirs[num_dirs++] = save_string (q, p - q); + if (dirs[num_dirs - 1] == NULL) + { + dirs[num_dirs] = NULL; + free_split_directories (dirs); + return NULL; + } + q = p; + } + } + + if (p - 1 - q > 0) + dirs[num_dirs++] = save_string (q, p - 1 - q); + dirs[num_dirs] = NULL; + + if (dirs[num_dirs - 1] == NULL) + { + free_split_directories (dirs); + return NULL; + } + + if (ptr_num_dirs) + *ptr_num_dirs = num_dirs; + return dirs; +} + +/* Release storage held by split directories. */ + +static void +free_split_directories (char **dirs) +{ + int i = 0; + + if (dirs != NULL) + { + while (dirs[i] != NULL) + free (dirs[i++]); + + free ((char *) dirs); + } +} + +/* Given three strings PROGNAME, BIN_PREFIX, PREFIX, return a string that gets + to PREFIX starting with the directory portion of PROGNAME and a relative + pathname of the difference between BIN_PREFIX and PREFIX. + + For example, if BIN_PREFIX is /alpha/beta/gamma/gcc/delta, PREFIX is + /alpha/beta/gamma/omega/, and PROGNAME is /red/green/blue/gcc, then this + function will return /red/green/blue/../../omega/. + + If no relative prefix can be found, return NULL. */ + +static char * +make_relative_prefix_1 (const char *progname, const char *bin_prefix, + const char *prefix, const int resolve_links) +{ + char **prog_dirs = NULL, **bin_dirs = NULL, **prefix_dirs = NULL; + int prog_num, bin_num, prefix_num; + int i, n, common; + int needed_len; + char *ret = NULL, *ptr, *full_progname; + + if (progname == NULL || bin_prefix == NULL || prefix == NULL) + return NULL; + + /* If there is no full pathname, try to find the program by checking in each + of the directories specified in the PATH environment variable. */ + if (lbasename (progname) == progname) + { + char *temp; + + temp = getenv ("PATH"); + if (temp) + { + char *startp, *endp, *nstore; + size_t prefixlen = strlen (temp) + 1; + if (prefixlen < 2) + prefixlen = 2; + + nstore = (char *) alloca (prefixlen + strlen (progname) + 1); + + startp = endp = temp; + while (1) + { + if (*endp == PATH_SEPARATOR || *endp == 0) + { + if (endp == startp) + { + nstore[0] = '.'; + nstore[1] = DIR_SEPARATOR; + nstore[2] = '\0'; + } + else + { + strncpy (nstore, startp, endp - startp); + if (! IS_DIR_SEPARATOR (endp[-1])) + { + nstore[endp - startp] = DIR_SEPARATOR; + nstore[endp - startp + 1] = 0; + } + else + nstore[endp - startp] = 0; + } + strcat (nstore, progname); + if (! access (nstore, X_OK) +#ifdef HAVE_HOST_EXECUTABLE_SUFFIX + || ! access (strcat (nstore, HOST_EXECUTABLE_SUFFIX), X_OK) +#endif + ) + { + progname = nstore; + break; + } + + if (*endp == 0) + break; + endp = startp = endp + 1; + } + else + endp++; + } + } + } + + if (resolve_links) + full_progname = lrealpath (progname); + else + full_progname = strdup (progname); + if (full_progname == NULL) + return NULL; + + prog_dirs = split_directories (full_progname, &prog_num); + free (full_progname); + if (prog_dirs == NULL) + return NULL; + + bin_dirs = split_directories (bin_prefix, &bin_num); + if (bin_dirs == NULL) + goto bailout; + + /* Remove the program name from comparison of directory names. */ + prog_num--; + + /* If we are still installed in the standard location, we don't need to + specify relative directories. Also, if argv[0] still doesn't contain + any directory specifiers after the search above, then there is not much + we can do. */ + if (prog_num == bin_num) + { + for (i = 0; i < bin_num; i++) + { + if (strcmp (prog_dirs[i], bin_dirs[i]) != 0) + break; + } + + if (prog_num <= 0 || i == bin_num) + goto bailout; + } + + prefix_dirs = split_directories (prefix, &prefix_num); + if (prefix_dirs == NULL) + goto bailout; + + /* Find how many directories are in common between bin_prefix & prefix. */ + n = (prefix_num < bin_num) ? prefix_num : bin_num; + for (common = 0; common < n; common++) + { + if (strcmp (bin_dirs[common], prefix_dirs[common]) != 0) + break; + } + + /* If there are no common directories, there can be no relative prefix. */ + if (common == 0) + goto bailout; + + /* Two passes: first figure out the size of the result string, and + then construct it. */ + needed_len = 0; + for (i = 0; i < prog_num; i++) + needed_len += strlen (prog_dirs[i]); + needed_len += sizeof (DIR_UP) * (bin_num - common); + for (i = common; i < prefix_num; i++) + needed_len += strlen (prefix_dirs[i]); + needed_len += 1; /* Trailing NUL. */ + + ret = (char *) malloc (needed_len); + if (ret == NULL) + goto bailout; + + /* Build up the pathnames in argv[0]. */ + *ret = '\0'; + for (i = 0; i < prog_num; i++) + strcat (ret, prog_dirs[i]); + + /* Now build up the ..'s. */ + ptr = ret + strlen(ret); + for (i = common; i < bin_num; i++) + { + strcpy (ptr, DIR_UP); + ptr += sizeof (DIR_UP) - 1; + *(ptr++) = DIR_SEPARATOR; + } + *ptr = '\0'; + + /* Put in directories to move over to prefix. */ + for (i = common; i < prefix_num; i++) + strcat (ret, prefix_dirs[i]); + + bailout: + free_split_directories (prog_dirs); + free_split_directories (bin_dirs); + free_split_directories (prefix_dirs); + + return ret; +} + + +/* Do the full job, including symlink resolution. + This path will find files installed in the same place as the + program even when a soft link has been made to the program + from somwhere else. */ + +char * +make_relative_prefix (const char *progname, const char *bin_prefix, + const char *prefix) +{ + return make_relative_prefix_1 (progname, bin_prefix, prefix, 1); +} + +/* Make the relative pathname without attempting to resolve any links. + '..' etc may also be left in the pathname. + This will find the files the user meant the program to find if the + installation is patched together with soft links. */ + +char * +make_relative_prefix_ignore_links (const char *progname, + const char *bin_prefix, + const char *prefix) +{ + return make_relative_prefix_1 (progname, bin_prefix, prefix, 0); +} + diff --git a/external/gpl3/gdb/dist/libiberty/make-temp-file.c b/external/gpl3/gdb/dist/libiberty/make-temp-file.c new file mode 100644 index 000000000000..7b74f8179b10 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/make-temp-file.c @@ -0,0 +1,217 @@ +/* Utility to pick a temporary filename prefix. + Copyright (C) 1996, 1997, 1998, 2001, 2009, 2010 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include /* May get P_tmpdir. */ +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_SYS_FILE_H +#include /* May get R_OK, etc. on some systems. */ +#endif +#if defined(_WIN32) && !defined(__CYGWIN__) +#include +#endif + +#ifndef R_OK +#define R_OK 4 +#define W_OK 2 +#define X_OK 1 +#endif + +#include "libiberty.h" +extern int mkstemps (char *, int); + +/* '/' works just fine on MS-DOS based systems. */ +#ifndef DIR_SEPARATOR +#define DIR_SEPARATOR '/' +#endif + +/* Name of temporary file. + mktemp requires 6 trailing X's. */ +#define TEMP_FILE "ccXXXXXX" +#define TEMP_FILE_LEN (sizeof(TEMP_FILE) - 1) + +#if !defined(_WIN32) || defined(__CYGWIN__) + +/* Subroutine of choose_tmpdir. + If BASE is non-NULL, return it. + Otherwise it checks if DIR is a usable directory. + If success, DIR is returned. + Otherwise NULL is returned. */ + +static inline const char *try_dir (const char *, const char *); + +static inline const char * +try_dir (const char *dir, const char *base) +{ + if (base != 0) + return base; + if (dir != 0 + && access (dir, R_OK | W_OK | X_OK) == 0) + return dir; + return 0; +} + +static const char tmp[] = { DIR_SEPARATOR, 't', 'm', 'p', 0 }; +static const char usrtmp[] = +{ DIR_SEPARATOR, 'u', 's', 'r', DIR_SEPARATOR, 't', 'm', 'p', 0 }; +static const char vartmp[] = +{ DIR_SEPARATOR, 'v', 'a', 'r', DIR_SEPARATOR, 't', 'm', 'p', 0 }; + +#endif + +static char *memoized_tmpdir; + +/* + +@deftypefn Replacement char* choose_tmpdir () + +Returns a pointer to a directory path suitable for creating temporary +files in. + +@end deftypefn + +*/ + +char * +choose_tmpdir (void) +{ + if (!memoized_tmpdir) + { +#if !defined(_WIN32) || defined(__CYGWIN__) + const char *base = 0; + char *tmpdir; + unsigned int len; + +#ifdef VMS + /* Try VMS standard temp logical. */ + base = try_dir ("/sys$scratch", base); +#else + base = try_dir (getenv ("TMPDIR"), base); + base = try_dir (getenv ("TMP"), base); + base = try_dir (getenv ("TEMP"), base); +#endif + +#ifdef P_tmpdir + /* We really want a directory name here as if concatenated with say \dir + we do not end up with a double \\ which defines an UNC path. */ + if (strcmp (P_tmpdir, "\\") == 0) + base = try_dir ("\\.", base); + else + base = try_dir (P_tmpdir, base); +#endif + + /* Try /var/tmp, /usr/tmp, then /tmp. */ + base = try_dir (vartmp, base); + base = try_dir (usrtmp, base); + base = try_dir (tmp, base); + + /* If all else fails, use the current directory! */ + if (base == 0) + base = "."; + /* Append DIR_SEPARATOR to the directory we've chosen + and return it. */ + len = strlen (base); + tmpdir = XNEWVEC (char, len + 2); + strcpy (tmpdir, base); + tmpdir[len] = DIR_SEPARATOR; + tmpdir[len+1] = '\0'; + memoized_tmpdir = tmpdir; +#else /* defined(_WIN32) && !defined(__CYGWIN__) */ + DWORD len; + + /* Figure out how much space we need. */ + len = GetTempPath(0, NULL); + if (len) + { + memoized_tmpdir = XNEWVEC (char, len); + if (!GetTempPath(len, memoized_tmpdir)) + { + XDELETEVEC (memoized_tmpdir); + memoized_tmpdir = NULL; + } + } + if (!memoized_tmpdir) + /* If all else fails, use the current directory. */ + memoized_tmpdir = xstrdup (".\\"); +#endif /* defined(_WIN32) && !defined(__CYGWIN__) */ + } + + return memoized_tmpdir; +} + +/* + +@deftypefn Replacement char* make_temp_file (const char *@var{suffix}) + +Return a temporary file name (as a string) or @code{NULL} if unable to +create one. @var{suffix} is a suffix to append to the file name. The +string is @code{malloc}ed, and the temporary file has been created. + +@end deftypefn + +*/ + +char * +make_temp_file (const char *suffix) +{ + const char *base = choose_tmpdir (); + char *temp_filename; + int base_len, suffix_len; + int fd; + + if (suffix == 0) + suffix = ""; + + base_len = strlen (base); + suffix_len = strlen (suffix); + + temp_filename = XNEWVEC (char, base_len + + TEMP_FILE_LEN + + suffix_len + 1); + strcpy (temp_filename, base); + strcpy (temp_filename + base_len, TEMP_FILE); + strcpy (temp_filename + base_len + TEMP_FILE_LEN, suffix); + + fd = mkstemps (temp_filename, suffix_len); + /* Mkstemps failed. It may be EPERM, ENOSPC etc. */ + if (fd == -1) + { + fprintf (stderr, "Cannot create temporary file in %s: %s\n", + base, strerror (errno)); + abort (); + } + /* We abort on failed close out of sheer paranoia. */ + if (close (fd)) + abort (); + return temp_filename; +} diff --git a/external/gpl3/gdb/dist/libiberty/makefile.vms b/external/gpl3/gdb/dist/libiberty/makefile.vms new file mode 100644 index 000000000000..606adac09643 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/makefile.vms @@ -0,0 +1,35 @@ +# +# Makefile for libiberty under openVMS +# +# For use with gnu-make for vms +# +# Created by Klaus K"ampf, kkaempf@progis.de +# +# + +OBJS=getopt.obj,obstack.obj,xexit.obj,xmalloc.obj,hex.obj,\ + getopt1.obj,cplus-dem.obj,cp-demangle.obj,cp-demint.obj,\ + asprintf.obj vasprintf.obj,mkstemps.obj,filename_cmp.obj,\ + concat.obj,getruntime.obj,getpagesize.obj,getpwd.obj,xstrerror.obj,\ + xmemdup.obj,xstrdup.obj,xatexit.obj,choose-temp.obj,fnmatch.obj,\ + objalloc.obj,safe-ctype.obj,hashtab.obj,lbasename.obj,argv.obj,\ + lrealpath.obj,make-temp-file.obj,stpcpy.obj,unlink-if-ordinary.obj + +ifeq ($(CC),gcc) +CFLAGS=/include=([],[-.include]) +else +# assume dec c +OPT=/noopt/debug/warnings=disable=(missingreturn) +CFLAGS=$(OPT)/include=([],[-.include])/name=(as_is,shortened)\ + /define=(HAVE_CONFIG_H=1)\ + /prefix=(all,except=("getopt","optarg","optopt","optind","opterr")) +endif + +libiberty.olb: $(OBJS) + purge + lib/create libiberty *.obj + +clean: + $$ purge + $(RM) *.obj; + $(RM) libiberty.olb; diff --git a/external/gpl3/gdb/dist/libiberty/md5.c b/external/gpl3/gdb/dist/libiberty/md5.c new file mode 100644 index 000000000000..9de9d88c22a5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/md5.c @@ -0,0 +1,431 @@ +/* md5.c - Functions to compute MD5 message digest of files or memory blocks + according to the definition of MD5 in RFC 1321 from April 1992. + Copyright (C) 1995, 1996 Free Software Foundation, Inc. + + NOTE: This source is derived from an old version taken from the GNU C + Library (glibc). + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Written by Ulrich Drepper , 1995. */ + +#ifdef HAVE_CONFIG_H +# include +#endif + +#include + +#if STDC_HEADERS || defined _LIBC +# include +# include +#else +# ifndef HAVE_MEMCPY +# define memcpy(d, s, n) bcopy ((s), (d), (n)) +# endif +#endif + +#include "ansidecl.h" +#include "md5.h" + +#ifdef _LIBC +# include +# if __BYTE_ORDER == __BIG_ENDIAN +# define WORDS_BIGENDIAN 1 +# endif +#endif + +#ifdef WORDS_BIGENDIAN +# define SWAP(n) \ + (((n) << 24) | (((n) & 0xff00) << 8) | (((n) >> 8) & 0xff00) | ((n) >> 24)) +#else +# define SWAP(n) (n) +#endif + + +/* This array contains the bytes used to pad the buffer to the next + 64-byte boundary. (RFC 1321, 3.1: Step 1) */ +static const unsigned char fillbuf[64] = { 0x80, 0 /* , 0, 0, ... */ }; + + +/* Initialize structure containing state of computation. + (RFC 1321, 3.3: Step 3) */ +void +md5_init_ctx (struct md5_ctx *ctx) +{ + ctx->A = (md5_uint32) 0x67452301; + ctx->B = (md5_uint32) 0xefcdab89; + ctx->C = (md5_uint32) 0x98badcfe; + ctx->D = (md5_uint32) 0x10325476; + + ctx->total[0] = ctx->total[1] = 0; + ctx->buflen = 0; +} + +/* Put result from CTX in first 16 bytes following RESBUF. The result + must be in little endian byte order. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +void * +md5_read_ctx (const struct md5_ctx *ctx, void *resbuf) +{ + ((md5_uint32 *) resbuf)[0] = SWAP (ctx->A); + ((md5_uint32 *) resbuf)[1] = SWAP (ctx->B); + ((md5_uint32 *) resbuf)[2] = SWAP (ctx->C); + ((md5_uint32 *) resbuf)[3] = SWAP (ctx->D); + + return resbuf; +} + +/* Process the remaining bytes in the internal buffer and the usual + prolog according to the standard and write the result to RESBUF. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +void * +md5_finish_ctx (struct md5_ctx *ctx, void *resbuf) +{ + /* Take yet unprocessed bytes into account. */ + md5_uint32 bytes = ctx->buflen; + size_t pad; + + /* Now count remaining bytes. */ + ctx->total[0] += bytes; + if (ctx->total[0] < bytes) + ++ctx->total[1]; + + pad = bytes >= 56 ? 64 + 56 - bytes : 56 - bytes; + memcpy (&ctx->buffer[bytes], fillbuf, pad); + + /* Put the 64-bit file length in *bits* at the end of the buffer. */ + *(md5_uint32 *) &ctx->buffer[bytes + pad] = SWAP (ctx->total[0] << 3); + *(md5_uint32 *) &ctx->buffer[bytes + pad + 4] = SWAP ((ctx->total[1] << 3) | + (ctx->total[0] >> 29)); + + /* Process last bytes. */ + md5_process_block (ctx->buffer, bytes + pad + 8, ctx); + + return md5_read_ctx (ctx, resbuf); +} + +/* Compute MD5 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 16 bytes + beginning at RESBLOCK. */ +int +md5_stream (FILE *stream, void *resblock) +{ + /* Important: BLOCKSIZE must be a multiple of 64. */ +#define BLOCKSIZE 4096 + struct md5_ctx ctx; + char buffer[BLOCKSIZE + 72]; + size_t sum; + + /* Initialize the computation context. */ + md5_init_ctx (&ctx); + + /* Iterate over full file contents. */ + while (1) + { + /* We read the file in blocks of BLOCKSIZE bytes. One call of the + computation function processes the whole buffer so that with the + next round of the loop another block can be read. */ + size_t n; + sum = 0; + + /* Read block. Take care for partial reads. */ + do + { + n = fread (buffer + sum, 1, BLOCKSIZE - sum, stream); + + sum += n; + } + while (sum < BLOCKSIZE && n != 0); + if (n == 0 && ferror (stream)) + return 1; + + /* If end of file is reached, end the loop. */ + if (n == 0) + break; + + /* Process buffer with BLOCKSIZE bytes. Note that + BLOCKSIZE % 64 == 0 + */ + md5_process_block (buffer, BLOCKSIZE, &ctx); + } + + /* Add the last bytes if necessary. */ + if (sum > 0) + md5_process_bytes (buffer, sum, &ctx); + + /* Construct result in desired memory. */ + md5_finish_ctx (&ctx, resblock); + return 0; +} + +/* Compute MD5 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +void * +md5_buffer (const char *buffer, size_t len, void *resblock) +{ + struct md5_ctx ctx; + + /* Initialize the computation context. */ + md5_init_ctx (&ctx); + + /* Process whole buffer but last len % 64 bytes. */ + md5_process_bytes (buffer, len, &ctx); + + /* Put result in desired memory area. */ + return md5_finish_ctx (&ctx, resblock); +} + + +void +md5_process_bytes (const void *buffer, size_t len, struct md5_ctx *ctx) +{ + /* When we already have some bits in our internal buffer concatenate + both inputs first. */ + if (ctx->buflen != 0) + { + size_t left_over = ctx->buflen; + size_t add = 128 - left_over > len ? len : 128 - left_over; + + memcpy (&ctx->buffer[left_over], buffer, add); + ctx->buflen += add; + + if (left_over + add > 64) + { + md5_process_block (ctx->buffer, (left_over + add) & ~63, ctx); + /* The regions in the following copy operation cannot overlap. */ + memcpy (ctx->buffer, &ctx->buffer[(left_over + add) & ~63], + (left_over + add) & 63); + ctx->buflen = (left_over + add) & 63; + } + + buffer = (const void *) ((const char *) buffer + add); + len -= add; + } + + /* Process available complete blocks. */ + if (len > 64) + { +#if !_STRING_ARCH_unaligned +/* To check alignment gcc has an appropriate operator. Other + compilers don't. */ +# if __GNUC__ >= 2 +# define UNALIGNED_P(p) (((md5_uintptr) p) % __alignof__ (md5_uint32) != 0) +# else +# define UNALIGNED_P(p) (((md5_uintptr) p) % sizeof (md5_uint32) != 0) +# endif + if (UNALIGNED_P (buffer)) + while (len > 64) + { + memcpy (ctx->buffer, buffer, 64); + md5_process_block (ctx->buffer, 64, ctx); + buffer = (const char *) buffer + 64; + len -= 64; + } + else +#endif + md5_process_block (buffer, len & ~63, ctx); + buffer = (const void *) ((const char *) buffer + (len & ~63)); + len &= 63; + } + + /* Move remaining bytes in internal buffer. */ + if (len > 0) + { + memcpy (ctx->buffer, buffer, len); + ctx->buflen = len; + } +} + + +/* These are the four functions used in the four steps of the MD5 algorithm + and defined in the RFC 1321. The first function is a little bit optimized + (as found in Colin Plumbs public domain implementation). */ +/* #define FF(b, c, d) ((b & c) | (~b & d)) */ +#define FF(b, c, d) (d ^ (b & (c ^ d))) +#define FG(b, c, d) FF (d, b, c) +#define FH(b, c, d) (b ^ c ^ d) +#define FI(b, c, d) (c ^ (b | ~d)) + +/* Process LEN bytes of BUFFER, accumulating context into CTX. + It is assumed that LEN % 64 == 0. */ + +void +md5_process_block (const void *buffer, size_t len, struct md5_ctx *ctx) +{ + md5_uint32 correct_words[16]; + const md5_uint32 *words = (const md5_uint32 *) buffer; + size_t nwords = len / sizeof (md5_uint32); + const md5_uint32 *endp = words + nwords; + md5_uint32 A = ctx->A; + md5_uint32 B = ctx->B; + md5_uint32 C = ctx->C; + md5_uint32 D = ctx->D; + + /* First increment the byte count. RFC 1321 specifies the possible + length of the file up to 2^64 bits. Here we only compute the + number of bytes. Do a double word increment. */ + ctx->total[0] += len; + if (ctx->total[0] < len) + ++ctx->total[1]; + + /* Process all bytes in the buffer with 64 bytes in each round of + the loop. */ + while (words < endp) + { + md5_uint32 *cwp = correct_words; + md5_uint32 A_save = A; + md5_uint32 B_save = B; + md5_uint32 C_save = C; + md5_uint32 D_save = D; + + /* First round: using the given function, the context and a constant + the next context is computed. Because the algorithms processing + unit is a 32-bit word and it is determined to work on words in + little endian byte order we perhaps have to change the byte order + before the computation. To reduce the work for the next steps + we store the swapped words in the array CORRECT_WORDS. */ + +#define OP(a, b, c, d, s, T) \ + do \ + { \ + a += FF (b, c, d) + (*cwp++ = SWAP (*words)) + T; \ + ++words; \ + CYCLIC (a, s); \ + a += b; \ + } \ + while (0) + + /* It is unfortunate that C does not provide an operator for + cyclic rotation. Hope the C compiler is smart enough. */ +#define CYCLIC(w, s) (w = (w << s) | (w >> (32 - s))) + + /* Before we start, one word to the strange constants. + They are defined in RFC 1321 as + + T[i] = (int) (4294967296.0 * fabs (sin (i))), i=1..64 + */ + + /* Round 1. */ + OP (A, B, C, D, 7, (md5_uint32) 0xd76aa478); + OP (D, A, B, C, 12, (md5_uint32) 0xe8c7b756); + OP (C, D, A, B, 17, (md5_uint32) 0x242070db); + OP (B, C, D, A, 22, (md5_uint32) 0xc1bdceee); + OP (A, B, C, D, 7, (md5_uint32) 0xf57c0faf); + OP (D, A, B, C, 12, (md5_uint32) 0x4787c62a); + OP (C, D, A, B, 17, (md5_uint32) 0xa8304613); + OP (B, C, D, A, 22, (md5_uint32) 0xfd469501); + OP (A, B, C, D, 7, (md5_uint32) 0x698098d8); + OP (D, A, B, C, 12, (md5_uint32) 0x8b44f7af); + OP (C, D, A, B, 17, (md5_uint32) 0xffff5bb1); + OP (B, C, D, A, 22, (md5_uint32) 0x895cd7be); + OP (A, B, C, D, 7, (md5_uint32) 0x6b901122); + OP (D, A, B, C, 12, (md5_uint32) 0xfd987193); + OP (C, D, A, B, 17, (md5_uint32) 0xa679438e); + OP (B, C, D, A, 22, (md5_uint32) 0x49b40821); + + /* For the second to fourth round we have the possibly swapped words + in CORRECT_WORDS. Redefine the macro to take an additional first + argument specifying the function to use. */ +#undef OP +#define OP(a, b, c, d, k, s, T) \ + do \ + { \ + a += FX (b, c, d) + correct_words[k] + T; \ + CYCLIC (a, s); \ + a += b; \ + } \ + while (0) + +#define FX(b, c, d) FG (b, c, d) + + /* Round 2. */ + OP (A, B, C, D, 1, 5, (md5_uint32) 0xf61e2562); + OP (D, A, B, C, 6, 9, (md5_uint32) 0xc040b340); + OP (C, D, A, B, 11, 14, (md5_uint32) 0x265e5a51); + OP (B, C, D, A, 0, 20, (md5_uint32) 0xe9b6c7aa); + OP (A, B, C, D, 5, 5, (md5_uint32) 0xd62f105d); + OP (D, A, B, C, 10, 9, (md5_uint32) 0x02441453); + OP (C, D, A, B, 15, 14, (md5_uint32) 0xd8a1e681); + OP (B, C, D, A, 4, 20, (md5_uint32) 0xe7d3fbc8); + OP (A, B, C, D, 9, 5, (md5_uint32) 0x21e1cde6); + OP (D, A, B, C, 14, 9, (md5_uint32) 0xc33707d6); + OP (C, D, A, B, 3, 14, (md5_uint32) 0xf4d50d87); + OP (B, C, D, A, 8, 20, (md5_uint32) 0x455a14ed); + OP (A, B, C, D, 13, 5, (md5_uint32) 0xa9e3e905); + OP (D, A, B, C, 2, 9, (md5_uint32) 0xfcefa3f8); + OP (C, D, A, B, 7, 14, (md5_uint32) 0x676f02d9); + OP (B, C, D, A, 12, 20, (md5_uint32) 0x8d2a4c8a); + +#undef FX +#define FX(b, c, d) FH (b, c, d) + + /* Round 3. */ + OP (A, B, C, D, 5, 4, (md5_uint32) 0xfffa3942); + OP (D, A, B, C, 8, 11, (md5_uint32) 0x8771f681); + OP (C, D, A, B, 11, 16, (md5_uint32) 0x6d9d6122); + OP (B, C, D, A, 14, 23, (md5_uint32) 0xfde5380c); + OP (A, B, C, D, 1, 4, (md5_uint32) 0xa4beea44); + OP (D, A, B, C, 4, 11, (md5_uint32) 0x4bdecfa9); + OP (C, D, A, B, 7, 16, (md5_uint32) 0xf6bb4b60); + OP (B, C, D, A, 10, 23, (md5_uint32) 0xbebfbc70); + OP (A, B, C, D, 13, 4, (md5_uint32) 0x289b7ec6); + OP (D, A, B, C, 0, 11, (md5_uint32) 0xeaa127fa); + OP (C, D, A, B, 3, 16, (md5_uint32) 0xd4ef3085); + OP (B, C, D, A, 6, 23, (md5_uint32) 0x04881d05); + OP (A, B, C, D, 9, 4, (md5_uint32) 0xd9d4d039); + OP (D, A, B, C, 12, 11, (md5_uint32) 0xe6db99e5); + OP (C, D, A, B, 15, 16, (md5_uint32) 0x1fa27cf8); + OP (B, C, D, A, 2, 23, (md5_uint32) 0xc4ac5665); + +#undef FX +#define FX(b, c, d) FI (b, c, d) + + /* Round 4. */ + OP (A, B, C, D, 0, 6, (md5_uint32) 0xf4292244); + OP (D, A, B, C, 7, 10, (md5_uint32) 0x432aff97); + OP (C, D, A, B, 14, 15, (md5_uint32) 0xab9423a7); + OP (B, C, D, A, 5, 21, (md5_uint32) 0xfc93a039); + OP (A, B, C, D, 12, 6, (md5_uint32) 0x655b59c3); + OP (D, A, B, C, 3, 10, (md5_uint32) 0x8f0ccc92); + OP (C, D, A, B, 10, 15, (md5_uint32) 0xffeff47d); + OP (B, C, D, A, 1, 21, (md5_uint32) 0x85845dd1); + OP (A, B, C, D, 8, 6, (md5_uint32) 0x6fa87e4f); + OP (D, A, B, C, 15, 10, (md5_uint32) 0xfe2ce6e0); + OP (C, D, A, B, 6, 15, (md5_uint32) 0xa3014314); + OP (B, C, D, A, 13, 21, (md5_uint32) 0x4e0811a1); + OP (A, B, C, D, 4, 6, (md5_uint32) 0xf7537e82); + OP (D, A, B, C, 11, 10, (md5_uint32) 0xbd3af235); + OP (C, D, A, B, 2, 15, (md5_uint32) 0x2ad7d2bb); + OP (B, C, D, A, 9, 21, (md5_uint32) 0xeb86d391); + + /* Add the starting values of the context. */ + A += A_save; + B += B_save; + C += C_save; + D += D_save; + } + + /* Put checksum in context given as argument. */ + ctx->A = A; + ctx->B = B; + ctx->C = C; + ctx->D = D; +} diff --git a/external/gpl3/gdb/dist/libiberty/memchr.c b/external/gpl3/gdb/dist/libiberty/memchr.c new file mode 100644 index 000000000000..7448ab9e71c3 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memchr.c @@ -0,0 +1,33 @@ +/* + +@deftypefn Supplemental void* memchr (const void *@var{s}, int @var{c}, @ + size_t @var{n}) + +This function searches memory starting at @code{*@var{s}} for the +character @var{c}. The search only ends with the first occurrence of +@var{c}, or after @var{length} characters; in particular, a null +character does not terminate the search. If the character @var{c} is +found within @var{length} characters of @code{*@var{s}}, a pointer +to the character is returned. If @var{c} is not found, then @code{NULL} is +returned. + +@end deftypefn + +*/ + +#include +#include + +PTR +memchr (register const PTR src_void, int c, size_t length) +{ + const unsigned char *src = (const unsigned char *)src_void; + + while (length-- > 0) + { + if (*src == c) + return (PTR)src; + src++; + } + return NULL; +} diff --git a/external/gpl3/gdb/dist/libiberty/memcmp.c b/external/gpl3/gdb/dist/libiberty/memcmp.c new file mode 100644 index 000000000000..37db60f38267 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memcmp.c @@ -0,0 +1,35 @@ +/* memcmp -- compare two memory regions. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental int memcmp (const void *@var{x}, const void *@var{y}, @ + size_t @var{count}) + +Compares the first @var{count} bytes of two areas of memory. Returns +zero if they are the same, a value less than zero if @var{x} is +lexically less than @var{y}, or a value greater than zero if @var{x} +is lexically greater than @var{y}. Note that lexical order is determined +as if comparing unsigned char arrays. + +@end deftypefn + +*/ + +#include +#include + +int +memcmp (const PTR str1, const PTR str2, size_t count) +{ + register const unsigned char *s1 = (const unsigned char*)str1; + register const unsigned char *s2 = (const unsigned char*)str2; + + while (count-- > 0) + { + if (*s1++ != *s2++) + return s1[-1] < s2[-1] ? -1 : 1; + } + return 0; +} + diff --git a/external/gpl3/gdb/dist/libiberty/memcpy.c b/external/gpl3/gdb/dist/libiberty/memcpy.c new file mode 100644 index 000000000000..7f67d0bd1f26 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memcpy.c @@ -0,0 +1,26 @@ +/* memcpy (the standard C function) + This function is in the public domain. */ + +/* + +@deftypefn Supplemental void* memcpy (void *@var{out}, const void *@var{in}, @ + size_t @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. Returns a pointer to @var{out}. + +@end deftypefn + +*/ + +#include +#include + +void bcopy (const void*, void*, size_t); + +PTR +memcpy (PTR out, const PTR in, size_t length) +{ + bcopy(in, out, length); + return out; +} diff --git a/external/gpl3/gdb/dist/libiberty/memmem.c b/external/gpl3/gdb/dist/libiberty/memmem.c new file mode 100644 index 000000000000..147253f5bad9 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memmem.c @@ -0,0 +1,71 @@ +/* Copyright (C) 1991,92,93,94,96,97,98,2000,2004,2007,2011 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Supplemental void* memmem (const void *@var{haystack}, @ + size_t @var{haystack_len} const void *@var{needle}, size_t @var{needle_len}) + +Returns a pointer to the first occurrence of @var{needle} (length +@var{needle_len}) in @var{haystack} (length @var{haystack_len}). +Returns @code{NULL} if not found. + +@end deftypefn + +*/ + +#ifndef _LIBC +# include +#endif + +#include +#include + +#ifndef _LIBC +# define __builtin_expect(expr, val) (expr) +#endif + +#undef memmem + +/* Return the first occurrence of NEEDLE in HAYSTACK. */ +void * +memmem (const void *haystack, size_t haystack_len, const void *needle, + size_t needle_len) +{ + const char *begin; + const char *const last_possible + = (const char *) haystack + haystack_len - needle_len; + + if (needle_len == 0) + /* The first occurrence of the empty string is deemed to occur at + the beginning of the string. */ + return (void *) haystack; + + /* Sanity check, otherwise the loop might search through the whole + memory. */ + if (__builtin_expect (haystack_len < needle_len, 0)) + return NULL; + + for (begin = (const char *) haystack; begin <= last_possible; ++begin) + if (begin[0] == ((const char *) needle)[0] && + !memcmp ((const void *) &begin[1], + (const void *) ((const char *) needle + 1), + needle_len - 1)) + return (void *) begin; + + return NULL; +} diff --git a/external/gpl3/gdb/dist/libiberty/memmove.c b/external/gpl3/gdb/dist/libiberty/memmove.c new file mode 100644 index 000000000000..ebda7cbb41ca --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memmove.c @@ -0,0 +1,26 @@ +/* Wrapper to implement ANSI C's memmove using BSD's bcopy. */ +/* This function is in the public domain. --Per Bothner. */ + +/* + +@deftypefn Supplemental void* memmove (void *@var{from}, const void *@var{to}, @ + size_t @var{count}) + +Copies @var{count} bytes from memory area @var{from} to memory area +@var{to}, returning a pointer to @var{to}. + +@end deftypefn + +*/ + +#include +#include + +void bcopy (const void*, void*, size_t); + +PTR +memmove (PTR s1, const PTR s2, size_t n) +{ + bcopy (s2, s1, n); + return s1; +} diff --git a/external/gpl3/gdb/dist/libiberty/mempcpy.c b/external/gpl3/gdb/dist/libiberty/mempcpy.c new file mode 100644 index 000000000000..f85a07f2910f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/mempcpy.c @@ -0,0 +1,42 @@ +/* Implement the mempcpy function. + Copyright (C) 2003, 2004, 2005, 2011 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Supplemental void* mempcpy (void *@var{out}, const void *@var{in}, @ + size_t @var{length}) + +Copies @var{length} bytes from memory region @var{in} to region +@var{out}. Returns a pointer to @var{out} + @var{length}. + +@end deftypefn + +*/ + +#include +#include + +extern PTR memcpy (PTR, const PTR, size_t); + +PTR +mempcpy (PTR dst, const PTR src, size_t len) +{ + return (char *) memcpy (dst, src, len) + len; +} diff --git a/external/gpl3/gdb/dist/libiberty/memset.c b/external/gpl3/gdb/dist/libiberty/memset.c new file mode 100644 index 000000000000..476668961271 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/memset.c @@ -0,0 +1,26 @@ +/* memset + This implementation is in the public domain. */ + +/* + +@deftypefn Supplemental void* memset (void *@var{s}, int @var{c}, @ + size_t @var{count}) + +Sets the first @var{count} bytes of @var{s} to the constant byte +@var{c}, returning a pointer to @var{s}. + +@end deftypefn + +*/ + +#include +#include + +PTR +memset (PTR dest, register int val, register size_t len) +{ + register unsigned char *ptr = (unsigned char*)dest; + while (len-- > 0) + *ptr++ = val; + return dest; +} diff --git a/external/gpl3/gdb/dist/libiberty/mkstemps.c b/external/gpl3/gdb/dist/libiberty/mkstemps.c new file mode 100644 index 000000000000..a0e68a73b491 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/mkstemps.c @@ -0,0 +1,147 @@ +/* Copyright (C) 1991, 1992, 1996, 1998, 2004 Free Software Foundation, Inc. + This file is derived from mkstemp.c from the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#include +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_SYS_TIME_H +#include +#endif +#include "ansidecl.h" + +/* We need to provide a type for gcc_uint64_t. */ +#ifdef __GNUC__ +__extension__ typedef unsigned long long gcc_uint64_t; +#else +typedef unsigned long gcc_uint64_t; +#endif + +#ifndef TMP_MAX +#define TMP_MAX 16384 +#endif + +#ifndef O_BINARY +# define O_BINARY 0 +#endif + +/* + +@deftypefn Replacement int mkstemps (char *@var{pattern}, int @var{suffix_len}) + +Generate a unique temporary file name from @var{pattern}. +@var{pattern} has the form: + +@example + @var{path}/ccXXXXXX@var{suffix} +@end example + +@var{suffix_len} tells us how long @var{suffix} is (it can be zero +length). The last six characters of @var{pattern} before @var{suffix} +must be @samp{XXXXXX}; they are replaced with a string that makes the +filename unique. Returns a file descriptor open on the file for +reading and writing. + +@end deftypefn + +*/ + +int +mkstemps (char *pattern, int suffix_len) +{ + static const char letters[] + = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; + static gcc_uint64_t value; +#ifdef HAVE_GETTIMEOFDAY + struct timeval tv; +#endif + char *XXXXXX; + size_t len; + int count; + + len = strlen (pattern); + + if ((int) len < 6 + suffix_len + || strncmp (&pattern[len - 6 - suffix_len], "XXXXXX", 6)) + { + return -1; + } + + XXXXXX = &pattern[len - 6 - suffix_len]; + +#ifdef HAVE_GETTIMEOFDAY + /* Get some more or less random data. */ + gettimeofday (&tv, NULL); + value += ((gcc_uint64_t) tv.tv_usec << 16) ^ tv.tv_sec ^ getpid (); +#else + value += getpid (); +#endif + + for (count = 0; count < TMP_MAX; ++count) + { + gcc_uint64_t v = value; + int fd; + + /* Fill in the random bits. */ + XXXXXX[0] = letters[v % 62]; + v /= 62; + XXXXXX[1] = letters[v % 62]; + v /= 62; + XXXXXX[2] = letters[v % 62]; + v /= 62; + XXXXXX[3] = letters[v % 62]; + v /= 62; + XXXXXX[4] = letters[v % 62]; + v /= 62; + XXXXXX[5] = letters[v % 62]; + + fd = open (pattern, O_BINARY|O_RDWR|O_CREAT|O_EXCL, 0600); + if (fd >= 0) + /* The file does not exist. */ + return fd; + if (errno != EEXIST +#ifdef EISDIR + && errno != EISDIR +#endif + ) + /* Fatal error (EPERM, ENOSPC etc). Doesn't make sense to loop. */ + break; + + /* This is a random value. It is only necessary that the next + TMP_MAX values generated by adding 7777 to VALUE are different + with (module 2^32). */ + value += 7777; + } + + /* We return the null string if we can't find a unique file name. */ + pattern[0] = '\0'; + return -1; +} diff --git a/external/gpl3/gdb/dist/libiberty/msdos.c b/external/gpl3/gdb/dist/libiberty/msdos.c new file mode 100644 index 000000000000..923e64d4ede6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/msdos.c @@ -0,0 +1,15 @@ +char msg[] = "No vfork available - aborting\n"; +vfork() +{ + write(1, msg, sizeof(msg)); +} + +sigsetmask() +{ + /* no signals support in go32 (yet) */ +} + +waitpid() +{ + return -1; +} diff --git a/external/gpl3/gdb/dist/libiberty/objalloc.c b/external/gpl3/gdb/dist/libiberty/objalloc.c new file mode 100644 index 000000000000..3ddac2ce4cbf --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/objalloc.c @@ -0,0 +1,291 @@ +/* objalloc.c -- routines to allocate memory for objects + Copyright 1997 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Solutions. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "ansidecl.h" + +#include "objalloc.h" + +/* Get a definition for NULL. */ +#include + +#if VMS +#include +#include +#else + +/* Get a definition for size_t. */ +#include + +#ifdef HAVE_STDLIB_H +#include +#else +/* For systems with larger pointers than ints, this must be declared. */ +extern PTR malloc (size_t); +extern void free (PTR); +#endif + +#endif + +/* These routines allocate space for an object. Freeing allocated + space may or may not free all more recently allocated space. + + We handle large and small allocation requests differently. If we + don't have enough space in the current block, and the allocation + request is for more than 512 bytes, we simply pass it through to + malloc. */ + +/* The objalloc structure is defined in objalloc.h. */ + +/* This structure appears at the start of each chunk. */ + +struct objalloc_chunk +{ + /* Next chunk. */ + struct objalloc_chunk *next; + /* If this chunk contains large objects, this is the value of + current_ptr when this chunk was allocated. If this chunk + contains small objects, this is NULL. */ + char *current_ptr; +}; + +/* The aligned size of objalloc_chunk. */ + +#define CHUNK_HEADER_SIZE \ + ((sizeof (struct objalloc_chunk) + OBJALLOC_ALIGN - 1) \ + &~ (OBJALLOC_ALIGN - 1)) + +/* We ask for this much memory each time we create a chunk which is to + hold small objects. */ + +#define CHUNK_SIZE (4096 - 32) + +/* A request for this amount or more is just passed through to malloc. */ + +#define BIG_REQUEST (512) + +/* Create an objalloc structure. */ + +struct objalloc * +objalloc_create (void) +{ + struct objalloc *ret; + struct objalloc_chunk *chunk; + + ret = (struct objalloc *) malloc (sizeof *ret); + if (ret == NULL) + return NULL; + + ret->chunks = (PTR) malloc (CHUNK_SIZE); + if (ret->chunks == NULL) + { + free (ret); + return NULL; + } + + chunk = (struct objalloc_chunk *) ret->chunks; + chunk->next = NULL; + chunk->current_ptr = NULL; + + ret->current_ptr = (char *) chunk + CHUNK_HEADER_SIZE; + ret->current_space = CHUNK_SIZE - CHUNK_HEADER_SIZE; + + return ret; +} + +/* Allocate space from an objalloc structure. */ + +PTR +_objalloc_alloc (struct objalloc *o, unsigned long len) +{ + /* We avoid confusion from zero sized objects by always allocating + at least 1 byte. */ + if (len == 0) + len = 1; + + len = (len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1); + + if (len <= o->current_space) + { + o->current_ptr += len; + o->current_space -= len; + return (PTR) (o->current_ptr - len); + } + + if (len >= BIG_REQUEST) + { + char *ret; + struct objalloc_chunk *chunk; + + ret = (char *) malloc (CHUNK_HEADER_SIZE + len); + if (ret == NULL) + return NULL; + + chunk = (struct objalloc_chunk *) ret; + chunk->next = (struct objalloc_chunk *) o->chunks; + chunk->current_ptr = o->current_ptr; + + o->chunks = (PTR) chunk; + + return (PTR) (ret + CHUNK_HEADER_SIZE); + } + else + { + struct objalloc_chunk *chunk; + + chunk = (struct objalloc_chunk *) malloc (CHUNK_SIZE); + if (chunk == NULL) + return NULL; + chunk->next = (struct objalloc_chunk *) o->chunks; + chunk->current_ptr = NULL; + + o->current_ptr = (char *) chunk + CHUNK_HEADER_SIZE; + o->current_space = CHUNK_SIZE - CHUNK_HEADER_SIZE; + + o->chunks = (PTR) chunk; + + return objalloc_alloc (o, len); + } +} + +/* Free an entire objalloc structure. */ + +void +objalloc_free (struct objalloc *o) +{ + struct objalloc_chunk *l; + + l = (struct objalloc_chunk *) o->chunks; + while (l != NULL) + { + struct objalloc_chunk *next; + + next = l->next; + free (l); + l = next; + } + + free (o); +} + +/* Free a block from an objalloc structure. This also frees all more + recently allocated blocks. */ + +void +objalloc_free_block (struct objalloc *o, PTR block) +{ + struct objalloc_chunk *p, *small; + char *b = (char *) block; + + /* First set P to the chunk which contains the block we are freeing, + and set Q to the last small object chunk we see before P. */ + small = NULL; + for (p = (struct objalloc_chunk *) o->chunks; p != NULL; p = p->next) + { + if (p->current_ptr == NULL) + { + if (b > (char *) p && b < (char *) p + CHUNK_SIZE) + break; + small = p; + } + else + { + if (b == (char *) p + CHUNK_HEADER_SIZE) + break; + } + } + + /* If we can't find the chunk, the caller has made a mistake. */ + if (p == NULL) + abort (); + + if (p->current_ptr == NULL) + { + struct objalloc_chunk *q; + struct objalloc_chunk *first; + + /* The block is in a chunk containing small objects. We can + free every chunk through SMALL, because they have certainly + been allocated more recently. After SMALL, we will not see + any chunks containing small objects; we can free any big + chunk if the current_ptr is greater than or equal to B. We + can then reset the new current_ptr to B. */ + + first = NULL; + q = (struct objalloc_chunk *) o->chunks; + while (q != p) + { + struct objalloc_chunk *next; + + next = q->next; + if (small != NULL) + { + if (small == q) + small = NULL; + free (q); + } + else if (q->current_ptr > b) + free (q); + else if (first == NULL) + first = q; + + q = next; + } + + if (first == NULL) + first = p; + o->chunks = (PTR) first; + + /* Now start allocating from this small block again. */ + o->current_ptr = b; + o->current_space = ((char *) p + CHUNK_SIZE) - b; + } + else + { + struct objalloc_chunk *q; + char *current_ptr; + + /* This block is in a large chunk by itself. We can free + everything on the list up to and including this block. We + then start allocating from the next chunk containing small + objects, setting current_ptr from the value stored with the + large chunk we are freeing. */ + + current_ptr = p->current_ptr; + p = p->next; + + q = (struct objalloc_chunk *) o->chunks; + while (q != p) + { + struct objalloc_chunk *next; + + next = q->next; + free (q); + q = next; + } + + o->chunks = (PTR) p; + + while (p->current_ptr != NULL) + p = p->next; + + o->current_ptr = current_ptr; + o->current_space = ((char *) p + CHUNK_SIZE) - current_ptr; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/obstack.c b/external/gpl3/gdb/dist/libiberty/obstack.c new file mode 100644 index 000000000000..a6dbaf095dfb --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/obstack.c @@ -0,0 +1,510 @@ +/* obstack.c - subroutines used implicitly by object stack macros + Copyright (C) 1988,89,90,91,92,93,94,96,97 Free Software Foundation, Inc. + + + NOTE: This source is derived from an old version taken from the GNU C + Library (glibc). + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "obstack.h" + +/* NOTE BEFORE MODIFYING THIS FILE: This version number must be + incremented whenever callers compiled using an old obstack.h can no + longer properly call the functions in this obstack.c. */ +#define OBSTACK_INTERFACE_VERSION 1 + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself, and the installed library + supports the same library interface we do. This code is part of the GNU + C Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object + files, it is simpler to just do this in the source for each such file. */ + +#include /* Random thing to get __GNU_LIBRARY__. */ +#if !defined (_LIBC) && defined (__GNU_LIBRARY__) && __GNU_LIBRARY__ > 1 +#include +#if _GNU_OBSTACK_INTERFACE_VERSION == OBSTACK_INTERFACE_VERSION +#define ELIDE_CODE +#endif +#endif + + +#ifndef ELIDE_CODE + + +#define POINTER void * + +/* Determine default alignment. */ +struct fooalign {char x; double d;}; +#define DEFAULT_ALIGNMENT \ + ((PTR_INT_TYPE) ((char *) &((struct fooalign *) 0)->d - (char *) 0)) +/* If malloc were really smart, it would round addresses to DEFAULT_ALIGNMENT. + But in fact it might be less smart and round addresses to as much as + DEFAULT_ROUNDING. So we prepare for it to do that. */ +union fooround {long x; double d;}; +#define DEFAULT_ROUNDING (sizeof (union fooround)) + +/* When we copy a long block of data, this is the unit to do it with. + On some machines, copying successive ints does not work; + in such a case, redefine COPYING_UNIT to `long' (if that works) + or `char' as a last resort. */ +#ifndef COPYING_UNIT +#define COPYING_UNIT int +#endif + + +/* The functions allocating more room by calling `obstack_chunk_alloc' + jump to the handler pointed to by `obstack_alloc_failed_handler'. + This variable by default points to the internal function + `print_and_abort'. */ +static void print_and_abort (void); +void (*obstack_alloc_failed_handler) (void) = print_and_abort; + +/* Exit value used when `print_and_abort' is used. */ +#if defined __GNU_LIBRARY__ || defined HAVE_STDLIB_H +#include +#endif +#ifndef EXIT_FAILURE +#define EXIT_FAILURE 1 +#endif +int obstack_exit_failure = EXIT_FAILURE; + +/* The non-GNU-C macros copy the obstack into this global variable + to avoid multiple evaluation. */ + +struct obstack *_obstack; + +/* Define a macro that either calls functions with the traditional malloc/free + calling interface, or calls functions with the mmalloc/mfree interface + (that adds an extra first argument), based on the state of use_extra_arg. + For free, do not use ?:, since some compilers, like the MIPS compilers, + do not allow (expr) ? void : void. */ + +#if defined (__STDC__) && __STDC__ +#define CALL_CHUNKFUN(h, size) \ + (((h) -> use_extra_arg) \ + ? (*(h)->chunkfun) ((h)->extra_arg, (size)) \ + : (*(struct _obstack_chunk *(*) (long)) (h)->chunkfun) ((size))) + +#define CALL_FREEFUN(h, old_chunk) \ + do { \ + if ((h) -> use_extra_arg) \ + (*(h)->freefun) ((h)->extra_arg, (old_chunk)); \ + else \ + (*(void (*) (void *)) (h)->freefun) ((old_chunk)); \ + } while (0) +#else +#define CALL_CHUNKFUN(h, size) \ + (((h) -> use_extra_arg) \ + ? (*(h)->chunkfun) ((h)->extra_arg, (size)) \ + : (*(struct _obstack_chunk *(*) ()) (h)->chunkfun) ((size))) + +#define CALL_FREEFUN(h, old_chunk) \ + do { \ + if ((h) -> use_extra_arg) \ + (*(h)->freefun) ((h)->extra_arg, (old_chunk)); \ + else \ + (*(void (*) ()) (h)->freefun) ((old_chunk)); \ + } while (0) +#endif + + +/* Initialize an obstack H for use. Specify chunk size SIZE (0 means default). + Objects start on multiples of ALIGNMENT (0 means use default). + CHUNKFUN is the function to use to allocate chunks, + and FREEFUN the function to free them. + + Return nonzero if successful, zero if out of memory. + To recover from an out of memory error, + free up some memory, then call this again. */ + +int +_obstack_begin (struct obstack *h, int size, int alignment, + POINTER (*chunkfun) (long), void (*freefun) (void *)) +{ + register struct _obstack_chunk *chunk; /* points to new chunk */ + + if (alignment == 0) + alignment = (int) DEFAULT_ALIGNMENT; + if (size == 0) + /* Default size is what GNU malloc can fit in a 4096-byte block. */ + { + /* 12 is sizeof (mhead) and 4 is EXTRA from GNU malloc. + Use the values for range checking, because if range checking is off, + the extra bytes won't be missed terribly, but if range checking is on + and we used a larger request, a whole extra 4096 bytes would be + allocated. + + These number are irrelevant to the new GNU malloc. I suspect it is + less sensitive to the size of the request. */ + int extra = ((((12 + DEFAULT_ROUNDING - 1) & ~(DEFAULT_ROUNDING - 1)) + + 4 + DEFAULT_ROUNDING - 1) + & ~(DEFAULT_ROUNDING - 1)); + size = 4096 - extra; + } + + h->chunkfun = (struct _obstack_chunk * (*)(void *, long)) chunkfun; + h->freefun = (void (*) (void *, struct _obstack_chunk *)) freefun; + h->chunk_size = size; + h->alignment_mask = alignment - 1; + h->use_extra_arg = 0; + + chunk = h->chunk = CALL_CHUNKFUN (h, h -> chunk_size); + if (!chunk) + (*obstack_alloc_failed_handler) (); + h->next_free = h->object_base = chunk->contents; + h->chunk_limit = chunk->limit + = (char *) chunk + h->chunk_size; + chunk->prev = 0; + /* The initial chunk now contains no empty object. */ + h->maybe_empty_object = 0; + h->alloc_failed = 0; + return 1; +} + +int +_obstack_begin_1 (struct obstack *h, int size, int alignment, + POINTER (*chunkfun) (POINTER, long), + void (*freefun) (POINTER, POINTER), POINTER arg) +{ + register struct _obstack_chunk *chunk; /* points to new chunk */ + + if (alignment == 0) + alignment = (int) DEFAULT_ALIGNMENT; + if (size == 0) + /* Default size is what GNU malloc can fit in a 4096-byte block. */ + { + /* 12 is sizeof (mhead) and 4 is EXTRA from GNU malloc. + Use the values for range checking, because if range checking is off, + the extra bytes won't be missed terribly, but if range checking is on + and we used a larger request, a whole extra 4096 bytes would be + allocated. + + These number are irrelevant to the new GNU malloc. I suspect it is + less sensitive to the size of the request. */ + int extra = ((((12 + DEFAULT_ROUNDING - 1) & ~(DEFAULT_ROUNDING - 1)) + + 4 + DEFAULT_ROUNDING - 1) + & ~(DEFAULT_ROUNDING - 1)); + size = 4096 - extra; + } + + h->chunkfun = (struct _obstack_chunk * (*)(void *,long)) chunkfun; + h->freefun = (void (*) (void *, struct _obstack_chunk *)) freefun; + h->chunk_size = size; + h->alignment_mask = alignment - 1; + h->extra_arg = arg; + h->use_extra_arg = 1; + + chunk = h->chunk = CALL_CHUNKFUN (h, h -> chunk_size); + if (!chunk) + (*obstack_alloc_failed_handler) (); + h->next_free = h->object_base = chunk->contents; + h->chunk_limit = chunk->limit + = (char *) chunk + h->chunk_size; + chunk->prev = 0; + /* The initial chunk now contains no empty object. */ + h->maybe_empty_object = 0; + h->alloc_failed = 0; + return 1; +} + +/* Allocate a new current chunk for the obstack *H + on the assumption that LENGTH bytes need to be added + to the current object, or a new object of length LENGTH allocated. + Copies any partial object from the end of the old chunk + to the beginning of the new one. */ + +void +_obstack_newchunk (struct obstack *h, int length) +{ + register struct _obstack_chunk *old_chunk = h->chunk; + register struct _obstack_chunk *new_chunk; + register long new_size; + register long obj_size = h->next_free - h->object_base; + register long i; + long already; + + /* Compute size for new chunk. */ + new_size = (obj_size + length) + (obj_size >> 3) + 100; + if (new_size < h->chunk_size) + new_size = h->chunk_size; + + /* Allocate and initialize the new chunk. */ + new_chunk = CALL_CHUNKFUN (h, new_size); + if (!new_chunk) + (*obstack_alloc_failed_handler) (); + h->chunk = new_chunk; + new_chunk->prev = old_chunk; + new_chunk->limit = h->chunk_limit = (char *) new_chunk + new_size; + + /* Move the existing object to the new chunk. + Word at a time is fast and is safe if the object + is sufficiently aligned. */ + if (h->alignment_mask + 1 >= DEFAULT_ALIGNMENT) + { + for (i = obj_size / sizeof (COPYING_UNIT) - 1; + i >= 0; i--) + ((COPYING_UNIT *)new_chunk->contents)[i] + = ((COPYING_UNIT *)h->object_base)[i]; + /* We used to copy the odd few remaining bytes as one extra COPYING_UNIT, + but that can cross a page boundary on a machine + which does not do strict alignment for COPYING_UNITS. */ + already = obj_size / sizeof (COPYING_UNIT) * sizeof (COPYING_UNIT); + } + else + already = 0; + /* Copy remaining bytes one by one. */ + for (i = already; i < obj_size; i++) + new_chunk->contents[i] = h->object_base[i]; + + /* If the object just copied was the only data in OLD_CHUNK, + free that chunk and remove it from the chain. + But not if that chunk might contain an empty object. */ + if (h->object_base == old_chunk->contents && ! h->maybe_empty_object) + { + new_chunk->prev = old_chunk->prev; + CALL_FREEFUN (h, old_chunk); + } + + h->object_base = new_chunk->contents; + h->next_free = h->object_base + obj_size; + /* The new chunk certainly contains no empty object yet. */ + h->maybe_empty_object = 0; +} + +/* Return nonzero if object OBJ has been allocated from obstack H. + This is here for debugging. + If you use it in a program, you are probably losing. */ + +/* Suppress -Wmissing-prototypes warning. We don't want to declare this in + obstack.h because it is just for debugging. */ +int _obstack_allocated_p (struct obstack *h, POINTER obj); + +int +_obstack_allocated_p (struct obstack *h, POINTER obj) +{ + register struct _obstack_chunk *lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk *plp; /* point to previous chunk if any */ + + lp = (h)->chunk; + /* We use >= rather than > since the object cannot be exactly at + the beginning of the chunk but might be an empty object exactly + at the end of an adjacent chunk. */ + while (lp != 0 && ((POINTER) lp >= obj || (POINTER) (lp)->limit < obj)) + { + plp = lp->prev; + lp = plp; + } + return lp != 0; +} + +/* Free objects in obstack H, including OBJ and everything allocate + more recently than OBJ. If OBJ is zero, free everything in H. */ + +#undef obstack_free + +/* This function has two names with identical definitions. + This is the first one, called from non-ANSI code. */ + +void +_obstack_free (struct obstack *h, POINTER obj) +{ + register struct _obstack_chunk *lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk *plp; /* point to previous chunk if any */ + + lp = h->chunk; + /* We use >= because there cannot be an object at the beginning of a chunk. + But there can be an empty object at that address + at the end of another chunk. */ + while (lp != 0 && ((POINTER) lp >= obj || (POINTER) (lp)->limit < obj)) + { + plp = lp->prev; + CALL_FREEFUN (h, lp); + lp = plp; + /* If we switch chunks, we can't tell whether the new current + chunk contains an empty object, so assume that it may. */ + h->maybe_empty_object = 1; + } + if (lp) + { + h->object_base = h->next_free = (char *) (obj); + h->chunk_limit = lp->limit; + h->chunk = lp; + } + else if (obj != 0) + /* obj is not in any of the chunks! */ + abort (); +} + +/* This function is used from ANSI code. */ + +void +obstack_free (struct obstack *h, POINTER obj) +{ + register struct _obstack_chunk *lp; /* below addr of any objects in this chunk */ + register struct _obstack_chunk *plp; /* point to previous chunk if any */ + + lp = h->chunk; + /* We use >= because there cannot be an object at the beginning of a chunk. + But there can be an empty object at that address + at the end of another chunk. */ + while (lp != 0 && ((POINTER) lp >= obj || (POINTER) (lp)->limit < obj)) + { + plp = lp->prev; + CALL_FREEFUN (h, lp); + lp = plp; + /* If we switch chunks, we can't tell whether the new current + chunk contains an empty object, so assume that it may. */ + h->maybe_empty_object = 1; + } + if (lp) + { + h->object_base = h->next_free = (char *) (obj); + h->chunk_limit = lp->limit; + h->chunk = lp; + } + else if (obj != 0) + /* obj is not in any of the chunks! */ + abort (); +} + +int +_obstack_memory_used (struct obstack *h) +{ + register struct _obstack_chunk* lp; + register int nbytes = 0; + + for (lp = h->chunk; lp != 0; lp = lp->prev) + { + nbytes += lp->limit - (char *) lp; + } + return nbytes; +} + +/* Define the error handler. */ +#ifndef _ +# if (HAVE_LIBINTL_H && ENABLE_NLS) || defined _LIBC +# include +# ifndef _ +# define _(Str) gettext (Str) +# endif +# else +# define _(Str) (Str) +# endif +#endif + +static void +print_and_abort (void) +{ + fputs (_("memory exhausted\n"), stderr); + exit (obstack_exit_failure); +} + +#if 0 +/* These are now turned off because the applications do not use it + and it uses bcopy via obstack_grow, which causes trouble on sysV. */ + +/* Now define the functional versions of the obstack macros. + Define them to simply use the corresponding macros to do the job. */ + +/* The function names appear in parentheses in order to prevent + the macro-definitions of the names from being expanded there. */ + +POINTER (obstack_base) (struct obstack *obstack) +{ + return obstack_base (obstack); +} + +POINTER (obstack_next_free) (struct obstack *obstack) +{ + return obstack_next_free (obstack); +} + +int (obstack_object_size) (struct obstack *obstack) +{ + return obstack_object_size (obstack); +} + +int (obstack_room) (struct obstack *obstack) +{ + return obstack_room (obstack); +} + +int (obstack_make_room) (struct obstack *obstack, int length) +{ + return obstack_make_room (obstack, length); +} + +void (obstack_grow) (struct obstack *obstack, POINTER pointer, int length) +{ + obstack_grow (obstack, pointer, length); +} + +void (obstack_grow0) (struct obstack *obstack, POINTER pointer, int length) +{ + obstack_grow0 (obstack, pointer, length); +} + +void (obstack_1grow) (struct obstack *obstack, int character) +{ + obstack_1grow (obstack, character); +} + +void (obstack_blank) (struct obstack *obstack, int length) +{ + obstack_blank (obstack, length); +} + +void (obstack_1grow_fast) (struct obstack *obstack, int character) +{ + obstack_1grow_fast (obstack, character); +} + +void (obstack_blank_fast) (struct obstack *obstack, int length) +{ + obstack_blank_fast (obstack, length); +} + +POINTER (obstack_finish) (struct obstack *obstack) +{ + return obstack_finish (obstack); +} + +POINTER (obstack_alloc) (struct obstack *obstack, int length) +{ + return obstack_alloc (obstack, length); +} + +POINTER (obstack_copy) (struct obstack *obstack, POINTER pointer, int length) +{ + return obstack_copy (obstack, pointer, length); +} + +POINTER (obstack_copy0) (struct obstack *obstack, POINTER pointer, int length) +{ + return obstack_copy0 (obstack, pointer, length); +} + +#endif /* 0 */ + +#endif /* !ELIDE_CODE */ diff --git a/external/gpl3/gdb/dist/libiberty/obstacks.texi b/external/gpl3/gdb/dist/libiberty/obstacks.texi new file mode 100644 index 000000000000..a1b1b478c389 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/obstacks.texi @@ -0,0 +1,758 @@ +@node Obstacks,Licenses,Functions,Top +@chapter Obstacks +@cindex obstacks + +An @dfn{obstack} is a pool of memory containing a stack of objects. You +can create any number of separate obstacks, and then allocate objects in +specified obstacks. Within each obstack, the last object allocated must +always be the first one freed, but distinct obstacks are independent of +each other. + +Aside from this one constraint of order of freeing, obstacks are totally +general: an obstack can contain any number of objects of any size. They +are implemented with macros, so allocation is usually very fast as long as +the objects are usually small. And the only space overhead per object is +the padding needed to start each object on a suitable boundary. + +@menu +* Creating Obstacks:: How to declare an obstack in your program. +* Preparing for Obstacks:: Preparations needed before you can + use obstacks. +* Allocation in an Obstack:: Allocating objects in an obstack. +* Freeing Obstack Objects:: Freeing objects in an obstack. +* Obstack Functions:: The obstack functions are both + functions and macros. +* Growing Objects:: Making an object bigger by stages. +* Extra Fast Growing:: Extra-high-efficiency (though more + complicated) growing objects. +* Status of an Obstack:: Inquiries about the status of an obstack. +* Obstacks Data Alignment:: Controlling alignment of objects in obstacks. +* Obstack Chunks:: How obstacks obtain and release chunks; + efficiency considerations. +* Summary of Obstacks:: +@end menu + +@node Creating Obstacks +@section Creating Obstacks + +The utilities for manipulating obstacks are declared in the header +file @file{obstack.h}. +@pindex obstack.h + +@comment obstack.h +@comment GNU +@deftp {Data Type} {struct obstack} +An obstack is represented by a data structure of type @code{struct +obstack}. This structure has a small fixed size; it records the status +of the obstack and how to find the space in which objects are allocated. +It does not contain any of the objects themselves. You should not try +to access the contents of the structure directly; use only the functions +described in this chapter. +@end deftp + +You can declare variables of type @code{struct obstack} and use them as +obstacks, or you can allocate obstacks dynamically like any other kind +of object. Dynamic allocation of obstacks allows your program to have a +variable number of different stacks. (You can even allocate an +obstack structure in another obstack, but this is rarely useful.) + +All the functions that work with obstacks require you to specify which +obstack to use. You do this with a pointer of type @code{struct obstack +*}. In the following, we often say ``an obstack'' when strictly +speaking the object at hand is such a pointer. + +The objects in the obstack are packed into large blocks called +@dfn{chunks}. The @code{struct obstack} structure points to a chain of +the chunks currently in use. + +The obstack library obtains a new chunk whenever you allocate an object +that won't fit in the previous chunk. Since the obstack library manages +chunks automatically, you don't need to pay much attention to them, but +you do need to supply a function which the obstack library should use to +get a chunk. Usually you supply a function which uses @code{malloc} +directly or indirectly. You must also supply a function to free a chunk. +These matters are described in the following section. + +@node Preparing for Obstacks +@section Preparing for Using Obstacks + +Each source file in which you plan to use the obstack functions +must include the header file @file{obstack.h}, like this: + +@smallexample +#include +@end smallexample + +@findex obstack_chunk_alloc +@findex obstack_chunk_free +Also, if the source file uses the macro @code{obstack_init}, it must +declare or define two functions or macros that will be called by the +obstack library. One, @code{obstack_chunk_alloc}, is used to allocate +the chunks of memory into which objects are packed. The other, +@code{obstack_chunk_free}, is used to return chunks when the objects in +them are freed. These macros should appear before any use of obstacks +in the source file. + +Usually these are defined to use @code{malloc} via the intermediary +@code{xmalloc} (@pxref{Unconstrained Allocation, , , libc, The GNU C Library Reference Manual}). This is done with +the following pair of macro definitions: + +@smallexample +#define obstack_chunk_alloc xmalloc +#define obstack_chunk_free free +@end smallexample + +@noindent +Though the memory you get using obstacks really comes from @code{malloc}, +using obstacks is faster because @code{malloc} is called less often, for +larger blocks of memory. @xref{Obstack Chunks}, for full details. + +At run time, before the program can use a @code{struct obstack} object +as an obstack, it must initialize the obstack by calling +@code{obstack_init}. + +@comment obstack.h +@comment GNU +@deftypefun int obstack_init (struct obstack *@var{obstack-ptr}) +Initialize obstack @var{obstack-ptr} for allocation of objects. This +function calls the obstack's @code{obstack_chunk_alloc} function. If +allocation of memory fails, the function pointed to by +@code{obstack_alloc_failed_handler} is called. The @code{obstack_init} +function always returns 1 (Compatibility notice: Former versions of +obstack returned 0 if allocation failed). +@end deftypefun + +Here are two examples of how to allocate the space for an obstack and +initialize it. First, an obstack that is a static variable: + +@smallexample +static struct obstack myobstack; +@dots{} +obstack_init (&myobstack); +@end smallexample + +@noindent +Second, an obstack that is itself dynamically allocated: + +@smallexample +struct obstack *myobstack_ptr + = (struct obstack *) xmalloc (sizeof (struct obstack)); + +obstack_init (myobstack_ptr); +@end smallexample + +@comment obstack.h +@comment GNU +@defvar obstack_alloc_failed_handler +The value of this variable is a pointer to a function that +@code{obstack} uses when @code{obstack_chunk_alloc} fails to allocate +memory. The default action is to print a message and abort. +You should supply a function that either calls @code{exit} +(@pxref{Program Termination, , , libc, The GNU C Library Reference Manual}) or @code{longjmp} (@pxref{Non-Local +Exits, , , libc, The GNU C Library Reference Manual}) and doesn't return. + +@smallexample +void my_obstack_alloc_failed (void) +@dots{} +obstack_alloc_failed_handler = &my_obstack_alloc_failed; +@end smallexample + +@end defvar + +@node Allocation in an Obstack +@section Allocation in an Obstack +@cindex allocation (obstacks) + +The most direct way to allocate an object in an obstack is with +@code{obstack_alloc}, which is invoked almost like @code{malloc}. + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_alloc (struct obstack *@var{obstack-ptr}, int @var{size}) +This allocates an uninitialized block of @var{size} bytes in an obstack +and returns its address. Here @var{obstack-ptr} specifies which obstack +to allocate the block in; it is the address of the @code{struct obstack} +object which represents the obstack. Each obstack function or macro +requires you to specify an @var{obstack-ptr} as the first argument. + +This function calls the obstack's @code{obstack_chunk_alloc} function if +it needs to allocate a new chunk of memory; it calls +@code{obstack_alloc_failed_handler} if allocation of memory by +@code{obstack_chunk_alloc} failed. +@end deftypefun + +For example, here is a function that allocates a copy of a string @var{str} +in a specific obstack, which is in the variable @code{string_obstack}: + +@smallexample +struct obstack string_obstack; + +char * +copystring (char *string) +@{ + size_t len = strlen (string) + 1; + char *s = (char *) obstack_alloc (&string_obstack, len); + memcpy (s, string, len); + return s; +@} +@end smallexample + +To allocate a block with specified contents, use the function +@code{obstack_copy}, declared like this: + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_copy (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +This allocates a block and initializes it by copying @var{size} +bytes of data starting at @var{address}. It calls +@code{obstack_alloc_failed_handler} if allocation of memory by +@code{obstack_chunk_alloc} failed. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_copy0 (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +Like @code{obstack_copy}, but appends an extra byte containing a null +character. This extra byte is not counted in the argument @var{size}. +@end deftypefun + +The @code{obstack_copy0} function is convenient for copying a sequence +of characters into an obstack as a null-terminated string. Here is an +example of its use: + +@smallexample +char * +obstack_savestring (char *addr, int size) +@{ + return obstack_copy0 (&myobstack, addr, size); +@} +@end smallexample + +@noindent +Contrast this with the previous example of @code{savestring} using +@code{malloc} (@pxref{Basic Allocation, , , libc, The GNU C Library Reference Manual}). + +@node Freeing Obstack Objects +@section Freeing Objects in an Obstack +@cindex freeing (obstacks) + +To free an object allocated in an obstack, use the function +@code{obstack_free}. Since the obstack is a stack of objects, freeing +one object automatically frees all other objects allocated more recently +in the same obstack. + +@comment obstack.h +@comment GNU +@deftypefun void obstack_free (struct obstack *@var{obstack-ptr}, void *@var{object}) +If @var{object} is a null pointer, everything allocated in the obstack +is freed. Otherwise, @var{object} must be the address of an object +allocated in the obstack. Then @var{object} is freed, along with +everything allocated in @var{obstack} since @var{object}. +@end deftypefun + +Note that if @var{object} is a null pointer, the result is an +uninitialized obstack. To free all memory in an obstack but leave it +valid for further allocation, call @code{obstack_free} with the address +of the first object allocated on the obstack: + +@smallexample +obstack_free (obstack_ptr, first_object_allocated_ptr); +@end smallexample + +Recall that the objects in an obstack are grouped into chunks. When all +the objects in a chunk become free, the obstack library automatically +frees the chunk (@pxref{Preparing for Obstacks}). Then other +obstacks, or non-obstack allocation, can reuse the space of the chunk. + +@node Obstack Functions +@section Obstack Functions and Macros +@cindex macros + +The interfaces for using obstacks may be defined either as functions or +as macros, depending on the compiler. The obstack facility works with +all C compilers, including both @w{ISO C} and traditional C, but there are +precautions you must take if you plan to use compilers other than GNU C. + +If you are using an old-fashioned @w{non-ISO C} compiler, all the obstack +``functions'' are actually defined only as macros. You can call these +macros like functions, but you cannot use them in any other way (for +example, you cannot take their address). + +Calling the macros requires a special precaution: namely, the first +operand (the obstack pointer) may not contain any side effects, because +it may be computed more than once. For example, if you write this: + +@smallexample +obstack_alloc (get_obstack (), 4); +@end smallexample + +@noindent +you will find that @code{get_obstack} may be called several times. +If you use @code{*obstack_list_ptr++} as the obstack pointer argument, +you will get very strange results since the incrementation may occur +several times. + +In @w{ISO C}, each function has both a macro definition and a function +definition. The function definition is used if you take the address of the +function without calling it. An ordinary call uses the macro definition by +default, but you can request the function definition instead by writing the +function name in parentheses, as shown here: + +@smallexample +char *x; +void *(*funcp) (); +/* @r{Use the macro}. */ +x = (char *) obstack_alloc (obptr, size); +/* @r{Call the function}. */ +x = (char *) (obstack_alloc) (obptr, size); +/* @r{Take the address of the function}. */ +funcp = obstack_alloc; +@end smallexample + +@noindent +This is the same situation that exists in @w{ISO C} for the standard library +functions. @xref{Macro Definitions, , , libc, The GNU C Library Reference Manual}. + +@strong{Warning:} When you do use the macros, you must observe the +precaution of avoiding side effects in the first operand, even in @w{ISO C}. + +If you use the GNU C compiler, this precaution is not necessary, because +various language extensions in GNU C permit defining the macros so as to +compute each argument only once. + +@node Growing Objects +@section Growing Objects +@cindex growing objects (in obstacks) +@cindex changing the size of a block (obstacks) + +Because memory in obstack chunks is used sequentially, it is possible to +build up an object step by step, adding one or more bytes at a time to the +end of the object. With this technique, you do not need to know how much +data you will put in the object until you come to the end of it. We call +this the technique of @dfn{growing objects}. The special functions +for adding data to the growing object are described in this section. + +You don't need to do anything special when you start to grow an object. +Using one of the functions to add data to the object automatically +starts it. However, it is necessary to say explicitly when the object is +finished. This is done with the function @code{obstack_finish}. + +The actual address of the object thus built up is not known until the +object is finished. Until then, it always remains possible that you will +add so much data that the object must be copied into a new chunk. + +While the obstack is in use for a growing object, you cannot use it for +ordinary allocation of another object. If you try to do so, the space +already added to the growing object will become part of the other object. + +@comment obstack.h +@comment GNU +@deftypefun void obstack_blank (struct obstack *@var{obstack-ptr}, int @var{size}) +The most basic function for adding to a growing object is +@code{obstack_blank}, which adds space without initializing it. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_grow (struct obstack *@var{obstack-ptr}, void *@var{data}, int @var{size}) +To add a block of initialized space, use @code{obstack_grow}, which is +the growing-object analogue of @code{obstack_copy}. It adds @var{size} +bytes of data to the growing object, copying the contents from +@var{data}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_grow0 (struct obstack *@var{obstack-ptr}, void *@var{data}, int @var{size}) +This is the growing-object analogue of @code{obstack_copy0}. It adds +@var{size} bytes copied from @var{data}, followed by an additional null +character. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_1grow (struct obstack *@var{obstack-ptr}, char @var{c}) +To add one character at a time, use the function @code{obstack_1grow}. +It adds a single byte containing @var{c} to the growing object. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_ptr_grow (struct obstack *@var{obstack-ptr}, void *@var{data}) +Adding the value of a pointer one can use the function +@code{obstack_ptr_grow}. It adds @code{sizeof (void *)} bytes +containing the value of @var{data}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_int_grow (struct obstack *@var{obstack-ptr}, int @var{data}) +A single value of type @code{int} can be added by using the +@code{obstack_int_grow} function. It adds @code{sizeof (int)} bytes to +the growing object and initializes them with the value of @var{data}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_finish (struct obstack *@var{obstack-ptr}) +When you are finished growing the object, use the function +@code{obstack_finish} to close it off and return its final address. + +Once you have finished the object, the obstack is available for ordinary +allocation or for growing another object. + +This function can return a null pointer under the same conditions as +@code{obstack_alloc} (@pxref{Allocation in an Obstack}). +@end deftypefun + +When you build an object by growing it, you will probably need to know +afterward how long it became. You need not keep track of this as you grow +the object, because you can find out the length from the obstack just +before finishing the object with the function @code{obstack_object_size}, +declared as follows: + +@comment obstack.h +@comment GNU +@deftypefun int obstack_object_size (struct obstack *@var{obstack-ptr}) +This function returns the current size of the growing object, in bytes. +Remember to call this function @emph{before} finishing the object. +After it is finished, @code{obstack_object_size} will return zero. +@end deftypefun + +If you have started growing an object and wish to cancel it, you should +finish it and then free it, like this: + +@smallexample +obstack_free (obstack_ptr, obstack_finish (obstack_ptr)); +@end smallexample + +@noindent +This has no effect if no object was growing. + +@cindex shrinking objects +You can use @code{obstack_blank} with a negative size argument to make +the current object smaller. Just don't try to shrink it beyond zero +length---there's no telling what will happen if you do that. + +@node Extra Fast Growing +@section Extra Fast Growing Objects +@cindex efficiency and obstacks + +The usual functions for growing objects incur overhead for checking +whether there is room for the new growth in the current chunk. If you +are frequently constructing objects in small steps of growth, this +overhead can be significant. + +You can reduce the overhead by using special ``fast growth'' +functions that grow the object without checking. In order to have a +robust program, you must do the checking yourself. If you do this checking +in the simplest way each time you are about to add data to the object, you +have not saved anything, because that is what the ordinary growth +functions do. But if you can arrange to check less often, or check +more efficiently, then you make the program faster. + +The function @code{obstack_room} returns the amount of room available +in the current chunk. It is declared as follows: + +@comment obstack.h +@comment GNU +@deftypefun int obstack_room (struct obstack *@var{obstack-ptr}) +This returns the number of bytes that can be added safely to the current +growing object (or to an object about to be started) in obstack +@var{obstack} using the fast growth functions. +@end deftypefun + +While you know there is room, you can use these fast growth functions +for adding data to a growing object: + +@comment obstack.h +@comment GNU +@deftypefun void obstack_1grow_fast (struct obstack *@var{obstack-ptr}, char @var{c}) +The function @code{obstack_1grow_fast} adds one byte containing the +character @var{c} to the growing object in obstack @var{obstack-ptr}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_ptr_grow_fast (struct obstack *@var{obstack-ptr}, void *@var{data}) +The function @code{obstack_ptr_grow_fast} adds @code{sizeof (void *)} +bytes containing the value of @var{data} to the growing object in +obstack @var{obstack-ptr}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_int_grow_fast (struct obstack *@var{obstack-ptr}, int @var{data}) +The function @code{obstack_int_grow_fast} adds @code{sizeof (int)} bytes +containing the value of @var{data} to the growing object in obstack +@var{obstack-ptr}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun void obstack_blank_fast (struct obstack *@var{obstack-ptr}, int @var{size}) +The function @code{obstack_blank_fast} adds @var{size} bytes to the +growing object in obstack @var{obstack-ptr} without initializing them. +@end deftypefun + +When you check for space using @code{obstack_room} and there is not +enough room for what you want to add, the fast growth functions +are not safe. In this case, simply use the corresponding ordinary +growth function instead. Very soon this will copy the object to a +new chunk; then there will be lots of room available again. + +So, each time you use an ordinary growth function, check afterward for +sufficient space using @code{obstack_room}. Once the object is copied +to a new chunk, there will be plenty of space again, so the program will +start using the fast growth functions again. + +Here is an example: + +@smallexample +@group +void +add_string (struct obstack *obstack, const char *ptr, int len) +@{ + while (len > 0) + @{ + int room = obstack_room (obstack); + if (room == 0) + @{ + /* @r{Not enough room. Add one character slowly,} + @r{which may copy to a new chunk and make room.} */ + obstack_1grow (obstack, *ptr++); + len--; + @} + else + @{ + if (room > len) + room = len; + /* @r{Add fast as much as we have room for.} */ + len -= room; + while (room-- > 0) + obstack_1grow_fast (obstack, *ptr++); + @} + @} +@} +@end group +@end smallexample + +@node Status of an Obstack +@section Status of an Obstack +@cindex obstack status +@cindex status of obstack + +Here are functions that provide information on the current status of +allocation in an obstack. You can use them to learn about an object while +still growing it. + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_base (struct obstack *@var{obstack-ptr}) +This function returns the tentative address of the beginning of the +currently growing object in @var{obstack-ptr}. If you finish the object +immediately, it will have that address. If you make it larger first, it +may outgrow the current chunk---then its address will change! + +If no object is growing, this value says where the next object you +allocate will start (once again assuming it fits in the current +chunk). +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun {void *} obstack_next_free (struct obstack *@var{obstack-ptr}) +This function returns the address of the first free byte in the current +chunk of obstack @var{obstack-ptr}. This is the end of the currently +growing object. If no object is growing, @code{obstack_next_free} +returns the same value as @code{obstack_base}. +@end deftypefun + +@comment obstack.h +@comment GNU +@deftypefun int obstack_object_size (struct obstack *@var{obstack-ptr}) +This function returns the size in bytes of the currently growing object. +This is equivalent to + +@smallexample +obstack_next_free (@var{obstack-ptr}) - obstack_base (@var{obstack-ptr}) +@end smallexample +@end deftypefun + +@node Obstacks Data Alignment +@section Alignment of Data in Obstacks +@cindex alignment (in obstacks) + +Each obstack has an @dfn{alignment boundary}; each object allocated in +the obstack automatically starts on an address that is a multiple of the +specified boundary. By default, this boundary is 4 bytes. + +To access an obstack's alignment boundary, use the macro +@code{obstack_alignment_mask}, whose function prototype looks like +this: + +@comment obstack.h +@comment GNU +@deftypefn Macro int obstack_alignment_mask (struct obstack *@var{obstack-ptr}) +The value is a bit mask; a bit that is 1 indicates that the corresponding +bit in the address of an object should be 0. The mask value should be one +less than a power of 2; the effect is that all object addresses are +multiples of that power of 2. The default value of the mask is 3, so that +addresses are multiples of 4. A mask value of 0 means an object can start +on any multiple of 1 (that is, no alignment is required). + +The expansion of the macro @code{obstack_alignment_mask} is an lvalue, +so you can alter the mask by assignment. For example, this statement: + +@smallexample +obstack_alignment_mask (obstack_ptr) = 0; +@end smallexample + +@noindent +has the effect of turning off alignment processing in the specified obstack. +@end deftypefn + +Note that a change in alignment mask does not take effect until +@emph{after} the next time an object is allocated or finished in the +obstack. If you are not growing an object, you can make the new +alignment mask take effect immediately by calling @code{obstack_finish}. +This will finish a zero-length object and then do proper alignment for +the next object. + +@node Obstack Chunks +@section Obstack Chunks +@cindex efficiency of chunks +@cindex chunks + +Obstacks work by allocating space for themselves in large chunks, and +then parceling out space in the chunks to satisfy your requests. Chunks +are normally 4096 bytes long unless you specify a different chunk size. +The chunk size includes 8 bytes of overhead that are not actually used +for storing objects. Regardless of the specified size, longer chunks +will be allocated when necessary for long objects. + +The obstack library allocates chunks by calling the function +@code{obstack_chunk_alloc}, which you must define. When a chunk is no +longer needed because you have freed all the objects in it, the obstack +library frees the chunk by calling @code{obstack_chunk_free}, which you +must also define. + +These two must be defined (as macros) or declared (as functions) in each +source file that uses @code{obstack_init} (@pxref{Creating Obstacks}). +Most often they are defined as macros like this: + +@smallexample +#define obstack_chunk_alloc malloc +#define obstack_chunk_free free +@end smallexample + +Note that these are simple macros (no arguments). Macro definitions with +arguments will not work! It is necessary that @code{obstack_chunk_alloc} +or @code{obstack_chunk_free}, alone, expand into a function name if it is +not itself a function name. + +If you allocate chunks with @code{malloc}, the chunk size should be a +power of 2. The default chunk size, 4096, was chosen because it is long +enough to satisfy many typical requests on the obstack yet short enough +not to waste too much memory in the portion of the last chunk not yet used. + +@comment obstack.h +@comment GNU +@deftypefn Macro int obstack_chunk_size (struct obstack *@var{obstack-ptr}) +This returns the chunk size of the given obstack. +@end deftypefn + +Since this macro expands to an lvalue, you can specify a new chunk size by +assigning it a new value. Doing so does not affect the chunks already +allocated, but will change the size of chunks allocated for that particular +obstack in the future. It is unlikely to be useful to make the chunk size +smaller, but making it larger might improve efficiency if you are +allocating many objects whose size is comparable to the chunk size. Here +is how to do so cleanly: + +@smallexample +if (obstack_chunk_size (obstack_ptr) < @var{new-chunk-size}) + obstack_chunk_size (obstack_ptr) = @var{new-chunk-size}; +@end smallexample + +@node Summary of Obstacks +@section Summary of Obstack Functions + +Here is a summary of all the functions associated with obstacks. Each +takes the address of an obstack (@code{struct obstack *}) as its first +argument. + +@table @code +@item void obstack_init (struct obstack *@var{obstack-ptr}) +Initialize use of an obstack. @xref{Creating Obstacks}. + +@item void *obstack_alloc (struct obstack *@var{obstack-ptr}, int @var{size}) +Allocate an object of @var{size} uninitialized bytes. +@xref{Allocation in an Obstack}. + +@item void *obstack_copy (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +Allocate an object of @var{size} bytes, with contents copied from +@var{address}. @xref{Allocation in an Obstack}. + +@item void *obstack_copy0 (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +Allocate an object of @var{size}+1 bytes, with @var{size} of them copied +from @var{address}, followed by a null character at the end. +@xref{Allocation in an Obstack}. + +@item void obstack_free (struct obstack *@var{obstack-ptr}, void *@var{object}) +Free @var{object} (and everything allocated in the specified obstack +more recently than @var{object}). @xref{Freeing Obstack Objects}. + +@item void obstack_blank (struct obstack *@var{obstack-ptr}, int @var{size}) +Add @var{size} uninitialized bytes to a growing object. +@xref{Growing Objects}. + +@item void obstack_grow (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +Add @var{size} bytes, copied from @var{address}, to a growing object. +@xref{Growing Objects}. + +@item void obstack_grow0 (struct obstack *@var{obstack-ptr}, void *@var{address}, int @var{size}) +Add @var{size} bytes, copied from @var{address}, to a growing object, +and then add another byte containing a null character. @xref{Growing +Objects}. + +@item void obstack_1grow (struct obstack *@var{obstack-ptr}, char @var{data-char}) +Add one byte containing @var{data-char} to a growing object. +@xref{Growing Objects}. + +@item void *obstack_finish (struct obstack *@var{obstack-ptr}) +Finalize the object that is growing and return its permanent address. +@xref{Growing Objects}. + +@item int obstack_object_size (struct obstack *@var{obstack-ptr}) +Get the current size of the currently growing object. @xref{Growing +Objects}. + +@item void obstack_blank_fast (struct obstack *@var{obstack-ptr}, int @var{size}) +Add @var{size} uninitialized bytes to a growing object without checking +that there is enough room. @xref{Extra Fast Growing}. + +@item void obstack_1grow_fast (struct obstack *@var{obstack-ptr}, char @var{data-char}) +Add one byte containing @var{data-char} to a growing object without +checking that there is enough room. @xref{Extra Fast Growing}. + +@item int obstack_room (struct obstack *@var{obstack-ptr}) +Get the amount of room now available for growing the current object. +@xref{Extra Fast Growing}. + +@item int obstack_alignment_mask (struct obstack *@var{obstack-ptr}) +The mask used for aligning the beginning of an object. This is an +lvalue. @xref{Obstacks Data Alignment}. + +@item int obstack_chunk_size (struct obstack *@var{obstack-ptr}) +The size for allocating chunks. This is an lvalue. @xref{Obstack Chunks}. + +@item void *obstack_base (struct obstack *@var{obstack-ptr}) +Tentative starting address of the currently growing object. +@xref{Status of an Obstack}. + +@item void *obstack_next_free (struct obstack *@var{obstack-ptr}) +Address just after the end of the currently growing object. +@xref{Status of an Obstack}. +@end table + diff --git a/external/gpl3/gdb/dist/libiberty/partition.c b/external/gpl3/gdb/dist/libiberty/partition.c new file mode 100644 index 000000000000..5f0745c91424 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/partition.c @@ -0,0 +1,183 @@ +/* List implementation of a partition of consecutive integers. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#include "libiberty.h" +#include "partition.h" + +static int elem_compare (const void *, const void *); + +/* Creates a partition of NUM_ELEMENTS elements. Initially each + element is in a class by itself. */ + +partition +partition_new (int num_elements) +{ + int e; + + partition part = (partition) + xmalloc (sizeof (struct partition_def) + + (num_elements - 1) * sizeof (struct partition_elem)); + part->num_elements = num_elements; + for (e = 0; e < num_elements; ++e) + { + part->elements[e].class_element = e; + part->elements[e].next = &(part->elements[e]); + part->elements[e].class_count = 1; + } + + return part; +} + +/* Freeds a partition. */ + +void +partition_delete (partition part) +{ + free (part); +} + +/* Unites the classes containing ELEM1 and ELEM2 into a single class + of partition PART. If ELEM1 and ELEM2 are already in the same + class, does nothing. Returns the canonical element of the + resulting union class. */ + +int +partition_union (partition part, int elem1, int elem2) +{ + struct partition_elem *elements = part->elements; + struct partition_elem *e1; + struct partition_elem *e2; + struct partition_elem *p; + struct partition_elem *old_next; + /* The canonical element of the resulting union class. */ + int class_element = elements[elem1].class_element; + + /* If they're already in the same class, do nothing. */ + if (class_element == elements[elem2].class_element) + return class_element; + + /* Make sure ELEM1 is in the larger class of the two. If not, swap + them. This way we always scan the shorter list. */ + if (elements[elem1].class_count < elements[elem2].class_count) + { + int temp = elem1; + elem1 = elem2; + elem2 = temp; + class_element = elements[elem1].class_element; + } + + e1 = &(elements[elem1]); + e2 = &(elements[elem2]); + + /* Keep a count of the number of elements in the list. */ + elements[class_element].class_count + += elements[e2->class_element].class_count; + + /* Update the class fields in elem2's class list. */ + e2->class_element = class_element; + for (p = e2->next; p != e2; p = p->next) + p->class_element = class_element; + + /* Splice ELEM2's class list into ELEM1's. These are circular + lists. */ + old_next = e1->next; + e1->next = e2->next; + e2->next = old_next; + + return class_element; +} + +/* Compare elements ELEM1 and ELEM2 from array of integers, given a + pointer to each. Used to qsort such an array. */ + +static int +elem_compare (const void *elem1, const void *elem2) +{ + int e1 = * (const int *) elem1; + int e2 = * (const int *) elem2; + if (e1 < e2) + return -1; + else if (e1 > e2) + return 1; + else + return 0; +} + +/* Prints PART to the file pointer FP. The elements of each + class are sorted. */ + +void +partition_print (partition part, FILE *fp) +{ + char *done; + int num_elements = part->num_elements; + struct partition_elem *elements = part->elements; + int *class_elements; + int e; + + /* Flag the elements we've already printed. */ + done = (char *) xmalloc (num_elements); + memset (done, 0, num_elements); + + /* A buffer used to sort elements in a class. */ + class_elements = (int *) xmalloc (num_elements * sizeof (int)); + + fputc ('[', fp); + for (e = 0; e < num_elements; ++e) + /* If we haven't printed this element, print its entire class. */ + if (! done[e]) + { + int c = e; + int count = elements[elements[e].class_element].class_count; + int i; + + /* Collect the elements in this class. */ + for (i = 0; i < count; ++i) { + class_elements[i] = c; + done[c] = 1; + c = elements[c].next - elements; + } + /* Sort them. */ + qsort ((void *) class_elements, count, sizeof (int), elem_compare); + /* Print them. */ + fputc ('(', fp); + for (i = 0; i < count; ++i) + fprintf (fp, i == 0 ? "%d" : " %d", class_elements[i]); + fputc (')', fp); + } + fputc (']', fp); + + free (class_elements); + free (done); +} + diff --git a/external/gpl3/gdb/dist/libiberty/pex-common.c b/external/gpl3/gdb/dist/libiberty/pex-common.c new file mode 100644 index 000000000000..55b63ae33fe9 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-common.c @@ -0,0 +1,649 @@ +/* Common code for executing a program in a sub-process. + Copyright (C) 2005, 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif + +extern int mkstemps (char *, int); + +/* This file contains subroutines for the program execution routines + (pex_init, pex_run, etc.). This file is compiled on all + systems. */ + +static void pex_add_remove (struct pex_obj *, const char *, int); +static int pex_get_status_and_time (struct pex_obj *, int, const char **, + int *); + +/* Initialize a pex_obj structure. */ + +struct pex_obj * +pex_init_common (int flags, const char *pname, const char *tempbase, + const struct pex_funcs *funcs) +{ + struct pex_obj *obj; + + obj = XNEW (struct pex_obj); + obj->flags = flags; + obj->pname = pname; + obj->tempbase = tempbase; + obj->next_input = STDIN_FILE_NO; + obj->next_input_name = NULL; + obj->next_input_name_allocated = 0; + obj->stderr_pipe = -1; + obj->count = 0; + obj->children = NULL; + obj->status = NULL; + obj->time = NULL; + obj->number_waited = 0; + obj->input_file = NULL; + obj->read_output = NULL; + obj->read_err = NULL; + obj->remove_count = 0; + obj->remove = NULL; + obj->funcs = funcs; + obj->sysdep = NULL; + return obj; +} + +/* Add a file to be removed when we are done. */ + +static void +pex_add_remove (struct pex_obj *obj, const char *name, int allocated) +{ + char *add; + + ++obj->remove_count; + obj->remove = XRESIZEVEC (char *, obj->remove, obj->remove_count); + if (allocated) + add = (char *) name; + else + add = xstrdup (name); + obj->remove[obj->remove_count - 1] = add; +} + +/* Generate a temporary file name based on OBJ, FLAGS, and NAME. + Return NULL if we were unable to reserve a temporary filename. + + If non-NULL, the result is either allocated with malloc, or the + same pointer as NAME. */ +static char * +temp_file (struct pex_obj *obj, int flags, char *name) +{ + if (name == NULL) + { + if (obj->tempbase == NULL) + { + name = make_temp_file (NULL); + } + else + { + int len = strlen (obj->tempbase); + int out; + + if (len >= 6 + && strcmp (obj->tempbase + len - 6, "XXXXXX") == 0) + name = xstrdup (obj->tempbase); + else + name = concat (obj->tempbase, "XXXXXX", NULL); + + out = mkstemps (name, 0); + if (out < 0) + { + free (name); + return NULL; + } + + /* This isn't obj->funcs->close because we got the + descriptor from mkstemps, not from a function in + obj->funcs. Calling close here is just like what + make_temp_file does. */ + close (out); + } + } + else if ((flags & PEX_SUFFIX) != 0) + { + if (obj->tempbase == NULL) + name = make_temp_file (name); + else + name = concat (obj->tempbase, name, NULL); + } + + return name; +} + + +/* As for pex_run (), but permits the environment for the child process + to be specified. */ + +const char * +pex_run_in_environment (struct pex_obj *obj, int flags, const char *executable, + char * const * argv, char * const * env, + const char *orig_outname, const char *errname, + int *err) +{ + const char *errmsg; + int in, out, errdes; + char *outname; + int outname_allocated; + int p[2]; + int toclose; + pid_t pid; + + in = -1; + out = -1; + errdes = -1; + outname = (char *) orig_outname; + outname_allocated = 0; + + /* If the user called pex_input_file, close the file now. */ + if (obj->input_file) + { + if (fclose (obj->input_file) == EOF) + { + errmsg = "closing pipeline input file"; + goto error_exit; + } + obj->input_file = NULL; + } + + /* Set IN. */ + + if (obj->next_input_name != NULL) + { + /* We have to make sure that the previous process has completed + before we try to read the file. */ + if (!pex_get_status_and_time (obj, 0, &errmsg, err)) + goto error_exit; + + in = obj->funcs->open_read (obj, obj->next_input_name, + (flags & PEX_BINARY_INPUT) != 0); + if (in < 0) + { + *err = errno; + errmsg = "open temporary file"; + goto error_exit; + } + if (obj->next_input_name_allocated) + { + free (obj->next_input_name); + obj->next_input_name_allocated = 0; + } + obj->next_input_name = NULL; + } + else + { + in = obj->next_input; + if (in < 0) + { + *err = 0; + errmsg = "pipeline already complete"; + goto error_exit; + } + } + + /* Set OUT and OBJ->NEXT_INPUT/OBJ->NEXT_INPUT_NAME. */ + + if ((flags & PEX_LAST) != 0) + { + if (outname == NULL) + out = STDOUT_FILE_NO; + else if ((flags & PEX_SUFFIX) != 0) + { + outname = concat (obj->tempbase, outname, NULL); + outname_allocated = 1; + } + obj->next_input = -1; + } + else if ((obj->flags & PEX_USE_PIPES) == 0) + { + outname = temp_file (obj, flags, outname); + if (! outname) + { + *err = 0; + errmsg = "could not create temporary file"; + goto error_exit; + } + + if (outname != orig_outname) + outname_allocated = 1; + + if ((obj->flags & PEX_SAVE_TEMPS) == 0) + { + pex_add_remove (obj, outname, outname_allocated); + outname_allocated = 0; + } + + /* Hand off ownership of outname to the next stage. */ + obj->next_input_name = outname; + obj->next_input_name_allocated = outname_allocated; + outname_allocated = 0; + } + else + { + if (obj->funcs->pipe (obj, p, (flags & PEX_BINARY_OUTPUT) != 0) < 0) + { + *err = errno; + errmsg = "pipe"; + goto error_exit; + } + + out = p[WRITE_PORT]; + obj->next_input = p[READ_PORT]; + } + + if (out < 0) + { + out = obj->funcs->open_write (obj, outname, + (flags & PEX_BINARY_OUTPUT) != 0); + if (out < 0) + { + *err = errno; + errmsg = "open temporary output file"; + goto error_exit; + } + } + + if (outname_allocated) + { + free (outname); + outname_allocated = 0; + } + + /* Set ERRDES. */ + + if (errname != NULL && (flags & PEX_STDERR_TO_PIPE) != 0) + { + *err = 0; + errmsg = "both ERRNAME and PEX_STDERR_TO_PIPE specified."; + goto error_exit; + } + + if (obj->stderr_pipe != -1) + { + *err = 0; + errmsg = "PEX_STDERR_TO_PIPE used in the middle of pipeline"; + goto error_exit; + } + + if (errname == NULL) + { + if (flags & PEX_STDERR_TO_PIPE) + { + if (obj->funcs->pipe (obj, p, (flags & PEX_BINARY_ERROR) != 0) < 0) + { + *err = errno; + errmsg = "pipe"; + goto error_exit; + } + + errdes = p[WRITE_PORT]; + obj->stderr_pipe = p[READ_PORT]; + } + else + { + errdes = STDERR_FILE_NO; + } + } + else + { + errdes = obj->funcs->open_write (obj, errname, + (flags & PEX_BINARY_ERROR) != 0); + if (errdes < 0) + { + *err = errno; + errmsg = "open error file"; + goto error_exit; + } + } + + /* If we are using pipes, the child process has to close the next + input pipe. */ + + if ((obj->flags & PEX_USE_PIPES) == 0) + toclose = -1; + else + toclose = obj->next_input; + + /* Run the program. */ + + pid = obj->funcs->exec_child (obj, flags, executable, argv, env, + in, out, errdes, toclose, &errmsg, err); + if (pid < 0) + goto error_exit; + + ++obj->count; + obj->children = XRESIZEVEC (pid_t, obj->children, obj->count); + obj->children[obj->count - 1] = pid; + + return NULL; + + error_exit: + if (in >= 0 && in != STDIN_FILE_NO) + obj->funcs->close (obj, in); + if (out >= 0 && out != STDOUT_FILE_NO) + obj->funcs->close (obj, out); + if (errdes >= 0 && errdes != STDERR_FILE_NO) + obj->funcs->close (obj, errdes); + if (outname_allocated) + free (outname); + return errmsg; +} + +/* Run a program. */ + +const char * +pex_run (struct pex_obj *obj, int flags, const char *executable, + char * const * argv, const char *orig_outname, const char *errname, + int *err) +{ + return pex_run_in_environment (obj, flags, executable, argv, NULL, + orig_outname, errname, err); +} + +/* Return a FILE pointer for a temporary file to fill with input for + the pipeline. */ +FILE * +pex_input_file (struct pex_obj *obj, int flags, const char *in_name) +{ + char *name = (char *) in_name; + FILE *f; + + /* This must be called before the first pipeline stage is run, and + there must not have been any other input selected. */ + if (obj->count != 0 + || (obj->next_input >= 0 && obj->next_input != STDIN_FILE_NO) + || obj->next_input_name) + { + errno = EINVAL; + return NULL; + } + + name = temp_file (obj, flags, name); + if (! name) + return NULL; + + f = fopen (name, (flags & PEX_BINARY_OUTPUT) ? "wb" : "w"); + if (! f) + { + free (name); + return NULL; + } + + obj->input_file = f; + obj->next_input_name = name; + obj->next_input_name_allocated = (name != in_name); + + return f; +} + +/* Return a stream for a pipe connected to the standard input of the + first stage of the pipeline. */ +FILE * +pex_input_pipe (struct pex_obj *obj, int binary) +{ + int p[2]; + FILE *f; + + /* You must call pex_input_pipe before the first pex_run or pex_one. */ + if (obj->count > 0) + goto usage_error; + + /* You must be using pipes. Implementations that don't support + pipes clear this flag before calling pex_init_common. */ + if (! (obj->flags & PEX_USE_PIPES)) + goto usage_error; + + /* If we have somehow already selected other input, that's a + mistake. */ + if ((obj->next_input >= 0 && obj->next_input != STDIN_FILE_NO) + || obj->next_input_name) + goto usage_error; + + if (obj->funcs->pipe (obj, p, binary != 0) < 0) + return NULL; + + f = obj->funcs->fdopenw (obj, p[WRITE_PORT], binary != 0); + if (! f) + { + int saved_errno = errno; + obj->funcs->close (obj, p[READ_PORT]); + obj->funcs->close (obj, p[WRITE_PORT]); + errno = saved_errno; + return NULL; + } + + obj->next_input = p[READ_PORT]; + + return f; + + usage_error: + errno = EINVAL; + return NULL; +} + +/* Return a FILE pointer for the output of the last program + executed. */ + +FILE * +pex_read_output (struct pex_obj *obj, int binary) +{ + if (obj->next_input_name != NULL) + { + const char *errmsg; + int err; + + /* We have to make sure that the process has completed before we + try to read the file. */ + if (!pex_get_status_and_time (obj, 0, &errmsg, &err)) + { + errno = err; + return NULL; + } + + obj->read_output = fopen (obj->next_input_name, binary ? "rb" : "r"); + + if (obj->next_input_name_allocated) + { + free (obj->next_input_name); + obj->next_input_name_allocated = 0; + } + obj->next_input_name = NULL; + } + else + { + int o; + + o = obj->next_input; + if (o < 0 || o == STDIN_FILE_NO) + return NULL; + obj->read_output = obj->funcs->fdopenr (obj, o, binary); + obj->next_input = -1; + } + + return obj->read_output; +} + +FILE * +pex_read_err (struct pex_obj *obj, int binary) +{ + int o; + + o = obj->stderr_pipe; + if (o < 0 || o == STDIN_FILE_NO) + return NULL; + obj->read_err = obj->funcs->fdopenr (obj, o, binary); + obj->stderr_pipe = -1; + return obj->read_err; +} + +/* Get the exit status and, if requested, the resource time for all + the child processes. Return 0 on failure, 1 on success. */ + +static int +pex_get_status_and_time (struct pex_obj *obj, int done, const char **errmsg, + int *err) +{ + int ret; + int i; + + if (obj->number_waited == obj->count) + return 1; + + obj->status = XRESIZEVEC (int, obj->status, obj->count); + if ((obj->flags & PEX_RECORD_TIMES) != 0) + obj->time = XRESIZEVEC (struct pex_time, obj->time, obj->count); + + ret = 1; + for (i = obj->number_waited; i < obj->count; ++i) + { + if (obj->funcs->wait (obj, obj->children[i], &obj->status[i], + obj->time == NULL ? NULL : &obj->time[i], + done, errmsg, err) < 0) + ret = 0; + } + obj->number_waited = i; + + return ret; +} + +/* Get exit status of executed programs. */ + +int +pex_get_status (struct pex_obj *obj, int count, int *vector) +{ + if (obj->status == NULL) + { + const char *errmsg; + int err; + + if (!pex_get_status_and_time (obj, 0, &errmsg, &err)) + return 0; + } + + if (count > obj->count) + { + memset (vector + obj->count, 0, (count - obj->count) * sizeof (int)); + count = obj->count; + } + + memcpy (vector, obj->status, count * sizeof (int)); + + return 1; +} + +/* Get process times of executed programs. */ + +int +pex_get_times (struct pex_obj *obj, int count, struct pex_time *vector) +{ + if (obj->status == NULL) + { + const char *errmsg; + int err; + + if (!pex_get_status_and_time (obj, 0, &errmsg, &err)) + return 0; + } + + if (obj->time == NULL) + return 0; + + if (count > obj->count) + { + memset (vector + obj->count, 0, + (count - obj->count) * sizeof (struct pex_time)); + count = obj->count; + } + + memcpy (vector, obj->time, count * sizeof (struct pex_time)); + + return 1; +} + +/* Free a pex_obj structure. */ + +void +pex_free (struct pex_obj *obj) +{ + /* Close pipe file descriptors corresponding to child's stdout and + stderr so that the child does not hang trying to output something + while we're waiting for it. */ + if (obj->next_input >= 0 && obj->next_input != STDIN_FILE_NO) + obj->funcs->close (obj, obj->next_input); + if (obj->stderr_pipe >= 0 && obj->stderr_pipe != STDIN_FILE_NO) + obj->funcs->close (obj, obj->stderr_pipe); + if (obj->read_output != NULL) + fclose (obj->read_output); + if (obj->read_err != NULL) + fclose (obj->read_err); + + /* If the caller forgot to wait for the children, we do it here, to + avoid zombies. */ + if (obj->status == NULL) + { + const char *errmsg; + int err; + + obj->flags &= ~ PEX_RECORD_TIMES; + pex_get_status_and_time (obj, 1, &errmsg, &err); + } + + if (obj->next_input_name_allocated) + free (obj->next_input_name); + if (obj->children != NULL) + free (obj->children); + if (obj->status != NULL) + free (obj->status); + if (obj->time != NULL) + free (obj->time); + + if (obj->remove_count > 0) + { + int i; + + for (i = 0; i < obj->remove_count; ++i) + { + remove (obj->remove[i]); + free (obj->remove[i]); + } + free (obj->remove); + } + + if (obj->funcs->cleanup != NULL) + obj->funcs->cleanup (obj); + + free (obj); +} diff --git a/external/gpl3/gdb/dist/libiberty/pex-common.h b/external/gpl3/gdb/dist/libiberty/pex-common.h new file mode 100644 index 000000000000..af338e6a34b0 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-common.h @@ -0,0 +1,153 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Shared logic. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifndef PEX_COMMON_H +#define PEX_COMMON_H + +#include "config.h" +#include "libiberty.h" +#include + +/* pid_t is may defined by config.h or sys/types.h needs to be + included. */ +#if !defined(pid_t) && defined(HAVE_SYS_TYPES_H) +#include +#endif + +#define install_error_msg "installation problem, cannot exec `%s'" + +/* stdin file number. */ +#define STDIN_FILE_NO 0 + +/* stdout file number. */ +#define STDOUT_FILE_NO 1 + +/* stderr file number. */ +#define STDERR_FILE_NO 2 + +/* value of `pipe': port index for reading. */ +#define READ_PORT 0 + +/* value of `pipe': port index for writing. */ +#define WRITE_PORT 1 + +/* The structure used by pex_init and friends. */ + +struct pex_obj +{ + /* Flags. */ + int flags; + /* Name of calling program, for error messages. */ + const char *pname; + /* Base name to use for temporary files. */ + const char *tempbase; + /* Pipe to use as stdin for next process. */ + int next_input; + /* File name to use as stdin for next process. */ + char *next_input_name; + /* Whether next_input_name was allocated using malloc. */ + int next_input_name_allocated; + /* If not -1, stderr pipe from the last process. */ + int stderr_pipe; + /* Number of child processes. */ + int count; + /* PIDs of child processes; array allocated using malloc. */ + pid_t *children; + /* Exit statuses of child processes; array allocated using malloc. */ + int *status; + /* Time used by child processes; array allocated using malloc. */ + struct pex_time *time; + /* Number of children we have already waited for. */ + int number_waited; + /* FILE created by pex_input_file. */ + FILE *input_file; + /* FILE created by pex_read_output. */ + FILE *read_output; + /* FILE created by pex_read_err. */ + FILE *read_err; + /* Number of temporary files to remove. */ + int remove_count; + /* List of temporary files to remove; array allocated using malloc + of strings allocated using malloc. */ + char **remove; + /* Pointers to system dependent functions. */ + const struct pex_funcs *funcs; + /* For use by system dependent code. */ + void *sysdep; +}; + +/* Functions passed to pex_run_common. */ + +struct pex_funcs +{ + /* Open file NAME for reading. If BINARY is non-zero, open in + binary mode. Return >= 0 on success, -1 on error. */ + int (*open_read) (struct pex_obj *, const char */* name */, int /* binary */); + /* Open file NAME for writing. If BINARY is non-zero, open in + binary mode. Return >= 0 on success, -1 on error. */ + int (*open_write) (struct pex_obj *, const char */* name */, + int /* binary */); + /* Execute a child process. FLAGS, EXECUTABLE, ARGV, ERR are from + pex_run. IN, OUT, ERRDES, TOCLOSE are all descriptors, from + open_read, open_write, or pipe, or they are one of STDIN_FILE_NO, + STDOUT_FILE_NO or STDERR_FILE_NO; if IN, OUT, and ERRDES are not + STD*_FILE_NO, they should be closed. If the descriptor TOCLOSE + is not -1, and the system supports pipes, TOCLOSE should be + closed in the child process. The function should handle the + PEX_STDERR_TO_STDOUT flag. Return >= 0 on success, or -1 on + error and set *ERRMSG and *ERR. */ + pid_t (*exec_child) (struct pex_obj *, int /* flags */, + const char */* executable */, char * const * /* argv */, + char * const * /* env */, + int /* in */, int /* out */, int /* errdes */, + int /* toclose */, const char **/* errmsg */, + int */* err */); + /* Close a descriptor. Return 0 on success, -1 on error. */ + int (*close) (struct pex_obj *, int); + /* Wait for a child to complete, returning exit status in *STATUS + and time in *TIME (if it is not null). CHILD is from fork. DONE + is 1 if this is called via pex_free. ERRMSG and ERR are as in + fork. Return 0 on success, -1 on error. */ + pid_t (*wait) (struct pex_obj *, pid_t /* child */, int * /* status */, + struct pex_time * /* time */, int /* done */, + const char ** /* errmsg */, int * /* err */); + /* Create a pipe (only called if PEX_USE_PIPES is set) storing two + descriptors in P[0] and P[1]. If BINARY is non-zero, open in + binary mode. Return 0 on success, -1 on error. */ + int (*pipe) (struct pex_obj *, int * /* p */, int /* binary */); + /* Get a FILE pointer to read from a file descriptor (only called if + PEX_USE_PIPES is set). If BINARY is non-zero, open in binary + mode. Return pointer on success, NULL on error. */ + FILE * (*fdopenr) (struct pex_obj *, int /* fd */, int /* binary */); + /* Get a FILE pointer to write to the file descriptor FD (only + called if PEX_USE_PIPES is set). If BINARY is non-zero, open in + binary mode. Arrange for FD not to be inherited by the child + processes. Return pointer on success, NULL on error. */ + FILE * (*fdopenw) (struct pex_obj *, int /* fd */, int /* binary */); + /* Free any system dependent data associated with OBJ. May be + NULL if there is nothing to do. */ + void (*cleanup) (struct pex_obj *); +}; + +extern struct pex_obj *pex_init_common (int, const char *, const char *, + const struct pex_funcs *); + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/pex-djgpp.c b/external/gpl3/gdb/dist/libiberty/pex-djgpp.c new file mode 100644 index 000000000000..0721139954ff --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-djgpp.c @@ -0,0 +1,294 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. DJGPP specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#include +#include +#include +#include +#include + +/* Use ECHILD if available, otherwise use EINVAL. */ +#ifdef ECHILD +#define PWAIT_ERROR ECHILD +#else +#define PWAIT_ERROR EINVAL +#endif + +static int pex_djgpp_open_read (struct pex_obj *, const char *, int); +static int pex_djgpp_open_write (struct pex_obj *, const char *, int); +static pid_t pex_djgpp_exec_child (struct pex_obj *, int, const char *, + char * const *, char * const *, + int, int, int, int, + const char **, int *); +static int pex_djgpp_close (struct pex_obj *, int); +static pid_t pex_djgpp_wait (struct pex_obj *, pid_t, int *, struct pex_time *, + int, const char **, int *); + +/* The list of functions we pass to the common routines. */ + +const struct pex_funcs funcs = +{ + pex_djgpp_open_read, + pex_djgpp_open_write, + pex_djgpp_exec_child, + pex_djgpp_close, + pex_djgpp_wait, + NULL, /* pipe */ + NULL, /* fdopenr */ + NULL, /* fdopenw */ + NULL /* cleanup */ +}; + +/* Return a newly initialized pex_obj structure. */ + +struct pex_obj * +pex_init (int flags, const char *pname, const char *tempbase) +{ + /* DJGPP does not support pipes. */ + flags &= ~ PEX_USE_PIPES; + return pex_init_common (flags, pname, tempbase, &funcs); +} + +/* Open a file for reading. */ + +static int +pex_djgpp_open_read (struct pex_obj *obj ATTRIBUTE_UNUSED, + const char *name, int binary) +{ + return open (name, O_RDONLY | (binary ? O_BINARY : O_TEXT)); +} + +/* Open a file for writing. */ + +static int +pex_djgpp_open_write (struct pex_obj *obj ATTRIBUTE_UNUSED, + const char *name, int binary) +{ + /* Note that we can't use O_EXCL here because gcc may have already + created the temporary file via make_temp_file. */ + return open (name, + (O_WRONLY | O_CREAT | O_TRUNC + | (binary ? O_BINARY : O_TEXT)), + S_IRUSR | S_IWUSR); +} + +/* Close a file. */ + +static int +pex_djgpp_close (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd) +{ + return close (fd); +} + +/* Execute a child. */ + +static pid_t +pex_djgpp_exec_child (struct pex_obj *obj, int flags, const char *executable, + char * const * argv, char * const * env, + int in, int out, int errdes, + int toclose ATTRIBUTE_UNUSED, const char **errmsg, + int *err) +{ + int org_in, org_out, org_errdes; + int status; + int *statuses; + + org_in = -1; + org_out = -1; + org_errdes = -1; + + if (in != STDIN_FILE_NO) + { + org_in = dup (STDIN_FILE_NO); + if (org_in < 0) + { + *err = errno; + *errmsg = "dup"; + return (pid_t) -1; + } + if (dup2 (in, STDIN_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (close (in) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + if (out != STDOUT_FILE_NO) + { + org_out = dup (STDOUT_FILE_NO); + if (org_out < 0) + { + *err = errno; + *errmsg = "dup"; + return (pid_t) -1; + } + if (dup2 (out, STDOUT_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (close (out) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + if (errdes != STDERR_FILE_NO + || (flags & PEX_STDERR_TO_STDOUT) != 0) + { + org_errdes = dup (STDERR_FILE_NO); + if (org_errdes < 0) + { + *err = errno; + *errmsg = "dup"; + return (pid_t) -1; + } + if (dup2 ((flags & PEX_STDERR_TO_STDOUT) != 0 ? STDOUT_FILE_NO : errdes, + STDERR_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (errdes != STDERR_FILE_NO) + { + if (close (errdes) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + } + + if (env) + status = (((flags & PEX_SEARCH) != 0 ? spawnvpe : spawnve) + (P_WAIT, executable, argv, env)); + else + status = (((flags & PEX_SEARCH) != 0 ? spawnvp : spawnv) + (P_WAIT, executable, argv)); + + if (status == -1) + { + *err = errno; + *errmsg = ((flags & PEX_SEARCH) != 0) ? "spawnvp" : "spawnv"; + } + + if (in != STDIN_FILE_NO) + { + if (dup2 (org_in, STDIN_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (close (org_in) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + if (out != STDOUT_FILE_NO) + { + if (dup2 (org_out, STDOUT_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (close (org_out) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + if (errdes != STDERR_FILE_NO + || (flags & PEX_STDERR_TO_STDOUT) != 0) + { + if (dup2 (org_errdes, STDERR_FILE_NO) < 0) + { + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; + } + if (close (org_errdes) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + /* Save the exit status for later. When we are called, obj->count + is the number of children which have executed before this + one. */ + statuses = (int *) obj->sysdep; + statuses = XRESIZEVEC (int, statuses, obj->count + 1); + statuses[obj->count] = status; + obj->sysdep = (void *) statuses; + + return (pid_t) obj->count; +} + +/* Wait for a child process to complete. Actually the child process + has already completed, and we just need to return the exit + status. */ + +static pid_t +pex_djgpp_wait (struct pex_obj *obj, pid_t pid, int *status, + struct pex_time *time, int done ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + int *statuses; + + if (time != NULL) + memset (time, 0, sizeof *time); + + statuses = (int *) obj->sysdep; + *status = statuses[pid]; + + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/pex-msdos.c b/external/gpl3/gdb/dist/libiberty/pex-msdos.c new file mode 100644 index 000000000000..4b77bf655fb5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-msdos.c @@ -0,0 +1,319 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic MSDOS specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "pex-common.h" + +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "safe-ctype.h" +#include + +/* The structure we keep in obj->sysdep. */ + +#define PEX_MSDOS_FILE_COUNT 3 + +#define PEX_MSDOS_FD_OFFSET 10 + +struct pex_msdos +{ + /* An array of file names. We refer to these using file descriptors + of 10 + array index. */ + const char *files[PEX_MSDOS_FILE_COUNT]; + /* Exit statuses of programs which have been run. */ + int *statuses; +}; + +static int pex_msdos_open (struct pex_obj *, const char *, int); +static int pex_msdos_open (struct pex_obj *, const char *, int); +static int pex_msdos_fdindex (struct pex_msdos *, int); +static pid_t pex_msdos_exec_child (struct pex_obj *, int, const char *, + char * const *, char * const *, + int, int, int, int, + int, const char **, int *); +static int pex_msdos_close (struct pex_obj *, int); +static pid_t pex_msdos_wait (struct pex_obj *, pid_t, int *, struct pex_time *, + int, const char **, int *); +static void pex_msdos_cleanup (struct pex_obj *); + +/* The list of functions we pass to the common routines. */ + +const struct pex_funcs funcs = +{ + pex_msdos_open, + pex_msdos_open, + pex_msdos_exec_child, + pex_msdos_close, + pex_msdos_wait, + NULL, /* pipe */ + NULL, /* fdopenr */ + NULL, /* fdopenw */ + pex_msdos_cleanup +}; + +/* Return a newly initialized pex_obj structure. */ + +struct pex_obj * +pex_init (int flags, const char *pname, const char *tempbase) +{ + struct pex_obj *ret; + int i; + + /* MSDOS does not support pipes. */ + flags &= ~ PEX_USE_PIPES; + + ret = pex_init_common (flags, pname, tempbase, funcs); + + ret->sysdep = XNEW (struct pex_msdos); + for (i = 0; i < PEX_MSDOS_FILE_COUNT; ++i) + ret->files[i] = NULL; + ret->statuses = NULL; + + return ret; +} + +/* Open a file. FIXME: We ignore the binary argument, since we have + no way to handle it. */ + +static int +pex_msdos_open (struct pex_obj *obj, const char *name, + int binary ATTRIBUTE_UNUSED) +{ + struct pex_msdos *ms; + int i; + + ms = (struct pex_msdos *) obj->sysdep; + + for (i = 0; i < PEX_MSDOS_FILE_COUNT; ++i) + { + if (ms->files[i] == NULL) + { + ms->files[i] = xstrdup (name); + return i + PEX_MSDOS_FD_OFFSET; + } + } + + abort (); +} + +/* Get the index into msdos->files associated with an open file + descriptor. */ + +static int +pex_msdos_fdindex (struct pex_msdos *ms, int fd) +{ + fd -= PEX_MSDOS_FD_OFFSET; + if (fd < 0 || fd >= PEX_MSDOS_FILE_COUNT || ms->files[fd] == NULL) + abort (); + return fd; +} + + +/* Close a file. */ + +static int +pex_msdos_close (struct pex_obj *obj, int fd) +{ + struct pex_msdos *ms; + int fdinex; + + ms = (struct pex_msdos *) obj->sysdep; + fdindex = pe_msdos_fdindex (ms, fd); + free (ms->files[fdindex]); + ms->files[fdindex] = NULL; +} + +/* Execute a child. */ + +static pid_t +pex_msdos_exec_child (struct pex_obj *obj, int flags, const char *executable, + char * const * argv, char * const * env, int in, int out, + int toclose ATTRIBUTE_UNUSED, + int errdes ATTRIBUTE_UNUSED, const char **errmsg, + int *err) +{ + struct pex_msdos *ms; + char *temp_base; + int temp_base_allocated; + char *rf; + int inindex; + char *infile; + int outindex; + char *outfile; + char *scmd; + FILE *argfile; + int i; + int status; + + ms = (struct pex_msdos *) obj->sysdep; + + /* FIXME: I don't know how to redirect stderr, so we ignore ERRDES + and PEX_STDERR_TO_STDOUT. */ + + temp_base = obj->temp_base; + if (temp_base != NULL) + temp_base_allocated = 0; + else + { + temp_base = choose_temp_base (); + temp_base_allocated = 1; + } + + rf = concat (temp_base, ".gp", NULL); + + if (temp_base_allocated) + free (temp_base); + + if (in == STDIN_FILE_NO) + { + inindex = -1; + infile = ""; + } + else + { + inindex = pex_msdos_fdindex (ms, in); + infile = ms->files[inindex]; + } + + if (out == STDOUT_FILE_NO) + { + outindex = -1; + outfile = ""; + } + else + { + outindex = pex_msdos_fdindex (ms, out); + outfile = ms->files[outindex]; + } + + scmd = XNEWVEC (char, strlen (program) + + ((flags & PEXECUTE_SEARCH) != 0 ? 4 : 0) + + strlen (rf) + + strlen (infile) + + strlen (outfile) + + 10); + sprintf (scmd, "%s%s @%s%s%s%s%s", + program, + (flags & PEXECUTE_SEARCH) != 0 ? ".exe" : "", + rf, + inindex != -1 ? " <" : "", + infile, + outindex != -1 ? " >" : "", + outfile); + + argfile = fopen (rf, "w"); + if (argfile == NULL) + { + *err = errno; + free (scmd); + free (rf); + *errmsg = "cannot open temporary command file"; + return (pid_t) -1; + } + + for (i = 1; argv[i] != NULL; ++i) + { + char *p; + + for (p = argv[i]; *p != '\0'; ++p) + { + if (*p == '"' || *p == '\'' || *p == '\\' || ISSPACE (*p)) + putc ('\\', argfile); + putc (*p, argfile); + } + putc ('\n', argfile); + } + + fclose (argfile); + + status = system (scmd); + + if (status == -1) + { + *err = errno; + remove (rf); + free (scmd); + free (rf); + *errmsg = "system"; + return (pid_t) -1; + } + + remove (rf); + free (scmd); + free (rf); + + /* Save the exit status for later. When we are called, obj->count + is the number of children which have executed before this + one. */ + ms->statuses = XRESIZEVEC(int, ms->statuses, obj->count + 1); + ms->statuses[obj->count] = status; + + return (pid_t) obj->count; +} + +/* Wait for a child process to complete. Actually the child process + has already completed, and we just need to return the exit + status. */ + +static pid_t +pex_msdos_wait (struct pex_obj *obj, pid_t pid, int *status, + struct pex_time *time, int done ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct pex_msdos *ms; + + ms = (struct pex_msdos *) obj->sysdep; + + if (time != NULL) + memset (time, 0, sizeof *time); + + *status = ms->statuses[pid]; + + return 0; +} + +/* Clean up the pex_msdos structure. */ + +static void +pex_msdos_cleanup (struct pex_obj *obj) +{ + struct pex_msdos *ms; + int i; + + ms = (struct pex_msdos *) obj->sysdep; + for (i = 0; i < PEX_MSDOS_FILE_COUNT; ++i) + if (msdos->files[i] != NULL) + free (msdos->files[i]); + if (msdos->statuses != NULL) + free (msdos->statuses); + free (msdos); + obj->sysdep = NULL; +} diff --git a/external/gpl3/gdb/dist/libiberty/pex-one.c b/external/gpl3/gdb/dist/libiberty/pex-one.c new file mode 100644 index 000000000000..696b8bcc62a3 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-one.c @@ -0,0 +1,43 @@ +/* Execute a program and wait for a result. + Copyright (C) 2005 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" + +const char * +pex_one (int flags, const char *executable, char * const *argv, + const char *pname, const char *outname, const char *errname, + int *status, int *err) +{ + struct pex_obj *obj; + const char *errmsg; + + obj = pex_init (0, pname, NULL); + errmsg = pex_run (obj, flags, executable, argv, outname, errname, err); + if (errmsg == NULL) + { + if (!pex_get_status (obj, 1, status)) + { + *err = 0; + errmsg = "pex_get_status failed"; + } + } + pex_free (obj); + return errmsg; +} diff --git a/external/gpl3/gdb/dist/libiberty/pex-unix.c b/external/gpl3/gdb/dist/libiberty/pex-unix.c new file mode 100644 index 000000000000..8d5145c523e6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-unix.c @@ -0,0 +1,788 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic Unix version + (also used for UWIN and VMS). + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2009, + 2010 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "pex-common.h" + +#include +#include +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif + +#include + +#ifdef HAVE_FCNTL_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif +#ifdef HAVE_GETRUSAGE +#include +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +#ifdef HAVE_PROCESS_H +#include +#endif + +#ifdef vfork /* Autoconf may define this to fork for us. */ +# define VFORK_STRING "fork" +#else +# define VFORK_STRING "vfork" +#endif +#ifdef HAVE_VFORK_H +#include +#endif +#if defined(VMS) && defined (__LONG_POINTERS) +#ifndef __CHAR_PTR32 +typedef char * __char_ptr32 +__attribute__ ((mode (SI))); +#endif + +typedef __char_ptr32 *__char_ptr_char_ptr32 +__attribute__ ((mode (SI))); + +/* Return a 32 bit pointer to an array of 32 bit pointers + given a 64 bit pointer to an array of 64 bit pointers. */ + +static __char_ptr_char_ptr32 +to_ptr32 (char **ptr64) +{ + int argc; + __char_ptr_char_ptr32 short_argv; + + for (argc=0; ptr64[argc]; argc++); + + /* Reallocate argv with 32 bit pointers. */ + short_argv = (__char_ptr_char_ptr32) decc$malloc + (sizeof (__char_ptr32) * (argc + 1)); + + for (argc=0; ptr64[argc]; argc++) + short_argv[argc] = (__char_ptr32) decc$strdup (ptr64[argc]); + + short_argv[argc] = (__char_ptr32) 0; + return short_argv; + +} +#else +#define to_ptr32(argv) argv +#endif + +/* File mode to use for private and world-readable files. */ + +#if defined (S_IRUSR) && defined (S_IWUSR) && defined (S_IRGRP) && defined (S_IWGRP) && defined (S_IROTH) && defined (S_IWOTH) +#define PUBLIC_MODE \ + (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH) +#else +#define PUBLIC_MODE 0666 +#endif + +/* Get the exit status of a particular process, and optionally get the + time that it took. This is simple if we have wait4, slightly + harder if we have waitpid, and is a pain if we only have wait. */ + +static pid_t pex_wait (struct pex_obj *, pid_t, int *, struct pex_time *); + +#ifdef HAVE_WAIT4 + +static pid_t +pex_wait (struct pex_obj *obj ATTRIBUTE_UNUSED, pid_t pid, int *status, + struct pex_time *time) +{ + pid_t ret; + struct rusage r; + +#ifdef HAVE_WAITPID + if (time == NULL) + return waitpid (pid, status, 0); +#endif + + ret = wait4 (pid, status, 0, &r); + + if (time != NULL) + { + time->user_seconds = r.ru_utime.tv_sec; + time->user_microseconds= r.ru_utime.tv_usec; + time->system_seconds = r.ru_stime.tv_sec; + time->system_microseconds= r.ru_stime.tv_usec; + } + + return ret; +} + +#else /* ! defined (HAVE_WAIT4) */ + +#ifdef HAVE_WAITPID + +#ifndef HAVE_GETRUSAGE + +static pid_t +pex_wait (struct pex_obj *obj ATTRIBUTE_UNUSED, pid_t pid, int *status, + struct pex_time *time) +{ + if (time != NULL) + memset (time, 0, sizeof (struct pex_time)); + return waitpid (pid, status, 0); +} + +#else /* defined (HAVE_GETRUSAGE) */ + +static pid_t +pex_wait (struct pex_obj *obj ATTRIBUTE_UNUSED, pid_t pid, int *status, + struct pex_time *time) +{ + struct rusage r1, r2; + pid_t ret; + + if (time == NULL) + return waitpid (pid, status, 0); + + getrusage (RUSAGE_CHILDREN, &r1); + + ret = waitpid (pid, status, 0); + if (ret < 0) + return ret; + + getrusage (RUSAGE_CHILDREN, &r2); + + time->user_seconds = r2.ru_utime.tv_sec - r1.ru_utime.tv_sec; + time->user_microseconds = r2.ru_utime.tv_usec - r1.ru_utime.tv_usec; + if (r2.ru_utime.tv_usec < r1.ru_utime.tv_usec) + { + --time->user_seconds; + time->user_microseconds += 1000000; + } + + time->system_seconds = r2.ru_stime.tv_sec - r1.ru_stime.tv_sec; + time->system_microseconds = r2.ru_stime.tv_usec - r1.ru_stime.tv_usec; + if (r2.ru_stime.tv_usec < r1.ru_stime.tv_usec) + { + --time->system_seconds; + time->system_microseconds += 1000000; + } + + return ret; +} + +#endif /* defined (HAVE_GETRUSAGE) */ + +#else /* ! defined (HAVE_WAITPID) */ + +struct status_list +{ + struct status_list *next; + pid_t pid; + int status; + struct pex_time time; +}; + +static pid_t +pex_wait (struct pex_obj *obj, pid_t pid, int *status, struct pex_time *time) +{ + struct status_list **pp; + + for (pp = (struct status_list **) &obj->sysdep; + *pp != NULL; + pp = &(*pp)->next) + { + if ((*pp)->pid == pid) + { + struct status_list *p; + + p = *pp; + *status = p->status; + if (time != NULL) + *time = p->time; + *pp = p->next; + free (p); + return pid; + } + } + + while (1) + { + pid_t cpid; + struct status_list *psl; + struct pex_time pt; +#ifdef HAVE_GETRUSAGE + struct rusage r1, r2; +#endif + + if (time != NULL) + { +#ifdef HAVE_GETRUSAGE + getrusage (RUSAGE_CHILDREN, &r1); +#else + memset (&pt, 0, sizeof (struct pex_time)); +#endif + } + + cpid = wait (status); + +#ifdef HAVE_GETRUSAGE + if (time != NULL && cpid >= 0) + { + getrusage (RUSAGE_CHILDREN, &r2); + + pt.user_seconds = r2.ru_utime.tv_sec - r1.ru_utime.tv_sec; + pt.user_microseconds = r2.ru_utime.tv_usec - r1.ru_utime.tv_usec; + if (pt.user_microseconds < 0) + { + --pt.user_seconds; + pt.user_microseconds += 1000000; + } + + pt.system_seconds = r2.ru_stime.tv_sec - r1.ru_stime.tv_sec; + pt.system_microseconds = r2.ru_stime.tv_usec - r1.ru_stime.tv_usec; + if (pt.system_microseconds < 0) + { + --pt.system_seconds; + pt.system_microseconds += 1000000; + } + } +#endif + + if (cpid < 0 || cpid == pid) + { + if (time != NULL) + *time = pt; + return cpid; + } + + psl = XNEW (struct status_list); + psl->pid = cpid; + psl->status = *status; + if (time != NULL) + psl->time = pt; + psl->next = (struct status_list *) obj->sysdep; + obj->sysdep = (void *) psl; + } +} + +#endif /* ! defined (HAVE_WAITPID) */ +#endif /* ! defined (HAVE_WAIT4) */ + +static void pex_child_error (struct pex_obj *, const char *, const char *, int) + ATTRIBUTE_NORETURN; +static int pex_unix_open_read (struct pex_obj *, const char *, int); +static int pex_unix_open_write (struct pex_obj *, const char *, int); +static pid_t pex_unix_exec_child (struct pex_obj *, int, const char *, + char * const *, char * const *, + int, int, int, int, + const char **, int *); +static int pex_unix_close (struct pex_obj *, int); +static int pex_unix_wait (struct pex_obj *, pid_t, int *, struct pex_time *, + int, const char **, int *); +static int pex_unix_pipe (struct pex_obj *, int *, int); +static FILE *pex_unix_fdopenr (struct pex_obj *, int, int); +static FILE *pex_unix_fdopenw (struct pex_obj *, int, int); +static void pex_unix_cleanup (struct pex_obj *); + +/* The list of functions we pass to the common routines. */ + +const struct pex_funcs funcs = +{ + pex_unix_open_read, + pex_unix_open_write, + pex_unix_exec_child, + pex_unix_close, + pex_unix_wait, + pex_unix_pipe, + pex_unix_fdopenr, + pex_unix_fdopenw, + pex_unix_cleanup +}; + +/* Return a newly initialized pex_obj structure. */ + +struct pex_obj * +pex_init (int flags, const char *pname, const char *tempbase) +{ + return pex_init_common (flags, pname, tempbase, &funcs); +} + +/* Open a file for reading. */ + +static int +pex_unix_open_read (struct pex_obj *obj ATTRIBUTE_UNUSED, const char *name, + int binary ATTRIBUTE_UNUSED) +{ + return open (name, O_RDONLY); +} + +/* Open a file for writing. */ + +static int +pex_unix_open_write (struct pex_obj *obj ATTRIBUTE_UNUSED, const char *name, + int binary ATTRIBUTE_UNUSED) +{ + /* Note that we can't use O_EXCL here because gcc may have already + created the temporary file via make_temp_file. */ + return open (name, O_WRONLY | O_CREAT | O_TRUNC, PUBLIC_MODE); +} + +/* Close a file. */ + +static int +pex_unix_close (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd) +{ + return close (fd); +} + +/* Report an error from a child process. We don't use stdio routines, + because we might be here due to a vfork call. */ + +static void +pex_child_error (struct pex_obj *obj, const char *executable, + const char *errmsg, int err) +{ + int retval = 0; +#define writeerr(s) retval |= (write (STDERR_FILE_NO, s, strlen (s)) < 0) + writeerr (obj->pname); + writeerr (": error trying to exec '"); + writeerr (executable); + writeerr ("': "); + writeerr (errmsg); + writeerr (": "); + writeerr (xstrerror (err)); + writeerr ("\n"); +#undef writeerr + /* Exit with -2 if the error output failed, too. */ + _exit (retval == 0 ? -1 : -2); +} + +/* Execute a child. */ + +extern char **environ; + +#if defined(HAVE_SPAWNVE) && defined(HAVE_SPAWNVPE) +/* Implementation of pex->exec_child using the Cygwin spawn operation. */ + +/* Subroutine of pex_unix_exec_child. Move OLD_FD to a new file descriptor + to be stored in *PNEW_FD, save the flags in *PFLAGS, and arrange for the + saved copy to be close-on-exec. Move CHILD_FD into OLD_FD. If CHILD_FD + is -1, OLD_FD is to be closed. Return -1 on error. */ + +static int +save_and_install_fd(int *pnew_fd, int *pflags, int old_fd, int child_fd) +{ + int new_fd, flags; + + flags = fcntl (old_fd, F_GETFD); + + /* If we could not retrieve the flags, then OLD_FD was not open. */ + if (flags < 0) + { + new_fd = -1, flags = 0; + if (child_fd >= 0 && dup2 (child_fd, old_fd) < 0) + return -1; + } + /* If we wish to close OLD_FD, just mark it CLOEXEC. */ + else if (child_fd == -1) + { + new_fd = old_fd; + if ((flags & FD_CLOEXEC) == 0 && fcntl (old_fd, F_SETFD, FD_CLOEXEC) < 0) + return -1; + } + /* Otherwise we need to save a copy of OLD_FD before installing CHILD_FD. */ + else + { +#ifdef F_DUPFD_CLOEXEC + new_fd = fcntl (old_fd, F_DUPFD_CLOEXEC, 3); + if (new_fd < 0) + return -1; +#else + /* Prefer F_DUPFD over dup in order to avoid getting a new fd + in the range 0-2, right where a new stderr fd might get put. */ + new_fd = fcntl (old_fd, F_DUPFD, 3); + if (new_fd < 0) + return -1; + if (fcntl (new_fd, F_SETFD, FD_CLOEXEC) < 0) + return -1; +#endif + if (dup2 (child_fd, old_fd) < 0) + return -1; + } + + *pflags = flags; + if (pnew_fd) + *pnew_fd = new_fd; + else if (new_fd != old_fd) + abort (); + + return 0; +} + +/* Subroutine of pex_unix_exec_child. Move SAVE_FD back to OLD_FD + restoring FLAGS. If SAVE_FD < 0, OLD_FD is to be closed. */ + +static int +restore_fd(int old_fd, int save_fd, int flags) +{ + /* For SAVE_FD < 0, all we have to do is restore the + "closed-ness" of the original. */ + if (save_fd < 0) + return close (old_fd); + + /* For SAVE_FD == OLD_FD, all we have to do is restore the + original setting of the CLOEXEC flag. */ + if (save_fd == old_fd) + { + if (flags & FD_CLOEXEC) + return 0; + return fcntl (old_fd, F_SETFD, flags); + } + + /* Otherwise we have to move the descriptor back, restore the flags, + and close the saved copy. */ +#ifdef HAVE_DUP3 + if (flags == FD_CLOEXEC) + { + if (dup3 (save_fd, old_fd, O_CLOEXEC) < 0) + return -1; + } + else +#endif + { + if (dup2 (save_fd, old_fd) < 0) + return -1; + if (flags != 0 && fcntl (old_fd, F_SETFD, flags) < 0) + return -1; + } + return close (save_fd); +} + +static pid_t +pex_unix_exec_child (struct pex_obj *obj ATTRIBUTE_UNUSED, + int flags, const char *executable, + char * const * argv, char * const * env, + int in, int out, int errdes, int toclose, + const char **errmsg, int *err) +{ + int fl_in = 0, fl_out = 0, fl_err = 0, fl_tc = 0; + int save_in = -1, save_out = -1, save_err = -1; + int max, retries; + pid_t pid; + + if (flags & PEX_STDERR_TO_STDOUT) + errdes = out; + + /* We need the three standard file descriptors to be set up as for + the child before we perform the spawn. The file descriptors for + the parent need to be moved and marked for close-on-exec. */ + if (in != STDIN_FILE_NO + && save_and_install_fd (&save_in, &fl_in, STDIN_FILE_NO, in) < 0) + goto error_dup2; + if (out != STDOUT_FILE_NO + && save_and_install_fd (&save_out, &fl_out, STDOUT_FILE_NO, out) < 0) + goto error_dup2; + if (errdes != STDERR_FILE_NO + && save_and_install_fd (&save_err, &fl_err, STDERR_FILE_NO, errdes) < 0) + goto error_dup2; + if (toclose >= 0 + && save_and_install_fd (NULL, &fl_tc, toclose, -1) < 0) + goto error_dup2; + + /* Now that we've moved the file descriptors for the child into place, + close the originals. Be careful not to close any of the standard + file descriptors that we just set up. */ + max = -1; + if (errdes >= 0) + max = STDERR_FILE_NO; + else if (out >= 0) + max = STDOUT_FILE_NO; + else if (in >= 0) + max = STDIN_FILE_NO; + if (in > max) + close (in); + if (out > max) + close (out); + if (errdes > max && errdes != out) + close (errdes); + + /* If we were not given an environment, use the global environment. */ + if (env == NULL) + env = environ; + + /* Launch the program. If we get EAGAIN (normally out of pid's), try + again a few times with increasing backoff times. */ + retries = 0; + while (1) + { + typedef const char * const *cc_cp; + + if (flags & PEX_SEARCH) + pid = spawnvpe (_P_NOWAITO, executable, (cc_cp)argv, (cc_cp)env); + else + pid = spawnve (_P_NOWAITO, executable, (cc_cp)argv, (cc_cp)env); + + if (pid > 0) + break; + + *err = errno; + *errmsg = "spawn"; + if (errno != EAGAIN || ++retries == 4) + return (pid_t) -1; + sleep (1 << retries); + } + + /* Success. Restore the parent's file descriptors that we saved above. */ + if (toclose >= 0 + && restore_fd (toclose, toclose, fl_tc) < 0) + goto error_dup2; + if (in != STDIN_FILE_NO + && restore_fd (STDIN_FILE_NO, save_in, fl_in) < 0) + goto error_dup2; + if (out != STDOUT_FILE_NO + && restore_fd (STDOUT_FILE_NO, save_out, fl_out) < 0) + goto error_dup2; + if (errdes != STDERR_FILE_NO + && restore_fd (STDERR_FILE_NO, save_err, fl_err) < 0) + goto error_dup2; + + return pid; + + error_dup2: + *err = errno; + *errmsg = "dup2"; + return (pid_t) -1; +} + +#else +/* Implementation of pex->exec_child using standard vfork + exec. */ + +static pid_t +pex_unix_exec_child (struct pex_obj *obj, int flags, const char *executable, + char * const * argv, char * const * env, + int in, int out, int errdes, + int toclose, const char **errmsg, int *err) +{ + pid_t pid; + + /* We declare these to be volatile to avoid warnings from gcc about + them being clobbered by vfork. */ + volatile int sleep_interval; + volatile int retries; + + /* We vfork and then set environ in the child before calling execvp. + This clobbers the parent's environ so we need to restore it. + It would be nice to use one of the exec* functions that takes an + environment as a parameter, but that may have portability issues. */ + char **save_environ = environ; + + sleep_interval = 1; + pid = -1; + for (retries = 0; retries < 4; ++retries) + { + pid = vfork (); + if (pid >= 0) + break; + sleep (sleep_interval); + sleep_interval *= 2; + } + + switch (pid) + { + case -1: + *err = errno; + *errmsg = VFORK_STRING; + return (pid_t) -1; + + case 0: + /* Child process. */ + if (in != STDIN_FILE_NO) + { + if (dup2 (in, STDIN_FILE_NO) < 0) + pex_child_error (obj, executable, "dup2", errno); + if (close (in) < 0) + pex_child_error (obj, executable, "close", errno); + } + if (out != STDOUT_FILE_NO) + { + if (dup2 (out, STDOUT_FILE_NO) < 0) + pex_child_error (obj, executable, "dup2", errno); + if (close (out) < 0) + pex_child_error (obj, executable, "close", errno); + } + if (errdes != STDERR_FILE_NO) + { + if (dup2 (errdes, STDERR_FILE_NO) < 0) + pex_child_error (obj, executable, "dup2", errno); + if (close (errdes) < 0) + pex_child_error (obj, executable, "close", errno); + } + if (toclose >= 0) + { + if (close (toclose) < 0) + pex_child_error (obj, executable, "close", errno); + } + if ((flags & PEX_STDERR_TO_STDOUT) != 0) + { + if (dup2 (STDOUT_FILE_NO, STDERR_FILE_NO) < 0) + pex_child_error (obj, executable, "dup2", errno); + } + + if (env) + { + /* NOTE: In a standard vfork implementation this clobbers the + parent's copy of environ "too" (in reality there's only one copy). + This is ok as we restore it below. */ + environ = (char**) env; + } + + if ((flags & PEX_SEARCH) != 0) + { + execvp (executable, to_ptr32 (argv)); + pex_child_error (obj, executable, "execvp", errno); + } + else + { + execv (executable, to_ptr32 (argv)); + pex_child_error (obj, executable, "execv", errno); + } + + /* NOTREACHED */ + return (pid_t) -1; + + default: + /* Parent process. */ + + /* Restore environ. + Note that the parent either doesn't run until the child execs/exits + (standard vfork behaviour), or if it does run then vfork is behaving + more like fork. In either case we needn't worry about clobbering + the child's copy of environ. */ + environ = save_environ; + + if (in != STDIN_FILE_NO) + { + if (close (in) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + if (out != STDOUT_FILE_NO) + { + if (close (out) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + if (errdes != STDERR_FILE_NO) + { + if (close (errdes) < 0) + { + *err = errno; + *errmsg = "close"; + return (pid_t) -1; + } + } + + return pid; + } +} +#endif /* SPAWN */ + +/* Wait for a child process to complete. */ + +static int +pex_unix_wait (struct pex_obj *obj, pid_t pid, int *status, + struct pex_time *time, int done, const char **errmsg, + int *err) +{ + /* If we are cleaning up when the caller didn't retrieve process + status for some reason, encourage the process to go away. */ + if (done) + kill (pid, SIGTERM); + + if (pex_wait (obj, pid, status, time) < 0) + { + *err = errno; + *errmsg = "wait"; + return -1; + } + + return 0; +} + +/* Create a pipe. */ + +static int +pex_unix_pipe (struct pex_obj *obj ATTRIBUTE_UNUSED, int *p, + int binary ATTRIBUTE_UNUSED) +{ + return pipe (p); +} + +/* Get a FILE pointer to read from a file descriptor. */ + +static FILE * +pex_unix_fdopenr (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd, + int binary ATTRIBUTE_UNUSED) +{ + return fdopen (fd, "r"); +} + +static FILE * +pex_unix_fdopenw (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd, + int binary ATTRIBUTE_UNUSED) +{ + if (fcntl (fd, F_SETFD, FD_CLOEXEC) < 0) + return NULL; + return fdopen (fd, "w"); +} + +static void +pex_unix_cleanup (struct pex_obj *obj ATTRIBUTE_UNUSED) +{ +#if !defined (HAVE_WAIT4) && !defined (HAVE_WAITPID) + while (obj->sysdep != NULL) + { + struct status_list *this; + struct status_list *next; + + this = (struct status_list *) obj->sysdep; + next = this->next; + free (this); + obj->sysdep = (void *) next; + } +#endif +} diff --git a/external/gpl3/gdb/dist/libiberty/pex-win32.c b/external/gpl3/gdb/dist/libiberty/pex-win32.c new file mode 100644 index 000000000000..44274067482c --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pex-win32.c @@ -0,0 +1,950 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. Generic Win32 specialization. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "pex-common.h" + +#include + +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +/* mingw32 headers may not define the following. */ + +#ifndef _P_WAIT +# define _P_WAIT 0 +# define _P_NOWAIT 1 +# define _P_OVERLAY 2 +# define _P_NOWAITO 3 +# define _P_DETACH 4 + +# define WAIT_CHILD 0 +# define WAIT_GRANDCHILD 1 +#endif + +#define MINGW_NAME "Minimalist GNU for Windows" +#define MINGW_NAME_LEN (sizeof(MINGW_NAME) - 1) + +extern char *stpcpy (char *dst, const char *src); + +/* Ensure that the executable pathname uses Win32 backslashes. This + is not necessary on NT, but on W9x, forward slashes causes + failure of spawn* and exec* functions (and probably any function + that calls CreateProcess) *iff* the executable pathname (argv[0]) + is a quoted string. And quoting is necessary in case a pathname + contains embedded white space. You can't win. */ +static void +backslashify (char *s) +{ + while ((s = strchr (s, '/')) != NULL) + *s = '\\'; + return; +} + +static int pex_win32_open_read (struct pex_obj *, const char *, int); +static int pex_win32_open_write (struct pex_obj *, const char *, int); +static pid_t pex_win32_exec_child (struct pex_obj *, int, const char *, + char * const *, char * const *, + int, int, int, int, + const char **, int *); +static int pex_win32_close (struct pex_obj *, int); +static pid_t pex_win32_wait (struct pex_obj *, pid_t, int *, + struct pex_time *, int, const char **, int *); +static int pex_win32_pipe (struct pex_obj *, int *, int); +static FILE *pex_win32_fdopenr (struct pex_obj *, int, int); +static FILE *pex_win32_fdopenw (struct pex_obj *, int, int); + +/* The list of functions we pass to the common routines. */ + +const struct pex_funcs funcs = +{ + pex_win32_open_read, + pex_win32_open_write, + pex_win32_exec_child, + pex_win32_close, + pex_win32_wait, + pex_win32_pipe, + pex_win32_fdopenr, + pex_win32_fdopenw, + NULL /* cleanup */ +}; + +/* Return a newly initialized pex_obj structure. */ + +struct pex_obj * +pex_init (int flags, const char *pname, const char *tempbase) +{ + return pex_init_common (flags, pname, tempbase, &funcs); +} + +/* Open a file for reading. */ + +static int +pex_win32_open_read (struct pex_obj *obj ATTRIBUTE_UNUSED, const char *name, + int binary) +{ + return _open (name, _O_RDONLY | (binary ? _O_BINARY : _O_TEXT)); +} + +/* Open a file for writing. */ + +static int +pex_win32_open_write (struct pex_obj *obj ATTRIBUTE_UNUSED, const char *name, + int binary) +{ + /* Note that we can't use O_EXCL here because gcc may have already + created the temporary file via make_temp_file. */ + return _open (name, + (_O_WRONLY | _O_CREAT | _O_TRUNC + | (binary ? _O_BINARY : _O_TEXT)), + _S_IREAD | _S_IWRITE); +} + +/* Close a file. */ + +static int +pex_win32_close (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd) +{ + return _close (fd); +} + +#ifdef USE_MINGW_MSYS +static const char *mingw_keys[] = {"SOFTWARE", "Microsoft", "Windows", "CurrentVersion", "Uninstall", NULL}; + +/* Tack the executable on the end of a (possibly slash terminated) buffer + and convert everything to \. */ +static const char * +tack_on_executable (char *buf, const char *executable) +{ + char *p = strchr (buf, '\0'); + if (p > buf && (p[-1] == '\\' || p[-1] == '/')) + p[-1] = '\0'; + backslashify (strcat (buf, executable)); + return buf; +} + +/* Walk down a registry hierarchy until the end. Return the key. */ +static HKEY +openkey (HKEY hStart, const char *keys[]) +{ + HKEY hKey, hTmp; + for (hKey = hStart; *keys; keys++) + { + LONG res; + hTmp = hKey; + res = RegOpenKey (hTmp, *keys, &hKey); + + if (hTmp != HKEY_LOCAL_MACHINE) + RegCloseKey (hTmp); + + if (res != ERROR_SUCCESS) + return NULL; + } + return hKey; +} + +/* Return the "mingw root" as derived from the mingw uninstall information. */ +static const char * +mingw_rootify (const char *executable) +{ + HKEY hKey, hTmp; + DWORD maxlen; + char *namebuf, *foundbuf; + DWORD i; + LONG res; + + /* Open the uninstall "directory". */ + hKey = openkey (HKEY_LOCAL_MACHINE, mingw_keys); + + /* Not found. */ + if (!hKey) + return executable; + + /* Need to enumerate all of the keys here looking for one the most recent + one for MinGW. */ + if (RegQueryInfoKey (hKey, NULL, NULL, NULL, NULL, &maxlen, NULL, NULL, + NULL, NULL, NULL, NULL) != ERROR_SUCCESS) + { + RegCloseKey (hKey); + return executable; + } + namebuf = XNEWVEC (char, ++maxlen); + foundbuf = XNEWVEC (char, maxlen); + foundbuf[0] = '\0'; + if (!namebuf || !foundbuf) + { + RegCloseKey (hKey); + if (namebuf) + free (namebuf); + if (foundbuf) + free (foundbuf); + return executable; + } + + /* Look through all of the keys for one that begins with Minimal GNU... + Try to get the latest version by doing a string compare although that + string never really works with version number sorting. */ + for (i = 0; RegEnumKey (hKey, i, namebuf, maxlen) == ERROR_SUCCESS; i++) + { + int match = strcasecmp (namebuf, MINGW_NAME); + if (match < 0) + continue; + if (match > 0 && strncasecmp (namebuf, MINGW_NAME, MINGW_NAME_LEN) > 0) + continue; + if (strcasecmp (namebuf, foundbuf) > 0) + strcpy (foundbuf, namebuf); + } + free (namebuf); + + /* If foundbuf is empty, we didn't find anything. Punt. */ + if (!foundbuf[0]) + { + free (foundbuf); + RegCloseKey (hKey); + return executable; + } + + /* Open the key that we wanted */ + res = RegOpenKey (hKey, foundbuf, &hTmp); + RegCloseKey (hKey); + free (foundbuf); + + /* Don't know why this would fail, but you gotta check */ + if (res != ERROR_SUCCESS) + return executable; + + maxlen = 0; + /* Get the length of the value pointed to by InstallLocation */ + if (RegQueryValueEx (hTmp, "InstallLocation", 0, NULL, NULL, + &maxlen) != ERROR_SUCCESS || maxlen == 0) + { + RegCloseKey (hTmp); + return executable; + } + + /* Allocate space for the install location */ + foundbuf = XNEWVEC (char, maxlen + strlen (executable)); + if (!foundbuf) + { + free (foundbuf); + RegCloseKey (hTmp); + } + + /* Read the install location into the buffer */ + res = RegQueryValueEx (hTmp, "InstallLocation", 0, NULL, (LPBYTE) foundbuf, + &maxlen); + RegCloseKey (hTmp); + if (res != ERROR_SUCCESS) + { + free (foundbuf); + return executable; + } + + /* Concatenate the install location and the executable, turn all slashes + to backslashes, and return that. */ + return tack_on_executable (foundbuf, executable); +} + +/* Read the install location of msys from it's installation file and + rootify the executable based on that. */ +static const char * +msys_rootify (const char *executable) +{ + size_t bufsize = 64; + size_t execlen = strlen (executable) + 1; + char *buf; + DWORD res = 0; + for (;;) + { + buf = XNEWVEC (char, bufsize + execlen); + if (!buf) + break; + res = GetPrivateProfileString ("InstallSettings", "InstallPath", NULL, + buf, bufsize, "msys.ini"); + if (!res) + break; + if (strlen (buf) < bufsize) + break; + res = 0; + free (buf); + bufsize *= 2; + if (bufsize > 65536) + { + buf = NULL; + break; + } + } + + if (res) + return tack_on_executable (buf, executable); + + /* failed */ + if (buf) + free (buf); + return executable; +} +#endif + +/* Return the number of arguments in an argv array, not including the null + terminating argument. */ + +static int +argv_to_argc (char *const *argv) +{ + char *const *i = argv; + while (*i) + i++; + return i - argv; +} + +/* Return a Windows command-line from ARGV. It is the caller's + responsibility to free the string returned. */ + +static char * +argv_to_cmdline (char *const *argv) +{ + char *cmdline; + char *p; + size_t cmdline_len; + int i, j, k; + + cmdline_len = 0; + for (i = 0; argv[i]; i++) + { + /* We quote every last argument. This simplifies the problem; + we need only escape embedded double-quotes and immediately + preceeding backslash characters. A sequence of backslach characters + that is not follwed by a double quote character will not be + escaped. */ + for (j = 0; argv[i][j]; j++) + { + if (argv[i][j] == '"') + { + /* Escape preceeding backslashes. */ + for (k = j - 1; k >= 0 && argv[i][k] == '\\'; k--) + cmdline_len++; + /* Escape the qote character. */ + cmdline_len++; + } + } + /* Trailing backslashes also need to be escaped because they will be + followed by the terminating quote. */ + for (k = j - 1; k >= 0 && argv[i][k] == '\\'; k--) + cmdline_len++; + cmdline_len += j; + cmdline_len += 3; /* for leading and trailing quotes and space */ + } + cmdline = XNEWVEC (char, cmdline_len); + p = cmdline; + for (i = 0; argv[i]; i++) + { + *p++ = '"'; + for (j = 0; argv[i][j]; j++) + { + if (argv[i][j] == '"') + { + for (k = j - 1; k >= 0 && argv[i][k] == '\\'; k--) + *p++ = '\\'; + *p++ = '\\'; + } + *p++ = argv[i][j]; + } + for (k = j - 1; k >= 0 && argv[i][k] == '\\'; k--) + *p++ = '\\'; + *p++ = '"'; + *p++ = ' '; + } + p[-1] = '\0'; + return cmdline; +} + +/* We'll try the passed filename with all the known standard + extensions, and then without extension. We try no extension + last so that we don't try to run some random extension-less + file that might be hanging around. We try both extension + and no extension so that we don't need any fancy logic + to determine if a file has extension. */ +static const char *const +std_suffixes[] = { + ".com", + ".exe", + ".bat", + ".cmd", + "", + 0 +}; + +/* Returns the full path to PROGRAM. If SEARCH is true, look for + PROGRAM in each directory in PATH. */ + +static char * +find_executable (const char *program, BOOL search) +{ + char *full_executable; + char *e; + size_t fe_len; + const char *path = 0; + const char *const *ext; + const char *p, *q; + size_t proglen = strlen (program); + int has_slash = (strchr (program, '/') || strchr (program, '\\')); + HANDLE h; + + if (has_slash) + search = FALSE; + + if (search) + path = getenv ("PATH"); + if (!path) + path = ""; + + fe_len = 0; + for (p = path; *p; p = q) + { + q = p; + while (*q != ';' && *q != '\0') + q++; + if ((size_t)(q - p) > fe_len) + fe_len = q - p; + if (*q == ';') + q++; + } + fe_len = fe_len + 1 + proglen + 5 /* space for extension */; + full_executable = XNEWVEC (char, fe_len); + + p = path; + do + { + q = p; + while (*q != ';' && *q != '\0') + q++; + + e = full_executable; + memcpy (e, p, q - p); + e += (q - p); + if (q - p) + *e++ = '\\'; + strcpy (e, program); + + if (*q == ';') + q++; + + for (e = full_executable; *e; e++) + if (*e == '/') + *e = '\\'; + + /* At this point, e points to the terminating NUL character for + full_executable. */ + for (ext = std_suffixes; *ext; ext++) + { + /* Remove any current extension. */ + *e = '\0'; + /* Add the new one. */ + strcat (full_executable, *ext); + + /* Attempt to open this file. */ + h = CreateFile (full_executable, GENERIC_READ, + FILE_SHARE_READ | FILE_SHARE_WRITE, + 0, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, 0); + if (h != INVALID_HANDLE_VALUE) + goto found; + } + p = q; + } + while (*p); + free (full_executable); + return 0; + + found: + CloseHandle (h); + return full_executable; +} + +/* Low-level process creation function and helper. */ + +static int +env_compare (const void *a_ptr, const void *b_ptr) +{ + const char *a; + const char *b; + unsigned char c1; + unsigned char c2; + + a = *(const char **) a_ptr; + b = *(const char **) b_ptr; + + /* a and b will be of the form: VAR=VALUE + We compare only the variable name part here using a case-insensitive + comparison algorithm. It might appear that in fact strcasecmp () can + take the place of this whole function, and indeed it could, save for + the fact that it would fail in cases such as comparing A1=foo and + A=bar (because 1 is less than = in the ASCII character set). + (Environment variables containing no numbers would work in such a + scenario.) */ + + do + { + c1 = (unsigned char) tolower (*a++); + c2 = (unsigned char) tolower (*b++); + + if (c1 == '=') + c1 = '\0'; + + if (c2 == '=') + c2 = '\0'; + } + while (c1 == c2 && c1 != '\0'); + + return c1 - c2; +} + +/* Execute a Windows executable as a child process. This will fail if the + * target is not actually an executable, such as if it is a shell script. */ + +static pid_t +win32_spawn (const char *executable, + BOOL search, + char *const *argv, + char *const *env, /* array of strings of the form: VAR=VALUE */ + DWORD dwCreationFlags, + LPSTARTUPINFO si, + LPPROCESS_INFORMATION pi) +{ + char *full_executable; + char *cmdline; + char **env_copy; + char *env_block = NULL; + + full_executable = NULL; + cmdline = NULL; + + if (env) + { + int env_size; + + /* Count the number of environment bindings supplied. */ + for (env_size = 0; env[env_size]; env_size++) + continue; + + /* Assemble an environment block, if required. This consists of + VAR=VALUE strings juxtaposed (with one null character between each + pair) and an additional null at the end. */ + if (env_size > 0) + { + int var; + int total_size = 1; /* 1 is for the final null. */ + char *bufptr; + + /* Windows needs the members of the block to be sorted by variable + name. */ + env_copy = (char **) alloca (sizeof (char *) * env_size); + memcpy (env_copy, env, sizeof (char *) * env_size); + qsort (env_copy, env_size, sizeof (char *), env_compare); + + for (var = 0; var < env_size; var++) + total_size += strlen (env[var]) + 1; + + env_block = XNEWVEC (char, total_size); + bufptr = env_block; + for (var = 0; var < env_size; var++) + bufptr = stpcpy (bufptr, env_copy[var]) + 1; + + *bufptr = '\0'; + } + } + + full_executable = find_executable (executable, search); + if (!full_executable) + goto error; + cmdline = argv_to_cmdline (argv); + if (!cmdline) + goto error; + + /* Create the child process. */ + if (!CreateProcess (full_executable, cmdline, + /*lpProcessAttributes=*/NULL, + /*lpThreadAttributes=*/NULL, + /*bInheritHandles=*/TRUE, + dwCreationFlags, + (LPVOID) env_block, + /*lpCurrentDirectory=*/NULL, + si, + pi)) + { + if (env_block) + free (env_block); + + free (full_executable); + + return (pid_t) -1; + } + + /* Clean up. */ + CloseHandle (pi->hThread); + free (full_executable); + if (env_block) + free (env_block); + + return (pid_t) pi->hProcess; + + error: + if (env_block) + free (env_block); + if (cmdline) + free (cmdline); + if (full_executable) + free (full_executable); + + return (pid_t) -1; +} + +/* Spawn a script. This simulates the Unix script execution mechanism. + This function is called as a fallback if win32_spawn fails. */ + +static pid_t +spawn_script (const char *executable, char *const *argv, + char* const *env, + DWORD dwCreationFlags, + LPSTARTUPINFO si, + LPPROCESS_INFORMATION pi) +{ + pid_t pid = (pid_t) -1; + int save_errno = errno; + int fd = _open (executable, _O_RDONLY); + + /* Try to open script, check header format, extract interpreter path, + and spawn script using that interpretter. */ + if (fd >= 0) + { + char buf[MAX_PATH + 5]; + int len = _read (fd, buf, sizeof (buf) - 1); + _close (fd); + if (len > 3) + { + char *eol; + buf[len] = '\0'; + eol = strchr (buf, '\n'); + if (eol && strncmp (buf, "#!", 2) == 0) + { + + /* Header format is OK. */ + char *executable1; + int new_argc; + const char **avhere; + + /* Extract interpreter path. */ + do + *eol = '\0'; + while (*--eol == '\r' || *eol == ' ' || *eol == '\t'); + for (executable1 = buf + 2; *executable1 == ' ' || *executable1 == '\t'; executable1++) + continue; + backslashify (executable1); + + /* Duplicate argv, prepending the interpreter path. */ + new_argc = argv_to_argc (argv) + 1; + avhere = XNEWVEC (const char *, new_argc + 1); + *avhere = executable1; + memcpy (avhere + 1, argv, new_argc * sizeof(*argv)); + argv = (char *const *)avhere; + + /* Spawn the child. */ +#ifndef USE_MINGW_MSYS + executable = strrchr (executable1, '\\') + 1; + if (!executable) + executable = executable1; + pid = win32_spawn (executable, TRUE, argv, env, + dwCreationFlags, si, pi); +#else + if (strchr (executable1, '\\') == NULL) + pid = win32_spawn (executable1, TRUE, argv, env, + dwCreationFlags, si, pi); + else if (executable1[0] != '\\') + pid = win32_spawn (executable1, FALSE, argv, env, + dwCreationFlags, si, pi); + else + { + const char *newex = mingw_rootify (executable1); + *avhere = newex; + pid = win32_spawn (newex, FALSE, argv, env, + dwCreationFlags, si, pi); + if (executable1 != newex) + free ((char *) newex); + if (pid == (pid_t) -1) + { + newex = msys_rootify (executable1); + if (newex != executable1) + { + *avhere = newex; + pid = win32_spawn (newex, FALSE, argv, env, + dwCreationFlags, si, pi); + free ((char *) newex); + } + } + } +#endif + free (avhere); + } + } + } + if (pid == (pid_t) -1) + errno = save_errno; + return pid; +} + +/* Execute a child. */ + +static pid_t +pex_win32_exec_child (struct pex_obj *obj ATTRIBUTE_UNUSED, int flags, + const char *executable, char * const * argv, + char* const* env, + int in, int out, int errdes, + int toclose ATTRIBUTE_UNUSED, + const char **errmsg, + int *err) +{ + pid_t pid; + HANDLE stdin_handle; + HANDLE stdout_handle; + HANDLE stderr_handle; + DWORD dwCreationFlags; + OSVERSIONINFO version_info; + STARTUPINFO si; + PROCESS_INFORMATION pi; + int orig_out, orig_in, orig_err; + BOOL separate_stderr = !(flags & PEX_STDERR_TO_STDOUT); + + /* Ensure we have inheritable descriptors to pass to the child, and close the + original descriptors. */ + orig_in = in; + in = _dup (orig_in); + if (orig_in != STDIN_FILENO) + _close (orig_in); + + orig_out = out; + out = _dup (orig_out); + if (orig_out != STDOUT_FILENO) + _close (orig_out); + + if (separate_stderr) + { + orig_err = errdes; + errdes = _dup (orig_err); + if (orig_err != STDERR_FILENO) + _close (orig_err); + } + + stdin_handle = INVALID_HANDLE_VALUE; + stdout_handle = INVALID_HANDLE_VALUE; + stderr_handle = INVALID_HANDLE_VALUE; + + stdin_handle = (HANDLE) _get_osfhandle (in); + stdout_handle = (HANDLE) _get_osfhandle (out); + if (separate_stderr) + stderr_handle = (HANDLE) _get_osfhandle (errdes); + else + stderr_handle = stdout_handle; + + /* Determine the version of Windows we are running on. */ + version_info.dwOSVersionInfoSize = sizeof (version_info); + GetVersionEx (&version_info); + if (version_info.dwPlatformId == VER_PLATFORM_WIN32_WINDOWS) + /* On Windows 95/98/ME the CREATE_NO_WINDOW flag is not + supported, so we cannot avoid creating a console window. */ + dwCreationFlags = 0; + else + { + HANDLE conout_handle; + + /* Determine whether or not we have an associated console. */ + conout_handle = CreateFile("CONOUT$", + GENERIC_WRITE, + FILE_SHARE_WRITE, + /*lpSecurityAttributes=*/NULL, + OPEN_EXISTING, + FILE_ATTRIBUTE_NORMAL, + /*hTemplateFile=*/NULL); + if (conout_handle == INVALID_HANDLE_VALUE) + /* There is no console associated with this process. Since + the child is a console process, the OS would normally + create a new console Window for the child. Since we'll be + redirecting the child's standard streams, we do not need + the console window. */ + dwCreationFlags = CREATE_NO_WINDOW; + else + { + /* There is a console associated with the process, so the OS + will not create a new console. And, if we use + CREATE_NO_WINDOW in this situation, the child will have + no associated console. Therefore, if the child's + standard streams are connected to the console, the output + will be discarded. */ + CloseHandle(conout_handle); + dwCreationFlags = 0; + } + } + + /* Since the child will be a console process, it will, by default, + connect standard input/output to its console. However, we want + the child to use the handles specifically designated above. In + addition, if there is no console (such as when we are running in + a Cygwin X window), then we must redirect the child's + input/output, as there is no console for the child to use. */ + memset (&si, 0, sizeof (si)); + si.cb = sizeof (si); + si.dwFlags = STARTF_USESTDHANDLES; + si.hStdInput = stdin_handle; + si.hStdOutput = stdout_handle; + si.hStdError = stderr_handle; + + /* Create the child process. */ + pid = win32_spawn (executable, (flags & PEX_SEARCH) != 0, + argv, env, dwCreationFlags, &si, &pi); + if (pid == (pid_t) -1) + pid = spawn_script (executable, argv, env, dwCreationFlags, + &si, &pi); + if (pid == (pid_t) -1) + { + *err = ENOENT; + *errmsg = "CreateProcess"; + } + + /* Close the standard input, standard output and standard error handles + in the parent. */ + + _close (in); + _close (out); + if (separate_stderr) + _close (errdes); + + return pid; +} + +/* Wait for a child process to complete. MS CRTDLL doesn't return + enough information in status to decide if the child exited due to a + signal or not, rather it simply returns an integer with the exit + code of the child; eg., if the child exited with an abort() call + and didn't have a handler for SIGABRT, it simply returns with + status == 3. We fix the status code to conform to the usual WIF* + macros. Note that WIFSIGNALED will never be true under CRTDLL. */ + +static pid_t +pex_win32_wait (struct pex_obj *obj ATTRIBUTE_UNUSED, pid_t pid, + int *status, struct pex_time *time, int done ATTRIBUTE_UNUSED, + const char **errmsg, int *err) +{ + DWORD termstat; + HANDLE h; + + if (time != NULL) + memset (time, 0, sizeof *time); + + h = (HANDLE) pid; + + /* FIXME: If done is non-zero, we should probably try to kill the + process. */ + if (WaitForSingleObject (h, INFINITE) != WAIT_OBJECT_0) + { + CloseHandle (h); + *err = ECHILD; + *errmsg = "WaitForSingleObject"; + return -1; + } + + GetExitCodeProcess (h, &termstat); + CloseHandle (h); + + /* A value of 3 indicates that the child caught a signal, but not + which one. Since only SIGABRT, SIGFPE and SIGINT do anything, we + report SIGABRT. */ + if (termstat == 3) + *status = SIGABRT; + else + *status = (termstat & 0xff) << 8; + + return 0; +} + +/* Create a pipe. */ + +static int +pex_win32_pipe (struct pex_obj *obj ATTRIBUTE_UNUSED, int *p, + int binary) +{ + return _pipe (p, 256, (binary ? _O_BINARY : _O_TEXT) | _O_NOINHERIT); +} + +/* Get a FILE pointer to read from a file descriptor. */ + +static FILE * +pex_win32_fdopenr (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd, + int binary) +{ + HANDLE h = (HANDLE) _get_osfhandle (fd); + if (h == INVALID_HANDLE_VALUE) + return NULL; + if (! SetHandleInformation (h, HANDLE_FLAG_INHERIT, 0)) + return NULL; + return fdopen (fd, binary ? "rb" : "r"); +} + +static FILE * +pex_win32_fdopenw (struct pex_obj *obj ATTRIBUTE_UNUSED, int fd, + int binary) +{ + HANDLE h = (HANDLE) _get_osfhandle (fd); + if (h == INVALID_HANDLE_VALUE) + return NULL; + if (! SetHandleInformation (h, HANDLE_FLAG_INHERIT, 0)) + return NULL; + return fdopen (fd, binary ? "wb" : "w"); +} + +#ifdef MAIN +#include + +int +main (int argc ATTRIBUTE_UNUSED, char **argv) +{ + char const *errmsg; + int err; + argv++; + printf ("%ld\n", (long) pex_win32_exec_child (NULL, PEX_SEARCH, argv[0], argv, NULL, 0, 0, 1, 2, &errmsg, &err)); + exit (0); +} +#endif diff --git a/external/gpl3/gdb/dist/libiberty/pexecute.c b/external/gpl3/gdb/dist/libiberty/pexecute.c new file mode 100644 index 000000000000..97f157447b71 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pexecute.c @@ -0,0 +1,124 @@ +/* Utilities to execute a program in a subprocess (possibly linked by pipes + with other subprocesses), and wait for it. + Copyright (C) 2004 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* pexecute is an old routine. This implementation uses the newer + pex_init/pex_run/pex_get_status/pex_free routines. Don't use + pexecute in new code. Use the newer routines instead. */ + +#include "config.h" +#include "libiberty.h" + +#ifdef HAVE_STDLIB_H +#include +#endif + +/* We only permit a single pexecute chain to execute at a time. This + was always true anyhow, though it wasn't documented. */ + +static struct pex_obj *pex; +static int idx; + +int +pexecute (const char *program, char * const *argv, const char *pname, + const char *temp_base, char **errmsg_fmt, char **errmsg_arg, + int flags) +{ + const char *errmsg; + int err; + + if ((flags & PEXECUTE_FIRST) != 0) + { + if (pex != NULL) + { + *errmsg_fmt = (char *) "pexecute already in progress"; + *errmsg_arg = NULL; + return -1; + } + pex = pex_init (PEX_USE_PIPES, pname, temp_base); + idx = 0; + } + else + { + if (pex == NULL) + { + *errmsg_fmt = (char *) "pexecute not in progress"; + *errmsg_arg = NULL; + return -1; + } + } + + errmsg = pex_run (pex, + (((flags & PEXECUTE_LAST) != 0 ? PEX_LAST : 0) + | ((flags & PEXECUTE_SEARCH) != 0 ? PEX_SEARCH : 0)), + program, argv, NULL, NULL, &err); + if (errmsg != NULL) + { + *errmsg_fmt = (char *) errmsg; + *errmsg_arg = NULL; + return -1; + } + + /* Instead of a PID, we just return a one-based index into the + status values. We avoid zero just because the old pexecute would + never return it. */ + return ++idx; +} + +int +pwait (int pid, int *status, int flags ATTRIBUTE_UNUSED) +{ + /* The PID returned by pexecute is one-based. */ + --pid; + + if (pex == NULL || pid < 0 || pid >= idx) + return -1; + + if (pid == 0 && idx == 1) + { + if (!pex_get_status (pex, 1, status)) + return -1; + } + else + { + int *vector; + + vector = XNEWVEC (int, idx); + if (!pex_get_status (pex, idx, vector)) + { + free (vector); + return -1; + } + *status = vector[pid]; + free (vector); + } + + /* Assume that we are done after the caller has retrieved the last + exit status. The original implementation did not require that + the exit statuses be retrieved in order, but this implementation + does. */ + if (pid + 1 == idx) + { + pex_free (pex); + pex = NULL; + idx = 0; + } + + return pid + 1; +} diff --git a/external/gpl3/gdb/dist/libiberty/pexecute.txh b/external/gpl3/gdb/dist/libiberty/pexecute.txh new file mode 100644 index 000000000000..c3e403856319 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/pexecute.txh @@ -0,0 +1,316 @@ +@c -*- mode: texinfo -*- +@deftypefn Extension {struct pex_obj *} pex_init (int @var{flags}, @ + const char *@var{pname}, const char *@var{tempbase}) + +Prepare to execute one or more programs, with standard output of each +program fed to standard input of the next. This is a system +independent interface to execute a pipeline. + +@var{flags} is a bitwise combination of the following: + +@table @code + +@vindex PEX_RECORD_TIMES +@item PEX_RECORD_TIMES +Record subprocess times if possible. + +@vindex PEX_USE_PIPES +@item PEX_USE_PIPES +Use pipes for communication between processes, if possible. + +@vindex PEX_SAVE_TEMPS +@item PEX_SAVE_TEMPS +Don't delete temporary files used for communication between +processes. + +@end table + +@var{pname} is the name of program to be executed, used in error +messages. @var{tempbase} is a base name to use for any required +temporary files; it may be @code{NULL} to use a randomly chosen name. + +@end deftypefn + +@deftypefn Extension {const char *} pex_run (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{executable}, char * const *@var{argv}, @ + const char *@var{outname}, const char *@var{errname}, int *@var{err}) + +Execute one program in a pipeline. On success this returns +@code{NULL}. On failure it returns an error message, a statically +allocated string. + +@var{obj} is returned by a previous call to @code{pex_init}. + +@var{flags} is a bitwise combination of the following: + +@table @code + +@vindex PEX_LAST +@item PEX_LAST +This must be set on the last program in the pipeline. In particular, +it should be set when executing a single program. The standard output +of the program will be sent to @var{outname}, or, if @var{outname} is +@code{NULL}, to the standard output of the calling program. Do @emph{not} +set this bit if you want to call @code{pex_read_output} +(described below). After a call to @code{pex_run} with this bit set, +@var{pex_run} may no longer be called with the same @var{obj}. + +@vindex PEX_SEARCH +@item PEX_SEARCH +Search for the program using the user's executable search path. + +@vindex PEX_SUFFIX +@item PEX_SUFFIX +@var{outname} is a suffix. See the description of @var{outname}, +below. + +@vindex PEX_STDERR_TO_STDOUT +@item PEX_STDERR_TO_STDOUT +Send the program's standard error to standard output, if possible. + +@vindex PEX_BINARY_INPUT +@vindex PEX_BINARY_OUTPUT +@vindex PEX_BINARY_ERROR +@item PEX_BINARY_INPUT +@itemx PEX_BINARY_OUTPUT +@itemx PEX_BINARY_ERROR +The standard input (output or error) of the program should be read (written) in +binary mode rather than text mode. These flags are ignored on systems +which do not distinguish binary mode and text mode, such as Unix. For +proper behavior these flags should match appropriately---a call to +@code{pex_run} using @code{PEX_BINARY_OUTPUT} should be followed by a +call using @code{PEX_BINARY_INPUT}. + +@vindex PEX_STDERR_TO_PIPE +@item PEX_STDERR_TO_PIPE +Send the program's standard error to a pipe, if possible. This flag +cannot be specified together with @code{PEX_STDERR_TO_STDOUT}. This +flag can be specified only on the last program in pipeline. + +@end table + +@var{executable} is the program to execute. @var{argv} is the set of +arguments to pass to the program; normally @code{@var{argv}[0]} will +be a copy of @var{executable}. + +@var{outname} is used to set the name of the file to use for standard +output. There are two cases in which no output file will be used: + +@enumerate +@item +if @code{PEX_LAST} is not set in @var{flags}, and @code{PEX_USE_PIPES} +was set in the call to @code{pex_init}, and the system supports pipes + +@item +if @code{PEX_LAST} is set in @var{flags}, and @var{outname} is +@code{NULL} +@end enumerate + +@noindent +Otherwise the code will use a file to hold standard +output. If @code{PEX_LAST} is not set, this file is considered to be +a temporary file, and it will be removed when no longer needed, unless +@code{PEX_SAVE_TEMPS} was set in the call to @code{pex_init}. + +There are two cases to consider when setting the name of the file to +hold standard output. + +@enumerate +@item +@code{PEX_SUFFIX} is set in @var{flags}. In this case +@var{outname} may not be @code{NULL}. If the @var{tempbase} parameter +to @code{pex_init} was not @code{NULL}, then the output file name is +the concatenation of @var{tempbase} and @var{outname}. If +@var{tempbase} was @code{NULL}, then the output file name is a random +file name ending in @var{outname}. + +@item +@code{PEX_SUFFIX} was not set in @var{flags}. In this +case, if @var{outname} is not @code{NULL}, it is used as the output +file name. If @var{outname} is @code{NULL}, and @var{tempbase} was +not NULL, the output file name is randomly chosen using +@var{tempbase}. Otherwise the output file name is chosen completely +at random. +@end enumerate + +@var{errname} is the file name to use for standard error output. If +it is @code{NULL}, standard error is the same as the caller's. +Otherwise, standard error is written to the named file. + +On an error return, the code sets @code{*@var{err}} to an @code{errno} +value, or to 0 if there is no relevant @code{errno}. + +@end deftypefn + +@deftypefn Extension {const char *} pex_run_in_environment (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{executable}, char * const *@var{argv}, @ + char * const *@var{env}, int @var{env_size}, const char *@var{outname}, @ + const char *@var{errname}, int *@var{err}) + +Execute one program in a pipeline, permitting the environment for the +program to be specified. Behaviour and parameters not listed below are +as for @code{pex_run}. + +@var{env} is the environment for the child process, specified as an array of +character pointers. Each element of the array should point to a string of the +form @code{VAR=VALUE}, with the exception of the last element that must be +@code{NULL}. + +@end deftypefn + +@deftypefn Extension {FILE *} pex_input_file (struct pex_obj *@var{obj}, @ + int @var{flags}, const char *@var{in_name}) + +Return a stream for a temporary file to pass to the first program in +the pipeline as input. + +The name of the input file is chosen according to the same rules +@code{pex_run} uses to choose output file names, based on +@var{in_name}, @var{obj} and the @code{PEX_SUFFIX} bit in @var{flags}. + +Don't call @code{fclose} on the returned stream; the first call to +@code{pex_run} closes it automatically. + +If @var{flags} includes @code{PEX_BINARY_OUTPUT}, open the stream in +binary mode; otherwise, open it in the default mode. Including +@code{PEX_BINARY_OUTPUT} in @var{flags} has no effect on Unix. +@end deftypefn + +@deftypefn Extension {FILE *} pex_input_pipe (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Return a stream @var{fp} for a pipe connected to the standard input of +the first program in the pipeline; @var{fp} is opened for writing. +You must have passed @code{PEX_USE_PIPES} to the @code{pex_init} call +that returned @var{obj}. + +You must close @var{fp} using @code{fclose} yourself when you have +finished writing data to the pipeline. + +The file descriptor underlying @var{fp} is marked not to be inherited +by child processes. + +On systems that do not support pipes, this function returns +@code{NULL}, and sets @code{errno} to @code{EINVAL}. If you would +like to write code that is portable to all systems the @code{pex} +functions support, consider using @code{pex_input_file} instead. + +There are two opportunities for deadlock using +@code{pex_input_pipe}: + +@itemize @bullet +@item +Most systems' pipes can buffer only a fixed amount of data; a process +that writes to a full pipe blocks. Thus, if you write to @file{fp} +before starting the first process, you run the risk of blocking when +there is no child process yet to read the data and allow you to +continue. @code{pex_input_pipe} makes no promises about the +size of the pipe's buffer, so if you need to write any data at all +before starting the first process in the pipeline, consider using +@code{pex_input_file} instead. + +@item +Using @code{pex_input_pipe} and @code{pex_read_output} together +may also cause deadlock. If the output pipe fills up, so that each +program in the pipeline is waiting for the next to read more data, and +you fill the input pipe by writing more data to @var{fp}, then there +is no way to make progress: the only process that could read data from +the output pipe is you, but you are blocked on the input pipe. + +@end itemize + +@end deftypefn + +@deftypefn Extension {FILE *} pex_read_output (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Returns a @code{FILE} pointer which may be used to read the standard +output of the last program in the pipeline. When this is used, +@code{PEX_LAST} should not be used in a call to @code{pex_run}. After +this is called, @code{pex_run} may no longer be called with the same +@var{obj}. @var{binary} should be non-zero if the file should be +opened in binary mode. Don't call @code{fclose} on the returned file; +it will be closed by @code{pex_free}. + +@end deftypefn + +@deftypefn Extension {FILE *} pex_read_err (struct pex_obj *@var{obj}, @ + int @var{binary}) + +Returns a @code{FILE} pointer which may be used to read the standard +error of the last program in the pipeline. When this is used, +@code{PEX_LAST} should not be used in a call to @code{pex_run}. After +this is called, @code{pex_run} may no longer be called with the same +@var{obj}. @var{binary} should be non-zero if the file should be +opened in binary mode. Don't call @code{fclose} on the returned file; +it will be closed by @code{pex_free}. + +@end deftypefn + + +@deftypefn Extension int pex_get_status (struct pex_obj *@var{obj}, @ + int @var{count}, int *@var{vector}) + +Returns the exit status of all programs run using @var{obj}. +@var{count} is the number of results expected. The results will be +placed into @var{vector}. The results are in the order of the calls +to @code{pex_run}. Returns 0 on error, 1 on success. + +@end deftypefn + +@deftypefn Extension int pex_get_times (struct pex_obj *@var{obj}, @ + int @var{count}, struct pex_time *@var{vector}) + +Returns the process execution times of all programs run using +@var{obj}. @var{count} is the number of results expected. The +results will be placed into @var{vector}. The results are in the +order of the calls to @code{pex_run}. Returns 0 on error, 1 on +success. + +@code{struct pex_time} has the following fields of the type +@code{unsigned long}: @code{user_seconds}, +@code{user_microseconds}, @code{system_seconds}, +@code{system_microseconds}. On systems which do not support reporting +process times, all the fields will be set to @code{0}. + +@end deftypefn + +@deftypefn Extension void pex_free (struct pex_obj @var{obj}) + +Clean up and free all data associated with @var{obj}. If you have not +yet called @code{pex_get_times} or @code{pex_get_status}, this will +try to kill the subprocesses. + +@end deftypefn + +@deftypefn Extension {const char *} pex_one (int @var{flags}, @ + const char *@var{executable}, char * const *@var{argv}, @ + const char *@var{pname}, const char *@var{outname}, const char *@var{errname}, @ + int *@var{status}, int *@var{err}) + +An interface to permit the easy execution of a +single program. The return value and most of the parameters are as +for a call to @code{pex_run}. @var{flags} is restricted to a +combination of @code{PEX_SEARCH}, @code{PEX_STDERR_TO_STDOUT}, and +@code{PEX_BINARY_OUTPUT}. @var{outname} is interpreted as if +@code{PEX_LAST} were set. On a successful return, @code{*@var{status}} will +be set to the exit status of the program. + +@end deftypefn + +@deftypefn Extension int pexecute (const char *@var{program}, @ + char * const *@var{argv}, const char *@var{this_pname}, @ + const char *@var{temp_base}, char **@var{errmsg_fmt}, @ + char **@var{errmsg_arg}, int @var{flags}) + +This is the old interface to execute one or more programs. It is +still supported for compatibility purposes, but is no longer +documented. + +@end deftypefn + +@deftypefn Extension int pwait (int @var{pid}, int *@var{status}, int @var{flags}) + +Another part of the old execution interface. + +@end deftypefn diff --git a/external/gpl3/gdb/dist/libiberty/physmem.c b/external/gpl3/gdb/dist/libiberty/physmem.c new file mode 100644 index 000000000000..09fbf3f8c83e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/physmem.c @@ -0,0 +1,305 @@ +/* Calculate the size of physical memory. + Copyright 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Written by Paul Eggert. */ + +#if HAVE_CONFIG_H +# include +#endif + +#if HAVE_UNISTD_H +# include +#endif + +#if HAVE_SYS_PSTAT_H +# include +#endif + +#if HAVE_SYS_SYSMP_H +# include +#endif + +#if HAVE_SYS_SYSINFO_H && HAVE_MACHINE_HAL_SYSINFO_H +# include +# include +#endif + +#if HAVE_SYS_TABLE_H +# include +#endif + +#include + +#if HAVE_SYS_PARAM_H +# include +#endif + +#if HAVE_SYS_SYSCTL_H +# include +#endif + +#if HAVE_SYS_SYSTEMCFG_H +# include +#endif + +#ifdef _WIN32 +# define WIN32_LEAN_AND_MEAN +# include +/* MEMORYSTATUSEX is missing from older windows headers, so define + a local replacement. */ +typedef struct +{ + DWORD dwLength; + DWORD dwMemoryLoad; + DWORDLONG ullTotalPhys; + DWORDLONG ullAvailPhys; + DWORDLONG ullTotalPageFile; + DWORDLONG ullAvailPageFile; + DWORDLONG ullTotalVirtual; + DWORDLONG ullAvailVirtual; + DWORDLONG ullAvailExtendedVirtual; +} lMEMORYSTATUSEX; +typedef WINBOOL (WINAPI *PFN_MS_EX) (lMEMORYSTATUSEX*); +#endif + +#include "libiberty.h" + +/* Return the total amount of physical memory. */ +double +physmem_total (void) +{ +#if defined _SC_PHYS_PAGES && defined _SC_PAGESIZE + { /* This works on linux-gnu, solaris2 and cygwin. */ + double pages = sysconf (_SC_PHYS_PAGES); + double pagesize = sysconf (_SC_PAGESIZE); + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } +#endif + +#if HAVE_PSTAT_GETSTATIC + { /* This works on hpux11. */ + struct pst_static pss; + if (0 <= pstat_getstatic (&pss, sizeof pss, 1, 0)) + { + double pages = pss.physical_memory; + double pagesize = pss.page_size; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSMP && defined MP_SAGET && defined MPSA_RMINFO && defined _SC_PAGESIZE + { /* This works on irix6. */ + struct rminfo realmem; + if (sysmp (MP_SAGET, MPSA_RMINFO, &realmem, sizeof realmem) == 0) + { + double pagesize = sysconf (_SC_PAGESIZE); + double pages = realmem.physmem; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_GETSYSINFO && defined GSI_PHYSMEM + { /* This works on Tru64 UNIX V4/5. */ + int physmem; + + if (getsysinfo (GSI_PHYSMEM, (caddr_t) &physmem, sizeof (physmem), + NULL, NULL, NULL) == 1) + { + double kbytes = physmem; + + if (0 <= kbytes) + return kbytes * 1024.0; + } + } +#endif + +#if HAVE_SYSCTL && defined HW_PHYSMEM + { /* This works on *bsd and darwin. */ + unsigned int physmem; + size_t len = sizeof physmem; + static int mib[2] = { CTL_HW, HW_PHYSMEM }; + + if (sysctl (mib, ARRAY_SIZE (mib), &physmem, &len, NULL, 0) == 0 + && len == sizeof (physmem)) + return (double) physmem; + } +#endif + +#if HAVE__SYSTEM_CONFIGURATION + /* This works on AIX 4.3.3+. */ + return _system_configuration.physmem; +#endif + +#if defined _WIN32 + { /* this works on windows */ + PFN_MS_EX pfnex; + HMODULE h = GetModuleHandle ("kernel32.dll"); + + if (!h) + return 0.0; + + /* Use GlobalMemoryStatusEx if available. */ + if ((pfnex = (PFN_MS_EX) GetProcAddress (h, "GlobalMemoryStatusEx"))) + { + lMEMORYSTATUSEX lms_ex; + lms_ex.dwLength = sizeof lms_ex; + if (!pfnex (&lms_ex)) + return 0.0; + return (double) lms_ex.ullTotalPhys; + } + + /* Fall back to GlobalMemoryStatus which is always available. + but returns wrong results for physical memory > 4GB. */ + else + { + MEMORYSTATUS ms; + GlobalMemoryStatus (&ms); + return (double) ms.dwTotalPhys; + } + } +#endif + + /* Return 0 if we can't determine the value. */ + return 0; +} + +/* Return the amount of physical memory available. */ +double +physmem_available (void) +{ +#if defined _SC_AVPHYS_PAGES && defined _SC_PAGESIZE + { /* This works on linux-gnu, solaris2 and cygwin. */ + double pages = sysconf (_SC_AVPHYS_PAGES); + double pagesize = sysconf (_SC_PAGESIZE); + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } +#endif + +#if HAVE_PSTAT_GETSTATIC && HAVE_PSTAT_GETDYNAMIC + { /* This works on hpux11. */ + struct pst_static pss; + struct pst_dynamic psd; + if (0 <= pstat_getstatic (&pss, sizeof pss, 1, 0) + && 0 <= pstat_getdynamic (&psd, sizeof psd, 1, 0)) + { + double pages = psd.psd_free; + double pagesize = pss.page_size; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSMP && defined MP_SAGET && defined MPSA_RMINFO && defined _SC_PAGESIZE + { /* This works on irix6. */ + struct rminfo realmem; + if (sysmp (MP_SAGET, MPSA_RMINFO, &realmem, sizeof realmem) == 0) + { + double pagesize = sysconf (_SC_PAGESIZE); + double pages = realmem.availrmem; + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_TABLE && defined TBL_VMSTATS + { /* This works on Tru64 UNIX V4/5. */ + struct tbl_vmstats vmstats; + + if (table (TBL_VMSTATS, 0, &vmstats, 1, sizeof (vmstats)) == 1) + { + double pages = vmstats.free_count; + double pagesize = vmstats.pagesize; + + if (0 <= pages && 0 <= pagesize) + return pages * pagesize; + } + } +#endif + +#if HAVE_SYSCTL && defined HW_USERMEM + { /* This works on *bsd and darwin. */ + unsigned int usermem; + size_t len = sizeof usermem; + static int mib[2] = { CTL_HW, HW_USERMEM }; + + if (sysctl (mib, ARRAY_SIZE (mib), &usermem, &len, NULL, 0) == 0 + && len == sizeof (usermem)) + return (double) usermem; + } +#endif + +#if defined _WIN32 + { /* this works on windows */ + PFN_MS_EX pfnex; + HMODULE h = GetModuleHandle ("kernel32.dll"); + + if (!h) + return 0.0; + + /* Use GlobalMemoryStatusEx if available. */ + if ((pfnex = (PFN_MS_EX) GetProcAddress (h, "GlobalMemoryStatusEx"))) + { + lMEMORYSTATUSEX lms_ex; + lms_ex.dwLength = sizeof lms_ex; + if (!pfnex (&lms_ex)) + return 0.0; + return (double) lms_ex.ullAvailPhys; + } + + /* Fall back to GlobalMemoryStatus which is always available. + but returns wrong results for physical memory > 4GB */ + else + { + MEMORYSTATUS ms; + GlobalMemoryStatus (&ms); + return (double) ms.dwAvailPhys; + } + } +#endif + + /* Guess 25% of physical memory. */ + return physmem_total () / 4; +} + + +#if DEBUG + +# include +# include + +int +main (void) +{ + printf ("%12.f %12.f\n", physmem_total (), physmem_available ()); + exit (0); +} + +#endif /* DEBUG */ + +/* +Local Variables: +compile-command: "gcc -DDEBUG -DHAVE_CONFIG_H -I.. -g -O -Wall -W physmem.c" +End: +*/ diff --git a/external/gpl3/gdb/dist/libiberty/putenv.c b/external/gpl3/gdb/dist/libiberty/putenv.c new file mode 100644 index 000000000000..248f50e92033 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/putenv.c @@ -0,0 +1,84 @@ +/* Copyright (C) 1991, 1994, 1995, 1996, 2002 Free Software Foundation, Inc. + This file based on putenv.c in the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Supplemental int putenv (const char *@var{string}) + +Uses @code{setenv} or @code{unsetenv} to put @var{string} into +the environment or remove it. If @var{string} is of the form +@samp{name=value} the string is added; if no @samp{=} is present the +name is unset/removed. + +@end deftypefn + +*/ + +#if defined (_AIX) && !defined (__GNUC__) + #pragma alloca +#endif + +#if HAVE_CONFIG_H +# include +#endif + +#include "ansidecl.h" + +#define putenv libiberty_putenv + +#if HAVE_STDLIB_H +# include +#endif +#if HAVE_STRING_H +# include +#endif + +#ifdef HAVE_ALLOCA_H +# include +#else +# ifndef alloca +# ifdef __GNUC__ +# define alloca __builtin_alloca +# else +extern char *alloca (); +# endif /* __GNUC__ */ +# endif /* alloca */ +#endif /* HAVE_ALLOCA_H */ + +#undef putenv + +/* Below this point, it's verbatim code from the glibc-2.0 implementation */ + + +/* Put STRING, which is of the form "NAME=VALUE", in the environment. */ +int +putenv (const char *string) +{ + const char *const name_end = strchr (string, '='); + + if (name_end) + { + char *name = (char *) alloca (name_end - string + 1); + memcpy (name, string, name_end - string); + name[name_end - string] = '\0'; + return setenv (name, name_end + 1, 1); + } + + unsetenv (string); + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/random.c b/external/gpl3/gdb/dist/libiberty/random.c new file mode 100644 index 000000000000..b1d3c6c6ae44 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/random.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 1983 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. [rescinded 22 July 1999] + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * This is derived from the Berkeley source: + * @(#)random.c 5.5 (Berkeley) 7/6/88 + * It was reworked for the GNU C Library by Roland McGrath. + */ + +/* + +@deftypefn Supplement {long int} random (void) +@deftypefnx Supplement void srandom (unsigned int @var{seed}) +@deftypefnx Supplement void* initstate (unsigned int @var{seed}, @ + void *@var{arg_state}, unsigned long @var{n}) +@deftypefnx Supplement void* setstate (void *@var{arg_state}) + +Random number functions. @code{random} returns a random number in the +range 0 to @code{LONG_MAX}. @code{srandom} initializes the random +number generator to some starting point determined by @var{seed} +(else, the values returned by @code{random} are always the same for each +run of the program). @code{initstate} and @code{setstate} allow fine-grained +control over the state of the random number generator. + +@end deftypefn + +*/ + +#include + +#if 0 + +#include +#include +#include +#include + +#else + +#define ULONG_MAX ((unsigned long)(~0L)) /* 0xFFFFFFFF for 32-bits */ +#define LONG_MAX ((long)(ULONG_MAX >> 1)) /* 0x7FFFFFFF for 32-bits*/ + +#ifdef __STDC__ +# define PTR void * +# ifndef NULL +# define NULL (void *) 0 +# endif +#else +# define PTR char * +# ifndef NULL +# define NULL (void *) 0 +# endif +#endif + +#endif + +long int random (void); + +/* An improved random number generation package. In addition to the standard + rand()/srand() like interface, this package also has a special state info + interface. The initstate() routine is called with a seed, an array of + bytes, and a count of how many bytes are being passed in; this array is + then initialized to contain information for random number generation with + that much state information. Good sizes for the amount of state + information are 32, 64, 128, and 256 bytes. The state can be switched by + calling the setstate() function with the same array as was initiallized + with initstate(). By default, the package runs with 128 bytes of state + information and generates far better random numbers than a linear + congruential generator. If the amount of state information is less than + 32 bytes, a simple linear congruential R.N.G. is used. Internally, the + state information is treated as an array of longs; the zeroeth element of + the array is the type of R.N.G. being used (small integer); the remainder + of the array is the state information for the R.N.G. Thus, 32 bytes of + state information will give 7 longs worth of state information, which will + allow a degree seven polynomial. (Note: The zeroeth word of state + information also has some other information stored in it; see setstate + for details). The random number generation technique is a linear feedback + shift register approach, employing trinomials (since there are fewer terms + to sum up that way). In this approach, the least significant bit of all + the numbers in the state table will act as a linear feedback shift register, + and will have period 2^deg - 1 (where deg is the degree of the polynomial + being used, assuming that the polynomial is irreducible and primitive). + The higher order bits will have longer periods, since their values are + also influenced by pseudo-random carries out of the lower bits. The + total period of the generator is approximately deg*(2**deg - 1); thus + doubling the amount of state information has a vast influence on the + period of the generator. Note: The deg*(2**deg - 1) is an approximation + only good for large deg, when the period of the shift register is the + dominant factor. With deg equal to seven, the period is actually much + longer than the 7*(2**7 - 1) predicted by this formula. */ + + + +/* For each of the currently supported random number generators, we have a + break value on the amount of state information (you need at least thi + bytes of state info to support this random number generator), a degree for + the polynomial (actually a trinomial) that the R.N.G. is based on, and + separation between the two lower order coefficients of the trinomial. */ + +/* Linear congruential. */ +#define TYPE_0 0 +#define BREAK_0 8 +#define DEG_0 0 +#define SEP_0 0 + +/* x**7 + x**3 + 1. */ +#define TYPE_1 1 +#define BREAK_1 32 +#define DEG_1 7 +#define SEP_1 3 + +/* x**15 + x + 1. */ +#define TYPE_2 2 +#define BREAK_2 64 +#define DEG_2 15 +#define SEP_2 1 + +/* x**31 + x**3 + 1. */ +#define TYPE_3 3 +#define BREAK_3 128 +#define DEG_3 31 +#define SEP_3 3 + +/* x**63 + x + 1. */ +#define TYPE_4 4 +#define BREAK_4 256 +#define DEG_4 63 +#define SEP_4 1 + + +/* Array versions of the above information to make code run faster. + Relies on fact that TYPE_i == i. */ + +#define MAX_TYPES 5 /* Max number of types above. */ + +static int degrees[MAX_TYPES] = { DEG_0, DEG_1, DEG_2, DEG_3, DEG_4 }; +static int seps[MAX_TYPES] = { SEP_0, SEP_1, SEP_2, SEP_3, SEP_4 }; + + + +/* Initially, everything is set up as if from: + initstate(1, randtbl, 128); + Note that this initialization takes advantage of the fact that srandom + advances the front and rear pointers 10*rand_deg times, and hence the + rear pointer which starts at 0 will also end up at zero; thus the zeroeth + element of the state information, which contains info about the current + position of the rear pointer is just + (MAX_TYPES * (rptr - state)) + TYPE_3 == TYPE_3. */ + +static long int randtbl[DEG_3 + 1] = + { TYPE_3, + 0x9a319039, 0x32d9c024, 0x9b663182, 0x5da1f342, + 0xde3b81e0, 0xdf0a6fb5, 0xf103bc02, 0x48f340fb, + 0x7449e56b, 0xbeb1dbb0, 0xab5c5918, 0x946554fd, + 0x8c2e680f, 0xeb3d799f, 0xb11ee0b7, 0x2d436b86, + 0xda672e2a, 0x1588ca88, 0xe369735d, 0x904f35f7, + 0xd7158fd6, 0x6fa6f051, 0x616e6b96, 0xac94efdc, + 0x36413f93, 0xc622c298, 0xf5a42ab8, 0x8a88d77b, + 0xf5ad9d0e, 0x8999220b, 0x27fb47b9 + }; + +/* FPTR and RPTR are two pointers into the state info, a front and a rear + pointer. These two pointers are always rand_sep places aparts, as they + cycle through the state information. (Yes, this does mean we could get + away with just one pointer, but the code for random is more efficient + this way). The pointers are left positioned as they would be from the call: + initstate(1, randtbl, 128); + (The position of the rear pointer, rptr, is really 0 (as explained above + in the initialization of randtbl) because the state table pointer is set + to point to randtbl[1] (as explained below).) */ + +static long int *fptr = &randtbl[SEP_3 + 1]; +static long int *rptr = &randtbl[1]; + + + +/* The following things are the pointer to the state information table, + the type of the current generator, the degree of the current polynomial + being used, and the separation between the two pointers. + Note that for efficiency of random, we remember the first location of + the state information, not the zeroeth. Hence it is valid to access + state[-1], which is used to store the type of the R.N.G. + Also, we remember the last location, since this is more efficient than + indexing every time to find the address of the last element to see if + the front and rear pointers have wrapped. */ + +static long int *state = &randtbl[1]; + +static int rand_type = TYPE_3; +static int rand_deg = DEG_3; +static int rand_sep = SEP_3; + +static long int *end_ptr = &randtbl[sizeof(randtbl) / sizeof(randtbl[0])]; + +/* Initialize the random number generator based on the given seed. If the + type is the trivial no-state-information type, just remember the seed. + Otherwise, initializes state[] based on the given "seed" via a linear + congruential generator. Then, the pointers are set to known locations + that are exactly rand_sep places apart. Lastly, it cycles the state + information a given number of times to get rid of any initial dependencies + introduced by the L.C.R.N.G. Note that the initialization of randtbl[] + for default usage relies on values produced by this routine. */ +void +srandom (unsigned int x) +{ + state[0] = x; + if (rand_type != TYPE_0) + { + register long int i; + for (i = 1; i < rand_deg; ++i) + state[i] = (1103515145 * state[i - 1]) + 12345; + fptr = &state[rand_sep]; + rptr = &state[0]; + for (i = 0; i < 10 * rand_deg; ++i) + random(); + } +} + +/* Initialize the state information in the given array of N bytes for + future random number generation. Based on the number of bytes we + are given, and the break values for the different R.N.G.'s, we choose + the best (largest) one we can and set things up for it. srandom is + then called to initialize the state information. Note that on return + from srandom, we set state[-1] to be the type multiplexed with the current + value of the rear pointer; this is so successive calls to initstate won't + lose this information and will be able to restart with setstate. + Note: The first thing we do is save the current state, if any, just like + setstate so that it doesn't matter when initstate is called. + Returns a pointer to the old state. */ +PTR +initstate (unsigned int seed, PTR arg_state, unsigned long n) +{ + PTR ostate = (PTR) &state[-1]; + + if (rand_type == TYPE_0) + state[-1] = rand_type; + else + state[-1] = (MAX_TYPES * (rptr - state)) + rand_type; + if (n < BREAK_1) + { + if (n < BREAK_0) + { + errno = EINVAL; + return NULL; + } + rand_type = TYPE_0; + rand_deg = DEG_0; + rand_sep = SEP_0; + } + else if (n < BREAK_2) + { + rand_type = TYPE_1; + rand_deg = DEG_1; + rand_sep = SEP_1; + } + else if (n < BREAK_3) + { + rand_type = TYPE_2; + rand_deg = DEG_2; + rand_sep = SEP_2; + } + else if (n < BREAK_4) + { + rand_type = TYPE_3; + rand_deg = DEG_3; + rand_sep = SEP_3; + } + else + { + rand_type = TYPE_4; + rand_deg = DEG_4; + rand_sep = SEP_4; + } + + state = &((long int *) arg_state)[1]; /* First location. */ + /* Must set END_PTR before srandom. */ + end_ptr = &state[rand_deg]; + srandom(seed); + if (rand_type == TYPE_0) + state[-1] = rand_type; + else + state[-1] = (MAX_TYPES * (rptr - state)) + rand_type; + + return ostate; +} + +/* Restore the state from the given state array. + Note: It is important that we also remember the locations of the pointers + in the current state information, and restore the locations of the pointers + from the old state information. This is done by multiplexing the pointer + location into the zeroeth word of the state information. Note that due + to the order in which things are done, it is OK to call setstate with the + same state as the current state + Returns a pointer to the old state information. */ + +PTR +setstate (PTR arg_state) +{ + register long int *new_state = (long int *) arg_state; + register int type = new_state[0] % MAX_TYPES; + register int rear = new_state[0] / MAX_TYPES; + PTR ostate = (PTR) &state[-1]; + + if (rand_type == TYPE_0) + state[-1] = rand_type; + else + state[-1] = (MAX_TYPES * (rptr - state)) + rand_type; + + switch (type) + { + case TYPE_0: + case TYPE_1: + case TYPE_2: + case TYPE_3: + case TYPE_4: + rand_type = type; + rand_deg = degrees[type]; + rand_sep = seps[type]; + break; + default: + /* State info munged. */ + errno = EINVAL; + return NULL; + } + + state = &new_state[1]; + if (rand_type != TYPE_0) + { + rptr = &state[rear]; + fptr = &state[(rear + rand_sep) % rand_deg]; + } + /* Set end_ptr too. */ + end_ptr = &state[rand_deg]; + + return ostate; +} + +/* If we are using the trivial TYPE_0 R.N.G., just do the old linear + congruential bit. Otherwise, we do our fancy trinomial stuff, which is the + same in all ther other cases due to all the global variables that have been + set up. The basic operation is to add the number at the rear pointer into + the one at the front pointer. Then both pointers are advanced to the next + location cyclically in the table. The value returned is the sum generated, + reduced to 31 bits by throwing away the "least random" low bit. + Note: The code takes advantage of the fact that both the front and + rear pointers can't wrap on the same call by not testing the rear + pointer if the front one has wrapped. Returns a 31-bit random number. */ + +long int +random (void) +{ + if (rand_type == TYPE_0) + { + state[0] = ((state[0] * 1103515245) + 12345) & LONG_MAX; + return state[0]; + } + else + { + long int i; + *fptr += *rptr; + /* Chucking least random bit. */ + i = (*fptr >> 1) & LONG_MAX; + ++fptr; + if (fptr >= end_ptr) + { + fptr = state; + ++rptr; + } + else + { + ++rptr; + if (rptr >= end_ptr) + rptr = state; + } + return i; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/regex.c b/external/gpl3/gdb/dist/libiberty/regex.c new file mode 100644 index 000000000000..420c7f4a47da --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/regex.c @@ -0,0 +1,8205 @@ +/* Extended regular expression matching and search library, + version 0.12. + (Implements POSIX draft P1003.2/D11.2, except for some of the + internationalization features.) + + Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, + 2002, 2005, 2010 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. */ + +/* This file has been modified for usage in libiberty. It includes "xregex.h" + instead of . The "xregex.h" header file renames all external + routines with an "x" prefix so they do not collide with the native regex + routines or with other components regex routines. */ +/* AIX requires this to be the first thing in the file. */ +#if defined _AIX && !defined __GNUC__ && !defined REGEX_MALLOC + #pragma alloca +#endif + +#undef _GNU_SOURCE +#define _GNU_SOURCE + +#ifndef INSIDE_RECURSION +# ifdef HAVE_CONFIG_H +# include +# endif +#endif + +#include + +#ifndef INSIDE_RECURSION + +# if defined STDC_HEADERS && !defined emacs +# include +# else +/* We need this for `regex.h', and perhaps for the Emacs include files. */ +# include +# endif + +# define WIDE_CHAR_SUPPORT (HAVE_WCTYPE_H && HAVE_WCHAR_H && HAVE_BTOWC) + +/* For platform which support the ISO C amendement 1 functionality we + support user defined character classes. */ +# if defined _LIBC || WIDE_CHAR_SUPPORT +/* Solaris 2.5 has a bug: must be included before . */ +# include +# include +# endif + +# ifdef _LIBC +/* We have to keep the namespace clean. */ +# define regfree(preg) __regfree (preg) +# define regexec(pr, st, nm, pm, ef) __regexec (pr, st, nm, pm, ef) +# define regcomp(preg, pattern, cflags) __regcomp (preg, pattern, cflags) +# define regerror(errcode, preg, errbuf, errbuf_size) \ + __regerror(errcode, preg, errbuf, errbuf_size) +# define re_set_registers(bu, re, nu, st, en) \ + __re_set_registers (bu, re, nu, st, en) +# define re_match_2(bufp, string1, size1, string2, size2, pos, regs, stop) \ + __re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop) +# define re_match(bufp, string, size, pos, regs) \ + __re_match (bufp, string, size, pos, regs) +# define re_search(bufp, string, size, startpos, range, regs) \ + __re_search (bufp, string, size, startpos, range, regs) +# define re_compile_pattern(pattern, length, bufp) \ + __re_compile_pattern (pattern, length, bufp) +# define re_set_syntax(syntax) __re_set_syntax (syntax) +# define re_search_2(bufp, st1, s1, st2, s2, startpos, range, regs, stop) \ + __re_search_2 (bufp, st1, s1, st2, s2, startpos, range, regs, stop) +# define re_compile_fastmap(bufp) __re_compile_fastmap (bufp) + +# define btowc __btowc + +/* We are also using some library internals. */ +# include +# include +# include +# include +# endif + +/* This is for other GNU distributions with internationalized messages. */ +# if (HAVE_LIBINTL_H && ENABLE_NLS) || defined _LIBC +# include +# ifdef _LIBC +# undef gettext +# define gettext(msgid) __dcgettext ("libc", msgid, LC_MESSAGES) +# endif +# else +# define gettext(msgid) (msgid) +# endif + +# ifndef gettext_noop +/* This define is so xgettext can find the internationalizable + strings. */ +# define gettext_noop(String) String +# endif + +/* The `emacs' switch turns on certain matching commands + that make sense only in Emacs. */ +# ifdef emacs + +# include "lisp.h" +# include "buffer.h" +# include "syntax.h" + +# else /* not emacs */ + +/* If we are not linking with Emacs proper, + we can't use the relocating allocator + even if config.h says that we can. */ +# undef REL_ALLOC + +# if defined STDC_HEADERS || defined _LIBC +# include +# else +char *malloc (); +char *realloc (); +# endif + +/* When used in Emacs's lib-src, we need to get bzero and bcopy somehow. + If nothing else has been done, use the method below. */ +# ifdef INHIBIT_STRING_HEADER +# if !(defined HAVE_BZERO && defined HAVE_BCOPY) +# if !defined bzero && !defined bcopy +# undef INHIBIT_STRING_HEADER +# endif +# endif +# endif + +/* This is the normal way of making sure we have a bcopy and a bzero. + This is used in most programs--a few other programs avoid this + by defining INHIBIT_STRING_HEADER. */ +# ifndef INHIBIT_STRING_HEADER +# if defined HAVE_STRING_H || defined STDC_HEADERS || defined _LIBC +# include +# ifndef bzero +# ifndef _LIBC +# define bzero(s, n) (memset (s, '\0', n), (s)) +# else +# define bzero(s, n) __bzero (s, n) +# endif +# endif +# else +# include +# ifndef memcmp +# define memcmp(s1, s2, n) bcmp (s1, s2, n) +# endif +# ifndef memcpy +# define memcpy(d, s, n) (bcopy (s, d, n), (d)) +# endif +# endif +# endif + +/* Define the syntax stuff for \<, \>, etc. */ + +/* This must be nonzero for the wordchar and notwordchar pattern + commands in re_match_2. */ +# ifndef Sword +# define Sword 1 +# endif + +# ifdef SWITCH_ENUM_BUG +# define SWITCH_ENUM_CAST(x) ((int)(x)) +# else +# define SWITCH_ENUM_CAST(x) (x) +# endif + +# endif /* not emacs */ + +# if defined _LIBC || HAVE_LIMITS_H +# include +# endif + +# ifndef MB_LEN_MAX +# define MB_LEN_MAX 1 +# endif + +/* Get the interface, including the syntax bits. */ +# include "xregex.h" /* change for libiberty */ + +/* isalpha etc. are used for the character classes. */ +# include + +/* Jim Meyering writes: + + "... Some ctype macros are valid only for character codes that + isascii says are ASCII (SGI's IRIX-4.0.5 is one such system --when + using /bin/cc or gcc but without giving an ansi option). So, all + ctype uses should be through macros like ISPRINT... If + STDC_HEADERS is defined, then autoconf has verified that the ctype + macros don't need to be guarded with references to isascii. ... + Defining isascii to 1 should let any compiler worth its salt + eliminate the && through constant folding." + Solaris defines some of these symbols so we must undefine them first. */ + +# undef ISASCII +# if defined STDC_HEADERS || (!defined isascii && !defined HAVE_ISASCII) +# define ISASCII(c) 1 +# else +# define ISASCII(c) isascii(c) +# endif + +# ifdef isblank +# define ISBLANK(c) (ISASCII (c) && isblank (c)) +# else +# define ISBLANK(c) ((c) == ' ' || (c) == '\t') +# endif +# ifdef isgraph +# define ISGRAPH(c) (ISASCII (c) && isgraph (c)) +# else +# define ISGRAPH(c) (ISASCII (c) && isprint (c) && !isspace (c)) +# endif + +# undef ISPRINT +# define ISPRINT(c) (ISASCII (c) && isprint (c)) +# define ISDIGIT(c) (ISASCII (c) && isdigit (c)) +# define ISALNUM(c) (ISASCII (c) && isalnum (c)) +# define ISALPHA(c) (ISASCII (c) && isalpha (c)) +# define ISCNTRL(c) (ISASCII (c) && iscntrl (c)) +# define ISLOWER(c) (ISASCII (c) && islower (c)) +# define ISPUNCT(c) (ISASCII (c) && ispunct (c)) +# define ISSPACE(c) (ISASCII (c) && isspace (c)) +# define ISUPPER(c) (ISASCII (c) && isupper (c)) +# define ISXDIGIT(c) (ISASCII (c) && isxdigit (c)) + +# ifdef _tolower +# define TOLOWER(c) _tolower(c) +# else +# define TOLOWER(c) tolower(c) +# endif + +# ifndef NULL +# define NULL (void *)0 +# endif + +/* We remove any previous definition of `SIGN_EXTEND_CHAR', + since ours (we hope) works properly with all combinations of + machines, compilers, `char' and `unsigned char' argument types. + (Per Bothner suggested the basic approach.) */ +# undef SIGN_EXTEND_CHAR +# if __STDC__ +# define SIGN_EXTEND_CHAR(c) ((signed char) (c)) +# else /* not __STDC__ */ +/* As in Harbison and Steele. */ +# define SIGN_EXTEND_CHAR(c) ((((unsigned char) (c)) ^ 128) - 128) +# endif + +# ifndef emacs +/* How many characters in the character set. */ +# define CHAR_SET_SIZE 256 + +# ifdef SYNTAX_TABLE + +extern char *re_syntax_table; + +# else /* not SYNTAX_TABLE */ + +static char re_syntax_table[CHAR_SET_SIZE]; + +static void init_syntax_once (void); + +static void +init_syntax_once (void) +{ + register int c; + static int done = 0; + + if (done) + return; + bzero (re_syntax_table, sizeof re_syntax_table); + + for (c = 0; c < CHAR_SET_SIZE; ++c) + if (ISALNUM (c)) + re_syntax_table[c] = Sword; + + re_syntax_table['_'] = Sword; + + done = 1; +} + +# endif /* not SYNTAX_TABLE */ + +# define SYNTAX(c) re_syntax_table[(unsigned char) (c)] + +# endif /* emacs */ + +/* Integer type for pointers. */ +# if !defined _LIBC && !defined HAVE_UINTPTR_T +typedef unsigned long int uintptr_t; +# endif + +/* Should we use malloc or alloca? If REGEX_MALLOC is not defined, we + use `alloca' instead of `malloc'. This is because using malloc in + re_search* or re_match* could cause memory leaks when C-g is used in + Emacs; also, malloc is slower and causes storage fragmentation. On + the other hand, malloc is more portable, and easier to debug. + + Because we sometimes use alloca, some routines have to be macros, + not functions -- `alloca'-allocated space disappears at the end of the + function it is called in. */ + +# ifdef REGEX_MALLOC + +# define REGEX_ALLOCATE malloc +# define REGEX_REALLOCATE(source, osize, nsize) realloc (source, nsize) +# define REGEX_FREE free + +# else /* not REGEX_MALLOC */ + +/* Emacs already defines alloca, sometimes. */ +# ifndef alloca + +/* Make alloca work the best possible way. */ +# ifdef __GNUC__ +# define alloca __builtin_alloca +# else /* not __GNUC__ */ +# if HAVE_ALLOCA_H +# include +# endif /* HAVE_ALLOCA_H */ +# endif /* not __GNUC__ */ + +# endif /* not alloca */ + +# define REGEX_ALLOCATE alloca + +/* Assumes a `char *destination' variable. */ +# define REGEX_REALLOCATE(source, osize, nsize) \ + (destination = (char *) alloca (nsize), \ + memcpy (destination, source, osize)) + +/* No need to do anything to free, after alloca. */ +# define REGEX_FREE(arg) ((void)0) /* Do nothing! But inhibit gcc warning. */ + +# endif /* not REGEX_MALLOC */ + +/* Define how to allocate the failure stack. */ + +# if defined REL_ALLOC && defined REGEX_MALLOC + +# define REGEX_ALLOCATE_STACK(size) \ + r_alloc (&failure_stack_ptr, (size)) +# define REGEX_REALLOCATE_STACK(source, osize, nsize) \ + r_re_alloc (&failure_stack_ptr, (nsize)) +# define REGEX_FREE_STACK(ptr) \ + r_alloc_free (&failure_stack_ptr) + +# else /* not using relocating allocator */ + +# ifdef REGEX_MALLOC + +# define REGEX_ALLOCATE_STACK malloc +# define REGEX_REALLOCATE_STACK(source, osize, nsize) realloc (source, nsize) +# define REGEX_FREE_STACK free + +# else /* not REGEX_MALLOC */ + +# define REGEX_ALLOCATE_STACK alloca + +# define REGEX_REALLOCATE_STACK(source, osize, nsize) \ + REGEX_REALLOCATE (source, osize, nsize) +/* No need to explicitly free anything. */ +# define REGEX_FREE_STACK(arg) + +# endif /* not REGEX_MALLOC */ +# endif /* not using relocating allocator */ + + +/* True if `size1' is non-NULL and PTR is pointing anywhere inside + `string1' or just past its end. This works if PTR is NULL, which is + a good thing. */ +# define FIRST_STRING_P(ptr) \ + (size1 && string1 <= (ptr) && (ptr) <= string1 + size1) + +/* (Re)Allocate N items of type T using malloc, or fail. */ +# define TALLOC(n, t) ((t *) malloc ((n) * sizeof (t))) +# define RETALLOC(addr, n, t) ((addr) = (t *) realloc (addr, (n) * sizeof (t))) +# define RETALLOC_IF(addr, n, t) \ + if (addr) RETALLOC((addr), (n), t); else (addr) = TALLOC ((n), t) +# define REGEX_TALLOC(n, t) ((t *) REGEX_ALLOCATE ((n) * sizeof (t))) + +# define BYTEWIDTH 8 /* In bits. */ + +# define STREQ(s1, s2) ((strcmp (s1, s2) == 0)) + +# undef MAX +# undef MIN +# define MAX(a, b) ((a) > (b) ? (a) : (b)) +# define MIN(a, b) ((a) < (b) ? (a) : (b)) + +typedef char boolean; +# define false 0 +# define true 1 + +static reg_errcode_t byte_regex_compile (const char *pattern, size_t size, + reg_syntax_t syntax, + struct re_pattern_buffer *bufp); + +static int byte_re_match_2_internal (struct re_pattern_buffer *bufp, + const char *string1, int size1, + const char *string2, int size2, + int pos, + struct re_registers *regs, + int stop); +static int byte_re_search_2 (struct re_pattern_buffer *bufp, + const char *string1, int size1, + const char *string2, int size2, + int startpos, int range, + struct re_registers *regs, int stop); +static int byte_re_compile_fastmap (struct re_pattern_buffer *bufp); + +#ifdef MBS_SUPPORT +static reg_errcode_t wcs_regex_compile (const char *pattern, size_t size, + reg_syntax_t syntax, + struct re_pattern_buffer *bufp); + + +static int wcs_re_match_2_internal (struct re_pattern_buffer *bufp, + const char *cstring1, int csize1, + const char *cstring2, int csize2, + int pos, + struct re_registers *regs, + int stop, + wchar_t *string1, int size1, + wchar_t *string2, int size2, + int *mbs_offset1, int *mbs_offset2); +static int wcs_re_search_2 (struct re_pattern_buffer *bufp, + const char *string1, int size1, + const char *string2, int size2, + int startpos, int range, + struct re_registers *regs, int stop); +static int wcs_re_compile_fastmap (struct re_pattern_buffer *bufp); +#endif + +/* These are the command codes that appear in compiled regular + expressions. Some opcodes are followed by argument bytes. A + command code can specify any interpretation whatsoever for its + arguments. Zero bytes may appear in the compiled regular expression. */ + +typedef enum +{ + no_op = 0, + + /* Succeed right away--no more backtracking. */ + succeed, + + /* Followed by one byte giving n, then by n literal bytes. */ + exactn, + +# ifdef MBS_SUPPORT + /* Same as exactn, but contains binary data. */ + exactn_bin, +# endif + + /* Matches any (more or less) character. */ + anychar, + + /* Matches any one char belonging to specified set. First + following byte is number of bitmap bytes. Then come bytes + for a bitmap saying which chars are in. Bits in each byte + are ordered low-bit-first. A character is in the set if its + bit is 1. A character too large to have a bit in the map is + automatically not in the set. */ + /* ifdef MBS_SUPPORT, following element is length of character + classes, length of collating symbols, length of equivalence + classes, length of character ranges, and length of characters. + Next, character class element, collating symbols elements, + equivalence class elements, range elements, and character + elements follow. + See regex_compile function. */ + charset, + + /* Same parameters as charset, but match any character that is + not one of those specified. */ + charset_not, + + /* Start remembering the text that is matched, for storing in a + register. Followed by one byte with the register number, in + the range 0 to one less than the pattern buffer's re_nsub + field. Then followed by one byte with the number of groups + inner to this one. (This last has to be part of the + start_memory only because we need it in the on_failure_jump + of re_match_2.) */ + start_memory, + + /* Stop remembering the text that is matched and store it in a + memory register. Followed by one byte with the register + number, in the range 0 to one less than `re_nsub' in the + pattern buffer, and one byte with the number of inner groups, + just like `start_memory'. (We need the number of inner + groups here because we don't have any easy way of finding the + corresponding start_memory when we're at a stop_memory.) */ + stop_memory, + + /* Match a duplicate of something remembered. Followed by one + byte containing the register number. */ + duplicate, + + /* Fail unless at beginning of line. */ + begline, + + /* Fail unless at end of line. */ + endline, + + /* Succeeds if at beginning of buffer (if emacs) or at beginning + of string to be matched (if not). */ + begbuf, + + /* Analogously, for end of buffer/string. */ + endbuf, + + /* Followed by two byte relative address to which to jump. */ + jump, + + /* Same as jump, but marks the end of an alternative. */ + jump_past_alt, + + /* Followed by two-byte relative address of place to resume at + in case of failure. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + on_failure_jump, + + /* Like on_failure_jump, but pushes a placeholder instead of the + current string position when executed. */ + on_failure_keep_string_jump, + + /* Throw away latest failure point and then jump to following + two-byte relative address. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + pop_failure_jump, + + /* Change to pop_failure_jump if know won't have to backtrack to + match; otherwise change to jump. This is used to jump + back to the beginning of a repeat. If what follows this jump + clearly won't match what the repeat does, such that we can be + sure that there is no use backtracking out of repetitions + already matched, then we change it to a pop_failure_jump. + Followed by two-byte address. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + maybe_pop_jump, + + /* Jump to following two-byte address, and push a dummy failure + point. This failure point will be thrown away if an attempt + is made to use it for a failure. A `+' construct makes this + before the first repeat. Also used as an intermediary kind + of jump when compiling an alternative. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + dummy_failure_jump, + + /* Push a dummy failure point and continue. Used at the end of + alternatives. */ + push_dummy_failure, + + /* Followed by two-byte relative address and two-byte number n. + After matching N times, jump to the address upon failure. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + succeed_n, + + /* Followed by two-byte relative address, and two-byte number n. + Jump to the address N times, then fail. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + jump_n, + + /* Set the following two-byte relative address to the + subsequent two-byte number. The address *includes* the two + bytes of number. */ + /* ifdef MBS_SUPPORT, the size of address is 1. */ + set_number_at, + + wordchar, /* Matches any word-constituent character. */ + notwordchar, /* Matches any char that is not a word-constituent. */ + + wordbeg, /* Succeeds if at word beginning. */ + wordend, /* Succeeds if at word end. */ + + wordbound, /* Succeeds if at a word boundary. */ + notwordbound /* Succeeds if not at a word boundary. */ + +# ifdef emacs + ,before_dot, /* Succeeds if before point. */ + at_dot, /* Succeeds if at point. */ + after_dot, /* Succeeds if after point. */ + + /* Matches any character whose syntax is specified. Followed by + a byte which contains a syntax code, e.g., Sword. */ + syntaxspec, + + /* Matches any character whose syntax is not that specified. */ + notsyntaxspec +# endif /* emacs */ +} re_opcode_t; +#endif /* not INSIDE_RECURSION */ + + +#ifdef BYTE +# define CHAR_T char +# define UCHAR_T unsigned char +# define COMPILED_BUFFER_VAR bufp->buffer +# define OFFSET_ADDRESS_SIZE 2 +# define PREFIX(name) byte_##name +# define ARG_PREFIX(name) name +# define PUT_CHAR(c) putchar (c) +#else +# ifdef WCHAR +# define CHAR_T wchar_t +# define UCHAR_T wchar_t +# define COMPILED_BUFFER_VAR wc_buffer +# define OFFSET_ADDRESS_SIZE 1 /* the size which STORE_NUMBER macro use */ +# define CHAR_CLASS_SIZE ((__alignof__(wctype_t)+sizeof(wctype_t))/sizeof(CHAR_T)+1) +# define PREFIX(name) wcs_##name +# define ARG_PREFIX(name) c##name +/* Should we use wide stream?? */ +# define PUT_CHAR(c) printf ("%C", c); +# define TRUE 1 +# define FALSE 0 +# else +# ifdef MBS_SUPPORT +# define WCHAR +# define INSIDE_RECURSION +# include "regex.c" +# undef INSIDE_RECURSION +# endif +# define BYTE +# define INSIDE_RECURSION +# include "regex.c" +# undef INSIDE_RECURSION +# endif +#endif + +#ifdef INSIDE_RECURSION +/* Common operations on the compiled pattern. */ + +/* Store NUMBER in two contiguous bytes starting at DESTINATION. */ +/* ifdef MBS_SUPPORT, we store NUMBER in 1 element. */ + +# ifdef WCHAR +# define STORE_NUMBER(destination, number) \ + do { \ + *(destination) = (UCHAR_T)(number); \ + } while (0) +# else /* BYTE */ +# define STORE_NUMBER(destination, number) \ + do { \ + (destination)[0] = (number) & 0377; \ + (destination)[1] = (number) >> 8; \ + } while (0) +# endif /* WCHAR */ + +/* Same as STORE_NUMBER, except increment DESTINATION to + the byte after where the number is stored. Therefore, DESTINATION + must be an lvalue. */ +/* ifdef MBS_SUPPORT, we store NUMBER in 1 element. */ + +# define STORE_NUMBER_AND_INCR(destination, number) \ + do { \ + STORE_NUMBER (destination, number); \ + (destination) += OFFSET_ADDRESS_SIZE; \ + } while (0) + +/* Put into DESTINATION a number stored in two contiguous bytes starting + at SOURCE. */ +/* ifdef MBS_SUPPORT, we store NUMBER in 1 element. */ + +# ifdef WCHAR +# define EXTRACT_NUMBER(destination, source) \ + do { \ + (destination) = *(source); \ + } while (0) +# else /* BYTE */ +# define EXTRACT_NUMBER(destination, source) \ + do { \ + (destination) = *(source) & 0377; \ + (destination) += SIGN_EXTEND_CHAR (*((source) + 1)) << 8; \ + } while (0) +# endif + +# ifdef DEBUG +static void PREFIX(extract_number) (int *dest, UCHAR_T *source); +static void +PREFIX(extract_number) (int *dest, UCHAR_T *source) +{ +# ifdef WCHAR + *dest = *source; +# else /* BYTE */ + int temp = SIGN_EXTEND_CHAR (*(source + 1)); + *dest = *source & 0377; + *dest += temp << 8; +# endif +} + +# ifndef EXTRACT_MACROS /* To debug the macros. */ +# undef EXTRACT_NUMBER +# define EXTRACT_NUMBER(dest, src) PREFIX(extract_number) (&dest, src) +# endif /* not EXTRACT_MACROS */ + +# endif /* DEBUG */ + +/* Same as EXTRACT_NUMBER, except increment SOURCE to after the number. + SOURCE must be an lvalue. */ + +# define EXTRACT_NUMBER_AND_INCR(destination, source) \ + do { \ + EXTRACT_NUMBER (destination, source); \ + (source) += OFFSET_ADDRESS_SIZE; \ + } while (0) + +# ifdef DEBUG +static void PREFIX(extract_number_and_incr) (int *destination, + UCHAR_T **source); +static void +PREFIX(extract_number_and_incr) (int *destination, UCHAR_T **source) +{ + PREFIX(extract_number) (destination, *source); + *source += OFFSET_ADDRESS_SIZE; +} + +# ifndef EXTRACT_MACROS +# undef EXTRACT_NUMBER_AND_INCR +# define EXTRACT_NUMBER_AND_INCR(dest, src) \ + PREFIX(extract_number_and_incr) (&dest, &src) +# endif /* not EXTRACT_MACROS */ + +# endif /* DEBUG */ + + + +/* If DEBUG is defined, Regex prints many voluminous messages about what + it is doing (if the variable `debug' is nonzero). If linked with the + main program in `iregex.c', you can enter patterns and strings + interactively. And if linked with the main program in `main.c' and + the other test files, you can run the already-written tests. */ + +# ifdef DEBUG + +# ifndef DEFINED_ONCE + +/* We use standard I/O for debugging. */ +# include + +/* It is useful to test things that ``must'' be true when debugging. */ +# include + +static int debug; + +# define DEBUG_STATEMENT(e) e +# define DEBUG_PRINT1(x) if (debug) printf (x) +# define DEBUG_PRINT2(x1, x2) if (debug) printf (x1, x2) +# define DEBUG_PRINT3(x1, x2, x3) if (debug) printf (x1, x2, x3) +# define DEBUG_PRINT4(x1, x2, x3, x4) if (debug) printf (x1, x2, x3, x4) +# endif /* not DEFINED_ONCE */ + +# define DEBUG_PRINT_COMPILED_PATTERN(p, s, e) \ + if (debug) PREFIX(print_partial_compiled_pattern) (s, e) +# define DEBUG_PRINT_DOUBLE_STRING(w, s1, sz1, s2, sz2) \ + if (debug) PREFIX(print_double_string) (w, s1, sz1, s2, sz2) + + +/* Print the fastmap in human-readable form. */ + +# ifndef DEFINED_ONCE +void +print_fastmap (char *fastmap) +{ + unsigned was_a_range = 0; + unsigned i = 0; + + while (i < (1 << BYTEWIDTH)) + { + if (fastmap[i++]) + { + was_a_range = 0; + putchar (i - 1); + while (i < (1 << BYTEWIDTH) && fastmap[i]) + { + was_a_range = 1; + i++; + } + if (was_a_range) + { + printf ("-"); + putchar (i - 1); + } + } + } + putchar ('\n'); +} +# endif /* not DEFINED_ONCE */ + + +/* Print a compiled pattern string in human-readable form, starting at + the START pointer into it and ending just before the pointer END. */ + +void +PREFIX(print_partial_compiled_pattern) (UCHAR_T *start, UCHAR_T *end) +{ + int mcnt, mcnt2; + UCHAR_T *p1; + UCHAR_T *p = start; + UCHAR_T *pend = end; + + if (start == NULL) + { + printf ("(null)\n"); + return; + } + + /* Loop over pattern commands. */ + while (p < pend) + { +# ifdef _LIBC + printf ("%td:\t", p - start); +# else + printf ("%ld:\t", (long int) (p - start)); +# endif + + switch ((re_opcode_t) *p++) + { + case no_op: + printf ("/no_op"); + break; + + case exactn: + mcnt = *p++; + printf ("/exactn/%d", mcnt); + do + { + putchar ('/'); + PUT_CHAR (*p++); + } + while (--mcnt); + break; + +# ifdef MBS_SUPPORT + case exactn_bin: + mcnt = *p++; + printf ("/exactn_bin/%d", mcnt); + do + { + printf("/%lx", (long int) *p++); + } + while (--mcnt); + break; +# endif /* MBS_SUPPORT */ + + case start_memory: + mcnt = *p++; + printf ("/start_memory/%d/%ld", mcnt, (long int) *p++); + break; + + case stop_memory: + mcnt = *p++; + printf ("/stop_memory/%d/%ld", mcnt, (long int) *p++); + break; + + case duplicate: + printf ("/duplicate/%ld", (long int) *p++); + break; + + case anychar: + printf ("/anychar"); + break; + + case charset: + case charset_not: + { +# ifdef WCHAR + int i, length; + wchar_t *workp = p; + printf ("/charset [%s", + (re_opcode_t) *(workp - 1) == charset_not ? "^" : ""); + p += 5; + length = *workp++; /* the length of char_classes */ + for (i=0 ; ibuffer; + + PREFIX(print_partial_compiled_pattern) (buffer, buffer + + bufp->used / sizeof(UCHAR_T)); + printf ("%ld bytes used/%ld bytes allocated.\n", + bufp->used, bufp->allocated); + + if (bufp->fastmap_accurate && bufp->fastmap) + { + printf ("fastmap: "); + print_fastmap (bufp->fastmap); + } + +# ifdef _LIBC + printf ("re_nsub: %Zd\t", bufp->re_nsub); +# else + printf ("re_nsub: %ld\t", (long int) bufp->re_nsub); +# endif + printf ("regs_alloc: %d\t", bufp->regs_allocated); + printf ("can_be_null: %d\t", bufp->can_be_null); + printf ("newline_anchor: %d\n", bufp->newline_anchor); + printf ("no_sub: %d\t", bufp->no_sub); + printf ("not_bol: %d\t", bufp->not_bol); + printf ("not_eol: %d\t", bufp->not_eol); + printf ("syntax: %lx\n", bufp->syntax); + /* Perhaps we should print the translate table? */ +} + + +void +PREFIX(print_double_string) (const CHAR_T *where, const CHAR_T *string1, + int size1, const CHAR_T *string2, int size2) +{ + int this_char; + + if (where == NULL) + printf ("(null)"); + else + { + int cnt; + + if (FIRST_STRING_P (where)) + { + for (this_char = where - string1; this_char < size1; this_char++) + PUT_CHAR (string1[this_char]); + + where = string2; + } + + cnt = 0; + for (this_char = where - string2; this_char < size2; this_char++) + { + PUT_CHAR (string2[this_char]); + if (++cnt > 100) + { + fputs ("...", stdout); + break; + } + } + } +} + +# ifndef DEFINED_ONCE +void +printchar (int c) +{ + putc (c, stderr); +} +# endif + +# else /* not DEBUG */ + +# ifndef DEFINED_ONCE +# undef assert +# define assert(e) + +# define DEBUG_STATEMENT(e) +# define DEBUG_PRINT1(x) +# define DEBUG_PRINT2(x1, x2) +# define DEBUG_PRINT3(x1, x2, x3) +# define DEBUG_PRINT4(x1, x2, x3, x4) +# endif /* not DEFINED_ONCE */ +# define DEBUG_PRINT_COMPILED_PATTERN(p, s, e) +# define DEBUG_PRINT_DOUBLE_STRING(w, s1, sz1, s2, sz2) + +# endif /* not DEBUG */ + + + +# ifdef WCHAR +/* This convert a multibyte string to a wide character string. + And write their correspondances to offset_buffer(see below) + and write whether each wchar_t is binary data to is_binary. + This assume invalid multibyte sequences as binary data. + We assume offset_buffer and is_binary is already allocated + enough space. */ + +static size_t convert_mbs_to_wcs (CHAR_T *dest, const unsigned char* src, + size_t len, int *offset_buffer, + char *is_binary); +static size_t +convert_mbs_to_wcs (CHAR_T *dest, const unsigned char*src, size_t len, + int *offset_buffer, char *is_binary) + /* It hold correspondances between src(char string) and + dest(wchar_t string) for optimization. + e.g. src = "xxxyzz" + dest = {'X', 'Y', 'Z'} + (each "xxx", "y" and "zz" represent one multibyte character + corresponding to 'X', 'Y' and 'Z'.) + offset_buffer = {0, 0+3("xxx"), 0+3+1("y"), 0+3+1+2("zz")} + = {0, 3, 4, 6} + */ +{ + wchar_t *pdest = dest; + const unsigned char *psrc = src; + size_t wc_count = 0; + + mbstate_t mbs; + int i, consumed; + size_t mb_remain = len; + size_t mb_count = 0; + + /* Initialize the conversion state. */ + memset (&mbs, 0, sizeof (mbstate_t)); + + offset_buffer[0] = 0; + for( ; mb_remain > 0 ; ++wc_count, ++pdest, mb_remain -= consumed, + psrc += consumed) + { +#ifdef _LIBC + consumed = __mbrtowc (pdest, psrc, mb_remain, &mbs); +#else + consumed = mbrtowc (pdest, psrc, mb_remain, &mbs); +#endif + + if (consumed <= 0) + /* failed to convert. maybe src contains binary data. + So we consume 1 byte manualy. */ + { + *pdest = *psrc; + consumed = 1; + is_binary[wc_count] = TRUE; + } + else + is_binary[wc_count] = FALSE; + /* In sjis encoding, we use yen sign as escape character in + place of reverse solidus. So we convert 0x5c(yen sign in + sjis) to not 0xa5(yen sign in UCS2) but 0x5c(reverse + solidus in UCS2). */ + if (consumed == 1 && (int) *psrc == 0x5c && (int) *pdest == 0xa5) + *pdest = (wchar_t) *psrc; + + offset_buffer[wc_count + 1] = mb_count += consumed; + } + + /* Fill remain of the buffer with sentinel. */ + for (i = wc_count + 1 ; i <= len ; i++) + offset_buffer[i] = mb_count + 1; + + return wc_count; +} + +# endif /* WCHAR */ + +#else /* not INSIDE_RECURSION */ + +/* Set by `re_set_syntax' to the current regexp syntax to recognize. Can + also be assigned to arbitrarily: each pattern buffer stores its own + syntax, so it can be changed between regex compilations. */ +/* This has no initializer because initialized variables in Emacs + become read-only after dumping. */ +reg_syntax_t re_syntax_options; + + +/* Specify the precise syntax of regexps for compilation. This provides + for compatibility for various utilities which historically have + different, incompatible syntaxes. + + The argument SYNTAX is a bit mask comprised of the various bits + defined in regex.h. We return the old syntax. */ + +reg_syntax_t +re_set_syntax (reg_syntax_t syntax) +{ + reg_syntax_t ret = re_syntax_options; + + re_syntax_options = syntax; +# ifdef DEBUG + if (syntax & RE_DEBUG) + debug = 1; + else if (debug) /* was on but now is not */ + debug = 0; +# endif /* DEBUG */ + return ret; +} +# ifdef _LIBC +weak_alias (__re_set_syntax, re_set_syntax) +# endif + +/* This table gives an error message for each of the error codes listed + in regex.h. Obviously the order here has to be same as there. + POSIX doesn't require that we do anything for REG_NOERROR, + but why not be nice? */ + +static const char *re_error_msgid[] = + { + gettext_noop ("Success"), /* REG_NOERROR */ + gettext_noop ("No match"), /* REG_NOMATCH */ + gettext_noop ("Invalid regular expression"), /* REG_BADPAT */ + gettext_noop ("Invalid collation character"), /* REG_ECOLLATE */ + gettext_noop ("Invalid character class name"), /* REG_ECTYPE */ + gettext_noop ("Trailing backslash"), /* REG_EESCAPE */ + gettext_noop ("Invalid back reference"), /* REG_ESUBREG */ + gettext_noop ("Unmatched [ or [^"), /* REG_EBRACK */ + gettext_noop ("Unmatched ( or \\("), /* REG_EPAREN */ + gettext_noop ("Unmatched \\{"), /* REG_EBRACE */ + gettext_noop ("Invalid content of \\{\\}"), /* REG_BADBR */ + gettext_noop ("Invalid range end"), /* REG_ERANGE */ + gettext_noop ("Memory exhausted"), /* REG_ESPACE */ + gettext_noop ("Invalid preceding regular expression"), /* REG_BADRPT */ + gettext_noop ("Premature end of regular expression"), /* REG_EEND */ + gettext_noop ("Regular expression too big"), /* REG_ESIZE */ + gettext_noop ("Unmatched ) or \\)") /* REG_ERPAREN */ + }; + +#endif /* INSIDE_RECURSION */ + +#ifndef DEFINED_ONCE +/* Avoiding alloca during matching, to placate r_alloc. */ + +/* Define MATCH_MAY_ALLOCATE unless we need to make sure that the + searching and matching functions should not call alloca. On some + systems, alloca is implemented in terms of malloc, and if we're + using the relocating allocator routines, then malloc could cause a + relocation, which might (if the strings being searched are in the + ralloc heap) shift the data out from underneath the regexp + routines. + + Here's another reason to avoid allocation: Emacs + processes input from X in a signal handler; processing X input may + call malloc; if input arrives while a matching routine is calling + malloc, then we're scrod. But Emacs can't just block input while + calling matching routines; then we don't notice interrupts when + they come in. So, Emacs blocks input around all regexp calls + except the matching calls, which it leaves unprotected, in the + faith that they will not malloc. */ + +/* Normally, this is fine. */ +# define MATCH_MAY_ALLOCATE + +/* When using GNU C, we are not REALLY using the C alloca, no matter + what config.h may say. So don't take precautions for it. */ +# ifdef __GNUC__ +# undef C_ALLOCA +# endif + +/* The match routines may not allocate if (1) they would do it with malloc + and (2) it's not safe for them to use malloc. + Note that if REL_ALLOC is defined, matching would not use malloc for the + failure stack, but we would still use it for the register vectors; + so REL_ALLOC should not affect this. */ +# if (defined C_ALLOCA || defined REGEX_MALLOC) && defined emacs +# undef MATCH_MAY_ALLOCATE +# endif +#endif /* not DEFINED_ONCE */ + +#ifdef INSIDE_RECURSION +/* Failure stack declarations and macros; both re_compile_fastmap and + re_match_2 use a failure stack. These have to be macros because of + REGEX_ALLOCATE_STACK. */ + + +/* Number of failure points for which to initially allocate space + when matching. If this number is exceeded, we allocate more + space, so it is not a hard limit. */ +# ifndef INIT_FAILURE_ALLOC +# define INIT_FAILURE_ALLOC 5 +# endif + +/* Roughly the maximum number of failure points on the stack. Would be + exactly that if always used MAX_FAILURE_ITEMS items each time we failed. + This is a variable only so users of regex can assign to it; we never + change it ourselves. */ + +# ifdef INT_IS_16BIT + +# ifndef DEFINED_ONCE +# if defined MATCH_MAY_ALLOCATE +/* 4400 was enough to cause a crash on Alpha OSF/1, + whose default stack limit is 2mb. */ +long int re_max_failures = 4000; +# else +long int re_max_failures = 2000; +# endif +# endif + +union PREFIX(fail_stack_elt) +{ + UCHAR_T *pointer; + long int integer; +}; + +typedef union PREFIX(fail_stack_elt) PREFIX(fail_stack_elt_t); + +typedef struct +{ + PREFIX(fail_stack_elt_t) *stack; + unsigned long int size; + unsigned long int avail; /* Offset of next open position. */ +} PREFIX(fail_stack_type); + +# else /* not INT_IS_16BIT */ + +# ifndef DEFINED_ONCE +# if defined MATCH_MAY_ALLOCATE +/* 4400 was enough to cause a crash on Alpha OSF/1, + whose default stack limit is 2mb. */ +int re_max_failures = 4000; +# else +int re_max_failures = 2000; +# endif +# endif + +union PREFIX(fail_stack_elt) +{ + UCHAR_T *pointer; + int integer; +}; + +typedef union PREFIX(fail_stack_elt) PREFIX(fail_stack_elt_t); + +typedef struct +{ + PREFIX(fail_stack_elt_t) *stack; + unsigned size; + unsigned avail; /* Offset of next open position. */ +} PREFIX(fail_stack_type); + +# endif /* INT_IS_16BIT */ + +# ifndef DEFINED_ONCE +# define FAIL_STACK_EMPTY() (fail_stack.avail == 0) +# define FAIL_STACK_PTR_EMPTY() (fail_stack_ptr->avail == 0) +# define FAIL_STACK_FULL() (fail_stack.avail == fail_stack.size) +# endif + + +/* Define macros to initialize and free the failure stack. + Do `return -2' if the alloc fails. */ + +# ifdef MATCH_MAY_ALLOCATE +# define INIT_FAIL_STACK() \ + do { \ + fail_stack.stack = (PREFIX(fail_stack_elt_t) *) \ + REGEX_ALLOCATE_STACK (INIT_FAILURE_ALLOC * sizeof (PREFIX(fail_stack_elt_t))); \ + \ + if (fail_stack.stack == NULL) \ + return -2; \ + \ + fail_stack.size = INIT_FAILURE_ALLOC; \ + fail_stack.avail = 0; \ + } while (0) + +# define RESET_FAIL_STACK() REGEX_FREE_STACK (fail_stack.stack) +# else +# define INIT_FAIL_STACK() \ + do { \ + fail_stack.avail = 0; \ + } while (0) + +# define RESET_FAIL_STACK() +# endif + + +/* Double the size of FAIL_STACK, up to approximately `re_max_failures' items. + + Return 1 if succeeds, and 0 if either ran out of memory + allocating space for it or it was already too large. + + REGEX_REALLOCATE_STACK requires `destination' be declared. */ + +# define DOUBLE_FAIL_STACK(fail_stack) \ + ((fail_stack).size > (unsigned) (re_max_failures * MAX_FAILURE_ITEMS) \ + ? 0 \ + : ((fail_stack).stack = (PREFIX(fail_stack_elt_t) *) \ + REGEX_REALLOCATE_STACK ((fail_stack).stack, \ + (fail_stack).size * sizeof (PREFIX(fail_stack_elt_t)), \ + ((fail_stack).size << 1) * sizeof (PREFIX(fail_stack_elt_t))),\ + \ + (fail_stack).stack == NULL \ + ? 0 \ + : ((fail_stack).size <<= 1, \ + 1))) + + +/* Push pointer POINTER on FAIL_STACK. + Return 1 if was able to do so and 0 if ran out of memory allocating + space to do so. */ +# define PUSH_PATTERN_OP(POINTER, FAIL_STACK) \ + ((FAIL_STACK_FULL () \ + && !DOUBLE_FAIL_STACK (FAIL_STACK)) \ + ? 0 \ + : ((FAIL_STACK).stack[(FAIL_STACK).avail++].pointer = POINTER, \ + 1)) + +/* Push a pointer value onto the failure stack. + Assumes the variable `fail_stack'. Probably should only + be called from within `PUSH_FAILURE_POINT'. */ +# define PUSH_FAILURE_POINTER(item) \ + fail_stack.stack[fail_stack.avail++].pointer = (UCHAR_T *) (item) + +/* This pushes an integer-valued item onto the failure stack. + Assumes the variable `fail_stack'. Probably should only + be called from within `PUSH_FAILURE_POINT'. */ +# define PUSH_FAILURE_INT(item) \ + fail_stack.stack[fail_stack.avail++].integer = (item) + +/* Push a fail_stack_elt_t value onto the failure stack. + Assumes the variable `fail_stack'. Probably should only + be called from within `PUSH_FAILURE_POINT'. */ +# define PUSH_FAILURE_ELT(item) \ + fail_stack.stack[fail_stack.avail++] = (item) + +/* These three POP... operations complement the three PUSH... operations. + All assume that `fail_stack' is nonempty. */ +# define POP_FAILURE_POINTER() fail_stack.stack[--fail_stack.avail].pointer +# define POP_FAILURE_INT() fail_stack.stack[--fail_stack.avail].integer +# define POP_FAILURE_ELT() fail_stack.stack[--fail_stack.avail] + +/* Used to omit pushing failure point id's when we're not debugging. */ +# ifdef DEBUG +# define DEBUG_PUSH PUSH_FAILURE_INT +# define DEBUG_POP(item_addr) *(item_addr) = POP_FAILURE_INT () +# else +# define DEBUG_PUSH(item) +# define DEBUG_POP(item_addr) +# endif + + +/* Push the information about the state we will need + if we ever fail back to it. + + Requires variables fail_stack, regstart, regend, reg_info, and + num_regs_pushed be declared. DOUBLE_FAIL_STACK requires `destination' + be declared. + + Does `return FAILURE_CODE' if runs out of memory. */ + +# define PUSH_FAILURE_POINT(pattern_place, string_place, failure_code) \ + do { \ + char *destination; \ + /* Must be int, so when we don't save any registers, the arithmetic \ + of 0 + -1 isn't done as unsigned. */ \ + /* Can't be int, since there is not a shred of a guarantee that int \ + is wide enough to hold a value of something to which pointer can \ + be assigned */ \ + active_reg_t this_reg; \ + \ + DEBUG_STATEMENT (failure_id++); \ + DEBUG_STATEMENT (nfailure_points_pushed++); \ + DEBUG_PRINT2 ("\nPUSH_FAILURE_POINT #%u:\n", failure_id); \ + DEBUG_PRINT2 (" Before push, next avail: %d\n", (fail_stack).avail);\ + DEBUG_PRINT2 (" size: %d\n", (fail_stack).size);\ + \ + DEBUG_PRINT2 (" slots needed: %ld\n", NUM_FAILURE_ITEMS); \ + DEBUG_PRINT2 (" available: %d\n", REMAINING_AVAIL_SLOTS); \ + \ + /* Ensure we have enough space allocated for what we will push. */ \ + while (REMAINING_AVAIL_SLOTS < NUM_FAILURE_ITEMS) \ + { \ + if (!DOUBLE_FAIL_STACK (fail_stack)) \ + return failure_code; \ + \ + DEBUG_PRINT2 ("\n Doubled stack; size now: %d\n", \ + (fail_stack).size); \ + DEBUG_PRINT2 (" slots available: %d\n", REMAINING_AVAIL_SLOTS);\ + } \ + \ + /* Push the info, starting with the registers. */ \ + DEBUG_PRINT1 ("\n"); \ + \ + if (1) \ + for (this_reg = lowest_active_reg; this_reg <= highest_active_reg; \ + this_reg++) \ + { \ + DEBUG_PRINT2 (" Pushing reg: %lu\n", this_reg); \ + DEBUG_STATEMENT (num_regs_pushed++); \ + \ + DEBUG_PRINT2 (" start: %p\n", regstart[this_reg]); \ + PUSH_FAILURE_POINTER (regstart[this_reg]); \ + \ + DEBUG_PRINT2 (" end: %p\n", regend[this_reg]); \ + PUSH_FAILURE_POINTER (regend[this_reg]); \ + \ + DEBUG_PRINT2 (" info: %p\n ", \ + reg_info[this_reg].word.pointer); \ + DEBUG_PRINT2 (" match_null=%d", \ + REG_MATCH_NULL_STRING_P (reg_info[this_reg])); \ + DEBUG_PRINT2 (" active=%d", IS_ACTIVE (reg_info[this_reg])); \ + DEBUG_PRINT2 (" matched_something=%d", \ + MATCHED_SOMETHING (reg_info[this_reg])); \ + DEBUG_PRINT2 (" ever_matched=%d", \ + EVER_MATCHED_SOMETHING (reg_info[this_reg])); \ + DEBUG_PRINT1 ("\n"); \ + PUSH_FAILURE_ELT (reg_info[this_reg].word); \ + } \ + \ + DEBUG_PRINT2 (" Pushing low active reg: %ld\n", lowest_active_reg);\ + PUSH_FAILURE_INT (lowest_active_reg); \ + \ + DEBUG_PRINT2 (" Pushing high active reg: %ld\n", highest_active_reg);\ + PUSH_FAILURE_INT (highest_active_reg); \ + \ + DEBUG_PRINT2 (" Pushing pattern %p:\n", pattern_place); \ + DEBUG_PRINT_COMPILED_PATTERN (bufp, pattern_place, pend); \ + PUSH_FAILURE_POINTER (pattern_place); \ + \ + DEBUG_PRINT2 (" Pushing string %p: `", string_place); \ + DEBUG_PRINT_DOUBLE_STRING (string_place, string1, size1, string2, \ + size2); \ + DEBUG_PRINT1 ("'\n"); \ + PUSH_FAILURE_POINTER (string_place); \ + \ + DEBUG_PRINT2 (" Pushing failure id: %u\n", failure_id); \ + DEBUG_PUSH (failure_id); \ + } while (0) + +# ifndef DEFINED_ONCE +/* This is the number of items that are pushed and popped on the stack + for each register. */ +# define NUM_REG_ITEMS 3 + +/* Individual items aside from the registers. */ +# ifdef DEBUG +# define NUM_NONREG_ITEMS 5 /* Includes failure point id. */ +# else +# define NUM_NONREG_ITEMS 4 +# endif + +/* We push at most this many items on the stack. */ +/* We used to use (num_regs - 1), which is the number of registers + this regexp will save; but that was changed to 5 + to avoid stack overflow for a regexp with lots of parens. */ +# define MAX_FAILURE_ITEMS (5 * NUM_REG_ITEMS + NUM_NONREG_ITEMS) + +/* We actually push this many items. */ +# define NUM_FAILURE_ITEMS \ + (((0 \ + ? 0 : highest_active_reg - lowest_active_reg + 1) \ + * NUM_REG_ITEMS) \ + + NUM_NONREG_ITEMS) + +/* How many items can still be added to the stack without overflowing it. */ +# define REMAINING_AVAIL_SLOTS ((fail_stack).size - (fail_stack).avail) +# endif /* not DEFINED_ONCE */ + + +/* Pops what PUSH_FAIL_STACK pushes. + + We restore into the parameters, all of which should be lvalues: + STR -- the saved data position. + PAT -- the saved pattern position. + LOW_REG, HIGH_REG -- the highest and lowest active registers. + REGSTART, REGEND -- arrays of string positions. + REG_INFO -- array of information about each subexpression. + + Also assumes the variables `fail_stack' and (if debugging), `bufp', + `pend', `string1', `size1', `string2', and `size2'. */ +# define POP_FAILURE_POINT(str, pat, low_reg, high_reg, regstart, regend, reg_info)\ +{ \ + DEBUG_STATEMENT (unsigned failure_id;) \ + active_reg_t this_reg; \ + const UCHAR_T *string_temp; \ + \ + assert (!FAIL_STACK_EMPTY ()); \ + \ + /* Remove failure points and point to how many regs pushed. */ \ + DEBUG_PRINT1 ("POP_FAILURE_POINT:\n"); \ + DEBUG_PRINT2 (" Before pop, next avail: %d\n", fail_stack.avail); \ + DEBUG_PRINT2 (" size: %d\n", fail_stack.size); \ + \ + assert (fail_stack.avail >= NUM_NONREG_ITEMS); \ + \ + DEBUG_POP (&failure_id); \ + DEBUG_PRINT2 (" Popping failure id: %u\n", failure_id); \ + \ + /* If the saved string location is NULL, it came from an \ + on_failure_keep_string_jump opcode, and we want to throw away the \ + saved NULL, thus retaining our current position in the string. */ \ + string_temp = POP_FAILURE_POINTER (); \ + if (string_temp != NULL) \ + str = (const CHAR_T *) string_temp; \ + \ + DEBUG_PRINT2 (" Popping string %p: `", str); \ + DEBUG_PRINT_DOUBLE_STRING (str, string1, size1, string2, size2); \ + DEBUG_PRINT1 ("'\n"); \ + \ + pat = (UCHAR_T *) POP_FAILURE_POINTER (); \ + DEBUG_PRINT2 (" Popping pattern %p:\n", pat); \ + DEBUG_PRINT_COMPILED_PATTERN (bufp, pat, pend); \ + \ + /* Restore register info. */ \ + high_reg = (active_reg_t) POP_FAILURE_INT (); \ + DEBUG_PRINT2 (" Popping high active reg: %ld\n", high_reg); \ + \ + low_reg = (active_reg_t) POP_FAILURE_INT (); \ + DEBUG_PRINT2 (" Popping low active reg: %ld\n", low_reg); \ + \ + if (1) \ + for (this_reg = high_reg; this_reg >= low_reg; this_reg--) \ + { \ + DEBUG_PRINT2 (" Popping reg: %ld\n", this_reg); \ + \ + reg_info[this_reg].word = POP_FAILURE_ELT (); \ + DEBUG_PRINT2 (" info: %p\n", \ + reg_info[this_reg].word.pointer); \ + \ + regend[this_reg] = (const CHAR_T *) POP_FAILURE_POINTER (); \ + DEBUG_PRINT2 (" end: %p\n", regend[this_reg]); \ + \ + regstart[this_reg] = (const CHAR_T *) POP_FAILURE_POINTER (); \ + DEBUG_PRINT2 (" start: %p\n", regstart[this_reg]); \ + } \ + else \ + { \ + for (this_reg = highest_active_reg; this_reg > high_reg; this_reg--) \ + { \ + reg_info[this_reg].word.integer = 0; \ + regend[this_reg] = 0; \ + regstart[this_reg] = 0; \ + } \ + highest_active_reg = high_reg; \ + } \ + \ + set_regs_matched_done = 0; \ + DEBUG_STATEMENT (nfailure_points_popped++); \ +} /* POP_FAILURE_POINT */ + +/* Structure for per-register (a.k.a. per-group) information. + Other register information, such as the + starting and ending positions (which are addresses), and the list of + inner groups (which is a bits list) are maintained in separate + variables. + + We are making a (strictly speaking) nonportable assumption here: that + the compiler will pack our bit fields into something that fits into + the type of `word', i.e., is something that fits into one item on the + failure stack. */ + + +/* Declarations and macros for re_match_2. */ + +typedef union +{ + PREFIX(fail_stack_elt_t) word; + struct + { + /* This field is one if this group can match the empty string, + zero if not. If not yet determined, `MATCH_NULL_UNSET_VALUE'. */ +# define MATCH_NULL_UNSET_VALUE 3 + unsigned match_null_string_p : 2; + unsigned is_active : 1; + unsigned matched_something : 1; + unsigned ever_matched_something : 1; + } bits; +} PREFIX(register_info_type); + +# ifndef DEFINED_ONCE +# define REG_MATCH_NULL_STRING_P(R) ((R).bits.match_null_string_p) +# define IS_ACTIVE(R) ((R).bits.is_active) +# define MATCHED_SOMETHING(R) ((R).bits.matched_something) +# define EVER_MATCHED_SOMETHING(R) ((R).bits.ever_matched_something) + + +/* Call this when have matched a real character; it sets `matched' flags + for the subexpressions which we are currently inside. Also records + that those subexprs have matched. */ +# define SET_REGS_MATCHED() \ + do \ + { \ + if (!set_regs_matched_done) \ + { \ + active_reg_t r; \ + set_regs_matched_done = 1; \ + for (r = lowest_active_reg; r <= highest_active_reg; r++) \ + { \ + MATCHED_SOMETHING (reg_info[r]) \ + = EVER_MATCHED_SOMETHING (reg_info[r]) \ + = 1; \ + } \ + } \ + } \ + while (0) +# endif /* not DEFINED_ONCE */ + +/* Registers are set to a sentinel when they haven't yet matched. */ +static CHAR_T PREFIX(reg_unset_dummy); +# define REG_UNSET_VALUE (&PREFIX(reg_unset_dummy)) +# define REG_UNSET(e) ((e) == REG_UNSET_VALUE) + +/* Subroutine declarations and macros for regex_compile. */ +static void PREFIX(store_op1) (re_opcode_t op, UCHAR_T *loc, int arg); +static void PREFIX(store_op2) (re_opcode_t op, UCHAR_T *loc, + int arg1, int arg2); +static void PREFIX(insert_op1) (re_opcode_t op, UCHAR_T *loc, + int arg, UCHAR_T *end); +static void PREFIX(insert_op2) (re_opcode_t op, UCHAR_T *loc, + int arg1, int arg2, UCHAR_T *end); +static boolean PREFIX(at_begline_loc_p) (const CHAR_T *pattern, + const CHAR_T *p, + reg_syntax_t syntax); +static boolean PREFIX(at_endline_loc_p) (const CHAR_T *p, + const CHAR_T *pend, + reg_syntax_t syntax); +# ifdef WCHAR +static reg_errcode_t wcs_compile_range (CHAR_T range_start, + const CHAR_T **p_ptr, + const CHAR_T *pend, + char *translate, + reg_syntax_t syntax, + UCHAR_T *b, + CHAR_T *char_set); +static void insert_space (int num, CHAR_T *loc, CHAR_T *end); +# else /* BYTE */ +static reg_errcode_t byte_compile_range (unsigned int range_start, + const char **p_ptr, + const char *pend, + char *translate, + reg_syntax_t syntax, + unsigned char *b); +# endif /* WCHAR */ + +/* Fetch the next character in the uncompiled pattern---translating it + if necessary. Also cast from a signed character in the constant + string passed to us by the user to an unsigned char that we can use + as an array index (in, e.g., `translate'). */ +/* ifdef MBS_SUPPORT, we translate only if character <= 0xff, + because it is impossible to allocate 4GB array for some encodings + which have 4 byte character_set like UCS4. */ +# ifndef PATFETCH +# ifdef WCHAR +# define PATFETCH(c) \ + do {if (p == pend) return REG_EEND; \ + c = (UCHAR_T) *p++; \ + if (translate && (c <= 0xff)) c = (UCHAR_T) translate[c]; \ + } while (0) +# else /* BYTE */ +# define PATFETCH(c) \ + do {if (p == pend) return REG_EEND; \ + c = (unsigned char) *p++; \ + if (translate) c = (unsigned char) translate[c]; \ + } while (0) +# endif /* WCHAR */ +# endif + +/* Fetch the next character in the uncompiled pattern, with no + translation. */ +# define PATFETCH_RAW(c) \ + do {if (p == pend) return REG_EEND; \ + c = (UCHAR_T) *p++; \ + } while (0) + +/* Go backwards one character in the pattern. */ +# define PATUNFETCH p-- + + +/* If `translate' is non-null, return translate[D], else just D. We + cast the subscript to translate because some data is declared as + `char *', to avoid warnings when a string constant is passed. But + when we use a character as a subscript we must make it unsigned. */ +/* ifdef MBS_SUPPORT, we translate only if character <= 0xff, + because it is impossible to allocate 4GB array for some encodings + which have 4 byte character_set like UCS4. */ + +# ifndef TRANSLATE +# ifdef WCHAR +# define TRANSLATE(d) \ + ((translate && ((UCHAR_T) (d)) <= 0xff) \ + ? (char) translate[(unsigned char) (d)] : (d)) +# else /* BYTE */ +# define TRANSLATE(d) \ + (translate ? (char) translate[(unsigned char) (d)] : (char) (d)) +# endif /* WCHAR */ +# endif + + +/* Macros for outputting the compiled pattern into `buffer'. */ + +/* If the buffer isn't allocated when it comes in, use this. */ +# define INIT_BUF_SIZE (32 * sizeof(UCHAR_T)) + +/* Make sure we have at least N more bytes of space in buffer. */ +# ifdef WCHAR +# define GET_BUFFER_SPACE(n) \ + while (((unsigned long)b - (unsigned long)COMPILED_BUFFER_VAR \ + + (n)*sizeof(CHAR_T)) > bufp->allocated) \ + EXTEND_BUFFER () +# else /* BYTE */ +# define GET_BUFFER_SPACE(n) \ + while ((unsigned long) (b - bufp->buffer + (n)) > bufp->allocated) \ + EXTEND_BUFFER () +# endif /* WCHAR */ + +/* Make sure we have one more byte of buffer space and then add C to it. */ +# define BUF_PUSH(c) \ + do { \ + GET_BUFFER_SPACE (1); \ + *b++ = (UCHAR_T) (c); \ + } while (0) + + +/* Ensure we have two more bytes of buffer space and then append C1 and C2. */ +# define BUF_PUSH_2(c1, c2) \ + do { \ + GET_BUFFER_SPACE (2); \ + *b++ = (UCHAR_T) (c1); \ + *b++ = (UCHAR_T) (c2); \ + } while (0) + + +/* As with BUF_PUSH_2, except for three bytes. */ +# define BUF_PUSH_3(c1, c2, c3) \ + do { \ + GET_BUFFER_SPACE (3); \ + *b++ = (UCHAR_T) (c1); \ + *b++ = (UCHAR_T) (c2); \ + *b++ = (UCHAR_T) (c3); \ + } while (0) + +/* Store a jump with opcode OP at LOC to location TO. We store a + relative address offset by the three bytes the jump itself occupies. */ +# define STORE_JUMP(op, loc, to) \ + PREFIX(store_op1) (op, loc, (int) ((to) - (loc) - (1 + OFFSET_ADDRESS_SIZE))) + +/* Likewise, for a two-argument jump. */ +# define STORE_JUMP2(op, loc, to, arg) \ + PREFIX(store_op2) (op, loc, (int) ((to) - (loc) - (1 + OFFSET_ADDRESS_SIZE)), arg) + +/* Like `STORE_JUMP', but for inserting. Assume `b' is the buffer end. */ +# define INSERT_JUMP(op, loc, to) \ + PREFIX(insert_op1) (op, loc, (int) ((to) - (loc) - (1 + OFFSET_ADDRESS_SIZE)), b) + +/* Like `STORE_JUMP2', but for inserting. Assume `b' is the buffer end. */ +# define INSERT_JUMP2(op, loc, to, arg) \ + PREFIX(insert_op2) (op, loc, (int) ((to) - (loc) - (1 + OFFSET_ADDRESS_SIZE)),\ + arg, b) + +/* This is not an arbitrary limit: the arguments which represent offsets + into the pattern are two bytes long. So if 2^16 bytes turns out to + be too small, many things would have to change. */ +/* Any other compiler which, like MSC, has allocation limit below 2^16 + bytes will have to use approach similar to what was done below for + MSC and drop MAX_BUF_SIZE a bit. Otherwise you may end up + reallocating to 0 bytes. Such thing is not going to work too well. + You have been warned!! */ +# ifndef DEFINED_ONCE +# if defined _MSC_VER && !defined WIN32 +/* Microsoft C 16-bit versions limit malloc to approx 65512 bytes. + The REALLOC define eliminates a flurry of conversion warnings, + but is not required. */ +# define MAX_BUF_SIZE 65500L +# define REALLOC(p,s) realloc ((p), (size_t) (s)) +# else +# define MAX_BUF_SIZE (1L << 16) +# define REALLOC(p,s) realloc ((p), (s)) +# endif + +/* Extend the buffer by twice its current size via realloc and + reset the pointers that pointed into the old block to point to the + correct places in the new one. If extending the buffer results in it + being larger than MAX_BUF_SIZE, then flag memory exhausted. */ +# if __BOUNDED_POINTERS__ +# define SET_HIGH_BOUND(P) (__ptrhigh (P) = __ptrlow (P) + bufp->allocated) +# define MOVE_BUFFER_POINTER(P) \ + (__ptrlow (P) += incr, SET_HIGH_BOUND (P), __ptrvalue (P) += incr) +# define ELSE_EXTEND_BUFFER_HIGH_BOUND \ + else \ + { \ + SET_HIGH_BOUND (b); \ + SET_HIGH_BOUND (begalt); \ + if (fixup_alt_jump) \ + SET_HIGH_BOUND (fixup_alt_jump); \ + if (laststart) \ + SET_HIGH_BOUND (laststart); \ + if (pending_exact) \ + SET_HIGH_BOUND (pending_exact); \ + } +# else +# define MOVE_BUFFER_POINTER(P) (P) += incr +# define ELSE_EXTEND_BUFFER_HIGH_BOUND +# endif +# endif /* not DEFINED_ONCE */ + +# ifdef WCHAR +# define EXTEND_BUFFER() \ + do { \ + UCHAR_T *old_buffer = COMPILED_BUFFER_VAR; \ + int wchar_count; \ + if (bufp->allocated + sizeof(UCHAR_T) > MAX_BUF_SIZE) \ + return REG_ESIZE; \ + bufp->allocated <<= 1; \ + if (bufp->allocated > MAX_BUF_SIZE) \ + bufp->allocated = MAX_BUF_SIZE; \ + /* How many characters the new buffer can have? */ \ + wchar_count = bufp->allocated / sizeof(UCHAR_T); \ + if (wchar_count == 0) wchar_count = 1; \ + /* Truncate the buffer to CHAR_T align. */ \ + bufp->allocated = wchar_count * sizeof(UCHAR_T); \ + RETALLOC (COMPILED_BUFFER_VAR, wchar_count, UCHAR_T); \ + bufp->buffer = (char*)COMPILED_BUFFER_VAR; \ + if (COMPILED_BUFFER_VAR == NULL) \ + return REG_ESPACE; \ + /* If the buffer moved, move all the pointers into it. */ \ + if (old_buffer != COMPILED_BUFFER_VAR) \ + { \ + int incr = COMPILED_BUFFER_VAR - old_buffer; \ + MOVE_BUFFER_POINTER (b); \ + MOVE_BUFFER_POINTER (begalt); \ + if (fixup_alt_jump) \ + MOVE_BUFFER_POINTER (fixup_alt_jump); \ + if (laststart) \ + MOVE_BUFFER_POINTER (laststart); \ + if (pending_exact) \ + MOVE_BUFFER_POINTER (pending_exact); \ + } \ + ELSE_EXTEND_BUFFER_HIGH_BOUND \ + } while (0) +# else /* BYTE */ +# define EXTEND_BUFFER() \ + do { \ + UCHAR_T *old_buffer = COMPILED_BUFFER_VAR; \ + if (bufp->allocated == MAX_BUF_SIZE) \ + return REG_ESIZE; \ + bufp->allocated <<= 1; \ + if (bufp->allocated > MAX_BUF_SIZE) \ + bufp->allocated = MAX_BUF_SIZE; \ + bufp->buffer = (UCHAR_T *) REALLOC (COMPILED_BUFFER_VAR, \ + bufp->allocated); \ + if (COMPILED_BUFFER_VAR == NULL) \ + return REG_ESPACE; \ + /* If the buffer moved, move all the pointers into it. */ \ + if (old_buffer != COMPILED_BUFFER_VAR) \ + { \ + int incr = COMPILED_BUFFER_VAR - old_buffer; \ + MOVE_BUFFER_POINTER (b); \ + MOVE_BUFFER_POINTER (begalt); \ + if (fixup_alt_jump) \ + MOVE_BUFFER_POINTER (fixup_alt_jump); \ + if (laststart) \ + MOVE_BUFFER_POINTER (laststart); \ + if (pending_exact) \ + MOVE_BUFFER_POINTER (pending_exact); \ + } \ + ELSE_EXTEND_BUFFER_HIGH_BOUND \ + } while (0) +# endif /* WCHAR */ + +# ifndef DEFINED_ONCE +/* Since we have one byte reserved for the register number argument to + {start,stop}_memory, the maximum number of groups we can report + things about is what fits in that byte. */ +# define MAX_REGNUM 255 + +/* But patterns can have more than `MAX_REGNUM' registers. We just + ignore the excess. */ +typedef unsigned regnum_t; + + +/* Macros for the compile stack. */ + +/* Since offsets can go either forwards or backwards, this type needs to + be able to hold values from -(MAX_BUF_SIZE - 1) to MAX_BUF_SIZE - 1. */ +/* int may be not enough when sizeof(int) == 2. */ +typedef long pattern_offset_t; + +typedef struct +{ + pattern_offset_t begalt_offset; + pattern_offset_t fixup_alt_jump; + pattern_offset_t inner_group_offset; + pattern_offset_t laststart_offset; + regnum_t regnum; +} compile_stack_elt_t; + + +typedef struct +{ + compile_stack_elt_t *stack; + unsigned size; + unsigned avail; /* Offset of next open position. */ +} compile_stack_type; + + +# define INIT_COMPILE_STACK_SIZE 32 + +# define COMPILE_STACK_EMPTY (compile_stack.avail == 0) +# define COMPILE_STACK_FULL (compile_stack.avail == compile_stack.size) + +/* The next available element. */ +# define COMPILE_STACK_TOP (compile_stack.stack[compile_stack.avail]) + +# endif /* not DEFINED_ONCE */ + +/* Set the bit for character C in a list. */ +# ifndef DEFINED_ONCE +# define SET_LIST_BIT(c) \ + (b[((unsigned char) (c)) / BYTEWIDTH] \ + |= 1 << (((unsigned char) c) % BYTEWIDTH)) +# endif /* DEFINED_ONCE */ + +/* Get the next unsigned number in the uncompiled pattern. */ +# define GET_UNSIGNED_NUMBER(num) \ + { \ + while (p != pend) \ + { \ + PATFETCH (c); \ + if (c < '0' || c > '9') \ + break; \ + if (num <= RE_DUP_MAX) \ + { \ + if (num < 0) \ + num = 0; \ + num = num * 10 + c - '0'; \ + } \ + } \ + } + +# ifndef DEFINED_ONCE +# if defined _LIBC || WIDE_CHAR_SUPPORT +/* The GNU C library provides support for user-defined character classes + and the functions from ISO C amendement 1. */ +# ifdef CHARCLASS_NAME_MAX +# define CHAR_CLASS_MAX_LENGTH CHARCLASS_NAME_MAX +# else +/* This shouldn't happen but some implementation might still have this + problem. Use a reasonable default value. */ +# define CHAR_CLASS_MAX_LENGTH 256 +# endif + +# ifdef _LIBC +# define IS_CHAR_CLASS(string) __wctype (string) +# else +# define IS_CHAR_CLASS(string) wctype (string) +# endif +# else +# define CHAR_CLASS_MAX_LENGTH 6 /* Namely, `xdigit'. */ + +# define IS_CHAR_CLASS(string) \ + (STREQ (string, "alpha") || STREQ (string, "upper") \ + || STREQ (string, "lower") || STREQ (string, "digit") \ + || STREQ (string, "alnum") || STREQ (string, "xdigit") \ + || STREQ (string, "space") || STREQ (string, "print") \ + || STREQ (string, "punct") || STREQ (string, "graph") \ + || STREQ (string, "cntrl") || STREQ (string, "blank")) +# endif +# endif /* DEFINED_ONCE */ + +# ifndef MATCH_MAY_ALLOCATE + +/* If we cannot allocate large objects within re_match_2_internal, + we make the fail stack and register vectors global. + The fail stack, we grow to the maximum size when a regexp + is compiled. + The register vectors, we adjust in size each time we + compile a regexp, according to the number of registers it needs. */ + +static PREFIX(fail_stack_type) fail_stack; + +/* Size with which the following vectors are currently allocated. + That is so we can make them bigger as needed, + but never make them smaller. */ +# ifdef DEFINED_ONCE +static int regs_allocated_size; + +static const char ** regstart, ** regend; +static const char ** old_regstart, ** old_regend; +static const char **best_regstart, **best_regend; +static const char **reg_dummy; +# endif /* DEFINED_ONCE */ + +static PREFIX(register_info_type) *PREFIX(reg_info); +static PREFIX(register_info_type) *PREFIX(reg_info_dummy); + +/* Make the register vectors big enough for NUM_REGS registers, + but don't make them smaller. */ + +static void +PREFIX(regex_grow_registers) (int num_regs) +{ + if (num_regs > regs_allocated_size) + { + RETALLOC_IF (regstart, num_regs, const char *); + RETALLOC_IF (regend, num_regs, const char *); + RETALLOC_IF (old_regstart, num_regs, const char *); + RETALLOC_IF (old_regend, num_regs, const char *); + RETALLOC_IF (best_regstart, num_regs, const char *); + RETALLOC_IF (best_regend, num_regs, const char *); + RETALLOC_IF (PREFIX(reg_info), num_regs, PREFIX(register_info_type)); + RETALLOC_IF (reg_dummy, num_regs, const char *); + RETALLOC_IF (PREFIX(reg_info_dummy), num_regs, PREFIX(register_info_type)); + + regs_allocated_size = num_regs; + } +} + +# endif /* not MATCH_MAY_ALLOCATE */ + +# ifndef DEFINED_ONCE +static boolean group_in_compile_stack (compile_stack_type compile_stack, + regnum_t regnum); +# endif /* not DEFINED_ONCE */ + +/* `regex_compile' compiles PATTERN (of length SIZE) according to SYNTAX. + Returns one of error codes defined in `regex.h', or zero for success. + + Assumes the `allocated' (and perhaps `buffer') and `translate' + fields are set in BUFP on entry. + + If it succeeds, results are put in BUFP (if it returns an error, the + contents of BUFP are undefined): + `buffer' is the compiled pattern; + `syntax' is set to SYNTAX; + `used' is set to the length of the compiled pattern; + `fastmap_accurate' is zero; + `re_nsub' is the number of subexpressions in PATTERN; + `not_bol' and `not_eol' are zero; + + The `fastmap' and `newline_anchor' fields are neither + examined nor set. */ + +/* Return, freeing storage we allocated. */ +# ifdef WCHAR +# define FREE_STACK_RETURN(value) \ + return (free(pattern), free(mbs_offset), free(is_binary), free (compile_stack.stack), value) +# else +# define FREE_STACK_RETURN(value) \ + return (free (compile_stack.stack), value) +# endif /* WCHAR */ + +static reg_errcode_t +PREFIX(regex_compile) (const char *ARG_PREFIX(pattern), + size_t ARG_PREFIX(size), reg_syntax_t syntax, + struct re_pattern_buffer *bufp) +{ + /* We fetch characters from PATTERN here. Even though PATTERN is + `char *' (i.e., signed), we declare these variables as unsigned, so + they can be reliably used as array indices. */ + register UCHAR_T c, c1; + +#ifdef WCHAR + /* A temporary space to keep wchar_t pattern and compiled pattern. */ + CHAR_T *pattern, *COMPILED_BUFFER_VAR; + size_t size; + /* offset buffer for optimization. See convert_mbs_to_wc. */ + int *mbs_offset = NULL; + /* It hold whether each wchar_t is binary data or not. */ + char *is_binary = NULL; + /* A flag whether exactn is handling binary data or not. */ + char is_exactn_bin = FALSE; +#endif /* WCHAR */ + + /* A random temporary spot in PATTERN. */ + const CHAR_T *p1; + + /* Points to the end of the buffer, where we should append. */ + register UCHAR_T *b; + + /* Keeps track of unclosed groups. */ + compile_stack_type compile_stack; + + /* Points to the current (ending) position in the pattern. */ +#ifdef WCHAR + const CHAR_T *p; + const CHAR_T *pend; +#else /* BYTE */ + const CHAR_T *p = pattern; + const CHAR_T *pend = pattern + size; +#endif /* WCHAR */ + + /* How to translate the characters in the pattern. */ + RE_TRANSLATE_TYPE translate = bufp->translate; + + /* Address of the count-byte of the most recently inserted `exactn' + command. This makes it possible to tell if a new exact-match + character can be added to that command or if the character requires + a new `exactn' command. */ + UCHAR_T *pending_exact = 0; + + /* Address of start of the most recently finished expression. + This tells, e.g., postfix * where to find the start of its + operand. Reset at the beginning of groups and alternatives. */ + UCHAR_T *laststart = 0; + + /* Address of beginning of regexp, or inside of last group. */ + UCHAR_T *begalt; + + /* Address of the place where a forward jump should go to the end of + the containing expression. Each alternative of an `or' -- except the + last -- ends with a forward jump of this sort. */ + UCHAR_T *fixup_alt_jump = 0; + + /* Counts open-groups as they are encountered. Remembered for the + matching close-group on the compile stack, so the same register + number is put in the stop_memory as the start_memory. */ + regnum_t regnum = 0; + +#ifdef WCHAR + /* Initialize the wchar_t PATTERN and offset_buffer. */ + p = pend = pattern = TALLOC(csize + 1, CHAR_T); + mbs_offset = TALLOC(csize + 1, int); + is_binary = TALLOC(csize + 1, char); + if (pattern == NULL || mbs_offset == NULL || is_binary == NULL) + { + free(pattern); + free(mbs_offset); + free(is_binary); + return REG_ESPACE; + } + pattern[csize] = L'\0'; /* sentinel */ + size = convert_mbs_to_wcs(pattern, cpattern, csize, mbs_offset, is_binary); + pend = p + size; + if (size < 0) + { + free(pattern); + free(mbs_offset); + free(is_binary); + return REG_BADPAT; + } +#endif + +#ifdef DEBUG + DEBUG_PRINT1 ("\nCompiling pattern: "); + if (debug) + { + unsigned debug_count; + + for (debug_count = 0; debug_count < size; debug_count++) + PUT_CHAR (pattern[debug_count]); + putchar ('\n'); + } +#endif /* DEBUG */ + + /* Initialize the compile stack. */ + compile_stack.stack = TALLOC (INIT_COMPILE_STACK_SIZE, compile_stack_elt_t); + if (compile_stack.stack == NULL) + { +#ifdef WCHAR + free(pattern); + free(mbs_offset); + free(is_binary); +#endif + return REG_ESPACE; + } + + compile_stack.size = INIT_COMPILE_STACK_SIZE; + compile_stack.avail = 0; + + /* Initialize the pattern buffer. */ + bufp->syntax = syntax; + bufp->fastmap_accurate = 0; + bufp->not_bol = bufp->not_eol = 0; + + /* Set `used' to zero, so that if we return an error, the pattern + printer (for debugging) will think there's no pattern. We reset it + at the end. */ + bufp->used = 0; + + /* Always count groups, whether or not bufp->no_sub is set. */ + bufp->re_nsub = 0; + +#if !defined emacs && !defined SYNTAX_TABLE + /* Initialize the syntax table. */ + init_syntax_once (); +#endif + + if (bufp->allocated == 0) + { + if (bufp->buffer) + { /* If zero allocated, but buffer is non-null, try to realloc + enough space. This loses if buffer's address is bogus, but + that is the user's responsibility. */ +#ifdef WCHAR + /* Free bufp->buffer and allocate an array for wchar_t pattern + buffer. */ + free(bufp->buffer); + COMPILED_BUFFER_VAR = TALLOC (INIT_BUF_SIZE/sizeof(UCHAR_T), + UCHAR_T); +#else + RETALLOC (COMPILED_BUFFER_VAR, INIT_BUF_SIZE, UCHAR_T); +#endif /* WCHAR */ + } + else + { /* Caller did not allocate a buffer. Do it for them. */ + COMPILED_BUFFER_VAR = TALLOC (INIT_BUF_SIZE / sizeof(UCHAR_T), + UCHAR_T); + } + + if (!COMPILED_BUFFER_VAR) FREE_STACK_RETURN (REG_ESPACE); +#ifdef WCHAR + bufp->buffer = (char*)COMPILED_BUFFER_VAR; +#endif /* WCHAR */ + bufp->allocated = INIT_BUF_SIZE; + } +#ifdef WCHAR + else + COMPILED_BUFFER_VAR = (UCHAR_T*) bufp->buffer; +#endif + + begalt = b = COMPILED_BUFFER_VAR; + + /* Loop through the uncompiled pattern until we're at the end. */ + while (p != pend) + { + PATFETCH (c); + + switch (c) + { + case '^': + { + if ( /* If at start of pattern, it's an operator. */ + p == pattern + 1 + /* If context independent, it's an operator. */ + || syntax & RE_CONTEXT_INDEP_ANCHORS + /* Otherwise, depends on what's come before. */ + || PREFIX(at_begline_loc_p) (pattern, p, syntax)) + BUF_PUSH (begline); + else + goto normal_char; + } + break; + + + case '$': + { + if ( /* If at end of pattern, it's an operator. */ + p == pend + /* If context independent, it's an operator. */ + || syntax & RE_CONTEXT_INDEP_ANCHORS + /* Otherwise, depends on what's next. */ + || PREFIX(at_endline_loc_p) (p, pend, syntax)) + BUF_PUSH (endline); + else + goto normal_char; + } + break; + + + case '+': + case '?': + if ((syntax & RE_BK_PLUS_QM) + || (syntax & RE_LIMITED_OPS)) + goto normal_char; + handle_plus: + case '*': + /* If there is no previous pattern... */ + if (!laststart) + { + if (syntax & RE_CONTEXT_INVALID_OPS) + FREE_STACK_RETURN (REG_BADRPT); + else if (!(syntax & RE_CONTEXT_INDEP_OPS)) + goto normal_char; + } + + { + /* Are we optimizing this jump? */ + boolean keep_string_p = false; + + /* 1 means zero (many) matches is allowed. */ + char zero_times_ok = 0, many_times_ok = 0; + + /* If there is a sequence of repetition chars, collapse it + down to just one (the right one). We can't combine + interval operators with these because of, e.g., `a{2}*', + which should only match an even number of `a's. */ + + for (;;) + { + zero_times_ok |= c != '+'; + many_times_ok |= c != '?'; + + if (p == pend) + break; + + PATFETCH (c); + + if (c == '*' + || (!(syntax & RE_BK_PLUS_QM) && (c == '+' || c == '?'))) + ; + + else if (syntax & RE_BK_PLUS_QM && c == '\\') + { + if (p == pend) FREE_STACK_RETURN (REG_EESCAPE); + + PATFETCH (c1); + if (!(c1 == '+' || c1 == '?')) + { + PATUNFETCH; + PATUNFETCH; + break; + } + + c = c1; + } + else + { + PATUNFETCH; + break; + } + + /* If we get here, we found another repeat character. */ + } + + /* Star, etc. applied to an empty pattern is equivalent + to an empty pattern. */ + if (!laststart) + break; + + /* Now we know whether or not zero matches is allowed + and also whether or not two or more matches is allowed. */ + if (many_times_ok) + { /* More than one repetition is allowed, so put in at the + end a backward relative jump from `b' to before the next + jump we're going to put in below (which jumps from + laststart to after this jump). + + But if we are at the `*' in the exact sequence `.*\n', + insert an unconditional jump backwards to the ., + instead of the beginning of the loop. This way we only + push a failure point once, instead of every time + through the loop. */ + assert (p - 1 > pattern); + + /* Allocate the space for the jump. */ + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + + /* We know we are not at the first character of the pattern, + because laststart was nonzero. And we've already + incremented `p', by the way, to be the character after + the `*'. Do we have to do something analogous here + for null bytes, because of RE_DOT_NOT_NULL? */ + if (TRANSLATE (*(p - 2)) == TRANSLATE ('.') + && zero_times_ok + && p < pend && TRANSLATE (*p) == TRANSLATE ('\n') + && !(syntax & RE_DOT_NEWLINE)) + { /* We have .*\n. */ + STORE_JUMP (jump, b, laststart); + keep_string_p = true; + } + else + /* Anything else. */ + STORE_JUMP (maybe_pop_jump, b, laststart - + (1 + OFFSET_ADDRESS_SIZE)); + + /* We've added more stuff to the buffer. */ + b += 1 + OFFSET_ADDRESS_SIZE; + } + + /* On failure, jump from laststart to b + 3, which will be the + end of the buffer after this jump is inserted. */ + /* ifdef WCHAR, 'b + 1 + OFFSET_ADDRESS_SIZE' instead of + 'b + 3'. */ + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + INSERT_JUMP (keep_string_p ? on_failure_keep_string_jump + : on_failure_jump, + laststart, b + 1 + OFFSET_ADDRESS_SIZE); + pending_exact = 0; + b += 1 + OFFSET_ADDRESS_SIZE; + + if (!zero_times_ok) + { + /* At least one repetition is required, so insert a + `dummy_failure_jump' before the initial + `on_failure_jump' instruction of the loop. This + effects a skip over that instruction the first time + we hit that loop. */ + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + INSERT_JUMP (dummy_failure_jump, laststart, laststart + + 2 + 2 * OFFSET_ADDRESS_SIZE); + b += 1 + OFFSET_ADDRESS_SIZE; + } + } + break; + + + case '.': + laststart = b; + BUF_PUSH (anychar); + break; + + + case '[': + { + boolean had_char_class = false; +#ifdef WCHAR + CHAR_T range_start = 0xffffffff; +#else + unsigned int range_start = 0xffffffff; +#endif + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + +#ifdef WCHAR + /* We assume a charset(_not) structure as a wchar_t array. + charset[0] = (re_opcode_t) charset(_not) + charset[1] = l (= length of char_classes) + charset[2] = m (= length of collating_symbols) + charset[3] = n (= length of equivalence_classes) + charset[4] = o (= length of char_ranges) + charset[5] = p (= length of chars) + + charset[6] = char_class (wctype_t) + charset[6+CHAR_CLASS_SIZE] = char_class (wctype_t) + ... + charset[l+5] = char_class (wctype_t) + + charset[l+6] = collating_symbol (wchar_t) + ... + charset[l+m+5] = collating_symbol (wchar_t) + ifdef _LIBC we use the index if + _NL_COLLATE_SYMB_EXTRAMB instead of + wchar_t string. + + charset[l+m+6] = equivalence_classes (wchar_t) + ... + charset[l+m+n+5] = equivalence_classes (wchar_t) + ifdef _LIBC we use the index in + _NL_COLLATE_WEIGHT instead of + wchar_t string. + + charset[l+m+n+6] = range_start + charset[l+m+n+7] = range_end + ... + charset[l+m+n+2o+4] = range_start + charset[l+m+n+2o+5] = range_end + ifdef _LIBC we use the value looked up + in _NL_COLLATE_COLLSEQ instead of + wchar_t character. + + charset[l+m+n+2o+6] = char + ... + charset[l+m+n+2o+p+5] = char + + */ + + /* We need at least 6 spaces: the opcode, the length of + char_classes, the length of collating_symbols, the length of + equivalence_classes, the length of char_ranges, the length of + chars. */ + GET_BUFFER_SPACE (6); + + /* Save b as laststart. And We use laststart as the pointer + to the first element of the charset here. + In other words, laststart[i] indicates charset[i]. */ + laststart = b; + + /* We test `*p == '^' twice, instead of using an if + statement, so we only need one BUF_PUSH. */ + BUF_PUSH (*p == '^' ? charset_not : charset); + if (*p == '^') + p++; + + /* Push the length of char_classes, the length of + collating_symbols, the length of equivalence_classes, the + length of char_ranges and the length of chars. */ + BUF_PUSH_3 (0, 0, 0); + BUF_PUSH_2 (0, 0); + + /* Remember the first position in the bracket expression. */ + p1 = p; + + /* charset_not matches newline according to a syntax bit. */ + if ((re_opcode_t) b[-6] == charset_not + && (syntax & RE_HAT_LISTS_NOT_NEWLINE)) + { + BUF_PUSH('\n'); + laststart[5]++; /* Update the length of characters */ + } + + /* Read in characters and ranges, setting map bits. */ + for (;;) + { + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + PATFETCH (c); + + /* \ might escape characters inside [...] and [^...]. */ + if ((syntax & RE_BACKSLASH_ESCAPE_IN_LISTS) && c == '\\') + { + if (p == pend) FREE_STACK_RETURN (REG_EESCAPE); + + PATFETCH (c1); + BUF_PUSH(c1); + laststart[5]++; /* Update the length of chars */ + range_start = c1; + continue; + } + + /* Could be the end of the bracket expression. If it's + not (i.e., when the bracket expression is `[]' so + far), the ']' character bit gets set way below. */ + if (c == ']' && p != p1 + 1) + break; + + /* Look ahead to see if it's a range when the last thing + was a character class. */ + if (had_char_class && c == '-' && *p != ']') + FREE_STACK_RETURN (REG_ERANGE); + + /* Look ahead to see if it's a range when the last thing + was a character: if this is a hyphen not at the + beginning or the end of a list, then it's the range + operator. */ + if (c == '-' + && !(p - 2 >= pattern && p[-2] == '[') + && !(p - 3 >= pattern && p[-3] == '[' && p[-2] == '^') + && *p != ']') + { + reg_errcode_t ret; + /* Allocate the space for range_start and range_end. */ + GET_BUFFER_SPACE (2); + /* Update the pointer to indicate end of buffer. */ + b += 2; + ret = wcs_compile_range (range_start, &p, pend, translate, + syntax, b, laststart); + if (ret != REG_NOERROR) FREE_STACK_RETURN (ret); + range_start = 0xffffffff; + } + else if (p[0] == '-' && p[1] != ']') + { /* This handles ranges made up of characters only. */ + reg_errcode_t ret; + + /* Move past the `-'. */ + PATFETCH (c1); + /* Allocate the space for range_start and range_end. */ + GET_BUFFER_SPACE (2); + /* Update the pointer to indicate end of buffer. */ + b += 2; + ret = wcs_compile_range (c, &p, pend, translate, syntax, b, + laststart); + if (ret != REG_NOERROR) FREE_STACK_RETURN (ret); + range_start = 0xffffffff; + } + + /* See if we're at the beginning of a possible character + class. */ + else if (syntax & RE_CHAR_CLASSES && c == '[' && *p == ':') + { /* Leave room for the null. */ + char str[CHAR_CLASS_MAX_LENGTH + 1]; + + PATFETCH (c); + c1 = 0; + + /* If pattern is `[[:'. */ + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (;;) + { + PATFETCH (c); + if ((c == ':' && *p == ']') || p == pend) + break; + if (c1 < CHAR_CLASS_MAX_LENGTH) + str[c1++] = c; + else + /* This is in any case an invalid class name. */ + str[0] = '\0'; + } + str[c1] = '\0'; + + /* If isn't a word bracketed by `[:' and `:]': + undo the ending character, the letters, and leave + the leading `:' and `[' (but store them as character). */ + if (c == ':' && *p == ']') + { + wctype_t wt; + uintptr_t alignedp; + + /* Query the character class as wctype_t. */ + wt = IS_CHAR_CLASS (str); + if (wt == 0) + FREE_STACK_RETURN (REG_ECTYPE); + + /* Throw away the ] at the end of the character + class. */ + PATFETCH (c); + + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + /* Allocate the space for character class. */ + GET_BUFFER_SPACE(CHAR_CLASS_SIZE); + /* Update the pointer to indicate end of buffer. */ + b += CHAR_CLASS_SIZE; + /* Move data which follow character classes + not to violate the data. */ + insert_space(CHAR_CLASS_SIZE, + laststart + 6 + laststart[1], + b - 1); + alignedp = ((uintptr_t)(laststart + 6 + laststart[1]) + + __alignof__(wctype_t) - 1) + & ~(uintptr_t)(__alignof__(wctype_t) - 1); + /* Store the character class. */ + *((wctype_t*)alignedp) = wt; + /* Update length of char_classes */ + laststart[1] += CHAR_CLASS_SIZE; + + had_char_class = true; + } + else + { + c1++; + while (c1--) + PATUNFETCH; + BUF_PUSH ('['); + BUF_PUSH (':'); + laststart[5] += 2; /* Update the length of characters */ + range_start = ':'; + had_char_class = false; + } + } + else if (syntax & RE_CHAR_CLASSES && c == '[' && (*p == '=' + || *p == '.')) + { + CHAR_T str[128]; /* Should be large enough. */ + CHAR_T delim = *p; /* '=' or '.' */ +# ifdef _LIBC + uint32_t nrules = + _NL_CURRENT_WORD (LC_COLLATE, _NL_COLLATE_NRULES); +# endif + PATFETCH (c); + c1 = 0; + + /* If pattern is `[[=' or '[[.'. */ + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (;;) + { + PATFETCH (c); + if ((c == delim && *p == ']') || p == pend) + break; + if (c1 < sizeof (str) - 1) + str[c1++] = c; + else + /* This is in any case an invalid class name. */ + str[0] = '\0'; + } + str[c1] = '\0'; + + if (c == delim && *p == ']' && str[0] != '\0') + { + unsigned int i, offset; + /* If we have no collation data we use the default + collation in which each character is in a class + by itself. It also means that ASCII is the + character set and therefore we cannot have character + with more than one byte in the multibyte + representation. */ + + /* If not defined _LIBC, we push the name and + `\0' for the sake of matching performance. */ + int datasize = c1 + 1; + +# ifdef _LIBC + int32_t idx = 0; + if (nrules == 0) +# endif + { + if (c1 != 1) + FREE_STACK_RETURN (REG_ECOLLATE); + } +# ifdef _LIBC + else + { + const int32_t *table; + const int32_t *weights; + const int32_t *extra; + const int32_t *indirect; + wint_t *cp; + + /* This #include defines a local function! */ +# include + + if(delim == '=') + { + /* We push the index for equivalence class. */ + cp = (wint_t*)str; + + table = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_TABLEWC); + weights = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_WEIGHTWC); + extra = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_EXTRAWC); + indirect = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_INDIRECTWC); + + idx = findidx ((const wint_t**)&cp); + if (idx == 0 || cp < (wint_t*) str + c1) + /* This is no valid character. */ + FREE_STACK_RETURN (REG_ECOLLATE); + + str[0] = (wchar_t)idx; + } + else /* delim == '.' */ + { + /* We push collation sequence value + for collating symbol. */ + int32_t table_size; + const int32_t *symb_table; + const unsigned char *extra; + int32_t idx; + int32_t elem; + int32_t second; + int32_t hash; + char char_str[c1]; + + /* We have to convert the name to a single-byte + string. This is possible since the names + consist of ASCII characters and the internal + representation is UCS4. */ + for (i = 0; i < c1; ++i) + char_str[i] = str[i]; + + table_size = + _NL_CURRENT_WORD (LC_COLLATE, + _NL_COLLATE_SYMB_HASH_SIZEMB); + symb_table = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_SYMB_TABLEMB); + extra = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_SYMB_EXTRAMB); + + /* Locate the character in the hashing table. */ + hash = elem_hash (char_str, c1); + + idx = 0; + elem = hash % table_size; + second = hash % (table_size - 2); + while (symb_table[2 * elem] != 0) + { + /* First compare the hashing value. */ + if (symb_table[2 * elem] == hash + && c1 == extra[symb_table[2 * elem + 1]] + && memcmp (char_str, + &extra[symb_table[2 * elem + 1] + + 1], c1) == 0) + { + /* Yep, this is the entry. */ + idx = symb_table[2 * elem + 1]; + idx += 1 + extra[idx]; + break; + } + + /* Next entry. */ + elem += second; + } + + if (symb_table[2 * elem] != 0) + { + /* Compute the index of the byte sequence + in the table. */ + idx += 1 + extra[idx]; + /* Adjust for the alignment. */ + idx = (idx + 3) & ~3; + + str[0] = (wchar_t) idx + 4; + } + else if (symb_table[2 * elem] == 0 && c1 == 1) + { + /* No valid character. Match it as a + single byte character. */ + had_char_class = false; + BUF_PUSH(str[0]); + /* Update the length of characters */ + laststart[5]++; + range_start = str[0]; + + /* Throw away the ] at the end of the + collating symbol. */ + PATFETCH (c); + /* exit from the switch block. */ + continue; + } + else + FREE_STACK_RETURN (REG_ECOLLATE); + } + datasize = 1; + } +# endif + /* Throw away the ] at the end of the equivalence + class (or collating symbol). */ + PATFETCH (c); + + /* Allocate the space for the equivalence class + (or collating symbol) (and '\0' if needed). */ + GET_BUFFER_SPACE(datasize); + /* Update the pointer to indicate end of buffer. */ + b += datasize; + + if (delim == '=') + { /* equivalence class */ + /* Calculate the offset of char_ranges, + which is next to equivalence_classes. */ + offset = laststart[1] + laststart[2] + + laststart[3] +6; + /* Insert space. */ + insert_space(datasize, laststart + offset, b - 1); + + /* Write the equivalence_class and \0. */ + for (i = 0 ; i < datasize ; i++) + laststart[offset + i] = str[i]; + + /* Update the length of equivalence_classes. */ + laststart[3] += datasize; + had_char_class = true; + } + else /* delim == '.' */ + { /* collating symbol */ + /* Calculate the offset of the equivalence_classes, + which is next to collating_symbols. */ + offset = laststart[1] + laststart[2] + 6; + /* Insert space and write the collationg_symbol + and \0. */ + insert_space(datasize, laststart + offset, b-1); + for (i = 0 ; i < datasize ; i++) + laststart[offset + i] = str[i]; + + /* In re_match_2_internal if range_start < -1, we + assume -range_start is the offset of the + collating symbol which is specified as + the character of the range start. So we assign + -(laststart[1] + laststart[2] + 6) to + range_start. */ + range_start = -(laststart[1] + laststart[2] + 6); + /* Update the length of collating_symbol. */ + laststart[2] += datasize; + had_char_class = false; + } + } + else + { + c1++; + while (c1--) + PATUNFETCH; + BUF_PUSH ('['); + BUF_PUSH (delim); + laststart[5] += 2; /* Update the length of characters */ + range_start = delim; + had_char_class = false; + } + } + else + { + had_char_class = false; + BUF_PUSH(c); + laststart[5]++; /* Update the length of characters */ + range_start = c; + } + } + +#else /* BYTE */ + /* Ensure that we have enough space to push a charset: the + opcode, the length count, and the bitset; 34 bytes in all. */ + GET_BUFFER_SPACE (34); + + laststart = b; + + /* We test `*p == '^' twice, instead of using an if + statement, so we only need one BUF_PUSH. */ + BUF_PUSH (*p == '^' ? charset_not : charset); + if (*p == '^') + p++; + + /* Remember the first position in the bracket expression. */ + p1 = p; + + /* Push the number of bytes in the bitmap. */ + BUF_PUSH ((1 << BYTEWIDTH) / BYTEWIDTH); + + /* Clear the whole map. */ + bzero (b, (1 << BYTEWIDTH) / BYTEWIDTH); + + /* charset_not matches newline according to a syntax bit. */ + if ((re_opcode_t) b[-2] == charset_not + && (syntax & RE_HAT_LISTS_NOT_NEWLINE)) + SET_LIST_BIT ('\n'); + + /* Read in characters and ranges, setting map bits. */ + for (;;) + { + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + PATFETCH (c); + + /* \ might escape characters inside [...] and [^...]. */ + if ((syntax & RE_BACKSLASH_ESCAPE_IN_LISTS) && c == '\\') + { + if (p == pend) FREE_STACK_RETURN (REG_EESCAPE); + + PATFETCH (c1); + SET_LIST_BIT (c1); + range_start = c1; + continue; + } + + /* Could be the end of the bracket expression. If it's + not (i.e., when the bracket expression is `[]' so + far), the ']' character bit gets set way below. */ + if (c == ']' && p != p1 + 1) + break; + + /* Look ahead to see if it's a range when the last thing + was a character class. */ + if (had_char_class && c == '-' && *p != ']') + FREE_STACK_RETURN (REG_ERANGE); + + /* Look ahead to see if it's a range when the last thing + was a character: if this is a hyphen not at the + beginning or the end of a list, then it's the range + operator. */ + if (c == '-' + && !(p - 2 >= pattern && p[-2] == '[') + && !(p - 3 >= pattern && p[-3] == '[' && p[-2] == '^') + && *p != ']') + { + reg_errcode_t ret + = byte_compile_range (range_start, &p, pend, translate, + syntax, b); + if (ret != REG_NOERROR) FREE_STACK_RETURN (ret); + range_start = 0xffffffff; + } + + else if (p[0] == '-' && p[1] != ']') + { /* This handles ranges made up of characters only. */ + reg_errcode_t ret; + + /* Move past the `-'. */ + PATFETCH (c1); + + ret = byte_compile_range (c, &p, pend, translate, syntax, b); + if (ret != REG_NOERROR) FREE_STACK_RETURN (ret); + range_start = 0xffffffff; + } + + /* See if we're at the beginning of a possible character + class. */ + + else if (syntax & RE_CHAR_CLASSES && c == '[' && *p == ':') + { /* Leave room for the null. */ + char str[CHAR_CLASS_MAX_LENGTH + 1]; + + PATFETCH (c); + c1 = 0; + + /* If pattern is `[[:'. */ + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (;;) + { + PATFETCH (c); + if ((c == ':' && *p == ']') || p == pend) + break; + if (c1 < CHAR_CLASS_MAX_LENGTH) + str[c1++] = c; + else + /* This is in any case an invalid class name. */ + str[0] = '\0'; + } + str[c1] = '\0'; + + /* If isn't a word bracketed by `[:' and `:]': + undo the ending character, the letters, and leave + the leading `:' and `[' (but set bits for them). */ + if (c == ':' && *p == ']') + { +# if defined _LIBC || WIDE_CHAR_SUPPORT + boolean is_lower = STREQ (str, "lower"); + boolean is_upper = STREQ (str, "upper"); + wctype_t wt; + int ch; + + wt = IS_CHAR_CLASS (str); + if (wt == 0) + FREE_STACK_RETURN (REG_ECTYPE); + + /* Throw away the ] at the end of the character + class. */ + PATFETCH (c); + + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (ch = 0; ch < 1 << BYTEWIDTH; ++ch) + { +# ifdef _LIBC + if (__iswctype (__btowc (ch), wt)) + SET_LIST_BIT (ch); +# else + if (iswctype (btowc (ch), wt)) + SET_LIST_BIT (ch); +# endif + + if (translate && (is_upper || is_lower) + && (ISUPPER (ch) || ISLOWER (ch))) + SET_LIST_BIT (ch); + } + + had_char_class = true; +# else + int ch; + boolean is_alnum = STREQ (str, "alnum"); + boolean is_alpha = STREQ (str, "alpha"); + boolean is_blank = STREQ (str, "blank"); + boolean is_cntrl = STREQ (str, "cntrl"); + boolean is_digit = STREQ (str, "digit"); + boolean is_graph = STREQ (str, "graph"); + boolean is_lower = STREQ (str, "lower"); + boolean is_print = STREQ (str, "print"); + boolean is_punct = STREQ (str, "punct"); + boolean is_space = STREQ (str, "space"); + boolean is_upper = STREQ (str, "upper"); + boolean is_xdigit = STREQ (str, "xdigit"); + + if (!IS_CHAR_CLASS (str)) + FREE_STACK_RETURN (REG_ECTYPE); + + /* Throw away the ] at the end of the character + class. */ + PATFETCH (c); + + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (ch = 0; ch < 1 << BYTEWIDTH; ch++) + { + /* This was split into 3 if's to + avoid an arbitrary limit in some compiler. */ + if ( (is_alnum && ISALNUM (ch)) + || (is_alpha && ISALPHA (ch)) + || (is_blank && ISBLANK (ch)) + || (is_cntrl && ISCNTRL (ch))) + SET_LIST_BIT (ch); + if ( (is_digit && ISDIGIT (ch)) + || (is_graph && ISGRAPH (ch)) + || (is_lower && ISLOWER (ch)) + || (is_print && ISPRINT (ch))) + SET_LIST_BIT (ch); + if ( (is_punct && ISPUNCT (ch)) + || (is_space && ISSPACE (ch)) + || (is_upper && ISUPPER (ch)) + || (is_xdigit && ISXDIGIT (ch))) + SET_LIST_BIT (ch); + if ( translate && (is_upper || is_lower) + && (ISUPPER (ch) || ISLOWER (ch))) + SET_LIST_BIT (ch); + } + had_char_class = true; +# endif /* libc || wctype.h */ + } + else + { + c1++; + while (c1--) + PATUNFETCH; + SET_LIST_BIT ('['); + SET_LIST_BIT (':'); + range_start = ':'; + had_char_class = false; + } + } + else if (syntax & RE_CHAR_CLASSES && c == '[' && *p == '=') + { + unsigned char str[MB_LEN_MAX + 1]; +# ifdef _LIBC + uint32_t nrules = + _NL_CURRENT_WORD (LC_COLLATE, _NL_COLLATE_NRULES); +# endif + + PATFETCH (c); + c1 = 0; + + /* If pattern is `[[='. */ + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (;;) + { + PATFETCH (c); + if ((c == '=' && *p == ']') || p == pend) + break; + if (c1 < MB_LEN_MAX) + str[c1++] = c; + else + /* This is in any case an invalid class name. */ + str[0] = '\0'; + } + str[c1] = '\0'; + + if (c == '=' && *p == ']' && str[0] != '\0') + { + /* If we have no collation data we use the default + collation in which each character is in a class + by itself. It also means that ASCII is the + character set and therefore we cannot have character + with more than one byte in the multibyte + representation. */ +# ifdef _LIBC + if (nrules == 0) +# endif + { + if (c1 != 1) + FREE_STACK_RETURN (REG_ECOLLATE); + + /* Throw away the ] at the end of the equivalence + class. */ + PATFETCH (c); + + /* Set the bit for the character. */ + SET_LIST_BIT (str[0]); + } +# ifdef _LIBC + else + { + /* Try to match the byte sequence in `str' against + those known to the collate implementation. + First find out whether the bytes in `str' are + actually from exactly one character. */ + const int32_t *table; + const unsigned char *weights; + const unsigned char *extra; + const int32_t *indirect; + int32_t idx; + const unsigned char *cp = str; + int ch; + + /* This #include defines a local function! */ +# include + + table = (const int32_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_TABLEMB); + weights = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_WEIGHTMB); + extra = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_EXTRAMB); + indirect = (const int32_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_INDIRECTMB); + + idx = findidx (&cp); + if (idx == 0 || cp < str + c1) + /* This is no valid character. */ + FREE_STACK_RETURN (REG_ECOLLATE); + + /* Throw away the ] at the end of the equivalence + class. */ + PATFETCH (c); + + /* Now we have to go throught the whole table + and find all characters which have the same + first level weight. + + XXX Note that this is not entirely correct. + we would have to match multibyte sequences + but this is not possible with the current + implementation. */ + for (ch = 1; ch < 256; ++ch) + /* XXX This test would have to be changed if we + would allow matching multibyte sequences. */ + if (table[ch] > 0) + { + int32_t idx2 = table[ch]; + size_t len = weights[idx2]; + + /* Test whether the lenghts match. */ + if (weights[idx] == len) + { + /* They do. New compare the bytes of + the weight. */ + size_t cnt = 0; + + while (cnt < len + && (weights[idx + 1 + cnt] + == weights[idx2 + 1 + cnt])) + ++cnt; + + if (cnt == len) + /* They match. Mark the character as + acceptable. */ + SET_LIST_BIT (ch); + } + } + } +# endif + had_char_class = true; + } + else + { + c1++; + while (c1--) + PATUNFETCH; + SET_LIST_BIT ('['); + SET_LIST_BIT ('='); + range_start = '='; + had_char_class = false; + } + } + else if (syntax & RE_CHAR_CLASSES && c == '[' && *p == '.') + { + unsigned char str[128]; /* Should be large enough. */ +# ifdef _LIBC + uint32_t nrules = + _NL_CURRENT_WORD (LC_COLLATE, _NL_COLLATE_NRULES); +# endif + + PATFETCH (c); + c1 = 0; + + /* If pattern is `[[.'. */ + if (p == pend) FREE_STACK_RETURN (REG_EBRACK); + + for (;;) + { + PATFETCH (c); + if ((c == '.' && *p == ']') || p == pend) + break; + if (c1 < sizeof (str)) + str[c1++] = c; + else + /* This is in any case an invalid class name. */ + str[0] = '\0'; + } + str[c1] = '\0'; + + if (c == '.' && *p == ']' && str[0] != '\0') + { + /* If we have no collation data we use the default + collation in which each character is the name + for its own class which contains only the one + character. It also means that ASCII is the + character set and therefore we cannot have character + with more than one byte in the multibyte + representation. */ +# ifdef _LIBC + if (nrules == 0) +# endif + { + if (c1 != 1) + FREE_STACK_RETURN (REG_ECOLLATE); + + /* Throw away the ] at the end of the equivalence + class. */ + PATFETCH (c); + + /* Set the bit for the character. */ + SET_LIST_BIT (str[0]); + range_start = ((const unsigned char *) str)[0]; + } +# ifdef _LIBC + else + { + /* Try to match the byte sequence in `str' against + those known to the collate implementation. + First find out whether the bytes in `str' are + actually from exactly one character. */ + int32_t table_size; + const int32_t *symb_table; + const unsigned char *extra; + int32_t idx; + int32_t elem; + int32_t second; + int32_t hash; + + table_size = + _NL_CURRENT_WORD (LC_COLLATE, + _NL_COLLATE_SYMB_HASH_SIZEMB); + symb_table = (const int32_t *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_SYMB_TABLEMB); + extra = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_SYMB_EXTRAMB); + + /* Locate the character in the hashing table. */ + hash = elem_hash (str, c1); + + idx = 0; + elem = hash % table_size; + second = hash % (table_size - 2); + while (symb_table[2 * elem] != 0) + { + /* First compare the hashing value. */ + if (symb_table[2 * elem] == hash + && c1 == extra[symb_table[2 * elem + 1]] + && memcmp (str, + &extra[symb_table[2 * elem + 1] + + 1], + c1) == 0) + { + /* Yep, this is the entry. */ + idx = symb_table[2 * elem + 1]; + idx += 1 + extra[idx]; + break; + } + + /* Next entry. */ + elem += second; + } + + if (symb_table[2 * elem] == 0) + /* This is no valid character. */ + FREE_STACK_RETURN (REG_ECOLLATE); + + /* Throw away the ] at the end of the equivalence + class. */ + PATFETCH (c); + + /* Now add the multibyte character(s) we found + to the accept list. + + XXX Note that this is not entirely correct. + we would have to match multibyte sequences + but this is not possible with the current + implementation. Also, we have to match + collating symbols, which expand to more than + one file, as a whole and not allow the + individual bytes. */ + c1 = extra[idx++]; + if (c1 == 1) + range_start = extra[idx]; + while (c1-- > 0) + { + SET_LIST_BIT (extra[idx]); + ++idx; + } + } +# endif + had_char_class = false; + } + else + { + c1++; + while (c1--) + PATUNFETCH; + SET_LIST_BIT ('['); + SET_LIST_BIT ('.'); + range_start = '.'; + had_char_class = false; + } + } + else + { + had_char_class = false; + SET_LIST_BIT (c); + range_start = c; + } + } + + /* Discard any (non)matching list bytes that are all 0 at the + end of the map. Decrease the map-length byte too. */ + while ((int) b[-1] > 0 && b[b[-1] - 1] == 0) + b[-1]--; + b += b[-1]; +#endif /* WCHAR */ + } + break; + + + case '(': + if (syntax & RE_NO_BK_PARENS) + goto handle_open; + else + goto normal_char; + + + case ')': + if (syntax & RE_NO_BK_PARENS) + goto handle_close; + else + goto normal_char; + + + case '\n': + if (syntax & RE_NEWLINE_ALT) + goto handle_alt; + else + goto normal_char; + + + case '|': + if (syntax & RE_NO_BK_VBAR) + goto handle_alt; + else + goto normal_char; + + + case '{': + if (syntax & RE_INTERVALS && syntax & RE_NO_BK_BRACES) + goto handle_interval; + else + goto normal_char; + + + case '\\': + if (p == pend) FREE_STACK_RETURN (REG_EESCAPE); + + /* Do not translate the character after the \, so that we can + distinguish, e.g., \B from \b, even if we normally would + translate, e.g., B to b. */ + PATFETCH_RAW (c); + + switch (c) + { + case '(': + if (syntax & RE_NO_BK_PARENS) + goto normal_backslash; + + handle_open: + bufp->re_nsub++; + regnum++; + + if (COMPILE_STACK_FULL) + { + RETALLOC (compile_stack.stack, compile_stack.size << 1, + compile_stack_elt_t); + if (compile_stack.stack == NULL) return REG_ESPACE; + + compile_stack.size <<= 1; + } + + /* These are the values to restore when we hit end of this + group. They are all relative offsets, so that if the + whole pattern moves because of realloc, they will still + be valid. */ + COMPILE_STACK_TOP.begalt_offset = begalt - COMPILED_BUFFER_VAR; + COMPILE_STACK_TOP.fixup_alt_jump + = fixup_alt_jump ? fixup_alt_jump - COMPILED_BUFFER_VAR + 1 : 0; + COMPILE_STACK_TOP.laststart_offset = b - COMPILED_BUFFER_VAR; + COMPILE_STACK_TOP.regnum = regnum; + + /* We will eventually replace the 0 with the number of + groups inner to this one. But do not push a + start_memory for groups beyond the last one we can + represent in the compiled pattern. */ + if (regnum <= MAX_REGNUM) + { + COMPILE_STACK_TOP.inner_group_offset = b + - COMPILED_BUFFER_VAR + 2; + BUF_PUSH_3 (start_memory, regnum, 0); + } + + compile_stack.avail++; + + fixup_alt_jump = 0; + laststart = 0; + begalt = b; + /* If we've reached MAX_REGNUM groups, then this open + won't actually generate any code, so we'll have to + clear pending_exact explicitly. */ + pending_exact = 0; + break; + + + case ')': + if (syntax & RE_NO_BK_PARENS) goto normal_backslash; + + if (COMPILE_STACK_EMPTY) + { + if (syntax & RE_UNMATCHED_RIGHT_PAREN_ORD) + goto normal_backslash; + else + FREE_STACK_RETURN (REG_ERPAREN); + } + + handle_close: + if (fixup_alt_jump) + { /* Push a dummy failure point at the end of the + alternative for a possible future + `pop_failure_jump' to pop. See comments at + `push_dummy_failure' in `re_match_2'. */ + BUF_PUSH (push_dummy_failure); + + /* We allocated space for this jump when we assigned + to `fixup_alt_jump', in the `handle_alt' case below. */ + STORE_JUMP (jump_past_alt, fixup_alt_jump, b - 1); + } + + /* See similar code for backslashed left paren above. */ + if (COMPILE_STACK_EMPTY) + { + if (syntax & RE_UNMATCHED_RIGHT_PAREN_ORD) + goto normal_char; + else + FREE_STACK_RETURN (REG_ERPAREN); + } + + /* Since we just checked for an empty stack above, this + ``can't happen''. */ + assert (compile_stack.avail != 0); + { + /* We don't just want to restore into `regnum', because + later groups should continue to be numbered higher, + as in `(ab)c(de)' -- the second group is #2. */ + regnum_t this_group_regnum; + + compile_stack.avail--; + begalt = COMPILED_BUFFER_VAR + COMPILE_STACK_TOP.begalt_offset; + fixup_alt_jump + = COMPILE_STACK_TOP.fixup_alt_jump + ? COMPILED_BUFFER_VAR + COMPILE_STACK_TOP.fixup_alt_jump - 1 + : 0; + laststart = COMPILED_BUFFER_VAR + COMPILE_STACK_TOP.laststart_offset; + this_group_regnum = COMPILE_STACK_TOP.regnum; + /* If we've reached MAX_REGNUM groups, then this open + won't actually generate any code, so we'll have to + clear pending_exact explicitly. */ + pending_exact = 0; + + /* We're at the end of the group, so now we know how many + groups were inside this one. */ + if (this_group_regnum <= MAX_REGNUM) + { + UCHAR_T *inner_group_loc + = COMPILED_BUFFER_VAR + COMPILE_STACK_TOP.inner_group_offset; + + *inner_group_loc = regnum - this_group_regnum; + BUF_PUSH_3 (stop_memory, this_group_regnum, + regnum - this_group_regnum); + } + } + break; + + + case '|': /* `\|'. */ + if (syntax & RE_LIMITED_OPS || syntax & RE_NO_BK_VBAR) + goto normal_backslash; + handle_alt: + if (syntax & RE_LIMITED_OPS) + goto normal_char; + + /* Insert before the previous alternative a jump which + jumps to this alternative if the former fails. */ + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + INSERT_JUMP (on_failure_jump, begalt, + b + 2 + 2 * OFFSET_ADDRESS_SIZE); + pending_exact = 0; + b += 1 + OFFSET_ADDRESS_SIZE; + + /* The alternative before this one has a jump after it + which gets executed if it gets matched. Adjust that + jump so it will jump to this alternative's analogous + jump (put in below, which in turn will jump to the next + (if any) alternative's such jump, etc.). The last such + jump jumps to the correct final destination. A picture: + _____ _____ + | | | | + | v | v + a | b | c + + If we are at `b', then fixup_alt_jump right now points to a + three-byte space after `a'. We'll put in the jump, set + fixup_alt_jump to right after `b', and leave behind three + bytes which we'll fill in when we get to after `c'. */ + + if (fixup_alt_jump) + STORE_JUMP (jump_past_alt, fixup_alt_jump, b); + + /* Mark and leave space for a jump after this alternative, + to be filled in later either by next alternative or + when know we're at the end of a series of alternatives. */ + fixup_alt_jump = b; + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + b += 1 + OFFSET_ADDRESS_SIZE; + + laststart = 0; + begalt = b; + break; + + + case '{': + /* If \{ is a literal. */ + if (!(syntax & RE_INTERVALS) + /* If we're at `\{' and it's not the open-interval + operator. */ + || (syntax & RE_NO_BK_BRACES)) + goto normal_backslash; + + handle_interval: + { + /* If got here, then the syntax allows intervals. */ + + /* At least (most) this many matches must be made. */ + int lower_bound = -1, upper_bound = -1; + + /* Place in the uncompiled pattern (i.e., just after + the '{') to go back to if the interval is invalid. */ + const CHAR_T *beg_interval = p; + + if (p == pend) + goto invalid_interval; + + GET_UNSIGNED_NUMBER (lower_bound); + + if (c == ',') + { + GET_UNSIGNED_NUMBER (upper_bound); + if (upper_bound < 0) + upper_bound = RE_DUP_MAX; + } + else + /* Interval such as `{1}' => match exactly once. */ + upper_bound = lower_bound; + + if (! (0 <= lower_bound && lower_bound <= upper_bound)) + goto invalid_interval; + + if (!(syntax & RE_NO_BK_BRACES)) + { + if (c != '\\' || p == pend) + goto invalid_interval; + PATFETCH (c); + } + + if (c != '}') + goto invalid_interval; + + /* If it's invalid to have no preceding re. */ + if (!laststart) + { + if (syntax & RE_CONTEXT_INVALID_OPS + && !(syntax & RE_INVALID_INTERVAL_ORD)) + FREE_STACK_RETURN (REG_BADRPT); + else if (syntax & RE_CONTEXT_INDEP_OPS) + laststart = b; + else + goto unfetch_interval; + } + + /* We just parsed a valid interval. */ + + if (RE_DUP_MAX < upper_bound) + FREE_STACK_RETURN (REG_BADBR); + + /* If the upper bound is zero, don't want to succeed at + all; jump from `laststart' to `b + 3', which will be + the end of the buffer after we insert the jump. */ + /* ifdef WCHAR, 'b + 1 + OFFSET_ADDRESS_SIZE' + instead of 'b + 3'. */ + if (upper_bound == 0) + { + GET_BUFFER_SPACE (1 + OFFSET_ADDRESS_SIZE); + INSERT_JUMP (jump, laststart, b + 1 + + OFFSET_ADDRESS_SIZE); + b += 1 + OFFSET_ADDRESS_SIZE; + } + + /* Otherwise, we have a nontrivial interval. When + we're all done, the pattern will look like: + set_number_at + set_number_at + succeed_n + + jump_n + (The upper bound and `jump_n' are omitted if + `upper_bound' is 1, though.) */ + else + { /* If the upper bound is > 1, we need to insert + more at the end of the loop. */ + unsigned nbytes = 2 + 4 * OFFSET_ADDRESS_SIZE + + (upper_bound > 1) * (2 + 4 * OFFSET_ADDRESS_SIZE); + + GET_BUFFER_SPACE (nbytes); + + /* Initialize lower bound of the `succeed_n', even + though it will be set during matching by its + attendant `set_number_at' (inserted next), + because `re_compile_fastmap' needs to know. + Jump to the `jump_n' we might insert below. */ + INSERT_JUMP2 (succeed_n, laststart, + b + 1 + 2 * OFFSET_ADDRESS_SIZE + + (upper_bound > 1) * (1 + 2 * OFFSET_ADDRESS_SIZE) + , lower_bound); + b += 1 + 2 * OFFSET_ADDRESS_SIZE; + + /* Code to initialize the lower bound. Insert + before the `succeed_n'. The `5' is the last two + bytes of this `set_number_at', plus 3 bytes of + the following `succeed_n'. */ + /* ifdef WCHAR, The '1+2*OFFSET_ADDRESS_SIZE' + is the 'set_number_at', plus '1+OFFSET_ADDRESS_SIZE' + of the following `succeed_n'. */ + PREFIX(insert_op2) (set_number_at, laststart, 1 + + 2 * OFFSET_ADDRESS_SIZE, lower_bound, b); + b += 1 + 2 * OFFSET_ADDRESS_SIZE; + + if (upper_bound > 1) + { /* More than one repetition is allowed, so + append a backward jump to the `succeed_n' + that starts this interval. + + When we've reached this during matching, + we'll have matched the interval once, so + jump back only `upper_bound - 1' times. */ + STORE_JUMP2 (jump_n, b, laststart + + 2 * OFFSET_ADDRESS_SIZE + 1, + upper_bound - 1); + b += 1 + 2 * OFFSET_ADDRESS_SIZE; + + /* The location we want to set is the second + parameter of the `jump_n'; that is `b-2' as + an absolute address. `laststart' will be + the `set_number_at' we're about to insert; + `laststart+3' the number to set, the source + for the relative address. But we are + inserting into the middle of the pattern -- + so everything is getting moved up by 5. + Conclusion: (b - 2) - (laststart + 3) + 5, + i.e., b - laststart. + + We insert this at the beginning of the loop + so that if we fail during matching, we'll + reinitialize the bounds. */ + PREFIX(insert_op2) (set_number_at, laststart, + b - laststart, + upper_bound - 1, b); + b += 1 + 2 * OFFSET_ADDRESS_SIZE; + } + } + pending_exact = 0; + break; + + invalid_interval: + if (!(syntax & RE_INVALID_INTERVAL_ORD)) + FREE_STACK_RETURN (p == pend ? REG_EBRACE : REG_BADBR); + unfetch_interval: + /* Match the characters as literals. */ + p = beg_interval; + c = '{'; + if (syntax & RE_NO_BK_BRACES) + goto normal_char; + else + goto normal_backslash; + } + +#ifdef emacs + /* There is no way to specify the before_dot and after_dot + operators. rms says this is ok. --karl */ + case '=': + BUF_PUSH (at_dot); + break; + + case 's': + laststart = b; + PATFETCH (c); + BUF_PUSH_2 (syntaxspec, syntax_spec_code[c]); + break; + + case 'S': + laststart = b; + PATFETCH (c); + BUF_PUSH_2 (notsyntaxspec, syntax_spec_code[c]); + break; +#endif /* emacs */ + + + case 'w': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + laststart = b; + BUF_PUSH (wordchar); + break; + + + case 'W': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + laststart = b; + BUF_PUSH (notwordchar); + break; + + + case '<': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (wordbeg); + break; + + case '>': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (wordend); + break; + + case 'b': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (wordbound); + break; + + case 'B': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (notwordbound); + break; + + case '`': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (begbuf); + break; + + case '\'': + if (syntax & RE_NO_GNU_OPS) + goto normal_char; + BUF_PUSH (endbuf); + break; + + case '1': case '2': case '3': case '4': case '5': + case '6': case '7': case '8': case '9': + if (syntax & RE_NO_BK_REFS) + goto normal_char; + + c1 = c - '0'; + + if (c1 > regnum) + FREE_STACK_RETURN (REG_ESUBREG); + + /* Can't back reference to a subexpression if inside of it. */ + if (group_in_compile_stack (compile_stack, (regnum_t) c1)) + goto normal_char; + + laststart = b; + BUF_PUSH_2 (duplicate, c1); + break; + + + case '+': + case '?': + if (syntax & RE_BK_PLUS_QM) + goto handle_plus; + else + goto normal_backslash; + + default: + normal_backslash: + /* You might think it would be useful for \ to mean + not to translate; but if we don't translate it + it will never match anything. */ + c = TRANSLATE (c); + goto normal_char; + } + break; + + + default: + /* Expects the character in `c'. */ + normal_char: + /* If no exactn currently being built. */ + if (!pending_exact +#ifdef WCHAR + /* If last exactn handle binary(or character) and + new exactn handle character(or binary). */ + || is_exactn_bin != is_binary[p - 1 - pattern] +#endif /* WCHAR */ + + /* If last exactn not at current position. */ + || pending_exact + *pending_exact + 1 != b + + /* We have only one byte following the exactn for the count. */ + || *pending_exact == (1 << BYTEWIDTH) - 1 + + /* If followed by a repetition operator. */ + || *p == '*' || *p == '^' + || ((syntax & RE_BK_PLUS_QM) + ? *p == '\\' && (p[1] == '+' || p[1] == '?') + : (*p == '+' || *p == '?')) + || ((syntax & RE_INTERVALS) + && ((syntax & RE_NO_BK_BRACES) + ? *p == '{' + : (p[0] == '\\' && p[1] == '{')))) + { + /* Start building a new exactn. */ + + laststart = b; + +#ifdef WCHAR + /* Is this exactn binary data or character? */ + is_exactn_bin = is_binary[p - 1 - pattern]; + if (is_exactn_bin) + BUF_PUSH_2 (exactn_bin, 0); + else + BUF_PUSH_2 (exactn, 0); +#else + BUF_PUSH_2 (exactn, 0); +#endif /* WCHAR */ + pending_exact = b - 1; + } + + BUF_PUSH (c); + (*pending_exact)++; + break; + } /* switch (c) */ + } /* while p != pend */ + + + /* Through the pattern now. */ + + if (fixup_alt_jump) + STORE_JUMP (jump_past_alt, fixup_alt_jump, b); + + if (!COMPILE_STACK_EMPTY) + FREE_STACK_RETURN (REG_EPAREN); + + /* If we don't want backtracking, force success + the first time we reach the end of the compiled pattern. */ + if (syntax & RE_NO_POSIX_BACKTRACKING) + BUF_PUSH (succeed); + +#ifdef WCHAR + free (pattern); + free (mbs_offset); + free (is_binary); +#endif + free (compile_stack.stack); + + /* We have succeeded; set the length of the buffer. */ +#ifdef WCHAR + bufp->used = (uintptr_t) b - (uintptr_t) COMPILED_BUFFER_VAR; +#else + bufp->used = b - bufp->buffer; +#endif + +#ifdef DEBUG + if (debug) + { + DEBUG_PRINT1 ("\nCompiled pattern: \n"); + PREFIX(print_compiled_pattern) (bufp); + } +#endif /* DEBUG */ + +#ifndef MATCH_MAY_ALLOCATE + /* Initialize the failure stack to the largest possible stack. This + isn't necessary unless we're trying to avoid calling alloca in + the search and match routines. */ + { + int num_regs = bufp->re_nsub + 1; + + /* Since DOUBLE_FAIL_STACK refuses to double only if the current size + is strictly greater than re_max_failures, the largest possible stack + is 2 * re_max_failures failure points. */ + if (fail_stack.size < (2 * re_max_failures * MAX_FAILURE_ITEMS)) + { + fail_stack.size = (2 * re_max_failures * MAX_FAILURE_ITEMS); + +# ifdef emacs + if (! fail_stack.stack) + fail_stack.stack + = (PREFIX(fail_stack_elt_t) *) xmalloc (fail_stack.size + * sizeof (PREFIX(fail_stack_elt_t))); + else + fail_stack.stack + = (PREFIX(fail_stack_elt_t) *) xrealloc (fail_stack.stack, + (fail_stack.size + * sizeof (PREFIX(fail_stack_elt_t)))); +# else /* not emacs */ + if (! fail_stack.stack) + fail_stack.stack + = (PREFIX(fail_stack_elt_t) *) malloc (fail_stack.size + * sizeof (PREFIX(fail_stack_elt_t))); + else + fail_stack.stack + = (PREFIX(fail_stack_elt_t) *) realloc (fail_stack.stack, + (fail_stack.size + * sizeof (PREFIX(fail_stack_elt_t)))); +# endif /* not emacs */ + } + + PREFIX(regex_grow_registers) (num_regs); + } +#endif /* not MATCH_MAY_ALLOCATE */ + + return REG_NOERROR; +} /* regex_compile */ + +/* Subroutines for `regex_compile'. */ + +/* Store OP at LOC followed by two-byte integer parameter ARG. */ +/* ifdef WCHAR, integer parameter is 1 wchar_t. */ + +static void +PREFIX(store_op1) (re_opcode_t op, UCHAR_T *loc, int arg) +{ + *loc = (UCHAR_T) op; + STORE_NUMBER (loc + 1, arg); +} + + +/* Like `store_op1', but for two two-byte parameters ARG1 and ARG2. */ +/* ifdef WCHAR, integer parameter is 1 wchar_t. */ + +static void +PREFIX(store_op2) (re_opcode_t op, UCHAR_T *loc, int arg1, int arg2) +{ + *loc = (UCHAR_T) op; + STORE_NUMBER (loc + 1, arg1); + STORE_NUMBER (loc + 1 + OFFSET_ADDRESS_SIZE, arg2); +} + + +/* Copy the bytes from LOC to END to open up three bytes of space at LOC + for OP followed by two-byte integer parameter ARG. */ +/* ifdef WCHAR, integer parameter is 1 wchar_t. */ + +static void +PREFIX(insert_op1) (re_opcode_t op, UCHAR_T *loc, int arg, UCHAR_T *end) +{ + register UCHAR_T *pfrom = end; + register UCHAR_T *pto = end + 1 + OFFSET_ADDRESS_SIZE; + + while (pfrom != loc) + *--pto = *--pfrom; + + PREFIX(store_op1) (op, loc, arg); +} + + +/* Like `insert_op1', but for two two-byte parameters ARG1 and ARG2. */ +/* ifdef WCHAR, integer parameter is 1 wchar_t. */ + +static void +PREFIX(insert_op2) (re_opcode_t op, UCHAR_T *loc, int arg1, + int arg2, UCHAR_T *end) +{ + register UCHAR_T *pfrom = end; + register UCHAR_T *pto = end + 1 + 2 * OFFSET_ADDRESS_SIZE; + + while (pfrom != loc) + *--pto = *--pfrom; + + PREFIX(store_op2) (op, loc, arg1, arg2); +} + + +/* P points to just after a ^ in PATTERN. Return true if that ^ comes + after an alternative or a begin-subexpression. We assume there is at + least one character before the ^. */ + +static boolean +PREFIX(at_begline_loc_p) (const CHAR_T *pattern, const CHAR_T *p, + reg_syntax_t syntax) +{ + const CHAR_T *prev = p - 2; + boolean prev_prev_backslash = prev > pattern && prev[-1] == '\\'; + + return + /* After a subexpression? */ + (*prev == '(' && (syntax & RE_NO_BK_PARENS || prev_prev_backslash)) + /* After an alternative? */ + || (*prev == '|' && (syntax & RE_NO_BK_VBAR || prev_prev_backslash)); +} + + +/* The dual of at_begline_loc_p. This one is for $. We assume there is + at least one character after the $, i.e., `P < PEND'. */ + +static boolean +PREFIX(at_endline_loc_p) (const CHAR_T *p, const CHAR_T *pend, + reg_syntax_t syntax) +{ + const CHAR_T *next = p; + boolean next_backslash = *next == '\\'; + const CHAR_T *next_next = p + 1 < pend ? p + 1 : 0; + + return + /* Before a subexpression? */ + (syntax & RE_NO_BK_PARENS ? *next == ')' + : next_backslash && next_next && *next_next == ')') + /* Before an alternative? */ + || (syntax & RE_NO_BK_VBAR ? *next == '|' + : next_backslash && next_next && *next_next == '|'); +} + +#else /* not INSIDE_RECURSION */ + +/* Returns true if REGNUM is in one of COMPILE_STACK's elements and + false if it's not. */ + +static boolean +group_in_compile_stack (compile_stack_type compile_stack, regnum_t regnum) +{ + int this_element; + + for (this_element = compile_stack.avail - 1; + this_element >= 0; + this_element--) + if (compile_stack.stack[this_element].regnum == regnum) + return true; + + return false; +} +#endif /* not INSIDE_RECURSION */ + +#ifdef INSIDE_RECURSION + +#ifdef WCHAR +/* This insert space, which size is "num", into the pattern at "loc". + "end" must point the end of the allocated buffer. */ +static void +insert_space (int num, CHAR_T *loc, CHAR_T *end) +{ + register CHAR_T *pto = end; + register CHAR_T *pfrom = end - num; + + while (pfrom >= loc) + *pto-- = *pfrom--; +} +#endif /* WCHAR */ + +#ifdef WCHAR +static reg_errcode_t +wcs_compile_range (CHAR_T range_start_char, const CHAR_T **p_ptr, + const CHAR_T *pend, RE_TRANSLATE_TYPE translate, + reg_syntax_t syntax, CHAR_T *b, CHAR_T *char_set) +{ + const CHAR_T *p = *p_ptr; + CHAR_T range_start, range_end; + reg_errcode_t ret; +# ifdef _LIBC + uint32_t nrules; + uint32_t start_val, end_val; +# endif + if (p == pend) + return REG_ERANGE; + +# ifdef _LIBC + nrules = _NL_CURRENT_WORD (LC_COLLATE, _NL_COLLATE_NRULES); + if (nrules != 0) + { + const char *collseq = (const char *) _NL_CURRENT(LC_COLLATE, + _NL_COLLATE_COLLSEQWC); + const unsigned char *extra = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_SYMB_EXTRAMB); + + if (range_start_char < -1) + { + /* range_start is a collating symbol. */ + int32_t *wextra; + /* Retreive the index and get collation sequence value. */ + wextra = (int32_t*)(extra + char_set[-range_start_char]); + start_val = wextra[1 + *wextra]; + } + else + start_val = collseq_table_lookup(collseq, TRANSLATE(range_start_char)); + + end_val = collseq_table_lookup (collseq, TRANSLATE (p[0])); + + /* Report an error if the range is empty and the syntax prohibits + this. */ + ret = ((syntax & RE_NO_EMPTY_RANGES) + && (start_val > end_val))? REG_ERANGE : REG_NOERROR; + + /* Insert space to the end of the char_ranges. */ + insert_space(2, b - char_set[5] - 2, b - 1); + *(b - char_set[5] - 2) = (wchar_t)start_val; + *(b - char_set[5] - 1) = (wchar_t)end_val; + char_set[4]++; /* ranges_index */ + } + else +# endif + { + range_start = (range_start_char >= 0)? TRANSLATE (range_start_char): + range_start_char; + range_end = TRANSLATE (p[0]); + /* Report an error if the range is empty and the syntax prohibits + this. */ + ret = ((syntax & RE_NO_EMPTY_RANGES) + && (range_start > range_end))? REG_ERANGE : REG_NOERROR; + + /* Insert space to the end of the char_ranges. */ + insert_space(2, b - char_set[5] - 2, b - 1); + *(b - char_set[5] - 2) = range_start; + *(b - char_set[5] - 1) = range_end; + char_set[4]++; /* ranges_index */ + } + /* Have to increment the pointer into the pattern string, so the + caller isn't still at the ending character. */ + (*p_ptr)++; + + return ret; +} +#else /* BYTE */ +/* Read the ending character of a range (in a bracket expression) from the + uncompiled pattern *P_PTR (which ends at PEND). We assume the + starting character is in `P[-2]'. (`P[-1]' is the character `-'.) + Then we set the translation of all bits between the starting and + ending characters (inclusive) in the compiled pattern B. + + Return an error code. + + We use these short variable names so we can use the same macros as + `regex_compile' itself. */ + +static reg_errcode_t +byte_compile_range (unsigned int range_start_char, const char **p_ptr, + const char *pend, RE_TRANSLATE_TYPE translate, + reg_syntax_t syntax, unsigned char *b) +{ + unsigned this_char; + const char *p = *p_ptr; + reg_errcode_t ret; +# if _LIBC + const unsigned char *collseq; + unsigned int start_colseq; + unsigned int end_colseq; +# else + unsigned end_char; +# endif + + if (p == pend) + return REG_ERANGE; + + /* Have to increment the pointer into the pattern string, so the + caller isn't still at the ending character. */ + (*p_ptr)++; + + /* Report an error if the range is empty and the syntax prohibits this. */ + ret = syntax & RE_NO_EMPTY_RANGES ? REG_ERANGE : REG_NOERROR; + +# if _LIBC + collseq = (const unsigned char *) _NL_CURRENT (LC_COLLATE, + _NL_COLLATE_COLLSEQMB); + + start_colseq = collseq[(unsigned char) TRANSLATE (range_start_char)]; + end_colseq = collseq[(unsigned char) TRANSLATE (p[0])]; + for (this_char = 0; this_char <= (unsigned char) -1; ++this_char) + { + unsigned int this_colseq = collseq[(unsigned char) TRANSLATE (this_char)]; + + if (start_colseq <= this_colseq && this_colseq <= end_colseq) + { + SET_LIST_BIT (TRANSLATE (this_char)); + ret = REG_NOERROR; + } + } +# else + /* Here we see why `this_char' has to be larger than an `unsigned + char' -- we would otherwise go into an infinite loop, since all + characters <= 0xff. */ + range_start_char = TRANSLATE (range_start_char); + /* TRANSLATE(p[0]) is casted to char (not unsigned char) in TRANSLATE, + and some compilers cast it to int implicitly, so following for_loop + may fall to (almost) infinite loop. + e.g. If translate[p[0]] = 0xff, end_char may equals to 0xffffffff. + To avoid this, we cast p[0] to unsigned int and truncate it. */ + end_char = ((unsigned)TRANSLATE(p[0]) & ((1 << BYTEWIDTH) - 1)); + + for (this_char = range_start_char; this_char <= end_char; ++this_char) + { + SET_LIST_BIT (TRANSLATE (this_char)); + ret = REG_NOERROR; + } +# endif + + return ret; +} +#endif /* WCHAR */ + +/* re_compile_fastmap computes a ``fastmap'' for the compiled pattern in + BUFP. A fastmap records which of the (1 << BYTEWIDTH) possible + characters can start a string that matches the pattern. This fastmap + is used by re_search to skip quickly over impossible starting points. + + The caller must supply the address of a (1 << BYTEWIDTH)-byte data + area as BUFP->fastmap. + + We set the `fastmap', `fastmap_accurate', and `can_be_null' fields in + the pattern buffer. + + Returns 0 if we succeed, -2 if an internal error. */ + +#ifdef WCHAR +/* local function for re_compile_fastmap. + truncate wchar_t character to char. */ +static unsigned char truncate_wchar (CHAR_T c); + +static unsigned char +truncate_wchar (CHAR_T c) +{ + unsigned char buf[MB_CUR_MAX]; + mbstate_t state; + int retval; + memset (&state, '\0', sizeof (state)); +# ifdef _LIBC + retval = __wcrtomb (buf, c, &state); +# else + retval = wcrtomb (buf, c, &state); +# endif + return retval > 0 ? buf[0] : (unsigned char) c; +} +#endif /* WCHAR */ + +static int +PREFIX(re_compile_fastmap) (struct re_pattern_buffer *bufp) +{ + int j, k; +#ifdef MATCH_MAY_ALLOCATE + PREFIX(fail_stack_type) fail_stack; +#endif +#ifndef REGEX_MALLOC + char *destination; +#endif + + register char *fastmap = bufp->fastmap; + +#ifdef WCHAR + /* We need to cast pattern to (wchar_t*), because we casted this compiled + pattern to (char*) in regex_compile. */ + UCHAR_T *pattern = (UCHAR_T*)bufp->buffer; + register UCHAR_T *pend = (UCHAR_T*) (bufp->buffer + bufp->used); +#else /* BYTE */ + UCHAR_T *pattern = bufp->buffer; + register UCHAR_T *pend = pattern + bufp->used; +#endif /* WCHAR */ + UCHAR_T *p = pattern; + +#ifdef REL_ALLOC + /* This holds the pointer to the failure stack, when + it is allocated relocatably. */ + fail_stack_elt_t *failure_stack_ptr; +#endif + + /* Assume that each path through the pattern can be null until + proven otherwise. We set this false at the bottom of switch + statement, to which we get only if a particular path doesn't + match the empty string. */ + boolean path_can_be_null = true; + + /* We aren't doing a `succeed_n' to begin with. */ + boolean succeed_n_p = false; + + assert (fastmap != NULL && p != NULL); + + INIT_FAIL_STACK (); + bzero (fastmap, 1 << BYTEWIDTH); /* Assume nothing's valid. */ + bufp->fastmap_accurate = 1; /* It will be when we're done. */ + bufp->can_be_null = 0; + + while (1) + { + if (p == pend || *p == (UCHAR_T) succeed) + { + /* We have reached the (effective) end of pattern. */ + if (!FAIL_STACK_EMPTY ()) + { + bufp->can_be_null |= path_can_be_null; + + /* Reset for next path. */ + path_can_be_null = true; + + p = fail_stack.stack[--fail_stack.avail].pointer; + + continue; + } + else + break; + } + + /* We should never be about to go beyond the end of the pattern. */ + assert (p < pend); + + switch (SWITCH_ENUM_CAST ((re_opcode_t) *p++)) + { + + /* I guess the idea here is to simply not bother with a fastmap + if a backreference is used, since it's too hard to figure out + the fastmap for the corresponding group. Setting + `can_be_null' stops `re_search_2' from using the fastmap, so + that is all we do. */ + case duplicate: + bufp->can_be_null = 1; + goto done; + + + /* Following are the cases which match a character. These end + with `break'. */ + +#ifdef WCHAR + case exactn: + fastmap[truncate_wchar(p[1])] = 1; + break; +#else /* BYTE */ + case exactn: + fastmap[p[1]] = 1; + break; +#endif /* WCHAR */ +#ifdef MBS_SUPPORT + case exactn_bin: + fastmap[p[1]] = 1; + break; +#endif + +#ifdef WCHAR + /* It is hard to distinguish fastmap from (multi byte) characters + which depends on current locale. */ + case charset: + case charset_not: + case wordchar: + case notwordchar: + bufp->can_be_null = 1; + goto done; +#else /* BYTE */ + case charset: + for (j = *p++ * BYTEWIDTH - 1; j >= 0; j--) + if (p[j / BYTEWIDTH] & (1 << (j % BYTEWIDTH))) + fastmap[j] = 1; + break; + + + case charset_not: + /* Chars beyond end of map must be allowed. */ + for (j = *p * BYTEWIDTH; j < (1 << BYTEWIDTH); j++) + fastmap[j] = 1; + + for (j = *p++ * BYTEWIDTH - 1; j >= 0; j--) + if (!(p[j / BYTEWIDTH] & (1 << (j % BYTEWIDTH)))) + fastmap[j] = 1; + break; + + + case wordchar: + for (j = 0; j < (1 << BYTEWIDTH); j++) + if (SYNTAX (j) == Sword) + fastmap[j] = 1; + break; + + + case notwordchar: + for (j = 0; j < (1 << BYTEWIDTH); j++) + if (SYNTAX (j) != Sword) + fastmap[j] = 1; + break; +#endif /* WCHAR */ + + case anychar: + { + int fastmap_newline = fastmap['\n']; + + /* `.' matches anything ... */ + for (j = 0; j < (1 << BYTEWIDTH); j++) + fastmap[j] = 1; + + /* ... except perhaps newline. */ + if (!(bufp->syntax & RE_DOT_NEWLINE)) + fastmap['\n'] = fastmap_newline; + + /* Return if we have already set `can_be_null'; if we have, + then the fastmap is irrelevant. Something's wrong here. */ + else if (bufp->can_be_null) + goto done; + + /* Otherwise, have to check alternative paths. */ + break; + } + +#ifdef emacs + case syntaxspec: + k = *p++; + for (j = 0; j < (1 << BYTEWIDTH); j++) + if (SYNTAX (j) == (enum syntaxcode) k) + fastmap[j] = 1; + break; + + + case notsyntaxspec: + k = *p++; + for (j = 0; j < (1 << BYTEWIDTH); j++) + if (SYNTAX (j) != (enum syntaxcode) k) + fastmap[j] = 1; + break; + + + /* All cases after this match the empty string. These end with + `continue'. */ + + + case before_dot: + case at_dot: + case after_dot: + continue; +#endif /* emacs */ + + + case no_op: + case begline: + case endline: + case begbuf: + case endbuf: + case wordbound: + case notwordbound: + case wordbeg: + case wordend: + case push_dummy_failure: + continue; + + + case jump_n: + case pop_failure_jump: + case maybe_pop_jump: + case jump: + case jump_past_alt: + case dummy_failure_jump: + EXTRACT_NUMBER_AND_INCR (j, p); + p += j; + if (j > 0) + continue; + + /* Jump backward implies we just went through the body of a + loop and matched nothing. Opcode jumped to should be + `on_failure_jump' or `succeed_n'. Just treat it like an + ordinary jump. For a * loop, it has pushed its failure + point already; if so, discard that as redundant. */ + if ((re_opcode_t) *p != on_failure_jump + && (re_opcode_t) *p != succeed_n) + continue; + + p++; + EXTRACT_NUMBER_AND_INCR (j, p); + p += j; + + /* If what's on the stack is where we are now, pop it. */ + if (!FAIL_STACK_EMPTY () + && fail_stack.stack[fail_stack.avail - 1].pointer == p) + fail_stack.avail--; + + continue; + + + case on_failure_jump: + case on_failure_keep_string_jump: + handle_on_failure_jump: + EXTRACT_NUMBER_AND_INCR (j, p); + + /* For some patterns, e.g., `(a?)?', `p+j' here points to the + end of the pattern. We don't want to push such a point, + since when we restore it above, entering the switch will + increment `p' past the end of the pattern. We don't need + to push such a point since we obviously won't find any more + fastmap entries beyond `pend'. Such a pattern can match + the null string, though. */ + if (p + j < pend) + { + if (!PUSH_PATTERN_OP (p + j, fail_stack)) + { + RESET_FAIL_STACK (); + return -2; + } + } + else + bufp->can_be_null = 1; + + if (succeed_n_p) + { + EXTRACT_NUMBER_AND_INCR (k, p); /* Skip the n. */ + succeed_n_p = false; + } + + continue; + + + case succeed_n: + /* Get to the number of times to succeed. */ + p += OFFSET_ADDRESS_SIZE; + + /* Increment p past the n for when k != 0. */ + EXTRACT_NUMBER_AND_INCR (k, p); + if (k == 0) + { + p -= 2 * OFFSET_ADDRESS_SIZE; + succeed_n_p = true; /* Spaghetti code alert. */ + goto handle_on_failure_jump; + } + continue; + + + case set_number_at: + p += 2 * OFFSET_ADDRESS_SIZE; + continue; + + + case start_memory: + case stop_memory: + p += 2; + continue; + + + default: + abort (); /* We have listed all the cases. */ + } /* switch *p++ */ + + /* Getting here means we have found the possible starting + characters for one path of the pattern -- and that the empty + string does not match. We need not follow this path further. + Instead, look at the next alternative (remembered on the + stack), or quit if no more. The test at the top of the loop + does these things. */ + path_can_be_null = false; + p = pend; + } /* while p */ + + /* Set `can_be_null' for the last path (also the first path, if the + pattern is empty). */ + bufp->can_be_null |= path_can_be_null; + + done: + RESET_FAIL_STACK (); + return 0; +} + +#else /* not INSIDE_RECURSION */ + +int +re_compile_fastmap (struct re_pattern_buffer *bufp) +{ +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + return wcs_re_compile_fastmap(bufp); + else +# endif + return byte_re_compile_fastmap(bufp); +} /* re_compile_fastmap */ +#ifdef _LIBC +weak_alias (__re_compile_fastmap, re_compile_fastmap) +#endif + + +/* Set REGS to hold NUM_REGS registers, storing them in STARTS and + ENDS. Subsequent matches using PATTERN_BUFFER and REGS will use + this memory for recording register information. STARTS and ENDS + must be allocated using the malloc library routine, and must each + be at least NUM_REGS * sizeof (regoff_t) bytes long. + + If NUM_REGS == 0, then subsequent matches should allocate their own + register data. + + Unless this function is called, the first search or match using + PATTERN_BUFFER will allocate its own register data, without + freeing the old data. */ + +void +re_set_registers (struct re_pattern_buffer *bufp, + struct re_registers *regs, unsigned num_regs, + regoff_t *starts, regoff_t *ends) +{ + if (num_regs) + { + bufp->regs_allocated = REGS_REALLOCATE; + regs->num_regs = num_regs; + regs->start = starts; + regs->end = ends; + } + else + { + bufp->regs_allocated = REGS_UNALLOCATED; + regs->num_regs = 0; + regs->start = regs->end = (regoff_t *) 0; + } +} +#ifdef _LIBC +weak_alias (__re_set_registers, re_set_registers) +#endif + +/* Searching routines. */ + +/* Like re_search_2, below, but only one string is specified, and + doesn't let you say where to stop matching. */ + +int +re_search (struct re_pattern_buffer *bufp, const char *string, int size, + int startpos, int range, struct re_registers *regs) +{ + return re_search_2 (bufp, NULL, 0, string, size, startpos, range, + regs, size); +} +#ifdef _LIBC +weak_alias (__re_search, re_search) +#endif + + +/* Using the compiled pattern in BUFP->buffer, first tries to match the + virtual concatenation of STRING1 and STRING2, starting first at index + STARTPOS, then at STARTPOS + 1, and so on. + + STRING1 and STRING2 have length SIZE1 and SIZE2, respectively. + + RANGE is how far to scan while trying to match. RANGE = 0 means try + only at STARTPOS; in general, the last start tried is STARTPOS + + RANGE. + + In REGS, return the indices of the virtual concatenation of STRING1 + and STRING2 that matched the entire BUFP->buffer and its contained + subexpressions. + + Do not consider matching one past the index STOP in the virtual + concatenation of STRING1 and STRING2. + + We return either the position in the strings at which the match was + found, -1 if no match, or -2 if error (such as failure + stack overflow). */ + +int +re_search_2 (struct re_pattern_buffer *bufp, const char *string1, int size1, + const char *string2, int size2, int startpos, int range, + struct re_registers *regs, int stop) +{ +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + return wcs_re_search_2 (bufp, string1, size1, string2, size2, startpos, + range, regs, stop); + else +# endif + return byte_re_search_2 (bufp, string1, size1, string2, size2, startpos, + range, regs, stop); +} /* re_search_2 */ +#ifdef _LIBC +weak_alias (__re_search_2, re_search_2) +#endif + +#endif /* not INSIDE_RECURSION */ + +#ifdef INSIDE_RECURSION + +#ifdef MATCH_MAY_ALLOCATE +# define FREE_VAR(var) if (var) REGEX_FREE (var); var = NULL +#else +# define FREE_VAR(var) if (var) free (var); var = NULL +#endif + +#ifdef WCHAR +# define MAX_ALLOCA_SIZE 2000 + +# define FREE_WCS_BUFFERS() \ + do { \ + if (size1 > MAX_ALLOCA_SIZE) \ + { \ + free (wcs_string1); \ + free (mbs_offset1); \ + } \ + else \ + { \ + FREE_VAR (wcs_string1); \ + FREE_VAR (mbs_offset1); \ + } \ + if (size2 > MAX_ALLOCA_SIZE) \ + { \ + free (wcs_string2); \ + free (mbs_offset2); \ + } \ + else \ + { \ + FREE_VAR (wcs_string2); \ + FREE_VAR (mbs_offset2); \ + } \ + } while (0) + +#endif + + +static int +PREFIX(re_search_2) (struct re_pattern_buffer *bufp, const char *string1, + int size1, const char *string2, int size2, + int startpos, int range, + struct re_registers *regs, int stop) +{ + int val; + register char *fastmap = bufp->fastmap; + register RE_TRANSLATE_TYPE translate = bufp->translate; + int total_size = size1 + size2; + int endpos = startpos + range; +#ifdef WCHAR + /* We need wchar_t* buffers correspond to cstring1, cstring2. */ + wchar_t *wcs_string1 = NULL, *wcs_string2 = NULL; + /* We need the size of wchar_t buffers correspond to csize1, csize2. */ + int wcs_size1 = 0, wcs_size2 = 0; + /* offset buffer for optimizatoin. See convert_mbs_to_wc. */ + int *mbs_offset1 = NULL, *mbs_offset2 = NULL; + /* They hold whether each wchar_t is binary data or not. */ + char *is_binary = NULL; +#endif /* WCHAR */ + + /* Check for out-of-range STARTPOS. */ + if (startpos < 0 || startpos > total_size) + return -1; + + /* Fix up RANGE if it might eventually take us outside + the virtual concatenation of STRING1 and STRING2. + Make sure we won't move STARTPOS below 0 or above TOTAL_SIZE. */ + if (endpos < 0) + range = 0 - startpos; + else if (endpos > total_size) + range = total_size - startpos; + + /* If the search isn't to be a backwards one, don't waste time in a + search for a pattern that must be anchored. */ + if (bufp->used > 0 && range > 0 + && ((re_opcode_t) bufp->buffer[0] == begbuf + /* `begline' is like `begbuf' if it cannot match at newlines. */ + || ((re_opcode_t) bufp->buffer[0] == begline + && !bufp->newline_anchor))) + { + if (startpos > 0) + return -1; + else + range = 1; + } + +#ifdef emacs + /* In a forward search for something that starts with \=. + don't keep searching past point. */ + if (bufp->used > 0 && (re_opcode_t) bufp->buffer[0] == at_dot && range > 0) + { + range = PT - startpos; + if (range <= 0) + return -1; + } +#endif /* emacs */ + + /* Update the fastmap now if not correct already. */ + if (fastmap && !bufp->fastmap_accurate) + if (re_compile_fastmap (bufp) == -2) + return -2; + +#ifdef WCHAR + /* Allocate wchar_t array for wcs_string1 and wcs_string2 and + fill them with converted string. */ + if (size1 != 0) + { + if (size1 > MAX_ALLOCA_SIZE) + { + wcs_string1 = TALLOC (size1 + 1, CHAR_T); + mbs_offset1 = TALLOC (size1 + 1, int); + is_binary = TALLOC (size1 + 1, char); + } + else + { + wcs_string1 = REGEX_TALLOC (size1 + 1, CHAR_T); + mbs_offset1 = REGEX_TALLOC (size1 + 1, int); + is_binary = REGEX_TALLOC (size1 + 1, char); + } + if (!wcs_string1 || !mbs_offset1 || !is_binary) + { + if (size1 > MAX_ALLOCA_SIZE) + { + free (wcs_string1); + free (mbs_offset1); + free (is_binary); + } + else + { + FREE_VAR (wcs_string1); + FREE_VAR (mbs_offset1); + FREE_VAR (is_binary); + } + return -2; + } + wcs_size1 = convert_mbs_to_wcs(wcs_string1, string1, size1, + mbs_offset1, is_binary); + wcs_string1[wcs_size1] = L'\0'; /* for a sentinel */ + if (size1 > MAX_ALLOCA_SIZE) + free (is_binary); + else + FREE_VAR (is_binary); + } + if (size2 != 0) + { + if (size2 > MAX_ALLOCA_SIZE) + { + wcs_string2 = TALLOC (size2 + 1, CHAR_T); + mbs_offset2 = TALLOC (size2 + 1, int); + is_binary = TALLOC (size2 + 1, char); + } + else + { + wcs_string2 = REGEX_TALLOC (size2 + 1, CHAR_T); + mbs_offset2 = REGEX_TALLOC (size2 + 1, int); + is_binary = REGEX_TALLOC (size2 + 1, char); + } + if (!wcs_string2 || !mbs_offset2 || !is_binary) + { + FREE_WCS_BUFFERS (); + if (size2 > MAX_ALLOCA_SIZE) + free (is_binary); + else + FREE_VAR (is_binary); + return -2; + } + wcs_size2 = convert_mbs_to_wcs(wcs_string2, string2, size2, + mbs_offset2, is_binary); + wcs_string2[wcs_size2] = L'\0'; /* for a sentinel */ + if (size2 > MAX_ALLOCA_SIZE) + free (is_binary); + else + FREE_VAR (is_binary); + } +#endif /* WCHAR */ + + + /* Loop through the string, looking for a place to start matching. */ + for (;;) + { + /* If a fastmap is supplied, skip quickly over characters that + cannot be the start of a match. If the pattern can match the + null string, however, we don't need to skip characters; we want + the first null string. */ + if (fastmap && startpos < total_size && !bufp->can_be_null) + { + if (range > 0) /* Searching forwards. */ + { + register const char *d; + register int lim = 0; + int irange = range; + + if (startpos < size1 && startpos + range >= size1) + lim = range - (size1 - startpos); + + d = (startpos >= size1 ? string2 - size1 : string1) + startpos; + + /* Written out as an if-else to avoid testing `translate' + inside the loop. */ + if (translate) + while (range > lim + && !fastmap[(unsigned char) + translate[(unsigned char) *d++]]) + range--; + else + while (range > lim && !fastmap[(unsigned char) *d++]) + range--; + + startpos += irange - range; + } + else /* Searching backwards. */ + { + register CHAR_T c = (size1 == 0 || startpos >= size1 + ? string2[startpos - size1] + : string1[startpos]); + + if (!fastmap[(unsigned char) TRANSLATE (c)]) + goto advance; + } + } + + /* If can't match the null string, and that's all we have left, fail. */ + if (range >= 0 && startpos == total_size && fastmap + && !bufp->can_be_null) + { +#ifdef WCHAR + FREE_WCS_BUFFERS (); +#endif + return -1; + } + +#ifdef WCHAR + val = wcs_re_match_2_internal (bufp, string1, size1, string2, + size2, startpos, regs, stop, + wcs_string1, wcs_size1, + wcs_string2, wcs_size2, + mbs_offset1, mbs_offset2); +#else /* BYTE */ + val = byte_re_match_2_internal (bufp, string1, size1, string2, + size2, startpos, regs, stop); +#endif /* BYTE */ + +#ifndef REGEX_MALLOC +# ifdef C_ALLOCA + alloca (0); +# endif +#endif + + if (val >= 0) + { +#ifdef WCHAR + FREE_WCS_BUFFERS (); +#endif + return startpos; + } + + if (val == -2) + { +#ifdef WCHAR + FREE_WCS_BUFFERS (); +#endif + return -2; + } + + advance: + if (!range) + break; + else if (range > 0) + { + range--; + startpos++; + } + else + { + range++; + startpos--; + } + } +#ifdef WCHAR + FREE_WCS_BUFFERS (); +#endif + return -1; +} + +#ifdef WCHAR +/* This converts PTR, a pointer into one of the search wchar_t strings + `string1' and `string2' into an multibyte string offset from the + beginning of that string. We use mbs_offset to optimize. + See convert_mbs_to_wcs. */ +# define POINTER_TO_OFFSET(ptr) \ + (FIRST_STRING_P (ptr) \ + ? ((regoff_t)(mbs_offset1 != NULL? mbs_offset1[(ptr)-string1] : 0)) \ + : ((regoff_t)((mbs_offset2 != NULL? mbs_offset2[(ptr)-string2] : 0) \ + + csize1))) +#else /* BYTE */ +/* This converts PTR, a pointer into one of the search strings `string1' + and `string2' into an offset from the beginning of that string. */ +# define POINTER_TO_OFFSET(ptr) \ + (FIRST_STRING_P (ptr) \ + ? ((regoff_t) ((ptr) - string1)) \ + : ((regoff_t) ((ptr) - string2 + size1))) +#endif /* WCHAR */ + +/* Macros for dealing with the split strings in re_match_2. */ + +#define MATCHING_IN_FIRST_STRING (dend == end_match_1) + +/* Call before fetching a character with *d. This switches over to + string2 if necessary. */ +#define PREFETCH() \ + while (d == dend) \ + { \ + /* End of string2 => fail. */ \ + if (dend == end_match_2) \ + goto fail; \ + /* End of string1 => advance to string2. */ \ + d = string2; \ + dend = end_match_2; \ + } + +/* Test if at very beginning or at very end of the virtual concatenation + of `string1' and `string2'. If only one string, it's `string2'. */ +#define AT_STRINGS_BEG(d) ((d) == (size1 ? string1 : string2) || !size2) +#define AT_STRINGS_END(d) ((d) == end2) + + +/* Test if D points to a character which is word-constituent. We have + two special cases to check for: if past the end of string1, look at + the first character in string2; and if before the beginning of + string2, look at the last character in string1. */ +#ifdef WCHAR +/* Use internationalized API instead of SYNTAX. */ +# define WORDCHAR_P(d) \ + (iswalnum ((wint_t)((d) == end1 ? *string2 \ + : (d) == string2 - 1 ? *(end1 - 1) : *(d))) != 0 \ + || ((d) == end1 ? *string2 \ + : (d) == string2 - 1 ? *(end1 - 1) : *(d)) == L'_') +#else /* BYTE */ +# define WORDCHAR_P(d) \ + (SYNTAX ((d) == end1 ? *string2 \ + : (d) == string2 - 1 ? *(end1 - 1) : *(d)) \ + == Sword) +#endif /* WCHAR */ + +/* Disabled due to a compiler bug -- see comment at case wordbound */ +#if 0 +/* Test if the character before D and the one at D differ with respect + to being word-constituent. */ +#define AT_WORD_BOUNDARY(d) \ + (AT_STRINGS_BEG (d) || AT_STRINGS_END (d) \ + || WORDCHAR_P (d - 1) != WORDCHAR_P (d)) +#endif + +/* Free everything we malloc. */ +#ifdef MATCH_MAY_ALLOCATE +# ifdef WCHAR +# define FREE_VARIABLES() \ + do { \ + REGEX_FREE_STACK (fail_stack.stack); \ + FREE_VAR (regstart); \ + FREE_VAR (regend); \ + FREE_VAR (old_regstart); \ + FREE_VAR (old_regend); \ + FREE_VAR (best_regstart); \ + FREE_VAR (best_regend); \ + FREE_VAR (reg_info); \ + FREE_VAR (reg_dummy); \ + FREE_VAR (reg_info_dummy); \ + if (!cant_free_wcs_buf) \ + { \ + FREE_VAR (string1); \ + FREE_VAR (string2); \ + FREE_VAR (mbs_offset1); \ + FREE_VAR (mbs_offset2); \ + } \ + } while (0) +# else /* BYTE */ +# define FREE_VARIABLES() \ + do { \ + REGEX_FREE_STACK (fail_stack.stack); \ + FREE_VAR (regstart); \ + FREE_VAR (regend); \ + FREE_VAR (old_regstart); \ + FREE_VAR (old_regend); \ + FREE_VAR (best_regstart); \ + FREE_VAR (best_regend); \ + FREE_VAR (reg_info); \ + FREE_VAR (reg_dummy); \ + FREE_VAR (reg_info_dummy); \ + } while (0) +# endif /* WCHAR */ +#else +# ifdef WCHAR +# define FREE_VARIABLES() \ + do { \ + if (!cant_free_wcs_buf) \ + { \ + FREE_VAR (string1); \ + FREE_VAR (string2); \ + FREE_VAR (mbs_offset1); \ + FREE_VAR (mbs_offset2); \ + } \ + } while (0) +# else /* BYTE */ +# define FREE_VARIABLES() ((void)0) /* Do nothing! But inhibit gcc warning. */ +# endif /* WCHAR */ +#endif /* not MATCH_MAY_ALLOCATE */ + +/* These values must meet several constraints. They must not be valid + register values; since we have a limit of 255 registers (because + we use only one byte in the pattern for the register number), we can + use numbers larger than 255. They must differ by 1, because of + NUM_FAILURE_ITEMS above. And the value for the lowest register must + be larger than the value for the highest register, so we do not try + to actually save any registers when none are active. */ +#define NO_HIGHEST_ACTIVE_REG (1 << BYTEWIDTH) +#define NO_LOWEST_ACTIVE_REG (NO_HIGHEST_ACTIVE_REG + 1) + +#else /* not INSIDE_RECURSION */ +/* Matching routines. */ + +#ifndef emacs /* Emacs never uses this. */ +/* re_match is like re_match_2 except it takes only a single string. */ + +int +re_match (struct re_pattern_buffer *bufp, const char *string, + int size, int pos, struct re_registers *regs) +{ + int result; +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + result = wcs_re_match_2_internal (bufp, NULL, 0, string, size, + pos, regs, size, + NULL, 0, NULL, 0, NULL, NULL); + else +# endif + result = byte_re_match_2_internal (bufp, NULL, 0, string, size, + pos, regs, size); +# ifndef REGEX_MALLOC +# ifdef C_ALLOCA + alloca (0); +# endif +# endif + return result; +} +# ifdef _LIBC +weak_alias (__re_match, re_match) +# endif +#endif /* not emacs */ + +#endif /* not INSIDE_RECURSION */ + +#ifdef INSIDE_RECURSION +static boolean PREFIX(group_match_null_string_p) (UCHAR_T **p, + UCHAR_T *end, + PREFIX(register_info_type) *reg_info); +static boolean PREFIX(alt_match_null_string_p) (UCHAR_T *p, + UCHAR_T *end, + PREFIX(register_info_type) *reg_info); +static boolean PREFIX(common_op_match_null_string_p) (UCHAR_T **p, + UCHAR_T *end, + PREFIX(register_info_type) *reg_info); +static int PREFIX(bcmp_translate) (const CHAR_T *s1, const CHAR_T *s2, + int len, char *translate); +#else /* not INSIDE_RECURSION */ + +/* re_match_2 matches the compiled pattern in BUFP against the + the (virtual) concatenation of STRING1 and STRING2 (of length SIZE1 + and SIZE2, respectively). We start matching at POS, and stop + matching at STOP. + + If REGS is non-null and the `no_sub' field of BUFP is nonzero, we + store offsets for the substring each group matched in REGS. See the + documentation for exactly how many groups we fill. + + We return -1 if no match, -2 if an internal error (such as the + failure stack overflowing). Otherwise, we return the length of the + matched substring. */ + +int +re_match_2 (struct re_pattern_buffer *bufp, const char *string1, int size1, + const char *string2, int size2, int pos, + struct re_registers *regs, int stop) +{ + int result; +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + result = wcs_re_match_2_internal (bufp, string1, size1, string2, size2, + pos, regs, stop, + NULL, 0, NULL, 0, NULL, NULL); + else +# endif + result = byte_re_match_2_internal (bufp, string1, size1, string2, size2, + pos, regs, stop); + +#ifndef REGEX_MALLOC +# ifdef C_ALLOCA + alloca (0); +# endif +#endif + return result; +} +#ifdef _LIBC +weak_alias (__re_match_2, re_match_2) +#endif + +#endif /* not INSIDE_RECURSION */ + +#ifdef INSIDE_RECURSION + +#ifdef WCHAR +static int count_mbs_length (int *, int); + +/* This check the substring (from 0, to length) of the multibyte string, + to which offset_buffer correspond. And count how many wchar_t_characters + the substring occupy. We use offset_buffer to optimization. + See convert_mbs_to_wcs. */ + +static int +count_mbs_length(int *offset_buffer, int length) +{ + int upper, lower; + + /* Check whether the size is valid. */ + if (length < 0) + return -1; + + if (offset_buffer == NULL) + return 0; + + /* If there are no multibyte character, offset_buffer[i] == i. + Optmize for this case. */ + if (offset_buffer[length] == length) + return length; + + /* Set up upper with length. (because for all i, offset_buffer[i] >= i) */ + upper = length; + lower = 0; + + while (true) + { + int middle = (lower + upper) / 2; + if (middle == lower || middle == upper) + break; + if (offset_buffer[middle] > length) + upper = middle; + else if (offset_buffer[middle] < length) + lower = middle; + else + return middle; + } + + return -1; +} +#endif /* WCHAR */ + +/* This is a separate function so that we can force an alloca cleanup + afterwards. */ +#ifdef WCHAR +static int +wcs_re_match_2_internal (struct re_pattern_buffer *bufp, + const char *cstring1, int csize1, + const char *cstring2, int csize2, + int pos, + struct re_registers *regs, + int stop, + /* string1 == string2 == NULL means string1/2, size1/2 and + mbs_offset1/2 need seting up in this function. */ + /* We need wchar_t* buffers correspond to cstring1, cstring2. */ + wchar_t *string1, int size1, + wchar_t *string2, int size2, + /* offset buffer for optimizatoin. See convert_mbs_to_wc. */ + int *mbs_offset1, int *mbs_offset2) +#else /* BYTE */ +static int +byte_re_match_2_internal (struct re_pattern_buffer *bufp, + const char *string1, int size1, + const char *string2, int size2, + int pos, + struct re_registers *regs, int stop) +#endif /* BYTE */ +{ + /* General temporaries. */ + int mcnt; + UCHAR_T *p1; +#ifdef WCHAR + /* They hold whether each wchar_t is binary data or not. */ + char *is_binary = NULL; + /* If true, we can't free string1/2, mbs_offset1/2. */ + int cant_free_wcs_buf = 1; +#endif /* WCHAR */ + + /* Just past the end of the corresponding string. */ + const CHAR_T *end1, *end2; + + /* Pointers into string1 and string2, just past the last characters in + each to consider matching. */ + const CHAR_T *end_match_1, *end_match_2; + + /* Where we are in the data, and the end of the current string. */ + const CHAR_T *d, *dend; + + /* Where we are in the pattern, and the end of the pattern. */ +#ifdef WCHAR + UCHAR_T *pattern, *p; + register UCHAR_T *pend; +#else /* BYTE */ + UCHAR_T *p = bufp->buffer; + register UCHAR_T *pend = p + bufp->used; +#endif /* WCHAR */ + + /* Mark the opcode just after a start_memory, so we can test for an + empty subpattern when we get to the stop_memory. */ + UCHAR_T *just_past_start_mem = 0; + + /* We use this to map every character in the string. */ + RE_TRANSLATE_TYPE translate = bufp->translate; + + /* Failure point stack. Each place that can handle a failure further + down the line pushes a failure point on this stack. It consists of + restart, regend, and reg_info for all registers corresponding to + the subexpressions we're currently inside, plus the number of such + registers, and, finally, two char *'s. The first char * is where + to resume scanning the pattern; the second one is where to resume + scanning the strings. If the latter is zero, the failure point is + a ``dummy''; if a failure happens and the failure point is a dummy, + it gets discarded and the next next one is tried. */ +#ifdef MATCH_MAY_ALLOCATE /* otherwise, this is global. */ + PREFIX(fail_stack_type) fail_stack; +#endif +#ifdef DEBUG + static unsigned failure_id; + unsigned nfailure_points_pushed = 0, nfailure_points_popped = 0; +#endif + +#ifdef REL_ALLOC + /* This holds the pointer to the failure stack, when + it is allocated relocatably. */ + fail_stack_elt_t *failure_stack_ptr; +#endif + + /* We fill all the registers internally, independent of what we + return, for use in backreferences. The number here includes + an element for register zero. */ + size_t num_regs = bufp->re_nsub + 1; + + /* The currently active registers. */ + active_reg_t lowest_active_reg = NO_LOWEST_ACTIVE_REG; + active_reg_t highest_active_reg = NO_HIGHEST_ACTIVE_REG; + + /* Information on the contents of registers. These are pointers into + the input strings; they record just what was matched (on this + attempt) by a subexpression part of the pattern, that is, the + regnum-th regstart pointer points to where in the pattern we began + matching and the regnum-th regend points to right after where we + stopped matching the regnum-th subexpression. (The zeroth register + keeps track of what the whole pattern matches.) */ +#ifdef MATCH_MAY_ALLOCATE /* otherwise, these are global. */ + const CHAR_T **regstart, **regend; +#endif + + /* If a group that's operated upon by a repetition operator fails to + match anything, then the register for its start will need to be + restored because it will have been set to wherever in the string we + are when we last see its open-group operator. Similarly for a + register's end. */ +#ifdef MATCH_MAY_ALLOCATE /* otherwise, these are global. */ + const CHAR_T **old_regstart, **old_regend; +#endif + + /* The is_active field of reg_info helps us keep track of which (possibly + nested) subexpressions we are currently in. The matched_something + field of reg_info[reg_num] helps us tell whether or not we have + matched any of the pattern so far this time through the reg_num-th + subexpression. These two fields get reset each time through any + loop their register is in. */ +#ifdef MATCH_MAY_ALLOCATE /* otherwise, this is global. */ + PREFIX(register_info_type) *reg_info; +#endif + + /* The following record the register info as found in the above + variables when we find a match better than any we've seen before. + This happens as we backtrack through the failure points, which in + turn happens only if we have not yet matched the entire string. */ + unsigned best_regs_set = false; +#ifdef MATCH_MAY_ALLOCATE /* otherwise, these are global. */ + const CHAR_T **best_regstart, **best_regend; +#endif + + /* Logically, this is `best_regend[0]'. But we don't want to have to + allocate space for that if we're not allocating space for anything + else (see below). Also, we never need info about register 0 for + any of the other register vectors, and it seems rather a kludge to + treat `best_regend' differently than the rest. So we keep track of + the end of the best match so far in a separate variable. We + initialize this to NULL so that when we backtrack the first time + and need to test it, it's not garbage. */ + const CHAR_T *match_end = NULL; + + /* This helps SET_REGS_MATCHED avoid doing redundant work. */ + int set_regs_matched_done = 0; + + /* Used when we pop values we don't care about. */ +#ifdef MATCH_MAY_ALLOCATE /* otherwise, these are global. */ + const CHAR_T **reg_dummy; + PREFIX(register_info_type) *reg_info_dummy; +#endif + +#ifdef DEBUG + /* Counts the total number of registers pushed. */ + unsigned num_regs_pushed = 0; +#endif + + DEBUG_PRINT1 ("\n\nEntering re_match_2.\n"); + + INIT_FAIL_STACK (); + +#ifdef MATCH_MAY_ALLOCATE + /* Do not bother to initialize all the register variables if there are + no groups in the pattern, as it takes a fair amount of time. If + there are groups, we include space for register 0 (the whole + pattern), even though we never use it, since it simplifies the + array indexing. We should fix this. */ + if (bufp->re_nsub) + { + regstart = REGEX_TALLOC (num_regs, const CHAR_T *); + regend = REGEX_TALLOC (num_regs, const CHAR_T *); + old_regstart = REGEX_TALLOC (num_regs, const CHAR_T *); + old_regend = REGEX_TALLOC (num_regs, const CHAR_T *); + best_regstart = REGEX_TALLOC (num_regs, const CHAR_T *); + best_regend = REGEX_TALLOC (num_regs, const CHAR_T *); + reg_info = REGEX_TALLOC (num_regs, PREFIX(register_info_type)); + reg_dummy = REGEX_TALLOC (num_regs, const CHAR_T *); + reg_info_dummy = REGEX_TALLOC (num_regs, PREFIX(register_info_type)); + + if (!(regstart && regend && old_regstart && old_regend && reg_info + && best_regstart && best_regend && reg_dummy && reg_info_dummy)) + { + FREE_VARIABLES (); + return -2; + } + } + else + { + /* We must initialize all our variables to NULL, so that + `FREE_VARIABLES' doesn't try to free them. */ + regstart = regend = old_regstart = old_regend = best_regstart + = best_regend = reg_dummy = NULL; + reg_info = reg_info_dummy = (PREFIX(register_info_type) *) NULL; + } +#endif /* MATCH_MAY_ALLOCATE */ + + /* The starting position is bogus. */ +#ifdef WCHAR + if (pos < 0 || pos > csize1 + csize2) +#else /* BYTE */ + if (pos < 0 || pos > size1 + size2) +#endif + { + FREE_VARIABLES (); + return -1; + } + +#ifdef WCHAR + /* Allocate wchar_t array for string1 and string2 and + fill them with converted string. */ + if (string1 == NULL && string2 == NULL) + { + /* We need seting up buffers here. */ + + /* We must free wcs buffers in this function. */ + cant_free_wcs_buf = 0; + + if (csize1 != 0) + { + string1 = REGEX_TALLOC (csize1 + 1, CHAR_T); + mbs_offset1 = REGEX_TALLOC (csize1 + 1, int); + is_binary = REGEX_TALLOC (csize1 + 1, char); + if (!string1 || !mbs_offset1 || !is_binary) + { + FREE_VAR (string1); + FREE_VAR (mbs_offset1); + FREE_VAR (is_binary); + return -2; + } + } + if (csize2 != 0) + { + string2 = REGEX_TALLOC (csize2 + 1, CHAR_T); + mbs_offset2 = REGEX_TALLOC (csize2 + 1, int); + is_binary = REGEX_TALLOC (csize2 + 1, char); + if (!string2 || !mbs_offset2 || !is_binary) + { + FREE_VAR (string1); + FREE_VAR (mbs_offset1); + FREE_VAR (string2); + FREE_VAR (mbs_offset2); + FREE_VAR (is_binary); + return -2; + } + size2 = convert_mbs_to_wcs(string2, cstring2, csize2, + mbs_offset2, is_binary); + string2[size2] = L'\0'; /* for a sentinel */ + FREE_VAR (is_binary); + } + } + + /* We need to cast pattern to (wchar_t*), because we casted this compiled + pattern to (char*) in regex_compile. */ + p = pattern = (CHAR_T*)bufp->buffer; + pend = (CHAR_T*)(bufp->buffer + bufp->used); + +#endif /* WCHAR */ + + /* Initialize subexpression text positions to -1 to mark ones that no + start_memory/stop_memory has been seen for. Also initialize the + register information struct. */ + for (mcnt = 1; (unsigned) mcnt < num_regs; mcnt++) + { + regstart[mcnt] = regend[mcnt] + = old_regstart[mcnt] = old_regend[mcnt] = REG_UNSET_VALUE; + + REG_MATCH_NULL_STRING_P (reg_info[mcnt]) = MATCH_NULL_UNSET_VALUE; + IS_ACTIVE (reg_info[mcnt]) = 0; + MATCHED_SOMETHING (reg_info[mcnt]) = 0; + EVER_MATCHED_SOMETHING (reg_info[mcnt]) = 0; + } + + /* We move `string1' into `string2' if the latter's empty -- but not if + `string1' is null. */ + if (size2 == 0 && string1 != NULL) + { + string2 = string1; + size2 = size1; + string1 = 0; + size1 = 0; +#ifdef WCHAR + mbs_offset2 = mbs_offset1; + csize2 = csize1; + mbs_offset1 = NULL; + csize1 = 0; +#endif + } + end1 = string1 + size1; + end2 = string2 + size2; + + /* Compute where to stop matching, within the two strings. */ +#ifdef WCHAR + if (stop <= csize1) + { + mcnt = count_mbs_length(mbs_offset1, stop); + end_match_1 = string1 + mcnt; + end_match_2 = string2; + } + else + { + if (stop > csize1 + csize2) + stop = csize1 + csize2; + end_match_1 = end1; + mcnt = count_mbs_length(mbs_offset2, stop-csize1); + end_match_2 = string2 + mcnt; + } + if (mcnt < 0) + { /* count_mbs_length return error. */ + FREE_VARIABLES (); + return -1; + } +#else + if (stop <= size1) + { + end_match_1 = string1 + stop; + end_match_2 = string2; + } + else + { + end_match_1 = end1; + end_match_2 = string2 + stop - size1; + } +#endif /* WCHAR */ + + /* `p' scans through the pattern as `d' scans through the data. + `dend' is the end of the input string that `d' points within. `d' + is advanced into the following input string whenever necessary, but + this happens before fetching; therefore, at the beginning of the + loop, `d' can be pointing at the end of a string, but it cannot + equal `string2'. */ +#ifdef WCHAR + if (size1 > 0 && pos <= csize1) + { + mcnt = count_mbs_length(mbs_offset1, pos); + d = string1 + mcnt; + dend = end_match_1; + } + else + { + mcnt = count_mbs_length(mbs_offset2, pos-csize1); + d = string2 + mcnt; + dend = end_match_2; + } + + if (mcnt < 0) + { /* count_mbs_length return error. */ + FREE_VARIABLES (); + return -1; + } +#else + if (size1 > 0 && pos <= size1) + { + d = string1 + pos; + dend = end_match_1; + } + else + { + d = string2 + pos - size1; + dend = end_match_2; + } +#endif /* WCHAR */ + + DEBUG_PRINT1 ("The compiled pattern is:\n"); + DEBUG_PRINT_COMPILED_PATTERN (bufp, p, pend); + DEBUG_PRINT1 ("The string to match is: `"); + DEBUG_PRINT_DOUBLE_STRING (d, string1, size1, string2, size2); + DEBUG_PRINT1 ("'\n"); + + /* This loops over pattern commands. It exits by returning from the + function if the match is complete, or it drops through if the match + fails at this starting point in the input data. */ + for (;;) + { +#ifdef _LIBC + DEBUG_PRINT2 ("\n%p: ", p); +#else + DEBUG_PRINT2 ("\n0x%x: ", p); +#endif + + if (p == pend) + { /* End of pattern means we might have succeeded. */ + DEBUG_PRINT1 ("end of pattern ... "); + + /* If we haven't matched the entire string, and we want the + longest match, try backtracking. */ + if (d != end_match_2) + { + /* 1 if this match ends in the same string (string1 or string2) + as the best previous match. */ + boolean same_str_p; + + /* 1 if this match is the best seen so far. */ + boolean best_match_p; + + same_str_p = (FIRST_STRING_P (match_end) + == MATCHING_IN_FIRST_STRING); + + /* AIX compiler got confused when this was combined + with the previous declaration. */ + if (same_str_p) + best_match_p = d > match_end; + else + best_match_p = !MATCHING_IN_FIRST_STRING; + + DEBUG_PRINT1 ("backtracking.\n"); + + if (!FAIL_STACK_EMPTY ()) + { /* More failure points to try. */ + + /* If exceeds best match so far, save it. */ + if (!best_regs_set || best_match_p) + { + best_regs_set = true; + match_end = d; + + DEBUG_PRINT1 ("\nSAVING match as best so far.\n"); + + for (mcnt = 1; (unsigned) mcnt < num_regs; mcnt++) + { + best_regstart[mcnt] = regstart[mcnt]; + best_regend[mcnt] = regend[mcnt]; + } + } + goto fail; + } + + /* If no failure points, don't restore garbage. And if + last match is real best match, don't restore second + best one. */ + else if (best_regs_set && !best_match_p) + { + restore_best_regs: + /* Restore best match. It may happen that `dend == + end_match_1' while the restored d is in string2. + For example, the pattern `x.*y.*z' against the + strings `x-' and `y-z-', if the two strings are + not consecutive in memory. */ + DEBUG_PRINT1 ("Restoring best registers.\n"); + + d = match_end; + dend = ((d >= string1 && d <= end1) + ? end_match_1 : end_match_2); + + for (mcnt = 1; (unsigned) mcnt < num_regs; mcnt++) + { + regstart[mcnt] = best_regstart[mcnt]; + regend[mcnt] = best_regend[mcnt]; + } + } + } /* d != end_match_2 */ + + succeed_label: + DEBUG_PRINT1 ("Accepting match.\n"); + /* If caller wants register contents data back, do it. */ + if (regs && !bufp->no_sub) + { + /* Have the register data arrays been allocated? */ + if (bufp->regs_allocated == REGS_UNALLOCATED) + { /* No. So allocate them with malloc. We need one + extra element beyond `num_regs' for the `-1' marker + GNU code uses. */ + regs->num_regs = MAX (RE_NREGS, num_regs + 1); + regs->start = TALLOC (regs->num_regs, regoff_t); + regs->end = TALLOC (regs->num_regs, regoff_t); + if (regs->start == NULL || regs->end == NULL) + { + FREE_VARIABLES (); + return -2; + } + bufp->regs_allocated = REGS_REALLOCATE; + } + else if (bufp->regs_allocated == REGS_REALLOCATE) + { /* Yes. If we need more elements than were already + allocated, reallocate them. If we need fewer, just + leave it alone. */ + if (regs->num_regs < num_regs + 1) + { + regs->num_regs = num_regs + 1; + RETALLOC (regs->start, regs->num_regs, regoff_t); + RETALLOC (regs->end, regs->num_regs, regoff_t); + if (regs->start == NULL || regs->end == NULL) + { + FREE_VARIABLES (); + return -2; + } + } + } + else + { + /* These braces fend off a "empty body in an else-statement" + warning under GCC when assert expands to nothing. */ + assert (bufp->regs_allocated == REGS_FIXED); + } + + /* Convert the pointer data in `regstart' and `regend' to + indices. Register zero has to be set differently, + since we haven't kept track of any info for it. */ + if (regs->num_regs > 0) + { + regs->start[0] = pos; +#ifdef WCHAR + if (MATCHING_IN_FIRST_STRING) + regs->end[0] = mbs_offset1 != NULL ? + mbs_offset1[d-string1] : 0; + else + regs->end[0] = csize1 + (mbs_offset2 != NULL ? + mbs_offset2[d-string2] : 0); +#else + regs->end[0] = (MATCHING_IN_FIRST_STRING + ? ((regoff_t) (d - string1)) + : ((regoff_t) (d - string2 + size1))); +#endif /* WCHAR */ + } + + /* Go through the first `min (num_regs, regs->num_regs)' + registers, since that is all we initialized. */ + for (mcnt = 1; (unsigned) mcnt < MIN (num_regs, regs->num_regs); + mcnt++) + { + if (REG_UNSET (regstart[mcnt]) || REG_UNSET (regend[mcnt])) + regs->start[mcnt] = regs->end[mcnt] = -1; + else + { + regs->start[mcnt] + = (regoff_t) POINTER_TO_OFFSET (regstart[mcnt]); + regs->end[mcnt] + = (regoff_t) POINTER_TO_OFFSET (regend[mcnt]); + } + } + + /* If the regs structure we return has more elements than + were in the pattern, set the extra elements to -1. If + we (re)allocated the registers, this is the case, + because we always allocate enough to have at least one + -1 at the end. */ + for (mcnt = num_regs; (unsigned) mcnt < regs->num_regs; mcnt++) + regs->start[mcnt] = regs->end[mcnt] = -1; + } /* regs && !bufp->no_sub */ + + DEBUG_PRINT4 ("%u failure points pushed, %u popped (%u remain).\n", + nfailure_points_pushed, nfailure_points_popped, + nfailure_points_pushed - nfailure_points_popped); + DEBUG_PRINT2 ("%u registers pushed.\n", num_regs_pushed); + +#ifdef WCHAR + if (MATCHING_IN_FIRST_STRING) + mcnt = mbs_offset1 != NULL ? mbs_offset1[d-string1] : 0; + else + mcnt = (mbs_offset2 != NULL ? mbs_offset2[d-string2] : 0) + + csize1; + mcnt -= pos; +#else + mcnt = d - pos - (MATCHING_IN_FIRST_STRING + ? string1 + : string2 - size1); +#endif /* WCHAR */ + + DEBUG_PRINT2 ("Returning %d from re_match_2.\n", mcnt); + + FREE_VARIABLES (); + return mcnt; + } + + /* Otherwise match next pattern command. */ + switch (SWITCH_ENUM_CAST ((re_opcode_t) *p++)) + { + /* Ignore these. Used to ignore the n of succeed_n's which + currently have n == 0. */ + case no_op: + DEBUG_PRINT1 ("EXECUTING no_op.\n"); + break; + + case succeed: + DEBUG_PRINT1 ("EXECUTING succeed.\n"); + goto succeed_label; + + /* Match the next n pattern characters exactly. The following + byte in the pattern defines n, and the n bytes after that + are the characters to match. */ + case exactn: +#ifdef MBS_SUPPORT + case exactn_bin: +#endif + mcnt = *p++; + DEBUG_PRINT2 ("EXECUTING exactn %d.\n", mcnt); + + /* This is written out as an if-else so we don't waste time + testing `translate' inside the loop. */ + if (translate) + { + do + { + PREFETCH (); +#ifdef WCHAR + if (*d <= 0xff) + { + if ((UCHAR_T) translate[(unsigned char) *d++] + != (UCHAR_T) *p++) + goto fail; + } + else + { + if (*d++ != (CHAR_T) *p++) + goto fail; + } +#else + if ((UCHAR_T) translate[(unsigned char) *d++] + != (UCHAR_T) *p++) + goto fail; +#endif /* WCHAR */ + } + while (--mcnt); + } + else + { + do + { + PREFETCH (); + if (*d++ != (CHAR_T) *p++) goto fail; + } + while (--mcnt); + } + SET_REGS_MATCHED (); + break; + + + /* Match any character except possibly a newline or a null. */ + case anychar: + DEBUG_PRINT1 ("EXECUTING anychar.\n"); + + PREFETCH (); + + if ((!(bufp->syntax & RE_DOT_NEWLINE) && TRANSLATE (*d) == '\n') + || (bufp->syntax & RE_DOT_NOT_NULL && TRANSLATE (*d) == '\000')) + goto fail; + + SET_REGS_MATCHED (); + DEBUG_PRINT2 (" Matched `%ld'.\n", (long int) *d); + d++; + break; + + + case charset: + case charset_not: + { + register UCHAR_T c; +#ifdef WCHAR + unsigned int i, char_class_length, coll_symbol_length, + equiv_class_length, ranges_length, chars_length, length; + CHAR_T *workp, *workp2, *charset_top; +#define WORK_BUFFER_SIZE 128 + CHAR_T str_buf[WORK_BUFFER_SIZE]; +# ifdef _LIBC + uint32_t nrules; +# endif /* _LIBC */ +#endif /* WCHAR */ + boolean negate = (re_opcode_t) *(p - 1) == charset_not; + + DEBUG_PRINT2 ("EXECUTING charset%s.\n", negate ? "_not" : ""); + PREFETCH (); + c = TRANSLATE (*d); /* The character to match. */ +#ifdef WCHAR +# ifdef _LIBC + nrules = _NL_CURRENT_WORD (LC_COLLATE, _NL_COLLATE_NRULES); +# endif /* _LIBC */ + charset_top = p - 1; + char_class_length = *p++; + coll_symbol_length = *p++; + equiv_class_length = *p++; + ranges_length = *p++; + chars_length = *p++; + /* p points charset[6], so the address of the next instruction + (charset[l+m+n+2o+k+p']) equals p[l+m+n+2*o+p'], + where l=length of char_classes, m=length of collating_symbol, + n=equivalence_class, o=length of char_range, + p'=length of character. */ + workp = p; + /* Update p to indicate the next instruction. */ + p += char_class_length + coll_symbol_length+ equiv_class_length + + 2*ranges_length + chars_length; + + /* match with char_class? */ + for (i = 0; i < char_class_length ; i += CHAR_CLASS_SIZE) + { + wctype_t wctype; + uintptr_t alignedp = ((uintptr_t)workp + + __alignof__(wctype_t) - 1) + & ~(uintptr_t)(__alignof__(wctype_t) - 1); + wctype = *((wctype_t*)alignedp); + workp += CHAR_CLASS_SIZE; +# ifdef _LIBC + if (__iswctype((wint_t)c, wctype)) + goto char_set_matched; +# else + if (iswctype((wint_t)c, wctype)) + goto char_set_matched; +# endif + } + + /* match with collating_symbol? */ +# ifdef _LIBC + if (nrules != 0) + { + const unsigned char *extra = (const unsigned char *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_SYMB_EXTRAMB); + + for (workp2 = workp + coll_symbol_length ; workp < workp2 ; + workp++) + { + int32_t *wextra; + wextra = (int32_t*)(extra + *workp++); + for (i = 0; i < *wextra; ++i) + if (TRANSLATE(d[i]) != wextra[1 + i]) + break; + + if (i == *wextra) + { + /* Update d, however d will be incremented at + char_set_matched:, we decrement d here. */ + d += i - 1; + goto char_set_matched; + } + } + } + else /* (nrules == 0) */ +# endif + /* If we can't look up collation data, we use wcscoll + instead. */ + { + for (workp2 = workp + coll_symbol_length ; workp < workp2 ;) + { + const CHAR_T *backup_d = d, *backup_dend = dend; +# ifdef _LIBC + length = __wcslen (workp); +# else + length = wcslen (workp); +# endif + + /* If wcscoll(the collating symbol, whole string) > 0, + any substring of the string never match with the + collating symbol. */ +# ifdef _LIBC + if (__wcscoll (workp, d) > 0) +# else + if (wcscoll (workp, d) > 0) +# endif + { + workp += length + 1; + continue; + } + + /* First, we compare the collating symbol with + the first character of the string. + If it don't match, we add the next character to + the compare buffer in turn. */ + for (i = 0 ; i < WORK_BUFFER_SIZE-1 ; i++, d++) + { + int match; + if (d == dend) + { + if (dend == end_match_2) + break; + d = string2; + dend = end_match_2; + } + + /* add next character to the compare buffer. */ + str_buf[i] = TRANSLATE(*d); + str_buf[i+1] = '\0'; + +# ifdef _LIBC + match = __wcscoll (workp, str_buf); +# else + match = wcscoll (workp, str_buf); +# endif + if (match == 0) + goto char_set_matched; + + if (match < 0) + /* (str_buf > workp) indicate (str_buf + X > workp), + because for all X (str_buf + X > str_buf). + So we don't need continue this loop. */ + break; + + /* Otherwise(str_buf < workp), + (str_buf+next_character) may equals (workp). + So we continue this loop. */ + } + /* not matched */ + d = backup_d; + dend = backup_dend; + workp += length + 1; + } + } + /* match with equivalence_class? */ +# ifdef _LIBC + if (nrules != 0) + { + const CHAR_T *backup_d = d, *backup_dend = dend; + /* Try to match the equivalence class against + those known to the collate implementation. */ + const int32_t *table; + const int32_t *weights; + const int32_t *extra; + const int32_t *indirect; + int32_t idx, idx2; + wint_t *cp; + size_t len; + + /* This #include defines a local function! */ +# include + + table = (const int32_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_TABLEWC); + weights = (const wint_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_WEIGHTWC); + extra = (const wint_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_EXTRAWC); + indirect = (const int32_t *) + _NL_CURRENT (LC_COLLATE, _NL_COLLATE_INDIRECTWC); + + /* Write 1 collating element to str_buf, and + get its index. */ + idx2 = 0; + + for (i = 0 ; idx2 == 0 && i < WORK_BUFFER_SIZE - 1; i++) + { + cp = (wint_t*)str_buf; + if (d == dend) + { + if (dend == end_match_2) + break; + d = string2; + dend = end_match_2; + } + str_buf[i] = TRANSLATE(*(d+i)); + str_buf[i+1] = '\0'; /* sentinel */ + idx2 = findidx ((const wint_t**)&cp); + } + + /* Update d, however d will be incremented at + char_set_matched:, we decrement d here. */ + d = backup_d + ((wchar_t*)cp - (wchar_t*)str_buf - 1); + if (d >= dend) + { + if (dend == end_match_2) + d = dend; + else + { + d = string2; + dend = end_match_2; + } + } + + len = weights[idx2]; + + for (workp2 = workp + equiv_class_length ; workp < workp2 ; + workp++) + { + idx = (int32_t)*workp; + /* We already checked idx != 0 in regex_compile. */ + + if (idx2 != 0 && len == weights[idx]) + { + int cnt = 0; + while (cnt < len && (weights[idx + 1 + cnt] + == weights[idx2 + 1 + cnt])) + ++cnt; + + if (cnt == len) + goto char_set_matched; + } + } + /* not matched */ + d = backup_d; + dend = backup_dend; + } + else /* (nrules == 0) */ +# endif + /* If we can't look up collation data, we use wcscoll + instead. */ + { + for (workp2 = workp + equiv_class_length ; workp < workp2 ;) + { + const CHAR_T *backup_d = d, *backup_dend = dend; +# ifdef _LIBC + length = __wcslen (workp); +# else + length = wcslen (workp); +# endif + + /* If wcscoll(the collating symbol, whole string) > 0, + any substring of the string never match with the + collating symbol. */ +# ifdef _LIBC + if (__wcscoll (workp, d) > 0) +# else + if (wcscoll (workp, d) > 0) +# endif + { + workp += length + 1; + break; + } + + /* First, we compare the equivalence class with + the first character of the string. + If it don't match, we add the next character to + the compare buffer in turn. */ + for (i = 0 ; i < WORK_BUFFER_SIZE - 1 ; i++, d++) + { + int match; + if (d == dend) + { + if (dend == end_match_2) + break; + d = string2; + dend = end_match_2; + } + + /* add next character to the compare buffer. */ + str_buf[i] = TRANSLATE(*d); + str_buf[i+1] = '\0'; + +# ifdef _LIBC + match = __wcscoll (workp, str_buf); +# else + match = wcscoll (workp, str_buf); +# endif + + if (match == 0) + goto char_set_matched; + + if (match < 0) + /* (str_buf > workp) indicate (str_buf + X > workp), + because for all X (str_buf + X > str_buf). + So we don't need continue this loop. */ + break; + + /* Otherwise(str_buf < workp), + (str_buf+next_character) may equals (workp). + So we continue this loop. */ + } + /* not matched */ + d = backup_d; + dend = backup_dend; + workp += length + 1; + } + } + + /* match with char_range? */ +# ifdef _LIBC + if (nrules != 0) + { + uint32_t collseqval; + const char *collseq = (const char *) + _NL_CURRENT(LC_COLLATE, _NL_COLLATE_COLLSEQWC); + + collseqval = collseq_table_lookup (collseq, c); + + for (; workp < p - chars_length ;) + { + uint32_t start_val, end_val; + + /* We already compute the collation sequence value + of the characters (or collating symbols). */ + start_val = (uint32_t) *workp++; /* range_start */ + end_val = (uint32_t) *workp++; /* range_end */ + + if (start_val <= collseqval && collseqval <= end_val) + goto char_set_matched; + } + } + else +# endif + { + /* We set range_start_char at str_buf[0], range_end_char + at str_buf[4], and compared char at str_buf[2]. */ + str_buf[1] = 0; + str_buf[2] = c; + str_buf[3] = 0; + str_buf[5] = 0; + for (; workp < p - chars_length ;) + { + wchar_t *range_start_char, *range_end_char; + + /* match if (range_start_char <= c <= range_end_char). */ + + /* If range_start(or end) < 0, we assume -range_start(end) + is the offset of the collating symbol which is specified + as the character of the range start(end). */ + + /* range_start */ + if (*workp < 0) + range_start_char = charset_top - (*workp++); + else + { + str_buf[0] = *workp++; + range_start_char = str_buf; + } + + /* range_end */ + if (*workp < 0) + range_end_char = charset_top - (*workp++); + else + { + str_buf[4] = *workp++; + range_end_char = str_buf + 4; + } + +# ifdef _LIBC + if (__wcscoll (range_start_char, str_buf+2) <= 0 + && __wcscoll (str_buf+2, range_end_char) <= 0) +# else + if (wcscoll (range_start_char, str_buf+2) <= 0 + && wcscoll (str_buf+2, range_end_char) <= 0) +# endif + goto char_set_matched; + } + } + + /* match with char? */ + for (; workp < p ; workp++) + if (c == *workp) + goto char_set_matched; + + negate = !negate; + + char_set_matched: + if (negate) goto fail; +#else + /* Cast to `unsigned' instead of `unsigned char' in case the + bit list is a full 32 bytes long. */ + if (c < (unsigned) (*p * BYTEWIDTH) + && p[1 + c / BYTEWIDTH] & (1 << (c % BYTEWIDTH))) + negate = !negate; + + p += 1 + *p; + + if (!negate) goto fail; +#undef WORK_BUFFER_SIZE +#endif /* WCHAR */ + SET_REGS_MATCHED (); + d++; + break; + } + + + /* The beginning of a group is represented by start_memory. + The arguments are the register number in the next byte, and the + number of groups inner to this one in the next. The text + matched within the group is recorded (in the internal + registers data structure) under the register number. */ + case start_memory: + DEBUG_PRINT3 ("EXECUTING start_memory %ld (%ld):\n", + (long int) *p, (long int) p[1]); + + /* Find out if this group can match the empty string. */ + p1 = p; /* To send to group_match_null_string_p. */ + + if (REG_MATCH_NULL_STRING_P (reg_info[*p]) == MATCH_NULL_UNSET_VALUE) + REG_MATCH_NULL_STRING_P (reg_info[*p]) + = PREFIX(group_match_null_string_p) (&p1, pend, reg_info); + + /* Save the position in the string where we were the last time + we were at this open-group operator in case the group is + operated upon by a repetition operator, e.g., with `(a*)*b' + against `ab'; then we want to ignore where we are now in + the string in case this attempt to match fails. */ + old_regstart[*p] = REG_MATCH_NULL_STRING_P (reg_info[*p]) + ? REG_UNSET (regstart[*p]) ? d : regstart[*p] + : regstart[*p]; + DEBUG_PRINT2 (" old_regstart: %d\n", + POINTER_TO_OFFSET (old_regstart[*p])); + + regstart[*p] = d; + DEBUG_PRINT2 (" regstart: %d\n", POINTER_TO_OFFSET (regstart[*p])); + + IS_ACTIVE (reg_info[*p]) = 1; + MATCHED_SOMETHING (reg_info[*p]) = 0; + + /* Clear this whenever we change the register activity status. */ + set_regs_matched_done = 0; + + /* This is the new highest active register. */ + highest_active_reg = *p; + + /* If nothing was active before, this is the new lowest active + register. */ + if (lowest_active_reg == NO_LOWEST_ACTIVE_REG) + lowest_active_reg = *p; + + /* Move past the register number and inner group count. */ + p += 2; + just_past_start_mem = p; + + break; + + + /* The stop_memory opcode represents the end of a group. Its + arguments are the same as start_memory's: the register + number, and the number of inner groups. */ + case stop_memory: + DEBUG_PRINT3 ("EXECUTING stop_memory %ld (%ld):\n", + (long int) *p, (long int) p[1]); + + /* We need to save the string position the last time we were at + this close-group operator in case the group is operated + upon by a repetition operator, e.g., with `((a*)*(b*)*)*' + against `aba'; then we want to ignore where we are now in + the string in case this attempt to match fails. */ + old_regend[*p] = REG_MATCH_NULL_STRING_P (reg_info[*p]) + ? REG_UNSET (regend[*p]) ? d : regend[*p] + : regend[*p]; + DEBUG_PRINT2 (" old_regend: %d\n", + POINTER_TO_OFFSET (old_regend[*p])); + + regend[*p] = d; + DEBUG_PRINT2 (" regend: %d\n", POINTER_TO_OFFSET (regend[*p])); + + /* This register isn't active anymore. */ + IS_ACTIVE (reg_info[*p]) = 0; + + /* Clear this whenever we change the register activity status. */ + set_regs_matched_done = 0; + + /* If this was the only register active, nothing is active + anymore. */ + if (lowest_active_reg == highest_active_reg) + { + lowest_active_reg = NO_LOWEST_ACTIVE_REG; + highest_active_reg = NO_HIGHEST_ACTIVE_REG; + } + else + { /* We must scan for the new highest active register, since + it isn't necessarily one less than now: consider + (a(b)c(d(e)f)g). When group 3 ends, after the f), the + new highest active register is 1. */ + UCHAR_T r = *p - 1; + while (r > 0 && !IS_ACTIVE (reg_info[r])) + r--; + + /* If we end up at register zero, that means that we saved + the registers as the result of an `on_failure_jump', not + a `start_memory', and we jumped to past the innermost + `stop_memory'. For example, in ((.)*) we save + registers 1 and 2 as a result of the *, but when we pop + back to the second ), we are at the stop_memory 1. + Thus, nothing is active. */ + if (r == 0) + { + lowest_active_reg = NO_LOWEST_ACTIVE_REG; + highest_active_reg = NO_HIGHEST_ACTIVE_REG; + } + else + highest_active_reg = r; + } + + /* If just failed to match something this time around with a + group that's operated on by a repetition operator, try to + force exit from the ``loop'', and restore the register + information for this group that we had before trying this + last match. */ + if ((!MATCHED_SOMETHING (reg_info[*p]) + || just_past_start_mem == p - 1) + && (p + 2) < pend) + { + boolean is_a_jump_n = false; + + p1 = p + 2; + mcnt = 0; + switch ((re_opcode_t) *p1++) + { + case jump_n: + is_a_jump_n = true; + case pop_failure_jump: + case maybe_pop_jump: + case jump: + case dummy_failure_jump: + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + if (is_a_jump_n) + p1 += OFFSET_ADDRESS_SIZE; + break; + + default: + /* do nothing */ ; + } + p1 += mcnt; + + /* If the next operation is a jump backwards in the pattern + to an on_failure_jump right before the start_memory + corresponding to this stop_memory, exit from the loop + by forcing a failure after pushing on the stack the + on_failure_jump's jump in the pattern, and d. */ + if (mcnt < 0 && (re_opcode_t) *p1 == on_failure_jump + && (re_opcode_t) p1[1+OFFSET_ADDRESS_SIZE] == start_memory + && p1[2+OFFSET_ADDRESS_SIZE] == *p) + { + /* If this group ever matched anything, then restore + what its registers were before trying this last + failed match, e.g., with `(a*)*b' against `ab' for + regstart[1], and, e.g., with `((a*)*(b*)*)*' + against `aba' for regend[3]. + + Also restore the registers for inner groups for, + e.g., `((a*)(b*))*' against `aba' (register 3 would + otherwise get trashed). */ + + if (EVER_MATCHED_SOMETHING (reg_info[*p])) + { + unsigned r; + + EVER_MATCHED_SOMETHING (reg_info[*p]) = 0; + + /* Restore this and inner groups' (if any) registers. */ + for (r = *p; r < (unsigned) *p + (unsigned) *(p + 1); + r++) + { + regstart[r] = old_regstart[r]; + + /* xx why this test? */ + if (old_regend[r] >= regstart[r]) + regend[r] = old_regend[r]; + } + } + p1++; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + PUSH_FAILURE_POINT (p1 + mcnt, d, -2); + + goto fail; + } + } + + /* Move past the register number and the inner group count. */ + p += 2; + break; + + + /* \ has been turned into a `duplicate' command which is + followed by the numeric value of as the register number. */ + case duplicate: + { + register const CHAR_T *d2, *dend2; + int regno = *p++; /* Get which register to match against. */ + DEBUG_PRINT2 ("EXECUTING duplicate %d.\n", regno); + + /* Can't back reference a group which we've never matched. */ + if (REG_UNSET (regstart[regno]) || REG_UNSET (regend[regno])) + goto fail; + + /* Where in input to try to start matching. */ + d2 = regstart[regno]; + + /* Where to stop matching; if both the place to start and + the place to stop matching are in the same string, then + set to the place to stop, otherwise, for now have to use + the end of the first string. */ + + dend2 = ((FIRST_STRING_P (regstart[regno]) + == FIRST_STRING_P (regend[regno])) + ? regend[regno] : end_match_1); + for (;;) + { + /* If necessary, advance to next segment in register + contents. */ + while (d2 == dend2) + { + if (dend2 == end_match_2) break; + if (dend2 == regend[regno]) break; + + /* End of string1 => advance to string2. */ + d2 = string2; + dend2 = regend[regno]; + } + /* At end of register contents => success */ + if (d2 == dend2) break; + + /* If necessary, advance to next segment in data. */ + PREFETCH (); + + /* How many characters left in this segment to match. */ + mcnt = dend - d; + + /* Want how many consecutive characters we can match in + one shot, so, if necessary, adjust the count. */ + if (mcnt > dend2 - d2) + mcnt = dend2 - d2; + + /* Compare that many; failure if mismatch, else move + past them. */ + if (translate + ? PREFIX(bcmp_translate) (d, d2, mcnt, translate) + : memcmp (d, d2, mcnt*sizeof(UCHAR_T))) + goto fail; + d += mcnt, d2 += mcnt; + + /* Do this because we've match some characters. */ + SET_REGS_MATCHED (); + } + } + break; + + + /* begline matches the empty string at the beginning of the string + (unless `not_bol' is set in `bufp'), and, if + `newline_anchor' is set, after newlines. */ + case begline: + DEBUG_PRINT1 ("EXECUTING begline.\n"); + + if (AT_STRINGS_BEG (d)) + { + if (!bufp->not_bol) break; + } + else if (d[-1] == '\n' && bufp->newline_anchor) + { + break; + } + /* In all other cases, we fail. */ + goto fail; + + + /* endline is the dual of begline. */ + case endline: + DEBUG_PRINT1 ("EXECUTING endline.\n"); + + if (AT_STRINGS_END (d)) + { + if (!bufp->not_eol) break; + } + + /* We have to ``prefetch'' the next character. */ + else if ((d == end1 ? *string2 : *d) == '\n' + && bufp->newline_anchor) + { + break; + } + goto fail; + + + /* Match at the very beginning of the data. */ + case begbuf: + DEBUG_PRINT1 ("EXECUTING begbuf.\n"); + if (AT_STRINGS_BEG (d)) + break; + goto fail; + + + /* Match at the very end of the data. */ + case endbuf: + DEBUG_PRINT1 ("EXECUTING endbuf.\n"); + if (AT_STRINGS_END (d)) + break; + goto fail; + + + /* on_failure_keep_string_jump is used to optimize `.*\n'. It + pushes NULL as the value for the string on the stack. Then + `pop_failure_point' will keep the current value for the + string, instead of restoring it. To see why, consider + matching `foo\nbar' against `.*\n'. The .* matches the foo; + then the . fails against the \n. But the next thing we want + to do is match the \n against the \n; if we restored the + string value, we would be back at the foo. + + Because this is used only in specific cases, we don't need to + check all the things that `on_failure_jump' does, to make + sure the right things get saved on the stack. Hence we don't + share its code. The only reason to push anything on the + stack at all is that otherwise we would have to change + `anychar's code to do something besides goto fail in this + case; that seems worse than this. */ + case on_failure_keep_string_jump: + DEBUG_PRINT1 ("EXECUTING on_failure_keep_string_jump"); + + EXTRACT_NUMBER_AND_INCR (mcnt, p); +#ifdef _LIBC + DEBUG_PRINT3 (" %d (to %p):\n", mcnt, p + mcnt); +#else + DEBUG_PRINT3 (" %d (to 0x%x):\n", mcnt, p + mcnt); +#endif + + PUSH_FAILURE_POINT (p + mcnt, NULL, -2); + break; + + + /* Uses of on_failure_jump: + + Each alternative starts with an on_failure_jump that points + to the beginning of the next alternative. Each alternative + except the last ends with a jump that in effect jumps past + the rest of the alternatives. (They really jump to the + ending jump of the following alternative, because tensioning + these jumps is a hassle.) + + Repeats start with an on_failure_jump that points past both + the repetition text and either the following jump or + pop_failure_jump back to this on_failure_jump. */ + case on_failure_jump: + on_failure: + DEBUG_PRINT1 ("EXECUTING on_failure_jump"); + + EXTRACT_NUMBER_AND_INCR (mcnt, p); +#ifdef _LIBC + DEBUG_PRINT3 (" %d (to %p)", mcnt, p + mcnt); +#else + DEBUG_PRINT3 (" %d (to 0x%x)", mcnt, p + mcnt); +#endif + + /* If this on_failure_jump comes right before a group (i.e., + the original * applied to a group), save the information + for that group and all inner ones, so that if we fail back + to this point, the group's information will be correct. + For example, in \(a*\)*\1, we need the preceding group, + and in \(zz\(a*\)b*\)\2, we need the inner group. */ + + /* We can't use `p' to check ahead because we push + a failure point to `p + mcnt' after we do this. */ + p1 = p; + + /* We need to skip no_op's before we look for the + start_memory in case this on_failure_jump is happening as + the result of a completed succeed_n, as in \(a\)\{1,3\}b\1 + against aba. */ + while (p1 < pend && (re_opcode_t) *p1 == no_op) + p1++; + + if (p1 < pend && (re_opcode_t) *p1 == start_memory) + { + /* We have a new highest active register now. This will + get reset at the start_memory we are about to get to, + but we will have saved all the registers relevant to + this repetition op, as described above. */ + highest_active_reg = *(p1 + 1) + *(p1 + 2); + if (lowest_active_reg == NO_LOWEST_ACTIVE_REG) + lowest_active_reg = *(p1 + 1); + } + + DEBUG_PRINT1 (":\n"); + PUSH_FAILURE_POINT (p + mcnt, d, -2); + break; + + + /* A smart repeat ends with `maybe_pop_jump'. + We change it to either `pop_failure_jump' or `jump'. */ + case maybe_pop_jump: + EXTRACT_NUMBER_AND_INCR (mcnt, p); + DEBUG_PRINT2 ("EXECUTING maybe_pop_jump %d.\n", mcnt); + { + register UCHAR_T *p2 = p; + + /* Compare the beginning of the repeat with what in the + pattern follows its end. If we can establish that there + is nothing that they would both match, i.e., that we + would have to backtrack because of (as in, e.g., `a*a') + then we can change to pop_failure_jump, because we'll + never have to backtrack. + + This is not true in the case of alternatives: in + `(a|ab)*' we do need to backtrack to the `ab' alternative + (e.g., if the string was `ab'). But instead of trying to + detect that here, the alternative has put on a dummy + failure point which is what we will end up popping. */ + + /* Skip over open/close-group commands. + If what follows this loop is a ...+ construct, + look at what begins its body, since we will have to + match at least one of that. */ + while (1) + { + if (p2 + 2 < pend + && ((re_opcode_t) *p2 == stop_memory + || (re_opcode_t) *p2 == start_memory)) + p2 += 3; + else if (p2 + 2 + 2 * OFFSET_ADDRESS_SIZE < pend + && (re_opcode_t) *p2 == dummy_failure_jump) + p2 += 2 + 2 * OFFSET_ADDRESS_SIZE; + else + break; + } + + p1 = p + mcnt; + /* p1[0] ... p1[2] are the `on_failure_jump' corresponding + to the `maybe_finalize_jump' of this case. Examine what + follows. */ + + /* If we're at the end of the pattern, we can change. */ + if (p2 == pend) + { + /* Consider what happens when matching ":\(.*\)" + against ":/". I don't really understand this code + yet. */ + p[-(1+OFFSET_ADDRESS_SIZE)] = (UCHAR_T) + pop_failure_jump; + DEBUG_PRINT1 + (" End of pattern: change to `pop_failure_jump'.\n"); + } + + else if ((re_opcode_t) *p2 == exactn +#ifdef MBS_SUPPORT + || (re_opcode_t) *p2 == exactn_bin +#endif + || (bufp->newline_anchor && (re_opcode_t) *p2 == endline)) + { + register UCHAR_T c + = *p2 == (UCHAR_T) endline ? '\n' : p2[2]; + + if (((re_opcode_t) p1[1+OFFSET_ADDRESS_SIZE] == exactn +#ifdef MBS_SUPPORT + || (re_opcode_t) p1[1+OFFSET_ADDRESS_SIZE] == exactn_bin +#endif + ) && p1[3+OFFSET_ADDRESS_SIZE] != c) + { + p[-(1+OFFSET_ADDRESS_SIZE)] = (UCHAR_T) + pop_failure_jump; +#ifdef WCHAR + DEBUG_PRINT3 (" %C != %C => pop_failure_jump.\n", + (wint_t) c, + (wint_t) p1[3+OFFSET_ADDRESS_SIZE]); +#else + DEBUG_PRINT3 (" %c != %c => pop_failure_jump.\n", + (char) c, + (char) p1[3+OFFSET_ADDRESS_SIZE]); +#endif + } + +#ifndef WCHAR + else if ((re_opcode_t) p1[3] == charset + || (re_opcode_t) p1[3] == charset_not) + { + int negate = (re_opcode_t) p1[3] == charset_not; + + if (c < (unsigned) (p1[4] * BYTEWIDTH) + && p1[5 + c / BYTEWIDTH] & (1 << (c % BYTEWIDTH))) + negate = !negate; + + /* `negate' is equal to 1 if c would match, which means + that we can't change to pop_failure_jump. */ + if (!negate) + { + p[-3] = (unsigned char) pop_failure_jump; + DEBUG_PRINT1 (" No match => pop_failure_jump.\n"); + } + } +#endif /* not WCHAR */ + } +#ifndef WCHAR + else if ((re_opcode_t) *p2 == charset) + { + /* We win if the first character of the loop is not part + of the charset. */ + if ((re_opcode_t) p1[3] == exactn + && ! ((int) p2[1] * BYTEWIDTH > (int) p1[5] + && (p2[2 + p1[5] / BYTEWIDTH] + & (1 << (p1[5] % BYTEWIDTH))))) + { + p[-3] = (unsigned char) pop_failure_jump; + DEBUG_PRINT1 (" No match => pop_failure_jump.\n"); + } + + else if ((re_opcode_t) p1[3] == charset_not) + { + int idx; + /* We win if the charset_not inside the loop + lists every character listed in the charset after. */ + for (idx = 0; idx < (int) p2[1]; idx++) + if (! (p2[2 + idx] == 0 + || (idx < (int) p1[4] + && ((p2[2 + idx] & ~ p1[5 + idx]) == 0)))) + break; + + if (idx == p2[1]) + { + p[-3] = (unsigned char) pop_failure_jump; + DEBUG_PRINT1 (" No match => pop_failure_jump.\n"); + } + } + else if ((re_opcode_t) p1[3] == charset) + { + int idx; + /* We win if the charset inside the loop + has no overlap with the one after the loop. */ + for (idx = 0; + idx < (int) p2[1] && idx < (int) p1[4]; + idx++) + if ((p2[2 + idx] & p1[5 + idx]) != 0) + break; + + if (idx == p2[1] || idx == p1[4]) + { + p[-3] = (unsigned char) pop_failure_jump; + DEBUG_PRINT1 (" No match => pop_failure_jump.\n"); + } + } + } +#endif /* not WCHAR */ + } + p -= OFFSET_ADDRESS_SIZE; /* Point at relative address again. */ + if ((re_opcode_t) p[-1] != pop_failure_jump) + { + p[-1] = (UCHAR_T) jump; + DEBUG_PRINT1 (" Match => jump.\n"); + goto unconditional_jump; + } + /* Note fall through. */ + + + /* The end of a simple repeat has a pop_failure_jump back to + its matching on_failure_jump, where the latter will push a + failure point. The pop_failure_jump takes off failure + points put on by this pop_failure_jump's matching + on_failure_jump; we got through the pattern to here from the + matching on_failure_jump, so didn't fail. */ + case pop_failure_jump: + { + /* We need to pass separate storage for the lowest and + highest registers, even though we don't care about the + actual values. Otherwise, we will restore only one + register from the stack, since lowest will == highest in + `pop_failure_point'. */ + active_reg_t dummy_low_reg, dummy_high_reg; + UCHAR_T *pdummy ATTRIBUTE_UNUSED = NULL; + const CHAR_T *sdummy ATTRIBUTE_UNUSED = NULL; + + DEBUG_PRINT1 ("EXECUTING pop_failure_jump.\n"); + POP_FAILURE_POINT (sdummy, pdummy, + dummy_low_reg, dummy_high_reg, + reg_dummy, reg_dummy, reg_info_dummy); + } + /* Note fall through. */ + + unconditional_jump: +#ifdef _LIBC + DEBUG_PRINT2 ("\n%p: ", p); +#else + DEBUG_PRINT2 ("\n0x%x: ", p); +#endif + /* Note fall through. */ + + /* Unconditionally jump (without popping any failure points). */ + case jump: + EXTRACT_NUMBER_AND_INCR (mcnt, p); /* Get the amount to jump. */ + DEBUG_PRINT2 ("EXECUTING jump %d ", mcnt); + p += mcnt; /* Do the jump. */ +#ifdef _LIBC + DEBUG_PRINT2 ("(to %p).\n", p); +#else + DEBUG_PRINT2 ("(to 0x%x).\n", p); +#endif + break; + + + /* We need this opcode so we can detect where alternatives end + in `group_match_null_string_p' et al. */ + case jump_past_alt: + DEBUG_PRINT1 ("EXECUTING jump_past_alt.\n"); + goto unconditional_jump; + + + /* Normally, the on_failure_jump pushes a failure point, which + then gets popped at pop_failure_jump. We will end up at + pop_failure_jump, also, and with a pattern of, say, `a+', we + are skipping over the on_failure_jump, so we have to push + something meaningless for pop_failure_jump to pop. */ + case dummy_failure_jump: + DEBUG_PRINT1 ("EXECUTING dummy_failure_jump.\n"); + /* It doesn't matter what we push for the string here. What + the code at `fail' tests is the value for the pattern. */ + PUSH_FAILURE_POINT (NULL, NULL, -2); + goto unconditional_jump; + + + /* At the end of an alternative, we need to push a dummy failure + point in case we are followed by a `pop_failure_jump', because + we don't want the failure point for the alternative to be + popped. For example, matching `(a|ab)*' against `aab' + requires that we match the `ab' alternative. */ + case push_dummy_failure: + DEBUG_PRINT1 ("EXECUTING push_dummy_failure.\n"); + /* See comments just above at `dummy_failure_jump' about the + two zeroes. */ + PUSH_FAILURE_POINT (NULL, NULL, -2); + break; + + /* Have to succeed matching what follows at least n times. + After that, handle like `on_failure_jump'. */ + case succeed_n: + EXTRACT_NUMBER (mcnt, p + OFFSET_ADDRESS_SIZE); + DEBUG_PRINT2 ("EXECUTING succeed_n %d.\n", mcnt); + + assert (mcnt >= 0); + /* Originally, this is how many times we HAVE to succeed. */ + if (mcnt > 0) + { + mcnt--; + p += OFFSET_ADDRESS_SIZE; + STORE_NUMBER_AND_INCR (p, mcnt); +#ifdef _LIBC + DEBUG_PRINT3 (" Setting %p to %d.\n", p - OFFSET_ADDRESS_SIZE + , mcnt); +#else + DEBUG_PRINT3 (" Setting 0x%x to %d.\n", p - OFFSET_ADDRESS_SIZE + , mcnt); +#endif + } + else if (mcnt == 0) + { +#ifdef _LIBC + DEBUG_PRINT2 (" Setting two bytes from %p to no_op.\n", + p + OFFSET_ADDRESS_SIZE); +#else + DEBUG_PRINT2 (" Setting two bytes from 0x%x to no_op.\n", + p + OFFSET_ADDRESS_SIZE); +#endif /* _LIBC */ + +#ifdef WCHAR + p[1] = (UCHAR_T) no_op; +#else + p[2] = (UCHAR_T) no_op; + p[3] = (UCHAR_T) no_op; +#endif /* WCHAR */ + goto on_failure; + } + break; + + case jump_n: + EXTRACT_NUMBER (mcnt, p + OFFSET_ADDRESS_SIZE); + DEBUG_PRINT2 ("EXECUTING jump_n %d.\n", mcnt); + + /* Originally, this is how many times we CAN jump. */ + if (mcnt) + { + mcnt--; + STORE_NUMBER (p + OFFSET_ADDRESS_SIZE, mcnt); + +#ifdef _LIBC + DEBUG_PRINT3 (" Setting %p to %d.\n", p + OFFSET_ADDRESS_SIZE, + mcnt); +#else + DEBUG_PRINT3 (" Setting 0x%x to %d.\n", p + OFFSET_ADDRESS_SIZE, + mcnt); +#endif /* _LIBC */ + goto unconditional_jump; + } + /* If don't have to jump any more, skip over the rest of command. */ + else + p += 2 * OFFSET_ADDRESS_SIZE; + break; + + case set_number_at: + { + DEBUG_PRINT1 ("EXECUTING set_number_at.\n"); + + EXTRACT_NUMBER_AND_INCR (mcnt, p); + p1 = p + mcnt; + EXTRACT_NUMBER_AND_INCR (mcnt, p); +#ifdef _LIBC + DEBUG_PRINT3 (" Setting %p to %d.\n", p1, mcnt); +#else + DEBUG_PRINT3 (" Setting 0x%x to %d.\n", p1, mcnt); +#endif + STORE_NUMBER (p1, mcnt); + break; + } + +#if 0 + /* The DEC Alpha C compiler 3.x generates incorrect code for the + test WORDCHAR_P (d - 1) != WORDCHAR_P (d) in the expansion of + AT_WORD_BOUNDARY, so this code is disabled. Expanding the + macro and introducing temporary variables works around the bug. */ + + case wordbound: + DEBUG_PRINT1 ("EXECUTING wordbound.\n"); + if (AT_WORD_BOUNDARY (d)) + break; + goto fail; + + case notwordbound: + DEBUG_PRINT1 ("EXECUTING notwordbound.\n"); + if (AT_WORD_BOUNDARY (d)) + goto fail; + break; +#else + case wordbound: + { + boolean prevchar, thischar; + + DEBUG_PRINT1 ("EXECUTING wordbound.\n"); + if (AT_STRINGS_BEG (d) || AT_STRINGS_END (d)) + break; + + prevchar = WORDCHAR_P (d - 1); + thischar = WORDCHAR_P (d); + if (prevchar != thischar) + break; + goto fail; + } + + case notwordbound: + { + boolean prevchar, thischar; + + DEBUG_PRINT1 ("EXECUTING notwordbound.\n"); + if (AT_STRINGS_BEG (d) || AT_STRINGS_END (d)) + goto fail; + + prevchar = WORDCHAR_P (d - 1); + thischar = WORDCHAR_P (d); + if (prevchar != thischar) + goto fail; + break; + } +#endif + + case wordbeg: + DEBUG_PRINT1 ("EXECUTING wordbeg.\n"); + if (!AT_STRINGS_END (d) && WORDCHAR_P (d) + && (AT_STRINGS_BEG (d) || !WORDCHAR_P (d - 1))) + break; + goto fail; + + case wordend: + DEBUG_PRINT1 ("EXECUTING wordend.\n"); + if (!AT_STRINGS_BEG (d) && WORDCHAR_P (d - 1) + && (AT_STRINGS_END (d) || !WORDCHAR_P (d))) + break; + goto fail; + +#ifdef emacs + case before_dot: + DEBUG_PRINT1 ("EXECUTING before_dot.\n"); + if (PTR_CHAR_POS ((unsigned char *) d) >= point) + goto fail; + break; + + case at_dot: + DEBUG_PRINT1 ("EXECUTING at_dot.\n"); + if (PTR_CHAR_POS ((unsigned char *) d) != point) + goto fail; + break; + + case after_dot: + DEBUG_PRINT1 ("EXECUTING after_dot.\n"); + if (PTR_CHAR_POS ((unsigned char *) d) <= point) + goto fail; + break; + + case syntaxspec: + DEBUG_PRINT2 ("EXECUTING syntaxspec %d.\n", mcnt); + mcnt = *p++; + goto matchsyntax; + + case wordchar: + DEBUG_PRINT1 ("EXECUTING Emacs wordchar.\n"); + mcnt = (int) Sword; + matchsyntax: + PREFETCH (); + /* Can't use *d++ here; SYNTAX may be an unsafe macro. */ + d++; + if (SYNTAX (d[-1]) != (enum syntaxcode) mcnt) + goto fail; + SET_REGS_MATCHED (); + break; + + case notsyntaxspec: + DEBUG_PRINT2 ("EXECUTING notsyntaxspec %d.\n", mcnt); + mcnt = *p++; + goto matchnotsyntax; + + case notwordchar: + DEBUG_PRINT1 ("EXECUTING Emacs notwordchar.\n"); + mcnt = (int) Sword; + matchnotsyntax: + PREFETCH (); + /* Can't use *d++ here; SYNTAX may be an unsafe macro. */ + d++; + if (SYNTAX (d[-1]) == (enum syntaxcode) mcnt) + goto fail; + SET_REGS_MATCHED (); + break; + +#else /* not emacs */ + case wordchar: + DEBUG_PRINT1 ("EXECUTING non-Emacs wordchar.\n"); + PREFETCH (); + if (!WORDCHAR_P (d)) + goto fail; + SET_REGS_MATCHED (); + d++; + break; + + case notwordchar: + DEBUG_PRINT1 ("EXECUTING non-Emacs notwordchar.\n"); + PREFETCH (); + if (WORDCHAR_P (d)) + goto fail; + SET_REGS_MATCHED (); + d++; + break; +#endif /* not emacs */ + + default: + abort (); + } + continue; /* Successfully executed one pattern command; keep going. */ + + + /* We goto here if a matching operation fails. */ + fail: + if (!FAIL_STACK_EMPTY ()) + { /* A restart point is known. Restore to that state. */ + DEBUG_PRINT1 ("\nFAIL:\n"); + POP_FAILURE_POINT (d, p, + lowest_active_reg, highest_active_reg, + regstart, regend, reg_info); + + /* If this failure point is a dummy, try the next one. */ + if (!p) + goto fail; + + /* If we failed to the end of the pattern, don't examine *p. */ + assert (p <= pend); + if (p < pend) + { + boolean is_a_jump_n = false; + + /* If failed to a backwards jump that's part of a repetition + loop, need to pop this failure point and use the next one. */ + switch ((re_opcode_t) *p) + { + case jump_n: + is_a_jump_n = true; + case maybe_pop_jump: + case pop_failure_jump: + case jump: + p1 = p + 1; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + p1 += mcnt; + + if ((is_a_jump_n && (re_opcode_t) *p1 == succeed_n) + || (!is_a_jump_n + && (re_opcode_t) *p1 == on_failure_jump)) + goto fail; + break; + default: + /* do nothing */ ; + } + } + + if (d >= string1 && d <= end1) + dend = end_match_1; + } + else + break; /* Matching at this starting point really fails. */ + } /* for (;;) */ + + if (best_regs_set) + goto restore_best_regs; + + FREE_VARIABLES (); + + return -1; /* Failure to match. */ +} /* re_match_2 */ + +/* Subroutine definitions for re_match_2. */ + + +/* We are passed P pointing to a register number after a start_memory. + + Return true if the pattern up to the corresponding stop_memory can + match the empty string, and false otherwise. + + If we find the matching stop_memory, sets P to point to one past its number. + Otherwise, sets P to an undefined byte less than or equal to END. + + We don't handle duplicates properly (yet). */ + +static boolean +PREFIX(group_match_null_string_p) (UCHAR_T **p, UCHAR_T *end, + PREFIX(register_info_type) *reg_info) +{ + int mcnt; + /* Point to after the args to the start_memory. */ + UCHAR_T *p1 = *p + 2; + + while (p1 < end) + { + /* Skip over opcodes that can match nothing, and return true or + false, as appropriate, when we get to one that can't, or to the + matching stop_memory. */ + + switch ((re_opcode_t) *p1) + { + /* Could be either a loop or a series of alternatives. */ + case on_failure_jump: + p1++; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + + /* If the next operation is not a jump backwards in the + pattern. */ + + if (mcnt >= 0) + { + /* Go through the on_failure_jumps of the alternatives, + seeing if any of the alternatives cannot match nothing. + The last alternative starts with only a jump, + whereas the rest start with on_failure_jump and end + with a jump, e.g., here is the pattern for `a|b|c': + + /on_failure_jump/0/6/exactn/1/a/jump_past_alt/0/6 + /on_failure_jump/0/6/exactn/1/b/jump_past_alt/0/3 + /exactn/1/c + + So, we have to first go through the first (n-1) + alternatives and then deal with the last one separately. */ + + + /* Deal with the first (n-1) alternatives, which start + with an on_failure_jump (see above) that jumps to right + past a jump_past_alt. */ + + while ((re_opcode_t) p1[mcnt-(1+OFFSET_ADDRESS_SIZE)] == + jump_past_alt) + { + /* `mcnt' holds how many bytes long the alternative + is, including the ending `jump_past_alt' and + its number. */ + + if (!PREFIX(alt_match_null_string_p) (p1, p1 + mcnt - + (1 + OFFSET_ADDRESS_SIZE), + reg_info)) + return false; + + /* Move to right after this alternative, including the + jump_past_alt. */ + p1 += mcnt; + + /* Break if it's the beginning of an n-th alternative + that doesn't begin with an on_failure_jump. */ + if ((re_opcode_t) *p1 != on_failure_jump) + break; + + /* Still have to check that it's not an n-th + alternative that starts with an on_failure_jump. */ + p1++; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + if ((re_opcode_t) p1[mcnt-(1+OFFSET_ADDRESS_SIZE)] != + jump_past_alt) + { + /* Get to the beginning of the n-th alternative. */ + p1 -= 1 + OFFSET_ADDRESS_SIZE; + break; + } + } + + /* Deal with the last alternative: go back and get number + of the `jump_past_alt' just before it. `mcnt' contains + the length of the alternative. */ + EXTRACT_NUMBER (mcnt, p1 - OFFSET_ADDRESS_SIZE); + + if (!PREFIX(alt_match_null_string_p) (p1, p1 + mcnt, reg_info)) + return false; + + p1 += mcnt; /* Get past the n-th alternative. */ + } /* if mcnt > 0 */ + break; + + + case stop_memory: + assert (p1[1] == **p); + *p = p1 + 2; + return true; + + + default: + if (!PREFIX(common_op_match_null_string_p) (&p1, end, reg_info)) + return false; + } + } /* while p1 < end */ + + return false; +} /* group_match_null_string_p */ + + +/* Similar to group_match_null_string_p, but doesn't deal with alternatives: + It expects P to be the first byte of a single alternative and END one + byte past the last. The alternative can contain groups. */ + +static boolean +PREFIX(alt_match_null_string_p) (UCHAR_T *p, UCHAR_T *end, + PREFIX(register_info_type) *reg_info) +{ + int mcnt; + UCHAR_T *p1 = p; + + while (p1 < end) + { + /* Skip over opcodes that can match nothing, and break when we get + to one that can't. */ + + switch ((re_opcode_t) *p1) + { + /* It's a loop. */ + case on_failure_jump: + p1++; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + p1 += mcnt; + break; + + default: + if (!PREFIX(common_op_match_null_string_p) (&p1, end, reg_info)) + return false; + } + } /* while p1 < end */ + + return true; +} /* alt_match_null_string_p */ + + +/* Deals with the ops common to group_match_null_string_p and + alt_match_null_string_p. + + Sets P to one after the op and its arguments, if any. */ + +static boolean +PREFIX(common_op_match_null_string_p) (UCHAR_T **p, UCHAR_T *end, + PREFIX(register_info_type) *reg_info) +{ + int mcnt; + boolean ret; + int reg_no; + UCHAR_T *p1 = *p; + + switch ((re_opcode_t) *p1++) + { + case no_op: + case begline: + case endline: + case begbuf: + case endbuf: + case wordbeg: + case wordend: + case wordbound: + case notwordbound: +#ifdef emacs + case before_dot: + case at_dot: + case after_dot: +#endif + break; + + case start_memory: + reg_no = *p1; + assert (reg_no > 0 && reg_no <= MAX_REGNUM); + ret = PREFIX(group_match_null_string_p) (&p1, end, reg_info); + + /* Have to set this here in case we're checking a group which + contains a group and a back reference to it. */ + + if (REG_MATCH_NULL_STRING_P (reg_info[reg_no]) == MATCH_NULL_UNSET_VALUE) + REG_MATCH_NULL_STRING_P (reg_info[reg_no]) = ret; + + if (!ret) + return false; + break; + + /* If this is an optimized succeed_n for zero times, make the jump. */ + case jump: + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + if (mcnt >= 0) + p1 += mcnt; + else + return false; + break; + + case succeed_n: + /* Get to the number of times to succeed. */ + p1 += OFFSET_ADDRESS_SIZE; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + + if (mcnt == 0) + { + p1 -= 2 * OFFSET_ADDRESS_SIZE; + EXTRACT_NUMBER_AND_INCR (mcnt, p1); + p1 += mcnt; + } + else + return false; + break; + + case duplicate: + if (!REG_MATCH_NULL_STRING_P (reg_info[*p1])) + return false; + break; + + case set_number_at: + p1 += 2 * OFFSET_ADDRESS_SIZE; + + default: + /* All other opcodes mean we cannot match the empty string. */ + return false; + } + + *p = p1; + return true; +} /* common_op_match_null_string_p */ + + +/* Return zero if TRANSLATE[S1] and TRANSLATE[S2] are identical for LEN + bytes; nonzero otherwise. */ + +static int +PREFIX(bcmp_translate) (const CHAR_T *s1, const CHAR_T *s2, register int len, + RE_TRANSLATE_TYPE translate) +{ + register const UCHAR_T *p1 = (const UCHAR_T *) s1; + register const UCHAR_T *p2 = (const UCHAR_T *) s2; + while (len) + { +#ifdef WCHAR + if (((*p1<=0xff)?translate[*p1++]:*p1++) + != ((*p2<=0xff)?translate[*p2++]:*p2++)) + return 1; +#else /* BYTE */ + if (translate[*p1++] != translate[*p2++]) return 1; +#endif /* WCHAR */ + len--; + } + return 0; +} + + +#else /* not INSIDE_RECURSION */ + +/* Entry points for GNU code. */ + +/* re_compile_pattern is the GNU regular expression compiler: it + compiles PATTERN (of length SIZE) and puts the result in BUFP. + Returns 0 if the pattern was valid, otherwise an error string. + + Assumes the `allocated' (and perhaps `buffer') and `translate' fields + are set in BUFP on entry. + + We call regex_compile to do the actual compilation. */ + +const char * +re_compile_pattern (const char *pattern, size_t length, + struct re_pattern_buffer *bufp) +{ + reg_errcode_t ret; + + /* GNU code is written to assume at least RE_NREGS registers will be set + (and at least one extra will be -1). */ + bufp->regs_allocated = REGS_UNALLOCATED; + + /* And GNU code determines whether or not to get register information + by passing null for the REGS argument to re_match, etc., not by + setting no_sub. */ + bufp->no_sub = 0; + + /* Match anchors at newline. */ + bufp->newline_anchor = 1; + +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + ret = wcs_regex_compile (pattern, length, re_syntax_options, bufp); + else +# endif + ret = byte_regex_compile (pattern, length, re_syntax_options, bufp); + + if (!ret) + return NULL; + return gettext (re_error_msgid[(int) ret]); +} +#ifdef _LIBC +weak_alias (__re_compile_pattern, re_compile_pattern) +#endif + +/* Entry points compatible with 4.2 BSD regex library. We don't define + them unless specifically requested. */ + +#if defined _REGEX_RE_COMP || defined _LIBC + +/* BSD has one and only one pattern buffer. */ +static struct re_pattern_buffer re_comp_buf; + +char * +#ifdef _LIBC +/* Make these definitions weak in libc, so POSIX programs can redefine + these names if they don't use our functions, and still use + regcomp/regexec below without link errors. */ +weak_function +#endif +re_comp (const char *s) +{ + reg_errcode_t ret; + + if (!s) + { + if (!re_comp_buf.buffer) + return (char *) gettext ("No previous regular expression"); + return 0; + } + + if (!re_comp_buf.buffer) + { + re_comp_buf.buffer = (unsigned char *) malloc (200); + if (re_comp_buf.buffer == NULL) + return (char *) gettext (re_error_msgid[(int) REG_ESPACE]); + re_comp_buf.allocated = 200; + + re_comp_buf.fastmap = (char *) malloc (1 << BYTEWIDTH); + if (re_comp_buf.fastmap == NULL) + return (char *) gettext (re_error_msgid[(int) REG_ESPACE]); + } + + /* Since `re_exec' always passes NULL for the `regs' argument, we + don't need to initialize the pattern buffer fields which affect it. */ + + /* Match anchors at newlines. */ + re_comp_buf.newline_anchor = 1; + +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + ret = wcs_regex_compile (s, strlen (s), re_syntax_options, &re_comp_buf); + else +# endif + ret = byte_regex_compile (s, strlen (s), re_syntax_options, &re_comp_buf); + + if (!ret) + return NULL; + + /* Yes, we're discarding `const' here if !HAVE_LIBINTL. */ + return (char *) gettext (re_error_msgid[(int) ret]); +} + + +int +#ifdef _LIBC +weak_function +#endif +re_exec (const char *s) +{ + const int len = strlen (s); + return + 0 <= re_search (&re_comp_buf, s, len, 0, len, (struct re_registers *) 0); +} + +#endif /* _REGEX_RE_COMP */ + +/* POSIX.2 functions. Don't define these for Emacs. */ + +#ifndef emacs + +/* regcomp takes a regular expression as a string and compiles it. + + PREG is a regex_t *. We do not expect any fields to be initialized, + since POSIX says we shouldn't. Thus, we set + + `buffer' to the compiled pattern; + `used' to the length of the compiled pattern; + `syntax' to RE_SYNTAX_POSIX_EXTENDED if the + REG_EXTENDED bit in CFLAGS is set; otherwise, to + RE_SYNTAX_POSIX_BASIC; + `newline_anchor' to REG_NEWLINE being set in CFLAGS; + `fastmap' to an allocated space for the fastmap; + `fastmap_accurate' to zero; + `re_nsub' to the number of subexpressions in PATTERN. + + PATTERN is the address of the pattern string. + + CFLAGS is a series of bits which affect compilation. + + If REG_EXTENDED is set, we use POSIX extended syntax; otherwise, we + use POSIX basic syntax. + + If REG_NEWLINE is set, then . and [^...] don't match newline. + Also, regexec will try a match beginning after every newline. + + If REG_ICASE is set, then we considers upper- and lowercase + versions of letters to be equivalent when matching. + + If REG_NOSUB is set, then when PREG is passed to regexec, that + routine will report only success or failure, and nothing about the + registers. + + It returns 0 if it succeeds, nonzero if it doesn't. (See regex.h for + the return codes and their meanings.) */ + +int +regcomp (regex_t *preg, const char *pattern, int cflags) +{ + reg_errcode_t ret; + reg_syntax_t syntax + = (cflags & REG_EXTENDED) ? + RE_SYNTAX_POSIX_EXTENDED : RE_SYNTAX_POSIX_BASIC; + + /* regex_compile will allocate the space for the compiled pattern. */ + preg->buffer = 0; + preg->allocated = 0; + preg->used = 0; + + /* Try to allocate space for the fastmap. */ + preg->fastmap = (char *) malloc (1 << BYTEWIDTH); + + if (cflags & REG_ICASE) + { + int i; + + preg->translate + = (RE_TRANSLATE_TYPE) malloc (CHAR_SET_SIZE + * sizeof (*(RE_TRANSLATE_TYPE)0)); + if (preg->translate == NULL) + return (int) REG_ESPACE; + + /* Map uppercase characters to corresponding lowercase ones. */ + for (i = 0; i < CHAR_SET_SIZE; i++) + preg->translate[i] = ISUPPER (i) ? TOLOWER (i) : i; + } + else + preg->translate = NULL; + + /* If REG_NEWLINE is set, newlines are treated differently. */ + if (cflags & REG_NEWLINE) + { /* REG_NEWLINE implies neither . nor [^...] match newline. */ + syntax &= ~RE_DOT_NEWLINE; + syntax |= RE_HAT_LISTS_NOT_NEWLINE; + /* It also changes the matching behavior. */ + preg->newline_anchor = 1; + } + else + preg->newline_anchor = 0; + + preg->no_sub = !!(cflags & REG_NOSUB); + + /* POSIX says a null character in the pattern terminates it, so we + can use strlen here in compiling the pattern. */ +# ifdef MBS_SUPPORT + if (MB_CUR_MAX != 1) + ret = wcs_regex_compile (pattern, strlen (pattern), syntax, preg); + else +# endif + ret = byte_regex_compile (pattern, strlen (pattern), syntax, preg); + + /* POSIX doesn't distinguish between an unmatched open-group and an + unmatched close-group: both are REG_EPAREN. */ + if (ret == REG_ERPAREN) ret = REG_EPAREN; + + if (ret == REG_NOERROR && preg->fastmap) + { + /* Compute the fastmap now, since regexec cannot modify the pattern + buffer. */ + if (re_compile_fastmap (preg) == -2) + { + /* Some error occurred while computing the fastmap, just forget + about it. */ + free (preg->fastmap); + preg->fastmap = NULL; + } + } + + return (int) ret; +} +#ifdef _LIBC +weak_alias (__regcomp, regcomp) +#endif + + +/* regexec searches for a given pattern, specified by PREG, in the + string STRING. + + If NMATCH is zero or REG_NOSUB was set in the cflags argument to + `regcomp', we ignore PMATCH. Otherwise, we assume PMATCH has at + least NMATCH elements, and we set them to the offsets of the + corresponding matched substrings. + + EFLAGS specifies `execution flags' which affect matching: if + REG_NOTBOL is set, then ^ does not match at the beginning of the + string; if REG_NOTEOL is set, then $ does not match at the end. + + We return 0 if we find a match and REG_NOMATCH if not. */ + +int +regexec (const regex_t *preg, const char *string, size_t nmatch, + regmatch_t pmatch[], int eflags) +{ + int ret; + struct re_registers regs; + regex_t private_preg; + int len = strlen (string); + boolean want_reg_info = !preg->no_sub && nmatch > 0; + + private_preg = *preg; + + private_preg.not_bol = !!(eflags & REG_NOTBOL); + private_preg.not_eol = !!(eflags & REG_NOTEOL); + + /* The user has told us exactly how many registers to return + information about, via `nmatch'. We have to pass that on to the + matching routines. */ + private_preg.regs_allocated = REGS_FIXED; + + if (want_reg_info) + { + regs.num_regs = nmatch; + regs.start = TALLOC (nmatch * 2, regoff_t); + if (regs.start == NULL) + return (int) REG_NOMATCH; + regs.end = regs.start + nmatch; + } + + /* Perform the searching operation. */ + ret = re_search (&private_preg, string, len, + /* start: */ 0, /* range: */ len, + want_reg_info ? ®s : (struct re_registers *) 0); + + /* Copy the register information to the POSIX structure. */ + if (want_reg_info) + { + if (ret >= 0) + { + unsigned r; + + for (r = 0; r < nmatch; r++) + { + pmatch[r].rm_so = regs.start[r]; + pmatch[r].rm_eo = regs.end[r]; + } + } + + /* If we needed the temporary register info, free the space now. */ + free (regs.start); + } + + /* We want zero return to mean success, unlike `re_search'. */ + return ret >= 0 ? (int) REG_NOERROR : (int) REG_NOMATCH; +} +#ifdef _LIBC +weak_alias (__regexec, regexec) +#endif + + +/* Returns a message corresponding to an error code, ERRCODE, returned + from either regcomp or regexec. We don't use PREG here. */ + +size_t +regerror (int errcode, const regex_t *preg ATTRIBUTE_UNUSED, + char *errbuf, size_t errbuf_size) +{ + const char *msg; + size_t msg_size; + + if (errcode < 0 + || errcode >= (int) (sizeof (re_error_msgid) + / sizeof (re_error_msgid[0]))) + /* Only error codes returned by the rest of the code should be passed + to this routine. If we are given anything else, or if other regex + code generates an invalid error code, then the program has a bug. + Dump core so we can fix it. */ + abort (); + + msg = gettext (re_error_msgid[errcode]); + + msg_size = strlen (msg) + 1; /* Includes the null. */ + + if (errbuf_size != 0) + { + if (msg_size > errbuf_size) + { +#if defined HAVE_MEMPCPY || defined _LIBC + *((char *) mempcpy (errbuf, msg, errbuf_size - 1)) = '\0'; +#else + memcpy (errbuf, msg, errbuf_size - 1); + errbuf[errbuf_size - 1] = 0; +#endif + } + else + memcpy (errbuf, msg, msg_size); + } + + return msg_size; +} +#ifdef _LIBC +weak_alias (__regerror, regerror) +#endif + + +/* Free dynamically allocated space used by PREG. */ + +void +regfree (regex_t *preg) +{ + if (preg->buffer != NULL) + free (preg->buffer); + preg->buffer = NULL; + + preg->allocated = 0; + preg->used = 0; + + if (preg->fastmap != NULL) + free (preg->fastmap); + preg->fastmap = NULL; + preg->fastmap_accurate = 0; + + if (preg->translate != NULL) + free (preg->translate); + preg->translate = NULL; +} +#ifdef _LIBC +weak_alias (__regfree, regfree) +#endif + +#endif /* not emacs */ + +#endif /* not INSIDE_RECURSION */ + + +#undef STORE_NUMBER +#undef STORE_NUMBER_AND_INCR +#undef EXTRACT_NUMBER +#undef EXTRACT_NUMBER_AND_INCR + +#undef DEBUG_PRINT_COMPILED_PATTERN +#undef DEBUG_PRINT_DOUBLE_STRING + +#undef INIT_FAIL_STACK +#undef RESET_FAIL_STACK +#undef DOUBLE_FAIL_STACK +#undef PUSH_PATTERN_OP +#undef PUSH_FAILURE_POINTER +#undef PUSH_FAILURE_INT +#undef PUSH_FAILURE_ELT +#undef POP_FAILURE_POINTER +#undef POP_FAILURE_INT +#undef POP_FAILURE_ELT +#undef DEBUG_PUSH +#undef DEBUG_POP +#undef PUSH_FAILURE_POINT +#undef POP_FAILURE_POINT + +#undef REG_UNSET_VALUE +#undef REG_UNSET + +#undef PATFETCH +#undef PATFETCH_RAW +#undef PATUNFETCH +#undef TRANSLATE + +#undef INIT_BUF_SIZE +#undef GET_BUFFER_SPACE +#undef BUF_PUSH +#undef BUF_PUSH_2 +#undef BUF_PUSH_3 +#undef STORE_JUMP +#undef STORE_JUMP2 +#undef INSERT_JUMP +#undef INSERT_JUMP2 +#undef EXTEND_BUFFER +#undef GET_UNSIGNED_NUMBER +#undef FREE_STACK_RETURN + +# undef POINTER_TO_OFFSET +# undef MATCHING_IN_FRST_STRING +# undef PREFETCH +# undef AT_STRINGS_BEG +# undef AT_STRINGS_END +# undef WORDCHAR_P +# undef FREE_VAR +# undef FREE_VARIABLES +# undef NO_HIGHEST_ACTIVE_REG +# undef NO_LOWEST_ACTIVE_REG + +# undef CHAR_T +# undef UCHAR_T +# undef COMPILED_BUFFER_VAR +# undef OFFSET_ADDRESS_SIZE +# undef CHAR_CLASS_SIZE +# undef PREFIX +# undef ARG_PREFIX +# undef PUT_CHAR +# undef BYTE +# undef WCHAR + +# define DEFINED_ONCE diff --git a/external/gpl3/gdb/dist/libiberty/rename.c b/external/gpl3/gdb/dist/libiberty/rename.c new file mode 100644 index 000000000000..ad342ffca65c --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/rename.c @@ -0,0 +1,36 @@ +/* rename -- rename a file + This function is in the public domain. */ + +/* + +@deftypefn Supplemental int rename (const char *@var{old}, const char *@var{new}) + +Renames a file from @var{old} to @var{new}. If @var{new} already +exists, it is removed. + +@end deftypefn + +*/ + +#include "ansidecl.h" +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +int +rename (const char *zfrom, const char *zto) +{ + if (link (zfrom, zto) < 0) + { + if (errno != EEXIST) + return -1; + if (unlink (zto) < 0 + || link (zfrom, zto) < 0) + return -1; + } + return unlink (zfrom); +} diff --git a/external/gpl3/gdb/dist/libiberty/rindex.c b/external/gpl3/gdb/dist/libiberty/rindex.c new file mode 100644 index 000000000000..194ef9fad786 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/rindex.c @@ -0,0 +1,21 @@ +/* Stub implementation of (obsolete) rindex(). */ + +/* + +@deftypefn Supplemental char* rindex (const char *@var{s}, int @var{c}) + +Returns a pointer to the last occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. The use of @code{rindex} is +deprecated in new programs in favor of @code{strrchr}. + +@end deftypefn + +*/ + +extern char *strrchr (const char *, int); + +char * +rindex (const char *s, int c) +{ + return strrchr (s, c); +} diff --git a/external/gpl3/gdb/dist/libiberty/safe-ctype.c b/external/gpl3/gdb/dist/libiberty/safe-ctype.c new file mode 100644 index 000000000000..0972b4b354fa --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/safe-ctype.c @@ -0,0 +1,255 @@ +/* replacement macros. + + Copyright (C) 2000, 2001, 2002, 2003, 2004, + 2005 Free Software Foundation, Inc. + Contributed by Zack Weinberg . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@defvr Extension HOST_CHARSET +This macro indicates the basic character set and encoding used by the +host: more precisely, the encoding used for character constants in +preprocessor @samp{#if} statements (the C "execution character set"). +It is defined by @file{safe-ctype.h}, and will be an integer constant +with one of the following values: + +@ftable @code +@item HOST_CHARSET_UNKNOWN +The host character set is unknown - that is, not one of the next two +possibilities. + +@item HOST_CHARSET_ASCII +The host character set is ASCII. + +@item HOST_CHARSET_EBCDIC +The host character set is some variant of EBCDIC. (Only one of the +nineteen EBCDIC varying characters is tested; exercise caution.) +@end ftable +@end defvr + +@deffn Extension ISALPHA (@var{c}) +@deffnx Extension ISALNUM (@var{c}) +@deffnx Extension ISBLANK (@var{c}) +@deffnx Extension ISCNTRL (@var{c}) +@deffnx Extension ISDIGIT (@var{c}) +@deffnx Extension ISGRAPH (@var{c}) +@deffnx Extension ISLOWER (@var{c}) +@deffnx Extension ISPRINT (@var{c}) +@deffnx Extension ISPUNCT (@var{c}) +@deffnx Extension ISSPACE (@var{c}) +@deffnx Extension ISUPPER (@var{c}) +@deffnx Extension ISXDIGIT (@var{c}) + +These twelve macros are defined by @file{safe-ctype.h}. Each has the +same meaning as the corresponding macro (with name in lowercase) +defined by the standard header @file{ctype.h}. For example, +@code{ISALPHA} returns true for alphabetic characters and false for +others. However, there are two differences between these macros and +those provided by @file{ctype.h}: + +@itemize @bullet +@item These macros are guaranteed to have well-defined behavior for all +values representable by @code{signed char} and @code{unsigned char}, and +for @code{EOF}. + +@item These macros ignore the current locale; they are true for these +fixed sets of characters: +@multitable {@code{XDIGIT}} {yada yada yada yada yada yada yada yada} +@item @code{ALPHA} @tab @kbd{A-Za-z} +@item @code{ALNUM} @tab @kbd{A-Za-z0-9} +@item @code{BLANK} @tab @kbd{space tab} +@item @code{CNTRL} @tab @code{!PRINT} +@item @code{DIGIT} @tab @kbd{0-9} +@item @code{GRAPH} @tab @code{ALNUM || PUNCT} +@item @code{LOWER} @tab @kbd{a-z} +@item @code{PRINT} @tab @code{GRAPH ||} @kbd{space} +@item @code{PUNCT} @tab @kbd{`~!@@#$%^&*()_-=+[@{]@}\|;:'",<.>/?} +@item @code{SPACE} @tab @kbd{space tab \n \r \f \v} +@item @code{UPPER} @tab @kbd{A-Z} +@item @code{XDIGIT} @tab @kbd{0-9A-Fa-f} +@end multitable + +Note that, if the host character set is ASCII or a superset thereof, +all these macros will return false for all values of @code{char} outside +the range of 7-bit ASCII. In particular, both ISPRINT and ISCNTRL return +false for characters with numeric values from 128 to 255. +@end itemize +@end deffn + +@deffn Extension ISIDNUM (@var{c}) +@deffnx Extension ISIDST (@var{c}) +@deffnx Extension IS_VSPACE (@var{c}) +@deffnx Extension IS_NVSPACE (@var{c}) +@deffnx Extension IS_SPACE_OR_NUL (@var{c}) +@deffnx Extension IS_ISOBASIC (@var{c}) +These six macros are defined by @file{safe-ctype.h} and provide +additional character classes which are useful when doing lexical +analysis of C or similar languages. They are true for the following +sets of characters: + +@multitable {@code{SPACE_OR_NUL}} {yada yada yada yada yada yada yada yada} +@item @code{IDNUM} @tab @kbd{A-Za-z0-9_} +@item @code{IDST} @tab @kbd{A-Za-z_} +@item @code{VSPACE} @tab @kbd{\r \n} +@item @code{NVSPACE} @tab @kbd{space tab \f \v \0} +@item @code{SPACE_OR_NUL} @tab @code{VSPACE || NVSPACE} +@item @code{ISOBASIC} @tab @code{VSPACE || NVSPACE || PRINT} +@end multitable +@end deffn + +*/ + +#include "ansidecl.h" +#include +#include /* for EOF */ + +#if EOF != -1 + #error " requires EOF == -1" +#endif + +/* Shorthand */ +#define bl _sch_isblank +#define cn _sch_iscntrl +#define di _sch_isdigit +#define is _sch_isidst +#define lo _sch_islower +#define nv _sch_isnvsp +#define pn _sch_ispunct +#define pr _sch_isprint +#define sp _sch_isspace +#define up _sch_isupper +#define vs _sch_isvsp +#define xd _sch_isxdigit + +/* Masks. */ +#define L (const unsigned short) (lo|is |pr) /* lower case letter */ +#define XL (const unsigned short) (lo|is|xd|pr) /* lowercase hex digit */ +#define U (const unsigned short) (up|is |pr) /* upper case letter */ +#define XU (const unsigned short) (up|is|xd|pr) /* uppercase hex digit */ +#define D (const unsigned short) (di |xd|pr) /* decimal digit */ +#define P (const unsigned short) (pn |pr) /* punctuation */ +#define _ (const unsigned short) (pn|is |pr) /* underscore */ + +#define C (const unsigned short) ( cn) /* control character */ +#define Z (const unsigned short) (nv |cn) /* NUL */ +#define M (const unsigned short) (nv|sp |cn) /* cursor movement: \f \v */ +#define V (const unsigned short) (vs|sp |cn) /* vertical space: \r \n */ +#define T (const unsigned short) (nv|sp|bl|cn) /* tab */ +#define S (const unsigned short) (nv|sp|bl|pr) /* space */ + +/* Are we ASCII? */ +#if HOST_CHARSET == HOST_CHARSET_ASCII + +const unsigned short _sch_istable[256] = +{ + Z, C, C, C, C, C, C, C, /* NUL SOH STX ETX EOT ENQ ACK BEL */ + C, T, V, M, M, V, C, C, /* BS HT LF VT FF CR SO SI */ + C, C, C, C, C, C, C, C, /* DLE DC1 DC2 DC3 DC4 NAK SYN ETB */ + C, C, C, C, C, C, C, C, /* CAN EM SUB ESC FS GS RS US */ + S, P, P, P, P, P, P, P, /* SP ! " # $ % & ' */ + P, P, P, P, P, P, P, P, /* ( ) * + , - . / */ + D, D, D, D, D, D, D, D, /* 0 1 2 3 4 5 6 7 */ + D, D, P, P, P, P, P, P, /* 8 9 : ; < = > ? */ + P, XU, XU, XU, XU, XU, XU, U, /* @ A B C D E F G */ + U, U, U, U, U, U, U, U, /* H I J K L M N O */ + U, U, U, U, U, U, U, U, /* P Q R S T U V W */ + U, U, U, P, P, P, P, _, /* X Y Z [ \ ] ^ _ */ + P, XL, XL, XL, XL, XL, XL, L, /* ` a b c d e f g */ + L, L, L, L, L, L, L, L, /* h i j k l m n o */ + L, L, L, L, L, L, L, L, /* p q r s t u v w */ + L, L, L, P, P, P, P, C, /* x y z { | } ~ DEL */ + + /* high half of unsigned char is locale-specific, so all tests are + false in "C" locale */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +}; + +const unsigned char _sch_tolower[256] = +{ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, + + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', + + 91, 92, 93, 94, 95, 96, + + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', + + 123,124,125,126,127, + + 128,129,130,131, 132,133,134,135, 136,137,138,139, 140,141,142,143, + 144,145,146,147, 148,149,150,151, 152,153,154,155, 156,157,158,159, + 160,161,162,163, 164,165,166,167, 168,169,170,171, 172,173,174,175, + 176,177,178,179, 180,181,182,183, 184,185,186,187, 188,189,190,191, + + 192,193,194,195, 196,197,198,199, 200,201,202,203, 204,205,206,207, + 208,209,210,211, 212,213,214,215, 216,217,218,219, 220,221,222,223, + 224,225,226,227, 228,229,230,231, 232,233,234,235, 236,237,238,239, + 240,241,242,243, 244,245,246,247, 248,249,250,251, 252,253,254,255, +}; + +const unsigned char _sch_toupper[256] = +{ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 64, + + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', + + 91, 92, 93, 94, 95, 96, + + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', + + 123,124,125,126,127, + + 128,129,130,131, 132,133,134,135, 136,137,138,139, 140,141,142,143, + 144,145,146,147, 148,149,150,151, 152,153,154,155, 156,157,158,159, + 160,161,162,163, 164,165,166,167, 168,169,170,171, 172,173,174,175, + 176,177,178,179, 180,181,182,183, 184,185,186,187, 188,189,190,191, + + 192,193,194,195, 196,197,198,199, 200,201,202,203, 204,205,206,207, + 208,209,210,211, 212,213,214,215, 216,217,218,219, 220,221,222,223, + 224,225,226,227, 228,229,230,231, 232,233,234,235, 236,237,238,239, + 240,241,242,243, 244,245,246,247, 248,249,250,251, 252,253,254,255, +}; + +#else +# if HOST_CHARSET == HOST_CHARSET_EBCDIC + #error "FIXME: write tables for EBCDIC" +# else + #error "Unrecognized host character set" +# endif +#endif diff --git a/external/gpl3/gdb/dist/libiberty/setenv.c b/external/gpl3/gdb/dist/libiberty/setenv.c new file mode 100644 index 000000000000..96917d5769f4 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/setenv.c @@ -0,0 +1,185 @@ +/* Copyright (C) 1992, 1995, 1996, 1997, 2002, 2011 Free Software Foundation, + Inc. + This file based on setenv.c in the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + + +/* + +@deftypefn Supplemental int setenv (const char *@var{name}, @ + const char *@var{value}, int @var{overwrite}) +@deftypefnx Supplemental void unsetenv (const char *@var{name}) + +@code{setenv} adds @var{name} to the environment with value +@var{value}. If the name was already present in the environment, +the new value will be stored only if @var{overwrite} is nonzero. +The companion @code{unsetenv} function removes @var{name} from the +environment. This implementation is not safe for multithreaded code. + +@end deftypefn + +*/ + +#if HAVE_CONFIG_H +# include +#endif + +#define setenv libiberty_setenv +#define unsetenv libiberty_unsetenv + +#include "ansidecl.h" +#include /* For `size_t' */ +#include /* For `NULL' */ + +#include +#if !defined(errno) && !defined(HAVE_ERRNO_DECL) +extern int errno; +#endif +#define __set_errno(ev) ((errno) = (ev)) + +#if HAVE_STDLIB_H +# include +#endif +#if HAVE_STRING_H +# include +#endif +#if HAVE_UNISTD_H +# include +#endif + +#define __environ environ +#ifndef HAVE_ENVIRON_DECL +extern char **environ; +#endif + +#undef setenv +#undef unsetenv + +/* LOCK and UNLOCK are defined as no-ops. This makes the libiberty + * implementation MT-Unsafe. */ +#define LOCK +#define UNLOCK + +/* Below this point, it's verbatim code from the glibc-2.0 implementation */ + +/* If this variable is not a null pointer we allocated the current + environment. */ +static char **last_environ; + + +int +setenv (const char *name, const char *value, int replace) +{ + register char **ep = 0; + register size_t size; + const size_t namelen = strlen (name); + const size_t vallen = strlen (value) + 1; + + LOCK; + + size = 0; + if (__environ != NULL) + { + for (ep = __environ; *ep != NULL; ++ep) + if (!strncmp (*ep, name, namelen) && (*ep)[namelen] == '=') + break; + else + ++size; + } + + if (__environ == NULL || *ep == NULL) + { + char **new_environ; + if (__environ == last_environ && __environ != NULL) + /* We allocated this space; we can extend it. */ + new_environ = (char **) realloc (last_environ, + (size + 2) * sizeof (char *)); + else + new_environ = (char **) malloc ((size + 2) * sizeof (char *)); + + if (new_environ == NULL) + { + UNLOCK; + return -1; + } + + new_environ[size] = (char *) malloc (namelen + 1 + vallen); + if (new_environ[size] == NULL) + { + free ((char *) new_environ); + __set_errno (ENOMEM); + UNLOCK; + return -1; + } + + if (__environ != last_environ) + memcpy ((char *) new_environ, (char *) __environ, + size * sizeof (char *)); + + memcpy (new_environ[size], name, namelen); + new_environ[size][namelen] = '='; + memcpy (&new_environ[size][namelen + 1], value, vallen); + + new_environ[size + 1] = NULL; + + last_environ = __environ = new_environ; + } + else if (replace) + { + size_t len = strlen (*ep); + if (len + 1 < namelen + 1 + vallen) + { + /* The existing string is too short; malloc a new one. */ + char *new_string = (char *) malloc (namelen + 1 + vallen); + if (new_string == NULL) + { + UNLOCK; + return -1; + } + *ep = new_string; + } + memcpy (*ep, name, namelen); + (*ep)[namelen] = '='; + memcpy (&(*ep)[namelen + 1], value, vallen); + } + + UNLOCK; + + return 0; +} + +void +unsetenv (const char *name) +{ + const size_t len = strlen (name); + char **ep; + + LOCK; + + for (ep = __environ; *ep; ++ep) + if (!strncmp (*ep, name, len) && (*ep)[len] == '=') + { + /* Found it. Remove this pointer by moving later ones back. */ + char **dp = ep; + do + dp[0] = dp[1]; + while (*dp++); + /* Continue the loop in case NAME appears again. */ + } + + UNLOCK; +} diff --git a/external/gpl3/gdb/dist/libiberty/setproctitle.c b/external/gpl3/gdb/dist/libiberty/setproctitle.c new file mode 100644 index 000000000000..3b3f377b67b7 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/setproctitle.c @@ -0,0 +1,48 @@ +/* Set the title of a process. + Copyright (C) 2010, 2011 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#ifdef HAVE_SYS_PRCTL_H +#include +#include +#endif +#include "ansidecl.h" + +/* + +@deftypefn Supplemental void setproctitle (const char *@var{fmt}, ...) + +Set the title of a process to @var{fmt}. va args not supported for now, +but defined for compatibility with BSD. + +@end deftypefn + +*/ + +void +setproctitle (const char *name ATTRIBUTE_UNUSED, ...) +{ +#ifdef PR_SET_NAME + /* On Linux this sets the top visible "comm", but not necessarily + the name visible in ps. */ + prctl (PR_SET_NAME, name); +#endif +} diff --git a/external/gpl3/gdb/dist/libiberty/sha1.c b/external/gpl3/gdb/dist/libiberty/sha1.c new file mode 100644 index 000000000000..6a25ab239925 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/sha1.c @@ -0,0 +1,416 @@ +/* sha1.c - Functions to compute SHA1 message digest of files or + memory blocks according to the NIST specification FIPS-180-1. + + Copyright (C) 2000, 2001, 2003, 2004, 2005, 2006, 2008 Free Software + Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Written by Scott G. Miller + Credits: + Robert Klep -- Expansion function fix +*/ + +#include + +#include "sha1.h" + +#include +#include + +#if USE_UNLOCKED_IO +# include "unlocked-io.h" +#endif + +#ifdef WORDS_BIGENDIAN +# define SWAP(n) (n) +#else +# define SWAP(n) \ + (((n) << 24) | (((n) & 0xff00) << 8) | (((n) >> 8) & 0xff00) | ((n) >> 24)) +#endif + +#define BLOCKSIZE 4096 +#if BLOCKSIZE % 64 != 0 +# error "invalid BLOCKSIZE" +#endif + +/* This array contains the bytes used to pad the buffer to the next + 64-byte boundary. (RFC 1321, 3.1: Step 1) */ +static const unsigned char fillbuf[64] = { 0x80, 0 /* , 0, 0, ... */ }; + + +/* Take a pointer to a 160 bit block of data (five 32 bit ints) and + initialize it to the start constants of the SHA1 algorithm. This + must be called before using hash in the call to sha1_hash. */ +void +sha1_init_ctx (struct sha1_ctx *ctx) +{ + ctx->A = 0x67452301; + ctx->B = 0xefcdab89; + ctx->C = 0x98badcfe; + ctx->D = 0x10325476; + ctx->E = 0xc3d2e1f0; + + ctx->total[0] = ctx->total[1] = 0; + ctx->buflen = 0; +} + +/* Put result from CTX in first 20 bytes following RESBUF. The result + must be in little endian byte order. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32-bit value. */ +void * +sha1_read_ctx (const struct sha1_ctx *ctx, void *resbuf) +{ + ((sha1_uint32 *) resbuf)[0] = SWAP (ctx->A); + ((sha1_uint32 *) resbuf)[1] = SWAP (ctx->B); + ((sha1_uint32 *) resbuf)[2] = SWAP (ctx->C); + ((sha1_uint32 *) resbuf)[3] = SWAP (ctx->D); + ((sha1_uint32 *) resbuf)[4] = SWAP (ctx->E); + + return resbuf; +} + +/* Process the remaining bytes in the internal buffer and the usual + prolog according to the standard and write the result to RESBUF. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32-bit value. */ +void * +sha1_finish_ctx (struct sha1_ctx *ctx, void *resbuf) +{ + /* Take yet unprocessed bytes into account. */ + sha1_uint32 bytes = ctx->buflen; + size_t size = (bytes < 56) ? 64 / 4 : 64 * 2 / 4; + + /* Now count remaining bytes. */ + ctx->total[0] += bytes; + if (ctx->total[0] < bytes) + ++ctx->total[1]; + + /* Put the 64-bit file length in *bits* at the end of the buffer. */ + ctx->buffer[size - 2] = SWAP ((ctx->total[1] << 3) | (ctx->total[0] >> 29)); + ctx->buffer[size - 1] = SWAP (ctx->total[0] << 3); + + memcpy (&((char *) ctx->buffer)[bytes], fillbuf, (size - 2) * 4 - bytes); + + /* Process last bytes. */ + sha1_process_block (ctx->buffer, size * 4, ctx); + + return sha1_read_ctx (ctx, resbuf); +} + +/* Compute SHA1 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 16 bytes + beginning at RESBLOCK. */ +int +sha1_stream (FILE *stream, void *resblock) +{ + struct sha1_ctx ctx; + char buffer[BLOCKSIZE + 72]; + size_t sum; + + /* Initialize the computation context. */ + sha1_init_ctx (&ctx); + + /* Iterate over full file contents. */ + while (1) + { + /* We read the file in blocks of BLOCKSIZE bytes. One call of the + computation function processes the whole buffer so that with the + next round of the loop another block can be read. */ + size_t n; + sum = 0; + + /* Read block. Take care for partial reads. */ + while (1) + { + n = fread (buffer + sum, 1, BLOCKSIZE - sum, stream); + + sum += n; + + if (sum == BLOCKSIZE) + break; + + if (n == 0) + { + /* Check for the error flag IFF N == 0, so that we don't + exit the loop after a partial read due to e.g., EAGAIN + or EWOULDBLOCK. */ + if (ferror (stream)) + return 1; + goto process_partial_block; + } + + /* We've read at least one byte, so ignore errors. But always + check for EOF, since feof may be true even though N > 0. + Otherwise, we could end up calling fread after EOF. */ + if (feof (stream)) + goto process_partial_block; + } + + /* Process buffer with BLOCKSIZE bytes. Note that + BLOCKSIZE % 64 == 0 + */ + sha1_process_block (buffer, BLOCKSIZE, &ctx); + } + + process_partial_block:; + + /* Process any remaining bytes. */ + if (sum > 0) + sha1_process_bytes (buffer, sum, &ctx); + + /* Construct result in desired memory. */ + sha1_finish_ctx (&ctx, resblock); + return 0; +} + +/* Compute SHA1 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +void * +sha1_buffer (const char *buffer, size_t len, void *resblock) +{ + struct sha1_ctx ctx; + + /* Initialize the computation context. */ + sha1_init_ctx (&ctx); + + /* Process whole buffer but last len % 64 bytes. */ + sha1_process_bytes (buffer, len, &ctx); + + /* Put result in desired memory area. */ + return sha1_finish_ctx (&ctx, resblock); +} + +void +sha1_process_bytes (const void *buffer, size_t len, struct sha1_ctx *ctx) +{ + /* When we already have some bits in our internal buffer concatenate + both inputs first. */ + if (ctx->buflen != 0) + { + size_t left_over = ctx->buflen; + size_t add = 128 - left_over > len ? len : 128 - left_over; + + memcpy (&((char *) ctx->buffer)[left_over], buffer, add); + ctx->buflen += add; + + if (ctx->buflen > 64) + { + sha1_process_block (ctx->buffer, ctx->buflen & ~63, ctx); + + ctx->buflen &= 63; + /* The regions in the following copy operation cannot overlap. */ + memcpy (ctx->buffer, + &((char *) ctx->buffer)[(left_over + add) & ~63], + ctx->buflen); + } + + buffer = (const char *) buffer + add; + len -= add; + } + + /* Process available complete blocks. */ + if (len >= 64) + { +#if !_STRING_ARCH_unaligned +# define alignof(type) offsetof (struct { char c; type x; }, x) +# define UNALIGNED_P(p) (((size_t) p) % alignof (sha1_uint32) != 0) + if (UNALIGNED_P (buffer)) + while (len > 64) + { + sha1_process_block (memcpy (ctx->buffer, buffer, 64), 64, ctx); + buffer = (const char *) buffer + 64; + len -= 64; + } + else +#endif + { + sha1_process_block (buffer, len & ~63, ctx); + buffer = (const char *) buffer + (len & ~63); + len &= 63; + } + } + + /* Move remaining bytes in internal buffer. */ + if (len > 0) + { + size_t left_over = ctx->buflen; + + memcpy (&((char *) ctx->buffer)[left_over], buffer, len); + left_over += len; + if (left_over >= 64) + { + sha1_process_block (ctx->buffer, 64, ctx); + left_over -= 64; + memcpy (ctx->buffer, &ctx->buffer[16], left_over); + } + ctx->buflen = left_over; + } +} + +/* --- Code below is the primary difference between md5.c and sha1.c --- */ + +/* SHA1 round constants */ +#define K1 0x5a827999 +#define K2 0x6ed9eba1 +#define K3 0x8f1bbcdc +#define K4 0xca62c1d6 + +/* Round functions. Note that F2 is the same as F4. */ +#define F1(B,C,D) ( D ^ ( B & ( C ^ D ) ) ) +#define F2(B,C,D) (B ^ C ^ D) +#define F3(B,C,D) ( ( B & C ) | ( D & ( B | C ) ) ) +#define F4(B,C,D) (B ^ C ^ D) + +/* Process LEN bytes of BUFFER, accumulating context into CTX. + It is assumed that LEN % 64 == 0. + Most of this code comes from GnuPG's cipher/sha1.c. */ + +void +sha1_process_block (const void *buffer, size_t len, struct sha1_ctx *ctx) +{ + const sha1_uint32 *words = (const sha1_uint32*) buffer; + size_t nwords = len / sizeof (sha1_uint32); + const sha1_uint32 *endp = words + nwords; + sha1_uint32 x[16]; + sha1_uint32 a = ctx->A; + sha1_uint32 b = ctx->B; + sha1_uint32 c = ctx->C; + sha1_uint32 d = ctx->D; + sha1_uint32 e = ctx->E; + + /* First increment the byte count. RFC 1321 specifies the possible + length of the file up to 2^64 bits. Here we only compute the + number of bytes. Do a double word increment. */ + ctx->total[0] += len; + if (ctx->total[0] < len) + ++ctx->total[1]; + +#define rol(x, n) (((x) << (n)) | ((sha1_uint32) (x) >> (32 - (n)))) + +#define M(I) ( tm = x[I&0x0f] ^ x[(I-14)&0x0f] \ + ^ x[(I-8)&0x0f] ^ x[(I-3)&0x0f] \ + , (x[I&0x0f] = rol(tm, 1)) ) + +#define R(A,B,C,D,E,F,K,M) do { E += rol( A, 5 ) \ + + F( B, C, D ) \ + + K \ + + M; \ + B = rol( B, 30 ); \ + } while(0) + + while (words < endp) + { + sha1_uint32 tm; + int t; + for (t = 0; t < 16; t++) + { + x[t] = SWAP (*words); + words++; + } + + R( a, b, c, d, e, F1, K1, x[ 0] ); + R( e, a, b, c, d, F1, K1, x[ 1] ); + R( d, e, a, b, c, F1, K1, x[ 2] ); + R( c, d, e, a, b, F1, K1, x[ 3] ); + R( b, c, d, e, a, F1, K1, x[ 4] ); + R( a, b, c, d, e, F1, K1, x[ 5] ); + R( e, a, b, c, d, F1, K1, x[ 6] ); + R( d, e, a, b, c, F1, K1, x[ 7] ); + R( c, d, e, a, b, F1, K1, x[ 8] ); + R( b, c, d, e, a, F1, K1, x[ 9] ); + R( a, b, c, d, e, F1, K1, x[10] ); + R( e, a, b, c, d, F1, K1, x[11] ); + R( d, e, a, b, c, F1, K1, x[12] ); + R( c, d, e, a, b, F1, K1, x[13] ); + R( b, c, d, e, a, F1, K1, x[14] ); + R( a, b, c, d, e, F1, K1, x[15] ); + R( e, a, b, c, d, F1, K1, M(16) ); + R( d, e, a, b, c, F1, K1, M(17) ); + R( c, d, e, a, b, F1, K1, M(18) ); + R( b, c, d, e, a, F1, K1, M(19) ); + R( a, b, c, d, e, F2, K2, M(20) ); + R( e, a, b, c, d, F2, K2, M(21) ); + R( d, e, a, b, c, F2, K2, M(22) ); + R( c, d, e, a, b, F2, K2, M(23) ); + R( b, c, d, e, a, F2, K2, M(24) ); + R( a, b, c, d, e, F2, K2, M(25) ); + R( e, a, b, c, d, F2, K2, M(26) ); + R( d, e, a, b, c, F2, K2, M(27) ); + R( c, d, e, a, b, F2, K2, M(28) ); + R( b, c, d, e, a, F2, K2, M(29) ); + R( a, b, c, d, e, F2, K2, M(30) ); + R( e, a, b, c, d, F2, K2, M(31) ); + R( d, e, a, b, c, F2, K2, M(32) ); + R( c, d, e, a, b, F2, K2, M(33) ); + R( b, c, d, e, a, F2, K2, M(34) ); + R( a, b, c, d, e, F2, K2, M(35) ); + R( e, a, b, c, d, F2, K2, M(36) ); + R( d, e, a, b, c, F2, K2, M(37) ); + R( c, d, e, a, b, F2, K2, M(38) ); + R( b, c, d, e, a, F2, K2, M(39) ); + R( a, b, c, d, e, F3, K3, M(40) ); + R( e, a, b, c, d, F3, K3, M(41) ); + R( d, e, a, b, c, F3, K3, M(42) ); + R( c, d, e, a, b, F3, K3, M(43) ); + R( b, c, d, e, a, F3, K3, M(44) ); + R( a, b, c, d, e, F3, K3, M(45) ); + R( e, a, b, c, d, F3, K3, M(46) ); + R( d, e, a, b, c, F3, K3, M(47) ); + R( c, d, e, a, b, F3, K3, M(48) ); + R( b, c, d, e, a, F3, K3, M(49) ); + R( a, b, c, d, e, F3, K3, M(50) ); + R( e, a, b, c, d, F3, K3, M(51) ); + R( d, e, a, b, c, F3, K3, M(52) ); + R( c, d, e, a, b, F3, K3, M(53) ); + R( b, c, d, e, a, F3, K3, M(54) ); + R( a, b, c, d, e, F3, K3, M(55) ); + R( e, a, b, c, d, F3, K3, M(56) ); + R( d, e, a, b, c, F3, K3, M(57) ); + R( c, d, e, a, b, F3, K3, M(58) ); + R( b, c, d, e, a, F3, K3, M(59) ); + R( a, b, c, d, e, F4, K4, M(60) ); + R( e, a, b, c, d, F4, K4, M(61) ); + R( d, e, a, b, c, F4, K4, M(62) ); + R( c, d, e, a, b, F4, K4, M(63) ); + R( b, c, d, e, a, F4, K4, M(64) ); + R( a, b, c, d, e, F4, K4, M(65) ); + R( e, a, b, c, d, F4, K4, M(66) ); + R( d, e, a, b, c, F4, K4, M(67) ); + R( c, d, e, a, b, F4, K4, M(68) ); + R( b, c, d, e, a, F4, K4, M(69) ); + R( a, b, c, d, e, F4, K4, M(70) ); + R( e, a, b, c, d, F4, K4, M(71) ); + R( d, e, a, b, c, F4, K4, M(72) ); + R( c, d, e, a, b, F4, K4, M(73) ); + R( b, c, d, e, a, F4, K4, M(74) ); + R( a, b, c, d, e, F4, K4, M(75) ); + R( e, a, b, c, d, F4, K4, M(76) ); + R( d, e, a, b, c, F4, K4, M(77) ); + R( c, d, e, a, b, F4, K4, M(78) ); + R( b, c, d, e, a, F4, K4, M(79) ); + + a = ctx->A += a; + b = ctx->B += b; + c = ctx->C += c; + d = ctx->D += d; + e = ctx->E += e; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/sigsetmask.c b/external/gpl3/gdb/dist/libiberty/sigsetmask.c new file mode 100644 index 000000000000..3b708b16adb4 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/sigsetmask.c @@ -0,0 +1,40 @@ +/* Version of sigsetmask.c + Written by Steve Chamberlain (sac@cygnus.com). + Contributed by Cygnus Support. + This file is in the public doamin. */ + +/* + +@deftypefn Supplemental int sigsetmask (int @var{set}) + +Sets the signal mask to the one provided in @var{set} and returns +the old mask (which, for libiberty's implementation, will always +be the value @code{1}). + +@end deftypefn + +*/ + +#define _POSIX_SOURCE +#include +/* Including seems to be needed by ISC. */ +#include +#include + +extern void abort (void) ATTRIBUTE_NORETURN; + +#ifdef SIG_SETMASK +int +sigsetmask (int set) +{ + sigset_t new_sig; + sigset_t old_sig; + + sigemptyset (&new_sig); + if (set != 0) { + abort(); /* FIXME, we don't know how to translate old mask to new */ + } + sigprocmask(SIG_SETMASK, &new_sig, &old_sig); + return 1; /* FIXME, we always return 1 as old value. */ +} +#endif diff --git a/external/gpl3/gdb/dist/libiberty/simple-object-coff.c b/external/gpl3/gdb/dist/libiberty/simple-object-coff.c new file mode 100644 index 000000000000..a7802a520760 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object-coff.c @@ -0,0 +1,804 @@ +/* simple-object-coff.c -- routines to manipulate COFF object files. + Copyright 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Google. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "simple-object.h" + +#include +#include + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STDINT_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "simple-object-common.h" + +/* COFF structures and constants. */ + +/* COFF file header. */ + +struct external_filehdr +{ + unsigned char f_magic[2]; /* magic number */ + unsigned char f_nscns[2]; /* number of sections */ + unsigned char f_timdat[4]; /* time & date stamp */ + unsigned char f_symptr[4]; /* file pointer to symtab */ + unsigned char f_nsyms[4]; /* number of symtab entries */ + unsigned char f_opthdr[2]; /* sizeof(optional hdr) */ + unsigned char f_flags[2]; /* flags */ +}; + +/* Bits for filehdr f_flags field. */ + +#define F_EXEC (0x0002) +#define IMAGE_FILE_SYSTEM (0x1000) +#define IMAGE_FILE_DLL (0x2000) + +/* COFF section header. */ + +struct external_scnhdr +{ + unsigned char s_name[8]; /* section name */ + unsigned char s_paddr[4]; /* physical address, aliased s_nlib */ + unsigned char s_vaddr[4]; /* virtual address */ + unsigned char s_size[4]; /* section size */ + unsigned char s_scnptr[4]; /* file ptr to raw data for section */ + unsigned char s_relptr[4]; /* file ptr to relocation */ + unsigned char s_lnnoptr[4]; /* file ptr to line numbers */ + unsigned char s_nreloc[2]; /* number of relocation entries */ + unsigned char s_nlnno[2]; /* number of line number entries */ + unsigned char s_flags[4]; /* flags */ +}; + +/* The length of the s_name field in struct external_scnhdr. */ + +#define SCNNMLEN (8) + +/* Bits for scnhdr s_flags field. This includes some bits defined + only for PE. This may need to be moved into coff_magic. */ + +#define STYP_DATA (1 << 6) +#define IMAGE_SCN_MEM_DISCARDABLE (1 << 25) +#define IMAGE_SCN_MEM_SHARED (1 << 28) +#define IMAGE_SCN_MEM_READ (1 << 30) + +#define IMAGE_SCN_ALIGN_POWER_BIT_POS 20 +#define IMAGE_SCN_ALIGN_POWER_CONST(val) \ + (((val) + 1) << IMAGE_SCN_ALIGN_POWER_BIT_POS) + +/* COFF symbol table entry. */ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ + +struct external_syment +{ + union + { + unsigned char e_name[E_SYMNMLEN]; + + struct + { + unsigned char e_zeroes[4]; + unsigned char e_offset[4]; + } e; + } e; + + unsigned char e_value[4]; + unsigned char e_scnum[2]; + unsigned char e_type[2]; + unsigned char e_sclass[1]; + unsigned char e_numaux[1]; +}; + +/* Length allowed for filename in aux sym format 4. */ + +#define E_FILNMLEN 18 + +/* Omits x_sym and other unused variants. */ + +union external_auxent +{ + /* Aux sym format 4: file. */ + union + { + char x_fname[E_FILNMLEN]; + struct + { + unsigned char x_zeroes[4]; + unsigned char x_offset[4]; + } x_n; + } x_file; + /* Aux sym format 5: section. */ + struct + { + unsigned char x_scnlen[4]; /* section length */ + unsigned char x_nreloc[2]; /* # relocation entries */ + unsigned char x_nlinno[2]; /* # line numbers */ + unsigned char x_checksum[4]; /* section COMDAT checksum */ + unsigned char x_associated[2]; /* COMDAT assoc section index */ + unsigned char x_comdat[1]; /* COMDAT selection number */ + } x_scn; +}; + +/* Symbol-related constants. */ + +#define IMAGE_SYM_DEBUG (-2) +#define IMAGE_SYM_TYPE_NULL (0) +#define IMAGE_SYM_DTYPE_NULL (0) +#define IMAGE_SYM_CLASS_STATIC (3) +#define IMAGE_SYM_CLASS_FILE (103) + +#define IMAGE_SYM_TYPE \ + ((IMAGE_SYM_DTYPE_NULL << 4) | IMAGE_SYM_TYPE_NULL) + +/* Private data for an simple_object_read. */ + +struct simple_object_coff_read +{ + /* Magic number. */ + unsigned short magic; + /* Whether the file is big-endian. */ + unsigned char is_big_endian; + /* Number of sections. */ + unsigned short nscns; + /* File offset of symbol table. */ + off_t symptr; + /* Number of symbol table entries. */ + unsigned int nsyms; + /* Flags. */ + unsigned short flags; + /* Offset of section headers in file. */ + off_t scnhdr_offset; +}; + +/* Private data for an simple_object_attributes. */ + +struct simple_object_coff_attributes +{ + /* Magic number. */ + unsigned short magic; + /* Whether the file is big-endian. */ + unsigned char is_big_endian; + /* Flags. */ + unsigned short flags; +}; + +/* There is no magic number which indicates a COFF file as opposed to + any other sort of file. Instead, each COFF file starts with a + two-byte magic number which also indicates the type of the target. + This struct holds a magic number as well as characteristics of that + COFF format. */ + +struct coff_magic_struct +{ + /* Magic number. */ + unsigned short magic; + /* Whether this magic number is for a big-endian file. */ + unsigned char is_big_endian; + /* Flag bits, in the f_flags fields, which indicates that this file + is not a relocatable object file. There is no flag which + specifically indicates a relocatable object file, it is only + implied by the absence of these flags. */ + unsigned short non_object_flags; +}; + +/* This is a list of the COFF magic numbers which we recognize, namely + the ones used on Windows. More can be added as needed. */ + +static const struct coff_magic_struct coff_magic[] = +{ + /* i386. */ + { 0x14c, 0, F_EXEC | IMAGE_FILE_SYSTEM | IMAGE_FILE_DLL }, + /* x86_64. */ + { 0x8664, 0, F_EXEC | IMAGE_FILE_SYSTEM | IMAGE_FILE_DLL } +}; + +/* See if we have a COFF file. */ + +static void * +simple_object_coff_match (unsigned char header[SIMPLE_OBJECT_MATCH_HEADER_LEN], + int descriptor, off_t offset, + const char *segment_name ATTRIBUTE_UNUSED, + const char **errmsg, int *err) +{ + size_t c; + unsigned short magic_big; + unsigned short magic_little; + unsigned short magic; + size_t i; + int is_big_endian; + unsigned short (*fetch_16) (const unsigned char *); + unsigned int (*fetch_32) (const unsigned char *); + unsigned char hdrbuf[sizeof (struct external_filehdr)]; + unsigned short flags; + struct simple_object_coff_read *ocr; + + c = sizeof (coff_magic) / sizeof (coff_magic[0]); + magic_big = simple_object_fetch_big_16 (header); + magic_little = simple_object_fetch_little_16 (header); + for (i = 0; i < c; ++i) + { + if (coff_magic[i].is_big_endian + ? coff_magic[i].magic == magic_big + : coff_magic[i].magic == magic_little) + break; + } + if (i >= c) + { + *errmsg = NULL; + *err = 0; + return NULL; + } + is_big_endian = coff_magic[i].is_big_endian; + + magic = is_big_endian ? magic_big : magic_little; + fetch_16 = (is_big_endian + ? simple_object_fetch_big_16 + : simple_object_fetch_little_16); + fetch_32 = (is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + if (!simple_object_internal_read (descriptor, offset, hdrbuf, sizeof hdrbuf, + errmsg, err)) + return NULL; + + flags = fetch_16 (hdrbuf + offsetof (struct external_filehdr, f_flags)); + if ((flags & coff_magic[i].non_object_flags) != 0) + { + *errmsg = "not relocatable object file"; + *err = 0; + return NULL; + } + + ocr = XNEW (struct simple_object_coff_read); + ocr->magic = magic; + ocr->is_big_endian = is_big_endian; + ocr->nscns = fetch_16 (hdrbuf + offsetof (struct external_filehdr, f_nscns)); + ocr->symptr = fetch_32 (hdrbuf + + offsetof (struct external_filehdr, f_symptr)); + ocr->nsyms = fetch_32 (hdrbuf + offsetof (struct external_filehdr, f_nsyms)); + ocr->flags = flags; + ocr->scnhdr_offset = (sizeof (struct external_filehdr) + + fetch_16 (hdrbuf + offsetof (struct external_filehdr, + f_opthdr))); + + return (void *) ocr; +} + +/* Read the string table in a COFF file. */ + +static char * +simple_object_coff_read_strtab (simple_object_read *sobj, size_t *strtab_size, + const char **errmsg, int *err) +{ + struct simple_object_coff_read *ocr = + (struct simple_object_coff_read *) sobj->data; + off_t strtab_offset; + unsigned char strsizebuf[4]; + size_t strsize; + char *strtab; + + strtab_offset = sobj->offset + ocr->symptr + + ocr->nsyms * sizeof (struct external_syment); + if (!simple_object_internal_read (sobj->descriptor, strtab_offset, + strsizebuf, 4, errmsg, err)) + return NULL; + strsize = (ocr->is_big_endian + ? simple_object_fetch_big_32 (strsizebuf) + : simple_object_fetch_little_32 (strsizebuf)); + strtab = XNEWVEC (char, strsize); + if (!simple_object_internal_read (sobj->descriptor, strtab_offset, + (unsigned char *) strtab, strsize, errmsg, + err)) + { + XDELETEVEC (strtab); + return NULL; + } + *strtab_size = strsize; + return strtab; +} + +/* Find all sections in a COFF file. */ + +static const char * +simple_object_coff_find_sections (simple_object_read *sobj, + int (*pfn) (void *, const char *, + off_t offset, off_t length), + void *data, + int *err) +{ + struct simple_object_coff_read *ocr = + (struct simple_object_coff_read *) sobj->data; + size_t scnhdr_size; + unsigned char *scnbuf; + const char *errmsg; + unsigned int (*fetch_32) (const unsigned char *); + unsigned int nscns; + char *strtab; + size_t strtab_size; + unsigned int i; + + scnhdr_size = sizeof (struct external_scnhdr); + scnbuf = XNEWVEC (unsigned char, scnhdr_size * ocr->nscns); + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + ocr->scnhdr_offset, + scnbuf, scnhdr_size * ocr->nscns, &errmsg, + err)) + { + XDELETEVEC (scnbuf); + return errmsg; + } + + fetch_32 = (ocr->is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + nscns = ocr->nscns; + strtab = NULL; + strtab_size = 0; + for (i = 0; i < nscns; ++i) + { + unsigned char *scnhdr; + unsigned char *scnname; + char namebuf[SCNNMLEN + 1]; + char *name; + off_t scnptr; + unsigned int size; + + scnhdr = scnbuf + i * scnhdr_size; + scnname = scnhdr + offsetof (struct external_scnhdr, s_name); + memcpy (namebuf, scnname, SCNNMLEN); + namebuf[SCNNMLEN] = '\0'; + name = &namebuf[0]; + if (namebuf[0] == '/') + { + size_t strindex; + char *end; + + strindex = strtol (namebuf + 1, &end, 10); + if (*end == '\0') + { + /* The real section name is found in the string + table. */ + if (strtab == NULL) + { + strtab = simple_object_coff_read_strtab (sobj, + &strtab_size, + &errmsg, err); + if (strtab == NULL) + { + XDELETEVEC (scnbuf); + return errmsg; + } + } + + if (strindex < 4 || strindex >= strtab_size) + { + XDELETEVEC (strtab); + XDELETEVEC (scnbuf); + *err = 0; + return "section string index out of range"; + } + + name = strtab + strindex; + } + } + + scnptr = fetch_32 (scnhdr + offsetof (struct external_scnhdr, s_scnptr)); + size = fetch_32 (scnhdr + offsetof (struct external_scnhdr, s_size)); + + if (!(*pfn) (data, name, scnptr, size)) + break; + } + + if (strtab != NULL) + XDELETEVEC (strtab); + XDELETEVEC (scnbuf); + + return NULL; +} + +/* Fetch the attributes for an simple_object_read. */ + +static void * +simple_object_coff_fetch_attributes (simple_object_read *sobj, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_coff_read *ocr = + (struct simple_object_coff_read *) sobj->data; + struct simple_object_coff_attributes *ret; + + ret = XNEW (struct simple_object_coff_attributes); + ret->magic = ocr->magic; + ret->is_big_endian = ocr->is_big_endian; + ret->flags = ocr->flags; + return ret; +} + +/* Release the private data for an simple_object_read. */ + +static void +simple_object_coff_release_read (void *data) +{ + XDELETE (data); +} + +/* Compare two attributes structures. */ + +static const char * +simple_object_coff_attributes_merge (void *todata, void *fromdata, int *err) +{ + struct simple_object_coff_attributes *to = + (struct simple_object_coff_attributes *) todata; + struct simple_object_coff_attributes *from = + (struct simple_object_coff_attributes *) fromdata; + + if (to->magic != from->magic || to->is_big_endian != from->is_big_endian) + { + *err = 0; + return "COFF object format mismatch"; + } + return NULL; +} + +/* Release the private data for an attributes structure. */ + +static void +simple_object_coff_release_attributes (void *data) +{ + XDELETE (data); +} + +/* Prepare to write out a file. */ + +static void * +simple_object_coff_start_write (void *attributes_data, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_coff_attributes *attrs = + (struct simple_object_coff_attributes *) attributes_data; + struct simple_object_coff_attributes *ret; + + /* We're just going to record the attributes, but we need to make a + copy because the user may delete them. */ + ret = XNEW (struct simple_object_coff_attributes); + *ret = *attrs; + return ret; +} + +/* Write out a COFF filehdr. */ + +static int +simple_object_coff_write_filehdr (simple_object_write *sobj, int descriptor, + unsigned int nscns, size_t symtab_offset, + unsigned int nsyms, const char **errmsg, + int *err) +{ + struct simple_object_coff_attributes *attrs = + (struct simple_object_coff_attributes *) sobj->data; + unsigned char hdrbuf[sizeof (struct external_filehdr)]; + unsigned char *hdr; + void (*set_16) (unsigned char *, unsigned short); + void (*set_32) (unsigned char *, unsigned int); + + hdr = &hdrbuf[0]; + + set_16 = (attrs->is_big_endian + ? simple_object_set_big_16 + : simple_object_set_little_16); + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + memset (hdr, 0, sizeof (struct external_filehdr)); + + set_16 (hdr + offsetof (struct external_filehdr, f_magic), attrs->magic); + set_16 (hdr + offsetof (struct external_filehdr, f_nscns), nscns); + /* f_timdat left as zero. */ + set_32 (hdr + offsetof (struct external_filehdr, f_symptr), symtab_offset); + set_32 (hdr + offsetof (struct external_filehdr, f_nsyms), nsyms); + /* f_opthdr left as zero. */ + set_16 (hdr + offsetof (struct external_filehdr, f_flags), attrs->flags); + + return simple_object_internal_write (descriptor, 0, hdrbuf, + sizeof (struct external_filehdr), + errmsg, err); +} + +/* Write out a COFF section header. */ + +static int +simple_object_coff_write_scnhdr (simple_object_write *sobj, int descriptor, + const char *name, size_t *name_offset, + off_t scnhdr_offset, size_t scnsize, + off_t offset, unsigned int align, + const char **errmsg, int *err) +{ + struct simple_object_coff_attributes *attrs = + (struct simple_object_coff_attributes *) sobj->data; + void (*set_32) (unsigned char *, unsigned int); + unsigned char hdrbuf[sizeof (struct external_scnhdr)]; + unsigned char *hdr; + size_t namelen; + unsigned int flags; + + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + memset (hdrbuf, 0, sizeof hdrbuf); + hdr = &hdrbuf[0]; + + namelen = strlen (name); + if (namelen <= SCNNMLEN) + strncpy ((char *) hdr + offsetof (struct external_scnhdr, s_name), name, + SCNNMLEN); + else + { + snprintf ((char *) hdr + offsetof (struct external_scnhdr, s_name), + SCNNMLEN, "/%lu", (unsigned long) *name_offset); + *name_offset += namelen + 1; + } + + /* s_paddr left as zero. */ + /* s_vaddr left as zero. */ + set_32 (hdr + offsetof (struct external_scnhdr, s_size), scnsize); + set_32 (hdr + offsetof (struct external_scnhdr, s_scnptr), offset); + /* s_relptr left as zero. */ + /* s_lnnoptr left as zero. */ + /* s_nreloc left as zero. */ + /* s_nlnno left as zero. */ + flags = (STYP_DATA | IMAGE_SCN_MEM_DISCARDABLE | IMAGE_SCN_MEM_SHARED + | IMAGE_SCN_MEM_READ); + /* PE can represent alignment up to 13. */ + if (align > 13) + align = 13; + flags |= IMAGE_SCN_ALIGN_POWER_CONST(align); + set_32 (hdr + offsetof (struct external_scnhdr, s_flags), flags); + + return simple_object_internal_write (descriptor, scnhdr_offset, hdrbuf, + sizeof (struct external_scnhdr), + errmsg, err); +} + +/* Write out a complete COFF file. */ + +static const char * +simple_object_coff_write_to_file (simple_object_write *sobj, int descriptor, + int *err) +{ + struct simple_object_coff_attributes *attrs = + (struct simple_object_coff_attributes *) sobj->data; + unsigned int nscns, secnum; + simple_object_write_section *section; + off_t scnhdr_offset; + size_t symtab_offset; + off_t secsym_offset; + unsigned int nsyms; + size_t offset; + size_t name_offset; + const char *errmsg; + unsigned char strsizebuf[4]; + /* The interface doesn't give us access to the name of the input file + yet. We want to use its basename for the FILE symbol. This is + what 'gas' uses when told to assemble from stdin. */ + const char *source_filename = "fake"; + size_t sflen; + union + { + struct external_syment sym; + union external_auxent aux; + } syms[2]; + void (*set_16) (unsigned char *, unsigned short); + void (*set_32) (unsigned char *, unsigned int); + + set_16 = (attrs->is_big_endian + ? simple_object_set_big_16 + : simple_object_set_little_16); + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + nscns = 0; + for (section = sobj->sections; section != NULL; section = section->next) + ++nscns; + + scnhdr_offset = sizeof (struct external_filehdr); + offset = scnhdr_offset + nscns * sizeof (struct external_scnhdr); + name_offset = 4; + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t mask; + size_t new_offset; + size_t scnsize; + struct simple_object_write_section_buffer *buffer; + + mask = (1U << section->align) - 1; + new_offset = offset & mask; + new_offset &= ~ mask; + while (new_offset > offset) + { + unsigned char zeroes[16]; + size_t write; + + memset (zeroes, 0, sizeof zeroes); + write = new_offset - offset; + if (write > sizeof zeroes) + write = sizeof zeroes; + if (!simple_object_internal_write (descriptor, offset, zeroes, write, + &errmsg, err)) + return errmsg; + } + + scnsize = 0; + for (buffer = section->buffers; buffer != NULL; buffer = buffer->next) + { + if (!simple_object_internal_write (descriptor, offset + scnsize, + ((const unsigned char *) + buffer->buffer), + buffer->size, &errmsg, err)) + return errmsg; + scnsize += buffer->size; + } + + if (!simple_object_coff_write_scnhdr (sobj, descriptor, section->name, + &name_offset, scnhdr_offset, + scnsize, offset, section->align, + &errmsg, err)) + return errmsg; + + scnhdr_offset += sizeof (struct external_scnhdr); + offset += scnsize; + } + + /* Symbol table is always half-word aligned. */ + offset += (offset & 1); + /* There is a file symbol and a section symbol per section, + and each of these has a single auxiliary symbol following. */ + nsyms = 2 * (nscns + 1); + symtab_offset = offset; + /* Advance across space reserved for symbol table to locate + start of string table. */ + offset += nsyms * sizeof (struct external_syment); + + /* Write out file symbol. */ + memset (&syms[0], 0, sizeof (syms)); + strcpy ((char *)&syms[0].sym.e.e_name[0], ".file"); + set_16 (&syms[0].sym.e_scnum[0], IMAGE_SYM_DEBUG); + set_16 (&syms[0].sym.e_type[0], IMAGE_SYM_TYPE); + syms[0].sym.e_sclass[0] = IMAGE_SYM_CLASS_FILE; + syms[0].sym.e_numaux[0] = 1; + /* The name need not be nul-terminated if it fits into the x_fname field + directly, but must be if it has to be placed into the string table. */ + sflen = strlen (source_filename); + if (sflen <= E_FILNMLEN) + memcpy (&syms[1].aux.x_file.x_fname[0], source_filename, sflen); + else + { + set_32 (&syms[1].aux.x_file.x_n.x_offset[0], name_offset); + if (!simple_object_internal_write (descriptor, offset + name_offset, + ((const unsigned char *) + source_filename), + sflen + 1, &errmsg, err)) + return errmsg; + name_offset += strlen (source_filename) + 1; + } + if (!simple_object_internal_write (descriptor, symtab_offset, + (const unsigned char *) &syms[0], + sizeof (syms), &errmsg, err)) + return errmsg; + + /* Write the string table length, followed by the strings and section + symbols in step with each other. */ + set_32 (strsizebuf, name_offset); + if (!simple_object_internal_write (descriptor, offset, strsizebuf, 4, + &errmsg, err)) + return errmsg; + + name_offset = 4; + secsym_offset = symtab_offset + sizeof (syms); + memset (&syms[0], 0, sizeof (syms)); + set_16 (&syms[0].sym.e_type[0], IMAGE_SYM_TYPE); + syms[0].sym.e_sclass[0] = IMAGE_SYM_CLASS_STATIC; + syms[0].sym.e_numaux[0] = 1; + secnum = 1; + + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t namelen; + size_t scnsize; + struct simple_object_write_section_buffer *buffer; + + namelen = strlen (section->name); + set_16 (&syms[0].sym.e_scnum[0], secnum++); + scnsize = 0; + for (buffer = section->buffers; buffer != NULL; buffer = buffer->next) + scnsize += buffer->size; + set_32 (&syms[1].aux.x_scn.x_scnlen[0], scnsize); + if (namelen > SCNNMLEN) + { + set_32 (&syms[0].sym.e.e.e_zeroes[0], 0); + set_32 (&syms[0].sym.e.e.e_offset[0], name_offset); + if (!simple_object_internal_write (descriptor, offset + name_offset, + ((const unsigned char *) + section->name), + namelen + 1, &errmsg, err)) + return errmsg; + name_offset += namelen + 1; + } + else + { + memcpy (&syms[0].sym.e.e_name[0], section->name, + strlen (section->name)); + memset (&syms[0].sym.e.e_name[strlen (section->name)], 0, + E_SYMNMLEN - strlen (section->name)); + } + + if (!simple_object_internal_write (descriptor, secsym_offset, + (const unsigned char *) &syms[0], + sizeof (syms), &errmsg, err)) + return errmsg; + secsym_offset += sizeof (syms); + } + + if (!simple_object_coff_write_filehdr (sobj, descriptor, nscns, + symtab_offset, nsyms, &errmsg, err)) + return errmsg; + + return NULL; +} + +/* Release the private data for an simple_object_write structure. */ + +static void +simple_object_coff_release_write (void *data) +{ + XDELETE (data); +} + +/* The COFF functions. */ + +const struct simple_object_functions simple_object_coff_functions = +{ + simple_object_coff_match, + simple_object_coff_find_sections, + simple_object_coff_fetch_attributes, + simple_object_coff_release_read, + simple_object_coff_attributes_merge, + simple_object_coff_release_attributes, + simple_object_coff_start_write, + simple_object_coff_write_to_file, + simple_object_coff_release_write +}; diff --git a/external/gpl3/gdb/dist/libiberty/simple-object-common.h b/external/gpl3/gdb/dist/libiberty/simple-object-common.h new file mode 100644 index 000000000000..264b179955e3 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object-common.h @@ -0,0 +1,355 @@ +/* simple-object-common.h -- common structs for object file manipulation. + Copyright (C) 2010 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, +write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* Forward reference. */ +struct simple_object_functions; + +/* An object file opened for reading. */ + +struct simple_object_read_struct +{ + /* The file descriptor. */ + int descriptor; + /* The offset within the file. */ + off_t offset; + /* The functions which do the actual work. */ + const struct simple_object_functions *functions; + /* Private data for the object file format. */ + void *data; +}; + +/* Object file attributes. */ + +struct simple_object_attributes_struct +{ + /* The functions which do the actual work. */ + const struct simple_object_functions *functions; + /* Private data for the object file format. */ + void *data; +}; + +/* An object file being created. */ + +struct simple_object_write_struct +{ + /* The functions which do the actual work. */ + const struct simple_object_functions *functions; + /* The segment_name argument from the user. */ + char *segment_name; + /* The start of the list of sections. */ + simple_object_write_section *sections; + /* The last entry in the list of sections. */ + simple_object_write_section *last_section; + /* Private data for the object file format. */ + void *data; +}; + +/* A section in an object file being created. */ + +struct simple_object_write_section_struct +{ + /* Next in the list of sections attached to an + simple_object_write. */ + simple_object_write_section *next; + /* The name of this section. */ + char *name; + /* The required alignment. */ + unsigned int align; + /* The first data attached to this section. */ + struct simple_object_write_section_buffer *buffers; + /* The last data attached to this section. */ + struct simple_object_write_section_buffer *last_buffer; +}; + +/* Data attached to a section. */ + +struct simple_object_write_section_buffer +{ + /* The next data for this section. */ + struct simple_object_write_section_buffer *next; + /* The size of the buffer. */ + size_t size; + /* The actual bytes. */ + const void *buffer; + /* A buffer to free, or NULL. */ + void *free_buffer; +}; + +/* The number of bytes we read from the start of the file to pass to + the match function. */ +#define SIMPLE_OBJECT_MATCH_HEADER_LEN (16) + +/* Format-specific object file functions. */ + +struct simple_object_functions +{ + /* If this file matches these functions, return a new value for the + private data for an simple_object_read. HEADER is the first 16 + bytes of the file. DESCRIPTOR, OFFSET, SEGMENT_NAME, ERRMSG, and + ERR are as for simple_object_open_read. If this file does not + match, this function should return NULL with *ERRMSG set to + NULL. */ + void *(*match) (unsigned char header[SIMPLE_OBJECT_MATCH_HEADER_LEN], + int descriptor, off_t offset, const char *segment_name, + const char **errmsg, int *err); + + /* Implement simple_object_find_sections. */ + const char *(*find_sections) (simple_object_read *, + int (*pfn) (void *, const char *, + off_t offset, off_t length), + void *data, + int *err); + + /* Return the private data for the attributes for SOBJ. */ + void *(*fetch_attributes) (simple_object_read *sobj, const char **errmsg, + int *err); + + /* Release the private data for an simple_object_read. */ + void (*release_read) (void *); + + /* Merge the private data for the attributes of two files. If they + could be linked together, return NULL. Otherwise return an error + message. */ + const char *(*attributes_merge) (void *, void *, int *err); + + /* Release the private data for an simple_object_attributes. */ + void (*release_attributes) (void *); + + /* Start creating an object file. */ + void *(*start_write) (void *attributes_data, const char **errmsg, + int *err); + + /* Write the complete object file. */ + const char *(*write_to_file) (simple_object_write *sobj, int descriptor, + int *err); + + /* Release the private data for an simple_object_write. */ + void (*release_write) (void *); +}; + +/* The known object file formats. */ + +extern const struct simple_object_functions simple_object_coff_functions; +extern const struct simple_object_functions simple_object_elf_functions; +extern const struct simple_object_functions simple_object_mach_o_functions; + +/* Read SIZE bytes from DESCRIPTOR at file offset OFFSET into BUFFER. + Return non-zero on success. On failure return 0 and set *ERRMSG + and *ERR. */ + +extern int +simple_object_internal_read (int descriptor, off_t offset, + unsigned char *buffer, size_t size, + const char **errmsg, int *err); + +/* Write SIZE bytes from BUFFER to DESCRIPTOR at file offset OFFSET. + Return non-zero on success. On failure return 0 and set *ERRMSG + and *ERR. */ + +extern int +simple_object_internal_write (int descriptor, off_t offset, + const unsigned char *buffer, size_t size, + const char **errmsg, int *err); + +/* Define ulong_type as an unsigned 64-bit type if available. + Otherwise just make it unsigned long. */ + +#ifdef UNSIGNED_64BIT_TYPE +__extension__ typedef UNSIGNED_64BIT_TYPE ulong_type; +#else +typedef unsigned long ulong_type; +#endif + +/* Fetch a big-endian 16-bit value. */ + +static inline unsigned short +simple_object_fetch_big_16 (const unsigned char *buf) +{ + return ((unsigned short) buf[0] << 8) | (unsigned short) buf[1]; +} + +/* Fetch a little-endian 16-bit value. */ + +static inline unsigned short +simple_object_fetch_little_16 (const unsigned char *buf) +{ + return ((unsigned short) buf[1] << 8) | (unsigned short) buf[0]; +} + +/* Fetch a big-endian 32-bit value. */ + +static inline unsigned int +simple_object_fetch_big_32 (const unsigned char *buf) +{ + return (((unsigned int) buf[0] << 24) + | ((unsigned int) buf[1] << 16) + | ((unsigned int) buf[2] << 8) + | (unsigned int) buf[3]); +} + +/* Fetch a little-endian 32-bit value. */ + +static inline unsigned int +simple_object_fetch_little_32 (const unsigned char *buf) +{ + return (((unsigned int) buf[3] << 24) + | ((unsigned int) buf[2] << 16) + | ((unsigned int) buf[1] << 8) + | (unsigned int) buf[0]); +} + +/* Fetch a big-endian 32-bit value as a ulong_type. */ + +static inline ulong_type +simple_object_fetch_big_32_ulong (const unsigned char *buf) +{ + return (ulong_type) simple_object_fetch_big_32 (buf); +} + +/* Fetch a little-endian 32-bit value as a ulong_type. */ + +static inline ulong_type +simple_object_fetch_little_32_ulong (const unsigned char *buf) +{ + return (ulong_type) simple_object_fetch_little_32 (buf); +} + +#ifdef UNSIGNED_64BIT_TYPE + +/* Fetch a big-endian 64-bit value. */ + +static inline ulong_type +simple_object_fetch_big_64 (const unsigned char *buf) +{ + return (((ulong_type) buf[0] << 56) + | ((ulong_type) buf[1] << 48) + | ((ulong_type) buf[2] << 40) + | ((ulong_type) buf[3] << 32) + | ((ulong_type) buf[4] << 24) + | ((ulong_type) buf[5] << 16) + | ((ulong_type) buf[6] << 8) + | (ulong_type) buf[7]); +} + +/* Fetch a little-endian 64-bit value. */ + +static inline ulong_type +simple_object_fetch_little_64 (const unsigned char *buf) +{ + return (((ulong_type) buf[7] << 56) + | ((ulong_type) buf[6] << 48) + | ((ulong_type) buf[5] << 40) + | ((ulong_type) buf[4] << 32) + | ((ulong_type) buf[3] << 24) + | ((ulong_type) buf[2] << 16) + | ((ulong_type) buf[1] << 8) + | (ulong_type) buf[0]); +} + +#endif + +/* Store a big-endian 16-bit value. */ + +static inline void +simple_object_set_big_16 (unsigned char *buf, unsigned short val) +{ + buf[0] = (val >> 8) & 0xff; + buf[1] = val & 0xff; +} + +/* Store a little-endian 16-bit value. */ + +static inline void +simple_object_set_little_16 (unsigned char *buf, unsigned short val) +{ + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; +} + +/* Store a big-endian 32-bit value. */ + +static inline void +simple_object_set_big_32 (unsigned char *buf, unsigned int val) +{ + buf[0] = (val >> 24) & 0xff; + buf[1] = (val >> 16) & 0xff; + buf[2] = (val >> 8) & 0xff; + buf[3] = val & 0xff; +} + +/* Store a little-endian 32-bit value. */ + +static inline void +simple_object_set_little_32 (unsigned char *buf, unsigned int val) +{ + buf[3] = (val >> 24) & 0xff; + buf[2] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; +} + +/* Store a big-endian 32-bit value coming in as a ulong_type. */ + +static inline void +simple_object_set_big_32_ulong (unsigned char *buf, ulong_type val) +{ + simple_object_set_big_32 (buf, val); +} + +/* Store a little-endian 32-bit value coming in as a ulong_type. */ + +static inline void +simple_object_set_little_32_ulong (unsigned char *buf, ulong_type val) +{ + simple_object_set_little_32 (buf, val); +} + +#ifdef UNSIGNED_64BIT_TYPE + +/* Store a big-endian 64-bit value. */ + +static inline void +simple_object_set_big_64 (unsigned char *buf, ulong_type val) +{ + buf[0] = (val >> 56) & 0xff; + buf[1] = (val >> 48) & 0xff; + buf[2] = (val >> 40) & 0xff; + buf[3] = (val >> 32) & 0xff; + buf[4] = (val >> 24) & 0xff; + buf[5] = (val >> 16) & 0xff; + buf[6] = (val >> 8) & 0xff; + buf[7] = val & 0xff; +} + +/* Store a little-endian 64-bit value. */ + +static inline void +simple_object_set_little_64 (unsigned char *buf, ulong_type val) +{ + buf[7] = (val >> 56) & 0xff; + buf[6] = (val >> 48) & 0xff; + buf[5] = (val >> 40) & 0xff; + buf[4] = (val >> 32) & 0xff; + buf[3] = (val >> 24) & 0xff; + buf[2] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/simple-object-elf.c b/external/gpl3/gdb/dist/libiberty/simple-object-elf.c new file mode 100644 index 000000000000..4196c537cde5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object-elf.c @@ -0,0 +1,953 @@ +/* simple-object-elf.c -- routines to manipulate ELF object files. + Copyright 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Google. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "simple-object.h" + +#include +#include + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STDINT_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "simple-object-common.h" + +/* ELF structures and constants. */ + +/* 32-bit ELF file header. */ + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[4]; /* Entry point virtual address */ + unsigned char e_phoff[4]; /* Program header table file offset */ + unsigned char e_shoff[4]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf32_External_Ehdr; + +/* 64-bit ELF file header. */ + +typedef struct { + unsigned char e_ident[16]; /* ELF "magic number" */ + unsigned char e_type[2]; /* Identifies object file type */ + unsigned char e_machine[2]; /* Specifies required architecture */ + unsigned char e_version[4]; /* Identifies object file version */ + unsigned char e_entry[8]; /* Entry point virtual address */ + unsigned char e_phoff[8]; /* Program header table file offset */ + unsigned char e_shoff[8]; /* Section header table file offset */ + unsigned char e_flags[4]; /* Processor-specific flags */ + unsigned char e_ehsize[2]; /* ELF header size in bytes */ + unsigned char e_phentsize[2]; /* Program header table entry size */ + unsigned char e_phnum[2]; /* Program header table entry count */ + unsigned char e_shentsize[2]; /* Section header table entry size */ + unsigned char e_shnum[2]; /* Section header table entry count */ + unsigned char e_shstrndx[2]; /* Section header string table index */ +} Elf64_External_Ehdr; + +/* Indexes and values in e_ident field of Ehdr. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7F /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +#define EI_CLASS 4 /* File class */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ + +#define EI_DATA 5 /* Data encoding */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ + +#define EI_VERSION 6 /* File version */ +#define EV_CURRENT 1 /* Current version */ + +#define EI_OSABI 7 /* Operating System/ABI indication */ + +/* Values for e_type field of Ehdr. */ + +#define ET_REL 1 /* Relocatable file */ + +/* Values for e_machine field of Ehdr. */ + +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ + +/* Special section index values. */ + +#define SHN_LORESERVE 0xFF00 /* Begin range of reserved indices */ +#define SHN_XINDEX 0xFFFF /* Section index is held elsewhere */ + +/* 32-bit ELF program header. */ + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_offset[4]; /* Segment file offset */ + unsigned char p_vaddr[4]; /* Segment virtual address */ + unsigned char p_paddr[4]; /* Segment physical address */ + unsigned char p_filesz[4]; /* Segment size in file */ + unsigned char p_memsz[4]; /* Segment size in memory */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_align[4]; /* Segment alignment, file & memory */ +} Elf32_External_Phdr; + +/* 64-bit ELF program header. */ + +typedef struct { + unsigned char p_type[4]; /* Identifies program segment type */ + unsigned char p_flags[4]; /* Segment flags */ + unsigned char p_offset[8]; /* Segment file offset */ + unsigned char p_vaddr[8]; /* Segment virtual address */ + unsigned char p_paddr[8]; /* Segment physical address */ + unsigned char p_filesz[8]; /* Segment size in file */ + unsigned char p_memsz[8]; /* Segment size in memory */ + unsigned char p_align[8]; /* Segment alignment, file & memory */ +} Elf64_External_Phdr; + +/* 32-bit ELF section header */ + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[4]; /* Miscellaneous section attributes */ + unsigned char sh_addr[4]; /* Section virtual addr at execution */ + unsigned char sh_offset[4]; /* Section file offset */ + unsigned char sh_size[4]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[4]; /* Section alignment */ + unsigned char sh_entsize[4]; /* Entry size if section holds table */ +} Elf32_External_Shdr; + +/* 64-bit ELF section header. */ + +typedef struct { + unsigned char sh_name[4]; /* Section name, index in string tbl */ + unsigned char sh_type[4]; /* Type of section */ + unsigned char sh_flags[8]; /* Miscellaneous section attributes */ + unsigned char sh_addr[8]; /* Section virtual addr at execution */ + unsigned char sh_offset[8]; /* Section file offset */ + unsigned char sh_size[8]; /* Size of section in bytes */ + unsigned char sh_link[4]; /* Index of another section */ + unsigned char sh_info[4]; /* Additional section information */ + unsigned char sh_addralign[8]; /* Section alignment */ + unsigned char sh_entsize[8]; /* Entry size if section holds table */ +} Elf64_External_Shdr; + +/* Values for sh_type field. */ + +#define SHT_PROGBITS 1 /* Program data */ +#define SHT_STRTAB 3 /* A string table */ + +/* Functions to fetch and store different ELF types, depending on the + endianness and size. */ + +struct elf_type_functions +{ + unsigned short (*fetch_Elf_Half) (const unsigned char *); + unsigned int (*fetch_Elf_Word) (const unsigned char *); + ulong_type (*fetch_Elf_Addr) (const unsigned char *); + void (*set_Elf_Half) (unsigned char *, unsigned short); + void (*set_Elf_Word) (unsigned char *, unsigned int); + void (*set_Elf_Addr) (unsigned char *, ulong_type); +}; + +static const struct elf_type_functions elf_big_32_functions = +{ + simple_object_fetch_big_16, + simple_object_fetch_big_32, + simple_object_fetch_big_32_ulong, + simple_object_set_big_16, + simple_object_set_big_32, + simple_object_set_big_32_ulong +}; + +static const struct elf_type_functions elf_little_32_functions = +{ + simple_object_fetch_little_16, + simple_object_fetch_little_32, + simple_object_fetch_little_32_ulong, + simple_object_set_little_16, + simple_object_set_little_32, + simple_object_set_little_32_ulong +}; + +#ifdef UNSIGNED_64BIT_TYPE + +static const struct elf_type_functions elf_big_64_functions = +{ + simple_object_fetch_big_16, + simple_object_fetch_big_32, + simple_object_fetch_big_64, + simple_object_set_big_16, + simple_object_set_big_32, + simple_object_set_big_64 +}; + +static const struct elf_type_functions elf_little_64_functions = +{ + simple_object_fetch_little_16, + simple_object_fetch_little_32, + simple_object_fetch_little_64, + simple_object_set_little_16, + simple_object_set_little_32, + simple_object_set_little_64 +}; + +#endif + +/* Hideous macro to fetch the value of a field from an external ELF + struct of some sort. TYPEFUNCS is the set of type functions. + BUFFER points to the external data. STRUCTTYPE is the appropriate + struct type. FIELD is a field within the struct. TYPE is the type + of the field in the struct: Elf_Half, Elf_Word, or Elf_Addr. */ + +#define ELF_FETCH_STRUCT_FIELD(TYPEFUNCS, STRUCTTYPE, FIELD, BUFFER, TYPE) \ + ((TYPEFUNCS)->fetch_ ## TYPE ((BUFFER) + offsetof (STRUCTTYPE, FIELD))) + +/* Even more hideous macro to fetch the value of FIELD from BUFFER. + SIZE is 32 or 64. STRUCTTYPE is the name of the struct from + elf/external.h: Ehdr, Shdr, etc. FIELD is the name of a field in + the struct. TYPE is the type of the field in the struct: Elf_Half, + Elf_Word, or Elf_Addr. */ + +#define ELF_FETCH_SIZED_FIELD(TYPEFUNCS, SIZE, STRUCTTYPE, BUFFER, \ + FIELD, TYPE) \ + ELF_FETCH_STRUCT_FIELD (TYPEFUNCS, \ + Elf ## SIZE ## _External_ ## STRUCTTYPE, \ + FIELD, BUFFER, TYPE) + +/* Like ELF_FETCH_SIZED_FIELD but taking an ELFCLASS value. */ + +#define ELF_FETCH_FIELD(TYPEFUNCS, CLASS, STRUCTTYPE, BUFFER, \ + FIELD, TYPE) \ + ((CLASS) == ELFCLASS32 \ + ? ELF_FETCH_SIZED_FIELD (TYPEFUNCS, 32, STRUCTTYPE, BUFFER, FIELD, \ + TYPE) \ + : ELF_FETCH_SIZED_FIELD (TYPEFUNCS, 64, STRUCTTYPE, BUFFER, FIELD, \ + TYPE)) + +/* Hideous macro to set the value of a field in an external ELF + structure to VAL. TYPEFUNCS is the set of type functions. BUFFER + points to the external data. STRUCTTYPE is the appropriate + structure type. FIELD is a field within the struct. TYPE is the + type of the field in the struct: Elf_Half, Elf_Word, or + Elf_Addr. */ + +#define ELF_SET_STRUCT_FIELD(TYPEFUNCS, STRUCTTYPE, FIELD, BUFFER, TYPE, VAL) \ + (TYPEFUNCS)->set_ ## TYPE ((BUFFER) + offsetof (STRUCTTYPE, FIELD), (VAL)) + +/* Even more hideous macro to set the value of FIELD in BUFFER to VAL. + SIZE is 32 or 64. STRUCTTYPE is the name of the struct from + elf/external.h: Ehdr, Shdr, etc. FIELD is the name of a field in + the struct. TYPE is the type of the field in the struct: Elf_Half, + Elf_Word, or Elf_Addr. */ + +#define ELF_SET_SIZED_FIELD(TYPEFUNCS, SIZE, STRUCTTYPE, BUFFER, FIELD, \ + TYPE, VAL) \ + ELF_SET_STRUCT_FIELD (TYPEFUNCS, \ + Elf ## SIZE ## _External_ ## STRUCTTYPE, \ + FIELD, BUFFER, TYPE, VAL) + +/* Like ELF_SET_SIZED_FIELD but taking an ELFCLASS value. */ + +#define ELF_SET_FIELD(TYPEFUNCS, CLASS, STRUCTTYPE, BUFFER, FIELD, \ + TYPE, VAL) \ + ((CLASS) == ELFCLASS32 \ + ? ELF_SET_SIZED_FIELD (TYPEFUNCS, 32, STRUCTTYPE, BUFFER, FIELD, \ + TYPE, VAL) \ + : ELF_SET_SIZED_FIELD (TYPEFUNCS, 64, STRUCTTYPE, BUFFER, FIELD, \ + TYPE, VAL)) + +/* Private data for an simple_object_read. */ + +struct simple_object_elf_read +{ + /* Type functions. */ + const struct elf_type_functions* type_functions; + /* Elf data. */ + unsigned char ei_data; + /* Elf class. */ + unsigned char ei_class; + /* ELF OS ABI. */ + unsigned char ei_osabi; + /* Elf machine number. */ + unsigned short machine; + /* Processor specific flags. */ + unsigned int flags; + /* File offset of section headers. */ + ulong_type shoff; + /* Number of sections. */ + unsigned int shnum; + /* Index of string table section header. */ + unsigned int shstrndx; +}; + +/* Private data for an simple_object_attributes. */ + +struct simple_object_elf_attributes +{ + /* Type functions. */ + const struct elf_type_functions* type_functions; + /* Elf data. */ + unsigned char ei_data; + /* Elf class. */ + unsigned char ei_class; + /* ELF OS ABI. */ + unsigned char ei_osabi; + /* Elf machine number. */ + unsigned short machine; + /* Processor specific flags. */ + unsigned int flags; +}; + +/* See if we have an ELF file. */ + +static void * +simple_object_elf_match (unsigned char header[SIMPLE_OBJECT_MATCH_HEADER_LEN], + int descriptor, off_t offset, + const char *segment_name ATTRIBUTE_UNUSED, + const char **errmsg, int *err) +{ + unsigned char ei_data; + unsigned char ei_class; + const struct elf_type_functions *type_functions; + unsigned char ehdr[sizeof (Elf64_External_Ehdr)]; + struct simple_object_elf_read *eor; + + if (header[EI_MAG0] != ELFMAG0 + || header[EI_MAG1] != ELFMAG1 + || header[EI_MAG2] != ELFMAG2 + || header[EI_MAG3] != ELFMAG3 + || header[EI_VERSION] != EV_CURRENT) + { + *errmsg = NULL; + *err = 0; + return NULL; + } + + ei_data = header[EI_DATA]; + if (ei_data != ELFDATA2LSB && ei_data != ELFDATA2MSB) + { + *errmsg = "unknown ELF endianness"; + *err = 0; + return NULL; + } + + ei_class = header[EI_CLASS]; + switch (ei_class) + { + case ELFCLASS32: + type_functions = (ei_data == ELFDATA2LSB + ? &elf_little_32_functions + : &elf_big_32_functions); + break; + + case ELFCLASS64: +#ifndef UNSIGNED_64BIT_TYPE + *errmsg = "64-bit ELF objects not supported"; + *err = 0; + return NULL; +#else + type_functions = (ei_data == ELFDATA2LSB + ? &elf_little_64_functions + : &elf_big_64_functions); + break; +#endif + + default: + *errmsg = "unrecognized ELF size"; + *err = 0; + return NULL; + } + + if (!simple_object_internal_read (descriptor, offset, ehdr, sizeof ehdr, + errmsg, err)) + return NULL; + + eor = XNEW (struct simple_object_elf_read); + eor->type_functions = type_functions; + eor->ei_data = ei_data; + eor->ei_class = ei_class; + eor->ei_osabi = header[EI_OSABI]; + eor->machine = ELF_FETCH_FIELD (type_functions, ei_class, Ehdr, ehdr, + e_machine, Elf_Half); + eor->flags = ELF_FETCH_FIELD (type_functions, ei_class, Ehdr, ehdr, + e_flags, Elf_Word); + eor->shoff = ELF_FETCH_FIELD (type_functions, ei_class, Ehdr, ehdr, + e_shoff, Elf_Addr); + eor->shnum = ELF_FETCH_FIELD (type_functions, ei_class, Ehdr, ehdr, + e_shnum, Elf_Half); + eor->shstrndx = ELF_FETCH_FIELD (type_functions, ei_class, Ehdr, ehdr, + e_shstrndx, Elf_Half); + + if ((eor->shnum == 0 || eor->shstrndx == SHN_XINDEX) + && eor->shoff != 0) + { + unsigned char shdr[sizeof (Elf64_External_Shdr)]; + + /* Object file has more than 0xffff sections. */ + + if (!simple_object_internal_read (descriptor, offset + eor->shoff, shdr, + (ei_class == ELFCLASS32 + ? sizeof (Elf32_External_Shdr) + : sizeof (Elf64_External_Shdr)), + errmsg, err)) + { + XDELETE (eor); + return NULL; + } + + if (eor->shnum == 0) + eor->shnum = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shdr, sh_size, Elf_Addr); + + if (eor->shstrndx == SHN_XINDEX) + { + eor->shstrndx = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shdr, sh_link, Elf_Word); + + /* Versions of the GNU binutils between 2.12 and 2.18 did + not handle objects with more than SHN_LORESERVE sections + correctly. All large section indexes were offset by + 0x100. There is more information at + http://sourceware.org/bugzilla/show_bug.cgi?id-5900 . + Fortunately these object files are easy to detect, as the + GNU binutils always put the section header string table + near the end of the list of sections. Thus if the + section header string table index is larger than the + number of sections, then we know we have to subtract + 0x100 to get the real section index. */ + if (eor->shstrndx >= eor->shnum + && eor->shstrndx >= SHN_LORESERVE + 0x100) + eor->shstrndx -= 0x100; + } + } + + if (eor->shstrndx >= eor->shnum) + { + *errmsg = "invalid ELF shstrndx >= shnum"; + *err = 0; + XDELETE (eor); + return NULL; + } + + return (void *) eor; +} + +/* Find all sections in an ELF file. */ + +static const char * +simple_object_elf_find_sections (simple_object_read *sobj, + int (*pfn) (void *, const char *, + off_t offset, off_t length), + void *data, + int *err) +{ + struct simple_object_elf_read *eor = + (struct simple_object_elf_read *) sobj->data; + const struct elf_type_functions *type_functions = eor->type_functions; + unsigned char ei_class = eor->ei_class; + size_t shdr_size; + unsigned int shnum; + unsigned char *shdrs; + const char *errmsg; + unsigned char *shstrhdr; + size_t name_size; + off_t shstroff; + unsigned char *names; + unsigned int i; + + shdr_size = (ei_class == ELFCLASS32 + ? sizeof (Elf32_External_Shdr) + : sizeof (Elf64_External_Shdr)); + + /* Read the section headers. We skip section 0, which is not a + useful section. */ + + shnum = eor->shnum; + shdrs = XNEWVEC (unsigned char, shdr_size * (shnum - 1)); + + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + eor->shoff + shdr_size, + shdrs, + shdr_size * (shnum - 1), + &errmsg, err)) + { + XDELETEVEC (shdrs); + return errmsg; + } + + /* Read the section names. */ + + shstrhdr = shdrs + (eor->shstrndx - 1) * shdr_size; + name_size = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shstrhdr, sh_size, Elf_Addr); + shstroff = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shstrhdr, sh_offset, Elf_Addr); + names = XNEWVEC (unsigned char, name_size); + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + shstroff, + names, name_size, &errmsg, err)) + { + XDELETEVEC (names); + XDELETEVEC (shdrs); + return errmsg; + } + + for (i = 1; i < shnum; ++i) + { + unsigned char *shdr; + unsigned int sh_name; + const char *name; + off_t offset; + off_t length; + + shdr = shdrs + (i - 1) * shdr_size; + sh_name = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shdr, sh_name, Elf_Word); + if (sh_name >= name_size) + { + *err = 0; + XDELETEVEC (names); + XDELETEVEC (shdrs); + return "ELF section name out of range"; + } + + name = (const char *) names + sh_name; + offset = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shdr, sh_offset, Elf_Addr); + length = ELF_FETCH_FIELD (type_functions, ei_class, Shdr, + shdr, sh_size, Elf_Addr); + + if (!(*pfn) (data, name, offset, length)) + break; + } + + XDELETEVEC (names); + XDELETEVEC (shdrs); + + return NULL; +} + +/* Fetch the attributes for an simple_object_read. */ + +static void * +simple_object_elf_fetch_attributes (simple_object_read *sobj, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_elf_read *eor = + (struct simple_object_elf_read *) sobj->data; + struct simple_object_elf_attributes *ret; + + ret = XNEW (struct simple_object_elf_attributes); + ret->type_functions = eor->type_functions; + ret->ei_data = eor->ei_data; + ret->ei_class = eor->ei_class; + ret->ei_osabi = eor->ei_osabi; + ret->machine = eor->machine; + ret->flags = eor->flags; + return ret; +} + +/* Release the privata data for an simple_object_read. */ + +static void +simple_object_elf_release_read (void *data) +{ + XDELETE (data); +} + +/* Compare two attributes structures. */ + +static const char * +simple_object_elf_attributes_merge (void *todata, void *fromdata, int *err) +{ + struct simple_object_elf_attributes *to = + (struct simple_object_elf_attributes *) todata; + struct simple_object_elf_attributes *from = + (struct simple_object_elf_attributes *) fromdata; + + if (to->ei_data != from->ei_data || to->ei_class != from->ei_class) + { + *err = 0; + return "ELF object format mismatch"; + } + + if (to->machine != from->machine) + { + int ok; + + /* EM_SPARC and EM_SPARC32PLUS are compatible and force an + output of EM_SPARC32PLUS. */ + ok = 0; + switch (to->machine) + { + case EM_SPARC: + if (from->machine == EM_SPARC32PLUS) + { + to->machine = from->machine; + ok = 1; + } + break; + + case EM_SPARC32PLUS: + if (from->machine == EM_SPARC) + ok = 1; + break; + + default: + break; + } + + if (!ok) + { + *err = 0; + return "ELF machine number mismatch"; + } + } + + return NULL; +} + +/* Release the private data for an attributes structure. */ + +static void +simple_object_elf_release_attributes (void *data) +{ + XDELETE (data); +} + +/* Prepare to write out a file. */ + +static void * +simple_object_elf_start_write (void *attributes_data, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_elf_attributes *attrs = + (struct simple_object_elf_attributes *) attributes_data; + struct simple_object_elf_attributes *ret; + + /* We're just going to record the attributes, but we need to make a + copy because the user may delete them. */ + ret = XNEW (struct simple_object_elf_attributes); + *ret = *attrs; + return ret; +} + +/* Write out an ELF ehdr. */ + +static int +simple_object_elf_write_ehdr (simple_object_write *sobj, int descriptor, + const char **errmsg, int *err) +{ + struct simple_object_elf_attributes *attrs = + (struct simple_object_elf_attributes *) sobj->data; + const struct elf_type_functions* fns; + unsigned char cl; + size_t ehdr_size; + unsigned char buf[sizeof (Elf64_External_Ehdr)]; + simple_object_write_section *section; + unsigned int shnum; + + fns = attrs->type_functions; + cl = attrs->ei_class; + + shnum = 0; + for (section = sobj->sections; section != NULL; section = section->next) + ++shnum; + if (shnum > 0) + { + /* Add a section header for the dummy section and one for + .shstrtab. */ + shnum += 2; + } + + ehdr_size = (cl == ELFCLASS32 + ? sizeof (Elf32_External_Ehdr) + : sizeof (Elf64_External_Ehdr)); + memset (buf, 0, sizeof (Elf64_External_Ehdr)); + + buf[EI_MAG0] = ELFMAG0; + buf[EI_MAG1] = ELFMAG1; + buf[EI_MAG2] = ELFMAG2; + buf[EI_MAG3] = ELFMAG3; + buf[EI_CLASS] = cl; + buf[EI_DATA] = attrs->ei_data; + buf[EI_VERSION] = EV_CURRENT; + buf[EI_OSABI] = attrs->ei_osabi; + + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_type, Elf_Half, ET_REL); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_machine, Elf_Half, attrs->machine); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_version, Elf_Word, EV_CURRENT); + /* e_entry left as zero. */ + /* e_phoff left as zero. */ + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_shoff, Elf_Addr, ehdr_size); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_flags, Elf_Word, attrs->flags); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_ehsize, Elf_Half, ehdr_size); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_phentsize, Elf_Half, + (cl == ELFCLASS32 + ? sizeof (Elf32_External_Phdr) + : sizeof (Elf64_External_Phdr))); + /* e_phnum left as zero. */ + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_shentsize, Elf_Half, + (cl == ELFCLASS32 + ? sizeof (Elf32_External_Shdr) + : sizeof (Elf64_External_Shdr))); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_shnum, Elf_Half, shnum); + ELF_SET_FIELD (fns, cl, Ehdr, buf, e_shstrndx, Elf_Half, + shnum == 0 ? 0 : shnum - 1); + + return simple_object_internal_write (descriptor, 0, buf, ehdr_size, + errmsg, err); +} + +/* Write out an ELF shdr. */ + +static int +simple_object_elf_write_shdr (simple_object_write *sobj, int descriptor, + off_t offset, unsigned int sh_name, + unsigned int sh_type, unsigned int sh_flags, + unsigned int sh_offset, unsigned int sh_size, + unsigned int sh_addralign, const char **errmsg, + int *err) +{ + struct simple_object_elf_attributes *attrs = + (struct simple_object_elf_attributes *) sobj->data; + const struct elf_type_functions* fns; + unsigned char cl; + size_t shdr_size; + unsigned char buf[sizeof (Elf64_External_Shdr)]; + + fns = attrs->type_functions; + cl = attrs->ei_class; + + shdr_size = (cl == ELFCLASS32 + ? sizeof (Elf32_External_Shdr) + : sizeof (Elf64_External_Shdr)); + memset (buf, 0, sizeof (Elf64_External_Shdr)); + + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_name, Elf_Word, sh_name); + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_type, Elf_Word, sh_type); + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_flags, Elf_Addr, sh_flags); + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_offset, Elf_Addr, sh_offset); + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_size, Elf_Addr, sh_size); + /* sh_link left as zero. */ + /* sh_info left as zero. */ + ELF_SET_FIELD (fns, cl, Shdr, buf, sh_addralign, Elf_Addr, sh_addralign); + /* sh_entsize left as zero. */ + + return simple_object_internal_write (descriptor, offset, buf, shdr_size, + errmsg, err); +} + +/* Write out a complete ELF file. + Ehdr + initial dummy Shdr + user-created Shdrs + .shstrtab Shdr + user-created section data + .shstrtab data */ + +static const char * +simple_object_elf_write_to_file (simple_object_write *sobj, int descriptor, + int *err) +{ + struct simple_object_elf_attributes *attrs = + (struct simple_object_elf_attributes *) sobj->data; + unsigned char cl; + size_t ehdr_size; + size_t shdr_size; + const char *errmsg; + simple_object_write_section *section; + unsigned int shnum; + size_t shdr_offset; + size_t sh_offset; + size_t sh_name; + unsigned char zero; + + if (!simple_object_elf_write_ehdr (sobj, descriptor, &errmsg, err)) + return errmsg; + + cl = attrs->ei_class; + if (cl == ELFCLASS32) + { + ehdr_size = sizeof (Elf32_External_Ehdr); + shdr_size = sizeof (Elf32_External_Shdr); + } + else + { + ehdr_size = sizeof (Elf64_External_Ehdr); + shdr_size = sizeof (Elf64_External_Shdr); + } + + shnum = 0; + for (section = sobj->sections; section != NULL; section = section->next) + ++shnum; + if (shnum == 0) + return NULL; + + /* Add initial dummy Shdr and .shstrtab. */ + shnum += 2; + + shdr_offset = ehdr_size; + sh_offset = shdr_offset + shnum * shdr_size; + + if (!simple_object_elf_write_shdr (sobj, descriptor, shdr_offset, + 0, 0, 0, 0, 0, 0, &errmsg, err)) + return errmsg; + + shdr_offset += shdr_size; + + sh_name = 1; + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t mask; + size_t new_sh_offset; + size_t sh_size; + struct simple_object_write_section_buffer *buffer; + + mask = (1U << section->align) - 1; + new_sh_offset = sh_offset + mask; + new_sh_offset &= ~ mask; + while (new_sh_offset > sh_offset) + { + unsigned char zeroes[16]; + size_t write; + + memset (zeroes, 0, sizeof zeroes); + write = new_sh_offset - sh_offset; + if (write > sizeof zeroes) + write = sizeof zeroes; + if (!simple_object_internal_write (descriptor, sh_offset, zeroes, + write, &errmsg, err)) + return errmsg; + sh_offset += write; + } + + sh_size = 0; + for (buffer = section->buffers; buffer != NULL; buffer = buffer->next) + { + if (!simple_object_internal_write (descriptor, sh_offset + sh_size, + ((const unsigned char *) + buffer->buffer), + buffer->size, &errmsg, err)) + return errmsg; + sh_size += buffer->size; + } + + if (!simple_object_elf_write_shdr (sobj, descriptor, shdr_offset, + sh_name, SHT_PROGBITS, 0, sh_offset, + sh_size, 1U << section->align, + &errmsg, err)) + return errmsg; + + shdr_offset += shdr_size; + sh_name += strlen (section->name) + 1; + sh_offset += sh_size; + } + + if (!simple_object_elf_write_shdr (sobj, descriptor, shdr_offset, + sh_name, SHT_STRTAB, 0, sh_offset, + sh_name + strlen (".shstrtab") + 1, + 1, &errmsg, err)) + return errmsg; + + /* .shstrtab has a leading zero byte. */ + zero = 0; + if (!simple_object_internal_write (descriptor, sh_offset, &zero, 1, + &errmsg, err)) + return errmsg; + ++sh_offset; + + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t len; + + len = strlen (section->name) + 1; + if (!simple_object_internal_write (descriptor, sh_offset, + (const unsigned char *) section->name, + len, &errmsg, err)) + return errmsg; + sh_offset += len; + } + + if (!simple_object_internal_write (descriptor, sh_offset, + (const unsigned char *) ".shstrtab", + strlen (".shstrtab") + 1, &errmsg, err)) + return errmsg; + + return NULL; +} + +/* Release the private data for an simple_object_write structure. */ + +static void +simple_object_elf_release_write (void *data) +{ + XDELETE (data); +} + +/* The ELF functions. */ + +const struct simple_object_functions simple_object_elf_functions = +{ + simple_object_elf_match, + simple_object_elf_find_sections, + simple_object_elf_fetch_attributes, + simple_object_elf_release_read, + simple_object_elf_attributes_merge, + simple_object_elf_release_attributes, + simple_object_elf_start_write, + simple_object_elf_write_to_file, + simple_object_elf_release_write +}; diff --git a/external/gpl3/gdb/dist/libiberty/simple-object-mach-o.c b/external/gpl3/gdb/dist/libiberty/simple-object-mach-o.c new file mode 100644 index 000000000000..bbbbd09de580 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object-mach-o.c @@ -0,0 +1,1022 @@ +/* simple-object-mach-o.c -- routines to manipulate Mach-O object files. + Copyright 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Google. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "simple-object.h" + +#include + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STDINT_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "simple-object-common.h" + +/* Mach-O structures and constants. */ + +/* Mach-O header (32-bit version). */ + +struct mach_o_header_32 +{ + unsigned char magic[4]; /* Magic number. */ + unsigned char cputype[4]; /* CPU that this object is for. */ + unsigned char cpusubtype[4]; /* CPU subtype. */ + unsigned char filetype[4]; /* Type of file. */ + unsigned char ncmds[4]; /* Number of load commands. */ + unsigned char sizeofcmds[4]; /* Total size of load commands. */ + unsigned char flags[4]; /* Flags for special featues. */ +}; + +/* Mach-O header (64-bit version). */ + +struct mach_o_header_64 +{ + unsigned char magic[4]; /* Magic number. */ + unsigned char cputype[4]; /* CPU that this object is for. */ + unsigned char cpusubtype[4]; /* CPU subtype. */ + unsigned char filetype[4]; /* Type of file. */ + unsigned char ncmds[4]; /* Number of load commands. */ + unsigned char sizeofcmds[4]; /* Total size of load commands. */ + unsigned char flags[4]; /* Flags for special featues. */ + unsigned char reserved[4]; /* Reserved. Duh. */ +}; + +/* For magic field in header. */ + +#define MACH_O_MH_MAGIC 0xfeedface +#define MACH_O_MH_MAGIC_64 0xfeedfacf + +/* For filetype field in header. */ + +#define MACH_O_MH_OBJECT 0x01 + +/* A Mach-O file is a list of load commands. This is the header of a + load command. */ + +struct mach_o_load_command +{ + unsigned char cmd[4]; /* The type of load command. */ + unsigned char cmdsize[4]; /* Size in bytes of entire command. */ +}; + +/* For cmd field in load command. */ + +#define MACH_O_LC_SEGMENT 0x01 +#define MACH_O_LC_SEGMENT_64 0x19 + +/* LC_SEGMENT load command. */ + +struct mach_o_segment_command_32 +{ + unsigned char cmd[4]; /* The type of load command (LC_SEGMENT). */ + unsigned char cmdsize[4]; /* Size in bytes of entire command. */ + unsigned char segname[16]; /* Name of this segment. */ + unsigned char vmaddr[4]; /* Virtual memory address of this segment. */ + unsigned char vmsize[4]; /* Size there, in bytes. */ + unsigned char fileoff[4]; /* Offset in bytes of the data to be mapped. */ + unsigned char filesize[4]; /* Size in bytes on disk. */ + unsigned char maxprot[4]; /* Maximum permitted vmem protection. */ + unsigned char initprot[4]; /* Initial vmem protection. */ + unsigned char nsects[4]; /* Number of sections in this segment. */ + unsigned char flags[4]; /* Flags that affect the loading. */ +}; + +/* LC_SEGMENT_64 load command. */ + +struct mach_o_segment_command_64 +{ + unsigned char cmd[4]; /* The type of load command (LC_SEGMENT_64). */ + unsigned char cmdsize[4]; /* Size in bytes of entire command. */ + unsigned char segname[16]; /* Name of this segment. */ + unsigned char vmaddr[8]; /* Virtual memory address of this segment. */ + unsigned char vmsize[8]; /* Size there, in bytes. */ + unsigned char fileoff[8]; /* Offset in bytes of the data to be mapped. */ + unsigned char filesize[8]; /* Size in bytes on disk. */ + unsigned char maxprot[4]; /* Maximum permitted vmem protection. */ + unsigned char initprot[4]; /* Initial vmem protection. */ + unsigned char nsects[4]; /* Number of sections in this segment. */ + unsigned char flags[4]; /* Flags that affect the loading. */ +}; + +/* 32-bit section header. */ + +struct mach_o_section_32 +{ + unsigned char sectname[16]; /* Section name. */ + unsigned char segname[16]; /* Segment that the section belongs to. */ + unsigned char addr[4]; /* Address of this section in memory. */ + unsigned char size[4]; /* Size in bytes of this section. */ + unsigned char offset[4]; /* File offset of this section. */ + unsigned char align[4]; /* log2 of this section's alignment. */ + unsigned char reloff[4]; /* File offset of this section's relocs. */ + unsigned char nreloc[4]; /* Number of relocs for this section. */ + unsigned char flags[4]; /* Section flags/attributes. */ + unsigned char reserved1[4]; + unsigned char reserved2[4]; +}; + +/* 64-bit section header. */ + +struct mach_o_section_64 +{ + unsigned char sectname[16]; /* Section name. */ + unsigned char segname[16]; /* Segment that the section belongs to. */ + unsigned char addr[8]; /* Address of this section in memory. */ + unsigned char size[8]; /* Size in bytes of this section. */ + unsigned char offset[4]; /* File offset of this section. */ + unsigned char align[4]; /* log2 of this section's alignment. */ + unsigned char reloff[4]; /* File offset of this section's relocs. */ + unsigned char nreloc[4]; /* Number of relocs for this section. */ + unsigned char flags[4]; /* Section flags/attributes. */ + unsigned char reserved1[4]; + unsigned char reserved2[4]; + unsigned char reserved3[4]; +}; + +/* Flags for Mach-O sections. */ + +#define MACH_O_S_ATTR_DEBUG 0x02000000 + +/* The length of a segment or section name. */ + +#define MACH_O_NAME_LEN (16) + +/* A GNU specific extension for long section names. */ + +#define GNU_SECTION_NAMES "__section_names" + +/* Private data for an simple_object_read. */ + +struct simple_object_mach_o_read +{ + /* User specified segment name. */ + char *segment_name; + /* Magic number. */ + unsigned int magic; + /* Whether this file is big-endian. */ + int is_big_endian; + /* CPU type from header. */ + unsigned int cputype; + /* CPU subtype from header. */ + unsigned int cpusubtype; + /* Number of commands, from header. */ + unsigned int ncmds; + /* Flags from header. */ + unsigned int flags; + /* Reserved field from header, only used on 64-bit. */ + unsigned int reserved; +}; + +/* Private data for an simple_object_attributes. */ + +struct simple_object_mach_o_attributes +{ + /* Magic number. */ + unsigned int magic; + /* Whether this file is big-endian. */ + int is_big_endian; + /* CPU type from header. */ + unsigned int cputype; + /* CPU subtype from header. */ + unsigned int cpusubtype; + /* Flags from header. */ + unsigned int flags; + /* Reserved field from header, only used on 64-bit. */ + unsigned int reserved; +}; + +/* See if we have a Mach-O file. */ + +static void * +simple_object_mach_o_match ( + unsigned char header[SIMPLE_OBJECT_MATCH_HEADER_LEN], + int descriptor, + off_t offset, + const char *segment_name, + const char **errmsg, + int *err) +{ + unsigned int magic; + int is_big_endian; + unsigned int (*fetch_32) (const unsigned char *); + unsigned int filetype; + struct simple_object_mach_o_read *omr; + unsigned char buf[sizeof (struct mach_o_header_64)]; + unsigned char *b; + + magic = simple_object_fetch_big_32 (header); + if (magic == MACH_O_MH_MAGIC || magic == MACH_O_MH_MAGIC_64) + is_big_endian = 1; + else + { + magic = simple_object_fetch_little_32 (header); + if (magic == MACH_O_MH_MAGIC || magic == MACH_O_MH_MAGIC_64) + is_big_endian = 0; + else + { + *errmsg = NULL; + *err = 0; + return NULL; + } + } + +#ifndef UNSIGNED_64BIT_TYPE + if (magic == MACH_O_MH_MAGIC_64) + { + *errmsg = "64-bit Mach-O objects not supported"; + *err = 0; + return NULL; + } +#endif + + /* We require the user to provide a segment name. This is + unfortunate but I don't see any good choices here. */ + + if (segment_name == NULL) + { + *errmsg = "Mach-O file found but no segment name specified"; + *err = 0; + return NULL; + } + + if (strlen (segment_name) > MACH_O_NAME_LEN) + { + *errmsg = "Mach-O segment name too long"; + *err = 0; + return NULL; + } + + /* The 32-bit and 64-bit headers are similar enough that we can use + the same code. */ + + fetch_32 = (is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + if (!simple_object_internal_read (descriptor, offset, buf, + (magic == MACH_O_MH_MAGIC + ? sizeof (struct mach_o_header_32) + : sizeof (struct mach_o_header_64)), + errmsg, err)) + return NULL; + + b = &buf[0]; + + filetype = (*fetch_32) (b + offsetof (struct mach_o_header_32, filetype)); + if (filetype != MACH_O_MH_OBJECT) + { + *errmsg = "Mach-O file is not object file"; + *err = 0; + return NULL; + } + + omr = XNEW (struct simple_object_mach_o_read); + omr->segment_name = xstrdup (segment_name); + omr->magic = magic; + omr->is_big_endian = is_big_endian; + omr->cputype = (*fetch_32) (b + offsetof (struct mach_o_header_32, cputype)); + omr->cpusubtype = (*fetch_32) (b + + offsetof (struct mach_o_header_32, + cpusubtype)); + omr->ncmds = (*fetch_32) (b + offsetof (struct mach_o_header_32, ncmds)); + omr->flags = (*fetch_32) (b + offsetof (struct mach_o_header_32, flags)); + if (magic == MACH_O_MH_MAGIC) + omr->reserved = 0; + else + omr->reserved = (*fetch_32) (b + + offsetof (struct mach_o_header_64, + reserved)); + + return (void *) omr; +} + +/* Get the file offset and size from a section header. */ + +static void +simple_object_mach_o_section_info (int is_big_endian, int is_32, + const unsigned char *sechdr, off_t *offset, + size_t *size) +{ + unsigned int (*fetch_32) (const unsigned char *); + ulong_type (*fetch_64) (const unsigned char *); + + fetch_32 = (is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + fetch_64 = NULL; +#ifdef UNSIGNED_64BIT_TYPE + fetch_64 = (is_big_endian + ? simple_object_fetch_big_64 + : simple_object_fetch_little_64); +#endif + + if (is_32) + { + *offset = fetch_32 (sechdr + + offsetof (struct mach_o_section_32, offset)); + *size = fetch_32 (sechdr + + offsetof (struct mach_o_section_32, size)); + } + else + { + *offset = fetch_32 (sechdr + + offsetof (struct mach_o_section_64, offset)); + *size = fetch_64 (sechdr + + offsetof (struct mach_o_section_64, size)); + } +} + +/* Handle a segment in a Mach-O file. Return 1 if we should continue, + 0 if the caller should return. */ + +static int +simple_object_mach_o_segment (simple_object_read *sobj, off_t offset, + const unsigned char *segbuf, + int (*pfn) (void *, const char *, off_t offset, + off_t length), + void *data, + const char **errmsg, int *err) +{ + struct simple_object_mach_o_read *omr = + (struct simple_object_mach_o_read *) sobj->data; + unsigned int (*fetch_32) (const unsigned char *); + int is_32; + size_t seghdrsize; + size_t sechdrsize; + size_t segname_offset; + size_t sectname_offset; + unsigned int nsects; + unsigned char *secdata; + unsigned int i; + unsigned int strtab_index; + char *strtab; + size_t strtab_size; + + fetch_32 = (omr->is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + is_32 = omr->magic == MACH_O_MH_MAGIC; + + if (is_32) + { + seghdrsize = sizeof (struct mach_o_segment_command_32); + sechdrsize = sizeof (struct mach_o_section_32); + segname_offset = offsetof (struct mach_o_section_32, segname); + sectname_offset = offsetof (struct mach_o_section_32, sectname); + nsects = (*fetch_32) (segbuf + + offsetof (struct mach_o_segment_command_32, + nsects)); + } + else + { + seghdrsize = sizeof (struct mach_o_segment_command_64); + sechdrsize = sizeof (struct mach_o_section_64); + segname_offset = offsetof (struct mach_o_section_64, segname); + sectname_offset = offsetof (struct mach_o_section_64, sectname); + nsects = (*fetch_32) (segbuf + + offsetof (struct mach_o_segment_command_64, + nsects)); + } + + secdata = XNEWVEC (unsigned char, nsects * sechdrsize); + if (!simple_object_internal_read (sobj->descriptor, offset + seghdrsize, + secdata, nsects * sechdrsize, errmsg, err)) + { + XDELETEVEC (secdata); + return 0; + } + + /* Scan for a __section_names section. This is in effect a GNU + extension that permits section names longer than 16 chars. */ + + for (i = 0; i < nsects; ++i) + { + size_t nameoff; + + nameoff = i * sechdrsize + segname_offset; + if (strcmp ((char *) secdata + nameoff, omr->segment_name) != 0) + continue; + nameoff = i * sechdrsize + sectname_offset; + if (strcmp ((char *) secdata + nameoff, GNU_SECTION_NAMES) == 0) + break; + } + + strtab_index = i; + if (strtab_index >= nsects) + { + strtab = NULL; + strtab_size = 0; + } + else + { + off_t strtab_offset; + + simple_object_mach_o_section_info (omr->is_big_endian, is_32, + secdata + strtab_index * sechdrsize, + &strtab_offset, &strtab_size); + strtab = XNEWVEC (char, strtab_size); + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + strtab_offset, + (unsigned char *) strtab, strtab_size, + errmsg, err)) + { + XDELETEVEC (strtab); + XDELETEVEC (secdata); + return 0; + } + } + + /* Process the sections. */ + + for (i = 0; i < nsects; ++i) + { + const unsigned char *sechdr; + char namebuf[MACH_O_NAME_LEN + 1]; + char *name; + off_t secoffset; + size_t secsize; + + if (i == strtab_index) + continue; + + sechdr = secdata + i * sechdrsize; + + if (strcmp ((char *) sechdr + segname_offset, omr->segment_name) != 0) + continue; + + memcpy (namebuf, sechdr + sectname_offset, MACH_O_NAME_LEN); + namebuf[MACH_O_NAME_LEN] = '\0'; + + name = &namebuf[0]; + if (strtab != NULL && name[0] == '_' && name[1] == '_') + { + unsigned long stringoffset; + + if (sscanf (name + 2, "%08lX", &stringoffset) == 1) + { + if (stringoffset >= strtab_size) + { + *errmsg = "section name offset out of range"; + *err = 0; + XDELETEVEC (strtab); + XDELETEVEC (secdata); + return 0; + } + + name = strtab + stringoffset; + } + } + + simple_object_mach_o_section_info (omr->is_big_endian, is_32, sechdr, + &secoffset, &secsize); + + if (!(*pfn) (data, name, secoffset, secsize)) + { + *errmsg = NULL; + *err = 0; + XDELETEVEC (strtab); + XDELETEVEC (secdata); + return 0; + } + } + + XDELETEVEC (strtab); + XDELETEVEC (secdata); + + return 1; +} + +/* Find all sections in a Mach-O file. */ + +static const char * +simple_object_mach_o_find_sections (simple_object_read *sobj, + int (*pfn) (void *, const char *, + off_t offset, off_t length), + void *data, + int *err) +{ + struct simple_object_mach_o_read *omr = + (struct simple_object_mach_o_read *) sobj->data; + off_t offset; + size_t seghdrsize; + unsigned int (*fetch_32) (const unsigned char *); + const char *errmsg; + unsigned int i; + + if (omr->magic == MACH_O_MH_MAGIC) + { + offset = sizeof (struct mach_o_header_32); + seghdrsize = sizeof (struct mach_o_segment_command_32); + } + else + { + offset = sizeof (struct mach_o_header_64); + seghdrsize = sizeof (struct mach_o_segment_command_64); + } + + fetch_32 = (omr->is_big_endian + ? simple_object_fetch_big_32 + : simple_object_fetch_little_32); + + for (i = 0; i < omr->ncmds; ++i) + { + unsigned char loadbuf[sizeof (struct mach_o_load_command)]; + unsigned int cmd; + unsigned int cmdsize; + + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + offset, + loadbuf, + sizeof (struct mach_o_load_command), + &errmsg, err)) + return errmsg; + + cmd = (*fetch_32) (loadbuf + offsetof (struct mach_o_load_command, cmd)); + cmdsize = (*fetch_32) (loadbuf + + offsetof (struct mach_o_load_command, cmdsize)); + + if (cmd == MACH_O_LC_SEGMENT || cmd == MACH_O_LC_SEGMENT_64) + { + unsigned char segbuf[sizeof (struct mach_o_segment_command_64)]; + int r; + + if (!simple_object_internal_read (sobj->descriptor, + sobj->offset + offset, + segbuf, seghdrsize, &errmsg, err)) + return errmsg; + + r = simple_object_mach_o_segment (sobj, offset, segbuf, pfn, + data, &errmsg, err); + if (!r) + return errmsg; + } + + offset += cmdsize; + } + + return NULL; +} + +/* Fetch the attributes for an simple_object_read. */ + +static void * +simple_object_mach_o_fetch_attributes (simple_object_read *sobj, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_mach_o_read *omr = + (struct simple_object_mach_o_read *) sobj->data; + struct simple_object_mach_o_attributes *ret; + + ret = XNEW (struct simple_object_mach_o_attributes); + ret->magic = omr->magic; + ret->is_big_endian = omr->is_big_endian; + ret->cputype = omr->cputype; + ret->cpusubtype = omr->cpusubtype; + ret->flags = omr->flags; + ret->reserved = omr->reserved; + return ret; +} + +/* Release the private data for an simple_object_read. */ + +static void +simple_object_mach_o_release_read (void *data) +{ + struct simple_object_mach_o_read *omr = + (struct simple_object_mach_o_read *) data; + + free (omr->segment_name); + XDELETE (omr); +} + +/* Compare two attributes structures. */ + +static const char * +simple_object_mach_o_attributes_merge (void *todata, void *fromdata, int *err) +{ + struct simple_object_mach_o_attributes *to = + (struct simple_object_mach_o_attributes *) todata; + struct simple_object_mach_o_attributes *from = + (struct simple_object_mach_o_attributes *) fromdata; + + if (to->magic != from->magic + || to->is_big_endian != from->is_big_endian + || to->cputype != from->cputype) + { + *err = 0; + return "Mach-O object format mismatch"; + } + return NULL; +} + +/* Release the private data for an attributes structure. */ + +static void +simple_object_mach_o_release_attributes (void *data) +{ + XDELETE (data); +} + +/* Prepare to write out a file. */ + +static void * +simple_object_mach_o_start_write (void *attributes_data, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_mach_o_attributes *attrs = + (struct simple_object_mach_o_attributes *) attributes_data; + struct simple_object_mach_o_attributes *ret; + + /* We're just going to record the attributes, but we need to make a + copy because the user may delete them. */ + ret = XNEW (struct simple_object_mach_o_attributes); + *ret = *attrs; + return ret; +} + +/* Write out the header of a Mach-O file. */ + +static int +simple_object_mach_o_write_header (simple_object_write *sobj, int descriptor, + size_t nsects, const char **errmsg, + int *err) +{ + struct simple_object_mach_o_attributes *attrs = + (struct simple_object_mach_o_attributes *) sobj->data; + void (*set_32) (unsigned char *, unsigned int); + unsigned char hdrbuf[sizeof (struct mach_o_header_64)]; + unsigned char *hdr; + size_t wrsize; + + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + memset (hdrbuf, 0, sizeof hdrbuf); + + /* The 32-bit and 64-bit headers start out the same. */ + + hdr = &hdrbuf[0]; + set_32 (hdr + offsetof (struct mach_o_header_32, magic), attrs->magic); + set_32 (hdr + offsetof (struct mach_o_header_32, cputype), attrs->cputype); + set_32 (hdr + offsetof (struct mach_o_header_32, cpusubtype), + attrs->cpusubtype); + set_32 (hdr + offsetof (struct mach_o_header_32, filetype), MACH_O_MH_OBJECT); + set_32 (hdr + offsetof (struct mach_o_header_32, ncmds), 1); + set_32 (hdr + offsetof (struct mach_o_header_32, flags), attrs->flags); + if (attrs->magic == MACH_O_MH_MAGIC) + { + wrsize = sizeof (struct mach_o_header_32); + set_32 (hdr + offsetof (struct mach_o_header_32, sizeofcmds), + (sizeof (struct mach_o_segment_command_32) + + nsects * sizeof (struct mach_o_section_32))); + } + else + { + set_32 (hdr + offsetof (struct mach_o_header_64, sizeofcmds), + (sizeof (struct mach_o_segment_command_64) + + nsects * sizeof (struct mach_o_section_64))); + set_32 (hdr + offsetof (struct mach_o_header_64, reserved), + attrs->reserved); + wrsize = sizeof (struct mach_o_header_64); + } + + return simple_object_internal_write (descriptor, 0, hdrbuf, wrsize, + errmsg, err); +} + +/* Write a Mach-O section header. */ + +static int +simple_object_mach_o_write_section_header (simple_object_write *sobj, + int descriptor, + size_t sechdr_offset, + const char *name, size_t secaddr, + size_t secsize, size_t offset, + unsigned int align, + const char **errmsg, int *err) +{ + struct simple_object_mach_o_attributes *attrs = + (struct simple_object_mach_o_attributes *) sobj->data; + void (*set_32) (unsigned char *, unsigned int); + unsigned char hdrbuf[sizeof (struct mach_o_section_64)]; + unsigned char *hdr; + size_t sechdrsize; + + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + memset (hdrbuf, 0, sizeof hdrbuf); + + hdr = &hdrbuf[0]; + if (attrs->magic == MACH_O_MH_MAGIC) + { + strncpy ((char *) hdr + offsetof (struct mach_o_section_32, sectname), + name, MACH_O_NAME_LEN); + strncpy ((char *) hdr + offsetof (struct mach_o_section_32, segname), + sobj->segment_name, MACH_O_NAME_LEN); + set_32 (hdr + offsetof (struct mach_o_section_32, addr), secaddr); + set_32 (hdr + offsetof (struct mach_o_section_32, size), secsize); + set_32 (hdr + offsetof (struct mach_o_section_32, offset), offset); + set_32 (hdr + offsetof (struct mach_o_section_32, align), align); + /* reloff left as zero. */ + /* nreloc left as zero. */ + set_32 (hdr + offsetof (struct mach_o_section_32, flags), + MACH_O_S_ATTR_DEBUG); + /* reserved1 left as zero. */ + /* reserved2 left as zero. */ + sechdrsize = sizeof (struct mach_o_section_32); + } + else + { +#ifdef UNSIGNED_64BIT_TYPE + void (*set_64) (unsigned char *, ulong_type); + + set_64 = (attrs->is_big_endian + ? simple_object_set_big_64 + : simple_object_set_little_64); + + strncpy ((char *) hdr + offsetof (struct mach_o_section_64, sectname), + name, MACH_O_NAME_LEN); + strncpy ((char *) hdr + offsetof (struct mach_o_section_64, segname), + sobj->segment_name, MACH_O_NAME_LEN); + set_64 (hdr + offsetof (struct mach_o_section_64, addr), secaddr); + set_64 (hdr + offsetof (struct mach_o_section_64, size), secsize); + set_32 (hdr + offsetof (struct mach_o_section_64, offset), offset); + set_32 (hdr + offsetof (struct mach_o_section_64, align), align); + /* reloff left as zero. */ + /* nreloc left as zero. */ + set_32 (hdr + offsetof (struct mach_o_section_64, flags), + MACH_O_S_ATTR_DEBUG); + /* reserved1 left as zero. */ + /* reserved2 left as zero. */ + /* reserved3 left as zero. */ +#endif + sechdrsize = sizeof (struct mach_o_section_64); + } + + return simple_object_internal_write (descriptor, sechdr_offset, hdr, + sechdrsize, errmsg, err); +} + +/* Write out the single segment and the sections of a Mach-O file. */ + +static int +simple_object_mach_o_write_segment (simple_object_write *sobj, int descriptor, + size_t nsects, const char **errmsg, + int *err) +{ + struct simple_object_mach_o_attributes *attrs = + (struct simple_object_mach_o_attributes *) sobj->data; + void (*set_32) (unsigned char *, unsigned int); + size_t hdrsize; + size_t seghdrsize; + size_t sechdrsize; + size_t cmdsize; + size_t offset; + size_t sechdr_offset; + size_t secaddr; + unsigned int name_offset; + simple_object_write_section *section; + unsigned char hdrbuf[sizeof (struct mach_o_segment_command_64)]; + unsigned char *hdr; + + set_32 = (attrs->is_big_endian + ? simple_object_set_big_32 + : simple_object_set_little_32); + + /* Write out the sections first. */ + + if (attrs->magic == MACH_O_MH_MAGIC) + { + hdrsize = sizeof (struct mach_o_header_32); + seghdrsize = sizeof (struct mach_o_segment_command_32); + sechdrsize = sizeof (struct mach_o_section_32); + } + else + { + hdrsize = sizeof (struct mach_o_header_64); + seghdrsize = sizeof (struct mach_o_segment_command_64); + sechdrsize = sizeof (struct mach_o_section_64); + } + + sechdr_offset = hdrsize + seghdrsize; + cmdsize = seghdrsize + nsects * sechdrsize; + offset = hdrsize + cmdsize; + name_offset = 0; + secaddr = 0; + + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t mask; + size_t new_offset; + size_t secsize; + struct simple_object_write_section_buffer *buffer; + char namebuf[MACH_O_NAME_LEN + 1]; + + mask = (1U << section->align) - 1; + new_offset = offset + mask; + new_offset &= ~ mask; + while (new_offset > offset) + { + unsigned char zeroes[16]; + size_t write; + + memset (zeroes, 0, sizeof zeroes); + write = new_offset - offset; + if (write > sizeof zeroes) + write = sizeof zeroes; + if (!simple_object_internal_write (descriptor, offset, zeroes, write, + errmsg, err)) + return 0; + offset += write; + } + + secsize = 0; + for (buffer = section->buffers; buffer != NULL; buffer = buffer->next) + { + if (!simple_object_internal_write (descriptor, offset + secsize, + ((const unsigned char *) + buffer->buffer), + buffer->size, errmsg, err)) + return 0; + secsize += buffer->size; + } + + snprintf (namebuf, sizeof namebuf, "__%08X", name_offset); + if (!simple_object_mach_o_write_section_header (sobj, descriptor, + sechdr_offset, namebuf, + secaddr, secsize, offset, + section->align, + errmsg, err)) + return 0; + + sechdr_offset += sechdrsize; + offset += secsize; + name_offset += strlen (section->name) + 1; + secaddr += secsize; + } + + /* Write out the section names. */ + + if (!simple_object_mach_o_write_section_header (sobj, descriptor, + sechdr_offset, + GNU_SECTION_NAMES, secaddr, + name_offset, offset, 0, + errmsg, err)) + return 0; + + for (section = sobj->sections; section != NULL; section = section->next) + { + size_t namelen; + + namelen = strlen (section->name) + 1; + if (!simple_object_internal_write (descriptor, offset, + (const unsigned char *) section->name, + namelen, errmsg, err)) + return 0; + offset += namelen; + } + + /* Write out the segment header. */ + + memset (hdrbuf, 0, sizeof hdrbuf); + + hdr = &hdrbuf[0]; + if (attrs->magic == MACH_O_MH_MAGIC) + { + set_32 (hdr + offsetof (struct mach_o_segment_command_32, cmd), + MACH_O_LC_SEGMENT); + set_32 (hdr + offsetof (struct mach_o_segment_command_32, cmdsize), + cmdsize); + strncpy (((char *) hdr + + offsetof (struct mach_o_segment_command_32, segname)), + sobj->segment_name, MACH_O_NAME_LEN); + /* vmaddr left as zero. */ + /* vmsize left as zero. */ + set_32 (hdr + offsetof (struct mach_o_segment_command_32, fileoff), + hdrsize + cmdsize); + set_32 (hdr + offsetof (struct mach_o_segment_command_32, filesize), + offset - (hdrsize + cmdsize)); + /* maxprot left as zero. */ + /* initprot left as zero. */ + set_32 (hdr + offsetof (struct mach_o_segment_command_32, nsects), + nsects); + /* flags left as zero. */ + } + else + { +#ifdef UNSIGNED_64BIT_TYPE + void (*set_64) (unsigned char *, ulong_type); + + set_64 = (attrs->is_big_endian + ? simple_object_set_big_64 + : simple_object_set_little_64); + + set_32 (hdr + offsetof (struct mach_o_segment_command_64, cmd), + MACH_O_LC_SEGMENT); + set_32 (hdr + offsetof (struct mach_o_segment_command_64, cmdsize), + cmdsize); + strncpy (((char *) hdr + + offsetof (struct mach_o_segment_command_64, segname)), + sobj->segment_name, MACH_O_NAME_LEN); + /* vmaddr left as zero. */ + /* vmsize left as zero. */ + set_64 (hdr + offsetof (struct mach_o_segment_command_64, fileoff), + hdrsize + cmdsize); + set_64 (hdr + offsetof (struct mach_o_segment_command_64, filesize), + offset - (hdrsize + cmdsize)); + /* maxprot left as zero. */ + /* initprot left as zero. */ + set_32 (hdr + offsetof (struct mach_o_segment_command_64, nsects), + nsects); + /* flags left as zero. */ +#endif + } + + return simple_object_internal_write (descriptor, hdrsize, hdr, seghdrsize, + errmsg, err); +} + +/* Write out a complete Mach-O file. */ + +static const char * +simple_object_mach_o_write_to_file (simple_object_write *sobj, int descriptor, + int *err) +{ + size_t nsects; + simple_object_write_section *section; + const char *errmsg; + + /* Start at 1 for symbol_names section. */ + nsects = 1; + for (section = sobj->sections; section != NULL; section = section->next) + ++nsects; + + if (!simple_object_mach_o_write_header (sobj, descriptor, nsects, + &errmsg, err)) + return errmsg; + + if (!simple_object_mach_o_write_segment (sobj, descriptor, nsects, + &errmsg, err)) + return errmsg; + + return NULL; +} + +/* Release the private data for an simple_object_write structure. */ + +static void +simple_object_mach_o_release_write (void *data) +{ + XDELETE (data); +} + +/* The Mach-O functions. */ + +const struct simple_object_functions simple_object_mach_o_functions = +{ + simple_object_mach_o_match, + simple_object_mach_o_find_sections, + simple_object_mach_o_fetch_attributes, + simple_object_mach_o_release_read, + simple_object_mach_o_attributes_merge, + simple_object_mach_o_release_attributes, + simple_object_mach_o_start_write, + simple_object_mach_o_write_to_file, + simple_object_mach_o_release_write +}; diff --git a/external/gpl3/gdb/dist/libiberty/simple-object.c b/external/gpl3/gdb/dist/libiberty/simple-object.c new file mode 100644 index 000000000000..d000cfc08067 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object.c @@ -0,0 +1,422 @@ +/* simple-object.c -- simple routines to read and write object files. + Copyright 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Google. + +This program is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include "libiberty.h" +#include "simple-object.h" + +#include + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STDINT_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#endif + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#ifndef SEEK_SET +#define SEEK_SET 0 +#endif + +#include "simple-object-common.h" + +/* The known object file formats. */ + +static const struct simple_object_functions * const format_functions[] = +{ + &simple_object_elf_functions, + &simple_object_mach_o_functions, + &simple_object_coff_functions +}; + +/* Read data from a file using the simple_object error reporting + conventions. */ + +int +simple_object_internal_read (int descriptor, off_t offset, + unsigned char *buffer, size_t size, + const char **errmsg, int *err) +{ + ssize_t got; + + if (lseek (descriptor, offset, SEEK_SET) < 0) + { + *errmsg = "lseek"; + *err = errno; + return 0; + } + + got = read (descriptor, buffer, size); + if (got < 0) + { + *errmsg = "read"; + *err = errno; + return 0; + } + + if ((size_t) got < size) + { + *errmsg = "file too short"; + *err = 0; + return 0; + } + + return 1; +} + +/* Write data to a file using the simple_object error reporting + conventions. */ + +int +simple_object_internal_write (int descriptor, off_t offset, + const unsigned char *buffer, size_t size, + const char **errmsg, int *err) +{ + ssize_t wrote; + + if (lseek (descriptor, offset, SEEK_SET) < 0) + { + *errmsg = "lseek"; + *err = errno; + return 0; + } + + wrote = write (descriptor, buffer, size); + if (wrote < 0) + { + *errmsg = "write"; + *err = errno; + return 0; + } + + if ((size_t) wrote < size) + { + *errmsg = "short write"; + *err = 0; + return 0; + } + + return 1; +} + +/* Open for read. */ + +simple_object_read * +simple_object_start_read (int descriptor, off_t offset, + const char *segment_name, const char **errmsg, + int *err) +{ + unsigned char header[SIMPLE_OBJECT_MATCH_HEADER_LEN]; + size_t len, i; + + if (!simple_object_internal_read (descriptor, offset, header, + SIMPLE_OBJECT_MATCH_HEADER_LEN, + errmsg, err)) + return NULL; + + len = sizeof (format_functions) / sizeof (format_functions[0]); + for (i = 0; i < len; ++i) + { + void *data; + + data = format_functions[i]->match (header, descriptor, offset, + segment_name, errmsg, err); + if (data != NULL) + { + simple_object_read *ret; + + ret = XNEW (simple_object_read); + ret->descriptor = descriptor; + ret->offset = offset; + ret->functions = format_functions[i]; + ret->data = data; + return ret; + } + } + + *errmsg = "file not recognized"; + *err = 0; + return NULL; +} + +/* Find all sections. */ + +const char * +simple_object_find_sections (simple_object_read *sobj, + int (*pfn) (void *, const char *, off_t, off_t), + void *data, + int *err) +{ + return sobj->functions->find_sections (sobj, pfn, data, err); +} + +/* Internal data passed to find_one_section. */ + +struct find_one_section_data +{ + /* The section we are looking for. */ + const char *name; + /* Where to store the section offset. */ + off_t *offset; + /* Where to store the section length. */ + off_t *length; + /* Set if the name is found. */ + int found; +}; + +/* Internal function passed to find_sections. */ + +static int +find_one_section (void *data, const char *name, off_t offset, off_t length) +{ + struct find_one_section_data *fosd = (struct find_one_section_data *) data; + + if (strcmp (name, fosd->name) != 0) + return 1; + + *fosd->offset = offset; + *fosd->length = length; + fosd->found = 1; + + /* Stop iteration. */ + return 0; +} + +/* Find a section. */ + +int +simple_object_find_section (simple_object_read *sobj, const char *name, + off_t *offset, off_t *length, + const char **errmsg, int *err) +{ + struct find_one_section_data fosd; + + fosd.name = name; + fosd.offset = offset; + fosd.length = length; + fosd.found = 0; + + *errmsg = simple_object_find_sections (sobj, find_one_section, + (void *) &fosd, err); + if (*errmsg != NULL) + return 0; + if (!fosd.found) + return 0; + return 1; +} + +/* Fetch attributes. */ + +simple_object_attributes * +simple_object_fetch_attributes (simple_object_read *sobj, const char **errmsg, + int *err) +{ + void *data; + simple_object_attributes *ret; + + data = sobj->functions->fetch_attributes (sobj, errmsg, err); + if (data == NULL) + return NULL; + ret = XNEW (simple_object_attributes); + ret->functions = sobj->functions; + ret->data = data; + return ret; +} + +/* Release an simple_object_read. */ + +void +simple_object_release_read (simple_object_read *sobj) +{ + sobj->functions->release_read (sobj->data); + XDELETE (sobj); +} + +/* Merge attributes. */ + +const char * +simple_object_attributes_merge (simple_object_attributes *to, + simple_object_attributes *from, + int *err) +{ + if (to->functions != from->functions) + { + *err = 0; + return "different object file format"; + } + return to->functions->attributes_merge (to->data, from->data, err); +} + +/* Release an attributes structure. */ + +void +simple_object_release_attributes (simple_object_attributes *attrs) +{ + attrs->functions->release_attributes (attrs->data); + XDELETE (attrs); +} + +/* Start creating an object file. */ + +simple_object_write * +simple_object_start_write (simple_object_attributes *attrs, + const char *segment_name, const char **errmsg, + int *err) +{ + void *data; + simple_object_write *ret; + + data = attrs->functions->start_write (attrs->data, errmsg, err); + if (data == NULL) + return NULL; + ret = XNEW (simple_object_write); + ret->functions = attrs->functions; + ret->segment_name = xstrdup (segment_name); + ret->sections = NULL; + ret->last_section = NULL; + ret->data = data; + return ret; +} + +/* Start creating a section. */ + +simple_object_write_section * +simple_object_write_create_section (simple_object_write *sobj, const char *name, + unsigned int align, + const char **errmsg ATTRIBUTE_UNUSED, + int *err ATTRIBUTE_UNUSED) +{ + simple_object_write_section *ret; + + ret = XNEW (simple_object_write_section); + ret->next = NULL; + ret->name = xstrdup (name); + ret->align = align; + ret->buffers = NULL; + ret->last_buffer = NULL; + + if (sobj->last_section == NULL) + { + sobj->sections = ret; + sobj->last_section = ret; + } + else + { + sobj->last_section->next = ret; + sobj->last_section = ret; + } + + return ret; +} + +/* Add data to a section. */ + +const char * +simple_object_write_add_data (simple_object_write *sobj ATTRIBUTE_UNUSED, + simple_object_write_section *section, + const void *buffer, + size_t size, int copy, + int *err ATTRIBUTE_UNUSED) +{ + struct simple_object_write_section_buffer *wsb; + + wsb = XNEW (struct simple_object_write_section_buffer); + wsb->next = NULL; + wsb->size = size; + + if (!copy) + { + wsb->buffer = buffer; + wsb->free_buffer = NULL; + } + else + { + wsb->free_buffer = (void *) XNEWVEC (char, size); + memcpy (wsb->free_buffer, buffer, size); + wsb->buffer = wsb->free_buffer; + } + + if (section->last_buffer == NULL) + { + section->buffers = wsb; + section->last_buffer = wsb; + } + else + { + section->last_buffer->next = wsb; + section->last_buffer = wsb; + } + + return NULL; +} + +/* Write the complete object file. */ + +const char * +simple_object_write_to_file (simple_object_write *sobj, int descriptor, + int *err) +{ + return sobj->functions->write_to_file (sobj, descriptor, err); +} + +/* Release an simple_object_write. */ + +void +simple_object_release_write (simple_object_write *sobj) +{ + simple_object_write_section *section; + + free (sobj->segment_name); + + section = sobj->sections; + while (section != NULL) + { + struct simple_object_write_section_buffer *buffer; + simple_object_write_section *next_section; + + buffer = section->buffers; + while (buffer != NULL) + { + struct simple_object_write_section_buffer *next_buffer; + + if (buffer->free_buffer != NULL) + XDELETEVEC (buffer->free_buffer); + next_buffer = buffer->next; + XDELETE (buffer); + buffer = next_buffer; + } + + next_section = section->next; + free (section->name); + XDELETE (section); + section = next_section; + } + + sobj->functions->release_write (sobj->data); + XDELETE (sobj); +} diff --git a/external/gpl3/gdb/dist/libiberty/simple-object.txh b/external/gpl3/gdb/dist/libiberty/simple-object.txh new file mode 100644 index 000000000000..34639f10a621 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/simple-object.txh @@ -0,0 +1,189 @@ +@c -*- mode: texinfo -*- +@deftypefn Extension {simple_object_read *} simple_object_open_read @ + (int @var{descriptor}, off_t @var{offset}, const char *{segment_name}, @ + const char **@var{errmsg}, int *@var{err}) + +Opens an object file for reading. Creates and returns an +@code{simple_object_read} pointer which may be passed to other +functions to extract data from the object file. + +@var{descriptor} holds a file descriptor which permits reading. + +@var{offset} is the offset into the file; this will be @code{0} in the +normal case, but may be a different value when reading an object file +in an archive file. + +@var{segment_name} is only used with the Mach-O file format used on +Darwin aka Mac OS X. It is required on that platform, and means to +only look at sections within the segment with that name. The +parameter is ignored on other systems. + +If an error occurs, this functions returns @code{NULL} and sets +@code{*@var{errmsg}} to an error string and sets @code{*@var{err}} to +an errno value or @code{0} if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {const char *} simple_object_find_sections @ + (simple_object_read *@var{simple_object}, int (*@var{pfn}) (void *@var{data}, @ + const char *@var{name}, off_t @var{offset}, off_t @var{length}), @ + void *@var{data}, int *@var{err}) + +This function calls @var{pfn} for each section in @var{simple_object}. +It calls @var{pfn} with the section name, the offset within the file +of the section contents, and the length of the section contents. The +offset within the file is relative to the offset passed to +@code{simple_object_open_read}. The @var{data} argument to this +function is passed along to @var{pfn}. + +If @var{pfn} returns @code{0}, the loop over the sections stops and +@code{simple_object_find_sections} returns. If @var{pfn} returns some +other value, the loop continues. + +On success @code{simple_object_find_sections} returns. On error it +returns an error string, and sets @code{*@var{err}} to an errno value +or @code{0} if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {int} simple_object_find_section @ + (simple_object_read *@var{simple_object} off_t *@var{offset}, @ + off_t *@var{length}, const char **@var{errmsg}, int *@var{err}) + +Look for the section @var{name} in @var{simple_object}. This returns +information for the first section with that name. + +If found, return 1 and set @code{*@var{offset}} to the offset in the +file of the section contents and set @code{*@var{length}} to the +length of the section contents. The value in @code{*@var{offset}} +will be relative to the offset passed to +@code{simple_object_open_read}. + +If the section is not found, and no error occurs, +@code{simple_object_find_section} returns @code{0} and set +@code{*@var{errmsg}} to @code{NULL}. + +If an error occurs, @code{simple_object_find_section} returns +@code{0}, sets @code{*@var{errmsg}} to an error message, and sets +@code{*@var{err}} to an errno value or @code{0} if there is no +relevant errno. + +@end deftypefn + +@deftypefn Extension {void} simple_object_release_read @ + (simple_object_read *@var{simple_object}) + +Release all resources associated with @var{simple_object}. This does +not close the file descriptor. + +@end deftypefn + +@deftypefn Extension {simple_object_attributes *} simple_object_fetch_attributes @ + (simple_object_read *@var{simple_object}, const char **@var{errmsg}, int *@var{err}) + +Fetch the attributes of @var{simple_object}. The attributes are +internal information such as the format of the object file, or the +architecture it was compiled for. This information will persist until +@code{simple_object_attributes_release} is called, even if +@var{simple_object} itself is released. + +On error this returns @code{NULL}, sets @code{*@var{errmsg}} to an +error message, and sets @code{*@var{err}} to an errno value or +@code{0} if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {const char *} simple_object_attributes_compare @ + (simple_object_attributes *@var{attrs1}, simple_object_attributes *@var{attrs2}, @ + int *@var{err}) + +Compare @var{attrs1} and @var{attrs2}. If they could be linked +together without error, return @code{NULL}. Otherwise, return an +error message and set @code{*@var{err}} to an errno value or @code{0} +if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {void} simple_object_release_attributes @ + (simple_object_attributes *@var{attrs}) + +Release all resources associated with @var{attrs}. + +@end deftypefn + +@deftypefn Extension {simple_object_write *} simple_object_start_write @ + (simple_object_attributes @var{attrs}, const char *@var{segment_name}, @ + const char **@var{errmsg}, int *@var{err}) + +Start creating a new object file using the object file format +described in @var{attrs}. You must fetch attribute information from +an existing object file before you can create a new one. There is +currently no support for creating an object file de novo. + +@var{segment_name} is only used with Mach-O as found on Darwin aka Mac +OS X. The parameter is required on that target. It means that all +sections are created within the named segment. It is ignored for +other object file formats. + +On error @code{simple_object_start_write} returns @code{NULL}, sets +@code{*@var{ERRMSG}} to an error message, and sets @code{*@var{err}} +to an errno value or @code{0} if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {simple_object_write_section *} simple_object_write_create_section @ + (simple_object_write *@var{simple_object}, const char *@var{name}, @ + unsigned int @var{align}, const char **@var{errmsg}, int *@var{err}) + +Add a section to @var{simple_object}. @var{name} is the name of the +new section. @var{align} is the required alignment expressed as the +number of required low-order 0 bits (e.g., 2 for alignment to a 32-bit +boundary). + +The section is created as containing data, readable, not writable, not +executable, not loaded at runtime. The section is not written to the +file until @code{simple_object_write_to_file} is called. + +On error this returns @code{NULL}, sets @code{*@var{errmsg}} to an +error message, and sets @code{*@var{err}} to an errno value or +@code{0} if there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {const char *} simple_object_write_add_data @ + (simple_object_write *@var{simple_object}, @ + simple_object_write_section *@var{section}, const void *@var{buffer}, @ + size_t @var{size}, int @var{copy}, int *@var{err}) + +Add data @var{buffer}/@var{size} to @var{section} in +@var{simple_object}. If @var{copy} is non-zero, the data will be +copied into memory if necessary. If @var{copy} is zero, @var{buffer} +must persist until @code{simple_object_write_to_file} is called. is +released. + +On success this returns @code{NULL}. On error this returns an error +message, and sets @code{*@var{err}} to an errno value or 0 if there is +no relevant erro. + +@end deftypefn + +@deftypefn Extension {const char *} simple_object_write_to_file @ + (simple_object_write *@var{simple_object}, int @var{descriptor}, int *@var{err}) + +Write the complete object file to @var{descriptor}, an open file +descriptor. This writes out all the data accumulated by calls to +@code{simple_object_write_create_section} and +@var{simple_object_write_add_data}. + +This returns @code{NULL} on success. On error this returns an error +message and sets @code{*@var{err}} to an errno value or @code{0} if +there is no relevant errno. + +@end deftypefn + +@deftypefn Extension {void} simple_object_release_write @ + (simple_object_write *@var{simple_object}) + +Release all resources associated with @var{simple_object}. + +@end deftypefn diff --git a/external/gpl3/gdb/dist/libiberty/snprintf.c b/external/gpl3/gdb/dist/libiberty/snprintf.c new file mode 100644 index 000000000000..1e3b03888e69 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/snprintf.c @@ -0,0 +1,63 @@ +/* Implement the snprintf function. + Copyright (C) 2003, 2011 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, @ + const char *@var{format}, ...) + +This function is similar to @code{sprintf}, but it will write to +@var{buf} at most @code{@var{n}-1} bytes of text, followed by a +terminating null byte, for a total of @var{n} bytes. +On error the return value is -1, otherwise it returns the number of +bytes, not including the terminating null byte, that would have been +written had @var{n} been sufficiently large, regardless of the actual +value of @var{n}. Note some pre-C99 system libraries do not implement +this correctly so users cannot generally rely on the return value if +the system version of this function is used. + +@end deftypefn + +*/ + +#include "ansidecl.h" + +#include +#include + +int vsnprintf (char *, size_t, const char *, va_list); + +int +snprintf (char *s, size_t n, const char *format, ...) +{ + int result; + VA_OPEN (ap, format); + VA_FIXEDARG (ap, char *, s); + VA_FIXEDARG (ap, size_t, n); + VA_FIXEDARG (ap, const char *, format); + result = vsnprintf (s, n, format, ap); + VA_CLOSE (ap); + return result; +} diff --git a/external/gpl3/gdb/dist/libiberty/sort.c b/external/gpl3/gdb/dist/libiberty/sort.c new file mode 100644 index 000000000000..3738dd733e58 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/sort.c @@ -0,0 +1,186 @@ +/* Sorting algorithms. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Mark Mitchell . + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "libiberty.h" +#include "sort.h" +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +#ifndef UCHAR_MAX +#define UCHAR_MAX ((unsigned char)(-1)) +#endif + +/* POINTERS and WORK are both arrays of N pointers. When this + function returns POINTERS will be sorted in ascending order. */ + +void sort_pointers (size_t n, void **pointers, void **work) +{ + /* The type of a single digit. This can be any unsigned integral + type. When changing this, DIGIT_MAX should be changed as + well. */ + typedef unsigned char digit_t; + + /* The maximum value a single digit can have. */ +#define DIGIT_MAX (UCHAR_MAX + 1) + + /* The Ith entry is the number of elements in *POINTERSP that have I + in the digit on which we are currently sorting. */ + unsigned int count[DIGIT_MAX]; + /* Nonzero if we are running on a big-endian machine. */ + int big_endian_p; + size_t i; + size_t j; + + /* The algorithm used here is radix sort which takes time linear in + the number of elements in the array. */ + + /* The algorithm here depends on being able to swap the two arrays + an even number of times. */ + if ((sizeof (void *) / sizeof (digit_t)) % 2 != 0) + abort (); + + /* Figure out the endianness of the machine. */ + for (i = 0, j = 0; i < sizeof (size_t); ++i) + { + j *= (UCHAR_MAX + 1); + j += i; + } + big_endian_p = (((char *)&j)[0] == 0); + + /* Move through the pointer values from least significant to most + significant digits. */ + for (i = 0; i < sizeof (void *) / sizeof (digit_t); ++i) + { + digit_t *digit; + digit_t *bias; + digit_t *top; + unsigned int *countp; + void **pointerp; + + /* The offset from the start of the pointer will depend on the + endianness of the machine. */ + if (big_endian_p) + j = sizeof (void *) / sizeof (digit_t) - i; + else + j = i; + + /* Now, perform a stable sort on this digit. We use counting + sort. */ + memset (count, 0, DIGIT_MAX * sizeof (unsigned int)); + + /* Compute the address of the appropriate digit in the first and + one-past-the-end elements of the array. On a little-endian + machine, the least-significant digit is closest to the front. */ + bias = ((digit_t *) pointers) + j; + top = ((digit_t *) (pointers + n)) + j; + + /* Count how many there are of each value. At the end of this + loop, COUNT[K] will contain the number of pointers whose Ith + digit is K. */ + for (digit = bias; + digit < top; + digit += sizeof (void *) / sizeof (digit_t)) + ++count[*digit]; + + /* Now, make COUNT[K] contain the number of pointers whose Ith + digit is less than or equal to K. */ + for (countp = count + 1; countp < count + DIGIT_MAX; ++countp) + *countp += countp[-1]; + + /* Now, drop the pointers into their correct locations. */ + for (pointerp = pointers + n - 1; pointerp >= pointers; --pointerp) + work[--count[((digit_t *) pointerp)[j]]] = *pointerp; + + /* Swap WORK and POINTERS so that POINTERS contains the sorted + array. */ + pointerp = pointers; + pointers = work; + work = pointerp; + } +} + +/* Everything below here is a unit test for the routines in this + file. */ + +#ifdef UNIT_TEST + +#include + +void *xmalloc (size_t n) +{ + return malloc (n); +} + +int main (int argc, char **argv) +{ + int k; + int result; + size_t i; + void **pointers; + void **work; + + if (argc > 1) + k = atoi (argv[1]); + else + k = 10; + + pointers = XNEWVEC (void*, k); + work = XNEWVEC (void*, k); + + for (i = 0; i < k; ++i) + { + pointers[i] = (void *) random (); + printf ("%x\n", pointers[i]); + } + + sort_pointers (k, pointers, work); + + printf ("\nSorted\n\n"); + + result = 0; + + for (i = 0; i < k; ++i) + { + printf ("%x\n", pointers[i]); + if (i > 0 && (char*) pointers[i] < (char*) pointers[i - 1]) + result = 1; + } + + free (pointers); + free (work); + + return result; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/spaces.c b/external/gpl3/gdb/dist/libiberty/spaces.c new file mode 100644 index 000000000000..67481c9bcd8f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/spaces.c @@ -0,0 +1,72 @@ +/* Allocate memory region filled with spaces. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Extension char* spaces (int @var{count}) + +Returns a pointer to a memory region filled with the specified +number of spaces and null terminated. The returned pointer is +valid until at least the next call. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" + +#if VMS +#include +#include +#else +/* For systems with larger pointers than ints, these must be declared. */ +extern PTR malloc (size_t); +extern void free (PTR); +#endif + +const char * +spaces (int count) +{ + register char *t; + static char *buf; + static int maxsize; + + if (count > maxsize) + { + if (buf) + { + free (buf); + } + buf = (char *) malloc (count + 1); + if (buf == (char *) 0) + return 0; + for (t = buf + count ; t != buf ; ) + { + *--t = ' '; + } + maxsize = count; + buf[count] = '\0'; + } + return (const char *) (buf + maxsize - count); +} + diff --git a/external/gpl3/gdb/dist/libiberty/splay-tree.c b/external/gpl3/gdb/dist/libiberty/splay-tree.c new file mode 100644 index 000000000000..12bfa8bbdcc9 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/splay-tree.c @@ -0,0 +1,593 @@ +/* A splay-tree datatype. + Copyright (C) 1998, 1999, 2000, 2001, 2009, + 2010, 2011 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* For an easily readable description of splay-trees, see: + + Lewis, Harry R. and Denenberg, Larry. Data Structures and Their + Algorithms. Harper-Collins, Inc. 1991. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#ifdef HAVE_STDLIB_H +#include +#endif + +#include + +#include "libiberty.h" +#include "splay-tree.h" + +static void splay_tree_delete_helper (splay_tree, splay_tree_node); +static inline void rotate_left (splay_tree_node *, + splay_tree_node, splay_tree_node); +static inline void rotate_right (splay_tree_node *, + splay_tree_node, splay_tree_node); +static void splay_tree_splay (splay_tree, splay_tree_key); +static int splay_tree_foreach_helper (splay_tree_node, + splay_tree_foreach_fn, void*); + +/* Deallocate NODE (a member of SP), and all its sub-trees. */ + +static void +splay_tree_delete_helper (splay_tree sp, splay_tree_node node) +{ + splay_tree_node pending = 0; + splay_tree_node active = 0; + + if (!node) + return; + +#define KDEL(x) if (sp->delete_key) (*sp->delete_key)(x); +#define VDEL(x) if (sp->delete_value) (*sp->delete_value)(x); + + KDEL (node->key); + VDEL (node->value); + + /* We use the "key" field to hold the "next" pointer. */ + node->key = (splay_tree_key)pending; + pending = (splay_tree_node)node; + + /* Now, keep processing the pending list until there aren't any + more. This is a little more complicated than just recursing, but + it doesn't toast the stack for large trees. */ + + while (pending) + { + active = pending; + pending = 0; + while (active) + { + splay_tree_node temp; + + /* active points to a node which has its key and value + deallocated, we just need to process left and right. */ + + if (active->left) + { + KDEL (active->left->key); + VDEL (active->left->value); + active->left->key = (splay_tree_key)pending; + pending = (splay_tree_node)(active->left); + } + if (active->right) + { + KDEL (active->right->key); + VDEL (active->right->value); + active->right->key = (splay_tree_key)pending; + pending = (splay_tree_node)(active->right); + } + + temp = active; + active = (splay_tree_node)(temp->key); + (*sp->deallocate) ((char*) temp, sp->allocate_data); + } + } +#undef KDEL +#undef VDEL +} + +/* Rotate the edge joining the left child N with its parent P. PP is the + grandparents' pointer to P. */ + +static inline void +rotate_left (splay_tree_node *pp, splay_tree_node p, splay_tree_node n) +{ + splay_tree_node tmp; + tmp = n->right; + n->right = p; + p->left = tmp; + *pp = n; +} + +/* Rotate the edge joining the right child N with its parent P. PP is the + grandparents' pointer to P. */ + +static inline void +rotate_right (splay_tree_node *pp, splay_tree_node p, splay_tree_node n) +{ + splay_tree_node tmp; + tmp = n->left; + n->left = p; + p->right = tmp; + *pp = n; +} + +/* Bottom up splay of key. */ + +static void +splay_tree_splay (splay_tree sp, splay_tree_key key) +{ + if (sp->root == 0) + return; + + do { + int cmp1, cmp2; + splay_tree_node n, c; + + n = sp->root; + cmp1 = (*sp->comp) (key, n->key); + + /* Found. */ + if (cmp1 == 0) + return; + + /* Left or right? If no child, then we're done. */ + if (cmp1 < 0) + c = n->left; + else + c = n->right; + if (!c) + return; + + /* Next one left or right? If found or no child, we're done + after one rotation. */ + cmp2 = (*sp->comp) (key, c->key); + if (cmp2 == 0 + || (cmp2 < 0 && !c->left) + || (cmp2 > 0 && !c->right)) + { + if (cmp1 < 0) + rotate_left (&sp->root, n, c); + else + rotate_right (&sp->root, n, c); + return; + } + + /* Now we have the four cases of double-rotation. */ + if (cmp1 < 0 && cmp2 < 0) + { + rotate_left (&n->left, c, c->left); + rotate_left (&sp->root, n, n->left); + } + else if (cmp1 > 0 && cmp2 > 0) + { + rotate_right (&n->right, c, c->right); + rotate_right (&sp->root, n, n->right); + } + else if (cmp1 < 0 && cmp2 > 0) + { + rotate_right (&n->left, c, c->right); + rotate_left (&sp->root, n, n->left); + } + else if (cmp1 > 0 && cmp2 < 0) + { + rotate_left (&n->right, c, c->left); + rotate_right (&sp->root, n, n->right); + } + } while (1); +} + +/* Call FN, passing it the DATA, for every node below NODE, all of + which are from SP, following an in-order traversal. If FN every + returns a non-zero value, the iteration ceases immediately, and the + value is returned. Otherwise, this function returns 0. */ + +static int +splay_tree_foreach_helper (splay_tree_node node, + splay_tree_foreach_fn fn, void *data) +{ + int val; + splay_tree_node *stack; + int stack_ptr, stack_size; + + /* A non-recursive implementation is used to avoid filling the stack + for large trees. Splay trees are worst case O(n) in the depth of + the tree. */ + +#define INITIAL_STACK_SIZE 100 + stack_size = INITIAL_STACK_SIZE; + stack_ptr = 0; + stack = XNEWVEC (splay_tree_node, stack_size); + val = 0; + + for (;;) + { + while (node != NULL) + { + if (stack_ptr == stack_size) + { + stack_size *= 2; + stack = XRESIZEVEC (splay_tree_node, stack, stack_size); + } + stack[stack_ptr++] = node; + node = node->left; + } + + if (stack_ptr == 0) + break; + + node = stack[--stack_ptr]; + + val = (*fn) (node, data); + if (val) + break; + + node = node->right; + } + + XDELETEVEC (stack); + return val; +} + +/* An allocator and deallocator based on xmalloc. */ +static void * +splay_tree_xmalloc_allocate (int size, void *data ATTRIBUTE_UNUSED) +{ + return (void *) xmalloc (size); +} + +static void +splay_tree_xmalloc_deallocate (void *object, void *data ATTRIBUTE_UNUSED) +{ + free (object); +} + + +/* Allocate a new splay tree, using COMPARE_FN to compare nodes, + DELETE_KEY_FN to deallocate keys, and DELETE_VALUE_FN to deallocate + values. Use xmalloc to allocate the splay tree structure, and any + nodes added. */ + +splay_tree +splay_tree_new (splay_tree_compare_fn compare_fn, + splay_tree_delete_key_fn delete_key_fn, + splay_tree_delete_value_fn delete_value_fn) +{ + return (splay_tree_new_with_allocator + (compare_fn, delete_key_fn, delete_value_fn, + splay_tree_xmalloc_allocate, splay_tree_xmalloc_deallocate, 0)); +} + + +/* Allocate a new splay tree, using COMPARE_FN to compare nodes, + DELETE_KEY_FN to deallocate keys, and DELETE_VALUE_FN to deallocate + values. */ + +splay_tree +splay_tree_new_with_allocator (splay_tree_compare_fn compare_fn, + splay_tree_delete_key_fn delete_key_fn, + splay_tree_delete_value_fn delete_value_fn, + splay_tree_allocate_fn allocate_fn, + splay_tree_deallocate_fn deallocate_fn, + void *allocate_data) +{ + return + splay_tree_new_typed_alloc (compare_fn, delete_key_fn, delete_value_fn, + allocate_fn, allocate_fn, deallocate_fn, + allocate_data); +} + +/* + +@deftypefn Supplemental splay_tree splay_tree_new_with_typed_alloc @ +(splay_tree_compare_fn @var{compare_fn}, @ +splay_tree_delete_key_fn @var{delete_key_fn}, @ +splay_tree_delete_value_fn @var{delete_value_fn}, @ +splay_tree_allocate_fn @var{tree_allocate_fn}, @ +splay_tree_allocate_fn @var{node_allocate_fn}, @ +splay_tree_deallocate_fn @var{deallocate_fn}, @ +void * @var{allocate_data}) + +This function creates a splay tree that uses two different allocators +@var{tree_allocate_fn} and @var{node_allocate_fn} to use for allocating the +tree itself and its nodes respectively. This is useful when variables of +different types need to be allocated with different allocators. + +The splay tree will use @var{compare_fn} to compare nodes, +@var{delete_key_fn} to deallocate keys, and @var{delete_value_fn} to +deallocate values. + +@end deftypefn + +*/ + +splay_tree +splay_tree_new_typed_alloc (splay_tree_compare_fn compare_fn, + splay_tree_delete_key_fn delete_key_fn, + splay_tree_delete_value_fn delete_value_fn, + splay_tree_allocate_fn tree_allocate_fn, + splay_tree_allocate_fn node_allocate_fn, + splay_tree_deallocate_fn deallocate_fn, + void * allocate_data) +{ + splay_tree sp = (splay_tree) (*tree_allocate_fn) + (sizeof (struct splay_tree_s), allocate_data); + + sp->root = 0; + sp->comp = compare_fn; + sp->delete_key = delete_key_fn; + sp->delete_value = delete_value_fn; + sp->allocate = node_allocate_fn; + sp->deallocate = deallocate_fn; + sp->allocate_data = allocate_data; + + return sp; +} + +/* Deallocate SP. */ + +void +splay_tree_delete (splay_tree sp) +{ + splay_tree_delete_helper (sp, sp->root); + (*sp->deallocate) ((char*) sp, sp->allocate_data); +} + +/* Insert a new node (associating KEY with DATA) into SP. If a + previous node with the indicated KEY exists, its data is replaced + with the new value. Returns the new node. */ + +splay_tree_node +splay_tree_insert (splay_tree sp, splay_tree_key key, splay_tree_value value) +{ + int comparison = 0; + + splay_tree_splay (sp, key); + + if (sp->root) + comparison = (*sp->comp)(sp->root->key, key); + + if (sp->root && comparison == 0) + { + /* If the root of the tree already has the indicated KEY, just + replace the value with VALUE. */ + if (sp->delete_value) + (*sp->delete_value)(sp->root->value); + sp->root->value = value; + } + else + { + /* Create a new node, and insert it at the root. */ + splay_tree_node node; + + node = ((splay_tree_node) + (*sp->allocate) (sizeof (struct splay_tree_node_s), + sp->allocate_data)); + node->key = key; + node->value = value; + + if (!sp->root) + node->left = node->right = 0; + else if (comparison < 0) + { + node->left = sp->root; + node->right = node->left->right; + node->left->right = 0; + } + else + { + node->right = sp->root; + node->left = node->right->left; + node->right->left = 0; + } + + sp->root = node; + } + + return sp->root; +} + +/* Remove KEY from SP. It is not an error if it did not exist. */ + +void +splay_tree_remove (splay_tree sp, splay_tree_key key) +{ + splay_tree_splay (sp, key); + + if (sp->root && (*sp->comp) (sp->root->key, key) == 0) + { + splay_tree_node left, right; + + left = sp->root->left; + right = sp->root->right; + + /* Delete the root node itself. */ + if (sp->delete_value) + (*sp->delete_value) (sp->root->value); + (*sp->deallocate) (sp->root, sp->allocate_data); + + /* One of the children is now the root. Doesn't matter much + which, so long as we preserve the properties of the tree. */ + if (left) + { + sp->root = left; + + /* If there was a right child as well, hang it off the + right-most leaf of the left child. */ + if (right) + { + while (left->right) + left = left->right; + left->right = right; + } + } + else + sp->root = right; + } +} + +/* Lookup KEY in SP, returning VALUE if present, and NULL + otherwise. */ + +splay_tree_node +splay_tree_lookup (splay_tree sp, splay_tree_key key) +{ + splay_tree_splay (sp, key); + + if (sp->root && (*sp->comp)(sp->root->key, key) == 0) + return sp->root; + else + return 0; +} + +/* Return the node in SP with the greatest key. */ + +splay_tree_node +splay_tree_max (splay_tree sp) +{ + splay_tree_node n = sp->root; + + if (!n) + return NULL; + + while (n->right) + n = n->right; + + return n; +} + +/* Return the node in SP with the smallest key. */ + +splay_tree_node +splay_tree_min (splay_tree sp) +{ + splay_tree_node n = sp->root; + + if (!n) + return NULL; + + while (n->left) + n = n->left; + + return n; +} + +/* Return the immediate predecessor KEY, or NULL if there is no + predecessor. KEY need not be present in the tree. */ + +splay_tree_node +splay_tree_predecessor (splay_tree sp, splay_tree_key key) +{ + int comparison; + splay_tree_node node; + + /* If the tree is empty, there is certainly no predecessor. */ + if (!sp->root) + return NULL; + + /* Splay the tree around KEY. That will leave either the KEY + itself, its predecessor, or its successor at the root. */ + splay_tree_splay (sp, key); + comparison = (*sp->comp)(sp->root->key, key); + + /* If the predecessor is at the root, just return it. */ + if (comparison < 0) + return sp->root; + + /* Otherwise, find the rightmost element of the left subtree. */ + node = sp->root->left; + if (node) + while (node->right) + node = node->right; + + return node; +} + +/* Return the immediate successor KEY, or NULL if there is no + successor. KEY need not be present in the tree. */ + +splay_tree_node +splay_tree_successor (splay_tree sp, splay_tree_key key) +{ + int comparison; + splay_tree_node node; + + /* If the tree is empty, there is certainly no successor. */ + if (!sp->root) + return NULL; + + /* Splay the tree around KEY. That will leave either the KEY + itself, its predecessor, or its successor at the root. */ + splay_tree_splay (sp, key); + comparison = (*sp->comp)(sp->root->key, key); + + /* If the successor is at the root, just return it. */ + if (comparison > 0) + return sp->root; + + /* Otherwise, find the leftmost element of the right subtree. */ + node = sp->root->right; + if (node) + while (node->left) + node = node->left; + + return node; +} + +/* Call FN, passing it the DATA, for every node in SP, following an + in-order traversal. If FN every returns a non-zero value, the + iteration ceases immediately, and the value is returned. + Otherwise, this function returns 0. */ + +int +splay_tree_foreach (splay_tree sp, splay_tree_foreach_fn fn, void *data) +{ + return splay_tree_foreach_helper (sp->root, fn, data); +} + +/* Splay-tree comparison function, treating the keys as ints. */ + +int +splay_tree_compare_ints (splay_tree_key k1, splay_tree_key k2) +{ + if ((int) k1 < (int) k2) + return -1; + else if ((int) k1 > (int) k2) + return 1; + else + return 0; +} + +/* Splay-tree comparison function, treating the keys as pointers. */ + +int +splay_tree_compare_pointers (splay_tree_key k1, splay_tree_key k2) +{ + if ((char*) k1 < (char*) k2) + return -1; + else if ((char*) k1 > (char*) k2) + return 1; + else + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/stpcpy.c b/external/gpl3/gdb/dist/libiberty/stpcpy.c new file mode 100644 index 000000000000..57b32d1c841a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/stpcpy.c @@ -0,0 +1,43 @@ +/* Implement the stpcpy function. + Copyright (C) 2003 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Supplemental char* stpcpy (char *@var{dst}, const char *@var{src}) + +Copies the string @var{src} into @var{dst}. Returns a pointer to +@var{dst} + strlen(@var{src}). + +@end deftypefn + +*/ + +#include +#include + +extern size_t strlen (const char *); +extern PTR memcpy (PTR, const PTR, size_t); + +char * +stpcpy (char *dst, const char *src) +{ + const size_t len = strlen (src); + return (char *) memcpy (dst, src, len + 1) + len; +} diff --git a/external/gpl3/gdb/dist/libiberty/stpncpy.c b/external/gpl3/gdb/dist/libiberty/stpncpy.c new file mode 100644 index 000000000000..83d54e60cb8e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/stpncpy.c @@ -0,0 +1,48 @@ +/* Implement the stpncpy function. + Copyright (C) 2003, 2011 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Supplemental char* stpncpy (char *@var{dst}, const char *@var{src}, @ + size_t @var{len}) + +Copies the string @var{src} into @var{dst}, copying exactly @var{len} +and padding with zeros if necessary. If @var{len} < strlen(@var{src}) +then return @var{dst} + @var{len}, otherwise returns @var{dst} + +strlen(@var{src}). + +@end deftypefn + +*/ + +#include +#include + +extern size_t strlen (const char *); +extern char *strncpy (char *, const char *, size_t); + +char * +stpncpy (char *dst, const char *src, size_t len) +{ + size_t n = strlen (src); + if (n > len) + n = len; + return strncpy (dst, src, len) + n; +} diff --git a/external/gpl3/gdb/dist/libiberty/strcasecmp.c b/external/gpl3/gdb/dist/libiberty/strcasecmp.c new file mode 100644 index 000000000000..131d81c2ce78 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strcasecmp.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 1987 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that this notice is preserved and that due credit is given + * to the University of California at Berkeley. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific written prior permission. This software + * is provided ``as is'' without express or implied warranty. + */ + +/* + +@deftypefn Supplemental int strcasecmp (const char *@var{s1}, const char *@var{s2}) + +A case-insensitive @code{strcmp}. + +@end deftypefn + +*/ + +#if defined(LIBC_SCCS) && !defined(lint) +static char sccsid[] = "@(#)strcasecmp.c 5.5 (Berkeley) 11/24/87"; +#endif /* LIBC_SCCS and not lint */ + +#include +#include + +/* + * This array is designed for mapping upper and lower case letter + * together for a case independent comparison. The mappings are + * based upon ascii character sequences. + */ +typedef unsigned char uc; +static const unsigned char charmap[] = { + (uc)'\000',(uc)'\001',(uc)'\002',(uc)'\003',(uc)'\004',(uc)'\005',(uc)'\006',(uc)'\007', + (uc)'\010',(uc)'\011',(uc)'\012',(uc)'\013',(uc)'\014',(uc)'\015',(uc)'\016',(uc)'\017', + (uc)'\020',(uc)'\021',(uc)'\022',(uc)'\023',(uc)'\024',(uc)'\025',(uc)'\026',(uc)'\027', + (uc)'\030',(uc)'\031',(uc)'\032',(uc)'\033',(uc)'\034',(uc)'\035',(uc)'\036',(uc)'\037', + (uc)'\040',(uc)'\041',(uc)'\042',(uc)'\043',(uc)'\044',(uc)'\045',(uc)'\046',(uc)'\047', + (uc)'\050',(uc)'\051',(uc)'\052',(uc)'\053',(uc)'\054',(uc)'\055',(uc)'\056',(uc)'\057', + (uc)'\060',(uc)'\061',(uc)'\062',(uc)'\063',(uc)'\064',(uc)'\065',(uc)'\066',(uc)'\067', + (uc)'\070',(uc)'\071',(uc)'\072',(uc)'\073',(uc)'\074',(uc)'\075',(uc)'\076',(uc)'\077', + (uc)'\100',(uc)'\141',(uc)'\142',(uc)'\143',(uc)'\144',(uc)'\145',(uc)'\146',(uc)'\147', + (uc)'\150',(uc)'\151',(uc)'\152',(uc)'\153',(uc)'\154',(uc)'\155',(uc)'\156',(uc)'\157', + (uc)'\160',(uc)'\161',(uc)'\162',(uc)'\163',(uc)'\164',(uc)'\165',(uc)'\166',(uc)'\167', + (uc)'\170',(uc)'\171',(uc)'\172',(uc)'\133',(uc)'\134',(uc)'\135',(uc)'\136',(uc)'\137', + (uc)'\140',(uc)'\141',(uc)'\142',(uc)'\143',(uc)'\144',(uc)'\145',(uc)'\146',(uc)'\147', + (uc)'\150',(uc)'\151',(uc)'\152',(uc)'\153',(uc)'\154',(uc)'\155',(uc)'\156',(uc)'\157', + (uc)'\160',(uc)'\161',(uc)'\162',(uc)'\163',(uc)'\164',(uc)'\165',(uc)'\166',(uc)'\167', + (uc)'\170',(uc)'\171',(uc)'\172',(uc)'\173',(uc)'\174',(uc)'\175',(uc)'\176',(uc)'\177', + (uc)'\200',(uc)'\201',(uc)'\202',(uc)'\203',(uc)'\204',(uc)'\205',(uc)'\206',(uc)'\207', + (uc)'\210',(uc)'\211',(uc)'\212',(uc)'\213',(uc)'\214',(uc)'\215',(uc)'\216',(uc)'\217', + (uc)'\220',(uc)'\221',(uc)'\222',(uc)'\223',(uc)'\224',(uc)'\225',(uc)'\226',(uc)'\227', + (uc)'\230',(uc)'\231',(uc)'\232',(uc)'\233',(uc)'\234',(uc)'\235',(uc)'\236',(uc)'\237', + (uc)'\240',(uc)'\241',(uc)'\242',(uc)'\243',(uc)'\244',(uc)'\245',(uc)'\246',(uc)'\247', + (uc)'\250',(uc)'\251',(uc)'\252',(uc)'\253',(uc)'\254',(uc)'\255',(uc)'\256',(uc)'\257', + (uc)'\260',(uc)'\261',(uc)'\262',(uc)'\263',(uc)'\264',(uc)'\265',(uc)'\266',(uc)'\267', + (uc)'\270',(uc)'\271',(uc)'\272',(uc)'\273',(uc)'\274',(uc)'\275',(uc)'\276',(uc)'\277', + (uc)'\300',(uc)'\341',(uc)'\342',(uc)'\343',(uc)'\344',(uc)'\345',(uc)'\346',(uc)'\347', + (uc)'\350',(uc)'\351',(uc)'\352',(uc)'\353',(uc)'\354',(uc)'\355',(uc)'\356',(uc)'\357', + (uc)'\360',(uc)'\361',(uc)'\362',(uc)'\363',(uc)'\364',(uc)'\365',(uc)'\366',(uc)'\367', + (uc)'\370',(uc)'\371',(uc)'\372',(uc)'\333',(uc)'\334',(uc)'\335',(uc)'\336',(uc)'\337', + (uc)'\340',(uc)'\341',(uc)'\342',(uc)'\343',(uc)'\344',(uc)'\345',(uc)'\346',(uc)'\347', + (uc)'\350',(uc)'\351',(uc)'\352',(uc)'\353',(uc)'\354',(uc)'\355',(uc)'\356',(uc)'\357', + (uc)'\360',(uc)'\361',(uc)'\362',(uc)'\363',(uc)'\364',(uc)'\365',(uc)'\366',(uc)'\367', + (uc)'\370',(uc)'\371',(uc)'\372',(uc)'\373',(uc)'\374',(uc)'\375',(uc)'\376',(uc)'\377', +}; + +int +strcasecmp(const char *s1, const char *s2) +{ + register unsigned char u1, u2; + + for (;;) { + u1 = (unsigned char) *s1++; + u2 = (unsigned char) *s2++; + if (charmap[u1] != charmap[u2]) { + return charmap[u1] - charmap[u2]; + } + if (u1 == '\0') { + return 0; + } + } +} + diff --git a/external/gpl3/gdb/dist/libiberty/strchr.c b/external/gpl3/gdb/dist/libiberty/strchr.c new file mode 100644 index 000000000000..935805ef4f4d --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strchr.c @@ -0,0 +1,28 @@ +/* Portable version of strchr() + This function is in the public domain. */ + +/* + +@deftypefn Supplemental char* strchr (const char *@var{s}, int @var{c}) + +Returns a pointer to the first occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. If @var{c} is itself the +null character, the results are undefined. + +@end deftypefn + +*/ + +#include + +char * +strchr (register const char *s, int c) +{ + do { + if (*s == c) + { + return (char*)s; + } + } while (*s++); + return (0); +} diff --git a/external/gpl3/gdb/dist/libiberty/strdup.c b/external/gpl3/gdb/dist/libiberty/strdup.c new file mode 100644 index 000000000000..78c2093b61a3 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strdup.c @@ -0,0 +1,27 @@ +/* + +@deftypefn Supplemental char* strdup (const char *@var{s}) + +Returns a pointer to a copy of @var{s} in memory obtained from +@code{malloc}, or @code{NULL} if insufficient memory was available. + +@end deftypefn + +*/ + +#include +#include + +extern size_t strlen (const char*); +extern PTR malloc (size_t); +extern PTR memcpy (PTR, const PTR, size_t); + +char * +strdup(const char *s) +{ + size_t len = strlen (s) + 1; + char *result = (char*) malloc (len); + if (result == (char*) 0) + return (char*) 0; + return (char*) memcpy (result, s, len); +} diff --git a/external/gpl3/gdb/dist/libiberty/strerror.c b/external/gpl3/gdb/dist/libiberty/strerror.c new file mode 100644 index 000000000000..0efadc3d65eb --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strerror.c @@ -0,0 +1,809 @@ +/* Extended support for using errno values. + Written by Fred Fish. fnf@cygnus.com + This file is in the public domain. --Per Bothner. */ + +#include "config.h" + +#ifdef HAVE_SYS_ERRLIST +/* Note that errno.h (not sure what OS) or stdio.h (BSD 4.4, at least) + might declare sys_errlist in a way that the compiler might consider + incompatible with our later declaration, perhaps by using const + attributes. So we hide the declaration in errno.h (if any) using a + macro. */ +#define sys_nerr sys_nerr__ +#define sys_errlist sys_errlist__ +#endif + +#include "ansidecl.h" +#include "libiberty.h" + +#include +#include + +#ifdef HAVE_SYS_ERRLIST +#undef sys_nerr +#undef sys_errlist +#endif + +/* Routines imported from standard C runtime libraries. */ + +#ifdef HAVE_STDLIB_H +#include +#else +extern PTR malloc (); +#endif + +#ifdef HAVE_STRING_H +#include +#else +extern PTR memset (); +#endif + +#ifndef MAX +# define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +static void init_error_tables (void); + +/* Translation table for errno values. See intro(2) in most UNIX systems + Programmers Reference Manuals. + + Note that this table is generally only accessed when it is used at runtime + to initialize errno name and message tables that are indexed by errno + value. + + Not all of these errnos will exist on all systems. This table is the only + thing that should have to be updated as new error numbers are introduced. + It's sort of ugly, but at least its portable. */ + +struct error_info +{ + const int value; /* The numeric value from */ + const char *const name; /* The equivalent symbolic value */ +#ifndef HAVE_SYS_ERRLIST + const char *const msg; /* Short message about this value */ +#endif +}; + +#ifndef HAVE_SYS_ERRLIST +# define ENTRY(value, name, msg) {value, name, msg} +#else +# define ENTRY(value, name, msg) {value, name} +#endif + +static const struct error_info error_table[] = +{ +#if defined (EPERM) + ENTRY(EPERM, "EPERM", "Not owner"), +#endif +#if defined (ENOENT) + ENTRY(ENOENT, "ENOENT", "No such file or directory"), +#endif +#if defined (ESRCH) + ENTRY(ESRCH, "ESRCH", "No such process"), +#endif +#if defined (EINTR) + ENTRY(EINTR, "EINTR", "Interrupted system call"), +#endif +#if defined (EIO) + ENTRY(EIO, "EIO", "I/O error"), +#endif +#if defined (ENXIO) + ENTRY(ENXIO, "ENXIO", "No such device or address"), +#endif +#if defined (E2BIG) + ENTRY(E2BIG, "E2BIG", "Arg list too long"), +#endif +#if defined (ENOEXEC) + ENTRY(ENOEXEC, "ENOEXEC", "Exec format error"), +#endif +#if defined (EBADF) + ENTRY(EBADF, "EBADF", "Bad file number"), +#endif +#if defined (ECHILD) + ENTRY(ECHILD, "ECHILD", "No child processes"), +#endif +#if defined (EWOULDBLOCK) /* Put before EAGAIN, sometimes aliased */ + ENTRY(EWOULDBLOCK, "EWOULDBLOCK", "Operation would block"), +#endif +#if defined (EAGAIN) + ENTRY(EAGAIN, "EAGAIN", "No more processes"), +#endif +#if defined (ENOMEM) + ENTRY(ENOMEM, "ENOMEM", "Not enough space"), +#endif +#if defined (EACCES) + ENTRY(EACCES, "EACCES", "Permission denied"), +#endif +#if defined (EFAULT) + ENTRY(EFAULT, "EFAULT", "Bad address"), +#endif +#if defined (ENOTBLK) + ENTRY(ENOTBLK, "ENOTBLK", "Block device required"), +#endif +#if defined (EBUSY) + ENTRY(EBUSY, "EBUSY", "Device busy"), +#endif +#if defined (EEXIST) + ENTRY(EEXIST, "EEXIST", "File exists"), +#endif +#if defined (EXDEV) + ENTRY(EXDEV, "EXDEV", "Cross-device link"), +#endif +#if defined (ENODEV) + ENTRY(ENODEV, "ENODEV", "No such device"), +#endif +#if defined (ENOTDIR) + ENTRY(ENOTDIR, "ENOTDIR", "Not a directory"), +#endif +#if defined (EISDIR) + ENTRY(EISDIR, "EISDIR", "Is a directory"), +#endif +#if defined (EINVAL) + ENTRY(EINVAL, "EINVAL", "Invalid argument"), +#endif +#if defined (ENFILE) + ENTRY(ENFILE, "ENFILE", "File table overflow"), +#endif +#if defined (EMFILE) + ENTRY(EMFILE, "EMFILE", "Too many open files"), +#endif +#if defined (ENOTTY) + ENTRY(ENOTTY, "ENOTTY", "Not a typewriter"), +#endif +#if defined (ETXTBSY) + ENTRY(ETXTBSY, "ETXTBSY", "Text file busy"), +#endif +#if defined (EFBIG) + ENTRY(EFBIG, "EFBIG", "File too large"), +#endif +#if defined (ENOSPC) + ENTRY(ENOSPC, "ENOSPC", "No space left on device"), +#endif +#if defined (ESPIPE) + ENTRY(ESPIPE, "ESPIPE", "Illegal seek"), +#endif +#if defined (EROFS) + ENTRY(EROFS, "EROFS", "Read-only file system"), +#endif +#if defined (EMLINK) + ENTRY(EMLINK, "EMLINK", "Too many links"), +#endif +#if defined (EPIPE) + ENTRY(EPIPE, "EPIPE", "Broken pipe"), +#endif +#if defined (EDOM) + ENTRY(EDOM, "EDOM", "Math argument out of domain of func"), +#endif +#if defined (ERANGE) + ENTRY(ERANGE, "ERANGE", "Math result not representable"), +#endif +#if defined (ENOMSG) + ENTRY(ENOMSG, "ENOMSG", "No message of desired type"), +#endif +#if defined (EIDRM) + ENTRY(EIDRM, "EIDRM", "Identifier removed"), +#endif +#if defined (ECHRNG) + ENTRY(ECHRNG, "ECHRNG", "Channel number out of range"), +#endif +#if defined (EL2NSYNC) + ENTRY(EL2NSYNC, "EL2NSYNC", "Level 2 not synchronized"), +#endif +#if defined (EL3HLT) + ENTRY(EL3HLT, "EL3HLT", "Level 3 halted"), +#endif +#if defined (EL3RST) + ENTRY(EL3RST, "EL3RST", "Level 3 reset"), +#endif +#if defined (ELNRNG) + ENTRY(ELNRNG, "ELNRNG", "Link number out of range"), +#endif +#if defined (EUNATCH) + ENTRY(EUNATCH, "EUNATCH", "Protocol driver not attached"), +#endif +#if defined (ENOCSI) + ENTRY(ENOCSI, "ENOCSI", "No CSI structure available"), +#endif +#if defined (EL2HLT) + ENTRY(EL2HLT, "EL2HLT", "Level 2 halted"), +#endif +#if defined (EDEADLK) + ENTRY(EDEADLK, "EDEADLK", "Deadlock condition"), +#endif +#if defined (ENOLCK) + ENTRY(ENOLCK, "ENOLCK", "No record locks available"), +#endif +#if defined (EBADE) + ENTRY(EBADE, "EBADE", "Invalid exchange"), +#endif +#if defined (EBADR) + ENTRY(EBADR, "EBADR", "Invalid request descriptor"), +#endif +#if defined (EXFULL) + ENTRY(EXFULL, "EXFULL", "Exchange full"), +#endif +#if defined (ENOANO) + ENTRY(ENOANO, "ENOANO", "No anode"), +#endif +#if defined (EBADRQC) + ENTRY(EBADRQC, "EBADRQC", "Invalid request code"), +#endif +#if defined (EBADSLT) + ENTRY(EBADSLT, "EBADSLT", "Invalid slot"), +#endif +#if defined (EDEADLOCK) + ENTRY(EDEADLOCK, "EDEADLOCK", "File locking deadlock error"), +#endif +#if defined (EBFONT) + ENTRY(EBFONT, "EBFONT", "Bad font file format"), +#endif +#if defined (ENOSTR) + ENTRY(ENOSTR, "ENOSTR", "Device not a stream"), +#endif +#if defined (ENODATA) + ENTRY(ENODATA, "ENODATA", "No data available"), +#endif +#if defined (ETIME) + ENTRY(ETIME, "ETIME", "Timer expired"), +#endif +#if defined (ENOSR) + ENTRY(ENOSR, "ENOSR", "Out of streams resources"), +#endif +#if defined (ENONET) + ENTRY(ENONET, "ENONET", "Machine is not on the network"), +#endif +#if defined (ENOPKG) + ENTRY(ENOPKG, "ENOPKG", "Package not installed"), +#endif +#if defined (EREMOTE) + ENTRY(EREMOTE, "EREMOTE", "Object is remote"), +#endif +#if defined (ENOLINK) + ENTRY(ENOLINK, "ENOLINK", "Link has been severed"), +#endif +#if defined (EADV) + ENTRY(EADV, "EADV", "Advertise error"), +#endif +#if defined (ESRMNT) + ENTRY(ESRMNT, "ESRMNT", "Srmount error"), +#endif +#if defined (ECOMM) + ENTRY(ECOMM, "ECOMM", "Communication error on send"), +#endif +#if defined (EPROTO) + ENTRY(EPROTO, "EPROTO", "Protocol error"), +#endif +#if defined (EMULTIHOP) + ENTRY(EMULTIHOP, "EMULTIHOP", "Multihop attempted"), +#endif +#if defined (EDOTDOT) + ENTRY(EDOTDOT, "EDOTDOT", "RFS specific error"), +#endif +#if defined (EBADMSG) + ENTRY(EBADMSG, "EBADMSG", "Not a data message"), +#endif +#if defined (ENAMETOOLONG) + ENTRY(ENAMETOOLONG, "ENAMETOOLONG", "File name too long"), +#endif +#if defined (EOVERFLOW) + ENTRY(EOVERFLOW, "EOVERFLOW", "Value too large for defined data type"), +#endif +#if defined (ENOTUNIQ) + ENTRY(ENOTUNIQ, "ENOTUNIQ", "Name not unique on network"), +#endif +#if defined (EBADFD) + ENTRY(EBADFD, "EBADFD", "File descriptor in bad state"), +#endif +#if defined (EREMCHG) + ENTRY(EREMCHG, "EREMCHG", "Remote address changed"), +#endif +#if defined (ELIBACC) + ENTRY(ELIBACC, "ELIBACC", "Can not access a needed shared library"), +#endif +#if defined (ELIBBAD) + ENTRY(ELIBBAD, "ELIBBAD", "Accessing a corrupted shared library"), +#endif +#if defined (ELIBSCN) + ENTRY(ELIBSCN, "ELIBSCN", ".lib section in a.out corrupted"), +#endif +#if defined (ELIBMAX) + ENTRY(ELIBMAX, "ELIBMAX", "Attempting to link in too many shared libraries"), +#endif +#if defined (ELIBEXEC) + ENTRY(ELIBEXEC, "ELIBEXEC", "Cannot exec a shared library directly"), +#endif +#if defined (EILSEQ) + ENTRY(EILSEQ, "EILSEQ", "Illegal byte sequence"), +#endif +#if defined (ENOSYS) + ENTRY(ENOSYS, "ENOSYS", "Operation not applicable"), +#endif +#if defined (ELOOP) + ENTRY(ELOOP, "ELOOP", "Too many symbolic links encountered"), +#endif +#if defined (ERESTART) + ENTRY(ERESTART, "ERESTART", "Interrupted system call should be restarted"), +#endif +#if defined (ESTRPIPE) + ENTRY(ESTRPIPE, "ESTRPIPE", "Streams pipe error"), +#endif +#if defined (ENOTEMPTY) + ENTRY(ENOTEMPTY, "ENOTEMPTY", "Directory not empty"), +#endif +#if defined (EUSERS) + ENTRY(EUSERS, "EUSERS", "Too many users"), +#endif +#if defined (ENOTSOCK) + ENTRY(ENOTSOCK, "ENOTSOCK", "Socket operation on non-socket"), +#endif +#if defined (EDESTADDRREQ) + ENTRY(EDESTADDRREQ, "EDESTADDRREQ", "Destination address required"), +#endif +#if defined (EMSGSIZE) + ENTRY(EMSGSIZE, "EMSGSIZE", "Message too long"), +#endif +#if defined (EPROTOTYPE) + ENTRY(EPROTOTYPE, "EPROTOTYPE", "Protocol wrong type for socket"), +#endif +#if defined (ENOPROTOOPT) + ENTRY(ENOPROTOOPT, "ENOPROTOOPT", "Protocol not available"), +#endif +#if defined (EPROTONOSUPPORT) + ENTRY(EPROTONOSUPPORT, "EPROTONOSUPPORT", "Protocol not supported"), +#endif +#if defined (ESOCKTNOSUPPORT) + ENTRY(ESOCKTNOSUPPORT, "ESOCKTNOSUPPORT", "Socket type not supported"), +#endif +#if defined (EOPNOTSUPP) + ENTRY(EOPNOTSUPP, "EOPNOTSUPP", "Operation not supported on transport endpoint"), +#endif +#if defined (EPFNOSUPPORT) + ENTRY(EPFNOSUPPORT, "EPFNOSUPPORT", "Protocol family not supported"), +#endif +#if defined (EAFNOSUPPORT) + ENTRY(EAFNOSUPPORT, "EAFNOSUPPORT", "Address family not supported by protocol"), +#endif +#if defined (EADDRINUSE) + ENTRY(EADDRINUSE, "EADDRINUSE", "Address already in use"), +#endif +#if defined (EADDRNOTAVAIL) + ENTRY(EADDRNOTAVAIL, "EADDRNOTAVAIL","Cannot assign requested address"), +#endif +#if defined (ENETDOWN) + ENTRY(ENETDOWN, "ENETDOWN", "Network is down"), +#endif +#if defined (ENETUNREACH) + ENTRY(ENETUNREACH, "ENETUNREACH", "Network is unreachable"), +#endif +#if defined (ENETRESET) + ENTRY(ENETRESET, "ENETRESET", "Network dropped connection because of reset"), +#endif +#if defined (ECONNABORTED) + ENTRY(ECONNABORTED, "ECONNABORTED", "Software caused connection abort"), +#endif +#if defined (ECONNRESET) + ENTRY(ECONNRESET, "ECONNRESET", "Connection reset by peer"), +#endif +#if defined (ENOBUFS) + ENTRY(ENOBUFS, "ENOBUFS", "No buffer space available"), +#endif +#if defined (EISCONN) + ENTRY(EISCONN, "EISCONN", "Transport endpoint is already connected"), +#endif +#if defined (ENOTCONN) + ENTRY(ENOTCONN, "ENOTCONN", "Transport endpoint is not connected"), +#endif +#if defined (ESHUTDOWN) + ENTRY(ESHUTDOWN, "ESHUTDOWN", "Cannot send after transport endpoint shutdown"), +#endif +#if defined (ETOOMANYREFS) + ENTRY(ETOOMANYREFS, "ETOOMANYREFS", "Too many references: cannot splice"), +#endif +#if defined (ETIMEDOUT) + ENTRY(ETIMEDOUT, "ETIMEDOUT", "Connection timed out"), +#endif +#if defined (ECONNREFUSED) + ENTRY(ECONNREFUSED, "ECONNREFUSED", "Connection refused"), +#endif +#if defined (EHOSTDOWN) + ENTRY(EHOSTDOWN, "EHOSTDOWN", "Host is down"), +#endif +#if defined (EHOSTUNREACH) + ENTRY(EHOSTUNREACH, "EHOSTUNREACH", "No route to host"), +#endif +#if defined (EALREADY) + ENTRY(EALREADY, "EALREADY", "Operation already in progress"), +#endif +#if defined (EINPROGRESS) + ENTRY(EINPROGRESS, "EINPROGRESS", "Operation now in progress"), +#endif +#if defined (ESTALE) + ENTRY(ESTALE, "ESTALE", "Stale NFS file handle"), +#endif +#if defined (EUCLEAN) + ENTRY(EUCLEAN, "EUCLEAN", "Structure needs cleaning"), +#endif +#if defined (ENOTNAM) + ENTRY(ENOTNAM, "ENOTNAM", "Not a XENIX named type file"), +#endif +#if defined (ENAVAIL) + ENTRY(ENAVAIL, "ENAVAIL", "No XENIX semaphores available"), +#endif +#if defined (EISNAM) + ENTRY(EISNAM, "EISNAM", "Is a named type file"), +#endif +#if defined (EREMOTEIO) + ENTRY(EREMOTEIO, "EREMOTEIO", "Remote I/O error"), +#endif + ENTRY(0, NULL, NULL) +}; + +#ifdef EVMSERR +/* This is not in the table, because the numeric value of EVMSERR (32767) + lies outside the range of sys_errlist[]. */ +static struct { int value; const char *name, *msg; } + evmserr = { EVMSERR, "EVMSERR", "VMS-specific error" }; +#endif + +/* Translation table allocated and initialized at runtime. Indexed by the + errno value to find the equivalent symbolic value. */ + +static const char **error_names; +static int num_error_names = 0; + +/* Translation table allocated and initialized at runtime, if it does not + already exist in the host environment. Indexed by the errno value to find + the descriptive string. + + We don't export it for use in other modules because even though it has the + same name, it differs from other implementations in that it is dynamically + initialized rather than statically initialized. */ + +#ifndef HAVE_SYS_ERRLIST + +#define sys_nerr sys_nerr__ +#define sys_errlist sys_errlist__ +static int sys_nerr; +static const char **sys_errlist; + +#else + +extern int sys_nerr; +extern char *sys_errlist[]; + +#endif + +/* + +NAME + + init_error_tables -- initialize the name and message tables + +SYNOPSIS + + static void init_error_tables (); + +DESCRIPTION + + Using the error_table, which is initialized at compile time, generate + the error_names and the sys_errlist (if needed) tables, which are + indexed at runtime by a specific errno value. + +BUGS + + The initialization of the tables may fail under low memory conditions, + in which case we don't do anything particularly useful, but we don't + bomb either. Who knows, it might succeed at a later point if we free + some memory in the meantime. In any case, the other routines know + how to deal with lack of a table after trying to initialize it. This + may or may not be considered to be a bug, that we don't specifically + warn about this particular failure mode. + +*/ + +static void +init_error_tables (void) +{ + const struct error_info *eip; + int nbytes; + + /* If we haven't already scanned the error_table once to find the maximum + errno value, then go find it now. */ + + if (num_error_names == 0) + { + for (eip = error_table; eip -> name != NULL; eip++) + { + if (eip -> value >= num_error_names) + { + num_error_names = eip -> value + 1; + } + } + } + + /* Now attempt to allocate the error_names table, zero it out, and then + initialize it from the statically initialized error_table. */ + + if (error_names == NULL) + { + nbytes = num_error_names * sizeof (char *); + if ((error_names = (const char **) malloc (nbytes)) != NULL) + { + memset (error_names, 0, nbytes); + for (eip = error_table; eip -> name != NULL; eip++) + { + error_names[eip -> value] = eip -> name; + } + } + } + +#ifndef HAVE_SYS_ERRLIST + + /* Now attempt to allocate the sys_errlist table, zero it out, and then + initialize it from the statically initialized error_table. */ + + if (sys_errlist == NULL) + { + nbytes = num_error_names * sizeof (char *); + if ((sys_errlist = (const char **) malloc (nbytes)) != NULL) + { + memset (sys_errlist, 0, nbytes); + sys_nerr = num_error_names; + for (eip = error_table; eip -> name != NULL; eip++) + { + sys_errlist[eip -> value] = eip -> msg; + } + } + } + +#endif + +} + +/* + + +@deftypefn Extension int errno_max (void) + +Returns the maximum @code{errno} value for which a corresponding +symbolic name or message is available. Note that in the case where we +use the @code{sys_errlist} supplied by the system, it is possible for +there to be more symbolic names than messages, or vice versa. In +fact, the manual page for @code{perror(3C)} explicitly warns that one +should check the size of the table (@code{sys_nerr}) before indexing +it, since new error codes may be added to the system before they are +added to the table. Thus @code{sys_nerr} might be smaller than value +implied by the largest @code{errno} value defined in @code{}. + +We return the maximum value that can be used to obtain a meaningful +symbolic name or message. + +@end deftypefn + +*/ + +int +errno_max (void) +{ + int maxsize; + + if (error_names == NULL) + { + init_error_tables (); + } + maxsize = MAX (sys_nerr, num_error_names); + return (maxsize - 1); +} + +#ifndef HAVE_STRERROR + +/* + +@deftypefn Supplemental char* strerror (int @var{errnoval}) + +Maps an @code{errno} number to an error message string, the contents +of which are implementation defined. On systems which have the +external variables @code{sys_nerr} and @code{sys_errlist}, these +strings will be the same as the ones used by @code{perror}. + +If the supplied error number is within the valid range of indices for +the @code{sys_errlist}, but no message is available for the particular +error number, then returns the string @samp{Error @var{num}}, where +@var{num} is the error number. + +If the supplied error number is not a valid index into +@code{sys_errlist}, returns @code{NULL}. + +The returned string is only guaranteed to be valid only until the +next call to @code{strerror}. + +@end deftypefn + +*/ + +char * +strerror (int errnoval) +{ + const char *msg; + static char buf[32]; + +#ifndef HAVE_SYS_ERRLIST + + if (error_names == NULL) + { + init_error_tables (); + } + +#endif + + if ((errnoval < 0) || (errnoval >= sys_nerr)) + { +#ifdef EVMSERR + if (errnoval == evmserr.value) + msg = evmserr.msg; + else +#endif + /* Out of range, just return NULL */ + msg = NULL; + } + else if ((sys_errlist == NULL) || (sys_errlist[errnoval] == NULL)) + { + /* In range, but no sys_errlist or no entry at this index. */ + sprintf (buf, "Error %d", errnoval); + msg = buf; + } + else + { + /* In range, and a valid message. Just return the message. */ + msg = (char *) sys_errlist[errnoval]; + } + + return (msg); +} + +#endif /* ! HAVE_STRERROR */ + + +/* + +@deftypefn Replacement {const char*} strerrno (int @var{errnum}) + +Given an error number returned from a system call (typically returned +in @code{errno}), returns a pointer to a string containing the +symbolic name of that error number, as found in @code{}. + +If the supplied error number is within the valid range of indices for +symbolic names, but no name is available for the particular error +number, then returns the string @samp{Error @var{num}}, where @var{num} +is the error number. + +If the supplied error number is not within the range of valid +indices, then returns @code{NULL}. + +The contents of the location pointed to are only guaranteed to be +valid until the next call to @code{strerrno}. + +@end deftypefn + +*/ + +const char * +strerrno (int errnoval) +{ + const char *name; + static char buf[32]; + + if (error_names == NULL) + { + init_error_tables (); + } + + if ((errnoval < 0) || (errnoval >= num_error_names)) + { +#ifdef EVMSERR + if (errnoval == evmserr.value) + name = evmserr.name; + else +#endif + /* Out of range, just return NULL */ + name = NULL; + } + else if ((error_names == NULL) || (error_names[errnoval] == NULL)) + { + /* In range, but no error_names or no entry at this index. */ + sprintf (buf, "Error %d", errnoval); + name = (const char *) buf; + } + else + { + /* In range, and a valid name. Just return the name. */ + name = error_names[errnoval]; + } + + return (name); +} + +/* + +@deftypefn Extension int strtoerrno (const char *@var{name}) + +Given the symbolic name of a error number (e.g., @code{EACCES}), map it +to an errno value. If no translation is found, returns 0. + +@end deftypefn + +*/ + +int +strtoerrno (const char *name) +{ + int errnoval = 0; + + if (name != NULL) + { + if (error_names == NULL) + { + init_error_tables (); + } + for (errnoval = 0; errnoval < num_error_names; errnoval++) + { + if ((error_names[errnoval] != NULL) && + (strcmp (name, error_names[errnoval]) == 0)) + { + break; + } + } + if (errnoval == num_error_names) + { +#ifdef EVMSERR + if (strcmp (name, evmserr.name) == 0) + errnoval = evmserr.value; + else +#endif + errnoval = 0; + } + } + return (errnoval); +} + + +/* A simple little main that does nothing but print all the errno translations + if MAIN is defined and this file is compiled and linked. */ + +#ifdef MAIN + +#include + +int +main (void) +{ + int errn; + int errnmax; + const char *name; + const char *msg; + char *strerror (); + + errnmax = errno_max (); + printf ("%d entries in names table.\n", num_error_names); + printf ("%d entries in messages table.\n", sys_nerr); + printf ("%d is max useful index.\n", errnmax); + + /* Keep printing values until we get to the end of *both* tables, not + *either* table. Note that knowing the maximum useful index does *not* + relieve us of the responsibility of testing the return pointer for + NULL. */ + + for (errn = 0; errn <= errnmax; errn++) + { + name = strerrno (errn); + name = (name == NULL) ? "" : name; + msg = strerror (errn); + msg = (msg == NULL) ? "" : msg; + printf ("%-4d%-18s%s\n", errn, name, msg); + } + + return 0; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/strncasecmp.c b/external/gpl3/gdb/dist/libiberty/strncasecmp.c new file mode 100644 index 000000000000..47700dde5183 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strncasecmp.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 1987 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that this notice is preserved and that due credit is given + * to the University of California at Berkeley. The name of the University + * may not be used to endorse or promote products derived from this + * software without specific written prior permission. This software + * is provided ``as is'' without express or implied warranty. + */ + +/* + +@deftypefn Supplemental int strncasecmp (const char *@var{s1}, const char *@var{s2}) + +A case-insensitive @code{strncmp}. + +@end deftypefn + +*/ + +#if defined(LIBC_SCCS) && !defined(lint) +static char sccsid[] = "@(#)strcasecmp.c 5.5 (Berkeley) 11/24/87"; +#endif /* LIBC_SCCS and not lint */ + +#include +#include + +/* + * This array is designed for mapping upper and lower case letter + * together for a case independent comparison. The mappings are + * based upon ascii character sequences. + */ +static const unsigned char charmap[] = { + '\000', '\001', '\002', '\003', '\004', '\005', '\006', '\007', + '\010', '\011', '\012', '\013', '\014', '\015', '\016', '\017', + '\020', '\021', '\022', '\023', '\024', '\025', '\026', '\027', + '\030', '\031', '\032', '\033', '\034', '\035', '\036', '\037', + '\040', '\041', '\042', '\043', '\044', '\045', '\046', '\047', + '\050', '\051', '\052', '\053', '\054', '\055', '\056', '\057', + '\060', '\061', '\062', '\063', '\064', '\065', '\066', '\067', + '\070', '\071', '\072', '\073', '\074', '\075', '\076', '\077', + '\100', '\141', '\142', '\143', '\144', '\145', '\146', '\147', + '\150', '\151', '\152', '\153', '\154', '\155', '\156', '\157', + '\160', '\161', '\162', '\163', '\164', '\165', '\166', '\167', + '\170', '\171', '\172', '\133', '\134', '\135', '\136', '\137', + '\140', '\141', '\142', '\143', '\144', '\145', '\146', '\147', + '\150', '\151', '\152', '\153', '\154', '\155', '\156', '\157', + '\160', '\161', '\162', '\163', '\164', '\165', '\166', '\167', + '\170', '\171', '\172', '\173', '\174', '\175', '\176', '\177', + '\200', '\201', '\202', '\203', '\204', '\205', '\206', '\207', + '\210', '\211', '\212', '\213', '\214', '\215', '\216', '\217', + '\220', '\221', '\222', '\223', '\224', '\225', '\226', '\227', + '\230', '\231', '\232', '\233', '\234', '\235', '\236', '\237', + '\240', '\241', '\242', '\243', '\244', '\245', '\246', '\247', + '\250', '\251', '\252', '\253', '\254', '\255', '\256', '\257', + '\260', '\261', '\262', '\263', '\264', '\265', '\266', '\267', + '\270', '\271', '\272', '\273', '\274', '\275', '\276', '\277', + '\300', '\341', '\342', '\343', '\344', '\345', '\346', '\347', + '\350', '\351', '\352', '\353', '\354', '\355', '\356', '\357', + '\360', '\361', '\362', '\363', '\364', '\365', '\366', '\367', + '\370', '\371', '\372', '\333', '\334', '\335', '\336', '\337', + '\340', '\341', '\342', '\343', '\344', '\345', '\346', '\347', + '\350', '\351', '\352', '\353', '\354', '\355', '\356', '\357', + '\360', '\361', '\362', '\363', '\364', '\365', '\366', '\367', + '\370', '\371', '\372', '\373', '\374', '\375', '\376', '\377', +}; + +int +strncasecmp(const char *s1, const char *s2, register size_t n) +{ + register unsigned char u1, u2; + + for (; n != 0; --n) { + u1 = (unsigned char) *s1++; + u2 = (unsigned char) *s2++; + if (charmap[u1] != charmap[u2]) { + return charmap[u1] - charmap[u2]; + } + if (u1 == '\0') { + return 0; + } + } + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/strncmp.c b/external/gpl3/gdb/dist/libiberty/strncmp.c new file mode 100644 index 000000000000..23f6df617562 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strncmp.c @@ -0,0 +1,34 @@ +/* strncmp -- compare two strings, stop after n bytes. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental int strncmp (const char *@var{s1}, @ + const char *@var{s2}, size_t @var{n}) + +Compares the first @var{n} bytes of two strings, returning a value as +@code{strcmp}. + +@end deftypefn + +*/ + +#include +#include + +int +strncmp(const char *s1, const char *s2, register size_t n) +{ + register unsigned char u1, u2; + + while (n-- > 0) + { + u1 = (unsigned char) *s1++; + u2 = (unsigned char) *s2++; + if (u1 != u2) + return u1 - u2; + if (u1 == '\0') + return 0; + } + return 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/strndup.c b/external/gpl3/gdb/dist/libiberty/strndup.c new file mode 100644 index 000000000000..9e9b4e2991f8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strndup.c @@ -0,0 +1,55 @@ +/* Implement the strndup function. + Copyright (C) 2005 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Extension char* strndup (const char *@var{s}, size_t @var{n}) + +Returns a pointer to a copy of @var{s} with at most @var{n} characters +in memory obtained from @code{malloc}, or @code{NULL} if insufficient +memory was available. The result is always NUL terminated. + +@end deftypefn + +*/ + +#include "ansidecl.h" +#include + +extern size_t strlen (const char*); +extern PTR malloc (size_t); +extern PTR memcpy (PTR, const PTR, size_t); + +char * +strndup (const char *s, size_t n) +{ + char *result; + size_t len = strlen (s); + + if (n < len) + len = n; + + result = (char *) malloc (len + 1); + if (!result) + return 0; + + result[len] = '\0'; + return (char *) memcpy (result, s, len); +} diff --git a/external/gpl3/gdb/dist/libiberty/strrchr.c b/external/gpl3/gdb/dist/libiberty/strrchr.c new file mode 100644 index 000000000000..5cf7c14d8b74 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strrchr.c @@ -0,0 +1,28 @@ +/* Portable version of strrchr(). + This function is in the public domain. */ + +/* + +@deftypefn Supplemental char* strrchr (const char *@var{s}, int @var{c}) + +Returns a pointer to the last occurrence of the character @var{c} in +the string @var{s}, or @code{NULL} if not found. If @var{c} is itself the +null character, the results are undefined. + +@end deftypefn + +*/ + +#include + +char * +strrchr (register const char *s, int c) +{ + char *rtnval = 0; + + do { + if (*s == c) + rtnval = (char*) s; + } while (*s++); + return (rtnval); +} diff --git a/external/gpl3/gdb/dist/libiberty/strsignal.c b/external/gpl3/gdb/dist/libiberty/strsignal.c new file mode 100644 index 000000000000..666b1b4f15e5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strsignal.c @@ -0,0 +1,610 @@ +/* Extended support for using signal values. + Written by Fred Fish. fnf@cygnus.com + This file is in the public domain. */ + +#include "config.h" +#include "ansidecl.h" +#include "libiberty.h" + +/* We need to declare sys_siglist, because even if the system provides + it we can't assume that it is declared in (for example, + SunOS provides sys_siglist, but it does not declare it in any + header file). However, we can't declare sys_siglist portably, + because on some systems it is declared with const and on some + systems it is declared without const. If we were using autoconf, + we could work out the right declaration. Until, then we just + ignore any declaration in the system header files, and always + declare it ourselves. With luck, this will always work. */ +#define sys_siglist no_such_symbol +#define sys_nsig sys_nsig__no_such_symbol + +#include +#include + +/* Routines imported from standard C runtime libraries. */ + +#ifdef HAVE_STDLIB_H +#include +#else +extern PTR malloc (); +#endif + +#ifdef HAVE_STRING_H +#include +#else +extern PTR memset (); +#endif + +/* Undefine the macro we used to hide the definition of sys_siglist + found in the system header files. */ +#undef sys_siglist +#undef sys_nsig + +#ifndef NULL +# define NULL (void *) 0 +#endif + +#ifndef MAX +# define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +static void init_signal_tables (void); + +/* Translation table for signal values. + + Note that this table is generally only accessed when it is used at runtime + to initialize signal name and message tables that are indexed by signal + value. + + Not all of these signals will exist on all systems. This table is the only + thing that should have to be updated as new signal numbers are introduced. + It's sort of ugly, but at least its portable. */ + +struct signal_info +{ + const int value; /* The numeric value from */ + const char *const name; /* The equivalent symbolic value */ +#ifndef HAVE_SYS_SIGLIST + const char *const msg; /* Short message about this value */ +#endif +}; + +#ifndef HAVE_SYS_SIGLIST +# define ENTRY(value, name, msg) {value, name, msg} +#else +# define ENTRY(value, name, msg) {value, name} +#endif + +static const struct signal_info signal_table[] = +{ +#if defined (SIGHUP) + ENTRY(SIGHUP, "SIGHUP", "Hangup"), +#endif +#if defined (SIGINT) + ENTRY(SIGINT, "SIGINT", "Interrupt"), +#endif +#if defined (SIGQUIT) + ENTRY(SIGQUIT, "SIGQUIT", "Quit"), +#endif +#if defined (SIGILL) + ENTRY(SIGILL, "SIGILL", "Illegal instruction"), +#endif +#if defined (SIGTRAP) + ENTRY(SIGTRAP, "SIGTRAP", "Trace/breakpoint trap"), +#endif +/* Put SIGIOT before SIGABRT, so that if SIGIOT==SIGABRT then SIGABRT + overrides SIGIOT. SIGABRT is in ANSI and POSIX.1, and SIGIOT isn't. */ +#if defined (SIGIOT) + ENTRY(SIGIOT, "SIGIOT", "IOT trap"), +#endif +#if defined (SIGABRT) + ENTRY(SIGABRT, "SIGABRT", "Aborted"), +#endif +#if defined (SIGEMT) + ENTRY(SIGEMT, "SIGEMT", "Emulation trap"), +#endif +#if defined (SIGFPE) + ENTRY(SIGFPE, "SIGFPE", "Arithmetic exception"), +#endif +#if defined (SIGKILL) + ENTRY(SIGKILL, "SIGKILL", "Killed"), +#endif +#if defined (SIGBUS) + ENTRY(SIGBUS, "SIGBUS", "Bus error"), +#endif +#if defined (SIGSEGV) + ENTRY(SIGSEGV, "SIGSEGV", "Segmentation fault"), +#endif +#if defined (SIGSYS) + ENTRY(SIGSYS, "SIGSYS", "Bad system call"), +#endif +#if defined (SIGPIPE) + ENTRY(SIGPIPE, "SIGPIPE", "Broken pipe"), +#endif +#if defined (SIGALRM) + ENTRY(SIGALRM, "SIGALRM", "Alarm clock"), +#endif +#if defined (SIGTERM) + ENTRY(SIGTERM, "SIGTERM", "Terminated"), +#endif +#if defined (SIGUSR1) + ENTRY(SIGUSR1, "SIGUSR1", "User defined signal 1"), +#endif +#if defined (SIGUSR2) + ENTRY(SIGUSR2, "SIGUSR2", "User defined signal 2"), +#endif +/* Put SIGCLD before SIGCHLD, so that if SIGCLD==SIGCHLD then SIGCHLD + overrides SIGCLD. SIGCHLD is in POXIX.1 */ +#if defined (SIGCLD) + ENTRY(SIGCLD, "SIGCLD", "Child status changed"), +#endif +#if defined (SIGCHLD) + ENTRY(SIGCHLD, "SIGCHLD", "Child status changed"), +#endif +#if defined (SIGPWR) + ENTRY(SIGPWR, "SIGPWR", "Power fail/restart"), +#endif +#if defined (SIGWINCH) + ENTRY(SIGWINCH, "SIGWINCH", "Window size changed"), +#endif +#if defined (SIGURG) + ENTRY(SIGURG, "SIGURG", "Urgent I/O condition"), +#endif +#if defined (SIGIO) + /* "I/O pending" has also been suggested, but is misleading since the + signal only happens when the process has asked for it, not everytime + I/O is pending. */ + ENTRY(SIGIO, "SIGIO", "I/O possible"), +#endif +#if defined (SIGPOLL) + ENTRY(SIGPOLL, "SIGPOLL", "Pollable event occurred"), +#endif +#if defined (SIGSTOP) + ENTRY(SIGSTOP, "SIGSTOP", "Stopped (signal)"), +#endif +#if defined (SIGTSTP) + ENTRY(SIGTSTP, "SIGTSTP", "Stopped (user)"), +#endif +#if defined (SIGCONT) + ENTRY(SIGCONT, "SIGCONT", "Continued"), +#endif +#if defined (SIGTTIN) + ENTRY(SIGTTIN, "SIGTTIN", "Stopped (tty input)"), +#endif +#if defined (SIGTTOU) + ENTRY(SIGTTOU, "SIGTTOU", "Stopped (tty output)"), +#endif +#if defined (SIGVTALRM) + ENTRY(SIGVTALRM, "SIGVTALRM", "Virtual timer expired"), +#endif +#if defined (SIGPROF) + ENTRY(SIGPROF, "SIGPROF", "Profiling timer expired"), +#endif +#if defined (SIGXCPU) + ENTRY(SIGXCPU, "SIGXCPU", "CPU time limit exceeded"), +#endif +#if defined (SIGXFSZ) + ENTRY(SIGXFSZ, "SIGXFSZ", "File size limit exceeded"), +#endif +#if defined (SIGWIND) + ENTRY(SIGWIND, "SIGWIND", "SIGWIND"), +#endif +#if defined (SIGPHONE) + ENTRY(SIGPHONE, "SIGPHONE", "SIGPHONE"), +#endif +#if defined (SIGLOST) + ENTRY(SIGLOST, "SIGLOST", "Resource lost"), +#endif +#if defined (SIGWAITING) + ENTRY(SIGWAITING, "SIGWAITING", "Process's LWPs are blocked"), +#endif +#if defined (SIGLWP) + ENTRY(SIGLWP, "SIGLWP", "Signal LWP"), +#endif +#if defined (SIGDANGER) + ENTRY(SIGDANGER, "SIGDANGER", "Swap space dangerously low"), +#endif +#if defined (SIGGRANT) + ENTRY(SIGGRANT, "SIGGRANT", "Monitor mode granted"), +#endif +#if defined (SIGRETRACT) + ENTRY(SIGRETRACT, "SIGRETRACT", "Need to relinguish monitor mode"), +#endif +#if defined (SIGMSG) + ENTRY(SIGMSG, "SIGMSG", "Monitor mode data available"), +#endif +#if defined (SIGSOUND) + ENTRY(SIGSOUND, "SIGSOUND", "Sound completed"), +#endif +#if defined (SIGSAK) + ENTRY(SIGSAK, "SIGSAK", "Secure attention"), +#endif + ENTRY(0, NULL, NULL) +}; + +/* Translation table allocated and initialized at runtime. Indexed by the + signal value to find the equivalent symbolic value. */ + +static const char **signal_names; +static int num_signal_names = 0; + +/* Translation table allocated and initialized at runtime, if it does not + already exist in the host environment. Indexed by the signal value to find + the descriptive string. + + We don't export it for use in other modules because even though it has the + same name, it differs from other implementations in that it is dynamically + initialized rather than statically initialized. */ + +#ifndef HAVE_SYS_SIGLIST + +static int sys_nsig; +static const char **sys_siglist; + +#else + +#ifdef NSIG +static int sys_nsig = NSIG; +#else +#ifdef _NSIG +static int sys_nsig = _NSIG; +#endif +#endif +extern const char * const sys_siglist[]; + +#endif + + +/* + +NAME + + init_signal_tables -- initialize the name and message tables + +SYNOPSIS + + static void init_signal_tables (); + +DESCRIPTION + + Using the signal_table, which is initialized at compile time, generate + the signal_names and the sys_siglist (if needed) tables, which are + indexed at runtime by a specific signal value. + +BUGS + + The initialization of the tables may fail under low memory conditions, + in which case we don't do anything particularly useful, but we don't + bomb either. Who knows, it might succeed at a later point if we free + some memory in the meantime. In any case, the other routines know + how to deal with lack of a table after trying to initialize it. This + may or may not be considered to be a bug, that we don't specifically + warn about this particular failure mode. + +*/ + +static void +init_signal_tables (void) +{ + const struct signal_info *eip; + int nbytes; + + /* If we haven't already scanned the signal_table once to find the maximum + signal value, then go find it now. */ + + if (num_signal_names == 0) + { + for (eip = signal_table; eip -> name != NULL; eip++) + { + if (eip -> value >= num_signal_names) + { + num_signal_names = eip -> value + 1; + } + } + } + + /* Now attempt to allocate the signal_names table, zero it out, and then + initialize it from the statically initialized signal_table. */ + + if (signal_names == NULL) + { + nbytes = num_signal_names * sizeof (char *); + if ((signal_names = (const char **) malloc (nbytes)) != NULL) + { + memset (signal_names, 0, nbytes); + for (eip = signal_table; eip -> name != NULL; eip++) + { + signal_names[eip -> value] = eip -> name; + } + } + } + +#ifndef HAVE_SYS_SIGLIST + + /* Now attempt to allocate the sys_siglist table, zero it out, and then + initialize it from the statically initialized signal_table. */ + + if (sys_siglist == NULL) + { + nbytes = num_signal_names * sizeof (char *); + if ((sys_siglist = (const char **) malloc (nbytes)) != NULL) + { + memset (sys_siglist, 0, nbytes); + sys_nsig = num_signal_names; + for (eip = signal_table; eip -> name != NULL; eip++) + { + sys_siglist[eip -> value] = eip -> msg; + } + } + } + +#endif + +} + + +/* + +@deftypefn Extension int signo_max (void) + +Returns the maximum signal value for which a corresponding symbolic +name or message is available. Note that in the case where we use the +@code{sys_siglist} supplied by the system, it is possible for there to +be more symbolic names than messages, or vice versa. In fact, the +manual page for @code{psignal(3b)} explicitly warns that one should +check the size of the table (@code{NSIG}) before indexing it, since +new signal codes may be added to the system before they are added to +the table. Thus @code{NSIG} might be smaller than value implied by +the largest signo value defined in @code{}. + +We return the maximum value that can be used to obtain a meaningful +symbolic name or message. + +@end deftypefn + +*/ + +int +signo_max (void) +{ + int maxsize; + + if (signal_names == NULL) + { + init_signal_tables (); + } + maxsize = MAX (sys_nsig, num_signal_names); + return (maxsize - 1); +} + + +/* + +@deftypefn Supplemental {const char *} strsignal (int @var{signo}) + +Maps an signal number to an signal message string, the contents of +which are implementation defined. On systems which have the external +variable @code{sys_siglist}, these strings will be the same as the +ones used by @code{psignal()}. + +If the supplied signal number is within the valid range of indices for +the @code{sys_siglist}, but no message is available for the particular +signal number, then returns the string @samp{Signal @var{num}}, where +@var{num} is the signal number. + +If the supplied signal number is not a valid index into +@code{sys_siglist}, returns @code{NULL}. + +The returned string is only guaranteed to be valid only until the next +call to @code{strsignal}. + +@end deftypefn + +*/ + +#ifndef HAVE_STRSIGNAL + +char * +strsignal (int signo) +{ + char *msg; + static char buf[32]; + +#ifndef HAVE_SYS_SIGLIST + + if (signal_names == NULL) + { + init_signal_tables (); + } + +#endif + + if ((signo < 0) || (signo >= sys_nsig)) + { + /* Out of range, just return NULL */ + msg = NULL; + } + else if ((sys_siglist == NULL) || (sys_siglist[signo] == NULL)) + { + /* In range, but no sys_siglist or no entry at this index. */ + sprintf (buf, "Signal %d", signo); + msg = buf; + } + else + { + /* In range, and a valid message. Just return the message. We + can safely cast away const, since POSIX says the user must + not modify the result. */ + msg = (char *) sys_siglist[signo]; + } + + return (msg); +} + +#endif /* ! HAVE_STRSIGNAL */ + +/* + +@deftypefn Extension {const char*} strsigno (int @var{signo}) + +Given an signal number, returns a pointer to a string containing the +symbolic name of that signal number, as found in @code{}. + +If the supplied signal number is within the valid range of indices for +symbolic names, but no name is available for the particular signal +number, then returns the string @samp{Signal @var{num}}, where +@var{num} is the signal number. + +If the supplied signal number is not within the range of valid +indices, then returns @code{NULL}. + +The contents of the location pointed to are only guaranteed to be +valid until the next call to @code{strsigno}. + +@end deftypefn + +*/ + +const char * +strsigno (int signo) +{ + const char *name; + static char buf[32]; + + if (signal_names == NULL) + { + init_signal_tables (); + } + + if ((signo < 0) || (signo >= num_signal_names)) + { + /* Out of range, just return NULL */ + name = NULL; + } + else if ((signal_names == NULL) || (signal_names[signo] == NULL)) + { + /* In range, but no signal_names or no entry at this index. */ + sprintf (buf, "Signal %d", signo); + name = (const char *) buf; + } + else + { + /* In range, and a valid name. Just return the name. */ + name = signal_names[signo]; + } + + return (name); +} + + +/* + +@deftypefn Extension int strtosigno (const char *@var{name}) + +Given the symbolic name of a signal, map it to a signal number. If no +translation is found, returns 0. + +@end deftypefn + +*/ + +int +strtosigno (const char *name) +{ + int signo = 0; + + if (name != NULL) + { + if (signal_names == NULL) + { + init_signal_tables (); + } + for (signo = 0; signo < num_signal_names; signo++) + { + if ((signal_names[signo] != NULL) && + (strcmp (name, signal_names[signo]) == 0)) + { + break; + } + } + if (signo == num_signal_names) + { + signo = 0; + } + } + return (signo); +} + + +/* + +@deftypefn Supplemental void psignal (int @var{signo}, char *@var{message}) + +Print @var{message} to the standard error, followed by a colon, +followed by the description of the signal specified by @var{signo}, +followed by a newline. + +@end deftypefn + +*/ + +#ifndef HAVE_PSIGNAL + +void +psignal (int signo, char *message) +{ + if (signal_names == NULL) + { + init_signal_tables (); + } + if ((signo <= 0) || (signo >= sys_nsig)) + { + fprintf (stderr, "%s: unknown signal\n", message); + } + else + { + fprintf (stderr, "%s: %s\n", message, sys_siglist[signo]); + } +} + +#endif /* ! HAVE_PSIGNAL */ + + +/* A simple little main that does nothing but print all the signal translations + if MAIN is defined and this file is compiled and linked. */ + +#ifdef MAIN + +#include + +int +main (void) +{ + int signo; + int maxsigno; + const char *name; + const char *msg; + + maxsigno = signo_max (); + printf ("%d entries in names table.\n", num_signal_names); + printf ("%d entries in messages table.\n", sys_nsig); + printf ("%d is max useful index.\n", maxsigno); + + /* Keep printing values until we get to the end of *both* tables, not + *either* table. Note that knowing the maximum useful index does *not* + relieve us of the responsibility of testing the return pointer for + NULL. */ + + for (signo = 0; signo <= maxsigno; signo++) + { + name = strsigno (signo); + name = (name == NULL) ? "" : name; + msg = strsignal (signo); + msg = (msg == NULL) ? "" : msg; + printf ("%-4d%-18s%s\n", signo, name, msg); + } + + return 0; +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/strstr.c b/external/gpl3/gdb/dist/libiberty/strstr.c new file mode 100644 index 000000000000..60902ea40ee8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strstr.c @@ -0,0 +1,41 @@ +/* Simple implementation of strstr for systems without it. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental char* strstr (const char *@var{string}, const char *@var{sub}) + +This function searches for the substring @var{sub} in the string +@var{string}, not including the terminating null characters. A pointer +to the first occurrence of @var{sub} is returned, or @code{NULL} if the +substring is absent. If @var{sub} points to a string with zero +length, the function returns @var{string}. + +@end deftypefn + + +*/ + + +/* FIXME: The above description is ANSI compiliant. This routine has not + been validated to comply with it. -fnf */ + +#include + +extern char *strchr (const char *, int); +extern int strncmp (const void *, const void *, size_t); +extern size_t strlen (const char *); + +char * +strstr (const char *s1, const char *s2) +{ + const char *p = s1; + const size_t len = strlen (s2); + + for (; (p = strchr (p, *s2)) != 0; p++) + { + if (strncmp (p, s2, len) == 0) + return (char *)p; + } + return (0); +} diff --git a/external/gpl3/gdb/dist/libiberty/strtod.c b/external/gpl3/gdb/dist/libiberty/strtod.c new file mode 100644 index 000000000000..e4da2113f5b2 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strtod.c @@ -0,0 +1,137 @@ +/* Implementation of strtod for systems with atof. + Copyright (C) 1991, 1995, 2002, 2011 Free Software Foundation, Inc. + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental double strtod (const char *@var{string}, @ + char **@var{endptr}) + +This ISO C function converts the initial portion of @var{string} to a +@code{double}. If @var{endptr} is not @code{NULL}, a pointer to the +character after the last character used in the conversion is stored in +the location referenced by @var{endptr}. If no conversion is +performed, zero is returned and the value of @var{string} is stored in +the location referenced by @var{endptr}. + +@end deftypefn + +*/ + +#include "ansidecl.h" +#include "safe-ctype.h" + +extern double atof (const char *); + +/* Disclaimer: this is currently just used by CHILL in GDB and therefore + has not been tested well. It may have been tested for nothing except + that it compiles. */ + +double +strtod (char *str, char **ptr) +{ + char *p; + + if (ptr == (char **)0) + return atof (str); + + p = str; + + while (ISSPACE (*p)) + ++p; + + if (*p == '+' || *p == '-') + ++p; + + /* INF or INFINITY. */ + if ((p[0] == 'i' || p[0] == 'I') + && (p[1] == 'n' || p[1] == 'N') + && (p[2] == 'f' || p[2] == 'F')) + { + if ((p[3] == 'i' || p[3] == 'I') + && (p[4] == 'n' || p[4] == 'N') + && (p[5] == 'i' || p[5] == 'I') + && (p[6] == 't' || p[6] == 'T') + && (p[7] == 'y' || p[7] == 'Y')) + { + *ptr = p + 8; + return atof (str); + } + else + { + *ptr = p + 3; + return atof (str); + } + } + + /* NAN or NAN(foo). */ + if ((p[0] == 'n' || p[0] == 'N') + && (p[1] == 'a' || p[1] == 'A') + && (p[2] == 'n' || p[2] == 'N')) + { + p += 3; + if (*p == '(') + { + ++p; + while (*p != '\0' && *p != ')') + ++p; + if (*p == ')') + ++p; + } + *ptr = p; + return atof (str); + } + + /* digits, with 0 or 1 periods in it. */ + if (ISDIGIT (*p) || *p == '.') + { + int got_dot = 0; + while (ISDIGIT (*p) || (!got_dot && *p == '.')) + { + if (*p == '.') + got_dot = 1; + ++p; + } + + /* Exponent. */ + if (*p == 'e' || *p == 'E') + { + int i; + i = 1; + if (p[i] == '+' || p[i] == '-') + ++i; + if (ISDIGIT (p[i])) + { + while (ISDIGIT (p[i])) + ++i; + *ptr = p + i; + return atof (str); + } + } + *ptr = p; + return atof (str); + } + /* Didn't find any digits. Doesn't look like a number. */ + *ptr = str; + return 0.0; +} diff --git a/external/gpl3/gdb/dist/libiberty/strtol.c b/external/gpl3/gdb/dist/libiberty/strtol.c new file mode 100644 index 000000000000..bde5647c9a6b --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strtol.c @@ -0,0 +1,165 @@ +/*- + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. [rescinded 22 July 1999] + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + +@deftypefn Supplemental {long int} strtol (const char *@var{string}, @ + char **@var{endptr}, int @var{base}) +@deftypefnx Supplemental {unsigned long int} strtoul (const char *@var{string}, @ + char **@var{endptr}, int @var{base}) + +The @code{strtol} function converts the string in @var{string} to a +long integer value according to the given @var{base}, which must be +between 2 and 36 inclusive, or be the special value 0. If @var{base} +is 0, @code{strtol} will look for the prefixes @code{0} and @code{0x} +to indicate bases 8 and 16, respectively, else default to base 10. +When the base is 16 (either explicitly or implicitly), a prefix of +@code{0x} is allowed. The handling of @var{endptr} is as that of +@code{strtod} above. The @code{strtoul} function is the same, except +that the converted value is unsigned. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#include "safe-ctype.h" + +/* FIXME: It'd be nice to configure around these, but the include files are too + painful. These macros should at least be more portable than hardwired hex + constants. */ + +#ifndef ULONG_MAX +#define ULONG_MAX ((unsigned long)(~0L)) /* 0xFFFFFFFF */ +#endif + +#ifndef LONG_MAX +#define LONG_MAX ((long)(ULONG_MAX >> 1)) /* 0x7FFFFFFF */ +#endif + +#ifndef LONG_MIN +#define LONG_MIN ((long)(~LONG_MAX)) /* 0x80000000 */ +#endif + +/* + * Convert a string to a long integer. + * + * Ignores `locale' stuff. Assumes that the upper and lower case + * alphabets and digits are each contiguous. + */ +long +strtol(const char *nptr, char **endptr, register int base) +{ + register const char *s = nptr; + register unsigned long acc; + register int c; + register unsigned long cutoff; + register int neg = 0, any, cutlim; + + /* + * Skip white space and pick up leading +/- sign if any. + * If base is 0, allow 0x for hex and 0 for octal, else + * assume decimal; if base is already 16, allow 0x. + */ + do { + c = *s++; + } while (ISSPACE(c)); + if (c == '-') { + neg = 1; + c = *s++; + } else if (c == '+') + c = *s++; + if ((base == 0 || base == 16) && + c == '0' && (*s == 'x' || *s == 'X')) { + c = s[1]; + s += 2; + base = 16; + } + if (base == 0) + base = c == '0' ? 8 : 10; + + /* + * Compute the cutoff value between legal numbers and illegal + * numbers. That is the largest legal value, divided by the + * base. An input number that is greater than this value, if + * followed by a legal input character, is too big. One that + * is equal to this value may be valid or not; the limit + * between valid and invalid numbers is then based on the last + * digit. For instance, if the range for longs is + * [-2147483648..2147483647] and the input base is 10, + * cutoff will be set to 214748364 and cutlim to either + * 7 (neg==0) or 8 (neg==1), meaning that if we have accumulated + * a value > 214748364, or equal but the next digit is > 7 (or 8), + * the number is too big, and we will return a range error. + * + * Set any if any `digits' consumed; make it negative to indicate + * overflow. + */ + cutoff = neg ? -(unsigned long)LONG_MIN : LONG_MAX; + cutlim = cutoff % (unsigned long)base; + cutoff /= (unsigned long)base; + for (acc = 0, any = 0;; c = *s++) { + if (ISDIGIT(c)) + c -= '0'; + else if (ISALPHA(c)) + c -= ISUPPER(c) ? 'A' - 10 : 'a' - 10; + else + break; + if (c >= base) + break; + if (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim)) + any = -1; + else { + any = 1; + acc *= base; + acc += c; + } + } + if (any < 0) { + acc = neg ? LONG_MIN : LONG_MAX; + errno = ERANGE; + } else if (neg) + acc = -acc; + if (endptr != 0) + *endptr = (char *) (any ? s - 1 : nptr); + return (acc); +} diff --git a/external/gpl3/gdb/dist/libiberty/strtoul.c b/external/gpl3/gdb/dist/libiberty/strtoul.c new file mode 100644 index 000000000000..ba80063531e5 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strtoul.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 1990 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. [rescinded 22 July 1999] + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#ifdef HAVE_LIMITS_H +#include +#endif +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include +#ifdef NEED_DECLARATION_ERRNO +extern int errno; +#endif +#if 0 +#include +#endif +#include "ansidecl.h" +#include "safe-ctype.h" + +#ifndef ULONG_MAX +#define ULONG_MAX ((unsigned long)(~0L)) /* 0xFFFFFFFF */ +#endif + +/* + * Convert a string to an unsigned long integer. + * + * Ignores `locale' stuff. Assumes that the upper and lower case + * alphabets and digits are each contiguous. + */ +unsigned long +strtoul(const char *nptr, char **endptr, register int base) +{ + register const char *s = nptr; + register unsigned long acc; + register int c; + register unsigned long cutoff; + register int neg = 0, any, cutlim; + + /* + * See strtol for comments as to the logic used. + */ + do { + c = *s++; + } while (ISSPACE(c)); + if (c == '-') { + neg = 1; + c = *s++; + } else if (c == '+') + c = *s++; + if ((base == 0 || base == 16) && + c == '0' && (*s == 'x' || *s == 'X')) { + c = s[1]; + s += 2; + base = 16; + } + if (base == 0) + base = c == '0' ? 8 : 10; + cutoff = (unsigned long)ULONG_MAX / (unsigned long)base; + cutlim = (unsigned long)ULONG_MAX % (unsigned long)base; + for (acc = 0, any = 0;; c = *s++) { + if (ISDIGIT(c)) + c -= '0'; + else if (ISALPHA(c)) + c -= ISUPPER(c) ? 'A' - 10 : 'a' - 10; + else + break; + if (c >= base) + break; + if (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim)) + any = -1; + else { + any = 1; + acc *= base; + acc += c; + } + } + if (any < 0) { + acc = ULONG_MAX; + errno = ERANGE; + } else if (neg) + acc = -acc; + if (endptr != 0) + *endptr = (char *) (any ? s - 1 : nptr); + return (acc); +} diff --git a/external/gpl3/gdb/dist/libiberty/strverscmp.c b/external/gpl3/gdb/dist/libiberty/strverscmp.c new file mode 100644 index 000000000000..04e1e4ae99ef --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/strverscmp.c @@ -0,0 +1,157 @@ +/* Compare strings while treating digits characters numerically. + Copyright (C) 1997, 2002, 2005 Free Software Foundation, Inc. + This file is part of the libiberty library. + Contributed by Jean-François Bignolles , 1997. + + Libiberty is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + Libiberty is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. */ + +#include "libiberty.h" +#include "safe-ctype.h" + +/* +@deftypefun int strverscmp (const char *@var{s1}, const char *@var{s2}) +The @code{strverscmp} function compares the string @var{s1} against +@var{s2}, considering them as holding indices/version numbers. Return +value follows the same conventions as found in the @code{strverscmp} +function. In fact, if @var{s1} and @var{s2} contain no digits, +@code{strverscmp} behaves like @code{strcmp}. + +Basically, we compare strings normally (character by character), until +we find a digit in each string - then we enter a special comparison +mode, where each sequence of digits is taken as a whole. If we reach the +end of these two parts without noticing a difference, we return to the +standard comparison mode. There are two types of numeric parts: +"integral" and "fractional" (those begin with a '0'). The types +of the numeric parts affect the way we sort them: + +@itemize @bullet +@item +integral/integral: we compare values as you would expect. + +@item +fractional/integral: the fractional part is less than the integral one. +Again, no surprise. + +@item +fractional/fractional: the things become a bit more complex. +If the common prefix contains only leading zeroes, the longest part is less +than the other one; else the comparison behaves normally. +@end itemize + +@smallexample +strverscmp ("no digit", "no digit") + @result{} 0 // @r{same behavior as strcmp.} +strverscmp ("item#99", "item#100") + @result{} <0 // @r{same prefix, but 99 < 100.} +strverscmp ("alpha1", "alpha001") + @result{} >0 // @r{fractional part inferior to integral one.} +strverscmp ("part1_f012", "part1_f01") + @result{} >0 // @r{two fractional parts.} +strverscmp ("foo.009", "foo.0") + @result{} <0 // @r{idem, but with leading zeroes only.} +@end smallexample + +This function is especially useful when dealing with filename sorting, +because filenames frequently hold indices/version numbers. +@end deftypefun + +*/ + +/* states: S_N: normal, S_I: comparing integral part, S_F: comparing + fractional parts, S_Z: idem but with leading Zeroes only */ +#define S_N 0x0 +#define S_I 0x4 +#define S_F 0x8 +#define S_Z 0xC + +/* result_type: CMP: return diff; LEN: compare using len_diff/diff */ +#define CMP 2 +#define LEN 3 + + +/* Compare S1 and S2 as strings holding indices/version numbers, + returning less than, equal to or greater than zero if S1 is less than, + equal to or greater than S2 (for more info, see the Glibc texinfo doc). */ + +int +strverscmp (const char *s1, const char *s2) +{ + const unsigned char *p1 = (const unsigned char *) s1; + const unsigned char *p2 = (const unsigned char *) s2; + unsigned char c1, c2; + int state; + int diff; + + /* Symbol(s) 0 [1-9] others (padding) + Transition (10) 0 (01) d (00) x (11) - */ + static const unsigned int next_state[] = + { + /* state x d 0 - */ + /* S_N */ S_N, S_I, S_Z, S_N, + /* S_I */ S_N, S_I, S_I, S_I, + /* S_F */ S_N, S_F, S_F, S_F, + /* S_Z */ S_N, S_F, S_Z, S_Z + }; + + static const int result_type[] = + { + /* state x/x x/d x/0 x/- d/x d/d d/0 d/- + 0/x 0/d 0/0 0/- -/x -/d -/0 -/- */ + + /* S_N */ CMP, CMP, CMP, CMP, CMP, LEN, CMP, CMP, + CMP, CMP, CMP, CMP, CMP, CMP, CMP, CMP, + /* S_I */ CMP, -1, -1, CMP, +1, LEN, LEN, CMP, + +1, LEN, LEN, CMP, CMP, CMP, CMP, CMP, + /* S_F */ CMP, CMP, CMP, CMP, CMP, LEN, CMP, CMP, + CMP, CMP, CMP, CMP, CMP, CMP, CMP, CMP, + /* S_Z */ CMP, +1, +1, CMP, -1, CMP, CMP, CMP, + -1, CMP, CMP, CMP + }; + + if (p1 == p2) + return 0; + + c1 = *p1++; + c2 = *p2++; + /* Hint: '0' is a digit too. */ + state = S_N | ((c1 == '0') + (ISDIGIT (c1) != 0)); + + while ((diff = c1 - c2) == 0 && c1 != '\0') + { + state = next_state[state]; + c1 = *p1++; + c2 = *p2++; + state |= (c1 == '0') + (ISDIGIT (c1) != 0); + } + + state = result_type[state << 2 | (((c2 == '0') + (ISDIGIT (c2) != 0)))]; + + switch (state) + { + case CMP: + return diff; + + case LEN: + while (ISDIGIT (*p1++)) + if (!ISDIGIT (*p2++)) + return 1; + + return ISDIGIT (*p2) ? -1 : diff; + + default: + return state; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/testsuite/Makefile.in b/external/gpl3/gdb/dist/libiberty/testsuite/Makefile.in new file mode 100644 index 000000000000..69ac1f5105e0 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/testsuite/Makefile.in @@ -0,0 +1,92 @@ +# +# Makefile +# Copyright (C) 1999, 2002, 2006 +# Free Software Foundation +# +# This file is part of the libiberty library. +# Libiberty is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# Libiberty is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with libiberty; see the file COPYING.LIB. If not, +# write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, +# Boston, MA 02110-1301, USA. +# + +# This file was written by Tom Tromey . + +# +# Makefile for libiberty/testsuite directory +# + +srcdir = @srcdir@ +VPATH = @srcdir@ + +SHELL = @SHELL@ + +CC = @CC@ +CFLAGS = @CFLAGS@ +LIBCFLAGS = $(CFLAGS) + +# Multilib support variables. +MULTISRCTOP = + +INCDIR=$(srcdir)/../$(MULTISRCTOP)../include + +all: + +# CHECK is set to "really_check" or the empty string by configure. +check: @CHECK@ + +really-check: check-cplus-dem check-pexecute check-expandargv + +# Run some tests of the demangler. +check-cplus-dem: test-demangle $(srcdir)/demangle-expected + ./test-demangle < $(srcdir)/demangle-expected + +# Check the pexecute code. +check-pexecute: test-pexecute + ./test-pexecute + +# Check the expandargv functionality +check-expandargv: test-expandargv + ./test-expandargv + +TEST_COMPILE = $(CC) @DEFS@ $(LIBCFLAGS) -I.. -I$(INCDIR) $(HDEFINES) +test-demangle: $(srcdir)/test-demangle.c ../libiberty.a + $(TEST_COMPILE) -o test-demangle \ + $(srcdir)/test-demangle.c ../libiberty.a + +test-pexecute: $(srcdir)/test-pexecute.c ../libiberty.a + $(TEST_COMPILE) -DHAVE_CONFIG_H -I.. -o test-pexecute \ + $(srcdir)/test-pexecute.c ../libiberty.a + +test-expandargv: $(srcdir)/test-expandargv.c ../libiberty.a + $(TEST_COMPILE) -DHAVE_CONFIG_H -I.. -o test-expandargv \ + $(srcdir)/test-expandargv.c ../libiberty.a + +# Standard (either GNU or Cygnus) rules we don't use. +html install-html info install-info clean-info dvi pdf install-pdf \ +install etags tags installcheck: + +# The standard clean rules. +mostlyclean: + rm -f test-demangle + rm -f test-pexecute + rm -f test-expandargv + rm -f core +clean: mostlyclean +distclean: clean + rm -f Makefile +maintainer-clean realclean: distclean + +Makefile: $(srcdir)/Makefile.in ../config.status + CONFIG_FILES=testsuite/Makefile CONFIG_HEADERS= \ + cd .. && $(SHELL) ./config.status diff --git a/external/gpl3/gdb/dist/libiberty/testsuite/demangle-expected b/external/gpl3/gdb/dist/libiberty/testsuite/demangle-expected new file mode 100644 index 000000000000..c350dbf24b91 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/testsuite/demangle-expected @@ -0,0 +1,4137 @@ +# This file holds test cases for the demangler. +# Each test case looks like this: +# options +# input to be demangled +# expected output +# +# Supported options: +# --format= Sets the demangling style. +# --no-params There are two lines of expected output; the first +# is with DMGL_PARAMS, the second is without it. +# --is-v3-ctor Calls is_gnu_v3_mangled_ctor on input; expected +# output is an integer representing ctor_kind. +# --is-v3-dtor Likewise, but for dtors. +# --ret-postfix Passes the DMGL_RET_POSTFIX option +# +# For compatibility, just in case it matters, the options line may be +# empty, to mean --format=auto. If it doesn't start with --, then it +# may contain only a format name. +# +# A line starting with `#' is ignored. +# However, blank lines in this file are NOT ignored. +# +--format=gnu --no-params +AddAlignment__9ivTSolverUiP12ivInteractorP7ivTGlue +ivTSolver::AddAlignment(unsigned int, ivInteractor *, ivTGlue *) +ivTSolver::AddAlignment +# +--format=gnu --no-params +ArrowheadIntersects__9ArrowLineP9ArrowheadR6BoxObjP7Graphic +ArrowLine::ArrowheadIntersects(Arrowhead *, BoxObj &, Graphic *) +ArrowLine::ArrowheadIntersects +# +--format=gnu --no-params +AtEnd__13ivRubberGroup +ivRubberGroup::AtEnd(void) +ivRubberGroup::AtEnd +# +--format=gnu --no-params +BgFilter__9ivTSolverP12ivInteractor +ivTSolver::BgFilter(ivInteractor *) +ivTSolver::BgFilter +# +--format=gnu --no-params +Check__6UArrayi +UArray::Check(int) +UArray::Check +# +--format=gnu --no-params +CoreConstDecls__8TextCodeR7ostream +TextCode::CoreConstDecls(ostream &) +TextCode::CoreConstDecls +# +--format=gnu --no-params +Detach__8StateVarP12StateVarView +StateVar::Detach(StateVarView *) +StateVar::Detach +# +--format=gnu --no-params +Done__9ComponentG8Iterator +Component::Done(Iterator) +Component::Done +# +--format=gnu --no-params +Effect__11RelateManipR7ivEvent +RelateManip::Effect(ivEvent &) +RelateManip::Effect +# +--format=gnu --no-params +FindFixed__FRP4CNetP4CNet +FindFixed(CNet *&, CNet *) +FindFixed +# +--format=gnu --no-params +Fix48_abort__FR8twolongs +Fix48_abort(twolongs &) +Fix48_abort +# +--format=gnu --no-params +GetBarInfo__15iv2_6_VScrollerP13ivPerspectiveRiT2 +iv2_6_VScroller::GetBarInfo(ivPerspective *, int &, int &) +iv2_6_VScroller::GetBarInfo +# +--format=gnu --no-params +GetBgColor__C9ivPainter +ivPainter::GetBgColor(void) const +ivPainter::GetBgColor +# +--format=gnu --no-params +InsertBody__15H_PullrightMenuii +H_PullrightMenu::InsertBody(int, int) +H_PullrightMenu::InsertBody +# +--format=gnu --no-params +InsertCharacter__9TextManipc +TextManip::InsertCharacter(char) +TextManip::InsertCharacter +# +--format=gnu --no-params +InsertToplevel__7ivWorldP12ivInteractorT1 +ivWorld::InsertToplevel(ivInteractor *, ivInteractor *) +ivWorld::InsertToplevel +# +--format=gnu --no-params +InsertToplevel__7ivWorldP12ivInteractorT1iiUi +ivWorld::InsertToplevel(ivInteractor *, ivInteractor *, int, int, unsigned int) +ivWorld::InsertToplevel +# +--format=gnu --no-params +IsAGroup__FP11GraphicViewP11GraphicComp +IsAGroup(GraphicView *, GraphicComp *) +IsAGroup +# +--format=gnu --no-params +IsA__10ButtonCodeUl +ButtonCode::IsA(unsigned long) +ButtonCode::IsA +# +--format=gnu --no-params +ReadName__FR7istreamPc +ReadName(istream &, char *) +ReadName +# +--format=gnu --no-params +Redraw__13StringBrowseriiii +StringBrowser::Redraw(int, int, int, int) +StringBrowser::Redraw +# +--format=gnu --no-params +Rotate__13ivTransformerf +ivTransformer::Rotate(float) +ivTransformer::Rotate +# +--format=gnu --no-params +Rotated__C13ivTransformerf +ivTransformer::Rotated(float) const +ivTransformer::Rotated +# +--format=gnu --no-params +Round__Ff +Round(float) +Round +# +--format=gnu --no-params +SetExport__16MemberSharedNameUi +MemberSharedName::SetExport(unsigned int) +MemberSharedName::SetExport +# +--format=gnu --no-params +Set__14ivControlState13ControlStatusUi +ivControlState::Set(ControlStatus, unsigned int) +ivControlState::Set +# +--format=gnu --no-params +Set__5DFacePcii +DFace::Set(char *, int, int) +DFace::Set +# +--format=gnu --no-params +VConvert__9ivTSolverP12ivInteractorRP8TElementT2 +ivTSolver::VConvert(ivInteractor *, TElement *&, TElement *&) +ivTSolver::VConvert +# +--format=gnu --no-params +VConvert__9ivTSolverP7ivTGlueRP8TElement +ivTSolver::VConvert(ivTGlue *, TElement *&) +ivTSolver::VConvert +# +--format=gnu --no-params +VOrder__9ivTSolverUiRP12ivInteractorT2 +ivTSolver::VOrder(unsigned int, ivInteractor *&, ivInteractor *&) +ivTSolver::VOrder +# +--format=gnu --no-params +_10PageButton$__both +PageButton::__both +PageButton::__both +# +--format=gnu --no-params +_3RNG$singleMantissa +RNG::singleMantissa +RNG::singleMantissa +# +--format=gnu --no-params +_5IComp$_release +IComp::_release +IComp::_release +# +--format=gnu --no-params +_$_10BitmapComp +BitmapComp::~BitmapComp(void) +BitmapComp::~BitmapComp +# +--format=gnu --no-params +_$_9__io_defs +__io_defs::~__io_defs(void) +__io_defs::~__io_defs +# +--format=gnu --no-params +_$_Q23foo3bar +foo::bar::~bar(void) +foo::bar::~bar +# +--format=gnu --no-params +_$_Q33foo3bar4bell +foo::bar::bell::~bell(void) +foo::bar::bell::~bell +# +--format=gnu --no-params +__10ivTelltaleiP7ivGlyph +ivTelltale::ivTelltale(int, ivGlyph *) +ivTelltale::ivTelltale +# +--format=gnu --no-params +__10ivViewportiP12ivInteractorUi +ivViewport::ivViewport(int, ivInteractor *, unsigned int) +ivViewport::ivViewport +# +--format=gnu --no-params +__10ostrstream +ostrstream::ostrstream(void) +ostrstream::ostrstream +# +--format=gnu --no-params +__10ostrstreamPcii +ostrstream::ostrstream(char *, int, int) +ostrstream::ostrstream +# +--format=gnu --no-params +__11BitmapTablei +BitmapTable::BitmapTable(int) +BitmapTable::BitmapTable +# +--format=gnu --no-params +__12ViewportCodeP12ViewportComp +ViewportCode::ViewportCode(ViewportComp *) +ViewportCode::ViewportCode +# +--format=gnu --no-params +__12iv2_6_Borderii +iv2_6_Border::iv2_6_Border(int, int) +iv2_6_Border::iv2_6_Border +# +--format=gnu --no-params +__12ivBreak_Listl +ivBreak_List::ivBreak_List(long) +ivBreak_List::ivBreak_List +# +--format=gnu --no-params +__14iv2_6_MenuItemiP12ivInteractor +iv2_6_MenuItem::iv2_6_MenuItem(int, ivInteractor *) +iv2_6_MenuItem::iv2_6_MenuItem +# +--format=gnu --no-params +__20DisplayList_IteratorR11DisplayList +DisplayList_Iterator::DisplayList_Iterator(DisplayList &) +DisplayList_Iterator::DisplayList_Iterator +# +--format=gnu --no-params +__3fooRT0 +foo::foo(foo &) +foo::foo +# +--format=gnu --no-params +__3fooiN31 +foo::foo(int, int, int, int) +foo::foo +# +--format=gnu --no-params +__3fooiRT0iT2iT2 +foo::foo(int, foo &, int, foo &, int, foo &) +foo::foo +# +--format=gnu --no-params +__6KeyMapPT0 +KeyMap::KeyMap(KeyMap *) +KeyMap::KeyMap +# +--format=gnu --no-params +__8ArrowCmdP6EditorUiUi +ArrowCmd::ArrowCmd(Editor *, unsigned int, unsigned int) +ArrowCmd::ArrowCmd +# +--format=gnu --no-params +__9F_EllipseiiiiP7Graphic +F_Ellipse::F_Ellipse(int, int, int, int, Graphic *) +F_Ellipse::F_Ellipse +# +--format=gnu --no-params +__9FrameDataP9FrameCompi +FrameData::FrameData(FrameComp *, int) +FrameData::FrameData +# +--format=gnu --no-params +__9HVGraphicP9CanvasVarP7Graphic +HVGraphic::HVGraphic(CanvasVar *, Graphic *) +HVGraphic::HVGraphic +# +--format=gnu --no-params +__Q23foo3bar +foo::bar::bar(void) +foo::bar::bar +# +--format=gnu --no-params +__Q33foo3bar4bell +foo::bar::bell::bell(void) +foo::bar::bell::bell +# +--format=gnu --no-params +__aa__3fooRT0 +foo::operator&&(foo &) +foo::operator&& +# +--format=gnu --no-params +__aad__3fooRT0 +foo::operator&=(foo &) +foo::operator&= +# +--format=gnu --no-params +__ad__3fooRT0 +foo::operator&(foo &) +foo::operator& +# +--format=gnu --no-params +__adv__3fooRT0 +foo::operator/=(foo &) +foo::operator/= +# +--format=gnu --no-params +__aer__3fooRT0 +foo::operator^=(foo &) +foo::operator^= +# +--format=gnu --no-params +__als__3fooRT0 +foo::operator<<=(foo &) +foo::operator<<= +# +--format=gnu --no-params +__amd__3fooRT0 +foo::operator%=(foo &) +foo::operator%= +# +--format=gnu --no-params +__ami__3fooRT0 +foo::operator-=(foo &) +foo::operator-= +# +--format=gnu --no-params +__aml__3FixRT0 +Fix::operator*=(Fix &) +Fix::operator*= +# +--format=gnu --no-params +__aml__5Fix16i +Fix16::operator*=(int) +Fix16::operator*= +# +--format=gnu --no-params +__aml__5Fix32RT0 +Fix32::operator*=(Fix32 &) +Fix32::operator*= +# +--format=gnu --no-params +__aor__3fooRT0 +foo::operator|=(foo &) +foo::operator|= +# +--format=gnu --no-params +__apl__3fooRT0 +foo::operator+=(foo &) +foo::operator+= +# +--format=gnu --no-params +__ars__3fooRT0 +foo::operator>>=(foo &) +foo::operator>>= +# +--format=gnu --no-params +__as__3fooRT0 +foo::operator=(foo &) +foo::operator= +# +--format=gnu --no-params +__cl__3fooRT0 +foo::operator()(foo &) +foo::operator() +# +--format=gnu --no-params +__cl__6Normal +Normal::operator()(void) +Normal::operator() +# +--format=gnu --no-params +__cl__6Stringii +String::operator()(int, int) +String::operator() +# +--format=gnu --no-params +__cm__3fooRT0 +foo::operator, (foo &) +foo::operator, +# +--format=gnu --no-params +__co__3foo +foo::operator~(void) +foo::operator~ +# +--format=gnu --no-params +__dl__3fooPv +foo::operator delete(void *) +foo::operator delete +# +--format=gnu --no-params +__dv__3fooRT0 +foo::operator/(foo &) +foo::operator/ +# +--format=gnu --no-params +__eq__3fooRT0 +foo::operator==(foo &) +foo::operator== +# +--format=gnu --no-params +__er__3fooRT0 +foo::operator^(foo &) +foo::operator^ +# +--format=gnu --no-params +__ge__3fooRT0 +foo::operator>=(foo &) +foo::operator>= +# +--format=gnu --no-params +__gt__3fooRT0 +foo::operator>(foo &) +foo::operator> +# +--format=gnu --no-params +__le__3fooRT0 +foo::operator<=(foo &) +foo::operator<= +# +--format=gnu --no-params +__ls__3fooRT0 +foo::operator<<(foo &) +foo::operator<< +# +--format=gnu --no-params +__ls__FR7ostreamPFR3ios_R3ios +operator<<(ostream &, ios &(*)(ios &)) +operator<< +# +--format=gnu --no-params +__ls__FR7ostreamR3Fix +operator<<(ostream &, Fix &) +operator<< +# +--format=gnu --no-params +__lt__3fooRT0 +foo::operator<(foo &) +foo::operator< +# +--format=gnu --no-params +__md__3fooRT0 +foo::operator%(foo &) +foo::operator% +# +--format=gnu --no-params +__mi__3fooRT0 +foo::operator-(foo &) +foo::operator- +# +--format=gnu --no-params +__ml__3fooRT0 +foo::operator*(foo &) +foo::operator* +# +--format=gnu --no-params +__mm__3fooi +foo::operator--(int) +foo::operator-- +# +--format=gnu --no-params +__ne__3fooRT0 +foo::operator!=(foo &) +foo::operator!= +# +--format=gnu --no-params +__nt__3foo +foo::operator!(void) +foo::operator! +# +--format=gnu --no-params +__nw__3fooi +foo::operator new(int) +foo::operator new +# +--format=gnu --no-params +__oo__3fooRT0 +foo::operator||(foo &) +foo::operator|| +# +--format=gnu --no-params +__opPc__3foo +foo::operator char *(void) +foo::operator char * +# +--format=gnu --no-params +__opi__3foo +foo::operator int(void) +foo::operator int +# +--format=gnu --no-params +__or__3fooRT0 +foo::operator|(foo &) +foo::operator| +# +--format=gnu --no-params +__pl__3fooRT0 +foo::operator+(foo &) +foo::operator+ +# +--format=gnu --no-params +__pp__3fooi +foo::operator++(int) +foo::operator++ +# +--format=gnu --no-params +__rf__3foo +foo::operator->(void) +foo::operator-> +# +--format=gnu --no-params +__rm__3fooRT0 +foo::operator->*(foo &) +foo::operator->* +# +--format=gnu --no-params +__rs__3fooRT0 +foo::operator>>(foo &) +foo::operator>> +# +--format=gnu --no-params +_new_Fix__FUs +_new_Fix(unsigned short) +_new_Fix +# +--format=gnu --no-params +_vt.foo +foo virtual table +foo virtual table +# +--format=gnu --no-params +_vt.foo.bar +foo::bar virtual table +foo::bar virtual table +# +--format=gnu --no-params +_vt$foo +foo virtual table +foo virtual table +# +--format=gnu --no-params +_vt$foo$bar +foo::bar virtual table +foo::bar virtual table +# +--format=gnu --no-params +append__7ivGlyphPT0 +ivGlyph::append(ivGlyph *) +ivGlyph::append +# +--format=gnu --no-params +clearok__FP7_win_sti +clearok(_win_st *, int) +clearok +# +--format=gnu --no-params +complexfunc2__FPFPc_i +complexfunc2(int (*)(char *)) +complexfunc2 +# +--format=gnu --no-params +complexfunc3__FPFPFPl_s_i +complexfunc3(int (*)(short (*)(long *))) +complexfunc3 +# +--format=gnu --no-params +complexfunc4__FPFPFPc_s_i +complexfunc4(int (*)(short (*)(char *))) +complexfunc4 +# +--format=gnu --no-params +complexfunc5__FPFPc_PFl_i +complexfunc5(int (*(*)(char *))(long)) +complexfunc5 +# +--format=gnu --no-params +complexfunc6__FPFPi_PFl_i +complexfunc6(int (*(*)(int *))(long)) +complexfunc6 +# +--format=gnu --no-params +complexfunc7__FPFPFPc_i_PFl_i +complexfunc7(int (*(*)(int (*)(char *)))(long)) +complexfunc7 +# +--format=gnu --no-params +foo__FiN30 +foo(int, int, int, int) +foo +# +--format=gnu --no-params +foo__FiR3fooiT1iT1 +foo(int, foo &, int, foo &, int, foo &) +foo +# +--format=gnu --no-params +foo___3barl +bar::foo_(long) +bar::foo_ +# +--format=gnu --no-params +insert__15ivClippingStacklRP8_XRegion +ivClippingStack::insert(long, _XRegion *&) +ivClippingStack::insert +# +--format=gnu --no-params +insert__16ChooserInfo_ListlR11ChooserInfo +ChooserInfo_List::insert(long, ChooserInfo &) +ChooserInfo_List::insert +# +--format=gnu --no-params +insert__17FontFamilyRepListlRP15ivFontFamilyRep +FontFamilyRepList::insert(long, ivFontFamilyRep *&) +FontFamilyRepList::insert +# +--format=gnu --no-params +leaveok__FP7_win_stc +leaveok(_win_st *, char) +leaveok +# +--format=gnu --no-params +left_mover__C7ivMFKitP12ivAdjustableP7ivStyle +ivMFKit::left_mover(ivAdjustable *, ivStyle *) const +ivMFKit::left_mover +# +--format=gnu --no-params +overload1arg__FSc +overload1arg(signed char) +overload1arg +# +--format=gnu --no-params +overload1arg__FUc +overload1arg(unsigned char) +overload1arg +# +--format=gnu --no-params +overload1arg__FUi +overload1arg(unsigned int) +overload1arg +# +--format=gnu --no-params +overload1arg__FUl +overload1arg(unsigned long) +overload1arg +# +--format=gnu --no-params +overload1arg__FUs +overload1arg(unsigned short) +overload1arg +# +--format=gnu --no-params +overload1arg__Fc +overload1arg(char) +overload1arg +# +--format=gnu --no-params +overload1arg__Fd +overload1arg(double) +overload1arg +# +--format=gnu --no-params +overload1arg__Ff +overload1arg(float) +overload1arg +# +--format=gnu --no-params +overload1arg__Fi +overload1arg(int) +overload1arg +# +--format=gnu --no-params +overload1arg__Fl +overload1arg(long) +overload1arg +# +--format=gnu --no-params +overload1arg__Fs +overload1arg(short) +overload1arg +# +--format=gnu --no-params +overload1arg__Fv +overload1arg(void) +overload1arg +# +--format=gnu --no-params +overloadargs__Fi +overloadargs(int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fii +overloadargs(int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiii +overloadargs(int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiii +overloadargs(int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiii +overloadargs(int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiii +overloadargs(int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiiii +overloadargs(int, int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiiiii +overloadargs(int, int, int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiiiiii +overloadargs(int, int, int, int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiiiiiii +overloadargs(int, int, int, int, int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +overloadargs__Fiiiiiiiiiii +overloadargs(int, int, int, int, int, int, int, int, int, int, int) +overloadargs +# +--format=gnu --no-params +poke__8ivRasterUlUlffff +ivRaster::poke(unsigned long, unsigned long, float, float, float, float) +ivRaster::poke +# +--format=gnu --no-params +polar__Fdd +polar(double, double) +polar +# +--format=gnu --no-params +scale__13ivTransformerff +ivTransformer::scale(float, float) +ivTransformer::scale +# +--format=gnu --no-params +sgetn__7filebufPci +filebuf::sgetn(char *, int) +filebuf::sgetn +# +--format=gnu --no-params +shift__FP5_FrepiT0 +shift(_Frep *, int, _Frep *) +shift +# +--format=gnu --no-params +test__C6BitSeti +BitSet::test(int) const +BitSet::test +# +--format=gnu --no-params +test__C6BitSetii +BitSet::test(int, int) const +BitSet::test +# +--format=gnu --no-params +text_source__8Documentl +Document::text_source(long) +Document::text_source +# +--format=gnu --no-params +variance__6Erlangd +Erlang::variance(double) +Erlang::variance +# +--format=gnu --no-params +view__14DocumentViewerP8ItemViewP11TabularItem +DocumentViewer::view(ItemView *, TabularItem *) +DocumentViewer::view +# +--format=gnu --no-params +xy_extents__11ivExtensionffff +ivExtension::xy_extents(float, float, float, float) +ivExtension::xy_extents +# +--format=gnu --no-params +zero__8osMemoryPvUi +osMemory::zero(void *, unsigned int) +osMemory::zero +# +--format=gnu --no-params +_2T4$N +T4::N +T4::N +# +--format=gnu --no-params +_Q22T42t1$N +T4::t1::N +T4::t1::N +# +--format=gnu --no-params +get__2T1 +T1::get(void) +T1::get +# +--format=gnu --no-params +get__Q22T11a +T1::a::get(void) +T1::a::get +# +--format=gnu --no-params +get__Q32T11a1b +T1::a::b::get(void) +T1::a::b::get +# +--format=gnu --no-params +get__Q42T11a1b1c +T1::a::b::c::get(void) +T1::a::b::c::get +# +--format=gnu --no-params +get__Q52T11a1b1c1d +T1::a::b::c::d::get(void) +T1::a::b::c::d::get +# +--format=gnu --no-params +put__2T1i +T1::put(int) +T1::put +# +--format=gnu --no-params +put__Q22T11ai +T1::a::put(int) +T1::a::put +# +--format=gnu --no-params +put__Q32T11a1bi +T1::a::b::put(int) +T1::a::b::put +# +--format=gnu --no-params +put__Q42T11a1b1ci +T1::a::b::c::put(int) +T1::a::b::c::put +# +--format=gnu --no-params +put__Q52T11a1b1c1di +T1::a::b::c::d::put(int) +T1::a::b::c::d::put +# +--format=gnu --no-params +bar__3fooPv +foo::bar(void *) +foo::bar +# +--format=gnu --no-params +bar__C3fooPv +foo::bar(void *) const +foo::bar +# +--format=gnu --no-params +__eq__3fooRT0 +foo::operator==(foo &) +foo::operator== +# +--format=gnu --no-params +__eq__C3fooR3foo +foo::operator==(foo &) const +foo::operator== +# +--format=gnu --no-params +elem__t6vector1Zdi +vector::elem(int) +vector::elem +# +--format=gnu --no-params +elem__t6vector1Zii +vector::elem(int) +vector::elem +# +--format=gnu --no-params +__t6vector1Zdi +vector::vector(int) +vector::vector +# +--format=gnu --no-params +__t6vector1Zii +vector::vector(int) +vector::vector +# +--format=gnu --no-params +_$_t6vector1Zdi +vector::~vector(int) +vector::~vector +# +--format=gnu --no-params +_$_t6vector1Zii +vector::~vector(int) +vector::~vector +# +--format=gnu --no-params +__nw__t2T11ZcUi +T1::operator new(unsigned int) +T1::operator new +# +--format=gnu --no-params +__nw__t2T11Z1tUi +T1::operator new(unsigned int) +T1::operator new +# +--format=gnu --no-params +__dl__t2T11ZcPv +T1::operator delete(void *) +T1::operator delete +# +--format=gnu --no-params +__dl__t2T11Z1tPv +T1::operator delete(void *) +T1::operator delete +# +--format=gnu --no-params +__t2T11Zci +T1::T1(int) +T1::T1 +# +--format=gnu --no-params +__t2T11Zc +T1::T1(void) +T1::T1 +# +--format=gnu --no-params +__t2T11Z1ti +T1::T1(int) +T1::T1 +# +--format=gnu --no-params +__t2T11Z1t +T1::T1(void) +T1::T1 +# +--format=gnu --no-params +__Q2t4List1Z10VHDLEntity3Pix +List::Pix::Pix(void) +List::Pix::Pix +# +--format=gnu --no-params +__Q2t4List1Z10VHDLEntity3PixPQ2t4List1Z10VHDLEntity7element +List::Pix::Pix(List::element *) +List::Pix::Pix +# +--format=gnu --no-params +__Q2t4List1Z10VHDLEntity3PixRCQ2t4List1Z10VHDLEntity3Pix +List::Pix::Pix(List::Pix const &) +List::Pix::Pix +# +--format=gnu --no-params +__Q2t4List1Z10VHDLEntity7elementRC10VHDLEntityPT0 +List::element::element(VHDLEntity const &, List::element *) +List::element::element +# +--format=gnu --no-params +__Q2t4List1Z10VHDLEntity7elementRCQ2t4List1Z10VHDLEntity7element +List::element::element(List::element const &) +List::element::element +# +--format=gnu --no-params +__cl__C11VHDLLibraryGt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity +VHDLLibrary::operator()(PixX >) const +VHDLLibrary::operator() +# +--format=gnu --no-params +__cl__Ct4List1Z10VHDLEntityRCQ2t4List1Z10VHDLEntity3Pix +List::operator()(List::Pix const &) const +List::operator() +# +--format=gnu --no-params +__ne__FPvRCQ2t4List1Z10VHDLEntity3Pix +operator!=(void *, List::Pix const &) +operator!= +# +--format=gnu --no-params +__ne__FPvRCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity +operator!=(void *, PixX > const &) +operator!= +# +--format=gnu --no-params +__t4List1Z10VHDLEntityRCt4List1Z10VHDLEntity +List::List(List const &) +List::List +# +--format=gnu --no-params +__t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity +PixX >::PixX(void) +PixX >::PixX +# +--format=gnu --no-params +__t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityP14VHDLLibraryRepGQ2t4List1Z10VHDLEntity3Pix +PixX >::PixX(VHDLLibraryRep *, List::Pix) +PixX >::PixX +# +--format=gnu --no-params +__t4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntityRCt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity +PixX >::PixX(PixX > const &) +PixX >::PixX +# +--format=gnu --no-params +nextE__C11VHDLLibraryRt4PixX3Z11VHDLLibraryZ14VHDLLibraryRepZt4List1Z10VHDLEntity +VHDLLibrary::nextE(PixX > &) const +VHDLLibrary::nextE +# +--format=gnu --no-params +next__Ct4List1Z10VHDLEntityRQ2t4List1Z10VHDLEntity3Pix +List::next(List::Pix &) const +List::next +# +--format=gnu --no-params +_GLOBAL_$D$set +global destructors keyed to set +global destructors keyed to set +# +--format=gnu --no-params +_GLOBAL_$I$set +global constructors keyed to set +global constructors keyed to set +# +--format=gnu --no-params +__as__t5ListS1ZUiRCt5ListS1ZUi +ListS::operator=(ListS const &) +ListS::operator= +# +--format=gnu --no-params +__cl__Ct5ListS1ZUiRCQ2t5ListS1ZUi3Vix +ListS::operator()(ListS::Vix const &) const +ListS::operator() +# +--format=gnu --no-params +__cl__Ct5SetLS1ZUiRCQ2t5SetLS1ZUi3Vix +SetLS::operator()(SetLS::Vix const &) const +SetLS::operator() +# +--format=gnu --no-params +__t10ListS_link1ZUiRCUiPT0 +ListS_link::ListS_link(unsigned int const &, ListS_link *) +ListS_link::ListS_link +# +--format=gnu --no-params +__t10ListS_link1ZUiRCt10ListS_link1ZUi +ListS_link::ListS_link(ListS_link const &) +ListS_link::ListS_link +# +--format=gnu --no-params +__t5ListS1ZUiRCt5ListS1ZUi +ListS::ListS(ListS const &) +ListS::ListS +# +--format=gnu --no-params +next__Ct5ListS1ZUiRQ2t5ListS1ZUi3Vix +ListS::next(ListS::Vix &) const +ListS::next +# +--format=gnu --no-params +__ne__FPvRCQ2t5SetLS1ZUi3Vix +operator!=(void *, SetLS::Vix const &) +operator!= +# +--format=gnu --no-params +__t8ListElem1Z5LabelRt4List1Z5Label +ListElem(A) +--format=gnu-v3 +_Z1hI1AEDTcldtfp_miEET_ +decltype (({parm#1}.(operator-))()) h(A) +--format=gnu-v3 +_Z1fDn +f(decltype(nullptr)) +--format=gnu-v3 +_ZN5aaaaa6bbbbbb5cccccIN23ddddddddddddddddddddddd3eeeENS2_4ffff16ggggggggggggggggENS0_9hhhhhhhhhES6_S6_S6_S6_S6_S6_S6_EE +aaaaa::bbbbbb::ccccc +--format=gnu-v3 +_Z5outerIsEcPFilE +char outer(int (*)(long)) +--format=gnu-v3 +_Z5outerPFsiEl +outer(short (*)(int), long) +--format=gnu-v3 +_Z6outer2IsEPFilES1_ +int (*outer2(int (*)(long)))(long) +--format=gnu-v3 --ret-postfix +_Z5outerIsEcPFilE +outer(int (*)(long))char +--format=gnu-v3 --ret-postfix +_Z5outerPFsiEl +outer(short (*)(int), long) +--format=gnu-v3 --ret-postfix +_Z6outer2IsEPFilES1_ +outer2(int (*)(long))int (*)(long) +--format=gnu-v3 --ret-drop +_Z5outerIsEcPFilE +outer(int (*)(long)) +--format=gnu-v3 --ret-drop +_Z5outerPFsiEl +outer(short (*)(int), long) +--format=gnu-v3 --ret-drop +_Z6outer2IsEPFilES1_ +outer2(int (*)(long)) +# +--format=gnu-v3 --no-params +_ZN1KIXadL_ZN1S1mEiEEE1fEv +K<&S::m>::f() +K<&S::m>::f +--format=gnu-v3 +_ZN1KILi1EXadL_ZN1S1mEiEEE1fEv +K<1, &S::m>::f() +# Here the `(int)' argument list of `S::m' is already removed. +--format=gnu-v3 +_ZN1KILi1EXadL_ZN1S1mEEEE1fEv +K<1, &S::m>::f() +# +# Ada (GNAT) tests. +# +# Simple test. +--format=gnat +yz__qrs +yz.qrs +# Operator +--format=gnat +oper__Oadd +oper."+" +# Overloaded subprogram. +--format=gnat +yz__qrs__2 +yz.qrs +# Nested subprogram. +--format=gnat +yz__qrs__tuv.1661 +yz.qrs.tuv +# Nested and overloaded subprograms. +--format=gnat +yz__qrs__tuv__2_1.1667 +yz.qrs.tuv +--format=gnat +yz__qrs__tuv__2_2.1670 +yz.qrs.tuv +--format=gnat +yz__qrs__tuv__2_3.1674 +yz.qrs.tuv +# Elaborated flag (not demangled) +--format=gnat +x_E + +# Nested package +--format=gnat +x__m1 +x.m1 +--format=gnat +x__m3 +x.m3 +--format=gnat +x__y__m2X +x.y.m2 +--format=gnat +x__y__z__rXb +x.y.z.r +# Child package +--format=gnat +x__y__j +x.y.j +# Library level +--format=gnat +_ada_x__m3 +x.m3 +# Package body elaborator +--format=gnat +p___elabb +p'Elab_Body +# Package spec elaborator +--format=gnat +p___elabs +p'Elab_Spec +# Task body +--format=gnat +p__taskobjTKB +p.taskobj +# Task subprogram +--format=gnat +p__taskobjTK__f1.2330 +p.taskobj.f1 +# Protected types subprograms +--format=gnat +prot__lock__getN +prot.lock.get +--format=gnat +prot__lock__getP +prot.lock.get +--format=gnat +prot__lock__get__sub.2590 +prot.lock.get.sub +--format=gnat +prot__lock__setN +prot.lock.set +--format=gnat +prot__lock__setP +prot.lock.set +# Protected type entries +--format=gnat +prot__lock__update_B7s +prot.lock.update +--format=gnat +prot__lock__update_E6s +prot.lock.update +# Controlled types +--format=gnat +gnat__sockets__sockets_library_controllerDF__2 +gnat.sockets.sockets_library_controller.Finalize +--format=gnat +system__partition_interface__racw_stub_typeDA +system.partition_interface.racw_stub_type.Adjust +# Stream operations +--format=gnat +gnat__wide_wide_string_split__slice_setSR__2 +gnat.wide_wide_string_split.slice_set'Read +--format=gnat +ada__real_time__timing_events__events__listSW__2Xnn +ada.real_time.timing_events.events.list'Write +--format=gnat +system__finalization_root__root_controlledSI +system.finalization_root.root_controlled'Input +--format=gnat +ada__finalization__limited_controlledSO__2 +ada.finalization.limited_controlled'Output +# Tagged types +--format=gnat +ada__synchronous_task_control___size__2 +ada.synchronous_task_control'Size +--format=gnat +ada__real_time__timing_events__events___alignment__2Xnn +ada.real_time.timing_events.events'Alignment +--format=gnat +system__finalization_root___assign__2 +system.finalization_root.":=" +# +# Used to crash the demangler. +--format=gnu-v3 +DFA +DFA +# +# http://sourceware.org/bugzilla/show_bug.cgi?id=11572 +--format=auto +_ZN3Psi7VariantIIcPKcEE5visitIIRZN11VariantTest9TestVisit11test_methodEvEUlS2_E0_RZNS6_11test_methodEvEUlcE1_RZNS6_11test_methodEvEUlNS_4NoneEE_EEENS_13VariantDetail19SelectVisitorResultIIDpT_EE4typeEDpOSG_ +Psi::VariantDetail::SelectVisitorResult::type Psi::Variant::visit((VariantTest::TestVisit::test_method()::{lambda(Psi::None)#1}&&&)...) diff --git a/external/gpl3/gdb/dist/libiberty/testsuite/test-demangle.c b/external/gpl3/gdb/dist/libiberty/testsuite/test-demangle.c new file mode 100644 index 000000000000..11d9729999b8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/testsuite/test-demangle.c @@ -0,0 +1,349 @@ +/* Demangler test program, + Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc. + Written by Zack Weinberg +#include "libiberty.h" +#include "demangle.h" +#ifdef HAVE_STRING_H +#include +#endif +#if HAVE_STDLIB_H +# include +#endif + +struct line +{ + size_t alloced; + char *data; +}; + +static unsigned int lineno; + +/* Safely read a single line of arbitrary length from standard input. */ + +#define LINELEN 80 + +static void +get_line(buf) + struct line *buf; +{ + char *data = buf->data; + size_t alloc = buf->alloced; + size_t count = 0; + int c; + + if (data == 0) + { + data = xmalloc (LINELEN); + alloc = LINELEN; + } + + /* Skip comment lines. */ + while ((c = getchar()) == '#') + { + while ((c = getchar()) != EOF && c != '\n'); + lineno++; + } + + /* c is the first character on the line, and it's not a comment + line: copy this line into the buffer and return. */ + while (c != EOF && c != '\n') + { + if (count + 1 >= alloc) + { + alloc *= 2; + data = xrealloc (data, alloc); + } + data[count++] = c; + c = getchar(); + } + lineno++; + data[count] = '\0'; + + buf->data = data; + buf->alloced = alloc; +} + +/* If we have mmap() and mprotect(), copy the string S just before a + protected page, so that if the demangler runs over the end of the + string we'll get a fault, and return the address of the new string. + If no mmap, or it fails, or it looks too hard, just return S. */ + +#ifdef HAVE_SYS_MMAN_H +#include +#endif +#if defined(MAP_ANON) && ! defined (MAP_ANONYMOUS) +#define MAP_ANONYMOUS MAP_ANON +#endif + +static const char * +protect_end (const char * s) +{ +#if defined(HAVE_MMAP) && defined (MAP_ANONYMOUS) + size_t pagesize = getpagesize(); + static char * buf; + size_t s_len = strlen (s); + char * result; + + /* Don't try if S is too long. */ + if (s_len >= pagesize) + return s; + + /* Allocate one page of allocated space followed by an unmapped + page. */ + if (buf == NULL) + { + buf = mmap (NULL, pagesize * 2, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (! buf) + return s; + munmap (buf + pagesize, pagesize); + } + + result = buf + (pagesize - s_len - 1); + memcpy (result, s, s_len + 1); + return result; +#else + return s; +#endif +} + +static void +fail (lineno, opts, in, out, exp) + int lineno; + const char *opts; + const char *in; + const char *out; + const char *exp; +{ + printf ("\ +FAIL at line %d, options %s:\n\ +in: %s\n\ +out: %s\n\ +exp: %s\n", + lineno, opts, in, out != NULL ? out : "(null)", exp); +} + +/* The tester operates on a data file consisting of groups of lines: + options + input to be demangled + expected output + + Supported options: + --format= Sets the demangling style. + --no-params There are two lines of expected output; the first + is with DMGL_PARAMS, the second is without it. + --is-v3-ctor Calls is_gnu_v3_mangled_ctor on input; expected + output is an integer representing ctor_kind. + --is-v3-dtor Likewise, but for dtors. + --ret-postfix Passes the DMGL_RET_POSTFIX option + --ret-drop Passes the DMGL_RET_DROP option + + For compatibility, just in case it matters, the options line may be + empty, to mean --format=auto. If it doesn't start with --, then it + may contain only a format name. +*/ + +int +main(argc, argv) + int argc; + char **argv; +{ + enum demangling_styles style = auto_demangling; + int no_params; + int is_v3_ctor; + int is_v3_dtor; + int ret_postfix, ret_drop; + struct line format; + struct line input; + struct line expect; + char *result; + int failures = 0; + int tests = 0; + + if (argc > 1) + { + fprintf (stderr, "usage: %s < test-set\n", argv[0]); + return 2; + } + + format.data = 0; + input.data = 0; + expect.data = 0; + + for (;;) + { + const char *inp; + + get_line (&format); + if (feof (stdin)) + break; + + get_line (&input); + get_line (&expect); + + inp = protect_end (input.data); + + tests++; + + no_params = 0; + ret_postfix = 0; + ret_drop = 0; + is_v3_ctor = 0; + is_v3_dtor = 0; + if (format.data[0] == '\0') + style = auto_demangling; + else if (format.data[0] != '-') + { + style = cplus_demangle_name_to_style (format.data); + if (style == unknown_demangling) + { + printf ("FAIL at line %d: unknown demangling style %s\n", + lineno, format.data); + failures++; + continue; + } + } + else + { + char *p; + char *opt; + + p = format.data; + while (*p != '\0') + { + char c; + + opt = p; + p += strcspn (p, " \t="); + c = *p; + *p = '\0'; + if (strcmp (opt, "--format") == 0 && c == '=') + { + char *fstyle; + + *p = c; + ++p; + fstyle = p; + p += strcspn (p, " \t"); + c = *p; + *p = '\0'; + style = cplus_demangle_name_to_style (fstyle); + if (style == unknown_demangling) + { + printf ("FAIL at line %d: unknown demangling style %s\n", + lineno, fstyle); + failures++; + continue; + } + } + else if (strcmp (opt, "--no-params") == 0) + no_params = 1; + else if (strcmp (opt, "--is-v3-ctor") == 0) + is_v3_ctor = 1; + else if (strcmp (opt, "--is-v3-dtor") == 0) + is_v3_dtor = 1; + else if (strcmp (opt, "--ret-postfix") == 0) + ret_postfix = 1; + else if (strcmp (opt, "--ret-drop") == 0) + ret_drop = 1; + else + { + printf ("FAIL at line %d: unrecognized option %s\n", + lineno, opt); + failures++; + continue; + } + *p = c; + p += strspn (p, " \t"); + } + } + + if (is_v3_ctor || is_v3_dtor) + { + char buf[20]; + + if (is_v3_ctor) + { + enum gnu_v3_ctor_kinds kc; + + kc = is_gnu_v3_mangled_ctor (inp); + sprintf (buf, "%d", (int) kc); + } + else + { + enum gnu_v3_dtor_kinds kd; + + kd = is_gnu_v3_mangled_dtor (inp); + sprintf (buf, "%d", (int) kd); + } + + if (strcmp (buf, expect.data) != 0) + { + fail (lineno, format.data, input.data, buf, expect.data); + failures++; + } + + continue; + } + + cplus_demangle_set_style (style); + + result = cplus_demangle (inp, (DMGL_PARAMS | DMGL_ANSI | DMGL_TYPES + | (ret_postfix ? DMGL_RET_POSTFIX : 0) + | (ret_drop ? DMGL_RET_DROP : 0))); + + if (result + ? strcmp (result, expect.data) + : strcmp (input.data, expect.data)) + { + fail (lineno, format.data, input.data, result, expect.data); + failures++; + } + free (result); + + if (no_params) + { + get_line (&expect); + result = cplus_demangle (inp, DMGL_ANSI|DMGL_TYPES); + + if (result + ? strcmp (result, expect.data) + : strcmp (input.data, expect.data)) + { + fail (lineno, format.data, input.data, result, expect.data); + failures++; + } + free (result); + } + } + + free (format.data); + free (input.data); + free (expect.data); + + printf ("%s: %d tests, %d failures\n", argv[0], tests, failures); + return failures ? 1 : 0; +} diff --git a/external/gpl3/gdb/dist/libiberty/testsuite/test-expandargv.c b/external/gpl3/gdb/dist/libiberty/testsuite/test-expandargv.c new file mode 100644 index 000000000000..c16a0322a6c4 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/testsuite/test-expandargv.c @@ -0,0 +1,328 @@ +/* expandargv test program, + Copyright (C) 2006 Free Software Foundation, Inc. + Written by Carlos O'Donell + + This file is part of the libiberty library, which is part of GCC. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combined + executable.) + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "libiberty.h" +#include +#include +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#endif + +#ifndef EXIT_SUCCESS +#define EXIT_SUCCESS 0 +#endif + +#ifndef EXIT_FAILURE +#define EXIT_FAILURE 1 +#endif + +static void fatal_error (int, const char *, int) ATTRIBUTE_NORETURN; +void writeout_test (int, const char *); +void run_replaces (char *); +void hook_char_replace (char *, size_t, char, char); +int run_tests (const char **); +void erase_test (int); + +/* Test input data, argv before, and argv after: + + The \n is an important part of test_data since expandargv + may have to work in environments where \n is translated + as \r\n. Thus \n is included in the test data for the file. + + We use \b to indicate that the test data is the null character. + This is because we use \0 normally to represent the end of the + file data, so we need something else for this. */ + +#define FILENAME_PATTERN "test-expandargv-%d.lst" +#define ARGV0 "test-expandargv" + +const char *test_data[] = { + /* Test 0 - Check for expansion with \r\n */ + "a\r\nb", /* Test 0 data */ + ARGV0, + "@test-expandargv-0.lst", + 0, /* End of argv[] before expansion */ + ARGV0, + "a", + "b", + 0, /* End of argv[] after expansion */ + + /* Test 1 - Check for expansion with \n */ + "a\nb", /* Test 1 data */ + ARGV0, + "@test-expandargv-1.lst", + 0, + ARGV0, + "a", + "b", + 0, + + /* Test 2 - Check for expansion with \0 */ + "a\bb", /* Test 2 data */ + ARGV0, + "@test-expandargv-2.lst", + 0, + ARGV0, + "a", + 0, + + /* Test 3 - Check for expansion with only \0 */ + "\b", /* Test 3 data */ + ARGV0, + "@test-expandargv-3.lst", + 0, + ARGV0, + 0, + + /* Test 4 - Check for options beginning with an empty line. */ + "\na\nb", /* Test 4 data */ + ARGV0, + "@test-expandargv-4.lst", + 0, + ARGV0, + "a", + "b", + 0, + + /* Test 5 - Check for options containing an empty argument. */ + "a\n''\nb", /* Test 5 data */ + ARGV0, + "@test-expandargv-5.lst", + 0, + ARGV0, + "a", + "", + "b", + 0, + + /* Test 6 - Check for options containing a quoted newline. */ + "a\n'a\n\nb'\nb", /* Test 6 data */ + ARGV0, + "@test-expandargv-6.lst", + 0, + ARGV0, + "a", + "a\n\nb", + "b", + 0, + + 0 /* Test done marker, don't remove. */ +}; + +/* Print a fatal error and exit. LINE is the line number where we + detected the error, ERRMSG is the error message to print, and ERR + is 0 or an errno value to print. */ + +static void +fatal_error (int line, const char *errmsg, int err) +{ + fprintf (stderr, "test-expandargv:%d: %s", line, errmsg); + if (errno != 0) + fprintf (stderr, ": %s", xstrerror (err)); + fprintf (stderr, "\n"); + exit (EXIT_FAILURE); +} + +/* hook_char_replace: + Replace 'replacethis' with 'withthis' */ + +void +hook_char_replace (char *string, size_t len, char replacethis, char withthis) +{ + int i = 0; + for (i = 0; i < len; i++) + if (string[i] == replacethis) + string[i] = withthis; +} + +/* run_replaces: + Hook here all the character for character replaces. + Be warned that expanding the string or contracting the string + should be handled with care. */ + +void +run_replaces (char * string) +{ + /* Store original string size */ + size_t len = strlen (string); + hook_char_replace (string, len, '\b', '\0'); +} + +/* write_test: + Write test datafile */ + +void +writeout_test (int test, const char * test_data) +{ + char filename[256]; + FILE *fd; + size_t len; + char * parse; + + /* Unique filename per test */ + sprintf (filename, FILENAME_PATTERN, test); + fd = fopen (filename, "w"); + if (fd == NULL) + fatal_error (__LINE__, "Failed to create test file.", errno); + + /* Generate RW copy of data for replaces */ + len = strlen (test_data); + parse = malloc (sizeof (char) * (len + 1)); + if (parse == NULL) + fatal_error (__LINE__, "Failed to malloc parse.", errno); + + memcpy (parse, test_data, sizeof (char) * len); + /* Run all possible replaces */ + run_replaces (parse); + + fwrite (parse, len, sizeof (char), fd); + free (parse); + fclose (fd); +} + +/* erase_test: + Erase the test file */ + +void +erase_test (int test) +{ + char filename[256]; + sprintf (filename, FILENAME_PATTERN, test); + if (unlink (filename) != 0) + fatal_error (__LINE__, "Failed to erase test file.", errno); +} + + +/* run_tests: + Run expandargv + Compare argv before and after. + Return number of fails */ + +int +run_tests (const char **test_data) +{ + int argc_after, argc_before; + char ** argv_before, ** argv_after; + int i, j, k, fails, failed; + + i = j = fails = 0; + /* Loop over all the tests */ + while (test_data[j]) + { + /* Write test data */ + writeout_test (i, test_data[j++]); + /* Copy argv before */ + argv_before = dupargv ((char **) &test_data[j]); + + /* Count argc before/after */ + argc_before = 0; + argc_after = 0; + while (test_data[j + argc_before]) + argc_before++; + j += argc_before + 1; /* Skip null */ + while (test_data[j + argc_after]) + argc_after++; + + /* Copy argv after */ + argv_after = dupargv ((char **) &test_data[j]); + + /* Run all possible replaces */ + for (k = 0; k < argc_before; k++) + run_replaces (argv_before[k]); + for (k = 0; k < argc_after; k++) + run_replaces (argv_after[k]); + + /* Run test: Expand arguments */ + expandargv (&argc_before, &argv_before); + + failed = 0; + /* Compare size first */ + if (argc_before != argc_after) + { + printf ("FAIL: test-expandargv-%d. Number of arguments don't match.\n", i); + failed++; + } + /* Compare each of the argv's ... */ + else + for (k = 0; k < argc_after; k++) + if (strcmp (argv_before[k], argv_after[k]) != 0) + { + printf ("FAIL: test-expandargv-%d. Arguments don't match.\n", i); + failed++; + } + + if (!failed) + printf ("PASS: test-expandargv-%d.\n", i); + else + fails++; + + freeargv (argv_before); + freeargv (argv_after); + /* Advance to next test */ + j += argc_after + 1; + /* Erase test file */ + erase_test (i); + i++; + } + return fails; +} + +/* main: + Run tests. + Check result and exit with appropriate code. */ + +int +main(int argc, char **argv) +{ + int fails; + /* Repeat for all the tests: + - Parse data array and write into file. + - Run replace hooks before writing to file. + - Parse data array and build argv before/after. + - Run replace hooks on argv before/after + - Run expandargv. + - Compare output of expandargv argv to after argv. + - If they compare the same then test passes + else the test fails. + - Erase test file. */ + + fails = run_tests (test_data); + if (!fails) + exit (EXIT_SUCCESS); + else + exit (EXIT_FAILURE); +} + diff --git a/external/gpl3/gdb/dist/libiberty/testsuite/test-pexecute.c b/external/gpl3/gdb/dist/libiberty/testsuite/test-pexecute.c new file mode 100644 index 000000000000..8e01fda479a8 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/testsuite/test-pexecute.c @@ -0,0 +1,522 @@ +/* Pexecute test program, + Copyright (C) 2005 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU libiberty. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" +#include +#include +#include +#ifdef HAVE_STRING_H +#include +#endif +#include +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_SYS_WAIT_H +#include +#endif +#ifdef HAVE_SYS_TIME_H +#include +#endif +#ifdef HAVE_SYS_RESOURCE_H +#include +#endif + +#ifndef WIFSIGNALED +#define WIFSIGNALED(S) (((S) & 0xff) != 0 && ((S) & 0xff) != 0x7f) +#endif +#ifndef WTERMSIG +#define WTERMSIG(S) ((S) & 0x7f) +#endif +#ifndef WIFEXITED +#define WIFEXITED(S) (((S) & 0xff) == 0) +#endif +#ifndef WEXITSTATUS +#define WEXITSTATUS(S) (((S) & 0xff00) >> 8) +#endif +#ifndef WSTOPSIG +#define WSTOPSIG WEXITSTATUS +#endif +#ifndef WCOREDUMP +#define WCOREDUMP(S) ((S) & WCOREFLG) +#endif +#ifndef WCOREFLG +#define WCOREFLG 0200 +#endif + +#ifndef EXIT_SUCCESS +#define EXIT_SUCCESS 0 +#endif + +#ifndef EXIT_FAILURE +#define EXIT_FAILURE 1 +#endif + +/* When this program is run with no arguments, it runs some tests of + the libiberty pexecute functions. As a test program, it simply + invokes itself with various arguments. + + argv[1]: + *empty string* Run tests, exit with success status + exit Exit success + error Exit error + abort Abort + echo Echo remaining arguments, exit success + echoerr Echo next arg to stdout, next to stderr, repeat + copy Copy stdin to stdout + write Write stdin to file named in next argument +*/ + +static void fatal_error (int, const char *, int) ATTRIBUTE_NORETURN; +static void error (int, const char *); +static void check_line (int, FILE *, const char *); +static void do_cmd (int, char **) ATTRIBUTE_NORETURN; + +/* The number of errors we have seen. */ + +static int error_count; + +/* Print a fatal error and exit. LINE is the line number where we + detected the error, ERRMSG is the error message to print, and ERR + is 0 or an errno value to print. */ + +static void +fatal_error (int line, const char *errmsg, int err) +{ + fprintf (stderr, "test-pexecute:%d: %s", line, errmsg); + if (errno != 0) + fprintf (stderr, ": %s", xstrerror (err)); + fprintf (stderr, "\n"); + exit (EXIT_FAILURE); +} + +#define FATAL_ERROR(ERRMSG, ERR) fatal_error (__LINE__, ERRMSG, ERR) + +/* Print an error message and bump the error count. LINE is the line + number where we detected the error, ERRMSG is the error to + print. */ + +static void +error (int line, const char *errmsg) +{ + fprintf (stderr, "test-pexecute:%d: %s\n", line, errmsg); + ++error_count; +} + +#define ERROR(ERRMSG) error (__LINE__, ERRMSG) + +/* Check a line in a file. */ + +static void +check_line (int line, FILE *e, const char *str) +{ + const char *p; + int c; + char buf[1000]; + + p = str; + while (1) + { + c = getc (e); + + if (*p == '\0') + { + if (c != '\n') + { + snprintf (buf, sizeof buf, "got '%c' when expecting newline", c); + fatal_error (line, buf, 0); + } + c = getc (e); + if (c != EOF) + { + snprintf (buf, sizeof buf, "got '%c' when expecting EOF", c); + fatal_error (line, buf, 0); + } + return; + } + + if (c != *p) + { + snprintf (buf, sizeof buf, "expected '%c', got '%c'", *p, c); + fatal_error (line, buf, 0); + } + + ++p; + } +} + +#define CHECK_LINE(E, STR) check_line (__LINE__, E, STR) + +/* Main function for the pexecute tester. Run the tests. */ + +int +main (int argc, char **argv) +{ + int trace; + struct pex_obj *test_pex_tmp; + int test_pex_status; + FILE *test_pex_file; + struct pex_obj *pex1; + char *subargv[10]; + int status; + FILE *e; + int statuses[10]; + + trace = 0; + if (argc > 1 && strcmp (argv[1], "-t") == 0) + { + trace = 1; + --argc; + ++argv; + } + + if (argc > 1) + do_cmd (argc, argv); + +#define TEST_PEX_INIT(FLAGS, TEMPBASE) \ + (((test_pex_tmp = pex_init (FLAGS, "test-pexecute", TEMPBASE)) \ + != NULL) \ + ? test_pex_tmp \ + : (FATAL_ERROR ("pex_init failed", 0), NULL)) + +#define TEST_PEX_RUN(PEXOBJ, FLAGS, EXECUTABLE, ARGV, OUTNAME, ERRNAME) \ + do \ + { \ + int err; \ + const char *pex_run_err; \ + if (trace) \ + fprintf (stderr, "Line %d: running %s %s\n", \ + __LINE__, EXECUTABLE, ARGV[0]); \ + pex_run_err = pex_run (PEXOBJ, FLAGS, EXECUTABLE, ARGV, OUTNAME, \ + ERRNAME, &err); \ + if (pex_run_err != NULL) \ + FATAL_ERROR (pex_run_err, err); \ + } \ + while (0) + +#define TEST_PEX_GET_STATUS_1(PEXOBJ) \ + (pex_get_status (PEXOBJ, 1, &test_pex_status) \ + ? test_pex_status \ + : (FATAL_ERROR ("pex_get_status failed", errno), 1)) + +#define TEST_PEX_GET_STATUS(PEXOBJ, COUNT, VECTOR) \ + do \ + { \ + if (!pex_get_status (PEXOBJ, COUNT, VECTOR)) \ + FATAL_ERROR ("pex_get_status failed", errno); \ + } \ + while (0) + +#define TEST_PEX_READ_OUTPUT(PEXOBJ) \ + ((test_pex_file = pex_read_output (PEXOBJ, 0)) != NULL \ + ? test_pex_file \ + : (FATAL_ERROR ("pex_read_output failed", errno), NULL)) + + remove ("temp.x"); + remove ("temp.y"); + + memset (subargv, 0, sizeof subargv); + + subargv[0] = "./test-pexecute"; + + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, NULL); + subargv[1] = "exit"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_LAST, "./test-pexecute", subargv, NULL, NULL); + status = TEST_PEX_GET_STATUS_1 (pex1); + if (!WIFEXITED (status) || WEXITSTATUS (status) != EXIT_SUCCESS) + ERROR ("exit failed"); + pex_free (pex1); + + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, NULL); + subargv[1] = "error"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_LAST, "./test-pexecute", subargv, NULL, NULL); + status = TEST_PEX_GET_STATUS_1 (pex1); + if (!WIFEXITED (status) || WEXITSTATUS (status) != EXIT_FAILURE) + ERROR ("error test failed"); + pex_free (pex1); + + /* We redirect stderr to a file to avoid an error message which is + printed on mingw32 when the child calls abort. */ + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, NULL); + subargv[1] = "abort"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_LAST, "./test-pexecute", subargv, NULL, "temp.z"); + status = TEST_PEX_GET_STATUS_1 (pex1); + if (!WIFSIGNALED (status) || WTERMSIG (status) != SIGABRT) + ERROR ("abort failed"); + pex_free (pex1); + remove ("temp.z"); + + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp"); + subargv[1] = "echo"; + subargv[2] = "foo"; + subargv[3] = NULL; + TEST_PEX_RUN (pex1, 0, "./test-pexecute", subargv, NULL, NULL); + e = TEST_PEX_READ_OUTPUT (pex1); + CHECK_LINE (e, "foo"); + if (TEST_PEX_GET_STATUS_1 (pex1) != 0) + ERROR ("echo exit status failed"); + pex_free (pex1); + + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp"); + subargv[1] = "echo"; + subargv[2] = "bar"; + subargv[3] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".x", NULL); + subargv[1] = "copy"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".y", NULL); + e = TEST_PEX_READ_OUTPUT (pex1); + CHECK_LINE (e, "bar"); + TEST_PEX_GET_STATUS (pex1, 2, statuses); + if (!WIFEXITED (statuses[0]) || WEXITSTATUS (statuses[0]) != EXIT_SUCCESS + || !WIFEXITED (statuses[1]) || WEXITSTATUS (statuses[1]) != EXIT_SUCCESS) + ERROR ("copy exit status failed"); + pex_free (pex1); + if (fopen ("temp.x", "r") != NULL || fopen ("temp.y", "r") != NULL) + ERROR ("temporary files exist"); + + pex1 = TEST_PEX_INIT (0, "temp"); + subargv[1] = "echo"; + subargv[2] = "bar"; + subargv[3] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".x", NULL); + subargv[1] = "copy"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".y", NULL); + e = TEST_PEX_READ_OUTPUT (pex1); + CHECK_LINE (e, "bar"); + TEST_PEX_GET_STATUS (pex1, 2, statuses); + if (!WIFEXITED (statuses[0]) || WEXITSTATUS (statuses[0]) != EXIT_SUCCESS + || !WIFEXITED (statuses[1]) || WEXITSTATUS (statuses[1]) != EXIT_SUCCESS) + ERROR ("copy exit status failed"); + pex_free (pex1); + if (fopen ("temp.x", "r") != NULL || fopen ("temp.y", "r") != NULL) + ERROR ("temporary files exist"); + + pex1 = TEST_PEX_INIT (PEX_SAVE_TEMPS, "temp"); + subargv[1] = "echo"; + subargv[2] = "quux"; + subargv[3] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".x", NULL); + subargv[1] = "copy"; + subargv[2] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".y", NULL); + e = TEST_PEX_READ_OUTPUT (pex1); + CHECK_LINE (e, "quux"); + TEST_PEX_GET_STATUS (pex1, 2, statuses); + if (!WIFEXITED (statuses[0]) || WEXITSTATUS (statuses[0]) != EXIT_SUCCESS + || !WIFEXITED (statuses[1]) || WEXITSTATUS (statuses[1]) != EXIT_SUCCESS) + ERROR ("copy temp exit status failed"); + e = fopen ("temp.x", "r"); + if (e == NULL) + FATAL_ERROR ("fopen temp.x failed in copy temp", errno); + CHECK_LINE (e, "quux"); + fclose (e); + e = fopen ("temp.y", "r"); + if (e == NULL) + FATAL_ERROR ("fopen temp.y failed in copy temp", errno); + CHECK_LINE (e, "quux"); + fclose (e); + pex_free (pex1); + remove ("temp.x"); + remove ("temp.y"); + + pex1 = TEST_PEX_INIT (PEX_USE_PIPES, "temp"); + subargv[1] = "echoerr"; + subargv[2] = "one"; + subargv[3] = "two"; + subargv[4] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".x", "temp2.x"); + subargv[1] = "write"; + subargv[2] = "temp2.y"; + subargv[3] = NULL; + TEST_PEX_RUN (pex1, PEX_SUFFIX, "./test-pexecute", subargv, ".y", NULL); + TEST_PEX_GET_STATUS (pex1, 2, statuses); + if (!WIFEXITED (statuses[0]) || WEXITSTATUS (statuses[0]) != EXIT_SUCCESS + || !WIFEXITED (statuses[1]) || WEXITSTATUS (statuses[1]) != EXIT_SUCCESS) + ERROR ("echoerr exit status failed"); + pex_free (pex1); + if (fopen ("temp.x", "r") != NULL || fopen ("temp.y", "r") != NULL) + ERROR ("temporary files exist"); + e = fopen ("temp2.x", "r"); + if (e == NULL) + FATAL_ERROR ("fopen temp2.x failed in echoerr", errno); + CHECK_LINE (e, "two"); + fclose (e); + e = fopen ("temp2.y", "r"); + if (e == NULL) + FATAL_ERROR ("fopen temp2.y failed in echoerr", errno); + CHECK_LINE (e, "one"); + fclose (e); + remove ("temp2.x"); + remove ("temp2.y"); + + /* Test the old pexecute interface. */ + { + int pid1, pid2; + char *errmsg_fmt; + char *errmsg_arg; + char errbuf1[1000]; + char errbuf2[1000]; + + subargv[1] = "echo"; + subargv[2] = "oldpexecute"; + subargv[3] = NULL; + pid1 = pexecute ("./test-pexecute", subargv, "test-pexecute", "temp", + &errmsg_fmt, &errmsg_arg, PEXECUTE_FIRST); + if (pid1 < 0) + { + snprintf (errbuf1, sizeof errbuf1, errmsg_fmt, errmsg_arg); + snprintf (errbuf2, sizeof errbuf2, "pexecute 1 failed: %s", errbuf1); + FATAL_ERROR (errbuf2, 0); + } + + subargv[1] = "write"; + subargv[2] = "temp.y"; + subargv[3] = NULL; + pid2 = pexecute ("./test-pexecute", subargv, "test-pexecute", "temp", + &errmsg_fmt, &errmsg_arg, PEXECUTE_LAST); + if (pid2 < 0) + { + snprintf (errbuf1, sizeof errbuf1, errmsg_fmt, errmsg_arg); + snprintf (errbuf2, sizeof errbuf2, "pexecute 2 failed: %s", errbuf1); + FATAL_ERROR (errbuf2, 0); + } + + if (pwait (pid1, &status, 0) < 0) + FATAL_ERROR ("write pwait 1 failed", errno); + if (!WIFEXITED (status) || WEXITSTATUS (status) != EXIT_SUCCESS) + ERROR ("write exit status 1 failed"); + + if (pwait (pid2, &status, 0) < 0) + FATAL_ERROR ("write pwait 1 failed", errno); + if (!WIFEXITED (status) || WEXITSTATUS (status) != EXIT_SUCCESS) + ERROR ("write exit status 2 failed"); + + e = fopen ("temp.y", "r"); + if (e == NULL) + FATAL_ERROR ("fopen temp.y failed in copy temp", errno); + CHECK_LINE (e, "oldpexecute"); + fclose (e); + + remove ("temp.y"); + } + + if (trace) + fprintf (stderr, "Exiting with status %d\n", error_count); + + return error_count; +} + +/* Execute one of the special testing commands. */ + +static void +do_cmd (int argc, char **argv) +{ + const char *s; + + /* Try to prevent generating a core dump. */ +#ifdef RLIMIT_CORE + { + struct rlimit r; + + r.rlim_cur = 0; + r.rlim_max = 0; + setrlimit (RLIMIT_CORE, &r); + } +#endif + + s = argv[1]; + if (strcmp (s, "exit") == 0) + exit (EXIT_SUCCESS); + else if (strcmp (s, "echo") == 0) + { + int i; + + for (i = 2; i < argc; ++i) + { + if (i > 2) + putchar (' '); + fputs (argv[i], stdout); + } + putchar ('\n'); + exit (EXIT_SUCCESS); + } + else if (strcmp (s, "echoerr") == 0) + { + int i; + + for (i = 2; i < argc; ++i) + { + if (i > 3) + putc (' ', (i & 1) == 0 ? stdout : stderr); + fputs (argv[i], (i & 1) == 0 ? stdout : stderr); + } + putc ('\n', stdout); + putc ('\n', stderr); + exit (EXIT_SUCCESS); + } + else if (strcmp (s, "error") == 0) + exit (EXIT_FAILURE); + else if (strcmp (s, "abort") == 0) + abort (); + else if (strcmp (s, "copy") == 0) + { + int c; + + while ((c = getchar ()) != EOF) + putchar (c); + exit (EXIT_SUCCESS); + } + else if (strcmp (s, "write") == 0) + { + FILE *e; + int c; + + e = fopen (argv[2], "w"); + if (e == NULL) + FATAL_ERROR ("fopen for write failed", errno); + while ((c = getchar ()) != EOF) + putc (c, e); + if (fclose (e) != 0) + FATAL_ERROR ("fclose for write failed", errno); + exit (EXIT_SUCCESS); + } + else + { + char buf[1000]; + + snprintf (buf, sizeof buf, "unrecognized command %s", argv[1]); + FATAL_ERROR (buf, 0); + } + + exit (EXIT_FAILURE); +} diff --git a/external/gpl3/gdb/dist/libiberty/tmpnam.c b/external/gpl3/gdb/dist/libiberty/tmpnam.c new file mode 100644 index 000000000000..cc343336642f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/tmpnam.c @@ -0,0 +1,52 @@ +/* + +@deftypefn Supplemental char* tmpnam (char *@var{s}) + +This function attempts to create a name for a temporary file, which +will be a valid file name yet not exist when @code{tmpnam} checks for +it. @var{s} must point to a buffer of at least @code{L_tmpnam} bytes, +or be @code{NULL}. Use of this function creates a security risk, and it must +not be used in new projects. Use @code{mkstemp} instead. + +@end deftypefn + +*/ + +#include + +#ifndef L_tmpnam +#define L_tmpnam 100 +#endif +#ifndef P_tmpdir +#define P_tmpdir "/usr/tmp" +#endif + +static char tmpnam_buffer[L_tmpnam]; +static int tmpnam_counter; + +extern int getpid (void); + +char * +tmpnam (char *s) +{ + int pid = getpid (); + + if (s == NULL) + s = tmpnam_buffer; + + /* Generate the filename and make sure that there isn't one called + it already. */ + + while (1) + { + FILE *f; + sprintf (s, "%s/%s%x.%x", P_tmpdir, "t", pid, tmpnam_counter); + f = fopen (s, "r"); + if (f == NULL) + break; + tmpnam_counter++; + fclose (f); + } + + return s; +} diff --git a/external/gpl3/gdb/dist/libiberty/unlink-if-ordinary.c b/external/gpl3/gdb/dist/libiberty/unlink-if-ordinary.c new file mode 100644 index 000000000000..c03b4dd7c706 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/unlink-if-ordinary.c @@ -0,0 +1,72 @@ +/* unlink-if-ordinary.c - remove link to a file unless it is special + Copyright (C) 2004, 2005 Free Software Foundation, Inc. + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental int unlink_if_ordinary (const char*) + +Unlinks the named file, unless it is special (e.g. a device file). +Returns 0 when the file was unlinked, a negative value (and errno set) when +there was an error deleting the file, and a positive value if no attempt +was made to unlink the file because it is special. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +#ifdef HAVE_UNISTD_H +#include +#endif +#if HAVE_SYS_STAT_H +#include +#endif + +#include "libiberty.h" + +#ifndef S_ISLNK +#ifdef S_IFLNK +#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) +#else +#define S_ISLNK(m) 0 +#define lstat stat +#endif +#endif + +int +unlink_if_ordinary (const char *name) +{ + struct stat st; + + if (lstat (name, &st) == 0 + && (S_ISREG (st.st_mode) || S_ISLNK (st.st_mode))) + return unlink (name); + + return 1; +} diff --git a/external/gpl3/gdb/dist/libiberty/vasprintf.c b/external/gpl3/gdb/dist/libiberty/vasprintf.c new file mode 100644 index 000000000000..85de5429fce6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vasprintf.c @@ -0,0 +1,197 @@ +/* Like vsprintf but provides a pointer to malloc'd storage, which must + be freed by the caller. + Copyright (C) 1994, 2003, 2011 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#include +#if !defined (va_copy) && defined (__va_copy) +# define va_copy(d,s) __va_copy((d),(s)) +#endif +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#else +extern unsigned long strtoul (); +extern PTR malloc (); +#endif +#include "libiberty.h" + +#ifdef TEST +int global_total_width; +#endif + +/* + +@deftypefn Extension int vasprintf (char **@var{resptr}, @ + const char *@var{format}, va_list @var{args}) + +Like @code{vsprintf}, but instead of passing a pointer to a buffer, +you pass a pointer to a pointer. This function will compute the size +of the buffer needed, allocate memory with @code{malloc}, and store a +pointer to the allocated memory in @code{*@var{resptr}}. The value +returned is the same as @code{vsprintf} would return. If memory could +not be allocated, minus one is returned and @code{NULL} is stored in +@code{*@var{resptr}}. + +@end deftypefn + +*/ + +static int int_vasprintf (char **, const char *, va_list); + +static int +int_vasprintf (char **result, const char *format, va_list args) +{ + const char *p = format; + /* Add one to make sure that it is never zero, which might cause malloc + to return NULL. */ + int total_width = strlen (format) + 1; + va_list ap; + +#ifdef va_copy + va_copy (ap, args); +#else + memcpy ((PTR) &ap, (PTR) &args, sizeof (va_list)); +#endif + + while (*p != '\0') + { + if (*p++ == '%') + { + while (strchr ("-+ #0", *p)) + ++p; + if (*p == '*') + { + ++p; + total_width += abs (va_arg (ap, int)); + } + else + total_width += strtoul (p, (char **) &p, 10); + if (*p == '.') + { + ++p; + if (*p == '*') + { + ++p; + total_width += abs (va_arg (ap, int)); + } + else + total_width += strtoul (p, (char **) &p, 10); + } + while (strchr ("hlL", *p)) + ++p; + /* Should be big enough for any format specifier except %s and floats. */ + total_width += 30; + switch (*p) + { + case 'd': + case 'i': + case 'o': + case 'u': + case 'x': + case 'X': + case 'c': + (void) va_arg (ap, int); + break; + case 'f': + case 'e': + case 'E': + case 'g': + case 'G': + (void) va_arg (ap, double); + /* Since an ieee double can have an exponent of 307, we'll + make the buffer wide enough to cover the gross case. */ + total_width += 307; + break; + case 's': + total_width += strlen (va_arg (ap, char *)); + break; + case 'p': + case 'n': + (void) va_arg (ap, char *); + break; + } + p++; + } + } +#ifdef va_copy + va_end (ap); +#endif +#ifdef TEST + global_total_width = total_width; +#endif + *result = (char *) malloc (total_width); + if (*result != NULL) + return vsprintf (*result, format, args); + else + return -1; +} + +int +vasprintf (char **result, const char *format, +#if defined (_BSD_VA_LIST_) && defined (__FreeBSD__) + _BSD_VA_LIST_ args) +#else + va_list args) +#endif +{ + return int_vasprintf (result, format, args); +} + +#ifdef TEST +static void ATTRIBUTE_PRINTF_1 +checkit (const char *format, ...) +{ + char *result; + VA_OPEN (args, format); + VA_FIXEDARG (args, const char *, format); + vasprintf (&result, format, args); + VA_CLOSE (args); + + if (strlen (result) < (size_t) global_total_width) + printf ("PASS: "); + else + printf ("FAIL: "); + printf ("%d %s\n", global_total_width, result); + + free (result); +} + +extern int main (void); + +int +main (void) +{ + checkit ("%d", 0x12345678); + checkit ("%200d", 5); + checkit ("%.300d", 6); + checkit ("%100.150d", 7); + checkit ("%s", "jjjjjjjjjiiiiiiiiiiiiiiioooooooooooooooooppppppppppppaa\n\ +777777777777777777333333333333366666666666622222222222777777777777733333"); + checkit ("%f%s%d%s", 1.0, "foo", 77, "asdjffffffffffffffiiiiiiiiiiixxxxx"); + + return 0; +} +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/libiberty/vfork.c b/external/gpl3/gdb/dist/libiberty/vfork.c new file mode 100644 index 000000000000..eb4ff622b44f --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vfork.c @@ -0,0 +1,22 @@ +/* Emulate vfork using just plain fork, for systems without a real vfork. + This function is in the public domain. */ + +/* + +@deftypefn Supplemental int vfork (void) + +Emulates @code{vfork} by calling @code{fork} and returning its value. + +@end deftypefn + +*/ + +#include "ansidecl.h" + +extern int fork (void); + +int +vfork (void) +{ + return (fork ()); +} diff --git a/external/gpl3/gdb/dist/libiberty/vfprintf.c b/external/gpl3/gdb/dist/libiberty/vfprintf.c new file mode 100644 index 000000000000..9bd3ed555d07 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vfprintf.c @@ -0,0 +1,15 @@ +/* Provide a version vfprintf in terms of _doprnt. + By Kaveh Ghazi (ghazi@caip.rutgers.edu) 3/29/98 + Copyright (C) 1998 Free Software Foundation, Inc. + */ + +#include "ansidecl.h" +#include +#include +#undef vfprintf + +int +vfprintf (FILE *stream, const char *format, va_list ap) +{ + return _doprnt (format, ap, stream); +} diff --git a/external/gpl3/gdb/dist/libiberty/vprintf.c b/external/gpl3/gdb/dist/libiberty/vprintf.c new file mode 100644 index 000000000000..c3193ac8196e --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vprintf.c @@ -0,0 +1,28 @@ +/* + +@deftypefn Supplemental int vprintf (const char *@var{format}, va_list @var{ap}) +@deftypefnx Supplemental int vfprintf (FILE *@var{stream}, @ + const char *@var{format}, va_list @var{ap}) +@deftypefnx Supplemental int vsprintf (char *@var{str}, @ + const char *@var{format}, va_list @var{ap}) + +These functions are the same as @code{printf}, @code{fprintf}, and +@code{sprintf}, respectively, except that they are called with a +@code{va_list} instead of a variable number of arguments. Note that +they do not call @code{va_end}; this is the application's +responsibility. In @libib{} they are implemented in terms of the +nonstandard but common function @code{_doprnt}. + +@end deftypefn + +*/ + +#include +#include +#include +#undef vprintf +int +vprintf (const char *format, va_list ap) +{ + return vfprintf (stdout, format, ap); +} diff --git a/external/gpl3/gdb/dist/libiberty/vsnprintf.c b/external/gpl3/gdb/dist/libiberty/vsnprintf.c new file mode 100644 index 000000000000..6c0afa6726cb --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vsnprintf.c @@ -0,0 +1,148 @@ +/* Implement the vsnprintf function. + Copyright (C) 2003, 2004, 2005, 2011 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +/* + +@deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, @ + const char *@var{format}, va_list @var{ap}) + +This function is similar to @code{vsprintf}, but it will write to +@var{buf} at most @code{@var{n}-1} bytes of text, followed by a +terminating null byte, for a total of @var{n} bytes. On error the +return value is -1, otherwise it returns the number of characters that +would have been printed had @var{n} been sufficiently large, +regardless of the actual value of @var{n}. Note some pre-C99 system +libraries do not implement this correctly so users cannot generally +rely on the return value if the system version of this function is +used. + +@end deftypefn + +*/ + +#include "config.h" +#include "ansidecl.h" + +#include +#ifdef HAVE_STRING_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "libiberty.h" + +/* This implementation relies on a working vasprintf. */ +int +vsnprintf (char *s, size_t n, const char *format, va_list ap) +{ + char *buf = 0; + int result = vasprintf (&buf, format, ap); + + if (!buf) + return -1; + if (result < 0) + { + free (buf); + return -1; + } + + result = strlen (buf); + if (n > 0) + { + if ((long) n > result) + memcpy (s, buf, result+1); + else + { + memcpy (s, buf, n-1); + s[n - 1] = 0; + } + } + free (buf); + return result; +} + +#ifdef TEST +/* Set the buffer to a known state. */ +#define CLEAR(BUF) do { memset ((BUF), 'X', sizeof (BUF)); (BUF)[14] = '\0'; } while (0) +/* For assertions. */ +#define VERIFY(P) do { if (!(P)) abort(); } while (0) + +static int ATTRIBUTE_PRINTF_3 +checkit (char *s, size_t n, const char *format, ...) +{ + int result; + VA_OPEN (ap, format); + VA_FIXEDARG (ap, char *, s); + VA_FIXEDARG (ap, size_t, n); + VA_FIXEDARG (ap, const char *, format); + result = vsnprintf (s, n, format, ap); + VA_CLOSE (ap); + return result; +} + +extern int main (void); +int +main (void) +{ + char buf[128]; + int status; + + CLEAR (buf); + status = checkit (buf, 10, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 9, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 8, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar:\0XXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 7, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "foobar\0XXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 6, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "fooba\0XXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 2, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "f\0XXXXXXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 1, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "\0XXXXXXXXXXXXX\0", 15) == 0); + + CLEAR (buf); + status = checkit (buf, 0, "%s:%d", "foobar", 9); + VERIFY (status==8 && memcmp (buf, "XXXXXXXXXXXXXX\0", 15) == 0); + + return 0; +} +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/libiberty/vsprintf.c b/external/gpl3/gdb/dist/libiberty/vsprintf.c new file mode 100644 index 000000000000..99e704493f58 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/vsprintf.c @@ -0,0 +1,56 @@ +/* Simple implementation of vsprintf for systems without it. + Highly system-dependent, but should work on most "traditional" + implementations of stdio; newer ones should already have vsprintf. + Written by Per Bothner of Cygnus Support. + Based on libg++'s "form" (written by Doug Lea; dl@rocky.oswego.edu). + Copyright (C) 1991, 1995, 2002 Free Software Foundation, Inc. + +This file is part of the libiberty library. This library is free +software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) +any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +As a special exception, if you link this library with files +compiled with a GNU compiler to produce an executable, this does not cause +the resulting executable to be covered by the GNU General Public License. +This exception does not however invalidate any other reasons why +the executable file might be covered by the GNU General Public License. */ + +#include +#include +#include +#undef vsprintf + +#if defined _IOSTRG && defined _IOWRT + +int +vsprintf (char *buf, const char *format, va_list ap) +{ + FILE b; + int ret; +#ifdef VMS + b->_flag = _IOWRT|_IOSTRG; + b->_ptr = buf; + b->_cnt = 12000; +#else + b._flag = _IOWRT|_IOSTRG; + b._ptr = buf; + b._cnt = 12000; +#endif + ret = _doprnt(format, ap, &b); + putc('\0', &b); + return ret; + +} + +#endif diff --git a/external/gpl3/gdb/dist/libiberty/waitpid.c b/external/gpl3/gdb/dist/libiberty/waitpid.c new file mode 100644 index 000000000000..fd519d7696e0 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/waitpid.c @@ -0,0 +1,35 @@ +/* + +@deftypefn Supplemental int waitpid (int @var{pid}, int *@var{status}, int) + +This is a wrapper around the @code{wait} function. Any ``special'' +values of @var{pid} depend on your implementation of @code{wait}, as +does the return value. The third argument is unused in @libib{}. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" + +/* On some systems (such as WindISS), you must include + to get the definition of "pid_t" before you include . */ +#include + +#ifdef HAVE_SYS_WAIT_H +#include +#endif + +pid_t +waitpid (pid_t pid, int *stat_loc, int options ATTRIBUTE_UNUSED) +{ + for (;;) + { + int wpid = wait(stat_loc); + if (wpid == pid || wpid == -1) + return wpid; + } +} diff --git a/external/gpl3/gdb/dist/libiberty/xatexit.c b/external/gpl3/gdb/dist/libiberty/xatexit.c new file mode 100644 index 000000000000..6fdad9ed806a --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xatexit.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 1990 Regents of the University of California. + * All rights reserved. + * + * %sccs.include.redist.c% + */ + + +/* + +@deftypefun int xatexit (void (*@var{fn}) (void)) + +Behaves as the standard @code{atexit} function, but with no limit on +the number of registered functions. Returns 0 on success, or @minus{}1 on +failure. If you use @code{xatexit} to register functions, you must use +@code{xexit} to terminate your program. + +@end deftypefun + +*/ + +/* Adapted from newlib/libc/stdlib/{,at}exit.[ch]. + If you use xatexit, you must call xexit instead of exit. */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" + +#include + +#include + +#if VMS +#include +#include +#else +/* For systems with larger pointers than ints, this must be declared. */ +PTR malloc (size_t); +#endif + +static void xatexit_cleanup (void); + +/* Pointer to function run by xexit. */ +extern void (*_xexit_cleanup) (void); + +#define XATEXIT_SIZE 32 + +struct xatexit { + struct xatexit *next; /* next in list */ + int ind; /* next index in this table */ + void (*fns[XATEXIT_SIZE]) (void); /* the table itself */ +}; + +/* Allocate one struct statically to guarantee that we can register + at least a few handlers. */ +static struct xatexit xatexit_first; + +/* Points to head of LIFO stack. */ +static struct xatexit *xatexit_head = &xatexit_first; + +/* Register function FN to be run by xexit. + Return 0 if successful, -1 if not. */ + +int +xatexit (void (*fn) (void)) +{ + register struct xatexit *p; + + /* Tell xexit to call xatexit_cleanup. */ + if (!_xexit_cleanup) + _xexit_cleanup = xatexit_cleanup; + + p = xatexit_head; + if (p->ind >= XATEXIT_SIZE) + { + if ((p = (struct xatexit *) malloc (sizeof *p)) == NULL) + return -1; + p->ind = 0; + p->next = xatexit_head; + xatexit_head = p; + } + p->fns[p->ind++] = fn; + return 0; +} + +/* Call any cleanup functions. */ + +static void +xatexit_cleanup (void) +{ + register struct xatexit *p; + register int n; + + for (p = xatexit_head; p; p = p->next) + for (n = p->ind; --n >= 0;) + (*p->fns[n]) (); +} diff --git a/external/gpl3/gdb/dist/libiberty/xexit.c b/external/gpl3/gdb/dist/libiberty/xexit.c new file mode 100644 index 000000000000..421e5e238419 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xexit.c @@ -0,0 +1,52 @@ +/* xexit.c -- Run any exit handlers, then exit. + Copyright (C) 1994, 95, 1997 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If not, write +to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Replacement void xexit (int @var{code}) + +Terminates the program. If any functions have been registered with +the @code{xatexit} replacement function, they will be called first. +Termination is handled via the system's normal @code{exit} call. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#ifdef HAVE_STDLIB_H +#include +#endif +#include "libiberty.h" + + +/* This variable is set by xatexit if it is called. This way, xmalloc + doesn't drag xatexit into the link. */ +void (*_xexit_cleanup) (void); + +void +xexit (int code) +{ + if (_xexit_cleanup != NULL) + (*_xexit_cleanup) (); + exit (code); +} diff --git a/external/gpl3/gdb/dist/libiberty/xmalloc.c b/external/gpl3/gdb/dist/libiberty/xmalloc.c new file mode 100644 index 000000000000..3e97aab563f0 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xmalloc.c @@ -0,0 +1,184 @@ +/* memory allocation routines with error checking. + Copyright 1989, 90, 91, 92, 93, 94 Free Software Foundation, Inc. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Replacement void* xmalloc (size_t) + +Allocate memory without fail. If @code{malloc} fails, this will print +a message to @code{stderr} (using the name set by +@code{xmalloc_set_program_name}, +if any) and then call @code{xexit}. Note that it is therefore safe for +a program to contain @code{#define malloc xmalloc} in its source. + +@end deftypefn + +@deftypefn Replacement void* xrealloc (void *@var{ptr}, size_t @var{size}) +Reallocate memory without fail. This routine functions like @code{realloc}, +but will behave the same as @code{xmalloc} if memory cannot be found. + +@end deftypefn + +@deftypefn Replacement void* xcalloc (size_t @var{nelem}, size_t @var{elsize}) + +Allocate memory without fail, and set it to zero. This routine functions +like @code{calloc}, but will behave the same as @code{xmalloc} if memory +cannot be found. + +@end deftypefn + +@deftypefn Replacement void xmalloc_set_program_name (const char *@var{name}) + +You can use this to set the name of the program used by +@code{xmalloc_failed} when printing a failure message. + +@end deftypefn + +@deftypefn Replacement void xmalloc_failed (size_t) + +This function is not meant to be called by client code, and is listed +here for completeness only. If any of the allocation routines fail, this +function will be called to print an error message and terminate execution. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" + +#include + +#include + +#if VMS +#include +#include +#else +/* For systems with larger pointers than ints, these must be declared. */ +# if HAVE_STDLIB_H && HAVE_UNISTD_H && HAVE_DECL_MALLOC \ + && HAVE_DECL_REALLOC && HAVE_DECL_CALLOC && HAVE_DECL_SBRK +# include +# include +# else +# ifdef __cplusplus +extern "C" { +# endif /* __cplusplus */ +void *malloc (size_t); +void *realloc (void *, size_t); +void *calloc (size_t, size_t); +void *sbrk (ptrdiff_t); +# ifdef __cplusplus +} +# endif /* __cplusplus */ +# endif /* HAVE_STDLIB_H ... */ +#endif /* VMS */ + +/* The program name if set. */ +static const char *name = ""; + +#ifdef HAVE_SBRK +/* The initial sbrk, set when the program name is set. Not used for win32 + ports other than cygwin32. */ +static char *first_break = NULL; +#endif /* HAVE_SBRK */ + +void +xmalloc_set_program_name (const char *s) +{ + name = s; +#ifdef HAVE_SBRK + /* Win32 ports other than cygwin32 don't have brk() */ + if (first_break == NULL) + first_break = (char *) sbrk (0); +#endif /* HAVE_SBRK */ +} + +void +xmalloc_failed (size_t size) +{ +#ifdef HAVE_SBRK + extern char **environ; + size_t allocated; + + if (first_break != NULL) + allocated = (char *) sbrk (0) - first_break; + else + allocated = (char *) sbrk (0) - (char *) &environ; + fprintf (stderr, + "\n%s%sout of memory allocating %lu bytes after a total of %lu bytes\n", + name, *name ? ": " : "", + (unsigned long) size, (unsigned long) allocated); +#else /* HAVE_SBRK */ + fprintf (stderr, + "\n%s%sout of memory allocating %lu bytes\n", + name, *name ? ": " : "", + (unsigned long) size); +#endif /* HAVE_SBRK */ + xexit (1); +} + +PTR +xmalloc (size_t size) +{ + PTR newmem; + + if (size == 0) + size = 1; + newmem = malloc (size); + if (!newmem) + xmalloc_failed (size); + + return (newmem); +} + +PTR +xcalloc (size_t nelem, size_t elsize) +{ + PTR newmem; + + if (nelem == 0 || elsize == 0) + nelem = elsize = 1; + + newmem = calloc (nelem, elsize); + if (!newmem) + xmalloc_failed (nelem * elsize); + + return (newmem); +} + +PTR +xrealloc (PTR oldmem, size_t size) +{ + PTR newmem; + + if (size == 0) + size = 1; + if (!oldmem) + newmem = malloc (size); + else + newmem = realloc (oldmem, size); + if (!newmem) + xmalloc_failed (size); + + return (newmem); +} diff --git a/external/gpl3/gdb/dist/libiberty/xmemdup.c b/external/gpl3/gdb/dist/libiberty/xmemdup.c new file mode 100644 index 000000000000..aa56f0bf572b --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xmemdup.c @@ -0,0 +1,39 @@ +/* xmemdup.c -- Duplicate a memory buffer, using xcalloc. + This trivial function is in the public domain. + Jeff Garzik, September 1999. */ + +/* + +@deftypefn Replacement void* xmemdup (void *@var{input}, @ + size_t @var{copy_size}, size_t @var{alloc_size}) + +Duplicates a region of memory without fail. First, @var{alloc_size} bytes +are allocated, then @var{copy_size} bytes from @var{input} are copied into +it, and the new memory is returned. If fewer bytes are copied than were +allocated, the remaining memory is zeroed. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "ansidecl.h" +#include "libiberty.h" + +#include /* For size_t. */ +#ifdef HAVE_STRING_H +#include +#else +# ifdef HAVE_STRINGS_H +# include +# endif +#endif + +PTR +xmemdup (const PTR input, size_t copy_size, size_t alloc_size) +{ + PTR output = xcalloc (1, alloc_size); + return (PTR) memcpy (output, input, copy_size); +} diff --git a/external/gpl3/gdb/dist/libiberty/xstrdup.c b/external/gpl3/gdb/dist/libiberty/xstrdup.c new file mode 100644 index 000000000000..fa12c96a3cd6 --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xstrdup.c @@ -0,0 +1,36 @@ +/* xstrdup.c -- Duplicate a string in memory, using xmalloc. + This trivial function is in the public domain. + Ian Lance Taylor, Cygnus Support, December 1995. */ + +/* + +@deftypefn Replacement char* xstrdup (const char *@var{s}) + +Duplicates a character string without fail, using @code{xmalloc} to +obtain memory. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#ifdef HAVE_STRING_H +#include +#else +# ifdef HAVE_STRINGS_H +# include +# endif +#endif +#include "ansidecl.h" +#include "libiberty.h" + +char * +xstrdup (const char *s) +{ + register size_t len = strlen (s) + 1; + register char *ret = XNEWVEC (char, len); + return (char *) memcpy (ret, s, len); +} diff --git a/external/gpl3/gdb/dist/libiberty/xstrerror.c b/external/gpl3/gdb/dist/libiberty/xstrerror.c new file mode 100644 index 000000000000..2ea2200e9fcf --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xstrerror.c @@ -0,0 +1,79 @@ +/* xstrerror.c -- jacket routine for more robust strerror() usage. + Fri Jun 16 18:30:00 1995 Pat Rankin + This code is in the public domain. */ + +/* + +@deftypefn Replacement char* xstrerror (int @var{errnum}) + +Behaves exactly like the standard @code{strerror} function, but +will never return a @code{NULL} pointer. + +@end deftypefn + +*/ + +#include + +#include "config.h" +#include "libiberty.h" + +#ifdef VMS +# include +# if !defined (__STRICT_ANSI__) && !defined (__HIDE_FORBIDDEN_NAMES) +# ifdef __cplusplus +extern "C" { +# endif /* __cplusplus */ +extern char *strerror (int,...); +# define DONT_DECLARE_STRERROR +# ifdef __cplusplus +} +# endif /* __cplusplus */ +# endif +#endif /* VMS */ + + +#ifndef DONT_DECLARE_STRERROR +# ifdef __cplusplus +extern "C" { +# endif /* __cplusplus */ +extern char *strerror (int); +# ifdef __cplusplus +} +# endif /* __cplusplus */ +#endif + +/* If strerror returns NULL, we'll format the number into a static buffer. */ + +#define ERRSTR_FMT "undocumented error #%d" +static char xstrerror_buf[sizeof ERRSTR_FMT + 20]; + +/* Like strerror, but result is never a null pointer. */ + +char * +xstrerror (int errnum) +{ + char *errstr; +#ifdef VMS + char *(*vmslib_strerror) (int,...); + + /* Override any possibly-conflicting declaration from system header. */ + vmslib_strerror = (char *(*) (int,...)) strerror; + /* Second argument matters iff first is EVMSERR, but it's simpler to + pass it unconditionally. `vaxc$errno' is declared in + and maintained by the run-time library in parallel to `errno'. + We assume that `errnum' corresponds to the last value assigned to + errno by the run-time library, hence vaxc$errno will be relevant. */ + errstr = (*vmslib_strerror) (errnum, vaxc$errno); +#else + errstr = strerror (errnum); +#endif + + /* If `errnum' is out of range, result might be NULL. We'll fix that. */ + if (!errstr) + { + sprintf (xstrerror_buf, ERRSTR_FMT, errnum); + errstr = xstrerror_buf; + } + return errstr; +} diff --git a/external/gpl3/gdb/dist/libiberty/xstrndup.c b/external/gpl3/gdb/dist/libiberty/xstrndup.c new file mode 100644 index 000000000000..0a41f608ec0b --- /dev/null +++ b/external/gpl3/gdb/dist/libiberty/xstrndup.c @@ -0,0 +1,60 @@ +/* Implement the xstrndup function. + Copyright (C) 2005 Free Software Foundation, Inc. + Written by Kaveh R. Ghazi . + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, +Boston, MA 02110-1301, USA. */ + +/* + +@deftypefn Replacement char* xstrndup (const char *@var{s}, size_t @var{n}) + +Returns a pointer to a copy of @var{s} with at most @var{n} characters +without fail, using @code{xmalloc} to obtain memory. The result is +always NUL terminated. + +@end deftypefn + +*/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#ifdef HAVE_STRING_H +#include +#else +# ifdef HAVE_STRINGS_H +# include +# endif +#endif +#include "ansidecl.h" +#include "libiberty.h" + +char * +xstrndup (const char *s, size_t n) +{ + char *result; + size_t len = strlen (s); + + if (n < len) + len = n; + + result = XNEWVEC (char, len + 1); + + result[len] = '\0'; + return (char *) memcpy (result, s, len); +} diff --git a/external/gpl3/gdb/dist/opcodes/.gitignore b/external/gpl3/gdb/dist/opcodes/.gitignore new file mode 100644 index 000000000000..94ece5d4a47f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/.gitignore @@ -0,0 +1,2 @@ +/s390-mkopc +/s390-opc.tab diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog b/external/gpl3/gdb/dist/opcodes/ChangeLog new file mode 100644 index 000000000000..734f824cd412 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog @@ -0,0 +1,211 @@ +2011-03-24 Mike Frysinger + + * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. + +2011-03-22 Eric B. Weddington + + * avr-dis.c (avr_operand): Add opcode_str parameter. Check for + post-increment to support LPM Z+ instruction. Add support for 'E' + constraint for DES instruction. + (print_insn_avr): Adjust calls to avr_operand. Rename variable. + +2011-03-14 Richard Sandiford + + * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. + +2011-03-14 Richard Sandiford + + * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. + Use branch types instead. + (print_insn): Likewise. + +2011-02-28 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Correct register use + annotation of "alnv.ps". + +2011-02-28 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. + +2011-02-22 Mike Frysinger + + * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. + +2011-02-22 Mike Frysinger + + * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. + +2011-02-19 Mike Frysinger + + * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and + a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, + av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, + exception, end_of_registers, msize, memory, bfd_mach. + (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, + LB0REG, LC1REG, LT1REG, LB1REG): Delete + (AXREG, AWREG, LCREG, LTREG, LBREG): Define. + (get_allreg): Change to new defines. Fallback to abort(). + +2011-02-14 Mike Frysinger + + * bfin-dis.c: Add whitespace/parenthesis where needed. + +2011-02-14 Mike Frysinger + + * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater + than 7. + +2011-02-13 Ralf Wildenhues + + * configure: Regenerate. + +2011-02-13 Mike Frysinger + + * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. + +2011-02-13 Mike Frysinger + + * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output + dregs only when P is set, and dregs_lo otherwise. + +2011-02-13 Mike Frysinger + + * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. + +2011-02-12 Mike Frysinger + + * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. + +2011-02-12 Mike Frysinger + + * bfin-dis.c (machine_registers): Delete REG_GP. + (reg_names): Delete "GP". + (decode_allregs): Change REG_GP to REG_LASTREG. + +2011-02-12 Mike Frysinger + + * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, + M_IH, M_IU): Delete. + +2011-02-11 Mike Frysinger + + * bfin-dis.c (reg_names): Add const. + (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, + decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, + decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, + decode_counters, decode_allregs): Likewise. + +2011-02-09 Michael Snyder + + * i386-dis.c (OP_J): Parenthesize expression to prevent + truncated addresses. + (print_insn): Fix indentation off-by-one. + +2011-02-01 Nick Clifton + + * po/da.po: Updated Danish translation. + +2011-01-21 Dave Murphy + + * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. + +2011-01-18 H.J. Lu + + * i386-dis.c (sIbT): New. + (b_T_mode): Likewise. + (dis386): Replace sIb with sIbT on "pushT". + (x86_64_table): Replace sIb with Ib on "aam" and "aad". + (OP_sI): Handle b_T_mode. Properly sign-extend byte. + +2011-01-18 Jan Kratochvil + + * i386-init.h: Regenerated. + * i386-tbl.h: Regenerated + +2011-01-17 Quentin Neill + + * i386-dis.c (REG_XOP_TBM_01): New. + (REG_XOP_TBM_02): New. + (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. + (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 + entries, and add bextr instruction. + + * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. + (cpu_flags): Add CpuTBM. + + * i386-opc.h (CpuTBM) New. + (i386_cpu_flags): Add bit cputbm. + + * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, + blcs, blsfill, blsic, t1mskc, and tzmsk. + +2011-01-12 DJ Delorie + + * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. + +2011-01-11 Mingjie Xing + + * mips-dis.c (print_insn_args): Adjust the value to print the real + offset for "+c" argument. + +2011-01-10 Nick Clifton + + * po/da.po: Updated Danish translation. + +2011-01-05 Nathan Sidwell + + * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. + +2011-01-04 H.J. Lu + + * i386-dis.c (REG_VEX_38F3): New. + (PREFIX_0FBC): Likewise. + (PREFIX_VEX_38F2): Likewise. + (PREFIX_VEX_38F3_REG_1): Likewise. + (PREFIX_VEX_38F3_REG_2): Likewise. + (PREFIX_VEX_38F3_REG_3): Likewise. + (PREFIX_VEX_38F7): Likewise. + (VEX_LEN_38F2_P_0): Likewise. + (VEX_LEN_38F3_R_1_P_0): Likewise. + (VEX_LEN_38F3_R_2_P_0): Likewise. + (VEX_LEN_38F3_R_3_P_0): Likewise. + (VEX_LEN_38F7_P_0): Likewise. + (dis386_twobyte): Use PREFIX_0FBC. + (reg_table): Add REG_VEX_38F3. + (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, + PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, + PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. + (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and + PREFIX_VEX_38F7. + (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, + VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and + VEX_LEN_38F7_P_0. + + * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. + (cpu_flags): Add CpuBMI. + + * i386-opc.h (CpuBMI): New. + (i386_cpu_flags): Add cpubmi. + + * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2011-01-04 H.J. Lu + + * i386-dis.c (VexGdq): New. + (OP_VEX): Handle dq_mode. + +2011-01-01 H.J. Lu + + * i386-gen.c (process_copyright): Update copyright to 2011. + +For older changes see ChangeLog-2010 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-0001 b/external/gpl3/gdb/dist/opcodes/ChangeLog-0001 new file mode 100644 index 000000000000..085453a34e98 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-0001 @@ -0,0 +1,2224 @@ +2001-12-31 Jeffrey A Law (law@redhat.com) + + * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, + 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. + Always emit a space after 'H'. + +2001-12-18 matthew green + + * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. + +2001-12-17 Richard Henderson + + * alpha-opc.c (unop): Encode with RB as $sp. + +2001-12-07 Geoffrey Keating + + * Makefile.am: Add support for xstormy16. + * Makefile.in: Regenerate. + * configure.in: Add support for xstormy16. + * configure: Regenerate. + * disassemble.c: Add support for xstormy16. + * xstormy16-asm.c: New generated file. + * xstormy16-desc.c: New generated file. + * xstormy16-desc.h: New generated file. + * xstormy16-dis.c: New generated file. + * xstormy16-ibld.c: New generated file. + * xstormy16-opc.c: New generated file. + * xstormy16-opc.h: New generated file. + +2001-12-06 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Add wh64en. + +2001-12-04 Alexandre Oliva + + * d10v-opc.c (d10v_predefined_registers): Remove warnings + introduced in Nov 29's patch. + + * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of + unmatched register. + + * d10v-dis.c (print_operand): Disregard OPERAND_SP in register + predefined value. + + * d10v-opc.c (RSRC_NOSP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". + +2001-11-29 Alexandre Oliva + + * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. + (RSRC_SP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. + +2001-11-23 Lars Brinkhoff + + * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. + Also, break out of the loop as soon as an instruction has been + printed. + +2001-11-17 matthew green + + * ppc-opc.c (mfvrsave, mtvrsave): New instructions. + +2001-11-15 Alan Modra + + * po/POTFILES.in: Regenerate. + + * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. + (insert_bat, extract_bat, insert_bba, extract_bba, + insert_bd, extract_bd, insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo, + insert_bo, extract_bo, insert_boe, extract_boe, + insert_ds, extract_ds, insert_de, extract_de, + insert_des, extract_des, insert_li, extract_li, + insert_mbe, extract_mbe, insert_mb6, extract_mb6, + insert_nb, extract_nb, insert_nsi, extract_nsi, + insert_ral, insert_ram, insert_ras, + insert_rbs, extract_rbs, insert_sh6, extract_sh6, + insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. + (extract_bd, extract_bdm, extract_bdp, + extract_ds, extract_des, + extract_li, extract_nsi): Implement sign extension without conditional. + (insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. + (extract_bdm, extract_bdp): Correct 32 bit validation. + (AT1_MASK, AT2_MASK): Define. + (BBOAT_MASK): Define. + (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. + (BOFM64, BOFP64, BOTM64, BOTP64): Define. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. + (PPCCOM32, PPCCOM64): Define. + (powerpc_opcodes): Modify existing 32 bit insns with branch hints + and add new patterns to implement 64 bit branches with hints. Move + booke instructions so they match before ppc64. + + * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for + 64 bit default targets, and parse "32" and "64" in options. + Formatting fixes. + (print_insn_powerpc): Pass dialect to operand->extract. + +2001-11-14 Dave Brolley + + * cgen-dis.c (count_decodable_bits): New function. + (add_insn_to_hash_chain): New function. + (hash_insn_array): Call add_insn_to_hash_chain. + (hash_insn_list): Call add_insn_to_hash_chain. + * m32r-dis.c: Regenerated. + * fr30-dis.c: Regenerated. + +2001-11-14 Andreas Jaeger + + * i386-dis.c (print_insn): Use x86-64 as option. + +2001-11-14 Alan Modra + + * disassemble.c (disassembler): Call print_insn_i386. + * i386-dis.c (SUFFIX_ALWAYS): Define. + (struct dis_private): Add orig_sizeflag. + (print_insn_i386): Make it a wrapper, calling.. + (print_insn): ..The old body of print_insn_i386. Avoid longjmp + warning without using volatile by moving orig_sizeflag to priv, + and removing inbuf. Parse disassembler_options. + (print_insn_i386_att, print_insn_i386_intel): Move initialisation + code to print_insn. + (putop): Remove #ifdef SUFFIX_ALWAYS. + +2001-11-11 Timothy Wall + + * tic54x-dis.c: Use revised opcode structure. Export opcode + template lookup. + (has_lkaddr): Don't forget about Lmem insns. + * tic54x-opc.c: Add emulation trap. Parallel table now uses + standard opcode templates. + +2001-11-13 Zack Weinberg + + * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries + to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand + category instead of Ew. + +2001-11-12 Niraj Gupta + + * m68k-opc.c: Fix definitions of wddata[bwl]. + +2001-11-09 Richard Sandiford + + * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to + fit in the buffer, try to match the empty keyword. + +2001-11-09 Nick Clifton + + * cgen-ibld.in (extract_1): Fix badly placed #if 0. + * fr30-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + +2001-11-04 Chris Demetriou + + * mips-dis.c (print_insn_mips): Remove spaces at end of line. + +2001-11-02 Nick Clifton + + * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". + * configure: Regernate. + * po/fr.po: New file. + * po/sv.po: New file. + * po/tr.po: New file. + +2001-11-01 Stephane Carrez + + * m68hc11-dis.c (print_insn): Fix disassembly of movb with a + constant as source. + +2001-10-30 Hans-Peter Nilsson + + * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate + dependencies. + * Makefile.in: Regenerate. + * mmix-dis.c, mmix-opc.c: New files. + +2001-10-29 Kazu Hirata + + * d30v-dis.c: Fix a comment typo. + +2001-10-23 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and + "bltzall" as writing GPR 31 (since they do). + + * mips-dis.c (print_insn_arg): Calculate info->target + where appropriate. + (print_insn_mips): Fill in instruction info. + (print_mips16_insn_arg): Remove unneded variable 'val'. + Removed duplicated instruction target calculations, + calculate once and print that result. Use same idiom for + masking the jump segment bits as is used in print_insn_arg. + +2001-10-20 Alan Modra + + * ppc-opc.c (CT): Make it an optional operand. + +2001-10-17 Chris Demetriou + + * mips-dis.c (mips_isa_type): Make the ISA used to disassemble + SB-1 binaries include instructions specific to the SB-1. + * mips-opc.c (SB1): New definition. + (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", + "recip.ps", "rsqrt.ps", and "sqrt.ps". + +2001-10-17 matthew green + + * ppc-opc.c (STRM): New AltiVec operand. + (XDSS): New AltiVec instruction form. + (mtvscr): Correct operand list. + (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. + +2001-10-17 Alan Modra + + * po/POTFILES.in: Regenerate. + +2001-10-13 matthew green + + * ppc-opc.c (MO): New macro for MO field of mbar instruction. + (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, + mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. + +2001-10-13 Nick Clifton + + * cgen-ibld.in: Include safe-ctype.h in preference to + ctype.h. + * cgen-asm.in: Include safe-ctype.h in preference to + ctype.h. Fix formatting. Use ISSPACE instead of isspace and + TOLOWER instead of tolower. + (@arch@_cgen_build_insn_regex): Remove duplication of syntax + string elements in constructed regular expression. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-ibld.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-12 matthew green + + * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New + instruction field instruction/extraction functions for new BookE + DE form instructions. + (CT): New macro for CT field in an X form instruction. + (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form + instructions. + (PPC64): Don't include PPC_OPCODE_PPC. + (403): New opcode macro for PPC403 processors. + (BOOKE): New opcode macro for BookE processors. + (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. + (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. + (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. + (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. + (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. + (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. + (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. + (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. + (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. + (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. + (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. + (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. + (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. + (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. + + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look + for a disassembler option of `booke', `booke32' or `booke64' to enable + BookE support in the disassembler. + +2001-10-12 John Healy + + * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) + for the length when extracting the base part of the insn. + +2001-10-09 Bruno Haible + + * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive + regular expression. Fix some formatting problems. + * fr30-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + +2001-10-09 Christian Groessler + + * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly + of indirect register memory accesses to be same format the + assembler accepts. + +2001-10-09 Nick Clifton + + * sh-opc.h: Fix encoding of least significant nibble of the + DSP single data transfer instructions. + + * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP + instructions. + +2001-10-08 Nick Clifton + + * cgen-asm.in: Fix compile time warning messages in generated + C files. + * cgen-dis.in: The same. + * cgen-ibld.in: The same. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opinst.c Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-08 Aldy Hernandez + + * arm-opc.h (arm_opcodes): Add cirrus insns. + + * arm-dis.c (print_insn_arm): Add 'I' case. + +2001-10-03 Alan Modra + + * po/POTFILES.in: Regenerate. + * configure: Regenerate. + +2001-10-02 Alan Modra + + * Makefile.am (Makefile): Depend on bfd/configure.in. + Run "make dep-am". + * Makefile.in: Regenerate. + +2001-09-30 John Healy + + * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits + calls to cgen_get_insn_value and cgen_put_insn_value calls. + (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. + +2001-09-30 Hans-Peter Nilsson + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate. + +2001-09-26 Alan Modra + + * arc-dis.c: Formatting fixes. + (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. + +2001-09-21 Bruno Haible + + * arc-dis.c: Don't include . + * openrisc-desc.c: Likewise. + * openrisc-ibld.c: Likewise. + +2001-09-20 Nick Clifton + + * fr30-opc.c: Fix compile time warning messages. + * i370-opc.c: Fix compile time warning messages. + * i960-dis.c: Fix compile time warning messages. + * m32r-asm.c: Fix compile time warning messages. + * m32r-desc.c: Fix compile time warning messages. + * m32r-dis.c: Fix compile time warning messages. + * m32r-ibld.c: Fix compile time warning messages. + * m32r-opc.c: Fix compile time warning messages. + * m32r-opinst.c: Fix compile time warning messages. + * ns32k-dis.c: Fix compile time warning messages. + * openrisc-asm.c: Fix compile time warning messages. + * openrisc-desc.c: Fix compile time warning messages. + * openrisc-dis.c: Fix compile time warning messages. + * openrisc-ibld.c: Fix compile time warning messages. + * openrisc-opc.c: Fix compile time warning messages. + * pdp11-dis.c: Fix compile time warning messages. + * tic54x-dis.c: Fix compile time warning messages. + * v850-opc.c: Fix compile time warning messages. + * vax-dis.c: Fix compile time warning messages. + * w65-opc.h: Fix compile time warning messages. + * z8k-opc.h: Fix compile time warning messages. + * z8kgen.c: Fix compile time warning messages. + +2001-09-19 Nick Clifton + + * arm-dis.c: Fix compile time warning messages. + * cgen-asm.c: Fix compile time warning messages. + * cgen-dis.c: Fix compile time warning messages. + * cris-dis.c: Fix compile time warning messages. + * d10v-dis.c: Fix compile time warning messages. + * fr30-asm.c: Fix compile time warning messages. + * fr30-desc.c: Fix compile time warning messages. + * fr30-dis.c: Fix compile time warning messages. + * fr30-ibld.c: Fix compile time warning messages. + +2001-09-18 Bruno Haible + + * cgen-asm.c: Include "safe-ctype.h" instead of . + (cgen_parse_keyword): Use ISALNUM instead of isalnum. + * cgen-opc.c: Include "safe-ctype.h" instead of . + (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of + isalpha/tolower. + (cgen_keyword_add): Use ISALNUM instead of isalnum. + (hash_keyword_name): Use TOLOWER instead of tolower. + * fr30-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. + * fr30-desc.c: Don't include . + * fr30-ibld.c: Likewise. + * ia64-gen.c: Include "safe-ctype.h" instead of . + (load_insn_classes, parse_resource_users, load_depfile): Use + ISSPACE instead of isspace. + * m32r-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. + * m32r-desc.c: Don't include . + * m32r-ibld.c: Likewise. + * openrisc-asm.c: Include "safe-ctype.h" instead of . + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. + +2001-09-18 Martin Schwidefsky + + * Makefile.am: Add rules and dependencies to create the s/390 opcode + table out of s390-opc.txt automatically. + * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. + * s390-mkopc.c (dumpTable): Change output to create a complete file. + * s390-opc.c: New improved opcode format macros and remove the + pregenerated opcode table. + * s390-opc.txt: Adapt to new improved opcode format macros. + +2001-09-14 David Schleef + + * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. + +2001-09-04 Alan Modra + + * i386-dis.c (grps): Don't print the implicit al/ax/eax register + for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. + +2001-08-31 Eric Christopher + Jason Eckhardt + + * mips-dis.c: Add support for bfd_mach_mipsisa32 and + bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, + bfd_mach_mips64. + +2001-08-31 Andreas Jaeger + + * tic54x-opc.c: Add default initializers to avoid warnings. + + * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. + * arc-ext.c: Likewise. + +2001-08-28 matthew green + + * ppc-opc.c (icbt): Order correctly. + +2001-08-27 David Edelsohn + Torbjorn Granlund + + * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. + (LS): Define. + (insert_ds): Complain if not a multiple of 4. + (XSYNC): Define. + (XSYNC_MASK): Define. + (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", + "slbmfee". Modify "sync" to use XSYNC_MASK and LS. + +2001-08-26 Andreas Jaeger + + * h8500-opc.h: Add default initializers to h8500_table to shut up + GCC warnings. + +2001-08-25 Andreas Jaeger + + * tic54x-dis.c: Add unused attributes where needed. + + * z8k-dis.c (output_instr): Add unused attribute. + + * h8300-dis.c: Add missing prototypes. + (bfd_h8_disassemble): Make static. + + * cris-dis.c: Add missing prototype. + * h8500-dis.c: Likewise. + * m68hc11-dis.c: Likewise. + * pj-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * v850-dis.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8k-dis.c: Likewise. + + * d10v-dis.c: Add missing prototype. + (dis_long): Remove unused variable. + (dis_2_short): Likewise. + + * sh-dis.c: Add missing prototypes. + * v850-opc.c: Likewise. + Add unused attributes where needed. + + * ns32k-dis.c: Add missing prototypes. + (bit_extract_simple): Remove unused variable. + +2001-08-23 Martin Schwidefsky + + * s390-opc.c: Add "low or high" and "not low or high" + branch instructions for gcc 3.0. + * s390-opc.txt: Likewise. + +2001-08-21 Andreas Jaeger + + * i960-dis.c: Add parameters for prototypes + (ctrl): Add unused attributes. + (cobr): Likewise. + (put_abs): Likewise. + + * mips-dis.c: Add missing prototypes. + * a29k-dis.c: Likewise. + * arc-dis.c: Likewise. + * ia64-opc.c: Likewise. + + * s390-dis.c: Add missing prototypes. + (init_disasm): Remove unused attribute since the parameter is + used. + +2001-08-16 Thiemo Seufer + + * mips-opc.c (M1): Define. Reformatted Code. + (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, + mtps, mtps. Typo. + +2001-08-16 Jonathan Larmour + + * mips-opc.c: R3900s can support all branch likely INSN_MACROs where + the corresponding non-likely insn is in MIPS I. + +2001-08-13 Kazu Hirata + + * mcore-dis.c: Fix formatting. + * mips-dis.c: Likewise. + * pj-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-08-12 Richard Henderson + + * cgen-ibld.in (extract_normal): Match type of VALUE and MASK + to *VALUEP. Regenerate all cgen files. + +2001-08-10 Richard Sandiford + + * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 + argument. + * mips-opc.c (G6): Undefine. + (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro + as the first "move" alternative. + +2001-08-10 Andreas Jaeger + + * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes + to build warnings. + * configure: Regenerate. + +2001-08-10 Alan Modra + + * ppc-opc.c: Revert 2001-08-08. + +2001-08-09 Alan Modra + + * dis-buf.c (generic_strcat_address): Add missing prototype. + #if 0 the functions as it is unused. + +2001-08-08 Alan Modra + + 1999-10-25 Torbjorn Granlund + * ppc-opc.c: Include "bfd.h". + (powerpc_operands): Add new field for reloc type. + +2001-07-21 Thiemo Seufer + + * mips-dis.c (print_insn_arg): Don't use software integer registers + for coprocessor registers. + (get_mips_isa): Removed. + (is_newabi): New function, checks if NewABI is used. + (_print_insn_mips): Get distinction between old ABI and new ABI right. + +2001-08-01 Christian Groessler + + * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to + get stderr definition. + (internal, gas): Removed warnings. + (gas): Create a correct final entry for created array. + * z8k-opc.h: Recreated with new z8kgen. + +2001-07-28 Kazu Hirata + + * i386-dis.c: Fix formatting. + +2001-07-28 Matthias Kramm + + * i386-dis.c: Change formatting conventions for architecture + i386:intel to better match the format of various intel i386 + assemblers, like nasm, tasm or masm. + +2001-07-24 Alan Modra + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate + +2001-07-24 Kazu Hirata + + * alpha-dis.c: Fix formatting. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * m10300-dis.c: Likewise. + * tic54x-dis.c: Likewise. + +2001-07-23 Kazu Hirata + + * m68k-dis.c: Fix formatting. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-07-21 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s + into the rest of the surrounding definitions. + +2001-07-18 Alan Modra + + * i386-dis.c (grps): Print l or w suffix, and require mem modrm + for lgdt, lidt, sgdt, sidt. + +2001-07-13 Philip Blundell + + * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. + +2001-07-12 Jeff Johnston + + * cgen-asm.in: Include "xregex.h" always to enable the libiberty + regex support. + (@arch@_cgen_build_insn_regex): New routine from Graydon. + (@arch@_cgen_assemble_insn): Add Graydon's code to use regex + to verify if it is worth parsing the insn as insn "x". Also update + error message when insn is not a recognized format of the insn vs + when the insn is completely unrecognized. + +2001-07-11 Frank Ch. Eigler + + * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of + bfd_get_bits. + * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect + non-zero CGEN_CPU_DESC->insn_chunk_bitsize. + +2001-07-09 Andreas Jaeger , Karsten Keil + + * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. + (OP_J): Use bfd_vma for mask to work properly with 64 bits. + (op_address,op_riprel): Use bfd_vma to handle 64 bits. + +2001-07-05 Ben Elliston + + * Makefile.am (CPUDIR): Define. + (stamp-m32r): Update dependencies. + (stamp-fr30): Ditto. + (stamp-openrisc): Ditto. + * Makefile.in: Regenerate. + +2001-07-03 Zoltan Hidvegi + + * ppc-opc.c: Fix encoding of 'clf' instruction. + +2001-06-30 Geoffrey Keating + + * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. + +2001-06-28 Geoffrey Keating + + * cgen-asm.c (cgen_parse_keyword): Allow any first character. + * cgen-opc.c (cgen_keyword_add): Ignore special first + character when building nonalpha_chars field. + +2001-06-24 Ben Elliston + + * m88k-dis.c: Format to conform to GNU coding standards. + +2001-06-23 Andreas Jaeger + + * disassemble.c (disassembler_usage): Add unused attribute. + +2001-06-22 Eric Christopher + + * mips-opc.c: Move prefx to start of the table. + +2001-06-22 Stacey Sheldon + + * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST + instruction. + +2001-06-22 Pauli + + * m68k-opc.c: Add wdebug instruction. + +2001-06-15 Aldy Hernandez + + * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. + +2001-06-14 Geoffrey Keating + + * cgen-asm.c (cgen_parse_keyword): When looking for the + boundaries of a keyword, allow any special characters + that are actually in one of the allowed keyword. + * cgen-opc.c (cgen_keyword_add): Add any special characters + to the nonalpha_chars field. + +2001-06-12 Martin Schwidefsky + + * s390-opc.c: Add lgh instruction. + * s390-opc.txt: Likewise. + +2001-06-11 Alan Modra + + * i386-dis.c: Group function prototypes in one place. + (FLOATCODE): Redefine as 1. + (USE_GROUPS): Redefine as 2. + (USE_PREFIX_USER_TABLE): Redefine as 3. + (X86_64_SPECIAL): Define as 4. + (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2. + (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE. + (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete. + (dis386): New table combining above four tables. + (dis386_twobyte_att, dis386_twobyte_intel): Delete. + (dis386_twobyte): New table combining above two tables. + (x86_64_table): New table to handle x86_64. + (X86_64_0): Define. + (float_mem_att, float_mem_intel): Delet. + (float_mem): New table combining above two tables. + (print_insn_i386): Modify for above. + (dofloat): Likewise. + (putop): Handle '{', '|' and '}' to select alternative mnemonics. + Return 0 on success, 1 if no valid alternative. + (putop , ): Print nothing for intel_syntax. + (putop ): Move to case 'U', and share case 'Q' code. + (putop ): Move to case 'T', and share case 'P' code. + (OP_REG ): Handle as for eAX_reg .. eDI_reg + if not 64-bit mode. + (OP_I ): Handle as for v_mode if not 64-bit mode. + (OP_I64): If not 64-bit mode, call OP_I. + OP_OFF64): If not 64-bit mode, call OP_OFF. + (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename + 'ignore'/'ignored' to 'bytemode'. + +2001-06-10 Alan Modra + + * configure.in: Sort 'ta' case statement. + * configure: Regenerate. + + * i386-dis.c (dis386_att): Add 'H' to conditional branch and + loop,jcxz insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't print branch hints as a prefix. + (putop): 'H' macro prints branch hints. + (get64): Kill compile warnings. + +2001-06-09 Alexandre Oliva + + * sh-opc.h (sh_table): Don't use empty initializers. + +2001-06-06 Christian Groessler + + * z8k-dis.c: Fix formatting. + (unpack_instr): Remove unused cases in switch statement. Add + safety abort() in default case. + (unparse_instr): Add safety abort() in default case. + +2001-06-06 Peter Jakubek + + * m68k-dis.c (print_insn_m68k): Fix typo. + * m68k-opc.c (m68k_opcodes): Correct allowed operands for + mcf (ColdFire) div, rem and moveb instructions. + +2001-06-06 Alan Modra + + * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. + (cond_jump_mode, loop_jcxz_mode): Define. + (dis386_att): Add cond_jump_flag and loop_jcxz_flag as + appropriate, and 'F' suffix to loop insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't output addr prefix for loop, jcxz insns. + Output data size prefix for long conditional jumps. Output cs and + ds branch hints. + (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. + (OP_J): Don't make PREFIX_DATA used. + +2001-06-04 Alexandre Oliva + + * sh-opc.h (sh_table): Complete last element entry to avoid + compiler warning. + +2001-05-16 Thiemo Seufer + + * mips-dis.c (mips_isa_type): Add MIPS r12k support. + +2001-05-23 Alan Modra + + * arc-opc.c: Whitespace changes. + +2001-05-18 Hans-Peter Nilsson + + * cris-opc.c (cris_spec_regs): Add missing initializer field for + last element. + +2001-05-15 Frank Ch. Eigler + + * cgen-dis.in (extract_normal): Complete support for min + + * mips-dis.c (INSNLEN): Rename MAXLEN. + (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. + (print_insn_arg): Remove $ prefix of register names. + (set_mips_isa_type): Remove. + (mips_isa_type): New function. + (get_mips_isa): New Function. + (print_insn_mips): Rename _print_insn_mips. + (_print_insn_mips): New function, contains code which was + duplicated in print_insn_big_mips and print_insn_little_mips. + (print_insn_big_mips): Moved code to _print_insn_mips. + (print_insn_little_mips): Likewise. + (print_mips16_insn_arg): Remove $ prefix of register names. + Print error message before abort. + +2001-05-14 J.T. Conklin + + * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of + simplified mnemonics used for setting PPC750-specific special + purpose registers. + +2001-05-12 H.J. Lu + + * i386-dis.c (print_insn_i386): Always set `mod', `reg' and + `rm'. + +2001-05-12 Peter Targett + + * arc-opc.c (arc_reg_names): Correct attribute for lp_count + register to r/w. Formatting fixes throughout file. + +2001-05-12 Alan Modra + + * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and + movq operands. + (twobyte_has_modrm): Update table. + (need_modrm): Give it file scope. + (MODRM_CHECK): Define. + (dofloat): Use MODRM_CHECK. + (OP_E): Likewise. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-05-07 Frank Ch. Eigler + + * cgen-dis.in (default_print_insn): Tolerate min + + * disassemble.c (disassembler_usage): Remove unused attribute. + +2001-05-04 Frank Ch. Eigler + + * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. + +2001-05-04 Frank Ch. Eigler + + * cgen-dis.in (print_insn): Remove call to read_insn. Instead, + assume incoming buffer already has the base insn loaded. Handle + smaller-than-base instructions for variable-length case. + +2001-05-04 Alan Modra + + * i386-dis.c (Ev, Ed): Remove duplicate define. + (Gd): Define. + (XS): Define. + (OP_XS): New function. + (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and + movmskp operands. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Use MS for maskmovq operand. + +2001-04-27 Johan Rydberg + + * Makefile.am: Add OpenRISC target. + * Makefile.in: Regenerated. + + * disassemble.c (disassembler): Recognize the OpenRISC disassembly. + + * configure.in (bfd_openrisc_arch): Add target. + * configure: Regenerated. + + * openrisc-asm.c: New file. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + +2001-04-24 Christian Groessler + + * z8k-dis.c: add names of control registers (ctrl_names); + (seg_length): provides instruction length fixup for segmented + mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, + CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; + (unparse_intr): handle CLASS_PR, print addresses without '#' + * z8k-opc.h: re-created with new z8kgen + * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new + entries for ldctl/ldctlb instruction + +2001-04-06 Andreas Jaeger + + * i386-dis.c: Add ffreep instruction. + +2001-03-30 Alexandre Oliva + + * ppc-opc.c (insert_mbe): Shift mask initializer as long. + +2001-03-24 Alan Modra + + * i386-dis.c (PREGRP25): Define. + (dis386_twobyte_att): Use here in place of "movntq" entry. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq". + (PREGRP26): Define. + (dis386_twobyte_att): Use here. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP26 entry for "punpcklqdq". + (prefix_user_table ): XM operand, not MX. + (prefix_user_table): Cosmetic changes to "bad" entries. + +2001-03-23 Nick Clifton + + * mips-opc.c: Remove extraneous whitespace. + * mips-dis.c: Remove extraneous whitespace. + +2001-03-22 Ben Elliston + + * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg + declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. + * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused + to allay a compiler warning. + +2001-03-22 Alan Modra + + * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. + (dis386_twobyte_intel): Likewise. + (twobyte_has_modrm): Set entry for paddq, psubq. + +2001-03-20 Patrick Macdonald + + * cgen-dis.in (print_insn_@arch@): Add support for target machine + determination via CGEN_COMPUTE_MACH. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-03-20 H.J. Lu + + * configure.in: Remove the redundent AC_ARG_PROGRAM. + * configure: Rebuild. + +2001-03-19 Jim Wilson + + * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and + notestr if larger than xsect. + (in_class): Handle format M5. + * ia64-asmtab.c: Regnerate. + +2001-03-19 John David Anglin + + * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer + has more than one byte left to read. + +2001-03-16 Martin Schwidefsky + + * s390-opc.c: Add new opcodes. Smooth out formatting. + * s390-opc.txt: Add new opcodes. + +2001-03-06 Nick Clifton + + * arm-dis.c (print_insn_thumb): Compute destination address + of BLX(1) instruction by taking bit 1 from PC and not from bit + 0 of the offset. + +2001-03-06 Igor Shevlyakov + + * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs + so command line switches will work. + +2001-03-05 Dave Brolley + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-desc.h: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-02-28 Igor Shevlyakov + + * m68k-opc.c: fix cpushl according to Motorola. Enable + bunch of instructions for Coldfire 5407 and add all new. + +2001-02-27 Alan Modra + + * configure.in (BFD_VERSION): Do without grep. + * configure: Regenerate. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2001-02-23 David Mosberger + + * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". + * ia64-asmtab.c: Regenerate. + +2001-02-21 David Mosberger + + * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two + separate variants: one for IMM22 and the other for IMM14. + * ia64-asmtab.c: Regenerate. + +2001-02-21 Greg McGary + + * cgen-opc.c (cgen_get_insn_value): Add missing `return'. + +2001-02-20 H.J. Lu + + * Makefile.am (ia64-ic.tbl): Remove the target. + (ia64-raw.tbl): Likewise. + (ia64-waw.tbl): Likewise. + (ia64-war.tbl): Likewise. + (ia64-asmtab.c): Generate it in the source directory. + * Makefile.in: Regenerated. + +2001-02-18 lars brinkhoff + + * Makefile.am: Add PDP-11 target. + * configure.in: Likewise. + * disassemble.c: Likewise. + * pdp11-dis.c: New file. + * pdp11-opc.c: New file. + +2001-02-14 Jim Wilson + + * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. + * ia64-asmtab.c: Regenerate. + +2001-02-12 Jan Hubicka + + * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison + instructions. + (putop): Handle 'Y' + +2001-02-11 Maciej W. Rozycki + + * mips-dis.c (print_insn_arg): Use top four bits of the address of + the following instruction not of the jump itself for the jump + target. + (print_mips16_insn_arg): Likewise. + +2001-02-11 Michael Sokolov + + * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build + directory. + * Makefile.in: Regenerate. + +2001-02-09 Schwidefsky + + * Makefile.am: Add linux target for S/390. + * Makefile.in: Likewise. + * configure.in: Likewise. + * disassemble.c: Likewise. + * s390-dis.c: New file. + * s390-mkopc.c: New file. + * s390-opc.c: New file. + * s390-opc.txt: New file. + +2001-02-05 Jim Wilson + + * ia64-asmtab.c: Revert 2000-12-16 change. + +2001-02-02 Patrick Macdonald + + * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. + * m32r-desc.h: Regenerate. + +2001-02-01 Jan Hubicka + + * i386-dis.c (dis386_att, grps): Use 'T' for push/pop + (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax + +2001-01-14 Alan Modra + + * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types. + +2001-01-13 Nick Clifton + + * disassemble.c: Remove spurious white space. + +2001-01-13 Jan Hubicka + + * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret + templates. + +2001-01-11 Peter Targett + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2001-01-10 Jan Hubicka + + * i386-dis.c (PREGRP15 - PREGRP24): New. + (dis386_twobyt): Add SSE2 instructions. + (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions. + (twobyte_uses_f3_prefix): ... this one. + (grps): Add SSE instructions. + (prefix_user_table): Add two new slots; add SSE2 instructions. + (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix; + Handle the REPNZ and Data16 prefixes as well; do proper lookup + to prefix_user_table. + (OP_E): Accept mfence and lfence as well. + (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions. + (OP_XMM): Support REX extensions. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-01-09 Nick Clifton + + * arm-dis.c (print_insn): Set pc to zero for instructions with + a reloc associated with them. + +2001-01-09 Jeff Johnston + + * cgen-asm.in (parse_insn_normal): Changed syn to be + CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn + as character to use CGEN_SYNTAX_CHAR macro and all comparisons + to '\0' to use 0 instead. + * cgen-dis.in (print_insn_normal): Ditto. + * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto. + +2001-01-05 Jan Hubicka + + * i386-dis.c: Add x86_64 support. + (rex): New static variable. + (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants. + (USED_REX): New macro. + (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros. + (OP_I64, OP_OFF64, OP_IMREG): New functions. + (OP_REG, OP_OFF): Declare. + (get64, get32, get32s): New functions. + (r??_reg): New constants. + (dis386_att): Change templates of instruction implicitly promoted + to 64bit; change e?? to RMe?? for unwind RM byte instructions. + (grps): Likewise. + (dis386_intel): Likewise. + (dixx86_64_att): New table based on dis386_att. + (dixx86_64_intel): New table based on dis386_intel. + (names64, names8rex): New global variable. + (names32, names16): Add extended registers. + (prefix_user_t): Recognize rex prefixes. + (prefix_name): Print REX prefixes nicely. + (op_riprel): New global variable. + (start_pc): Set type to bfd_vma. + (print_insn_i386): Detect the 64bit mode and use proper table; + move ckprefix after initializing the buffer; output unused rex prefixes; + output information about target of RIP relative addresses. + (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S'; + (print_operand_value): New function. + (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for + REX prefix and new modes. + (get64, get32s): New. + (get32): Return bfd_signed_vma type. + (set_op): Initialize the op_riprel. + * disassemble.c (disassembler): Recognize the x86-64 disassembly. + +2001-01-03 Richard Sandiford + + cgen-dis.in (read_insn): Use bfd_get_bits() + +2001-01-02 Richard Sandiford + + * cgen-dis.c (hash_insn_array): Use bfd_put_bits(). + (hash_insn_list): Likewise + * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits(). + (extract_1): Use bfd_get_bits(). + (extract_normal): Apply sign extension to both extraction + methods. + * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits() + (cgen_put_insn_value): Use bfd_put_bits() + +2000-12-28 Frank Ch. Eigler + + * cgen-asm.in (parse_insn_normal): Print better error message for + instructions with missing operands. + +2000-12-21 Santeri Paavolainen + + * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined. + +2000-12-16 Nick Clifton + + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure.in: Add spacing. + * configure: Regenerate. + * ia64-asmtab.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-12-12 Frank Ch. Eigler + + * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time + error messages over later parse-time ones. + +2000-12-12 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode + argument. + * ia64-gen.c (insert_deplist): Cast sizeof result to int. + (print_dependency_table): Print NULL if semantics field not set. + (insert_opcode_dependencies): Mark cmp parameter as unused. + (print_main_table): Use fprintf_vma to print long long fields. + (main): Mark argv paramter as unused. Convert to old style definition. + * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. + * ia64-asmtab.c: Regnerate. + +2000-12-09 Nick Clifton + + * m32r-dis.c (print_insn): Prevent re-read of instruction from + wrong address. + + * fr30-dis.c: Regenerate. + +2000-12-08 Peter Targett + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2000-12-03 Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO, + MOD_HILO, and MOD_LO macros. + + * mips-opc.c (M1, M2): Delete. + (mips_builtin_opcodes): Remove all uses of M1. + + * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 + instructions take "G" format second operands and use the + correct flags. + There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to + match. + Delete "sel" code operands from mfc1 and mtc1. + Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants + for dm[ft]c[023]. + +2000-12-03 Ed Satterthwaite ehs@sibyte.com and + Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Finish additions + for MIPS32 support, and clean up existing entries for + aesthetics, consistency with the MIPS32 ISA, and + with consistency the rest of the table. + +2000-12-01 Nick Clifton + + * mips16-opc.c (mips16_opcodes): Add initialiser for membership + field. + +2000-12-01 Chris Demetriou + + mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument + specifiers. Update 'B' for new constant names, and remove + 'm'. + mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" + near the top of the array, so they are disassembled properly. + Enable "ssnop" for MIPS32. Add "break" variant with 20 bit + code for MIPS32. Update "clo" and "clz" to use 'U' operand + specifier. Add 'H' format specifier variants for "mfc1," + "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update + MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 + "wait" variant which uses 'J' operand specifier. + + * mips-dis.c (set_mips_isa_type): Update to use + CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case. + Replace bfd_mach_mips4K with bfd_mach_mips32_4k case. + * mips-opc.c (I32): New constant for instructions added in + MIPS32. + (P4): Delete. + (mips_builtin_opcodes) Replace all uses of P4 with I32. + + * mips-dis.c (set_mips_isa_type): Add cases for + bfd_mach_mips5 and bfd_mach_mips64. + * mips-opc.c (I64): New definitions. + + * mips-dis.c (set_mips_isa_type): Add case for + bfd_mach_mips_sb1. + +2000-11-28 Hans-Peter Nilsson + + * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. + (print_insn_ppi): Make nib1, nib2, nib3 unsigned. + Initialize variable dc to NULL. + (print_insn_shx): Remove unused label d_reg_n. + +2000-11-24 Nick Clifton + + * arm-opc.h: Add new opcode formatting parameter 'B'. + (arm_opcodes): Add XScale, v5, and v5te instructions. + (thumb_opcodes): Add v5t instructions. + + * arm-dis.c (print_insn_arm): Handle new 'B' format + parameter. + (print_insn_thumb): Decode BLX(1) instruction. + +2000-11-21 Chris Demetriou + + * mips-opc.c: Fix file header comment. + +2000-11-14 Hans-Peter Nilsson + + * cris-dis.c (cris_get_disassembler): If abfd is NULL, return + print_insn_cris_with_register_prefix. + +2000-11-11 Alexandre Oliva + + * sh-opc.h: The operand of `mov.w r0, (,GBR)' is IMM1, not 0. + +2000-11-07 Matthew Green + + * cgen-dis.in (print_insn): All insns which can fit into insn_value + must be loaded there in their entirety. + +2000-10-20 Jakub Jelinek + + * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. + (compute_arch_mask): Add v8plusb and v9b machines. + (print_insn_sparc): siam mode decoding, accept ASRs up to 25. + * sparc-opc.c: Support for Cheetah instruction set. + (prefetch_table): Add #invalidate. + +2000-10-16 Nick Clifton + + * mcore-dis.c (imsk): Change mask for OC to 0xFE00. + +2000-10-06 Dave Brolley + + * fr30-desc.h: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-ibld.c: Regenerate. + +2000-10-05 Jim Wilson + + * ia64-ic.tbl: Update from Intel. + * ia64-asmtab.c: Regenerate. + +2000-10-04 Kazu Hirata + + * ia64-gen.c: Convert C++-style comments to C-style comments. + * tic54x-dis.c: Likewise. + +2000-09-29 Hans-Peter Nilsson + + Changes to add dollar prefix to registers for files where user symbols + don't have a leading underscore. Fix formatting. + * cris-dis.c (REGISTER_PREFIX_CHAR): New. + (format_reg): Add parameter with_reg_prefix. All callers changed. + (print_with_operands): Ditto. + (print_insn_cris_generic): Renamed from print_insn_cris, add + parameter with_reg_prefix. + (print_insn_cris_with_register_prefix, + print_insn_cris_without_register_prefix, cris_get_disassembler): + New. + * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler. + +2000-09-22 Jim Wilson + + * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for + gt, ge, ngt, and nge. + * ia64-asmtab.c: Regenerate. + + * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. + * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. + (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". + * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. + * ia64-asmtab.c: Regnerate. + +2000-09-13 Anders Norlander + + * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores. + Add mfc0 and mtc0 with sub-selection values. + Add clo and clz opcodes. + Add msub and msubu instructions for MIPS32. + Add madd/maddu aliases for mad/madu for MIPS32. + Support wait, deret, eret, movn, pref for MIPS32. + Support tlbp, tlbr, tlbwi, tlbwr. + (P4): New define. + + * mips-dis.c (print_insn_arg): Print sdbbp 'm' args. + (print_insn_arg): Handle 'H' args. + (set_mips_isa_type): Recognize 4K. + Use CPU_* defines instead of hardcoded numbers. + +2000-09-11 Catherine Moore + + * d30v-opc.c (d30v_operand_t): New operand type Rb2. + (d30v_format_tab): Use Rb2 for modinc and moddec. + +2000-09-07 Catherine Moore + + * d30v-opc.c (d30v_format_tab): Use format Ra for + modinc and moddec. + +2000-09-06 Alexandre Oliva + + * configure: Rebuilt with new libtool.m4. + +2000-09-05 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-08-31 Alexandre Oliva + + * acinclude.m4: Include libtool and gettext macros from the + top level. + * aclocal.m4, configure: Rebuilt. + +2000-08-30 Kazu Hirata + + * tic80-dis.c: Fix formatting. + +2000-08-29 Kazu Hirata + + * w65-dis.c: Fix formatting. + +2000-08-28 Mark Hatle + + * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics. + (powerpc_opcodes): Add table entries for PPC 405 instructions. + Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 + instructions. Added extended mnemonic mftbl as defined in the + 405GP manual for all PPCs. + +2000-08-28 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode + call. Change last goto to use failed instead of done. + +2000-08-28 Dave Brolley + + * cgen-ibld.in (cgen_put_insn_int_value): New function. + (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. + (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + * cgen-dis.in (read_insn): New static function. + (print_insn): Use read_insn to read the insn into the buffer and set + up for disassembly. + (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is + in the buffer. + * fr30-asm.c: Regenerated. + * fr30-desc.c: Regenerated. + * fr30-desc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-ibld.c: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * m32r-asm.c: Regenerated. + * m32r-desc.c: Regenerated. + * m32r-desc.h: Regenerated. + * m32r-dis.c: Regenerated. + * m32r-ibld.c: Regenerated. + * m32r-opc.c: Regenerated. + +2000-08-28 Kazu Hirata + + * tic30-dis.c: Fix formatting. + +2000-08-27 Kazu Hirata + + * sh-dis.c: Fix formatting. + +2000-08-24 David Edelsohn + + * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd. + +2000-08-24 Kazu Hirata + + * z8k-dis.c: Fix formatting. + +2000-08-16 Jim Wilson + + * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete + break, mov-immediate, nop. + * ia64-opc-f.c: Delete fpsub instructions. + * ia64-opc-m.c: Add POSTINC to all instructions with postincrement + address operand. Rewrite using macros to avoid long lines. + * ia64-opc.h (POSTINC): Define. + * ia64-asmtab.c: Regenerate. + +2000-08-15 Jim Wilson + + * ia64-ic.tbl: Add missing entries. + +2000-08-08 Jason Eckhardt + + * i860-dis.c (print_br_address): Change third argument from int + to long. + +2000-08-07 Richard Henderson + + * ia64-dis.c (print_insn_ia64): Get byte skip count correct + for MLI templates. Handle IA64_OPND_TGT64. + +2000-08-04 Ben Elliston + + * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files. + * cgen.sh: Likewise. + +2000-08-02 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end. + +2000-07-29 Marek Michalkiewicz + + * avr-dis.c (avr_operand): Use PARAMS macro in declaration. + Change return type from void to int. Check the combination + of operands, return 1 if valid. Fix to avoid BUF overflow. + Report undefined combinations of operands in COMMENT. + Report internal errors to stderr. Output the adiw/sbiw + constant operand in both decimal and hex. + (print_insn_avr): Disassemble ldd/std with displacement of 0 + as ld/st. Check avr_operand () return value, handle invalid + combinations of operands like unknown opcodes. + +2000-07-28 Ben Elliston + + * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New. + (run-cgen, stamp-m32r, stamp-fr30): New targets. + * Makefile.in: Regenerate. + * configure.in: Add --enable-cgen-maint option. + * configure: Regenerate. + +2000-07-26 Dave Brolley + + * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (print_address): Ditto. + (print_keyword): Ditto. + * cgen-dis.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + * cgen-asm.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + (cgen_parse_keyword): Ditto. + +2000-07-22 Jason Eckhardt + + * i860-dis.c: New file. + (print_insn_i860): New function. + (print_br_address): New function. + (sign_extend): New function. + (BITWISE_OP): New macro. + (I860_REG_PREFIX): New macro. + (grnames, frnames, crnames): New structures. + + * disassemble.c (ARCH_i860): Define. + (disassembler): Add check for bfd_arch_i860 to set disassemble + function to print_insn_i860. + + * Makefile.in (CFILES): Added i860-dis.c. + (ALL_MACHINES): Added i860-dis.lo. + (i860-dis.lo): New dependences. + + * configure.in: New bits for bfd_i860_arch. + + * configure: Regenerated. + +2000-07-20 Hans-Peter Nilsson + + * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c. + (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. + (cris-dis.lo, cris-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure.in (bfd_cris_arch): New target. + * configure: Rebuild. + * disassemble.c (ARCH_cris): Define. + (disassembler): Support ARCH_cris. + * cris-dis.c, cris-opc.c: New files. + * po/POTFILES.in, po/opcodes.pot: Regenerate. + +2000-07-11 Jakub Jelinek + + * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2. + Reported by Bill Clarke . + +2000-07-09 Geoffrey Keating + + * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw. + Patch by Randall J Fisher . + +2000-07-09 Alan Modra + + * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg, + fput_const, extract_3, extract_5_load, extract_5_store, + extract_5r_store, extract_5R_store, extract_10U_store, + extract_5Q_store, extract_11, extract_14, extract_16, extract_21, + extract_12, extract_17, extract_22): Prototype. + (print_insn_hppa): Rename inner block opcode -> opc to avoid + shadowing outer block. + (GET_BIT): Define. + +2000-07-05 DJ Delorie + + * MAINTAINERS: new + +2000-07-04 Alexandre Oliva + + * arm-dis.c (print_insn_arm): Output combinations of PSR flags. + +2000-07-03 Marek Michalkiewicz + + * avr-dis.c (avr_operand): Change _ () to _() around all strings + marked for translation (exception from the usual coding style). + (print_insn_avr): Initialize insn2 to avoid warnings. + +2000-07-03 Kazu Hirata + + * h8300-dis.c (bfd_h8_disassemble): Improve readability. + * h8500-dis.c: Fix formatting. + +2000-07-01 Alan Modra + + * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed + (CLEANFILES): Add DEPA. + * Makefile.in: Regenerate. + +2000-06-26 Scott Bambrough + + * arm-dis.c (regnames): Add an additional register set to match + the set used by GCC. Make it the default. + +2000-06-22 Alan Modra + + * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we + find one. + * Makefile.in: Regenerate. + +2000-06-20 H.J. Lu + + * Makefile.am: Rebuild dependency. + * Makefile.in: Rebuild. + +2000-06-18 Stephane Carrez + + * Makefile.in, configure: regenerate + * disassemble.c (disassembler): Recognize ARCH_m68hc12, + ARCH_m68hc11. + * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12): + New functions. + * configure.in: Recognize m68hc12 and m68hc11. + * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x + * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly + and opcode generation for m68hc11 and m68hc12. + +2000-06-16 Nick Duffek + + * disassemble.c (disassembler): Refer to the PowerPC 620 using + bfd_mach_ppc_620 instead of 620. + +2000-06-12 Kazu Hirata + + * h8300-dis.c: Fix formatting. + (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl] + correctly. + +2000-06-09 Denis Chertykov + + * avr-dis.c (avr_operand): Bugfix for jmp/call address. + +2000-06-07 Denis Chertykov + + * avr-dis.c: completely rewritten. + +2000-06-02 Kazu Hirata + + * h8300-dis.c: Follow the GNU coding style. + (bfd_h8_disassemble) Fix a typo. + +2000-06-01 Kazu Hirata + + * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo. + (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl] + correctly. Fix a typo. + +2000-05-31 Nick Clifton + + * opintl.h (_(String)): Explain why dgettext is used instead of + gettext. + +2000-05-30 Nick Clifton + + * opintl.h (gettext, dgettext, dcgettext, textdomain, + bindtextdomain): Replace defines with those from intl/libgettext.h + to quieten gcc warnings. + +2000-05-26 Alan Modra + + * Makefile.am: Update dependencies with "make dep-am" + * Makefile.in: Regenerate. + +2000-05-25 Alexandre Oliva + + * m10300-dis.c (disassemble): Don't assume 32-bit longs when + sign-extending operands. + +2000-05-15 Donald Lindsay + + * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches + except brf's. + +2000-05-21 Nick Clifton + + * Makefile.am (LIBIBERTY): Define. + +2000-05-19 Diego Novillo + + * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES. + (STD_REGISTER_NAMES): New name for REGISTER_NAMES. + (reg_names): Rename to std_reg_names. Change it to a char ** + static variable. + (std_reg_names): New name for reg_names. + (set_mips_isa_type): Set reg_names to point to std_reg_names by + default. + +2000-05-16 Frank Ch. Eigler + + * fr30-desc.h: Partially regenerated to account for changed + CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. + * m32r-desc.h: Ditto. + +2000-05-15 Nick Clifton + + * arm-opc.h: Use upper case for flasg in MSR and MRS + instructions. Allow any bit to be set in the field_mask of + the MSR instruction. + + * arm-dis.c (print_insn_arm): Decode _x and _s bits of the + field_mask of an MSR instruction. + +2000-05-11 Thomas de Lellis + + * arm-opc.h: Disassembly of thumb ldsb/ldsh + instructions changed to ldrsb/ldrsh. + +2000-05-11 Ulf Carlsson + + * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit + target addresses for 'jal' and 'j'. + +2000-05-10 Geoff Keating + + * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes + also available in common mode when powerpc syntax is being used. + +2000-05-08 Alan Modra + + * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args. + (dummy_print_address): Ditto. + +2000-05-04 Timothy Wall + + * tic54x-opc.c: New. + * tic54x-dis.c: New. + * disassemble.c (disassembler): Add ARCH_tic54x. + * configure.in: Added tic54x target. + * configure: Ditto. + * Makefile.am: Add tic54x dependencies. + * Makefile.in: Ditto. + +2000-05-03 J.T. Conklin + + * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for + vector unit operands. + (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector + unit instruction formats. + (PPCVEC): New macro, mask for vector instructions. + (powerpc_operands): Add table entries for above operand types. + (powerpc_opcodes): Add table entries for vector instructions. + + * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Prepend 'v' when printing vector registers. + +2000-04-24 Clinton Popetz + + * configure.in: Add bfd_powerpc_64_arch. + * disassemble.c (disassembler): Use print_insn_big_powerpc for + 64 bit code. + +2000-04-24 Nick Clifton + + * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow + field. + +2000-04-23 Denis Chertykov + + * avr-dis.c (reg_fmul_d): New. Extract destination register from + FMUL instruction. + (reg_fmul_r): New. Extract source register from FMUL instruction. + (reg_muls_d): New. Extract destination register from MULS instruction. + (reg_muls_r): New. Extract source register from MULS instruction. + (reg_movw_d): New. Extract destination register from MOVW instruction. + (reg_movw_r): New. Extract source register from MOVW instruction. + (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, + EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions. + +2000-04-22 Timothy Wall + + * ia64-gen.c (general): Add an ordered table of primary + opcode names, as well as priority fields to disassembly data + structures to enforce a preferred disassembly format based on the + ordering of the opcode tables. + (load_insn_classes): Show a useful message if IC tables are missing. + (load_depfile): Ditto. + * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to + distinguish preferred disassembly. + * ia64-opc-f.c: Reorder some insn for preferred disassembly + format. Fix incorrect flag on fma.s/fma.s.s0. + * ia64-opc.c: Scan *all* disassembly matches and use the one with + the highest priority. + * ia64-opc-b.c: Use more abbreviations. + * ia64-asmtab.c: Regenerate. + +2000-04-21 Jason Eckhardt + + * hppa-dis.c (extract_16): New function. + (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of + new operand types l,y,&,fe,fE,fx. + +2000-04-21 Richard Henderson + David Mosberger + Timothy Wall + Bob Manson + Jim Wilson + + * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. + (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, + ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, + ia64-asmtab.c. + (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. + (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, + ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure Rebuild. + * configure.in (bfd_ia64_arch): New target. + * disassemble.c (ARCH_ia64): Define. + (disassembler): Support ARCH_ia64. + * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, + ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, + ia64-war.tbl, ia64-waw.tbl: New files. + +2000-04-20 Alexandre Oliva + + * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. + (disassemble): Use them. + +2000-04-14 Alan Modra + + * sysdep.h: Include "ansidecl.h" not + * Makefile.am: Update dependencies. + * Makefile.in: Regenerate. + +2000-04-14 Michael Sokolov + + * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, + avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, + disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, + i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, + m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, + mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, + ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, + tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, + w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove + ansidecl.h as sysdep.h includes it. + +2000-04-7 Andrew Cagney + + * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add + --enable-build-warnings option. + * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions. + * Makefile.in, configure: Re-generate. + +2000-04-05 J"orn Rennecke + + * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. + stc GBR,@- is available for arch_sh1_up. + Group parallel processing insn with identical mnemonics together. + Make three-operand psha / pshl come first. + +2000-04-05 J"orn Rennecke + + * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + (sh_arg_type): Add A_PC. + (sh_table): Update entries using immediates. Add repeat. + * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + +2000-04-04 Alan Modra + + * po/opcodes.pot: Regenerate. + + * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. + (DEP): Quote when passing vars to sub-make. Add warning message + to end. + (DEP1): Rewrite for "gcc -MM". + (CLEANFILES): Add DEP2. + Update dependencies. + * Makefile.in: Regenerate. + +2000-04-03 Denis Chertykov + + * avr-dis.c: Syntax cleanup. + (add0fff): Print the pc relative address as a signed number. + (add03f8): Likewise. + +2000-04-01 Ian Lance Taylor + + * disassemble.c (disassembler_usage): Don't use a prototype. Mark + the parameter ATTRIBUTE_UNUSED. + * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. + +2000-04-01 Alexandre Oliva + + * m10300-opc.c: SP-based offsets are always unsigned. + +2000-03-29 Thomas de Lellis + + * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" + [branch always] instead of "undefined". + +2000-03-27 Nick Clifton + + * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of + short instructions, from end of list of long instructions. + +2000-03-27 Ian Lance Taylor + + * Makefile.am (CFILES): Add avr-dis.c. + (ALL_MACHINES): Add avr-dis.lo. + +2000-03-27 Alan Modra + + * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to + truncate integers. + (print_insn_avr): Call function via pointer in K&R compatible way. + (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, + add0fff, add03f8): Convert to old style function declaration and + add prototype. + (avrdis_opcode): Add prototype. + +2000-03-27 Denis Chertykov + + * avr-dis.c: New file. AVR disassembler. + * configure.in (bfd_avr_arch): New architecture support. + * disassemble.c: Likewise. + * configure: Regenerate. + +2000-03-06 J"oern Rennecke + + * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. + +2000-03-02 J"orn Rennecke + + * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand + flag to determine if operand is pc-relative. + * d30v-opc.c: + (d30v_format_table): + (REL6S3): Renamed from IMM6S3. + Added flag OPERAND_PCREL. + (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with + added flag OPERAND_PCREL. + (IMM12S3U): Replaced with REL12S3. + (SHORT_D2, LONG_D): Delay target is pc-relative. + (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): + Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, + using the REL* operands. + (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. + (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, + LONG_Db, using REL* operands. + (SHORT_U, SHORT_A5S): Removed stray alternatives. + (d30v_opcode_table): Use new *r formats. + +2000-02-28 Nick Clifton + + * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with + 'signed_overflow_ok_p'. + +2000-02-27 Eli Zaretskii + + * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the + name of the libtool directory. + * Makefile.in: Rebuild. + +2000-02-24 Nick Clifton + + * cgen-opc.c (cgen_set_signed_overflow_ok): New function. + (cgen_clear_signed_overflow_ok): New function. + (cgen_signed_overflow_ok_p): New function. + +2000-02-23 Andrew Haley + + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, + m32r-ibld.c, m32r-opc.h: Rebuild. + +2000-02-23 Linas Vepstas + + * i370-dis.c, i370-opc.c: New. + + * disassemble.c (ARCH_i370): Define. + (disassembler): Handle it. + + * Makefile.am: Add support for Linux/IBM 370. + * configure.in: Likewise. + + * Makefile.in: Regenerate. + * configure: Likewise. + +2000-02-22 Chandra Chavva + + * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to + ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel + procedure. + +2000-02-22 Andrew Haley + + * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: + force gp32 to zero. + * mips-opc.c (G6): New define. + (mips_builtin_op): Add "move" definition for -gp32. + +2000-02-22 Ian Lance Taylor + + From Grant Erickson : + * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. + +2000-02-21 Alan Modra + + * dis-buf.c (buffer_read_memory): Change `length' param and all int + vars to unsigned. + +2000-02-17 J"orn Rennecke + + * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. + (print_insn_ppi): Likewise. + (print_insn_shx): Use info->mach to select appropriate insn set. + Add support for sh-dsp. Remove FD_REG_N support. + * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. + (sh_arg_type): Likewise. Remove FD_REG_N. + (sh_dsp_reg_nums): New enum. + (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. + (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. + (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. + (arch_sh3_dsp_up): Likewise. + (sh_opcode_info): New field: arch. + (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and + D_REG_N. Fill in arch field. Add sh-dsp insns. + +2000-02-14 Fernando Nasser + + * arm-dis.c: Change flavor name from atpcs-special to + special-atpcs to prevent name conflict in gdb. + (get_arm_regname_num_options, set_arm_regname_option, + get_arm_regnames): New functions. API to access the several + flavor of register names. Note: Used by gdb. + (print_insn_thumb): Use the register name entry from the currently + selected flavor for LR and PC. + +2000-02-10 Nick Clifton + + * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR + classes. + (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and + "mulsh.h" instructions. + * mcore-dis.c (imsk array): Add masks for MULSH and OPSR + classes. + (print_insn_mcore): Add support for little endian targets. + Add support for MULSH and OPSR classes. + +2000-02-07 Nick Clifton + + * arm-dis.c (parse_arm_diassembler_option): Rename again. + Previous delat did not take. + +2000-02-03 Timothy Wall + + * dis-buf.c (buffer_read_memory): Use octets_per_byte field + to adjust target address bounds checking and calculate the + appropriate octet offset into data. + +2000-01-27 Nick Clifton + + * arm-dis.c: (parse_disassembler_option): Rename to + parse_arm_disassembler_option and allow to be exported. + + * disassemble.c (disassembler_usage): New function: Print out any + target specific disassembler options. + Call arm_disassembler_options() if the ARM architecture is being + supported. + + * arm-dis.c (NUM_ELEM): Define this macro if not already + defined. + (arm_regname): New struct type for ARM register names. + (arm_toggle_regnames): Delete. + (parse_disassembler_option): Use register name structure. + (print_insn): New function: Combines duplicate code found in + print_insn_big_arm and print_insn_little_arm. + (print_insn_big_arm): Call print_insn. + (print_insn_little_arm): Call print_insn. + (print_arm_disassembler_options): Display list of supported, + ARM specific disassembler options. + +2000-01-27 Thomas de Lellis + + * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the + ARM_STT_16BIT flag as Thumb code symbols. + + * arm-dis.c (printf_insn_little_arm): Ditto. + +2000-01-25 Thomas de Lellis + + * arm-dis.c (printf_insn_thumb): Prevent double dumping + of raw thumb instructions. + +2000-01-20 Nick Clifton + + * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". + +2000-01-03 Nick Clifton + + * arm-dis.c (streq): New macro. + (strneq): New macro. + (force_thumb): ew local variable. + (parse_disassembler_option): New function: Parse a single, ARM + specific disassembler command line switch. + (parse_disassembler_option): Call parse_disassembler_option to + parse individual command line switches. + (print_insn_big_arm): Check force_thumb. + (print_insn_little_arm): Check force_thumb. + +For older changes see ChangeLog-9899 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-0203 b/external/gpl3/gdb/dist/opcodes/ChangeLog-0203 new file mode 100644 index 000000000000..25ed8b558687 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-0203 @@ -0,0 +1,2110 @@ +2003-12-15 Christian Groessler + + * z8k-dis.c (intr_names): Removed. + (print_intr, print_flags): New functions. + (unparse_instr): Use new functions. + +2003-12-15 Kazuhiro Inaoka + + * m32r-opc.c: Regenerate. + +2003-12-14 Mark Mitchell + + * arm-opc.h (arm_opcodes): Put V6 instructions before XScale + instructions. + +2003-12-13 Hans-Peter Nilsson + + * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE, + SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE + and SWYM_INSN_BYTE instead of raw numbers. + +2003-12-10 Zack Weinberg + + * ppc-opc.c (MO): Make optional. + (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. + (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. + +2003-12-05 Ricardo Anguiano + Mark Mitchell + Richard Earnshaw + + * arm-dis.c (print_arm_insn): Add 'W' macro. + * arm-opc.h (arm_opcodes): Add V6 instructions. + (thumb_opcodes): Likewise. + +2003-12-04 Alan Modra + + * openrisc-asm.c: Regenerate. + * pj-opc.c: Update copyright date. + +2003-12-03 Kazuhiro Inaoka + + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2003-12-02 Alexandre Oliva + + * sh-opc.h: Add support for sh4a and no-fpu variants. + * sh-dis.c: Ditto. + +2003-12-02 Kazu Hirata + + * alpha-opc.c: Remove ARGSUSED. + * i370-opc.c: Likewise. + * ppc-opc.c: Likewise. + +2003-12-02 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2003-11-28 Christian Groessler + + * z8k-dis.c: Convert to ISO C90. + * z8kgen.c: Convert to ISO C90. + (opt): Move long opcode for "ldb rdb,imm8" after short one, now + the short one is created when assembling. + * z8k-opc.h: Regenerate with new z8kgen.c. + +2003-11-19 Kazu Hirata + + * h8300-dis.c (print_colon_thingie): Remove. + +2003-11-18 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and + "dlca". + +2003-11-14 Nick Clifton + + * dis-init.c (init_disassemble_info): Initialise + symbol_is_valid field. + * dis-buf.c (generic_symbol_is_valid): New function. Always + returns TRUE. + * arm-dis.c (arm_symbol_is_valid): New function. Return FALSE + for ARM ELF mapping symbols. + * disassemble.c (disassemble_init_for_target): Set + symbol_is_valid field to arm_symbol_is_valid of the target is + an ARM. + +2003-11-05 H.J. Lu + + * m68k-opc.c (m68k_opcodes): Reorder "fmovel". + +2003-11-03 Daniel Jacobowitz + + * arm-dis.c (print_arm_insn): Print "-" after "#". + +2003-10-30 Falk Hueffner + + * alpha-opc.c: Add support for a second argument to RPCC. + +2003-10-27 Stephane Carrez + + * m68hc11-dis.c: Convert to ISO C90 prototypes. + +2003-10-21 Peter Barada + Bernardo Innocenti + + * m68k-dis.c: Add MCFv4/MCF5528x support. + * m68k-opc.c: Likewise. + +2003-10-10 Dave Brolley + + * frv-asm.c,frv-desc.c,frv-opc.c: Regenerated. + +2003-10-08 Dave Brolley + + * frv-desc.[ch], frv-opc.[ch]: Regenerated. + +2003-09-30 Bob Wilson + + * xtensa-dis.c (fetch_data): Remove numBytes parameter. + (print_insn_xtensa): Fix call to fetch_data. + +2003-09-30 Chris Demetriou + + * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" + (print_insn_args): Add handing for +E, +F, +G, and +H. + * mips-opc.c (I65): New define for MIPS64r2. + (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", + "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", + and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to + be supported on MIPS64r2. + +2003-09-24 Dave Brolley + + * frv-desc.c, frv-opc.c, frv-opc.h: Regenerated. + +2003-09-14 Andreas Jaeger + + * i386-dis.c: Convert to ISO C90 prototypes. + * i370-dis.c: Likewise. + * i370-opc.c: Likewiwse. + * i960-dis.c: Likewise. + * ia64-opc.c: Likewise. + +2003-09-09 Dave Brolley + + * frv-desc.c: Regenerated. + +2003-09-08 Dave Brolley + + On behalf of Doug Evans + * Makefile.am (run-cgen): Pass new args archfile and opcfile + to cgen.sh. + (stamp-ip2k,stamp-m32r,stamp-fr30,stamp-frv,stamp-openrisc, + stamp-iq2000,stamp-xstormy16): Pass paths of .cpu and .opc files + to cgen.sh. + (stamp-frv): Delete hardcoded path spec workaround. + * Makefile.in: Regenerate. + * cgen.sh: New args archfile and opcfile. Pass on to cgen. + +2003-09-04 Nick Clifton + + * v850-dis.c (disassemble): Accept bfd_mach_v850e1. + * v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions. + +2003-09-04 Alan Modra + + * ppc-dis.c (struct dis_private): New. + (powerpc_dialect): Make static. Accept -Many in addition to existing + options. Save dialect in dis_private. + (print_insn_big_powerpc): Retrieve dialect from dis_private. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Call powpc_dialect here. Remove unnecessary + efs/altivec check. Try harder to disassemble if given -Many. + * ppc-opc.c (insert_fxm): Expand comment. + (PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY. + (POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise. + (POWER4): Remove PPCCOM. + (PPCONLY): Don't define. Update all occurrences to PPC. + +2003-09-03 Andrew Cagney + + * dis-init.c (init_disassemble_info): New file and function. + * Makefile.am (CFILES): Add "dis-init.c". + (libopcodes_la_SOURCES): Add "dis-init.c". + (dis-init.lo): Specify dependencies. + * Makefile.in: Regenerate. + +2003-09-03 Dave Brolley + + * frv-*: Regenerated. + +2003-09-02 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries. + Move duplicate mnemonic entries together. Use RS instead of RT on + all mt*. + * ppc-dis.c: Convert to ISO C. + +2003-08-29 Dave Brolley + + * Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from + $(srcdir)/../cpu temporarily when regenerating source files. + * Makefile.in: Regenerated. + +2003-08-19 Nick Clifton + + * arm-dis.c (print_insn_arm: case 'A'): Add code to + disassemble unindexed form of Addressing Mode 5. + +2003-08-19 Alan Modra + + * ppc-opc.c (PPC440): Define. + (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci, + icread instructions when PPC440. Add dlmzb instruction. + +2003-08-14 Alan Modra + + * dep-in.sed: Remove libintl.h. + * Makefile.am (POTFILES.in): Unset LC_COLLATE. + Run "make dep-am". + * Makefile.in: Regenerate. + +2003-08-07 Michael Meissner + + * cgen-asm.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_set_parse_operand_fn): Prototype definition. + (cgen_init_parse_operand): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_asm_lookup_insn): Ditto. + (cgen_parse_keyword): Ditto. + (cgen_parse_signed_integer): Ditto. + (cgen_parse_unsigned_integer): Ditto. + (cgen_parse_address): Ditto. + (cgen_validate_signed_integer): Ditto. + (cgen_validate_unsigned_integer): Ditto. + + * cgen-opc.c (hash_keyword_name): Remove PARAMS macro. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_keyword_lookup_name): Prototype definition. + (cgen_keyword_lookup_value): Ditto. + (cgen_keyword_add): Ditto. + (cgen_keyword_search_init): Ditto. + (cgen_keyword_search_next): Ditto. + (hash_keyword_name): Ditto. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_hw_lookup_by_name): Ditto. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (cgen_operand_lookup_by_num): Ditto. + (cgen_insn_count): Ditto. + (cgen_macro_insn_count): Ditto. + (cgen_get_insn_value): Ditto. + (cgen_put_insn_value): Ditto. + (cgen_lookup_insn): Ditto. + (cgen_get_insn_operands): Ditto. + (cgen_lookup_get_insn_operands): Ditto. + (cgen_set_signed_overflow_ok): Ditto. + (cgen_clear_signed_overflow_ok): Ditto. + (cgen_signed_overflow_ok_p): Ditto. + + * cgen-dis.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (count_decodable_bits): Ditto. + (add_insn_to_hash_chain): Ditto. + (count_decodable_bits): Prototype definition. + (add_insn_to_hash_chain): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (cgen_dis_lookup_insn): Ditto. + + * cgen-asm.in (parse_insn_normal): Remove PARAMS macro. + (@arch@_cgen_build_insn_regex): Prototype definition. + (parse_insn_normal): Ditto. + (@arch@_cgen_assemble_insn): Ditto. + (@arch@_cgen_asm_hash_keywords): Ditto. + + * cgen-dis.in (print_normal): Remove PARAMS macro. Use void * + instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (read_insn): Ditto. + (print_normal): Prototype definition. Use void * instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (read_insn): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (print_insn_@arch@): Ditto. + + * cgen-ibld.in (insert_normal): Remove PARAMS macro. + (insn_insn_normal): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (insert_1): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (insert_1): Prototype definition. + (insert_normal): Ditto. + (insert_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + + * fr30-asm.c: Regenerate. + * fr30-dis.c: Ditto. + * fr30-ibld.c: Ditto. + * frv-asm.c: Ditto. + * frv-dis.c: Ditto. + * frv-ibld.c: Ditto. + * ip2k-asm.c: Ditto. + * ip2k-dis.c: Ditto. + * ip2k-ibld.c: Ditto. + * iq2000-asm.c: Ditto. + * iq2000-dis.c: Ditto. + * iq2000-ibld.c: Ditto. + * m32r-asm.c: Ditto. + * m32r-dis.c: Ditto. + * m32r-ibld.c: Ditto. + * openrisc-asm.c: Ditto. + * openrisc-dis.c: Ditto. + * openrisc-ibld.c: Ditto. + * xstormy16-asm.c: Ditto. + * xstormy16-dis.c: Ditto. + * xstormy16-ibld.c: Ditto. + +2003-08-06 Nick Clifton + + * po/fr.po: Updated French translation. + +2003-08-05 Nick Clifton + + * configure.in (ALL_LINGUAS): Add nl. + * configure: Regenerate. + * po/nl.po: New Dutch translation. + +2003-07-30 Jason Eckhardt + + * i860-dis.c: Convert to ISO C90. Remove superflous prototypes. + +2003-07-30 Nick Clifton + + * po/ro.po: Updated Romanian translation. + +2003-07-29 Jakub Jelinek + + * ppc-opc.c (insert_mbe, extract_mbe): Shift 1L instead of 1 up. + +2003-07-24 Nick Clifton + + * po/fr.po: Updated French translation. + +2003-07-18 Nick Clifton + + * arm-dis.c (parse_arm_disassembler_option): Do not expect + option string to be NUL terminated. + (parse_disassembler_options): Allow options to be space or + comma separated. + +2003-07-17 Nick Clifton + + * po/es.po: New Spanish translation. + * po/sv.po: New Swedish translation. + * po/opcodes.pot: Regenerate. + +2003-07-15 Richard Sandiford + + * mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries. + +2003-07-14 Nick Clifton + + * po/tr.po: Update with latest version. + * po/POTFILES.in: Regenerate. + * Makefile.in: Regenerate. + +2003-07-11 Alan Modra + + * po/opcodes.pot: Regenerate. + +2003-07-09 Alexandre Oliva + + 2000-05-25 Alexandre Oliva + * m10300-dis.c (disassemble): Negate negative accumulator's shift. + 2000-05-24 Alexandre Oliva + * m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume + 32-bit longs when sign-extending operands. + 2000-04-20 Alexandre Oliva + * m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs. + * m10300-dis.c (HAVE_AM33_2): Define. + (disassemble): Use it. + (HAVE_AM33): Redefine. + (print_insn_mn10300): Fix mask for 5-byte extended insns. + 2000-04-01 Alexandre Oliva + * m10300-opc.c: Renamed AM332 to AM33_2. + 2000-03-31 Alexandre Oliva + * m10300-opc.c: Defined AM33 2.0 register operands. Added support + for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and + bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns. + * m10300-dis.c (print_insn_mn10300): Recognize 5byte extended + insn code of AM33 2.0. + (disassemble): Recognize FMT_D3. Print out FP register names. + +2003-07-09 Chris Demetriou + + * mips-dis.c (set_default_mips_dis_options): Get BFD from + the disassembler_info's section, rather than from the + disassembler_info's symbols pointer. + +2003-07-07 Alan Modra + + * ppc-opc.c: Remove NULL pointer checks. Formatting. Remove + extraneous ATTRIBUTE_UNUSED. + * ppc-dis.c (print_insn_powerpc): Always pass a valid address to + operand->extract. + +2003-07-04 Alan Modra + + * ppc-opc.c: Convert to C90, removing unnecessary prototypes and + casts. Formatting. + + * ppc-opc.c: Remove PARAMS from prototypes. + (FXM4): Define. + (insert_fxm): New function, used by both FXM and FXM4. + (extract_fxm): Likewise. + (XFXFXM_MASK): Remove 1 << 20 term. + (powerpc_opcodes): Add Power4 version of "mfcr". Simplify "mtcr" mask. + +2003-07-01 Martin Schwidefsky + + * s390-dis.c (s390_extract_operand): Add support for long displacements. + * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z990. + * s390-opc.c (D20_20): Add define for 20 bit displacements. + (INSTR_RRF_R0RR, INSTR_RSL_R0RD, INSTR_RSY_RRRD, INSTR_RSY_RURD, + INSTR_RSY_AARD, INSTR_RXY_RRRD, INSTR_RXY_FRRD, INSTR_SIY_URD): Add + new instruction formats. + (MASK_RRF_R0RR, MASK_RSL_R0RD, MASK_RSY_RRRD, MASK_RSY_RURD, + MASK_RSY_AARD, MASK_RXY_RRRD, MASK_RXY_FRRD, MASK_SIY_URD): Likewise. + (s390_opformats): Likewise. + * s390-opc.txt: Add new instructions for cpu type z990. Add missing + hfp instructions. Add missing instructions pgin, pgout and xsch. + +2003-06-23 H.J. Lu + + * i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in + Intel Precott New Instructions. + (PREGRP27): New. Added for "addsubpd" and "addsubps". + (PREGRP28): New. Added for "haddpd" and "haddps". + (PREGRP29): New. Added for "hsubpd" and "hsubps". + (PREGRP30): New. Added for "movsldup" and "movddup". + (PREGRP31): New. Added for "movshdup" and "movhpd". + (PREGRP32): New. Added for "lddqu". + (dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry. + Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for + entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for + entry 0xd0. Use PREGRP32 for entry 0xf0. + (twobyte_has_modrm): Updated. + (twobyte_uses_SSE_prefix): Likewise. + (grps): Use PNI_Fixup in the "sidtQ" entry. + (prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30, + PREGRP31 and PREGRP32. + (float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb. + Use "fisttpll" in entry 1 in opcode 0xdd. + Use "fisttp" in entry 1 in opcode 0xdf. + +2003-06-19 Christian Groessler + + * z8k-dis.c (instr_data_s): Change tabl_index from long to int. + (print_insn_z8k): Correctly check return value from + z8k_lookup_instr call. + (unparse_instr): Handle CLASS_IRO case. + * z8kgen.c: Fix function definitions. Fix formatting. + (opt): Add brk opcode alias for non-simulator breakpoint. Add + missing and fix existing in/out and sin/sout opcode definitions. + (args): "@ri", "@ro" - add CLASS_IRO register usage for in/out + opcodes. + (internal): Check p->flags for non-zero before dereferencing it. + (gas): Add CLASS_IRO line. Insert new OPC_xxx lines for the added + opcodes and renumber the remaining lines repectively. + (main): Remove "-d" command line switch. + * z8k-opc.h: Regenerate with new z8kgen.c. + +2003-06-11 H.J. Lu + + * po/Make-in (DESTDIR): New. + (install-data-yes): Support $(DESTDIR). + (uninstall): Likewise. + +2003-06-11 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2003-06-10 Doug Evans + + * cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to + CGEN_INSN_RELAXED. + * fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate. + * frv-asm.c,frv-desc.c,frv-desc.h: Regenerate. + * ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate. + * iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate. + * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate. + * openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate. + * xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate. + +2003-06-10 Gary Hade + Alan Modra + + * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define. + (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New. + (powerpc_opcodes): Add "attn", "lq" and "stq". + +2003-06-10 Richard Sandiford + + * h8300-dis.c (bfd_h8_disassemble): Don't print brackets round + rts/l and rte/l register lists. + +2003-06-03 Nick Clifton + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-asm.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.h: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-06-03 Michael Snyder + and Bernd Schmidt + and Alexandre Oliva + + * disassemble.c (disassembler): Add support for h8300sx. + * h8300-dis.c: Ditto. + +2003-06-03 Nick Clifton + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-desc.c: Regenerate. + * iq2000-desc.h: Regenerate. + * iq2000-dis.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * iq2000-opc.c: Regenerate. + * iq2000-opc.h: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-05-23 Jason Eckhardt + + * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3. + (print_insn_i860): Grab 4 bits of the control register field + instead of 3. + +2003-05-18 Jason Eckhardt + + * i860-dis.c (print_insn_i860): Instruction shrd has a dual bit, + print it. + +2003-05-17 Andreas Jaeger + + * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. + (libopcodes_la_DEPENDENCIES): Add libbfd.la. + * Makefile.in: Regenerated. + +2003-05-16 Nick Clifton + + * configure.in (ALL_LINGUAS): Add Romanian translation. + * configure: Regenerate. + * po/ro.po: New file: Romanian translation. + +2003-05-12 Dhananjay Deshpande + + * disassemble.c (disassembler): Add support for h8300hn and h8300sn. + +2003-05-09 Alan Modra + + * i386-dis.c (print_insn): Test intel_syntax against (char) -1 in + case char is unsigned. + +2003-05-01 Christian Groessler + + * z8k-dis.c (z8k_lookup_instr): Optimize FETCH_DATA calls. + (unpack_instr): Fix representation of segmented addresses. + (intr_name): Added, contains names of the parameters to the EI/DI + instructions. + (unparse_instr): Fix display of EI/DI parameters. + +2003-04-22 Doug Evans + + * fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate. + * frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate. + * ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate. + * m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + * openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate. + * xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate. + +2003-04-15 Rohit Kumar Srivastava + + * h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'. + +2003-04-07 James E Wilson + + * ia64-ic.tbl (fr-readers): Add mem-writers-fp. + * ia64-asmtab.c: Regenerate. + +2003-04-08 Alexandre Oliva + + * mips-dis.c (mips_gpr_names_newabi): Reverted previous patch. + +2003-04-07 Alexandre Oliva + + * mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7. + +2003-04-04 Svein E. Seldal + + * tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and + s/c3x/tic3x/ + +2003-04-01 Nick Clifton + + * arm-dis.c: Remove presence of (r) and (tm) symbols. + * arm-opc.h: Remove presence of (r) and (tm) symbols. + +2003-03-25 Stan Cox + Nick Clifton + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm-dis.c (regnames): Add iWMMXt register names. + (set_iwmmxt_regnames): New function. + (print_insn_arm): Handle iWMMXt formatters. + * arm-opc.h: Document iWMMXt formatters. + (arm_opcod): Add iWMMXt instructions. + +2003-03-22 Doug Evans + + * i386-dis.c (dis386): Recognize icebp (0xf1). + +2003-03-21 Martin Schwidefsky + + * s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to + S390_OPCODE_ZARCH. + (print_insn_s390): Use new modes field of s390_opcodes. + * s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove. + (s390_opcode_mode_val, s390_opcode_cpu_val): New enums. + (struct op_struct): Remove archbits. Add mode_bits and min_cpu. + (insertOpcode): Replace archbits by min_cpu and mode_bits. + (dumpTable): Write mode_bits and min_cpu instead of archbits. + (main): Adapt to new format in s390-opcode.txt. + * s390-opc.c (s390_opformats): Replace archbits by min_cpu and + mode_bits. + * s390-opc.txt: Replace archbits by min_cpu and mode_bits. + +2003-03-17 Nick Clifton + + * ppc-opc.c: Fix formatting. Update copyright date. + +2003-03-14 Daniel Jacobowitz + + * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403. + +2003-02-25 Alan Modra + + * hppa-dis.c: Formatting. + +2003-02-25 Matthew Wilcox + + * hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers. + + * hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print + the space register when the value is zero. + +2003-02-23 Elias Athanasopoulos + + * mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned, + use ARRAY_SIZE in loops. + +2003-02-12 Dave Brolley + + * fr30-desc.c: Regenerate. + +2003-02-06 Gwenole Beauchesne + + * i386-dis.c (dq_mode, Edq): Define. + (dis386_twobyte): Correct movd operands. + (OP_E): Handle dq_mode case. + +2003-01-29 Henric Jungheim + + * sparc-dis.c (print_insn_sparc): When examining values added in + to rs1, make sure that there are previous instructions. + +2003-01-23 Nick Clifton + + * Add sh2e support: + + 2002-04-02 Alexandre Oliva + + * sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e. + * sh-opc.h (arch_sh2e, arch_sh2e_up): New. + (arch_sh2_up): Added sh2e. + (sh_table): Replaced all occurrences of arch_sh3e_up with + arch_sh2e_up, except in fsqrt. + +2003-01-23 Alan Modra + + * sh64-dis.c: Include elf32-sh64.h. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2003-01-17 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap + PAL entry points. + +2003-01-16 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2003-01-08 Klee Dienes + + * Makefile.am (ALL_MACHINES): Add msp430-dis.lo. + * Makefile.in: Regenerate. + +2003-01-08 Alan Modra + + * ppc-opc.c (powerpc_macros ): Accept a shift of 32. + +2002-01-02 Ben Elliston + Jeff Johnston + + * iq2000-asm.c: New file. + * iq2000-desc.c: Likewise. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * iq2000-opc.c: Likewise. + * iq2000-opc.h: Likewise. + * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. + (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c. + (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, + iq2000-ibld.lo, iq2000-opc.lo. + (CLEANFILES): Add stamp-iq2000. + (IQ2000_DEPS): New macro. + (stamp-iq2000): New target. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_iq2000_arch. + * configure: Regenerate. + +2003-01-02 Chris Demetriou + + * mips-dis.c (print_insn_args): Use position extracted by "+A" + to calculate size for "+B". Redo code for "+C" so it shares + the same style as "+A" and "+B" now do. + +2003-01-02 Chris Demetriou + + * mips-dis.c: Update copyright years. + (print_insn_arg): Rename to... + (print_insn_args): This, returning void. Process the whole + string of args rather than a single one. Reindent. + (print_insn_mips): Update to match the above. + +2002-12-31 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Move "di" into the + right order alphabetically, and make all hex constants use + lower-case letters. + +2002-12-31 Chris Demetriou + + * mips-dis.c (mips_cp0sel_name): New structure. + (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2) + (mips_cp0sel_names_sb1): New arrays. + (mips_arch_choice): New structure members "cp0sel_names" and + "cp0sel_names_len". + (mips_arch_choices): Add references to new cp0sel_names arrays + as appropriate, and make all existing entries reference + appropriate mips_XXX_names_numeric arrays rather than simply + using NULL. + (mips_cp0sel_names, mips_cp0sel_names_len): New variables. + (lookup_mips_cp0sel_name): New function. + (set_default_mips_dis_options): Set mips_cp0sel_names and + mips_cp0sel_names_len as appropriate. Remove now-unnecessary + checks for NULL register name arrays. + (parse_mips_dis_option): Likewise. + (print_insn_arg): Handle "+D" operand type. + * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants + of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register + names symbolically. + +2002-12-30 Chris Demetriou + + * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) + (mips_hwr_names_mips3264r2): New arrays. + (mips_arch_choice): New "hwr_names" member. + (mips_arch_choices): Adjust for structure change, and add a new + entry for "mips32r2" ISA. + (mips_hwr_names): New variable. + (set_default_mips_dis_options): Set mips_hwr_names. + (parse_mips_dis_option): New "hwr-names" option which sets + mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. + (print_insn_arg): Change return type to "int" + and use that to indicate number of characters consumed. + Add support for "+" operand extension character, "+A", "+B", + "+C", and "K" operands. + (print_insn_mips): Adjust for changes to print_insn_arg. + (print_mips_disassembler_options): Adjust for "hwr-names" + addition and "reg-names" change. + * mips-opc (I33): New define (shorthand for INSN_ISA32R2). + (mips_builtin_opcodes): Note that "nop" and "ssnop" are special + forms of "sll". Add new MIPS32 Release 2 instructions: ehb, + di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, + rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. + Note that hardware rotate instructions (ror, rorv) can be + used on MIPS32 Release 2, and add the official mnemonics + for them (rotr, rotrv) and the similar "rotl" mnemonic for + left-rotate. + +2002-12-30 Dmitry Diky + + * configure.in: Add msp430 target. + * configure: Regenerate. + * disassemble.c: Add entry for msp430 disassembly. + * msp430-dis.c: New file: msp430 disassembler. + +2002-12-27 Chris Demetriou + + * disassemble.c (disassembler_usage): Add invocation of + print_mips_disassembler_options. + * mips-dis.c: Include libiberty.h. + (print_mips_disassembler_options, set_default_mips_dis_options) + (parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name) + (choose_arch_by_name, choose_arch_by_number): New functions. + (mips_abi_choice, mips_arch_choice): New structures. + (mips32_reg_names, mips64_reg_names, reg_names): Remove. + (mips_gpr_names_numeric, mips_gpr_names_oldabi) + (mips_gpr_names_newabi, mips_fpr_names_numeric) + (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64) + (mips_cp0_names_numeric, mips_cp0_names_mips3264) + (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices) + (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names) + (mips_cp0_names): New variables. + (print_insn_args): Use new variables to print GPR, FPR, and CP0 + register names. + (mips_isa_type): Remove. + (print_insn_mips): Remove ISA and CPU setup since it is now done... + (_print_insn_mips): Here. Remove register setup code, and + call set_default_mips_dis_options and parse_mips_dis_options + instead. + (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names. + +2002-12-23 Alan Modra + + * Makefile.in: Regenerate. + +2002-12-19 Nick Kelsey + + * cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character + check to fix false keyword trigger with names such as _foo. + +2002-12-19 Doug Evans + + * Makefile.am (CGEN_CPUS): New variable. + (run-cgen-all): New rule. + * Makefile.in: Regenerate. + +2002-12-18 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two + "dror" entries, and reorder the remaining "dror" and "ror" entries. + +2002-12-16 DJ Delorie + + * xstormy16-asm.c (parse_immediate16): Add prototype. + +2002-12-16 Andrew MacLeod + + * xstormy16-asm.c: Regenerate. + +2002-12-16 Alan Modra + + * ns32k-dis.c (print_insn_ns32k): Constify "d", remove register + keyword. + +2002-12-13 Alan Modra + + * h8500-opc.h (h8500_table): Add missing initializers to quiet + warnings. + * pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change. + * pj-opc.c (pj_opc_info): Add braces around union initializer. + * z8kgen.c: Include "libiberty.h". + (opt, args, toks): Fix initializer warnings. + (chewname): Make "name" a char **. Return mnemonic trimmed of + operands. + (gas): Improve emitted "DO NOT EDIT" warning. Format emitted + opcode_entry_type, and make "nicename" and "name" const. Make + z8k_table const too. Formatting. Generate idx as gas needs it. + * z8k-opc.h: Regenerate. + +2002-12-08 Stephane Carrez + + * m68hc11-dis.c (print_indexed_operand): Fix PC-relative address + for 9 and 16-bit PC-relative addressing mode. + +2002-12-05 Aldy Hernandez + + * ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub, + evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq, + evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi, + evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa, + evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, + evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, + evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, + evmwhgsmian, evmwhgumian. + (mftb): Add to opcode table. + (mtspefscr): Change RT to RS in opcode table. + +2002-12-05 Aldy Hernandez + + * ppc-opc.c: Move mbar and msync up. Change mask for mbar and + msync. + +2002-12-04 David Mosberger + + * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. + * ia64-opc-b.c: Add "hint.b" instruction. + * ia64-opc-f.c: Add "hint.f" instruction. + * ia64-opc-i.c: Add "hint.i" instruction. + * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and + "cmp8xchg16" instructions. + * ia64-opc-x.c: Add "hint.x" instruction. + + * ia64-opc.h (AR_CSD): New macro. + + * ia64-ic.tbl: Update according to SDM2.1. + * ia64-raw.tbl: Ditto. + * ia64-waw.tbl: Ditto. + + * ia64-gen.c (in_iclass): Handle "hint" like "nop". + (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], + AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. + * ia64-asmtab.c: Regenerate. + +2002-11-25 Aldy Hernandez + + * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa, + evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw. + +2002-12-04 Aldy Hernandez + + * ppc-opc.c (PMRN): Remove. + (RA): Set to NB + 1. + (powerpc_opcodes): Change PMRN to SPR. + Change all RD to RS. + Change mftb to look like mftbl. + Move mftb before mftbl. + Add mfbbtar. + Add mtbbtar. + Change mfpmr to use PMR. + Change mtpmr to use PMR. + (RD): Remove. + (insert_ev2): Fix mask and shift. + (extract_ev2): Same. + (insert_ev4): Same. + (extract_ev4): Same. + (PMR): Define. + (extract_pmrn): Remove. + (insert_pmrn): Remove. + +2002-12-03 Richard Henderson + + * ia64-opc-m.c: Add ld8.mov. + * ia64-asmtab.c: Regenerate. + +2002-12-02 Alan Modra + + * arm-dis.c (print_insn_arm): Constify "insn". Formatting. + (print_insn_thumb): Likewise. + * h8500-dis.c (print_insn_h8500): Constify "opcode". + * mcore-dis.c (print_insn_mcore): Constify "op". Formatting. + * ns32k-dis.c (print_insn_arg ): Use a union to avoid + type-punned pointer warnings. + : Likewise. Fix error message too. + * pdp11-dis.c (print_reg): Warning fix. + * sh-dis.c (print_movxy): Constify "op" param. + (print_insn_ddt): Constify sh_opcode_info vars. + (print_insn_ppi): Likewise. + (print_insn_sh): Likewise. + * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid + type-punned pointer warnings. + * w65-dis.c (print_insn_w65): Constify "op". + +2002-12-01 Stephane Carrez + + * m68hc11-dis.c (PC_REGNUM): Define. + (print_indexed_operand): Need an adjustment for some PC-relative + operand modes; print the final address of PC-relative modes. + (print_insn): Take into account movw/movb to adjust the PC-relative + operand addresses. + +2002-11-30 Alan Modra + + *arm-dis.c, cris-dis.c, h8300-dis.c, mips-dis.c, mmix-dis.c, sh-dis.c, + sh64-dis.c, v850-dis.c: Replace boolean with bfd_boolean, true with + TRUE, false with FALSE. Simplify comparisons of bfd_boolean vars + with TRUE/FALSE. Formatting. + +2002-11-25 DJ Delorie + + * xstormy16-opc.c: Regenerate. + +2002-11-25 Jim Wilson + + * ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64. + +2002-11-15 DJ Delorie + + * xstormy16-desc.c: Regenerate. + * xstormy16-opc.c: Regenerate. + * xstormy16-opc.h: Regenerate. + +2002-11-18 Klee Dienes + + * avr-dis.c: Include libiberty.h (for xmalloc). + (struct avr_opcodes_s): Remove 'bin_mask' field (it's + automatically computed in the init routine). + (AVR_INSN): No longer provide bin_mask field in initializer. + (avr_opcodes_s): Declare as const. + (print_insn_avr): Store the bin_mask field in a separate table + (allocated with xmalloc); iterate through it at the same time as + we iterate through the opcodes. + +2002-11-18 Klee Dienes + + * h8300-dis.c: Include libiberty.h (for xmalloc). + (struct h8_instruction): New type, used to wrap h8_opcodes with a + length field (computed at run-time). + (h8_instructions): New variable. + (bfd_h8_disassemble_init): Allocate the storage for + h8_instructions. Fill h8_instructions with pointers to the + appropriate opcode and the correct value for the length field. + (bfd_h8_disassemble): Iterate through h8_instructions instead of + h8_opcodes. + +2002-11-18 Klee Dienes + + * arc-opc.c (arc_ext_opcodes): Define. + (arc_ext_operands): Define. + * i386-dis.c (Suffix3DNow): Declare as const. + * arm-opc.h (arm_opcodes): Declare as const. + (thumb_opcodes): Declare as const. + * h8500-opc.h (h8500_table): Declare as const. + (h8500_table): Use a NULL for the opcode in the terminator, so + that code testing (opcode->name) behaves correctly. + * mcore-opc.h (mcore_table): Declare as const. + * sh-opc.h (sh_table): Declare as const. + * w65-opc.h (optable): Declare as const. + * z8k-opc.h (z8k_table): Declare as const. + +2002-11-18 Svein E. Seldal + + * tic4x-dis.c: Added support for enhanced and special insn. + (c4x_print_op): Added insn class 'i' and 'j' + (c4x_hash_opcode_special): Add to support special insn + (c4x_hash_opcode): Update to support the new opcode-list + format. Add support for the new special insns. + (c4x_disassemble): New opcode-list support. + +2002-11-16 Klee Dienes + + * m88k-dis.c: Include libiberty.h (for xmalloc). + (HASHTAB): New type, used to build instruction hash tables. + Contains a pointer to an INSTAB and a pointer to the next hash + chain entry. + (instructions): Move definition from m88k.h; remove initialization + of 'next' field. + (hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB. + (printop): Mark pointer to OPSPEC as const. + (install): Remove; fold into init_disasm. + (m88kdis): Update to ihashtab_initialized to 1 after calling + init_disasm. entry_ptr now iterates through HASHTABs, not + INSTABs. + (init_disasm): Iterate through the instructions and add to + hashtable[]. + +2002-11-16 Svein E. Seldal + + * tic4x-dis.c: (c4x_print_op): Add support for the new argument + format. Fix bug in 'N' register printer. + +2002-11-12 Segher Boessenkool + + * ppc-dis.c (print_insn_powerpc): Correct condition register display. + +2002-11-07 Aldy Hernandez + + * ppc-opc.c (EVUIMM_4): Change bit size to 32. + (EVUIMM_2): Same. + (EVUIMM_8): Same. + +2002-11-07 Klee Dienes + + * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' + argument to ia64-gen. + Regenerate dependencies for ia64-len.lo. + * Makefile.in: Regenerate. + * ia64-gen.c: Convert to use getopt(). Add the standard GNU + options, as well as '--srcdir', which controls the directory in + which ia64-gen looks for the sources it uses to generate the + output table. Add a 'const' to the declaration of the final + output table. Call xmalloc_set_program_name to set the program + name. + * ia64-asmtab.c: Regenerate. + +2002-11-07 Nick Clifton + + * ia64-gen.c: Fix comment formatting and compile time warnings. + * ia64-opc-a.c: Fix compile time warnings. + * ia64-opc-b.c: Likewise. + * ia64-opc-d.c: Likewise. + * ia64-opc-f.c: Likewise. + * ia64-opc-i.c: Likewise. + * ia64-opc-m.c: Likewise. + * ia64-opc-x.c: Likewise. + +2002-11-06 Aldy Hernandez + + * ppc-opc.c: Change RD to RS for evmerge*. + +2002-10-07 Nathan Tallent + + * sparc-opc.c (sparc_opcodes) : Add conditional/unconditional branch + classification. + +2002-10-13 Stephane Carrez + + * m68hc11-dis.c (print_insn): Treat bitmask and branch operands + at the end. + +2002-09-30 Gavin Romig-Koch + Ken Raeburn + Aldy Hernandez + Eric Christopher + Richard Sandiford + + * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. + (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 + and bfd_mach_mips5500. + * mips-opc.c (V1): Include INSN_4111 and INSN_4120. + (N411, N412, N5, N54, N55): New convenience defines. + (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. + Change dmadd16 and madd16 from V1 to N411. + +2002-09-26 Thiemo Seufer + + * mips-dis.c (print_insn_mips): Always allow disassembly of + 32-bit jalx opcode. + +2002-09-24 Nick Clifton + + * po/de.po: Updated German translation. + +2002-09-21 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-09-20 Nick Clifton + + * ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr + register names are accepted. + +2002-09-17 Svein E. Seldal + + * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED. + Convert functions to K&R format. + +2002-09-13 Nick Clifton + + * ppc-opc.c (MFDEC2): Include Book-E. + (PPCCHLK64): New opcode mask. + (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid, + mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl, + mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1, + mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr, + mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5, + mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11, + mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0, + mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear, + mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7, + mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3, + mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0, + mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7, + mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13, + mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New + Book-E instructions. + (evfsneg): Fix opcode value. + (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64 + mask. + (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit + Book-E. + (extsw): Restrict to 64-bit PPC instruction sets. + (extsw.): Does not exist in 64-bit Book-E. + (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as + they are no longer needed. + +2002-09-12 Gary Hade + + * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC. + +2002-09-11 Nick Clifton + + * po/da.po: Updated Danish translation file. + +2002-09-04 Nick Clifton + + * ppc-opc.c (extsw, extsw.): Do not allow for the BookE32. + +2002-09-04 Nick Clifton + + * disassemble.c (disassembler_usage): Add invocation of + print_ppc_disassembler_options. + * ppc-dis.c (print_ppc_disassembler_options): New function. + +2002-09-04 Nick Clifton + + * ppc-opc.c: The BookE implementations of the TLBWE and TLBRE + instructions do not take any arguments. + +2002-09-02 Nick Clifton + + * v850-opc.c: Remove redundant references to V850EA architecture. + +2002-09-02 Alan Modra + + * arc-opc.c: Include bfd.h. + (arc_get_opcode_mach): Subtract off base bfd_mach value. + +2002-08-30 Alan Modra + + * v850-dis.c (disassemble): Remove bfd_mach_v850ea case. + + * mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants. + +2002-08-28 Svein E. Seldal + + * configure.in: Added bfd_tic4x_arch. + * configure: Regenerate. + * Makefile.am: Added tic4x-dis.o target. + * Makefile.in: Regenerate. + +2002-08-28 Michael Hayes + + * disassemble.c: Added tic4x target and c4x + disassembler routine. + * tic4x-dis.c: New file. + +2002-08-16 Christian Groessler + + * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex + values as those. + * z8kgen.c (opt): Fix definition of "in rd,imm16" opcode. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-08-19 Elena Zannoni + + From matthew green + + * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and + `-mefs'. Turn off AltiVec for E500 and efs. + (print_insn_powerpc): Don't print an AltiVec instruction if the + dialect is not efs. + + * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, + insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions + for extracting pmrn/evld/evstd/etc operands. + (CRB, CRFD, CRFS, DC, RD): New instruction fields. + (CT): Make this equal to RD + 1. + (PMRN): New operand. + (RA): Update. + (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. + (WS): Update. + (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. + (ISEL, ISEL_MASK): New instruction form and mask for ISEL. + (XISEL, XISEL_MASK): New instruction form and mask for ISEL. + (CTX, CTX_MASK): New instruction form and mask for context cache + instructions. + (UCTX, UCTX_MASK): New instruction form and mask for user context + cache instructions. + (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. + (CLASSIC): New define. + (PPCESPE): New define. + (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New + defines for integer select, cache control, branch + locking, power management, cache locking and machine check + APU instructions, respectively. + (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, + efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, + efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, + efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, + evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, + evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, + evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, + evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, + evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, + evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, + evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, + evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, + evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, + evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, + evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, + evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, + evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, + evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, + evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, + evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, + evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, + evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, + evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, + evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, + evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, + evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, + evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, + evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, + evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, + evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, + evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, + evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, + evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, + evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, + evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, + evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, + evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, + evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, + evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, + evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, + evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, + evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, + evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, + evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, + evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, + evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex + instructions. + (rfmci): New machine check APU instruction. + (isel): New integer select APU instructino. + (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, + dcbtstlse, dcblc, dcblce): New cache control APU instructions. + (mtspefscr, mfspefscr): New instructions. + (mfpmr, mtpmr): New performance monitor APU instructions. + (savecontext): New context cache APU instructions. + (bblels, bbelr): New branch locking APU instructions. + (bblels, bbelr): New instructions. + (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias. + +2002-08-13 Stephane Carrez + + * m68hc11-opc.c: Update call operand to accept the page definition. + Identify instructions that are branches and calls to generate a + RL_JUMP relocation. + +2002-08-13 Stephane Carrez + + * m68hc11-dis.c (print_insn): Take into account 68HC12 memory + banks and fix disassembling of call instruction. + (print_indexed_operand): New param to tell whether + it was an indirect addressing operand (for disassembling call). + +2002-08-09 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2002-08-08 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as + aliases to "daddiu" and "addiu". + +2002-07-30 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2002-07-25 Nick Clifton + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + * po/tr.po: Updated Turkish translation. + * po/fr.po: Updated French translation. + +2002-07-24 Nick Clifton + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + +2002-07-23 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-07-23 Nick Clifton + + * po/fr.po: Updated French translation. + * po/pr_BR.po: New Brazilian Portuguese translation. + * po/id.po: Updated Indonesian translation. + * configure.in (LINGUAS): Add pr_BR. + * configure: Regenerate. + +2002-07-18 Denis Chertykov + Frank Ch. Eigler + Alan Lehotsky + matthew green + + * configure.in: Add support for ip2k. + * configure: Regenerate. + * Makefile.am: Add support for ip2k. + * Makefile.in: Regenerate. + * disassemble.c: Add support for ip2k. + * ip2k-asm.c: New generated file. + * ip2k-desc.c: New generated file. + * ip2k-desc.h: New generated file. + * ip2k-dis.c: New generated file. + * ip2k-ibld.c: New generated file. + * ip2k-opc.c: New generated file. + * ip2k-opc.h: New generated file. + +2002-07-17 David Mosberger + + * ia64-opc-b.c (bWhc): New macro. + (mWhc): Ditto. + (OpPaWhcD): Ditto. + (ia64_opcodes_b): Correct patterns for indirect call + instructions to use 3-bit "wh" field. + * ia64-asmtab.c: Regnerate. + +2002-07-09 Thiemo Seufer + + * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. + * mips-opc.c (I16): New define. + (mips_builtin_opcodes): Make jalx an I16 insn. + +2002-06-18 Dave Brolley + + * po/POTFILES.in: Add frv-*.[ch]. + * disassemble.c (ARCH_frv): New macro. + (disassembler): Handle bfd_arch_frv. + * configure.in: Support frv_bfd_arch. + * Makefile.am (HFILES): Add frv-*.h. + (CFILES): Add frv-*.c + (ALL_MACHINES): Add frv-*.lo. + (CLEANFILES): Add stamp-frv. + (FRV_DEPS): New variable. + (stamp-frv): New target. + (frv-asm.lo): New target. + (frv-desc.lo): New target. + (frv-dis.lo): New target. + (frv-ibld.lo): New target. + (frv-opc.lo): New target. + (frv-*.[ch]): New files. + +2002-06-18 Ben Elliston + + * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. + * Makefile.in: Regenerate. + +2002-06-08 Alan Modra + + * a29k-dis.c: Replace CONST with const. + * h8300-dis.c: Likewise. + * m68k-dis.c: Likewise. + * or32-dis.c: Likewise. + * sparc-dis.c: Likewise. + +2002-06-04 Jason Thorpe + + * configure.in: Add "sh5*-*" to list of targets which include + sh64 support. + * configure: Regenerate. + +2002-05-31 Chris G. Demetriou + + * mips-opc.c: Clean up a few whitespace issues, and sort a + few entries understanding that 'x' follows 'w' in the alphabet. + +2002-05-31 Chris G. Demetriou + Ed Satterthwaite + + * mips-opc.c: Add support for SB-1 MDMX subset and extensions. + +2002-05-31 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-05-30 Chris G. Demetriou + Ed Satterthwaite + + * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', + and 'Z' formats, for MDMX. + (mips_isa_type): Add MDMX instructions to the ISA + bit mask for bfd_mach_mipsisa64. + * mips-opc.c: Add support for MDMX instructions. + (MX): New definition. + + * mips-dis.c: Update copyright years to include 2002. + +2002-05-30 Diego Novillo + + * d10v-opc.c (d10v_opcodes): `btsti' does not modify its + arguments. + +2002-05-28 Kuang Hwa Lin + + * configure.in: Add DLX configuraton support. + * configure: Regenerate. + * Makefile.am: Add DLX configuraton support. + * Makefile.in: Regenerate. + * disassemble.c: Add DLX support. + * dlx-dis.c: New file. + +2002-05-25 Alan Modra + + * Makefile.am (sh-dis.lo): Don't put make commands in deps. + * Makefile.in: Regenerate. + * arc-dis.c: Use #include "" instead of <> for local header files. + * m68k-dis.c: Likewise. + +2002-05-22 J"orn Rennecke + + * Makefile.am (sh-dis.lo): Compile with @archdefs@. + * Makefile.in: regenerate. + + * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 + for disassembly. + +2002-05-22 Thiemo Seufer + + * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. + +2002-05-17 J"orn Rennecke + + * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. + * sh-dis.c (LITTLE_BIT): Delete. + (print_insn_sh, print_insn_shl): Deleted. + (print_insn_shx): Renamed to + (print_insn_sh). No longer static. Handle SHmedia instructions. + Use info->endian to determine endianness. + * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. + (print_insn_sh64x): No longer static. Renamed to + (print_insn_sh64). Removed pfun_compact and endian arguments. + If we got an uneven address to indicate SHmedia, adjust it. + Return -2 for SHcompact instructions. + +2002-05-17 Alan Modra + + * acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. + * configure.in: Invoke AM_INSTALL_LIBBFD. + * Makefile.am (install-data-local): Move to.. + (install_libopcodes): .. New target. + (uninstall_libopcodes): Likewise. + (install-bfdlibLTLIBRARIES): Likewise. + (uninstall-bfdlibLTLIBRARIES): Likewise. + (bfdlibdir): New. + (bfdincludedir): New. + (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * Makefile.in: Regenerate. + +2002-05-15 Nick Clifton + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Regenerate. + * xstormy16-dis.c: Regenerate. + +2002-05-15 Thiemo Seufer + + * mips-dis.c (is_newabi): EABI is not a NewABI. + +2002-05-13 Jason Thorpe + + * configure.in (shle-*-*elf*): Include sh64 support. + * configure: Regenerate. + +2002-04-28 Jason Thorpe + + * vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode. + (print_insn_mode): Print some basic info about floating point values. + +2002-05-09 Anton Blanchard + + * ppc-opc.c: Add "tlbiel" for POWER4. + +2002-05-07 Graydon Hoare + + * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather + than just most-recently-opened. + +2002-05-01 Alan Modra + + * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. + +2002-04-24 Christian Groessler + + * z8k-dis.c (print_insn_z8k): Set disassemble_info to 2 + bytes_per_chunk, 6 bytes_per_line for nicer display of the hex + codes. + (z8k_lookup_instr): CLASS_IGNORE case added. + (output_instr): Don't print hex codes, they are already + printed. + (unpack_instr): ARG_NIM4 case added. ARG_NIM8 case + fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases. + (unparse_instr): Fix base and indexed addressing disassembly: + The index is inside the brackets. + * z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines. + (opt): Fix shift left/right arithmetic/logical byte defines: + The high byte of the immediate word is ignored by the + processor. + Fix n parameter of ldm opcodes: The opcode contains (n-1). + (args): Fix "n" entry. + (toks): Add "nim4" and "iiii" entries. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-04-24 Nick Clifton + + * po/id.po: New Indonesian translation. + * configure.in (ALL_LIGUAS): Add id.po + * configure: Regenerate. + +2002-04-17 matthew green + + * ppc-opc.c (powerpc_opcode): Fix dssall operand list. + +2002-04-04 Alan Modra + + * dep-in.sed: Cope with absolute paths. + * Makefile.am (dep.sed): Subst TOPDIR. + Run "make dep-am". + * Makefile.in: Regenerate. + * ppc-opc.c: Whitespace. + * s390-dis.c: Fix copyright date. + +2002-03-23 matthew green + + * ppc-opc.c (vmaddfp): Fix operand order. + +2002-03-21 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2002-03-21 Anton Blanchard + + * ppc-opc.c: Add optional field to mtmsrd. + (MTMSRD_L, XRLARB_MASK): Define. + +2002-03-18 Jan Hubicka + + * i386-dis.c (prefix_name): Fix handling of 32bit address prefix + in 64bit mode. + (print_insn) Likewise. + (putop): Fix handling of 'E' + (OP_E, OP_OFF): handle 32bit addressing mode in 64bit. + (ptr_reg): Likewise. + +2002-03-18 Nick Clifton + + * po/fr.po: Updated version. + +2002-03-16 Chris Demetriou + + * mips-opc.c (M3D): Tweak comment. + (mips_builtin_op): Add comment indicating that opcodes of the + same name must be placed together in the table, and sort + the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", + "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. + +2002-03-16 Nick Clifton + + * Makefile.am: Tidy up sh64 rules. + * Makefile.in: Regenerate. + +2002-03-15 Chris G. Demetriou + + * mips-dis.c: Update copyright years. + +2002-03-15 Chris G. Demetriou + + * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA + bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add + comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that + indicate that they should dissassemble all applicable + MIPS-specified ASEs. + * mips-opc.c: Add support for MIPS-3D instructions. + (M3D): New definition. + + * mips-opc.c: Update copyright years. + +2002-03-15 Chris G. Demetriou + + * mips-opc.c (mips_builtin_opcodes): Sort bc opcodes by name. + +2002-03-15 Chris Demetriou + + * mips-dis.c (is_newabi): Fix ABI decoding. + +2002-03-14 Chris G. Demetriou + + * mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 + and bfd_mach_mipsisa64 cases to match the rest. + +2002-03-13 Nick Clifton + + * po/fr.po: Updated version. + +2002-03-13 Alan Modra + + * ppc-opc.c: Add optional `L' field to tlbie. + (XRTLRA_MASK): Define. + +2002-03-06 Chris Demetriou + + * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being + present on I4. + + * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". + +2002-03-05 Paul Koning + + * pdp11-opc.c: Fix "mark" operand type. Fix operand types + for float opcodes that take float operands. Add alternate + names (xxxD vs. xxxF) for float opcodes. + * pdp11-dis.c (print_operand): Clean up formatting for mode 67. + (print_foperand): New function to handle float opcode operands. + (print_insn_pdp11): Use print_foperand to disassemble float ops. + +2002-02-27 Nick Clifton + + * po/de.po: Updated. + +2002-02-26 Brian Gaeke + + * Makefile.am (install-data-local): Install dis-asm.h. + +2002-02-26 Nick Clifton + + * configure.in (LINGUAS): Add de.po. + * configure: Regenerate. + * po/de.po: New file. + +2002-02-25 Alan Modra + + * ppc-dis.c (powerpc_dialect): Handle power4 option. + * ppc-opc.c (insert_bdm): Correct description of "at" branch + hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour. + (extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise. + (BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise. + (PPCCOM32, PPCCOM64): Delete. + (NOPOWER4, POWER4): Define. + (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4, + and PPCCOM4 with POWER4 so that "at" style branch hint opcodes + are enabled for power4 rather than ppc64. + +2002-02-20 Tom Rix + + * ppc-opc.c (powerpc_operands): Add WS field. Use for tlbre, tlbwe. + +2002-02-19 Martin Schwidefsky + + * s390-dis.c (init_disasm): Use renamed architecture defines. + +2002-02-19 matthew green + + * ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola + specific. + +2002-02-18 Nick Clifton + + * po/tr.po: Updated translation. + +2002-02-15 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo + disassembly mask. + +2002-02-15 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Add simple pseudos for + lda, ldah, jmp, ret. + +2002-02-14 Nick Clifton + + * po/da.po: Updated translation. + +2002-02-12 Graydon Hoare + + * cgen-asm.in (parse_insn_normal): Change call from + @arch@_cgen_parse_operand to cd->parse_operand, to + facilitate CGEN_ASM_INIT_HOOK doing useful work. + +2002-02-11 Alexandre Oliva + + * sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not + sign-extended. + +2002-02-11 Alan Modra + + * Makefile.am: "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + +2002-02-10 Hans-Peter Nilsson + + * configure.in : For sh-* and shl-*, enable sh64 + support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and + shl-*-linux*. + * configure: Regenerate. + +2002-02-10 Daniel Jacobowitz + + * cgen-dis.c: Add prototypes for count_decodable_bits + and add_insn_to_hash_chain. + +2002-02-08 Alexandre Oliva + + * configure.in : Enable sh64 support on sh-*. + * configure: Rebuilt. + +2002-02-08 Ivan Guzvinec + + * or32-opc.c: Fix compile time warning messages. + * or32-dis.c: Fix compile time warning messages. + +2002-02-08 Alexandre Oliva + + Contribute sh64-elf. + 2001-10-08 Nick Clifton + * sh64-opc.c: Regenerate. + 2001-03-13 DJ Delorie + * sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its + purpose is more obvious. + * sh64-opc.c (shmedia_table): Ditto. + * sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto. + (print_insn_shmedia): Ditto. + 2001-03-12 DJ Delorie + * sh64-opc.c: Adjust comments to reflect reality: replace bits + 3:0 with zeros (not "reserved"), replace "rrrrrr" with + "gggggg" for two-operand floating point opcodes. Remove + "fsina". + 2001-01-08 Hans-Peter Nilsson + * sh64-dis.c (print_insn_shmedia) : + Correct printing of .byte:s. Return number of printed bytes or + -1; never 0. + (print_insn_sh64x) : Ditto. Print as .byte:s + to next four-byte-alignment if insn or data is not aligned. + 2001-01-06 Hans-Peter Nilsson + * sh64-dis.c: Update comments and fix comment formatting. + (initialize_shmedia_opcode_mask_table) : + Abort instead of setting length to 0. + (crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb, + crange_bsearch_cmpl, sh64_get_contents_type, + sh64_address_in_cranges): Move to bfd/elf32-sh64.c. + 2001-01-05 Hans-Peter Nilsson + * sh64-opc.c: Remove #if 0:d entries for instructions not found in + SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo. + 2000-12-30 Hans-Peter Nilsson + * sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed + address with same prefix as SHcompact. + In the disassembler, use a .cranges section for linked executables. + * sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file + and update for using structure in info->private_data. + (struct sh64_disassemble_info): New. + (is_shmedia_p): Delete. + (crange_qsort_cmpb): New function. + (crange_qsort_cmpl, crange_bsearch_cmpb): New functions. + (crange_bsearch_cmpl, sh64_address_in_cranges): New functions. + (init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions. + (sh64_get_contents_type, sh64_address_is_shmedia): New functions. + (print_insn_shmedia): Correct displaying of address after MOVI/SHORI + pair. Display addresses for linked executables only. + (print_insn_sh64x_media): Initialize info->private_data by calling + init_sh64_disasm_info. + (print_insn_sh64x): Ditto. Find out type of contents by calling + sh64_contents_type_disasm. Display data regions using ".long" and + ".byte" similar to unrecognized opcodes. + 2000-12-19 Hans-Peter Nilsson + * sh64-dis.c (is_shmedia_p): Check info->section and look for ISA + information in section flags before considering symbols. Don't + assume an info->mach setting of bfd_mach_sh5 means SHmedia code. + * configure.in (bfd_sh_arch): Check presence of sh64 insns by + matching $target $canon_targets instead of looking at the + now-removed -DINCLUDE_SHMEDIA in $targ_cflags. + * configure: Regenerate. + 2000-11-25 Hans-Peter Nilsson + * sh64-opc.c (shmedia_creg_table): New. + * sh64-opc.h (shmedia_creg_info): New type. + (shmedia_creg_table): Declare. + * sh64-dis.c (creg_name): New function. + (print_insn_shmedia): Use it. + * disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map + bfd_mach_sh5 to print_insn_sh64 if big-endian and to + print_insn_sh64l if little-endian. + * sh64-dis.c (print_insn_shmedia): Make r unsigned. + (print_insn_sh64l): New. + (print_insn_sh64x): New. + (print_insn_sh64x_media): New. + (print_insn_sh64): Break out code to print_insn_sh64x and + print_insn_sh64x_media. + 2000-11-24 Hans-Peter Nilsson + * sh64-opc.h: New file + * sh64-opc.c: New file + * sh64-dis.c: New file + * Makefile.am: Add sh64 targets. + (HFILES): Add sh64-opc.h. + (CFILES): Add sh64-opc.c and sh64-dis.c. + (ALL_MACHINES): Add sh64 files. + * Makefile.in: Regenerate. + * configure.in: Add support for sh64 to bfd_sh_arch. + * configure: Regenerate. + * disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define. + (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to + print_insn_sh64. + * sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-02-04 Frank Ch. Eigler + + * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. + +2002-02-04 Alexandre Oliva + + * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. + +2002-02-01 Alan Modra + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2002-01-31 Ivan Guzvinec + + * or32-dis.c: New file. + * or32-opc.c: New file. + * configure.in: Add support for or32. + * configure: Regenerate. + * Makefile.am: Add support for or32. + * Makefile.in: Regenerate. + * disassemble.c: Add support for or32. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-01-27 Daniel Jacobowitz + + * configure: Regenerated. + +2002-01-26 Nick Clifton + + * po/fr.po: Updated version. + +2002-01-25 Nick Clifton + + * po/es.po: Updated version. + +2002-01-24 Nick Clifton + + * po/da.po: New version. + +2002-01-23 Nick Clifton + + * po/da.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add da. + * configure: Regenerate. + +2002-01-22 Graydon Hoare + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Likewise. + * fr30-desc.h: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * fr30-opc.c: Likewise. + * fr30-opc.h: Likewise. + * m32r-asm.c: Likewise. + * m32r-desc.c: Likewise. + * m32r-desc.h: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * m32r-opc.c: Likewise. + * m32r-opc.h: Likewise. + * m32r-opinst.c: Likewise. + * openrisc-asm.c: Likewise. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + * xstormy16-desc.c: Likewise. + +2002-01-22 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Also mask the base opcode for + comparison. + +2002-01-22 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-01-19 Richard Earnshaw + + * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. + * arm-dis.c (print_insn_arm): Don't handle 'h' case. + +2002-01-18 Keith Walker + + * arm-opc.h (arm_opcodes): Add bxj instruction. + +2002-01-17 Nick Clifton + + * po/opcodes.pot: Regenerate. + * po/fr.po: Regenerate. + * po/sv.po: Regenerate. + * po/tr.po: Regenerate. + +2002-01-16 Nick Clifton + + * po/tr.po: Import new version. + +2002-01-15 Richard Earnshaw + + * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. + * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for + VFP bitfields. + +2002-01-10 matthew green + + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Likewise. + * xstormy16-desc.h: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-opc.c: Likewise. + * xstormy16-opc.h: Likewise. + +2002-01-07 Nick Clifton + + * po/es.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add es. + * configure: Regenerate. + +For older changes see ChangeLog-0001 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2004 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2004 new file mode 100644 index 000000000000..139655b213b1 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2004 @@ -0,0 +1,741 @@ +2004-12-23 Tomer Levi + + * crx-opc.c: Mark 'bcop' instruction as RELAXABLE. + +2004-12-14 Svein E. Seldal + + * avr-dis.c: Prettyprint. Added printing of symbol names in all + memory references. Convert avr_operand() to C90 formatting. + +2004-12-05 Tomer Levi + + * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing. + +2004-11-29 Tomer Levi + + * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed. + (no_op_insn): Initialize array with instructions that have no + operands. + * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping. + +2004-11-29 Richard Earnshaw + + * arm-dis.c: Correct top-level comment. + +2004-11-27 Richard Earnshaw + + * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the + architecuture defining the insn. + (arm_opcodes, thumb_opcodes): Delete. Move to ... + * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre + field. + Also include opcode/arm.h. + * Makefile.am (arm-dis.lo): Update dependency list. + * Makefile.in: Regenerate. + +2004-11-22 Ravi Ramaseshan + + * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to + reflect the change to the short immediate syntax. + +2004-11-19 Alan Modra + + * or32-opc.c (debug): Warning fix. + * po/POTFILES.in: Regenerate. + + * maxq-dis.c: Formatting. + (print_insn): Warning fix. + +2004-11-17 Daniel Jacobowitz + + * arm-dis.c (WORD_ADDRESS): Define. + (print_insn): Use it. Correct big-endian end-of-section handling. + +2004-11-08 Inderpreet Singh + Vineet Sharma + + * maxq-dis.c: New file. + * disassemble.c (ARCH_maxq): Define. + (disassembler): Add 'print_insn_maxq_little' for handling maxq + instructions.. + * configure.in: Add case for bfd_maxq_arch. + * configure: Regenerate. + * Makefile.am: Add support for maxq-dis.c + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + +2004-11-05 Tomer Levi + + * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register + mode. + * crx-dis.c: Likewise. + +2004-11-04 Hans-Peter Nilsson + + Generally, handle CRISv32. + * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case). + (struct cris_disasm_data): New type. + (format_reg, format_hex, cris_constraint, print_flags) + (get_opcode_entry): Add struct cris_disasm_data * parameter. All + callers changed. + (format_sup_reg, print_insn_crisv32_with_register_prefix) + (print_insn_crisv32_without_register_prefix) + (print_insn_crisv10_v32_with_register_prefix) + (print_insn_crisv10_v32_without_register_prefix) + (cris_parse_disassembler_options): New functions. + (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family + parameter. All callers changed. + (get_opcode_entry): Call malloc, not xmalloc. Return NULL on + failure. + (cris_constraint) : New cases. + (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes + for constraint 'n'. + (print_with_operands) : New case. + (print_with_operands) + : New cases. + (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32. + (print_insn_cris_with_register_prefix) + (print_insn_cris_without_register_prefix): Call + cris_parse_disassembler_options. + * cris-opc.c (cris_spec_regs): Mention that this table isn't used + for CRISv32 and the size of immediate operands. New v32-only + entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and + spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change + ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10. + Change brp to be v3..v10. + (cris_support_regs): New vector. + (cris_opcodes): Update head comment. New format characters '[', + ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'. + Add new opcodes for v32 and adjust existing opcodes to accommodate + differences to earlier variants. + (cris_cond15s): New vector. + +2004-11-04 Jan Beulich + + * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. + (indirEb): Remove. + (Mp): Use f_mode rather than none at all. + (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode + replaces what previously was x_mode; x_mode now means 128-bit SSE + operands. + (dis386): Make far jumps and calls have an 'l' prefix only in AT&T + mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq. + pinsrw's second operand is Edqw. + (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's + operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt, + fldenv, frstor, fsave, fstenv all should also have suffixes in Intel + mode when an operand size override is present or always suffixing. + More instructions will need to be added to this group. + (putop): Handle new macro chars 'C' (short/long suffix selector), + 'I' (Intel mode override for following macro char), and 'J' (for + adding the 'l' prefix to far branches in AT&T mode). When an + alternative was specified in the template, honor macro character when + specified for Intel mode. + (OP_E): Handle new *_mode values. Correct pointer specifications for + memory operands. Consolidate output of index register. + (OP_G): Handle new *_mode values. + (OP_I): Handle const_1_mode. + (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate + respective opcode prefix bits have been consumed. + (OP_EM, OP_EX): Provide some default handling for generating pointer + specifications. + +2004-10-28 Tomer Levi + + * crx-opc.c (REV_COP_INST): New macro, reverse operand order of + COP_INST macro. + +2004-10-27 Tomer Levi + + * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE. + (getregliststring): Support HI/LO and user registers. + * crx-opc.c (crx_instruction): Update data structure according to the + rearrangement done in CRX opcode header file. + (crx_regtab): Likewise. + (crx_optab): Likewise. + (crx_instruction): Reorder load/stor instructions, remove unsupported + formats. + support new Co-Processor instruction 'cpi'. + +2004-10-27 Nick Clifton + + * opcodes/iq2000-asm.c: Regenerate. + * opcodes/iq2000-desc.c: Regenerate. + * opcodes/iq2000-desc.h: Regenerate. + * opcodes/iq2000-dis.c: Regenerate. + * opcodes/iq2000-ibld.c: Regenerate. + * opcodes/iq2000-opc.c: Regenerate. + * opcodes/iq2000-opc.h: Regenerate. + +2004-10-21 Tomer Levi + + * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3, + us4, us5 (respectively). + Remove unsupported 'popa' instruction. + Reverse operands order in store co-processor instructions. + +2004-10-15 Alan Modra + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2004-10-12 Bob Wilson + + * xtensa-dis.c: Use ISO C90 formatting. + +2004-10-09 Alan Modra + + * ppc-opc.c: Revert 2004-09-09 change. + +2004-10-07 Bob Wilson + + * xtensa-dis.c (state_names): Delete. + (fetch_data): Use xtensa_isa_maxlength. + (print_xtensa_operand): Replace operand parameter with opcode/operand + pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions. + (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot + instruction bundles. Use xmalloc instead of malloc. + +2004-10-07 David Gibson + + * ppc-opc.c: Replace literal "0"s with NULLs in pointer + initializers. + +2004-10-07 Tomer Levi + + * crx-opc.c (crx_instruction): Support Co-processor insns. + * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments. + (getregliststring): Change function to use the above enum. + (print_arg): Handle CO-Processor insns. + (crx_cinvs): Add 'b' option to invalidate the branch-target + cache. + +2004-10-06 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs, + efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt, + efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid, + efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz, + efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs. + +2004-10-01 Bill Farmer + + * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement + rather than add it. + +2004-09-30 Paul Brook + + * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction. + * arm-opc.h: Document %e. Add ARMv6ZK instructions. + +2004-09-17 H.J. Lu + + * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9. + (CONFIG_STATUS_DEPENDENCIES): New. + (Makefile): Removed. + (config.status): Likewise. + * Makefile.in: Regenerated. + +2004-09-17 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2004-09-11 Andreas Schwab + + * configure: Rebuild. + +2004-09-09 Segher Boessenkool + + * ppc-opc.c (L): Make this field not optional. + +2004-09-03 Tomer Levi + + * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'. + Fix parameter to 'm[t|f]csr' insns. + +2004-08-30 Nathanael Nerode + + * configure.in: Autoupdate to autoconf 2.59. + * aclocal.m4: Rebuild with aclocal 1.4p6. + * configure: Rebuild with autoconf 2.59. + * Makefile.in: Rebuild with automake 1.4p6 (picking up + bfd changes for autoconf 2.59 on the way). + * config.in: Rebuild with autoheader 2.59. + +2004-08-27 Richard Sandiford + + * frv-desc.[ch], frv-opc.[ch]: Regenerated. + +2004-07-30 Michal Ludvig + + * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1 + (GRPPADLCK2): New define. + (twobyte_has_modrm): True for 0xA6. + (grps): GRPPADLCK2 for opcode 0xA6. + +2004-07-29 Alexandre Oliva + + Introduce SH2a support. + * sh-opc.h (arch_sh2a_base): Renumber. + (arch_sh2a_nofpu_base): Remove. + (arch_sh_base_mask): Adjust. + (arch_opann_mask): New. + (arch_sh2a, arch_sh2a_nofpu): Adjust. + (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise. + (sh_table): Adjust whitespace. + 2004-02-24 Corinna Vinschen + * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in + instruction list throughout. + (arch_sh2a_up): Redefine to include fpu instruction set. Use instead + of arch_sh2a in instruction list throughout. + (arch_sh2e_up): Accomodate above changes. + (arch_sh2_up): Ditto. + 2004-02-20 Corinna Vinschen + * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up. + 2004-02-18 Corinna Vinschen + * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling. + * sh-opc.h (arch_sh2a_nofpu): New. + (arch_sh2a_up): New, defines sh2a and sh2a_nofpu. + (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU + instruction. + 2004-01-20 DJ Delorie + * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs. + 2003-12-29 DJ Delorie + * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up, + sh_opcode_info, sh_table): Add sh2a support. + (arch_op32): New, to tag 32-bit opcodes. + * sh-dis.c (print_insn_sh): Support sh2a opcodes. + 2003-12-02 Michael Snyder + * sh-opc.h (arch_sh2a): Add. + * sh-dis.c (arch_sh2a): Handle. + * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a. + +2004-07-27 Tomer Levi + + * crx-opc.c: Add popx,pushx insns. Indent code, fix comments. + +2004-07-22 Nick Clifton + + PR/280 + * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the + insns - this is done by objdump itself. + * h8500-dis.c (print_insn_h8500): Likewise. + +2004-07-21 Jan Beulich + + * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode + regardless of address size prefix in effect. + (ptr_reg): Size or address registers does not depend on rex64, but + on the presence of an address size override. + (OP_MMX): Use rex.x only for xmm registers. + (OP_EM): Use rex.z only for xmm registers. + +2004-07-20 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2 + move/branch operations to the bottom so that VR5400 multimedia + instructions take precedence in disassembly. + +2004-07-20 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32 + ISA-specific "break" encoding. + +2004-07-13 Elvis Chiang + + * arm-opc.h: Fix typo in comment. + +2004-07-11 Andreas Schwab + + * m68k-dis.c (m68k_valid_ea): Fix typos in last change. + +2004-07-09 Andreas Schwab + + * m68k-dis.c (m68k_valid_ea): Check validity of all codes. + +2004-07-07 Tomer Levi + + * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c. + (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo. + (crx-dis.lo): New target. + (crx-opc.lo): Likewise. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_crx_arch. + * configure: Regenerate. + * crx-dis.c: New file. + * crx-opc.c: New file. + * disassemble.c (ARCH_crx): Define. + (disassembler): Handle ARCH_crx. + +2004-06-29 James E Wilson + + * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds. + * ia64-asmtab.c: Regnerate. + +2004-06-28 Alan Modra + + * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf. + (extract_fxm): Don't test dialect. + (XFXFXM_MASK): Include the power4 bit. + (XFXM): Add p4 param. + (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr. + +2004-06-27 Alexandre Oliva + + 2003-07-21 Richard Sandiford + * disassemble.c (disassembler): Handle bfd_mach_h8300sxn. + +2004-06-26 Alan Modra + + * ppc-opc.c (BH, XLBH_MASK): Define. + (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl. + +2004-06-24 Alan Modra + + * i386-dis.c (x_mode): Comment. + (two_source_ops): File scope. + (float_mem): Correct fisttpll and fistpll. + (float_mem_mode): New table. + (dofloat): Use it. + (OP_E): Correct intel mode PTR output. + (ptr_reg): Use open_char and close_char. + (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for + operands. Set two_source_ops. + +2004-06-15 Alan Modra + + * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size + instead of _raw_size. + +2004-06-08 Jakub Jelinek + + * ia64-gen.c (in_iclass): Handle more postinc st + and ld variants. + * ia64-asmtab.c: Rebuilt. + +2004-06-01 Martin Schwidefsky + + * s390-opc.txt: Correct architecture mask for some opcodes. + lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available + in the esa mode as well. + +2004-05-28 Andrew Stubbs + + * sh-dis.c (target_arch): Make unsigned. + (print_insn_sh): Replace (most of) switch with a call to + sh_get_arch_from_bfd_mach(). Also use new architecture flags system. + * sh-opc.h: Redefine architecture flags values. + Add sh3-nommu architecture. + Reorganise _up macros so they make more visual sense. + (SH_MERGE_ARCH_SET): Define new macro. + (SH_VALID_BASE_ARCH_SET): Likewise. + (SH_VALID_MMU_ARCH_SET): Likewise. + (SH_VALID_CO_ARCH_SET): Likewise. + (SH_VALID_ARCH_SET): Likewise. + (SH_MERGE_ARCH_SET_VALID): Likewise. + (SH_ARCH_SET_HAS_FPU): Likewise. + (SH_ARCH_SET_HAS_DSP): Likewise. + (SH_ARCH_UNKNOWN_ARCH): Likewise. + (sh_get_arch_from_bfd_mach): Add prototype. + (sh_get_arch_up_from_bfd_mach): Likewise. + (sh_get_bfd_mach_from_arch_set): Likewise. + (sh_merge_bfd_arc): Likewise. + +2004-05-24 Peter Barada + + * m68k-dis.c(print_insn_m68k): Strip body of diassembly out + into new match_insn_m68k function. Loop over canidate + matches and select first that completely matches. + * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit. + * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea + to verify addressing for MAC/EMAC. + * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC + reigster halves since 'fpu' and 'spl' look misleading. + * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases. + * m68k-opc.c: Rearragne mac/emac cases to use longest for + first, tighten up match masks. + * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce + 'size' from special case code in print_insn_m68k to + determine decode size of insns. + +2004-05-19 Alan Modra + + * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as + well as when -mpower4. + +2004-05-13 Nick Clifton + + * po/fr.po: Updated French translation. + +2004-05-05 Peter Barada + + * m68k-dis.c(print_insn_m68k): Add new chips, use core + variants in arch_mask. Only set m68881/68851 for 68k chips. + * m68k-op.c: Switch from ColdFire chips to core variants. + +2004-05-05 Alan Modra + + PR 147. + * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC. + +2004-04-29 Ben Elliston + + * ppc-opc.c (XCMPL): Renmame to XOPL. Update users. + (powerpc_opcodes): Add "dbczl" instruction for PPC970. + +2004-04-22 Kaz Kojima + + * sh-dis.c (print_insn_sh): Print the value in constant pool + as a symbol if it looks like a symbol. + +2004-04-22 Peter Barada + + * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on + appropriate ColdFire architectures. + (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC + mask addressing. + Add EMAC instructions, fix MAC instructions. Remove + macmw/macml/msacmw/msacml instructions since mask addressing now + supported. + +2004-04-20 Jakub Jelinek + + * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define. + (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to + suffix. Use fmov*x macros, create all 3 fpsize variants in one + macro. Adjust all users. + +2004-04-15 Anil Paranjpe + + * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs" + separately. + +2004-03-30 Kazuhiro Inaoka + + * m32r-asm.c: Regenerate. + +2004-03-29 Stan Shebs + + * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer + used. + +2004-03-19 Alan Modra + + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2004-03-16 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle + PPC_OPERANDS_GPR_0. + * ppc-opc.c (RA0): Define. + (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. + (RAOPT): Rename from RAO. Update all uses. + (powerpc_opcodes): Use RA0 as appropriate. + +2004-03-15 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. + +2004-03-15 Alan Modra + + * sparc-dis.c (print_insn_sparc): Update getword prototype. + +2004-03-12 Michal Ludvig + + * i386-dis.c (GRPPLOCK): Delete. + (grps): Delete GRPPLOCK entry. + +2004-03-12 Alan Modra + + * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions. + (M, Mp): Use OP_M. + (None, PADLOCK_SPECIAL, PADLOCK_0): Delete. + (GRPPADLCK): Define. + (dis386): Use NOP_Fixup on "nop". + (dis386_twobyte): Use GRPPADLCK on opcode 0xa7. + (twobyte_has_modrm): Set for 0xa7. + (padlock_table): Delete. Move to.. + (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence + and clflush. + (print_insn): Revert PADLOCK_SPECIAL code. + (OP_E): Delete sfence, lfence, mfence checks. + +2004-03-12 Jakub Jelinek + + * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg. + (INVLPG_Fixup): New function. + (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag. + +2004-03-12 Michal Ludvig + + * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. + (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. + (padlock_table): New struct with PadLock instructions. + (print_insn): Handle PADLOCK_SPECIAL. + +2004-03-12 Alan Modra + + * i386-dis.c (grps): Use clflush by default for 0x0fae/7. + (OP_E): Twiddle clflush to sfence here. + +2004-03-08 Nick Clifton + + * po/de.po: Updated German translation. + +2003-03-03 Andrew Stubbs + + * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in + nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. + * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions + accordingly. + +2004-03-01 Richard Sandiford + + * frv-asm.c: Regenerate. + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-opc.h: Regenerate. + +2004-03-01 Richard Sandiford + + * frv-desc.c, frv-opc.c: Regenerate. + +2004-03-01 Richard Sandiford + + * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate. + +2004-02-26 Andrew Stubbs + + * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. + Also correct mistake in the comment. + +2004-02-26 Andrew Stubbs + + * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to + ensure that double registers have even numbers. + Add REG_N_B01 for nn01 (binary 01) nibble to ensure + that reserved instruction 0xfffd does not decode the same + as 0xfdfd (ftrv). + * sh-opc.h: Add REG_N_D nibble type and use it whereever + REG_N refers to a double register. + Add REG_N_B01 nibble type and use it instead of REG_NM + in ftrv. + Adjust the bit patterns in a few comments. + +2004-02-25 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. + +2004-02-20 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat. + +2004-02-20 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add m*ivor35. + +2004-02-20 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, + mtivor32, mtivor33, mtivor34. + +2004-02-19 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Add mfmcar. + +2004-02-10 Petko Manolov + + * arm-opc.h Maverick accumulator register opcode fixes. + +2004-02-13 Ben Elliston + + * m32r-dis.c: Regenerate. + +2004-01-27 Michael Snyder + + * sh-opc.h (sh_table): "fsrra", not "fssra". + +2004-01-23 Andrew Over + + * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten + contraints. + +2004-01-19 Andrew Over + + * sparc-opc.c (sparc_opcodes) : Fix args. + +2004-01-19 Alan Modra + + * i386-dis.c (OP_E): Print scale factor on intel mode sib when not + 1. Don't print scale factor on AT&T mode when index missing. + +2004-01-16 Alexandre Oliva + + * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended + when loaded into XR registers. + +2004-01-14 Richard Sandiford + + * frv-desc.h: Regenerate. + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + +2004-01-13 Michael Snyder + + * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn. + +2004-01-09 Paul Brook + + * arm-opc.h (arm_opcodes): Move generic mcrr after known + specific opcodes. + +2004-01-07 Daniel Jacobowitz + + * Makefile.am (libopcodes_la_DEPENDENCIES) + (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory + comment about the problem. + * Makefile.in: Regenerate. + +2004-01-06 Alexandre Oliva + + 2003-12-19 Alexandre Oliva + * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some + cut&paste errors in shifting/truncating numerical operands. + 2003-08-04 Alexandre Oliva + * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. + (parse_d12): Parse gotoff12 and gotofffuncdesc12. + (parse_s12): Likewise. + 2003-08-04 Alexandre Oliva + * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gothi and gotfuncdeschi. + (parse_d12): Parse got12 and gotfuncdesc12. + (parse_s12): Likewise. + +2004-01-02 Albert Bartoszko + + * msp430-dis.c (msp430_doubleoperand): Check for an 'add' + instruction which looks similar to an 'rla' instruction. + +For older changes see ChangeLog-0203 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2005 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2005 new file mode 100644 index 000000000000..30845578dc1b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2005 @@ -0,0 +1,1253 @@ +2005-12-27 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2005-12-22 Laurent Menten + + * pj-opc.c (jsr, ret, getstatic, putstatic, getfield, putfield, + invokevirtual, invokespecial, invokestatic, invokeinterface, + goto_w, jsr_w, ldc_quick, ldc_w_quick, ldc2_w_quick, + getfield_quick, putfield_quick, getfield2_quick, putfield2_quick, + getstatic_quick, putstatic_quick, getstatic2_quick, + putstatic2_quick, invokevirtual_quick, invokenonvirtual_quick, + invokesuper_quick, invokestatic_quick, invokeinterface_quick, + aastore_quick, new_quick, anewarray_quick, multianewarray_quick, + checkcast_quick, instanceof_quick, invokevirtiual_quick_w, + getfield_quick_w, putfield_quick_w, nonnull_quick, + agetfield_quick, aputfield_quick, agetstatic_quick, + aputstatic_quick, aldc_quick, aldc_w_quick, exit_sync_method): Fix + opcodes. + +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust. + (stamp-mt): Adjust rule. + (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename & + adjust. + * Makefile.in: Rebuilt. + * configure: Rebuilt. + * configure.in (bfd_mt_arch): Rename & adjust. + * disassemble.c (ARCH_mt): Renamed. + (disassembler): Adjust. + * mt-asm.c: Renamed, rebuilt. + * mt-desc.c: Renamed, rebuilt. + * mt-desc.h: Renamed, rebuilt. + * mt-dis.c: Renamed, rebuilt. + * mt-ibld.c: Renamed, rebuilt. + * mt-opc.c: Renamed, rebuilt. + * mt-opc.h: Renamed, rebuilt. + +2005-12-13 DJ Delorie + + * m32c-desc.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-12-12 Nathan Sidwell + + * Makefile.am (CLEANFILES, CGEN_CPUS, MT_DEPS): Replace ms1 with mt. + * Makefile.in: Rebuilt. + * configure.in: Replace ms1 files with mt files. + * configure: Rebuilt. + +2005-12-08 Jan Beulich + + * i386-dis.c (MAXLEN): Reduce to architectural limit. + (fetch_data): Check for sufficient buffer size. + +2005-12-08 Jan Beulich + + * i386-dis.c (OP_ST): Remove prefix in Intel mode. + +2005-12-08 Daniel Jacobowitz + + * i386-dis.c (dofloat): Handle %rip-relative floating point addressing. + +2005-12-07 Hans-Peter Nilsson + + * cris-opc.c (cris_opcodes) <"move" "s,P">: Define using + MOVE_M_TO_PREG_OPCODE and MOVE_M_TO_PREG_ZBITS instead of constants. + +2005-12-06 H.J. Lu + + PR gas/1874 + * i386-dis.c (address_mode): New enum type. + (address_mode): New variable. + (mode_64bit): Removed. + (ckprefix): Updated to check address_mode instead of mode_64bit. + (prefix_name): Likewise. + (print_insn): Likewise. + (putop): Likewise. + (print_operand_value): Likewise. + (intel_operand_size): Likewise. + (OP_E): Likewise. + (OP_G): Likewise. + (set_op): Likewise. + (OP_REG): Likewise. + (OP_I): Likewise. + (OP_I64): Likewise. + (OP_OFF): Likewise. + (OP_OFF64): Likewise. + (ptr_reg): Likewise. + (OP_C): Likewise. + (SVME_Fixup): Likewise. + (print_insn): Set address_mode. + (PNI_Fixup): Add 64bit and address size override support for + monitor and mwait. + +2005-12-06 Hans-Peter Nilsson + + * cris-dis.c (bytes_to_skip): Handle new parameter prefix_matchedp. + (print_with_operands): Check for prefix when [PC+] is seen. + +2005-12-02 Dave Brolley + + * configure.in (cgen_files): Add cgen-bitset.lo. + (ta): Add cgen-bitset.lo when arch==bfd_cris_arch. + * Makefile.am (CFILES): Add cgen-bitset.c. + (ALL_MACHINES): Add cgen-bitset.lo. + (cgen-bitset.lo): New target. + * cgen-opc.c (cgen_bitset_create, cgen_bitset_init, cgen_bitset_clear) + (cgen_bitset_add, cgen_bitset_set, cgen_bitset_contains) + (cgen_bitset_compare, cgen_bitset_intersect_p, cgen_bitset_copy) + (cgen_bitset_union): Moved from here ... + * cgen-bitset.c: ... to here. New file. + * Makefile.in: Regenerated. + * configure: Regenerated. + +2005-11-22 James E Wilson + + * ia64-gen.c (_opcode_int64_low, _opcode_int64_high, + opcode_fprintf_vma): New. + (print_main_table): New opcode_fprintf_vma instead of fprintf_vma. + +2005-11-16 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. Correct + frsqrtes. + +2005-11-14 David Ung + + * mips16-opc.c: Add MIPS16e save/restore opcodes. + * mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M' + codes for save/restore. + +2005-11-10 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Only match FPU insns with + coprocessor ID 1. + +2005-11-08 H.J. Lu + + * m32c-desc.c: Regenerated. + +2005-11-08 Nathan Sidwell + + Add ms2. + * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, + ms1-opc.c, ms1-opc.h: Regenerated. + +2005-11-07 Steve Ellcey + + * configure: Regenerate after modifying bfd/warning.m4. + +2005-11-07 Alan Modra + + * i386-dis.c (ckprefix): Handle rex on fwait. Don't print + ignored rex prefixes here. + (print_insn): Instead, handle them similarly to fwait followed + by non-fp insns. + +2005-11-02 H.J. Lu + + * iq2000-desc.c: Regenerated. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-opc.c: Likewise. + +2005-11-02 Paul Brook + + * arm-dis.c (print_insn_thumb32): Word align blx target address. + +2005-10-31 Alan Modra + + * arm-dis.c (print_insn): Warning fix. + +2005-10-30 H.J. Lu + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerated. + + * dep-in.sed: Replace " ./" with " ". + +2005-10-28 Dave Brolley + + * All CGEN-generated sources: Regenerate. + + Contribute the following changes: + 2005-09-19 Dave Brolley + + * disassemble.c (disassemble_init_for_target): Add 'break' to case for + bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for + bfd_arch_m32c case. + + 2005-02-16 Dave Brolley + + * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename + cgen_isa_mask_* to cgen_bitset_*. + * cgen-opc.c: Likewise. + + 2003-11-28 Richard Sandiford + + * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. + * *-dis.c: Regenerate. + + 2003-06-05 DJ Delorie + + * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign + it, as it may point to a reused buffer. Set prev_isas when we + change cpus. + + 2002-12-13 Dave Brolley + + * cgen-opc.c (cgen_isa_mask_create): New support function for + CGEN_ISA_MASK. + (cgen_isa_mask_init): Ditto. + (cgen_isa_mask_clear): Ditto. + (cgen_isa_mask_add): Ditto. + (cgen_isa_mask_set): Ditto. + (cgen_isa_supported): Ditto. + (cgen_isa_mask_compare): Ditto. + (cgen_isa_mask_intersection): Ditto. + (cgen_isa_mask_copy): Ditto. + (cgen_isa_mask_combine): Ditto. + * cgen-dis.in (libiberty.h): #include it. + (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *). + (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. + * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. + * Makefile.in: Regenerated. + +2005-10-27 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-10-26 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-10-26 Paul Brook + + * arm-dis.c (arm_opcodes): Correct "sel" entry. + +2005-10-26 Kazuhiro Inaoka + + * m32r-asm.c: Regenerate. + +2005-10-25 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-10-25 Arnold Metselaar + + * configure.in: Add target architecture bfd_arch_z80. + * configure: Regenerated. + * disassemble.c (disassembler): Add case + bfd_arch_z80. + * z80-dis.c: New file. + +2005-10-25 Alan Modra + + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2005-10-24 Jan Beulich + + * ia64-asmtab.c: Regenerate. + +2005-10-21 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-10-21 Nick Clifton + + * bfin-dis.c: Tidy up code, removing redundant constructs. + +2005-10-19 Martin Schwidefsky + + * s390-opc.txt: Add unnormalized hfp multiply and multiply-and-add + instructions. + +2005-10-18 Nick Clifton + + * m32r-asm.c: Regenerate after updating m32r.opc. + +2005-10-18 Jie Zhang + + * bfin-dis.c (print_insn_bfin): Do proper endian transform when + reading instruction from memory. + +2005-10-18 Nick Clifton + + * m32r-asm.c: Regenerate after updating m32r.opc. + +2005-10-14 Kazuhiro Inaoka + + * m32r-asm.c: Regenerate after updating m32r.opc. + +2005-10-08 James Lemke + + * arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP + operations. + +2005-10-06 Daniel Jacobowitz + + * ppc-dis.c (struct dis_private): Remove. + (powerpc_dialect): Avoid aliasing warnings. + (print_insn_big_powerpc, print_insn_little_powerpc): Likewise. + +2005-09-30 Nick Clifton + + * po/ga.po: New Irish translation. + * configure.in (ALL_LINGUAS): Add "ga". + * configure: Regenerate. + +2005-09-30 H.J. Lu + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerated. + * aclocal.m4: Likewise. + * configure: Likewise. + +2005-09-30 Catherine Moore + + * Makefile.am: Bfin support. + * Makefile.in: Regenerated. + * aclocal.m4: Regenerated. + * bfin-dis.c: New file. + * configure.in: Bfin support. + * configure: Regenerated. + * disassemble.c (ARCH_bfin): Define. + (disassembler): Add case for bfd_arch_bfin. + +2005-09-28 Jan Beulich + + * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. + (indirEv): Use it. + (stackEv): New. + (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. + (dis386): Document and use new 'V' meta character. Use it for + single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop + opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. + (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark + data prefix as used whenever DFLAG was examined. Handle 'V'. + (intel_operand_size): Use stack_v_mode. + (OP_E): Use stack_v_mode, but handle only the special case of + 64-bit mode without operand size override here; fall through to + v_mode case otherwise. + (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode + and no operand size override is present. + (OP_J): Use get32s for obtaining the displacement also when rex64 + is present. + +2005-09-08 Paul Brook + + * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc. + +2005-09-06 Chao-ying Fu + + * mips-opc.c (MT32): New define. + (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the + bottom to avoid opcode collision with "mftr" and "mttr". + Add MT instructions. + * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2. + (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand + formats. + +2005-09-02 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Add null terminator. + +2005-09-02 Paul Brook + + * arm-dis.c (coprocessor_opcodes): New. + (arm_opcodes, thumb32_opcodes): Remove coprocessor insns. + (print_insn_coprocessor): New function. + (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor + format characters. + (print_insn_thumb32): Use print_insn_coprocessor. + +2005-08-30 Paul Brook + + * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs. + +2005-08-26 Jan Beulich + + * i386-dis.c (intel_operand_size): New, broken out from OP_E for + re-use. + (OP_E): Call intel_operand_size, move call site out of mode + dependent code. + (OP_OFF): Call intel_operand_size if suffix_always. Remove + ATTRIBUTE_UNUSED from parameters. + (OP_OFF64): Likewise. + (OP_ESreg): Call intel_operand_size. + (OP_DSreg): Likewise. + (OP_DIR): Use colon rather than semicolon as separator of far + jump/call operands. + +2005-08-25 Chao-ying Fu + + * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define. + (mips_builtin_opcodes): Add DSP instructions. + * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2, + mips64, mips64r2. + (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ + operand formats. + +2005-08-23 David Ung + + * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc + instructions to the table. + +2005-08-18 Alan Modra + + * a29k-dis.c: Delete. + * Makefile.am: Remove a29k support. + * configure.in: Likewise. + * disassemble.c: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2005-08-15 Daniel Jacobowitz + + * ppc-dis.c (powerpc_dialect): Handle e300. + (print_ppc_disassembler_options): Likewise. + * ppc-opc.c (PPCE300): Define. + (powerpc_opcodes): Mark icbt as available for the e300. + +2005-08-13 John David Anglin + + * hppa-dis.c (print_insn_hppa): Don't print '%' before register names. + Use "rp" instead of "%r2" in "b,l" insns. + +2005-08-12 Martin Schwidefsky + + * s390-dis.c (print_insn_s390): Print unsigned operands with %u. + * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109. + (main): Likewise. + * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates + and 4 bit optional masks. + (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD, + INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats. + (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD, + MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise. + (s390_opformats): Likewise. + * s390-opc.txt: Add new instructions for cpu type z9-109. + +2005-08-05 John David Anglin + + * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%". + +2005-07-29 Paul Brook + + * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes. + +2005-07-29 Paul Brook + + * arm-dis.c (thumb32_opc): Fix addressing mode for tbh. + (print_insn_thumb32): Fix decoding of thumb2 'I' operands. + +2005-07-25 DJ Delorie + + * m32c-asm.c Regenerate. + * m32c-dis.c Regenerate. + +2005-07-20 DJ Delorie + + * disassemble.c (disassemble_init_for_target): M32C ISAs are + enums, so convert them to bit masks, which attributes are. + +2005-07-18 Nick Clifton + + * configure.in: Restore alpha ordering to list of arches. + * configure: Regenerate. + * disassemble.c: Restore alpha ordering to list of arches. + +2005-07-18 Nick Clifton + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.h: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-07-18 H.J. Lu + + * i386-dis.c (PNI_Fixup): Update comment. + (VMX_Fixup): Properly handle the suffix check. + +2005-07-16 John David Anglin + + * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode + mfctl disassembly. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + (stamp-m32c): Fix cpu dependencies. + * Makefile.in: Regenerate. + * ip2k-dis.c: Regenerate. + +2007-07-15 H.J. Lu + + * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions. + (VMX_Fixup): New. Fix up Intel VMX Instructions. + (Em): New. + (Gm): New. + (VM): New. + (dis386_twobyte): Updated entries 0x78 and 0x79. + (twobyte_has_modrm): Likewise. + (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9. + (OP_G): Handle m_mode. + +2005-07-14 Jim Blandy + + Add support for the Renesas M32C and M16C. + * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New. + * m32c-desc.h, m32c-opc.h: New. + * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h. + (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, + m32c-opc.c. + (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, + m32c-ibld.lo, m32c-opc.lo. + (CLEANFILES): List stamp-m32c. + (M32C_DEPS): List stamp-m32c, if CGEN_MAINT. + (CGEN_CPUS): Add m32c. + (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c) + (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS. + (m32c_opc_h): New variable. + (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo) + (m32c-opc.lo): New rules. + * Makefile.in: Regenerated. + * configure.in: Add case for bfd_m32c_arch. + * configure: Regenerated. + * disassemble.c (ARCH_m32c): New. + [ARCH_m32c]: #include "m32c-desc.h". + (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c. + (disassemble_init_for_target) [ARCH_m32c]: Same. + + * cgen-ops.h, cgen-types.h: New files. + * Makefile.am (HFILES): List them. + * Makefile.in: Regenerated. + +2005-07-07 Kaveh R. Ghazi + + * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, + d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, + ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, + m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, + ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, + v850-dis.c: Fix format bugs. + * ia64-gen.c (fail, warn): Add format attribute. + * or32-opc.c (debug): Likewise. + +2005-07-07 Khem Raj + + * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction + disassembly pattern. + +2005-07-06 Alan Modra + + * Makefile.am (stamp-m32r): Fix path to cpu files. + (stamp-m32r, stamp-iq2000): Likewise. + * Makefile.in: Regenerate. + * m32r-asm.c: Regenerate. + * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c, + ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h. + +2005-07-05 Nick Clifton + + * iq2000-asm.c: Regenerate. + * ms1-asm.c: Regenerate. + +2005-07-05 Jan Beulich + + * i386-dis.c (SVME_Fixup): New. + (grps): Use it for the lidt entry. + (PNI_Fixup): Call OP_M rather than OP_E. + (INVLPG_Fixup): Likewise. + +2005-07-04 H.J. Lu + + * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined. + +2005-07-01 Nick Clifton + + * a29k-dis.c: Update to ISO C90 style function declarations and + fix formatting. + * alpha-opc.c: Likewise. + * arc-dis.c: Likewise. + * arc-opc.c: Likewise. + * avr-dis.c: Likewise. + * cgen-asm.in: Likewise. + * cgen-dis.in: Likewise. + * cgen-ibld.in: Likewise. + * cgen-opc.c: Likewise. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * d30v-opc.c: Likewise. + * dis-buf.c: Likewise. + * dlx-dis.c: Likewise. + * h8300-dis.c: Likewise. + * h8500-dis.c: Likewise. + * hppa-dis.c: Likewise. + * i370-dis.c: Likewise. + * i370-opc.c: Likewise. + * m10200-dis.c: Likewise. + * m10300-dis.c: Likewise. + * m68k-dis.c: Likewise. + * m88k-dis.c: Likewise. + * mips-dis.c: Likewise. + * mmix-dis.c: Likewise. + * msp430-dis.c: Likewise. + * ns32k-dis.c: Likewise. + * or32-dis.c: Likewise. + * or32-opc.c: Likewise. + * pdp11-dis.c: Likewise. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * sh-dis.c: Likewise. + * sh64-dis.c: Likewise. + * sparc-dis.c: Likewise. + * sparc-opc.c: Likewise. + * sysdep.h: Likewise. + * tic30-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * tic80-dis.c: Likewise. + * v850-dis.c: Likewise. + * v850-opc.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8kgen.c: Likewise. + + * fr30-*: Regenerate. + * frv-*: Regenerate. + * ip2k-*: Regenerate. + * iq2000-*: Regenerate. + * m32r-*: Regenerate. + * ms1-*: Regenerate. + * openrisc-*: Regenerate. + * xstormy16-*: Regenerate. + +2005-06-23 Ben Elliston + + * m68k-dis.c: Use ISC C90. + * m68k-opc.c: Formatting fixes. + +2005-06-16 David Ung + + * mips16-opc.c (mips16_opcodes): Add the following MIPS16e + instructions to the table; seb/seh/sew/zeb/zeh/zew. + +2005-06-15 Dave Brolley + + Contribute Morpho ms1 on behalf of Red Hat + * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c, + ms1-opc.h: New files, Morpho ms1 target. + + 2004-05-14 Stan Cox + + * disassemble.c (ARCH_ms1): Define. + (disassembler): Handle bfd_arch_ms1 + + 2004-05-13 Michael Snyder + + * Makefile.am, Makefile.in: Add ms1 target. + * configure.in: Ditto. + +2005-06-08 Zack Weinberg + + * arm-opc.h: Delete; fold contents into ... + * arm-dis.c: ... here. Move includes of internal COFF headers + next to includes of internal ELF headers. + (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused. + (struct arm_opcode): Rename struct opcode32. Make 'assembler' const. + (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const. + (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames) + (iwmmxt_wwnames, iwmmxt_wwssnames): + Make const. + (regnames): Remove iWMMXt coprocessor register sets. + (iwmmxt_regnames, iwmmxt_cregnames): New statics. + (get_arm_regnames): Adjust fourth argument to match above changes. + (set_iwmmxt_regnames): Delete. + (print_insn_arm): Constify 'c'. Use ISO syntax for function + pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames + and iwmmxt_cregnames, not set_iwmmxt_regnames. + (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use + ISO syntax for function pointer calls. + +2005-06-07 Zack Weinberg + + * arm-dis.c: Split up the comments describing the format codes, so + that the ARM and 16-bit Thumb opcode tables each have comments + preceding them that describe all the codes, and only the codes, + valid in those tables. (32-bit Thumb table is already like this.) + Reorder the lists in all three comments to match the order in + which the codes are implemented. + Remove all forward declarations of static functions. Convert all + function definitions to ISO C format. + (print_insn_arm, print_insn_thumb16, print_insn_thumb32): + Return nothing. + (print_insn_thumb16): Remove unused case 'I'. + (print_insn): Update for changed calling convention of subroutines. + +2005-05-25 Jan Beulich + + * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in + hex (but retain it being displayed as signed). Remove redundant + checks. Add handling of displacements for 16-bit addressing in Intel + mode. + +2005-05-25 Jan Beulich + + * i386-dis.c (prefix_name): Remove pointless mode_64bit check. + (OP_E): Remove redundant REX_EXTZ handling. Remove pointless + masking of 'rm' in 16-bit memory address handling. + +2005-05-19 Anton Blanchard + + * ppc-dis.c (powerpc_dialect): Handle "-Mpower5". + (print_ppc_disassembler_options): Document it. + * ppc-opc.c (SVC_LEV): Define. + (LEV): Allow optional operand. + (POWER5): Define. + (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add + "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.". + +2005-05-19 Kelley Cook + + * Makefile.in: Regenerate. + +2005-05-17 Zack Weinberg + + * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit + instructions. Adjust disassembly of some opcodes to match + unified syntax. + (thumb32_opcodes): New table. + (print_insn_thumb): Rename print_insn_thumb16; don't handle + two-halfword branches here. + (print_insn_thumb32): New function. + (print_insn): Choose among print_insn_arm, print_insn_thumb16, + and print_insn_thumb32. Be consistent about order of + halfwords when printing 32-bit instructions. + +2005-05-07 H.J. Lu + + PR 843 + * i386-dis.c (branch_v_mode): New. + (indirEv): Use branch_v_mode instead of v_mode. + (OP_E): Handle branch_v_mode. + +2005-05-07 H.J. Lu + + * d10v-dis.c (dis_2_short): Support 64bit host. + +2005-05-07 Nick Clifton + + * po/nl.po: Updated translation. + +2005-05-07 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c, + arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h, + avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in, + cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c, + crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, + d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c, + fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, + fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h, + frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c, + h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c, + i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c, + ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c, + ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c, + ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h, + ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c, + iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c, + iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c, + m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h, + m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c, + m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, + maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c, + mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c, + openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c, + openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h, + or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c, + pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c, + s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c, + sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c, + tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c, + v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h, + xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h, + xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c, + xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c + +2005-05-05 James E Wilson + + * ia64-opc.c: Include sysdep.h before libiberty.h. + +2005-05-05 Nick Clifton + + * configure.in (ALL_LINGUAS): Add vi. + * configure: Regenerate. + * po/vi.po: New. + +2005-04-26 Jerome Guitton + + * configure.in: Fix the check for basename declaration. + * configure: Regenerate. + +2005-04-19 Alan Modra + + * ppc-opc.c (RTO): Define. + (powerpc_opcodes ): Combine PPC403 and BOOKE + entries to suit PPC440. + +2005-04-18 Mark Kettenis + + * i386-dis.c: Insert hyphens into selected VIA PadLock extensions. + Add xcrypt-ctr. + +2005-04-14 Nick Clifton + + * po/fi.po: New translation: Finnish. + * configure.in (ALL_LINGUAS): Add fi. + * configure: Regenerate. + +2005-04-14 Alan Modra + + * Makefile.am (NO_WERROR): Define. + * configure.in: Invoke AM_BINUTILS_WARNINGS. + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * configure: Regenerate. + +2005-04-04 Nick Clifton + + * fr30-asm.c: Regenerate. + * frv-asm.c: Regenerate. + * iq2000-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + +2005-04-01 Jan Beulich + + * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any + visible operands in Intel mode. The first operand of monitor is + %rax in 64-bit mode. + +2005-04-01 Jan Beulich + + * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for + easier future additions. + +2005-03-31 Jerome Guitton + + * configure.in: Check for basename. + * configure: Regenerate. + * config.in: Ditto. + +2005-03-29 H.J. Lu + + * i386-dis.c (SEG_Fixup): New. + (Sv): New. + (dis386): Use "Sv" for 0x8c and 0x8e. + +2005-03-21 Jan-Benedict Glaw + Nick Clifton + + * vax-dis.c: (entry_addr): New varible: An array of user supplied + function entry mask addresses. + (entry_addr_occupied_slots): New variable: The number of occupied + elements in entry_addr. + (entry_addr_total_slots): New variable: The total number of + elements in entry_addr. + (parse_disassembler_options): New function. Fills in the entry_addr + array. + (free_entry_array): New function. Release the memory used by the + entry addr array. Suppressed because there is no way to call it. + (is_function_entry): Check if a given address is a function's + start address by looking at supplied entry mask addresses and + symbol information, if available. + (print_insn_vax): Use parse_disassembler_options and is_function_entry. + +2005-03-23 H.J. Lu + + * cris-dis.c (print_with_operands): Use ~31L for long instead + of ~31. + +2005-03-20 H.J. Lu + + * mmix-opc.c (O): Revert the last change. + (Z): Likewise. + +2005-03-19 H.J. Lu + + * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long. + (Z): Likewise. + +2005-03-19 Hans-Peter Nilsson + + * mmix-opc.c (O, Z): Force expression as unsigned long. + +2005-03-18 Nick Clifton + + * ip2k-asm.c: Regenerate. + * op/opcodes.pot: Regenerate. + +2005-03-16 Nick Clifton + Ben Elliston + + * configure.in (werror): New switch: Add -Werror to the + compiler command line. Enabled by default. Disable via + --disable-werror. + * configure: Regenerate. + +2005-03-16 Alan Modra + + * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when + BOOKE. + +2005-03-15 Alan Modra + + * po/es.po: Commit new Spanish translation. + + * po/fr.po: Commit new French translation. + +2005-03-14 Jan-Benedict Glaw + + * vax-dis.c: Fix spelling error + (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead + of just "Entry mask: < r1 ... >" + +2005-03-12 Zack Weinberg + + * arm-dis.c (arm_opcodes): Document %E and %V. + Add entries for v6T2 ARM instructions: + bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx. + (print_insn_arm): Add support for %E and %V. + (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield. + +2005-03-10 Jeff Baker + Alan Modra + + * ppc-opc.c (insert_sprg, extract_sprg): New Functions. + (powerpc_operands ): Call the above. Bit field is 5 bits. + (SPRG_MASK): Delete. + (XSPRG_MASK): Mask off extra bits now part of sprg field. + (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move + mfsprg4..7 after msprg and consolidate. + +2005-03-09 Jan-Benedict Glaw + + * vax-dis.c (entry_mask_bit): New array. + (print_insn_vax): Decode function entry mask. + +2005-03-07 Aldy Hernandez + + * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd. + +2005-03-05 Alan Modra + + * po/opcodes.pot: Regenerate. + +2005-03-03 Ramana Radhakrishnan + + * arc-dis.c (a4_decoding_class): New enum. + (dsmOneArcInst): Use the enum values for the decoding class. + Remove redundant case in the switch for decodingClass value 11. + +2005-03-02 Jan Beulich + + * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15 + accesses. + (OP_C): Consider lock prefix in non-64-bit modes. + +2005-02-24 Alan Modra + + * cris-dis.c (format_hex): Remove ineffective warning fix. + * crx-dis.c (make_instruction): Warning fix. + * frv-asm.c: Regenerate. + +2005-02-23 Nick Clifton + + * cgen-dis.in: Use bfd_byte for buffers that are passed to + read_memory. + + * ia64-opc.c (locate_opcode_ent): Initialise opval array. + + * crx-dis.c (make_instruction): Move argument structure into inner + scope and ensure that all of its fields are initialised before + they are used. + + * fr30-asm.c: Regenerate. + * fr30-dis.c: Regenerate. + * frv-asm.c: Regenerate. + * frv-dis.c: Regenerate. + * ip2k-asm.c: Regenerate. + * ip2k-dis.c: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-dis.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-dis.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-dis.c: Regenerate. + * xstormy16-asm.c: Regenerate. + * xstormy16-dis.c: Regenerate. + +2005-02-22 Alan Modra + + * arc-ext.c: Warning fixes. + * arc-ext.h: Likewise. + * cgen-opc.c: Likewise. + * ia64-gen.c: Likewise. + * maxq-dis.c: Likewise. + * ns32k-dis.c: Likewise. + * w65-dis.c: Likewise. + * ia64-asmtab.c: Regenerate. + +2005-02-22 Alan Modra + + * fr30-desc.c: Regenerate. + * fr30-desc.h: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-opc.c: Regenerate. + * frv-opc.h: Regenerate. + * ip2k-desc.c: Regenerate. + * ip2k-desc.h: Regenerate. + * ip2k-opc.c: Regenerate. + * ip2k-opc.h: Regenerate. + * iq2000-desc.c: Regenerate. + * iq2000-desc.h: Regenerate. + * iq2000-opc.c: Regenerate. + * iq2000-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-desc.h: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * xstormy16-desc.c: Regenerate. + * xstormy16-desc.h: Regenerate. + * xstormy16-opc.c: Regenerate. + * xstormy16-opc.h: Regenerate. + +2005-02-21 Alan Modra + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2005-02-15 Nick Clifton + + * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent + compile time warnings. + (print_keyword): Likewise. + (default_print_insn): Likewise. + + * fr30-desc.c: Regenerated. + * fr30-desc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * frv-desc.c: Regenerated. + * frv-dis.c: Regenerated. + * frv-opc.c: Regenerated. + * ip2k-asm.c: Regenerated. + * ip2k-desc.c: Regenerated. + * ip2k-desc.h: Regenerated. + * ip2k-dis.c: Regenerated. + * ip2k-opc.c: Regenerated. + * ip2k-opc.h: Regenerated. + * iq2000-desc.c: Regenerated. + * iq2000-dis.c: Regenerated. + * iq2000-opc.c: Regenerated. + * m32r-asm.c: Regenerated. + * m32r-desc.c: Regenerated. + * m32r-desc.h: Regenerated. + * m32r-dis.c: Regenerated. + * m32r-opc.c: Regenerated. + * m32r-opc.h: Regenerated. + * m32r-opinst.c: Regenerated. + * openrisc-desc.c: Regenerated. + * openrisc-desc.h: Regenerated. + * openrisc-dis.c: Regenerated. + * openrisc-opc.c: Regenerated. + * openrisc-opc.h: Regenerated. + * xstormy16-desc.c: Regenerated. + * xstormy16-desc.h: Regenerated. + * xstormy16-dis.c: Regenerated. + * xstormy16-opc.c: Regenerated. + * xstormy16-opc.h: Regenerated. + +2005-02-14 H.J. Lu + + * dis-buf.c (perror_memory): Use sprintf_vma to print out + address. + +2005-02-11 Nick Clifton + + * iq2000-asm.c: Regenerate. + + * frv-dis.c: Regenerate. + +2005-02-07 Jim Blandy + + * Makefile.am (CGEN): Load guile.scm before calling the main + application script. + * Makefile.in: Regenerated. + * cgen.sh: Be prepared for the 'cgen' argument to contain spaces. + Simply pass the cgen-opc.scm path to ${cgen} as its first + argument; ${cgen} itself now contains the '-s', or whatever is + appropriate for the Scheme being used. + +2005-01-31 Andrew Cagney + + * configure: Regenerate to track ../gettext.m4. + +2005-01-31 Jan Beulich + + * ia64-gen.c (NELEMS): Define. + (shrink): Generate alias with missing second predicate register when + opcode has two outputs and these are both predicates. + * ia64-opc-i.c (FULL17): Define. + (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17 + here to generate output template. + (TBITCM, TNATCM): Undefine after use. + * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as + first input. Add ld16 aliases without ar.csd as second output. Add + st16 aliases without ar.csd as second input. Add cmpxchg aliases + without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/ + ar.ccv as third/fourth inputs. Consolidate through... + (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8, + CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define. + * ia64-asmtab.c: Regenerate. + +2005-01-27 Andrew Cagney + + * configure: Regenerate to track ../gettext.m4 change. + +2005-01-25 Alexandre Oliva + + 2004-11-10 Alexandre Oliva + * frv-asm.c: Rebuilt. + * frv-desc.c: Rebuilt. + * frv-desc.h: Rebuilt. + * frv-dis.c: Rebuilt. + * frv-ibld.c: Rebuilt. + * frv-opc.c: Rebuilt. + * frv-opc.h: Rebuilt. + +2005-01-24 Andrew Cagney + + * configure: Regenerate, ../gettext.m4 was updated. + +2005-01-21 Fred Fish + + * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS. + Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. + Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. + * mips-dis.c: Ditto. + +2005-01-20 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel. + +2005-01-19 Fred Fish + + * mips-dis.c (no_aliases): New disassembly option flag. + (set_default_mips_dis_options): Init no_aliases to zero. + (parse_mips_dis_option): Handle no-aliases option. + (print_insn_mips): Ignore table entries that are aliases + if no_aliases is set. + (print_insn_mips16): Ditto. + * mips-opc.c (mips_builtin_opcodes): Add initializer column for + new pinfo2 member and add INSN_ALIAS initializers as needed. Also + move WR_MACC and RD_MACC initializers from pinfo to pinfo2. + * mips16-opc.c (mips16_opcodes): Ditto. + +2005-01-17 Andrew Stubbs + + * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition. + (inheritance diagram): Add missing edge. + (arch_sh1_up): Rename arch_sh_up to match external name to make life + easier for the testsuite. + (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up. + (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up. + (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing + arch_sh2a_or_sh4_up child. + (sh_table): Do renaming as above. + Correct comment for ldc.l for gas testsuite to read. + Remove rogue mul.l from sh1 (duplicate of the one for sh2). + Correct comments for movy.w and movy.l for gas testsuite to read. + Correct comments for fmov.d and fmov.s for gas testsuite to read. + +2005-01-12 H.J. Lu + + * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode. + +2005-01-12 H.J. Lu + + * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB. + +2005-01-10 Andreas Schwab + + * disassemble.c (disassemble_init_for_target) : Set skip_zeroes to 16. + : Set skip_zeroes to 32. + +For older changes see ChangeLog-2004 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2006 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2006 new file mode 100644 index 000000000000..cc5ec75d9c01 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2006 @@ -0,0 +1,837 @@ +2006-12-27 Kazu Hirata + + * m68k-dis.c (print_insn_arg): Add support for cac and mbb. + +2006-12-27 Kazu Hirata + + * m68k-opc.c (m68k_opcodes): Add sleep and trapx. + +2006-12-15 H.J. Lu + + * i386-dis.c (o_mode): New for 16-byte operand. + (intel_operand_size): Generate "OWORD PTR " for o_mode. + (CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode. + +2006-12-14 H.J. Lu + + * i386-dis.c (CMPXCHG8B_Fixup): New. + (grps): Use CMPXCHG8B_Fixup for cmpxchg8b. + +2006-12-11 H.J. Lu + + * i386-dis.c (Eq): Replaced by ... + (Mq): New. This. + (Ma): Defined with OP_M instead of OP_E. + (grps): Updated cmpxchg8b and vmptrst for Eq -> Mq. + (OP_M): Added bound, cmpxchg8b and vmptrst to bad modrm list. + +2006-12-11 Daniel Jacobowitz + + * po/Make-in (.po.gmo): Put gmo files in objdir. + +2006-12-09 H.J. Lu + + * i386-dis.c (X86_64_1): New. + (X86_64_2): Likewise. + (X86_64_3): Likewise. + (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64 + tables. + (x86_64_table): Add entries for 0x60, 0x61 and 0x62. + +2006-12-09 H.J. Lu + + * i386-dis.c: Adjust white spaces. + +2006-12-04 Jan Beulich + + * i386-dis.c (OP_J): Update used_prefixes in v_mode. + +2006-11-30 Jan Beulich + + * i386-dis.c (SEG_Fixup): Delete. + (Sv): Use OP_SEG. + (putop): New suffix character 'D'. + (dis386): Use it. + (grps): Likewise. + (OP_SEG): Handle bytemode other than w_mode. + +2006-11-30 Jan Beulich + + * i386-dis.c (zAX): New. + (Xz): New. + (Yzr): New. + (z_mode): New. + (z_mode_ax_reg): New. + (putop): New suffix character 'G'. + (dis386): Use it for in, out, ins, and outs. + (intel_operand_size): Handle z_mode. + (OP_REG): Delete unreachable case indir_dx_reg. + (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle + z_mode_ax_reg. + (OP_ESreg): Fix Intel syntax operand size handling. + (OP_DSreg): Likewise. + +2006-11-30 Jan Beulich + + * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally. + (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix + used. For 'R' and 'W' suffix, simplify and fix Intel mode. + +2006-11-29 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd. + +2006-11-22 Daniel Jacobowitz + + * arm-dis.c (last_is_thumb): Delete. + (enum map_type, last_type): New. + (print_insn_data): New. + (get_sym_code_type): Take MAP_TYPE argument. Check the type of + the right symbol. Handle $d. + (print_insn): Check for mapping symbols even without a normal + symbol. Adjust searching. If $d is found see how much data + to print. Handle data. + +2006-11-16 Nathan Sidwell + + * m68k-opc.c (m68k_opcodes): Place trap instructions before set + conditionals. Add tpf coldfire instruction as alias for trapf. + +2006-11-09 H.J. Lu + + * i386-dis.c (print_insn): Check PREFIX_REPNZ before + PREFIX_DATA when prefix user table is used. + +2006-11-09 H.J. Lu + + * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ... + (twobyte_uses_DATA_prefix): This. + (twobyte_uses_REPNZ_prefix): New. + (twobyte_uses_REPZ_prefix): Likewise. + (threebyte_0x38_uses_DATA_prefix): Likewise. + (threebyte_0x38_uses_REPNZ_prefix): Likewise. + (threebyte_0x38_uses_REPZ_prefix): Likewise. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (threebyte_0x3a_uses_REPNZ_prefix): Likewise. + (threebyte_0x3a_uses_REPZ_prefix): Likewise. + (print_insn): Updated checking usages of DATA/REPNZ/REPZ + prefixes. + +2006-11-06 Troy Rollo + + * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04. + +2006-11-01 Mei Ligang + + * score-opc.h (score_opcodes): Delete modifier '0x'. + +2006-10-30 Paul Brook + + * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. + (get_sym_code_type): New function. + (print_insn): Search for mapping symbols. + +2006-10-31 Mei Ligang + + * score-dis.c (print_insn): Correct the error code to print + correct PCE instruction disassembly. + +2006-10-26 Ben Elliston + Anton Blanchard + Peter Bergner + + * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, + AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. + (POWER6): Define. + (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", + "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". + Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", + "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", + "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", + "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", + "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", + "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", + "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", + "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", + "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", + "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", + "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", + "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", + "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", + "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", + "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", + "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", + "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", + "diexq" and "diexq." opcodes. + +2006-10-26 Daniel Jacobowitz + + * h8300-dis.c (bfd_h8_disassemble): Add missing consts. + +2006-10-25 Trevor Smigiel + Yukishige Shibata + Nobuhisa Fujinami + Takeaki Fukuoka + Alan Modra + + * spu-dis.c: New file. + * spu-opc.c: New file. + * configure.in: Add SPU support. + * disassemble.c: Likewise. + * Makefile.am: Likewise. Run "make dep-am". + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2006-10-24 Andrew Pinski + + * ppc-opc.c (CELL): New define. + (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx, + cell specific instructions. Add {st,l}x{r,l}{,l} cell specific + VMX instructions. + * ppc-dis.c (powerpc_dialect): Handle cell. + +2006-10-23 Dwarakanath Rajagopal + + * i386-dis.c (dis386): Add support for the change in POPCNT opcode in + amdfam10 architecture. + (PREGRP37): NEW. + (print_insn): Disallow REP prefix for POPCNT. + +2006-10-20 Andrew Stubbs + + * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB + duplicating it. + +2006-10-18 Dave Brolley + + * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch. + * configure: Regenerated. + +2006-09-29 Alan Modra + + * po/POTFILES.in: Regenerate. + +2006-09-26 Mark Shinwell + Joseph Myers + Ian Lance Taylor + Ben Elliston + + * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may + only be used with the default multiply-add operation, so if N is + set, don't bother printing X. Add new iwmmxt instructions. + (IWMMXT_INSN_COUNT): Update. + (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 + with a 'c' suffix. + (print_insn_coprocessor): Check for iWMMXt2. Handle format + specifiers 'r', 'i'. + +2006-09-24 Dwarakanath Rajagopal + + PR binutils/3100 + * i386-dis.c (prefix_user_table): Fix the second operand of + maskmovdqu instruction to allow only %xmm register instead of + both %xmm register and memory. + +2006-09-23 H.J. Lu + + PR binutils/3235 + * i386-dis.c (OP_OFF64): Get 32bit offset if there is an + address size prefix. + +2006-09-17 Mei Ligang + + * score-dis.c: New file. + * score-opc.h: New file. + * Makefile.am: Add Score files. + * Makefile.in: Regenerate. + * configure.in: Add support for Score target. + * configure: Regenerate. + * disassemble.c: Add support for Score target. + +2006-09-16 Nick Clifton + Pedro Alves + + * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ + macros defined in bfd.h. + * cris-dis.c: Likewise. + * h8300-dis.c: Likewise. + * i386-dis.c: Likewise. + * ia64-gen.c: Likewise. + * mips-dis: Likewise. + +2006-09-04 Paul Brook + + * arm-dis.c (neon_opcode): Fix suffix on VMOVN. + +2006-08-23 H.J. Lu + + * i386-dis.c (three_byte_table): Expand to 256 elements. + +2006-08-04 Dwarakanath Rajagopal + + PR binutils/3000 + * i386-dis.c (MXC,EMC): Define. + (OP_MXC): New function to handle cvt* (convert instructions) between + %xmm and %mm register correctly. + (OP_EMC): ditto. + (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi + instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately + with EMC/MXC. + +2006-07-29 Richard Sandiford + + * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire + "fdaddl" entry. + +2006-07-19 Paul Brook + + * armd-dis.c (arm_opcodes): Fix rbit opcode. + +2006-07-18 H.J. Lu + + * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to + "sldt", "str" and "smsw". + +2006-07-15 H.J. Lu + + PR binutils/2829 + * i386-dis.c (GRP11_C6): NEW. + (GRP11_C7): Likewise. + (GRP12): Updated. + (GRP13): Likewise. + (GRP14): Likewise. + (GRP15): Likewise. + (GRP16): Likewise. + (GRPAMD): Likewise. + (GRPPADLCK1): Likewise. + (GRPPADLCK2): Likewise. + (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, + respectively. + (grps): Add entries for GRP11_C6 and GRP11_C7. + +2006-07-10 Dwarakanath Rajagopal + Michael Meissner + + * i386-dis.c (dis386): Add support for 4 operand instructions. Add + support for amdfam10 SSE4a/ABM instructions. Modify all + initializer macros to have additional arguments. Disallow REP + prefix for non-string instructions. + (print_insn): Ditto. + +2006-07-05 Julian Brown + + * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax. + +2006-06-12 H.J. Lu + + * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. + (twobyte_has_modrm): Set 1 for 0x1f. + +2006-06-12 H.J. Lu + + * i386-dis.c (NOP_Fixup): Removed. + (NOP_Fixup1): New. + (NOP_Fixup2): Likewise. + (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90. + +2006-06-12 Julian Brown + + * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed + on 64-bit hosts. + +2006-06-10 H.J. Lu + + * i386.c (GRP10): Renamed to ... + (GRP12): This. + (GRP11): Renamed to ... + (GRP13): This. + (GRP12): Renamed to ... + (GRP14): This. + (GRP13): Renamed to ... + (GRP15): This. + (GRP14): Renamed to ... + (GRP16): This. + (dis386_twobyte): Updated. + (grps): Likewise. + +2006-06-09 Nick Clifton + + * po/fi.po: Updated Finnish translation. + +2006-06-07 Joseph S. Myers + + * po/Make-in (pdf, ps): New dummy targets. + +2006-06-06 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm + instructions. + (neon_opcodes): Add conditional execution specifiers. + (thumb_opcodes): Ditto. + (thumb32_opcodes): Ditto. + (arm_conditional): Change 0xe to "al" and add "" to end. + (ifthen_state, ifthen_next_state, ifthen_address): New. + (IFTHEN_COND): Define. + (print_insn_coprocessor, print_insn_neon): Print thumb conditions. + (print_insn_arm): Change %c to use new values of arm_conditional. + (print_insn_thumb16): Print thumb conditions. Add %I. + (print_insn_thumb32): Print thumb conditions. + (find_ifthen_state): New function. + (print_insn): Track IT block state. + +2006-06-06 Ben Elliston + Anton Blanchard + Peter Bergner + + * ppc-dis.c (powerpc_dialect): Handle power6 option. + (print_ppc_disassembler_options): Mention power6. + +2006-06-06 Thiemo Seufer + Chao-ying Fu + + * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. + * mips-opc.c: Add DSP64 instructions. + +2006-06-06 Alan Modra + + * m68hc11-dis.c (print_insn): Warning fix. + +2006-06-05 Daniel Jacobowitz + + * po/Make-in (top_builddir): Define. + +2006-06-05 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * config.in: Regenerate. + +2006-05-31 Daniel Jacobowitz + + * Makefile.am (INCLUDES): Use @INCINTL@. + * acinclude.m4: Include new gettext macros. + * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. + Remove local code for po/Makefile. + * Makefile.in, aclocal.m4, configure: Regenerated. + +2006-05-30 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2006-05-25 Richard Sandiford + + * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd + and fmovem entries. Put register list entries before immediate + mask entries. Use "l" rather than "L" in the fmovem entries. + * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it + out from INFO. + (m68k_scan_mask): New function, split out from... + (print_insn_m68k): ...here. If no architecture has been set, + first try printing an m680x0 instruction, then try a Coldfire one. + +2006-05-24 Nick Clifton + + * po/ga.po: Updated Irish translation. + +2006-05-22 Nick Clifton + + * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. + +2006-05-22 Nick Clifton + + * po/nl.po: Updated translation. + +2006-05-18 Alan Modra + + * avr-dis.c: Formatting fix. + +2006-05-14 Thiemo Seufer + + * mips16-opc.c (I1, I32, I64): New shortcut defines. + (mips16_opcodes): Change membership of instructions to their + lowest baseline ISA. + +2006-05-09 H.J. Lu + + * i386-dis.c (grps): Update sgdt/sidt for 64bit. + +2006-05-05 Julian Brown + + * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as + vldm/vstm. + +2006-05-05 Thiemo Seufer + David Ung + + * mips-opc.c: Add macro for cache instruction. + +2006-05-04 Thiemo Seufer + Nigel Stephens + David Ung + + * mips-dis.c (mips_arch_choices): Add smartmips instruction + decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release + 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to + MIPS64R2. + * mips-opc.c: fix random typos in comments. + (INSN_SMARTMIPS): New defines. + (mips_builtin_opcodes): Add paired single support for MIPS32R2. + Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, + flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the + FP_S and FP_D flags to denote single and double register + accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. + Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 + for MIPS32R2. Add SmartMIPS instructions. Add two-argument + variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to + release 2 ISAs. + * mips16-opc.c (mips16_opcodes): Add sdbbp instruction. + +2006-05-03 Thiemo Seufer + + * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. + +2006-05-02 Thiemo Seufer + Nigel Stephens + David Ung + + * mips-dis.c (print_insn_args): Force mips16 to odd addresses. + (print_mips16_insn_arg): Force mips16 to odd addresses. + +2006-04-30 Thiemo Seufer + David Ung + + * mips-opc.c (mips_builtin_opcodes): Add udi instructions + "udi0" to "udi15". + * mips-dis.c (print_insn_args): Adds udi argument handling. + +2006-04-28 James E Wilson + + * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing + error message. + +2006-04-28 Thiemo Seufer + David Ung + Nigel Stephens + + * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register + names. + +2006-04-28 Thiemo Seufer + Nigel Stephens + David Ung + + * mips-dis.c (print_insn_args): Add mips_opcode argument. + (print_insn_mips): Adjust print_insn_args call. + +2006-04-28 Thiemo Seufer + Nigel Stephens + + * mips-dis.c (print_insn_args): Print $fcc only for FP + instructions, use $cc elsewise. + +2006-04-28 Thiemo Seufer + Nigel Stephens + + * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): + Map MIPS16 registers to O32 names. + (print_mips16_insn_arg): Use mips16_reg_names. + +2006-04-26 Julian Brown + + * arm-dis.c (print_insn_neon): Disassemble floating-point constant + VMOV. + +2006-04-26 Nathan Sidwell + Julian Brown + + * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert + %[zy] into %[zy]. Expand meaning of %['`?]. + Add unified load/store instruction names. + (neon_opcode_table): New. + (arm_opcodes): Expand meaning of %['`?]. + (arm_decode_bitfield): New. + (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. + Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. + (print_insn_neon): New. + (print_insn_arm): Adjust print_insn_coprocessor call. Call + print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. + (print_insn_thumb32): Likewise. + +2006-04-19 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2006-04-19 Alan Modra + + * avr-dis.c (avr_operand): Warning fix. + + * configure: Regenerate. + +2006-04-16 Daniel Jacobowitz + + * po/POTFILES.in: Regenerated. + +2006-04-12 Hochstein + + PR binutils/2454 + * avr-dis.c (avr_operand): Arrange for a comment to appear before + the symolic form of an address, so that the output of objdump -d + can be reassembled. + +2006-04-10 DJ Delorie + + * m32c-asm.c: Regenerate. + +2006-04-06 Carlos O'Donell + + * Makefile.am: Add install-html target. + * Makefile.in: Regenerate. + +2006-04-06 Nick Clifton + + * po/vi/po: Updated Vietnamese translation. + +2006-03-31 Paul Koning + + * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. + +2006-03-16 Bernd Schmidt + + * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the + logic to identify halfword shifts. + +2006-03-16 Paul Brook + + * arm-dis.c (arm_opcodes): Rename swi to svc. + (thumb_opcodes): Ditto. + +2006-03-13 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Likewise. + * m32c-desc.h: Likewise. + * m32c-dis.c: Likewise. + * m32c-ibld.c: Likewise. + * m32c-opc.c: Likewise. + * m32c-opc.h: Likewise. + +2006-03-10 DJ Delorie + + * m32c-desc.c: Regenerate with mul.l, mulu.l. + * m32c-opc.c: Likewise. + * m32c-opc.h: Likewise. + + +2006-03-09 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2006-03-07 H.J. Lu + + PR binutils/2428 + * i386-dis.c (REP_Fixup): New function. + (AL): Remove duplicate. + (Xbr): New. + (Xvr): Likewise. + (Ybr): Likewise. + (Yvr): Likewise. + (indirDXr): Likewise. + (ALr): Likewise. + (eAXr): Likewise. + (dis386): Updated entries of ins, outs, movs, lods and stos. + +2006-03-05 Nick Clifton + + * cgen-ibld.in (insert_normal): Cope with attempts to insert a + signed 32-bit value into an unsigned 32-bit field when the host is + a 64-bit machine. + * fr30-ibld.c: Regenerate. + * frv-ibld.c: Regenerate. + * ip2k-ibld.c: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * xc16x-ibld.c: Regenerate. + * xstormy16-ibld.c: Regenerate. + +2006-03-03 Shrirang Khisti + + * po/Make-in: Add html target. + +2006-02-27 H.J. Lu + + * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by + Intel Merom New Instructions. + (THREE_BYTE_0): Likewise. + (THREE_BYTE_1): Likewise. + (three_byte_table): Likewise. + (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use + THREE_BYTE_1 for entry 0x3a. + (twobyte_has_modrm): Updated. + (twobyte_uses_SSE_prefix): Likewise. + (print_insn): Handle 3-byte opcodes used by Intel Merom New + Instructions. + +2006-02-24 David S. Miller + + * sparc-dis.c (v9_priv_reg_names): Add "gl" entry. + (v9_hpriv_reg_names): New table. + (print_insn_sparc): Allow values up to 16 for '?' and '!'. + New cases '$' and '%' for read/write hyperprivileged register. + * sparc-opc.c (sparc_opcodes): Add new entries for UA2005 + window handling and rdhpr/wrhpr instructions. + +2006-02-24 DJ Delorie + + * m32c-desc.c: Regenerate with linker relaxation attributes. + * m32c-desc.h: Likewise. + * m32c-dis.c: Likewise. + * m32c-opc.c: Likewise. + +2006-02-24 Paul Brook + + * arm-dis.c (arm_opcodes): Add V7 instructions. + (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. + (print_arm_address): New function. + (print_insn_arm): Use it. Add 'P' and 'U' cases. + (psr_name): New function. + (print_insn_thumb32): Add 'U', 'C' and 'D' cases. + +2006-02-23 H.J. Lu + + * ia64-opc-i.c (bXc): New. + (mXc): Likewise. + (OpX2TaTbYaXcC): Likewise. + (TF). Likewise. + (TFCM). Likewise. + (ia64_opcodes_i): Add instructions for tf. + + * ia64-opc.h (IMMU5b): New. + + * ia64-asmtab.c: Regenerated. + +2006-02-23 H.J. Lu + + * ia64-gen.c: Update copyright years. + * ia64-opc-b.c: Likewise. + +2006-02-22 H.J. Lu + + * ia64-gen.c (lookup_regindex): Handle ".vm". + (print_dependency_table): Handle '\"'. + + * ia64-ic.tbl: Updated from SDM 2.2. + * ia64-raw.tbl: Likewise. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerated. + + * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1. + +2006-02-17 Shrirang Khisti + Anil Paranjape + Shilin Shakti + + * xc16x-desc.h: New file + * xc16x-desc.c: New file + * xc16x-opc.h: New file + * xc16x-opc.c: New file + * xc16x-ibld.c: New file + * xc16x-asm.c: New file + * xc16x-dis.c: New file + * Makefile.am: Entries for xc16x + * Makefile.in: Regenerate + * cofigure.in: Add xc16x target information. + * configure: Regenerate. + * disassemble.c: Add xc16x target information. + +2006-02-11 H.J. Lu + + * i386-dis.c (dis386_twobyte): Use "movZ" for debug register + moves. + +2006-02-11 H.J. Lu + + * i386-dis.c ('Z'): Add a new macro. + (dis386_twobyte): Use "movZ" for control register moves. + +2006-02-10 Nick Clifton + + * iq2000-asm.c: Regenerate. + +2006-02-07 Nathan Sidwell + + * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. + +2006-01-26 David Ung + + * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, + ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, + floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, + nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, + rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s. + +2006-01-18 Arnold Metselaar + + * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d, + ld_d_r, pref_xd_cb): Use signed char to hold data to be + disassembled. + * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes + buffer overflows when disassembling instructions like + ld (ix+123),0x23 + * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed + operand, if the offset is negative. + +2006-01-17 Arnold Metselaar + + * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use + unsigned char to hold data to be disassembled. + +2006-01-17 Andreas Schwab + + PR binutils/1486 + * disassemble.c (disassemble_init_for_target): Set + disassembler_needs_relocs for bfd_arch_arm. + +2006-01-16 Paul Brook + + * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss, + f?add?, and f?sub? instructions. + +2006-01-16 Nick Clifton + + * po/zh_CN.po: New Chinese (simplified) translation. + * configure.in (ALL_LINGUAS): Add "zh_CH". + * configure: Regenerate. + +2006-01-05 Paul Brook + + * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry. + +2006-01-06 DJ Delorie + + * m32c-desc.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2006-01-03 DJ Delorie + + * cgen-ibld.in (extract_normal): Avoid memory range errors. + * m32c-ibld.c: Regenerated. + +For older changes see ChangeLog-2005 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2007 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2007 new file mode 100644 index 000000000000..21fb65c3b359 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2007 @@ -0,0 +1,1863 @@ +2007-12-31 H.J. Lu + + * i386-dis.c (prefix_table): Use "%LQ" on cvtsi2ss/cvtsi2sd. + (putop): Handle '%' and "LQ". + + * i386-opc.tbl: Remove IgnoreSize from cvtsi2ss/cvtsi2sd. + * i386-tbl.h: Regenerated. + +2007-12-28 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuSSE4_1_Or_5 to + CPU_SSE4_1_FLAGS, CPU_SSE4_2_FLAGS and CPU_SSE5_FLAGS. + (cpu_flags): Add CpuSSE4_1_Or_5. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + + * i386-opc.h (CpuSSE4_1_Or_5): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpusse4_1_or_5. + + * i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1|CpuSSE5 + on ptest, roundpd, roundps, roundsd and roundss. + +2007-12-23 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and + IntelMnemonic. + + * i386-opc.h (OldGcc): New. + (ATTMnemonic): Likewise. + (IntelMnemonic): Likewise. + (Opcode_Modifier_Max): Updated. + (i386_opcode_modifier): Add oldgcc, attmnemonic and + intelmnemonic. + + * i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul, + fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and + IntelMnemonic. + * i386-tbl.h: Regeneratd. + +2007-12-22 H.J. Lu + + * i386-dis.c (intel_mnemonic): New. + (print_i386_disassembler_options): Display att-mnemonic and + intel-mnemonic options. + (print_insn): Handle att-mnemonic and intel-mnemonic. + (float_reg): Replace SYSV386_COMPAT with "!M" and "M". + (putop): Handle "!M" and "M". + +2007-12-21 H.J. Lu + + * Makefile.am (i386-gen.o): Also depend on + $(srcdir)/../include/opcode/i386.h. + * Makefile.in: Regenerated. + +2007-11-29 Mark Shinwell + + * mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F + entries. + * mips-opc.c (IL2E): New. + (IL2F): New. + (mips_builtin_opcodes): Add Loongson-2E and -2F instructions. + Allow movz and movn for Loongson-2E and -2F. Add movnz entry. + Move coprocessor encodings to the end of the table. Allow + certain MIPS V .ps instructions on the Loongson-2E and -2F. + +2007-11-29 Mark Shinwell + + * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New. + (mips_builtin_opcodes): Use these new I* values. + +2007-11-27 Andreas Krebbel + + * s390-opc.txt ("tcet", "tcdt", "tcxt", "tget", "tgdt", + "tgxt"): Removed. + ("tdcet", "tdcdt", "tdcxt", "tdget", "tdgdt", "tdgxt"): Added. + +2007-11-14 H.J. Lu + + * ia64-ic.tbl: Updated for Itanium 9100 series. + * ia64-raw.tbl: Likewise. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerated. + +2007-11-14 Tristan Gingold + + * ia64-dis.c (print_insn_ia64): Handle ar.ruc. + * ia64-gen.c (lookup_regindex): Likewise. + +2007-11-07 Jens Arnold + + PR gas/5228 + * m68k-opc.c (m68k_opcodes): Fix coldfire msac.w instructions with + parallel loads. + +2007-11-07 Tristan Gingold + + * ia64-dis.c (print_insn_ia64): Generate symbolic names for cr + registers instead of register number. + +2007-11-07 David O'Brien + + * arm-dis.c (arm_opcodes): Remove superflous escapes of percent + operators. + +2007-11-06 Peter Bergner + + * ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. opcodes + which are not included in the "Preliminary Decimal Floating-Point + Architecture" document. + +2007-11-01 H.J. Lu + + * i386-gen.c (opcode_modifiers): Replace No_xSuf with + No_ldSuf. + * i386-opc.tbl: Likewise. + + * i386-opc.h (No_xSuf): Renamed to ... + (No_ldSuf): This. + (FWait): Updated. + +2007-11-01 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword, + ToQword and AddrPrefixOp0. + + * i386-opc.h (ByteOkIntel): New. + (ToDword): Likewise. + (ToQword): Likewise. + (AddrPrefixOp0): Likewise. + (IsPrefix): Updated. + (i386_opcode_modifier): Add byteokintel, todword, toqword + and addrprefixop0. + + * i386-opc.tbl (cvtss2si): Add ToQword. + (cvttss2si): Likewise. + (cvtsd2si): Add ToDword. + (cvttsd2si): Likewise. + (monitor): Add AddrPrefixOp0. + (invlpga): Likewise. + (vmload): Likewise. + (vmrun): Likewise. + (vmsave): Likewise. + (pextrb): Add ByteOkIntel. + (pinsrb): Likewise. + * i386-tbl.h: Regenerated. + +2007-10-31 H.J. Lu + + * i386-dis.c (USE_REG_TABLE): Defined as the previous one + 1. + (USE_REG_TABLE): Likewise. + (USE_MOD_TABLE): Likewise. + (USE_RM_TABLE): Likewise. + (USE_PREFIX_TABLE): Likewise. + (USE_X86_64_TABLE): Likewise. + (USE_3BYTE_TABLE): Likewise. + +2007-10-26 H.J. Lu + + * i386-dis.c (MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3): New. + (MOD_0F51): Likewise. + (MOD_0FD7): Likewise. + (MOD_0FE7_PREFIX_2): Likewise. + (MOD_0F382A_PREFIX_2): Likewise. + (MOD_0F71_REG_2): Updated. + (MOD_0FF0_PREFIX_3): Likewise. + (MOD_62_32BIT): Likewise. + (dis386_twobyte): Use MOD_0F51 and MOD_0FD7. + (prefix_table): Use MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3, + MOD_0FE7_PREFIX_2 and MOD_0F382A_PREFIX_2. + (mod_table): Add MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3, + MOD_0F51, MOD_0FD7 and MOD_0F382A_PREFIX_2. + +2007-10-26 Nick Clifton + + * arm-dis.c (print_insn): Check for a symtab that exists but is + empty. + +2007-10-24 Alan Modra + + * po/POTFILES.in: Regenerate. + +2007-10-23 H.J. Lu + + * i386-dis.c (OP_SIMD_Suffix): Renamed to ... + (CMP_Fixup): This. Rewrite. + (OPSIMD): Renamed to ... + (CMP): This. Updated. + (prefix_table): Update PREFIX_0FC2 entry. + +2007-10-22 H.J. Lu + + * i386-dis.c (prefix_table): Reordered by opcode. + (mod_table): Likewise. + +2007-10-19 H.J. Lu + + * i386-dis.c (prefix_table): Use XS on psrldq and pslldq. + +2007-10-17 Nathan Sidwell + + * m68k-opc.c (m68k_opcodes): Correct move sr and ccr masks for + coldfire. + +2007-10-15 Peter Bergner + + * ppc-opc.c (powerpc_opcodes): Fix the first two operands of + dquaiq. to use the TE and FRT macros. + +2007-10-15 Peter Bergner + + * ppc-opc.c (TE): Correct signedness. + (powerpc_opcodes): Sort psq_st and psq_stu according to major + opcode number. + +2007-10-15 H.J. Lu + + * i386-dis.c (dis386_twobyte): Reformat. + (prefix_table): Likewise. + (three_byte_table): Likewise. + +2007-10-15 Alan Modra + + * mcore-dis.c (print_insn_mcore): Protect "fprintf" var against + macro expansion. + +2007-10-12 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add FirstXmm0. + + * i386-opc.h (FirstXmm0): New. + (IsPrefix): Updated. + (i386_opcode_modifier): Add firstxmm0. + + * i386-opc.tbl (blendvpd): Replace RegKludge with FirstXmm0. + (blendvps): Likewise. + (pblendvb): Likewise. + * i386-tbl.h: Regenerated. + +2007-10-12 H.J. Lu + + * i386-dis.c (prefix_table): Reformat pblendvb and blendvps. + +2007-10-10 H.J. Lu + + * i386-dis.c (v_mode): Defined as previous one + 1. + (w_mode): Likewise. + (d_mode): Likewise. + (q_mode): Likewise. + (t_mode): Likewise. + (x_mode): Likewise. + (m_mode): Likewise. + (cond_jump_mode): Likewise. + (loop_jcxz_mode): Likewise. + (dq_mode): Likewise. + (dqw_mode): Likewise. + (f_mode): Likewise. + (const_1_mode): Likewise. + (stack_v_mode): Likewise. + (z_mode): Likewise. + (o_mode): Likewise. + (dqb_mode): Likewise. + (dqd_mode): Likewise. + (es_reg): Likewise. + (cs_reg): Likewise. + (ss_reg): Likewise. + (ds_reg): Likewise. + (fs_reg): Likewise. + (gs_reg): Likewise. + (eAX_reg): Likewise. + (eCX_reg): Likewise. + (eDX_reg): Likewise. + (eBX_reg): Likewise. + (eSP_reg): Likewise. + (eBP_reg): Likewise. + (eSI_reg): Likewise. + (eDI_reg): Likewise. + (al_reg): Likewise. + (cl_reg): Likewise. + (dl_reg): Likewise. + (bl_reg): Likewise. + (ah_reg): Likewise. + (ch_reg): Likewise. + (dh_reg): Likewise. + (bh_reg): Likewise. + (ax_reg): Likewise. + (cx_reg): Likewise. + (dx_reg): Likewise. + (bx_reg): Likewise. + (sp_reg): Likewise. + (bp_reg): Likewise. + (si_reg): Likewise. + (di_reg): Likewise. + (rAX_reg): Likewise. + (rCX_reg): Likewise. + (rDX_reg): Likewise. + (rBX_reg): Likewise. + (rSP_reg): Likewise. + (rBP_reg): Likewise. + (rSI_reg): Likewise. + (rDI_reg): Likewise. + (z_mode_ax_reg): Likewise. + (indir_dx_reg): Likewise. + (DREX_OC1): Updated. + (DREX_NO_OC0): Likewise. + (DREX_MASK): Likewise. + (MAX_BYTEMODE): New. Issue an error if MAX_BYTEMODE is not + less than DREX_OC1. + +2007-10-08 H.J. Lu + + * i386-dis.c: Updated comments for 'Y'. + (putop): Don't add 'q' for 'Y' if suffix_always isn't true. + +2007-10-08 Maciej W. Rozycki + + * opcodes/mips-dis.c (mips_cp0_names_r3000): New definition. + (mips_cp0_names_r4000): Likewise. + (mips_arch_choices): Link to the above as appropriate. + +2007-10-08 Nick Clifton + + * configure.in (SHARED_DEPENDENCIES): Change non-cygwin dependency + to be ../bfd/libbfd.la. + * configure: Regenerate. + +2007-10-05 H.J. Lu + + * i386-dis.c (dis386_twobyte): Add getsec. + + * i386-gen.c (cpu_flags): Add CpuSMX. + + * i386-opc.h (CpuSMX): New. + (CpuSSSE3): Updated. + (i386_cpu_flags): Add cpusmx. + + * i386-opc.tbl: Add getsec. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2007-10-05 H.J. Lu + + * i386-dis.c (reg_table): Use "{ XX }" on "(bad)". + (prefix_table): Likewise. + +2007-10-04 H.J. Lu + + * i386-dis.c (dis386_twobyte): Use EXx instead of EXq on + unpckhpX and unpckhpX. + +2007-10-04 David Daney + + * mips-opc.c (mips_builtin_opcodes): Mark lwxc1 as working on FP_S + registers. + +2007-10-04 H.J. Lu + + * i386-dis.c (MOD_0F12_PREFIX_0): Use "movlps" and "movhlps" + instead of "movlpX" and "movhlpX", respectively. + (MOD_0F16_PREFIX_0): Use "movhps" and "movlhps" instead of + "movhpX" and "movlhpX", respectively. + +2007-10-04 Nick Clifton + + * configure.in (WIN32LDFLAGS): Rename to SHARED_LDFLAGS. + (WIN32LIBADD): Rename to SHARED_LIBADD + (SHARED_DEPENDENCIES): New exported variable. + (enable_shared): Add dependency upon libbfd.la for non-cygwin + based shared library builds. + * Makefile.am (libopcodes_la_DEPENDENCIES): Append + SHARED_DEPENDENCIES. + (libopcodes_la_LIBADD): Rename WIN32LIBADD to SHARED_LIBADD. + (libopcodes_la_LDFLAGS): Rename WIN32LDFLAGS to SHARED_LDFLAGS. + * configure: Regenerate. + * Makefile.in: Regenerate. + + PR gas/5100 + * arc-opc.c (insert_offset): Fix spelling mistake in error + message. + +2007-10-03 H.J. Lu + + * i386-dis.c (OP_REG): Set add to 0 only when needed. + (OP_C): Likewise. + (OP_D): Likewise. + (OP_MMX): Likewise. + (OP_XMM): Likewise. + (OP_EM): Likewise. + (OP_MXC): Likewise. + (OP_EX): Likewise. + +2007-10-03 H.J. Lu + + * i386-opc.tbl: Update SSE comments. + +2007-10-01 H.J. Lu + + * i386-dis.c (THREE_BYTE_0FBA): Renamed to ... + (THREE_BYTE_0F7B): This. + (dis386_twobyte): Updated. + (three_byte_table): Updated comments. + +2007-10-01 M R Swami Reddy + + * cr16-opc.c: Updated the branch on condition instructions with + RELAXABLE flag. + +2007-09-30 H.J. Lu + + * 386-dis.c (prefix_table): Reformat comment. + +2007-09-29 H.J. Lu + + * 386-dis.c (USE_GROUPS): Renamed to ... + (USE_REG_TABLE): This. + (USE_OPC_EXT_TABLE): Renamed to ... + (USE_MOD_TABLE): This. + (USE_OPC_EXT_RM_TABLE): Renamed to ... + (USE_RM_TABLE): This. + (USE_XXX_TABLE): Reordered. + (GRP): Renamed to ... + (REG_TABLE): This. + (OPC_EXT_TABLE): Renamed to ... + (MOD_TABLE): This. + (OPC_EXT_RM_TABLE): Renamed to ... + (RM_TABLE): This. + (GRP_XXX): Renamed to ... + (REG_XXX): This. + (PREGRP_XXX): Renamed to ... + (PREFIX_XXX): This. + (OPC_EXT_XXX): Renamed to ... + (MOD_XXX): This. + (OPC_EXT_RM_XXX): Renamed to ... + (RM_XXX): This. + (grps): Renamed to ... + (reg_table): This + (prefix_user_table): Renamed to ... + (prefix_table): This + (opc_ext_table): Renamed to ... + (mod_table): This + (opc_ext_rm_table): Renamed to ... + (rm_table): This + (OPC_EXT_RM_XXX): Likewise. + (dis386): Updated. + (dis386_twobyte): Likewise. + (reg_table): Likewise. + (prefix_table): Likewise. + (x86_64_table): Likewise. + (three_byte_table): Likewise. + (mod_table): Likewise. + (rm_table): Likewise. + (get_valid_dis386): Likewise. + +2007-09-28 H.J. Lu + + * 386-dis.c (USE_PREFIX_USER_TABLE): Renamed to ... + (USE_PREFIX_TABLE): This. + (X86_64_SPECIAL): Renamed to ... + (USE_X86_64_TABLE): This. + (IS_3BYTE_OPCODE): Renamed to ... + (USE_3BYTE_TABLE): This. + (GRPXXX): Removed. + (PREGRPXXX): Likewise. + (X86_64_XXX): Likewise. + (THREE_BYTE_XXX): Likewise. + (OPC_EXT_XXX): Likewise. + (OPC_EXT_RM_XXX): Likewise. + (DIS386): New. + (GRP): Likewise. + (PREGRP): Likewise. + (X86_64_TABLE): Likewise. + (THREE_BYTE_TABLE): Likewise. + (OPC_EXT_TABLE): Likewise. + (OPC_EXT_RM_TABLE): Likewise. + (GRP_XXX): Likewise. + (PREGRP_XXX): Likewise. + (X86_64_XXX): Likewise. + (THREE_BYTE_XXX): Likewise. + (OPC_EXT_XXX): Likewise. + (OPC_EXT_RM_XXX): Likewise. + (dis386): Updated. + (dis386_twobyte): Likewise. + (grps): Likewise. + (prefix_user_table): Likewise. + (x86_64_table): Likewise. + (three_byte_table): Likewise. + (opc_ext_table): Likewise. + (opc_ext_rm_table): Likewise. + (get_valid_dis386): Likewise. + +2007-09-27 H.J. Lu + + * i386-dis.c (dis386): Swap X86_64_27 with OPC_EXT_2. + (x86_64_table): Likewise. + (opc_ext_table): Likewise. + +2007-09-27 H.J. Lu + + PR binutils/5072 + * i386-dis.c: Update comments on '{', '}' and '|' to support + only AT&T and Intel modes. + (X86_64_4...X86_64_27): New. + (dis386): Updated. Use X86_64_4...X86_64_21. + (dis386_twobyte): Updated. + (float_mem): Likewise. + (x86_64_table): Add X86_64_4...X86_64_27. + (opc_ext_table): Updated. Use X86_64_22...X86_64_27. + (putop): Updated handling of '{', '}' and '|' to support only + AT&T and Intel modes. + +2007-09-27 Kazu Hirata + + * m68k-dis.c (print_insn_arg): Use %mbo instead of %mbb. + +2007-09-26 James E. Wilson + + * ia64-gen.c (print_dependency_table): Fix typo in last patch. + +2007-09-26 Nick Clifton + + * mt-asm.c (parse_imm16): Reword error message in order to allow + it to be translated properly. + * ia64-gen.c (print_dependency_table): Likewise. + * mips-dis.c (print_insn_args): Likewise. + +2007-09-26 Jan Beulich + + * i386-dis.c (OP_E_extended): Distinguish rip- and eip- + relative addressing. Update used_prefixes based on whether any + base or index register was printed. + +2007-09-26 Jan Beulich + + * i386-opc.h (RegEip): Define. + (RegEiz): Adjust. + * i386-reg.tbl: Add eip. Mark rip and eip with RegRex64. + * i386-tbl.h: Re-generate. + +2007-09-25 H.J. Lu + + * i386-gen.c (process_i386_opcodes): Process opcode_length. + + * i386-opc.h (template): Add opcode_length. + * 386-opc.tbl: Likewise. + * i386-tbl.h: Regenerated. + +2007-09-21 H.J. Lu + + * i386-opc.h: Adjust whitespaces. + +2007-09-21 Dave Brolley + + * mep-desc.c: Regenerated. + +2007-09-20 H.J. Lu + + * i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset]. + +2007-09-20 H.J. Lu + + PR 658 + * 386-dis.c (index64): New. + (index32): Likewise. + (intel_index64): Likewise. + (intel_index32): Likewise. + (att_index64): Likewise. + (att_index32): Likewise. + (print_insn): Set index64 and index32. + (OP_E_extended): Use index64/index32 for index register for + SIB with INDEX == 4. + + * i386-opc.h (RegEiz): New. + (RegRiz): Likewise. + + * i386-reg.tbl: Add eiz and riz. + * i386-tbl.h: Regenerated. + +2007-09-19 H.J. Lu + + * i386-dis.c (OP_E_extended): Always display scale for memory. + +2007-09-17 H.J. Lu + + * i386-opc.h (RegRip): New. + + * i386-reg.tbl (rip): Use RegRip for reg_num. + * i386-tbl.h: Regenerated. + +2007-09-17 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2007-09-14 H.J. Lu + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2007-09-14 Michael Meissner + Dwarakanath Rajagopal + Tony Linthicum + + * i386-opc.h (CpuSSE5): New macro. + (i386_cpu_flags): Add Drex, Drexv and Drexc. + + * i386-gen.c (cpu_flag_init): Add CPU_SSE5_FLAGS. + (operand_type_init): Add CpuSSE5. + (opcode_modifiers): Add Drex, Drexv and Drexc. + (i386_opcode_modifier): Ditto. + + * i386-opc.tbl (fmaddps,fmaddpd,fmaddss,fmaddsd): Define SSE5 + instructions here. + (fmsubps,fmsubpd,fmsubss,fmsubsd): Ditto. + (fnmaddps,fnmaddpd,fnmaddss,fnmaddsd): Ditto. + (fnmsubps,fnmsubpd,fnmsubss,fnmsubsd): Ditto. + (pmacssww,pmacsww,pmacsswd,pmacswd): Ditto. + (pmacssdd,pmacsdd,pmacssdql,pmacssdqh): Ditto. + (pmacsdql,pmacsdqh,pmadcsswd,pmadcswd): Ditto. + (phaddbw,phaddbd,phaddbq,phaddwd): Ditto. + (phaddwq,phadddq,phaddubw,phaddubd): Ditto. + (phaddubq,phadduwd,phadduwq,phaddudq): Ditto. + (phsubbw,phsubwd,phsubdq): Ditto. + (pcmov,pperm,permps,permpd): Ditto. + (protb,protw,protd,protq): Ditto. + (pshlb,pshlw,pshld,pshlq): Ditto. + (pshab,pshaw,pshad,pshaq): Ditto. + (comps,comeqps,comltps,comungeps,comleps,comungtps): Ditto. + (comunordps,comneps,comneqps,comnltps,comugeps): Ditto. + (comnleps,comugtps,comordps,comueqps,comultps): Ditto. + (comngeps,comuleps,comngtps,comfalseps,comuneps): Ditto. + (comuneqps,comunltps,comgeps,comunleps,comgtps,comtrueps): Ditto. + (compd,comeqpd,comltpd,comungepd,comlepd,comungtpd,comunordpd): Ditto. + (comnepd,comneqpd,comnltpd,comugepd,comnlepd,comugtpd): Ditto. + (comordpd,comueqpd,comultpd,comngepd,comulepd,comngtpd): Ditto. + (comfalsepd,comunepd,comuneqpd,comunltpd,comgepd): Ditto. + (comunlepd,comgtpd,comtruepd): Ditto. + (comss,comeqss,comltss,comungess,comless,comungtss,comunordss): Ditto. + (comness,comneqss,comnltss,comugess,comnless,comugtss): Ditto. + (comordss,comueqss,comultss,comngess,comuless,comngtss): Ditto. + (comfalsess,comuness,comuneqss,comunltss,comgess): Ditto. + (comunless,comgtss,comtruess): Ditto. + (comsd,comeqsd,comltsd,comungesd,comlesd,comungtsd,comunordsd): Ditto. + (comnesd,comneqsd,comnltsd,comugesd,comnlesd,comugtsd): Ditto. + (comordsd,comueqsd,comultsd,comngesd,comulesd,comngtsd): Ditto. + (comfalsesd,comunesd,comuneqsd,comunltsd,comgesd): Ditto. + (comunlesd,comgtsd,comtruesd): Ditto. + (pcomub,pcomltub,pcomleub,pcomgtub,pcomgeub,pcomequb): Ditto. + (pcomnequb,pcomneub): Ditto. + (pcomuw,pcomltuw,pcomleuw,pcomgtuw,pcomgeuw,pcomequw): Ditto. + (pcomnequw,pcomneuw): Ditto. + (pcomud,pcomltud,pcomleud,pcomgtud,pcomgeud,pcomequd): Ditto. + (pcomnequd,pcomneud): Ditto. + (pcomuq,pcomltuq,pcomleuq,pcomgtuq,pcomgeuq,pcomequq): Ditto. + (pcomnequq,pcomneuq): Ditto. + (pcomb,pcomltb,pcomleb,pcomgtb,pcomgeb,pcomeqb): Ditto. + (pcomneqb,pcomneb): Ditto. + (pcomw,pcomltw,pcomlew,pcomgtw,pcomgew,pcomeqw): Ditto. + (pcomneqw,pcomnew): Ditto. + (pcomd,pcomltd,pcomled,pcomgtd,pcomged,pcomeqd): Ditto. + (pcomneqd,pcomned): Ditto. + (pcomq,pcomltq,pcomleq,pcomgtq,pcomgeq): Ditto. + (pcomeqq,pcomneqq,pcomneq): Ditto. + (pcomtrueb, pcomtruew, pcomtrued, pcomtrueq): Ditto. + (pcomtrueub, pcomtrueuw, pcomtrueud, pcomtrueuq): Ditto. + (pcomfalseb, pcomfalsew, pcomfalsed, pcomfalseq): Ditto. + (pcomfalseub, pcomfalseuw, pcomfalseud, pcomfalseuq): Ditto. + (frczps,frczpd,frczss,frczsd): Ditto. + (cvtph2ps,cvtps2ph): Ditto. + + * i386-tbl.h: Regenerate from i386-opc.tbl. + * i386-init.h: Likewise. + + * i386-dis.c (libiberty.h): Include to get ARRAY_SIZE. + (dis386_move_test): New disassembly support for move from test + register instruction that overlaps with SSE5 instructions. + (print_insn): Add support for special casing the i386/i486 move + from test register instruction that overlaps with the SSE5 + 0x0f24 4 operand instructions. + (OP_DREX_ICMP): New macros for SSE5 DREX handling. + (OP_DREX_FCMP): Ditto. + (OP_E_extended): Rename from OP_E, add additional argument to skip + the DREX byte. + (OP_E): Call OP_E_extended. + (DREX_REG_MEMORY): New macros for drex handling. + (DREX_REG_UNKNOWN): Ditto. + (DREX4_OC1): Ditto. + (DREX4_NO_OC0): Ditto. + (DREX4_MASK): Ditto. + (three_byte_table): Add SSE5 instructions. + (print_drex_arg): New function to print a DREX register or memory + reference. + (OP_DREX4): New function for handling DREX 4 argument ops. + (OP_DREX3): New function for handling DREX 3 argument ops. + (twobyte_has_modrm): 0f{25,7a,7b} all use the modrm byte. + (THREE_BYTE_SSE5_0F{24,25,7A,7B}): New macros for initializing 3 + byte opcode support for SSE5 instructions. + (dis386_twobyte): Add SSE5 24/25/7a/7b support. + (three_byte_table): Add rows for describing SSE5 instructions. + +2007-09-13 H.J. Lu + + * i386-dis.c (get_valid_dis386): Take a pointer to + disassemble_info. Handle IS_3BYTE_OPCODE. + (print_insn): Updated. Don't handle IS_3BYTE_OPCODE here. + +2007-09-12 H.J. Lu + + * i386-opc.h (CpuUnused): Defined with CpuMax. + (OTUnused): Defined with OTMax. + +2007-09-12 Jan Beulich + + * i386-opc.tbl: Add two-operand forms of blendvps, blendvpd, and + pblendvb. + * i386-tbl.h: Regenerate. + +2007-09-09 H.J. Lu + + * i386-gen.c (main): Remove the local variable, unused. + +2007-09-08 H.J. Lu + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2007-09-08 H.J. Lu + + * configure.in (AC_CHECK_HEADERS): Add limits.h. + * configure: Regenerated. + * config.in: Likewise. + + * i386-gen.c: Include "sysdep.h" instead of and + . Use xstrerror instead of strerror. + (initializer): New. + (cpu_flag_init): Likewise. + (bitfield): Likewise. + (BITFIELD): New. + (cpu_flags): Likewise. + (opcode_modifiers): Likewise. + (operand_types): Likewise. + (compare): Likewise. + (set_cpu_flags): Likewise. + (output_cpu_flags): Likewise. + (process_i386_cpu_flags): Likewise. + (output_opcode_modifier): Likewise. + (process_i386_opcode_modifier): Likewise. + (output_operand_type): Likewise. + (process_i386_operand_type): Likewise. + (set_bitfield): Likewise. + (operand_type_init): Likewise. + (process_i386_initializers): Likewise. + (process_i386_opcodes): Call process_i386_opcode_modifier to + process opcode_modifier. Call process_i386_operand_type to + process operand_types. + (process_i386_registers): Call process_i386_operand_type to + process reg_type. + (main): Check unused bits in i386_cpu_flags and i386_operand_type. + Sort cpu_flags, opcode_modifiers and operand_types. Call + process_i386_initializers. + + * i386-init.h: New. + * i386-tbl.h: Regenerated. + + * i386-opc.h: Include . + (CHAR_BIT): Define as 8 if not defined. + (Cpu186): Changed to position of bitfiled. + (Cpu286): Likewise. + (Cpu386): Likewise. + (Cpu486): Likewise. + (Cpu586): Likewise. + (Cpu686): Likewise. + (CpuP4): Likewise. + (CpuK6): Likewise. + (CpuK8): Likewise. + (CpuMMX): Likewise. + (CpuMMX2): Likewise. + (CpuSSE): Likewise. + (CpuSSE2): Likewise. + (Cpu3dnow): Likewise. + (Cpu3dnowA): Likewise. + (CpuSSE3): Likewise. + (CpuPadLock): Likewise. + (CpuSVME): Likewise. + (CpuVMX): Likewise. + (CpuSSSE3): Likewise. + (CpuSSE4a): Likewise. + (CpuABM): Likewise. + (CpuSSE4_1): Likewise. + (CpuSSE4_2): Likewise. + (Cpu64): Likewise. + (CpuNo64): Likewise. + (D): Likewise. + (W): Likewise. + (Modrm): Likewise. + (ShortForm): Likewise. + (Jump): Likewise. + (JumpDword): Likewise. + (JumpByte): Likewise. + (JumpInterSegment): Likewise. + (FloatMF): Likewise. + (FloatR): Likewise. + (FloatD): Likewise. + (Size16): Likewise. + (Size32): Likewise. + (Size64): Likewise. + (IgnoreSize): Likewise. + (DefaultSize): Likewise. + (No_bSuf): Likewise. + (No_wSuf): Likewise. + (No_lSuf): Likewise. + (No_sSuf): Likewise. + (No_qSuf): Likewise. + (No_xSuf): Likewise. + (FWait): Likewise. + (IsString): Likewise. + (RegKludge): Likewise. + (IsPrefix): Likewise. + (ImmExt): Likewise. + (NoRex64): Likewise. + (Rex64): Likewise. + (Ugh): Likewise. + (Reg8): Likewise. + (Reg16): Likewise. + (Reg32): Likewise. + (Reg64): Likewise. + (FloatReg): Likewise. + (RegMMX): Likewise. + (RegXMM): Likewise. + (Imm8): Likewise. + (Imm8S): Likewise. + (Imm16): Likewise. + (Imm32): Likewise. + (Imm32S): Likewise. + (Imm64): Likewise. + (Imm1): Likewise. + (BaseIndex): Likewise. + (Disp8): Likewise. + (Disp16): Likewise. + (Disp32): Likewise. + (Disp32S): Likewise. + (Disp64): Likewise. + (InOutPortReg): Likewise. + (ShiftCount): Likewise. + (Control): Likewise. + (Debug): Likewise. + (Test): Likewise. + (SReg2): Likewise. + (SReg3): Likewise. + (Acc): Likewise. + (FloatAcc): Likewise. + (JumpAbsolute): Likewise. + (EsSeg): Likewise. + (RegMem): Likewise. + (OTMax): Likewise. + (Reg): Commented out. + (WordReg): Likewise. + (ImplicitRegister): Likewise. + (Imm): Likewise. + (EncImm): Likewise. + (Disp): Likewise. + (AnyMem): Likewise. + (LLongMem): Likewise. + (LongMem): Likewise. + (ShortMem): Likewise. + (WordMem): Likewise. + (ByteMem): Likewise. + (CpuMax): New + (CpuLM): Likewise. + (CpuNumOfUints): Likewise. + (CpuNumOfBits): Likewise. + (CpuUnused): Likewise. + (OTNumOfUints): Likewise. + (OTNumOfBits): Likewise. + (OTUnused): Likewise. + (i386_cpu_flags): New type. + (i386_operand_type): Likewise. + (i386_opcode_modifier): Likewise. + (CpuSledgehammer): Removed. + (CpuSSE4): Likewise. + (CpuUnknownFlags): Likewise. + (Reg): Likewise. + (WordReg): Likewise. + (ImplicitRegister): Likewise. + (Imm): Likewise. + (EncImm): Likewise. + (Disp): Likewise. + (AnyMem): Likewise. + (LLongMem): Likewise. + (LongMem): Likewise. + (ShortMem): Likewise. + (WordMem): Likewise. + (ByteMem): Likewise. + (template): Use i386_cpu_flags for cpu_flags, use + i386_opcode_modifier for opcode_modifier, use + i386_operand_type for operand_types. + (reg_entry): Use i386_operand_type for reg_type. + + * Makefile.am (HFILES): Add i386-init.h. + ($(srcdir)/i386-init.h): New rule. + ($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h + instead. + * Makefile.in: Regenerated. + +2007-09-06 H.J. Lu + + * i386-gen.c (next_field): Updated to take a separator. + (process_i386_opcodes): Updated. + (process_i386_registers): Likewise. + +2007-09-06 H.J. Lu + + * i386-gen.c (table): Moved ... + (main): Here. Call process_copyright to output copyright. + (process_copyright): New. + (process_i386_opcodes): Take FILE *table. + (process_i386_registers): Likewise. + +2007-09-06 H.J. Lu + + * i386-gen.c (table): New. + (process_i386_opcodes): Report errno when faied to open + i386-opc.tbl. Output opcodes to table. Close i386-opc.tbl + before return. + (process_i386_registers): Report errno when faied to open + i386-reg.tbl. Output opcodes to table. Close i386-reg.tbl + before return. + (main): Open i386-tbl.h for output. + + * Makefile.am ($(srcdir)/i386-tbl.h): Remove " > $@". + * Makefile.in: Regenerated. + +2007-09-06 H.J. Lu + + * i386-opc.tbl: Correct SVME instructions to allow 32bit register + operand in 64bit mode. + * i386-tbl.h: Regenerated. + +2007-08-31 H.J. Lu + + * i386-dis.c (OPC_EXT_40...OPC_EXT_45): New. + (dis386_twobyte): Use OPC_EXT_40...OPC_EXT_45. + (opc_ext_table): Add OPC_EXT_40...OPC_EXT_45. + +2007-08-31 H.J. Lu + + * i386-dis.c (SVME_Fixup): Removed. + (OPC_EXT_39): New. + (OPC_EXT_RM_6): Likewise. + (grps): Use OPC_EXT_39. + (opc_ext_table): Add OPC_EXT_39. + (opc_ext_rm_table): Add OPC_EXT_RM_6. + + * i386-opc.tbl: Correct SVME instructions to take register + operand only. + * i386-tbl.h: Regenerated. + +2007-08-31 H.J. Lu + + * Makefile.am (INCLUDES): Remove -D_GNU_SOURCE. + * Makefile.in: Regenerated. + + * configure.in (AC_GNU_SOURCE): Added. + (AC_PROG_CC): Moved before AC_GNU_SOURCE. + (AC_CHECK_DECLS): Add stpcpy. + * configure: Regenerated. + * config.in: Likewise. + + * i386-dis.c: Include "sysdep.h" before "dis-asm.h". + + * sysdep.h (stpcpy): New. + +2007-08-30 H.J. Lu + + * i386-dis.c (INVLPG_Fixup): Removed. + (OPC_EXT_38): New. + (OPC_EXT_RM_5): Likewise. + (grps): Use OPC_EXT_38. + (opc_ext_table): Add OPC_EXT_38. + (opc_ext_rm_table): Add OPC_EXT_RM_5. + +2007-08-29 H.J. Lu + + * i386-dis.c (SIMD_Fixup): Removed. + (OPC_EXT_34...OPC_EXT_37): New. + (dis386_twobyte): Use OPC_EXT_34 and OPC_EXT_35. + (prefix_user_table): Use OPC_EXT_36 and OPC_EXT_37. + (opc_ext_table): Add OPC_EXT_34...OPC_EXT_37. + +2007-08-29 H.J. Lu + + * i386-dis.c (OPC_EXT_25...OPC_EXT_33): New. + (dis386): Use OPC_EXT_0...OPC_EXT_2. + (dis386_twobyte): Use OPC_EXT_3...OPC_EXT_5. + (grps): Updated to use OPC_EXT_6...OPC_EXT_31. + (prefix_user_table): Use OPC_EXT_32. + (x86_64_table): Use OPC_EXT_33. + (opc_ext_table): Reorder and add OPC_EXT_25...OPC_EXT_33. + +2007-08-29 H.J. Lu + + * i386-dis.c (prefix_user_table): Fix comment. + +2007-08-29 H.J. Lu + + * i386-dis.c (OP_Skip_MODRM): New. + (OP_Monitor): Likewise. + (OP_Mwait): Likewise. + (Mb): Likewise. + (Skip_MODRM): Likewise. + (USE_OPC_EXT_TABLE): Likewise. + (USE_OPC_EXT_RM_TABLE): Likewise. + (PREGRP98...PREGRP100): Likewise. + (OPC_EXT_0...OPC_EXT_24): Likewise. + (OPC_EXT_RM_0...OPC_EXT_RM_4): Likewise. + (lock_prefix): Likewise. + (data_prefix): Likewise. + (addr_prefix): Likewise. + (repz_prefix): Likewise. + (repnz_prefix): Likewise. + (opc_ext_table): Likewise. + (opc_ext_rm_table): Likewise. + (get_valid_dis386): Likewise. + (OP_VMX): Removed. + (OP_0fae): Likewise. + (PNI_Fixup): Likewise. + (VMX_Fixup): Likewise. + (VM): Likewise. + (twobyte_uses_DATA_prefix): Likewise. + (twobyte_uses_REPNZ_prefix): Likewise. + (twobyte_uses_REPZ_prefix): Likewise. + (threebyte_0x38_uses_DATA_prefix): Likewise. + (threebyte_0x38_uses_REPNZ_prefix): Likewise. + (threebyte_0x38_uses_REPZ_prefix): Likewise. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (threebyte_0x3a_uses_REPNZ_prefix): Likewise. + (threebyte_0x3a_uses_REPZ_prefix): Likewise. + (grps): Use OPC_EXT_0...OPC_EXT_24. + (prefix_user_table): Add PREGRP98...PREGRP100. + (print_insn): Remove uses_DATA_prefix, uses_LOCK_prefix, + uses_REPNZ_prefix and uses_REPZ_prefix. Initialize + repz_prefix, repnz_prefix, lock_prefix, addr_prefix and + data_prefix based on prefixes. Call get_valid_dis386 to + get a pointer to the valid dis386. Print out prefixes if + they aren't NULL. + (OP_C): Clear lock_prefix if PREFIX_LOCK is used. + (REP_Fixup): Set repz_prefix to "rep " when seeing + PREFIX_REPZ. + +2007-08-28 Daniel Jacobowitz + + * po/nl.po: Updated translation. + +2007-08-28 H.J. Lu + + * i386-dis.c (Md): New. + (grps): Use 0 on invlpg. Use M on fxsave and fxrstor. Use + Md on ldmxcsr and stmxcsr. Use b_mode on clflush. + (OP_0fae): Clear bytemode for sfence. + +2007-08-22 Ben Elliston + + * ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New. + (XOPS, XOPS_MASK, XW, XW_MASK): Likewise. + (PPCPS): Likewise. + (powerpc_opcodes): Add all pair singles instructions. + * ppc-dis.c (powerpc_dialect): Handle "ppcps". + (print_ppc_disassembler_options): Document -Mppcps. + +2007-08-21 Andreas Krebbel + + * s390-mkopc.c (struct s390_cond_ext_format): New global struct. + (s390_cond_ext_format): New global variable. + (expandConditionalJump): New function. + (main): Invoke expandConditionalJump for mnemonics containing '*'. + * s390-opc.txt: Replace mnemonics with conditional + mask extensions with instructions using the newly introduced '*' tag. + +2007-08-17 Alan Modra + + * po/Make-in: Add --msgid-bugs-address to xgettext invocation. + +2007-08-10 Nick Clifton + + * po/fi.po: Updated Finnish translation. + * po/ga.po: Updated Irish translation. + * po/vi.po: Updated Vietnamese translation. + +2007-08-09 H.J. Lu + + * i386-opc.tbl: Add NoRex64 to pmovsxbw, pmovsxwd, pmovsxdq, + pmovzxbw, pmovzxwd, pmovzxdq and roundsd. + * i386-tbl.h: Regenerated. + +2007-08-03 James E. Wilson + + * ia64-gen.c: (main): Add missing newline to copyright message. + * ia64-ic.tbl (fp-non-arith): Add xmpy. + * ia64-asmtab.c: Regenerate. + +2007-08-01 Michael Snyder + + * i386-dis.c (print_insn): Guard against NULL. + +2007-07-29 H.J. Lu + + PR binutils/4834 + * i386-dis.c (EXw): New. + (prefix_user_table): Updated to use EXw, EXd and EXq for SSE4 + instructions when appropriated. + +2007-07-28 H.J. Lu + + PR binutils/4834 + * i386-dis.c (Eq): New. + (EMC): Renamed to ... + (EMCq): This. Use q_mode instead of v_mode. + (prefix_user_table): Updated to use EXd, EXq, EMCq, Ed and Eq + when appropriated. + +2007-07-28 H.J. Lu + + * i386-dis.c (dis386_twobyte): Change "movd" to "movK". + (prefix_user_table): Likewise. Use EXq instead of EXx on + "movq". + +2007-07-27 Nathan Sidwell + + * ppc-opc (PPC7450): New. + (powerpc_opcodes): Use it in dcba. + +2007-07-24 H.J. Lu + + * i386-gen.c (main): Print a newline after copyright notice. + +2007-07-19 Nick Clifton + + PR binutils/4801 + * maxq-dis.c (get_reg_name): Fix the scan of the + mem_access_syntax_table. + +2007-07-16 H.J. Lu + + * i386-dis.c (EMq): Removed. + (EMx): New. + (prefix_user_table): Replace EMq with EMx. + +2007-07-16 Nick Clifton + + * po/nl.po: Updated translation. + +2007-07-12 Nick Clifton + + * po/vi.po: Updated translation. + * po/nl.po: Updated translation. + +2007-07-06 Mark Kettenis + H.J. Lu + + * Makefile.am (i386-tbl.h): Add $(srcdir)/ to target. + (ia64-asmtab.c): Likewise. + * Makefile.in: Regenerate. + +2007-07-05 H.J. Lu + + * aclocal.m4: Regenerated. + +2007-07-04 Nick Clifton + + * alpha-dis.c: Update copyright notice to refer to GPLv3. + * alpha-opc.c, arc-dis.c, arc-dis.h, arc-ext.c, arc-ext.h, + arc-opc.c, arm-dis.c, avr-dis.c, bfin-dis.c, cgen-asm.c, + cgen-asm.in, cgen-bitset.c, cgen-dis.c, cgen-dis.in, cgen-ibld.in, + cgen-opc.c, cgen-ops.h, cgen.sh, cgen-types.h, cr16-dis.c, + cr16-opc.c, cris-dis.c, cris-opc.c, crx-dis.c, crx-opc.c, + d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, disassemble.c, + dis-buf.c, dis-init.c, dlx-dis.c, h8300-dis.c, h8500-dis.c, + h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c, i386-dis.c, + i386-gen.c, i386-opc.c, i386-opc.h, i860-dis.c, i960-dis.c, + ia64-asmtab.h, ia64-dis.c, ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, + ia64-opc.c, ia64-opc-d.c, ia64-opc-f.c, ia64-opc.h, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-x.c, m10200-dis.c, m10200-opc.c, + m10300-dis.c, m10300-opc.c, m68hc11-dis.c, m68hc11-opc.c, + m68k-dis.c, m68k-opc.c, m88k-dis.c, maxq-dis.c, mcore-dis.c, + mcore-opc.h, mips16-opc.c, mips-dis.c, mips-opc.c, mmix-dis.c, + mmix-opc.c, msp430-dis.c, ns32k-dis.c, opintl.h, or32-dis.c, + or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c, pj-opc.c, + ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c, s390-opc.c, + score-dis.c, score-opc.h, sh64-dis.c, sh64-opc.c, sh64-opc.h, + sh-dis.c, sh-opc.h, sparc-dis.c, sparc-opc.c, spu-dis.c, + spu-opc.c, sysdep.h, tic30-dis.c, tic4x-dis.c, tic54x-dis.c, + tic54x-opc.c, tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, + vax-dis.c, w65-dis.c, w65-opc.h, xtensa-dis.c, z80-dis.c, + z8k-dis.c, z8kgen.c: Likewise. + * i386-opc.tbl, i386-reg.tbl: Add copyright notice. + * aclocal.m4, configure, fr30-asm.c, fr30-desc.c, fr30-desc.h, + fr30-dis.c, fr30-ibld.c, fr30-opc.c, fr30-opc.h, frv-asm.c, + frv-desc.c, frv-desc.h, frv-dis.c, frv-ibld.c, frv-opc.c, + frv-opc.h, i386-tbl.h, ia64-asmtab.c, ip2k-asm.c, ip2k-desc.c, + ip2k-desc.h, ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, + iq2000-asm.c, iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c, iq2000-opc.h, m32c-asm.c, + m32c-desc.c, m32c-desc.h, m32c-dis.c, m32c-ibld.c, m32c-opc.c, + m32c-opc.h, m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, + m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c, mep-asm.c, + mep-desc.c, mep-desc.h, mep-dis.c, mep-ibld.c, mep-opc.c, + mep-opc.h, mt-asm.c, mt-desc.c, mt-desc.h, mt-dis.c, mt-ibld.c, + mt-opc.c, mt-opc.h, openrisc-asm.c, openrisc-desc.c, + openrisc-desc.h, openrisc-dis.c, openrisc-ibld.c, openrisc-opc.c, + openrisc-opc.h, xc16x-asm.c, xc16x-desc.c, xc16x-desc.h, + xc16x-dis.c, xc16x-ibld.c, xc16x-opc.c, xc16x-opc.h, + xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h, + xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c, + xstormy16-opc.h, z8k-opc.h: Regenerated + +2007-07-04 M R Swami Reddy + + * cr16-dis.c (getcinvstring): Add const qualifier to char * + parameter. + (print_insn_cr16): Remove cast to char *. + +2007-07-03 Nathan Sidwell + + * m68k-dis.c (fetch_arg): Add E. Replace length switch with + direct masking. + (print_ins_arg): Add j & K operand types. + (match_insn_m68k): Check and skip initial '.' arg character. + (m68k_scan_mask): Likewise. + * m68k-opc.c (m68k_opcodes): Add coprocessor instructions. + +2007-07-02 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2007-06-30 H.J. Lu + + * aclocal.m4: Regenerated. + * Makefile.in: Likewise. + +2007-06-29 H.J. Lu + + * i386-reg.tbl: Remove spaces before comments. + +2007-06-29 M R Swami Reddy + + * cr16-opc.c: New file. + * cr16-dis.c: New file. + * Makefile.am: Entries for cr16. + * Makefile.in: Regenerate. + * cofigure.in: Add cr16 target information. + * configure : Regenerate. + * disassemble.c: Add cr16 target information. + +2007-06-28 H.J. Lu + + * Makefile.am (HFILES): Add i386-opc.h and i386-tbl.h. + (CFILES): Add i386-gen.c. + (i386-gen): New rule. + (i386-gen.o): Likewise. + (i386-tbl.h): Likewise. + Run "make dep-am". + * Makefile.in: Regenerated. + + * i386-gen.c: New file. + * i386-opc.tbl: Likewise. + * i386-reg.tbl: Likewise. + * i386-tbl.h: Likewise. + + * i386-opc.c: Include "i386-tbl.h". + (i386_optab): Removed. + (i386_regtab): Likewise. + (i386_regtab_size): Likewise. + +2007-06-26 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1. + +2007-06-25 H.J. Lu + + * i386-opc.h (regKludge): Renamed to ... + (RegKludge): This. + + * i386-opc.c (i386_optab): Replace regKludge with RegKludge. + +2007-06-23 H.J. Lu + + PR binutils/4667 + * i386-dis.c (EX): Removed. + (EMd): New. + (EMq): Likewise. + (EXd): Likewise. + (EXq): Likewise. + (EXx): Likewise. + (PREGRP93...PREGRP97): Likewise. + (dis386_twobyte): Updated. + (prefix_user_table): Updated. Add PREGRP93...PREGRP97. + (OP_EX): Remove Intel syntax handling. + +2007-06-18 Nathan Sidwell + + * m68k-opc.c (m68k_opcodes): Add wdebugl variants. + +2007-06-14 H.J. Lu + + * Makefile.am (ACLOCAL_AMFLAGS): Add -I ../config -I ../bfd. + + * acinclude.m4: Removed. + + * Makefile.in: Regenerated. + * doc/Makefile.in: Likewise. + * aclocal.m4: Likewise. + * configure: Likewise. + +2007-06-05 Paul Brook + + * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses. + +2007-05-24 Steve Ellcey + + * Makefile.in: Regnerate. + * configure: Regenerate. + * aclocal.m4: Regenerate. + +2007-05-18 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Don't skip all operands + after setting skip_optional. + +2007-05-16 Peter Bergner + + * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New. + (print_insn_powerpc): Use the new operand_value_powerpc and + skip_optional_operands functions to omit or print all optional + operands as a group. + * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New. + (XFL_MASK): Delete L and W bits from the mask. + (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK + with XWRA_MASK. Use W. + (mtfsf, mtfsf.): Use XFL_L and W. + +2007-05-14 H.J. Lu + + PR binutils/4502 + * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw". + +2007-05-10 H.J. Lu + + * i386-opc.h (ShortForm): Redefined. + (Jump): Likewise. + (JumpDword): Likewise. + (JumpByte): Likewise. + (JumpInterSegment): Likewise. + (FloatMF): Likewise. + (FloatR): Likewise. + (FloatD): Likewise. + (Size16): Likewise. + (Size32): Likewise. + (Size64): Likewise. + (IgnoreSize): Likewise. + (DefaultSize): Likewise. + (No_bSuf): Likewise. + (No_wSuf): Likewise. + (No_lSuf): Likewise. + (No_sSuf): Likewise. + (No_qSuf): Likewise. + (No_xSuf): Likewise. + (FWait): Likewise. + (IsString): Likewise. + (regKludge): Likewise. + (IsPrefix): Likewise. + (ImmExt): Likewise. + (NoRex64): Likewise. + (Rex64): Likewise. + (Ugh): Likewise. + +2007-05-07 H.J. Lu + + * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries + for some SSE4 instructions. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + +2007-05-03 H.J. Lu + + * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode. + + * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand + type for crc32. + +2007-05-01 H.J. Lu + + * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and + check data size prefix in 16bit mode. + + * i386-opc.c (i386_optab): Default crc32 to non-8bit and + support Intel mode. + +2007-04-30 Mark Salter + + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + +2007-04-30 Alan Modra + + PR 4436 + * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE. + +2007-04-27 H.J. Lu + + * i386-dis.c (modrm): Put reg before rm. + +2007-04-26 H.J. Lu + + PR binutils/4430 + * i386-dis.c (print_displacement): New. + (OP_E): Call print_displacement instead of print_operand_value + to output displacement when either base or index exist. Print + the explicit zero displacement in 16bit mode. + +2007-04-26 H.J. Lu + + PR binutils/4429 + * i386-dis.c (print_insn): Also swap the order of op_riprel + when swapping op_index. Break when the RIP relative address + is printed. + (OP_E): Properly handle RIP relative addressing and print the + explicit zero displacement for Intel mode. + +2007-04-27 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * ns32k-dis.c: Include sysdep.h first. + +2007-04-24 Andreas Krebbel + + * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the + opcode. + * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions. + +2007-04-24 Nick Clifton + + * arm-dis.c (print_insn): Initialise type. + +2007-04-24 Alan Modra + + * cgen-types.h: Include bfd_stdint.h, not stdint.h. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2007-04-23 Nathan Sidwell + + * m68k-opc.c: Mark mcfisa_c instructions. + +2007-04-21 Richard Earnshaw + + * arm-dis.c (arm_opcodes): Disassemble to unified syntax. + (thumb_opcodes): Add missing white space in adr. + (arm_decode_shift): New parameter, print_shift. Only decode the + shift parameter if set. Adjust callers. + (print_insn_arm): Support for operand type q with no shift decode. + +2007-04-21 Alan Modra + + * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete. + Move contents to.. + (i386_regtab): ..here. + * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete. + + * ppc-opc.c (powerpc_operands): Delete duplicate entries. + (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete. + (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete. + (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L. + +2007-04-20 Nathan Sidwell + + * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as + rambar1. + +2007-04-20 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand + change. + * ppc-opc.c (powerpc_operands): Replace bit count with bit mask + in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove + references to following deleted functions. + (insert_bd, extract_bd, insert_dq, extract_dq): Delete. + (insert_ds, extract_ds, insert_de, extract_de): Delete. + (insert_des, extract_des, insert_li, extract_li): Delete. + (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete. + (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete. + (num_powerpc_operands): New constant. + (XSPRG_MASK): Remove entire SPRG field. + (powerpc_opcodes ): Use XLBB_MASK not XLYBB_MASK. + +2007-04-20 Alan Modra + + * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift. + (Z2_MASK): Define. + (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand. + +2007-04-20 Richard Earnshaw + + * arm-dis.c (print_insn): Only look for a mapping symbol in the section + being disassembled. + +2007-04-19 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2007-04-19 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc, + db10cyc, db12cyc, db16cyc. + +2007-04-19 Nathan Froyd + + * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe. + +2007-04-18 H.J. Lu + + * i386-dis.c (CRC32_Fixup): New. + (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90, + PREGRP91): New. + (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87, + PREGRP88, PREGRP89, PREGRP90 and PREGRP91. + (three_byte_table): Likewise. + + * i386-opc.c (i386_optab): Add SSE4.2 opcodes. + + * i386-opc.h (CpuSSE4_2): New. + (CpuSSE4): Likewise. + (CpuUnknownFlags): Add CpuSSE4_2. + +2007-04-18 H.J. Lu + + * i386-dis.c (XMM_Fixup): New. + (Edqb): New. + (Edqd): New. + (XMM0): New. + (dqb_mode): New. + (dqd_mode): New. + (PREGRP39 ... PREGRP85): New. + (threebyte_0x38_uses_DATA_prefix): Updated for SSE4. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (prefix_user_table): Add PREGRP39 ... PREGRP85. + (three_byte_table): Likewise. + (putop): Handle 'K'. + (intel_operand_size): Handle dqb_mode, dqd_mode): + (OP_E): Likewise. + (OP_G): Likewise. + + * i386-opc.c (i386_optab): Add SSE4.1 opcodes. + + * i386-opc.h (CpuSSE4_1): New. + (CpuUnknownFlags): Add CpuSSE4_1. + (regKludge): Update comment. + +2007-04-18 Matthias Klose + + * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion. + * Makefile.in: Regenerate. + +2007-04-14 Steve Ellcey + + * Makefile.am: Add ACLOCAL_AMFLAGS. + * Makefile.in: Regenerate. + +2007-04-13 H.J. Lu + + * i386-dis.c: Remove trailing white spaces. + * i386-opc.c: Likewise. + * i386-opc.h: Likewise. + +2007-04-11 H.J. Lu + + PR binutils/4333 + * i386-dis.c (GRP1a): New. + (GRP1b ... GRPPADLCK2): Update index. + (dis386): Use GRP1a for entry 0x8f. + (mod, rm, reg): Removed. Replaced by ... + (modrm): This. + (grps): Add GRP1a. + +2007-04-09 Kazu Hirata + + * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and + info->print_address_func if longjmp is called. + +2007-03-29 DJ Delorie + + * m32c-desc.c: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-opc.c: Regenerate. + +2007-03-28 H.J. Lu + + * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and + movq. Remove InvMem from sldt, smsw and str. + + * i386-opc.h (InvMem): Renamed to ... + (RegMem): Update comments. + (AnyMem): Remove InvMem. + +2007-03-27 Paul Brook + + * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??). + +2007-03-24 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x. + (print_insn_coprocessor): Handle %x. + +2007-03-24 Paul Brook + Mark Shinwell + + * arm-dis.c (arm_opcodes): Print SRS base register. + +2007-03-23 H.J. Lu + + * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB. + + * i386-opc.c (i386_optab): Add rex.wrxb. + +2007-03-21 H.J. Lu + + * i386-dis.c (REX_MODE64): Remove definition. + (REX_EXTX): Likewise. + (REX_EXTY): Likewise. + (REX_EXTZ): Likewise. + (USED_REX): Use REX_OPCODE instead of 0x40. + Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, + REX_R, REX_X and REX_B respectively. + +2007-03-21 H.J. Lu + + PR binutils/4218 + * i386-dis.c (PREGRP38): New. + (dis386): Use PREGRP38 for 0x90. + (prefix_user_table): Add PREGRP38. + (print_insn): Set uses_REPZ_prefix to 1 for pause. + (NOP_Fixup1): Properly handle REX bits. + (NOP_Fixup2): Likewise. + + * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit. + Allow register with nop. + +2007-03-20 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.h: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2007-03-15 H.J. Lu + + * i386-opc.c: Include "libiberty.h". + (i386_regtab): Remove the last entry. + (i386_regtab_size): New. + (i386_float_regtab_size): Likewise. + + * i386-opc.h (i386_regtab_size): New. + (i386_float_regtab_size): Likewise. + +2007-03-15 H.J. Lu + + * Makefile.am (CFILES): Add i386-opc.c. + (ALL_MACHINES): Add i386-opc.lo. + Run "make dep-am". + * Makefile.in: Regenerated. + + * configure.in: Add i386-opc.lo for bfd_i386_arch. + * configure: Regenerated. + + * i386-dis.c: Include "opcode/i386.h". + (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition. + (FWAIT_OPCODE): Remove definition. + (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition. + (MAX_OPERANDS): Remove definition. + + * i386-opc.c: New file. + * i386-opc.h: Likewise. + +2007-03-15 H.J. Lu + + * Makefile.in: Regenerated. + +2007-03-09 H.J. Lu + + * i386-dis.c (OP_Rd): Renamed to ... + (OP_R): This. + (Rd): Updated. + (Rm): Likewise. + +2007-03-08 Alan Modra + + * fr30-asm.c: Regenerate. + * frv-asm.c: Regenerate. + * ip2k-asm.c: Regenerate. + * iq2000-asm.c: Regenerate. + * m32c-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-dis.c: Regenerate. + * mt-asm.c: Regenerate. + * mt-ibld.c: Regenerate. + * mt-opc.c: Regenerate. + * openrisc-asm.c: Regenerate. + * xc16x-asm.c: Regenerate. + * xstormy16-asm.c: Regenerate. + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2007-03-06 Andreas Krebbel + + * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, + INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New + instruction formats added. + (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF, + MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format + masks added. + * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point + instructions added. + * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + (main): z9-ec cpu type option added. + * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + +2007-02-22 DJ Delorie + + * s390-opc.c (INSTR_SS_L2RDRD): New. + (MASK_SS_L2RDRD): New. + * s390-opc.txt (pka): Use it. + +2007-02-20 Thiemo Seufer + Chao-Ying Fu + + * mips-dis.c (mips_arch_choices): Add DSP R2 support. + (print_insn_args): Add support for balign instruction. + * mips-opc.c (D33): New shortcut for DSP R2 instructions. + (mips_builtin_opcodes): Add DSP R2 instructions. + +2007-02-19 Andreas Krebbel + + * s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed. + (INSTR_RRF_U0RF, MASK_RRF_U0RF): Added. + * s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr, + cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF. + +2007-02-19 Andreas Krebbel + + * s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type. + * s390-opc.c (s390_operands): Add RO_28 as optional gpr. + (INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc + and sfpc. + +2007-02-16 Nick Clifton + + PR binutils/4045 + * avr-dis.c (comment_start): New variable, contains the prefix to + use when printing addresses in comments. + (print_insn_avr): Set comment_start to an empty space if there is + no symbol table available as the generic address printing code + will prefix the numeric value of the address with 0x. + +2007-02-13 H.J. Lu + + * i386-dis.c: Updated to use an array of MAX_OPERANDS operands + in struct dis386. + +2007-02-05 Dave Brolley + Richard Sandiford + DJ Delorie + Graydon Hoare + Frank Ch. Eigler + Ben Elliston + + * Makefile.am (HFILES): Add mep-desc.h mep-opc.h. + (CFILES): Add mep-*.c + (ALL_MACHINES): Add mep-*.lo. + (CLEANFILES): Add stamp-mep. + (CGEN_CPUS): Add mep. + (MEP_DEPS): New variable. + (mep-*): New targets. + * configure.in: Handle bfd_mep_arch. + * disassemble.c (ARCH_mep): New macro. + (disassembler): Handle bfd_arch_mep. + (disassemble_init_for_target): Likewise. + * mep-*: New files for Toshiba Media Processor (MeP). + * Makefile.in: Regenerated. + * configure: Regenerated. + +2007-02-05 H.J. Lu + + * i386-dis.c (OP_J): Undo the last change. Properly handle 64K + wrap around within the same segment in 16bit mode. + +2007-02-02 H.J. Lu + + * i386-dis.c (OP_J): Mask to 16bit only if there is a data16 + prefix. + +2007-02-02 H.J. Lu + + * avr-dis.c (avr_operand): Correct PR number in comment. + +2007-02-02 H.J. Lu + + * disassemble.c (disassembler_usage): Call + print_i386_disassembler_options for i386 disassembler. + + * i386-dis.c (print_i386_disassembler_options): New. + (print_insn): Support the new addr64 option. + +2007-02-02 Hiroki Kaminaga + + * ppc-dis.c (powerpc_dialect): Handle ppc440. + * ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can + be used. + +2007-02-02 Alan Modra + + * ppc-opc.c (insert_bdm): -Many comment. + (valid_bo): Add "extract" param. Accept both powerpc and power4 + BO fields when disassembling with -Many. + (insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call. + +2007-01-08 Kazu Hirata + + * m68k-opc.c (m68k_opcodes): Replace cpu32 with + cpu32 | fido_a except on tbl instructions. + +2007-01-04 Paul Brook + + * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries. + +2007-01-04 Andreas Schwab + + * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns. + +2007-01-04 Julian Brown + + * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl, + vqrshl instructions. + +For older changes see ChangeLog-2006 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2008 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2008 new file mode 100644 index 000000000000..4b4f7ba64242 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2008 @@ -0,0 +1,1204 @@ +2008-12-30 Martin Schwidefsky + + * s390-opc.txt: Add ptff instruction. + +2008-12-24 Jan Kratochvil + + * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files. + * Makefile.in: Regenerate. + +2008-12-23 Jon Beniston + + * Makefile.am: Add LM32 object files and dependencies. + * Makefile.in: Regenerate. + * configure.in: Add LM32 target. + * configure: Regenerate. + * disassemble.c: Add LM32 disassembler. + * cgen-asm.in: Update copyright year. + * cgen-dis.in: Update copyright year. + * cgen-ibld.in: Update copyright year. + * lm32-asm.c: New file. + * lm32-desc.c: New file. + * lm32-desc.h: New file. + * lm32-dis.c: New file. + * lm32-ibld.c: New file. + * lm32-opc.c: New file. + * lm32-opc.h: New file. + * lm32-opinst.c: New file. + +2008-12-23 H.J. Lu + + * i386-dis.c (EXdS): New. + (EXdVexS): Likewise. + (EXqVexS): Likewise. + (d_swap_mode): Likewise. + (q_mode): Updated. + (prefix_table): Use EXdS on movss and EXqS on movsd. + (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd. + (intel_operand_size): Handle d_swap_mode. + (OP_EX): Likewise. + + * i386-opc.h (S): Update comments. + + * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd. + * i386-tbl.h: Regenerated. + +2008-12-23 Nick Clifton + + * po/ga.po: Updated Irish translation. + +2008-12-20 H.J. Lu + + * i386-dis.c (EbS): New. + (EvS): Likewise. + (EMS): Likewise. + (EXqS): Likewise. + (EXxS): Likewise. + (b_swap_mode): Likewise. + (v_swap_mode): Likewise. + (q_swap_mode): Likewise. + (x_swap_mode): Likewise. + (v_mode): Updated. + (w_mode): Likewise. + (t_mode): Likewise. + (xmm_mode): Likewise. + (swap_operand): Likewise. + (dis386): Use EbS on movB. Use EvS on moveS. + (dis386_twobyte): Use EXxS on movapX. + (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa, + vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq. + (vex_table): Use EXxS on vmovapX. + (vex_len_table): Use EXqS on vmovq. + (intel_operand_size): Handle b_swap_mode, v_swap_mode, + q_swap_mode and x_swap_mode. + (OP_E_register): Handle b_swap_mode and v_swap_mode. + (OP_EM): Handle v_swap_mode. + (OP_EX): x_swap_mode and q_swap_mode. + + * i386-gen.c (opcode_modifiers): Add S. + + * i386-opc.h (S): New. + (Modrm): Updated. + (i386_opcode_modifier): Add s. + + * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq, + movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq. + * i386-tbl.h: Regenerated. + +2008-12-18 H.J. Lu + + * i386-dis.c (mnemonicendp): New. + (op): Likewise. + (print_insn): Use mnemonicendp. + (OP_3DNowSuffix): Likewise. + (CMP_Fixup): Likewise. + (CMPXCHG8B_Fixup): Likewise. + (CRC32_Fixup): Likewise. + (OP_DREX_FCMP): Likewise. + (OP_DREX_ICMP): Likewise. + (VZERO_Fixup): Likewise. + (VCMP_Fixup): Likewise. + (PCLMUL_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (MOVBE_Fixup): Likewise. + (putop): Update mnemonicendp. + (oappend): Use stpcpy. + (simd_cmp_op): Changed to struct op. + (vex_cmp_op): Likewise. + (pclmul_op): Likewise. + (vpermil2_op): Likewise. + +2008-12-18 Ralf Wildenhues + + * configure: Regenerate. + +2008-12-15 Richard Earnshaw + + * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using + unified syntax. + +2008-12-08 H.J. Lu + + * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD. + +2008-12-08 H.J. Lu + + * i386-dis.c (putop): Remove strayed comments. + +2008-12-04 Ben Elliston + + * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE + for -Mbooke. + (print_ppc_disassembler_options): Update usage. + * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove. + (BOOKE64): Remove. + (PPCCHLK64): Likewise. + (powerpc_opcodes): Remove all BOOKE64 instructions. + +2008-11-28 Joshua Kinard + + * mips-dis.c (mips_arch_choices): Add r14000, r16000. + +2008-11-27 M R Swami Reddy + + * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and + adjusted the mask for 32-bit branch instruction. + +2008-11-27 Alan Modra + + * ppc-opc.c (extract_sprg): Correct operand range check. + +2008-11-26 Andreas Schwab + + * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE) + (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling. + (save_printer, save_print_address): Remove. + (fetch_data): Don't use them. + (match_insn_m68k): Always restore printing functions. + (print_insn_m68k): Don't save/restore printing functions. + +2008-11-25 Nick Clifton + + * m68k-dis.c: Rewrite to remove use of setjmp/longjmp. + +2008-11-18 Catherine Moore + + * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt + instructions. + (neon_opcodes): Likewise. + (print_insn_coprocessor): Print 't' or 'b' for vcvt + instructions. + +2008-11-14 Tristan Gingold + + * makefile.vms (OBJS): Update list of objects. + (DEFS): Update + (CFLAGS): Update. + +2008-11-06 Chao-ying Fu + + * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these + before sync. + (sync): New instruction with 5-bit sync type. + * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values. + +2008-11-06 Nick Clifton + + * avr-dis.c: Replace uses of sprintf without a format string with + calls to strcpy. + +2008-11-03 H.J. Lu + + * i386-opc.tbl: Add cmovpe and cmovpo. + * i386-tbl.h: Regenerated. + +2008-10-22 Nick Clifton + + PR 6937 + * configure.in (SHARED_LIBADD): Revert previous change. + Add a comment explaining why. + (SHARED_DEPENDENCIES): Revert previous change. + * configure: Regenerate. + +2008-10-10 Nick Clifton + + PR 6937 + * configure.in (SHARED_LIBADD): Add libiberty.a. + (SHARED_DEPENDENCIES): Add libiberty.a. + +2008-09-30 H.J. Lu + + * i386-gen.c: Include "hashtab.h". + (next_field): Take a new argument, last. Check last. + (process_i386_cpu_flag): Updated. + (process_i386_opcode_modifier): Likewise. + (process_i386_operand_type): Likewise. + (process_i386_registers): Likewise. + (output_i386_opcode): New. + (opcode_hash_entry): Likewise. + (opcode_hash_table): Likewise. + (opcode_hash_hash): Likewise. + (opcode_hash_eq): Likewise. + (process_i386_opcodes): Use opcode hash table and opcode array. + +2008-09-30 Andreas Krebbel + + * s390-opc.txt (stdy, stey): Fix description + +2008-09-30 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2008-09-29 H.J. Lu + + * aclocal.m4: Regenerated. + * configure: Likewise. + * Makefile.in: Likewise. + +2008-09-29 Nick Clifton + + * po/vi.po: Updated Vietnamese translation. + * po/fr.po: Updated French translation. + +2008-09-26 Florian Krohm + + * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF. + (cfxr, cfdr, cfer, clclu): Add esa flag. + (sqd): Instruction added. + (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF. + * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed. + +2008-09-14 Arnold Metselaar + + * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes. + (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions. + +2008-09-11 H.J. Lu + + * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd]. + * i386-tbl.h: Regenerated. + +2008-08-28 Jan Beulich + + * i386-dis.c (dis386): Adjust far return mnemonics. + * i386-opc.tbl: Add retf. + * i386-tbl.h: Re-generate. + +2008-08-28 Jan Beulich + + * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics. + +2008-08-28 H.J. Lu + + * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. + * ia64-gen.c (lookup_specifier): Likewise. + + * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. + * ia64-raw.tbl: Likewise. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerated. + +2008-08-27 H.J. Lu + + * i386-opc.tbl: Correct fidivr operand size. + + * i386-tbl.h: Regenerated. + +2008-08-24 Alan Modra + + * configure.in: Update a number of obsolete autoconf macros. + * aclocal.m4: Regenerate. + +2008-08-20 H.J. Lu + + AVX Programming Reference (August, 2008) + * i386-dis.c (PREFIX_VEX_38DB): New. + (PREFIX_VEX_38DC): Likewise. + (PREFIX_VEX_38DD): Likewise. + (PREFIX_VEX_38DE): Likewise. + (PREFIX_VEX_38DF): Likewise. + (PREFIX_VEX_3ADF): Likewise. + (VEX_LEN_38DB_P_2): Likewise. + (VEX_LEN_38DC_P_2): Likewise. + (VEX_LEN_38DD_P_2): Likewise. + (VEX_LEN_38DE_P_2): Likewise. + (VEX_LEN_38DF_P_2): Likewise. + (VEX_LEN_3ADF_P_2): Likewise. + (PREFIX_VEX_3A04): Updated. + (VEX_LEN_3A06_P_2): Likewise. + (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, + PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. + (x86_64_table): Likewise. + (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, + VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and + VEX_LEN_3ADF_P_2. + + * i386-opc.tbl: Add AES + AVX instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-08-15 Andreas Krebbel + + * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format. + * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format. + +2008-08-15 Alan Modra + + PR 6526 + * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS. + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + +2008-08-14 Sebastian Huber + + PR 6825 + * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300. + +2008-08-12 H.J. Lu + + * i386-opc.tbl: Add syscall and sysret for Cpu64. + + * i386-tbl.h: Regenerated. + +2008-08-04 Alan Modra + + * Makefile.am (POTFILES.in): Set LC_ALL=C. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2008-08-01 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. + (print_insn_powerpc): Prepend 'vs' when printing VSX registers. + (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. + * ppc-opc.c (insert_xt6): New static function. + (extract_xt6): Likewise. + (insert_xa6): Likewise. + (extract_xa6: Likewise. + (insert_xb6): Likewise. + (extract_xb6): Likewise. + (insert_xb6s): Likewise. + (extract_xb6s): Likewise. + (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, + XX3DM_MASK, PPCVSX): New. + (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", + "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp". + +2008-08-01 Pedro Alves + + * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. + * Makefile.in: Regenerate. + +2008-08-01 H.J. Lu + + * i386-reg.tbl: Use Dw2Inval on AVX registers. + * i386-tbl.h: Regenerated. + +2008-07-30 Michael J. Eager + + * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. + * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. + (insert_sprg, PPC405): Use PPC_OPCODE_405. + (powerpc_opcodes): Add Xilinx APU related opcodes. + +2008-07-30 Alan Modra + + * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings. + +2008-07-10 Richard Sandiford + + * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. + +2008-07-07 Adam Nemet + + * mips-opc.c (CP): New macro. + (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the + membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and + dmtc2 Octeon instructions. + +2008-07-07 Stan Shebs + + * dis-init.c (init_disassemble_info): Init endian_code field. + * arm-dis.c (print_insn): Disassemble code according to + setting of endian_code. + (print_insn_big_arm): Detect when BE8 extension flag has been set. + +2008-06-30 Richard Sandiford + + * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check + for ELF symbols. + +2008-06-25 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Handle -M464. + (print_ppc_disassembler_options): Likewise. + * ppc-opc.c (PPC464): Define. + (powerpc_opcodes): Add mfdcrux and mtdcrux. + +2008-06-17 Ralf Wildenhues + + * configure: Regenerate. + +2008-06-13 Peter Bergner + + * ppc-dis.c (print_insn_powerpc): Update prototye to use new + ppc_cpu_t typedef. + (struct dis_private): New. + (POWERPC_DIALECT): New define. + (powerpc_dialect): Renamed to... + (powerpc_init_dialect): This. Update to use ppc_cpu_t and + struct dis_private. + (print_insn_big_powerpc): Update for using structure in + info->private_data. + (print_insn_little_powerpc): Likewise. + (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. + (skip_optional_operands): Likewise. + (print_insn_powerpc): Likewise. Remove initialization of dialect. + * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, + extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, + extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, + extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, + insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, + insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, + insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect + param to be of type ppc_cpu_t. Update prototype. + +2008-06-12 Adam Nemet + + * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, + +s, +S. + * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions + baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, + syncw, syncws, vm3mulu, vm0 and vmulu. + + * mips-dis.c (print_insn_args): Handle field descriptor +Q. + * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, + seqi, sne and snei. + +2008-05-30 H.J. Lu + + * i386-opc.tbl: Add vmovd with 64bit operand. + * i386-tbl.h: Regenerated. + +2008-05-27 Martin Schwidefsky + + * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. + +2008-05-22 H.J. Lu + + * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. + * i386-tbl.h: Regenerated. + +2008-05-22 H.J. Lu + + PR gas/6517 + * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss + into 32bit and 64bit. Remove Reg64|Qword and add + IgnoreSize|No_qSuf on 32bit version. + * i386-tbl.h: Regenerated. + +2008-05-21 H.J. Lu + + * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. + * i386-tbl.h: Regenerated. + +2008-05-21 M R Swami Reddy + + * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond. + +2008-05-14 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2008-05-02 H.J. Lu + + * i386-dis.c (MOVBE_Fixup): New. + (Mo): Likewise. + (PREFIX_0F3880): Likewise. + (PREFIX_0F3881): Likewise. + (PREFIX_0F38F0): Updated. + (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update + PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. + (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. + + * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and + CPU_EPT_FLAGS. + (cpu_flags): Add CpuMovbe and CpuEPT. + + * i386-opc.h (CpuMovbe): New. + (CpuEPT): Likewise. + (CpuLM): Updated. + (i386_cpu_flags): Add cpumovbe and cpuept. + + * i386-opc.tbl: Add entries for movbe and EPT instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-04-29 Adam Nemet + + * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for + the two drem and the two dremu macros. + +2008-04-28 Adam Nemet + + * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 + instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and + cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros + INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D. + +2008-04-25 David S. Miller + + * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr + instead of %sys_tick_cmpr, as suggested in architecture manuals. + +2008-04-23 Paolo Bonzini + + * aclocal.m4: Regenerate. + * configure: Regenerate. + +2008-04-23 David S. Miller + + * sparc-opc.c (asi_table): Add UltraSPARC and Niagara + extended values. + (prefetch_table): Add missing values. + +2008-04-22 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add NoAVX. + + * i386-opc.h (NoAVX): New. + (OldGcc): Updated. + (i386_opcode_modifier): Add noavx. + + * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3 + instructions which don't have AVX equivalent. + * i386-tbl.h: Regenerated. + +2008-04-18 H.J. Lu + + * i386-dis.c (OP_VEX_FMA): New. + (OP_EX_VexImmW): Likewise. + (VexFMA): Likewise. + (Vex128FMA): Likewise. + (EXVexImmW): Likewise. + (get_vex_imm8): Likewise. + (OP_EX_VexReg): Likewise. + (vex_i4_done): Renamed to ... + (vex_w_done): This. + (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps + and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on + FMA instructions. + (print_insn): Updated. + (OP_EX_VexW): Rewrite to swap register in VEX with EX. + (OP_REG_VexI4): Check invalid high registers. + +2008-04-16 Dwarakanath Rajagopal + Michael Meissner + + * i386-opc.tbl: Fix protX to allow memory in the middle operand. + * i386-tbl.h: Regenerate from i386-opc.tbl. + +2008-04-14 Edmar Wienskoski + + * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to + accept Power E500MC instructions. + (print_ppc_disassembler_options): Document -Me500mc. + * ppc-opc.c (DUIS, DUI, T): New. + (XRT, XRTRA): Likewise. + (E500MC): Likewise. + (powerpc_opcodes): Add new Power E500MC instructions. + +2008-04-10 Andreas Krebbel + + * s390-dis.c (init_disasm): Evaluate disassembler_options. + (print_s390_disassembler_options): New function. + * disassemble.c (disassembler_usage): Invoke + print_s390_disassembler_options. + +2008-04-10 Andreas Krebbel + + * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes + of local variables used for mnemonic parsing: prefix, suffix and + number. + +2008-04-10 Andreas Krebbel + + * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic + extensions for conditional jumps (o, p, m, nz, z, nm, np, no). + (s390_crb_extensions): New extensions table. + (insertExpandedMnemonic): Handle '$' tag. + * s390-opc.txt: Remove conditional jump variants which can now + be expanded automatically. + Replace '*' tag with '$' in the compare and branch instructions. + +2008-04-07 H.J. Lu + + * i386-dis.c (PREFIX_VEX_38XX): Add a tab. + (PREFIX_VEX_3AXX): Likewis. + +2008-04-07 H.J. Lu + + * i386-opc.tbl: Remove 4 extra blank lines. + +2008-04-04 H.J. Lu + + * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL + with CPU_PCLMUL_FLAGS/CpuPCLMUL. + (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. + * i386-opc.tbl: Likewise. + + * i386-opc.h (CpuCLMUL): Renamed to ... + (CpuPCLMUL): This. + (CpuFMA): Updated. + (i386_cpu_flags): Replace cpuclmul with cpupclmul. + + * i386-init.h: Regenerated. + +2008-04-03 H.J. Lu + + * i386-dis.c (OP_E_register): New. + (OP_E_memory): Likewise. + (OP_VEX): Likewise. + (OP_EX_Vex): Likewise. + (OP_EX_VexW): Likewise. + (OP_XMM_Vex): Likewise. + (OP_XMM_VexW): Likewise. + (OP_REG_VexI4): Likewise. + (PCLMUL_Fixup): Likewise. + (VEXI4_Fixup): Likewise. + (VZERO_Fixup): Likewise. + (VCMP_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (rex_original): Likewise. + (rex_ignored): Likewise. + (Mxmm): Likewise. + (XMM): Likewise. + (EXxmm): Likewise. + (EXxmmq): Likewise. + (EXymmq): Likewise. + (Vex): Likewise. + (Vex128): Likewise. + (Vex256): Likewise. + (VexI4): Likewise. + (EXdVex): Likewise. + (EXqVex): Likewise. + (EXVexW): Likewise. + (EXdVexW): Likewise. + (EXqVexW): Likewise. + (XMVex): Likewise. + (XMVexW): Likewise. + (XMVexI4): Likewise. + (PCLMUL): Likewise. + (VZERO): Likewise. + (VCMP): Likewise. + (VPERMIL2): Likewise. + (xmm_mode): Likewise. + (xmmq_mode): Likewise. + (ymmq_mode): Likewise. + (vex_mode): Likewise. + (vex128_mode): Likewise. + (vex256_mode): Likewise. + (USE_VEX_C4_TABLE): Likewise. + (USE_VEX_C5_TABLE): Likewise. + (USE_VEX_LEN_TABLE): Likewise. + (VEX_C4_TABLE): Likewise. + (VEX_C5_TABLE): Likewise. + (VEX_LEN_TABLE): Likewise. + (REG_VEX_XX): Likewise. + (MOD_VEX_XXX): Likewise. + (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. + (PREFIX_0F3A44): Likewise. + (PREFIX_0F3ADF): Likewise. + (PREFIX_VEX_XXX): Likewise. + (VEX_OF): Likewise. + (VEX_OF38): Likewise. + (VEX_OF3A): Likewise. + (VEX_LEN_XXX): Likewise. + (vex): Likewise. + (need_vex): Likewise. + (need_vex_reg): Likewise. + (vex_i4_done): Likewise. + (vex_table): Likewise. + (vex_len_table): Likewise. + (OP_REG_VexI4): Likewise. + (vex_cmp_op): Likewise. + (pclmul_op): Likewise. + (vpermil2_op): Likewise. + (m_mode): Updated. + (es_reg): Likewise. + (PREFIX_0F38F0): Likewise. + (PREFIX_0F3A60): Likewise. + (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. + (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF + and PREFIX_VEX_XXX entries. + (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. + (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and + PREFIX_0F3ADF. + (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. + Add MOD_VEX_XXX entries. + (ckprefix): Initialize rex_original and rex_ignored. Store the + REX byte in rex_original. + (get_valid_dis386): Handle the implicit prefix in VEX prefix + bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. + (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before + calling get_valid_dis386. Use rex_original and rex_ignored when + printing out REX. + (putop): Handle "XY". + (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and + ymmq_mode. + (OP_E_extended): Updated to use OP_E_register and + OP_E_memory. + (OP_XMM): Handle VEX. + (OP_EX): Likewise. + (XMM_Fixup): Likewise. + (CMP_Fixup): Use ARRAY_SIZE. + + * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, + CPU_FMA_FLAGS and CPU_AVX_FLAGS. + (operand_type_init): Add OPERAND_TYPE_REGYMM and + OPERAND_TYPE_VEX_IMM4. + (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. + (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, + VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, + VexImmExt and SSE2AVX. + (operand_types): Add RegYMM, Ymmword and Vex_Imm4. + + * i386-opc.h (CpuAVX): New. + (CpuAES): Likewise. + (CpuCLMUL): Likewise. + (CpuFMA): Likewise. + (Vex): Likewise. + (Vex256): Likewise. + (VexNDS): Likewise. + (VexNDD): Likewise. + (VexW0): Likewise. + (VexW1): Likewise. + (Vex0F): Likewise. + (Vex0F38): Likewise. + (Vex0F3A): Likewise. + (Vex3Sources): Likewise. + (VexImmExt): Likewise. + (SSE2AVX): Likewise. + (RegYMM): Likewise. + (Ymmword): Likewise. + (Vex_Imm4): Likewise. + (Implicit1stXmm0): Likewise. + (CpuXsave): Updated. + (CpuLM): Likewise. + (ByteOkIntel): Likewise. + (OldGcc): Likewise. + (Control): Likewise. + (Unspecified): Likewise. + (OTMax): Likewise. + (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. + (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, + vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, + vex3sources, veximmext and sse2avx. + (i386_operand_type): Add regymm, ymmword and vex_imm4. + + * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. + + * i386-reg.tbl: Add AVX registers, ymm0..ymm15. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-03-26 Bernd Schmidt + + From Robin Getz + * bfin-dis.c (bu32): Typedef. + (enum const_forms_t): Add c_uimm32 and c_huimm32. + (constant_formats[]): Add uimm32 and huimm16. + (fmtconst_val): New. + (uimm32): Define. + (huimm32): Define. + (imm16_val): Define. + (luimm16_val): Define. + (struct saved_state): Define. + (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, + A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, + LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. + (get_allreg): New. + (decode_LDIMMhalf_0): Print out the whole register value. + + From Jie Zhang + * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for + multiply and multiply-accumulate to data register instruction. + + * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, + c_imm32, c_huimm32e): Define. + (constant_formats): Add flags for printing decimal, leading spaces, and + exact symbols. + (comment, parallel): Add global flags in all disassembly. + (fmtconst): Take advantage of new flags, and print default in hex. + (fmtconst_val): Likewise. + (decode_macfunc): Be consistant with spaces, tabs, comments, + capitalization in disassembly, fix minor coding style issues. + (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. + (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, + decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, + decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, + decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, + decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, + decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, + decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, + decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, + decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, + _print_insn_bfin, print_insn_bfin): Likewise. + +2008-03-17 Ralf Wildenhues + + * aclocal.m4: Regenerate. + * configure: Likewise. + * Makefile.in: Likewise. + +2008-03-13 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * configure: Regenerate. + +2008-03-07 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Order and format. + +2008-03-01 H.J. Lu + + * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. + * i386-tbl.h: Regenerated. + +2008-02-23 H.J. Lu + + * i386-opc.tbl: Disallow 16-bit near indirect branches for + x86-64. + * i386-tbl.h: Regenerated. + +2008-02-21 Jan Beulich + + * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword + and Fword for far indirect jmp. Allow Reg16 and Word for near + indirect jmp on x86-64. Disallow Fword for lcall. + * i386-tbl.h: Re-generate. + +2008-02-18 M R Swami Reddy + + * cr16-opc.c (cr16_num_optab): Defined + +2008-02-16 H.J. Lu + + * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. + * i386-init.h: Regenerated. + +2008-02-14 Nick Clifton + + PR binutils/5524 + * configure.in (SHARED_LIBADD): Select the correct host specific + file extension for shared libraries. + * configure: Regenerate. + +2008-02-13 Jan Beulich + + * i386-opc.h (RegFlat): New. + * i386-reg.tbl (flat): Add. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich + + * i386-dis.c (a_mode): New. + (cond_jump_mode): Adjust. + (Ma): Change to a_mode. + (intel_operand_size): Handle a_mode. + * i386-opc.tbl: Allow Dword and Qword for bound. + * i386-tbl.h: Re-generate. + +2008-02-13 Jan Beulich + + * i386-gen.c (process_i386_registers): Process new fields. + * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to + unsigned char. Add dw2_regnum and Dw2Inval. + * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo + register names. + * i386-tbl.h: Re-generate. + +2008-02-11 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. + * i386-init.h: Updated. + +2008-02-11 H.J. Lu + + * i386-gen.c (cpu_flags): Add CpuXsave. + + * i386-opc.h (CpuXsave): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpuxsave. + + * i386-dis.c (MOD_0FAE_REG_4): New. + (RM_0F01_REG_2): Likewise. + (MOD_0FAE_REG_5): Updated. + (RM_0F01_REG_3): Likewise. + (reg_table): Use MOD_0FAE_REG_4. + (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated + for xrstor. + (rm_table): Add RM_0F01_REG_2. + + * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-02-11 Jan Beulich + + * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove + Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz). + * i386-tbl.h: Re-generate. + +2008-02-04 H.J. Lu + + PR 5715 + * configure: Regenerated. + +2008-02-04 Adam Nemet + + * mips-dis.c: Update copyright. + (mips_arch_choices): Add Octeon. + * mips-opc.c: Update copyright. + (IOCT): New macro. + (mips_builtin_opcodes): Add Octeon instruction synciobdma. + +2008-01-29 Alan Modra + + * ppc-opc.c: Support optional L form mtmsr. + +2008-01-24 H.J. Lu + + * i386-dis.c (OP_E_extended): Handle r12 like rsp. + +2008-01-23 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS. + * i386-init.h: Regenerated. + +2008-01-23 Tristan Gingold + + * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr, + ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr. + +2008-01-22 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove CpuMMX2. + (cpu_flags): Likewise. + + * i386-opc.h (CpuMMX2): Removed. + (CpuSSE): Updated. + + * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-22 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and + CPU_SMX_FLAGS. + * i386-init.h: Regenerated. + +2008-01-15 H.J. Lu + + * i386-opc.tbl: Use Qword on movddup. + * i386-tbl.h: Regenerated. + +2008-01-15 H.J. Lu + + * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. + * i386-tbl.h: Regenerated. + +2008-01-15 H.J. Lu + + * i386-dis.c (Mx): New. + (PREFIX_0FC3): Likewise. + (PREFIX_0FC7_REG_6): Updated. + (dis386_twobyte): Use PREFIX_0FC3. + (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd. + Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on + movntss. + +2008-01-14 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add IntelSyntax. + (operand_types): Add Mem. + + * i386-opc.h (IntelSyntax): New. + * i386-opc.h (Mem): New. + (Byte): Updated. + (Opcode_Modifier_Max): Updated. + (i386_opcode_modifier): Add intelsyntax. + (i386_operand_type): Add mem. + + * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more + instructions. + + * i386-reg.tbl: Add size for accumulator. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-13 H.J. Lu + + * i386-opc.h (Byte): Fix a typo. + +2008-01-12 H.J. Lu + + PR gas/5534 + * i386-gen.c (operand_type_init): Add Dword to + OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. + (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, + Qword and Xmmword. + (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, + Xmmword, Unspecified and Anysize. + (set_bitfield): Make Mmword an alias of Qword. Make Oword + an alias of Xmmword. + + * i386-opc.h (CheckSize): Removed. + (Byte): Updated. + (Word): Likewise. + (Dword): Likewise. + (Qword): Likewise. + (Xmmword): Likewise. + (FWait): Updated. + (OTMax): Likewise. + (i386_opcode_modifier): Remove checksize, byte, word, dword, + qword and xmmword. + (Fword): New. + (TBYTE): Likewise. + (Unspecified): Likewise. + (Anysize): Likewise. + (i386_operand_type): Add byte, word, dword, fword, qword, + tbyte xmmword, unspecified and anysize. + + * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, + Tbyte, Xmmword, Unspecified and Anysize. + + * i386-reg.tbl: Add size for accumulator. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-10 H.J. Lu + + * i386-dis.c (REG_0F0E): Renamed to REG_0F0D. + (REG_0F18): Updated. + (reg_table): Updated. + (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e. + (twobyte_has_modrm): Set 1 for 0x19 to 0x1e. + +2008-01-08 H.J. Lu + + * i386-gen.c (set_bitfield): Use fail () on error. + +2008-01-08 H.J. Lu + + * i386-gen.c (lineno): New. + (filename): Likewise. + (set_bitfield): Report filename and line numer on error. + (process_i386_opcodes): Set filename and update lineno. + (process_i386_registers): Likewise. + +2008-01-05 H.J. Lu + + * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to + ATTSyntax. + + * i386-opc.h (IntelMnemonic): Renamed to .. + (ATTSyntax): This + (Opcode_Modifier_Max): Updated. + (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax + and intelsyntax. + + * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax + on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp. + * i386-tbl.h: Regenerated. + +2008-01-04 H.J. Lu + + * i386-gen.c: Update copyright to 2008. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-04 H.J. Lu + + * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps, + pextrb, pextrw, pinsrb, pinsrw and pmovmskb. + * i386-tbl.h: Regenerated. + +2008-01-03 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and + CpuSSE4_2_Or_ABM. + (cpu_flags): Likewise. + + * i386-opc.h (CpuSSE4_1_Or_5): Removed. + (CpuSSE4_2_Or_ABM): Likewise. + (CpuLM): Updated. + (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm. + + * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and + Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2 + and CpuPadLock, respectively. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-03 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove No_xSuf. + + * i386-opc.h (No_xSuf): Removed. + (CheckSize): Updated. + + * i386-tbl.h: Regenerated. + +2008-01-02 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to + CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and + CPU_SSE5_FLAGS. + (cpu_flags): Add CpuSSE4_2_Or_ABM. + + * i386-opc.h (CpuSSE4_2_Or_ABM): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpusse4_2_or_abm. + + * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of + CpuABM|CpuSSE4_2 on popcnt. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2008-01-02 H.J. Lu + + * i386-opc.h: Update comments. + +2008-01-02 H.J. Lu + + * i386-gen.c (opcode_modifiers): Use Qword instead of QWord. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + +2008-01-02 H.J. Lu + + PR gas/5534 + * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, + Byte, Word, Dword, QWord and Xmmword. + + * i386-opc.h (No_xSuf): New. + (CheckSize): Likewise. + (Byte): Likewise. + (Word): Likewise. + (Dword): Likewise. + (QWord): Likewise. + (Xmmword): Likewise. + (FWait): Updated. + (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, + Dword, QWord and Xmmword. + + * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is + used. + * i386-tbl.h: Regenerated. + +2008-01-02 Mark Kettenis + + * m88k-dis.c (instructions): Fix fcvt.* instructions. + From Miod Vallat. + +For older changes see ChangeLog-2007 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2009 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2009 new file mode 100644 index 000000000000..c5edeb1cee63 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2009 @@ -0,0 +1,1801 @@ +2009-12-19 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and + VexLWP. Add VexVVVV. + + * i386-opc.h (VexNDS): Removed. + (VexNDD): Likewise. + (VexLWP): Likewise. + (VEXXDS): New. + (VEXNDD): Likewise. + (VEXLWP): Likewise. + (VexVVVV): Likewise. + (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. + Add vexvvvv. + + * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with + VexVVVV=2 and VexLWP with VexVVVV=3. + * i386-tbl.h: Regenerated. + +2009-12-18 H.J. Lu + + * i386-gen.c (operand_types): Move Imm1 before Imm8. + +2009-12-17 Nick Clifton + + PR binutils/10924 + * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce + unique register numbers. Extend support for %<>R format to + thumb32 and coprocessor instructions. + +2009-12-16 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. + + * i386-opc.h (ByteOkIntel): Removed. + (i386_opcode_modifier): Remove byteokintel. + + * i386-opc.tbl: Remove ByteOkIntel. + * i386-tbl.h: Regenerated. + +2009-12-16 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, + Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. + + * i386-opc.h (Vex0F): Removed. + (Vex0F38): Likewise. + (Vex0F3A): Likewise. + (VexOpcode): New. + (VEX0F): Likewise. + (VEX0F38): Likewise. + (VEX0F3A): Likewise. + (XOP08): Defined as a macro. + (XOP09): Likewise. + (XOP0A): Likewise. + (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, + xop09 and xop0a. Add vexopcode. + + * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with + VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, + XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. + * i386-tbl.h: Regenerated. + +2009-12-15 H.J. Lu + + * i386-opc.h (VEX2SOURCES): Renamed to ... + (XOP2SOURCES): This. + +2009-12-15 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove Vex3Sources and + Vex2Sources. Add VexSources. + + * i386-opc.h (Vex2Sources): Removed. + (Vex3Sources): Likewise. + (VEX2SOURCES): New. + (VEX3SOURCES): Likewise. + (VexSources): Likewise. + (i386_opcode_modifier): Remove vex2sources and vex3sources. + Add vexsources. + + * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and + Vex3Sourceswith VexSources=2. + * i386-tbl.h: Regenerated. + +2009-12-15 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add + VexW. + + * i386-opc.h (VexW0): Removed. + (VexW1): Likewise. + (VEXW0): New. + (VEXW1): Likewise. + (VexW): Likewise. + (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. + + * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with + Vex=2. + * i386-tbl.h: Regenerated. + +2009-12-15 H.J. Lu + + * i386-dis.c (VEX_W_3818_P_2_M_0): New. + (vex_w_table): Add VEX_W_3818_P_2_M_0. + (mod_table): Use VEX_W_3818_P_2_M_0. + +2009-12-15 H.J. Lu + + * i386-dis.c (vex_w_table): Reformat. + +2009-12-15 H.J. Lu + + * i386-dis.c (VEX_W_382X_P_2_M_0): New. + (vex_w_table): Add VEX_W_382X_P_2_M_0. + (mod_table): Use VEX_W_382X_P_2_M_0. + +2009-12-15 H.J. Lu + + * i386-dis.c (vex_w_table): Reformat. + +2009-12-15 H.J. Lu + + * i386-dis.c (USE_VEX_W_TABLE): New. + (VEX_W_TABLE): Likewise. + (VEX_W_XXX): Likewise. + (vex_w_table): Likewise. + (prefix_table): Use VEX_W_XXX. + (vex_table): Likewise. + (vex_len_table): Likewise. + (mod_table): Likewise. + (get_valid_dis386): Handle USE_VEX_W_TABLE. + + * i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit + isn't used. + * i386-tbl.h: Regenerated. + +2009-12-15 H.J. Lu + + * i386-opc.h (VEX128): New. + (VEX256): Likewise. + +2009-12-14 H.J. Lu + + * i386-dis.c (vex_len_table): Reformat. + +2009-12-14 H.J. Lu + + * i386-dis.c (MOD_VEX_51): Renamed to ... + (MOD_VEX_50): This. + (vex_table): Updated. + (mod_table): Likewise. + +2009-12-14 Nick Clifton + + PR binutils/10924 + * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 + results in unpredictable behaviour. + (print_insn_arm): Handle %R. + +2009-12-11 H.J. Lu + + * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5 + prefix. + (print_insn): Don't set vex.w here. + +2009-12-11 H.J. Lu + + * i386-dis.c (print_insn): Set vex.w to 0. + +2009-12-11 Quentin Neill + + * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, + to avoid fetching ahead for the immediate bytes when OP_E_memory + has already been called. Fix indentation. + +2009-12-11 Nick Clifton + + * Makefile.in: Regenerate. + * configure: Regenerate. + * arm-dis.c: Fix shadowed variable warnings. + * cgen-opc.c: Likewise. + * cr16-dis.c: Likewise. + * crx-dis.c: Likewise. + * d30v-dis.c: Likewise. + * fr30-dis.c: Likewise. + * frv-opc.c: Likewise. + * h8500-dis.c: Likewise. + * i386-dis.c: Likewise. + * i960-dis.c: Likewise. + * ia64-gen.c: Likewise. + * ia64-opc.c: Likewise. + * m32c-asm.c: Likewise. + * m32c-dis.c: Likewise. + * m68k-dis.c: Likewise. + * maxq-dis.c: Likewise. + * mcore-dis.c: Likewise. + * mep-asm.c: Likewise. + * microblaze-dis.c: Likewise. + * mmix-dis.c: Likewise. + * ns32k-dis.c: Likewise. + * or32-opc.c: Likewise. + * s390-dis.c: Likewise. + * sh64-dis.c: Likewise. + * spu-dis.c: Likewise. + * tic30-dis.c: Likewise. + +2009-12-09 Nick Clifton + + PR 10924 + * arm-dis.c (print_insn_arm): Mark insns that use the PC in + post-indexed addressing as unpredictable. + +2009-12-03 H.J. Lu + + * i386-dis.c (FXSAVE_Fixup): New. + (FXSAVE): Likewise. + (mod_table): Use FXSAVE on fxsave and fxrstor. + + * i386-opc.tbl: Add fxsave64 and fxrstor64. + * i386-tbl.h: Regenerated. + +2009-12-02 Nick Clifton + Richard Earnshaw + + PR gas/11013 + * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB + and QDSUB. + +2009-11-30 Massimo Ruo Roch + + PR gas/11030 + * m68k-opc.c (m68k_opcodes): Allow the STLDSR instruction on the + Coldfire ISA A+. + +2009-11-17 Quentin Neill + Sebastian Pop + + * i386-dis.c (get_vex_imm8): Increase bytes_before_imm when + decoding the second source operand from the immediate byte. + (OP_EX_VexW): Pass an extra integer to identify the second + and third source arguments. + +2009-11-19 H.J. Lu + + * i386-opc.tbl: Add IsLockable to cmpxch16b. + * i386-tbl.h: Regenerated. + +2009-11-19 Nick Clifton + + PR binutils/10924 + * arm-dis.c (print_insn_arm): Do not print an offset of zero when + decoding Immediaate Offset addressing. + +2009-11-18 Sebastian Pop + + PR binutils/10973 + * i386-dis.c (get_vex_imm8): Do not increment codep. + Avoid incrementing bytes_before_imm when OP_E_memory + has already forwarded the codep pointer. + (OP_EX_VexW): Increment codep to skip mod/rm byte. + +2009-11-18 Sebastian Pop + + * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. + (VEX_LEN_XOP_08_A1): Removed. + (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and + VEX_LEN_XOP_08_A1. + (vex_len_table): Same. + * i386-gen.c (CPU_CVT16_FLAGS): Removed. + (cpu_flags): Remove field for CpuCVT16. + * i386-opc.h (CpuCVT16): Removed. + (i386_cpu_flags): Remove bitfield cpucvt16. + (i386-opc.tbl): Remove CVT16 instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Regenerated. + +2009-11-17 Sebastian Pop + Quentin Neill + + * i386-dis.c (OP_Vex_2src_1): New. + (OP_Vex_2src_2): New. + (Vex_2src_1): New. + (Vex_2src_2): New. + (XOP_08): Added. + (VEX_LEN_XOP_08_A0): Added. + (VEX_LEN_XOP_08_A1): Added. + (VEX_LEN_XOP_09_80): Added. + (VEX_LEN_XOP_09_81): Added. + (xop_table): Added an entry for XOP_08. Handle xop instructions. + (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, + VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. + (get_valid_dis386): Handle XOP_08. + (OP_Vex_2src): New. + * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. + (cpu_flags): Add CpuXOP and CpuCVT16. + (opcode_modifiers): Add XOP08, Vex2Sources. + * i386-opc.h (CpuXOP): Added. + (CpuCVT16): Added. + (i386_cpu_flags): Add cpuxop and cpucvt16. + (XOP08): Added. + (Vex2Sources): Added. + (i386_opcode_modifier): Add xop08, vex2sources. + * i386-opc.tbl: Add entries for XOP and CVT16 instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Regenerated. + +2009-11-17 Nick Clifton + + PR binutils/10924 + * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB + instruction variants. Add pattern for MRS variant that was being + confused with CMP. + (arm_decode_shift): Place error message in a comment. + (print_insn_arm): Note that writing back to the PC is + unpredictable. + Only print 'p' variants of cmp/cmn/teq/tst instructions if + decoding for pre-V6 architectures. + +2009-11-17 Edward Nevill + + * arm-dis.c (print_insn_thumb32): Handle undefined instruction. + +2009-11-14 Doug Evans + + * Makefile.am (stamp-xc16x): Use ../cpu/xc16x.cpu instead of + ../cgen/cpu. + * Makefile.in: Regenerate. + +2009-11-13 H.J. Lu + + * i386-dis.c (OP_E_extended): Removed. + +2009-11-13 H.J. Lu + + * i386-dis.c (print_insn): Check rex_ignored. + +2009-11-13 H.J. Lu + + * i386-dis.c (ckprefix): Updated to return 0 if number of + prefixes > 14 and record the last position for each prefix. + (lock_prefix): Removed. + (data_prefix): Likewise. + (addr_prefix): Likewise. + (repz_prefix): Likewise. + (repnz_prefix): Likewise. + (last_lock_prefix): New. + (last_repz_prefix): Likewise. + (last_repnz_prefix): Likewise. + (last_data_prefix): Likewise. + (last_addr_prefix): Likewise. + (last_rex_prefix): Likewise. + (last_seg_prefix): Likewise. + (MAX_CODE_LENGTH): Likewise. + (ADDR16_PREFIX): Likewise. + (ADDR32_PREFIX): Likewise. + (DATA16_PREFIX): Likewise. + (DATA32_PREFIX): Likewise. + (REP_PREFIX): Likewise. + (seg_prefix): Likewise. + (all_prefixes): Change size to MAX_CODE_LENGTH - 1. + (prefix_name): Handle ADDR16_PREFIX, ADDR32_PREFIX, + DATA16_PREFIX, DATA32_PREFIX and REP_PREFIX. + (get_valid_dis386): Updated. + (OP_C): Likewise. + (OP_Monitor): Likewise. + (REP_Fixup): Likewise. + (print_insn): Display all prefixes. + (putop): Set PREFIX_DATA on used_prefixes only if it is used. + (intel_operand_size): Likewise. + (OP_E_register): Likewise. + (OP_G): Likewise. + (OP_REG): Likewise. + (OP_IMREG): Likewise. + (OP_I): Likewise. + (OP_I64): Likewise. + (OP_sI): Likewise. + (CRC32_Fixup): Likewise. + (MOVBE_Fixup): Likewise. + (OP_E_memory): Set REFIX_DATA on used_prefixes when it is used + in 16bit mode. + (OP_J): Set REX_W used if it is used. Set PREFIX_DATA on + used_prefixes only if it is used. + +2009-11-12 H.J. Lu + + * i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc, + or, sbb, sub, xor and xchg with register only operands. + * i386-tbl.h: Regenerated. + +2009-11-12 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add IsLockable. + + * i386-opc.h (IsLockable): New. + (i386_opcode_modifier): Add islockable. + + * i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr, + bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub, + xor, xadd and xchg. + * i386-tbl.h: Regenerated. + +2009-11-12 Daniel Jacobowitz + + * arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove + generic coprocessor instructions for FPA loads and stores. + (print_insn_coprocessor): Remove %C support. Display address for + PC-relative offsets in %A. + +2009-11-11 H.J. Lu + + * i386-dis.c (all_prefixes): New. + (ckprefix): Set all_prefixes. + (print_insn): Print all_prefixes instead of lock_prefix, + repz_prefix, repnz_prefix, addr_prefix and data_prefix. + +2009-11-11 Nick Clifton + + PR binutils/10924 + * arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro. + (print_insn_arm): Extend %s format control code to check for + unpredictable addressing modes. Add support for %S format control + code which suppresses this check. + (W_BIT, I_BIT, U_BIT, P_BIT): New macros. + (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET, + PRE_BIT_SET): New macros. + (print_insn_coprocessor): Use the new macros instead of magic + constants. + (print_arm_address): Likewise. + (pirnt_insn_arm): Likewise. + (print_insn_thumb32): Likewise. + +2009-11-11 Nick Clifton + + * po/id.po: Updated Indonesian translation. + +2009-11-10 Maxim Kuvyrkov + + * m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01]. + +2009-11-06 Sebastian Pop + + * i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to + reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to + B.mm in the RXB.mmmmm byte, and so when B is set, we still should use + the xop_table. + (get_valid_dis386): Removed unused condition (from cut/n/paste) for + XOP instructions. + +2009-11-05 Sebastian Pop + Quentin Neill + + * opcodes/i386-dis.c (OP_LWPCB_E): New. + (OP_LWP_E): New. + (OP_LWP_I): New. + (USE_XOP_8F_TABLE): New. + (XOP_8F_TABLE): New. + (REG_XOP_LWPCB): New. + (REG_XOP_LWP): New. + (XOP_09): New. + (XOP_0A): New. + (reg_table): Redirect REG_8F to XOP_8F_TABLE. + Add entries for REG_XOP_LWPCB and REG_XOP_LWP. + (xop_table): New. + (get_valid_dis386): Handle USE_XOP_8F_TABLE. + Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values + to access to the vex_table. + (OP_LWPCB_E): New. + (OP_LWP_E): New. + (OP_LWP_I): New. + * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP. + (cpu_flags): Add CpuLWP. + (opcode_modifiers): Add VexLWP, XOP09, and XOP0A. + * opcodes/i386-opc.h (CpuLWP): New. + (i386_cpu_flags): Add bit cpulwp. + (VexLWP): New. + (XOP09): New. + (XOP0A): New. + (i386_opcode_modifier): Add vexlwp, xop09, and xop0a. + * opcodes/i386-opc.tbl (llwpcb): Added. + (lwpval): Added. + (lwpins): Added. + +2009-11-04 DJ Delorie + + * rx-decode.opc (rx_decode_opcode) (mvtipl): Add. + (mvtcp, mvfcp, opecp): Remove. + * rx-decode.c: Regenerate. + * rx-dis.c (cpen): Remove. + +2009-11-03 Doug Evans + + * m32c-desc.c: Regenerate. + * mep-desc.c: Regenerate. + +2009-11-02 Paul Brook + + * arm-dis.c (coprocessor_opcodes): Update to use new feature flags. + Add VFPv4 instructions. + +2009-10-29 Sebastian Pop + + * i386-dis.c (OP_VEX_FMA): Removed. + (VexFMA): Removed. + (Vex128FMA): Removed. + (prefix_table): First source operand of FMA4 insns is decoded + with Vex not with VexFMA. + (OP_EX_VexW): Second source operand is decoded with get_vex_imm8 + when vex.w is set. Third source operand is decoded with + +2009-10-27 Alan Modra + + * Makefile.am (HFILES): Remove cgen-ops.h and cgen-types.h. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2009-10-23 Doug Evans + + * cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h. + * cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h. + * cgen-bitset.c: Update. + * fr30-desc.h: Regenerate. + * frv-desc.h: Regenerate. + * ip2k-desc.h: Regenerate. + * iq2000-desc.h: Regenerate. + * lm32-desc.h: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-opc.h: Regenerate. + * m32r-desc.h: Regenerate. + * mep-desc.h: Regenerate. + * mt-desc.h: Regenerate. + * openrisc-desc.h: Regenerate. + * xc16x-desc.h: Regenerate. + * xstormy16-desc.h: Regenerate. + +2009-10-22 DJ Delorie + + * rx-decode.opc (decode_opcode): Fix flags for MUL, SUNTIL, and SWHILE. + * rx-decode.c: Regenerated. + +2009-10-20 H.J. Lu + + PR gas/10775 + * i386-dis.c: Document LB, LS and LV macros. + (dis386): Use mov%LB, mov%LS and mov%LV on mov instruction + with the 64-bit displacement or immediate operand. + (putop): Handle LB, LS and LV macros. + +2009-10-18 Doug Evans + + * lm32-opinst.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32r-opinst.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * xc16x-desc.c: Regenerate. + * xc16x-desc.h: Regenerate. + +2009-10-17 Doug Evans + + * Makefile.am (CGEN_CPUS): Add iq2000, lm32. + (FR30_DEPS, FRV_DEPS, IQ2000_DEPS): Move so all cgen *_DEPS are + sorted alphabetically. + (stamp-fr30, stamp-frv, stamp-iq2000, stamp-xc16x): Move so all cgen + stamp-* rules are sorted alphabetically. + * Makefile.in: Regenerate. + +2009-10-16 H.J. Lu + + * i386-opc.h: Use enum instead of nested macros. + +2009-10-16 H.J. Lu + + * i386-dis.c: Simplify enums. + +2009-10-15 H.J. Lu + Ineiev + + PR binutils/10767 + * i386-dis.c: Use enum instead of nested macros. + +2009-10-15 H.J. Lu + + * i386-dis.c (MAX_BYTEMODE): Removed. + +2009-10-14 Tomas Hurka + + PR 969 + * m68k-opc.c (m68k_opcodes): Correct mask for macl and msacl. + +2009-10-13 H.J. Lu + + * i386-dis.c (print_insn): Always clear need_vex, need_vex_reg + and vex_w_done. + +2009-10-07 Michael Eager + + * microblaze-dis.c: Add include for microblaze-dis.h, + eliminate local extern decls. + * microblaze-dis.h: New. + +2009-10-06 Nick Clifton + + * po/fi.po: Updated Finnish translation. + +2009-10-03 Andreas Schwab + + * opc2c.c: Include "libiberty.h" and . + (orig_filename): Constify. + (dump_lines): Fix line number directive. + (main): Set orig_filename to basename of input file. Use + xstrerror. + + * Makefile.am (rx-dis.lo): Remove explicit dependencies. + ($(srcdir)/rx-decode.c): Use @MAINT@. Use $(EXEEXT_FOR_BUILD) + instead of $(EXEEXT). + (opc2c$(EXEEXT_FOR_BUILD)): Renamed from opc2c$(EXEEXT) and use + $(LINK_FOR_BUILD). Link with libiberty. + (MOSTLYCLEANFILES): Add opc2c$(EXEEXT_FOR_BUILD). + (MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c. + * Makefile.in: Regenerated. + * rx-decode.c: Regenerated. + +2009-10-03 Paul Reed + + * arm-dis.c (print_insn): Check symtab_size not *symtab. + +2009-10-02 H.J. Lu + + * i386-opc.tbl: Drop Disp64 on jump and loop instructions. + * i386-tbl.h: Regenerated. + +2009-10-02 Peter Bergner + + * ppc-dis.c (ppc_opts): Add "476" entry. + * ppc-opc.c (PPC476): Define. + (powerpc_opcodes): Update mnemonics where required for 476. + +2009-10-01 Peter Bergner + + * ppc-opc.c (PPCA2): Use renamed mask PPC_OPCODE_A2. + * ppc-dis.c (ppc_opts): Likewise. + Rename "ppca2" to "a2". + +2009-10-01 M R Swami Reddy + + * crx-dis.c (match_opcode): Truncate mcode to 32-bit. + +2009-09-29 DJ Delorie + + * Makefile.am: Add RX files. + * configure.in: Add support for RX target. + * disassemble.c: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * opc2c.c: New file. + * rx-decode.c: New file. + * rx-decode.opc: New file. + * rx-dis.c: New file. + +2009-09-29 Peter Bergner + + * ppc-opc.c (powerpc_opcodes): Remove support for the the "lxsdux", + "lxvd2ux", "lxvw4ux", "stxsdux", "stxvd2ux" and "stxvw4ux" opcodes. + +2009-09-25 Michael Eager + + * microblaze-dis.c (get_insn_microblaze, microblaze_get_target_address, + microblaze_decode_insn): Add declarations. + (get_delay_slots_microblaze): Remove. + +2009-09-25 Martin Thuresson + + Update sources to make arc and arm targets compile cleanly with + -Wc++-compat: + * arc-dis.c Fix casts. + * arc-ext.c: Add casts. + * arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous + enum. + +2009-09-24 H.J. Lu + + * i386-gen.c (opcode_modifiers): Remove Vex256. + (set_bitfield): Handle XXX=V. + + * i386-opc.h (Vex): Update comments. + (Vex256): Removed. + (VexNDS): Updated. + (i386_opcode_modifier): Change vex to 2 bits. Remove vex256. + + * i386-opc.tbl: Replace "Vex|Vex256" with Vex=2. + * i386-tbl.h: Regenerated. + +2009-09-23 Nick Clifton + + * po/fr.po: Updated French translation. + +2009-09-21 Ben Elliston + Peter Bergner + + * ppc-dis.c (ppc_opts): Add "ppca2" entry. + * ppc-opc.c (powerpc_opcodes): Add eratilx, eratsx, eratsx., + eratre, wchkall, eratwe, ldawx., mdfcrx., mfdcr. mtdcrx., icswx, + icswx., mtdcr., dci, wclrone, wclrall, wclr, erativax, tlbsrx., + ici mnemonics. + (ERAT_T): New operand. + (XWC_MASK): New mask. + (XOPL2): New macro. + (PPCA2): Define. + +2009-09-18 Nick Clifton + + * po/es.po: Updated Spanish translation. + * po/vi.po: Updated Vietnamese translation. + +2009-09-15 H.J. Lu + + * i386-dis.c (OP_E_memory): Don't print '-' in Intel mode if + disp == -disp. + +2009-09-14 Nick Clifton + + * po/nl.po: Updated Dutch translation. + +2009-09-11 Nick Clifton + + * po/opcodes.pot: Updated by the Translation project. + +2009-09-11 Martin Thuresson + + Updated sources to compile cleanly with -Wc++-compat: + * ld.h (enum endian_enum,enum symbolic_enum,enum dynamic_list_enum): Move to top level. + * ldcref.c: Add casts. + * ldctor.c: Add casts. + * ldexp.c + * ldexp.h (enum node_tree_enum,enum phase_enum): Move to top level. + * ldlang.c: Add casts. (lang_insert_orphan): Use enum name instead of integer. + * ldlang.h (enum statement_enum): Move to top level. + * ldmain.c: Add casts. + * ldwrite.c: Add casts. + * lexsup.c: Add casts. (enum control_enum): Move to top level. + * mri.c: Add casts. (mri_draw_tree): Use enum name instead of integer. + +2009-09-10 Andreas Krebbel + + * s390-dis.c (print_insn_s390): Avoid 'long long'. + +2009-09-10 Andreas Krebbel + + * s390-dis.c (s390_extract_operand): Remove the shift for pcrel operands. + (print_insn_s390): Signextend and shift pcrel operands before printing. + +2009-09-09 H.J. Lu + + * i386-dis.c (vex_len_table): Change VEX_LEN_AE_R_X_M0 to + VEX_LEN_AE_R_X_M_0 in comments. + +2009-09-08 DJ Delorie + + * mep-opc.c: Regenerate. + +2009-09-08 Andreas Schwab + + * z8kgen.c (struct op): Replace unused flavor with id. + (opt): Remove extra xorb entry. + (func): Use id field as fallback. + (sub): Return new string, caller changed. + (internal): Allocate end marker. Assign unique id before sorting. + (gas): Likewise. Fix loop end condition. + * z8k-opc.h: Regenerate. + +2009-09-08 Alan Modra + + * ppc-opc.c (powerpc_macros ): Allow n+b of 64. + +2009-09-07 Alan Modra + + * z8kgen.c (func): Fix thinko last patch. + +2009-09-07 Alan Modra + + * z8kgen.c (func): Stabilize qsort of identically named entries. + * z8k-opc.h: Regenerate. + +2009-09-07 Tristan Gingold + + * po/opcodes.pot: Regenerate. + +2009-09-07 Alan Modra + + * configure.in (BUILD_LIBS, BUILD_LIB_DEPS): Define and subst. + * configure: Regenerate. + * Makefile.am (LIBIBERTY, BUILD_LIBIBERTY, BUILD_LIBINTL): Delete. + (BUILD_LIBS, BUILD_LIB_DEPS): Define. Use.. + (i386-gen, ia64-gen, z8kgen): ..here. + * Makefile.in: Regenerate. + +2009-09-07 Tristan Gingold + + * z8k-opc.h: Regenerate. + +2009-09-05 Martin Thuresson + + * ia64-dis.c (print_insn_ia64): Update code to use renamed member. + * m88k-dis.c (m88kdis): Rename variable class to in_class. + * tic80-opc.c (tic80_symbol_to_value, tic80_value_to_symbol): + Rename argument class to symbol_class. + +2009-09-04 Jie Zhang + + * bfin-dis.c (decode_pseudodbg_assert_0): Change according + to the new encoding of DBGA, DBGAH, and DBGAL. + (_print_insn_bfin): Likewise. + +2009-09-03 Jie Zhang + + * bfin-dis.c (_print_insn_bfin): Don't declare. + (print_insn_bfin): Don't declare. + (dregs_pair): Remove. + (ignore_bits): Remove. + (ccstat): Remove. + +2009-09-03 Jie Zhang + + * bfin-dis.c (IS_DREG): Define. + (IS_PREG): Define. + (IS_AREG): Define. + (IS_GENREG): Define. + (IS_DAGREG): Define. + (IS_SYSREG): Define. + (decode_REGMV_0): Check illegal register move instructions. + +2009-09-03 Dave Korn + + * Makefile.am (BUILD_LIBINTL): New variable. + (i386-gen$(EXEEXT_FOR_BUILD)): Use it. + (ia64-gen$(EXEEXT_FOR_BUILD)): And here. + (z8kgen$(EXEEXT_FOR_BUILD)): And here. + * Makefile.in: Regenerate. + +2009-09-01 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mep-opc.c: Regenerate. + +2009-09-01 Tristan Gingold + + * makefile.vms: Ported to Itanium VMS. Remove useless targets and + dependencies. Remove unused FORMAT variable. + * configure.com: New file to create build.com DCL script for + Itanium VMS or Alpha VMS. + +2009-08-29 Martin Thuresson + + * cris-dis.c (bytes_to_skip): Update code to use new name. + * i386-dis.c (putop): Update code to use new name. + * i386-gen.c (process_i386_opcodes): Update code to use + new name. + * i386-opc.h (struct template): Rename struct template to + insn_template. Update code accordingly. + * i386-tbl.h (i386_optab): Update type to use new name. + * ia64-dis.c (print_insn_ia64): Rename variable template + to template_val. + * tic30-dis.c (struct instruction, get_tic30_instruction): + Update code to use new name. + * tic54x-dis.c (has_lkaddr, get_insn_size) + (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): + Update code to use new name. + * tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): + Update type to new name. + * z8kgen.c (internal, gas): Rename variable new to new_op. + +2009-08-28 H.J. Lu + + * Makefile.am (COMPILE_FOR_BUILD): Remove BUILD_CPPFLAGS. + Replace BUILD_CFLAGS with CFLAGS_FOR_BUILD. + (LINK_FOR_BUILD): Replace BUILD_CFLAGS/BUILD_LDFLAGS with + CFLAGS_FOR_BUILD/LDFLAGS_FOR_BUILD. + * Makefile.in: Regenerated. + +2009-08-27 Ralf Wildenhues + + * Makefile.am (bfdlibdir, bfdincludedir): Move definition ... + [INSTALL_LIBBFD]: ... here, ... + [INSTALL_LIBBFD]: ... and empty overrides here. + [!INSTALL_LIBBFD]: (rpath_bfdlibdir): New variable. + [!INSTALL_LIBBFD] (libbfd_la_LDFLAGS): Use it. + * Makefile.in: Regenerate. + * configure: Regenerate. + +2009-08-26 Philippe De Muyter + + * m68k-dis.c (print_insn_arg): Add movecr register names for + coldfire v4e families. + +2009-08-25 Ralf Wildenhues + + * Makefile.am (SUBDIRS): Build '.' before 'po'. + (COMPILE_FOR_BUILD, LINK_FOR_BUILD, BUILD_LIBIBERTY) + (MOSTLYCLEANFILES, MAINTAINERCLEANFILES): New variables. + (i386-gen$(EXEEXT_FOR_BUILD)): Renamed from i386-gen, rewrite + using *BUILD variables, depend upon $(BUILD_LIBIBERTY). + (i386-gen.o): New rule. + ($(srcdir)/i386-init.h): Adjust. + (i386-opc.lo): Depend on $(srcdir)/i386-tbl.h. + (ia64-gen$(EXEEXT_FOR_BUILD)): Rename from ia64-gen, adjust likewise. + (ia64-gen.o): New rule. + (ia64_asmtab_deps): New variable. + ($(srcdir)/ia64-asmtab.c): Use it; adjust likewise. + (ia64-opc.lo): Depend on $(srcdir)/ia64-asmtab.c. + (s390-mkopc$(EXEEXT_FOR_BUILD)): Rename from s390-mkopc, adjust + likewise. + (s390-opc.tab): Adjust. + (z8kgen$(EXEEXT_FOR_BUILD), z8kgen.o, $(srcdir)/z8k-opc.h): New + rules. + (z8k-dis.lo): Depend on $(srcdir)/z8k-opc.h. + * Makefile.in: Regenerate. + * z8kgen.c (gas): Avoid '/*' in comment. + * z8k-opc.h (func): Regenerate. + +2009-08-24 Ralf Wildenhues + + * Makefile.am (TARGET_LIBOPCODES_CFILES): New variable, taken + from $(CFILES), sorted, with dis-buf.c, dis-init.c, disassemble.c, + i386-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-d.c, ia64-gen.c, ia64-asmtab.c removed, and + msp430-dis.c added. + (LIBOPCODES_CFILES): New variable, adding to + TARGET_LIBOPCODES_CFILES also non-target library sources. + (CFILES): Factorize based on $(LIBOPCODES_CFILES), adding generator + files. + (ALL_MACHINES): Factorize based on $(TARGET_LIBOPCODES_CFILES). + (EXTRA_libopcodes_la_SOURCES): Use $(LIBOPCODES_CFILES). + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2009-08-22 Ralf Wildenhues + + * Makefile.am (libopcodes_la_LDFLAGS): Initialize early. + [INSTALL_LIBBFD] (bfdlib_LTLIBRARIES): Set only in this condition. + [INSTALL_LIBBFD] (bfdinclude_DATA): New. + [!INSTALL_LIBBFD] (noinst_LTLIBRARIES): New. + [!INSTALL_LIBBFD] (libopcodes_la_LDFLAGS): Ensure libopcodes.la + is built shared even if it is not to be installed. + (install-bfdlibLTLIBRARIES,uninstall-bfdlibLTLIBRARIES) + (install_libopcodes, uninstall_libopcodes): Remove. + (AM_CPPFLAGS): Renamed from ... + (INCLUDES): ... this. + * Makefile.in: Regenerate. + + * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9 and cygnus, add + 1.11, foreign, no-dist. + (MKDEP, m32c_opc_h): Remove variables. + (disassemble.lo): Rewrite using automake-style dependency + tracking rules; only list the dependency upon the primary source + file, but no included headers. + (m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo, m32c-opc.lo) + (i386-gen.o, ia64-gen.o): Remove dependency statements. + (EXTRA_libopcodes_la_SOURCES): New variable, list $(CFILES) to + ensure all dependency fragments are included in the Makefile. + (s390-opc.lo): Depend on s390-opc.tab. + (DEP, DEP1, dep.sed, dep, dep-in, dep-am): Remove rules. + (mkdep section): Remove. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + + * Makefile.am (install-pdf, install-html): Remove. + * Makefile.in: Regenerate. + + * Makefile.in: Regenerate. + * aclocal.m4: Likewise. + * config.in: Likewise. + * configure: Likewise. + +2009-08-06 Michael Eager + + * Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to + CFILES, microblaze-dis.lo to ALL_MACHINES, targets. + * Makefile.in: Regenerate. + * configure.in: Add bfd_microblaze_arch target. + * configure: Regenerate. + * disassemble.c: Define ARCH_microblaze, return + print_insn_microblaze(). + * microblaze-dis.c: New MicroBlaze disassembler. + * microblaze-opc.h: New MicroBlaze opcode definitions. + * microblaze-opcm.h: New MicroBlaze opcode types. + +2009-07-25 H.J. Lu + + * configure.in: Handle bfd_l1om_arch. + * disassemble.c (disassembler): Likewise. + + * configure: Regenerated. + + * i386-dis.c (print_insn): Handle bfd_mach_l1om and + bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. + + * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. + Add CPU_L1OM_FLAGS. + (cpu_flags): Add CpuL1OM. + (set_bitfield): Take an argument to set the value field. + (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). + (process_i386_opcode_modifier): Updated. + (process_i386_operand_type): Likewise. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + + * i386-opc.h (CpuL1OM): New. + (CpuXsave): Updated. + (i386_cpu_flags): Add cpul1om. + +2009-07-24 Jan Beulich + + * i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add + frstpm. + * i386-gen.c (cpu_flag_init): Add FP enabling flags where needed. + (cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP. + (set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387. + * i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP): + Define. + (union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687, + and cpufisttp. + * i386-opc.tbl: Qualify floating point instructions by their + respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos, + and fsincos to be avilable only on 387. Fix fstsw ax to be + available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm, + and frstpm. + * i386-init.h, i386-tbl.h: Regenerate. + +2009-07-20 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register + offset or indexed based addressing mode 3. + +2009-07-14 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1 + patterns. + (arm_decode_shift): Catch illegal register based shifts. + (print_insn_arm): Properly handle negative register r0 + post-indexed addressing. + +2009-07-10 Doug Kwan + + * arm-disc.c (print_insn_coprocessor, print_insn_arm): Print only + lower 32 bits of long types to make hexadecimal output consistent + on both 32-bit and 64-bit hosts. + +2009-07-10 Alan Modra + + * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, * fr30-opc.h, + * frv-desc.c, * frv-desc.h, * frv-opc.c, * frv-opc.h, + * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, * ip2k-opc.h, + * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, * iq2000-opc.h, + * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opc.h, + * lm32-opinst.c, * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, + * m32c-opc.h, * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, + * m32r-opc.h, * m32r-opinst.c, * mt-desc.c, * mt-desc.h, + * mt-opc.c, * mt-opc.h, * openrisc-desc.c, * openrisc-desc.h, + * openrisc-opc.c, * openrisc-opc.h, * xc16x-desc.c, * xc16x-desc.h, + * xc16x-opc.c, * xc16x-opc.h, * xstormy16-desc.c, * xstormy16-desc.h, + * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. + +2009-07-07 Chung-Lin Tang + + * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus. + +2009-07-07 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Be more strict about decoding scaled + addressing modes. + +2009-07-06 DJ Delorie + + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-07-06 Dwarakanath Rajagopal + + * i386-opc.h (CpuFMA4): Add CpuFMA4. + (i386_cpu_flags): New. + * i386-gen.c: Add CPU_FMA4_FLAGS. + * i386-opc.tbl: Add FMA4 instructions. + * i386-tbl.h: Regenerate. + * i386-init.h: Regenerate. + * i386-dis.c (OP_VEX_FMA): New. Handle FMA4. + (OP_XMM_VexW): Ditto. + (OP_EX_VexW): Ditto. + (VEXI4_Fixup): Ditto. + (VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros. + (PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New. + (PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New. + (PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New. + (PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New. + (PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New. + (PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New. + (PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New. + (VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New. + (VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New. + (VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New. + (get_vex_imm8): New. handle FMA4. + (OP_EX_VexReg): Ditto. + +2009-06-30 Nick Clifton + + PR 10288 + * arm-dis.c (coprocessor): Print the LDC and STC versions of the + LFM and SFM instructions as comments,. + Improve consistency of formatting for instructions displayed as + comments and decimal values displayed with their hexadecimal + equivalents. + Formatting tidy ups. + +2009-06-29 Nick Clifton + + PR 10288 + * arm-dis.c (enum opcode_sentinels): New: Used to mark the + boundary between variaant and generic coprocessor instuctions. + (coprocessor): Use it. + Fix architecture version of MCRR and MRRC instructions. + (arm_opcdes): Fix patterns for STRB and STRH instructions. + (print_insn_coprocessor): Check architecture and extension masks. + Print a hexadecimal version of any decimal constant that is + outside of the range of -16 to +32. + (print_arm_address): Add a return value of the offset used in the + adress, if it is worth printing a hexadecimal version of it. + (print_insn_neon): Print a hexadecimal version of any decimal + constant that is outside of the range of -16 to +32. + (print_insn_arm): Likewise. + (print_insn_thumb16): Likewise. + (print_insn_thumb32): Likewise. + + PR 10297 + * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description + of an undefined instruction. + (arm_opcodes): Use it. + (thumb_opcod): Use it. + (thumb32_opc): Use it. + +2009-06-23 DJ Delorie + + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + + * mep-asm.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-06-22 Nick Clifton + + * po/fi.po: Updated Finish translation. + +2009-06-22 Alan Modra + + * m32c-asm.c: Regenerate. + +2009-06-22 Alan Modra + + * score-dis.c (print_insn_score48, print_insn_score32): Move default + case label to proper lexical block. + * score7-dis.c (print_insn_score32): Likewise. + +2009-06-19 Martin Schwidefsky + + * s390-opc.c (INSTR_RR_0R_OPT, INSTR_RX_0RRD_OPT, MASK_RR_0R_OPT, + MASK_RX_0RRD_OPT): New instruction formats with optional arguments. + * s390-opc.txt (nopr, nop): Use new instruction format. + +2009-06-18 Nick Clifton + + PR 10288 + * arm-dis.c (print_insn_coprocessor): Check that a user specified + ARM architecture supports the matched instruction. + (print_insn_arm): Likewise. + (select_arm_features): New function. Fills in the fields of an + arm_feature_set structure based on a given arm machine number. + (print_insn): Initialise an arm_feature_set structure. + +2009-06-16 Maciej W. Rozycki + + * vax-dis.c (is_function_entry): Return success for synthetic + symbols too. + (is_plt_tail): New function. + (print_insn_vax): Decode PLT entry offset longword. + +2009-06-15 Nick Clifton + + PR 10186 + * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W + instruction. + + PR 10173 + * cr16-dis.c (print_arg): Avoid printing the 0x prefix twice. + +2009-06-15 Nick Clifton + + PR 10263 + * arm-dis.c (print_insn): Ignore is_data if the user has requested + the disassembly of data as well as instructions. + +2009-06-11 Doug Evans + + * cgen.sh: Handle multiple simultaneous runs for parallel makes. + +2009-06-11 Anthony Green + + * moxie-opc.c (moxie_form1_opc_info): Remove branch instructions. + (moxie_form3_opc_info): Add branch instructions. + * moxie-dis.c (print_insn_moxie): Disassemble MOXIE_F3_PCREL + encoded instructions. + +2009-06-06 Anthony Green + + * moxie-opc.c: Recode some MOXIE_F1_4 opcodes as MOXIE_F1_M. + * moxie-dis.c (print_insn_moxie): Handle MOXIE_F1_M case. + +2009-06-04 Alan Modra + + * dep-in.sed: Don't use \n in replacement part of s command. + * Makefile.am (DEP1): LC_ALL for uniq. + * Makefile.in: Regenerate. + +2009-06-02 Nick Clifton + + * po/nl.po: Updated Dutch translation. + +2009-06-02 Tristan Gingold + + * ia64-gen.c (parse_resource_users, print_dependency_table, + add_dis_table_ent, finish_distable, insert_bit_table_ent, + add_dis_entry, compact_distree, gen_dis_table, completer_entries_eq, + get_prefix_len, compute_completer_bits, insert_opcode_dependencies, + insert_completer_entry, print_completer_entry, print_completer_table, + opcodes_eq, add_opcode_entry, shrink): Use ISO C syntax for functions. + +2009-05-28 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + +2009-05-26 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-05-26 Nick Clifton + + * po/id.po: Updated Indonesian translation. + * po/opcodes.pot: Updated template file. + +2009-05-26 Alan Modra + + * dep-in.sed: Don't modify .o to .lo here. Output one filename + per line with all lines having continuation backslash. Prefix + first line with "A", following lines with "B". + * Makefile.am (DEP): Don't use dep.sed here. + (DEP1): Run $MKDEP on single files, modify .o to .lo here. Use + dep.sed here on dependencies, sort and uniq. + * Makefile.in: Regenerate. + +2009-05-25 Tristan Gingold + + * makefile.vms (OPT): New variable. + (CFLAGS): Update compilation flags. + +2009-05-22 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-05-22 Dwarakanath Rajagopal + + * i386-opc.h (Cpusse5): Delete. + (i386_cpu_flags): Delete. + * i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc. + * i386-opc.tbl: Remove SSE5 instructions. + * i386-tbl.h: Regenerate. + * i386-init.h: Regenerate. + * i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling. + (print_drex_arg): Delete. + (OP_DREX4): Delete. + (OP_DREX3): Delete. + (OP_DREX_ICMP): Delete. + (OP_DREX_FCMP): Delete. + (DREX_*): Delete. + (THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete. + +2009-05-22 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2009-05-19 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-opc.c: Regenerate. + +2009-04-30 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-04-17 DJ Delorie + + * moxie-opc.c, moxie-dis.c: Created. + * Makefile.am: Build the moxie source files. + * configure.in: Add moxie support. + * Makefile.in, configure: Rebuilt. + * disassemble.c (disassembler): Add moxie support. + (ARCH_moxie): Define. + +2009-04-15 Jan Beulich + + * i386-opc.tbl (protb, protw, protd, protq): Set opcode + extension to None. + (pshab, pshaw, pshad, pshaq): Likewise. + * i386-tbl.h: Re-generate. + +2009-04-08 DJ Delorie + + * ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva", + "tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation. + Reorder entries so the extended mnemonics are listed before tlbilx. + +2009-04-02 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect + due to -many/-Many. + (print_insn_powerpc): Make sure we only deprecate instructions using + the original dialect and not a modified dialect due to -Many handling. + Move the handling of the condition register and default operands to + the end of the if/else if/else chain. + * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that + instructions from newer processors are listed before older ones. + <"icblce", "sync", "eieio", "tlbld">: Deprecate for processors + that have instructions with conflicting opcodes. + +2009-04-01 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and + E500MC entries. + +2009-04-01 Christophe Lyon + + * arm-dis.c (print_insn): Print BE8 opcodes in little endianness. + +2009-03-30 Joseph Myers + + * arm-dis.c (print_insn): Also check section matches in backwards + search for mapping symbol. + +2009-03-26 H.J. Lu + + * i386-dis.c (get_valid_dis386): Abort on unhandled table. + +2009-03-18 Alan Modra + + * cgen-opc.c: Include alloca-conf.h rather than alloca.h. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * openrisc-opc.c: Regenerate. + +2009-03-10 Nick Clifton + + * po/id.po: Updated Indonesian translation. + +2009-03-10 Alan Modra + + * ppc-dis.c: Include "opintl.h". + (struct ppc_mopt, ppc_opts): New. + (ppc_parse_cpu): New function. + (powerpc_init_dialect): Use it. + (print_ppc_disassembler_options): Dump options from ppc_opts. + Internationalize message. + +2009-03-06 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2009-03-04 Alan Modra + + PR 6768 + * configure.in: Test for ld --as-needed support. Link shared + libopcodes against libm. + * configure: Regenerate. + +2009-03-03 Peter Bergner + + * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that + instructions from newer processors are listed before older ones. + +2009-03-03 Alan Modra + + * Makefile.am: Run "make dep-am". + (HFILES): Move lm32-desc.h and lm32-opc.h from.. + (CFILES): ..here. + * Makefile.in: Regenerate. + +2009-03-02 Qinwei + + * score7-dis.c: New file. + * Makefile.am: Add dependencies for score7-dis.c. + * Makefile.in: Regenerate. + * configure.in: Add score7-dis to score files. + * configure: Regenerate. + * score-dis.c: Add support for score7 architecture. + * score-opc.h: Likewise. + +2009-03-01 Ralf Wildenhues + + * configure: Regenerate. + +2009-02-27 H.J. Lu + + * i386-dis.c (OP_EX): Call OP_E_memory instead of OP_E. + +2009-02-26 Peter Bergner + + * ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble + the power7 and the isel instructions. + * ppc-opc.c (insert_xc6, extract_xc6): New static functions. + (insert_dm, extract_dm): Likewise. + (XB6): Update comment to include XX2 form. + (WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK, + XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New. + (RemoveXX3DM): Delete. + (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr", + "mftgpr">: Deprecate for POWER7. + <"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte", + "frsqrte.">: Deprecate the three operand form and enable the two + operand form for POWER7 and later. + <"wait">: Extend to accept optional parameter. Enable for POWER7. + <"waitsrv", "waitimpl">: Add extended opcodes. + <"ldbrx", "stdbrx">: Enable for POWER7. + <"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes. + <"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde", + "divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo", + "divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.", + "divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.", + "fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.", + "fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx", + "lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes. + <"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx", + "stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp", + "xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds", + "xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp", + "xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp", + "xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp", + "xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic", + "xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp", + "xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp", + "xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp", + "xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.", + "xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp", + "xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp", + "xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp", + "xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp", + "xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp", + "xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp", + "xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp", + "xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp", + "xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp", + "xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi", + "xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp", + "xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp", + "xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp", + "xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor", + "xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd", + "xxspltw", "xxswapd">: Add VSX opcodes. + +2009-02-23 H.J. Lu + + * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4. + (operand_types): Remove Vex_Imm4. + + * i386-opc.h (Vex_Imm4): Removed. + (OTMax): Updated. + (i386_operand_type): Remove vex_imm4. + + * i386-opc.tbl: Remove Vex_Imm4 comments. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2009-02-23 Richard Earnshaw + + * arm-dis.c (neon_opcodes): Correct bit-mask and patterns for + vq{r}shr{u}n.s64 insnstructions. + +2009-02-19 Peter Bergner + + * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first + operand to be a float point register (FRT/FRS). + +2009-02-18 Adam Nemet + + * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific + dmfc2 and dmtc2 before the architecture-level variants. + +2009-02-18 Pierre Muller + + * fr30-opc.c: Regenerate. + * frv-opc.c: Regenerate. + * ip2k-opc.c: Regenerate. + * iq2000-opc.c: Regenerate. + * lm32-opc.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32r-opc.c: Regenerate. + * mep-opc.c: Regenerate. + * mt-opc.c: Regenerate. + * xc16x-opc.c: Regenerate. + * xstormy16-opc.c: Regenerate. + * tic54x-dis.c (print_instruction): Avoid compiler warning on + sprintf call. + +2009-02-12 Nathan Sidwell + + * m68k-opc.c (m68k_opcodes): Add stldsr instruction. + +2009-02-05 Peter Bergner + + * ppc-opc.c: Update copyright year. + (powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand + ordering for POWER4 and later and use the correct Server ordering. + +2009-02-04 H.J. Lu + + AVX Programming Reference (January, 2009) + * i386-dis.c (PREFIX_VEX_3A44): New. + (VEX_LEN_3A44_P_2): Likewise. + (PREFIX_VEX_3A48): Updated. + (VEX_LEN_3A4C_P_2): Likewise. + (prefix_table): Add PREFIX_VEX_3A44. + (vex_table): Likewise. + (vex_len_table): Add VEX_LEN_3A44_P_2. + + * i386-opc.tbl: Add PCLMUL + AVX instructions. + * i386-tbl.h: Regenerated. + +2009-02-03 Sandip Matte + + * mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define. + (mips_arch_choices): Add XLR entry. + * mips-opc.c (XLR): Define. + (mips_builtin_opcodes): Add XLR instructions. + +2009-02-03 Carlos O'Donell + + * Makefile.am: Add install-pdf target. + * po/Make-in: Add install-pdf target. + * Makefile.in: Regenerate. + +2009-02-02 DJ Delorie + + * mep-asm.c: Regenerate. + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-01-29 Mark Mitchell + + * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, + qsub, and qdsub. + +2009-01-28 Chao-ying Fu + + * mips-opc.c (suxc1): Add the flag of FP_D. + +2009-01-20 Alan Modra + + * fr30-asm.c, fr30-dis.c, fr30-ibld.c, frv-asm.c, frv-dis.c, + * frv-ibld.c, ip2k-asm.c, ip2k-dis.c, ip2k-ibld.c, + * iq2000-asm.c, iq2000-dis.c, iq2000-ibld.c, m32c-asm.c, + * m32c-dis.c, m32c-ibld.c, m32r-asm.c, m32r-dis.c, + * m32r-ibld.c, mep-asm.c, mep-dis.c, mep-ibld.c, mt-asm.c, + * mt-dis.c, mt-ibld.c, openrisc-asm.c, openrisc-dis.c, + * openrisc-ibld.c, xc16x-asm.c, xc16x-dis.c, xc16x-ibld.c, + * xstormy16-asm.c, xstormy16-dis.c, xstormy16-ibld.c: Regenerate. + +2009-01-16 Alan Modra + + * configure.in (commonbfdlib): Delete. + (SHARED_LIBADD): Add pic libiberty if such is available. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2009-01-14 Peter Bergner + + * ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated. + * ppc-opc.c (powerpc_opcodes) : Deprecate the two + operand form and enable the four operand form for POWER6 and later. + : Deprecate the two operand form and enable the + three operand form for POWER6 and later. + +2009-01-14 Mike Frysinger + + * bfin-dis.c (OUTS): Use "%s" as format string. + +2009-01-13 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove a white space. + (operand_type_init): Likewise. + +2009-01-12 H.J. Lu + + * i386-opc.tbl: Add NoAVX to movnti, lfence and mfence. + * i386-tbl.h: Regenerated. + +2009-01-12 H.J. Lu + + * i386-dis.c (dis386): Use EbS on addB, orB, adcB, sbbB, andB, + subB, xorB and cmpB. Use EvS on addS, orS, adcS, sbbS, andS, + subS, xorS and cmpS. + +2009-01-10 H.J. Lu + + * i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with + CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add + CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS. + (cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush + and CpuSYSCALL. + (lineno): Removed. + (set_bitfield): Take an argument, lineno. Don't report lineno + on error if it is -1. + (process_i386_cpu_flag): Take an argument, lineno. + (process_i386_opcode_modifier): Likewise. + (process_i386_operand_type): Likewise. + (output_i386_opcode): Likewise. + (opcode_hash_entry): Add lineno. + (process_i386_opcodes): Updated. + (process_i386_registers): Likewise. + (process_i386_initializers): Likewise. + + * i386-opc.h (CpuP4): Removed. + (CpuK6): Likewise. + (CpuK8): Likewise. + (CpuClflush): New. + (CpuSYSCALL): Likewise. + (CpuMMX): Updated. + (i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add + cpuclflush and cpusyscall. + + * i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause, + syscall and sysret. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2009-01-09 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS + and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS. + (cpu_flags): Add CpuRdtscp. + (set_bitfield): Remove CpuSledgehammer check. + + * i386-opc.h (CpuRdtscp): New. + (CpuLM): Updated. + (i386_cpu_flags): Add cpurdtscp. + + * i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2009-01-09 Peter Bergner + + * ppc-opc.c (PPCNONE): Define. + (NOPOWER4): Delete. + (powerpc_opcodes): Initialize the new "deprecated" field. + +2009-01-06 H.J. Lu + + AVX Programming Reference (December, 2008) + * i386-dis.c (VEX_LEN_2B_M_0): Removed. + (VEX_LEN_E7_P_2_M_0): Likewise. + (VEX_LEN_2C_P_1): Updated. + (VEX_LEN_E8_P_2): Likewise. + (vex_len_table): Remove VEX_LEN_2B_M_0 and VEX_LEN_E7_P_2_M_0. + (mod_table): Likewise. + + * i386-opc.tbl: Add 256bit vmovntdq, vmovntpd and vmovntps. + * i386-tbl.h: Regenerated. + +2009-01-05 H.J. Lu + + * i386-gen.c (process_copyright): Update for 2009. + + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2009-01-05 H.J. Lu + + AVX Programming Reference (December, 2008) + * i386-dis.c (OP_VEX_FMA): Removed. + (OP_EX_VexW): Likewise. + (OP_EX_VexImmW): Likewise. + (OP_XMM_VexW): Likewise. + (VEXI4_Fixup): Likewise. + (VPERMIL2_Fixup): Likewise. + (VexI4): Likewise. + (VexFMA): Likewise. + (Vex128FMA): Likewise. + (EXVexW): Likewise. + (EXdVexW): Likewise. + (EXqVexW): Likewise. + (EXVexImmW): Likewise. + (XMVexW): Likewise. + (VPERMIL2): Likewise. + (PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise. + (PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise. + (PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise. + (PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise. + (VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise. + (VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise. + (get_vex_imm8): Likewise. + (OP_EX_VexReg): Likewise. + vpermil2_op): Likewise. + (EXVexWdq): New. + (vex_w_dq_mode): Likewise. + (PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise. + (PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise. + (PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise. + (es_reg): Updated. + (PREFIX_VEX_38DB): Likewise. + (PREFIX_VEX_3A4A): Likewise. + (PREFIX_VEX_3A60): Likewise. + (PREFIX_VEX_3ADF): Likewise. + (VEX_LEN_3ADF_P_2): Likewise. + (prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A, + PREFIX_VEX_3A5C...PREFIX_VEX_3A5F, + PREFIX_VEX_3A68...PREFIX_VEX_3A6F and + PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add + PREFIX_VEX_3896...PREFIX_VEX_389F, + PREFIX_VEX_38A6...PREFIX_VEX_38AF and + PREFIX_VEX_38B6...PREFIX_VEX_38BF. + (vex_table): Likewise. + (vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2 + and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2. + (putop): Support "%XW". + (intel_operand_size): Handle vex_w_dq_mode. + + * i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS. + + * i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA + instructions. Add new FMA instructions. + * i386-tbl.h: Regenerated. + +2009-01-02 Matthias Klose + + * or32-opc.c (or32_print_register, or32_print_immediate, + disassemble_insn): Don't rely on undefined sprintf behaviour. + +For older changes see ChangeLog-2008 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-2010 b/external/gpl3/gdb/dist/opcodes/ChangeLog-2010 new file mode 100644 index 000000000000..34a8d3054233 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-2010 @@ -0,0 +1,1012 @@ +2010-12-31 John David Anglin + + PR gas/11395 + * hppa-dis.c (compare_cond_64_names): Change never condition to ",*". + (add_cond_64_names): Likewise. + (logical_cond_64_names): Likewise. + (unit_cond_64_names): Likewise. + +2010-12-30 H.J. Lu + + * i386-dis.c (print_insn): Support bfd_mach_x64_32 and + bfd_mach_x64_32_intel_syntax. + +2010-12-18 Mingjie Xing + + * mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define. + (mips_builtin_opcodes): Add loongson3a specific instructions. + * mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z. + +2010-12-11 Mingming Sun + + * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and + fixed point instructions. + +2010-12-09 Mike Frysinger + + * .gitignore: New file. + +2010-11-25 Alan Modra + + * po/es.po: Update. + * po/fr.po: Update. + * po/nl.po: Update. + * po/zh_CN.po: Update. + +2010-11-11 Mingming Sun + + * mips-dis.c (mips_arch_choices): Add loongson3a. + * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A. + (mips_builtin_opcodes): Modify some instructions' membership from + IL2F to IL2F|IL3A. + +2010-11-10 Nick Clifton + + * po/fi.po: Updated Finnish translation. + +2010-11-05 Tristan Gingold + + * po/opcodes.pot: Regenerate + +2010-10-28 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld". + +2010-10-28 Andreas Krebbel + + * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5. + +2010-10-25 Chao-ying Fu + + * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32. + +2010-10-25 Nathan Sidwell + + * tic6x-dis.c: Add attribution. + +2010-10-22 Alan Modra + + * Makefile.am (CLEANFILES): Add stamp-lm32. Sort. + * Makefile.in: Regenerate. + +2010-10-18 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB + macros before their corresponding MIPS III hardware instructions. + +2010-10-16 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. + + * i386-init.h: Regenerated. + +2010-10-15 Mike Frysinger + + * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M. + +2010-10-14 H.J. Lu + + * i386-opc.tbl: Remove CheckRegSize from movq. + * i386-tbl.h: Regenerated. + +2010-10-14 H.J. Lu + + * i386-opc.tbl: Remove CheckRegSize from instructions with + 0, 1 or fixed operands. + * i386-tbl.h: Regenerated. + +2010-10-14 H.J. Lu + + * i386-gen.c (opcode_modifiers): Add CheckRegSize. + + * i386-opc.h (CheckRegSize): New. + (i386_opcode_modifier): Add checkregsize. + + * i386-opc.tbl: Add CheckRegSize to instructions which + require register size check. + * i386-tbl.h: Regenerated. + +2010-10-12 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Move fnop before fbf. + +2010-10-11 Andreas Krebbel + + * s390-opc.c: Make the instruction masks for the load/store on + condition instructions to cover the condition code mask as well. + * s390-opc.txt: lgoc -> locg and stgoc -> stocg. + +2010-10-11 Jan Kratochvil + Jiang Jilin + + * Makefile.am (libopcodes_a_SOURCES): New as empty. + * Makefile.in: Regenerate. + +2010-10-09 Matt Rice + + * fr30-desc.h: Regenerate. + * frv-desc.h: Regenerate. + * ip2k-desc.h: Regenerate. + * iq2000-desc.h: Regenerate. + * lm32-desc.h: Regenerate. + * m32c-desc.h: Regenerate. + * m32r-desc.h: Regenerate. + * mep-desc.h: Regenerate. + * mep-opc.c: Regenerate. + * mt-desc.h: Regenerate. + * openrisc-desc.h: Regenerate. + * xc16x-desc.h: Regenerate. + * xstormy16-desc.h: Regenerate. + +2010-10-08 Pierre Muller + + Fix build with -DDEBUG=7 + * frv-opc.c: Regenerate. + * or32-dis.c (DEBUG): Don't redefine. + (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register): + Adapt DEBUG code to some type changes throughout. + * or32-opc.c (or32_extract): Likewise. + +2010-10-07 Bernd Schmidt + + * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field + in SPKERNEL instructions. + +2010-10-02 H.J. Lu + + PR binutils/12076 + * i386-dis.c (RMAL): Remove duplicate. + +2010-09-30 Pierre Muller + + * s390-mkopc.c (main): Exit with error 1 if sscanf fails + to parse all 6 parameters. + +2010-09-28 Pierre Muller + + * s390-mkopc.c (main): Change description array size to 80. + Add maximum length of 79 to description parsing. + +2010-09-27 Ralf Wildenhues + + * configure: Regenerate. + +2010-09-27 Andreas Krebbel + + * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. + (main): Recognize the new CPU string. + * s390-opc.c: Add new instruction formats and masks. + * s390-opc.txt: Add new z196 instructions. + +2010-09-27 Andreas Krebbel + + * s390-dis.c (print_insn_s390): Pick instruction with most + specific mask. + * s390-opc.c: Add unused bits to the insn mask. + * s390-opc.txt: Reorder some instructions to prefer more recent + versions. + +2010-09-27 Tejas Belagod + + * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment + correction to unaligned PCs while printing comment. + +2010-09-23 Matthew Gretton-Dann + + * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. + (thumb32_opcodes): Likewise. + (banked_regname): New function. + (print_insn_arm): Add Virtualization Extensions support. + (print_insn_thumb32): Likewise. + +2010-09-23 Matthew Gretton-Dann + + * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in + ARM state. + +2010-09-23 Matthew Gretton-Dann + + * arm-dis.c (arm_opcodes): SMC implies Security Extensions. + (thumb32_opcodes): Likewise. + +2010-09-23 Matthew Gretton-Dann + + * arm-dis.c (arm_opcodes): Add support for pldw. + (thumb32_opcodes): Likewise. + +2010-09-22 Robin Getz + + * bfin-dis.c (fmtconst): Cast address to 32bits. + +2010-09-22 Mike Frysinger + + * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks. + +2010-09-22 Robin Getz + + * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns. + Reject P6/P7 to TESTSET. + (decode_PushPopReg_0): Check for parallel insns. Reject pushing + SP onto the stack. + (decode_PushPopMultiple_0): Check for parallel insns. Make sure + P/D fields match all the time. + (decode_CCflag_0): Check for parallel insns. Verify x/y fields + are 0 for accumulator compares. + (decode_CC2stat_0): Check for parallel insns. Reject CCCC. + (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0, + decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0, + decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0, + decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0, + decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel + insns. + (decode_dagMODim_0): Verify br field for IREG ops. + (decode_LDST_0): Reject preg load into same preg. + (_print_insn_bfin): Handle returns for ILLEGAL decodes. + (print_insn_bfin): Likewise. + +2010-09-22 Mike Frysinger + + * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5. + +2010-09-22 Robin Getz + + * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag. + +2010-09-22 Mike Frysinger + + * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits. + +2010-09-22 Robin Getz + + * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject + register values greater than 8. + (IS_RESERVEDREG, allreg, mostreg): New helpers. + (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate. + (decode_PushPopReg_0): Call mostreg/allreg as appropriate. + (decode_CC2dreg_0): Check valid CC register number. + +2010-09-22 Robin Getz + + * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG. + +2010-09-22 Robin Getz + + * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD. + (reg_names): Likewise. + (decode_statbits): Likewise; while reformatting to make manageable. + +2010-09-22 Mike Frysinger + + * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC. + (decode_pseudoOChar_0): New function. + (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0. + +2010-09-22 Robin Getz + + * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as + LSHIFT instead of SHIFT. + +2010-09-22 Mike Frysinger + + * bfin-dis.c (constant_formats): Constify the whole structure. + (fmtconst): Add const to return value. + (reg_names): Mark const. + (decode_multfunc): Mark s0/s1 as const. + (decode_macfunc): Mark a/sop as const. + +2010-09-17 Tejas Belagod + + * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv. + +2010-09-14 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", + "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". + +2010-09-10 Pierre Muller + + * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for + dlx_insn_type array. + +2010-08-31 H.J. Lu + + PR binutils/11960 + * i386-dis.c (sIv): New. + (dis386): Replace Iq with sIv on "pushT". + (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. + (x86_64_table): Replace {T|}/{P|} with P. + (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. + (OP_sI): Update v_mode. Remove w_mode. + +2010-08-27 Nathan Froyd + + * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate + on E500 and E500MC. + +2010-08-17 H.J. Lu + + * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and + prefetchw. + +2010-08-06 Quentin Neill + + * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add + to processor flags for PENTIUMPRO processors and later. + * i386-opc.h (enum): Add CpuNop. + (i386_cpu_flags): Add cpunop bit. + * i386-opc.tbl: Change nop cpu_flags. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2010-08-06 Quentin Neill + + * i386-opc.h (enum): Fix typos in comments. + +2010-08-06 Alan Modra + + * disassemble.c: Formatting. + (disassemble_init_for_target ): Comment on endian. + +2010-08-05 H.J. Lu + + * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. + * i386-tbl.h: Regenerated. + +2010-08-05 H.J. Lu + + * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. + + * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. + * i386-tbl.h: Regenerated. + +2010-07-29 DJ Delorie + + * rx-decode.opc (SRR): New. + (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov + r0,r0) and NOP3 (max r0,r0) special cases. + * rx-decode.c: Regenerate. + +2010-07-28 H.J. Lu + + * i386-dis.c: Add 0F to VEX opcode enums. + +2010-07-27 DJ Delorie + + * rx-decode.opc (store_flags): Remove, replace with F_* macros. + (rx_decode_opcode): Likewise. + * rx-decode.c: Regenerate. + +2010-07-23 Naveen.H.S + Ina Pandit + + * v850-dis.c (v850_sreg_names): Updated structure for system + registers. + (float_cc_names): new structure for condition codes. + (print_value): Update the function that prints value. + (get_operand_value): New function to get the operand value. + (disassemble): Updated to handle the disassembly of instructions. + (print_insn_v850): Updated function to print instruction for different + families. + * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1, + extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3, + extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6, + insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop, + extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16, + extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22, + extract_d22, insert_d23, extract_d23, insert_i9, extract_i9, + insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New. + (insert_d8_7, insert_d5_4, insert_i5div): Remove. + (v850_operands): Update with the relocation name. Also update + the instructions with specific set of processors. + +2010-07-08 Tejas Belagod + + * arm-dis.c (print_insn_arm): Add cases for printing more + symbolic operands. + (print_insn_thumb32): Likewise. + +2010-07-06 Maciej W. Rozycki + + * mips-dis.c (print_insn_mips): Correct branch instruction type + determination. + +2010-07-06 Maciej W. Rozycki + + * mips-dis.c (print_mips16_insn_arg): Remove branch instruction + type and delay slot determination. + (print_insn_mips16): Extend branch instruction type and delay + slot determination to cover all instructions. + * mips16-opc.c (BR): Remove macro. + (UBR, CBR): New macros. + (mips16_opcodes): Update branch annotation for "b", "beqz", + "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" + and "jrc". + +2010-07-05 H.J. Lu + + AVX Programming Reference (June, 2010) + * i386-dis.c (mod_table): Replace rdrnd with rdrand. + * i386-opc.tbl: Likewise. + * i386-tbl.h: Regenerated. + +2010-07-05 H.J. Lu + + * i386-opc.h (CpuFSGSBase): Fix a typo in comments. + +2010-07-03 Andreas Schwab + + * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to + ppc_cpu_t before inverting. + (ppc_parse_cpu): Likewise. + (print_insn_powerpc): Likewise. + +2010-07-03 Alan Modra + + * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. + * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. + (PPC64, MFDEC2): Update. + (NON32, NO371): Define. + (powerpc_opcode): Update to not use old opcode flags, and avoid + -m601 duplicates. + +2010-07-03 DJ Delorie + + * m32c-ibld.c: Regenerate. + +2010-07-03 Alan Modra + + * ppc-opc.c (PWR2COM): Define. + (PPCPWR2): Add PPC_OPCODE_COMMON. + (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", + "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", + "rac" from -mcom. + +2010-07-01 H.J. Lu + + AVX Programming Reference (June, 2010) + * i386-dis.c (PREFIX_0FAE_REG_0): New. + (PREFIX_0FAE_REG_1): Likewise. + (PREFIX_0FAE_REG_2): Likewise. + (PREFIX_0FAE_REG_3): Likewise. + (PREFIX_VEX_3813): Likewise. + (PREFIX_VEX_3A1D): Likewise. + (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, + PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and + PREFIX_VEX_3A1D. + (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. + (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, + PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. + + * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, + CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. + (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. + + * i386-opc.h (CpuXsaveopt): New. + (CpuFSGSBase): Likewise. + (CpuRdRnd): Likewise. + (CpuF16C): Likewise. + (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and + cpuf16c. + + * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, + wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2010-07-01 Sebastian Andrzej Siewior + + * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf + and mtocrf on EFS. + +2010-06-29 Alan Modra + + * maxq-dis.c: Delete file. + * Makefile.am: Remove references to maxq. + * configure.in: Likewise. + * disassemble.c: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2010-06-29 Alan Modra + + * mep-dis.c: Regenerate. + +2010-06-28 Matthew Gretton-Dann + + * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax. + +2010-06-27 Alan Modra + + * arc-dis.c (arc_sprintf): Delete set but unused variables. + (decodeInstr): Likewise. + * dlx-dis.c (print_insn_dlx): Likewise. + * h8300-dis.c (bfd_h8_disassemble_init): Likewise. + * maxq-dis.c (check_move, print_insn): Likewise. + * mep-dis.c (mep_examine_ivc2_insns): Likewise. + * msp430-dis.c (msp430_branchinstr): Likewise. + * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning. + * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise. + * sparc-dis.c (print_insn_sparc): Likewise. + * fr30-asm.c: Regenerate. + * frv-asm.c: Regenerate. + * ip2k-asm.c: Regenerate. + * iq2000-asm.c: Regenerate. + * lm32-asm.c: Regenerate. + * m32c-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + * mep-asm.c: Regenerate. + * mt-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + * xc16x-asm.c: Regenerate. + * xstormy16-asm.c: Regenerate. + +2010-06-16 Vincent Rivière + + PR gas/11673 + * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. + +2010-06-16 Vincent Rivière + + PR binutils/11676 + * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. + +2010-06-14 Sebastian Andrzej Siewior + + * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and + e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 + * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which + touch floating point regs and are enabled by COM, PPC or PPCCOM. + Treat sync as msync on e500. Treat eieio as mbar 1 on e500. + Treat lwsync as msync on e500. + +2010-06-07 Matthew Gretton-Dann + + * arm-dis.c (thumb-opcodes): Add disassembly for movs. + +2010-05-28 Matthew Gretton-Dann + + * arm-dis.c (print_insn_neon): Ensure disassembly of Neon + constants is the same on 32-bit and 64-bit hosts. + +2010-05-27 Jason Duerstock + + * m68k-dis.c (print_insn_m68k): Emit undefined instructions as + .short directives so that they can be reassembled. + +2010-05-26 Catherine Moore + David Ung + + * mips-opc.c: Change membership to I1 for instructions ssnop and + ehb. + +2010-05-26 H.J. Lu + + * i386-dis.c (sib): New. + (get_sib): Likewise. + (print_insn): Call get_sib. + OP_E_memory): Use sib. + +2010-05-26 Catherine Moore + + * mips-dis.c (mips_arch): Remove INSN_MIPS16. + * mips-opc.c (I16): Remove. + (mips_builtin_op): Reclassify jalx. + +2010-05-19 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, + divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx. + +2010-05-13 Alan Modra + + * ppc-opc.c (powerpc_opcodes): Correct wclr encoding. + +2010-05-11 Matthew Gretton-Dann + + * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W + format. + (print_insn_thumb16): Add support for new %W format. + +2010-05-07 Tristan Gingold + + * Makefile.in: Regenerate with automake 1.11.1. + * aclocal.m4: Ditto. + +2010-05-05 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2010-04-22 Nick Clifton + + * po/opcodes.pot: Updated by the Translation project. + * po/vi.po: Updated Vietnamese translation. + +2010-04-16 H.J. Lu + + * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown + bits in opcode. + +2010-04-09 Nick Clifton + + * i386-dis.c (print_insn): Remove unused variable op. + (OP_sI): Remove unused variable mask. + +2010-04-07 Alan Modra + + * configure: Regenerate. + +2010-04-06 Peter Bergner + + * ppc-opc.c (RBOPT): New define. + ("dccci"): Enable for PPCA2. Make operands optional. + ("iccci"): Likewise. Do not deprecate for PPC476. + +2010-04-02 Masaki Muranaka + + * cr16-opc.c (cr16_instruction): Fix typo in comment. + +2010-03-25 Joseph Myers + + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c. + * Makefile.in: Regenerate. + * configure.in (bfd_tic6x_arch): New. + * configure: Regenerate. + * disassemble.c (ARCH_tic6x): Define if ARCH_all. + (disassembler): Handle TI C6X. + * tic6x-dis.c: New. + +2010-03-24 Mike Frysinger + + * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2. + +2010-03-23 Joseph Myers + + * dis-buf.c (buffer_read_memory): Give error for reading just + before the start of memory. + +2010-03-22 Sebastian Pop + Quentin Neill + + * i386-dis.c (OP_LWP_I): Removed. + (reg_table): Do not use OP_LWP_I, use Iq. + (OP_LWPCB_E): Remove use of names16. + (OP_LWP_E): Same. + * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns + should not set the Vex.length bit. + * i386-tbl.h: Regenerated. + +2010-02-25 Edmar Wienskoski + + * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64". + +2010-02-24 Nick Clifton + + PR binutils/6773 + * arm-dis.c (arm_opcodes): Replace addsubx with + asx. Replace subaddx with sax. + (thumb32_opcodes): Likewise. + +2010-02-15 Nick Clifton + + * po/vi.po: Updated Vietnamese translation. + +2010-02-12 Doug Evans + + * lm32-opinst.c: Regenerate. + +2010-02-11 Doug Evans + + * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL. + (print_address): Delete CGEN_PRINT_ADDRESS. + * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c, + * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h, + * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c, + * xc16x-dis.c, * xstormy16-dis.c: Regenerate. + + * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, + * frv-desc.c, * frv-desc.h, * frv-opc.c, + * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, + * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, + * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c, + * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, + * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c, + * mep-desc.c, * mep-desc.h, * mep-opc.c, + * mt-desc.c, * mt-desc.h, * mt-opc.c, + * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c, + * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c, + * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate. + +2010-02-11 H.J. Lu + + * i386-dis.c: Update copyright. + * i386-gen.c: Likewise. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + +2010-02-10 Quentin Neill + Sebastian Pop + + * i386-dis.c (OP_EX_VexImmW): Reintroduced + function to handle 5th imm8 operand. + (PREFIX_VEX_3A48): Added. + (PREFIX_VEX_3A49): Added. + (VEX_W_3A48_P_2): Added. + (VEX_W_3A49_P_2): Added. + (prefix table): Added entries for PREFIX_VEX_3A48 + and PREFIX_VEX_3A49. + (vex table): Added entries for VEX_W_3A48_P_2 and + and VEX_W_3A49_P_2. + * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 + for Vec_Imm4 operands. + * i386-opc.h (enum): Added Vec_Imm4. + (i386_operand_type): Added vec_imm4. + * i386-opc.tbl: Add entries for vpermilp[ds]. + * i386-init.h: Regenerated. + * i386-tbl.h: Regenerated. + +2010-02-10 Richard Sandiford + + * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" + and "pwr7". Move "a2" into alphabetical order. + +2010-02-08 Philipp Tomsich + + * ppc-dis.c (ppc_opts): Add titan entry. + * ppc-opc.c (TITAN, MULHW): Define. + (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). + +2010-02-03 Quentin Neill + + * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS + to CPU_BDVER1_FLAGS + * i386-init.h: Regenerated. + +2010-02-03 Anthony Green + + * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to + 0x0f, and make 0x00 an illegal instruction. + +2010-01-29 Daniel Jacobowitz + + * opcodes/arm-dis.c (struct arm_private_data): New. + (print_insn_coprocessor, print_insn_arm): Update to use struct + arm_private_data. + (is_mapping_symbol, get_map_sym_type): New functions. + (get_sym_code_type): Check the symbol's section. Do not check + mapping symbols. + (print_insn): Default to disassembling ARM mode code. Check + for mapping symbols separately from other symbols. Use + struct arm_private_data. + +2010-01-28 H.J. Lu + + * i386-dis.c (EXVexWdqScalar): New. + (vex_scalar_w_dq_mode): Likewise. + (prefix_table): Update entries for PREFIX_VEX_3899, + PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, + PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, + PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, + PREFIX_VEX_38BD and PREFIX_VEX_38BF. + (intel_operand_size): Handle vex_scalar_w_dq_mode. + (OP_EX): Likewise. + +2010-01-27 H.J. Lu + + * i386-dis.c (XMScalar): New. + (EXdScalar): Likewise. + (EXqScalar): Likewise. + (EXqScalarS): Likewise. + (VexScalar): Likewise. + (EXdVexScalarS): Likewise. + (EXqVexScalarS): Likewise. + (XMVexScalar): Likewise. + (scalar_mode): Likewise. + (d_scalar_mode): Likewise. + (d_scalar_swap_mode): Likewise. + (q_scalar_mode): Likewise. + (q_scalar_swap_mode): Likewise. + (vex_scalar_mode): Likewise. + (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, + VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, + VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, + VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, + VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, + VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, + VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, + VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, + VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, + VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. + (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, + VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, + VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, + VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, + VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, + VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, + VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, + VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, + VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. + (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, + q_scalar_mode, q_scalar_swap_mode. + (OP_XMM): Handle scalar_mode. + (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode + and q_scalar_swap_mode. + (OP_VEX): Handle vex_scalar_mode. + +2010-01-24 H.J. Lu + + * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. + +2010-01-24 H.J. Lu + + * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }. + +2010-01-24 H.J. Lu + + * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }. + +2010-01-24 H.J. Lu + + * i386-dis.c (Bad_Opcode): New. + (bad_opcode): Likewise. + (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. + (dis386_twobyte): Likewise. + (reg_table): Likewise. + (prefix_table): Likewise. + (x86_64_table): Likewise. + (vex_len_table): Likewise. + (vex_w_table): Likewise. + (mod_table): Likewise. + (rm_table): Likewise. + (float_reg): Likewise. + (reg_table): Remove trailing "(bad)" entries. + (prefix_table): Likewise. + (x86_64_table): Likewise. + (vex_len_table): Likewise. + (vex_w_table): Likewise. + (mod_table): Likewise. + (rm_table): Likewise. + (get_valid_dis386): Handle bytemode 0. + +2010-01-23 H.J. Lu + + * i386-opc.h (VEXScalar): New. + + * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar + instructions. + * i386-tbl.h: Regenerated. + +2010-01-21 H.J. Lu + + * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. + + * i386-opc.tbl: Add xsave64 and xrstor64. + * i386-tbl.h: Regenerated. + +2010-01-20 Nick Clifton + + PR 11170 + * arm-dis.c (print_arm_address): Do not ignore negative bit in PC + based post-indexed addressing. + +2010-01-15 Sebastian Pop + + * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. + * i386-tbl.h: Regenerated. + +2010-01-14 H.J. Lu + + * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in + comments. + +2010-01-14 H.J. Lu + + * i386-dis.c (names_mm): New. + (intel_names_mm): Likewise. + (att_names_mm): Likewise. + (names_xmm): Likewise. + (intel_names_xmm): Likewise. + (att_names_xmm): Likewise. + (names_ymm): Likewise. + (intel_names_ymm): Likewise. + (att_names_ymm): Likewise. + (print_insn): Set names_mm, names_xmm and names_ymm. + (OP_MMX): Use names_mm, names_xmm and names_ymm. + (OP_XMM): Likewise. + (OP_EM): Likewise. + (OP_EMC): Likewise. + (OP_MXC): Likewise. + (OP_EX): Likewise. + (XMM_Fixup): Likewise. + (OP_VEX): Likewise. + (OP_EX_VexReg): Likewise. + (OP_Vex_2src): Likewise. + (OP_Vex_2src_1): Likewise. + (OP_Vex_2src_2): Likewise. + (OP_REG_VexI4): Likewise. + +2010-01-13 H.J. Lu + + * i386-dis.c (print_insn): Update comments. + +2010-01-12 H.J. Lu + + * i386-dis.c (rex_original): Removed. + (ckprefix): Remove rex_original. + (print_insn): Update comments. + +2010-01-09 Ralf Wildenhues + + * Makefile.in: Regenerate. + * configure: Regenerate. + +2010-01-07 Doug Evans + + * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup. + * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, + * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, + * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, + * xstormy16-ibld.c: Regenerate. + +2010-01-06 Quentin Neill + + * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. + * i386-init.h: Regenerated. + +2010-01-06 Daniel Gutson + + * arm-dis.c (print_insn): Fixed search for next symbol and data + dumping condition, and the initial mapping symbol state. + +2010-01-05 Doug Evans + + * cgen-ibld.in: #include "cgen/basic-modes.h". + * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, + * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, + * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, + * xstormy16-ibld.c: Regenerate. + +2010-01-04 Nick Clifton + + PR 11123 + * arm-dis.c (print_insn_coprocessor): Initialise value. + +2010-01-04 Edmar Wienskoski + + * ppc-dis.c (ppc_opts): Add entry for "e500mc64". + +2010-01-02 Doug Evans + + * cgen-asm.in: Update copyright year. + * cgen-dis.in: Update copyright year. + * cgen-ibld.in: Update copyright year. + * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, + * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, + * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, + * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, + * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, + * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, + * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, + * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, + * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, + * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, + * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, + * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, + * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, + * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, + * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, + * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, + * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, + * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, + * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, + * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, + * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. + +For older changes see ChangeLog-2009 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-9297 b/external/gpl3/gdb/dist/opcodes/ChangeLog-9297 new file mode 100644 index 000000000000..799457e22354 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-9297 @@ -0,0 +1,3797 @@ +Mon Dec 22 12:37:06 1997 Ian Lance Taylor + + * mips-opc.c: Add FP_D to s.d instruction flags. + +Wed Dec 17 11:38:29 1997 Andreas Schwab + + * m68k-opc.c (halt, pulse): Enable them on the 68060. + +Tue Dec 16 15:22:53 1997 Fred Fish + + * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit + PC relative offset forms before the 15 bit forms. An assembler command + line option now chooses the default. + +Tue Dec 16 15:22:51 1997 Michael Meissner + + * d30v-opc.c (d30v_opcode_table): Set new flags bits + FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. + +1997-12-15 Brendan Kehoe + + * configure: Only build libopcodes shared if --enable-shared's value + was `yes', or was set to `*opcodes*'. + * aclocal.m4: Likewise. + * NOTE: this really needs to be fixed in libtool/libtool.m4, the + original source of this bit of code. It's not clear what the best fix + would be, though. + +Fri Dec 12 11:57:04 1997 Fred Fish + + * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. + (tic80_opcodes): Reorder table entries to put the 32 bit PC relative + offset forms before the 15 bit forms, to default to the long forms. + +Fri Dec 12 01:32:30 1997 Richard Henderson + + * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. + +Wed Dec 10 17:42:35 1997 Nick Clifton + + * arm-dis.c (print_insn_little_arm): Prevent examination of stored + symbol if none is present. + (print_insn_big_arm): Prevent examination of stored symbol if + none is present. + +Thu Oct 23 21:13:37 1997 Fred Fish + + * d10v-opc.c (d10v_opcodes): Correct entry for RTE. + +Mon Dec 8 11:21:07 1997 Nick Clifton + + * disassemble.c: Remove disasm_symaddr() function. + + * arm-dis.c: Use info->symbol instead of info->flags to determine + if disassmbly should be in Thumb or Arm mode. + +Tue Dec 2 09:54:27 1997 Nick Clifton + + * arm-dis.c: Add support for disassembling Thumb opcodes. + (print_insn_thumb): New function. + + * disassemble.c (disasm_symaddr): New function. + + * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. + (thumb_opcodes): Table of Thumb opcodes. + +Mon Dec 1 12:25:57 1997 Andreas Schwab + + * m68k-opc.c (btst): Change Dd@s to Dd;b. + + * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', + and 'v' as operand types. + +Mon Dec 1 11:56:50 1997 Ian Lance Taylor + + * m68k-opc.c: Add argument for lpstop. From Olivier Carmona + . + * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, + which has a two word opcode with a one word argument. + +Sun Nov 23 22:25:21 1997 Michael Meissner + + * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is + unsigned, not signed. + (d30v_format_table): Add SHORT_CMPU cases for cmpu. + +Tue Nov 18 23:10:03 1997 J"orn Rennecke + + * d10v-dis.c (print_operand): + Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. + +Tue Nov 18 18:45:14 1997 J"orn Rennecke + + * d10v-opc.c (OPERAND_FLAG): Split into: + (OPERAND_FFLAG, OPERAND_CFLAG) . + (FSRC): Split into: + (FFSRC, CFSRC). + +Thu Nov 13 11:05:33 1997 Gavin Koch + + * mips-opc.c: Move the INSN_MACRO ISA value to the membership + field for all INSN_MACRO's. + * mips16-opc.c: same + +Wed Nov 12 10:16:57 1997 Gavin Koch + + * mips-opc.c (sync,cache): These are 3900 insns. + +Tue Nov 11 23:53:41 1997 J"orn Rennecke + + sh-opc.h (sh_table): Remove ftst/nan. + +Tue Oct 28 17:59:32 1997 Ken Raeburn + + * mips-opc.c (ffc, ffs): Fix mask. + +Tue Oct 28 16:34:54 1997 Michael Meissner + + * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m + control registers. + +Mon Oct 27 22:34:03 1997 Ken Raeburn + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Mon Oct 27 22:34:03 1997 Ken Raeburn + + * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. + (WR_HILO, RD_HILO, MOD_HILO): New macros. + +Thu Oct 23 14:57:58 1997 Nick Clifton + + * v850-dis.c (disassemble): Replace // with /* ... */ + +Wed Oct 22 17:33:21 1997 Richard Henderson + + * sparc-opc.c: Add wr & rd for v9a asr's. + * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. + (v9a_asr_reg_names): New variable. + Patch from David Miller . + +Wed Oct 22 17:18:02 1997 Richard Henderson + + * sparc-opc.c (v9notv9a): New insn type. + (IMPDEP): Move to the end to not conflict with edge8 et al. + Patch from David Miller . + +Fri Oct 17 13:18:53 1997 Gavin Koch + + * mips-opc.c (bnezl,beqzl): Mark these as also tx39. + +Thu Oct 16 11:55:20 1997 Gavin Koch + + * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. + +Tue Oct 14 16:10:31 1997 Nick Clifton + + * v850-dis.c (disassemble): Use new symbol_at_address_func() field + of disassemble_info structure to determine if an overlay address + has a matching symbol in low memory. + + * dis-buf.c (generic_symbol_at_address): New (dummy) function for + new symbol_at_address_func field in disassemble_info structure. + +Fri Oct 10 16:44:52 1997 Nick Clifton + + * v850-opc.c (extract_d22): Use signed arithmatic. + +Tue Oct 7 23:40:43 1997 Gavin Koch + + * mips-opc.c: Three op mult is not an ISA insn. + +Tue Oct 7 23:37:21 1997 Gavin Koch + + * mips-opc.c: Fix formatting. + +Fri Oct 3 17:26:54 1997 Ian Lance Taylor + + * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather + than assuming that char is signed. Explicitly sign extend 16 bit + values, rather than assuming that short is 16 bits. + (OP_sI, OP_J, OP_DIR): Likewise. + +Thu Oct 2 13:36:45 1997 Nick Clifton + + * v850-dis.c (v850_sreg_names): Use symbolic names for higher + system registers. + +Wed Oct 1 16:58:54 1997 Nick Clifton + + * v850-opc.c: Fix typo in comment. + + * v850-dis.c (disassemble): Add test of processor type when + determining opcodes. + +Wed Oct 1 14:10:20 1997 Ian Lance Taylor + + * configure.in: Use a diversion to set enable_shared before the + arguments are parsed. + * configure: Rebuild. + +Thu Sep 25 13:04:59 1997 Ian Lance Taylor + + * m68k-opc.c (TBL1): Use ! rather than `. + * m68k-dis.c (print_insn_arg): Remove ` operand specifier. + +Wed Sep 24 11:29:35 1997 Ian Lance Taylor + + * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. + + * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. + + * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr + for mcf5200. + + * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. + * aclocal.m4: Rebuild with new libtool. + * configure: Rebuild. + +Fri Sep 19 11:45:49 1997 Andrew Cagney + + * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. + +Thu Sep 18 11:21:43 1997 Doug Evans + + * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. + +Tue Sep 16 15:18:20 1997 Nick Clifton + + * v850-opc.c (v850_opcodes): Further rearrangements. + +Tue Sep 16 16:12:11 1997 Ken Raeburn + + * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. + +Tue Sep 16 09:48:50 1997 Nick Clifton + + * v850-opc.c (v850_opcodes): Fields reordered to allow assembler + parser to work. + +Tue Sep 16 10:01:00 1997 Gavin Koch + + * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. + +Mon Sep 15 18:31:52 1997 Nick Clifton + + * v850-opc.c: Initialise processors field of v850_opcode structure. + +Wed Aug 27 21:42:39 1997 Ken Raeburn + + Merge changes from Martin Hunt: + + * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. + + * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. + (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix + rot2h, sra2h, and srl2h to use new SHORT_A5S format. + + * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. + + * d30v-dis.c (print_insn): First operand of d*i (delayed + branch) instructions is relative. + + * d30v-opc.c (d30v_opcode_table): Change form for repeati. + (d30v_operand_table): Add IMM6S3 type. + (d30v_format_table): Change SHORT_D2. Add LONG_Db. + + * d30v-dis.c: Fix bug with ".s" and ".l" extensions + and cmp instructions. + + * d30v-opc.c: Correct entries for repeat*, and sat*. + Make IMM5 unsigned. Create IMM6U and IMM12S3U operand + types. Correct several formats. + + * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. + + * d30v-opc.c (pre_defined_registers): Change control registers. + + * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and + SHORT_C2. Manual was incorrect. + + * d30v-dis.c (lookup_opcode): Return value now indicates + if an opcode has a short and a long form. Used for deciding + to append a ".s" or ".l". + (print_insn): Append a ".s" to an instruction if it is + the short form and ".l" if it is a long form. Do not append + anything if the instruction has only one possible size. + + * d30v-opc.c: Change mulx2h to require an even register. + New form: SHORT_A2; a SHORT_A form that needs an even + register as the first operand. + + * d30v-dis.c (print_insn_d30v): Fix problem where the last + instruction was not being disassembled if there were an odd + number of instructions. + + * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. + +Fri Sep 12 11:43:54 1997 Nick Clifton + + * v850-dis.c (disassemble): Improved display of register lists. + +Thu Sep 11 17:35:10 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix assembler args to + fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, + fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, + fandnot1s, fandnot2s. + +Tue Sep 9 10:03:49 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. + +Mon Sep 8 14:06:59 1997 Doug Evans + + * cgen-asm.c (cgen_parse_address): New argument resultp. + All callers updated. + * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. + +Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): PC relative instructions are + relative to the next instruction, not the current instruction. + +Tue Sep 2 15:41:55 1997 Nick Clifton + + * v850-dis.c (disassemble): Only signed extend values that are not + returned by extract functions. + Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. + +Tue Sep 2 15:39:40 1997 Nick Clifton + + * v850-opc.c: Update comments. Remove use of + V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. + +Tue Aug 26 09:42:28 1997 Nick Clifton + + * v850-opc.c (MOVHI): Immediate parameter is unsigned. + +Mon Aug 25 15:58:07 1997 Christopher Provenzano + + * configure: Rebuilt with latest devo autoconf for NT support. + +Fri Aug 22 10:35:15 1997 Nick Clifton + + * v850-dis.c (disassemble): Use curly brace syntax for register + lists. + + * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases + where r0 is being used as a destination register. + +Thu Aug 21 11:09:09 1997 Nick Clifton + + * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. + +Tue Aug 19 10:59:59 1997 Richard Henderson + + * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. + +Mon Aug 18 11:10:03 1997 Nick Clifton + + * v850-opc.c (v850_opcodes[]): Remove use of flag field. + * v850-opc.c (v850_opcodes[]): Add support for reversed short load + opcodes.. + +Mon Aug 18 11:08:25 1997 Nick Clifton + + * configure (cgen_files): Add support for v850e target. + * configure.in (cgen_files): Add support for v850e target. + +Mon Aug 18 11:08:25 1997 Nick Clifton + + * configure (cgen_files): Add support for v850ea target. + * configure.in (cgen_files): Add support for v850ea target. + +Fri Aug 15 05:17:48 1997 Doug Evans + + * configure.in (bfd_arc_arch): Add. + * configure: Rebuild. + * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. + * Makefile.in: Rebuild. + * arc-dis.c, arc-opc.c: New files. + * disassemble.c (ARCH_all): Define ARCH_arc. + (disassembler): Add ARC support. + +Wed Aug 13 18:52:11 1997 Nick Clifton + + * v850-dis.c (disassemble): Add support for v850EA instructions. + + * v850-opc.c (insert_i5div, extract_i5div): New Functions. + (v850_opcodes): Add v850EA instructions. + + * v850-dis.c (disassemble): Add support for v850E instructions. + + * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, + extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, + insert_spe, extract_spe): New Functions. + (v850_opcodes): Add v850E instructions. + + * v850-opc.c: Reorganised and re-layed out to improve readability + and portability. + +Tue Aug 5 23:09:31 1997 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.12.1. + +Mon Aug 4 12:02:16 1997 Ian Lance Taylor + + * aclocal.m4, configure: Rebuild with new automake patches. + +Fri Aug 1 13:02:04 1997 Ian Lance Taylor + + * configure.in: Set enable_shared before AM_PROG_LIBTOOL. + * acinclude.m4: Just include acinclude.m4 from BFD. + * aclocal.m4, configure: Rebuild. + +Thu Jul 31 21:44:42 1997 Ian Lance Taylor + + * Makefile.am: New file, based on old Makefile.in. + * acconfig.h: New file. + * acinclude.m4: New file. + * stamp-h.in: New file. + * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. + Removed shared library handling; now handled by libtool. Replace + AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, + AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with + AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h + handling in AC_OUTPUT. + * dep-in.sed: Change .o to .lo. + * Makefile.in: Now built with automake. + * aclocal.m4: Now built with aclocal. + * config.in, configure: Rebuild. + +Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Fix typo/thinko in "eret" instruction. + +Thu Jul 24 13:03:26 1997 Doug Evans + + * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. + Make array const. + * sparc-dis.c (sorted_opcodes): New static local. + (struct opcode_hash): `opcode' is pointer to const element. + (build_hash): First arg is now table of sorted pointers. + (print_insn_sparc): Sort opcodes by sorting table of pointers. + (compare_opcodes): Update. + +Tue Jul 15 12:05:23 1997 Doug Evans + + * cgen-opc.c: #include . + (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. + Handle case insensitive hashing. + (hash_keyword_value): Change type of `value' to unsigned int. + +Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c (mips_builtin_opcodes): If an insn uses single + precision FP, mark it as such. Likewise for double precision + FP. Mark ISA1 insns. Consolidate duplicate opcodes where + possible. + +Wed Jun 25 15:25:57 1997 Felix Lee + + * ppc-opc.c (extract_nsi): make unsigned expression signed before + negating it. + (UNUSED): remove one level of parens, so MSVC doesn't choke on + nesting depth when all the macros are expanded. + +Tue Jun 17 17:02:17 1997 Ian Lance Taylor + + * sparc-opc.c: The fcmp v9a instructions take an integer register + as a destination, not a floating point register. From Christian + Kuehnke . + +Mon Jun 16 14:13:18 1997 Ian Lance Taylor + + * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() + syntax. From Roman Hodek + . + + * i386-dis.c (twobyte_has_modrm): Fix pand. + +Mon Jun 16 14:08:38 1997 Michael Taylor + + * i386-dis.c (dis386_twobyte): Fix pand and pandn. + +Tue Jun 10 11:26:47 1997 H.J. Lu + + * arm-dis.c: Add prototypes for arm_decode_shift and + print_insn_arm. + +Mon Jun 2 11:39:04 1997 Gavin Koch + + * mips-opc.c: Add r3900 insns. + +Tue May 27 15:55:44 1997 Ian Lance Taylor + + * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't + print delay slot instructions on the same line. When using a PC + relative load, add a comment with the value being loaded if it can + be obtained. + +Tue May 27 11:02:08 1997 Alan Modra + + * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl + to pushS/popS for segment regs and byte constant so that + pushw/popw printed when in 16 bit data mode. + + * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to + print cbtw, cwtd in 16 bit data mode. + * i386-dis.c (putop): extra case W to support above. + + * i386-dis.c (print_insn_x86): print addr32 prefix when given + address size prefix in 16 bit address mode. + +Fri May 23 16:47:23 1997 Ian Lance Taylor + + * sh-dis.c: Reindent. Rename local variable fprintf to + fprintf_fn. + +Thu May 22 14:06:02 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. + +Tue May 20 11:26:27 1997 Gavin Koch + + * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new + field membership. + * mips16-opc.c (mip16_opcodes): same. + +Mon May 12 15:10:53 1997 Jim Wilson + + * m68k-opc.c (moveb): Change $d to %d. + +Mon May 5 14:28:41 1997 Ian Lance Taylor + + * i386-dis.c: (dis386_twobyte): Add MMX instructions. + (twobyte_has_modrm): Likewise. + (grps): Likewise. + (OP_MMX, OP_EM, OP_MS): New static functions. + + * i386-dis.c: Revert patch of April 4. The output now matches + what gcc generates. + +Fri May 2 12:48:37 1997 Doug Evans + + * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead + of $simm16. + +Thu May 1 15:34:15 1997 Doug Evans + + * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. + +Tue Apr 15 12:40:08 1997 Ian Lance Taylor + + * Makefile.in (install): Depend upon installdirs. + (installdirs): New target. + +Mon Apr 14 12:13:51 1997 Ian Lance Taylor + + From Thomas Graichen : + * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. + * configure: Rebuild. + +Sun Apr 13 17:50:41 1997 Doug Evans + + * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. + Delete string{,s}.h support. + +Thu Apr 10 14:44:56 1997 Doug Evans + + * cgen-asm.c (cgen_parse_operand_fn): New global. + (cgen_parse_{{,un}signed_integer,address}): Update call to + cgen_parse_operand_fn. + (cgen_init_parse_operand): New function. + * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed + from cgen_asm_init_parse. + (m32r_cgen_assemble_insn): New operand `errmsg'. + Delete call to as_bad, return error message to caller. + (m32r_cgen_asm_hash_keywords): #if 0 out. + +Wed Apr 9 12:05:25 1997 Andreas Schwab + + * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, + not data register. + [case 'J']: Fix typo in register name. + +Mon Apr 7 16:48:22 1997 Ian Lance Taylor + + * configure.in: Substitute SHLIB_LIBS. + * configure: Rebuild. + * Makefile.in (SHLIB_LIBS): New variable. + ($(SHLIB)): Use $(SHLIB_LIBS). + +Mon Apr 7 11:45:44 1997 Doug Evans + + * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. + + * cgen-opc.c (hash_keyword_name): Improve algorithm. + + * disassemble.c (disassembler): Handle m32r. + +Fri Apr 4 12:29:38 1997 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. + * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. + * Makefile.in (CFILES): Add them. + (ALL_MACHINES): Add them. + (dependencies): Regenerate. + * configure.in (cgen_files): New variable. + (bfd_m32r_arch): Add entry. + * configure: Regenerate. + +Fri Apr 4 14:04:16 1997 Ian Lance Taylor + + * configure.in: Correct file names for bfd_mn10[23]00_arch. + * configure: Rebuild. + + * Makefile.in: Rebuild dependencies. + + * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". + + * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and + fdivp. + +Thu Apr 3 13:22:45 1997 Ian Lance Taylor + + * Branched binutils 2.8. + +Wed Apr 2 12:23:53 1997 Ian Lance Taylor + + * m10200-dis.c: Rename from mn10200-dis.c. + * m10200-opc.c: Rename from mn10200-opc.c. + * m10300-dis.c: Rename from mn10300-dis.c + * m10300-opc.c: Rename from mn10300-opc.c. + * Makefile.in: Update accordingly. + + * mips16-opc.c: Add mul and dmul macros. + +Tue Apr 1 16:27:45 1997 Klaus Kaempf + + * makefile.vms: Update CFLAGS, add clean target. + +Fri Mar 28 12:10:09 1997 Ian Lance Taylor + + * mips-opc.c: Add "wait". From Ralf Baechle + . + + * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. + * configure, config.in: Rebuild. + * sysdep.h: Include if it exists. + * sparc-dis.c: Include and "sysdep.h". Don't include + . + * Makefile.in: Rebuild dependencies. + +Thu Mar 27 14:24:43 1997 Ian Lance Taylor + + * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From + Andrew Bray . + + * mips-opc.c: Add cast when setting mips_opcodes. + +Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Fix sign extension problem. + * v850-opc.c (extract_d*): Fix sign extension problems to make + disassembly calculate branch offsets correctly. + +Mon Mar 24 13:22:13 1997 Ian Lance Taylor + + * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. + + * mips-opc.c: Add dctr and dctw. + +Sun Mar 23 18:08:10 1997 Martin M. Hunt + + * d30v-dis.c (print_insn): Change the way signed constants + are displayed. + +Fri Mar 21 14:37:52 1997 Ian Lance Taylor + + * Makefile.in (BFD_H): New variable. + (HFILES): New variable. + (CFILES): Add all C files. + (.dep, .dep1, dep.sed, dep, dep-in): New targets. + Delete old dependencies, and build new ones. + * dep-in.sed: New file. + +Thu Mar 20 19:03:30 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. + +Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Change "trap" to "syscall". + * mn10300-opc.c: Add new "syscall" instruction. + +Mon Mar 17 08:48:03 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and + mulul insns on the coldfire. + +Sat Mar 15 17:13:05 1997 Ian Lance Taylor + + * arm-dis.c (print_insn_arm): Don't print instruction bytes. + (print_insn_big_arm): Set bytes_per_chunk and display_endian. + (print_insn_little_arm): Likewise. + +Fri Mar 14 15:08:59 1997 Ian Lance Taylor + + Based on patches from H.J. Lu : + * i386-dis.c (fetch_data): Add prototype. + * m68k-dis.c (fetch_data): Add prototype. + (dummy_print_address): Add prototype. Make static. + * ppc-opc.c (valid_bo): Add prototype. + * sparc-dis.c (build_hash_table): Add prototype. + (is_delayed_branch, compute_arch_mask): Add prototypes. + (print_insn_sparc): Make several local variables const. + (compare_opcodes): Change arguments to const PTR. Add prototype. + * sparc-opc.c (arg): Change name field to be const. + (lookup_name, lookup_value): Add prototypes. Change table and + name parameters to be const. + (sparc_encode_asi): Change name parameter to be const. + (sparc_encode_membar, sparc_encode_prefetch): Likewise. + (sparc_encode_sparclet_cpreg): Likewise. + (sparc_decode_asi): Change return type to be const. + (sparc_decode_membar, sparc_decode_prefetch): Likewise. + (sparc_decode_sparclet_cpreg): Likewise. + +Fri Mar 7 10:51:49 1997 Ian Lance Taylor + + * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since + Solaris doesn't like the combined options, and the -f is + unnecessary. + (stamp-tshlink, install): Likewise. + +Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these + as relaxable. + +Tue Mar 4 06:10:36 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. + +Mon Mar 3 07:45:20 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on + the mc68000. + +Thu Feb 27 14:04:32 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. + +Thu Feb 27 11:36:41 1997 Michael Meissner + + * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. + +Wed Feb 26 15:34:48 1997 Michael Meissner + + * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. + +Wed Feb 26 13:38:30 1997 Andreas Schwab + + * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use + floatformat_to_double to make portable. + (print_insn_arg): Use NEXTEXTEND macro when extracting extended + precision float. + +Mon Feb 24 19:26:12 1997 Dawn Perchik + + * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, + and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. + +Mon Feb 24 15:19:01 1997 Martin M. Hunt + + * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to + d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. + +Mon Feb 24 14:33:26 1997 Fred Fish + + * tic80-opc.c (LSI_SCALED): Renamed from this ... + (OFF_SL_BR_SCALED): ... to this, and added the flag + TIC80_OPERAND_BASEREL to the flags word. + (tic80_opcodes): Replace all occurances of LSI_SCALED with + OFF_SL_BR_SCALED. + +Sat Feb 22 21:25:00 1997 Dawn Perchik + + * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. + Change mips_opcodes from const array to a pointer, + and change bfd_mips_num_opcodes from const int to int, + so that we can increase the size of the mips opcodes table + dynamically. + +Sat Feb 22 21:03:47 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Revert change to + store BITNUM values in the table in one's complement form + to match behavior when assembler is given a raw numeric + value for a BITNUM operand. + * tic80-dis.c (print_operand_bitnum): Ditto. + +Fri Feb 21 16:31:18 1997 Martin M. Hunt + + * d30v-opc.c: Removed references to FLAG_X. + +Wed Feb 19 14:51:20 1997 Ian Lance Taylor + + * Makefile.in: Add dependencies on ../bfd/bfd.h as required. + +Tue Feb 18 17:43:43 1997 Martin M. Hunt + + * Makefile.in: Added d30v object files. + * configure: (bfd_d30v_arch) Rebuilt. + * configure.in: (bfd_d30v_arch) Added new case. + * d30v-dis.c: New file. + * d30v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d30v. + +Tue Feb 18 16:32:08 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Add symbolic + representations for the floating point BITNUM values. + +Fri Feb 14 12:14:05 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values + in the table in one's complement form, as they appear in the + actual instruction. + (tic80_symbol_to_value): Use macros to access predefined + symbol fields. + (tic80_value_to_symbol): Ditto. + (tic80_next_predefined_symbol): New function. + * tic80-dis.c (print_operand_bitnum): Remove code that did + one's complement for BITNUM values. + +Thu Feb 13 21:56:51 1997 Klaus Kaempf + + * makefile.vms: Remove 8 bit characters. Update to latest + gcc release. + +Thu Feb 13 20:41:22 1997 Philippe De Muyter + + * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. + +Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (IMM16_PCREL): This is a signed operand. + (IMM24_PCREL): Likewise. + +Thu Feb 13 13:28:43 1997 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base + address for an extended PC relative instruction that is not a + branch. + +Wed Feb 12 12:27:40 1997 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and + bytes_per_line. + +Tue Feb 11 16:36:31 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. + (tic80_opcodes): Sort entries so that long immediate forms + come after short immediate forms, making it easier for + assembler to select the right one for a given operand. + +Tue Feb 11 15:26:47 1997 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and + display_endian. + (print_insn_mips16): Likewise. + +Mon Feb 10 10:12:41 1997 Fred Fish + + * tic80-opc.c (tic80_symbol_to_value): Changed to accept + a symbol class that restricts translation to just that + class (general register, condition code, etc). + +Thu Feb 6 17:34:09 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, + and REG_DEST_E for register operands that have to be + an even numbered register. Add REG_FPA for operands that + are one of the floating point accumulator registers. + Add TIC80_OPERAND_MASK to flags for ENDMASK operand. + (tic80_opcodes): Change entries that need even numbered + register operands to use the new operand table entries. + Add "or" entries that are identical to "or.tt" entries. + +Wed Feb 5 11:12:44 1997 Ian Lance Taylor + + * mips16-opc.c: Add new cases of exit instruction for + disassembler. + * mips-dis.c (print_mips16_insn_arg): Display floating point + registers in operands of exit instruction. Print `$' before + register names in operands of entry and exit instructions. + +Thu Jan 30 14:09:03 1997 Fred Fish + + * tic80-opc.c (tic80_predefined_symbols): Table of name/value + pairs for all predefined symbols recognized by the assembler. + Also used by the disassembling routines. + (tic80_symbol_to_value): New function. + (tic80_value_to_symbol): New function. + * tic80-dis.c (print_operand_control_register, + print_operand_condition_code, print_operand_bitnum): + Remove private tables and use tic80_value_to_symbol function. + +Thu Jan 30 11:30:45 1997 Martin M. Hunt + + * d10v-dis.c (print_operand): Change address printing + to correctly handle PC wrapping. Fixes PR11490. + +Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative + branches relaxable. + +Tue Jan 28 15:57:34 1997 Ian Lance Taylor + + * mips-dis.c (print_insn_mips16): Set insn_info information. + (print_mips16_insn_arg): Likewise. + + * mips-dis.c (print_insn_mips16): Better handling of an extend + opcode followed by an instruction which can not be extended. + +Fri Jan 24 12:08:21 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Changed operand specifier for the + coldfire moveb instruction to not allow an address register as + destination. Although the documentation does not indicate that + this is invalid, experiments uncovered unexpected behavior. + Added a comment explaining the situation. Thanks to Andreas + Schwab for pointing this out to me. + +Wed Jan 22 20:13:51 1997 Fred Fish + + * tic80-opc.c (tic80_opcodes): Expand comment to note that the + entries are presorted so that entries with the same mnemonic are + adjacent to each other in the table. Sort the entries for each + instruction so that this is true. + +Mon Jan 20 12:48:57 1997 Andreas Schwab + + * m68k-dis.c: Include . + (print_insn_m68k): Sort the opcode table on the most significant + nibble of the opcode. + +Sat Jan 18 15:15:05 1997 Fred Fish + + * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", + "vsub", "vst", "xnor", and "xor" instructions. + (V_a1): Renamed from V_a, msb of accumulator reg number. + (V_a0): Add macro, lsb of accumulator reg number. + +Fri Jan 17 18:24:31 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Broke excessively long + function up into several smaller ones and arranged for + the instruction printing function to be callable recursively + to print vector instructions that have both a load and a + math instruction packed into a single opcode. + * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode + to explain why it comes after the other vector opcodes. + +Fri Jan 17 16:19:15 1997 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire + move insns to handle immediate operands. + +Thu Jan 17 16:19:00 1997 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". + fix operand mask in the "moveml" entries for the coldfire. + +Thu Jan 16 20:54:40 1997 Fred Fish + + * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): + New macros for building vector instruction opcodes. + (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and + FMT_LI, which were unused. The field is now a flags field. + Remove some opcodes that are possible, but illegal, such + as long immediate instructions with doubles for immediate + values. Add "vadd" and "vld" instructions. + +Wed Jan 15 18:59:51 1997 Fred Fish + + * tic80-opc.c (tic80_operands): Reorder some table entries to make + the order more logical. Move the shift alias instructions ("rotl", + "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be + interspersed with the regular sr.x and sl.x instructions. Add + and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", + "sub", "subu", "swcr", and "trap". + +Tue Jan 14 19:42:50 1997 Fred Fish + + * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. + (OFF_SL_PC): Renamed from OFF_SL. + (OFF_SS_BR): New operand type for base relative operand. + (OFF_SL_BR): New operand type for base relative operand. + (REG_BASE): New operand type for base register operand. + (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", + "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", + "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" + instructions. + * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width + 10 char field, padded with spaces on rhs, rather than a string + followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather + than old TIC80_OPERAND_RELATIVE. Add support for new + TIC80_OPERAND_BASEREL flag bit. + +Mon Jan 13 15:58:56 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print floating point operands + as floats. + * tic80-opc.c (SPFI): Add single precision floating point + immediate operand type. + (ROTATE): Add rotate operand type for shifts. + (ENDMASK): Add for shifts. + (n): Macro for the 'n' bit. + (i): Macro for the 'i' bit. + (PD): Macro for the 'PD' field. + (P2): Macro for the 'P2' field. + (P1): Macro for the 'P1' field. + (tic80_opcodes): Add entries for "exts", "extu", "fadd", + "fcmp", and "fdiv". + +Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c (disassemble): Mask off unwanted bits after + adding in current address for pc-relative operands. + +Mon Jan 6 10:56:25 1997 Fred Fish + + * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. + (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. + * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names + changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. + (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, + REG_BASE_M_SI, REG_BASE_M_LI respectively. + (REG_SCALED, LSI_SCALED): New operand types. + (E): New macro for 'E' bit at bit 27. + (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap + opcodes, including the various size flavors (b,h,w,d) for + the direct load and store instructions. + +Sun Jan 5 12:18:14 1997 Fred Fish + + * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit + in an instruction. + * tic80-dis.c (print_insn_tic80): Change comma and paren handling. + Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. + * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. + (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. + (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode + masks with "MASK_* & ~M_*" to get the M bit reset. + (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. + +Sat Jan 4 19:05:05 1997 Fred Fish + + * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE + correctly. Add support for printing TIC80_OPERAND_BITNUM and + TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic + form. + * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, + CC, SICR, and LICR table entries. + (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", + "bcnd", and "brcr" opcodes. + +Fri Jan 3 18:32:11 1997 Fred Fish + + * ppc-opc.c (powerpc_operands): Make comment match the + actual fields (no shift field). + * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". + * tic80-dis.c (print_insn_tic80): Replace abort stub with a + partial implementation, work in progress. + * tic80-opc.c (tic80_operands): Begin construction operands table. + (tic80_opcodes): Continue populating opcodes table and start + filling in the operand indices. + (tic80_num_opcodes): Add this. + +Fri Jan 3 12:13:52 1997 Ian Lance Taylor + + * m68k-opc.c: Add #B case for moveq. + +Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Make sure all variables are initialized + before they are used. + +Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Put curly-braces around operands + for "breakpoint" instruction. + +Tue Dec 31 15:38:13 1996 Ian Lance Taylor + + * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. + (dep): Use ALL_CFLAGS rather than CFLAGS. + +Tue Dec 31 15:09:16 1996 Michael Meissner + + * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY + flag. + +Mon Dec 30 17:02:11 1996 Fred Fish + + * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. + (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. + +Mon Dec 30 11:38:01 1996 Ian Lance Taylor + + * mips16-opc.c: Add "abs". + +Sun Dec 29 10:58:22 1996 Fred Fish + + * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. + * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. + (disassembler): Add bfd_arch_tic80 support to set disassemble + to print_insn_tic80. + * tic80-dis.c (print_insn_tic80): Add stub. + +Fri Dec 27 22:30:57 1996 Fred Fish + + * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. + * configure: Regenerate with autoconf. + * tic80-dis.c: Add file. + * tic80-opc.c: Add file. + +Fri Dec 20 14:30:19 1996 Martin M. Hunt + + * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. + +Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_operands): Add SIMM16N. + (mn10200_opcodes): Use it for some logicals and btst insns. + Add "break" and "trap" instructions. + + * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. + + * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". + +Sat Dec 14 22:36:20 1996 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): The base address of a PC + relative load or add now depends upon whether the instruction is + in a delay slot. + +Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-dis.c: Finish writing disassembler. + * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". + Fix mask for "jmp (an)". + + * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently + handle endianness issues for mn10300. + + * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". + +Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 + instruction. Fix opcode field for "movb (imm24),dn". + + * mn10200-opc.c (mn10200_operands): Fix insertion position + for DI operand. + +Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c: Create mn10200 opcode table. + * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, + but moving along nicely. + +Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add mips16-opc.o. + +Fri Dec 6 16:47:40 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Revert change to use < and > + specifiers for fmovem* instructions. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Remove '$' register prefixing. + +Fri Dec 6 17:34:39 1996 Ian Lance Taylor + + * mips16-opc.c: Change opcode for entry/exit to avoid conflicting + with dsrl. + +Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c: Add some comments explaining the various + operands and such. + + * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. + +Thu Dec 5 12:09:48 1996 J.T. Conklin + + * m68k-dis.c (print_insn_arg): Handle new < and > operand + specifiers. + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in fmovm* instructions. + +Wed Dec 4 14:52:18 1996 Ian Lance Taylor + + * ppc-opc.c (insert_li): Give an error if the offset has the two + least significant bits set. + +Wed Nov 27 13:09:01 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_mips16): Separate the instruction from + the arguments with a tab, not a space. + +Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disasemble): Finish conversion to '$' as + register prefix. + + * mn10300-opc.c (mn10300_opcodes): Fix mask field for + mov am,(imm32,sp). + +Tue Nov 26 10:53:21 1996 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.12. + + Add support for mips16 (16 bit MIPS implementation): + * mips16-opc.c: New file. + * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". + (mips16_reg_names): New static array. + (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or + after seeing a 16 bit symbol. + (print_insn_little_mips): Likewise. + (print_insn_mips16): New static function. + (print_mips16_insn_arg): New static function. + * mips-opc.c: Add jalx instruction. + * Makefile.in (mips16-opc.o): New target. + * configure.in: Use mips16-opc.o for bfd_mips_arch. + * configure: Rebuild. + +Mon Nov 25 16:15:17 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Simplify table by using < and > + operand specifiers in *save, *restore and movem* instructions. + + * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for + the coldfire. + + * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use + register operands for immediate arithmetic, not, neg, negx, and + set according to condition instructions. + + * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage + specifier of the effective-address operand in immediate forms of + arithmetic instructions. The specifier for the immediate operand + notes how and where the constant will be stored. + +Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" + opcode. + + * mn10300-dis.c (disassemble): Use '$' instead of '%' for + register prefix. + + * mn10300-dis.c (disassemble): Prefix registers with '%'. + +Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c (disassemble): Handle register lists. + + * mn10300-opc.c: Fix handling of register list operand for + "call", "ret", and "rets" instructions. + + * mn10300-dis.c (disassemble): Print PC-relative and memory + addresses symbolically if possible. + * mn10300-opc.c: Distinguish between absolute memory addresses, + pc-relative offsets & random immediates. + + * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte + in 7 byte insns. + (disassemble): Handle SPLIT and EXTENDED operands. + +Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-dis.c: Rough cut at printing some operands. + + * mn10300-dis.c: Start working on disassembler support. + * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. + + * mn10300-opc.c (mn10300_operands): Add "REGS" for a register + list. + (mn10300_opcodes): Use REGS for register list in "movm" instructions. + +Mon Nov 18 15:20:35 1996 Michael Meissner + + * d10v-opc.c (d10v_opcodes): Add3 sets the carry. + +Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Demand parens around + register argument is calls and jmp instructions. + +Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and + getx operand. Fix opcode for mulqu imm,dn. + +Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Hijack "bits" field + in MN10300_OPERAND_SPLIT operands for how many bits + appear in the basic insn word. Add IMM32_HIGH24, + IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. + (mn10300_opcodes): Use new operands as needed. + + * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 + for bset, bclr, btst instructions. + (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. + + * mn10300-opc.c (mn10300_operands): Remove many redundant + operands. Update opcode table as appropriate. + (IMM32): Add MN10300_OPERAND_SPLIT flag. + (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. + +Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 + operands (for indexed load/stores). Fix bitpos for DI + operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the + few instructions that insert immediates/displacements in the + middle of the instruction. Add IMM8E for 8 bit immediate in + the extended part of an instruction. + (mn10300_operands): Use new opcodes as appropriate. + +Tue Nov 5 10:30:51 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Declare the trap instruction + sequential so the assembler never parallelizes it with + other instructions. + +Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for + a data/address register that appears in register field 0 + and register field 1. + (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN + +Fri Nov 1 10:29:11 1996 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for + standard disassembly. + + * alpha-opc.c (alpha_operands): Rearrange flags slot. + (alpha_opcodes): Add new BWX, CIX, and MAX instructions. + Recategorize PALcode instructions. + +Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add relaxing "jbr". + +Tue Oct 29 16:30:28 1996 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Don't print a trailing tab if + there are no operand types. + +Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (D9_RELAX): Renamed from D9, all references + changed. + (v850_operands): Make sure D22 immediately follows D9_RELAX. + +Fri Oct 25 12:12:53 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. + +Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w + and sst.w instructions. + + * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for + "bCC"instructions). + +Thu Oct 24 17:21:20 1996 Ian Lance Taylor + + * mips-dis.c (_print_insn_mips): Use a tab between the instruction + and the arguments. + +Tue Oct 22 23:32:56 1996 Ian Lance Taylor + + * ppc-opc.c (PPCPWR2): Define. + (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating + it. + +Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode + field for movhu instruction. + + * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, + cast value to "long" not "signed long" to keep hpux10 + compiler quiet. + +Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field + for mov (abs16),DN. + + * mn10300-opc.c (FMT*): Remove definitions. + + * mn10300-opc.c (mn10300_opcodes): Fix destination register + for shift-by-register opcodes. + + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM + into [AD][MN][01] for encoding the position of the register + in the opcode. + +Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, + "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". + +Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. + Fix various typos. Add "PAREN" operand. + (MEM, MEM2): Define. + (mn10300_opcodes): Surround all memory addresses with "PAREN" + operands. Fix several typos. + + * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's + changes. + +Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (FMT_XX): Renumber starting at one. + (mn10300_operands): Rough cut. Enough to parse "mov" instructions + at this time. + (mn10300_opcodes): Break opcode format out into its own field. + Update many operand fields to deal with signed vs unsigned + issues. Fix one or two typos in the "mov" instruction + opcode, mask and/or operand fields. + +Mon Oct 7 11:39:49 1996 Andreas Schwab + + * m68k-opc.c (plusha): Prefer encoding for m68040up, in case + m68851 wasn't reset. + +Thu Oct 3 17:17:02 1996 Ian Lance Taylor + + * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for + all opcodes. Very rough cut at operands for all opcodes. + + * mn10300-opc.c (mn10300_opcodes): Start fleshing out the + opcode table. + +Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200-opc.c, mn10300-opc.c: New files. + * mn10200-dis.c, mn10300-dis.c: New files. + * mn10x00-opc.c, mn10x00-dis.c: Deleted. + * disassemble.c: Break mn10x00 support into 10200 and 10300 + support. + * configure.in: Likewise. + * configure: Rebuilt. + +Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. + +Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) + + * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita + MN10x00 processors. + * disassemble.c (ARCH_mn10x00): Define. + (disassembler): Handle bfd_arch_mn10x00. + * configure.in: Recognize bfd_mn10x00_arch. + * configure: Rebuilt. + +Tue Oct 1 10:49:11 1996 Ian Lance Taylor + + * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses + accordingly. Don't declare functions using op_rtn. + +Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) + + * v850-dis.c (disassemble): Add memaddr argument. Re-arrange + params to be more standard. + * (disassemble): Print absolute addresses and symbolic names for + branch and jump targets. + * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 + bit operands. + * (v850_opcodes): Add breakpoint insn. + +Mon Sep 23 12:32:26 1996 Ian Lance Taylor + + * m68k-opc.c: Move the fmovemx data register cases before the + other cases, so that they get recognized before the data register + does gets treated as a degenerate register list. + +Tue Sep 17 12:06:51 1996 Ian Lance Taylor + + * mips-opc.c: Add a case for "div" and "divu" with two registers + and a destination of $0. + +Tue Sep 10 16:12:39 1996 Fred Fish + + * mips-dis.c (print_insn_arg): Add prototype. + (_print_insn_mips): Ditto. + +Mon Sep 9 14:26:26 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_arg): Print condition code registers as + $fccN. + +Tue Sep 3 12:09:46 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. + +Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Make static. Provide prototype. + +Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (insert_d9, insert_d22): Fix boundary case + in range checks. + +Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-dis.c (disassemble): Handle insertion of ',', '[' and + ']' characters into the output stream. + * v850-opc.c (v850_opcodes: Remove size field from all opcodes. + Add "memop" field to all opcodes (for the disassembler). + Reorder opcodes so that "nop" comes before "mov" and "jr" + comes before "jarl". + + * v850-dis.c (print_insn_v850): Fix typo in last change. + + * v850-dis.c (print_insn_v850): Properly handle disassembling + a two byte insn at the end of a memory region when the memory + region's size is only two byte aligned. + + * v850-dis.c (v850_cc_names): Fix stupid thinkos. + + * v850-dis.c (v850_reg_names): Define. + (v850_sreg_names, v850_cc_names): Likewise. + (disassemble): Very rough cut at printing operands (unformatted). + + * v850-opc.c (BOP_MASK): Fix. + (v850_opcodes): Fix mask for jarl and jr. + + * v850-dis.c: New file. Skeleton for disassembler support. + * Makefile.in Remove v850 references, they're not needed here. + * configure.in: Add v850-dis.o when building v850 toolchains. + * configure: Rebuilt. + * disassemble.c (disassembler): Call v850 disassembler. + + * v850-opc.c (insert_d8_7, extract_d8_7): New functions. + (insert_d8_6, extract_d8_6): New functions. + (v850_operands): Rename D7S to D7; operand for D7 is unsigned. + Rename D8 to D8_7, use {insert,extract}_d8_7 routines. + Add D8_6. + (IF4A, IF4B): Use "D7" instead of "D7S". + (IF4C, IF4D): Use "D8_7" instead of "D8". + (IF4E, IF4F): New. Use "D8_6". + (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for + sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. + + * v850-opc.c (insert_d16_15, extract_d16_15): New functions. + (v850_operands): Change D16 to D16_15, use special insert/extract + routines. New new D16 that uses the generic insert/extract code. + (IF7A, IF7B): Use D16_15. + (IF7C, IF7D): New. Use D16. + (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. + + * v850-opc.c (insert_d9, insert_d22): Slightly improve error + message. Issue an error if the branch offset is odd. + + * v850-opc.c: Add notes about needing special insert/extract + for all the load/store insns, except "ld.b" and "st.b". + + * v850-opc.c (insert_d22, extract_d22): New functions. + (v850_operands): Use insert_d22 and extract_d22 for + D22 operands. + (insert_d9): Fix range check. + +Fri Aug 30 18:01:02 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag + and set bits field to D9 and D22 operands. + +Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Define SR2 operand. + (v850_opcodes): "ldsr" uses R1,SR2. + + * v850-opc.c (v850_opcodes): Fix opcode specs for + sld.w, sst.b, sst.h, sst.w, and nop. + +Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Add null opcode to mark the + end of the opcode table. + +Mon Aug 26 13:35:53 1996 Martin M. Hunt + + * d10v-opc.c (pre_defined_registers): Added register pairs, + "r0-r1", "r2-r3", etc. + +Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Make I16 be a signed operand. + Create I16U for an unsigned 16bit mmediate operand. + (v850_opcodes): Use I16U for "ori", "andi" and "xori". + + * v850-opc.c (v850_operands): Define EP operand. + (IF4A, IF4B, IF4C, IF4D): Use EP. + + * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" + with immediate operand, "movhi". Tweak "ldsr". + + * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] + correct. Get sld.[bhw] and sst.[bhw] closer. + + * v850-opc.c (v850_operands): "not" is a two byte insn + + * v850-opc.c (v850_opcodes): Correct bit pattern for setf. + + * v850-opc.c (v850_operands): D16 inserts at offset 16! + + * v850-opc.c (two): Get order of words correct. + + * v850-opc.c (v850_operands): I16 inserts at offset 16! + + * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system + register source and destination operands. + (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". + + * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix + same thinko in "trap" opcode. + + * v850-opc.c (v850_opcodes): Add initializer for size field + on all opcodes. + + * v850-opc.c (v850_operands): D6 -> DS7. References changed. + Add D8 for 8-bit unsigned field in short load/store insns. + (IF4A, IF4D): These both need two registers. + (IF4C, IF4D): Define. Use 8-bit unsigned field. + (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use + IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand + for "ldsr" and "stsr". + * v850-opc.c (v850_operands): 3-bit immediate for bit insns + is unsigned. + + * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and + short store word (sst.w). + +Thu Aug 22 16:57:27 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Added insert and extract fields, + pointers to functions that handle unusual operand encodings. + +Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_opcodes): Enable "trap". + + * v850-opc.c (v850_opcodes): Fix order of displacement + and register for "set1", "clr1", "not1", and "tst1". + +Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) + + * v850-opc.c (v850_operands): Add "B3" support. + (v850_opcodes): Fix and enable "set1", "clr1", "not1" + and "tst1". + + * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. + + * v850-opc.c: Close unterminated comment. + +Wed Aug 21 17:31:26 1996 J.T. Conklin + + * v850-opc.c (v850_operands): Add flags field. + (v850_opcodes): add move opcodes. + +Tue Aug 20 14:41:03 1996 J.T. Conklin + + * Makefile.in (ALL_MACHINES): Add v850-opc.o. + * configure: (bfd_v850v_arch) Add new case. + * configure.in: (bfd_v850_arch) Add new case. + * v850-opc.c: New file. + +Mon Aug 19 15:21:38 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. + +Thu Aug 15 13:14:43 1996 Martin M. Hunt + + * d10v-opc.c: Add additional information to the opcode + table to help determinine which instructions can be done + in parallel. + +Thu Aug 15 13:11:13 1996 Stan Shebs + + * mpw-make.sed: Update editing of include pathnames to be + more general. + +Thu Aug 15 16:28:41 1996 James G. Smith + + * arm-opc.h: Added "bx" instruction definition. + +Wed Aug 14 17:00:04 1996 Richard Henderson + + * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. + +Mon Aug 12 14:30:37 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. + +Fri Aug 9 13:21:59 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. + +Thu Aug 8 12:43:52 1996 Klaus Kaempf + + * makefile.vms: Update for alpha-opc changes. + +Wed Aug 7 11:55:10 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_i386): Actually return the correct value. + (ONE, OP_ONE): #ifdef out; not used. + +Fri Aug 2 17:47:03 1996 Martin M. Hunt + + * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. + Changed subi operand type to treat 0 as 16. + +Wed Jul 31 16:21:41 1996 Ian Lance Taylor + + * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose + . + +Wed Jul 31 14:39:27 1996 James G. Smith + + * arm-opc.h: (arm_opcodes): Added halfword and sign-extension + memory transfer instructions. Add new format string entries %h and %s. + * arm-dis.c: (print_insn_arm): Provide decoding of the new + formats %h and %s. + +Fri Jul 26 11:45:04 1996 Martin M. Hunt + + * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. + (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. + +Fri Jul 26 14:01:43 1996 Ian Lance Taylor + + * alpha-dis.c (print_insn_alpha_osf): Remove. + (print_insn_alpha_vms): Remove. + (print_insn_alpha): Make globally visible. Chose the register + names based on info->flavour. + * disassemble.c: Always return print_insn_alpha for the alpha. + +Thu Jul 25 15:24:17 1996 Martin M. Hunt + + * d10v-dis.c (dis_long): Handle unknown opcodes. + +Thu Jul 25 12:08:09 1996 Martin M. Hunt + + * d10v-opc.c: Changes to support signed and unsigned numbers. + All instructions with the same name that have long and short forms + now end in ".l" or ".s". Divs added. + * d10v-dis.c: Changes to support signed and unsigned numbers. + +Tue Jul 23 11:02:53 1996 Martin M. Hunt + + * d10v-dis.c: Change all functions to use info->print_address_func. + +Mon Jul 22 15:38:53 1996 Andreas Schwab + + * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire + move ccr/sr insns more strict so that the disassembler only + selects them when the addressing mode is data register. + +Mon Jul 22 11:25:24 1996 Martin M. Hunt + * d10v-opc.c (pre_defined_registers): Declare. + * d10v-dis.c (print_operand): Now uses pre_defined_registers + to pick a better name for the registers. + +Mon Jul 22 13:47:23 1996 Ian Lance Taylor + + * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix + operands for fexpand and fpmerge. From Christian Kuehnke + . + +Mon Jul 22 13:17:06 1996 Richard Henderson + + * alpha-dis.c (print_insn_alpha): No longer the user-visible + print routine. Take new regnames and cpumask arguments. + Kill the environment variable nonsense. + (print_insn_alpha_osf): New function. Do OSF/1 style regnames. + (print_insn_alpha_vms): New function. Do VMS style regnames. + * disassemble.c (disassembler): Test bfd flavour to pick + between OSF and VMS routines. Default to OSF. + +Thu Jul 18 17:19:34 1996 Ian Lance Taylor + + * configure.in: Call AC_SUBST (INSTALL_SHLIB). + * configure: Rebuild. + * Makefile.in (install): Use @INSTALL_SHLIB@. + +Wed Jul 17 14:39:05 1996 Martin M. Hunt + + * configure: (bfd_d10v_arch) Add new case. + * configure.in: (bfd_d10v_arch) Add new case. + * d10v-dis.c: New file. + * d10v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d10v. + +Wed Jul 17 10:12:05 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating + to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. + +Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to + distinguish between variants of the instruction set. + * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to + distinguish between variants of the instruction set. + +Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) + + * i386-dis.c (print_insn_i8086): New routine to disassemble using + the 8086 instruction set. + * i386-dis.c: General cleanups. Make most things static. Add + prototypes. Get rid of static variables aflags and dflags. Pass + them as args (to almost everything). + +Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. + + * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". + + * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two + if the next arg is marked with SRC_IN_DST. Gross. + + * h8300-dis.c (bfd_h8_disassemble): Print "exr" when + we're looking for and find EXR. + + * h8300-dis.c (bfd_h8_disassemble): We don't have a match + if we're looking for KBIT and we don't find it. + + * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits + for L_3 and L_2. + + * h8300-dis.c (bfd_h8_disassemble): Don't set plen for + 3bit immediate operands. + +Tue Jul 9 10:55:20 1996 Ian Lance Taylor + + * Released binutils 2.7. + + * alpha-opc.c: Add new case of "mov". From Klaus Kaempf + . + +Thu Jul 4 11:42:51 1996 Ian Lance Taylor + + * alpha-opc.c: Correct second case of "mov" to use OPRL. + +Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) + + * sparc-dis.c (print_insn_sparclite): New routine to print + sparclite instructions. + +Wed Jul 3 14:21:18 1996 J.T. Conklin + + * m68k-opc.c (m68k_opcodes): Add coldfire support. + +Fri Jun 28 15:53:51 1996 Doug Evans + + * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, + #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L + to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. + +Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): + Use autoconf-set values. + (docdir, oldincludedir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + +Fri Jun 21 13:53:36 1996 Richard Henderson + + * alpha-opc.c: New file. + * alpha-opc.h: Remove. + * alpha-dis.c: Complete rewrite to use new opcode table. + * configure.in: For bfd_alpha_arch, use alpha-opc.o. + * configure: Rebuild with autoconf 2.10. + * Makefile.in (ALL_MACHINES): Add alpha-opc.o. + (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not + alpha-opc.h. + (alpha-opc.o): New target. + +Wed Jun 19 15:55:12 1996 Ian Lance Taylor + + * sparc-dis.c (print_insn_sparc): Remove unused local variable i. + Set imm_added_to_rs1 even if the source and destination register + are not the same. + + * sparc-opc.c: Add some two operand forms of the wr instruction. + +Tue Jun 18 15:58:27 1996 Jeffrey A. Law + + * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument + to just "mode". + + * disassemble.c (disassembler): Handle H8/S. + * h8300-dis.c (print_insn_h8300s): New function for H8/S. + +Tue Jun 18 18:06:50 1996 Ian Lance Taylor + + * sparc-opc.c: Add beq/teq as aliases for be/te. + + * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko + . + +Tue Jun 18 15:08:54 1996 Klaus Kaempf + + * makefile.vms: New file. + + * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. + +Mon Jun 10 18:50:38 1996 Ian Lance Taylor + + * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, + regardless of plen. + +Tue Jun 4 09:15:53 1996 Doug Evans + + * i386-dis.c (OP_OFF): Call append_prefix. + +Thu May 23 15:18:23 1996 Michael Meissner + + * ppc-opc.c (instruction encoding macros): Add explicit casts to + unsigned long to silence a warning from the Solaris PowerPC + compiler. + +Thu Apr 25 19:33:32 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. + +Mon Apr 22 17:12:35 1996 Doug Evans + + * sparc-dis.c (X_IMM,X_SIMM): New macros. + (X_IMM13): Delete. + (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. + * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, + Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, + cpush, cpusha, cpull sparclet insns. + +Wed Apr 17 14:20:22 1996 Doug Evans + + * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. + +Thu Apr 11 17:30:02 1996 Ian Lance Taylor + + * sparc-opc.c: Set F_FBR on floating point branch instructions. + Set F_FLOAT on other floating point instructions. + +Mon Apr 8 17:02:48 1996 Michael Meissner + + * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and + registers. + (powerpc_opcodes): Add 860/821 specific SPRs. + +Mon Apr 8 14:00:44 1996 Ian Lance Taylor + + * configure.in: Permit --enable-shared to specify a list of + directories. Set and substitute BFD_PICLIST. + * configure: Rebuild. + * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all + uses. Set to @BFD_PICLIST@. + +Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, + not "abs", which may be needed for the absolute in something + like btst #0,@10:8. Print L_3 immediates separately from other + immediates. Change ABSMOV reference to ABS8MEM. + +Wed Apr 3 10:40:45 1996 Doug Evans + + * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. + (current_arch_mask): New static global. + (compute_arch_mask): New static function. + (print_insn_sparc): Delete sparc_v9_p. New static local + current_mach. Resort opcode table if current_mach changes. + Generalize "insn not supported" test. + (compare_opcodes): Prefer supported opcodes to nonsupported ones. + Delete test for v9/!v9. + * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. + (v6notlet): Define. + (brfc): Split into CBR and FBR for coprocessor/fp branches. + (brfcx): Renamed to FBRX. + (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard + coprocessor mnemonics are not supported on the sparclet). + (condf): Renamed to CONDF. + (SLCBCC2): Delete F_ALIAS flag. + +Sat Mar 30 21:45:59 1996 Doug Evans + + * sparc-opc.c (sparc_opcodes): rd must be 0 for + mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. + +Fri Mar 29 13:02:40 1996 Ian Lance Taylor + + * Makefile.in (config.status): Depend upon BFD VERSION file, so + that the shared library version number is set correctly. + +Tue Mar 26 15:47:14 1996 Ian Lance Taylor + + * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From + Miles Bader . + * configure: Rebuild. + +Sat Mar 16 13:04:07 1996 Fred Fish + + * z8kgen.c (internal, gas): Call xmalloc rather than unchecked + malloc. + +Tue Mar 12 12:14:10 1996 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.8. + +Thu Mar 7 15:11:10 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. + * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. + +Tue Mar 5 15:51:57 1996 Ian Lance Taylor + + * configure.in: Don't set SHLIB or SHLINK to an empty string, + since they appear as targets in Makefile.in. + * configure: Rebuild. + +Mon Feb 26 13:03:40 1996 Stan Shebs + + * mpw-make.sed: Edit out shared library support bits. + +Tue Feb 20 20:48:28 1996 Doug Evans + + * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. + (sparc_opcode_archs): Add MASK_V8 to sparclet entry. + (sparc_opcodes): Add sparclet insns. + (sparclet_cpreg_table): New static local. + (sparc_{encode,decode}_sparclet_cpreg): New functions. + * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. + +Tue Feb 20 11:02:44 1996 Alan Modra + + * i386-dis.c (index16): New static variable. + (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the + other way around. + (OP_indirE): Return result of OP_E. + (OP_E): Check for 16 bit addressing mode, and disassemble + correctly. Optimised 32 bit case a little. Don't print + "(base,index,scale)" when sib specifies only an offset. + +Mon Feb 19 12:32:17 1996 Ian Lance Taylor + + * configure.in: Set and substitute SHLIB_DEP. + * configure: Rebuild. + * Makefile.in (SHLIB_DEP): New variable. + (LIBIBERTY_LISTS, BFD_LIST): New variables. + (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If + COMMON_SHLIB, add them to piclist with appropriate modifications. + ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB + here: just use piclist. + +Mon Feb 19 02:03:50 1996 Doug Evans + + * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. + (print_insn_sparc): Rewrite v9/not-v9 tests. + (compare_opcodes): Likewise. + * sparc-opc.c (MASK_): Define. + (v6,v7,v8,sparclite,v9,v9a): Redefine. + (sparclet,v6notv9): Define. + (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. + (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. + +Thu Feb 15 14:45:05 1996 Ian Lance Taylor + + * configure.in: Call AC_PROG_CC before configure.host. + * configure: Rebuild. + + * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). + +Wed Feb 14 19:01:27 1996 Alan Modra + + * i386-dis.c (onebyte_has_modrm): New static array. + (twobyte_has_modrm): New static array. + (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. + +Tue Feb 13 15:15:01 1996 Ian Lance Taylor + + * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not + $(SHLINK). + +Mon Feb 12 16:26:06 1996 Michael Meissner + + * ppc-opc.c (PPC): Undef, so default defination on Windows NT + doesn't conflict. + +Wed Feb 7 13:59:54 1996 Ian Lance Taylor + + * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on + m68010up, not just m68020up | cpu32. + + * Makefile.in (SONAME): New variable. + ($(SHLINK)): Make a link to the transformed name, as well. + (stamp-tshlink): New target. + (install): Skip stamp-tshlink during install. + +Tue Feb 6 12:28:54 1996 Ian Lance Taylor + + * configure.in: Call AC_ARG_PROGRAM. + * configure: Rebuild. + * Makefile.in (program_transform_name): New variable. + (install): Transform library name before installing it. + +Mon Feb 5 16:14:42 1996 Ian Lance Taylor + + * i960-dis.c (mem): Add HX dcinva instruction. + + Support for building as a shared library, based on patches from + Alan Modra : + * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. + New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, + SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. + * configure: Rebuild. + * Makefile.in (ALLLIBS): New variable. + (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. + (COMMON_SHLIB, SHLINK): New variables. + (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. + (STAGESTUFF): Remove variable. + (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). + (stamp-piclist, piclist): New targets. + ($(SHLIB), $(SHLINK)): New targets. + ($(OFILES)): Depend upon stamp-picdir. + (disassemble.o): Build twice if PICFLAG is set. + (MOSTLYCLEAN): Add pic/*.o. + (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. + (distclean): Remove pic and stamp-picdir. + (install): Install shared libraries. + (stamp-picdir): New target. + +Fri Feb 2 17:15:25 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. + Print unknown instruction as "unknown", rather than in hex. + +Tue Jan 30 14:06:08 1996 Ian Lance Taylor + + * dis-buf.c: Include "sysdep.h" before "dis-asm.h". + +Thu Jan 25 20:24:07 1996 Doug Evans + + * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. + +Thu Jan 25 11:56:49 1996 Ian Lance Taylor + + * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte + when necessary. From Ulrich Drepper + . + +Thu Jan 25 03:39:10 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with + sparc_num_opcodes. Update architecture enum values. + * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. + (sparc_opcode_lookup_arch): New function. + (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. + (sparc_opcodes): Add v9a shutdown insn. + +Mon Jan 22 08:29:59 1996 Doug Evans + + * sparc-dis.c (print_insn_sparc): Renamed from print_insn. + If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode + architecture. + (print_insn_sparc64): Deleted. + * disassemble.c (disassembler, case bfd_arch_sparc): Always use + print_insn_sparc. + + * sparc-opc.c (architecture_pname): Add v9a. + +Fri Jan 12 14:35:58 1996 David Mosberger-Tang + + * alpha-opc.h (alpha_insn_set): VAX floating point opcode was + incorrectly defined as 0x16 when it should be 0x15. + (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! + (alpha_insn_set): added cvtst and cvttq float ops. Also added + excb (exception barrier) which is defined in the Alpha + Architecture Handbook version 2. + * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for + OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be + disassembled as or, for example. + +Wed Jan 10 12:37:22 1996 Ian Lance Taylor + + * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. + (_print_insn_mips): Change i from int to unsigned int. + +Thu Jan 4 17:21:10 1996 David Edelsohn + + * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different + from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. + +Thu Dec 28 13:29:19 1995 John Hassey + + * i386-dis.c: Added Pentium Pro instructions. + +Tue Dec 19 22:56:35 1995 Michael Meissner + + * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to + being for Power2. + +Fri Dec 15 14:14:15 1995 J.T. Conklin + + * sh-opc.h (sh_nibble_type): Added REG_B. + (sh_arg_type): Added A_REG_B. + (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc + and stc.l opcodes. + * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. + +Fri Dec 15 16:44:31 1995 Ian Lance Taylor + + * disassemble.c (disassembler): Use new bfd_big_endian macro. + +Tue Dec 12 12:22:24 1995 Ian Lance Taylor + + * Makefile.in (distclean): Remove stamp-h. From Ronald + F. Guilmette . + +Tue Dec 5 13:42:44 1995 Stan Shebs + + From David Mosberger-Tang : + * alpha-dis.c (print_insn_alpha): fixed decoding of cpys + instruction. + +Mon Dec 4 12:29:05 1995 J.T. Conklin + + * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. + (sh_table): Added many SH3 opcodes. + * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. + +Fri Dec 1 07:42:18 1995 Michael Meissner + + * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. + (subco,subco.): Mark this PPC, not PPCCOM. + +Mon Nov 27 13:09:52 1995 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.7. + +Tue Nov 21 18:28:06 1995 Ian Lance Taylor + + * configure: Rebuild with autoconf 2.6. + +Wed Nov 15 19:02:53 1995 Ken Raeburn + + * configure.in: Sort list of architectures. Accept but do nothing + for alliant, convex, pyramid, romp, and tahoe. + +Wed Nov 8 20:18:59 1995 Ian Lance Taylor + + * a29k-dis.c (print_special): Change num to unsigned int. + +Wed Nov 8 20:10:35 1995 Eric Freudenthal + + * a29k-dis.c (print_insn): Cast insn24 to unsigned long when + shifting it. + +Tue Nov 7 15:21:06 1995 Ian Lance Taylor + + * configure.in: Call AC_CHECK_PROG to find and cache AR. + * configure: Rebuilt. + +Mon Nov 6 17:39:47 1995 Harry Dolan + + * configure.in: Add case for bfd_i860_arch. + * configure: Rebuild. + +Fri Nov 3 12:45:31 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. + * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. + (NEXTDOUBLE): Likewise. + (print_insn_m68k): Don't match fmoveml if there is more than one + register in the list. + (print_insn_arg): Handle a place of '8' for a type of 'L'. + +Thu Nov 2 23:06:33 1995 Ian Lance Taylor + + * m68k-opc.c: Use #W rather than #w. + * m68k-dis.c (print_insn_arg): Handle new 'W' place. + +Wed Nov 1 13:30:24 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, + and likewise for all the dbxx opcodes. + +Mon Oct 30 20:50:40 1995 Fred Fish + + * arc-dis.c: Include elf-bfd.h rather than libelf.h. + +Mon Oct 23 11:11:34 1995 James G. Smith + + * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added + the VR4100 specific instructions to the mips_opcodes structure. + +Thu Oct 19 11:05:23 1995 Stan Shebs + + * mpw-config.in, mpw-make.sed: Remove ugly workaround for + ugly Metrowerks bug in CW6, is fixed in CW7. + +Mon Oct 16 12:59:01 1995 Michael Meissner + + * ppc-opc.c (whole file): Add flags for common/any support. + +Tue Oct 10 11:06:07 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + (FLAGS_TO_PASS): Remove BISON. + +Fri Oct 6 16:26:45 1995 Ken Raeburn + + Mon Sep 25 22:49:32 1995 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Recognize all two-word + instructions that take no args by looking at the match mask. + (print_insn_arg): Always print "%" before register names. + [case 'c']: Use "nc" for the no-cache case, as recognized by gas. + [case '_']: Don't print "@#" before address. + [case 'J']: Use "%s" as format string, not register name. + [case 'B']: Treat place == 'C' like 'l' and 'L'. + +Thu Oct 5 22:16:20 1995 Ken Raeburn + + * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode + name correctly. + +Tue Oct 3 08:30:20 1995 steve chamberlain + + From David Mosberger-Tang + + * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. + (alpha_insn_set): added definitions for VAX floating point + instructions (Unix compilers don't generate these, but handcoded + assembly might still use them). + + * alpha-dis.c (print_insn_alpha): added support for disassembling + the miscellaneous instructions in the Alpha instruction set. + +Tue Sep 26 18:47:20 1995 Stan Shebs + + * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, + no longer create sysdep.h, sed ppc-opc.c to work around a + serious Metrowerks C bug. + * mpw-make.in: Remove. + * mpw-make.sed: New file, used by mpw-configure to edit + Makefile.in into an MPW makefile. + +Wed Sep 20 12:55:28 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Tue Sep 19 15:28:36 1995 Ian Lance Taylor + + * m68k-opc.c: Split pmove patterns which use 'P' into patterns + which use '0', '1', and '2' instead. Specify the proper size for + a pmove immediate operand. Correct the pmovefd patterns to be + moves to a register, not from a register. + * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. + +Thu Sep 14 11:58:22 1995 Doug Evans + + * sparc-opc.c (sparc_opcodes): Mark all insns that reference + %psr, %wim, %tbr as F_NOTV9. + +Fri Sep 8 01:07:38 1995 Ian Lance Taylor + + * Makefile.in (Makefile): Just rebuild Makefile when running + config.status. + (config.h, stamp-h): New targets. + * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM + earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when + rebuilding config.h. + * configure: Rebuild. + + * mips-opc.c: Change unaligned loads and stores with "t,A" + operands to use "t,A(b)". + +Thu Sep 7 19:02:46 1995 Jim Wilson + + * sh-dis.c (print_insn_shx): Add F_FR0 support. + +Thu Sep 7 19:02:46 1995 Jim Wilson + + * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate + until 3 instead of until 2. + +Wed Sep 6 21:21:33 1995 Ian Lance Taylor + + * Makefile.in (ALL_CFLAGS): Define. + (.c.o, disassemble.o): Use $(ALL_CFLAGS). + (MOSTLYCLEAN): Add config.log. + (distclean): Don't remove config.log. + * configure.in: Substitute HDEFINES. + * configure: Rebuild. + +Wed Sep 6 15:08:09 1995 Jim Wilson + + * sh-opc.h (sh_arg_type): Add F_FR0. + (sh_table, case fmac): Add F_FR0 as first argument. + +Wed Sep 6 15:08:09 1995 Jim Wilson + + * sh-opc.h (sh_opcode_info): Increase arg array size to 4. + +Tue Sep 5 18:28:10 1995 Doug Evans + + * sparc-dis.c: Remove all references to NO_V9. + +Tue Sep 5 20:03:26 1995 Ian Lance Taylor + + * aclocal.m4: Just include ../bfd/aclocal.m4. + * configure: Rebuild. + +Tue Sep 5 16:09:59 1995 Doug Evans + + * sparc-dis.c (X_DISP19): Define. + (print_insn, case 'G'): Use it. + (print_insn, case 'L'): Sign extend displacement. + +Mon Sep 4 14:28:46 1995 Ian Lance Taylor + + * configure.in: Run ../bfd/configure.host before AC_PROG_CC. + Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute + host_makefile_frag or frags. + * aclocal.m4: New file. + * configure: Rebuild. + * Makefile.in (INSTALL): Set to @INSTALL@. + (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. + (INSTALL_DATA): Set to @INSTALL_DATA@. + (AR): Set to @AR@. + (AR_FLAGS): Set to rc rather than qc. + (CC): Define as @CC@. + (CFLAGS): Set to @CFLAGS@. + (@host_makefile_frag@): Remove. + (config.status): Remove dependency upon @frags@. + + * configure.in: ../bfd/config.bfd now just sets shell variables. + Use them rather than looking through target Makefile fragments. + * configure: Rebuild. + +Thu Aug 31 12:35:32 1995 Jim Wilson + + * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. + +Wed Aug 30 13:52:28 1995 Doug Evans + + * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. + Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic + sparc64 insns. + + * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. + (lookup_{name,value}): New functions. + (prefetch_table): New static local. + (sparc_{encode,decode}_prefetch): New functions. + * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). + +Wed Aug 30 11:11:58 1995 Jim Wilson + + * sh-opc.h: Add blank lines to improve readabililty of sh3e + instructions. + +Wed Aug 30 11:09:38 1995 Jim Wilson + + * sh-dis.c: Correct comment on first line of file. + +Tue Aug 29 15:37:18 1995 Doug Evans + + * disassemble.c (disassembler): Handle bfd_mach_sparc64. + + * sparc-opc.c (asi, membar): New static locals. + (sparc_{encode,decode}_{asi,membar}): New functions. + (sparc_opcodes, membar insn): Fix. + * sparc-dis.c (print_insn): Call sparc_decode_asi. + Support decoding of membar masks. + (X_MEMBAR): Define. + +Sat Aug 26 21:22:48 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. + +Mon Aug 21 17:33:36 1995 Ian Lance Taylor + + * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, + and likewise for the other branches. Add bhs as an alias for bcc, + and likewise for the size variants. Add dbhs as an alias for + dbcc. + +Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-opc.h (FP sts instructions): Update to match reality. + +Mon Aug 7 16:12:58 1995 Ian Lance Taylor + + * m68k-dis.c: (fpcr_names): Add % before all register names. + (reg_names): Likewise. + (print_insn_arg): Don't explicitly print % before register names. + Add % before register names in static array names. In case 'r', + print data registers as `@(Dn)', not `Dn@'. When printing a + memory address, don't print @# before it. + (print_indexed): Change base_disp and outer_disp from int to + bfd_vma. Print using MIT syntax, not mutant invalid Motorola + syntax. Sign extend 8 byte displacement correctly. + (print_base): Print using MIT syntax. Print zpc when appropriate. + Change parameter disp from int to bfd_vma. + + * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases + for jsr. + +Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, + F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. + * sh-opc.h (sh_arg_type): Add new operand types. + (sh_table): Add new opcodes from SH3E Floating Point ISA. + +Sat Aug 5 16:50:14 1995 Fred Fish + + * Makefile.in (distclean): Remove generated file config.h. + +Sat Aug 5 16:50:14 1995 Fred Fish + + * Makefile.in (distclean): Remove generated file config.h. + +Wed Aug 2 18:33:40 1995 Ian Lance Taylor + + * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. + Clean up tables. + * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. + (opcode): Remove. + (print_insn_m68k): Change d to be const. Use m68k_numopcodes + rather than numopcodes. Use m68k_opcodes rather than removed + opcode function. Don't check F_ALIAS. + (print_insn_arg): Change first parameter to be const char *. + * Makefile.in (ALL_MACHINES): Add m68k-opc.o. + (m68k-opc.o): New target. + * configure.in: Build m68k-opc.o for bfd_m68k_arch. + * configure: Rebuild. + +Wed Aug 2 08:23:38 1995 Doug Evans + + * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. + (opcode_bits, opcode_hash_table): New variables. + (opcodes_initialized): Renamed from opcodes_sorted. + (build_hash_table): New function. + (is_delayed_branch): Use hash table. + (print_insn): Renamed from print_insn_sparc, made static. + Build and use hash table. If !sparc64, ignore sparc64 insns, + and vice-versa if sparc64. + (print_insn_sparc, print_insn_sparc64): New functions. + (compare_opcodes): Move sparc64 opcodes to end. + Print commutative insns with constant second. + * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. + +Tue Aug 1 00:12:49 1995 Ian Lance Taylor + + * sh-dis.c (print_insn_shx): Remove unused local dslot. Use + print_address_func for A_BDISP12 and A_BDISP8. Correct test which + avoids printing a delay slot in a delay slot. + * sh-opc.h (sh_table): Fully bracket last entry. + +Mon Jul 31 12:04:47 1995 Doug Evans + + * sparc-opc.c (sllx, srax, srlx): Fix disassembly. + +Wed Jul 12 00:59:34 1995 Ken Raeburn + + * configure.in: Get host_makefile_frag from ${srcdir}. + + * configure.in: Autoconfiscated. Check for string[s].h. Create + config.h from config.in. Don't set up sysdep.h link. + * sysdep.h: New file. + * configure, config.in: New files, generated from configure.in. + * Makefile.in: Updated to be processed autoconf-style. + (distclean): Keep sysdep.h. Remove config.log and config.cache. + (Makefile): Depend on config.status. + (config.status): New rule. + * configure.bat: Update Makefile substitutions. + +Tue Jul 11 14:23:37 1995 Jeff Spiegel + + * mips-opc.c (L1): Define. + (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, + addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, + and wb. + +Tue Jul 11 11:49:49 1995 Ian Lance Taylor + + * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu + if ISA 3 and addu otherwise, replacing or, since some MIPS chips + have multiple add units but only a single logical unit. + + * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, + shifted by 18, without any insertion or extraction function. + (insert_cr, extract_cr): Remove. + +Wed Jun 21 20:05:39 1995 Ken Raeburn + + * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before + register names. + +Thu Jun 15 17:23:31 1995 Stan Shebs + + * mpw-config.in: Add sh and i386 configs, remove sparc config. + * sh-opc.h: Add copyright. + +Mon Jun 5 03:30:43 1995 Ken Raeburn + + * Makefile.in (crunch-m68k): Delete extra target accidentally + checked in a while ago. + +Wed May 24 16:22:13 1995 Jim Wilson + + * sh-opc.h (sh_table): Add SH3 support. + +Wed May 24 14:16:08 1995 Steve Chamberlain + + * sh-opc.h: Added bsrf and braf. + +Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete + bogus [ls]fm{ea,fd} patterns. + + * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. + * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and + initialize it from memory. Make function static. + (print_insn_{big,little}_arm): New functions. + * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for + the correct endianness. + +Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> + + * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from + enum list. + +Wed Apr 19 14:07:03 1995 Michael Meissner + + * m68k-dis.c (opcode): Finish change made by Kung Hsu on April + 17th, so that it builds again using GCC as the compiler. + +Tue Apr 18 12:14:51 1995 Ken Raeburn + + * mips-dis.c (print_insn_little_mips): Cast return value from + bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips + expects an unsigned long, and that might be fewer words of + argument storage (e.g., if bfd_vma is long long on a 32-bit + machine). + (print_insn_big_mips): Likewise with bfd_getb32 value. + (_print_insn_mips): Now static. + +Mon Apr 17 12:23:28 1995 Kung Hsu + + * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because + gcc memory hog problem with initializer is fixed. + +Mon Apr 10 15:55:01 1995 Stan Shebs + + Merge in support for Mac MPW as a host. + (Old change descriptions retained for informational value.) + + * mpw-config.in (archname): Compute from the config. + (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. + + * mpw-config.in (target_arch): Compute from canonical target. + (m68k, mips, powerpc, sparc): Add architectures. + * mpw-make.in (disassemble.c.o): Add. + (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). + + * mpw-config.in (BFD_MACHINES): Set to a default value. + * mpw-make.in (BFD_MACHINES): Remove wired-in value. + + * mpw-make.in (CSEARCH): Add extra-include to search path. + + * mpw-config.in (varargs.h): Don't create. + (sysdep.h): Create using forward-include. + * mpw-make.in (CSEARCH): Add include/mpw to search path. + + * mpw-config.in: New file, MPW version of configure.in. + * mpw-make.in: New file, MPW version of Makefile.in. + +Fri Mar 31 14:23:38 1995 Ken Raeburn + + * alpha-dis.c (print_insn_alpha): Put empty statement after + default label. + +Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. + (low_sign_extend): Likewise. + (get_field): Delete unused function. + (set_field, deposit_14, deposit_21): Likewise. + +Fri Mar 17 15:55:53 1995 J.T. Conklin + + * i386-dis.c: Support for more pentium opcodes. From Guy Harris + (guy@netapp.com). + +Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) + + * alpha-opc.h (OSF_ASMCODE): define + print pal-code names as defined in App C of the + Alpha Architecture Reference Manual + + * alpha-dis.c: cleaned up output + print stylized code forms as defined in App A.4.3 of the + Alpha Architecture Reference Manual + +Wed Mar 8 15:21:14 1995 Ian Lance Taylor + + * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for + `rfe'. + * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', + 'N', and 'M'. + +Wed Mar 8 02:54:05 1995 Ken Raeburn + + * m68k-dis.c (opcode): New function. Returns address of opcode + table entry given index, even if the opcode table was split to + work around gcc bugs. + (print_insn_m68k): Call opcode instead of referencing m68k_opcodes + directly. + (BREAK_UP_BIG_DECL): Make secondary array static and const. + (reg_names): Now const. + (print_insn_arg): Arrays cacheFieldName and names now const. + (print_indexed): Array scales now const. + +Tue Mar 7 16:41:21 1995 Ian Lance Taylor + + * ppc-opc.c: Sort recently added instructions by minor opcode + number within major opcode number. + +Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c: Include libhppa.h. + +Fri Feb 24 19:15:36 1995 Ian Lance Taylor + + * mips-opc.c: Change dli to use M_DLI, and add dla. + +Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Makefile.in (ALL_MACHINES): Add w65-dis.o. + +Thu Feb 16 17:34:41 1995 Ian Lance Taylor + + * mips-opc.c: Add r4650 mul instruction. + +Wed Feb 15 15:45:20 1995 Ian Lance Taylor + + * mips-opc.c: Add uld and usd macros for unaligned double load and + store. + +Tue Feb 14 13:17:37 1995 Michael Meissner + + * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, + mfdcr, mtdcr, icbt, iccci. + +Thu Feb 9 12:28:13 1995 Stan Shebs + + * i960-dis.c (struct tabent, struct sparse_tabent): Change the + signed char fields to shorts, more portable. + +Wed Feb 8 17:29:29 1995 Stan Shebs + + * i960-dis.c (struct tabent, struct sparse_tabent): Declare the + char fields as signed chars, since they may have negative values. + +Mon Feb 6 10:52:06 1995 J.T. Conklin + + * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum + (mycroft@netbsd.org). + +Mon Jan 30 12:38:00 1995 Ian Lance Taylor + + From "Logg, Ed" : + * ppc-opc.c (extract_bdm): Correct parenthezisation. + * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized + value. + +Thu Jan 26 18:32:08 1995 Ian Lance Taylor + + * ppc-opc.c: Changes based on patch from David Edelsohn + . + (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of + SPR. + (FXM_MASK): Define. + (insert_tbr): New static function. + (extract_tbr): New static function. + (XFXFXM_MASK, XFXM): Define. + (XSPRBAT_MASK, XSPRG_MASK): Define. + (powerpc_opcodes): Add instructions to access special registers by + name. Add mtcr and mftbu. + +Tue Jan 17 10:56:43 1995 Ian Lance Taylor + + * mips-opc.c (P3): Define. + (mips_opcodes): Add mad and madu. + +Sun Jan 15 16:32:59 1995 Steve Chamberlain + + * configure.in: Add W65 support. + * disassemble.c: Likewise. + * w65-opc.h, w65-dis.c: New files. + +Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit + immediates. + +Tue Dec 20 11:25:12 1994 Ian Lance Taylor + + * mips-opc.c: Add dli as a synonym for li. + +Thu Dec 8 18:23:31 1994 Ken Raeburn + + * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and + print something for reserved opcode values, even if it won't + assemble again. + + * mips-dis.c (_print_insn_mips): When initializing, shift right + and mask, to avoid sign extension problems on the Alpha. + + * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr + control registers. + +Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh-opc.h (mov.l gbr): Get direction right. + * sh-dis.c (print_insn_shx): New function. + (print_insn_shl, print_insn_sh): Call print_insn_shx to + print opcodes with right byte order. + +Thu Nov 3 19:32:22 1994 Ken Raeburn + + * ns32k-dis.c (struct ns32k_option): Renamed from struct option, + to avoid conflicts with getopt. + +Mon Oct 31 18:48:10 1994 Ian Lance Taylor + + * hppa-dis.c (print_insn_hppa): Read the instruction using + bfd_getb32, so that it works on a little endian or 64 bit host. + Remove unused local variable op. + +Tue Oct 25 17:07:57 1994 Ian Lance Taylor + + * mips-opc.c: Use or instead of addu for pseudo-op move, since + addu does not work correctly if -mips3. + +Wed Oct 19 13:40:16 1994 Ian Lance Taylor + + * a29k-dis.c (print_special): Add special register names defined + on 29030, 29040 and 29050. + (print_insn): Handle new operand type 'I'. + +Wed Oct 12 11:59:55 1994 Ian Lance Taylor + + * Makefile.in (INSTALL): Use top level install.sh script. + +Wed Oct 5 19:16:29 1994 Ian Lance Taylor + + * sparc-dis.c: Rewrite to use bitfields, rather than a union, so + that it works on a little endian host. + +Tue Oct 4 12:14:21 1994 Ian Lance Taylor + + * configure.in: Use ${config_shell} when running config.bfd. + +Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. + +Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * a29k-dis.c (print_insn): Print the opcode. + +Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. + +Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) + + * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. + +Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions + which store a value into memory. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * configure.in, Makefile.in, disassemble.c: Add support for the ARM. + * arm-dis.c, arm-opc.h: New files. + +Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) + + * Makefile.in (ns32k-dis.o): Add dependency. + * ns32k-dis.c (print_insn_arg): Declare initialized local as + string, not as array of chars. + +Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. + + * sparc-opc.c: Added sparclite extended FP operations, and + versions of v9 impdep* instructions permitting specification of + the OPF field. + +Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960-dis.c (reg_names): Now const. + (struct sparse_tabent): New type, copied from array type in mem + function. + (ctrl): Local static array ctrl_tab now const. + (cobr): Local static array cobr_tab now const. + (mem): Local variables reg1, reg2, reg3 now point to const. Local + static variable mem_tab no longer explicitly initialized. Changed + mem_init to const array of struct sparse_tabent. + (reg): Local static variable reg_tab no longer explicitly + initialized. Changed reg_init to const array of struct + sparse_tabent. + (ea): Local static array scale_tab now const. + + * i960-dis.c (reg): Added i960JX instructions to reg_init table. + (REG_MAX): Updated. + +Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: the disassember needs to be enabled for + "objdump -d" to work in djgpp. + +Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * ns32k-dis.c: Deleted all code in "#ifdef GDB". + (invalid_float): Enabled general version, doesn't require running + on ns32k host. Changed to take char* argument, and test for + explicitly specified sizes, instead of using sizeof() on host CPU + types. + (INVALID_FLOAT): Cast first argument. + (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, + list_P032, list_M032): Now const. + (optlist, list_search): Made appropriate arguments now point to + const. + (print_insn_arg): Changed static array of one-character-string + pointers into a static const array of characters; fixed sprintf + statement accordingly. + +Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * ns32k-dis.c: Semi-new file. Had apparently been dropped + from distribution. A ns32k-dis.c from a previous distribution has + been brought up to date and supports the new interface. + + * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. + + * configure.in: add bfd_ns32k_arch target support. + + * Makefile.in: add ns32k-dis.o to ALL_MACHINES. + Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. + +Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch + disassembly right. + +Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) + + * h8300-dis.c, mips-dis.c: Don't use true and false. + +Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) + + * configure.in: Change --with-targets to --enable-targets. + +Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * mips-dis.c (_print_insn_mips): Build a static hash table mapping + opcodes to the first instruction with that opcode, to speed + disassembly of large files. From ralphc@pyramid.com (Ralph + Campbell). + +Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * Makefile.in (mostlyclean): Fix typo (was mostyclean). + +Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) + + * configure.bat: update to latest makefile.in + +Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) + + * a29k-dis.c (print_insn): Print 'x' type operand in hex. + * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. + * sh-dis.c (print_insn_sh): Don't recur endlessly if delay + slot insn is in a delay slot. + * z8k-opc.h: (resflg): Fix patterns. + * h8500-opc.h Fix CR insn patterns. + +Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and + "cmpl" before POWER versions, so that gas -many uses them. + +Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * disassemble.c: New file. + * Makefile.in (OFILES): Add disassemble.o. + (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). + * configure.in: Define ARCHDEFS in Makefile. Code taken from + binutils/configure.in. + + * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the + opcode being examined. + +Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. + (insert_ral, insert_ram, insert_ras): New functions. + (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and + RAS for store with update. + +Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn + (edelsohn@npac.syr.edu). + +Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (mips_opcodes): Correct operands of "nor" with an + immediate argument. + +Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) + + * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". + +Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): The signedp field has been + removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag + instead. Add new operand SISIGNOPT. + (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. + Based on patch from David Edelsohn (edelsohn@npac.syr.edu). + * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather + than signedp field. + +Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * i386-dis.c (struct private): Renamed to dis_private. `private' + is a reserved word for dynix cc. + +Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Change error message to refer to bfd/config.bfd + rather than bfd/configure.in. + +Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) + + * ppc-opc.c: Define POWER2 as short alias flag. + (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and + fsqrt. + +Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Don't read a second word for + opcodes 0, 1, 2 and 3. + +Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. + +Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m68881-ext.c: Removed; no longer used. + * Makefile.in: Changed accordingly. + + * m68k-dis.c (ext_format_68881): Don't declare. + (print_insn_m68k): If an instruction uses place 'i', it uses at + least four fixed bytes. + (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For + extended float, convert to double using floatformat_to_double, not + ieee_extended_to_double, and fetch the data before converting it. + +Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: It's sqrt.s, not sqrt.w. From + davidj@ICSI.Berkeley.EDU (David Johnson). + +Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the + PowerPC uses bdnz[l][a]. + +Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * dis-buf.c, i386-dis.c: Include sysdep.h. + +Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. + + * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported + by Motorola PowerPC 601 with PPC_OPCODE_601. + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): + Disassemble Motorola PowerPC 601 instructions as well as normal + PowerPC instructions. + +Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * i960-dis.c (reg, mem): Just use a static array instead of + calling xmalloc. + +Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the + condition name index if this is for a negated condition. + + * hppa-dis.c (print_insn_hppa): No space before 'H' operand. + Floating point format for 'H' operand is backwards from normal + case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' + operands (fmpyadd and fmpysub), handle bizarre register + translation correctly for single precision format. + + * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' + or 'I' operands if the next format specifier is 'M' (fcmp + condition completer). + +Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c (powerpc_operands): New operand type MBE to handle a + single number giving a bitmask for the MB and ME fields of an M + form instruction. Change NB to accept 32, and turn it into 0; + also turn 0 into 32 when disassembling. Seperated SH from NB. + (insert_mbe, extract_mbe): New functions. + (insert_nb, extract_nb): New functions. + (SC_MASK): Mask out SA and LK bits. + (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, + RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark + "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", + "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", + "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to + use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. + (powerpc_macros): Define table of macro definitions. + (powerpc_num_macros): Define. + + * ppc-dis.c (print_insn_powerpc): Don't skip optional operands + if PPC_OPERAND_NEXT is set. + +Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of + char. Retrieve contents using bfd_getl32 instead of shifting. + +Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ppc-opc.c: New file. Opcode table for PowerPC, including + opcodes for POWER (RS/6000). + * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. + * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. + (CFILES): Add ppc-dis.c. + (ppc-dis.o, ppc-opc.o): New targets. + * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. + +Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. + No space before 'u', 'f', or 'N'. + +Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading + farther than we should. + + * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. + +Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. + +Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + * i960-dis.c (print_insn_i960): Only read word2 if the instruction + needs it, to prevent reading past the end of a section. + +Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Use macro for j instruction, to support SVR4 PIC. + Removed t,A case for la; always use t,A(b) case. + +Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + From Ted Lemen + * mips-dis.c (print_insn_arg): Handle 'k'. + * mips-opc.c: Make cache use k, not t. + +Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add + FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct + FLOAT_FORMAT_CODE to put out floating point register names. + +Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. + +Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. + +Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts + larger than 32. Moved dsxx32 variants first for disassembler. + +Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8kgen.c, z8k-opc.h: Add full lda information. + +Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Do not emit a space after + movb instructions. Any necessary space will be emitted by + the code to handle nullification completers. + +Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Moved l.d down so that it disassembles as ldc1. + +Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-opc.h: Add ldl_l, fix typo for ldq_u. + * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. + +Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Correct lwu opcode value (book had it wrong). + +Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * z8k-dis.c (FETCH_DATA): get just the right amount of data. + (unpack_instr): Cope with ARG_IMM4M1 type instructions. + +Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * m88k-dis.c (m88kdis): comment change. Remove space after + printing mnemonic. + (printop): handle new arg types DEC and XREG for m88110. + +Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) + + * hppa-dis.c (print_insn_hppa): Handle 'z' operand + type for absolute branch addresses. Delete special + "ble" and "be" code in 'W' operand code. + +Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set hazard information correctly for branch + likely instructions. + +Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use + info->fprintf_func for printing and info->print_address_func for + address output. + +Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Set INSN_TRAP for tXX instructions. + +Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): + Corrected second case of "b" for disassembler. + +Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls + to BFD swapping routines to correspond to BFD name changes. + +Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Change div machine instruction to be z,s,t rather + than s,t. Change div macro to be d,v,t rather than d,s,t. + Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, + rem and remu which generates only the corresponding div + instruction. This is for compatibility with the MIPS assembler, + which only generates the simple machine instruction when an + explicit destination of $0 is used. + * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). + +Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set + WR_31 hazard for bal, bgezal, bltzal. + +Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use print function + from within the disassemble_info, not fprintf_filtered. + +Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff + Law, law@cs.utah.edu.) + +Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c ("absu"): Removed. + ("dabs"): Added. + +Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added r6000 and r4000 instructions and macros. + Changed hazard information to distinguish between memory load + delays and coprocessor load delays. + +Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. + +Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * configure.in: Don't pass cpu to config.bfd. + +Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c (m88kdis): Make class unsigned. + +Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha-dis.c (print_insn_alpha): One branch format case was + missing the instruction name. + +Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. + Add the arch-specific auxiliary files. + (OFILES): Remove the arch-specific auxiliary files + and use BFD_MACHINES instead of DIS_LIBS. + * configure.in: Set BFD_MACHINES based on --with-targets option. + +Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly + for swc1. + +Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-opc.c: Change CONST to const to deal with gcc + -Dconst=__const -traditional. + +Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took + coprocessor instructions out of #if 0, and made them use new + argument type "C". + +Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. + +Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) + + * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch + instruction, for use by the disassembler. + + * sparc-dis.c (SEX): Add sign extension macro. Replace many + hand-coded sign extensions that depended on 32-bit host ints. + FIXME, we still depend on big-endian host bitfield ordering. + (sparc_print_insn): Set the insn_info_valid field, and the + other fields that describe the instruction being printed. + +Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) + + * sparc-opc.c (call): Accept all 6 addressing modes valid for + `jmp' instead of just one of them. + +Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. + (fput_fp_reg_r): Renamed from fput_reg_r. + (fput_fp_reg): New function. + (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. + + * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. + + * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. + +Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) + + * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. + + * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', + don't output a space. + + * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. + +Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * mips-opc.c: New file, containing opcode table from + ../include/opcode/mips.h. + * Makefile.in: Add it. + +Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k-dis.c: New file, moved in from gdb and changed to use the + new dis-asm.h disassembler interface. + * Makefile.in (DIS_LIBS): Added m88k-dis.o. + (m88k-dis.o): New target. + +Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to + argument string const char * to correspond to opcode/mips.h. + +Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips-dis.c: Updated to account for name changes in new version + of opcode/mips.h. + * Makefile.in: Added header file dependencies. + +Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) + + * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. + +Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign + extend, rather than shifts. + +Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * Makefile.in: Undo 15 June change. + +Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) + + * m68k-dis.c (print_insn_arg): Change return value to byte count + or error code. + * m68k-dis.c: Re-write to detect invalid operands before + printing anything, so we can handle this the same way we + handle invalid opcodes. + +Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * sh-dis.c, sh-opc.h: Understand some more opcodes. + +Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) + + * hppa-dis.c: Include and sysdep.h before other + header files. + +Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * sparc-dis.c: Don't declare qsort, since sysdep.h might. + + * configure.in: Do make sysdep.h link. + * Makefile.in: Search ../include. Don't search ../bfd. + +Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. + Do not print a space before the completers specified by + 'a' and 'd'. + +Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) + + * mips-dis.c: No longer need to bomb out if HOST_64_BIT is + defined, since gdb has been fixed. + + Changes from Jeff Law, law@cs.utah.edu: + * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, + fput_reg_r, fput_creg, fput_const, and fputs_filtered should + be a *disassemble_info, not a *FILE. + * hppa-dis.c: Support 'd', '!', and 'a'. + * hppa-dis.c: Support 's' to extract a 2 bit space register. + * hppa-dis.c: Delete cases which are no longer needed. + +Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) + + * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. + +Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with + H8/300-H opcodes. + +Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. + * configure.in: No longer need to configure to get sysdep.h. + +Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) + + * Patches from Jeffrey Law . + * hppa-dis.c: Support 'I', 'J', and 'K' in output + templates for 1.1 FP computational instructions. + +Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Address argument is type + bfd_vma. + * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): + Ditto. + + * h8500-opc.h (addr_class_type): No comma at end of enumerator. + * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. + + * sparc-dis.c (compare_opcodes): Move static declaration to + top-level. + +Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp + instruction, remove unimp hack from 'l' argument. + +Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) + + * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's + happy. + +Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) + + * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): + * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor + instructions. + +Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some + arrays of string pointers to 2-d arrays of chars, to save + space. + +Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) + + * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: + Cast second arg to read_memory_func to "bfd_byte *", as necessary. + +Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * hppa-dis.c: New file from Utah, adapted to new disassembler + calling interface. + * Makefile.in: Include it. + +Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * sh-dis.c, sh-opc.h: New files. + +Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha-dis.c, alpha-opc.h: New files. + +Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed + value. + +Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) + + * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. + +Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than + const. + +Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) + + * sparc-dis.c: Use fprintf_func a few places where I forgot, + and double percent signs a few places. + + * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. + + * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: + Use info->print_address_func not print_address. + + * dis-buf.c (generic_print_address): New function. + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add sparc-dis.c. + sparc-dis.c: New file, merges binutils and gdb versions as follows: + From GDB: + Add `add' instruction to the set that get checked + for a preceding `sethi' in order to print an absolute address. + * (print_insn): Disassembly prefers real instructions. + (is_delayed_branch): Speed up. + * sparc-opc.c: Add ALIAS bit to aliases. Fix up opcode tables. + Still missing some float ops, and needs testing. + * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by + F_ALIAS. Use printf, not fprintf, when not passing a file + pointer... + (compare_opcodes): Check that identical instructions have + identical opcodes, complain otherwise. + From binutils: + * New 'm' arg. + * Include reg_names. + From neither: + Use dis-asm.h/read_memory_func interface. + +Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) + + * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): + deliberately return non-zero to setjmp from longjmp. Otherwise + this code fails to compile. + +Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) + + * m68k-dis.c: Fix prototype for fetch_arg(). + +Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-buf.c: New file, for new read_memory_func interface. + Makefile.in (OFILES): Include it. + m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: + Use new read_memory_func interface. + +Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. + * h8500-opc.h: Fix couple of opcodes. + +Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: add dvi & installcheck targets + +Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) + + * Makefile.in: Update for h8500-dis.c. + +Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * h8500-dis.c, h8500-opc.h: New files + +Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) + + * mips-dis.c, z8k-dis.c: Converted to use interface defined in + ../include/dis-asm.h. + * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c + and ../gdb/m68k-pinsn.c). + * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c + and ../gdb/i386-pinsn.c). + * m68881-ext.c: New file. Moved definition of + ext_format ext_format_68881 from ../gdb/m68k-tdep.c. + * Makefile.in: Adjust for new files. + * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). + * m68k-dis.c: Recognize '9' placement code, so (say) pflush + can be dis-assembled. + +Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * mips-dis.c (print_insn_arg): Now returns void. + +Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) + + * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h + files that use the macros. + +Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips-dis.c: New file, from gdb/mips-pinsn.c. + * Makefile.in (DIS_LIBS): Added mips-dis.o. + (CFILES): Added mips-dis.c. + +Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines + * z8kgen.c, z8k-opc.h: fix sizes of some shifts. + +Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) + + * Makefile.in: Improve *clean rules. + * configure.in: Allow a default host. + +Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep + files include other sysdep files + +Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint + +Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) + + * configure.in: For host support, use ../bfd/configure.host + so it stays in sync with the ../bfd/hosts database. + +Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use cpu-vendor-os triple instead of nested cases + +Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c (unparse_instr): fix bug where opcode returned was + *always* the wrong one. + +Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8kgen.c: added copyright info + +Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c (unparse_instr): prettier tabs + * z8kgen.c z8k-opc.h: bug fixes in tables + +Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) + + * configure.in: Add ncr* configuration. + * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make + picayune ANSI compilers happy. + +Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) + + * configure.in (i386): Make i386 and i486 synonymous for now. + * configure.in (i[34]86-*-sysv4): Add my_host definition. + +Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Fix typo. + +Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) + + * Makefile.in (make): Remove obsolete crud. + (sparc-opc.o): Avoid Sun Make VPATH bug. + +Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * Makefile.in: since there are no SUBDIRS, remove rule and + references of subdir_do. + +Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * Makefile.in (install): Get the library name right here too. + Don't install bfd.h, since it's unrelated to this library. No + subdirs to recurse into, either. + (CFILES): The source file has a .c suffix, not .o. + + * sparc-opc.c: New file, moved from BFD. + * Makefile.in (OFILES): Build it. + +Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) + + * z8k-dis.c: fixed forward refferences of some declarations. + +Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) + + * Makefile.in: get the name of the library right + +Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * z8k-dis.c: knows how to disassemble z8k stuff + * z8k-opc.h: new file full of z8000 opcodes + +Fri Aug 28 15:38:03 1992 Ken Raeburn (raeburn@cygnus.com) + + * Renamed opc-sparc.c to sparc-opc.c for systems with short + filename constraints. + * Makefile.in: Updated to reflect change. + + +Local Variables: +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/ChangeLog-9899 b/external/gpl3/gdb/dist/opcodes/ChangeLog-9899 new file mode 100644 index 000000000000..3f8bf77de018 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ChangeLog-9899 @@ -0,0 +1,1669 @@ +1999-12-27 Alan Modra + + * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall". + +Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c, m10300-dis.c: Add am33 support. + +Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names. + (print_insn_hppa): Handle 'B' operand. + +1999-11-22 Nick Clifton + + * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction. + +1999-11-18 Gavin Romig-Koch + + * mips-opc.c (I5): New. + (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s + madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, + pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New. + +Mon Nov 15 19:34:58 1999 Donald Lindsay + + * arm-dis.c (print_insn_arm): Added general purpose 'X' format. + * arm-opc.h (print_insn_arm): Added comment documenting + the 'X' format just added to arm-dis.c. + +1999-11-15 Gavin Romig-Koch + + * mips-opc.c (la): Create a version that just uses addiu directly. + (dla): Expand to daddiu if possible. + +1999-11-11 Nick Clifton + + * mips-opc.c: Add ssnop pattern. + +1999-11-01 Gavin Romig-Koch + + * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. + +1999-10-29 Nick Clifton + + * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA + (d30v_format_tab): Define the SHORT_AR format. + +1999-10-28 Nick Clifton + + * mcore-dis.c: Remove spurious code introduced in previous delta. + +1999-10-27 Scott Bambrough + + * arm-dis.c: Include sysdep.h to prevent compile time warnings. + +1999-10-18 Michael Meissner + + * alpha-opc.c (alpha_operands): Fill in missing initializer. + (alpha_num_operands): Convert to unsigned. + (alpha_num_opcodes): Ditto. + (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED. + (insert_rca): Ditto. + (insert_za): Ditto. + (insert_zb): Ditto. + (insert_zc): Ditto. + (extract_bdisp): Ditto. + (extract_jhint): Ditto. + (extract_ev6hwjhint): Ditto. + +Sun Oct 10 01:48:01 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC', + 'co', '@'. + + * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'. + + * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q". + +Thu Oct 7 00:12:43 MDT 1999 Diego Novillo + + * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for + rac/rachi instructions. + (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi, + slae, st and st2w. + +1999-10-04 Doug Evans + + * fr30-asm.c, fr30-desc.h: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h: Rebuild. Add m32rx support. + * m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c: Ditto. + +1999-09-29 Nick Clifton + + * sh-opc.h: Fix bit patterns for several load and store + instructions. + +Thu Sep 23 08:27:20 1999 Jerry Quinn + + * configure.in (Canonicalization of target names): Remove adding + ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14 + generates $ac_config_sub with a ${CONFIG_SHELL} already. + * configure: Regenerate. + +Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa): Escape '%' in output strings. + + * hppa-dis.c (print_insn_hppa): Handle 'Z' argument. + +1999-09-07 Nick Clifton + + * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct + names for the mulu and muls patterns. + +1999-09-04 Steve Chamberlain + + * pj-opc.c: New file. + * pj-dis.c: New file. + * disassemble.c (disassembler): Handle bfd_arch_pj. + * configure.in: Handle bfd_pj_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add pj-dis.c and pj-opc.c. + (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo. + * configure, Makefile.in: Rebuild. + +1999-09-04 H.J. Lu + + * i386-dis.c (print_insn_i386): Set bytes_per_line to 7. + +Mon Aug 30 18:56:14 1999 Richard Henderson + + * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31. + +1999-08-04 Doug Evans + + * fr30-asm.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-asm.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Aug 28 00:27:24 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float + register args by 'f'. + + * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |. + + * hppa-dis.c (MASK_10, read_write_names, add_compl_names, + extract_10U_store): New. + (print_insn_hppa): Add new completers. + + * hppa-dis.c (signed_unsigned_names,mix_half_names, + saturation_names): New. + (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'. + + * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. + + * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!' + + * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits + to decide to print a space. + +1999-08-21 Alan Modra + + * i386-dis.c: Add AMD athlon instruction support. + +1999-08-10 Ian Lance Taylor + + From Wally Iimura : + * dis-buf.c (buffer_read_memory): Rewrite expression to avoid + overflow at end of address space. + (generic_print_address): Use sprintf_vma. + +1999-08-08 Ian Lance Taylor + + * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to + MKDEP. Rebuild dependencies. + * Makefile.in: Rebuild. + +Fri Aug 6 09:46:35 1999 Jerry Quinn + + * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names, + add_cond_64_names, wide_add_cond_names, logical_cond_64_names, + unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New. + (print_insn_hppa): Add 64 bit condition completers. + +Thu Aug 5 16:59:58 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Change condition args to use + '?' prefix. + +Wed Jul 28 04:33:58 1999 Jerry Quinn + + * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E' + code. + +1999-07-21 Ian Lance Taylor + + From Mark Elbrecht: + * configure.bat: Remove; obsolete. + +1999-07-11 Ian Lance Taylor + + * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate. + (generic_strcat_address): Add cast to avoid warning. + * i386-dis.c: Initialize all structure fields to avoid warnings. + Add ATTRIBUTE_UNUSED as appropriate. + +1999-07-08 Jakub Jelinek + + * sparc-dis.c (print_insn_sparc): Differentiate between + addition and oring when guessing symbol for comment. + +1999-07-05 Nick Clifton + + * arm-dis.c (print_insn_arm): Display hex equivalent of rotated + constant. + +1999-06-23 Alan Modra + + * i386-dis.c: Mention intel mode specials in macro char comment. + +1999-06-21 Ian Lance Taylor + + * alpha-dis.c: Don't include . + * arm-dis.c: Include "sysdep.h". + * tic30-dis.c: Don't include or . Include + "sysdep.h". + * Makefile.am: Rebuild dependencies. + * Makefile.in: Rebuild. + +1999-06-16 Nick Clifton + + * arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange + SWIs. + +1999-06-14 Nick Clifton & Drew Mosley + + * arm-dis.c (arm_regnames): Turn into a pointer to a register + name set. + (arm_regnames_standard): New variable: Array of ARM register + names according to ARM instruction set nomenclature. + (arm_regnames_apcs): New variable: Array of ARM register names + according to ARM Procedure Call Standard. + (arm_regnames_raw): New variable: Array of ARM register names + using just 'r' and the register number. + (arm_toggle_regnames): New function: Toggle the chosen register set + naming scheme. + (parse_disassembler_options): New function: Parse any target + disassembler command line options. + (print_insn_big_arm): Call parse_disassembler_options if any + are defined. + (print_insn_little_arm): Call parse_disassembler_options if any + are defined. + +1999-06-13 Ian Lance Taylor + + * i386-dis.c (FWAIT_OPCODE): Define. + (used_prefixes): New static variable. + (fetch_data): Don't print an error message if we have already + fetched some bytes successfully. + (ckprefix): Clear used_prefixes. Use FWAIT_OPCODE, not 0x9b. + (prefix_name): New static function. + (print_insn_i386): If setjmp fails, indicating a data error, but + we have managed to fetch some bytes, print the first one as a + prefix or a .byte pseudo-op. If fwait is followed by a non + floating point instruction, print the first prefix. Set + used_prefixes when prefixes are used. If any prefixes were not + used after disassembling the instruction, print the first prefix + instead of printing the instruction. + (putop): Set used_prefixes when prefixes are used. + (append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise. + (OP_DIR, OP_SIMD_Suffix): Likewise. + +1999-06-07 Jakub Jelinek + + * sparc-opc.c: Fix up set, setsw, setuw operand kinds. + Support signx %reg, clruw %reg. + +1999-06-07 Jakub Jelinek + + * sparc-opc.c: Add aliases Solaris as supports. + +Mon Jun 7 12:04:52 1999 Andreas Schwab + + * Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c. + * Makefile.in: Regenerated. + +1999-06-03 Philip Blundell + + * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR + when target is PC-relative. + +1999-05-28 Linus Nordberg + + * m68k-opc.c: Rename MACL/MSACL to MAC/MSAC. Add MACM/MSACM. Add + MOVE MACSR,CCR. + + * m68k-dis.c (fetch_arg): Add places `n', `o'. + + * m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK. + Add mcf5206e to appropriate instructions. + Add alias for MAC, MSAC. + + * m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place + `N'. + + * m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl, + macw, remsl, remul for mcf5307. Change mcf5200 --> mcf. + + * m68k-dis.c: Add format `u' and places `h', `m', `M'. + +1999-05-18 Alan Modra + + * i386-dis.c (Ed): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd. + (Rw): Remove. + (OP_rm): Rename to OP_Rd. + (ONE): Remove. + (OP_ONE): Remove. + (putop): Add const to template and p. + (print_insn_x86): Delete. + (print_insn_i386): Merge old function print_insn_x86. Add const + to dp. + (struct dis386): Add const to name. + (dis386_att, dis386_intel): Add const. + (dis386_twobyte_att, dis386_twobyte_intel): Add const. + (names32, names16, names8, names_seg, index16): Add const. + (grps, prefix_user_table, float_reg): Add const. + (float_mem_att, float_mem_intel): Add const. + (oappend): Add const to s. + (OP_REG): Add const to s. + (ptr_reg): Add const to s. + (dofloat): Add const to dp. + (OP_C): Don't skip modrm, it's now done in OP_Rd. + (OP_D): Ditto. + (OP_T): Ditto. + (OP_Rd): Check for valid mod. Call Op_E to print. + (OP_E): Handle d_mode arg. Check for bad sfence,lea,lds etc. + (OP_MS): Check for valid mod. Call Op_EM to print. + (OP_3DNowSuffix): Set obufp and use oappend rather than + strcat. Call BadOp() for errors. + (OP_SIMD_Suffix): Likewise. + (BadOp): New function. + +1999-05-12 Alan Modra + + * i386-dis.c (dis386_intel): Remove macro chars, except for + jEcxz. Change cWtR and cRtd to cW and cR. + (dis386_twobyte_intel): Remove macro chars here too. + (putop): Handle R and W macros for intel mode. + + * i386-dis.c (SIMD_Fixup): New function. + (dis386_twobyte_att): Use it on movlps and movhps, and change + Ev to EX on these insns. Change movmskps Ev, XM to Gv, EX. + (dis386_twobyte_intel): Same here. + + * i386-dis.c (Av): Remove. + (Ap): remove lptr. + (lptr): Remove. + (OPSIMD): Define. + (OP_SIMD_Suffix): New function. + (OP_DIR): Remove dead code. + (eAX_reg..eDI_reg): Renumber. + (onebyte_has_modrm): Table numbering comments. + (INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86. + (print_insn_x86): Move all prefix oappends to after uses_f3_prefix + checks. Print error on invalid dp->bytemode2. Remove simd_cmp, + and handle SIMD cmp insns in OP_SIMD_Suffix. + (info->bytes_per_line): Bump from 5 to 6. + (OP_None): Remove. + (OP_E): Use INTERNAL_DISASSEMBLER_ERROR. Handle sfence. + (OP_3DNowSuffix): Ensure mnemonic index unsigned. + + PIII SIMD support from Doug Ledford + * i386-dis.c (XM, EX, None): Define. + (OP_XMM, OP_EX, OP_None): New functions. + (USE_GROUPS, USE_PREFIX_USER_TABLE): Define. + (GRP14): Rename to GRPAMD. + (GRP*): Add USE_GROUPS flag. + (PREGRP*): Define. + (dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns. + (twobyte_has_modrm): Add SIMD entries. + (twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New. + (grps): Add SIMD insns. + (print_insn_x86): New vars uses_f3_prefix and simd_cmp. Don't + oappend repz if uses_f3_prefix. Add code to handle new groups for + SIMD insns. + + From Maciej W. Rozycki + * i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn + operand from Av to Jv. + +1999-05-07 Nick Clifton + + * mcore-dis.c (print_insn_mcore): Use .short to display + unidentified instructions, not .word. + +1999-04-26 Tom Tromey + + * aclocal.m4, configure: Updated for new version of libtool. + +1999-04-14 Doug Evans + + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + +Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) + + * hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0 + instructions. + +1999-04-10 Doug Evans + + * fr30-desc.c, fr30-desc.h, fr30-ibld.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-opinst.c: Rebuild. + +1999-04-06 Ian Lance Taylor + + * opintl.h (LC_MESSAGES): Never define. + +1999-04-04 Ian Lance Taylor + + * i386-dis.c (intel_syntax, open_char, close_char): Make static. + (separator_char, scale_char): Likewise. + (print_insn_x86): Likewise. + (print_insn_i386): Likewise. Add declaration. + +1999-03-26 Doug Evans + + * fr30-dis.c: Rebuild. + * m32r-dis.c: Rebuild. + +1999-03-23 Ian Lance Taylor + + * m68k-opc.c: Change compare instructions to use "@s" rather than + ";s" when used with an immediate operand. + +1999-03-22 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Delete. + (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c, + fr30-opc.h: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c, + m32r-opc.h: Rebuild. + * po/opcodes.pot: Rebuild. + +1999-03-16 Martin Hunt + + * d30v-opc.c (mvtsys): Remove FLAG_LKR. + +1999-03-11 Doug Evans + + * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. + (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. + * fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c: Rebuild. + * m32r-opinst.c: Rebuild. + +1999-02-25 Doug Evans + + * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. + (cgen_hw_lookup_by_num): Rewrite. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + +Sat Feb 13 14:06:19 1999 Richard Henderson + + * alpha-opc.c: Add sqrt+flags patterns. Add EV6 PALcode insns. + (insert_jhint): Fix insertion mask. + * alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns. + +1999-02-10 Doug Evans + + * Makefile.in: Rebuild. + +1999-02-09 Doug Evans + + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: Delete. + * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. + * Makefile.am: Remove references to them. + (HFILES): Add fr30-desc.h, m32r-desc.h. + (CFILES): Add fr30-desc.c, fr30-ibld.c, m32r-desc.c, m32r-ibld.c, + m32r-opinst.c. + (ALL_MACHINES): Update. + * configure.in: Redo handling of cgen_files. + (bfd_i960_arch): Delete i960c-*.lo files. + * configure: Regenerate. + * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (hash_insn_array): Rewrite. + * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. + (cgen_lookup_insn,cgen_get_insn_operands): Define here. + (cgen_lookup_get_insn_operands): Ditto. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + * po/POTFILES.in: Rebuild. + * po/opcodes.pot: Rebuild. + +Fri Feb 5 00:04:24 1999 Ian Lance Taylor + + * Makefile.am: Rebuild dependencies. + (HFILES): Add fr30-opc.h. + (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. + * Makefile.in: Rebuild. + + * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. + Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to + AC_PROG_INSTALL. + * acconfig.h: Remove. + * configure: Rebuild with current autoconf/automake. + * aclocal.m4: Likewise. + * config.in: Likewise. + * Makefile.in: Likewise. + +Thu Feb 4 13:48:52 1999 Ian Lance Taylor + + * m68k-opc.c: Correct move (not movew) to status word on 5200. + +Mon Feb 1 20:54:36 1999 Catherine Moore + + * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. + * i386-dis.c (x_mode): Define. + (dis386): Remove. + (dis386_att): New. + (dis386_intel): New. + (dis386_twobyte): Remove. + (dis386_twobyte_att): New. + (dis386_twobyte_intel): New. + (print_insn_x86): Use new arrays. + (float_mem): Remove. + (float_mem_intel): New. + (float_mem_att): New. + (dofloat): Use new float_mem arrays. + (print_insn_i386_att): New. + (print_insn_i386_intel): New. + (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. + (putop): Handle intel syntax. + (OP_indirE): Handle intel syntax. + (OP_E): Handle intel syntax. + (OP_I): Handle intel syntax. + (OP_sI): Handle intel syntax. + (OP_OFF): Handle intel syntax. + +1999-01-27 Doug Evans + + * fr30-opc.h, fr30-opc.c: Rebuild. + * i960c-opc.h, i960c-opc.c: Rebuild. + * m32r-opc.c: Rebuild. + +Tue Jan 19 18:01:54 1999 David Taylor + + * hppa-dis.c: revert HP merge changes until HP gives us + an updated file. + +1999-01-19 Nick Clifton + + * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative + offsets as well as symbloic address. + +Tue Jan 19 10:51:01 1999 David Taylor + + * hppa-dis.c: fix comments and some indentation. + +1999-01-12 Doug Evans + + * fr30-opc.c, i960c-opc.c: Regenerate. + +1999-01-11 Doug Evans + + * fr30-opc.c: Regenerate. + +1999-01-06 Doug Evans + + * m32r-dis.c: Regenerate. + +1999-01-05 Doug Evans + + * fr30-asm.c, fr30-dis.c, fr30-opc.h, fr30-opc.c: Regenerate. + * i960c-asm.c, i960c-dis.c, i960c-opc.h, i960c-opc.c: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. + +1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) + + * configure.in: Require autoconf 2.12.1 or higher. + +1998-12-30 Gavin Romig-Koch + + * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. + +Wed Dec 16 16:17:49 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + +1998-12-16 Gavin Romig-Koch + + * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. + +1998-12-15 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +1998-12-14 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 10 18:39:46 1998 Dave Brolley + + * fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 10 12:49:24 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Tue Dec 8 13:56:18 1998 David Taylor + + * dis-buf.c (generic_strcat_address): reformat to GNU coding + conventions. change sprintf call to an sprintf_vma call. + +Tue Dec 8 13:12:44 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Tue Dec 8 10:50:46 1998 David Taylor + + The following changes were made by + Elena Zannoni , + David Taylor , and + Edith Epstein as part of a project to + merge in changes by HP; HP did not create ChangeLog entries. + + * dis-buf.c (generic_strcat_address): new function. + + * hppa-dis.c: Changes to improve hppa disassembly. + Changed formatting in : reg_names, fp_reg_names,control_reg, + New variables : sign_extension_names, deposit_names, conversion_names + float_test_names, compare_cond_names_double, add_cond_names_double, + logical_cond_names_double, unit_cond_names_double, + branch_push_pop_names, saturation_names, shift_names, mix_names, + New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG + Move some definitions to libhppa.h: GET_FIELD, GET_BIT + (fput_const): renamed as fput_hex_const + (print_insn_hppa): + - use the macros fputs_filtered and + fput_decimal_const whenever possible; calls to sign_extend require + 2 params -- add a missing second param of 0. + - Some new code ifdefed for LOCAL_ONLY, all related to figuring out + architecture version number of current machine. HP folks are + trying to handle situation where the target program was compiled + for PA 1.x (32-bit), but is running on a PA 2.0 machine and + visa versa. + - added new cases : 'g', 'B', 'm' + - added cases specifically for PA 2.0 + - changed the following cases : '"', 'n', 'N', 'p', 'Z', + - calls to fput_const become calls to fput_hex_const + +1998-12-07 James E Wilson + + * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. + (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. + (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. + * Makefile.in: Rebuilt. + * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, + i960-dis.c to ta. + * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. + +Mon Dec 7 14:33:44 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Sun Dec 6 14:06:48 1998 Ian Lance Taylor + + * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. + + * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. + From Saitoh Masanobu . + +Fri Dec 4 17:45:51 1998 Doug Evans + + * fr30-opc.c: Regenerate. + +Fri Dec 4 17:08:08 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 3 14:26:20 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +Thu Dec 3 00:09:17 1998 Doug Evans + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. + +1998-11-30 Doug Evans + + * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> + CGEN_INSN_BASE_VALUE. + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. + * fr30-opc.c, fr30-opc.h, fr30-asm.c, fr30-dis.c: Regenerate. + +Thu Nov 26 11:26:32 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Regenerated. + +Tue Nov 24 11:20:54 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c: Regenerated. + +Mon Nov 23 18:28:48 1998 Dave Brolley + + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. + +1998-11-20 Doug Evans + + * fr30-opc.c: Regenerated. + +Thu Nov 19 16:02:46 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 19 07:54:15 1998 Doug Evans + + * mips-opc.c (sync.p,sync.l): Swap insn values. + +1998-11-19 Doug Evans + + * fr30-opc.c: Regenerate. + +Wed Nov 18 21:36:37 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + +1998-11-18 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Rebuild. + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Rebuild. + +Wed Nov 18 11:30:04 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + +Mon Nov 16 19:21:48 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Thu Nov 12 19:24:18 1998 Dave Brolley + + * po/opcodes.pot: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +Tue Nov 10 15:26:27 1998 Nick Clifton + + * disassemble.c (disassembler): Add support for FR30 target. + +Tue Nov 10 11:00:04 1998 Doug Evans + + * m32r-dis.c, m32r-opc.c, m32r-opc.h: Rebuild. + * fr30-dis.c, fr30-opc.c, fr30-opc.h: Rebuild. + +Mon Nov 9 18:22:55 1998 Dave Brolley + + * po/opcodes.pot: Regenerate. + * po/POTFILES.in: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + +Fri Nov 6 17:21:38 1998 Doug Evans + + * m32r-asm.c: Regenerate. + +Wed Nov 4 18:46:47 1998 Dave Brolley + + * configure.in: Added case for bfd_fr30_arch. + * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. + (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. + (CLEANFILES): Added stamp-fr30. + (FR30_DEPS): Added. + * fr30-asm.c: New file. + * fr30-dis.c: New file. + * fr30-opc.c: New file. + * fr30-opc.h: New file. + * po/POTFILES.in: Regenerated + * po/opcodes.pot: Regenerated + +Mon Nov 2 15:05:33 1998 Geoffrey Noer + + * configure.in: detect cygwin* instead of cygwin32* + * configure: regenerate + +Tue Oct 27 08:58:37 1998 Gavin Romig-Koch + + * mips-opc.c (IS_M): Added. + +Mon Oct 19 13:03:19 1998 Doug Evans + + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. + +Fri Oct 9 14:01:56 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c: Regenerate. + +Sun Oct 4 21:01:44 1998 Alan Modra + + * i386-dis.c (OP_3DNowSuffix): New static function. + (OPSUF): Define. + (GRP14): Define. + (dis386_twobyte): Add GRP14, femms, and 3DNow entries. + (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. + (insn_codep): New static variable. + (print_insn_x86): Init insn_codep after prefixes. + (grps): Add GRP14 entries for prefetch, prefetchw. + (OP_REG): Reformat. + + From Jeff B Epler + * i386-dis.c (Suffix3DNow): New table. + +Wed Sep 30 10:17:50 1998 Nick Clifton + + * d10v-opc.c: Treat TRAP as if it were a branch type instruction. + +Mon Sep 28 14:35:43 1998 Martin M. Hunt + + * d10v-dis.c (print_operand): If num is nonzero, then + add OPERAND_ACC1, not OPERAND_ACC0. + +Thu Sep 24 09:20:03 1998 Nick Clifton + + * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP + insns. + +Tue Sep 22 17:55:14 1998 Nick Clifton + + * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit + class. + +Tue Sep 15 15:14:45 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c: Add bbpc,bbpsw support. + +1998-09-09 Michael Meissner + + * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move + to/from SPRs. + +Fri Sep 4 19:42:59 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf + object files. + (print_insn_little_arm): Detect Thumb symbols in elf object + files. + +Sat Aug 29 22:24:09 1998 Richard Henderson + + * alpha-dis.c (print_insn_alpha): Use the machine type to + decide which PALcode set to include. + +Sun Aug 23 02:16:18 1998 Richard Henderson + + * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. + +Fri Aug 21 16:07:52 1998 Nick Clifton + + * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, + MSUB and MSUBS instructions. + +Thu Aug 13 16:23:04 1998 Ian Lance Taylor + + * ppc-opc.c (powerpc_operands): Omit parens around additions in + operand name macros. + +Wed Aug 12 14:00:38 1998 Ian Lance Taylor + + From Peter Jeremy : + * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, + +, -, and d for ColdFire. + + From Peter Thiemann : + * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. + (extract_mbe): Likewise. + +Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. + + * m10300-opc.c: First cut at UDF instructions. + +Mon Aug 10 14:08:22 1998 Doug Evans + + * m32r-opc.c: Regenerate (remove semantic descriptions). + +Mon Aug 10 12:51:12 1998 Catherine Moore + + * arm-dis.c (print_insn_big_arm): Fix indentation. + (print_insn_little_arm): Likewise. + +Sun Aug 9 20:17:28 1998 Catherine Moore + + * arm-dis.c (print_insn_big_arm): Check for thumb symbol + attributes. + (print_insn_little_arm): Likewise. + +Mon Aug 3 12:43:16 1998 Doug Evans + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen-asm.c (all fns): New first arg of opcode table descriptor. + (cgen_asm_init): Delete. + (cgen_set_parse_operand_fn): New function. + * cgen-dis.c (all fns): New first arg of opcode table descriptor. + (cgen_dis_init): Delete. + * cgen-opc.c (all fns): New first arg of opcode table descriptor. + (cgen_current_{opcode_table_mach,endian}): Delete. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + +Thu Jul 30 21:41:10 1998 Frank Ch. Eigler + + * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some + instructions. + +Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Add entries for "no_match_operands" field in + the opcode table. + +Fri Jul 24 11:41:37 1998 Doug Evans + + * m32r-asm.c, m32r-opc.c: Regenerate (-Wall cleanups). + +Tue Jul 21 13:41:07 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Mon Jul 13 14:53:59 1998 Alan Modra + + * i386-dis.c (ckprefix): Handle fwait specially only when it isn't + the first prefix. + (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather + than `fnstsw %eax'. + (OP_J): Remove unnecessary subtraction when 16-bit displacement + will be masked later. + +Thu Jul 2 17:11:27 1998 Doug Evans + + * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. + +Wed Jul 1 16:11:16 1998 Doug Evans + + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. + +Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-dis.c: Only recognize instructions from the currently + selected machine. + * m10300-opc.c: Add field indicating the particular variant of + the mn10300 each instruction is available on. + +Fri Jun 26 12:04:21 1998 Ian Lance Taylor + + * configure.in: For bfd_vax_arch, build vax-dis.lo. + * Makefile.am: Rebuild dependencies. + (CFILES): Add vax-dis.c. + (ALL_MACHINES): Add vax-dis.lo. + * aclocal.m4: Rebuild with current libtool. + * configure, Makefile.in: Rebuild. + +Fri Jun 26 12:03:20 1998 Klaus Kaempf + + * vax-dis.c: New file, from work by Pauline Middelink + . + * disassemble.c (ARCH_vax): Define if ARCH_all. + (disassembler): Add case for ARCH_vax. + * makefile.vms: Support compilation on vms/vax. + +Tue Jun 23 19:42:18 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities + related to sign extension and the size of ints. + +Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Support one operand "asr", "lsr" and "asl" + instructions. Support (sp) addressing mode by expanding it into + (0,sp). + +Sat Jun 20 14:46:20 1998 Frank Ch. Eigler + + * mips-dis.c (_print_insn_mips): Fix argument interchange typo. + +Fri Jun 19 09:16:42 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. + +1998-06-18 Ulrich Drepper + + * i386-dis.c: Add support for fxsave, fxrstor, sysenter and + sysexit. + +Thu Jun 18 10:22:24 1998 John Metzler + + * mips-dis.c (print_insn_little_mips): Previously, instruction + printing references the symbol table to determine whether the + instruction resides in a block regular instructions or mips16 + instructions. However, when the disassembler gets used in other + environments where the symbol table is not present, we no longer + rely in the symbol table, rather, use the low bit of the + instructions address to guess. There should be no change for usage + of the disassembler in host based programs, gdb, objdump. + (print_insn_big_mips): ditto. + (print_insn_mips): ditto + +Wed Jun 17 21:19:01 1998 Mark Alexander + + * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. + +Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". + +Tue Jun 16 13:10:51 1998 Alan Modra + + * i386-dis.c (index16): Add '%' to register names. Use ',' + instead of '+'. + +Sat Jun 13 11:33:55 1998 Alan Modra + + * i386-dis.c: Don't print opcode suffix when we can figure out the + size (and gas can!) by register operands, or from the default + size. + (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' + macro to 'E'. + (dis386, dis386_twobyte, grps): Use new suffix macros. + (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be + consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse + order of cmps operands to agree with Intel docs. Correct operand + of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to + agree with Intel docs. + (print_insn_x86): Print orphan fwait before other prefixes. + Return correct byte count for orphan fwait with prefixes. Don't + print `bound' operands in reverse order. + (ckprefix): Stop accumulating prefixes if we get fwait. + (OP_DIR): Print `$' before Ap operands of ljmp, lcall. + +Fri Jun 12 13:40:38 1998 Tom Tromey + + * po/Make-in (all-yes): If maintainer mode, depend on .pot file. + ($(PACKAGE).pot): Unconditionally depend on POTFILES. + +Fri Jun 12 11:04:06 1998 Andreas Schwab + + Fix problems when bfd_vma is wider than long. + * i386-dis.c: Make op_address and start_pc unsigned. + (set_op): Make parameter unsigned. + (print_insn_x86): Cast to bfd_vma when passing a value to + print_address_func. + * ns32k-dis.c (CORE_ADDR): Don't define. + (print_insn_ns32k): Change type of addr to bfd_vma. Use + bfd_scan_vma to read back address. + (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma + to format it. + * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. + (NEXTULONG): New definition. + (print_insn_m68k): Avoid overflow when computing third argument of + print_insn_arg. + (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. + Use disp instead of val to store offset values. + (print_indexed): Use base_disp instead of word to store base + displacement, to avoid overflow. + * m10300-dis.c (disassemble): Cast value to long when computing + pc-relative address, to get correct sign extension. + +Wed Jun 10 15:58:37 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Tue Jun 9 14:27:57 1998 Nick Clifton + + * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as + 'mov rX, rY'. Patch courtesy of Tony Thompson + +Mon Jun 8 18:17:21 1998 Nick Clifton + + * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. + +Fri Jun 5 23:47:55 1998 Alan Modra + + * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* + functions to void. + (OP_DSreg): Rename from OP_DSSI. + (OP_ESreg): Rename from OP_ESDI. + (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. + (DSBX): Define. + (append_seg): Rename from append_prefix. + (ptr_reg): New function. + (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. + Add DSBX for xlat. + (PREFIX_ADDR): Rename from PREFIX_ADR. + (float_reg): Add non-broken opcodes for people who don't want + UNIXWARE_COMPAT. + +Fri Jun 5 19:15:04 1998 Andreas Schwab + + * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on + 68000/68008/68010. + +Wed Jun 3 18:56:22 1998 H.J. Lu + + * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". + +Tue Jun 2 15:06:46 1998 Geoff Keating + + * ppc-opc.c (powerpc_macros): Support shifts and rotates of size + 0; produce error message for shifts of size 32 (or 64 for 64-bit + shifts), because the hardware doesn't support them. + +Wed May 27 15:29:13 1998 Nick Clifton + + * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, + LONG_2, LONG_2b formats to use this new operand. + +Tue May 26 20:47:48 1998 Stan Cox + + * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. + +Tue May 26 20:45:33 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): big endian instruction / little + endian data support. + +Tue May 26 16:14:39 1998 Nick Clifton + + * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 + and SHORT_B3b formats to use Rb instead of Ra. + + Add FLAG_MUL16 to MUL2XH opcode. + + Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension + to existing 1.1.1 parallelisation prohibition procedure. + +Fri May 22 16:00:00 1998 Doug Evans + + * m32r-asm.c, m32r-dis.c: Regenerate. + +Tue May 19 17:36:08 1998 Ian Lance Taylor + + * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly + with a shift count of 0. + +Fri May 15 14:58:31 1998 Doug Evans + + * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): New function. + +Wed May 13 17:03:59 1998 Doug Evans + + * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). + +Wed May 13 14:34:31 1998 Mark Alexander + + * sparc-dis.c (print_insn_sparc): Always fetch instructions + as big-endian on SPARClite. + +Tue May 12 11:46:31 1998 Richard Henderson + + * d30v-opc.c (pre_defined_register): Remove alias for r0. + +Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) + + * po/Make-in (install-info): New target. + +Thu May 7 17:15:59 1998 Ian Lance Taylor + + * configure.in (WIN32LIBADD): Add -lintl on cygwin32. + * configure: Rebuild. + +Thu May 7 12:49:46 1998 Frank Ch. Eigler + + * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand + variety of ISA2 instructions to set bottom ten bits of trap code. + +Thu May 7 11:54:25 1998 Ian Lance Taylor + + * Makefile.am (config.status): Add explicit target so that + config.status depends upon bfd/configure.in. + * Makefile.in: Rebuild. + +Thu May 7 09:33:02 1998 Frank Ch. Eigler + + * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 + instructions to set bottom ten bits of break code. + * mips-dis.c (print_insn_arg): Implement 'q' operand format used + for above optional argument. + +Wed May 6 15:30:06 1998 Klaus Kaempf + + * makefile.vms: Run dec c with /nodebug. + +Mon May 4 10:19:57 1998 Tom Tromey + + * Makefile.in: Rebuilt. + * Makefile.am: Regenerated dependencies with mkdep. + + * opintl.h (_): Define as dgettext. + +Tue Apr 28 14:12:12 1998 Nick Clifton + + * cgen-asm.c: Internationalised. + * m32r-asm.c: Internationalised. + * m32r-dis.c: Internationalised. + * m32r-opc.c: Internationalised. + + * aclocal.m4: Regenerated. + * configure: Regenerated. + * Makefile.am (POTFILES): Remove inclusion of BFD_H. + * Makefile.in: Rebuild. + * po/POTFILES.in: Rebuilt using rule in Makefile.in. + * po/opcodes.pot: Rebuilt after changing POTFILES.in. + +Tue Apr 28 13:13:13 1998 Ian Lance Taylor + + * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT + after AC_PROG_CC. + * aclocal.m4, configure: Rebuild with current tools. + +Mon Apr 27 14:31:00 1998 Nick Clifton + + * opintl.h: New file - contains internationalisation macros used + by source files in this directory. + * po/: New subdirectory - contains internationalisation files. + * po/Make-in: New file - Makefile constructor. + * po/POTFILES.in: New file - list of files in opcodes directory + that should be scan for internationalisation macros. + * po/opcodes.pot: New file - list of internationisation strings + found in files mentioned in po/POTFILES.in. + * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS + entry. Add intl directory to include paths. + * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, + HAVE_STRCPY, HAVE_LC_MESSAGES + * configure.in: Add rule to build Makefile in po subdirectory. + * Makefile.in: Rebuilt. + * aclocal.m4: Rebuilt. + * config.in: Rebuilt. + * configure: Rebuilt. + * alpha-opc.c: Internationalised. + * arc-dis.c: Internationalised. + * arc-opc.c: Internationalised. + * arm-dis.c: Internationalised. + * cgen-asm.c: Internationalised. + * d30v-dis.c: Internationalised. + * dis-buf.c: Internationalised. + * h8300-dis.c: Internationalised. + * h8500-dis.c: Internationalised. + * i386-dis.c: Internationalised. + * m10200-dis.c: Internationalised. + * m10300-dis.c: Internationalised. + * m68k-dis.c: Internationalised. + * m88k-dis.c: Internationalised. + * mips-dis.c: Internationalised. + * ns32k-dis.c: Internationalised. + * opintl.h: Internationalised. + * ppc-opc.c: Internationalised. + * sparc-dis.c: Internationalised. + * v850-dis.c: Internationalised. + * v850-opc.c: Internationalised. + +Mon Apr 27 10:33:56 1998 Doug Evans + + * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. + (asm_hash_table_entries): New variable. + (cgen_asm_init): Free asm_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_asm_hash_table): Use them. Hash macro insns as well. + (cgen_asm_lookup_insn): Update. + * cgen-dis.c (cgen_current_opcode_table): Renamed from ..._data. + (dis_hash_table_entries): New variable. + (cgen_dis_init): Free dis_hash_table_entries. + (hash_insn_array,hash_insn_list): New functions. + (build_dis_hash_table): Use them. Hash macro insns as well. + (cgen_dis_lookup_insn): Update. + * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. + (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. + (cgen_macro_insn_count): New function. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Fri Apr 24 16:07:57 1998 Alan Modra + + * i386-dis.c (OP_DSSI): Print segment override. + +Mon Apr 13 16:59:39 1998 Nick Clifton + + * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' + operator. + +Mon Apr 13 16:50:27 1998 Ian Lance Taylor + + * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. + (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. + * configure.in: Define and substitute WIN32LDFLAGS and + WIN32LIBADD. + * aclocal.m4: Rebuild with new libtool. + * configure, Makefile.in: Rebuild. + +Fri Apr 10 18:14:31 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Sun Apr 5 16:04:39 1998 H.J. Lu + + * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists + before trying to copy it. + * Makefile.in: Rebuild. + +Thu Apr 2 17:25:49 1998 Nick Clifton + + * m32r-opc.c: Use signed immediate values for CMPUI instruction. + +Wed Apr 1 16:20:27 1998 Ian Dall + + * ns32k-dis.c (bit_extract_simple): New function to extract bits + from an arbitrary valid buffer instead of fetching them on demand + using fetch_data(). + (invalid_float): use bit_extract_simple() instead of bit_extract(). + +Tue Mar 31 11:09:08 1998 Ian Lance Taylor + + From H.J. Lu : + * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew + to Ev for both. + +Mon Mar 30 17:32:03 1998 Ian Lance Taylor + + * Branched binutils 2.9. + +Mon Mar 30 15:18:00 1998 Ken Raeburn + + * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when + disassembling last 4 bytes of a section. + +Fri Mar 27 18:08:13 1998 Ian Lance Taylor + + Fix some gcc -Wall warnings: + * arc-dis.c (print_insn): Add casts to avoid warnings. + * cgen-opc.c (cgen_keyword_lookup_name): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * m10200-dis.c (disassemble): Likewise. + * m10300-dis.c (disassemble): Likewise. + * ns32k-dis.c (print_insn_ns32k): Likewise. + * ppc-opc.c (insert_ral, insert_ram): Likewise. + * cgen-dis.c (build_dis_hash_table): Remove used local variables. + * cgen-opc.c (cgen_keyword_search_next): Likewise. + * d10v-dis.c (dis_long, dis_2_short): Likewise. + * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. + * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. + * tic80-dis.c (print_one_instruction): Likewise. + * w65-dis.c (print_operand): Likewise. + * z8k-dis.c (fetch_data): Likewise. + * a29k-dis.c: Add return type for find_byte_func_type. + * arc-opc.c: Include . Remove declarations of + insert_multshift and extract_multshift. + * d30v-dis.c (lookup_opcode): Parenthesize assignments in + conditionals. + (extract_value): Fully parenthesize expression. + * h8500-dis.c (print_insn_h8500): Initialize local variables. + * h8500-opc.h (h8500_table): Fully bracket initializer. + * w65-opc.h (optable): Likewise. + * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. + * i386-dis.c (OP_E): Initialize local variables. + * m10200-dis.c (print_insn_mn10200): Likewise. + * mips-dis.c (print_insn_mips16): Likewise. + * sh-dis.c (print_insn_shx): Likewise. + * v850-dis.c (print_insn_v850): Likewise. + * ns32k-dis.c (print_insn_arg): Declare. + (get_displacement, invalid_float): Declare. + (list_search, sign_extend, flip_bytes): Declare return type. + (get_displacement): Likewise. + (print_insn_arg): Likewise. Make d int. Fix sprintf format + string. + (print_insn_ns32k): Make i unsigned. + (invalid_float): Make static. Declare type of val. + * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen + on each for iteration. + * tic30-dis.c (get_indirect_operand): Likewise. + * z8k-dis.c (print_insn_z8001): Declare return type. + (print_insn_z8002): Likewise. + (unparse_instr): Fix sprintf format strings. + +Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) + + * mips-opc.c: Add "sync.l" and "sync.p". + +Wed Mar 25 14:32:48 1998 Andreas Schwab + + * m68k-dis.c (print_insn_m68k): Use info->mach to select the + default m68k variant to recognize. + + * i960-dis.c (pinsn): Change type of first argument to bfd_vma. + (ctrl, cobr, mem, ea): Likewise. + (print_addr): Likewise. Remove cast. + (ea): Cast argument of print_addr to bfd_vma. + + * cgen-asm.c (cgen_parse_signed_integer): Fix type of local + variable value. + (cgen_parse_unsigned_integer): Likewise. + (cgen_parse_address): Likewise. + +Wed Mar 25 14:31:31 1998 Ian Lance Taylor + + * i960-dis.c (ctrl): Add full braces to structure initialization. + (cobr, mem, reg): Likewise. + (ea): Correct parenthesization in expression. + + * cgen-asm.c: Include . + (build_asm_hash_table): Remove unused local variable i. + (cgen_parse_keyword): Add casts to avoid warnings. + + * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF + symbol. Fix indentation. + (print_insn_little_arm): Likewise. + +Fri Mar 20 18:55:18 1998 Ian Lance Taylor + + * configure.in: Use AM_DISABLE_SHARED. + * aclocal.m4, configure: Rebuild with libtool 1.2. + +Thu Mar 19 15:46:53 1998 Nick Clifton + + These patches are courtesy of Jonathan Walton and Tony Thompson + (athompso@cambridge.arm.com). + + * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC + relative addresses. + + * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with + both the offset and the label closest to the destination. + +Sat Mar 14 23:47:14 1998 Doug Evans + + * m32r-opc.h: Regenerate. + +Wed Mar 4 12:08:14 1998 Doug Evans + + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Sat Feb 28 16:02:34 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not + assume that info->symbols is non-empty. + +Sat Feb 28 12:19:05 1998 Richard Henderson + + * alpha-opc.c (cvtqs) There is no such thing. + (cvttq): Missing most of the /*d variants. + +Thu Feb 26 15:53:09 1998 Michael Meissner + + * d30v-opc.c (d30v_opcode_table): Indicate which instructions are + delayed branches or jumps. + +Tue Feb 24 10:46:44 1998 Doug Evans + + * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed + to *info->symbols. + * mips-dis.c (print_insn_{big,little}_mips): Likewise. + * tic30-dis.c (print_branch): Likewise. + +Tue Feb 24 11:06:18 1998 Nick Clifton + + * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove + saved_symbol code as it is no longer needed. + +Mon Feb 23 13:16:17 1998 Doug Evans + + * cgen-asm.c: Include symcat.h. + * cgen-dis.c, cgen-opc.c: Ditto. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. + +Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. + +Thu Feb 19 16:51:13 1998 Doug Evans + + * m32r-opc.[ch]: Regenerate. + +Tue Feb 17 17:14:50 1998 Doug Evans + + * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max + arguments. Don't perform validation here. + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Regenerate. + +Fri Feb 13 14:26:06 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Fri Feb 13 14:53:02 1998 Ian Lance Taylor + + * Makefile.am (AUTOMAKE_OPTIONS): Define. + * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. + +Fri Feb 13 10:21:09 1998 Mark Alexander + + * m10300-dis.c (print_insn_mn10300): Recognize break instruction. + +Fri Feb 13 13:12:14 1998 Ian Lance Taylor + + * configure.in: Get the version number from BFD. + * configure: Rebuild. + + From H.J. Lu : + * Makefile.am (libopcodes_la_LDFLAGS): Define. + * Makefile.in: Rebuild. + +Fri Feb 13 09:50:32 1998 Nick Clifton + + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + +Thu Feb 12 11:01:40 1998 Doug Evans + + * m32r-opc.c: Regenerate. + +Thu Feb 12 03:41:00 1998 J"orn Rennecke + + Fix rac to accept only a0: + * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): + Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. + Introduce OPERAND_GPR. + * d10v-dis.c (print_operand): Likewise. + +Wed Feb 11 18:58:34 1998 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. + (cgen_hw_lookup): Make result const. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Sat Feb 7 15:30:27 1998 Ian Lance Taylor + + * configure, aclocal.m4: Rebuild with new libtool. + +Thu Feb 5 17:56:10 1998 Michael Meissner + + * d30v-opc.c (repeat{,i} instructions): Repeat/repeati + instructions use a PC relative branch, not absolute. + +Wed Feb 4 19:17:37 1998 Ian Lance Taylor + + * configure.in: Set libtool_enable_shared rather than + libtool_shared. Remove diversion hack. + * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. + +Tue Feb 3 17:19:40 1998 Doug Evans + + * cgen-opc.c (cgen_set_cpu): Initialize hardware table. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. + +Mon Feb 2 19:22:15 1998 Steve Haworth + + * tic30-dis.c: New file. + * disassemble.c (disassembler): Add bfd_arch_tic30 case. + * configure.in: Handle bfd_tic30_arch. + * Makefile.am: Rebuild dependencies. + (CFILES): Add tic30-dis.c + (ALL_MACHINES): Add tic30-dis.lo. + * configure, Makefile.in: Rebuild. + +Thu Jan 29 13:02:56 1998 Doug Evans + + * m32r-opc.h (HAVE_CPU_M32R): Define. + +Wed Jan 28 09:55:03 1998 Nick Clifton + + * v850-opc.c (insertion routines): If both alignment and size is + wrong then report this. + +Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) + + * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. + Only recognize instructions for the current target_processor. + +Thu Jan 22 16:20:17 1998 Fred Fish + + * d10v-dis.c (PC_MASK): Correct value. + (print_operand): If there's a reloc, don't calculate the + address because they could be in different sections. + +Fri Jan 16 15:29:11 1998 Jim Blandy + + * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" + instruction after the 4650's "mul" instruction; nobody's using the + 4010 these days. If object files someday indicate which processor + variant they're intended for, we can do a better job at this. + +Mon Jan 12 14:43:54 1998 Doug Evans + + * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MNEMONIC. + (cgen_parse_keyword): Rewrite. + * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using + table provided entry size. Use CGEN_INSN_MASK_BITSIZE. + * cgen-opc.c: Clean up pass over `struct foo' usage. + (cgen_keyword_lookup_value): Handle "" entry. + (cgen_keyword_add): Likewise. + +For older changes see ChangeLog-9297 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/external/gpl3/gdb/dist/opcodes/MAINTAINERS b/external/gpl3/gdb/dist/opcodes/MAINTAINERS new file mode 100644 index 000000000000..d59a3bd7f889 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/external/gpl3/gdb/dist/opcodes/Makefile.am b/external/gpl3/gdb/dist/opcodes/Makefile.am new file mode 100644 index 000000000000..668085cb5333 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/Makefile.am @@ -0,0 +1,538 @@ +## Process this file with automake to generate Makefile.in + +AUTOMAKE_OPTIONS = 1.11 foreign no-dist +ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd + +# Build '.' first so all generated files exist. +SUBDIRS = . po + +INCDIR = $(srcdir)/../include +BFDDIR = $(srcdir)/../bfd + +WARN_CFLAGS = @WARN_CFLAGS@ +NO_WERROR = @NO_WERROR@ +AM_CFLAGS = $(WARN_CFLAGS) + +COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CFLAGS_FOR_BUILD) +LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) \ + $(LDFLAGS_FOR_BUILD) -o $@ + +libopcodes_la_LDFLAGS = +if INSTALL_LIBBFD +bfdlibdir = @bfdlibdir@ +bfdincludedir = @bfdincludedir@ +bfdlib_LTLIBRARIES = libopcodes.la +bfdinclude_DATA = $(INCDIR)/dis-asm.h +else +# Empty these so that the respective installation directories will not be created. +bfdlibdir = +bfdincludedir = +rpath_bfdlibdir = @bfdlibdir@ +noinst_LTLIBRARIES = libopcodes.la +libopcodes_la_LDFLAGS += -rpath $(rpath_bfdlibdir) +endif + +# This is where bfd.h lives. +BFD_H = ../bfd/bfd.h + +BUILD_LIBS = @BUILD_LIBS@ +BUILD_LIB_DEPS = @BUILD_LIB_DEPS@ + +# Header files. +HFILES = \ + fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ + h8500-opc.h \ + i386-init.h \ + i386-opc.h \ + i386-tbl.h \ + ia64-asmtab.h \ + ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ + lm32-desc.h \ + lm32-opc.h \ + m32c-desc.h m32c-opc.h \ + m32r-desc.h m32r-opc.h \ + mcore-opc.h \ + mep-desc.h mep-opc.h \ + microblaze-opc.h \ + mt-desc.h mt-opc.h \ + openrisc-desc.h openrisc-opc.h \ + score-opc.h \ + sh-opc.h \ + sh64-opc.h \ + sysdep.h \ + w65-opc.h \ + xc16x-desc.h xc16x-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ + z8k-opc.h + +# C source files that correspond to .o's ending up in libopcodes +# for all machines. +TARGET_LIBOPCODES_CFILES = \ + alpha-dis.c \ + alpha-opc.c \ + arc-dis.c \ + arc-ext.c \ + arc-opc.c \ + arm-dis.c \ + avr-dis.c \ + bfin-dis.c \ + cgen-asm.c \ + cgen-bitset.c \ + cgen-dis.c \ + cgen-opc.c \ + cr16-dis.c \ + cr16-opc.c \ + cris-dis.c \ + cris-opc.c \ + crx-dis.c \ + crx-opc.c \ + d10v-dis.c \ + d10v-opc.c \ + d30v-dis.c \ + d30v-opc.c \ + dlx-dis.c \ + fr30-asm.c \ + fr30-desc.c \ + fr30-dis.c \ + fr30-ibld.c \ + fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ + h8300-dis.c \ + h8500-dis.c \ + hppa-dis.c \ + i370-dis.c \ + i370-opc.c \ + i386-dis.c \ + i386-opc.c \ + i860-dis.c \ + i960-dis.c \ + ia64-dis.c \ + ia64-opc.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ + lm32-asm.c \ + lm32-desc.c \ + lm32-dis.c \ + lm32-ibld.c \ + lm32-opc.c \ + lm32-opinst.c \ + m10200-dis.c \ + m10200-opc.c \ + m10300-dis.c \ + m10300-opc.c \ + m32c-asm.c \ + m32c-desc.c \ + m32c-dis.c \ + m32c-ibld.c \ + m32c-opc.c \ + m32r-asm.c \ + m32r-desc.c \ + m32r-dis.c \ + m32r-ibld.c \ + m32r-opc.c \ + m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ + m68k-dis.c \ + m68k-opc.c \ + m88k-dis.c \ + mcore-dis.c \ + mep-asm.c \ + mep-desc.c \ + mep-dis.c \ + mep-ibld.c \ + mep-opc.c \ + microblaze-dis.c \ + mips-dis.c \ + mips-opc.c \ + mips16-opc.c \ + mmix-dis.c \ + mmix-opc.c \ + moxie-dis.c \ + moxie-opc.c \ + msp430-dis.c \ + mt-asm.c \ + mt-desc.c \ + mt-dis.c \ + mt-ibld.c \ + mt-opc.c \ + ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + or32-dis.c \ + or32-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ + pj-dis.c \ + pj-opc.c \ + ppc-dis.c \ + ppc-opc.c \ + rx-decode.c \ + rx-dis.c \ + s390-dis.c \ + s390-opc.c \ + score-dis.c \ + score7-dis.c \ + sh-dis.c \ + sh64-dis.c \ + sh64-opc.c \ + sparc-dis.c \ + sparc-opc.c \ + spu-dis.c \ + spu-opc.c \ + tic30-dis.c \ + tic4x-dis.c \ + tic54x-dis.c \ + tic54x-opc.c \ + tic6x-dis.c \ + tic80-dis.c \ + tic80-opc.c \ + v850-dis.c \ + v850-opc.c \ + vax-dis.c \ + w65-dis.c \ + xc16x-asm.c \ + xc16x-desc.c \ + xc16x-dis.c \ + xc16x-ibld.c \ + xc16x-opc.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ + xtensa-dis.c \ + z80-dis.c \ + z8k-dis.c + +# C source files that correspond to .o's ending up in libopcodes. +LIBOPCODES_CFILES = \ + $(TARGET_LIBOPCODES_CFILES) \ + dis-buf.c \ + dis-init.c \ + disassemble.c + +# C source files that correspond to .o's. +CFILES = \ + $(LIBOPCODES_CFILES) \ + i386-gen.c \ + ia64-asmtab.c \ + ia64-gen.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + s390-mkopc.c \ + z8kgen.c + +ALL_MACHINES = $(TARGET_LIBOPCODES_CFILES:.c=.lo) + +OFILES = @BFD_MACHINES@ + +# We should reconfigure whenever bfd/configure.in changes, because +# that's where the version number in Makefile comes from. +CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in + +AM_CPPFLAGS = -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ @INCINTL@ + +disassemble.lo: disassemble.c +if am__fastdepCC + $(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $(srcdir)/disassemble.c + mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo +else +if AMDEP + source='disassemble.c' object='$@' libtool=yes @AMDEPBACKSLASH@ + DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +endif + $(LTCOMPILE) -c -o $@ @archdefs@ $(srcdir)/disassemble.c +endif + +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c +# It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. +# Unfortunately this causes libtool to add -L$(libdir), referring to the +# planned install directory of libbfd. This can cause us to pick up an +# old version of libbfd, or to pick up libbfd for the wrong architecture +# if host != build. So for building with shared libraries we use a +# hardcoded path to libbfd.so instead of relying on the entries in libbfd.la. +libopcodes_la_DEPENDENCIES = $(OFILES) @SHARED_DEPENDENCIES@ +libopcodes_la_LIBADD = $(OFILES) @SHARED_LIBADD@ +libopcodes_la_LDFLAGS += -release `cat ../bfd/libtool-soversion` @SHARED_LDFLAGS@ +# Allow dependency tracking to work on all the source files. +EXTRA_libopcodes_la_SOURCES = $(LIBOPCODES_CFILES) + +# libtool will build .libs/libopcodes.a. We create libopcodes.a in +# the build directory so that we don't have to convert all the +# programs that use libopcodes.a simultaneously. This is a hack which +# should be removed if everything else starts using libtool. FIXME. + +noinst_LIBRARIES = libopcodes.a +libopcodes_a_SOURCES = + +stamp-lib: libopcodes.la + libtooldir=`$(LIBTOOL) --config | sed -n -e 's/^objdir=//p'`; \ + if [ -f $$libtooldir/libopcodes.a ]; then \ + cp $$libtooldir/libopcodes.a libopcodes.tmp; \ + $(RANLIB) libopcodes.tmp; \ + $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \ + else true; fi + touch stamp-lib + +libopcodes.a: stamp-lib ; @true + +POTFILES = $(HFILES) $(CFILES) +po/POTFILES.in: @MAINT@ Makefile + for f in $(POTFILES); do echo $$f; done | LC_ALL=C sort > tmp \ + && mv tmp $(srcdir)/po/POTFILES.in + +CLEANFILES = \ + stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ + stamp-m32c stamp-m32r stamp-mep stamp-mt \ + stamp-openrisc stamp-xc16x stamp-xstormy16 \ + libopcodes.a stamp-lib + + +CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu +CGEN = "`if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` -l ${cgendir}/guile.scm -s" +CGENFLAGS = -v + +CGENDEPS = \ + $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ + $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ + $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ + $(CGENDIR)/opc-opinst.scm \ + cgen-asm.in cgen-dis.in cgen-ibld.in + +CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 + +if CGEN_MAINT +FR30_DEPS = stamp-fr30 +FRV_DEPS = stamp-frv +IP2K_DEPS = stamp-ip2k +IQ2000_DEPS = stamp-iq2000 +LM32_DEPS = stamp-lm32 +M32C_DEPS = stamp-m32c +M32R_DEPS = stamp-m32r +MEP_DEPS = stamp-mep +MT_DEPS = stamp-mt +OPENRISC_DEPS = stamp-openrisc +XC16X_DEPS = stamp-xc16x +XSTORMY16_DEPS = stamp-xstormy16 +else +FR30_DEPS = +FRV_DEPS = +IP2K_DEPS = +IQ2000_DEPS = +LM32_DEPS = +M32C_DEPS = +M32R_DEPS = +MEP_DEPS = +MT_DEPS = +OPENRISC_DEPS = +XC16X_DEPS = +XSTORMY16_DEPS = +endif + +run-cgen: + $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ + "$(options)" "$(extrafiles)" + touch stamp-${prefix} +.PHONY: run-cgen + +# Maintainer utility rule to regenerate all cgen files. +run-cgen-all: + for c in $(CGEN_CPUS) ; \ + do \ + $(MAKE) stamp-$$c || exit 1 ; \ + done +.PHONY: run-cgen-all + +# For now, require developers to configure with --enable-cgen-maint. + +$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) + @true +stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ + archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= + +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= \ + archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= + +$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) + @true +stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ + archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= + +$(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) + @true +stamp-iq2000: $(CGENDEPS) $(srcdir)/../cpu/iq2000.cpu \ + $(srcdir)/../cpu/iq2000.opc $(srcdir)/../cpu/iq2000m.cpu \ + $(srcdir)/../cpu/iq10.cpu + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ + archfile=$(srcdir)/../cpu/iq2000.cpu \ + opcfile=$(srcdir)/../cpu/iq2000.opc extrafiles= + +$(srcdir)lm32-desc.h $(srcdir)/lm32-desc.c $(srcdir)/lm32-opc.h $(srcdir)/lm32-opc.c $(srcdir)/lm32-ibld.c $(srcdir)/lm32-opinst.c $(srcdir)/lm32-asm.c $(srcdir)/lm32-dis.c: $(LM32_DEPS) + @true +stamp-lm32: $(CGENDEPS) $(srcdir)/../cpu/lm32.cpu $(srcdir)/../cpu/lm32.opc + $(MAKE) run-cgen arch=lm32 prefix=lm32 options=opinst \ + archfile=$(srcdir)/../cpu/lm32.cpu \ + opcfile=$(srcdir)/../cpu/lm32.opc \ + extrafiles=opinst + +$(srcdir)/m32c-desc.h $(srcdir)/m32c-desc.c $(srcdir)/m32c-opc.h $(srcdir)/m32c-opc.c $(srcdir)/m32c-ibld.c $(srcdir)/m32c-asm.c $(srcdir)/m32c-dis.c: $(M32C_DEPS) +# @true +stamp-m32c: $(CGENDEPS) $(srcdir)/../cpu/m32c.cpu $(srcdir)/../cpu/m32c.opc + $(MAKE) run-cgen arch=m32c prefix=m32c options= \ + archfile=$(srcdir)/../cpu/m32c.cpu \ + opcfile=$(srcdir)/../cpu/m32c.opc extrafiles= + +$(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) + @true +stamp-m32r: $(CGENDEPS) $(srcdir)/../cpu/m32r.cpu $(srcdir)/../cpu/m32r.opc + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ + archfile=$(srcdir)/../cpu/m32r.cpu \ + opcfile=$(srcdir)/../cpu/m32r.opc extrafiles=opinst + +$(srcdir)/mep-desc.h $(srcdir)/mep-desc.c $(srcdir)/mep-opc.h $(srcdir)/mep-opc.c $(srcdir)/mep-ibld.c $(srcdir)/mep-asm.c $(srcdir)/mep-dis.c: $(MEP_DEPS) + @true +stamp-mep: $(CGENDEPS) $(CPUDIR)/mep.cpu $(CPUDIR)/mep-default.cpu $(CPUDIR)/mep-core.cpu $(CPUDIR)/mep-h1.cpu $(CPUDIR)/mep-ext-cop.cpu $(CPUDIR)/mep-sample-ucidsp.cpu $(CPUDIR)/mep-rhcop.cpu $(CPUDIR)/mep-fmax.cpu $(CPUDIR)/mep.opc + $(MAKE) run-cgen arch=mep prefix=mep options= \ + archfile=$(CPUDIR)/mep.cpu opcfile=$(CPUDIR)/mep.opc extrafiles= + +$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS) + @true +stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc + $(MAKE) run-cgen arch=mt prefix=mt options= \ + archfile=$(srcdir)/../cpu/mt.cpu \ + opcfile=$(srcdir)/../cpu/mt.opc extrafiles= + +$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) + @true +stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ + archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= + +$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS) + @true +stamp-xc16x: $(CGENDEPS) $(srcdir)/../cpu/xc16x.cpu $(srcdir)/../cpu/xc16x.opc + $(MAKE) run-cgen arch=xc16x prefix=xc16x options= \ + archfile=$(srcdir)/../cpu/xc16x.cpu \ + opcfile=$(srcdir)/../cpu/xc16x.opc \ + extrafiles= + +$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) + @true +stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \ + archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles= + +MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \ + s390-mkopc$(EXEEXT_FOR_BUILD) z8kgen$(EXEEXT_FOR_BUILD) \ + opc2c$(EXEEXT_FOR_BUILD) + +MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \ + $(srcdir)/ia64-asmtab.c s390-opc.tab $(srcdir)/z8k-opc.h \ + $(srcdir)/rx-decode.c + +i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS) + $(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS) + +i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/getopt.h $(INCDIR)/hashtab.h \ + $(INCDIR)/libiberty.h $(INCDIR)/opcode/i386.h $(INCDIR)/safe-ctype.h \ + config.h i386-opc.h sysdep.h + $(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c + +$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h + @echo $@ + +$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl + ./i386-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir) + +i386-opc.lo: $(srcdir)/i386-tbl.h + +ia64-gen$(EXEEXT_FOR_BUILD): ia64-gen.o $(BUILD_LIB_DEPS) + $(LINK_FOR_BUILD) ia64-gen.o $(BUILD_LIBS) + +ia64-gen.o: ia64-gen.c $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/getopt.h \ + $(INCDIR)/libiberty.h $(INCDIR)/opcode/ia64.h $(INCDIR)/safe-ctype.h \ + $(INCDIR)/symcat.h config.h ia64-opc-a.c ia64-opc-b.c \ + ia64-opc-d.c ia64-opc-f.c ia64-opc-i.c ia64-opc-m.c \ + ia64-opc-x.c ia64-opc.h sysdep.h + $(COMPILE_FOR_BUILD) -c $(srcdir)/ia64-gen.c + +# Use a helper variable for the dependencies to avoid 'make' issues +# with continuations in comments, as @MAINT@ can be expanded to '#'. +ia64_asmtab_deps = ia64-gen$(EXEEXT_FOR_BUILD) ia64-ic.tbl \ + ia64-raw.tbl ia64-waw.tbl ia64-war.tbl +$(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps) + ./ia64-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir) > $@ + +ia64-opc.lo: $(srcdir)/ia64-asmtab.c + +$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD) + ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c + +opc2c$(EXEEXT_FOR_BUILD): opc2c.o $(BUILD_LIBS_DEPS) + $(LINK_FOR_BUILD) opc2c.o $(BUILD_LIBS) + +opc2c.o: opc2c.c $(INCDIR)/libiberty.h + $(COMPILE_FOR_BUILD) -c $(srcdir)/opc2c.c + +s390-mkopc$(EXEEXT_FOR_BUILD): s390-mkopc.c + $(COMPILE_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c + +s390-opc.tab: s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.txt + ./s390-mkopc$(EXEEXT_FOR_BUILD) < $(srcdir)/s390-opc.txt > s390-opc.tab + +s390-opc.lo: s390-opc.tab + +z8kgen$(EXEEXT_FOR_BUILD): z8kgen.o $(BUILD_LIB_DEPS) + $(LINK_FOR_BUILD) z8kgen.o $(BUILD_LIBS) + +z8kgen.o: z8kgen.c + $(COMPILE_FOR_BUILD) -c $(srcdir)/z8kgen.c + +$(srcdir)/z8k-opc.h: @MAINT@ z8kgen$(EXEEXT_FOR_BUILD) + ./z8kgen$(EXEEXT_FOR_BUILD) -a > $@ + +z8k-dis.lo: $(srcdir)/z8k-opc.h + +sh-dis.lo: sh-dis.c +if am__fastdepCC + $(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $(srcdir)/sh-dis.c + mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo +else +if AMDEP + source='sh-dis.c' object='$@' libtool=yes @AMDEPBACKSLASH@ + DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +endif + $(LTCOMPILE) -c -o $@ @archdefs@ $(srcdir)/sh-dis.c +endif diff --git a/external/gpl3/gdb/dist/opcodes/Makefile.in b/external/gpl3/gdb/dist/opcodes/Makefile.in new file mode 100644 index 000000000000..8928b1bcce5a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/Makefile.in @@ -0,0 +1,1372 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, +# Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkglibexecdir = $(libexecdir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +@INSTALL_LIBBFD_FALSE@am__append_1 = -rpath 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is where bfd.h lives. +BFD_H = ../bfd/bfd.h + +# Header files. +HFILES = \ + fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ + h8500-opc.h \ + i386-init.h \ + i386-opc.h \ + i386-tbl.h \ + ia64-asmtab.h \ + ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ + lm32-desc.h \ + lm32-opc.h \ + m32c-desc.h m32c-opc.h \ + m32r-desc.h m32r-opc.h \ + mcore-opc.h \ + mep-desc.h mep-opc.h \ + microblaze-opc.h \ + mt-desc.h mt-opc.h \ + openrisc-desc.h openrisc-opc.h \ + score-opc.h \ + sh-opc.h \ + sh64-opc.h \ + sysdep.h \ + w65-opc.h \ + xc16x-desc.h xc16x-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ + z8k-opc.h + + +# C source files that correspond to .o's ending up in libopcodes +# for all machines. +TARGET_LIBOPCODES_CFILES = \ + alpha-dis.c \ + alpha-opc.c \ + arc-dis.c \ + arc-ext.c \ + arc-opc.c \ + arm-dis.c \ + avr-dis.c \ + bfin-dis.c \ + cgen-asm.c \ + cgen-bitset.c \ + cgen-dis.c \ + cgen-opc.c \ + cr16-dis.c \ + cr16-opc.c \ + cris-dis.c \ + cris-opc.c \ + crx-dis.c \ + crx-opc.c \ + d10v-dis.c \ + d10v-opc.c \ + d30v-dis.c \ + d30v-opc.c \ + dlx-dis.c \ + fr30-asm.c \ + fr30-desc.c \ + fr30-dis.c \ + fr30-ibld.c \ + fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ + h8300-dis.c \ + h8500-dis.c \ + hppa-dis.c \ + i370-dis.c \ + i370-opc.c \ + i386-dis.c \ + i386-opc.c \ + i860-dis.c \ + i960-dis.c \ + ia64-dis.c \ + ia64-opc.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ + lm32-asm.c \ + lm32-desc.c \ + lm32-dis.c \ + lm32-ibld.c \ + lm32-opc.c \ + lm32-opinst.c \ + m10200-dis.c \ + m10200-opc.c \ + m10300-dis.c \ + m10300-opc.c \ + m32c-asm.c \ + m32c-desc.c \ + m32c-dis.c \ + m32c-ibld.c \ + m32c-opc.c \ + m32r-asm.c \ + m32r-desc.c \ + m32r-dis.c \ + m32r-ibld.c \ + m32r-opc.c \ + m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ + m68k-dis.c \ + m68k-opc.c \ + m88k-dis.c \ + mcore-dis.c \ + mep-asm.c \ + mep-desc.c \ + mep-dis.c \ + mep-ibld.c \ + mep-opc.c \ + microblaze-dis.c \ + mips-dis.c \ + mips-opc.c \ + mips16-opc.c \ + mmix-dis.c \ + mmix-opc.c \ + moxie-dis.c \ + moxie-opc.c \ + msp430-dis.c \ + mt-asm.c \ + mt-desc.c \ + mt-dis.c \ + mt-ibld.c \ + mt-opc.c \ + ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + or32-dis.c \ + or32-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ + pj-dis.c \ + pj-opc.c \ + ppc-dis.c \ + ppc-opc.c \ + rx-decode.c \ + rx-dis.c \ + s390-dis.c \ + s390-opc.c \ + score-dis.c \ + score7-dis.c \ + sh-dis.c \ + sh64-dis.c \ + sh64-opc.c \ + sparc-dis.c \ + sparc-opc.c \ + spu-dis.c \ + spu-opc.c \ + tic30-dis.c \ + tic4x-dis.c \ + tic54x-dis.c \ + tic54x-opc.c \ + tic6x-dis.c \ + tic80-dis.c \ + tic80-opc.c \ + v850-dis.c \ + v850-opc.c \ + vax-dis.c \ + w65-dis.c \ + xc16x-asm.c \ + xc16x-desc.c \ + xc16x-dis.c \ + xc16x-ibld.c \ + xc16x-opc.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ + xtensa-dis.c \ + z80-dis.c \ + z8k-dis.c + + +# C source files that correspond to .o's ending up in libopcodes. +LIBOPCODES_CFILES = \ + $(TARGET_LIBOPCODES_CFILES) \ + dis-buf.c \ + dis-init.c \ + disassemble.c + + +# C source files that correspond to .o's. +CFILES = \ + $(LIBOPCODES_CFILES) \ + i386-gen.c \ + ia64-asmtab.c \ + ia64-gen.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + s390-mkopc.c \ + z8kgen.c + +ALL_MACHINES = $(TARGET_LIBOPCODES_CFILES:.c=.lo) +OFILES = @BFD_MACHINES@ + +# We should reconfigure whenever bfd/configure.in changes, because +# that's where the version number in Makefile comes from. +CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in +AM_CPPFLAGS = -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ @INCINTL@ +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c +# It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. +# Unfortunately this causes libtool to add -L$(libdir), referring to the +# planned install directory of libbfd. This can cause us to pick up an +# old version of libbfd, or to pick up libbfd for the wrong architecture +# if host != build. So for building with shared libraries we use a +# hardcoded path to libbfd.so instead of relying on the entries in libbfd.la. +libopcodes_la_DEPENDENCIES = $(OFILES) @SHARED_DEPENDENCIES@ +libopcodes_la_LIBADD = $(OFILES) @SHARED_LIBADD@ +# Allow dependency tracking to work on all the source files. +EXTRA_libopcodes_la_SOURCES = $(LIBOPCODES_CFILES) + +# libtool will build .libs/libopcodes.a. We create libopcodes.a in +# the build directory so that we don't have to convert all the +# programs that use libopcodes.a simultaneously. This is a hack which +# should be removed if everything else starts using libtool. FIXME. +noinst_LIBRARIES = libopcodes.a +libopcodes_a_SOURCES = +POTFILES = $(HFILES) $(CFILES) +CLEANFILES = \ + stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ + stamp-m32c stamp-m32r stamp-mep stamp-mt \ + stamp-openrisc stamp-xc16x stamp-xstormy16 \ + libopcodes.a stamp-lib + +CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu +CGEN = "`if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` -l ${cgendir}/guile.scm -s" +CGENFLAGS = -v +CGENDEPS = \ + $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ + $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ + $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ + $(CGENDIR)/opc-opinst.scm \ + cgen-asm.in cgen-dis.in cgen-ibld.in + +CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 +@CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30 +@CGEN_MAINT_FALSE@FRV_DEPS = +@CGEN_MAINT_TRUE@FRV_DEPS = stamp-frv +@CGEN_MAINT_FALSE@IP2K_DEPS = +@CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k +@CGEN_MAINT_FALSE@IQ2000_DEPS = +@CGEN_MAINT_TRUE@IQ2000_DEPS = stamp-iq2000 +@CGEN_MAINT_FALSE@LM32_DEPS = +@CGEN_MAINT_TRUE@LM32_DEPS = stamp-lm32 +@CGEN_MAINT_FALSE@M32C_DEPS = +@CGEN_MAINT_TRUE@M32C_DEPS = stamp-m32c +@CGEN_MAINT_FALSE@M32R_DEPS = +@CGEN_MAINT_TRUE@M32R_DEPS = stamp-m32r +@CGEN_MAINT_FALSE@MEP_DEPS = +@CGEN_MAINT_TRUE@MEP_DEPS = stamp-mep +@CGEN_MAINT_FALSE@MT_DEPS = +@CGEN_MAINT_TRUE@MT_DEPS = stamp-mt +@CGEN_MAINT_FALSE@OPENRISC_DEPS = +@CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc +@CGEN_MAINT_FALSE@XC16X_DEPS = +@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x +@CGEN_MAINT_FALSE@XSTORMY16_DEPS = +@CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16 +MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_BUILD) ia64-gen$(EXEEXT_FOR_BUILD) \ + s390-mkopc$(EXEEXT_FOR_BUILD) z8kgen$(EXEEXT_FOR_BUILD) \ + opc2c$(EXEEXT_FOR_BUILD) + +MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \ + $(srcdir)/ia64-asmtab.c s390-opc.tab $(srcdir)/z8k-opc.h \ + $(srcdir)/rx-decode.c + + +# Use a helper variable for the dependencies to avoid 'make' issues +# with continuations in comments, as @MAINT@ can be expanded to '#'. +ia64_asmtab_deps = ia64-gen$(EXEEXT_FOR_BUILD) ia64-ic.tbl \ + ia64-raw.tbl ia64-waw.tbl ia64-war.tbl + +all: config.h + $(MAKE) $(AM_MAKEFLAGS) all-recursive + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +am--refresh: + @: +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \ + $(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \ + $(am__cd) $(top_srcdir) && \ + $(AUTOMAKE) --foreign Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + echo ' $(SHELL) ./config.status'; \ + $(SHELL) ./config.status;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + $(SHELL) ./config.status --recheck + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + $(am__cd) $(srcdir) && $(AUTOCONF) +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + $(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS) +$(am__aclocal_m4_deps): + +config.h: stamp-h1 + @if test ! -f $@; then \ + rm -f stamp-h1; \ + $(MAKE) $(AM_MAKEFLAGS) stamp-h1; \ + else :; fi + +stamp-h1: $(srcdir)/config.in $(top_builddir)/config.status + @rm -f stamp-h1 + cd $(top_builddir) && $(SHELL) ./config.status config.h +$(srcdir)/config.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + ($(am__cd) $(top_srcdir) && $(AUTOHEADER)) + rm -f stamp-h1 + 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We just wanted to have am__tar + # and am__untar set. + test -n "${am_cv_prog_tar_$1}" && break + + # tar/untar a dummy directory, and stop if the command works + rm -rf conftest.dir + mkdir conftest.dir + echo GrepMe > conftest.dir/file + AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) + rm -rf conftest.dir + if test -s conftest.tar; then + AM_RUN_LOG([$am__untar /dev/null 2>&1 && break + fi +done +rm -rf conftest.dir + +AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) +AC_MSG_RESULT([$am_cv_prog_tar_$1])]) +AC_SUBST([am__tar]) +AC_SUBST([am__untar]) +]) # _AM_PROG_TAR + +m4_include([../bfd/acinclude.m4]) +m4_include([../bfd/warning.m4]) +m4_include([../config/acx.m4]) +m4_include([../config/depstand.m4]) +m4_include([../config/gettext-sister.m4]) +m4_include([../config/lead-dot.m4]) +m4_include([../config/nls.m4]) +m4_include([../config/override.m4]) +m4_include([../config/po.m4]) +m4_include([../config/progtest.m4]) +m4_include([../libtool.m4]) +m4_include([../ltoptions.m4]) +m4_include([../ltsugar.m4]) +m4_include([../ltversion.m4]) +m4_include([../lt~obsolete.m4]) diff --git a/external/gpl3/gdb/dist/opcodes/alpha-dis.c b/external/gpl3/gdb/dist/opcodes/alpha-dis.c new file mode 100644 index 000000000000..00b552f7049d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/alpha-dis.c @@ -0,0 +1,210 @@ +/* alpha-dis.c -- Disassemble Alpha AXP instructions + Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2005, 2007 + Free Software Foundation, Inc. + Contributed by Richard Henderson , + patterned after the PPC opcode handling written by Ian Lance Taylor. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/alpha.h" + +/* OSF register names. */ + +static const char * const osf_regnames[64] = { + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +/* VMS register names. */ + +static const char * const vms_regnames[64] = { + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", + "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", + "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", + "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", + "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", + "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", + "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" +}; + +/* Disassemble Alpha instructions. */ + +int +print_insn_alpha (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; + const char * const * regnames; + const struct alpha_opcode *opcode, *opcode_end; + const unsigned char *opindex; + unsigned insn, op, isa_mask; + int need_comma; + + /* Initialize the majorop table the first time through */ + if (!opcode_index[0]) + { + opcode = alpha_opcodes; + opcode_end = opcode + alpha_num_opcodes; + + for (op = 0; op < AXP_NOPS; ++op) + { + opcode_index[op] = opcode; + while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) + ++opcode; + } + opcode_index[op] = opcode; + } + + if (info->flavour == bfd_target_evax_flavour) + regnames = vms_regnames; + else + regnames = osf_regnames; + + isa_mask = AXP_OPCODE_NOPAL; + switch (info->mach) + { + case bfd_mach_alpha_ev4: + isa_mask |= AXP_OPCODE_EV4; + break; + case bfd_mach_alpha_ev5: + isa_mask |= AXP_OPCODE_EV5; + break; + case bfd_mach_alpha_ev6: + isa_mask |= AXP_OPCODE_EV6; + break; + } + + /* Read the insn into a host word */ + { + bfd_byte buffer[4]; + int status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getl32 (buffer); + } + + /* Get the major opcode of the instruction. */ + op = AXP_OP (insn); + + /* Find the first match in the opcode table. */ + opcode_end = opcode_index[op + 1]; + for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) + { + if ((insn ^ opcode->opcode) & opcode->mask) + continue; + + if (!(opcode->flags & isa_mask)) + continue; + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + { + int invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, &invalid); + } + if (invalid) + continue; + } + + /* The instruction is valid. */ + goto found; + } + + /* No instruction found */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + + return 4; + +found: + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + + /* Now extract and print the operands. */ + need_comma = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct alpha_operand *operand = alpha_operands + *opindex; + int value; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & AXP_OPERAND_FAKE) != 0) + continue; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, (int *) NULL); + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if (operand->flags & AXP_OPERAND_SIGNED) + { + int signbit = 1 << (operand->bits - 1); + value = (value ^ signbit) - signbit; + } + } + + if (need_comma && + ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) + != AXP_OPERAND_PARENS)) + { + (*info->fprintf_func) (info->stream, ","); + } + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, "("); + + /* Print the operand as directed by the flags. */ + if (operand->flags & AXP_OPERAND_IR) + (*info->fprintf_func) (info->stream, "%s", regnames[value]); + else if (operand->flags & AXP_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); + else if (operand->flags & AXP_OPERAND_RELATIVE) + (*info->print_address_func) (memaddr + 4 + value, info); + else if (operand->flags & AXP_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%d", value); + else + (*info->fprintf_func) (info->stream, "%#x", value); + + if (operand->flags & AXP_OPERAND_PARENS) + (*info->fprintf_func) (info->stream, ")"); + need_comma = 1; + } + + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/alpha-opc.c b/external/gpl3/gdb/dist/opcodes/alpha-opc.c new file mode 100644 index 000000000000..d8c71219e61d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/alpha-opc.c @@ -0,0 +1,1498 @@ +/* alpha-opc.c -- Alpha AXP opcode list + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 + Free Software Foundation, Inc. + Contributed by Richard Henderson , + patterned after the PPC opcode handling written by Ian Lance Taylor. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/alpha.h" +#include "bfd.h" +#include "opintl.h" + +/* This file holds the Alpha AXP opcode table. The opcode table includes + almost all of the extended instruction mnemonics. This permits the + disassembler to use them, and simplifies the assembler logic, at the + cost of increasing the table size. The table is strictly constant + data, so the compiler should be able to put it in the text segment. + + This file also holds the operand table. All knowledge about inserting + and extracting operands from instructions is kept in this file. + + The information for the base instruction set was compiled from the + _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, + version 2. + + The information for the post-ev5 architecture extensions BWX, CIX and + MAX came from version 3 of this same document, which is also available + on-line at http://ftp.digital.com/pub/Digital/info/semiconductor + /literature/alphahb2.pdf + + The information for the EV4 PALcode instructions was compiled from + _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware + Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary + revision dated June 1994. + + The information for the EV5 PALcode instructions was compiled from + _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital + Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ + +/* The RB field when it is the same as the RA field in the same insn. + This operand is marked fake. The insertion function just copies + the RA field into the RB field, and the extraction function just + checks that the fields are the same. */ + +static unsigned +insert_rba (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 21) & 0x1f) << 16); +} + +static int +extract_rba (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The same for the RC field. */ + +static unsigned +insert_rca (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((insn >> 21) & 0x1f); +} + +static int +extract_rca (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != (insn & 0x1f)) + *invalid = 1; + return 0; +} + +/* Fake arguments in which the registers must be set to ZERO. */ + +static unsigned +insert_za (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (31 << 21); +} + +static int +extract_za (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +static unsigned +insert_zb (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (31 << 16); +} + +static int +extract_zb (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +static unsigned +insert_zc (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | 31; +} + +static int +extract_zc (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && (insn & 0x1f) != 31) + *invalid = 1; + return 0; +} + + +/* The displacement field of a Branch format insn. */ + +static unsigned +insert_bdisp (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("branch operand unaligned"); + return insn | ((value / 4) & 0x1FFFFF); +} + +static int +extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); +} + +/* The hint field of a JMP/JSR insn. */ + +static unsigned +insert_jhint (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x3FFF); +} + +static int +extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); +} + +/* The hint field of an EV6 HW_JMP/JSR insn. */ + +static unsigned +insert_ev6hwjhint (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x1FFF); +} + +static int +extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); +} + +/* The operands table. */ + +const struct alpha_operand alpha_operands[] = +{ + /* The fields are bits, shift, insert, extract, flags */ + /* The zero index is used to indicate end-of-list */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, 0 }, + + /* The plain integer register fields. */ +#define RA (UNUSED + 1) + { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, +#define RB (RA + 1) + { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, +#define RC (RB + 1) + { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, + + /* The plain fp register fields. */ +#define FA (RC + 1) + { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, +#define FB (FA + 1) + { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, +#define FC (FB + 1) + { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, + + /* The integer registers when they are ZERO. */ +#define ZA (FC + 1) + { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, +#define ZB (ZA + 1) + { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, +#define ZC (ZB + 1) + { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, + + /* The RB field when it needs parentheses. */ +#define PRB (ZC + 1) + { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, + + /* The RB field when it needs parentheses _and_ a preceding comma. */ +#define CPRB (PRB + 1) + { 5, 16, 0, + AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, + + /* The RB field when it must be the same as the RA field. */ +#define RBA (CPRB + 1) + { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, + + /* The RC field when it must be the same as the RB field. */ +#define RCA (RBA + 1) + { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, + + /* The RC field when it can *default* to RA. */ +#define DRC1 (RCA + 1) + { 5, 0, 0, + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, + + /* The RC field when it can *default* to RB. */ +#define DRC2 (DRC1 + 1) + { 5, 0, 0, + AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, + + /* The FC field when it can *default* to RA. */ +#define DFC1 (DRC2 + 1) + { 5, 0, 0, + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, + + /* The FC field when it can *default* to RB. */ +#define DFC2 (DFC1 + 1) + { 5, 0, 0, + AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, + + /* The unsigned 8-bit literal of Operate format insns. */ +#define LIT (DFC2 + 1) + { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The signed 16-bit displacement of Memory format insns. From here + we can't tell what relocation should be used, so don't use a default. */ +#define MDISP (LIT + 1) + { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The signed "23-bit" aligned displacement of Branch format insns. */ +#define BDISP (MDISP + 1) + { 21, 0, BFD_RELOC_23_PCREL_S2, + AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, + + /* The 26-bit PALcode function */ +#define PALFN (BDISP + 1) + { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */ +#define JMPHINT (PALFN + 1) + { 14, 0, BFD_RELOC_ALPHA_HINT, + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, + insert_jhint, extract_jhint }, + + /* The optional hint to RET/JSR_COROUTINE. */ +#define RETHINT (JMPHINT + 1) + { 14, 0, -RETHINT, + AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, + + /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */ +#define EV4HWDISP (RETHINT + 1) +#define EV6HWDISP (EV4HWDISP) + { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */ +#define EV4HWINDEX (EV4HWDISP + 1) + { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns + that occur in DEC PALcode. */ +#define EV4EXTHWINDEX (EV4HWINDEX + 1) + { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */ +#define EV5HWDISP (EV4EXTHWINDEX + 1) + { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, + + /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */ +#define EV5HWINDEX (EV5HWDISP + 1) + { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 16-bit combined index/scoreboard mask for the ev6 + hw_m[ft]pr (pal19/pal1d) insns. */ +#define EV6HWINDEX (EV5HWINDEX + 1) + { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, + + /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */ +#define EV6HWJMPHINT (EV6HWINDEX+ 1) + { 8, 0, -EV6HWJMPHINT, + AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, + insert_ev6hwjhint, extract_ev6hwjhint } +}; + +const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); + + +/* Macros used to form opcodes. */ + +/* The main opcode. */ +#define OP(x) (((x) & 0x3F) << 26) +#define OP_MASK 0xFC000000 + +/* Branch format instructions. */ +#define BRA_(oo) OP(oo) +#define BRA_MASK OP_MASK +#define BRA(oo) BRA_(oo), BRA_MASK + +/* Floating point format instructions. */ +#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) +#define FP_MASK (OP_MASK | 0xFFE0) +#define FP(oo,fff) FP_(oo,fff), FP_MASK + +/* Memory format instructions. */ +#define MEM_(oo) OP(oo) +#define MEM_MASK OP_MASK +#define MEM(oo) MEM_(oo), MEM_MASK + +/* Memory/Func Code format instructions. */ +#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) +#define MFC_MASK (OP_MASK | 0xFFFF) +#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK + +/* Memory/Branch format instructions. */ +#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) +#define MBR_MASK (OP_MASK | 0xC000) +#define MBR(oo,h) MBR_(oo,h), MBR_MASK + +/* Operate format instructions. The OPRL variant specifies a + literal second argument. */ +#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) +#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) +#define OPR_MASK (OP_MASK | 0x1FE0) +#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK +#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK + +/* Generic PALcode format instructions. */ +#define PCD_(oo) OP(oo) +#define PCD_MASK OP_MASK +#define PCD(oo) PCD_(oo), PCD_MASK + +/* Specific PALcode instructions. */ +#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) +#define SPCD_MASK 0xFFFFFFFF +#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK + +/* Hardware memory (hw_{ld,st}) instructions. */ +#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) +#define EV4HWMEM_MASK (OP_MASK | 0xF000) +#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK + +#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) +#define EV5HWMEM_MASK (OP_MASK | 0xF800) +#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK + +#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) +#define EV6HWMEM_MASK (OP_MASK | 0xF000) +#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK + +#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) +#define EV6HWMBR_MASK (OP_MASK | 0xE000) +#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK + +/* Abbreviations for instruction subsets. */ +#define BASE AXP_OPCODE_BASE +#define EV4 AXP_OPCODE_EV4 +#define EV5 AXP_OPCODE_EV5 +#define EV6 AXP_OPCODE_EV6 +#define BWX AXP_OPCODE_BWX +#define CIX AXP_OPCODE_CIX +#define MAX AXP_OPCODE_MAX + +/* Common combinations of arguments. */ +#define ARG_NONE { 0 } +#define ARG_BRA { RA, BDISP } +#define ARG_FBRA { FA, BDISP } +#define ARG_FP { FA, FB, DFC1 } +#define ARG_FPZ1 { ZA, FB, DFC1 } +#define ARG_MEM { RA, MDISP, PRB } +#define ARG_FMEM { FA, MDISP, PRB } +#define ARG_OPR { RA, RB, DRC1 } +#define ARG_OPRL { RA, LIT, DRC1 } +#define ARG_OPRZ1 { ZA, RB, DRC1 } +#define ARG_OPRLZ1 { ZA, LIT, RC } +#define ARG_PCD { PALFN } +#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } +#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } +#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } +#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } + + NAME is the name of the instruction. + + OPCODE is the instruction opcode. + + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + + OPERANDS is the list of operands. + + The preceding macros merge the text of the OPCODE and MASK fields. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. + + Otherwise, it is sorted by major opcode and minor function code. + + There are three classes of not-really-instructions in this table: + + ALIAS is another name for another instruction. Some of + these come from the Architecture Handbook, some + come from the original gas opcode tables. In all + cases, the functionality of the opcode is unchanged. + + PSEUDO a stylized code form endorsed by Chapter A.4 of the + Architecture Handbook. + + EXTRA a stylized code form found in the original gas tables. + + And two annotations: + + EV56 BUT opcodes that are officially introduced as of the ev56, + but with defined results on previous implementations. + + EV56 UNA opcodes that were introduced as of the ev56 with + presumably undefined results on previous implementations + that were not assigned to a particular extension. */ + +const struct alpha_opcode alpha_opcodes[] = +{ + { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, + { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, + { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, + { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, + { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, + { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, + { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, + { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, + { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, + { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, + { "call_pal", PCD(0x00), BASE, ARG_PCD }, + { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ + + { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ + { "lda", MEM(0x08), BASE, ARG_MEM }, + { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ + { "ldah", MEM(0x09), BASE, ARG_MEM }, + { "ldbu", MEM(0x0A), BWX, ARG_MEM }, + { "unop", MEM_(0x0B) | (30 << 16), + MEM_MASK, BASE, { ZA } }, /* pseudo */ + { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, + { "ldwu", MEM(0x0C), BWX, ARG_MEM }, + { "stw", MEM(0x0D), BWX, ARG_MEM }, + { "stb", MEM(0x0E), BWX, ARG_MEM }, + { "stq_u", MEM(0x0F), BASE, ARG_MEM }, + + { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ + { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, + { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, + { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, + { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, + { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, + { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, + { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, + { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, + { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, + { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, + { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, + { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, + { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, + { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, + { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, + { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, + { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, + { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, + { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, + { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, + { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, + { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, + { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, + { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, + { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, + { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, + { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, + { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, + { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, + { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, + { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, + { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, + { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, + { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, + { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, + { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, + { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, + { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, + { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, + { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, + { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ + { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, + { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, + { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, + { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, + + { "and", OPR(0x11,0x00), BASE, ARG_OPR }, + { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, + { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ + { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ + { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, + { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, + { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, + { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, + { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, + { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, + { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ + { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ + { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ + { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ + { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ + { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ + { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ + { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, + { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, + { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, + { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, + { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, + { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, + { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ + { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ + { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, + { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, + { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, + { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, + { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, + { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, + { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, + { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, + { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, + { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, + { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ + { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ + { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ + { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ + { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, + { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, + { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, + { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, + { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), + 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ + + { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, + { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, + { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, + { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, + { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, + { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, + { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, + { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, + { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, + { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, + { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, + { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, + { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, + { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, + { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, + { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, + { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, + { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, + { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, + { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, + { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, + { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, + { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, + { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, + { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, + { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, + { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, + { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, + { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, + { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, + { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, + { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, + { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, + { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, + { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, + { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, + { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, + { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, + { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, + { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, + { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, + { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, + { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, + { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, + { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, + { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, + { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, + { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, + { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, + { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, + { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, + { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, + + { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, + { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, + { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, + { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, + { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, + { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, + { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, + { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, + { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, + { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, + + { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, + { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, + { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, + { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, + { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, + { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, + { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, + { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, + { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, + { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, + { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, + { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, + { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, + { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, + { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, + { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, + { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, + { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, + { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, + { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, + { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, + { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, + { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, + { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, + { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, + { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, + { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, + { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, + { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, + { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, + { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, + { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, + { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, + { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, + { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, + { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, + { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, + { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, + { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, + { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, + { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, + { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, + { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, + { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, + { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, + { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, + { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, + { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, + { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, + { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, + { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, + + { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, + { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, + { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, + { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, + { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, + { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, + { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, + { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, + { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, + { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, + { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, + { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, + { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, + { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, + { "addf", FP(0x15,0x080), BASE, ARG_FP }, + { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ + { "subf", FP(0x15,0x081), BASE, ARG_FP }, + { "mulf", FP(0x15,0x082), BASE, ARG_FP }, + { "divf", FP(0x15,0x083), BASE, ARG_FP }, + { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, + { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, + { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, + { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, + { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, + { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, + { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, + { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, + { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, + { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, + { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, + { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, + { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, + { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, + { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, + { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, + { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, + { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, + { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, + { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, + { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, + { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, + { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, + { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, + { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, + { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, + { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, + { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, + { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, + { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, + { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, + { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, + { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, + { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, + { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, + { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, + { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, + { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, + { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, + { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, + { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, + { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, + { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, + { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, + { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, + { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, + { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, + { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, + { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, + { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, + { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ + { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, + { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, + { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, + { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, + { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, + { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, + { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, + { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, + { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, + { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, + { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, + { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, + { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, + { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, + { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, + { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, + { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, + { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, + { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, + { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, + { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, + { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, + { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, + { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, + { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, + { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, + { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, + { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, + { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, + { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, + { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, + { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, + { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, + { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, + { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, + { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, + { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, + { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, + + { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, + { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, + { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, + { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, + { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, + { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, + { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, + { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, + { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, + { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, + { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, + { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, + { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, + { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, + { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, + { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, + { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, + { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, + { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, + { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, + { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, + { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, + { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, + { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, + { "adds", FP(0x16,0x080), BASE, ARG_FP }, + { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs", FP(0x16,0x081), BASE, ARG_FP }, + { "muls", FP(0x16,0x082), BASE, ARG_FP }, + { "divs", FP(0x16,0x083), BASE, ARG_FP }, + { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, + { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, + { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, + { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, + { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, + { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, + { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, + { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, + { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, + { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, + { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, + { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, + { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, + { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, + { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, + { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, + { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, + { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, + { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, + { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, + { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, + { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, + { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, + { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, + { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, + { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, + { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, + { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, + { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, + { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, + { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, + { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, + { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, + { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, + { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, + { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, + { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, + { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, + { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, + { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, + { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, + { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, + { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, + { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, + { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, + { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, + { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, + { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, + { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, + { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, + { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, + { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, + { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, + { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, + { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, + { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, + { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, + { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, + { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, + { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, + { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, + { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, + { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, + { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, + { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, + { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, + { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, + { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, + { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, + { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, + { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, + { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, + { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, + { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, + { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, + { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, + { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, + { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, + { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, + { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, + { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, + { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, + { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, + { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, + { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, + { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, + { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, + { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, + { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, + { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, + { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, + { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, + { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, + { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, + { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, + { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, + { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, + { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, + { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, + { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, + { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, + { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, + { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, + { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, + { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, + { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, + { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, + { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, + { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, + { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, + { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, + { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, + { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, + { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, + { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, + { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, + { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, + { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, + { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, + { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, + { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, + { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, + { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, + { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, + { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, + { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, + { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, + { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, + { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, + { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, + { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, + { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, + { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, + { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, + { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, + { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ + { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, + { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, + { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, + { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, + { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ + { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, + { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, + { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, + { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, + { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, + { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, + { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, + { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, + { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, + { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, + { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, + { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, + { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, + { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, + { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, + { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, + { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, + { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, + { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, + + { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, + { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ + { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ + { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ + { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ + { "cpys", FP(0x17,0x020), BASE, ARG_FP }, + { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ + { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, + { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, + { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, + { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, + { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, + { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, + { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, + { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, + { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, + { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, + { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, + { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, + { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, + + { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, + { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ + { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, + { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, + { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, + { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, + { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, + { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, + { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ + { "rc", MFC(0x18,0xE000), BASE, { RA } }, + { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ + { "rs", MFC(0x18,0xF000), BASE, { RA } }, + { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ + { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ + + { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, + { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, + { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, + { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, + { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, + { "pal19", PCD(0x19), BASE, ARG_PCD }, + + { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ + BASE, { ZA, CPRB } }, + { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, + { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, + { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ + 0xFFFFFFFF, BASE, { 0 } }, + { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, + { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ + { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, + + { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, + { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, + { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, + { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, + { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, + { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, + { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, + { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, + { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, + { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, + { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, + { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, + { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, + { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, + { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, + { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, + { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, + { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, + { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, + { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, + { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, + { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, + { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, + { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, + { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, + { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, + { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, + { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, + { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, + { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, + { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, + { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, + { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, + { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, + { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, + { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, + { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, + { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, + { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, + { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, + { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, + { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, + { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, + { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, + { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, + { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, + { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, + { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, + { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, + { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, + { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, + { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, + { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, + { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, + { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, + { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, + { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, + { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, + { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, + { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, + { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, + { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, + { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, + { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, + { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, + { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, + { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, + { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, + { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, + { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, + { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, + { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, + { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, + { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, + { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, + { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, + { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, + { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, + { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, + { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, + { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, + { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, + { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, + { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, + { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, + { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, + { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, + { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, + { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, + { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, + { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, + { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, + { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, + { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, + { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, + { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, + { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, + { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, + { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, + { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, + { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, + { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, + { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, + { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, + { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, + { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, + { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, + { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, + { "pal1b", PCD(0x1B), BASE, ARG_PCD }, + + { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, + { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, + { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, + { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, + { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, + { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, + { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, + { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, + { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, + { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, + { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, + { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, + { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, + { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, + { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, + { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, + { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, + { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, + { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, + { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, + { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, + { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, + { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, + { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, + { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, + { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, + { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, + { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, + + { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, + { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, + { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, + { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, + { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, + { "pal1d", PCD(0x1D), BASE, ARG_PCD }, + + { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, + { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, + { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, + { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, + { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ + { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, + { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, + { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, + { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ + { "pal1e", PCD(0x1E), BASE, ARG_PCD }, + + { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, + { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, + { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ + { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, + { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, + { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, + { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, + { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, + { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, + { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, + { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, + { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, + { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, + { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, + { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, + { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, + { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, + { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, + { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, + { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, + { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, + { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ + { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, + { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, + { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, + { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, + { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, + { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, + { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, + { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, + { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, + { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, + { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, + { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, + { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, + { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, + { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, + { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, + { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, + { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, + { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, + { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, + { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, + { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, + { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, + { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, + { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, + { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, + { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, + { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, + { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, + { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, + { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, + { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, + { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, + { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, + { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, + { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, + { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, + { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, + { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, + { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, + { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, + { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, + { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, + { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, + { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, + { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, + { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, + { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, + { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, + { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, + { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, + { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, + { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, + { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, + { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, + { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, + { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, + { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, + { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, + { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, + { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, + { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, + { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, + { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, + { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, + { "pal1f", PCD(0x1F), BASE, ARG_PCD }, + + { "ldf", MEM(0x20), BASE, ARG_FMEM }, + { "ldg", MEM(0x21), BASE, ARG_FMEM }, + { "lds", MEM(0x22), BASE, ARG_FMEM }, + { "ldt", MEM(0x23), BASE, ARG_FMEM }, + { "stf", MEM(0x24), BASE, ARG_FMEM }, + { "stg", MEM(0x25), BASE, ARG_FMEM }, + { "sts", MEM(0x26), BASE, ARG_FMEM }, + { "stt", MEM(0x27), BASE, ARG_FMEM }, + + { "ldl", MEM(0x28), BASE, ARG_MEM }, + { "ldq", MEM(0x29), BASE, ARG_MEM }, + { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, + { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, + { "stl", MEM(0x2C), BASE, ARG_MEM }, + { "stq", MEM(0x2D), BASE, ARG_MEM }, + { "stl_c", MEM(0x2E), BASE, ARG_MEM }, + { "stq_c", MEM(0x2F), BASE, ARG_MEM }, + + { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ + { "br", BRA(0x30), BASE, ARG_BRA }, + { "fbeq", BRA(0x31), BASE, ARG_FBRA }, + { "fblt", BRA(0x32), BASE, ARG_FBRA }, + { "fble", BRA(0x33), BASE, ARG_FBRA }, + { "bsr", BRA(0x34), BASE, ARG_BRA }, + { "fbne", BRA(0x35), BASE, ARG_FBRA }, + { "fbge", BRA(0x36), BASE, ARG_FBRA }, + { "fbgt", BRA(0x37), BASE, ARG_FBRA }, + { "blbc", BRA(0x38), BASE, ARG_BRA }, + { "beq", BRA(0x39), BASE, ARG_BRA }, + { "blt", BRA(0x3A), BASE, ARG_BRA }, + { "ble", BRA(0x3B), BASE, ARG_BRA }, + { "blbs", BRA(0x3C), BASE, ARG_BRA }, + { "bne", BRA(0x3D), BASE, ARG_BRA }, + { "bge", BRA(0x3E), BASE, ARG_BRA }, + { "bgt", BRA(0x3F), BASE, ARG_BRA }, +}; + +const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); diff --git a/external/gpl3/gdb/dist/opcodes/arc-dis.c b/external/gpl3/gdb/dist/opcodes/arc-dis.c new file mode 100644 index 000000000000..b4cc241615fc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arc-dis.c @@ -0,0 +1,1230 @@ +/* Instruction printing code for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009, 2010 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "dis-asm.h" +#include "opcode/arc.h" +#include "elf-bfd.h" +#include "elf/arc.h" +#include +#include "opintl.h" + +#include +#include "arc-dis.h" +#include "arc-ext.h" + +#ifndef dbg +#define dbg (0) +#endif + +/* Classification of the opcodes for the decoder to print + the instructions. */ + +typedef enum +{ + CLASS_A4_ARITH, + CLASS_A4_OP3_GENERAL, + CLASS_A4_FLAG, + /* All branches other than JC. */ + CLASS_A4_BRANCH, + CLASS_A4_JC , + /* All loads other than immediate + indexed loads. */ + CLASS_A4_LD0, + CLASS_A4_LD1, + CLASS_A4_ST, + CLASS_A4_SR, + /* All single operand instructions. */ + CLASS_A4_OP3_SUBOPC3F, + CLASS_A4_LR +} a4_decoding_class; + +#define BIT(word,n) ((word) & (1 << n)) +#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) +#define OPCODE(word) (BITS ((word), 27, 31)) +#define FIELDA(word) (BITS ((word), 21, 26)) +#define FIELDB(word) (BITS ((word), 15, 20)) +#define FIELDC(word) (BITS ((word), 9, 14)) + +/* FIELD D is signed in all of its uses, so we make sure argument is + treated as signed for bit shifting purposes: */ +#define FIELDD(word) (BITS (((signed int)word), 0, 8)) + +#define PUT_NEXT_WORD_IN(a) \ + do \ + { \ + if (is_limm == 1 && !NEXT_WORD (1)) \ + mwerror (state, _("Illegal limm reference in last instruction!\n")); \ + a = state->words[1]; \ + } \ + while (0) + +#define CHECK_FLAG_COND_NULLIFY() \ + do \ + { \ + if (is_shimm == 0) \ + { \ + flag = BIT (state->words[0], 8); \ + state->nullifyMode = BITS (state->words[0], 5, 6); \ + cond = BITS (state->words[0], 0, 4); \ + } \ + } \ + while (0) + +#define CHECK_COND() \ + do \ + { \ + if (is_shimm == 0) \ + cond = BITS (state->words[0], 0, 4); \ + } \ + while (0) + +#define CHECK_FIELD(field) \ + do \ + { \ + if (field == 62) \ + { \ + is_limm++; \ + field##isReg = 0; \ + PUT_NEXT_WORD_IN (field); \ + limm_value = field; \ + } \ + else if (field > 60) \ + { \ + field##isReg = 0; \ + is_shimm++; \ + flag = (field == 61); \ + field = FIELDD (state->words[0]); \ + } \ + } \ + while (0) + +#define CHECK_FIELD_A() \ + do \ + { \ + fieldA = FIELDA (state->words[0]); \ + if (fieldA > 60) \ + { \ + fieldAisReg = 0; \ + fieldA = 0; \ + } \ + } \ + while (0) + +#define CHECK_FIELD_B() \ + do \ + { \ + fieldB = FIELDB (state->words[0]); \ + CHECK_FIELD (fieldB); \ + } \ + while (0) + +#define CHECK_FIELD_C() \ + do \ + { \ + fieldC = FIELDC (state->words[0]); \ + CHECK_FIELD (fieldC); \ + } \ + while (0) + +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","") +#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ + (IS_REG (x) ? cb1"%r"ca1 : \ + usesAuxReg ? cb"%a"ca : \ + IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) +#define WRITE_FORMAT_RB() strcat (formatString, "]") +#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) +#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); + +#define NEXT_WORD(x) (offset += 4, state->words[x]) + +#define add_target(x) (state->targets[state->tcnt++] = (x)) + +static char comment_prefix[] = "\t; "; + +static const char * +core_reg_name (struct arcDisState * state, int val) +{ + if (state->coreRegName) + return (*state->coreRegName)(state->_this, val); + return 0; +} + +static const char * +aux_reg_name (struct arcDisState * state, int val) +{ + if (state->auxRegName) + return (*state->auxRegName)(state->_this, val); + return 0; +} + +static const char * +cond_code_name (struct arcDisState * state, int val) +{ + if (state->condCodeName) + return (*state->condCodeName)(state->_this, val); + return 0; +} + +static const char * +instruction_name (struct arcDisState * state, + int op1, + int op2, + int * flags) +{ + if (state->instName) + return (*state->instName)(state->_this, op1, op2, flags); + return 0; +} + +static void +mwerror (struct arcDisState * state, const char * msg) +{ + if (state->err != 0) + (*state->err)(state->_this, (msg)); +} + +static const char * +post_address (struct arcDisState * state, int addr) +{ + static char id[3 * ARRAY_SIZE (state->addresses)]; + int j, i = state->acnt; + + if (i < ((int) ARRAY_SIZE (state->addresses))) + { + state->addresses[i] = addr; + ++state->acnt; + j = i*3; + id[j+0] = '@'; + id[j+1] = '0'+i; + id[j+2] = 0; + + return id + j; + } + return ""; +} + +static void +arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) +{ + char *bp; + const char *p; + int size, leading_zero, regMap[2]; + va_list ap; + + va_start (ap, format); + + bp = buf; + *bp = 0; + p = format; + regMap[0] = 0; + regMap[1] = 0; + + while (1) + switch (*p++) + { + case 0: + goto DOCOMM; /* (return) */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY: ; + switch (*p++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + /* size. */ + size = p[-1] - '0'; + if (size == 0) + leading_zero = 1; /* e.g. %08x */ + while (*p >= '0' && *p <= '9') + { + size = size * 10 + *p - '0'; + p++; + } + goto RETRY; + } +#define inc_bp() bp = bp + strlen (bp) + + case 'h': + { + unsigned u = va_arg (ap, int); + + /* Hex. We can change the format to 0x%08x in + one place, here, if we wish. + We add underscores for easy reading. */ + if (u > 65536) + sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); + else + sprintf (bp, "0x%x", u); + inc_bp (); + } + break; + case 'X': case 'x': + { + int val = va_arg (ap, int); + + if (size != 0) + if (leading_zero) + sprintf (bp, "%0*x", size, val); + else + sprintf (bp, "%*x", size, val); + else + sprintf (bp, "%x", val); + inc_bp (); + } + break; + case 'd': + { + int val = va_arg (ap, int); + + if (size != 0) + sprintf (bp, "%*d", size, val); + else + sprintf (bp, "%d", val); + inc_bp (); + } + break; + case 'r': + { + /* Register. */ + int val = va_arg (ap, int); + +#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ + regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; + + switch (val) + { + REG2NAME (26, "gp"); + REG2NAME (27, "fp"); + REG2NAME (28, "sp"); + REG2NAME (29, "ilink1"); + REG2NAME (30, "ilink2"); + REG2NAME (31, "blink"); + REG2NAME (60, "lp_count"); + default: + { + const char * ext; + + ext = core_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + sprintf (bp,"r%d",val); + } + break; + } + inc_bp (); + } break; + + case 'a': + { + /* Aux Register. */ + int val = va_arg (ap, int); + +#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; + + switch (val) + { + AUXREG2NAME (0x0, "status"); + AUXREG2NAME (0x1, "semaphore"); + AUXREG2NAME (0x2, "lp_start"); + AUXREG2NAME (0x3, "lp_end"); + AUXREG2NAME (0x4, "identity"); + AUXREG2NAME (0x5, "debug"); + default: + { + const char *ext; + + ext = aux_reg_name (state, val); + if (ext) + sprintf (bp, "%s", ext); + else + arc_sprintf (state, bp, "%h", val); + } + break; + } + inc_bp (); + } + break; + + case 's': + { + sprintf (bp, "%s", va_arg (ap, char *)); + inc_bp (); + } + break; + + default: + fprintf (stderr, "?? format %c\n", p[-1]); + break; + } + } + + DOCOMM: *bp = 0; + va_end (ap); +} + +static void +write_comments_(struct arcDisState * state, + int shimm, + int is_limm, + long limm_value) +{ + if (state->commentBuffer != 0) + { + int i; + + if (is_limm) + { + const char *name = post_address (state, limm_value + shimm); + + if (*name != 0) + WRITE_COMMENT (name); + } + for (i = 0; i < state->commNum; i++) + { + if (i == 0) + strcpy (state->commentBuffer, comment_prefix); + else + strcat (state->commentBuffer, ", "); + strncat (state->commentBuffer, state->comm[i], + sizeof (state->commentBuffer)); + } + } +} + +#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value) +#define write_comments() write_comments2 (0) + +static const char *condName[] = +{ + /* 0..15. */ + "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , + "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" +}; + +static void +write_instr_name_(struct arcDisState * state, + const char * instrName, + int cond, + int condCodeIsPartOfName, + int flag, + int signExtend, + int addrWriteBack, + int directMem) +{ + strcpy (state->instrBuffer, instrName); + + if (cond > 0) + { + const char *cc = 0; + + if (!condCodeIsPartOfName) + strcat (state->instrBuffer, "."); + + if (cond < 16) + cc = condName[cond]; + else + cc = cond_code_name (state, cond); + + if (!cc) + cc = "???"; + + strcat (state->instrBuffer, cc); + } + + if (flag) + strcat (state->instrBuffer, ".f"); + + switch (state->nullifyMode) + { + case BR_exec_always: + strcat (state->instrBuffer, ".d"); + break; + case BR_exec_when_jump: + strcat (state->instrBuffer, ".jd"); + break; + } + + if (signExtend) + strcat (state->instrBuffer, ".x"); + + if (addrWriteBack) + strcat (state->instrBuffer, ".a"); + + if (directMem) + strcat (state->instrBuffer, ".di"); +} + +#define write_instr_name() \ + do \ + { \ + write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ + flag, signExtend, addrWriteBack, directMem); \ + formatString[0] = '\0'; \ + } \ + while (0) + +enum +{ + op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, + op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, + op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, + op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 +}; + +extern disassemble_info tm_print_insn_info; + +static int +dsmOneArcInst (bfd_vma addr, struct arcDisState * state) +{ + int condCodeIsPartOfName = 0; + a4_decoding_class decodingClass; + const char * instrName; + int repeatsOp = 0; + int fieldAisReg = 1; + int fieldBisReg = 1; + int fieldCisReg = 1; + int fieldA; + int fieldB; + int fieldC = 0; + int flag = 0; + int cond = 0; + int is_shimm = 0; + int is_limm = 0; + long limm_value = 0; + int signExtend = 0; + int addrWriteBack = 0; + int directMem = 0; + int is_linked = 0; + int offset = 0; + int usesAuxReg = 0; + int flags; + int ignoreFirstOpd; + char formatString[60]; + + state->instructionLen = 4; + state->nullifyMode = BR_exec_when_no_jump; + state->opWidth = 12; + state->isBranch = 0; + + state->_mem_load = 0; + state->_ea_present = 0; + state->_load_len = 0; + state->ea_reg1 = no_reg; + state->ea_reg2 = no_reg; + state->_offset = 0; + + if (! NEXT_WORD (0)) + return 0; + + state->_opcode = OPCODE (state->words[0]); + instrName = 0; + decodingClass = CLASS_A4_ARITH; /* default! */ + repeatsOp = 0; + condCodeIsPartOfName=0; + state->commNum = 0; + state->tcnt = 0; + state->acnt = 0; + state->flow = noflow; + ignoreFirstOpd = 0; + + if (state->commentBuffer) + state->commentBuffer[0] = '\0'; + + switch (state->_opcode) + { + case op_LD0: + switch (BITS (state->words[0],1,2)) + { + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = CLASS_A4_LD0; + break; + + case op_LD1: + if (BIT (state->words[0],13)) + { + instrName = "lr"; + decodingClass = CLASS_A4_LR; + } + else + { + switch (BITS (state->words[0], 10, 11)) + { + case 0: + instrName = "ld"; + state->_load_len = 4; + break; + case 1: + instrName = "ldb"; + state->_load_len = 1; + break; + case 2: + instrName = "ldw"; + state->_load_len = 2; + break; + default: + instrName = "??? (1[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = CLASS_A4_LD1; + } + break; + + case op_ST: + if (BIT (state->words[0], 25)) + { + instrName = "sr"; + decodingClass = CLASS_A4_SR; + } + else + { + switch (BITS (state->words[0], 22, 23)) + { + case 0: + instrName = "st"; + break; + case 1: + instrName = "stb"; + break; + case 2: + instrName = "stw"; + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + decodingClass = CLASS_A4_ST; + } + break; + + case op_3: + decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */ + switch (FIELDC (state->words[0])) + { + case 0: + instrName = "flag"; + decodingClass = CLASS_A4_FLAG; + break; + case 1: + instrName = "asr"; + break; + case 2: + instrName = "lsr"; + break; + case 3: + instrName = "ror"; + break; + case 4: + instrName = "rrc"; + break; + case 5: + instrName = "sexb"; + break; + case 6: + instrName = "sexw"; + break; + case 7: + instrName = "extb"; + break; + case 8: + instrName = "extw"; + break; + case 0x3f: + { + decodingClass = CLASS_A4_OP3_SUBOPC3F; + switch (FIELDD (state->words[0])) + { + case 0: + instrName = "brk"; + break; + case 1: + instrName = "sleep"; + break; + case 2: + instrName = "swi"; + break; + default: + instrName = "???"; + state->flow=invalid_instr; + break; + } + } + break; + + /* ARC Extension Library Instructions + NOTE: We assume that extension codes are these instrs. */ + default: + instrName = instruction_name (state, + state->_opcode, + FIELDC (state->words[0]), + &flags); + if (!instrName) + { + instrName = "???"; + state->flow = invalid_instr; + } + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + break; + + case op_BC: + instrName = "b"; + case op_BLC: + if (!instrName) + instrName = "bl"; + case op_LPC: + if (!instrName) + instrName = "lp"; + case op_JC: + if (!instrName) + { + if (BITS (state->words[0],9,9)) + { + instrName = "jl"; + is_linked = 1; + } + else + { + instrName = "j"; + is_linked = 0; + } + } + condCodeIsPartOfName = 1; + decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH ); + state->isBranch = 1; + break; + + case op_ADD: + case op_ADC: + case op_AND: + repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); + + switch (state->_opcode) + { + case op_ADD: + instrName = (repeatsOp ? "asl" : "add"); + break; + case op_ADC: + instrName = (repeatsOp ? "rlc" : "adc"); + break; + case op_AND: + instrName = (repeatsOp ? "mov" : "and"); + break; + } + break; + + case op_SUB: instrName = "sub"; + break; + case op_SBC: instrName = "sbc"; + break; + case op_OR: instrName = "or"; + break; + case op_BIC: instrName = "bic"; + break; + + case op_XOR: + if (state->words[0] == 0x7fffffff) + { + /* NOP encoded as xor -1, -1, -1. */ + instrName = "nop"; + decodingClass = CLASS_A4_OP3_SUBOPC3F; + } + else + instrName = "xor"; + break; + + default: + instrName = instruction_name (state,state->_opcode,0,&flags); + /* if (instrName) printf("FLAGS=0x%x\n", flags); */ + if (!instrName) + { + instrName = "???"; + state->flow=invalid_instr; + } + if (flags & IGNORE_FIRST_OPD) + ignoreFirstOpd = 1; + break; + } + + fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ + flag = cond = is_shimm = is_limm = 0; + state->nullifyMode = BR_exec_when_no_jump; /* 0 */ + signExtend = addrWriteBack = directMem = 0; + usesAuxReg = 0; + + switch (decodingClass) + { + case CLASS_A4_ARITH: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + if (!repeatsOp) + CHECK_FIELD_C (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + WRITE_NOP_COMMENT (); + arc_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + } + else + { + WRITE_FORMAT_x (B); + if (!repeatsOp) + WRITE_FORMAT_COMMA_x (C); + arc_sprintf (state, state->operandBuffer, formatString, + fieldB, fieldC); + } + write_comments (); + break; + + case CLASS_A4_OP3_GENERAL: + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + write_instr_name (); + if (!ignoreFirstOpd) + { + WRITE_FORMAT_x (A); + WRITE_FORMAT_COMMA_x (B); + WRITE_NOP_COMMENT (); + arc_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB); + } + else + { + WRITE_FORMAT_x (B); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); + } + write_comments (); + break; + + case CLASS_A4_FLAG: + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + flag = 0; /* This is the FLAG instruction -- it's redundant. */ + + write_instr_name (); + WRITE_FORMAT_x (B); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); + write_comments (); + break; + + case CLASS_A4_BRANCH: + fieldA = BITS (state->words[0],7,26) << 2; + fieldA = (fieldA << 10) >> 10; /* Make it signed. */ + fieldA += addr + 4; + CHECK_FLAG_COND_NULLIFY (); + flag = 0; + + write_instr_name (); + /* This address could be a label we know. Convert it. */ + if (state->_opcode != op_LPC /* LP */) + { + add_target (fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BLC /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; + lr dest<- func addr; j [dest]" */ + } + + strcat (formatString, "%s"); /* Address/label name. */ + arc_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldA)); + write_comments (); + break; + + case CLASS_A4_JC: + /* For op_JC -- jump to address specified. + Also covers jump and link--bit 9 of the instr. word + selects whether linked, thus "is_linked" is set above. */ + fieldA = 0; + CHECK_FIELD_B (); + CHECK_FLAG_COND_NULLIFY (); + + if (!fieldBisReg) + { + fieldAisReg = 0; + fieldA = (fieldB >> 25) & 0x7F; /* Flags. */ + fieldB = (fieldB & 0xFFFFFF) << 2; + state->flow = is_linked ? direct_call : direct_jump; + add_target (fieldB); + /* Screwy JLcc requires .jd mode to execute correctly + but we pretend it is .nd (no delay slot). */ + if (is_linked && state->nullifyMode == BR_exec_when_jump) + state->nullifyMode = BR_exec_when_no_jump; + } + else + { + state->flow = is_linked ? indirect_call : indirect_jump; + /* We should also treat this as indirect call if NOT linked + but the preceding instruction was a "lr blink,[status]" + and we have a delay slot with "add blink,blink,2". + For now we can't detect such. */ + state->register_for_indirect_jump = fieldB; + } + + write_instr_name (); + strcat (formatString, + IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */ + if (fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x (A); + } + if (IS_REG (B)) + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + else + arc_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldB), fieldA); + write_comments (); + break; + + case CLASS_A4_LD0: + /* LD instruction. + B and C can be regs, or one (both?) can be limm. */ + CHECK_FIELD_A (); + CHECK_FIELD_B (); + CHECK_FIELD_C (); + if (dbg) + printf ("5:b reg %d %d c reg %d %d \n", + fieldBisReg,fieldB,fieldCisReg,fieldC); + state->_offset = 0; + state->_ea_present = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + else + state->_offset += fieldB; + if (fieldCisReg) + state->ea_reg2 = fieldC; + else + state->_offset += fieldC; + state->_mem_load = 1; + + directMem = BIT (state->words[0], 5); + addrWriteBack = BIT (state->words[0], 3); + signExtend = BIT (state->words[0], 0); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB(A); + if (fieldBisReg || fieldB != 0) + WRITE_FORMAT_x_COMMA (B); + else + fieldB = fieldC; + + WRITE_FORMAT_x_RB (C); + arc_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + write_comments (); + break; + + case CLASS_A4_LD1: + /* LD instruction. */ + CHECK_FIELD_B (); + CHECK_FIELD_A (); + fieldC = FIELDD (state->words[0]); + + if (dbg) + printf ("6:b reg %d %d c 0x%x \n", + fieldBisReg, fieldB, fieldC); + state->_ea_present = 1; + state->_offset = fieldC; + state->_mem_load = 1; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* Field B is either a shimm (same as fieldC) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT (state->words[0],14); + addrWriteBack = BIT (state->words[0],12); + signExtend = BIT (state->words[0],9); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB (B); + } + else + { + WRITE_FORMAT_x (B); + if (fieldC != 0 && !BIT (state->words[0],13)) + { + fieldCisReg = 0; + WRITE_FORMAT_COMMA_x_RB (C); + } + else + WRITE_FORMAT_RB (); + } + arc_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); + write_comments (); + break; + + case CLASS_A4_ST: + /* ST instruction. */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + fieldA = FIELDD(state->words[0]); /* shimm */ + + /* [B,A offset] */ + if (dbg) printf("7:b reg %d %x off %x\n", + fieldBisReg,fieldB,fieldA); + state->_ea_present = 1; + state->_offset = fieldA; + if (fieldBisReg) + state->ea_reg1 = fieldB; + /* Field B is either a shimm (same as fieldA) or limm (different!) + Say ea is not present, so only one of us will do the name lookup. + (for is_limm we do the name translation here). */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT (state->words[0], 26); + addrWriteBack = BIT (state->words[0], 24); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB(C); + + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB (B); + } + else + { + WRITE_FORMAT_x (B); + if (fieldBisReg && fieldA != 0) + { + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x_RB(A); + } + else + WRITE_FORMAT_RB(); + } + arc_sprintf (state, state->operandBuffer, formatString, + fieldC, fieldB, fieldA); + write_comments2 (fieldA); + break; + + case CLASS_A4_SR: + /* SR instruction */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB(C); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); + write_comments (); + break; + + case CLASS_A4_OP3_SUBOPC3F: + write_instr_name (); + state->operandBuffer[0] = '\0'; + break; + + case CLASS_A4_LR: + /* LR instruction */ + CHECK_FIELD_A (); + CHECK_FIELD_B (); + + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + write_comments (); + break; + + default: + mwerror (state, "Bad decoding class in ARC disassembler"); + break; + } + + state->_cond = cond; + return state->instructionLen = offset; +} + + +/* Returns the name the user specified core extension register. */ + +static const char * +_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_coreRegName (regval); +} + +/* Returns the name the user specified AUX extension register. */ + +static const char * +_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_auxRegName(regval); +} + +/* Returns the name the user specified condition code name. */ + +static const char * +_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) +{ + return arcExtMap_condCodeName(regval); +} + +/* Returns the name the user specified extension instruction. */ + +static const char * +_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) +{ + return arcExtMap_instName(majop, minop, flags); +} + +/* Decode an instruction returning the size of the instruction + in bytes or zero if unrecognized. */ + +static int +decodeInstr (bfd_vma address, /* Address of this instruction. */ + disassemble_info * info) +{ + int status; + bfd_byte buffer[4]; + struct arcDisState s; /* ARC Disassembler state. */ + void *stream = info->stream; /* Output stream. */ + fprintf_ftype func = info->fprintf_func; + + memset (&s, 0, sizeof(struct arcDisState)); + + /* read first instruction */ + status = (*info->read_memory_func) (address, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, address, info); + return 0; + } + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[0] = bfd_getl32(buffer); + else + s.words[0] = bfd_getb32(buffer); + /* Always read second word in case of limm. */ + + /* We ignore the result since last insn may not have a limm. */ + status = (*info->read_memory_func) (address + 4, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[1] = bfd_getl32(buffer); + else + s.words[1] = bfd_getb32(buffer); + + s._this = &s; + s.coreRegName = _coreRegName; + s.auxRegName = _auxRegName; + s.condCodeName = _condCodeName; + s.instName = _instName; + + /* Disassemble. */ + dsmOneArcInst (address, & s); + + /* Display the disassembly instruction. */ + (*func) (stream, "%08lx ", s.words[0]); + (*func) (stream, " "); + (*func) (stream, "%-10s ", s.instrBuffer); + + if (__TRANSLATION_REQUIRED (s)) + { + bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + + (*info->print_address_func) ((bfd_vma) addr, info); + (*func) (stream, "\n"); + } + else + (*func) (stream, "%s",s.operandBuffer); + + return s.instructionLen; +} + +/* Return the print_insn function to use. + Side effect: load (possibly empty) extension section */ + +disassembler_ftype +arc_get_disassembler (void *ptr) +{ + if (ptr) + build_ARC_extmap ((struct bfd *) ptr); + return decodeInstr; +} diff --git a/external/gpl3/gdb/dist/opcodes/arc-dis.h b/external/gpl3/gdb/dist/opcodes/arc-dis.h new file mode 100644 index 000000000000..33445322b161 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arc-dis.h @@ -0,0 +1,83 @@ +/* Disassembler structures definitions for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2005, 2007 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef ARCDIS_H +#define ARCDIS_H + +enum +{ + BR_exec_when_no_jump, + BR_exec_always, + BR_exec_when_jump +}; + +enum Flow +{ + noflow, + direct_jump, + direct_call, + indirect_jump, + indirect_call, + invalid_instr +}; + +enum { no_reg = 99 }; +enum { allOperandsSize = 256 }; + +struct arcDisState +{ + void *_this; + int instructionLen; + void (*err)(void*, const char*); + const char *(*coreRegName)(void*, int); + const char *(*auxRegName)(void*, int); + const char *(*condCodeName)(void*, int); + const char *(*instName)(void*, int, int, int*); + + unsigned char* instruction; + unsigned index; + const char *comm[6]; /* instr name, cond, NOP, 3 operands */ + int opWidth; + int targets[4]; + int addresses[4]; + /* Set as a side-effect of calling the disassembler. + Used only by the debugger. */ + enum Flow flow; + int register_for_indirect_jump; + int ea_reg1, ea_reg2, _offset; + int _cond, _opcode; + unsigned long words[2]; + char *commentBuffer; + char instrBuffer[40]; + char operandBuffer[allOperandsSize]; + char _ea_present; + char _mem_load; + char _load_len; + char nullifyMode; + unsigned char commNum; + unsigned char isBranch; + unsigned char tcnt; + unsigned char acnt; +}; + +#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) + +#endif diff --git a/external/gpl3/gdb/dist/opcodes/arc-ext.c b/external/gpl3/gdb/dist/opcodes/arc-ext.c new file mode 100644 index 000000000000..376cd0316e3d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arc-ext.c @@ -0,0 +1,262 @@ +/* ARC target-dependent stuff. Extension structure access functions + Copyright 1995, 1997, 2000, 2001, 2004, 2005, 2007, 2009 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include +#include "bfd.h" +#include "arc-ext.h" +#include "libiberty.h" + +/* Extension structure */ +static struct arcExtMap arc_extension_map; + +/* Get the name of an extension instruction. */ + +const char * +arcExtMap_instName(int opcode, int minor, int *flags) +{ + if (opcode == 3) + { + /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ + if (minor < 0x09 || minor == 0x3f) + return 0; + else + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + } + else + if (opcode < 0x10) + return 0; + else + opcode -= 0x10; + if (!arc_extension_map.instructions[opcode]) + return 0; + *flags = arc_extension_map.instructions[opcode]->flags; + return arc_extension_map.instructions[opcode]->name; +} + +/* Get the name of an extension core register. */ + +const char * +arcExtMap_coreRegName(int value) +{ + if (value < 32) + return 0; + return arc_extension_map.coreRegisters[value-32]; +} + +/* Get the name of an extension condition code. */ + +const char * +arcExtMap_condCodeName(int value) +{ + if (value < 16) + return 0; + return arc_extension_map.condCodes[value-16]; +} + +/* Get the name of an extension aux register. */ + +const char * +arcExtMap_auxRegName(long address) +{ + /* walk the list of aux reg names and find the name */ + struct ExtAuxRegister *r; + + for (r = arc_extension_map.auxRegisters; r; r = r->next) { + if (r->address == address) + return (const char *) r->name; + } + return 0; +} + +/* Recursively free auxilliary register strcture pointers until + the list is empty. */ + +static void +clean_aux_registers(struct ExtAuxRegister *r) +{ + if (r -> next) + { + clean_aux_registers( r->next); + free(r -> name); + free(r -> next); + r ->next = NULL; + } + else + free(r -> name); +} + +/* Free memory that has been allocated for the extensions. */ + +static void +cleanup_ext_map(void) +{ + struct ExtAuxRegister *r; + struct ExtInstruction *insn; + int i; + + /* clean aux reg structure */ + r = arc_extension_map.auxRegisters; + if (r) + { + (clean_aux_registers(r)); + free(r); + } + + /* clean instructions */ + for (i = 0; i < NUM_EXT_INST; i++) + { + insn = arc_extension_map.instructions[i]; + if (insn) + free(insn->name); + } + + /* clean core reg struct */ + for (i = 0; i < NUM_EXT_CORE; i++) + { + if (arc_extension_map.coreRegisters[i]) + free(arc_extension_map.coreRegisters[i]); + } + + for (i = 0; i < NUM_EXT_COND; i++) { + if (arc_extension_map.condCodes[i]) + free(arc_extension_map.condCodes[i]); + } + + memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); +} + +int +arcExtMap_add(void *base, unsigned long length) +{ + unsigned char *block = (unsigned char *) base; + unsigned char *p = (unsigned char *) block; + + /* Clean up and reset everything if needed. */ + cleanup_ext_map(); + + while (p && p < (block + length)) + { + /* p[0] == length of record + p[1] == type of record + For instructions: + p[2] = opcode + p[3] = minor opcode (if opcode == 3) + p[4] = flags + p[5]+ = name + For core regs and condition codes: + p[2] = value + p[3]+ = name + For aux regs: + p[2..5] = value + p[6]+ = name + (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ + + if (p[0] == 0) + return -1; + + switch (p[1]) + { + case EXT_INSTRUCTION: + { + char opcode = p[2]; + char minor = p[3]; + char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); + struct ExtInstruction * insn = + (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); + + if (opcode==3) + opcode = 0x1f - 0x10 + minor - 0x09 + 1; + else + opcode -= 0x10; + insn -> flags = (char) *(p+4); + strcpy (insn_name, (char *) (p+5)); + insn -> name = insn_name; + arc_extension_map.instructions[(int) opcode] = insn; + } + break; + + case EXT_CORE_REGISTER: + { + char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); + + strcpy(core_name, (char *) (p+3)); + arc_extension_map.coreRegisters[p[2]-32] = core_name; + } + break; + + case EXT_COND_CODE: + { + char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); + strcpy(cc_name, (char *) (p+3)); + arc_extension_map.condCodes[p[2]-16] = cc_name; + } + break; + + case EXT_AUX_REGISTER: + { + /* trickier -- need to store linked list to these */ + struct ExtAuxRegister *newAuxRegister = + (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); + char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); + + strcpy (aux_name, (char *) (p+6)); + newAuxRegister->name = aux_name; + newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; + newAuxRegister->next = arc_extension_map.auxRegisters; + arc_extension_map.auxRegisters = newAuxRegister; + } + break; + + default: + return -1; + + } + p += p[0]; /* move to next record */ + } + + return 0; +} + +/* Load hw extension descibed in .extArcMap ELF section. */ + +void +build_ARC_extmap (text_bfd) + bfd *text_bfd; +{ + char *arcExtMap; + bfd_size_type count; + asection *p; + + for (p = text_bfd->sections; p != NULL; p = p->next) + if (!strcmp (p->name, ".arcextmap")) + { + count = bfd_get_section_size (p); + arcExtMap = (char *) xmalloc (count); + if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) + { + arcExtMap_add ((PTR) arcExtMap, count); + break; + } + free ((PTR) arcExtMap); + } +} diff --git a/external/gpl3/gdb/dist/opcodes/arc-ext.h b/external/gpl3/gdb/dist/opcodes/arc-ext.h new file mode 100644 index 000000000000..8a0deab0c477 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arc-ext.h @@ -0,0 +1,63 @@ +/* ARC target-dependent stuff. Extension data structures. + Copyright 1995, 1997, 2000, 2001, 2005, 2007 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef ARCEXT_H +#define ARCEXT_H + +enum {EXT_INSTRUCTION = 0, + EXT_CORE_REGISTER = 1, + EXT_AUX_REGISTER = 2, + EXT_COND_CODE = 3}; + +enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; +enum {NUM_EXT_CORE = 59-32+1}; +enum {NUM_EXT_COND = 0x1f-0x10+1}; + +struct ExtInstruction +{ + char flags; + char *name; +}; + +struct ExtAuxRegister +{ + long address; + char *name; + struct ExtAuxRegister *next; +}; + +struct arcExtMap +{ + struct ExtAuxRegister *auxRegisters; + struct ExtInstruction *instructions[NUM_EXT_INST]; + char *coreRegisters[NUM_EXT_CORE]; + char *condCodes[NUM_EXT_COND]; +}; + +extern int arcExtMap_add(void*, unsigned long); +extern const char *arcExtMap_coreRegName(int); +extern const char *arcExtMap_auxRegName(long); +extern const char *arcExtMap_condCodeName(int); +extern const char *arcExtMap_instName(int, int, int*); +extern void build_ARC_extmap(bfd *); + +#define IGNORE_FIRST_OPD 1 + +#endif diff --git a/external/gpl3/gdb/dist/opcodes/arc-opc.c b/external/gpl3/gdb/dist/opcodes/arc-opc.c new file mode 100644 index 000000000000..2a5ae712afec --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arc-opc.c @@ -0,0 +1,1763 @@ +/* Opcode table for the ARC. + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004, 2005, 2007 + Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "opcode/arc.h" +#include "opintl.h" + +enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; + +#define OPERANDS 3 + +enum operand ls_operand[OPERANDS]; + +struct arc_opcode *arc_ext_opcodes; +struct arc_ext_operand_value *arc_ext_operands; + +#define LS_VALUE 0 +#define LS_DEST 0 +#define LS_BASE 1 +#define LS_OFFSET 2 + +/* Given a format letter, yields the index into `arc_operands'. + eg: arc_operand_map['a'] = REGA. */ +unsigned char arc_operand_map[256]; + +/* Nonzero if we've seen an 'f' suffix (in certain insns). */ +static int flag_p; + +/* Nonzero if we've finished processing the 'f' suffix. */ +static int flagshimm_handled_p; + +/* Nonzero if we've seen a 'a' suffix (address writeback). */ +static int addrwb_p; + +/* Nonzero if we've seen a 'q' suffix (condition code). */ +static int cond_p; + +/* Nonzero if we've inserted a nullify condition. */ +static int nullify_p; + +/* The value of the a nullify condition we inserted. */ +static int nullify; + +/* Nonzero if we've inserted jumpflags. */ +static int jumpflags_p; + +/* Nonzero if we've inserted a shimm. */ +static int shimm_p; + +/* The value of the shimm we inserted (each insn only gets one but it can + appear multiple times). */ +static int shimm; + +/* Nonzero if we've inserted a limm (during assembly) or seen a limm + (during disassembly). */ +static int limm_p; + +/* The value of the limm we inserted. Each insn only gets one but it can + appear multiple times. */ +static long limm; + +#define INSERT_FN(fn) \ +static arc_insn fn (arc_insn, const struct arc_operand *, \ + int, const struct arc_operand_value *, long, \ + const char **) + +#define EXTRACT_FN(fn) \ +static long fn (arc_insn *, const struct arc_operand *, \ + int, const struct arc_operand_value **, int *) + +INSERT_FN (insert_reg); +INSERT_FN (insert_shimmfinish); +INSERT_FN (insert_limmfinish); +INSERT_FN (insert_offset); +INSERT_FN (insert_base); +INSERT_FN (insert_st_syntax); +INSERT_FN (insert_ld_syntax); +INSERT_FN (insert_addr_wb); +INSERT_FN (insert_flag); +INSERT_FN (insert_nullify); +INSERT_FN (insert_flagfinish); +INSERT_FN (insert_cond); +INSERT_FN (insert_forcelimm); +INSERT_FN (insert_reladdr); +INSERT_FN (insert_absaddr); +INSERT_FN (insert_jumpflags); +INSERT_FN (insert_unopmacro); + +EXTRACT_FN (extract_reg); +EXTRACT_FN (extract_ld_offset); +EXTRACT_FN (extract_ld_syntax); +EXTRACT_FN (extract_st_offset); +EXTRACT_FN (extract_st_syntax); +EXTRACT_FN (extract_flag); +EXTRACT_FN (extract_cond); +EXTRACT_FN (extract_reladdr); +EXTRACT_FN (extract_jumpflags); +EXTRACT_FN (extract_unopmacro); + +/* Various types of ARC operands, including insn suffixes. */ + +/* Insn format values: + + 'a' REGA register A field + 'b' REGB register B field + 'c' REGC register C field + 'S' SHIMMFINISH finish inserting a shimm value + 'L' LIMMFINISH finish inserting a limm value + 'o' OFFSET offset in st insns + 'O' OFFSET offset in ld insns + '0' SYNTAX_ST_NE enforce store insn syntax, no errors + '1' SYNTAX_LD_NE enforce load insn syntax, no errors + '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only + '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only + 's' BASE base in st insn + 'f' FLAG F flag + 'F' FLAGFINISH finish inserting the F flag + 'G' FLAGINSN insert F flag in "flag" insn + 'n' DELAY N field (nullify field) + 'q' COND condition code field + 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm + 'B' BRANCH branch address (22 bit pc relative) + 'J' JUMP jump address (26 bit absolute) + 'j' JUMPFLAGS optional high order bits of 'J' + 'z' SIZE1 size field in ld a,[b,c] + 'Z' SIZE10 size field in ld a,[b,shimm] + 'y' SIZE22 size field in st c,[b,shimm] + 'x' SIGN0 sign extend field ld a,[b,c] + 'X' SIGN9 sign extend field ld a,[b,shimm] + 'w' ADDRESS3 write-back field in ld a,[b,c] + 'W' ADDRESS12 write-back field in ld a,[b,shimm] + 'v' ADDRESS24 write-back field in st c,[b,shimm] + 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] + 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] + 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] + 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros + + The following modifiers may appear between the % and char (eg: %.f): + + '.' MODDOT '.' prefix must be present + 'r' REG generic register value, for register table + 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] + + Fields are: + + CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ + +const struct arc_operand arc_operands[] = +{ +/* Place holder (??? not sure if needed). */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, 0 }, + +/* Register A or shimm/limm indicator. */ +#define REGA (UNUSED + 1) + { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* Register B or shimm/limm indicator. */ +#define REGB (REGA + 1) + { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* Register C or shimm/limm indicator. */ +#define REGC (REGB + 1) + { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, + +/* Fake operand used to insert shimm value into most instructions. */ +#define SHIMMFINISH (REGC + 1) + { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, + +/* Fake operand used to insert limm value into most instructions. */ +#define LIMMFINISH (SHIMMFINISH + 1) + { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, + +/* Shimm operand when there is no reg indicator (st). */ +#define ST_OFFSET (LIMMFINISH + 1) + { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, + +/* Shimm operand when there is no reg indicator (ld). */ +#define LD_OFFSET (ST_OFFSET + 1) + { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, + +/* Operand for base. */ +#define BASE (LD_OFFSET + 1) + { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, + +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST_NE (BASE + 1) + { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, + +/* 1 enforce syntax for ld insns. */ +#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) + { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, + +/* 0 enforce syntax for st insns. */ +#define SYNTAX_ST (SYNTAX_LD_NE + 1) + { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, + +/* 0 enforce syntax for ld insns. */ +#define SYNTAX_LD (SYNTAX_ST + 1) + { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, + +/* Flag update bit (insertion is defered until we know how). */ +#define FLAG (SYNTAX_LD + 1) + { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, + +/* Fake utility operand to finish 'f' suffix handling. */ +#define FLAGFINISH (FLAG + 1) + { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, + +/* Fake utility operand to set the 'f' flag for the "flag" insn. */ +#define FLAGINSN (FLAGFINISH + 1) + { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, + +/* Branch delay types. */ +#define DELAY (FLAGINSN + 1) + { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, + +/* Conditions. */ +#define COND (DELAY + 1) + { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, + +/* Set `cond_p' to 1 to ensure a constant is treated as a limm. */ +#define FORCELIMM (COND + 1) + { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, + +/* Branch address; b, bl, and lp insns. */ +#define BRANCH (FORCELIMM + 1) + { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, + +/* Jump address; j insn (this is basically the same as 'L' except that the + value is right shifted by 2). */ +#define JUMP (BRANCH + 1) + { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, + +/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ +#define JUMPFLAGS (JUMP + 1) + { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, + +/* Size field, stored in bit 1,2. */ +#define SIZE1 (JUMPFLAGS + 1) + { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Size field, stored in bit 10,11. */ +#define SIZE10 (SIZE1 + 1) + { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Size field, stored in bit 22,23. */ +#define SIZE22 (SIZE10 + 1) + { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Sign extend field, stored in bit 0. */ +#define SIGN0 (SIZE22 + 1) + { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Sign extend field, stored in bit 9. */ +#define SIGN9 (SIGN0 + 1) + { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Address write back, stored in bit 3. */ +#define ADDRESS3 (SIGN9 + 1) + { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* Address write back, stored in bit 12. */ +#define ADDRESS12 (ADDRESS3 + 1) + { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* Address write back, stored in bit 24. */ +#define ADDRESS24 (ADDRESS12 + 1) + { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, + +/* Cache bypass, stored in bit 5. */ +#define CACHEBYPASS5 (ADDRESS24 + 1) + { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Cache bypass, stored in bit 14. */ +#define CACHEBYPASS14 (CACHEBYPASS5 + 1) + { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Cache bypass, stored in bit 26. */ +#define CACHEBYPASS26 (CACHEBYPASS14 + 1) + { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, + +/* Unop macro, used to copy REGB to REGC. */ +#define UNOPMACRO (CACHEBYPASS26 + 1) + { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, + +/* '.' modifier ('.' required). */ +#define MODDOT (UNOPMACRO + 1) + { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, + +/* Dummy 'r' modifier for the register table. + It's called a "dummy" because there's no point in inserting an 'r' into all + the %a/%b/%c occurrences in the insn table. */ +#define REG (MODDOT + 1) + { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, + +/* Known auxiliary register modifier (stored in shimm field). */ +#define AUXREG (REG + 1) + { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, + +/* End of list place holder. */ + { 0, 0, 0, 0, 0, 0 } +}; + +/* Insert a value into a register field. + If REG is NULL, then this is actually a constant. + + We must also handle auxiliary registers for lr/sr insns. */ + +static arc_insn +insert_reg (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) +{ + static char buf[100]; + enum operand op_type = OP_NONE; + + if (reg == NULL) + { + /* We have a constant that also requires a value stored in a register + field. Handle these by updating the register field and saving the + value for later handling by either %S (shimm) or %L (limm). */ + + /* Try to use a shimm value before a limm one. */ + if (ARC_SHIMM_CONST_P (value) + /* If we've seen a conditional suffix we have to use a limm. */ + && !cond_p + /* If we already have a shimm value that is different than ours + we have to use a limm. */ + && (!shimm_p || shimm == value)) + { + int marker; + + op_type = OP_SHIMM; + /* Forget about shimm as dest mlm. */ + + if ('a' != operand->fmt) + { + shimm_p = 1; + shimm = value; + flagshimm_handled_p = 1; + marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; + } + else + { + /* Don't request flag setting on shimm as dest. */ + marker = ARC_REG_SHIMM; + } + insn |= marker << operand->shift; + /* insn |= value & 511; - done later. */ + } + /* We have to use a limm. If we've already seen one they must match. */ + else if (!limm_p || limm == value) + { + op_type = OP_LIMM; + limm_p = 1; + limm = value; + insn |= ARC_REG_LIMM << operand->shift; + /* The constant is stored later. */ + } + else + *errmsg = _("unable to fit different valued constants into instruction"); + } + else + { + /* We have to handle both normal and auxiliary registers. */ + + if (reg->type == AUXREG) + { + if (!(mods & ARC_MOD_AUXREG)) + *errmsg = _("auxiliary register not allowed here"); + else + { + if ((insn & I(-1)) == I(2)) /* Check for use validity. */ + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = _("attempt to set readonly register"); + } + else + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = _("attempt to read writeonly register"); + } + insn |= ARC_REG_SHIMM << operand->shift; + insn |= reg->value << arc_operands[reg->type].shift; + } + } + else + { + /* check for use validity. */ + if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = _("attempt to set readonly register"); + } + if ('a' != operand->fmt) + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = _("attempt to read writeonly register"); + } + /* We should never get an invalid register number here. */ + if ((unsigned int) reg->value > 60) + { + sprintf (buf, _("invalid register number `%d'"), reg->value); + *errmsg = buf; + } + insn |= reg->value << operand->shift; + op_type = OP_REG; + } + } + + switch (operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn & I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + + return insn; +} + +/* Called when we see an 'f' flag. */ + +static arc_insn +insert_flag (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + /* We can't store anything in the insn until we've parsed the registers. + Just record the fact that we've got this flag. `insert_reg' will use it + to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ + flag_p = 1; + return insn; +} + +/* Called when we see an nullify condition. */ + +static arc_insn +insert_nullify (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + nullify_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + nullify = value; + return insn; +} + +/* Called after completely building an insn to ensure the 'f' flag gets set + properly. This is needed because we don't know how to set this flag until + we've parsed the registers. */ + +static arc_insn +insert_flagfinish (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (flag_p && !flagshimm_handled_p) + { + if (shimm_p) + abort (); + flagshimm_handled_p = 1; + insn |= (1 << operand->shift); + } + return insn; +} + +/* Called when we see a conditional flag (eg: .eq). */ + +static arc_insn +insert_cond (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + cond_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Used in the "j" instruction to prevent constants from being interpreted as + shimm values (which the jump insn doesn't accept). This can also be used + to force the use of limm values in other situations (eg: ld r0,[foo] uses + this). + ??? The mechanism is sound. Access to it is a bit klunky right now. */ + +static arc_insn +insert_forcelimm (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + cond_p = 1; + return insn; +} + +static arc_insn +insert_addr_wb (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + addrwb_p = 1 << operand->shift; + return insn; +} + +static arc_insn +insert_base (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) +{ + if (reg != NULL) + { + arc_insn myinsn; + myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; + insn |= B(myinsn); + ls_operand[LS_BASE] = OP_REG; + } + else if (ARC_SHIMM_CONST_P (value) && !cond_p) + { + if (shimm_p && value != shimm) + { + /* Convert the previous shimm operand to a limm. */ + limm_p = 1; + limm = shimm; + insn &= ~C(-1); /* We know where the value is in insn. */ + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + insn |= ARC_REG_SHIMM << operand->shift; + shimm_p = 1; + shimm = value; + ls_operand[LS_BASE] = OP_SHIMM; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + else + { + if (limm_p && value != limm) + { + *errmsg = _("too many long constants"); + return insn; + } + limm_p = 1; + limm = value; + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + + return insn; +} + +/* Used in ld/st insns to handle the offset field. We don't try to + match operand syntax here. we catch bad combinations later. */ + +static arc_insn +insert_offset (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) +{ + long minval, maxval; + + if (reg != NULL) + { + arc_insn myinsn; + myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; + ls_operand[LS_OFFSET] = OP_REG; + if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */ + if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */ + insn |= C (myinsn); + } + else + { + /* This is *way* more general than necessary, but maybe some day it'll + be useful. */ + if (operand->flags & ARC_OPERAND_SIGNED) + { + minval = -(1 << (operand->bits - 1)); + maxval = (1 << (operand->bits - 1)) - 1; + } + else + { + minval = 0; + maxval = (1 << operand->bits) - 1; + } + if ((cond_p && !limm_p) || (value < minval || value > maxval)) + { + if (limm_p && value != limm) + *errmsg = _("too many long constants"); + + else + { + limm_p = 1; + limm = value; + if (operand->flags & ARC_OPERAND_STORE) + insn |= B(ARC_REG_LIMM); + if (operand->flags & ARC_OPERAND_LOAD) + insn |= C(ARC_REG_LIMM); + ls_operand[LS_OFFSET] = OP_LIMM; + } + } + else + { + if ((value < minval || value > maxval)) + *errmsg = "need too many limms"; + else if (shimm_p && value != shimm) + { + /* Check for bad operand combinations + before we lose info about them. */ + if ((insn & I(-1)) == I(1)) + { + *errmsg = _("too many shimms in load"); + goto out; + } + if (limm_p && operand->flags & ARC_OPERAND_LOAD) + { + *errmsg = _("too many long constants"); + goto out; + } + /* Convert what we thought was a shimm to a limm. */ + limm_p = 1; + limm = shimm; + if (ls_operand[LS_VALUE] == OP_SHIMM + && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~C(-1); + insn |= C(ARC_REG_LIMM); + ls_operand[LS_VALUE] = OP_LIMM; + } + if (ls_operand[LS_BASE] == OP_SHIMM + && operand->flags & ARC_OPERAND_STORE) + { + insn &= ~B(-1); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + } + shimm = value; + shimm_p = 1; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } + out: + return insn; +} + +/* Used in st insns to do final disasemble syntax check. */ + +static long +extract_st_syntax (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ +#define ST_SYNTAX(V,B,O) \ +((ls_operand[LS_VALUE] == (V) && \ + ls_operand[LS_BASE] == (B) && \ + ls_operand[LS_OFFSET] == (O))) + + if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) + || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) + || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) + || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) + *invalid = 1; + return 0; +} + +int +arc_limm_fixup_adjust (arc_insn insn) +{ + int retval = 0; + + /* Check for st shimm,[limm]. */ + if ((insn & (I(-1) | C(-1) | B(-1))) == + (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) + { + retval = insn & 0x1ff; + if (retval & 0x100) /* Sign extend 9 bit offset. */ + retval |= ~0x1ff; + } + return -retval; /* Negate offset for return. */ +} + +/* Used in st insns to do final syntax check. */ + +static arc_insn +insert_st_syntax (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) + { + /* Change an illegal insn into a legal one, it's easier to + do it here than to try to handle it during operand scan. */ + limm_p = 1; + limm = shimm; + shimm_p = 0; + shimm = 0; + insn = insn & ~(C(-1) | 511); + insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; + ls_operand[LS_VALUE] = OP_LIMM; + } + + if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) + || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE)) + { + /* Try to salvage this syntax. */ + if (shimm & 0x1) /* Odd shimms won't work. */ + { + if (limm_p) /* Do we have a limm already? */ + *errmsg = _("impossible store"); + + limm_p = 1; + limm = shimm; + shimm = 0; + shimm_p = 0; + insn = insn & ~(B(-1) | 511); + insn |= B(ARC_REG_LIMM); + ls_operand[LS_BASE] = OP_LIMM; + } + else + { + shimm >>= 1; + insn = insn & ~511; + insn |= shimm; + ls_operand[LS_OFFSET] = OP_SHIMM; + } + } + if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) + limm += arc_limm_fixup_adjust(insn); + + if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE) + || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE) + || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) + || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) + || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE) + || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM))) + *errmsg = _("st operand error"); + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = _("address writeback not allowed"); + insn |= addrwb_p; + } + if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) + *errmsg = _("store value must be zero"); + return insn; +} + +/* Used in ld insns to do final syntax check. */ + +static arc_insn +insert_ld_syntax (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) +{ +#define LD_SYNTAX(D, B, O) \ + ( (ls_operand[LS_DEST] == (D) \ + && ls_operand[LS_BASE] == (B) \ + && ls_operand[LS_OFFSET] == (O))) + + int test = insn & I (-1); + + if (!(test == I (1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *errmsg = _("invalid load/shimm insn"); + } + if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) + || LD_SYNTAX(OP_REG,OP_REG,OP_REG) + || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) + || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) + || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) + || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + *errmsg = _("ld operand error"); + if (addrwb_p) + { + if (ls_operand[LS_BASE] != OP_REG) + *errmsg = _("address writeback not allowed"); + insn |= addrwb_p; + } + return insn; +} + +/* Used in ld insns to do final syntax check. */ + +static long +extract_ld_syntax (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + int test = insn[0] & I(-1); + + if (!(test == I(1))) + { + if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM + || ls_operand[LS_OFFSET] == OP_SHIMM)) + *invalid = 1; + } + if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1))) + || LD_SYNTAX (OP_REG, OP_REG, OP_REG) + || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) + || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1))) + || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1))) + || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0)) + || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) + || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1))))) + *invalid = 1; + return 0; +} + +/* Called at the end of processing normal insns (eg: add) to insert a shimm + value (if present) into the insn. */ + +static arc_insn +insert_shimmfinish (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (shimm_p) + insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Called at the end of processing normal insns (eg: add) to insert a limm + value (if present) into the insn. + + Note that this function is only intended to handle instructions (with 4 byte + immediate operands). It is not intended to handle data. */ + +/* ??? Actually, there's nothing for us to do as we can't call frag_more, the + caller must do that. The extract fns take a pointer to two words. The + insert fns could be converted and then we could do something useful, but + then the reloc handlers would have to know to work on the second word of + a 2 word quantity. That's too much so we don't handle them. */ + +static arc_insn +insert_limmfinish (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn; +} + +static arc_insn +insert_jumpflags (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg) +{ + if (!flag_p) + *errmsg = _("jump flags, but no .f seen"); + + else if (!limm_p) + *errmsg = _("jump flags, but no limm addr"); + + else if (limm & 0xfc000000) + *errmsg = _("flag bits of jump address limm lost"); + + else if (limm & 0x03000000) + *errmsg = _("attempt to set HR bits"); + + else if ((value & ((1 << operand->bits) - 1)) != value) + *errmsg = _("bad jump flags value"); + + jumpflags_p = 1; + limm = ((limm & ((1 << operand->shift) - 1)) + | ((value & ((1 << operand->bits) - 1)) << operand->shift)); + return insn; +} + +/* Called at the end of unary operand macros to copy the B field to C. */ + +static arc_insn +insert_unopmacro (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; + return insn; +} + +/* Insert a relative address for a branch insn (b, bl, or lp). */ + +static arc_insn +insert_reladdr (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg) +{ + if (value & 3) + *errmsg = _("branch address not on 4 byte boundary"); + insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; + return insn; +} + +/* Insert a limm value as a 26 bit address right shifted 2 into the insn. + + Note that this function is only intended to handle instructions (with 4 byte + immediate operands). It is not intended to handle data. */ + +/* ??? Actually, there's little for us to do as we can't call frag_more, the + caller must do that. The extract fns take a pointer to two words. The + insert fns could be converted and then we could do something useful, but + then the reloc handlers would have to know to work on the second word of + a 2 word quantity. That's too much so we don't handle them. + + We do check for correct usage of the nullify suffix, or we + set the default correctly, though. */ + +static arc_insn +insert_absaddr (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (limm_p) + { + /* If it is a jump and link, .jd must be specified. */ + if (insn & R (-1, 9, 1)) + { + if (!nullify_p) + insn |= 0x02 << 5; /* Default nullify to .jd. */ + + else if (nullify != 0x02) + *errmsg = _("must specify .jd or no nullify suffix"); + } + } + return insn; +} + +/* Extraction functions. + + The suffix extraction functions' return value is redundant since it can be + obtained from (*OPVAL)->value. However, the boolean suffixes don't have + a suffix table entry for the "false" case, so values of zero must be + obtained from the return value (*OPVAL == NULL). */ + +/* Called by the disassembler before printing an instruction. */ + +void +arc_opcode_init_extract (void) +{ + arc_opcode_init_insert (); +} + +static const struct arc_operand_value * +lookup_register (int type, long regno) +{ + const struct arc_operand_value *r,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (ext_oper->operand.type == type && ext_oper->operand.value == regno) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } + + if (type == REG) + return &arc_reg_names[regno]; + + /* ??? This is a little slow and can be speeded up. */ + for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; + r < end; ++r) + if (type == r->type && regno == r->value) + return r; + return 0; +} + +/* As we're extracting registers, keep an eye out for the 'f' indicator + (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, + like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. + + We must also handle auxiliary registers for lr/sr insns. They are just + constants with special names. */ + +static long +extract_reg (arc_insn *insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) +{ + int regno; + long value; + enum operand op_type; + + /* Get the register number. */ + regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + + /* Is it a constant marker? */ + if (regno == ARC_REG_SHIMM) + { + op_type = OP_SHIMM; + /* Always return zero if dest is a shimm mlm. */ + + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) + && (value & 256)) + value -= 512; + if (!flagshimm_handled_p) + flag_p = 0; + flagshimm_handled_p = 1; + } + else + value = 0; + } + else if (regno == ARC_REG_SHIMM_UPDATE) + { + op_type = OP_SHIMM; + + /* Always return zero if dest is a shimm mlm. */ + if ('a' != operand->fmt) + { + value = *insn & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + } + else + value = 0; + + flag_p = 1; + flagshimm_handled_p = 1; + } + else if (regno == ARC_REG_LIMM) + { + op_type = OP_LIMM; + value = insn[1]; + limm_p = 1; + + /* If this is a jump instruction (j,jl), show new pc correctly. */ + if (0x07 == ((*insn & I(-1)) >> 27)) + value = (value & 0xffffff); + } + + /* It's a register, set OPVAL (that's the only way we distinguish registers + from constants here). */ + else + { + const struct arc_operand_value *reg = lookup_register (REG, regno); + + op_type = OP_REG; + + if (reg == NULL) + abort (); + if (opval != NULL) + *opval = reg; + value = regno; + } + + /* If this field takes an auxiliary register, see if it's a known one. */ + if ((mods & ARC_MOD_AUXREG) + && ARC_REG_CONSTANT_P (regno)) + { + const struct arc_operand_value *reg = lookup_register (AUXREG, value); + + /* This is really a constant, but tell the caller it has a special + name. */ + if (reg != NULL && opval != NULL) + *opval = reg; + } + + switch(operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn[0]& I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + + return value; +} + +/* Return the value of the "flag update" field for shimm insns. + This value is actually stored in the register field. */ + +static long +extract_flag (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) +{ + int f; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + f = flag_p != 0; + else + f = (*insn & (1 << operand->shift)) != 0; + + /* There is no text for zero values. */ + if (f == 0) + return 0; + flag_p = 1; + val = arc_opcode_lookup_suffix (operand, 1); + if (opval != NULL && val != NULL) + *opval = val; + return val->value; +} + +/* Extract the condition code (if it exists). + If we've seen a shimm value in this insn (meaning that the insn can't have + a condition code field), then we don't store anything in OPVAL and return + zero. */ + +static long +extract_cond (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) +{ + long cond; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + return 0; + + cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + val = arc_opcode_lookup_suffix (operand, cond); + + /* Ignore NULL values of `val'. Several condition code values are + reserved for extensions. */ + if (opval != NULL && val != NULL) + *opval = val; + return cond; +} + +/* Extract a branch address. + We return the value as a real address (not right shifted by 2). */ + +static long +extract_reladdr (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long addr; + + addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & ARC_OPERAND_SIGNED) + && (addr & (1 << (operand->bits - 1)))) + addr -= 1 << operand->bits; + return addr << 2; +} + +/* Extract the flags bits from a j or jl long immediate. */ + +static long +extract_jumpflags (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + if (!flag_p || !limm_p) + *invalid = 1; + return ((flag_p && limm_p) + ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); +} + +/* Extract st insn's offset. */ + +static long +extract_st_offset (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + int value = 0; + + if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + } + else + *invalid = 1; + + return value; +} + +/* Extract ld insn's offset. */ + +static long +extract_ld_offset (arc_insn *insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value **opval, + int *invalid) +{ + int test = insn[0] & I(-1); + int value; + + if (test) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + + return value; + } + /* If it isn't in the insn, it's concealed behind reg 'c'. */ + return extract_reg (insn, &arc_operands[arc_operand_map['c']], + mods, opval, invalid); +} + +/* The only thing this does is set the `invalid' flag if B != C. + This is needed because the "mov" macro appears before it's real insn "and" + and we don't want the disassembler to confuse them. */ + +static long +extract_unopmacro (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + /* This misses the case where B == ARC_REG_SHIMM_UPDATE && + C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get + printed as "and"s. */ + if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) + != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) + if (invalid != NULL) + *invalid = 1; + return 0; +} + +/* ARC instructions. + + Longer versions of insns must appear before shorter ones (if gas sees + "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is + junk). This isn't necessary for `ld' because of the trailing ']'. + + Instructions that are really macros based on other insns must appear + before the real insn so they're chosen when disassembling. Eg: The `mov' + insn is really the `and' insn. */ + +struct arc_opcode arc_opcodes[] = +{ + /* Base case instruction set (core versions 5-8). */ + + /* "mov" is really an "and". */ + { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, + /* "asl" is really an "add". */ + { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "lsl" is really an "add". */ + { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "nop" is really an "xor". */ + { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, + /* "rlc" is really an "adc". */ + { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, + { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, + { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, + { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, + { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, + { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, + { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, + { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, + { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, + { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, + /* %Q: force cond_p=1 -> no shimm values. This insn allows an + optional flags spec. */ + { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* This insn allows an optional flags spec. */ + { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* Put opcode 1 ld insns first so shimm gets prefered over limm. + "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, + { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, + { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, + { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, + { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, + { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, + { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, + { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, + { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, + { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, + { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, + /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, + { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } +}; + +const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); + +const struct arc_operand_value arc_reg_names[] = +{ + /* Core register set r0-r63. */ + + /* r0-r28 - general purpose registers. */ + { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, + { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, + { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, + { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, + { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, + { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, + { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, + { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, + { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, + { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink1", 29, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink2", 30, REG, 0 }, + /* Branch-link register. */ + { "blink", 31, REG, 0 }, + + /* r32-r59 reserved for extensions. */ + { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, + { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, + { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, + { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, + { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, + { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, + { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, + { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, + { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, + { "r59", 59, REG, 0 }, + + /* Loop count register (24 bits). */ + { "lp_count", 60, REG, 0 }, + /* Short immediate data indicator setting flags. */ + { "r61", 61, REG, ARC_REGISTER_READONLY }, + /* Long immediate data indicator setting flags. */ + { "r62", 62, REG, ARC_REGISTER_READONLY }, + /* Short immediate data indicator not setting flags. */ + { "r63", 63, REG, ARC_REGISTER_READONLY }, + + /* Small-data base register. */ + { "gp", 26, REG, 0 }, + /* Frame pointer. */ + { "fp", 27, REG, 0 }, + /* Stack pointer. */ + { "sp", 28, REG, 0 }, + + { "r29", 29, REG, 0 }, + { "r30", 30, REG, 0 }, + { "r31", 31, REG, 0 }, + { "r60", 60, REG, 0 }, + + /* Auxiliary register set. */ + + /* Auxiliary register address map: + 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation + 0xfffffeff-0x80000000 - customer limm allocation + 0x7fffffff-0x00000100 - ARC limm allocation + 0x000000ff-0x00000000 - ARC shimm allocation */ + + /* Base case auxiliary registers (shimm address). */ + { "status", 0x00, AUXREG, 0 }, + { "semaphore", 0x01, AUXREG, 0 }, + { "lp_start", 0x02, AUXREG, 0 }, + { "lp_end", 0x03, AUXREG, 0 }, + { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, + { "debug", 0x05, AUXREG, 0 }, +}; + +const int arc_reg_names_count = + sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + +/* The suffix table. + Operands with the same name must be stored together. */ + +const struct arc_operand_value arc_suffixes[] = +{ + /* Entry 0 is special, default values aren't printed by the disassembler. */ + { "", 0, -1, 0 }, + + /* Base case condition codes. */ + { "al", 0, COND, 0 }, + { "ra", 0, COND, 0 }, + { "eq", 1, COND, 0 }, + { "z", 1, COND, 0 }, + { "ne", 2, COND, 0 }, + { "nz", 2, COND, 0 }, + { "pl", 3, COND, 0 }, + { "p", 3, COND, 0 }, + { "mi", 4, COND, 0 }, + { "n", 4, COND, 0 }, + { "cs", 5, COND, 0 }, + { "c", 5, COND, 0 }, + { "lo", 5, COND, 0 }, + { "cc", 6, COND, 0 }, + { "nc", 6, COND, 0 }, + { "hs", 6, COND, 0 }, + { "vs", 7, COND, 0 }, + { "v", 7, COND, 0 }, + { "vc", 8, COND, 0 }, + { "nv", 8, COND, 0 }, + { "gt", 9, COND, 0 }, + { "ge", 10, COND, 0 }, + { "lt", 11, COND, 0 }, + { "le", 12, COND, 0 }, + { "hi", 13, COND, 0 }, + { "ls", 14, COND, 0 }, + { "pnz", 15, COND, 0 }, + + /* Condition codes 16-31 reserved for extensions. */ + + { "f", 1, FLAG, 0 }, + + { "nd", ARC_DELAY_NONE, DELAY, 0 }, + { "d", ARC_DELAY_NORMAL, DELAY, 0 }, + { "jd", ARC_DELAY_JUMP, DELAY, 0 }, + + { "b", 1, SIZE1, 0 }, + { "b", 1, SIZE10, 0 }, + { "b", 1, SIZE22, 0 }, + { "w", 2, SIZE1, 0 }, + { "w", 2, SIZE10, 0 }, + { "w", 2, SIZE22, 0 }, + { "x", 1, SIGN0, 0 }, + { "x", 1, SIGN9, 0 }, + { "a", 1, ADDRESS3, 0 }, + { "a", 1, ADDRESS12, 0 }, + { "a", 1, ADDRESS24, 0 }, + + { "di", 1, CACHEBYPASS5, 0 }, + { "di", 1, CACHEBYPASS14, 0 }, + { "di", 1, CACHEBYPASS26, 0 }, +}; + +const int arc_suffixes_count = + sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); + +/* Indexed by first letter of opcode. Points to chain of opcodes with same + first letter. */ +static struct arc_opcode *opcode_map[26 + 1]; + +/* Indexed by insn code. Points to chain of opcodes with same insn code. */ +static struct arc_opcode *icode_map[32]; + +/* Configuration flags. */ + +/* Various ARC_HAVE_XXX bits. */ +static int cpu_type; + +/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ + +int +arc_get_opcode_mach (int bfd_mach, int big_p) +{ + static int mach_type_map[] = + { + ARC_MACH_5, + ARC_MACH_6, + ARC_MACH_7, + ARC_MACH_8 + }; + return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); +} + +/* Initialize any tables that need it. + Must be called once at start up (or when first needed). + + FLAGS is a set of bits that say what version of the cpu we have, + and in particular at least (one of) ARC_MACH_XXX. */ + +void +arc_opcode_init_tables (int flags) +{ + static int init_p = 0; + + cpu_type = flags; + + /* We may be intentionally called more than once (for example gdb will call + us each time the user switches cpu). These tables only need to be init'd + once though. */ + if (!init_p) + { + int i,n; + + memset (arc_operand_map, 0, sizeof (arc_operand_map)); + n = sizeof (arc_operands) / sizeof (arc_operands[0]); + for (i = 0; i < n; ++i) + arc_operand_map[arc_operands[i].fmt] = i; + + memset (opcode_map, 0, sizeof (opcode_map)); + memset (icode_map, 0, sizeof (icode_map)); + /* Scan the table backwards so macros appear at the front. */ + for (i = arc_opcodes_count - 1; i >= 0; --i) + { + int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); + int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); + + arc_opcodes[i].next_asm = opcode_map[opcode_hash]; + opcode_map[opcode_hash] = &arc_opcodes[i]; + + arc_opcodes[i].next_dis = icode_map[icode_hash]; + icode_map[icode_hash] = &arc_opcodes[i]; + } + + init_p = 1; + } +} + +/* Return non-zero if OPCODE is supported on the specified cpu. + Cpu selection is made when calling `arc_opcode_init_tables'. */ + +int +arc_opcode_supported (const struct arc_opcode *opcode) +{ + if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) + return 1; + return 0; +} + +/* Return the first insn in the chain for assembling INSN. */ + +const struct arc_opcode * +arc_opcode_lookup_asm (const char *insn) +{ + return opcode_map[ARC_HASH_OPCODE (insn)]; +} + +/* Return the first insn in the chain for disassembling INSN. */ + +const struct arc_opcode * +arc_opcode_lookup_dis (unsigned int insn) +{ + return icode_map[ARC_HASH_ICODE (insn)]; +} + +/* Called by the assembler before parsing an instruction. */ + +void +arc_opcode_init_insert (void) +{ + int i; + + for(i = 0; i < OPERANDS; i++) + ls_operand[i] = OP_NONE; + + flag_p = 0; + flagshimm_handled_p = 0; + cond_p = 0; + addrwb_p = 0; + shimm_p = 0; + limm_p = 0; + jumpflags_p = 0; + nullify_p = 0; + nullify = 0; /* The default is important. */ +} + +/* Called by the assembler to see if the insn has a limm operand. + Also called by the disassembler to see if the insn contains a limm. */ + +int +arc_opcode_limm_p (long *limmp) +{ + if (limmp) + *limmp = limm; + return limm_p; +} + +/* Utility for the extraction functions to return the index into + `arc_suffixes'. */ + +const struct arc_operand_value * +arc_opcode_lookup_suffix (const struct arc_operand *type, int value) +{ + const struct arc_operand_value *v,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (type == &arc_operands[ext_oper->operand.type] + && value == ext_oper->operand.value) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } + + /* ??? This is a little slow and can be speeded up. */ + for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) + if (type == &arc_operands[v->type] + && value == v->value) + return v; + return 0; +} + +int +arc_insn_is_j (arc_insn insn) +{ + return (insn & (I(-1))) == I(0x7); +} + +int +arc_insn_not_jl (arc_insn insn) +{ + return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) + != (I(0x7) | R(-1,9,1))); +} + +int +arc_operand_type (int opertype) +{ + switch (opertype) + { + case 0: + return COND; + break; + case 1: + return REG; + break; + case 2: + return AUXREG; + break; + } + return -1; +} + +struct arc_operand_value * +get_ext_suffix (char *s) +{ + struct arc_ext_operand_value *suffix = arc_ext_operands; + + while (suffix) + { + if ((COND == suffix->operand.type) + && !strcmp(s,suffix->operand.name)) + return(&suffix->operand); + suffix = suffix->next; + } + return NULL; +} + +int +arc_get_noshortcut_flag (void) +{ + return ARC_REGISTER_NOSHORT_CUT; +} diff --git a/external/gpl3/gdb/dist/opcodes/arm-dis.c b/external/gpl3/gdb/dist/opcodes/arm-dis.c new file mode 100644 index 000000000000..e8abbf51b1da --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/arm-dis.c @@ -0,0 +1,4967 @@ +/* Instruction printing code for the ARM + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) + Modification by James G. Smith (jsmith@cygnus.co.uk) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" + +#include "dis-asm.h" +#include "opcode/arm.h" +#include "opintl.h" +#include "safe-ctype.h" +#include "floatformat.h" + +/* FIXME: This shouldn't be done here. */ +#include "coff/internal.h" +#include "libcoff.h" +#include "elf-bfd.h" +#include "elf/internal.h" +#include "elf/arm.h" + +/* FIXME: Belongs in global header. */ +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +struct arm_private_data +{ + /* The features to use when disassembling optional instructions. */ + arm_feature_set features; + + /* Whether any mapping symbols are present in the provided symbol + table. -1 if we do not know yet, otherwise 0 or 1. */ + int has_mapping_symbols; +}; + +struct opcode32 +{ + unsigned long arch; /* Architecture defining this insn. */ + unsigned long value; /* If arch == 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ + const char * assembler; /* How to disassemble this insn. */ +}; + +struct opcode16 +{ + unsigned long arch; /* Architecture defining this insn. */ + unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ + const char *assembler; /* How to disassemble this insn. */ +}; + +/* print_insn_coprocessor recognizes the following format control codes: + + %% % + + %c print condition code (always bits 28-31 in ARM mode) + %q print shifter argument + %u print condition code (unconditional in ARM mode) + %A print address for ldc/stc/ldf/stf instruction + %B print vstm/vldm register list + %I print cirrus signed shift immediate: bits 0..3|4..6 + %F print the COUNT field of a LFM/SFM instruction. + %P print floating point precision in arithmetic insn + %Q print floating point precision in ldf/stf insn + %R print floating point rounding mode + + %r print as an ARM register + %R as %<>r but r15 is UNPREDICTABLE + %ru as %<>r but each u register must be unique. + %d print the bitfield in decimal + %k print immediate for VFPv3 conversion instruction + %x print the bitfield in hex + %X print the bitfield as 1 hex digit without leading "0x" + %f print a floating point constant if >7 else a + floating point register + %w print as an iWMMXt width field - [bhwd]ss/us + %g print as an iWMMXt 64-bit register + %G print as an iWMMXt general purpose or control register + %D print as a NEON D register + %Q print as a NEON Q register + + %y print a single precision VFP reg. + Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair + %z print a double precision VFP reg + Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list + + %'c print specified char iff bitfield is all ones + %`c print specified char iff bitfield is all zeroes + %?ab... select from array of values in big endian order + + %L print as an iWMMXt N/M width field. + %Z print the Immediate of a WSHUFH instruction. + %l like 'A' except use byte offsets for 'B' & 'H' + versions. + %i print 5-bit immediate in bits 8,3..0 + (print "32" when 0) + %r print register offset address for wldt/wstr instruction. */ + +enum opcode_sentinel_enum +{ + SENTINEL_IWMMXT_START = 1, + SENTINEL_IWMMXT_END, + SENTINEL_GENERIC_START +} opcode_sentinels; + +#define UNDEFINED_INSTRUCTION "\t\t; instruction: %0-31x" +#define UNPREDICTABLE_INSTRUCTION "\t; " + +/* Common coprocessor opcodes shared between Arm and Thumb-2. */ + +static const struct opcode32 coprocessor_opcodes[] = +{ + /* XScale instructions. */ + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, + + /* Intel Wireless MMX technology instructions. */ + { 0, SENTINEL_IWMMXT_START, 0, "" }, + {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, + {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, + {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, + {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, + {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, + {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, + {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, + {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, + {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, + {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, + {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, + {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, + {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, + { 0, SENTINEL_IWMMXT_END, 0, "" }, + + /* Floating point coprocessor (FPA) instructions. */ + {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, + {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, + {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, + {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, + {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, + {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, + {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, + {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, + {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, + {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, + {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + + /* Register load/store. */ + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, + {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, + {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, + {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, + {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, + + {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + + /* Data transfer between ARM and NEON registers. */ + {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, + {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, + {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, + {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, + /* Half-precision conversion instructions. */ + {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, + {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, + + /* Floating point coprocessor (VFP) instructions. */ + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, + {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, + {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, + {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, + {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, + {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, + {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, + {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, + {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, + {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, "}, + {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, + {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, + {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, + {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, + {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, + {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, + {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, + {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, + {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, + {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"}, + {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, + {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, + {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, + {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, + + /* Cirrus coprocessor instructions. */ + {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, + {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, + {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, + {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, + {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, + {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + + /* VFP Fused multiply add instructions. */ + {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + + /* Generic coprocessor instructions. */ + { 0, SENTINEL_GENERIC_START, 0, "" }, + {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, + {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, + + /* V6 coprocessor instructions. */ + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, + + /* V5 coprocessor instructions. */ + {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + + {0, 0, 0, 0} +}; + +/* Neon opcode table: This does not encode the top byte -- that is + checked by the print_insn_neon routine, as it depends on whether we are + doing thumb32 or arm32 disassembly. */ + +/* print_insn_neon recognizes the following format control codes: + + %% % + + %c print condition code + %A print v{st,ld}[1234] operands + %B print v{st,ld}[1234] any one operands + %C print v{st,ld}[1234] single->all operands + %D print scalar + %E print vmov, vmvn, vorr, vbic encoded constant + %F print vtbl,vtbx register list + + %r print as an ARM register + %d print the bitfield in decimal + %e print the 2^N - bitfield in decimal + %D print as a NEON D register + %Q print as a NEON Q register + %R print as a NEON D or Q register + %Sn print byte scaled width limited by n + %Tn print short scaled width limited by n + %Un print long scaled width limited by n + + %'c print specified char iff bitfield is all ones + %`c print specified char iff bitfield is all zeroes + %?ab... select from array of values in big endian order. */ + +static const struct opcode32 neon_opcodes[] = +{ + /* Extract. */ + {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + + /* Move data element to all lanes. */ + {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, + {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, + {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, + + /* Table lookup. */ + {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, + + /* Half-precision conversions. */ + {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, + {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, + + /* NEON fused multiply add instructions. */ + {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + + /* Two registers, miscellaneous. */ + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, + {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, + + /* Three registers of the same length. */ + {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + + /* One register and an immediate value. */ + {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, + + /* Two registers and a shift amount. */ + {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, + + /* Three registers of different lengths. */ + {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + + /* Two registers and a scalar. */ + {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + + /* Element and structure load/store. */ + {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, + + {0,0 ,0, 0} +}; + +/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially + ordered: they must be searched linearly from the top to obtain a correct + match. */ + +/* print_insn_arm recognizes the following format control codes: + + %% % + + %a print address for ldr/str instruction + %s print address for ldr/str halfword/signextend instruction + %S like %s but allow UNPREDICTABLE addressing + %b print branch destination + %c print condition code (always bits 28-31) + %m print register mask for ldm/stm instruction + %o print operand2 (immediate or register + shift) + %p print 'p' iff bits 12-15 are 15 + %t print 't' iff bit 21 set and bit 24 clear + %B print arm BLX(1) destination + %C print the PSR sub type. + %U print barrier type. + %P print address for pli instruction. + + %r print as an ARM register + %R as %r but r15 is UNPREDICTABLE + %{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE + %{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE + %d print the bitfield in decimal + %W print the bitfield plus one in decimal + %x print the bitfield in hex + %X print the bitfield as 1 hex digit without leading "0x" + + %'c print specified char iff bitfield is all ones + %`c print specified char iff bitfield is all zeroes + %?ab... select from array of values in big endian order + + %e print arm SMI operand (bits 0..7,8..19). + %E print the LSB and WIDTH fields of a BFI or BFC instruction. + %V print the 16-bit immediate field of a MOVT or MOVW instruction. + %R print the SPSR/CPSR or banked register of an MRS. */ + +static const struct opcode32 arm_opcodes[] = +{ + /* ARM instructions. */ + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, + {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"}, + {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, + + /* Integer Divide Extension instructions. */ + {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"}, + + /* V7 instructions. */ + {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, + {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, + {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, + {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, + + /* ARM V6T2 instructions. */ + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"}, + + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, + + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, + {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, + + /* ARM Security extension instructions. */ + {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, + + /* ARM V6K instructions. */ + {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, + {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, + {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, + {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, + + /* ARM V6K NOP hints. */ + {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, + {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, + {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, + {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, + {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, + + /* ARM V6 instructions. */ + {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, + {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, + {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, + {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, + {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, + {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, + {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, + {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, + + /* V5J instruction. */ + {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, + + /* V5 Instructions. */ + {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, + {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, + + /* V5E "El Segundo" Instructions. */ + {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, + {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, + {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, + {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, + + {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, + + {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + + {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, + + {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, + + {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, + + /* ARM Instructions. */ + {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, + {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, + + {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, + + {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, + {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, + + {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + + {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, + {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, + {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, + {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, + {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, + {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, + + {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, + + {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, + + {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + + {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, + + /* The rest. */ + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {0, 0x00000000, 0x00000000, 0} +}; + +/* print_insn_thumb16 recognizes the following format control codes: + + %S print Thumb register (bits 3..5 as high number if bit 6 set) + %D print Thumb register (bits 0..2 as high number if bit 7 set) + %I print bitfield as a signed decimal + (top bit of range being the sign bit) + %N print Thumb register mask (with LR) + %O print Thumb register mask (with PC) + %M print Thumb register mask + %b print CZB's 6-bit unsigned branch destination + %s print Thumb right-shift immediate (6..10; 0 == 32). + %c print the condition code + %C print the condition code, or "s" if not conditional + %x print warning if conditional an not at end of IT block" + %X print "\t; unpredictable " if conditional + %I print IT instruction suffix and operands + %W print Thumb Writeback indicator for LDMIA + %r print bitfield as an ARM register + %d print bitfield as a decimal + %H print (bitfield * 2) as a decimal + %W print (bitfield * 4) as a decimal + %a print (bitfield * 4) as a pc-rel offset + decoded symbol + %B print Thumb branch destination (signed displacement) + %c print bitfield as a condition code + %'c print specified char iff bit is one + %?ab print a if bit is one else print b. */ + +static const struct opcode16 thumb_opcodes[] = +{ + /* Thumb instructions. */ + + /* ARM V6K no-argument instructions. */ + {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, + {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, + {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, + {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, + {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, + {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, + + /* ARM V6T2 instructions. */ + {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, + {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, + {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, + + /* ARM V6. */ + {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, + {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, + {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, + {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, + + /* ARM V5 ISA extends Thumb. */ + {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ + /* This is BLX(2). BLX(1) is a 32-bit instruction. */ + {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ + /* ARM V4T ISA (Thumb v1). */ + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, + /* Format 4. */ + {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, + /* format 13 */ + {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, + {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, + /* format 5 */ + {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, + {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, + {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, + {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, + /* format 14 */ + {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, + {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, + /* format 2 */ + {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, + /* format 8 */ + {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, + /* format 7 */ + {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + /* format 1 */ + {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, + {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, + {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, + /* format 3 */ + {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, + /* format 6 */ + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ + /* format 9 */ + {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, + /* format 10 */ + {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, + /* format 11 */ + {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, + /* format 12 */ + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, + {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, + /* format 15 */ + {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, + /* format 17 */ + {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, + /* format 16 */ + {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, + {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, + /* format 18 */ + {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, + + /* The E800 .. FFFF range is unconditionally redirected to the + 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs + are processed via that table. Thus, we can never encounter a + bare "second half of BL/BLX(1)" instruction here. */ + {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, + {0, 0, 0, 0} +}; + +/* Thumb32 opcodes use the same table structure as the ARM opcodes. + We adopt the convention that hw1 is the high 16 bits of .value and + .mask, hw2 the low 16 bits. + + print_insn_thumb32 recognizes the following format control codes: + + %% % + + %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] + %M print a modified 12-bit immediate (same location) + %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] + %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] + %H print a 16-bit immediate from hw2[3:0],hw1[11:0] + %S print a possibly-shifted Rm + + %a print the address of a plain load/store + %w print the width and signedness of a core load/store + %m print register mask for ldm/stm + + %E print the lsb and width fields of a bfc/bfi instruction + %F print the lsb and width fields of a sbfx/ubfx instruction + %b print a conditional branch offset + %B print an unconditional branch offset + %s print the shift field of an SSAT instruction + %R print the rotation field of an SXT instruction + %U print barrier type. + %P print address for pli instruction. + %c print the condition code + %x print warning if conditional an not at end of IT block" + %X print "\t; unpredictable " if conditional + + %d print bitfield in decimal + %W print bitfield*4 in decimal + %r print bitfield as an ARM register + %R as %<>r bit r15 is UNPREDICTABLE + %c print bitfield as a condition code + + %'c print specified char iff bitfield is all ones + %`c print specified char iff bitfield is all zeroes + %?ab... select from array of values in big endian order + + With one exception at the bottom (done because BL and BLX(1) need + to come dead last), this table was machine-sorted first in + decreasing order of number of bits set in the mask, then in + increasing numeric order of mask, then in increasing numeric order + of opcode. This order is not the clearest for a human reader, but + is guaranteed never to catch a special-case bit pattern with a more + general mask, which is important, because this instruction encoding + makes heavy use of special-case bit patterns. */ +static const struct opcode32 thumb32_opcodes[] = +{ + /* V7 instructions. */ + {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, + {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, + {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, + {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, + {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + + /* Virtualization Extension instructions. */ + {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, + /* We skip ERET as that is SUBS pc, lr, #0. */ + + /* MP Extension instructions. */ + {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"}, + + /* Security extension instructions. */ + {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + + /* Instructions defined in the basic V6T2 set. */ + {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, + {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, + {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, + {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, + {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"}, + {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, + + {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, + {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, + {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, + {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, + {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, + {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, + {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, + {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, + {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, + {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, + {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, + {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, + {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, + {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, + + /* Filter out Bcc with cond=E or F, which are used for other instructions. */ + {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, + {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, + {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, + {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, + + /* These have been 32-bit since the invention of Thumb. */ + {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, + {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, + + /* Fallback. */ + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {0, 0, 0, 0} +}; + +static const char *const arm_conditional[] = +{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "al", "", ""}; + +static const char *const arm_fp_const[] = +{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; + +static const char *const arm_shift[] = +{"lsl", "lsr", "asr", "ror"}; + +typedef struct +{ + const char *name; + const char *description; + const char *reg_names[16]; +} +arm_regname; + +static const arm_regname regnames[] = +{ + { "raw" , "Select raw register names", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, + { "gcc", "Select register names used by GCC", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, + { "std", "Select register names used in ARM's ISA documentation", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, + { "apcs", "Select register names used in the APCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, + { "atpcs", "Select register names used in the ATPCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, + { "special-atpcs", "Select special register names used in the ATPCS", + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, +}; + +static const char *const iwmmxt_wwnames[] = +{"b", "h", "w", "d"}; + +static const char *const iwmmxt_wwssnames[] = +{"b", "bus", "bc", "bss", + "h", "hus", "hc", "hss", + "w", "wus", "wc", "wss", + "d", "dus", "dc", "dss" +}; + +static const char *const iwmmxt_regnames[] = +{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", + "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" +}; + +static const char *const iwmmxt_cregnames[] = +{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", + "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" +}; + +/* Default to GCC register name set. */ +static unsigned int regname_selected = 1; + +#define NUM_ARM_REGNAMES NUM_ELEM (regnames) +#define arm_regnames regnames[regname_selected].reg_names + +static bfd_boolean force_thumb = FALSE; + +/* Current IT instruction state. This contains the same state as the IT + bits in the CPSR. */ +static unsigned int ifthen_state; +/* IT state for the next instruction. */ +static unsigned int ifthen_next_state; +/* The address of the insn for which the IT state is valid. */ +static bfd_vma ifthen_address; +#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) + +/* Cached mapping symbol state. */ +enum map_type +{ + MAP_ARM, + MAP_THUMB, + MAP_DATA +}; + +enum map_type last_type; +int last_mapping_sym = -1; +bfd_vma last_mapping_addr = 0; + + +/* Functions. */ +int +get_arm_regname_num_options (void) +{ + return NUM_ARM_REGNAMES; +} + +int +set_arm_regname_option (int option) +{ + int old = regname_selected; + regname_selected = option; + return old; +} + +int +get_arm_regnames (int option, + const char **setname, + const char **setdescription, + const char *const **register_names) +{ + *setname = regnames[option].name; + *setdescription = regnames[option].description; + *register_names = regnames[option].reg_names; + return 16; +} + +/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. + Returns pointer to following character of the format string and + fills in *VALUEP and *WIDTHP with the extracted value and number of + bits extracted. WIDTHP can be NULL. */ + +static const char * +arm_decode_bitfield (const char *ptr, + unsigned long insn, + unsigned long *valuep, + int *widthp) +{ + unsigned long value = 0; + int width = 0; + + do + { + int start, end; + int bits; + + for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) + start = start * 10 + *ptr - '0'; + if (*ptr == '-') + for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) + end = end * 10 + *ptr - '0'; + else + end = start; + bits = end - start; + if (bits < 0) + abort (); + value |= ((insn >> start) & ((2ul << bits) - 1)) << width; + width += bits + 1; + } + while (*ptr++ == ','); + *valuep = value; + if (widthp) + *widthp = width; + return ptr - 1; +} + +static void +arm_decode_shift (long given, fprintf_ftype func, void *stream, + bfd_boolean print_shift) +{ + func (stream, "%s", arm_regnames[given & 0xf]); + + if ((given & 0xff0) != 0) + { + if ((given & 0x10) == 0) + { + int amount = (given & 0xf80) >> 7; + int shift = (given & 0x60) >> 5; + + if (amount == 0) + { + if (shift == 3) + { + func (stream, ", rrx"); + return; + } + + amount = 32; + } + + if (print_shift) + func (stream, ", %s #%d", arm_shift[shift], amount); + else + func (stream, ", #%d", amount); + } + else if ((given & 0x80) == 0x80) + func (stream, "\t; "); + else if (print_shift) + func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], + arm_regnames[(given & 0xf00) >> 8]); + else + func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); + } +} + +#define W_BIT 21 +#define I_BIT 22 +#define U_BIT 23 +#define P_BIT 24 + +#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) +#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) +#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) +#define PRE_BIT_SET (given & (1 << P_BIT)) + +/* Print one coprocessor instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised coprocessor instruction. */ + +static bfd_boolean +print_insn_coprocessor (bfd_vma pc, + struct disassemble_info *info, + long given, + bfd_boolean thumb) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + unsigned long mask; + unsigned long value = 0; + struct arm_private_data *private_data = info->private_data; + unsigned long allowed_arches = private_data->features.coproc; + int cond; + + for (insn = coprocessor_opcodes; insn->assembler; insn++) + { + unsigned long u_reg = 16; + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; + const char *c; + + if (insn->arch == 0) + switch (insn->value) + { + case SENTINEL_IWMMXT_START: + if (info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt + && info->mach != bfd_mach_arm_iWMMXt2) + do + insn++; + while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END); + continue; + + case SENTINEL_IWMMXT_END: + continue; + + case SENTINEL_GENERIC_START: + allowed_arches = private_data->features.core; + continue; + + default: + abort (); + } + + mask = insn->mask; + value = insn->value; + if (thumb) + { + /* The high 4 bits are 0xe for Arm conditional instructions, and + 0xe for arm unconditional instructions. The rest of the + encoding is the same. */ + mask |= 0xf0000000; + value |= 0xe0000000; + if (ifthen_state) + cond = IFTHEN_COND; + else + cond = 16; + } + else + { + /* Only match unconditional instuctions against unconditional + patterns. */ + if ((given & 0xf0000000) == 0xf0000000) + { + mask |= 0xf0000000; + cond = 16; + } + else + { + cond = (given >> 28) & 0xf; + if (cond == 0xe) + cond = 16; + } + } + + if ((given & mask) != value) + continue; + + if ((insn->arch & allowed_arches) == 0) + continue; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'A': + { + int rn = (given >> 16) & 0xf; + int offset = given & 0xff; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (PRE_BIT_SET || WRITEBACK_BIT_SET) + { + /* Not unindexed. The offset is scaled. */ + offset = offset * 4; + if (NEGATIVE_BIT_SET) + offset = - offset; + if (rn != 15) + value_in_comment = offset; + } + + if (PRE_BIT_SET) + { + if (offset) + func (stream, ", #%d]%s", + offset, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "]"); + } + else + { + func (stream, "]"); + + if (WRITEBACK_BIT_SET) + { + if (offset) + func (stream, ", #%d", offset); + } + else + { + func (stream, ", {%d}", offset); + value_in_comment = offset; + } + } + if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) + { + func (stream, "\t; "); + /* For unaligned PCs, apply off-by-alignment + correction. */ + info->print_address_func (offset + pc + + info->bytes_per_chunk * 2 + - (pc & 3), + info); + } + } + break; + + case 'B': + { + int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); + int offset = (given >> 1) & 0x3f; + + if (offset == 1) + func (stream, "{d%d}", regno); + else if (regno + offset > 32) + func (stream, "{d%d-}", regno, regno + offset - 1); + else + func (stream, "{d%d-d%d}", regno, regno + offset - 1); + } + break; + + case 'c': + func (stream, "%s", arm_conditional[cond]); + break; + + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; + + imm = (given & 0xf) | ((given & 0xe0) >> 1); + + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + + case 'F': + switch (given & 0x00408000) + { + case 0: + func (stream, "4"); + break; + case 0x8000: + func (stream, "1"); + break; + case 0x00400000: + func (stream, "2"); + break; + default: + func (stream, "3"); + } + break; + + case 'P': + switch (given & 0x00080080) + { + case 0: + func (stream, "s"); + break; + case 0x80: + func (stream, "d"); + break; + case 0x00080000: + func (stream, "e"); + break; + default: + func (stream, _("")); + break; + } + break; + + case 'Q': + switch (given & 0x00408000) + { + case 0: + func (stream, "s"); + break; + case 0x8000: + func (stream, "d"); + break; + case 0x00400000: + func (stream, "e"); + break; + default: + func (stream, "p"); + break; + } + break; + + case 'R': + switch (given & 0x60) + { + case 0: + break; + case 0x20: + func (stream, "p"); + break; + case 0x40: + func (stream, "m"); + break; + default: + func (stream, "z"); + break; + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + + c = arm_decode_bitfield (c, given, &value, &width); + + switch (*c) + { + case 'R': + if (value == 15) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + if (c[1] == 'u') + { + /* Eat the 'u' character. */ + ++ c; + + if (u_reg == value) + is_unpredictable = TRUE; + u_reg = value; + } + func (stream, "%s", arm_regnames[value]); + break; + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + if (value & 1) + func (stream, "", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + case 'd': + func (stream, "%ld", value); + value_in_comment = value; + break; + case 'k': + { + int from = (given & (1 << 7)) ? 32 : 16; + func (stream, "%ld", from - value); + } + break; + + case 'f': + if (value > 7) + func (stream, "#%s", arm_fp_const[value & 7]); + else + func (stream, "f%ld", value); + break; + + case 'w': + if (width == 2) + func (stream, "%s", iwmmxt_wwnames[value]); + else + func (stream, "%s", iwmmxt_wwssnames[value]); + break; + + case 'g': + func (stream, "%s", iwmmxt_regnames[value]); + break; + case 'G': + func (stream, "%s", iwmmxt_cregnames[value]); + break; + + case 'x': + func (stream, "0x%lx", (value & 0xffffffffUL)); + break; + + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int) value]); + c += 1 << width; + break; + default: + abort (); + } + break; + + case 'y': + case 'z': + { + int single = *c++ == 'y'; + int regno; + + switch (*c) + { + case '4': /* Sm pair */ + case '0': /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + else + regno += ((given >> 5) & 1) << 4; + break; + + case '1': /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; + + case '2': /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + else + regno += ((given >> 7) & 1) << 4; + break; + + case '3': /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; + + default: + abort (); + } + + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (*c == '3') + { + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } + + func (stream, "}"); + } + else if (*c == '4') + func (stream, ", %c%d", single ? 's' : 'd', + regno + 1); + } + break; + + case 'L': + switch (given & 0x00400100) + { + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: + break; + } + break; + + case 'Z': + { + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", value); + } + break; + + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (multiplier > 1) + { + value_in_comment = offset * multiplier; + if (NEGATIVE_BIT_SET) + value_in_comment = - value_in_comment; + } + + if (offset) + { + if (PRE_BIT_SET) + func (stream, ", #%s%d]%s", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier); + } + else + func (stream, "]"); + } + break; + + case 'r': + { + int imm4 = (given >> 4) & 0xf; + int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); + int ubit = ! NEGATIVE_BIT_SET; + const char *rm = arm_regnames [given & 0xf]; + const char *rn = arm_regnames [(given >> 16) & 0xf]; + + switch (puw_bits) + { + case 1: + case 3: + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); + if (imm4) + func (stream, ", lsl #%d", imm4); + break; + + case 4: + case 5: + case 6: + case 7: + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); + if (imm4 > 0) + func (stream, ", lsl #%d", imm4); + func (stream, "]"); + if (puw_bits == 5 || puw_bits == 7) + func (stream, "!"); + break; + + default: + func (stream, "INVALID"); + } + } + break; + + case 'i': + { + long imm5; + imm5 = ((given & 0x100) >> 4) | (given & 0xf); + func (stream, "%ld", (imm5 == 0) ? 32 : imm5); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return TRUE; + } + return FALSE; +} + +/* Decodes and prints ARM addressing modes. Returns the offset + used in the address, if any, if it is worthwhile printing the + offset as a hexadecimal value in a comment at the end of the + line of disassembly. */ + +static signed long +print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + int offset = 0; + + if (((given & 0x000f0000) == 0x000f0000) + && ((given & 0x02000000) == 0)) + { + offset = given & 0xfff; + + func (stream, "[pc"); + + if (NEGATIVE_BIT_SET) + offset = - offset; + + if (PRE_BIT_SET) + { + /* Pre-indexed. */ + func (stream, ", #%d]", offset); + + offset += pc + 8; + + /* Cope with the possibility of write-back + being used. Probably a very dangerous thing + for the programmer to do, but who are we to + argue ? */ + if (WRITEBACK_BIT_SET) + func (stream, "!"); + } + else /* Post indexed. */ + { + func (stream, "], #%d", offset); + + /* Ie ignore the offset. */ + offset = pc + 8; + } + + func (stream, "\t; "); + info->print_address_func (offset, info); + offset = 0; + } + else + { + func (stream, "[%s", + arm_regnames[(given >> 16) & 0xf]); + + if (PRE_BIT_SET) + { + if ((given & 0x02000000) == 0) + { + offset = given & 0xfff; + if (offset) + func (stream, ", #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + } + else + { + func (stream, ", %s", + NEGATIVE_BIT_SET ? "-" : ""); + arm_decode_shift (given, func, stream, TRUE); + } + + func (stream, "]%s", + WRITEBACK_BIT_SET ? "!" : ""); + } + else + { + if ((given & 0x02000000) == 0) + { + offset = given & 0xfff; + if (offset) + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + else + func (stream, "]"); + } + else + { + func (stream, "], %s", + NEGATIVE_BIT_SET ? "-" : ""); + arm_decode_shift (given, func, stream, TRUE); + } + } + } + + return (signed long) offset; +} + +/* Print one neon instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised neon instruction. */ + +static bfd_boolean +print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (thumb) + { + if ((given & 0xef000000) == 0xef000000) + { + /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ + unsigned long bit28 = given & (1 << 28); + + given &= 0x00ffffff; + if (bit28) + given |= 0xf3000000; + else + given |= 0xf2000000; + } + else if ((given & 0xff000000) == 0xf9000000) + given ^= 0xf9000000 ^ 0xf4000000; + else + return FALSE; + } + + for (insn = neon_opcodes; insn->assembler; insn++) + { + if ((given & insn->mask) == insn->value) + { + signed long value_in_comment = 0; + const char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'c': + if (thumb && ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'A': + { + static const unsigned char enc[16] = + { + 0x4, 0x14, /* st4 0,1 */ + 0x4, /* st1 2 */ + 0x4, /* st2 3 */ + 0x3, /* st3 4 */ + 0x13, /* st3 5 */ + 0x3, /* st1 6 */ + 0x1, /* st1 7 */ + 0x2, /* st2 8 */ + 0x12, /* st2 9 */ + 0x2, /* st1 10 */ + 0, 0, 0, 0, 0 + }; + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int align = ((given >> 4) & 0x3); + int type = ((given >> 8) & 0xf); + int n = enc[type] & 0xf; + int stride = (enc[type] >> 4) + 1; + int ix; + + func (stream, "{"); + if (stride > 1) + for (ix = 0; ix != n; ix++) + func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); + else if (n == 1) + func (stream, "d%d", rd); + else + func (stream, "d%d-d%d", rd, rd + n - 1); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + func (stream, " :%d", 32 << align); + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'B': + { + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int idx_align = ((given >> 4) & 0xf); + int align = 0; + int size = ((given >> 10) & 0x3); + int idx = idx_align >> (size + 1); + int length = ((given >> 8) & 3) + 1; + int stride = 1; + int i; + + if (length > 1 && size > 0) + stride = (idx_align & (1 << size)) ? 2 : 1; + + switch (length) + { + case 1: + { + int amask = (1 << size) - 1; + if ((idx_align & (1 << size)) != 0) + return FALSE; + if (size > 0) + { + if ((idx_align & amask) == amask) + align = 8 << size; + else if ((idx_align & amask) != 0) + return FALSE; + } + } + break; + + case 2: + if (size == 2 && (idx_align & 2) != 0) + return FALSE; + align = (idx_align & 1) ? 16 << size : 0; + break; + + case 3: + if ((size == 2 && (idx_align & 3) != 0) + || (idx_align & 1) != 0) + return FALSE; + break; + + case 4: + if (size == 2) + { + if ((idx_align & 3) == 3) + return FALSE; + align = (idx_align & 3) * 64; + } + else + align = (idx_align & 1) ? 32 << size : 0; + break; + + default: + abort (); + } + + func (stream, "{"); + for (i = 0; i < length; i++) + func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", + rd + i * stride, idx); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + func (stream, " :%d", align); + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'C': + { + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int align = ((given >> 4) & 0x1); + int size = ((given >> 6) & 0x3); + int type = ((given >> 8) & 0x3); + int n = type + 1; + int stride = ((given >> 5) & 0x1); + int ix; + + if (stride && (n == 1)) + n++; + else + stride++; + + func (stream, "{"); + if (stride > 1) + for (ix = 0; ix != n; ix++) + func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); + else if (n == 1) + func (stream, "d%d[]", rd); + else + func (stream, "d%d[]-d%d[]", rd, rd + n - 1); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + { + align = (8 * (type + 1)) << size; + if (type == 3) + align = (size > 1) ? align >> 1 : align; + if (type == 2 || (type == 0 && !size)) + func (stream, " :", align); + else + func (stream, " :%d", align); + } + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'D': + { + int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); + int size = (given >> 20) & 3; + int reg = raw_reg & ((4 << size) - 1); + int ix = raw_reg >> size >> 2; + + func (stream, "d%d[%d]", reg, ix); + } + break; + + case 'E': + /* Neon encoded constant for mov, mvn, vorr, vbic. */ + { + int bits = 0; + int cmode = (given >> 8) & 0xf; + int op = (given >> 5) & 0x1; + unsigned long value = 0, hival = 0; + unsigned shift; + int size = 0; + int isfloat = 0; + + bits |= ((given >> 24) & 1) << 7; + bits |= ((given >> 16) & 7) << 4; + bits |= ((given >> 0) & 15) << 0; + + if (cmode < 8) + { + shift = (cmode >> 1) & 3; + value = (unsigned long) bits << (8 * shift); + size = 32; + } + else if (cmode < 12) + { + shift = (cmode >> 1) & 1; + value = (unsigned long) bits << (8 * shift); + size = 16; + } + else if (cmode < 14) + { + shift = (cmode & 1) + 1; + value = (unsigned long) bits << (8 * shift); + value |= (1ul << (8 * shift)) - 1; + size = 32; + } + else if (cmode == 14) + { + if (op) + { + /* Bit replication into bytes. */ + int ix; + unsigned long mask; + + value = 0; + hival = 0; + for (ix = 7; ix >= 0; ix--) + { + mask = ((bits >> ix) & 1) ? 0xff : 0; + if (ix <= 3) + value = (value << 8) | mask; + else + hival = (hival << 8) | mask; + } + size = 64; + } + else + { + /* Byte replication. */ + value = (unsigned long) bits; + size = 8; + } + } + else if (!op) + { + /* Floating point encoding. */ + int tmp; + + value = (unsigned long) (bits & 0x7f) << 19; + value |= (unsigned long) (bits & 0x80) << 24; + tmp = bits & 0x40 ? 0x3c : 0x40; + value |= (unsigned long) tmp << 24; + size = 32; + isfloat = 1; + } + else + { + func (stream, "", + bits, cmode, op); + size = 32; + break; + } + switch (size) + { + case 8: + func (stream, "#%ld\t; 0x%.2lx", value, value); + break; + + case 16: + func (stream, "#%ld\t; 0x%.4lx", value, value); + break; + + case 32: + if (isfloat) + { + unsigned char valbytes[4]; + double fvalue; + + /* Do this a byte at a time so we don't have to + worry about the host's endianness. */ + valbytes[0] = value & 0xff; + valbytes[1] = (value >> 8) & 0xff; + valbytes[2] = (value >> 16) & 0xff; + valbytes[3] = (value >> 24) & 0xff; + + floatformat_to_double + (& floatformat_ieee_single_little, valbytes, + & fvalue); + + func (stream, "#%.7g\t; 0x%.8lx", fvalue, + value); + } + else + func (stream, "#%ld\t; 0x%.8lx", + (long) (((value & 0x80000000L) != 0) + ? value | ~0xffffffffL : value), + value); + break; + + case 64: + func (stream, "#0x%.8lx%.8lx", hival, value); + break; + + default: + abort (); + } + } + break; + + case 'F': + { + int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); + int num = (given >> 8) & 0x3; + + if (!num) + func (stream, "{d%d}", regno); + else if (num + regno >= 32) + func (stream, "{d%d-= '0' && *c <= '9') + limit = *c - '0'; + else if (*c >= 'a' && *c <= 'f') + limit = *c - 'a' + 10; + else + abort (); + low = limit >> 2; + high = limit & 3; + + if (value < low || value > high) + func (stream, "", base << value); + else + func (stream, "%d", base << value); + } + break; + case 'R': + if (given & (1 << 6)) + goto Q; + /* FALLTHROUGH */ + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + Q: + if (value & 1) + func (stream, "", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int) value]); + c += 1 << width; + break; + default: + abort (); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + + return TRUE; + } + } + return FALSE; +} + +/* Return the name of a v7A special register. */ + +static const char * +banked_regname (unsigned reg) +{ + switch (reg) + { + case 15: return "CPSR"; + case 32: return "R8_usr"; + case 33: return "R9_usr"; + case 34: return "R10_usr"; + case 35: return "R11_usr"; + case 36: return "R12_usr"; + case 37: return "SP_usr"; + case 38: return "LR_usr"; + case 40: return "R8_fiq"; + case 41: return "R9_fiq"; + case 42: return "R10_fiq"; + case 43: return "R11_fiq"; + case 44: return "R12_fiq"; + case 45: return "SP_fiq"; + case 46: return "LR_fiq"; + case 48: return "LR_irq"; + case 49: return "SP_irq"; + case 50: return "LR_svc"; + case 51: return "SP_svc"; + case 52: return "LR_abt"; + case 53: return "SP_abt"; + case 54: return "LR_und"; + case 55: return "SP_und"; + case 60: return "LR_mon"; + case 61: return "SP_mon"; + case 62: return "ELR_hyp"; + case 63: return "SP_hyp"; + case 79: return "SPSR"; + case 110: return "SPSR_fiq"; + case 112: return "SPSR_irq"; + case 114: return "SPSR_svc"; + case 116: return "SPSR_abt"; + case 118: return "SPSR_und"; + case 124: return "SPSR_mon"; + case 126: return "SPSR_hyp"; + default: return NULL; + } +} + +/* Print one ARM instruction from PC on INFO->STREAM. */ + +static void +print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + struct arm_private_data *private_data = info->private_data; + + if (print_insn_coprocessor (pc, info, given, FALSE)) + return; + + if (print_insn_neon (info, given, FALSE)) + return; + + for (insn = arm_opcodes; insn->assembler; insn++) + { + if ((given & insn->mask) != insn->value) + continue; + + if ((insn->arch & private_data->features.core) == 0) + continue; + + /* Special case: an instruction with all bits set in the condition field + (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, + or by the catchall at the end of the table. */ + if ((given & 0xF0000000) != 0xF0000000 + || (insn->mask & 0xF0000000) == 0xF0000000 + || (insn->mask == 0 && insn->value == 0)) + { + unsigned long u_reg = 16; + unsigned long U_reg = 16; + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; + const char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + bfd_boolean allow_unpredictable = FALSE; + + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'a': + value_in_comment = print_arm_address (pc, info, given); + break; + + case 'P': + /* Set P address bit and use normal address + printing routine. */ + value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); + break; + + case 'S': + allow_unpredictable = TRUE; + case 's': + if ((given & 0x004f0000) == 0x004f0000) + { + /* PC relative with immediate offset. */ + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + + if (NEGATIVE_BIT_SET) + offset = - offset; + + if (PRE_BIT_SET) + { + if (offset) + func (stream, "[pc, #%d]\t; ", offset); + else + func (stream, "[pc]\t; "); + info->print_address_func (offset + pc + 8, info); + } + else + { + func (stream, "[pc], #%d", offset); + if (! allow_unpredictable) + is_unpredictable = TRUE; + } + } + else + { + int offset = ((given & 0xf00) >> 4) | (given & 0xf); + + if (NEGATIVE_BIT_SET) + offset = - offset; + + func (stream, "[%s", + arm_regnames[(given >> 16) & 0xf]); + + if (PRE_BIT_SET) + { + if (IMMEDIATE_BIT_SET) + { + if (WRITEBACK_BIT_SET) + /* Immediate Pre-indexed. */ + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, ", #%d", offset); + else if (offset) + /* Immediate Offset: printing zero offset is optional. */ + func (stream, ", #%d", offset); + + value_in_comment = offset; + } + else + { + /* Register Offset or Register Pre-Indexed. */ + func (stream, ", %s%s", + NEGATIVE_BIT_SET ? "-" : "", + arm_regnames[given & 0xf]); + + /* Writing back to the register that is the source/ + destination of the load/store is unpredictable. */ + if (! allow_unpredictable + && WRITEBACK_BIT_SET + && ((given & 0xf) == ((given >> 12) & 0xf))) + is_unpredictable = TRUE; + } + + func (stream, "]%s", + WRITEBACK_BIT_SET ? "!" : ""); + } + else + { + if (IMMEDIATE_BIT_SET) + { + /* Immediate Post-indexed. */ + /* PR 10924: Offset must be printed, even if it is zero. */ + func (stream, "], #%d", offset); + value_in_comment = offset; + } + else + { + /* Register Post-indexed. */ + func (stream, "], %s%s", + NEGATIVE_BIT_SET ? "-" : "", + arm_regnames[given & 0xf]); + + /* Writing back to the register that is the source/ + destination of the load/store is unpredictable. */ + if (! allow_unpredictable + && (given & 0xf) == ((given >> 12) & 0xf)) + is_unpredictable = TRUE; + } + + if (! allow_unpredictable) + { + /* Writeback is automatically implied by post- addressing. + Setting the W bit is unnecessary and ARM specify it as + being unpredictable. */ + if (WRITEBACK_BIT_SET + /* Specifying the PC register as the post-indexed + registers is also unpredictable. */ + || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) + is_unpredictable = TRUE; + } + } + } + break; + + case 'b': + { + int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); + info->print_address_func (disp * 4 + pc + 8, info); + } + break; + + case 'c': + if (((given >> 28) & 0xf) != 0xe) + func (stream, "%s", + arm_conditional [(given >> 28) & 0xf]); + break; + + case 'm': + { + int started = 0; + int reg; + + func (stream, "{"); + for (reg = 0; reg < 16; reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + func (stream, "}"); + if (! started) + is_unpredictable = TRUE; + } + break; + + case 'q': + arm_decode_shift (given, func, stream, FALSE); + break; + + case 'o': + if ((given & 0x02000000) != 0) + { + int rotate = (given & 0xf00) >> 7; + int immed = (given & 0xff); + + immed = (((immed << (32 - rotate)) + | (immed >> rotate)) & 0xffffffff); + func (stream, "#%d", immed); + value_in_comment = immed; + } + else + arm_decode_shift (given, func, stream, TRUE); + break; + + case 'p': + if ((given & 0x0000f000) == 0x0000f000) + { + /* The p-variants of tst/cmp/cmn/teq are the pre-V6 + mechanism for setting PSR flag bits. They are + obsolete in V6 onwards. */ + if ((private_data->features.core & ARM_EXT_V6) == 0) + func (stream, "p"); + } + break; + + case 't': + if ((given & 0x01200000) == 0x00200000) + func (stream, "t"); + break; + + case 'A': + { + int offset = given & 0xff; + + value_in_comment = offset * 4; + if (NEGATIVE_BIT_SET) + value_in_comment = - value_in_comment; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (PRE_BIT_SET) + { + if (offset) + func (stream, ", #%d]%s", + value_in_comment, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "]"); + } + else + { + func (stream, "]"); + + if (WRITEBACK_BIT_SET) + { + if (offset) + func (stream, ", #%d", value_in_comment); + } + else + { + func (stream, ", {%d}", offset); + value_in_comment = offset; + } + } + } + break; + + case 'B': + /* Print ARM V5 BLX(1) address: pc+25 bits. */ + { + bfd_vma address; + bfd_vma offset = 0; + + if (! NEGATIVE_BIT_SET) + /* Is signed, hi bits should be ones. */ + offset = (-1) ^ 0x00ffffff; + + /* Offset is (SignExtend(offset field)<<2). */ + offset += given & 0x00ffffff; + offset <<= 2; + address = offset + pc + 8; + + if (given & 0x01000000) + /* H bit allows addressing to 2-byte boundaries. */ + address += 2; + + info->print_address_func (address, info); + } + break; + + case 'C': + if ((given & 0x02000200) == 0x200) + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", sysm); + } + else + { + func (stream, "%cPSR_", + (given & 0x00400000) ? 'S' : 'C'); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); + } + break; + + case 'U': + if ((given & 0xf0) == 0x60) + { + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + else + { + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + case 0x7: func (stream, "un"); break; + case 0xe: func (stream, "st"); break; + case 0x6: func (stream, "unst"); break; + case 0xb: func (stream, "ish"); break; + case 0xa: func (stream, "ishst"); break; + case 0x3: func (stream, "osh"); break; + case 0x2: func (stream, "oshst"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + unsigned long value; + + c = arm_decode_bitfield (c, given, &value, &width); + + switch (*c) + { + case 'R': + if (value == 15) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + if (c[1] == 'u') + { + /* Eat the 'u' character. */ + ++ c; + + if (u_reg == value) + is_unpredictable = TRUE; + u_reg = value; + } + if (c[1] == 'U') + { + /* Eat the 'U' character. */ + ++ c; + + if (U_reg == value) + is_unpredictable = TRUE; + U_reg = value; + } + func (stream, "%s", arm_regnames[value]); + break; + case 'd': + func (stream, "%ld", value); + value_in_comment = value; + break; + case 'b': + func (stream, "%ld", value * 8); + value_in_comment = value * 8; + break; + case 'W': + func (stream, "%ld", value + 1); + value_in_comment = value + 1; + break; + case 'x': + func (stream, "0x%08lx", value); + + /* Some SWI instructions have special + meanings. */ + if ((given & 0x0fffffff) == 0x0FF00000) + func (stream, "\t; IMB"); + else if ((given & 0x0fffffff) == 0x0FF00001) + func (stream, "\t; IMBRange"); + break; + case 'X': + func (stream, "%01lx", value & 0xf); + value_in_comment = value; + break; + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int) value]); + c += 1 << width; + break; + default: + abort (); + } + break; + + case 'e': + { + int imm; + + imm = (given & 0xf) | ((given & 0xfff00) >> 4); + func (stream, "%d", imm); + value_in_comment = imm; + } + break; + + case 'E': + /* LSB and WIDTH fields of BFI or BFC. The machine- + language instruction encodes LSB and MSB. */ + { + long msb = (given & 0x001f0000) >> 16; + long lsb = (given & 0x00000f80) >> 7; + long w = msb - lsb + 1; + + if (w > 0) + func (stream, "#%lu, #%lu", lsb, w); + else + func (stream, "(invalid: %lu:%lu)", lsb, msb); + } + break; + + case 'R': + /* Get the PSR/banked register name. */ + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", sysm); + } + break; + + case 'V': + /* 16-bit unsigned immediate from a MOVT or MOVW + instruction, encoded in bits 0:11 and 15:19. */ + { + long hi = (given & 0x000f0000) >> 4; + long lo = (given & 0x00000fff); + long imm16 = hi | lo; + + func (stream, "#%lu", imm16); + value_in_comment = imm16; + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return; + } + } + abort (); +} + +/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ + +static void +print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) +{ + const struct opcode16 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = thumb_opcodes; insn->assembler; insn++) + if ((given & insn->mask) == insn->value) + { + signed long value_in_comment = 0; + const char *c = insn->assembler; + + for (; *c; c++) + { + int domaskpc = 0; + int domasklr = 0; + + if (*c != '%') + { + func (stream, "%c", *c); + continue; + } + + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'c': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'C': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + else + func (stream, "s"); + break; + + case 'I': + { + unsigned int tmp; + + ifthen_next_state = given & 0xff; + for (tmp = given << 1; tmp & 0xf; tmp <<= 1) + func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); + func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); + } + break; + + case 'x': + if (ifthen_next_state) + func (stream, "\t; unpredictable branch in IT block\n"); + break; + + case 'X': + if (ifthen_state) + func (stream, "\t; unpredictable ", + arm_conditional[IFTHEN_COND]); + break; + + case 'S': + { + long reg; + + reg = (given >> 3) & 0x7; + if (given & (1 << 6)) + reg += 8; + + func (stream, "%s", arm_regnames[reg]); + } + break; + + case 'D': + { + long reg; + + reg = given & 0x7; + if (given & (1 << 7)) + reg += 8; + + func (stream, "%s", arm_regnames[reg]); + } + break; + + case 'N': + if (given & (1 << 8)) + domasklr = 1; + /* Fall through. */ + case 'O': + if (*c == 'O' && (given & (1 << 8))) + domaskpc = 1; + /* Fall through. */ + case 'M': + { + int started = 0; + int reg; + + func (stream, "{"); + + /* It would be nice if we could spot + ranges, and generate the rS-rE format: */ + for (reg = 0; (reg < 8); reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + + if (domasklr) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, arm_regnames[14] /* "lr" */); + } + + if (domaskpc) + { + if (started) + func (stream, ", "); + func (stream, arm_regnames[15] /* "pc" */); + } + + func (stream, "}"); + } + break; + + case 'W': + /* Print writeback indicator for a LDMIA. We are doing a + writeback if the base register is not in the register + mask. */ + if ((given & (1 << ((given & 0x0700) >> 8))) == 0) + func (stream, "!"); + break; + + case 'b': + /* Print ARM V6T2 CZB address: pc+4+6 bits. */ + { + bfd_vma address = (pc + 4 + + ((given & 0x00f8) >> 2) + + ((given & 0x0200) >> 3)); + info->print_address_func (address, info); + } + break; + + case 's': + /* Right shift immediate -- bits 6..10; 1-31 print + as themselves, 0 prints as 32. */ + { + long imm = (given & 0x07c0) >> 6; + if (imm == 0) + imm = 32; + func (stream, "#%ld", imm); + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + switch (*c) + { + case 'r': + func (stream, "%s", arm_regnames[reg]); + break; + + case 'd': + func (stream, "%ld", reg); + value_in_comment = reg; + break; + + case 'H': + func (stream, "%ld", reg << 1); + value_in_comment = reg << 1; + break; + + case 'W': + func (stream, "%ld", reg << 2); + value_in_comment = reg << 2; + break; + + case 'a': + /* PC-relative address -- the bottom two + bits of the address are dropped + before the calculation. */ + info->print_address_func + (((pc + 4) & ~3) + (reg << 2), info); + value_in_comment = 0; + break; + + case 'x': + func (stream, "0x%04lx", reg); + break; + + case 'B': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + info->print_address_func (reg * 2 + pc + 4, info); + value_in_comment = 0; + break; + + case 'c': + func (stream, "%s", arm_conditional [reg]); + break; + + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + + case '?': + ++c; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c++); + else + func (stream, "%c", *++c); + break; + + default: + abort (); + } + } + break; + + default: + abort (); + } + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + return; + } + + /* No match. */ + abort (); +} + +/* Return the name of an V7M special register. */ + +static const char * +psr_name (int regno) +{ + switch (regno) + { + case 0: return "APSR"; + case 1: return "IAPSR"; + case 2: return "EAPSR"; + case 3: return "PSR"; + case 5: return "IPSR"; + case 6: return "EPSR"; + case 7: return "IEPSR"; + case 8: return "MSP"; + case 9: return "PSP"; + case 16: return "PRIMASK"; + case 17: return "BASEPRI"; + case 18: return "BASEPRI_MASK"; + case 19: return "FAULTMASK"; + case 20: return "CONTROL"; + default: return ""; + } +} + +/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ + +static void +print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (print_insn_coprocessor (pc, info, given, TRUE)) + return; + + if (print_insn_neon (info, given, TRUE)) + return; + + for (insn = thumb32_opcodes; insn->assembler; insn++) + if ((given & insn->mask) == insn->value) + { + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; + const char *c = insn->assembler; + + for (; *c; c++) + { + if (*c != '%') + { + func (stream, "%c", *c); + continue; + } + + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'c': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'x': + if (ifthen_next_state) + func (stream, "\t; unpredictable branch in IT block\n"); + break; + + case 'X': + if (ifthen_state) + func (stream, "\t; unpredictable ", + arm_conditional[IFTHEN_COND]); + break; + + case 'I': + { + unsigned int imm12 = 0; + + imm12 |= (given & 0x000000ffu); + imm12 |= (given & 0x00007000u) >> 4; + imm12 |= (given & 0x04000000u) >> 15; + func (stream, "#%u", imm12); + value_in_comment = imm12; + } + break; + + case 'M': + { + unsigned int bits = 0, imm, imm8, mod; + + bits |= (given & 0x000000ffu); + bits |= (given & 0x00007000u) >> 4; + bits |= (given & 0x04000000u) >> 15; + imm8 = (bits & 0x0ff); + mod = (bits & 0xf00) >> 8; + switch (mod) + { + case 0: imm = imm8; break; + case 1: imm = ((imm8 << 16) | imm8); break; + case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; + case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; + default: + mod = (bits & 0xf80) >> 7; + imm8 = (bits & 0x07f) | 0x80; + imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); + } + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'J': + { + unsigned int imm = 0; + + imm |= (given & 0x000000ffu); + imm |= (given & 0x00007000u) >> 4; + imm |= (given & 0x04000000u) >> 15; + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'K': + { + unsigned int imm = 0; + + imm |= (given & 0x000f0000u) >> 16; + imm |= (given & 0x00000ff0u) >> 0; + imm |= (given & 0x0000000fu) << 12; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'V': + { + unsigned int imm = 0; + + imm |= (given & 0x00000fffu); + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'S': + { + unsigned int reg = (given & 0x0000000fu); + unsigned int stp = (given & 0x00000030u) >> 4; + unsigned int imm = 0; + imm |= (given & 0x000000c0u) >> 6; + imm |= (given & 0x00007000u) >> 10; + + func (stream, "%s", arm_regnames[reg]); + switch (stp) + { + case 0: + if (imm > 0) + func (stream, ", lsl #%u", imm); + break; + + case 1: + if (imm == 0) + imm = 32; + func (stream, ", lsr #%u", imm); + break; + + case 2: + if (imm == 0) + imm = 32; + func (stream, ", asr #%u", imm); + break; + + case 3: + if (imm == 0) + func (stream, ", rrx"); + else + func (stream, ", ror #%u", imm); + } + } + break; + + case 'a': + { + unsigned int Rn = (given & 0x000f0000) >> 16; + unsigned int U = ! NEGATIVE_BIT_SET; + unsigned int op = (given & 0x00000f00) >> 8; + unsigned int i12 = (given & 0x00000fff); + unsigned int i8 = (given & 0x000000ff); + bfd_boolean writeback = FALSE, postind = FALSE; + int offset = 0; + + func (stream, "[%s", arm_regnames[Rn]); + if (U) /* 12-bit positive immediate offset. */ + { + offset = i12; + if (Rn != 15) + value_in_comment = offset; + } + else if (Rn == 15) /* 12-bit negative immediate offset. */ + offset = - (int) i12; + else if (op == 0x0) /* Shifted register offset. */ + { + unsigned int Rm = (i8 & 0x0f); + unsigned int sh = (i8 & 0x30) >> 4; + + func (stream, ", %s", arm_regnames[Rm]); + if (sh) + func (stream, ", lsl #%u", sh); + func (stream, "]"); + break; + } + else switch (op) + { + case 0xE: /* 8-bit positive immediate offset. */ + offset = i8; + break; + + case 0xC: /* 8-bit negative immediate offset. */ + offset = -i8; + break; + + case 0xF: /* 8-bit + preindex with wb. */ + offset = i8; + writeback = TRUE; + break; + + case 0xD: /* 8-bit - preindex with wb. */ + offset = -i8; + writeback = TRUE; + break; + + case 0xB: /* 8-bit + postindex. */ + offset = i8; + postind = TRUE; + break; + + case 0x9: /* 8-bit - postindex. */ + offset = -i8; + postind = TRUE; + break; + + default: + func (stream, ", ]"); + goto skip; + } + + if (postind) + func (stream, "], #%d", offset); + else + { + if (offset) + func (stream, ", #%d", offset); + func (stream, writeback ? "]!" : "]"); + } + + if (Rn == 15) + { + func (stream, "\t; "); + info->print_address_func (((pc + 4) & ~3) + offset, info); + } + } + skip: + break; + + case 'A': + { + unsigned int U = ! NEGATIVE_BIT_SET; + unsigned int W = WRITEBACK_BIT_SET; + unsigned int Rn = (given & 0x000f0000) >> 16; + unsigned int off = (given & 0x000000ff); + + func (stream, "[%s", arm_regnames[Rn]); + + if (PRE_BIT_SET) + { + if (off || !U) + { + func (stream, ", #%c%u", U ? '+' : '-', off * 4); + value_in_comment = off * 4 * U ? 1 : -1; + } + func (stream, "]"); + if (W) + func (stream, "!"); + } + else + { + func (stream, "], "); + if (W) + { + func (stream, "#%c%u", U ? '+' : '-', off * 4); + value_in_comment = off * 4 * U ? 1 : -1; + } + else + { + func (stream, "{%u}", off); + value_in_comment = off; + } + } + } + break; + + case 'w': + { + unsigned int Sbit = (given & 0x01000000) >> 24; + unsigned int type = (given & 0x00600000) >> 21; + + switch (type) + { + case 0: func (stream, Sbit ? "sb" : "b"); break; + case 1: func (stream, Sbit ? "sh" : "h"); break; + case 2: + if (Sbit) + func (stream, "??"); + break; + case 3: + func (stream, "??"); + break; + } + } + break; + + case 'm': + { + int started = 0; + int reg; + + func (stream, "{"); + for (reg = 0; reg < 16; reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + func (stream, "}"); + } + break; + + case 'E': + { + unsigned int msb = (given & 0x0000001f); + unsigned int lsb = 0; + + lsb |= (given & 0x000000c0u) >> 6; + lsb |= (given & 0x00007000u) >> 10; + func (stream, "#%u, #%u", lsb, msb - lsb + 1); + } + break; + + case 'F': + { + unsigned int width = (given & 0x0000001f) + 1; + unsigned int lsb = 0; + + lsb |= (given & 0x000000c0u) >> 6; + lsb |= (given & 0x00007000u) >> 10; + func (stream, "#%u, #%u", lsb, width); + } + break; + + case 'b': + { + unsigned int S = (given & 0x04000000u) >> 26; + unsigned int J1 = (given & 0x00002000u) >> 13; + unsigned int J2 = (given & 0x00000800u) >> 11; + int offset = 0; + + offset |= !S << 20; + offset |= J2 << 19; + offset |= J1 << 18; + offset |= (given & 0x003f0000) >> 4; + offset |= (given & 0x000007ff) << 1; + offset -= (1 << 20); + + info->print_address_func (pc + 4 + offset, info); + } + break; + + case 'B': + { + unsigned int S = (given & 0x04000000u) >> 26; + unsigned int I1 = (given & 0x00002000u) >> 13; + unsigned int I2 = (given & 0x00000800u) >> 11; + int offset = 0; + + offset |= !S << 24; + offset |= !(I1 ^ S) << 23; + offset |= !(I2 ^ S) << 22; + offset |= (given & 0x03ff0000u) >> 4; + offset |= (given & 0x000007ffu) << 1; + offset -= (1 << 24); + offset += pc + 4; + + /* BLX target addresses are always word aligned. */ + if ((given & 0x00001000u) == 0) + offset &= ~2u; + + info->print_address_func (offset, info); + } + break; + + case 's': + { + unsigned int shift = 0; + + shift |= (given & 0x000000c0u) >> 6; + shift |= (given & 0x00007000u) >> 10; + if (WRITEBACK_BIT_SET) + func (stream, ", asr #%u", shift); + else if (shift) + func (stream, ", lsl #%u", shift); + /* else print nothing - lsl #0 */ + } + break; + + case 'R': + { + unsigned int rot = (given & 0x00000030) >> 4; + + if (rot) + func (stream, ", ror #%u", rot * 8); + } + break; + + case 'U': + if ((given & 0xf0) == 0x60) + { + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + else + { + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + case 0x7: func (stream, "un"); break; + case 0xe: func (stream, "st"); break; + case 0x6: func (stream, "unst"); break; + case 0xb: func (stream, "ish"); break; + case 0xa: func (stream, "ishst"); break; + case 0x3: func (stream, "osh"); break; + case 0x2: func (stream, "oshst"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + break; + + case 'C': + if ((given & 0xff) == 0) + { + func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); + if (given & 0x800) + func (stream, "f"); + if (given & 0x400) + func (stream, "s"); + if (given & 0x200) + func (stream, "x"); + if (given & 0x100) + func (stream, "c"); + } + else if ((given & 0x20) == 0x20) + { + char const* name; + unsigned sysm = (given & 0xf00) >> 8; + + sysm |= (given & 0x30); + sysm |= (given & 0x00100000) >> 14; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", sysm); + } + else + { + func (stream, psr_name (given & 0xff)); + } + break; + + case 'D': + if (((given & 0xff) == 0) + || ((given & 0x20) == 0x20)) + { + char const* name; + unsigned sm = (given & 0xf0000) >> 16; + + sm |= (given & 0x30); + sm |= (given & 0x00100000) >> 14; + name = banked_regname (sm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", sm); + } + else + func (stream, psr_name (given & 0xff)); + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + unsigned long val; + + c = arm_decode_bitfield (c, given, &val, &width); + + switch (*c) + { + case 'd': + func (stream, "%lu", val); + value_in_comment = val; + break; + + case 'W': + func (stream, "%lu", val * 4); + value_in_comment = val * 4; + break; + + case 'R': + if (val == 15) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + func (stream, "%s", arm_regnames[val]); + break; + + case 'c': + func (stream, "%s", arm_conditional[val]); + break; + + case '\'': + c++; + if (val == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + + case '`': + c++; + if (val == 0) + func (stream, "%c", *c); + break; + + case '?': + func (stream, "%c", c[(1 << width) - (int) val]); + c += 1 << width; + break; + + case 'x': + func (stream, "0x%lx", val & 0xffffffffUL); + break; + + default: + abort (); + } + } + break; + + default: + abort (); + } + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return; + } + + /* No match. */ + abort (); +} + +/* Print data bytes on INFO->STREAM. */ + +static void +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info *info, + long given) +{ + switch (info->bytes_per_chunk) + { + case 1: + info->fprintf_func (info->stream, ".byte\t0x%02lx", given); + break; + case 2: + info->fprintf_func (info->stream, ".short\t0x%04lx", given); + break; + case 4: + info->fprintf_func (info->stream, ".word\t0x%08lx", given); + break; + default: + abort (); + } +} + +/* Disallow mapping symbols ($a, $b, $d, $t etc) from + being displayed in symbol relative addresses. */ + +bfd_boolean +arm_symbol_is_valid (asymbol * sym, + struct disassemble_info * info ATTRIBUTE_UNUSED) +{ + const char * name; + + if (sym == NULL) + return FALSE; + + name = bfd_asymbol_name (sym); + + return (name && *name != '$'); +} + +/* Parse an individual disassembler option. */ + +void +parse_arm_disassembler_option (char *option) +{ + if (option == NULL) + return; + + if (CONST_STRNEQ (option, "reg-names-")) + { + int i; + + option += 10; + + for (i = NUM_ARM_REGNAMES; i--;) + if (strneq (option, regnames[i].name, strlen (regnames[i].name))) + { + regname_selected = i; + break; + } + + if (i < 0) + /* XXX - should break 'option' at following delimiter. */ + fprintf (stderr, _("Unrecognised register name set: %s\n"), option); + } + else if (CONST_STRNEQ (option, "force-thumb")) + force_thumb = 1; + else if (CONST_STRNEQ (option, "no-force-thumb")) + force_thumb = 0; + else + /* XXX - should break 'option' at following delimiter. */ + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); + + return; +} + +/* Parse the string of disassembler options, spliting it at whitespaces + or commas. (Whitespace separators supported for backwards compatibility). */ + +static void +parse_disassembler_options (char *options) +{ + if (options == NULL) + return; + + while (*options) + { + parse_arm_disassembler_option (options); + + /* Skip forward to next seperator. */ + while ((*options) && (! ISSPACE (*options)) && (*options != ',')) + ++ options; + /* Skip forward past seperators. */ + while (ISSPACE (*options) || (*options == ',')) + ++ options; + } +} + +/* Search back through the insn stream to determine if this instruction is + conditionally executed. */ + +static void +find_ifthen_state (bfd_vma pc, + struct disassemble_info *info, + bfd_boolean little) +{ + unsigned char b[2]; + unsigned int insn; + int status; + /* COUNT is twice the number of instructions seen. It will be odd if we + just crossed an instruction boundary. */ + int count; + int it_count; + unsigned int seen_it; + bfd_vma addr; + + ifthen_address = pc; + ifthen_state = 0; + + addr = pc; + count = 1; + it_count = 0; + seen_it = 0; + /* Scan backwards looking for IT instructions, keeping track of where + instruction boundaries are. We don't know if something is actually an + IT instruction until we find a definite instruction boundary. */ + for (;;) + { + if (addr == 0 || info->symbol_at_address_func (addr, info)) + { + /* A symbol must be on an instruction boundary, and will not + be within an IT block. */ + if (seen_it && (count & 1)) + break; + + return; + } + addr -= 2; + status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); + if (status) + return; + + if (little) + insn = (b[0]) | (b[1] << 8); + else + insn = (b[1]) | (b[0] << 8); + if (seen_it) + { + if ((insn & 0xf800) < 0xe800) + { + /* Addr + 2 is an instruction boundary. See if this matches + the expected boundary based on the position of the last + IT candidate. */ + if (count & 1) + break; + seen_it = 0; + } + } + if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) + { + /* This could be an IT instruction. */ + seen_it = insn; + it_count = count >> 1; + } + if ((insn & 0xf800) >= 0xe800) + count++; + else + count = (count + 2) | 1; + /* IT blocks contain at most 4 instructions. */ + if (count >= 8 && !seen_it) + return; + } + /* We found an IT instruction. */ + ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); + if ((ifthen_state & 0xf) == 0) + ifthen_state = 0; +} + +/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a + mapping symbol. */ + +static int +is_mapping_symbol (struct disassemble_info *info, int n, + enum map_type *map_type) +{ + const char *name; + + name = bfd_asymbol_name (info->symtab[n]); + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') + && (name[2] == 0 || name[2] == '.')) + { + *map_type = ((name[1] == 'a') ? MAP_ARM + : (name[1] == 't') ? MAP_THUMB + : MAP_DATA); + return TRUE; + } + + return FALSE; +} + +/* Try to infer the code type (ARM or Thumb) from a mapping symbol. + Returns nonzero if *MAP_TYPE was set. */ + +static int +get_map_sym_type (struct disassemble_info *info, + int n, + enum map_type *map_type) +{ + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; + + return is_mapping_symbol (info, n, map_type); +} + +/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. + Returns nonzero if *MAP_TYPE was set. */ + +static int +get_sym_code_type (struct disassemble_info *info, + int n, + enum map_type *map_type) +{ + elf_symbol_type *es; + unsigned int type; + + /* If the symbol is in a different section, ignore it. */ + if (info->section != NULL && info->section != info->symtab[n]->section) + return FALSE; + + es = *(elf_symbol_type **)(info->symtab + n); + type = ELF_ST_TYPE (es->internal_elf_sym.st_info); + + /* If the symbol has function type then use that. */ + if (type == STT_FUNC || type == STT_GNU_IFUNC) + { + if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB) + *map_type = MAP_THUMB; + else + *map_type = MAP_ARM; + return TRUE; + } + + return FALSE; +} + +/* Given a bfd_mach_arm_XXX value, this function fills in the fields + of the supplied arm_feature_set structure with bitmasks indicating + the support base architectures and coprocessor extensions. + + FIXME: This could more efficiently implemented as a constant array, + although it would also be less robust. */ + +static void +select_arm_features (unsigned long mach, + arm_feature_set * features) +{ +#undef ARM_FEATURE +#define ARM_FEATURE(ARCH,CEXT) \ + features->core = (ARCH); \ + features->coproc = (CEXT) | FPU_FPA; \ + return + + switch (mach) + { + case bfd_mach_arm_2: ARM_ARCH_V2; + case bfd_mach_arm_2a: ARM_ARCH_V2S; + case bfd_mach_arm_3: ARM_ARCH_V3; + case bfd_mach_arm_3M: ARM_ARCH_V3M; + case bfd_mach_arm_4: ARM_ARCH_V4; + case bfd_mach_arm_4T: ARM_ARCH_V4T; + case bfd_mach_arm_5: ARM_ARCH_V5; + case bfd_mach_arm_5T: ARM_ARCH_V5T; + case bfd_mach_arm_5TE: ARM_ARCH_V5TE; + case bfd_mach_arm_XScale: ARM_ARCH_XSCALE; + case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK); + case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT; + case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2; + /* If the machine type is unknown allow all + architecture types and all extensions. */ + case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL); + default: + abort (); + } +} + + +/* NOTE: There are no checks in these routines that + the relevant number of data bytes exist. */ + +static int +print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) +{ + unsigned char b[4]; + long given; + int status; + int is_thumb = FALSE; + int is_data = FALSE; + int little_code; + unsigned int size = 4; + void (*printer) (bfd_vma, struct disassemble_info *, long); + bfd_boolean found = FALSE; + struct arm_private_data *private_data; + + if (info->disassembler_options) + { + parse_disassembler_options (info->disassembler_options); + + /* To avoid repeated parsing of these options, we remove them here. */ + info->disassembler_options = NULL; + } + + /* PR 10288: Control which instructions will be disassembled. */ + if (info->private_data == NULL) + { + static struct arm_private_data private; + + if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) + /* If the user did not use the -m command line switch then default to + disassembling all types of ARM instruction. + + The info->mach value has to be ignored as this will be based on + the default archictecture for the target and/or hints in the notes + section, but it will never be greater than the current largest arm + machine value (iWMMXt2), which is only equivalent to the V5TE + architecture. ARM architectures have advanced beyond the machine + value encoding, and these newer architectures would be ignored if + the machine value was used. + + Ie the -m switch is used to restrict which instructions will be + disassembled. If it is necessary to use the -m switch to tell + objdump that an ARM binary is being disassembled, eg because the + input is a raw binary file, but it is also desired to disassemble + all ARM instructions then use "-marm". This will select the + "unknown" arm architecture which is compatible with any ARM + instruction. */ + info->mach = bfd_mach_arm_unknown; + + /* Compute the architecture bitmask from the machine number. + Note: This assumes that the machine number will not change + during disassembly.... */ + select_arm_features (info->mach, & private.features); + + private.has_mapping_symbols = -1; + + info->private_data = & private; + } + + private_data = info->private_data; + + /* Decide if our code is going to be little-endian, despite what the + function argument might say. */ + little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); + + /* For ELF, consult the symbol table to determine what kind of code + or data we have. */ + if (info->symtab_size != 0 + && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) + { + bfd_vma addr; + int n, start; + int last_sym = -1; + enum map_type type = MAP_ARM; + + /* Start scanning at the start of the function, or wherever + we finished last time. */ + start = info->symtab_pos + 1; + if (start < last_mapping_sym) + start = last_mapping_sym; + found = FALSE; + + /* First, look for mapping symbols. */ + if (private_data->has_mapping_symbols != 0) + { + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceeding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + + if (found) + private_data->has_mapping_symbols = 1; + + /* No mapping symbols were found. A leading $d may be + omitted for sections which start with data; but for + compatibility with legacy and stripped binaries, only + assume the leading $d if there is at least one mapping + symbol in the file. */ + if (!found && private_data->has_mapping_symbols == -1) + { + /* Look for mapping symbols, in any section. */ + for (n = 0; n < info->symtab_size; n++) + if (is_mapping_symbol (info, n, &type)) + { + private_data->has_mapping_symbols = 1; + break; + } + if (private_data->has_mapping_symbols == -1) + private_data->has_mapping_symbols = 0; + } + + if (!found && private_data->has_mapping_symbols == 1) + { + type = MAP_DATA; + found = TRUE; + } + } + + /* Next search for function symbols to separate ARM from Thumb + in binaries without mapping symbols. */ + if (!found) + { + /* Scan up to the location being disassembled. */ + for (n = start; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + /* No mapping symbol found at this address. Look backwards + for a preceeding one. */ + for (n = start - 1; n >= 0; n--) + { + if (get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + } + + last_mapping_sym = last_sym; + last_type = type; + is_thumb = (last_type == MAP_THUMB); + is_data = (last_type == MAP_DATA); + + /* Look a little bit ahead to see if we should print out + two or four bytes of data. If there's a symbol, + mapping or otherwise, after two bytes then don't + print more. */ + if (is_data) + { + size = 4 - (pc & 3); + for (n = last_sym + 1; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc + && (info->section == NULL + || info->section == info->symtab[n]->section)) + { + if (addr - pc < size) + size = addr - pc; + break; + } + } + /* If the next symbol is after three bytes, we need to + print only part of the data, so that we can use either + .byte or .short. */ + if (size == 3) + size = (pc & 1) ? 1 : 2; + } + } + + if (info->symbols != NULL) + { + if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) + { + coff_symbol_type * cs; + + cs = coffsymbol (*info->symbols); + is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT + || cs->native->u.syment.n_sclass == C_THUMBSTAT + || cs->native->u.syment.n_sclass == C_THUMBLABEL + || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC + || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); + } + else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour + && !found) + { + /* If no mapping symbol has been found then fall back to the type + of the function symbol. */ + elf_symbol_type * es; + unsigned int type; + + es = *(elf_symbol_type **)(info->symbols); + type = ELF_ST_TYPE (es->internal_elf_sym.st_info); + + is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) + == ST_BRANCH_TO_THUMB) + || type == STT_ARM_16BIT); + } + } + + if (force_thumb) + is_thumb = TRUE; + + if (is_data) + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + else + info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + + info->bytes_per_line = 4; + + /* PR 10263: Disassemble data if requested to do so by the user. */ + if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) + { + int i; + + /* Size was already set above. */ + info->bytes_per_chunk = size; + printer = print_insn_data; + + status = info->read_memory_func (pc, (bfd_byte *) b, size, info); + given = 0; + if (little) + for (i = size - 1; i >= 0; i--) + given = b[i] | (given << 8); + else + for (i = 0; i < (int) size; i++) + given = b[i] | (given << 8); + } + else if (!is_thumb) + { + /* In ARM mode endianness is a straightforward issue: the instruction + is four bytes long and is either ordered 0123 or 3210. */ + printer = print_insn_arm; + info->bytes_per_chunk = 4; + size = 4; + + status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); + if (little_code) + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + else + given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); + } + else + { + /* In Thumb mode we have the additional wrinkle of two + instruction lengths. Fortunately, the bits that determine + the length of the current instruction are always to be found + in the first two bytes. */ + printer = print_insn_thumb16; + info->bytes_per_chunk = 2; + size = 2; + + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + if (little_code) + given = (b[0]) | (b[1] << 8); + else + given = (b[1]) | (b[0] << 8); + + if (!status) + { + /* These bit patterns signal a four-byte Thumb + instruction. */ + if ((given & 0xF800) == 0xF800 + || (given & 0xF800) == 0xF000 + || (given & 0xF800) == 0xE800) + { + status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); + if (little_code) + given = (b[0]) | (b[1] << 8) | (given << 16); + else + given = (b[1]) | (b[0] << 8) | (given << 16); + + printer = print_insn_thumb32; + size = 4; + } + } + + if (ifthen_address != pc) + find_ifthen_state (pc, info, little_code); + + if (ifthen_state) + { + if ((ifthen_state & 0xf) == 0x8) + ifthen_next_state = 0; + else + ifthen_next_state = (ifthen_state & 0xe0) + | ((ifthen_state & 0xf) << 1); + } + } + + if (status) + { + info->memory_error_func (status, pc, info); + return -1; + } + if (info->flags & INSN_HAS_RELOC) + /* If the instruction has a reloc associated with it, then + the offset field in the instruction will actually be the + addend for the reloc. (We are using REL type relocs). + In such cases, we can ignore the pc when computing + addresses, since the addend is not currently pc-relative. */ + pc = 0; + + printer (pc, info, given); + + if (is_thumb) + { + ifthen_state = ifthen_next_state; + ifthen_address += size; + } + return size; +} + +int +print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) +{ + /* Detect BE8-ness and record it in the disassembler info. */ + if (info->flavour == bfd_target_elf_flavour + && info->section != NULL + && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) + info->endian_code = BFD_ENDIAN_LITTLE; + + return print_insn (pc, info, FALSE); +} + +int +print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) +{ + return print_insn (pc, info, TRUE); +} + +void +print_arm_disassembler_options (FILE *stream) +{ + int i; + + fprintf (stream, _("\n\ +The following ARM specific disassembler options are supported for use with\n\ +the -M switch:\n")); + + for (i = NUM_ARM_REGNAMES; i--;) + fprintf (stream, " reg-names-%s %*c%s\n", + regnames[i].name, + (int)(14 - strlen (regnames[i].name)), ' ', + regnames[i].description); + + fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); + fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); +} diff --git a/external/gpl3/gdb/dist/opcodes/avr-dis.c b/external/gpl3/gdb/dist/opcodes/avr-dis.c new file mode 100644 index 000000000000..85d7ab3fec61 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/avr-dis.c @@ -0,0 +1,402 @@ +/* Disassemble AVR instructions. + Copyright 1999, 2000, 2002, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + + Contributed by Denis Chertykov + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opintl.h" +#include "libiberty.h" + +struct avr_opcodes_s +{ + char *name; + char *constraints; + char *opcode; + int insn_size; /* In words. */ + int isa; + unsigned int bin_opcode; +}; + +#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ +{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN}, + +const struct avr_opcodes_s avr_opcodes[] = +{ + #include "opcode/avr.h" + {NULL, NULL, NULL, 0, 0, 0} +}; + +static const char * comment_start = "0x"; + +static int +avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint, + char *opcode_str, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr) +{ + int ok = 1; + *sym = 0; + + switch (constraint) + { + /* Any register operand. */ + case 'r': + if (regs) + insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */ + else + insn = (insn & 0x01f0) >> 4; /* Destination register. */ + + sprintf (buf, "r%d", insn); + break; + + case 'd': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 0xf)); + else + sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); + break; + + case 'w': + sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3)); + break; + + case 'a': + if (regs) + sprintf (buf, "r%d", 16 + (insn & 7)); + else + sprintf (buf, "r%d", 16 + ((insn >> 4) & 7)); + break; + + case 'v': + if (regs) + sprintf (buf, "r%d", (insn & 0xf) * 2); + else + sprintf (buf, "r%d", ((insn & 0xf0) >> 3)); + break; + + case 'e': + { + char *xyz; + + switch (insn & 0x100f) + { + case 0x0000: xyz = "Z"; break; + case 0x1001: xyz = "Z+"; break; + case 0x1002: xyz = "-Z"; break; + case 0x0008: xyz = "Y"; break; + case 0x1009: xyz = "Y+"; break; + case 0x100a: xyz = "-Y"; break; + case 0x100c: xyz = "X"; break; + case 0x100d: xyz = "X+"; break; + case 0x100e: xyz = "-X"; break; + default: xyz = "??"; ok = 0; + } + strcpy (buf, xyz); + + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + } + break; + + case 'z': + *buf++ = 'Z'; + + /* Check for post-increment. */ + char *s; + for (s = opcode_str; *s; ++s) + { + if (*s == '+') + { + *buf++ = '+'; + break; + } + } + + *buf = '\0'; + if (AVR_UNDEF_P (insn)) + sprintf (comment, _("undefined")); + break; + + case 'b': + { + unsigned int x; + + x = (insn & 7); + x |= (insn >> 7) & (3 << 3); + x |= (insn >> 8) & (1 << 5); + + if (insn & 0x8) + *buf++ = 'Y'; + else + *buf++ = 'Z'; + sprintf (buf, "+%d", x); + sprintf (comment, "0x%02x", x); + } + break; + + case 'h': + *sym = 1; + *sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2; + /* See PR binutils/2454. Ideally we would like to display the hex + value of the address only once, but this would mean recoding + objdump_print_address() which would affect many targets. */ + sprintf (buf, "%#lx", (unsigned long) *sym_addr); + strcpy (comment, comment_start); + break; + + case 'L': + { + int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2; + sprintf (buf, ".%+-8d", rel_addr); + *sym = 1; + *sym_addr = pc + 2 + rel_addr; + strcpy (comment, comment_start); + } + break; + + case 'l': + { + int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2; + + sprintf (buf, ".%+-8d", rel_addr); + *sym = 1; + *sym_addr = pc + 2 + rel_addr; + strcpy (comment, comment_start); + } + break; + + case 'i': + sprintf (buf, "0x%04X", insn2); + break; + + case 'M': + sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf)); + sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf)); + break; + + case 'n': + sprintf (buf, "??"); + fprintf (stderr, _("Internal disassembler error")); + ok = 0; + break; + + case 'K': + { + unsigned int x; + + x = (insn & 0xf) | ((insn >> 2) & 0x30); + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 's': + sprintf (buf, "%d", insn & 7); + break; + + case 'S': + sprintf (buf, "%d", (insn >> 4) & 7); + break; + + case 'P': + { + unsigned int x; + + x = (insn & 0xf); + x |= (insn >> 5) & 0x30; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 'p': + { + unsigned int x; + + x = (insn >> 3) & 0x1f; + sprintf (buf, "0x%02x", x); + sprintf (comment, "%d", x); + } + break; + + case 'E': + sprintf (buf, "%d", (insn >> 4) & 15); + break; + + case '?': + *buf = '\0'; + break; + + default: + sprintf (buf, "??"); + fprintf (stderr, _("unknown constraint `%c'"), constraint); + ok = 0; + } + + return ok; +} + +static unsigned short +avrdis_opcode (bfd_vma addr, disassemble_info *info) +{ + bfd_byte buffer[2]; + int status; + + status = info->read_memory_func (addr, buffer, 2, info); + + if (status == 0) + return bfd_getl16 (buffer); + + info->memory_error_func (status, addr, info); + return -1; +} + + +int +print_insn_avr (bfd_vma addr, disassemble_info *info) +{ + unsigned int insn, insn2; + const struct avr_opcodes_s *opcode; + static unsigned int *maskptr; + void *stream = info->stream; + fprintf_ftype prin = info->fprintf_func; + static unsigned int *avr_bin_masks; + static int initialized; + int cmd_len = 2; + int ok = 0; + char op1[20], op2[20], comment1[40], comment2[40]; + int sym_op1 = 0, sym_op2 = 0; + bfd_vma sym_addr1, sym_addr2; + + + if (!initialized) + { + unsigned int nopcodes; + + /* PR 4045: Try to avoid duplicating the 0x prefix that + objdump_print_addr() will put on addresses when there + is no symbol table available. */ + if (info->symtab_size == 0) + comment_start = " "; + + nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s); + + avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int)); + + for (opcode = avr_opcodes, maskptr = avr_bin_masks; + opcode->name; + opcode++, maskptr++) + { + char * s; + unsigned int bin = 0; + unsigned int mask = 0; + + for (s = opcode->opcode; *s; ++s) + { + bin <<= 1; + mask <<= 1; + bin |= (*s == '1'); + mask |= (*s == '1' || *s == '0'); + } + assert (s - opcode->opcode == 16); + assert (opcode->bin_opcode == bin); + *maskptr = mask; + } + + initialized = 1; + } + + insn = avrdis_opcode (addr, info); + + for (opcode = avr_opcodes, maskptr = avr_bin_masks; + opcode->name; + opcode++, maskptr++) + if ((insn & *maskptr) == opcode->bin_opcode) + break; + + /* Special case: disassemble `ldd r,b+0' as `ld r,b', and + `std b+0,r' as `st b,r' (next entry in the table). */ + + if (AVR_DISP0_P (insn)) + opcode++; + + op1[0] = 0; + op2[0] = 0; + comment1[0] = 0; + comment2[0] = 0; + + if (opcode->name) + { + char *constraints = opcode->constraints; + char *opcode_str = opcode->opcode; + + insn2 = 0; + ok = 1; + + if (opcode->insn_size > 1) + { + insn2 = avrdis_opcode (addr + 2, info); + cmd_len = 4; + } + + if (*constraints && *constraints != '?') + { + int regs = REGISTER_P (*constraints); + + ok = avr_operand (insn, insn2, addr, *constraints, opcode_str, op1, comment1, 0, &sym_op1, &sym_addr1); + + if (ok && *(++constraints) == ',') + ok = avr_operand (insn, insn2, addr, *(++constraints), opcode_str, op2, + *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2); + } + } + + if (!ok) + { + /* Unknown opcode, or invalid combination of operands. */ + sprintf (op1, "0x%04x", insn); + op2[0] = 0; + sprintf (comment1, "????"); + comment2[0] = 0; + } + + (*prin) (stream, "%s", ok ? opcode->name : ".word"); + + if (*op1) + (*prin) (stream, "\t%s", op1); + + if (*op2) + (*prin) (stream, ", %s", op2); + + if (*comment1) + (*prin) (stream, "\t; %s", comment1); + + if (sym_op1) + info->print_address_func (sym_addr1, info); + + if (*comment2) + (*prin) (stream, " %s", comment2); + + if (sym_op2) + info->print_address_func (sym_addr2, info); + + return cmd_len; +} diff --git a/external/gpl3/gdb/dist/opcodes/bfin-dis.c b/external/gpl3/gdb/dist/opcodes/bfin-dis.c new file mode 100644 index 000000000000..130dfc7719e5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/bfin-dis.c @@ -0,0 +1,4816 @@ +/* Disassemble ADI Blackfin Instructions. + Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include + +#include "opcode/bfin.h" + +#ifndef PRINTF +#define PRINTF printf +#endif + +#ifndef EXIT +#define EXIT exit +#endif + +typedef long TIword; + +#define HOST_LONG_WORD_SIZE (sizeof (long) * 8) +#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p)) +#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) +#define MASKBITS(val, bits) (val & ((1 << bits) - 1)) + +#include "dis-asm.h" + +typedef unsigned int bu32; + +static char comment = 0; +static char parallel = 0; + +typedef enum +{ + c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, + c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6, + c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, + c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, + c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e, +} const_forms_t; + +static const struct +{ + const char *name; + const int nbits; + const char reloc; + const char issigned; + const char pcrel; + const char scale; + const char offset; + const char negative; + const char positive; + const char decimal; + const char leading; + const char exact; +} constant_formats[] = +{ + { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0}, + { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0}, + { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, + { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0}, + { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}, + { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0}, + { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0}, + { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0}, + { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0}, + { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}, +}; + +static const char * +fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf) +{ + static char buf[60]; + + if (constant_formats[cf].reloc) + { + bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + + /* truncate to 32-bits for proper symbol lookup/matching */ + ea = (bu32)ea; + + if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact) + { + outf->print_address_func (ea, outf); + return ""; + } + else + { + sprintf (buf, "%lx", (unsigned long) x); + return buf; + } + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else + x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x; + + if (constant_formats[cf].offset) + x += constant_formats[cf].offset; + + if (constant_formats[cf].scale) + x <<= constant_formats[cf].scale; + + if (constant_formats[cf].decimal) + { + if (constant_formats[cf].leading) + { + char ps[10]; + sprintf (ps, "%%%ii", constant_formats[cf].leading); + sprintf (buf, ps, x); + } + else + sprintf (buf, "%li", x); + } + else + { + if (constant_formats[cf].issigned && x < 0) + sprintf (buf, "-0x%x", abs (x)); + else + sprintf (buf, "0x%lx", (unsigned long) x); + } + + return buf; +} + +static bu32 +fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc) +{ + if (0 && constant_formats[cf].reloc) + { + bu32 ea = (((constant_formats[cf].pcrel + ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) + << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + + return ea; + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else if (constant_formats[cf].issigned) + x = SIGNEXTEND (x, constant_formats[cf].nbits); + + x += constant_formats[cf].offset; + x <<= constant_formats[cf].scale; + + return x; +} + +enum machine_registers +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3, + REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w, + REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, + REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, + REG_L2, REG_L3, + REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S, + REG_AQ, REG_V, REG_VS, + REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, + REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, + REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, + REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, + REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, + REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, + REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, + REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, + REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, + REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, + REG_AC0_COPY, REG_V_COPY, REG_RND_MOD, + REG_LASTREG, +}; + +enum reg_class +{ + rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext, + rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs, + rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2, + rc_sysregs3, rc_allregs, + LIM_REG_CLASSES +}; + +static const char * const reg_names[] = +{ + "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", + "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3", + "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W", + "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1", + "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1", + "L2", "L3", + "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S", + "AQ", "V", "VS", + "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", + "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", + "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", + "RETE", "EMUDAT", + "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", + "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", + "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", + "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L", + "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L", + "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H", + "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H", + "AC0_COPY", "V_COPY", "RND_MOD", + "LASTREG", + 0 +}; + +#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......") + +/* RL(0..7). */ +static const enum machine_registers decode_dregs_lo[] = +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, +}; + +#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7]) + +/* RH(0..7). */ +static const enum machine_registers decode_dregs_hi[] = +{ + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, +}; + +#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7]) + +/* R(0..7). */ +static const enum machine_registers decode_dregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, +}; + +#define dregs(x) REGNAME (decode_dregs[(x) & 7]) + +/* R BYTE(0..7). */ +static const enum machine_registers decode_dregs_byte[] = +{ + REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, +}; + +#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7]) + +/* P(0..5) SP FP. */ +static const enum machine_registers decode_pregs[] = +{ + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define pregs(x) REGNAME (decode_pregs[(x) & 7]) +#define spfp(x) REGNAME (decode_spfp[(x) & 1]) +#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)]) +#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1]) +#define accum_word(x) REGNAME (decode_accum_word[(x) & 1]) +#define accum(x) REGNAME (decode_accum[(x) & 1]) + +/* I(0..3). */ +static const enum machine_registers decode_iregs[] = +{ + REG_I0, REG_I1, REG_I2, REG_I3, +}; + +#define iregs(x) REGNAME (decode_iregs[(x) & 3]) + +/* M(0..3). */ +static const enum machine_registers decode_mregs[] = +{ + REG_M0, REG_M1, REG_M2, REG_M3, +}; + +#define mregs(x) REGNAME (decode_mregs[(x) & 3]) +#define bregs(x) REGNAME (decode_bregs[(x) & 3]) +#define lregs(x) REGNAME (decode_lregs[(x) & 3]) + +/* dregs pregs. */ +static const enum machine_registers decode_dpregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define dpregs(x) REGNAME (decode_dpregs[(x) & 15]) + +/* [dregs pregs]. */ +static const enum machine_registers decode_gregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, +}; + +#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs)]. */ +static const enum machine_registers decode_regs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, +}; + +#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */ +static const enum machine_registers decode_regs_lo[] = +{ + REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7, + REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, + REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3, + REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3, +}; + +#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)]) + +/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */ +static const enum machine_registers decode_regs_hi[] = +{ + REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7, + REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP, + REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3, + REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3, +}; + +#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)]) + +static const enum machine_registers decode_statbits[] = +{ + REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY, + REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG, + REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG, + REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_V, REG_VS, REG_LASTREG, REG_LASTREG, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, +}; + +#define statbits(x) REGNAME (decode_statbits[(x) & 31]) + +/* LC0 LC1. */ +static const enum machine_registers decode_counters[] = +{ + REG_LC0, REG_LC1, +}; + +#define counters(x) REGNAME (decode_counters[(x) & 1]) +#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7]) + +/* [dregs pregs (iregs mregs) (bregs lregs) + dregs2_sysregs1 open sysregs2 sysregs3]. */ +static const enum machine_registers decode_allregs[] = +{ + REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS, + REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, + REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, + REG_LASTREG, +}; + +#define IS_DREG(g,r) ((g) == 0 && (r) < 8) +#define IS_PREG(g,r) ((g) == 1 && (r) < 8) +#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4) +#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r)) +#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8) +#define IS_SYSREG(g,r) \ + (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7) +#define IS_RESERVEDREG(g,r) \ + (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5) + +#define allreg(r,g) (!IS_RESERVEDREG (g, r)) +#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r))) + +#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)]) +#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf) +#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf) +#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf) +#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf) +#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf) +#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf) +#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf) +#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf) +#define rimm16(x) fmtconst (c_rimm16, x, 0, outf) +#define huimm16(x) fmtconst (c_huimm16, x, 0, outf) +#define imm16(x) fmtconst (c_imm16, x, 0, outf) +#define imm16d(x) fmtconst (c_imm16d, x, 0, outf) +#define uimm2(x) fmtconst (c_uimm2, x, 0, outf) +#define uimm3(x) fmtconst (c_uimm3, x, 0, outf) +#define luimm16(x) fmtconst (c_luimm16, x, 0, outf) +#define uimm4(x) fmtconst (c_uimm4, x, 0, outf) +#define uimm5(x) fmtconst (c_uimm5, x, 0, outf) +#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf) +#define uimm8(x) fmtconst (c_uimm8, x, 0, outf) +#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf) +#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf) +#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf) +#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf) +#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf) +#define imm3(x) fmtconst (c_imm3, x, 0, outf) +#define imm4(x) fmtconst (c_imm4, x, 0, outf) +#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf) +#define imm5(x) fmtconst (c_imm5, x, 0, outf) +#define imm5d(x) fmtconst (c_imm5d, x, 0, outf) +#define imm6(x) fmtconst (c_imm6, x, 0, outf) +#define imm7(x) fmtconst (c_imm7, x, 0, outf) +#define imm7d(x) fmtconst (c_imm7d, x, 0, outf) +#define imm8(x) fmtconst (c_imm8, x, 0, outf) +#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf) +#define uimm16(x) fmtconst (c_uimm16, x, 0, outf) +#define uimm32(x) fmtconst (c_uimm32, x, 0, outf) +#define imm32(x) fmtconst (c_imm32, x, 0, outf) +#define huimm32(x) fmtconst (c_huimm32, x, 0, outf) +#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf) +#define imm7_val(x) fmtconst_val (c_imm7, x, 0) +#define imm16_val(x) fmtconst_val (c_uimm16, x, 0) +#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0) + +/* (arch.pm)arch_disassembler_functions. */ +#ifndef OUTS +#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt) +#endif + +static void +amod0 (int s0, int x0, disassemble_info *outf) +{ + if (s0 == 1 && x0 == 0) + OUTS (outf, " (S)"); + else if (s0 == 0 && x0 == 1) + OUTS (outf, " (CO)"); + else if (s0 == 1 && x0 == 1) + OUTS (outf, " (SCO)"); +} + +static void +amod1 (int s0, int x0, disassemble_info *outf) +{ + if (s0 == 0 && x0 == 0) + OUTS (outf, " (NS)"); + else if (s0 == 1 && x0 == 0) + OUTS (outf, " (S)"); +} + +static void +amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf) +{ + if (s0 == 1 && x0 == 0 && aop0 == 0) + OUTS (outf, " (S)"); + else if (s0 == 0 && x0 == 1 && aop0 == 0) + OUTS (outf, " (CO)"); + else if (s0 == 1 && x0 == 1 && aop0 == 0) + OUTS (outf, " (SCO)"); + else if (s0 == 0 && x0 == 0 && aop0 == 2) + OUTS (outf, " (ASR)"); + else if (s0 == 1 && x0 == 0 && aop0 == 2) + OUTS (outf, " (S, ASR)"); + else if (s0 == 0 && x0 == 1 && aop0 == 2) + OUTS (outf, " (CO, ASR)"); + else if (s0 == 1 && x0 == 1 && aop0 == 2) + OUTS (outf, " (SCO, ASR)"); + else if (s0 == 0 && x0 == 0 && aop0 == 3) + OUTS (outf, " (ASL)"); + else if (s0 == 1 && x0 == 0 && aop0 == 3) + OUTS (outf, " (S, ASL)"); + else if (s0 == 0 && x0 == 1 && aop0 == 3) + OUTS (outf, " (CO, ASL)"); + else if (s0 == 1 && x0 == 1 && aop0 == 3) + OUTS (outf, " (SCO, ASL)"); +} + +static void +searchmod (int r0, disassemble_info *outf) +{ + if (r0 == 0) + OUTS (outf, "GT"); + else if (r0 == 1) + OUTS (outf, "GE"); + else if (r0 == 2) + OUTS (outf, "LT"); + else if (r0 == 3) + OUTS (outf, "LE"); +} + +static void +aligndir (int r0, disassemble_info *outf) +{ + if (r0 == 1) + OUTS (outf, " (R)"); +} + +static int +decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) +{ + const char *s0, *s1; + + if (h0) + s0 = dregs_hi (src0); + else + s0 = dregs_lo (src0); + + if (h1) + s1 = dregs_hi (src1); + else + s1 = dregs_lo (src1); + + OUTS (outf, s0); + OUTS (outf, " * "); + OUTS (outf, s1); + return 0; +} + +static int +decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) +{ + const char *a; + const char *sop = ""; + + if (which) + a = "A1"; + else + a = "A0"; + + if (op == 3) + { + OUTS (outf, a); + return 0; + } + + switch (op) + { + case 0: sop = " = "; break; + case 1: sop = " += "; break; + case 2: sop = " -= "; break; + default: break; + } + + OUTS (outf, a); + OUTS (outf, sop); + decode_multfunc (h0, h1, src0, src1, outf); + + return 0; +} + +static void +decode_optmode (int mod, int MM, disassemble_info *outf) +{ + if (mod == 0 && MM == 0) + return; + + OUTS (outf, " ("); + + if (MM && !mod) + { + OUTS (outf, "M)"); + return; + } + + if (MM) + OUTS (outf, "M, "); + + if (mod == M_S2RND) + OUTS (outf, "S2RND"); + else if (mod == M_T) + OUTS (outf, "T"); + else if (mod == M_W32) + OUTS (outf, "W32"); + else if (mod == M_FU) + OUTS (outf, "FU"); + else if (mod == M_TFU) + OUTS (outf, "TFU"); + else if (mod == M_IS) + OUTS (outf, "IS"); + else if (mod == M_ISS2) + OUTS (outf, "ISS2"); + else if (mod == M_IH) + OUTS (outf, "IH"); + else if (mod == M_IU) + OUTS (outf, "IU"); + else + abort (); + + OUTS (outf, ")"); +} + +static struct saved_state +{ + bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4]; + bu32 ax[2], aw[2]; + bu32 lt[2], lc[2], lb[2]; + bu32 rets; +} saved_state; + +#define DREG(x) (saved_state.dpregs[x]) +#define GREG(x, i) DPREG ((x) | ((i) << 3)) +#define DPREG(x) (saved_state.dpregs[x]) +#define DREG(x) (saved_state.dpregs[x]) +#define PREG(x) (saved_state.dpregs[(x) + 8]) +#define SPREG PREG (6) +#define FPREG PREG (7) +#define IREG(x) (saved_state.iregs[x]) +#define MREG(x) (saved_state.mregs[x]) +#define BREG(x) (saved_state.bregs[x]) +#define LREG(x) (saved_state.lregs[x]) +#define AXREG(x) (saved_state.ax[x]) +#define AWREG(x) (saved_state.aw[x]) +#define LCREG(x) (saved_state.lc[x]) +#define LTREG(x) (saved_state.lt[x]) +#define LBREG(x) (saved_state.lb[x]) +#define RETSREG (saved_state.rets) + +static bu32 * +get_allreg (int grp, int reg) +{ + int fullreg = (grp << 3) | reg; + /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS, + , , , , , , , , + REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, + REG_CYCLES2, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, + REG_LASTREG */ + switch (fullreg >> 2) + { + case 0: case 1: return &DREG (reg); + case 2: case 3: return &PREG (reg); + case 4: return &IREG (reg & 3); + case 5: return &MREG (reg & 3); + case 6: return &BREG (reg & 3); + case 7: return &LREG (reg & 3); + default: + switch (fullreg) + { + case 32: return &AXREG (0); + case 33: return &AWREG (0); + case 34: return &AXREG (1); + case 35: return &AWREG (1); + case 39: return &RETSREG; + case 48: return &LCREG (0); + case 49: return <REG (0); + case 50: return &LBREG (0); + case 51: return &LCREG (1); + case 52: return <REG (1); + case 53: return &LBREG (1); + } + } + abort (); +} + +static int +decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf) +{ + /* ProgCtrl + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); + int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); + + if (prgfunc == 0 && poprnd == 0) + OUTS (outf, "NOP"); + else if (parallel) + return 0; + else if (prgfunc == 1 && poprnd == 0) + OUTS (outf, "RTS"); + else if (prgfunc == 1 && poprnd == 1) + OUTS (outf, "RTI"); + else if (prgfunc == 1 && poprnd == 2) + OUTS (outf, "RTX"); + else if (prgfunc == 1 && poprnd == 3) + OUTS (outf, "RTN"); + else if (prgfunc == 1 && poprnd == 4) + OUTS (outf, "RTE"); + else if (prgfunc == 2 && poprnd == 0) + OUTS (outf, "IDLE"); + else if (prgfunc == 2 && poprnd == 3) + OUTS (outf, "CSYNC"); + else if (prgfunc == 2 && poprnd == 4) + OUTS (outf, "SSYNC"); + else if (prgfunc == 2 && poprnd == 5) + OUTS (outf, "EMUEXCPT"); + else if (prgfunc == 3 && IS_DREG (0, poprnd)) + { + OUTS (outf, "CLI "); + OUTS (outf, dregs (poprnd)); + } + else if (prgfunc == 4 && IS_DREG (0, poprnd)) + { + OUTS (outf, "STI "); + OUTS (outf, dregs (poprnd)); + } + else if (prgfunc == 5 && IS_PREG (1, poprnd)) + { + OUTS (outf, "JUMP ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 6 && IS_PREG (1, poprnd)) + { + OUTS (outf, "CALL ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 7 && IS_PREG (1, poprnd)) + { + OUTS (outf, "CALL (PC + "); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 8 && IS_PREG (1, poprnd)) + { + OUTS (outf, "JUMP (PC + "); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else if (prgfunc == 9) + { + OUTS (outf, "RAISE "); + OUTS (outf, uimm4 (poprnd)); + } + else if (prgfunc == 10) + { + OUTS (outf, "EXCPT "); + OUTS (outf, uimm4 (poprnd)); + } + else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5) + { + OUTS (outf, "TESTSET ("); + OUTS (outf, pregs (poprnd)); + OUTS (outf, ")"); + } + else + return 0; + return 2; +} + +static int +decode_CaCTRL_0 (TIword iw0, disassemble_info *outf) +{ + /* CaCTRL + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask); + int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask); + int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask); + + if (parallel) + return 0; + + if (a == 0 && op == 0) + { + OUTS (outf, "PREFETCH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 1) + { + OUTS (outf, "FLUSHINV["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 2) + { + OUTS (outf, "FLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 0 && op == 3) + { + OUTS (outf, "IFLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "]"); + } + else if (a == 1 && op == 0) + { + OUTS (outf, "PREFETCH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 1) + { + OUTS (outf, "FLUSHINV["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 2) + { + OUTS (outf, "FLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else if (a == 1 && op == 3) + { + OUTS (outf, "IFLUSH["); + OUTS (outf, pregs (reg)); + OUTS (outf, "++]"); + } + else + return 0; + return 2; +} + +static int +decode_PushPopReg_0 (TIword iw0, disassemble_info *outf) +{ + /* PushPopReg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask); + int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask); + int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask); + + if (parallel) + return 0; + + if (W == 0 && mostreg (reg, grp)) + { + OUTS (outf, allregs (reg, grp)); + OUTS (outf, " = [SP++]"); + } + else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6)) + { + OUTS (outf, "[--SP] = "); + OUTS (outf, allregs (reg, grp)); + } + else + return 0; + return 2; +} + +static int +decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf) +{ + /* PushPopMultiple + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask); + int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask); + int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); + int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); + int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); + + if (parallel) + return 0; + + if (pr > 5) + return 0; + + if (W == 1 && d == 1 && p == 1) + { + OUTS (outf, "[--SP] = (R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ", P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ")"); + } + else if (W == 1 && d == 1 && p == 0 && pr == 0) + { + OUTS (outf, "[--SP] = (R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ")"); + } + else if (W == 1 && d == 0 && p == 1 && dr == 0) + { + OUTS (outf, "[--SP] = (P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ")"); + } + else if (W == 0 && d == 1 && p == 1) + { + OUTS (outf, "(R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ", P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ") = [SP++]"); + } + else if (W == 0 && d == 1 && p == 0 && pr == 0) + { + OUTS (outf, "(R7:"); + OUTS (outf, imm5d (dr)); + OUTS (outf, ") = [SP++]"); + } + else if (W == 0 && d == 0 && p == 1 && dr == 0) + { + OUTS (outf, "(P5:"); + OUTS (outf, imm5d (pr)); + OUTS (outf, ") = [SP++]"); + } + else + return 0; + return 2; +} + +static int +decode_ccMV_0 (TIword iw0, disassemble_info *outf) +{ + /* ccMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask); + int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask); + int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask); + int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask); + int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask); + + if (parallel) + return 0; + + if (T == 1) + { + OUTS (outf, "IF CC "); + OUTS (outf, gregs (dst, d)); + OUTS (outf, " = "); + OUTS (outf, gregs (src, s)); + } + else if (T == 0) + { + OUTS (outf, "IF !CC "); + OUTS (outf, gregs (dst, d)); + OUTS (outf, " = "); + OUTS (outf, gregs (src, s)); + } + else + return 0; + return 2; +} + +static int +decode_CCflag_0 (TIword iw0, disassemble_info *outf) +{ + /* CCflag + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask); + int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask); + int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask); + int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask); + int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask); + + if (parallel) + return 0; + + if (opc == 0 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " == "); + OUTS (outf, dregs (y)); + } + else if (opc == 1 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, dregs (y)); + } + else if (opc == 2 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, dregs (y)); + } + else if (opc == 3 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, dregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 0 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, dregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " == "); + OUTS (outf, imm3 (y)); + } + else if (opc == 1 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, imm3 (y)); + } + else if (opc == 2 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, imm3 (y)); + } + else if (opc == 3 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " < "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 1 && G == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (x)); + OUTS (outf, " <= "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " == "); + OUTS (outf, pregs (y)); + } + else if (opc == 1 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, pregs (y)); + } + else if (opc == 2 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, pregs (y)); + } + else if (opc == 3 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, pregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 0 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, pregs (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 0 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " == "); + OUTS (outf, imm3 (y)); + } + else if (opc == 1 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, imm3 (y)); + } + else if (opc == 2 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, imm3 (y)); + } + else if (opc == 3 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " < "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 4 && I == 1 && G == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, pregs (x)); + OUTS (outf, " <= "); + OUTS (outf, uimm3 (y)); + OUTS (outf, " (IU)"); + } + else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 == A1"); + + else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 < A1"); + + else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0) + OUTS (outf, "CC = A0 <= A1"); + + else + return 0; + return 2; +} + +static int +decode_CC2dreg_0 (TIword iw0, disassemble_info *outf) +{ + /* CC2dreg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask); + int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask); + + if (parallel) + return 0; + + if (op == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = CC"); + } + else if (op == 1) + { + OUTS (outf, "CC = "); + OUTS (outf, dregs (reg)); + } + else if (op == 3 && reg == 0) + OUTS (outf, "CC = !CC"); + else + return 0; + + return 2; +} + +static int +decode_CC2stat_0 (TIword iw0, disassemble_info *outf) +{ + /* CC2stat + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask); + int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask); + int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask); + + const char *bitname = statbits (cbit); + + if (parallel) + return 0; + + if (decode_statbits[cbit] == REG_LASTREG) + { + /* All ASTAT bits except CC may be operated on in hardware, but may + not have a dedicated insn, so still decode "valid" insns. */ + static char bitnames[64]; + if (cbit != 5) + sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit); + else + return 0; + + bitname = bitnames; + } + + if (op == 0 && D == 0) + { + OUTS (outf, "CC = "); + OUTS (outf, bitname); + } + else if (op == 1 && D == 0) + { + OUTS (outf, "CC |= "); + OUTS (outf, bitname); + } + else if (op == 2 && D == 0) + { + OUTS (outf, "CC &= "); + OUTS (outf, bitname); + } + else if (op == 3 && D == 0) + { + OUTS (outf, "CC ^= "); + OUTS (outf, bitname); + } + else if (op == 0 && D == 1) + { + OUTS (outf, bitname); + OUTS (outf, " = CC"); + } + else if (op == 1 && D == 1) + { + OUTS (outf, bitname); + OUTS (outf, " |= CC"); + } + else if (op == 2 && D == 1) + { + OUTS (outf, bitname); + OUTS (outf, " &= CC"); + } + else if (op == 3 && D == 1) + { + OUTS (outf, bitname); + OUTS (outf, " ^= CC"); + } + else + return 0; + + return 2; +} + +static int +decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) +{ + /* BRCC + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask); + int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask); + int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask); + + if (parallel) + return 0; + + if (T == 1 && B == 1) + { + OUTS (outf, "IF CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + OUTS (outf, " (BP)"); + } + else if (T == 0 && B == 1) + { + OUTS (outf, "IF !CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + OUTS (outf, " (BP)"); + } + else if (T == 1) + { + OUTS (outf, "IF CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + } + else if (T == 0) + { + OUTS (outf, "IF !CC JUMP 0x"); + OUTS (outf, pcrel10 (offset)); + } + else + return 0; + + return 2; +} + +static int +decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf) +{ + /* UJUMP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 0 |.offset........................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); + + if (parallel) + return 0; + + OUTS (outf, "JUMP.S 0x"); + OUTS (outf, pcrel12 (offset)); + return 2; +} + +static int +decode_REGMV_0 (TIword iw0, disassemble_info *outf) +{ + /* REGMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask); + int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask); + int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); + int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); + + /* Reserved slots cannot be a src/dst. */ + if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst)) + goto invalid_move; + + /* Standard register moves */ + if ((gs < 2) || /* Dregs/Pregs as source */ + (gd < 2) || /* Dregs/Pregs as dest */ + (gs == 4 && src < 4) || /* Accumulators as source */ + (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */ + (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */ + (gd == 7 && dst == 7)) /* EMUDAT as dest */ + goto valid_move; + + /* dareg = dareg (IMBL) */ + if (gs < 4 && gd < 4) + goto valid_move; + + /* USP can be src to sysregs, but not dagregs. */ + if ((gs == 7 && src == 0) && (gd >= 4)) + goto valid_move; + + /* USP can move between genregs (only check Accumulators). */ + if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) || + ((gd == 7 && dst == 0) && (gs == 4 && src < 4))) + goto valid_move; + + /* Still here ? Invalid reg pair. */ + invalid_move: + return 0; + + valid_move: + OUTS (outf, allregs (dst, gd)); + OUTS (outf, " = "); + OUTS (outf, allregs (src, gs)); + return 2; +} + +static int +decode_ALU2op_0 (TIword iw0, disassemble_info *outf) +{ + /* ALU2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask); + int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask); + int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask); + + if (opc == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>>= "); + OUTS (outf, dregs (src)); + } + else if (opc == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>= "); + OUTS (outf, dregs (src)); + } + else if (opc == 2) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " <<= "); + OUTS (outf, dregs (src)); + } + else if (opc == 3) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " *= "); + OUTS (outf, dregs (src)); + } + else if (opc == 4) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, dregs (dst)); + OUTS (outf, " + "); + OUTS (outf, dregs (src)); + OUTS (outf, ") << 0x1"); + } + else if (opc == 5) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, dregs (dst)); + OUTS (outf, " + "); + OUTS (outf, dregs (src)); + OUTS (outf, ") << 0x2"); + } + else if (opc == 8) + { + OUTS (outf, "DIVQ ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, dregs (src)); + OUTS (outf, ")"); + } + else if (opc == 9) + { + OUTS (outf, "DIVS ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, dregs (src)); + OUTS (outf, ")"); + } + else if (opc == 10) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src)); + OUTS (outf, " (X)"); + } + else if (opc == 11) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src)); + OUTS (outf, " (Z)"); + } + else if (opc == 12) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_byte (src)); + OUTS (outf, " (X)"); + } + else if (opc == 13) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs_byte (src)); + OUTS (outf, " (Z)"); + } + else if (opc == 14) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src)); + } + else if (opc == 15) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " =~ "); + OUTS (outf, dregs (src)); + } + else + return 0; + + return 2; +} + +static int +decode_PTR2op_0 (TIword iw0, disassemble_info *outf) +{ + /* PTR2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask); + int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask); + int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask); + + if (opc == 0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " -= "); + OUTS (outf, pregs (src)); + } + else if (opc == 1) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " << 0x2"); + } + else if (opc == 3) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " >> 0x2"); + } + else if (opc == 4) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src)); + OUTS (outf, " >> 0x1"); + } + else if (opc == 5) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " += "); + OUTS (outf, pregs (src)); + OUTS (outf, " (BREV)"); + } + else if (opc == 6) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, pregs (dst)); + OUTS (outf, " + "); + OUTS (outf, pregs (src)); + OUTS (outf, ") << 0x1"); + } + else if (opc == 7) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = ("); + OUTS (outf, pregs (dst)); + OUTS (outf, " + "); + OUTS (outf, pregs (src)); + OUTS (outf, ") << 0x2"); + } + else + return 0; + + return 2; +} + +static int +decode_LOGI2op_0 (TIword iw0, disassemble_info *outf) +{ + /* LOGI2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask); + int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask); + int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask); + + if (parallel) + return 0; + + if (opc == 0) + { + OUTS (outf, "CC = !BITTST ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; + } + else if (opc == 1) + { + OUTS (outf, "CC = BITTST ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; + } + else if (opc == 2) + { + OUTS (outf, "BITSET ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; + } + else if (opc == 3) + { + OUTS (outf, "BITTGL ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; + } + else if (opc == 4) + { + OUTS (outf, "BITCLR ("); + OUTS (outf, dregs (dst)); + OUTS (outf, ", "); + OUTS (outf, uimm5 (src)); + OUTS (outf, ");\t\t/* bit"); + OUTS (outf, imm7d (src)); + OUTS (outf, " */"); + comment = 1; + } + else if (opc == 5) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>>= "); + OUTS (outf, uimm5 (src)); + } + else if (opc == 6) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " >>= "); + OUTS (outf, uimm5 (src)); + } + else if (opc == 7) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " <<= "); + OUTS (outf, uimm5 (src)); + } + else + return 0; + + return 2; +} + +static int +decode_COMP3op_0 (TIword iw0, disassemble_info *outf) +{ + /* COMP3op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask); + int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask); + int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); + int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); + + if (opc == 5 && src1 == src0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " << 0x1"); + } + else if (opc == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + } + else if (opc == 2) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " & "); + OUTS (outf, dregs (src1)); + } + else if (opc == 3) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " | "); + OUTS (outf, dregs (src1)); + } + else if (opc == 4) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " ^ "); + OUTS (outf, dregs (src1)); + } + else if (opc == 5) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + "); + OUTS (outf, pregs (src1)); + } + else if (opc == 6) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + ("); + OUTS (outf, pregs (src1)); + OUTS (outf, " << 0x1)"); + } + else if (opc == 7) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, pregs (src0)); + OUTS (outf, " + ("); + OUTS (outf, pregs (src1)); + OUTS (outf, " << 0x2)"); + } + else if (opc == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + } + else + return 0; + + return 2; +} + +static int +decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf) +{ + /* COMPI2opD + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask); + int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); + int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); + + bu32 *pval = get_allreg (0, dst); + + if (parallel) + return 0; + + /* Since we don't have 32-bit immediate loads, we allow the disassembler + to combine them, so it prints out the right values. + Here we keep track of the registers. */ + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + + if (op == 0) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " = "); + OUTS (outf, imm7 (src)); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, dregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; + } + else if (op == 1) + { + OUTS (outf, dregs (dst)); + OUTS (outf, " += "); + OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + comment = 1; + } + else + return 0; + + return 2; +} + +static int +decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf) +{ + /* COMPI2opP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask); + int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); + int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); + + bu32 *pval = get_allreg (1, dst); + + if (parallel) + return 0; + + if (op == 0) + { + *pval = imm7_val (src); + if (src & 0x40) + *pval |= 0xFFFFFF80; + else + *pval &= 0x7F; + } + + if (op == 0) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " = "); + OUTS (outf, imm7 (src)); + OUTS (outf, " (X);\t\t/*\t\t"); + OUTS (outf, pregs (dst)); + OUTS (outf, "="); + OUTS (outf, uimm32 (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; + } + else if (op == 1) + { + OUTS (outf, pregs (dst)); + OUTS (outf, " += "); + OUTS (outf, imm7 (src)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm7d (src)); + OUTS (outf, ") */"); + comment = 1; + } + else + return 0; + + return 2; +} + +static int +decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTpmod + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); + int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); + int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); + int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); + int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); + + if (aop == 1 && W == 0 && idx == ptr) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && idx == ptr) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 1 && W == 1 && idx == ptr) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1 && idx == ptr) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 1 && W == 0) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "]"); + } + else if (aop == 3 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] (Z)"); + } + else if (aop == 3 && W == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] (X)"); + } + else if (aop == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " ++ "); + OUTS (outf, pregs (idx)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_dagMODim_0 (TIword iw0, disassemble_info *outf) +{ + /* dagMODim + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); + int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask); + int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask); + int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); + + if (op == 0 && br == 1) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += "); + OUTS (outf, mregs (m)); + OUTS (outf, " (BREV)"); + } + else if (op == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += "); + OUTS (outf, mregs (m)); + } + else if (op == 1 && br == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= "); + OUTS (outf, mregs (m)); + } + else + return 0; + + return 2; +} + +static int +decode_dagMODik_0 (TIword iw0, disassemble_info *outf) +{ + /* dagMODik + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); + int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask); + + if (op == 0) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += 0x2"); + } + else if (op == 1) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= 0x2"); + } + else if (op == 2) + { + OUTS (outf, iregs (i)); + OUTS (outf, " += 0x4"); + } + else if (op == 3) + { + OUTS (outf, iregs (i)); + OUTS (outf, " -= 0x4"); + } + else + return 0; + + if (! parallel) + { + OUTS (outf, ";\t\t/* ( "); + if (op == 0 || op == 1) + OUTS (outf, "2"); + else if (op == 2 || op == 3) + OUTS (outf, "4"); + OUTS (outf, ") */"); + comment = 1; + } + + return 2; +} + +static int +decode_dspLDST_0 (TIword iw0, disassemble_info *outf) +{ + /* dspLDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); + int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); + int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); + int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); + int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); + + if (aop == 0 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 0 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 0 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++]"); + } + else if (aop == 1 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 1 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 1 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--]"); + } + else if (aop == 2 && W == 0 && m == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && m == 1) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 2 && W == 0 && m == 2) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = W["); + OUTS (outf, iregs (i)); + OUTS (outf, "]"); + } + else if (aop == 0 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 0 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "++] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 1 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 1 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "--] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 2 && W == 1 && m == 0) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && W == 1 && m == 1) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs_lo (reg)); + } + else if (aop == 2 && W == 1 && m == 2) + { + OUTS (outf, "W["); + OUTS (outf, iregs (i)); + OUTS (outf, "] = "); + OUTS (outf, dregs_hi (reg)); + } + else if (aop == 3 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, iregs (i)); + OUTS (outf, " ++ "); + OUTS (outf, mregs (m)); + OUTS (outf, "]"); + } + else if (aop == 3 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, iregs (i)); + OUTS (outf, " ++ "); + OUTS (outf, mregs (m)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDST_0 (TIword iw0, disassemble_info *outf) +{ + /* LDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); + int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); + int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); + int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); + int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); + int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask); + + if (aop == 0 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++]"); + } + else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++]"); + } + else if (aop == 0 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (Z)"); + } + else if (aop == 0 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (X)"); + } + else if (aop == 0 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (Z)"); + } + else if (aop == 0 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] (X)"); + } + else if (aop == 1 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--]"); + } + else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--]"); + } + else if (aop == 1 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (Z)"); + } + else if (aop == 1 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (X)"); + } + else if (aop == 1 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (Z)"); + } + else if (aop == 1 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] (X)"); + } + else if (aop == 2 && sz == 0 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && sz == 0 && Z == 1 && W == 0) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "]"); + } + else if (aop == 2 && sz == 1 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (Z)"); + } + else if (aop == 2 && sz == 1 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (X)"); + } + else if (aop == 2 && sz == 2 && Z == 0 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (Z)"); + } + else if (aop == 2 && sz == 2 && Z == 1 && W == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] (X)"); + } + else if (aop == 0 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 0 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 0 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "++] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 1 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 1 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "--] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 0 && Z == 0 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 0 && Z == 1 && W == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else if (aop == 2 && sz == 1 && Z == 0 && W == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (aop == 2 && sz == 2 && Z == 0 && W == 1) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTiiFP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask); + int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask); + int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); + + if (W == 0) + { + OUTS (outf, dpregs (reg)); + OUTS (outf, " = [FP "); + OUTS (outf, negimm5s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 1) + { + OUTS (outf, "[FP "); + OUTS (outf, negimm5s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dpregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LDSTii_0 (TIword iw0, disassemble_info *outf) +{ + /* LDSTii + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); + int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask); + int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask); + int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); + int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); + + if (W == 0 && op == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && op == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && op == 2) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 0 && op == 3) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 1 && op == 0) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && op == 1) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s2 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && op == 3) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, uimm4s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else + return 0; + + return 2; +} + +static int +decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) +{ + /* LoopSetup + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| + |.reg...........| - | - |.eoffset...............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask); + int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask); + int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask); + int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask); + int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask); + + if (parallel) + return 0; + + if (reg > 7) + return 0; + + if (rop == 0) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + } + else if (rop == 1) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + OUTS (outf, " = "); + OUTS (outf, pregs (reg)); + } + else if (rop == 3) + { + OUTS (outf, "LSETUP"); + OUTS (outf, "(0x"); + OUTS (outf, pcrel4 (soffset)); + OUTS (outf, ", 0x"); + OUTS (outf, lppcrel10 (eoffset)); + OUTS (outf, ") "); + OUTS (outf, counters (c)); + OUTS (outf, " = "); + OUTS (outf, pregs (reg)); + OUTS (outf, " >> 0x1"); + } + else + return 0; + + return 4; +} + +static int +decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* LDIMMhalf + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| + |.hword.........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask); + int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask); + int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask); + int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask); + int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask); + int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask); + + bu32 *pval = get_allreg (grp, reg); + + if (parallel) + return 0; + + /* Since we don't have 32-bit immediate loads, we allow the disassembler + to combine them, so it prints out the right values. + Here we keep track of the registers. */ + if (H == 0 && S == 1 && Z == 0) + { + /* regs = imm16 (x) */ + *pval = imm16_val (hword); + if (hword & 0x8000) + *pval |= 0xFFFF0000; + else + *pval &= 0xFFFF; + } + else if (H == 0 && S == 0 && Z == 1) + { + /* regs = luimm16 (Z) */ + *pval = luimm16_val (hword); + *pval &= 0xFFFF; + } + else if (H == 0 && S == 0 && Z == 0) + { + /* regs_lo = luimm16 */ + *pval &= 0xFFFF0000; + *pval |= luimm16_val (hword); + } + else if (H == 1 && S == 0 && Z == 0) + { + /* regs_hi = huimm16 */ + *pval &= 0xFFFF; + *pval |= luimm16_val (hword) << 16; + } + + /* Here we do the disassembly */ + if (grp == 0 && H == 0 && S == 0 && Z == 0) + { + OUTS (outf, dregs_lo (reg)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (grp == 0 && H == 1 && S == 0 && Z == 0) + { + OUTS (outf, dregs_hi (reg)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (grp == 0 && H == 0 && S == 1 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = "); + OUTS (outf, imm16 (hword)); + OUTS (outf, " (X)"); + } + else if (H == 0 && S == 1 && Z == 0) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, imm16 (hword)); + OUTS (outf, " (X)"); + } + else if (H == 0 && S == 0 && Z == 1) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + OUTS (outf, " (Z)"); + } + else if (H == 0 && S == 0 && Z == 0) + { + OUTS (outf, regs_lo (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else if (H == 1 && S == 0 && Z == 0) + { + OUTS (outf, regs_hi (reg, grp)); + OUTS (outf, " = "); + OUTS (outf, uimm16 (hword)); + } + else + return 0; + + /* And we print out the 32-bit value if it is a pointer. */ + if (S == 0 && Z == 0) + { + OUTS (outf, ";\t\t/* ("); + OUTS (outf, imm16d (hword)); + OUTS (outf, ")\t"); + + /* If it is an MMR, don't print the symbol. */ + if (*pval < 0xFFC00000 && grp == 1) + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + } + else + { + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ")"); + } + + OUTS (outf, " */"); + comment = 1; + } + if (S == 1 || Z == 1) + { + OUTS (outf, ";\t\t/*\t\t"); + OUTS (outf, regs (reg, grp)); + OUTS (outf, "=0x"); + OUTS (outf, huimm32e (*pval)); + OUTS (outf, "("); + OUTS (outf, imm32 (*pval)); + OUTS (outf, ") */"); + comment = 1; + } + return 4; +} + +static int +decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf) +{ + /* CALLa + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| + |.lsw...........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask); + int lsw = ((iw1 >> 0) & 0xffff); + int msw = ((iw0 >> 0) & 0xff); + + if (parallel) + return 0; + + if (S == 1) + OUTS (outf, "CALL 0x"); + else if (S == 0) + OUTS (outf, "JUMP.L 0x"); + else + return 0; + + OUTS (outf, pcrel24 (((msw) << 16) | (lsw))); + return 4; +} + +static int +decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* LDSTidxI + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| + |.offset........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask); + int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask); + int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask); + int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask); + int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask); + int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); + + if (W == 0 && sz == 0 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && sz == 0 && Z == 1) + { + OUTS (outf, pregs (reg)); + OUTS (outf, " = ["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "]"); + } + else if (W == 0 && sz == 1 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && sz == 1 && Z == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 0 && sz == 2 && Z == 0) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] (Z)"); + } + else if (W == 0 && sz == 2 && Z == 1) + { + OUTS (outf, dregs (reg)); + OUTS (outf, " = B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] (X)"); + } + else if (W == 1 && sz == 0 && Z == 0) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && sz == 0 && Z == 1) + { + OUTS (outf, "["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s4 (offset)); + OUTS (outf, "] = "); + OUTS (outf, pregs (reg)); + } + else if (W == 1 && sz == 1 && Z == 0) + { + OUTS (outf, "W["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16s2 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else if (W == 1 && sz == 2 && Z == 0) + { + OUTS (outf, "B["); + OUTS (outf, pregs (ptr)); + OUTS (outf, " + "); + OUTS (outf, imm16 (offset)); + OUTS (outf, "] = "); + OUTS (outf, dregs (reg)); + } + else + return 0; + + return 4; +} + +static int +decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* linkage + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| + |.framesize.....................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask); + int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask); + + if (parallel) + return 0; + + if (R == 0) + { + OUTS (outf, "LINK "); + OUTS (outf, uimm16s4 (framesize)); + OUTS (outf, ";\t\t/* ("); + OUTS (outf, uimm16s4d (framesize)); + OUTS (outf, ") */"); + comment = 1; + } + else if (R == 1) + OUTS (outf, "UNLINK"); + else + return 0; + + return 4; +} + +static int +decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32mac + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) + return 0; + + if (op1 == 3 && MM) + return 0; + + if ((w1 || w0) && mmod == M_W32) + return 0; + + if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) + return 0; + + if (w1 == 1 || op1 != 3) + { + if (w1) + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); + + if (op1 == 3) + OUTS (outf, " = A1"); + else + { + if (w1) + OUTS (outf, " = ("); + decode_macfunc (1, op1, h01, h11, src0, src1, outf); + if (w1) + OUTS (outf, ")"); + } + + if (w0 == 1 || op0 != 3) + { + if (MM) + OUTS (outf, " (M)"); + OUTS (outf, ", "); + } + } + + if (w0 == 1 || op0 != 3) + { + /* Clear MM option since it only matters for MAC1, and if we made + it this far, we've already shown it or we want to ignore it. */ + MM = 0; + + if (w0) + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); + + if (op0 == 3) + OUTS (outf, " = A0"); + else + { + if (w0) + OUTS (outf, " = ("); + decode_macfunc (0, op0, h00, h10, src0, src1, outf); + if (w0) + OUTS (outf, ")"); + } + } + + decode_optmode (mmod, MM, outf); + + return 4; +} + +static int +decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32mult + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + if (w1 == 0 && w0 == 0) + return 0; + + if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) + return 0; + + if (w1) + { + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); + OUTS (outf, " = "); + decode_multfunc (h01, h11, src0, src1, outf); + + if (w0) + { + if (MM) + OUTS (outf, " (M)"); + MM = 0; + OUTS (outf, ", "); + } + } + + if (w0) + { + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); + OUTS (outf, " = "); + decode_multfunc (h00, h10, src0, src1, outf); + } + + decode_optmode (mmod, MM, outf); + return 4; +} + +static int +decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32alu + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| + |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); + int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); + int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); + int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); + int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask); + int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); + int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); + int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); + int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); + + if (aop == 0 && aopcde == 9 && HL == 0 && s == 0) + { + OUTS (outf, "A0.L = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0) + { + OUTS (outf, "A1.H = "); + OUTS (outf, dregs_hi (src0)); + } + else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0) + { + OUTS (outf, "A1.L = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0) + { + OUTS (outf, "A0.H = "); + OUTS (outf, dregs_hi (src0)); + } + else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND20)"); + } + else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + OUTS (outf, " (RND12)"); + } + else if (HL == 1 && aop == 0 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 1 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 2 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 3 && aopcde == 2) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 0 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 1 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 3 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 0 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 1 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 2 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 1 && aop == 3 && aopcde == 3) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 2 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 1 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 2 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 3 && aopcde == 3) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs_hi (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aop == 0 && aopcde == 2) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs_lo (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 9 && s == 1) + { + OUTS (outf, "A0 = "); + OUTS (outf, dregs (src0)); + } + else if (aop == 3 && aopcde == 11 && s == 0) + OUTS (outf, "A0 -= A1"); + + else if (aop == 3 && aopcde == 11 && s == 1) + OUTS (outf, "A0 -= A1 (W32)"); + + else if (aop == 1 && aopcde == 22 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TH"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 1 && aopcde == 22 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (TL"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 22 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDH"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 22 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP2P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (RNDL"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && s == 0 && aopcde == 8) + OUTS (outf, "A0 = 0"); + + else if (aop == 0 && s == 1 && aopcde == 8) + OUTS (outf, "A0 = A0 (S)"); + + else if (aop == 1 && s == 0 && aopcde == 8) + OUTS (outf, "A1 = 0"); + + else if (aop == 1 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A1 (S)"); + + else if (aop == 2 && s == 0 && aopcde == 8) + OUTS (outf, "A1 = A0 = 0"); + + else if (aop == 2 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A1 (S), A0 = A0 (S)"); + + else if (aop == 3 && s == 0 && aopcde == 8) + OUTS (outf, "A0 = A1"); + + else if (aop == 3 && s == 1 && aopcde == 8) + OUTS (outf, "A1 = A0"); + + else if (aop == 1 && aopcde == 9 && s == 0) + { + OUTS (outf, "A0.X = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 1 && HL == 0 && aopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 3 && HL == 0 && aopcde == 16) + OUTS (outf, "A1 = ABS A1, A0 = ABS A0"); + + else if (aop == 0 && aopcde == 23 && HL == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP3P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (HI"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 3 && aopcde == 9 && s == 0) + { + OUTS (outf, "A1.X = "); + OUTS (outf, dregs_lo (src0)); + } + else if (aop == 1 && HL == 1 && aopcde == 16) + OUTS (outf, "A1 = ABS A1"); + + else if (aop == 0 && HL == 1 && aopcde == 16) + OUTS (outf, "A1 = ABS A0"); + + else if (aop == 2 && aopcde == 9 && s == 1) + { + OUTS (outf, "A1 = "); + OUTS (outf, dregs (src0)); + } + else if (HL == 0 && aop == 3 && aopcde == 12) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (RND)"); + } + else if (aop == 1 && HL == 0 && aopcde == 16) + OUTS (outf, "A0 = ABS A1"); + + else if (aop == 0 && HL == 0 && aopcde == 16) + OUTS (outf, "A0 = ABS A0"); + + else if (aop == 3 && HL == 0 && aopcde == 15) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (V)"); + } + else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (S)"); + } + else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = -"); + OUTS (outf, dregs (src0)); + OUTS (outf, " (NS)"); + } + else if (aop == 1 && HL == 1 && aopcde == 11) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 2 && aopcde == 11 && s == 0) + OUTS (outf, "A0 += A1"); + + else if (aop == 2 && aopcde == 11 && s == 1) + OUTS (outf, "A0 += A1 (W32)"); + + else if (aop == 3 && HL == 0 && aopcde == 14) + OUTS (outf, "A1 = -A1, A0 = -A0"); + + else if (HL == 1 && aop == 3 && aopcde == 12) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (RND)"); + } + else if (aop == 0 && aopcde == 23 && HL == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP3P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (LO"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && HL == 0 && aopcde == 14) + OUTS (outf, "A0 = -A0"); + + else if (aop == 1 && HL == 0 && aopcde == 14) + OUTS (outf, "A0 = -A1"); + + else if (aop == 0 && HL == 1 && aopcde == 14) + OUTS (outf, "A1 = -A0"); + + else if (aop == 1 && HL == 1 && aopcde == 14) + OUTS (outf, "A1 = -A1"); + + else if (aop == 0 && aopcde == 12) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGN ("); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ") * "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " + SIGN ("); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") * "); + OUTS (outf, dregs_lo (src1)); + } + else if (aop == 2 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|+ "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 1 && aopcde == 12) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A1.L + A1.H, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A0.L + A0.H"); + } + else if (aop == 2 && aopcde == 4) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (HL == 0 && aopcde == 1) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|+ "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|- "); + OUTS (outf, dregs (src1)); + amod0amod2 (s, x, aop, outf); + } + else if (aop == 0 && aopcde == 11) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = (A0 += A1)"); + } + else if (aop == 0 && aopcde == 10) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = A0.X"); + } + else if (aop == 1 && aopcde == 10) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = A1.X"); + } + else if (aop == 1 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|- "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 3 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|- "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 1 && aopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " - "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 17) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A1 + A0, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A1 - A0"); + amod1 (s, x, outf); + } + else if (aop == 1 && aopcde == 17) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = A0 + A1, "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = A0 - A1"); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 18) + { + OUTS (outf, "SAA ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 3 && aopcde == 18) + OUTS (outf, "DISALGNEXCPT"); + + else if (aop == 0 && aopcde == 20) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP1P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 1 && aopcde == 20) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEOP1P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ") (T"); + if (s == 1) + OUTS (outf, ", R)"); + else + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 21) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEOP16P ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 1 && aopcde == 21) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEOP16M ("); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src1)); + OUTS (outf, ")"); + aligndir (s, outf); + } + else if (aop == 2 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ABS "); + OUTS (outf, dregs (src0)); + } + else if (aop == 1 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MIN ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 0 && aopcde == 7) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MAX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 2 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ABS "); + OUTS (outf, dregs (src0)); + OUTS (outf, " (V)"); + } + else if (aop == 1 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MIN ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (V)"); + } + else if (aop == 0 && aopcde == 6) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = MAX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (V)"); + } + else if (HL == 1 && aopcde == 1) + { + OUTS (outf, dregs (dst1)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|- "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " -|+ "); + OUTS (outf, dregs (src1)); + amod0amod2 (s, x, aop, outf); + } + else if (aop == 0 && aopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " + "); + OUTS (outf, dregs (src1)); + amod1 (s, x, outf); + } + else if (aop == 0 && aopcde == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src0)); + OUTS (outf, " +|+ "); + OUTS (outf, dregs (src1)); + amod0 (s, x, outf); + } + else if (aop == 0 && aopcde == 24) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = BYTEPACK ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ")"); + } + else if (aop == 1 && aopcde == 24) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = BYTEUNPACK "); + OUTS (outf, dregs (src0 + 1)); + OUTS (outf, ":"); + OUTS (outf, imm5d (src0)); + aligndir (s, outf); + } + else if (aopcde == 13) + { + OUTS (outf, "("); + OUTS (outf, dregs (dst1)); + OUTS (outf, ", "); + OUTS (outf, dregs (dst0)); + OUTS (outf, ") = SEARCH "); + OUTS (outf, dregs (src0)); + OUTS (outf, " ("); + searchmod (aop, outf); + OUTS (outf, ")"); + } + else + return 0; + + return 4; +} + +static int +decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32shift + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); + int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); + int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); + int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); + int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); + int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); + const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1"; + + if (HLs == 0 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 1 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 2 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 3 && sop == 0 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (HLs == 0 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 1 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 2 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (HLs == 3 && sop == 1 && sopcde == 0) + { + OUTS (outf, dregs_hi (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 0) + { + OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 0 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = ASHIFT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = LSHIFT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 2 && sopcde == 3) + { + OUTS (outf, acc01); + OUTS (outf, " = ROT "); + OUTS (outf, acc01); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 3 && sopcde == 3) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V, S)"); + } + else if (sop == 0 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 1 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ASHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 3 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + } + else if (sop == 2 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = LSHIFT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ")"); + } + else if (sop == 2 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 4) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = PACK ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_hi (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs (src1)); + } + else if (sop == 1 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs_lo (src1)); + } + else if (sop == 2 && sopcde == 5) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS "); + OUTS (outf, dregs_hi (src1)); + } + else if (sop == 0 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS A0"); + } + else if (sop == 1 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = SIGNBITS A1"); + } + else if (sop == 3 && sopcde == 6) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = ONES "); + OUTS (outf, dregs (src1)); + } + else if (sop == 0 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (V)"); + } + else if (sop == 2 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs_lo (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 7) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = EXPADJ ("); + OUTS (outf, dregs_hi (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 8) + { + OUTS (outf, "BITMUX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", A0) (ASR)"); + } + else if (sop == 1 && sopcde == 8) + { + OUTS (outf, "BITMUX ("); + OUTS (outf, dregs (src0)); + OUTS (outf, ", "); + OUTS (outf, dregs (src1)); + OUTS (outf, ", A0) (ASL)"); + } + else if (sop == 0 && sopcde == 9) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (ASL)"); + } + else if (sop == 1 && sopcde == 9) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ") (ASR)"); + } + else if (sop == 2 && sopcde == 9) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (ASL)"); + } + else if (sop == 3 && sopcde == 9) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = VIT_MAX ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (ASR)"); + } + else if (sop == 0 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = EXTRACT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (Z)"); + } + else if (sop == 1 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = EXTRACT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs_lo (src0)); + OUTS (outf, ") (X)"); + } + else if (sop == 2 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = DEPOSIT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 3 && sopcde == 10) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = DEPOSIT ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ") (X)"); + } + else if (sop == 0 && sopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXORSHIFT (A0, "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 11) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXOR (A0, "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 0 && sopcde == 12) + OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)"); + + else if (sop == 1 && sopcde == 12) + { + OUTS (outf, dregs_lo (dst0)); + OUTS (outf, " = CC = BXOR (A0, A1, CC)"); + } + else if (sop == 0 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN8 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 1 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN16 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else if (sop == 2 && sopcde == 13) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ALIGN24 ("); + OUTS (outf, dregs (src1)); + OUTS (outf, ", "); + OUTS (outf, dregs (src0)); + OUTS (outf, ")"); + } + else + return 0; + + return 4; +} + +static int +decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* dsp32shiftimm + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......|.immag.................|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask); + int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); + int bit8 = ((iw1 >> 8) & 0x1); + int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); + int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); + int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); + + if (sop == 0 && sopcde == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm4 (newimmag)); + } + else if (sop == 1 && sopcde == 0 && bit8 == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm4 (immag)); + OUTS (outf, " (S)"); + } + else if (sop == 1 && sopcde == 0 && bit8 == 1) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm4 (newimmag)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 0 && bit8 == 0) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm4 (immag)); + } + else if (sop == 2 && sopcde == 0 && bit8 == 1) + { + OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0)); + OUTS (outf, " = "); + OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm4 (newimmag)); + } + else if (sop == 2 && sopcde == 3 && HLs == 1) + { + OUTS (outf, "A1 = ROT A1 BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0) + { + OUTS (outf, "A0 = A0 << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1) + { + OUTS (outf, "A0 = A0 >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0) + { + OUTS (outf, "A1 = A1 << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1) + { + OUTS (outf, "A1 = A1 >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 1 && sopcde == 3 && HLs == 0) + { + OUTS (outf, "A0 = A0 >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 1 && sopcde == 3 && HLs == 1) + { + OUTS (outf, "A1 = A1 >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 2 && sopcde == 3 && HLs == 0) + { + OUTS (outf, "A0 = ROT A0 BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 1 && sopcde == 1 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + OUTS (outf, " (V, S)"); + } + else if (sop == 1 && sopcde == 1 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, imm5 (-immag)); + OUTS (outf, " (V, S)"); + } + else if (sop == 2 && sopcde == 1 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm5 (newimmag)); + OUTS (outf, " (V)"); + } + else if (sop == 2 && sopcde == 1 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, imm5 (immag)); + OUTS (outf, " (V)"); + } + else if (sop == 0 && sopcde == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm5 (newimmag)); + OUTS (outf, " (V)"); + } + else if (sop == 1 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + OUTS (outf, " (S)"); + } + else if (sop == 2 && sopcde == 2 && bit8 == 1) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >> "); + OUTS (outf, uimm5 (newimmag)); + } + else if (sop == 2 && sopcde == 2 && bit8 == 0) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " << "); + OUTS (outf, uimm5 (immag)); + } + else if (sop == 3 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = ROT "); + OUTS (outf, dregs (src1)); + OUTS (outf, " BY "); + OUTS (outf, imm6 (immag)); + } + else if (sop == 0 && sopcde == 2) + { + OUTS (outf, dregs (dst0)); + OUTS (outf, " = "); + OUTS (outf, dregs (src1)); + OUTS (outf, " >>> "); + OUTS (outf, uimm5 (newimmag)); + } + else + return 0; + + return 4; +} + +static int +decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf) +{ + /* pseudoDEBUG + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); + int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask); + int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); + + if (parallel) + return 0; + + if (reg == 0 && fn == 3) + OUTS (outf, "DBG A0"); + + else if (reg == 1 && fn == 3) + OUTS (outf, "DBG A1"); + + else if (reg == 3 && fn == 3) + OUTS (outf, "ABORT"); + + else if (reg == 4 && fn == 3) + OUTS (outf, "HLT"); + + else if (reg == 5 && fn == 3) + OUTS (outf, "DBGHALT"); + + else if (reg == 6 && fn == 3) + { + OUTS (outf, "DBGCMPLX ("); + OUTS (outf, dregs (grp)); + OUTS (outf, ")"); + } + else if (reg == 7 && fn == 3) + OUTS (outf, "DBG"); + + else if (grp == 0 && fn == 2) + { + OUTS (outf, "OUTC "); + OUTS (outf, dregs (reg)); + } + else if (fn == 0) + { + OUTS (outf, "DBG "); + OUTS (outf, allregs (reg, grp)); + } + else if (fn == 1) + { + OUTS (outf, "PRNT "); + OUTS (outf, allregs (reg, grp)); + } + else + return 0; + + return 2; +} + +static int +decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf) +{ + /* psedoOChar + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask); + + if (parallel) + return 0; + + OUTS (outf, "OUTC "); + OUTS (outf, uimm8 (ch)); + + return 2; +} + +static int +decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf) +{ + /* pseudodbg_assert + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| + |.expected......................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); + int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask); + int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask); + int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask); + + if (parallel) + return 0; + + if (dbgop == 0) + { + OUTS (outf, "DBGA ("); + OUTS (outf, regs_lo (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 1) + { + OUTS (outf, "DBGA ("); + OUTS (outf, regs_hi (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 2) + { + OUTS (outf, "DBGAL ("); + OUTS (outf, allregs (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else if (dbgop == 3) + { + OUTS (outf, "DBGAH ("); + OUTS (outf, allregs (regtest, grp)); + OUTS (outf, ", "); + OUTS (outf, uimm16 (expected)); + OUTS (outf, ")"); + } + else + return 0; + return 4; +} + +static int +_print_insn_bfin (bfd_vma pc, disassemble_info *outf) +{ + bfd_byte buf[4]; + TIword iw0; + TIword iw1; + int status; + int rv = 0; + + status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf); + /* FIXME */ + (void) status; + status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf); + /* FIXME */ + (void) status; + + iw0 = bfd_getl16 (buf); + iw1 = bfd_getl16 (buf + 2); + + if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800) + { + if (parallel) + { + OUTS (outf, "ILLEGAL"); + return 0; + } + OUTS (outf, "MNOP"); + return 4; + } + else if ((iw0 & 0xff00) == 0x0000) + rv = decode_ProgCtrl_0 (iw0, outf); + else if ((iw0 & 0xffc0) == 0x0240) + rv = decode_CaCTRL_0 (iw0, outf); + else if ((iw0 & 0xff80) == 0x0100) + rv = decode_PushPopReg_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x0400) + rv = decode_PushPopMultiple_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x0600) + rv = decode_ccMV_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x0800) + rv = decode_CCflag_0 (iw0, outf); + else if ((iw0 & 0xffe0) == 0x0200) + rv = decode_CC2dreg_0 (iw0, outf); + else if ((iw0 & 0xff00) == 0x0300) + rv = decode_CC2stat_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x1000) + rv = decode_BRCC_0 (iw0, pc, outf); + else if ((iw0 & 0xf000) == 0x2000) + rv = decode_UJUMP_0 (iw0, pc, outf); + else if ((iw0 & 0xf000) == 0x3000) + rv = decode_REGMV_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0x4000) + rv = decode_ALU2op_0 (iw0, outf); + else if ((iw0 & 0xfe00) == 0x4400) + rv = decode_PTR2op_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x4800) + rv = decode_LOGI2op_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x5000) + rv = decode_COMP3op_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x6000) + rv = decode_COMPI2opD_0 (iw0, outf); + else if ((iw0 & 0xf800) == 0x6800) + rv = decode_COMPI2opP_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x8000) + rv = decode_LDSTpmod_0 (iw0, outf); + else if ((iw0 & 0xff60) == 0x9e60) + rv = decode_dagMODim_0 (iw0, outf); + else if ((iw0 & 0xfff0) == 0x9f60) + rv = decode_dagMODik_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0x9c00) + rv = decode_dspLDST_0 (iw0, outf); + else if ((iw0 & 0xf000) == 0x9000) + rv = decode_LDST_0 (iw0, outf); + else if ((iw0 & 0xfc00) == 0xb800) + rv = decode_LDSTiiFP_0 (iw0, outf); + else if ((iw0 & 0xe000) == 0xA000) + rv = decode_LDSTii_0 (iw0, outf); + else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000) + rv = decode_LoopSetup_0 (iw0, iw1, pc, outf); + else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000) + rv = decode_LDIMMhalf_0 (iw0, iw1, outf); + else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000) + rv = decode_CALLa_0 (iw0, iw1, pc, outf); + else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000) + rv = decode_LDSTidxI_0 (iw0, iw1, outf); + else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000) + rv = decode_linkage_0 (iw0, iw1, outf); + else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32mac_0 (iw0, iw1, outf); + else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32mult_0 (iw0, iw1, outf); + else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32alu_0 (iw0, iw1, outf); + else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000) + rv = decode_dsp32shift_0 (iw0, iw1, outf); + else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000) + rv = decode_dsp32shiftimm_0 (iw0, iw1, outf); + else if ((iw0 & 0xff00) == 0xf800) + rv = decode_pseudoDEBUG_0 (iw0, outf); + else if ((iw0 & 0xFF00) == 0xF900) + rv = decode_pseudoOChar_0 (iw0, outf); + else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000) + rv = decode_pseudodbg_assert_0 (iw0, iw1, outf); + + if (rv == 0) + OUTS (outf, "ILLEGAL"); + + return rv; +} + +int +print_insn_bfin (bfd_vma pc, disassemble_info *outf) +{ + bfd_byte buf[2]; + unsigned short iw0; + int status; + int count = 0; + + status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf); + /* FIXME */ + (void) status; + iw0 = bfd_getl16 (buf); + + count += _print_insn_bfin (pc, outf); + + /* Proper display of multiple issue instructions. */ + + if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS) + && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ )) + { + int legal = 1; + int len; + + parallel = 1; + OUTS (outf, " || "); + len = _print_insn_bfin (pc + 4, outf); + OUTS (outf, " || "); + if (len != 2) + legal = 0; + len = _print_insn_bfin (pc + 6, outf); + if (len != 2) + legal = 0; + + if (legal) + count = 8; + else + { + OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */"); + comment = 1; + count = 0; + } + parallel = 0; + } + + if (!comment) + OUTS (outf, ";"); + + if (count == 0) + return 2; + + comment = 0; + + return count; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-asm.c b/external/gpl3/gdb/dist/opcodes/cgen-asm.c new file mode 100644 index 000000000000..f5fde408290c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-asm.c @@ -0,0 +1,364 @@ +/* CGEN generic assembler support code. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" +#include "opintl.h" + +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_asm_hash_table (CGEN_CPU_DESC); + +/* Set the cgen_parse_operand_fn callback. */ + +void +cgen_set_parse_operand_fn (CGEN_CPU_DESC cd, cgen_parse_operand_fn fn) +{ + cd->parse_operand_fn = fn; +} + +/* Called whenever starting to parse an insn. */ + +void +cgen_init_parse_operand (CGEN_CPU_DESC cd) +{ + /* This tells the callback to re-initialize. */ + (void) (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL); +} + +/* Subroutine of build_asm_hash_table to add INSNS to the hash table. + + COUNT is the number of elements in INSNS. + ENTSIZE is sizeof (CGEN_IBASE) for the target. + ??? No longer used but leave in for now. + HTABLE points to the hash table. + HENTBUF is a pointer to sufficiently large buffer of hash entries. + The result is a pointer to the next entry to use. + + The table is scanned backwards as additions are made to the front of the + list and we want earlier ones to be prefered. */ + +static CGEN_INSN_LIST * +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN *insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) +{ + int i; + + for (i = count - 1; i >= 0; --i, ++hentbuf) + { + unsigned int hash; + const CGEN_INSN *insn = &insns[i]; + + if (! (* cd->asm_hash_p) (insn)) + continue; + hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (insn)); + hentbuf->next = htable[hash]; + hentbuf->insn = insn; + htable[hash] = hentbuf; + } + + return hentbuf; +} + +/* Subroutine of build_asm_hash_table to add INSNS to the hash table. + This function is identical to hash_insn_array except the insns are + in a list. */ + +static CGEN_INSN_LIST * +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) +{ + const CGEN_INSN_LIST *ilist; + + for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) + { + unsigned int hash; + + if (! (* cd->asm_hash_p) (ilist->insn)) + continue; + hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); + hentbuf->next = htable[hash]; + hentbuf->insn = ilist->insn; + htable[hash] = hentbuf; + } + + return hentbuf; +} + +/* Build the assembler instruction hash table. */ + +static void +build_asm_hash_table (CGEN_CPU_DESC cd) +{ + int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); + CGEN_INSN_TABLE *insn_table = &cd->insn_table; + CGEN_INSN_TABLE *macro_insn_table = &cd->macro_insn_table; + unsigned int hash_size = cd->asm_hash_size; + CGEN_INSN_LIST *hash_entry_buf; + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + asm_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); + memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); + asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) + xmalloc (count * sizeof (CGEN_INSN_LIST)); + + /* Add compiled in insns. + Don't include the first one as it is a reserved entry. */ + /* ??? It was the end of all hash chains, and also the special + "invalid insn" marker. May be able to do it differently now. */ + + hash_entry_buf = hash_insn_array (cd, + insn_table->init_entries + 1, + insn_table->num_init_entries - 1, + insn_table->entry_size, + asm_hash_table, hash_entry_buf); + + /* Add compiled in macro-insns. */ + + hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, + macro_insn_table->num_init_entries, + macro_insn_table->entry_size, + asm_hash_table, hash_entry_buf); + + /* Add runtime added insns. + Later added insns will be prefered over earlier ones. */ + + hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, + asm_hash_table, hash_entry_buf); + + /* Add runtime added macro-insns. */ + + hash_insn_list (cd, macro_insn_table->new_entries, + asm_hash_table, hash_entry_buf); + + cd->asm_hash_table = asm_hash_table; + cd->asm_hash_table_entries = asm_hash_table_entries; +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_asm_lookup_insn (CGEN_CPU_DESC cd, const char *insn) +{ + unsigned int hash; + + if (cd->asm_hash_table == NULL) + build_asm_hash_table (cd); + + hash = (* cd->asm_hash) (insn); + return cd->asm_hash_table[hash]; +} + +/* Keyword parser. + The result is NULL upon success or an error message. + If successful, *STRP is updated to point passed the keyword. + + ??? At present we have a static notion of how to pick out a keyword. + Later we can allow a target to customize this if necessary [say by + recording something in the keyword table]. */ + +const char * +cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + CGEN_KEYWORD *keyword_table, + long *valuep) +{ + const CGEN_KEYWORD_ENTRY *ke; + char buf[256]; + const char *p,*start; + + if (keyword_table->name_hash_table == NULL) + (void) cgen_keyword_search_init (keyword_table, NULL); + + p = start = *strp; + + /* Allow any first character. This is to make life easier for + the fairly common case of suffixes, eg. 'ld.b.w', where the first + character of the suffix ('.') is special. */ + if (*p) + ++p; + + /* Allow letters, digits, and any special characters. */ + while (((p - start) < (int) sizeof (buf)) + && *p + && (ISALNUM (*p) + || *p == '_' + || strchr (keyword_table->nonalpha_chars, *p))) + ++p; + + if (p - start >= (int) sizeof (buf)) + { + /* All non-empty CGEN keywords can fit into BUF. The only thing + we can match here is the empty keyword. */ + buf[0] = 0; + } + else + { + memcpy (buf, start, p - start); + buf[p - start] = 0; + } + + ke = cgen_keyword_lookup_name (keyword_table, buf); + + if (ke != NULL) + { + *valuep = ke->value; + /* Don't advance pointer if we recognized the null keyword. */ + if (ke->name[0] != 0) + *strp = p; + return NULL; + } + + return "unrecognized keyword/register name"; +} + +/* Parse a small signed integer parser. + ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. + Note that if the caller expects a bfd_vma result, it should call + cgen_parse_address. */ + +const char * +cgen_parse_signed_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + *valuep = value; + return errmsg; +} + +/* Parse a small unsigned integer parser. + ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. + Note that if the caller expects a bfd_vma result, it should call + cgen_parse_address. */ + +const char * +cgen_parse_unsigned_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + &result, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + *valuep = value; + return errmsg; +} + +/* Address parser. */ + +const char * +cgen_parse_address (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result *resultp, + bfd_vma *valuep) +{ + bfd_vma value; + enum cgen_parse_operand_result result_type; + const char *errmsg; + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_ADDRESS, strp, opindex, opinfo, + &result_type, &value); + /* FIXME: Examine `result'. */ + if (!errmsg) + { + if (resultp != NULL) + *resultp = result_type; + *valuep = value; + } + return errmsg; +} + +/* Signed integer validation routine. */ + +const char * +cgen_validate_signed_integer (long value, long min, long max) +{ + if (value < min || value > max) + { + static char buf[100]; + + /* xgettext:c-format */ + sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), + value, min, max); + return buf; + } + + return NULL; +} + +/* Unsigned integer validation routine. + Supplying `min' here may seem unnecessary, but we also want to handle + cases where min != 0 (and max > LONG_MAX). */ + +const char * +cgen_validate_unsigned_integer (unsigned long value, + unsigned long min, + unsigned long max) +{ + if (value < min || value > max) + { + static char buf[100]; + + /* xgettext:c-format */ + sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), + value, min, max); + return buf; + } + + return NULL; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-asm.in b/external/gpl3/gdb/dist/opcodes/cgen-asm.in new file mode 100644 index 000000000000..be34ef56e068 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-asm.in @@ -0,0 +1,435 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by @arch@_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +@arch@_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-bitset.c b/external/gpl3/gdb/dist/opcodes/cgen-bitset.c new file mode 100644 index 000000000000..34d31d71c19f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-bitset.c @@ -0,0 +1,173 @@ +/* CGEN generic opcode support. + Copyright 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Functions for manipulating CGEN_BITSET. */ + +#include "libiberty.h" +#include "cgen/bitset.h" +#include + +/* Create a bit mask. */ + +CGEN_BITSET * +cgen_bitset_create (unsigned bit_count) +{ + CGEN_BITSET * mask = xmalloc (sizeof (* mask)); + cgen_bitset_init (mask, bit_count); + return mask; +} + +/* Initialize an existing bit mask. */ + +void +cgen_bitset_init (CGEN_BITSET * mask, unsigned bit_count) +{ + if (! mask) + return; + mask->length = (bit_count / 8) + 1; + mask->bits = xmalloc (mask->length); + cgen_bitset_clear (mask); +} + +/* Clear the bits of a bit mask. */ + +void +cgen_bitset_clear (CGEN_BITSET * mask) +{ + unsigned i; + + if (! mask) + return; + + for (i = 0; i < mask->length; ++i) + mask->bits[i] = 0; +} + +/* Add a bit to a bit mask. */ + +void +cgen_bitset_add (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return; + byte_ix = bit_num / 8; + bit_ix = bit_num % 8; + bit_mask = 1 << (7 - bit_ix); + mask->bits[byte_ix] |= bit_mask; +} + +/* Set a bit mask. */ + +void +cgen_bitset_set (CGEN_BITSET * mask, unsigned bit_num) +{ + if (! mask) + return; + cgen_bitset_clear (mask); + cgen_bitset_add (mask, bit_num); +} + +/* Test for a bit in a bit mask. + Returns 1 if the bit is found */ + +int +cgen_bitset_contains (CGEN_BITSET * mask, unsigned bit_num) +{ + int byte_ix, bit_ix; + int bit_mask; + + if (! mask) + return 1; /* No bit restrictions. */ + + byte_ix = bit_num / 8; + bit_ix = 7 - (bit_num % 8); + bit_mask = 1 << bit_ix; + return (mask->bits[byte_ix] & bit_mask) >> bit_ix; +} + +/* Compare two bit masks for equality. + Returns 0 if they are equal. */ + +int +cgen_bitset_compare (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + if (mask1 == mask2) + return 0; + if (! mask1 || ! mask2) + return 1; + if (mask1->length != mask2->length) + return 1; + return memcmp (mask1->bits, mask2->bits, mask1->length); +} + +/* Test two bit masks for common bits. + Returns 1 if a common bit is found. */ + +int +cgen_bitset_intersect_p (CGEN_BITSET * mask1, CGEN_BITSET * mask2) +{ + unsigned i, limit; + + if (mask1 == mask2) + return 1; + if (! mask1 || ! mask2) + return 0; + limit = mask1->length < mask2->length ? mask1->length : mask2->length; + + for (i = 0; i < limit; ++i) + if ((mask1->bits[i] & mask2->bits[i])) + return 1; + + return 0; +} + +/* Make a copy of a bit mask. */ + +CGEN_BITSET * +cgen_bitset_copy (CGEN_BITSET * mask) +{ + CGEN_BITSET* newmask; + + if (! mask) + return NULL; + newmask = cgen_bitset_create ((mask->length * 8) - 1); + memcpy (newmask->bits, mask->bits, mask->length); + return newmask; +} + +/* Combine two bit masks. */ + +void +cgen_bitset_union (CGEN_BITSET * mask1, CGEN_BITSET * mask2, + CGEN_BITSET * result) +{ + unsigned i; + + if (! mask1 || ! mask2 || ! result + || mask1->length != mask2->length + || mask1->length != result->length) + return; + + for (i = 0; i < result->length; ++i) + result->bits[i] = mask1->bits[i] | mask2->bits[i]; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-dis.c b/external/gpl3/gdb/dist/opcodes/cgen-dis.c new file mode 100644 index 000000000000..0efdc105fe76 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-dis.c @@ -0,0 +1,240 @@ +/* CGEN generic disassembler support code. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" + +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_dis_hash_table (CGEN_CPU_DESC); +static int count_decodable_bits (const CGEN_INSN *); +static void add_insn_to_hash_chain (CGEN_INSN_LIST *, + const CGEN_INSN *, + CGEN_INSN_LIST **, + unsigned int); + +/* Return the number of decodable bits in this insn. */ +static int +count_decodable_bits (const CGEN_INSN *insn) +{ + unsigned mask = CGEN_INSN_BASE_MASK (insn); + int bits = 0; + int m; + for (m = 1; m != 0; m <<= 1) + { + if (mask & m) + ++bits; + } + return bits; +} + +/* Add an instruction to the hash chain. */ +static void +add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf, + const CGEN_INSN *insn, + CGEN_INSN_LIST **htable, + unsigned int hash) +{ + CGEN_INSN_LIST *current_buf; + CGEN_INSN_LIST *previous_buf; + int insn_decodable_bits; + + /* Add insns sorted by the number of decodable bits, in decreasing order. + This ensures that any insn which is a special case of another will be + checked first. */ + insn_decodable_bits = count_decodable_bits (insn); + previous_buf = NULL; + for (current_buf = htable[hash]; current_buf != NULL; + current_buf = current_buf->next) + { + int current_decodable_bits = count_decodable_bits (current_buf->insn); + if (insn_decodable_bits >= current_decodable_bits) + break; + previous_buf = current_buf; + } + + /* Now insert the new insn. */ + hentbuf->insn = insn; + hentbuf->next = current_buf; + if (previous_buf == NULL) + htable[hash] = hentbuf; + else + previous_buf->next = hentbuf; +} + +/* Subroutine of build_dis_hash_table to add INSNS to the hash table. + + COUNT is the number of elements in INSNS. + ENTSIZE is sizeof (CGEN_IBASE) for the target. + ??? No longer used but leave in for now. + HTABLE points to the hash table. + HENTBUF is a pointer to sufficiently large buffer of hash entries. + The result is a pointer to the next entry to use. + + The table is scanned backwards as additions are made to the front of the + list and we want earlier ones to be prefered. */ + +static CGEN_INSN_LIST * +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN * insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST ** htable, + CGEN_INSN_LIST * hentbuf) +{ + int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; + int i; + + for (i = count - 1; i >= 0; --i, ++hentbuf) + { + unsigned int hash; + char buf [4]; + unsigned long value; + const CGEN_INSN *insn = &insns[i]; + + if (! (* cd->dis_hash_p) (insn)) + continue; + + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + + value = CGEN_INSN_BASE_VALUE (insn); + bfd_put_bits ((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (insn), + big_p); + hash = (* cd->dis_hash) (buf, value); + add_insn_to_hash_chain (hentbuf, insn, htable, hash); + } + + return hentbuf; +} + +/* Subroutine of build_dis_hash_table to add INSNS to the hash table. + This function is identical to hash_insn_array except the insns are + in a list. */ + +static CGEN_INSN_LIST * +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) +{ + int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; + const CGEN_INSN_LIST *ilist; + + for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) + { + unsigned int hash; + char buf[4]; + unsigned long value; + + if (! (* cd->dis_hash_p) (ilist->insn)) + continue; + + /* We don't know whether the target uses the buffer or the base insn + to hash on, so set both up. */ + + value = CGEN_INSN_BASE_VALUE (ilist->insn); + bfd_put_bits((bfd_vma) value, + buf, + CGEN_INSN_MASK_BITSIZE (ilist->insn), + big_p); + hash = (* cd->dis_hash) (buf, value); + add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash); + } + + return hentbuf; +} + +/* Build the disassembler instruction hash table. */ + +static void +build_dis_hash_table (CGEN_CPU_DESC cd) +{ + int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); + CGEN_INSN_TABLE *insn_table = & cd->insn_table; + CGEN_INSN_TABLE *macro_insn_table = & cd->macro_insn_table; + unsigned int hash_size = cd->dis_hash_size; + CGEN_INSN_LIST *hash_entry_buf; + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; + + /* The space allocated for the hash table consists of two parts: + the hash table and the hash lists. */ + + dis_hash_table = (CGEN_INSN_LIST **) + xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); + memset (dis_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); + dis_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) + xmalloc (count * sizeof (CGEN_INSN_LIST)); + + /* Add compiled in insns. + Don't include the first one as it is a reserved entry. */ + /* ??? It was the end of all hash chains, and also the special + "invalid insn" marker. May be able to do it differently now. */ + + hash_entry_buf = hash_insn_array (cd, + insn_table->init_entries + 1, + insn_table->num_init_entries - 1, + insn_table->entry_size, + dis_hash_table, hash_entry_buf); + + /* Add compiled in macro-insns. */ + + hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, + macro_insn_table->num_init_entries, + macro_insn_table->entry_size, + dis_hash_table, hash_entry_buf); + + /* Add runtime added insns. + Later added insns will be prefered over earlier ones. */ + + hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, + dis_hash_table, hash_entry_buf); + + /* Add runtime added macro-insns. */ + + hash_insn_list (cd, macro_insn_table->new_entries, + dis_hash_table, hash_entry_buf); + + cd->dis_hash_table = dis_hash_table; + cd->dis_hash_table_entries = dis_hash_table_entries; +} + +/* Return the first entry in the hash list for INSN. */ + +CGEN_INSN_LIST * +cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) +{ + unsigned int hash; + + if (cd->dis_hash_table == NULL) + build_dis_hash_table (cd); + + hash = (* cd->dis_hash) (buf, value); + + return cd->dis_hash_table[hash]; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-dis.in b/external/gpl3/gdb/dist/opcodes/cgen-dis.in new file mode 100644 index 000000000000..0941853916fc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-dis.in @@ -0,0 +1,460 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! @arch@_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_@arch@ (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_@arch@ +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + @arch@_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen-ibld.in b/external/gpl3/gdb/dist/opcodes/cgen-ibld.in new file mode 100644 index 000000000000..a29f48816bd8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-ibld.in @@ -0,0 +1,538 @@ +/* Instruction building/extraction support for @arch@. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "@prefix@-desc.h" +#include "@prefix@-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ diff --git a/external/gpl3/gdb/dist/opcodes/cgen-opc.c b/external/gpl3/gdb/dist/opcodes/cgen-opc.c new file mode 100644 index 000000000000..263eb2c4d58f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen-opc.c @@ -0,0 +1,614 @@ +/* CGEN generic opcode support. + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005, 2007, 2009 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "alloca-conf.h" +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "bfd.h" +#include "symcat.h" +#include "opcode/cgen.h" + +static unsigned int hash_keyword_name + (const CGEN_KEYWORD *, const char *, int); +static unsigned int hash_keyword_value + (const CGEN_KEYWORD *, unsigned int); +static void build_keyword_hash_tables + (CGEN_KEYWORD *); + +/* Return number of hash table entries to use for N elements. */ +#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) + +/* Look up *NAMEP in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name) +{ + const CGEN_KEYWORD_ENTRY *ke; + const char *p,*n; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; + + /* We do case insensitive comparisons. + If that ever becomes a problem, add an attribute that denotes + "do case sensitive comparisons". */ + + while (ke != NULL) + { + n = name; + p = ke->name; + + while (*p + && (*p == *n + || (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n))))) + ++n, ++p; + + if (!*p && !*n) + return ke; + + ke = ke->next_name; + } + + if (kt->null_entry) + return kt->null_entry; + return NULL; +} + +/* Look up VALUE in the keyword table KT. + The result is the keyword entry or NULL if not found. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value) +{ + const CGEN_KEYWORD_ENTRY *ke; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + ke = kt->value_hash_table[hash_keyword_value (kt, value)]; + + while (ke != NULL) + { + if (value == ke->value) + return ke; + ke = ke->next_value; + } + + return NULL; +} + +/* Add an entry to a keyword table. */ + +void +cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke) +{ + unsigned int hash; + size_t i; + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + hash = hash_keyword_name (kt, ke->name, 0); + ke->next_name = kt->name_hash_table[hash]; + kt->name_hash_table[hash] = ke; + + hash = hash_keyword_value (kt, ke->value); + ke->next_value = kt->value_hash_table[hash]; + kt->value_hash_table[hash] = ke; + + if (ke->name[0] == 0) + kt->null_entry = ke; + + for (i = 1; i < strlen (ke->name); i++) + if (! ISALNUM (ke->name[i]) + && ! strchr (kt->nonalpha_chars, ke->name[i])) + { + size_t idx = strlen (kt->nonalpha_chars); + + /* If you hit this limit, please don't just + increase the size of the field, instead + look for a better algorithm. */ + if (idx >= sizeof (kt->nonalpha_chars) - 1) + abort (); + kt->nonalpha_chars[idx] = ke->name[i]; + kt->nonalpha_chars[idx+1] = 0; + } +} + +/* FIXME: Need function to return count of keywords. */ + +/* Initialize a keyword table search. + SPEC is a specification of what to search for. + A value of NULL means to find every keyword. + Currently NULL is the only acceptable value [further specification + deferred]. + The result is an opaque data item used to record the search status. + It is passed to each call to cgen_keyword_search_next. */ + +CGEN_KEYWORD_SEARCH +cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec) +{ + CGEN_KEYWORD_SEARCH search; + + /* FIXME: Need to specify format of params. */ + if (spec != NULL) + abort (); + + if (kt->name_hash_table == NULL) + build_keyword_hash_tables (kt); + + search.table = kt; + search.spec = spec; + search.current_hash = 0; + search.current_entry = NULL; + return search; +} + +/* Return the next keyword specified by SEARCH. + The result is the next entry or NULL if there are no more. */ + +const CGEN_KEYWORD_ENTRY * +cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search) +{ + /* Has search finished? */ + if (search->current_hash == search->table->hash_table_size) + return NULL; + + /* Search in progress? */ + if (search->current_entry != NULL + /* Anything left on this hash chain? */ + && search->current_entry->next_name != NULL) + { + search->current_entry = search->current_entry->next_name; + return search->current_entry; + } + + /* Move to next hash chain [unless we haven't started yet]. */ + if (search->current_entry != NULL) + ++search->current_hash; + + while (search->current_hash < search->table->hash_table_size) + { + search->current_entry = search->table->name_hash_table[search->current_hash]; + if (search->current_entry != NULL) + return search->current_entry; + ++search->current_hash; + } + + return NULL; +} + +/* Return first entry in hash chain for NAME. + If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ + +static unsigned int +hash_keyword_name (const CGEN_KEYWORD *kt, + const char *name, + int case_sensitive_p) +{ + unsigned int hash; + + if (case_sensitive_p) + for (hash = 0; *name; ++name) + hash = (hash * 97) + (unsigned char) *name; + else + for (hash = 0; *name; ++name) + hash = (hash * 97) + (unsigned char) TOLOWER (*name); + return hash % kt->hash_table_size; +} + +/* Return first entry in hash chain for VALUE. */ + +static unsigned int +hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value) +{ + return value % kt->hash_table_size; +} + +/* Build a keyword table's hash tables. + We probably needn't build the value hash table for the assembler when + we're using the disassembler, but we keep things simple. */ + +static void +build_keyword_hash_tables (CGEN_KEYWORD *kt) +{ + int i; + /* Use the number of compiled in entries as an estimate for the + typical sized table [not too many added at runtime]. */ + unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); + + kt->hash_table_size = size; + kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) + xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); + memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); + kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) + xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); + memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); + + /* The table is scanned backwards as we want keywords appearing earlier to + be prefered over later ones. */ + for (i = kt->num_init_entries - 1; i >= 0; --i) + cgen_keyword_add (kt, &kt->init_entries[i]); +} + +/* Hardware support. */ + +/* Lookup a hardware element by its name. + Returns NULL if NAME is not supported by the currently selected + mach/isa. */ + +const CGEN_HW_ENTRY * +cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name) +{ + unsigned int i; + const CGEN_HW_ENTRY **hw = cd->hw_table.entries; + + for (i = 0; i < cd->hw_table.num_entries; ++i) + if (hw[i] && strcmp (name, hw[i]->name) == 0) + return hw[i]; + + return NULL; +} + +/* Lookup a hardware element by its number. + Hardware elements are enumerated, however it may be possible to add some + at runtime, thus HWNUM is not an enum type but rather an int. + Returns NULL if HWNUM is not supported by the currently selected mach. */ + +const CGEN_HW_ENTRY * +cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum) +{ + unsigned int i; + const CGEN_HW_ENTRY **hw = cd->hw_table.entries; + + /* ??? This can be speeded up. */ + for (i = 0; i < cd->hw_table.num_entries; ++i) + if (hw[i] && hwnum == hw[i]->type) + return hw[i]; + + return NULL; +} + +/* Operand support. */ + +/* Lookup an operand by its name. + Returns NULL if NAME is not supported by the currently selected + mach/isa. */ + +const CGEN_OPERAND * +cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name) +{ + unsigned int i; + const CGEN_OPERAND **op = cd->operand_table.entries; + + for (i = 0; i < cd->operand_table.num_entries; ++i) + if (op[i] && strcmp (name, op[i]->name) == 0) + return op[i]; + + return NULL; +} + +/* Lookup an operand by its number. + Operands are enumerated, however it may be possible to add some + at runtime, thus OPNUM is not an enum type but rather an int. + Returns NULL if OPNUM is not supported by the currently selected + mach/isa. */ + +const CGEN_OPERAND * +cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum) +{ + return cd->operand_table.entries[opnum]; +} + +/* Instruction support. */ + +/* Return number of instructions. This includes any added at runtime. */ + +int +cgen_insn_count (CGEN_CPU_DESC cd) +{ + int count = cd->insn_table.num_init_entries; + CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; + + for ( ; rt_insns != NULL; rt_insns = rt_insns->next) + ++count; + + return count; +} + +/* Return number of macro-instructions. + This includes any added at runtime. */ + +int +cgen_macro_insn_count (CGEN_CPU_DESC cd) +{ + int count = cd->macro_insn_table.num_init_entries; + CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; + + for ( ; rt_insns != NULL; rt_insns = rt_insns->next) + ++count; + + return count; +} + +/* Cover function to read and properly byteswap an insn value. */ + +CGEN_INSN_INT +cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) +{ + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + CGEN_INSN_INT value = 0; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int bit_index; + bfd_vma this_value; + + bit_index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */ + this_value = bfd_get_bits (& buf[bit_index / 8], insn_chunk_bitsize, big_p); + value = (value << insn_chunk_bitsize) | this_value; + } + } + else + { + value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + } + + return value; +} + +/* Cover function to store an insn value properly byteswapped. */ + +void +cgen_put_insn_value (CGEN_CPU_DESC cd, + unsigned char *buf, + int length, + CGEN_INSN_INT value) +{ + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int bit_index; + + bit_index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */ + bfd_put_bits ((bfd_vma) value, & buf[bit_index / 8], insn_chunk_bitsize, big_p); + value >>= insn_chunk_bitsize; + } + } + else + { + bfd_put_bits ((bfd_vma) value, buf, length, big_p); + } +} + +/* Look up instruction INSN_*_VALUE and extract its fields. + INSN_INT_VALUE is used if CGEN_INT_INSN_P. + Otherwise INSN_BYTES_VALUE is used. + INSN, if non-null, is the insn table entry. + Otherwise INSN_*_VALUE is examined to compute it. + LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0. + 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. + If INSN != NULL, LENGTH must be valid. + ALIAS_P is non-zero if alias insns are to be included in the search. + + The result is a pointer to the insn table entry, or NULL if the instruction + wasn't recognized. */ + +/* ??? Will need to be revisited for VLIW architectures. */ + +const CGEN_INSN * +cgen_lookup_insn (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + CGEN_FIELDS *fields, + int alias_p) +{ + unsigned char *buf; + CGEN_INSN_INT base_insn; + CGEN_EXTRACT_INFO ex_info; + CGEN_EXTRACT_INFO *info; + + if (cd->int_insn_p) + { + info = NULL; + buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8); + cgen_put_insn_value (cd, buf, length, insn_int_value); + base_insn = insn_int_value; + } + else + { + info = &ex_info; + ex_info.dis_info = NULL; + ex_info.insn_bytes = insn_bytes_value; + ex_info.valid = -1; + buf = insn_bytes_value; + base_insn = cgen_get_insn_value (cd, buf, length); + } + + if (!insn) + { + const CGEN_INSN_LIST *insn_list; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = cgen_dis_lookup_insn (cd, (char *) buf, base_insn); + while (insn_list != NULL) + { + insn = insn_list->insn; + + if (alias_p + /* FIXME: Ensure ALIAS attribute always has same index. */ + || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) + { + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the + extract handler. */ + if ((base_insn & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* ??? 0 is passed for `pc' */ + int elength = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, info, base_insn, fields, (bfd_vma) 0); + if (elength > 0) + { + /* sanity check */ + if (length != 0 && length != elength) + abort (); + return insn; + } + } + } + + insn_list = insn_list->next; + } + } + else + { + /* Sanity check: can't pass an alias insn if ! alias_p. */ + if (! alias_p + && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) + abort (); + /* Sanity check: length must be correct. */ + if (length != CGEN_INSN_BITSIZE (insn)) + abort (); + + /* ??? 0 is passed for `pc' */ + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, info, base_insn, fields, (bfd_vma) 0); + /* Sanity check: must succeed. + Could relax this later if it ever proves useful. */ + if (length == 0) + abort (); + return insn; + } + + return NULL; +} + +/* Fill in the operand instances used by INSN whose operands are FIELDS. + INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled + in. */ + +void +cgen_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const CGEN_FIELDS *fields, + int *indices) +{ + const CGEN_OPINST *opinst; + int i; + + if (insn->opinst == NULL) + abort (); + for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst) + { + enum cgen_operand_type op_type = opinst->op_type; + if (op_type == CGEN_OPERAND_NIL) + indices[i] = opinst->index; + else + indices[i] = (*cd->get_int_operand) (cd, op_type, fields); + } +} + +/* Cover function to cgen_get_insn_operands when either INSN or FIELDS + isn't known. + The INSN, INSN_*_VALUE, and LENGTH arguments are passed to + cgen_lookup_insn unchanged. + INSN_INT_VALUE is used if CGEN_INT_INSN_P. + Otherwise INSN_BYTES_VALUE is used. + + The result is the insn table entry or NULL if the instruction wasn't + recognized. */ + +const CGEN_INSN * +cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + int *indices, + CGEN_FIELDS *fields) +{ + /* Pass non-zero for ALIAS_P only if INSN != NULL. + If INSN == NULL, we want a real insn. */ + insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, + length, fields, insn != NULL); + if (! insn) + return NULL; + + cgen_get_insn_operands (cd, insn, fields, indices); + return insn; +} + +/* Allow signed overflow of instruction fields. */ +void +cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd) +{ + cd->signed_overflow_ok_p = 1; +} + +/* Generate an error message if a signed field in an instruction overflows. */ +void +cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd) +{ + cd->signed_overflow_ok_p = 0; +} + +/* Will an error message be generated if a signed field in an instruction overflows ? */ +unsigned int +cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) +{ + return cd->signed_overflow_ok_p; +} diff --git a/external/gpl3/gdb/dist/opcodes/cgen.sh b/external/gpl3/gdb/dist/opcodes/cgen.sh new file mode 100644 index 000000000000..f65fcd489a52 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cgen.sh @@ -0,0 +1,168 @@ +#! /bin/sh +# CGEN generic assembler support code. +# +# Copyright 2000, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. +# +# This file is part of the GNU opcodes library. +# +# This library is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# It is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +# License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ +# +# Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch], +# arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. +# +# Usage: +# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \ +# arch-file opc-file options [extrafiles] +# +# ACTION is currently always "opcodes". It exists to be consistent with the +# simulator. +# ARCH is the name of the architecture. +# It is substituted into @arch@ and @ARCH@ in the generated files. +# PREFIX is both the generated file prefix and is substituted into +# @prefix@ in the generated files. +# ARCH-FILE is the name of the .cpu file (including path). +# OPC-FILE is the name of the .opc file (including path). +# OPTIONS is comma separated list of options (???). +# EXTRAFILES is a space separated list (1 arg still) of extra files to build: +# - opinst - arch-opinst.c is being made, causes semantic analysis +# +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter (or other implementation) with gdb/binutils. +# Maybe we never will. + +# We want to behave like make, any error forces us to stop. +set -e + +action=$1 +srcdir=$2 +cgen="$3" +cgendir=$4 +cgenflags=$5 +arch=$6 +prefix=$7 +archfile=$8 +opcfile=$9 +shift ; options=$9 + +# List of extra files to build. +# Values: opinst (only 1 extra file at present) +shift ; extrafiles=$9 + +rootdir=${srcdir}/.. + +# $arch is $6, as passed on the command line. +# $ARCH is the same argument but in all uppercase. +# Both forms are used in this script. + +lowercase='abcdefghijklmnopqrstuvwxyz' +uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` + +# Allow parallel makes to run multiple cgen's without colliding. +tmp=tmp-$$ + +extrafile_args="" +for ef in .. $extrafiles +do + case $ef in + ..) ;; + opinst) extrafile_args="-Q ${tmp}-opinst.c1 $extrafile_args" ;; + esac +done + +case $action in +opcodes) + # Remove residual working files. + rm -f ${tmp}-desc.h ${tmp}-desc.h1 + rm -f ${tmp}-desc.c ${tmp}-desc.c1 + rm -f ${tmp}-opc.h ${tmp}-opc.h1 + rm -f ${tmp}-opc.c ${tmp}-opc.c1 + rm -f ${tmp}-opinst.c ${tmp}-opinst.c1 + rm -f ${tmp}-ibld.h ${tmp}-ibld.h1 + rm -f ${tmp}-ibld.c ${tmp}-ibld.in1 + rm -f ${tmp}-asm.c ${tmp}-asm.in1 + rm -f ${tmp}-dis.c ${tmp}-dis.in1 + + # Run CGEN. + ${cgen} ${cgendir}/cgen-opc.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${options}" \ + -m all \ + -a ${archfile} \ + -OPC ${opcfile} \ + -H ${tmp}-desc.h1 \ + -C ${tmp}-desc.c1 \ + -O ${tmp}-opc.h1 \ + -P ${tmp}-opc.c1 \ + -L ${tmp}-ibld.in1 \ + -A ${tmp}-asm.in1 \ + -D ${tmp}-dis.in1 \ + ${extrafile_args} + + # Customise generated files for the particular architecture. + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < ${tmp}-desc.h1 > ${tmp}-desc.h + ${rootdir}/move-if-change ${tmp}-desc.h ${srcdir}/${prefix}-desc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < ${tmp}-desc.c1 > ${tmp}-desc.c + ${rootdir}/move-if-change ${tmp}-desc.c ${srcdir}/${prefix}-desc.c + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < ${tmp}-opc.h1 > ${tmp}-opc.h + ${rootdir}/move-if-change ${tmp}-opc.h ${srcdir}/${prefix}-opc.h + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < ${tmp}-opc.c1 > ${tmp}-opc.c + ${rootdir}/move-if-change ${tmp}-opc.c ${srcdir}/${prefix}-opc.c + + case $extrafiles in + *opinst*) + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" < ${tmp}-opinst.c1 >${tmp}-opinst.c + ${rootdir}/move-if-change ${tmp}-opinst.c ${srcdir}/${prefix}-opinst.c + ;; + esac + + cat ${srcdir}/cgen-ibld.in ${tmp}-ibld.in1 | \ + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > ${tmp}-ibld.c + ${rootdir}/move-if-change ${tmp}-ibld.c ${srcdir}/${prefix}-ibld.c + + sed -e "/ -- assembler routines/ r ${tmp}-asm.in1" ${srcdir}/cgen-asm.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > ${tmp}-asm.c + ${rootdir}/move-if-change ${tmp}-asm.c ${srcdir}/${prefix}-asm.c + + sed -e "/ -- disassembler routines/ r ${tmp}-dis.in1" ${srcdir}/cgen-dis.in \ + | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/" > ${tmp}-dis.c + ${rootdir}/move-if-change ${tmp}-dis.c ${srcdir}/${prefix}-dis.c + + # Remove temporary files. + rm -f ${tmp}-desc.h1 ${tmp}-desc.c1 + rm -f ${tmp}-opc.h1 ${tmp}-opc.c1 + rm -f ${tmp}-opinst.c1 + rm -f ${tmp}-ibld.h1 ${tmp}-ibld.in1 + rm -f ${tmp}-asm.in1 ${tmp}-dis.in1 + ;; + +*) + echo "$0: bad action: ${action}" >&2 + exit 1 + ;; + +esac + +exit 0 diff --git a/external/gpl3/gdb/dist/opcodes/config.in b/external/gpl3/gdb/dist/opcodes/config.in new file mode 100644 index 000000000000..fab2a5120f60 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/config.in @@ -0,0 +1,109 @@ +/* config.in. Generated from configure.in by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the declaration of `basename', and to 0 if you + don't. */ +#undef HAVE_DECL_BASENAME + +/* Define to 1 if you have the declaration of `stpcpy', and to 0 if you don't. + */ +#undef HAVE_DECL_STPCPY + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to the sub-directory in which libtool stores uninstalled libraries. + */ +#undef LT_OBJDIR + +/* Name of package */ +#undef PACKAGE + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Enable extensions on AIX 3, Interix. */ +#ifndef _ALL_SOURCE +# undef _ALL_SOURCE +#endif +/* Enable GNU extensions on systems that have them. */ +#ifndef _GNU_SOURCE +# undef _GNU_SOURCE +#endif +/* Enable threading extensions on Solaris. */ +#ifndef _POSIX_PTHREAD_SEMANTICS +# undef _POSIX_PTHREAD_SEMANTICS +#endif +/* Enable extensions on HP NonStop. */ +#ifndef _TANDEM_SOURCE +# undef _TANDEM_SOURCE +#endif +/* Enable general extensions on Solaris. */ +#ifndef __EXTENSIONS__ +# undef __EXTENSIONS__ +#endif + + +/* Version number of package */ +#undef VERSION + +/* Define to 1 if on MINIX. */ +#undef _MINIX + +/* Define to 2 if the system does not provide POSIX.1 features except with + this defined. */ +#undef _POSIX_1_SOURCE + +/* Define to 1 if you need to in order for `stat' and other things to work. */ +#undef _POSIX_SOURCE diff --git a/external/gpl3/gdb/dist/opcodes/configure b/external/gpl3/gdb/dist/opcodes/configure new file mode 100755 index 000000000000..83ac9aecf2dc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/configure @@ -0,0 +1,14985 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. 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"$ac_site_file" + fi +done + +if test -r "$cache_file"; then + # Some versions of bash will fail to source /dev/null (special + # files actually), so we avoid doing that. + if test -f "$cache_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +$as_echo "$as_me: loading cache $cache_file" >&6;} + case $cache_file in + [\\/]* | ?:[\\/]* ) . "$cache_file";; + *) . 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" >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing strerror" >&5 +$as_echo_n "checking for library containing strerror... " >&6; } +if test "${ac_cv_search_strerror+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char strerror (); +int +main () +{ +return strerror (); + ; + return 0; +} +_ACEOF +for ac_lib in '' cposix; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_strerror=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_strerror+set}" = set; then : + break +fi +done +if test "${ac_cv_search_strerror+set}" = set; then : + +else + ac_cv_search_strerror=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_strerror" >&5 +$as_echo "$ac_cv_search_strerror" >&6; } +ac_res=$ac_cv_search_strerror +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + + +# We currently only use the version number for the name of any shared +# library. For user convenience, we always use the same version +# number that BFD is using. +BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${srcdir}/../bfd/configure.in` + +am__api_version='1.11' + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5 +$as_echo_n "checking whether build environment is sane... " >&6; } +# Just in case +sleep 1 +echo timestamp > conftest.file +# Reject unsafe characters in $srcdir or the absolute working directory +# name. Accept space and tab only in the latter. +am_lf=' +' +case `pwd` in + *[\\\"\#\$\&\'\`$am_lf]*) + as_fn_error "unsafe absolute working directory name" "$LINENO" 5;; +esac +case $srcdir in + *[\\\"\#\$\&\'\`$am_lf\ \ ]*) + as_fn_error "unsafe srcdir value: \`$srcdir'" "$LINENO" 5;; +esac + +# Do `set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` + if test "$*" = "X"; then + # -L didn't work. + set X `ls -t "$srcdir/configure" conftest.file` + fi + rm -f conftest.file + if test "$*" != "X $srcdir/configure conftest.file" \ + && test "$*" != "X conftest.file $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + as_fn_error "ls -t appears to fail. Make sure there is not a broken +alias in your environment" "$LINENO" 5 + fi + + test "$2" = conftest.file + ) +then + # Ok. + : +else + as_fn_error "newly created file is older than distributed files! +Check your system clock" "$LINENO" 5 +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +# expand $ac_aux_dir to an absolute path +am_aux_dir=`cd $ac_aux_dir && pwd` + +if test x"${MISSING+set}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; + *) + MISSING="\${SHELL} $am_aux_dir/missing" ;; + esac +fi +# Use eval to expand $SHELL +if eval "$MISSING --run true"; then + am_missing_run="$MISSING --run " +else + am_missing_run= + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`missing' script is too old or missing" >&5 +$as_echo "$as_me: WARNING: \`missing' script is too old or missing" >&2;} +fi + +if test x"${install_sh}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; + *) + install_sh="\${SHELL} $am_aux_dir/install-sh" + esac +fi + +# Installed binaries are usually stripped using `strip' when the user +# run `make install-strip'. However `strip' might not be the right +# tool to use in cross-compilation environments, therefore Automake +# will honor the `STRIP' environment variable to overrule this program. +if test "$cross_compiling" != no; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_STRIP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +STRIP=$ac_cv_prog_STRIP +if test -n "$STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +$as_echo "$STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_STRIP"; then + ac_ct_STRIP=$STRIP + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_STRIP"; then + ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_STRIP="strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP +if test -n "$ac_ct_STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +$as_echo "$ac_ct_STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_STRIP" = x; then + STRIP=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + STRIP=$ac_ct_STRIP + fi +else + STRIP="$ac_cv_prog_STRIP" +fi + +fi +INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5 +$as_echo_n "checking for a thread-safe mkdir -p... " >&6; } +if test -z "$MKDIR_P"; then + if test "${ac_cv_path_mkdir+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/opt/sfw/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in mkdir gmkdir; do + for ac_exec_ext in '' $ac_executable_extensions; do + { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; } || continue + case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #( + 'mkdir (GNU coreutils) '* | \ + 'mkdir (coreutils) '* | \ + 'mkdir (fileutils) '4.1*) + ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext + break 3;; + esac + done + done + done +IFS=$as_save_IFS + +fi + + if test "${ac_cv_path_mkdir+set}" = set; then + MKDIR_P="$ac_cv_path_mkdir -p" + else + # As a last resort, use the slow shell script. Don't cache a + # value for MKDIR_P within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + test -d ./--version && rmdir ./--version + MKDIR_P="$ac_install_sh -d" + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5 +$as_echo "$MKDIR_P" >&6; } + +mkdir_p="$MKDIR_P" +case $mkdir_p in + [\\/$]* | ?:[\\/]*) ;; + */*) mkdir_p="\$(top_builddir)/$mkdir_p" ;; +esac + +for ac_prog in gawk mawk nawk awk +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AWK+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AWK"; then + ac_cv_prog_AWK="$AWK" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AWK="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AWK=$ac_cv_prog_AWK +if test -n "$AWK"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 +$as_echo "$AWK" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$AWK" && break +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 +$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... 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The system "awk" is bad on +# some platforms. +# Always define AMTAR for backward compatibility. + +AMTAR=${AMTAR-"${am_missing_run}tar"} + +am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -' + + + + +depcc="$CC" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if test "${am_cv_CC_dependencies_compiler_type+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named `D' -- because `-MD' means `put the output + # in D'. + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CC_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with + # Solaris 8's {/usr,}/bin/sh. + touch sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with `-c' and `-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle `-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # after this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvisualcpp | msvcmsys) + # This compiler won't grok `-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CC_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CC_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } +CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then + am__fastdepCC_TRUE= + am__fastdepCC_FALSE='#' +else + am__fastdepCC_TRUE='#' + am__fastdepCC_FALSE= +fi + + + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + + + ac_fn_c_check_header_mongrel "$LINENO" "minix/config.h" "ac_cv_header_minix_config_h" "$ac_includes_default" +if test "x$ac_cv_header_minix_config_h" = x""yes; then : + MINIX=yes +else + MINIX= +fi + + + if test "$MINIX" = yes; then + +$as_echo "#define _POSIX_SOURCE 1" >>confdefs.h + + +$as_echo "#define _POSIX_1_SOURCE 2" >>confdefs.h + + +$as_echo "#define _MINIX 1" >>confdefs.h + + fi + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether it is safe to define __EXTENSIONS__" >&5 +$as_echo_n "checking whether it is safe to define __EXTENSIONS__... " >&6; } +if test "${ac_cv_safe_to_define___extensions__+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +# define __EXTENSIONS__ 1 + $ac_includes_default +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_safe_to_define___extensions__=yes +else + ac_cv_safe_to_define___extensions__=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_safe_to_define___extensions__" >&5 +$as_echo "$ac_cv_safe_to_define___extensions__" >&6; } + test $ac_cv_safe_to_define___extensions__ = yes && + $as_echo "#define __EXTENSIONS__ 1" >>confdefs.h + + $as_echo "#define _ALL_SOURCE 1" >>confdefs.h + + $as_echo "#define _GNU_SOURCE 1" >>confdefs.h + + $as_echo "#define _POSIX_PTHREAD_SEMANTICS 1" >>confdefs.h + + $as_echo "#define _TANDEM_SOURCE 1" >>confdefs.h + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Check whether --enable-shared was given. +if test "${enable_shared+set}" = set; then : + enableval=$enable_shared; p=${PACKAGE-default} + case $enableval in + yes) enable_shared=yes ;; + no) enable_shared=no ;; + *) + enable_shared=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_shared=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_shared=no +fi + + + + + + + + + + +case `pwd` in + *\ * | *\ *) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&5 +$as_echo "$as_me: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&2;} ;; +esac + + + +macro_version='2.2.7a' +macro_revision='1.3134' + + + + + + + + + + + + + +ltmain="$ac_aux_dir/ltmain.sh" + +# Backslashify metacharacters that are still active within +# double-quoted strings. +sed_quote_subst='s/\(["`$\\]\)/\\\1/g' + +# Same as above, but do not quote variable references. +double_quote_subst='s/\(["`\\]\)/\\\1/g' + +# Sed substitution to delay expansion of an escaped shell variable in a +# double_quote_subst'ed string. +delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' + +# Sed substitution to delay expansion of an escaped single quote. +delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' + +# Sed substitution to avoid accidental globbing in evaled expressions +no_glob_subst='s/\*/\\\*/g' + +ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO +ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to print strings" >&5 +$as_echo_n "checking how to print strings... " >&6; } +# Test print first, because it will be a builtin if present. +if test "X`print -r -- -n 2>/dev/null`" = X-n && \ + test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then + ECHO='print -r --' +elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then + ECHO='printf %s\n' +else + # Use this function as a fallback that always works. + func_fallback_echo () + { + eval 'cat <<_LTECHO_EOF +$1 +_LTECHO_EOF' + } + ECHO='func_fallback_echo' +fi + +# func_echo_all arg... +# Invoke $ECHO with all args, space-separated. +func_echo_all () +{ + $ECHO "" +} + +case "$ECHO" in + printf*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: printf" >&5 +$as_echo "printf" >&6; } ;; + print*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: print -r" >&5 +$as_echo "print -r" >&6; } ;; + *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: cat" >&5 +$as_echo "cat" >&6; } ;; +esac + + + + + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5 +$as_echo_n "checking for a sed that does not truncate output... " >&6; } +if test "${ac_cv_path_SED+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/ + for ac_i in 1 2 3 4 5 6 7; do + ac_script="$ac_script$as_nl$ac_script" + done + echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed + { ac_script=; unset ac_script;} + if test -z "$SED"; then + ac_path_SED_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in sed gsed; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_SED="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_SED" && $as_test_x "$ac_path_SED"; } || continue +# Check for GNU ac_path_SED and select it if it is found. + # Check for GNU $ac_path_SED +case `"$ac_path_SED" --version 2>&1` in +*GNU*) + ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo '' >> "conftest.nl" + "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_SED_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_SED="$ac_path_SED" + ac_path_SED_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_SED_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_SED"; then + as_fn_error "no acceptable sed could be found in \$PATH" "$LINENO" 5 + fi +else + ac_cv_path_SED=$SED +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_SED" >&5 +$as_echo "$ac_cv_path_SED" >&6; } + SED="$ac_cv_path_SED" + rm -f conftest.sed + +test -z "$SED" && SED=sed +Xsed="$SED -e 1s/^X//" + + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for fgrep" >&5 +$as_echo_n "checking for fgrep... " >&6; } +if test "${ac_cv_path_FGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo 'ab*c' | $GREP -F 'ab*c' >/dev/null 2>&1 + then ac_cv_path_FGREP="$GREP -F" + else + if test -z "$FGREP"; then + ac_path_FGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in fgrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_FGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_FGREP" && $as_test_x "$ac_path_FGREP"; } || continue +# Check for GNU ac_path_FGREP and select it if it is found. + # Check for GNU $ac_path_FGREP +case `"$ac_path_FGREP" --version 2>&1` in +*GNU*) + ac_cv_path_FGREP="$ac_path_FGREP" ac_path_FGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'FGREP' >> "conftest.nl" + "$ac_path_FGREP" FGREP < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_FGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_FGREP="$ac_path_FGREP" + ac_path_FGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_FGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_FGREP"; then + as_fn_error "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_FGREP=$FGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_FGREP" >&5 +$as_echo "$ac_cv_path_FGREP" >&6; } + FGREP="$ac_cv_path_FGREP" + + +test -z "$GREP" && GREP=grep + + + + + + + + + + + + + + + + + + + +# Check whether --with-gnu-ld was given. +if test "${with_gnu_ld+set}" = set; then : + withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes +else + with_gnu_ld=no +fi + +ac_prog=ld +if test "$GCC" = yes; then + # Check if gcc -print-prog-name=ld gives a path. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by $CC" >&5 +$as_echo_n "checking for ld used by $CC... " >&6; } + case $host in + *-*-mingw*) + # gcc leaves a trailing carriage return which upsets mingw + ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; + *) + ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; + esac + case $ac_prog in + # Accept absolute paths. + [\\/]* | ?:[\\/]*) + re_direlt='/[^/][^/]*/\.\./' + # Canonicalize the pathname of ld + ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` + while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do + ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` + done + test -z "$LD" && LD="$ac_prog" + ;; + "") + # If it fails, then pretend we aren't using GCC. + ac_prog=ld + ;; + *) + # If it is relative, then search for the first ld in PATH. + with_gnu_ld=unknown + ;; + esac +elif test "$with_gnu_ld" = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5 +$as_echo_n "checking for GNU ld... " >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 +$as_echo_n "checking for non-GNU ld... " >&6; } +fi +if test "${lt_cv_path_LD+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$LD"; then + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then + lt_cv_path_LD="$ac_dir/$ac_prog" + # Check to see if the program is GNU ld. I'd rather use --version, + # but apparently some variants of GNU ld only accept -v. + # Break only if it was the GNU/non-GNU ld that we prefer. + case `"$lt_cv_path_LD" -v 2>&1 &5 +$as_echo "$LD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi +test -z "$LD" && as_fn_error "no acceptable ld found in \$PATH" "$LINENO" 5 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 +$as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } +if test "${lt_cv_prog_gnu_ld+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # I'd rather use --version here, but apparently some GNU lds only accept -v. +case `$LD -v 2>&1 &5 +$as_echo "$lt_cv_prog_gnu_ld" >&6; } +with_gnu_ld=$lt_cv_prog_gnu_ld + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for BSD- or MS-compatible name lister (nm)" >&5 +$as_echo_n "checking for BSD- or MS-compatible name lister (nm)... " >&6; } +if test "${lt_cv_path_NM+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$NM"; then + # Let the user override the test. + lt_cv_path_NM="$NM" +else + lt_nm_to_check="${ac_tool_prefix}nm" + if test -n "$ac_tool_prefix" && test "$build" = "$host"; then + lt_nm_to_check="$lt_nm_to_check nm" + fi + for lt_tmp_nm in $lt_nm_to_check; do + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + tmp_nm="$ac_dir/$lt_tmp_nm" + if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then + # Check to see if the nm accepts a BSD-compat flag. + # Adding the `sed 1q' prevents false positives on HP-UX, which says: + # nm: unknown option "B" ignored + # Tru64's nm complains that /dev/null is an invalid object file + case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in + */dev/null* | *'Invalid file or object type'*) + lt_cv_path_NM="$tmp_nm -B" + break + ;; + *) + case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in + */dev/null*) + lt_cv_path_NM="$tmp_nm -p" + break + ;; + *) + lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but + continue # so that we can try to find one that supports BSD flags + ;; + esac + ;; + esac + fi + done + IFS="$lt_save_ifs" + done + : ${lt_cv_path_NM=no} +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_NM" >&5 +$as_echo "$lt_cv_path_NM" >&6; } +if test "$lt_cv_path_NM" != "no"; then + NM="$lt_cv_path_NM" +else + # Didn't find any BSD compatible name lister, look for dumpbin. + if test -n "$DUMPBIN"; then : + # Let the user override the test. + else + if test -n "$ac_tool_prefix"; then + for ac_prog in dumpbin "link -dump" + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_DUMPBIN+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$DUMPBIN"; then + ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +DUMPBIN=$ac_cv_prog_DUMPBIN +if test -n "$DUMPBIN"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DUMPBIN" >&5 +$as_echo "$DUMPBIN" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$DUMPBIN" && break + done +fi +if test -z "$DUMPBIN"; then + ac_ct_DUMPBIN=$DUMPBIN + for ac_prog in dumpbin "link -dump" +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_DUMPBIN+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_DUMPBIN"; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN +if test -n "$ac_ct_DUMPBIN"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DUMPBIN" >&5 +$as_echo "$ac_ct_DUMPBIN" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_DUMPBIN" && break +done + + if test "x$ac_ct_DUMPBIN" = x; then + DUMPBIN=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + DUMPBIN=$ac_ct_DUMPBIN + fi +fi + + case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in + *COFF*) + DUMPBIN="$DUMPBIN -symbols" + ;; + *) + DUMPBIN=: + ;; + esac + fi + + if test "$DUMPBIN" != ":"; then + NM="$DUMPBIN" + fi +fi +test -z "$NM" && NM=nm + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the name lister ($NM) interface" >&5 +$as_echo_n "checking the name lister ($NM) interface... " >&6; } +if test "${lt_cv_nm_interface+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_nm_interface="BSD nm" + echo "int some_variable = 0;" > conftest.$ac_ext + (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&5) + (eval "$ac_compile" 2>conftest.err) + cat conftest.err >&5 + (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&5) + (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) + cat conftest.err >&5 + (eval echo "\"\$as_me:$LINENO: output\"" >&5) + cat conftest.out >&5 + if $GREP 'External.*some_variable' conftest.out > /dev/null; then + lt_cv_nm_interface="MS dumpbin" + fi + rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_nm_interface" >&5 +$as_echo "$lt_cv_nm_interface" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5 +$as_echo_n "checking whether ln -s works... " >&6; } +LN_S=$as_ln_s +if test "$LN_S" = "ln -s"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5 +$as_echo "no, using $LN_S" >&6; } +fi + +# find the maximum length of command line arguments +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking the maximum length of command line arguments" >&5 +$as_echo_n "checking the maximum length of command line arguments... " >&6; } +if test "${lt_cv_sys_max_cmd_len+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + i=0 + teststring="ABCD" + + case $build_os in + msdosdjgpp*) + # On DJGPP, this test can blow up pretty badly due to problems in libc + # (any single argument exceeding 2000 bytes causes a buffer overrun + # during glob expansion). Even if it were fixed, the result of this + # check would be larger than it should be. + lt_cv_sys_max_cmd_len=12288; # 12K is about right + ;; + + gnu*) + # Under GNU Hurd, this test is not required because there is + # no limit to the length of command line arguments. + # Libtool will interpret -1 as no limit whatsoever + lt_cv_sys_max_cmd_len=-1; + ;; + + cygwin* | mingw* | cegcc*) + # On Win9x/ME, this test blows up -- it succeeds, but takes + # about 5 minutes as the teststring grows exponentially. + # Worse, since 9x/ME are not pre-emptively multitasking, + # you end up with a "frozen" computer, even though with patience + # the test eventually succeeds (with a max line length of 256k). + # Instead, let's just punt: use the minimum linelength reported by + # all of the supported platforms: 8192 (on NT/2K/XP). + lt_cv_sys_max_cmd_len=8192; + ;; + + mint*) + # On MiNT this can take a long time and run out of memory. + lt_cv_sys_max_cmd_len=8192; + ;; + + amigaos*) + # On AmigaOS with pdksh, this test takes hours, literally. + # So we just punt and use a minimum line length of 8192. + lt_cv_sys_max_cmd_len=8192; + ;; + + netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) + # This has been around since 386BSD, at least. Likely further. + if test -x /sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` + elif test -x /usr/sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` + else + lt_cv_sys_max_cmd_len=65536 # usable default for all BSDs + fi + # And add a safety zone + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + ;; + + interix*) + # We know the value 262144 and hardcode it with a safety zone (like BSD) + lt_cv_sys_max_cmd_len=196608 + ;; + + osf*) + # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure + # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not + # nice to cause kernel panics so lets avoid the loop below. + # First set a reasonable default. + lt_cv_sys_max_cmd_len=16384 + # + if test -x /sbin/sysconfig; then + case `/sbin/sysconfig -q proc exec_disable_arg_limit` in + *1*) lt_cv_sys_max_cmd_len=-1 ;; + esac + fi + ;; + sco3.2v5*) + lt_cv_sys_max_cmd_len=102400 + ;; + sysv5* | sco5v6* | sysv4.2uw2*) + kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null` + if test -n "$kargmax"; then + lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[ ]//'` + else + lt_cv_sys_max_cmd_len=32768 + fi + ;; + *) + lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null` + if test -n "$lt_cv_sys_max_cmd_len"; then + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + else + # Make teststring a little bigger before we do anything with it. + # a 1K string should be a reasonable start. + for i in 1 2 3 4 5 6 7 8 ; do + teststring=$teststring$teststring + done + SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}} + # If test is not a shell built-in, we'll probably end up computing a + # maximum length that is only half of the actual maximum length, but + # we can't tell. + while { test "X"`func_fallback_echo "$teststring$teststring" 2>/dev/null` \ + = "X$teststring$teststring"; } >/dev/null 2>&1 && + test $i != 17 # 1/2 MB should be enough + do + i=`expr $i + 1` + teststring=$teststring$teststring + done + # Only check the string length outside the loop. + lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1` + teststring= + # Add a significant safety factor because C++ compilers can tack on + # massive amounts of additional arguments before passing them to the + # linker. It appears as though 1/2 is a usable value. + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2` + fi + ;; + esac + +fi + +if test -n $lt_cv_sys_max_cmd_len ; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sys_max_cmd_len" >&5 +$as_echo "$lt_cv_sys_max_cmd_len" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none" >&5 +$as_echo "none" >&6; } +fi +max_cmd_len=$lt_cv_sys_max_cmd_len + + + + + + +: ${CP="cp -f"} +: ${MV="mv -f"} +: ${RM="rm -f"} + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands some XSI constructs" >&5 +$as_echo_n "checking whether the shell understands some XSI constructs... " >&6; } +# Try some XSI features +xsi_shell=no +( _lt_dummy="a/b/c" + test "${_lt_dummy##*/},${_lt_dummy%/*},"${_lt_dummy%"$_lt_dummy"}, \ + = c,a/b,, \ + && eval 'test $(( 1 + 1 )) -eq 2 \ + && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \ + && xsi_shell=yes +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $xsi_shell" >&5 +$as_echo "$xsi_shell" >&6; } + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands \"+=\"" >&5 +$as_echo_n "checking whether the shell understands \"+=\"... " >&6; } +lt_shell_append=no +( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \ + >/dev/null 2>&1 \ + && lt_shell_append=yes +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_shell_append" >&5 +$as_echo "$lt_shell_append" >&6; } + + +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then + lt_unset=unset +else + lt_unset=false +fi + + + + + +# test EBCDIC or ASCII +case `echo X|tr X '\101'` in + A) # ASCII based system + # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr + lt_SP2NL='tr \040 \012' + lt_NL2SP='tr \015\012 \040\040' + ;; + *) # EBCDIC based system + lt_SP2NL='tr \100 \n' + lt_NL2SP='tr \r\n \100\100' + ;; +esac + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $LD option to reload object files" >&5 +$as_echo_n "checking for $LD option to reload object files... " >&6; } +if test "${lt_cv_ld_reload_flag+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_reload_flag='-r' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_reload_flag" >&5 +$as_echo "$lt_cv_ld_reload_flag" >&6; } +reload_flag=$lt_cv_ld_reload_flag +case $reload_flag in +"" | " "*) ;; +*) reload_flag=" $reload_flag" ;; +esac +reload_cmds='$LD$reload_flag -o $output$reload_objs' +case $host_os in + darwin*) + if test "$GCC" = yes; then + reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs' + else + reload_cmds='$LD$reload_flag -o $output$reload_objs' + fi + ;; +esac + + + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}objdump", so it can be a program name with args. +set dummy ${ac_tool_prefix}objdump; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_OBJDUMP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OBJDUMP"; then + ac_cv_prog_OBJDUMP="$OBJDUMP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_OBJDUMP="${ac_tool_prefix}objdump" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OBJDUMP=$ac_cv_prog_OBJDUMP +if test -n "$OBJDUMP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OBJDUMP" >&5 +$as_echo "$OBJDUMP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OBJDUMP"; then + ac_ct_OBJDUMP=$OBJDUMP + # Extract the first word of "objdump", so it can be a program name with args. +set dummy objdump; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_OBJDUMP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OBJDUMP"; then + ac_cv_prog_ac_ct_OBJDUMP="$ac_ct_OBJDUMP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_OBJDUMP="objdump" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OBJDUMP=$ac_cv_prog_ac_ct_OBJDUMP +if test -n "$ac_ct_OBJDUMP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OBJDUMP" >&5 +$as_echo "$ac_ct_OBJDUMP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OBJDUMP" = x; then + OBJDUMP="false" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OBJDUMP=$ac_ct_OBJDUMP + fi +else + OBJDUMP="$ac_cv_prog_OBJDUMP" +fi + +test -z "$OBJDUMP" && OBJDUMP=objdump + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to recognize dependent libraries" >&5 +$as_echo_n "checking how to recognize dependent libraries... " >&6; } +if test "${lt_cv_deplibs_check_method+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_file_magic_cmd='$MAGIC_CMD' +lt_cv_file_magic_test_file= +lt_cv_deplibs_check_method='unknown' +# Need to set the preceding variable on all platforms that support +# interlibrary dependencies. +# 'none' -- dependencies not supported. +# `unknown' -- same as none, but documents that we really don't know. +# 'pass_all' -- all dependencies passed with no checks. +# 'test_compile' -- check by making test program. +# 'file_magic [[regex]]' -- check by looking for files in library path +# which responds to the $file_magic_cmd with a given extended regex. +# If you have `file' or equivalent on your system and you're not sure +# whether `pass_all' will *always* work, you probably want this one. + +case $host_os in +aix[4-9]*) + lt_cv_deplibs_check_method=pass_all + ;; + +beos*) + lt_cv_deplibs_check_method=pass_all + ;; + +bsdi[45]*) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' + lt_cv_file_magic_cmd='/usr/bin/file -L' + lt_cv_file_magic_test_file=/shlib/libc.so + ;; + +cygwin*) + # func_win32_libid is a shell function defined in ltmain.sh + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + ;; + +mingw* | pw32*) + # Base MSYS/MinGW do not provide the 'file' command needed by + # func_win32_libid shell function, so use a weaker test based on 'objdump', + # unless we find 'file', for example because we are cross-compiling. + # func_win32_libid assumes BSD nm, so disallow it if using MS dumpbin. + if ( test "$lt_cv_nm_interface" = "BSD nm" && file / ) >/dev/null 2>&1; then + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + else + lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?' + lt_cv_file_magic_cmd='$OBJDUMP -f' + fi + ;; + +cegcc*) + # use the weaker test based on 'objdump'. See mingw*. + lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?' + lt_cv_file_magic_cmd='$OBJDUMP -f' + ;; + +darwin* | rhapsody*) + lt_cv_deplibs_check_method=pass_all + ;; + +freebsd* | dragonfly*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then + case $host_cpu in + i*86 ) + # Not sure whether the presence of OpenBSD here was a mistake. + # Let's accept both of them until this is cleared up. + lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` + ;; + esac + else + lt_cv_deplibs_check_method=pass_all + fi + ;; + +gnu*) + lt_cv_deplibs_check_method=pass_all + ;; + +haiku*) + lt_cv_deplibs_check_method=pass_all + ;; + +hpux10.20* | hpux11*) + lt_cv_file_magic_cmd=/usr/bin/file + case $host_cpu in + ia64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' + lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so + ;; + hppa*64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' + lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl + ;; + *) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9]\.[0-9]) shared library' + lt_cv_file_magic_test_file=/usr/lib/libc.sl + ;; + esac + ;; + +interix[3-9]*) + # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$' + ;; + +irix5* | irix6* | nonstopux*) + case $LD in + *-32|*"-32 ") libmagic=32-bit;; + *-n32|*"-n32 ") libmagic=N32;; + *-64|*"-64 ") libmagic=64-bit;; + *) libmagic=never-match;; + esac + lt_cv_deplibs_check_method=pass_all + ;; + +# This must be Linux ELF. +linux* | k*bsd*-gnu | kopensolaris*-gnu) + lt_cv_deplibs_check_method=pass_all + ;; + +netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$' + fi + ;; + +newos6*) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/libnls.so + ;; + +*nto* | *qnx*) + lt_cv_deplibs_check_method=pass_all + ;; + +openbsd*) + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' + fi + ;; + +osf3* | osf4* | osf5*) + lt_cv_deplibs_check_method=pass_all + ;; + +rdos*) + lt_cv_deplibs_check_method=pass_all + ;; + +solaris*) + lt_cv_deplibs_check_method=pass_all + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + lt_cv_deplibs_check_method=pass_all + ;; + +sysv4 | sysv4.3*) + case $host_vendor in + motorola) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` + ;; + ncr) + lt_cv_deplibs_check_method=pass_all + ;; + sequent) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' + ;; + sni) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib" + lt_cv_file_magic_test_file=/lib/libc.so + ;; + siemens) + lt_cv_deplibs_check_method=pass_all + ;; + pc) + lt_cv_deplibs_check_method=pass_all + ;; + esac + ;; + +tpf*) + lt_cv_deplibs_check_method=pass_all + ;; +esac + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_deplibs_check_method" >&5 +$as_echo "$lt_cv_deplibs_check_method" >&6; } +file_magic_cmd=$lt_cv_file_magic_cmd +deplibs_check_method=$lt_cv_deplibs_check_method +test -z "$deplibs_check_method" && deplibs_check_method=unknown + + + + + + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="false" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + +test -z "$AR" && AR=ar +test -z "$AR_FLAGS" && AR_FLAGS=cru + + + + + + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_STRIP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +STRIP=$ac_cv_prog_STRIP +if test -n "$STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +$as_echo "$STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_STRIP"; then + ac_ct_STRIP=$STRIP + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_STRIP"; then + ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_STRIP="strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP +if test -n "$ac_ct_STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +$as_echo "$ac_ct_STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_STRIP" = x; then + STRIP=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + STRIP=$ac_ct_STRIP + fi +else + STRIP="$ac_cv_prog_STRIP" +fi + +test -z "$STRIP" && STRIP=: + + + + + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + +test -z "$RANLIB" && RANLIB=: + + + + + + +# Determine commands to create old-style static archives. +old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs' +old_postinstall_cmds='chmod 644 $oldlib' +old_postuninstall_cmds= + +if test -n "$RANLIB"; then + case $host_os in + openbsd*) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib" + ;; + *) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib" + ;; + esac + old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib" +fi + +case $host_os in + darwin*) + lock_old_archive_extraction=yes ;; + *) + lock_old_archive_extraction=no ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + + +# Check for command to grab the raw symbol name followed by C symbol from nm. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking command to parse $NM output from $compiler object" >&5 +$as_echo_n "checking command to parse $NM output from $compiler object... " >&6; } +if test "${lt_cv_sys_global_symbol_pipe+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + +# These are sane defaults that work on at least a few old systems. +# [They come from Ultrix. What could be older than Ultrix?!! ;)] + +# Character class describing NM global symbol codes. +symcode='[BCDEGRST]' + +# Regexp to match symbols that can be accessed directly from C. +sympat='\([_A-Za-z][_A-Za-z0-9]*\)' + +# Define system-specific variables. +case $host_os in +aix*) + symcode='[BCDT]' + ;; +cygwin* | mingw* | pw32* | cegcc*) + symcode='[ABCDGISTW]' + ;; +hpux*) + if test "$host_cpu" = ia64; then + symcode='[ABCDEGRST]' + fi + ;; +irix* | nonstopux*) + symcode='[BCDEGRST]' + ;; +osf*) + symcode='[BCDEGQRST]' + ;; +solaris*) + symcode='[BDRT]' + ;; +sco3.2v5*) + symcode='[DT]' + ;; +sysv4.2uw2*) + symcode='[DT]' + ;; +sysv5* | sco5v6* | unixware* | OpenUNIX*) + symcode='[ABDT]' + ;; +sysv4) + symcode='[DFNSTU]' + ;; +esac + +# If we're using GNU nm, then use its standard symbol codes. +case `$NM -V 2>&1` in +*GNU* | *'with BFD'*) + symcode='[ABCDGIRSTW]' ;; +esac + +# Transform an extracted symbol line into a proper C declaration. +# Some systems (esp. on ia64) link data and code symbols differently, +# so use this general approach. +lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" + +# Transform an extracted symbol line into symbol name and symbol address +lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (void *) \&\2},/p'" +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \(lib[^ ]*\)$/ {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"lib\2\", (void *) \&\2},/p'" + +# Handle CRLF in mingw tool chain +opt_cr= +case $build_os in +mingw*) + opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp + ;; +esac + +# Try without a prefix underscore, then with it. +for ac_symprfx in "" "_"; do + + # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. + symxfrm="\\1 $ac_symprfx\\2 \\2" + + # Write the raw and C identifiers. + if test "$lt_cv_nm_interface" = "MS dumpbin"; then + # Fake it for dumpbin and say T for any non-static function + # and D for any global variable. + # Also find C++ and __fastcall symbols from MSVC++, + # which start with @ or ?. + lt_cv_sys_global_symbol_pipe="$AWK '"\ +" {last_section=section; section=\$ 3};"\ +" /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ +" \$ 0!~/External *\|/{next};"\ +" / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ +" {if(hide[section]) next};"\ +" {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ +" {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ +" s[1]~/^[@?]/{print s[1], s[1]; next};"\ +" s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ +" ' prfx=^$ac_symprfx" + else + lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[ ]\($symcode$symcode*\)[ ][ ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" + fi + + # Check to see that the pipe works correctly. + pipe_works=no + + rm -f conftest* + cat > conftest.$ac_ext <<_LT_EOF +#ifdef __cplusplus +extern "C" { +#endif +char nm_test_var; +void nm_test_func(void); +void nm_test_func(void){} +#ifdef __cplusplus +} +#endif +int main(){nm_test_var='a';nm_test_func();return(0);} +_LT_EOF + + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + # Now try to grab the symbols. + nlist=conftest.nm + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist\""; } >&5 + (eval $NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s "$nlist"; then + # Try sorting and uniquifying the output. + if sort "$nlist" | uniq > "$nlist"T; then + mv -f "$nlist"T "$nlist" + else + rm -f "$nlist"T + fi + + # Make sure that we snagged all the symbols we need. + if $GREP ' nm_test_var$' "$nlist" >/dev/null; then + if $GREP ' nm_test_func$' "$nlist" >/dev/null; then + cat <<_LT_EOF > conftest.$ac_ext +#ifdef __cplusplus +extern "C" { +#endif + +_LT_EOF + # Now generate the symbol file. + eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' + + cat <<_LT_EOF >> conftest.$ac_ext + +/* The mapping between symbol names and symbols. */ +const struct { + const char *name; + void *address; +} +lt__PROGRAM__LTX_preloaded_symbols[] = +{ + { "@PROGRAM@", (void *) 0 }, +_LT_EOF + $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext + cat <<\_LT_EOF >> conftest.$ac_ext + {0, (void *) 0} +}; + +/* This works around a problem in FreeBSD linker */ +#ifdef FREEBSD_WORKAROUND +static const void *lt_preloaded_setup() { + return lt__PROGRAM__LTX_preloaded_symbols; +} +#endif + +#ifdef __cplusplus +} +#endif +_LT_EOF + # Now try linking the two files. + mv conftest.$ac_objext conftstm.$ac_objext + lt_save_LIBS="$LIBS" + lt_save_CFLAGS="$CFLAGS" + LIBS="conftstm.$ac_objext" + CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag" + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext}; then + pipe_works=yes + fi + LIBS="$lt_save_LIBS" + CFLAGS="$lt_save_CFLAGS" + else + echo "cannot find nm_test_func in $nlist" >&5 + fi + else + echo "cannot find nm_test_var in $nlist" >&5 + fi + else + echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5 + fi + else + echo "$progname: failed program was:" >&5 + cat conftest.$ac_ext >&5 + fi + rm -rf conftest* conftst* + + # Do not use the global_symbol_pipe unless it works. + if test "$pipe_works" = yes; then + break + else + lt_cv_sys_global_symbol_pipe= + fi +done + +fi + +if test -z "$lt_cv_sys_global_symbol_pipe"; then + lt_cv_sys_global_symbol_to_cdecl= +fi +if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: failed" >&5 +$as_echo "failed" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok" >&5 +$as_echo "ok" >&6; } +fi + + + + + + + + + + + + + + + + + + + + + + +# Check whether --enable-libtool-lock was given. +if test "${enable_libtool_lock+set}" = set; then : + enableval=$enable_libtool_lock; +fi + +test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes + +# Some flags need to be propagated to the compiler or linker for good +# libtool support. +case $host in +ia64-*-hpux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.$ac_objext` in + *ELF-32*) + HPUX_IA64_MODE="32" + ;; + *ELF-64*) + HPUX_IA64_MODE="64" + ;; + esac + fi + rm -rf conftest* + ;; +*-*-irix6*) + # Find out which ABI we are using. + echo '#line '$LINENO' "configure"' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + if test "$lt_cv_prog_gnu_ld" = yes; then + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -melf32bsmip" + ;; + *N32*) + LD="${LD-ld} -melf32bmipn32" + ;; + *64-bit*) + LD="${LD-ld} -melf64bmip" + ;; + esac + else + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -32" + ;; + *N32*) + LD="${LD-ld} -n32" + ;; + *64-bit*) + LD="${LD-ld} -64" + ;; + esac + fi + fi + rm -rf conftest* + ;; + +x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ +s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.o` in + *32-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_i386_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_i386" + ;; + ppc64-*linux*|powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) + LD="${LD-ld} -m elf_s390" + ;; + sparc64-*linux*) + LD="${LD-ld} -m elf32_sparc" + ;; + esac + ;; + *64-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_x86_64_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; + ppc*-*linux*|powerpc*-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) + LD="${LD-ld} -m elf64_s390" + ;; + sparc*-*linux*) + LD="${LD-ld} -m elf64_sparc" + ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; + +*-*-sco3.2v5*) + # On SCO OpenServer 5, we need -belf to get full-featured binaries. + SAVE_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -belf" + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler needs -belf" >&5 +$as_echo_n "checking whether the C compiler needs -belf... " >&6; } +if test "${lt_cv_cc_needs_belf+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + lt_cv_cc_needs_belf=yes +else + lt_cv_cc_needs_belf=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_cc_needs_belf" >&5 +$as_echo "$lt_cv_cc_needs_belf" >&6; } + if test x"$lt_cv_cc_needs_belf" != x"yes"; then + # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf + CFLAGS="$SAVE_CFLAGS" + fi + ;; +sparc*-*solaris*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + case `/usr/bin/file conftest.o` in + *64-bit*) + case $lt_cv_prog_gnu_ld in + yes*) LD="${LD-ld} -m elf64_sparc" ;; + *) + if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then + LD="${LD-ld} -64" + fi + ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; +esac + +need_locks="$enable_libtool_lock" + + + case $host_os in + rhapsody* | darwin*) + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}dsymutil", so it can be a program name with args. +set dummy ${ac_tool_prefix}dsymutil; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_DSYMUTIL+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$DSYMUTIL"; then + ac_cv_prog_DSYMUTIL="$DSYMUTIL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_DSYMUTIL="${ac_tool_prefix}dsymutil" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +DSYMUTIL=$ac_cv_prog_DSYMUTIL +if test -n "$DSYMUTIL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DSYMUTIL" >&5 +$as_echo "$DSYMUTIL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_DSYMUTIL"; then + ac_ct_DSYMUTIL=$DSYMUTIL + # Extract the first word of "dsymutil", so it can be a program name with args. +set dummy dsymutil; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_DSYMUTIL+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_DSYMUTIL"; then + ac_cv_prog_ac_ct_DSYMUTIL="$ac_ct_DSYMUTIL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_DSYMUTIL="dsymutil" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_DSYMUTIL=$ac_cv_prog_ac_ct_DSYMUTIL +if test -n "$ac_ct_DSYMUTIL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DSYMUTIL" >&5 +$as_echo "$ac_ct_DSYMUTIL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_DSYMUTIL" = x; then + DSYMUTIL=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + DSYMUTIL=$ac_ct_DSYMUTIL + fi +else + DSYMUTIL="$ac_cv_prog_DSYMUTIL" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}nmedit", so it can be a program name with args. +set dummy ${ac_tool_prefix}nmedit; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_NMEDIT+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$NMEDIT"; then + ac_cv_prog_NMEDIT="$NMEDIT" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_NMEDIT="${ac_tool_prefix}nmedit" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +NMEDIT=$ac_cv_prog_NMEDIT +if test -n "$NMEDIT"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $NMEDIT" >&5 +$as_echo "$NMEDIT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_NMEDIT"; then + ac_ct_NMEDIT=$NMEDIT + # Extract the first word of "nmedit", so it can be a program name with args. +set dummy nmedit; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_NMEDIT+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_NMEDIT"; then + ac_cv_prog_ac_ct_NMEDIT="$ac_ct_NMEDIT" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_NMEDIT="nmedit" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_NMEDIT=$ac_cv_prog_ac_ct_NMEDIT +if test -n "$ac_ct_NMEDIT"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_NMEDIT" >&5 +$as_echo "$ac_ct_NMEDIT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_NMEDIT" = x; then + NMEDIT=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + NMEDIT=$ac_ct_NMEDIT + fi +else + NMEDIT="$ac_cv_prog_NMEDIT" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}lipo", so it can be a program name with args. +set dummy ${ac_tool_prefix}lipo; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_LIPO+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$LIPO"; then + ac_cv_prog_LIPO="$LIPO" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_LIPO="${ac_tool_prefix}lipo" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +LIPO=$ac_cv_prog_LIPO +if test -n "$LIPO"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LIPO" >&5 +$as_echo "$LIPO" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_LIPO"; then + ac_ct_LIPO=$LIPO + # Extract the first word of "lipo", so it can be a program name with args. +set dummy lipo; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_LIPO+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_LIPO"; then + ac_cv_prog_ac_ct_LIPO="$ac_ct_LIPO" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_LIPO="lipo" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_LIPO=$ac_cv_prog_ac_ct_LIPO +if test -n "$ac_ct_LIPO"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_LIPO" >&5 +$as_echo "$ac_ct_LIPO" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_LIPO" = x; then + LIPO=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + LIPO=$ac_ct_LIPO + fi +else + LIPO="$ac_cv_prog_LIPO" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}otool", so it can be a program name with args. +set dummy ${ac_tool_prefix}otool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_OTOOL+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OTOOL"; then + ac_cv_prog_OTOOL="$OTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_OTOOL="${ac_tool_prefix}otool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OTOOL=$ac_cv_prog_OTOOL +if test -n "$OTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL" >&5 +$as_echo "$OTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OTOOL"; then + ac_ct_OTOOL=$OTOOL + # Extract the first word of "otool", so it can be a program name with args. +set dummy otool; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_OTOOL+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OTOOL"; then + ac_cv_prog_ac_ct_OTOOL="$ac_ct_OTOOL" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_OTOOL="otool" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OTOOL=$ac_cv_prog_ac_ct_OTOOL +if test -n "$ac_ct_OTOOL"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL" >&5 +$as_echo "$ac_ct_OTOOL" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OTOOL" = x; then + OTOOL=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OTOOL=$ac_ct_OTOOL + fi +else + OTOOL="$ac_cv_prog_OTOOL" +fi + + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}otool64", so it can be a program name with args. +set dummy ${ac_tool_prefix}otool64; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_OTOOL64+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$OTOOL64"; then + ac_cv_prog_OTOOL64="$OTOOL64" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_OTOOL64="${ac_tool_prefix}otool64" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +OTOOL64=$ac_cv_prog_OTOOL64 +if test -n "$OTOOL64"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL64" >&5 +$as_echo "$OTOOL64" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_OTOOL64"; then + ac_ct_OTOOL64=$OTOOL64 + # Extract the first word of "otool64", so it can be a program name with args. +set dummy otool64; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_OTOOL64+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_OTOOL64"; then + ac_cv_prog_ac_ct_OTOOL64="$ac_ct_OTOOL64" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_OTOOL64="otool64" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_OTOOL64=$ac_cv_prog_ac_ct_OTOOL64 +if test -n "$ac_ct_OTOOL64"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL64" >&5 +$as_echo "$ac_ct_OTOOL64" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_OTOOL64" = x; then + OTOOL64=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + OTOOL64=$ac_ct_OTOOL64 + fi +else + OTOOL64="$ac_cv_prog_OTOOL64" +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -single_module linker flag" >&5 +$as_echo_n "checking for -single_module linker flag... " >&6; } +if test "${lt_cv_apple_cc_single_mod+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_apple_cc_single_mod=no + if test -z "${LT_MULTI_MODULE}"; then + # By default we will add the -single_module flag. You can override + # by either setting the environment variable LT_MULTI_MODULE + # non-empty at configure time, or by adding -multi_module to the + # link flags. + rm -rf libconftest.dylib* + echo "int foo(void){return 1;}" > conftest.c + echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ +-dynamiclib -Wl,-single_module conftest.c" >&5 + $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ + -dynamiclib -Wl,-single_module conftest.c 2>conftest.err + _lt_result=$? + if test -f libconftest.dylib && test ! -s conftest.err && test $_lt_result = 0; then + lt_cv_apple_cc_single_mod=yes + else + cat conftest.err >&5 + fi + rm -rf libconftest.dylib* + rm -f conftest.* + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_apple_cc_single_mod" >&5 +$as_echo "$lt_cv_apple_cc_single_mod" >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -exported_symbols_list linker flag" >&5 +$as_echo_n "checking for -exported_symbols_list linker flag... " >&6; } +if test "${lt_cv_ld_exported_symbols_list+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_exported_symbols_list=no + save_LDFLAGS=$LDFLAGS + echo "_main" > conftest.sym + LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + lt_cv_ld_exported_symbols_list=yes +else + lt_cv_ld_exported_symbols_list=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_exported_symbols_list" >&5 +$as_echo "$lt_cv_ld_exported_symbols_list" >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -force_load linker flag" >&5 +$as_echo_n "checking for -force_load linker flag... " >&6; } +if test "${lt_cv_ld_force_load+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_ld_force_load=no + cat > conftest.c << _LT_EOF +int forced_loaded() { return 2;} +_LT_EOF + echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&5 + $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&5 + echo "$AR cru libconftest.a conftest.o" >&5 + $AR cru libconftest.a conftest.o 2>&5 + cat > conftest.c << _LT_EOF +int main() { return 0;} +_LT_EOF + echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&5 + $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err + _lt_result=$? + if test -f conftest && test ! -s conftest.err && test $_lt_result = 0 && $GREP forced_load conftest 2>&1 >/dev/null; then + lt_cv_ld_force_load=yes + else + cat conftest.err >&5 + fi + rm -f conftest.err libconftest.a conftest conftest.c + rm -rf conftest.dSYM + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_force_load" >&5 +$as_echo "$lt_cv_ld_force_load" >&6; } + case $host_os in + rhapsody* | darwin1.[012]) + _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;; + darwin1.*) + _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; + darwin*) # darwin 5.x on + # if running on 10.5 or later, the deployment target defaults + # to the OS version, if on x86, and 10.4, the deployment + # target defaults to 10.4. Don't you love it? + case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in + 10.0,*86*-darwin8*|10.0,*-darwin[91]*) + _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; + 10.[012]*) + _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; + 10.*) + _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; + esac + ;; + esac + if test "$lt_cv_apple_cc_single_mod" = "yes"; then + _lt_dar_single_mod='$single_module' + fi + if test "$lt_cv_ld_exported_symbols_list" = "yes"; then + _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym' + else + _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}' + fi + if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then + _lt_dsymutil='~$DSYMUTIL $lib || :' + else + _lt_dsymutil= + fi + ;; + esac + +for ac_header in dlfcn.h +do : + ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default +" +if test "x$ac_cv_header_dlfcn_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_DLFCN_H 1 +_ACEOF + +fi + +done + + + + + +# Set options + + + + enable_dlopen=no + + + enable_win32_dll=no + + + + # Check whether --enable-static was given. +if test "${enable_static+set}" = set; then : + enableval=$enable_static; p=${PACKAGE-default} + case $enableval in + yes) enable_static=yes ;; + no) enable_static=no ;; + *) + enable_static=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_static=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_static=yes +fi + + + + + + + + + + +# Check whether --with-pic was given. +if test "${with_pic+set}" = set; then : + withval=$with_pic; pic_mode="$withval" +else + pic_mode=default +fi + + +test -z "$pic_mode" && pic_mode=default + + + + + + + + # Check whether --enable-fast-install was given. +if test "${enable_fast_install+set}" = set; then : + enableval=$enable_fast_install; p=${PACKAGE-default} + case $enableval in + yes) enable_fast_install=yes ;; + no) enable_fast_install=no ;; + *) + enable_fast_install=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_fast_install=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac +else + enable_fast_install=yes +fi + + + + + + + + + + + +# This can be used to rebuild libtool when needed +LIBTOOL_DEPS="$ltmain" + +# Always use our own libtool. +LIBTOOL='$(SHELL) $(top_builddir)/libtool' + + + + + + + + + + + + + + + + + + + + + + + + + + +test -z "$LN_S" && LN_S="ln -s" + + + + + + + + + + + + + + +if test -n "${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for objdir" >&5 +$as_echo_n "checking for objdir... " >&6; } +if test "${lt_cv_objdir+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + rm -f .libs 2>/dev/null +mkdir .libs 2>/dev/null +if test -d .libs; then + lt_cv_objdir=.libs +else + # MS-DOS does not allow filenames that begin with a dot. + lt_cv_objdir=_libs +fi +rmdir .libs 2>/dev/null +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_objdir" >&5 +$as_echo "$lt_cv_objdir" >&6; } +objdir=$lt_cv_objdir + + + + + +cat >>confdefs.h <<_ACEOF +#define LT_OBJDIR "$lt_cv_objdir/" +_ACEOF + + + + +case $host_os in +aix3*) + # AIX sometimes has problems with the GCC collect2 program. For some + # reason, if we set the COLLECT_NAMES environment variable, the problems + # vanish in a puff of smoke. + if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES + fi + ;; +esac + +# Global variables: +ofile=libtool +can_build_shared=yes + +# All known linkers require a `.a' archive for static linking (except MSVC, +# which needs '.lib'). +libext=a + +with_gnu_ld="$lt_cv_prog_gnu_ld" + +old_CC="$CC" +old_CFLAGS="$CFLAGS" + +# Set sane defaults for various variables +test -z "$CC" && CC=cc +test -z "$LTCC" && LTCC=$CC +test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS +test -z "$LD" && LD=ld +test -z "$ac_objext" && ac_objext=o + +for cc_temp in $compiler""; do + case $cc_temp in + compile | *[\\/]compile | ccache | *[\\/]ccache ) ;; + distcc | *[\\/]distcc | purify | *[\\/]purify ) ;; + \-*) ;; + *) break;; + esac +done +cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"` + + +# Only perform the check for file, if the check method requires it +test -z "$MAGIC_CMD" && MAGIC_CMD=file +case $deplibs_check_method in +file_magic*) + if test "$file_magic_cmd" = '$MAGIC_CMD'; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ${ac_tool_prefix}file" >&5 +$as_echo_n "checking for ${ac_tool_prefix}file... " >&6; } +if test "${lt_cv_path_MAGIC_CMD+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/${ac_tool_prefix}file; then + lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 +$as_echo "$MAGIC_CMD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + + + +if test -z "$lt_cv_path_MAGIC_CMD"; then + if test -n "$ac_tool_prefix"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for file" >&5 +$as_echo_n "checking for file... " >&6; } +if test "${lt_cv_path_MAGIC_CMD+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/file; then + lt_cv_path_MAGIC_CMD="$ac_dir/file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac +fi + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 +$as_echo "$MAGIC_CMD" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + else + MAGIC_CMD=: + fi +fi + + fi + ;; +esac + +# Use C for the default configuration in the libtool script + +lt_save_CC="$CC" +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +# Source file extension for C test sources. +ac_ext=c + +# Object file extension for compiled C test sources. +objext=o +objext=$objext + +# Code to be used in simple compile tests +lt_simple_compile_test_code="int some_variable = 0;" + +# Code to be used in simple link tests +lt_simple_link_test_code='int main(){return(0);}' + + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + +# Save the default compiler, since it gets overwritten when the other +# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP. +compiler_DEFAULT=$CC + +# save warnings/boilerplate of simple test code +ac_outfile=conftest.$ac_objext +echo "$lt_simple_compile_test_code" >conftest.$ac_ext +eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_compiler_boilerplate=`cat conftest.err` +$RM conftest* + +ac_outfile=conftest.$ac_objext +echo "$lt_simple_link_test_code" >conftest.$ac_ext +eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_linker_boilerplate=`cat conftest.err` +$RM -r conftest* + + +## CAVEAT EMPTOR: +## There is no encapsulation within the following macros, do not change +## the running order or otherwise move them around unless you know exactly +## what you are doing... +if test -n "$compiler"; then + +lt_prog_compiler_no_builtin_flag= + +if test "$GCC" = yes; then + case $cc_basename in + nvcc*) + lt_prog_compiler_no_builtin_flag=' -Xcompiler -fno-builtin' ;; + *) + lt_prog_compiler_no_builtin_flag=' -fno-builtin' ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -fno-rtti -fno-exceptions" >&5 +$as_echo_n "checking if $compiler supports -fno-rtti -fno-exceptions... " >&6; } +if test "${lt_cv_prog_compiler_rtti_exceptions+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_rtti_exceptions=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="-fno-rtti -fno-exceptions" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_rtti_exceptions=yes + fi + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_rtti_exceptions" >&5 +$as_echo "$lt_cv_prog_compiler_rtti_exceptions" >&6; } + +if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then + lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions" +else + : +fi + +fi + + + + + + + lt_prog_compiler_wl= +lt_prog_compiler_pic= +lt_prog_compiler_static= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $compiler option to produce PIC" >&5 +$as_echo_n "checking for $compiler option to produce PIC... " >&6; } + + if test "$GCC" = yes; then + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_static='-static' + + case $host_os in + aix*) + # All AIX code is PIC. + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + lt_prog_compiler_pic='-fPIC' + ;; + m68k) + # FIXME: we need at least 68020 code to build shared libraries, but + # adding the `-m68020' flag to GCC prevents building anything better, + # like `-m68040'. + lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4' + ;; + esac + ;; + + beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) + # PIC is the default for these OSes. + ;; + + mingw* | cygwin* | pw32* | os2* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + # Although the cygwin gcc ignores -fPIC, still need this for old-style + # (--disable-auto-import) libraries + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + darwin* | rhapsody*) + # PIC is the default on this platform + # Common symbols not allowed in MH_DYLIB files + lt_prog_compiler_pic='-fno-common' + ;; + + haiku*) + # PIC is the default for Haiku. + # The "-static" flag exists, but is broken. + lt_prog_compiler_static= + ;; + + hpux*) + # PIC is the default for 64-bit PA HP-UX, but not for 32-bit + # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag + # sets the default TLS model and affects inlining. + case $host_cpu in + hppa*64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + ;; + + interix[3-9]*) + # Interix 3.x gcc -fpic/-fPIC options generate broken code. + # Instead, we relocate shared libraries at runtime. + ;; + + msdosdjgpp*) + # Just because we use GCC doesn't mean we suddenly get shared libraries + # on systems that don't support them. + lt_prog_compiler_can_build_shared=no + enable_shared=no + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + lt_prog_compiler_pic=-Kconform_pic + fi + ;; + + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + + case $cc_basename in + nvcc*) # Cuda Compiler Driver 2.2 + lt_prog_compiler_wl='-Xlinker ' + lt_prog_compiler_pic='-Xcompiler -fPIC' + ;; + esac + else + # PORTME Check for flag to pass linker flags through the system compiler. + case $host_os in + aix*) + lt_prog_compiler_wl='-Wl,' + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + else + lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp' + fi + ;; + + mingw* | cygwin* | pw32* | os2* | cegcc*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + hpux9* | hpux10* | hpux11*) + lt_prog_compiler_wl='-Wl,' + # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but + # not for PA HP-UX. + case $host_cpu in + hppa*64*|ia64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='+Z' + ;; + esac + # Is there a better lt_prog_compiler_static that works with the bundled CC? + lt_prog_compiler_static='${wl}-a ${wl}archive' + ;; + + irix5* | irix6* | nonstopux*) + lt_prog_compiler_wl='-Wl,' + # PIC (with -KPIC) is the default. + lt_prog_compiler_static='-non_shared' + ;; + + linux* | k*bsd*-gnu | kopensolaris*-gnu) + case $cc_basename in + # old Intel for x86_64 which still supported -KPIC. + ecc*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-static' + ;; + # icc used to be incompatible with GCC. + # ICC 10 doesn't accept -KPIC any more. + icc* | ifort*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fPIC' + lt_prog_compiler_static='-static' + ;; + # Lahey Fortran 8.1. + lf95*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='--shared' + lt_prog_compiler_static='--static' + ;; + pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*) + # Portland Group compilers (*not* the Pentium gcc compiler, + # which looks to be a dead project) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fpic' + lt_prog_compiler_static='-Bstatic' + ;; + ccc*) + lt_prog_compiler_wl='-Wl,' + # All Alpha code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + xl* | bgxl* | bgf* | mpixl*) + # IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-qpic' + lt_prog_compiler_static='-qstaticlink' + ;; + *) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ F* | *Sun*Fortran*) + # Sun Fortran 8.3 passes all unrecognized flags to the linker + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='' + ;; + *Sun\ C*) + # Sun C 5.9 + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='-Wl,' + ;; + esac + ;; + esac + ;; + + newsos6) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + osf3* | osf4* | osf5*) + lt_prog_compiler_wl='-Wl,' + # All OSF/1 code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + + rdos*) + lt_prog_compiler_static='-non_shared' + ;; + + solaris*) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + case $cc_basename in + f77* | f90* | f95*) + lt_prog_compiler_wl='-Qoption ld ';; + *) + lt_prog_compiler_wl='-Wl,';; + esac + ;; + + sunos4*) + lt_prog_compiler_wl='-Qoption ld ' + lt_prog_compiler_pic='-PIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4 | sysv4.2uw2* | sysv4.3*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4*MP*) + if test -d /usr/nec ;then + lt_prog_compiler_pic='-Kconform_pic' + lt_prog_compiler_static='-Bstatic' + fi + ;; + + sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + unicos*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_can_build_shared=no + ;; + + uts4*) + lt_prog_compiler_pic='-pic' + lt_prog_compiler_static='-Bstatic' + ;; + + *) + lt_prog_compiler_can_build_shared=no + ;; + esac + fi + +case $host_os in + # For platforms which do not support PIC, -DPIC is meaningless: + *djgpp*) + lt_prog_compiler_pic= + ;; + *) + lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC" + ;; +esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_prog_compiler_pic" >&5 +$as_echo "$lt_prog_compiler_pic" >&6; } + + + + + + +# +# Check to make sure the PIC flag actually works. +# +if test -n "$lt_prog_compiler_pic"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5 +$as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic works... " >&6; } +if test "${lt_cv_prog_compiler_pic_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_pic_works=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="$lt_prog_compiler_pic -DPIC" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_pic_works=yes + fi + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_works" >&5 +$as_echo "$lt_cv_prog_compiler_pic_works" >&6; } + +if test x"$lt_cv_prog_compiler_pic_works" = xyes; then + case $lt_prog_compiler_pic in + "" | " "*) ;; + *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;; + esac +else + lt_prog_compiler_pic= + lt_prog_compiler_can_build_shared=no +fi + +fi + + + + + + +# +# Check to make sure the static flag actually works. +# +wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 +$as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } +if test "${lt_cv_prog_compiler_static_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_static_works=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS $lt_tmp_static_flag" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_static_works=yes + fi + else + lt_cv_prog_compiler_static_works=yes + fi + fi + $RM -r conftest* + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_static_works" >&5 +$as_echo "$lt_cv_prog_compiler_static_works" >&6; } + +if test x"$lt_cv_prog_compiler_static_works" = xyes; then + : +else + lt_prog_compiler_static= +fi + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if test "${lt_cv_prog_compiler_c_o+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 +$as_echo "$lt_cv_prog_compiler_c_o" >&6; } + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 +$as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } +if test "${lt_cv_prog_compiler_c_o+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 +$as_echo "$lt_cv_prog_compiler_c_o" >&6; } + + + + +hard_links="nottested" +if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then + # do not overwrite the value of need_locks provided by the user + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if we can lock with hard links" >&5 +$as_echo_n "checking if we can lock with hard links... " >&6; } + hard_links=yes + $RM conftest* + ln conftest.a conftest.b 2>/dev/null && hard_links=no + touch conftest.a + ln conftest.a conftest.b 2>&5 || hard_links=no + ln conftest.a conftest.b 2>/dev/null && hard_links=no + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hard_links" >&5 +$as_echo "$hard_links" >&6; } + if test "$hard_links" = no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5 +$as_echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;} + need_locks=warn + fi +else + need_locks=no +fi + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5 +$as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; } + + runpath_var= + allow_undefined_flag= + always_export_symbols=no + archive_cmds= + archive_expsym_cmds= + compiler_needs_object=no + enable_shared_with_static_runtimes=no + export_dynamic_flag_spec= + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' + hardcode_automatic=no + hardcode_direct=no + hardcode_direct_absolute=no + hardcode_libdir_flag_spec= + hardcode_libdir_flag_spec_ld= + hardcode_libdir_separator= + hardcode_minus_L=no + hardcode_shlibpath_var=unsupported + inherit_rpath=no + link_all_deplibs=unknown + module_cmds= + module_expsym_cmds= + old_archive_from_new_cmds= + old_archive_from_expsyms_cmds= + thread_safe_flag_spec= + whole_archive_flag_spec= + # include_expsyms should be a list of space-separated symbols to be *always* + # included in the symbol list + include_expsyms= + # exclude_expsyms can be an extended regexp of symbols to exclude + # it will be wrapped by ` (' and `)$', so one must not match beginning or + # end of line. Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc', + # as well as any symbol that contains `d'. + exclude_expsyms='_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*' + # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out + # platforms (ab)use it in PIC code, but their linkers get confused if + # the symbol is explicitly referenced. Since portable code cannot + # rely on this symbol name, it's probably fine to never include it in + # preloaded symbol tables. + # Exclude shared library initialization/finalization symbols. + extract_expsyms_cmds= + + case $host_os in + cygwin* | mingw* | pw32* | cegcc*) + # FIXME: the MSVC++ port hasn't been tested in a loooong time + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + if test "$GCC" != yes; then + with_gnu_ld=no + fi + ;; + interix*) + # we just hope/assume this is gcc and not c89 (= MSVC++) + with_gnu_ld=yes + ;; + openbsd*) + with_gnu_ld=no + ;; + esac + + ld_shlibs=yes + + # On some targets, GNU ld is compatible enough with the native linker + # that we're better off using the native interface for both. + lt_use_gnu_ld_interface=no + if test "$with_gnu_ld" = yes; then + case $host_os in + aix*) + # The AIX port of GNU ld has always aspired to compatibility + # with the native linker. However, as the warning in the GNU ld + # block says, versions before 2.19.5* couldn't really create working + # shared libraries, regardless of the interface used. + case `$LD -v 2>&1` in + *\ \(GNU\ Binutils\)\ 2.19.5*) ;; + *\ \(GNU\ Binutils\)\ 2.[2-9]*) ;; + *\ \(GNU\ Binutils\)\ [3-9]*) ;; + *) + lt_use_gnu_ld_interface=yes + ;; + esac + ;; + *) + lt_use_gnu_ld_interface=yes + ;; + esac + fi + + if test "$lt_use_gnu_ld_interface" = yes; then + # If archive_cmds runs LD, not CC, wlarc should be empty + wlarc='${wl}' + + # Set some defaults for GNU ld with shared library support. These + # are reset later if shared libraries are not supported. Putting them + # here allows them to be overridden if necessary. + runpath_var=LD_RUN_PATH + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + export_dynamic_flag_spec='${wl}--export-dynamic' + # ancient GNU ld didn't support --whole-archive et. al. + if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then + whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' + else + whole_archive_flag_spec= + fi + supports_anon_versioning=no + case `$LD -v 2>&1` in + *GNU\ gold*) supports_anon_versioning=yes ;; + *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11 + *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ... + *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ... + *\ 2.11.*) ;; # other 2.11 versions + *) supports_anon_versioning=yes ;; + esac + + # See if GNU ld supports shared libraries. + case $host_os in + aix[3-9]*) + # On AIX/PPC, the GNU linker is very broken + if test "$host_cpu" != ia64; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: the GNU linker, at least up to release 2.19, is reported +*** to be unable to reliably create shared libraries on AIX. +*** Therefore, libtool is disabling shared libraries support. If you +*** really care for shared libraries, you may want to install binutils +*** 2.20 or above, or modify your PATH so that a non-GNU linker is found. +*** You will then need to restart the configuration process. + +_LT_EOF + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='' + ;; + m68k) + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + ;; + esac + ;; + + beos*) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + allow_undefined_flag=unsupported + # Joseph Beckenbach says some releases of gcc + # support --undefined. This deserves some investigation. FIXME + archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + else + ld_shlibs=no + fi + ;; + + cygwin* | mingw* | pw32* | cegcc*) + # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless, + # as there is no search path for DLLs. + hardcode_libdir_flag_spec='-L$libdir' + export_dynamic_flag_spec='${wl}--export-all-symbols' + allow_undefined_flag=unsupported + always_export_symbols=no + enable_shared_with_static_runtimes=yes + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols' + + if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + # If the export-symbols file already is a .def file (1st line + # is EXPORTS), use it as is; otherwise, prepend... + archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + cp $export_symbols $output_objdir/$soname.def; + else + echo EXPORTS > $output_objdir/$soname.def; + cat $export_symbols >> $output_objdir/$soname.def; + fi~ + $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + else + ld_shlibs=no + fi + ;; + + haiku*) + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + link_all_deplibs=yes + ;; + + interix[3-9]*) + hardcode_direct=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. + # Instead, shared libraries are loaded at an image base (0x10000000 by + # default) and relocated if they conflict, which is a slow very memory + # consuming and fragmenting process. To avoid this, we pick a random, + # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link + # time. Moving up from 0x10000000 also allows more sbrk(2) space. + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + ;; + + gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu) + tmp_diet=no + if test "$host_os" = linux-dietlibc; then + case $cc_basename in + diet\ *) tmp_diet=yes;; # linux-dietlibc with static linking (!diet-dyn) + esac + fi + if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \ + && test "$tmp_diet" = no + then + tmp_addflag= + tmp_sharedflag='-shared' + case $cc_basename,$host_cpu in + pgcc*) # Portland Group C compiler + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag' + ;; + pgf77* | pgf90* | pgf95* | pgfortran*) + # Portland Group f77 and f90 compilers + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag -Mnomain' ;; + ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 + tmp_addflag=' -i_dynamic' ;; + efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 + tmp_addflag=' -i_dynamic -nofor_main' ;; + ifc* | ifort*) # Intel Fortran compiler + tmp_addflag=' -nofor_main' ;; + lf95*) # Lahey Fortran 8.1 + whole_archive_flag_spec= + tmp_sharedflag='--shared' ;; + xl[cC]* | bgxl[cC]* | mpixl[cC]*) # IBM XL C 8.0 on PPC (deal with xlf below) + tmp_sharedflag='-qmkshrobj' + tmp_addflag= ;; + nvcc*) # Cuda Compiler Driver 2.2 + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object=yes + ;; + esac + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) # Sun C 5.9 + whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object=yes + tmp_sharedflag='-G' ;; + *Sun\ F*) # Sun Fortran 8.3 + tmp_sharedflag='-G' ;; + esac + archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' + fi + + case $cc_basename in + xlf* | bgf* | bgxlf* | mpixlf*) + # IBM XL Fortran 10.1 on PPC cannot create shared libs itself + whole_archive_flag_spec='--whole-archive$convenience --no-whole-archive' + hardcode_libdir_flag_spec= + hardcode_libdir_flag_spec_ld='-rpath $libdir' + archive_cmds='$LD -shared $libobjs $deplibs $compiler_flags -soname $soname -o $lib' + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $LD -shared $libobjs $deplibs $compiler_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib' + fi + ;; + esac + else + ld_shlibs=no + fi + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' + wlarc= + else + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + fi + ;; + + solaris*) + if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: The releases 2.8.* of the GNU linker cannot reliably +*** create shared libraries on Solaris systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.9.1 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + + sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) + case `$LD -v 2>&1` in + *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*) + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not +*** reliably create shared libraries on SCO systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.16.91.0.3 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + ;; + *) + # For security reasons, it is highly recommended that you always + # use absolute paths for naming shared libraries, and exclude the + # DT_RUNPATH tag from executables and libraries. But doing so + # requires that you compile everything twice, which is a pain. + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + ;; + + sunos4*) + archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' + wlarc= + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + *) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + + if test "$ld_shlibs" = no; then + runpath_var= + hardcode_libdir_flag_spec= + export_dynamic_flag_spec= + whole_archive_flag_spec= + fi + else + # PORTME fill in a description of your system's linker (not GNU ld) + case $host_os in + aix3*) + allow_undefined_flag=unsupported + always_export_symbols=yes + archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' + # Note: this linker hardcodes the directories in LIBPATH if there + # are no directories specified by -L. + hardcode_minus_L=yes + if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then + # Neither direct hardcoding nor static linking is supported with a + # broken collect2. + hardcode_direct=unsupported + fi + ;; + + aix[4-9]*) + if test "$host_cpu" = ia64; then + # On IA64, the linker does run time linking by default, so we don't + # have to do anything special. + aix_use_runtimelinking=no + exp_sym_flag='-Bexport' + no_entry_flag="" + else + # If we're using GNU nm, then we don't want the "-C" option. + # -C means demangle to AIX nm, but means don't demangle with GNU nm + # Also, AIX nm treats weak defined symbols like other global + # defined symbols, whereas GNU nm marks them as "W". + if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then + export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + else + export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + fi + aix_use_runtimelinking=no + + # Test if we are trying to use run time linking or normal + # AIX style linking. If -brtl is somewhere in LDFLAGS, we + # need to do runtime linking. + case $host_os in aix4.[23]|aix4.[23].*|aix[5-9]*) + for ld_flag in $LDFLAGS; do + if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then + aix_use_runtimelinking=yes + break + fi + done + ;; + esac + + exp_sym_flag='-bexport' + no_entry_flag='-bnoentry' + fi + + # When large executables or shared objects are built, AIX ld can + # have problems creating the table of contents. If linking a library + # or program results in "error TOC overflow" add -mminimal-toc to + # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not + # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. + + archive_cmds='' + hardcode_direct=yes + hardcode_direct_absolute=yes + hardcode_libdir_separator=':' + link_all_deplibs=yes + file_list_spec='${wl}-f,' + + if test "$GCC" = yes; then + case $host_os in aix4.[012]|aix4.[012].*) + # We only want to do this on AIX 4.2 and lower, the check + # below for broken collect2 doesn't work under 4.3+ + collect2name=`${CC} -print-prog-name=collect2` + if test -f "$collect2name" && + strings "$collect2name" | $GREP resolve_lib_name >/dev/null + then + # We have reworked collect2 + : + else + # We have old collect2 + hardcode_direct=unsupported + # It fails to find uninstalled libraries when the uninstalled + # path is not listed in the libpath. Setting hardcode_minus_L + # to unsupported forces relinking + hardcode_minus_L=yes + hardcode_libdir_flag_spec='-L$libdir' + hardcode_libdir_separator= + fi + ;; + esac + shared_flag='-shared' + if test "$aix_use_runtimelinking" = yes; then + shared_flag="$shared_flag "'${wl}-G' + fi + else + # not using gcc + if test "$host_cpu" = ia64; then + # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release + # chokes on -Wl,-G. The following line is correct: + shared_flag='-G' + else + if test "$aix_use_runtimelinking" = yes; then + shared_flag='${wl}-G' + else + shared_flag='${wl}-bM:SRE' + fi + fi + fi + + export_dynamic_flag_spec='${wl}-bexpall' + # It seems that -bexpall does not export symbols beginning with + # underscore (_), so it is better to generate a list of symbols to export. + always_export_symbols=yes + if test "$aix_use_runtimelinking" = yes; then + # Warning - without using the other runtime loading flags (-brtl), + # -berok will link without error, but may produce a broken library. + allow_undefined_flag='-berok' + # Determine the default libpath from the value encoded in an + # empty executable. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\(.*\)$/\1/ + p + } + }' +aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +# Check for a 64-bit object if we didn't find anything. +if test -z "$aix_libpath"; then + aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi + + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" + else + if test "$host_cpu" = ia64; then + hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib' + allow_undefined_flag="-z nodefs" + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" + else + # Determine the default libpath from the value encoded in an + # empty executable. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\(.*\)$/\1/ + p + } + }' +aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +# Check for a 64-bit object if we didn't find anything. +if test -z "$aix_libpath"; then + aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi + + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + # Warning - without using the other run time loading flags, + # -berok will link without error, but may produce a broken library. + no_undefined_flag=' ${wl}-bernotok' + allow_undefined_flag=' ${wl}-berok' + if test "$with_gnu_ld" = yes; then + # We only use this code for GNU lds that support --whole-archive. + whole_archive_flag_spec='${wl}--whole-archive$convenience ${wl}--no-whole-archive' + else + # Exported symbols can be pulled into shared objects from archives + whole_archive_flag_spec='$convenience' + fi + archive_cmds_need_lc=yes + # This is similar to how AIX traditionally builds its shared libraries. + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' + fi + fi + ;; + + amigaos*) + case $host_cpu in + powerpc) + # see comment about AmigaOS4 .so support + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='' + ;; + m68k) + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + ;; + esac + ;; + + bsdi[45]*) + export_dynamic_flag_spec=-rdynamic + ;; + + cygwin* | mingw* | pw32* | cegcc*) + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + hardcode_libdir_flag_spec=' ' + allow_undefined_flag=unsupported + # Tell ltmain to make .lib files, not .a files. + libext=lib + # Tell ltmain to make .dll files, not .so files. + shrext_cmds=".dll" + # FIXME: Setting linknames here is a bad hack. + archive_cmds='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames=' + # The linker will automatically build a .lib file if we build a DLL. + old_archive_from_new_cmds='true' + # FIXME: Should let the user specify the lib program. + old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs' + fix_srcfile_path='`cygpath -w "$srcfile"`' + enable_shared_with_static_runtimes=yes + ;; + + darwin* | rhapsody*) + + + archive_cmds_need_lc=no + hardcode_direct=no + hardcode_automatic=yes + hardcode_shlibpath_var=unsupported + if test "$lt_cv_ld_force_load" = "yes"; then + whole_archive_flag_spec='`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`' + else + whole_archive_flag_spec='' + fi + link_all_deplibs=yes + allow_undefined_flag="$_lt_dar_allow_undefined" + case $cc_basename in + ifort*) _lt_dar_can_shared=yes ;; + *) _lt_dar_can_shared=$GCC ;; + esac + if test "$_lt_dar_can_shared" = "yes"; then + output_verbose_link_cmd=func_echo_all + archive_cmds="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}" + module_cmds="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}" + archive_expsym_cmds="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}" + module_expsym_cmds="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}" + + else + ld_shlibs=no + fi + + ;; + + dgux*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor + # support. Future versions do this automatically, but an explicit c++rt0.o + # does not break anything, and helps significantly (at the cost of a little + # extra space). + freebsd2.2*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + # Unfortunately, older versions of FreeBSD 2 do not have this feature. + freebsd2*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + # FreeBSD 3 and greater uses gcc -shared to do shared libraries. + freebsd* | dragonfly*) + archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + hpux9*) + if test "$GCC" = yes; then + archive_cmds='$RM $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + else + archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + fi + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + export_dynamic_flag_spec='${wl}-E' + ;; + + hpux10*) + if test "$GCC" = yes && test "$with_gnu_ld" = no; then + archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_flag_spec_ld='+b $libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + fi + ;; + + hpux11*) + if test "$GCC" = yes && test "$with_gnu_ld" = no; then + case $host_cpu in + hppa*64*) + archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + else + case $host_cpu in + hppa*64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + + # Older versions of the 11.00 compiler do not understand -b yet + # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $CC understands -b" >&5 +$as_echo_n "checking if $CC understands -b... " >&6; } +if test "${lt_cv_prog_compiler__b+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_prog_compiler__b=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS -b" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler__b=yes + fi + else + lt_cv_prog_compiler__b=yes + fi + fi + $RM -r conftest* + LDFLAGS="$save_LDFLAGS" + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler__b" >&5 +$as_echo "$lt_cv_prog_compiler__b" >&6; } + +if test x"$lt_cv_prog_compiler__b" = xyes; then + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' +else + archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' +fi + + ;; + esac + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + + case $host_cpu in + hppa*64*|ia64*) + hardcode_direct=no + hardcode_shlibpath_var=no + ;; + *) + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + esac + fi + ;; + + irix5* | irix6* | nonstopux*) + if test "$GCC" = yes; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + # Try to use the -exported_symbol ld option, if it does not + # work, assume that -exports_file does not work either and + # implicitly export all symbols. + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +int foo(void) {} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib' + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS="$save_LDFLAGS" + else + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + inherit_rpath=yes + link_all_deplibs=yes + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out + else + archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + newsos6) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_shlibpath_var=no + ;; + + *nto* | *qnx*) + ;; + + openbsd*) + if test -f /usr/libexec/ld.so; then + hardcode_direct=yes + hardcode_shlibpath_var=no + hardcode_direct_absolute=yes + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + else + case $host_os in + openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-R$libdir' + ;; + *) + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + ;; + esac + fi + else + ld_shlibs=no + fi + ;; + + os2*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + allow_undefined_flag=unsupported + archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' + old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' + ;; + + osf3*) + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; + + osf4* | osf5*) # as osf3* with the addition of -msym flag + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~ + $CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp' + + # Both c and cxx compiler support -rpath directly + hardcode_libdir_flag_spec='-rpath $libdir' + fi + archive_cmds_need_lc='no' + hardcode_libdir_separator=: + ;; + + solaris*) + no_undefined_flag=' -z defs' + if test "$GCC" = yes; then + wlarc='${wl}' + archive_cmds='$CC -shared ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -shared ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + else + case `$CC -V 2>&1` in + *"Compilers 5.0"*) + wlarc='' + archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp' + ;; + *) + wlarc='${wl}' + archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + ;; + esac + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_shlibpath_var=no + case $host_os in + solaris2.[0-5] | solaris2.[0-5].*) ;; + *) + # The compiler driver will combine and reorder linker options, + # but understands `-z linker_flag'. GCC discards it without `$wl', + # but is careful enough not to reorder. + # Supported since Solaris 2.6 (maybe 2.5.1?) + if test "$GCC" = yes; then + whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' + else + whole_archive_flag_spec='-z allextract$convenience -z defaultextract' + fi + ;; + esac + link_all_deplibs=yes + ;; + + sunos4*) + if test "x$host_vendor" = xsequent; then + # Use $CC to link under sequent, because it throws in some extra .o + # files that make .init and .fini sections work. + archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' + fi + hardcode_libdir_flag_spec='-L$libdir' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + sysv4) + case $host_vendor in + sni) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes # is this really true??? + ;; + siemens) + ## LD is ld it makes a PLAMLIB + ## CC just makes a GrossModule. + archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags' + reload_cmds='$CC -r -o $output$reload_objs' + hardcode_direct=no + ;; + motorola) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=no #Motorola manual says yes, but my tests say they lie + ;; + esac + runpath_var='LD_RUN_PATH' + hardcode_shlibpath_var=no + ;; + + sysv4.3*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + export_dynamic_flag_spec='-Bexport' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + runpath_var=LD_RUN_PATH + hardcode_runpath_var=yes + ld_shlibs=yes + fi + ;; + + sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) + no_undefined_flag='${wl}-z,text' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + sysv5* | sco3.2v5* | sco5v6*) + # Note: We can NOT use -z defs as we might desire, because we do not + # link with -lc, and that would cause any symbols used from libc to + # always be unresolved, which means just about no library would + # ever link correctly. If we're not using GNU ld we use -z text + # though, which does catch some bad symbols but isn't as heavy-handed + # as -z defs. + no_undefined_flag='${wl}-z,text' + allow_undefined_flag='${wl}-z,nodefs' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-R,$libdir' + hardcode_libdir_separator=':' + link_all_deplibs=yes + export_dynamic_flag_spec='${wl}-Bexport' + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + uts4*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + *) + ld_shlibs=no + ;; + esac + + if test x$host_vendor = xsni; then + case $host in + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + export_dynamic_flag_spec='${wl}-Blargedynsym' + ;; + esac + fi + fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs" >&5 +$as_echo "$ld_shlibs" >&6; } +test "$ld_shlibs" = no && can_build_shared=no + +with_gnu_ld=$with_gnu_ld + + + + + + + + + + + + + + + +# +# Do we need to explicitly link libc? +# +case "x$archive_cmds_need_lc" in +x|xyes) + # Assume -lc should be added + archive_cmds_need_lc=yes + + if test "$enable_shared" = yes && test "$GCC" = yes; then + case $archive_cmds in + *'~'*) + # FIXME: we may have to deal with multi-command sequences. + ;; + '$CC '*) + # Test whether the compiler implicitly links with -lc since on some + # systems, -lgcc has to come before -lc. If gcc already passes -lc + # to ld, don't add -lc before -lgcc. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 +$as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } +if test "${lt_cv_archive_cmds_need_lc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + $RM conftest* + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } 2>conftest.err; then + soname=conftest + lib=conftest + libobjs=conftest.$ac_objext + deplibs= + wl=$lt_prog_compiler_wl + pic_flag=$lt_prog_compiler_pic + compiler_flags=-v + linker_flags=-v + verstring= + output_objdir=. + libname=conftest + lt_save_allow_undefined_flag=$allow_undefined_flag + allow_undefined_flag= + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\""; } >&5 + (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + then + lt_cv_archive_cmds_need_lc=no + else + lt_cv_archive_cmds_need_lc=yes + fi + allow_undefined_flag=$lt_save_allow_undefined_flag + else + cat conftest.err 1>&5 + fi + $RM conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_archive_cmds_need_lc" >&5 +$as_echo "$lt_cv_archive_cmds_need_lc" >&6; } + archive_cmds_need_lc=$lt_cv_archive_cmds_need_lc + ;; + esac + fi + ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking dynamic linker characteristics" >&5 +$as_echo_n "checking dynamic linker characteristics... " >&6; } + +if test "$GCC" = yes; then + case $host_os in + darwin*) lt_awk_arg="/^libraries:/,/LR/" ;; + *) lt_awk_arg="/^libraries:/" ;; + esac + case $host_os in + mingw* | cegcc*) lt_sed_strip_eq="s,=\([A-Za-z]:\),\1,g" ;; + *) lt_sed_strip_eq="s,=/,/,g" ;; + esac + lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq` + case $lt_search_path_spec in + *\;*) + # if the path contains ";" then we assume it to be the separator + # otherwise default to the standard path separator (i.e. ":") - it is + # assumed that no part of a normal pathname contains ";" but that should + # okay in the real world where ";" in dirpaths is itself problematic. + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'` + ;; + *) + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"` + ;; + esac + # Ok, now we have the path, separated by spaces, we can step through it + # and add multilib dir if necessary. + lt_tmp_lt_search_path_spec= + lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null` + for lt_sys_path in $lt_search_path_spec; do + if test -d "$lt_sys_path/$lt_multi_os_dir"; then + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir" + else + test -d "$lt_sys_path" && \ + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path" + fi + done + lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk ' +BEGIN {RS=" "; FS="/|\n";} { + lt_foo=""; + lt_count=0; + for (lt_i = NF; lt_i > 0; lt_i--) { + if ($lt_i != "" && $lt_i != ".") { + if ($lt_i == "..") { + lt_count++; + } else { + if (lt_count == 0) { + lt_foo="/" $lt_i lt_foo; + } else { + lt_count--; + } + } + } + } + if (lt_foo != "") { lt_freq[lt_foo]++; } + if (lt_freq[lt_foo] == 1) { print lt_foo; } +}'` + # AWK program above erroneously prepends '/' to C:/dos/paths + # for these hosts. + case $host_os in + mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\ + $SED 's,/\([A-Za-z]:\),\1,g'` ;; + esac + sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP` +else + sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib" +fi +library_names_spec= +libname_spec='lib$name' +soname_spec= +shrext_cmds=".so" +postinstall_cmds= +postuninstall_cmds= +finish_cmds= +finish_eval= +shlibpath_var= +shlibpath_overrides_runpath=unknown +version_type=none +dynamic_linker="$host_os ld.so" +sys_lib_dlsearch_path_spec="/lib /usr/lib" +need_lib_prefix=unknown +hardcode_into_libs=no + +# when you set need_version to no, make sure it does not cause -set_version +# flags to be left without arguments +need_version=unknown + +case $host_os in +aix3*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' + shlibpath_var=LIBPATH + + # AIX 3 has no versioning support, so we append a major version to the name. + soname_spec='${libname}${release}${shared_ext}$major' + ;; + +aix[4-9]*) + version_type=linux + need_lib_prefix=no + need_version=no + hardcode_into_libs=yes + if test "$host_cpu" = ia64; then + # AIX 5 supports IA64 + library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + else + # With GCC up to 2.95.x, collect2 would create an import file + # for dependence libraries. The import file would start with + # the line `#! .'. This would cause the generated library to + # depend on `.', always an invalid library. This was fixed in + # development snapshots of GCC prior to 3.0. + case $host_os in + aix4 | aix4.[01] | aix4.[01].*) + if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' + echo ' yes ' + echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then + : + else + can_build_shared=no + fi + ;; + esac + # AIX (on Power*) has no versioning support, so currently we can not hardcode correct + # soname into executable. Probably we can add versioning support to + # collect2, so additional links can be useful in future. + if test "$aix_use_runtimelinking" = yes; then + # If using run time linking (on AIX 4.2 or later) use lib.so + # instead of lib.a to let people know that these are not + # typical AIX shared libraries. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + else + # We preserve .a as extension for shared libraries through AIX4.2 + # and later when we are not doing run time linking. + library_names_spec='${libname}${release}.a $libname.a' + soname_spec='${libname}${release}${shared_ext}$major' + fi + shlibpath_var=LIBPATH + fi + ;; + +amigaos*) + case $host_cpu in + powerpc) + # Since July 2007 AmigaOS4 officially supports .so libraries. + # When compiling the executable, add -use-dynld -Lsobjs: to the compileline. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + ;; + m68k) + library_names_spec='$libname.ixlibrary $libname.a' + # Create ${libname}_ixlibrary.a entries in /sys/libs. + finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' + ;; + esac + ;; + +beos*) + library_names_spec='${libname}${shared_ext}' + dynamic_linker="$host_os ld.so" + shlibpath_var=LIBRARY_PATH + ;; + +bsdi[45]*) + version_type=linux + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" + sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" + # the default ld.so.conf also contains /usr/contrib/lib and + # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow + # libtool to hard-code these into programs + ;; + +cygwin* | mingw* | pw32* | cegcc*) + version_type=windows + shrext_cmds=".dll" + need_version=no + need_lib_prefix=no + + case $GCC,$host_os in + yes,cygwin* | yes,mingw* | yes,pw32* | yes,cegcc*) + library_names_spec='$libname.dll.a' + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname~ + chmod a+x \$dldir/$dlname~ + if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then + eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; + fi' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + + case $host_os in + cygwin*) + # Cygwin DLLs use 'cyg' prefix rather than 'lib' + soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + + sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api" + ;; + mingw* | cegcc*) + # MinGW DLLs use traditional 'lib' prefix + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + pw32*) + # pw32 DLLs use 'pw' prefix rather than 'lib' + library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + esac + ;; + + *) + library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib' + ;; + esac + dynamic_linker='Win32 ld.exe' + # FIXME: first we should search . and the directory the executable is in + shlibpath_var=PATH + ;; + +darwin* | rhapsody*) + dynamic_linker="$host_os dyld" + version_type=darwin + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' + soname_spec='${libname}${release}${major}$shared_ext' + shlibpath_overrides_runpath=yes + shlibpath_var=DYLD_LIBRARY_PATH + shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' + + sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib" + sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' + ;; + +dgux*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +freebsd* | dragonfly*) + # DragonFly does not have aout. When/if they implement a new + # versioning mechanism, adjust this. + if test -x /usr/bin/objformat; then + objformat=`/usr/bin/objformat` + else + case $host_os in + freebsd[123]*) objformat=aout ;; + *) objformat=elf ;; + esac + fi + version_type=freebsd-$objformat + case $version_type in + freebsd-elf*) + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + need_version=no + need_lib_prefix=no + ;; + freebsd-*) + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' + need_version=yes + ;; + esac + shlibpath_var=LD_LIBRARY_PATH + case $host_os in + freebsd2*) + shlibpath_overrides_runpath=yes + ;; + freebsd3.[01]* | freebsdelf3.[01]*) + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ + freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + *) # from 4.6 on, and DragonFly + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + esac + ;; + +gnu*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + hardcode_into_libs=yes + ;; + +haiku*) + version_type=linux + need_lib_prefix=no + need_version=no + dynamic_linker="$host_os runtime_loader" + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LIBRARY_PATH + shlibpath_overrides_runpath=yes + sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/beos/system/lib' + hardcode_into_libs=yes + ;; + +hpux9* | hpux10* | hpux11*) + # Give a soname corresponding to the major version so that dld.sl refuses to + # link against other versions. + version_type=sunos + need_lib_prefix=no + need_version=no + case $host_cpu in + ia64*) + shrext_cmds='.so' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.so" + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + if test "X$HPUX_IA64_MODE" = X32; then + sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" + else + sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" + fi + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + hppa*64*) + shrext_cmds='.sl' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.sl" + shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + *) + shrext_cmds='.sl' + dynamic_linker="$host_os dld.sl" + shlibpath_var=SHLIB_PATH + shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + ;; + esac + # HP-UX runs *really* slowly unless shared libraries are mode 555, ... + postinstall_cmds='chmod 555 $lib' + # or fails outright, so override atomically: + install_override_mode=555 + ;; + +interix[3-9]*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +irix5* | irix6* | nonstopux*) + case $host_os in + nonstopux*) version_type=nonstopux ;; + *) + if test "$lt_cv_prog_gnu_ld" = yes; then + version_type=linux + else + version_type=irix + fi ;; + esac + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' + case $host_os in + irix5* | nonstopux*) + libsuff= shlibsuff= + ;; + *) + case $LD in # libtool.m4 will add one of these switches to LD + *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") + libsuff= shlibsuff= libmagic=32-bit;; + *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") + libsuff=32 shlibsuff=N32 libmagic=N32;; + *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") + libsuff=64 shlibsuff=64 libmagic=64-bit;; + *) libsuff= shlibsuff= libmagic=never-match;; + esac + ;; + esac + shlibpath_var=LD_LIBRARY${shlibsuff}_PATH + shlibpath_overrides_runpath=no + sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" + sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" + hardcode_into_libs=yes + ;; + +# No shared lib support for Linux oldld, aout, or coff. +linux*oldld* | linux*aout* | linux*coff*) + dynamic_linker=no + ;; + +# This must be Linux ELF. +linux* | k*bsd*-gnu | kopensolaris*-gnu) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + + # Some binutils ld are patched to set DT_RUNPATH + if test "${lt_cv_shlibpath_overrides_runpath+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + lt_cv_shlibpath_overrides_runpath=no + save_LDFLAGS=$LDFLAGS + save_libdir=$libdir + eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \ + LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\"" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + if ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null; then : + lt_cv_shlibpath_overrides_runpath=yes +fi +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$save_LDFLAGS + libdir=$save_libdir + +fi + + shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath + + # This implies no fast_install, which is unacceptable. + # Some rework will be needed to allow for fast_install + # before this can be enabled. + hardcode_into_libs=yes + + # Append ld.so.conf contents to the search path + if test -f /etc/ld.so.conf; then + lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '` + sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" + fi + + # We used to test for /lib/ld.so.1 and disable shared libraries on + # powerpc, because MkLinux only supported shared libraries with the + # GNU dynamic linker. Since this was broken with cross compilers, + # most powerpc-linux boxes support dynamic linking these days and + # people can always --disable-shared, the test was removed, and we + # assume the GNU/Linux dynamic linker is in use. + dynamic_linker='GNU/Linux ld.so' + ;; + +netbsd*) + version_type=sunos + need_lib_prefix=no + need_version=no + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + dynamic_linker='NetBSD (a.out) ld.so' + else + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='NetBSD ld.elf_so' + fi + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + +newsos6) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + ;; + +*nto* | *qnx*) + version_type=qnx + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + dynamic_linker='ldqnx.so' + ;; + +openbsd*) + version_type=sunos + sys_lib_dlsearch_path_spec="/usr/lib" + need_lib_prefix=no + # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. + case $host_os in + openbsd3.3 | openbsd3.3.*) need_version=yes ;; + *) need_version=no ;; + esac + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + shlibpath_var=LD_LIBRARY_PATH + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + case $host_os in + openbsd2.[89] | openbsd2.[89].*) + shlibpath_overrides_runpath=no + ;; + *) + shlibpath_overrides_runpath=yes + ;; + esac + else + shlibpath_overrides_runpath=yes + fi + ;; + +os2*) + libname_spec='$name' + shrext_cmds=".dll" + need_lib_prefix=no + library_names_spec='$libname${shared_ext} $libname.a' + dynamic_linker='OS/2 ld.exe' + shlibpath_var=LIBPATH + ;; + +osf3* | osf4* | osf5*) + version_type=osf + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" + sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" + ;; + +rdos*) + dynamic_linker=no + ;; + +solaris*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + # ldd complains unless libraries are executable + postinstall_cmds='chmod +x $lib' + ;; + +sunos4*) + version_type=sunos + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + if test "$with_gnu_ld" = yes; then + need_lib_prefix=no + fi + need_version=yes + ;; + +sysv4 | sysv4.3*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + case $host_vendor in + sni) + shlibpath_overrides_runpath=no + need_lib_prefix=no + runpath_var=LD_RUN_PATH + ;; + siemens) + need_lib_prefix=no + ;; + motorola) + need_lib_prefix=no + need_version=no + shlibpath_overrides_runpath=no + sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' + ;; + esac + ;; + +sysv4*MP*) + if test -d /usr/nec ;then + version_type=linux + library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' + soname_spec='$libname${shared_ext}.$major' + shlibpath_var=LD_LIBRARY_PATH + fi + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + version_type=freebsd-elf + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + if test "$with_gnu_ld" = yes; then + sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' + else + sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' + case $host_os in + sco3.2v5*) + sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" + ;; + esac + fi + sys_lib_dlsearch_path_spec='/usr/lib' + ;; + +tpf*) + # TPF is a cross-target only. Preferred cross-host = GNU/Linux. + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +uts4*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +*) + dynamic_linker=no + ;; +esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5 +$as_echo "$dynamic_linker" >&6; } +test "$dynamic_linker" = no && can_build_shared=no + +variables_saved_for_relink="PATH $shlibpath_var $runpath_var" +if test "$GCC" = yes; then + variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" +fi + +if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then + sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec" +fi +if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then + sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec" +fi + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5 +$as_echo_n "checking how to hardcode library paths into programs... " >&6; } +hardcode_action= +if test -n "$hardcode_libdir_flag_spec" || + test -n "$runpath_var" || + test "X$hardcode_automatic" = "Xyes" ; then + + # We can hardcode non-existent directories. + if test "$hardcode_direct" != no && + # If the only mechanism to avoid hardcoding is shlibpath_var, we + # have to relink, otherwise we might link with an installed library + # when we should be linking with a yet-to-be-installed one + ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no && + test "$hardcode_minus_L" != no; then + # Linking always hardcodes the temporary library directory. + hardcode_action=relink + else + # We can link without hardcoding, and we can hardcode nonexisting dirs. + hardcode_action=immediate + fi +else + # We cannot hardcode anything, or else we can only hardcode existing + # directories. + hardcode_action=unsupported +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action" >&5 +$as_echo "$hardcode_action" >&6; } + +if test "$hardcode_action" = relink || + test "$inherit_rpath" = yes; then + # Fast installation is not supported + enable_fast_install=no +elif test "$shlibpath_overrides_runpath" = yes || + test "$enable_shared" = no; then + # Fast installation is not necessary + enable_fast_install=needless +fi + + + + + + + if test "x$enable_dlopen" != xyes; then + enable_dlopen=unknown + enable_dlopen_self=unknown + enable_dlopen_self_static=unknown +else + lt_cv_dlopen=no + lt_cv_dlopen_libs= + + case $host_os in + beos*) + lt_cv_dlopen="load_add_on" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes + ;; + + mingw* | pw32* | cegcc*) + lt_cv_dlopen="LoadLibrary" + lt_cv_dlopen_libs= + ;; + + cygwin*) + lt_cv_dlopen="dlopen" + lt_cv_dlopen_libs= + ;; + + darwin*) + # if libdl is installed we need to link against it + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +$as_echo_n "checking for dlopen in -ldl... " >&6; } +if test "${ac_cv_lib_dl_dlopen+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dl_dlopen=yes +else + ac_cv_lib_dl_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +$as_echo "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = x""yes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" +else + + lt_cv_dlopen="dyld" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes + +fi + + ;; + + *) + ac_fn_c_check_func "$LINENO" "shl_load" "ac_cv_func_shl_load" +if test "x$ac_cv_func_shl_load" = x""yes; then : + lt_cv_dlopen="shl_load" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shl_load in -ldld" >&5 +$as_echo_n "checking for shl_load in -ldld... " >&6; } +if test "${ac_cv_lib_dld_shl_load+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char shl_load (); +int +main () +{ +return shl_load (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dld_shl_load=yes +else + ac_cv_lib_dld_shl_load=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_shl_load" >&5 +$as_echo "$ac_cv_lib_dld_shl_load" >&6; } +if test "x$ac_cv_lib_dld_shl_load" = x""yes; then : + lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld" +else + ac_fn_c_check_func "$LINENO" "dlopen" "ac_cv_func_dlopen" +if test "x$ac_cv_func_dlopen" = x""yes; then : + lt_cv_dlopen="dlopen" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +$as_echo_n "checking for dlopen in -ldl... " >&6; } +if test "${ac_cv_lib_dl_dlopen+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dl_dlopen=yes +else + ac_cv_lib_dl_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +$as_echo "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = x""yes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -lsvld" >&5 +$as_echo_n "checking for dlopen in -lsvld... " >&6; } +if test "${ac_cv_lib_svld_dlopen+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsvld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_svld_dlopen=yes +else + ac_cv_lib_svld_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_svld_dlopen" >&5 +$as_echo "$ac_cv_lib_svld_dlopen" >&6; } +if test "x$ac_cv_lib_svld_dlopen" = x""yes; then : + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dld_link in -ldld" >&5 +$as_echo_n "checking for dld_link in -ldld... " >&6; } +if test "${ac_cv_lib_dld_dld_link+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dld_link (); +int +main () +{ +return dld_link (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dld_dld_link=yes +else + ac_cv_lib_dld_dld_link=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_dld_link" >&5 +$as_echo "$ac_cv_lib_dld_dld_link" >&6; } +if test "x$ac_cv_lib_dld_dld_link" = x""yes; then : + lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld" +fi + + +fi + + +fi + + +fi + + +fi + + +fi + + ;; + esac + + if test "x$lt_cv_dlopen" != xno; then + enable_dlopen=yes + else + enable_dlopen=no + fi + + case $lt_cv_dlopen in + dlopen) + save_CPPFLAGS="$CPPFLAGS" + test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H" + + save_LDFLAGS="$LDFLAGS" + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\" + + save_LIBS="$LIBS" + LIBS="$lt_cv_dlopen_libs $LIBS" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a program can dlopen itself" >&5 +$as_echo_n "checking whether a program can dlopen itself... " >&6; } +if test "${lt_cv_dlopen_self+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line 11137 "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H +#include +#endif + +#include + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +/* When -fvisbility=hidden is used, assume the code has been annotated + correspondingly for the symbols needed. */ +#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) +void fnord () __attribute__((visibility("default"))); +#endif + +void fnord () { int i=42; } +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else + { + if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + else puts (dlerror ()); + } + /* dlclose (self); */ + } + else + puts (dlerror ()); + + return status; +} +_LT_EOF + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self=no + fi +fi +rm -fr conftest* + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self" >&5 +$as_echo "$lt_cv_dlopen_self" >&6; } + + if test "x$lt_cv_dlopen_self" = xyes; then + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a statically linked program can dlopen itself" >&5 +$as_echo_n "checking whether a statically linked program can dlopen itself... " >&6; } +if test "${lt_cv_dlopen_self_static+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self_static=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line 11243 "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H +#include +#endif + +#include + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +/* When -fvisbility=hidden is used, assume the code has been annotated + correspondingly for the symbols needed. */ +#if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) +void fnord () __attribute__((visibility("default"))); +#endif + +void fnord () { int i=42; } +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else + { + if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + else puts (dlerror ()); + } + /* dlclose (self); */ + } + else + puts (dlerror ()); + + return status; +} +_LT_EOF + if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 + (eval $ac_link) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self_static=no + fi +fi +rm -fr conftest* + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self_static" >&5 +$as_echo "$lt_cv_dlopen_self_static" >&6; } + fi + + CPPFLAGS="$save_CPPFLAGS" + LDFLAGS="$save_LDFLAGS" + LIBS="$save_LIBS" + ;; + esac + + case $lt_cv_dlopen_self in + yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;; + *) enable_dlopen_self=unknown ;; + esac + + case $lt_cv_dlopen_self_static in + yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;; + *) enable_dlopen_self_static=unknown ;; + esac +fi + + + + + + + + + + + + + + + + + +striplib= +old_striplib= +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether stripping libraries is possible" >&5 +$as_echo_n "checking whether stripping libraries is possible... " >&6; } +if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then + test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" + test -z "$striplib" && striplib="$STRIP --strip-unneeded" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else +# FIXME - insert some real tests, host_os isn't really good enough + case $host_os in + darwin*) + if test -n "$STRIP" ; then + striplib="$STRIP -x" + old_striplib="$STRIP -S" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + fi + ;; + *) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + ;; + esac +fi + + + + + + + + + + + + + # Report which library types will actually be built + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if libtool supports shared libraries" >&5 +$as_echo_n "checking if libtool supports shared libraries... " >&6; } + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $can_build_shared" >&5 +$as_echo "$can_build_shared" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build shared libraries" >&5 +$as_echo_n "checking whether to build shared libraries... " >&6; } + test "$can_build_shared" = "no" && enable_shared=no + + # On AIX, shared libraries and static libraries use the same namespace, and + # are all built from PIC. + case $host_os in + aix3*) + test "$enable_shared" = yes && enable_static=no + if test -n "$RANLIB"; then + archive_cmds="$archive_cmds~\$RANLIB \$lib" + postinstall_cmds='$RANLIB $lib' + fi + ;; + + aix[4-9]*) + if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then + test "$enable_shared" = yes && enable_static=no + fi + ;; + esac + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_shared" >&5 +$as_echo "$enable_shared" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build static libraries" >&5 +$as_echo_n "checking whether to build static libraries... " >&6; } + # Make sure either enable_shared or enable_static is yes. + test "$enable_shared" = yes || enable_static=yes + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_static" >&5 +$as_echo "$enable_static" >&6; } + + + + +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +CC="$lt_save_CC" + + + + + + + + + + + + + + ac_config_commands="$ac_config_commands libtool" + + + + +# Only expand once: + + + +# Check whether --enable-targets was given. +if test "${enable_targets+set}" = set; then : + enableval=$enable_targets; case "${enableval}" in + yes | "") as_fn_error "enable-targets option must specify target names or 'all'" "$LINENO" 5 + ;; + no) enable_targets= ;; + *) enable_targets=$enableval ;; +esac +fi + + +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +__GNUC__ +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "^[0-3]$" >/dev/null 2>&1; then : + +else + GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Wshadow" +fi +rm -f conftest* + + +# Check whether --enable-werror was given. +if test "${enable_werror+set}" = set; then : + enableval=$enable_werror; case "${enableval}" in + yes | y) ERROR_ON_WARNING="yes" ;; + no | n) ERROR_ON_WARNING="no" ;; + *) as_fn_error "bad value ${enableval} for --enable-werror" "$LINENO" 5 ;; + esac +fi + + +# Disable -Wformat by default when using gcc on mingw +case "${host}" in + *-*-mingw32*) + if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then + GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Wno-format" + fi + ;; + *) ;; +esac + +# Enable -Werror by default when using gcc +if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then + ERROR_ON_WARNING=yes +fi + +NO_WERROR= +if test "${ERROR_ON_WARNING}" = yes ; then + GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Werror" + NO_WERROR="-Wno-error" +fi + +if test "${GCC}" = yes ; then + WARN_CFLAGS="${GCC_WARN_CFLAGS}" +fi + +# Check whether --enable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then : + enableval=$enable_build_warnings; case "${enableval}" in + yes) WARN_CFLAGS="${GCC_WARN_CFLAGS}";; + no) if test "${GCC}" = yes ; then + WARN_CFLAGS="-w" + fi;; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}";; + *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +fi + + +if test x"$silent" != x"yes" && test x"$WARN_CFLAGS" != x""; then + echo "Setting warning flags = $WARN_CFLAGS" 6>&1 +fi + + + + + +ac_config_headers="$ac_config_headers config.h:config.in" + + +if test -z "$target" ; then + as_fn_error "Unrecognized target system type; please check config.sub." "$LINENO" 5 +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5 +$as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } + # Check whether --enable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then : + enableval=$enable_maintainer_mode; USE_MAINTAINER_MODE=$enableval +else + USE_MAINTAINER_MODE=no +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_MAINTAINER_MODE" >&5 +$as_echo "$USE_MAINTAINER_MODE" >&6; } + if test $USE_MAINTAINER_MODE = yes; then + MAINTAINER_MODE_TRUE= + MAINTAINER_MODE_FALSE='#' +else + MAINTAINER_MODE_TRUE='#' + MAINTAINER_MODE_FALSE= +fi + + MAINT=$MAINTAINER_MODE_TRUE + + + case ${build_alias} in + "") build_noncanonical=${build} ;; + *) build_noncanonical=${build_alias} ;; +esac + + case ${host_alias} in + "") host_noncanonical=${build_noncanonical} ;; + *) host_noncanonical=${host_alias} ;; +esac + + case ${target_alias} in + "") target_noncanonical=${host_noncanonical} ;; + *) target_noncanonical=${target_alias} ;; +esac + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to install libbfd" >&5 +$as_echo_n "checking whether to install libbfd... " >&6; } + # Check whether --enable-install-libbfd was given. +if test "${enable_install_libbfd+set}" = set; then : + enableval=$enable_install_libbfd; install_libbfd_p=$enableval +else + if test "${host}" = "${target}" || test "$enable_shared" = "yes"; then + install_libbfd_p=yes + else + install_libbfd_p=no + fi +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $install_libbfd_p" >&5 +$as_echo "$install_libbfd_p" >&6; } + if test $install_libbfd_p = yes; then + INSTALL_LIBBFD_TRUE= + INSTALL_LIBBFD_FALSE='#' +else + INSTALL_LIBBFD_TRUE='#' + INSTALL_LIBBFD_FALSE= +fi + + # Need _noncanonical variables for this. + + + + + # libbfd.a is a host library containing target dependent code + bfdlibdir='$(libdir)' + bfdincludedir='$(includedir)' + if test "${host}" != "${target}"; then + bfdlibdir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/lib' + bfdincludedir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/include' + fi + + + + + + + + +# host-specific stuff: + +ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl fi vi ga zh_CN" +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../intl/config.intl; then + . ../intl/config.intl +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } +if test x"$USE_NLS" != xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define ENABLE_NLS 1" >>confdefs.h + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5 +$as_echo_n "checking for catalogs to be installed... " >&6; } + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5 +$as_echo "$LINGUAS" >&6; } + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + + MKINSTALLDIRS= + if test -n "$ac_aux_dir"; then + case "$ac_aux_dir" in + /*) MKINSTALLDIRS="$ac_aux_dir/mkinstalldirs" ;; + *) MKINSTALLDIRS="\$(top_builddir)/$ac_aux_dir/mkinstalldirs" ;; + esac + fi + if test -z "$MKINSTALLDIRS"; then + MKINSTALLDIRS="\$(top_srcdir)/mkinstalldirs" + fi + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } + # Check whether --enable-nls was given. +if test "${enable_nls+set}" = set; then : + enableval=$enable_nls; USE_NLS=$enableval +else + USE_NLS=yes +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_NLS" >&5 +$as_echo "$USE_NLS" >&6; } + + + + + + +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_MSGFMT+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case "$MSGFMT" in + [\\/]* | ?:[\\/]*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --statistics /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + ac_cv_path_MSGFMT="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT=":" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test "$MSGFMT" != ":"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MSGFMT" >&5 +$as_echo "$MSGFMT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_GMSGFMT+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $GMSGFMT in + [\\/]* | ?:[\\/]*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT=$ac_cv_path_GMSGFMT +if test -n "$GMSGFMT"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $GMSGFMT" >&5 +$as_echo "$GMSGFMT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + + +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_XGETTEXT+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case "$XGETTEXT" in + [\\/]* | ?:[\\/]*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test "$XGETTEXT" != ":"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $XGETTEXT" >&5 +$as_echo "$XGETTEXT" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + rm -f messages.po + + +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "msgmerge", so it can be a program name with args. +set dummy msgmerge; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_MSGMERGE+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case "$MSGMERGE" in + [\\/]* | ?:[\\/]*) + ac_cv_path_MSGMERGE="$MSGMERGE" # Let the user override the test with a path. + ;; + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --update -q /dev/null /dev/null >/dev/null 2>&1; then + ac_cv_path_MSGMERGE="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" + test -z "$ac_cv_path_MSGMERGE" && ac_cv_path_MSGMERGE=":" + ;; +esac +fi +MSGMERGE="$ac_cv_path_MSGMERGE" +if test "$MSGMERGE" != ":"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MSGMERGE" >&5 +$as_echo "$MSGMERGE" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + if test "$GMSGFMT" != ":"; then + if $GMSGFMT --statistics /dev/null >/dev/null 2>&1 && + (if $GMSGFMT --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + GMSGFMT=`echo "$GMSGFMT" | sed -e 's,^.*/,,'` + { $as_echo "$as_me:${as_lineno-$LINENO}: result: found $GMSGFMT program is not GNU msgfmt; ignore it" >&5 +$as_echo "found $GMSGFMT program is not GNU msgfmt; ignore it" >&6; } + GMSGFMT=":" + fi + fi + + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: found xgettext program is not GNU xgettext; ignore it" >&5 +$as_echo "found xgettext program is not GNU xgettext; ignore it" >&6; } + XGETTEXT=":" + fi + rm -f messages.po + fi + + ac_config_commands="$ac_config_commands default-1" + + + +. ${srcdir}/../bfd/configure.host + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test -z "$CC_FOR_BUILD"; then + if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' + else + CC_FOR_BUILD=gcc + fi +fi + +# Also set EXEEXT_FOR_BUILD. +if test "x$cross_compiling" = "xno"; then + EXEEXT_FOR_BUILD='$(EXEEXT)' +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for build system executable suffix" >&5 +$as_echo_n "checking for build system executable suffix... " >&6; } +if test "${bfd_cv_build_exeext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.c + bfd_cv_build_exeext= + ${CC_FOR_BUILD} -o conftest conftest.c 1>&5 2>&5 + for file in conftest.*; do + case $file in + *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *) bfd_cv_build_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + rm -f conftest* + test x"${bfd_cv_build_exeext}" = x && bfd_cv_build_exeext=no +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bfd_cv_build_exeext" >&5 +$as_echo "$bfd_cv_build_exeext" >&6; } + EXEEXT_FOR_BUILD="" + test x"${bfd_cv_build_exeext}" != xno && EXEEXT_FOR_BUILD=${bfd_cv_build_exeext} +fi + + + + + +for ac_header in string.h strings.h stdlib.h limits.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +ac_fn_c_check_decl "$LINENO" "basename" "ac_cv_have_decl_basename" "$ac_includes_default" +if test "x$ac_cv_have_decl_basename" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_BASENAME $ac_have_decl +_ACEOF +ac_fn_c_check_decl "$LINENO" "stpcpy" "ac_cv_have_decl_stpcpy" "$ac_includes_default" +if test "x$ac_cv_have_decl_stpcpy" = x""yes; then : + ac_have_decl=1 +else + ac_have_decl=0 +fi + +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_STPCPY $ac_have_decl +_ACEOF + + +cgen_maint=no +cgendir='$(srcdir)/../cgen' + +# Check whether --enable-cgen-maint was given. +if test "${enable_cgen_maint+set}" = set; then : + enableval=$enable_cgen_maint; case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgen_maint=yes + cgendir=${cgen_maint}/lib/cgen + ;; +esac +fi + if test x${cgen_maint} = xyes; then + CGEN_MAINT_TRUE= + CGEN_MAINT_FALSE='#' +else + CGEN_MAINT_TRUE='#' + CGEN_MAINT_FALSE= +fi + + + +using_cgen=no + +# Check if linker supports --as-needed and --no-as-needed options +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking linker --as-needed support" >&5 +$as_echo_n "checking linker --as-needed support... " >&6; } +if test "${bfd_cv_ld_as_needed+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + bfd_cv_ld_as_needed=no + if $LD --help 2>/dev/null | grep as-needed > /dev/null; then + bfd_cv_ld_as_needed=yes + fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bfd_cv_ld_as_needed" >&5 +$as_echo "$bfd_cv_ld_as_needed" >&6; } + +LIBM= +case $host in +*-*-beos* | *-*-cegcc* | *-*-cygwin* | *-*-haiku* | *-*-pw32* | *-*-darwin*) + # These system don't have libm, or don't need it + ;; +*-ncr-sysv4.3*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _mwvalidcheckl in -lmw" >&5 +$as_echo_n "checking for _mwvalidcheckl in -lmw... " >&6; } +if test "${ac_cv_lib_mw__mwvalidcheckl+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lmw $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char _mwvalidcheckl (); +int +main () +{ +return _mwvalidcheckl (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_mw__mwvalidcheckl=yes +else + ac_cv_lib_mw__mwvalidcheckl=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_mw__mwvalidcheckl" >&5 +$as_echo "$ac_cv_lib_mw__mwvalidcheckl" >&6; } +if test "x$ac_cv_lib_mw__mwvalidcheckl" = x""yes; then : + LIBM="-lmw" +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for cos in -lm" >&5 +$as_echo_n "checking for cos in -lm... " >&6; } +if test "${ac_cv_lib_m_cos+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lm $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char cos (); +int +main () +{ +return cos (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_m_cos=yes +else + ac_cv_lib_m_cos=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_m_cos" >&5 +$as_echo "$ac_cv_lib_m_cos" >&6; } +if test "x$ac_cv_lib_m_cos" = x""yes; then : + LIBM="$LIBM -lm" +fi + + ;; +*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for cos in -lm" >&5 +$as_echo_n "checking for cos in -lm... " >&6; } +if test "${ac_cv_lib_m_cos+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lm $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char cos (); +int +main () +{ +return cos (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_m_cos=yes +else + ac_cv_lib_m_cos=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_m_cos" >&5 +$as_echo "$ac_cv_lib_m_cos" >&6; } +if test "x$ac_cv_lib_m_cos" = x""yes; then : + LIBM="-lm" +fi + + ;; +esac + + + +#Libs for generator progs +if test "x$cross_compiling" = "xno"; then + BUILD_LIBS=../libiberty/libiberty.a + BUILD_LIB_DEPS=$BUILD_LIBS +else + # if cross-compiling, assume that the system provides -liberty + # and that the version is compatible with new headers. + BUILD_LIBS=-liberty + BUILD_LIB_DEPS= +fi +BUILD_LIBS="$BUILD_LIBS $LIBINTL" +BUILD_LIB_DEPS="$BUILD_LIB_DEPS $LIBINTL_DEP" + + + + +# Horrible hacks to build DLLs on Windows and a shared library elsewhere. +SHARED_LDFLAGS= +SHARED_LIBADD= +SHARED_DEPENDENCIES= +if test "$enable_shared" = "yes"; then +# When building a shared libopcodes, link against the pic version of libiberty +# so that apps that use libopcodes won't need libiberty just to satisfy any +# libopcodes references. +# We can't do that if a pic libiberty is unavailable since including non-pic +# code would insert text relocations into libopcodes. +# Note that linking against libbfd as we do here, which is itself linked +# against libiberty, may not satisfy all the libopcodes libiberty references +# since libbfd may not pull in the entirety of libiberty. + x=`sed -n -e 's/^[ ]*PICFLAG[ ]*=[ ]*//p' < ../libiberty/Makefile | sed -n '$p'` + if test -n "$x"; then + SHARED_LIBADD="-L`pwd`/../libiberty/pic -liberty" + fi + + case "${host}" in + *-*-cygwin*) + SHARED_LDFLAGS="-no-undefined" + SHARED_LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" + ;; + *-*-darwin*) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.dylib ${SHARED_LIBADD}" + SHARED_DEPENDENCIES="../bfd/libbfd.la" + ;; + *) + case "$host_vendor" in + hp) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.sl ${SHARED_LIBADD}" + ;; + *) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.so ${SHARED_LIBADD}" + ;; + esac + SHARED_DEPENDENCIES="../bfd/libbfd.la" + ;; + esac + + if test -n "$SHARED_LIBADD"; then + if test -n "$LIBM"; then + if test x"$bfd_cv_ld_as_needed" = xyes; then + # Link against libm only when needed. Put -lc, -lm inside -Wl + # to stop libtool reordering these options. + SHARED_LIBADD="$SHARED_LIBADD -Wl,-lc,--as-needed,`echo $LIBM | sed 's/ /,/g'`,--no-as-needed" + else + SHARED_LIBADD="$SHARED_LIBADD $LIBM" + fi + fi + fi +fi + + + + +# target-specific stuff: + +# Canonicalize the secondary target names. +if test -n "$enable_targets" ; then + for targ in `echo $enable_targets | sed 's/,/ /g'` + do + result=`$ac_config_sub $targ 2>/dev/null` + if test -n "$result" ; then + canon_targets="$canon_targets $result" + else + # Allow targets that config.sub doesn't recognize, like "all". + canon_targets="$canon_targets $targ" + fi + done +fi + +all_targets=false +selarchs= +for targ in $target $canon_targets +do + if test "x$targ" = "xall" ; then + all_targets=true + else + . $srcdir/../bfd/config.bfd + selarchs="$selarchs $targ_archs" + fi +done + +# Utility var, documents generic cgen support files. + +cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo cgen-bitset.lo" + +# We don't do any links based on the target system, just makefile config. + +if test x${all_targets} = xfalse ; then + + # Target architecture .o files. + ta= + + for arch in $selarchs + do + ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` + archdefs="$archdefs -DARCH_$ad" + case "$arch" in + bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; + bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arm_arch) ta="$ta arm-dis.lo" ;; + bfd_avr_arch) ta="$ta avr-dis.lo" ;; + bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; + bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; + bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; + bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; + bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; + bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; + bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; + bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; + bfd_moxie_arch) ta="$ta moxie-dis.lo moxie-opc.lo" ;; + bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; + bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; + bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; + bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; + bfd_i386_arch|bfd_l1om_arch) + ta="$ta i386-dis.lo i386-opc.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; + bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; + bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;; + bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; + bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; + bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; + bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; + bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;; + bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; + bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; + bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; + bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; + bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; + bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; + bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_pyramid_arch) ;; + bfd_romp_arch) ;; + bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; + bfd_sh_arch) + # We can't decide what we want just from the CPU family. + # We want SH5 support unless a specific version of sh is + # specified, as in sh3-elf, sh3b-linux-gnu, etc. + # Include it just for ELF targets, since the SH5 bfd:s are ELF only. + for t in $target $canon_targets; do + case $t in + all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ + sh-*-linux* | shl-*-linux*) + ta="$ta sh64-dis.lo sh64-opc.lo" + archdefs="$archdefs -DINCLUDE_SHMEDIA" + break;; + esac; + done + ta="$ta sh-dis.lo cgen-bitset.lo" ;; + bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_spu_arch) ta="$ta spu-dis.lo spu-opc.lo" ;; + bfd_tahoe_arch) ;; + bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; + bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; + bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;; + bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; + bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_vax_arch) ta="$ta vax-dis.lo" ;; + bfd_w65_arch) ta="$ta w65-dis.lo" ;; + bfd_we32k_arch) ;; + bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; + bfd_z80_arch) ta="$ta z80-dis.lo" ;; + bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + + "") ;; + *) as_fn_error "*** unknown target architecture $arch" "$LINENO" 5 ;; + esac + done + + if test $using_cgen = yes ; then + ta="$ta $cgen_files" + fi + + # Weed out duplicate .o files. + f="" + for i in $ta ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + ta="$f" + + # And duplicate -D flags. + f="" + for i in $archdefs ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + archdefs="$f" + + BFD_MACHINES="$ta" + +else # all_targets is true + archdefs=-DARCH_all + BFD_MACHINES='$(ALL_MACHINES)' +fi + + + + +ac_config_files="$ac_config_files Makefile po/Makefile.in:po/Make-in" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + +if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then + as_fn_error "conditional \"AMDEP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then + as_fn_error "conditional \"am__fastdepCC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi + if test -n "$EXEEXT"; then + am__EXEEXT_TRUE= + am__EXEEXT_FALSE='#' +else + am__EXEEXT_TRUE='#' + am__EXEEXT_FALSE= +fi + +if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then + as_fn_error "conditional \"MAINTAINER_MODE\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${INSTALL_LIBBFD_TRUE}" && test -z "${INSTALL_LIBBFD_FALSE}"; then + as_fn_error "conditional \"INSTALL_LIBBFD\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${CGEN_MAINT_TRUE}" && test -z "${CGEN_MAINT_FALSE}"; then + as_fn_error "conditional \"CGEN_MAINT\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. 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$SED "$delay_single_quote_subst"`' +EGREP='`$ECHO "$EGREP" | $SED "$delay_single_quote_subst"`' +FGREP='`$ECHO "$FGREP" | $SED "$delay_single_quote_subst"`' +LD='`$ECHO "$LD" | $SED "$delay_single_quote_subst"`' +NM='`$ECHO "$NM" | $SED "$delay_single_quote_subst"`' +LN_S='`$ECHO "$LN_S" | $SED "$delay_single_quote_subst"`' +max_cmd_len='`$ECHO "$max_cmd_len" | $SED "$delay_single_quote_subst"`' +ac_objext='`$ECHO "$ac_objext" | $SED "$delay_single_quote_subst"`' +exeext='`$ECHO "$exeext" | $SED "$delay_single_quote_subst"`' +lt_unset='`$ECHO "$lt_unset" | $SED "$delay_single_quote_subst"`' +lt_SP2NL='`$ECHO "$lt_SP2NL" | $SED "$delay_single_quote_subst"`' +lt_NL2SP='`$ECHO "$lt_NL2SP" | $SED "$delay_single_quote_subst"`' +reload_flag='`$ECHO "$reload_flag" | $SED "$delay_single_quote_subst"`' +reload_cmds='`$ECHO "$reload_cmds" | $SED "$delay_single_quote_subst"`' +OBJDUMP='`$ECHO "$OBJDUMP" | $SED "$delay_single_quote_subst"`' +deplibs_check_method='`$ECHO "$deplibs_check_method" | $SED "$delay_single_quote_subst"`' +file_magic_cmd='`$ECHO "$file_magic_cmd" | $SED "$delay_single_quote_subst"`' +AR='`$ECHO "$AR" | $SED "$delay_single_quote_subst"`' +AR_FLAGS='`$ECHO "$AR_FLAGS" | $SED "$delay_single_quote_subst"`' +STRIP='`$ECHO "$STRIP" | $SED "$delay_single_quote_subst"`' +RANLIB='`$ECHO "$RANLIB" | $SED "$delay_single_quote_subst"`' +old_postinstall_cmds='`$ECHO "$old_postinstall_cmds" | $SED "$delay_single_quote_subst"`' +old_postuninstall_cmds='`$ECHO "$old_postuninstall_cmds" | $SED "$delay_single_quote_subst"`' +old_archive_cmds='`$ECHO "$old_archive_cmds" | $SED "$delay_single_quote_subst"`' +lock_old_archive_extraction='`$ECHO "$lock_old_archive_extraction" | $SED "$delay_single_quote_subst"`' +CC='`$ECHO "$CC" | $SED "$delay_single_quote_subst"`' +CFLAGS='`$ECHO "$CFLAGS" | $SED "$delay_single_quote_subst"`' +compiler='`$ECHO "$compiler" | $SED "$delay_single_quote_subst"`' +GCC='`$ECHO "$GCC" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_pipe='`$ECHO "$lt_cv_sys_global_symbol_pipe" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_cdecl='`$ECHO "$lt_cv_sys_global_symbol_to_cdecl" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address" | $SED "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address_lib_prefix" | $SED "$delay_single_quote_subst"`' +objdir='`$ECHO "$objdir" | $SED "$delay_single_quote_subst"`' +MAGIC_CMD='`$ECHO "$MAGIC_CMD" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_no_builtin_flag='`$ECHO "$lt_prog_compiler_no_builtin_flag" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_wl='`$ECHO "$lt_prog_compiler_wl" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_pic='`$ECHO "$lt_prog_compiler_pic" | $SED "$delay_single_quote_subst"`' +lt_prog_compiler_static='`$ECHO "$lt_prog_compiler_static" | $SED "$delay_single_quote_subst"`' +lt_cv_prog_compiler_c_o='`$ECHO "$lt_cv_prog_compiler_c_o" | $SED "$delay_single_quote_subst"`' +need_locks='`$ECHO "$need_locks" | $SED "$delay_single_quote_subst"`' +DSYMUTIL='`$ECHO "$DSYMUTIL" | $SED "$delay_single_quote_subst"`' +NMEDIT='`$ECHO "$NMEDIT" | $SED "$delay_single_quote_subst"`' +LIPO='`$ECHO "$LIPO" | $SED "$delay_single_quote_subst"`' +OTOOL='`$ECHO "$OTOOL" | $SED "$delay_single_quote_subst"`' +OTOOL64='`$ECHO "$OTOOL64" | $SED "$delay_single_quote_subst"`' +libext='`$ECHO "$libext" | $SED "$delay_single_quote_subst"`' +shrext_cmds='`$ECHO "$shrext_cmds" | $SED "$delay_single_quote_subst"`' +extract_expsyms_cmds='`$ECHO "$extract_expsyms_cmds" | $SED "$delay_single_quote_subst"`' +archive_cmds_need_lc='`$ECHO "$archive_cmds_need_lc" | $SED "$delay_single_quote_subst"`' +enable_shared_with_static_runtimes='`$ECHO "$enable_shared_with_static_runtimes" | $SED "$delay_single_quote_subst"`' +export_dynamic_flag_spec='`$ECHO "$export_dynamic_flag_spec" | $SED "$delay_single_quote_subst"`' +whole_archive_flag_spec='`$ECHO "$whole_archive_flag_spec" | $SED "$delay_single_quote_subst"`' +compiler_needs_object='`$ECHO "$compiler_needs_object" | $SED "$delay_single_quote_subst"`' +old_archive_from_new_cmds='`$ECHO "$old_archive_from_new_cmds" | $SED "$delay_single_quote_subst"`' +old_archive_from_expsyms_cmds='`$ECHO "$old_archive_from_expsyms_cmds" | $SED "$delay_single_quote_subst"`' +archive_cmds='`$ECHO "$archive_cmds" | $SED "$delay_single_quote_subst"`' +archive_expsym_cmds='`$ECHO "$archive_expsym_cmds" | $SED "$delay_single_quote_subst"`' +module_cmds='`$ECHO "$module_cmds" | $SED "$delay_single_quote_subst"`' +module_expsym_cmds='`$ECHO "$module_expsym_cmds" | $SED "$delay_single_quote_subst"`' +with_gnu_ld='`$ECHO "$with_gnu_ld" | $SED "$delay_single_quote_subst"`' +allow_undefined_flag='`$ECHO "$allow_undefined_flag" | $SED "$delay_single_quote_subst"`' +no_undefined_flag='`$ECHO "$no_undefined_flag" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec='`$ECHO "$hardcode_libdir_flag_spec" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec_ld='`$ECHO "$hardcode_libdir_flag_spec_ld" | $SED "$delay_single_quote_subst"`' +hardcode_libdir_separator='`$ECHO "$hardcode_libdir_separator" | $SED "$delay_single_quote_subst"`' +hardcode_direct='`$ECHO "$hardcode_direct" | $SED "$delay_single_quote_subst"`' +hardcode_direct_absolute='`$ECHO "$hardcode_direct_absolute" | $SED "$delay_single_quote_subst"`' +hardcode_minus_L='`$ECHO "$hardcode_minus_L" | $SED "$delay_single_quote_subst"`' +hardcode_shlibpath_var='`$ECHO "$hardcode_shlibpath_var" | $SED "$delay_single_quote_subst"`' +hardcode_automatic='`$ECHO "$hardcode_automatic" | $SED "$delay_single_quote_subst"`' +inherit_rpath='`$ECHO "$inherit_rpath" | $SED "$delay_single_quote_subst"`' +link_all_deplibs='`$ECHO "$link_all_deplibs" | $SED "$delay_single_quote_subst"`' +fix_srcfile_path='`$ECHO "$fix_srcfile_path" | $SED "$delay_single_quote_subst"`' +always_export_symbols='`$ECHO "$always_export_symbols" | $SED "$delay_single_quote_subst"`' +export_symbols_cmds='`$ECHO "$export_symbols_cmds" | $SED "$delay_single_quote_subst"`' +exclude_expsyms='`$ECHO "$exclude_expsyms" | $SED "$delay_single_quote_subst"`' +include_expsyms='`$ECHO "$include_expsyms" | $SED "$delay_single_quote_subst"`' +prelink_cmds='`$ECHO "$prelink_cmds" | $SED "$delay_single_quote_subst"`' +file_list_spec='`$ECHO "$file_list_spec" | $SED "$delay_single_quote_subst"`' +variables_saved_for_relink='`$ECHO "$variables_saved_for_relink" | $SED "$delay_single_quote_subst"`' +need_lib_prefix='`$ECHO "$need_lib_prefix" | $SED "$delay_single_quote_subst"`' +need_version='`$ECHO "$need_version" | $SED "$delay_single_quote_subst"`' +version_type='`$ECHO "$version_type" | $SED "$delay_single_quote_subst"`' +runpath_var='`$ECHO "$runpath_var" | $SED "$delay_single_quote_subst"`' +shlibpath_var='`$ECHO "$shlibpath_var" | $SED "$delay_single_quote_subst"`' +shlibpath_overrides_runpath='`$ECHO "$shlibpath_overrides_runpath" | $SED "$delay_single_quote_subst"`' +libname_spec='`$ECHO "$libname_spec" | $SED "$delay_single_quote_subst"`' +library_names_spec='`$ECHO "$library_names_spec" | $SED "$delay_single_quote_subst"`' +soname_spec='`$ECHO "$soname_spec" | $SED "$delay_single_quote_subst"`' +install_override_mode='`$ECHO "$install_override_mode" | $SED "$delay_single_quote_subst"`' +postinstall_cmds='`$ECHO "$postinstall_cmds" | $SED "$delay_single_quote_subst"`' +postuninstall_cmds='`$ECHO "$postuninstall_cmds" | $SED "$delay_single_quote_subst"`' +finish_cmds='`$ECHO "$finish_cmds" | $SED "$delay_single_quote_subst"`' +finish_eval='`$ECHO "$finish_eval" | $SED "$delay_single_quote_subst"`' +hardcode_into_libs='`$ECHO "$hardcode_into_libs" | $SED "$delay_single_quote_subst"`' +sys_lib_search_path_spec='`$ECHO "$sys_lib_search_path_spec" | $SED "$delay_single_quote_subst"`' +sys_lib_dlsearch_path_spec='`$ECHO "$sys_lib_dlsearch_path_spec" | $SED "$delay_single_quote_subst"`' +hardcode_action='`$ECHO "$hardcode_action" | $SED "$delay_single_quote_subst"`' +enable_dlopen='`$ECHO "$enable_dlopen" | $SED "$delay_single_quote_subst"`' +enable_dlopen_self='`$ECHO "$enable_dlopen_self" | $SED "$delay_single_quote_subst"`' +enable_dlopen_self_static='`$ECHO "$enable_dlopen_self_static" | $SED "$delay_single_quote_subst"`' +old_striplib='`$ECHO "$old_striplib" | $SED "$delay_single_quote_subst"`' +striplib='`$ECHO "$striplib" | $SED "$delay_single_quote_subst"`' + +LTCC='$LTCC' +LTCFLAGS='$LTCFLAGS' +compiler='$compiler_DEFAULT' + +# A function that is used when there is no print builtin or printf. +func_fallback_echo () +{ + eval 'cat <<_LTECHO_EOF +\$1 +_LTECHO_EOF' +} + +# Quote evaled strings. +for var in SHELL \ +ECHO \ +SED \ +GREP \ +EGREP \ +FGREP \ +LD \ +NM \ +LN_S \ +lt_SP2NL \ +lt_NL2SP \ +reload_flag \ +OBJDUMP \ +deplibs_check_method \ +file_magic_cmd \ +AR \ +AR_FLAGS \ +STRIP \ +RANLIB \ +CC \ +CFLAGS \ +compiler \ +lt_cv_sys_global_symbol_pipe \ +lt_cv_sys_global_symbol_to_cdecl \ +lt_cv_sys_global_symbol_to_c_name_address \ +lt_cv_sys_global_symbol_to_c_name_address_lib_prefix \ +lt_prog_compiler_no_builtin_flag \ +lt_prog_compiler_wl \ +lt_prog_compiler_pic \ +lt_prog_compiler_static \ +lt_cv_prog_compiler_c_o \ +need_locks \ +DSYMUTIL \ +NMEDIT \ +LIPO \ +OTOOL \ +OTOOL64 \ +shrext_cmds \ +export_dynamic_flag_spec \ +whole_archive_flag_spec \ +compiler_needs_object \ +with_gnu_ld \ +allow_undefined_flag \ +no_undefined_flag \ +hardcode_libdir_flag_spec \ +hardcode_libdir_flag_spec_ld \ +hardcode_libdir_separator \ +fix_srcfile_path \ +exclude_expsyms \ +include_expsyms \ +file_list_spec \ +variables_saved_for_relink \ +libname_spec \ +library_names_spec \ +soname_spec \ +install_override_mode \ +finish_eval \ +old_striplib \ +striplib; do + case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +# Double-quote double-evaled strings. +for var in reload_cmds \ +old_postinstall_cmds \ +old_postuninstall_cmds \ +old_archive_cmds \ +extract_expsyms_cmds \ +old_archive_from_new_cmds \ +old_archive_from_expsyms_cmds \ +archive_cmds \ +archive_expsym_cmds \ +module_cmds \ +module_expsym_cmds \ +export_symbols_cmds \ +prelink_cmds \ +postinstall_cmds \ +postuninstall_cmds \ +finish_cmds \ +sys_lib_search_path_spec \ +sys_lib_dlsearch_path_spec; do + case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +ac_aux_dir='$ac_aux_dir' +xsi_shell='$xsi_shell' +lt_shell_append='$lt_shell_append' + +# See if we are running on zsh, and set the options which allow our +# commands through without removal of \ escapes INIT. +if test -n "\${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + + + PACKAGE='$PACKAGE' + VERSION='$VERSION' + TIMESTAMP='$TIMESTAMP' + RM='$RM' + ofile='$ofile' + + + +# Capture the value of obsolete ALL_LINGUAS because we need it to compute + # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it + # from automake. + eval 'OBSOLETE_ALL_LINGUAS''="$ALL_LINGUAS"' + # Capture the value of LINGUAS because we need it to compute CATALOGS. + LINGUAS="${LINGUAS-%UNSET%}" + + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;; + "libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;; + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "default-1") CONFIG_COMMANDS="$CONFIG_COMMANDS default-1" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "po/Makefile.in") CONFIG_FILES="$CONFIG_FILES po/Makefile.in:po/Make-in" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. 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See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Libtool; see the file COPYING. If not, a copy +# can be downloaded from http://www.gnu.org/licenses/gpl.html, or +# obtained by writing to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + + +# The names of the tagged configurations supported by this script. +available_tags="" + +# ### BEGIN LIBTOOL CONFIG + +# Whether or not to build shared libraries. +build_libtool_libs=$enable_shared + +# Which release of libtool.m4 was used? +macro_version=$macro_version +macro_revision=$macro_revision + +# Whether or not to build static libraries. +build_old_libs=$enable_static + +# What type of objects to build. +pic_mode=$pic_mode + +# Whether or not to optimize for fast installation. +fast_install=$enable_fast_install + +# Shell to use when invoking shell scripts. +SHELL=$lt_SHELL + +# An echo program that protects backslashes. +ECHO=$lt_ECHO + +# The host system. +host_alias=$host_alias +host=$host +host_os=$host_os + +# The build system. +build_alias=$build_alias +build=$build +build_os=$build_os + +# A sed program that does not truncate output. +SED=$lt_SED + +# Sed that helps us avoid accidentally triggering echo(1) options like -n. +Xsed="\$SED -e 1s/^X//" + +# A grep program that handles long lines. +GREP=$lt_GREP + +# An ERE matcher. +EGREP=$lt_EGREP + +# A literal string matcher. +FGREP=$lt_FGREP + +# A BSD- or MS-compatible name lister. +NM=$lt_NM + +# Whether we need soft or hard links. +LN_S=$lt_LN_S + +# What is the maximum length of a command? +max_cmd_len=$max_cmd_len + +# Object file suffix (normally "o"). +objext=$ac_objext + +# Executable file suffix (normally ""). +exeext=$exeext + +# whether the shell understands "unset". +lt_unset=$lt_unset + +# turn spaces into newlines. +SP2NL=$lt_lt_SP2NL + +# turn newlines into spaces. +NL2SP=$lt_lt_NL2SP + +# An object symbol dumper. +OBJDUMP=$lt_OBJDUMP + +# Method to check whether dependent libraries are shared objects. +deplibs_check_method=$lt_deplibs_check_method + +# Command to use when deplibs_check_method == "file_magic". +file_magic_cmd=$lt_file_magic_cmd + +# The archiver. +AR=$lt_AR +AR_FLAGS=$lt_AR_FLAGS + +# A symbol stripping program. +STRIP=$lt_STRIP + +# Commands used to install an old-style archive. +RANLIB=$lt_RANLIB +old_postinstall_cmds=$lt_old_postinstall_cmds +old_postuninstall_cmds=$lt_old_postuninstall_cmds + +# Whether to use a lock for old archive extraction. +lock_old_archive_extraction=$lock_old_archive_extraction + +# A C compiler. +LTCC=$lt_CC + +# LTCC compiler flags. +LTCFLAGS=$lt_CFLAGS + +# Take the output of nm and produce a listing of raw symbols and C names. +global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe + +# Transform the output of nm in a proper C declaration. +global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl + +# Transform the output of nm in a C name address pair. +global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address + +# Transform the output of nm in a C name address pair when lib prefix is needed. +global_symbol_to_c_name_address_lib_prefix=$lt_lt_cv_sys_global_symbol_to_c_name_address_lib_prefix + +# The name of the directory that contains temporary libtool files. +objdir=$objdir + +# Used to examine libraries when file_magic_cmd begins with "file". +MAGIC_CMD=$MAGIC_CMD + +# Must we lock files when doing compilation? +need_locks=$lt_need_locks + +# Tool to manipulate archived DWARF debug symbol files on Mac OS X. +DSYMUTIL=$lt_DSYMUTIL + +# Tool to change global to local symbols on Mac OS X. +NMEDIT=$lt_NMEDIT + +# Tool to manipulate fat objects and archives on Mac OS X. +LIPO=$lt_LIPO + +# ldd/readelf like tool for Mach-O binaries on Mac OS X. +OTOOL=$lt_OTOOL + +# ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4. +OTOOL64=$lt_OTOOL64 + +# Old archive suffix (normally "a"). +libext=$libext + +# Shared library suffix (normally ".so"). +shrext_cmds=$lt_shrext_cmds + +# The commands to extract the exported symbol list from a shared archive. +extract_expsyms_cmds=$lt_extract_expsyms_cmds + +# Variables whose values should be saved in libtool wrapper scripts and +# restored at link time. +variables_saved_for_relink=$lt_variables_saved_for_relink + +# Do we need the "lib" prefix for modules? +need_lib_prefix=$need_lib_prefix + +# Do we need a version for libraries? +need_version=$need_version + +# Library versioning type. +version_type=$version_type + +# Shared library runtime path variable. +runpath_var=$runpath_var + +# Shared library path variable. +shlibpath_var=$shlibpath_var + +# Is shlibpath searched before the hard-coded library search path? +shlibpath_overrides_runpath=$shlibpath_overrides_runpath + +# Format of library name prefix. +libname_spec=$lt_libname_spec + +# List of archive names. First name is the real one, the rest are links. +# The last name is the one that the linker finds with -lNAME +library_names_spec=$lt_library_names_spec + +# The coded name of the library, if different from the real name. +soname_spec=$lt_soname_spec + +# Permission mode override for installation of shared libraries. +install_override_mode=$lt_install_override_mode + +# Command to use after installation of a shared archive. +postinstall_cmds=$lt_postinstall_cmds + +# Command to use after uninstallation of a shared archive. +postuninstall_cmds=$lt_postuninstall_cmds + +# Commands used to finish a libtool library installation in a directory. +finish_cmds=$lt_finish_cmds + +# As "finish_cmds", except a single script fragment to be evaled but +# not shown. +finish_eval=$lt_finish_eval + +# Whether we should hardcode library paths into libraries. +hardcode_into_libs=$hardcode_into_libs + +# Compile-time system search path for libraries. +sys_lib_search_path_spec=$lt_sys_lib_search_path_spec + +# Run-time system search path for libraries. +sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec + +# Whether dlopen is supported. +dlopen_support=$enable_dlopen + +# Whether dlopen of programs is supported. +dlopen_self=$enable_dlopen_self + +# Whether dlopen of statically linked programs is supported. +dlopen_self_static=$enable_dlopen_self_static + +# Commands to strip libraries. +old_striplib=$lt_old_striplib +striplib=$lt_striplib + + +# The linker used to build libraries. +LD=$lt_LD + +# How to create reloadable object files. +reload_flag=$lt_reload_flag +reload_cmds=$lt_reload_cmds + +# Commands used to build an old-style archive. +old_archive_cmds=$lt_old_archive_cmds + +# A language specific compiler. +CC=$lt_compiler + +# Is the compiler the GNU compiler? +with_gcc=$GCC + +# Compiler flag to turn off builtin functions. +no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag + +# How to pass a linker flag through the compiler. +wl=$lt_lt_prog_compiler_wl + +# Additional compiler flags for building library objects. +pic_flag=$lt_lt_prog_compiler_pic + +# Compiler flag to prevent dynamic linking. +link_static_flag=$lt_lt_prog_compiler_static + +# Does compiler simultaneously support -c and -o options? +compiler_c_o=$lt_lt_cv_prog_compiler_c_o + +# Whether or not to add -lc for building shared libraries. +build_libtool_need_lc=$archive_cmds_need_lc + +# Whether or not to disallow shared libs when runtime libs are static. +allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes + +# Compiler flag to allow reflexive dlopens. +export_dynamic_flag_spec=$lt_export_dynamic_flag_spec + +# Compiler flag to generate shared objects directly from archives. +whole_archive_flag_spec=$lt_whole_archive_flag_spec + +# Whether the compiler copes with passing no objects directly. +compiler_needs_object=$lt_compiler_needs_object + +# Create an old-style archive from a shared archive. +old_archive_from_new_cmds=$lt_old_archive_from_new_cmds + +# Create a temporary old-style archive to link instead of a shared archive. +old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds + +# Commands used to build a shared archive. +archive_cmds=$lt_archive_cmds +archive_expsym_cmds=$lt_archive_expsym_cmds + +# Commands used to build a loadable module if different from building +# a shared archive. +module_cmds=$lt_module_cmds +module_expsym_cmds=$lt_module_expsym_cmds + +# Whether we are building with GNU ld or not. +with_gnu_ld=$lt_with_gnu_ld + +# Flag that allows shared libraries with undefined symbols to be built. +allow_undefined_flag=$lt_allow_undefined_flag + +# Flag that enforces no undefined symbols. +no_undefined_flag=$lt_no_undefined_flag + +# Flag to hardcode \$libdir into a binary during linking. +# This must work even if \$libdir does not exist +hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec + +# If ld is used when linking, flag to hardcode \$libdir into a binary +# during linking. This must work even if \$libdir does not exist. +hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld + +# Whether we need a single "-rpath" flag with a separated argument. +hardcode_libdir_separator=$lt_hardcode_libdir_separator + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary. +hardcode_direct=$hardcode_direct + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary and the resulting library dependency is +# "absolute",i.e impossible to change by setting \${shlibpath_var} if the +# library is relocated. +hardcode_direct_absolute=$hardcode_direct_absolute + +# Set to "yes" if using the -LDIR flag during linking hardcodes DIR +# into the resulting binary. +hardcode_minus_L=$hardcode_minus_L + +# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR +# into the resulting binary. +hardcode_shlibpath_var=$hardcode_shlibpath_var + +# Set to "yes" if building a shared library automatically hardcodes DIR +# into the library and all subsequent libraries and executables linked +# against it. +hardcode_automatic=$hardcode_automatic + +# Set to yes if linker adds runtime paths of dependent libraries +# to runtime path list. +inherit_rpath=$inherit_rpath + +# Whether libtool must link a program against all its dependency libraries. +link_all_deplibs=$link_all_deplibs + +# Fix the shell variable \$srcfile for the compiler. +fix_srcfile_path=$lt_fix_srcfile_path + +# Set to "yes" if exported symbols are required. +always_export_symbols=$always_export_symbols + +# The commands to list exported symbols. +export_symbols_cmds=$lt_export_symbols_cmds + +# Symbols that should not be listed in the preloaded symbols. +exclude_expsyms=$lt_exclude_expsyms + +# Symbols that must always be exported. +include_expsyms=$lt_include_expsyms + +# Commands necessary for linking programs (against libraries) with templates. +prelink_cmds=$lt_prelink_cmds + +# Specify filename containing input files. +file_list_spec=$lt_file_list_spec + +# How to hardcode a shared library path into an executable. +hardcode_action=$hardcode_action + +# ### END LIBTOOL CONFIG + +_LT_EOF + + case $host_os in + aix3*) + cat <<\_LT_EOF >> "$cfgfile" +# AIX sometimes has problems with the GCC collect2 program. For some +# reason, if we set the COLLECT_NAMES environment variable, the problems +# vanish in a puff of smoke. +if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES +fi +_LT_EOF + ;; + esac + + +ltmain="$ac_aux_dir/ltmain.sh" + + + # We use sed instead of cat because bash on DJGPP gets confused if + # if finds mixed CR/LF and LF-only lines. Since sed operates in + # text mode, it properly converts lines to CR/LF. This bash problem + # is reportedly fixed, but why not run on old versions too? + sed '/^# Generated shell functions inserted here/q' "$ltmain" >> "$cfgfile" \ + || (rm -f "$cfgfile"; exit 1) + + case $xsi_shell in + yes) + cat << \_LT_EOF >> "$cfgfile" + +# func_dirname file append nondir_replacement +# Compute the dirname of FILE. If nonempty, add APPEND to the result, +# otherwise set result to NONDIR_REPLACEMENT. +func_dirname () +{ + case ${1} in + */*) func_dirname_result="${1%/*}${2}" ;; + * ) func_dirname_result="${3}" ;; + esac +} + +# func_basename file +func_basename () +{ + func_basename_result="${1##*/}" +} + +# func_dirname_and_basename file append nondir_replacement +# perform func_basename and func_dirname in a single function +# call: +# dirname: Compute the dirname of FILE. If nonempty, +# add APPEND to the result, otherwise set result +# to NONDIR_REPLACEMENT. +# value returned in "$func_dirname_result" +# basename: Compute filename of FILE. +# value retuned in "$func_basename_result" +# Implementation must be kept synchronized with func_dirname +# and func_basename. For efficiency, we do not delegate to +# those functions but instead duplicate the functionality here. +func_dirname_and_basename () +{ + case ${1} in + */*) func_dirname_result="${1%/*}${2}" ;; + * ) func_dirname_result="${3}" ;; + esac + func_basename_result="${1##*/}" +} + +# func_stripname prefix suffix name +# strip PREFIX and SUFFIX off of NAME. +# PREFIX and SUFFIX must not contain globbing or regex special +# characters, hashes, percent signs, but SUFFIX may contain a leading +# dot (in which case that matches only a dot). +func_stripname () +{ + # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are + # positional parameters, so assign one to ordinary parameter first. + func_stripname_result=${3} + func_stripname_result=${func_stripname_result#"${1}"} + func_stripname_result=${func_stripname_result%"${2}"} +} + +# func_opt_split +func_opt_split () +{ + func_opt_split_opt=${1%%=*} + func_opt_split_arg=${1#*=} +} + +# func_lo2o object +func_lo2o () +{ + case ${1} in + *.lo) func_lo2o_result=${1%.lo}.${objext} ;; + *) func_lo2o_result=${1} ;; + esac +} + +# func_xform libobj-or-source +func_xform () +{ + func_xform_result=${1%.*}.lo +} + +# func_arith arithmetic-term... +func_arith () +{ + func_arith_result=$(( $* )) +} + +# func_len string +# STRING may not start with a hyphen. +func_len () +{ + func_len_result=${#1} +} + +_LT_EOF + ;; + *) # Bourne compatible functions. + cat << \_LT_EOF >> "$cfgfile" + +# func_dirname file append nondir_replacement +# Compute the dirname of FILE. If nonempty, add APPEND to the result, +# otherwise set result to NONDIR_REPLACEMENT. +func_dirname () +{ + # Extract subdirectory from the argument. + func_dirname_result=`$ECHO "${1}" | $SED "$dirname"` + if test "X$func_dirname_result" = "X${1}"; then + func_dirname_result="${3}" + else + func_dirname_result="$func_dirname_result${2}" + fi +} + +# func_basename file +func_basename () +{ + func_basename_result=`$ECHO "${1}" | $SED "$basename"` +} + + +# func_stripname prefix suffix name +# strip PREFIX and SUFFIX off of NAME. +# PREFIX and SUFFIX must not contain globbing or regex special +# characters, hashes, percent signs, but SUFFIX may contain a leading +# dot (in which case that matches only a dot). +# func_strip_suffix prefix name +func_stripname () +{ + case ${2} in + .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;; + *) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;; + esac +} + +# sed scripts: +my_sed_long_opt='1s/^\(-[^=]*\)=.*/\1/;q' +my_sed_long_arg='1s/^-[^=]*=//' + +# func_opt_split +func_opt_split () +{ + func_opt_split_opt=`$ECHO "${1}" | $SED "$my_sed_long_opt"` + func_opt_split_arg=`$ECHO "${1}" | $SED "$my_sed_long_arg"` +} + +# func_lo2o object +func_lo2o () +{ + func_lo2o_result=`$ECHO "${1}" | $SED "$lo2o"` +} + +# func_xform libobj-or-source +func_xform () +{ + func_xform_result=`$ECHO "${1}" | $SED 's/\.[^.]*$/.lo/'` +} + +# func_arith arithmetic-term... +func_arith () +{ + func_arith_result=`expr "$@"` +} + +# func_len string +# STRING may not start with a hyphen. +func_len () +{ + func_len_result=`expr "$1" : ".*" 2>/dev/null || echo $max_cmd_len` +} + +_LT_EOF +esac + +case $lt_shell_append in + yes) + cat << \_LT_EOF >> "$cfgfile" + +# func_append var value +# Append VALUE to the end of shell variable VAR. +func_append () +{ + eval "$1+=\$2" +} +_LT_EOF + ;; + *) + cat << \_LT_EOF >> "$cfgfile" + +# func_append var value +# Append VALUE to the end of shell variable VAR. +func_append () +{ + eval "$1=\$$1\$2" +} + +_LT_EOF + ;; + esac + + + sed -n '/^# Generated shell functions inserted here/,$p' "$ltmain" >> "$cfgfile" \ + || (rm -f "$cfgfile"; exit 1) + + mv -f "$cfgfile" "$ofile" || + (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile") + chmod +x "$ofile" + + ;; + "default-1":C) + for ac_file in $CONFIG_FILES; do + # Support "outfile[:infile[:infile...]]" + case "$ac_file" in + *:*) ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + esac + # PO directories have a Makefile.in generated from Makefile.in.in. + case "$ac_file" in */Makefile.in) + # Adjust a relative srcdir. + ac_dir=`echo "$ac_file"|sed 's%/[^/][^/]*$%%'` + ac_dir_suffix=/`echo "$ac_dir"|sed 's%^\./%%'` + ac_dots=`echo "$ac_dir_suffix"|sed 's%/[^/]*%../%g'` + # In autoconf-2.13 it is called $ac_given_srcdir. + # In autoconf-2.50 it is called $srcdir. + test -n "$ac_given_srcdir" || ac_given_srcdir="$srcdir" + case "$ac_given_srcdir" in + .) top_srcdir=`echo $ac_dots|sed 's%/$%%'` ;; + /*) top_srcdir="$ac_given_srcdir" ;; + *) top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + if test -f "$ac_given_srcdir/$ac_dir/POTFILES.in"; then + rm -f "$ac_dir/POTFILES" + test -n "$as_me" && echo "$as_me: creating $ac_dir/POTFILES" || echo "creating $ac_dir/POTFILES" + cat "$ac_given_srcdir/$ac_dir/POTFILES.in" | sed -e "/^#/d" -e "/^[ ]*\$/d" -e "s,.*, $top_srcdir/& \\\\," | sed -e "\$s/\(.*\) \\\\/\1/" > "$ac_dir/POTFILES" + POMAKEFILEDEPS="POTFILES.in" + # ALL_LINGUAS, POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES depend + # on $ac_dir but don't depend on user-specified configuration + # parameters. + if test -f "$ac_given_srcdir/$ac_dir/LINGUAS"; then + # The LINGUAS file contains the set of available languages. + if test -n "$OBSOLETE_ALL_LINGUAS"; then + test -n "$as_me" && echo "$as_me: setting ALL_LINGUAS in configure.in is obsolete" || echo "setting ALL_LINGUAS in configure.in is obsolete" + fi + ALL_LINGUAS_=`sed -e "/^#/d" "$ac_given_srcdir/$ac_dir/LINGUAS"` + # Hide the ALL_LINGUAS assigment from automake. + eval 'ALL_LINGUAS''=$ALL_LINGUAS_' + POMAKEFILEDEPS="$POMAKEFILEDEPS LINGUAS" + else + # The set of available languages was given in configure.in. + eval 'ALL_LINGUAS''=$OBSOLETE_ALL_LINGUAS' + fi + case "$ac_given_srcdir" in + .) srcdirpre= ;; + *) srcdirpre='$(srcdir)/' ;; + esac + POFILES= + GMOFILES= + UPDATEPOFILES= + DUMMYPOFILES= + for lang in $ALL_LINGUAS; do + POFILES="$POFILES $srcdirpre$lang.po" + GMOFILES="$GMOFILES $srcdirpre$lang.gmo" + UPDATEPOFILES="$UPDATEPOFILES $lang.po-update" + DUMMYPOFILES="$DUMMYPOFILES $lang.nop" + done + # CATALOGS depends on both $ac_dir and the user's LINGUAS + # environment variable. + INST_LINGUAS= + if test -n "$ALL_LINGUAS"; then + for presentlang in $ALL_LINGUAS; do + useit=no + if test "%UNSET%" != "$LINGUAS"; then + desiredlanguages="$LINGUAS" + else + desiredlanguages="$ALL_LINGUAS" + fi + for desiredlang in $desiredlanguages; do + # Use the presentlang catalog if desiredlang is + # a. equal to presentlang, or + # b. a variant of presentlang (because in this case, + # presentlang can be used as a fallback for messages + # which are not translated in the desiredlang catalog). + case "$desiredlang" in + "$presentlang"*) useit=yes;; + esac + done + if test $useit = yes; then + INST_LINGUAS="$INST_LINGUAS $presentlang" + fi + done + fi + CATALOGS= + if test -n "$INST_LINGUAS"; then + for lang in $INST_LINGUAS; do + CATALOGS="$CATALOGS $lang.gmo" + done + fi + test -n "$as_me" && echo "$as_me: creating $ac_dir/Makefile" || echo "creating $ac_dir/Makefile" + sed -e "/^POTFILES =/r $ac_dir/POTFILES" -e "/^# Makevars/r $ac_given_srcdir/$ac_dir/Makevars" -e "s|@POFILES@|$POFILES|g" -e "s|@GMOFILES@|$GMOFILES|g" -e "s|@UPDATEPOFILES@|$UPDATEPOFILES|g" -e "s|@DUMMYPOFILES@|$DUMMYPOFILES|g" -e "s|@CATALOGS@|$CATALOGS|g" -e "s|@POMAKEFILEDEPS@|$POMAKEFILEDEPS|g" "$ac_dir/Makefile.in" > "$ac_dir/Makefile" + for f in "$ac_given_srcdir/$ac_dir"/Rules-*; do + if test -f "$f"; then + case "$f" in + *.orig | *.bak | *~) ;; + *) cat "$f" >> "$ac_dir/Makefile" ;; + esac + fi + done + fi + ;; + esac + done ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/external/gpl3/gdb/dist/opcodes/configure.com b/external/gpl3/gdb/dist/opcodes/configure.com new file mode 100644 index 000000000000..a97bd9ba75c4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/configure.com @@ -0,0 +1,51 @@ +$! +$! This file configures the opcodes library for use with openVMS. +$! +$! We do not use the configure script, since we do not have /bin/sh +$! to execute it. +$! +$! Written by Tristan Gingold (gingold@adacore.com) +$! +$ arch=F$GETSYI("ARCH_NAME") +$ arch=F$EDIT(arch,"LOWERCASE") + +$! +$ write sys$output "Generate opcodes/build.com" +$! +$ if arch.eqs."ia64" +$ then +$ create build.com +$DECK +$ FILES="ia64-dis,ia64-opc" +$ DEFS="""ARCH_ia64""" +$EOD +$ endif +$ if arch.eqs."alpha" +$ then +$ create build.com +$DECK +$ FILES="alpha-dis,alpha-opc" +$ DEFS="""ARCH_alpha""" +$EOD +$ endif +$! +$ append sys$input build.com +$DECK +$ FILES=FILES + ",dis-init,dis-buf,disassemble" +$ OPT="/noopt/debug" +$ CFLAGS=OPT + "/include=([],""../include"",[-.bfd])/name=(as_is,shortened)" + - + "/define=(" + DEFS + ")" +$ write sys$output "CFLAGS=",CFLAGS +$ NUM = 0 +$ LOOP: +$ F = F$ELEMENT(NUM,",",FILES) +$ IF F.EQS."," THEN GOTO END +$ write sys$output "Compiling ", F, ".c" +$ cc 'CFLAGS 'F.c +$ NUM = NUM + 1 +$ GOTO LOOP +$ END: +$ purge +$ lib/create libopcodes 'FILES +$EOD +$exit diff --git a/external/gpl3/gdb/dist/opcodes/configure.in b/external/gpl3/gdb/dist/opcodes/configure.in new file mode 100644 index 000000000000..0518781ab32a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/configure.in @@ -0,0 +1,351 @@ +dnl Process this file with autoconf to produce a configure script. +dnl + +AC_PREREQ(2.59) +AC_INIT +AC_CONFIG_SRCDIR([z8k-dis.c]) + +AC_CANONICAL_TARGET +AC_ISC_POSIX + +# We currently only use the version number for the name of any shared +# library. For user convenience, we always use the same version +# number that BFD is using. +changequote(,)dnl +BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${srcdir}/../bfd/configure.in` +changequote([,])dnl + +AM_INIT_AUTOMAKE(opcodes, ${BFD_VERSION}) + +AC_PROG_CC +AC_GNU_SOURCE +AC_USE_SYSTEM_EXTENSIONS + +dnl These must be called before LT_INIT, because it may want +dnl to call AC_CHECK_PROG. +AC_CHECK_TOOL(AR, ar) +AC_CHECK_TOOL(RANLIB, ranlib, :) + +dnl Default to a non shared library. This may be overridden by the +dnl configure option --enable-shared. +AC_DISABLE_SHARED + +LT_INIT + +AC_ARG_ENABLE(targets, +[ --enable-targets alternative target configurations], +[case "${enableval}" in + yes | "") AC_MSG_ERROR([enable-targets option must specify target names or 'all']) + ;; + no) enable_targets= ;; + *) enable_targets=$enableval ;; +esac])dnl + +AM_BINUTILS_WARNINGS + +AC_CONFIG_HEADERS(config.h:config.in) + +if test -z "$target" ; then + AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) +fi + +AM_MAINTAINER_MODE +AM_INSTALL_LIBBFD +AC_EXEEXT + +# host-specific stuff: + +ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl fi vi ga zh_CN" +ZW_GNU_GETTEXT_SISTER_DIR +AM_PO_SUBDIRS + +. ${srcdir}/../bfd/configure.host + +BFD_CC_FOR_BUILD + +AC_SUBST(HDEFINES) +AC_PROG_INSTALL + +AC_CHECK_HEADERS(string.h strings.h stdlib.h limits.h) + +AC_CHECK_DECLS([basename, stpcpy]) + +cgen_maint=no +cgendir='$(srcdir)/../cgen' + +AC_ARG_ENABLE(cgen-maint, +[ --enable-cgen-maint[=dir] build cgen generated files], +[case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgen_maint=yes + cgendir=${cgen_maint}/lib/cgen + ;; +esac])dnl +AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} = xyes) +AC_SUBST(cgendir) + +using_cgen=no + +# Check if linker supports --as-needed and --no-as-needed options +AC_CACHE_CHECK(linker --as-needed support, bfd_cv_ld_as_needed, + [bfd_cv_ld_as_needed=no + if $LD --help 2>/dev/null | grep as-needed > /dev/null; then + bfd_cv_ld_as_needed=yes + fi + ]) + +LT_LIB_M + +#Libs for generator progs +if test "x$cross_compiling" = "xno"; then + BUILD_LIBS=../libiberty/libiberty.a + BUILD_LIB_DEPS=$BUILD_LIBS +else + # if cross-compiling, assume that the system provides -liberty + # and that the version is compatible with new headers. + BUILD_LIBS=-liberty + BUILD_LIB_DEPS= +fi +BUILD_LIBS="$BUILD_LIBS $LIBINTL" +BUILD_LIB_DEPS="$BUILD_LIB_DEPS $LIBINTL_DEP" + +AC_SUBST(BUILD_LIBS) +AC_SUBST(BUILD_LIB_DEPS) + +# Horrible hacks to build DLLs on Windows and a shared library elsewhere. +SHARED_LDFLAGS= +SHARED_LIBADD= +SHARED_DEPENDENCIES= +if test "$enable_shared" = "yes"; then +# When building a shared libopcodes, link against the pic version of libiberty +# so that apps that use libopcodes won't need libiberty just to satisfy any +# libopcodes references. +# We can't do that if a pic libiberty is unavailable since including non-pic +# code would insert text relocations into libopcodes. +# Note that linking against libbfd as we do here, which is itself linked +# against libiberty, may not satisfy all the libopcodes libiberty references +# since libbfd may not pull in the entirety of libiberty. +changequote(,)dnl + x=`sed -n -e 's/^[ ]*PICFLAG[ ]*=[ ]*//p' < ../libiberty/Makefile | sed -n '$p'` +changequote([,])dnl + if test -n "$x"; then + SHARED_LIBADD="-L`pwd`/../libiberty/pic -liberty" + fi + + case "${host}" in + *-*-cygwin*) + SHARED_LDFLAGS="-no-undefined" + SHARED_LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" + ;; + *-*-darwin*) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.dylib ${SHARED_LIBADD}" + SHARED_DEPENDENCIES="../bfd/libbfd.la" + ;; + *) + case "$host_vendor" in + hp) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.sl ${SHARED_LIBADD}" + ;; + *) + SHARED_LIBADD="-Wl,`pwd`/../bfd/.libs/libbfd.so ${SHARED_LIBADD}" + ;; + esac + SHARED_DEPENDENCIES="../bfd/libbfd.la" + ;; + esac + + if test -n "$SHARED_LIBADD"; then + if test -n "$LIBM"; then + if test x"$bfd_cv_ld_as_needed" = xyes; then + # Link against libm only when needed. Put -lc, -lm inside -Wl + # to stop libtool reordering these options. + SHARED_LIBADD="$SHARED_LIBADD -Wl,-lc,--as-needed,`echo $LIBM | sed 's/ /,/g'`,--no-as-needed" + else + SHARED_LIBADD="$SHARED_LIBADD $LIBM" + fi + fi + fi +fi +AC_SUBST(SHARED_LDFLAGS) +AC_SUBST(SHARED_LIBADD) +AC_SUBST(SHARED_DEPENDENCIES) + +# target-specific stuff: + +# Canonicalize the secondary target names. +if test -n "$enable_targets" ; then + for targ in `echo $enable_targets | sed 's/,/ /g'` + do + result=`$ac_config_sub $targ 2>/dev/null` + if test -n "$result" ; then + canon_targets="$canon_targets $result" + else + # Allow targets that config.sub doesn't recognize, like "all". + canon_targets="$canon_targets $targ" + fi + done +fi + +all_targets=false +selarchs= +for targ in $target $canon_targets +do + if test "x$targ" = "xall" ; then + all_targets=true + else + . $srcdir/../bfd/config.bfd + selarchs="$selarchs $targ_archs" + fi +done + +# Utility var, documents generic cgen support files. + +cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo cgen-bitset.lo" + +# We don't do any links based on the target system, just makefile config. + +if test x${all_targets} = xfalse ; then + + # Target architecture .o files. + ta= + + for arch in $selarchs + do + ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` + archdefs="$archdefs -DARCH_$ad" + case "$arch" in + bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; + bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arm_arch) ta="$ta arm-dis.lo" ;; + bfd_avr_arch) ta="$ta avr-dis.lo" ;; + bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; + bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; + bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; + bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; + bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; + bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; + bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; + bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; + bfd_moxie_arch) ta="$ta moxie-dis.lo moxie-opc.lo" ;; + bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; + bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; + bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; + bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; + bfd_i386_arch|bfd_l1om_arch) + ta="$ta i386-dis.lo i386-opc.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; + bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; + bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;; + bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; + bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; + bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; + bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; + bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;; + bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; + bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; + bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; + bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; + bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; + bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; + bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_pyramid_arch) ;; + bfd_romp_arch) ;; + bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;; + bfd_sh_arch) + # We can't decide what we want just from the CPU family. + # We want SH5 support unless a specific version of sh is + # specified, as in sh3-elf, sh3b-linux-gnu, etc. + # Include it just for ELF targets, since the SH5 bfd:s are ELF only. + for t in $target $canon_targets; do + case $t in + all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ + sh-*-linux* | shl-*-linux*) + ta="$ta sh64-dis.lo sh64-opc.lo" + archdefs="$archdefs -DINCLUDE_SHMEDIA" + break;; + esac; + done + ta="$ta sh-dis.lo cgen-bitset.lo" ;; + bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_spu_arch) ta="$ta spu-dis.lo spu-opc.lo" ;; + bfd_tahoe_arch) ;; + bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; + bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; + bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;; + bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; + bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; + bfd_vax_arch) ta="$ta vax-dis.lo" ;; + bfd_w65_arch) ta="$ta w65-dis.lo" ;; + bfd_we32k_arch) ;; + bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; + bfd_z80_arch) ta="$ta z80-dis.lo" ;; + bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + + "") ;; + *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; + esac + done + + if test $using_cgen = yes ; then + ta="$ta $cgen_files" + fi + + # Weed out duplicate .o files. + f="" + for i in $ta ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + ta="$f" + + # And duplicate -D flags. + f="" + for i in $archdefs ; do + case " $f " in + *" $i "*) ;; + *) f="$f $i" ;; + esac + done + archdefs="$f" + + BFD_MACHINES="$ta" + +else # all_targets is true + archdefs=-DARCH_all + BFD_MACHINES='$(ALL_MACHINES)' +fi + +AC_SUBST(archdefs) +AC_SUBST(BFD_MACHINES) + +AC_CONFIG_FILES([Makefile po/Makefile.in:po/Make-in]) +AC_OUTPUT diff --git a/external/gpl3/gdb/dist/opcodes/cr16-dis.c b/external/gpl3/gdb/dist/opcodes/cr16-dis.c new file mode 100644 index 000000000000..0aaf61c3276a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cr16-dis.c @@ -0,0 +1,831 @@ +/* Disassembler code for CR16. + Copyright 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com). + + This file is part of GAS, GDB and the GNU binutils. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/cr16.h" +#include "libiberty.h" + +/* String to print when opcode was not matched. */ +#define ILLEGAL "illegal" + /* Escape to 16-bit immediate. */ +#define ESCAPE_16_BIT 0xB + +/* Extract 'n_bits' from 'a' starting from offset 'offs'. */ +#define EXTRACT(a, offs, n_bits) \ + (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \ + : (((a) >> (offs)) & ((1 << (n_bits)) -1))) + +/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */ +#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs))) + +typedef unsigned long dwordU; +typedef unsigned short wordU; + +typedef struct +{ + dwordU val; + int nbits; +} parameter; + +/* Structure to map valid 'cinv' instruction options. */ + +typedef struct + { + /* Cinv printed string. */ + char *istr; + /* Value corresponding to the string. */ + char *ostr; + } +cinv_entry; + +/* CR16 'cinv' options mapping. */ +const cinv_entry cr16_cinvs[] = +{ + {"cinv[i]", "cinv [i]"}, + {"cinv[i,u]", "cinv [i,u]"}, + {"cinv[d]", "cinv [d]"}, + {"cinv[d,u]", "cinv [d,u]"}, + {"cinv[d,i]", "cinv [d,i]"}, + {"cinv[d,i,u]", "cinv [d,i,u]"} +}; + +/* Number of valid 'cinv' instruction options. */ +static int NUMCINVS = ARRAY_SIZE (cr16_cinvs); + +/* Enum to distinguish different registers argument types. */ +typedef enum REG_ARG_TYPE + { + /* General purpose register (r). */ + REG_ARG = 0, + /*Processor register */ + P_ARG, + } +REG_ARG_TYPE; + +/* Current opcode table entry we're disassembling. */ +const inst *instruction; +/* Current instruction we're disassembling. */ +ins currInsn; +/* The current instruction is read into 3 consecutive words. */ +wordU words[3]; +/* Contains all words in appropriate order. */ +ULONGLONG allWords; +/* Holds the current processed argument number. */ +int processing_argument_number; +/* Nonzero means a IMM4 instruction. */ +int imm4flag; +/* Nonzero means the instruction's original size is + incremented (escape sequence is used). */ +int size_changed; + + +/* Print the constant expression length. */ + +static char * +print_exp_len (int size) +{ + switch (size) + { + case 4: + case 5: + case 6: + case 8: + case 14: + case 16: + return ":s"; + case 20: + case 24: + case 32: + return ":m"; + case 48: + return ":l"; + default: + return ""; + } +} + + +/* Retrieve the number of operands for the current assembled instruction. */ + +static int +get_number_of_operands (void) +{ + int i; + + for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) + ; + + return i; +} + +/* Return the bit size for a given operand. */ + +static int +getbits (operand_type op) +{ + if (op < MAX_OPRD) + return cr16_optab[op].bit_size; + + return 0; +} + +/* Return the argument type of a given operand. */ + +static argtype +getargtype (operand_type op) +{ + if (op < MAX_OPRD) + return cr16_optab[op].arg_type; + + return nullargs; +} + +/* Given a 'CC' instruction constant operand, return its corresponding + string. This routine is used when disassembling the 'CC' instruction. */ + +static char * +getccstring (unsigned cc_insn) +{ + return (char *) cr16_b_cond_tab[cc_insn]; +} + + +/* Given a 'cinv' instruction constant operand, return its corresponding + string. This routine is used when disassembling the 'cinv' instruction. */ + +static char * +getcinvstring (const char *str) +{ + const cinv_entry *cinv; + + for (cinv = cr16_cinvs; cinv < (cr16_cinvs + NUMCINVS); cinv++) + if (strcmp (cinv->istr, str) == 0) + return cinv->ostr; + + return ILLEGAL; +} + +/* Given the trap index in dispatch table, return its name. + This routine is used when disassembling the 'excp' instruction. */ + +static char * +gettrapstring (unsigned int trap_index) +{ + const trap_entry *trap; + + for (trap = cr16_traps; trap < cr16_traps + NUMTRAPS; trap++) + if (trap->entry == trap_index) + return trap->name; + + return ILLEGAL; +} + +/* Given a register enum value, retrieve its name. */ + +static char * +getregname (reg r) +{ + const reg_entry * regentry = cr16_regtab + r; + + if (regentry->type != CR16_R_REGTYPE) + return ILLEGAL; + + return regentry->name; +} + +/* Given a register pair enum value, retrieve its name. */ + +static char * +getregpname (reg r) +{ + const reg_entry * regentry = cr16_regptab + r; + + if (regentry->type != CR16_RP_REGTYPE) + return ILLEGAL; + + return regentry->name; +} + +/* Given a index register pair enum value, retrieve its name. */ + +static char * +getidxregpname (reg r) +{ + const reg_entry * regentry; + + switch (r) + { + case 0: r = 0; break; + case 1: r = 2; break; + case 2: r = 4; break; + case 3: r = 6; break; + case 4: r = 8; break; + case 5: r = 10; break; + case 6: r = 3; break; + case 7: r = 5; break; + default: + break; + } + + regentry = cr16_regptab + r; + + if (regentry->type != CR16_RP_REGTYPE) + return ILLEGAL; + + return regentry->name; +} + +/* Getting a processor register name. */ + +static char * +getprocregname (int reg_index) +{ + const reg_entry *r; + + for (r = cr16_pregtab; r < cr16_pregtab + NUMPREGS; r++) + if (r->image == reg_index) + return r->name; + + return "ILLEGAL REGISTER"; +} + +/* Getting a processor register name - 32 bit size. */ + +static char * +getprocpregname (int reg_index) +{ + const reg_entry *r; + + for (r = cr16_pregptab; r < cr16_pregptab + NUMPREGPS; r++) + if (r->image == reg_index) + return r->name; + + return "ILLEGAL REGISTER"; +} + +/* START and END are relating 'allWords' struct, which is 48 bits size. + + START|--------|END + +---------+---------+---------+---------+ + | | V | A | L | + +---------+---------+---------+---------+ + 0 16 32 48 + words [0] [1] [2] */ + +static parameter +makelongparameter (ULONGLONG val, int start, int end) +{ + parameter p; + + p.val = (dwordU) EXTRACT (val, 48 - end, end - start); + p.nbits = end - start; + return p; +} + +/* Build a mask of the instruction's 'constant' opcode, + based on the instruction's printing flags. */ + +static unsigned long +build_mask (void) +{ + unsigned long mask = SBM (instruction->match_bits); + + /* Adjust mask for bcond with 32-bit size instruction. */ + if ((IS_INSN_MNEMONIC("b") && instruction->size == 2)) + mask = 0xff0f0000; + + return mask; +} + +/* Search for a matching opcode. Return 1 for success, 0 for failure. */ + +static int +match_opcode (void) +{ + unsigned long mask; + /* The instruction 'constant' opcode doewsn't exceed 32 bits. */ + unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff; + + /* Start searching from end of instruction table. */ + instruction = &cr16_instruction[NUMOPCODES - 2]; + + /* Loop over instruction table until a full match is found. */ + while (instruction >= cr16_instruction) + { + mask = build_mask (); + /* Adjust mask for bcond with 32-bit size instruction */ + if ((IS_INSN_MNEMONIC("b") && instruction->size == 2)) + mask = 0xff0f0000; + + if ((doubleWord & mask) == BIN (instruction->match, + instruction->match_bits)) + return 1; + else + instruction--; + } + return 0; +} + +/* Set the proper parameter value for different type of arguments. */ + +static void +make_argument (argument * a, int start_bits) +{ + int inst_bit_size; + parameter p; + + if ((instruction->size == 3) && a->size >= 16) + inst_bit_size = 48; + else + inst_bit_size = 32; + + switch (a->type) + { + case arg_r: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_rp: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->rp = p.val; + break; + + case arg_pr: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->pr = p.val; + break; + + case arg_prp: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->prp = p.val; + break; + + case arg_ic: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->constant = p.val; + break; + + case arg_cc: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + + a->cc = p.val; + break; + + case arg_idxr: + if ((IS_INSN_MNEMONIC ("cbitb")) + || (IS_INSN_MNEMONIC ("sbitb")) + || (IS_INSN_MNEMONIC ("tbitb"))) + p = makelongparameter (allWords, 8, 9); + else + p = makelongparameter (allWords, 9, 10); + a->i_r = p.val; + p = makelongparameter (allWords, inst_bit_size - a->size, inst_bit_size); + a->constant = p.val; + break; + + case arg_idxrp: + p = makelongparameter (allWords, start_bits + 12, start_bits + 13); + a->i_r = p.val; + p = makelongparameter (allWords, start_bits + 13, start_bits + 16); + a->rp = p.val; + if (inst_bit_size > 32) + { + p = makelongparameter (allWords, inst_bit_size - start_bits - 12, + inst_bit_size); + a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, inst_bit_size - 22, inst_bit_size); + a->constant = (p.val & 0xf) | (((p.val >>20) & 0x3) << 4) + | ((p.val >>14 & 0x3) << 6) | (((p.val >>7) & 0x1f) <<7); + } + else if (instruction->size == 1 && a->size == 0) + a->constant = 0; + + break; + + case arg_rbase: + p = makelongparameter (allWords, inst_bit_size, inst_bit_size); + a->constant = p.val; + p = makelongparameter (allWords, inst_bit_size - (start_bits + 4), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_cr: + p = makelongparameter (allWords, start_bits + 12, start_bits + 16); + a->r = p.val; + p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size); + a->constant = p.val; + break; + + case arg_crp: + if (instruction->size == 1) + p = makelongparameter (allWords, 12, 16); + else + p = makelongparameter (allWords, start_bits + 12, start_bits + 16); + a->rp = p.val; + + if (inst_bit_size > 32) + { + p = makelongparameter (allWords, inst_bit_size - start_bits - 12, + inst_bit_size); + a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size); + a->constant = p.val; + } + else if (instruction->size == 1 && a->size != 0) + { + p = makelongparameter (allWords, 4, 8); + if (IS_INSN_MNEMONIC ("loadw") + || IS_INSN_MNEMONIC ("loadd") + || IS_INSN_MNEMONIC ("storw") + || IS_INSN_MNEMONIC ("stord")) + a->constant = (p.val * 2); + else + a->constant = p.val; + } + else /* below case for 0x0(reg pair) */ + a->constant = 0; + + break; + + case arg_c: + + if ((IS_INSN_TYPE (BRANCH_INS)) + || (IS_INSN_MNEMONIC ("bal")) + || (IS_INSN_TYPE (CSTBIT_INS)) + || (IS_INSN_TYPE (LD_STOR_INS))) + { + switch (a->size) + { + case 8 : + p = makelongparameter (allWords, 0, start_bits); + a->constant = ((((p.val&0xf00)>>4)) | (p.val&0xf)); + break; + + case 24: + if (instruction->size == 3) + { + p = makelongparameter (allWords, 16, inst_bit_size); + a->constant = ((((p.val>>16)&0xf) << 20) + | (((p.val>>24)&0xf) << 16) + | (p.val & 0xffff)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, 8, inst_bit_size); + a->constant = p.val; + } + break; + + default: + p = makelongparameter (allWords, inst_bit_size - (start_bits + + a->size), inst_bit_size - start_bits); + a->constant = p.val; + break; + } + } + else + { + p = makelongparameter (allWords, inst_bit_size - + (start_bits + a->size), + inst_bit_size - start_bits); + a->constant = p.val; + } + break; + + default: + break; + } +} + +/* Print a single argument. */ + +static void +print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info) +{ + LONGLONG longdisp, mask; + int sign_flag = 0; + int relative = 0; + bfd_vma number; + PTR stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (a->type) + { + case arg_r: + func (stream, "%s", getregname (a->r)); + break; + + case arg_rp: + func (stream, "%s", getregpname (a->rp)); + break; + + case arg_pr: + func (stream, "%s", getprocregname (a->pr)); + break; + + case arg_prp: + func (stream, "%s", getprocpregname (a->prp)); + break; + + case arg_cc: + func (stream, "%s", getccstring (a->cc)); + func (stream, "%s", "\t"); + break; + + case arg_ic: + if (IS_INSN_MNEMONIC ("excp")) + { + func (stream, "%s", gettrapstring (a->constant)); + break; + } + else if ((IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS)) + && ((instruction->size == 1) && (a->constant == 9))) + func (stream, "$%d", -1); + else if (INST_HAS_REG_LIST) + func (stream, "$0x%lx", a->constant +1); + else if (IS_INSN_TYPE (SHIFT_INS)) + { + longdisp = a->constant; + mask = ((LONGLONG)1 << a->size) - 1; + if (longdisp & ((LONGLONG)1 << (a->size -1))) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + a->constant = (unsigned long int) (longdisp & mask); + func (stream, "$%d", ((int)(sign_flag ? -a->constant : + a->constant))); + } + else + func (stream, "$0x%lx", a->constant); + switch (a->size) + { + case 4 : case 5 : case 6 : case 8 : + func (stream, "%s", ":s"); break; + case 16 : case 20 : func (stream, "%s", ":m"); break; + case 24 : case 32 : func (stream, "%s", ":l"); break; + default: break; + } + break; + + case arg_idxr: + if (a->i_r == 0) func (stream, "[r12]"); + if (a->i_r == 1) func (stream, "[r13]"); + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + break; + + case arg_idxrp: + if (a->i_r == 0) func (stream, "[r12]"); + if (a->i_r == 1) func (stream, "[r13]"); + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "%s", getidxregpname (a->rp)); + break; + + case arg_rbase: + func (stream, "(%s)", getregname (a->r)); + break; + + case arg_cr: + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "(%s)", getregname (a->r)); + break; + + case arg_crp: + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "%s", getregpname (a->rp)); + break; + + case arg_c: + /*Removed the *2 part as because implicit zeros are no more required. + Have to fix this as this needs a bit of extension in terms of branch + instructions. */ + if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal")) + { + relative = 1; + longdisp = a->constant; + /* REVISIT: To sync with WinIDEA and CR16 4.1tools, the below + line commented */ + /* longdisp <<= 1; */ + mask = ((LONGLONG)1 << a->size) - 1; + switch (a->size) + { + case 8 : + { + longdisp <<= 1; + if (longdisp & ((LONGLONG)1 << a->size)) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + break; + } + case 16 : + case 24 : + { + if (longdisp & 1) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + break; + } + default: + func (stream, "Wrong offset used in branch/bal instruction"); + break; + } + a->constant = (unsigned long int) (longdisp & mask); + } + /* For branch Neq instruction it is 2*offset + 2. */ + else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) + a->constant = 2 * a->constant + 2; + + if ((!IS_INSN_TYPE (CSTBIT_INS)) && (!IS_INSN_TYPE (LD_STOR_INS))) + (sign_flag) ? func (stream, "%s", "*-"): func (stream, "%s","*+"); + + /* PR 10173: Avoid printing the 0x prefix twice. */ + if (info->num_symbols > 0) + func (stream, "%s", "0x"); + number = ((relative ? memaddr : 0) + + (sign_flag ? ((- a->constant) & 0xffffffe) : a->constant)); + + (*info->print_address_func) ((number & ((1 << 24) - 1)), info); + + func (stream, "%s", print_exp_len (instruction->size * 16)); + break; + + default: + break; + } +} + +/* Print all the arguments of CURRINSN instruction. */ + +static void +print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + + /* For "pop/push/popret RA instruction only. */ + if ((IS_INSN_MNEMONIC ("pop") + || (IS_INSN_MNEMONIC ("popret") + || (IS_INSN_MNEMONIC ("push")))) + && currentInsn->nargs == 1) + { + info->fprintf_func (info->stream, "RA"); + return; + } + + for (i = 0; i < currentInsn->nargs; i++) + { + processing_argument_number = i; + + /* For "bal (ra), disp17" instruction only. */ + if ((IS_INSN_MNEMONIC ("bal")) && (i == 0) && instruction->size == 2) + { + info->fprintf_func (info->stream, "(ra),"); + continue; + } + + if ((INST_HAS_REG_LIST) && (i == 2)) + info->fprintf_func (info->stream, "RA"); + else + print_arg (¤tInsn->arg[i], memaddr, info); + + if ((i != currentInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b"))) + info->fprintf_func (info->stream, ","); + } +} + +/* Build the instruction's arguments. */ + +static void +make_instruction (void) +{ + int i; + unsigned int shift; + + for (i = 0; i < currInsn.nargs; i++) + { + argument a; + + memset (&a, 0, sizeof (a)); + a.type = getargtype (instruction->operands[i].op_type); + a.size = getbits (instruction->operands[i].op_type); + shift = instruction->operands[i].shift; + + make_argument (&a, shift); + currInsn.arg[i] = a; + } + + /* Calculate instruction size (in bytes). */ + currInsn.size = instruction->size + (size_changed ? 1 : 0); + /* Now in bits. */ + currInsn.size *= 2; +} + +/* Retrieve a single word from a given memory address. */ + +static wordU +get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int status; + wordU insn = 0; + + status = info->read_memory_func (memaddr, buffer, 2, info); + + if (status == 0) + insn = (wordU) bfd_getl16 (buffer); + + return insn; +} + +/* Retrieve multiple words (3) from a given memory address. */ + +static void +get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + bfd_vma mem; + + for (i = 0, mem = memaddr; i < 3; i++, mem += 2) + words[i] = get_word_at_PC (mem, info); + + allWords = + ((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2]; +} + +/* Prints the instruction by calling print_arguments after proper matching. */ + +int +print_insn_cr16 (bfd_vma memaddr, struct disassemble_info *info) +{ + int is_decoded; /* Nonzero means instruction has a match. */ + + /* Initialize global variables. */ + imm4flag = 0; + size_changed = 0; + + /* Retrieve the encoding from current memory location. */ + get_words_at_PC (memaddr, info); + /* Find a matching opcode in table. */ + is_decoded = match_opcode (); + /* If found, print the instruction's mnemonic and arguments. */ + if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0) + { + if (strneq (instruction->mnemonic, "cinv", 4)) + info->fprintf_func (info->stream,"%s", getcinvstring (instruction->mnemonic)); + else + info->fprintf_func (info->stream, "%s", instruction->mnemonic); + + if (((currInsn.nargs = get_number_of_operands ()) != 0) + && ! (IS_INSN_MNEMONIC ("b"))) + info->fprintf_func (info->stream, "\t"); + make_instruction (); + /* For push/pop/pushrtn with RA instructions. */ + if ((INST_HAS_REG_LIST) && ((words[0] >> 7) & 0x1)) + currInsn.nargs +=1; + print_arguments (&currInsn, memaddr, info); + return currInsn.size; + } + + /* No match found. */ + info->fprintf_func (info->stream,"%s ",ILLEGAL); + return 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/cr16-opc.c b/external/gpl3/gdb/dist/opcodes/cr16-opc.c new file mode 100644 index 000000000000..059794f07e8b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cr16-opc.c @@ -0,0 +1,612 @@ +/* cr16-opc.c -- Table of opcodes for the CR16 processor. + Copyright 2007, 2008, 2010 Free Software Foundation, Inc. + Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include +#include "libiberty.h" +#include "symcat.h" +#include "opcode/cr16.h" + +const inst cr16_instruction[] = +{ +/* Create an arithmetic instruction - INST[bw]. */ +#define ARITH_BYTE_INST(NAME, OPC, OP1) \ + /* opc8 imm4 r */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \ + /* opc8 imm16 r */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \ + /* opc8 r r */ \ + {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} + +/* For Logical operations, allow unsigned imm16 also. */ +#define ARITH1_BYTE_INST(NAME, OPC, OP1) \ + /* opc8 imm16 r */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}} + + + ARITH_BYTE_INST ("andb", 0x20, uimm16), + ARITH1_BYTE_INST ("andb", 0x20, imm16), + ARITH_BYTE_INST ("andw", 0x22, uimm16), + ARITH1_BYTE_INST ("andw", 0x22, imm16), + + ARITH_BYTE_INST ("orb", 0x24, uimm16), + ARITH1_BYTE_INST ("orb", 0x24, imm16), + ARITH_BYTE_INST ("orw", 0x26, uimm16), + ARITH1_BYTE_INST ("orw", 0x26, imm16), + + ARITH_BYTE_INST ("xorb", 0x28, uimm16), + ARITH1_BYTE_INST ("xorb", 0x28, imm16), + ARITH_BYTE_INST ("xorw", 0x2A, uimm16), + ARITH1_BYTE_INST ("xorw", 0x2A, imm16), + + ARITH_BYTE_INST ("addub", 0x2C, imm16), + ARITH_BYTE_INST ("adduw", 0x2E, imm16), + ARITH_BYTE_INST ("addb", 0x30, imm16), + ARITH_BYTE_INST ("addw", 0x32, imm16), + ARITH_BYTE_INST ("addcb", 0x34, imm16), + ARITH_BYTE_INST ("addcw", 0x36, imm16), + + ARITH_BYTE_INST ("subb", 0x38, imm16), + ARITH_BYTE_INST ("subw", 0x3A, imm16), + ARITH_BYTE_INST ("subcb", 0x3C, imm16), + ARITH_BYTE_INST ("subcw", 0x3E, imm16), + + ARITH_BYTE_INST ("cmpb", 0x50, imm16), + ARITH_BYTE_INST ("cmpw", 0x52, imm16), + + ARITH_BYTE_INST ("movb", 0x58, imm16), + ARITH_BYTE_INST ("movw", 0x5A, imm16), + + ARITH_BYTE_INST ("mulb", 0x64, imm16), + ARITH_BYTE_INST ("mulw", 0x66, imm16), + +#define ARITH_BYTE_INST1(NAME, OPC) \ + /* opc8 r r */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} + + ARITH_BYTE_INST1 ("movxb", 0x5C), + ARITH_BYTE_INST1 ("movzb", 0x5D), + ARITH_BYTE_INST1 ("mulsb", 0x0B), + +#define ARITH_BYTE_INST2(NAME, OPC) \ + /* opc8 r rp */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}} + + ARITH_BYTE_INST2 ("movxw", 0x5E), + ARITH_BYTE_INST2 ("movzw", 0x5F), + ARITH_BYTE_INST2 ("mulsw", 0x62), + ARITH_BYTE_INST2 ("muluw", 0x63), + +/* Create an arithmetic instruction - INST[d]- with 3 types. */ +#define ARITH_INST_D(NAME, OPC) \ + /* opc8 imm4 rp */ \ + {NAME, 1, OPC, 24, ARITH_INS, {{uimm4_1,20}, {regp,16}}}, \ + /* opc8 imm16 rp */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_INS, {{imm16,0}, {regp,16}}}, \ + /* opc8 rp rp */ \ + {NAME, 1, OPC+1, 24, ARITH_INS, {{regp,20}, {regp,16}}} + +/* Create an arithmetic instruction - INST[d]-20 bit types. */ +#define ARITH_INST20(NAME, OPC) \ + /* opc8 uimm20 rp */ \ + {NAME, 2, OPC, 24, ARITH_INS, {{uimm20,0}, {regp,20}}} + +/* Create an arithmetic instruction - INST[d]-32 bit types. */ +#define ARITH_INST32(NAME, OPC, OP1) \ + /* opc12 imm32 rp */ \ + {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0}, {regp,16}}} + +/* Create an arithmetic instruction - INST[d]-32bit types(reg pairs).*/ +#define ARITH_INST32RP(NAME, OPC) \ + /* opc24 rp rp */ \ + {NAME, 2, OPC, 12, ARITH_INS, {{regp,4}, {regp,0}}} + + ARITH_INST_D ("movd", 0x54), + ARITH_INST20 ("movd", 0x05), + ARITH_INST32 ("movd", 0x007, imm32), + ARITH_INST_D ("addd", 0x60), + ARITH_INST20 ("addd", 0x04), + ARITH_INST32 ("addd", 0x002, imm32), + ARITH_INST32 ("subd", 0x003, imm32), + ARITH_INST32RP ("subd", 0x0014C), + ARITH_INST_D ("cmpd", 0x56), + ARITH_INST32 ("cmpd", 0x009, imm32), + ARITH_INST32 ("andd", 0x004, uimm32), + ARITH_INST32RP ("andd", 0x0014B), + ARITH_INST32 ("ord", 0x005, uimm32), + ARITH_INST32RP ("ord", 0x00149), + ARITH_INST32 ("xord", 0x006, uimm32), + ARITH_INST32RP ("xord", 0x0014A), + +/* Create a shift instruction. */ +#define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ + /* opc imm r */ \ + {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ + /* opc imm r */ \ + {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ + /* opc r r */ \ + {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} + + SHIFT_INST_A("ashub", 0x80, 0x41, 23, imm4, regr), + SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp), + SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr), + +#define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ + /* opc imm r */ \ + {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ + /* opc r r */ \ + {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} + + SHIFT_INST_L("lshb", 0x13, 0x44, 23, imm4, regr), + SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp), + SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr), + +/* Create a conditional branch instruction. */ +#define BRANCH_INST(NAME, OPC) \ + /* opc4 c4 dispe9 */ \ + {NAME, 1, OPC, 28, BRANCH_INS | RELAXABLE, {{cc,20}, {dispe9,16}}},\ + /* opc4 c4 disps17 */ \ + {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS | RELAXABLE, {{cc,20}, {disps17,0}}},\ + /* opc4 c4 disps25 */ \ + {NAME, 3, (OPC<<4), 16 , BRANCH_INS | RELAXABLE, {{cc,4}, {disps25,16}}} + + BRANCH_INST ("b", 0x1), + +/* Create a 'Branch if Equal to 0' instruction. */ +#define BRANCH_NEQ_INST(NAME, OPC) \ + /* opc8 disps5 r */ \ + {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}} + + BRANCH_NEQ_INST ("beq0b", 0x0C), + BRANCH_NEQ_INST ("bne0b", 0x0D), + BRANCH_NEQ_INST ("beq0w", 0x0E), + BRANCH_NEQ_INST ("bne0w", 0x0F), + + +/* Create an instruction using a single register operand. */ +#define REG1_INST(NAME, OPC) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} + +#define REGP1_INST(NAME, OPC) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS, {{regp,16}}} + +/* Same as REG1_INST, with additional FLAGS. */ +#define REG1_FLAG_INST(NAME, OPC, FLAGS) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regp,16}}} + + /* JCond instructions */ + REGP1_INST ("jeq", 0x0A0), + REGP1_INST ("jne", 0x0A1), + REGP1_INST ("jcs", 0x0A2), + REGP1_INST ("jcc", 0x0A3), + REGP1_INST ("jhi", 0x0A4), + REGP1_INST ("jls", 0x0A5), + REGP1_INST ("jgt", 0x0A6), + REGP1_INST ("jle", 0x0A7), + REGP1_INST ("jfs", 0x0A8), + REGP1_INST ("jfc", 0x0A9), + REGP1_INST ("jlo", 0x0AA), + REGP1_INST ("jhs", 0x0AB), + REGP1_INST ("jlt", 0x0AC), + REGP1_INST ("jge", 0x0AD), + REGP1_INST ("jump", 0x0AE), + REGP1_INST ("jusr", 0x0AF), + + /* SCond instructions */ + REG1_INST ("seq", 0x080), + REG1_INST ("sne", 0x081), + REG1_INST ("scs", 0x082), + REG1_INST ("scc", 0x083), + REG1_INST ("shi", 0x084), + REG1_INST ("sls", 0x085), + REG1_INST ("sgt", 0x086), + REG1_INST ("sle", 0x087), + REG1_INST ("sfs", 0x088), + REG1_INST ("sfc", 0x089), + REG1_INST ("slo", 0x08A), + REG1_INST ("shs", 0x08B), + REG1_INST ("slt", 0x08C), + REG1_INST ("sge", 0x08D), + + +/* Create an instruction using two register operands. */ +#define REG3_INST(NAME, OPC) \ + /* opc24 r r rp */ \ + {NAME, 2, OPC, 12, NO_TYPE_INS, {{regr,4}, {regr,0}, {regp,8}}} + + /* MULTIPLY INSTRUCTIONS */ + REG3_INST ("macqw", 0x0014d), + REG3_INST ("macuw", 0x0014e), + REG3_INST ("macsw", 0x0014f), + +/* Create a branch instruction. */ +#define BR_INST(NAME, OPC) \ + /* opc12 ra disps25 */ \ + {NAME, 2, OPC, 24, NO_TYPE_INS, {{rra,0}, {disps25,0}}} + +#define BR_INST_RP(NAME, OPC) \ + /* opc8 rp disps25 */ \ + {NAME, 3, OPC, 12, NO_TYPE_INS, {{regp,4}, {disps25,16}}} + + BR_INST ("bal", 0xC0), + BR_INST_RP ("bal", 0x00102), + +#define REGPP2_INST(NAME, OPC) \ + /* opc16 rp rp */ \ + {NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}} + /* Jump and link instructions. */ + REGP1_INST ("jal",0x00D), + REGPP2_INST ("jal",0x00148), + + +/* Instructions including a register list (opcode is represented as a mask). */ +#define REGLIST_INST(NAME, OPC, TYPE) \ + /* opc7 r count3 RA */ \ + {NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \ + /* opc8 r count3 */ \ + {NAME, 1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}}, \ + /* opc12 RA */ \ + {NAME, 1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}} + + REGLIST_INST ("push", 0x01, (NO_TYPE_INS | REG_LIST)), + REGLIST_INST ("pop", 0x02, (NO_TYPE_INS | REG_LIST)), + REGLIST_INST ("popret", 0x03, (NO_TYPE_INS | REG_LIST)), + + {"loadm", 1, 0x14, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"loadmp", 1, 0x15, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + + /* Processor Regsiter Manipulation instructions */ + /* opc16 reg, preg */ + {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}}, + /* opc16 regp, pregp */ + {"lprd", 2, 0x00141, 12, NO_TYPE_INS, {{regp,0}, {pregrp,4}}}, + /* opc16 preg, reg */ + {"spr", 2, 0x00142, 12, NO_TYPE_INS, {{pregr,4}, {regr,0}}}, + /* opc16 pregp, regp */ + {"sprd", 2, 0x00143, 12, NO_TYPE_INS, {{pregrp,4}, {regp,0}}}, + + /* Miscellaneous. */ + /* opc12 ui4 */ + {"excp", 1, 0x00C, 20, NO_TYPE_INS, {{uimm4,16}}}, + +/* Create a bit-b instruction. */ +#define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, (OPC3+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC3-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC3, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} + + CSTBIT_INST_B ("cbitb", uimm3, 0x68, 0x00104, 0xD6, 0x1AA), + CSTBIT_INST_B ("sbitb", uimm3, 0x70, 0x00108, 0xE6, 0x1CA), + CSTBIT_INST_B ("tbitb", uimm3, 0x78, 0x0010C, 0xF6, 0x1EA), + +/* Create a bit-w instruction. */ +#define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, OPC2+3, 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC3, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, OPC2+1, 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC2+2, 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} + + CSTBIT_INST_W ("cbitw", uimm4, 0x69, 0x00114, 0x36, 0x1AB), + CSTBIT_INST_W ("sbitw", uimm4, 0x71, 0x00118, 0x3A, 0x1CB), + CSTBIT_INST_W ("tbitw", uimm4, 0x79, 0x0011C, 0x3E, 0x1EB), + + /* tbit cnt */ + {"tbit", 1, 0x06, 24, CSTBIT_INS, {{uimm4,20}, {regr,16}}}, + /* tbit reg reg */ + {"tbit", 1, 0x07, 24, CSTBIT_INS, {{regr,20}, {regr,16}}}, + + +/* Load instructions (from memory to register). */ +#define LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D) \ + /* opc8 reg abs20 */ \ + {NAME, 2, OPC3, 24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}}, \ + /* opc20 reg abs24 */ \ + {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{abs24,16}, {OP_D,4}}}, \ + /* opc7 reg rindex8_abs20 */ \ + {NAME, 2, OPC5, 25, LD_STOR_INS, {{rindex8_abs20,0}, {OP_D,20}}}, \ + /* opc4 reg disps4(RPbase) */ \ + {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,24}, {OP_D,20}}}, \ + /* opcNN reg disps0(RPbase) */ \ + {NAME, 1, OPC2, 24, LD_STOR_INS, {{rpindex_disps0,0}, {OP_D,20}}}, \ + /* opc reg disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}}, \ + /* opc reg -disps20(Rbase) */ \ + {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{rbase_dispe20,16}, {OP_D,4}}}, \ + /* opc reg disps20(Rbase) */ \ + {NAME, 3, OPC1, 12, LD_STOR_INS, {{rbase_disps20,16}, {OP_D,4}}}, \ + /* opc reg (rp) disps16(RPbase) */ \ + {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{rpbase_disps16,0}, {OP_D,20}}}, \ + /* opc16 reg (rp) disps20(RPbase) */ \ + {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{rpbase_disps20,16}, {OP_D,4}}}, \ + /* op reg (rp) -disps20(RPbase) */ \ + {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{rpbase_dispe20,16}, {OP_D,4}}}, \ + /* opc reg rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, (OPC1+2), 12, LD_STOR_INS, {{rpindex_disps20,16}, {OP_D,4}}} + + LD_REG_INST ("loadb", 0x00124, 0xBE, 0x88, 0x219, 0x45, rpbase_disps4, regr), + LD_REG_INST ("loadd", 0x00128, 0xAE, 0x87, 0x21A, 0x46, rpbase_dispe4, regp), + LD_REG_INST ("loadw", 0x0012C, 0x9E, 0x89, 0x21B, 0x47, rpbase_dispe4, regr), + +/* Store instructions (from reg to memory). */ +#define ST_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_D, OP_S) \ + /* opc8 reg abs20 */ \ + {NAME, 2, OPC3, 24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}}, \ + /* opc20 reg abs24 */ \ + {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{OP_S,4}, {abs24,16}}}, \ + /* opc7 reg rindex8_abs20 */ \ + {NAME, 2, OPC5, 25, LD_STOR_INS, {{OP_S,20}, {rindex8_abs20,0}}}, \ + /* opc4 reg disps4(RPbase) */ \ + {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,20}, {OP_D,24}}}, \ + /* opcNN reg disps0(RPbase) */ \ + {NAME, 1, OPC2, 24, LD_STOR_INS, {{OP_S,20}, {rpindex_disps0,0}}}, \ + /* opc reg disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{OP_S,20}, {rpindex_disps14,0}}}, \ + /* opc reg -disps20(Rbase) */ \ + {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{OP_S,4}, {rbase_dispe20,16}}}, \ + /* opc reg disps20(Rbase) */ \ + {NAME, 3, OPC1, 12, LD_STOR_INS, {{OP_S,4}, {rbase_disps20,16}}}, \ + /* opc reg disps16(RPbase) */ \ + {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{OP_S,20}, {rpbase_disps16,0}}}, \ + /* opc16 reg disps20(RPbase) */ \ + {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_disps20,16}}}, \ + /* op reg (rp) -disps20(RPbase) */ \ + {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_dispe20,16}}}, \ + /* opc reg rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC1+2, 12, LD_STOR_INS, {{OP_S,4}, {rpindex_disps20,16}}} + + +/* Store instructions (from imm to memory). */ +#define ST_IMM_INST(NAME, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, OPC1, 24, LD_STOR_INS, {{uimm4,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, OPC2+3, 12, LD_STOR_INS, {{uimm4,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}} + + ST_REG_INST ("storb", 0x00134, 0xFE, 0xC8, 0x319, 0x65, rpbase_disps4, regr), + ST_IMM_INST ("storb", 0x81, 0x00120, 0x42, 0x218), + ST_REG_INST ("stord", 0x00138, 0xEE, 0xC7, 0x31A, 0x66, rpbase_dispe4, regp), + ST_REG_INST ("storw", 0x0013C, 0xDE, 0xC9, 0x31B, 0x67, rpbase_dispe4, regr), + ST_IMM_INST ("storw", 0xC1, 0x00130, 0x62, 0x318), + +/* Create instruction with no operands. */ +#define NO_OP_INST(NAME, OPC) \ + /* opc16 */ \ + {NAME, 1, OPC, 16, 0, {{0, 0}}} + + NO_OP_INST ("cinv[i]", 0x000A), + NO_OP_INST ("cinv[i,u]", 0x000B), + NO_OP_INST ("cinv[d]", 0x000C), + NO_OP_INST ("cinv[d,u]", 0x000D), + NO_OP_INST ("cinv[d,i]", 0x000E), + NO_OP_INST ("cinv[d,i,u]", 0x000F), + NO_OP_INST ("nop", 0x2C00), + NO_OP_INST ("retx", 0x0003), + NO_OP_INST ("di", 0x0004), + NO_OP_INST ("ei", 0x0005), + NO_OP_INST ("wait", 0x0006), + NO_OP_INST ("eiwait", 0x0007), + + {NULL, 0, 0, 0, 0, {{0, 0}}} +}; + +const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction); + +/* Macro to build a reg_entry, which have an opcode image : + For example : + REG(u4, 0x84, CR16_U_REGTYPE) + is interpreted as : + {"u4", u4, 0x84, CR16_U_REGTYPE} */ +#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} + +#define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE} + +const reg_entry cr16_regtab[] = +{ /* Build a general purpose register r. */ +#define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE) + + REG_R(0), REG_R(1), REG_R(2), REG_R(3), + REG_R(4), REG_R(5), REG_R(6), REG_R(7), + REG_R(8), REG_R(9), REG_R(10), REG_R(11), + REG_R(12), REG_R(13), REG_R(14), REG_R(15), + REG(r12_L, 12, CR16_R_REGTYPE), + REG(r13_L, 13, CR16_R_REGTYPE), + REG(ra, 0xe, CR16_R_REGTYPE), + REG(sp, 0xf, CR16_R_REGTYPE), + REG(sp_L, 0xf, CR16_R_REGTYPE), + REG(RA, 0xe, CR16_R_REGTYPE), +}; + +const reg_entry cr16_regptab[] = +{ /* Build a general purpose register r. */ + +#define REG_RP(M,N) REGP((CONCAT2(r,M),CONCAT2(r,N)), CONCAT2(r,N), N, CR16_RP_REGTYPE) + + REG_RP(1,0), REG_RP(2,1), REG_RP(3,2), REG_RP(4,3), + REG_RP(5,4), REG_RP(6,5), REG_RP(7,6), REG_RP(8,7), + REG_RP(9,8), REG_RP(10,9), REG_RP(11,10), REG_RP(12,11), + REG((r12), 0xc, CR16_RP_REGTYPE), + REG((r13), 0xd, CR16_RP_REGTYPE), + //REG((r14), 0xe, CR16_RP_REGTYPE), + REG((ra), 0xe, CR16_RP_REGTYPE), + REG((sp), 0xf, CR16_RP_REGTYPE), +}; + + +const unsigned int cr16_num_regs = ARRAY_SIZE (cr16_regtab) ; +const unsigned int cr16_num_regps = ARRAY_SIZE (cr16_regptab) ; + +const reg_entry cr16_pregtab[] = +{ +/* Build a processor register. */ + REG(dbs, 0x0, CR16_P_REGTYPE), + REG(dsr, 0x1, CR16_P_REGTYPE), + REG(dcrl, 0x2, CR16_P_REGTYPE), + REG(dcrh, 0x3, CR16_P_REGTYPE), + REG(car0l, 0x4, CR16_P_REGTYPE), + REG(car0h, 0x5, CR16_P_REGTYPE), + REG(car1l, 0x6, CR16_P_REGTYPE), + REG(car1h, 0x7, CR16_P_REGTYPE), + REG(cfg, 0x8, CR16_P_REGTYPE), + REG(psr, 0x9, CR16_P_REGTYPE), + REG(intbasel, 0xa, CR16_P_REGTYPE), + REG(intbaseh, 0xb, CR16_P_REGTYPE), + REG(ispl, 0xc, CR16_P_REGTYPE), + REG(isph, 0xd, CR16_P_REGTYPE), + REG(uspl, 0xe, CR16_P_REGTYPE), + REG(usph, 0xf, CR16_P_REGTYPE), +}; + +const reg_entry cr16_pregptab[] = +{ + REG(dbs, 0, CR16_P_REGTYPE), + REG(dsr, 1, CR16_P_REGTYPE), + REG(dcr, 2, CR16_P_REGTYPE), + REG(car0, 4, CR16_P_REGTYPE), + REG(car1, 6, CR16_P_REGTYPE), + REG(cfg, 8, CR16_P_REGTYPE), + REG(psr, 9, CR16_P_REGTYPE), + REG(intbase, 10, CR16_P_REGTYPE), + REG(isp, 12, CR16_P_REGTYPE), + REG(usp, 14, CR16_P_REGTYPE), +}; + +const unsigned int cr16_num_pregs = ARRAY_SIZE (cr16_pregtab); +const unsigned int cr16_num_pregps = ARRAY_SIZE (cr16_pregptab); + +const char *cr16_b_cond_tab[]= +{ + "eq","ne","cs","cc","hi","ls","gt","le","fs","fc", + "lo","hs","lt","ge","r", "???" +}; + +const unsigned int cr16_num_cc = ARRAY_SIZE (cr16_b_cond_tab); + +/* CR16 operands table. */ +const operand_entry cr16_optab[] = +{ + /* Index 0 is dummy, so we can count the instruction's operands. */ + {0, nullargs, 0}, /* dummy */ + {3, arg_ic, OP_SIGNED}, /* imm3 */ + {4, arg_ic, OP_SIGNED}, /* imm4 */ + {5, arg_ic, OP_SIGNED}, /* imm5 */ + {6, arg_ic, OP_SIGNED}, /* imm6 */ + {16, arg_ic, OP_SIGNED}, /* imm16 */ + {20, arg_ic, OP_SIGNED}, /* imm20 */ + {32, arg_ic, OP_SIGNED}, /* imm32 */ + {3, arg_ic, OP_UNSIGNED}, /* uimm3 */ + {3, arg_ic, OP_UNSIGNED|OP_DEC}, /* uimm3_1 */ + {4, arg_ic, OP_UNSIGNED}, /* uimm4 */ + {4, arg_ic, OP_UNSIGNED|OP_ESC}, /* uimm4_1 */ + {5, arg_ic, OP_UNSIGNED}, /* uimm5 */ + {16, arg_ic, OP_UNSIGNED}, /* uimm16 */ + {20, arg_ic, OP_UNSIGNED}, /* uimm20 */ + {32, arg_ic, OP_UNSIGNED}, /* uimm32 */ + {5, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_SIGNED}, /* disps5 */ + {16, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps17 */ + {24, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps25 */ + {8, arg_c, OP_EVEN|OP_UNSIGNED}, /* dispe9 */ + {20, arg_c, OP_UNSIGNED|OP_ABS20}, /* abs20 */ + {24, arg_c, OP_UNSIGNED|OP_ABS24}, /* abs24 */ + {4, arg_rp, 0}, /* rra */ + {4, arg_rbase, 0}, /* rbase */ + {20, arg_cr, OP_UNSIGNED}, /* rbase_disps20 */ + {21, arg_cr, OP_NEG}, /* rbase_dispe20 */ + {0, arg_crp, 0}, /* rpbase_disps0 */ + {4, arg_crp, OP_EVEN|OP_SHIFT|OP_UNSIGNED|OP_ESC1},/* rpbase_dispe4 */ + {4, arg_crp, OP_UNSIGNED|OP_ESC1}, /* rpbase_disps4 */ + {16, arg_crp, OP_UNSIGNED}, /* rpbase_disps16 */ + {20, arg_crp, OP_UNSIGNED}, /* rpbase_disps20 */ + {21, arg_crp, OP_NEG}, /* rpbase_dispe20 */ + {20, arg_idxr, OP_UNSIGNED}, /* rindex7_abs20 */ + {20, arg_idxr, OP_UNSIGNED}, /* rindex8_abs20 */ + {0, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps0 */ + {14, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps14 */ + {20, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps20 */ + {4, arg_r, 0}, /* regr */ + {4, arg_rp, 0}, /* reg pair */ + {4, arg_pr, 0}, /* proc reg */ + {4, arg_prp, 0}, /* 32 bit proc reg */ + {4, arg_cc, OP_UNSIGNED} /* cc - code */ +}; + +const unsigned int cr16_num_optab = ARRAY_SIZE (cr16_optab); + +/* CR16 traps/interrupts. */ +const trap_entry cr16_traps[] = +{ + {"svc", 5}, {"dvz", 6}, {"flg", 7}, {"bpt", 8}, {"trc", 9}, + {"und", 10}, {"iad", 12}, {"dbg",14}, {"ise",15} +}; + +const unsigned int cr16_num_traps = ARRAY_SIZE (cr16_traps); + +/* CR16 instructions that don't have arguments. */ +const char * cr16_no_op_insn[] = +{ + "cinv[i]", "cinv[i,u]", "cinv[d]", "cinv[d,u]", "cinv[d,i]", "cinv[d,i,u]", + "di", "ei", "eiwait", "nop", "retx", "wait", NULL +}; diff --git a/external/gpl3/gdb/dist/opcodes/cris-dis.c b/external/gpl3/gdb/dist/opcodes/cris-dis.c new file mode 100644 index 000000000000..01ada9d8f977 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cris-dis.c @@ -0,0 +1,1689 @@ +/* Disassembler code for CRIS. + Copyright 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009 + Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/cris.h" +#include "libiberty.h" + +/* No instruction will be disassembled longer than this. In theory, and + in silicon, address prefixes can be cascaded. In practice, cascading + is not used by GCC, and not supported by the assembler. */ +#ifndef MAX_BYTES_PER_CRIS_INSN +#define MAX_BYTES_PER_CRIS_INSN 8 +#endif + +/* Whether or not to decode prefixes, folding it into the following + instruction. FIXME: Make this optional later. */ +#ifndef PARSE_PREFIX +#define PARSE_PREFIX 1 +#endif + +/* Sometimes we prefix all registers with this character. */ +#define REGISTER_PREFIX_CHAR '$' + +/* Whether or not to trace the following sequence: + sub* X,r%d + bound* Y,r%d + adds.w [pc+r%d.w],pc + + This is the assembly form of a switch-statement in C. + The "sub is optional. If there is none, then X will be zero. + X is the value of the first case, + Y is the number of cases (including default). + + This results in case offsets printed on the form: + case N: -> case_address + where N is an estimation on the corresponding 'case' operand in C, + and case_address is where execution of that case continues after the + sequence presented above. + + The old style of output was to print the offsets as instructions, + which made it hard to follow "case"-constructs in the disassembly, + and caused a lot of annoying warnings about undefined instructions. + + FIXME: Make this optional later. */ +#ifndef TRACE_CASE +#define TRACE_CASE (disdata->trace_case) +#endif + +enum cris_disass_family + { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 }; + +/* Stored in the disasm_info->private_data member. */ +struct cris_disasm_data +{ + /* Whether to print something less confusing if we find something + matching a switch-construct. */ + bfd_boolean trace_case; + + /* Whether this code is flagged as crisv32. FIXME: Should be an enum + that includes "compatible". */ + enum cris_disass_family distype; +}; + +/* Value of first element in switch. */ +static long case_offset = 0; + +/* How many more case-offsets to print. */ +static long case_offset_counter = 0; + +/* Number of case offsets. */ +static long no_of_case_offsets = 0; + +/* Candidate for next case_offset. */ +static long last_immediate = 0; + +static int cris_constraint + (const char *, unsigned, unsigned, struct cris_disasm_data *); + +/* Parse disassembler options and store state in info. FIXME: For the + time being, we abuse static variables. */ + +static bfd_boolean +cris_parse_disassembler_options (disassemble_info *info, + enum cris_disass_family distype) +{ + struct cris_disasm_data *disdata; + + info->private_data = calloc (1, sizeof (struct cris_disasm_data)); + disdata = (struct cris_disasm_data *) info->private_data; + if (disdata == NULL) + return FALSE; + + /* Default true. */ + disdata->trace_case + = (info->disassembler_options == NULL + || (strcmp (info->disassembler_options, "nocase") != 0)); + + disdata->distype = distype; + return TRUE; +} + +static const struct cris_spec_reg * +spec_reg_info (unsigned int sreg, enum cris_disass_family distype) +{ + int i; + + for (i = 0; cris_spec_regs[i].name != NULL; i++) + { + if (cris_spec_regs[i].number == sreg) + { + if (distype == cris_dis_v32) + switch (cris_spec_regs[i].applicable_version) + { + case cris_ver_warning: + case cris_ver_version_all: + case cris_ver_v3p: + case cris_ver_v8p: + case cris_ver_v10p: + case cris_ver_v32p: + /* No ambiguous sizes or register names with CRISv32. */ + if (cris_spec_regs[i].warning == NULL) + return &cris_spec_regs[i]; + default: + ; + } + else if (cris_spec_regs[i].applicable_version != cris_ver_v32p) + return &cris_spec_regs[i]; + } + } + + return NULL; +} + +/* Return the number of bits in the argument. */ + +static int +number_of_bits (unsigned int val) +{ + int bits; + + for (bits = 0; val != 0; val &= val - 1) + bits++; + + return bits; +} + +/* Get an entry in the opcode-table. */ + +static const struct cris_opcode * +get_opcode_entry (unsigned int insn, + unsigned int prefix_insn, + struct cris_disasm_data *disdata) +{ + /* For non-prefixed insns, we keep a table of pointers, indexed by the + insn code. Each entry is initialized when found to be NULL. */ + static const struct cris_opcode **opc_table = NULL; + + const struct cris_opcode *max_matchedp = NULL; + const struct cris_opcode **prefix_opc_table = NULL; + + /* We hold a table for each prefix that need to be handled differently. */ + static const struct cris_opcode **dip_prefixes = NULL; + static const struct cris_opcode **bdapq_m1_prefixes = NULL; + static const struct cris_opcode **bdapq_m2_prefixes = NULL; + static const struct cris_opcode **bdapq_m4_prefixes = NULL; + static const struct cris_opcode **rest_prefixes = NULL; + + /* Allocate and clear the opcode-table. */ + if (opc_table == NULL) + { + opc_table = malloc (65536 * sizeof (opc_table[0])); + if (opc_table == NULL) + return NULL; + + memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *)); + + dip_prefixes + = malloc (65536 * sizeof (const struct cris_opcode **)); + if (dip_prefixes == NULL) + return NULL; + + memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0])); + + bdapq_m1_prefixes + = malloc (65536 * sizeof (const struct cris_opcode **)); + if (bdapq_m1_prefixes == NULL) + return NULL; + + memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0])); + + bdapq_m2_prefixes + = malloc (65536 * sizeof (const struct cris_opcode **)); + if (bdapq_m2_prefixes == NULL) + return NULL; + + memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0])); + + bdapq_m4_prefixes + = malloc (65536 * sizeof (const struct cris_opcode **)); + if (bdapq_m4_prefixes == NULL) + return NULL; + + memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0])); + + rest_prefixes + = malloc (65536 * sizeof (const struct cris_opcode **)); + if (rest_prefixes == NULL) + return NULL; + + memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0])); + } + + /* Get the right table if this is a prefix. + This code is connected to cris_constraints in that it knows what + prefixes play a role in recognition of patterns; the necessary + state is reflected by which table is used. If constraints + involving match or non-match of prefix insns are changed, then this + probably needs changing too. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + const struct cris_opcode *popcodep + = (opc_table[prefix_insn] != NULL + ? opc_table[prefix_insn] + : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); + + if (popcodep == NULL) + return NULL; + + if (popcodep->match == BDAP_QUICK_OPCODE) + { + /* Since some offsets are recognized with "push" macros, we + have to have different tables for them. */ + int offset = (prefix_insn & 255); + + if (offset > 127) + offset -= 256; + + switch (offset) + { + case -4: + prefix_opc_table = bdapq_m4_prefixes; + break; + + case -2: + prefix_opc_table = bdapq_m2_prefixes; + break; + + case -1: + prefix_opc_table = bdapq_m1_prefixes; + break; + + default: + prefix_opc_table = rest_prefixes; + break; + } + } + else if (popcodep->match == DIP_OPCODE) + /* We don't allow postincrement when the prefix is DIP, so use a + different table for DIP. */ + prefix_opc_table = dip_prefixes; + else + prefix_opc_table = rest_prefixes; + } + + if (prefix_insn != NO_CRIS_PREFIX + && prefix_opc_table[insn] != NULL) + max_matchedp = prefix_opc_table[insn]; + else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) + max_matchedp = opc_table[insn]; + else + { + const struct cris_opcode *opcodep; + int max_level_of_match = -1; + + for (opcodep = cris_opcodes; + opcodep->name != NULL; + opcodep++) + { + int level_of_match; + + if (disdata->distype == cris_dis_v32) + { + switch (opcodep->applicable_version) + { + case cris_ver_version_all: + break; + + case cris_ver_v0_3: + case cris_ver_v0_10: + case cris_ver_v3_10: + case cris_ver_sim_v0_10: + case cris_ver_v8_10: + case cris_ver_v10: + case cris_ver_warning: + continue; + + case cris_ver_v3p: + case cris_ver_v8p: + case cris_ver_v10p: + case cris_ver_v32p: + break; + + case cris_ver_v8: + abort (); + default: + abort (); + } + } + else + { + switch (opcodep->applicable_version) + { + case cris_ver_version_all: + case cris_ver_v0_3: + case cris_ver_v3p: + case cris_ver_v0_10: + case cris_ver_v8p: + case cris_ver_v8_10: + case cris_ver_v10: + case cris_ver_sim_v0_10: + case cris_ver_v10p: + case cris_ver_warning: + break; + + case cris_ver_v32p: + continue; + + case cris_ver_v8: + abort (); + default: + abort (); + } + } + + /* We give a double lead for bits matching the template in + cris_opcodes. Not even, because then "move p8,r10" would + be given 2 bits lead over "clear.d r10". When there's a + tie, the first entry in the table wins. This is + deliberate, to avoid a more complicated recognition + formula. */ + if ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0 + && ((level_of_match + = cris_constraint (opcodep->args, + insn, + prefix_insn, + disdata)) + >= 0) + && ((level_of_match + += 2 * number_of_bits (opcodep->match + | opcodep->lose)) + > max_level_of_match)) + { + max_matchedp = opcodep; + max_level_of_match = level_of_match; + + /* If there was a full match, never mind looking + further. */ + if (level_of_match >= 2 * 16) + break; + } + } + /* Fill in the new entry. + + If there are changes to the opcode-table involving prefixes, and + disassembly then does not work correctly, try removing the + else-clause below that fills in the prefix-table. If that + helps, you need to change the prefix_opc_table setting above, or + something related. */ + if (prefix_insn == NO_CRIS_PREFIX) + opc_table[insn] = max_matchedp; + else + prefix_opc_table[insn] = max_matchedp; + } + + return max_matchedp; +} + +/* Return -1 if the constraints of a bitwise-matched instruction say + that there is no match. Otherwise return a nonnegative number + indicating the confidence in the match (higher is better). */ + +static int +cris_constraint (const char *cs, + unsigned int insn, + unsigned int prefix_insn, + struct cris_disasm_data *disdata) +{ + int retval = 0; + int tmp; + int prefix_ok = 0; + const char *s; + + for (s = cs; *s; s++) + switch (*s) + { + case '!': + /* Do not recognize "pop" if there's a prefix and then only for + v0..v10. */ + if (prefix_insn != NO_CRIS_PREFIX + || disdata->distype != cris_dis_v0_v10) + return -1; + break; + + case 'U': + /* Not recognized at disassembly. */ + return -1; + + case 'M': + /* Size modifier for "clear", i.e. special register 0, 4 or 8. + Check that it is one of them. Only special register 12 could + be mismatched, but checking for matches is more logical than + checking for mismatches when there are only a few cases. */ + tmp = ((insn >> 12) & 0xf); + if (tmp != 0 && tmp != 4 && tmp != 8) + return -1; + break; + + case 'm': + if ((insn & 0x30) == 0x30) + return -1; + break; + + case 'S': + /* A prefix operand without side-effect. */ + if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) + { + prefix_ok = 1; + break; + } + else + return -1; + + case 's': + case 'y': + case 'Y': + /* If this is a prefixed insn with postincrement (side-effect), + the prefix must not be DIP. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + if (insn & 0x400) + { + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); + + if (prefix_opcodep->match == DIP_OPCODE) + return -1; + } + + prefix_ok = 1; + } + break; + + case 'B': + /* If we don't fall through, then the prefix is ok. */ + prefix_ok = 1; + + /* A "push" prefix. Check for valid "push" size. + In case of special register, it may be != 4. */ + if (prefix_insn != NO_CRIS_PREFIX) + { + /* Match the prefix insn to BDAPQ. */ + const struct cris_opcode *prefix_opcodep + = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); + + if (prefix_opcodep->match == BDAP_QUICK_OPCODE) + { + int pushsize = (prefix_insn & 255); + + if (pushsize > 127) + pushsize -= 256; + + if (s[1] == 'P') + { + unsigned int spec_reg = (insn >> 12) & 15; + const struct cris_spec_reg *sregp + = spec_reg_info (spec_reg, disdata->distype); + + /* For a special-register, the "prefix size" must + match the size of the register. */ + if (sregp && sregp->reg_size == (unsigned int) -pushsize) + break; + } + else if (s[1] == 'R') + { + if ((insn & 0x30) == 0x20 && pushsize == -4) + break; + } + /* FIXME: Should abort here; next constraint letter + *must* be 'P' or 'R'. */ + } + } + return -1; + + case 'D': + retval = (((insn >> 12) & 15) == (insn & 15)); + if (!retval) + return -1; + else + retval += 4; + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15, disdata->distype); + + /* Since we match four bits, we will give a value of 4-1 = 3 + in a match. If there is a corresponding exact match of a + special register in another pattern, it will get a value of + 4, which will be higher. This should be correct in that an + exact pattern would match better than a general pattern. + + Note that there is a reason for not returning zero; the + pattern for "clear" is partly matched in the bit-pattern + (the two lower bits must be zero), while the bit-pattern + for a move from a special register is matched in the + register constraint. */ + + if (sregp != NULL) + { + retval += 3; + break; + } + else + return -1; + } + } + + if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok) + return -1; + + return retval; +} + +/* Format number as hex with a leading "0x" into outbuffer. */ + +static char * +format_hex (unsigned long number, + char *outbuffer, + struct cris_disasm_data *disdata) +{ + /* Truncate negative numbers on >32-bit hosts. */ + number &= 0xffffffff; + + sprintf (outbuffer, "0x%lx", number); + + /* Save this value for the "case" support. */ + if (TRACE_CASE) + last_immediate = number; + + return outbuffer + strlen (outbuffer); +} + +/* Format number as decimal into outbuffer. Parameter signedp says + whether the number should be formatted as signed (!= 0) or + unsigned (== 0). */ + +static char * +format_dec (long number, char *outbuffer, int signedp) +{ + last_immediate = number; + if (signedp) + sprintf (outbuffer, "%ld", number); + else + sprintf (outbuffer, "%lu", (unsigned long) number); + + return outbuffer + strlen (outbuffer); +} + +/* Format the name of the general register regno into outbuffer. */ + +static char * +format_reg (struct cris_disasm_data *disdata, + int regno, + char *outbuffer_start, + bfd_boolean with_reg_prefix) +{ + char *outbuffer = outbuffer_start; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + switch (regno) + { + case 15: + /* For v32, there is no context in which we output PC. */ + if (disdata->distype == cris_dis_v32) + strcpy (outbuffer, "acr"); + else + strcpy (outbuffer, "pc"); + break; + + case 14: + strcpy (outbuffer, "sp"); + break; + + default: + sprintf (outbuffer, "r%d", regno); + break; + } + + return outbuffer_start + strlen (outbuffer_start); +} + +/* Format the name of a support register into outbuffer. */ + +static char * +format_sup_reg (unsigned int regno, + char *outbuffer_start, + bfd_boolean with_reg_prefix) +{ + char *outbuffer = outbuffer_start; + int i; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + for (i = 0; cris_support_regs[i].name != NULL; i++) + if (cris_support_regs[i].number == regno) + { + sprintf (outbuffer, "%s", cris_support_regs[i].name); + return outbuffer_start + strlen (outbuffer_start); + } + + /* There's supposed to be register names covering all numbers, though + some may be generic names. */ + sprintf (outbuffer, "format_sup_reg-BUG"); + return outbuffer_start + strlen (outbuffer_start); +} + +/* Return the length of an instruction. */ + +static unsigned +bytes_to_skip (unsigned int insn, + const struct cris_opcode *matchedp, + enum cris_disass_family distype, + const struct cris_opcode *prefix_matchedp) +{ + /* Each insn is a word plus "immediate" operands. */ + unsigned to_skip = 2; + const char *template_name = (const char *) matchedp->args; + const char *s; + + for (s = template_name; *s; s++) + if ((*s == 's' || *s == 'N' || *s == 'Y') + && (insn & 0x400) && (insn & 15) == 15 + && prefix_matchedp == NULL) + { + /* Immediate via [pc+], so we have to check the size of the + operand. */ + int mode_size = 1 << ((insn >> 4) & (*template_name == 'z' ? 1 : 3)); + + if (matchedp->imm_oprnd_size == SIZE_FIX_32) + to_skip += 4; + else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15, distype); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + return 2; + + /* PC is incremented by two, not one, for a byte. Except on + CRISv32, where constants are always DWORD-size for + special registers. */ + to_skip += + distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; + } + else + to_skip += (mode_size + 1) & ~1; + } + else if (*s == 'n') + to_skip += 4; + else if (*s == 'b') + to_skip += 2; + + return to_skip; +} + +/* Print condition code flags. */ + +static char * +print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) +{ + /* Use the v8 (Etrax 100) flag definitions for disassembly. + The differences with v0 (Etrax 1..4) vs. Svinto are: + v0 'd' <=> v8 'm' + v0 'e' <=> v8 'b'. + FIXME: Emit v0..v3 flag names somehow. */ + static const char v8_fnames[] = "cvznxibm"; + static const char v32_fnames[] = "cvznxiup"; + const char *fnames + = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames; + + unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); + int i; + + for (i = 0; i < 8; i++) + if (flagbits & (1 << i)) + *cp++ = fnames[i]; + + return cp; +} + +/* Print out an insn with its operands, and update the info->insn_type + fields. The prefix_opcodep and the rest hold a prefix insn that is + supposed to be output as an address mode. */ + +static void +print_with_operands (const struct cris_opcode *opcodep, + unsigned int insn, + unsigned char *buffer, + bfd_vma addr, + disassemble_info *info, + /* If a prefix insn was before this insn (and is supposed + to be output as an address), here is a description of + it. */ + const struct cris_opcode *prefix_opcodep, + unsigned int prefix_insn, + unsigned char *prefix_buffer, + bfd_boolean with_reg_prefix) +{ + /* Get a buffer of somewhat reasonable size where we store + intermediate parts of the insn. */ + char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; + char *tp = temp; + static const char mode_char[] = "bwd?"; + const char *s; + const char *cs; + struct cris_disasm_data *disdata + = (struct cris_disasm_data *) info->private_data; + + /* Print out the name first thing we do. */ + (*info->fprintf_func) (info->stream, "%s", opcodep->name); + + cs = opcodep->args; + s = cs; + + /* Ignore any prefix indicator. */ + if (*s == 'p') + s++; + + if (*s == 'm' || *s == 'M' || *s == 'z') + { + *tp++ = '.'; + + /* Get the size-letter. */ + *tp++ = *s == 'M' + ? (insn & 0x8000 ? 'd' + : insn & 0x4000 ? 'w' : 'b') + : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; + + /* Ignore the size and the space character that follows. */ + s += 2; + } + + /* Add a space if this isn't a long-branch, because for those will add + the condition part of the name later. */ + if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) + *tp++ = ' '; + + /* Fill in the insn-type if deducible from the name (and there's no + better way). */ + if (opcodep->name[0] == 'j') + { + if (CONST_STRNEQ (opcodep->name, "jsr")) + /* It's "jsr" or "jsrc". */ + info->insn_type = dis_jsr; + else + /* Any other jump-type insn is considered a branch. */ + info->insn_type = dis_branch; + } + + /* We might know some more fields right now. */ + info->branch_delay_insns = opcodep->delayed; + + /* Handle operands. */ + for (; *s; s++) + { + switch (*s) + { + case 'T': + tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); + break; + + case 'A': + if (with_reg_prefix) + *tp++ = REGISTER_PREFIX_CHAR; + *tp++ = 'a'; + *tp++ = 'c'; + *tp++ = 'r'; + break; + + case '[': + case ']': + case ',': + *tp++ = *s; + break; + + case '!': + /* Ignore at this point; used at earlier stages to avoid + recognition if there's a prefix at something that in other + ways looks like a "pop". */ + break; + + case 'd': + /* Ignore. This is an optional ".d " on the large one of + relaxable insns. */ + break; + + case 'B': + /* This was the prefix that made this a "push". We've already + handled it by recognizing it, so signal that the prefix is + handled by setting it to NULL. */ + prefix_opcodep = NULL; + break; + + case 'D': + case 'r': + tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); + break; + + case 'R': + tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); + break; + + case 'n': + { + /* Like N but pc-relative to the start of the insn. */ + unsigned long number + = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000 + addr); + + /* Finish off and output previous formatted bytes. */ + *tp = 0; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + tp = temp; + + (*info->print_address_func) ((bfd_vma) number, info); + } + break; + + case 'u': + { + /* Like n but the offset is bits <3:0> in the instruction. */ + unsigned long number = (buffer[0] & 0xf) * 2 + addr; + + /* Finish off and output previous formatted bytes. */ + *tp = 0; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + tp = temp; + + (*info->print_address_func) ((bfd_vma) number, info); + } + break; + + case 'N': + case 'y': + case 'Y': + case 'S': + case 's': + /* Any "normal" memory operand. */ + if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL) + { + /* We're looking at [pc+], i.e. we need to output an immediate + number, where the size can depend on different things. */ + long number; + int signedp + = ((*cs == 'z' && (insn & 0x20)) + || opcodep->match == BDAP_QUICK_OPCODE); + int nbytes; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + nbytes = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15, disdata->distype); + + /* A NULL return should have been as a non-match earlier, + so catch it as an internal error in the error-case + below. */ + if (sregp == NULL) + /* Whatever non-valid size. */ + nbytes = 42; + else + /* PC is always incremented by a multiple of two. + For CRISv32, immediates are always 4 bytes for + special registers. */ + nbytes = disdata->distype == cris_dis_v32 + ? 4 : (sregp->reg_size + 1) & ~1; + } + else + { + int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + } + + switch (nbytes) + { + case 1: + number = buffer[2]; + if (signedp && number > 127) + number -= 256; + break; + + case 2: + number = buffer[2] + buffer[3] * 256; + if (signedp && number > 32767) + number -= 65536; + break; + + case 4: + number + = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + if ((*cs == 'z' && (insn & 0x20)) + || (opcodep->match == BDAP_QUICK_OPCODE + && (nbytes <= 2 || buffer[1 + nbytes] == 0))) + tp = format_dec (number, tp, signedp); + else + { + unsigned int highbyte = (number >> 24) & 0xff; + + /* Either output this as an address or as a number. If it's + a dword with the same high-byte as the address of the + insn, assume it's an address, and also if it's a non-zero + non-0xff high-byte. If this is a jsr or a jump, then + it's definitely an address. */ + if (nbytes == 4 + && (highbyte == ((addr >> 24) & 0xff) + || (highbyte != 0 && highbyte != 0xff) + || info->insn_type == dis_branch + || info->insn_type == dis_jsr)) + { + /* Finish off and output previous formatted bytes. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + + info->target = number; + } + else + tp = format_hex (number, tp, disdata); + } + } + else + { + /* Not an immediate number. Then this is a (possibly + prefixed) memory operand. */ + if (info->insn_type != dis_nonbranch) + { + int mode_size + = 1 << ((insn >> 4) + & (opcodep->args[0] == 'z' ? 1 : 3)); + int size; + info->insn_type = dis_dref; + info->flags |= CRIS_DIS_FLAG_MEMREF; + + if (opcodep->imm_oprnd_size == SIZE_FIX_32) + size = 4; + else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15, disdata->distype); + + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp == NULL) + size = 4; + else + size = sregp->reg_size; + } + else + size = mode_size; + + info->data_size = size; + } + + *tp++ = '['; + + if (prefix_opcodep + /* We don't match dip with a postincremented field + as a side-effect address mode. */ + && ((insn & 0x400) == 0 + || prefix_opcodep->match != DIP_OPCODE)) + { + if (insn & 0x400) + { + tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); + *tp++ = '='; + } + + + /* We mainly ignore the prefix format string when the + address-mode syntax is output. */ + switch (prefix_opcodep->match) + { + case DIP_OPCODE: + /* It's [r], [r+] or [pc+]. */ + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + /* It's [pc+]. This cannot possibly be anything + but an address. */ + unsigned long number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + + info->target = (bfd_vma) number; + + /* Finish off and output previous formatted + data. */ + *tp = 0; + tp = temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + /* For a memref in an address, we use target2. + In this case, target is zero. */ + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM); + + info->target2 = prefix_insn & 15; + + *tp++ = '['; + tp = format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + } + break; + + case BDAP_QUICK_OPCODE: + { + int number; + + number = prefix_buffer[0]; + if (number > 127) + number -= 256; + + /* Output "reg+num" or, if num < 0, "reg-num". */ + tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, + with_reg_prefix); + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = (prefix_insn >> 12) & 15; + info->target2 = (bfd_vma) number; + break; + } + + case BIAP_OPCODE: + /* Output "r+R.m". */ + tp = format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + *tp++ = '+'; + tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, + with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 + : ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); + + /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */ + if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) + /* Then start interpreting data as offsets. */ + case_offset_counter = no_of_case_offsets; + break; + + case BDAP_INDIR_OPCODE: + /* Output "r+s.m", or, if "s" is [pc+], "r+s" or + "r-s". */ + tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, + with_reg_prefix); + + if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) + { + long number; + unsigned int nbytes; + + /* It's a value. Get its size. */ + int mode_size = 1 << ((prefix_insn >> 4) & 3); + + if (mode_size == 1) + nbytes = 2; + else + nbytes = mode_size; + + switch (nbytes) + { + case 1: + number = prefix_buffer[2]; + if (number > 127) + number -= 256; + break; + + case 2: + number = prefix_buffer[2] + prefix_buffer[3] * 256; + if (number > 32767) + number -= 65536; + break; + + case 4: + number + = prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + break; + + default: + strcpy (tp, "bug"); + tp += 3; + number = 42; + } + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target2 = (bfd_vma) number; + + /* If the size is dword, then assume it's an + address. */ + if (nbytes == 4) + { + /* Finish off and output previous formatted + bytes. */ + *tp++ = '+'; + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + + (*info->print_address_func) ((bfd_vma) number, info); + } + else + { + if (number >= 0) + *tp++ = '+'; + tp = format_dec (number, tp, 1); + } + } + else + { + /* Output "r+[R].m" or "r+[R+].m". */ + *tp++ = '+'; + *tp++ = '['; + tp = format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ = '+'; + *tp++ = ']'; + *tp++ = '.'; + *tp++ = mode_char[(prefix_insn >> 4) & 3]; + + info->flags + |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + + | (((prefix_insn >> 4) == 2) + ? 0 + : (((prefix_insn >> 4) & 3) == 1 + ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD + : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); + } + break; + + default: + (*info->fprintf_func) (info->stream, "?prefix-bug"); + } + + /* To mark that the prefix is used, reset it. */ + prefix_opcodep = NULL; + } + else + { + tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); + + info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target = insn & 15; + + if (insn & 0x400) + *tp++ = '+'; + } + *tp++ = ']'; + } + break; + + case 'x': + tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); + *tp++ = '.'; + *tp++ = mode_char[(insn >> 4) & 3]; + break; + + case 'I': + tp = format_dec (insn & 63, tp, 0); + break; + + case 'b': + { + int where = buffer[2] + buffer[3] * 256; + + if (where > 32767) + where -= 65536; + + where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4); + + if (insn == BA_PC_INCR_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + info->target = (bfd_vma) where; + + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s%s ", + temp, cris_cc_strings[insn >> 12]); + + (*info->print_address_func) ((bfd_vma) where, info); + } + break; + + case 'c': + tp = format_dec (insn & 31, tp, 0); + break; + + case 'C': + tp = format_dec (insn & 15, tp, 0); + break; + + case 'o': + { + long offset = insn & 0xfe; + bfd_vma target; + + if (insn & 1) + offset |= ~0xff; + + if (opcodep->match == BA_QUICK_OPCODE) + info->insn_type = dis_branch; + else + info->insn_type = dis_condbranch; + + target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset; + info->target = target; + *tp = 0; + tp = temp; + (*info->fprintf_func) (info->stream, "%s", temp); + (*info->print_address_func) (target, info); + } + break; + + case 'Q': + case 'O': + { + long number = buffer[0]; + + if (number > 127) + number = number - 256; + + tp = format_dec (number, tp, 1); + *tp++ = ','; + tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); + } + break; + + case 'f': + tp = print_flags (disdata, insn, tp); + break; + + case 'i': + tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1); + break; + + case 'P': + { + const struct cris_spec_reg *sregp + = spec_reg_info ((insn >> 12) & 15, disdata->distype); + + if (sregp->name == NULL) + /* Should have been caught as a non-match eariler. */ + *tp++ = '?'; + else + { + if (with_reg_prefix) + *tp++ = REGISTER_PREFIX_CHAR; + strcpy (tp, sregp->name); + tp += strlen (tp); + } + } + break; + + default: + strcpy (tp, "???"); + tp += 3; + } + } + + *tp = 0; + + if (prefix_opcodep) + (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")", + prefix_opcodep->name, prefix_opcodep->args); + + (*info->fprintf_func) (info->stream, "%s", temp); + + /* Get info for matching case-tables, if we don't have any active. + We assume that the last constant seen is used; either in the insn + itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */ + if (TRACE_CASE && case_offset_counter == 0) + { + if (CONST_STRNEQ (opcodep->name, "sub")) + case_offset = last_immediate; + + /* It could also be an "add", if there are negative case-values. */ + else if (CONST_STRNEQ (opcodep->name, "add")) + /* The first case is the negated operand to the add. */ + case_offset = -last_immediate; + + /* A bound insn will tell us the number of cases. */ + else if (CONST_STRNEQ (opcodep->name, "bound")) + no_of_case_offsets = last_immediate + 1; + + /* A jump or jsr or branch breaks the chain of insns for a + case-table, so assume default first-case again. */ + else if (info->insn_type == dis_jsr + || info->insn_type == dis_branch + || info->insn_type == dis_condbranch) + case_offset = 0; + } +} + + +/* Print the CRIS instruction at address memaddr on stream. Returns + length of the instruction, in bytes. Prefix register names with `$' if + WITH_REG_PREFIX. */ + +static int +print_insn_cris_generic (bfd_vma memaddr, + disassemble_info *info, + bfd_boolean with_reg_prefix) +{ + int nbytes; + unsigned int insn; + const struct cris_opcode *matchedp; + int advance = 0; + struct cris_disasm_data *disdata + = (struct cris_disasm_data *) info->private_data; + + /* No instruction will be disassembled as longer than this number of + bytes; stacked prefixes will not be expanded. */ + unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; + unsigned char *bufp; + int status = 0; + bfd_vma addr; + + /* There will be an "out of range" error after the last instruction. + Reading pairs of bytes in decreasing number, we hope that we will get + at least the amount that we will consume. + + If we can't get any data, or we do not get enough data, we print + the error message. */ + + for (nbytes = MAX_BYTES_PER_CRIS_INSN; nbytes > 0; nbytes -= 2) + { + status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); + if (status == 0) + break; + } + + /* If we did not get all we asked for, then clear the rest. + Hopefully this makes a reproducible result in case of errors. */ + if (nbytes != MAX_BYTES_PER_CRIS_INSN) + memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes); + + addr = memaddr; + bufp = buffer; + + /* Set some defaults for the insn info. */ + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->flags = 0; + info->target = 0; + info->target2 = 0; + + /* If we got any data, disassemble it. */ + if (nbytes != 0) + { + matchedp = NULL; + + insn = bufp[0] + bufp[1] * 256; + + /* If we're in a case-table, don't disassemble the offsets. */ + if (TRACE_CASE && case_offset_counter != 0) + { + info->insn_type = dis_noninsn; + advance += 2; + + /* If to print data as offsets, then shortcut here. */ + (*info->fprintf_func) (info->stream, "case %ld%s: -> ", + case_offset + no_of_case_offsets + - case_offset_counter, + case_offset_counter == 1 ? "/default" : + ""); + + (*info->print_address_func) ((bfd_vma) + ((short) (insn) + + (long) (addr + - (no_of_case_offsets + - case_offset_counter) + * 2)), info); + case_offset_counter--; + + /* The default case start (without a "sub" or "add") must be + zero. */ + if (case_offset_counter == 0) + case_offset = 0; + } + else if (insn == 0) + { + /* We're often called to disassemble zeroes. While this is a + valid "bcc .+2" insn, it is also useless enough and enough + of a nuiscance that we will just output "bcc .+2" for it + and signal it as a noninsn. */ + (*info->fprintf_func) (info->stream, + disdata->distype == cris_dis_v32 + ? "bcc ." : "bcc .+2"); + info->insn_type = dis_noninsn; + advance += 2; + } + else + { + const struct cris_opcode *prefix_opcodep = NULL; + unsigned char *prefix_buffer = bufp; + unsigned int prefix_insn = insn; + int prefix_size = 0; + + matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); + + /* Check if we're supposed to write out prefixes as address + modes and if this was a prefix. */ + if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') + { + /* If it's a prefix, put it into the prefix vars and get the + main insn. */ + prefix_size = bytes_to_skip (prefix_insn, matchedp, + disdata->distype, NULL); + prefix_opcodep = matchedp; + + insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; + matchedp = get_opcode_entry (insn, prefix_insn, disdata); + + if (matchedp != NULL) + { + addr += prefix_size; + bufp += prefix_size; + advance += prefix_size; + } + else + { + /* The "main" insn wasn't valid, at least not when + prefixed. Put back things enough to output the + prefix insn only, as a normal insn. */ + matchedp = prefix_opcodep; + insn = prefix_insn; + prefix_opcodep = NULL; + } + } + + if (matchedp == NULL) + { + (*info->fprintf_func) (info->stream, "??0x%x", insn); + advance += 2; + + info->insn_type = dis_noninsn; + } + else + { + advance + += bytes_to_skip (insn, matchedp, disdata->distype, + prefix_opcodep); + + /* The info_type and assorted fields will be set according + to the operands. */ + print_with_operands (matchedp, insn, bufp, addr, info, + prefix_opcodep, prefix_insn, + prefix_buffer, with_reg_prefix); + } + } + } + else + info->insn_type = dis_noninsn; + + /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error + status when reading that much, and the insn decoding indicated a + length exceeding what we read, there is an error. */ + if (status != 0 && (nbytes == 0 || advance > nbytes)) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Max supported insn size with one folded prefix insn. */ + info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; + + /* I would like to set this to a fixed value larger than the actual + number of bytes to print in order to avoid spaces between bytes, + but objdump.c (2.9.1) does not like that, so we print 16-bit + chunks, which is the next choice. */ + info->bytes_per_chunk = 2; + + /* Printing bytes in order of increasing addresses makes sense, + especially on a little-endian target. + This is completely the opposite of what you think; setting this to + BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N + we want. */ + info->display_endian = BFD_ENDIAN_BIG; + + return advance; +} + +/* Disassemble, prefixing register names with `$'. CRIS v0..v10. */ + +static int +print_insn_cris_with_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) + return -1; + return print_insn_cris_generic (vma, info, TRUE); +} + +/* Disassemble, prefixing register names with `$'. CRIS v32. */ + +static int +print_insn_crisv32_with_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_v32)) + return -1; + return print_insn_cris_generic (vma, info, TRUE); +} + +/* Disassemble, prefixing register names with `$'. + Common v10 and v32 subset. */ + +static int +print_insn_crisv10_v32_with_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) + return -1; + return print_insn_cris_generic (vma, info, TRUE); +} + +/* Disassemble, no prefixes on register names. CRIS v0..v10. */ + +static int +print_insn_cris_without_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) + return -1; + return print_insn_cris_generic (vma, info, FALSE); +} + +/* Disassemble, no prefixes on register names. CRIS v32. */ + +static int +print_insn_crisv32_without_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_v32)) + return -1; + return print_insn_cris_generic (vma, info, FALSE); +} + +/* Disassemble, no prefixes on register names. + Common v10 and v32 subset. */ + +static int +print_insn_crisv10_v32_without_register_prefix (bfd_vma vma, + disassemble_info *info) +{ + if (info->private_data == NULL + && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) + return -1; + return print_insn_cris_generic (vma, info, FALSE); +} + +/* Return a disassembler-function that prints registers with a `$' prefix, + or one that prints registers without a prefix. + FIXME: We should improve the solution to avoid the multitude of + functions seen above. */ + +disassembler_ftype +cris_get_disassembler (bfd *abfd) +{ + /* If there's no bfd in sight, we return what is valid as input in all + contexts if fed back to the assembler: disassembly *with* register + prefix. Unfortunately this will be totally wrong for v32. */ + if (abfd == NULL) + return print_insn_cris_with_register_prefix; + + if (bfd_get_symbol_leading_char (abfd) == 0) + { + if (bfd_get_mach (abfd) == bfd_mach_cris_v32) + return print_insn_crisv32_with_register_prefix; + if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32) + return print_insn_crisv10_v32_with_register_prefix; + + /* We default to v10. This may be specifically specified in the + bfd mach, but is also the default setting. */ + return print_insn_cris_with_register_prefix; + } + + if (bfd_get_mach (abfd) == bfd_mach_cris_v32) + return print_insn_crisv32_without_register_prefix; + if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32) + return print_insn_crisv10_v32_without_register_prefix; + return print_insn_cris_without_register_prefix; +} + +/* Local variables: + eval: (c-set-style "gnu") + indent-tabs-mode: t + End: */ diff --git a/external/gpl3/gdb/dist/opcodes/cris-opc.c b/external/gpl3/gdb/dist/opcodes/cris-opc.c new file mode 100644 index 000000000000..341c31bfa11f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/cris-opc.c @@ -0,0 +1,1209 @@ +/* cris-opc.c -- Table of opcodes for the CRIS processor. + Copyright 2000, 2001, 2004, 2005, 2007 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Reorganized by Hans-Peter Nilsson. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "opcode/cris.h" + +#ifndef NULL +#define NULL (0) +#endif + +/* This table isn't used for CRISv32 and the size of immediate operands. */ +const struct cris_spec_reg +cris_spec_regs[] = +{ + {"bz", 0, 1, cris_ver_v32p, NULL}, + {"p0", 0, 1, 0, NULL}, + {"vr", 1, 1, 0, NULL}, + {"p1", 1, 1, 0, NULL}, + {"pid", 2, 1, cris_ver_v32p, NULL}, + {"p2", 2, 1, cris_ver_v32p, NULL}, + {"p2", 2, 1, cris_ver_warning, NULL}, + {"srs", 3, 1, cris_ver_v32p, NULL}, + {"p3", 3, 1, cris_ver_v32p, NULL}, + {"p3", 3, 1, cris_ver_warning, NULL}, + {"wz", 4, 2, cris_ver_v32p, NULL}, + {"p4", 4, 2, 0, NULL}, + {"ccr", 5, 2, cris_ver_v0_10, NULL}, + {"exs", 5, 4, cris_ver_v32p, NULL}, + {"p5", 5, 2, cris_ver_v0_10, NULL}, + {"p5", 5, 4, cris_ver_v32p, NULL}, + {"dcr0",6, 2, cris_ver_v0_3, NULL}, + {"eda", 6, 4, cris_ver_v32p, NULL}, + {"p6", 6, 2, cris_ver_v0_3, NULL}, + {"p6", 6, 4, cris_ver_v32p, NULL}, + {"dcr1/mof", 7, 4, cris_ver_v10p, + "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, + {"dcr1/mof", 7, 2, cris_ver_v0_3, + "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, + {"mof", 7, 4, cris_ver_v10p, NULL}, + {"dcr1",7, 2, cris_ver_v0_3, NULL}, + {"p7", 7, 4, cris_ver_v10p, NULL}, + {"p7", 7, 2, cris_ver_v0_3, NULL}, + {"dz", 8, 4, cris_ver_v32p, NULL}, + {"p8", 8, 4, 0, NULL}, + {"ibr", 9, 4, cris_ver_v0_10, NULL}, + {"ebp", 9, 4, cris_ver_v32p, NULL}, + {"p9", 9, 4, 0, NULL}, + {"irp", 10, 4, cris_ver_v0_10, NULL}, + {"erp", 10, 4, cris_ver_v32p, NULL}, + {"p10", 10, 4, 0, NULL}, + {"srp", 11, 4, 0, NULL}, + {"p11", 11, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"bar/dtp0", 12, 4, cris_ver_warning, + "Ambiguous register `bar/dtp0' specified"}, + {"nrp", 12, 4, cris_ver_v32p, NULL}, + {"bar", 12, 4, cris_ver_v8_10, NULL}, + {"dtp0",12, 4, cris_ver_v0_3, NULL}, + {"p12", 12, 4, 0, NULL}, + /* For disassembly use only. Accept at assembly with a warning. */ + {"dccr/dtp1",13, 4, cris_ver_warning, + "Ambiguous register `dccr/dtp1' specified"}, + {"ccs", 13, 4, cris_ver_v32p, NULL}, + {"dccr",13, 4, cris_ver_v8_10, NULL}, + {"dtp1",13, 4, cris_ver_v0_3, NULL}, + {"p13", 13, 4, 0, NULL}, + {"brp", 14, 4, cris_ver_v3_10, NULL}, + {"usp", 14, 4, cris_ver_v32p, NULL}, + {"p14", 14, 4, cris_ver_v3p, NULL}, + {"usp", 15, 4, cris_ver_v10, NULL}, + {"spc", 15, 4, cris_ver_v32p, NULL}, + {"p15", 15, 4, cris_ver_v10p, NULL}, + {NULL, 0, 0, cris_ver_version_all, NULL} +}; + +/* Add version specifiers to this table when necessary. + The (now) regular coding of register names suggests a simpler + implementation. */ +const struct cris_support_reg cris_support_regs[] = +{ + {"s0", 0}, + {"s1", 1}, + {"s2", 2}, + {"s3", 3}, + {"s4", 4}, + {"s5", 5}, + {"s6", 6}, + {"s7", 7}, + {"s8", 8}, + {"s9", 9}, + {"s10", 10}, + {"s11", 11}, + {"s12", 12}, + {"s13", 13}, + {"s14", 14}, + {"s15", 15}, + {NULL, 0} +}; + +/* All CRIS opcodes are 16 bits. + + - The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + - The args component is a string containing characters symbolically + matching the operands of an instruction. Used for both assembly + and disassembly. + + Operand-matching characters: + [ ] , space + Verbatim. + A The string "ACR" (case-insensitive). + B Not really an operand. It causes a "BDAP -size,SP" prefix to be + output for the PUSH alias-instructions and recognizes a push- + prefix at disassembly. This letter isn't recognized for v32. + Must be followed by a R or P letter. + ! Non-match pattern, will not match if there's a prefix insn. + b Non-matching operand, used for branches with 16-bit + displacement. Only recognized by the disassembler. + c 5-bit unsigned immediate in bits <4:0>. + C 4-bit unsigned immediate in bits <3:0>. + d At assembly, optionally (as in put other cases before this one) + ".d" or ".D" at the start of the operands, followed by one space + character. At disassembly, nothing. + D General register in bits <15:12> and <3:0>. + f List of flags in bits <15:12> and <3:0>. + i 6-bit signed immediate in bits <5:0>. + I 6-bit unsigned immediate in bits <5:0>. + M Size modifier (B, W or D) for CLEAR instructions. + m Size modifier (B, W or D) in bits <5:4> + N A 32-bit dword, like in the difference between s and y. + This has no effect on bits in the opcode. Can also be expressed + as "[pc+]" in input. + n As N, but PC-relative (to the start of the instruction). + o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit + branch instructions. + O [-128..127] offset in bits <7:0>. Also matches a comma and a + general register after the expression, in bits <15:12>. Used + only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode). + P Special register in bits <15:12>. + p Indicates that the insn is a prefix insn. Must be first + character. + Q As O, but don't relax; force an 8-bit offset. + R General register in bits <15:12>. + r General register in bits <3:0>. + S Source operand in bit <10> and a prefix; a 3-operand prefix + without side-effect. + s Source operand in bits <10> and <3:0>, optionally with a + side-effect prefix, except [pc] (the name, not R15 as in ACR) + isn't allowed for v32 and higher. + T Support register in bits <15:12>. + u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>. + U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC. + Not recognized at disassembly. + x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. + y Like 's' but do not allow an integer at assembly. + Y The difference s-y; only an integer is allowed. + z Size modifier (B or W) in bit <4>. */ + + +/* Please note the order of the opcodes in this table is significant. + The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler might not recognize + them, or may indicate an internal error. + + The disassembler should not normally care about the order of the + opcodes, but will prefer an earlier alternative if the "match-score" + (see cris-dis.c) is computed as equal. + + It should not be significant for proper execution that this table is + in alphabetical order, but please follow that convention for an easy + overview. */ + +const struct cris_opcode +cris_opcodes[] = +{ + {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, + cris_abs_op}, + + {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, + cris_ver_v32p, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_not_implemented_op}, + + {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_not_implemented_op}, + + {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, + cris_ver_v32p, + cris_addi_op}, + + {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, + cris_addi_op}, + + /* This collates after "addo", but we want to disassemble as "addoq", + not "addo". */ + {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, + cris_ver_v32p, + cris_not_implemented_op}, + + /* This must be located after the insn above, lest we misinterpret + "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a + parser bug. */ + {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ + {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, + cris_asr_op}, + + {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, + cris_asrq_op}, + + {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + /* FIXME: Should use branch #defines. */ + {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, + cris_sixteen_bit_offset_branch_op}, + + {"ba", + BA_QUICK_OPCODE, + 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + /* Needs to come after the usual "ba o", which might be relaxed to + this one. */ + {"ba", BA_DWORD_OPCODE, + 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"bcc", + BRANCH_QUICK_OPCODE+CC_CC*0x1000, + 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bcs", + BRANCH_QUICK_OPCODE+CC_CS*0x1000, + 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bdap", + BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED, + cris_ver_v0_10, + cris_bdap_prefix}, + + {"bdap", + BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, + cris_ver_v0_10, + cris_quick_mode_bdap_prefix}, + + {"beq", + BRANCH_QUICK_OPCODE+CC_EQ*0x1000, + 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + /* This is deliberately put before "bext" to trump it, even though not + in alphabetical order, since we don't do excluding version checks + for v0..v10. */ + {"bwf", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v10, + cris_eight_bit_offset_branch_op}, + + {"bext", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v0_3, + cris_eight_bit_offset_branch_op}, + + {"bge", + BRANCH_QUICK_OPCODE+CC_GE*0x1000, + 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bgt", + BRANCH_QUICK_OPCODE+CC_GT*0x1000, + 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhi", + BRANCH_QUICK_OPCODE+CC_HI*0x1000, + 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bhs", + BRANCH_QUICK_OPCODE+CC_HS*0x1000, + 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, + cris_ver_v0_10, + cris_biap_prefix}, + + {"ble", + BRANCH_QUICK_OPCODE+CC_LE*0x1000, + 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blo", + BRANCH_QUICK_OPCODE+CC_LO*0x1000, + 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bls", + BRANCH_QUICK_OPCODE+CC_LS*0x1000, + 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"blt", + BRANCH_QUICK_OPCODE+CC_LT*0x1000, + 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmi", + BRANCH_QUICK_OPCODE+CC_MI*0x1000, + 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, + cris_ver_sim_v0_10, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, + cris_ver_sim_v0_10, + cris_not_implemented_op}, + + {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, + cris_ver_sim_v0_10, + cris_not_implemented_op}, + + {"bne", + BRANCH_QUICK_OPCODE+CC_NE*0x1000, + 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, + cris_two_operand_bound_op}, + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, + cris_ver_v0_10, + cris_two_operand_bound_op}, + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_two_operand_bound_op}, + {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_bound_op}, + + {"bpl", + BRANCH_QUICK_OPCODE+CC_PL*0x1000, + 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, + cris_ver_v3p, + cris_break_op}, + + {"bsb", + BRANCH_QUICK_OPCODE+CC_EXT*0x1000, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + cris_ver_v32p, + cris_eight_bit_offset_branch_op}, + + {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, + cris_ver_warning, + cris_not_implemented_op}, + + {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, + cris_btst_nop_op}, + + {"bvc", + BRANCH_QUICK_OPCODE+CC_VC*0x1000, + 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"bvs", + BRANCH_QUICK_OPCODE+CC_VS*0x1000, + 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, + cris_eight_bit_offset_branch_op}, + + {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, + cris_reg_mode_clear_op}, + + {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, + cris_none_reg_mode_clear_test_op}, + + {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_clear_test_op}, + + {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ + {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, + cris_clearf_di_op}, + + {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, + cris_ver_v0_10, + cris_dip_prefix}, + + {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, + cris_not_implemented_op}, + + {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, + cris_ver_v8_10, + cris_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, + cris_ver_v8_10, + cris_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, + cris_ver_v8_10, + cris_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, + cris_ver_v0_10, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, + cris_ver_v8_10, + cris_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, + cris_ver_v8_10, + cris_none_reg_mode_jump_op}, + + {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_reg_mode_jump_op}, + + {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, + cris_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, + cris_ver_v0_10, + cris_none_reg_mode_jump_op}, + + {"jump", + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_jump_op}, + + {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"jump", + JUMP_PC_INCR_OPCODE_V32, + (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, + cris_ver_v10, + cris_none_reg_mode_jump_op}, + + {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, + cris_ver_v10, + cris_none_reg_mode_jump_op}, + + {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, + cris_ver_v32p, + cris_not_implemented_op}, + + {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, + cris_ver_v32p, + cris_addi_op}, + + {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, + cris_ver_v3p, + cris_not_implemented_op}, + + {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, + cris_move_to_preg_op}, + + {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, + cris_reg_mode_move_from_preg_op}, + + {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"move", + MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS, + "s,P", 0, SIZE_SPEC_REG, 0, + cris_move_to_preg_op}, + + {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, + cris_ver_v0_10, + cris_move_to_preg_op}, + + {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, + cris_none_reg_mode_move_from_preg_op}, + + {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_move_from_preg_op}, + + {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_move_reg_to_mem_movem_op}, + + {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, + cris_move_mem_to_reg_movem_op}, + + {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_move_mem_to_reg_movem_op}, + + {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ + {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, + cris_ver_v0_10, + cris_dstep_logshift_mstep_neg_not_op}, + + {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_muls_op}, + + {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, + cris_ver_v10p, + cris_mulu_op}, + + {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, + cris_ver_v0_10, + cris_btst_nop_op}, + + {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_btst_nop_op}, + + {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, + cris_dstep_logshift_mstep_neg_not_op}, + + {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, + cris_quick_mode_and_cmp_move_or_op}, + + {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_move_from_preg_op}, + + {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, + cris_ver_v0_10, + cris_move_to_preg_op}, + + {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, + cris_ver_v10, + cris_not_implemented_op}, + + {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, + cris_ver_v10, + cris_not_implemented_op}, + + {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, + cris_ver_v0_10, + cris_reg_mode_move_from_preg_op}, + + {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_move_from_preg_op}, + + {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, + cris_ver_v0_10, + cris_reg_mode_move_from_preg_op}, + + {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_move_from_preg_op}, + + {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, + cris_ver_v0_10, + cris_reg_mode_move_from_preg_op}, + + {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, + cris_ver_v32p, + cris_reg_mode_move_from_preg_op}, + + {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, + cris_ver_v10, + cris_not_implemented_op}, + + {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, + cris_ver_v10, + cris_not_implemented_op}, + + {"sa", + 0x0530+CC_A*0x1000, + 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"ssb", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v32p, + cris_scc_op}, + + {"scc", + 0x0530+CC_CC*0x1000, + 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"scs", + 0x0530+CC_CS*0x1000, + 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"seq", + 0x0530+CC_EQ*0x1000, + 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, + cris_ax_ei_setf_op}, + + {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, + cris_ver_v32p, + cris_not_implemented_op}, + + /* Need to have "swf" in front of "sext" so it is the one displayed in + disassembly. */ + {"swf", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v10, + cris_scc_op}, + + {"sext", + 0x0530+CC_EXT*0x1000, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + cris_ver_v0_3, + cris_scc_op}, + + {"sge", + 0x0530+CC_GE*0x1000, + 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sgt", + 0x0530+CC_GT*0x1000, + 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shi", + 0x0530+CC_HI*0x1000, + 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"shs", + 0x0530+CC_HS*0x1000, + 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sle", + 0x0530+CC_LE*0x1000, + 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slo", + 0x0530+CC_LO*0x1000, + 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sls", + 0x0530+CC_LS*0x1000, + 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"slt", + 0x0530+CC_LT*0x1000, + 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"smi", + 0x0530+CC_MI*0x1000, + 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sne", + 0x0530+CC_NE*0x1000, + 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"spl", + 0x0530+CC_PL*0x1000, + 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, + cris_quick_mode_add_sub_op}, + + {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ + {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, + cris_reg_mode_add_sub_cmp_and_or_move_op}, + + /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ + {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_add_sub_cmp_and_or_move_op}, + + {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, + cris_ver_v0_10, + cris_three_operand_add_sub_cmp_and_or_op}, + + {"svc", + 0x0530+CC_VC*0x1000, + 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + {"svs", + 0x0530+CC_VS*0x1000, + 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, + cris_scc_op}, + + /* The insn "swapn" is the same as "not" and will be disassembled as + such, but the swap* family of mnmonics are generally v8-and-higher + only, so count it in. */ + {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, + cris_ver_v8p, + cris_not_implemented_op}, + + {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, + cris_ver_v0_10, + cris_reg_mode_test_op}, + + {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, + cris_none_reg_mode_clear_test_op}, + + {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, + cris_ver_v0_10, + cris_none_reg_mode_clear_test_op}, + + {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, + cris_xor_op}, + + {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} +}; + +/* Condition-names, indexed by the CC_* numbers as found in cris.h. */ +const char * const +cris_cc_strings[] = +{ + "hs", + "lo", + "ne", + "eq", + "vc", + "vs", + "pl", + "mi", + "ls", + "hi", + "ge", + "lt", + "gt", + "le", + "a", + /* This is a placeholder. In v0, this would be "ext". In v32, this + is "sb". See cris_conds15. */ + "wf" +}; + +/* Different names and semantics for condition 1111 (0xf). */ +const struct cris_cond15 cris_cond15s[] = +{ + /* FIXME: In what version did condition "ext" disappear? */ + {"ext", cris_ver_v0_3}, + {"wf", cris_ver_v10}, + {"sb", cris_ver_v32p}, + {NULL, 0} +}; + + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/external/gpl3/gdb/dist/opcodes/crx-dis.c b/external/gpl3/gdb/dist/opcodes/crx-dis.c new file mode 100644 index 000000000000..f909897444dd --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/crx-dis.c @@ -0,0 +1,745 @@ +/* Disassembler code for CRX. + Copyright 2004, 2005, 2006, 2007 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Written by Tomer Levi. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/crx.h" + +/* String to print when opcode was not matched. */ +#define ILLEGAL "illegal" + /* Escape to 16-bit immediate. */ +#define ESCAPE_16_BIT 0xE + +/* Extract 'n_bits' from 'a' starting from offset 'offs'. */ +#define EXTRACT(a, offs, n_bits) \ + (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \ + : (((a) >> (offs)) & ((1 << (n_bits)) -1))) + +/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */ +#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs))) + +typedef unsigned long dwordU; +typedef unsigned short wordU; + +typedef struct +{ + dwordU val; + int nbits; +} parameter; + +/* Structure to hold valid 'cinv' instruction options. */ + +typedef struct + { + /* Cinv printed string. */ + char *str; + /* Value corresponding to the string. */ + unsigned int value; + } +cinv_entry; + +/* CRX 'cinv' options. */ +const cinv_entry crx_cinvs[] = +{ + {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5}, + {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8}, + {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12}, + {"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15} +}; + +/* Enum to distinguish different registers argument types. */ +typedef enum REG_ARG_TYPE + { + /* General purpose register (r). */ + REG_ARG = 0, + /* User register (u). */ + USER_REG_ARG, + /* CO-Processor register (c). */ + COP_ARG, + /* CO-Processor special register (cs). */ + COPS_ARG + } +REG_ARG_TYPE; + +/* Number of valid 'cinv' instruction options. */ +int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0])); +/* Current opcode table entry we're disassembling. */ +const inst *instruction; +/* Current instruction we're disassembling. */ +ins currInsn; +/* The current instruction is read into 3 consecutive words. */ +wordU words[3]; +/* Contains all words in appropriate order. */ +ULONGLONG allWords; +/* Holds the current processed argument number. */ +int processing_argument_number; +/* Nonzero means a CST4 instruction. */ +int cst4flag; +/* Nonzero means the instruction's original size is + incremented (escape sequence is used). */ +int size_changed; + +static int get_number_of_operands (void); +static argtype getargtype (operand_type); +static int getbits (operand_type); +static char *getregname (reg); +static char *getcopregname (copreg, reg_type); +static char * getprocregname (int); +static char *gettrapstring (unsigned); +static char *getcinvstring (unsigned); +static void getregliststring (int, char *, enum REG_ARG_TYPE); +static wordU get_word_at_PC (bfd_vma, struct disassemble_info *); +static void get_words_at_PC (bfd_vma, struct disassemble_info *); +static unsigned long build_mask (void); +static int powerof2 (int); +static int match_opcode (void); +static void make_instruction (void); +static void print_arguments (ins *, bfd_vma, struct disassemble_info *); +static void print_arg (argument *, bfd_vma, struct disassemble_info *); + +/* Retrieve the number of operands for the current assembled instruction. */ + +static int +get_number_of_operands (void) +{ + int i; + + for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) + ; + + return i; +} + +/* Return the bit size for a given operand. */ + +static int +getbits (operand_type op) +{ + if (op < MAX_OPRD) + return crx_optab[op].bit_size; + else + return 0; +} + +/* Return the argument type of a given operand. */ + +static argtype +getargtype (operand_type op) +{ + if (op < MAX_OPRD) + return crx_optab[op].arg_type; + else + return nullargs; +} + +/* Given the trap index in dispatch table, return its name. + This routine is used when disassembling the 'excp' instruction. */ + +static char * +gettrapstring (unsigned int trap_index) +{ + const trap_entry *trap; + + for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++) + if (trap->entry == trap_index) + return trap->name; + + return ILLEGAL; +} + +/* Given a 'cinv' instruction constant operand, return its corresponding string. + This routine is used when disassembling the 'cinv' instruction. */ + +static char * +getcinvstring (unsigned int num) +{ + const cinv_entry *cinv; + + for (cinv = crx_cinvs; cinv < (crx_cinvs + NUMCINVS); cinv++) + if (cinv->value == num) + return cinv->str; + + return ILLEGAL; +} + +/* Given a register enum value, retrieve its name. */ + +char * +getregname (reg r) +{ + const reg_entry * regentry = &crx_regtab[r]; + + if (regentry->type != CRX_R_REGTYPE) + return ILLEGAL; + else + return regentry->name; +} + +/* Given a coprocessor register enum value, retrieve its name. */ + +char * +getcopregname (copreg r, reg_type type) +{ + const reg_entry * regentry; + + if (type == CRX_C_REGTYPE) + regentry = &crx_copregtab[r]; + else if (type == CRX_CS_REGTYPE) + regentry = &crx_copregtab[r+(cs0-c0)]; + else + return ILLEGAL; + + return regentry->name; +} + + +/* Getting a processor register name. */ + +static char * +getprocregname (int reg_index) +{ + const reg_entry *r; + + for (r = crx_regtab; r < crx_regtab + NUMREGS; r++) + if (r->image == reg_index) + return r->name; + + return "ILLEGAL REGISTER"; +} + +/* Get the power of two for a given integer. */ + +static int +powerof2 (int x) +{ + int product, i; + + for (i = 0, product = 1; i < x; i++) + product *= 2; + + return product; +} + +/* Transform a register bit mask to a register list. */ + +void +getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop) +{ + char temp_string[5]; + int i; + + string[0] = '{'; + string[1] = '\0'; + + + /* A zero mask means HI/LO registers. */ + if (mask == 0) + { + if (core_cop == USER_REG_ARG) + strcat (string, "ulo,uhi"); + else + strcat (string, "lo,hi"); + } + else + { + for (i = 0; i < 16; i++) + { + if (mask & 0x1) + { + switch (core_cop) + { + case REG_ARG: + sprintf (temp_string, "r%d", i); + break; + case USER_REG_ARG: + sprintf (temp_string, "u%d", i); + break; + case COP_ARG: + sprintf (temp_string, "c%d", i); + break; + case COPS_ARG: + sprintf (temp_string, "cs%d", i); + break; + default: + break; + } + strcat (string, temp_string); + if (mask & 0xfffe) + strcat (string, ","); + } + mask >>= 1; + } + } + + strcat (string, "}"); +} + +/* START and END are relating 'allWords' struct, which is 48 bits size. + + START|--------|END + +---------+---------+---------+---------+ + | | V | A | L | + +---------+---------+---------+---------+ + 0 16 32 48 + words [0] [1] [2] */ + +static parameter +makelongparameter (ULONGLONG val, int start, int end) +{ + parameter p; + + p.val = (dwordU) EXTRACT(val, 48 - end, end - start); + p.nbits = end - start; + return p; +} + +/* Build a mask of the instruction's 'constant' opcode, + based on the instruction's printing flags. */ + +static unsigned long +build_mask (void) +{ + unsigned int print_flags; + unsigned long mask; + + print_flags = instruction->flags & FMT_CRX; + switch (print_flags) + { + case FMT_1: + mask = 0xF0F00000; + break; + case FMT_2: + mask = 0xFFF0FF00; + break; + case FMT_3: + mask = 0xFFF00F00; + break; + case FMT_4: + mask = 0xFFF0F000; + break; + case FMT_5: + mask = 0xFFF0FFF0; + break; + default: + mask = SBM(instruction->match_bits); + break; + } + + return mask; +} + +/* Search for a matching opcode. Return 1 for success, 0 for failure. */ + +static int +match_opcode (void) +{ + unsigned long mask; + + /* The instruction 'constant' opcode doewsn't exceed 32 bits. */ + unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff; + + /* Start searching from end of instruction table. */ + instruction = &crx_instruction[NUMOPCODES - 2]; + + /* Loop over instruction table until a full match is found. */ + while (instruction >= crx_instruction) + { + mask = build_mask (); + if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits)) + return 1; + else + instruction--; + } + return 0; +} + +/* Set the proper parameter value for different type of arguments. */ + +static void +make_argument (argument * a, int start_bits) +{ + int inst_bit_size, total_size; + parameter p; + + if ((instruction->size == 3) && a->size >= 16) + inst_bit_size = 48; + else + inst_bit_size = 32; + + switch (a->type) + { + case arg_copr: + case arg_copsr: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->cr = p.val; + break; + + case arg_r: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_ic: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + + if ((p.nbits == 4) && cst4flag) + { + if (IS_INSN_TYPE (CMPBR_INS) && (p.val == ESCAPE_16_BIT)) + { + /* A special case, where the value is actually stored + in the last 4 bits. */ + p = makelongparameter (allWords, 44, 48); + /* The size of the instruction should be incremented. */ + size_changed = 1; + } + + if (p.val == 6) + p.val = -1; + else if (p.val == 13) + p.val = 48; + else if (p.val == 5) + p.val = -4; + else if (p.val == 10) + p.val = 32; + else if (p.val == 11) + p.val = 20; + else if (p.val == 9) + p.val = 16; + } + + a->constant = p.val; + break; + + case arg_idxr: + a->scale = 0; + total_size = a->size + 10; /* sizeof(rbase + ridx + scl2) = 10. */ + p = makelongparameter (allWords, inst_bit_size - total_size, + inst_bit_size - (total_size - 4)); + a->r = p.val; + p = makelongparameter (allWords, inst_bit_size - (total_size - 4), + inst_bit_size - (total_size - 8)); + a->i_r = p.val; + p = makelongparameter (allWords, inst_bit_size - (total_size - 8), + inst_bit_size - (total_size - 10)); + a->scale = p.val; + p = makelongparameter (allWords, inst_bit_size - (total_size - 10), + inst_bit_size); + a->constant = p.val; + break; + + case arg_rbase: + p = makelongparameter (allWords, inst_bit_size - (start_bits + 4), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_cr: + if (a->size <= 8) + { + p = makelongparameter (allWords, inst_bit_size - (start_bits + 4), + inst_bit_size - start_bits); + a->r = p.val; + /* Case for opc4 r dispu rbase. */ + p = makelongparameter (allWords, inst_bit_size - (start_bits + 8), + inst_bit_size - (start_bits + 4)); + } + else + { + /* The 'rbase' start_bits is always relative to a 32-bit data type. */ + p = makelongparameter (allWords, 32 - (start_bits + 4), + 32 - start_bits); + a->r = p.val; + p = makelongparameter (allWords, 32 - start_bits, + inst_bit_size); + } + if ((p.nbits == 4) && cst4flag) + { + if (instruction->flags & DISPUW4) + p.val *= 2; + else if (instruction->flags & DISPUD4) + p.val *= 4; + } + a->constant = p.val; + break; + + case arg_c: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->constant = p.val; + break; + default: + break; + } +} + +/* Print a single argument. */ + +static void +print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info) +{ + LONGLONG longdisp, mask; + int sign_flag = 0; + int relative = 0; + bfd_vma number; + int op_index = 0; + char string[200]; + PTR stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (a->type) + { + case arg_copr: + func (stream, "%s", getcopregname (a->cr, CRX_C_REGTYPE)); + break; + + case arg_copsr: + func (stream, "%s", getcopregname (a->cr, CRX_CS_REGTYPE)); + break; + + case arg_r: + if (IS_INSN_MNEMONIC ("mtpr") || IS_INSN_MNEMONIC ("mfpr")) + func (stream, "%s", getprocregname (a->r)); + else + func (stream, "%s", getregname (a->r)); + break; + + case arg_ic: + if (IS_INSN_MNEMONIC ("excp")) + func (stream, "%s", gettrapstring (a->constant)); + + else if (IS_INSN_MNEMONIC ("cinv")) + func (stream, "%s", getcinvstring (a->constant)); + + else if (INST_HAS_REG_LIST) + { + REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ? + COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ? + COPS_ARG : (instruction->flags & USER_REG) ? + USER_REG_ARG : REG_ARG; + + if ((reg_arg_type == COP_ARG) || (reg_arg_type == COPS_ARG)) + { + /* Check for proper argument number. */ + if (processing_argument_number == 2) + { + getregliststring (a->constant, string, reg_arg_type); + func (stream, "%s", string); + } + else + func (stream, "$0x%lx", a->constant); + } + else + { + getregliststring (a->constant, string, reg_arg_type); + func (stream, "%s", string); + } + } + else + func (stream, "$0x%lx", a->constant); + break; + + case arg_idxr: + func (stream, "0x%lx(%s,%s,%d)", a->constant, getregname (a->r), + getregname (a->i_r), powerof2 (a->scale)); + break; + + case arg_rbase: + func (stream, "(%s)", getregname (a->r)); + break; + + case arg_cr: + func (stream, "0x%lx(%s)", a->constant, getregname (a->r)); + + if (IS_INSN_TYPE (LD_STOR_INS_INC)) + func (stream, "+"); + break; + + case arg_c: + /* Removed the *2 part as because implicit zeros are no more required. + Have to fix this as this needs a bit of extension in terms of branchins. + Have to add support for cmp and branch instructions. */ + if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal") + || IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (DCR_BRANCH_INS) + || IS_INSN_TYPE (COP_BRANCH_INS)) + { + relative = 1; + longdisp = a->constant; + longdisp <<= 1; + + switch (a->size) + { + case 8: + case 16: + case 24: + case 32: + mask = ((LONGLONG)1 << a->size) - 1; + if (longdisp & ((LONGLONG)1 << a->size)) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + a->constant = (unsigned long int) (longdisp & mask); + break; + default: + func (stream, + "Wrong offset used in branch/bal instruction"); + break; + } + + } + /* For branch Neq instruction it is 2*offset + 2. */ + else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) + a->constant = 2 * a->constant + 2; + else if (IS_INSN_TYPE (LD_STOR_INS_INC) + || IS_INSN_TYPE (LD_STOR_INS) + || IS_INSN_TYPE (STOR_IMM_INS) + || IS_INSN_TYPE (CSTBIT_INS)) + { + op_index = instruction->flags & REVERSE_MATCH ? 0 : 1; + if (instruction->operands[op_index].op_type == abs16) + a->constant |= 0xFFFF0000; + } + func (stream, "%s", "0x"); + number = (relative ? memaddr : 0) + + (sign_flag ? -a->constant : a->constant); + (*info->print_address_func) (number, info); + break; + default: + break; + } +} + +/* Print all the arguments of CURRINSN instruction. */ + +static void +print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + + for (i = 0; i < currentInsn->nargs; i++) + { + processing_argument_number = i; + + print_arg (¤tInsn->arg[i], memaddr, info); + + if (i != currentInsn->nargs - 1) + info->fprintf_func (info->stream, ", "); + } +} + +/* Build the instruction's arguments. */ + +static void +make_instruction (void) +{ + int i; + unsigned int shift; + + for (i = 0; i < currInsn.nargs; i++) + { + argument a; + + memset (&a, 0, sizeof (a)); + a.type = getargtype (instruction->operands[i].op_type); + if (instruction->operands[i].op_type == cst4 + || instruction->operands[i].op_type == rbase_dispu4) + cst4flag = 1; + a.size = getbits (instruction->operands[i].op_type); + shift = instruction->operands[i].shift; + + make_argument (&a, shift); + currInsn.arg[i] = a; + } + + /* Calculate instruction size (in bytes). */ + currInsn.size = instruction->size + (size_changed ? 1 : 0); + /* Now in bits. */ + currInsn.size *= 2; +} + +/* Retrieve a single word from a given memory address. */ + +static wordU +get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int status; + wordU insn = 0; + + status = info->read_memory_func (memaddr, buffer, 2, info); + + if (status == 0) + insn = (wordU) bfd_getl16 (buffer); + + return insn; +} + +/* Retrieve multiple words (3) from a given memory address. */ + +static void +get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + bfd_vma mem; + + for (i = 0, mem = memaddr; i < 3; i++, mem += 2) + words[i] = get_word_at_PC (mem, info); + + allWords = + ((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2]; +} + +/* Prints the instruction by calling print_arguments after proper matching. */ + +int +print_insn_crx (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int is_decoded; /* Nonzero means instruction has a match. */ + + /* Initialize global variables. */ + cst4flag = 0; + size_changed = 0; + + /* Retrieve the encoding from current memory location. */ + get_words_at_PC (memaddr, info); + /* Find a matching opcode in table. */ + is_decoded = match_opcode (); + /* If found, print the instruction's mnemonic and arguments. */ + if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0) + { + info->fprintf_func (info->stream, "%s", instruction->mnemonic); + if ((currInsn.nargs = get_number_of_operands ()) != 0) + info->fprintf_func (info->stream, "\t"); + make_instruction (); + print_arguments (&currInsn, memaddr, info); + return currInsn.size; + } + + /* No match found. */ + info->fprintf_func (info->stream,"%s ",ILLEGAL); + return 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/crx-opc.c b/external/gpl3/gdb/dist/opcodes/crx-opc.c new file mode 100644 index 000000000000..b046c913e33f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/crx-opc.c @@ -0,0 +1,715 @@ +/* crx-opc.c -- Table of opcodes for the CRX processor. + Copyright 2004, 2005, 2007 Free Software Foundation, Inc. + Contributed by Tomer Levi NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "libiberty.h" +#include "symcat.h" +#include "opcode/crx.h" + +const inst crx_instruction[] = +{ +/* Create an arithmetic instruction - INST[bw]. */ +#define ARITH_BYTE_INST(NAME, OPC) \ + /* opc8 cst4 r */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ + /* opc8 i16 r */ \ + {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ + /* opc8 r r */ \ + {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} + + ARITH_BYTE_INST ("addub", 0x0), + ARITH_BYTE_INST ("addb", 0x1), + ARITH_BYTE_INST ("addcb", 0x2), + ARITH_BYTE_INST ("andb", 0x3), + ARITH_BYTE_INST ("cmpb", 0x4), + ARITH_BYTE_INST ("movb", 0x5), + ARITH_BYTE_INST ("orb", 0x6), + ARITH_BYTE_INST ("subb", 0x7), + ARITH_BYTE_INST ("subcb", 0x8), + ARITH_BYTE_INST ("xorb", 0x9), + ARITH_BYTE_INST ("mulb", 0xA), + + ARITH_BYTE_INST ("adduw", 0x10), + ARITH_BYTE_INST ("addw", 0x11), + ARITH_BYTE_INST ("addcw", 0x12), + ARITH_BYTE_INST ("andw", 0x13), + ARITH_BYTE_INST ("cmpw", 0x14), + ARITH_BYTE_INST ("movw", 0x15), + ARITH_BYTE_INST ("orw", 0x16), + ARITH_BYTE_INST ("subw", 0x17), + ARITH_BYTE_INST ("subcw", 0x18), + ARITH_BYTE_INST ("xorw", 0x19), + ARITH_BYTE_INST ("mulw", 0x1A), + +/* Create an arithmetic instruction - INST[d]. */ +#define ARITH_INST(NAME, OPC) \ + /* opc8 cst4 r */ \ + {NAME, 1, OPC, 24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \ + /* opc8 i16 r */ \ + {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0}, {regr,16}}}, \ + /* opc8 i32 r */ \ + {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \ + /* opc8 r r */ \ + {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}} + + ARITH_INST ("addud", 0x20), + ARITH_INST ("addd", 0x21), + ARITH_INST ("addcd", 0x22), + ARITH_INST ("andd", 0x23), + ARITH_INST ("cmpd", 0x24), + ARITH_INST ("movd", 0x25), + ARITH_INST ("ord", 0x26), + ARITH_INST ("subd", 0x27), + ARITH_INST ("subcd", 0x28), + ARITH_INST ("xord", 0x29), + ARITH_INST ("muld", 0x2A), + +/* Create a shift instruction. */ +#define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \ + /* OPRD=ui3 -->> opc9 ui3 r */ \ + /* OPRD=ui4 -->> opc8 ui4 r */ \ + /* OPRD=ui5 -->> opc7 ui5 r */ \ + {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \ + /* opc8 r r */ \ + {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}} + + SHIFT_INST ("sllb", ui3, 0x1F8, 23, 0x4D), + SHIFT_INST ("srlb", ui3, 0x1F9, 23, 0x4E), + SHIFT_INST ("srab", ui3, 0x1FA, 23, 0x4F), + + SHIFT_INST ("sllw", ui4, 0xB6, 24, 0x5D), + SHIFT_INST ("srlw", ui4, 0xB7, 24, 0x5E), + SHIFT_INST ("sraw", ui4, 0xB8, 24, 0x5F), + + SHIFT_INST ("slld", ui5, 0x78, 25, 0x6D), + SHIFT_INST ("srld", ui5, 0x79, 25, 0x6E), + SHIFT_INST ("srad", ui5, 0x7A, 25, 0x6F), + +/* Create a conditional branch instruction. */ +#define BRANCH_INST(NAME, OPC) \ + /* opc4 c4 dispe9 */ \ + {NAME, 1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}}, \ + /* opc4 c4 disps17 */ \ + {NAME, 2, (OPC<<8)+0x7E, 16, BRANCH_INS | RELAXABLE, {{disps17,0}}}, \ + /* opc4 c4 disps32 */ \ + {NAME, 3, (OPC<<8)+0x7F, 16, BRANCH_INS | RELAXABLE, {{disps32,0}}} + + BRANCH_INST ("beq", 0x70), + BRANCH_INST ("bne", 0x71), + BRANCH_INST ("bcs", 0x72), + BRANCH_INST ("bcc", 0x73), + BRANCH_INST ("bhi", 0x74), + BRANCH_INST ("bls", 0x75), + BRANCH_INST ("bgt", 0x76), + BRANCH_INST ("ble", 0x77), + BRANCH_INST ("bfs", 0x78), + BRANCH_INST ("bfc", 0x79), + BRANCH_INST ("blo", 0x7A), + BRANCH_INST ("bhs", 0x7B), + BRANCH_INST ("blt", 0x7C), + BRANCH_INST ("bge", 0x7D), + BRANCH_INST ("br", 0x7E), + +/* Create a 'Branch if Equal to 0' instruction. */ +#define BRANCH_NEQ_INST(NAME, OPC) \ + /* opc8 dispu5 r */ \ + {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}} + + BRANCH_NEQ_INST ("beq0b", 0xB0), + BRANCH_NEQ_INST ("bne0b", 0xB1), + BRANCH_NEQ_INST ("beq0w", 0xB2), + BRANCH_NEQ_INST ("bne0w", 0xB3), + BRANCH_NEQ_INST ("beq0d", 0xB4), + BRANCH_NEQ_INST ("bne0d", 0xB5), + +/* Create instruction with no operands. */ +#define NO_OP_INST(NAME, OPC) \ + /* opc16 */ \ + {NAME, 1, OPC, 16, 0, {{0, 0}}} + + NO_OP_INST ("nop", 0x3002), + NO_OP_INST ("retx", 0x3003), + NO_OP_INST ("di", 0x3004), + NO_OP_INST ("ei", 0x3005), + NO_OP_INST ("wait", 0x3006), + NO_OP_INST ("eiwait", 0x3007), + +/* Create a 'Compare & Branch' instruction. */ +#define CMPBR_INST(NAME, OPC1, OPC2, C4) \ + /* opc12 r r c4 disps9 */ \ + {NAME, 2, ((0x300+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3| RELAXABLE, \ + {{regr,16}, {regr,12}, {disps9,0}}}, \ + /* opc12 r r c4 disps25 */ \ + {NAME, 3, ((0x310+OPC1)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ + {{regr,16}, {regr,12}, {disps25,0}}}, \ + /* opc12 i4cst4 r c4 disps9 */ \ + {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ + {{cst4,16}, {regr,12}, {disps9,0}}}, \ + /* opc12 i4cst4 r c4 disps25 */ \ + {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \ + {{cst4,16}, {regr,12}, {disps25,0}}} + + CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0), + CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1), + CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4), + CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5), + CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6), + CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7), + CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA), + CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB), + CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC), + CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD), + + CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0), + CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1), + CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4), + CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5), + CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6), + CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7), + CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA), + CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB), + CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC), + CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD), + + CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0), + CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1), + CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4), + CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5), + CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6), + CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7), + CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA), + CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB), + CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC), + CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD), + +/* Create an instruction using a single register operand. */ +#define REG1_INST(NAME, OPC) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} + +/* Same as REG1_INST, with additional FLAGS. */ +#define REG1_FLAG_INST(NAME, OPC, FLAGS) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}} + + /* JCond instructions */ + REG1_INST ("jeq", 0xBA0), + REG1_INST ("jne", 0xBA1), + REG1_INST ("jcs", 0xBA2), + REG1_INST ("jcc", 0xBA3), + REG1_INST ("jhi", 0xBA4), + REG1_INST ("jls", 0xBA5), + REG1_INST ("jgt", 0xBA6), + REG1_INST ("jle", 0xBA7), + REG1_INST ("jfs", 0xBA8), + REG1_INST ("jfc", 0xBA9), + REG1_INST ("jlo", 0xBAA), + REG1_INST ("jhs", 0xBAB), + REG1_INST ("jlt", 0xBAC), + REG1_INST ("jge", 0xBAD), + REG1_INST ("jump", 0xBAE), + + /* SCond instructions */ + REG1_INST ("seq", 0xBB0), + REG1_INST ("sne", 0xBB1), + REG1_INST ("scs", 0xBB2), + REG1_INST ("scc", 0xBB3), + REG1_INST ("shi", 0xBB4), + REG1_INST ("sls", 0xBB5), + REG1_INST ("sgt", 0xBB6), + REG1_INST ("sle", 0xBB7), + REG1_INST ("sfs", 0xBB8), + REG1_INST ("sfc", 0xBB9), + REG1_INST ("slo", 0xBBA), + REG1_INST ("shs", 0xBBB), + REG1_INST ("slt", 0xBBC), + REG1_INST ("sge", 0xBBD), + +/* Create an instruction using two register operands. */ +#define REG2_INST(NAME, OPC) \ + /* opc24 r r OR opc20 c4 r r */ \ + {NAME, 2, 0x300800+OPC, 8, NO_TYPE_INS, {{regr,4}, {regr,0}}} + + /* MULTIPLY INSTRUCTIONS */ + REG2_INST ("macsb", 0x40), + REG2_INST ("macub", 0x41), + REG2_INST ("macqb", 0x42), + + REG2_INST ("macsw", 0x50), + REG2_INST ("macuw", 0x51), + REG2_INST ("macqw", 0x52), + + REG2_INST ("macsd", 0x60), + REG2_INST ("macud", 0x61), + REG2_INST ("macqd", 0x62), + + REG2_INST ("mullsd", 0x65), + REG2_INST ("mullud", 0x66), + + REG2_INST ("mulsbw", 0x3B), + REG2_INST ("mulubw", 0x3C), + REG2_INST ("mulswd", 0x3D), + REG2_INST ("muluwd", 0x3E), + + /* SIGNEXTEND STUFF */ + REG2_INST ("sextbw", 0x30), + REG2_INST ("sextbd", 0x31), + REG2_INST ("sextwd", 0x32), + REG2_INST ("zextbw", 0x34), + REG2_INST ("zextbd", 0x35), + REG2_INST ("zextwd", 0x36), + + REG2_INST ("bswap", 0x3F), + + REG2_INST ("maxsb", 0x80), + REG2_INST ("minsb", 0x81), + REG2_INST ("maxub", 0x82), + REG2_INST ("minub", 0x83), + REG2_INST ("absb", 0x84), + REG2_INST ("negb", 0x85), + REG2_INST ("cntl0b", 0x86), + REG2_INST ("cntl1b", 0x87), + REG2_INST ("popcntb",0x88), + REG2_INST ("rotlb", 0x89), + REG2_INST ("rotrb", 0x8A), + REG2_INST ("mulqb", 0x8B), + REG2_INST ("addqb", 0x8C), + REG2_INST ("subqb", 0x8D), + REG2_INST ("cntlsb", 0x8E), + + REG2_INST ("maxsw", 0x90), + REG2_INST ("minsw", 0x91), + REG2_INST ("maxuw", 0x92), + REG2_INST ("minuw", 0x93), + REG2_INST ("absw", 0x94), + REG2_INST ("negw", 0x95), + REG2_INST ("cntl0w", 0x96), + REG2_INST ("cntl1w", 0x97), + REG2_INST ("popcntw",0x98), + REG2_INST ("rotlw", 0x99), + REG2_INST ("rotrw", 0x9A), + REG2_INST ("mulqw", 0x9B), + REG2_INST ("addqw", 0x9C), + REG2_INST ("subqw", 0x9D), + REG2_INST ("cntlsw", 0x9E), + + REG2_INST ("maxsd", 0xA0), + REG2_INST ("minsd", 0xA1), + REG2_INST ("maxud", 0xA2), + REG2_INST ("minud", 0xA3), + REG2_INST ("absd", 0xA4), + REG2_INST ("negd", 0xA5), + REG2_INST ("cntl0d", 0xA6), + REG2_INST ("cntl1d", 0xA7), + REG2_INST ("popcntd",0xA8), + REG2_INST ("rotld", 0xA9), + REG2_INST ("rotrd", 0xAA), + REG2_INST ("mulqd", 0xAB), + REG2_INST ("addqd", 0xAC), + REG2_INST ("subqd", 0xAD), + REG2_INST ("cntlsd", 0xAE), + +/* Conditional move instructions */ + REG2_INST ("cmoveqd", 0x70), + REG2_INST ("cmovned", 0x71), + REG2_INST ("cmovcsd", 0x72), + REG2_INST ("cmovccd", 0x73), + REG2_INST ("cmovhid", 0x74), + REG2_INST ("cmovlsd", 0x75), + REG2_INST ("cmovgtd", 0x76), + REG2_INST ("cmovled", 0x77), + REG2_INST ("cmovfsd", 0x78), + REG2_INST ("cmovfcd", 0x79), + REG2_INST ("cmovlod", 0x7A), + REG2_INST ("cmovhsd", 0x7B), + REG2_INST ("cmovltd", 0x7C), + REG2_INST ("cmovged", 0x7D), + +/* Load instructions (from memory to register). */ +#define LD_REG_INST(NAME, OPC1, OPC2, DISP) \ + /* opc12 r abs16 */ \ + {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ + {{abs16,0}, {regr,16}}}, \ + /* opc12 r abs32 */ \ + {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ + {{abs32,0}, {regr,16}}}, \ + /* opc4 r rbase dispu[bwd]4 */ \ + {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, \ + {{rbase_dispu4,16}, {regr,24}}}, \ + /* opc4 r rbase disps16 */ \ + {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ + {{rbase_disps16,16}, {regr,24}}}, \ + /* opc4 r rbase disps32 */ \ + {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \ + {{rbase_disps32,16}, {regr,24}}}, \ + /* opc12 r rbase ridx scl2 disps6 */ \ + {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ + {{rindex_disps6,0}, {regr,16}}}, \ + /* opc12 r rbase ridx scl2 disps22 */ \ + {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS | REVERSE_MATCH, \ + {{rindex_disps22,0}, {regr,16}}}, \ + /* opc12 r rbase disps12 */ \ + {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC | REVERSE_MATCH, \ + {{rbase_disps12,12}, {regr,16}}} + + LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4), + LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4), + LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4), + +/* Store instructions (from Register to Memory). */ +#define ST_REG_INST(NAME, OPC1, OPC2, DISP) \ + /* opc12 r abs16 */ \ + {NAME, 2, 0x320+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs16,0}}}, \ + /* opc12 r abs32 */ \ + {NAME, 3, 0x330+OPC1, 20, LD_STOR_INS, {{regr,16}, {abs32,0}}}, \ + /* opc4 r rbase dispu[bwd]4 */ \ + {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP, \ + {{regr,24}, {rbase_dispu4,16}}}, \ + /* opc4 r rbase disps16 */ \ + {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1, \ + {{regr,24}, {rbase_disps16,16}}}, \ + /* opc4 r rbase disps32 */ \ + {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1, \ + {{regr,24}, {rbase_disps32,16}}}, \ + /* opc12 r rbase ridx scl2 disps6 */ \ + {NAME, 2, 0x32C+OPC1, 20, LD_STOR_INS, \ + {{regr,16}, {rindex_disps6,0}}}, \ + /* opc12 r rbase ridx scl2 disps22 */ \ + {NAME, 3, 0x33C+OPC1, 20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}}, \ + /* opc12 r rbase disps12 */ \ + {NAME, 2, 0x328+OPC1, 20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}} + +/* Store instructions (Immediate to Memory). */ +#define ST_I_INST(NAME, OPC) \ + /* opc12 ui4 rbase disps12 */ \ + {NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \ + /* opc12 ui4 abs16 */ \ + {NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}}, \ + /* opc12 ui4 abs32 */ \ + {NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}}, \ + /* opc12 ui4 rbase disps12 */ \ + {NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}}, \ + /* opc12 ui4 rbase disps28 */ \ + {NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}}, \ + /* opc12 ui4 rbase ridx scl2 disps6 */ \ + {NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}}, \ + /* opc12 ui4 rbase ridx scl2 disps22 */ \ + {NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}} + + ST_REG_INST ("storb", 0x20, 0x4, DISPUB4), + ST_I_INST ("storb", 0x0), + + ST_REG_INST ("storw", 0x21, 0x5, DISPUW4), + ST_I_INST ("storw", 0x1), + + ST_REG_INST ("stord", 0x22, 0x6, DISPUD4), + ST_I_INST ("stord", 0x2), + +/* Create a bit instruction. */ +#define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \ + /* OP=ui3 -->> opc13 ui3 */ \ + /* OP=ui4 -->> opc12 ui4 */ \ + /* OP=ui5 -->> opc11 ui5 */ \ + \ + /* opcNN iN abs16 */ \ + {NAME, 2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}}, \ + /* opcNN iN abs32 */ \ + {NAME, 3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}}, \ + /* opcNN iN rbase */ \ + {NAME, 1, OPC2, SHIFT+4, CSTBIT_INS, {{OP,20}, {rbase,16}}}, \ + /* opcNN iN rbase disps12 */ \ + {NAME, 2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}}, \ + /* opcNN iN rbase disps28 */ \ + {NAME, 3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}}, \ + /* opcNN iN rbase ridx scl2 disps6 */ \ + {NAME, 2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}}, \ + /* opcNN iN rbase ridx scl2 disps22 */ \ + {NAME, 3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}} + + CSTBIT_INST ("cbitb", ui3, 0x700, 0x20, 19, 0x1FC), + CSTBIT_INST ("cbitw", ui4, 0x382, 0x10, 20, 0xBD), + CSTBIT_INST ("cbitd", ui5, 0x1C3, 0x8, 21, 0x7B), + {"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, + {"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, + + CSTBIT_INST ("sbitb", ui3, 0x701, 0x20, 19, 0x1FD), + CSTBIT_INST ("sbitw", ui4, 0x383, 0x10, 20, 0xBE), + CSTBIT_INST ("sbitd", ui5, 0x1C4, 0x8, 21, 0x7C), + {"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, + {"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, + + CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE), + CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF), + CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8, 21, 0x7D), + {"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}}, + {"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}}, + +/* Instructions including a register list (opcode is represented as a mask). */ +#define REGLIST_INST(NAME, OPC, FLAG) \ + /* opc12 r mask16 */ \ + {NAME, 2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}} + + REG1_INST ("getrfid", 0xFF9), + REG1_INST ("setrfid", 0xFFA), + + REGLIST_INST ("push", 0x346, NO_RPTR), + REG1_FLAG_INST ("push", 0xFFB, NO_SP), + REGLIST_INST ("pushx", 0x347, NO_RPTR), + + REGLIST_INST ("pop", 0x324, NO_RPTR), + REG1_FLAG_INST ("pop", 0xFFC, NO_SP), + REGLIST_INST ("popx", 0x327, NO_RPTR), + + REGLIST_INST ("popret", 0x326, NO_RPTR), + REG1_FLAG_INST ("popret",0xFFD,NO_SP), + + REGLIST_INST ("loadm", 0x324, NO_RPTR), + REGLIST_INST ("loadma", 0x325, USER_REG), + + REGLIST_INST ("storm", 0x344, NO_RPTR), + REGLIST_INST ("storma", 0x345, USER_REG), + +/* Create a branch instruction. */ +#define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \ + /* opc12 r disps17 */ \ + {NAME, 2, OPC1, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}}, \ + /* opc12 r disps32 */ \ + {NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}} + + BR_INST ("bal", 0x307, 0x317, NO_TYPE_INS), + + /* Decrement and Branch instructions. */ + BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS), + BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS), + BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS), + + /* Jump and link instructions. */ + REG1_INST ("jal", 0xFF8), + REG2_INST ("jal", 0x37), + REG2_INST ("jalid", 0x33), + +/* Create a CO-processor instruction. */ + /* esc12 c4 ui16 */ + {"cpi", 2, 0x301, 20, COP_REG_INS, {{ui4,16}, {ui16,0}}}, + /* esc12 c4 ui16 ui16 */ + {"cpi", 3, 0x311, 20, COP_REG_INS, {{ui4,16}, {ui16,0}, {ui16,16}}}, + +#define COP_INST(NAME, OPC, TYPE, REG1, REG2) \ + /* opc12 c4 opc8 REG1 REG2 */ \ + {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}} +/* A reverse form of the above macro. */ +#define REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \ + /* opc12 c4 opc8 REG2 REG1 */ \ + {NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}} + + COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr), + COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr), + COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr), + COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr), + COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr), + REV_COP_INST ("stcr", 5, COP_REG_INS, copregr, regr), + COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr), + REV_COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr), + +/* Create a memory-related CO-processor instruction. */ +#define COPMEM_INST(NAME, OPC, TYPE) \ + /* opc12 c4 opc12 r mask16 */ \ + {NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, \ + {{ui4,16}, {regr,0}, {ui16,16}}} + + COPMEM_INST("loadmcr", 0, COP_REG_INS), + COPMEM_INST("stormcr", 1, COP_REG_INS), + COPMEM_INST("loadmcsr", 2, COPS_REG_INS), + COPMEM_INST("stormcsr", 3, COPS_REG_INS), + + /* CO-processor extensions. */ + /* opc12 c4 opc4 ui4 disps9 */ + {"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, + {{ui4,8}, {ui4,16}, {disps9,0}}}, + /* opc12 c4 opc4 ui4 disps25 */ + {"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, + {{ui4,8}, {ui4,16}, {disps25,0}}}, + /* opc12 c4 opc4 cpdo r r */ + {"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, + {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}}, + /* opc12 c4 opc4 cpdo r r cpdo16 */ + {"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, + {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}}, + /* esc16 r procreg */ + {"mtpr", 2, 0x3009, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, + /* esc16 procreg r */ + {"mfpr", 2, 0x300A, 16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}}, + + /* Miscellaneous. */ + /* opc12 ui4 */ + {"excp", 1, 0xFFF, 20, NO_TYPE_INS, {{ui4,16}}}, + /* opc28 ui4 */ + {"cinv", 2, 0x3010000, 4, NO_TYPE_INS, {{ui4,0}}}, + + /* opc9 ui5 ui5 ui5 r r */ + {"ram", 2, 0x7C, 23, NO_TYPE_INS, + {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, + {"rim", 2, 0x7D, 23, NO_TYPE_INS, + {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}}, + + /* opc9 ui3 r */ + {"rotb", 1, 0x1FB, 23, NO_TYPE_INS, {{ui3,20}, {regr,16}}}, + /* opc8 ui4 r */ + {"rotw", 1, 0xB9, 24, NO_TYPE_INS, {{ui4,20}, {regr,16}}}, + /* opc23 ui5 r */ + {"rotd", 2, 0x180478, 9, NO_TYPE_INS, {{ui5,4}, {regr,0}}}, + + {NULL, 0, 0, 0, 0, {{0, 0}}} +}; + +const int crx_num_opcodes = ARRAY_SIZE (crx_instruction); + +/* Macro to build a reg_entry, which have an opcode image : + For example : + REG(u4, 0x84, CRX_U_REGTYPE) + is interpreted as : + {"u4", u4, 0x84, CRX_U_REGTYPE} */ +#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} + +const reg_entry crx_regtab[] = +{ +/* Build a general purpose register r. */ +#define REG_R(N) REG(CONCAT2(r,N), N, CRX_R_REGTYPE) + + REG_R(0), REG_R(1), REG_R(2), REG_R(3), + REG_R(4), REG_R(5), REG_R(6), REG_R(7), + REG_R(8), REG_R(9), REG_R(10), REG_R(11), + REG_R(12), REG_R(13), REG_R(14), REG_R(15), + REG(ra, 0xe, CRX_R_REGTYPE), + REG(sp, 0xf, CRX_R_REGTYPE), + +/* Build a user register u. */ +#define REG_U(N) REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE) + + REG_U(0), REG_U(1), REG_U(2), REG_U(3), + REG_U(4), REG_U(5), REG_U(6), REG_U(7), + REG_U(8), REG_U(9), REG_U(10), REG_U(11), + REG_U(12), REG_U(13), REG_U(14), REG_U(15), + REG(ura, 0x8e, CRX_U_REGTYPE), + REG(usp, 0x8f, CRX_U_REGTYPE), + +/* Build a configuration register. */ +#define REG_CFG(NAME, N) REG(NAME, N, CRX_CFG_REGTYPE) + + REG_CFG(hi, 0x10), + REG_CFG(lo, 0x11), + REG_CFG(uhi, 0x90), + REG_CFG(ulo, 0x91), + REG_CFG(psr, 0x12), + REG_CFG(intbase, 0x13), + REG_CFG(isp, 0x14), + REG_CFG(cfg, 0x15), + REG_CFG(cpcfg, 0x16), + REG_CFG(cen, 0x17) +}; + +const int crx_num_regs = ARRAY_SIZE (crx_regtab); + +const reg_entry crx_copregtab[] = +{ +/* Build a Coprocessor register c. */ +#define REG_C(N) REG(CONCAT2(c,N), N, CRX_C_REGTYPE) + + REG_C(0), REG_C(1), REG_C(2), REG_C(3), + REG_C(4), REG_C(5), REG_C(6), REG_C(7), + REG_C(8), REG_C(9), REG_C(10), REG_C(11), + REG_C(12), REG_C(13), REG_C(14), REG_C(15), + +/* Build a Coprocessor Special register cs. */ +#define REG_CS(N) REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE) + + REG_CS(0), REG_CS(1), REG_CS(2), REG_CS(3), + REG_CS(4), REG_CS(5), REG_CS(6), REG_CS(7), + REG_CS(8), REG_CS(9), REG_CS(10), REG_CS(11), + REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15) +}; + +const int crx_num_copregs = ARRAY_SIZE (crx_copregtab); + +/* CRX operands table. */ +const operand_entry crx_optab[] = +{ + /* Index 0 is dummy, so we can count the instruction's operands. */ + {0, nullargs, 0}, /* dummy */ + {4, arg_ic, OP_CST4}, /* cst4 */ + {16, arg_ic, OP_SIGNED}, /* i16 */ + {32, arg_ic, OP_SIGNED}, /* i32 */ + {3, arg_ic, OP_UNSIGNED}, /* ui3 */ + {4, arg_ic, OP_UNSIGNED}, /* ui4 */ + {5, arg_ic, OP_UNSIGNED}, /* ui5 */ + {16, arg_ic, OP_UNSIGNED}, /* ui16 */ + {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps9 */ + {16, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps17 */ + {24, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps25 */ + {32, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED}, /* disps32 */ + {4, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_UNSIGNED}, /* dispu5 */ + {8, arg_c, OP_EVEN|OP_SHIFT|OP_SIGNED|OP_ESC}, /* dispe9 */ + {16, arg_c, OP_UNSIGNED|OP_UPPER_64KB}, /* abs16 */ + {32, arg_c, OP_UNSIGNED}, /* abs32 */ + {4, arg_rbase, 0}, /* rbase */ + {4, arg_cr, OP_DISPU4}, /* rbase_dispu4 */ + {12, arg_cr, OP_SIGNED}, /* rbase_disps12 */ + {16, arg_cr, OP_SIGNED}, /* rbase_disps16 */ + {28, arg_cr, OP_SIGNED}, /* rbase_disps28 */ + {32, arg_cr, OP_SIGNED}, /* rbase_disps32 */ + {6, arg_idxr, OP_SIGNED}, /* rindex_disps6 */ + {22, arg_idxr, OP_SIGNED}, /* rindex_disps22 */ + {4, arg_r, 0}, /* regr */ + {8, arg_r, 0}, /* regr8 */ + {4, arg_copr, 0}, /* copregr */ + {4, arg_copsr, 0} /* copsregr */ +}; + +/* CRX traps/interrupts. */ +const trap_entry crx_traps[] = +{ + {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7}, + {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12} +}; + +const int crx_num_traps = ARRAY_SIZE (crx_traps); + +/* cst4 operand mapping: +The value in entry is mapped to the value + Value Binary mapping + cst4_map[N] -->> N + +Example (for N=5): + + cst4_map[5]=-4 -->> 5 */ +const long cst4_map[] = +{ + 0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48 +}; + +const int cst4_maps = ARRAY_SIZE (cst4_map); + +/* CRX instructions that don't have arguments. */ +const char* no_op_insn[] = +{ + "di", "ei", "eiwait", "nop", "retx", "wait", NULL +}; diff --git a/external/gpl3/gdb/dist/opcodes/d10v-dis.c b/external/gpl3/gdb/dist/opcodes/d10v-dis.c new file mode 100644 index 000000000000..dbedb3d76596 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/d10v-dis.c @@ -0,0 +1,299 @@ +/* Disassemble D10V instructions. + Copyright 1996, 1997, 1998, 2000, 2001, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/d10v.h" +#include "dis-asm.h" + +/* The PC wraps at 18 bits, except for the segment number, + so use this mask to keep the parts we want. */ +#define PC_MASK 0x0303FFFF + +static void +print_operand (struct d10v_operand *oper, + unsigned long insn, + struct d10v_opcode *op, + bfd_vma memaddr, + struct disassemble_info *info) +{ + int num, shift; + + if (oper->flags == OPERAND_ATMINUS) + { + (*info->fprintf_func) (info->stream, "@-"); + return; + } + if (oper->flags == OPERAND_MINUS) + { + (*info->fprintf_func) (info->stream, "-"); + return; + } + if (oper->flags == OPERAND_PLUS) + { + (*info->fprintf_func) (info->stream, "+"); + return; + } + if (oper->flags == OPERAND_ATSIGN) + { + (*info->fprintf_func) (info->stream, "@"); + return; + } + if (oper->flags == OPERAND_ATPAR) + { + (*info->fprintf_func) (info->stream, "@("); + return; + } + + shift = oper->shift; + + /* The LONG_L format shifts registers over by 15. */ + if (op->format == LONG_L && (oper->flags & OPERAND_REG)) + shift += 15; + + num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits)); + + if (oper->flags & OPERAND_REG) + { + int i; + int match = 0; + + num += (oper->flags + & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)); + if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) + num += num ? OPERAND_ACC1 : OPERAND_ACC0; + for (i = 0; i < d10v_reg_name_cnt (); i++) + { + if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP)) + { + if (d10v_predefined_registers[i].pname) + (*info->fprintf_func) (info->stream, "%s", + d10v_predefined_registers[i].pname); + else + (*info->fprintf_func) (info->stream, "%s", + d10v_predefined_registers[i].name); + match = 1; + break; + } + } + if (match == 0) + { + /* This would only get executed if a register was not in the + register table. */ + if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) + (*info->fprintf_func) (info->stream, "a"); + else if (oper->flags & OPERAND_CONTROL) + (*info->fprintf_func) (info->stream, "cr"); + else if (oper->flags & OPERAND_REG) + (*info->fprintf_func) (info->stream, "r"); + (*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK); + } + } + else + { + /* Addresses are right-shifted by 2. */ + if (oper->flags & OPERAND_ADDR) + { + long max; + int neg = 0; + + max = (1 << (oper->bits - 1)); + if (num & max) + { + num = -num & ((1 << oper->bits) - 1); + neg = 1; + } + num = num << 2; + if (info->flags & INSN_HAS_RELOC) + (*info->print_address_func) (num & PC_MASK, info); + else + { + if (neg) + (*info->print_address_func) ((memaddr - num) & PC_MASK, info); + else + (*info->print_address_func) ((memaddr + num) & PC_MASK, info); + } + } + else + { + if (oper->flags & OPERAND_SIGNED) + { + int max = (1 << (oper->bits - 1)); + if (num & max) + { + num = -num & ((1 << oper->bits) - 1); + (*info->fprintf_func) (info->stream, "-"); + } + } + (*info->fprintf_func) (info->stream, "0x%x", num); + } + } +} + +static void +dis_long (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info) +{ + int i; + struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes; + struct d10v_operand *oper; + int need_paren = 0; + int match = 0; + + while (op->name) + { + if ((op->format & LONG_OPCODE) + && ((op->mask & insn) == (unsigned long) op->opcode)) + { + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + for (i = 0; op->operands[i]; i++) + { + oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (oper, insn, op, memaddr, info); + if (op->operands[i + 1] && oper->bits + && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS + && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS) + (*info->fprintf_func) (info->stream, ", "); + } + break; + } + op++; + } + + if (!match) + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); + + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + +static void +dis_2_short (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info, + int order) +{ + int i, j; + unsigned int ins[2]; + struct d10v_opcode *op; + int match, num_match = 0; + struct d10v_operand *oper; + int need_paren = 0; + + ins[0] = (insn & 0x3FFFFFFF) >> 15; + ins[1] = insn & 0x00007FFF; + + for (j = 0; j < 2; j++) + { + op = (struct d10v_opcode *) d10v_opcodes; + match = 0; + while (op->name) + { + if ((op->format & SHORT_OPCODE) + && ((((unsigned int) op->mask) & ins[j]) + == (unsigned int) op->opcode)) + { + (*info->fprintf_func) (info->stream, "%s\t", op->name); + for (i = 0; op->operands[i]; i++) + { + oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (oper, ins[j], op, memaddr, info); + if (op->operands[i + 1] && oper->bits + && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS + && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS) + (*info->fprintf_func) (info->stream, ", "); + } + match = 1; + num_match++; + break; + } + op++; + } + if (!match) + (*info->fprintf_func) (info->stream, "unknown"); + + switch (order) + { + case 0: + (*info->fprintf_func) (info->stream, "\t->\t"); + order = -1; + break; + case 1: + (*info->fprintf_func) (info->stream, "\t<-\t"); + order = -1; + break; + case 2: + (*info->fprintf_func) (info->stream, "\t||\t"); + order = -1; + break; + default: + break; + } + } + + if (num_match == 0) + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); + + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + +int +print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + + status = insn & FM11; + switch (status) + { + case 0: + dis_2_short (insn, memaddr, info, 2); + break; + case FM01: + dis_2_short (insn, memaddr, info, 0); + break; + case FM10: + dis_2_short (insn, memaddr, info, 1); + break; + case FM11: + dis_long (insn, memaddr, info); + break; + } + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/d10v-opc.c b/external/gpl3/gdb/dist/opcodes/d10v-opc.c new file mode 100644 index 000000000000..f99d66a8ab7c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/d10v-opc.c @@ -0,0 +1,351 @@ +/* d10v-opc.c -- D10V opcode list + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005, 2007 + Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d10v.h" + + +/* The table is sorted. Suitable for searching by a binary search. */ +const struct pd_reg d10v_predefined_registers[] = +{ + { "a0", NULL, OPERAND_ACC0+0 }, + { "a1", NULL, OPERAND_ACC1+1 }, + { "bpc", NULL, OPERAND_CONTROL+3 }, + { "bpsw", NULL, OPERAND_CONTROL+1 }, + { "c", NULL, OPERAND_CFLAG+3 }, + { "cr0", "psw", OPERAND_CONTROL }, + { "cr1", "bpsw", OPERAND_CONTROL+1 }, + { "cr10", "mod_s", OPERAND_CONTROL+10 }, + { "cr11", "mod_e", OPERAND_CONTROL+11 }, + { "cr12", NULL, OPERAND_CONTROL+12 }, + { "cr13", NULL, OPERAND_CONTROL+13 }, + { "cr14", "iba", OPERAND_CONTROL+14 }, + { "cr15", NULL, OPERAND_CONTROL+15 }, + { "cr2", "pc", OPERAND_CONTROL+2 }, + { "cr3", "bpc", OPERAND_CONTROL+3 }, + { "cr4", "dpsw", OPERAND_CONTROL+4 }, + { "cr5", "dpc", OPERAND_CONTROL+5 }, + { "cr6", NULL, OPERAND_CONTROL+6 }, + { "cr7", "rpt_c", OPERAND_CONTROL+7 }, + { "cr8", "rpt_s", OPERAND_CONTROL+8 }, + { "cr9", "rpt_e", OPERAND_CONTROL+9 }, + { "dpc", NULL, OPERAND_CONTROL+5 }, + { "dpsw", NULL, OPERAND_CONTROL+4 }, + { "f0", NULL, OPERAND_FFLAG+0 }, + { "f1", NULL, OPERAND_FFLAG+1 }, + { "iba", NULL, OPERAND_CONTROL+14 }, + { "link", "r13", OPERAND_GPR+13 }, + { "mod_e", NULL, OPERAND_CONTROL+11 }, + { "mod_s", NULL, OPERAND_CONTROL+10 }, + { "pc", NULL, OPERAND_CONTROL+2 }, + { "psw", NULL, OPERAND_CONTROL+0 }, + { "r0", NULL, OPERAND_GPR+0 }, + { "r0-r1", NULL, OPERAND_GPR+0}, + { "r1", NULL, OPERAND_GPR+1 }, + { "r1", NULL, OPERAND_GPR+1 }, + { "r10", NULL, OPERAND_GPR+10 }, + { "r10-r11", NULL, OPERAND_GPR+10 }, + { "r11", NULL, OPERAND_GPR+11 }, + { "r12", NULL, OPERAND_GPR+12 }, + { "r12-r13", NULL, OPERAND_GPR+12 }, + { "r13", NULL, OPERAND_GPR+13 }, + { "r14", NULL, OPERAND_GPR+14 }, + { "r14-r15", NULL, OPERAND_GPR+14 }, + { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) }, + { "r2", NULL, OPERAND_GPR+2 }, + { "r2-r3", NULL, OPERAND_GPR+2 }, + { "r3", NULL, OPERAND_GPR+3 }, + { "r4", NULL, OPERAND_GPR+4 }, + { "r4-r5", NULL, OPERAND_GPR+4 }, + { "r5", NULL, OPERAND_GPR+5 }, + { "r6", NULL, OPERAND_GPR+6 }, + { "r6-r7", NULL, OPERAND_GPR+6 }, + { "r7", NULL, OPERAND_GPR+7 }, + { "r8", NULL, OPERAND_GPR+8 }, + { "r8-r9", NULL, OPERAND_GPR+8 }, + { "r9", NULL, OPERAND_GPR+9 }, + { "rpt_c", NULL, OPERAND_CONTROL+7 }, + { "rpt_e", NULL, OPERAND_CONTROL+9 }, + { "rpt_s", NULL, OPERAND_CONTROL+8 }, + { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) }, +}; + +int +d10v_reg_name_cnt() +{ + return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg)); +} + +const struct d10v_operand d10v_operands[] = +{ +#define UNUSED (0) + { 0, 0, 0 }, +#define RSRC (UNUSED + 1) + { 4, 1, OPERAND_GPR|OPERAND_REG }, +#define RSRC_SP (RSRC + 1) + { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG }, +#define RSRC_NOSP (RSRC_SP + 1) + { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG }, +#define RDST (RSRC_NOSP + 1) + { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, +#define ASRC (RDST + 1) + { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define ASRC0ONLY (ASRC + 1) + { 1, 4, OPERAND_ACC0|OPERAND_REG }, +#define ADST (ASRC0ONLY + 1) + { 1, 8, OPERAND_DEST|OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define RSRCE (ADST + 1) + { 4, 1, OPERAND_EVEN|OPERAND_GPR|OPERAND_REG }, +#define RDSTE (RSRCE + 1) + { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_GPR|OPERAND_REG }, +#define NUM16 (RDSTE + 1) + { 16, 0, OPERAND_NUM|OPERAND_SIGNED }, +#define NUM3 (NUM16 + 1) /* rac, rachi */ + { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 }, +#define NUM4 (NUM3 + 1) + { 4, 1, OPERAND_NUM|OPERAND_SIGNED }, +#define UNUM4 (NUM4 + 1) + { 4, 1, OPERAND_NUM }, +#define UNUM4S (UNUM4 + 1) /* addi, slli, srai, srli, subi */ + { 4, 1, OPERAND_NUM|OPERAND_SHIFT }, +#define UNUM8 (UNUM4S + 1) /* repi */ + { 8, 16, OPERAND_NUM }, +#define UNUM16 (UNUM8 + 1) /* cmpui */ + { 16, 0, OPERAND_NUM }, +#define ANUM16 (UNUM16 + 1) + { 16, 0, OPERAND_ADDR|OPERAND_SIGNED }, +#define ANUM8 (ANUM16 + 1) + { 8, 0, OPERAND_ADDR|OPERAND_SIGNED }, +#define ASRC2 (ANUM8 + 1) + { 1, 8, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define RSRC2 (ASRC2 + 1) + { 4, 5, OPERAND_GPR|OPERAND_REG }, +#define RSRC2E (RSRC2 + 1) + { 4, 5, OPERAND_GPR|OPERAND_REG|OPERAND_EVEN }, +#define ASRC0 (RSRC2E + 1) + { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG }, +#define ADST0 (ASRC0 + 1) + { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG|OPERAND_DEST }, +#define FFSRC (ADST0 + 1) + { 2, 1, OPERAND_REG | OPERAND_FFLAG }, +#define CFSRC (FFSRC + 1) + { 2, 1, OPERAND_REG | OPERAND_CFLAG }, +#define FDST (CFSRC + 1) + { 1, 5, OPERAND_REG | OPERAND_FFLAG | OPERAND_DEST}, +#define ATSIGN (FDST + 1) + { 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* postincrement */ + { 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* postdecrement */ + { 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* predecrement */ + { 0, 0, OPERAND_ATMINUS}, +#define CSRC (ATMINUS + 1) /* control register */ + { 4, 1, OPERAND_REG|OPERAND_CONTROL}, +#define CDST (CSRC + 1) /* control register */ + { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, +}; + +const struct d10v_opcode d10v_opcodes[] = { + { "abs", SHORT_2, 1, EITHER, PAR|WF0, 0x4607, 0x7e1f, { RDST } }, + { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } }, + { "add", SHORT_2, 1, EITHER, PAR|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, + { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } }, + { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } }, + { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } }, + { "add3", LONG_L, 1, MU, SEQ|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addi", SHORT_2, 1, EITHER, PAR|WCAR, 0x201, 0x7e01, { RDST, UNUM4S } }, + { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, + { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } }, + { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } }, + { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } }, + { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }, + { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } }, + { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, + { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } }, + { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, + { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, + { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } }, + { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, + { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } }, + { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } }, + { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, + { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, + { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } }, + { "cmpeq", SHORT_2, 1, EITHER, PAR|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, + { "cmpeq", SHORT_2, 1, IU, PAR|WF0, 0x1403, 0x7eef, { ASRC2, ASRC } }, + { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpeqi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x401, 0x7e01, { RSRC2, NUM4 } }, + { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x601, 0x7e01, { RSRC2, NUM4 } }, + { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, + { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } }, + { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } }, + { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } }, + { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } }, + { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, + { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } }, + { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } }, + { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } }, + { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } }, + { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } }, + { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } }, + { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } }, + { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, + { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } }, + { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } }, + { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } }, + { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } }, + { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } }, + { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } }, + { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } }, + { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "ldi.s", SHORT_2, 1, EITHER, PAR|RMEM, 0x4001, 0x7e01 , { RDST, NUM4 } }, + { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, + { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldub", SHORT_2, 1, MU, PAR|RMEM, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x2600, 0x7e01, { RDST, RSRC } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x3600, 0x7ee3, { ADST, RSRCE } }, + { "max", SHORT_2, 1, IU, PAR|WF0, 0x3602, 0x7eef, { ADST, ASRC } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x2601, 0x7e01 , { RDST, RSRC } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x3601, 0x7ee3 , { ADST, RSRCE } }, + { "min", SHORT_2, 1, IU, PAR|WF0, 0x3603, 0x7eef, { ADST, ASRC } }, + { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } }, + { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } }, + { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } }, + { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } }, + { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } }, + { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } }, + { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } }, + { "mvf0f", SHORT_2, 1, EITHER, PAR|RF0, 0x4400, 0x7e01, { RDST, RSRC } }, + { "mvf0t", SHORT_2, 1, EITHER, PAR|RF0, 0x4401, 0x7e01, { RDST, RSRC } }, + { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } }, + { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } }, + { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } }, + { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } }, + { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } }, + { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } }, + { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } }, + { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } }, + { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } }, + { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } }, + { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } }, + { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } }, + { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } }, + { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } }, + { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + /* Special case. sac&sachi must occur before rac&rachi because they have + intersecting masks! The masks for rac&rachi will match sac&sachi but + not the other way around. + */ + { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } }, + { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } }, + { "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } }, + { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, + { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, + { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } }, + { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } }, + { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } }, + { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, + { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } }, + { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } }, + { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } }, + { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } }, + { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, + { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, + { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } }, + { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } }, + { "slx", SHORT_2, 1, IU, PAR|RF0, 0x460b, 0x7e1f, { RDST } }, + { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } }, + { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } }, + { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } }, + { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } }, + { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } }, + { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } }, + { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } }, + { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } }, + { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } }, + { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, + { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } }, + { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } }, + { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, + { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } }, + { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } }, + { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } }, + { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } }, + { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } }, + { "sub2w", SHORT_2, 1, IU, PAR|WCAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } }, + { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } }, + { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } }, + { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } }, + { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { 0, 0, 0, 0, 0, 0, 0, { 0 } }, +}; + + diff --git a/external/gpl3/gdb/dist/opcodes/d30v-dis.c b/external/gpl3/gdb/dist/opcodes/d30v-dis.c new file mode 100644 index 000000000000..5f5d07fcd8e0 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/d30v-dis.c @@ -0,0 +1,398 @@ +/* Disassemble D30V instructions. + Copyright 1997, 1998, 2000, 2001, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d30v.h" +#include "dis-asm.h" +#include "opintl.h" + +#define PC_MASK 0xFFFFFFFF + +/* Return 0 if lookup fails, + 1 if found and only one form, + 2 if found and there are short and long forms. */ + +static int +lookup_opcode (struct d30v_insn *insn, long num, int is_long) +{ + int i = 0, op_index; + struct d30v_format *f; + struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table; + int op1 = (num >> 25) & 0x7; + int op2 = (num >> 20) & 0x1f; + int mod = (num >> 18) & 0x3; + + /* Find the opcode. */ + do + { + if ((op->op1 == op1) && (op->op2 == op2)) + break; + op++; + } + while (op->name); + + if (!op || !op->name) + return 0; + + while (op->op1 == op1 && op->op2 == op2) + { + /* Scan through all the formats for the opcode. */ + op_index = op->format[i++]; + do + { + f = (struct d30v_format *) &d30v_format_table[op_index]; + while (f->form == op_index) + { + if ((!is_long || f->form >= LONG) && (f->modifier == mod)) + { + insn->form = f; + break; + } + f++; + } + if (insn->form) + break; + } + while ((op_index = op->format[i++]) != 0); + if (insn->form) + break; + op++; + i = 0; + } + if (insn->form == NULL) + return 0; + + insn->op = op; + insn->ecc = (num >> 28) & 0x7; + if (op->format[1]) + return 2; + else + return 1; +} + +static int +extract_value (long long num, struct d30v_operand *oper, int is_long) +{ + int val; + int shift = 12 - oper->position; + int mask = (0xFFFFFFFF >> (32 - oper->bits)); + + if (is_long) + { + if (oper->bits == 32) + /* Piece together 32-bit constant. */ + val = ((num & 0x3FFFF) + | ((num & 0xFF00000) >> 2) + | ((num & 0x3F00000000LL) >> 6)); + else + val = (num >> (32 + shift)) & mask; + } + else + val = (num >> shift) & mask; + + if (oper->flags & OPERAND_SHIFT) + val <<= 3; + + return val; +} + +static void +print_insn (struct disassemble_info *info, + bfd_vma memaddr, + long long num, + struct d30v_insn *insn, + int is_long, + int show_ext) +{ + int val, opnum, need_comma = 0; + struct d30v_operand *oper; + int i, match, opind = 0, need_paren = 0, found_control = 0; + + (*info->fprintf_func) (info->stream, "%s", insn->op->name); + + /* Check for CMP or CMPU. */ + if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME) + { + opind++; + val = + extract_value (num, + (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]], + is_long); + (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]); + } + + /* Add in ".s" or ".l". */ + if (show_ext == 2) + { + if (is_long) + (*info->fprintf_func) (info->stream, ".l"); + else + (*info->fprintf_func) (info->stream, ".s"); + } + + if (insn->ecc) + (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]); + + (*info->fprintf_func) (info->stream, "\t"); + + while ((opnum = insn->form->operands[opind++]) != 0) + { + int bits; + + oper = (struct d30v_operand *) &d30v_operand_table[opnum]; + bits = oper->bits; + if (oper->flags & OPERAND_SHIFT) + bits += 3; + + if (need_comma + && oper->flags != OPERAND_PLUS + && oper->flags != OPERAND_MINUS) + { + need_comma = 0; + (*info->fprintf_func) (info->stream, ", "); + } + + if (oper->flags == OPERAND_ATMINUS) + { + (*info->fprintf_func) (info->stream, "@-"); + continue; + } + if (oper->flags == OPERAND_MINUS) + { + (*info->fprintf_func) (info->stream, "-"); + continue; + } + if (oper->flags == OPERAND_PLUS) + { + (*info->fprintf_func) (info->stream, "+"); + continue; + } + if (oper->flags == OPERAND_ATSIGN) + { + (*info->fprintf_func) (info->stream, "@"); + continue; + } + if (oper->flags == OPERAND_ATPAR) + { + (*info->fprintf_func) (info->stream, "@("); + need_paren = 1; + continue; + } + + if (oper->flags == OPERAND_SPECIAL) + continue; + + val = extract_value (num, oper, is_long); + + if (oper->flags & OPERAND_REG) + { + match = 0; + if (oper->flags & OPERAND_CONTROL) + { + struct d30v_operand *oper3 = + (struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]]; + int id = extract_value (num, oper3, is_long); + + found_control = 1; + switch (id) + { + case 0: + val |= OPERAND_CONTROL; + break; + case 1: + case 2: + val = OPERAND_CONTROL + MAX_CONTROL_REG + id; + break; + case 3: + val |= OPERAND_FLAG; + break; + default: + fprintf (stderr, "illegal id (%d)\n", id); + } + } + else if (oper->flags & OPERAND_ACC) + val |= OPERAND_ACC; + else if (oper->flags & OPERAND_FLAG) + val |= OPERAND_FLAG; + for (i = 0; i < reg_name_cnt (); i++) + { + if (val == pre_defined_registers[i].value) + { + if (pre_defined_registers[i].pname) + (*info->fprintf_func) + (info->stream, "%s", pre_defined_registers[i].pname); + else + (*info->fprintf_func) + (info->stream, "%s", pre_defined_registers[i].name); + match = 1; + break; + } + } + if (match == 0) + { + /* This would only get executed if a register was not in + the register table. */ + (*info->fprintf_func) + (info->stream, _(""), val & 0x3F); + } + } + /* repeati has a relocation, but its first argument is a plain + immediate. OTOH instructions like djsri have a pc-relative + delay target, but an absolute jump target. Therefore, a test + of insn->op->reloc_flag is not specific enough; we must test + if the actual operand we are handling now is pc-relative. */ + else if (oper->flags & OPERAND_PCREL) + { + int neg = 0; + + /* IMM6S3 is unsigned. */ + if (oper->flags & OPERAND_SIGNED || bits == 32) + { + long max; + max = (1 << (bits - 1)); + if (val & max) + { + if (bits == 32) + val = -val; + else + val = -val & ((1 << bits) - 1); + neg = 1; + } + } + if (neg) + { + (*info->fprintf_func) (info->stream, "-%x\t(", val); + (*info->print_address_func) ((memaddr - val) & PC_MASK, info); + (*info->fprintf_func) (info->stream, ")"); + } + else + { + (*info->fprintf_func) (info->stream, "%x\t(", val); + (*info->print_address_func) ((memaddr + val) & PC_MASK, info); + (*info->fprintf_func) (info->stream, ")"); + } + } + else if (insn->op->reloc_flag == RELOC_ABS) + { + (*info->print_address_func) (val, info); + } + else + { + if (oper->flags & OPERAND_SIGNED) + { + int max = (1 << (bits - 1)); + + if (val & max) + { + val = -val; + if (bits < 32) + val &= ((1 << bits) - 1); + (*info->fprintf_func) (info->stream, "-"); + } + } + (*info->fprintf_func) (info->stream, "0x%x", val); + } + /* If there is another operand, then write a comma and space. */ + if (insn->form->operands[opind] && !(found_control && opind == 2)) + need_comma = 1; + } + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + +int +print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info) +{ + int status, result; + bfd_byte buffer[12]; + unsigned long in1, in2; + struct d30v_insn insn; + long long num; + + insn.form = NULL; + + info->bytes_per_line = 8; + info->bytes_per_chunk = 4; + info->display_endian = BFD_ENDIAN_BIG; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + in1 = bfd_getb32 (buffer); + + status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info); + if (status != 0) + { + info->bytes_per_line = 8; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1); + else + print_insn (info, memaddr, (long long) in1, &insn, 0, result); + return 4; + } + in2 = bfd_getb32 (buffer); + + if (in1 & in2 & FM01) + { + /* LONG instruction. */ + if (!(result = lookup_opcode (&insn, in1, 1))) + { + (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2); + return 8; + } + num = (long long) in1 << 32 | in2; + print_insn (info, memaddr, num, &insn, 1, result); + } + else + { + num = in1; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1); + else + print_insn (info, memaddr, num, &insn, 0, result); + + switch (((in1 >> 31) << 1) | (in2 >> 31)) + { + case 0: + (*info->fprintf_func) (info->stream, "\t||\t"); + break; + case 1: + (*info->fprintf_func) (info->stream, "\t->\t"); + break; + case 2: + (*info->fprintf_func) (info->stream, "\t<-\t"); + default: + break; + } + + insn.form = NULL; + num = in2; + if (!(result = lookup_opcode (&insn, in2, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in2); + else + print_insn (info, memaddr, num, &insn, 0, result); + } + return 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/d30v-opc.c b/external/gpl3/gdb/dist/opcodes/d30v-opc.c new file mode 100644 index 000000000000..806fb3c64763 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/d30v-opc.c @@ -0,0 +1,518 @@ +/* d30v-opc.c -- D30V opcode list + Copyright 1997, 1998, 1999, 2000, 2005, 2007 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/d30v.h" + +/* This table is sorted. + If you add anything, it MUST be in alphabetical order. + The first field is the name the assembler uses when looking + up orcodes. The second field is the name the disassembler will use. + This allows the assembler to assemble references to r63 (for example) + or "sp". The disassembler will always use the preferred form (sp). */ +const struct pd_reg pre_defined_registers[] = +{ + { "a0", NULL, OPERAND_ACC + 0 }, + { "a1", NULL, OPERAND_ACC + 1 }, + { "bpc", NULL, OPERAND_CONTROL + 3 }, + { "bpsw", NULL, OPERAND_CONTROL + 1 }, + { "c", "c", OPERAND_FLAG + 7 }, + { "cr0", "psw", OPERAND_CONTROL }, + { "cr1", "bpsw", OPERAND_CONTROL + 1 }, + { "cr10", "mod_s", OPERAND_CONTROL + 10 }, + { "cr11", "mod_e", OPERAND_CONTROL + 11 }, + { "cr12", NULL, OPERAND_CONTROL + 12 }, + { "cr13", NULL, OPERAND_CONTROL + 13 }, + { "cr14", "iba", OPERAND_CONTROL + 14 }, + { "cr15", "eit_vb", OPERAND_CONTROL + 15 }, + { "cr16", "int_s", OPERAND_CONTROL + 16 }, + { "cr17", "int_m", OPERAND_CONTROL + 17 }, + { "cr18", NULL, OPERAND_CONTROL + 18 }, + { "cr19", NULL, OPERAND_CONTROL + 19 }, + { "cr2", "pc", OPERAND_CONTROL + 2 }, + { "cr20", NULL, OPERAND_CONTROL + 20 }, + { "cr21", NULL, OPERAND_CONTROL + 21 }, + { "cr22", NULL, OPERAND_CONTROL + 22 }, + { "cr23", NULL, OPERAND_CONTROL + 23 }, + { "cr24", NULL, OPERAND_CONTROL + 24 }, + { "cr25", NULL, OPERAND_CONTROL + 25 }, + { "cr26", NULL, OPERAND_CONTROL + 26 }, + { "cr27", NULL, OPERAND_CONTROL + 27 }, + { "cr28", NULL, OPERAND_CONTROL + 28 }, + { "cr29", NULL, OPERAND_CONTROL + 29 }, + { "cr3", "bpc", OPERAND_CONTROL + 3 }, + { "cr30", NULL, OPERAND_CONTROL + 30 }, + { "cr31", NULL, OPERAND_CONTROL + 31 }, + { "cr32", NULL, OPERAND_CONTROL + 32 }, + { "cr33", NULL, OPERAND_CONTROL + 33 }, + { "cr34", NULL, OPERAND_CONTROL + 34 }, + { "cr35", NULL, OPERAND_CONTROL + 35 }, + { "cr36", NULL, OPERAND_CONTROL + 36 }, + { "cr37", NULL, OPERAND_CONTROL + 37 }, + { "cr38", NULL, OPERAND_CONTROL + 38 }, + { "cr39", NULL, OPERAND_CONTROL + 39 }, + { "cr4", "dpsw", OPERAND_CONTROL + 4 }, + { "cr40", NULL, OPERAND_CONTROL + 40 }, + { "cr41", NULL, OPERAND_CONTROL + 41 }, + { "cr42", NULL, OPERAND_CONTROL + 42 }, + { "cr43", NULL, OPERAND_CONTROL + 43 }, + { "cr44", NULL, OPERAND_CONTROL + 44 }, + { "cr45", NULL, OPERAND_CONTROL + 45 }, + { "cr46", NULL, OPERAND_CONTROL + 46 }, + { "cr47", NULL, OPERAND_CONTROL + 47 }, + { "cr48", NULL, OPERAND_CONTROL + 48 }, + { "cr49", NULL, OPERAND_CONTROL + 49 }, + { "cr5","dpc", OPERAND_CONTROL + 5 }, + { "cr50", NULL, OPERAND_CONTROL + 50 }, + { "cr51", NULL, OPERAND_CONTROL + 51 }, + { "cr52", NULL, OPERAND_CONTROL + 52 }, + { "cr53", NULL, OPERAND_CONTROL + 53 }, + { "cr54", NULL, OPERAND_CONTROL + 54 }, + { "cr55", NULL, OPERAND_CONTROL + 55 }, + { "cr56", NULL, OPERAND_CONTROL + 56 }, + { "cr57", NULL, OPERAND_CONTROL + 57 }, + { "cr58", NULL, OPERAND_CONTROL + 58 }, + { "cr59", NULL, OPERAND_CONTROL + 59 }, + { "cr6", NULL, OPERAND_CONTROL + 6 }, + { "cr60", NULL, OPERAND_CONTROL + 60 }, + { "cr61", NULL, OPERAND_CONTROL + 61 }, + { "cr62", NULL, OPERAND_CONTROL + 62 }, + { "cr63", NULL, OPERAND_CONTROL + 63 }, + { "cr7", "rpt_c", OPERAND_CONTROL + 7 }, + { "cr8", "rpt_s", OPERAND_CONTROL + 8 }, + { "cr9", "rpt_e", OPERAND_CONTROL + 9 }, + { "dpc", NULL, OPERAND_CONTROL + 5 }, + { "dpsw", NULL, OPERAND_CONTROL + 4 }, + { "eit_vb", NULL, OPERAND_CONTROL + 15 }, + { "f0", NULL, OPERAND_FLAG + 0 }, + { "f1", NULL, OPERAND_FLAG + 1 }, + { "f2", NULL, OPERAND_FLAG + 2 }, + { "f3", NULL, OPERAND_FLAG + 3 }, + { "f4", "s", OPERAND_FLAG + 4 }, + { "f5", "v", OPERAND_FLAG + 5 }, + { "f6", "va", OPERAND_FLAG + 6 }, + { "f7", "c", OPERAND_FLAG + 7 }, + { "iba", NULL, OPERAND_CONTROL + 14 }, + { "int_m", NULL, OPERAND_CONTROL + 17 }, + { "int_s", NULL, OPERAND_CONTROL + 16 }, + { "link", "r62", 62 }, + { "mod_e", NULL, OPERAND_CONTROL + 11 }, + { "mod_s", NULL, OPERAND_CONTROL + 10 }, + { "pc", NULL, OPERAND_CONTROL + 2 }, + { "psw", NULL, OPERAND_CONTROL }, + { "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 }, + { "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 }, + { "r0", NULL, 0 }, + { "r1", NULL, 1 }, + { "r10", NULL, 10 }, + { "r11", NULL, 11 }, + { "r12", NULL, 12 }, + { "r13", NULL, 13 }, + { "r14", NULL, 14 }, + { "r15", NULL, 15 }, + { "r16", NULL, 16 }, + { "r17", NULL, 17 }, + { "r18", NULL, 18 }, + { "r19", NULL, 19 }, + { "r2", NULL, 2 }, + { "r20", NULL, 20 }, + { "r21", NULL, 21 }, + { "r22", NULL, 22 }, + { "r23", NULL, 23 }, + { "r24", NULL, 24 }, + { "r25", NULL, 25 }, + { "r26", NULL, 26 }, + { "r27", NULL, 27 }, + { "r28", NULL, 28 }, + { "r29", NULL, 29 }, + { "r3", NULL, 3 }, + { "r30", NULL, 30 }, + { "r31", NULL, 31 }, + { "r32", NULL, 32 }, + { "r33", NULL, 33 }, + { "r34", NULL, 34 }, + { "r35", NULL, 35 }, + { "r36", NULL, 36 }, + { "r37", NULL, 37 }, + { "r38", NULL, 38 }, + { "r39", NULL, 39 }, + { "r4", NULL, 4 }, + { "r40", NULL, 40 }, + { "r41", NULL, 41 }, + { "r42", NULL, 42 }, + { "r43", NULL, 43 }, + { "r44", NULL, 44 }, + { "r45", NULL, 45 }, + { "r46", NULL, 46 }, + { "r47", NULL, 47 }, + { "r48", NULL, 48 }, + { "r49", NULL, 49 }, + { "r5", NULL, 5 }, + { "r50", NULL, 50 }, + { "r51", NULL, 51 }, + { "r52", NULL, 52 }, + { "r53", NULL, 53 }, + { "r54", NULL, 54 }, + { "r55", NULL, 55 }, + { "r56", NULL, 56 }, + { "r57", NULL, 57 }, + { "r58", NULL, 58 }, + { "r59", NULL, 59 }, + { "r6", NULL, 6 }, + { "r60", NULL, 60 }, + { "r61", NULL, 61 }, + { "r62", "link", 62 }, + { "r63", "sp", 63 }, + { "r7", NULL, 7 }, + { "r8", NULL, 8 }, + { "r9", NULL, 9 }, + { "rpt_c", NULL, OPERAND_CONTROL + 7 }, + { "rpt_e", NULL, OPERAND_CONTROL + 9 }, + { "rpt_s", NULL, OPERAND_CONTROL + 8 }, + { "s", NULL, OPERAND_FLAG + 4 }, + { "sp", NULL, 63 }, + { "v", NULL, OPERAND_FLAG + 5 }, + { "va", NULL, OPERAND_FLAG + 6 }, +}; + +int +reg_name_cnt (void) +{ + return sizeof (pre_defined_registers) / sizeof (struct pd_reg); +} + +/* OPCODE TABLE. + The format of this table is defined in opcode/d30v.h. */ + +const struct d30v_opcode d30v_opcode_table[] = +{ + { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, + { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 }, + { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, + { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 }, + { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 }, + { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, + { "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 }, + { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, + { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, + { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 }, + { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 }, + { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, + { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, + { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, + { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, + { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, + { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, + { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, + { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 }, + { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, + { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, + { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 }, + { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, + { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, + { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 }, + { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 }, + { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 }, + { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, + { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, + { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, + { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, + { "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 }, + { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, + { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, + { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 }, + { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 }, + { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, + { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 }, + { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 }, + { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 }, + { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 }, + { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, + { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 }, + { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 }, + { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, +}; + + +/* Now define the operand types. + Format is length, bits, position, flags. */ + +const struct d30v_operand d30v_operand_table[] = +{ +#define UNUSED (0) + { 0, 0, 0, 0 }, +#define Ra (UNUSED + 1) + { 6, 6, 0, OPERAND_REG | OPERAND_DEST }, +#define Ra2 (Ra + 1) + { 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG }, +#define Ra3 (Ra2 + 1) + { 6, 6, 0, OPERAND_REG }, +#define Rb (Ra3 + 1) + { 6, 6, 6, OPERAND_REG }, +#define Rb2 (Rb + 1) + { 6, 6, 6, OPERAND_REG | OPERAND_DEST }, +#define Rc (Rb2 + 1) + { 6, 6, 12, OPERAND_REG }, +#define Aa (Rc + 1) + { 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST }, +#define Ab (Aa + 1) + { 6, 1, 6, OPERAND_ACC | OPERAND_REG }, +#define IMM5 (Ab + 1) + { 6, 5, 12, OPERAND_NUM }, +#define IMM5U (IMM5 + 1) + { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */ +#define IMM5S3 (IMM5U + 1) + { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */ +#define IMM6 (IMM5S3 + 1) + { 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED }, +#define IMM6U (IMM6 + 1) + { 6, 6, 0, OPERAND_NUM }, +#define IMM6U2 (IMM6U + 1) + { 6, 6, 12, OPERAND_NUM }, +#define REL6S3 (IMM6U2 + 1) + { 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL }, +#define REL12S3 (REL6S3 + 1) + { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL }, +#define IMM12S3 (REL12S3 + 1) + { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT }, +#define REL18S3 (IMM12S3 + 1) + { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL }, +#define IMM18S3 (REL18S3 + 1) + { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT }, +#define REL32 (IMM18S3 + 1) + { 32, 32, 0, OPERAND_NUM | OPERAND_PCREL }, +#define IMM32 (REL32 + 1) + { 32, 32, 0, OPERAND_NUM }, +#define Fa (IMM32 + 1) + { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, +#define Fb (Fa + 1) + { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, +#define Fc (Fb + 1) + { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, +#define ATSIGN (Fc + 1) + { 0, 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* Postincrement. */ + { 0, 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* Postdecrement. */ + { 0, 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* Predecrement. */ + { 0, 0, 0, OPERAND_ATMINUS}, +#define Ca (ATMINUS + 1) /* Control register. */ + { 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST}, +#define Cb (Ca + 1) /* Control register. */ + { 6, 6, 6, OPERAND_REG | OPERAND_CONTROL}, +#define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */ + { 3, 3, -3, OPERAND_NAME}, +#define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */ + { 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST}, +#define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */ + { 6, 2, 12, OPERAND_SPECIAL}, +}; + +/* Now we need to define the instruction formats. */ + +const struct d30v_format d30v_format_table[] = +{ + { 0, 0, { 0 } }, + { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ + { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ + { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ + { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ + { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ + { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */ + { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ + { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */ + { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ + { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ + { SHORT_B1, 0, { Rc } }, /* Rc */ + { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ + { SHORT_B2r, 2, { REL18S3 } }, /* rel18 */ + { SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */ + { SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */ + { SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */ + { SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */ + { SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */ + { SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */ + { SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */ + { SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */ + { SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */ + { SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */ + { SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */ + { SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */ + { SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */ + { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ + { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ + { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ + { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ + { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ + { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */ + { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ + { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ + { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ + { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ + { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ + { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */ + { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ + { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ + { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ + { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ + { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ + { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */ + { SHORT_MODINC, 1, { Rb2, IMM5 } }, /* Rb2,imm5 (modinc) */ + { SHORT_MODDEC, 3, { Rb2, IMM5 } }, /* Rb2,imm5 (moddec) */ + { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ + { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ + { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ + { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */ + { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */ + { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ + { SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ + { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ + { LONG_U, 2, { IMM32 } }, /* imm32 */ + { LONG_Ur, 2, { REL32 } }, /* rel32 */ + { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ + { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ + { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ + { LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */ + { LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */ + { LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */ + { LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */ + { LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */ + { LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */ + { LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */ + { 0, 0, { 0 } }, +}; + +const char *d30v_ecc_names[] = +{ + "al", + "tx", + "fx", + "xt", + "xf", + "tt", + "tf", + "res" +}; + +const char *d30v_cc_names[] = +{ + "eq", + "ne", + "gt", + "ge", + "lt", + "le", + "ps", + "ng", + NULL +}; diff --git a/external/gpl3/gdb/dist/opcodes/dep-in.sed b/external/gpl3/gdb/dist/opcodes/dep-in.sed new file mode 100644 index 000000000000..56403a978106 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/dep-in.sed @@ -0,0 +1,20 @@ +:loop +/\\$/N +s/\\\n */ /g +t loop + +s! \./! !g +s! @BFD_H@! $(BFD_H)!g +s!@INCDIR@!$(INCDIR)!g +s!@TOPDIR@/include!$(INCDIR)!g +s!@BFDDIR@!$(BFDDIR)!g +s!@TOPDIR@/bfd!$(BFDDIR)!g +s!@SRCDIR@/!!g +s! \.\./intl/libintl\.h!!g + +s/ *$// +s/ */ /g +s/^ */A/ +s/ / \\\ +B/g +$s/$/ \\/ diff --git a/external/gpl3/gdb/dist/opcodes/dis-buf.c b/external/gpl3/gdb/dist/opcodes/dis-buf.c new file mode 100644 index 000000000000..372fb96b2808 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/dis-buf.c @@ -0,0 +1,105 @@ +/* Disassemble from a buffer, for GNU. + Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005, + 2007, 2009, 2010 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include +#include "opintl.h" + +/* Get LENGTH bytes from info's buffer, at target address memaddr. + Transfer them to myaddr. */ +int +buffer_read_memory (bfd_vma memaddr, + bfd_byte *myaddr, + unsigned int length, + struct disassemble_info *info) +{ + unsigned int opb = info->octets_per_byte; + unsigned int end_addr_offset = length / opb; + unsigned int max_addr_offset = info->buffer_length / opb; + unsigned int octets = (memaddr - info->buffer_vma) * opb; + + if (memaddr < info->buffer_vma + || memaddr - info->buffer_vma > max_addr_offset + || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset) + /* Out of bounds. Use EIO because GDB uses it. */ + return EIO; + memcpy (myaddr, info->buffer + octets, length); + + return 0; +} + +/* Print an error message. We can assume that this is in response to + an error return from buffer_read_memory. */ + +void +perror_memory (int status, + bfd_vma memaddr, + struct disassemble_info *info) +{ + if (status != EIO) + /* Can't happen. */ + info->fprintf_func (info->stream, _("Unknown error %d\n"), status); + else + { + char buf[30]; + + /* Actually, address between memaddr and memaddr + len was + out of bounds. */ + sprintf_vma (buf, memaddr); + info->fprintf_func (info->stream, + _("Address 0x%s is out of bounds.\n"), buf); + } +} + +/* This could be in a separate file, to save miniscule amounts of space + in statically linked executables. */ + +/* Just print the address is hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ + +void +generic_print_address (bfd_vma addr, struct disassemble_info *info) +{ + char buf[30]; + + sprintf_vma (buf, addr); + (*info->fprintf_func) (info->stream, "0x%s", buf); +} + +/* Just return true. */ + +int +generic_symbol_at_address (bfd_vma addr ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ + return 1; +} + +/* Just return TRUE. */ + +bfd_boolean +generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ + return TRUE; +} diff --git a/external/gpl3/gdb/dist/opcodes/dis-init.c b/external/gpl3/gdb/dist/opcodes/dis-init.c new file mode 100644 index 000000000000..bd7ea8ba2f5b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/dis-init.c @@ -0,0 +1,46 @@ +/* Initialize "struct disassemble_info". + + Copyright 2003, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "bfd.h" + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func) +{ + memset (info, 0, sizeof (*info)); + + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->endian_code = info->endian; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->stream = stream; + info->read_memory_func = buffer_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->symbol_is_valid = generic_symbol_is_valid; + info->display_endian = BFD_ENDIAN_UNKNOWN; +} + diff --git a/external/gpl3/gdb/dist/opcodes/disassemble.c b/external/gpl3/gdb/dist/opcodes/disassemble.c new file mode 100644 index 000000000000..0fb35acf2f7e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/disassemble.c @@ -0,0 +1,547 @@ +/* Select disassembly routine for specified architecture. + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +#ifdef ARCH_all +#define ARCH_alpha +#define ARCH_arc +#define ARCH_arm +#define ARCH_avr +#define ARCH_bfin +#define ARCH_cr16 +#define ARCH_cris +#define ARCH_crx +#define ARCH_d10v +#define ARCH_d30v +#define ARCH_dlx +#define ARCH_fr30 +#define ARCH_frv +#define ARCH_h8300 +#define ARCH_h8500 +#define ARCH_hppa +#define ARCH_i370 +#define ARCH_i386 +#define ARCH_i860 +#define ARCH_i960 +#define ARCH_ia64 +#define ARCH_ip2k +#define ARCH_iq2000 +#define ARCH_lm32 +#define ARCH_m32c +#define ARCH_m32r +#define ARCH_m68hc11 +#define ARCH_m68hc12 +#define ARCH_m68k +#define ARCH_m88k +#define ARCH_mcore +#define ARCH_mep +#define ARCH_microblaze +#define ARCH_mips +#define ARCH_mmix +#define ARCH_mn10200 +#define ARCH_mn10300 +#define ARCH_moxie +#define ARCH_mt +#define ARCH_msp430 +#define ARCH_ns32k +#define ARCH_openrisc +#define ARCH_or32 +#define ARCH_pdp11 +#define ARCH_pj +#define ARCH_powerpc +#define ARCH_rs6000 +#define ARCH_rx +#define ARCH_s390 +#define ARCH_score +#define ARCH_sh +#define ARCH_sparc +#define ARCH_spu +#define ARCH_tic30 +#define ARCH_tic4x +#define ARCH_tic54x +#define ARCH_tic6x +#define ARCH_tic80 +#define ARCH_v850 +#define ARCH_vax +#define ARCH_w65 +#define ARCH_xstormy16 +#define ARCH_xc16x +#define ARCH_xtensa +#define ARCH_z80 +#define ARCH_z8k +#define INCLUDE_SHMEDIA +#endif + +#ifdef ARCH_m32c +#include "m32c-desc.h" +#endif + +disassembler_ftype +disassembler (abfd) + bfd *abfd; +{ + enum bfd_architecture a = bfd_get_arch (abfd); + disassembler_ftype disassemble; + + switch (a) + { + /* If you add a case to this table, also add it to the + ARCH_all definition right above this function. */ +#ifdef ARCH_alpha + case bfd_arch_alpha: + disassemble = print_insn_alpha; + break; +#endif +#ifdef ARCH_arc + case bfd_arch_arc: + disassemble = arc_get_disassembler (abfd); + break; +#endif +#ifdef ARCH_arm + case bfd_arch_arm: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_arm; + else + disassemble = print_insn_little_arm; + break; +#endif +#ifdef ARCH_avr + case bfd_arch_avr: + disassemble = print_insn_avr; + break; +#endif +#ifdef ARCH_bfin + case bfd_arch_bfin: + disassemble = print_insn_bfin; + break; +#endif +#ifdef ARCH_cr16 + case bfd_arch_cr16: + disassemble = print_insn_cr16; + break; +#endif +#ifdef ARCH_cris + case bfd_arch_cris: + disassemble = cris_get_disassembler (abfd); + break; +#endif +#ifdef ARCH_crx + case bfd_arch_crx: + disassemble = print_insn_crx; + break; +#endif +#ifdef ARCH_d10v + case bfd_arch_d10v: + disassemble = print_insn_d10v; + break; +#endif +#ifdef ARCH_d30v + case bfd_arch_d30v: + disassemble = print_insn_d30v; + break; +#endif +#ifdef ARCH_dlx + case bfd_arch_dlx: + /* As far as I know we only handle big-endian DLX objects. */ + disassemble = print_insn_dlx; + break; +#endif +#ifdef ARCH_h8300 + case bfd_arch_h8300: + if (bfd_get_mach (abfd) == bfd_mach_h8300h + || bfd_get_mach (abfd) == bfd_mach_h8300hn) + disassemble = print_insn_h8300h; + else if (bfd_get_mach (abfd) == bfd_mach_h8300s + || bfd_get_mach (abfd) == bfd_mach_h8300sn + || bfd_get_mach (abfd) == bfd_mach_h8300sx + || bfd_get_mach (abfd) == bfd_mach_h8300sxn) + disassemble = print_insn_h8300s; + else + disassemble = print_insn_h8300; + break; +#endif +#ifdef ARCH_h8500 + case bfd_arch_h8500: + disassemble = print_insn_h8500; + break; +#endif +#ifdef ARCH_hppa + case bfd_arch_hppa: + disassemble = print_insn_hppa; + break; +#endif +#ifdef ARCH_i370 + case bfd_arch_i370: + disassemble = print_insn_i370; + break; +#endif +#ifdef ARCH_i386 + case bfd_arch_i386: + case bfd_arch_l1om: + disassemble = print_insn_i386; + break; +#endif +#ifdef ARCH_i860 + case bfd_arch_i860: + disassemble = print_insn_i860; + break; +#endif +#ifdef ARCH_i960 + case bfd_arch_i960: + disassemble = print_insn_i960; + break; +#endif +#ifdef ARCH_ia64 + case bfd_arch_ia64: + disassemble = print_insn_ia64; + break; +#endif +#ifdef ARCH_ip2k + case bfd_arch_ip2k: + disassemble = print_insn_ip2k; + break; +#endif +#ifdef ARCH_fr30 + case bfd_arch_fr30: + disassemble = print_insn_fr30; + break; +#endif +#ifdef ARCH_lm32 + case bfd_arch_lm32: + disassemble = print_insn_lm32; + break; +#endif +#ifdef ARCH_m32r + case bfd_arch_m32r: + disassemble = print_insn_m32r; + break; +#endif +#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) + case bfd_arch_m68hc11: + disassemble = print_insn_m68hc11; + break; + case bfd_arch_m68hc12: + disassemble = print_insn_m68hc12; + break; +#endif +#ifdef ARCH_m68k + case bfd_arch_m68k: + disassemble = print_insn_m68k; + break; +#endif +#ifdef ARCH_m88k + case bfd_arch_m88k: + disassemble = print_insn_m88k; + break; +#endif +#ifdef ARCH_mt + case bfd_arch_mt: + disassemble = print_insn_mt; + break; +#endif +#ifdef ARCH_microblaze + case bfd_arch_microblaze: + disassemble = print_insn_microblaze; + break; +#endif +#ifdef ARCH_msp430 + case bfd_arch_msp430: + disassemble = print_insn_msp430; + break; +#endif +#ifdef ARCH_ns32k + case bfd_arch_ns32k: + disassemble = print_insn_ns32k; + break; +#endif +#ifdef ARCH_mcore + case bfd_arch_mcore: + disassemble = print_insn_mcore; + break; +#endif +#ifdef ARCH_mep + case bfd_arch_mep: + disassemble = print_insn_mep; + break; +#endif +#ifdef ARCH_mips + case bfd_arch_mips: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_mips; + else + disassemble = print_insn_little_mips; + break; +#endif +#ifdef ARCH_mmix + case bfd_arch_mmix: + disassemble = print_insn_mmix; + break; +#endif +#ifdef ARCH_mn10200 + case bfd_arch_mn10200: + disassemble = print_insn_mn10200; + break; +#endif +#ifdef ARCH_mn10300 + case bfd_arch_mn10300: + disassemble = print_insn_mn10300; + break; +#endif +#ifdef ARCH_openrisc + case bfd_arch_openrisc: + disassemble = print_insn_openrisc; + break; +#endif +#ifdef ARCH_or32 + case bfd_arch_or32: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_or32; + else + disassemble = print_insn_little_or32; + break; +#endif +#ifdef ARCH_pdp11 + case bfd_arch_pdp11: + disassemble = print_insn_pdp11; + break; +#endif +#ifdef ARCH_pj + case bfd_arch_pj: + disassemble = print_insn_pj; + break; +#endif +#ifdef ARCH_powerpc + case bfd_arch_powerpc: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_powerpc; + else + disassemble = print_insn_little_powerpc; + break; +#endif +#ifdef ARCH_rs6000 + case bfd_arch_rs6000: + if (bfd_get_mach (abfd) == bfd_mach_ppc_620) + disassemble = print_insn_big_powerpc; + else + disassemble = print_insn_rs6000; + break; +#endif +#ifdef ARCH_rx + case bfd_arch_rx: + disassemble = print_insn_rx; + break; +#endif +#ifdef ARCH_s390 + case bfd_arch_s390: + disassemble = print_insn_s390; + break; +#endif +#ifdef ARCH_score + case bfd_arch_score: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_score; + else + disassemble = print_insn_little_score; + break; +#endif +#ifdef ARCH_sh + case bfd_arch_sh: + disassemble = print_insn_sh; + break; +#endif +#ifdef ARCH_sparc + case bfd_arch_sparc: + disassemble = print_insn_sparc; + break; +#endif +#ifdef ARCH_spu + case bfd_arch_spu: + disassemble = print_insn_spu; + break; +#endif +#ifdef ARCH_tic30 + case bfd_arch_tic30: + disassemble = print_insn_tic30; + break; +#endif +#ifdef ARCH_tic4x + case bfd_arch_tic4x: + disassemble = print_insn_tic4x; + break; +#endif +#ifdef ARCH_tic54x + case bfd_arch_tic54x: + disassemble = print_insn_tic54x; + break; +#endif +#ifdef ARCH_tic6x + case bfd_arch_tic6x: + disassemble = print_insn_tic6x; + break; +#endif +#ifdef ARCH_tic80 + case bfd_arch_tic80: + disassemble = print_insn_tic80; + break; +#endif +#ifdef ARCH_v850 + case bfd_arch_v850: + disassemble = print_insn_v850; + break; +#endif +#ifdef ARCH_w65 + case bfd_arch_w65: + disassemble = print_insn_w65; + break; +#endif +#ifdef ARCH_xstormy16 + case bfd_arch_xstormy16: + disassemble = print_insn_xstormy16; + break; +#endif +#ifdef ARCH_xc16x + case bfd_arch_xc16x: + disassemble = print_insn_xc16x; + break; +#endif +#ifdef ARCH_xtensa + case bfd_arch_xtensa: + disassemble = print_insn_xtensa; + break; +#endif +#ifdef ARCH_z80 + case bfd_arch_z80: + disassemble = print_insn_z80; + break; +#endif +#ifdef ARCH_z8k + case bfd_arch_z8k: + if (bfd_get_mach(abfd) == bfd_mach_z8001) + disassemble = print_insn_z8001; + else + disassemble = print_insn_z8002; + break; +#endif +#ifdef ARCH_vax + case bfd_arch_vax: + disassemble = print_insn_vax; + break; +#endif +#ifdef ARCH_frv + case bfd_arch_frv: + disassemble = print_insn_frv; + break; +#endif +#ifdef ARCH_moxie + case bfd_arch_moxie: + disassemble = print_insn_moxie; + break; +#endif +#ifdef ARCH_iq2000 + case bfd_arch_iq2000: + disassemble = print_insn_iq2000; + break; +#endif +#ifdef ARCH_m32c + case bfd_arch_m32c: + disassemble = print_insn_m32c; + break; +#endif + default: + return 0; + } + return disassemble; +} + +void +disassembler_usage (stream) + FILE * stream ATTRIBUTE_UNUSED; +{ +#ifdef ARCH_arm + print_arm_disassembler_options (stream); +#endif +#ifdef ARCH_mips + print_mips_disassembler_options (stream); +#endif +#ifdef ARCH_powerpc + print_ppc_disassembler_options (stream); +#endif +#ifdef ARCH_i386 + print_i386_disassembler_options (stream); +#endif +#ifdef ARCH_s390 + print_s390_disassembler_options (stream); +#endif + + return; +} + +void +disassemble_init_for_target (struct disassemble_info * info) +{ + if (info == NULL) + return; + + switch (info->arch) + { +#ifdef ARCH_arm + case bfd_arch_arm: + info->symbol_is_valid = arm_symbol_is_valid; + info->disassembler_needs_relocs = TRUE; + break; +#endif +#ifdef ARCH_ia64 + case bfd_arch_ia64: + info->skip_zeroes = 16; + break; +#endif +#ifdef ARCH_tic4x + case bfd_arch_tic4x: + info->skip_zeroes = 32; + break; +#endif +#ifdef ARCH_mep + case bfd_arch_mep: + info->skip_zeroes = 256; + info->skip_zeroes_at_end = 0; + break; +#endif +#ifdef ARCH_m32c + case bfd_arch_m32c: + /* This processor in fact is little endian. The value set here + reflects the way opcodes are written in the cgen description. */ + info->endian = BFD_ENDIAN_BIG; + if (! info->insn_sets) + { + info->insn_sets = cgen_bitset_create (ISA_MAX); + if (info->mach == bfd_mach_m16c) + cgen_bitset_set (info->insn_sets, ISA_M16C); + else + cgen_bitset_set (info->insn_sets, ISA_M32C); + } + break; +#endif + default: + break; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/dlx-dis.c b/external/gpl3/gdb/dist/opcodes/dlx-dis.c new file mode 100644 index 000000000000..aca9db45d964 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/dlx-dis.c @@ -0,0 +1,514 @@ +/* Instruction printing code for the DLX Microprocessor + Copyright 2002, 2005, 2007, 2010 Free Software Foundation, Inc. + Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/dlx.h" + +#define R_ERROR 0x1 +#define R_TYPE 0x2 +#define ILD_TYPE 0x3 +#define IST_TYPE 0x4 +#define IAL_TYPE 0x5 +#define IBR_TYPE 0x6 +#define IJ_TYPE 0x7 +#define IJR_TYPE 0x8 +#define NIL 0x9 + +#define OPC(x) ((x >> 26) & 0x3F) +#define FUNC(x) (x & 0x7FF) + +unsigned char opc, rs1, rs2, rd; +unsigned long imm26, imm16, func, current_insn_addr; + +/* Print one instruction from MEMADDR on INFO->STREAM. + Return the size of the instruction (always 4 on dlx). */ + +static unsigned char +dlx_get_opcode (unsigned long opcode) +{ + return (unsigned char) ((opcode >> 26) & 0x3F); +} + +static unsigned char +dlx_get_rs1 (unsigned long opcode) +{ + return (unsigned char) ((opcode >> 21) & 0x1F); +} + +static unsigned char +dlx_get_rs2 (unsigned long opcode) +{ + return (unsigned char) ((opcode >> 16) & 0x1F); +} + +static unsigned char +dlx_get_rdR (unsigned long opcode) +{ + return (unsigned char) ((opcode >> 11) & 0x1F); +} + +static unsigned long +dlx_get_func (unsigned long opcode) +{ + return (unsigned char) (opcode & 0x7FF); +} + +static unsigned long +dlx_get_imm16 (unsigned long opcode) +{ + return (unsigned long) (opcode & 0xFFFF); +} + +static unsigned long +dlx_get_imm26 (unsigned long opcode) +{ + return (unsigned long) (opcode & 0x03FFFFFF); +} + +/* Fill the opcode to the max length. */ + +static void +operand_deliminator (struct disassemble_info *info, char *ptr) +{ + int difft = 8 - (int) strlen (ptr); + + while (difft > 0) + { + (*info->fprintf_func) (info->stream, "%c", ' '); + difft -= 1; + } +} + +/* Process the R-type opcode. */ + +static unsigned char +dlx_r_type (struct disassemble_info *info) +{ + unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */ + int r_opc_num = (sizeof r_opc) / (sizeof (char)); + struct _r_opcode + { + unsigned long func; + char *name; + } + dlx_r_opcode[] = + { + { NOPF, "nop" }, /* NOP */ + { ADDF, "add" }, /* Add */ + { ADDUF, "addu" }, /* Add Unsigned */ + { SUBF, "sub" }, /* SUB */ + { SUBUF, "subu" }, /* Sub Unsigned */ + { MULTF, "mult" }, /* MULTIPLY */ + { MULTUF, "multu" }, /* MULTIPLY Unsigned */ + { DIVF, "div" }, /* DIVIDE */ + { DIVUF, "divu" }, /* DIVIDE Unsigned */ + { ANDF, "and" }, /* AND */ + { ORF, "or" }, /* OR */ + { XORF, "xor" }, /* Exclusive OR */ + { SLLF, "sll" }, /* SHIFT LEFT LOGICAL */ + { SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */ + { SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */ + { SEQF, "seq" }, /* Set if equal */ + { SNEF, "sne" }, /* Set if not equal */ + { SLTF, "slt" }, /* Set if less */ + { SGTF, "sgt" }, /* Set if greater */ + { SLEF, "sle" }, /* Set if less or equal */ + { SGEF, "sge" }, /* Set if greater or equal */ + { SEQUF, "sequ" }, /* Set if equal */ + { SNEUF, "sneu" }, /* Set if not equal */ + { SLTUF, "sltu" }, /* Set if less */ + { SGTUF, "sgtu" }, /* Set if greater */ + { SLEUF, "sleu" }, /* Set if less or equal */ + { SGEUF, "sgeu" }, /* Set if greater or equal */ + { MVTSF, "mvts" }, /* Move to special register */ + { MVFSF, "mvfs" }, /* Move from special register */ + { BSWAPF, "bswap" }, /* Byte swap ?? */ + { LUTF, "lut" } /* ????????? ?? */ + }; + int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]); + int idx; + + for (idx = 0; idx < r_opc_num; idx++) + { + if (r_opc[idx] != opc) + continue; + else + break; + } + + if (idx == r_opc_num) + return NIL; + + for (idx = 0 ; idx < dlx_r_opcode_num; idx++) + if (dlx_r_opcode[idx].func == func) + { + (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name); + + if (func != NOPF) + { + /* This is not a nop. */ + operand_deliminator (info, dlx_r_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rd); + (*info->fprintf_func) (info->stream, "r%d", (int)rs1); + if (func != MVTSF && func != MVFSF) + (*info->fprintf_func) (info->stream, ",r%d", (int)rs2); + } + return (unsigned char) R_TYPE; + } + + return (unsigned char) R_ERROR; +} + +/* Process the memory read opcode. */ + +static unsigned char +dlx_load_type (struct disassemble_info* info) +{ + struct _load_opcode + { + unsigned long opcode; + char *name; + } + dlx_load_opcode[] = + { + { OPC(LHIOP), "lhi" }, /* Load HI to register. */ + { OPC(LBOP), "lb" }, /* load byte sign extended. */ + { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ + { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ + { OPC(LHOP), "lh" }, /* load halfword sign extended. */ + { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ + { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ + { OPC(LWOP), "lw" }, /* load word. */ + { OPC(LSWOP), "ldstw" } /* load store word. */ + }; + int dlx_load_opcode_num = + (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_load_opcode_num; idx++) + if (dlx_load_opcode[idx].opcode == opc) + { + if (opc == OPC (LHIOP)) + { + (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); + operand_deliminator (info, dlx_load_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); + } + else + { + (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); + operand_deliminator (info, dlx_load_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1); + } + + return (unsigned char) ILD_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the memory store opcode. */ + +static unsigned char +dlx_store_type (struct disassemble_info* info) +{ + struct _store_opcode + { + unsigned long opcode; + char *name; + } + dlx_store_opcode[] = + { + { OPC(SBOP), "sb" }, /* Store byte. */ + { OPC(SHOP), "sh" }, /* Store halfword. */ + { OPC(SWOP), "sw" }, /* Store word. */ + }; + int dlx_store_opcode_num = + (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_store_opcode_num; idx++) + if (dlx_store_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name); + operand_deliminator (info, dlx_store_opcode[idx].name); + (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1); + (*info->fprintf_func) (info->stream, "r%d", (int)rs2); + return (unsigned char) IST_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the Arithmetic and Logical I-TYPE opcode. */ + +static unsigned char +dlx_aluI_type (struct disassemble_info* info) +{ + struct _aluI_opcode + { + unsigned long opcode; + char *name; + } + dlx_aluI_opcode[] = + { + { OPC(ADDIOP), "addi" }, /* Store byte. */ + { OPC(ADDUIOP), "addui" }, /* Store halfword. */ + { OPC(SUBIOP), "subi" }, /* Store word. */ + { OPC(SUBUIOP), "subui" }, /* Store word. */ + { OPC(ANDIOP), "andi" }, /* Store word. */ + { OPC(ORIOP), "ori" }, /* Store word. */ + { OPC(XORIOP), "xori" }, /* Store word. */ + { OPC(SLLIOP), "slli" }, /* Store word. */ + { OPC(SRAIOP), "srai" }, /* Store word. */ + { OPC(SRLIOP), "srli" }, /* Store word. */ + { OPC(SEQIOP), "seqi" }, /* Store word. */ + { OPC(SNEIOP), "snei" }, /* Store word. */ + { OPC(SLTIOP), "slti" }, /* Store word. */ + { OPC(SGTIOP), "sgti" }, /* Store word. */ + { OPC(SLEIOP), "slei" }, /* Store word. */ + { OPC(SGEIOP), "sgei" }, /* Store word. */ + { OPC(SEQUIOP), "sequi" }, /* Store word. */ + { OPC(SNEUIOP), "sneui" }, /* Store word. */ + { OPC(SLTUIOP), "sltui" }, /* Store word. */ + { OPC(SGTUIOP), "sgtui" }, /* Store word. */ + { OPC(SLEUIOP), "sleui" }, /* Store word. */ + { OPC(SGEUIOP), "sgeui" }, /* Store word. */ +#if 0 + { OPC(MVTSOP), "mvts" }, /* Store word. */ + { OPC(MVFSOP), "mvfs" }, /* Store word. */ +#endif + }; + int dlx_aluI_opcode_num = + (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++) + if (dlx_aluI_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name); + operand_deliminator (info, dlx_aluI_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); + (*info->fprintf_func) (info->stream, "r%d,", (int)rs1); + (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); + + return (unsigned char) IAL_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the branch instruction. */ + +static unsigned char +dlx_br_type (struct disassemble_info* info) +{ + struct _br_opcode + { + unsigned long opcode; + char *name; + } + dlx_br_opcode[] = + { + { OPC(BEQOP), "beqz" }, /* Store byte. */ + { OPC(BNEOP), "bnez" } /* Store halfword. */ + }; + int dlx_br_opcode_num = + (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_br_opcode_num; idx++) + if (dlx_br_opcode[idx].opcode == opc) + { + if (imm16 & 0x00008000) + imm16 |= 0xFFFF0000; + + imm16 += (current_insn_addr + 4); + (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name); + operand_deliminator (info, dlx_br_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d,", (int) rs1); + (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16); + + return (unsigned char) IBR_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the jump instruction. */ + +static unsigned char +dlx_jmp_type (struct disassemble_info* info) +{ + struct _jmp_opcode + { + unsigned long opcode; + char *name; + } + dlx_jmp_opcode[] = + { + { OPC(JOP), "j" }, /* Store byte. */ + { OPC(JALOP), "jal" }, /* Store halfword. */ + { OPC(BREAKOP), "break" }, /* Store halfword. */ + { OPC(TRAPOP), "trap" }, /* Store halfword. */ + { OPC(RFEOP), "rfe" } /* Store halfword. */ + }; + int dlx_jmp_opcode_num = + (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++) + if (dlx_jmp_opcode[idx].opcode == opc) + { + if (imm26 & 0x02000000) + imm26 |= 0xFC000000; + + imm26 += (current_insn_addr + 4); + + (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name); + operand_deliminator (info, dlx_jmp_opcode[idx].name); + (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26); + + return (unsigned char) IJ_TYPE; + } + + return (unsigned char) NIL; +} + +/* Process the jump register instruction. */ + +static unsigned char +dlx_jr_type (struct disassemble_info* info) +{ + struct _jr_opcode + { + unsigned long opcode; + char *name; + } + dlx_jr_opcode[] = + { + { OPC(JROP), "jr" }, /* Store byte. */ + { OPC(JALROP), "jalr" } /* Store halfword. */ + }; + int dlx_jr_opcode_num = + (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]); + int idx; + + for (idx = 0 ; idx < dlx_jr_opcode_num; idx++) + if (dlx_jr_opcode[idx].opcode == opc) + { + (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name); + operand_deliminator (info, dlx_jr_opcode[idx].name); + (*info->fprintf_func) (info->stream, "r%d", (int)rs1); + return (unsigned char) IJR_TYPE; + } + + return (unsigned char) NIL; +} + +typedef unsigned char (* dlx_insn) (struct disassemble_info *); + +/* This is the main DLX insn handling routine. */ + +int +print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info) +{ + bfd_byte buffer[4]; + int insn_idx; + unsigned long insn_word; + dlx_insn dlx_insn_type[] = + { + dlx_r_type, + dlx_load_type, + dlx_store_type, + dlx_aluI_type, + dlx_br_type, + dlx_jmp_type, + dlx_jr_type, + (dlx_insn) NULL + }; + int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (dlx_insn))) - 1; + int status = + (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info); + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Now decode the insn */ + insn_word = bfd_getb32 (buffer); + opc = dlx_get_opcode (insn_word); + rs1 = dlx_get_rs1 (insn_word); + rs2 = dlx_get_rs2 (insn_word); + rd = dlx_get_rdR (insn_word); + func = dlx_get_func (insn_word); + imm16= dlx_get_imm16 (insn_word); + imm26= dlx_get_imm26 (insn_word); + +#if 0 + printf ("print_insn_big_dlx: opc = 0x%02x\n" + " rs1 = 0x%02x\n" + " rs2 = 0x%02x\n" + " rd = 0x%02x\n" + " func = 0x%08x\n" + " imm16 = 0x%08x\n" + " imm26 = 0x%08x\n", + opc, rs1, rs2, rd, func, imm16, imm26); +#endif + + /* Scan through all the insn type and print the insn out. */ + current_insn_addr = (unsigned long) memaddr; + + for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++) + switch ((dlx_insn_type[insn_idx]) (info)) + { + /* Found the correct opcode */ + case R_TYPE: + case ILD_TYPE: + case IST_TYPE: + case IAL_TYPE: + case IBR_TYPE: + case IJ_TYPE: + case IJR_TYPE: + return 4; + + /* Wrong insn type check next one. */ + default: + case NIL: + continue; + + /* All rest of the return code are not recongnized, treat it as error */ + /* we should never get here, I hope! */ + case R_ERROR: + return -1; + } + + if (insn_idx == dlx_insn_type_num) + /* Well, does not recoganize this opcode. */ + (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode"); + + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/fr30-asm.c b/external/gpl3/gdb/dist/opcodes/fr30-asm.c new file mode 100644 index 000000000000..ad0456e0cf8e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-asm.c @@ -0,0 +1,718 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +/* Handle register lists for LDMx and STMx. */ + +static int +parse_register_number (const char **strp) +{ + int regno; + + if (**strp < '0' || **strp > '9') + return -1; /* Error. */ + regno = **strp - '0'; + ++*strp; + + if (**strp >= '0' && **strp <= '9') + { + regno = regno * 10 + (**strp - '0'); + ++*strp; + } + + return regno; +} + +static const char * +parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep, + int high_low, /* 0 == high, 1 == low. */ + int load_store) /* 0 == load, 1 == store. */ +{ + *valuep = 0; + while (**strp && **strp != ')') + { + int regno; + + if (**strp != 'R' && **strp != 'r') + break; + ++*strp; + + regno = parse_register_number (strp); + if (regno == -1) + return _("Register number is not valid"); + if (regno > 7 && !high_low) + return _("Register must be between r0 and r7"); + if (regno < 8 && high_low) + return _("Register must be between r8 and r15"); + + if (high_low) + regno -= 8; + + if (load_store) /* Mask is reversed for store. */ + *valuep |= 0x80 >> regno; + else + *valuep |= 1 << regno; + + if (**strp == ',') + { + if (*(*strp + 1) == ')') + break; + ++*strp; + } + } + + if (!*strp || **strp != ')') + return _("Register list is not valid"); + + return NULL; +} + +static const char * +parse_low_register_list_ld (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_register_list (cd, strp, opindex, valuep, + 0 /* Low. */, 0 /* Load. */); +} + +static const char * +parse_hi_register_list_ld (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_register_list (cd, strp, opindex, valuep, + 1 /* High. */, 0 /* Load. */); +} + +static const char * +parse_low_register_list_st (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_register_list (cd, strp, opindex, valuep, + 0 /* Low. */, 1 /* Store. */); +} + +static const char * +parse_hi_register_list_st (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_register_list (cd, strp, opindex, valuep, + 1 /* High. */, 1 /* Store. */); +} + +/* -- */ + +const char * fr30_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +fr30_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case FR30_OPERAND_CRI : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRi); + break; + case FR30_OPERAND_CRJ : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRj); + break; + case FR30_OPERAND_R13 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r13, & junk); + break; + case FR30_OPERAND_R14 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r14, & junk); + break; + case FR30_OPERAND_R15 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r15, & junk); + break; + case FR30_OPERAND_RI : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ri); + break; + case FR30_OPERAND_RIC : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ric); + break; + case FR30_OPERAND_RJ : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rj); + break; + case FR30_OPERAND_RJC : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Rjc); + break; + case FR30_OPERAND_RS1 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs1); + break; + case FR30_OPERAND_RS2 : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_dr_names, & fields->f_Rs2); + break; + case FR30_OPERAND_CC : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CC, (unsigned long *) (& fields->f_cc)); + break; + case FR30_OPERAND_CCC : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_CCC, (unsigned long *) (& fields->f_ccc)); + break; + case FR30_OPERAND_DIR10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR10, (unsigned long *) (& fields->f_dir10)); + break; + case FR30_OPERAND_DIR8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR8, (unsigned long *) (& fields->f_dir8)); + break; + case FR30_OPERAND_DIR9 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_DIR9, (unsigned long *) (& fields->f_dir9)); + break; + case FR30_OPERAND_DISP10 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP10, (long *) (& fields->f_disp10)); + break; + case FR30_OPERAND_DISP8 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP8, (long *) (& fields->f_disp8)); + break; + case FR30_OPERAND_DISP9 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_DISP9, (long *) (& fields->f_disp9)); + break; + case FR30_OPERAND_I20 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I20, (unsigned long *) (& fields->f_i20)); + break; + case FR30_OPERAND_I32 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I32, (unsigned long *) (& fields->f_i32)); + break; + case FR30_OPERAND_I8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_I8, (unsigned long *) (& fields->f_i8)); + break; + case FR30_OPERAND_LABEL12 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL12, 0, NULL, & value); + fields->f_rel12 = value; + } + break; + case FR30_OPERAND_LABEL9 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL9, 0, NULL, & value); + fields->f_rel9 = value; + } + break; + case FR30_OPERAND_M4 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_M4, (long *) (& fields->f_m4)); + break; + case FR30_OPERAND_PS : + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_ps, & junk); + break; + case FR30_OPERAND_REGLIST_HI_LD : + errmsg = parse_hi_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_HI_LD, (unsigned long *) (& fields->f_reglist_hi_ld)); + break; + case FR30_OPERAND_REGLIST_HI_ST : + errmsg = parse_hi_register_list_st (cd, strp, FR30_OPERAND_REGLIST_HI_ST, (unsigned long *) (& fields->f_reglist_hi_st)); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + errmsg = parse_low_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_LOW_LD, (unsigned long *) (& fields->f_reglist_low_ld)); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + errmsg = parse_low_register_list_st (cd, strp, FR30_OPERAND_REGLIST_LOW_ST, (unsigned long *) (& fields->f_reglist_low_st)); + break; + case FR30_OPERAND_S10 : + errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_S10, (long *) (& fields->f_s10)); + break; + case FR30_OPERAND_U10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U10, (unsigned long *) (& fields->f_u10)); + break; + case FR30_OPERAND_U4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4, (unsigned long *) (& fields->f_u4)); + break; + case FR30_OPERAND_U4C : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U4C, (unsigned long *) (& fields->f_u4c)); + break; + case FR30_OPERAND_U8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_U8, (unsigned long *) (& fields->f_u8)); + break; + case FR30_OPERAND_UDISP6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FR30_OPERAND_UDISP6, (unsigned long *) (& fields->f_udisp6)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const fr30_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +fr30_cgen_init_asm (CGEN_CPU_DESC cd) +{ + fr30_cgen_init_opcode_table (cd); + fr30_cgen_init_ibld_table (cd); + cd->parse_handlers = & fr30_cgen_parse_handlers[0]; + cd->parse_operand = fr30_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by fr30_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +fr30_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +fr30_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! fr30_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/fr30-desc.c b/external/gpl3/gdb/dist/opcodes/fr30-desc.c new file mode 100644 index 000000000000..d80cd488586b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-desc.c @@ -0,0 +1,1748 @@ +/* CPU data for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "fr30", MACH_FR30 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "fr30", ISA_FR30 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA fr30_cgen_isa_table[] = { + { "fr30", 16, 16, 16, 48 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH fr30_cgen_mach_table[] = { + { "fr30", "fr30", MACH_FR30, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ac", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_gr_names = +{ + & fr30_cgen_opval_gr_names_entries[0], + 19, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] = +{ + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_cr_names = +{ + & fr30_cgen_opval_cr_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] = +{ + { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "rp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "usp", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_dr_names = +{ + & fr30_cgen_opval_dr_names_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] = +{ + { "ps", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_ps = +{ + & fr30_cgen_opval_h_ps_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] = +{ + { "r13", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r13 = +{ + & fr30_cgen_opval_h_r13_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] = +{ + { "r14", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r14 = +{ + & fr30_cgen_opval_h_r14_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] = +{ + { "r15", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD fr30_cgen_opval_h_r15 = +{ + & fr30_cgen_opval_h_r15_entries[0], + 1, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY fr30_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & fr30_cgen_ifld_table[0]; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & fr30_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of fr30_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & fr30_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */ + +static void +fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & fr30_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (fr30_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = fr30_cgen_rebuild_tables; + fr30_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +fr30_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/fr30-desc.h b/external/gpl3/gdb/dist/opcodes/fr30-desc.h new file mode 100644 index 000000000000..b547fde2c941 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-desc.h @@ -0,0 +1,312 @@ +/* CPU data header for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef FR30_CPU_H +#define FR30_CPU_H + +#define CGEN_ARCH fr30 + +/* Given symbol S, return fr30_cgen_. */ +#define CGEN_SYM(s) fr30##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_FR30BF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 6 + +#define CGEN_INT_INSN_P 0 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 + +/* Enums. */ + +/* Enum declaration for insn op1 enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_A, OP1_B + , OP1_C, OP1_D, OP1_E, OP1_F +} INSN_OP1; + +/* Enum declaration for insn op2 enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_A, OP2_B + , OP2_C, OP2_D, OP2_E, OP2_F +} INSN_OP2; + +/* Enum declaration for insn op3 enums. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 + , OP3_4, OP3_5, OP3_6, OP3_7 + , OP3_8, OP3_9, OP3_A, OP3_B + , OP3_C, OP3_D, OP3_E, OP3_F +} INSN_OP3; + +/* Enum declaration for insn op4 enums. */ +typedef enum insn_op4 { + OP4_0 +} INSN_OP4; + +/* Enum declaration for insn op5 enums. */ +typedef enum insn_op5 { + OP5_0, OP5_1 +} INSN_OP5; + +/* Enum declaration for insn cc enums. */ +typedef enum insn_cc { + CC_RA, CC_NO, CC_EQ, CC_NE + , CC_C, CC_NC, CC_N, CC_P + , CC_V, CC_NV, CC_LT, CC_GE + , CC_LE, CC_GT, CC_LS, CC_HI +} INSN_CC; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 + , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 + , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 + , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 + , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 + , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 + , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 + , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 +} CR_NAMES; + +/* Enum declaration for . */ +typedef enum dr_names { + H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP + , H_DR_MDH, H_DR_MDL +} DR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_FR30, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_FR30, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for fr30 ifield types. */ +typedef enum ifield_type { + FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 + , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC + , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 + , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ + , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 + , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 + , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 + , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 + , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 + , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST + , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) FR30_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for fr30 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR + , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 + , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT + , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT + , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR + , HW_H_ILM, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + +/* Enum declaration for fr30 operand types. */ +typedef enum cgen_operand_type { + FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC + , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 + , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 + , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 + , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 + , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 + , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 + , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD + , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC + , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT + , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT + , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR + , FR30_OPERAND_ILM, FR30_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 49 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld fr30_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD fr30_cgen_opval_gr_names; +extern CGEN_KEYWORD fr30_cgen_opval_cr_names; +extern CGEN_KEYWORD fr30_cgen_opval_dr_names; +extern CGEN_KEYWORD fr30_cgen_opval_h_ps; +extern CGEN_KEYWORD fr30_cgen_opval_h_r13; +extern CGEN_KEYWORD fr30_cgen_opval_h_r14; +extern CGEN_KEYWORD fr30_cgen_opval_h_r15; + +extern const CGEN_HW_ENTRY fr30_cgen_hw_table[]; + + + +#endif /* FR30_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/fr30-dis.c b/external/gpl3/gdb/dist/opcodes/fr30-dis.c new file mode 100644 index 000000000000..d998dac3d42f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-dis.c @@ -0,0 +1,720 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ +static void +print_register_list (void * dis_info, + long value, + long offset, + int load_store) /* 0 == load, 1 == store. */ +{ + disassemble_info *info = dis_info; + int mask; + int reg_index = 0; + char * comma = ""; + + if (load_store) + mask = 0x80; + else + mask = 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "r%li", reg_index + offset); + comma = ","; + } + + for (reg_index = 1; reg_index <= 7; ++reg_index) + { + if (load_store) + mask >>= 1; + else + mask <<= 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset); + comma = ","; + } + } +} + +static void +print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_register_list (dis_info, value, 8, 0 /* Load. */); +} + +static void +print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_register_list (dis_info, value, 0, 0 /* Load. */); +} + +static void +print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_register_list (dis_info, value, 8, 1 /* Store. */); +} + +static void +print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_register_list (dis_info, value, 0, 1 /* Store. */); +} + +static void +print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "%ld", value); +} +/* -- */ + +void fr30_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +fr30_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case FR30_OPERAND_CRI : + print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0); + break; + case FR30_OPERAND_CRJ : + print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0); + break; + case FR30_OPERAND_R13 : + print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0); + break; + case FR30_OPERAND_R14 : + print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0); + break; + case FR30_OPERAND_R15 : + print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0); + break; + case FR30_OPERAND_RI : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0); + break; + case FR30_OPERAND_RIC : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0); + break; + case FR30_OPERAND_RJ : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0); + break; + case FR30_OPERAND_RJC : + print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0); + break; + case FR30_OPERAND_RS1 : + print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0); + break; + case FR30_OPERAND_RS2 : + print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0); + break; + case FR30_OPERAND_CC : + print_normal (cd, info, fields->f_cc, 0, pc, length); + break; + case FR30_OPERAND_CCC : + print_normal (cd, info, fields->f_ccc, 0|(1<f_dir10, 0, pc, length); + break; + case FR30_OPERAND_DIR8 : + print_normal (cd, info, fields->f_dir8, 0, pc, length); + break; + case FR30_OPERAND_DIR9 : + print_normal (cd, info, fields->f_dir9, 0, pc, length); + break; + case FR30_OPERAND_DISP10 : + print_normal (cd, info, fields->f_disp10, 0|(1<f_disp8, 0|(1<f_disp9, 0|(1<f_i20, 0|(1<f_i32, 0|(1<f_i8, 0|(1<f_rel12, 0|(1<f_rel9, 0|(1<f_m4, 0|(1<f_reglist_hi_ld, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_HI_ST : + print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length); + break; + case FR30_OPERAND_S10 : + print_normal (cd, info, fields->f_s10, 0|(1<f_u10, 0|(1<f_u4, 0|(1<f_u4c, 0|(1<f_u8, 0|(1<f_udisp6, 0|(1<print_handlers = & fr30_cgen_print_handlers[0]; + cd->print_operand = fr30_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! fr30_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_fr30 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_fr30 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + fr30_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/fr30-ibld.c b/external/gpl3/gdb/dist/opcodes/fr30-ibld.c new file mode 100644 index 000000000000..748747081b4f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-ibld.c @@ -0,0 +1,1479 @@ +/* Instruction building/extraction support for fr30. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * fr30_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +fr30_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FR30_OPERAND_CRI : + errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CRJ : + errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RIC : + errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RJ : + errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RJC : + errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RS1 : + errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_RS2 : + errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CC : + errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_CCC : + errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_DIR10 : + { + long value = fields->f_dir10; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_DIR8 : + errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_DIR9 : + { + long value = fields->f_dir9; + value = ((USI) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_DISP10 : + { + long value = fields->f_disp10; + value = ((SI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp8, 0|(1<f_disp9; + value = ((SI) (value) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<> (16)); + FLD (f_i20_16) = ((FLD (f_i20)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer); + if (errmsg) + break; + } + break; + case FR30_OPERAND_I32 : + errmsg = insert_normal (cd, fields->f_i32, 0|(1<f_i8, 0, 0, 4, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_LABEL12 : + { + long value = fields->f_rel12; + value = ((SI) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_rel9; + value = ((SI) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_m4; + value = ((value) & (15)); + errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); + } + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_HI_ST : + errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_S10 : + { + long value = fields->f_s10; + value = ((SI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_u10; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); + } + break; + case FR30_OPERAND_U4 : + errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_U4C : + errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer); + break; + case FR30_OPERAND_U8 : + errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer); + break; + case FR30_OPERAND_UDISP6 : + { + long value = fields->f_udisp6; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int fr30_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +fr30_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FR30_OPERAND_CRI : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi); + break; + case FR30_OPERAND_CRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj); + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri); + break; + case FR30_OPERAND_RIC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric); + break; + case FR30_OPERAND_RJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj); + break; + case FR30_OPERAND_RJC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc); + break; + case FR30_OPERAND_RS1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1); + break; + case FR30_OPERAND_RS2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2); + break; + case FR30_OPERAND_CC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc); + break; + case FR30_OPERAND_CCC : + length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc); + break; + case FR30_OPERAND_DIR10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_dir10 = value; + } + break; + case FR30_OPERAND_DIR8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8); + break; + case FR30_OPERAND_DIR9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (1)); + fields->f_dir9 = value; + } + break; + case FR30_OPERAND_DISP10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp10 = value; + } + break; + case FR30_OPERAND_DISP8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp8); + break; + case FR30_OPERAND_DISP9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp9 = value; + } + break; + case FR30_OPERAND_I20 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16); + if (length <= 0) break; +{ + FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16))); +} + } + break; + case FR30_OPERAND_I32 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_i32); + break; + case FR30_OPERAND_I8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8); + break; + case FR30_OPERAND_LABEL12 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12 = value; + } + break; + case FR30_OPERAND_LABEL9 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel9 = value; + } + break; + case FR30_OPERAND_M4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); + value = ((value) | (((-1) << (4)))); + fields->f_m4 = value; + } + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld); + break; + case FR30_OPERAND_REGLIST_HI_ST : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st); + break; + case FR30_OPERAND_REGLIST_LOW_LD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld); + break; + case FR30_OPERAND_REGLIST_LOW_ST : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st); + break; + case FR30_OPERAND_S10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s10 = value; + } + break; + case FR30_OPERAND_U10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_u10 = value; + } + break; + case FR30_OPERAND_U4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4); + break; + case FR30_OPERAND_U4C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c); + break; + case FR30_OPERAND_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8); + break; + case FR30_OPERAND_UDISP6 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); + value = ((value) << (2)); + fields->f_udisp6 = value; + } + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const fr30_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const fr30_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int fr30_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma fr30_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +fr30_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FR30_OPERAND_R13 : + value = 0; + break; + case FR30_OPERAND_R14 : + value = 0; + break; + case FR30_OPERAND_R15 : + value = 0; + break; + case FR30_OPERAND_RI : + value = fields->f_Ri; + break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJ : + value = fields->f_Rj; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_RS1 : + value = fields->f_Rs1; + break; + case FR30_OPERAND_RS2 : + value = fields->f_Rs2; + break; + case FR30_OPERAND_CC : + value = fields->f_cc; + break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; + case FR30_OPERAND_DIR10 : + value = fields->f_dir10; + break; + case FR30_OPERAND_DIR8 : + value = fields->f_dir8; + break; + case FR30_OPERAND_DIR9 : + value = fields->f_dir9; + break; + case FR30_OPERAND_DISP10 : + value = fields->f_disp10; + break; + case FR30_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case FR30_OPERAND_DISP9 : + value = fields->f_disp9; + break; + case FR30_OPERAND_I20 : + value = fields->f_i20; + break; + case FR30_OPERAND_I32 : + value = fields->f_i32; + break; + case FR30_OPERAND_I8 : + value = fields->f_i8; + break; + case FR30_OPERAND_LABEL12 : + value = fields->f_rel12; + break; + case FR30_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case FR30_OPERAND_M4 : + value = fields->f_m4; + break; + case FR30_OPERAND_PS : + value = 0; + break; + case FR30_OPERAND_REGLIST_HI_LD : + value = fields->f_reglist_hi_ld; + break; + case FR30_OPERAND_REGLIST_HI_ST : + value = fields->f_reglist_hi_st; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + value = fields->f_reglist_low_ld; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + value = fields->f_reglist_low_st; + break; + case FR30_OPERAND_S10 : + value = fields->f_s10; + break; + case FR30_OPERAND_U10 : + value = fields->f_u10; + break; + case FR30_OPERAND_U4 : + value = fields->f_u4; + break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; + case FR30_OPERAND_U8 : + value = fields->f_u8; + break; + case FR30_OPERAND_UDISP6 : + value = fields->f_udisp6; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +fr30_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FR30_OPERAND_R13 : + value = 0; + break; + case FR30_OPERAND_R14 : + value = 0; + break; + case FR30_OPERAND_R15 : + value = 0; + break; + case FR30_OPERAND_RI : + value = fields->f_Ri; + break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJ : + value = fields->f_Rj; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_RS1 : + value = fields->f_Rs1; + break; + case FR30_OPERAND_RS2 : + value = fields->f_Rs2; + break; + case FR30_OPERAND_CC : + value = fields->f_cc; + break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; + case FR30_OPERAND_DIR10 : + value = fields->f_dir10; + break; + case FR30_OPERAND_DIR8 : + value = fields->f_dir8; + break; + case FR30_OPERAND_DIR9 : + value = fields->f_dir9; + break; + case FR30_OPERAND_DISP10 : + value = fields->f_disp10; + break; + case FR30_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case FR30_OPERAND_DISP9 : + value = fields->f_disp9; + break; + case FR30_OPERAND_I20 : + value = fields->f_i20; + break; + case FR30_OPERAND_I32 : + value = fields->f_i32; + break; + case FR30_OPERAND_I8 : + value = fields->f_i8; + break; + case FR30_OPERAND_LABEL12 : + value = fields->f_rel12; + break; + case FR30_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case FR30_OPERAND_M4 : + value = fields->f_m4; + break; + case FR30_OPERAND_PS : + value = 0; + break; + case FR30_OPERAND_REGLIST_HI_LD : + value = fields->f_reglist_hi_ld; + break; + case FR30_OPERAND_REGLIST_HI_ST : + value = fields->f_reglist_hi_st; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + value = fields->f_reglist_low_ld; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + value = fields->f_reglist_low_st; + break; + case FR30_OPERAND_S10 : + value = fields->f_s10; + break; + case FR30_OPERAND_U10 : + value = fields->f_u10; + break; + case FR30_OPERAND_U4 : + value = fields->f_u4; + break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; + case FR30_OPERAND_U8 : + value = fields->f_u8; + break; + case FR30_OPERAND_UDISP6 : + value = fields->f_udisp6; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void fr30_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void fr30_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +fr30_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + fields->f_Ri = value; + break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJ : + fields->f_Rj = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_RS1 : + fields->f_Rs1 = value; + break; + case FR30_OPERAND_RS2 : + fields->f_Rs2 = value; + break; + case FR30_OPERAND_CC : + fields->f_cc = value; + break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; + case FR30_OPERAND_DIR10 : + fields->f_dir10 = value; + break; + case FR30_OPERAND_DIR8 : + fields->f_dir8 = value; + break; + case FR30_OPERAND_DIR9 : + fields->f_dir9 = value; + break; + case FR30_OPERAND_DISP10 : + fields->f_disp10 = value; + break; + case FR30_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case FR30_OPERAND_DISP9 : + fields->f_disp9 = value; + break; + case FR30_OPERAND_I20 : + fields->f_i20 = value; + break; + case FR30_OPERAND_I32 : + fields->f_i32 = value; + break; + case FR30_OPERAND_I8 : + fields->f_i8 = value; + break; + case FR30_OPERAND_LABEL12 : + fields->f_rel12 = value; + break; + case FR30_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case FR30_OPERAND_M4 : + fields->f_m4 = value; + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + fields->f_reglist_hi_ld = value; + break; + case FR30_OPERAND_REGLIST_HI_ST : + fields->f_reglist_hi_st = value; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + fields->f_reglist_low_ld = value; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + fields->f_reglist_low_st = value; + break; + case FR30_OPERAND_S10 : + fields->f_s10 = value; + break; + case FR30_OPERAND_U10 : + fields->f_u10 = value; + break; + case FR30_OPERAND_U4 : + fields->f_u4 = value; + break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; + case FR30_OPERAND_U8 : + fields->f_u8 = value; + break; + case FR30_OPERAND_UDISP6 : + fields->f_udisp6 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +fr30_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FR30_OPERAND_R13 : + break; + case FR30_OPERAND_R14 : + break; + case FR30_OPERAND_R15 : + break; + case FR30_OPERAND_RI : + fields->f_Ri = value; + break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJ : + fields->f_Rj = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_RS1 : + fields->f_Rs1 = value; + break; + case FR30_OPERAND_RS2 : + fields->f_Rs2 = value; + break; + case FR30_OPERAND_CC : + fields->f_cc = value; + break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; + case FR30_OPERAND_DIR10 : + fields->f_dir10 = value; + break; + case FR30_OPERAND_DIR8 : + fields->f_dir8 = value; + break; + case FR30_OPERAND_DIR9 : + fields->f_dir9 = value; + break; + case FR30_OPERAND_DISP10 : + fields->f_disp10 = value; + break; + case FR30_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case FR30_OPERAND_DISP9 : + fields->f_disp9 = value; + break; + case FR30_OPERAND_I20 : + fields->f_i20 = value; + break; + case FR30_OPERAND_I32 : + fields->f_i32 = value; + break; + case FR30_OPERAND_I8 : + fields->f_i8 = value; + break; + case FR30_OPERAND_LABEL12 : + fields->f_rel12 = value; + break; + case FR30_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case FR30_OPERAND_M4 : + fields->f_m4 = value; + break; + case FR30_OPERAND_PS : + break; + case FR30_OPERAND_REGLIST_HI_LD : + fields->f_reglist_hi_ld = value; + break; + case FR30_OPERAND_REGLIST_HI_ST : + fields->f_reglist_hi_st = value; + break; + case FR30_OPERAND_REGLIST_LOW_LD : + fields->f_reglist_low_ld = value; + break; + case FR30_OPERAND_REGLIST_LOW_ST : + fields->f_reglist_low_st = value; + break; + case FR30_OPERAND_S10 : + fields->f_s10 = value; + break; + case FR30_OPERAND_U10 : + fields->f_u10 = value; + break; + case FR30_OPERAND_U4 : + fields->f_u4 = value; + break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; + case FR30_OPERAND_U8 : + fields->f_u8 = value; + break; + case FR30_OPERAND_UDISP6 : + fields->f_udisp6 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +fr30_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & fr30_cgen_insert_handlers[0]; + cd->extract_handlers = & fr30_cgen_extract_handlers[0]; + + cd->insert_operand = fr30_cgen_insert_operand; + cd->extract_operand = fr30_cgen_extract_operand; + + cd->get_int_operand = fr30_cgen_get_int_operand; + cd->set_int_operand = fr30_cgen_set_int_operand; + cd->get_vma_operand = fr30_cgen_get_vma_operand; + cd->set_vma_operand = fr30_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/fr30-opc.c b/external/gpl3/gdb/dist/opcodes/fr30-opc.c new file mode 100644 index 000000000000..9ff93edc2f59 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-opc.c @@ -0,0 +1,1372 @@ +/* Instruction opcode table for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "fr30-desc.h" +#include "fr30-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & fr30_cgen_ifld_table[FR30_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RJ) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U4) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_M4) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div0s ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div3 ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_OP4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi8 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi20 ATTRIBUTE_UNUSED = { + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_I20) }, { F (F_OP2) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi32 ATTRIBUTE_UNUSED = { + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_I32) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP10) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14uh ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP9) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr14ub ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr15 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_UDISP6) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldr15dr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RS2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movdr ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS1) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = { + 16, 16, 0xf800, { { F (F_OP1) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brad ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_CC) }, { F (F_REL9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13h ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dmovr13b ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copop ATTRIBUTE_UNUSED = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copld ATTRIBUTE_UNUSED = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RJC) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_copst ATTRIBUTE_UNUSED = { + 16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_RIC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addsp ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldm0 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_LD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldm1 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_LD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stm0 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_ST) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stm1 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_ST) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U10) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) FR30_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa600 } + }, +/* add $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa400 } + }, +/* add2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa500 } + }, +/* addc $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa700 } + }, +/* addn $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xa200 } + }, +/* addn $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa000 } + }, +/* addn2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa100 } + }, +/* sub $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xac00 } + }, +/* subc $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xad00 } + }, +/* subn $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xae00 } + }, +/* cmp $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xaa00 } + }, +/* cmp $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xa800 } + }, +/* cmp2 $m4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } }, + & ifmt_add2, { 0xa900 } + }, +/* and $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8200 } + }, +/* or $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x9200 } + }, +/* eor $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x9a00 } + }, +/* and $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8400 } + }, +/* andh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8500 } + }, +/* andb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x8600 } + }, +/* or $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9400 } + }, +/* orh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9500 } + }, +/* orb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9600 } + }, +/* eor $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9c00 } + }, +/* eorh $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9d00 } + }, +/* eorb $Rj,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } }, + & ifmt_add, { 0x9e00 } + }, +/* bandl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8000 } + }, +/* borl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9000 } + }, +/* beorl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9800 } + }, +/* bandh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8100 } + }, +/* borh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9100 } + }, +/* beorh $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x9900 } + }, +/* btstl $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8800 } + }, +/* btsth $u4,@$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } }, + & ifmt_addi, { 0x8900 } + }, +/* mul $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xaf00 } + }, +/* mulu $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xab00 } + }, +/* mulh $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xbf00 } + }, +/* muluh $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xbb00 } + }, +/* div0s $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9740 } + }, +/* div0u $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9750 } + }, +/* div1 $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9760 } + }, +/* div2 $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9770 } + }, +/* div3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f60 } + }, +/* div4s */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f70 } + }, +/* lsl $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xb600 } + }, +/* lsl $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb400 } + }, +/* lsl2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb500 } + }, +/* lsr $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xb200 } + }, +/* lsr $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb000 } + }, +/* lsr2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb100 } + }, +/* asr $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0xba00 } + }, +/* asr $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb800 } + }, +/* asr2 $u4,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } }, + & ifmt_addi, { 0xb900 } + }, +/* ldi:8 $i8,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } }, + & ifmt_ldi8, { 0xc000 } + }, +/* ldi:20 $i20,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } }, + & ifmt_ldi20, { 0x9b00 } + }, +/* ldi:32 $i32,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } }, + & ifmt_ldi32, { 0x9f80 } + }, +/* ld @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x400 } + }, +/* lduh @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x500 } + }, +/* ldub @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x600 } + }, +/* ld @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x0 } + }, +/* lduh @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x100 } + }, +/* ldub @($R13,$Rj),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } }, + & ifmt_add, { 0x200 } + }, +/* ld @($R14,$disp10),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14, { 0x2000 } + }, +/* lduh @($R14,$disp9),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14uh, { 0x4000 } + }, +/* ldub @($R14,$disp8),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } }, + & ifmt_ldr14ub, { 0x6000 } + }, +/* ld @($R15,$udisp6),$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } }, + & ifmt_ldr15, { 0x300 } + }, +/* ld @$R15+,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } }, + & ifmt_div0s, { 0x700 } + }, +/* ld @$R15+,$Rs2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } }, + & ifmt_ldr15dr, { 0x780 } + }, +/* ld @$R15+,$ps */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } }, + & ifmt_div3, { 0x790 } + }, +/* st $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1400 } + }, +/* sth $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1500 } + }, +/* stb $Ri,@$Rj */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } }, + & ifmt_add, { 0x1600 } + }, +/* st $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1000 } + }, +/* sth $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1100 } + }, +/* stb $Ri,@($R13,$Rj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } }, + & ifmt_add, { 0x1200 } + }, +/* st $Ri,@($R14,$disp10) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } }, + & ifmt_ldr14, { 0x3000 } + }, +/* sth $Ri,@($R14,$disp9) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } }, + & ifmt_ldr14uh, { 0x5000 } + }, +/* stb $Ri,@($R14,$disp8) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } }, + & ifmt_ldr14ub, { 0x7000 } + }, +/* st $Ri,@($R15,$udisp6) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } }, + & ifmt_ldr15, { 0x1300 } + }, +/* st $Ri,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } }, + & ifmt_div0s, { 0x1700 } + }, +/* st $Rs2,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } }, + & ifmt_ldr15dr, { 0x1780 } + }, +/* st $ps,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } }, + & ifmt_div3, { 0x1790 } + }, +/* mov $Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8b00 } + }, +/* mov $Rs1,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } }, + & ifmt_movdr, { 0xb700 } + }, +/* mov $ps,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } }, + & ifmt_div0s, { 0x1710 } + }, +/* mov $Ri,$Rs1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } }, + & ifmt_movdr, { 0xb300 } + }, +/* mov $Ri,$ps */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } }, + & ifmt_div0s, { 0x710 } + }, +/* jmp @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9700 } + }, +/* jmp:d @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9f00 } + }, +/* call @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9710 } + }, +/* call:d @$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), 0 } }, + & ifmt_div0s, { 0x9f10 } + }, +/* call $label12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL12), 0 } }, + & ifmt_call, { 0xd000 } + }, +/* call:d $label12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL12), 0 } }, + & ifmt_call, { 0xd800 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9720 } + }, +/* ret:d */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f20 } + }, +/* int $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x1f00 } + }, +/* inte */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f30 } + }, +/* reti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9730 } + }, +/* bra:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf000 } + }, +/* bra $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe000 } + }, +/* bno:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf100 } + }, +/* bno $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe100 } + }, +/* beq:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf200 } + }, +/* beq $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe200 } + }, +/* bne:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf300 } + }, +/* bne $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe300 } + }, +/* bc:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf400 } + }, +/* bc $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe400 } + }, +/* bnc:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf500 } + }, +/* bnc $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe500 } + }, +/* bn:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf600 } + }, +/* bn $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe600 } + }, +/* bp:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf700 } + }, +/* bp $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe700 } + }, +/* bv:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf800 } + }, +/* bv $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe800 } + }, +/* bnv:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xf900 } + }, +/* bnv $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xe900 } + }, +/* blt:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfa00 } + }, +/* blt $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xea00 } + }, +/* bge:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfb00 } + }, +/* bge $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xeb00 } + }, +/* ble:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfc00 } + }, +/* ble $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xec00 } + }, +/* bgt:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfd00 } + }, +/* bgt $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xed00 } + }, +/* bls:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xfe00 } + }, +/* bls $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xee00 } + }, +/* bhi:d $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xff00 } + }, +/* bhi $label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LABEL9), 0 } }, + & ifmt_brad, { 0xef00 } + }, +/* dmov $R13,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1800 } + }, +/* dmovh $R13,@$dir9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } }, + & ifmt_dmovr13h, { 0x1900 } + }, +/* dmovb $R13,@$dir8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } }, + & ifmt_dmovr13b, { 0x1a00 } + }, +/* dmov @$R13+,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1c00 } + }, +/* dmovh @$R13+,@$dir9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } }, + & ifmt_dmovr13h, { 0x1d00 } + }, +/* dmovb @$R13+,@$dir8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } }, + & ifmt_dmovr13b, { 0x1e00 } + }, +/* dmov @$R15+,@$dir10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } }, + & ifmt_dmovr13, { 0x1b00 } + }, +/* dmov @$dir10,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } }, + & ifmt_dmovr13, { 0x800 } + }, +/* dmovh @$dir9,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } }, + & ifmt_dmovr13h, { 0x900 } + }, +/* dmovb @$dir8,$R13 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } }, + & ifmt_dmovr13b, { 0xa00 } + }, +/* dmov @$dir10,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13, { 0xc00 } + }, +/* dmovh @$dir9,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13h, { 0xd00 } + }, +/* dmovb @$dir8,@$R13+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } }, + & ifmt_dmovr13b, { 0xe00 } + }, +/* dmov @$dir10,@-$R15 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } }, + & ifmt_dmovr13, { 0xb00 } + }, +/* ldres @$Ri+,$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } }, + & ifmt_addi, { 0xbc00 } + }, +/* stres $u4,@$Ri+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } }, + & ifmt_addi, { 0xbd00 } + }, +/* copop $u4c,$ccc,$CRj,$CRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } }, + & ifmt_copop, { 0x9fc0 } + }, +/* copld $u4c,$ccc,$Rjc,$CRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } }, + & ifmt_copld, { 0x9fd0 } + }, +/* copst $u4c,$ccc,$CRj,$Ric */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, + & ifmt_copst, { 0x9fe0 } + }, +/* copsv $u4c,$ccc,$CRj,$Ric */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } }, + & ifmt_copst, { 0x9ff0 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9fa0 } + }, +/* andccr $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x8300 } + }, +/* orccr $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x9300 } + }, +/* stilm $u8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U8), 0 } }, + & ifmt_int, { 0x8700 } + }, +/* addsp $s10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (S10), 0 } }, + & ifmt_addsp, { 0xa300 } + }, +/* extsb $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9780 } + }, +/* extub $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x9790 } + }, +/* extsh $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x97a0 } + }, +/* extuh $Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RI), 0 } }, + & ifmt_div0s, { 0x97b0 } + }, +/* ldm0 ($reglist_low_ld) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } }, + & ifmt_ldm0, { 0x8c00 } + }, +/* ldm1 ($reglist_hi_ld) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } }, + & ifmt_ldm1, { 0x8d00 } + }, +/* stm0 ($reglist_low_st) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } }, + & ifmt_stm0, { 0x8e00 } + }, +/* stm1 ($reglist_hi_st) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } }, + & ifmt_stm1, { 0x8f00 } + }, +/* enter $u10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (U10), 0 } }, + & ifmt_enter, { 0xf00 } + }, +/* leave */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_div3, { 0x9f90 } + }, +/* xchb @$Rj,$Ri */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } }, + & ifmt_add, { 0x8a00 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & fr30_cgen_ifld_table[FR30_##f] +static const CGEN_IFMT ifmt_ldi8m ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi20m ATTRIBUTE_UNUSED = { + 16, 32, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RI) }, { F (F_I20) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi32m ATTRIBUTE_UNUSED = { + 16, 48, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { F (F_I32) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) FR30_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE fr30_cgen_macro_insn_table[] = +{ +/* ldi8 $i8,$Ri */ + { + -1, "ldi8m", "ldi8", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + fr30_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & fr30_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + fr30_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/fr30-opc.h b/external/gpl3/gdb/dist/opcodes/fr30-opc.h new file mode 100644 index 000000000000..8f3dfe1f091d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/fr30-opc.h @@ -0,0 +1,151 @@ +/* Instruction opcode header for fr30. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef FR30_OPC_H +#define FR30_OPC_H + +/* -- opc.h */ + +/* ??? This can be improved upon. */ +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 16 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) + +/* -- */ +/* Enum declaration for fr30 instruction types. */ +typedef enum cgen_insn_type { + FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2 + , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2 + , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP + , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR + , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB + , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM + , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL + , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH + , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU + , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U + , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S + , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR + , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI + , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32 + , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13 + , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH + , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR + , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB + , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14 + , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR + , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR + , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP + , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL + , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT + , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRAD, FR30_INSN_BRA + , FR30_INSN_BNOD, FR30_INSN_BNO, FR30_INSN_BEQD, FR30_INSN_BEQ + , FR30_INSN_BNED, FR30_INSN_BNE, FR30_INSN_BCD, FR30_INSN_BC + , FR30_INSN_BNCD, FR30_INSN_BNC, FR30_INSN_BND, FR30_INSN_BN + , FR30_INSN_BPD, FR30_INSN_BP, FR30_INSN_BVD, FR30_INSN_BV + , FR30_INSN_BNVD, FR30_INSN_BNV, FR30_INSN_BLTD, FR30_INSN_BLT + , FR30_INSN_BGED, FR30_INSN_BGE, FR30_INSN_BLED, FR30_INSN_BLE + , FR30_INSN_BGTD, FR30_INSN_BGT, FR30_INSN_BLSD, FR30_INSN_BLS + , FR30_INSN_BHID, FR30_INSN_BHI, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H + , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB + , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B + , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD + , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD + , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR + , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB + , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0 + , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER + , FR30_INSN_LEAVE, FR30_INSN_XCHB +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID FR30_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) FR30_INSN_XCHB + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_op1; + long f_op2; + long f_op3; + long f_op4; + long f_op5; + long f_cc; + long f_ccc; + long f_Rj; + long f_Ri; + long f_Rs1; + long f_Rs2; + long f_Rjc; + long f_Ric; + long f_CRj; + long f_CRi; + long f_u4; + long f_u4c; + long f_i4; + long f_m4; + long f_u8; + long f_i8; + long f_i20_4; + long f_i20_16; + long f_i20; + long f_i32; + long f_udisp6; + long f_disp8; + long f_disp9; + long f_disp10; + long f_s10; + long f_u10; + long f_rel9; + long f_dir8; + long f_dir9; + long f_dir10; + long f_rel12; + long f_reglist_hi_st; + long f_reglist_low_st; + long f_reglist_hi_ld; + long f_reglist_low_ld; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* FR30_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/frv-asm.c b/external/gpl3/gdb/dist/opcodes/frv-asm.c new file mode 100644 index 000000000000..dffa059ec294 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-asm.c @@ -0,0 +1,1671 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +inline static const char * +parse_symbolic_address (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result *resultp, + bfd_vma *valuep) +{ + enum cgen_parse_operand_result result_type; + const char *errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_SYMBOLIC, strp, opindex, opinfo, + &result_type, valuep); + + if (errmsg == NULL + && result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED) + return "symbolic expression required"; + + if (resultp) + *resultp = result_type; + + return errmsg; +} + +static const char * +parse_ldd_annotation (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "tlsdesc(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSDESC_RELAX, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + if (valuep) + *valuep = value; + ++*strp; + if (errmsg) + return errmsg; + } + } + + while (**strp == ' ' || **strp == '\t') + ++*strp; + + if (**strp != '@') + return "missing `@'"; + + ++*strp; + + return NULL; +} + +static const char * +parse_call_annotation (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GETTLSOFF_RELAX, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + if (valuep) + *valuep = value; + ++*strp; + if (errmsg) + return errmsg; + } + } + + while (**strp == ' ' || **strp == '\t') + ++*strp; + + if (**strp != '@') + return "missing `@'"; + + ++*strp; + + return NULL; +} + +static const char * +parse_ld_annotation (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "tlsoff(", 7) == 0) + { + *strp += 8; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSOFF_RELAX, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + if (valuep) + *valuep = value; + ++*strp; + if (errmsg) + return errmsg; + } + } + + while (**strp == ' ' || **strp == '\t') + ++*strp; + + if (**strp != '@') + return "missing `@'"; + + ++*strp; + + return NULL; +} + +static const char * +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPRELLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0) + { + *strp += 7; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0) + { + *strp += 15; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0) + { + *strp += 10; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0) + { + *strp += 18; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0) + { + *strp += 14; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSDESCLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSMOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0) + { + *strp += 13; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uslo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + signed long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPRELLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0) + { + *strp += 7; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0) + { + *strp += 15; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0) + { + *strp += 10; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0) + { + *strp += 18; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0) + { + *strp += 14; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSDESCLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSMOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0) + { + *strp += 13; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSOFFLO, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uhi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "hi(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* If bfd_vma is wider than 32 bits, but we have a sign- + or zero-extension, truncate it. */ + if (value >= - ((bfd_vma)1 << 31) + || value <= ((bfd_vma)1 << 31) - (bfd_vma)1) + value &= (((bfd_vma)1 << 16) << 16) - 1; + value >>= 16; + } + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPRELHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gothi(", 6) == 0) + { + *strp += 7; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotfuncdeschi(", 14) == 0) + { + *strp += 15; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotoffhi(", 9) == 0) + { + *strp += 10; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTOFFHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofffuncdeschi(", 17) == 0) + { + *strp += 18; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTOFFHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsdeschi(", 13) == 0) + { + *strp += 14; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSDESCHI, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "tlsmoffhi(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSMOFFHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsoffhi(", 12) == 0) + { + *strp += 13; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSOFFHI, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static long +parse_register_number (const char **strp) +{ + int regno; + + if (**strp < '0' || **strp > '9') + return -1; /* error */ + + regno = **strp - '0'; + for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp) + regno = regno * 10 + (**strp - '0'); + + return regno; +} + +static const char * +parse_spr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD * table, + long *valuep) +{ + const char *save_strp; + long regno; + + /* Check for spr index notation. */ + if (strncasecmp (*strp, "spr[", 4) == 0) + { + *strp += 4; + regno = parse_register_number (strp); + if (**strp != ']') + return _("missing `]'"); + ++*strp; + if (! spr_valid (regno)) + return _("Special purpose register number is out of range"); + *valuep = regno; + return NULL; + } + + save_strp = *strp; + regno = parse_register_number (strp); + if (regno != -1) + { + if (! spr_valid (regno)) + return _("Special purpose register number is out of range"); + *valuep = regno; + return NULL; + } + + *strp = save_strp; + return cgen_parse_keyword (cd, strp, table, valuep); +} + +static const char * +parse_d12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPREL12, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "got12(", 6) == 0) + { + *strp += 7; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOT12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0) + { + *strp += 15; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOT12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0) + { + *strp += 10; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0) + { + *strp += 18; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0) + { + *strp += 14; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSDESC12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSMOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0) + { + *strp += 13; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_s12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPREL12, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "got12(", 6) == 0) + { + *strp += 7; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOT12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0) + { + *strp += 15; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOT12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0) + { + *strp += 10; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0) + { + *strp += 18; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_FUNCDESC_GOTOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0) + { + *strp += 14; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSDESC12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_TLSMOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0) + { + *strp += 13; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GOTTLSOFF12, + & result_type, & value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_u12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GPRELU12, + & result_type, & value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +static const char * +parse_A (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep, + unsigned long A) +{ + const char *errmsg; + + if (**strp == '#') + ++*strp; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + if (errmsg) + return errmsg; + + if (*valuep != A) + return _("Value of A operand must be 0 or 1"); + + return NULL; +} + +static const char * +parse_A0 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_A (cd, strp, opindex, valuep, 0); +} + +static const char * +parse_A1 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_A (cd, strp, opindex, valuep, 1); +} + +static const char * +parse_even_register (CGEN_CPU_DESC cd, + const char ** strP, + CGEN_KEYWORD * tableP, + long * valueP) +{ + const char * errmsg; + const char * saved_star_strP = * strP; + + errmsg = cgen_parse_keyword (cd, strP, tableP, valueP); + + if (errmsg == NULL && ((* valueP) & 1)) + { + errmsg = _("register number must be even"); + * strP = saved_star_strP; + } + + return errmsg; +} + +static const char * +parse_call_label (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result *resultp, + bfd_vma *valuep) +{ + const char *errmsg; + bfd_vma value; + + /* Check for small data reference. */ + if (opinfo == 0 && (**strp == '#' || **strp == '%')) + { + if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0) + { + *strp += 11; + errmsg = parse_symbolic_address (cd, strp, opindex, + BFD_RELOC_FRV_GETTLSOFF, + resultp, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + *valuep = value; + return errmsg; + } + } + + return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep); +} + +/* -- */ + +const char * frv_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +frv_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case FRV_OPERAND_A0 : + errmsg = parse_A0 (cd, strp, FRV_OPERAND_A0, (unsigned long *) (& fields->f_A)); + break; + case FRV_OPERAND_A1 : + errmsg = parse_A1 (cd, strp, FRV_OPERAND_A1, (unsigned long *) (& fields->f_A)); + break; + case FRV_OPERAND_ACC40SI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_int); + break; + case FRV_OPERAND_CRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, (unsigned long *) (& fields->f_LI)); + break; + case FRV_OPERAND_LRAD : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAD, (unsigned long *) (& fields->f_LRAD)); + break; + case FRV_OPERAND_LRAE : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAE, (unsigned long *) (& fields->f_LRAE)); + break; + case FRV_OPERAND_LRAS : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAS, (unsigned long *) (& fields->f_LRAS)); + break; + case FRV_OPERAND_TLBPRL : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPRL, (unsigned long *) (& fields->f_TLBPRL)); + break; + case FRV_OPERAND_TLBPROPX : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPROPX, (unsigned long *) (& fields->f_TLBPRopx)); + break; + case FRV_OPERAND_AE : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, (unsigned long *) (& fields->f_ae)); + break; + case FRV_OPERAND_CALLANN : + errmsg = parse_call_annotation (cd, strp, FRV_OPERAND_CALLANN, (unsigned long *) (& fields->f_reloc_ann)); + break; + case FRV_OPERAND_CCOND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_CCOND, (unsigned long *) (& fields->f_ccond)); + break; + case FRV_OPERAND_COND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_COND, (unsigned long *) (& fields->f_cond)); + break; + case FRV_OPERAND_D12 : + errmsg = parse_d12 (cd, strp, FRV_OPERAND_D12, (long *) (& fields->f_d12)); + break; + case FRV_OPERAND_DEBUG : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_DEBUG, (unsigned long *) (& fields->f_debug)); + break; + case FRV_OPERAND_EIR : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_EIR, (unsigned long *) (& fields->f_eir)); + break; + case FRV_OPERAND_HINT : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_HINT, (unsigned long *) (& fields->f_hint)); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_not_taken, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_taken, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL, & value); + fields->f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + bfd_vma value = 0; + errmsg = parse_call_label (cd, strp, FRV_OPERAND_LABEL24, 0, NULL, & value); + fields->f_label24 = value; + } + break; + case FRV_OPERAND_LDANN : + errmsg = parse_ld_annotation (cd, strp, FRV_OPERAND_LDANN, (unsigned long *) (& fields->f_reloc_ann)); + break; + case FRV_OPERAND_LDDANN : + errmsg = parse_ldd_annotation (cd, strp, FRV_OPERAND_LDDANN, (unsigned long *) (& fields->f_reloc_ann)); + break; + case FRV_OPERAND_LOCK : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LOCK, (unsigned long *) (& fields->f_lock)); + break; + case FRV_OPERAND_PACK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_pack, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S10, (long *) (& fields->f_s10)); + break; + case FRV_OPERAND_S12 : + errmsg = parse_s12 (cd, strp, FRV_OPERAND_S12, (long *) (& fields->f_d12)); + break; + case FRV_OPERAND_S16 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S16, (long *) (& fields->f_s16)); + break; + case FRV_OPERAND_S5 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S5, (long *) (& fields->f_s5)); + break; + case FRV_OPERAND_S6 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6, (long *) (& fields->f_s6)); + break; + case FRV_OPERAND_S6_1 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6_1, (long *) (& fields->f_s6_1)); + break; + case FRV_OPERAND_SLO16 : + errmsg = parse_uslo16 (cd, strp, FRV_OPERAND_SLO16, (long *) (& fields->f_s16)); + break; + case FRV_OPERAND_SPR : + errmsg = parse_spr (cd, strp, & frv_cgen_opval_spr_names, & fields->f_spr); + break; + case FRV_OPERAND_U12 : + errmsg = parse_u12 (cd, strp, FRV_OPERAND_U12, (long *) (& fields->f_u12)); + break; + case FRV_OPERAND_U16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U16, (unsigned long *) (& fields->f_u16)); + break; + case FRV_OPERAND_U6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U6, (unsigned long *) (& fields->f_u6)); + break; + case FRV_OPERAND_UHI16 : + errmsg = parse_uhi16 (cd, strp, FRV_OPERAND_UHI16, (unsigned long *) (& fields->f_u16)); + break; + case FRV_OPERAND_ULO16 : + errmsg = parse_ulo16 (cd, strp, FRV_OPERAND_ULO16, (unsigned long *) (& fields->f_u16)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const frv_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +frv_cgen_init_asm (CGEN_CPU_DESC cd) +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->parse_handlers = & frv_cgen_parse_handlers[0]; + cd->parse_operand = frv_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by frv_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +frv_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +frv_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/frv-desc.c b/external/gpl3/gdb/dist/opcodes/frv-desc.c new file mode 100644 index 000000000000..df82930e70aa --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-desc.c @@ -0,0 +1,6488 @@ +/* CPU data for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "frv", MACH_FRV }, + { "fr550", MACH_FR550 }, + { "fr500", MACH_FR500 }, + { "fr450", MACH_FR450 }, + { "fr400", MACH_FR400 }, + { "tomcat", MACH_TOMCAT }, + { "simple", MACH_SIMPLE }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "frv", ISA_FRV }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY UNIT_attr[] ATTRIBUTE_UNUSED = +{ + { "NIL", UNIT_NIL }, + { "I0", UNIT_I0 }, + { "I1", UNIT_I1 }, + { "I01", UNIT_I01 }, + { "I2", UNIT_I2 }, + { "I3", UNIT_I3 }, + { "IALL", UNIT_IALL }, + { "FM0", UNIT_FM0 }, + { "FM1", UNIT_FM1 }, + { "FM01", UNIT_FM01 }, + { "FM2", UNIT_FM2 }, + { "FM3", UNIT_FM3 }, + { "FMALL", UNIT_FMALL }, + { "FMLOW", UNIT_FMLOW }, + { "B0", UNIT_B0 }, + { "B1", UNIT_B1 }, + { "B01", UNIT_B01 }, + { "C", UNIT_C }, + { "MULT_DIV", UNIT_MULT_DIV }, + { "IACC", UNIT_IACC }, + { "LOAD", UNIT_LOAD }, + { "STORE", UNIT_STORE }, + { "SCAN", UNIT_SCAN }, + { "DCPL", UNIT_DCPL }, + { "MDUALACC", UNIT_MDUALACC }, + { "MDCUTSSI", UNIT_MDCUTSSI }, + { "MCLRACC_1", UNIT_MCLRACC_1 }, + { "NUM_UNITS", UNIT_NUM_UNITS }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", FR400_MAJOR_NONE }, + { "I_1", FR400_MAJOR_I_1 }, + { "I_2", FR400_MAJOR_I_2 }, + { "I_3", FR400_MAJOR_I_3 }, + { "I_4", FR400_MAJOR_I_4 }, + { "I_5", FR400_MAJOR_I_5 }, + { "B_1", FR400_MAJOR_B_1 }, + { "B_2", FR400_MAJOR_B_2 }, + { "B_3", FR400_MAJOR_B_3 }, + { "B_4", FR400_MAJOR_B_4 }, + { "B_5", FR400_MAJOR_B_5 }, + { "B_6", FR400_MAJOR_B_6 }, + { "C_1", FR400_MAJOR_C_1 }, + { "C_2", FR400_MAJOR_C_2 }, + { "M_1", FR400_MAJOR_M_1 }, + { "M_2", FR400_MAJOR_M_2 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR450_MAJOR_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", FR450_MAJOR_NONE }, + { "I_1", FR450_MAJOR_I_1 }, + { "I_2", FR450_MAJOR_I_2 }, + { "I_3", FR450_MAJOR_I_3 }, + { "I_4", FR450_MAJOR_I_4 }, + { "I_5", FR450_MAJOR_I_5 }, + { "B_1", FR450_MAJOR_B_1 }, + { "B_2", FR450_MAJOR_B_2 }, + { "B_3", FR450_MAJOR_B_3 }, + { "B_4", FR450_MAJOR_B_4 }, + { "B_5", FR450_MAJOR_B_5 }, + { "B_6", FR450_MAJOR_B_6 }, + { "C_1", FR450_MAJOR_C_1 }, + { "C_2", FR450_MAJOR_C_2 }, + { "M_1", FR450_MAJOR_M_1 }, + { "M_2", FR450_MAJOR_M_2 }, + { "M_3", FR450_MAJOR_M_3 }, + { "M_4", FR450_MAJOR_M_4 }, + { "M_5", FR450_MAJOR_M_5 }, + { "M_6", FR450_MAJOR_M_6 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", FR500_MAJOR_NONE }, + { "I_1", FR500_MAJOR_I_1 }, + { "I_2", FR500_MAJOR_I_2 }, + { "I_3", FR500_MAJOR_I_3 }, + { "I_4", FR500_MAJOR_I_4 }, + { "I_5", FR500_MAJOR_I_5 }, + { "I_6", FR500_MAJOR_I_6 }, + { "B_1", FR500_MAJOR_B_1 }, + { "B_2", FR500_MAJOR_B_2 }, + { "B_3", FR500_MAJOR_B_3 }, + { "B_4", FR500_MAJOR_B_4 }, + { "B_5", FR500_MAJOR_B_5 }, + { "B_6", FR500_MAJOR_B_6 }, + { "C_1", FR500_MAJOR_C_1 }, + { "C_2", FR500_MAJOR_C_2 }, + { "F_1", FR500_MAJOR_F_1 }, + { "F_2", FR500_MAJOR_F_2 }, + { "F_3", FR500_MAJOR_F_3 }, + { "F_4", FR500_MAJOR_F_4 }, + { "F_5", FR500_MAJOR_F_5 }, + { "F_6", FR500_MAJOR_F_6 }, + { "F_7", FR500_MAJOR_F_7 }, + { "F_8", FR500_MAJOR_F_8 }, + { "M_1", FR500_MAJOR_M_1 }, + { "M_2", FR500_MAJOR_M_2 }, + { "M_3", FR500_MAJOR_M_3 }, + { "M_4", FR500_MAJOR_M_4 }, + { "M_5", FR500_MAJOR_M_5 }, + { "M_6", FR500_MAJOR_M_6 }, + { "M_7", FR500_MAJOR_M_7 }, + { "M_8", FR500_MAJOR_M_8 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR550_MAJOR_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", FR550_MAJOR_NONE }, + { "I_1", FR550_MAJOR_I_1 }, + { "I_2", FR550_MAJOR_I_2 }, + { "I_3", FR550_MAJOR_I_3 }, + { "I_4", FR550_MAJOR_I_4 }, + { "I_5", FR550_MAJOR_I_5 }, + { "I_6", FR550_MAJOR_I_6 }, + { "I_7", FR550_MAJOR_I_7 }, + { "I_8", FR550_MAJOR_I_8 }, + { "B_1", FR550_MAJOR_B_1 }, + { "B_2", FR550_MAJOR_B_2 }, + { "B_3", FR550_MAJOR_B_3 }, + { "B_4", FR550_MAJOR_B_4 }, + { "B_5", FR550_MAJOR_B_5 }, + { "B_6", FR550_MAJOR_B_6 }, + { "C_1", FR550_MAJOR_C_1 }, + { "C_2", FR550_MAJOR_C_2 }, + { "F_1", FR550_MAJOR_F_1 }, + { "F_2", FR550_MAJOR_F_2 }, + { "F_3", FR550_MAJOR_F_3 }, + { "F_4", FR550_MAJOR_F_4 }, + { "M_1", FR550_MAJOR_M_1 }, + { "M_2", FR550_MAJOR_M_2 }, + { "M_3", FR550_MAJOR_M_3 }, + { "M_4", FR550_MAJOR_M_4 }, + { "M_5", FR550_MAJOR_M_5 }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "UNIT", & UNIT_attr[0], & UNIT_attr[0] }, + { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] }, + { "FR450-MAJOR", & FR450_MAJOR_attr[0], & FR450_MAJOR_attr[0] }, + { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] }, + { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "PRIVILEGED", &bool_attr[0], &bool_attr[0] }, + { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] }, + { "CONDITIONAL", &bool_attr[0], &bool_attr[0] }, + { "FR-ACCESS", &bool_attr[0], &bool_attr[0] }, + { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] }, + { "AUDIO", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA frv_cgen_isa_table[] = { + { "frv", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH frv_cgen_mach_table[] = { + { "frv", "frv", MACH_FRV, 0 }, + { "fr550", "fr550", MACH_FR550, 0 }, + { "fr500", "fr500", MACH_FR500, 0 }, + { "tomcat", "tomcat", MACH_TOMCAT, 0 }, + { "fr400", "fr400", MACH_FR400, 0 }, + { "fr450", "fr450", MACH_FR450, 0 }, + { "simple", "simple", MACH_SIMPLE, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] = +{ + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "gr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "gr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "gr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "gr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "gr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "gr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "gr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "gr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "gr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "gr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "gr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "gr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "gr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "gr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "gr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "gr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "gr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "gr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "gr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "gr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "gr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "gr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "gr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "gr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "gr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "gr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "gr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "gr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "gr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "gr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "gr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "gr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "gr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "gr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "gr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "gr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "gr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "gr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "gr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "gr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "gr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "gr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "gr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "gr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "gr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "gr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "gr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "gr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "gr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "gr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "gr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "gr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "gr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "gr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "gr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "gr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "gr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "gr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "gr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "gr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "gr63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_gr_names = +{ + & frv_cgen_opval_gr_names_entries[0], + 66, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] = +{ + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "fr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "fr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "fr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "fr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "fr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "fr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "fr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "fr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "fr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "fr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "fr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "fr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "fr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "fr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "fr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "fr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "fr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "fr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "fr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "fr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "fr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "fr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "fr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "fr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "fr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "fr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "fr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "fr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "fr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "fr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "fr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "fr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "fr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "fr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "fr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "fr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "fr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "fr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "fr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "fr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "fr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "fr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "fr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "fr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "fr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "fr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "fr63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fr_names = +{ + & frv_cgen_opval_fr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] = +{ + { "cpr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "cpr63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cpr_names = +{ + & frv_cgen_opval_cpr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = +{ + { "psr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "pcsr", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "bpcsr", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "tbr", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "bpsr", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr0", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr1", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr2", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr3", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr4", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr5", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr6", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr7", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr8", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr9", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr10", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr11", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr12", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr13", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr14", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr15", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr16", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr17", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr18", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr19", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr20", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr21", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr22", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr23", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr24", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr25", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr26", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr27", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr28", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr29", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr30", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr31", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr32", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr33", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr34", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr35", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr36", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr37", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr38", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr39", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr40", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr41", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr42", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr43", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr44", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr45", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr46", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr47", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr48", 64, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr49", 65, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr50", 66, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr51", 67, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr52", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr53", 69, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr54", 70, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr55", 71, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr56", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr57", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr58", 74, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr59", 75, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr60", 76, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr61", 77, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr62", 78, {0, {{{0, 0}}}}, 0, 0 }, + { "hsr63", 79, {0, {{{0, 0}}}}, 0, 0 }, + { "ccr", 256, {0, {{{0, 0}}}}, 0, 0 }, + { "cccr", 263, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 272, {0, {{{0, 0}}}}, 0, 0 }, + { "lcr", 273, {0, {{{0, 0}}}}, 0, 0 }, + { "iacc0h", 280, {0, {{{0, 0}}}}, 0, 0 }, + { "iacc0l", 281, {0, {{{0, 0}}}}, 0, 0 }, + { "isr", 288, {0, {{{0, 0}}}}, 0, 0 }, + { "neear0", 352, {0, {{{0, 0}}}}, 0, 0 }, + { "neear1", 353, {0, {{{0, 0}}}}, 0, 0 }, + { "neear2", 354, {0, {{{0, 0}}}}, 0, 0 }, + { "neear3", 355, {0, {{{0, 0}}}}, 0, 0 }, + { "neear4", 356, {0, {{{0, 0}}}}, 0, 0 }, + { "neear5", 357, {0, {{{0, 0}}}}, 0, 0 }, + { "neear6", 358, {0, {{{0, 0}}}}, 0, 0 }, + { "neear7", 359, {0, {{{0, 0}}}}, 0, 0 }, + { "neear8", 360, {0, {{{0, 0}}}}, 0, 0 }, + { "neear9", 361, {0, {{{0, 0}}}}, 0, 0 }, + { "neear10", 362, {0, {{{0, 0}}}}, 0, 0 }, + { "neear11", 363, {0, {{{0, 0}}}}, 0, 0 }, + { "neear12", 364, {0, {{{0, 0}}}}, 0, 0 }, + { "neear13", 365, {0, {{{0, 0}}}}, 0, 0 }, + { "neear14", 366, {0, {{{0, 0}}}}, 0, 0 }, + { "neear15", 367, {0, {{{0, 0}}}}, 0, 0 }, + { "neear16", 368, {0, {{{0, 0}}}}, 0, 0 }, + { "neear17", 369, {0, {{{0, 0}}}}, 0, 0 }, + { "neear18", 370, {0, {{{0, 0}}}}, 0, 0 }, + { "neear19", 371, {0, {{{0, 0}}}}, 0, 0 }, + { "neear20", 372, {0, {{{0, 0}}}}, 0, 0 }, + { "neear21", 373, {0, {{{0, 0}}}}, 0, 0 }, + { "neear22", 374, {0, {{{0, 0}}}}, 0, 0 }, + { "neear23", 375, {0, {{{0, 0}}}}, 0, 0 }, + { "neear24", 376, {0, {{{0, 0}}}}, 0, 0 }, + { "neear25", 377, {0, {{{0, 0}}}}, 0, 0 }, + { "neear26", 378, {0, {{{0, 0}}}}, 0, 0 }, + { "neear27", 379, {0, {{{0, 0}}}}, 0, 0 }, + { "neear28", 380, {0, {{{0, 0}}}}, 0, 0 }, + { "neear29", 381, {0, {{{0, 0}}}}, 0, 0 }, + { "neear30", 382, {0, {{{0, 0}}}}, 0, 0 }, + { "neear31", 383, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr0", 384, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr1", 385, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr2", 386, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr3", 387, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr4", 388, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr5", 389, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr6", 390, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr7", 391, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr8", 392, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr9", 393, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr10", 394, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr11", 395, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr12", 396, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr13", 397, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr14", 398, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr15", 399, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr16", 400, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr17", 401, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr18", 402, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr19", 403, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr20", 404, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr21", 405, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr22", 406, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr23", 407, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr24", 408, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr25", 409, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr26", 410, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr27", 411, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr28", 412, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr29", 413, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr30", 414, {0, {{{0, 0}}}}, 0, 0 }, + { "nesr31", 415, {0, {{{0, 0}}}}, 0, 0 }, + { "necr", 416, {0, {{{0, 0}}}}, 0, 0 }, + { "gner0", 432, {0, {{{0, 0}}}}, 0, 0 }, + { "gner1", 433, {0, {{{0, 0}}}}, 0, 0 }, + { "fner0", 434, {0, {{{0, 0}}}}, 0, 0 }, + { "fner1", 435, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr0", 512, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr1", 513, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr2", 514, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr3", 515, {0, {{{0, 0}}}}, 0, 0 }, + { "epcr4", 516, {0, {{{0, 0}}}}, 0, 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}, + { "dbmr11", 2081, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr12", 2082, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr13", 2083, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr20", 2084, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr21", 2085, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr22", 2086, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr23", 2087, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr30", 2088, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 }, + { "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcfr", 2304, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcr", 2305, {0, {{{0, 0}}}}, 0, 0 }, + { "cpsr", 2306, {0, {{{0, 0}}}}, 0, 0 }, + { "cptr", 2307, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr0", 2308, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr1", 2309, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr0", 2320, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr1", 2321, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr0", 2322, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr1", 2323, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr0", 2324, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr1", 2325, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjsr", 2326, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjrr", 2327, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr0", 2336, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr1", 2337, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer0", 2338, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer1", 2339, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwr", 2340, {0, {{{0, 0}}}}, 0, 0 }, + { "mbhsr", 2352, {0, {{{0, 0}}}}, 0, 0 }, + { "mbssr", 2353, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrsr", 2354, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsdr", 2355, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrdr", 2356, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsmr", 2357, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr0", 2359, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr1", 2360, {0, {{{0, 0}}}}, 0, 0 }, + { "slpr", 2368, {0, {{{0, 0}}}}, 0, 0 }, + { "sldr", 2369, {0, {{{0, 0}}}}, 0, 0 }, + { "slhsr", 2370, {0, {{{0, 0}}}}, 0, 0 }, + { "sltr", 2371, {0, {{{0, 0}}}}, 0, 0 }, + { "slwr", 2372, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr9", 3849, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr10", 3850, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_spr_names = +{ + & frv_cgen_opval_spr_names_entries[0], + 1049, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] = +{ + { "accg0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "accg1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "accg2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "accg3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "accg4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "accg5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "accg6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "accg7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "accg8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "accg9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "accg10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "accg11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "accg12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "accg13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "accg14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "accg15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "accg16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "accg17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "accg18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "accg19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "accg20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "accg21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "accg22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "accg23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "accg24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "accg25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "accg26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "accg27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "accg28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "accg29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "accg30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "accg31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "accg32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "accg33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "accg34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "accg35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "accg36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "accg37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "accg38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "accg39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "accg40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "accg41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "accg42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "accg43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "accg44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "accg45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "accg46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "accg47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "accg48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "accg49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "accg50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "accg51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "accg52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "accg53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "accg54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "accg55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "accg56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "accg57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "accg58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "accg59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "accg60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "accg61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "accg62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "accg63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_accg_names = +{ + & frv_cgen_opval_accg_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] = +{ + { "acc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "acc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "acc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "acc3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "acc4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "acc5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "acc6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "acc7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "acc8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "acc9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "acc10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "acc11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "acc12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "acc13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "acc14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "acc15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "acc16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "acc17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "acc18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "acc19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "acc20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "acc21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "acc22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "acc23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "acc24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "acc25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "acc26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "acc27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "acc28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "acc29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "acc30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "acc31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "acc32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "acc33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "acc34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "acc35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "acc36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "acc37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "acc38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "acc39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "acc40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "acc41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "acc42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "acc43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "acc44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "acc45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "acc46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "acc47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "acc48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "acc49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "acc50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "acc51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "acc52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "acc53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "acc54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "acc55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "acc56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "acc57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "acc58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "acc59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "acc60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "acc61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "acc62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "acc63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_acc_names = +{ + & frv_cgen_opval_acc_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] = +{ + { "iacc0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_iacc0_names = +{ + & frv_cgen_opval_iacc0_names_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] = +{ + { "icc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "icc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "icc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "icc3", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_iccr_names = +{ + & frv_cgen_opval_iccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] = +{ + { "fcc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fcc3", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fccr_names = +{ + & frv_cgen_opval_fccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] = +{ + { "cc0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cc1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cc2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cc3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cc4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cc5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cc7", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cccr_names = +{ + & frv_cgen_opval_cccr_names_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] = +{ + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { ".p", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".P", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_pack = +{ + & frv_cgen_opval_h_pack_entries[0], + 3, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] = +{ + { "", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_taken = +{ + & frv_cgen_opval_h_hint_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = +{ + & frv_cgen_opval_h_hint_not_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY frv_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & frv_cgen_ifld_table[0]; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & frv_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & frv_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of frv_cgen_cpu_open to rebuild the tables. */ + +static void +frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & frv_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & frv_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (frv_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = frv_cgen_rebuild_tables; + frv_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +frv_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/frv-desc.h b/external/gpl3/gdb/dist/opcodes/frv-desc.h new file mode 100644 index 000000000000..02b3c314b5f8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-desc.h @@ -0,0 +1,844 @@ +/* CPU data header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef FRV_CPU_H +#define FRV_CPU_H + +#define CGEN_ARCH frv + +/* Given symbol S, return frv_cgen_. */ +#define CGEN_SYM(s) frv##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_FRVBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 + +/* Enums. */ + +/* Enum declaration for insn op enums. */ +typedef enum insn_op { + OP_00, OP_01, OP_02, OP_03 + , OP_04, OP_05, OP_06, OP_07 + , OP_08, OP_09, OP_0A, OP_0B + , OP_0C, OP_0D, OP_0E, OP_0F + , OP_10, OP_11, OP_12, OP_13 + , OP_14, OP_15, OP_16, OP_17 + , OP_18, OP_19, OP_1A, OP_1B + , OP_1C, OP_1D, OP_1E, OP_1F + , OP_20, OP_21, OP_22, OP_23 + , OP_24, OP_25, OP_26, OP_27 + , OP_28, OP_29, OP_2A, OP_2B + , OP_2C, OP_2D, OP_2E, OP_2F + , OP_30, OP_31, OP_32, OP_33 + , OP_34, OP_35, OP_36, OP_37 + , OP_38, OP_39, OP_3A, OP_3B + , OP_3C, OP_3D, OP_3E, OP_3F + , OP_40, OP_41, OP_42, OP_43 + , OP_44, OP_45, OP_46, OP_47 + , OP_48, OP_49, OP_4A, OP_4B + , OP_4C, OP_4D, OP_4E, OP_4F + , OP_50, OP_51, OP_52, OP_53 + , OP_54, OP_55, OP_56, OP_57 + , OP_58, OP_59, OP_5A, OP_5B + , OP_5C, OP_5D, OP_5E, OP_5F + , OP_60, OP_61, OP_62, OP_63 + , OP_64, OP_65, OP_66, OP_67 + , OP_68, OP_69, OP_6A, OP_6B + , OP_6C, OP_6D, OP_6E, OP_6F + , OP_70, OP_71, OP_72, OP_73 + , OP_74, OP_75, OP_76, OP_77 + , OP_78, OP_79, OP_7A, OP_7B + , OP_7C, OP_7D, OP_7E, OP_7F +} INSN_OP; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope1 { + OPE1_00, OPE1_01, OPE1_02, OPE1_03 + , OPE1_04, OPE1_05, OPE1_06, OPE1_07 + , OPE1_08, OPE1_09, OPE1_0A, OPE1_0B + , OPE1_0C, OPE1_0D, OPE1_0E, OPE1_0F + , OPE1_10, OPE1_11, OPE1_12, OPE1_13 + , OPE1_14, OPE1_15, OPE1_16, OPE1_17 + , OPE1_18, OPE1_19, OPE1_1A, OPE1_1B + , OPE1_1C, OPE1_1D, OPE1_1E, OPE1_1F + , OPE1_20, OPE1_21, OPE1_22, OPE1_23 + , OPE1_24, OPE1_25, OPE1_26, OPE1_27 + , OPE1_28, OPE1_29, OPE1_2A, OPE1_2B + , OPE1_2C, OPE1_2D, OPE1_2E, OPE1_2F + , OPE1_30, OPE1_31, OPE1_32, OPE1_33 + , OPE1_34, OPE1_35, OPE1_36, OPE1_37 + , OPE1_38, OPE1_39, OPE1_3A, OPE1_3B + , OPE1_3C, OPE1_3D, OPE1_3E, OPE1_3F +} INSN_OPE1; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope2 { + OPE2_00, OPE2_01, OPE2_02, OPE2_03 + , OPE2_04, OPE2_05, OPE2_06, OPE2_07 + , OPE2_08, OPE2_09, OPE2_0A, OPE2_0B + , OPE2_0C, OPE2_0D, OPE2_0E, OPE2_0F +} INSN_OPE2; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope3 { + OPE3_00, OPE3_01, OPE3_02, OPE3_03 + , OPE3_04, OPE3_05, OPE3_06, OPE3_07 +} INSN_OPE3; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope4 { + OPE4_0, OPE4_1, OPE4_2, OPE4_3 +} INSN_OPE4; + +/* Enum declaration for integer branch cond enums. */ +typedef enum int_cc { + ICC_NEV, ICC_C, ICC_V, ICC_LT + , ICC_EQ, ICC_LS, ICC_N, ICC_LE + , ICC_RA, ICC_NC, ICC_NV, ICC_GE + , ICC_NE, ICC_HI, ICC_P, ICC_GT +} INT_CC; + +/* Enum declaration for float branch cond enums. */ +typedef enum flt_cc { + FCC_NEV, FCC_U, FCC_GT, FCC_UG + , FCC_LT, FCC_UL, FCC_LG, FCC_NE + , FCC_EQ, FCC_UE, FCC_GE, FCC_UGE + , FCC_LE, FCC_ULE, FCC_O, FCC_RA +} FLT_CC; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_SP = 1, H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1 + , H_GR_GR2 = 2, H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5 + , H_GR_GR6 = 6, H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9 + , H_GR_GR10 = 10, H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13 + , H_GR_GR14 = 14, H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17 + , H_GR_GR18 = 18, H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21 + , H_GR_GR22 = 22, H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25 + , H_GR_GR26 = 26, H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29 + , H_GR_GR30 = 30, H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33 + , H_GR_GR34 = 34, H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37 + , H_GR_GR38 = 38, H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41 + , H_GR_GR42 = 42, H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45 + , H_GR_GR46 = 46, H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49 + , H_GR_GR50 = 50, H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53 + , H_GR_GR54 = 54, H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57 + , H_GR_GR58 = 58, H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61 + , H_GR_GR62 = 62, H_GR_GR63 = 63 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum fr_names { + H_FR_FR0, H_FR_FR1, H_FR_FR2, H_FR_FR3 + , H_FR_FR4, H_FR_FR5, H_FR_FR6, H_FR_FR7 + , H_FR_FR8, H_FR_FR9, H_FR_FR10, H_FR_FR11 + , H_FR_FR12, H_FR_FR13, H_FR_FR14, H_FR_FR15 + , H_FR_FR16, H_FR_FR17, H_FR_FR18, H_FR_FR19 + , H_FR_FR20, H_FR_FR21, H_FR_FR22, H_FR_FR23 + , H_FR_FR24, H_FR_FR25, H_FR_FR26, H_FR_FR27 + , H_FR_FR28, H_FR_FR29, H_FR_FR30, H_FR_FR31 + , H_FR_FR32, H_FR_FR33, H_FR_FR34, H_FR_FR35 + , H_FR_FR36, H_FR_FR37, H_FR_FR38, H_FR_FR39 + , H_FR_FR40, H_FR_FR41, H_FR_FR42, H_FR_FR43 + , H_FR_FR44, H_FR_FR45, H_FR_FR46, H_FR_FR47 + , H_FR_FR48, H_FR_FR49, H_FR_FR50, H_FR_FR51 + , H_FR_FR52, H_FR_FR53, H_FR_FR54, H_FR_FR55 + , H_FR_FR56, H_FR_FR57, H_FR_FR58, H_FR_FR59 + , H_FR_FR60, H_FR_FR61, H_FR_FR62, H_FR_FR63 +} FR_NAMES; + +/* Enum declaration for . */ +typedef enum cpr_names { + H_CPR_CPR0, H_CPR_CPR1, H_CPR_CPR2, H_CPR_CPR3 + , H_CPR_CPR4, H_CPR_CPR5, H_CPR_CPR6, H_CPR_CPR7 + , H_CPR_CPR8, H_CPR_CPR9, H_CPR_CPR10, H_CPR_CPR11 + , H_CPR_CPR12, H_CPR_CPR13, H_CPR_CPR14, H_CPR_CPR15 + , H_CPR_CPR16, H_CPR_CPR17, H_CPR_CPR18, H_CPR_CPR19 + , H_CPR_CPR20, H_CPR_CPR21, H_CPR_CPR22, H_CPR_CPR23 + , H_CPR_CPR24, H_CPR_CPR25, H_CPR_CPR26, H_CPR_CPR27 + , H_CPR_CPR28, H_CPR_CPR29, H_CPR_CPR30, H_CPR_CPR31 + , H_CPR_CPR32, H_CPR_CPR33, H_CPR_CPR34, H_CPR_CPR35 + , H_CPR_CPR36, H_CPR_CPR37, H_CPR_CPR38, H_CPR_CPR39 + , H_CPR_CPR40, H_CPR_CPR41, H_CPR_CPR42, H_CPR_CPR43 + , H_CPR_CPR44, H_CPR_CPR45, H_CPR_CPR46, H_CPR_CPR47 + , H_CPR_CPR48, H_CPR_CPR49, H_CPR_CPR50, H_CPR_CPR51 + , H_CPR_CPR52, H_CPR_CPR53, H_CPR_CPR54, H_CPR_CPR55 + , H_CPR_CPR56, H_CPR_CPR57, H_CPR_CPR58, H_CPR_CPR59 + , H_CPR_CPR60, H_CPR_CPR61, H_CPR_CPR62, H_CPR_CPR63 +} CPR_NAMES; + +/* Enum declaration for . */ +typedef enum spr_names { + H_SPR_PSR = 0, H_SPR_PCSR = 1, H_SPR_BPCSR = 2, H_SPR_TBR = 3 + , H_SPR_BPSR = 4, H_SPR_HSR0 = 16, H_SPR_HSR1 = 17, H_SPR_HSR2 = 18 + , H_SPR_HSR3 = 19, H_SPR_HSR4 = 20, H_SPR_HSR5 = 21, H_SPR_HSR6 = 22 + , H_SPR_HSR7 = 23, H_SPR_HSR8 = 24, H_SPR_HSR9 = 25, H_SPR_HSR10 = 26 + , H_SPR_HSR11 = 27, H_SPR_HSR12 = 28, H_SPR_HSR13 = 29, H_SPR_HSR14 = 30 + , H_SPR_HSR15 = 31, H_SPR_HSR16 = 32, H_SPR_HSR17 = 33, H_SPR_HSR18 = 34 + , H_SPR_HSR19 = 35, H_SPR_HSR20 = 36, H_SPR_HSR21 = 37, H_SPR_HSR22 = 38 + , H_SPR_HSR23 = 39, H_SPR_HSR24 = 40, H_SPR_HSR25 = 41, H_SPR_HSR26 = 42 + , H_SPR_HSR27 = 43, H_SPR_HSR28 = 44, H_SPR_HSR29 = 45, H_SPR_HSR30 = 46 + , H_SPR_HSR31 = 47, H_SPR_HSR32 = 48, H_SPR_HSR33 = 49, H_SPR_HSR34 = 50 + , H_SPR_HSR35 = 51, H_SPR_HSR36 = 52, H_SPR_HSR37 = 53, H_SPR_HSR38 = 54 + , H_SPR_HSR39 = 55, H_SPR_HSR40 = 56, H_SPR_HSR41 = 57, H_SPR_HSR42 = 58 + , H_SPR_HSR43 = 59, H_SPR_HSR44 = 60, H_SPR_HSR45 = 61, H_SPR_HSR46 = 62 + , H_SPR_HSR47 = 63, H_SPR_HSR48 = 64, H_SPR_HSR49 = 65, H_SPR_HSR50 = 66 + , H_SPR_HSR51 = 67, H_SPR_HSR52 = 68, H_SPR_HSR53 = 69, H_SPR_HSR54 = 70 + , H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74 + , H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78 + , H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272 + , H_SPR_LCR = 273, H_SPR_IACC0H = 280, H_SPR_IACC0L = 281, H_SPR_ISR = 288 + , H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353, H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355 + , H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357, H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359 + , H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361, H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363 + , H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365, H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367 + , H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369, H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371 + , H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373, H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375 + , H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377, H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379 + , H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381, H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383 + , H_SPR_NESR0 = 384, H_SPR_NESR1 = 385, H_SPR_NESR2 = 386, H_SPR_NESR3 = 387 + , H_SPR_NESR4 = 388, H_SPR_NESR5 = 389, H_SPR_NESR6 = 390, H_SPR_NESR7 = 391 + , H_SPR_NESR8 = 392, H_SPR_NESR9 = 393, H_SPR_NESR10 = 394, H_SPR_NESR11 = 395 + , H_SPR_NESR12 = 396, H_SPR_NESR13 = 397, H_SPR_NESR14 = 398, H_SPR_NESR15 = 399 + , H_SPR_NESR16 = 400, H_SPR_NESR17 = 401, H_SPR_NESR18 = 402, H_SPR_NESR19 = 403 + , H_SPR_NESR20 = 404, H_SPR_NESR21 = 405, H_SPR_NESR22 = 406, H_SPR_NESR23 = 407 + , H_SPR_NESR24 = 408, H_SPR_NESR25 = 409, H_SPR_NESR26 = 410, H_SPR_NESR27 = 411 + , H_SPR_NESR28 = 412, H_SPR_NESR29 = 413, H_SPR_NESR30 = 414, H_SPR_NESR31 = 415 + , H_SPR_NECR = 416, H_SPR_GNER0 = 432, H_SPR_GNER1 = 433, H_SPR_FNER0 = 434 + , H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512, H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514 + , H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516, H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518 + , H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520, H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522 + , H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524, H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526 + , H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528, H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530 + , H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532, H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534 + , H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536, H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538 + , H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540, H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542 + , H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544, H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546 + , H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548, H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550 + , H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552, H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554 + , H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556, H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558 + , H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560, H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562 + , H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564, H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566 + , H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568, H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570 + , H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572, H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574 + , H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576, H_SPR_ESR1 = 577, H_SPR_ESR2 = 578 + , H_SPR_ESR3 = 579, H_SPR_ESR4 = 580, H_SPR_ESR5 = 581, H_SPR_ESR6 = 582 + , H_SPR_ESR7 = 583, H_SPR_ESR8 = 584, H_SPR_ESR9 = 585, H_SPR_ESR10 = 586 + , H_SPR_ESR11 = 587, H_SPR_ESR12 = 588, H_SPR_ESR13 = 589, H_SPR_ESR14 = 590 + , H_SPR_ESR15 = 591, H_SPR_ESR16 = 592, H_SPR_ESR17 = 593, H_SPR_ESR18 = 594 + , H_SPR_ESR19 = 595, H_SPR_ESR20 = 596, H_SPR_ESR21 = 597, H_SPR_ESR22 = 598 + , H_SPR_ESR23 = 599, H_SPR_ESR24 = 600, H_SPR_ESR25 = 601, H_SPR_ESR26 = 602 + , H_SPR_ESR27 = 603, H_SPR_ESR28 = 604, H_SPR_ESR29 = 605, H_SPR_ESR30 = 606 + , H_SPR_ESR31 = 607, H_SPR_ESR32 = 608, H_SPR_ESR33 = 609, H_SPR_ESR34 = 610 + , H_SPR_ESR35 = 611, H_SPR_ESR36 = 612, H_SPR_ESR37 = 613, H_SPR_ESR38 = 614 + , H_SPR_ESR39 = 615, H_SPR_ESR40 = 616, H_SPR_ESR41 = 617, H_SPR_ESR42 = 618 + , H_SPR_ESR43 = 619, H_SPR_ESR44 = 620, H_SPR_ESR45 = 621, H_SPR_ESR46 = 622 + , H_SPR_ESR47 = 623, H_SPR_ESR48 = 624, H_SPR_ESR49 = 625, H_SPR_ESR50 = 626 + , H_SPR_ESR51 = 627, H_SPR_ESR52 = 628, H_SPR_ESR53 = 629, H_SPR_ESR54 = 630 + , H_SPR_ESR55 = 631, H_SPR_ESR56 = 632, H_SPR_ESR57 = 633, H_SPR_ESR58 = 634 + , H_SPR_ESR59 = 635, H_SPR_ESR60 = 636, H_SPR_ESR61 = 637, H_SPR_ESR62 = 638 + , H_SPR_ESR63 = 639, H_SPR_EIR0 = 640, H_SPR_EIR1 = 641, H_SPR_EIR2 = 642 + , H_SPR_EIR3 = 643, H_SPR_EIR4 = 644, H_SPR_EIR5 = 645, H_SPR_EIR6 = 646 + , H_SPR_EIR7 = 647, H_SPR_EIR8 = 648, H_SPR_EIR9 = 649, H_SPR_EIR10 = 650 + , H_SPR_EIR11 = 651, H_SPR_EIR12 = 652, H_SPR_EIR13 = 653, H_SPR_EIR14 = 654 + , H_SPR_EIR15 = 655, H_SPR_EIR16 = 656, H_SPR_EIR17 = 657, H_SPR_EIR18 = 658 + , H_SPR_EIR19 = 659, H_SPR_EIR20 = 660, H_SPR_EIR21 = 661, H_SPR_EIR22 = 662 + , H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666 + , H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670 + , H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768 + , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_SCR0 = 832 + , H_SPR_SCR1 = 833, H_SPR_SCR2 = 834, H_SPR_SCR3 = 835, H_SPR_FSR0 = 1024 + , H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028 + , H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032 + , H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036 + , H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038, H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040 + , H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042, H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044 + , H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046, H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048 + , H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050, H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052 + , H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054, H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056 + , H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058, H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060 + , H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062, H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064 + , H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066, H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068 + , H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070, H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072 + , H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074, H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076 + , H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078, H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080 + , H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082, H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084 + , H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086, H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088 + , H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092, H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096 + , H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100, H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104 + , H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108, H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112 + , H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116, H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120 + , H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124, H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128 + , H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132, H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136 + , H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140, H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144 + , H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148, H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089 + , H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093, H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097 + , H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101, H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105 + , H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109, H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113 + , H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117, H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121 + , H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125, H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129 + , H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133, H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137 + , H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141, H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145 + , H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149, H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272 + , H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280, H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282 + , H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284, H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286 + , H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288, H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290 + , H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292, H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294 + , H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296, H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298 + , H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300, H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302 + , H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304, H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306 + , H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308, H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310 + , H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312, H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314 + , H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316, H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318 + , H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320, H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322 + , H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324, H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326 + , H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328, H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330 + , H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332, H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334 + , H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336, H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338 + , H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340, H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342 + , H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344, H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348 + , H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352, H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356 + , H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360, H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364 + , H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368, H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372 + , H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376, H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380 + , H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384, H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388 + , H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392, H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396 + , H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400, H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404 + , H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345, H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349 + , H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353, H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357 + , H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361, H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365 + , H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369, H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373 + , H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377, H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381 + , H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385, H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389 + , H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393, H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397 + , H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401, H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405 + , H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536, H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538 + , H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540, H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542 + , H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544, H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546 + , H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548, H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550 + , H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552, H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554 + , H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556, H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558 + , H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560, H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562 + , H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564, H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566 + , H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568, H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570 + , H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572, H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574 + , H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576, H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578 + , H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580, H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582 + , H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584, H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586 + , H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588, H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590 + , H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592, H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594 + , H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596, H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598 + , H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600, H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602 + , H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604, H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606 + , H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608, H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610 + , H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612, H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614 + , H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616, H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618 + , H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620, H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622 + , H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624, H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626 + , H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628, H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630 + , H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632, H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634 + , H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636, H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638 + , H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640, H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642 + , H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644, H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646 + , H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648, H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650 + , H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652, H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654 + , H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656, H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658 + , H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660, H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662 + , H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664, H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666 + , H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668, H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670 + , H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672, H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674 + , H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676, H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678 + , H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680, H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682 + , H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684, H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686 + , H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688, H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690 + , H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692, H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694 + , H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696, H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698 + , H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700, H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702 + , H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704, H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706 + , H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708, H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710 + , H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712, H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714 + , H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716, H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718 + , H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720, H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722 + , H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724, H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726 + , H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728, H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730 + , H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732, H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734 + , H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736, H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738 + , H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740, H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742 + , H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744, H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746 + , H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748, H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750 + , H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752, H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754 + , H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756, H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758 + , H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760, H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762 + , H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764, H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766 + , H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768, H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770 + , H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772, H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774 + , H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776, H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778 + , H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780, H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782 + , H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784, H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786 + , H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788, H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790 + , H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792, H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794 + , H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796, H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798 + , H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800, H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802 + , H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804, H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806 + , H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808, H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810 + , H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812, H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814 + , H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816, H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818 + , H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820, H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822 + , H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824, H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826 + , H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828, H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830 + , H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832, H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834 + , H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836, H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838 + , H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840, H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842 + , H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844, H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846 + , H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848, H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850 + , H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852, H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854 + , H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856, H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858 + , H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860, H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862 + , H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864, H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866 + , H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868, H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870 + , H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872, H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874 + , H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876, H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878 + , H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880, H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882 + , H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884, H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886 + , H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888, H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890 + , H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892, H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894 + , H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896, H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898 + , H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900, H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902 + , H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904, H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906 + , H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908, H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910 + , H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914 + , H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918 + , H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922 + , H_SPR_IAMVR1 = 1925, H_SPR_DAMVR1 = 1927, H_SPR_CXNR = 1936, H_SPR_TTBR = 1937 + , H_SPR_TPLR = 1938, H_SPR_TPPR = 1939, H_SPR_TPXR = 1940, H_SPR_TIMERH = 1952 + , H_SPR_TIMERL = 1953, H_SPR_TIMERD = 1954, H_SPR_DCR = 2048, H_SPR_BRR = 2049 + , H_SPR_NMAR = 2050, H_SPR_BTBR = 2051, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053 + , H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057 + , H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061 + , H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065 + , H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069 + , H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073 + , H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077 + , H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081 + , H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085 + , H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089 + , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2304, H_SPR_CPCR = 2305 + , H_SPR_CPSR = 2306, H_SPR_CPTR = 2307, H_SPR_CPHSR0 = 2308, H_SPR_CPHSR1 = 2309 + , H_SPR_CPESR0 = 2320, H_SPR_CPESR1 = 2321, H_SPR_CPEMR0 = 2322, H_SPR_CPEMR1 = 2323 + , H_SPR_IPERR0 = 2324, H_SPR_IPERR1 = 2325, H_SPR_IPJSR = 2326, H_SPR_IPJRR = 2327 + , H_SPR_IPCSR0 = 2336, H_SPR_IPCSR1 = 2337, H_SPR_IPCWER0 = 2338, H_SPR_IPCWER1 = 2339 + , H_SPR_IPCWR = 2340, H_SPR_MBHSR = 2352, H_SPR_MBSSR = 2353, H_SPR_MBRSR = 2354 + , H_SPR_MBSDR = 2355, H_SPR_MBRDR = 2356, H_SPR_MBSMR = 2357, H_SPR_MBSTR0 = 2359 + , H_SPR_MBSTR1 = 2360, H_SPR_SLPR = 2368, H_SPR_SLDR = 2369, H_SPR_SLHSR = 2370 + , H_SPR_SLTR = 2371, H_SPR_SLWR = 2372, H_SPR_IHSR8 = 3848, H_SPR_IHSR9 = 3849 + , H_SPR_IHSR10 = 3850 +} SPR_NAMES; + +/* Enum declaration for . */ +typedef enum accg_names { + H_ACCG_ACCG0, H_ACCG_ACCG1, H_ACCG_ACCG2, H_ACCG_ACCG3 + , H_ACCG_ACCG4, H_ACCG_ACCG5, H_ACCG_ACCG6, H_ACCG_ACCG7 + , H_ACCG_ACCG8, H_ACCG_ACCG9, H_ACCG_ACCG10, H_ACCG_ACCG11 + , H_ACCG_ACCG12, H_ACCG_ACCG13, H_ACCG_ACCG14, H_ACCG_ACCG15 + , H_ACCG_ACCG16, H_ACCG_ACCG17, H_ACCG_ACCG18, H_ACCG_ACCG19 + , H_ACCG_ACCG20, H_ACCG_ACCG21, H_ACCG_ACCG22, H_ACCG_ACCG23 + , H_ACCG_ACCG24, H_ACCG_ACCG25, H_ACCG_ACCG26, H_ACCG_ACCG27 + , H_ACCG_ACCG28, H_ACCG_ACCG29, H_ACCG_ACCG30, H_ACCG_ACCG31 + , H_ACCG_ACCG32, H_ACCG_ACCG33, H_ACCG_ACCG34, H_ACCG_ACCG35 + , H_ACCG_ACCG36, H_ACCG_ACCG37, H_ACCG_ACCG38, H_ACCG_ACCG39 + , H_ACCG_ACCG40, H_ACCG_ACCG41, H_ACCG_ACCG42, H_ACCG_ACCG43 + , H_ACCG_ACCG44, H_ACCG_ACCG45, H_ACCG_ACCG46, H_ACCG_ACCG47 + , H_ACCG_ACCG48, H_ACCG_ACCG49, H_ACCG_ACCG50, H_ACCG_ACCG51 + , H_ACCG_ACCG52, H_ACCG_ACCG53, H_ACCG_ACCG54, H_ACCG_ACCG55 + , H_ACCG_ACCG56, H_ACCG_ACCG57, H_ACCG_ACCG58, H_ACCG_ACCG59 + , H_ACCG_ACCG60, H_ACCG_ACCG61, H_ACCG_ACCG62, H_ACCG_ACCG63 +} ACCG_NAMES; + +/* Enum declaration for . */ +typedef enum acc_names { + H_ACC40_ACC0, H_ACC40_ACC1, H_ACC40_ACC2, H_ACC40_ACC3 + , H_ACC40_ACC4, H_ACC40_ACC5, H_ACC40_ACC6, H_ACC40_ACC7 + , H_ACC40_ACC8, H_ACC40_ACC9, H_ACC40_ACC10, H_ACC40_ACC11 + , H_ACC40_ACC12, H_ACC40_ACC13, H_ACC40_ACC14, H_ACC40_ACC15 + , H_ACC40_ACC16, H_ACC40_ACC17, H_ACC40_ACC18, H_ACC40_ACC19 + , H_ACC40_ACC20, H_ACC40_ACC21, H_ACC40_ACC22, H_ACC40_ACC23 + , H_ACC40_ACC24, H_ACC40_ACC25, H_ACC40_ACC26, H_ACC40_ACC27 + , H_ACC40_ACC28, H_ACC40_ACC29, H_ACC40_ACC30, H_ACC40_ACC31 + , H_ACC40_ACC32, H_ACC40_ACC33, H_ACC40_ACC34, H_ACC40_ACC35 + , H_ACC40_ACC36, H_ACC40_ACC37, H_ACC40_ACC38, H_ACC40_ACC39 + , H_ACC40_ACC40, H_ACC40_ACC41, H_ACC40_ACC42, H_ACC40_ACC43 + , H_ACC40_ACC44, H_ACC40_ACC45, H_ACC40_ACC46, H_ACC40_ACC47 + , H_ACC40_ACC48, H_ACC40_ACC49, H_ACC40_ACC50, H_ACC40_ACC51 + , H_ACC40_ACC52, H_ACC40_ACC53, H_ACC40_ACC54, H_ACC40_ACC55 + , H_ACC40_ACC56, H_ACC40_ACC57, H_ACC40_ACC58, H_ACC40_ACC59 + , H_ACC40_ACC60, H_ACC40_ACC61, H_ACC40_ACC62, H_ACC40_ACC63 +} ACC_NAMES; + +/* Enum declaration for . */ +typedef enum iacc0_names { + H_IACC0_IACC0 +} IACC0_NAMES; + +/* Enum declaration for . */ +typedef enum iccr_names { + H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3 +} ICCR_NAMES; + +/* Enum declaration for . */ +typedef enum fccr_names { + H_FCCR_FCC0, H_FCCR_FCC1, H_FCCR_FCC2, H_FCCR_FCC3 +} FCCR_NAMES; + +/* Enum declaration for . */ +typedef enum cccr_names { + H_CCCR_CC0, H_CCCR_CC1, H_CCCR_CC2, H_CCCR_CC3 + , H_CCCR_CC4, H_CCCR_CC5, H_CCCR_CC6, H_CCCR_CC7 +} CCCR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_FRV, MACH_FR550, MACH_FR500 + , MACH_FR450, MACH_FR400, MACH_TOMCAT, MACH_SIMPLE + , MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_FRV, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum unit_attr { + UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01 + , UNIT_I2, UNIT_I3, UNIT_IALL, UNIT_FM0 + , UNIT_FM1, UNIT_FM01, UNIT_FM2, UNIT_FM3 + , UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1 + , UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC + , UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL + , UNIT_MDUALACC, UNIT_MDCUTSSI, UNIT_MCLRACC_1, UNIT_NUM_UNITS +} UNIT_ATTR; + +/* Enum declaration for fr400 major insn categories. */ +typedef enum fr400_major_attr { + FR400_MAJOR_NONE, FR400_MAJOR_I_1, FR400_MAJOR_I_2, FR400_MAJOR_I_3 + , FR400_MAJOR_I_4, FR400_MAJOR_I_5, FR400_MAJOR_B_1, FR400_MAJOR_B_2 + , FR400_MAJOR_B_3, FR400_MAJOR_B_4, FR400_MAJOR_B_5, FR400_MAJOR_B_6 + , FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2 +} FR400_MAJOR_ATTR; + +/* Enum declaration for fr450 major insn categories. */ +typedef enum fr450_major_attr { + FR450_MAJOR_NONE, FR450_MAJOR_I_1, FR450_MAJOR_I_2, FR450_MAJOR_I_3 + , FR450_MAJOR_I_4, FR450_MAJOR_I_5, FR450_MAJOR_B_1, FR450_MAJOR_B_2 + , FR450_MAJOR_B_3, FR450_MAJOR_B_4, FR450_MAJOR_B_5, FR450_MAJOR_B_6 + , FR450_MAJOR_C_1, FR450_MAJOR_C_2, FR450_MAJOR_M_1, FR450_MAJOR_M_2 + , FR450_MAJOR_M_3, FR450_MAJOR_M_4, FR450_MAJOR_M_5, FR450_MAJOR_M_6 +} FR450_MAJOR_ATTR; + +/* Enum declaration for fr500 major insn categories. */ +typedef enum fr500_major_attr { + FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3 + , FR500_MAJOR_I_4, FR500_MAJOR_I_5, FR500_MAJOR_I_6, FR500_MAJOR_B_1 + , FR500_MAJOR_B_2, FR500_MAJOR_B_3, FR500_MAJOR_B_4, FR500_MAJOR_B_5 + , FR500_MAJOR_B_6, FR500_MAJOR_C_1, FR500_MAJOR_C_2, FR500_MAJOR_F_1 + , FR500_MAJOR_F_2, FR500_MAJOR_F_3, FR500_MAJOR_F_4, FR500_MAJOR_F_5 + , FR500_MAJOR_F_6, FR500_MAJOR_F_7, FR500_MAJOR_F_8, FR500_MAJOR_M_1 + , FR500_MAJOR_M_2, FR500_MAJOR_M_3, FR500_MAJOR_M_4, FR500_MAJOR_M_5 + , FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8 +} FR500_MAJOR_ATTR; + +/* Enum declaration for fr550 major insn categories. */ +typedef enum fr550_major_attr { + FR550_MAJOR_NONE, FR550_MAJOR_I_1, FR550_MAJOR_I_2, FR550_MAJOR_I_3 + , FR550_MAJOR_I_4, FR550_MAJOR_I_5, FR550_MAJOR_I_6, FR550_MAJOR_I_7 + , FR550_MAJOR_I_8, FR550_MAJOR_B_1, FR550_MAJOR_B_2, FR550_MAJOR_B_3 + , FR550_MAJOR_B_4, FR550_MAJOR_B_5, FR550_MAJOR_B_6, FR550_MAJOR_C_1 + , FR550_MAJOR_C_2, FR550_MAJOR_F_1, FR550_MAJOR_F_2, FR550_MAJOR_F_3 + , FR550_MAJOR_F_4, FR550_MAJOR_M_1, FR550_MAJOR_M_2, FR550_MAJOR_M_3 + , FR550_MAJOR_M_4, FR550_MAJOR_M_5 +} FR550_MAJOR_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for frv ifield types. */ +typedef enum ifield_type { + FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP + , FRV_F_OPE1, FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4 + , FRV_F_GRI, FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI + , FRV_F_FRJ, FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ + , FRV_F_CPRK, FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI + , FRV_F_ACC40UI, FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI + , FRV_F_CRJ, FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT + , FRV_F_CRJ_FLOAT, FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3 + , FRV_F_FCCI_1, FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK + , FRV_F_EIR, FRV_F_S10, FRV_F_S12, FRV_F_D12 + , FRV_F_U16, FRV_F_S16, FRV_F_S6, FRV_F_S6_1 + , FRV_F_U6, FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L + , FRV_F_U12, FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND + , FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK + , FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H + , FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6 + , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD + , FRV_F_LRAS, FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL + , FRV_F_ICCI_2_NULL, FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL + , FRV_F_FCCI_3_NULL, FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL + , FRV_F_GRK_NULL, FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL + , FRV_F_RD_NULL, FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL + , FRV_F_LABEL16_NULL, FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3 + , FRV_F_MISC_NULL_4, FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7 + , FRV_F_MISC_NULL_8, FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11 + , FRV_F_LRA_NULL, FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON + , FRV_F_RELOC_ANN, FRV_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) FRV_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for frv hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_RELOC_ANN, HW_H_PC, HW_H_PSR_IMPLE + , HW_H_PSR_VER, HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM + , HW_H_PSR_BE, HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM + , HW_H_PSR_PIL, HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S + , HW_H_TBR_TBA, HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET + , HW_H_GR, HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO + , HW_H_FR, HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI + , HW_H_FR_LO, HW_H_FR_0, HW_H_FR_1, HW_H_FR_2 + , HW_H_FR_3, HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR + , HW_H_ACCG, HW_H_ACC40S, HW_H_ACC40U, HW_H_IACC0 + , HW_H_ICCR, HW_H_FCCR, HW_H_CCCR, HW_H_PACK + , HW_H_HINT_TAKEN, HW_H_HINT_NOT_TAKEN, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) + +/* Enum declaration for frv operand types. */ +typedef enum cgen_operand_type { + FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ + , FRV_OPERAND_GRK, FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK + , FRV_OPERAND_ACC40SI, FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK + , FRV_OPERAND_ACCGI, FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ + , FRV_OPERAND_CPRK, FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ + , FRV_OPERAND_FRINTK, FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK + , FRV_OPERAND_FRKHI, FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ + , FRV_OPERAND_FRDOUBLEK, FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT + , FRV_OPERAND_CRJ_FLOAT, FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1 + , FRV_OPERAND_ICCI_2, FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2 + , FRV_OPERAND_FCCI_3, FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10 + , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1 + , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND + , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI + , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16 + , FRV_OPERAND_LRAE, FRV_OPERAND_LRAD, FRV_OPERAND_LRAS, FRV_OPERAND_TLBPROPX + , FRV_OPERAND_TLBPRL, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN + , FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12 + , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 + , FRV_OPERAND_UHI16, FRV_OPERAND_LABEL24, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S + , FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET + , FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT, FRV_OPERAND_LDANN, FRV_OPERAND_LDDANN + , FRV_OPERAND_CALLANN, FRV_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 89 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING + , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT + , CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR + , CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PRIVILEGED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NON_EXCEPTING)) != 0) +#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_CONDITIONAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FR_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PRESERVE_OVF)) != 0) +#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_AUDIO)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld frv_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_spr_names; +extern CGEN_KEYWORD frv_cgen_opval_accg_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_iacc0_names; +extern CGEN_KEYWORD frv_cgen_opval_iccr_names; +extern CGEN_KEYWORD frv_cgen_opval_fccr_names; +extern CGEN_KEYWORD frv_cgen_opval_cccr_names; +extern CGEN_KEYWORD frv_cgen_opval_h_pack; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_taken; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken; + +extern const CGEN_HW_ENTRY frv_cgen_hw_table[]; + + + +#endif /* FRV_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/frv-dis.c b/external/gpl3/gdb/dist/opcodes/frv-dis.c new file mode 100644 index 000000000000..ff9a57d20305 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-dis.c @@ -0,0 +1,817 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ +static void +print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long reloc_ann ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "@"); +} + +static void +print_spr (CGEN_CPU_DESC cd, + void * dis_info, + CGEN_KEYWORD *names, + long regno, + unsigned int attrs) +{ + /* Use the register index format for any unnamed registers. */ + if (cgen_keyword_lookup_value (names, regno) == NULL) + { + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "spr[%ld]", regno); + } + else + print_keyword (cd, dis_info, names, regno, attrs); +} + +static void +print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value); +} + +static void +print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); +} + +/* -- */ + +void frv_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +frv_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case FRV_OPERAND_A0 : + print_normal (cd, info, fields->f_A, 0, pc, length); + break; + case FRV_OPERAND_A1 : + print_normal (cd, info, fields->f_A, 0, pc, length); + break; + case FRV_OPERAND_ACC40SI : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0); + break; + case FRV_OPERAND_ACC40SK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0); + break; + case FRV_OPERAND_ACC40UI : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0); + break; + case FRV_OPERAND_ACC40UK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0); + break; + case FRV_OPERAND_ACCGI : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0); + break; + case FRV_OPERAND_ACCGK : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0); + break; + case FRV_OPERAND_CCI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0); + break; + case FRV_OPERAND_CPRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CPRI : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0); + break; + case FRV_OPERAND_CPRJ : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0); + break; + case FRV_OPERAND_CPRK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CRI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0); + break; + case FRV_OPERAND_CRJ : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0); + break; + case FRV_OPERAND_CRJ_FLOAT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0); + break; + case FRV_OPERAND_CRJ_INT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0); + break; + case FRV_OPERAND_CRK : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0); + break; + case FRV_OPERAND_FCCI_1 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0); + break; + case FRV_OPERAND_FCCI_2 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0); + break; + case FRV_OPERAND_FCCI_3 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0); + break; + case FRV_OPERAND_FCCK : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0); + break; + case FRV_OPERAND_FRDOUBLEI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRDOUBLEJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTIEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRINTJEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRINTK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRINTKEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKHI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKLO : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_GRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0); + break; + case FRV_OPERAND_GRJ : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0); + break; + case FRV_OPERAND_GRK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKHI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKLO : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_ICCI_1 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0); + break; + case FRV_OPERAND_ICCI_2 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0); + break; + case FRV_OPERAND_ICCI_3 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0); + break; + case FRV_OPERAND_LI : + print_normal (cd, info, fields->f_LI, 0, pc, length); + break; + case FRV_OPERAND_LRAD : + print_normal (cd, info, fields->f_LRAD, 0, pc, length); + break; + case FRV_OPERAND_LRAE : + print_normal (cd, info, fields->f_LRAE, 0, pc, length); + break; + case FRV_OPERAND_LRAS : + print_normal (cd, info, fields->f_LRAS, 0, pc, length); + break; + case FRV_OPERAND_TLBPRL : + print_normal (cd, info, fields->f_TLBPRL, 0, pc, length); + break; + case FRV_OPERAND_TLBPROPX : + print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length); + break; + case FRV_OPERAND_AE : + print_normal (cd, info, fields->f_ae, 0|(1<f_reloc_ann, 0, pc, length); + break; + case FRV_OPERAND_CCOND : + print_normal (cd, info, fields->f_ccond, 0|(1<f_cond, 0|(1<f_d12, 0|(1<f_debug, 0|(1<f_eir, 0, pc, length); + break; + case FRV_OPERAND_HINT : + print_normal (cd, info, fields->f_hint, 0|(1<f_hint, 0); + break; + case FRV_OPERAND_HINT_TAKEN : + print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0); + break; + case FRV_OPERAND_LABEL16 : + print_address (cd, info, fields->f_label16, 0|(1<f_label24, 0|(1<f_reloc_ann, 0, pc, length); + break; + case FRV_OPERAND_LDDANN : + print_at (cd, info, fields->f_reloc_ann, 0, pc, length); + break; + case FRV_OPERAND_LOCK : + print_normal (cd, info, fields->f_lock, 0|(1<f_pack, 0); + break; + case FRV_OPERAND_S10 : + print_normal (cd, info, fields->f_s10, 0|(1<f_d12, 0|(1<f_s16, 0|(1<f_s5, 0|(1<f_s6, 0|(1<f_s6_1, 0|(1<f_s16, 0|(1<f_spr, 0|(1<f_u12, 0|(1<f_u16, 0|(1<f_u6, 0|(1<f_u16, 0, pc, length); + break; + case FRV_OPERAND_ULO16 : + print_lo (cd, info, fields->f_u16, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const frv_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +frv_cgen_init_dis (CGEN_CPU_DESC cd) +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->print_handlers = & frv_cgen_print_handlers[0]; + cd->print_operand = frv_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_frv (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_frv +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + frv_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/frv-ibld.c b/external/gpl3/gdb/dist/opcodes/frv-ibld.c new file mode 100644 index 000000000000..61db1bf86e9e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-ibld.c @@ -0,0 +1,2253 @@ +/* Instruction building/extraction support for frv. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * frv_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +frv_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A0 : + errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_A1 : + errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SI : + errmsg = insert_normal (cd, fields->f_ACC40Si, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SK : + errmsg = insert_normal (cd, fields->f_ACC40Sk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UI : + errmsg = insert_normal (cd, fields->f_ACC40Ui, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UK : + errmsg = insert_normal (cd, fields->f_ACC40Uk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGI : + errmsg = insert_normal (cd, fields->f_ACCGi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGK : + errmsg = insert_normal (cd, fields->f_ACCGk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CCI : + errmsg = insert_normal (cd, fields->f_CCi, 0, 0, 11, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRI : + errmsg = insert_normal (cd, fields->f_CPRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRJ : + errmsg = insert_normal (cd, fields->f_CPRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CRI : + errmsg = insert_normal (cd, fields->f_CRi, 0, 0, 14, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ : + errmsg = insert_normal (cd, fields->f_CRj, 0, 0, 2, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = insert_normal (cd, fields->f_CRj_float, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_INT : + { + long value = fields->f_CRj_int; + value = ((value) - (4)); + errmsg = insert_normal (cd, value, 0, 0, 26, 2, 32, total_length, buffer); + } + break; + case FRV_OPERAND_CRK : + errmsg = insert_normal (cd, fields->f_CRk, 0, 0, 27, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = insert_normal (cd, fields->f_FCCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = insert_normal (cd, fields->f_FCCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = insert_normal (cd, fields->f_FCCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCK : + errmsg = insert_normal (cd, fields->f_FCCk, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKHI : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKLO : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRI : + errmsg = insert_normal (cd, fields->f_GRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRJ : + errmsg = insert_normal (cd, fields->f_GRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKHI : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKLO : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = insert_normal (cd, fields->f_ICCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = insert_normal (cd, fields->f_ICCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = insert_normal (cd, fields->f_ICCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LI : + errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_LRAD : + errmsg = insert_normal (cd, fields->f_LRAD, 0, 0, 4, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_LRAE : + errmsg = insert_normal (cd, fields->f_LRAE, 0, 0, 5, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_LRAS : + errmsg = insert_normal (cd, fields->f_LRAS, 0, 0, 3, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_TLBPRL : + errmsg = insert_normal (cd, fields->f_TLBPRL, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_TLBPROPX : + errmsg = insert_normal (cd, fields->f_TLBPRopx, 0, 0, 28, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_AE : + errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_CALLANN : + errmsg = insert_normal (cd, fields->f_reloc_ann, 0, 0, 0, 0, 32, total_length, buffer); + break; + case FRV_OPERAND_CCOND : + errmsg = insert_normal (cd, fields->f_ccond, 0, 0, 12, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_COND : + errmsg = insert_normal (cd, fields->f_cond, 0, 0, 8, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_D12 : + errmsg = insert_normal (cd, fields->f_d12, 0|(1<f_debug, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_EIR : + errmsg = insert_normal (cd, fields->f_eir, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LABEL16 : + { + long value = fields->f_label16; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<> (20)); + FLD (f_labelL18) = ((((UINT) (((FLD (f_label24)) - (pc))) >> (2))) & (262143)); +} + errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<f_labelL18, 0, 0, 17, 18, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_LDANN : + errmsg = insert_normal (cd, fields->f_reloc_ann, 0, 0, 0, 0, 32, total_length, buffer); + break; + case FRV_OPERAND_LDDANN : + errmsg = insert_normal (cd, fields->f_reloc_ann, 0, 0, 0, 0, 32, total_length, buffer); + break; + case FRV_OPERAND_LOCK : + errmsg = insert_normal (cd, fields->f_lock, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_PACK : + errmsg = insert_normal (cd, fields->f_pack, 0, 0, 31, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_S10 : + errmsg = insert_normal (cd, fields->f_s10, 0|(1<f_d12, 0|(1<f_s16, 0|(1<f_s5, 0|(1<f_s6, 0|(1<f_s6_1, 0|(1<f_s16, 0|(1<> (6)); + FLD (f_spr_l) = ((FLD (f_spr)) & (63)); +} + errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_spr_l, 0, 0, 17, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U12 : + { +{ + FLD (f_u12_h) = ((SI) (FLD (f_u12)) >> (6)); + FLD (f_u12_l) = ((FLD (f_u12)) & (63)); +} + errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<f_u12_l, 0, 0, 5, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_U6 : + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_UHI16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_ULO16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int frv_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +frv_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); + break; + case FRV_OPERAND_A1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); + break; + case FRV_OPERAND_ACC40SI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 32, total_length, pc, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & value); + value = ((value) + (4)); + fields->f_CRj_int = value; + } + break; + case FRV_OPERAND_CRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 3, 32, total_length, pc, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTIEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTJEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRINTKEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI); + break; + case FRV_OPERAND_LRAD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_LRAD); + break; + case FRV_OPERAND_LRAE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_LRAE); + break; + case FRV_OPERAND_LRAS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 1, 32, total_length, pc, & fields->f_LRAS); + break; + case FRV_OPERAND_TLBPRL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_TLBPRL); + break; + case FRV_OPERAND_TLBPROPX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_TLBPRopx); + break; + case FRV_OPERAND_AE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae); + break; + case FRV_OPERAND_CALLANN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 32, total_length, pc, & fields->f_reloc_ann); + break; + case FRV_OPERAND_CCOND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 1, 32, total_length, pc, & fields->f_ccond); + break; + case FRV_OPERAND_COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_cond); + break; + case FRV_OPERAND_D12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d12); + break; + case FRV_OPERAND_DEBUG : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_debug); + break; + case FRV_OPERAND_EIR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_eir); + break; + case FRV_OPERAND_HINT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_labelH6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18); + if (length <= 0) break; +{ + FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc)); +} + } + break; + case FRV_OPERAND_LDANN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 32, total_length, pc, & fields->f_reloc_ann); + break; + case FRV_OPERAND_LDDANN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 32, total_length, pc, & fields->f_reloc_ann); + break; + case FRV_OPERAND_LOCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_lock); + break; + case FRV_OPERAND_PACK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 1, 32, total_length, pc, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s10); + break; + case FRV_OPERAND_S12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_d12); + break; + case FRV_OPERAND_S16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s16); + break; + case FRV_OPERAND_S5 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s5); + break; + case FRV_OPERAND_S6 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s6); + break; + case FRV_OPERAND_S6_1 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s6_1); + break; + case FRV_OPERAND_SLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_s16); + break; + case FRV_OPERAND_SPR : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_spr_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_spr_l); + if (length <= 0) break; +{ + FLD (f_spr) = ((((FLD (f_spr_h)) << (6))) | (FLD (f_spr_l))); +} + } + break; + case FRV_OPERAND_U12 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_u12_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l); + if (length <= 0) break; +{ + FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l))); +} + } + break; + case FRV_OPERAND_U16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u6); + break; + case FRV_OPERAND_UHI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_ULO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const frv_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const frv_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int frv_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma frv_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +frv_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case FRV_OPERAND_A0 : + value = fields->f_A; + break; + case FRV_OPERAND_A1 : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_LRAD : + value = fields->f_LRAD; + break; + case FRV_OPERAND_LRAE : + value = fields->f_LRAE; + break; + case FRV_OPERAND_LRAS : + value = fields->f_LRAS; + break; + case FRV_OPERAND_TLBPRL : + value = fields->f_TLBPRL; + break; + case FRV_OPERAND_TLBPROPX : + value = fields->f_TLBPRopx; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CALLANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LDANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_LDDANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +frv_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case FRV_OPERAND_A0 : + value = fields->f_A; + break; + case FRV_OPERAND_A1 : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_LRAD : + value = fields->f_LRAD; + break; + case FRV_OPERAND_LRAE : + value = fields->f_LRAE; + break; + case FRV_OPERAND_LRAS : + value = fields->f_LRAS; + break; + case FRV_OPERAND_TLBPRL : + value = fields->f_TLBPRL; + break; + case FRV_OPERAND_TLBPROPX : + value = fields->f_TLBPRopx; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CALLANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LDANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_LDDANN : + value = fields->f_reloc_ann; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void frv_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void frv_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +frv_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case FRV_OPERAND_A0 : + fields->f_A = value; + break; + case FRV_OPERAND_A1 : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_LRAD : + fields->f_LRAD = value; + break; + case FRV_OPERAND_LRAE : + fields->f_LRAE = value; + break; + case FRV_OPERAND_LRAS : + fields->f_LRAS = value; + break; + case FRV_OPERAND_TLBPRL : + fields->f_TLBPRL = value; + break; + case FRV_OPERAND_TLBPROPX : + fields->f_TLBPRopx = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CALLANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LDANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_LDDANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +frv_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case FRV_OPERAND_A0 : + fields->f_A = value; + break; + case FRV_OPERAND_A1 : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_LRAD : + fields->f_LRAD = value; + break; + case FRV_OPERAND_LRAE : + fields->f_LRAE = value; + break; + case FRV_OPERAND_LRAS : + fields->f_LRAS = value; + break; + case FRV_OPERAND_TLBPRL : + fields->f_TLBPRL = value; + break; + case FRV_OPERAND_TLBPROPX : + fields->f_TLBPRopx = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CALLANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LDANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_LDDANN : + fields->f_reloc_ann = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +frv_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & frv_cgen_insert_handlers[0]; + cd->extract_handlers = & frv_cgen_extract_handlers[0]; + + cd->insert_operand = frv_cgen_insert_operand; + cd->extract_operand = frv_cgen_extract_operand; + + cd->get_int_operand = frv_cgen_get_int_operand; + cd->set_int_operand = frv_cgen_set_int_operand; + cd->get_vma_operand = frv_cgen_get_vma_operand; + cd->set_vma_operand = frv_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/frv-opc.c b/external/gpl3/gdb/dist/opcodes/frv-opc.c new file mode 100644 index 000000000000..e7107a8ba2a4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-opc.c @@ -0,0 +1,6237 @@ +/* Instruction opcode table for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "elf/frv.h" +#include + +/* DEBUG appears below as argument of OP macro. */ +#undef DEBUG + +/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV + development tree. */ + +bfd_boolean +frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) + return TRUE; + break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) + return TRUE; + break; + default: + if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) + return TRUE; + break; + } + + return FALSE; +} + +/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ + +bfd_boolean +frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + case bfd_mach_fr450: + return FALSE; + default: + if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) + return TRUE; + break; + } + + return FALSE; +} + +/* Returns TRUE if {MAJOR,MACH} supports media insns. */ + +bfd_boolean +frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) + return TRUE; + break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) + return TRUE; + break; + default: + if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) + return TRUE; + break; + } + + return FALSE; +} + +bfd_boolean +frv_is_branch_insn (const CGEN_INSN *insn) +{ + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return TRUE; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return TRUE; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return TRUE; + + return FALSE; +} + +bfd_boolean +frv_is_float_insn (const CGEN_INSN *insn) +{ + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return TRUE; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return TRUE; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return TRUE; + + return FALSE; +} + +bfd_boolean +frv_is_media_insn (const CGEN_INSN *insn) +{ + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return TRUE; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return TRUE; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return TRUE; + + return FALSE; +} + +/* This table represents the allowable packing for vliw insns for the fr400. + The fr400 has only 2 vliw slots. Represent this by not allowing any insns + in the extra slots. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr400_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_I1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_FM1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_B0, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } +}; + +/* This table represents the allowable packing for vliw insns for the fr500. + The fr500 has only 4 vliw slots. Represent this by not allowing any insns + in the extra slots. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr500_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_I0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } +}; + +/* This table represents the allowable packing for vliw insns for the fr550. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr550_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 slot4 slot5 slot6 slot7 */ + { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_FM3 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_FM3, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ +}; + +static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M2 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* IACC */ UNIT_NIL, /* iacc multiply not implemented */ +/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ +/* DCPL */ UNIT_C, /* dcpl only in C unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ +}; + +static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_I2, +/* I3 */ UNIT_I3, +/* IALL */ UNIT_IALL, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_FM2, +/* FM3 */ UNIT_FM3, +/* FMALL */ UNIT_FMALL, +/* FMLOW */ UNIT_FM01, /* Only F0,F1,M0,M1 units */ +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* IACC */ UNIT_NIL, /* iacc multiply not implemented. */ +/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ +/* STORE */ UNIT_I01, /* store in I0 or I1 unit. */ +/* SCAN */ UNIT_IALL, /* scan in any integer unit. */ +/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ +/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */ +/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ +}; + +void +frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) +{ + vliw->next_slot = 0; + vliw->constraint_violation = 0; + vliw->mach = mach; + vliw->elf_flags = elf_flags; + + switch (mach) + { + case bfd_mach_fr400: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr400_unit_mapping; + break; + case bfd_mach_fr450: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr450_unit_mapping; + break; + case bfd_mach_fr550: + vliw->current_vliw = fr550_allowed_vliw; + vliw->unit_mapping = fr550_unit_mapping; + break; + default: + vliw->current_vliw = fr500_allowed_vliw; + vliw->unit_mapping = fr500_unit_mapping; + break; + } +} + +/* Return TRUE if unit1 is a match for unit2. + Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the + *_allowed_vliw tables above. */ +static bfd_boolean +match_unit (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2) +{ + /* Map any specialized implementation units to actual ones. */ + unit1 = vliw->unit_mapping[unit1]; + + if (unit1 == unit2) + return TRUE; + if (unit1 < unit2) + return FALSE; + + switch (unit1) + { + case UNIT_I01: + case UNIT_FM01: + case UNIT_B01: + /* The 01 versions of these units are within 2 enums of the 0 or 1 + versions. */ + if (unit1 - unit2 <= 2) + return TRUE; + break; + case UNIT_IALL: + case UNIT_FMALL: + /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3 + versions. */ + if (unit1 - unit2 <= 5) + return TRUE; + break; + default: + break; + } + + return FALSE; +} + +/* Return TRUE if the vliws match, FALSE otherwise. */ + +static bfd_boolean +match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) +{ + int i; + + for (i = 0; i < vliw_size; ++i) + if ((*vliw1)[i] != (*vliw2)[i]) + return FALSE; + + return TRUE; +} + +/* Find the next vliw vliw in the table that can accomodate the new insn. + If one is found then return it. Otherwise return NULL. */ + +static VLIW_COMBO * +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) +{ + int next = vliw->next_slot; + VLIW_COMBO *current = vliw->current_vliw; + VLIW_COMBO *potential; + + if (next <= 0) + { + fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n", + __LINE__); + abort (); /* Should never happen. */ + } + + /* The table is sorted by units allowed within slots, so vliws with + identical starting sequences are together. */ + potential = current; + do + { + if (match_unit (vliw, unit, (*potential)[next])) + return potential; + ++potential; + } + while (match_vliw (potential, current, next)); + + return NULL; +} + +/* Look for the given major insn type in the given vliw. + Returns TRUE if found, FALSE otherwise. */ + +static bfd_boolean +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major) + return TRUE; + + return FALSE; +} + +/* Check for constraints between the insns in the vliw due to major insn + types. */ + +static bfd_boolean +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) +{ + /* In the cpu file, all media insns are represented as being allowed in + both media units. This makes it easier since this is the case for fr500. + Catch the invalid combinations here. Insns of major class FR400_MAJOR_M_2 + cannot coexist with any other media insn in a vliw. */ + switch (major) + { + case FR400_MAJOR_M_2: + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + case FR400_MAJOR_M_1: + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + default: + break; + } + return TRUE; +} + +static bfd_boolean +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) +{ + CGEN_ATTR_VALUE_ENUM_TYPE other_major; + + /* Our caller guarantees there's at least one other instruction. */ + other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); + + /* (M4, M5) and (M4, M6) are allowed. */ + if (other_major == FR450_MAJOR_M_4) + if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) + return TRUE; + + /* Otherwise, instructions in even-numbered media categories cannot be + executed in parallel with other media instructions. */ + switch (major) + { + case FR450_MAJOR_M_2: + case FR450_MAJOR_M_4: + case FR450_MAJOR_M_6: + return !(other_major >= FR450_MAJOR_M_1 + && other_major <= FR450_MAJOR_M_6); + + case FR450_MAJOR_M_1: + case FR450_MAJOR_M_3: + case FR450_MAJOR_M_5: + return !(other_major == FR450_MAJOR_M_2 + || other_major == FR450_MAJOR_M_4 + || other_major == FR450_MAJOR_M_6); + + default: + return TRUE; + } +} + +static bfd_boolean +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit) + return TRUE; + + return FALSE; /* Not found. */ +} + +static bfd_boolean +find_major_in_slot (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_ENUM_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE slot) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot) + return TRUE; + + return FALSE; +} + +static bfd_boolean +fr550_find_media_in_vliw (FRV_VLIW *vliw) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + { + if (vliw->major[i] < FR550_MAJOR_M_1 || vliw->major[i] > FR550_MAJOR_M_5) + continue; + + /* Found a media insn, however, MNOP and MCLRACC don't count. */ + if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MNOP + || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_0 + || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1) + continue; + + return TRUE; /* Found one. */ + } + + return FALSE; +} + +static bfd_boolean +fr550_find_float_in_vliw (FRV_VLIW *vliw) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + { + if (vliw->major[i] < FR550_MAJOR_F_1 || vliw->major[i] > FR550_MAJOR_F_4) + continue; + + /* Found a floating point insn, however, FNOP doesn't count. */ + if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP) + continue; + + return TRUE; /* Found one. */ + } + + return FALSE; +} + +static bfd_boolean +fr550_check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_ENUM_TYPE major, + const CGEN_INSN *insn) +{ + CGEN_ATTR_VALUE_ENUM_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; + switch (slot) + { + case UNIT_I2: + /* If it's a store, then there must be another store in I1 */ + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_STORE) + return find_unit_in_vliw (vliw, UNIT_STORE); + break; + case UNIT_FM2: + case UNIT_FM3: + /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist + with media insns. */ + if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4 + && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP) + return ! fr550_find_media_in_vliw (vliw); + /* Media insns other than MNOP in slot m2 or m3 cannot coexist with + floating point insns. */ + if (major >= FR550_MAJOR_M_1 && major <= FR550_MAJOR_M_5 + && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP) + return ! fr550_find_float_in_vliw (vliw); + /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2 + respectively. */ + if (major == FR550_MAJOR_F_2) + return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, + slot - (UNIT_FM2 - UNIT_FM0)) + && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, + slot - (UNIT_FM2 - UNIT_FM0)); + /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2 + respectively. */ + if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5) + return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, + slot - (UNIT_FM2 - UNIT_FM0)); + /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2 + respectively. */ + if (major == FR550_MAJOR_M_4) + return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, + slot - (UNIT_FM2 - UNIT_FM0)); + break; + default: + break; + } + return TRUE; /* All OK. */ +} + +static bfd_boolean +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) +{ + /* TODO: A table might be faster for some of the more complex instances + here. */ + switch (major) + { + case FR500_MAJOR_I_1: + case FR500_MAJOR_I_4: + case FR500_MAJOR_I_5: + case FR500_MAJOR_I_6: + case FR500_MAJOR_B_1: + case FR500_MAJOR_B_2: + case FR500_MAJOR_B_3: + case FR500_MAJOR_B_4: + case FR500_MAJOR_B_5: + case FR500_MAJOR_B_6: + case FR500_MAJOR_F_4: + case FR500_MAJOR_F_8: + case FR500_MAJOR_M_8: + return TRUE; /* OK */ + case FR500_MAJOR_I_2: + /* Cannot coexist with I-3 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); + case FR500_MAJOR_I_3: + /* Cannot coexist with I-2 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2); + case FR500_MAJOR_F_1: + case FR500_MAJOR_F_2: + /* Cannot coexist with F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_3: + /* Cannot coexist with F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_5: + /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_6: + /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_7: + /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_1: + /* Cannot coexist with M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_2: + case FR500_MAJOR_M_3: + /* Cannot coexist with M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_4: + /* Cannot coexist with M-6 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6); + case FR500_MAJOR_M_5: + /* Cannot coexist with M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_6: + /* Cannot coexist with M-2, M-3, M-4, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_4) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_7: + /* Cannot coexist with M-1, M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7); + default: + fprintf (stderr, "frv-opc.c, line %d: bad major code, aborting.\n", + __LINE__); + abort (); + break; + } + return TRUE; +} + +static bfd_boolean +check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_ENUM_TYPE major, + const CGEN_INSN *insn) +{ + switch (vliw->mach) + { + case bfd_mach_fr400: + return fr400_check_insn_major_constraints (vliw, major); + + case bfd_mach_fr450: + return fr450_check_insn_major_constraints (vliw, major); + + case bfd_mach_fr550: + return fr550_check_insn_major_constraints (vliw, major, insn); + + default: + return fr500_check_insn_major_constraints (vliw, major); + } +} + +/* Add in insn to the VLIW vliw if possible. + Return 0 if successful, non-zero otherwise. */ + +int +frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) +{ + int slot_index; + CGEN_ATTR_VALUE_ENUM_TYPE major; + CGEN_ATTR_VALUE_ENUM_TYPE unit; + VLIW_COMBO *new_vliw; + + if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) + return 1; + + slot_index = vliw->next_slot; + if (slot_index >= FRV_VLIW_SIZE) + return 1; + + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_NIL) + { + fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n", + __LINE__); + abort (); /* No UNIT specified for this insn in frv.cpu. */ + } + + switch (vliw->mach) + { + case bfd_mach_fr400: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); + break; + case bfd_mach_fr450: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR); + break; + case bfd_mach_fr550: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR); + break; + default: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + break; + } + + if (slot_index <= 0) + { + /* Any insn can be added to slot 0. */ + while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) + ++vliw->current_vliw; + vliw->major[0] = major; + vliw->insn[0] = insn; + vliw->next_slot = 1; + return 0; + } + + /* If there are already insns in the vliw(s) check to see that + this one can be added. Do this by finding an allowable vliw + combination that can accept the new insn. */ + if (! (vliw->elf_flags & EF_FRV_NOPACK)) + { + new_vliw = add_next_to_vliw (vliw, unit); + if (new_vliw && check_insn_major_constraints (vliw, major, insn)) + { + vliw->current_vliw = new_vliw; + vliw->major[slot_index] = major; + vliw->insn[slot_index] = insn; + vliw->next_slot++; + return 0; + } + + /* The frv machine supports all packing conbinations. If we fail, + to add the insn, then it could not be handled as if it was the fr500. + Just return as if it was handled ok. */ + if (vliw->mach == bfd_mach_frv) + return 0; + } + + vliw->constraint_violation = 1; + return 1; +} + +bfd_boolean +spr_valid (long regno) +{ + if (regno < 0) return FALSE; + if (regno <= 4095) return TRUE; + return FALSE; +} +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & frv_cgen_ifld_table[FRV_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smul ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smu ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slass ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_scutss ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cadd ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cnot ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_csmul ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addcc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulcc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smuli ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addicc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulicc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpb ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlo ATTRIBUTE_UNUSED = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sethi ATTRIBUTE_UNUSED = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlos ATTRIBUTE_UNUSED = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbf ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldd ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddf ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldsbi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbfi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddfi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cldbf ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clddf ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgf ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovgf ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_OP) }, { F (F_SPR) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bno ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbra ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbno ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbne ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bctrlr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bralr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnolr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqlr ATTRIBUTE_UNUSED = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbralr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbnolr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbeqlr ATTRIBUTE_UNUSED = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcralr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bceqlr ATTRIBUTE_UNUSED = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbralr ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbeqlr ATTRIBUTE_UNUSED = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpl ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_calll ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpil ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callil ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_OP) }, { F (F_LABEL24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rett ATTRIBUTE_UNUSED = { + 32, 32, 0x7dffffff, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_DEBUG) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rei ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_EIR) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tra ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tno ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_teq ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftra ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftno ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftne ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tira ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tino ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tieq ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftira ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftino ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftine ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andcr ATTRIBUTE_UNUSED = { + 32, 32, 0x71ff8ff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_MISC_NULL_7) }, { F (F_CRI) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_notcr ATTRIBUTE_UNUSED = { + 32, 32, 0x71fffff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckra ATTRIBUTE_UNUSED = { + 32, 32, 0x79ffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckeq ATTRIBUTE_UNUSED = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fckra ATTRIBUTE_UNUSED = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckra ATTRIBUTE_UNUSED = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckeq ATTRIBUTE_UNUSED = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckra ATTRIBUTE_UNUSED = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckne ATTRIBUTE_UNUSED = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cjmpl ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccalll ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icei ATTRIBUTE_UNUSED = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_AE) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icpl ATTRIBUTE_UNUSED = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LOCK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icul ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bar ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lrai ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc7, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_LRAE) }, { F (F_LRAD) }, { F (F_LRAS) }, { F (F_LRA_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tlbpr ATTRIBUTE_UNUSED = { + 32, 32, 0x61fc0fc0, { { F (F_PACK) }, { F (F_TLBPR_NULL) }, { F (F_TLBPROPX) }, { F (F_TLBPRL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cop1 ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrgr ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrfr ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitos ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fstoi ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitod ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fdtoi ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfitos ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfstoi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovs ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovd ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfmovs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fadds ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_faddd ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfadds ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmps ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmpd ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfcmps ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc00c0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetlos ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethis ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdsets ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetloh ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethih ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdseth ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mand ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmand ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnot ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmnot ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrotli ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcut ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcuti ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mdcutssi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mdrotli ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mqsaths ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcmpsh ATTRIBUTE_UNUSED = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mabshs ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqaddhss ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mqsllhi ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_maddaccs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmulhs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmulhs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mqmulhs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmulhs ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmachu ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmachu ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mqmachu ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmachu ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhw ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mexpdhd ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhd ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_munpackh ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mdunpackh ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mbtoh ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtoh ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhtob ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmhtob ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtohe ATTRIBUTE_UNUSED = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnop ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mclracc_0 ATTRIBUTE_UNUSED = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdacc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdaccg ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACCGI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtacc ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtaccg ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACCGK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fnop ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) FRV_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x0 } + }, +/* sub$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x100 } + }, +/* and$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40000 } + }, +/* or$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40080 } + }, +/* xor$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40100 } + }, +/* not$pack $GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_not, { 0x40180 } + }, +/* sdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x380 } + }, +/* nsdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40380 } + }, +/* udiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x3c0 } + }, +/* nudiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x403c0 } + }, +/* smul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x200 } + }, +/* umul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x280 } + }, +/* smu$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_smu, { 0x1180140 } + }, +/* smass$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_smu, { 0x1180180 } + }, +/* smsss$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_smu, { 0x11801c0 } + }, +/* sll$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40200 } + }, +/* srl$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40280 } + }, +/* sra$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40300 } + }, +/* slass$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x1180080 } + }, +/* scutss$pack $GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_scutss, { 0x1180100 } + }, +/* scan$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x2c0000 } + }, +/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600000 } + }, +/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600040 } + }, +/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680000 } + }, +/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680040 } + }, +/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680080 } + }, +/* cnot$pack $GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cnot, { 0x16800c0 } + }, +/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1600080 } + }, +/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16000c0 } + }, +/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16400c0 } + }, +/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700000 } + }, +/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700040 } + }, +/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700080 } + }, +/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19400c0 } + }, +/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40 } + }, +/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x140 } + }, +/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40040 } + }, +/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x400c0 } + }, +/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40140 } + }, +/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40240 } + }, +/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x402c0 } + }, +/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40340 } + }, +/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x240 } + }, +/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x2c0 } + }, +/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640000 } + }, +/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640040 } + }, +/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1640080 } + }, +/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0000 } + }, +/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0040 } + }, +/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0080 } + }, +/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740000 } + }, +/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740040 } + }, +/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740080 } + }, +/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x80 } + }, +/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x180 } + }, +/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0xc0 } + }, +/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x1c0 } + }, +/* addss$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x1180000 } + }, +/* subss$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x1180040 } + }, +/* addi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x400000 } + }, +/* subi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x500000 } + }, +/* andi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x800000 } + }, +/* ori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x880000 } + }, +/* xori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x900000 } + }, +/* sdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x780000 } + }, +/* nsdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb80000 } + }, +/* udivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x7c0000 } + }, +/* nudivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xbc0000 } + }, +/* smuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x600000 } + }, +/* umuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x680000 } + }, +/* slli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa00000 } + }, +/* srli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa80000 } + }, +/* srai$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb00000 } + }, +/* scani$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x11c0000 } + }, +/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x440000 } + }, +/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x540000 } + }, +/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x840000 } + }, +/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x8c0000 } + }, +/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x940000 } + }, +/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x640000 } + }, +/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x6c0000 } + }, +/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xa40000 } + }, +/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xac0000 } + }, +/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xb40000 } + }, +/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x480000 } + }, +/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x580000 } + }, +/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x4c0000 } + }, +/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x5c0000 } + }, +/* cmpb$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x300 } + }, +/* cmpba$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x340 } + }, +/* setlo$pack $ulo16,$GRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ULO16), ',', OP (GRKLO), 0 } }, + & ifmt_setlo, { 0xf40000 } + }, +/* sethi$pack $uhi16,$GRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (UHI16), ',', OP (GRKHI), 0 } }, + & ifmt_sethi, { 0xf80000 } + }, +/* setlos$pack $slo16,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SLO16), ',', OP (GRK), 0 } }, + & ifmt_setlos, { 0xfc0000 } + }, +/* ldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80000 } + }, +/* ldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80040 } + }, +/* ldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80080 } + }, +/* lduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x800c0 } + }, +/* ld$pack $ldann($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (LDANN), '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80100 } + }, +/* ldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80200 } + }, +/* ldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80240 } + }, +/* ldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80280 } + }, +/* ldc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80340 } + }, +/* nldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80800 } + }, +/* nldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80840 } + }, +/* nldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80880 } + }, +/* nlduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x808c0 } + }, +/* nld$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80900 } + }, +/* nldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a00 } + }, +/* nldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a40 } + }, +/* nldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a80 } + }, +/* ldd$pack $lddann($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (LDDANN), '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80140 } + }, +/* lddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x802c0 } + }, +/* lddc$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80380 } + }, +/* nldd$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80940 } + }, +/* nlddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ac0 } + }, +/* ldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80180 } + }, +/* ldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80300 } + }, +/* ldqc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x803c0 } + }, +/* nldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80980 } + }, +/* nldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80b00 } + }, +/* ldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80400 } + }, +/* ldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80440 } + }, +/* ldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80480 } + }, +/* lduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x804c0 } + }, +/* ldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80500 } + }, +/* nldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80c00 } + }, +/* nldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80c40 } + }, +/* nldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80c80 } + }, +/* nlduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80cc0 } + }, +/* nldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80d00 } + }, +/* ldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80600 } + }, +/* ldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80640 } + }, +/* ldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80680 } + }, +/* ldcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80740 } + }, +/* nldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e00 } + }, +/* nldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e40 } + }, +/* nldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e80 } + }, +/* lddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80540 } + }, +/* nlddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80d40 } + }, +/* lddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x806c0 } + }, +/* lddcu$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80780 } + }, +/* nlddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ec0 } + }, +/* ldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80580 } + }, +/* nldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0x80d80 } + }, +/* ldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80700 } + }, +/* ldqcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x807c0 } + }, +/* nldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80f00 } + }, +/* ldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc00000 } + }, +/* ldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc40000 } + }, +/* ldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc80000 } + }, +/* ldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd40000 } + }, +/* lduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd80000 } + }, +/* ldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe00000 } + }, +/* ldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe40000 } + }, +/* ldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe80000 } + }, +/* nldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1000000 } + }, +/* nldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1040000 } + }, +/* nldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1080000 } + }, +/* nlduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x10c0000 } + }, +/* nldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1100000 } + }, +/* nldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1200000 } + }, +/* nldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1240000 } + }, +/* nldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1280000 } + }, +/* lddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0xcc0000 } + }, +/* lddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0xec0000 } + }, +/* nlddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0x1140000 } + }, +/* nlddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0x12c0000 } + }, +/* ldqi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd00000 } + }, +/* ldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xf00000 } + }, +/* nldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1300000 } + }, +/* stb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0000 } + }, +/* sth$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0040 } + }, +/* st$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0080 } + }, +/* stbf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0200 } + }, +/* sthf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0240 } + }, +/* stf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0280 } + }, +/* stc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0940 } + }, +/* std$pack $GRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldd, { 0xc00c0 } + }, +/* stdf$pack $FRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_lddf, { 0xc02c0 } + }, +/* stdc$pack $CPRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_lddc, { 0xc0980 } + }, +/* stq$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0100 } + }, +/* stqf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0300 } + }, +/* stqc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc09c0 } + }, +/* stbu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0400 } + }, +/* sthu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0440 } + }, +/* stu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0480 } + }, +/* stbfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0600 } + }, +/* sthfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0640 } + }, +/* stfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0680 } + }, +/* stcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0b40 } + }, +/* stdu$pack $GRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldd, { 0xc04c0 } + }, +/* stdfu$pack $FRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_lddf, { 0xc06c0 } + }, +/* stdcu$pack $CPRdoublek,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_lddc, { 0xc0b80 } + }, +/* stqu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0500 } + }, +/* stqfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0700 } + }, +/* stqcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0bc0 } + }, +/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780000 } + }, +/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780040 } + }, +/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780080 } + }, +/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17800c0 } + }, +/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0000 } + }, +/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800000 } + }, +/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800040 } + }, +/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800080 } + }, +/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x17c0040 } + }, +/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18000c0 } + }, +/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0080 } + }, +/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840000 } + }, +/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840040 } + }, +/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840080 } + }, +/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x18400c0 } + }, +/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880000 } + }, +/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0000 } + }, +/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0040 } + }, +/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0080 } + }, +/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1880040 } + }, +/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18c00c0 } + }, +/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880080 } + }, +/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900000 } + }, +/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900040 } + }, +/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900080 } + }, +/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980000 } + }, +/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980040 } + }, +/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980080 } + }, +/* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x19000c0 } + }, +/* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x19800c0 } + }, +/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940000 } + }, +/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0000 } + }, +/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0040 } + }, +/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0080 } + }, +/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00000 } + }, +/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00040 } + }, +/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00080 } + }, +/* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x19c00c0 } + }, +/* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x1a000c0 } + }, +/* stbi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1400000 } + }, +/* sthi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1440000 } + }, +/* sti$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1480000 } + }, +/* stbfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1380000 } + }, +/* sthfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x13c0000 } + }, +/* stfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1540000 } + }, +/* stdi$pack $GRdoublek,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_lddi, { 0x14c0000 } + }, +/* stdfi$pack $FRdoublek,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_lddfi, { 0x1580000 } + }, +/* stqi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1500000 } + }, +/* stqfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x15c0000 } + }, +/* swap$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_slass, { 0xc0140 } + }, +/* swapi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1340000 } + }, +/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940080 } + }, +/* movgf$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0540 } + }, +/* movfg$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0340 } + }, +/* movgfd$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0580 } + }, +/* movfgd$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0380 } + }, +/* movgfq$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc05c0 } + }, +/* movfgq$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc03c0 } + }, +/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40000 } + }, +/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40080 } + }, +/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40040 } + }, +/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a400c0 } + }, +/* movgs$pack $GRj,$spr */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (SPR), 0 } }, + & ifmt_movgs, { 0xc0180 } + }, +/* movsg$pack $spr,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SPR), ',', OP (GRJ), 0 } }, + & ifmt_movgs, { 0xc01c0 } + }, +/* bra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_bra, { 0x40180000 } + }, +/* bno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bno, { 0x180000 } + }, +/* beq$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x20180000 } + }, +/* bne$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x60180000 } + }, +/* ble$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x38180000 } + }, +/* bgt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x78180000 } + }, +/* blt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x18180000 } + }, +/* bge$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x58180000 } + }, +/* bls$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x28180000 } + }, +/* bhi$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x68180000 } + }, +/* bc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x8180000 } + }, +/* bnc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x48180000 } + }, +/* bn$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x30180000 } + }, +/* bp$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x70180000 } + }, +/* bv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x10180000 } + }, +/* bnv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x50180000 } + }, +/* fbra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_fbra, { 0x781c0000 } + }, +/* fbno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbno, { 0x1c0000 } + }, +/* fbne$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x381c0000 } + }, +/* fbeq$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x401c0000 } + }, +/* fblg$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x301c0000 } + }, +/* fbue$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x481c0000 } + }, +/* fbul$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x281c0000 } + }, +/* fbge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x501c0000 } + }, +/* fblt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x201c0000 } + }, +/* fbuge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x581c0000 } + }, +/* fbug$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x181c0000 } + }, +/* fble$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x601c0000 } + }, +/* fbgt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x101c0000 } + }, +/* fbule$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x681c0000 } + }, +/* fbu$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x81c0000 } + }, +/* fbo$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x701c0000 } + }, +/* bctrlr$pack $ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bctrlr, { 0x382000 } + }, +/* bralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_bralr, { 0x40384000 } + }, +/* bnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x384000 } + }, +/* beqlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x20384000 } + }, +/* bnelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x60384000 } + }, +/* blelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x38384000 } + }, +/* bgtlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x78384000 } + }, +/* bltlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x18384000 } + }, +/* bgelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x58384000 } + }, +/* blslr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x28384000 } + }, +/* bhilr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x68384000 } + }, +/* bclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x8384000 } + }, +/* bnclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x48384000 } + }, +/* bnlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x30384000 } + }, +/* bplr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x70384000 } + }, +/* bvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x10384000 } + }, +/* bnvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x50384000 } + }, +/* fbralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_fbralr, { 0x7838c000 } + }, +/* fbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38c000 } + }, +/* fbeqlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4038c000 } + }, +/* fbnelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3838c000 } + }, +/* fblglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3038c000 } + }, +/* fbuelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4838c000 } + }, +/* fbullr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2838c000 } + }, +/* fbgelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5038c000 } + }, +/* fbltlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2038c000 } + }, +/* fbugelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5838c000 } + }, +/* fbuglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1838c000 } + }, +/* fblelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6038c000 } + }, +/* fbgtlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1038c000 } + }, +/* fbulelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6838c000 } + }, +/* fbulr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x838c000 } + }, +/* fbolr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x7038c000 } + }, +/* bcralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_bcralr, { 0x40386000 } + }, +/* bcnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x386000 } + }, +/* bceqlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x20386000 } + }, +/* bcnelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x60386000 } + }, +/* bclelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x38386000 } + }, +/* bcgtlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x78386000 } + }, +/* bcltlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x18386000 } + }, +/* bcgelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x58386000 } + }, +/* bclslr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x28386000 } + }, +/* bchilr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x68386000 } + }, +/* bcclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x8386000 } + }, +/* bcnclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x48386000 } + }, +/* bcnlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x30386000 } + }, +/* bcplr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x70386000 } + }, +/* bcvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x10386000 } + }, +/* bcnvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x50386000 } + }, +/* fcbralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_fcbralr, { 0x7838e000 } + }, +/* fcbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38e000 } + }, +/* fcbeqlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4038e000 } + }, +/* fcbnelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3838e000 } + }, +/* fcblglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3038e000 } + }, +/* fcbuelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4838e000 } + }, +/* fcbullr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2838e000 } + }, +/* fcbgelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5038e000 } + }, +/* fcbltlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2038e000 } + }, +/* fcbugelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5838e000 } + }, +/* fcbuglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1838e000 } + }, +/* fcblelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6038e000 } + }, +/* fcbgtlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1038e000 } + }, +/* fcbulelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6838e000 } + }, +/* fcbulr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x838e000 } + }, +/* fcbolr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x7038e000 } + }, +/* jmpl$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_jmpl, { 0x300000 } + }, +/* calll$pack $callann($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CALLANN), '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_calll, { 0x2300000 } + }, +/* jmpil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_jmpil, { 0x340000 } + }, +/* callil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_callil, { 0x2340000 } + }, +/* call$pack $label24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (LABEL24), 0 } }, + & ifmt_call, { 0x3c0000 } + }, +/* rett$pack $debug */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (DEBUG), 0 } }, + & ifmt_rett, { 0x140000 } + }, +/* rei$pack $eir */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (EIR), 0 } }, + & ifmt_rei, { 0xdc0000 } + }, +/* tra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_tra, { 0x40100000 } + }, +/* tno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tno, { 0x100000 } + }, +/* teq$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x20100000 } + }, +/* tne$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x60100000 } + }, +/* tle$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x38100000 } + }, +/* tgt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x78100000 } + }, +/* tlt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x18100000 } + }, +/* tge$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x58100000 } + }, +/* tls$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x28100000 } + }, +/* thi$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x68100000 } + }, +/* tc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x8100000 } + }, +/* tnc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x48100000 } + }, +/* tn$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x30100000 } + }, +/* tp$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x70100000 } + }, +/* tv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x10100000 } + }, +/* tnv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x50100000 } + }, +/* ftra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftra, { 0x78100040 } + }, +/* ftno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftno, { 0x100040 } + }, +/* ftne$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x38100040 } + }, +/* fteq$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x40100040 } + }, +/* ftlg$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x30100040 } + }, +/* ftue$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x48100040 } + }, +/* ftul$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x28100040 } + }, +/* ftge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x50100040 } + }, +/* ftlt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x20100040 } + }, +/* ftuge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x58100040 } + }, +/* ftug$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x18100040 } + }, +/* ftle$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x60100040 } + }, +/* ftgt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x10100040 } + }, +/* ftule$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x68100040 } + }, +/* ftu$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x8100040 } + }, +/* fto$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x70100040 } + }, +/* tira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tira, { 0x40700000 } + }, +/* tino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tino, { 0x700000 } + }, +/* tieq$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x20700000 } + }, +/* tine$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x60700000 } + }, +/* tile$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x38700000 } + }, +/* tigt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x78700000 } + }, +/* tilt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x18700000 } + }, +/* tige$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x58700000 } + }, +/* tils$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x28700000 } + }, +/* tihi$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x68700000 } + }, +/* tic$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x8700000 } + }, +/* tinc$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x48700000 } + }, +/* tin$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x30700000 } + }, +/* tip$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x70700000 } + }, +/* tiv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x10700000 } + }, +/* tinv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x50700000 } + }, +/* ftira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftira, { 0x78740000 } + }, +/* ftino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftino, { 0x740000 } + }, +/* ftine$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x38740000 } + }, +/* ftieq$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x40740000 } + }, +/* ftilg$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x30740000 } + }, +/* ftiue$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x48740000 } + }, +/* ftiul$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x28740000 } + }, +/* ftige$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x50740000 } + }, +/* ftilt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x20740000 } + }, +/* ftiuge$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x58740000 } + }, +/* ftiug$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x18740000 } + }, +/* ftile$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x60740000 } + }, +/* ftigt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x10740000 } + }, +/* ftiule$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x68740000 } + }, +/* ftiu$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x8740000 } + }, +/* ftio$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x70740000 } + }, +/* break$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x1000c0 } + }, +/* mtrap$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x100080 } + }, +/* andcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280200 } + }, +/* orcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280240 } + }, +/* xorcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280280 } + }, +/* nandcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280300 } + }, +/* norcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280340 } + }, +/* andncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280400 } + }, +/* orncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280440 } + }, +/* nandncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280500 } + }, +/* norncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280540 } + }, +/* notcr$pack $CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_notcr, { 0x2802c0 } + }, +/* ckra$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x40200000 } + }, +/* ckno$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x200000 } + }, +/* ckeq$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x20200000 } + }, +/* ckne$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x60200000 } + }, +/* ckle$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x38200000 } + }, +/* ckgt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x78200000 } + }, +/* cklt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x18200000 } + }, +/* ckge$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x58200000 } + }, +/* ckls$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x28200000 } + }, +/* ckhi$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x68200000 } + }, +/* ckc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x8200000 } + }, +/* cknc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x48200000 } + }, +/* ckn$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x30200000 } + }, +/* ckp$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x70200000 } + }, +/* ckv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x10200000 } + }, +/* cknv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x50200000 } + }, +/* fckra$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x78240000 } + }, +/* fckno$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x240000 } + }, +/* fckne$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x38240000 } + }, +/* fckeq$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x40240000 } + }, +/* fcklg$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x30240000 } + }, +/* fckue$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x48240000 } + }, +/* fckul$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x28240000 } + }, +/* fckge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x50240000 } + }, +/* fcklt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x20240000 } + }, +/* fckuge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x58240000 } + }, +/* fckug$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x18240000 } + }, +/* fckle$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x60240000 } + }, +/* fckgt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x10240000 } + }, +/* fckule$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x68240000 } + }, +/* fcku$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x8240000 } + }, +/* fcko$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x70240000 } + }, +/* cckra$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x41a80000 } + }, +/* cckno$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x1a80000 } + }, +/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x21a80000 } + }, +/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x61a80000 } + }, +/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x39a80000 } + }, +/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x79a80000 } + }, +/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x19a80000 } + }, +/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x59a80000 } + }, +/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x29a80000 } + }, +/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x69a80000 } + }, +/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x9a80000 } + }, +/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x49a80000 } + }, +/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x31a80000 } + }, +/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x71a80000 } + }, +/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x11a80000 } + }, +/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x51a80000 } + }, +/* cfckra$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x79a80040 } + }, +/* cfckno$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x1a80040 } + }, +/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x39a80040 } + }, +/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x41a80040 } + }, +/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x31a80040 } + }, +/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x49a80040 } + }, +/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x29a80040 } + }, +/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x51a80040 } + }, +/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x21a80040 } + }, +/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x59a80040 } + }, +/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x19a80040 } + }, +/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x61a80040 } + }, +/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x11a80040 } + }, +/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x69a80040 } + }, +/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x9a80040 } + }, +/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x71a80040 } + }, +/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cjmpl, { 0x1a80080 } + }, +/* ccalll$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_ccalll, { 0x3a80080 } + }, +/* ici$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_smu, { 0xc0e00 } + }, +/* dci$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_smu, { 0xc0f00 } + }, +/* icei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e40 } + }, +/* dcei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e80 } + }, +/* dcf$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_smu, { 0xc0f40 } + }, +/* dcef$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0ec0 } + }, +/* witlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0c80 } + }, +/* wdtlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_slass, { 0xc0d80 } + }, +/* itlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_smu, { 0xc0cc0 } + }, +/* dtlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_smu, { 0xc0dc0 } + }, +/* icpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0c00 } + }, +/* dcpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0d00 } + }, +/* icul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0c40 } + }, +/* dcul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0d40 } + }, +/* bar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0f80 } + }, +/* membar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0fc0 } + }, +/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } }, + & ifmt_lrai, { 0xc0800 } + }, +/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } }, + & ifmt_lrai, { 0xc0840 } + }, +/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (TLBPROPX), ',', OP (TLBPRL), 0 } }, + & ifmt_tlbpr, { 0xc0900 } + }, +/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1f80000 } + }, +/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1fc0000 } + }, +/* clrgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280000 } + }, +/* clrfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280080 } + }, +/* clrga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280040 } + }, +/* clrfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2800c0 } + }, +/* commitgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280100 } + }, +/* commitfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280180 } + }, +/* commitga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280140 } + }, +/* commitfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2801c0 } + }, +/* fitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40000 } + }, +/* fstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40040 } + }, +/* fitod$pack $FRintj,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fitod, { 0x1e80000 } + }, +/* fdtoi$pack $FRdoublej,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRINTK), 0 } }, + & ifmt_fdtoi, { 0x1e80040 } + }, +/* fditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40400 } + }, +/* fdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40440 } + }, +/* nfditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40c00 } + }, +/* nfdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40c40 } + }, +/* cfitos$pack $FRintj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfitos, { 0x1ac0000 } + }, +/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfstoi, { 0x1ac0040 } + }, +/* nfitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40800 } + }, +/* nfstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40840 } + }, +/* fmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40080 } + }, +/* fmovd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80080 } + }, +/* fdmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40480 } + }, +/* cfmovs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00000 } + }, +/* fnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e400c0 } + }, +/* fnegd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e800c0 } + }, +/* fdnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e404c0 } + }, +/* cfnegs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00040 } + }, +/* fabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40100 } + }, +/* fabsd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80100 } + }, +/* fdabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40500 } + }, +/* cfabss$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00080 } + }, +/* fsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40140 } + }, +/* fdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40540 } + }, +/* nfdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40d40 } + }, +/* fsqrtd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80140 } + }, +/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b80080 } + }, +/* nfsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40940 } + }, +/* fadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40180 } + }, +/* fsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e401c0 } + }, +/* fmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40200 } + }, +/* fdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40240 } + }, +/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80180 } + }, +/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e801c0 } + }, +/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80200 } + }, +/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80240 } + }, +/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40000 } + }, +/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40040 } + }, +/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80000 } + }, +/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80040 } + }, +/* nfadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40980 } + }, +/* nfsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e409c0 } + }, +/* nfmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a00 } + }, +/* nfdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a40 } + }, +/* fcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40280 } + }, +/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmpd, { 0x1e80280 } + }, +/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfcmps, { 0x1b40080 } + }, +/* fdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40680 } + }, +/* fmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e402c0 } + }, +/* fmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40300 } + }, +/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e802c0 } + }, +/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80300 } + }, +/* fdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e406c0 } + }, +/* nfdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ec0 } + }, +/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0000 } + }, +/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0040 } + }, +/* nfmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ac0 } + }, +/* nfmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b00 } + }, +/* fmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40380 } + }, +/* fmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e403c0 } + }, +/* fdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40700 } + }, +/* fdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40740 } + }, +/* nfdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f00 } + }, +/* nfdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f40 } + }, +/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0080 } + }, +/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc00c0 } + }, +/* fmad$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e80380 } + }, +/* fmsd$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e803c0 } + }, +/* nfmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b80 } + }, +/* nfmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40bc0 } + }, +/* fdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40580 } + }, +/* fdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e405c0 } + }, +/* fdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40600 } + }, +/* fddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40640 } + }, +/* fdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40780 } + }, +/* fdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e407c0 } + }, +/* nfdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40fc0 } + }, +/* nfdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40d80 } + }, +/* nfdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40dc0 } + }, +/* nfdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e00 } + }, +/* nfddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e40 } + }, +/* nfdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f80 } + }, +/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40e80 } + }, +/* mhsetlos$pack $u12,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetlos, { 0x1e00800 } + }, +/* mhsethis$pack $u12,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethis, { 0x1e00880 } + }, +/* mhdsets$pack $u12,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRINTK), 0 } }, + & ifmt_mhdsets, { 0x1e00900 } + }, +/* mhsetloh$pack $s5,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetloh, { 0x1e00840 } + }, +/* mhsethih$pack $s5,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethih, { 0x1e008c0 } + }, +/* mhdseth$pack $s5,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRINTK), 0 } }, + & ifmt_mhdseth, { 0x1e00940 } + }, +/* mand$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0000 } + }, +/* mor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0040 } + }, +/* mxor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0080 } + }, +/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00000 } + }, +/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00040 } + }, +/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00080 } + }, +/* mnot$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mnot, { 0x1ec00c0 } + }, +/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmnot, { 0x1c000c0 } + }, +/* mrotli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0100 } + }, +/* mrotri$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0140 } + }, +/* mwcut$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0180 } + }, +/* mwcuti$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec01c0 } + }, +/* mcut$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b00 } + }, +/* mcuti$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0b80 } + }, +/* mcutss$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b40 } + }, +/* mcutssi$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0bc0 } + }, +/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mdcutssi, { 0x1e00380 } + }, +/* maveh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0200 } + }, +/* msllhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0240 } + }, +/* msrlhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0280 } + }, +/* msrahi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec02c0 } + }, +/* mdrotli$pack $FRintieven,$s6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mdrotli, { 0x1e002c0 } + }, +/* mcplhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00300 } + }, +/* mcpli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00340 } + }, +/* msaths$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0300 } + }, +/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e003c0 } + }, +/* msathu$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0340 } + }, +/* mcmpsh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec0380 } + }, +/* mcmpuh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec03c0 } + }, +/* mabshs$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1e00280 } + }, +/* maddhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0400 } + }, +/* maddhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0440 } + }, +/* msubhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0480 } + }, +/* msubhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec04c0 } + }, +/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40000 } + }, +/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40040 } + }, +/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40080 } + }, +/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c400c0 } + }, +/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0600 } + }, +/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0640 } + }, +/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0680 } + }, +/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec06c0 } + }, +/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0000 } + }, +/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0040 } + }, +/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0080 } + }, +/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc00c0 } + }, +/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e00400 } + }, +/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e00500 } + }, +/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsllhi, { 0x1e00440 } + }, +/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsllhi, { 0x1e004c0 } + }, +/* maddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00100 } + }, +/* msubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00140 } + }, +/* mdaddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00180 } + }, +/* mdsubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e001c0 } + }, +/* masaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00200 } + }, +/* mdasaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00240 } + }, +/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0500 } + }, +/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0540 } + }, +/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a00 } + }, +/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a40 } + }, +/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80000 } + }, +/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80040 } + }, +/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0700 } + }, +/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0740 } + }, +/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0a80 } + }, +/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0ac0 } + }, +/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00000 } + }, +/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00040 } + }, +/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0580 } + }, +/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec05c0 } + }, +/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0c00 } + }, +/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec0c40 } + }, +/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80080 } + }, +/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmachu, { 0x1c800c0 } + }, +/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0780 } + }, +/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), 0 } }, + & ifmt_mqmachu, { 0x1ec07c0 } + }, +/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00080 } + }, +/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmachu, { 0x1d000c0 } + }, +/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00000 } + }, +/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00040 } + }, +/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00080 } + }, +/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0800 } + }, +/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0840 } + }, +/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0880 } + }, +/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec08c0 } + }, +/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40000 } + }, +/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40040 } + }, +/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40080 } + }, +/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d400c0 } + }, +/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0900 } + }, +/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0940 } + }, +/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0980 } + }, +/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec09c0 } + }, +/* mexpdhw$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0c80 } + }, +/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhw, { 0x1d80080 } + }, +/* mexpdhd$pack $FRinti,$u6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mexpdhd, { 0x1ec0cc0 } + }, +/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhd, { 0x1d800c0 } + }, +/* mpackh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0d00 } + }, +/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0d80 } + }, +/* munpackh$pack $FRinti,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_munpackh, { 0x1ec0d40 } + }, +/* mdunpackh$pack $FRintieven,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mdunpackh, { 0x1ec0dc0 } + }, +/* mbtoh$pack $FRintj,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mbtoh, { 0x1ec0e00 } + }, +/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0000 } + }, +/* mhtob$pack $FRintjeven,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mhtob, { 0x1ec0e40 } + }, +/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmhtob, { 0x1dc0040 } + }, +/* mbtohe$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e80 } + }, +/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtohe, { 0x1dc0080 } + }, +/* mnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_mnop, { 0x7fee0ec0 } + }, +/* mclracc$pack $ACC40Sk,$A0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A0), 0 } }, + & ifmt_mclracc_0, { 0x1ec0ec0 } + }, +/* mclracc$pack $ACC40Sk,$A1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A1), 0 } }, + & ifmt_mclracc_0, { 0x1ee0ec0 } + }, +/* mrdacc$pack $ACC40Si,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdacc, { 0x1ec0f00 } + }, +/* mrdaccg$pack $ACCGi,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACCGI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdaccg, { 0x1ec0f80 } + }, +/* mwtacc$pack $FRinti,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACC40SK), 0 } }, + & ifmt_mwtacc, { 0x1ec0f40 } + }, +/* mwtaccg$pack $FRinti,$ACCGk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACCGK), 0 } }, + & ifmt_mwtaccg, { 0x1ec0fc0 } + }, +/* mcop1$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f00000 } + }, +/* mcop2$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f40000 } + }, +/* fnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_fnop, { 0x1e40340 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & frv_cgen_ifld_table[FRV_##f] +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccmp ATTRIBUTE_UNUSED = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov ATTRIBUTE_UNUSED = { + 32, 32, 0x1fc00ff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) FRV_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE frv_cgen_macro_insn_table[] = +{ +/* nop$pack */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + frv_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & frv_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + frv_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/frv-opc.h b/external/gpl3/gdb/dist/opcodes/frv-opc.h new file mode 100644 index 000000000000..5869d87c12e9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/frv-opc.h @@ -0,0 +1,387 @@ +/* Instruction opcode header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef FRV_OPC_H +#define FRV_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 128 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Vliw support. */ +#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ +#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL + +typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; + +typedef struct +{ + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping; + VLIW_COMBO * current_vliw; + CGEN_ATTR_VALUE_ENUM_TYPE major[FRV_VLIW_SIZE]; + const CGEN_INSN * insn[FRV_VLIW_SIZE]; +} FRV_VLIW; + +int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_branch_insn (const CGEN_INSN *); +int frv_is_float_insn (const CGEN_INSN *); +int frv_is_media_insn (const CGEN_INSN *); +void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); +int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); +int spr_valid (long); +/* -- */ +/* Enum declaration for frv instruction types. */ +typedef enum cgen_insn_type { + FRV_INSN_INVALID, FRV_INSN_ADD, FRV_INSN_SUB, FRV_INSN_AND + , FRV_INSN_OR, FRV_INSN_XOR, FRV_INSN_NOT, FRV_INSN_SDIV + , FRV_INSN_NSDIV, FRV_INSN_UDIV, FRV_INSN_NUDIV, FRV_INSN_SMUL + , FRV_INSN_UMUL, FRV_INSN_SMU, FRV_INSN_SMASS, FRV_INSN_SMSSS + , FRV_INSN_SLL, FRV_INSN_SRL, FRV_INSN_SRA, FRV_INSN_SLASS + , FRV_INSN_SCUTSS, FRV_INSN_SCAN, FRV_INSN_CADD, FRV_INSN_CSUB + , FRV_INSN_CAND, FRV_INSN_COR, FRV_INSN_CXOR, FRV_INSN_CNOT + , FRV_INSN_CSMUL, FRV_INSN_CSDIV, FRV_INSN_CUDIV, FRV_INSN_CSLL + , FRV_INSN_CSRL, FRV_INSN_CSRA, FRV_INSN_CSCAN, FRV_INSN_ADDCC + , FRV_INSN_SUBCC, FRV_INSN_ANDCC, FRV_INSN_ORCC, FRV_INSN_XORCC + , FRV_INSN_SLLCC, FRV_INSN_SRLCC, FRV_INSN_SRACC, FRV_INSN_SMULCC + , FRV_INSN_UMULCC, FRV_INSN_CADDCC, FRV_INSN_CSUBCC, FRV_INSN_CSMULCC + , FRV_INSN_CANDCC, FRV_INSN_CORCC, FRV_INSN_CXORCC, FRV_INSN_CSLLCC + , FRV_INSN_CSRLCC, FRV_INSN_CSRACC, FRV_INSN_ADDX, FRV_INSN_SUBX + , FRV_INSN_ADDXCC, FRV_INSN_SUBXCC, FRV_INSN_ADDSS, FRV_INSN_SUBSS + , FRV_INSN_ADDI, FRV_INSN_SUBI, FRV_INSN_ANDI, FRV_INSN_ORI + , FRV_INSN_XORI, FRV_INSN_SDIVI, FRV_INSN_NSDIVI, FRV_INSN_UDIVI + , FRV_INSN_NUDIVI, FRV_INSN_SMULI, FRV_INSN_UMULI, FRV_INSN_SLLI + , FRV_INSN_SRLI, FRV_INSN_SRAI, FRV_INSN_SCANI, FRV_INSN_ADDICC + , FRV_INSN_SUBICC, FRV_INSN_ANDICC, FRV_INSN_ORICC, FRV_INSN_XORICC + , FRV_INSN_SMULICC, FRV_INSN_UMULICC, FRV_INSN_SLLICC, FRV_INSN_SRLICC + , FRV_INSN_SRAICC, FRV_INSN_ADDXI, FRV_INSN_SUBXI, FRV_INSN_ADDXICC + , FRV_INSN_SUBXICC, FRV_INSN_CMPB, FRV_INSN_CMPBA, FRV_INSN_SETLO + , FRV_INSN_SETHI, FRV_INSN_SETLOS, FRV_INSN_LDSB, FRV_INSN_LDUB + , FRV_INSN_LDSH, FRV_INSN_LDUH, FRV_INSN_LD, FRV_INSN_LDBF + , FRV_INSN_LDHF, FRV_INSN_LDF, FRV_INSN_LDC, FRV_INSN_NLDSB + , FRV_INSN_NLDUB, FRV_INSN_NLDSH, FRV_INSN_NLDUH, FRV_INSN_NLD + , FRV_INSN_NLDBF, FRV_INSN_NLDHF, FRV_INSN_NLDF, FRV_INSN_LDD + , FRV_INSN_LDDF, FRV_INSN_LDDC, FRV_INSN_NLDD, FRV_INSN_NLDDF + , FRV_INSN_LDQ, FRV_INSN_LDQF, FRV_INSN_LDQC, FRV_INSN_NLDQ + , FRV_INSN_NLDQF, FRV_INSN_LDSBU, FRV_INSN_LDUBU, FRV_INSN_LDSHU + , FRV_INSN_LDUHU, FRV_INSN_LDU, FRV_INSN_NLDSBU, FRV_INSN_NLDUBU + , FRV_INSN_NLDSHU, FRV_INSN_NLDUHU, FRV_INSN_NLDU, FRV_INSN_LDBFU + , FRV_INSN_LDHFU, FRV_INSN_LDFU, FRV_INSN_LDCU, FRV_INSN_NLDBFU + , FRV_INSN_NLDHFU, FRV_INSN_NLDFU, FRV_INSN_LDDU, FRV_INSN_NLDDU + , FRV_INSN_LDDFU, FRV_INSN_LDDCU, FRV_INSN_NLDDFU, FRV_INSN_LDQU + , FRV_INSN_NLDQU, FRV_INSN_LDQFU, FRV_INSN_LDQCU, FRV_INSN_NLDQFU + , FRV_INSN_LDSBI, FRV_INSN_LDSHI, FRV_INSN_LDI, FRV_INSN_LDUBI + , FRV_INSN_LDUHI, FRV_INSN_LDBFI, FRV_INSN_LDHFI, FRV_INSN_LDFI + , FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI, FRV_INSN_NLDUHI + , FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI, FRV_INSN_NLDFI + , FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI, FRV_INSN_NLDDFI + , FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQFI, FRV_INSN_STB + , FRV_INSN_STH, FRV_INSN_ST, FRV_INSN_STBF, FRV_INSN_STHF + , FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_STD, FRV_INSN_STDF + , FRV_INSN_STDC, FRV_INSN_STQ, FRV_INSN_STQF, FRV_INSN_STQC + , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU + , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU + , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU + , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH + , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF + , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ + , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU + , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU + , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB + , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF + , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ + , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU + , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU + , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI + , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI + , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI + , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD + , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF + , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS + , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ + , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT + , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC + , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV + , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE + , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL + , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG + , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU + , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR + , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR + , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR + , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR + , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR + , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR + , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR + , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR + , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR + , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR + , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR + , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR + , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR + , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR + , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR + , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR + , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL + , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT + , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ + , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT + , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC + , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV + , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE + , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL + , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG + , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU + , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ + , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT + , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC + , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV + , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE + , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL + , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG + , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU + , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR + , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR + , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR + , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ + , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT + , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC + , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV + , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE + , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL + , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG + , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU + , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ + , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT + , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC + , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV + , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE + , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL + , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG + , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU + , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI + , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF + , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI + , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL + , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_LRAI + , FRV_INSN_LRAD, FRV_INSN_TLBPR, FRV_INSN_COP1, FRV_INSN_COP2 + , FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA + , FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA + , FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI + , FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI + , FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI + , FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS + , FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS + , FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS + , FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD + , FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS + , FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD + , FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS + , FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS + , FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD + , FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS + , FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS + , FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS + , FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS + , FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS + , FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS + , FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS + , FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS + , FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS + , FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS + , FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND + , FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR + , FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI + , FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT + , FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI + , FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI + , FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS + , FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH + , FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS + , FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS + , FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS + , FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS + , FRV_INSN_CMQSUBHUS, FRV_INSN_MQLCLRHS, FRV_INSN_MQLMTHS, FRV_INSN_MQSLLHI + , FRV_INSN_MQSRAHI, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS + , FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS + , FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS + , FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS + , FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS + , FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS + , FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS + , FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS + , FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU + , FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU + , FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU + , FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD + , FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH + , FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB + , FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0 + , FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC + , FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID FRV_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) FRV_INSN_FNOP + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_pack; + long f_op; + long f_ope1; + long f_ope2; + long f_ope3; + long f_ope4; + long f_GRi; + long f_GRj; + long f_GRk; + long f_FRi; + long f_FRj; + long f_FRk; + long f_CPRi; + long f_CPRj; + long f_CPRk; + long f_ACCGi; + long f_ACCGk; + long f_ACC40Si; + long f_ACC40Ui; + long f_ACC40Sk; + long f_ACC40Uk; + long f_CRi; + long f_CRj; + long f_CRk; + long f_CCi; + long f_CRj_int; + long f_CRj_float; + long f_ICCi_1; + long f_ICCi_2; + long f_ICCi_3; + long f_FCCi_1; + long f_FCCi_2; + long f_FCCi_3; + long f_FCCk; + long f_eir; + long f_s10; + long f_s12; + long f_d12; + long f_u16; + long f_s16; + long f_s6; + long f_s6_1; + long f_u6; + long f_s5; + long f_u12_h; + long f_u12_l; + long f_u12; + long f_int_cc; + long f_flt_cc; + long f_cond; + long f_ccond; + long f_hint; + long f_LI; + long f_lock; + long f_debug; + long f_A; + long f_ae; + long f_spr_h; + long f_spr_l; + long f_spr; + long f_label16; + long f_labelH6; + long f_labelL18; + long f_label24; + long f_LRAE; + long f_LRAD; + long f_LRAS; + long f_TLBPRopx; + long f_TLBPRL; + long f_ICCi_1_null; + long f_ICCi_2_null; + long f_ICCi_3_null; + long f_FCCi_1_null; + long f_FCCi_2_null; + long f_FCCi_3_null; + long f_rs_null; + long f_GRi_null; + long f_GRj_null; + long f_GRk_null; + long f_FRi_null; + long f_FRj_null; + long f_ACCj_null; + long f_rd_null; + long f_cond_null; + long f_ccond_null; + long f_s12_null; + long f_label16_null; + long f_misc_null_1; + long f_misc_null_2; + long f_misc_null_3; + long f_misc_null_4; + long f_misc_null_5; + long f_misc_null_6; + long f_misc_null_7; + long f_misc_null_8; + long f_misc_null_9; + long f_misc_null_10; + long f_misc_null_11; + long f_LRA_null; + long f_TLBPR_null; + long f_LI_off; + long f_LI_on; + long f_reloc_ann; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* FRV_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/h8300-dis.c b/external/gpl3/gdb/dist/opcodes/h8300-dis.c new file mode 100644 index 000000000000..0d260de68e0c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/h8300-dis.c @@ -0,0 +1,727 @@ +/* Disassemble h8300 instructions. + Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2006, + 2007, 2010 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define DEFINE_TABLE + +#include "sysdep.h" +#define h8_opcodes h8ops +#include "opcode/h8300.h" +#include "dis-asm.h" +#include "opintl.h" +#include "libiberty.h" + +struct h8_instruction +{ + int length; + const struct h8_opcode *opcode; +}; + +struct h8_instruction *h8_instructions; + +/* Run through the opcodes and sort them into order to make them easy + to disassemble. */ + +static void +bfd_h8_disassemble_init (void) +{ + unsigned int i; + unsigned int nopcodes; + const struct h8_opcode *p; + struct h8_instruction *pi; + + nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); + + h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction)); + + for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++) + { + /* Just make sure there are an even number of nibbles in it, and + that the count is the same as the length. */ + for (i = 0; p->data.nib[i] != (op_type) E; i++) + ; + + if (i & 1) + { + fprintf (stderr, "Internal error, h8_disassemble_init.\n"); + abort (); + } + + pi->length = i / 2; + pi->opcode = p; + } + + /* Add entry for the NULL vector terminator. */ + pi->length = 0; + pi->opcode = p; +} + +static void +extract_immediate (FILE *stream, + op_type looking_for, + int thisnib, + unsigned char *data, + int *cst, + int *len, + const struct h8_opcode *q) +{ + switch (looking_for & SIZE) + { + case L_2: + *len = 2; + *cst = thisnib & 3; + + /* DISP2 special treatment. */ + if ((looking_for & MODE) == DISP) + { + if (OP_KIND (q->how) == O_MOVAB + || OP_KIND (q->how) == O_MOVAW + || OP_KIND (q->how) == O_MOVAL) + { + /* Handling for mova insn. */ + switch (q->args.nib[0] & MODE) + { + case INDEXB: + default: + break; + case INDEXW: + *cst *= 2; + break; + case INDEXL: + *cst *= 4; + break; + } + } + else + { + /* Handling for non-mova insn. */ + switch (OP_SIZE (q->how)) + { + default: break; + case SW: + *cst *= 2; + break; + case SL: + *cst *= 4; + break; + } + } + } + break; + case L_8: + *len = 8; + *cst = data[0]; + break; + case L_16: + case L_16U: + *len = 16; + *cst = (data[0] << 8) + data [1]; +#if 0 + if ((looking_for & SIZE) == L_16) + *cst = (short) *cst; /* Sign extend. */ +#endif + break; + case L_32: + *len = 32; + *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3]; + break; + default: + *len = 0; + *cst = 0; + fprintf (stream, "DISP bad size\n"); + break; + } +} + +static const char *regnames[] = +{ + "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", + "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l" +}; +static const char *wregnames[] = +{ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" +}; +static const char *lregnames[] = +{ + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", + "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" +}; +static const char *cregnames[] = +{ + "ccr", "exr", "mach", "macl", "", "", "vbr", "sbr" +}; + +static void +print_one_arg (disassemble_info *info, + bfd_vma addr, + op_type x, + int cst, + int cstlen, + int rdisp_n, + int rn, + const char **pregnames, + int len) +{ + void * stream = info->stream; + fprintf_ftype outfn = info->fprintf_func; + + if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ) + outfn (stream, "#0x%x", (unsigned) cst); + else if ((x & MODE) == IMM) + outfn (stream, "#0x%x", (unsigned) cst); + else if ((x & MODE) == DBIT || (x & MODE) == KBIT) + outfn (stream, "#%d", (unsigned) cst); + else if ((x & MODE) == CONST_2) + outfn (stream, "#2"); + else if ((x & MODE) == CONST_4) + outfn (stream, "#4"); + else if ((x & MODE) == CONST_8) + outfn (stream, "#8"); + else if ((x & MODE) == CONST_16) + outfn (stream, "#16"); + else if ((x & MODE) == REG) + { + switch (x & SIZE) + { + case L_8: + outfn (stream, "%s", regnames[rn]); + break; + case L_16: + case L_16U: + outfn (stream, "%s", wregnames[rn]); + break; + case L_P: + case L_32: + outfn (stream, "%s", lregnames[rn]); + break; + } + } + else if ((x & MODE) == LOWREG) + { + switch (x & SIZE) + { + case L_8: + /* Always take low half of reg. */ + outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]); + break; + case L_16: + case L_16U: + /* Always take low half of reg. */ + outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn - 8]); + break; + case L_P: + case L_32: + outfn (stream, "%s.l", lregnames[rn]); + break; + } + } + else if ((x & MODE) == POSTINC) + outfn (stream, "@%s+", pregnames[rn]); + + else if ((x & MODE) == POSTDEC) + outfn (stream, "@%s-", pregnames[rn]); + + else if ((x & MODE) == PREINC) + outfn (stream, "@+%s", pregnames[rn]); + + else if ((x & MODE) == PREDEC) + outfn (stream, "@-%s", pregnames[rn]); + + else if ((x & MODE) == IND) + outfn (stream, "@%s", pregnames[rn]); + + else if ((x & MODE) == ABS || (x & ABSJMP)) + outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen); + + else if ((x & MODE) == MEMIND) + outfn (stream, "@@%d (0x%x)", cst, cst); + + else if ((x & MODE) == VECIND) + { + /* FIXME Multiplier should be 2 or 4, depending on processor mode, + by which is meant "normal" vs. "middle", "advanced", "maximum". */ + + int offset = (cst + 0x80) * 4; + outfn (stream, "@@%d (0x%x)", offset, offset); + } + else if ((x & MODE) == PCREL) + { + if ((x & SIZE) == L_16 || + (x & SIZE) == L_16U) + { + outfn (stream, ".%s%d (0x%lx)", + (short) cst > 0 ? "+" : "", + (short) cst, + (long)(addr + (short) cst + len)); + } + else + { + outfn (stream, ".%s%d (0x%lx)", + (char) cst > 0 ? "+" : "", + (char) cst, + (long)(addr + (char) cst + len)); + } + } + else if ((x & MODE) == DISP) + outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]); + + else if ((x & MODE) == INDEXB) + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, + regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]); + + else if ((x & MODE) == INDEXW) + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, + wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]); + + else if ((x & MODE) == INDEXL) + outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]); + + else if (x & CTRL) + outfn (stream, cregnames[rn]); + + else if ((x & MODE) == CCR) + outfn (stream, "ccr"); + + else if ((x & MODE) == EXR) + outfn (stream, "exr"); + + else if ((x & MODE) == MACREG) + outfn (stream, "mac%c", cst ? 'l' : 'h'); + + else + /* xgettext:c-format */ + outfn (stream, _("Hmmmm 0x%x"), x); +} + +static unsigned int +bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach) +{ + /* Find the first entry in the table for this opcode. */ + int regno[3] = { 0, 0, 0 }; + int dispregno[3] = { 0, 0, 0 }; + int cst[3] = { 0, 0, 0 }; + int cstlen[3] = { 0, 0, 0 }; + static bfd_boolean init = 0; + const struct h8_instruction *qi; + char const **pregnames = mach != 0 ? lregnames : wregnames; + int status; + unsigned int l; + unsigned char data[MAX_CODE_NIBBLES]; + void *stream = info->stream; + fprintf_ftype outfn = info->fprintf_func; + + if (!init) + { + bfd_h8_disassemble_init (); + init = 1; + } + + status = info->read_memory_func (addr, data, 2, info); + if (status != 0) + { + info->memory_error_func (status, addr, info); + return -1; + } + + for (l = 2; status == 0 && l < sizeof (data) / 2; l += 2) + status = info->read_memory_func (addr + l, data + l, 2, info); + + /* Find the exact opcode/arg combo. */ + for (qi = h8_instructions; qi->opcode->name; qi++) + { + const struct h8_opcode *q = qi->opcode; + const op_type *nib = q->data.nib; + unsigned int len = 0; + + while (1) + { + op_type looking_for = *nib; + int thisnib = data[len / 2]; + int opnr; + + thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib / 16) & 0xf); + opnr = ((looking_for & OP3) == OP3 ? 2 + : (looking_for & DST) == DST ? 1 : 0); + + if (looking_for < 16 && looking_for >= 0) + { + if (looking_for != thisnib) + goto fail; + } + else + { + if ((int) looking_for & (int) B31) + { + if (!((thisnib & 0x8) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B31); + thisnib &= 0x7; + } + else if ((int) looking_for & (int) B30) + { + if (!((thisnib & 0x8) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B30); + } + + if ((int) looking_for & (int) B21) + { + if (!((thisnib & 0x4) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B21); + thisnib &= 0xb; + } + else if ((int) looking_for & (int) B20) + { + if (!((thisnib & 0x4) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B20); + } + if ((int) looking_for & (int) B11) + { + if (!((thisnib & 0x2) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B11); + thisnib &= 0xd; + } + else if ((int) looking_for & (int) B10) + { + if (!((thisnib & 0x2) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B10); + } + + if ((int) looking_for & (int) B01) + { + if (!((thisnib & 0x1) != 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B01); + thisnib &= 0xe; + } + else if ((int) looking_for & (int) B00) + { + if (!((thisnib & 0x1) == 0)) + goto fail; + + looking_for = (op_type) ((int) looking_for & ~(int) B00); + } + + if (looking_for & IGNORE) + { + /* Hitachi has declared that IGNORE must be zero. */ + if (thisnib != 0) + goto fail; + } + else if ((looking_for & MODE) == DATA) + { + ; /* Skip embedded data. */ + } + else if ((looking_for & MODE) == DBIT) + { + /* Exclude adds/subs by looking at bit 0 and 2, and + make sure the operand size, either w or l, + matches by looking at bit 1. */ + if ((looking_for & 7) != (thisnib & 7)) + goto fail; + + cst[opnr] = (thisnib & 0x8) ? 2 : 1; + } + else if ((looking_for & MODE) == DISP + || (looking_for & MODE) == ABS + || (looking_for & MODE) == PCREL + || (looking_for & MODE) == INDEXB + || (looking_for & MODE) == INDEXW + || (looking_for & MODE) == INDEXL) + { + extract_immediate (stream, looking_for, thisnib, + data + len / 2, cst + opnr, + cstlen + opnr, q); + /* Even address == bra, odd == bra/s. */ + if (q->how == O (O_BRAS, SB)) + cst[opnr] -= 1; + } + else if ((looking_for & MODE) == REG + || (looking_for & MODE) == LOWREG + || (looking_for & MODE) == IND + || (looking_for & MODE) == PREINC + || (looking_for & MODE) == POSTINC + || (looking_for & MODE) == PREDEC + || (looking_for & MODE) == POSTDEC) + { + regno[opnr] = thisnib; + } + else if (looking_for & CTRL) /* Control Register. */ + { + thisnib &= 7; + if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) + || ((looking_for & MODE) == EXR && (thisnib != C_EXR)) + || ((looking_for & MODE) == MACH && (thisnib != C_MACH)) + || ((looking_for & MODE) == MACL && (thisnib != C_MACL)) + || ((looking_for & MODE) == VBR && (thisnib != C_VBR)) + || ((looking_for & MODE) == SBR && (thisnib != C_SBR))) + goto fail; + if (((looking_for & MODE) == CCR_EXR + && (thisnib != C_CCR && thisnib != C_EXR)) + || ((looking_for & MODE) == VBR_SBR + && (thisnib != C_VBR && thisnib != C_SBR)) + || ((looking_for & MODE) == MACREG + && (thisnib != C_MACH && thisnib != C_MACL))) + goto fail; + if (((looking_for & MODE) == CC_EX_VB_SB + && (thisnib != C_CCR && thisnib != C_EXR + && thisnib != C_VBR && thisnib != C_SBR))) + goto fail; + + regno[opnr] = thisnib; + } + else if ((looking_for & SIZE) == L_5) + { + cst[opnr] = data[len / 2] & 31; + cstlen[opnr] = 5; + } + else if ((looking_for & SIZE) == L_4) + { + cst[opnr] = thisnib; + cstlen[opnr] = 4; + } + else if ((looking_for & SIZE) == L_16 + || (looking_for & SIZE) == L_16U) + { + cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2]; + cstlen[opnr] = 16; + } + else if ((looking_for & MODE) == MEMIND) + { + cst[opnr] = data[1]; + } + else if ((looking_for & MODE) == VECIND) + { + cst[opnr] = data[1] & 0x7f; + } + else if ((looking_for & SIZE) == L_32) + { + int i = len / 2; + + cst[opnr] = ((data[i] << 24) + | (data[i + 1] << 16) + | (data[i + 2] << 8) + | (data[i + 3])); + + cstlen[opnr] = 32; + } + else if ((looking_for & SIZE) == L_24) + { + int i = len / 2; + + cst[opnr] = + (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); + cstlen[opnr] = 24; + } + else if (looking_for & IGNORE) + { + ; + } + else if (looking_for & DISPREG) + { + dispregno[opnr] = thisnib & 7; + } + else if ((looking_for & MODE) == KBIT) + { + switch (thisnib) + { + case 9: + cst[opnr] = 4; + break; + case 8: + cst[opnr] = 2; + break; + case 0: + cst[opnr] = 1; + break; + default: + goto fail; + } + } + else if ((looking_for & SIZE) == L_8) + { + cstlen[opnr] = 8; + cst[opnr] = data[len / 2]; + } + else if ((looking_for & SIZE) == L_3 + || (looking_for & SIZE) == L_3NZ) + { + cst[opnr] = thisnib & 0x7; + if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ) + goto fail; + } + else if ((looking_for & SIZE) == L_2) + { + cstlen[opnr] = 2; + cst[opnr] = thisnib & 0x3; + } + else if ((looking_for & MODE) == MACREG) + { + cst[opnr] = (thisnib == 3); + } + else if (looking_for == (op_type) E) + { + outfn (stream, "%s\t", q->name); + + /* Gross. Disgusting. */ + if (strcmp (q->name, "ldm.l") == 0) + { + int count, high; + + count = (data[1] / 16) & 0x3; + high = regno[1]; + + outfn (stream, "@sp+,er%d-er%d", high - count, high); + return qi->length; + } + + if (strcmp (q->name, "stm.l") == 0) + { + int count, low; + + count = (data[1] / 16) & 0x3; + low = regno[0]; + + outfn (stream, "er%d-er%d,@-sp", low, low + count); + return qi->length; + } + if (strcmp (q->name, "rte/l") == 0 + || strcmp (q->name, "rts/l") == 0) + { + if (regno[0] == 0) + outfn (stream, "er%d", regno[1]); + else + outfn (stream, "er%d-er%d", regno[1] - regno[0], + regno[1]); + return qi->length; + } + if (CONST_STRNEQ (q->name, "mova")) + { + const op_type *args = q->args.nib; + + if (args[1] == (op_type) E) + { + /* Short form. */ + print_one_arg (info, addr, args[0], cst[0], + cstlen[0], dispregno[0], regno[0], + pregnames, qi->length); + outfn (stream, ",er%d", dispregno[0]); + } + else + { + outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]); + print_one_arg (info, addr, args[1], cst[1], + cstlen[1], dispregno[1], regno[1], + pregnames, qi->length); + outfn (stream, ".%c),", + (args[0] & MODE) == INDEXB ? 'b' : 'w'); + print_one_arg (info, addr, args[2], cst[2], + cstlen[2], dispregno[2], regno[2], + pregnames, qi->length); + } + return qi->length; + } + /* Fill in the args. */ + { + const op_type *args = q->args.nib; + int hadone = 0; + int nargs; + + /* Special case handling for the adds and subs instructions + since in H8 mode thay can only take the r0-r7 registers + but in other (higher) modes they can take the er0-er7 + registers as well. */ + if (strcmp (qi->opcode->name, "adds") == 0 + || strcmp (qi->opcode->name, "subs") == 0) + { + outfn (stream, "#%d,%s", cst[0], pregnames[regno[1] & 0x7]); + return qi->length; + } + + for (nargs = 0; + nargs < 3 && args[nargs] != (op_type) E; + nargs++) + { + int x = args[nargs]; + + if (hadone) + outfn (stream, ","); + + print_one_arg (info, addr, x, + cst[nargs], cstlen[nargs], + dispregno[nargs], regno[nargs], + pregnames, qi->length); + + hadone = 1; + } + } + + return qi->length; + } + else + /* xgettext:c-format */ + outfn (stream, _("Don't understand 0x%x \n"), looking_for); + } + + len++; + nib++; + } + + fail: + ; + } + + /* Fell off the end. */ + outfn (stream, ".word\tH'%x,H'%x", data[0], data[1]); + return 2; +} + +int +print_insn_h8300 (bfd_vma addr, disassemble_info *info) +{ + return bfd_h8_disassemble (addr, info, 0); +} + +int +print_insn_h8300h (bfd_vma addr, disassemble_info *info) +{ + return bfd_h8_disassemble (addr, info, 1); +} + +int +print_insn_h8300s (bfd_vma addr, disassemble_info *info) +{ + return bfd_h8_disassemble (addr, info, 2); +} diff --git a/external/gpl3/gdb/dist/opcodes/h8500-dis.c b/external/gpl3/gdb/dist/opcodes/h8500-dis.c new file mode 100644 index 000000000000..1c9463afbccf --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/h8500-dis.c @@ -0,0 +1,326 @@ +/* Disassemble h8500 instructions. + Copyright 1993, 1998, 2000, 2001, 2002, 2004, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#define DISASSEMBLER_TABLE +#define DEFINE_TABLE + +#include "sysdep.h" +#include "h8500-opc.h" +#include "dis-asm.h" +#include "opintl.h" + +/* Maximum length of an instruction. */ +#define MAXLEN 8 + +#include + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + struct private *priv = (struct private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" }; + +int +print_insn_h8500 (bfd_vma addr, disassemble_info *info) +{ + const h8500_opcode_info *opcode; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + + info->private_data = (PTR) & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = addr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Run down the table to find the one which matches. */ + for (opcode = h8500_table; opcode->name; opcode++) + { + int byte; + int rn = 0; + int rd = 0; + int rs = 0; + int disp = 0; + int abs_val = 0; + int imm = 0; + int pcrel = 0; + int qim = 0; + int i; + int cr = 0; + + for (byte = 0; byte < opcode->length; byte++) + { + FETCH_DATA (info, buffer + byte + 1); + if ((buffer[byte] & opcode->bytes[byte].mask) + != (opcode->bytes[byte].contents)) + goto next; + + else + { + /* Extract any info parts. */ + switch (opcode->bytes[byte].insert) + { + case 0: + case FP: + break; + default: + /* xgettext:c-format */ + func (stream, _("can't cope with insert %d\n"), + opcode->bytes[byte].insert); + break; + case RN: + rn = buffer[byte] & 0x7; + break; + case RS: + rs = buffer[byte] & 0x7; + break; + case CRB: + cr = buffer[byte] & 0x7; + if (cr == 0) + goto next; + break; + case CRW: + cr = buffer[byte] & 0x7; + if (cr != 0) + goto next; + break; + case DISP16: + FETCH_DATA (info, buffer + byte + 2); + disp = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case FPIND_D8: + case DISP8: + disp = ((char) (buffer[byte])); + break; + case RD: + case RDIND: + rd = buffer[byte] & 0x7; + break; + case ABS24: + FETCH_DATA (info, buffer + byte + 3); + abs_val = + (buffer[byte] << 16) + | (buffer[byte + 1] << 8) + | (buffer[byte + 2]); + break; + case ABS16: + FETCH_DATA (info, buffer + byte + 2); + abs_val = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case ABS8: + abs_val = (buffer[byte]); + break; + case IMM16: + FETCH_DATA (info, buffer + byte + 2); + imm = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case IMM4: + imm = (buffer[byte]) & 0xf; + break; + case IMM8: + case RLIST: + imm = (buffer[byte]); + break; + case PCREL16: + FETCH_DATA (info, buffer + byte + 2); + pcrel = (buffer[byte] << 8) | (buffer[byte + 1]); + break; + case PCREL8: + pcrel = (buffer[byte]); + break; + case QIM: + switch (buffer[byte] & 0x7) + { + case 0: + qim = 1; + break; + case 1: + qim = 2; + break; + case 4: + qim = -1; + break; + case 5: + qim = -2; + break; + } + break; + + } + } + } + /* We get here when all the masks have passed so we can output + the operands. */ + FETCH_DATA (info, buffer + opcode->length); + (func) (stream, "%s\t", opcode->name); + for (i = 0; i < opcode->nargs; i++) + { + if (i) + (func) (stream, ","); + switch (opcode->arg_type[i]) + { + case FP: + func (stream, "fp"); + break; + case RNIND_D16: + func (stream, "@(0x%x:16,r%d)", disp, rn); + break; + case RNIND_D8: + func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn); + break; + case RDIND_D16: + func (stream, "@(0x%x:16,r%d)", disp, rd); + break; + case RDIND_D8: + func (stream, "@(0x%x:8 (%d), r%d)", disp & 0xff, disp, rd); + break; + case FPIND_D8: + func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp); + break; + case CRB: + case CRW: + func (stream, "%s", crname[cr]); + break; + case RN: + func (stream, "r%d", rn); + break; + case RD: + func (stream, "r%d", rd); + break; + case RS: + func (stream, "r%d", rs); + break; + case RNDEC: + func (stream, "@-r%d", rn); + break; + case RNINC: + func (stream, "@r%d+", rn); + break; + case RNIND: + func (stream, "@r%d", rn); + break; + case RDIND: + func (stream, "@r%d", rd); + break; + case SPINC: + func (stream, "@sp+"); + break; + case SPDEC: + func (stream, "@-sp"); + break; + case ABS24: + func (stream, "@0x%0x:24", abs_val); + break; + case ABS16: + func (stream, "@0x%0x:16", abs_val & 0xffff); + break; + case ABS8: + func (stream, "@0x%0x:8", abs_val & 0xff); + break; + case IMM16: + func (stream, "#0x%0x:16", imm & 0xffff); + break; + case RLIST: + { + int j; + int nc = 0; + + func (stream, "("); + for (j = 0; j < 8; j++) + { + if (imm & (1 << j)) + { + func (stream, "r%d", j); + if (nc) + func (stream, ","); + nc = 1; + } + } + func (stream, ")"); + } + break; + case IMM8: + func (stream, "#0x%0x:8", imm & 0xff); + break; + case PCREL16: + func (stream, "0x%0x:16", + (int)(pcrel + addr + opcode->length) & 0xffff); + break; + case PCREL8: + func (stream, "#0x%0x:8", + (int)((char) pcrel + addr + opcode->length) & 0xffff); + break; + case QIM: + func (stream, "#%d:q", qim); + break; + case IMM4: + func (stream, "#%d:4", imm); + break; + } + } + return opcode->length; + next: + ; + } + + /* Couldn't understand anything. */ + /* xgettext:c-format */ + func (stream, _("%02x\t\t*unknown*"), buffer[0]); + return 1; +} diff --git a/external/gpl3/gdb/dist/opcodes/h8500-opc.h b/external/gpl3/gdb/dist/opcodes/h8500-opc.h new file mode 100644 index 000000000000..7c343d1d1a9b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/h8500-opc.h @@ -0,0 +1,3858 @@ +/* Instruction opcode header for Renesas 8500. + + Copyright 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +typedef enum +{ + GR0,GR1,GR2,GR3,GR4,GR5,GR6,GR7, + GPR0, GPR1, GPR2, GPR3, GPR4, GPR5, GPR6, GPR7, + GCCR, GPC, + GSEGC, GSEGD, GSEGE, GSEGT,GLAST +} gdbreg_type; + +#define O_XORC 1 +#define O_XOR 2 +#define O_XCH 3 +#define O_UNLK 4 +#define O_TST 5 +#define O_TRAPA 6 +#define O_TRAP_VS 7 +#define O_TAS 8 +#define O_SWAP 9 +#define O_SUBX 10 +#define O_SUBS 11 +#define O_SUB 12 +#define O_STM 13 +#define O_STC 14 +#define O_SLEEP 15 +#define O_SHLR 16 +#define O_SHLL 17 +#define O_SHAR 18 +#define O_SHAL 19 +#define O_SCB_NE 20 +#define O_SCB_F 21 +#define O_SCB_EQ 22 +#define O_RTS 23 +#define O_RTD 24 +#define O_ROTXR 25 +#define O_ROTXL 26 +#define O_ROTR 27 +#define O_ROTL 28 +#define O_PRTS 29 +#define O_PRTD 30 +#define O_PJSR 31 +#define O_PJMP 32 +#define O_ORC 33 +#define O_OR 34 +#define O_NOT 35 +#define O_NOP 36 +#define O_NEG 37 +#define O_MULXU 38 +#define O_MOVTPE 39 +#define O_MOVFPE 40 +#define O_MOV 41 +#define O_LINK 42 +#define O_LDM 43 +#define O_LDC 44 +#define O_JSR 45 +#define O_JMP 46 +#define O_EXTU 47 +#define O_EXTS 48 +#define O_DSUB 49 +#define O_DIVXU 50 +#define O_DADD 51 +#define O_CMP 52 +#define O_CLR 53 +#define O_BVS 54 +#define O_BVC 55 +#define O_BTST 56 +#define O_BT 57 +#define O_BSR 58 +#define O_BSET 59 +#define O_BRN 60 +#define O_BRA 61 +#define O_BPT 62 +#define O_BPL 63 +#define O_BNOT 64 +#define O_BNE 65 +#define O_BMI 66 +#define O_BLT 67 +#define O_BLS 68 +#define O_BLO 69 +#define O_BLE 70 +#define O_BHS 71 +#define O_BHI 72 +#define O_BGT 73 +#define O_BGE 74 +#define O_BF 75 +#define O_BEQ 76 +#define O_BCS 77 +#define O_BCLR 78 +#define O_BCC 79 +#define O_ANDC 80 +#define O_AND 81 +#define O_ADDX 82 +#define O_ADDS 83 +#define O_ADD 84 +#define O_BYTE 128 +#define O_WORD 0x000 +#define O_UNSZ 0x000 +#define FPIND_D8 10 +#define RDIND_D16 11 +#define RDIND_D8 12 +#define SPDEC 13 +#define RDIND 14 +#define RN 15 +#define RNIND_D8 16 +#define RNIND_D16 17 +#define RNDEC 18 +#define RNINC 19 +#define RNIND 20 +#define SPINC 21 +#define ABS16 22 +#define ABS24 23 +#define PCREL16 24 +#define PCREL8 25 +#define ABS8 26 +#define CRB 27 +#define CR 28 +#define CRW 29 +#define DISP16 30 +#define DISP8 31 +#define FP 32 +#define IMM16 33 +#define IMM4 34 +#define IMM8 35 +#define RLIST 36 +#define QIM 37 +#define RD 38 +#define RS 39 +#define SP 40 +typedef enum { AC_BAD, AC_EI, AC_RI, AC_D, AC_,AC_ERR, AC_X,AC_B, AC_EE,AC_RR,AC_IE, + AC_RE,AC_E, AC_I, AC_ER,AC_IRR, AC_IR, AC_RER, AC_ERE,AC_EIE } addr_class_type; +typedef struct { + short int idx; + char flags,src1,src2,dst; + unsigned char flavor; + char *name; + int nargs; + int arg_type[2]; + int length; + struct { unsigned char contents;unsigned char mask; char insert; } bytes[6]; +} h8500_opcode_info; +const h8500_opcode_info h8500_table[] +#ifdef ASSEMBLER_TABLE +#ifdef DEFINE_TABLE +={ +/* +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS16},6, {{0x1d,0xff, }, + {0x00,0x00,ABS16 }, + {0x00,0x00, }, + {0x07,0xff, }, + {0x00,0x00,IMM16 },{0x00,0x00, }}},*/ + +{1,'s','E','C','C',O_XORC|O_WORD,"xorc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x68,0xf8,CRW }}}, +{2,'s','E','C','C',O_XORC|O_BYTE,"xorc.b",2,{IMM8,CRB},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x68,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}}, +{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{8,'-','B','!','!',O_UNLK|O_UNSZ,"unlk",1,{FP,0},1, {{0x0f,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS8,0},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{ABS16,0},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{IMM16,0},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{IMM8,0},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS8,0},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{ABS16,0},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS8,0},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{IMM16,0},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{ABS16,0},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}}, +{12,'-','I','!','!',O_TRAPA|O_UNSZ,"trapa",1,{IMM4,0},2, {{0x08,0xff,0 },{0x10,0xf0,IMM4 }}}, +{13,'-','B','!','!',O_TRAP_VS|O_UNSZ,"trap/vs",0,{0,0},1, {{0x09,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{ABS8,0},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{IMM8,0},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{ABS16,0},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x17,0xff,0 }}}, +{14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RN,0},2, {{0xa0,0xf8,RN },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{IMM8,0},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{ABS8,0},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{ABS16,0},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x17,0xff,0 }}}, +{15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x17,0xff,0 }}}, +{16,'m','D','!','D',O_SWAP|O_BYTE,"swap.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x10,0xff,0 }}}, +{17,'m','D','!','D',O_SWAP|O_UNSZ,"swap",1,{RD,0},2, {{0xa0,0xf8,RD },{0x10,0xff,0 }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}, +{18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}, +{19,'a','E','D','D',O_SUBX|O_BYTE,"subx.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}, 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{{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x14,0xff,0 }}}, +{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{IMM16,0},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x14,0xff,0 }}}, +{77,'a','E','!','E',O_NEG|O_UNSZ,"neg",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x14,0xff,0 }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{80,'p','E','D','D',O_MULXU|O_UNSZ,"mulxu",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{82,'-','S','!','E',O_MOVTPE|O_UNSZ,"movtpe",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x90,0xf8,RS }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{IMM8,RD},4, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS8,RD},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{ABS16,RD},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{84,'-','E','!','D',O_MOVFPE|O_UNSZ,"movfpe",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x00,0xff,0 },{0x80,0xf8,RD }}}, +{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{87,'m','S','!','E',O_MOV|O_UNSZ,"mov:s",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{90,'m','E','!','D',O_MOV|O_UNSZ,"mov:l",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{92,'m','I','!','D',O_MOV|O_UNSZ,"mov:i", 2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5,{{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, + +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND},3, {{0xd8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNDEC},3, {{0xb8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNINC},3, {{0xc8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D8},4, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS8},4, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','S','!','E',O_MOV|O_UNSZ,"mov:g",2,{RS,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{95,'m','E','!','D',O_MOV|O_UNSZ,"mov:g",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,ABS16},5, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM8,RNIND_D16},5, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{95,'m','I','!','E',O_MOV|O_UNSZ,"mov:g",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{98,'m','S','!','E',O_MOV|O_UNSZ,"mov:f",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{98,'m','E','!','D',O_MOV|O_UNSZ,"mov:f",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{100,'m','I','!','D',O_MOV|O_UNSZ,"mov:e",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{101,'m','I','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{101,'m','S','!','E',O_MOV|O_WORD,"mov.w",2,{RS,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{101,'m','E','!','D',O_MOV|O_WORD,"mov.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{101,'m','I','!','E',O_MOV|O_WORD,"mov.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, + +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{102,'m','I','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS8},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,ABS16},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{102,'m','S','!','E',O_MOV|O_BYTE,"mov.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{102,'m','E','!','D',O_MOV|O_BYTE,"mov.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{102,'m','I','!','E',O_MOV|O_BYTE,"mov.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +/*{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM8,RD},2, {{0x58,0xf8,RD },{0x00,0x00,IMM8 }}},*/ +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND},3, {{0xd8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNINC},3, {{0xc8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNDEC},3, {{0xb8,0xf8,RN },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{103,'m','I','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS8},4, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','S','!','E',O_MOV|O_UNSZ,"mov",2,{RS,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x90,0xf8,RS }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D8},4, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{103,'m','E','!','D',O_MOV|O_UNSZ,"mov",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x80,0xf8,RD }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,ABS16},5, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM8,RNIND_D16},5, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x06,0xff,0 },{0x00,0x00,IMM8 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{103,'m','I','!','E',O_MOV|O_UNSZ,"mov",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x07,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM8},2, {{0x17,0xff,0 },{0x00,0x00,IMM8 }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM16},3, {{0x1f,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{105,'-','E','!','C',O_LDM|O_UNSZ,"ldm",2,{SPINC,RLIST},2, {{0x02,0xff,0 },{0x00,0x00,RLIST }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RN,CRW},2, {{0xa8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND,CRW},2, {{0xd8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNINC,CRW},2, {{0xc8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNDEC,CRW},2, {{0xb8,0xf8,RN },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS8,CRW},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D8,CRW},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{ABS16,CRW},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x88,0xf8,CRW }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{RNIND_D16,CRW},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x88,0xf8,CRW }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRW},2, {{0xa8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRW},2, {{0xc8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRW},2, {{0xb8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNIND,CRW},2, {{0xd8,0xf8,RN },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRW},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x88,0xf8,CRW }}}, +{108,'s','E','!','C',O_LDC|O_UNSZ,"ldc",2,{ABS8,CRB},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, 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+{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{124,'a','D','E','!',O_CMP|O_UNSZ,"cmp:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{124,'a','E','I','!',O_CMP|O_UNSZ,"cmp:g",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{126,'a','D','I','!',O_CMP|O_UNSZ,"cmp:e",2,{IMM8,RD},2, {{0x48,0xf8,RD },{0x00,0x00,IMM8 }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{127,'a','D','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{127,'a','D','E','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,RNIND_D16},6,{{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{127,'a','E','I','!',O_CMP|O_WORD,"cmp.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','D','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS8},4, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','D','E','!',O_CMP|O_BYTE,"cmp.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,ABS16},5, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{128,'a','E','I','!',O_CMP|O_BYTE,"cmp.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x04,0xff,0 },{0x00,0x00,IMM8 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM8,RD},2, {{0x48,0xf8,RD },{0x00,0x00,IMM8 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{129,'a','D','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{129,'a','D','E','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x70,0xf8,RD }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS8},5, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,ABS16},6, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{129,'a','E','I','!',O_CMP|O_UNSZ,"cmp",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x05,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS8,0},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x13,0xff,0 }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{ABS16,0},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x13,0xff,0 }}}, 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}}}, +{201,'-','B','!','!',O_BCS|O_BYTE,"bcs.b",1,{PCREL8,0},2, {{0x25,0xff,0 },{0x00,0x00,PCREL8 }}}, +{202,'-','B','!','!',O_BCS|O_UNSZ,"bcs",1,{PCREL8,0},2, {{0x25,0xff,0 },{0x00,0x00,PCREL8 }}}, +{202,'-','B','!','!',O_BCS|O_UNSZ,"bcs",1,{PCREL16,0},3, {{0x35,0xff,0 },{0x00,0x00,PCREL16 },{0x00,0x00,0 }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,RN},2, {{0xa8,0xf8,RN },{0x58,0xf8,RS }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x58,0xf8,RS }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,RNDEC},2, {{0xb8,0xf8,RN },{0xd0,0xf0,IMM4 }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x58,0xf8,RS }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x58,0xf8,RS }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,RNINC},2, {{0xc8,0xf8,RN },{0xd0,0xf0,IMM4 }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,RN},2, {{0xa8,0xf8,RN },{0xd0,0xf0,IMM4 }}}, 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}}}, +{205,'b','E','S','E',O_BCLR|O_UNSZ,"bclr",2,{RS,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x58,0xf8,RS }}}, +{205,'b','E','I','E',O_BCLR|O_UNSZ,"bclr",2,{IMM4,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xd0,0xf0,IMM4 }}}, +{205,'b','E','I','E',O_BCLR|O_UNSZ,"bclr",2,{IMM4,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0xd0,0xf0,IMM4 }}}, +{205,'b','E','S','E',O_BCLR|O_UNSZ,"bclr",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x58,0xf8,RS }}}, +{205,'b','E','S','E',O_BCLR|O_UNSZ,"bclr",2,{RS,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x58,0xf8,RS }}}, +{205,'b','E','I','E',O_BCLR|O_UNSZ,"bclr",2,{IMM4,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xd0,0xf0,IMM4 }}}, +{206,'-','B','!','!',O_BCC|O_WORD,"bcc.w",1,{PCREL16,0},3, {{0x34,0xff,0 },{0x00,0x00,PCREL16 },{0x00,0x00,0 }}}, +{207,'-','B','!','!',O_BCC|O_BYTE,"bcc.b",1,{PCREL8,0},2, {{0x24,0xff,0 },{0x00,0x00,PCREL8 }}}, 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+{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{226,'a','E','D','D',O_ADD|O_UNSZ,"add:g",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RN},2, {{0xa8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND},2, {{0xd8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNDEC},2, {{0xb8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNINC},2, {{0xc8,0xf8,RN },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{227,'a','I','E','E',O_ADD|O_WORD,"add.w",2,{QIM,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{227,'a','E','D','D',O_ADD|O_WORD,"add.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RN},2, {{0xa0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNINC},2, {{0xc0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND},2, {{0xd0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNDEC},2, {{0xb0,0xf8,RN },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{IMM8,RD},3, {{0x04,0xff,0 },{0x00,0x00,IMM8 },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,ABS8},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{ABS8,RD},3, {{0x05,0xff,0 },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{228,'a','I','E','E',O_ADD|O_BYTE,"add.b",2,{QIM,ABS16},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{ABS16,RD},4, {{0x15,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{228,'a','E','D','D',O_ADD|O_BYTE,"add.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RN},2, {{0xa8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNDEC},2, {{0xb8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND},2, {{0xd8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNINC},2, {{0xc8,0xf8,RN },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS8},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS8,RD},3, {{0x0d,0xff,0 },{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{ABS16,RD},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{IMM16,RD},4, {{0x0c,0xff,0 },{0x00,0x00,IMM16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{229,'a','I','E','E',O_ADD|O_UNSZ,"add",2,{QIM,ABS16},4, {{0x1d,0xff,0 },{0x00,0x00,ABS16 },{0x00,0x00,0 },{0x08,0xf8,QIM }}}, +{229,'a','E','D','D',O_ADD|O_UNSZ,"add",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x20,0xf8,RD }}}, +{0,0,0,0,0,0,0,0,{0,0},0,{{0,0,0}}} +} +#endif +; +#endif +#ifdef DISASSEMBLER_TABLE +#ifdef DEFINE_TABLE +={ +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RN},2, {{0xa0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNDEC},2, {{0xb0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNINC},2, {{0xc0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x60,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND},2, {{0xd0,0xf8,RN },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x30,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x30,0xf8,RD }}}, +{4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x60,0xf8,RD }}}, +{29,'s','C','!','E',O_STC|O_BYTE,"stc.b",2,{CRB,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x98,0xf8,CRB }}}, +{3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x60,0xf8,RD }}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x30,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x16,0xff,0}}}, +{6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}}, +{9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x16,0xff,0}}}, +{25,'a','E','D','D',O_SUB|O_BYTE,"sub.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x30,0xf8,RD }}}, +{10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN 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{{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1e,0xff,0}}}, +{50,'h','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1f,0xff,0}}}, +{50,'h','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1f,0xff,0}}}, +{49,'h','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1f,0xff,0}}}, +{42,'h','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x18,0xff,0}}}, +{53,'h','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1e,0xff,0}}}, +{44,'-','B','S','S',O_SCB_NE|O_UNSZ,"scb/ne",2,{RS,PCREL8},3, {{0x06,0xff,0},{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, +{46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL8},3, {{0x07,0xff,0},{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1e,0xff,0}}}, +{49,'h','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1f,0xff,0}}}, +{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM16,0},3, {{0x14,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{48,'-','B','!','!',O_RTD|O_UNSZ,"rtd",1,{IMM8,0},2, {{0x14,0xff,0},{0x00,0x00,IMM8 }}}, +{42,'h','E','!','E',O_SHAL|O_BYTE,"shal.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{53,'h','E','!','E',O_ROTXL|O_BYTE,"rotxl.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{50,'h','E','!','E',O_ROTXR|O_BYTE,"rotxr.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1f,0xff,0}}}, +{47,'-','B','!','!',O_RTS|O_UNSZ,"rts",0,{0,0},1, {{0x19,0xff,0}}}, +{41,'h','E','!','E',O_SHAL|O_WORD,"shal.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x18,0xff,0}}}, +{52,'h','E','!','E',O_ROTXL|O_WORD,"rotxl.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1e,0xff,0}}}, +{49,'h','E','!','E',O_ROTXR|O_WORD,"rotxr.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1f,0xff,0}}}, +{99,'m','I','!','D',O_MOV|O_BYTE,"mov:e.b",2,{IMM8,RD},2, {{0x50,0xf8,RD },{0x00,0x00,IMM8 }}}, +{97,'m','E','!','D',O_MOV|O_BYTE,"mov:f.b",2,{FPIND_D8,RD},2, {{0x80,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{96,'m','E','!','D',O_MOV|O_WORD,"mov:f.w",2,{FPIND_D8,RD},2, {{0x88,0xf8,RD },{0x00,0x00,FPIND_D8 }}}, +{97,'m','S','!','E',O_MOV|O_BYTE,"mov:f.b",2,{RS,FPIND_D8},2, {{0x90,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{96,'m','S','!','E',O_MOV|O_WORD,"mov:f.w",2,{RS,FPIND_D8},2, {{0x98,0xf8,RS },{0x00,0x00,FPIND_D8 }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x80,0xf8,RD }}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1d,0xff,0}}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNDEC},2, {{0xb0,0xf8,RN },{0x90,0xf8,RS }}}, +{91,'m','I','!','D',O_MOV|O_WORD,"mov:i.w",2,{IMM16,RD},3, {{0x58,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{89,'m','E','!','D',O_MOV|O_BYTE,"mov:l.b",2,{ABS8,RD},2, {{0x60,0xf8,RD },{0x00,0x00,ABS8 }}}, +{88,'m','E','!','D',O_MOV|O_WORD,"mov:l.w",2,{ABS8,RD},2, {{0x68,0xf8,RD },{0x00,0x00,ABS8 }}}, +{86,'m','S','!','E',O_MOV|O_BYTE,"mov:s.b",2,{RS,ABS8},2, {{0x70,0xf8,RS },{0x00,0x00,ABS8 }}}, +{85,'m','S','!','E',O_MOV|O_WORD,"mov:s.w",2,{RS,ABS8},2, {{0x78,0xf8,RS },{0x00,0x00,ABS8 }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RN,RD},3, {{0xa0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNDEC,RD},3, {{0xb0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RN},3, {{0xa0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x1c,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x40,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xa8,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x40,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xa8,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RN,0},2, {{0xa8,0xf8,RN },{0x15,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x40,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNDEC},3, {{0xb0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1c,0xff,0}}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x14,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x40,0xf8,RD }}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1c,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x40,0xf8,RD }}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1d,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x40,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{ABS24,0},4, {{0x03,0xff,0},{0x00,0x00,ABS24 },{0x00,0x00,0},{0x00,0x00,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x40,0xf8,RD }}}, +{66,'s','I','C','C',O_ORC|O_BYTE,"orc.b",2,{IMM8,CRB},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x48,0xf8,CRB }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x14,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1c,0xff,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x15,0xff,0}}}, +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x14,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x15,0xff,0}}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{74,'-','!','!','!',O_NOP|O_UNSZ,"nop",0,{0,0},1, {{0x00,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{65,'s','I','C','C',O_ORC|O_WORD,"orc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x48,0xf8,CRW }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x40,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x14,0xff,0}}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x15,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1d,0xff,0}}}, +{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{RDIND,0},2, {{0x11,0xff,0},{0xc0,0xf8,RDIND }}}, +{63,'-','J','!','!',O_PJSR|O_UNSZ,"pjsr",1,{RDIND,0},2, {{0x11,0xff,0},{0xc8,0xf8,RDIND }}}, +{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM8,0},3, {{0x11,0xff,0},{0x14,0xff,0},{0x00,0x00,IMM8 }}}, +{61,'-','B','!','!',O_PRTS|O_UNSZ,"prts",0,{0,0},2, {{0x11,0xff,0},{0x19,0xff,0}}}, +{62,'-','B','!','!',O_PRTD|O_UNSZ,"prtd",1,{IMM16,0},4, {{0x11,0xff,0},{0x1c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{64,'-','J','!','!',O_PJMP|O_UNSZ,"pjmp",1,{ABS24,0},4, {{0x13,0xff,0},{0x00,0x00,ABS24 },{0x00,0x00,0},{0x00,0x00,0}}}, +{69,'m','E','D','D',O_OR|O_BYTE,"or.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNDEC,0},2, {{0xb8,0xf8,RN },{0x1c,0xff,0}}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND_D8,0},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x1c,0xff,0}}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0xa8,0xf8,RD }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xa8,0xf8,RD }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS8,0},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x1c,0xff,0}}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{79,'p','E','D','D',O_MULXU|O_BYTE,"mulxu.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNINC},3, {{0xc0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x1c,0xff,0}}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND},3, {{0xd0,0xf8,RN },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x1c,0xff,0}}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x00,0xff,0},{0x90,0xf8,RS }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x00,0xff,0},{0x90,0xf8,RS }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND,RD},3, {{0xd0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNINC,RD},3, {{0xc0,0xf8,RN },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D8,RD},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{RNIND_D16,RD},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{IMM8,RD},4, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS8,RD},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x00,0xff,0},{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNINC,0},2, {{0xc0,0xf8,RN },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND,0},2, {{0xd0,0xf8,RN },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNIND_D8,0},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x80,0xf8,RD }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{RNDEC,0},2, {{0xb0,0xf8,RN },{0x1d,0xff,0}}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x90,0xf8,RS }}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{IMM8,0},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x1d,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS8,0},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x1d,0xff,0}}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNDEC},4, {{0xb8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNINC},4, {{0xc8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND},4, {{0xd8,0xf8,RN },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x90,0xf8,RS }}}, + + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x80,0xf8,RD }}}, +{94,'m','E','!','D',O_MOV|O_BYTE,"mov:g.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{94,'m','S','!','E',O_MOV|O_BYTE,"mov:g.b",2,{RS,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x06,0xff,0},{0x00,0x00,IMM8 }}}, +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + + +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{IMM16,0},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x80,0xf8,RD }}}, +{83,'-','E','!','D',O_MOVFPE|O_BYTE,"movfpe.b",2,{ABS16,RD},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x00,0xff,0},{0x80,0xf8,RD }}}, +{81,'-','S','!','E',O_MOVTPE|O_BYTE,"movtpe.b",2,{RS,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x00,0xff,0},{0x90,0xf8,RS }}}, +{94,'m','I','!','E',O_MOV|O_BYTE,"mov:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 }}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x07,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, + +{93,'m','I','!','E',O_MOV|O_WORD,"mov:g.w",2,{IMM8,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x06,0xff,0},{0x00,0x00,IMM8 },{0x00,0x00,0}}}, + +{76,'a','E','!','E',O_NEG|O_BYTE,"neg.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{56,'h','E','!','E',O_ROTR|O_BYTE,"rotr.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{93,'m','E','!','D',O_MOV|O_WORD,"mov:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x80,0xf8,RD }}}, +{93,'m','S','!','E',O_MOV|O_WORD,"mov:g.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x90,0xf8,RS }}}, +{78,'p','E','D','D',O_MULXU|O_WORD,"mulxu.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa8,0xf8,RD }}}, +{75,'a','E','!','E',O_NEG|O_WORD,"neg.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x14,0xff,0}}}, +{55,'h','E','!','E',O_ROTR|O_WORD,"rotr.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1d,0xff,0}}}, +{72,'m','E','!','E',O_NOT|O_BYTE,"not.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{68,'m','E','D','D',O_OR|O_WORD,"or.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x40,0xf8,RD }}}, +{71,'m','E','!','E',O_NOT|O_WORD,"not.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x15,0xff,0}}}, +{58,'h','E','!','E',O_ROTL|O_WORD,"rotl.w",1,{ABS16,0},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{59,'h','E','!','E',O_ROTL|O_BYTE,"rotl.b",1,{ABS16,0},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x1c,0xff,0}}}, +{125,'a','D','I','!',O_CMP|O_BYTE,"cmp:e.b",2,{IMM8,RD},2, {{0x40,0xf8,RD },{0x00,0x00,IMM8 }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RN},3, {{0xa0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0x70,0xf8,RD }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RN},4, {{0xa8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RN,CRB},2, {{0xa0,0xf8,RN },{0x88,0xf8,CRB }}}, +{120,'a','D','I','!',O_CMP|O_WORD,"cmp:i.w",2,{IMM16,RD},3, {{0x48,0xf8,RD },{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RN,RD},2, {{0xa0,0xf8,RN },{0xb8,0xf8,RD }}}, +{119,'s','D','!','!',O_DADD|O_UNSZ,"dadd",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff,0},{0xa0,0xf8,RD }}}, +{115,'s','D','!','!',O_DSUB|O_UNSZ,"dsub",2,{RS,RD},3, {{0xa0,0xf8,RS },{0x00,0xff,0},{0xb0,0xf8,RD }}}, +{113,'s','D','!','D',O_EXTS|O_BYTE,"exts.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x11,0xff,0}}}, +{111,'s','D','!','D',O_EXTU|O_BYTE,"extu.b",1,{RD,0},2, {{0xa0,0xf8,RD },{0x12,0xff,0}}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RN,RD},2, {{0xa8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D8,CRB},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x88,0xf8,CRB }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND_D16,CRB},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x88,0xf8,CRB }}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{ABS16,0},3, {{0x10,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0}}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND,0},2, {{0x11,0xff,0},{0xd0,0xf8,RD }}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND,0},2, {{0x11,0xff,0},{0xd8,0xf8,RD }}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D8,0},3, {{0x11,0xff,0},{0xe0,0xf8,RDIND_D8 },{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D8,0},3, {{0x11,0xff,0},{0xe8,0xf8,RDIND_D8 },{0x00,0x00,0}}}, +{110,'-','B','!','!',O_JMP|O_UNSZ,"jmp",1,{RDIND_D16,0},4, {{0x11,0xff,0},{0xf0,0xf8,RDIND_D16 },{0x00,0x00,0},{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{RDIND_D16,0},4, {{0x11,0xff,0},{0xf8,0xf8,RDIND_D16 },{0x00,0x00,0},{0x00,0x00,0}}}, +{109,'-','B','!','!',O_JSR|O_UNSZ,"jsr",1,{ABS16,0},3, {{0x18,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0}}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS16,CRB},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNINC,CRB},2, {{0xc0,0xf8,RN },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNIND,CRB},2, {{0xd0,0xf8,RN },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{IMM8,CRB},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x88,0xf8,CRB }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{117,'s','E','D','D',O_DIVXU|O_BYTE,"divxu.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xb8,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{ABS8,CRB},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x88,0xf8,CRB }}}, +{116,'s','E','D','D',O_DIVXU|O_WORD,"divxu.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xb8,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNDEC,RD},2, {{0xb0,0xf8,RN },{0x70,0xf8,RD }}}, +{107,'s','E','!','C',O_LDC|O_BYTE,"ldc.b",2,{RNDEC,CRB},2, {{0xb0,0xf8,RN },{0x88,0xf8,CRB }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNDEC},3, {{0xb0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNDEC},4, {{0xb8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNDEC,RD},2, {{0xb8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNINC,RD},2, {{0xc0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNINC},3, {{0xc0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNINC},4, {{0xc8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNINC,RD},2, {{0xc8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND,RD},2, {{0xd0,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND},3, {{0xd0,0xf8,RN },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND},4, {{0xd8,0xf8,RN },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND,RD},2, {{0xd8,0xf8,RN },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D8,RD},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D8},4, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D8},5, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D8,RD},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RNIND_D16},5, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RNIND_D16},6, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{105,'-','E','!','C',O_LDM|O_UNSZ,"ldm",2,{SPINC,RLIST},2, {{0x02,0xff,0},{0x00,0x00,RLIST }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS8},4, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS8},5, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{106,'s','E','!','C',O_LDC|O_WORD,"ldc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x88,0xf8,CRW }}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x70,0xf8,RD }}}, +{123,'a','D','E','!',O_CMP|O_BYTE,"cmp:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{123,'a','E','I','!',O_CMP|O_BYTE,"cmp:g.b",2,{IMM8,ABS16},5, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x04,0xff,0},{0x00,0x00,IMM8 }}}, +{122,'a','E','I','!',O_CMP|O_WORD,"cmp:g.w",2,{IMM16,ABS16},6, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x05,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{122,'a','D','E','!',O_CMP|O_WORD,"cmp:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x70,0xf8,RD }}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM16},3, {{0x1f,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0}}}, +{104,'-','S','I','!',O_LINK|O_UNSZ,"link",2,{FP,IMM8},2, {{0x17,0xff,0},{0x00,0x00,IMM8 }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RN},2, {{0xa0,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{140,'b','E','I','E',O_BTST|O_BYTE,"btst.b",2,{IMM4,RN},2, {{0xa0,0xf8,RN },{0xf0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RN},2, {{0xa0,0xf8,RN },{0x48,0xf8,RS }}}, +{140,'b','E','S','E',O_BTST|O_BYTE,"btst.b",2,{RS,RN},2, {{0xa0,0xf8,RN },{0x78,0xf8,RS }}}, +{131,'c','!','!','E',O_CLR|O_BYTE,"clr.b",1,{RN,0},2, {{0xa0,0xf8,RN },{0x13,0xff,0}}}, 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{{0xb8,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,RNDEC},2, {{0xb8,0xf8,RN },{0x48,0xf8,RS }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RNINC},2, {{0xc0,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RNINC},2, {{0xc0,0xf8,RN },{0x48,0xf8,RS }}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,RNINC},2, {{0xc8,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,RNINC},2, {{0xc8,0xf8,RN },{0x48,0xf8,RS }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNINC,0},2, {{0xc8,0xf8,RN },{0x13,0xff,0}}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RNIND},2, {{0xd0,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RNIND},2, {{0xd0,0xf8,RN },{0x48,0xf8,RS }}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,RNIND},2, {{0xd8,0xf8,RN },{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,RNIND},2, {{0xd8,0xf8,RN },{0x48,0xf8,RS }}}, +{130,'c','!','!','E',O_CLR|O_WORD,"clr.w",1,{RNIND,0},2, {{0xd8,0xf8,RN },{0x13,0xff,0}}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RNIND_D8},3, {{0xe0,0xf8,RN },{0x00,0x00,DISP8 },{0x48,0xf8,RS }}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,RNIND_D8},3, {{0xe8,0xf8,RN },{0x00,0x00,DISP8 },{0x48,0xf8,RS }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x48,0xf8,RS }}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x48,0xf8,RS }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x48,0xf8,RS }}}, +{148,'b','E','I','E',O_BSET|O_WORD,"bset.w",2,{IMM4,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xc0,0xf0,IMM4 }}}, +{148,'b','E','S','E',O_BSET|O_WORD,"bset.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x48,0xf8,RS }}}, +{146,'-','B','!','!',O_BSR|O_BYTE,"bsr.b",1,{PCREL8,0},2, {{0x0e,0xff,0},{0x00,0x00,PCREL8 }}}, +{149,'b','E','I','E',O_BSET|O_BYTE,"bset.b",2,{IMM4,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xc0,0xf0,IMM4 }}}, +{149,'b','E','S','E',O_BSET|O_BYTE,"bset.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x48,0xf8,RS }}}, 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},{0x00,0x00,DISP16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{162,'b','E','S','E',O_BNOT|O_BYTE,"bnot.b",2,{RS,RNIND_D16},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xd0,0xf0,IMM4 }}}, +{161,'b','E','I','E',O_BNOT|O_WORD,"bnot.w",2,{IMM4,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xe0,0xf0,IMM4 }}}, +{221,'a','I','E','E',O_ADD|O_WORD,"add:q.w",2,{QIM,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x08,0xf8,QIM }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x58,0xf8,RS }}}, +{161,'b','E','S','E',O_BNOT|O_WORD,"bnot.w",2,{RS,RNIND_D16},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x20,0xf8,RD }}}, +{219,'-','E','D','D',O_ADDS|O_BYTE,"adds.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x28,0xf8,RD }}}, +{213,'m','E','D','D',O_AND|O_BYTE,"and.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x50,0xf8,RD }}}, +{210,'s','I','S','S',O_ANDC|O_BYTE,"andc.b",2,{IMM8,CRB},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0x58,0xf8,CRB }}}, +{216,'a','E','D','D',O_ADDX|O_BYTE,"addx.b",2,{IMM8,RD},3, {{0x04,0xff,0},{0x00,0x00,IMM8 },{0xa0,0xf8,RD }}}, +{204,'b','E','I','E',O_BCLR|O_BYTE,"bclr.b",2,{IMM4,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xd0,0xf0,IMM4 }}}, +{162,'b','E','I','E',O_BNOT|O_BYTE,"bnot.b",2,{IMM4,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xe0,0xf0,IMM4 }}}, +{222,'a','I','E','E',O_ADD|O_BYTE,"add:q.b",2,{QIM,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{219,'-','E','D','D',O_ADDS|O_BYTE,"adds.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x28,0xf8,RD }}}, +{213,'m','E','D','D',O_AND|O_BYTE,"and.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x50,0xf8,RD }}}, +{204,'b','E','S','E',O_BCLR|O_BYTE,"bclr.b",2,{RS,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x58,0xf8,RS }}}, +{162,'b','E','S','E',O_BNOT|O_BYTE,"bnot.b",2,{RS,ABS8},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0x68,0xf8,RS }}}, +{216,'a','E','D','D',O_ADDX|O_BYTE,"addx.b",2,{ABS8,RD},3, {{0x05,0xff,0},{0x00,0x00,ABS8 },{0xa0,0xf8,RD }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{209,'s','I','S','S',O_ANDC|O_WORD,"andc.w",2,{IMM16,CRW},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0x58,0xf8,CRW }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{IMM16,RD},4, {{0x0c,0xff,0},{0x00,0x00,IMM16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{161,'b','E','I','E',O_BNOT|O_WORD,"bnot.w",2,{IMM4,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xe0,0xf0,IMM4 }}}, +{221,'a','I','E','E',O_ADD|O_WORD,"add:q.w",2,{QIM,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x08,0xf8,QIM }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x20,0xf8,RD }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x28,0xf8,RD }}}, +{157,'-','!','!','!',O_BPT|O_UNSZ,"bpt",0,{0,0},1, {{0x0b,0xff,0}}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xd0,0xf0,IMM4 }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x50,0xf8,RD }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x58,0xf8,RS }}}, +{161,'b','E','S','E',O_BNOT|O_WORD,"bnot.w",2,{RS,ABS8},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0x68,0xf8,RS }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{ABS8,RD},3, {{0x0d,0xff,0},{0x00,0x00,ABS8 },{0xa0,0xf8,RD }}}, +{204,'b','E','I','E',O_BCLR|O_BYTE,"bclr.b",2,{IMM4,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xd0,0xf0,IMM4 }}}, +{225,'a','E','D','D',O_ADD|O_BYTE,"add:g.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{219,'-','E','D','D',O_ADDS|O_BYTE,"adds.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{213,'m','E','D','D',O_AND|O_BYTE,"and.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{204,'b','E','S','E',O_BCLR|O_BYTE,"bclr.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x58,0xf8,RS }}}, +{216,'a','E','D','D',O_ADDX|O_BYTE,"addx.b",2,{ABS16,RD},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{203,'b','E','I','E',O_BCLR|O_WORD,"bclr.w",2,{IMM4,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xd0,0xf0,IMM4 }}}, +{218,'-','E','D','D',O_ADDS|O_WORD,"adds.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x28,0xf8,RD }}}, +{212,'m','E','D','D',O_AND|O_WORD,"and.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x50,0xf8,RD }}}, +{203,'b','E','S','E',O_BCLR|O_WORD,"bclr.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x58,0xf8,RS }}}, +{215,'a','E','D','D',O_ADDX|O_WORD,"addx.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xa0,0xf8,RD }}}, +{155,'-','B','!','!',O_BRA|O_BYTE,"bra.b",1,{PCREL8,0},2, {{0x20,0xff,0},{0x00,0x00,PCREL8 }}}, +{162,'b','E','I','E',O_BNOT|O_BYTE,"bnot.b",2,{IMM4,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xe0,0xf0,IMM4 }}}, +{222,'a','I','E','E',O_ADD|O_BYTE,"add:q.b",2,{QIM,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x08,0xf8,QIM }}}, +{162,'b','E','S','E',O_BNOT|O_BYTE,"bnot.b",2,{RS,ABS16},4, {{0x15,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{161,'b','E','I','E',O_BNOT|O_WORD,"bnot.w",2,{IMM4,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0xe0,0xf0,IMM4 }}}, +{221,'a','I','E','E',O_ADD|O_WORD,"add:q.w",2,{QIM,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x08,0xf8,QIM }}}, +{224,'a','E','D','D',O_ADD|O_WORD,"add:g.w",2,{ABS16,RD},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x20,0xf8,RD }}}, +{161,'b','E','S','E',O_BNOT|O_WORD,"bnot.w",2,{RS,ABS16},4, {{0x1d,0xff,0},{0x00,0x00,ABS16 },{0x00,0x00,0},{0x68,0xf8,RS }}}, +{152,'-','B','!','!',O_BRN|O_BYTE,"brn.b",1,{PCREL8,0},2, {{0x21,0xff,0},{0x00,0x00,PCREL8 }}}, +{186,'-','B','!','!',O_BHI|O_BYTE,"bhi.b",1,{PCREL8,0},2, {{0x22,0xff,0},{0x00,0x00,PCREL8 }}}, +{174,'-','B','!','!',O_BLS|O_BYTE,"bls.b",1,{PCREL8,0},2, {{0x23,0xff,0},{0x00,0x00,PCREL8 }}}, +{207,'-','B','!','!',O_BCC|O_BYTE,"bcc.b",1,{PCREL8,0},2, {{0x24,0xff,0},{0x00,0x00,PCREL8 }}}, +{201,'-','B','!','!',O_BCS|O_BYTE,"bcs.b",1,{PCREL8,0},2, {{0x25,0xff,0},{0x00,0x00,PCREL8 }}}, +{165,'-','B','!','!',O_BNE|O_BYTE,"bne.b",1,{PCREL8,0},2, {{0x26,0xff,0},{0x00,0x00,PCREL8 }}}, +{198,'-','B','!','!',O_BEQ|O_BYTE,"beq.b",1,{PCREL8,0},2, {{0x27,0xff,0},{0x00,0x00,PCREL8 }}}, +{159,'-','B','!','!',O_BPL|O_BYTE,"bpl.b",1,{PCREL8,0},2, {{0x2a,0xff,0},{0x00,0x00,PCREL8 }}}, +{168,'-','B','!','!',O_BMI|O_BYTE,"bmi.b",1,{PCREL8,0},2, {{0x2b,0xff,0},{0x00,0x00,PCREL8 }}}, +{192,'-','B','!','!',O_BGE|O_BYTE,"bge.b",1,{PCREL8,0},2, {{0x2c,0xff,0},{0x00,0x00,PCREL8 }}}, +{171,'-','B','!','!',O_BLT|O_BYTE,"blt.b",1,{PCREL8,0},2, {{0x2d,0xff,0},{0x00,0x00,PCREL8 }}}, +{189,'-','B','!','!',O_BGT|O_BYTE,"bgt.b",1,{PCREL8,0},2, {{0x2e,0xff,0},{0x00,0x00,PCREL8 }}}, +{180,'-','B','!','!',O_BLE|O_BYTE,"ble.b",1,{PCREL8,0},2, {{0x2f,0xff,0},{0x00,0x00,PCREL8 }}}, +{154,'-','B','!','!',O_BRA|O_WORD,"bra.w",1,{PCREL16,0},3, {{0x30,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{151,'-','B','!','!',O_BRN|O_WORD,"brn.w",1,{PCREL16,0},3, {{0x31,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{185,'-','B','!','!',O_BHI|O_WORD,"bhi.w",1,{PCREL16,0},3, {{0x32,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{173,'-','B','!','!',O_BLS|O_WORD,"bls.w",1,{PCREL16,0},3, {{0x33,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{206,'-','B','!','!',O_BCC|O_WORD,"bcc.w",1,{PCREL16,0},3, {{0x34,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{200,'-','B','!','!',O_BCS|O_WORD,"bcs.w",1,{PCREL16,0},3, {{0x35,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{164,'-','B','!','!',O_BNE|O_WORD,"bne.w",1,{PCREL16,0},3, {{0x36,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{197,'-','B','!','!',O_BEQ|O_WORD,"beq.w",1,{PCREL16,0},3, {{0x37,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{158,'-','B','!','!',O_BPL|O_WORD,"bpl.w",1,{PCREL16,0},3, {{0x3a,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{167,'-','B','!','!',O_BMI|O_WORD,"bmi.w",1,{PCREL16,0},3, {{0x3b,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{191,'-','B','!','!',O_BGE|O_WORD,"bge.w",1,{PCREL16,0},3, {{0x3c,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{170,'-','B','!','!',O_BLT|O_WORD,"blt.w",1,{PCREL16,0},3, {{0x3d,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{188,'-','B','!','!',O_BGT|O_WORD,"bgt.w",1,{PCREL16,0},3, {{0x3e,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +{179,'-','B','!','!',O_BLE|O_WORD,"ble.w",1,{PCREL16,0},3, {{0x3f,0xff,0},{0x00,0x00,PCREL16 },{0x00,0x00,0}}}, +/* +RN,RD 'm','E','D','D' +CRB,RN 's','C','!','E' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +CRB,RNDEC 's','C','!','E' +RNDEC,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +CRB,RNINC 's','C','!','E' +RNINC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +CRB,RNIND 's','C','!','E' +RNIND,RD 'm','E','D','D' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD 'm','E','D','D' +CRB,RNIND_D8 's','C','!','E' +RNIND_D8,RD 'm','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD 'm','E','D','D' +CRB,RNIND_D16 's','C','!','E' +RNIND_D16,RD 'm','E','D','D' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +RNIND_D8,RD 'm','E','D','D' +ABS8,RD 'm','E','D','D' +IMM16,RD 'm','E','D','D' +ABS16,RD 'm','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RN,RD 'a','E','D','D' +RS,RD '-','X','!','!' +RN,0 'a','E','!','!' +RS,RD '-','X','!','!' +RN,0 'a','E','!','!' +RNDEC,RD 'a','E','D','D' +RNDEC,0 'a','E','!','!' +RNDEC,RD 'a','E','D','D' +RNDEC,0 'a','E','!','!' +RNINC,RD 'a','E','D','D' +RNINC,0 'a','E','!','!' +RNINC,0 'a','E','!','!' +RNIND,RD 'a','E','D','D' +RNIND,0 'a','E','!','!' +RNIND,RD 'a','E','D','D' +RNIND,0 'a','E','!','!' +RNIND_D8,0 'a','E','!','!' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,0 'a','E','!','!' +RNIND_D16,0 'a','E','!','!' +RNIND_D16,RD 'a','E','D','D' +RN,0 'a','E','!','!' +RNIND,0 'a','E','!','!' +RNDEC,0 'a','E','!','!' +RNINC,0 'a','E','!','!' +ABS8,0 'a','E','!','!' +RNIND_D8,0 'a','E','!','!' +RD,0 'm','D','!','D' +ABS16,0 'a','E','!','!' +RNIND_D16,0 'a','E','!','!' +RN,0 's','E','!','E' +RN,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +RNDEC,0 's','E','!','E' +RNDEC,RD 'a','E','D','D' +RNINC,0 's','E','!','E' +RNINC,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +RNIND,0 's','E','!','E' +RNIND,RD 'a','E','D','D' +RNIND_D8,0 's','E','!','E' +RN,0 's','E','!','E' +RNIND,0 's','E','!','E' +RNINC,0 's','E','!','E' +RNDEC,0 's','E','!','E' +IMM8,0 's','E','!','E' +ABS8,0 's','E','!','E' +RNIND_D8,0 's','E','!','E' +ABS16,0 's','E','!','E' +RNIND_D16,0 's','E','!','E' +RNIND_D8,RD '-','E','D','D' +RD,0 'm','D','!','D' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,0 's','E','!','E' +IMM16,0 'a','E','!','!' +RN,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RN,RD '-','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNINC,RD '-','E','D','D' +RNINC,RD 'a','E','D','D' +RNINC,RD '-','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +RNIND_D8,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,0 'a','E','!','!' +IMM8,RD 'a','E','D','D' +IMM8,RD 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'a','E','I','!' +IMM16,RNIND_D16 'a','E','I','!' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RS,RN 'b','E','S','E' +RS,RN 'b','E','S','E' +RN,0 'c','!','!','E' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RNDEC,0 'c','!','!','E' +RNINC,0 'c','!','!','E' +RNIND,0 'c','!','!','E' +RS,RNIND 'b','E','S','E' +RNIND_D8,0 'c','!','!','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RNIND_D16,0 'c','!','!','E' +RNIND_D16,0 'c','!','!','E' +IMM8,0 'c','!','!','E' +ABS8,0 'c','!','!','E' +RN,0 'c','!','!','E' +RNIND,0 'c','!','!','E' +RNINC,0 'c','!','!','E' +RNDEC,0 'c','!','!','E' +ABS8,0 'c','!','!','E' +RNIND_D8,0 'c','!','!','E' +IMM16,0 'c','!','!','E' +ABS16,0 'c','!','!','E' +RNIND_D16,0 'c','!','!','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RNDEC 'b','E','S','E' +IMM4,RNDEC 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'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNDEC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +RN,0 'c','!','!','E' +IMM4,RNDEC 'b','E','I','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +RS,RNINC 'b','E','S','E' +RNINC,0 'c','!','!','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RNIND,0 'c','!','!','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +PCREL8,0 '-','B','!','!' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +IMM4,RN 'b','E','I','E' +IMM4,RNIND 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNINC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RN 'a','I','E','E' +RN,RD '-','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RN,RD 'a','E','D','D' +RN,RD 'm','E','D','D' +RS,RN 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RN 'b','E','S','E' +RN,RD 'a','E','D','D' +IMM4,RN 'b','E','I','E' +IMM4,RN 'b','E','I','E' +QIM,RN 'a','I','E','E' +RN,RD 'a','E','D','D' +RN,RD '-','E','D','D' +RN,RD 'm','E','D','D' +RS,RN 'b','E','S','E' +RS,RN 'b','E','S','E' +RN,RD 'a','E','D','D' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'm','E','D','D' +RS,RNDEC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +RNDEC,RD 'a','E','D','D' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNDEC 'b','E','I','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +RNDEC,RD '-','E','D','D' +RNDEC,RD 'm','E','D','D' +RS,RNDEC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNINC,RD 'm','E','D','D' +IMM4,RNINC 'b','E','I','E' +RS,RN 'b','E','S','E' +RS,RNIND 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD '-','E','D','D' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RNINC 'a','I','E','E' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD 'a','E','D','D' +IMM4,RNINC 'b','E','I','E' +RNINC,RD 'a','E','D','D' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RS,RNINC 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +IMM4,RNIND 'b','E','I','E' +PCREL8,0 '-','B','!','!' +RNINC,RD 'a','E','D','D' +PCREL16,0 '-','B','!','!' +RNINC,RD '-','E','D','D' +RS,RNINC 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNINC,RD 'm','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +QIM,RNINC 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND,RD 'm','E','D','D' +RS,RNIND 'b','E','S','E' +RS,RNIND 'b','E','S','E' +RNIND,RD 'a','E','D','D' +IMM4,RNIND 'b','E','I','E' +IMM4,RNIND 'b','E','I','E' +QIM,RNIND 'a','I','E','E' +RNIND,RD 'a','E','D','D' +RNIND,RD '-','E','D','D' +RNIND,RD 'm','E','D','D' +RS,RNIND 'b','E','S','E' +RS,RNIND 'b','E','S','E' +RNIND,RD 'a','E','D','D' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,RNIND_D8 'b','E','I','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D8,RD 'm','E','D','D' +RS,RNIND_D8 'b','E','S','E' +RS,RNIND_D8 'b','E','S','E' +RNIND_D8,RD 'a','E','D','D' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,RNIND_D8 'b','E','I','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +RNIND_D8,RD '-','E','D','D' +RNIND_D8,RD 'm','E','D','D' +RS,RNIND_D8 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +QIM,RNIND_D16 'a','I','E','E' +RS,RNIND_D16 'b','E','S','E' +RS,RN 'b','E','S','E' +IMM4,RNDEC 'b','E','I','E' +IMM4,RNINC 'b','E','I','E' +RS,RNIND 'b','E','S','E' +RS,RNINC 'b','E','S','E' +RS,RNDEC 'b','E','S','E' +IMM4,RNIND 'b','E','I','E' +IMM4,RN 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +IMM4,ABS8 'b','E','I','E' +RS,ABS8 'b','E','S','E' +IMM4,RNIND_D8 'b','E','I','E' +IMM4,ABS16 'b','E','I','E' +RS,RNIND_D16 'b','E','S','E' +RS,ABS16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +RS,RNIND_D8 'b','E','S','E' +RNIND_D16,RD 'a','E','D','D' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RNIND_D16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +IMM8,CRB 's','I','S','S' +IMM16,CRW 's','I','S','S' +RNIND_D8,RD 'a','E','D','D' +IMM4,RNIND_D16 'b','E','I','E' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RS,RNIND_D16 'b','E','S','E' +IMM4,RNIND_D16 'b','E','I','E' +IMM4,RNIND_D16 'b','E','I','E' +QIM,RNIND_D16 'a','I','E','E' +RNIND_D16,RD '-','E','D','D' +RNIND_D16,RD 'm','E','D','D' +RS,RNIND_D16 'b','E','S','E' +RS,RNIND_D16 'b','E','S','E' +RNIND_D16,RD 'a','E','D','D' +IMM8,RD 'a','E','D','D' +IMM8,RD '-','E','D','D' +IMM8,RD 'm','E','D','D' +IMM8,CRB 's','I','S','S' +IMM8,RD 'a','E','D','D' +RN,RD 'm','E','D','D' +RNDEC,RD 'm','E','D','D' +RNINC,RD 'm','E','D','D' +RNIND,RD 'm','E','D','D' +ABS8,RD 'm','E','D','D' +RNIND_D8,RD 'm','E','D','D' +IMM16,RD 'm','E','D','D' +ABS16,RD 'm','E','D','D' +RNIND_D16,RD 'm','E','D','D' +IMM4,ABS8 'b','E','I','E' +IMM4,ABS8 'b','E','I','E' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +ABS8,RD '-','E','D','D' +ABS8,RD 'm','E','D','D' +RS,ABS8 'b','E','S','E' +RS,ABS8 'b','E','S','E' +ABS8,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +IMM16,RD '-','E','D','D' +IMM16,RD 'm','E','D','D' +IMM16,CRW 's','I','S','S' +IMM16,RD 'a','E','D','D' +IMM4,ABS8 'b','E','I','E' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +ABS8,RD '-','E','D','D' +RN,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +0,0 '-','!','!','!' +IMM4,ABS8 'b','E','I','E' +ABS8,RD 'm','E','D','D' +RS,ABS8 'b','E','S','E' +RS,ABS8 'b','E','S','E' +ABS8,RD 'a','E','D','D' +IMM4,ABS16 'b','E','I','E' +ABS16,RD 'a','E','D','D' +ABS16,RD '-','E','D','D' +ABS16,RD 'm','E','D','D' +RS,ABS16 'b','E','S','E' +ABS16,RD 'a','E','D','D' +IMM4,ABS16 'b','E','I','E' +ABS16,RD '-','E','D','D' +ABS16,RD 'm','E','D','D' +RS,ABS16 'b','E','S','E' +ABS16,RD 'a','E','D','D' +PCREL8,0 '-','B','!','!' +RN,RD '-','E','D','D' +RNIND,RD '-','E','D','D' +RNINC,RD '-','E','D','D' +RNDEC,RD '-','E','D','D' +ABS8,RD '-','E','D','D' +RNIND_D8,RD '-','E','D','D' +ABS16,RD '-','E','D','D' +IMM16,RD '-','E','D','D' +RNIND_D16,RD '-','E','D','D' +IMM4,ABS16 'b','E','I','E' +QIM,ABS16 'a','I','E','E' +RS,ABS16 'b','E','S','E' +IMM4,ABS16 'b','E','I','E' +QIM,ABS16 'a','I','E','E' +ABS16,RD 'a','E','D','D' +RS,ABS16 'b','E','S','E' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +QIM,RN 'a','I','E','E' +QIM,RNDEC 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +QIM,ABS16 'a','I','E','E' +QIM,RNIND_D16 'a','I','E','E' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL8,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +PCREL16,0 '-','B','!','!' +RN,RD 'a','E','D','D' +RNDEC,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +IMM16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNIND 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNDEC 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNIND,RD 'a','E','D','D' +RNINC,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +IMM16,RD 'a','E','D','D' +QIM,ABS16 'a','I','E','E' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNIND 'a','I','E','E' +RNINC,RD 'a','E','D','D' +QIM,RNDEC 'a','I','E','E' +RNIND,RD 'a','E','D','D' +QIM,RNIND_D8 'a','I','E','E' +IMM8,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +ABS8,RD 'a','E','D','D' +RNIND_D8,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +QIM,ABS16 'a','I','E','E' +ABS16,RD 'a','E','D','D' +RNIND_D16,RD 'a','E','D','D' +RN,RD 'a','E','D','D' +QIM,RN 'a','I','E','E' +QIM,RNDEC 'a','I','E','E' +RNDEC,RD 'a','E','D','D' +QIM,RNIND 'a','I','E','E' +QIM,RNINC 'a','I','E','E' +RNINC,RD 'a','E','D','D' +RNIND,RD 'a','E','D','D' +QIM,ABS8 'a','I','E','E' +QIM,RNIND_D8 'a','I','E','E' +RNIND_D8,RD 'a','E','D','D' +ABS8,RD 'a','E','D','D' +ABS16,RD 'a','E','D','D' +QIM,RNIND_D16 'a','I','E','E' +IMM16,RD 'a','E','D','D' +QIM,ABS16 'a','I','E','E' +RNIND_D16,RD 'a','E','D','D' +*/ +{0,0,0,0,0,0,NULL,0,{0,0},0,{}}} +#endif +; +#endif diff --git a/external/gpl3/gdb/dist/opcodes/hppa-dis.c b/external/gpl3/gdb/dist/opcodes/hppa-dis.c new file mode 100644 index 000000000000..74d9ece9f8a4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/hppa-dis.c @@ -0,0 +1,1236 @@ +/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. + Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003, + 2005, 2007 Free Software Foundation, Inc. + + Contributed by the Center for Software Science at the + University of Utah (pa-gdb-bugs@cs.utah.edu). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libhppa.h" +#include "opcode/hppa.h" + +/* Integer register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const reg_names[] = +{ + "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", + "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1", + "sp", "r31" +}; + +/* Floating point register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const fp_reg_names[] = +{ + "fpsr", "fpe2", "fpe4", "fpe6", + "fr4", "fr5", "fr6", "fr7", "fr8", + "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31" +}; + +typedef unsigned int CORE_ADDR; + +/* Get at various relevent fields of an instruction word. */ + +#define MASK_5 0x1f +#define MASK_10 0x3ff +#define MASK_11 0x7ff +#define MASK_14 0x3fff +#define MASK_16 0xffff +#define MASK_21 0x1fffff + +/* These macros get bit fields using HP's numbering (MSB = 0). */ + +#define GET_FIELD(X, FROM, TO) \ + ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) + +#define GET_BIT(X, WHICH) \ + GET_FIELD (X, WHICH, WHICH) + +/* Some of these have been converted to 2-d arrays because they + consume less storage this way. If the maintenance becomes a + problem, convert them back to const 1-d pointer arrays. */ +static const char *const control_reg[] = +{ + "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", + "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr", + "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3", + "tr4", "tr5", "tr6", "tr7" +}; + +static const char *const compare_cond_names[] = +{ + "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od", + ",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev" +}; +static const char *const compare_cond_64_names[] = +{ + ",*", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od", + ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev" +}; +static const char *const cmpib_cond_64_names[] = +{ + ",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>" +}; +static const char *const add_cond_names[] = +{ + "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od", + ",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev" +}; +static const char *const add_cond_64_names[] = +{ + ",*", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od", + ",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev" +}; +static const char *const wide_add_cond_names[] = +{ + "", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=", + ",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>" +}; +static const char *const logical_cond_names[] = +{ + "", ",=", ",<", ",<=", 0, 0, 0, ",od", + ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"}; +static const char *const logical_cond_64_names[] = +{ + ",*", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od", + ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"}; +static const char *const unit_cond_names[] = +{ + "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc", + ",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc" +}; +static const char *const unit_cond_64_names[] = +{ + ",*", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc", + ",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc" +}; +static const char *const shift_cond_names[] = +{ + "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev" +}; +static const char *const shift_cond_64_names[] = +{ + ",*", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev" +}; +static const char *const bb_cond_64_names[] = +{ + ",*<", ",*>=" +}; +static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"}; +static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"}; +static const char *const short_bytes_compl_names[] = +{ + "", ",b,m", ",e", ",e,m" +}; +static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; +static const char *const fcnv_fixed_names[] = {",w", ",dw", "", ",qw"}; +static const char *const fcnv_ufixed_names[] = {",uw", ",udw", "", ",uqw"}; +static const char *const float_comp_names[] = +{ + ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>", + ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>", + ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<", + ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true" +}; +static const char *const signed_unsigned_names[] = {",u", ",s"}; +static const char *const mix_half_names[] = {",l", ",r"}; +static const char *const saturation_names[] = {",us", ",ss", 0, ""}; +static const char *const read_write_names[] = {",r", ",w"}; +static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" }; + +/* For a bunch of different instructions form an index into a + completer name table. */ +#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ + GET_FIELD (insn, 18, 18) << 1) + +#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ + (GET_FIELD ((insn), 19, 19) ? 8 : 0)) + +/* Utility function to print registers. Put these first, so gcc's function + inlining can do its stuff. */ + +#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR) + +static void +fput_reg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0"); +} + +static void +fput_fp_reg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0"); +} + +static void +fput_fp_reg_r (unsigned reg, disassemble_info *info) +{ + /* Special case floating point exception registers. */ + if (reg < 4) + (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1); + else + (*info->fprintf_func) (info->stream, "%sR", + reg ? fp_reg_names[reg] : "fr0"); +} + +static void +fput_creg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, control_reg[reg]); +} + +/* Print constants with sign. */ + +static void +fput_const (unsigned num, disassemble_info *info) +{ + if ((int) num < 0) + (*info->fprintf_func) (info->stream, "-%x", - (int) num); + else + (*info->fprintf_func) (info->stream, "%x", num); +} + +/* Routines to extract various sized constants out of hppa + instructions. */ + +/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ +static int +extract_3 (unsigned word) +{ + return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17); +} + +static int +extract_5_load (unsigned word) +{ + return low_sign_extend (word >> 16 & MASK_5, 5); +} + +/* Extract the immediate field from a st{bhw}s instruction. */ + +static int +extract_5_store (unsigned word) +{ + return low_sign_extend (word & MASK_5, 5); +} + +/* Extract the immediate field from a break instruction. */ + +static unsigned +extract_5r_store (unsigned word) +{ + return (word & MASK_5); +} + +/* Extract the immediate field from a {sr}sm instruction. */ + +static unsigned +extract_5R_store (unsigned word) +{ + return (word >> 16 & MASK_5); +} + +/* Extract the 10 bit immediate field from a {sr}sm instruction. */ + +static unsigned +extract_10U_store (unsigned word) +{ + return (word >> 16 & MASK_10); +} + +/* Extract the immediate field from a bb instruction. */ + +static unsigned +extract_5Q_store (unsigned word) +{ + return (word >> 21 & MASK_5); +} + +/* Extract an 11 bit immediate field. */ + +static int +extract_11 (unsigned word) +{ + return low_sign_extend (word & MASK_11, 11); +} + +/* Extract a 14 bit immediate field. */ + +static int +extract_14 (unsigned word) +{ + return low_sign_extend (word & MASK_14, 14); +} + +/* Extract a 16 bit immediate field (PA2.0 wide only). */ + +static int +extract_16 (unsigned word) +{ + int m15, m0, m1; + + m0 = GET_BIT (word, 16); + m1 = GET_BIT (word, 17); + m15 = GET_BIT (word, 31); + word = (word >> 1) & 0x1fff; + word = word | (m15 << 15) | ((m15 ^ m0) << 14) | ((m15 ^ m1) << 13); + return sign_extend (word, 16); +} + +/* Extract a 21 bit constant. */ + +static int +extract_21 (unsigned word) +{ + int val; + + word &= MASK_21; + word <<= 11; + val = GET_FIELD (word, 20, 20); + val <<= 11; + val |= GET_FIELD (word, 9, 19); + val <<= 2; + val |= GET_FIELD (word, 5, 6); + val <<= 5; + val |= GET_FIELD (word, 0, 4); + val <<= 2; + val |= GET_FIELD (word, 7, 8); + return sign_extend (val, 21) << 11; +} + +/* Extract a 12 bit constant from branch instructions. */ + +static int +extract_12 (unsigned word) +{ + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | (word & 0x1) << 11, 12) << 2; +} + +/* Extract a 17 bit constant from branch instructions, returning the + 19 bit signed value. */ + +static int +extract_17 (unsigned word) +{ + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | GET_FIELD (word, 11, 15) << 11 + | (word & 0x1) << 16, 17) << 2; +} + +static int +extract_22 (unsigned word) +{ + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | GET_FIELD (word, 11, 15) << 11 + | GET_FIELD (word, 6, 10) << 16 + | (word & 0x1) << 21, 22) << 2; +} + +/* Print one instruction. */ + +int +print_insn_hppa (bfd_vma memaddr, disassemble_info *info) +{ + bfd_byte buffer[4]; + unsigned int insn, i; + + { + int status = + (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + insn = bfd_getb32 (buffer); + + for (i = 0; i < NUMOPCODES; ++i) + { + const struct pa_opcode *opcode = &pa_opcodes[i]; + + if ((insn & opcode->mask) == opcode->match) + { + const char *s; +#ifndef BFD64 + if (opcode->arch == pa20w) + continue; +#endif + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0])) + (*info->fprintf_func) (info->stream, " "); + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case 'x': + fput_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'a': + case 'b': + fput_reg (GET_FIELD (insn, 6, 10), info); + break; + case '^': + fput_creg (GET_FIELD (insn, 6, 10), info); + break; + case 't': + fput_reg (GET_FIELD (insn, 27, 31), info); + break; + + /* Handle floating point registers. */ + case 'f': + switch (*++s) + { + case 't': + fput_fp_reg (GET_FIELD (insn, 27, 31), info); + break; + case 'T': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 27, 31), info); + else + fput_fp_reg (GET_FIELD (insn, 27, 31), info); + break; + case 'a': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); + else + fput_fp_reg (GET_FIELD (insn, 6, 10), info); + break; + + /* 'fA' will not generate a space before the regsiter + name. Normally that is fine. Except that it + causes problems with xmpyu which has no FP format + completer. */ + case 'X': + fputs_filtered (" ", info); + /* FALLTHRU */ + + case 'A': + if (GET_FIELD (insn, 24, 24)) + fput_fp_reg_r (GET_FIELD (insn, 6, 10), info); + else + fput_fp_reg (GET_FIELD (insn, 6, 10), info); + break; + case 'b': + if (GET_FIELD (insn, 25, 25)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'B': + if (GET_FIELD (insn, 19, 19)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'C': + { + int reg = GET_FIELD (insn, 21, 22); + reg |= GET_FIELD (insn, 16, 18) << 2; + if (GET_FIELD (insn, 23, 23) != 0) + fput_fp_reg_r (reg, info); + else + fput_fp_reg (reg, info); + break; + } + case 'i': + { + int reg = GET_FIELD (insn, 6, 10); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'j': + { + int reg = GET_FIELD (insn, 11, 15); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'k': + { + int reg = GET_FIELD (insn, 27, 31); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'l': + { + int reg = GET_FIELD (insn, 21, 25); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + case 'm': + { + int reg = GET_FIELD (insn, 16, 20); + + reg |= (GET_FIELD (insn, 26, 26) << 4); + fput_fp_reg (reg, info); + break; + } + + /* 'fe' will not generate a space before the register + name. Normally that is fine. Except that it + causes problems with fstw fe,y(b) which has no FP + format completer. */ + case 'E': + fputs_filtered (" ", info); + /* FALLTHRU */ + + case 'e': + if (GET_FIELD (insn, 30, 30)) + fput_fp_reg_r (GET_FIELD (insn, 11, 15), info); + else + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + case 'x': + fput_fp_reg (GET_FIELD (insn, 11, 15), info); + break; + } + break; + + case '5': + fput_const (extract_5_load (insn), info); + break; + case 's': + { + int space = GET_FIELD (insn, 16, 17); + /* Zero means implicit addressing, not use of sr0. */ + if (space != 0) + (*info->fprintf_func) (info->stream, "sr%d", space); + } + break; + + case 'S': + (*info->fprintf_func) (info->stream, "sr%d", + extract_3 (insn)); + break; + + /* Handle completers. */ + case 'c': + switch (*++s) + { + case 'x': + (*info->fprintf_func) + (info->stream, "%s", + index_compl_names[GET_COMPL (insn)]); + break; + case 'X': + (*info->fprintf_func) + (info->stream, "%s ", + index_compl_names[GET_COMPL (insn)]); + break; + case 'm': + (*info->fprintf_func) + (info->stream, "%s", + short_ldst_compl_names[GET_COMPL (insn)]); + break; + case 'M': + (*info->fprintf_func) + (info->stream, "%s ", + short_ldst_compl_names[GET_COMPL (insn)]); + break; + case 'A': + (*info->fprintf_func) + (info->stream, "%s ", + short_bytes_compl_names[GET_COMPL (insn)]); + break; + case 's': + (*info->fprintf_func) + (info->stream, "%s", + short_bytes_compl_names[GET_COMPL (insn)]); + break; + case 'c': + case 'C': + switch (GET_FIELD (insn, 20, 21)) + { + case 1: + (*info->fprintf_func) (info->stream, ",bc "); + break; + case 2: + (*info->fprintf_func) (info->stream, ",sl "); + break; + default: + (*info->fprintf_func) (info->stream, " "); + } + break; + case 'd': + switch (GET_FIELD (insn, 20, 21)) + { + case 1: + (*info->fprintf_func) (info->stream, ",co "); + break; + default: + (*info->fprintf_func) (info->stream, " "); + } + break; + case 'o': + (*info->fprintf_func) (info->stream, ",o"); + break; + case 'g': + (*info->fprintf_func) (info->stream, ",gate"); + break; + case 'p': + (*info->fprintf_func) (info->stream, ",l,push"); + break; + case 'P': + (*info->fprintf_func) (info->stream, ",pop"); + break; + case 'l': + case 'L': + (*info->fprintf_func) (info->stream, ",l"); + break; + case 'w': + (*info->fprintf_func) + (info->stream, "%s ", + read_write_names[GET_FIELD (insn, 25, 25)]); + break; + case 'W': + (*info->fprintf_func) (info->stream, ",w "); + break; + case 'r': + if (GET_FIELD (insn, 23, 26) == 5) + (*info->fprintf_func) (info->stream, ",r"); + break; + case 'Z': + if (GET_FIELD (insn, 26, 26)) + (*info->fprintf_func) (info->stream, ",m "); + else + (*info->fprintf_func) (info->stream, " "); + break; + case 'i': + if (GET_FIELD (insn, 25, 25)) + (*info->fprintf_func) (info->stream, ",i"); + break; + case 'z': + if (!GET_FIELD (insn, 21, 21)) + (*info->fprintf_func) (info->stream, ",z"); + break; + case 'a': + (*info->fprintf_func) + (info->stream, "%s", + add_compl_names[GET_FIELD (insn, 20, 21)]); + break; + case 'Y': + (*info->fprintf_func) + (info->stream, ",dc%s", + add_compl_names[GET_FIELD (insn, 20, 21)]); + break; + case 'y': + (*info->fprintf_func) + (info->stream, ",c%s", + add_compl_names[GET_FIELD (insn, 20, 21)]); + break; + case 'v': + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 't': + (*info->fprintf_func) (info->stream, ",tc"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'B': + (*info->fprintf_func) (info->stream, ",db"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'b': + (*info->fprintf_func) (info->stream, ",b"); + if (GET_FIELD (insn, 20, 20)) + (*info->fprintf_func) (info->stream, ",tsv"); + break; + case 'T': + if (GET_FIELD (insn, 25, 25)) + (*info->fprintf_func) (info->stream, ",tc"); + break; + case 'S': + /* EXTRD/W has a following condition. */ + if (*(s + 1) == '?') + (*info->fprintf_func) + (info->stream, "%s", + signed_unsigned_names[GET_FIELD (insn, 21, 21)]); + else + (*info->fprintf_func) + (info->stream, "%s ", + signed_unsigned_names[GET_FIELD (insn, 21, 21)]); + break; + case 'h': + (*info->fprintf_func) + (info->stream, "%s", + mix_half_names[GET_FIELD (insn, 17, 17)]); + break; + case 'H': + (*info->fprintf_func) + (info->stream, "%s ", + saturation_names[GET_FIELD (insn, 24, 25)]); + break; + case '*': + (*info->fprintf_func) + (info->stream, ",%d%d%d%d ", + GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21), + GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25)); + break; + + case 'q': + { + int m, a; + + m = GET_FIELD (insn, 28, 28); + a = GET_FIELD (insn, 29, 29); + + if (m && !a) + fputs_filtered (",ma ", info); + else if (m && a) + fputs_filtered (",mb ", info); + else + fputs_filtered (" ", info); + break; + } + + case 'J': + { + int opc = GET_FIELD (insn, 0, 5); + + if (opc == 0x16 || opc == 0x1e) + { + if (GET_FIELD (insn, 29, 29) == 0) + fputs_filtered (",ma ", info); + else + fputs_filtered (",mb ", info); + } + else + fputs_filtered (" ", info); + break; + } + + case 'e': + { + int opc = GET_FIELD (insn, 0, 5); + + if (opc == 0x13 || opc == 0x1b) + { + if (GET_FIELD (insn, 18, 18) == 1) + fputs_filtered (",mb ", info); + else + fputs_filtered (",ma ", info); + } + else if (opc == 0x17 || opc == 0x1f) + { + if (GET_FIELD (insn, 31, 31) == 1) + fputs_filtered (",ma ", info); + else + fputs_filtered (",mb ", info); + } + else + fputs_filtered (" ", info); + + break; + } + } + break; + + /* Handle conditions. */ + case '?': + { + s++; + switch (*s) + { + case 'f': + (*info->fprintf_func) + (info->stream, "%s ", + float_comp_names[GET_FIELD (insn, 27, 31)]); + break; + + /* These four conditions are for the set of instructions + which distinguish true/false conditions by opcode + rather than by the 'f' bit (sigh): comb, comib, + addb, addib. */ + case 't': + fputs_filtered + (compare_cond_names[GET_FIELD (insn, 16, 18)], info); + break; + case 'n': + fputs_filtered + (compare_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8], + info); + break; + case 'N': + fputs_filtered + (compare_cond_64_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 2, 2) * 8], + info); + break; + case 'Q': + fputs_filtered + (cmpib_cond_64_names[GET_FIELD (insn, 16, 18)], + info); + break; + case '@': + fputs_filtered + (add_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8], + info); + break; + case 's': + (*info->fprintf_func) + (info->stream, "%s ", + compare_cond_names[GET_COND (insn)]); + break; + case 'S': + (*info->fprintf_func) + (info->stream, "%s ", + compare_cond_64_names[GET_COND (insn)]); + break; + case 'a': + (*info->fprintf_func) + (info->stream, "%s ", + add_cond_names[GET_COND (insn)]); + break; + case 'A': + (*info->fprintf_func) + (info->stream, "%s ", + add_cond_64_names[GET_COND (insn)]); + break; + case 'd': + (*info->fprintf_func) + (info->stream, "%s", + add_cond_names[GET_FIELD (insn, 16, 18)]); + break; + + case 'W': + (*info->fprintf_func) + (info->stream, "%s", + wide_add_cond_names[GET_FIELD (insn, 16, 18) + + GET_FIELD (insn, 4, 4) * 8]); + break; + + case 'l': + (*info->fprintf_func) + (info->stream, "%s ", + logical_cond_names[GET_COND (insn)]); + break; + case 'L': + (*info->fprintf_func) + (info->stream, "%s ", + logical_cond_64_names[GET_COND (insn)]); + break; + case 'u': + (*info->fprintf_func) + (info->stream, "%s ", + unit_cond_names[GET_COND (insn)]); + break; + case 'U': + (*info->fprintf_func) + (info->stream, "%s ", + unit_cond_64_names[GET_COND (insn)]); + break; + case 'y': + case 'x': + case 'b': + (*info->fprintf_func) + (info->stream, "%s", + shift_cond_names[GET_FIELD (insn, 16, 18)]); + + /* If the next character in args is 'n', it will handle + putting out the space. */ + if (s[1] != 'n') + (*info->fprintf_func) (info->stream, " "); + break; + case 'X': + (*info->fprintf_func) + (info->stream, "%s ", + shift_cond_64_names[GET_FIELD (insn, 16, 18)]); + break; + case 'B': + (*info->fprintf_func) + (info->stream, "%s", + bb_cond_64_names[GET_FIELD (insn, 16, 16)]); + + /* If the next character in args is 'n', it will handle + putting out the space. */ + if (s[1] != 'n') + (*info->fprintf_func) (info->stream, " "); + break; + } + break; + } + + case 'V': + fput_const (extract_5_store (insn), info); + break; + case 'r': + fput_const (extract_5r_store (insn), info); + break; + case 'R': + fput_const (extract_5R_store (insn), info); + break; + case 'U': + fput_const (extract_10U_store (insn), info); + break; + case 'B': + case 'Q': + fput_const (extract_5Q_store (insn), info); + break; + case 'i': + fput_const (extract_11 (insn), info); + break; + case 'j': + fput_const (extract_14 (insn), info); + break; + case 'k': + fputs_filtered ("L%", info); + fput_const (extract_21 (insn), info); + break; + case '<': + case 'l': + /* 16-bit long disp., PA2.0 wide only. */ + fput_const (extract_16 (insn), info); + break; + case 'n': + if (insn & 0x2) + (*info->fprintf_func) (info->stream, ",n "); + else + (*info->fprintf_func) (info->stream, " "); + break; + case 'N': + if ((insn & 0x20) && s[1]) + (*info->fprintf_func) (info->stream, ",n "); + else if (insn & 0x20) + (*info->fprintf_func) (info->stream, ",n"); + else if (s[1]) + (*info->fprintf_func) (info->stream, " "); + break; + case 'w': + (*info->print_address_func) + (memaddr + 8 + extract_12 (insn), info); + break; + case 'W': + /* 17 bit PC-relative branch. */ + (*info->print_address_func) + ((memaddr + 8 + extract_17 (insn)), info); + break; + case 'z': + /* 17 bit displacement. This is an offset from a register + so it gets disasssembled as just a number, not any sort + of address. */ + fput_const (extract_17 (insn), info); + break; + + case 'Z': + /* addil %r1 implicit output. */ + fputs_filtered ("r1", info); + break; + + case 'Y': + /* be,l %sr0,%r31 implicit output. */ + fputs_filtered ("sr0,r31", info); + break; + + case '@': + (*info->fprintf_func) (info->stream, "0"); + break; + + case '.': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 24, 25)); + break; + case '*': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 22, 25)); + break; + case '!': + fputs_filtered ("sar", info); + break; + case 'p': + (*info->fprintf_func) (info->stream, "%d", + 31 - GET_FIELD (insn, 22, 26)); + break; + case '~': + { + int num; + num = GET_FIELD (insn, 20, 20) << 5; + num |= GET_FIELD (insn, 22, 26); + (*info->fprintf_func) (info->stream, "%d", 63 - num); + break; + } + case 'P': + (*info->fprintf_func) (info->stream, "%d", + GET_FIELD (insn, 22, 26)); + break; + case 'q': + { + int num; + num = GET_FIELD (insn, 20, 20) << 5; + num |= GET_FIELD (insn, 22, 26); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case 'T': + (*info->fprintf_func) (info->stream, "%d", + 32 - GET_FIELD (insn, 27, 31)); + break; + case '%': + { + int num; + num = (GET_FIELD (insn, 23, 23) + 1) * 32; + num -= GET_FIELD (insn, 27, 31); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case '|': + { + int num; + num = (GET_FIELD (insn, 19, 19) + 1) * 32; + num -= GET_FIELD (insn, 27, 31); + (*info->fprintf_func) (info->stream, "%d", num); + break; + } + case '$': + fput_const (GET_FIELD (insn, 20, 28), info); + break; + case 'A': + fput_const (GET_FIELD (insn, 6, 18), info); + break; + case 'D': + fput_const (GET_FIELD (insn, 6, 31), info); + break; + case 'v': + (*info->fprintf_func) (info->stream, ",%d", + GET_FIELD (insn, 23, 25)); + break; + case 'O': + fput_const ((GET_FIELD (insn, 6,20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case 'o': + fput_const (GET_FIELD (insn, 6, 20), info); + break; + case '2': + fput_const ((GET_FIELD (insn, 6, 22) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case '1': + fput_const ((GET_FIELD (insn, 11, 20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case '0': + fput_const ((GET_FIELD (insn, 16, 20) << 5 | + GET_FIELD (insn, 27, 31)), info); + break; + case 'u': + (*info->fprintf_func) (info->stream, ",%d", + GET_FIELD (insn, 23, 25)); + break; + case 'F': + /* If no destination completer and not before a completer + for fcmp, need a space here. */ + if (s[1] == 'G' || s[1] == '?') + fputs_filtered + (float_format_names[GET_FIELD (insn, 19, 20)], info); + else + (*info->fprintf_func) + (info->stream, "%s ", + float_format_names[GET_FIELD (insn, 19, 20)]); + break; + case 'G': + (*info->fprintf_func) + (info->stream, "%s ", + float_format_names[GET_FIELD (insn, 17, 18)]); + break; + case 'H': + if (GET_FIELD (insn, 26, 26) == 1) + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[0]); + else + (*info->fprintf_func) (info->stream, "%s ", + float_format_names[1]); + break; + case 'I': + /* If no destination completer and not before a completer + for fcmp, need a space here. */ + if (s[1] == '?') + fputs_filtered + (float_format_names[GET_FIELD (insn, 20, 20)], info); + else + (*info->fprintf_func) + (info->stream, "%s ", + float_format_names[GET_FIELD (insn, 20, 20)]); + break; + + case 'J': + fput_const (extract_14 (insn), info); + break; + + case '#': + { + int sign = GET_FIELD (insn, 31, 31); + int imm10 = GET_FIELD (insn, 18, 27); + int disp; + + if (sign) + disp = (-1 << 10) | imm10; + else + disp = imm10; + + disp <<= 3; + fput_const (disp, info); + break; + } + case 'K': + case 'd': + { + int sign = GET_FIELD (insn, 31, 31); + int imm11 = GET_FIELD (insn, 18, 28); + int disp; + + if (sign) + disp = (-1 << 11) | imm11; + else + disp = imm11; + + disp <<= 2; + fput_const (disp, info); + break; + } + + case '>': + case 'y': + { + /* 16-bit long disp., PA2.0 wide only. */ + int disp = extract_16 (insn); + disp &= ~3; + fput_const (disp, info); + break; + } + + case '&': + { + /* 16-bit long disp., PA2.0 wide only. */ + int disp = extract_16 (insn); + disp &= ~7; + fput_const (disp, info); + break; + } + + case '_': + break; /* Dealt with by '{' */ + + case '{': + { + int sub = GET_FIELD (insn, 14, 16); + int df = GET_FIELD (insn, 17, 18); + int sf = GET_FIELD (insn, 19, 20); + const char * const * source = float_format_names; + const char * const * dest = float_format_names; + char *t = ""; + + if (sub == 4) + { + fputs_filtered (",UND ", info); + break; + } + if ((sub & 3) == 3) + t = ",t"; + if ((sub & 3) == 1) + source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names; + if (sub & 2) + dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names; + + (*info->fprintf_func) (info->stream, "%s%s%s ", + t, source[sf], dest[df]); + break; + } + + case 'm': + { + int y = GET_FIELD (insn, 16, 18); + + if (y != 1) + fput_const ((y ^ 1) - 1, info); + } + break; + + case 'h': + { + int cbit; + + cbit = GET_FIELD (insn, 16, 18); + + if (cbit > 0) + (*info->fprintf_func) (info->stream, ",%d", cbit - 1); + break; + } + + case '=': + { + int cond = GET_FIELD (insn, 27, 31); + + switch (cond) + { + case 0: fputs_filtered (" ", info); break; + case 1: fputs_filtered ("acc ", info); break; + case 2: fputs_filtered ("rej ", info); break; + case 5: fputs_filtered ("acc8 ", info); break; + case 6: fputs_filtered ("rej8 ", info); break; + case 9: fputs_filtered ("acc6 ", info); break; + case 13: fputs_filtered ("acc4 ", info); break; + case 17: fputs_filtered ("acc2 ", info); break; + default: break; + } + break; + } + + case 'X': + (*info->print_address_func) + (memaddr + 8 + extract_22 (insn), info); + break; + case 'L': + fputs_filtered (",rp", info); + break; + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + return sizeof (insn); + } + } + (*info->fprintf_func) (info->stream, "#%8x", insn); + return sizeof (insn); +} diff --git a/external/gpl3/gdb/dist/opcodes/i370-dis.c b/external/gpl3/gdb/dist/opcodes/i370-dis.c new file mode 100644 index 000000000000..98c110bcdfaa --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i370-dis.c @@ -0,0 +1,161 @@ +/* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions + Copyright 1994, 2000, 2003, 2005, 2007 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support by Linas Vepstas + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/i370.h" + +/* This file provides several disassembler functions, all of which use + the disassembler interface defined in dis-asm.h. */ + +int +print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[8]; + int status; + i370_insn_t insn; + const struct i370_opcode *opcode; + const struct i370_opcode *opcode_end; + + status = (*info->read_memory_func) (memaddr, buffer, 6, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Cast the bytes into the insn (in a host-endian indep way). */ + insn.i[0] = (buffer[0] << 24) & 0xff000000; + insn.i[0] |= (buffer[1] << 16) & 0xff0000; + insn.i[0] |= (buffer[2] << 8) & 0xff00; + insn.i[0] |= buffer[3] & 0xff; + insn.i[1] = (buffer[4] << 24) & 0xff000000; + insn.i[1] |= (buffer[5] << 16) & 0xff0000; + + /* Find the first match in the opcode table. We could speed this up + a bit by doing a binary search on the major opcode. */ + opcode_end = i370_opcodes + i370_num_opcodes; + for (opcode = i370_opcodes; opcode < opcode_end; opcode++) + { + const unsigned char *opindex; + const struct i370_operand *operand; + i370_insn_t masked; + int invalid; + + /* Mask off operands, and look for a match ... */ + masked = insn; + if (2 == opcode->len) + { + masked.i[0] >>= 16; + masked.i[0] &= 0xffff; + } + masked.i[0] &= opcode->mask.i[0]; + if (masked.i[0] != opcode->opcode.i[0]) + continue; + + if (6 == opcode->len) + { + masked.i[1] &= opcode->mask.i[1]; + if (masked.i[1] != opcode->opcode.i[1]) + continue; + } + + /* Found a match. adjust a tad. */ + if (2 == opcode->len) + { + insn.i[0] >>= 16; + insn.i[0] &= 0xffff; + } + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = i370_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, &invalid); + } + if (invalid) + continue; + + /* The instruction is valid. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + + /* Now extract and print the operands. */ + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + long value; + + operand = i370_operands + *opindex; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, (int *) NULL); + else + value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1); + + /* Print the operand as directed by the flags. */ + if ((operand->flags & I370_OPERAND_OPTIONAL) != 0) + { + if (value) + (*info->fprintf_func) (info->stream, "(r%ld)", value); + } + else if ((operand->flags & I370_OPERAND_SBASE) != 0) + { + (*info->fprintf_func) (info->stream, "(r%ld)", value); + } + else if ((operand->flags & I370_OPERAND_INDEX) != 0) + { + if (value) + (*info->fprintf_func) (info->stream, "(r%ld,", value); + else + (*info->fprintf_func) (info->stream, "(,"); + } + else if ((operand->flags & I370_OPERAND_LENGTH) != 0) + { + (*info->fprintf_func) (info->stream, "(%ld,", value); + } + else if ((operand->flags & I370_OPERAND_BASE) != 0) + (*info->fprintf_func) (info->stream, "r%ld)", value); + else if ((operand->flags & I370_OPERAND_GPR) != 0) + (*info->fprintf_func) (info->stream, "r%ld,", value); + else if ((operand->flags & I370_OPERAND_FPR) != 0) + (*info->fprintf_func) (info->stream, "f%ld,", value); + else if ((operand->flags & I370_OPERAND_RELATIVE) != 0) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, " %ld, ", value); + } + + return opcode->len; + } + + /* We could not find a match. */ + (*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]); + + return 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/i370-opc.c b/external/gpl3/gdb/dist/opcodes/i370-opc.c new file mode 100644 index 000000000000..e684ff4d6f83 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i370-opc.c @@ -0,0 +1,936 @@ +/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list + Copyright 1994, 1999, 2000, 2001, 2003, 2005, 2007 + Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support by Linas Vepstas 1998, 1999 + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/i370.h" + +/* This file holds the i370 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* The functions used to insert and extract complicated operands. */ + +static i370_insn_t +insert_ss_b2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static i370_insn_t +insert_ss_d2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xfff) << 16; + return insn; +} + +static i370_insn_t +insert_rxf_r3 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static long +extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>28) & 0xf; +} + +static long +extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>16) & 0xfff; +} + +static long +extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>28) & 0xf; +} + +/* The operands table. + The fields are bits, shift, insert, extract, flags, name. + The types: + I370_OPERAND_GPR register, must name a register, must be present + I370_OPERAND_RELATIVE displacement or legnth field, must be present + I370_OPERAND_BASE base register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_INDEX index register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */ + +const struct i370_operand i370_operands[] = +{ + /* The zero index is used to indicate the end of the list of + operands. */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, "unused" }, + + /* The R1 register field in an RR form instruction. */ +#define RR_R1 (UNUSED + 1) +#define RR_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" }, + + /* The R2 register field in an RR form instruction. */ +#define RR_R2 (RR_R1 + 1) +#define RR_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" }, + + /* The I field in an RR form SVC-style instruction. */ +#define RR_I (RR_R2 + 1) +#define RR_I_MASK (0xff) + { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" }, + + /* The R1 register field in an RRE form instruction. */ +#define RRE_R1 (RR_I + 1) +#define RRE_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" }, + + /* The R2 register field in an RRE form instruction. */ +#define RRE_R2 (RRE_R1 + 1) +#define RRE_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" }, + + /* The R1 register field in an RRF form instruction. */ +#define RRF_R1 (RRE_R2 + 1) +#define RRF_R1_MASK (0xf << 4) + { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" }, + + /* The R2 register field in an RRF form instruction. */ +#define RRF_R2 (RRF_R1 + 1) +#define RRF_R2_MASK (0xf) + { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" }, + + /* The R3 register field in an RRF form instruction. */ +#define RRF_R3 (RRF_R2 + 1) +#define RRF_R3_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" }, + + /* The R1 register field in an RX or RS form instruction. */ +#define RX_R1 (RRF_R3 + 1) +#define RX_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" }, + + /* The X2 index field in an RX form instruction. */ +#define RX_X2 (RX_R1 + 1) +#define RX_X2_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"}, + + /* The B2 base field in an RX form instruction. */ +#define RX_B2 (RX_X2 + 1) +#define RX_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"}, + + /* The D2 displacement field in an RX form instruction. */ +#define RX_D2 (RX_B2 + 1) +#define RX_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"}, + + /* The R3 register field in an RXF form instruction. */ +#define RXF_R3 (RX_D2 + 1) +#define RXF_R3_MASK (0xf << 12) + { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" }, + + /* The D2 displacement field in an RS form instruction. */ +#define RS_D2 (RXF_R3 + 1) +#define RS_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"}, + + /* The R3 register field in an RS form instruction. */ +#define RS_R3 (RS_D2 + 1) +#define RS_R3_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" }, + + /* The B2 base field in an RS form instruction. */ +#define RS_B2 (RS_R3 + 1) +#define RS_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"}, + + /* The optional B2 base field in an RS form instruction. */ + /* Note that this field will almost always be absent */ +#define RS_B2_OPT (RS_B2 + 1) +#define RS_B2_OPT_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"}, + + /* The R1 register field in an RSI form instruction. */ +#define RSI_R1 (RS_B2_OPT + 1) +#define RSI_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" }, + + /* The R3 register field in an RSI form instruction. */ +#define RSI_R3 (RSI_R1 + 1) +#define RSI_R3_MASK (0xf << 16) + { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" }, + + /* The I2 immediate field in an RSI form instruction. */ +#define RSI_I2 (RSI_R3 + 1) +#define RSI_I2_MASK (0xffff) + { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" }, + + /* The R1 register field in an RI form instruction. */ +#define RI_R1 (RSI_I2 + 1) +#define RI_R1_MASK (0xf << 20) + { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" }, + + /* The I2 immediate field in an RI form instruction. */ +#define RI_I2 (RI_R1 + 1) +#define RI_I2_MASK (0xffff) + { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" }, + + /* The I2 index field in an SI form instruction. */ +#define SI_I2 (RI_I2 + 1) +#define SI_I2_MASK (0xff << 16) + { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"}, + + /* The B1 base register field in an SI form instruction. */ +#define SI_B1 (SI_I2 + 1) +#define SI_B1_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" }, + + /* The D1 displacement field in an SI form instruction. */ +#define SI_D1 (SI_B1 + 1) +#define SI_D1_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" }, + + /* The B2 base register field in an S form instruction. */ +#define S_B2 (SI_D1 + 1) +#define S_B2_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" }, + + /* The D2 displacement field in an S form instruction. */ +#define S_D2 (S_B2 + 1) +#define S_D2_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" }, + + /* The L length field in an SS form instruction. */ +#define SS_L (S_D2 + 1) +#define SS_L_MASK (0xffff<<16) + { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" }, + + /* The B1 base register field in an SS form instruction. */ +#define SS_B1 (SS_L + 1) +#define SS_B1_MASK (0xf << 12) + { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" }, + + /* The D1 displacement field in an SS form instruction. */ +#define SS_D1 (SS_B1 + 1) +#define SS_D1_MASK (0xfff) + { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" }, + + /* The B2 base register field in an SS form instruction. */ +#define SS_B2 (SS_D1 + 1) +#define SS_B2_MASK (0xf << 12) + { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" }, + + /* The D2 displacement field in an SS form instruction. */ +#define SS_D2 (SS_B2 + 1) +#define SS_D2_MASK (0xfff) + { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" }, + +}; + + +/* Macros used to form opcodes. */ + +/* The short-instruction opcode. */ +#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8) +#define OPS_MASK OPS (0xff) + +/* the extended instruction opcode */ +#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24) +#define XOPS_MASK XOPS (0xff) + +/* the S instruction opcode */ +#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16) +#define SOPS_MASK SOPS (0xffff) + +/* the E instruction opcode */ +#define EOPS(x) (((unsigned short) (x)) & 0xffff) +#define EOPS_MASK EOPS (0xffff) + +/* the RI instruction opcode */ +#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \ + ((((unsigned short) (x)) & 0x00f) << 16)) +#define ROPS_MASK ROPS (0xfff) + + +/* An E form instruction. */ +#define E(op) (EOPS (op)) +#define E_MASK E (0xffff) + +/* An RR form instruction. */ +#define RR(op, r1, r2) \ + (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) + +#define RR_MASK RR (0xff, 0x0, 0x0) + +/* An SVC-style instruction. */ +#define SVC(op, i) \ + (OPS (op) | (((unsigned short) (i)) & 0xff)) + +#define SVC_MASK SVC (0xff, 0x0) + +/* An RRE form instruction. */ +#define RRE(op, r1, r2) \ + (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) + +#define RRE_MASK RRE (0xffff, 0x0, 0x0) + +/* An RRF form instruction. */ +#define RRF(op, r3, r1, r2) \ + (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \ + ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) + +#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) + +/* An RX form instruction. */ +#define RX(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) + +#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) + +/* An RXE form instruction high word. */ +#define RXEH(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) + +#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) + +/* An RXE form instruction low word. */ +#define RXEL(op) \ + ((((unsigned short) (op)) & 0xff) << 16 ) + +#define RXEL_MASK RXEL (0xff) + +/* An RXF form instruction high word. */ +#define RXFH(op, r1, x2, b2, d2) \ + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) + +#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) + +/* An RXF form instruction low word. */ +#define RXFL(op, r3) \ + (((((unsigned short) (r3)) & 0xf) << 28 ) | \ + ((((unsigned short) (op)) & 0xff) << 16 )) + +#define RXFL_MASK RXFL (0xff, 0) + +/* An RS form instruction. */ +#define RS(op, r1, b3, b2, d2) \ + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (b3)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) + +#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) + +/* An RSI form instruction. */ +#define RSI(op, r1, r3, i2) \ + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (r3)) & 0xf) << 16) | \ + ((((unsigned short) (i2)) & 0xffff))) + +#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) + +/* An RI form instruction. */ +#define RI(op, r1, i2) \ + (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (i2)) & 0xffff))) + +#define RI_MASK RI (0xfff, 0x0, 0x0) + +/* An SI form instruction. */ +#define SI(op, i2, b1, d1) \ + (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \ + ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) + +#define SI_MASK SI (0xff, 0x0, 0x0, 0x0) + +/* An S form instruction. */ +#define S(op, b2, d2) \ + (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \ + ((((unsigned short)(d2)) & 0xfff))) + +#define S_MASK S (0xffff, 0x0, 0x0) + +/* An SS form instruction high word. */ +#define SSH(op, l, b1, d1) \ + (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \ + ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) + +/* An SS form instruction low word. */ +#define SSL(b2, d2) \ + ( ((((unsigned short) (b1)) & 0xf) << 28) | \ + ((((unsigned short) (d1)) & 0xfff) << 16 )) + +#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) + +/* An SSE form instruction high word. */ +#define SSEH(op, b1, d1) \ + (SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) + +/* An SSE form instruction low word. */ +#define SSEL(b2, d2) \ + ( ((((unsigned short) (b1)) & 0xf) << 28) | \ + ((((unsigned short) (d1)) & 0xfff) << 16 )) + +#define SSE_MASK SSEH (0xffff, 0x0, 0x0) + + +/* Smaller names for the flags so each entry in the opcodes table will + fit on a single line. These flags are set up so that e.g. IXA means + the insn is supported on the 370/XA or newer architecture. + Note that 370 or older obsolete insn's are not supported ... */ +#define IBF I370_OPCODE_ESA390_BF +#define IBS I370_OPCODE_ESA390_BS +#define ICK I370_OPCODE_ESA390_CK +#define ICM I370_OPCODE_ESA390_CM +#define IFX I370_OPCODE_ESA390_FX +#define IHX I370_OPCODE_ESA390_HX +#define IIR I370_OPCODE_ESA390_IR +#define IMI I370_OPCODE_ESA390_MI +#define IPC I370_OPCODE_ESA390_PC +#define IPL I370_OPCODE_ESA390_PL +#define IQR I370_OPCODE_ESA390_QR +#define IRP I370_OPCODE_ESA390_RP +#define ISA I370_OPCODE_ESA390_SA +#define ISG I370_OPCODE_ESA390_SG +#define ISR I370_OPCODE_ESA390_SR +#define ITR I370_OPCODE_ESA390_SR +#define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390 +#define IESA I390 | I370_OPCODE_ESA370 +#define IXA IESA | I370_OPCODE_370_XA +#define I370 IXA | I370_OPCODE_370 +#define I360 I370 | I370_OPCODE_360 + + +/* The opcode table. + + The format of the opcode table is: + + NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + FLAGS are flags indicated what processors support the instruction. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct i370_opcode i370_opcodes[] = +{ +/* E form instructions */ +{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} }, + +{ "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} }, +{ "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} }, + +/* RR form instructions */ +{ "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} }, +{ "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} }, +{ "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, +{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, + +/* Unusual RR formats. */ +{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} }, + +/* RRE form instructions. */ +{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} }, +{ "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} }, +{ "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} }, +{ "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} }, +{ "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} }, +{ "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} }, +{ "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} }, +{ "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, +{ "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} }, +{ "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} }, +{ "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} }, +{ "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} }, +{ "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, +{ "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} }, +{ "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} }, +{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, +{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, + +/* RRF form instructions. */ +{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, +{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, +{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, + +/* RX form instructions. */ +{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, + +/* RXE form instructions. */ +{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, +{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, + +/* RXF form instructions. */ +{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, +{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, + +/* RS form instructions. */ +{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, +{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, + +/* RS form instructions with blank R3 and optional B2 (shift left/right). */ +{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, +{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, + +/* RSI form instructions. */ +{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, +{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, + +/* RI form instructions. */ +{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, +{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, + +/* SI form instructions. */ +{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, +{ "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} }, +{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, +{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, + +/* S form instructions. */ +{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} }, +{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} }, +{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} }, +{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, +{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} }, +{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, +{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} }, +{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, +{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, + +/* SS form instructions. */ +{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, +{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, + +/* SSE form instructions. */ +{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, +{ "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, + +/* */ +}; + +const int i370_num_opcodes = + sizeof (i370_opcodes) / sizeof (i370_opcodes[0]); + +/* The macro table. This is only used by the assembler. */ + +const struct i370_macro i370_macros[] = +{ +{ "b", 1, I370, "bc 15,%0" }, +{ "br", 1, I370, "bcr 15,%0" }, + +{ "nop", 1, I370, "bc 0,%0" }, +{ "nopr", 1, I370, "bcr 0,%0" }, + +{ "bh", 1, I370, "bc 2,%0" }, +{ "bhr", 1, I370, "bcr 2,%0" }, +{ "bl", 1, I370, "bc 4,%0" }, +{ "blr", 1, I370, "bcr 4,%0" }, +{ "be", 1, I370, "bc 8,%0" }, +{ "ber", 1, I370, "bcr 8,%0" }, + +{ "bnh", 1, I370, "bc 13,%0" }, +{ "bnhr", 1, I370, "bcr 13,%0" }, +{ "bnl", 1, I370, "bc 11,%0" }, +{ "bnlr", 1, I370, "bcr 11,%0" }, +{ "bne", 1, I370, "bc 7,%0" }, +{ "bner", 1, I370, "bcr 7,%0" }, + +{ "bp", 1, I370, "bc 2,%0" }, +{ "bpr", 1, I370, "bcr 2,%0" }, +{ "bm", 1, I370, "bc 4,%0" }, +{ "bmr", 1, I370, "bcr 4,%0" }, +{ "bz", 1, I370, "bc 8,%0" }, +{ "bzr", 1, I370, "bcr 8,%0" }, +{ "bo", 1, I370, "bc 1,%0" }, +{ "bor", 1, I370, "bcr 1,%0" }, + +{ "bnp", 1, I370, "bc 13,%0" }, +{ "bnpr", 1, I370, "bcr 13,%0" }, +{ "bnm", 1, I370, "bc 11,%0" }, +{ "bnmr", 1, I370, "bcr 11,%0" }, +{ "bnz", 1, I370, "bc 7,%0" }, +{ "bnzr", 1, I370, "bcr 7,%0" }, +{ "bno", 1, I370, "bc 14,%0" }, +{ "bnor", 1, I370, "bcr 14,%0" }, + +{ "sync", 0, I370, "bcr 15,0" }, + +}; + +const int i370_num_macros = + sizeof (i370_macros) / sizeof (i370_macros[0]); diff --git a/external/gpl3/gdb/dist/opcodes/i386-dis.c b/external/gpl3/gdb/dist/opcodes/i386-dis.c new file mode 100644 index 000000000000..9834098ea552 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-dis.c @@ -0,0 +1,15204 @@ +/* Print i386 instructions for GDB, the GNU debugger. + Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) + July 1988 + modified by John Hassey (hassey@dg-rtp.dg.com) + x86-64 support added by Jan Hubicka (jh@suse.cz) + VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ + +/* The main tables describing the instructions is essentially a copy + of the "Opcode Map" chapter (Appendix A) of the Intel 80386 + Programmers Manual. Usually, there is a capital letter, followed + by a small letter. The capital letter tell the addressing mode, + and the small letter tells about the operand size. Refer to + the Intel manual for details. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opintl.h" +#include "opcode/i386.h" +#include "libiberty.h" + +#include + +static int print_insn (bfd_vma, disassemble_info *); +static void dofloat (int); +static void OP_ST (int, int); +static void OP_STi (int, int); +static int putop (const char *, int); +static void oappend (const char *); +static void append_seg (void); +static void OP_indirE (int, int); +static void print_operand_value (char *, int, bfd_vma); +static void OP_E_register (int, int); +static void OP_E_memory (int, int); +static void print_displacement (char *, bfd_vma); +static void OP_E (int, int); +static void OP_G (int, int); +static bfd_vma get64 (void); +static bfd_signed_vma get32 (void); +static bfd_signed_vma get32s (void); +static int get16 (void); +static void set_op (bfd_vma, int); +static void OP_Skip_MODRM (int, int); +static void OP_REG (int, int); +static void OP_IMREG (int, int); +static void OP_I (int, int); +static void OP_I64 (int, int); +static void OP_sI (int, int); +static void OP_J (int, int); +static void OP_SEG (int, int); +static void OP_DIR (int, int); +static void OP_OFF (int, int); +static void OP_OFF64 (int, int); +static void ptr_reg (int, int); +static void OP_ESreg (int, int); +static void OP_DSreg (int, int); +static void OP_C (int, int); +static void OP_D (int, int); +static void OP_T (int, int); +static void OP_R (int, int); +static void OP_MMX (int, int); +static void OP_XMM (int, int); +static void OP_EM (int, int); +static void OP_EX (int, int); +static void OP_EMC (int,int); +static void OP_MXC (int,int); +static void OP_MS (int, int); +static void OP_XS (int, int); +static void OP_M (int, int); +static void OP_VEX (int, int); +static void OP_EX_Vex (int, int); +static void OP_EX_VexW (int, int); +static void OP_EX_VexImmW (int, int); +static void OP_XMM_Vex (int, int); +static void OP_XMM_VexW (int, int); +static void OP_REG_VexI4 (int, int); +static void PCLMUL_Fixup (int, int); +static void VEXI4_Fixup (int, int); +static void VZERO_Fixup (int, int); +static void VCMP_Fixup (int, int); +static void OP_0f07 (int, int); +static void OP_Monitor (int, int); +static void OP_Mwait (int, int); +static void NOP_Fixup1 (int, int); +static void NOP_Fixup2 (int, int); +static void OP_3DNowSuffix (int, int); +static void CMP_Fixup (int, int); +static void BadOp (void); +static void REP_Fixup (int, int); +static void CMPXCHG8B_Fixup (int, int); +static void XMM_Fixup (int, int); +static void CRC32_Fixup (int, int); +static void FXSAVE_Fixup (int, int); +static void OP_LWPCB_E (int, int); +static void OP_LWP_E (int, int); +static void OP_Vex_2src_1 (int, int); +static void OP_Vex_2src_2 (int, int); + +static void MOVBE_Fixup (int, int); + +struct dis_private { + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAX_MNEM_SIZE]; + bfd_vma insn_start; + int orig_sizeflag; + jmp_buf bailout; +}; + +enum address_mode +{ + mode_16bit, + mode_32bit, + mode_64bit +}; + +enum address_mode address_mode; + +/* Flags for the prefixes for the current instruction. See below. */ +static int prefixes; + +/* REX prefix the current instruction. See below. */ +static int rex; +/* Bits of REX we've already used. */ +static int rex_used; +/* REX bits in original REX prefix ignored. */ +static int rex_ignored; +/* Mark parts used in the REX prefix. When we are testing for + empty prefix (for 8bit register REX extension), just mask it + out. Otherwise test for REX bit is excuse for existence of REX + only in case value is nonzero. */ +#define USED_REX(value) \ + { \ + if (value) \ + { \ + if ((rex & value)) \ + rex_used |= (value) | REX_OPCODE; \ + } \ + else \ + rex_used |= REX_OPCODE; \ + } + +/* Flags for prefixes which we somehow handled when printing the + current instruction. */ +static int used_prefixes; + +/* Flags stored in PREFIXES. */ +#define PREFIX_REPZ 1 +#define PREFIX_REPNZ 2 +#define PREFIX_LOCK 4 +#define PREFIX_CS 8 +#define PREFIX_SS 0x10 +#define PREFIX_DS 0x20 +#define PREFIX_ES 0x40 +#define PREFIX_FS 0x80 +#define PREFIX_GS 0x100 +#define PREFIX_DATA 0x200 +#define PREFIX_ADDR 0x400 +#define PREFIX_FWAIT 0x800 + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + struct dis_private *priv = (struct dis_private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + if (addr <= priv->the_buffer + MAX_MNEM_SIZE) + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + else + status = -1; + if (status != 0) + { + /* If we did manage to read at least one byte, then + print_insn_i386 will do something sensible. Otherwise, print + an error. We do that here because this is where we know + STATUS. */ + if (priv->max_fetched == priv->the_buffer) + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +#define XX { NULL, 0 } +#define Bad_Opcode NULL, { { NULL, 0 } } + +#define Eb { OP_E, b_mode } +#define EbS { OP_E, b_swap_mode } +#define Ev { OP_E, v_mode } +#define EvS { OP_E, v_swap_mode } +#define Ed { OP_E, d_mode } +#define Edq { OP_E, dq_mode } +#define Edqw { OP_E, dqw_mode } +#define Edqb { OP_E, dqb_mode } +#define Edqd { OP_E, dqd_mode } +#define Eq { OP_E, q_mode } +#define indirEv { OP_indirE, stack_v_mode } +#define indirEp { OP_indirE, f_mode } +#define stackEv { OP_E, stack_v_mode } +#define Em { OP_E, m_mode } +#define Ew { OP_E, w_mode } +#define M { OP_M, 0 } /* lea, lgdt, etc. */ +#define Ma { OP_M, a_mode } +#define Mb { OP_M, b_mode } +#define Md { OP_M, d_mode } +#define Mo { OP_M, o_mode } +#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ +#define Mq { OP_M, q_mode } +#define Mx { OP_M, x_mode } +#define Mxmm { OP_M, xmm_mode } +#define Gb { OP_G, b_mode } +#define Gv { OP_G, v_mode } +#define Gd { OP_G, d_mode } +#define Gdq { OP_G, dq_mode } +#define Gm { OP_G, m_mode } +#define Gw { OP_G, w_mode } +#define Rd { OP_R, d_mode } +#define Rm { OP_R, m_mode } +#define Ib { OP_I, b_mode } +#define sIb { OP_sI, b_mode } /* sign extened byte */ +#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ +#define Iv { OP_I, v_mode } +#define sIv { OP_sI, v_mode } +#define Iq { OP_I, q_mode } +#define Iv64 { OP_I64, v_mode } +#define Iw { OP_I, w_mode } +#define I1 { OP_I, const_1_mode } +#define Jb { OP_J, b_mode } +#define Jv { OP_J, v_mode } +#define Cm { OP_C, m_mode } +#define Dm { OP_D, m_mode } +#define Td { OP_T, d_mode } +#define Skip_MODRM { OP_Skip_MODRM, 0 } + +#define RMeAX { OP_REG, eAX_reg } +#define RMeBX { OP_REG, eBX_reg } +#define RMeCX { OP_REG, eCX_reg } +#define RMeDX { OP_REG, eDX_reg } +#define RMeSP { OP_REG, eSP_reg } +#define RMeBP { OP_REG, eBP_reg } +#define RMeSI { OP_REG, eSI_reg } +#define RMeDI { OP_REG, eDI_reg } +#define RMrAX { OP_REG, rAX_reg } +#define RMrBX { OP_REG, rBX_reg } +#define RMrCX { OP_REG, rCX_reg } +#define RMrDX { OP_REG, rDX_reg } +#define RMrSP { OP_REG, rSP_reg } +#define RMrBP { OP_REG, rBP_reg } +#define RMrSI { OP_REG, rSI_reg } +#define RMrDI { OP_REG, rDI_reg } +#define RMAL { OP_REG, al_reg } +#define RMCL { OP_REG, cl_reg } +#define RMDL { OP_REG, dl_reg } +#define RMBL { OP_REG, bl_reg } +#define RMAH { OP_REG, ah_reg } +#define RMCH { OP_REG, ch_reg } +#define RMDH { OP_REG, dh_reg } +#define RMBH { OP_REG, bh_reg } +#define RMAX { OP_REG, ax_reg } +#define RMDX { OP_REG, dx_reg } + +#define eAX { OP_IMREG, eAX_reg } +#define eBX { OP_IMREG, eBX_reg } +#define eCX { OP_IMREG, eCX_reg } +#define eDX { OP_IMREG, eDX_reg } +#define eSP { OP_IMREG, eSP_reg } +#define eBP { OP_IMREG, eBP_reg } +#define eSI { OP_IMREG, eSI_reg } +#define eDI { OP_IMREG, eDI_reg } +#define AL { OP_IMREG, al_reg } +#define CL { OP_IMREG, cl_reg } +#define DL { OP_IMREG, dl_reg } +#define BL { OP_IMREG, bl_reg } +#define AH { OP_IMREG, ah_reg } +#define CH { OP_IMREG, ch_reg } +#define DH { OP_IMREG, dh_reg } +#define BH { OP_IMREG, bh_reg } +#define AX { OP_IMREG, ax_reg } +#define DX { OP_IMREG, dx_reg } +#define zAX { OP_IMREG, z_mode_ax_reg } +#define indirDX { OP_IMREG, indir_dx_reg } + +#define Sw { OP_SEG, w_mode } +#define Sv { OP_SEG, v_mode } +#define Ap { OP_DIR, 0 } +#define Ob { OP_OFF64, b_mode } +#define Ov { OP_OFF64, v_mode } +#define Xb { OP_DSreg, eSI_reg } +#define Xv { OP_DSreg, eSI_reg } +#define Xz { OP_DSreg, eSI_reg } +#define Yb { OP_ESreg, eDI_reg } +#define Yv { OP_ESreg, eDI_reg } +#define DSBX { OP_DSreg, eBX_reg } + +#define es { OP_REG, es_reg } +#define ss { OP_REG, ss_reg } +#define cs { OP_REG, cs_reg } +#define ds { OP_REG, ds_reg } +#define fs { OP_REG, fs_reg } +#define gs { OP_REG, gs_reg } + +#define MX { OP_MMX, 0 } +#define XM { OP_XMM, 0 } +#define XMScalar { OP_XMM, scalar_mode } +#define XMM { OP_XMM, xmm_mode } +#define EM { OP_EM, v_mode } +#define EMS { OP_EM, v_swap_mode } +#define EMd { OP_EM, d_mode } +#define EMx { OP_EM, x_mode } +#define EXw { OP_EX, w_mode } +#define EXd { OP_EX, d_mode } +#define EXdScalar { OP_EX, d_scalar_mode } +#define EXdS { OP_EX, d_swap_mode } +#define EXq { OP_EX, q_mode } +#define EXqScalar { OP_EX, q_scalar_mode } +#define EXqScalarS { OP_EX, q_scalar_swap_mode } +#define EXqS { OP_EX, q_swap_mode } +#define EXx { OP_EX, x_mode } +#define EXxS { OP_EX, x_swap_mode } +#define EXxmm { OP_EX, xmm_mode } +#define EXxmmq { OP_EX, xmmq_mode } +#define EXymmq { OP_EX, ymmq_mode } +#define EXVexWdq { OP_EX, vex_w_dq_mode } +#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } +#define MS { OP_MS, v_mode } +#define XS { OP_XS, v_mode } +#define EMCq { OP_EMC, q_mode } +#define MXC { OP_MXC, 0 } +#define OPSUF { OP_3DNowSuffix, 0 } +#define CMP { CMP_Fixup, 0 } +#define XMM0 { XMM_Fixup, 0 } +#define FXSAVE { FXSAVE_Fixup, 0 } +#define Vex_2src_1 { OP_Vex_2src_1, 0 } +#define Vex_2src_2 { OP_Vex_2src_2, 0 } + +#define Vex { OP_VEX, vex_mode } +#define VexScalar { OP_VEX, vex_scalar_mode } +#define Vex128 { OP_VEX, vex128_mode } +#define Vex256 { OP_VEX, vex256_mode } +#define VexGdq { OP_VEX, dq_mode } +#define VexI4 { VEXI4_Fixup, 0} +#define EXdVex { OP_EX_Vex, d_mode } +#define EXdVexS { OP_EX_Vex, d_swap_mode } +#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } +#define EXqVex { OP_EX_Vex, q_mode } +#define EXqVexS { OP_EX_Vex, q_swap_mode } +#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } +#define EXVexW { OP_EX_VexW, x_mode } +#define EXdVexW { OP_EX_VexW, d_mode } +#define EXqVexW { OP_EX_VexW, q_mode } +#define EXVexImmW { OP_EX_VexImmW, x_mode } +#define XMVex { OP_XMM_Vex, 0 } +#define XMVexScalar { OP_XMM_Vex, scalar_mode } +#define XMVexW { OP_XMM_VexW, 0 } +#define XMVexI4 { OP_REG_VexI4, x_mode } +#define PCLMUL { PCLMUL_Fixup, 0 } +#define VZERO { VZERO_Fixup, 0 } +#define VCMP { VCMP_Fixup, 0 } + +/* Used handle "rep" prefix for string instructions. */ +#define Xbr { REP_Fixup, eSI_reg } +#define Xvr { REP_Fixup, eSI_reg } +#define Ybr { REP_Fixup, eDI_reg } +#define Yvr { REP_Fixup, eDI_reg } +#define Yzr { REP_Fixup, eDI_reg } +#define indirDXr { REP_Fixup, indir_dx_reg } +#define ALr { REP_Fixup, al_reg } +#define eAXr { REP_Fixup, eAX_reg } + +#define cond_jump_flag { NULL, cond_jump_mode } +#define loop_jcxz_flag { NULL, loop_jcxz_mode } + +/* bits in sizeflag */ +#define SUFFIX_ALWAYS 4 +#define AFLAG 2 +#define DFLAG 1 + +enum +{ + /* byte operand */ + b_mode = 1, + /* byte operand with operand swapped */ + b_swap_mode, + /* byte operand, sign extend like 'T' suffix */ + b_T_mode, + /* operand size depends on prefixes */ + v_mode, + /* operand size depends on prefixes with operand swapped */ + v_swap_mode, + /* word operand */ + w_mode, + /* double word operand */ + d_mode, + /* double word operand with operand swapped */ + d_swap_mode, + /* quad word operand */ + q_mode, + /* quad word operand with operand swapped */ + q_swap_mode, + /* ten-byte operand */ + t_mode, + /* 16-byte XMM or 32-byte YMM operand */ + x_mode, + /* 16-byte XMM or 32-byte YMM operand with operand swapped */ + x_swap_mode, + /* 16-byte XMM operand */ + xmm_mode, + /* 16-byte XMM or quad word operand */ + xmmq_mode, + /* 32-byte YMM or quad word operand */ + ymmq_mode, + /* d_mode in 32bit, q_mode in 64bit mode. */ + m_mode, + /* pair of v_mode operands */ + a_mode, + cond_jump_mode, + loop_jcxz_mode, + /* operand size depends on REX prefixes. */ + dq_mode, + /* registers like dq_mode, memory like w_mode. */ + dqw_mode, + /* 4- or 6-byte pointer operand */ + f_mode, + const_1_mode, + /* v_mode for stack-related opcodes. */ + stack_v_mode, + /* non-quad operand size depends on prefixes */ + z_mode, + /* 16-byte operand */ + o_mode, + /* registers like dq_mode, memory like b_mode. */ + dqb_mode, + /* registers like dq_mode, memory like d_mode. */ + dqd_mode, + /* normal vex mode */ + vex_mode, + /* 128bit vex mode */ + vex128_mode, + /* 256bit vex mode */ + vex256_mode, + /* operand size depends on the VEX.W bit. */ + vex_w_dq_mode, + + /* scalar, ignore vector length. */ + scalar_mode, + /* like d_mode, ignore vector length. */ + d_scalar_mode, + /* like d_swap_mode, ignore vector length. */ + d_scalar_swap_mode, + /* like q_mode, ignore vector length. */ + q_scalar_mode, + /* like q_swap_mode, ignore vector length. */ + q_scalar_swap_mode, + /* like vex_mode, ignore vector length. */ + vex_scalar_mode, + /* like vex_w_dq_mode, ignore vector length. */ + vex_scalar_w_dq_mode, + + es_reg, + cs_reg, + ss_reg, + ds_reg, + fs_reg, + gs_reg, + + eAX_reg, + eCX_reg, + eDX_reg, + eBX_reg, + eSP_reg, + eBP_reg, + eSI_reg, + eDI_reg, + + al_reg, + cl_reg, + dl_reg, + bl_reg, + ah_reg, + ch_reg, + dh_reg, + bh_reg, + + ax_reg, + cx_reg, + dx_reg, + bx_reg, + sp_reg, + bp_reg, + si_reg, + di_reg, + + rAX_reg, + rCX_reg, + rDX_reg, + rBX_reg, + rSP_reg, + rBP_reg, + rSI_reg, + rDI_reg, + + z_mode_ax_reg, + indir_dx_reg +}; + +enum +{ + FLOATCODE = 1, + USE_REG_TABLE, + USE_MOD_TABLE, + USE_RM_TABLE, + USE_PREFIX_TABLE, + USE_X86_64_TABLE, + USE_3BYTE_TABLE, + USE_XOP_8F_TABLE, + USE_VEX_C4_TABLE, + USE_VEX_C5_TABLE, + USE_VEX_LEN_TABLE, + USE_VEX_W_TABLE +}; + +#define FLOAT NULL, { { NULL, FLOATCODE } } + +#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } +#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) +#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) +#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) +#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) +#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) +#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) +#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) +#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) +#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) +#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) +#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) + +enum +{ + REG_80 = 0, + REG_81, + REG_82, + REG_8F, + REG_C0, + REG_C1, + REG_C6, + REG_C7, + REG_D0, + REG_D1, + REG_D2, + REG_D3, + REG_F6, + REG_F7, + REG_FE, + REG_FF, + REG_0F00, + REG_0F01, + REG_0F0D, + REG_0F18, + REG_0F71, + REG_0F72, + REG_0F73, + REG_0FA6, + REG_0FA7, + REG_0FAE, + REG_0FBA, + REG_0FC7, + REG_VEX_0F71, + REG_VEX_0F72, + REG_VEX_0F73, + REG_VEX_0FAE, + REG_VEX_0F38F3, + REG_XOP_LWPCB, + REG_XOP_LWP, + REG_XOP_TBM_01, + REG_XOP_TBM_02 +}; + +enum +{ + MOD_8D = 0, + MOD_0F01_REG_0, + MOD_0F01_REG_1, + MOD_0F01_REG_2, + MOD_0F01_REG_3, + MOD_0F01_REG_7, + MOD_0F12_PREFIX_0, + MOD_0F13, + MOD_0F16_PREFIX_0, + MOD_0F17, + MOD_0F18_REG_0, + MOD_0F18_REG_1, + MOD_0F18_REG_2, + MOD_0F18_REG_3, + MOD_0F20, + MOD_0F21, + MOD_0F22, + MOD_0F23, + MOD_0F24, + MOD_0F26, + MOD_0F2B_PREFIX_0, + MOD_0F2B_PREFIX_1, + MOD_0F2B_PREFIX_2, + MOD_0F2B_PREFIX_3, + MOD_0F51, + MOD_0F71_REG_2, + MOD_0F71_REG_4, + MOD_0F71_REG_6, + MOD_0F72_REG_2, + MOD_0F72_REG_4, + MOD_0F72_REG_6, + MOD_0F73_REG_2, + MOD_0F73_REG_3, + MOD_0F73_REG_6, + MOD_0F73_REG_7, + MOD_0FAE_REG_0, + MOD_0FAE_REG_1, + MOD_0FAE_REG_2, + MOD_0FAE_REG_3, + MOD_0FAE_REG_4, + MOD_0FAE_REG_5, + MOD_0FAE_REG_6, + MOD_0FAE_REG_7, + MOD_0FB2, + MOD_0FB4, + MOD_0FB5, + MOD_0FC7_REG_6, + MOD_0FC7_REG_7, + MOD_0FD7, + MOD_0FE7_PREFIX_2, + MOD_0FF0_PREFIX_3, + MOD_0F382A_PREFIX_2, + MOD_62_32BIT, + MOD_C4_32BIT, + MOD_C5_32BIT, + MOD_VEX_0F12_PREFIX_0, + MOD_VEX_0F13, + MOD_VEX_0F16_PREFIX_0, + MOD_VEX_0F17, + MOD_VEX_0F2B, + MOD_VEX_0F50, + MOD_VEX_0F71_REG_2, + MOD_VEX_0F71_REG_4, + MOD_VEX_0F71_REG_6, + MOD_VEX_0F72_REG_2, + MOD_VEX_0F72_REG_4, + MOD_VEX_0F72_REG_6, + MOD_VEX_0F73_REG_2, + MOD_VEX_0F73_REG_3, + MOD_VEX_0F73_REG_6, + MOD_VEX_0F73_REG_7, + MOD_VEX_0FAE_REG_2, + MOD_VEX_0FAE_REG_3, + MOD_VEX_0FD7_PREFIX_2, + MOD_VEX_0FE7_PREFIX_2, + MOD_VEX_0FF0_PREFIX_3, + MOD_VEX_0F3818_PREFIX_2, + MOD_VEX_0F3819_PREFIX_2, + MOD_VEX_0F381A_PREFIX_2, + MOD_VEX_0F382A_PREFIX_2, + MOD_VEX_0F382C_PREFIX_2, + MOD_VEX_0F382D_PREFIX_2, + MOD_VEX_0F382E_PREFIX_2, + MOD_VEX_0F382F_PREFIX_2 +}; + +enum +{ + RM_0F01_REG_0 = 0, + RM_0F01_REG_1, + RM_0F01_REG_2, + RM_0F01_REG_3, + RM_0F01_REG_7, + RM_0FAE_REG_5, + RM_0FAE_REG_6, + RM_0FAE_REG_7 +}; + +enum +{ + PREFIX_90 = 0, + PREFIX_0F10, + PREFIX_0F11, + PREFIX_0F12, + PREFIX_0F16, + PREFIX_0F2A, + PREFIX_0F2B, + PREFIX_0F2C, + PREFIX_0F2D, + PREFIX_0F2E, + PREFIX_0F2F, + PREFIX_0F51, + PREFIX_0F52, + PREFIX_0F53, + PREFIX_0F58, + PREFIX_0F59, + PREFIX_0F5A, + PREFIX_0F5B, + PREFIX_0F5C, + PREFIX_0F5D, + PREFIX_0F5E, + PREFIX_0F5F, + PREFIX_0F60, + PREFIX_0F61, + PREFIX_0F62, + PREFIX_0F6C, + PREFIX_0F6D, + PREFIX_0F6F, + PREFIX_0F70, + PREFIX_0F73_REG_3, + PREFIX_0F73_REG_7, + PREFIX_0F78, + PREFIX_0F79, + PREFIX_0F7C, + PREFIX_0F7D, + PREFIX_0F7E, + PREFIX_0F7F, + PREFIX_0FAE_REG_0, + PREFIX_0FAE_REG_1, + PREFIX_0FAE_REG_2, + PREFIX_0FAE_REG_3, + PREFIX_0FB8, + PREFIX_0FBC, + PREFIX_0FBD, + PREFIX_0FC2, + PREFIX_0FC3, + PREFIX_0FC7_REG_6, + PREFIX_0FD0, + PREFIX_0FD6, + PREFIX_0FE6, + PREFIX_0FE7, + PREFIX_0FF0, + PREFIX_0FF7, + PREFIX_0F3810, + PREFIX_0F3814, + PREFIX_0F3815, + PREFIX_0F3817, + PREFIX_0F3820, + PREFIX_0F3821, + PREFIX_0F3822, + PREFIX_0F3823, + PREFIX_0F3824, + PREFIX_0F3825, + PREFIX_0F3828, + PREFIX_0F3829, + PREFIX_0F382A, + PREFIX_0F382B, + PREFIX_0F3830, + PREFIX_0F3831, + PREFIX_0F3832, + PREFIX_0F3833, + PREFIX_0F3834, + PREFIX_0F3835, + PREFIX_0F3837, + PREFIX_0F3838, + PREFIX_0F3839, + PREFIX_0F383A, + PREFIX_0F383B, + PREFIX_0F383C, + PREFIX_0F383D, + PREFIX_0F383E, + PREFIX_0F383F, + PREFIX_0F3840, + PREFIX_0F3841, + PREFIX_0F3880, + PREFIX_0F3881, + PREFIX_0F38DB, + PREFIX_0F38DC, + PREFIX_0F38DD, + PREFIX_0F38DE, + PREFIX_0F38DF, + PREFIX_0F38F0, + PREFIX_0F38F1, + PREFIX_0F3A08, + PREFIX_0F3A09, + PREFIX_0F3A0A, + PREFIX_0F3A0B, + PREFIX_0F3A0C, + PREFIX_0F3A0D, + PREFIX_0F3A0E, + PREFIX_0F3A14, + PREFIX_0F3A15, + PREFIX_0F3A16, + PREFIX_0F3A17, + PREFIX_0F3A20, + PREFIX_0F3A21, + PREFIX_0F3A22, + PREFIX_0F3A40, + PREFIX_0F3A41, + PREFIX_0F3A42, + PREFIX_0F3A44, + PREFIX_0F3A60, + PREFIX_0F3A61, + PREFIX_0F3A62, + PREFIX_0F3A63, + PREFIX_0F3ADF, + PREFIX_VEX_0F10, + PREFIX_VEX_0F11, + PREFIX_VEX_0F12, + PREFIX_VEX_0F16, + PREFIX_VEX_0F2A, + PREFIX_VEX_0F2C, + PREFIX_VEX_0F2D, + PREFIX_VEX_0F2E, + PREFIX_VEX_0F2F, + PREFIX_VEX_0F51, + PREFIX_VEX_0F52, + PREFIX_VEX_0F53, + PREFIX_VEX_0F58, + PREFIX_VEX_0F59, + PREFIX_VEX_0F5A, + PREFIX_VEX_0F5B, + PREFIX_VEX_0F5C, + PREFIX_VEX_0F5D, + PREFIX_VEX_0F5E, + PREFIX_VEX_0F5F, + PREFIX_VEX_0F60, + PREFIX_VEX_0F61, + PREFIX_VEX_0F62, + PREFIX_VEX_0F63, + PREFIX_VEX_0F64, + PREFIX_VEX_0F65, + PREFIX_VEX_0F66, + PREFIX_VEX_0F67, + PREFIX_VEX_0F68, + PREFIX_VEX_0F69, + PREFIX_VEX_0F6A, + PREFIX_VEX_0F6B, + PREFIX_VEX_0F6C, + PREFIX_VEX_0F6D, + PREFIX_VEX_0F6E, + PREFIX_VEX_0F6F, + PREFIX_VEX_0F70, + PREFIX_VEX_0F71_REG_2, + PREFIX_VEX_0F71_REG_4, + PREFIX_VEX_0F71_REG_6, + PREFIX_VEX_0F72_REG_2, + PREFIX_VEX_0F72_REG_4, + PREFIX_VEX_0F72_REG_6, + PREFIX_VEX_0F73_REG_2, + PREFIX_VEX_0F73_REG_3, + PREFIX_VEX_0F73_REG_6, + PREFIX_VEX_0F73_REG_7, + PREFIX_VEX_0F74, + PREFIX_VEX_0F75, + PREFIX_VEX_0F76, + PREFIX_VEX_0F77, + PREFIX_VEX_0F7C, + PREFIX_VEX_0F7D, + PREFIX_VEX_0F7E, + PREFIX_VEX_0F7F, + PREFIX_VEX_0FC2, + PREFIX_VEX_0FC4, + PREFIX_VEX_0FC5, + PREFIX_VEX_0FD0, + PREFIX_VEX_0FD1, + PREFIX_VEX_0FD2, + PREFIX_VEX_0FD3, + PREFIX_VEX_0FD4, + PREFIX_VEX_0FD5, + PREFIX_VEX_0FD6, + PREFIX_VEX_0FD7, + PREFIX_VEX_0FD8, + PREFIX_VEX_0FD9, + PREFIX_VEX_0FDA, + PREFIX_VEX_0FDB, + PREFIX_VEX_0FDC, + PREFIX_VEX_0FDD, + PREFIX_VEX_0FDE, + PREFIX_VEX_0FDF, + PREFIX_VEX_0FE0, + PREFIX_VEX_0FE1, + PREFIX_VEX_0FE2, + PREFIX_VEX_0FE3, + PREFIX_VEX_0FE4, + PREFIX_VEX_0FE5, + PREFIX_VEX_0FE6, + PREFIX_VEX_0FE7, + PREFIX_VEX_0FE8, + PREFIX_VEX_0FE9, + PREFIX_VEX_0FEA, + PREFIX_VEX_0FEB, + PREFIX_VEX_0FEC, + PREFIX_VEX_0FED, + PREFIX_VEX_0FEE, + PREFIX_VEX_0FEF, + PREFIX_VEX_0FF0, + PREFIX_VEX_0FF1, + PREFIX_VEX_0FF2, + PREFIX_VEX_0FF3, + PREFIX_VEX_0FF4, + PREFIX_VEX_0FF5, + PREFIX_VEX_0FF6, + PREFIX_VEX_0FF7, + PREFIX_VEX_0FF8, + PREFIX_VEX_0FF9, + PREFIX_VEX_0FFA, + PREFIX_VEX_0FFB, + PREFIX_VEX_0FFC, + PREFIX_VEX_0FFD, + PREFIX_VEX_0FFE, + PREFIX_VEX_0F3800, + PREFIX_VEX_0F3801, + PREFIX_VEX_0F3802, + PREFIX_VEX_0F3803, + PREFIX_VEX_0F3804, + PREFIX_VEX_0F3805, + PREFIX_VEX_0F3806, + PREFIX_VEX_0F3807, + PREFIX_VEX_0F3808, + PREFIX_VEX_0F3809, + PREFIX_VEX_0F380A, + PREFIX_VEX_0F380B, + PREFIX_VEX_0F380C, + PREFIX_VEX_0F380D, + PREFIX_VEX_0F380E, + PREFIX_VEX_0F380F, + PREFIX_VEX_0F3813, + PREFIX_VEX_0F3817, + PREFIX_VEX_0F3818, + PREFIX_VEX_0F3819, + PREFIX_VEX_0F381A, + PREFIX_VEX_0F381C, + PREFIX_VEX_0F381D, + PREFIX_VEX_0F381E, + PREFIX_VEX_0F3820, + PREFIX_VEX_0F3821, + PREFIX_VEX_0F3822, + PREFIX_VEX_0F3823, + PREFIX_VEX_0F3824, + PREFIX_VEX_0F3825, + PREFIX_VEX_0F3828, + PREFIX_VEX_0F3829, + PREFIX_VEX_0F382A, + PREFIX_VEX_0F382B, + PREFIX_VEX_0F382C, + PREFIX_VEX_0F382D, + PREFIX_VEX_0F382E, + PREFIX_VEX_0F382F, + PREFIX_VEX_0F3830, + PREFIX_VEX_0F3831, + PREFIX_VEX_0F3832, + PREFIX_VEX_0F3833, + PREFIX_VEX_0F3834, + PREFIX_VEX_0F3835, + PREFIX_VEX_0F3837, + PREFIX_VEX_0F3838, + PREFIX_VEX_0F3839, + PREFIX_VEX_0F383A, + PREFIX_VEX_0F383B, + PREFIX_VEX_0F383C, + PREFIX_VEX_0F383D, + PREFIX_VEX_0F383E, + PREFIX_VEX_0F383F, + PREFIX_VEX_0F3840, + PREFIX_VEX_0F3841, + PREFIX_VEX_0F3896, + PREFIX_VEX_0F3897, + PREFIX_VEX_0F3898, + PREFIX_VEX_0F3899, + PREFIX_VEX_0F389A, + PREFIX_VEX_0F389B, + PREFIX_VEX_0F389C, + PREFIX_VEX_0F389D, + PREFIX_VEX_0F389E, + PREFIX_VEX_0F389F, + PREFIX_VEX_0F38A6, + PREFIX_VEX_0F38A7, + PREFIX_VEX_0F38A8, + PREFIX_VEX_0F38A9, + PREFIX_VEX_0F38AA, + PREFIX_VEX_0F38AB, + PREFIX_VEX_0F38AC, + PREFIX_VEX_0F38AD, + PREFIX_VEX_0F38AE, + PREFIX_VEX_0F38AF, + PREFIX_VEX_0F38B6, + PREFIX_VEX_0F38B7, + PREFIX_VEX_0F38B8, + PREFIX_VEX_0F38B9, + PREFIX_VEX_0F38BA, + PREFIX_VEX_0F38BB, + PREFIX_VEX_0F38BC, + PREFIX_VEX_0F38BD, + PREFIX_VEX_0F38BE, + PREFIX_VEX_0F38BF, + PREFIX_VEX_0F38DB, + PREFIX_VEX_0F38DC, + PREFIX_VEX_0F38DD, + PREFIX_VEX_0F38DE, + PREFIX_VEX_0F38DF, + PREFIX_VEX_0F38F2, + PREFIX_VEX_0F38F3_REG_1, + PREFIX_VEX_0F38F3_REG_2, + PREFIX_VEX_0F38F3_REG_3, + PREFIX_VEX_0F38F7, + PREFIX_VEX_0F3A04, + PREFIX_VEX_0F3A05, + PREFIX_VEX_0F3A06, + PREFIX_VEX_0F3A08, + PREFIX_VEX_0F3A09, + PREFIX_VEX_0F3A0A, + PREFIX_VEX_0F3A0B, + PREFIX_VEX_0F3A0C, + PREFIX_VEX_0F3A0D, + PREFIX_VEX_0F3A0E, + PREFIX_VEX_0F3A0F, + PREFIX_VEX_0F3A14, + PREFIX_VEX_0F3A15, + PREFIX_VEX_0F3A16, + PREFIX_VEX_0F3A17, + PREFIX_VEX_0F3A18, + PREFIX_VEX_0F3A19, + PREFIX_VEX_0F3A1D, + PREFIX_VEX_0F3A20, + PREFIX_VEX_0F3A21, + PREFIX_VEX_0F3A22, + PREFIX_VEX_0F3A40, + PREFIX_VEX_0F3A41, + PREFIX_VEX_0F3A42, + PREFIX_VEX_0F3A44, + PREFIX_VEX_0F3A48, + PREFIX_VEX_0F3A49, + PREFIX_VEX_0F3A4A, + PREFIX_VEX_0F3A4B, + PREFIX_VEX_0F3A4C, + PREFIX_VEX_0F3A5C, + PREFIX_VEX_0F3A5D, + PREFIX_VEX_0F3A5E, + PREFIX_VEX_0F3A5F, + PREFIX_VEX_0F3A60, + PREFIX_VEX_0F3A61, + PREFIX_VEX_0F3A62, + PREFIX_VEX_0F3A63, + PREFIX_VEX_0F3A68, + PREFIX_VEX_0F3A69, + PREFIX_VEX_0F3A6A, + PREFIX_VEX_0F3A6B, + PREFIX_VEX_0F3A6C, + PREFIX_VEX_0F3A6D, + PREFIX_VEX_0F3A6E, + PREFIX_VEX_0F3A6F, + PREFIX_VEX_0F3A78, + PREFIX_VEX_0F3A79, + PREFIX_VEX_0F3A7A, + PREFIX_VEX_0F3A7B, + PREFIX_VEX_0F3A7C, + PREFIX_VEX_0F3A7D, + PREFIX_VEX_0F3A7E, + PREFIX_VEX_0F3A7F, + PREFIX_VEX_0F3ADF +}; + +enum +{ + X86_64_06 = 0, + X86_64_07, + X86_64_0D, + X86_64_16, + X86_64_17, + X86_64_1E, + X86_64_1F, + X86_64_27, + X86_64_2F, + X86_64_37, + X86_64_3F, + X86_64_60, + X86_64_61, + X86_64_62, + X86_64_63, + X86_64_6D, + X86_64_6F, + X86_64_9A, + X86_64_C4, + X86_64_C5, + X86_64_CE, + X86_64_D4, + X86_64_D5, + X86_64_EA, + X86_64_0F01_REG_0, + X86_64_0F01_REG_1, + X86_64_0F01_REG_2, + X86_64_0F01_REG_3 +}; + +enum +{ + THREE_BYTE_0F38 = 0, + THREE_BYTE_0F3A, + THREE_BYTE_0F7A +}; + +enum +{ + XOP_08 = 0, + XOP_09, + XOP_0A +}; + +enum +{ + VEX_0F = 0, + VEX_0F38, + VEX_0F3A +}; + +enum +{ + VEX_LEN_0F10_P_1 = 0, + VEX_LEN_0F10_P_3, + VEX_LEN_0F11_P_1, + VEX_LEN_0F11_P_3, + VEX_LEN_0F12_P_0_M_0, + VEX_LEN_0F12_P_0_M_1, + VEX_LEN_0F12_P_2, + VEX_LEN_0F13_M_0, + VEX_LEN_0F16_P_0_M_0, + VEX_LEN_0F16_P_0_M_1, + VEX_LEN_0F16_P_2, + VEX_LEN_0F17_M_0, + VEX_LEN_0F2A_P_1, + VEX_LEN_0F2A_P_3, + VEX_LEN_0F2C_P_1, + VEX_LEN_0F2C_P_3, + VEX_LEN_0F2D_P_1, + VEX_LEN_0F2D_P_3, + VEX_LEN_0F2E_P_0, + VEX_LEN_0F2E_P_2, + VEX_LEN_0F2F_P_0, + VEX_LEN_0F2F_P_2, + VEX_LEN_0F51_P_1, + VEX_LEN_0F51_P_3, + VEX_LEN_0F52_P_1, + VEX_LEN_0F53_P_1, + VEX_LEN_0F58_P_1, + VEX_LEN_0F58_P_3, + VEX_LEN_0F59_P_1, + VEX_LEN_0F59_P_3, + VEX_LEN_0F5A_P_1, + VEX_LEN_0F5A_P_3, + VEX_LEN_0F5C_P_1, + VEX_LEN_0F5C_P_3, + VEX_LEN_0F5D_P_1, + VEX_LEN_0F5D_P_3, + VEX_LEN_0F5E_P_1, + VEX_LEN_0F5E_P_3, + VEX_LEN_0F5F_P_1, + VEX_LEN_0F5F_P_3, + VEX_LEN_0F60_P_2, + VEX_LEN_0F61_P_2, + VEX_LEN_0F62_P_2, + VEX_LEN_0F63_P_2, + VEX_LEN_0F64_P_2, + VEX_LEN_0F65_P_2, + VEX_LEN_0F66_P_2, + VEX_LEN_0F67_P_2, + VEX_LEN_0F68_P_2, + VEX_LEN_0F69_P_2, + VEX_LEN_0F6A_P_2, + VEX_LEN_0F6B_P_2, + VEX_LEN_0F6C_P_2, + VEX_LEN_0F6D_P_2, + VEX_LEN_0F6E_P_2, + VEX_LEN_0F70_P_1, + VEX_LEN_0F70_P_2, + VEX_LEN_0F70_P_3, + VEX_LEN_0F71_R_2_P_2, + VEX_LEN_0F71_R_4_P_2, + VEX_LEN_0F71_R_6_P_2, + VEX_LEN_0F72_R_2_P_2, + VEX_LEN_0F72_R_4_P_2, + VEX_LEN_0F72_R_6_P_2, + VEX_LEN_0F73_R_2_P_2, + VEX_LEN_0F73_R_3_P_2, + VEX_LEN_0F73_R_6_P_2, + VEX_LEN_0F73_R_7_P_2, + VEX_LEN_0F74_P_2, + VEX_LEN_0F75_P_2, + VEX_LEN_0F76_P_2, + VEX_LEN_0F7E_P_1, + VEX_LEN_0F7E_P_2, + VEX_LEN_0FAE_R_2_M_0, + VEX_LEN_0FAE_R_3_M_0, + VEX_LEN_0FC2_P_1, + VEX_LEN_0FC2_P_3, + VEX_LEN_0FC4_P_2, + VEX_LEN_0FC5_P_2, + VEX_LEN_0FD1_P_2, + VEX_LEN_0FD2_P_2, + VEX_LEN_0FD3_P_2, + VEX_LEN_0FD4_P_2, + VEX_LEN_0FD5_P_2, + VEX_LEN_0FD6_P_2, + VEX_LEN_0FD7_P_2_M_1, + VEX_LEN_0FD8_P_2, + VEX_LEN_0FD9_P_2, + VEX_LEN_0FDA_P_2, + VEX_LEN_0FDB_P_2, + VEX_LEN_0FDC_P_2, + VEX_LEN_0FDD_P_2, + VEX_LEN_0FDE_P_2, + VEX_LEN_0FDF_P_2, + VEX_LEN_0FE0_P_2, + VEX_LEN_0FE1_P_2, + VEX_LEN_0FE2_P_2, + VEX_LEN_0FE3_P_2, + VEX_LEN_0FE4_P_2, + VEX_LEN_0FE5_P_2, + VEX_LEN_0FE8_P_2, + VEX_LEN_0FE9_P_2, + VEX_LEN_0FEA_P_2, + VEX_LEN_0FEB_P_2, + VEX_LEN_0FEC_P_2, + VEX_LEN_0FED_P_2, + VEX_LEN_0FEE_P_2, + VEX_LEN_0FEF_P_2, + VEX_LEN_0FF1_P_2, + VEX_LEN_0FF2_P_2, + VEX_LEN_0FF3_P_2, + VEX_LEN_0FF4_P_2, + VEX_LEN_0FF5_P_2, + VEX_LEN_0FF6_P_2, + VEX_LEN_0FF7_P_2, + VEX_LEN_0FF8_P_2, + VEX_LEN_0FF9_P_2, + VEX_LEN_0FFA_P_2, + VEX_LEN_0FFB_P_2, + VEX_LEN_0FFC_P_2, + VEX_LEN_0FFD_P_2, + VEX_LEN_0FFE_P_2, + VEX_LEN_0F3800_P_2, + VEX_LEN_0F3801_P_2, + VEX_LEN_0F3802_P_2, + VEX_LEN_0F3803_P_2, + VEX_LEN_0F3804_P_2, + VEX_LEN_0F3805_P_2, + VEX_LEN_0F3806_P_2, + VEX_LEN_0F3807_P_2, + VEX_LEN_0F3808_P_2, + VEX_LEN_0F3809_P_2, + VEX_LEN_0F380A_P_2, + VEX_LEN_0F380B_P_2, + VEX_LEN_0F3819_P_2_M_0, + VEX_LEN_0F381A_P_2_M_0, + VEX_LEN_0F381C_P_2, + VEX_LEN_0F381D_P_2, + VEX_LEN_0F381E_P_2, + VEX_LEN_0F3820_P_2, + VEX_LEN_0F3821_P_2, + VEX_LEN_0F3822_P_2, + VEX_LEN_0F3823_P_2, + VEX_LEN_0F3824_P_2, + VEX_LEN_0F3825_P_2, + VEX_LEN_0F3828_P_2, + VEX_LEN_0F3829_P_2, + VEX_LEN_0F382A_P_2_M_0, + VEX_LEN_0F382B_P_2, + VEX_LEN_0F3830_P_2, + VEX_LEN_0F3831_P_2, + VEX_LEN_0F3832_P_2, + VEX_LEN_0F3833_P_2, + VEX_LEN_0F3834_P_2, + VEX_LEN_0F3835_P_2, + VEX_LEN_0F3837_P_2, + VEX_LEN_0F3838_P_2, + VEX_LEN_0F3839_P_2, + VEX_LEN_0F383A_P_2, + VEX_LEN_0F383B_P_2, + VEX_LEN_0F383C_P_2, + VEX_LEN_0F383D_P_2, + VEX_LEN_0F383E_P_2, + VEX_LEN_0F383F_P_2, + VEX_LEN_0F3840_P_2, + VEX_LEN_0F3841_P_2, + VEX_LEN_0F38DB_P_2, + VEX_LEN_0F38DC_P_2, + VEX_LEN_0F38DD_P_2, + VEX_LEN_0F38DE_P_2, + VEX_LEN_0F38DF_P_2, + VEX_LEN_0F38F2_P_0, + VEX_LEN_0F38F3_R_1_P_0, + VEX_LEN_0F38F3_R_2_P_0, + VEX_LEN_0F38F3_R_3_P_0, + VEX_LEN_0F38F7_P_0, + VEX_LEN_0F3A06_P_2, + VEX_LEN_0F3A0A_P_2, + VEX_LEN_0F3A0B_P_2, + VEX_LEN_0F3A0E_P_2, + VEX_LEN_0F3A0F_P_2, + VEX_LEN_0F3A14_P_2, + VEX_LEN_0F3A15_P_2, + VEX_LEN_0F3A16_P_2, + VEX_LEN_0F3A17_P_2, + VEX_LEN_0F3A18_P_2, + VEX_LEN_0F3A19_P_2, + VEX_LEN_0F3A20_P_2, + VEX_LEN_0F3A21_P_2, + VEX_LEN_0F3A22_P_2, + VEX_LEN_0F3A41_P_2, + VEX_LEN_0F3A42_P_2, + VEX_LEN_0F3A44_P_2, + VEX_LEN_0F3A4C_P_2, + VEX_LEN_0F3A60_P_2, + VEX_LEN_0F3A61_P_2, + VEX_LEN_0F3A62_P_2, + VEX_LEN_0F3A63_P_2, + VEX_LEN_0F3A6A_P_2, + VEX_LEN_0F3A6B_P_2, + VEX_LEN_0F3A6E_P_2, + VEX_LEN_0F3A6F_P_2, + VEX_LEN_0F3A7A_P_2, + VEX_LEN_0F3A7B_P_2, + VEX_LEN_0F3A7E_P_2, + VEX_LEN_0F3A7F_P_2, + VEX_LEN_0F3ADF_P_2, + VEX_LEN_0FXOP_09_80, + VEX_LEN_0FXOP_09_81 +}; + +enum +{ + VEX_W_0F10_P_0 = 0, + VEX_W_0F10_P_1, + VEX_W_0F10_P_2, + VEX_W_0F10_P_3, + VEX_W_0F11_P_0, + VEX_W_0F11_P_1, + VEX_W_0F11_P_2, + VEX_W_0F11_P_3, + VEX_W_0F12_P_0_M_0, + VEX_W_0F12_P_0_M_1, + VEX_W_0F12_P_1, + VEX_W_0F12_P_2, + VEX_W_0F12_P_3, + VEX_W_0F13_M_0, + VEX_W_0F14, + VEX_W_0F15, + VEX_W_0F16_P_0_M_0, + VEX_W_0F16_P_0_M_1, + VEX_W_0F16_P_1, + VEX_W_0F16_P_2, + VEX_W_0F17_M_0, + VEX_W_0F28, + VEX_W_0F29, + VEX_W_0F2B_M_0, + VEX_W_0F2E_P_0, + VEX_W_0F2E_P_2, + VEX_W_0F2F_P_0, + VEX_W_0F2F_P_2, + VEX_W_0F50_M_0, + VEX_W_0F51_P_0, + VEX_W_0F51_P_1, + VEX_W_0F51_P_2, + VEX_W_0F51_P_3, + VEX_W_0F52_P_0, + VEX_W_0F52_P_1, + VEX_W_0F53_P_0, + VEX_W_0F53_P_1, + VEX_W_0F58_P_0, + VEX_W_0F58_P_1, + VEX_W_0F58_P_2, + VEX_W_0F58_P_3, + VEX_W_0F59_P_0, + VEX_W_0F59_P_1, + VEX_W_0F59_P_2, + VEX_W_0F59_P_3, + VEX_W_0F5A_P_0, + VEX_W_0F5A_P_1, + VEX_W_0F5A_P_3, + VEX_W_0F5B_P_0, + VEX_W_0F5B_P_1, + VEX_W_0F5B_P_2, + VEX_W_0F5C_P_0, + VEX_W_0F5C_P_1, + VEX_W_0F5C_P_2, + VEX_W_0F5C_P_3, + VEX_W_0F5D_P_0, + VEX_W_0F5D_P_1, + VEX_W_0F5D_P_2, + VEX_W_0F5D_P_3, + VEX_W_0F5E_P_0, + VEX_W_0F5E_P_1, + VEX_W_0F5E_P_2, + VEX_W_0F5E_P_3, + VEX_W_0F5F_P_0, + VEX_W_0F5F_P_1, + VEX_W_0F5F_P_2, + VEX_W_0F5F_P_3, + VEX_W_0F60_P_2, + VEX_W_0F61_P_2, + VEX_W_0F62_P_2, + VEX_W_0F63_P_2, + VEX_W_0F64_P_2, + VEX_W_0F65_P_2, + VEX_W_0F66_P_2, + VEX_W_0F67_P_2, + VEX_W_0F68_P_2, + VEX_W_0F69_P_2, + VEX_W_0F6A_P_2, + VEX_W_0F6B_P_2, + VEX_W_0F6C_P_2, + VEX_W_0F6D_P_2, + VEX_W_0F6F_P_1, + VEX_W_0F6F_P_2, + VEX_W_0F70_P_1, + VEX_W_0F70_P_2, + VEX_W_0F70_P_3, + VEX_W_0F71_R_2_P_2, + VEX_W_0F71_R_4_P_2, + VEX_W_0F71_R_6_P_2, + VEX_W_0F72_R_2_P_2, + VEX_W_0F72_R_4_P_2, + VEX_W_0F72_R_6_P_2, + VEX_W_0F73_R_2_P_2, + VEX_W_0F73_R_3_P_2, + VEX_W_0F73_R_6_P_2, + VEX_W_0F73_R_7_P_2, + VEX_W_0F74_P_2, + VEX_W_0F75_P_2, + VEX_W_0F76_P_2, + VEX_W_0F77_P_0, + VEX_W_0F7C_P_2, + VEX_W_0F7C_P_3, + VEX_W_0F7D_P_2, + VEX_W_0F7D_P_3, + VEX_W_0F7E_P_1, + VEX_W_0F7F_P_1, + VEX_W_0F7F_P_2, + VEX_W_0FAE_R_2_M_0, + VEX_W_0FAE_R_3_M_0, + VEX_W_0FC2_P_0, + VEX_W_0FC2_P_1, + VEX_W_0FC2_P_2, + VEX_W_0FC2_P_3, + VEX_W_0FC4_P_2, + VEX_W_0FC5_P_2, + VEX_W_0FD0_P_2, + VEX_W_0FD0_P_3, + VEX_W_0FD1_P_2, + VEX_W_0FD2_P_2, + VEX_W_0FD3_P_2, + VEX_W_0FD4_P_2, + VEX_W_0FD5_P_2, + VEX_W_0FD6_P_2, + VEX_W_0FD7_P_2_M_1, + VEX_W_0FD8_P_2, + VEX_W_0FD9_P_2, + VEX_W_0FDA_P_2, + VEX_W_0FDB_P_2, + VEX_W_0FDC_P_2, + VEX_W_0FDD_P_2, + VEX_W_0FDE_P_2, + VEX_W_0FDF_P_2, + VEX_W_0FE0_P_2, + VEX_W_0FE1_P_2, + VEX_W_0FE2_P_2, + VEX_W_0FE3_P_2, + VEX_W_0FE4_P_2, + VEX_W_0FE5_P_2, + VEX_W_0FE6_P_1, + VEX_W_0FE6_P_2, + VEX_W_0FE6_P_3, + VEX_W_0FE7_P_2_M_0, + VEX_W_0FE8_P_2, + VEX_W_0FE9_P_2, + VEX_W_0FEA_P_2, + VEX_W_0FEB_P_2, + VEX_W_0FEC_P_2, + VEX_W_0FED_P_2, + VEX_W_0FEE_P_2, + VEX_W_0FEF_P_2, + VEX_W_0FF0_P_3_M_0, + VEX_W_0FF1_P_2, + VEX_W_0FF2_P_2, + VEX_W_0FF3_P_2, + VEX_W_0FF4_P_2, + VEX_W_0FF5_P_2, + VEX_W_0FF6_P_2, + VEX_W_0FF7_P_2, + VEX_W_0FF8_P_2, + VEX_W_0FF9_P_2, + VEX_W_0FFA_P_2, + VEX_W_0FFB_P_2, + VEX_W_0FFC_P_2, + VEX_W_0FFD_P_2, + VEX_W_0FFE_P_2, + VEX_W_0F3800_P_2, + VEX_W_0F3801_P_2, + VEX_W_0F3802_P_2, + VEX_W_0F3803_P_2, + VEX_W_0F3804_P_2, + VEX_W_0F3805_P_2, + VEX_W_0F3806_P_2, + VEX_W_0F3807_P_2, + VEX_W_0F3808_P_2, + VEX_W_0F3809_P_2, + VEX_W_0F380A_P_2, + VEX_W_0F380B_P_2, + VEX_W_0F380C_P_2, + VEX_W_0F380D_P_2, + VEX_W_0F380E_P_2, + VEX_W_0F380F_P_2, + VEX_W_0F3817_P_2, + VEX_W_0F3818_P_2_M_0, + VEX_W_0F3819_P_2_M_0, + VEX_W_0F381A_P_2_M_0, + VEX_W_0F381C_P_2, + VEX_W_0F381D_P_2, + VEX_W_0F381E_P_2, + VEX_W_0F3820_P_2, + VEX_W_0F3821_P_2, + VEX_W_0F3822_P_2, + VEX_W_0F3823_P_2, + VEX_W_0F3824_P_2, + VEX_W_0F3825_P_2, + VEX_W_0F3828_P_2, + VEX_W_0F3829_P_2, + VEX_W_0F382A_P_2_M_0, + VEX_W_0F382B_P_2, + VEX_W_0F382C_P_2_M_0, + VEX_W_0F382D_P_2_M_0, + VEX_W_0F382E_P_2_M_0, + VEX_W_0F382F_P_2_M_0, + VEX_W_0F3830_P_2, + VEX_W_0F3831_P_2, + VEX_W_0F3832_P_2, + VEX_W_0F3833_P_2, + VEX_W_0F3834_P_2, + VEX_W_0F3835_P_2, + VEX_W_0F3837_P_2, + VEX_W_0F3838_P_2, + VEX_W_0F3839_P_2, + VEX_W_0F383A_P_2, + VEX_W_0F383B_P_2, + VEX_W_0F383C_P_2, + VEX_W_0F383D_P_2, + VEX_W_0F383E_P_2, + VEX_W_0F383F_P_2, + VEX_W_0F3840_P_2, + VEX_W_0F3841_P_2, + VEX_W_0F38DB_P_2, + VEX_W_0F38DC_P_2, + VEX_W_0F38DD_P_2, + VEX_W_0F38DE_P_2, + VEX_W_0F38DF_P_2, + VEX_W_0F3A04_P_2, + VEX_W_0F3A05_P_2, + VEX_W_0F3A06_P_2, + VEX_W_0F3A08_P_2, + VEX_W_0F3A09_P_2, + VEX_W_0F3A0A_P_2, + VEX_W_0F3A0B_P_2, + VEX_W_0F3A0C_P_2, + VEX_W_0F3A0D_P_2, + VEX_W_0F3A0E_P_2, + VEX_W_0F3A0F_P_2, + VEX_W_0F3A14_P_2, + VEX_W_0F3A15_P_2, + VEX_W_0F3A18_P_2, + VEX_W_0F3A19_P_2, + VEX_W_0F3A20_P_2, + VEX_W_0F3A21_P_2, + VEX_W_0F3A40_P_2, + VEX_W_0F3A41_P_2, + VEX_W_0F3A42_P_2, + VEX_W_0F3A44_P_2, + VEX_W_0F3A48_P_2, + VEX_W_0F3A49_P_2, + VEX_W_0F3A4A_P_2, + VEX_W_0F3A4B_P_2, + VEX_W_0F3A4C_P_2, + VEX_W_0F3A60_P_2, + VEX_W_0F3A61_P_2, + VEX_W_0F3A62_P_2, + VEX_W_0F3A63_P_2, + VEX_W_0F3ADF_P_2 +}; + +typedef void (*op_rtn) (int bytemode, int sizeflag); + +struct dis386 { + const char *name; + struct + { + op_rtn rtn; + int bytemode; + } op[MAX_OPERANDS]; +}; + +/* Upper case letters in the instruction names here are macros. + 'A' => print 'b' if no register operands or suffix_always is true + 'B' => print 'b' if suffix_always is true + 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand + size prefix + 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if + suffix_always is true + 'E' => print 'e' if 32-bit form of jcxz + 'F' => print 'w' or 'l' depending on address size prefix (loop insns) + 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) + 'H' => print ",pt" or ",pn" branch hint + 'I' => honor following macro letter even in Intel mode (implemented only + for some of the macro letters) + 'J' => print 'l' + 'K' => print 'd' or 'q' if rex prefix is present. + 'L' => print 'l' if suffix_always is true + 'M' => print 'r' if intel_mnemonic is false. + 'N' => print 'n' if instruction has no wait "prefix" + 'O' => print 'd' or 'o' (or 'q' in Intel mode) + 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, + or suffix_always is true. print 'q' if rex prefix is present. + 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always + is true + 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) + 'S' => print 'w', 'l' or 'q' if suffix_always is true + 'T' => print 'q' in 64bit mode and behave as 'P' otherwise + 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise + 'V' => print 'q' in 64bit mode and behave as 'S' otherwise + 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) + 'X' => print 's', 'd' depending on data16 prefix (for XMM) + 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and + suffix_always is true. + 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise + '!' => change condition from true to false or from false to true. + '%' => add 1 upper case letter to the macro. + + 2 upper case letter macros: + "XY" => print 'x' or 'y' if no register operands or suffix_always + is true. + "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) + "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand + or suffix_always is true + "LB" => print "abs" in 64bit mode and behave as 'B' otherwise + "LS" => print "abs" in 64bit mode and behave as 'S' otherwise + "LV" => print "abs" for 64bit operand and behave as 'S' otherwise + + Many of the above letters print nothing in Intel mode. See "putop" + for the details. + + Braces '{' and '}', and vertical bars '|', indicate alternative + mnemonic strings for AT&T and Intel. */ + +static const struct dis386 dis386[] = { + /* 00 */ + { "addB", { Eb, Gb } }, + { "addS", { Ev, Gv } }, + { "addB", { Gb, EbS } }, + { "addS", { Gv, EvS } }, + { "addB", { AL, Ib } }, + { "addS", { eAX, Iv } }, + { X86_64_TABLE (X86_64_06) }, + { X86_64_TABLE (X86_64_07) }, + /* 08 */ + { "orB", { Eb, Gb } }, + { "orS", { Ev, Gv } }, + { "orB", { Gb, EbS } }, + { "orS", { Gv, EvS } }, + { "orB", { AL, Ib } }, + { "orS", { eAX, Iv } }, + { X86_64_TABLE (X86_64_0D) }, + { Bad_Opcode }, /* 0x0f extended opcode escape */ + /* 10 */ + { "adcB", { Eb, Gb } }, + { "adcS", { Ev, Gv } }, + { "adcB", { Gb, EbS } }, + { "adcS", { Gv, EvS } }, + { "adcB", { AL, Ib } }, + { "adcS", { eAX, Iv } }, + { X86_64_TABLE (X86_64_16) }, + { X86_64_TABLE (X86_64_17) }, + /* 18 */ + { "sbbB", { Eb, Gb } }, + { "sbbS", { Ev, Gv } }, + { "sbbB", { Gb, EbS } }, + { "sbbS", { Gv, EvS } }, + { "sbbB", { AL, Ib } }, + { "sbbS", { eAX, Iv } }, + { X86_64_TABLE (X86_64_1E) }, + { X86_64_TABLE (X86_64_1F) }, + /* 20 */ + { "andB", { Eb, Gb } }, + { "andS", { Ev, Gv } }, + { "andB", { Gb, EbS } }, + { "andS", { Gv, EvS } }, + { "andB", { AL, Ib } }, + { "andS", { eAX, Iv } }, + { Bad_Opcode }, /* SEG ES prefix */ + { X86_64_TABLE (X86_64_27) }, + /* 28 */ + { "subB", { Eb, Gb } }, + { "subS", { Ev, Gv } }, + { "subB", { Gb, EbS } }, + { "subS", { Gv, EvS } }, + { "subB", { AL, Ib } }, + { "subS", { eAX, Iv } }, + { Bad_Opcode }, /* SEG CS prefix */ + { X86_64_TABLE (X86_64_2F) }, + /* 30 */ + { "xorB", { Eb, Gb } }, + { "xorS", { Ev, Gv } }, + { "xorB", { Gb, EbS } }, + { "xorS", { Gv, EvS } }, + { "xorB", { AL, Ib } }, + { "xorS", { eAX, Iv } }, + { Bad_Opcode }, /* SEG SS prefix */ + { X86_64_TABLE (X86_64_37) }, + /* 38 */ + { "cmpB", { Eb, Gb } }, + { "cmpS", { Ev, Gv } }, + { "cmpB", { Gb, EbS } }, + { "cmpS", { Gv, EvS } }, + { "cmpB", { AL, Ib } }, + { "cmpS", { eAX, Iv } }, + { Bad_Opcode }, /* SEG DS prefix */ + { X86_64_TABLE (X86_64_3F) }, + /* 40 */ + { "inc{S|}", { RMeAX } }, + { "inc{S|}", { RMeCX } }, + { "inc{S|}", { RMeDX } }, + { "inc{S|}", { RMeBX } }, + { "inc{S|}", { RMeSP } }, + { "inc{S|}", { RMeBP } }, + { "inc{S|}", { RMeSI } }, + { "inc{S|}", { RMeDI } }, + /* 48 */ + { "dec{S|}", { RMeAX } }, + { "dec{S|}", { RMeCX } }, + { "dec{S|}", { RMeDX } }, + { "dec{S|}", { RMeBX } }, + { "dec{S|}", { RMeSP } }, + { "dec{S|}", { RMeBP } }, + { "dec{S|}", { RMeSI } }, + { "dec{S|}", { RMeDI } }, + /* 50 */ + { "pushV", { RMrAX } }, + { "pushV", { RMrCX } }, + { "pushV", { RMrDX } }, + { "pushV", { RMrBX } }, + { "pushV", { RMrSP } }, + { "pushV", { RMrBP } }, + { "pushV", { RMrSI } }, + { "pushV", { RMrDI } }, + /* 58 */ + { "popV", { RMrAX } }, + { "popV", { RMrCX } }, + { "popV", { RMrDX } }, + { "popV", { RMrBX } }, + { "popV", { RMrSP } }, + { "popV", { RMrBP } }, + { "popV", { RMrSI } }, + { "popV", { RMrDI } }, + /* 60 */ + { X86_64_TABLE (X86_64_60) }, + { X86_64_TABLE (X86_64_61) }, + { X86_64_TABLE (X86_64_62) }, + { X86_64_TABLE (X86_64_63) }, + { Bad_Opcode }, /* seg fs */ + { Bad_Opcode }, /* seg gs */ + { Bad_Opcode }, /* op size prefix */ + { Bad_Opcode }, /* adr size prefix */ + /* 68 */ + { "pushT", { sIv } }, + { "imulS", { Gv, Ev, Iv } }, + { "pushT", { sIbT } }, + { "imulS", { Gv, Ev, sIb } }, + { "ins{b|}", { Ybr, indirDX } }, + { X86_64_TABLE (X86_64_6D) }, + { "outs{b|}", { indirDXr, Xb } }, + { X86_64_TABLE (X86_64_6F) }, + /* 70 */ + { "joH", { Jb, XX, cond_jump_flag } }, + { "jnoH", { Jb, XX, cond_jump_flag } }, + { "jbH", { Jb, XX, cond_jump_flag } }, + { "jaeH", { Jb, XX, cond_jump_flag } }, + { "jeH", { Jb, XX, cond_jump_flag } }, + { "jneH", { Jb, XX, cond_jump_flag } }, + { "jbeH", { Jb, XX, cond_jump_flag } }, + { "jaH", { Jb, XX, cond_jump_flag } }, + /* 78 */ + { "jsH", { Jb, XX, cond_jump_flag } }, + { "jnsH", { Jb, XX, cond_jump_flag } }, + { "jpH", { Jb, XX, cond_jump_flag } }, + { "jnpH", { Jb, XX, cond_jump_flag } }, + { "jlH", { Jb, XX, cond_jump_flag } }, + { "jgeH", { Jb, XX, cond_jump_flag } }, + { "jleH", { Jb, XX, cond_jump_flag } }, + { "jgH", { Jb, XX, cond_jump_flag } }, + /* 80 */ + { REG_TABLE (REG_80) }, + { REG_TABLE (REG_81) }, + { Bad_Opcode }, + { REG_TABLE (REG_82) }, + { "testB", { Eb, Gb } }, + { "testS", { Ev, Gv } }, + { "xchgB", { Eb, Gb } }, + { "xchgS", { Ev, Gv } }, + /* 88 */ + { "movB", { Eb, Gb } }, + { "movS", { Ev, Gv } }, + { "movB", { Gb, EbS } }, + { "movS", { Gv, EvS } }, + { "movD", { Sv, Sw } }, + { MOD_TABLE (MOD_8D) }, + { "movD", { Sw, Sv } }, + { REG_TABLE (REG_8F) }, + /* 90 */ + { PREFIX_TABLE (PREFIX_90) }, + { "xchgS", { RMeCX, eAX } }, + { "xchgS", { RMeDX, eAX } }, + { "xchgS", { RMeBX, eAX } }, + { "xchgS", { RMeSP, eAX } }, + { "xchgS", { RMeBP, eAX } }, + { "xchgS", { RMeSI, eAX } }, + { "xchgS", { RMeDI, eAX } }, + /* 98 */ + { "cW{t|}R", { XX } }, + { "cR{t|}O", { XX } }, + { X86_64_TABLE (X86_64_9A) }, + { Bad_Opcode }, /* fwait */ + { "pushfT", { XX } }, + { "popfT", { XX } }, + { "sahf", { XX } }, + { "lahf", { XX } }, + /* a0 */ + { "mov%LB", { AL, Ob } }, + { "mov%LS", { eAX, Ov } }, + { "mov%LB", { Ob, AL } }, + { "mov%LS", { Ov, eAX } }, + { "movs{b|}", { Ybr, Xb } }, + { "movs{R|}", { Yvr, Xv } }, + { "cmps{b|}", { Xb, Yb } }, + { "cmps{R|}", { Xv, Yv } }, + /* a8 */ + { "testB", { AL, Ib } }, + { "testS", { eAX, Iv } }, + { "stosB", { Ybr, AL } }, + { "stosS", { Yvr, eAX } }, + { "lodsB", { ALr, Xb } }, + { "lodsS", { eAXr, Xv } }, + { "scasB", { AL, Yb } }, + { "scasS", { eAX, Yv } }, + /* b0 */ + { "movB", { RMAL, Ib } }, + { "movB", { RMCL, Ib } }, + { "movB", { RMDL, Ib } }, + { "movB", { RMBL, Ib } }, + { "movB", { RMAH, Ib } }, + { "movB", { RMCH, Ib } }, + { "movB", { RMDH, Ib } }, + { "movB", { RMBH, Ib } }, + /* b8 */ + { "mov%LV", { RMeAX, Iv64 } }, + { "mov%LV", { RMeCX, Iv64 } }, + { "mov%LV", { RMeDX, Iv64 } }, + { "mov%LV", { RMeBX, Iv64 } }, + { "mov%LV", { RMeSP, Iv64 } }, + { "mov%LV", { RMeBP, Iv64 } }, + { "mov%LV", { RMeSI, Iv64 } }, + { "mov%LV", { RMeDI, Iv64 } }, + /* c0 */ + { REG_TABLE (REG_C0) }, + { REG_TABLE (REG_C1) }, + { "retT", { Iw } }, + { "retT", { XX } }, + { X86_64_TABLE (X86_64_C4) }, + { X86_64_TABLE (X86_64_C5) }, + { REG_TABLE (REG_C6) }, + { REG_TABLE (REG_C7) }, + /* c8 */ + { "enterT", { Iw, Ib } }, + { "leaveT", { XX } }, + { "Jret{|f}P", { Iw } }, + { "Jret{|f}P", { XX } }, + { "int3", { XX } }, + { "int", { Ib } }, + { X86_64_TABLE (X86_64_CE) }, + { "iretP", { XX } }, + /* d0 */ + { REG_TABLE (REG_D0) }, + { REG_TABLE (REG_D1) }, + { REG_TABLE (REG_D2) }, + { REG_TABLE (REG_D3) }, + { X86_64_TABLE (X86_64_D4) }, + { X86_64_TABLE (X86_64_D5) }, + { Bad_Opcode }, + { "xlat", { DSBX } }, + /* d8 */ + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + { FLOAT }, + /* e0 */ + { "loopneFH", { Jb, XX, loop_jcxz_flag } }, + { "loopeFH", { Jb, XX, loop_jcxz_flag } }, + { "loopFH", { Jb, XX, loop_jcxz_flag } }, + { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, + { "inB", { AL, Ib } }, + { "inG", { zAX, Ib } }, + { "outB", { Ib, AL } }, + { "outG", { Ib, zAX } }, + /* e8 */ + { "callT", { Jv } }, + { "jmpT", { Jv } }, + { X86_64_TABLE (X86_64_EA) }, + { "jmp", { Jb } }, + { "inB", { AL, indirDX } }, + { "inG", { zAX, indirDX } }, + { "outB", { indirDX, AL } }, + { "outG", { indirDX, zAX } }, + /* f0 */ + { Bad_Opcode }, /* lock prefix */ + { "icebp", { XX } }, + { Bad_Opcode }, /* repne */ + { Bad_Opcode }, /* repz */ + { "hlt", { XX } }, + { "cmc", { XX } }, + { REG_TABLE (REG_F6) }, + { REG_TABLE (REG_F7) }, + /* f8 */ + { "clc", { XX } }, + { "stc", { XX } }, + { "cli", { XX } }, + { "sti", { XX } }, + { "cld", { XX } }, + { "std", { XX } }, + { REG_TABLE (REG_FE) }, + { REG_TABLE (REG_FF) }, +}; + +static const struct dis386 dis386_twobyte[] = { + /* 00 */ + { REG_TABLE (REG_0F00 ) }, + { REG_TABLE (REG_0F01 ) }, + { "larS", { Gv, Ew } }, + { "lslS", { Gv, Ew } }, + { Bad_Opcode }, + { "syscall", { XX } }, + { "clts", { XX } }, + { "sysretP", { XX } }, + /* 08 */ + { "invd", { XX } }, + { "wbinvd", { XX } }, + { Bad_Opcode }, + { "ud2", { XX } }, + { Bad_Opcode }, + { REG_TABLE (REG_0F0D) }, + { "femms", { XX } }, + { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ + /* 10 */ + { PREFIX_TABLE (PREFIX_0F10) }, + { PREFIX_TABLE (PREFIX_0F11) }, + { PREFIX_TABLE (PREFIX_0F12) }, + { MOD_TABLE (MOD_0F13) }, + { "unpcklpX", { XM, EXx } }, + { "unpckhpX", { XM, EXx } }, + { PREFIX_TABLE (PREFIX_0F16) }, + { MOD_TABLE (MOD_0F17) }, + /* 18 */ + { REG_TABLE (REG_0F18) }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + { "nopQ", { Ev } }, + /* 20 */ + { MOD_TABLE (MOD_0F20) }, + { MOD_TABLE (MOD_0F21) }, + { MOD_TABLE (MOD_0F22) }, + { MOD_TABLE (MOD_0F23) }, + { MOD_TABLE (MOD_0F24) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F26) }, + { Bad_Opcode }, + /* 28 */ + { "movapX", { XM, EXx } }, + { "movapX", { EXxS, XM } }, + { PREFIX_TABLE (PREFIX_0F2A) }, + { PREFIX_TABLE (PREFIX_0F2B) }, + { PREFIX_TABLE (PREFIX_0F2C) }, + { PREFIX_TABLE (PREFIX_0F2D) }, + { PREFIX_TABLE (PREFIX_0F2E) }, + { PREFIX_TABLE (PREFIX_0F2F) }, + /* 30 */ + { "wrmsr", { XX } }, + { "rdtsc", { XX } }, + { "rdmsr", { XX } }, + { "rdpmc", { XX } }, + { "sysenter", { XX } }, + { "sysexit", { XX } }, + { Bad_Opcode }, + { "getsec", { XX } }, + /* 38 */ + { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, + { Bad_Opcode }, + { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { "cmovoS", { Gv, Ev } }, + { "cmovnoS", { Gv, Ev } }, + { "cmovbS", { Gv, Ev } }, + { "cmovaeS", { Gv, Ev } }, + { "cmoveS", { Gv, Ev } }, + { "cmovneS", { Gv, Ev } }, + { "cmovbeS", { Gv, Ev } }, + { "cmovaS", { Gv, Ev } }, + /* 48 */ + { "cmovsS", { Gv, Ev } }, + { "cmovnsS", { Gv, Ev } }, + { "cmovpS", { Gv, Ev } }, + { "cmovnpS", { Gv, Ev } }, + { "cmovlS", { Gv, Ev } }, + { "cmovgeS", { Gv, Ev } }, + { "cmovleS", { Gv, Ev } }, + { "cmovgS", { Gv, Ev } }, + /* 50 */ + { MOD_TABLE (MOD_0F51) }, + { PREFIX_TABLE (PREFIX_0F51) }, + { PREFIX_TABLE (PREFIX_0F52) }, + { PREFIX_TABLE (PREFIX_0F53) }, + { "andpX", { XM, EXx } }, + { "andnpX", { XM, EXx } }, + { "orpX", { XM, EXx } }, + { "xorpX", { XM, EXx } }, + /* 58 */ + { PREFIX_TABLE (PREFIX_0F58) }, + { PREFIX_TABLE (PREFIX_0F59) }, + { PREFIX_TABLE (PREFIX_0F5A) }, + { PREFIX_TABLE (PREFIX_0F5B) }, + { PREFIX_TABLE (PREFIX_0F5C) }, + { PREFIX_TABLE (PREFIX_0F5D) }, + { PREFIX_TABLE (PREFIX_0F5E) }, + { PREFIX_TABLE (PREFIX_0F5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_0F60) }, + { PREFIX_TABLE (PREFIX_0F61) }, + { PREFIX_TABLE (PREFIX_0F62) }, + { "packsswb", { MX, EM } }, + { "pcmpgtb", { MX, EM } }, + { "pcmpgtw", { MX, EM } }, + { "pcmpgtd", { MX, EM } }, + { "packuswb", { MX, EM } }, + /* 68 */ + { "punpckhbw", { MX, EM } }, + { "punpckhwd", { MX, EM } }, + { "punpckhdq", { MX, EM } }, + { "packssdw", { MX, EM } }, + { PREFIX_TABLE (PREFIX_0F6C) }, + { PREFIX_TABLE (PREFIX_0F6D) }, + { "movK", { MX, Edq } }, + { PREFIX_TABLE (PREFIX_0F6F) }, + /* 70 */ + { PREFIX_TABLE (PREFIX_0F70) }, + { REG_TABLE (REG_0F71) }, + { REG_TABLE (REG_0F72) }, + { REG_TABLE (REG_0F73) }, + { "pcmpeqb", { MX, EM } }, + { "pcmpeqw", { MX, EM } }, + { "pcmpeqd", { MX, EM } }, + { "emms", { XX } }, + /* 78 */ + { PREFIX_TABLE (PREFIX_0F78) }, + { PREFIX_TABLE (PREFIX_0F79) }, + { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F7C) }, + { PREFIX_TABLE (PREFIX_0F7D) }, + { PREFIX_TABLE (PREFIX_0F7E) }, + { PREFIX_TABLE (PREFIX_0F7F) }, + /* 80 */ + { "joH", { Jv, XX, cond_jump_flag } }, + { "jnoH", { Jv, XX, cond_jump_flag } }, + { "jbH", { Jv, XX, cond_jump_flag } }, + { "jaeH", { Jv, XX, cond_jump_flag } }, + { "jeH", { Jv, XX, cond_jump_flag } }, + { "jneH", { Jv, XX, cond_jump_flag } }, + { "jbeH", { Jv, XX, cond_jump_flag } }, + { "jaH", { Jv, XX, cond_jump_flag } }, + /* 88 */ + { "jsH", { Jv, XX, cond_jump_flag } }, + { "jnsH", { Jv, XX, cond_jump_flag } }, + { "jpH", { Jv, XX, cond_jump_flag } }, + { "jnpH", { Jv, XX, cond_jump_flag } }, + { "jlH", { Jv, XX, cond_jump_flag } }, + { "jgeH", { Jv, XX, cond_jump_flag } }, + { "jleH", { Jv, XX, cond_jump_flag } }, + { "jgH", { Jv, XX, cond_jump_flag } }, + /* 90 */ + { "seto", { Eb } }, + { "setno", { Eb } }, + { "setb", { Eb } }, + { "setae", { Eb } }, + { "sete", { Eb } }, + { "setne", { Eb } }, + { "setbe", { Eb } }, + { "seta", { Eb } }, + /* 98 */ + { "sets", { Eb } }, + { "setns", { Eb } }, + { "setp", { Eb } }, + { "setnp", { Eb } }, + { "setl", { Eb } }, + { "setge", { Eb } }, + { "setle", { Eb } }, + { "setg", { Eb } }, + /* a0 */ + { "pushT", { fs } }, + { "popT", { fs } }, + { "cpuid", { XX } }, + { "btS", { Ev, Gv } }, + { "shldS", { Ev, Gv, Ib } }, + { "shldS", { Ev, Gv, CL } }, + { REG_TABLE (REG_0FA6) }, + { REG_TABLE (REG_0FA7) }, + /* a8 */ + { "pushT", { gs } }, + { "popT", { gs } }, + { "rsm", { XX } }, + { "btsS", { Ev, Gv } }, + { "shrdS", { Ev, Gv, Ib } }, + { "shrdS", { Ev, Gv, CL } }, + { REG_TABLE (REG_0FAE) }, + { "imulS", { Gv, Ev } }, + /* b0 */ + { "cmpxchgB", { Eb, Gb } }, + { "cmpxchgS", { Ev, Gv } }, + { MOD_TABLE (MOD_0FB2) }, + { "btrS", { Ev, Gv } }, + { MOD_TABLE (MOD_0FB4) }, + { MOD_TABLE (MOD_0FB5) }, + { "movz{bR|x}", { Gv, Eb } }, + { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ + /* b8 */ + { PREFIX_TABLE (PREFIX_0FB8) }, + { "ud1", { XX } }, + { REG_TABLE (REG_0FBA) }, + { "btcS", { Ev, Gv } }, + { PREFIX_TABLE (PREFIX_0FBC) }, + { PREFIX_TABLE (PREFIX_0FBD) }, + { "movs{bR|x}", { Gv, Eb } }, + { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ + /* c0 */ + { "xaddB", { Eb, Gb } }, + { "xaddS", { Ev, Gv } }, + { PREFIX_TABLE (PREFIX_0FC2) }, + { PREFIX_TABLE (PREFIX_0FC3) }, + { "pinsrw", { MX, Edqw, Ib } }, + { "pextrw", { Gdq, MS, Ib } }, + { "shufpX", { XM, EXx, Ib } }, + { REG_TABLE (REG_0FC7) }, + /* c8 */ + { "bswap", { RMeAX } }, + { "bswap", { RMeCX } }, + { "bswap", { RMeDX } }, + { "bswap", { RMeBX } }, + { "bswap", { RMeSP } }, + { "bswap", { RMeBP } }, + { "bswap", { RMeSI } }, + { "bswap", { RMeDI } }, + /* d0 */ + { PREFIX_TABLE (PREFIX_0FD0) }, + { "psrlw", { MX, EM } }, + { "psrld", { MX, EM } }, + { "psrlq", { MX, EM } }, + { "paddq", { MX, EM } }, + { "pmullw", { MX, EM } }, + { PREFIX_TABLE (PREFIX_0FD6) }, + { MOD_TABLE (MOD_0FD7) }, + /* d8 */ + { "psubusb", { MX, EM } }, + { "psubusw", { MX, EM } }, + { "pminub", { MX, EM } }, + { "pand", { MX, EM } }, + { "paddusb", { MX, EM } }, + { "paddusw", { MX, EM } }, + { "pmaxub", { MX, EM } }, + { "pandn", { MX, EM } }, + /* e0 */ + { "pavgb", { MX, EM } }, + { "psraw", { MX, EM } }, + { "psrad", { MX, EM } }, + { "pavgw", { MX, EM } }, + { "pmulhuw", { MX, EM } }, + { "pmulhw", { MX, EM } }, + { PREFIX_TABLE (PREFIX_0FE6) }, + { PREFIX_TABLE (PREFIX_0FE7) }, + /* e8 */ + { "psubsb", { MX, EM } }, + { "psubsw", { MX, EM } }, + { "pminsw", { MX, EM } }, + { "por", { MX, EM } }, + { "paddsb", { MX, EM } }, + { "paddsw", { MX, EM } }, + { "pmaxsw", { MX, EM } }, + { "pxor", { MX, EM } }, + /* f0 */ + { PREFIX_TABLE (PREFIX_0FF0) }, + { "psllw", { MX, EM } }, + { "pslld", { MX, EM } }, + { "psllq", { MX, EM } }, + { "pmuludq", { MX, EM } }, + { "pmaddwd", { MX, EM } }, + { "psadbw", { MX, EM } }, + { PREFIX_TABLE (PREFIX_0FF7) }, + /* f8 */ + { "psubb", { MX, EM } }, + { "psubw", { MX, EM } }, + { "psubd", { MX, EM } }, + { "psubq", { MX, EM } }, + { "paddb", { MX, EM } }, + { "paddw", { MX, EM } }, + { "paddd", { MX, EM } }, + { Bad_Opcode }, +}; + +static const unsigned char onebyte_has_modrm[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ + /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ + /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ + /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ + /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ + /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ + /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ + /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ + /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static const unsigned char twobyte_has_modrm[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ + /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ + /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ + /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ + /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ + /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ + /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ + /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ + /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ + /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ + /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static char obuf[100]; +static char *obufp; +static char *mnemonicendp; +static char scratchbuf[100]; +static unsigned char *start_codep; +static unsigned char *insn_codep; +static unsigned char *codep; +static int last_lock_prefix; +static int last_repz_prefix; +static int last_repnz_prefix; +static int last_data_prefix; +static int last_addr_prefix; +static int last_rex_prefix; +static int last_seg_prefix; +#define MAX_CODE_LENGTH 15 +/* We can up to 14 prefixes since the maximum instruction length is + 15bytes. */ +static int all_prefixes[MAX_CODE_LENGTH - 1]; +static disassemble_info *the_info; +static struct + { + int mod; + int reg; + int rm; + } +modrm; +static unsigned char need_modrm; +static struct + { + int scale; + int index; + int base; + } +sib; +static struct + { + int register_specifier; + int length; + int prefix; + int w; + } +vex; +static unsigned char need_vex; +static unsigned char need_vex_reg; +static unsigned char vex_w_done; + +struct op + { + const char *name; + unsigned int len; + }; + +/* If we are accessing mod/rm/reg without need_modrm set, then the + values are stale. Hitting this abort likely indicates that you + need to update onebyte_has_modrm or twobyte_has_modrm. */ +#define MODRM_CHECK if (!need_modrm) abort () + +static const char **names64; +static const char **names32; +static const char **names16; +static const char **names8; +static const char **names8rex; +static const char **names_seg; +static const char *index64; +static const char *index32; +static const char **index16; + +static const char *intel_names64[] = { + "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; +static const char *intel_names32[] = { + "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", + "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" +}; +static const char *intel_names16[] = { + "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", + "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" +}; +static const char *intel_names8[] = { + "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", +}; +static const char *intel_names8rex[] = { + "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", + "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" +}; +static const char *intel_names_seg[] = { + "es", "cs", "ss", "ds", "fs", "gs", "?", "?", +}; +static const char *intel_index64 = "riz"; +static const char *intel_index32 = "eiz"; +static const char *intel_index16[] = { + "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" +}; + +static const char *att_names64[] = { + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" +}; +static const char *att_names32[] = { + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", + "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" +}; +static const char *att_names16[] = { + "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", + "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" +}; +static const char *att_names8[] = { + "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", +}; +static const char *att_names8rex[] = { + "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", + "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" +}; +static const char *att_names_seg[] = { + "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", +}; +static const char *att_index64 = "%riz"; +static const char *att_index32 = "%eiz"; +static const char *att_index16[] = { + "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" +}; + +static const char **names_mm; +static const char *intel_names_mm[] = { + "mm0", "mm1", "mm2", "mm3", + "mm4", "mm5", "mm6", "mm7" +}; +static const char *att_names_mm[] = { + "%mm0", "%mm1", "%mm2", "%mm3", + "%mm4", "%mm5", "%mm6", "%mm7" +}; + +static const char **names_xmm; +static const char *intel_names_xmm[] = { + "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15" +}; +static const char *att_names_xmm[] = { + "%xmm0", "%xmm1", "%xmm2", "%xmm3", + "%xmm4", "%xmm5", "%xmm6", "%xmm7", + "%xmm8", "%xmm9", "%xmm10", "%xmm11", + "%xmm12", "%xmm13", "%xmm14", "%xmm15" +}; + +static const char **names_ymm; +static const char *intel_names_ymm[] = { + "ymm0", "ymm1", "ymm2", "ymm3", + "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", + "ymm12", "ymm13", "ymm14", "ymm15" +}; +static const char *att_names_ymm[] = { + "%ymm0", "%ymm1", "%ymm2", "%ymm3", + "%ymm4", "%ymm5", "%ymm6", "%ymm7", + "%ymm8", "%ymm9", "%ymm10", "%ymm11", + "%ymm12", "%ymm13", "%ymm14", "%ymm15" +}; + +static const struct dis386 reg_table[][8] = { + /* REG_80 */ + { + { "addA", { Eb, Ib } }, + { "orA", { Eb, Ib } }, + { "adcA", { Eb, Ib } }, + { "sbbA", { Eb, Ib } }, + { "andA", { Eb, Ib } }, + { "subA", { Eb, Ib } }, + { "xorA", { Eb, Ib } }, + { "cmpA", { Eb, Ib } }, + }, + /* REG_81 */ + { + { "addQ", { Ev, Iv } }, + { "orQ", { Ev, Iv } }, + { "adcQ", { Ev, Iv } }, + { "sbbQ", { Ev, Iv } }, + { "andQ", { Ev, Iv } }, + { "subQ", { Ev, Iv } }, + { "xorQ", { Ev, Iv } }, + { "cmpQ", { Ev, Iv } }, + }, + /* REG_82 */ + { + { "addQ", { Ev, sIb } }, + { "orQ", { Ev, sIb } }, + { "adcQ", { Ev, sIb } }, + { "sbbQ", { Ev, sIb } }, + { "andQ", { Ev, sIb } }, + { "subQ", { Ev, sIb } }, + { "xorQ", { Ev, sIb } }, + { "cmpQ", { Ev, sIb } }, + }, + /* REG_8F */ + { + { "popU", { stackEv } }, + { XOP_8F_TABLE (XOP_09) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { XOP_8F_TABLE (XOP_09) }, + }, + /* REG_C0 */ + { + { "rolA", { Eb, Ib } }, + { "rorA", { Eb, Ib } }, + { "rclA", { Eb, Ib } }, + { "rcrA", { Eb, Ib } }, + { "shlA", { Eb, Ib } }, + { "shrA", { Eb, Ib } }, + { Bad_Opcode }, + { "sarA", { Eb, Ib } }, + }, + /* REG_C1 */ + { + { "rolQ", { Ev, Ib } }, + { "rorQ", { Ev, Ib } }, + { "rclQ", { Ev, Ib } }, + { "rcrQ", { Ev, Ib } }, + { "shlQ", { Ev, Ib } }, + { "shrQ", { Ev, Ib } }, + { Bad_Opcode }, + { "sarQ", { Ev, Ib } }, + }, + /* REG_C6 */ + { + { "movA", { Eb, Ib } }, + }, + /* REG_C7 */ + { + { "movQ", { Ev, Iv } }, + }, + /* REG_D0 */ + { + { "rolA", { Eb, I1 } }, + { "rorA", { Eb, I1 } }, + { "rclA", { Eb, I1 } }, + { "rcrA", { Eb, I1 } }, + { "shlA", { Eb, I1 } }, + { "shrA", { Eb, I1 } }, + { Bad_Opcode }, + { "sarA", { Eb, I1 } }, + }, + /* REG_D1 */ + { + { "rolQ", { Ev, I1 } }, + { "rorQ", { Ev, I1 } }, + { "rclQ", { Ev, I1 } }, + { "rcrQ", { Ev, I1 } }, + { "shlQ", { Ev, I1 } }, + { "shrQ", { Ev, I1 } }, + { Bad_Opcode }, + { "sarQ", { Ev, I1 } }, + }, + /* REG_D2 */ + { + { "rolA", { Eb, CL } }, + { "rorA", { Eb, CL } }, + { "rclA", { Eb, CL } }, + { "rcrA", { Eb, CL } }, + { "shlA", { Eb, CL } }, + { "shrA", { Eb, CL } }, + { Bad_Opcode }, + { "sarA", { Eb, CL } }, + }, + /* REG_D3 */ + { + { "rolQ", { Ev, CL } }, + { "rorQ", { Ev, CL } }, + { "rclQ", { Ev, CL } }, + { "rcrQ", { Ev, CL } }, + { "shlQ", { Ev, CL } }, + { "shrQ", { Ev, CL } }, + { Bad_Opcode }, + { "sarQ", { Ev, CL } }, + }, + /* REG_F6 */ + { + { "testA", { Eb, Ib } }, + { Bad_Opcode }, + { "notA", { Eb } }, + { "negA", { Eb } }, + { "mulA", { Eb } }, /* Don't print the implicit %al register, */ + { "imulA", { Eb } }, /* to distinguish these opcodes from other */ + { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ + { "idivA", { Eb } }, /* and idiv for consistency. */ + }, + /* REG_F7 */ + { + { "testQ", { Ev, Iv } }, + { Bad_Opcode }, + { "notQ", { Ev } }, + { "negQ", { Ev } }, + { "mulQ", { Ev } }, /* Don't print the implicit register. */ + { "imulQ", { Ev } }, + { "divQ", { Ev } }, + { "idivQ", { Ev } }, + }, + /* REG_FE */ + { + { "incA", { Eb } }, + { "decA", { Eb } }, + }, + /* REG_FF */ + { + { "incQ", { Ev } }, + { "decQ", { Ev } }, + { "call{T|}", { indirEv } }, + { "Jcall{T|}", { indirEp } }, + { "jmp{T|}", { indirEv } }, + { "Jjmp{T|}", { indirEp } }, + { "pushU", { stackEv } }, + { Bad_Opcode }, + }, + /* REG_0F00 */ + { + { "sldtD", { Sv } }, + { "strD", { Sv } }, + { "lldt", { Ew } }, + { "ltr", { Ew } }, + { "verr", { Ew } }, + { "verw", { Ew } }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* REG_0F01 */ + { + { MOD_TABLE (MOD_0F01_REG_0) }, + { MOD_TABLE (MOD_0F01_REG_1) }, + { MOD_TABLE (MOD_0F01_REG_2) }, + { MOD_TABLE (MOD_0F01_REG_3) }, + { "smswD", { Sv } }, + { Bad_Opcode }, + { "lmsw", { Ew } }, + { MOD_TABLE (MOD_0F01_REG_7) }, + }, + /* REG_0F0D */ + { + { "prefetch", { Mb } }, + { "prefetchw", { Mb } }, + }, + /* REG_0F18 */ + { + { MOD_TABLE (MOD_0F18_REG_0) }, + { MOD_TABLE (MOD_0F18_REG_1) }, + { MOD_TABLE (MOD_0F18_REG_2) }, + { MOD_TABLE (MOD_0F18_REG_3) }, + }, + /* REG_0F71 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F71_REG_2) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F71_REG_4) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F71_REG_6) }, + }, + /* REG_0F72 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F72_REG_2) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F72_REG_4) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F72_REG_6) }, + }, + /* REG_0F73 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F73_REG_2) }, + { MOD_TABLE (MOD_0F73_REG_3) }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F73_REG_6) }, + { MOD_TABLE (MOD_0F73_REG_7) }, + }, + /* REG_0FA6 */ + { + { "montmul", { { OP_0f07, 0 } } }, + { "xsha1", { { OP_0f07, 0 } } }, + { "xsha256", { { OP_0f07, 0 } } }, + }, + /* REG_0FA7 */ + { + { "xstore-rng", { { OP_0f07, 0 } } }, + { "xcrypt-ecb", { { OP_0f07, 0 } } }, + { "xcrypt-cbc", { { OP_0f07, 0 } } }, + { "xcrypt-ctr", { { OP_0f07, 0 } } }, + { "xcrypt-cfb", { { OP_0f07, 0 } } }, + { "xcrypt-ofb", { { OP_0f07, 0 } } }, + }, + /* REG_0FAE */ + { + { MOD_TABLE (MOD_0FAE_REG_0) }, + { MOD_TABLE (MOD_0FAE_REG_1) }, + { MOD_TABLE (MOD_0FAE_REG_2) }, + { MOD_TABLE (MOD_0FAE_REG_3) }, + { MOD_TABLE (MOD_0FAE_REG_4) }, + { MOD_TABLE (MOD_0FAE_REG_5) }, + { MOD_TABLE (MOD_0FAE_REG_6) }, + { MOD_TABLE (MOD_0FAE_REG_7) }, + }, + /* REG_0FBA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "btQ", { Ev, Ib } }, + { "btsQ", { Ev, Ib } }, + { "btrQ", { Ev, Ib } }, + { "btcQ", { Ev, Ib } }, + }, + /* REG_0FC7 */ + { + { Bad_Opcode }, + { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0FC7_REG_6) }, + { MOD_TABLE (MOD_0FC7_REG_7) }, + }, + /* REG_VEX_0F71 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F71_REG_2) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F71_REG_4) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F71_REG_6) }, + }, + /* REG_VEX_0F72 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F72_REG_2) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F72_REG_4) }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F72_REG_6) }, + }, + /* REG_VEX_0F73 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F73_REG_2) }, + { MOD_TABLE (MOD_VEX_0F73_REG_3) }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F73_REG_6) }, + { MOD_TABLE (MOD_VEX_0F73_REG_7) }, + }, + /* REG_VEX_0FAE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, + { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, + }, + /* REG_VEX_0F38F3 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, + { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, + { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, + }, + /* REG_XOP_LWPCB */ + { + { "llwpcb", { { OP_LWPCB_E, 0 } } }, + { "slwpcb", { { OP_LWPCB_E, 0 } } }, + }, + /* REG_XOP_LWP */ + { + { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, + }, + /* REG_XOP_TBM_01 */ + { + { Bad_Opcode }, + { "blcfill", { { OP_LWP_E, 0 }, Ev } }, + { "blsfill", { { OP_LWP_E, 0 }, Ev } }, + { "blcs", { { OP_LWP_E, 0 }, Ev } }, + { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, + { "blcic", { { OP_LWP_E, 0 }, Ev } }, + { "blsic", { { OP_LWP_E, 0 }, Ev } }, + { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, + }, + /* REG_XOP_TBM_02 */ + { + { Bad_Opcode }, + { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "blci", { { OP_LWP_E, 0 }, Ev } }, + }, +}; + +static const struct dis386 prefix_table[][4] = { + /* PREFIX_90 */ + { + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, + { "pause", { XX } }, + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, + }, + + /* PREFIX_0F10 */ + { + { "movups", { XM, EXx } }, + { "movss", { XM, EXd } }, + { "movupd", { XM, EXx } }, + { "movsd", { XM, EXq } }, + }, + + /* PREFIX_0F11 */ + { + { "movups", { EXxS, XM } }, + { "movss", { EXdS, XM } }, + { "movupd", { EXxS, XM } }, + { "movsd", { EXqS, XM } }, + }, + + /* PREFIX_0F12 */ + { + { MOD_TABLE (MOD_0F12_PREFIX_0) }, + { "movsldup", { XM, EXx } }, + { "movlpd", { XM, EXq } }, + { "movddup", { XM, EXq } }, + }, + + /* PREFIX_0F16 */ + { + { MOD_TABLE (MOD_0F16_PREFIX_0) }, + { "movshdup", { XM, EXx } }, + { "movhpd", { XM, EXq } }, + }, + + /* PREFIX_0F2A */ + { + { "cvtpi2ps", { XM, EMCq } }, + { "cvtsi2ss%LQ", { XM, Ev } }, + { "cvtpi2pd", { XM, EMCq } }, + { "cvtsi2sd%LQ", { XM, Ev } }, + }, + + /* PREFIX_0F2B */ + { + { MOD_TABLE (MOD_0F2B_PREFIX_0) }, + { MOD_TABLE (MOD_0F2B_PREFIX_1) }, + { MOD_TABLE (MOD_0F2B_PREFIX_2) }, + { MOD_TABLE (MOD_0F2B_PREFIX_3) }, + }, + + /* PREFIX_0F2C */ + { + { "cvttps2pi", { MXC, EXq } }, + { "cvttss2siY", { Gv, EXd } }, + { "cvttpd2pi", { MXC, EXx } }, + { "cvttsd2siY", { Gv, EXq } }, + }, + + /* PREFIX_0F2D */ + { + { "cvtps2pi", { MXC, EXq } }, + { "cvtss2siY", { Gv, EXd } }, + { "cvtpd2pi", { MXC, EXx } }, + { "cvtsd2siY", { Gv, EXq } }, + }, + + /* PREFIX_0F2E */ + { + { "ucomiss",{ XM, EXd } }, + { Bad_Opcode }, + { "ucomisd",{ XM, EXq } }, + }, + + /* PREFIX_0F2F */ + { + { "comiss", { XM, EXd } }, + { Bad_Opcode }, + { "comisd", { XM, EXq } }, + }, + + /* PREFIX_0F51 */ + { + { "sqrtps", { XM, EXx } }, + { "sqrtss", { XM, EXd } }, + { "sqrtpd", { XM, EXx } }, + { "sqrtsd", { XM, EXq } }, + }, + + /* PREFIX_0F52 */ + { + { "rsqrtps",{ XM, EXx } }, + { "rsqrtss",{ XM, EXd } }, + }, + + /* PREFIX_0F53 */ + { + { "rcpps", { XM, EXx } }, + { "rcpss", { XM, EXd } }, + }, + + /* PREFIX_0F58 */ + { + { "addps", { XM, EXx } }, + { "addss", { XM, EXd } }, + { "addpd", { XM, EXx } }, + { "addsd", { XM, EXq } }, + }, + + /* PREFIX_0F59 */ + { + { "mulps", { XM, EXx } }, + { "mulss", { XM, EXd } }, + { "mulpd", { XM, EXx } }, + { "mulsd", { XM, EXq } }, + }, + + /* PREFIX_0F5A */ + { + { "cvtps2pd", { XM, EXq } }, + { "cvtss2sd", { XM, EXd } }, + { "cvtpd2ps", { XM, EXx } }, + { "cvtsd2ss", { XM, EXq } }, + }, + + /* PREFIX_0F5B */ + { + { "cvtdq2ps", { XM, EXx } }, + { "cvttps2dq", { XM, EXx } }, + { "cvtps2dq", { XM, EXx } }, + }, + + /* PREFIX_0F5C */ + { + { "subps", { XM, EXx } }, + { "subss", { XM, EXd } }, + { "subpd", { XM, EXx } }, + { "subsd", { XM, EXq } }, + }, + + /* PREFIX_0F5D */ + { + { "minps", { XM, EXx } }, + { "minss", { XM, EXd } }, + { "minpd", { XM, EXx } }, + { "minsd", { XM, EXq } }, + }, + + /* PREFIX_0F5E */ + { + { "divps", { XM, EXx } }, + { "divss", { XM, EXd } }, + { "divpd", { XM, EXx } }, + { "divsd", { XM, EXq } }, + }, + + /* PREFIX_0F5F */ + { + { "maxps", { XM, EXx } }, + { "maxss", { XM, EXd } }, + { "maxpd", { XM, EXx } }, + { "maxsd", { XM, EXq } }, + }, + + /* PREFIX_0F60 */ + { + { "punpcklbw",{ MX, EMd } }, + { Bad_Opcode }, + { "punpcklbw",{ MX, EMx } }, + }, + + /* PREFIX_0F61 */ + { + { "punpcklwd",{ MX, EMd } }, + { Bad_Opcode }, + { "punpcklwd",{ MX, EMx } }, + }, + + /* PREFIX_0F62 */ + { + { "punpckldq",{ MX, EMd } }, + { Bad_Opcode }, + { "punpckldq",{ MX, EMx } }, + }, + + /* PREFIX_0F6C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "punpcklqdq", { XM, EXx } }, + }, + + /* PREFIX_0F6D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "punpckhqdq", { XM, EXx } }, + }, + + /* PREFIX_0F6F */ + { + { "movq", { MX, EM } }, + { "movdqu", { XM, EXx } }, + { "movdqa", { XM, EXx } }, + }, + + /* PREFIX_0F70 */ + { + { "pshufw", { MX, EM, Ib } }, + { "pshufhw",{ XM, EXx, Ib } }, + { "pshufd", { XM, EXx, Ib } }, + { "pshuflw",{ XM, EXx, Ib } }, + }, + + /* PREFIX_0F73_REG_3 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "psrldq", { XS, Ib } }, + }, + + /* PREFIX_0F73_REG_7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pslldq", { XS, Ib } }, + }, + + /* PREFIX_0F78 */ + { + {"vmread", { Em, Gm } }, + { Bad_Opcode }, + {"extrq", { XS, Ib, Ib } }, + {"insertq", { XM, XS, Ib, Ib } }, + }, + + /* PREFIX_0F79 */ + { + {"vmwrite", { Gm, Em } }, + { Bad_Opcode }, + {"extrq", { XM, XS } }, + {"insertq", { XM, XS } }, + }, + + /* PREFIX_0F7C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "haddpd", { XM, EXx } }, + { "haddps", { XM, EXx } }, + }, + + /* PREFIX_0F7D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "hsubpd", { XM, EXx } }, + { "hsubps", { XM, EXx } }, + }, + + /* PREFIX_0F7E */ + { + { "movK", { Edq, MX } }, + { "movq", { XM, EXq } }, + { "movK", { Edq, XM } }, + }, + + /* PREFIX_0F7F */ + { + { "movq", { EMS, MX } }, + { "movdqu", { EXxS, XM } }, + { "movdqa", { EXxS, XM } }, + }, + + /* PREFIX_0FAE_REG_0 */ + { + { Bad_Opcode }, + { "rdfsbase", { Ev } }, + }, + + /* PREFIX_0FAE_REG_1 */ + { + { Bad_Opcode }, + { "rdgsbase", { Ev } }, + }, + + /* PREFIX_0FAE_REG_2 */ + { + { Bad_Opcode }, + { "wrfsbase", { Ev } }, + }, + + /* PREFIX_0FAE_REG_3 */ + { + { Bad_Opcode }, + { "wrgsbase", { Ev } }, + }, + + /* PREFIX_0FB8 */ + { + { Bad_Opcode }, + { "popcntS", { Gv, Ev } }, + }, + + /* PREFIX_0FBC */ + { + { "bsfS", { Gv, Ev } }, + { "tzcntS", { Gv, Ev } }, + { "bsfS", { Gv, Ev } }, + }, + + /* PREFIX_0FBD */ + { + { "bsrS", { Gv, Ev } }, + { "lzcntS", { Gv, Ev } }, + { "bsrS", { Gv, Ev } }, + }, + + /* PREFIX_0FC2 */ + { + { "cmpps", { XM, EXx, CMP } }, + { "cmpss", { XM, EXd, CMP } }, + { "cmppd", { XM, EXx, CMP } }, + { "cmpsd", { XM, EXq, CMP } }, + }, + + /* PREFIX_0FC3 */ + { + { "movntiS", { Ma, Gv } }, + }, + + /* PREFIX_0FC7_REG_6 */ + { + { "vmptrld",{ Mq } }, + { "vmxon", { Mq } }, + { "vmclear",{ Mq } }, + }, + + /* PREFIX_0FD0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "addsubpd", { XM, EXx } }, + { "addsubps", { XM, EXx } }, + }, + + /* PREFIX_0FD6 */ + { + { Bad_Opcode }, + { "movq2dq",{ XM, MS } }, + { "movq", { EXqS, XM } }, + { "movdq2q",{ MX, XS } }, + }, + + /* PREFIX_0FE6 */ + { + { Bad_Opcode }, + { "cvtdq2pd", { XM, EXq } }, + { "cvttpd2dq", { XM, EXx } }, + { "cvtpd2dq", { XM, EXx } }, + }, + + /* PREFIX_0FE7 */ + { + { "movntq", { Mq, MX } }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0FE7_PREFIX_2) }, + }, + + /* PREFIX_0FF0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0FF0_PREFIX_3) }, + }, + + /* PREFIX_0FF7 */ + { + { "maskmovq", { MX, MS } }, + { Bad_Opcode }, + { "maskmovdqu", { XM, XS } }, + }, + + /* PREFIX_0F3810 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pblendvb", { XM, EXx, XMM0 } }, + }, + + /* PREFIX_0F3814 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "blendvps", { XM, EXx, XMM0 } }, + }, + + /* PREFIX_0F3815 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "blendvpd", { XM, EXx, XMM0 } }, + }, + + /* PREFIX_0F3817 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "ptest", { XM, EXx } }, + }, + + /* PREFIX_0F3820 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxbw", { XM, EXq } }, + }, + + /* PREFIX_0F3821 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxbd", { XM, EXd } }, + }, + + /* PREFIX_0F3822 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxbq", { XM, EXw } }, + }, + + /* PREFIX_0F3823 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxwd", { XM, EXq } }, + }, + + /* PREFIX_0F3824 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxwq", { XM, EXd } }, + }, + + /* PREFIX_0F3825 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovsxdq", { XM, EXq } }, + }, + + /* PREFIX_0F3828 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmuldq", { XM, EXx } }, + }, + + /* PREFIX_0F3829 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpeqq", { XM, EXx } }, + }, + + /* PREFIX_0F382A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F382A_PREFIX_2) }, + }, + + /* PREFIX_0F382B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "packusdw", { XM, EXx } }, + }, + + /* PREFIX_0F3830 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxbw", { XM, EXq } }, + }, + + /* PREFIX_0F3831 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxbd", { XM, EXd } }, + }, + + /* PREFIX_0F3832 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxbq", { XM, EXw } }, + }, + + /* PREFIX_0F3833 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxwd", { XM, EXq } }, + }, + + /* PREFIX_0F3834 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxwq", { XM, EXd } }, + }, + + /* PREFIX_0F3835 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmovzxdq", { XM, EXq } }, + }, + + /* PREFIX_0F3837 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpgtq", { XM, EXx } }, + }, + + /* PREFIX_0F3838 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pminsb", { XM, EXx } }, + }, + + /* PREFIX_0F3839 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pminsd", { XM, EXx } }, + }, + + /* PREFIX_0F383A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pminuw", { XM, EXx } }, + }, + + /* PREFIX_0F383B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pminud", { XM, EXx } }, + }, + + /* PREFIX_0F383C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmaxsb", { XM, EXx } }, + }, + + /* PREFIX_0F383D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmaxsd", { XM, EXx } }, + }, + + /* PREFIX_0F383E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmaxuw", { XM, EXx } }, + }, + + /* PREFIX_0F383F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmaxud", { XM, EXx } }, + }, + + /* PREFIX_0F3840 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pmulld", { XM, EXx } }, + }, + + /* PREFIX_0F3841 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "phminposuw", { XM, EXx } }, + }, + + /* PREFIX_0F3880 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "invept", { Gm, Mo } }, + }, + + /* PREFIX_0F3881 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "invvpid", { Gm, Mo } }, + }, + + /* PREFIX_0F38DB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aesimc", { XM, EXx } }, + }, + + /* PREFIX_0F38DC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aesenc", { XM, EXx } }, + }, + + /* PREFIX_0F38DD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aesenclast", { XM, EXx } }, + }, + + /* PREFIX_0F38DE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aesdec", { XM, EXx } }, + }, + + /* PREFIX_0F38DF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aesdeclast", { XM, EXx } }, + }, + + /* PREFIX_0F38F0 */ + { + { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, + { Bad_Opcode }, + { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, + { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, + }, + + /* PREFIX_0F38F1 */ + { + { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, + { Bad_Opcode }, + { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, + { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, + }, + + /* PREFIX_0F3A08 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "roundps", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A09 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "roundpd", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A0A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "roundss", { XM, EXd, Ib } }, + }, + + /* PREFIX_0F3A0B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "roundsd", { XM, EXq, Ib } }, + }, + + /* PREFIX_0F3A0C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "blendps", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A0D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "blendpd", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A0E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pblendw", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A14 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pextrb", { Edqb, XM, Ib } }, + }, + + /* PREFIX_0F3A15 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pextrw", { Edqw, XM, Ib } }, + }, + + /* PREFIX_0F3A16 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pextrK", { Edq, XM, Ib } }, + }, + + /* PREFIX_0F3A17 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "extractps", { Edqd, XM, Ib } }, + }, + + /* PREFIX_0F3A20 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pinsrb", { XM, Edqb, Ib } }, + }, + + /* PREFIX_0F3A21 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "insertps", { XM, EXd, Ib } }, + }, + + /* PREFIX_0F3A22 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pinsrK", { XM, Edq, Ib } }, + }, + + /* PREFIX_0F3A40 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "dpps", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A41 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "dppd", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A42 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "mpsadbw", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A44 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pclmulqdq", { XM, EXx, PCLMUL } }, + }, + + /* PREFIX_0F3A60 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpestrm", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A61 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpestri", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A62 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpistrm", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3A63 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "pcmpistri", { XM, EXx, Ib } }, + }, + + /* PREFIX_0F3ADF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "aeskeygenassist", { XM, EXx, Ib } }, + }, + + /* PREFIX_VEX_0F10 */ + { + { VEX_W_TABLE (VEX_W_0F10_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, + { VEX_W_TABLE (VEX_W_0F10_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, + }, + + /* PREFIX_VEX_0F11 */ + { + { VEX_W_TABLE (VEX_W_0F11_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, + { VEX_W_TABLE (VEX_W_0F11_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, + }, + + /* PREFIX_VEX_0F12 */ + { + { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, + { VEX_W_TABLE (VEX_W_0F12_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, + { VEX_W_TABLE (VEX_W_0F12_P_3) }, + }, + + /* PREFIX_VEX_0F16 */ + { + { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, + { VEX_W_TABLE (VEX_W_0F16_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, + }, + + /* PREFIX_VEX_0F2A */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, + }, + + /* PREFIX_VEX_0F2C */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, + }, + + /* PREFIX_VEX_0F2D */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, + }, + + /* PREFIX_VEX_0F2E */ + { + { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, + }, + + /* PREFIX_VEX_0F2F */ + { + { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, + }, + + /* PREFIX_VEX_0F51 */ + { + { VEX_W_TABLE (VEX_W_0F51_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, + { VEX_W_TABLE (VEX_W_0F51_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, + }, + + /* PREFIX_VEX_0F52 */ + { + { VEX_W_TABLE (VEX_W_0F52_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, + }, + + /* PREFIX_VEX_0F53 */ + { + { VEX_W_TABLE (VEX_W_0F53_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, + }, + + /* PREFIX_VEX_0F58 */ + { + { VEX_W_TABLE (VEX_W_0F58_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, + { VEX_W_TABLE (VEX_W_0F58_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, + }, + + /* PREFIX_VEX_0F59 */ + { + { VEX_W_TABLE (VEX_W_0F59_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, + { VEX_W_TABLE (VEX_W_0F59_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, + }, + + /* PREFIX_VEX_0F5A */ + { + { VEX_W_TABLE (VEX_W_0F5A_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, + { "vcvtpd2ps%XY", { XMM, EXx } }, + { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, + }, + + /* PREFIX_VEX_0F5B */ + { + { VEX_W_TABLE (VEX_W_0F5B_P_0) }, + { VEX_W_TABLE (VEX_W_0F5B_P_1) }, + { VEX_W_TABLE (VEX_W_0F5B_P_2) }, + }, + + /* PREFIX_VEX_0F5C */ + { + { VEX_W_TABLE (VEX_W_0F5C_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, + { VEX_W_TABLE (VEX_W_0F5C_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, + }, + + /* PREFIX_VEX_0F5D */ + { + { VEX_W_TABLE (VEX_W_0F5D_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, + { VEX_W_TABLE (VEX_W_0F5D_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, + }, + + /* PREFIX_VEX_0F5E */ + { + { VEX_W_TABLE (VEX_W_0F5E_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, + { VEX_W_TABLE (VEX_W_0F5E_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, + }, + + /* PREFIX_VEX_0F5F */ + { + { VEX_W_TABLE (VEX_W_0F5F_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, + { VEX_W_TABLE (VEX_W_0F5F_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, + }, + + /* PREFIX_VEX_0F60 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) }, + }, + + /* PREFIX_VEX_0F61 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) }, + }, + + /* PREFIX_VEX_0F62 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) }, + }, + + /* PREFIX_VEX_0F63 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) }, + }, + + /* PREFIX_VEX_0F64 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) }, + }, + + /* PREFIX_VEX_0F65 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) }, + }, + + /* PREFIX_VEX_0F66 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) }, + }, + + /* PREFIX_VEX_0F67 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) }, + }, + + /* PREFIX_VEX_0F68 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) }, + }, + + /* PREFIX_VEX_0F69 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) }, + }, + + /* PREFIX_VEX_0F6A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) }, + }, + + /* PREFIX_VEX_0F6B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) }, + }, + + /* PREFIX_VEX_0F6C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) }, + }, + + /* PREFIX_VEX_0F6D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) }, + }, + + /* PREFIX_VEX_0F6E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, + }, + + /* PREFIX_VEX_0F6F */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F6F_P_1) }, + { VEX_W_TABLE (VEX_W_0F6F_P_2) }, + }, + + /* PREFIX_VEX_0F70 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) }, + }, + + /* PREFIX_VEX_0F71_REG_2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) }, + }, + + /* PREFIX_VEX_0F71_REG_4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) }, + }, + + /* PREFIX_VEX_0F71_REG_6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) }, + }, + + /* PREFIX_VEX_0F72_REG_2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) }, + }, + + /* PREFIX_VEX_0F72_REG_4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) }, + }, + + /* PREFIX_VEX_0F72_REG_6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) }, + }, + + /* PREFIX_VEX_0F73_REG_2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) }, + }, + + /* PREFIX_VEX_0F73_REG_3 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) }, + }, + + /* PREFIX_VEX_0F73_REG_6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) }, + }, + + /* PREFIX_VEX_0F73_REG_7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) }, + }, + + /* PREFIX_VEX_0F74 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) }, + }, + + /* PREFIX_VEX_0F75 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) }, + }, + + /* PREFIX_VEX_0F76 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) }, + }, + + /* PREFIX_VEX_0F77 */ + { + { VEX_W_TABLE (VEX_W_0F77_P_0) }, + }, + + /* PREFIX_VEX_0F7C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F7C_P_2) }, + { VEX_W_TABLE (VEX_W_0F7C_P_3) }, + }, + + /* PREFIX_VEX_0F7D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F7D_P_2) }, + { VEX_W_TABLE (VEX_W_0F7D_P_3) }, + }, + + /* PREFIX_VEX_0F7E */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, + { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, + }, + + /* PREFIX_VEX_0F7F */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F7F_P_1) }, + { VEX_W_TABLE (VEX_W_0F7F_P_2) }, + }, + + /* PREFIX_VEX_0FC2 */ + { + { VEX_W_TABLE (VEX_W_0FC2_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, + { VEX_W_TABLE (VEX_W_0FC2_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, + }, + + /* PREFIX_VEX_0FC4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, + }, + + /* PREFIX_VEX_0FC5 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, + }, + + /* PREFIX_VEX_0FD0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0FD0_P_2) }, + { VEX_W_TABLE (VEX_W_0FD0_P_3) }, + }, + + /* PREFIX_VEX_0FD1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) }, + }, + + /* PREFIX_VEX_0FD2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) }, + }, + + /* PREFIX_VEX_0FD3 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) }, + }, + + /* PREFIX_VEX_0FD4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) }, + }, + + /* PREFIX_VEX_0FD5 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) }, + }, + + /* PREFIX_VEX_0FD6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, + }, + + /* PREFIX_VEX_0FD7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, + }, + + /* PREFIX_VEX_0FD8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) }, + }, + + /* PREFIX_VEX_0FD9 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) }, + }, + + /* PREFIX_VEX_0FDA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) }, + }, + + /* PREFIX_VEX_0FDB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) }, + }, + + /* PREFIX_VEX_0FDC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) }, + }, + + /* PREFIX_VEX_0FDD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) }, + }, + + /* PREFIX_VEX_0FDE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) }, + }, + + /* PREFIX_VEX_0FDF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) }, + }, + + /* PREFIX_VEX_0FE0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) }, + }, + + /* PREFIX_VEX_0FE1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) }, + }, + + /* PREFIX_VEX_0FE2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) }, + }, + + /* PREFIX_VEX_0FE3 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) }, + }, + + /* PREFIX_VEX_0FE4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) }, + }, + + /* PREFIX_VEX_0FE5 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) }, + }, + + /* PREFIX_VEX_0FE6 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0FE6_P_1) }, + { VEX_W_TABLE (VEX_W_0FE6_P_2) }, + { VEX_W_TABLE (VEX_W_0FE6_P_3) }, + }, + + /* PREFIX_VEX_0FE7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, + }, + + /* PREFIX_VEX_0FE8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) }, + }, + + /* PREFIX_VEX_0FE9 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) }, + }, + + /* PREFIX_VEX_0FEA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) }, + }, + + /* PREFIX_VEX_0FEB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) }, + }, + + /* PREFIX_VEX_0FEC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) }, + }, + + /* PREFIX_VEX_0FED */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) }, + }, + + /* PREFIX_VEX_0FEE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) }, + }, + + /* PREFIX_VEX_0FEF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) }, + }, + + /* PREFIX_VEX_0FF0 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, + }, + + /* PREFIX_VEX_0FF1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) }, + }, + + /* PREFIX_VEX_0FF2 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) }, + }, + + /* PREFIX_VEX_0FF3 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) }, + }, + + /* PREFIX_VEX_0FF4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) }, + }, + + /* PREFIX_VEX_0FF5 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) }, + }, + + /* PREFIX_VEX_0FF6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) }, + }, + + /* PREFIX_VEX_0FF7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, + }, + + /* PREFIX_VEX_0FF8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) }, + }, + + /* PREFIX_VEX_0FF9 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) }, + }, + + /* PREFIX_VEX_0FFA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) }, + }, + + /* PREFIX_VEX_0FFB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) }, + }, + + /* PREFIX_VEX_0FFC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) }, + }, + + /* PREFIX_VEX_0FFD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) }, + }, + + /* PREFIX_VEX_0FFE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) }, + }, + + /* PREFIX_VEX_0F3800 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) }, + }, + + /* PREFIX_VEX_0F3801 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) }, + }, + + /* PREFIX_VEX_0F3802 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) }, + }, + + /* PREFIX_VEX_0F3803 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) }, + }, + + /* PREFIX_VEX_0F3804 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) }, + }, + + /* PREFIX_VEX_0F3805 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) }, + }, + + /* PREFIX_VEX_0F3806 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) }, + }, + + /* PREFIX_VEX_0F3807 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) }, + }, + + /* PREFIX_VEX_0F3808 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) }, + }, + + /* PREFIX_VEX_0F3809 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) }, + }, + + /* PREFIX_VEX_0F380A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) }, + }, + + /* PREFIX_VEX_0F380B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) }, + }, + + /* PREFIX_VEX_0F380C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F380C_P_2) }, + }, + + /* PREFIX_VEX_0F380D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F380D_P_2) }, + }, + + /* PREFIX_VEX_0F380E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F380E_P_2) }, + }, + + /* PREFIX_VEX_0F380F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F380F_P_2) }, + }, + + /* PREFIX_VEX_0F3813 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vcvtph2ps", { XM, EXxmmq } }, + }, + + /* PREFIX_VEX_0F3817 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3817_P_2) }, + }, + + /* PREFIX_VEX_0F3818 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F3819 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F381A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F381C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) }, + }, + + /* PREFIX_VEX_0F381D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) }, + }, + + /* PREFIX_VEX_0F381E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) }, + }, + + /* PREFIX_VEX_0F3820 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) }, + }, + + /* PREFIX_VEX_0F3821 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) }, + }, + + /* PREFIX_VEX_0F3822 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) }, + }, + + /* PREFIX_VEX_0F3823 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) }, + }, + + /* PREFIX_VEX_0F3824 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) }, + }, + + /* PREFIX_VEX_0F3825 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) }, + }, + + /* PREFIX_VEX_0F3828 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) }, + }, + + /* PREFIX_VEX_0F3829 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) }, + }, + + /* PREFIX_VEX_0F382A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F382B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) }, + }, + + /* PREFIX_VEX_0F382C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F382D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F382E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F382F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, + }, + + /* PREFIX_VEX_0F3830 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) }, + }, + + /* PREFIX_VEX_0F3831 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) }, + }, + + /* PREFIX_VEX_0F3832 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) }, + }, + + /* PREFIX_VEX_0F3833 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) }, + }, + + /* PREFIX_VEX_0F3834 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) }, + }, + + /* PREFIX_VEX_0F3835 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) }, + }, + + /* PREFIX_VEX_0F3837 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) }, + }, + + /* PREFIX_VEX_0F3838 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) }, + }, + + /* PREFIX_VEX_0F3839 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) }, + }, + + /* PREFIX_VEX_0F383A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) }, + }, + + /* PREFIX_VEX_0F383B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) }, + }, + + /* PREFIX_VEX_0F383C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) }, + }, + + /* PREFIX_VEX_0F383D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) }, + }, + + /* PREFIX_VEX_0F383E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) }, + }, + + /* PREFIX_VEX_0F383F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) }, + }, + + /* PREFIX_VEX_0F3840 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) }, + }, + + /* PREFIX_VEX_0F3841 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, + }, + + /* PREFIX_VEX_0F3896 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F3897 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubadd132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F3898 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F3899 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F389A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F389B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F389C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F389D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F389E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub132p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F389F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38A6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub213p%XW", { XM, Vex, EXx } }, + { Bad_Opcode }, + }, + + /* PREFIX_VEX_0F38A7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubadd213p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38A8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd213p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38A9 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38AA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub213p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38AB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38AC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd213p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38AD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38AE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub213p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38AF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38B6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38B7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubadd231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38B8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38B9 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38BA */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38BB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38BC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38BD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38BE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub231p%XW", { XM, Vex, EXx } }, + }, + + /* PREFIX_VEX_0F38BF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + }, + + /* PREFIX_VEX_0F38DB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, + }, + + /* PREFIX_VEX_0F38DC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, + }, + + /* PREFIX_VEX_0F38DD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, + }, + + /* PREFIX_VEX_0F38DE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, + }, + + /* PREFIX_VEX_0F38DF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, + }, + + /* PREFIX_VEX_0F38F2 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, + }, + + /* PREFIX_VEX_0F38F3_REG_1 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, + }, + + /* PREFIX_VEX_0F38F3_REG_2 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, + }, + + /* PREFIX_VEX_0F38F3_REG_3 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, + }, + + /* PREFIX_VEX_0F38F7 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, + }, + + /* PREFIX_VEX_0F3A04 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, + }, + + /* PREFIX_VEX_0F3A05 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, + }, + + /* PREFIX_VEX_0F3A06 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, + }, + + /* PREFIX_VEX_0F3A08 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, + }, + + /* PREFIX_VEX_0F3A09 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, + }, + + /* PREFIX_VEX_0F3A0A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, + }, + + /* PREFIX_VEX_0F3A0B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, + }, + + /* PREFIX_VEX_0F3A0C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, + }, + + /* PREFIX_VEX_0F3A0D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, + }, + + /* PREFIX_VEX_0F3A0E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) }, + }, + + /* PREFIX_VEX_0F3A0F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) }, + }, + + /* PREFIX_VEX_0F3A14 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, + }, + + /* PREFIX_VEX_0F3A15 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, + }, + + /* PREFIX_VEX_0F3A16 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, + }, + + /* PREFIX_VEX_0F3A17 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, + }, + + /* PREFIX_VEX_0F3A18 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, + }, + + /* PREFIX_VEX_0F3A19 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, + }, + + /* PREFIX_VEX_0F3A1D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vcvtps2ph", { EXxmmq, XM, Ib } }, + }, + + /* PREFIX_VEX_0F3A20 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, + }, + + /* PREFIX_VEX_0F3A21 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, + }, + + /* PREFIX_VEX_0F3A22 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, + }, + + /* PREFIX_VEX_0F3A40 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, + }, + + /* PREFIX_VEX_0F3A41 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, + }, + + /* PREFIX_VEX_0F3A42 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) }, + }, + + /* PREFIX_VEX_0F3A44 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, + }, + + /* PREFIX_VEX_0F3A48 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, + }, + + /* PREFIX_VEX_0F3A49 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, + }, + + /* PREFIX_VEX_0F3A4A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, + }, + + /* PREFIX_VEX_0F3A4B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, + }, + + /* PREFIX_VEX_0F3A4C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) }, + }, + + /* PREFIX_VEX_0F3A5C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A5D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A5E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A5F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A60 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, + { Bad_Opcode }, + }, + + /* PREFIX_VEX_0F3A61 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, + }, + + /* PREFIX_VEX_0F3A62 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, + }, + + /* PREFIX_VEX_0F3A63 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, + }, + + /* PREFIX_VEX_0F3A68 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A69 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A6A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, + }, + + /* PREFIX_VEX_0F3A6B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, + }, + + /* PREFIX_VEX_0F3A6C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A6D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A6E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, + }, + + /* PREFIX_VEX_0F3A6F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, + }, + + /* PREFIX_VEX_0F3A78 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A79 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A7A */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, + }, + + /* PREFIX_VEX_0F3A7B */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, + }, + + /* PREFIX_VEX_0F3A7C */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { Bad_Opcode }, + }, + + /* PREFIX_VEX_0F3A7D */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + }, + + /* PREFIX_VEX_0F3A7E */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, + }, + + /* PREFIX_VEX_0F3A7F */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, + }, + + /* PREFIX_VEX_0F3ADF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, + }, +}; + +static const struct dis386 x86_64_table[][2] = { + /* X86_64_06 */ + { + { "pushP", { es } }, + }, + + /* X86_64_07 */ + { + { "popP", { es } }, + }, + + /* X86_64_0D */ + { + { "pushP", { cs } }, + }, + + /* X86_64_16 */ + { + { "pushP", { ss } }, + }, + + /* X86_64_17 */ + { + { "popP", { ss } }, + }, + + /* X86_64_1E */ + { + { "pushP", { ds } }, + }, + + /* X86_64_1F */ + { + { "popP", { ds } }, + }, + + /* X86_64_27 */ + { + { "daa", { XX } }, + }, + + /* X86_64_2F */ + { + { "das", { XX } }, + }, + + /* X86_64_37 */ + { + { "aaa", { XX } }, + }, + + /* X86_64_3F */ + { + { "aas", { XX } }, + }, + + /* X86_64_60 */ + { + { "pushaP", { XX } }, + }, + + /* X86_64_61 */ + { + { "popaP", { XX } }, + }, + + /* X86_64_62 */ + { + { MOD_TABLE (MOD_62_32BIT) }, + }, + + /* X86_64_63 */ + { + { "arpl", { Ew, Gw } }, + { "movs{lq|xd}", { Gv, Ed } }, + }, + + /* X86_64_6D */ + { + { "ins{R|}", { Yzr, indirDX } }, + { "ins{G|}", { Yzr, indirDX } }, + }, + + /* X86_64_6F */ + { + { "outs{R|}", { indirDXr, Xz } }, + { "outs{G|}", { indirDXr, Xz } }, + }, + + /* X86_64_9A */ + { + { "Jcall{T|}", { Ap } }, + }, + + /* X86_64_C4 */ + { + { MOD_TABLE (MOD_C4_32BIT) }, + { VEX_C4_TABLE (VEX_0F) }, + }, + + /* X86_64_C5 */ + { + { MOD_TABLE (MOD_C5_32BIT) }, + { VEX_C5_TABLE (VEX_0F) }, + }, + + /* X86_64_CE */ + { + { "into", { XX } }, + }, + + /* X86_64_D4 */ + { + { "aam", { Ib } }, + }, + + /* X86_64_D5 */ + { + { "aad", { Ib } }, + }, + + /* X86_64_EA */ + { + { "Jjmp{T|}", { Ap } }, + }, + + /* X86_64_0F01_REG_0 */ + { + { "sgdt{Q|IQ}", { M } }, + { "sgdt", { M } }, + }, + + /* X86_64_0F01_REG_1 */ + { + { "sidt{Q|IQ}", { M } }, + { "sidt", { M } }, + }, + + /* X86_64_0F01_REG_2 */ + { + { "lgdt{Q|Q}", { M } }, + { "lgdt", { M } }, + }, + + /* X86_64_0F01_REG_3 */ + { + { "lidt{Q|Q}", { M } }, + { "lidt", { M } }, + }, +}; + +static const struct dis386 three_byte_table[][256] = { + + /* THREE_BYTE_0F38 */ + { + /* 00 */ + { "pshufb", { MX, EM } }, + { "phaddw", { MX, EM } }, + { "phaddd", { MX, EM } }, + { "phaddsw", { MX, EM } }, + { "pmaddubsw", { MX, EM } }, + { "phsubw", { MX, EM } }, + { "phsubd", { MX, EM } }, + { "phsubsw", { MX, EM } }, + /* 08 */ + { "psignb", { MX, EM } }, + { "psignw", { MX, EM } }, + { "psignd", { MX, EM } }, + { "pmulhrsw", { MX, EM } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { PREFIX_TABLE (PREFIX_0F3810) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3814) }, + { PREFIX_TABLE (PREFIX_0F3815) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3817) }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "pabsb", { MX, EM } }, + { "pabsw", { MX, EM } }, + { "pabsd", { MX, EM } }, + { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_0F3820) }, + { PREFIX_TABLE (PREFIX_0F3821) }, + { PREFIX_TABLE (PREFIX_0F3822) }, + { PREFIX_TABLE (PREFIX_0F3823) }, + { PREFIX_TABLE (PREFIX_0F3824) }, + { PREFIX_TABLE (PREFIX_0F3825) }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { PREFIX_TABLE (PREFIX_0F3828) }, + { PREFIX_TABLE (PREFIX_0F3829) }, + { PREFIX_TABLE (PREFIX_0F382A) }, + { PREFIX_TABLE (PREFIX_0F382B) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { PREFIX_TABLE (PREFIX_0F3830) }, + { PREFIX_TABLE (PREFIX_0F3831) }, + { PREFIX_TABLE (PREFIX_0F3832) }, + { PREFIX_TABLE (PREFIX_0F3833) }, + { PREFIX_TABLE (PREFIX_0F3834) }, + { PREFIX_TABLE (PREFIX_0F3835) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3837) }, + /* 38 */ + { PREFIX_TABLE (PREFIX_0F3838) }, + { PREFIX_TABLE (PREFIX_0F3839) }, + { PREFIX_TABLE (PREFIX_0F383A) }, + { PREFIX_TABLE (PREFIX_0F383B) }, + { PREFIX_TABLE (PREFIX_0F383C) }, + { PREFIX_TABLE (PREFIX_0F383D) }, + { PREFIX_TABLE (PREFIX_0F383E) }, + { PREFIX_TABLE (PREFIX_0F383F) }, + /* 40 */ + { PREFIX_TABLE (PREFIX_0F3840) }, + { PREFIX_TABLE (PREFIX_0F3841) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { PREFIX_TABLE (PREFIX_0F3880) }, + { PREFIX_TABLE (PREFIX_0F3881) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38DB) }, + { PREFIX_TABLE (PREFIX_0F38DC) }, + { PREFIX_TABLE (PREFIX_0F38DD) }, + { PREFIX_TABLE (PREFIX_0F38DE) }, + { PREFIX_TABLE (PREFIX_0F38DF) }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { PREFIX_TABLE (PREFIX_0F38F0) }, + { PREFIX_TABLE (PREFIX_0F38F1) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* THREE_BYTE_0F3A */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { PREFIX_TABLE (PREFIX_0F3A08) }, + { PREFIX_TABLE (PREFIX_0F3A09) }, + { PREFIX_TABLE (PREFIX_0F3A0A) }, + { PREFIX_TABLE (PREFIX_0F3A0B) }, + { PREFIX_TABLE (PREFIX_0F3A0C) }, + { PREFIX_TABLE (PREFIX_0F3A0D) }, + { PREFIX_TABLE (PREFIX_0F3A0E) }, + { "palignr", { MX, EM, Ib } }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3A14) }, + { PREFIX_TABLE (PREFIX_0F3A15) }, + { PREFIX_TABLE (PREFIX_0F3A16) }, + { PREFIX_TABLE (PREFIX_0F3A17) }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_0F3A20) }, + { PREFIX_TABLE (PREFIX_0F3A21) }, + { PREFIX_TABLE (PREFIX_0F3A22) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { PREFIX_TABLE (PREFIX_0F3A40) }, + { PREFIX_TABLE (PREFIX_0F3A41) }, + { PREFIX_TABLE (PREFIX_0F3A42) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3A44) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { PREFIX_TABLE (PREFIX_0F3A60) }, + { PREFIX_TABLE (PREFIX_0F3A61) }, + { PREFIX_TABLE (PREFIX_0F3A62) }, + { PREFIX_TABLE (PREFIX_0F3A63) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3ADF) }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + + /* THREE_BYTE_0F7A */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { "ptest", { XX } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { "phaddbw", { XM, EXq } }, + { "phaddbd", { XM, EXq } }, + { "phaddbq", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "phaddwd", { XM, EXq } }, + { "phaddwq", { XM, EXq } }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "phadddq", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { "phaddubw", { XM, EXq } }, + { "phaddubd", { XM, EXq } }, + { "phaddubq", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "phadduwd", { XM, EXq } }, + { "phadduwq", { XM, EXq } }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "phaddudq", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { "phsubbw", { XM, EXq } }, + { "phsubbd", { XM, EXq } }, + { "phsubbq", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, +}; + +static const struct dis386 xop_table[][256] = { + /* XOP_08 */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { "bextr", { Gv, Ev, Iq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { "vprotb", { XM, Vex_2src_1, Ib } }, + { "vprotw", { XM, Vex_2src_1, Ib } }, + { "vprotd", { XM, Vex_2src_1, Ib } }, + { "vprotq", { XM, Vex_2src_1, Ib } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpcomb", { XM, Vex128, EXx, Ib } }, + { "vpcomw", { XM, Vex128, EXx, Ib } }, + { "vpcomd", { XM, Vex128, EXx, Ib } }, + { "vpcomq", { XM, Vex128, EXx, Ib } }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vpcomub", { XM, Vex128, EXx, Ib } }, + { "vpcomuw", { XM, Vex128, EXx, Ib } }, + { "vpcomud", { XM, Vex128, EXx, Ib } }, + { "vpcomuq", { XM, Vex128, EXx, Ib } }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* XOP_09 */ + { + /* 00 */ + { Bad_Opcode }, + { REG_TABLE (REG_XOP_TBM_01) }, + { REG_TABLE (REG_XOP_TBM_02) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { REG_TABLE (REG_XOP_LWPCB) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, + { "vfrczss", { XM, EXd } }, + { "vfrczsd", { XM, EXq } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, + /* 98 */ + { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { "vphaddbw", { XM, EXxmm } }, + { "vphaddbd", { XM, EXxmm } }, + { "vphaddbq", { XM, EXxmm } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vphaddwd", { XM, EXxmm } }, + { "vphaddwq", { XM, EXxmm } }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vphadddq", { XM, EXxmm } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { "vphaddubw", { XM, EXxmm } }, + { "vphaddubd", { XM, EXxmm } }, + { "vphaddubq", { XM, EXxmm } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vphadduwd", { XM, EXxmm } }, + { "vphadduwq", { XM, EXxmm } }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vphaddudq", { XM, EXxmm } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { "vphsubbw", { XM, EXxmm } }, + { "vphsubwd", { XM, EXxmm } }, + { "vphsubdq", { XM, EXxmm } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* XOP_0A */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { "bextr", { Gv, Ev, Iq } }, + { Bad_Opcode }, + { REG_TABLE (REG_XOP_LWP) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, +}; + +static const struct dis386 vex_table[][256] = { + /* VEX_0F */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { PREFIX_TABLE (PREFIX_VEX_0F10) }, + { PREFIX_TABLE (PREFIX_VEX_0F11) }, + { PREFIX_TABLE (PREFIX_VEX_0F12) }, + { MOD_TABLE (MOD_VEX_0F13) }, + { VEX_W_TABLE (VEX_W_0F14) }, + { VEX_W_TABLE (VEX_W_0F15) }, + { PREFIX_TABLE (PREFIX_VEX_0F16) }, + { MOD_TABLE (MOD_VEX_0F17) }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { VEX_W_TABLE (VEX_W_0F28) }, + { VEX_W_TABLE (VEX_W_0F29) }, + { PREFIX_TABLE (PREFIX_VEX_0F2A) }, + { MOD_TABLE (MOD_VEX_0F2B) }, + { PREFIX_TABLE (PREFIX_VEX_0F2C) }, + { PREFIX_TABLE (PREFIX_VEX_0F2D) }, + { PREFIX_TABLE (PREFIX_VEX_0F2E) }, + { PREFIX_TABLE (PREFIX_VEX_0F2F) }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { MOD_TABLE (MOD_VEX_0F50) }, + { PREFIX_TABLE (PREFIX_VEX_0F51) }, + { PREFIX_TABLE (PREFIX_VEX_0F52) }, + { PREFIX_TABLE (PREFIX_VEX_0F53) }, + { "vandpX", { XM, Vex, EXx } }, + { "vandnpX", { XM, Vex, EXx } }, + { "vorpX", { XM, Vex, EXx } }, + { "vxorpX", { XM, Vex, EXx } }, + /* 58 */ + { PREFIX_TABLE (PREFIX_VEX_0F58) }, + { PREFIX_TABLE (PREFIX_VEX_0F59) }, + { PREFIX_TABLE (PREFIX_VEX_0F5A) }, + { PREFIX_TABLE (PREFIX_VEX_0F5B) }, + { PREFIX_TABLE (PREFIX_VEX_0F5C) }, + { PREFIX_TABLE (PREFIX_VEX_0F5D) }, + { PREFIX_TABLE (PREFIX_VEX_0F5E) }, + { PREFIX_TABLE (PREFIX_VEX_0F5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_VEX_0F60) }, + { PREFIX_TABLE (PREFIX_VEX_0F61) }, + { PREFIX_TABLE (PREFIX_VEX_0F62) }, + { PREFIX_TABLE (PREFIX_VEX_0F63) }, + { PREFIX_TABLE (PREFIX_VEX_0F64) }, + { PREFIX_TABLE (PREFIX_VEX_0F65) }, + { PREFIX_TABLE (PREFIX_VEX_0F66) }, + { PREFIX_TABLE (PREFIX_VEX_0F67) }, + /* 68 */ + { PREFIX_TABLE (PREFIX_VEX_0F68) }, + { PREFIX_TABLE (PREFIX_VEX_0F69) }, + { PREFIX_TABLE (PREFIX_VEX_0F6A) }, + { PREFIX_TABLE (PREFIX_VEX_0F6B) }, + { PREFIX_TABLE (PREFIX_VEX_0F6C) }, + { PREFIX_TABLE (PREFIX_VEX_0F6D) }, + { PREFIX_TABLE (PREFIX_VEX_0F6E) }, + { PREFIX_TABLE (PREFIX_VEX_0F6F) }, + /* 70 */ + { PREFIX_TABLE (PREFIX_VEX_0F70) }, + { REG_TABLE (REG_VEX_0F71) }, + { REG_TABLE (REG_VEX_0F72) }, + { REG_TABLE (REG_VEX_0F73) }, + { PREFIX_TABLE (PREFIX_VEX_0F74) }, + { PREFIX_TABLE (PREFIX_VEX_0F75) }, + { PREFIX_TABLE (PREFIX_VEX_0F76) }, + { PREFIX_TABLE (PREFIX_VEX_0F77) }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F7C) }, + { PREFIX_TABLE (PREFIX_VEX_0F7D) }, + { PREFIX_TABLE (PREFIX_VEX_0F7E) }, + { PREFIX_TABLE (PREFIX_VEX_0F7F) }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { REG_TABLE (REG_VEX_0FAE) }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FC2) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FC4) }, + { PREFIX_TABLE (PREFIX_VEX_0FC5) }, + { "vshufpX", { XM, Vex, EXx, Ib } }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { PREFIX_TABLE (PREFIX_VEX_0FD0) }, + { PREFIX_TABLE (PREFIX_VEX_0FD1) }, + { PREFIX_TABLE (PREFIX_VEX_0FD2) }, + { PREFIX_TABLE (PREFIX_VEX_0FD3) }, + { PREFIX_TABLE (PREFIX_VEX_0FD4) }, + { PREFIX_TABLE (PREFIX_VEX_0FD5) }, + { PREFIX_TABLE (PREFIX_VEX_0FD6) }, + { PREFIX_TABLE (PREFIX_VEX_0FD7) }, + /* d8 */ + { PREFIX_TABLE (PREFIX_VEX_0FD8) }, + { PREFIX_TABLE (PREFIX_VEX_0FD9) }, + { PREFIX_TABLE (PREFIX_VEX_0FDA) }, + { PREFIX_TABLE (PREFIX_VEX_0FDB) }, + { PREFIX_TABLE (PREFIX_VEX_0FDC) }, + { PREFIX_TABLE (PREFIX_VEX_0FDD) }, + { PREFIX_TABLE (PREFIX_VEX_0FDE) }, + { PREFIX_TABLE (PREFIX_VEX_0FDF) }, + /* e0 */ + { PREFIX_TABLE (PREFIX_VEX_0FE0) }, + { PREFIX_TABLE (PREFIX_VEX_0FE1) }, + { PREFIX_TABLE (PREFIX_VEX_0FE2) }, + { PREFIX_TABLE (PREFIX_VEX_0FE3) }, + { PREFIX_TABLE (PREFIX_VEX_0FE4) }, + { PREFIX_TABLE (PREFIX_VEX_0FE5) }, + { PREFIX_TABLE (PREFIX_VEX_0FE6) }, + { PREFIX_TABLE (PREFIX_VEX_0FE7) }, + /* e8 */ + { PREFIX_TABLE (PREFIX_VEX_0FE8) }, + { PREFIX_TABLE (PREFIX_VEX_0FE9) }, + { PREFIX_TABLE (PREFIX_VEX_0FEA) }, + { PREFIX_TABLE (PREFIX_VEX_0FEB) }, + { PREFIX_TABLE (PREFIX_VEX_0FEC) }, + { PREFIX_TABLE (PREFIX_VEX_0FED) }, + { PREFIX_TABLE (PREFIX_VEX_0FEE) }, + { PREFIX_TABLE (PREFIX_VEX_0FEF) }, + /* f0 */ + { PREFIX_TABLE (PREFIX_VEX_0FF0) }, + { PREFIX_TABLE (PREFIX_VEX_0FF1) }, + { PREFIX_TABLE (PREFIX_VEX_0FF2) }, + { PREFIX_TABLE (PREFIX_VEX_0FF3) }, + { PREFIX_TABLE (PREFIX_VEX_0FF4) }, + { PREFIX_TABLE (PREFIX_VEX_0FF5) }, + { PREFIX_TABLE (PREFIX_VEX_0FF6) }, + { PREFIX_TABLE (PREFIX_VEX_0FF7) }, + /* f8 */ + { PREFIX_TABLE (PREFIX_VEX_0FF8) }, + { PREFIX_TABLE (PREFIX_VEX_0FF9) }, + { PREFIX_TABLE (PREFIX_VEX_0FFA) }, + { PREFIX_TABLE (PREFIX_VEX_0FFB) }, + { PREFIX_TABLE (PREFIX_VEX_0FFC) }, + { PREFIX_TABLE (PREFIX_VEX_0FFD) }, + { PREFIX_TABLE (PREFIX_VEX_0FFE) }, + { Bad_Opcode }, + }, + /* VEX_0F38 */ + { + /* 00 */ + { PREFIX_TABLE (PREFIX_VEX_0F3800) }, + { PREFIX_TABLE (PREFIX_VEX_0F3801) }, + { PREFIX_TABLE (PREFIX_VEX_0F3802) }, + { PREFIX_TABLE (PREFIX_VEX_0F3803) }, + { PREFIX_TABLE (PREFIX_VEX_0F3804) }, + { PREFIX_TABLE (PREFIX_VEX_0F3805) }, + { PREFIX_TABLE (PREFIX_VEX_0F3806) }, + { PREFIX_TABLE (PREFIX_VEX_0F3807) }, + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_0F3808) }, + { PREFIX_TABLE (PREFIX_VEX_0F3809) }, + { PREFIX_TABLE (PREFIX_VEX_0F380A) }, + { PREFIX_TABLE (PREFIX_VEX_0F380B) }, + { PREFIX_TABLE (PREFIX_VEX_0F380C) }, + { PREFIX_TABLE (PREFIX_VEX_0F380D) }, + { PREFIX_TABLE (PREFIX_VEX_0F380E) }, + { PREFIX_TABLE (PREFIX_VEX_0F380F) }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3813) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3817) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_0F3818) }, + { PREFIX_TABLE (PREFIX_VEX_0F3819) }, + { PREFIX_TABLE (PREFIX_VEX_0F381A) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F381C) }, + { PREFIX_TABLE (PREFIX_VEX_0F381D) }, + { PREFIX_TABLE (PREFIX_VEX_0F381E) }, + { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_0F3820) }, + { PREFIX_TABLE (PREFIX_VEX_0F3821) }, + { PREFIX_TABLE (PREFIX_VEX_0F3822) }, + { PREFIX_TABLE (PREFIX_VEX_0F3823) }, + { PREFIX_TABLE (PREFIX_VEX_0F3824) }, + { PREFIX_TABLE (PREFIX_VEX_0F3825) }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { PREFIX_TABLE (PREFIX_VEX_0F3828) }, + { PREFIX_TABLE (PREFIX_VEX_0F3829) }, + { PREFIX_TABLE (PREFIX_VEX_0F382A) }, + { PREFIX_TABLE (PREFIX_VEX_0F382B) }, + { PREFIX_TABLE (PREFIX_VEX_0F382C) }, + { PREFIX_TABLE (PREFIX_VEX_0F382D) }, + { PREFIX_TABLE (PREFIX_VEX_0F382E) }, + { PREFIX_TABLE (PREFIX_VEX_0F382F) }, + /* 30 */ + { PREFIX_TABLE (PREFIX_VEX_0F3830) }, + { PREFIX_TABLE (PREFIX_VEX_0F3831) }, + { PREFIX_TABLE (PREFIX_VEX_0F3832) }, + { PREFIX_TABLE (PREFIX_VEX_0F3833) }, + { PREFIX_TABLE (PREFIX_VEX_0F3834) }, + { PREFIX_TABLE (PREFIX_VEX_0F3835) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3837) }, + /* 38 */ + { PREFIX_TABLE (PREFIX_VEX_0F3838) }, + { PREFIX_TABLE (PREFIX_VEX_0F3839) }, + { PREFIX_TABLE (PREFIX_VEX_0F383A) }, + { PREFIX_TABLE (PREFIX_VEX_0F383B) }, + { PREFIX_TABLE (PREFIX_VEX_0F383C) }, + { PREFIX_TABLE (PREFIX_VEX_0F383D) }, + { PREFIX_TABLE (PREFIX_VEX_0F383E) }, + { PREFIX_TABLE (PREFIX_VEX_0F383F) }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_0F3840) }, + { PREFIX_TABLE (PREFIX_VEX_0F3841) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3896) }, + { PREFIX_TABLE (PREFIX_VEX_0F3897) }, + /* 98 */ + { PREFIX_TABLE (PREFIX_VEX_0F3898) }, + { PREFIX_TABLE (PREFIX_VEX_0F3899) }, + { PREFIX_TABLE (PREFIX_VEX_0F389A) }, + { PREFIX_TABLE (PREFIX_VEX_0F389B) }, + { PREFIX_TABLE (PREFIX_VEX_0F389C) }, + { PREFIX_TABLE (PREFIX_VEX_0F389D) }, + { PREFIX_TABLE (PREFIX_VEX_0F389E) }, + { PREFIX_TABLE (PREFIX_VEX_0F389F) }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, + { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, + /* a8 */ + { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, + { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, + { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, + /* b8 */ + { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, + { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, + { REG_TABLE (REG_VEX_0F38F3) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* VEX_0F3A */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, + { Bad_Opcode }, + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* a8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* b8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* c8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* d8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, + /* e0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* f8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, +}; + +static const struct dis386 vex_len_table[][2] = { + /* VEX_LEN_0F10_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F10_P_1) }, + { VEX_W_TABLE (VEX_W_0F10_P_1) }, + }, + + /* VEX_LEN_0F10_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F10_P_3) }, + { VEX_W_TABLE (VEX_W_0F10_P_3) }, + }, + + /* VEX_LEN_0F11_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F11_P_1) }, + { VEX_W_TABLE (VEX_W_0F11_P_1) }, + }, + + /* VEX_LEN_0F11_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F11_P_3) }, + { VEX_W_TABLE (VEX_W_0F11_P_3) }, + }, + + /* VEX_LEN_0F12_P_0_M_0 */ + { + { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, + }, + + /* VEX_LEN_0F12_P_0_M_1 */ + { + { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, + }, + + /* VEX_LEN_0F12_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F12_P_2) }, + }, + + /* VEX_LEN_0F13_M_0 */ + { + { VEX_W_TABLE (VEX_W_0F13_M_0) }, + }, + + /* VEX_LEN_0F16_P_0_M_0 */ + { + { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, + }, + + /* VEX_LEN_0F16_P_0_M_1 */ + { + { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, + }, + + /* VEX_LEN_0F16_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F16_P_2) }, + }, + + /* VEX_LEN_0F17_M_0 */ + { + { VEX_W_TABLE (VEX_W_0F17_M_0) }, + }, + + /* VEX_LEN_0F2A_P_1 */ + { + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, + }, + + /* VEX_LEN_0F2A_P_3 */ + { + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, + }, + + /* VEX_LEN_0F2C_P_1 */ + { + { "vcvttss2siY", { Gv, EXdScalar } }, + { "vcvttss2siY", { Gv, EXdScalar } }, + }, + + /* VEX_LEN_0F2C_P_3 */ + { + { "vcvttsd2siY", { Gv, EXqScalar } }, + { "vcvttsd2siY", { Gv, EXqScalar } }, + }, + + /* VEX_LEN_0F2D_P_1 */ + { + { "vcvtss2siY", { Gv, EXdScalar } }, + { "vcvtss2siY", { Gv, EXdScalar } }, + }, + + /* VEX_LEN_0F2D_P_3 */ + { + { "vcvtsd2siY", { Gv, EXqScalar } }, + { "vcvtsd2siY", { Gv, EXqScalar } }, + }, + + /* VEX_LEN_0F2E_P_0 */ + { + { VEX_W_TABLE (VEX_W_0F2E_P_0) }, + { VEX_W_TABLE (VEX_W_0F2E_P_0) }, + }, + + /* VEX_LEN_0F2E_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F2E_P_2) }, + { VEX_W_TABLE (VEX_W_0F2E_P_2) }, + }, + + /* VEX_LEN_0F2F_P_0 */ + { + { VEX_W_TABLE (VEX_W_0F2F_P_0) }, + { VEX_W_TABLE (VEX_W_0F2F_P_0) }, + }, + + /* VEX_LEN_0F2F_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F2F_P_2) }, + { VEX_W_TABLE (VEX_W_0F2F_P_2) }, + }, + + /* VEX_LEN_0F51_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F51_P_1) }, + { VEX_W_TABLE (VEX_W_0F51_P_1) }, + }, + + /* VEX_LEN_0F51_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F51_P_3) }, + { VEX_W_TABLE (VEX_W_0F51_P_3) }, + }, + + /* VEX_LEN_0F52_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F52_P_1) }, + { VEX_W_TABLE (VEX_W_0F52_P_1) }, + }, + + /* VEX_LEN_0F53_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F53_P_1) }, + { VEX_W_TABLE (VEX_W_0F53_P_1) }, + }, + + /* VEX_LEN_0F58_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F58_P_1) }, + { VEX_W_TABLE (VEX_W_0F58_P_1) }, + }, + + /* VEX_LEN_0F58_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F58_P_3) }, + { VEX_W_TABLE (VEX_W_0F58_P_3) }, + }, + + /* VEX_LEN_0F59_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F59_P_1) }, + { VEX_W_TABLE (VEX_W_0F59_P_1) }, + }, + + /* VEX_LEN_0F59_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F59_P_3) }, + { VEX_W_TABLE (VEX_W_0F59_P_3) }, + }, + + /* VEX_LEN_0F5A_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F5A_P_1) }, + { VEX_W_TABLE (VEX_W_0F5A_P_1) }, + }, + + /* VEX_LEN_0F5A_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F5A_P_3) }, + { VEX_W_TABLE (VEX_W_0F5A_P_3) }, + }, + + /* VEX_LEN_0F5C_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F5C_P_1) }, + { VEX_W_TABLE (VEX_W_0F5C_P_1) }, + }, + + /* VEX_LEN_0F5C_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F5C_P_3) }, + { VEX_W_TABLE (VEX_W_0F5C_P_3) }, + }, + + /* VEX_LEN_0F5D_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F5D_P_1) }, + { VEX_W_TABLE (VEX_W_0F5D_P_1) }, + }, + + /* VEX_LEN_0F5D_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F5D_P_3) }, + { VEX_W_TABLE (VEX_W_0F5D_P_3) }, + }, + + /* VEX_LEN_0F5E_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F5E_P_1) }, + { VEX_W_TABLE (VEX_W_0F5E_P_1) }, + }, + + /* VEX_LEN_0F5E_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F5E_P_3) }, + { VEX_W_TABLE (VEX_W_0F5E_P_3) }, + }, + + /* VEX_LEN_0F5F_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F5F_P_1) }, + { VEX_W_TABLE (VEX_W_0F5F_P_1) }, + }, + + /* VEX_LEN_0F5F_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F5F_P_3) }, + { VEX_W_TABLE (VEX_W_0F5F_P_3) }, + }, + + /* VEX_LEN_0F60_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F60_P_2) }, + }, + + /* VEX_LEN_0F61_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F61_P_2) }, + }, + + /* VEX_LEN_0F62_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F62_P_2) }, + }, + + /* VEX_LEN_0F63_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F63_P_2) }, + }, + + /* VEX_LEN_0F64_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F64_P_2) }, + }, + + /* VEX_LEN_0F65_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F65_P_2) }, + }, + + /* VEX_LEN_0F66_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F66_P_2) }, + }, + + /* VEX_LEN_0F67_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F67_P_2) }, + }, + + /* VEX_LEN_0F68_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F68_P_2) }, + }, + + /* VEX_LEN_0F69_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F69_P_2) }, + }, + + /* VEX_LEN_0F6A_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F6A_P_2) }, + }, + + /* VEX_LEN_0F6B_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F6B_P_2) }, + }, + + /* VEX_LEN_0F6C_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F6C_P_2) }, + }, + + /* VEX_LEN_0F6D_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F6D_P_2) }, + }, + + /* VEX_LEN_0F6E_P_2 */ + { + { "vmovK", { XMScalar, Edq } }, + { "vmovK", { XMScalar, Edq } }, + }, + + /* VEX_LEN_0F70_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F70_P_1) }, + }, + + /* VEX_LEN_0F70_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F70_P_2) }, + }, + + /* VEX_LEN_0F70_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F70_P_3) }, + }, + + /* VEX_LEN_0F71_R_2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, + }, + + /* VEX_LEN_0F71_R_4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, + }, + + /* VEX_LEN_0F71_R_6_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, + }, + + /* VEX_LEN_0F72_R_2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, + }, + + /* VEX_LEN_0F72_R_4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, + }, + + /* VEX_LEN_0F72_R_6_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, + }, + + /* VEX_LEN_0F73_R_2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, + }, + + /* VEX_LEN_0F73_R_3_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, + }, + + /* VEX_LEN_0F73_R_6_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, + }, + + /* VEX_LEN_0F73_R_7_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, + }, + + /* VEX_LEN_0F74_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F74_P_2) }, + }, + + /* VEX_LEN_0F75_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F75_P_2) }, + }, + + /* VEX_LEN_0F76_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F76_P_2) }, + }, + + /* VEX_LEN_0F7E_P_1 */ + { + { VEX_W_TABLE (VEX_W_0F7E_P_1) }, + { VEX_W_TABLE (VEX_W_0F7E_P_1) }, + }, + + /* VEX_LEN_0F7E_P_2 */ + { + { "vmovK", { Edq, XMScalar } }, + { "vmovK", { Edq, XMScalar } }, + }, + + /* VEX_LEN_0FAE_R_2_M_0 */ + { + { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, + }, + + /* VEX_LEN_0FAE_R_3_M_0 */ + { + { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, + }, + + /* VEX_LEN_0FC2_P_1 */ + { + { VEX_W_TABLE (VEX_W_0FC2_P_1) }, + { VEX_W_TABLE (VEX_W_0FC2_P_1) }, + }, + + /* VEX_LEN_0FC2_P_3 */ + { + { VEX_W_TABLE (VEX_W_0FC2_P_3) }, + { VEX_W_TABLE (VEX_W_0FC2_P_3) }, + }, + + /* VEX_LEN_0FC4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FC4_P_2) }, + }, + + /* VEX_LEN_0FC5_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FC5_P_2) }, + }, + + /* VEX_LEN_0FD1_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD1_P_2) }, + }, + + /* VEX_LEN_0FD2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD2_P_2) }, + }, + + /* VEX_LEN_0FD3_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD3_P_2) }, + }, + + /* VEX_LEN_0FD4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD4_P_2) }, + }, + + /* VEX_LEN_0FD5_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD5_P_2) }, + }, + + /* VEX_LEN_0FD6_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD6_P_2) }, + { VEX_W_TABLE (VEX_W_0FD6_P_2) }, + }, + + /* VEX_LEN_0FD7_P_2_M_1 */ + { + { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + }, + + /* VEX_LEN_0FD8_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD8_P_2) }, + }, + + /* VEX_LEN_0FD9_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FD9_P_2) }, + }, + + /* VEX_LEN_0FDA_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDA_P_2) }, + }, + + /* VEX_LEN_0FDB_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDB_P_2) }, + }, + + /* VEX_LEN_0FDC_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDC_P_2) }, + }, + + /* VEX_LEN_0FDD_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDD_P_2) }, + }, + + /* VEX_LEN_0FDE_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDE_P_2) }, + }, + + /* VEX_LEN_0FDF_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FDF_P_2) }, + }, + + /* VEX_LEN_0FE0_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE0_P_2) }, + }, + + /* VEX_LEN_0FE1_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE1_P_2) }, + }, + + /* VEX_LEN_0FE2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE2_P_2) }, + }, + + /* VEX_LEN_0FE3_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE3_P_2) }, + }, + + /* VEX_LEN_0FE4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE4_P_2) }, + }, + + /* VEX_LEN_0FE5_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE5_P_2) }, + }, + + /* VEX_LEN_0FE8_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE8_P_2) }, + }, + + /* VEX_LEN_0FE9_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FE9_P_2) }, + }, + + /* VEX_LEN_0FEA_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FEA_P_2) }, + }, + + /* VEX_LEN_0FEB_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FEB_P_2) }, + }, + + /* VEX_LEN_0FEC_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FEC_P_2) }, + }, + + /* VEX_LEN_0FED_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FED_P_2) }, + }, + + /* VEX_LEN_0FEE_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FEE_P_2) }, + }, + + /* VEX_LEN_0FEF_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FEF_P_2) }, + }, + + /* VEX_LEN_0FF1_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF1_P_2) }, + }, + + /* VEX_LEN_0FF2_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF2_P_2) }, + }, + + /* VEX_LEN_0FF3_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF3_P_2) }, + }, + + /* VEX_LEN_0FF4_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF4_P_2) }, + }, + + /* VEX_LEN_0FF5_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF5_P_2) }, + }, + + /* VEX_LEN_0FF6_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF6_P_2) }, + }, + + /* VEX_LEN_0FF7_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF7_P_2) }, + }, + + /* VEX_LEN_0FF8_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF8_P_2) }, + }, + + /* VEX_LEN_0FF9_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FF9_P_2) }, + }, + + /* VEX_LEN_0FFA_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FFA_P_2) }, + }, + + /* VEX_LEN_0FFB_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FFB_P_2) }, + }, + + /* VEX_LEN_0FFC_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FFC_P_2) }, + }, + + /* VEX_LEN_0FFD_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FFD_P_2) }, + }, + + /* VEX_LEN_0FFE_P_2 */ + { + { VEX_W_TABLE (VEX_W_0FFE_P_2) }, + }, + + /* VEX_LEN_0F3800_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3800_P_2) }, + }, + + /* VEX_LEN_0F3801_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3801_P_2) }, + }, + + /* VEX_LEN_0F3802_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3802_P_2) }, + }, + + /* VEX_LEN_0F3803_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3803_P_2) }, + }, + + /* VEX_LEN_0F3804_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3804_P_2) }, + }, + + /* VEX_LEN_0F3805_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3805_P_2) }, + }, + + /* VEX_LEN_0F3806_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3806_P_2) }, + }, + + /* VEX_LEN_0F3807_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3807_P_2) }, + }, + + /* VEX_LEN_0F3808_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3808_P_2) }, + }, + + /* VEX_LEN_0F3809_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3809_P_2) }, + }, + + /* VEX_LEN_0F380A_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F380A_P_2) }, + }, + + /* VEX_LEN_0F380B_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F380B_P_2) }, + }, + + /* VEX_LEN_0F3819_P_2_M_0 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) }, + }, + + /* VEX_LEN_0F381A_P_2_M_0 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, + }, + + /* VEX_LEN_0F381C_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F381C_P_2) }, + }, + + /* VEX_LEN_0F381D_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F381D_P_2) }, + }, + + /* VEX_LEN_0F381E_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F381E_P_2) }, + }, + + /* VEX_LEN_0F3820_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3820_P_2) }, + }, + + /* VEX_LEN_0F3821_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3821_P_2) }, + }, + + /* VEX_LEN_0F3822_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3822_P_2) }, + }, + + /* VEX_LEN_0F3823_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3823_P_2) }, + }, + + /* VEX_LEN_0F3824_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3824_P_2) }, + }, + + /* VEX_LEN_0F3825_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3825_P_2) }, + }, + + /* VEX_LEN_0F3828_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3828_P_2) }, + }, + + /* VEX_LEN_0F3829_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3829_P_2) }, + }, + + /* VEX_LEN_0F382A_P_2_M_0 */ + { + { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + }, + + /* VEX_LEN_0F382B_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F382B_P_2) }, + }, + + /* VEX_LEN_0F3830_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3830_P_2) }, + }, + + /* VEX_LEN_0F3831_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3831_P_2) }, + }, + + /* VEX_LEN_0F3832_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3832_P_2) }, + }, + + /* VEX_LEN_0F3833_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3833_P_2) }, + }, + + /* VEX_LEN_0F3834_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3834_P_2) }, + }, + + /* VEX_LEN_0F3835_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3835_P_2) }, + }, + + /* VEX_LEN_0F3837_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3837_P_2) }, + }, + + /* VEX_LEN_0F3838_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3838_P_2) }, + }, + + /* VEX_LEN_0F3839_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3839_P_2) }, + }, + + /* VEX_LEN_0F383A_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383A_P_2) }, + }, + + /* VEX_LEN_0F383B_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383B_P_2) }, + }, + + /* VEX_LEN_0F383C_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383C_P_2) }, + }, + + /* VEX_LEN_0F383D_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383D_P_2) }, + }, + + /* VEX_LEN_0F383E_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383E_P_2) }, + }, + + /* VEX_LEN_0F383F_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F383F_P_2) }, + }, + + /* VEX_LEN_0F3840_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3840_P_2) }, + }, + + /* VEX_LEN_0F3841_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3841_P_2) }, + }, + + /* VEX_LEN_0F38DB_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, + }, + + /* VEX_LEN_0F38DC_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, + }, + + /* VEX_LEN_0F38DD_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, + }, + + /* VEX_LEN_0F38DE_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, + }, + + /* VEX_LEN_0F38DF_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, + }, + + /* VEX_LEN_0F38F2_P_0 */ + { + { "andnS", { Gdq, VexGdq, Edq } }, + }, + + /* VEX_LEN_0F38F3_R_1_P_0 */ + { + { "blsrS", { VexGdq, Edq } }, + }, + + /* VEX_LEN_0F38F3_R_2_P_0 */ + { + { "blsmskS", { VexGdq, Edq } }, + }, + + /* VEX_LEN_0F38F3_R_3_P_0 */ + { + { "blsiS", { VexGdq, Edq } }, + }, + + /* VEX_LEN_0F38F7_P_0 */ + { + { "bextrS", { Gdq, Edq, VexGdq } }, + }, + + /* VEX_LEN_0F3A06_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, + }, + + /* VEX_LEN_0F3A0A_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, + { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, + }, + + /* VEX_LEN_0F3A0B_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, + { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, + }, + + /* VEX_LEN_0F3A0E_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, + }, + + /* VEX_LEN_0F3A0F_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, + }, + + /* VEX_LEN_0F3A14_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, + }, + + /* VEX_LEN_0F3A15_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, + }, + + /* VEX_LEN_0F3A16_P_2 */ + { + { "vpextrK", { Edq, XM, Ib } }, + }, + + /* VEX_LEN_0F3A17_P_2 */ + { + { "vextractps", { Edqd, XM, Ib } }, + }, + + /* VEX_LEN_0F3A18_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, + }, + + /* VEX_LEN_0F3A19_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, + }, + + /* VEX_LEN_0F3A20_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, + }, + + /* VEX_LEN_0F3A21_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, + }, + + /* VEX_LEN_0F3A22_P_2 */ + { + { "vpinsrK", { XM, Vex128, Edq, Ib } }, + }, + + /* VEX_LEN_0F3A41_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, + }, + + /* VEX_LEN_0F3A42_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, + }, + + /* VEX_LEN_0F3A44_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, + }, + + /* VEX_LEN_0F3A4C_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, + }, + + /* VEX_LEN_0F3A60_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, + }, + + /* VEX_LEN_0F3A61_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, + }, + + /* VEX_LEN_0F3A62_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, + }, + + /* VEX_LEN_0F3A63_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, + }, + + /* VEX_LEN_0F3A6A_P_2 */ + { + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A6B_P_2 */ + { + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A6E_P_2 */ + { + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A6F_P_2 */ + { + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A7A_P_2 */ + { + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A7B_P_2 */ + { + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A7E_P_2 */ + { + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3A7F_P_2 */ + { + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + }, + + /* VEX_LEN_0F3ADF_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, + }, + + /* VEX_LEN_0FXOP_09_80 */ + { + { "vfrczps", { XM, EXxmm } }, + { "vfrczps", { XM, EXymmq } }, + }, + + /* VEX_LEN_0FXOP_09_81 */ + { + { "vfrczpd", { XM, EXxmm } }, + { "vfrczpd", { XM, EXymmq } }, + }, +}; + +static const struct dis386 vex_w_table[][2] = { + { + /* VEX_W_0F10_P_0 */ + { "vmovups", { XM, EXx } }, + }, + { + /* VEX_W_0F10_P_1 */ + { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F10_P_2 */ + { "vmovupd", { XM, EXx } }, + }, + { + /* VEX_W_0F10_P_3 */ + { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F11_P_0 */ + { "vmovups", { EXxS, XM } }, + }, + { + /* VEX_W_0F11_P_1 */ + { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, + }, + { + /* VEX_W_0F11_P_2 */ + { "vmovupd", { EXxS, XM } }, + }, + { + /* VEX_W_0F11_P_3 */ + { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, + }, + { + /* VEX_W_0F12_P_0_M_0 */ + { "vmovlps", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F12_P_0_M_1 */ + { "vmovhlps", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F12_P_1 */ + { "vmovsldup", { XM, EXx } }, + }, + { + /* VEX_W_0F12_P_2 */ + { "vmovlpd", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F12_P_3 */ + { "vmovddup", { XM, EXymmq } }, + }, + { + /* VEX_W_0F13_M_0 */ + { "vmovlpX", { EXq, XM } }, + }, + { + /* VEX_W_0F14 */ + { "vunpcklpX", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F15 */ + { "vunpckhpX", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F16_P_0_M_0 */ + { "vmovhps", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F16_P_0_M_1 */ + { "vmovlhps", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F16_P_1 */ + { "vmovshdup", { XM, EXx } }, + }, + { + /* VEX_W_0F16_P_2 */ + { "vmovhpd", { XM, Vex128, EXq } }, + }, + { + /* VEX_W_0F17_M_0 */ + { "vmovhpX", { EXq, XM } }, + }, + { + /* VEX_W_0F28 */ + { "vmovapX", { XM, EXx } }, + }, + { + /* VEX_W_0F29 */ + { "vmovapX", { EXxS, XM } }, + }, + { + /* VEX_W_0F2B_M_0 */ + { "vmovntpX", { Mx, XM } }, + }, + { + /* VEX_W_0F2E_P_0 */ + { "vucomiss", { XMScalar, EXdScalar } }, + }, + { + /* VEX_W_0F2E_P_2 */ + { "vucomisd", { XMScalar, EXqScalar } }, + }, + { + /* VEX_W_0F2F_P_0 */ + { "vcomiss", { XMScalar, EXdScalar } }, + }, + { + /* VEX_W_0F2F_P_2 */ + { "vcomisd", { XMScalar, EXqScalar } }, + }, + { + /* VEX_W_0F50_M_0 */ + { "vmovmskpX", { Gdq, XS } }, + }, + { + /* VEX_W_0F51_P_0 */ + { "vsqrtps", { XM, EXx } }, + }, + { + /* VEX_W_0F51_P_1 */ + { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F51_P_2 */ + { "vsqrtpd", { XM, EXx } }, + }, + { + /* VEX_W_0F51_P_3 */ + { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F52_P_0 */ + { "vrsqrtps", { XM, EXx } }, + }, + { + /* VEX_W_0F52_P_1 */ + { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F53_P_0 */ + { "vrcpps", { XM, EXx } }, + }, + { + /* VEX_W_0F53_P_1 */ + { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F58_P_0 */ + { "vaddps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F58_P_1 */ + { "vaddss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F58_P_2 */ + { "vaddpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F58_P_3 */ + { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F59_P_0 */ + { "vmulps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F59_P_1 */ + { "vmulss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F59_P_2 */ + { "vmulpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F59_P_3 */ + { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F5A_P_0 */ + { "vcvtps2pd", { XM, EXxmmq } }, + }, + { + /* VEX_W_0F5A_P_1 */ + { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F5A_P_3 */ + { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F5B_P_0 */ + { "vcvtdq2ps", { XM, EXx } }, + }, + { + /* VEX_W_0F5B_P_1 */ + { "vcvttps2dq", { XM, EXx } }, + }, + { + /* VEX_W_0F5B_P_2 */ + { "vcvtps2dq", { XM, EXx } }, + }, + { + /* VEX_W_0F5C_P_0 */ + { "vsubps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5C_P_1 */ + { "vsubss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F5C_P_2 */ + { "vsubpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5C_P_3 */ + { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F5D_P_0 */ + { "vminps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5D_P_1 */ + { "vminss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F5D_P_2 */ + { "vminpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5D_P_3 */ + { "vminsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F5E_P_0 */ + { "vdivps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5E_P_1 */ + { "vdivss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F5E_P_2 */ + { "vdivpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5E_P_3 */ + { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F5F_P_0 */ + { "vmaxps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5F_P_1 */ + { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, + }, + { + /* VEX_W_0F5F_P_2 */ + { "vmaxpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F5F_P_3 */ + { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, + }, + { + /* VEX_W_0F60_P_2 */ + { "vpunpcklbw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F61_P_2 */ + { "vpunpcklwd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F62_P_2 */ + { "vpunpckldq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F63_P_2 */ + { "vpacksswb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F64_P_2 */ + { "vpcmpgtb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F65_P_2 */ + { "vpcmpgtw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F66_P_2 */ + { "vpcmpgtd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F67_P_2 */ + { "vpackuswb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F68_P_2 */ + { "vpunpckhbw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F69_P_2 */ + { "vpunpckhwd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F6A_P_2 */ + { "vpunpckhdq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F6B_P_2 */ + { "vpackssdw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F6C_P_2 */ + { "vpunpcklqdq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F6D_P_2 */ + { "vpunpckhqdq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F6F_P_1 */ + { "vmovdqu", { XM, EXx } }, + }, + { + /* VEX_W_0F6F_P_2 */ + { "vmovdqa", { XM, EXx } }, + }, + { + /* VEX_W_0F70_P_1 */ + { "vpshufhw", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F70_P_2 */ + { "vpshufd", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F70_P_3 */ + { "vpshuflw", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F71_R_2_P_2 */ + { "vpsrlw", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F71_R_4_P_2 */ + { "vpsraw", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F71_R_6_P_2 */ + { "vpsllw", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F72_R_2_P_2 */ + { "vpsrld", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F72_R_4_P_2 */ + { "vpsrad", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F72_R_6_P_2 */ + { "vpslld", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F73_R_2_P_2 */ + { "vpsrlq", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F73_R_3_P_2 */ + { "vpsrldq", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F73_R_6_P_2 */ + { "vpsllq", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F73_R_7_P_2 */ + { "vpslldq", { Vex128, XS, Ib } }, + }, + { + /* VEX_W_0F74_P_2 */ + { "vpcmpeqb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F75_P_2 */ + { "vpcmpeqw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F76_P_2 */ + { "vpcmpeqd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F77_P_0 */ + { "", { VZERO } }, + }, + { + /* VEX_W_0F7C_P_2 */ + { "vhaddpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F7C_P_3 */ + { "vhaddps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F7D_P_2 */ + { "vhsubpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F7D_P_3 */ + { "vhsubps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F7E_P_1 */ + { "vmovq", { XMScalar, EXqScalar } }, + }, + { + /* VEX_W_0F7F_P_1 */ + { "vmovdqu", { EXxS, XM } }, + }, + { + /* VEX_W_0F7F_P_2 */ + { "vmovdqa", { EXxS, XM } }, + }, + { + /* VEX_W_0FAE_R_2_M_0 */ + { "vldmxcsr", { Md } }, + }, + { + /* VEX_W_0FAE_R_3_M_0 */ + { "vstmxcsr", { Md } }, + }, + { + /* VEX_W_0FC2_P_0 */ + { "vcmpps", { XM, Vex, EXx, VCMP } }, + }, + { + /* VEX_W_0FC2_P_1 */ + { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, + }, + { + /* VEX_W_0FC2_P_2 */ + { "vcmppd", { XM, Vex, EXx, VCMP } }, + }, + { + /* VEX_W_0FC2_P_3 */ + { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, + }, + { + /* VEX_W_0FC4_P_2 */ + { "vpinsrw", { XM, Vex128, Edqw, Ib } }, + }, + { + /* VEX_W_0FC5_P_2 */ + { "vpextrw", { Gdq, XS, Ib } }, + }, + { + /* VEX_W_0FD0_P_2 */ + { "vaddsubpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0FD0_P_3 */ + { "vaddsubps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0FD1_P_2 */ + { "vpsrlw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD2_P_2 */ + { "vpsrld", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD3_P_2 */ + { "vpsrlq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD4_P_2 */ + { "vpaddq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD5_P_2 */ + { "vpmullw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD6_P_2 */ + { "vmovq", { EXqScalarS, XMScalar } }, + }, + { + /* VEX_W_0FD7_P_2_M_1 */ + { "vpmovmskb", { Gdq, XS } }, + }, + { + /* VEX_W_0FD8_P_2 */ + { "vpsubusb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FD9_P_2 */ + { "vpsubusw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDA_P_2 */ + { "vpminub", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDB_P_2 */ + { "vpand", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDC_P_2 */ + { "vpaddusb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDD_P_2 */ + { "vpaddusw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDE_P_2 */ + { "vpmaxub", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FDF_P_2 */ + { "vpandn", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE0_P_2 */ + { "vpavgb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE1_P_2 */ + { "vpsraw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE2_P_2 */ + { "vpsrad", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE3_P_2 */ + { "vpavgw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE4_P_2 */ + { "vpmulhuw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE5_P_2 */ + { "vpmulhw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE6_P_1 */ + { "vcvtdq2pd", { XM, EXxmmq } }, + }, + { + /* VEX_W_0FE6_P_2 */ + { "vcvttpd2dq%XY", { XMM, EXx } }, + }, + { + /* VEX_W_0FE6_P_3 */ + { "vcvtpd2dq%XY", { XMM, EXx } }, + }, + { + /* VEX_W_0FE7_P_2_M_0 */ + { "vmovntdq", { Mx, XM } }, + }, + { + /* VEX_W_0FE8_P_2 */ + { "vpsubsb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FE9_P_2 */ + { "vpsubsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FEA_P_2 */ + { "vpminsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FEB_P_2 */ + { "vpor", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FEC_P_2 */ + { "vpaddsb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FED_P_2 */ + { "vpaddsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FEE_P_2 */ + { "vpmaxsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FEF_P_2 */ + { "vpxor", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF0_P_3_M_0 */ + { "vlddqu", { XM, M } }, + }, + { + /* VEX_W_0FF1_P_2 */ + { "vpsllw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF2_P_2 */ + { "vpslld", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF3_P_2 */ + { "vpsllq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF4_P_2 */ + { "vpmuludq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF5_P_2 */ + { "vpmaddwd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF6_P_2 */ + { "vpsadbw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF7_P_2 */ + { "vmaskmovdqu", { XM, XS } }, + }, + { + /* VEX_W_0FF8_P_2 */ + { "vpsubb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FF9_P_2 */ + { "vpsubw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FFA_P_2 */ + { "vpsubd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FFB_P_2 */ + { "vpsubq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FFC_P_2 */ + { "vpaddb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FFD_P_2 */ + { "vpaddw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0FFE_P_2 */ + { "vpaddd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3800_P_2 */ + { "vpshufb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3801_P_2 */ + { "vphaddw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3802_P_2 */ + { "vphaddd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3803_P_2 */ + { "vphaddsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3804_P_2 */ + { "vpmaddubsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3805_P_2 */ + { "vphsubw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3806_P_2 */ + { "vphsubd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3807_P_2 */ + { "vphsubsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3808_P_2 */ + { "vpsignb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3809_P_2 */ + { "vpsignw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F380A_P_2 */ + { "vpsignd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F380B_P_2 */ + { "vpmulhrsw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F380C_P_2 */ + { "vpermilps", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F380D_P_2 */ + { "vpermilpd", { XM, Vex, EXx } }, + }, + { + /* VEX_W_0F380E_P_2 */ + { "vtestps", { XM, EXx } }, + }, + { + /* VEX_W_0F380F_P_2 */ + { "vtestpd", { XM, EXx } }, + }, + { + /* VEX_W_0F3817_P_2 */ + { "vptest", { XM, EXx } }, + }, + { + /* VEX_W_0F3818_P_2_M_0 */ + { "vbroadcastss", { XM, Md } }, + }, + { + /* VEX_W_0F3819_P_2_M_0 */ + { "vbroadcastsd", { XM, Mq } }, + }, + { + /* VEX_W_0F381A_P_2_M_0 */ + { "vbroadcastf128", { XM, Mxmm } }, + }, + { + /* VEX_W_0F381C_P_2 */ + { "vpabsb", { XM, EXx } }, + }, + { + /* VEX_W_0F381D_P_2 */ + { "vpabsw", { XM, EXx } }, + }, + { + /* VEX_W_0F381E_P_2 */ + { "vpabsd", { XM, EXx } }, + }, + { + /* VEX_W_0F3820_P_2 */ + { "vpmovsxbw", { XM, EXq } }, + }, + { + /* VEX_W_0F3821_P_2 */ + { "vpmovsxbd", { XM, EXd } }, + }, + { + /* VEX_W_0F3822_P_2 */ + { "vpmovsxbq", { XM, EXw } }, + }, + { + /* VEX_W_0F3823_P_2 */ + { "vpmovsxwd", { XM, EXq } }, + }, + { + /* VEX_W_0F3824_P_2 */ + { "vpmovsxwq", { XM, EXd } }, + }, + { + /* VEX_W_0F3825_P_2 */ + { "vpmovsxdq", { XM, EXq } }, + }, + { + /* VEX_W_0F3828_P_2 */ + { "vpmuldq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3829_P_2 */ + { "vpcmpeqq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F382A_P_2_M_0 */ + { "vmovntdqa", { XM, Mx } }, + }, + { + /* VEX_W_0F382B_P_2 */ + { "vpackusdw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F382C_P_2_M_0 */ + { "vmaskmovps", { XM, Vex, Mx } }, + }, + { + /* VEX_W_0F382D_P_2_M_0 */ + { "vmaskmovpd", { XM, Vex, Mx } }, + }, + { + /* VEX_W_0F382E_P_2_M_0 */ + { "vmaskmovps", { Mx, Vex, XM } }, + }, + { + /* VEX_W_0F382F_P_2_M_0 */ + { "vmaskmovpd", { Mx, Vex, XM } }, + }, + { + /* VEX_W_0F3830_P_2 */ + { "vpmovzxbw", { XM, EXq } }, + }, + { + /* VEX_W_0F3831_P_2 */ + { "vpmovzxbd", { XM, EXd } }, + }, + { + /* VEX_W_0F3832_P_2 */ + { "vpmovzxbq", { XM, EXw } }, + }, + { + /* VEX_W_0F3833_P_2 */ + { "vpmovzxwd", { XM, EXq } }, + }, + { + /* VEX_W_0F3834_P_2 */ + { "vpmovzxwq", { XM, EXd } }, + }, + { + /* VEX_W_0F3835_P_2 */ + { "vpmovzxdq", { XM, EXq } }, + }, + { + /* VEX_W_0F3837_P_2 */ + { "vpcmpgtq", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3838_P_2 */ + { "vpminsb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3839_P_2 */ + { "vpminsd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383A_P_2 */ + { "vpminuw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383B_P_2 */ + { "vpminud", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383C_P_2 */ + { "vpmaxsb", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383D_P_2 */ + { "vpmaxsd", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383E_P_2 */ + { "vpmaxuw", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F383F_P_2 */ + { "vpmaxud", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3840_P_2 */ + { "vpmulld", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3841_P_2 */ + { "vphminposuw", { XM, EXx } }, + }, + { + /* VEX_W_0F38DB_P_2 */ + { "vaesimc", { XM, EXx } }, + }, + { + /* VEX_W_0F38DC_P_2 */ + { "vaesenc", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F38DD_P_2 */ + { "vaesenclast", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F38DE_P_2 */ + { "vaesdec", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F38DF_P_2 */ + { "vaesdeclast", { XM, Vex128, EXx } }, + }, + { + /* VEX_W_0F3A04_P_2 */ + { "vpermilps", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A05_P_2 */ + { "vpermilpd", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A06_P_2 */ + { "vperm2f128", { XM, Vex256, EXx, Ib } }, + }, + { + /* VEX_W_0F3A08_P_2 */ + { "vroundps", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A09_P_2 */ + { "vroundpd", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A0A_P_2 */ + { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, + }, + { + /* VEX_W_0F3A0B_P_2 */ + { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, + }, + { + /* VEX_W_0F3A0C_P_2 */ + { "vblendps", { XM, Vex, EXx, Ib } }, + }, + { + /* VEX_W_0F3A0D_P_2 */ + { "vblendpd", { XM, Vex, EXx, Ib } }, + }, + { + /* VEX_W_0F3A0E_P_2 */ + { "vpblendw", { XM, Vex128, EXx, Ib } }, + }, + { + /* VEX_W_0F3A0F_P_2 */ + { "vpalignr", { XM, Vex128, EXx, Ib } }, + }, + { + /* VEX_W_0F3A14_P_2 */ + { "vpextrb", { Edqb, XM, Ib } }, + }, + { + /* VEX_W_0F3A15_P_2 */ + { "vpextrw", { Edqw, XM, Ib } }, + }, + { + /* VEX_W_0F3A18_P_2 */ + { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, + }, + { + /* VEX_W_0F3A19_P_2 */ + { "vextractf128", { EXxmm, XM, Ib } }, + }, + { + /* VEX_W_0F3A20_P_2 */ + { "vpinsrb", { XM, Vex128, Edqb, Ib } }, + }, + { + /* VEX_W_0F3A21_P_2 */ + { "vinsertps", { XM, Vex128, EXd, Ib } }, + }, + { + /* VEX_W_0F3A40_P_2 */ + { "vdpps", { XM, Vex, EXx, Ib } }, + }, + { + /* VEX_W_0F3A41_P_2 */ + { "vdppd", { XM, Vex128, EXx, Ib } }, + }, + { + /* VEX_W_0F3A42_P_2 */ + { "vmpsadbw", { XM, Vex128, EXx, Ib } }, + }, + { + /* VEX_W_0F3A44_P_2 */ + { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, + }, + { + /* VEX_W_0F3A48_P_2 */ + { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + }, + { + /* VEX_W_0F3A49_P_2 */ + { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + }, + { + /* VEX_W_0F3A4A_P_2 */ + { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, + }, + { + /* VEX_W_0F3A4B_P_2 */ + { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, + }, + { + /* VEX_W_0F3A4C_P_2 */ + { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, + }, + { + /* VEX_W_0F3A60_P_2 */ + { "vpcmpestrm", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A61_P_2 */ + { "vpcmpestri", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A62_P_2 */ + { "vpcmpistrm", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3A63_P_2 */ + { "vpcmpistri", { XM, EXx, Ib } }, + }, + { + /* VEX_W_0F3ADF_P_2 */ + { "vaeskeygenassist", { XM, EXx, Ib } }, + }, +}; + +static const struct dis386 mod_table[][2] = { + { + /* MOD_8D */ + { "leaS", { Gv, M } }, + }, + { + /* MOD_0F01_REG_0 */ + { X86_64_TABLE (X86_64_0F01_REG_0) }, + { RM_TABLE (RM_0F01_REG_0) }, + }, + { + /* MOD_0F01_REG_1 */ + { X86_64_TABLE (X86_64_0F01_REG_1) }, + { RM_TABLE (RM_0F01_REG_1) }, + }, + { + /* MOD_0F01_REG_2 */ + { X86_64_TABLE (X86_64_0F01_REG_2) }, + { RM_TABLE (RM_0F01_REG_2) }, + }, + { + /* MOD_0F01_REG_3 */ + { X86_64_TABLE (X86_64_0F01_REG_3) }, + { RM_TABLE (RM_0F01_REG_3) }, + }, + { + /* MOD_0F01_REG_7 */ + { "invlpg", { Mb } }, + { RM_TABLE (RM_0F01_REG_7) }, + }, + { + /* MOD_0F12_PREFIX_0 */ + { "movlps", { XM, EXq } }, + { "movhlps", { XM, EXq } }, + }, + { + /* MOD_0F13 */ + { "movlpX", { EXq, XM } }, + }, + { + /* MOD_0F16_PREFIX_0 */ + { "movhps", { XM, EXq } }, + { "movlhps", { XM, EXq } }, + }, + { + /* MOD_0F17 */ + { "movhpX", { EXq, XM } }, + }, + { + /* MOD_0F18_REG_0 */ + { "prefetchnta", { Mb } }, + }, + { + /* MOD_0F18_REG_1 */ + { "prefetcht0", { Mb } }, + }, + { + /* MOD_0F18_REG_2 */ + { "prefetcht1", { Mb } }, + }, + { + /* MOD_0F18_REG_3 */ + { "prefetcht2", { Mb } }, + }, + { + /* MOD_0F20 */ + { Bad_Opcode }, + { "movZ", { Rm, Cm } }, + }, + { + /* MOD_0F21 */ + { Bad_Opcode }, + { "movZ", { Rm, Dm } }, + }, + { + /* MOD_0F22 */ + { Bad_Opcode }, + { "movZ", { Cm, Rm } }, + }, + { + /* MOD_0F23 */ + { Bad_Opcode }, + { "movZ", { Dm, Rm } }, + }, + { + /* MOD_0F24 */ + { Bad_Opcode }, + { "movL", { Rd, Td } }, + }, + { + /* MOD_0F26 */ + { Bad_Opcode }, + { "movL", { Td, Rd } }, + }, + { + /* MOD_0F2B_PREFIX_0 */ + {"movntps", { Mx, XM } }, + }, + { + /* MOD_0F2B_PREFIX_1 */ + {"movntss", { Md, XM } }, + }, + { + /* MOD_0F2B_PREFIX_2 */ + {"movntpd", { Mx, XM } }, + }, + { + /* MOD_0F2B_PREFIX_3 */ + {"movntsd", { Mq, XM } }, + }, + { + /* MOD_0F51 */ + { Bad_Opcode }, + { "movmskpX", { Gdq, XS } }, + }, + { + /* MOD_0F71_REG_2 */ + { Bad_Opcode }, + { "psrlw", { MS, Ib } }, + }, + { + /* MOD_0F71_REG_4 */ + { Bad_Opcode }, + { "psraw", { MS, Ib } }, + }, + { + /* MOD_0F71_REG_6 */ + { Bad_Opcode }, + { "psllw", { MS, Ib } }, + }, + { + /* MOD_0F72_REG_2 */ + { Bad_Opcode }, + { "psrld", { MS, Ib } }, + }, + { + /* MOD_0F72_REG_4 */ + { Bad_Opcode }, + { "psrad", { MS, Ib } }, + }, + { + /* MOD_0F72_REG_6 */ + { Bad_Opcode }, + { "pslld", { MS, Ib } }, + }, + { + /* MOD_0F73_REG_2 */ + { Bad_Opcode }, + { "psrlq", { MS, Ib } }, + }, + { + /* MOD_0F73_REG_3 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F73_REG_3) }, + }, + { + /* MOD_0F73_REG_6 */ + { Bad_Opcode }, + { "psllq", { MS, Ib } }, + }, + { + /* MOD_0F73_REG_7 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F73_REG_7) }, + }, + { + /* MOD_0FAE_REG_0 */ + { "fxsave", { FXSAVE } }, + { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, + }, + { + /* MOD_0FAE_REG_1 */ + { "fxrstor", { FXSAVE } }, + { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, + }, + { + /* MOD_0FAE_REG_2 */ + { "ldmxcsr", { Md } }, + { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, + }, + { + /* MOD_0FAE_REG_3 */ + { "stmxcsr", { Md } }, + { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, + }, + { + /* MOD_0FAE_REG_4 */ + { "xsave", { FXSAVE } }, + }, + { + /* MOD_0FAE_REG_5 */ + { "xrstor", { FXSAVE } }, + { RM_TABLE (RM_0FAE_REG_5) }, + }, + { + /* MOD_0FAE_REG_6 */ + { "xsaveopt", { FXSAVE } }, + { RM_TABLE (RM_0FAE_REG_6) }, + }, + { + /* MOD_0FAE_REG_7 */ + { "clflush", { Mb } }, + { RM_TABLE (RM_0FAE_REG_7) }, + }, + { + /* MOD_0FB2 */ + { "lssS", { Gv, Mp } }, + }, + { + /* MOD_0FB4 */ + { "lfsS", { Gv, Mp } }, + }, + { + /* MOD_0FB5 */ + { "lgsS", { Gv, Mp } }, + }, + { + /* MOD_0FC7_REG_6 */ + { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, + { "rdrand", { Ev } }, + }, + { + /* MOD_0FC7_REG_7 */ + { "vmptrst", { Mq } }, + }, + { + /* MOD_0FD7 */ + { Bad_Opcode }, + { "pmovmskb", { Gdq, MS } }, + }, + { + /* MOD_0FE7_PREFIX_2 */ + { "movntdq", { Mx, XM } }, + }, + { + /* MOD_0FF0_PREFIX_3 */ + { "lddqu", { XM, M } }, + }, + { + /* MOD_0F382A_PREFIX_2 */ + { "movntdqa", { XM, Mx } }, + }, + { + /* MOD_62_32BIT */ + { "bound{S|}", { Gv, Ma } }, + }, + { + /* MOD_C4_32BIT */ + { "lesS", { Gv, Mp } }, + { VEX_C4_TABLE (VEX_0F) }, + }, + { + /* MOD_C5_32BIT */ + { "ldsS", { Gv, Mp } }, + { VEX_C5_TABLE (VEX_0F) }, + }, + { + /* MOD_VEX_0F12_PREFIX_0 */ + { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, + }, + { + /* MOD_VEX_0F13 */ + { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, + }, + { + /* MOD_VEX_0F16_PREFIX_0 */ + { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, + }, + { + /* MOD_VEX_0F17 */ + { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, + }, + { + /* MOD_VEX_0F2B */ + { VEX_W_TABLE (VEX_W_0F2B_M_0) }, + }, + { + /* MOD_VEX_0F50 */ + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F50_M_0) }, + }, + { + /* MOD_VEX_0F71_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, + }, + { + /* MOD_VEX_0F71_REG_4 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, + }, + { + /* MOD_VEX_0F71_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, + }, + { + /* MOD_VEX_0F72_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, + }, + { + /* MOD_VEX_0F72_REG_4 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, + }, + { + /* MOD_VEX_0F72_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, + }, + { + /* MOD_VEX_0F73_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, + }, + { + /* MOD_VEX_0F73_REG_3 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, + }, + { + /* MOD_VEX_0F73_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, + }, + { + /* MOD_VEX_0F73_REG_7 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, + }, + { + /* MOD_VEX_0FAE_REG_2 */ + { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, + }, + { + /* MOD_VEX_0FAE_REG_3 */ + { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, + }, + { + /* MOD_VEX_0FD7_PREFIX_2 */ + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) }, + }, + { + /* MOD_VEX_0FE7_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + }, + { + /* MOD_VEX_0FF0_PREFIX_3 */ + { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + }, + { + /* MOD_VEX_0F3818_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) }, + }, + { + /* MOD_VEX_0F3819_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) }, + }, + { + /* MOD_VEX_0F381A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382C_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382D_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382E_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382F_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, + }, +}; + +static const struct dis386 rm_table[][8] = { + { + /* RM_0F01_REG_0 */ + { Bad_Opcode }, + { "vmcall", { Skip_MODRM } }, + { "vmlaunch", { Skip_MODRM } }, + { "vmresume", { Skip_MODRM } }, + { "vmxoff", { Skip_MODRM } }, + }, + { + /* RM_0F01_REG_1 */ + { "monitor", { { OP_Monitor, 0 } } }, + { "mwait", { { OP_Mwait, 0 } } }, + }, + { + /* RM_0F01_REG_2 */ + { "xgetbv", { Skip_MODRM } }, + { "xsetbv", { Skip_MODRM } }, + }, + { + /* RM_0F01_REG_3 */ + { "vmrun", { Skip_MODRM } }, + { "vmmcall", { Skip_MODRM } }, + { "vmload", { Skip_MODRM } }, + { "vmsave", { Skip_MODRM } }, + { "stgi", { Skip_MODRM } }, + { "clgi", { Skip_MODRM } }, + { "skinit", { Skip_MODRM } }, + { "invlpga", { Skip_MODRM } }, + }, + { + /* RM_0F01_REG_7 */ + { "swapgs", { Skip_MODRM } }, + { "rdtscp", { Skip_MODRM } }, + }, + { + /* RM_0FAE_REG_5 */ + { "lfence", { Skip_MODRM } }, + }, + { + /* RM_0FAE_REG_6 */ + { "mfence", { Skip_MODRM } }, + }, + { + /* RM_0FAE_REG_7 */ + { "sfence", { Skip_MODRM } }, + }, +}; + +#define INTERNAL_DISASSEMBLER_ERROR _("") + +/* We use the high bit to indicate different name for the same + prefix. */ +#define ADDR16_PREFIX (0x67 | 0x100) +#define ADDR32_PREFIX (0x67 | 0x200) +#define DATA16_PREFIX (0x66 | 0x100) +#define DATA32_PREFIX (0x66 | 0x200) +#define REP_PREFIX (0xf3 | 0x100) + +static int +ckprefix (void) +{ + int newrex, i, length; + rex = 0; + rex_ignored = 0; + prefixes = 0; + used_prefixes = 0; + rex_used = 0; + last_lock_prefix = -1; + last_repz_prefix = -1; + last_repnz_prefix = -1; + last_data_prefix = -1; + last_addr_prefix = -1; + last_rex_prefix = -1; + last_seg_prefix = -1; + for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) + all_prefixes[i] = 0; + i = 0; + length = 0; + /* The maximum instruction length is 15bytes. */ + while (length < MAX_CODE_LENGTH - 1) + { + FETCH_DATA (the_info, codep + 1); + newrex = 0; + switch (*codep) + { + /* REX prefixes family. */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + if (address_mode == mode_64bit) + newrex = *codep; + else + return 1; + last_rex_prefix = i; + break; + case 0xf3: + prefixes |= PREFIX_REPZ; + last_repz_prefix = i; + break; + case 0xf2: + prefixes |= PREFIX_REPNZ; + last_repnz_prefix = i; + break; + case 0xf0: + prefixes |= PREFIX_LOCK; + last_lock_prefix = i; + break; + case 0x2e: + prefixes |= PREFIX_CS; + last_seg_prefix = i; + break; + case 0x36: + prefixes |= PREFIX_SS; + last_seg_prefix = i; + break; + case 0x3e: + prefixes |= PREFIX_DS; + last_seg_prefix = i; + break; + case 0x26: + prefixes |= PREFIX_ES; + last_seg_prefix = i; + break; + case 0x64: + prefixes |= PREFIX_FS; + last_seg_prefix = i; + break; + case 0x65: + prefixes |= PREFIX_GS; + last_seg_prefix = i; + break; + case 0x66: + prefixes |= PREFIX_DATA; + last_data_prefix = i; + break; + case 0x67: + prefixes |= PREFIX_ADDR; + last_addr_prefix = i; + break; + case FWAIT_OPCODE: + /* fwait is really an instruction. If there are prefixes + before the fwait, they belong to the fwait, *not* to the + following instruction. */ + if (prefixes || rex) + { + prefixes |= PREFIX_FWAIT; + codep++; + return 1; + } + prefixes = PREFIX_FWAIT; + break; + default: + return 1; + } + /* Rex is ignored when followed by another prefix. */ + if (rex) + { + rex_used = rex; + return 1; + } + if (*codep != FWAIT_OPCODE) + all_prefixes[i++] = *codep; + rex = newrex; + codep++; + length++; + } + return 0; +} + +static int +seg_prefix (int pref) +{ + switch (pref) + { + case 0x2e: + return PREFIX_CS; + case 0x36: + return PREFIX_SS; + case 0x3e: + return PREFIX_DS; + case 0x26: + return PREFIX_ES; + case 0x64: + return PREFIX_FS; + case 0x65: + return PREFIX_GS; + default: + return 0; + } +} + +/* Return the name of the prefix byte PREF, or NULL if PREF is not a + prefix byte. */ + +static const char * +prefix_name (int pref, int sizeflag) +{ + static const char *rexes [16] = + { + "rex", /* 0x40 */ + "rex.B", /* 0x41 */ + "rex.X", /* 0x42 */ + "rex.XB", /* 0x43 */ + "rex.R", /* 0x44 */ + "rex.RB", /* 0x45 */ + "rex.RX", /* 0x46 */ + "rex.RXB", /* 0x47 */ + "rex.W", /* 0x48 */ + "rex.WB", /* 0x49 */ + "rex.WX", /* 0x4a */ + "rex.WXB", /* 0x4b */ + "rex.WR", /* 0x4c */ + "rex.WRB", /* 0x4d */ + "rex.WRX", /* 0x4e */ + "rex.WRXB", /* 0x4f */ + }; + + switch (pref) + { + /* REX prefixes family. */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + return rexes [pref - 0x40]; + case 0xf3: + return "repz"; + case 0xf2: + return "repnz"; + case 0xf0: + return "lock"; + case 0x2e: + return "cs"; + case 0x36: + return "ss"; + case 0x3e: + return "ds"; + case 0x26: + return "es"; + case 0x64: + return "fs"; + case 0x65: + return "gs"; + case 0x66: + return (sizeflag & DFLAG) ? "data16" : "data32"; + case 0x67: + if (address_mode == mode_64bit) + return (sizeflag & AFLAG) ? "addr32" : "addr64"; + else + return (sizeflag & AFLAG) ? "addr16" : "addr32"; + case FWAIT_OPCODE: + return "fwait"; + case ADDR16_PREFIX: + return "addr16"; + case ADDR32_PREFIX: + return "addr32"; + case DATA16_PREFIX: + return "data16"; + case DATA32_PREFIX: + return "data32"; + case REP_PREFIX: + return "rep"; + default: + return NULL; + } +} + +static char op_out[MAX_OPERANDS][100]; +static int op_ad, op_index[MAX_OPERANDS]; +static int two_source_ops; +static bfd_vma op_address[MAX_OPERANDS]; +static bfd_vma op_riprel[MAX_OPERANDS]; +static bfd_vma start_pc; + +/* + * On the 386's of 1988, the maximum length of an instruction is 15 bytes. + * (see topic "Redundant prefixes" in the "Differences from 8086" + * section of the "Virtual 8086 Mode" chapter.) + * 'pc' should be the address of this instruction, it will + * be used to print the target address if this is a relative jump or call + * The function returns the length of this instruction in bytes. + */ + +static char intel_syntax; +static char intel_mnemonic = !SYSV386_COMPAT; +static char open_char; +static char close_char; +static char separator_char; +static char scale_char; + +/* Here for backwards compatibility. When gdb stops using + print_insn_i386_att and print_insn_i386_intel these functions can + disappear, and print_insn_i386 be merged into print_insn. */ +int +print_insn_i386_att (bfd_vma pc, disassemble_info *info) +{ + intel_syntax = 0; + + return print_insn (pc, info); +} + +int +print_insn_i386_intel (bfd_vma pc, disassemble_info *info) +{ + intel_syntax = 1; + + return print_insn (pc, info); +} + +int +print_insn_i386 (bfd_vma pc, disassemble_info *info) +{ + intel_syntax = -1; + + return print_insn (pc, info); +} + +void +print_i386_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following i386/x86-64 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); + fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); + fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); + fprintf (stream, _(" att Display instruction in AT&T syntax\n")); + fprintf (stream, _(" intel Display instruction in Intel syntax\n")); + fprintf (stream, _(" att-mnemonic\n" + " Display instruction in AT&T mnemonic\n")); + fprintf (stream, _(" intel-mnemonic\n" + " Display instruction in Intel mnemonic\n")); + fprintf (stream, _(" addr64 Assume 64bit address size\n")); + fprintf (stream, _(" addr32 Assume 32bit address size\n")); + fprintf (stream, _(" addr16 Assume 16bit address size\n")); + fprintf (stream, _(" data32 Assume 32bit data size\n")); + fprintf (stream, _(" data16 Assume 16bit data size\n")); + fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); +} + +/* Bad opcode. */ +static const struct dis386 bad_opcode = { "(bad)", { XX } }; + +/* Get a pointer to struct dis386 with a valid name. */ + +static const struct dis386 * +get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) +{ + int vindex, vex_table_index; + + if (dp->name != NULL) + return dp; + + switch (dp->op[0].bytemode) + { + case USE_REG_TABLE: + dp = ®_table[dp->op[1].bytemode][modrm.reg]; + break; + + case USE_MOD_TABLE: + vindex = modrm.mod == 0x3 ? 1 : 0; + dp = &mod_table[dp->op[1].bytemode][vindex]; + break; + + case USE_RM_TABLE: + dp = &rm_table[dp->op[1].bytemode][modrm.rm]; + break; + + case USE_PREFIX_TABLE: + if (need_vex) + { + /* The prefix in VEX is implicit. */ + switch (vex.prefix) + { + case 0: + vindex = 0; + break; + case REPE_PREFIX_OPCODE: + vindex = 1; + break; + case DATA_PREFIX_OPCODE: + vindex = 2; + break; + case REPNE_PREFIX_OPCODE: + vindex = 3; + break; + default: + abort (); + break; + } + } + else + { + vindex = 0; + used_prefixes |= (prefixes & PREFIX_REPZ); + if (prefixes & PREFIX_REPZ) + { + vindex = 1; + all_prefixes[last_repz_prefix] = 0; + } + else + { + /* We should check PREFIX_REPNZ and PREFIX_REPZ before + PREFIX_DATA. */ + used_prefixes |= (prefixes & PREFIX_REPNZ); + if (prefixes & PREFIX_REPNZ) + { + vindex = 3; + all_prefixes[last_repnz_prefix] = 0; + } + else + { + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + { + vindex = 2; + all_prefixes[last_data_prefix] = 0; + } + } + } + } + dp = &prefix_table[dp->op[1].bytemode][vindex]; + break; + + case USE_X86_64_TABLE: + vindex = address_mode == mode_64bit ? 1 : 0; + dp = &x86_64_table[dp->op[1].bytemode][vindex]; + break; + + case USE_3BYTE_TABLE: + FETCH_DATA (info, codep + 2); + vindex = *codep++; + dp = &three_byte_table[dp->op[1].bytemode][vindex]; + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + break; + + case USE_VEX_LEN_TABLE: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + vindex = 0; + break; + case 256: + vindex = 1; + break; + default: + abort (); + break; + } + + dp = &vex_len_table[dp->op[1].bytemode][vindex]; + break; + + case USE_XOP_8F_TABLE: + FETCH_DATA (info, codep + 3); + /* All bits in the REX prefix are ignored. */ + rex_ignored = rex; + rex = ~(*codep >> 5) & 0x7; + + /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ + switch ((*codep & 0x1f)) + { + default: + dp = &bad_opcode; + return dp; + case 0x8: + vex_table_index = XOP_08; + break; + case 0x9: + vex_table_index = XOP_09; + break; + case 0xa: + vex_table_index = XOP_0A; + break; + } + codep++; + vex.w = *codep & 0x80; + if (vex.w && address_mode == mode_64bit) + rex |= REX_W; + + vex.register_specifier = (~(*codep >> 3)) & 0xf; + if (address_mode != mode_64bit + && vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } + + vex.length = (*codep & 0x4) ? 256 : 128; + switch ((*codep & 0x3)) + { + case 0: + vex.prefix = 0; + break; + case 1: + vex.prefix = DATA_PREFIX_OPCODE; + break; + case 2: + vex.prefix = REPE_PREFIX_OPCODE; + break; + case 3: + vex.prefix = REPNE_PREFIX_OPCODE; + break; + } + need_vex = 1; + need_vex_reg = 1; + codep++; + vindex = *codep++; + dp = &xop_table[vex_table_index][vindex]; + + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + break; + + case USE_VEX_C4_TABLE: + FETCH_DATA (info, codep + 3); + /* All bits in the REX prefix are ignored. */ + rex_ignored = rex; + rex = ~(*codep >> 5) & 0x7; + switch ((*codep & 0x1f)) + { + default: + dp = &bad_opcode; + return dp; + case 0x1: + vex_table_index = VEX_0F; + break; + case 0x2: + vex_table_index = VEX_0F38; + break; + case 0x3: + vex_table_index = VEX_0F3A; + break; + } + codep++; + vex.w = *codep & 0x80; + if (vex.w && address_mode == mode_64bit) + rex |= REX_W; + + vex.register_specifier = (~(*codep >> 3)) & 0xf; + if (address_mode != mode_64bit + && vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } + + vex.length = (*codep & 0x4) ? 256 : 128; + switch ((*codep & 0x3)) + { + case 0: + vex.prefix = 0; + break; + case 1: + vex.prefix = DATA_PREFIX_OPCODE; + break; + case 2: + vex.prefix = REPE_PREFIX_OPCODE; + break; + case 3: + vex.prefix = REPNE_PREFIX_OPCODE; + break; + } + need_vex = 1; + need_vex_reg = 1; + codep++; + vindex = *codep++; + dp = &vex_table[vex_table_index][vindex]; + /* There is no MODRM byte for VEX [82|77]. */ + if (vindex != 0x77 && vindex != 0x82) + { + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + } + break; + + case USE_VEX_C5_TABLE: + FETCH_DATA (info, codep + 2); + /* All bits in the REX prefix are ignored. */ + rex_ignored = rex; + rex = (*codep & 0x80) ? 0 : REX_R; + + vex.register_specifier = (~(*codep >> 3)) & 0xf; + if (address_mode != mode_64bit + && vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } + + vex.w = 0; + + vex.length = (*codep & 0x4) ? 256 : 128; + switch ((*codep & 0x3)) + { + case 0: + vex.prefix = 0; + break; + case 1: + vex.prefix = DATA_PREFIX_OPCODE; + break; + case 2: + vex.prefix = REPE_PREFIX_OPCODE; + break; + case 3: + vex.prefix = REPNE_PREFIX_OPCODE; + break; + } + need_vex = 1; + need_vex_reg = 1; + codep++; + vindex = *codep++; + dp = &vex_table[dp->op[1].bytemode][vindex]; + /* There is no MODRM byte for VEX [82|77]. */ + if (vindex != 0x77 && vindex != 0x82) + { + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + } + break; + + case USE_VEX_W_TABLE: + if (!need_vex) + abort (); + + dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; + break; + + case 0: + dp = &bad_opcode; + break; + + default: + abort (); + } + + if (dp->name != NULL) + return dp; + else + return get_valid_dis386 (dp, info); +} + +static void +get_sib (disassemble_info *info) +{ + /* If modrm.mod == 3, operand must be register. */ + if (need_modrm + && address_mode != mode_16bit + && modrm.mod != 3 + && modrm.rm == 4) + { + FETCH_DATA (info, codep + 2); + sib.index = (codep [1] >> 3) & 7; + sib.scale = (codep [1] >> 6) & 3; + sib.base = codep [1] & 7; + } +} + +static int +print_insn (bfd_vma pc, disassemble_info *info) +{ + const struct dis386 *dp; + int i; + char *op_txt[MAX_OPERANDS]; + int needcomma; + int sizeflag; + const char *p; + struct dis_private priv; + int prefix_length; + int default_prefixes; + + if (info->mach == bfd_mach_x86_64_intel_syntax + || info->mach == bfd_mach_x86_64 + || info->mach == bfd_mach_x64_32_intel_syntax + || info->mach == bfd_mach_x64_32 + || info->mach == bfd_mach_l1om + || info->mach == bfd_mach_l1om_intel_syntax) + address_mode = mode_64bit; + else + address_mode = mode_32bit; + + if (intel_syntax == (char) -1) + intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax + || info->mach == bfd_mach_x86_64_intel_syntax + || info->mach == bfd_mach_x64_32_intel_syntax + || info->mach == bfd_mach_l1om_intel_syntax); + + if (info->mach == bfd_mach_i386_i386 + || info->mach == bfd_mach_x86_64 + || info->mach == bfd_mach_x64_32 + || info->mach == bfd_mach_l1om + || info->mach == bfd_mach_i386_i386_intel_syntax + || info->mach == bfd_mach_x86_64_intel_syntax + || info->mach == bfd_mach_x64_32_intel_syntax + || info->mach == bfd_mach_l1om_intel_syntax) + priv.orig_sizeflag = AFLAG | DFLAG; + else if (info->mach == bfd_mach_i386_i8086) + priv.orig_sizeflag = 0; + else + abort (); + + for (p = info->disassembler_options; p != NULL; ) + { + if (CONST_STRNEQ (p, "x86-64")) + { + address_mode = mode_64bit; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (CONST_STRNEQ (p, "i386")) + { + address_mode = mode_32bit; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (CONST_STRNEQ (p, "i8086")) + { + address_mode = mode_16bit; + priv.orig_sizeflag = 0; + } + else if (CONST_STRNEQ (p, "intel")) + { + intel_syntax = 1; + if (CONST_STRNEQ (p + 5, "-mnemonic")) + intel_mnemonic = 1; + } + else if (CONST_STRNEQ (p, "att")) + { + intel_syntax = 0; + if (CONST_STRNEQ (p + 3, "-mnemonic")) + intel_mnemonic = 0; + } + else if (CONST_STRNEQ (p, "addr")) + { + if (address_mode == mode_64bit) + { + if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '6' && p[5] == '4') + priv.orig_sizeflag |= AFLAG; + } + else + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= AFLAG; + } + } + else if (CONST_STRNEQ (p, "data")) + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~DFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= DFLAG; + } + else if (CONST_STRNEQ (p, "suffix")) + priv.orig_sizeflag |= SUFFIX_ALWAYS; + + p = strchr (p, ','); + if (p != NULL) + p++; + } + + if (intel_syntax) + { + names64 = intel_names64; + names32 = intel_names32; + names16 = intel_names16; + names8 = intel_names8; + names8rex = intel_names8rex; + names_seg = intel_names_seg; + names_mm = intel_names_mm; + names_xmm = intel_names_xmm; + names_ymm = intel_names_ymm; + index64 = intel_index64; + index32 = intel_index32; + index16 = intel_index16; + open_char = '['; + close_char = ']'; + separator_char = '+'; + scale_char = '*'; + } + else + { + names64 = att_names64; + names32 = att_names32; + names16 = att_names16; + names8 = att_names8; + names8rex = att_names8rex; + names_seg = att_names_seg; + names_mm = att_names_mm; + names_xmm = att_names_xmm; + names_ymm = att_names_ymm; + index64 = att_index64; + index32 = att_index32; + index16 = att_index16; + open_char = '('; + close_char = ')'; + separator_char = ','; + scale_char = ','; + } + + /* The output looks better if we put 7 bytes on a line, since that + puts most long word instructions on a single line. Use 8 bytes + for Intel L1OM. */ + if (info->mach == bfd_mach_l1om + || info->mach == bfd_mach_l1om_intel_syntax) + info->bytes_per_line = 8; + else + info->bytes_per_line = 7; + + info->private_data = &priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = pc; + + obuf[0] = 0; + for (i = 0; i < MAX_OPERANDS; ++i) + { + op_out[i][0] = 0; + op_index[i] = -1; + } + + the_info = info; + start_pc = pc; + start_codep = priv.the_buffer; + codep = priv.the_buffer; + + if (setjmp (priv.bailout) != 0) + { + const char *name; + + /* Getting here means we tried for data but didn't get it. That + means we have an incomplete instruction of some sort. Just + print the first byte as a prefix or a .byte pseudo-op. */ + if (codep > priv.the_buffer) + { + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); + if (name != NULL) + (*info->fprintf_func) (info->stream, "%s", name); + else + { + /* Just print the first byte as a .byte instruction. */ + (*info->fprintf_func) (info->stream, ".byte 0x%x", + (unsigned int) priv.the_buffer[0]); + } + + return 1; + } + + return -1; + } + + obufp = obuf; + sizeflag = priv.orig_sizeflag; + + if (!ckprefix () || rex_used) + { + /* Too many prefixes or unused REX prefixes. */ + for (i = 0; + all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes); + i++) + (*info->fprintf_func) (info->stream, "%s", + prefix_name (all_prefixes[i], sizeflag)); + return 1; + } + + insn_codep = codep; + + FETCH_DATA (info, codep + 1); + two_source_ops = (*codep == 0x62) || (*codep == 0xc8); + + if (((prefixes & PREFIX_FWAIT) + && ((*codep < 0xd8) || (*codep > 0xdf)))) + { + (*info->fprintf_func) (info->stream, "fwait"); + return 1; + } + + if (*codep == 0x0f) + { + unsigned char threebyte; + FETCH_DATA (info, codep + 2); + threebyte = *++codep; + dp = &dis386_twobyte[threebyte]; + need_modrm = twobyte_has_modrm[*codep]; + codep++; + } + else + { + dp = &dis386[*codep]; + need_modrm = onebyte_has_modrm[*codep]; + codep++; + } + + if ((prefixes & PREFIX_REPZ)) + used_prefixes |= PREFIX_REPZ; + if ((prefixes & PREFIX_REPNZ)) + used_prefixes |= PREFIX_REPNZ; + if ((prefixes & PREFIX_LOCK)) + used_prefixes |= PREFIX_LOCK; + + default_prefixes = 0; + if (prefixes & PREFIX_ADDR) + { + sizeflag ^= AFLAG; + if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) + { + if ((sizeflag & AFLAG) || address_mode == mode_64bit) + all_prefixes[last_addr_prefix] = ADDR32_PREFIX; + else + all_prefixes[last_addr_prefix] = ADDR16_PREFIX; + default_prefixes |= PREFIX_ADDR; + } + } + + if ((prefixes & PREFIX_DATA)) + { + sizeflag ^= DFLAG; + if (dp->op[2].bytemode == cond_jump_mode + && dp->op[0].bytemode == v_mode + && !intel_syntax) + { + if (sizeflag & DFLAG) + all_prefixes[last_data_prefix] = DATA32_PREFIX; + else + all_prefixes[last_data_prefix] = DATA16_PREFIX; + default_prefixes |= PREFIX_DATA; + } + else if (rex & REX_W) + { + /* REX_W will override PREFIX_DATA. */ + default_prefixes |= PREFIX_DATA; + } + } + + if (need_modrm) + { + FETCH_DATA (info, codep + 1); + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; + } + + need_vex = 0; + need_vex_reg = 0; + vex_w_done = 0; + + if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) + { + get_sib (info); + dofloat (sizeflag); + } + else + { + dp = get_valid_dis386 (dp, info); + if (dp != NULL && putop (dp->name, sizeflag) == 0) + { + get_sib (info); + for (i = 0; i < MAX_OPERANDS; ++i) + { + obufp = op_out[i]; + op_ad = MAX_OPERANDS - 1 - i; + if (dp->op[i].rtn) + (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); + } + } + } + + /* See if any prefixes were not used. If so, print the first one + separately. If we don't do this, we'll wind up printing an + instruction stream which does not precisely correspond to the + bytes we are disassembling. */ + if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) + { + for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) + if (all_prefixes[i]) + { + const char *name; + name = prefix_name (all_prefixes[i], priv.orig_sizeflag); + if (name == NULL) + name = INTERNAL_DISASSEMBLER_ERROR; + (*info->fprintf_func) (info->stream, "%s", name); + return 1; + } + } + + /* Check if the REX prefix is used. */ + if (rex_ignored == 0 && (rex ^ rex_used) == 0) + all_prefixes[last_rex_prefix] = 0; + + /* Check if the SEG prefix is used. */ + if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES + | PREFIX_FS | PREFIX_GS)) != 0 + && (used_prefixes + & seg_prefix (all_prefixes[last_seg_prefix])) != 0) + all_prefixes[last_seg_prefix] = 0; + + /* Check if the ADDR prefix is used. */ + if ((prefixes & PREFIX_ADDR) != 0 + && (used_prefixes & PREFIX_ADDR) != 0) + all_prefixes[last_addr_prefix] = 0; + + /* Check if the DATA prefix is used. */ + if ((prefixes & PREFIX_DATA) != 0 + && (used_prefixes & PREFIX_DATA) != 0) + all_prefixes[last_data_prefix] = 0; + + prefix_length = 0; + for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) + if (all_prefixes[i]) + { + const char *name; + name = prefix_name (all_prefixes[i], sizeflag); + if (name == NULL) + abort (); + prefix_length += strlen (name) + 1; + (*info->fprintf_func) (info->stream, "%s ", name); + } + + /* Check maximum code length. */ + if ((codep - start_codep) > MAX_CODE_LENGTH) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return MAX_CODE_LENGTH; + } + + obufp = mnemonicendp; + for (i = strlen (obuf) + prefix_length; i < 6; i++) + oappend (" "); + oappend (" "); + (*info->fprintf_func) (info->stream, "%s", obuf); + + /* The enter and bound instructions are printed with operands in the same + order as the intel book; everything else is printed in reverse order. */ + if (intel_syntax || two_source_ops) + { + bfd_vma riprel; + + for (i = 0; i < MAX_OPERANDS; ++i) + op_txt[i] = op_out[i]; + + for (i = 0; i < (MAX_OPERANDS >> 1); ++i) + { + op_ad = op_index[i]; + op_index[i] = op_index[MAX_OPERANDS - 1 - i]; + op_index[MAX_OPERANDS - 1 - i] = op_ad; + riprel = op_riprel[i]; + op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; + op_riprel[MAX_OPERANDS - 1 - i] = riprel; + } + } + else + { + for (i = 0; i < MAX_OPERANDS; ++i) + op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; + } + + needcomma = 0; + for (i = 0; i < MAX_OPERANDS; ++i) + if (*op_txt[i]) + { + if (needcomma) + (*info->fprintf_func) (info->stream, ","); + if (op_index[i] != -1 && !op_riprel[i]) + (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); + else + (*info->fprintf_func) (info->stream, "%s", op_txt[i]); + needcomma = 1; + } + + for (i = 0; i < MAX_OPERANDS; i++) + if (op_index[i] != -1 && op_riprel[i]) + { + (*info->fprintf_func) (info->stream, " # "); + (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep + + op_address[op_index[i]]), info); + break; + } + return codep - priv.the_buffer; +} + +static const char *float_mem[] = { + /* d8 */ + "fadd{s|}", + "fmul{s|}", + "fcom{s|}", + "fcomp{s|}", + "fsub{s|}", + "fsubr{s|}", + "fdiv{s|}", + "fdivr{s|}", + /* d9 */ + "fld{s|}", + "(bad)", + "fst{s|}", + "fstp{s|}", + "fldenvIC", + "fldcw", + "fNstenvIC", + "fNstcw", + /* da */ + "fiadd{l|}", + "fimul{l|}", + "ficom{l|}", + "ficomp{l|}", + "fisub{l|}", + "fisubr{l|}", + "fidiv{l|}", + "fidivr{l|}", + /* db */ + "fild{l|}", + "fisttp{l|}", + "fist{l|}", + "fistp{l|}", + "(bad)", + "fld{t||t|}", + "(bad)", + "fstp{t||t|}", + /* dc */ + "fadd{l|}", + "fmul{l|}", + "fcom{l|}", + "fcomp{l|}", + "fsub{l|}", + "fsubr{l|}", + "fdiv{l|}", + "fdivr{l|}", + /* dd */ + "fld{l|}", + "fisttp{ll|}", + "fst{l||}", + "fstp{l|}", + "frstorIC", + "(bad)", + "fNsaveIC", + "fNstsw", + /* de */ + "fiadd", + "fimul", + "ficom", + "ficomp", + "fisub", + "fisubr", + "fidiv", + "fidivr", + /* df */ + "fild", + "fisttp", + "fist", + "fistp", + "fbld", + "fild{ll|}", + "fbstp", + "fistp{ll|}", +}; + +static const unsigned char float_mem_mode[] = { + /* d8 */ + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + /* d9 */ + d_mode, + 0, + d_mode, + d_mode, + 0, + w_mode, + 0, + w_mode, + /* da */ + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + d_mode, + /* db */ + d_mode, + d_mode, + d_mode, + d_mode, + 0, + t_mode, + 0, + t_mode, + /* dc */ + q_mode, + q_mode, + q_mode, + q_mode, + q_mode, + q_mode, + q_mode, + q_mode, + /* dd */ + q_mode, + q_mode, + q_mode, + q_mode, + 0, + 0, + 0, + w_mode, + /* de */ + w_mode, + w_mode, + w_mode, + w_mode, + w_mode, + w_mode, + w_mode, + w_mode, + /* df */ + w_mode, + w_mode, + w_mode, + w_mode, + t_mode, + q_mode, + t_mode, + q_mode +}; + +#define ST { OP_ST, 0 } +#define STi { OP_STi, 0 } + +#define FGRPd9_2 NULL, { { NULL, 0 } } +#define FGRPd9_4 NULL, { { NULL, 1 } } +#define FGRPd9_5 NULL, { { NULL, 2 } } +#define FGRPd9_6 NULL, { { NULL, 3 } } +#define FGRPd9_7 NULL, { { NULL, 4 } } +#define FGRPda_5 NULL, { { NULL, 5 } } +#define FGRPdb_4 NULL, { { NULL, 6 } } +#define FGRPde_3 NULL, { { NULL, 7 } } +#define FGRPdf_4 NULL, { { NULL, 8 } } + +static const struct dis386 float_reg[][8] = { + /* d8 */ + { + { "fadd", { ST, STi } }, + { "fmul", { ST, STi } }, + { "fcom", { STi } }, + { "fcomp", { STi } }, + { "fsub", { ST, STi } }, + { "fsubr", { ST, STi } }, + { "fdiv", { ST, STi } }, + { "fdivr", { ST, STi } }, + }, + /* d9 */ + { + { "fld", { STi } }, + { "fxch", { STi } }, + { FGRPd9_2 }, + { Bad_Opcode }, + { FGRPd9_4 }, + { FGRPd9_5 }, + { FGRPd9_6 }, + { FGRPd9_7 }, + }, + /* da */ + { + { "fcmovb", { ST, STi } }, + { "fcmove", { ST, STi } }, + { "fcmovbe",{ ST, STi } }, + { "fcmovu", { ST, STi } }, + { Bad_Opcode }, + { FGRPda_5 }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* db */ + { + { "fcmovnb",{ ST, STi } }, + { "fcmovne",{ ST, STi } }, + { "fcmovnbe",{ ST, STi } }, + { "fcmovnu",{ ST, STi } }, + { FGRPdb_4 }, + { "fucomi", { ST, STi } }, + { "fcomi", { ST, STi } }, + { Bad_Opcode }, + }, + /* dc */ + { + { "fadd", { STi, ST } }, + { "fmul", { STi, ST } }, + { Bad_Opcode }, + { Bad_Opcode }, + { "fsub!M", { STi, ST } }, + { "fsubM", { STi, ST } }, + { "fdiv!M", { STi, ST } }, + { "fdivM", { STi, ST } }, + }, + /* dd */ + { + { "ffree", { STi } }, + { Bad_Opcode }, + { "fst", { STi } }, + { "fstp", { STi } }, + { "fucom", { STi } }, + { "fucomp", { STi } }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* de */ + { + { "faddp", { STi, ST } }, + { "fmulp", { STi, ST } }, + { Bad_Opcode }, + { FGRPde_3 }, + { "fsub!Mp", { STi, ST } }, + { "fsubMp", { STi, ST } }, + { "fdiv!Mp", { STi, ST } }, + { "fdivMp", { STi, ST } }, + }, + /* df */ + { + { "ffreep", { STi } }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { FGRPdf_4 }, + { "fucomip", { ST, STi } }, + { "fcomip", { ST, STi } }, + { Bad_Opcode }, + }, +}; + +static char *fgrps[][8] = { + /* d9_2 0 */ + { + "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_4 1 */ + { + "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", + }, + + /* d9_5 2 */ + { + "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", + }, + + /* d9_6 3 */ + { + "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", + }, + + /* d9_7 4 */ + { + "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", + }, + + /* da_5 5 */ + { + "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* db_4 6 */ + { + "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", + "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", + }, + + /* de_3 7 */ + { + "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* df_4 8 */ + { + "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, +}; + +static void +swap_operand (void) +{ + mnemonicendp[0] = '.'; + mnemonicendp[1] = 's'; + mnemonicendp += 2; +} + +static void +OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; +} + +static void +dofloat (int sizeflag) +{ + const struct dis386 *dp; + unsigned char floatop; + + floatop = codep[-1]; + + if (modrm.mod != 3) + { + int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; + + putop (float_mem[fp_indx], sizeflag); + obufp = op_out[0]; + op_ad = 2; + OP_E (float_mem_mode[fp_indx], sizeflag); + return; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + dp = &float_reg[floatop - 0xd8][modrm.reg]; + if (dp->name == NULL) + { + putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); + + /* Instruction fnstsw is only one with strange arg. */ + if (floatop == 0xdf && codep[-1] == 0xe0) + strcpy (op_out[0], names16[0]); + } + else + { + putop (dp->name, sizeflag); + + obufp = op_out[0]; + op_ad = 2; + if (dp->op[0].rtn) + (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); + + obufp = op_out[1]; + op_ad = 1; + if (dp->op[1].rtn) + (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); + } +} + +static void +OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + oappend ("%st" + intel_syntax); +} + +static void +OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + sprintf (scratchbuf, "%%st(%d)", modrm.rm); + oappend (scratchbuf + intel_syntax); +} + +/* Capital letters in template are macros. */ +static int +putop (const char *in_template, int sizeflag) +{ + const char *p; + int alt = 0; + int cond = 1; + unsigned int l = 0, len = 1; + char last[4]; + +#define SAVE_LAST(c) \ + if (l < len && l < sizeof (last)) \ + last[l++] = c; \ + else \ + abort (); + + for (p = in_template; *p; p++) + { + switch (*p) + { + default: + *obufp++ = *p; + break; + case '%': + len++; + break; + case '!': + cond = 0; + break; + case '{': + alt = 0; + if (intel_syntax) + { + while (*++p != '|') + if (*p == '}' || *p == '\0') + abort (); + } + /* Fall through. */ + case 'I': + alt = 1; + continue; + case '|': + while (*++p != '}') + { + if (*p == '\0') + abort (); + } + break; + case '}': + break; + case 'A': + if (intel_syntax) + break; + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + *obufp++ = 'b'; + break; + case 'B': + if (l == 0 && len == 1) + { +case_B: + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'b'; + } + else + { + if (l != 1 + || len != 2 + || last[0] != 'L') + { + SAVE_LAST (*p); + break; + } + + if (address_mode == mode_64bit + && !(prefixes & PREFIX_ADDR)) + { + *obufp++ = 'a'; + *obufp++ = 'b'; + *obufp++ = 's'; + } + + goto case_B; + } + break; + case 'C': + if (intel_syntax && !alt) + break; + if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) + { + if (sizeflag & DFLAG) + *obufp++ = intel_syntax ? 'd' : 'l'; + else + *obufp++ = intel_syntax ? 'w' : 's'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case 'D': + if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) + break; + USED_REX (REX_W); + if (modrm.mod == 3) + { + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = intel_syntax ? 'd' : 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + else + *obufp++ = 'w'; + break; + case 'E': /* For jcxz/jecxz */ + if (address_mode == mode_64bit) + { + if (sizeflag & AFLAG) + *obufp++ = 'r'; + else + *obufp++ = 'e'; + } + else + if (sizeflag & AFLAG) + *obufp++ = 'e'; + used_prefixes |= (prefixes & PREFIX_ADDR); + break; + case 'F': + if (intel_syntax) + break; + if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) + { + if (sizeflag & AFLAG) + *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; + else + *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; + used_prefixes |= (prefixes & PREFIX_ADDR); + } + break; + case 'G': + if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) + break; + if ((rex & REX_W) || (sizeflag & DFLAG)) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 'H': + if (intel_syntax) + break; + if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS + || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) + { + used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); + *obufp++ = ','; + *obufp++ = 'p'; + if (prefixes & PREFIX_DS) + *obufp++ = 't'; + else + *obufp++ = 'n'; + } + break; + case 'J': + if (intel_syntax) + break; + *obufp++ = 'l'; + break; + case 'K': + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else + *obufp++ = 'd'; + break; + case 'Z': + if (intel_syntax) + break; + if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) + { + *obufp++ = 'q'; + break; + } + /* Fall through. */ + goto case_L; + case 'L': + if (l != 0 || len != 1) + { + SAVE_LAST (*p); + break; + } +case_L: + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'l'; + break; + case 'M': + if (intel_mnemonic != cond) + *obufp++ = 'r'; + break; + case 'N': + if ((prefixes & PREFIX_FWAIT) == 0) + *obufp++ = 'n'; + else + used_prefixes |= PREFIX_FWAIT; + break; + case 'O': + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'o'; + else if (intel_syntax && (sizeflag & DFLAG)) + *obufp++ = 'q'; + else + *obufp++ = 'd'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 'T': + if (!intel_syntax + && address_mode == mode_64bit + && (sizeflag & DFLAG)) + { + *obufp++ = 'q'; + break; + } + /* Fall through. */ + case 'P': + if (intel_syntax) + { + if ((rex & REX_W) == 0 + && (prefixes & PREFIX_DATA)) + { + if ((sizeflag & DFLAG) == 0) + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + } + if ((prefixes & PREFIX_DATA) + || (rex & REX_W) + || (sizeflag & SUFFIX_ALWAYS)) + { + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + break; + case 'U': + if (intel_syntax) + break; + if (address_mode == mode_64bit && (sizeflag & DFLAG)) + { + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + *obufp++ = 'q'; + break; + } + /* Fall through. */ + goto case_Q; + case 'Q': + if (l == 0 && len == 1) + { +case_Q: + if (intel_syntax && !alt) + break; + USED_REX (REX_W); + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + { + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = intel_syntax ? 'd' : 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + } + else + { + if (l != 1 || len != 2 || last[0] != 'L') + { + SAVE_LAST (*p); + break; + } + if (intel_syntax + || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + break; + if ((rex & REX_W)) + { + USED_REX (REX_W); + *obufp++ = 'q'; + } + else + *obufp++ = 'l'; + } + break; + case 'R': + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else if (sizeflag & DFLAG) + { + if (intel_syntax) + *obufp++ = 'd'; + else + *obufp++ = 'l'; + } + else + *obufp++ = 'w'; + if (intel_syntax && !p[1] + && ((rex & REX_W) || (sizeflag & DFLAG))) + *obufp++ = 'e'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case 'V': + if (l == 0 && len == 1) + { + if (intel_syntax) + break; + if (address_mode == mode_64bit && (sizeflag & DFLAG)) + { + if (sizeflag & SUFFIX_ALWAYS) + *obufp++ = 'q'; + break; + } + } + else + { + if (l != 1 + || len != 2 + || last[0] != 'L') + { + SAVE_LAST (*p); + break; + } + + if (rex & REX_W) + { + *obufp++ = 'a'; + *obufp++ = 'b'; + *obufp++ = 's'; + } + } + /* Fall through. */ + goto case_S; + case 'S': + if (l == 0 && len == 1) + { +case_S: + if (intel_syntax) + break; + if (sizeflag & SUFFIX_ALWAYS) + { + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + } + else + { + if (l != 1 + || len != 2 + || last[0] != 'L') + { + SAVE_LAST (*p); + break; + } + + if (address_mode == mode_64bit + && !(prefixes & PREFIX_ADDR)) + { + *obufp++ = 'a'; + *obufp++ = 'b'; + *obufp++ = 's'; + } + + goto case_S; + } + break; + case 'X': + if (l != 0 || len != 1) + { + SAVE_LAST (*p); + break; + } + if (need_vex && vex.prefix) + { + if (vex.prefix == DATA_PREFIX_OPCODE) + *obufp++ = 'd'; + else + *obufp++ = 's'; + } + else + { + if (prefixes & PREFIX_DATA) + *obufp++ = 'd'; + else + *obufp++ = 's'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case 'Y': + if (l == 0 && len == 1) + { + if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) + break; + if (rex & REX_W) + { + USED_REX (REX_W); + *obufp++ = 'q'; + } + break; + } + else + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex) + abort (); + if (intel_syntax + || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + break; + switch (vex.length) + { + case 128: + *obufp++ = 'x'; + break; + case 256: + *obufp++ = 'y'; + break; + default: + abort (); + } + } + break; + case 'W': + if (l == 0 && len == 1) + { + /* operand size flag for cwtl, cbtw */ + USED_REX (REX_W); + if (rex & REX_W) + { + if (intel_syntax) + *obufp++ = 'd'; + else + *obufp++ = 'l'; + } + else if (sizeflag & DFLAG) + *obufp++ = 'w'; + else + *obufp++ = 'b'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + } + else + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex) + abort (); + *obufp++ = vex.w ? 'd': 's'; + } + break; + } + alt = 0; + } + *obufp = 0; + mnemonicendp = obufp; + return 0; +} + +static void +oappend (const char *s) +{ + obufp = stpcpy (obufp, s); +} + +static void +append_seg (void) +{ + if (prefixes & PREFIX_CS) + { + used_prefixes |= PREFIX_CS; + oappend ("%cs:" + intel_syntax); + } + if (prefixes & PREFIX_DS) + { + used_prefixes |= PREFIX_DS; + oappend ("%ds:" + intel_syntax); + } + if (prefixes & PREFIX_SS) + { + used_prefixes |= PREFIX_SS; + oappend ("%ss:" + intel_syntax); + } + if (prefixes & PREFIX_ES) + { + used_prefixes |= PREFIX_ES; + oappend ("%es:" + intel_syntax); + } + if (prefixes & PREFIX_FS) + { + used_prefixes |= PREFIX_FS; + oappend ("%fs:" + intel_syntax); + } + if (prefixes & PREFIX_GS) + { + used_prefixes |= PREFIX_GS; + oappend ("%gs:" + intel_syntax); + } +} + +static void +OP_indirE (int bytemode, int sizeflag) +{ + if (!intel_syntax) + oappend ("*"); + OP_E (bytemode, sizeflag); +} + +static void +print_operand_value (char *buf, int hex, bfd_vma disp) +{ + if (address_mode == mode_64bit) + { + if (hex) + { + char tmp[30]; + int i; + buf[0] = '0'; + buf[1] = 'x'; + sprintf_vma (tmp, disp); + for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); + strcpy (buf + 2, tmp + i); + } + else + { + bfd_signed_vma v = disp; + char tmp[30]; + int i; + if (v < 0) + { + *(buf++) = '-'; + v = -disp; + /* Check for possible overflow on 0x8000000000000000. */ + if (v < 0) + { + strcpy (buf, "9223372036854775808"); + return; + } + } + if (!v) + { + strcpy (buf, "0"); + return; + } + + i = 0; + tmp[29] = 0; + while (v) + { + tmp[28 - i] = (v % 10) + '0'; + v /= 10; + i++; + } + strcpy (buf, tmp + 29 - i); + } + } + else + { + if (hex) + sprintf (buf, "0x%x", (unsigned int) disp); + else + sprintf (buf, "%d", (int) disp); + } +} + +/* Put DISP in BUF as signed hex number. */ + +static void +print_displacement (char *buf, bfd_vma disp) +{ + bfd_signed_vma val = disp; + char tmp[30]; + int i, j = 0; + + if (val < 0) + { + buf[j++] = '-'; + val = -disp; + + /* Check for possible overflow. */ + if (val < 0) + { + switch (address_mode) + { + case mode_64bit: + strcpy (buf + j, "0x8000000000000000"); + break; + case mode_32bit: + strcpy (buf + j, "0x80000000"); + break; + case mode_16bit: + strcpy (buf + j, "0x8000"); + break; + } + return; + } + } + + buf[j++] = '0'; + buf[j++] = 'x'; + + sprintf_vma (tmp, (bfd_vma) val); + for (i = 0; tmp[i] == '0'; i++) + continue; + if (tmp[i] == '\0') + i--; + strcpy (buf + j, tmp + i); +} + +static void +intel_operand_size (int bytemode, int sizeflag) +{ + switch (bytemode) + { + case b_mode: + case b_swap_mode: + case dqb_mode: + oappend ("BYTE PTR "); + break; + case w_mode: + case dqw_mode: + oappend ("WORD PTR "); + break; + case stack_v_mode: + if (address_mode == mode_64bit && (sizeflag & DFLAG)) + { + oappend ("QWORD PTR "); + break; + } + /* FALLTHRU */ + case v_mode: + case v_swap_mode: + case dq_mode: + USED_REX (REX_W); + if (rex & REX_W) + oappend ("QWORD PTR "); + else + { + if ((sizeflag & DFLAG) || bytemode == dq_mode) + oappend ("DWORD PTR "); + else + oappend ("WORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case z_mode: + if ((rex & REX_W) || (sizeflag & DFLAG)) + *obufp++ = 'D'; + oappend ("WORD PTR "); + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case a_mode: + if (sizeflag & DFLAG) + oappend ("QWORD PTR "); + else + oappend ("DWORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case d_mode: + case d_scalar_mode: + case d_scalar_swap_mode: + case d_swap_mode: + case dqd_mode: + oappend ("DWORD PTR "); + break; + case q_mode: + case q_scalar_mode: + case q_scalar_swap_mode: + case q_swap_mode: + oappend ("QWORD PTR "); + break; + case m_mode: + if (address_mode == mode_64bit) + oappend ("QWORD PTR "); + else + oappend ("DWORD PTR "); + break; + case f_mode: + if (sizeflag & DFLAG) + oappend ("FWORD PTR "); + else + oappend ("DWORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case t_mode: + oappend ("TBYTE PTR "); + break; + case x_mode: + case x_swap_mode: + if (need_vex) + { + switch (vex.length) + { + case 128: + oappend ("XMMWORD PTR "); + break; + case 256: + oappend ("YMMWORD PTR "); + break; + default: + abort (); + } + } + else + oappend ("XMMWORD PTR "); + break; + case xmm_mode: + oappend ("XMMWORD PTR "); + break; + case xmmq_mode: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + oappend ("QWORD PTR "); + break; + case 256: + oappend ("XMMWORD PTR "); + break; + default: + abort (); + } + break; + case ymmq_mode: + if (!need_vex) + abort (); + + switch (vex.length) + { + case 128: + oappend ("QWORD PTR "); + break; + case 256: + oappend ("YMMWORD PTR "); + break; + default: + abort (); + } + break; + case o_mode: + oappend ("OWORD PTR "); + break; + case vex_w_dq_mode: + case vex_scalar_w_dq_mode: + if (!need_vex) + abort (); + + if (vex.w) + oappend ("QWORD PTR "); + else + oappend ("DWORD PTR "); + break; + default: + break; + } +} + +static void +OP_E_register (int bytemode, int sizeflag) +{ + int reg = modrm.rm; + const char **names; + + USED_REX (REX_B); + if ((rex & REX_B)) + reg += 8; + + if ((sizeflag & SUFFIX_ALWAYS) + && (bytemode == b_swap_mode || bytemode == v_swap_mode)) + swap_operand (); + + switch (bytemode) + { + case b_mode: + case b_swap_mode: + USED_REX (0); + if (rex) + names = names8rex; + else + names = names8; + break; + case w_mode: + names = names16; + break; + case d_mode: + names = names32; + break; + case q_mode: + names = names64; + break; + case m_mode: + names = address_mode == mode_64bit ? names64 : names32; + break; + case stack_v_mode: + if (address_mode == mode_64bit && (sizeflag & DFLAG)) + { + names = names64; + break; + } + bytemode = v_mode; + /* FALLTHRU */ + case v_mode: + case v_swap_mode: + case dq_mode: + case dqb_mode: + case dqd_mode: + case dqw_mode: + USED_REX (REX_W); + if (rex & REX_W) + names = names64; + else + { + if ((sizeflag & DFLAG) + || (bytemode != v_mode + && bytemode != v_swap_mode)) + names = names32; + else + names = names16; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case 0: + return; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + oappend (names[reg]); +} + +static void +OP_E_memory (int bytemode, int sizeflag) +{ + bfd_vma disp = 0; + int add = (rex & REX_B) ? 8 : 0; + int riprel = 0; + + USED_REX (REX_B); + if (intel_syntax) + intel_operand_size (bytemode, sizeflag); + append_seg (); + + if ((sizeflag & AFLAG) || address_mode == mode_64bit) + { + /* 32/64 bit address mode */ + int havedisp; + int havesib; + int havebase; + int haveindex; + int needindex; + int base, rbase; + int vindex = 0; + int scale = 0; + + havesib = 0; + havebase = 1; + haveindex = 0; + base = modrm.rm; + + if (base == 4) + { + havesib = 1; + vindex = sib.index; + scale = sib.scale; + base = sib.base; + USED_REX (REX_X); + if (rex & REX_X) + vindex += 8; + haveindex = vindex != 4; + codep++; + } + rbase = base + add; + + switch (modrm.mod) + { + case 0: + if (base == 5) + { + havebase = 0; + if (address_mode == mode_64bit && !havesib) + riprel = 1; + disp = get32s (); + } + break; + case 1: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case 2: + disp = get32s (); + break; + } + + /* In 32bit mode, we need index register to tell [offset] from + [eiz*1 + offset]. */ + needindex = (havesib + && !havebase + && !haveindex + && address_mode == mode_32bit); + havedisp = (havebase + || needindex + || (havesib && (haveindex || scale != 0))); + + if (!intel_syntax) + if (modrm.mod != 0 || base == 5) + { + if (havedisp || riprel) + print_displacement (scratchbuf, disp); + else + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); + if (riprel) + { + set_op (disp, 1); + oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); + } + } + + if (havebase || haveindex || riprel) + used_prefixes |= PREFIX_ADDR; + + if (havedisp || (intel_syntax && riprel)) + { + *obufp++ = open_char; + if (intel_syntax && riprel) + { + set_op (disp, 1); + oappend (sizeflag & AFLAG ? "rip" : "eip"); + } + *obufp = '\0'; + if (havebase) + oappend (address_mode == mode_64bit && (sizeflag & AFLAG) + ? names64[rbase] : names32[rbase]); + if (havesib) + { + /* ESP/RSP won't allow index. If base isn't ESP/RSP, + print index to tell base + index from base. */ + if (scale != 0 + || needindex + || haveindex + || (havebase && base != ESP_REG_NUM)) + { + if (!intel_syntax || havebase) + { + *obufp++ = separator_char; + *obufp = '\0'; + } + if (haveindex) + oappend (address_mode == mode_64bit + && (sizeflag & AFLAG) + ? names64[vindex] : names32[vindex]); + else + oappend (address_mode == mode_64bit + && (sizeflag & AFLAG) + ? index64 : index32); + + *obufp++ = scale_char; + *obufp = '\0'; + sprintf (scratchbuf, "%d", 1 << scale); + oappend (scratchbuf); + } + } + if (intel_syntax + && (disp || modrm.mod != 0 || base == 5)) + { + if (!havedisp || (bfd_signed_vma) disp >= 0) + { + *obufp++ = '+'; + *obufp = '\0'; + } + else if (modrm.mod != 1 && disp != -disp) + { + *obufp++ = '-'; + *obufp = '\0'; + disp = - (bfd_signed_vma) disp; + } + + if (havedisp) + print_displacement (scratchbuf, disp); + else + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); + } + + *obufp++ = close_char; + *obufp = '\0'; + } + else if (intel_syntax) + { + if (modrm.mod != 0 || base == 5) + { + if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS)) + ; + else + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); + } + } + } + else + { + /* 16 bit address mode */ + used_prefixes |= prefixes & PREFIX_ADDR; + switch (modrm.mod) + { + case 0: + if (modrm.rm == 6) + { + disp = get16 (); + if ((disp & 0x8000) != 0) + disp -= 0x10000; + } + break; + case 1: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case 2: + disp = get16 (); + if ((disp & 0x8000) != 0) + disp -= 0x10000; + break; + } + + if (!intel_syntax) + if (modrm.mod != 0 || modrm.rm == 6) + { + print_displacement (scratchbuf, disp); + oappend (scratchbuf); + } + + if (modrm.mod != 0 || modrm.rm != 6) + { + *obufp++ = open_char; + *obufp = '\0'; + oappend (index16[modrm.rm]); + if (intel_syntax + && (disp || modrm.mod != 0 || modrm.rm == 6)) + { + if ((bfd_signed_vma) disp >= 0) + { + *obufp++ = '+'; + *obufp = '\0'; + } + else if (modrm.mod != 1) + { + *obufp++ = '-'; + *obufp = '\0'; + disp = - (bfd_signed_vma) disp; + } + + print_displacement (scratchbuf, disp); + oappend (scratchbuf); + } + + *obufp++ = close_char; + *obufp = '\0'; + } + else if (intel_syntax) + { + if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS)) + ; + else + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + print_operand_value (scratchbuf, 1, disp & 0xffff); + oappend (scratchbuf); + } + } +} + +static void +OP_E (int bytemode, int sizeflag) +{ + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (modrm.mod == 3) + OP_E_register (bytemode, sizeflag); + else + OP_E_memory (bytemode, sizeflag); +} + +static void +OP_G (int bytemode, int sizeflag) +{ + int add = 0; + USED_REX (REX_R); + if (rex & REX_R) + add += 8; + switch (bytemode) + { + case b_mode: + USED_REX (0); + if (rex) + oappend (names8rex[modrm.reg + add]); + else + oappend (names8[modrm.reg + add]); + break; + case w_mode: + oappend (names16[modrm.reg + add]); + break; + case d_mode: + oappend (names32[modrm.reg + add]); + break; + case q_mode: + oappend (names64[modrm.reg + add]); + break; + case v_mode: + case dq_mode: + case dqb_mode: + case dqd_mode: + case dqw_mode: + USED_REX (REX_W); + if (rex & REX_W) + oappend (names64[modrm.reg + add]); + else + { + if ((sizeflag & DFLAG) || bytemode != v_mode) + oappend (names32[modrm.reg + add]); + else + oappend (names16[modrm.reg + add]); + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case m_mode: + if (address_mode == mode_64bit) + oappend (names64[modrm.reg + add]); + else + oappend (names32[modrm.reg + add]); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } +} + +static bfd_vma +get64 (void) +{ + bfd_vma x; +#ifdef BFD64 + unsigned int a; + unsigned int b; + + FETCH_DATA (the_info, codep + 8); + a = *codep++ & 0xff; + a |= (*codep++ & 0xff) << 8; + a |= (*codep++ & 0xff) << 16; + a |= (*codep++ & 0xff) << 24; + b = *codep++ & 0xff; + b |= (*codep++ & 0xff) << 8; + b |= (*codep++ & 0xff) << 16; + b |= (*codep++ & 0xff) << 24; + x = a + ((bfd_vma) b << 32); +#else + abort (); + x = 0; +#endif + return x; +} + +static bfd_signed_vma +get32 (void) +{ + bfd_signed_vma x = 0; + + FETCH_DATA (the_info, codep + 4); + x = *codep++ & (bfd_signed_vma) 0xff; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; + return x; +} + +static bfd_signed_vma +get32s (void) +{ + bfd_signed_vma x = 0; + + FETCH_DATA (the_info, codep + 4); + x = *codep++ & (bfd_signed_vma) 0xff; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; + x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; + + x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); + + return x; +} + +static int +get16 (void) +{ + int x = 0; + + FETCH_DATA (the_info, codep + 2); + x = *codep++ & 0xff; + x |= (*codep++ & 0xff) << 8; + return x; +} + +static void +set_op (bfd_vma op, int riprel) +{ + op_index[op_ad] = op_ad; + if (address_mode == mode_64bit) + { + op_address[op_ad] = op; + op_riprel[op_ad] = riprel; + } + else + { + /* Mask to get a 32-bit address. */ + op_address[op_ad] = op & 0xffffffff; + op_riprel[op_ad] = riprel & 0xffffffff; + } +} + +static void +OP_REG (int code, int sizeflag) +{ + const char *s; + int add; + USED_REX (REX_B); + if (rex & REX_B) + add = 8; + else + add = 0; + + switch (code) + { + case ax_reg: case cx_reg: case dx_reg: case bx_reg: + case sp_reg: case bp_reg: case si_reg: case di_reg: + s = names16[code - ax_reg + add]; + break; + case es_reg: case ss_reg: case cs_reg: + case ds_reg: case fs_reg: case gs_reg: + s = names_seg[code - es_reg + add]; + break; + case al_reg: case ah_reg: case cl_reg: case ch_reg: + case dl_reg: case dh_reg: case bl_reg: case bh_reg: + USED_REX (0); + if (rex) + s = names8rex[code - al_reg + add]; + else + s = names8[code - al_reg]; + break; + case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: + case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: + if (address_mode == mode_64bit && (sizeflag & DFLAG)) + { + s = names64[code - rAX_reg + add]; + break; + } + code += eAX_reg - rAX_reg; + /* Fall through. */ + case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: + case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: + USED_REX (REX_W); + if (rex & REX_W) + s = names64[code - eAX_reg + add]; + else + { + if (sizeflag & DFLAG) + s = names32[code - eAX_reg + add]; + else + s = names16[code - eAX_reg + add]; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + default: + s = INTERNAL_DISASSEMBLER_ERROR; + break; + } + oappend (s); +} + +static void +OP_IMREG (int code, int sizeflag) +{ + const char *s; + + switch (code) + { + case indir_dx_reg: + if (intel_syntax) + s = "dx"; + else + s = "(%dx)"; + break; + case ax_reg: case cx_reg: case dx_reg: case bx_reg: + case sp_reg: case bp_reg: case si_reg: case di_reg: + s = names16[code - ax_reg]; + break; + case es_reg: case ss_reg: case cs_reg: + case ds_reg: case fs_reg: case gs_reg: + s = names_seg[code - es_reg]; + break; + case al_reg: case ah_reg: case cl_reg: case ch_reg: + case dl_reg: case dh_reg: case bl_reg: case bh_reg: + USED_REX (0); + if (rex) + s = names8rex[code - al_reg]; + else + s = names8[code - al_reg]; + break; + case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: + case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: + USED_REX (REX_W); + if (rex & REX_W) + s = names64[code - eAX_reg]; + else + { + if (sizeflag & DFLAG) + s = names32[code - eAX_reg]; + else + s = names16[code - eAX_reg]; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case z_mode_ax_reg: + if ((rex & REX_W) || (sizeflag & DFLAG)) + s = *names32; + else + s = *names16; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + s = INTERNAL_DISASSEMBLER_ERROR; + break; + } + oappend (s); +} + +static void +OP_I (int bytemode, int sizeflag) +{ + bfd_signed_vma op; + bfd_signed_vma mask = -1; + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + mask = 0xff; + break; + case q_mode: + if (address_mode == mode_64bit) + { + op = get32s (); + break; + } + /* Fall through. */ + case v_mode: + USED_REX (REX_W); + if (rex & REX_W) + op = get32s (); + else + { + if (sizeflag & DFLAG) + { + op = get32 (); + mask = 0xffffffff; + } + else + { + op = get16 (); + mask = 0xfffff; + } + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case w_mode: + mask = 0xfffff; + op = get16 (); + break; + case const_1_mode: + if (intel_syntax) + oappend ("1"); + return; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + op &= mask; + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; +} + +static void +OP_I64 (int bytemode, int sizeflag) +{ + bfd_signed_vma op; + bfd_signed_vma mask = -1; + + if (address_mode != mode_64bit) + { + OP_I (bytemode, sizeflag); + return; + } + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + mask = 0xff; + break; + case v_mode: + USED_REX (REX_W); + if (rex & REX_W) + op = get64 (); + else + { + if (sizeflag & DFLAG) + { + op = get32 (); + mask = 0xffffffff; + } + else + { + op = get16 (); + mask = 0xfffff; + } + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case w_mode: + mask = 0xfffff; + op = get16 (); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + op &= mask; + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; +} + +static void +OP_sI (int bytemode, int sizeflag) +{ + bfd_signed_vma op; + + switch (bytemode) + { + case b_mode: + case b_T_mode: + FETCH_DATA (the_info, codep + 1); + op = *codep++; + if ((op & 0x80) != 0) + op -= 0x100; + if (bytemode == b_T_mode) + { + if (address_mode != mode_64bit + || !(sizeflag & DFLAG)) + { + if (sizeflag & DFLAG) + op &= 0xffffffff; + else + op &= 0xffff; + } + } + else + { + if (!(rex & REX_W)) + { + if (sizeflag & DFLAG) + op &= 0xffffffff; + else + op &= 0xffff; + } + } + break; + case v_mode: + if (sizeflag & DFLAG) + op = get32s (); + else + op = get16 (); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, op); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_J (int bytemode, int sizeflag) +{ + bfd_vma disp; + bfd_vma mask = -1; + bfd_vma segment = 0; + + switch (bytemode) + { + case b_mode: + FETCH_DATA (the_info, codep + 1); + disp = *codep++; + if ((disp & 0x80) != 0) + disp -= 0x100; + break; + case v_mode: + USED_REX (REX_W); + if ((sizeflag & DFLAG) || (rex & REX_W)) + disp = get32s (); + else + { + disp = get16 (); + if ((disp & 0x8000) != 0) + disp -= 0x10000; + /* In 16bit mode, address is wrapped around at 64k within + the same segment. Otherwise, a data16 prefix on a jump + instruction means that the pc is masked to 16 bits after + the displacement is added! */ + mask = 0xffff; + if ((prefixes & PREFIX_DATA) == 0) + segment = ((start_pc + codep - start_codep) + & ~((bfd_vma) 0xffff)); + } + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + return; + } + disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; + set_op (disp, 0); + print_operand_value (scratchbuf, 1, disp); + oappend (scratchbuf); +} + +static void +OP_SEG (int bytemode, int sizeflag) +{ + if (bytemode == w_mode) + oappend (names_seg[modrm.reg]); + else + OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); +} + +static void +OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) +{ + int seg, offset; + + if (sizeflag & DFLAG) + { + offset = get32 (); + seg = get16 (); + } + else + { + offset = get16 (); + seg = get16 (); + } + used_prefixes |= (prefixes & PREFIX_DATA); + if (intel_syntax) + sprintf (scratchbuf, "0x%x:0x%x", seg, offset); + else + sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); + oappend (scratchbuf); +} + +static void +OP_OFF (int bytemode, int sizeflag) +{ + bfd_vma off; + + if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) + intel_operand_size (bytemode, sizeflag); + append_seg (); + + if ((sizeflag & AFLAG) || address_mode == mode_64bit) + off = get32 (); + else + off = get16 (); + + if (intel_syntax) + { + if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + } + print_operand_value (scratchbuf, 1, off); + oappend (scratchbuf); +} + +static void +OP_OFF64 (int bytemode, int sizeflag) +{ + bfd_vma off; + + if (address_mode != mode_64bit + || (prefixes & PREFIX_ADDR)) + { + OP_OFF (bytemode, sizeflag); + return; + } + + if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) + intel_operand_size (bytemode, sizeflag); + append_seg (); + + off = get64 (); + + if (intel_syntax) + { + if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + { + oappend (names_seg[ds_reg - es_reg]); + oappend (":"); + } + } + print_operand_value (scratchbuf, 1, off); + oappend (scratchbuf); +} + +static void +ptr_reg (int code, int sizeflag) +{ + const char *s; + + *obufp++ = open_char; + used_prefixes |= (prefixes & PREFIX_ADDR); + if (address_mode == mode_64bit) + { + if (!(sizeflag & AFLAG)) + s = names32[code - eAX_reg]; + else + s = names64[code - eAX_reg]; + } + else if (sizeflag & AFLAG) + s = names32[code - eAX_reg]; + else + s = names16[code - eAX_reg]; + oappend (s); + *obufp++ = close_char; + *obufp = 0; +} + +static void +OP_ESreg (int code, int sizeflag) +{ + if (intel_syntax) + { + switch (codep[-1]) + { + case 0x6d: /* insw/insl */ + intel_operand_size (z_mode, sizeflag); + break; + case 0xa5: /* movsw/movsl/movsq */ + case 0xa7: /* cmpsw/cmpsl/cmpsq */ + case 0xab: /* stosw/stosl */ + case 0xaf: /* scasw/scasl */ + intel_operand_size (v_mode, sizeflag); + break; + default: + intel_operand_size (b_mode, sizeflag); + } + } + oappend ("%es:" + intel_syntax); + ptr_reg (code, sizeflag); +} + +static void +OP_DSreg (int code, int sizeflag) +{ + if (intel_syntax) + { + switch (codep[-1]) + { + case 0x6f: /* outsw/outsl */ + intel_operand_size (z_mode, sizeflag); + break; + case 0xa5: /* movsw/movsl/movsq */ + case 0xa7: /* cmpsw/cmpsl/cmpsq */ + case 0xad: /* lodsw/lodsl/lodsq */ + intel_operand_size (v_mode, sizeflag); + break; + default: + intel_operand_size (b_mode, sizeflag); + } + } + if ((prefixes + & (PREFIX_CS + | PREFIX_DS + | PREFIX_SS + | PREFIX_ES + | PREFIX_FS + | PREFIX_GS)) == 0) + prefixes |= PREFIX_DS; + append_seg (); + ptr_reg (code, sizeflag); +} + +static void +OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + int add; + if (rex & REX_R) + { + USED_REX (REX_R); + add = 8; + } + else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) + { + all_prefixes[last_lock_prefix] = 0; + used_prefixes |= PREFIX_LOCK; + add = 8; + } + else + add = 0; + sprintf (scratchbuf, "%%cr%d", modrm.reg + add); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + int add; + USED_REX (REX_R); + if (rex & REX_R) + add = 8; + else + add = 0; + if (intel_syntax) + sprintf (scratchbuf, "db%d", modrm.reg + add); + else + sprintf (scratchbuf, "%%db%d", modrm.reg + add); + oappend (scratchbuf); +} + +static void +OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + sprintf (scratchbuf, "%%tr%d", modrm.reg); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_R (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + OP_E (bytemode, sizeflag); + else + BadOp (); +} + +static void +OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg = modrm.reg; + const char **names; + + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + { + names = names_xmm; + USED_REX (REX_R); + if (rex & REX_R) + reg += 8; + } + else + names = names_mm; + oappend (names[reg]); +} + +static void +OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg = modrm.reg; + const char **names; + + USED_REX (REX_R); + if (rex & REX_R) + reg += 8; + if (need_vex + && bytemode != xmm_mode + && bytemode != scalar_mode) + { + switch (vex.length) + { + case 128: + names = names_xmm; + break; + case 256: + names = names_ymm; + break; + default: + abort (); + } + } + else + names = names_xmm; + oappend (names[reg]); +} + +static void +OP_EM (int bytemode, int sizeflag) +{ + int reg; + const char **names; + + if (modrm.mod != 3) + { + if (intel_syntax + && (bytemode == v_mode || bytemode == v_swap_mode)) + { + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } + OP_E (bytemode, sizeflag); + return; + } + + if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) + swap_operand (); + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + used_prefixes |= (prefixes & PREFIX_DATA); + reg = modrm.rm; + if (prefixes & PREFIX_DATA) + { + names = names_xmm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + } + else + names = names_mm; + oappend (names[reg]); +} + +/* cvt* are the only instructions in sse2 which have + both SSE and MMX operands and also have 0x66 prefix + in their opcode. 0x66 was originally used to differentiate + between SSE and MMX instruction(operands). So we have to handle the + cvt* separately using OP_EMC and OP_MXC */ +static void +OP_EMC (int bytemode, int sizeflag) +{ + if (modrm.mod != 3) + { + if (intel_syntax && bytemode == v_mode) + { + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } + OP_E (bytemode, sizeflag); + return; + } + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + used_prefixes |= (prefixes & PREFIX_DATA); + oappend (names_mm[modrm.rm]); +} + +static void +OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + used_prefixes |= (prefixes & PREFIX_DATA); + oappend (names_mm[modrm.reg]); +} + +static void +OP_EX (int bytemode, int sizeflag) +{ + int reg; + const char **names; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (modrm.mod != 3) + { + OP_E_memory (bytemode, sizeflag); + return; + } + + reg = modrm.rm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + + if ((sizeflag & SUFFIX_ALWAYS) + && (bytemode == x_swap_mode + || bytemode == d_swap_mode + || bytemode == d_scalar_swap_mode + || bytemode == q_swap_mode + || bytemode == q_scalar_swap_mode)) + swap_operand (); + + if (need_vex + && bytemode != xmm_mode + && bytemode != xmmq_mode + && bytemode != d_scalar_mode + && bytemode != d_scalar_swap_mode + && bytemode != q_scalar_mode + && bytemode != q_scalar_swap_mode + && bytemode != vex_scalar_w_dq_mode) + { + switch (vex.length) + { + case 128: + names = names_xmm; + break; + case 256: + names = names_ymm; + break; + default: + abort (); + } + } + else + names = names_xmm; + oappend (names[reg]); +} + +static void +OP_MS (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + OP_EM (bytemode, sizeflag); + else + BadOp (); +} + +static void +OP_XS (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + OP_EX (bytemode, sizeflag); + else + BadOp (); +} + +static void +OP_M (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ + BadOp (); + else + OP_E (bytemode, sizeflag); +} + +static void +OP_0f07 (int bytemode, int sizeflag) +{ + if (modrm.mod != 3 || modrm.rm != 0) + BadOp (); + else + OP_E (bytemode, sizeflag); +} + +/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in + 32bit mode and "xchg %rax,%rax" in 64bit mode. */ + +static void +NOP_Fixup1 (int bytemode, int sizeflag) +{ + if ((prefixes & PREFIX_DATA) != 0 + || (rex != 0 + && rex != 0x48 + && address_mode == mode_64bit)) + OP_REG (bytemode, sizeflag); + else + strcpy (obuf, "nop"); +} + +static void +NOP_Fixup2 (int bytemode, int sizeflag) +{ + if ((prefixes & PREFIX_DATA) != 0 + || (rex != 0 + && rex != 0x48 + && address_mode == mode_64bit)) + OP_IMREG (bytemode, sizeflag); +} + +static const char *const Suffix3DNow[] = { +/* 00 */ NULL, NULL, NULL, NULL, +/* 04 */ NULL, NULL, NULL, NULL, +/* 08 */ NULL, NULL, NULL, NULL, +/* 0C */ "pi2fw", "pi2fd", NULL, NULL, +/* 10 */ NULL, NULL, NULL, NULL, +/* 14 */ NULL, NULL, NULL, NULL, +/* 18 */ NULL, NULL, NULL, NULL, +/* 1C */ "pf2iw", "pf2id", NULL, NULL, +/* 20 */ NULL, NULL, NULL, NULL, +/* 24 */ NULL, NULL, NULL, NULL, +/* 28 */ NULL, NULL, NULL, NULL, +/* 2C */ NULL, NULL, NULL, NULL, +/* 30 */ NULL, NULL, NULL, NULL, +/* 34 */ NULL, NULL, NULL, NULL, +/* 38 */ NULL, NULL, NULL, NULL, +/* 3C */ NULL, NULL, NULL, NULL, +/* 40 */ NULL, NULL, NULL, NULL, +/* 44 */ NULL, NULL, NULL, NULL, +/* 48 */ NULL, NULL, NULL, NULL, +/* 4C */ NULL, NULL, NULL, NULL, +/* 50 */ NULL, NULL, NULL, NULL, +/* 54 */ NULL, NULL, NULL, NULL, +/* 58 */ NULL, NULL, NULL, NULL, +/* 5C */ NULL, NULL, NULL, NULL, +/* 60 */ NULL, NULL, NULL, NULL, +/* 64 */ NULL, NULL, NULL, NULL, +/* 68 */ NULL, NULL, NULL, NULL, +/* 6C */ NULL, NULL, NULL, NULL, +/* 70 */ NULL, NULL, NULL, NULL, +/* 74 */ NULL, NULL, NULL, NULL, +/* 78 */ NULL, NULL, NULL, NULL, +/* 7C */ NULL, NULL, NULL, NULL, +/* 80 */ NULL, NULL, NULL, NULL, +/* 84 */ NULL, NULL, NULL, NULL, +/* 88 */ NULL, NULL, "pfnacc", NULL, +/* 8C */ NULL, NULL, "pfpnacc", NULL, +/* 90 */ "pfcmpge", NULL, NULL, NULL, +/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", +/* 98 */ NULL, NULL, "pfsub", NULL, +/* 9C */ NULL, NULL, "pfadd", NULL, +/* A0 */ "pfcmpgt", NULL, NULL, NULL, +/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", +/* A8 */ NULL, NULL, "pfsubr", NULL, +/* AC */ NULL, NULL, "pfacc", NULL, +/* B0 */ "pfcmpeq", NULL, NULL, NULL, +/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", +/* B8 */ NULL, NULL, NULL, "pswapd", +/* BC */ NULL, NULL, NULL, "pavgusb", +/* C0 */ NULL, NULL, NULL, NULL, +/* C4 */ NULL, NULL, NULL, NULL, +/* C8 */ NULL, NULL, NULL, NULL, +/* CC */ NULL, NULL, NULL, NULL, +/* D0 */ NULL, NULL, NULL, NULL, +/* D4 */ NULL, NULL, NULL, NULL, +/* D8 */ NULL, NULL, NULL, NULL, +/* DC */ NULL, NULL, NULL, NULL, +/* E0 */ NULL, NULL, NULL, NULL, +/* E4 */ NULL, NULL, NULL, NULL, +/* E8 */ NULL, NULL, NULL, NULL, +/* EC */ NULL, NULL, NULL, NULL, +/* F0 */ NULL, NULL, NULL, NULL, +/* F4 */ NULL, NULL, NULL, NULL, +/* F8 */ NULL, NULL, NULL, NULL, +/* FC */ NULL, NULL, NULL, NULL, +}; + +static void +OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + const char *mnemonic; + + FETCH_DATA (the_info, codep + 1); + /* AMD 3DNow! instructions are specified by an opcode suffix in the + place where an 8-bit immediate would normally go. ie. the last + byte of the instruction. */ + obufp = mnemonicendp; + mnemonic = Suffix3DNow[*codep++ & 0xff]; + if (mnemonic) + oappend (mnemonic); + else + { + /* Since a variable sized modrm/sib chunk is between the start + of the opcode (0x0f0f) and the opcode suffix, we need to do + all the modrm processing first, and don't know until now that + we have a bad opcode. This necessitates some cleaning up. */ + op_out[0][0] = '\0'; + op_out[1][0] = '\0'; + BadOp (); + } + mnemonicendp = obufp; +} + +static struct op simd_cmp_op[] = +{ + { STRING_COMMA_LEN ("eq") }, + { STRING_COMMA_LEN ("lt") }, + { STRING_COMMA_LEN ("le") }, + { STRING_COMMA_LEN ("unord") }, + { STRING_COMMA_LEN ("neq") }, + { STRING_COMMA_LEN ("nlt") }, + { STRING_COMMA_LEN ("nle") }, + { STRING_COMMA_LEN ("ord") } +}; + +static void +CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (simd_cmp_op)) + { + char suffix [3]; + char *p = mnemonicendp - 2; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); + mnemonicendp += simd_cmp_op[cmp_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} + +static void +OP_Mwait (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* mwait %eax,%ecx */ + if (!intel_syntax) + { + const char **names = (address_mode == mode_64bit + ? names64 : names32); + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names[1]); + two_source_ops = 1; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; +} + +static void +OP_Monitor (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* monitor %eax,%ecx,%edx" */ + if (!intel_syntax) + { + const char **op1_names; + const char **names = (address_mode == mode_64bit + ? names64 : names32); + + if (!(prefixes & PREFIX_ADDR)) + op1_names = (address_mode == mode_16bit + ? names16 : names); + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + op1_names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + strcpy (op_out[0], op1_names[0]); + strcpy (op_out[1], names[1]); + strcpy (op_out[2], names[2]); + two_source_ops = 1; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; +} + +static void +BadOp (void) +{ + /* Throw away prefixes and 1st. opcode byte. */ + codep = insn_codep + 1; + oappend ("(bad)"); +} + +static void +REP_Fixup (int bytemode, int sizeflag) +{ + /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, + lods and stos. */ + if (prefixes & PREFIX_REPZ) + all_prefixes[last_repz_prefix] = REP_PREFIX; + + switch (bytemode) + { + case al_reg: + case eAX_reg: + case indir_dx_reg: + OP_IMREG (bytemode, sizeflag); + break; + case eDI_reg: + OP_ESreg (bytemode, sizeflag); + break; + case eSI_reg: + OP_DSreg (bytemode, sizeflag); + break; + default: + abort (); + break; + } +} + +static void +CMPXCHG8B_Fixup (int bytemode, int sizeflag) +{ + USED_REX (REX_W); + if (rex & REX_W) + { + /* Change cmpxchg8b to cmpxchg16b. */ + char *p = mnemonicendp - 2; + mnemonicendp = stpcpy (p, "16b"); + bytemode = o_mode; + } + OP_M (bytemode, sizeflag); +} + +static void +XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) +{ + const char **names; + + if (need_vex) + { + switch (vex.length) + { + case 128: + names = names_xmm; + break; + case 256: + names = names_ymm; + break; + default: + abort (); + } + } + else + names = names_xmm; + oappend (names[reg]); +} + +static void +CRC32_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "crc32". */ + char *p = mnemonicendp; + + switch (bytemode) + { + case b_mode: + if (intel_syntax) + goto skip; + + *p++ = 'b'; + break; + case v_mode: + if (intel_syntax) + goto skip; + + USED_REX (REX_W); + if (rex & REX_W) + *p++ = 'q'; + else + { + if (sizeflag & DFLAG) + *p++ = 'l'; + else + *p++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + mnemonicendp = p; + *p = '\0'; + +skip: + if (modrm.mod == 3) + { + int add; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + USED_REX (REX_B); + add = (rex & REX_B) ? 8 : 0; + if (bytemode == b_mode) + { + USED_REX (0); + if (rex) + oappend (names8rex[modrm.rm + add]); + else + oappend (names8[modrm.rm + add]); + } + else + { + USED_REX (REX_W); + if (rex & REX_W) + oappend (names64[modrm.rm + add]); + else if ((prefixes & PREFIX_DATA)) + oappend (names16[modrm.rm + add]); + else + oappend (names32[modrm.rm + add]); + } + } + else + OP_E (bytemode, sizeflag); +} + +static void +FXSAVE_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "fxsave" and "fxrstor". */ + USED_REX (REX_W); + if (rex & REX_W) + { + char *p = mnemonicendp; + *p++ = '6'; + *p++ = '4'; + *p = '\0'; + mnemonicendp = p; + } + OP_M (bytemode, sizeflag); +} + +/* Display the destination register operand for instructions with + VEX. */ + +static void +OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg; + const char **names; + + if (!need_vex) + abort (); + + if (!need_vex_reg) + return; + + reg = vex.register_specifier; + if (bytemode == vex_scalar_mode) + { + oappend (names_xmm[reg]); + return; + } + + switch (vex.length) + { + case 128: + switch (bytemode) + { + case vex_mode: + case vex128_mode: + names = names_xmm; + break; + case dq_mode: + if (vex.w) + names = names64; + else + names = names32; + break; + default: + abort (); + return; + } + break; + case 256: + switch (bytemode) + { + case vex_mode: + case vex256_mode: + break; + default: + abort (); + return; + } + + names = names_ymm; + break; + default: + abort (); + break; + } + oappend (names[reg]); +} + +/* Get the VEX immediate byte without moving codep. */ + +static unsigned char +get_vex_imm8 (int sizeflag, int opnum) +{ + int bytes_before_imm = 0; + + if (modrm.mod != 3) + { + /* There are SIB/displacement bytes. */ + if ((sizeflag & AFLAG) || address_mode == mode_64bit) + { + /* 32/64 bit address mode */ + int base = modrm.rm; + + /* Check SIB byte. */ + if (base == 4) + { + FETCH_DATA (the_info, codep + 1); + base = *codep & 7; + /* When decoding the third source, don't increase + bytes_before_imm as this has already been incremented + by one in OP_E_memory while decoding the second + source operand. */ + if (opnum == 0) + bytes_before_imm++; + } + + /* Don't increase bytes_before_imm when decoding the third source, + it has already been incremented by OP_E_memory while decoding + the second source operand. */ + if (opnum == 0) + { + switch (modrm.mod) + { + case 0: + /* When modrm.rm == 5 or modrm.rm == 4 and base in + SIB == 5, there is a 4 byte displacement. */ + if (base != 5) + /* No displacement. */ + break; + case 2: + /* 4 byte displacement. */ + bytes_before_imm += 4; + break; + case 1: + /* 1 byte displacement. */ + bytes_before_imm++; + break; + } + } + } + else + { + /* 16 bit address mode */ + /* Don't increase bytes_before_imm when decoding the third source, + it has already been incremented by OP_E_memory while decoding + the second source operand. */ + if (opnum == 0) + { + switch (modrm.mod) + { + case 0: + /* When modrm.rm == 6, there is a 2 byte displacement. */ + if (modrm.rm != 6) + /* No displacement. */ + break; + case 2: + /* 2 byte displacement. */ + bytes_before_imm += 2; + break; + case 1: + /* 1 byte displacement: when decoding the third source, + don't increase bytes_before_imm as this has already + been incremented by one in OP_E_memory while decoding + the second source operand. */ + if (opnum == 0) + bytes_before_imm++; + + break; + } + } + } + } + + FETCH_DATA (the_info, codep + bytes_before_imm + 1); + return codep [bytes_before_imm]; +} + +static void +OP_EX_VexReg (int bytemode, int sizeflag, int reg) +{ + const char **names; + + if (reg == -1 && modrm.mod != 3) + { + OP_E_memory (bytemode, sizeflag); + return; + } + else + { + if (reg == -1) + { + reg = modrm.rm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + } + else if (reg > 7 && address_mode != mode_64bit) + BadOp (); + } + + switch (vex.length) + { + case 128: + names = names_xmm; + break; + case 256: + names = names_ymm; + break; + default: + abort (); + } + oappend (names[reg]); +} + +static void +OP_EX_VexImmW (int bytemode, int sizeflag) +{ + int reg = -1; + static unsigned char vex_imm8; + + if (vex_w_done == 0) + { + vex_w_done = 1; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + vex_imm8 = get_vex_imm8 (sizeflag, 0); + + if (vex.w) + reg = vex_imm8 >> 4; + + OP_EX_VexReg (bytemode, sizeflag, reg); + } + else if (vex_w_done == 1) + { + vex_w_done = 2; + + if (!vex.w) + reg = vex_imm8 >> 4; + + OP_EX_VexReg (bytemode, sizeflag, reg); + } + else + { + /* Output the imm8 directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + codep++; + } +} + +static void +OP_Vex_2src (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + { + int reg = modrm.rm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + oappend (names_xmm[reg]); + } + else + { + if (intel_syntax + && (bytemode == v_mode || bytemode == v_swap_mode)) + { + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } + OP_E (bytemode, sizeflag); + } +} + +static void +OP_Vex_2src_1 (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + { + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + } + + if (vex.w) + oappend (names_xmm[vex.register_specifier]); + else + OP_Vex_2src (bytemode, sizeflag); +} + +static void +OP_Vex_2src_2 (int bytemode, int sizeflag) +{ + if (vex.w) + OP_Vex_2src (bytemode, sizeflag); + else + oappend (names_xmm[vex.register_specifier]); +} + +static void +OP_EX_VexW (int bytemode, int sizeflag) +{ + int reg = -1; + + if (!vex_w_done) + { + vex_w_done = 1; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (vex.w) + reg = get_vex_imm8 (sizeflag, 0) >> 4; + } + else + { + if (!vex.w) + reg = get_vex_imm8 (sizeflag, 1) >> 4; + } + + OP_EX_VexReg (bytemode, sizeflag, reg); +} + +static void +VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* Skip the immediate byte and check for invalid bits. */ + FETCH_DATA (the_info, codep + 1); + if (*codep++ & 0xf) + BadOp (); +} + +static void +OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg; + const char **names; + + FETCH_DATA (the_info, codep + 1); + reg = *codep++; + + if (bytemode != x_mode) + abort (); + + if (reg & 0xf) + BadOp (); + + reg >>= 4; + if (reg > 7 && address_mode != mode_64bit) + BadOp (); + + switch (vex.length) + { + case 128: + names = names_xmm; + break; + case 256: + names = names_ymm; + break; + default: + abort (); + } + oappend (names[reg]); +} + +static void +OP_XMM_VexW (int bytemode, int sizeflag) +{ + /* Turn off the REX.W bit since it is used for swapping operands + now. */ + rex &= ~REX_W; + OP_XMM (bytemode, sizeflag); +} + +static void +OP_EX_Vex (int bytemode, int sizeflag) +{ + if (modrm.mod != 3) + { + if (vex.register_specifier != 0) + BadOp (); + need_vex_reg = 0; + } + OP_EX (bytemode, sizeflag); +} + +static void +OP_XMM_Vex (int bytemode, int sizeflag) +{ + if (modrm.mod != 3) + { + if (vex.register_specifier != 0) + BadOp (); + need_vex_reg = 0; + } + OP_XMM (bytemode, sizeflag); +} + +static void +VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + switch (vex.length) + { + case 128: + mnemonicendp = stpcpy (obuf, "vzeroupper"); + break; + case 256: + mnemonicendp = stpcpy (obuf, "vzeroall"); + break; + default: + abort (); + } +} + +static struct op vex_cmp_op[] = +{ + { STRING_COMMA_LEN ("eq") }, + { STRING_COMMA_LEN ("lt") }, + { STRING_COMMA_LEN ("le") }, + { STRING_COMMA_LEN ("unord") }, + { STRING_COMMA_LEN ("neq") }, + { STRING_COMMA_LEN ("nlt") }, + { STRING_COMMA_LEN ("nle") }, + { STRING_COMMA_LEN ("ord") }, + { STRING_COMMA_LEN ("eq_uq") }, + { STRING_COMMA_LEN ("nge") }, + { STRING_COMMA_LEN ("ngt") }, + { STRING_COMMA_LEN ("false") }, + { STRING_COMMA_LEN ("neq_oq") }, + { STRING_COMMA_LEN ("ge") }, + { STRING_COMMA_LEN ("gt") }, + { STRING_COMMA_LEN ("true") }, + { STRING_COMMA_LEN ("eq_os") }, + { STRING_COMMA_LEN ("lt_oq") }, + { STRING_COMMA_LEN ("le_oq") }, + { STRING_COMMA_LEN ("unord_s") }, + { STRING_COMMA_LEN ("neq_us") }, + { STRING_COMMA_LEN ("nlt_uq") }, + { STRING_COMMA_LEN ("nle_uq") }, + { STRING_COMMA_LEN ("ord_s") }, + { STRING_COMMA_LEN ("eq_us") }, + { STRING_COMMA_LEN ("nge_uq") }, + { STRING_COMMA_LEN ("ngt_uq") }, + { STRING_COMMA_LEN ("false_os") }, + { STRING_COMMA_LEN ("neq_os") }, + { STRING_COMMA_LEN ("ge_oq") }, + { STRING_COMMA_LEN ("gt_oq") }, + { STRING_COMMA_LEN ("true_us") }, +}; + +static void +VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (vex_cmp_op)) + { + char suffix [3]; + char *p = mnemonicendp - 2; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); + mnemonicendp += vex_cmp_op[cmp_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} + +static const struct op pclmul_op[] = +{ + { STRING_COMMA_LEN ("lql") }, + { STRING_COMMA_LEN ("hql") }, + { STRING_COMMA_LEN ("lqh") }, + { STRING_COMMA_LEN ("hqh") } +}; + +static void +PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int pclmul_type; + + FETCH_DATA (the_info, codep + 1); + pclmul_type = *codep++ & 0xff; + switch (pclmul_type) + { + case 0x10: + pclmul_type = 2; + break; + case 0x11: + pclmul_type = 3; + break; + default: + break; + } + if (pclmul_type < ARRAY_SIZE (pclmul_op)) + { + char suffix [4]; + char *p = mnemonicendp - 3; + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = p[2]; + suffix[3] = '\0'; + sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); + mnemonicendp += pclmul_op[pclmul_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, pclmul_type); + oappend (scratchbuf + intel_syntax); + scratchbuf[0] = '\0'; + } +} + +static void +MOVBE_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "movbe". */ + char *p = mnemonicendp; + + switch (bytemode) + { + case v_mode: + if (intel_syntax) + goto skip; + + USED_REX (REX_W); + if (sizeflag & SUFFIX_ALWAYS) + { + if (rex & REX_W) + *p++ = 'q'; + else + { + if (sizeflag & DFLAG) + *p++ = 'l'; + else + *p++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + } + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + mnemonicendp = p; + *p = '\0'; + +skip: + OP_M (bytemode, sizeflag); +} + +static void +OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + int reg; + const char **names; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + if (vex.w) + names = names64; + else + names = names32; + + reg = modrm.rm; + USED_REX (REX_B); + if (rex & REX_B) + reg += 8; + + oappend (names[reg]); +} + +static void +OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + const char **names; + + if (vex.w) + names = names64; + else + names = names32; + + oappend (names[vex.register_specifier]); +} + diff --git a/external/gpl3/gdb/dist/opcodes/i386-gen.c b/external/gpl3/gdb/dist/opcodes/i386-gen.c new file mode 100644 index 000000000000..e791c6103799 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-gen.c @@ -0,0 +1,1257 @@ +/* Copyright 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#include +#include "getopt.h" +#include "libiberty.h" +#include "hashtab.h" +#include "safe-ctype.h" + +#include "i386-opc.h" + +#include +#define _(String) gettext (String) + +static const char *program_name = NULL; +static int debug = 0; + +typedef struct initializer +{ + const char *name; + const char *init; +} initializer; + +static initializer cpu_flag_init[] = +{ + { "CPU_UNKNOWN_FLAGS", + "~CpuL1OM" }, + { "CPU_GENERIC32_FLAGS", + "Cpu186|Cpu286|Cpu386" }, + { "CPU_GENERIC64_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuLM" }, + { "CPU_NONE_FLAGS", + "0" }, + { "CPU_I186_FLAGS", + "Cpu186" }, + { "CPU_I286_FLAGS", + "Cpu186|Cpu286" }, + { "CPU_I386_FLAGS", + "Cpu186|Cpu286|Cpu386" }, + { "CPU_I486_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486" }, + { "CPU_I586_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu387" }, + { "CPU_I686_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687" }, + { "CPU_PENTIUMPRO_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687|CpuNop" }, + { "CPU_P2_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687|CpuNop|CpuMMX" }, + { "CPU_P3_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE" }, + { "CPU_P4_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2" }, + { "CPU_NOCONA_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuLM" }, + { "CPU_CORE_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" }, + { "CPU_CORE2_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuLM" }, + { "CPU_COREI7_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuClflush|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuRdtscp|CpuLM" }, + { "CPU_K6_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuMMX" }, + { "CPU_K6_2_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuNop|CpuMMX|Cpu3dnow" }, + { "CPU_ATHLON_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|Cpu387|Cpu687|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA" }, + { "CPU_K8_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" }, + { "CPU_AMDFAM10_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" }, + { "CPU_BDVER1_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA4|CpuXOP|CpuLWP" }, + { "CPU_8087_FLAGS", + "Cpu8087" }, + { "CPU_287_FLAGS", + "Cpu287" }, + { "CPU_387_FLAGS", + "Cpu387" }, + { "CPU_ANY87_FLAGS", + "Cpu8087|Cpu287|Cpu387|Cpu687|CpuFISTTP" }, + { "CPU_CLFLUSH_FLAGS", + "CpuClflush" }, + { "CPU_NOP_FLAGS", + "CpuNop" }, + { "CPU_SYSCALL_FLAGS", + "CpuSYSCALL" }, + { "CPU_MMX_FLAGS", + "CpuMMX" }, + { "CPU_SSE_FLAGS", + "CpuMMX|CpuSSE" }, + { "CPU_SSE2_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2" }, + { "CPU_SSE3_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3" }, + { "CPU_SSSE3_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" }, + { "CPU_SSE4_1_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" }, + { "CPU_SSE4_2_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" }, + { "CPU_ANY_SSE_FLAGS", + "CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX" }, + { "CPU_VMX_FLAGS", + "CpuVMX" }, + { "CPU_SMX_FLAGS", + "CpuSMX" }, + { "CPU_XSAVE_FLAGS", + "CpuXsave" }, + { "CPU_XSAVEOPT_FLAGS", + "CpuXsaveopt" }, + { "CPU_AES_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" }, + { "CPU_PCLMUL_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" }, + { "CPU_FMA_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" }, + { "CPU_FMA4_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" }, + { "CPU_XOP_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" }, + { "CPU_LWP_FLAGS", + "CpuLWP" }, + { "CPU_BMI_FLAGS", + "CpuBMI" }, + { "CPU_TBM_FLAGS", + "CpuTBM" }, + { "CPU_MOVBE_FLAGS", + "CpuMovbe" }, + { "CPU_RDTSCP_FLAGS", + "CpuRdtscp" }, + { "CPU_EPT_FLAGS", + "CpuEPT" }, + { "CPU_FSGSBASE_FLAGS", + "CpuFSGSBase" }, + { "CPU_RDRND_FLAGS", + "CpuRdRnd" }, + { "CPU_F16C_FLAGS", + "CpuF16C" }, + { "CPU_3DNOW_FLAGS", + "CpuMMX|Cpu3dnow" }, + { "CPU_3DNOWA_FLAGS", + "CpuMMX|Cpu3dnow|Cpu3dnowA" }, + { "CPU_PADLOCK_FLAGS", + "CpuPadLock" }, + { "CPU_SVME_FLAGS", + "CpuSVME" }, + { "CPU_SSE4A_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" }, + { "CPU_ABM_FLAGS", + "CpuABM" }, + { "CPU_AVX_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" }, + { "CPU_ANY_AVX_FLAGS", + "CpuAVX" }, + { "CPU_L1OM_FLAGS", + "unknown" }, +}; + +static initializer operand_type_init[] = +{ + { "OPERAND_TYPE_NONE", + "0" }, + { "OPERAND_TYPE_REG8", + "Reg8" }, + { "OPERAND_TYPE_REG16", + "Reg16" }, + { "OPERAND_TYPE_REG32", + "Reg32" }, + { "OPERAND_TYPE_REG64", + "Reg64" }, + { "OPERAND_TYPE_IMM1", + "Imm1" }, + { "OPERAND_TYPE_IMM8", + "Imm8" }, + { "OPERAND_TYPE_IMM8S", + "Imm8S" }, + { "OPERAND_TYPE_IMM16", + "Imm16" }, + { "OPERAND_TYPE_IMM32", + "Imm32" }, + { "OPERAND_TYPE_IMM32S", + "Imm32S" }, + { "OPERAND_TYPE_IMM64", + "Imm64" }, + { "OPERAND_TYPE_BASEINDEX", + "BaseIndex" }, + { "OPERAND_TYPE_DISP8", + "Disp8" }, + { "OPERAND_TYPE_DISP16", + "Disp16" }, + { "OPERAND_TYPE_DISP32", + "Disp32" }, + { "OPERAND_TYPE_DISP32S", + "Disp32S" }, + { "OPERAND_TYPE_DISP64", + "Disp64" }, + { "OPERAND_TYPE_INOUTPORTREG", + "InOutPortReg" }, + { "OPERAND_TYPE_SHIFTCOUNT", + "ShiftCount" }, + { "OPERAND_TYPE_CONTROL", + "Control" }, + { "OPERAND_TYPE_TEST", + "Test" }, + { "OPERAND_TYPE_DEBUG", + "FloatReg" }, + { "OPERAND_TYPE_FLOATREG", + "FloatReg" }, + { "OPERAND_TYPE_FLOATACC", + "FloatAcc" }, + { "OPERAND_TYPE_SREG2", + "SReg2" }, + { "OPERAND_TYPE_SREG3", + "SReg3" }, + { "OPERAND_TYPE_ACC", + "Acc" }, + { "OPERAND_TYPE_JUMPABSOLUTE", + "JumpAbsolute" }, + { "OPERAND_TYPE_REGMMX", + "RegMMX" }, + { "OPERAND_TYPE_REGXMM", + "RegXMM" }, + { "OPERAND_TYPE_REGYMM", + "RegYMM" }, + { "OPERAND_TYPE_ESSEG", + "EsSeg" }, + { "OPERAND_TYPE_ACC32", + "Reg32|Acc|Dword" }, + { "OPERAND_TYPE_ACC64", + "Reg64|Acc|Qword" }, + { "OPERAND_TYPE_INOUTPORTREG", + "InOutPortReg" }, + { "OPERAND_TYPE_REG16_INOUTPORTREG", + "Reg16|InOutPortReg" }, + { "OPERAND_TYPE_DISP16_32", + "Disp16|Disp32" }, + { "OPERAND_TYPE_ANYDISP", + "Disp8|Disp16|Disp32|Disp32S|Disp64" }, + { "OPERAND_TYPE_IMM16_32", + "Imm16|Imm32" }, + { "OPERAND_TYPE_IMM16_32S", + "Imm16|Imm32S" }, + { "OPERAND_TYPE_IMM16_32_32S", + "Imm16|Imm32|Imm32S" }, + { "OPERAND_TYPE_IMM32_32S_DISP32", + "Imm32|Imm32S|Disp32" }, + { "OPERAND_TYPE_IMM64_DISP64", + "Imm64|Disp64" }, + { "OPERAND_TYPE_IMM32_32S_64_DISP32", + "Imm32|Imm32S|Imm64|Disp32" }, + { "OPERAND_TYPE_IMM32_32S_64_DISP32_64", + "Imm32|Imm32S|Imm64|Disp32|Disp64" }, + { "OPERAND_TYPE_VEC_IMM4", + "Vec_Imm4" }, +}; + +typedef struct bitfield +{ + int position; + int value; + const char *name; +} bitfield; + +#define BITFIELD(n) { n, 0, #n } + +static bitfield cpu_flags[] = +{ + BITFIELD (Cpu186), + BITFIELD (Cpu286), + BITFIELD (Cpu386), + BITFIELD (Cpu486), + BITFIELD (Cpu586), + BITFIELD (Cpu686), + BITFIELD (CpuClflush), + BITFIELD (CpuNop), + BITFIELD (CpuSYSCALL), + BITFIELD (Cpu8087), + BITFIELD (Cpu287), + BITFIELD (Cpu387), + BITFIELD (Cpu687), + BITFIELD (CpuFISTTP), + BITFIELD (CpuMMX), + BITFIELD (CpuSSE), + BITFIELD (CpuSSE2), + BITFIELD (CpuSSE3), + BITFIELD (CpuSSSE3), + BITFIELD (CpuSSE4_1), + BITFIELD (CpuSSE4_2), + BITFIELD (CpuAVX), + BITFIELD (CpuL1OM), + BITFIELD (CpuSSE4a), + BITFIELD (Cpu3dnow), + BITFIELD (Cpu3dnowA), + BITFIELD (CpuPadLock), + BITFIELD (CpuSVME), + BITFIELD (CpuVMX), + BITFIELD (CpuSMX), + BITFIELD (CpuABM), + BITFIELD (CpuXsave), + BITFIELD (CpuXsaveopt), + BITFIELD (CpuAES), + BITFIELD (CpuPCLMUL), + BITFIELD (CpuFMA), + BITFIELD (CpuFMA4), + BITFIELD (CpuXOP), + BITFIELD (CpuLWP), + BITFIELD (CpuBMI), + BITFIELD (CpuTBM), + BITFIELD (CpuLM), + BITFIELD (CpuMovbe), + BITFIELD (CpuEPT), + BITFIELD (CpuRdtscp), + BITFIELD (CpuFSGSBase), + BITFIELD (CpuRdRnd), + BITFIELD (CpuF16C), + BITFIELD (Cpu64), + BITFIELD (CpuNo64), +#ifdef CpuUnused + BITFIELD (CpuUnused), +#endif +}; + +static bitfield opcode_modifiers[] = +{ + BITFIELD (D), + BITFIELD (W), + BITFIELD (S), + BITFIELD (Modrm), + BITFIELD (ShortForm), + BITFIELD (Jump), + BITFIELD (JumpDword), + BITFIELD (JumpByte), + BITFIELD (JumpInterSegment), + BITFIELD (FloatMF), + BITFIELD (FloatR), + BITFIELD (FloatD), + BITFIELD (Size16), + BITFIELD (Size32), + BITFIELD (Size64), + BITFIELD (CheckRegSize), + BITFIELD (IgnoreSize), + BITFIELD (DefaultSize), + BITFIELD (No_bSuf), + BITFIELD (No_wSuf), + BITFIELD (No_lSuf), + BITFIELD (No_sSuf), + BITFIELD (No_qSuf), + BITFIELD (No_ldSuf), + BITFIELD (FWait), + BITFIELD (IsString), + BITFIELD (IsLockable), + BITFIELD (RegKludge), + BITFIELD (FirstXmm0), + BITFIELD (Implicit1stXmm0), + BITFIELD (ToDword), + BITFIELD (ToQword), + BITFIELD (AddrPrefixOp0), + BITFIELD (IsPrefix), + BITFIELD (ImmExt), + BITFIELD (NoRex64), + BITFIELD (Rex64), + BITFIELD (Ugh), + BITFIELD (Vex), + BITFIELD (VexVVVV), + BITFIELD (VexW), + BITFIELD (VexOpcode), + BITFIELD (VexSources), + BITFIELD (VexImmExt), + BITFIELD (SSE2AVX), + BITFIELD (NoAVX), + BITFIELD (OldGcc), + BITFIELD (ATTMnemonic), + BITFIELD (ATTSyntax), + BITFIELD (IntelSyntax), +}; + +static bitfield operand_types[] = +{ + BITFIELD (Reg8), + BITFIELD (Reg16), + BITFIELD (Reg32), + BITFIELD (Reg64), + BITFIELD (FloatReg), + BITFIELD (RegMMX), + BITFIELD (RegXMM), + BITFIELD (RegYMM), + BITFIELD (Imm1), + BITFIELD (Imm8), + BITFIELD (Imm8S), + BITFIELD (Imm16), + BITFIELD (Imm32), + BITFIELD (Imm32S), + BITFIELD (Imm64), + BITFIELD (BaseIndex), + BITFIELD (Disp8), + BITFIELD (Disp16), + BITFIELD (Disp32), + BITFIELD (Disp32S), + BITFIELD (Disp64), + BITFIELD (InOutPortReg), + BITFIELD (ShiftCount), + BITFIELD (Control), + BITFIELD (Debug), + BITFIELD (Test), + BITFIELD (SReg2), + BITFIELD (SReg3), + BITFIELD (Acc), + BITFIELD (FloatAcc), + BITFIELD (JumpAbsolute), + BITFIELD (EsSeg), + BITFIELD (RegMem), + BITFIELD (Mem), + BITFIELD (Byte), + BITFIELD (Word), + BITFIELD (Dword), + BITFIELD (Fword), + BITFIELD (Qword), + BITFIELD (Tbyte), + BITFIELD (Xmmword), + BITFIELD (Ymmword), + BITFIELD (Unspecified), + BITFIELD (Anysize), + BITFIELD (Vec_Imm4), +#ifdef OTUnused + BITFIELD (OTUnused), +#endif +}; + +static const char *filename; + +static int +compare (const void *x, const void *y) +{ + const bitfield *xp = (const bitfield *) x; + const bitfield *yp = (const bitfield *) y; + return xp->position - yp->position; +} + +static void +fail (const char *message, ...) +{ + va_list args; + + va_start (args, message); + fprintf (stderr, _("%s: Error: "), program_name); + vfprintf (stderr, message, args); + va_end (args); + xexit (1); +} + +static void +process_copyright (FILE *fp) +{ + fprintf (fp, "/* This file is automatically generated by i386-gen. Do not edit! */\n\ +/* Copyright 2007, 2008, 2009, 2010, 2011\n\ + Free Software Foundation, Inc.\n\ +\n\ + This file is part of the GNU opcodes library.\n\ +\n\ + This library is free software; you can redistribute it and/or modify\n\ + it under the terms of the GNU General Public License as published by\n\ + the Free Software Foundation; either version 3, or (at your option)\n\ + any later version.\n\ +\n\ + It is distributed in the hope that it will be useful, but WITHOUT\n\ + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\ + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\ + License for more details.\n\ +\n\ + You should have received a copy of the GNU General Public License\n\ + along with this program; if not, write to the Free Software\n\ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,\n\ + MA 02110-1301, USA. */\n"); +} + +/* Remove leading white spaces. */ + +static char * +remove_leading_whitespaces (char *str) +{ + while (ISSPACE (*str)) + str++; + return str; +} + +/* Remove trailing white spaces. */ + +static void +remove_trailing_whitespaces (char *str) +{ + size_t last = strlen (str); + + if (last == 0) + return; + + do + { + last--; + if (ISSPACE (str [last])) + str[last] = '\0'; + else + break; + } + while (last != 0); +} + +/* Find next field separated by SEP and terminate it. Return a + pointer to the one after it. */ + +static char * +next_field (char *str, char sep, char **next, char *last) +{ + char *p; + + p = remove_leading_whitespaces (str); + for (str = p; *str != sep && *str != '\0'; str++); + + *str = '\0'; + remove_trailing_whitespaces (p); + + *next = str + 1; + + if (p >= last) + abort (); + + return p; +} + +static void +set_bitfield (const char *f, bitfield *array, int value, + unsigned int size, int lineno) +{ + unsigned int i; + + if (strcmp (f, "CpuFP") == 0) + { + set_bitfield("Cpu387", array, value, size, lineno); + set_bitfield("Cpu287", array, value, size, lineno); + f = "Cpu8087"; + } + else if (strcmp (f, "Mmword") == 0) + f= "Qword"; + else if (strcmp (f, "Oword") == 0) + f= "Xmmword"; + + for (i = 0; i < size; i++) + if (strcasecmp (array[i].name, f) == 0) + { + array[i].value = value; + return; + } + + if (value) + { + const char *v = strchr (f, '='); + + if (v) + { + size_t n = v - f; + char *end; + + for (i = 0; i < size; i++) + if (strncasecmp (array[i].name, f, n) == 0) + { + value = strtol (v + 1, &end, 0); + if (*end == '\0') + { + array[i].value = value; + return; + } + break; + } + } + } + + if (lineno != -1) + fail (_("%s: %d: Unknown bitfield: %s\n"), filename, lineno, f); + else + fail (_("Unknown bitfield: %s\n"), f); +} + +static void +output_cpu_flags (FILE *table, bitfield *flags, unsigned int size, + int macro, const char *comma, const char *indent) +{ + unsigned int i; + + fprintf (table, "%s{ { ", indent); + + for (i = 0; i < size - 1; i++) + { + fprintf (table, "%d, ", flags[i].value); + if (((i + 1) % 20) == 0) + { + /* We need \\ for macro. */ + if (macro) + fprintf (table, " \\\n %s", indent); + else + fprintf (table, "\n %s", indent); + } + } + + fprintf (table, "%d } }%s\n", flags[i].value, comma); +} + +static void +process_i386_cpu_flag (FILE *table, char *flag, int macro, + const char *comma, const char *indent, + int lineno) +{ + char *str, *next, *last; + unsigned int i; + bitfield flags [ARRAY_SIZE (cpu_flags)]; + + /* Copy the default cpu flags. */ + memcpy (flags, cpu_flags, sizeof (cpu_flags)); + + if (strcasecmp (flag, "unknown") == 0) + { + /* We turn on everything except for cpu64 in case of + CPU_UNKNOWN_FLAGS. */ + for (i = 0; i < ARRAY_SIZE (flags); i++) + if (flags[i].position != Cpu64) + flags[i].value = 1; + } + else if (flag[0] == '~') + { + last = flag + strlen (flag); + + if (flag[1] == '(') + { + last -= 1; + next = flag + 2; + if (*last != ')') + fail (_("%s: %d: Missing `)' in bitfield: %s\n"), filename, + lineno, flag); + *last = '\0'; + } + else + next = flag + 1; + + /* First we turn on everything except for cpu64. */ + for (i = 0; i < ARRAY_SIZE (flags); i++) + if (flags[i].position != Cpu64) + flags[i].value = 1; + + /* Turn off selective bits. */ + for (; next && next < last; ) + { + str = next_field (next, '|', &next, last); + if (str) + set_bitfield (str, flags, 0, ARRAY_SIZE (flags), lineno); + } + } + else if (strcmp (flag, "0")) + { + /* Turn on selective bits. */ + last = flag + strlen (flag); + for (next = flag; next && next < last; ) + { + str = next_field (next, '|', &next, last); + if (str) + set_bitfield (str, flags, 1, ARRAY_SIZE (flags), lineno); + } + } + + output_cpu_flags (table, flags, ARRAY_SIZE (flags), macro, + comma, indent); +} + +static void +output_opcode_modifier (FILE *table, bitfield *modifier, unsigned int size) +{ + unsigned int i; + + fprintf (table, " { "); + + for (i = 0; i < size - 1; i++) + { + fprintf (table, "%d, ", modifier[i].value); + if (((i + 1) % 20) == 0) + fprintf (table, "\n "); + } + + fprintf (table, "%d },\n", modifier[i].value); +} + +static void +process_i386_opcode_modifier (FILE *table, char *mod, int lineno) +{ + char *str, *next, *last; + bitfield modifiers [ARRAY_SIZE (opcode_modifiers)]; + + /* Copy the default opcode modifier. */ + memcpy (modifiers, opcode_modifiers, sizeof (modifiers)); + + if (strcmp (mod, "0")) + { + last = mod + strlen (mod); + for (next = mod; next && next < last; ) + { + str = next_field (next, '|', &next, last); + if (str) + set_bitfield (str, modifiers, 1, ARRAY_SIZE (modifiers), + lineno); + } + } + output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers)); +} + +static void +output_operand_type (FILE *table, bitfield *types, unsigned int size, + int macro, const char *indent) +{ + unsigned int i; + + fprintf (table, "{ { "); + + for (i = 0; i < size - 1; i++) + { + fprintf (table, "%d, ", types[i].value); + if (((i + 1) % 20) == 0) + { + /* We need \\ for macro. */ + if (macro) + fprintf (table, "\\\n%s", indent); + else + fprintf (table, "\n%s", indent); + } + } + + fprintf (table, "%d } }", types[i].value); +} + +static void +process_i386_operand_type (FILE *table, char *op, int macro, + const char *indent, int lineno) +{ + char *str, *next, *last; + bitfield types [ARRAY_SIZE (operand_types)]; + + /* Copy the default operand type. */ + memcpy (types, operand_types, sizeof (types)); + + if (strcmp (op, "0")) + { + last = op + strlen (op); + for (next = op; next && next < last; ) + { + str = next_field (next, '|', &next, last); + if (str) + set_bitfield (str, types, 1, ARRAY_SIZE (types), lineno); + } + } + output_operand_type (table, types, ARRAY_SIZE (types), macro, + indent); +} + +static void +output_i386_opcode (FILE *table, const char *name, char *str, + char *last, int lineno) +{ + unsigned int i; + char *operands, *base_opcode, *extension_opcode, *opcode_length; + char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS]; + + /* Find number of operands. */ + operands = next_field (str, ',', &str, last); + + /* Find base_opcode. */ + base_opcode = next_field (str, ',', &str, last); + + /* Find extension_opcode. */ + extension_opcode = next_field (str, ',', &str, last); + + /* Find opcode_length. */ + opcode_length = next_field (str, ',', &str, last); + + /* Find cpu_flags. */ + cpu_flags = next_field (str, ',', &str, last); + + /* Find opcode_modifier. */ + opcode_modifier = next_field (str, ',', &str, last); + + /* Remove the first {. */ + str = remove_leading_whitespaces (str); + if (*str != '{') + abort (); + str = remove_leading_whitespaces (str + 1); + + i = strlen (str); + + /* There are at least "X}". */ + if (i < 2) + abort (); + + /* Remove trailing white spaces and }. */ + do + { + i--; + if (ISSPACE (str[i]) || str[i] == '}') + str[i] = '\0'; + else + break; + } + while (i != 0); + + last = str + i; + + /* Find operand_types. */ + for (i = 0; i < ARRAY_SIZE (operand_types); i++) + { + if (str >= last) + { + operand_types [i] = NULL; + break; + } + + operand_types [i] = next_field (str, ',', &str, last); + if (*operand_types[i] == '0') + { + if (i != 0) + operand_types[i] = NULL; + break; + } + } + + fprintf (table, " { \"%s\", %s, %s, %s, %s,\n", + name, operands, base_opcode, extension_opcode, + opcode_length); + + process_i386_cpu_flag (table, cpu_flags, 0, ",", " ", lineno); + + process_i386_opcode_modifier (table, opcode_modifier, lineno); + + fprintf (table, " { "); + + for (i = 0; i < ARRAY_SIZE (operand_types); i++) + { + if (operand_types[i] == NULL || *operand_types[i] == '0') + { + if (i == 0) + process_i386_operand_type (table, "0", 0, "\t ", lineno); + break; + } + + if (i != 0) + fprintf (table, ",\n "); + + process_i386_operand_type (table, operand_types[i], 0, + "\t ", lineno); + } + fprintf (table, " } },\n"); +} + +struct opcode_hash_entry +{ + struct opcode_hash_entry *next; + char *name; + char *opcode; + int lineno; +}; + +/* Calculate the hash value of an opcode hash entry P. */ + +static hashval_t +opcode_hash_hash (const void *p) +{ + struct opcode_hash_entry *entry = (struct opcode_hash_entry *) p; + return htab_hash_string (entry->name); +} + +/* Compare a string Q against an opcode hash entry P. */ + +static int +opcode_hash_eq (const void *p, const void *q) +{ + struct opcode_hash_entry *entry = (struct opcode_hash_entry *) p; + const char *name = (const char *) q; + return strcmp (name, entry->name) == 0; +} + +static void +process_i386_opcodes (FILE *table) +{ + FILE *fp; + char buf[2048]; + unsigned int i, j; + char *str, *p, *last, *name; + struct opcode_hash_entry **hash_slot, **entry, *next; + htab_t opcode_hash_table; + struct opcode_hash_entry **opcode_array; + unsigned int opcode_array_size = 1024; + int lineno = 0; + + filename = "i386-opc.tbl"; + fp = fopen (filename, "r"); + + if (fp == NULL) + fail (_("can't find i386-opc.tbl for reading, errno = %s\n"), + xstrerror (errno)); + + i = 0; + opcode_array = (struct opcode_hash_entry **) + xmalloc (sizeof (*opcode_array) * opcode_array_size); + + opcode_hash_table = htab_create_alloc (16, opcode_hash_hash, + opcode_hash_eq, NULL, + xcalloc, free); + + fprintf (table, "\n/* i386 opcode table. */\n\n"); + fprintf (table, "const insn_template i386_optab[] =\n{\n"); + + /* Put everything on opcode array. */ + while (!feof (fp)) + { + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + lineno++; + + p = remove_leading_whitespaces (buf); + + /* Skip comments. */ + str = strstr (p, "//"); + if (str != NULL) + str[0] = '\0'; + + /* Remove trailing white spaces. */ + remove_trailing_whitespaces (p); + + switch (p[0]) + { + case '#': + /* Ignore comments. */ + case '\0': + continue; + break; + default: + break; + } + + last = p + strlen (p); + + /* Find name. */ + name = next_field (p, ',', &str, last); + + /* Get the slot in hash table. */ + hash_slot = (struct opcode_hash_entry **) + htab_find_slot_with_hash (opcode_hash_table, name, + htab_hash_string (name), + INSERT); + + if (*hash_slot == NULL) + { + /* It is the new one. Put it on opcode array. */ + if (i >= opcode_array_size) + { + /* Grow the opcode array when needed. */ + opcode_array_size += 1024; + opcode_array = (struct opcode_hash_entry **) + xrealloc (opcode_array, + sizeof (*opcode_array) * opcode_array_size); + } + + opcode_array[i] = (struct opcode_hash_entry *) + xmalloc (sizeof (struct opcode_hash_entry)); + opcode_array[i]->next = NULL; + opcode_array[i]->name = xstrdup (name); + opcode_array[i]->opcode = xstrdup (str); + opcode_array[i]->lineno = lineno; + *hash_slot = opcode_array[i]; + i++; + } + else + { + /* Append it to the existing one. */ + entry = hash_slot; + while ((*entry) != NULL) + entry = &(*entry)->next; + *entry = (struct opcode_hash_entry *) + xmalloc (sizeof (struct opcode_hash_entry)); + (*entry)->next = NULL; + (*entry)->name = (*hash_slot)->name; + (*entry)->opcode = xstrdup (str); + (*entry)->lineno = lineno; + } + } + + /* Process opcode array. */ + for (j = 0; j < i; j++) + { + for (next = opcode_array[j]; next; next = next->next) + { + name = next->name; + str = next->opcode; + lineno = next->lineno; + last = str + strlen (str); + output_i386_opcode (table, name, str, last, lineno); + } + } + + fclose (fp); + + fprintf (table, " { NULL, 0, 0, 0, 0,\n"); + + process_i386_cpu_flag (table, "0", 0, ",", " ", -1); + + process_i386_opcode_modifier (table, "0", -1); + + fprintf (table, " { "); + process_i386_operand_type (table, "0", 0, "\t ", -1); + fprintf (table, " } }\n"); + + fprintf (table, "};\n"); +} + +static void +process_i386_registers (FILE *table) +{ + FILE *fp; + char buf[2048]; + char *str, *p, *last; + char *reg_name, *reg_type, *reg_flags, *reg_num; + char *dw2_32_num, *dw2_64_num; + int lineno = 0; + + filename = "i386-reg.tbl"; + fp = fopen (filename, "r"); + if (fp == NULL) + fail (_("can't find i386-reg.tbl for reading, errno = %s\n"), + xstrerror (errno)); + + fprintf (table, "\n/* i386 register table. */\n\n"); + fprintf (table, "const reg_entry i386_regtab[] =\n{\n"); + + while (!feof (fp)) + { + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + lineno++; + + p = remove_leading_whitespaces (buf); + + /* Skip comments. */ + str = strstr (p, "//"); + if (str != NULL) + str[0] = '\0'; + + /* Remove trailing white spaces. */ + remove_trailing_whitespaces (p); + + switch (p[0]) + { + case '#': + fprintf (table, "%s\n", p); + case '\0': + continue; + break; + default: + break; + } + + last = p + strlen (p); + + /* Find reg_name. */ + reg_name = next_field (p, ',', &str, last); + + /* Find reg_type. */ + reg_type = next_field (str, ',', &str, last); + + /* Find reg_flags. */ + reg_flags = next_field (str, ',', &str, last); + + /* Find reg_num. */ + reg_num = next_field (str, ',', &str, last); + + fprintf (table, " { \"%s\",\n ", reg_name); + + process_i386_operand_type (table, reg_type, 0, "\t", lineno); + + /* Find 32-bit Dwarf2 register number. */ + dw2_32_num = next_field (str, ',', &str, last); + + /* Find 64-bit Dwarf2 register number. */ + dw2_64_num = next_field (str, ',', &str, last); + + fprintf (table, ",\n %s, %s, { %s, %s } },\n", + reg_flags, reg_num, dw2_32_num, dw2_64_num); + } + + fclose (fp); + + fprintf (table, "};\n"); + + fprintf (table, "\nconst unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n"); +} + +static void +process_i386_initializers (void) +{ + unsigned int i; + FILE *fp = fopen ("i386-init.h", "w"); + char *init; + + if (fp == NULL) + fail (_("can't create i386-init.h, errno = %s\n"), + xstrerror (errno)); + + process_copyright (fp); + + for (i = 0; i < ARRAY_SIZE (cpu_flag_init); i++) + { + fprintf (fp, "\n#define %s \\\n", cpu_flag_init[i].name); + init = xstrdup (cpu_flag_init[i].init); + process_i386_cpu_flag (fp, init, 1, "", " ", -1); + free (init); + } + + for (i = 0; i < ARRAY_SIZE (operand_type_init); i++) + { + fprintf (fp, "\n\n#define %s \\\n ", operand_type_init[i].name); + init = xstrdup (operand_type_init[i].init); + process_i386_operand_type (fp, init, 1, " ", -1); + free (init); + } + fprintf (fp, "\n"); + + fclose (fp); +} + +/* Program options. */ +#define OPTION_SRCDIR 200 + +struct option long_options[] = +{ + {"srcdir", required_argument, NULL, OPTION_SRCDIR}, + {"debug", no_argument, NULL, 'd'}, + {"version", no_argument, NULL, 'V'}, + {"help", no_argument, NULL, 'h'}, + {0, no_argument, NULL, 0} +}; + +static void +print_version (void) +{ + printf ("%s: version 1.0\n", program_name); + xexit (0); +} + +static void +usage (FILE * stream, int status) +{ + fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", + program_name); + xexit (status); +} + +int +main (int argc, char **argv) +{ + extern int chdir (char *); + char *srcdir = NULL; + int c; + FILE *table; + + program_name = *argv; + xmalloc_set_program_name (program_name); + + while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) + switch (c) + { + case OPTION_SRCDIR: + srcdir = optarg; + break; + case 'V': + case 'v': + print_version (); + break; + case 'd': + debug = 1; + break; + case 'h': + case '?': + usage (stderr, 0); + default: + case 0: + break; + } + + if (optind != argc) + usage (stdout, 1); + + if (srcdir != NULL) + if (chdir (srcdir) != 0) + fail (_("unable to change directory to \"%s\", errno = %s\n"), + srcdir, xstrerror (errno)); + + /* Check the unused bitfield in i386_cpu_flags. */ +#ifndef CpuUnused + c = CpuNumOfBits - CpuMax - 1; + if (c) + fail (_("%d unused bits in i386_cpu_flags.\n"), c); +#endif + + /* Check the unused bitfield in i386_operand_type. */ +#ifndef OTUnused + c = OTNumOfBits - OTMax - 1; + if (c) + fail (_("%d unused bits in i386_operand_type.\n"), c); +#endif + + qsort (cpu_flags, ARRAY_SIZE (cpu_flags), sizeof (cpu_flags [0]), + compare); + + qsort (opcode_modifiers, ARRAY_SIZE (opcode_modifiers), + sizeof (opcode_modifiers [0]), compare); + + qsort (operand_types, ARRAY_SIZE (operand_types), + sizeof (operand_types [0]), compare); + + table = fopen ("i386-tbl.h", "w"); + if (table == NULL) + fail (_("can't create i386-tbl.h, errno = %s\n"), + xstrerror (errno)); + + process_copyright (table); + + process_i386_opcodes (table); + process_i386_registers (table); + process_i386_initializers (); + + fclose (table); + + exit (0); +} diff --git a/external/gpl3/gdb/dist/opcodes/i386-init.h b/external/gpl3/gdb/dist/opcodes/i386-init.h new file mode 100644 index 000000000000..6a57b2940985 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-init.h @@ -0,0 +1,586 @@ +/* This file is automatically generated by i386-gen. Do not edit! */ +/* Copyright 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define CPU_UNKNOWN_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } } + +#define CPU_GENERIC32_FLAGS \ + { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_GENERIC64_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_NONE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I186_FLAGS \ + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I286_FLAGS \ + { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I386_FLAGS \ + { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I486_FLAGS \ + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I586_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_I686_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_PENTIUMPRO_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_P2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_P3_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_P4_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_NOCONA_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_CORE_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_CORE2_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_COREI7_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_K6_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_K6_2_FLAGS \ + { { 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ATHLON_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_K8_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_AMDFAM10_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_BDVER1_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \ + 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0 } } + +#define CPU_8087_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_287_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_387_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY87_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_CLFLUSH_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_NOP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SYSCALL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_MMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSSE3_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE4_1_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE4_2_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_SSE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_VMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_XSAVE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_XSAVEOPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AES_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_PCLMUL_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_FMA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_FMA4_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_XOP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_LWP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_BMI_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_TBM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_MOVBE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_RDTSCP_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_EPT_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_FSGSBASE_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } + +#define CPU_RDRND_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } + +#define CPU_F16C_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } + +#define CPU_3DNOW_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_3DNOWA_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_PADLOCK_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SVME_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SSE4A_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ABM_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_ANY_AVX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_L1OM_FLAGS \ + { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } } + + +#define OPERAND_TYPE_NONE \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REG8 \ + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REG16 \ + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REG32 \ + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REG64 \ + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM1 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM8 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM8S \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM16 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM32S \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM64 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_BASEINDEX \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP8 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP16 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP32S \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP64 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_INOUTPORTREG \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_SHIFTCOUNT \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_CONTROL \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_TEST \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DEBUG \ + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_FLOATREG \ + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_FLOATACC \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_SREG2 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_SREG3 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_ACC \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_JUMPABSOLUTE \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REGMMX \ + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REGXMM \ + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REGYMM \ + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_ESSEG \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_ACC32 \ + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_ACC64 \ + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_INOUTPORTREG \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_REG16_INOUTPORTREG \ + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_DISP16_32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_ANYDISP \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM16_32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM16_32S \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM16_32_32S \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM32_32S_DISP32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM64_DISP64 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM32_32S_64_DISP32 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ + 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 } } + +#define OPERAND_TYPE_VEC_IMM4 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 1, 0 } } diff --git a/external/gpl3/gdb/dist/opcodes/i386-opc.c b/external/gpl3/gdb/dist/opcodes/i386-opc.c new file mode 100644 index 000000000000..1e97566c3f4c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-opc.c @@ -0,0 +1,33 @@ +/* Intel 80386 opcode table + Copyright 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "libiberty.h" +#include "i386-opc.h" +#include "i386-tbl.h" + +/* Segment stuff. */ +const seg_entry cs = { "cs", 0x2e }; +const seg_entry ds = { "ds", 0x3e }; +const seg_entry ss = { "ss", 0x36 }; +const seg_entry es = { "es", 0x26 }; +const seg_entry fs = { "fs", 0x64 }; +const seg_entry gs = { "gs", 0x65 }; diff --git a/external/gpl3/gdb/dist/opcodes/i386-opc.h b/external/gpl3/gdb/dist/opcodes/i386-opc.h new file mode 100644 index 000000000000..f90dff59d442 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-opc.h @@ -0,0 +1,686 @@ +/* Declarations for Intel 80386 opcode table + Copyright 2007, 2008, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "opcode/i386.h" +#ifdef HAVE_LIMITS_H +#include +#endif + +#ifndef CHAR_BIT +#define CHAR_BIT 8 +#endif + +/* Position of cpu flags bitfiled. */ + +enum +{ + /* i186 or better required */ + Cpu186 = 0, + /* i286 or better required */ + Cpu286, + /* i386 or better required */ + Cpu386, + /* i486 or better required */ + Cpu486, + /* i585 or better required */ + Cpu586, + /* i686 or better required */ + Cpu686, + /* CLFLUSH Instruction support required */ + CpuClflush, + /* NOP Instruction support required */ + CpuNop, + /* SYSCALL Instructions support required */ + CpuSYSCALL, + /* Floating point support required */ + Cpu8087, + /* i287 support required */ + Cpu287, + /* i387 support required */ + Cpu387, + /* i686 and floating point support required */ + Cpu687, + /* SSE3 and floating point support required */ + CpuFISTTP, + /* MMX support required */ + CpuMMX, + /* SSE support required */ + CpuSSE, + /* SSE2 support required */ + CpuSSE2, + /* 3dnow! support required */ + Cpu3dnow, + /* 3dnow! Extensions support required */ + Cpu3dnowA, + /* SSE3 support required */ + CpuSSE3, + /* VIA PadLock required */ + CpuPadLock, + /* AMD Secure Virtual Machine Ext-s required */ + CpuSVME, + /* VMX Instructions required */ + CpuVMX, + /* SMX Instructions required */ + CpuSMX, + /* SSSE3 support required */ + CpuSSSE3, + /* SSE4a support required */ + CpuSSE4a, + /* ABM New Instructions required */ + CpuABM, + /* SSE4.1 support required */ + CpuSSE4_1, + /* SSE4.2 support required */ + CpuSSE4_2, + /* AVX support required */ + CpuAVX, + /* Intel L1OM support required */ + CpuL1OM, + /* Xsave/xrstor New Instructions support required */ + CpuXsave, + /* Xsaveopt New Instructions support required */ + CpuXsaveopt, + /* AES support required */ + CpuAES, + /* PCLMUL support required */ + CpuPCLMUL, + /* FMA support required */ + CpuFMA, + /* FMA4 support required */ + CpuFMA4, + /* XOP support required */ + CpuXOP, + /* LWP support required */ + CpuLWP, + /* BMI support required */ + CpuBMI, + /* TBM support required */ + CpuTBM, + /* MOVBE Instruction support required */ + CpuMovbe, + /* EPT Instructions required */ + CpuEPT, + /* RDTSCP Instruction support required */ + CpuRdtscp, + /* FSGSBASE Instructions required */ + CpuFSGSBase, + /* RDRND Instructions required */ + CpuRdRnd, + /* F16C Instructions required */ + CpuF16C, + /* 64bit support available, used by -march= in assembler. */ + CpuLM, + /* 64bit support required */ + Cpu64, + /* Not supported in the 64bit mode */ + CpuNo64, + /* The last bitfield in i386_cpu_flags. */ + CpuMax = CpuNo64 +}; + +#define CpuNumOfUints \ + (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) +#define CpuNumOfBits \ + (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) + +/* If you get a compiler error for zero width of the unused field, + comment it out. */ +#define CpuUnused (CpuMax + 1) + +/* We can check if an instruction is available with array instead + of bitfield. */ +typedef union i386_cpu_flags +{ + struct + { + unsigned int cpui186:1; + unsigned int cpui286:1; + unsigned int cpui386:1; + unsigned int cpui486:1; + unsigned int cpui586:1; + unsigned int cpui686:1; + unsigned int cpuclflush:1; + unsigned int cpunop:1; + unsigned int cpusyscall:1; + unsigned int cpu8087:1; + unsigned int cpu287:1; + unsigned int cpu387:1; + unsigned int cpu687:1; + unsigned int cpufisttp:1; + unsigned int cpummx:1; + unsigned int cpusse:1; + unsigned int cpusse2:1; + unsigned int cpua3dnow:1; + unsigned int cpua3dnowa:1; + unsigned int cpusse3:1; + unsigned int cpupadlock:1; + unsigned int cpusvme:1; + unsigned int cpuvmx:1; + unsigned int cpusmx:1; + unsigned int cpussse3:1; + unsigned int cpusse4a:1; + unsigned int cpuabm:1; + unsigned int cpusse4_1:1; + unsigned int cpusse4_2:1; + unsigned int cpuavx:1; + unsigned int cpul1om:1; + unsigned int cpuxsave:1; + unsigned int cpuxsaveopt:1; + unsigned int cpuaes:1; + unsigned int cpupclmul:1; + unsigned int cpufma:1; + unsigned int cpufma4:1; + unsigned int cpuxop:1; + unsigned int cpulwp:1; + unsigned int cpubmi:1; + unsigned int cputbm:1; + unsigned int cpumovbe:1; + unsigned int cpuept:1; + unsigned int cpurdtscp:1; + unsigned int cpufsgsbase:1; + unsigned int cpurdrnd:1; + unsigned int cpuf16c:1; + unsigned int cpulm:1; + unsigned int cpu64:1; + unsigned int cpuno64:1; +#ifdef CpuUnused + unsigned int unused:(CpuNumOfBits - CpuUnused); +#endif + } bitfield; + unsigned int array[CpuNumOfUints]; +} i386_cpu_flags; + +/* Position of opcode_modifier bits. */ + +enum +{ + /* has direction bit. */ + D = 0, + /* set if operands can be words or dwords encoded the canonical way */ + W, + /* Skip the current insn and use the next insn in i386-opc.tbl to swap + operand in encoding. */ + S, + /* insn has a modrm byte. */ + Modrm, + /* register is in low 3 bits of opcode */ + ShortForm, + /* special case for jump insns. */ + Jump, + /* call and jump */ + JumpDword, + /* loop and jecxz */ + JumpByte, + /* special case for intersegment leaps/calls */ + JumpInterSegment, + /* FP insn memory format bit, sized by 0x4 */ + FloatMF, + /* src/dest swap for floats. */ + FloatR, + /* has float insn direction bit. */ + FloatD, + /* needs size prefix if in 32-bit mode */ + Size16, + /* needs size prefix if in 16-bit mode */ + Size32, + /* needs size prefix if in 64-bit mode */ + Size64, + /* check register size. */ + CheckRegSize, + /* instruction ignores operand size prefix and in Intel mode ignores + mnemonic size suffix check. */ + IgnoreSize, + /* default insn size depends on mode */ + DefaultSize, + /* b suffix on instruction illegal */ + No_bSuf, + /* w suffix on instruction illegal */ + No_wSuf, + /* l suffix on instruction illegal */ + No_lSuf, + /* s suffix on instruction illegal */ + No_sSuf, + /* q suffix on instruction illegal */ + No_qSuf, + /* long double suffix on instruction illegal */ + No_ldSuf, + /* instruction needs FWAIT */ + FWait, + /* quick test for string instructions */ + IsString, + /* quick test for lockable instructions */ + IsLockable, + /* fake an extra reg operand for clr, imul and special register + processing for some instructions. */ + RegKludge, + /* The first operand must be xmm0 */ + FirstXmm0, + /* An implicit xmm0 as the first operand */ + Implicit1stXmm0, + /* Convert to DWORD */ + ToDword, + /* Convert to QWORD */ + ToQword, + /* Address prefix changes operand 0 */ + AddrPrefixOp0, + /* opcode is a prefix */ + IsPrefix, + /* instruction has extension in 8 bit imm */ + ImmExt, + /* instruction don't need Rex64 prefix. */ + NoRex64, + /* instruction require Rex64 prefix. */ + Rex64, + /* deprecated fp insn, gets a warning */ + Ugh, + /* insn has VEX prefix: + 1: 128bit VEX prefix. + 2: 256bit VEX prefix. + 3: Scalar VEX prefix. + */ +#define VEX128 1 +#define VEX256 2 +#define VEXScalar 3 + Vex, + /* How to encode VEX.vvvv: + 0: VEX.vvvv must be 1111b. + 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where + the content of source registers will be preserved. + VEX.DDS. The second register operand is encoded in VEX.vvvv + where the content of first source register will be overwritten + by the result. + For assembler, there are no difference between VEX.NDS and + VEX.DDS. + 2. VEX.NDD. Register destination is encoded in VEX.vvvv. + 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one + of the operands can access a memory location. + */ +#define VEXXDS 1 +#define VEXNDD 2 +#define VEXLWP 3 + VexVVVV, + /* How the VEX.W bit is used: + 0: Set by the REX.W bit. + 1: VEX.W0. Should always be 0. + 2: VEX.W1. Should always be 1. + */ +#define VEXW0 1 +#define VEXW1 2 + VexW, + /* VEX opcode prefix: + 0: VEX 0x0F opcode prefix. + 1: VEX 0x0F38 opcode prefix. + 2: VEX 0x0F3A opcode prefix + 3: XOP 0x08 opcode prefix. + 4: XOP 0x09 opcode prefix + 5: XOP 0x0A opcode prefix. + */ +#define VEX0F 0 +#define VEX0F38 1 +#define VEX0F3A 2 +#define XOP08 3 +#define XOP09 4 +#define XOP0A 5 + VexOpcode, + /* number of VEX source operands: + 0: <= 2 source operands. + 1: 2 XOP source operands. + 2: 3 source operands. + */ +#define XOP2SOURCES 1 +#define VEX3SOURCES 2 + VexSources, + /* instruction has VEX 8 bit imm */ + VexImmExt, + /* SSE to AVX support required */ + SSE2AVX, + /* No AVX equivalent */ + NoAVX, + /* Compatible with old (<= 2.8.1) versions of gcc */ + OldGcc, + /* AT&T mnemonic. */ + ATTMnemonic, + /* AT&T syntax. */ + ATTSyntax, + /* Intel syntax. */ + IntelSyntax, + /* The last bitfield in i386_opcode_modifier. */ + Opcode_Modifier_Max +}; + +typedef struct i386_opcode_modifier +{ + unsigned int d:1; + unsigned int w:1; + unsigned int s:1; + unsigned int modrm:1; + unsigned int shortform:1; + unsigned int jump:1; + unsigned int jumpdword:1; + unsigned int jumpbyte:1; + unsigned int jumpintersegment:1; + unsigned int floatmf:1; + unsigned int floatr:1; + unsigned int floatd:1; + unsigned int size16:1; + unsigned int size32:1; + unsigned int size64:1; + unsigned int checkregsize:1; + unsigned int ignoresize:1; + unsigned int defaultsize:1; + unsigned int no_bsuf:1; + unsigned int no_wsuf:1; + unsigned int no_lsuf:1; + unsigned int no_ssuf:1; + unsigned int no_qsuf:1; + unsigned int no_ldsuf:1; + unsigned int fwait:1; + unsigned int isstring:1; + unsigned int islockable:1; + unsigned int regkludge:1; + unsigned int firstxmm0:1; + unsigned int implicit1stxmm0:1; + unsigned int todword:1; + unsigned int toqword:1; + unsigned int addrprefixop0:1; + unsigned int isprefix:1; + unsigned int immext:1; + unsigned int norex64:1; + unsigned int rex64:1; + unsigned int ugh:1; + unsigned int vex:2; + unsigned int vexvvvv:2; + unsigned int vexw:2; + unsigned int vexopcode:3; + unsigned int vexsources:2; + unsigned int veximmext:1; + unsigned int sse2avx:1; + unsigned int noavx:1; + unsigned int oldgcc:1; + unsigned int attmnemonic:1; + unsigned int attsyntax:1; + unsigned int intelsyntax:1; +} i386_opcode_modifier; + +/* Position of operand_type bits. */ + +enum +{ + /* 8bit register */ + Reg8 = 0, + /* 16bit register */ + Reg16, + /* 32bit register */ + Reg32, + /* 64bit register */ + Reg64, + /* Floating pointer stack register */ + FloatReg, + /* MMX register */ + RegMMX, + /* SSE register */ + RegXMM, + /* AVX registers */ + RegYMM, + /* Control register */ + Control, + /* Debug register */ + Debug, + /* Test register */ + Test, + /* 2 bit segment register */ + SReg2, + /* 3 bit segment register */ + SReg3, + /* 1 bit immediate */ + Imm1, + /* 8 bit immediate */ + Imm8, + /* 8 bit immediate sign extended */ + Imm8S, + /* 16 bit immediate */ + Imm16, + /* 32 bit immediate */ + Imm32, + /* 32 bit immediate sign extended */ + Imm32S, + /* 64 bit immediate */ + Imm64, + /* 8bit/16bit/32bit displacements are used in different ways, + depending on the instruction. For jumps, they specify the + size of the PC relative displacement, for instructions with + memory operand, they specify the size of the offset relative + to the base register, and for instructions with memory offset + such as `mov 1234,%al' they specify the size of the offset + relative to the segment base. */ + /* 8 bit displacement */ + Disp8, + /* 16 bit displacement */ + Disp16, + /* 32 bit displacement */ + Disp32, + /* 32 bit signed displacement */ + Disp32S, + /* 64 bit displacement */ + Disp64, + /* Accumulator %al/%ax/%eax/%rax */ + Acc, + /* Floating pointer top stack register %st(0) */ + FloatAcc, + /* Register which can be used for base or index in memory operand. */ + BaseIndex, + /* Register to hold in/out port addr = dx */ + InOutPortReg, + /* Register to hold shift count = cl */ + ShiftCount, + /* Absolute address for jump. */ + JumpAbsolute, + /* String insn operand with fixed es segment */ + EsSeg, + /* RegMem is for instructions with a modrm byte where the register + destination operand should be encoded in the mod and regmem fields. + Normally, it will be encoded in the reg field. We add a RegMem + flag to the destination register operand to indicate that it should + be encoded in the regmem field. */ + RegMem, + /* Memory. */ + Mem, + /* BYTE memory. */ + Byte, + /* WORD memory. 2 byte */ + Word, + /* DWORD memory. 4 byte */ + Dword, + /* FWORD memory. 6 byte */ + Fword, + /* QWORD memory. 8 byte */ + Qword, + /* TBYTE memory. 10 byte */ + Tbyte, + /* XMMWORD memory. */ + Xmmword, + /* YMMWORD memory. */ + Ymmword, + /* Unspecified memory size. */ + Unspecified, + /* Any memory size. */ + Anysize, + + /* Vector 4 bit immediate. */ + Vec_Imm4, + + /* The last bitfield in i386_operand_type. */ + OTMax +}; + +#define OTNumOfUints \ + (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) +#define OTNumOfBits \ + (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) + +/* If you get a compiler error for zero width of the unused field, + comment it out. */ +#define OTUnused (OTMax + 1) + +typedef union i386_operand_type +{ + struct + { + unsigned int reg8:1; + unsigned int reg16:1; + unsigned int reg32:1; + unsigned int reg64:1; + unsigned int floatreg:1; + unsigned int regmmx:1; + unsigned int regxmm:1; + unsigned int regymm:1; + unsigned int control:1; + unsigned int debug:1; + unsigned int test:1; + unsigned int sreg2:1; + unsigned int sreg3:1; + unsigned int imm1:1; + unsigned int imm8:1; + unsigned int imm8s:1; + unsigned int imm16:1; + unsigned int imm32:1; + unsigned int imm32s:1; + unsigned int imm64:1; + unsigned int disp8:1; + unsigned int disp16:1; + unsigned int disp32:1; + unsigned int disp32s:1; + unsigned int disp64:1; + unsigned int acc:1; + unsigned int floatacc:1; + unsigned int baseindex:1; + unsigned int inoutportreg:1; + unsigned int shiftcount:1; + unsigned int jumpabsolute:1; + unsigned int esseg:1; + unsigned int regmem:1; + unsigned int mem:1; + unsigned int byte:1; + unsigned int word:1; + unsigned int dword:1; + unsigned int fword:1; + unsigned int qword:1; + unsigned int tbyte:1; + unsigned int xmmword:1; + unsigned int ymmword:1; + unsigned int unspecified:1; + unsigned int anysize:1; + unsigned int vec_imm4:1; +#ifdef OTUnused + unsigned int unused:(OTNumOfBits - OTUnused); +#endif + } bitfield; + unsigned int array[OTNumOfUints]; +} i386_operand_type; + +typedef struct insn_template +{ + /* instruction name sans width suffix ("mov" for movl insns) */ + char *name; + + /* how many operands */ + unsigned int operands; + + /* base_opcode is the fundamental opcode byte without optional + prefix(es). */ + unsigned int base_opcode; +#define Opcode_D 0x2 /* Direction bit: + set if Reg --> Regmem; + unset if Regmem --> Reg. */ +#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ +#define Opcode_FloatD 0x400 /* Direction bit for float insns. */ + + /* extension_opcode is the 3 bit extension for group insns. + This field is also used to store the 8-bit opcode suffix for the + AMD 3DNow! instructions. + If this template has no extension opcode (the usual case) use None + Instructions */ + unsigned int extension_opcode; +#define None 0xffff /* If no extension_opcode is possible. */ + + /* Opcode length. */ + unsigned char opcode_length; + + /* cpu feature flags */ + i386_cpu_flags cpu_flags; + + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + i386_opcode_modifier opcode_modifier; + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand. */ + i386_operand_type operand_types[MAX_OPERANDS]; +} +insn_template; + +extern const insn_template i386_optab[]; + +/* these are for register name --> number & type hash lookup */ +typedef struct +{ + char *reg_name; + i386_operand_type reg_type; + unsigned char reg_flags; +#define RegRex 0x1 /* Extended register. */ +#define RegRex64 0x2 /* Extended 8 bit register. */ + unsigned char reg_num; +#define RegRip ((unsigned char ) ~0) +#define RegEip (RegRip - 1) +/* EIZ and RIZ are fake index registers. */ +#define RegEiz (RegEip - 1) +#define RegRiz (RegEiz - 1) +/* FLAT is a fake segment register (Intel mode). */ +#define RegFlat ((unsigned char) ~0) + signed char dw2_regnum[2]; +#define Dw2Inval (-1) +} +reg_entry; + +/* Entries in i386_regtab. */ +#define REGNAM_AL 1 +#define REGNAM_AX 25 +#define REGNAM_EAX 41 + +extern const reg_entry i386_regtab[]; +extern const unsigned int i386_regtab_size; + +typedef struct +{ + char *seg_name; + unsigned int seg_prefix; +} +seg_entry; + +extern const seg_entry cs; +extern const seg_entry ds; +extern const seg_entry ss; +extern const seg_entry es; +extern const seg_entry fs; +extern const seg_entry gs; diff --git a/external/gpl3/gdb/dist/opcodes/i386-opc.tbl b/external/gpl3/gdb/dist/opcodes/i386-opc.tbl new file mode 100644 index 000000000000..bffe13404a6e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-opc.tbl @@ -0,0 +1,2846 @@ +// i386 opcode table. +// Copyright 2007, 2008, 2009, 2010 +// Free Software Foundation, Inc. +// +// This file is part of the GNU opcodes library. +// +// This library is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3, or (at your option) +// any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +// License for more details. +// +// You should have received a copy of the GNU General Public License +// along with GAS; see the file COPYING. If not, write to the Free +// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA +// 02110-1301, USA. + +// Move instructions. +// We put the 64bit displacement first and we only mark constants +// larger than 32bit as Disp64. +mov, 2, 0xa0, None, 1, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +mov, 2, 0xa0, None, 1, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } +mov, 2, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// In the 64bit mode the short form mov immediate is redefined to have +// 64bit value. +mov, 2, 0xb0, None, 1, 0, W|CheckRegSize|ShortForm|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } +mov, 2, 0xc6, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0xb0, None, 1, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 } +// The segment register moves accept WordReg so that a segment register +// can be copied to a 32 bit register, and vice versa, without using a +// size prefix. When moving to a 32 bit register, the upper 16 bits +// are set to an implementation defined value (on the Pentium Pro, the +// implementation defined value is zero). +mov, 2, 0x8c, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2, Reg16|Reg32|Reg64|RegMem } +mov, 2, 0x8c, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0x8c, None, 1, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3, Reg16|Reg32|Reg64|RegMem } +mov, 2, 0x8c, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64, SReg2 } +mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 } +mov, 2, 0x8e, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64, SReg3 } +mov, 2, 0x8e, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 } +// Move to/from control debug registers. In the 16 or 32bit modes +// they are 32bit. In the 64bit mode they are 64bit. +mov, 2, 0xf20, None, 2, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Control, Reg32|RegMem } +mov, 2, 0xf20, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Control, Reg64|RegMem } +mov, 2, 0xf21, None, 2, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Debug, Reg32|RegMem } +mov, 2, 0xf21, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Debug, Reg64|RegMem } +mov, 2, 0xf24, None, 2, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32|RegMem } +movabs, 2, 0xa0, None, 1, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } +movabs, 2, 0xb0, None, 1, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 } + +// Move after swapping the bytes +movbe, 2, 0x0f38f0, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movbe, 2, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Move with sign extend. +// "movsbl" & "movsbw" must not be unified into "movsb" to avoid +// conflict with the "movs" string move instruction. +movsbl, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movsbw, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } +movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +// Intel Syntax next 3 insns +movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } + +// Move with zero extend. We can't remove "movzb" since existing +// assembly codes may use it. +movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +// "movzbl" & "movzbw" should not be unified into "movzb" for +// consistency with the sign extending moves above. +movzbl, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movzbw, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } +movzwl, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +// These instructions are not particulary useful, since the zero extend +// 32->64 is implicit, but we can encode them. +movzbq, 2, 0xfb6, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +movzwq, 2, 0xfb7, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +// Intel Syntax next 2 insns (the 64-bit variants are not particulary +// useful since the zero extend 32->64 is implicit, but we can encode them). +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } + +// Push instructions. +push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S } +push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 } +push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2 } +push, 1, 0xfa0, None, 2, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3 } +// In 64bit mode, the operand size is implicitly 64bit. +push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } +push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S } +push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S } +push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg3 } + +pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Pop instructions. +pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2 } +pop, 1, 0xfa1, None, 2, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3 } +// In 64bit mode, the operand size is implicitly 64bit. +pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } +pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg3 } + +popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Exchange instructions. +// xchg commutes: we allow both operand orders. + +// In the 64bit code, xchg rax, rax is reused for new nop instruction. +xchg, 2, 0x90, None, 1, 0, ShortForm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } +xchg, 2, 0x90, None, 1, 0, ShortForm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 } +xchg, 2, 0x86, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xchg, 2, 0x86, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } + +// In/out from ports. +in, 2, 0xe4, None, 1, 0, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Acc|Byte|Word|Dword } +in, 2, 0xec, None, 1, 0, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg, Acc|Byte|Word|Dword } +in, 1, 0xe4, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } +in, 1, 0xec, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg } +out, 2, 0xe6, None, 1, 0, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, Imm8 } +out, 2, 0xee, None, 1, 0, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, InOutPortReg } +out, 1, 0xe6, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } +out, 1, 0xee, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg } + +// Load effective address. +lea, 2, 0x8d, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// Load segment registers from memory. +lds, 2, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32, Reg16|Reg32 } +les, 2, 0xc4, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32, Reg16|Reg32 } +lfs, 2, 0xfb4, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lgs, 2, 0xfb5, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lss, 2, 0xfb2, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// Flags register instructions. +clc, 0, 0xf8, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cld, 0, 0xfc, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cli, 0, 0xfa, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +clts, 0, 0xf06, None, 2, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cmc, 0, 0xf5, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +lahf, 0, 0x9f, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +sahf, 0, 0x9e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +pushf, 0, 0x9c, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +pushf, 0, 0x9c, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 } +popf, 0, 0x9d, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +popf, 0, 0x9d, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 } +stc, 0, 0xf9, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +std, 0, 0xfd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +sti, 0, 0xfb, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Arithmetic. +add, 2, 0x0, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +add, 2, 0x83, 0x0, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +add, 2, 0x4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +add, 2, 0x80, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +inc, 1, 0x40, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +inc, 1, 0xfe, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sub, 2, 0x28, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sub, 2, 0x83, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sub, 2, 0x2c, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +sub, 2, 0x80, 0x5, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +dec, 1, 0x48, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +dec, 1, 0xfe, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sbb, 2, 0x18, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sbb, 2, 0x83, 0x3, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sbb, 2, 0x1c, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +sbb, 2, 0x80, 0x3, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +cmp, 2, 0x38, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmp, 2, 0x83, 0x7, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmp, 2, 0x3c, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +cmp, 2, 0x80, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +test, 2, 0x84, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +test, 2, 0x84, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } +test, 2, 0xa8, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +test, 2, 0xf6, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +and, 2, 0x20, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +and, 2, 0x24, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +and, 2, 0x80, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +or, 2, 0x8, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +or, 2, 0x83, 0x1, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +or, 2, 0xc, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +or, 2, 0x80, 0x1, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +xor, 2, 0x30, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xor, 2, 0x83, 0x6, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xor, 2, 0x34, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +xor, 2, 0x80, 0x6, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// clr with 1 operand is really xor with 2 operands. +clr, 1, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 } + +adc, 2, 0x10, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +adc, 2, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +adc, 2, 0x14, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } +adc, 2, 0x80, 0x2, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +neg, 1, 0xf6, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +not, 1, 0xf6, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +aaa, 0, 0x37, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +aas, 0, 0x3f, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +daa, 0, 0x27, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +das, 0, 0x2f, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +aad, 0, 0xd50a, None, 2, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +aad, 1, 0xd5, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } +aam, 0, 0xd40a, None, 2, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +aam, 1, 0xd4, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } + +// Conversion insns. +// Intel naming +cbw, 0, 0x98, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cdqe, 0, 0x98, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cwde, 0, 0x98, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cwd, 0, 0x99, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cdq, 0, 0x99, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cqo, 0, 0x99, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// AT&T naming +cbtw, 0, 0x98, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cltq, 0, 0x98, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cwtl, 0, 0x98, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cwtd, 0, 0x99, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cltd, 0, 0x99, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cqto, 0, 0x99, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are +// expanding 64-bit multiplies, and *cannot* be selected to accomplish +// 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) +// These multiplies can only be selected with single operand forms. +mul, 1, 0xf6, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +imul, 1, 0xf6, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +imul, 2, 0xfaf, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +imul, 3, 0x6b, None, 1, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +imul, 3, 0x69, None, 1, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +// imul with 2 operands mimics imul with 3 by putting the register in +// both i.rm.reg & i.rm.regmem fields. RegKludge enables this +// transformation. +imul, 2, 0x6b, None, 1, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } +imul, 2, 0x69, None, 1, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } + +div, 1, 0xf6, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +div, 2, 0xf6, 0x6, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword } +idiv, 1, 0xf6, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +idiv, 2, 0xf6, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword } + +rol, 2, 0xd0, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 2, 0xc0, 0x0, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 2, 0xd2, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 1, 0xd0, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +ror, 2, 0xd0, 0x1, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 2, 0xc0, 0x1, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 2, 0xd2, 0x1, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 1, 0xd0, 0x1, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +rcl, 2, 0xd0, 0x2, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 2, 0xc0, 0x2, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 2, 0xd2, 0x2, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 1, 0xd0, 0x2, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +rcr, 2, 0xd0, 0x3, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 2, 0xc0, 0x3, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 2, 0xd2, 0x3, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 1, 0xd0, 0x3, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sal, 2, 0xd0, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 2, 0xc0, 0x4, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 2, 0xd2, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 1, 0xd0, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shl, 2, 0xd0, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 2, 0xc0, 0x4, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 2, 0xd2, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 1, 0xd0, 0x4, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shr, 2, 0xd0, 0x5, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 2, 0xc0, 0x5, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 2, 0xd2, 0x5, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 1, 0xd0, 0x5, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sar, 2, 0xd0, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 2, 0xc0, 0x7, 1, Cpu186, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 2, 0xd2, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 1, 0xd0, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shld, 3, 0xfa4, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shld, 3, 0xfa5, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shld, 2, 0xfa5, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shrd, 3, 0xfac, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shrd, 3, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shrd, 2, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Control transfer instructions. +call, 1, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32 } +call, 1, 0xe8, None, 1, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Disp16|Disp32 } +call, 1, 0xff, 0x2, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute } +call, 1, 0xff, 0x2, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } +// Intel Syntax +call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } +// Intel Syntax +call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } +lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } + +jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute } +jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute } +// Intel Syntax. +jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } +// Intel Syntax. +jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } +ljmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } + +ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16 } +ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 } +ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16 } +lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 } +lret, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 } +// Intel Syntax. +retf, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 } +retf, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 } + +enter, 2, 0xc8, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 } +enter, 2, 0xc8, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 } +leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +leave, 0, 0xc9, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { 0 } + +// Conditional jumps. +jo, 1, 0x70, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jno, 1, 0x71, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jb, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jc, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnae, 1, 0x72, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnb, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnc, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jae, 1, 0x73, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +je, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jz, 1, 0x74, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jne, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnz, 1, 0x75, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jbe, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jna, 1, 0x76, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnbe, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +ja, 1, 0x77, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +js, 1, 0x78, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jns, 1, 0x79, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jp, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jpe, 1, 0x7a, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnp, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jpo, 1, 0x7b, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jl, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnge, 1, 0x7c, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnl, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jge, 1, 0x7d, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jle, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jng, 1, 0x7e, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } +jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S } + +// jcxz vs. jecxz is chosen on the basis of the address size prefix. +jcxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +jecxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +jecxz, 1, 0x67e3, None, 2, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp32|Disp32S } +jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } + +// The loop instructions also use the address size prefix to select +// %cx rather than %ecx for the loop count, so the `w' form of these +// instructions emit an address size prefix rather than a data size +// prefix. +loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } +loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } +loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } +loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } +loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 } +loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S } + +// Set byte on flag instructions. +seto, 1, 0xf90, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setno, 1, 0xf91, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setb, 1, 0xf92, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setc, 1, 0xf92, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnae, 1, 0xf92, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnb, 1, 0xf93, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnc, 1, 0xf93, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setae, 1, 0xf93, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sete, 1, 0xf94, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setz, 1, 0xf94, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setne, 1, 0xf95, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnz, 1, 0xf95, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setbe, 1, 0xf96, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setna, 1, 0xf96, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnbe, 1, 0xf97, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +seta, 1, 0xf97, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sets, 1, 0xf98, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setns, 1, 0xf99, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setp, 1, 0xf9a, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setpe, 1, 0xf9a, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnp, 1, 0xf9b, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setpo, 1, 0xf9b, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setl, 1, 0xf9c, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnge, 1, 0xf9c, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnl, 1, 0xf9d, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setge, 1, 0xf9d, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setle, 1, 0xf9e, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setng, 1, 0xf9e, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnle, 1, 0xf9f, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setg, 1, 0xf9f, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// String manipulation. +cmps, 0, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +cmps, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +scmp, 0, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +scmp, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ins, 0, 0x6c, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } +ins, 2, 0x6c, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +outs, 0, 0x6e, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } +outs, 2, 0x6e, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg } +lods, 0, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +lods, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lods, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword } +slod, 0, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +slod, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +slod, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword } +movs, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +movs, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +smov, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +smov, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +scas, 0, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +scas, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +scas, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc|Byte|Word|Dword|Qword } +ssca, 0, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +ssca, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssca, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc|Byte|Word|Dword|Qword } +stos, 0, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +stos, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +stos, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssto, 0, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { 0 } +ssto, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssto, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +xlat, 0, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } +xlat, 1, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Bit manipulation. +bsf, 2, 0xfbc, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +bsr, 2, 0xfbd, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +bt, 2, 0xfa3, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bt, 2, 0xfba, 0x4, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btc, 2, 0xfbb, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btc, 2, 0xfba, 0x7, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btr, 2, 0xfb3, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btr, 2, 0xfba, 0x6, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bts, 2, 0xfab, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Interrupts & op. sys insns. +// See gas/config/tc-i386.c for conversion of 'int $3' into the special +// int 3 insn. +int, 1, 0xcd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } +int3, 0, 0xcc, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +into, 0, 0xce, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +iret, 0, 0xcf, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 } +// i386sl, i486sl, later 486, and Pentium. +rsm, 0, 0xfaa, None, 2, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +bound, 2, 0x62, None, 1, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } + +hlt, 0, 0xf4, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +nop, 1, 0xf1f, 0x0, 2, CpuNop, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in +// 32bit mode and "xchg %rax,%rax" in 64bit mode. +nop, 0, 0x90, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Protection control. +arpl, 2, 0x63, None, 1, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +lar, 2, 0xf02, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lgdt, 1, 0xf01, 0x2, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Tbyte|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +lgdt, 1, 0xf01, 0x2, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +lidt, 1, 0xf01, 0x3, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +lidt, 1, 0xf01, 0x3, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +lldt, 1, 0xf00, 0x2, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lmsw, 1, 0xf01, 0x6, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lsl, 2, 0xf03, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +ltr, 1, 0xf00, 0x3, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sgdt, 1, 0xf01, 0x0, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +sgdt, 1, 0xf01, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +sidt, 1, 0xf01, 0x1, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +sidt, 1, 0xf01, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 } +sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +smsw, 1, 0xf01, 0x4, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 } +smsw, 1, 0xf01, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +str, 1, 0xf00, 0x1, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 } +str, 1, 0xf00, 0x1, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +verr, 1, 0xf00, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +verw, 1, 0xf00, 0x5, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Floating point instructions. + +// load +fld, 1, 0xd9c0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fld, 1, 0xd9, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fld, 1, 0xd9c0, None, 2, CpuFP, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } +// Intel Syntax +fld, 1, 0xdb, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fild, 1, 0xdf, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fild, 1, 0xdf, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fildll, 1, 0xdf, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fldt, 1, 0xdb, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fbld, 1, 0xdf, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// store (no pop) +fst, 1, 0xddd0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fst, 1, 0xd9, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fst, 1, 0xddd0, None, 2, CpuFP, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } +fist, 1, 0xdf, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// store (with pop) +fstp, 1, 0xddd8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fstp, 1, 0xd9, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstp, 1, 0xddd8, None, 2, CpuFP, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } +// Intel Syntax +fstp, 1, 0xdb, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistp, 1, 0xdf, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistp, 1, 0xdf, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistpll, 1, 0xdf, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstpt, 1, 0xdb, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fbstp, 1, 0xdf, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// exchange %st with %st0 +fxch, 1, 0xd9c8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fxch %st(1) +fxch, 0, 0xd9c9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// comparison (without pop) +fcom, 1, 0xd8d0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fcom %st(1) +fcom, 0, 0xd8d1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcom, 1, 0xd8, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcom, 1, 0xd8d0, None, 2, CpuFP, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } +ficom, 1, 0xde, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// comparison (with pop) +fcomp, 1, 0xd8d8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fcomp %st(1) +fcomp, 0, 0xd8d9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcomp, 1, 0xd8, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcomp, 1, 0xd8d8, None, 2, CpuFP, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } +ficomp, 1, 0xde, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcompp, 0, 0xded9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// unordered comparison (with pop) +fucom, 1, 0xdde0, None, 2, Cpu387, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fucom %st(1) +fucom, 0, 0xdde1, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fucomp, 1, 0xdde8, None, 2, Cpu387, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fucomp %st(1) +fucomp, 0, 0xdde9, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fucompp, 0, 0xdae9, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +ftst, 0, 0xd9e4, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fxam, 0, 0xd9e5, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// load constants into %st0 +fld1, 0, 0xd9e8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldl2t, 0, 0xd9e9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldl2e, 0, 0xd9ea, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldpi, 0, 0xd9eb, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldlg2, 0, 0xd9ec, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldln2, 0, 0xd9ed, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fldz, 0, 0xd9ee, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Arithmetic. + +// add +fadd, 2, 0xd8c0, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +// alias for fadd %st(i), %st +fadd, 1, 0xd8c0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for faddp +fadd, 0, 0xdec1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fadd, 1, 0xd8, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fiadd, 1, 0xde, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +faddp, 2, 0xdec0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg } +faddp, 1, 0xdec0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for faddp %st, %st(1) +faddp, 0, 0xdec1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +faddp, 2, 0xdec0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc } + +// subtract +fsub, 1, 0xd8e0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fsub, 2, 0xd8e0, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +// alias for fsubp +fsub, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 } +fsub, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fsub, 2, 0xd8e0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +fsub, 1, 0xd8, 0x4, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisub, 1, 0xde, 0x4, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fsubp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubp, 1, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubp, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 } +fsubp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc } +fsubp, 2, 0xdee9, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc } +fsubp, 2, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fsubp, 1, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg } +fsubp, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// subtract reverse +fsubr, 1, 0xd8e8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fsubr, 2, 0xd8e8, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +// alias for fsubrp +fsubr, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 } +fsubr, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fsubr, 2, 0xd8e8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +fsubr, 1, 0xd8, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisubr, 1, 0xde, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fsubrp, 2, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fsubrp, 1, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fsubrp, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 } +fsubrp, 2, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc } +fsubrp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc } +fsubrp, 2, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fsubrp, 1, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg } +fsubrp, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 } + +// multiply +fmul, 2, 0xd8c8, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fmul, 1, 0xd8c8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// alias for fmulp +fmul, 0, 0xdec9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fmul, 1, 0xd8, 0x1, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fimul, 1, 0xde, 0x1, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fmulp, 2, 0xdec8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg } +fmulp, 1, 0xdec8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fmulp, 0, 0xdec9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fmulp, 2, 0xdec8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc } + +// divide +fdiv, 1, 0xd8f0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fdiv, 2, 0xd8f0, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +// alias for fdivp +fdiv, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 } +fdiv, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fdiv, 2, 0xd8f0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +fdiv, 1, 0xd8, 0x6, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fidiv, 1, 0xde, 0x6, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fdivp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivp, 1, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivp, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 } +fdivp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc } +fdivp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc } +fdivp, 2, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fdivp, 1, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg } +fdivp, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 } + +// divide reverse +fdivr, 1, 0xd8f8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fdivr, 2, 0xd8f8, None, 2, CpuFP, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc } +// alias for fdivrp +fdivr, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, { 0 } +fdivr, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } +fdivr, 2, 0xd8f8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +fdivr, 1, 0xd8, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fidivr, 1, 0xde, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fdivrp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } +fdivrp, 1, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg } +fdivrp, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 } +fdivrp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc } +fdivrp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc } +fdivrp, 2, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fdivrp, 1, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg } +fdivrp, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 } + +f2xm1, 0, 0xd9f0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fyl2x, 0, 0xd9f1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fptan, 0, 0xd9f2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fpatan, 0, 0xd9f3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fxtract, 0, 0xd9f4, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fprem1, 0, 0xd9f5, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fdecstp, 0, 0xd9f6, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fincstp, 0, 0xd9f7, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fprem, 0, 0xd9f8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fyl2xp1, 0, 0xd9f9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fsqrt, 0, 0xd9fa, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fsincos, 0, 0xd9fb, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +frndint, 0, 0xd9fc, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fscale, 0, 0xd9fd, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fsin, 0, 0xd9fe, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcos, 0, 0xd9ff, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fchs, 0, 0xd9e0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fabs, 0, 0xd9e1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// processor control +fninit, 0, 0xdbe3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +finit, 0, 0xdbe3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +fldcw, 1, 0xd9, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnstcw, 1, 0xd9, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstcw, 1, 0xd9, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnstsw, 1, 0xdfe0, None, 2, Cpu287|Cpu387, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Word } +fnstsw, 1, 0xdd, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnstsw, 0, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fstsw, 1, 0xdfe0, None, 2, Cpu287|Cpu387, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Acc|Word } +fstsw, 1, 0xdd, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstsw, 0, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +fnclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fclex, 0, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +// Short forms of fldenv, fstenv use data size prefix. +fnstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstenv, 1, 0xd9, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fldenv, 1, 0xd9, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fsave, 1, 0xdd, 0x6, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +frstor, 1, 0xdd, 0x4, 1, CpuFP, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// 8087 only +fneni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +feni, 0, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +fndisi, 0, 0xdbe1, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fdisi, 0, 0xdbe1, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +// 287 only +fnsetpm, 0, 0xdbe4, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fsetpm, 0, 0xdbe4, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { 0 } +frstpm, 0, 0xdbe5, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +ffree, 1, 0xddc0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +// P6:free st(i), pop st +ffreep, 1, 0xdfc0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fnop, 0, 0xd9d0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fwait, 0, 0x9b, None, 1, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Opcode prefixes; we allow them as separate insns too. + +addr16, 0, 0x67, None, 1, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +addr32, 0, 0x67, None, 1, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +aword, 0, 0x67, None, 1, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +adword, 0, 0x67, None, 1, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +data16, 0, 0x66, None, 1, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +data32, 0, 0x66, None, 1, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +word, 0, 0x66, None, 1, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +dword, 0, 0x66, None, 1, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +lock, 0, 0xf0, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +wait, 0, 0x9b, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +cs, 0, 0x2e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +ds, 0, 0x3e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +es, 0, 0x26, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +fs, 0, 0x64, None, 1, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +gs, 0, 0x65, None, 1, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +ss, 0, 0x36, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rep, 0, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +repe, 0, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +repz, 0, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +repne, 0, 0xf2, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +repnz, 0, 0xf2, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +ht, 0, 0x3e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +hnt, 0, 0x2e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex, 0, 0x40, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexz, 0, 0x41, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexy, 0, 0x42, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexyz, 0, 0x43, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexx, 0, 0x44, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexxz, 0, 0x45, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexxy, 0, 0x46, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rexxyz, 0, 0x47, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64, 0, 0x48, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64z, 0, 0x49, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64y, 0, 0x4a, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64yz, 0, 0x4b, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64x, 0, 0x4c, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64xz, 0, 0x4d, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64xy, 0, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex64xyz, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.b, 0, 0x41, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.x, 0, 0x42, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.xb, 0, 0x43, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.r, 0, 0x44, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.rb, 0, 0x45, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.rx, 0, 0x46, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.rxb, 0, 0x47, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.w, 0, 0x48, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wb, 0, 0x49, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wx, 0, 0x4a, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wxb, 0, 0x4b, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wr, 0, 0x4c, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wrb, 0, 0x4d, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wrx, 0, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } +rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 } + +// 486 extensions. + +bswap, 1, 0xfc8, None, 2, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64 } +xadd, 2, 0xfc0, None, 2, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmpxchg, 2, 0xfb0, None, 2, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +invd, 0, 0xf08, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +wbinvd, 0, 0xf09, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// 586 and late 486 extensions. +cpuid, 0, 0xfa2, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// Pentium extensions. +wrmsr, 0, 0xf30, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +rdtsc, 0, 0xf31, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|IsLockable, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Pentium II/Pentium Pro extensions. +sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fxsave, 1, 0xfae, 0x0, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxsave64, 1, 0xfae, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxrstor, 1, 0xfae, 0x1, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxrstor64, 1, 0xfae, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rdpmc, 0, 0xf33, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// official undefined instr. +ud2, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// alias for ud2 +ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// 2nd. official undefined instr. +ud1, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// alias for ud1 +ud2b, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +cmovo, 2, 0xf40, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovno, 2, 0xf41, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovb, 2, 0xf42, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovc, 2, 0xf42, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnae, 2, 0xf42, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovae, 2, 0xf43, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnc, 2, 0xf43, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnb, 2, 0xf43, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmove, 2, 0xf44, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovz, 2, 0xf44, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovne, 2, 0xf45, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnz, 2, 0xf45, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovbe, 2, 0xf46, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovna, 2, 0xf46, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmova, 2, 0xf47, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnbe, 2, 0xf47, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovs, 2, 0xf48, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovns, 2, 0xf49, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovp, 2, 0xf4a, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnp, 2, 0xf4b, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovl, 2, 0xf4c, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnge, 2, 0xf4c, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovge, 2, 0xf4d, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnl, 2, 0xf4d, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovle, 2, 0xf4e, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovng, 2, 0xf4e, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovg, 2, 0xf4f, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnle, 2, 0xf4f, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovpe, 2, 0xf4a, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovpo, 2, 0xf4b, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +fcmovb, 2, 0xdac0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovnae, 2, 0xdac0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmove, 2, 0xdac8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovbe, 2, 0xdad0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovna, 2, 0xdad0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovu, 2, 0xdad8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovae, 2, 0xdbc0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovnb, 2, 0xdbc0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovne, 2, 0xdbc8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmova, 2, 0xdbd0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovnbe, 2, 0xdbd0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcmovnu, 2, 0xdbd8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } + +fcomi, 2, 0xdbf0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcomi, 0, 0xdbf1, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcomi, 1, 0xdbf0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fucomi, 2, 0xdbe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fucomi, 0, 0xdbe9, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fucomi, 1, 0xdbe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fcomip, 2, 0xdff0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcomip, 0, 0xdff1, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcomip, 1, 0xdff0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fcompi, 2, 0xdff0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fcompi, 0, 0xdff1, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fcompi, 1, 0xdff0, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fucomip, 2, 0xdfe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fucomip, 0, 0xdfe9, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fucomip, 1, 0xdfe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } +fucompi, 2, 0xdfe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc } +fucompi, 0, 0xdfe9, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +fucompi, 1, 0xdfe8, None, 2, Cpu687, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg } + +// Pentium4 extensions. + +movnti, 2, 0xfc3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +clflush, 1, 0xfae, 0x7, 2, CpuClflush, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lfence, 0, 0xfae, 0xe8, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 } +mfence, 0, 0xfae, 0xf0, 2, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 } +// Processors that do not support PAUSE treat this opcode as a NOP instruction. +pause, 0, 0xf390, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// MMX/SSE2 instructions. + +emms, 0, 0xf77, None, 2, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +// These really shouldn't allow for Reg64 (movq is the right mnemonic for +// copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's +// spec). AMD's spec, having been in existence for much longer, failed to +// recognize that and specified movd for 32- and 64-bit operations. +movd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|SSE2AVX, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S } +movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S, RegXMM } +movd, 2, 0x660f6e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S, RegXMM } +movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S } +movd, 2, 0x660f7e, None, 2, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S } +movd, 2, 0xf6e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +movd, 2, 0xf6e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } +movd, 2, 0xf7e, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Disp32S } +movd, 2, 0xf7e, None, 2, CpuMMX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegMMX, Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S|Disp32S } +// In the 64bit mode the short form mov immediate is redefined to have +// 64bit displacement value. We put the 64bit displacement first and +// we only mark constants larger than 32bit as Disp64. +movq, 2, 0xa0, None, 1, Cpu64, D|W|CheckRegSize|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp64|Unspecified|Qword, Acc|Qword } +movq, 2, 0x88, None, 1, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm32S, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm64, Reg64 } +movq, 2, 0xf37e, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xf30f7e, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } +movq, 2, 0xf6f, None, 2, CpuMMX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } +movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX } +movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S } +// The segment register moves accept Reg64 so that a segment register +// can be copied to a 64 bit register, and vice versa. +movq, 2, 0x8c, None, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Reg64|RegMem } +movq, 2, 0x8e, None, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, SReg2|SReg3 } +// Move to/from control debug registers. In the 16 or 32bit modes they +// are 32bit. In the 64bit mode they are 64bit. +movq, 2, 0xf20, None, 2, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Control, Reg64|RegMem } +movq, 2, 0xf21, None, 2, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Debug, Reg64|RegMem } +// Real MMX/SSE instructions. +packssdw, 2, 0x666b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packssdw, 2, 0x660f6b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packssdw, 2, 0xf6b, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packsswb, 2, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packsswb, 2, 0x660f63, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packsswb, 2, 0xf63, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packuswb, 2, 0x6667, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packuswb, 2, 0x660f67, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packuswb, 2, 0xf67, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddb, 2, 0x66fc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddb, 2, 0x660ffc, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddb, 2, 0xffc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddw, 2, 0x66fd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddw, 2, 0x660ffd, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddw, 2, 0xffd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddd, 2, 0x66fe, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddd, 2, 0x660ffe, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddd, 2, 0xffe, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddq, 2, 0x66d4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddq, 2, 0x660fd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddq, 2, 0xfd4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsb, 2, 0x66ec, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsb, 2, 0x660fec, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsb, 2, 0xfec, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsw, 2, 0x66ed, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsw, 2, 0x660fed, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsw, 2, 0xfed, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusb, 2, 0x66dc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusb, 2, 0x660fdc, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusb, 2, 0xfdc, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusw, 2, 0x66dd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusw, 2, 0x660fdd, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusw, 2, 0xfdd, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pand, 2, 0x66db, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pand, 2, 0x660fdb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pand, 2, 0xfdb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pandn, 2, 0x66df, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pandn, 2, 0x660fdf, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pandn, 2, 0xfdf, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqb, 2, 0x6674, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqb, 2, 0x660f74, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqb, 2, 0xf74, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqw, 2, 0x6675, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqw, 2, 0x660f75, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqw, 2, 0xf75, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqd, 2, 0x6676, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqd, 2, 0x660f76, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqd, 2, 0xf76, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtb, 2, 0x6664, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtb, 2, 0x660f64, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtb, 2, 0xf64, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtw, 2, 0x6665, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtw, 2, 0x660f65, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtw, 2, 0xf65, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtd, 2, 0x6666, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtd, 2, 0x660f66, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtd, 2, 0xf66, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddwd, 2, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddwd, 2, 0x660ff5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddwd, 2, 0xff5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhw, 2, 0x66e5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhw, 2, 0x660fe5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhw, 2, 0xfe5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmullw, 2, 0x66d5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmullw, 2, 0x660fd5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmullw, 2, 0xfd5, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +por, 2, 0x66eb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +por, 2, 0x660feb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +por, 2, 0xfeb, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllw, 2, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psllw, 2, 0x66f1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllw, 2, 0x660f71, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psllw, 2, 0x660ff1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllw, 2, 0xf71, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psllw, 2, 0xff1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pslld, 2, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +pslld, 2, 0x66f2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslld, 2, 0x660f72, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +pslld, 2, 0x660ff2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslld, 2, 0xf72, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +pslld, 2, 0xff2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllq, 2, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psllq, 2, 0x66f3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllq, 2, 0x660f73, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psllq, 2, 0x660ff3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllq, 2, 0xf73, 0x6, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psllq, 2, 0xff3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psraw, 2, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psraw, 2, 0x66e1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psraw, 2, 0x660f71, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psraw, 2, 0x660fe1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psraw, 2, 0xf71, 0x4, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psraw, 2, 0xfe1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrad, 2, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrad, 2, 0x66e2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrad, 2, 0x660f72, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrad, 2, 0x660fe2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrad, 2, 0xf72, 0x4, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psrad, 2, 0xfe2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlw, 2, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrlw, 2, 0x66d1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlw, 2, 0x660f71, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrlw, 2, 0x660fd1, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlw, 2, 0xf71, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psrlw, 2, 0xfd1, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrld, 2, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrld, 2, 0x66d2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrld, 2, 0x660f72, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrld, 2, 0x660fd2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrld, 2, 0xf72, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psrld, 2, 0xfd2, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlq, 2, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrlq, 2, 0x66d3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlq, 2, 0x660f73, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrlq, 2, 0x660fd3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlq, 2, 0xf73, 0x2, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX } +psrlq, 2, 0xfd3, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubb, 2, 0x66f8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubb, 2, 0x660ff8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubb, 2, 0xff8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubw, 2, 0x66f9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubw, 2, 0x660ff9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubw, 2, 0xff9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubd, 2, 0x66fa, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubd, 2, 0x660ffa, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubd, 2, 0xffa, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubq, 2, 0x66fb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubq, 2, 0x660ffb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubq, 2, 0xffb, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsb, 2, 0x66e8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsb, 2, 0x660fe8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsb, 2, 0xfe8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsw, 2, 0x66e9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsw, 2, 0x660fe9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsw, 2, 0xfe9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusb, 2, 0x66d8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusb, 2, 0x660fd8, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusb, 2, 0xfd8, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusw, 2, 0x66d9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusw, 2, 0x660fd9, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusw, 2, 0xfd9, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhbw, 2, 0x6668, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhbw, 2, 0x660f68, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhbw, 2, 0xf68, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhwd, 2, 0x6669, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhwd, 2, 0x660f69, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhwd, 2, 0xf69, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhdq, 2, 0x666a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhdq, 2, 0x660f6a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhdq, 2, 0xf6a, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklbw, 2, 0x6660, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklbw, 2, 0x660f60, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklbw, 2, 0xf60, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklwd, 2, 0x6661, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklwd, 2, 0x660f61, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklwd, 2, 0xf61, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckldq, 2, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckldq, 2, 0x660f62, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckldq, 2, 0xf62, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pxor, 2, 0x66ef, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pxor, 2, 0x660fef, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pxor, 2, 0xfef, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } + +// SSE instructions. + +addps, 2, 0x58, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addps, 2, 0xf58, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addss, 2, 0xf358, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addss, 2, 0xf30f58, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnps, 2, 0x55, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnps, 2, 0xf55, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andps, 2, 0x54, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andps, 2, 0xf54, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqps, 2, 0xfc2, 0x0, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqss, 2, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqss, 2, 0xf30fc2, 0x0, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpleps, 2, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpleps, 2, 0xfc2, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpless, 2, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpless, 2, 0xf30fc2, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltps, 2, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltps, 2, 0xfc2, 0x1, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltss, 2, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltss, 2, 0xf30fc2, 0x1, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqps, 2, 0xfc2, 0x4, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqss, 2, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqss, 2, 0xf30fc2, 0x4, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnleps, 2, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnleps, 2, 0xfc2, 0x6, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnless, 2, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnless, 2, 0xf30fc2, 0x6, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltps, 2, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltps, 2, 0xfc2, 0x5, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltss, 2, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltss, 2, 0xf30fc2, 0x5, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordps, 2, 0xfc2, 0x7, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordss, 2, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordss, 2, 0xf30fc2, 0x7, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordps, 2, 0xfc2, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordss, 2, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordss, 2, 0xf30fc2, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpps, 3, 0xc2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpps, 3, 0xfc2, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpss, 3, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpss, 3, 0xf30fc2, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comiss, 2, 0xf2f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpi2ps, 2, 0xf2a, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } +cvtps2pi, 2, 0xf2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2ss, 2, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +divps, 2, 0x5e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divps, 2, 0xf5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divss, 2, 0xf35e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divss, 2, 0xf30f5e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ldmxcsr, 1, 0xfae, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +maskmovq, 2, 0xff7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegMMX } +maxps, 2, 0x5f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxps, 2, 0xf5f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxss, 2, 0xf35f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxss, 2, 0xf30f5f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minps, 2, 0x5d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movaps, 2, 0xf28, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } +movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhps, 2, 0xf17, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlhps, 2, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } +movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlps, 2, 0xf13, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } +movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movss, 2, 0xf310, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } +movss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|RegMem } +movss, 2, 0xf30f10, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movups, 2, 0xf10, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulss, 2, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulss, 2, 0xf30f59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orps, 2, 0x56, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orps, 2, 0xf56, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgb, 2, 0xfe0, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgb, 2, 0x66e0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 } +pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsw, 2, 0x660fee, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxub, 2, 0x66de, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxub, 2, 0x660fde, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxub, 2, 0xfde, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminsw, 2, 0x66ea, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsw, 2, 0x660fea, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsw, 2, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminub, 2, 0x66da, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminub, 2, 0x660fda, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminub, 2, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } +pmovmskb, 2, 0x660fd7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +pmovmskb, 2, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { RegMMX, Reg32|Reg64 } +pmulhuw, 2, 0x66e4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhuw, 2, 0x660fe4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhuw, 2, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +prefetchnta, 1, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht0, 1, 0xf18, 0x1, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht1, 1, 0xf18, 0x2, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht2, 1, 0xf18, 0x3, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +psadbw, 2, 0xff6, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psadbw, 2, 0x66f6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psadbw, 2, 0x660ff6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufw, 3, 0xf70, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +rcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rcpps, 2, 0xf53, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rcpss, 2, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rcpss, 2, 0xf30f53, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtps, 2, 0xf52, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtss, 2, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtss, 2, 0xf30f52, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sfence, 0, 0xfae, 0xf8, 2, CpuSSE|Cpu3dnowA, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 } +shufps, 3, 0xc6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +shufps, 3, 0xfc6, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtps, 2, 0xf51, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtss, 2, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtss, 2, 0xf30f51, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +stmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +stmxcsr, 1, 0xfae, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +subps, 2, 0x5c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subps, 2, 0xf5c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subss, 2, 0xf35c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subss, 2, 0xf30f5c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomiss, 2, 0xf2e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhps, 2, 0x15, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhps, 2, 0xf15, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklps, 2, 0x14, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklps, 2, 0xf14, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorps, 2, 0x57, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorps, 2, 0xf57, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// SSE2 instructions. + +addpd, 2, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addpd, 2, 0x660f58, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsd, 2, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsd, 2, 0xf20f58, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnpd, 2, 0x6655, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnpd, 2, 0x660f55, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andpd, 2, 0x6654, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andpd, 2, 0x660f54, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqpd, 2, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqpd, 2, 0x660fc2, 0x0, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqsd, 2, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqsd, 2, 0xf20fc2, 0x0, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplepd, 2, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplepd, 2, 0x660fc2, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplesd, 2, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplesd, 2, 0xf20fc2, 0x2, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltpd, 2, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltpd, 2, 0x660fc2, 0x1, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltsd, 2, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltsd, 2, 0xf20fc2, 0x1, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqpd, 2, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqpd, 2, 0x660fc2, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqsd, 2, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqsd, 2, 0xf20fc2, 0x4, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlepd, 2, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlepd, 2, 0x660fc2, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlesd, 2, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlesd, 2, 0xf20fc2, 0x6, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltpd, 2, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltpd, 2, 0x660fc2, 0x5, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltsd, 2, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltsd, 2, 0xf20fc2, 0x5, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordpd, 2, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordpd, 2, 0x660fc2, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordsd, 2, 0xf20fc2, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordpd, 2, 0x660fc2, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordsd, 2, 0xf20fc2, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmppd, 3, 0x66c2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmppd, 3, 0x660fc2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +// Intel mode string compare. +cmpsd, 0, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } +cmpsd, 2, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +cmpsd, 3, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpsd, 3, 0xf20fc2, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comisd, 2, 0x660f2f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpi2pd, 2, 0x660f2a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } +cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +divpd, 2, 0x665e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divpd, 2, 0x660f5e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divsd, 2, 0xf25e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divsd, 2, 0xf20f5e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxpd, 2, 0x665f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxpd, 2, 0x660f5f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxsd, 2, 0xf25f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxsd, 2, 0xf20f5f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minpd, 2, 0x665d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movapd, 2, 0x660f28, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movhpd, 2, 0x660f16, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 } +movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// Intel mode string move. +movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 } +movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movsd, 2, 0xf210, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } +movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM|Regmem } +movsd, 2, 0xf20f10, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movupd, 2, 0x660f10, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulsd, 2, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulsd, 2, 0xf20f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orpd, 2, 0x6656, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orpd, 2, 0x660f56, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +shufpd, 3, 0x66c6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +shufpd, 3, 0x660fc6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtpd, 2, 0x660f51, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtsd, 2, 0xf251, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtsd, 2, 0xf20f51, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subpd, 2, 0x665c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subpd, 2, 0x660f5c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subsd, 2, 0xf25c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subsd, 2, 0xf20f5c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomisd, 2, 0x662e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomisd, 2, 0x660f2e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhpd, 2, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhpd, 2, 0x660f15, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklpd, 2, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklpd, 2, 0x660f14, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorpd, 2, 0x6657, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorpd, 2, 0x660f57, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2pd, 2, 0xf30fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2dq, 2, 0xf20fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2ps, 2, 0xf5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2pi, 2, 0x660f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2ps, 2, 0x660f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2pd, 2, 0xf5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2dq, 2, 0x660f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvtsd2si, 2, 0xf20f2d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvtsd2ss, 2, 0xf25a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtsd2ss, 2, 0xf20f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtss2sd, 2, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtss2sd, 2, 0xf30f5a, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttpd2pi, 2, 0x660f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttsd2si, 2, 0xf22c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttsd2si, 2, 0xf20f2c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttpd2dq, 2, 0x660fe6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } +maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +movdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdqa, 2, 0x660f6f, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX } +movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM } +pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufd, 3, 0x660f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufhw, 3, 0xf370, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufhw, 3, 0xf30f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshuflw, 3, 0xf270, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshuflw, 3, 0xf20f70, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslldq, 2, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +pslldq, 2, 0x660f73, 0x7, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +psrldq, 2, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM } +psrldq, 2, 0x660f73, 0x3, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM } +punpckhqdq, 2, 0x666d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhqdq, 2, 0x660f6d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklqdq, 2, 0x666c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklqdq, 2, 0x660f6c, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// SSE3 instructions. + +addsubpd, 2, 0x66d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsubpd, 2, 0x660fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsubps, 2, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsubps, 2, 0xf20fd0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpxchg16b, 1, 0xfc7, 0x1, 2, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX|IsLockable, { Oword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +fisttp, 1, 0xdf, 0x1, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|NoAVX, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisttp, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisttpll, 1, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +haddpd, 2, 0x667c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +haddpd, 2, 0x660f7c, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +haddps, 2, 0xf27c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +haddps, 2, 0xf20f7c, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubpd, 2, 0x667d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubpd, 2, 0x660f7d, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubps, 2, 0xf27d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubps, 2, 0xf20f7d, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +lddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +lddqu, 2, 0xf20ff0, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 } +// monitor is very special. CX and DX are always 64bits with zero upper +// 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The +// address size override prefix can be used to overrride the AX size in +// all modes. +// Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. +monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoAVX, { Reg16|Reg32, Reg32, Reg32 } +// Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. +monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64|NoAVX, { Reg32|Reg64, Reg64, Reg64 } +movddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movshdup, 2, 0xf30f16, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mwait, 0, 0xf01, 0xc9, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { 0 } +// mwait is very special. AX and CX are always 64bits with zero upper +// 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. +// Need to ensure only "mwait %eax,%ecx" is accepted. +mwait, 2, 0xf01, 0xc9, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoAVX, { Reg32, Reg32 } +// Need to ensure only "mwait %rax,%rcx" is accepted. +mwait, 2, 0xf01, 0xc9, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoRex64|NoAVX, { Reg64, Reg64 } + +// VMX instructions. + +vmcall, 0, 0xf01, 0xc1, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmclear, 1, 0x660fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmlaunch, 0, 0xf01, 0xc2, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmresume, 0, 0xf01, 0xc3, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmptrld, 1, 0xfc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmptrst, 1, 0xfc7, 0x7, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmread, 2, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32 } +vmread, 2, 0xf78, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +vmwrite, 2, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32, Reg32 } +vmwrite, 2, 0xf79, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +vmxoff, 0, 0xf01, 0xc4, 2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// SMX instructions. + +getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// EPT instructions. + +invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +invept, 2, 0x660f3880, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } + +// SSSE3 instructions. + +phaddw, 2, 0x6601, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddw, 2, 0x660f3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddw, 2, 0xf3801, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddd, 2, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddd, 2, 0x660f3802, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddd, 2, 0xf3802, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddsw, 2, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddsw, 2, 0x660f3803, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddsw, 2, 0xf3803, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubw, 2, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubw, 2, 0x660f3805, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubw, 2, 0xf3805, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubd, 2, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubd, 2, 0x660f3806, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubd, 2, 0xf3806, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubsw, 2, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubsw, 2, 0x660f3807, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubsw, 2, 0xf3807, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddubsw, 2, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddubsw, 2, 0x660f3804, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddubsw, 2, 0xf3804, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrsw, 2, 0x660b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhrsw, 2, 0x660f380b, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhrsw, 2, 0xf380b, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufb, 2, 0x6600, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufb, 2, 0x660f3800, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufb, 2, 0xf3800, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignb, 2, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignb, 2, 0x660f3808, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignb, 2, 0xf3808, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignw, 2, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignw, 2, 0x660f3809, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignw, 2, 0xf3809, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignd, 2, 0x660a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignd, 2, 0x660f380a, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignd, 2, 0xf380a, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +palignr, 3, 0x660f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +palignr, 3, 0x660f3a0f, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +palignr, 3, 0xf3a0f, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsb, 2, 0x660f381c, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsb, 2, 0xf381c, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsw, 2, 0x660f381d, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsw, 2, 0xf381d, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsd, 2, 0x660f381e, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsd, 2, 0xf381e, None, 3, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } + +// SSE4.1 instructions. + +blendpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendpd, 3, 0x660f3a0d, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendps, 3, 0x660f3a0c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 3, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 2, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 3, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 2, 0x660f3815, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 3, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 2, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 3, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 2, 0x660f3814, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dppd, 3, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dpps, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dpps, 3, 0x660f3a40, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +insertps, 3, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +insertps, 3, 0x660f3a21, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movntdqa, 2, 0x660f382a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +mpsadbw, 3, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mpsadbw, 3, 0x660f3a42, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packusdw, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packusdw, 2, 0x660f382b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 3, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0|VexImmExt|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 2, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|VexImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 3, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FirstXmm0, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 2, 0x660f3810, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendw, 3, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqq, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrd, 3, 0x660f3a16, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +phminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrd, 3, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrd, 3, 0x660f3a22, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrq, 3, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +pinsrq, 3, 0x660f3a22, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +pmaxsb, 2, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsb, 2, 0x660f383c, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsd, 2, 0x663d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsd, 2, 0x660f383d, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxud, 2, 0x663f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxud, 2, 0x660f383f, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxuw, 2, 0x663e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxuw, 2, 0x660f383e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsb, 2, 0x6638, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsb, 2, 0x660f3838, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsd, 2, 0x6639, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsd, 2, 0x660f3839, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminud, 2, 0x663b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminud, 2, 0x660f383b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminuw, 2, 0x663a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminuw, 2, 0x660f383a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbw, 2, 0x660f3820, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbd, 2, 0x660f3821, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbq, 2, 0x660f3822, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwd, 2, 0x660f3823, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwq, 2, 0x660f3824, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxdq, 2, 0x660f3825, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbw, 2, 0x660f3830, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbd, 2, 0x660f3831, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbq, 2, 0x660f3832, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwd, 2, 0x660f3833, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwq, 2, 0x660f3834, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxdq, 2, 0x660f3835, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuldq, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuldq, 2, 0x660f3828, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulld, 2, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulld, 2, 0x660f3840, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ptest, 2, 0x660f3817, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundpd, 3, 0x660f3a09, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundps, 3, 0x660f3a08, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundsd, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundsd, 3, 0x660f3a0b, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundss, 3, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundss, 3, 0x660f3a0a, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// SSE4.2 instructions. + +pcmpgtq, 2, 0x6637, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtq, 2, 0x660f3837, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestri, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestri, 3, 0x660f3a61, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestrm, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestrm, 3, 0x660f3a60, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistri, 3, 0x660f3a63, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistrm, 3, 0x660f3a62, None, 3, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +// We put non-8bit version before 8bit so that crc32 with memory operand +// defaults to non-8bit. +crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64|NoAVX, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } +crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 } + +// xsave/xrstor New Instructions. + +xsave, 1, 0xfae, 0x4, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xsave64, 1, 0xfae, 0x4, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xrstor64, 1, 0xfae, 0x5, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } + +// xsaveopt +xsaveopt, 1, 0xfae, 0x6, 2, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xsaveopt64, 1, 0xfae, 0x6, 2, CpuXsaveopt|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// AES instructions. + +aesdec, 2, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesdec, 2, 0x660f38de, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesdeclast, 2, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesdeclast, 2, 0x660f38df, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenc, 2, 0x66dc, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenc, 2, 0x660f38dc, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenclast, 2, 0x66dd, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesimc, 2, 0x66db, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aeskeygenassist, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// PCLMUL + +pclmulqdq, 3, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqlqdq, 2, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqlqdq, 2, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqhqdq, 2, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqhqdq, 2, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// AVX instructions. + +vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddsd, 3, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddss, 3, 0xf358, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubpd, 3, 0x66d0, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaddsubps, 3, 0xf2d0, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandnpd, 3, 0x6655, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandnps, 3, 0x55, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandpd, 3, 0x6654, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vandps, 3, 0x54, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendpd, 4, 0x660d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendps, 4, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendvpd, 4, 0x664b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexSources=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexSources=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpge_oqsd, 3, 0xf2c2, 0x1d, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpge_oqss, 3, 0xf3c2, 0x1d, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgesd, 3, 0xf2c2, 0xd, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgess, 3, 0xf3c2, 0xd, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgt_oqsd, 3, 0xf2c2, 0x1e, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgt_oqss, 3, 0xf3c2, 0x1e, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpgtsd, 3, 0xf2c2, 0xe, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpgtss, 3, 0xf3c2, 0xe, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmple_oqsd, 3, 0xf2c2, 0x12, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmple_oqss, 3, 0xf3c2, 0x12, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplesd, 3, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpless, 3, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmplt_oqsd, 3, 0xf2c2, 0x11, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmplt_oqss, 3, 0xf3c2, 0x11, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpltsd, 3, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpltss, 3, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngesd, 3, 0xf2c2, 0x9, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngess, 3, 0xf3c2, 0x9, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnge_uqsd, 3, 0xf2c2, 0x19, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnge_uqss, 3, 0xf3c2, 0x19, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngtsd, 3, 0xf2c2, 0xa, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngtss, 3, 0xf3c2, 0xa, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpngt_uqsd, 3, 0xf2c2, 0x1a, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpngt_uqss, 3, 0xf3c2, 0x1a, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlesd, 3, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnless, 3, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnle_uqsd, 3, 0xf2c2, 0x16, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnle_uqss, 3, 0xf3c2, 0x16, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnltsd, 3, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnltss, 3, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpnlt_uqsd, 3, 0xf2c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpnlt_uqss, 3, 0xf3c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpsd, 4, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpss, 4, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcomisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcomiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM } +vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtdq2ps, 2, 0x5b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtps2pd, 2, 0x5a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM } +vcvtsd2si, 2, 0xf22d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvtsd2ss, 3, 0xf25a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtsi2sd, 3, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtsi2ss, 3, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vcvtss2sd, 3, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vcvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Xmmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM } +vcvttpd2dq, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Intelsyntax, { Ymmword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vcvttpd2dqx, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvttpd2dqy, 2, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegXMM } +vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vcvttsd2si, 2, 0xf22c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vcvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivpd, 3, 0x665e, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivps, 3, 0x5e, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vdivsd, 3, 0xf25e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdivss, 3, 0xf35e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhsubpd, 3, 0x667d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vhsubps, 3, 0xf27d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vinsertf128, 4, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM, RegYMM } +vinsertps, 4, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vlddqu, 2, 0xf2f0, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM } +vldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovpd, 3, 0x662f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmaskmovpd, 3, 0x662d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM } +vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovps, 3, 0x662e, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmaskmovps, 3, 0x662c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM, RegYMM } +vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxpd, 3, 0x665f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxps, 3, 0x5f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmaxsd, 3, 0xf25f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmaxss, 3, 0xf35f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminpd, 3, 0x665d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +// vmovd really shouldn't allow for 64bit operand (vmovq is the right +// mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated +// by Intel AVX spec). To avoid extra template in gcc x86 backend and +// support assembler for AMD64, we accept 64bit operand on vmovd so +// that we can use one template for both SSE and AVX instructions. +vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S } +vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovhpd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovhps, 3, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovhps, 2, 0x17, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovlhps, 3, 0x16, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovlpd, 3, 0x6612, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovlpd, 2, 0x6613, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vmovlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vmovmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 } +vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vmovmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegYMM, Reg32|Reg64 } +vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovq, 2, 0xf37e, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM } +vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +vmovsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovsd, 3, 0xf210, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovsd, 3, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem } +vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovshdup, 2, 0xf316, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +vmovss, 3, 0xf310, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovss, 3, 0xf311, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM|RegMem } +vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } +vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulps, 3, 0x59, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vmulsd, 3, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vmulss, 3, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorpd, 3, 0x6656, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vorps, 3, 0x56, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpabsb, 2, 0x661c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpabsd, 2, 0x661e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpabsw, 2, 0x661d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpackssdw, 3, 0x666b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpacksswb, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpackusdw, 3, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpackuswb, 3, 0x6667, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddsb, 3, 0x66ec, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddsw, 3, 0x66ed, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddb, 3, 0x66fc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddd, 3, 0x66fe, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddq, 3, 0x66d4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddw, 3, 0x66fd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddusb, 3, 0x66dc, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpaddusw, 3, 0x66dd, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpalignr, 4, 0x660f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpand, 3, 0x66db, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpandn, 3, 0x66df, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpavgb, 3, 0x66e0, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpavgw, 3, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpblendvb, 4, 0x664c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpblendw, 4, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqb, 3, 0x6674, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqd, 3, 0x6676, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqq, 3, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpeqw, 3, 0x6675, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpestri, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpestrm, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpgtb, 3, 0x6664, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtd, 3, 0x6666, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtq, 3, 0x6637, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpgtw, 3, 0x6665, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S } +vpextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphaddw, 3, 0x6601, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM, RegXMM } +vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsd, 3, 0x663d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxsw, 3, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxub, 3, 0x66de, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxud, 3, 0x663f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmaxuw, 3, 0x663e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsb, 3, 0x6638, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsd, 3, 0x6639, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminsw, 3, 0x66ea, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminub, 3, 0x66da, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminud, 3, 0x663b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpminuw, 3, 0x663a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmovmskb, 2, 0x66d7, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } +vpmovsxbd, 2, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxbq, 2, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxbw, 2, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxdq, 2, 0x6625, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxwd, 2, 0x6623, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovsxwq, 2, 0x6624, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbd, 2, 0x6631, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbq, 2, 0x6632, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxbw, 2, 0x6630, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxdq, 2, 0x6635, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxwd, 2, 0x6633, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmovzxwq, 2, 0x6634, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpmuldq, 3, 0x6628, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhrsw, 3, 0x660b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhuw, 3, 0x66e4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulhw, 3, 0x66e5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmulld, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmullw, 3, 0x66d5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpmuludq, 3, 0x66f4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpor, 3, 0x66eb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsadbw, 3, 0x66f6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpshufb, 3, 0x6600, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpshufd, 3, 0x6670, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpshufhw, 3, 0xf370, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpshuflw, 3, 0xf270, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vpsignb, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsignd, 3, 0x660a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsignw, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpslld, 3, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpslld, 3, 0x66f2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpslldq, 3, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllq, 3, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllq, 3, 0x66f3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsllw, 3, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsllw, 3, 0x66f1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrad, 3, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrad, 3, 0x66e2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsraw, 3, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsraw, 3, 0x66e1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrld, 3, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrld, 3, 0x66d2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrldq, 3, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlq, 3, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlq, 3, 0x66d3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsrlw, 3, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM } +vpsrlw, 3, 0x66d1, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubb, 3, 0x66f8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubd, 3, 0x66fa, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubq, 3, 0x66fb, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubsb, 3, 0x66e8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubsw, 3, 0x66e9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubusb, 3, 0x66d8, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubusw, 3, 0x66d9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpsubw, 3, 0x66f9, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vptest, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vpunpckhbw, 3, 0x6668, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhdq, 3, 0x666a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhqdq, 3, 0x666d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckhwd, 3, 0x6669, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklbw, 3, 0x6660, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpckldq, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklqdq, 3, 0x666c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpunpcklwd, 3, 0x6661, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpxor, 3, 0x66ef, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vrcpps, 2, 0x53, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vrcpss, 3, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vroundpd, 3, 0x6609, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vroundss, 4, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vsqrtps, 2, 0x51, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vsqrtsd, 3, 0xf251, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsqrtss, 3, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vstmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubpd, 3, 0x665c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubps, 3, 0x5c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vsubsd, 3, 0xf25c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vsubss, 3, 0xf35c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vtestpd, 2, 0x660f, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vtestps, 2, 0x660e, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vucomisd, 2, 0x662e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpckhpd, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpckhps, 3, 0x15, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpcklpd, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vunpcklps, 3, 0x14, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vxorpd, 3, 0x6657, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vxorps, 3, 0x57, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vzeroall, 0, 0x77, None, 1, CpuAVX, Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +vzeroupper, 0, 0x77, None, 1, CpuAVX, Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// AES + AVX + +vaesdec, 3, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaesdeclast, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaesenc, 3, 0x66dc, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaesenclast, 3, 0x66dd, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vaesimc, 2, 0x66db, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vaeskeygenassist, 3, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// PCLMUL + AVX + +vpclmulqdq, 4, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpclmullqlqdq, 3, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpclmulhqlqdq, 3, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } + +// FSGSBASE, RDRND and F16C + +rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } +rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } +rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 } +wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } +wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 } +vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegYMM } +vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } + +// FMA instructions + +vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmadd132sd, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd132ss, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213sd, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd213ss, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231sd, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmadd231ss, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsub132sd, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub132ss, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213sd, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub213ss, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231sd, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsub231ss, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmadd132sd, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd132ss, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213sd, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd213ss, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231sd, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmadd231ss, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex=3|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } + +// FMA4 instructions + +vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddpd, 4, 0x6669, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddps, 4, 0x6668, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsd, 4, 0x666b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddss, 4, 0x666a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmaddsubps, 4, 0x665c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubaddps, 4, 0x665e, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubpd, 4, 0x666d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfmsubps, 4, 0x666c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubsd, 4, 0x666f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfmsubss, 4, 0x666e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmaddpd, 4, 0x6679, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmaddps, 4, 0x6678, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddsd, 4, 0x667b, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddss, 4, 0x667a, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmsubpd, 4, 0x667d, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vfnmsubps, 4, 0x667c, None, 1, CpuFMA4, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } + +// XOP instructions +// We add Imm8 to Vex_Imm4. We use Imm8 to indicate that the operand +// is an immediate. We will check if its value will fit 4 bits. + +vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } +vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } +vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { RegYMM, Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM, RegYMM } +vpcomb, 4, 0xcc, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomd, 4, 0xce, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomq, 4, 0xcf, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomub, 4, 0xec, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermil2pd, 5, 0x6649, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=1|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } +vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=1|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } +vpermil2ps, 5, 0x6648, None, 1, CpuXOP, Modrm|VexOpcode=2|VexVVVV=1|VexW=2|Vex=2|VexSources=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, { Imm8|Vec_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM } +vpcomltb, 3, 0xcc, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltd, 3, 0xce, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltq, 3, 0xcf, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltub, 3, 0xec, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltud, 3, 0xee, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltuq, 3, 0xef, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltuw, 3, 0xed, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomltw, 3, 0xcd, 0x0, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleb, 3, 0xcc, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomled, 3, 0xce, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleq, 3, 0xcf, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleub, 3, 0xec, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleud, 3, 0xee, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleuq, 3, 0xef, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomleuw, 3, 0xed, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomlew, 3, 0xcd, 0x1, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtb, 3, 0xcc, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtd, 3, 0xce, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtq, 3, 0xcf, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtub, 3, 0xec, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtud, 3, 0xee, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtuq, 3, 0xef, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtuw, 3, 0xed, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgtw, 3, 0xcd, 0x2, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeb, 3, 0xcc, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomged, 3, 0xce, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeq, 3, 0xcf, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeub, 3, 0xec, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeud, 3, 0xee, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeuq, 3, 0xef, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgeuw, 3, 0xed, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomgew, 3, 0xcd, 0x3, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomeqb, 3, 0xcc, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomeqd, 3, 0xce, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomeqq, 3, 0xcf, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomequb, 3, 0xec, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomequd, 3, 0xee, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomequq, 3, 0xef, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomequw, 3, 0xed, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomeqw, 3, 0xcd, 0x4, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomneqb, 3, 0xcc, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomneqd, 3, 0xce, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomneqq, 3, 0xcf, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomnequb, 3, 0xec, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomnequd, 3, 0xee, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomnequq, 3, 0xef, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomnequw, 3, 0xed, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomneqw, 3, 0xcd, 0x5, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseb, 3, 0xcc, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalsed, 3, 0xce, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseq, 3, 0xcf, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseub, 3, 0xec, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseud, 3, 0xee, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseuq, 3, 0xef, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalseuw, 3, 0xed, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomfalsew, 3, 0xcd, 0x6, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueb, 3, 0xcc, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrued, 3, 0xce, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueq, 3, 0xcf, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueub, 3, 0xec, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueud, 3, 0xee, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueuq, 3, 0xef, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtrueuw, 3, 0xed, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomtruew, 3, 0xcd, 0x7, 1, CpuXOP, Modrm|VexOpcode=3|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex|ImmExt, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vphaddbd, 2, 0xc2, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddbq, 2, 0xc3, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddbw, 2, 0xc1, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadddq, 2, 0xcb, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubd, 2, 0xd2, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubq, 2, 0xd3, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubw, 2, 0xd1, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddudq, 2, 0xdb, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadduwd, 2, 0xd6, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadduwq, 2, 0xd7, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddwd, 2, 0xc6, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddwq, 2, 0xc7, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubbw, 2, 0xe1, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubdq, 2, 0xe3, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubwd, 2, 0xe2, None, 1, CpuXOP, Modrm|VexOpcode=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpmacsdd, 4, 0x9e, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 4, 0x9f, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 4, 0x97, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 4, 0x8e, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 4, 0x8f, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 4, 0x87, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 4, 0x86, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 4, 0x85, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 4, 0x96, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 4, 0x95, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 4, 0xa6, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 4, 0xb6, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexSources=2|VexImmExt|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM, RegXMM } +vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotb, 3, 0xc0, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotd, 3, 0xc2, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotq, 3, 0xc3, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotw, 3, 0xc1, None, 1, CpuXOP, Modrm|VexOpcode=3|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|VexOpcode=4|VexW=2|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } + +// LWP instructions + +llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg32 } +llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|Vex, { Reg64 } +slwpcb, 1, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg32 } +slwpcb, 1, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=4|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|Vex, { Reg64 } +lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 } +lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 } +lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 } +lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 } + +// BMI instructions + +andn, 3, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64, Reg32|Reg64 } +bextr, 3, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +blsi, 2, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// TBM instructions +bextr, 3, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } +tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 } + +// AMD 3DNow! instructions. + +prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +femms, 0, 0xf0e, None, 2, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +pavgusb, 2, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pf2id, 2, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pf2iw, 2, 0xf0f, 0x1c, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfacc, 2, 0xf0f, 0xae, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfadd, 2, 0xf0f, 0x9e, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpeq, 2, 0xf0f, 0xb0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpge, 2, 0xf0f, 0x90, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpgt, 2, 0xf0f, 0xa0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmax, 2, 0xf0f, 0xa4, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmin, 2, 0xf0f, 0x94, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmul, 2, 0xf0f, 0xb4, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfnacc, 2, 0xf0f, 0x8a, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfpnacc, 2, 0xf0f, 0x8e, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcp, 2, 0xf0f, 0x96, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcpit1, 2, 0xf0f, 0xa6, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcpit2, 2, 0xf0f, 0xb6, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrsqit1, 2, 0xf0f, 0xa7, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrsqrt, 2, 0xf0f, 0x97, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfsub, 2, 0xf0f, 0x9a, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfsubr, 2, 0xf0f, 0xaa, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pi2fd, 2, 0xf0f, 0xd, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pi2fw, 2, 0xf0f, 0xc, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrw, 2, 0xf0f, 0xb7, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } + +// AMD extensions. +syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +syscall, 0, 0xf05, None, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 } +sysret, 0, 0xf07, None, 2, Cpu64, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 } +swapgs, 0, 0xf01, 0xf8, 2, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +rdtscp, 0, 0xf01, 0xf9, 2, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } + +// AMD Pacifica additions. +clgi, 0, 0xf01, 0xdd, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +invlpga, 0, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// FIXME: Need to ensure only "invlpga %[re]ax,%ecx" is accepted. +invlpga, 2, 0xf01, 0xdf, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg32 } +skinit, 0, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// FIXME: Need to ensure only "skinit %eax" is accepted. +skinit, 1, 0xf01, 0xde, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Reg32 } +stgi, 0, 0xf01, 0xdc, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmload, 0, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// FIXME: Need to ensure only "vmload %[re]ax" is accepted. +vmload, 1, 0xf01, 0xda, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +vmmcall, 0, 0xf01, 0xd9, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +vmrun, 0, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// FIXME: Need to ensure only "vmrun %[re]ax" is accepted. +vmrun, 1, 0xf01, 0xd8, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } +vmsave, 0, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 } +// FIXME: Need to ensure only "vmsave %[re]ax" is accepted. +vmsave, 1, 0xf01, 0xdb, 2, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64 } + + +// SSE4a instructions +movntsd, 2, 0xf20f2b, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntss, 2, 0xf30f2b, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +extrq, 3, 0x660f78, 0x0, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM } +extrq, 2, 0x660f79, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +insertq, 2, 0xf20f79, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } +insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM } + +// ABM instructions +popcnt, 2, 0xf30fb8, None, 2, CpuABM|CpuSSE4_2, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|NoAVX, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lzcnt, 2, 0xf30fbd, None, 2, CpuABM, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// VIA PadLock extensions. +xstore-rng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcrypt-ecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcrypt-cbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcrypt-ctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcrypt-cfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcrypt-ofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +montmul, 0, 0xf30fa6, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xsha1, 0, 0xf30fa6, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xsha256, 0, 0xf30fa6, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +// Aliases without hyphens. +xstorerng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcryptecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcryptcbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcryptctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcryptcfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +xcryptofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } +// Alias for xstore-rng. +xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|ImmExt, { 0 } diff --git a/external/gpl3/gdb/dist/opcodes/i386-reg.tbl b/external/gpl3/gdb/dist/opcodes/i386-reg.tbl new file mode 100644 index 000000000000..8c5b5d1faf53 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-reg.tbl @@ -0,0 +1,243 @@ +// i386 register table. +// Copyright 2007, 2008 +// Free Software Foundation, Inc. +// +// This file is part of the GNU opcodes library. +// +// This library is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 3, or (at your option) +// any later version. +// +// It is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +// License for more details. +// +// You should have received a copy of the GNU General Public License +// along with GAS; see the file COPYING. If not, write to the Free +// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA +// 02110-1301, USA. + +// Make %st first as we test for it. +st, FloatReg|FloatAcc, 0, 0, 11, 33 +// 8 bit regs +al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval +cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval +dl, Reg8, 0, 2, Dw2Inval, Dw2Inval +bl, Reg8, 0, 3, Dw2Inval, Dw2Inval +ah, Reg8, 0, 4, Dw2Inval, Dw2Inval +ch, Reg8, 0, 5, Dw2Inval, Dw2Inval +dh, Reg8, 0, 6, Dw2Inval, Dw2Inval +bh, Reg8, 0, 7, Dw2Inval, Dw2Inval +axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval +dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval +bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval +spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval +bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval +sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval +dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval +r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval +r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval +r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval +r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval +r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval +r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval +r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval +r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval +// 16 bit regs +ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval +cx, Reg16, 0, 1, Dw2Inval, Dw2Inval +dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval +bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval +sp, Reg16, 0, 4, Dw2Inval, Dw2Inval +bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval +si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval +di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval +r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval +r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval +r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval +r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval +r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval +r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval +r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval +r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval +// 32 bit regs +eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval +ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval +edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval +ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval +esp, Reg32, 0, 4, 4, Dw2Inval +ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval +esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval +edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval +r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval +r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval +r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval +r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval +r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval +r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval +r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval +r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval +rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0 +rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 +rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 +rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 +rsp, Reg64, 0, 4, Dw2Inval, 7 +rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 +rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 +rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 +r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 +r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 +r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 +r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 +r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 +r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 +r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 +r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 +// Segment registers. +es, SReg2, 0, 0, 40, 50 +cs, SReg2, 0, 1, 41, 51 +ss, SReg2, 0, 2, 42, 52 +ds, SReg2, 0, 3, 43, 53 +fs, SReg3, 0, 4, 44, 54 +gs, SReg3, 0, 5, 45, 55 +flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval +// Control registers. +cr0, Control, 0, 0, Dw2Inval, Dw2Inval +cr1, Control, 0, 1, Dw2Inval, Dw2Inval +cr2, Control, 0, 2, Dw2Inval, Dw2Inval +cr3, Control, 0, 3, Dw2Inval, Dw2Inval +cr4, Control, 0, 4, Dw2Inval, Dw2Inval +cr5, Control, 0, 5, Dw2Inval, Dw2Inval +cr6, Control, 0, 6, Dw2Inval, Dw2Inval +cr7, Control, 0, 7, Dw2Inval, Dw2Inval +cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval +cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval +cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval +cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval +cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval +cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval +cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval +cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval +// Debug registers. +db0, Debug, 0, 0, Dw2Inval, Dw2Inval +db1, Debug, 0, 1, Dw2Inval, Dw2Inval +db2, Debug, 0, 2, Dw2Inval, Dw2Inval +db3, Debug, 0, 3, Dw2Inval, Dw2Inval +db4, Debug, 0, 4, Dw2Inval, Dw2Inval +db5, Debug, 0, 5, Dw2Inval, Dw2Inval +db6, Debug, 0, 6, Dw2Inval, Dw2Inval +db7, Debug, 0, 7, Dw2Inval, Dw2Inval +db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval +db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval +db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval +db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval +db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval +db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval +db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval +db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval +dr0, Debug, 0, 0, Dw2Inval, Dw2Inval +dr1, Debug, 0, 1, Dw2Inval, Dw2Inval +dr2, Debug, 0, 2, Dw2Inval, Dw2Inval +dr3, Debug, 0, 3, Dw2Inval, Dw2Inval +dr4, Debug, 0, 4, Dw2Inval, Dw2Inval +dr5, Debug, 0, 5, Dw2Inval, Dw2Inval +dr6, Debug, 0, 6, Dw2Inval, Dw2Inval +dr7, Debug, 0, 7, Dw2Inval, Dw2Inval +dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval +dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval +dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval +dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval +dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval +dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval +dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval +dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval +// Test registers. +tr0, Test, 0, 0, Dw2Inval, Dw2Inval +tr1, Test, 0, 1, Dw2Inval, Dw2Inval +tr2, Test, 0, 2, Dw2Inval, Dw2Inval +tr3, Test, 0, 3, Dw2Inval, Dw2Inval +tr4, Test, 0, 4, Dw2Inval, Dw2Inval +tr5, Test, 0, 5, Dw2Inval, Dw2Inval +tr6, Test, 0, 6, Dw2Inval, Dw2Inval +tr7, Test, 0, 7, Dw2Inval, Dw2Inval +// MMX and simd registers. +mm0, RegMMX, 0, 0, 29, 41 +mm1, RegMMX, 0, 1, 30, 42 +mm2, RegMMX, 0, 2, 31, 43 +mm3, RegMMX, 0, 3, 32, 44 +mm4, RegMMX, 0, 4, 33, 45 +mm5, RegMMX, 0, 5, 34, 46 +mm6, RegMMX, 0, 6, 35, 47 +mm7, RegMMX, 0, 7, 36, 48 +xmm0, RegXMM, 0, 0, 21, 17 +xmm1, RegXMM, 0, 1, 22, 18 +xmm2, RegXMM, 0, 2, 23, 19 +xmm3, RegXMM, 0, 3, 24, 20 +xmm4, RegXMM, 0, 4, 25, 21 +xmm5, RegXMM, 0, 5, 26, 22 +xmm6, RegXMM, 0, 6, 27, 23 +xmm7, RegXMM, 0, 7, 28, 24 +xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 +xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 +xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 +xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 +xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 +xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 +xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 +xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 +// AVX registers. +ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval +ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval +ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval +ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval +ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval +ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval +ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval +ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval +ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval +ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval +ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval +ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval +ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval +ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval +ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval +ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval +// No type will make these registers rejected for all purposes except +// for addressing. This saves creating one extra type for RIP/EIP. +rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 +eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval +// No type will make these registers rejected for all purposes except +// for addressing. +eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval +riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval +// fp regs. +st(0), FloatReg|FloatAcc, 0, 0, 11, 33 +st(1), FloatReg, 0, 1, 12, 34 +st(2), FloatReg, 0, 2, 13, 35 +st(3), FloatReg, 0, 3, 14, 36 +st(4), FloatReg, 0, 4, 15, 37 +st(5), FloatReg, 0, 5, 16, 38 +st(6), FloatReg, 0, 6, 17, 39 +st(7), FloatReg, 0, 7, 18, 40 +// Pseudo-register names only used in .cfi_* directives +eflags, 0, 0, 0, 9, 49 +rflags, 0, 0, 0, Dw2Inval, 49 +fs.base, 0, 0, 0, Dw2Inval, 58 +gs.base, 0, 0, 0, Dw2Inval, 59 +tr, 0, 0, 0, 48, 62 +ldtr, 0, 0, 0, 49, 63 +// st0...7 for backward compatibility +st0, 0, 0, 0, 11, 33 +st1, 0, 0, 1, 12, 34 +st2, 0, 0, 2, 13, 35 +st3, 0, 0, 3, 14, 36 +st4, 0, 0, 4, 15, 37 +st5, 0, 0, 5, 16, 38 +st6, 0, 0, 6, 17, 39 +st7, 0, 0, 7, 18, 40 +fcw, 0, 0, 0, 37, 65 +fsw, 0, 0, 0, 38, 66 +mxcsr, 0, 0, 0, 39, 64 diff --git a/external/gpl3/gdb/dist/opcodes/i386-tbl.h b/external/gpl3/gdb/dist/opcodes/i386-tbl.h new file mode 100644 index 000000000000..c86f77d9e38f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i386-tbl.h @@ -0,0 +1,34751 @@ +/* This file is automatically generated by i386-gen. Do not edit! */ +/* Copyright 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* i386 opcode table. */ + +const insn_template i386_optab[] = +{ + { "mov", 2, 0xa0, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, + { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0xa0, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, + { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0x88, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } } } }, + { "mov", 2, 0xb0, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0xc6, 0x0, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } } } }, + { "mov", 2, 0xb0, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, + { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0x8c, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0x8c, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } } } }, + { "mov", 2, 0x8c, None, 1, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "mov", 2, 0x8c, None, 1, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0 } } } 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0x80, 0x1, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } } } }, + { "xor", 2, 0x30, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 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0x34, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xor", 2, 0x80, 0x6, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 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None, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "fsin", 0, 0xd9fe, None, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 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0xf30fa7, 0xe0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "montmul", 0, 0xf30fa6, 0xc0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xsha1", 0, 0xf30fa6, 0xc8, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcryptecb", 0, 0xf30fa7, 0xc8, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcryptcbc", 0, 0xf30fa7, 0xd0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcryptctr", 0, 0xf30fa7, 0xd8, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcryptcfb", 0, 0xf30fa7, 0xe0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xcryptofb", 0, 0xf30fa7, 0xe8, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { "xstore", 0, 0xfa7, 0xc0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, + 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } }, + { NULL, 0, 0, 0, 0, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } } } } +}; + +/* i386 register table. */ + +const reg_entry i386_regtab[] = +{ + { "st", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 11, 33 } }, + { "al", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "cl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "dl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "bl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "ah", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "ch", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "dh", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "bh", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "axl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 0, { Dw2Inval, Dw2Inval } }, + { "cxl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 1, { Dw2Inval, Dw2Inval } }, + { "dxl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 2, { Dw2Inval, Dw2Inval } }, + { "bxl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 3, { Dw2Inval, Dw2Inval } }, + { "spl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 4, { Dw2Inval, Dw2Inval } }, + { "bpl", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 5, { Dw2Inval, Dw2Inval } }, + { "sil", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 6, { Dw2Inval, Dw2Inval } }, + { "dil", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, 7, { Dw2Inval, Dw2Inval } }, + { "r8b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 0, { Dw2Inval, Dw2Inval } }, + { "r9b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 1, { Dw2Inval, Dw2Inval } }, + { "r10b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 2, { Dw2Inval, Dw2Inval } }, + { "r11b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 3, { Dw2Inval, Dw2Inval } }, + { "r12b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 4, { Dw2Inval, Dw2Inval } }, + { "r13b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 5, { Dw2Inval, Dw2Inval } }, + { "r14b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 6, { Dw2Inval, Dw2Inval } }, + { "r15b", + { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex|RegRex64, 7, { Dw2Inval, Dw2Inval } }, + { "ax", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "cx", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "dx", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "bx", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "sp", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "bp", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "si", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "di", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "r8w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "r9w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "r10w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "r11w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "r12w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "r13w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "r14w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "r15w", + { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "eax", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 0, Dw2Inval } }, + { "ecx", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 1, Dw2Inval } }, + { "edx", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 2, Dw2Inval } }, + { "ebx", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 3, Dw2Inval } }, + { "esp", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 4, Dw2Inval } }, + { "ebp", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 5, Dw2Inval } }, + { "esi", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 6, Dw2Inval } }, + { "edi", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 7, Dw2Inval } }, + { "r8d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "r9d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "r10d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "r11d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "r12d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "r13d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "r14d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "r15d", + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "rax", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, 0 } }, + { "rcx", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, 2 } }, + { "rdx", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, 1 } }, + { "rbx", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, 3 } }, + { "rsp", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, 7 } }, + { "rbp", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, 6 } }, + { "rsi", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, 4 } }, + { "rdi", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, 5 } }, + { "r8", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, 8 } }, + { "r9", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, 9 } }, + { "r10", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, 10 } }, + { "r11", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, 11 } }, + { "r12", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, 12 } }, + { "r13", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, 13 } }, + { "r14", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, 14 } }, + { "r15", + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, 15 } }, + { "es", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 40, 50 } }, + { "cs", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 41, 51 } }, + { "ss", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 42, 52 } }, + { "ds", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 43, 53 } }, + { "fs", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 44, 54 } }, + { "gs", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 45, 55 } }, + { "flat", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, RegFlat, { Dw2Inval, Dw2Inval } }, + { "cr0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "cr1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "cr2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "cr3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "cr4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "cr5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "cr6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "cr7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "cr8", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "cr9", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "cr10", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "cr11", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "cr12", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "cr13", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "cr14", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "cr15", + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "db0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "db1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "db2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "db3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "db4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "db5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "db6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "db7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "db8", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "db9", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "db10", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "db11", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "db12", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "db13", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "db14", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "db15", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "dr0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "dr1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "dr2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "dr3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "dr4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "dr5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "dr6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "dr7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "dr8", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "dr9", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "dr10", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "dr11", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "dr12", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "dr13", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "dr14", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "dr15", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "tr0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "tr1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "tr2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "tr3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "tr4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "tr5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "tr6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "tr7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "mm0", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 29, 41 } }, + { "mm1", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 30, 42 } }, + { "mm2", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 31, 43 } }, + { "mm3", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 32, 44 } }, + { "mm4", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 33, 45 } }, + { "mm5", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 34, 46 } }, + { "mm6", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 35, 47 } }, + { "mm7", + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 36, 48 } }, + { "xmm0", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 21, 17 } }, + { "xmm1", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 22, 18 } }, + { "xmm2", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 23, 19 } }, + { "xmm3", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 24, 20 } }, + { "xmm4", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 25, 21 } }, + { "xmm5", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 26, 22 } }, + { "xmm6", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 27, 23 } }, + { "xmm7", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 28, 24 } }, + { "xmm8", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, 25 } }, + { "xmm9", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, 26 } }, + { "xmm10", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, 27 } }, + { "xmm11", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, 28 } }, + { "xmm12", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, 29 } }, + { "xmm13", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, 30 } }, + { "xmm14", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, 31 } }, + { "xmm15", + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, 32 } }, + { "ymm0", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, Dw2Inval } }, + { "ymm1", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { Dw2Inval, Dw2Inval } }, + { "ymm2", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { Dw2Inval, Dw2Inval } }, + { "ymm3", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { Dw2Inval, Dw2Inval } }, + { "ymm4", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { Dw2Inval, Dw2Inval } }, + { "ymm5", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { Dw2Inval, Dw2Inval } }, + { "ymm6", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { Dw2Inval, Dw2Inval } }, + { "ymm7", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { Dw2Inval, Dw2Inval } }, + { "ymm8", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 0, { Dw2Inval, Dw2Inval } }, + { "ymm9", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 1, { Dw2Inval, Dw2Inval } }, + { "ymm10", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 2, { Dw2Inval, Dw2Inval } }, + { "ymm11", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 3, { Dw2Inval, Dw2Inval } }, + { "ymm12", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 4, { Dw2Inval, Dw2Inval } }, + { "ymm13", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 5, { Dw2Inval, Dw2Inval } }, + { "ymm14", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 6, { Dw2Inval, Dw2Inval } }, + { "ymm15", + { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex, 7, { Dw2Inval, Dw2Inval } }, + { "rip", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, RegRip, { Dw2Inval, 16 } }, + { "eip", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + RegRex64, RegEip, { 8, Dw2Inval } }, + { "eiz", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, RegEiz, { Dw2Inval, Dw2Inval } }, + { "riz", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, RegRiz, { Dw2Inval, Dw2Inval } }, + { "st(0)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 11, 33 } }, + { "st(1)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 12, 34 } }, + { "st(2)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 13, 35 } }, + { "st(3)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 14, 36 } }, + { "st(4)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 15, 37 } }, + { "st(5)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 16, 38 } }, + { "st(6)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 17, 39 } }, + { "st(7)", + { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 18, 40 } }, + { "eflags", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 9, 49 } }, + { "rflags", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, 49 } }, + { "fs.base", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, 58 } }, + { "gs.base", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { Dw2Inval, 59 } }, + { "tr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 48, 62 } }, + { "ldtr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 49, 63 } }, + { "st0", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 11, 33 } }, + { "st1", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 1, { 12, 34 } }, + { "st2", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 2, { 13, 35 } }, + { "st3", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 3, { 14, 36 } }, + { "st4", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 4, { 15, 37 } }, + { "st5", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 5, { 16, 38 } }, + { "st6", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 6, { 17, 39 } }, + { "st7", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 7, { 18, 40 } }, + { "fcw", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 37, 65 } }, + { "fsw", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 38, 66 } }, + { "mxcsr", + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + 0, 0, { 39, 64 } }, +}; + +const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab); diff --git a/external/gpl3/gdb/dist/opcodes/i860-dis.c b/external/gpl3/gdb/dist/opcodes/i860-dis.c new file mode 100644 index 000000000000..65b74afb52e8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i860-dis.c @@ -0,0 +1,285 @@ +/* Disassembler for the i860. + Copyright 2000, 2003, 2005, 2007 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt . + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "dis-asm.h" +#include "opcode/i860.h" + +/* Later we should probably choose the prefix based on which OS flavor. */ +#define I860_REG_PREFIX "%" + +/* Integer register names (encoded as 0..31 in the instruction). */ +static const char *const grnames[] = + {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; + +/* FP register names (encoded as 0..31 in the instruction). */ +static const char *const frnames[] = + {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; + +/* Control/status register names (encoded as 0..11 in the instruction). + Registers bear, ccr, p0, p1, p2 and p3 are XP only. */ +static const char *const crnames[] = + {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr", + "p0", "p1", "p2", "p3", "--", "--", "--", "--" }; + + + +/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */ +#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \ + || (op) == 0x34 || (op) == 0x35 \ + || (op) == 0x38 || (op) == 0x39 \ + || (op) == 0x3c || (op) == 0x3d \ + || (op) == 0x33 || (op) == 0x37 \ + || (op) == 0x3b || (op) == 0x3f) + + +/* Sign extend N-bit number. */ +static int +sign_ext (unsigned int x, int n) +{ + int t; + t = x >> (n - 1); + t = ((-t) << n) | x; + return t; +} + + +/* Print a PC-relative branch offset. VAL is the sign extended value + from the branch instruction. */ +static void +print_br_address (disassemble_info *info, bfd_vma memaddr, long val) +{ + + long adj = (long)memaddr + 4 + (val << 2); + + (*info->fprintf_func) (info->stream, "0x%08lx", adj); + + /* Attempt to obtain a symbol for the target address. */ + + if (info->print_address_func && adj != 0) + { + (*info->fprintf_func) (info->stream, "\t// "); + (*info->print_address_func) (adj, info); + } +} + + +/* Print one instruction. */ +int +print_insn_i860 (bfd_vma memaddr, disassemble_info *info) +{ + bfd_byte buff[4]; + unsigned int insn, i; + int status; + const struct i860_opcode *opcode = 0; + + status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Note that i860 instructions are always accessed as little endian + data, regardless of the endian mode of the i860. */ + insn = bfd_getl32 (buff); + + status = 0; + i = 0; + while (i860_opcodes[i].name != NULL) + { + opcode = &i860_opcodes[i]; + if ((insn & opcode->match) == opcode->match + && (insn & opcode->lose) == 0) + { + status = 1; + break; + } + ++i; + } + + if (status == 0) + { + /* Instruction not in opcode table. */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + } + else + { + const char *s; + int val; + + /* If this a flop (or a shrd) and its dual bit is set, + prefix with 'd.'. */ + if (((insn & 0xfc000000) == 0x48000000 + || (insn & 0xfc000000) == 0xb0000000) + && (insn & 0x200)) + (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + + for (s = opcode->args; *s; s++) + { + switch (*s) + { + /* Integer register (src1). */ + case '1': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 11) & 0x1f]); + break; + + /* Integer register (src2). */ + case '2': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 21) & 0x1f]); + break; + + /* Integer destination register. */ + case 'd': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 16) & 0x1f]); + break; + + /* Floating-point register (src1). */ + case 'e': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 11) & 0x1f]); + break; + + /* Floating-point register (src2). */ + case 'f': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 21) & 0x1f]); + break; + + /* Floating-point destination register. */ + case 'g': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 16) & 0x1f]); + break; + + /* Control register. */ + case 'c': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + crnames[(insn >> 21) & 0xf]); + break; + + /* 16-bit immediate (sign extend, except for bitwise ops). */ + case 'i': + if (BITWISE_OP ((insn & 0xfc000000) >> 26)) + (*info->fprintf_func) (info->stream, "0x%04x", + (unsigned int) (insn & 0xffff)); + else + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^0, ld.b). */ + case 'I': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^1, ld.s). */ + case 'J': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffe), 16)); + break; + + /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */ + case 'K': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffc), 16)); + break; + + /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */ + case 'L': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff8), 16)); + break; + + /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */ + case 'M': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff0), 16)); + break; + + /* 5-bit immediate (zero extend). */ + case '5': + (*info->fprintf_func) (info->stream, "%d", + ((insn >> 11) & 0x1f)); + break; + + /* Split 16 bit immediate (20..16:10..0). */ + case 's': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^0, st.b). */ + case 'S': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^1, st.s). */ + case 'T': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fe); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^2, st.l). */ + case 'U': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fc); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* 26-bit PC relative immediate (lbroff). */ + case 'l': + val = sign_ext ((insn & 0x03ffffff), 26); + print_br_address (info, memaddr, val); + break; + + /* 16-bit PC relative immediate (sbroff). */ + case 'r': + val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); + print_br_address (info, memaddr, val); + break; + + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + } + + return sizeof (insn); +} + diff --git a/external/gpl3/gdb/dist/opcodes/i960-dis.c b/external/gpl3/gdb/dist/opcodes/i960-dis.c new file mode 100644 index 000000000000..53d723cc12c6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/i960-dis.c @@ -0,0 +1,933 @@ +/* Disassemble i80960 instructions. + Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2003, + 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +static const char *const reg_names[] = { +/* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7", +/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", +/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", +/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", +/* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3" +}; + + +static FILE *stream; /* Output goes here */ +static struct disassemble_info *info; +static void print_addr (bfd_vma); +static void ctrl (bfd_vma, unsigned long, unsigned long); +static void cobr (bfd_vma, unsigned long, unsigned long); +static void reg (unsigned long); +static int mem (bfd_vma, unsigned long, unsigned long, int); +static void ea (bfd_vma, int, const char *, const char *, int, unsigned int); +static void dstop (int, int, int); +static void regop (int, int, int, int); +static void invalid (int); +static int pinsn (bfd_vma, unsigned long, unsigned long); +static void put_abs (unsigned long, unsigned long); + + +/* Print the i960 instruction at address 'memaddr' in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_i960 (bfd_vma memaddr, struct disassemble_info *info_arg) +{ + unsigned int word1, word2 = 0xdeadbeef; + bfd_byte buffer[8]; + int status; + + info = info_arg; + stream = info->stream; + + /* Read word1. Only read word2 if the instruction + needs it, to prevent reading past the end of a section. */ + + status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + word1 = bfd_getl32 (buffer); + + /* Divide instruction set into classes based on high 4 bits of opcode. */ + switch ( (word1 >> 28) & 0xf ) + { + default: + break; + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + /* Read word2. */ + status = (*info->read_memory_func) + (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + word2 = bfd_getl32 (buffer + 4); + break; + } + + return pinsn( memaddr, word1, word2 ); +} + +#define IN_GDB + +/***************************************************************************** + * All code below this point should be identical with that of + * the disassembler in gdmp960. + + A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it + just ain't so. -kingdon, 31 Mar 93 + *****************************************************************************/ + +struct tabent { + char *name; + short numops; +}; + +struct sparse_tabent { + int opcode; + char *name; + short numops; +}; + +static int +pinsn (bfd_vma memaddr, unsigned long word1, unsigned long word2) +{ + int instr_len; + + instr_len = 4; + put_abs (word1, word2); + + /* Divide instruction set into classes based on high 4 bits of opcode. */ + switch ((word1 >> 28) & 0xf) + { + case 0x0: + case 0x1: + ctrl (memaddr, word1, word2); + break; + case 0x2: + case 0x3: + cobr (memaddr, word1, word2); + break; + case 0x5: + case 0x6: + case 0x7: + reg (word1); + break; + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + instr_len = mem (memaddr, word1, word2, 0); + break; + default: + /* Invalid instruction, print as data word. */ + invalid (word1); + break; + } + return instr_len; +} + +/* CTRL format.. */ + +static void +ctrl (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) +{ + int i; + static const struct tabent ctrl_tab[] = { + { NULL, 0, }, /* 0x00 */ + { NULL, 0, }, /* 0x01 */ + { NULL, 0, }, /* 0x02 */ + { NULL, 0, }, /* 0x03 */ + { NULL, 0, }, /* 0x04 */ + { NULL, 0, }, /* 0x05 */ + { NULL, 0, }, /* 0x06 */ + { NULL, 0, }, /* 0x07 */ + { "b", 1, }, /* 0x08 */ + { "call", 1, }, /* 0x09 */ + { "ret", 0, }, /* 0x0a */ + { "bal", 1, }, /* 0x0b */ + { NULL, 0, }, /* 0x0c */ + { NULL, 0, }, /* 0x0d */ + { NULL, 0, }, /* 0x0e */ + { NULL, 0, }, /* 0x0f */ + { "bno", 1, }, /* 0x10 */ + { "bg", 1, }, /* 0x11 */ + { "be", 1, }, /* 0x12 */ + { "bge", 1, }, /* 0x13 */ + { "bl", 1, }, /* 0x14 */ + { "bne", 1, }, /* 0x15 */ + { "ble", 1, }, /* 0x16 */ + { "bo", 1, }, /* 0x17 */ + { "faultno", 0, }, /* 0x18 */ + { "faultg", 0, }, /* 0x19 */ + { "faulte", 0, }, /* 0x1a */ + { "faultge", 0, }, /* 0x1b */ + { "faultl", 0, }, /* 0x1c */ + { "faultne", 0, }, /* 0x1d */ + { "faultle", 0, }, /* 0x1e */ + { "faulto", 0, }, /* 0x1f */ + }; + + i = (word1 >> 24) & 0xff; + if ((ctrl_tab[i].name == NULL) || ((word1 & 1) != 0)) + { + invalid (word1); + return; + } + + (*info->fprintf_func) (stream, ctrl_tab[i].name); + if (word1 & 2) + /* Predicts branch not taken. */ + (*info->fprintf_func) (stream, ".f"); + + if (ctrl_tab[i].numops == 1) + { + /* Extract displacement and convert to address. */ + word1 &= 0x00ffffff; + + if (word1 & 0x00800000) + { + /* Sign bit is set. */ + word1 |= (-1 & ~0xffffff); /* Sign extend. */ + } + + (*info->fprintf_func) (stream, "\t"); + print_addr (word1 + memaddr); + } +} + +/* COBR format. */ + +static void +cobr (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) +{ + int src1; + int src2; + int i; + + static const struct tabent cobr_tab[] = { + { "testno", 1, }, /* 0x20 */ + { "testg", 1, }, /* 0x21 */ + { "teste", 1, }, /* 0x22 */ + { "testge", 1, }, /* 0x23 */ + { "testl", 1, }, /* 0x24 */ + { "testne", 1, }, /* 0x25 */ + { "testle", 1, }, /* 0x26 */ + { "testo", 1, }, /* 0x27 */ + { NULL, 0, }, /* 0x28 */ + { NULL, 0, }, /* 0x29 */ + { NULL, 0, }, /* 0x2a */ + { NULL, 0, }, /* 0x2b */ + { NULL, 0, }, /* 0x2c */ + { NULL, 0, }, /* 0x2d */ + { NULL, 0, }, /* 0x2e */ + { NULL, 0, }, /* 0x2f */ + { "bbc", 3, }, /* 0x30 */ + { "cmpobg", 3, }, /* 0x31 */ + { "cmpobe", 3, }, /* 0x32 */ + { "cmpobge",3, }, /* 0x33 */ + { "cmpobl", 3, }, /* 0x34 */ + { "cmpobne",3, }, /* 0x35 */ + { "cmpoble",3, }, /* 0x36 */ + { "bbs", 3, }, /* 0x37 */ + { "cmpibno",3, }, /* 0x38 */ + { "cmpibg", 3, }, /* 0x39 */ + { "cmpibe", 3, }, /* 0x3a */ + { "cmpibge",3, }, /* 0x3b */ + { "cmpibl", 3, }, /* 0x3c */ + { "cmpibne",3, }, /* 0x3d */ + { "cmpible",3, }, /* 0x3e */ + { "cmpibo", 3, }, /* 0x3f */ + }; + + i = ((word1 >> 24) & 0xff) - 0x20; + if (cobr_tab[i].name == NULL) + { + invalid (word1); + return; + } + + (*info->fprintf_func) (stream, cobr_tab[i].name); + + /* Predicts branch not taken. */ + if (word1 & 2) + (*info->fprintf_func) (stream, ".f"); + + (*info->fprintf_func) (stream, "\t"); + + src1 = (word1 >> 19) & 0x1f; + src2 = (word1 >> 14) & 0x1f; + + if (word1 & 0x02000) + /* M1 is 1 */ + (*info->fprintf_func) (stream, "%d", src1); + else + (*info->fprintf_func) (stream, reg_names[src1]); + + if (cobr_tab[i].numops > 1) + { + if (word1 & 1) + /* S2 is 1. */ + (*info->fprintf_func) (stream, ",sf%d,", src2); + else + /* S1 is 0. */ + (*info->fprintf_func) (stream, ",%s,", reg_names[src2]); + + /* Extract displacement and convert to address. */ + word1 &= 0x00001ffc; + if (word1 & 0x00001000) + /* Negative displacement. */ + word1 |= (-1 & ~0x1fff); /* Sign extend. */ + + print_addr (memaddr + word1); + } +} + +/* MEM format. */ +/* Returns instruction length: 4 or 8. */ + +static int +mem (bfd_vma memaddr, unsigned long word1, unsigned long word2, int noprint) +{ + int i, j; + int len; + int mode; + int offset; + const char *reg1, *reg2, *reg3; + + /* This lookup table is too sparse to make it worth typing in, but not + so large as to make a sparse array necessary. We create the table + at runtime. */ + + /* NOTE: In this table, the meaning of 'numops' is: + 1: single operand + 2: 2 operands, load instruction + -2: 2 operands, store instruction. */ + static struct tabent *mem_tab; + /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ +#define MEM_MIN 0x80 +#define MEM_MAX 0xcf +#define MEM_SIZ ( * sizeof(struct tabent)) + + static const struct sparse_tabent mem_init[] = { + { 0x80, "ldob", 2 }, + { 0x82, "stob", -2 }, + { 0x84, "bx", 1 }, + { 0x85, "balx", 2 }, + { 0x86, "callx", 1 }, + { 0x88, "ldos", 2 }, + { 0x8a, "stos", -2 }, + { 0x8c, "lda", 2 }, + { 0x90, "ld", 2 }, + { 0x92, "st", -2 }, + { 0x98, "ldl", 2 }, + { 0x9a, "stl", -2 }, + { 0xa0, "ldt", 2 }, + { 0xa2, "stt", -2 }, + { 0xac, "dcinva", 1 }, + { 0xb0, "ldq", 2 }, + { 0xb2, "stq", -2 }, + { 0xc0, "ldib", 2 }, + { 0xc2, "stib", -2 }, + { 0xc8, "ldis", 2 }, + { 0xca, "stis", -2 }, + { 0, NULL, 0 } + }; + static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1]; + + if (mem_tab == NULL) + { + mem_tab = mem_tab_buf; + + for (i = 0; mem_init[i].opcode != 0; i++) + { + j = mem_init[i].opcode - MEM_MIN; + mem_tab[j].name = mem_init[i].name; + mem_tab[j].numops = mem_init[i].numops; + } + } + + i = ((word1 >> 24) & 0xff) - MEM_MIN; + mode = (word1 >> 10) & 0xf; + + if ((mem_tab[i].name != NULL) /* Valid instruction */ + && ((mode == 5) || (mode >= 12))) + /* With 32-bit displacement. */ + len = 8; + else + len = 4; + + if (noprint) + return len; + + if ((mem_tab[i].name == NULL) || (mode == 6)) + { + invalid (word1); + return len; + } + + (*info->fprintf_func) (stream, "%s\t", mem_tab[i].name); + + reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */ + reg2 = reg_names[ (word1 >> 14) & 0x1f ]; + reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */ + offset = word1 & 0xfff; /* MEMA only */ + + switch (mem_tab[i].numops) + { + case 2: /* LOAD INSTRUCTION */ + if (mode & 4) + { /* MEMB FORMAT */ + ea (memaddr, mode, reg2, reg3, word1, word2); + (*info->fprintf_func) (stream, ",%s", reg1); + } + else + { /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); + + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + + (*info->fprintf_func)(stream, ",%s", reg1); + } + break; + + case -2: /* STORE INSTRUCTION */ + if (mode & 4) + { + /* MEMB FORMAT */ + (*info->fprintf_func) (stream, "%s,", reg1); + ea (memaddr, mode, reg2, reg3, word1, word2); + } + else + { + /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset); + + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + } + break; + + case 1: /* BX/CALLX INSTRUCTION */ + if (mode & 4) + { + /* MEMB FORMAT */ + ea (memaddr, mode, reg2, reg3, word1, word2); + } + else + { + /* MEMA FORMAT */ + (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); + if (mode & 8) + (*info->fprintf_func) (stream, "(%s)", reg2); + } + break; + } + + return len; +} + +/* REG format. */ + +static void +reg (unsigned long word1) +{ + int i, j; + int opcode; + int fp; + int m1, m2, m3; + int s1, s2; + int src, src2, dst; + char *mnemp; + + /* This lookup table is too sparse to make it worth typing in, but not + so large as to make a sparse array necessary. We create the table + at runtime. */ + + /* NOTE: In this table, the meaning of 'numops' is: + 1: single operand, which is NOT a destination. + -1: single operand, which IS a destination. + 2: 2 operands, the 2nd of which is NOT a destination. + -2: 2 operands, the 2nd of which IS a destination. + 3: 3 operands + + If an opcode mnemonic begins with "F", it is a floating-point + opcode (the "F" is not printed). */ + + static struct tabent *reg_tab; + static const struct sparse_tabent reg_init[] = + { +#define REG_MIN 0x580 + { 0x580, "notbit", 3 }, + { 0x581, "and", 3 }, + { 0x582, "andnot", 3 }, + { 0x583, "setbit", 3 }, + { 0x584, "notand", 3 }, + { 0x586, "xor", 3 }, + { 0x587, "or", 3 }, + { 0x588, "nor", 3 }, + { 0x589, "xnor", 3 }, + { 0x58a, "not", -2 }, + { 0x58b, "ornot", 3 }, + { 0x58c, "clrbit", 3 }, + { 0x58d, "notor", 3 }, + { 0x58e, "nand", 3 }, + { 0x58f, "alterbit", 3 }, + { 0x590, "addo", 3 }, + { 0x591, "addi", 3 }, + { 0x592, "subo", 3 }, + { 0x593, "subi", 3 }, + { 0x594, "cmpob", 2 }, + { 0x595, "cmpib", 2 }, + { 0x596, "cmpos", 2 }, + { 0x597, "cmpis", 2 }, + { 0x598, "shro", 3 }, + { 0x59a, "shrdi", 3 }, + { 0x59b, "shri", 3 }, + { 0x59c, "shlo", 3 }, + { 0x59d, "rotate", 3 }, + { 0x59e, "shli", 3 }, + { 0x5a0, "cmpo", 2 }, + { 0x5a1, "cmpi", 2 }, + { 0x5a2, "concmpo", 2 }, + { 0x5a3, "concmpi", 2 }, + { 0x5a4, "cmpinco", 3 }, + { 0x5a5, "cmpinci", 3 }, + { 0x5a6, "cmpdeco", 3 }, + { 0x5a7, "cmpdeci", 3 }, + { 0x5ac, "scanbyte", 2 }, + { 0x5ad, "bswap", -2 }, + { 0x5ae, "chkbit", 2 }, + { 0x5b0, "addc", 3 }, + { 0x5b2, "subc", 3 }, + { 0x5b4, "intdis", 0 }, + { 0x5b5, "inten", 0 }, + { 0x5cc, "mov", -2 }, + { 0x5d8, "eshro", 3 }, + { 0x5dc, "movl", -2 }, + { 0x5ec, "movt", -2 }, + { 0x5fc, "movq", -2 }, + { 0x600, "synmov", 2 }, + { 0x601, "synmovl", 2 }, + { 0x602, "synmovq", 2 }, + { 0x603, "cmpstr", 3 }, + { 0x604, "movqstr", 3 }, + { 0x605, "movstr", 3 }, + { 0x610, "atmod", 3 }, + { 0x612, "atadd", 3 }, + { 0x613, "inspacc", -2 }, + { 0x614, "ldphy", -2 }, + { 0x615, "synld", -2 }, + { 0x617, "fill", 3 }, + { 0x630, "sdma", 3 }, + { 0x631, "udma", 0 }, + { 0x640, "spanbit", -2 }, + { 0x641, "scanbit", -2 }, + { 0x642, "daddc", 3 }, + { 0x643, "dsubc", 3 }, + { 0x644, "dmovt", -2 }, + { 0x645, "modac", 3 }, + { 0x646, "condrec", -2 }, + { 0x650, "modify", 3 }, + { 0x651, "extract", 3 }, + { 0x654, "modtc", 3 }, + { 0x655, "modpc", 3 }, + { 0x656, "receive", -2 }, + { 0x658, "intctl", -2 }, + { 0x659, "sysctl", 3 }, + { 0x65b, "icctl", 3 }, + { 0x65c, "dcctl", 3 }, + { 0x65d, "halt", 0 }, + { 0x660, "calls", 1 }, + { 0x662, "send", 3 }, + { 0x663, "sendserv", 1 }, + { 0x664, "resumprcs", 1 }, + { 0x665, "schedprcs", 1 }, + { 0x666, "saveprcs", 0 }, + { 0x668, "condwait", 1 }, + { 0x669, "wait", 1 }, + { 0x66a, "signal", 1 }, + { 0x66b, "mark", 0 }, + { 0x66c, "fmark", 0 }, + { 0x66d, "flushreg", 0 }, + { 0x66f, "syncf", 0 }, + { 0x670, "emul", 3 }, + { 0x671, "ediv", 3 }, + { 0x673, "ldtime", -1 }, + { 0x674, "Fcvtir", -2 }, + { 0x675, "Fcvtilr", -2 }, + { 0x676, "Fscalerl", 3 }, + { 0x677, "Fscaler", 3 }, + { 0x680, "Fatanr", 3 }, + { 0x681, "Flogepr", 3 }, + { 0x682, "Flogr", 3 }, + { 0x683, "Fremr", 3 }, + { 0x684, "Fcmpor", 2 }, + { 0x685, "Fcmpr", 2 }, + { 0x688, "Fsqrtr", -2 }, + { 0x689, "Fexpr", -2 }, + { 0x68a, "Flogbnr", -2 }, + { 0x68b, "Froundr", -2 }, + { 0x68c, "Fsinr", -2 }, + { 0x68d, "Fcosr", -2 }, + { 0x68e, "Ftanr", -2 }, + { 0x68f, "Fclassr", 1 }, + { 0x690, "Fatanrl", 3 }, + { 0x691, "Flogeprl", 3 }, + { 0x692, "Flogrl", 3 }, + { 0x693, "Fremrl", 3 }, + { 0x694, "Fcmporl", 2 }, + { 0x695, "Fcmprl", 2 }, + { 0x698, "Fsqrtrl", -2 }, + { 0x699, "Fexprl", -2 }, + { 0x69a, "Flogbnrl", -2 }, + { 0x69b, "Froundrl", -2 }, + { 0x69c, "Fsinrl", -2 }, + { 0x69d, "Fcosrl", -2 }, + { 0x69e, "Ftanrl", -2 }, + { 0x69f, "Fclassrl", 1 }, + { 0x6c0, "Fcvtri", -2 }, + { 0x6c1, "Fcvtril", -2 }, + { 0x6c2, "Fcvtzri", -2 }, + { 0x6c3, "Fcvtzril", -2 }, + { 0x6c9, "Fmovr", -2 }, + { 0x6d9, "Fmovrl", -2 }, + { 0x6e1, "Fmovre", -2 }, + { 0x6e2, "Fcpysre", 3 }, + { 0x6e3, "Fcpyrsre", 3 }, + { 0x701, "mulo", 3 }, + { 0x708, "remo", 3 }, + { 0x70b, "divo", 3 }, + { 0x741, "muli", 3 }, + { 0x748, "remi", 3 }, + { 0x749, "modi", 3 }, + { 0x74b, "divi", 3 }, + { 0x780, "addono", 3 }, + { 0x781, "addino", 3 }, + { 0x782, "subono", 3 }, + { 0x783, "subino", 3 }, + { 0x784, "selno", 3 }, + { 0x78b, "Fdivr", 3 }, + { 0x78c, "Fmulr", 3 }, + { 0x78d, "Fsubr", 3 }, + { 0x78f, "Faddr", 3 }, + { 0x790, "addog", 3 }, + { 0x791, "addig", 3 }, + { 0x792, "subog", 3 }, + { 0x793, "subig", 3 }, + { 0x794, "selg", 3 }, + { 0x79b, "Fdivrl", 3 }, + { 0x79c, "Fmulrl", 3 }, + { 0x79d, "Fsubrl", 3 }, + { 0x79f, "Faddrl", 3 }, + { 0x7a0, "addoe", 3 }, + { 0x7a1, "addie", 3 }, + { 0x7a2, "suboe", 3 }, + { 0x7a3, "subie", 3 }, + { 0x7a4, "sele", 3 }, + { 0x7b0, "addoge", 3 }, + { 0x7b1, "addige", 3 }, + { 0x7b2, "suboge", 3 }, + { 0x7b3, "subige", 3 }, + { 0x7b4, "selge", 3 }, + { 0x7c0, "addol", 3 }, + { 0x7c1, "addil", 3 }, + { 0x7c2, "subol", 3 }, + { 0x7c3, "subil", 3 }, + { 0x7c4, "sell", 3 }, + { 0x7d0, "addone", 3 }, + { 0x7d1, "addine", 3 }, + { 0x7d2, "subone", 3 }, + { 0x7d3, "subine", 3 }, + { 0x7d4, "selne", 3 }, + { 0x7e0, "addole", 3 }, + { 0x7e1, "addile", 3 }, + { 0x7e2, "subole", 3 }, + { 0x7e3, "subile", 3 }, + { 0x7e4, "selle", 3 }, + { 0x7f0, "addoo", 3 }, + { 0x7f1, "addio", 3 }, + { 0x7f2, "suboo", 3 }, + { 0x7f3, "subio", 3 }, + { 0x7f4, "selo", 3 }, +#define REG_MAX 0x7f4 + { 0, NULL, 0 } + }; + static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1]; + + if (reg_tab == NULL) + { + reg_tab = reg_tab_buf; + + for (i = 0; reg_init[i].opcode != 0; i++) + { + j = reg_init[i].opcode - REG_MIN; + reg_tab[j].name = reg_init[i].name; + reg_tab[j].numops = reg_init[i].numops; + } + } + + opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf); + i = opcode - REG_MIN; + + if ((opcodeREG_MAX) || (reg_tab[i].name==NULL)) + { + invalid (word1); + return; + } + + mnemp = reg_tab[i].name; + if (*mnemp == 'F') + { + fp = 1; + mnemp++; + } + else + { + fp = 0; + } + + (*info->fprintf_func) (stream, mnemp); + + s1 = (word1 >> 5) & 1; + s2 = (word1 >> 6) & 1; + m1 = (word1 >> 11) & 1; + m2 = (word1 >> 12) & 1; + m3 = (word1 >> 13) & 1; + src = word1 & 0x1f; + src2 = (word1 >> 14) & 0x1f; + dst = (word1 >> 19) & 0x1f; + + if (reg_tab[i].numops != 0) + { + (*info->fprintf_func) (stream, "\t"); + + switch (reg_tab[i].numops) + { + case 1: + regop (m1, s1, src, fp); + break; + case -1: + dstop (m3, dst, fp); + break; + case 2: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + regop (m2, s2, src2, fp); + break; + case -2: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + dstop (m3, dst, fp); + break; + case 3: + regop (m1, s1, src, fp); + (*info->fprintf_func) (stream, ","); + regop (m2, s2, src2, fp); + (*info->fprintf_func) (stream, ","); + dstop (m3, dst, fp); + break; + } + } +} + +/* Print out effective address for memb instructions. */ + +static void +ea (bfd_vma memaddr, int mode, const char *reg2, const char *reg3, int word1, + unsigned int word2) +{ + int scale; + static const int scale_tab[] = { 1, 2, 4, 8, 16 }; + + scale = (word1 >> 7) & 0x07; + + if ((scale > 4) || (((word1 >> 5) & 0x03) != 0)) + { + invalid (word1); + return; + } + scale = scale_tab[scale]; + + switch (mode) + { + case 4: /* (reg) */ + (*info->fprintf_func)( stream, "(%s)", reg2 ); + break; + case 5: /* displ+8(ip) */ + print_addr (word2 + 8 + memaddr); + break; + case 7: /* (reg)[index*scale] */ + if (scale == 1) + (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); + else + (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); + break; + case 12: /* displacement */ + print_addr ((bfd_vma) word2); + break; + case 13: /* displ(reg) */ + print_addr ((bfd_vma) word2); + (*info->fprintf_func) (stream, "(%s)", reg2); + break; + case 14: /* displ[index*scale] */ + print_addr ((bfd_vma) word2); + if (scale == 1) + (*info->fprintf_func) (stream, "[%s]", reg3); + else + (*info->fprintf_func) (stream, "[%s*%d]", reg3, scale); + break; + case 15: /* displ(reg)[index*scale] */ + print_addr ((bfd_vma) word2); + if (scale == 1) + (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); + else + (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); + break; + default: + invalid (word1); + return; + } +} + + +/* Register Instruction Operand. */ + +static void +regop (int mode, int spec, int fp_reg, int fp) +{ + if (fp) + { + /* Floating point instruction. */ + if (mode == 1) + { + /* FP operand. */ + switch (fp_reg) + { + case 0: (*info->fprintf_func) (stream, "fp0"); + break; + case 1: (*info->fprintf_func) (stream, "fp1"); + break; + case 2: (*info->fprintf_func) (stream, "fp2"); + break; + case 3: (*info->fprintf_func) (stream, "fp3"); + break; + case 16: (*info->fprintf_func) (stream, "0f0.0"); + break; + case 22: (*info->fprintf_func) (stream, "0f1.0"); + break; + default: (*info->fprintf_func) (stream, "?"); + break; + } + } + else + { + /* Non-FP register. */ + (*info->fprintf_func) (stream, reg_names[fp_reg]); + } + } + else + { + /* Not floating point. */ + if (mode == 1) + { + /* Literal. */ + (*info->fprintf_func) (stream, "%d", fp_reg); + } + else + { + /* Register. */ + if (spec == 0) + (*info->fprintf_func) (stream, reg_names[fp_reg]); + else + (*info->fprintf_func) (stream, "sf%d", fp_reg); + } + } +} + +/* Register Instruction Destination Operand. */ + +static void +dstop (int mode, int dest_reg, int fp) +{ + /* 'dst' operand can't be a literal. On non-FP instructions, register + mode is assumed and "m3" acts as if were "s3"; on FP-instructions, + sf registers are not allowed so m3 acts normally. */ + if (fp) + regop (mode, 0, dest_reg, fp); + else + regop (0, mode, dest_reg, fp); +} + +static void +invalid (int word1) +{ + (*info->fprintf_func) (stream, ".word\t0x%08x", (unsigned) word1); +} + +static void +print_addr (bfd_vma a) +{ + (*info->print_address_func) (a, info); +} + +static void +put_abs (unsigned long word1 ATTRIBUTE_UNUSED, + unsigned long word2 ATTRIBUTE_UNUSED) +{ +#ifdef IN_GDB + return; +#else + int len; + + switch ((word1 >> 28) & 0xf) + { + case 0x8: + case 0x9: + case 0xa: + case 0xb: + case 0xc: + /* MEM format instruction. */ + len = mem (0, word1, word2, 1); + break; + default: + len = 4; + break; + } + + if (len == 8) + (*info->fprintf_func) (stream, "%08x %08x\t", word1, word2); + else + (*info->fprintf_func) (stream, "%08x \t", word1); +#endif +} diff --git a/external/gpl3/gdb/dist/opcodes/ia64-asmtab.c b/external/gpl3/gdb/dist/opcodes/ia64-asmtab.c new file mode 100644 index 000000000000..3285228220a9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-asmtab.c @@ -0,0 +1,8797 @@ +/* This file is automatically generated by ia64-gen. Do not edit! */ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ +static const char * const ia64_strings[] = { + "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", + "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16", + "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", + "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", + "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", + "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", + "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", + "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", + "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", + "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", + "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", + "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", + "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia", + "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", + "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", + "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", + "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", + "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", + "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1", + "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1", + "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", + "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", + "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", + "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", + "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig", + "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2", + "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1", + "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa", + "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4", + "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2", + "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", + "zxt4", +}; + +static const struct ia64_dependency +dependencies[] = { + { "ALAT", 0, 0, 0, -1, NULL, }, + { "AR[BSP]", 27, 0, 2, 17, NULL, }, + { "AR[BSPSTORE]", 27, 0, 2, 18, NULL, }, + { "AR[CCV]", 27, 0, 2, 32, NULL, }, + { "AR[CFLG]", 27, 0, 2, 27, NULL, }, + { "AR[CSD]", 27, 0, 2, 25, NULL, }, + { "AR[EC]", 27, 0, 2, 66, NULL, }, + { "AR[EFLAG]", 27, 0, 2, 24, NULL, }, + { "AR[FCR]", 27, 0, 2, 21, NULL, }, + { "AR[FDR]", 27, 0, 2, 30, NULL, }, + { "AR[FIR]", 27, 0, 2, 29, NULL, }, + { "AR[FPSR].sf0.controls", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].traps", 31, 0, 2, -1, NULL, }, + { "AR[FPSR].rv", 31, 0, 2, -1, NULL, }, + { "AR[FSR]", 27, 0, 2, 28, NULL, }, + { "AR[ITC]", 27, 0, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, + { "AR[LC]", 27, 0, 2, 65, NULL, }, + { "AR[PFS]", 27, 0, 2, 64, NULL, }, + { "AR[PFS]", 27, 0, 2, 64, NULL, }, + { "AR[PFS]", 27, 0, 0, 64, NULL, }, + { "AR[RNAT]", 27, 0, 2, 19, NULL, }, + { "AR[RSC]", 27, 0, 2, 16, NULL, }, + { "AR[RUC]", 27, 0, 2, 45, NULL, }, + { "AR[SSD]", 27, 0, 2, 26, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111", 3, 0, 0, -1, NULL, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 0, -1, NULL, }, + { "CPUID#", 7, 0, 5, -1, NULL, }, + { "CR[CMCV]", 28, 0, 3, 74, NULL, }, + { "CR[DCR]", 28, 0, 3, 0, NULL, }, + { "CR[EOI]", 28, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, + { "CR[GPTA]", 28, 0, 3, 9, NULL, }, + { "CR[IFA]", 28, 0, 1, 20, NULL, }, + { "CR[IFA]", 28, 0, 3, 20, NULL, }, + { "CR[IFS]", 28, 0, 3, 23, NULL, }, + { "CR[IFS]", 28, 0, 1, 23, NULL, }, + { "CR[IFS]", 28, 0, 1, 23, NULL, }, + { "CR[IHA]", 28, 0, 3, 25, NULL, }, + { "CR[IIB%], % in 0 - 1", 8, 0, 3, -1, NULL, }, + { "CR[IIM]", 28, 0, 3, 24, NULL, }, + { "CR[IIP]", 28, 0, 3, 19, NULL, }, + { "CR[IIP]", 28, 0, 1, 19, NULL, }, + { "CR[IIPA]", 28, 0, 3, 22, NULL, }, + { "CR[IPSR]", 28, 0, 3, 16, NULL, }, + { "CR[IPSR]", 28, 0, 1, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 9, 0, 3, -1, NULL, }, + { "CR[ISR]", 28, 0, 3, 17, NULL, }, + { "CR[ITIR]", 28, 0, 3, 21, NULL, }, + { "CR[ITIR]", 28, 0, 1, 21, NULL, }, + { "CR[ITM]", 28, 0, 3, 1, NULL, }, + { "CR[ITV]", 28, 0, 3, 72, NULL, }, + { "CR[IVA]", 28, 0, 4, 2, NULL, }, + { "CR[IVR]", 28, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", }, + { "CR[LID]", 28, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", }, + { "CR[LRR%], % in 0 - 1", 10, 0, 3, -1, NULL, }, + { "CR[PMV]", 28, 0, 3, 73, NULL, }, + { "CR[PTA]", 28, 0, 3, 8, NULL, }, + { "CR[TPR]", 28, 0, 3, 66, NULL, }, + { "CR[TPR]", 28, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", }, + { "CR[TPR]", 28, 0, 1, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127", 11, 0, 0, -1, NULL, }, + { "DBR#", 12, 0, 2, -1, NULL, }, + { "DBR#", 12, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC", 0, 0, 0, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 0, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "FR%, % in 0 - 1", 13, 0, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 14, 0, 2, -1, NULL, }, + { "FR%, % in 2 - 127", 14, 0, 0, -1, NULL, }, + { "GR0", 15, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 16, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 16, 0, 2, -1, NULL, }, + { "IBR#", 17, 0, 2, -1, NULL, }, + { "InService*", 18, 0, 3, -1, NULL, }, + { "InService*", 18, 0, 2, -1, NULL, }, + { "InService*", 18, 0, 2, -1, NULL, }, + { "IP", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 0, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "memory", 0, 0, 0, -1, NULL, }, + { "MSR#", 19, 0, 5, -1, NULL, }, + { "PKR#", 20, 0, 3, -1, NULL, }, + { "PKR#", 20, 0, 0, -1, NULL, }, + { "PKR#", 20, 0, 2, -1, NULL, }, + { "PKR#", 20, 0, 2, -1, NULL, }, + { "PMC#", 21, 0, 2, -1, NULL, }, + { "PMC#", 21, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", }, + { "PMD#", 22, 0, 2, -1, NULL, }, + { "PR0", 0, 0, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 0, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 0, 0, -1, NULL, }, + { "PR63", 25, 0, 2, -1, NULL, }, + { "PR63", 25, 0, 2, -1, NULL, }, + { "PR63", 25, 0, 0, -1, NULL, }, + { "PSR.ac", 29, 0, 1, 3, NULL, }, + { "PSR.ac", 29, 0, 3, 3, NULL, }, + { "PSR.ac", 29, 0, 2, 3, NULL, }, + { "PSR.ac", 29, 0, 2, 3, NULL, }, + { "PSR.be", 29, 0, 1, 1, NULL, }, + { "PSR.be", 29, 0, 3, 1, NULL, }, + { "PSR.be", 29, 0, 2, 1, NULL, }, + { "PSR.be", 29, 0, 2, 1, NULL, }, + { "PSR.bn", 29, 0, 2, 44, NULL, }, + { "PSR.cpl", 29, 0, 1, 32, NULL, }, + { "PSR.cpl", 29, 0, 2, 32, NULL, }, + { "PSR.da", 29, 0, 2, 38, NULL, }, + { "PSR.db", 29, 0, 3, 24, NULL, }, + { "PSR.db", 29, 0, 2, 24, NULL, }, + { "PSR.db", 29, 0, 2, 24, NULL, }, + { "PSR.dd", 29, 0, 2, 39, NULL, }, + { "PSR.dfh", 29, 0, 3, 19, NULL, }, + { "PSR.dfh", 29, 0, 2, 19, NULL, }, + { "PSR.dfh", 29, 0, 2, 19, NULL, }, + { "PSR.dfl", 29, 0, 3, 18, NULL, }, + { "PSR.dfl", 29, 0, 2, 18, NULL, }, + { "PSR.dfl", 29, 0, 2, 18, NULL, }, + { "PSR.di", 29, 0, 3, 22, NULL, }, + { "PSR.di", 29, 0, 2, 22, NULL, }, + { "PSR.di", 29, 0, 2, 22, NULL, }, + { "PSR.dt", 29, 0, 3, 17, NULL, }, + { "PSR.dt", 29, 0, 2, 17, NULL, }, + { "PSR.dt", 29, 0, 2, 17, NULL, }, + { "PSR.ed", 29, 0, 2, 43, NULL, }, + { "PSR.i", 29, 0, 2, 14, NULL, }, + { "PSR.ia", 29, 0, 0, 14, NULL, }, + { "PSR.ic", 29, 0, 2, 13, NULL, }, + { "PSR.ic", 29, 0, 3, 13, NULL, }, + { "PSR.ic", 29, 0, 2, 13, NULL, }, + { "PSR.id", 29, 0, 0, 14, NULL, }, + { "PSR.is", 29, 0, 0, 14, NULL, }, + { "PSR.it", 29, 0, 2, 14, NULL, }, + { "PSR.lp", 29, 0, 2, 25, NULL, }, + { "PSR.lp", 29, 0, 3, 25, NULL, }, + { "PSR.lp", 29, 0, 2, 25, NULL, }, + { "PSR.mc", 29, 0, 2, 35, NULL, }, + { "PSR.mfh", 29, 0, 2, 5, NULL, }, + { "PSR.mfl", 29, 0, 2, 4, NULL, }, + { "PSR.pk", 29, 0, 3, 15, NULL, }, + { "PSR.pk", 29, 0, 2, 15, NULL, }, + { "PSR.pk", 29, 0, 2, 15, NULL, }, + { "PSR.pp", 29, 0, 2, 21, NULL, }, + { "PSR.ri", 29, 0, 0, 41, NULL, }, + { "PSR.rt", 29, 0, 2, 27, NULL, }, + { "PSR.rt", 29, 0, 3, 27, NULL, }, + { "PSR.rt", 29, 0, 2, 27, NULL, }, + { "PSR.si", 29, 0, 2, 23, NULL, }, + { "PSR.si", 29, 0, 3, 23, NULL, }, + { "PSR.si", 29, 0, 2, 23, NULL, }, + { "PSR.sp", 29, 0, 2, 20, NULL, }, + { "PSR.sp", 29, 0, 3, 20, NULL, }, + { "PSR.sp", 29, 0, 2, 20, NULL, }, + { "PSR.ss", 29, 0, 2, 40, NULL, }, + { "PSR.tb", 29, 0, 3, 26, NULL, }, + { "PSR.tb", 29, 0, 2, 26, NULL, }, + { "PSR.tb", 29, 0, 2, 26, NULL, }, + { "PSR.up", 29, 0, 2, 2, NULL, }, + { "PSR.vm", 29, 0, 1, 46, NULL, }, + { "PSR.vm", 29, 0, 2, 46, NULL, }, + { "RR#", 26, 0, 3, -1, NULL, }, + { "RR#", 26, 0, 2, -1, NULL, }, + { "RSE", 30, 0, 2, -1, NULL, }, + { "ALAT", 0, 1, 0, -1, NULL, }, + { "AR[BSP]", 27, 1, 2, 17, NULL, }, + { "AR[BSPSTORE]", 27, 1, 2, 18, NULL, }, + { "AR[CCV]", 27, 1, 2, 32, NULL, }, + { "AR[CFLG]", 27, 1, 2, 27, NULL, }, + { "AR[CSD]", 27, 1, 2, 25, NULL, }, + { "AR[EC]", 27, 1, 2, 66, NULL, }, + { "AR[EFLAG]", 27, 1, 2, 24, NULL, }, + { "AR[FCR]", 27, 1, 2, 21, NULL, }, + { "AR[FDR]", 27, 1, 2, 30, NULL, }, + { "AR[FIR]", 27, 1, 2, 29, NULL, }, + { "AR[FPSR].sf0.controls", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 31, 1, 0, -1, NULL, }, + { "AR[FPSR].sf0.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 31, 1, 0, -1, NULL, }, + { "AR[FPSR].sf1.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 31, 1, 0, -1, NULL, }, + { "AR[FPSR].sf2.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 31, 1, 0, -1, NULL, }, + { "AR[FPSR].sf3.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].rv", 31, 1, 2, -1, NULL, }, + { "AR[FPSR].traps", 31, 1, 2, -1, NULL, }, + { "AR[FSR]", 27, 1, 2, 28, NULL, }, + { "AR[ITC]", 27, 1, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, + { "AR[LC]", 27, 1, 2, 65, NULL, }, + { "AR[PFS]", 27, 1, 0, 64, NULL, }, + { "AR[PFS]", 27, 1, 2, 64, NULL, }, + { "AR[PFS]", 27, 1, 2, 64, NULL, }, + { "AR[RNAT]", 27, 1, 2, 19, NULL, }, + { "AR[RSC]", 27, 1, 2, 16, NULL, }, + { "AR[RUC]", 27, 1, 2, 45, NULL, }, + { "AR[SSD]", 27, 1, 2, 26, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111", 3, 1, 0, -1, NULL, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, + { "CFM", 6, 1, 2, -1, NULL, }, + { "CPUID#", 7, 1, 0, -1, NULL, }, + { "CR[CMCV]", 28, 1, 2, 74, NULL, }, + { "CR[DCR]", 28, 1, 2, 0, NULL, }, + { "CR[EOI]", 28, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, + { "CR[GPTA]", 28, 1, 2, 9, NULL, }, + { "CR[IFA]", 28, 1, 2, 20, NULL, }, + { "CR[IFS]", 28, 1, 2, 23, NULL, }, + { "CR[IHA]", 28, 1, 2, 25, NULL, }, + { "CR[IIB%], % in 0 - 1", 8, 1, 2, -1, NULL, }, + { "CR[IIM]", 28, 1, 2, 24, NULL, }, + { "CR[IIP]", 28, 1, 2, 19, NULL, }, + { "CR[IIPA]", 28, 1, 2, 22, NULL, }, + { "CR[IPSR]", 28, 1, 2, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 9, 1, 2, -1, NULL, }, + { "CR[ISR]", 28, 1, 2, 17, NULL, }, + { "CR[ITIR]", 28, 1, 2, 21, NULL, }, + { "CR[ITM]", 28, 1, 2, 1, NULL, }, + { "CR[ITV]", 28, 1, 2, 72, NULL, }, + { "CR[IVA]", 28, 1, 2, 2, NULL, }, + { "CR[IVR]", 28, 1, 7, 65, "SC", }, + { "CR[LID]", 28, 1, 7, 64, "SC", }, + { "CR[LRR%], % in 0 - 1", 10, 1, 2, -1, NULL, }, + { "CR[PMV]", 28, 1, 2, 73, NULL, }, + { "CR[PTA]", 28, 1, 2, 8, NULL, }, + { "CR[TPR]", 28, 1, 2, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127", 11, 1, 0, -1, NULL, }, + { "DBR#", 12, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 0, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 0, -1, NULL, }, + { "FR%, % in 0 - 1", 13, 1, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 14, 1, 2, -1, NULL, }, + { "GR0", 15, 1, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 16, 1, 2, -1, NULL, }, + { "IBR#", 17, 1, 2, -1, NULL, }, + { "InService*", 18, 1, 7, -1, "SC", }, + { "IP", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 0, -1, NULL, }, + { "memory", 0, 1, 0, -1, NULL, }, + { "MSR#", 19, 1, 7, -1, "SC", }, + { "PKR#", 20, 1, 0, -1, NULL, }, + { "PKR#", 20, 1, 0, -1, NULL, }, + { "PKR#", 20, 1, 2, -1, NULL, }, + { "PMC#", 21, 1, 2, -1, NULL, }, + { "PMD#", 22, 1, 2, -1, NULL, }, + { "PR0", 0, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 1, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 23, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 24, 1, 2, -1, NULL, }, + { "PR63", 25, 1, 0, -1, NULL, }, + { "PR63", 25, 1, 0, -1, NULL, }, + { "PR63", 25, 1, 2, -1, NULL, }, + { "PR63", 25, 1, 2, -1, NULL, }, + { "PSR.ac", 29, 1, 2, 3, NULL, }, + { "PSR.be", 29, 1, 2, 1, NULL, }, + { "PSR.bn", 29, 1, 2, 44, NULL, }, + { "PSR.cpl", 29, 1, 2, 32, NULL, }, + { "PSR.da", 29, 1, 2, 38, NULL, }, + { "PSR.db", 29, 1, 2, 24, NULL, }, + { "PSR.dd", 29, 1, 2, 39, NULL, }, + { "PSR.dfh", 29, 1, 2, 19, NULL, }, + { "PSR.dfl", 29, 1, 2, 18, NULL, }, + { "PSR.di", 29, 1, 2, 22, NULL, }, + { "PSR.dt", 29, 1, 2, 17, NULL, }, + { "PSR.ed", 29, 1, 2, 43, NULL, }, + { "PSR.i", 29, 1, 2, 14, NULL, }, + { "PSR.ia", 29, 1, 2, 14, NULL, }, + { "PSR.ic", 29, 1, 2, 13, NULL, }, + { "PSR.id", 29, 1, 2, 14, NULL, }, + { "PSR.is", 29, 1, 2, 14, NULL, }, + { "PSR.it", 29, 1, 2, 14, NULL, }, + { "PSR.lp", 29, 1, 2, 25, NULL, }, + { "PSR.mc", 29, 1, 2, 35, NULL, }, + { "PSR.mfh", 29, 1, 0, 5, NULL, }, + { "PSR.mfh", 29, 1, 2, 5, NULL, }, + { "PSR.mfh", 29, 1, 2, 5, NULL, }, + { "PSR.mfl", 29, 1, 0, 4, NULL, }, + { "PSR.mfl", 29, 1, 2, 4, NULL, }, + { "PSR.mfl", 29, 1, 2, 4, NULL, }, + { "PSR.pk", 29, 1, 2, 15, NULL, }, + { "PSR.pp", 29, 1, 2, 21, NULL, }, + { "PSR.ri", 29, 1, 2, 41, NULL, }, + { "PSR.rt", 29, 1, 2, 27, NULL, }, + { "PSR.si", 29, 1, 2, 23, NULL, }, + { "PSR.sp", 29, 1, 2, 20, NULL, }, + { "PSR.ss", 29, 1, 2, 40, NULL, }, + { "PSR.tb", 29, 1, 2, 26, NULL, }, + { "PSR.up", 29, 1, 2, 2, NULL, }, + { "PSR.vm", 29, 1, 2, 46, NULL, }, + { "RR#", 26, 1, 2, -1, NULL, }, + { "RSE", 30, 1, 2, -1, NULL, }, + { "PR63", 25, 2, 6, -1, NULL, }, +}; + +static const unsigned short dep0[] = { + 99, 286, 2142, 2331, +}; + +static const unsigned short dep1[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2331, 4136, 20618, +}; + +static const unsigned short dep2[] = { + 99, 286, 2168, 2169, 2171, 2172, 2174, 2175, 2177, 2348, 2351, 2352, 2355, + 2356, 2359, 2360, +}; + +static const unsigned short dep3[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 20618, +}; + +static const unsigned short dep4[] = { + 99, 286, 22648, 22649, 22651, 22652, 22654, 22655, 22657, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep5[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 4136, 20618, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep6[] = { + 99, 286, 2168, 2169, 2171, 2172, 2174, 2175, 2177, 2348, 2349, 2351, 2353, + 2355, 2357, 2359, +}; + +static const unsigned short dep7[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2348, 2349, 2352, 2353, 2356, 2357, 2360, 4136, 20618, +}; + +static const unsigned short dep8[] = { + 99, 286, 2168, 2169, 2171, 2172, 2174, 2175, 2177, 2348, 2350, 2352, 2354, + 2356, 2358, 2360, +}; + +static const unsigned short dep9[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2348, 2350, 2351, 2354, 2355, 2358, 2359, 4136, 20618, +}; + +static const unsigned short dep10[] = { + 99, 286, 2168, 2169, 2171, 2172, 2174, 2175, 2177, 2348, 2349, 2350, 2351, + 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, +}; + +static const unsigned short dep11[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, + 4136, 20618, +}; + +static const unsigned short dep12[] = { + 99, 286, 2399, +}; + +static const unsigned short dep13[] = { + 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2083, 2084, 2168, 2170, + 2171, 2173, 2174, 2176, 2177, 4136, +}; + +static const unsigned short dep14[] = { + 99, 165, 286, 329, 2399, 28868, 29022, +}; + +static const unsigned short dep15[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 41, 42, 99, 152, 154, 160, + 164, 166, 177, 187, 188, 190, 286, 329, 2083, 2084, 2168, 2170, 2171, 2173, + 2174, 2176, 2177, 4136, 28868, 29022, +}; + +static const unsigned short dep16[] = { + 1, 6, 41, 99, 139, 198, 203, 244, 286, 316, 2399, 28868, 29022, +}; + +static const unsigned short dep17[] = { + 1, 25, 27, 39, 41, 42, 99, 160, 164, 166, 168, 169, 177, 187, 188, 190, 198, + 203, 244, 286, 316, 2083, 2084, 2168, 2170, 2171, 2173, 2174, 2176, 2177, + 4136, 28868, 29022, +}; + +static const unsigned short dep18[] = { + 1, 41, 52, 99, 198, 244, 251, 286, 28868, 29022, +}; + +static const unsigned short dep19[] = { + 1, 39, 41, 42, 99, 160, 162, 163, 164, 177, 187, 192, 193, 198, 244, 251, + 286, 4136, 28868, 29022, +}; + +static const unsigned short dep20[] = { + 41, 99, 244, 286, +}; + +static const unsigned short dep21[] = { + 99, 160, 164, 177, 187, 244, 286, +}; + +static const unsigned short dep22[] = { + 1, 41, 99, 133, 137, 138, 140, 141, 144, 145, 148, 151, 154, 157, 158, 159, + 160, 163, 164, 165, 166, 169, 170, 171, 172, 175, 176, 177, 180, 183, 186, + 187, 190, 191, 193, 198, 244, 286, 313, 314, 315, 316, 317, 318, 319, 320, + 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 334, 335, 337, + 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 28868, 29022, +}; + +static const unsigned short dep23[] = { + 1, 39, 41, 42, 51, 52, 57, 60, 75, 99, 139, 140, 160, 164, 177, 187, 192, + 193, 198, 244, 286, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, + 324, 325, 326, 327, 328, 329, 330, 331, 332, 334, 335, 337, 338, 339, 340, + 341, 342, 343, 344, 345, 346, 347, 348, 4136, 28868, 29022, +}; + +static const unsigned short dep24[] = { + 99, 138, 286, 315, +}; + +static const unsigned short dep25[] = { + 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 315, +}; + +static const unsigned short dep26[] = { + 99, 139, 286, 316, +}; + +static const unsigned short dep27[] = { + 25, 26, 99, 100, 103, 107, 110, 139, 140, 160, 164, 166, 177, 187, 286, 316, + +}; + +static const unsigned short dep28[] = { + 99, 192, 286, 348, +}; + +static const unsigned short dep29[] = { + 99, 100, 103, 107, 110, 139, 140, 160, 164, 166, 177, 187, 286, 348, +}; + +static const unsigned short dep30[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2170, 2171, 2173, 2174, 2176, 2177, + 4136, +}; + +static const unsigned short dep31[] = { + 1, 25, 41, 99, 198, 230, 231, 244, 286, 2083, 2288, 2291, 2399, 28868, 29022, + +}; + +static const unsigned short dep32[] = { + 1, 6, 39, 41, 42, 99, 139, 140, 160, 164, 166, 177, 187, 188, 190, 198, 230, + 232, 244, 286, 2083, 2084, 2168, 2170, 2171, 2173, 2174, 2176, 2177, 2289, + 2291, 4136, 28868, 29022, +}; + +static const unsigned short dep33[] = { + 99, 286, +}; + +static const unsigned short dep34[] = { + 99, 160, 164, 177, 187, 286, 2083, 2085, +}; + +static const unsigned short dep35[] = { + 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, 2170, 2171, 2173, + 2174, 2176, 2177, 4136, +}; + +static const unsigned short dep36[] = { + 6, 38, 39, 40, 99, 127, 128, 203, 244, 286, 311, 312, 2399, +}; + +static const unsigned short dep37[] = { + 6, 38, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 203, 244, 286, 311, + 312, 351, 2168, 2170, 2171, 2173, 2174, 2176, 2177, 4136, +}; + +static const unsigned short dep38[] = { + 24, 99, 229, 286, 2399, +}; + +static const unsigned short dep39[] = { + 24, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 229, 286, 2168, 2170, 2171, + 2173, 2174, 2176, 2177, 4136, +}; + +static const unsigned short dep40[] = { + 6, 24, 38, 39, 40, 99, 127, 128, 203, 229, 244, 286, 311, 312, 2399, +}; + +static const unsigned short dep41[] = { + 6, 24, 38, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 203, 229, 244, 286, + 311, 312, 351, 2168, 2170, 2171, 2173, 2174, 2176, 2177, 4136, +}; + +static const unsigned short dep42[] = { + 1, 6, 39, 41, 42, 99, 139, 140, 160, 164, 166, 177, 187, 188, 190, 198, 230, + 232, 244, 286, 2168, 2170, 2171, 2173, 2174, 2176, 2177, 2289, 2291, 4136, + 28868, 29022, +}; + +static const unsigned short dep43[] = { + 99, 160, 164, 177, 187, 286, +}; + +static const unsigned short dep44[] = { + 15, 99, 212, 213, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, 22835, + 22836, 22839, 22840, +}; + +static const unsigned short dep45[] = { + 11, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep46[] = { + 15, 16, 17, 18, 99, 212, 213, 215, 216, 218, 219, 221, 222, 286, 2138, 2329, + 18603, 18604, 18765, 18766, 18768, 18769, 22648, 22649, 22650, 22652, 22653, + 22655, 22656, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep47[] = { + 11, 12, 13, 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 215, 217, + 218, 220, 221, 223, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, 2329, 4136, + 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep48[] = { + 16, 99, 215, 216, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, 22835, + 22836, 22839, 22840, +}; + +static const unsigned short dep49[] = { + 12, 19, 20, 41, 42, 99, 160, 164, 177, 187, 215, 217, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep50[] = { + 17, 99, 218, 219, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, 22835, + 22836, 22839, 22840, +}; + +static const unsigned short dep51[] = { + 13, 19, 20, 41, 42, 99, 160, 164, 177, 187, 218, 220, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep52[] = { + 18, 99, 221, 222, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, 22835, + 22836, 22839, 22840, +}; + +static const unsigned short dep53[] = { + 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 221, 223, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep54[] = { + 15, 99, 212, 213, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + +}; + +static const unsigned short dep55[] = { + 11, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, +}; + +static const unsigned short dep56[] = { + 15, 16, 17, 18, 99, 212, 213, 215, 216, 218, 219, 221, 222, 286, 2138, 2329, + 18603, 18604, 18765, 18766, 18768, 18769, +}; + +static const unsigned short dep57[] = { + 11, 12, 13, 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 215, 217, + 218, 220, 221, 223, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, 2329, 4136, + 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, +}; + +static const unsigned short dep58[] = { + 16, 99, 215, 216, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + +}; + +static const unsigned short dep59[] = { + 12, 19, 20, 41, 42, 99, 160, 164, 177, 187, 215, 217, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, +}; + +static const unsigned short dep60[] = { + 17, 99, 218, 219, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + +}; + +static const unsigned short dep61[] = { + 13, 19, 20, 41, 42, 99, 160, 164, 177, 187, 218, 220, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, +}; + +static const unsigned short dep62[] = { + 18, 99, 221, 222, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, + +}; + +static const unsigned short dep63[] = { + 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 221, 223, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, + 18768, 18770, +}; + +static const unsigned short dep64[] = { + 99, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, +}; + +static const unsigned short dep65[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, + 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, +}; + +static const unsigned short dep66[] = { + 11, 99, 208, 286, +}; + +static const unsigned short dep67[] = { + 11, 41, 42, 99, 160, 164, 177, 187, 208, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep68[] = { + 11, 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep69[] = { + 12, 99, 209, 286, +}; + +static const unsigned short dep70[] = { + 11, 41, 42, 99, 160, 164, 177, 187, 209, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep71[] = { + 13, 99, 210, 286, +}; + +static const unsigned short dep72[] = { + 11, 41, 42, 99, 160, 164, 177, 187, 210, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep73[] = { + 14, 99, 211, 286, +}; + +static const unsigned short dep74[] = { + 11, 41, 42, 99, 160, 164, 177, 187, 211, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep75[] = { + 15, 99, 213, 214, 286, +}; + +static const unsigned short dep76[] = { + 41, 42, 99, 160, 164, 177, 187, 213, 214, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep77[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep78[] = { + 16, 99, 216, 217, 286, +}; + +static const unsigned short dep79[] = { + 41, 42, 99, 160, 164, 177, 187, 216, 217, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep80[] = { + 17, 99, 219, 220, 286, +}; + +static const unsigned short dep81[] = { + 41, 42, 99, 160, 164, 177, 187, 219, 220, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep82[] = { + 18, 99, 222, 223, 286, +}; + +static const unsigned short dep83[] = { + 41, 42, 99, 160, 164, 177, 187, 222, 223, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep84[] = { + 15, 19, 20, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, 2169, + 2172, 2175, 4136, +}; + +static const unsigned short dep85[] = { + 15, 16, 19, 20, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, + 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep86[] = { + 15, 17, 19, 20, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, + 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep87[] = { + 15, 18, 19, 20, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, + 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep88[] = { + 15, 99, 212, 213, 286, +}; + +static const unsigned short dep89[] = { + 11, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 286, 2168, 2169, 2172, + 2175, 4136, +}; + +static const unsigned short dep90[] = { + 15, 16, 17, 18, 99, 212, 213, 215, 216, 218, 219, 221, 222, 286, +}; + +static const unsigned short dep91[] = { + 11, 12, 13, 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 215, 217, + 218, 220, 221, 223, 286, 2168, 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep92[] = { + 16, 99, 215, 216, 286, +}; + +static const unsigned short dep93[] = { + 12, 19, 20, 41, 42, 99, 160, 164, 177, 187, 215, 217, 286, 2168, 2169, 2172, + 2175, 4136, +}; + +static const unsigned short dep94[] = { + 17, 99, 218, 219, 286, +}; + +static const unsigned short dep95[] = { + 13, 19, 20, 41, 42, 99, 160, 164, 177, 187, 218, 220, 286, 2168, 2169, 2172, + 2175, 4136, +}; + +static const unsigned short dep96[] = { + 18, 99, 221, 222, 286, +}; + +static const unsigned short dep97[] = { + 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 221, 223, 286, 2168, 2169, 2172, + 2175, 4136, +}; + +static const unsigned short dep98[] = { + 15, 99, 212, 213, 286, 2168, 2169, 2170, 2172, 2173, 2175, 2176, 2348, 2351, + 2352, 2355, 2356, 2359, 2360, +}; + +static const unsigned short dep99[] = { + 11, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 16530, + 16532, 16533, 16535, +}; + +static const unsigned short dep100[] = { + 15, 16, 17, 18, 99, 212, 213, 215, 216, 218, 219, 221, 222, 286, 2168, 2169, + 2170, 2172, 2173, 2175, 2176, 2348, 2351, 2352, 2355, 2356, 2359, 2360, +}; + +static const unsigned short dep101[] = { + 11, 12, 13, 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 215, 217, + 218, 220, 221, 223, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, 2348, 2351, + 2352, 2355, 2356, 2359, 2360, 4136, 16530, 16532, 16533, 16535, +}; + +static const unsigned short dep102[] = { + 16, 99, 215, 216, 286, 2168, 2169, 2170, 2172, 2173, 2175, 2176, 2348, 2351, + 2352, 2355, 2356, 2359, 2360, +}; + +static const unsigned short dep103[] = { + 12, 19, 20, 41, 42, 99, 160, 164, 177, 187, 215, 217, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 16530, + 16532, 16533, 16535, +}; + +static const unsigned short dep104[] = { + 17, 99, 218, 219, 286, 2168, 2169, 2170, 2172, 2173, 2175, 2176, 2348, 2351, + 2352, 2355, 2356, 2359, 2360, +}; + +static const unsigned short dep105[] = { + 13, 19, 20, 41, 42, 99, 160, 164, 177, 187, 218, 220, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 16530, + 16532, 16533, 16535, +}; + +static const unsigned short dep106[] = { + 18, 99, 221, 222, 286, 2168, 2169, 2170, 2172, 2173, 2175, 2176, 2348, 2351, + 2352, 2355, 2356, 2359, 2360, +}; + +static const unsigned short dep107[] = { + 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 221, 223, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 16530, + 16532, 16533, 16535, +}; + +static const unsigned short dep108[] = { + 15, 99, 212, 213, 286, 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, + 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep109[] = { + 11, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 4136, 16530, 16532, 16533, 16535, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep110[] = { + 15, 16, 17, 18, 99, 212, 213, 215, 216, 218, 219, 221, 222, 286, 22648, 22649, + 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, 22835, 22836, 22839, + 22840, +}; + +static const unsigned short dep111[] = { + 11, 12, 13, 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 212, 214, 215, 217, + 218, 220, 221, 223, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, 4136, 16530, + 16532, 16533, 16535, 22828, 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep112[] = { + 16, 99, 215, 216, 286, 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, + 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep113[] = { + 12, 19, 20, 41, 42, 99, 160, 164, 177, 187, 215, 217, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 4136, 16530, 16532, 16533, 16535, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep114[] = { + 17, 99, 218, 219, 286, 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, + 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep115[] = { + 13, 19, 20, 41, 42, 99, 160, 164, 177, 187, 218, 220, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 4136, 16530, 16532, 16533, 16535, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep116[] = { + 18, 99, 221, 222, 286, 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, + 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep117[] = { + 14, 19, 20, 41, 42, 99, 160, 164, 177, 187, 221, 223, 286, 2137, 2138, 2139, + 2168, 2169, 2172, 2175, 4136, 16530, 16532, 16533, 16535, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep118[] = { + 99, 286, 2168, 2169, 2170, 2172, 2173, 2175, 2176, 2348, 2351, 2352, 2355, + 2356, 2359, 2360, +}; + +static const unsigned short dep119[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, + 2348, 2351, 2352, 2355, 2356, 2359, 2360, 4136, 16530, 16532, 16533, 16535, + +}; + +static const unsigned short dep120[] = { + 99, 286, 22648, 22649, 22650, 22652, 22653, 22655, 22656, 22828, 22831, 22832, + 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep121[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, + 4136, 16530, 16532, 16533, 16535, 22828, 22831, 22832, 22835, 22836, 22839, + 22840, +}; + +static const unsigned short dep122[] = { + 19, 20, 41, 42, 99, 160, 164, 177, 187, 286, 2137, 2138, 2139, 2168, 2169, + 2172, 2175, 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, + +}; + +static const unsigned short dep123[] = { + 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep124[] = { + 99, 286, 2084, 2085, 2289, 2290, +}; + +static const unsigned short dep125[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2288, 2290, 4136, 20618, +}; + +static const unsigned short dep126[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2083, 2085, 2168, 2169, 2172, 2175, 2331, + 4136, 20618, +}; + +static const unsigned short dep127[] = { + 99, 286, 14457, 14459, 14460, 14462, 14463, 14465, 14639, 14640, 14643, 14644, + 14647, 14648, +}; + +static const unsigned short dep128[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 4136, 14639, 14640, + 14643, 14644, 14647, 14648, 20618, 24696, 24697, 24700, 24703, +}; + +static const unsigned short dep129[] = { + 99, 124, 126, 127, 129, 286, 307, 308, 311, 312, +}; + +static const unsigned short dep130[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 307, 308, 311, 312, 4136, 24696, 24697, + 24700, 24703, +}; + +static const unsigned short dep131[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 2331, 4136, 20618, + +}; + +static const unsigned short dep132[] = { + 41, 42, 99, 121, 124, 127, 160, 164, 177, 187, 286, 2331, 4136, 20618, 24696, + +}; + +static const unsigned short dep133[] = { + 6, 24, 26, 27, 99, 203, 229, 232, 286, 2082, 2287, +}; + +static const unsigned short dep134[] = { + 41, 42, 99, 160, 164, 177, 187, 203, 229, 231, 286, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 2287, 4136, 20618, +}; + +static const unsigned short dep135[] = { + 6, 24, 25, 26, 41, 42, 99, 160, 164, 177, 187, 286, 2082, 2168, 2169, 2172, + 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep136[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 2348, 2351, 2352, + 2355, 2356, 2359, 2360, 4136, +}; + +static const unsigned short dep137[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 4136, 22828, + 22831, 22832, 22835, 22836, 22839, 22840, +}; + +static const unsigned short dep138[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 2348, 2349, 2352, + 2353, 2356, 2357, 2360, 4136, +}; + +static const unsigned short dep139[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 2348, 2350, 2351, + 2354, 2355, 2358, 2359, 4136, +}; + +static const unsigned short dep140[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2168, 2169, 2172, 2175, 2348, 2349, 2350, + 2351, 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 4136, +}; + +static const unsigned short dep141[] = { + 0, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2168, 2169, 2172, 2175, + 4136, +}; + +static const unsigned short dep142[] = { + 0, 99, 197, 286, +}; + +static const unsigned short dep143[] = { + 0, 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 197, 286, 2168, 2169, 2172, + 2175, 4136, +}; + +static const unsigned short dep144[] = { + 41, 42, 99, 160, 164, 177, 187, 197, 286, 2168, 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep145[] = { + 2, 28, 99, 199, 233, 286, 28868, 29022, +}; + +static const unsigned short dep146[] = { + 1, 2, 28, 29, 99, 160, 164, 177, 179, 180, 187, 199, 233, 286, 28868, 29022, + +}; + +static const unsigned short dep147[] = { + 1, 28, 29, 39, 41, 42, 99, 160, 164, 177, 179, 180, 187, 199, 233, 286, 4136, + 28868, 29022, +}; + +static const unsigned short dep148[] = { + 0, 41, 42, 99, 160, 164, 177, 187, 197, 286, 2168, 2169, 2172, 2175, 4136, + +}; + +static const unsigned short dep149[] = { + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 32, 99, 198, 199, 200, 201, 202, 204, 205, 206, 207, 208, + 209, 210, 211, 213, 214, 216, 217, 219, 220, 222, 223, 224, 225, 226, 227, + 233, 234, 235, 236, 237, 286, 2071, 2082, 2276, 2287, 28868, 29022, +}; + +static const unsigned short dep150[] = { + 29, 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 198, 199, 200, 201, + 202, 204, 205, 206, 207, 208, 209, 210, 211, 213, 214, 216, 217, 219, 220, + 222, 223, 224, 225, 226, 227, 233, 234, 235, 236, 237, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2276, 2287, 4136, 20618, 28868, 29022, +}; + +static const unsigned short dep151[] = { + 99, 286, 14466, 14468, 14470, 14472, 14507, 14508, 14527, 14649, 14650, 14670, + 14671, 14673, 14674, 14683, +}; + +static const unsigned short dep152[] = { + 41, 42, 99, 160, 164, 177, 185, 186, 187, 286, 2168, 2169, 2172, 2175, 4136, + 14649, 14650, 14670, 14671, 14673, 14674, 14683, +}; + +static const unsigned short dep153[] = { + 14466, 14468, 14470, 14472, 14507, 14508, 14527, 14649, 14650, 14670, 14671, + 14673, 14674, 14683, +}; + +static const unsigned short dep154[] = { + 185, 186, 14649, 14650, 14670, 14671, 14673, 14674, 14683, +}; + +static const unsigned short dep155[] = { + 99, 286, 14467, 14468, 14471, 14472, 14482, 14483, 14485, 14486, 14488, 14489, + 14491, 14492, 14495, 14497, 14498, 14507, 14508, 14509, 14510, 14512, 14517, + 14518, 14520, 14521, 14527, 14649, 14650, 14656, 14657, 14658, 14659, 14661, + 14663, 14670, 14671, 14673, 14674, 14675, 14676, 14679, 14680, 14683, +}; + +static const unsigned short dep156[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2168, 2169, 2172, + 2175, 4136, 14649, 14650, 14656, 14657, 14658, 14659, 14661, 14663, 14670, + 14671, 14673, 14674, 14675, 14676, 14679, 14680, 14683, 34890, +}; + +static const unsigned short dep157[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2168, 2169, 2172, + 2175, 4136, 14649, 14650, 14656, 14657, 14658, 14659, 14661, 14663, 14670, + 14671, 14673, 14674, 14675, 14676, 14679, 14680, 14683, +}; + +static const unsigned short dep158[] = { + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 32, 41, 42, 99, 139, 140, 160, 164, 177, 182, 183, 187, 192, + 193, 286, 2071, 2082, 2168, 2169, 2172, 2175, 2331, 4136, 20618, 28868, +}; + +static const unsigned short dep159[] = { + 44, 45, 46, 47, 48, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, + 65, 66, 67, 69, 71, 72, 73, 74, 75, 96, 98, 99, 246, 247, 248, 249, 250, 251, + 252, 253, 254, 255, 256, 257, 259, 260, 261, 262, 263, 265, 267, 268, 269, + 285, 286, 2118, 2314, +}; + +static const unsigned short dep160[] = { + 41, 42, 98, 99, 139, 140, 160, 162, 163, 164, 177, 187, 192, 193, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 259, 260, 261, 262, 263, + 265, 267, 268, 269, 285, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2314, + 4136, 20618, +}; + +static const unsigned short dep161[] = { + 61, 97, 99, 258, 285, 286, 2142, 2331, +}; + +static const unsigned short dep162[] = { + 41, 42, 44, 45, 47, 49, 50, 52, 53, 54, 55, 56, 58, 59, 62, 63, 65, 66, 67, + 68, 69, 71, 72, 73, 96, 97, 99, 139, 140, 160, 162, 163, 164, 177, 187, 192, + 193, 258, 285, 286, 2109, 2118, 2168, 2169, 2172, 2175, 2331, 4136, 20618, + +}; + +static const unsigned short dep163[] = { + 2, 28, 42, 99, 199, 233, 244, 286, 2142, 2331, 28868, 29022, +}; + +static const unsigned short dep164[] = { + 2, 25, 26, 28, 29, 39, 41, 42, 99, 160, 164, 177, 179, 180, 187, 199, 233, + 244, 286, 2331, 4136, 20618, 28868, 29022, +}; + +static const unsigned short dep165[] = { + 99, 131, 132, 135, 136, 142, 143, 146, 147, 149, 150, 152, 153, 155, 156, + 159, 161, 162, 167, 168, 171, 172, 173, 174, 176, 178, 179, 181, 182, 184, + 185, 188, 189, 191, 286, 313, 314, 318, 320, 321, 322, 323, 325, 327, 331, + 334, 335, 337, 338, 339, 340, 342, 343, 344, 346, 347, +}; + +static const unsigned short dep166[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 313, 314, 318, 320, + 321, 322, 323, 325, 327, 331, 334, 335, 337, 338, 339, 340, 342, 343, 344, + 346, 347, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, 34890, +}; + +static const unsigned short dep167[] = { + 99, 130, 132, 134, 136, 171, 172, 191, 286, 313, 314, 334, 335, 337, 338, + 347, +}; + +static const unsigned short dep168[] = { + 41, 42, 99, 160, 164, 177, 185, 186, 187, 286, 313, 314, 334, 335, 337, 338, + 347, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep169[] = { + 41, 42, 99, 132, 133, 136, 137, 139, 140, 143, 144, 147, 148, 150, 151, 153, + 154, 156, 157, 159, 160, 161, 163, 164, 166, 167, 169, 170, 171, 172, 174, + 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, 189, 190, 191, 192, 193, + 286, 2168, 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep170[] = { + 41, 42, 99, 132, 133, 136, 137, 160, 164, 171, 172, 177, 187, 191, 286, 2168, + 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep171[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 113, 139, 140, 155, 157, 160, 164, 173, 175, + 177, 187, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep172[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 113, 139, 140, 141, 142, 144, 145, 155, 157, + 160, 164, 173, 175, 177, 187, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 4136, 20618, +}; + +static const unsigned short dep173[] = { + 79, 80, 99, 103, 104, 273, 274, 286, 288, 289, +}; + +static const unsigned short dep174[] = { + 41, 42, 48, 64, 80, 82, 88, 99, 101, 104, 139, 140, 160, 162, 163, 164, 177, + 187, 192, 193, 194, 273, 274, 286, 288, 289, 2140, 2141, 2142, 2168, 2169, + 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep175[] = { + 41, 42, 48, 64, 80, 82, 99, 101, 104, 106, 108, 139, 140, 160, 162, 163, 164, + 177, 187, 192, 193, 194, 273, 274, 286, 288, 289, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep176[] = { + 99, 286, 12482, 12483, 12637, +}; + +static const unsigned short dep177[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 12637, 20618, +}; + +static const unsigned short dep178[] = { + 99, 286, 6221, 6222, 6415, +}; + +static const unsigned short dep179[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 6415, 20618, +}; + +static const unsigned short dep180[] = { + 99, 286, 6239, 6428, +}; + +static const unsigned short dep181[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 6428, 20618, +}; + +static const unsigned short dep182[] = { + 99, 286, 6257, 6258, 6259, 6260, 6439, 6441, 8488, +}; + +static const unsigned short dep183[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 6260, 6440, 6441, 8306, 8487, 20618, +}; + +static const unsigned short dep184[] = { + 99, 286, 6261, 6262, 6442, +}; + +static const unsigned short dep185[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 6442, 20618, +}; + +static const unsigned short dep186[] = { + 99, 286, 6263, 6443, +}; + +static const unsigned short dep187[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 6443, 20618, +}; + +static const unsigned short dep188[] = { + 99, 286, 10352, 10534, +}; + +static const unsigned short dep189[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 10534, 20618, +}; + +static const unsigned short dep190[] = { + 79, 80, 84, 85, 99, 103, 104, 273, 274, 276, 277, 286, 288, 289, +}; + +static const unsigned short dep191[] = { + 41, 42, 48, 64, 80, 82, 85, 88, 99, 101, 104, 139, 140, 160, 162, 163, 164, + 177, 187, 192, 193, 194, 273, 274, 276, 278, 286, 288, 289, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep192[] = { + 79, 80, 99, 103, 104, 106, 107, 273, 274, 286, 288, 289, 290, 291, +}; + +static const unsigned short dep193[] = { + 41, 42, 48, 64, 80, 82, 99, 101, 104, 106, 108, 139, 140, 160, 162, 163, 164, + 177, 187, 192, 193, 194, 273, 274, 286, 288, 289, 290, 291, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep194[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 12483, 20618, +}; + +static const unsigned short dep195[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 6221, 20618, +}; + +static const unsigned short dep196[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 6239, 20618, +}; + +static const unsigned short dep197[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 6259, 8305, 20618, +}; + +static const unsigned short dep198[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 6261, 20618, +}; + +static const unsigned short dep199[] = { + 41, 42, 99, 139, 140, 160, 164, 177, 185, 186, 187, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 6262, 6263, 20618, +}; + +static const unsigned short dep200[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2331, 4136, 10352, 20618, +}; + +static const unsigned short dep201[] = { + 41, 42, 99, 160, 164, 177, 187, 192, 193, 286, 2140, 2141, 2142, 2168, 2169, + 2172, 2175, 2331, 4136, 6187, 20618, +}; + +static const unsigned short dep202[] = { + 79, 81, 82, 99, 100, 101, 102, 272, 273, 286, 287, 288, +}; + +static const unsigned short dep203[] = { + 41, 42, 80, 81, 85, 87, 99, 102, 104, 106, 109, 139, 140, 160, 164, 177, 187, + 192, 193, 194, 272, 274, 286, 287, 289, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 4136, 20618, +}; + +static const unsigned short dep204[] = { + 79, 81, 82, 83, 99, 100, 101, 102, 105, 272, 273, 275, 286, 287, 288, +}; + +static const unsigned short dep205[] = { + 41, 42, 80, 81, 83, 85, 87, 99, 102, 104, 105, 106, 109, 139, 140, 160, 164, + 177, 187, 192, 193, 194, 272, 274, 275, 286, 287, 289, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep206[] = { + 79, 81, 82, 86, 87, 88, 99, 100, 101, 102, 272, 273, 278, 279, 286, 287, 288, + +}; + +static const unsigned short dep207[] = { + 41, 42, 80, 81, 85, 87, 99, 102, 104, 139, 140, 160, 164, 177, 187, 192, 193, + 194, 272, 274, 277, 279, 286, 287, 289, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 4136, 20618, +}; + +static const unsigned short dep208[] = { + 79, 81, 82, 99, 100, 101, 102, 108, 109, 110, 272, 273, 286, 287, 288, 291, + 292, +}; + +static const unsigned short dep209[] = { + 41, 42, 80, 81, 99, 102, 104, 106, 109, 139, 140, 160, 164, 177, 187, 192, + 193, 194, 272, 274, 286, 287, 289, 290, 292, 2140, 2141, 2142, 2168, 2169, + 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep210[] = { + 41, 42, 47, 72, 99, 160, 164, 177, 187, 192, 193, 194, 286, 2140, 2141, 2142, + 2168, 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep211[] = { + 41, 42, 99, 160, 164, 177, 187, 192, 193, 194, 286, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep212[] = { + 41, 42, 72, 79, 84, 86, 99, 139, 140, 155, 157, 160, 164, 177, 187, 192, 193, + 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep213[] = { + 41, 42, 99, 160, 164, 166, 177, 187, 188, 190, 286, 2137, 2138, 2139, 2140, + 2141, 2142, 2168, 2169, 2172, 2175, 4136, 16530, 16532, 16533, 16535, 20618, + +}; + +static const unsigned short dep214[] = { + 41, 42, 72, 79, 84, 86, 99, 155, 157, 160, 164, 177, 187, 194, 286, 2140, + 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep215[] = { + 41, 42, 80, 81, 99, 102, 139, 140, 160, 164, 177, 187, 192, 193, 272, 274, + 286, 287, 289, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, +}; + +static const unsigned short dep216[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep217[] = { + 5, 99, 202, 286, 2142, 2331, +}; + +static const unsigned short dep218[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 202, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, 20618, + +}; + +static const unsigned short dep219[] = { + 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, 187, + 192, 193, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep220[] = { + 0, 99, 197, 286, 2142, 2331, +}; + +static const unsigned short dep221[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep222[] = { + 0, 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, + 137, 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, + 187, 192, 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, + 4136, 20618, +}; + +static const unsigned short dep223[] = { + 32, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, 20618, + +}; + +static const unsigned short dep224[] = { + 0, 99, 197, 286, 2331, 26717, +}; + +static const unsigned short dep225[] = { + 0, 99, 111, 197, 286, 293, +}; + +static const unsigned short dep226[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, + +}; + +static const unsigned short dep227[] = { + 0, 5, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, + +}; + +static const unsigned short dep228[] = { + 0, 32, 99, 111, 197, 237, 286, 293, +}; + +static const unsigned short dep229[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 237, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 4136, 20618, + +}; + +static const unsigned short dep230[] = { + 0, 99, 111, 197, 286, 293, 2142, 2331, +}; + +static const unsigned short dep231[] = { + 0, 3, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep232[] = { + 0, 3, 5, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, + 137, 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, + 192, 193, 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, + 4136, 20618, +}; + +static const unsigned short dep233[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep234[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2137, 2138, 2139, 2168, 2169, 2172, 2175, + 2331, 4136, 16530, 16532, 16533, 16535, 20618, +}; + +static const unsigned short dep235[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep236[] = { + 0, 32, 99, 111, 197, 237, 286, 293, 2142, 2331, +}; + +static const unsigned short dep237[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 237, 286, 293, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2331, 4136, + 20618, +}; + +static const unsigned short dep238[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 4136, 16530, 16532, + 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep239[] = { + 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, 187, + 192, 193, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 4136, + 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep240[] = { + 0, 99, 197, 286, 2138, 2329, 18603, 18604, 18765, 18766, 18768, 18769, +}; + +static const unsigned short dep241[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 4136, + 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep242[] = { + 0, 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, + 137, 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, + 187, 192, 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, + 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep243[] = { + 0, 99, 197, 286, 2139, 2329, 18603, 18604, 18765, 18766, 18768, 18769, +}; + +static const unsigned short dep244[] = { + 99, 286, 2138, 2142, 2329, 2331, 18603, 18604, 18765, 18766, 18768, 18769, + +}; + +static const unsigned short dep245[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 2331, 4136, 16530, + 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep246[] = { + 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, 187, + 192, 193, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 2331, + 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep247[] = { + 0, 99, 197, 286, 2138, 2142, 2329, 2331, 18603, 18604, 18765, 18766, 18768, + 18769, +}; + +static const unsigned short dep248[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, 137, + 139, 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, + 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, 2331, + 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, +}; + +static const unsigned short dep249[] = { + 0, 41, 42, 45, 72, 78, 79, 84, 86, 99, 111, 113, 130, 131, 133, 134, 135, + 137, 139, 140, 141, 142, 144, 145, 155, 157, 158, 160, 164, 173, 175, 177, + 187, 192, 193, 194, 197, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, 2329, + 2331, 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, + +}; + +static const unsigned short dep250[] = { + 0, 99, 197, 286, 2139, 2142, 2329, 2331, 18603, 18604, 18765, 18766, 18768, + 18769, +}; + +static const unsigned short dep251[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 286, 293, 2137, 2138, 2139, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 4136, 16530, 16532, 16533, 16535, 20618, +}; + +static const unsigned short dep252[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 139, 140, 141, 142, 144, 145, 155, 157, 158, + 160, 164, 173, 175, 177, 187, 194, 286, 2168, 2169, 2172, 2175, 4136, +}; + +static const unsigned short dep253[] = { + 41, 42, 72, 78, 79, 84, 86, 99, 139, 140, 141, 142, 144, 145, 155, 157, 158, + 160, 164, 173, 175, 177, 187, 194, 286, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 2331, 4136, 20618, +}; + +static const unsigned short dep254[] = { + 41, 42, 99, 160, 164, 177, 187, 286, 2140, 2141, 2142, 2168, 2169, 2172, 2175, + 2329, 4136, 16530, 16532, 16533, 16535, 18765, 18767, 18768, 18770, 20618, + +}; + +static const unsigned short dep255[] = { + 0, 41, 42, 72, 78, 79, 84, 86, 99, 113, 130, 131, 133, 134, 135, 137, 139, + 140, 141, 142, 144, 145, 155, 157, 160, 164, 173, 175, 177, 187, 192, 193, + 194, 197, 286, 293, 2137, 2138, 2139, 2140, 2141, 2142, 2168, 2169, 2172, + 2175, 2331, 4136, 16530, 16532, 16533, 16535, 20618, +}; + +static const unsigned short dep256[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 26, 27, 28, 29, 30, 31, 32, 99, 198, 199, 200, 201, 202, 203, 204, + 205, 206, 207, 208, 209, 210, 211, 213, 214, 216, 217, 219, 220, 222, 223, + 224, 225, 226, 227, 229, 232, 233, 234, 235, 236, 237, 286, 2071, 2082, 2142, + 2276, 2287, 2331, 28868, 29022, +}; + +static const unsigned short dep257[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 25, 26, 28, 29, 30, 31, 32, 41, 42, 99, 139, 140, 160, 164, 177, 182, + 183, 187, 192, 193, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, + 209, 210, 211, 213, 214, 216, 217, 219, 220, 222, 223, 224, 225, 226, 227, + 229, 231, 233, 234, 235, 236, 237, 286, 2071, 2082, 2140, 2141, 2142, 2168, + 2169, 2172, 2175, 2276, 2287, 2331, 4136, 20618, 28868, 29022, +}; + +#define NELS(X) (sizeof(X)/sizeof(X[0])) +static const struct ia64_opcode_dependency +op_dependencies[] = { + { NELS(dep1), dep1, NELS(dep0), dep0, }, + { NELS(dep3), dep3, NELS(dep2), dep2, }, + { NELS(dep5), dep5, NELS(dep4), dep4, }, + { NELS(dep7), dep7, NELS(dep6), dep6, }, + { NELS(dep9), dep9, NELS(dep8), dep8, }, + { NELS(dep11), dep11, NELS(dep10), dep10, }, + { NELS(dep13), dep13, NELS(dep12), dep12, }, + { NELS(dep15), dep15, NELS(dep14), dep14, }, + { NELS(dep17), dep17, NELS(dep16), dep16, }, + { NELS(dep19), dep19, NELS(dep18), dep18, }, + { NELS(dep21), dep21, NELS(dep20), dep20, }, + { NELS(dep23), dep23, NELS(dep22), dep22, }, + { NELS(dep25), dep25, NELS(dep24), dep24, }, + { NELS(dep27), dep27, NELS(dep26), dep26, }, + { NELS(dep29), dep29, NELS(dep28), dep28, }, + { NELS(dep30), dep30, NELS(dep12), dep12, }, + { NELS(dep32), dep32, NELS(dep31), dep31, }, + { NELS(dep34), dep34, NELS(dep33), dep33, }, + { NELS(dep35), dep35, NELS(dep12), dep12, }, + { NELS(dep37), dep37, NELS(dep36), dep36, }, + { NELS(dep39), dep39, NELS(dep38), dep38, }, + { NELS(dep41), dep41, NELS(dep40), dep40, }, + { NELS(dep42), dep42, NELS(dep31), dep31, }, + { NELS(dep43), dep43, NELS(dep33), dep33, }, + { NELS(dep45), dep45, NELS(dep44), dep44, }, + { NELS(dep47), dep47, NELS(dep46), dep46, }, + { NELS(dep49), dep49, NELS(dep48), dep48, }, + { NELS(dep51), dep51, NELS(dep50), dep50, }, + { NELS(dep53), dep53, NELS(dep52), dep52, }, + { NELS(dep55), dep55, NELS(dep54), dep54, }, + { NELS(dep57), dep57, NELS(dep56), dep56, }, + { NELS(dep59), dep59, NELS(dep58), dep58, }, + { NELS(dep61), dep61, NELS(dep60), dep60, }, + { NELS(dep63), dep63, NELS(dep62), dep62, }, + { NELS(dep65), dep65, NELS(dep64), dep64, }, + { NELS(dep67), dep67, NELS(dep66), dep66, }, + { NELS(dep68), dep68, NELS(dep33), dep33, }, + { NELS(dep70), dep70, NELS(dep69), dep69, }, + { NELS(dep72), dep72, NELS(dep71), dep71, }, + { NELS(dep74), dep74, NELS(dep73), dep73, }, + { NELS(dep76), dep76, NELS(dep75), dep75, }, + { NELS(dep77), dep77, NELS(dep33), dep33, }, + { NELS(dep79), dep79, NELS(dep78), dep78, }, + { NELS(dep81), dep81, NELS(dep80), dep80, }, + { NELS(dep83), dep83, NELS(dep82), dep82, }, + { NELS(dep84), dep84, NELS(dep33), dep33, }, + { NELS(dep85), dep85, NELS(dep33), dep33, }, + { NELS(dep86), dep86, NELS(dep33), dep33, }, + { NELS(dep87), dep87, NELS(dep33), dep33, }, + { NELS(dep89), dep89, NELS(dep88), dep88, }, + { NELS(dep91), dep91, NELS(dep90), dep90, }, + { NELS(dep93), dep93, NELS(dep92), dep92, }, + { NELS(dep95), dep95, NELS(dep94), dep94, }, + { NELS(dep97), dep97, NELS(dep96), dep96, }, + { NELS(dep99), dep99, NELS(dep98), dep98, }, + { NELS(dep101), dep101, NELS(dep100), dep100, }, + { NELS(dep103), dep103, NELS(dep102), dep102, }, + { NELS(dep105), dep105, NELS(dep104), dep104, }, + { NELS(dep107), dep107, NELS(dep106), dep106, }, + { NELS(dep109), dep109, NELS(dep108), dep108, }, + { NELS(dep111), dep111, NELS(dep110), dep110, }, + { NELS(dep113), dep113, NELS(dep112), dep112, }, + { NELS(dep115), dep115, NELS(dep114), dep114, }, + { NELS(dep117), dep117, NELS(dep116), dep116, }, + { NELS(dep119), dep119, NELS(dep118), dep118, }, + { NELS(dep121), dep121, NELS(dep120), dep120, }, + { NELS(dep122), dep122, NELS(dep64), dep64, }, + { NELS(dep123), dep123, NELS(dep33), dep33, }, + { NELS(dep125), dep125, NELS(dep124), dep124, }, + { NELS(dep126), dep126, NELS(dep0), dep0, }, + { NELS(dep128), dep128, NELS(dep127), dep127, }, + { NELS(dep130), dep130, NELS(dep129), dep129, }, + { NELS(dep131), dep131, NELS(dep0), dep0, }, + { NELS(dep132), dep132, NELS(dep0), dep0, }, + { NELS(dep134), dep134, NELS(dep133), dep133, }, + { NELS(dep135), dep135, NELS(dep0), dep0, }, + { NELS(dep136), dep136, NELS(dep2), dep2, }, + { NELS(dep137), dep137, NELS(dep4), dep4, }, + { NELS(dep138), dep138, NELS(dep6), dep6, }, + { NELS(dep139), dep139, NELS(dep8), dep8, }, + { NELS(dep140), dep140, NELS(dep10), dep10, }, + { NELS(dep141), dep141, NELS(dep33), dep33, }, + { NELS(dep143), dep143, NELS(dep142), dep142, }, + { NELS(dep144), dep144, NELS(dep142), dep142, }, + { NELS(dep146), dep146, NELS(dep145), dep145, }, + { NELS(dep147), dep147, NELS(dep145), dep145, }, + { NELS(dep148), dep148, NELS(dep142), dep142, }, + { NELS(dep150), dep150, NELS(dep149), dep149, }, + { NELS(dep152), dep152, NELS(dep151), dep151, }, + { NELS(dep154), dep154, NELS(dep153), dep153, }, + { NELS(dep156), dep156, NELS(dep155), dep155, }, + { NELS(dep157), dep157, NELS(dep155), dep155, }, + { NELS(dep158), dep158, NELS(dep0), dep0, }, + { NELS(dep160), dep160, NELS(dep159), dep159, }, + { NELS(dep162), dep162, NELS(dep161), dep161, }, + { NELS(dep164), dep164, NELS(dep163), dep163, }, + { NELS(dep166), dep166, NELS(dep165), dep165, }, + { NELS(dep168), dep168, NELS(dep167), dep167, }, + { NELS(dep169), dep169, NELS(dep0), dep0, }, + { NELS(dep170), dep170, NELS(dep0), dep0, }, + { NELS(dep171), dep171, NELS(dep0), dep0, }, + { NELS(dep172), dep172, NELS(dep33), dep33, }, + { NELS(dep174), dep174, NELS(dep173), dep173, }, + { NELS(dep175), dep175, NELS(dep173), dep173, }, + { NELS(dep177), dep177, NELS(dep176), dep176, }, + { NELS(dep179), dep179, NELS(dep178), dep178, }, + { NELS(dep181), dep181, NELS(dep180), dep180, }, + { NELS(dep183), dep183, NELS(dep182), dep182, }, + { NELS(dep185), dep185, NELS(dep184), dep184, }, + { NELS(dep187), dep187, NELS(dep186), dep186, }, + { NELS(dep189), dep189, NELS(dep188), dep188, }, + { NELS(dep191), dep191, NELS(dep190), dep190, }, + { NELS(dep193), dep193, NELS(dep192), dep192, }, + { NELS(dep194), dep194, NELS(dep0), dep0, }, + { NELS(dep195), dep195, NELS(dep0), dep0, }, + { NELS(dep196), dep196, NELS(dep0), dep0, }, + { NELS(dep197), dep197, NELS(dep0), dep0, }, + { NELS(dep198), dep198, NELS(dep0), dep0, }, + { NELS(dep199), dep199, NELS(dep0), dep0, }, + { NELS(dep200), dep200, NELS(dep0), dep0, }, + { NELS(dep201), dep201, NELS(dep0), dep0, }, + { NELS(dep203), dep203, NELS(dep202), dep202, }, + { NELS(dep205), dep205, NELS(dep204), dep204, }, + { NELS(dep207), dep207, NELS(dep206), dep206, }, + { NELS(dep209), dep209, NELS(dep208), dep208, }, + { NELS(dep210), dep210, NELS(dep0), dep0, }, + { NELS(dep211), dep211, NELS(dep0), dep0, }, + { NELS(dep212), dep212, NELS(dep0), dep0, }, + { NELS(dep213), dep213, NELS(dep33), dep33, }, + { NELS(dep214), dep214, NELS(dep33), dep33, }, + { NELS(dep215), dep215, NELS(dep202), dep202, }, + { NELS(dep216), dep216, NELS(dep0), dep0, }, + { NELS(dep218), dep218, NELS(dep217), dep217, }, + { NELS(dep219), dep219, NELS(dep0), dep0, }, + { NELS(dep221), dep221, NELS(dep220), dep220, }, + { NELS(dep222), dep222, NELS(dep220), dep220, }, + { NELS(dep223), dep223, NELS(dep0), dep0, }, + { NELS(dep221), dep221, NELS(dep224), dep224, }, + { NELS(dep226), dep226, NELS(dep225), dep225, }, + { NELS(dep227), dep227, NELS(dep225), dep225, }, + { NELS(dep229), dep229, NELS(dep228), dep228, }, + { NELS(dep231), dep231, NELS(dep230), dep230, }, + { NELS(dep232), dep232, NELS(dep230), dep230, }, + { NELS(dep233), dep233, NELS(dep230), dep230, }, + { NELS(dep234), dep234, NELS(dep0), dep0, }, + { NELS(dep235), dep235, NELS(dep230), dep230, }, + { NELS(dep237), dep237, NELS(dep236), dep236, }, + { NELS(dep238), dep238, NELS(dep64), dep64, }, + { NELS(dep239), dep239, NELS(dep64), dep64, }, + { NELS(dep241), dep241, NELS(dep240), dep240, }, + { NELS(dep242), dep242, NELS(dep240), dep240, }, + { NELS(dep241), dep241, NELS(dep243), dep243, }, + { NELS(dep245), dep245, NELS(dep244), dep244, }, + { NELS(dep246), dep246, NELS(dep244), dep244, }, + { NELS(dep248), dep248, NELS(dep247), dep247, }, + { NELS(dep249), dep249, NELS(dep247), dep247, }, + { NELS(dep248), dep248, NELS(dep250), dep250, }, + { NELS(dep251), dep251, NELS(dep225), dep225, }, + { NELS(dep252), dep252, NELS(dep33), dep33, }, + { NELS(dep253), dep253, NELS(dep0), dep0, }, + { NELS(dep254), dep254, NELS(dep64), dep64, }, + { NELS(dep255), dep255, NELS(dep230), dep230, }, + { 0, NULL, 0, NULL, }, + { NELS(dep257), dep257, NELS(dep256), dep256, }, +}; + +static const struct ia64_completer_table +completer_table[] = { + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 594, -1, 0, 1, 6 }, + { 0x0, 0x0, 0, 657, -1, 0, 1, 18 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, + { 0x0, 0x0, 0, 756, -1, 0, 1, 18 }, + { 0x0, 0x0, 0, 2198, -1, 0, 1, 10 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, + { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 2406, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 1140, -1, 0, 1, 129 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 45 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, + { 0x0, 0x0, 0, 2246, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2473, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2250, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, 2252, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2482, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2485, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2507, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 2510, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 36 }, + { 0x0, 0x0, 0, 2518, -1, 0, 1, 30 }, + { 0x0, 0x0, 0, 1409, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 83 }, + { 0x0, 0x0, 0, 1457, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1466, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1475, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1477, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 1479, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 1488, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1497, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1506, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1515, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1524, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1533, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1543, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1553, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1563, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1572, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1578, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1584, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1590, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1596, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1602, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1608, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1614, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1620, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1626, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1632, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1638, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1644, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1650, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1656, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1662, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 1668, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1674, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, 1678, -1, 0, 1, 158 }, + { 0x0, 0x0, 0, 1682, -1, 0, 1, 159 }, + { 0x0, 0x0, 0, 1686, -1, 0, 1, 159 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 85 }, + { 0x0, 0x0, 0, 258, -1, 0, 1, 41 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, + { 0x1, 0x1, 0, 1166, -1, 20, 1, 68 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 73 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 93 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 94 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 96 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 97 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 98 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 99 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 104 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 105 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 106 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 107 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 108 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 109 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 110 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 113 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 114 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 115 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 116 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 117 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 118 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 119 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 120 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 163 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 163 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 163 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2858, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2859, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2210, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2211, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2873, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2874, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2875, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2876, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2877, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2860, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2861, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 11 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 91 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 89 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, 2879, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 90 }, + { 0x0, 0x0, 0, 1966, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1968, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1970, -1, 0, 1, 139 }, + { 0x0, 0x0, 0, 1972, -1, 0, 1, 139 }, + { 0x0, 0x0, 0, 1974, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1976, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1978, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1980, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1983, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1986, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1989, -1, 0, 1, 157 }, + { 0x0, 0x0, 0, 1990, -1, 0, 1, 161 }, + { 0x0, 0x0, 0, 1991, -1, 0, 1, 157 }, + { 0x0, 0x0, 0, 1992, -1, 0, 1, 161 }, + { 0x0, 0x0, 0, 1993, -1, 0, 1, 157 }, + { 0x0, 0x0, 0, 1994, -1, 0, 1, 161 }, + { 0x0, 0x0, 0, 1995, -1, 0, 1, 157 }, + { 0x0, 0x0, 0, 1996, -1, 0, 1, 161 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 88 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 127 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 125 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 127 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 126 }, + { 0x0, 0x0, 0, 1687, -1, 0, 1, 143 }, + { 0x0, 0x0, 0, 1688, -1, 0, 1, 143 }, + { 0x0, 0x0, 0, 1689, -1, 0, 1, 143 }, + { 0x0, 0x0, 0, 1690, -1, 0, 1, 143 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 1, 224, -1, 0, 1, 12 }, + { 0x0, 0x0, 1, 225, -1, 0, 1, 14 }, + { 0x1, 0x1, 2, -1, -1, 27, 1, 12 }, + { 0x1, 0x1, 2, -1, -1, 27, 1, 14 }, + { 0x0, 0x0, 3, -1, 1340, 0, 0, -1 }, + { 0x0, 0x0, 3, -1, 1341, 0, 0, -1 }, + { 0x1, 0x1, 3, 2749, 1450, 33, 1, 134 }, + { 0x1, 0x1, 3, 2750, 1459, 33, 1, 134 }, + { 0x1, 0x1, 3, 2751, 1468, 33, 1, 134 }, + { 0x1, 0x1, 3, 2752, 1481, 33, 1, 134 }, + { 0x1, 0x1, 3, 2753, 1490, 33, 1, 134 }, + { 0x1, 0x1, 3, 2754, 1499, 33, 1, 134 }, + { 0x1, 0x1, 3, 2755, 1508, 33, 1, 134 }, + { 0x1, 0x1, 3, 2756, 1517, 33, 1, 134 }, + { 0x1, 0x1, 3, 2757, 1526, 33, 1, 134 }, + { 0x1, 0x1, 3, 2758, 1535, 33, 1, 134 }, + { 0x1, 0x1, 3, 2759, 1545, 33, 1, 134 }, + { 0x1, 0x1, 3, 2760, 1555, 33, 1, 134 }, + { 0x1, 0x1, 3, 2761, 1568, 33, 1, 149 }, + { 0x1, 0x1, 3, 2762, 1574, 33, 1, 154 }, + { 0x1, 0x1, 3, 2763, 1580, 33, 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2314, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2316, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2318, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x0, 0x0, 264, -1, 2320, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2322, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2324, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2326, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2328, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2330, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2332, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2334, 12, 1, 50 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 50 }, + { 0x0, 0x0, 264, -1, 2336, 0, 0, -1 }, + { 0x0, 0x0, 264, -1, 2338, 0, 0, -1 }, + { 0x1, 0x1, 264, -1, 2340, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, 2342, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, + { 0x1, 0x1, 264, 393, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 395, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 517, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 519, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 401, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 403, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 525, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 527, -1, 12, 1, 77 }, + { 0x1, 0x1, 264, 409, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 411, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 533, -1, 12, 1, 2 }, + { 0x1, 0x1, 264, 535, -1, 12, 1, 2 }, + { 0x0, 0x0, 265, -1, 2303, 0, 0, -1 }, + { 0x9, 0x9, 265, -1, 2311, 33, 1, 50 }, + { 0x9, 0x9, 265, -1, 2975, 33, 1, 50 }, + { 0x0, 0x0, 265, 1399, 2376, 0, 0, -1 }, + { 0x3, 0x3, 265, 1400, -1, 27, 1, 50 }, + { 0x0, 0x0, 269, 2856, -1, 0, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 271, 3018, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3019, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3020, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, 3021, -1, 28, 1, 0 }, + { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, + { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, + { 0x0, 0x0, 273, -1, 968, 0, 0, -1 }, + { 0x0, 0x0, 274, 3031, 2833, 0, 0, -1 }, + { 0x0, 0x0, 274, 3032, 2835, 0, 0, -1 }, + { 0x0, 0x0, 275, -1, 2834, 0, 0, -1 }, + { 0x0, 0x0, 275, -1, 2836, 0, 0, -1 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, + { 0x0, 0x0, 281, -1, -1, 0, 1, 34 }, + { 0x0, 0x0, 285, -1, 2350, 0, 1, 30 }, + { 0x0, 0x0, 286, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 286, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 286, 2001, 3000, 0, 1, 1 }, + { 0x0, 0x0, 286, 2002, 3001, 0, 1, 1 }, + { 0x0, 0x0, 286, -1, 518, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 520, 0, 0, -1 }, + { 0x0, 0x0, 286, 2005, 3004, 0, 1, 76 }, + { 0x0, 0x0, 286, 2006, 3005, 0, 1, 76 }, + { 0x0, 0x0, 286, -1, 526, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 528, 0, 0, -1 }, + { 0x0, 0x0, 286, 2009, 3008, 0, 1, 1 }, + { 0x0, 0x0, 286, 2010, 3009, 0, 1, 1 }, + { 0x0, 0x0, 286, -1, 534, 0, 0, -1 }, + { 0x0, 0x0, 286, -1, 536, 0, 0, -1 }, +}; + +static const struct ia64_main_table +main_table[] = { + { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 1, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 2, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 64, 26, 0, 0 }, 0x0, 3, }, + { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 4, }, + { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 5, }, + { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 6, }, + { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 7, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 53, 54, 55 }, 0x221, 8, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 53, 54, 55, 0 }, 0x261, 9, }, + { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 10, }, + { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 11, }, + { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 12, }, + { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 13, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0, 0 }, 0x40, 969, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x0, 825, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x40, 826, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x200, 2234, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x240, 2235, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x0, 582, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x40, 583, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 82, 0, 0, 0, 0 }, 0x40, 990, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x0, 827, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x40, 828, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x210, 3029, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x250, 3030, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x30, 590, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x70, 591, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x230, 588, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x270, 589, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x0, 584, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x40, 585, }, + { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 537, }, + { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 960, }, + { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x2, 1138, }, + { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 1263, }, + { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 70, 0, 0, 0, 0 }, 0x0, 3033, }, + { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 66, 0, 0, 0, 0 }, 0x0, 16, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 83, 0, 0, 0, 0 }, 0x40, 1023, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x0, 829, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x40, 830, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 }, 0x0, 586, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 }, 0x40, 587, }, + { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 16, 78, 0, 0, 0 }, 0x20, 2852, }, + { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 82, 78, 0, 0, 0 }, 0x20, 2853, }, + { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 222, }, + { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2239, }, + { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 24, 82, 0, 0, 0 }, 0x0, 226, }, + { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 18, 82, 0, 0, 0 }, 0x0, 227, }, + { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2240, }, + { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 19, 81, 0, 0, 0 }, 0x0, 2241, }, + { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 25, 81, 0, 0, 0 }, 0x0, 2242, }, + { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 18, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x0, 1222, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 25, 26, 0, 0 }, 0x40, 1223, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 26, 25, 0 }, 0x0, 1181, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 26, 25, 0, 0 }, 0x40, 1182, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 25, 0 }, 0x0, 1090, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 26, 25, 0, 0 }, 0x40, 1091, }, + { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x0, 1052, }, + { 26, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 25, 26, 0, 0 }, 0x40, 1053, }, + { 26, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x40, 1376, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x0, 1092, }, + { 26, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 7, 26, 0, 0 }, 0x40, 1093, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 7, 0 }, 0x40, 1226, }, + { 26, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 26, 7, 0, 0 }, 0x40, 1227, }, + { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x40, 1187, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x0, 1229, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 56, 26, 0, 0 }, 0x40, 1230, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 58, 26, 0 }, 0x0, 1188, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 58, 26, 0, 0 }, 0x40, 1189, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 58, 26, 0 }, 0x0, 1097, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 58, 26, 0, 0 }, 0x40, 1098, }, + { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 56, 26, 0 }, 0x0, 1059, }, + { 26, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 56, 26, 0, 0 }, 0x40, 1060, }, + { 26, 1, 2, 0x0000018a00000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x40, 1381, }, + { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 23, 60, 26, 0 }, 0x0, 1214, }, + { 26, 1, 1, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 60, 26, 0, 0 }, 0x40, 1215, }, + { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 23, 22, 60, 26, 0 }, 0x0, 1125, }, + { 26, 1, 1, 0x000001a800000000ull, 0x000001ee00001000ull, { 23, 60, 26, 0, 0 }, 0x40, 1126, }, + { 26, 1, 2, 0x000001c200000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x40, 1382, }, + { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 7, 26, 0 }, 0x40, 1190, }, + { 26, 1, 1, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 7, 26, 0, 0 }, 0x40, 1191, }, + { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 26, 7, 0 }, 0x40, 1063, }, + { 26, 1, 1, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 26, 7, 0, 0 }, 0x40, 1064, }, + { 26, 1, 2, 0x000001ca00000000ull, 0x000001ee00001000ull, { 23, 22, 56, 26, 0 }, 0x40, 1383, }, + { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x0, 1235, }, + { 27, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 25, 26, 0, 0 }, 0x40, 1236, }, + { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 26, 25, 0 }, 0x0, 1194, }, + { 27, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 26, 25, 0, 0 }, 0x40, 1195, }, + { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 26, 25, 0 }, 0x0, 1103, }, + { 27, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 26, 25, 0, 0 }, 0x40, 1104, }, + { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x0, 1065, }, + { 27, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 25, 26, 0, 0 }, 0x40, 1066, }, + { 27, 1, 2, 0x0000018600000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x40, 1388, }, + { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x0, 1105, }, + { 27, 1, 1, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 7, 26, 0, 0 }, 0x40, 1106, }, + { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 26, 7, 0 }, 0x40, 1239, }, + { 27, 1, 1, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 26, 7, 0, 0 }, 0x40, 1240, }, + { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x40, 1200, }, + { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x0, 1242, }, + { 27, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 56, 26, 0, 0 }, 0x40, 1243, }, + { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 58, 26, 0 }, 0x0, 1201, }, + { 27, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 58, 26, 0, 0 }, 0x40, 1202, }, + { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 58, 26, 0 }, 0x0, 1110, }, + { 27, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 58, 26, 0, 0 }, 0x40, 1111, }, + { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 56, 26, 0 }, 0x0, 1072, }, + { 27, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 56, 26, 0, 0 }, 0x40, 1073, }, + { 27, 1, 2, 0x0000018e00000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x40, 1393, }, + { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 57, 26, 0 }, 0x0, 1259, }, + { 27, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 57, 26, 0, 0 }, 0x40, 1260, }, + { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 59, 26, 0 }, 0x0, 1218, }, + { 27, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 59, 26, 0, 0 }, 0x40, 1219, }, + { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 22, 59, 26, 0 }, 0x0, 1129, }, + { 27, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 59, 26, 0, 0 }, 0x40, 1130, }, + { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 22, 57, 26, 0 }, 0x0, 1088, }, + { 27, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 57, 26, 0, 0 }, 0x40, 1089, }, + { 27, 1, 2, 0x000001c600000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x40, 1394, }, + { 27, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 22, 7, 26, 0 }, 0x40, 1203, }, + { 27, 1, 1, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 7, 26, 0, 0 }, 0x40, 1204, }, + { 27, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 22, 26, 7, 0 }, 0x40, 1076, }, + { 27, 1, 1, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 26, 7, 0, 0 }, 0x40, 1077, }, + { 27, 1, 2, 0x000001ce00000000ull, 0x000001ee00001000ull, { 23, 22, 56, 26, 0 }, 0x40, 1395, }, + { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 28, 25, 1, 2 }, 0x0, 259, }, + { 28, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 260, }, + { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 261, }, + { 29, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 262, }, + { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 263, }, + { 30, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 264, }, + { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 265, }, + { 31, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 266, }, + { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 2, 0 }, 0x0, 267, }, + { 32, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x40, 268, }, + { 34, 4, 0, 0x0000000010000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 19, }, + { 36, 2, 1, 0x00000000c0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 1167, }, + { 37, 2, 1, 0x00000000c8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 1168, }, + { 39, 2, 1, 0x0000008000000000ull, 0x000001e000000000ull, { 24, 25, 26, 47, 73 }, 0x0, 20, }, + { 39, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 24, 25, 45, 74, 0 }, 0x0, 3038, }, + { 39, 2, 1, 0x000000a604000000ull, 0x000001ee04000000ull, { 24, 56, 45, 74, 0 }, 0x0, 3039, }, + { 39, 2, 1, 0x000000ae00000000ull, 0x000001ee00000000ull, { 24, 48, 26, 46, 74 }, 0x0, 21, }, + { 43, 4, 0, 0x0000000080000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x20, 22, }, + { 48, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 24, 26, 77, 74, 0 }, 0x0, 2870, }, + { 50, 5, 1, 0x0000000080000000ull, 0x000001e3f80fe000ull, { 18, 20, 0, 0, 0 }, 0x40, 24, }, + { 51, 5, 1, 0x0000010008000000ull, 0x000001fff8000000ull, { 18, 20, 19, 0, 0 }, 0x40, 2291, }, + { 52, 5, 1, 0x00000000b8000000ull, 0x000001eff8000000ull, { 18, 19, 20, 0, 0 }, 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0x0000002110000000ull, 0x000001eff8000000ull, { 24, 14, 0, 0, 0 }, 0x0, 1270, }, + { 155, 3, 1, 0x0000002160000000ull, 0x000001eff8000000ull, { 17, 25, 0, 0, 0 }, 0x8, 118, }, + { 155, 3, 1, 0x0000002120000000ull, 0x000001eff8000000ull, { 24, 17, 0, 0, 0 }, 0x8, 119, }, + { 155, 3, 1, 0x0000002168000000ull, 0x000001eff8000000ull, { 12, 25, 0, 0, 0 }, 0x8, 120, }, + { 155, 3, 1, 0x0000002148000000ull, 0x000001eff8000000ull, { 13, 25, 0, 0, 0 }, 0x0, 121, }, + { 155, 3, 1, 0x0000002128000000ull, 0x000001eff8000000ull, { 24, 11, 0, 0, 0 }, 0x8, 122, }, + { 155, 3, 1, 0x0000002108000000ull, 0x000001eff8000000ull, { 24, 13, 0, 0, 0 }, 0x0, 123, }, + { 155, 3, 1, 0x0000002000000000ull, 0x000001eff8000000ull, { 38, 25, 0, 0, 0 }, 0x8, 124, }, + { 155, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 30, 25, 0, 0, 0 }, 0x8, 125, }, + { 155, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 33, 25, 0, 0, 0 }, 0x8, 126, }, + { 155, 3, 1, 0x0000002018000000ull, 0x000001eff8000000ull, { 35, 25, 0, 0, 0 }, 0x8, 127, }, + { 155, 3, 1, 0x0000002020000000ull, 0x000001eff8000000ull, { 36, 25, 0, 0, 0 }, 0x8, 128, }, + { 155, 3, 1, 0x0000002028000000ull, 0x000001eff8000000ull, { 37, 25, 0, 0, 0 }, 0x8, 129, }, + { 155, 3, 1, 0x0000002030000000ull, 0x000001eff8000000ull, { 34, 25, 0, 0, 0 }, 0x8, 130, }, + { 155, 3, 1, 0x0000002080000000ull, 0x000001eff8000000ull, { 24, 38, 0, 0, 0 }, 0x8, 131, }, + { 155, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 24, 30, 0, 0, 0 }, 0x8, 132, }, + { 155, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 24, 33, 0, 0, 0 }, 0x8, 133, }, + { 155, 3, 1, 0x0000002098000000ull, 0x000001eff8000000ull, { 24, 35, 0, 0, 0 }, 0x8, 134, }, + { 155, 3, 1, 0x00000020a0000000ull, 0x000001eff8000000ull, { 24, 36, 0, 0, 0 }, 0x8, 135, }, + { 155, 3, 1, 0x00000020a8000000ull, 0x000001eff8000000ull, { 24, 37, 0, 0, 0 }, 0x0, 136, }, + { 155, 3, 1, 0x00000020b0000000ull, 0x000001eff8000000ull, { 24, 34, 0, 0, 0 }, 0x8, 137, }, + { 155, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 24, 29, 0, 0, 0 }, 0x0, 138, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 14, 0, 0, 0 }, 0x0, 139, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 56, 0, 0, 0 }, 0x0, 140, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 25, 0, 0, 0 }, 0x0, 141, }, + { 156, 6, 1, 0x000000c000000000ull, 0x000001e000100000ull, { 24, 71, 0, 0, 0 }, 0x0, 142, }, + { 157, 2, 1, 0x000000eca0000000ull, 0x000001fff0000000ull, { 24, 25, 75, 0, 0 }, 0x0, 143, }, + { 158, 2, 1, 0x000000eea0000000ull, 0x000001fff0000000ull, { 24, 25, 76, 0, 0 }, 0x0, 144, }, + { 168, 4, 0, 0x0000004000000000ull, 0x000001e1f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 539, }, + { 168, 5, 0, 0x0000000008000000ull, 0x000001e3fc000000ull, { 66, 0, 0, 0, 0 }, 0x0, 962, }, + { 168, 2, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 66, 0, 0, 0, 0 }, 0x2, 1147, }, + { 168, 3, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 66, 0, 0, 0, 0 }, 0x0, 1271, }, + { 168, 6, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 70, 0, 0, 0, 0 }, 0x0, 3035, }, + { 168, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 66, 0, 0, 0, 0 }, 0x0, 145, }, + { 175, 1, 1, 0x0000010070000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 146, }, + { 175, 1, 1, 0x0000010170000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 147, }, + { 178, 2, 1, 0x000000ea00000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 3017, }, + { 179, 2, 1, 0x000000f820000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2857, }, + { 180, 1, 1, 0x0000010400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 148, }, + { 181, 1, 1, 0x0000010600000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 149, }, + { 182, 1, 1, 0x0000011400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 150, }, + { 183, 1, 1, 0x0000010450000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 151, }, + { 184, 1, 1, 0x0000010650000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 152, }, + { 185, 1, 1, 0x0000010470000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 153, }, + { 186, 1, 1, 0x0000010670000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 154, }, + { 187, 1, 1, 0x0000010520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 948, }, + { 188, 1, 1, 0x0000010720000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 949, }, + { 189, 1, 1, 0x0000011520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 950, }, + { 190, 2, 1, 0x000000e850000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2871, }, + { 191, 2, 1, 0x000000ea70000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 155, }, + { 192, 2, 1, 0x000000e810000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2872, }, + { 193, 2, 1, 0x000000ea30000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 156, }, + { 194, 2, 1, 0x000000ead0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2206, }, + { 195, 2, 1, 0x000000e230000000ull, 0x000001ff30000000ull, { 24, 25, 26, 42, 0 }, 0x0, 157, }, + { 196, 2, 1, 0x000000e690000000ull, 0x000001fff0000000ull, { 24, 26, 0, 0, 0 }, 0x0, 158, }, + { 198, 3, 1, 0x00000021c0000000ull, 0x000001eff8000000ull, { 24, 26, 25, 0, 0 }, 0x0, 2207, }, + { 198, 3, 1, 0x00000020c0000000ull, 0x000001eff8000000ull, { 24, 26, 49, 0, 0 }, 0x0, 2208, }, + { 198, 3, 0, 0x0000002188000000ull, 0x000001eff8000000ull, { 26, 49, 0, 0, 0 }, 0x0, 2238, }, + { 199, 2, 1, 0x000000e8b0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 159, }, + { 200, 2, 1, 0x000000e240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 160, }, + { 200, 2, 1, 0x000000ee50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 161, }, + { 201, 2, 1, 0x000000f040000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 162, }, + { 201, 2, 1, 0x000000fc50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 163, }, + { 202, 1, 1, 0x0000010680000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 164, }, + { 203, 2, 1, 0x000000e220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 165, }, + { 203, 2, 1, 0x000000e630000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 166, }, + { 204, 2, 1, 0x000000f020000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 167, }, + { 204, 2, 1, 0x000000f430000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 168, }, + { 205, 1, 1, 0x00000106c0000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 169, }, + { 206, 1, 1, 0x0000010420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 170, }, + { 207, 1, 1, 0x0000010620000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 171, }, + { 208, 1, 1, 0x0000011420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 172, }, + { 209, 3, 0, 0x0000002048000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 1175, }, + { 209, 3, 0, 0x0000002050000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0xc, 1050, }, + { 209, 3, 0, 0x00000021a0000000ull, 0x000001eff8000000ull, { 26, 0, 0, 0, 0 }, 0x8, 922, }, + { 210, 3, 0, 0x0000002060000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 848, }, + { 215, 4, 0, 0x0000000040000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 173, }, + { 216, 3, 0, 0x0000000038000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x8, 174, }, + { 217, 3, 0, 0x0000000028000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x0, 175, }, + { 226, 3, 1, 0x000000c708000000ull, 0x000001ffc8000000ull, { 18, 25, 0, 0, 0 }, 0x0, 2782, }, + { 227, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 24, 25, 45, 0, 0 }, 0x140, 176, }, + { 227, 2, 1, 0x000000f240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 177, }, + { 228, 1, 1, 0x0000010080000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 178, }, + { 229, 1, 1, 0x00000100c0000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 179, }, + { 230, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 24, 26, 77, 0, 0 }, 0x140, 2878, }, + { 230, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 181, }, + { 231, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 24, 25, 26, 44, 0 }, 0x0, 182, }, + { 236, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 850, }, + { 237, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x8, 183, }, + { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 184, }, + { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 185, }, + { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 1, 0, 0 }, 0x0, 186, }, + { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x40, 187, }, + { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 188, }, + { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 189, }, + { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 190, }, + { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 191, }, + { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 192, }, + { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 193, }, + { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 2785, }, + { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 2786, }, + { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 194, }, + { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 195, }, + { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 196, }, + { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 197, }, + { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 198, }, + { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 199, }, + { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 200, }, + { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 201, }, + { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 202, }, + { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 203, }, + { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 204, }, + { 250, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x0, 205, }, + { 251, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 206, }, + { 252, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 207, }, + { 253, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 208, }, + { 254, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 1150, }, + { 255, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 209, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 23, 26, 77, 0 }, 0x0, 3040, }, + { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 26, 77, 0, 0 }, 0x40, 3041, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 22, 26, 77, 0 }, 0x40, 2003, }, + { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 26, 77, 0, 0 }, 0x40, 2004, }, + { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 23, 50, 0, 0 }, 0x0, 3044, }, + { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 50, 0, 0, 0 }, 0x40, 3045, }, + { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 22, 50, 0, 0 }, 0x40, 2007, }, + { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 50, 0, 0, 0 }, 0x40, 2008, }, + { 258, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 210, }, + { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 23, 26, 0, 0 }, 0x0, 3048, }, + { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 26, 0, 0, 0 }, 0x40, 3049, }, + { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 22, 26, 0, 0 }, 0x40, 2011, }, + { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 26, 0, 0, 0 }, 0x40, 2012, }, + { 260, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 211, }, + { 262, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 212, }, + { 266, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1131, }, + { 267, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1132, }, + { 268, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1133, }, + { 272, 4, 0, 0x00000000c0000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x28, 223, }, + { 277, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 213, }, + { 278, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 214, }, + { 279, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 215, }, + { 280, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 216, }, + { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 1179, }, + { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1261, }, + { 283, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 1180, }, + { 284, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 217, }, + { 284, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 218, }, + { 287, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 219, }, + { 288, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 220, }, + { 289, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 221, }, +}; + +static const char dis_table[] = { +0xa0, 0xc7, 0xc8, 0xa0, 0x2e, 0xd8, 0xa0, 0x2c, 0xc0, 0xa0, 0x1c, 0x00, +0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x39, 0x28, 0x24, +0x39, 0x20, 0x90, 0x28, 0x24, 0x39, 0x18, 0x24, 0x39, 0x10, 0x91, 0x60, +0x90, 0x28, 0x24, 0x39, 0x00, 0x10, 0x10, 0x58, 0x41, 0x61, 0xc7, 0xc0, +0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x10, 0x24, 0x24, 0x70, 0x90, 0x28, 0x24, 0x38, 0xf0, 0x24, +0x38, 0xe8, 0xa8, 0x0b, 0x48, 0x15, 0x20, 0x97, 0x20, 0x95, 0xc8, 0x9a, +0xb8, 0x05, 0x38, 0x91, 0x18, 0x90, 0xa0, 0x90, 0x60, 0x80, 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0xe5, 0x20, +0x01, 0x80, 0x30, 0x07, 0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, +0xe5, 0x20, 0x00, 0x00, 0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, +0x35, 0xc0, 0x38, 0xcd, 0xe5, 0x22, 0x38, 0x00, 0x38, 0xf5, 0x90, 0x40, +0xe5, 0x22, 0x24, 0x40, 0x38, 0x87, 0xe5, 0x22, 0x26, 0x80, 0x38, 0xaf, +0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x25, 0x48, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x22, 0x8c, 0xc0, 0x3a, 0x2f, 0xe5, 0x22, 0x89, 0xc0, 0x3a, 0x3b, +0x90, 0x40, 0xe5, 0x22, 0x7c, 0xc0, 0x39, 0xef, 0xe5, 0x22, 0x79, 0xc0, +0x39, 0xfb, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, +0x6a, 0xc0, 0x39, 0xc3, 0xe5, 0x22, 0x5e, 0xc0, 0x39, 0x93, 0xcb, 0x61, +0x2b, 0x00, 0x85, 0x34, 0xb0, 0x90, 0x40, 0xe5, 0x22, 0x52, 0xc0, 0x39, +0x63, 0xe5, 0x22, 0x46, 0xc0, 0x39, 0x33, 0x90, 0x48, 0xcb, 0xa1, 0x2a, +0x80, 0x85, 0x34, 0xae, 0xcb, 0xa1, 0x2a, 0xc0, 0x85, 0x34, 0xaf, 0x10, +0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x3c, 0x40, 0x38, 0xed, 0xe5, +0x22, 0x39, 0x40, 0x38, 0xfb, 0x90, 0x40, 0xe5, 0x22, 0x2a, 0xc0, 0x38, +0xa7, 0xe5, 0x22, 0x27, 0xc0, 0x38, 0xb5, +}; + +static const struct ia64_dis_names ia64_dis_names[] = { +{ 0x51, 41, 0, 10 }, +{ 0x31, 41, 1, 20 }, +{ 0x11, 42, 0, 19 }, +{ 0x29, 41, 0, 12 }, +{ 0x19, 41, 1, 24 }, +{ 0x9, 42, 0, 23 }, +{ 0x15, 41, 0, 14 }, +{ 0xd, 41, 1, 28 }, +{ 0x5, 42, 0, 27 }, +{ 0xb, 41, 0, 16 }, +{ 0x7, 41, 1, 32 }, +{ 0x3, 42, 0, 31 }, +{ 0x51, 39, 1, 58 }, +{ 0x50, 39, 0, 34 }, +{ 0xd1, 39, 1, 57 }, +{ 0xd0, 39, 0, 33 }, +{ 0x31, 39, 1, 68 }, +{ 0x30, 39, 1, 44 }, +{ 0x11, 40, 1, 67 }, +{ 0x10, 40, 0, 43 }, +{ 0x71, 39, 1, 66 }, +{ 0x70, 39, 1, 42 }, +{ 0x31, 40, 1, 65 }, +{ 0x30, 40, 0, 41 }, +{ 0x29, 39, 1, 60 }, +{ 0x28, 39, 0, 36 }, +{ 0x69, 39, 1, 59 }, +{ 0x68, 39, 0, 35 }, +{ 0x19, 39, 1, 72 }, +{ 0x18, 39, 1, 48 }, +{ 0x9, 40, 1, 71 }, +{ 0x8, 40, 0, 47 }, +{ 0x39, 39, 1, 70 }, +{ 0x38, 39, 1, 46 }, +{ 0x19, 40, 1, 69 }, +{ 0x18, 40, 0, 45 }, +{ 0x15, 39, 1, 62 }, +{ 0x14, 39, 0, 38 }, +{ 0x35, 39, 1, 61 }, +{ 0x34, 39, 0, 37 }, +{ 0xd, 39, 1, 76 }, +{ 0xc, 39, 1, 52 }, +{ 0x5, 40, 1, 75 }, +{ 0x4, 40, 0, 51 }, +{ 0x1d, 39, 1, 74 }, +{ 0x1c, 39, 1, 50 }, +{ 0xd, 40, 1, 73 }, +{ 0xc, 40, 0, 49 }, +{ 0xb, 39, 1, 64 }, +{ 0xa, 39, 0, 40 }, +{ 0x1b, 39, 1, 63 }, +{ 0x1a, 39, 0, 39 }, +{ 0x7, 39, 1, 80 }, +{ 0x6, 39, 1, 56 }, +{ 0x3, 40, 1, 79 }, +{ 0x2, 40, 0, 55 }, +{ 0xf, 39, 1, 78 }, +{ 0xe, 39, 1, 54 }, +{ 0x7, 40, 1, 77 }, +{ 0x6, 40, 0, 53 }, +{ 0x8, 38, 0, 82 }, +{ 0x18, 38, 0, 81 }, +{ 0x1, 38, 1, 86 }, +{ 0x2, 38, 0, 85 }, +{ 0x3, 38, 1, 84 }, +{ 0x4, 38, 0, 83 }, +{ 0x1, 336, 0, 87 }, +{ 0x20, 289, 0, 98 }, +{ 0x220, 289, 0, 94 }, +{ 0x1220, 289, 0, 91 }, +{ 0xa20, 289, 0, 92 }, +{ 0x620, 289, 0, 93 }, +{ 0x120, 289, 0, 95 }, +{ 0xa0, 289, 0, 96 }, +{ 0x60, 289, 0, 97 }, +{ 0x10, 289, 0, 102 }, +{ 0x90, 289, 0, 99 }, +{ 0x50, 289, 0, 100 }, +{ 0x30, 289, 0, 101 }, +{ 0x8, 289, 0, 103 }, +{ 0x4, 289, 0, 104 }, +{ 0x2, 289, 0, 105 }, +{ 0x1, 289, 0, 106 }, +{ 0x1, 411, 0, 108 }, +{ 0x3, 411, 0, 107 }, +{ 0x2, 417, 0, 109 }, +{ 0x1, 417, 0, 110 }, +{ 0x2, 413, 0, 111 }, +{ 0x1, 413, 0, 112 }, +{ 0x2, 415, 0, 113 }, +{ 0x1, 415, 0, 114 }, +{ 0x2, 419, 0, 115 }, +{ 0x1, 419, 0, 116 }, +{ 0x1, 268, 0, 143 }, +{ 0x5, 268, 0, 141 }, +{ 0x3, 268, 0, 142 }, +{ 0x140, 277, 0, 119 }, +{ 0x540, 277, 0, 117 }, +{ 0x340, 277, 0, 118 }, +{ 0xc0, 277, 0, 131 }, +{ 0x2c0, 277, 0, 129 }, +{ 0x1c0, 277, 0, 130 }, +{ 0x20, 277, 0, 146 }, +{ 0xa0, 277, 0, 144 }, +{ 0x60, 277, 0, 145 }, +{ 0x10, 277, 0, 158 }, +{ 0x50, 277, 0, 156 }, +{ 0x30, 277, 0, 157 }, +{ 0x8, 277, 0, 170 }, +{ 0x28, 277, 0, 168 }, +{ 0x18, 277, 0, 169 }, +{ 0x4, 277, 0, 180 }, +{ 0x2, 277, 0, 181 }, +{ 0x1, 277, 0, 182 }, +{ 0x140, 271, 0, 122 }, +{ 0x540, 271, 0, 120 }, +{ 0x340, 271, 0, 121 }, +{ 0xc0, 271, 0, 134 }, +{ 0x2c0, 271, 0, 132 }, +{ 0x1c0, 271, 0, 133 }, +{ 0x20, 271, 0, 149 }, +{ 0xa0, 271, 0, 147 }, +{ 0x60, 271, 0, 148 }, +{ 0x10, 271, 0, 161 }, +{ 0x50, 271, 0, 159 }, +{ 0x30, 271, 0, 160 }, +{ 0x8, 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121, 0, 2245 }, +{ 0xc, 95, 1, 2556 }, +{ 0xc, 96, 1, 2555 }, +{ 0x18, 96, 1, 2551 }, +{ 0xc, 97, 1, 2554 }, +{ 0x18, 97, 1, 2550 }, +{ 0xc, 98, 1, 2553 }, +{ 0x18, 98, 1, 2549 }, +{ 0xc, 99, 0, 2552 }, +{ 0xa, 95, 1, 2404 }, +{ 0x11, 96, 1, 2399 }, +{ 0x22, 96, 1, 2403 }, +{ 0x11, 97, 1, 2398 }, +{ 0x22, 97, 1, 2402 }, +{ 0x11, 98, 1, 2397 }, +{ 0x22, 98, 1, 2401 }, +{ 0xa, 99, 0, 2400 }, +{ 0x1a, 95, 1, 2260 }, +{ 0x62, 96, 1, 2259 }, +{ 0x62, 97, 1, 2258 }, +{ 0x62, 98, 1, 2257 }, +{ 0xe, 118, 1, 2256 }, +{ 0xe, 119, 1, 2255 }, +{ 0xe, 120, 1, 2254 }, +{ 0xe, 121, 0, 2253 }, +{ 0x6, 95, 1, 2564 }, +{ 0x5, 96, 1, 2559 }, +{ 0xa, 96, 1, 2563 }, +{ 0x5, 97, 1, 2558 }, +{ 0xa, 97, 1, 2562 }, +{ 0x5, 98, 1, 2557 }, +{ 0xa, 98, 1, 2561 }, +{ 0x6, 99, 0, 2560 }, +{ 0x5, 95, 1, 2412 }, +{ 0x9, 96, 1, 2411 }, +{ 0x12, 96, 1, 2407 }, +{ 0x9, 97, 1, 2410 }, +{ 0x12, 97, 1, 2406 }, +{ 0x9, 98, 1, 2409 }, +{ 0x12, 98, 1, 2405 }, +{ 0x5, 99, 0, 2408 }, +{ 0xd, 95, 1, 2268 }, +{ 0x19, 96, 1, 2267 }, +{ 0x19, 97, 1, 2266 }, +{ 0x19, 98, 1, 2265 }, +{ 0x7, 118, 1, 2264 }, +{ 0x7, 119, 1, 2263 }, +{ 0x7, 120, 1, 2262 }, +{ 0x7, 121, 0, 2261 }, +{ 0x3, 95, 1, 2572 }, +{ 0x3, 96, 1, 2571 }, +{ 0x6, 96, 1, 2567 }, +{ 0x3, 97, 1, 2570 }, +{ 0x6, 97, 1, 2566 }, +{ 0x3, 98, 1, 2569 }, +{ 0x6, 98, 1, 2565 }, +{ 0x3, 99, 0, 2568 }, +{ 0x28, 62, 1, 2420 }, +{ 0x44, 63, 1, 2415 }, +{ 0x88, 63, 1, 2419 }, +{ 0x44, 64, 1, 2414 }, +{ 0x88, 64, 1, 2418 }, +{ 0x44, 65, 1, 2413 }, +{ 0x88, 65, 1, 2417 }, +{ 0x28, 66, 0, 2416 }, +{ 0x68, 62, 1, 2276 }, +{ 0x188, 63, 1, 2275 }, +{ 0x188, 64, 1, 2274 }, +{ 0x188, 65, 1, 2273 }, +{ 0x38, 81, 1, 2272 }, +{ 0x38, 82, 1, 2271 }, +{ 0x38, 83, 1, 2270 }, +{ 0x38, 84, 0, 2269 }, +{ 0x18, 62, 1, 2580 }, +{ 0x14, 63, 1, 2575 }, +{ 0x28, 63, 1, 2579 }, +{ 0x14, 64, 1, 2574 }, +{ 0x28, 64, 1, 2578 }, +{ 0x14, 65, 1, 2573 }, +{ 0x28, 65, 1, 2577 }, +{ 0x18, 66, 0, 2576 }, +{ 0x14, 62, 1, 2428 }, +{ 0x24, 63, 1, 2427 }, +{ 0x48, 63, 1, 2423 }, +{ 0x24, 64, 1, 2426 }, +{ 0x48, 64, 1, 2422 }, +{ 0x24, 65, 1, 2425 }, +{ 0x48, 65, 1, 2421 }, +{ 0x14, 66, 0, 2424 }, +{ 0x34, 62, 1, 2284 }, +{ 0x64, 63, 1, 2283 }, +{ 0x64, 64, 1, 2282 }, +{ 0x64, 65, 1, 2281 }, +{ 0x1c, 81, 1, 2280 }, +{ 0x1c, 82, 1, 2279 }, +{ 0x1c, 83, 1, 2278 }, +{ 0x1c, 84, 0, 2277 }, +{ 0xc, 62, 1, 2588 }, +{ 0xc, 63, 1, 2587 }, +{ 0x18, 63, 1, 2583 }, +{ 0xc, 64, 1, 2586 }, +{ 0x18, 64, 1, 2582 }, +{ 0xc, 65, 1, 2585 }, +{ 0x18, 65, 1, 2581 }, +{ 0xc, 66, 0, 2584 }, +{ 0xa, 62, 1, 2436 }, +{ 0x11, 63, 1, 2431 }, +{ 0x22, 63, 1, 2435 }, +{ 0x11, 64, 1, 2430 }, +{ 0x22, 64, 1, 2434 }, +{ 0x11, 65, 1, 2429 }, +{ 0x22, 65, 1, 2433 }, +{ 0xa, 66, 0, 2432 }, +{ 0x1a, 62, 1, 2292 }, +{ 0x62, 63, 1, 2291 }, +{ 0x62, 64, 1, 2290 }, +{ 0x62, 65, 1, 2289 }, +{ 0xe, 81, 1, 2288 }, +{ 0xe, 82, 1, 2287 }, +{ 0xe, 83, 1, 2286 }, +{ 0xe, 84, 0, 2285 }, +{ 0x6, 62, 1, 2596 }, +{ 0x5, 63, 1, 2591 }, +{ 0xa, 63, 1, 2595 }, +{ 0x5, 64, 1, 2590 }, +{ 0xa, 64, 1, 2594 }, +{ 0x5, 65, 1, 2589 }, +{ 0xa, 65, 1, 2593 }, +{ 0x6, 66, 0, 2592 }, +{ 0x5, 62, 1, 2444 }, +{ 0x9, 63, 1, 2443 }, +{ 0x12, 63, 1, 2439 }, +{ 0x9, 64, 1, 2442 }, +{ 0x12, 64, 1, 2438 }, +{ 0x9, 65, 1, 2441 }, +{ 0x12, 65, 1, 2437 }, +{ 0x5, 66, 0, 2440 }, +{ 0xd, 62, 1, 2300 }, +{ 0x19, 63, 1, 2299 }, +{ 0x19, 64, 1, 2298 }, +{ 0x19, 65, 1, 2297 }, +{ 0x7, 81, 1, 2296 }, +{ 0x7, 82, 1, 2295 }, +{ 0x7, 83, 1, 2294 }, +{ 0x7, 84, 0, 2293 }, +{ 0x3, 62, 1, 2604 }, +{ 0x3, 63, 1, 2603 }, +{ 0x6, 63, 1, 2599 }, +{ 0x3, 64, 1, 2602 }, +{ 0x6, 64, 1, 2598 }, +{ 0x3, 65, 1, 2601 }, +{ 0x6, 65, 1, 2597 }, +{ 0x3, 66, 0, 2600 }, +{ 0x8, 86, 1, 2468 }, +{ 0x8, 87, 1, 2467 }, +{ 0x2, 88, 1, 2466 }, +{ 0x2, 89, 1, 2465 }, +{ 0x2, 90, 1, 2464 }, +{ 0x2, 91, 1, 2463 }, +{ 0x2, 92, 1, 2462 }, +{ 0x2, 93, 0, 2461 }, +{ 0x18, 86, 1, 2460 }, +{ 0x18, 87, 1, 2459 }, +{ 0x6, 88, 1, 2458 }, +{ 0x6, 89, 1, 2457 }, +{ 0x6, 90, 1, 2456 }, +{ 0x6, 91, 1, 2455 }, +{ 0x6, 92, 1, 2454 }, +{ 0x6, 93, 0, 2453 }, +{ 0x14, 86, 1, 2448 }, +{ 0x22, 87, 1, 2445 }, +{ 0x44, 87, 1, 2447 }, +{ 0xa, 94, 0, 2446 }, +{ 0x34, 86, 1, 2304 }, +{ 0xc4, 87, 1, 2303 }, +{ 0x38, 93, 1, 2301 }, +{ 0xe, 117, 0, 2302 }, +{ 0xc, 86, 1, 2608 }, +{ 0xa, 87, 1, 2605 }, +{ 0x14, 87, 1, 2607 }, +{ 0x6, 94, 0, 2606 }, +{ 0x2, 86, 1, 2316 }, +{ 0x2, 87, 1, 2315 }, +{ 0x4, 92, 1, 2314 }, +{ 0x4, 93, 0, 2313 }, +{ 0x12, 86, 1, 2312 }, +{ 0x42, 87, 1, 2311 }, +{ 0xc, 92, 1, 2310 }, +{ 0xc, 93, 0, 2309 }, +{ 0xa, 86, 1, 2452 }, +{ 0x12, 87, 1, 2451 }, +{ 0x24, 87, 1, 2449 }, +{ 0x5, 94, 0, 2450 }, +{ 0x1a, 86, 1, 2308 }, +{ 0x32, 87, 1, 2307 }, +{ 0x34, 93, 1, 2305 }, +{ 0x7, 117, 0, 2306 }, +{ 0x6, 86, 1, 2612 }, +{ 0x6, 87, 1, 2611 }, +{ 0xc, 87, 1, 2609 }, +{ 0x3, 94, 0, 2610 }, +{ 0x1, 86, 1, 2628 }, +{ 0x1, 87, 1, 2627 }, +{ 0x1, 88, 1, 2626 }, +{ 0x1, 89, 1, 2625 }, +{ 0x1, 90, 1, 2624 }, +{ 0x1, 91, 1, 2623 }, +{ 0x1, 92, 1, 2622 }, +{ 0x1, 93, 0, 2621 }, +{ 0x3, 86, 1, 2620 }, +{ 0x3, 87, 1, 2619 }, +{ 0x3, 88, 1, 2618 }, +{ 0x3, 89, 1, 2617 }, +{ 0x3, 90, 1, 2616 }, +{ 0x3, 91, 1, 2615 }, +{ 0x3, 92, 1, 2614 }, +{ 0x3, 93, 0, 2613 }, +{ 0x8, 53, 1, 2492 }, +{ 0x8, 54, 1, 2491 }, +{ 0x2, 55, 1, 2490 }, +{ 0x2, 56, 1, 2489 }, +{ 0x2, 57, 1, 2488 }, +{ 0x2, 58, 1, 2487 }, +{ 0x2, 59, 1, 2486 }, +{ 0x2, 60, 0, 2485 }, +{ 0x18, 53, 1, 2484 }, +{ 0x18, 54, 1, 2483 }, +{ 0x6, 55, 1, 2482 }, +{ 0x6, 56, 1, 2481 }, +{ 0x6, 57, 1, 2480 }, +{ 0x6, 58, 1, 2479 }, +{ 0x6, 59, 1, 2478 }, +{ 0x6, 60, 0, 2477 }, +{ 0x14, 53, 1, 2472 }, +{ 0x22, 54, 1, 2469 }, +{ 0x44, 54, 1, 2471 }, +{ 0xa, 61, 0, 2470 }, +{ 0x34, 53, 1, 2320 }, +{ 0xc4, 54, 1, 2319 }, +{ 0x38, 60, 1, 2317 }, +{ 0xe, 80, 0, 2318 }, +{ 0xc, 53, 1, 2632 }, +{ 0xa, 54, 1, 2629 }, +{ 0x14, 54, 1, 2631 }, +{ 0x6, 61, 0, 2630 }, +{ 0x2, 53, 1, 2332 }, +{ 0x2, 54, 1, 2331 }, +{ 0x4, 59, 1, 2330 }, +{ 0x4, 60, 0, 2329 }, +{ 0x12, 53, 1, 2328 }, +{ 0x42, 54, 1, 2327 }, +{ 0xc, 59, 1, 2326 }, +{ 0xc, 60, 0, 2325 }, +{ 0xa, 53, 1, 2476 }, +{ 0x12, 54, 1, 2475 }, +{ 0x24, 54, 1, 2473 }, +{ 0x5, 61, 0, 2474 }, +{ 0x1a, 53, 1, 2324 }, +{ 0x32, 54, 1, 2323 }, +{ 0x34, 60, 1, 2321 }, +{ 0x7, 80, 0, 2322 }, +{ 0x6, 53, 1, 2636 }, +{ 0x6, 54, 1, 2635 }, +{ 0xc, 54, 1, 2633 }, +{ 0x3, 61, 0, 2634 }, +{ 0x1, 53, 1, 2652 }, +{ 0x1, 54, 1, 2651 }, +{ 0x1, 55, 1, 2650 }, +{ 0x1, 56, 1, 2649 }, +{ 0x1, 57, 1, 2648 }, +{ 0x1, 58, 1, 2647 }, +{ 0x1, 59, 1, 2646 }, +{ 0x1, 60, 0, 2645 }, +{ 0x3, 53, 1, 2644 }, +{ 0x3, 54, 1, 2643 }, +{ 0x3, 55, 1, 2642 }, +{ 0x3, 56, 1, 2641 }, +{ 0x3, 57, 1, 2640 }, +{ 0x3, 58, 1, 2639 }, +{ 0x3, 59, 1, 2638 }, +{ 0x3, 60, 0, 2637 }, +{ 0x1, 4, 0, 2653 }, +{ 0x1, 296, 0, 2654 }, +{ 0x1, 379, 0, 2655 }, +{ 0x1, 374, 0, 2656 }, +{ 0x2, 358, 0, 2657 }, +{ 0x1, 358, 0, 2660 }, +{ 0x2, 357, 0, 2658 }, +{ 0x1, 357, 0, 2661 }, +{ 0x2, 356, 0, 2659 }, +{ 0x1, 356, 0, 2662 }, +{ 0x1, 355, 0, 2663 }, +{ 0x1, 354, 0, 2664 }, +{ 0x2, 353, 0, 2665 }, +{ 0x1, 353, 0, 2667 }, +{ 0x2, 352, 0, 2666 }, +{ 0x1, 352, 0, 2668 }, +{ 0x1, 382, 0, 2675 }, +{ 0x8, 381, 0, 2669 }, +{ 0x4, 381, 0, 2671 }, +{ 0x2, 381, 0, 2673 }, +{ 0x1, 381, 0, 2676 }, +{ 0x8, 380, 0, 2670 }, +{ 0x4, 380, 0, 2672 }, +{ 0x2, 380, 0, 2674 }, +{ 0x1, 380, 0, 2677 }, +{ 0x1, 351, 0, 2684 }, +{ 0x8, 350, 0, 2678 }, +{ 0x4, 350, 0, 2680 }, +{ 0x2, 350, 0, 2682 }, +{ 0x1, 350, 0, 2685 }, +{ 0x8, 349, 0, 2679 }, +{ 0x4, 349, 0, 2681 }, +{ 0x2, 349, 1, 2683 }, +{ 0x4, 143, 0, 1377 }, +{ 0x1, 349, 0, 2686 }, +{ 0x1, 6, 0, 2687 }, +{ 0x1, 7, 0, 2688 }, +{ 0x1, 295, 0, 2689 }, +{ 0x1, 456, 0, 2690 }, +{ 0x1, 346, 0, 2691 }, +{ 0x1, 13, 0, 2692 }, +{ 0x1, 11, 0, 2693 }, +{ 0x1, 422, 0, 2694 }, +{ 0x1, 394, 0, 2695 }, +{ 0x1, 393, 0, 2696 }, +{ 0x1, 455, 0, 2697 }, +{ 0x1, 345, 0, 2698 }, +{ 0x1, 12, 0, 2699 }, +{ 0x1, 10, 0, 2700 }, +{ 0x1, 5, 0, 2701 }, +{ 0x1, 421, 0, 2702 }, +{ 0x1, 420, 0, 2703 }, +{ 0x1, 1, 0, 2704 }, +{ 0x1, 0, 0, 2705 }, +}; + diff --git a/external/gpl3/gdb/dist/opcodes/ia64-asmtab.h b/external/gpl3/gdb/dist/opcodes/ia64-asmtab.h new file mode 100644 index 000000000000..fbca883a4658 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-asmtab.h @@ -0,0 +1,148 @@ +/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. + Copyright 1999, 2000, 2005, 2007 Free Software Foundation, Inc. + Contributed by Bob Manson of Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef IA64_ASMTAB_H +#define IA64_ASMTAB_H + +#include "opcode/ia64.h" + +/* The primary opcode table is made up of the following: */ +struct ia64_main_table +{ + /* The entry in the string table that corresponds to the name of this + opcode. */ + unsigned short name_index; + + /* The type of opcode; corresponds to the TYPE field in + struct ia64_opcode. */ + unsigned char opcode_type; + + /* The number of outputs for this opcode. */ + unsigned char num_outputs; + + /* The base insn value for this opcode. It may be modified by completers. */ + ia64_insn opcode; + + /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ + ia64_insn mask; + + /* The operands of this instruction. Corresponds to the OPERANDS field + in struct ia64_opcode. */ + unsigned char operands[5]; + + /* The flags for this instruction. Corresponds to the FLAGS field in + struct ia64_opcode. */ + short flags; + + /* The tree of completers for this instruction; this is an offset into + completer_table. */ + short completers; +}; + +/* Each instruction has a set of possible "completers", or additional + suffixes that can alter the instruction's behavior, and which has + potentially different dependencies. + + The completer entries modify certain bits in the instruction opcode. + Which bits are to be modified are marked by the BITS, MASK and + OFFSET fields. The completer entry may also note dependencies for the + opcode. + + These completers are arranged in a DAG; the pointers are indexes + into the completer_table array. The completer DAG is searched by + find_completer () and ia64_find_matching_opcode (). + + Note that each completer needs to be applied in turn, so that if we + have the instruction + cmp.lt.unc + the completer entries for both "lt" and "unc" would need to be applied + to the opcode's value. + + Some instructions do not require any completers; these contain an + empty completer entry. Instructions that require a completer do + not contain an empty entry. + + Terminal completers (those completers that validly complete an + instruction) are marked by having the TERMINAL_COMPLETER flag set. + + Only dependencies listed in the terminal completer for an opcode are + considered to apply to that opcode instance. */ + +struct ia64_completer_table +{ + /* The bit value that this completer sets. */ + unsigned int bits; + + /* And its mask. 1s are bits that are to be modified in the + instruction. */ + unsigned int mask; + + /* The entry in the string table that corresponds to the name of this + completer. */ + unsigned short name_index; + + /* An alternative completer, or -1 if this is the end of the chain. */ + short alternative; + + /* A pointer to the DAG of completers that can potentially follow + this one, or -1. */ + short subentries; + + /* The bit offset in the instruction where BITS and MASK should be + applied. */ + unsigned char offset : 7; + + unsigned char terminal_completer : 1; + + /* Index into the dependency list table */ + short dependencies; +}; + +/* This contains sufficient information for the disassembler to resolve + the complete name of the original instruction. */ +struct ia64_dis_names +{ + /* COMPLETER_INDEX represents the tree of completers that make up + the instruction. The LSB represents the top of the tree for the + specified instruction. + + A 0 bit indicates to go to the next alternate completer via the + alternative field; a 1 bit indicates that the current completer + is part of the instruction, and to go down the subentries index. + We know we've reached the final completer when we run out of 1 + bits. + + There is always at least one 1 bit. */ + unsigned int completer_index : 20; + + /* The index in the main_table[] array for the instruction. */ + unsigned short insn_index : 11; + + /* If set, the next entry in this table is an alternate possibility + for this instruction encoding. Which one to use is determined by + the instruction type and other factors (see opcode_verify ()). */ + unsigned int next_flag : 1; + + /* The disassembly priority of this entry among instructions. */ + unsigned short priority; +}; + +#endif diff --git a/external/gpl3/gdb/dist/opcodes/ia64-dis.c b/external/gpl3/gdb/dist/opcodes/ia64-dis.c new file mode 100644 index 000000000000..13ee19492589 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-dis.c @@ -0,0 +1,321 @@ +/* ia64-dis.c -- Disassemble ia64 instructions + Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2008, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include + +#include "dis-asm.h" +#include "opcode/ia64.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) + +/* Disassemble ia64 instruction. */ + +/* Return the instruction type for OPCODE found in unit UNIT. */ + +static enum ia64_insn_type +unit_to_type (ia64_insn opcode, enum ia64_unit unit) +{ + enum ia64_insn_type type; + int op; + + op = IA64_OP (opcode); + + if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) + { + type = IA64_TYPE_A; + } + else + { + switch (unit) + { + case IA64_UNIT_I: + type = IA64_TYPE_I; break; + case IA64_UNIT_M: + type = IA64_TYPE_M; break; + case IA64_UNIT_B: + type = IA64_TYPE_B; break; + case IA64_UNIT_F: + type = IA64_TYPE_F; break; + case IA64_UNIT_L: + case IA64_UNIT_X: + type = IA64_TYPE_X; break; + default: + type = -1; + } + } + return type; +} + +int +print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) +{ + ia64_insn t0, t1, slot[3], template_val, s_bit, insn; + int slotnum, j, status, need_comma, retval, slot_multiplier; + const struct ia64_operand *odesc; + const struct ia64_opcode *idesc; + const char *err, *str, *tname; + BFD_HOST_U_64_BIT value; + bfd_byte bundle[16]; + enum ia64_unit unit; + char regname[16]; + + if (info->bytes_per_line == 0) + info->bytes_per_line = 6; + info->display_endian = info->endian; + + slot_multiplier = info->bytes_per_line; + retval = slot_multiplier; + + slotnum = (((long) memaddr) & 0xf) / slot_multiplier; + if (slotnum > 2) + return -1; + + memaddr -= (memaddr & 0xf); + status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (bundle); + t1 = bfd_getl64 (bundle + 8); + s_bit = t0 & 1; + template_val = (t0 >> 1) & 0xf; + slot[0] = (t0 >> 5) & 0x1ffffffffffLL; + slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + slot[2] = (t1 >> 23) & 0x1ffffffffffLL; + + tname = ia64_templ_desc[template_val].name; + if (slotnum == 0) + (*info->fprintf_func) (info->stream, "[%s] ", tname); + else + (*info->fprintf_func) (info->stream, " "); + + unit = ia64_templ_desc[template_val].exec_unit[slotnum]; + + if (template_val == 2 && slotnum == 1) + { + /* skip L slot in MLI template: */ + slotnum = 2; + retval += slot_multiplier; + } + + insn = slot[slotnum]; + + if (unit == IA64_UNIT_NIL) + goto decoding_failed; + + idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); + if (idesc == NULL) + goto decoding_failed; + + /* print predicate, if any: */ + + if ((idesc->flags & IA64_OPCODE_NO_PRED) + || (insn & 0x3f) == 0) + (*info->fprintf_func) (info->stream, " "); + else + (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); + + /* now the actual instruction: */ + + (*info->fprintf_func) (info->stream, "%s", idesc->name); + if (idesc->operands[0]) + (*info->fprintf_func) (info->stream, " "); + + need_comma = 0; + for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) + { + odesc = elf64_ia64_operands + idesc->operands[j]; + + if (need_comma) + (*info->fprintf_func) (info->stream, ","); + + if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) + { + /* special case of 64 bit immediate load: */ + value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) + | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) + | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) + { + /* 62-bit immediate for nop.x/break.x */ + value = ((slot[1] & 0x1ffffffffffLL) << 21) + | (((insn >> 36) & 0x1) << 20) + | ((insn >> 6) & 0xfffff); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) + { + /* 60-bit immediate for long branches. */ + value = (((insn >> 13) & 0xfffff) + | (((insn >> 36) & 1) << 59) + | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; + } + else + { + err = (*odesc->extract) (odesc, insn, &value); + if (err) + { + (*info->fprintf_func) (info->stream, "%s", err); + goto done; + } + } + + switch (odesc->op_class) + { + case IA64_OPND_CLASS_CST: + (*info->fprintf_func) (info->stream, "%s", odesc->str); + break; + + case IA64_OPND_CLASS_REG: + if (odesc->str[0] == 'a' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: case 1: case 2: case 3: + case 4: case 5: case 6: case 7: + sprintf (regname, "ar.k%u", (unsigned int) value); + break; + case 16: strcpy (regname, "ar.rsc"); break; + case 17: strcpy (regname, "ar.bsp"); break; + case 18: strcpy (regname, "ar.bspstore"); break; + case 19: strcpy (regname, "ar.rnat"); break; + case 21: strcpy (regname, "ar.fcr"); break; + case 24: strcpy (regname, "ar.eflag"); break; + case 25: strcpy (regname, "ar.csd"); break; + case 26: strcpy (regname, "ar.ssd"); break; + case 27: strcpy (regname, "ar.cflg"); break; + case 28: strcpy (regname, "ar.fsr"); break; + case 29: strcpy (regname, "ar.fir"); break; + case 30: strcpy (regname, "ar.fdr"); break; + case 32: strcpy (regname, "ar.ccv"); break; + case 36: strcpy (regname, "ar.unat"); break; + case 40: strcpy (regname, "ar.fpsr"); break; + case 44: strcpy (regname, "ar.itc"); break; + case 45: strcpy (regname, "ar.ruc"); break; + case 64: strcpy (regname, "ar.pfs"); break; + case 65: strcpy (regname, "ar.lc"); break; + case 66: strcpy (regname, "ar.ec"); break; + default: + sprintf (regname, "ar%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else if (odesc->str[0] == 'c' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: strcpy (regname, "cr.dcr"); break; + case 1: strcpy (regname, "cr.itm"); break; + case 2: strcpy (regname, "cr.iva"); break; + case 8: strcpy (regname, "cr.pta"); break; + case 16: strcpy (regname, "cr.ipsr"); break; + case 17: strcpy (regname, "cr.isr"); break; + case 19: strcpy (regname, "cr.iip"); break; + case 20: strcpy (regname, "cr.ifa"); break; + case 21: strcpy (regname, "cr.itir"); break; + case 22: strcpy (regname, "cr.iipa"); break; + case 23: strcpy (regname, "cr.ifs"); break; + case 24: strcpy (regname, "cr.iim"); break; + case 25: strcpy (regname, "cr.iha"); break; + case 26: strcpy (regname, "cr.iib0"); break; + case 27: strcpy (regname, "cr.iib1"); break; + case 64: strcpy (regname, "cr.lid"); break; + case 65: strcpy (regname, "cr.ivr"); break; + case 66: strcpy (regname, "cr.tpr"); break; + case 67: strcpy (regname, "cr.eoi"); break; + case 68: strcpy (regname, "cr.irr0"); break; + case 69: strcpy (regname, "cr.irr1"); break; + case 70: strcpy (regname, "cr.irr2"); break; + case 71: strcpy (regname, "cr.irr3"); break; + case 72: strcpy (regname, "cr.itv"); break; + case 73: strcpy (regname, "cr.pmv"); break; + case 74: strcpy (regname, "cr.cmcv"); break; + case 80: strcpy (regname, "cr.lrr0"); break; + case 81: strcpy (regname, "cr.lrr1"); break; + default: + sprintf (regname, "cr%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else + (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_IND: + (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_ABS: + str = 0; + if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) + switch (value) + { + case 0x0: str = "@brcst"; break; + case 0x8: str = "@mix"; break; + case 0x9: str = "@shuf"; break; + case 0xa: str = "@alt"; break; + case 0xb: str = "@rev"; break; + } + + if (str) + (*info->fprintf_func) (info->stream, "%s", str); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) + (*info->fprintf_func) (info->stream, "%lld", (long long) value); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) + (*info->fprintf_func) (info->stream, "%llu", (long long) value); + else + (*info->fprintf_func) (info->stream, "0x%llx", (long long) value); + break; + + case IA64_OPND_CLASS_REL: + (*info->print_address_func) (memaddr + value, info); + break; + } + + need_comma = 1; + if (j + 1 == idesc->num_outputs) + { + (*info->fprintf_func) (info->stream, "="); + need_comma = 0; + } + } + if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary + || ((slotnum == 2) && s_bit)) + (*info->fprintf_func) (info->stream, ";;"); + + done: + ia64_free_opcode ((struct ia64_opcode *)idesc); + failed: + if (slotnum == 2) + retval += 16 - 3*slot_multiplier; + return retval; + + decoding_failed: + (*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn); + goto failed; +} diff --git a/external/gpl3/gdb/dist/opcodes/ia64-gen.c b/external/gpl3/gdb/dist/opcodes/ia64-gen.c new file mode 100644 index 000000000000..eefa81c6ac25 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-gen.c @@ -0,0 +1,2864 @@ +/* ia64-gen.c -- Generate a shrunk set of opcode tables + Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009 + Free Software Foundation, Inc. + Written by Bob Manson, Cygnus Solutions, + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + + +/* While the ia64-opc-* set of opcode tables are easy to maintain, + they waste a tremendous amount of space. ia64-gen rearranges the + instructions into a directed acyclic graph (DAG) of instruction opcodes and + their possible completers, as well as compacting the set of strings used. + + The disassembler table consists of a state machine that does + branching based on the bits of the opcode being disassembled. The + state encodings have been chosen to minimize the amount of space + required. + + The resource table is constructed based on some text dependency tables, + which are also easier to maintain than the final representation. */ + +#include +#include +#include + +#include "ansidecl.h" +#include "libiberty.h" +#include "safe-ctype.h" +#include "sysdep.h" +#include "getopt.h" +#include "ia64-opc.h" +#include "ia64-opc-a.c" +#include "ia64-opc-i.c" +#include "ia64-opc-m.c" +#include "ia64-opc-b.c" +#include "ia64-opc-f.c" +#include "ia64-opc-x.c" +#include "ia64-opc-d.c" + +#include +#define _(String) gettext (String) + +/* This is a copy of fprintf_vma from bfd/bfd-in2.h. We have to use this + always, because we might be compiled without BFD64 defined, if configured + for a 32-bit target and --enable-targets=all is used. This will work for + both 32-bit and 64-bit hosts. */ +#define _opcode_int64_low(x) ((unsigned long) (((x) & 0xffffffff))) +#define _opcode_int64_high(x) ((unsigned long) (((x) >> 32) & 0xffffffff)) +#define opcode_fprintf_vma(s,x) \ + fprintf ((s), "%08lx%08lx", _opcode_int64_high (x), _opcode_int64_low (x)) + +const char * program_name = NULL; +int debug = 0; + +#define NELEMS(a) (sizeof (a) / sizeof ((a)[0])) +#define tmalloc(X) (X *) xmalloc (sizeof (X)) + +/* The main opcode table entry. Each entry is a unique combination of + name and flags (no two entries in the table compare as being equal + via opcodes_eq). */ +struct main_entry +{ + /* The base name of this opcode. The names of its completers are + appended to it to generate the full instruction name. */ + struct string_entry *name; + /* The base opcode entry. Which one to use is a fairly arbitrary choice; + it uses the first one passed to add_opcode_entry. */ + struct ia64_opcode *opcode; + /* The list of completers that can be applied to this opcode. */ + struct completer_entry *completers; + /* Next entry in the chain. */ + struct main_entry *next; + /* Index in the main table. */ + int main_index; +} *maintable, **ordered_table; + +int otlen = 0; +int ottotlen = 0; +int opcode_count = 0; + +/* The set of possible completers for an opcode. */ +struct completer_entry +{ + /* This entry's index in the ia64_completer_table[] array. */ + int num; + + /* The name of the completer. */ + struct string_entry *name; + + /* This entry's parent. */ + struct completer_entry *parent; + + /* Set if this is a terminal completer (occurs at the end of an + opcode). */ + int is_terminal; + + /* An alternative completer. */ + struct completer_entry *alternative; + + /* Additional completers that can be appended to this one. */ + struct completer_entry *addl_entries; + + /* Before compute_completer_bits () is invoked, this contains the actual + instruction opcode for this combination of opcode and completers. + Afterwards, it contains those bits that are different from its + parent opcode. */ + ia64_insn bits; + + /* Bits set to 1 correspond to those bits in this completer's opcode + that are different from its parent completer's opcode (or from + the base opcode if the entry is the root of the opcode's completer + list). This field is filled in by compute_completer_bits (). */ + ia64_insn mask; + + /* Index into the opcode dependency list, or -1 if none. */ + int dependencies; + + /* Remember the order encountered in the opcode tables. */ + int order; +}; + +/* One entry in the disassembler name table. */ +struct disent +{ + /* The index into the ia64_name_dis array for this entry. */ + int ournum; + + /* The index into the main_table[] array. */ + int insn; + + /* The disassmbly priority of this entry. */ + int priority; + + /* The completer_index value for this entry. */ + int completer_index; + + /* How many other entries share this decode. */ + int nextcnt; + + /* The next entry sharing the same decode. */ + struct disent *nexte; + + /* The next entry in the name list. */ + struct disent *next_ent; +} *disinsntable = NULL; + +/* A state machine that will eventually be used to generate the + disassembler table. */ +struct bittree +{ + struct disent *disent; + struct bittree *bits[3]; /* 0, 1, and X (don't care). */ + int bits_to_skip; + int skip_flag; +} *bittree; + +/* The string table contains all opcodes and completers sorted in + alphabetical order. */ + +/* One entry in the string table. */ +struct string_entry +{ + /* The index in the ia64_strings[] array for this entry. */ + int num; + /* And the string. */ + char *s; +} **string_table = NULL; + +int strtablen = 0; +int strtabtotlen = 0; + + +/* Resource dependency entries. */ +struct rdep +{ + char *name; /* Resource name. */ + unsigned + mode:2, /* RAW, WAW, or WAR. */ + semantics:3; /* Dependency semantics. */ + char *extra; /* Additional semantics info. */ + int nchks; + int total_chks; /* Total #of terminal insns. */ + int *chks; /* Insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc. */ + int *chknotes; /* Dependency notes for each class. */ + int nregs; + int total_regs; /* Total #of terminal insns. */ + int *regs; /* Insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc. */ + int *regnotes; /* Dependency notes for each class. */ + + int waw_special; /* Special WAW dependency note. */ +} **rdeps = NULL; + +static int rdepslen = 0; +static int rdepstotlen = 0; + +/* Array of all instruction classes. */ +struct iclass +{ + char *name; /* Instruction class name. */ + int is_class; /* Is a class, not a terminal. */ + int nsubs; + int *subs; /* Other classes within this class. */ + int nxsubs; + int xsubs[4]; /* Exclusions. */ + char *comment; /* Optional comment. */ + int note; /* Optional note. */ + int terminal_resolved; /* Did we match this with anything? */ + int orphan; /* Detect class orphans. */ +} **ics = NULL; + +static int iclen = 0; +static int ictotlen = 0; + +/* An opcode dependency (chk/reg pair of dependency lists). */ +struct opdep +{ + int chk; /* index into dlists */ + int reg; /* index into dlists */ +} **opdeps; + +static int opdeplen = 0; +static int opdeptotlen = 0; + +/* A generic list of dependencies w/notes encoded. These may be shared. */ +struct deplist +{ + int len; + unsigned short *deps; +} **dlists; + +static int dlistlen = 0; +static int dlisttotlen = 0; + + +static void fail (const char *, ...) ATTRIBUTE_PRINTF_1; +static void warn (const char *, ...) ATTRIBUTE_PRINTF_1; +static struct rdep * insert_resource (const char *, enum ia64_dependency_mode); +static int deplist_equals (struct deplist *, struct deplist *); +static short insert_deplist (int, unsigned short *); +static short insert_dependencies (int, unsigned short *, int, unsigned short *); +static void mark_used (struct iclass *, int); +static int fetch_insn_class (const char *, int); +static int sub_compare (const void *, const void *); +static void load_insn_classes (void); +static void parse_resource_users (const char *, int **, int *, int **); +static int parse_semantics (char *); +static void add_dep (const char *, const char *, const char *, int, int, char *, int); +static void load_depfile (const char *, enum ia64_dependency_mode); +static void load_dependencies (void); +static int irf_operand (int, const char *); +static int in_iclass_mov_x (struct ia64_opcode *, struct iclass *, const char *, const char *); +static int in_iclass (struct ia64_opcode *, struct iclass *, const char *, const char *, int *); +static int lookup_regindex (const char *, int); +static int lookup_specifier (const char *); +static void print_dependency_table (void); +static struct string_entry * insert_string (char *); +static void gen_dis_table (struct bittree *); +static void print_dis_table (void); +static void generate_disassembler (void); +static void print_string_table (void); +static int completer_entries_eq (struct completer_entry *, struct completer_entry *); +static struct completer_entry * insert_gclist (struct completer_entry *); +static int get_prefix_len (const char *); +static void compute_completer_bits (struct main_entry *, struct completer_entry *); +static void collapse_redundant_completers (void); +static int insert_opcode_dependencies (struct ia64_opcode *, struct completer_entry *); +static void insert_completer_entry (struct ia64_opcode *, struct main_entry *, int); +static void print_completer_entry (struct completer_entry *); +static void print_completer_table (void); +static int opcodes_eq (struct ia64_opcode *, struct ia64_opcode *); +static void add_opcode_entry (struct ia64_opcode *); +static void print_main_table (void); +static void shrink (struct ia64_opcode *); +static void print_version (void); +static void usage (FILE *, int); +static void finish_distable (void); +static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, int); +static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, int); +static void compact_distree (struct bittree *); +static struct bittree * make_bittree_entry (void); +static struct disent * add_dis_table_ent (struct disent *, int, int, int); + + +static void +fail (const char *message, ...) +{ + va_list args; + + va_start (args, message); + fprintf (stderr, _("%s: Error: "), program_name); + vfprintf (stderr, message, args); + va_end (args); + xexit (1); +} + +static void +warn (const char *message, ...) +{ + va_list args; + + va_start (args, message); + + fprintf (stderr, _("%s: Warning: "), program_name); + vfprintf (stderr, message, args); + va_end (args); +} + +/* Add NAME to the resource table, where TYPE is RAW or WAW. */ +static struct rdep * +insert_resource (const char *name, enum ia64_dependency_mode type) +{ + if (rdepslen == rdepstotlen) + { + rdepstotlen += 20; + rdeps = (struct rdep **) + xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); + } + rdeps[rdepslen] = tmalloc(struct rdep); + memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); + rdeps[rdepslen]->name = xstrdup (name); + rdeps[rdepslen]->mode = type; + rdeps[rdepslen]->waw_special = 0; + + return rdeps[rdepslen++]; +} + +/* Are the lists of dependency indexes equivalent? */ +static int +deplist_equals (struct deplist *d1, struct deplist *d2) +{ + int i; + + if (d1->len != d2->len) + return 0; + + for (i = 0; i < d1->len; i++) + if (d1->deps[i] != d2->deps[i]) + return 0; + + return 1; +} + +/* Add the list of dependencies to the list of dependency lists. */ +static short +insert_deplist (int count, unsigned short *deps) +{ + /* Sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists. */ + struct deplist *list; + char set[0x10000]; + int i; + + memset ((void *)set, 0, sizeof (set)); + for (i = 0; i < count; i++) + set[deps[i]] = 1; + + count = 0; + for (i = 0; i < (int) sizeof (set); i++) + if (set[i]) + ++count; + + list = tmalloc (struct deplist); + list->len = count; + list->deps = (unsigned short *) malloc (sizeof (unsigned short) * count); + + for (i = 0, count = 0; i < (int) sizeof (set); i++) + if (set[i]) + list->deps[count++] = i; + + /* Does this list exist already? */ + for (i = 0; i < dlistlen; i++) + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } + + if (dlistlen == dlisttotlen) + { + dlisttotlen += 20; + dlists = (struct deplist **) + xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); + } + dlists[dlistlen] = list; + + return dlistlen++; +} + +/* Add the given pair of dependency lists to the opcode dependency list. */ +static short +insert_dependencies (int nchks, unsigned short *chks, + int nregs, unsigned short *regs) +{ + struct opdep *pair; + int i; + int regind = -1; + int chkind = -1; + + if (nregs > 0) + regind = insert_deplist (nregs, regs); + if (nchks > 0) + chkind = insert_deplist (nchks, chks); + + for (i = 0; i < opdeplen; i++) + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + + pair = tmalloc (struct opdep); + pair->chk = chkind; + pair->reg = regind; + + if (opdeplen == opdeptotlen) + { + opdeptotlen += 20; + opdeps = (struct opdep **) + xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); + } + opdeps[opdeplen] = pair; + + return opdeplen++; +} + +static void +mark_used (struct iclass *ic, int clear_terminals) +{ + int i; + + ic->orphan = 0; + if (clear_terminals) + ic->terminal_resolved = 1; + + for (i = 0; i < ic->nsubs; i++) + mark_used (ics[ic->subs[i]], clear_terminals); + + for (i = 0; i < ic->nxsubs; i++) + mark_used (ics[ic->xsubs[i]], clear_terminals); +} + +/* Look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array. */ +static int +fetch_insn_class (const char *full_name, int create) +{ + char *name; + char *notestr; + char *xsect; + char *comment; + int i, note = 0; + int ind; + int is_class = 0; + + if (CONST_STRNEQ (full_name, "IC:")) + { + name = xstrdup (full_name + 3); + is_class = 1; + } + else + name = xstrdup (full_name); + + if ((xsect = strchr(name, '\\')) != NULL) + is_class = 1; + if ((comment = strchr(name, '[')) != NULL) + is_class = 1; + if ((notestr = strchr(name, '+')) != NULL) + is_class = 1; + + /* If it is a composite class, then ignore comments and notes that come after + the '\\', since they don't apply to the part we are decoding now. */ + if (xsect) + { + if (comment > xsect) + comment = 0; + if (notestr > xsect) + notestr = 0; + } + + if (notestr) + { + char *nextnotestr; + + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + warn (_("multiple note %s not handled\n"), notestr); + } + } + + /* If it's a composite class, leave the notes and comments in place so that + we have a unique name for the composite class. Otherwise, we remove + them. */ + if (!xsect) + { + if (notestr) + *notestr = 0; + if (comment) + *comment = 0; + } + + for (i = 0; i < iclen; i++) + if (strcmp (name, ics[i]->name) == 0 + && ((comment == NULL && ics[i]->comment == NULL) + || (comment != NULL && ics[i]->comment != NULL + && strncmp (ics[i]->comment, comment, + strlen (ics[i]->comment)) == 0)) + && note == ics[i]->note) + return i; + + if (!create) + return -1; + + /* Doesn't exist, so make a new one. */ + if (iclen == ictotlen) + { + ictotlen += 20; + ics = (struct iclass **) + xrealloc (ics, (ictotlen) * sizeof (struct iclass *)); + } + + ind = iclen++; + ics[ind] = tmalloc (struct iclass); + memset ((void *)ics[ind], 0, sizeof (struct iclass)); + ics[ind]->name = xstrdup (name); + ics[ind]->is_class = is_class; + ics[ind]->orphan = 1; + + if (comment) + { + ics[ind]->comment = xstrdup (comment + 1); + ics[ind]->comment[strlen (ics[ind]->comment)-1] = 0; + } + + if (notestr) + ics[ind]->note = note; + + /* If it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ + if ((xsect || comment || notestr) && is_class) + { + /* First, populate with the class we're based on. */ + char *subname = name; + + if (xsect) + *xsect = 0; + else if (comment) + *comment = 0; + else if (notestr) + *notestr = 0; + + ics[ind]->nsubs = 1; + ics[ind]->subs = tmalloc(int); + ics[ind]->subs[0] = fetch_insn_class (subname, 1);; + } + + while (xsect) + { + char *subname = xsect + 1; + + xsect = strchr (subname, '\\'); + if (xsect) + *xsect = 0; + ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); + ics[ind]->nxsubs++; + } + free (name); + + return ind; +} + +/* For sorting a class's sub-class list only; make sure classes appear before + terminals. */ +static int +sub_compare (const void *e1, const void *e2) +{ + struct iclass *ic1 = ics[*(int *)e1]; + struct iclass *ic2 = ics[*(int *)e2]; + + if (ic1->is_class) + { + if (!ic2->is_class) + return -1; + } + else if (ic2->is_class) + return 1; + + return strcmp (ic1->name, ic2->name); +} + +static void +load_insn_classes (void) +{ + FILE *fp = fopen ("ia64-ic.tbl", "r"); + char buf[2048]; + + if (fp == NULL) + fail (_("can't find ia64-ic.tbl for reading\n")); + + /* Discard first line. */ + fgets (buf, sizeof(buf), fp); + + while (!feof (fp)) + { + int iclass; + char *name; + char *tmp; + + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + *tmp++ = '\0'; + + iclass = fetch_insn_class (name, 1); + ics[iclass]->is_class = 1; + + if (strcmp (name, "none") == 0) + { + ics[iclass]->is_class = 0; + ics[iclass]->terminal_resolved = 1; + continue; + } + + /* For this class, record all sub-classes. */ + while (*tmp) + { + char *subname; + int sub; + + while (*tmp && ISSPACE (*tmp)) + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + subname = tmp; + while (*tmp && *tmp != ',') + { + ++tmp; + if (tmp == buf + sizeof (buf)) + abort (); + } + if (*tmp == ',') + *tmp++ = '\0'; + + ics[iclass]->subs = (int *) + xrealloc ((void *)ics[iclass]->subs, + (ics[iclass]->nsubs + 1) * sizeof (int)); + + sub = fetch_insn_class (subname, 1); + ics[iclass]->subs = (int *) + xrealloc (ics[iclass]->subs, (ics[iclass]->nsubs + 1) * sizeof (int)); + ics[iclass]->subs[ics[iclass]->nsubs++] = sub; + } + + /* Make sure classes come before terminals. */ + qsort ((void *)ics[iclass]->subs, + ics[iclass]->nsubs, sizeof(int), sub_compare); + } + fclose (fp); + + if (debug) + printf ("%d classes\n", iclen); +} + +/* Extract the insn classes from the given line. */ +static void +parse_resource_users (const char *ref, int **usersp, int *nusersp, + int **notesp) +{ + int c; + char *line = xstrdup (ref); + char *tmp = line; + int *users = *usersp; + int count = *nusersp; + int *notes = *notesp; + + c = *tmp; + while (c != 0) + { + char *notestr; + int note; + char *xsect; + int iclass; + int create = 0; + char *name; + + while (ISSPACE (*tmp)) + ++tmp; + name = tmp; + while (*tmp && *tmp != ',') + ++tmp; + c = *tmp; + *tmp++ = '\0'; + + xsect = strchr (name, '\\'); + if ((notestr = strstr (name, "+")) != NULL) + { + char *nextnotestr; + + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + /* Note 13 always implies note 1. */ + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + warn (_("multiple note %s not handled\n"), notestr); + } + if (!xsect) + *notestr = '\0'; + } + else + note = 0; + + /* All classes are created when the insn class table is parsed; + Individual instructions might not appear until the dependency tables + are read. Only create new classes if it's *not* an insn class, + or if it's a composite class (which wouldn't necessarily be in the IC + table). */ + if (! CONST_STRNEQ (name, "IC:") || xsect != NULL) + create = 1; + + iclass = fetch_insn_class (name, create); + if (iclass != -1) + { + users = (int *) + xrealloc ((void *) users,(count + 1) * sizeof (int)); + notes = (int *) + xrealloc ((void *) notes,(count + 1) * sizeof (int)); + notes[count] = note; + users[count++] = iclass; + mark_used (ics[iclass], 0); + } + else if (debug) + printf("Class %s not found\n", name); + } + /* Update the return values. */ + *usersp = users; + *nusersp = count; + *notesp = notes; + + free (line); +} + +static int +parse_semantics (char *sem) +{ + if (strcmp (sem, "none") == 0) + return IA64_DVS_NONE; + else if (strcmp (sem, "implied") == 0) + return IA64_DVS_IMPLIED; + else if (strcmp (sem, "impliedF") == 0) + return IA64_DVS_IMPLIEDF; + else if (strcmp (sem, "data") == 0) + return IA64_DVS_DATA; + else if (strcmp (sem, "instr") == 0) + return IA64_DVS_INSTR; + else if (strcmp (sem, "specific") == 0) + return IA64_DVS_SPECIFIC; + else if (strcmp (sem, "stop") == 0) + return IA64_DVS_STOP; + else + return IA64_DVS_OTHER; +} + +static void +add_dep (const char *name, const char *chk, const char *reg, + int semantics, int mode, char *extra, int flag) +{ + struct rdep *rs; + + rs = insert_resource (name, mode); + + parse_resource_users (chk, &rs->chks, &rs->nchks, &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, &rs->regnotes); + + rs->semantics = semantics; + rs->extra = extra; + rs->waw_special = flag; +} + +static void +load_depfile (const char *filename, enum ia64_dependency_mode mode) +{ + FILE *fp = fopen (filename, "r"); + char buf[1024]; + + if (fp == NULL) + fail (_("can't find %s for reading\n"), filename); + + fgets (buf, sizeof(buf), fp); + while (!feof (fp)) + { + char *name, *tmp; + int semantics; + char *extra; + char *regp, *chkp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + ++tmp; + *tmp++ = '\0'; + + while (ISSPACE (*tmp)) + ++tmp; + regp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + chkp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (ISSPACE (*tmp)) + ++tmp; + semantics = parse_semantics (tmp); + extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; + + /* For WAW entries, if the chks and regs differ, we need to enter the + entries in both positions so that the tables will be parsed properly, + without a lot of extra work. */ + if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + add_dep (name, regp, chkp, semantics, mode, extra, 1); + } + else + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + } + } + fclose (fp); +} + +static void +load_dependencies (void) +{ + load_depfile ("ia64-raw.tbl", IA64_DV_RAW); + load_depfile ("ia64-waw.tbl", IA64_DV_WAW); + load_depfile ("ia64-war.tbl", IA64_DV_WAR); + + if (debug) + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); +} + +/* Is the given operand an indirect register file operand? */ +static int +irf_operand (int op, const char *field) +{ + if (!field) + { + return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 + || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 + || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 + || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; + } + else + { + return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) + || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) + || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) + || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) + || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) + || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) + || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) + || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); + } +} + +/* Handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes. */ +static int +in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field) +{ + int plain_mov = strcmp (idesc->name, "mov") == 0; + + if (!format) + return 0; + + switch (ic->name[4]) + { + default: + abort (); + case 'a': + { + int i = strcmp (idesc->name, "mov.i") == 0; + int m = strcmp (idesc->name, "mov.m") == 0; + int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; + int i28 = i && idesc->operands[1] == IA64_OPND_AR3; + int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; + int m31 = m && idesc->operands[1] == IA64_OPND_AR3; + int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; + int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; + + /* IC:mov ar */ + if (i2627) + return strstr (format, "I26") || strstr (format, "I27"); + if (i28) + return strstr (format, "I28") != NULL; + if (m2930) + return strstr (format, "M29") || strstr (format, "M30"); + if (m31) + return strstr (format, "M31") != NULL; + if (pseudo0 || pseudo1) + return 1; + } + break; + case 'b': + { + int i21 = idesc->operands[0] == IA64_OPND_B1; + int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; + if (i22) + return strstr (format, "I22") != NULL; + if (i21) + return strstr (format, "I21") != NULL; + } + break; + case 'c': + { + int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; + int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; + if (m32) + return strstr (format, "M32") != NULL; + if (m33) + return strstr (format, "M33") != NULL; + } + break; + case 'i': + if (ic->name[5] == 'n') + { + int m42 = plain_mov && irf_operand (idesc->operands[0], field); + int m43 = plain_mov && irf_operand (idesc->operands[1], field); + if (m42) + return strstr (format, "M42") != NULL; + if (m43) + return strstr (format, "M43") != NULL; + } + else if (ic->name[5] == 'p') + { + return idesc->operands[1] == IA64_OPND_IP; + } + else + abort (); + break; + case 'p': + if (ic->name[5] == 'r') + { + int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; + int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; + int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; + if (i23) + return strstr (format, "I23") != NULL; + if (i24) + return strstr (format, "I24") != NULL; + if (i25) + return strstr (format, "I25") != NULL; + } + else if (ic->name[5] == 's') + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + else + abort (); + break; + case 'u': + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + break; + } + return 0; +} + +/* Is the given opcode in the given insn class? */ +static int +in_iclass (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) +{ + int i; + int resolved = 0; + + if (ic->comment) + { + if (CONST_STRNEQ (ic->comment, "Format")) + { + /* Assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ + if (format) + { + if (strlen (ic->comment) < strlen (format)) + { + warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"), + ic->comment, format); + format = ic->comment; + } + } + else + format = ic->comment; + } + else if (CONST_STRNEQ (ic->comment, "Field")) + { + if (field) + warn (_("overlapping field %s->%s\n"), + ic->comment, field); + field = ic->comment; + } + } + + /* An insn class matches anything that is the same followed by completers, + except when the absence and presence of completers constitutes different + instructions. */ + if (ic->nsubs == 0 && ic->nxsubs == 0) + { + int is_mov = CONST_STRNEQ (idesc->name, "mov"); + int plain_mov = strcmp (idesc->name, "mov") == 0; + int len = strlen(ic->name); + + resolved = ((strncmp (ic->name, idesc->name, len) == 0) + && (idesc->name[len] == '\0' + || idesc->name[len] == '.')); + + /* All break, nop, and hint variations must match exactly. */ + if (resolved && + (strcmp (ic->name, "break") == 0 + || strcmp (ic->name, "nop") == 0 + || strcmp (ic->name, "hint") == 0)) + resolved = strcmp (ic->name, idesc->name) == 0; + + /* Assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block. */ + if (resolved && field) + { + /* Check Field(sf)==sN against opcode sN. */ + if (strstr(field, "(sf)==") != NULL) + { + char *sf; + + if ((sf = strstr (idesc->name, ".s")) != 0) + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; + } + /* Check Field(lftype)==XXX. */ + else if (strstr (field, "(lftype)") != NULL) + { + if (strstr (idesc->name, "fault") != NULL) + resolved = strstr (field, "fault") != NULL; + else + resolved = strstr (field, "fault") == NULL; + } + /* Handle Field(ctype)==XXX. */ + else if (strstr (field, "(ctype)") != NULL) + { + if (strstr (idesc->name, "or.andcm")) + resolved = strstr (field, "or.andcm") != NULL; + else if (strstr (idesc->name, "and.orcm")) + resolved = strstr (field, "and.orcm") != NULL; + else if (strstr (idesc->name, "orcm")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "or")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "andcm")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "and")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "unc")) + resolved = strstr (field, "unc") != NULL; + else + resolved = strcmp (field, "Field(ctype)==") == 0; + } + } + + if (resolved && format) + { + if (CONST_STRNEQ (idesc->name, "dep") + && strstr (format, "I13") != NULL) + resolved = idesc->operands[1] == IA64_OPND_IMM8; + else if (CONST_STRNEQ (idesc->name, "chk") + && strstr (format, "M21") != NULL) + resolved = idesc->operands[0] == IA64_OPND_F2; + else if (CONST_STRNEQ (idesc->name, "lfetch")) + resolved = (strstr (format, "M14 M15") != NULL + && (idesc->operands[1] == IA64_OPND_R2 + || idesc->operands[1] == IA64_OPND_IMM9b)); + else if (CONST_STRNEQ (idesc->name, "br.call") + && strstr (format, "B5") != NULL) + resolved = idesc->operands[1] == IA64_OPND_B2; + else if (CONST_STRNEQ (idesc->name, "br.call") + && strstr (format, "B3") != NULL) + resolved = idesc->operands[1] == IA64_OPND_TGT25c; + else if (CONST_STRNEQ (idesc->name, "brp") + && strstr (format, "B7") != NULL) + resolved = idesc->operands[0] == IA64_OPND_B2; + else if (strcmp (ic->name, "invala") == 0) + resolved = strcmp (idesc->name, ic->name) == 0; + else if (CONST_STRNEQ (idesc->name, "st") + && (strstr (format, "M5") != NULL + || strstr (format, "M10") != NULL)) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else if (CONST_STRNEQ (idesc->name, "ld") + && (strstr (format, "M2 M3") != NULL + || strstr (format, "M12") != NULL + || strstr (format, "M7 M8") != NULL)) + resolved = idesc->flags & IA64_OPCODE_POSTINC; + else + resolved = 0; + } + + /* Misc brl variations ('.cond' is optional); + plain brl matches brl.cond. */ + if (!resolved + && (strcmp (idesc->name, "brl") == 0 + || CONST_STRNEQ (idesc->name, "brl.")) + && strcmp (ic->name, "brl.cond") == 0) + { + resolved = 1; + } + + /* Misc br variations ('.cond' is optional). */ + if (!resolved + && (strcmp (idesc->name, "br") == 0 + || CONST_STRNEQ (idesc->name, "br.")) + && strcmp (ic->name, "br.cond") == 0) + { + if (format) + resolved = (strstr (format, "B4") != NULL + && idesc->operands[0] == IA64_OPND_B2) + || (strstr (format, "B1") != NULL + && idesc->operands[0] == IA64_OPND_TGT25c); + else + resolved = 1; + } + + /* probe variations. */ + if (!resolved && CONST_STRNEQ (idesc->name, "probe")) + { + resolved = strcmp (ic->name, "probe") == 0 + && !((strstr (idesc->name, "fault") != NULL) + ^ (format && strstr (format, "M40") != NULL)); + } + + /* mov variations. */ + if (!resolved && is_mov) + { + if (plain_mov) + { + /* mov alias for fmerge. */ + if (strcmp (ic->name, "fmerge") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_F1 + && idesc->operands[1] == IA64_OPND_F3; + } + /* mov alias for adds (r3 or imm14). */ + else if (strcmp (ic->name, "adds") == 0) + { + resolved = (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_R3 + || (idesc->operands[1] == IA64_OPND_IMM14))); + } + /* mov alias for addl. */ + else if (strcmp (ic->name, "addl") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_R1 + && idesc->operands[1] == IA64_OPND_IMM22; + } + } + + /* Some variants of mov and mov.[im]. */ + if (!resolved && CONST_STRNEQ (ic->name, "mov_")) + resolved = in_iclass_mov_x (idesc, ic, format, field); + } + + /* Keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn. */ + if (resolved) + ic->terminal_resolved = 1; + } + else for (i = 0; i < ic->nsubs; i++) + { + if (in_iclass (idesc, ics[ic->subs[i]], format, field, notep)) + { + int j; + + for (j = 0; j < ic->nxsubs; j++) + if (in_iclass (idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + + if (debug > 1) + printf ("%s is in IC %s\n", idesc->name, ic->name); + + resolved = 1; + break; + } + } + + /* If it's in this IC, add the IC note (if any) to the insn. */ + if (resolved) + { + if (ic->note && notep) + { + if (*notep && *notep != ic->note) + warn (_("overwriting note %d with note %d (IC:%s)\n"), + *notep, ic->note, ic->name); + + *notep = ic->note; + } + } + + return resolved; +} + + +static int +lookup_regindex (const char *name, int specifier) +{ + switch (specifier) + { + case IA64_RS_ARX: + if (strstr (name, "[RSC]")) + return 16; + if (strstr (name, "[BSP]")) + return 17; + else if (strstr (name, "[BSPSTORE]")) + return 18; + else if (strstr (name, "[RNAT]")) + return 19; + else if (strstr (name, "[FCR]")) + return 21; + else if (strstr (name, "[EFLAG]")) + return 24; + else if (strstr (name, "[CSD]")) + return 25; + else if (strstr (name, "[SSD]")) + return 26; + else if (strstr (name, "[CFLG]")) + return 27; + else if (strstr (name, "[FSR]")) + return 28; + else if (strstr (name, "[FIR]")) + return 29; + else if (strstr (name, "[FDR]")) + return 30; + else if (strstr (name, "[CCV]")) + return 32; + else if (strstr (name, "[ITC]")) + return 44; + else if (strstr (name, "[RUC]")) + return 45; + else if (strstr (name, "[PFS]")) + return 64; + else if (strstr (name, "[LC]")) + return 65; + else if (strstr (name, "[EC]")) + return 66; + abort (); + case IA64_RS_CRX: + if (strstr (name, "[DCR]")) + return 0; + else if (strstr (name, "[ITM]")) + return 1; + else if (strstr (name, "[IVA]")) + return 2; + else if (strstr (name, "[PTA]")) + return 8; + else if (strstr (name, "[GPTA]")) + return 9; + else if (strstr (name, "[IPSR]")) + return 16; + else if (strstr (name, "[ISR]")) + return 17; + else if (strstr (name, "[IIP]")) + return 19; + else if (strstr (name, "[IFA]")) + return 20; + else if (strstr (name, "[ITIR]")) + return 21; + else if (strstr (name, "[IIPA]")) + return 22; + else if (strstr (name, "[IFS]")) + return 23; + else if (strstr (name, "[IIM]")) + return 24; + else if (strstr (name, "[IHA]")) + return 25; + else if (strstr (name, "[LID]")) + return 64; + else if (strstr (name, "[IVR]")) + return 65; + else if (strstr (name, "[TPR]")) + return 66; + else if (strstr (name, "[EOI]")) + return 67; + else if (strstr (name, "[ITV]")) + return 72; + else if (strstr (name, "[PMV]")) + return 73; + else if (strstr (name, "[CMCV]")) + return 74; + abort (); + case IA64_RS_PSR: + if (strstr (name, ".be")) + return 1; + else if (strstr (name, ".up")) + return 2; + else if (strstr (name, ".ac")) + return 3; + else if (strstr (name, ".mfl")) + return 4; + else if (strstr (name, ".mfh")) + return 5; + else if (strstr (name, ".ic")) + return 13; + else if (strstr (name, ".i")) + return 14; + else if (strstr (name, ".pk")) + return 15; + else if (strstr (name, ".dt")) + return 17; + else if (strstr (name, ".dfl")) + return 18; + else if (strstr (name, ".dfh")) + return 19; + else if (strstr (name, ".sp")) + return 20; + else if (strstr (name, ".pp")) + return 21; + else if (strstr (name, ".di")) + return 22; + else if (strstr (name, ".si")) + return 23; + else if (strstr (name, ".db")) + return 24; + else if (strstr (name, ".lp")) + return 25; + else if (strstr (name, ".tb")) + return 26; + else if (strstr (name, ".rt")) + return 27; + else if (strstr (name, ".cpl")) + return 32; + else if (strstr (name, ".rs")) + return 34; + else if (strstr (name, ".mc")) + return 35; + else if (strstr (name, ".it")) + return 36; + else if (strstr (name, ".id")) + return 37; + else if (strstr (name, ".da")) + return 38; + else if (strstr (name, ".dd")) + return 39; + else if (strstr (name, ".ss")) + return 40; + else if (strstr (name, ".ri")) + return 41; + else if (strstr (name, ".ed")) + return 43; + else if (strstr (name, ".bn")) + return 44; + else if (strstr (name, ".ia")) + return 45; + else if (strstr (name, ".vm")) + return 46; + else + abort (); + default: + break; + } + return REG_NONE; +} + +static int +lookup_specifier (const char *name) +{ + if (strchr (name, '%')) + { + if (strstr (name, "AR[K%]") != NULL) + return IA64_RS_AR_K; + if (strstr (name, "AR[UNAT]") != NULL) + return IA64_RS_AR_UNAT; + if (strstr (name, "AR%, % in 8") != NULL) + return IA64_RS_AR; + if (strstr (name, "AR%, % in 48") != NULL) + return IA64_RS_ARb; + if (strstr (name, "BR%") != NULL) + return IA64_RS_BR; + if (strstr (name, "CR[IIB%]") != NULL) + return IA64_RS_CR_IIB; + if (strstr (name, "CR[IRR%]") != NULL) + return IA64_RS_CR_IRR; + if (strstr (name, "CR[LRR%]") != NULL) + return IA64_RS_CR_LRR; + if (strstr (name, "CR%") != NULL) + return IA64_RS_CR; + if (strstr (name, "FR%, % in 0") != NULL) + return IA64_RS_FR; + if (strstr (name, "FR%, % in 2") != NULL) + return IA64_RS_FRb; + if (strstr (name, "GR%") != NULL) + return IA64_RS_GR; + if (strstr (name, "PR%, % in 1 ") != NULL) + return IA64_RS_PR; + if (strstr (name, "PR%, % in 16 ") != NULL) + return IA64_RS_PRr; + + warn (_("don't know how to specify %% dependency %s\n"), + name); + } + else if (strchr (name, '#')) + { + if (strstr (name, "CPUID#") != NULL) + return IA64_RS_CPUID; + if (strstr (name, "DBR#") != NULL) + return IA64_RS_DBR; + if (strstr (name, "IBR#") != NULL) + return IA64_RS_IBR; + if (strstr (name, "MSR#") != NULL) + return IA64_RS_MSR; + if (strstr (name, "PKR#") != NULL) + return IA64_RS_PKR; + if (strstr (name, "PMC#") != NULL) + return IA64_RS_PMC; + if (strstr (name, "PMD#") != NULL) + return IA64_RS_PMD; + if (strstr (name, "RR#") != NULL) + return IA64_RS_RR; + + warn (_("Don't know how to specify # dependency %s\n"), + name); + } + else if (CONST_STRNEQ (name, "AR[FPSR]")) + return IA64_RS_AR_FPSR; + else if (CONST_STRNEQ (name, "AR[")) + return IA64_RS_ARX; + else if (CONST_STRNEQ (name, "CR[")) + return IA64_RS_CRX; + else if (CONST_STRNEQ (name, "PSR.")) + return IA64_RS_PSR; + else if (strcmp (name, "InService*") == 0) + return IA64_RS_INSERVICE; + else if (strcmp (name, "GR0") == 0) + return IA64_RS_GR0; + else if (strcmp (name, "CFM") == 0) + return IA64_RS_CFM; + else if (strcmp (name, "PR63") == 0) + return IA64_RS_PR63; + else if (strcmp (name, "RSE") == 0) + return IA64_RS_RSE; + + return IA64_RS_ANY; +} + +static void +print_dependency_table (void) +{ + int i, j; + + if (debug) + { + for (i=0;i < iclen;i++) + { + if (ics[i]->is_class) + { + if (!ics[i]->nsubs) + { + if (ics[i]->comment) + warn (_("IC:%s [%s] has no terminals or sub-classes\n"), + ics[i]->name, ics[i]->comment); + else + warn (_("IC:%s has no terminals or sub-classes\n"), + ics[i]->name); + } + } + else + { + if (!ics[i]->terminal_resolved && !ics[i]->orphan) + { + if (ics[i]->comment) + warn (_("no insns mapped directly to terminal IC %s [%s]"), + ics[i]->name, ics[i]->comment); + else + warn (_("no insns mapped directly to terminal IC %s\n"), + ics[i]->name); + } + } + } + + for (i = 0; i < iclen; i++) + { + if (ics[i]->orphan) + { + mark_used (ics[i], 1); + warn (_("class %s is defined but not used\n"), + ics[i]->name); + } + } + + if (debug > 1) + for (i = 0; i < rdepslen; i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + + if (rdeps[i]->total_chks == 0) + { + if (rdeps[i]->total_regs) + warn (_("Warning: rsrc %s (%s) has no chks\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode]); + else + warn (_("Warning: rsrc %s (%s) has no chks or regs\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + else if (rdeps[i]->total_regs == 0) + warn (_("rsrc %s (%s) has no regs\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + } + + /* The dependencies themselves. */ + printf ("static const struct ia64_dependency\ndependencies[] = {\n"); + for (i = 0; i < rdepslen; i++) + { + /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual + resource used. */ + int specifier = lookup_specifier (rdeps[i]->name); + int regindex = lookup_regindex (rdeps[i]->name, specifier); + + printf (" { \"%s\", %d, %d, %d, %d, ", + rdeps[i]->name, specifier, + (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); + if (rdeps[i]->semantics == IA64_DVS_OTHER) + { + const char *quote, *rest; + + putchar ('\"'); + rest = rdeps[i]->extra; + quote = strchr (rest, '\"'); + while (quote != NULL) + { + printf ("%.*s\\\"", (int) (quote - rest), rest); + rest = quote + 1; + quote = strchr (rest, '\"'); + } + printf ("%s\", ", rest); + } + else + printf ("NULL, "); + printf("},\n"); + } + printf ("};\n\n"); + + /* And dependency lists. */ + for (i=0;i < dlistlen;i++) + { + int len = 2; + printf ("static const unsigned short dep%d[] = {\n ", i); + for (j=0;j < dlists[i]->len; j++) + { + len += printf ("%d, ", dlists[i]->deps[j]); + if (len > 75) + { + printf("\n "); + len = 2; + } + } + printf ("\n};\n\n"); + } + + /* And opcode dependency list. */ + printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); + printf ("static const struct ia64_opcode_dependency\n"); + printf ("op_dependencies[] = {\n"); + for (i = 0; i < opdeplen; i++) + { + printf (" { "); + if (opdeps[i]->chk == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); + if (opdeps[i]->reg == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); + printf ("},\n"); + } + printf ("};\n\n"); +} + + +/* Add STR to the string table. */ +static struct string_entry * +insert_string (char *str) +{ + int start = 0, end = strtablen; + int i, x; + + if (strtablen == strtabtotlen) + { + strtabtotlen += 20; + string_table = (struct string_entry **) + xrealloc (string_table, + sizeof (struct string_entry **) * strtabtotlen); + } + + if (strtablen == 0) + { + strtablen = 1; + string_table[0] = tmalloc (struct string_entry); + string_table[0]->s = xstrdup (str); + string_table[0]->num = 0; + return string_table[0]; + } + + if (strcmp (str, string_table[strtablen - 1]->s) > 0) + i = end; + else if (strcmp (str, string_table[0]->s) < 0) + i = 0; + else + { + while (1) + { + int c; + + i = (start + end) / 2; + c = strcmp (str, string_table[i]->s); + + if (c < 0) + end = i - 1; + else if (c == 0) + return string_table[i]; + else + start = i + 1; + + if (start > end) + break; + } + } + + for (; i > 0 && i < strtablen; i--) + if (strcmp (str, string_table[i - 1]->s) > 0) + break; + + for (; i < strtablen; i++) + if (strcmp (str, string_table[i]->s) < 0) + break; + + for (x = strtablen - 1; x >= i; x--) + { + string_table[x + 1] = string_table[x]; + string_table[x + 1]->num = x + 1; + } + + string_table[i] = tmalloc (struct string_entry); + string_table[i]->s = xstrdup (str); + string_table[i]->num = i; + strtablen++; + + return string_table[i]; +} + +static struct bittree * +make_bittree_entry (void) +{ + struct bittree *res = tmalloc (struct bittree); + + res->disent = NULL; + res->bits[0] = NULL; + res->bits[1] = NULL; + res->bits[2] = NULL; + res->skip_flag = 0; + res->bits_to_skip = 0; + return res; +} + + +static struct disent * +add_dis_table_ent (struct disent *which, int insn, int order, + int completer_index) +{ + int ci = 0; + struct disent *ent; + + if (which != NULL) + { + ent = which; + + ent->nextcnt++; + while (ent->nexte != NULL) + ent = ent->nexte; + + ent = (ent->nexte = tmalloc (struct disent)); + } + else + { + ent = tmalloc (struct disent); + ent->next_ent = disinsntable; + disinsntable = ent; + which = ent; + } + ent->nextcnt = 0; + ent->nexte = NULL; + ent->insn = insn; + ent->priority = order; + + while (completer_index != 1) + { + ci = (ci << 1) | (completer_index & 1); + completer_index >>= 1; + } + ent->completer_index = ci; + return which; +} + +static void +finish_distable (void) +{ + struct disent *ent = disinsntable; + struct disent *prev = ent; + + ent->ournum = 32768; + while ((ent = ent->next_ent) != NULL) + { + ent->ournum = prev->ournum + prev->nextcnt + 1; + prev = ent; + } +} + +static void +insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode, + ia64_insn mask, int opcodenum, int order, + int completer_index) +{ + ia64_insn m; + int b; + struct bittree *next; + + if (bit == -1) + { + struct disent *nent = add_dis_table_ent (curr_ent->disent, + opcodenum, order, + completer_index); + curr_ent->disent = nent; + return; + } + + m = ((ia64_insn) 1) << bit; + + if (mask & m) + b = (opcode & m) ? 1 : 0; + else + b = 2; + + next = curr_ent->bits[b]; + if (next == NULL) + { + next = make_bittree_entry (); + curr_ent->bits[b] = next; + } + insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, + completer_index); +} + +static void +add_dis_entry (struct bittree *first, ia64_insn opcode, ia64_insn mask, + int opcodenum, struct completer_entry *ent, int completer_index) +{ + if (completer_index & (1 << 20)) + abort (); + + while (ent != NULL) + { + ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; + add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, + (completer_index << 1) | 1); + + if (ent->is_terminal) + { + insert_bit_table_ent (bittree, 40, newopcode, mask, + opcodenum, opcode_count - ent->order - 1, + (completer_index << 1) | 1); + } + completer_index <<= 1; + ent = ent->alternative; + } +} + +/* This optimization pass combines multiple "don't care" nodes. */ +static void +compact_distree (struct bittree *ent) +{ +#define IS_SKIP(ent) \ + ((ent->bits[2] !=NULL) \ + && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) + + int bitcnt = 0; + struct bittree *nent = ent; + int x; + + while (IS_SKIP (nent)) + { + bitcnt++; + nent = nent->bits[2]; + } + + if (bitcnt) + { + struct bittree *next = ent->bits[2]; + + ent->bits[0] = nent->bits[0]; + ent->bits[1] = nent->bits[1]; + ent->bits[2] = nent->bits[2]; + ent->disent = nent->disent; + ent->skip_flag = 1; + ent->bits_to_skip = bitcnt; + while (next != nent) + { + struct bittree *b = next; + next = next->bits[2]; + free (b); + } + free (nent); + } + + for (x = 0; x < 3; x++) + { + struct bittree *i = ent->bits[x]; + + if (i != NULL) + compact_distree (i); + } +} + +static unsigned char *insn_list; +static int insn_list_len = 0; +static int tot_insn_list_len = 0; + +/* Generate the disassembler state machine corresponding to the tree + in ENT. */ +static void +gen_dis_table (struct bittree *ent) +{ + int x; + int our_offset = insn_list_len; + int bitsused = 5; + int totbits = bitsused; + int needed_bytes; + int zero_count = 0; + int zero_dest = 0; /* Initialize this with 0 to keep gcc quiet... */ + + /* If this is a terminal entry, there's no point in skipping any + bits. */ + if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && + ent->bits[2] == NULL) + { + if (ent->disent == NULL) + abort (); + else + ent->skip_flag = 0; + } + + /* Calculate the amount of space needed for this entry, or at least + a conservatively large approximation. */ + if (ent->skip_flag) + totbits += 5; + + for (x = 1; x < 3; x++) + if (ent->bits[x] != NULL) + totbits += 16; + + if (ent->disent != NULL) + { + if (ent->bits[2] != NULL) + abort (); + + totbits += 16; + } + + /* Now allocate the space. */ + needed_bytes = (totbits + 7) / 8; + if ((needed_bytes + insn_list_len) > tot_insn_list_len) + { + tot_insn_list_len += 256; + insn_list = (unsigned char *) xrealloc (insn_list, tot_insn_list_len); + } + our_offset = insn_list_len; + insn_list_len += needed_bytes; + memset (insn_list + our_offset, 0, needed_bytes); + + /* Encode the skip entry by setting bit 6 set in the state op field, + and store the # of bits to skip immediately after. */ + if (ent->skip_flag) + { + bitsused += 5; + insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); + insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); + } + +#define IS_ONLY_IFZERO(ENT) \ + ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ + && (ENT)->disent == NULL && (ENT)->skip_flag == 0) + + /* Store an "if (bit is zero)" instruction by setting bit 7 in the + state op field. */ + if (ent->bits[0] != NULL) + { + struct bittree *nent = ent->bits[0]; + zero_count = 0; + + insn_list[our_offset] |= 0x80; + + /* We can encode sequences of multiple "if (bit is zero)" tests + by storing the # of zero bits to check in the lower 3 bits of + the instruction. However, this only applies if the state + solely tests for a zero bit. */ + + if (IS_ONLY_IFZERO (ent)) + { + while (IS_ONLY_IFZERO (nent) && zero_count < 7) + { + nent = nent->bits[0]; + zero_count++; + } + + insn_list[our_offset + 0] |= zero_count; + } + zero_dest = insn_list_len; + gen_dis_table (nent); + } + + /* Now store the remaining tests. We also handle a sole "termination + entry" by storing it as an "any bit" test. */ + + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) + { + struct bittree *i = ent->bits[x]; + int idest; + int currbits = 15; + + if (i != NULL) + { + /* If the instruction being branched to only consists of + a termination entry, use the termination entry as the + place to branch to instead. */ + if (i->bits[0] == NULL && i->bits[1] == NULL + && i->bits[2] == NULL && i->disent != NULL) + { + idest = i->disent->ournum; + i = NULL; + } + else + idest = insn_list_len - our_offset; + } + else + idest = ent->disent->ournum; + + /* If the destination offset for the if (bit is 1) test is less + than 256 bytes away, we can store it as 8-bits instead of 16; + the instruction has bit 5 set for the 16-bit address, and bit + 4 for the 8-bit address. Since we've already allocated 16 + bits for the address we need to deallocate the space. + + Note that branchings within the table are relative, and + there are no branches that branch past our instruction yet + so we do not need to adjust any other offsets. */ + if (x == 1) + { + if (idest <= 256) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 7; + totbits -= 8; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x10; + idest--; + } + else + insn_list[our_offset] |= 0x20; + } + else + { + /* An instruction which solely consists of a termination + marker and whose disassembly name index is < 4096 + can be stored in 16 bits. The encoding is slightly + odd; the upper 4 bits of the instruction are 0x3, and + bit 3 loses its normal meaning. */ + + if (ent->bits[0] == NULL && ent->bits[1] == NULL + && ent->bits[2] == NULL && ent->skip_flag == 0 + && ent->disent != NULL + && ent->disent->ournum < (32768 + 4096)) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 11; + totbits -= 5; + bitsused--; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x30; + idest &= ~32768; + } + else + insn_list[our_offset] |= 0x08; + } + + if (debug) + { + int id = idest; + + if (i == NULL) + id |= 32768; + else if (! (id & 32768)) + id += our_offset; + + if (x == 1) + printf ("%d: if (1) goto %d\n", our_offset, id); + else + printf ("%d: try %d\n", our_offset, id); + } + + /* Store the address of the entry being branched to. */ + while (currbits >= 0) + { + unsigned char *byte = insn_list + our_offset + bitsused / 8; + + if (idest & (1 << currbits)) + *byte |= (1 << (7 - (bitsused % 8))); + + bitsused++; + currbits--; + } + + /* Now generate the states for the entry being branched to. */ + if (i != NULL) + gen_dis_table (i); + } + } + + if (debug) + { + if (ent->skip_flag) + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); + + if (ent->bits[0] != NULL) + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); + } + + if (bitsused != totbits) + abort (); +} + +static void +print_dis_table (void) +{ + int x; + struct disent *cent = disinsntable; + + printf ("static const char dis_table[] = {\n"); + for (x = 0; x < insn_list_len; x++) + { + if ((x > 0) && ((x % 12) == 0)) + printf ("\n"); + + printf ("0x%02x, ", insn_list[x]); + } + printf ("\n};\n\n"); + + printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); + while (cent != NULL) + { + struct disent *ent = cent; + + while (ent != NULL) + { + printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index, + ent->insn, (ent->nexte != NULL ? 1 : 0), + ent->priority); + ent = ent->nexte; + } + cent = cent->next_ent; + } + printf ("};\n\n"); +} + +static void +generate_disassembler (void) +{ + int i; + + bittree = make_bittree_entry (); + + for (i = 0; i < otlen; i++) + { + struct main_entry *ptr = ordered_table[i]; + + if (ptr->opcode->type != IA64_TYPE_DYN) + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, + ptr->main_index, + ptr->completers, 1); + } + + compact_distree (bittree); + finish_distable (); + gen_dis_table (bittree); + + print_dis_table (); +} + +static void +print_string_table (void) +{ + int x; + char lbuf[80], buf[80]; + int blen = 0; + + printf ("static const char * const ia64_strings[] = {\n"); + lbuf[0] = '\0'; + + for (x = 0; x < strtablen; x++) + { + int len; + + if (strlen (string_table[x]->s) > 75) + abort (); + + sprintf (buf, " \"%s\",", string_table[x]->s); + len = strlen (buf); + + if ((blen + len) > 75) + { + printf (" %s\n", lbuf); + lbuf[0] = '\0'; + blen = 0; + } + strcat (lbuf, buf); + blen += len; + } + + if (blen > 0) + printf (" %s\n", lbuf); + + printf ("};\n\n"); +} + +static struct completer_entry **glist; +static int glistlen = 0; +static int glisttotlen = 0; + +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ + +static int +completer_entries_eq (struct completer_entry *ent1, + struct completer_entry *ent2) +{ + while (ent1 != NULL && ent2 != NULL) + { + if (ent1->name->num != ent2->name->num + || ent1->bits != ent2->bits + || ent1->mask != ent2->mask + || ent1->is_terminal != ent2->is_terminal + || ent1->dependencies != ent2->dependencies + || ent1->order != ent2->order) + return 0; + + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) + return 0; + + ent1 = ent1->alternative; + ent2 = ent2->alternative; + } + + return ent1 == ent2; +} + +/* Insert ENT into the global list of completers and return it. If an + equivalent entry (according to completer_entries_eq) already exists, + it is returned instead. */ +static struct completer_entry * +insert_gclist (struct completer_entry *ent) +{ + if (ent != NULL) + { + int i; + int x; + int start = 0, end; + + ent->addl_entries = insert_gclist (ent->addl_entries); + ent->alternative = insert_gclist (ent->alternative); + + i = glistlen / 2; + end = glistlen; + + if (glisttotlen == glistlen) + { + glisttotlen += 20; + glist = (struct completer_entry **) + xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); + } + + if (glistlen == 0) + { + glist[0] = ent; + glistlen = 1; + return ent; + } + + if (ent->name->num < glist[0]->name->num) + i = 0; + else if (ent->name->num > glist[end - 1]->name->num) + i = end; + else + { + int c; + + while (1) + { + i = (start + end) / 2; + c = ent->name->num - glist[i]->name->num; + + if (c < 0) + end = i - 1; + else if (c == 0) + { + while (i > 0 + && ent->name->num == glist[i - 1]->name->num) + i--; + + break; + } + else + start = i + 1; + + if (start > end) + break; + } + + if (c == 0) + { + while (i < glistlen) + { + if (ent->name->num != glist[i]->name->num) + break; + + if (completer_entries_eq (ent, glist[i])) + return glist[i]; + + i++; + } + } + } + + for (; i > 0 && i < glistlen; i--) + if (ent->name->num >= glist[i - 1]->name->num) + break; + + for (; i < glistlen; i++) + if (ent->name->num < glist[i]->name->num) + break; + + for (x = glistlen - 1; x >= i; x--) + glist[x + 1] = glist[x]; + + glist[i] = ent; + glistlen++; + } + return ent; +} + +static int +get_prefix_len (const char *name) +{ + char *c; + + if (name[0] == '\0') + return 0; + + c = strchr (name, '.'); + if (c != NULL) + return c - name; + else + return strlen (name); +} + +static void +compute_completer_bits (struct main_entry *ment, struct completer_entry *ent) +{ + while (ent != NULL) + { + compute_completer_bits (ment, ent->addl_entries); + + if (ent->is_terminal) + { + ia64_insn mask = 0; + ia64_insn our_bits = ent->bits; + struct completer_entry *p = ent->parent; + ia64_insn p_bits; + int x; + + while (p != NULL && ! p->is_terminal) + p = p->parent; + + if (p != NULL) + p_bits = p->bits; + else + p_bits = ment->opcode->opcode; + + for (x = 0; x < 64; x++) + { + ia64_insn m = ((ia64_insn) 1) << x; + + if ((p_bits & m) != (our_bits & m)) + mask |= m; + else + our_bits &= ~m; + } + ent->bits = our_bits; + ent->mask = mask; + } + else + { + ent->bits = 0; + ent->mask = 0; + } + + ent = ent->alternative; + } +} + +/* Find identical completer trees that are used in different + instructions and collapse their entries. */ +static void +collapse_redundant_completers (void) +{ + struct main_entry *ptr; + int x; + + for (ptr = maintable; ptr != NULL; ptr = ptr->next) + { + if (ptr->completers == NULL) + abort (); + + compute_completer_bits (ptr, ptr->completers); + ptr->completers = insert_gclist (ptr->completers); + } + + /* The table has been finalized, now number the indexes. */ + for (x = 0; x < glistlen; x++) + glist[x]->num = x; +} + + +/* Attach two lists of dependencies to each opcode. + 1) all resources which, when already marked in use, conflict with this + opcode (chks) + 2) all resources which must be marked in use when this opcode is used + (regs). */ +static int +insert_opcode_dependencies (struct ia64_opcode *opc, + struct completer_entry *cmp ATTRIBUTE_UNUSED) +{ + /* Note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough. */ + int i; + int nregs = 0; + unsigned short regs[256]; + int nchks = 0; + unsigned short chks[256]; + /* Flag insns for which no class matched; there should be none. */ + int no_class_found = 1; + + for (i = 0; i < rdepslen; i++) + { + struct rdep *rs = rdeps[i]; + int j; + + if (strcmp (opc->name, "cmp.eq.and") == 0 + && CONST_STRNEQ (rs->name, "PR%") + && rs->mode == 1) + no_class_found = 99; + + for (j=0; j < rs->nregs;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources. */ + if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR")) + ic_note = 0; + + if (ic_note != 0 && rs->regnotes[j] != 0 + && ic_note != rs->regnotes[j] + && !(ic_note == 11 && rs->regnotes[j] == 1)) + warn (_("IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); + /* Instruction class notes override resource notes. + So far, only note 11 applies to an IC instead of a resource, + and note 11 implies note 1. */ + if (ic_note) + regs[nregs++] = RDEP(ic_note, i); + else + regs[nregs++] = RDEP(rs->regnotes[j], i); + no_class_found = 0; + ++rs->total_regs; + } + } + + for (j = 0; j < rs->nchks; j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources. */ + if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR")) + ic_note = 0; + + if (ic_note != 0 && rs->chknotes[j] != 0 + && ic_note != rs->chknotes[j] + && !(ic_note == 11 && rs->chknotes[j] == 1)) + warn (_("IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); + if (ic_note) + chks[nchks++] = RDEP(ic_note, i); + else + chks[nchks++] = RDEP(rs->chknotes[j], i); + no_class_found = 0; + ++rs->total_chks; + } + } + } + + if (no_class_found) + warn (_("opcode %s has no class (ops %d %d %d)\n"), + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); + + return insert_dependencies (nchks, chks, nregs, regs); +} + +static void +insert_completer_entry (struct ia64_opcode *opc, struct main_entry *tabent, + int order) +{ + struct completer_entry **ptr = &tabent->completers; + struct completer_entry *parent = NULL; + char pcopy[129], *prefix; + int at_end = 0; + + if (strlen (opc->name) > 128) + abort (); + + strcpy (pcopy, opc->name); + prefix = pcopy + get_prefix_len (pcopy); + + if (prefix[0] != '\0') + prefix++; + + while (! at_end) + { + int need_new_ent = 1; + int plen = get_prefix_len (prefix); + struct string_entry *sent; + + at_end = (prefix[plen] == '\0'); + prefix[plen] = '\0'; + sent = insert_string (prefix); + + while (*ptr != NULL) + { + int cmpres = sent->num - (*ptr)->name->num; + + if (cmpres == 0) + { + need_new_ent = 0; + break; + } + else + ptr = &((*ptr)->alternative); + } + + if (need_new_ent) + { + struct completer_entry *nent = tmalloc (struct completer_entry); + + nent->name = sent; + nent->parent = parent; + nent->addl_entries = NULL; + nent->alternative = *ptr; + *ptr = nent; + nent->is_terminal = 0; + nent->dependencies = -1; + } + + if (! at_end) + { + parent = *ptr; + ptr = &((*ptr)->addl_entries); + prefix += plen + 1; + } + } + + if ((*ptr)->is_terminal) + abort (); + + (*ptr)->is_terminal = 1; + (*ptr)->mask = (ia64_insn)-1; + (*ptr)->bits = opc->opcode; + (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); + (*ptr)->order = order; +} + +static void +print_completer_entry (struct completer_entry *ent) +{ + int moffset = 0; + ia64_insn mask = ent->mask, bits = ent->bits; + + if (mask != 0) + { + while (! (mask & 1)) + { + moffset++; + mask = mask >> 1; + bits = bits >> 1; + } + + if (bits & 0xffffffff00000000LL) + abort (); + } + + printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", + (int)bits, + (int)mask, + ent->name->num, + ent->alternative != NULL ? ent->alternative->num : -1, + ent->addl_entries != NULL ? ent->addl_entries->num : -1, + moffset, + ent->is_terminal ? 1 : 0, + ent->dependencies); +} + +static void +print_completer_table (void) +{ + int x; + + printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); + for (x = 0; x < glistlen; x++) + print_completer_entry (glist[x]); + printf ("};\n\n"); +} + +static int +opcodes_eq (struct ia64_opcode *opc1, struct ia64_opcode *opc2) +{ + int x; + int plen1, plen2; + + if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) + || (opc1->num_outputs != opc2->num_outputs) + || (opc1->flags != opc2->flags)) + return 0; + + for (x = 0; x < 5; x++) + if (opc1->operands[x] != opc2->operands[x]) + return 0; + + plen1 = get_prefix_len (opc1->name); + plen2 = get_prefix_len (opc2->name); + + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) + return 1; + + return 0; +} + +static void +add_opcode_entry (struct ia64_opcode *opc) +{ + struct main_entry **place; + struct string_entry *name; + char prefix[129]; + int found_it = 0; + + if (strlen (opc->name) > 128) + abort (); + + place = &maintable; + strcpy (prefix, opc->name); + prefix[get_prefix_len (prefix)] = '\0'; + name = insert_string (prefix); + + /* Walk the list of opcode table entries. If it's a new + instruction, allocate and fill in a new entry. Note + the main table is alphabetical by opcode name. */ + + while (*place != NULL) + { + if ((*place)->name->num == name->num + && opcodes_eq ((*place)->opcode, opc)) + { + found_it = 1; + break; + } + if ((*place)->name->num > name->num) + break; + + place = &((*place)->next); + } + if (! found_it) + { + struct main_entry *nent = tmalloc (struct main_entry); + + nent->name = name; + nent->opcode = opc; + nent->next = *place; + nent->completers = 0; + *place = nent; + + if (otlen == ottotlen) + { + ottotlen += 20; + ordered_table = (struct main_entry **) + xrealloc (ordered_table, sizeof (struct main_entry *) * ottotlen); + } + ordered_table[otlen++] = nent; + } + + insert_completer_entry (opc, *place, opcode_count++); +} + +static void +print_main_table (void) +{ + struct main_entry *ptr = maintable; + int tindex = 0; + + printf ("static const struct ia64_main_table\nmain_table[] = {\n"); + while (ptr != NULL) + { + printf (" { %d, %d, %d, 0x", + ptr->name->num, + ptr->opcode->type, + ptr->opcode->num_outputs); + opcode_fprintf_vma (stdout, ptr->opcode->opcode); + printf ("ull, 0x"); + opcode_fprintf_vma (stdout, ptr->opcode->mask); + printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + ptr->opcode->operands[0], + ptr->opcode->operands[1], + ptr->opcode->operands[2], + ptr->opcode->operands[3], + ptr->opcode->operands[4], + ptr->opcode->flags, + ptr->completers->num); + + ptr->main_index = tindex++; + + ptr = ptr->next; + } + printf ("};\n\n"); +} + +static void +shrink (struct ia64_opcode *table) +{ + int curr_opcode; + + for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) + { + add_opcode_entry (table + curr_opcode); + if (table[curr_opcode].num_outputs == 2 + && ((table[curr_opcode].operands[0] == IA64_OPND_P1 + && table[curr_opcode].operands[1] == IA64_OPND_P2) + || (table[curr_opcode].operands[0] == IA64_OPND_P2 + && table[curr_opcode].operands[1] == IA64_OPND_P1))) + { + struct ia64_opcode *alias = tmalloc(struct ia64_opcode); + unsigned i; + + *alias = table[curr_opcode]; + for (i = 2; i < NELEMS (alias->operands); ++i) + alias->operands[i - 1] = alias->operands[i]; + alias->operands[NELEMS (alias->operands) - 1] = IA64_OPND_NIL; + --alias->num_outputs; + alias->flags |= PSEUDO; + add_opcode_entry (alias); + } + } +} + + +/* Program options. */ +#define OPTION_SRCDIR 200 + +struct option long_options[] = +{ + {"srcdir", required_argument, NULL, OPTION_SRCDIR}, + {"debug", no_argument, NULL, 'd'}, + {"version", no_argument, NULL, 'V'}, + {"help", no_argument, NULL, 'h'}, + {0, no_argument, NULL, 0} +}; + +static void +print_version (void) +{ + printf ("%s: version 1.0\n", program_name); + xexit (0); +} + +static void +usage (FILE * stream, int status) +{ + fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", + program_name); + xexit (status); +} + +int +main (int argc, char **argv) +{ + extern int chdir (char *); + char *srcdir = NULL; + int c; + + program_name = *argv; + xmalloc_set_program_name (program_name); + + while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) + switch (c) + { + case OPTION_SRCDIR: + srcdir = optarg; + break; + case 'V': + case 'v': + print_version (); + break; + case 'd': + debug = 1; + break; + case 'h': + case '?': + usage (stderr, 0); + default: + case 0: + break; + } + + if (optind != argc) + usage (stdout, 1); + + if (srcdir != NULL) + if (chdir (srcdir) != 0) + fail (_("unable to change directory to \"%s\", errno = %s\n"), + srcdir, strerror (errno)); + + load_insn_classes (); + load_dependencies (); + + shrink (ia64_opcodes_a); + shrink (ia64_opcodes_b); + shrink (ia64_opcodes_f); + shrink (ia64_opcodes_i); + shrink (ia64_opcodes_m); + shrink (ia64_opcodes_x); + shrink (ia64_opcodes_d); + + collapse_redundant_completers (); + + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + printf ("/* Copyright 2007 Free Software Foundation, Inc.\n\ +\n\ + This file is part of the GNU opcodes library.\n\ +\n\ + This library is free software; you can redistribute it and/or modify\n\ + it under the terms of the GNU General Public License as published by\n\ + the Free Software Foundation; either version 3, or (at your option)\n\ + any later version.\n\ +\n\ + It is distributed in the hope that it will be useful, but WITHOUT\n\ + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\ + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\ + License for more details.\n\ +\n\ + You should have received a copy of the GNU General Public License\n\ + along with this program; see the file COPYING. If not, write to the\n\ + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA\n\ + 02110-1301, USA. */\n"); + + print_string_table (); + print_dependency_table (); + print_completer_table (); + print_main_table (); + + generate_disassembler (); + + exit (0); +} diff --git a/external/gpl3/gdb/dist/opcodes/ia64-ic.tbl b/external/gpl3/gdb/dist/opcodes/ia64-ic.tbl new file mode 100644 index 000000000000..015a088901f9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-ic.tbl @@ -0,0 +1,257 @@ +Class; Events/Instructions +all; IC:predicatable-instructions, IC:unpredicatable-instructions +branches; IC:indirect-brs, IC:ip-rel-brs +cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e +chk-a; chk.a.clr, chk.a.nc +cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8, cmp8xchg16 +czx; czx1, czx2 +fcmp-s0; fcmp[Field(sf)==s0] +fcmp-s1; fcmp[Field(sf)==s1] +fcmp-s2; fcmp[Field(sf)==s2] +fcmp-s3; fcmp[Field(sf)==s3] +fetchadd; fetchadd4, fetchadd8 +fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub +fp-arith-s0; IC:fp-arith[Field(sf)==s0] +fp-arith-s1; IC:fp-arith[Field(sf)==s1] +fp-arith-s2; IC:fp-arith[Field(sf)==s2] +fp-arith-s3; IC:fp-arith[Field(sf)==s3] +fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma, xmpy +fpcmp-s0; fpcmp[Field(sf)==s0] +fpcmp-s1; fpcmp[Field(sf)==s1] +fpcmp-s2; fpcmp[Field(sf)==s2] +fpcmp-s3; fpcmp[Field(sf)==s3] +fr-readers; IC:fp-arith, IC:fp-non-arith, IC:mem-writers-fp, IC:pr-writers-fp, chk.s[Format in {M21}], getf +fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf +gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat +gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, clz, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, shrp4, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt +gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl +indirect-brp; brp[Format in {B7}] +indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret +invala-all; invala[Format in {M24}], invala.e +ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop +ld; ld1, ld2, ld4, ld8, ld8.fill, ld16 +ld-a; ld1.a, ld2.a, ld4.a, ld8.a +ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] +ld-c; IC:ld-c-nc, IC:ld-c-clr +ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq +ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq +ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc +ld-s; ld1.s, ld2.s, ld4.s, ld8.s +ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa +ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill +ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a +ldf-c; IC:ldf-c-nc, IC:ldf-c-clr +ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr +ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc +ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s +ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa +ldfp; ldfps, ldfpd, ldfp8 +ldfp-a; ldfps.a, ldfpd.a, ldfp8.a +ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr +ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr +ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc +ldfp-s; ldfps.s, ldfpd.s, ldfp8.s +ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa +lfetch-all; lfetch +lfetch-fault; lfetch[Field(lftype)==fault] +lfetch-nofault; lfetch[Field(lftype)==] +lfetch-postinc; lfetch[Format in {M14 M15}] +mem-readers; IC:mem-readers-fp, IC:mem-readers-int +mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c +mem-readers-fp; IC:ldf, IC:ldfp +mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld +mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa +mem-writers; IC:mem-writers-fp, IC:mem-writers-int +mem-writers-fp; IC:stf +mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st +mix; mix1, mix2, mix4 +mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop +mod-sched-brs-counted; br.cexit, br.cloop, br.ctop +mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM +mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] +mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] +mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] +mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG] +mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD] +mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] +mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG] +mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR] +mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) == FDR] +mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) == FIR] +mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] +mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR] +mov-from-AR-I; mov_ar[Format in {I28}] +mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] +mov-from-AR-IM; mov_ar[Format in {I28 M31}] +mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC] +mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC] +mov-from-AR-M; mov_ar[Format in {M31}] +mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] +mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] +mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] +mov-from-AR-RUC; IC:mov-from-AR-M[Field(ar3) == RUC] +mov-from-AR-rv; IC:none +mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) == SSD] +mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] +mov-from-BR; mov_br[Format in {I22}] +mov-from-CR; mov_cr[Format in {M33}] +mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV] +mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR] +mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI] +mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA] +mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA] +mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS] +mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA] +mov-from-CR-IIB; IC:mov-from-CR[Field(cr3) in {IIB0 IIB1}] +mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM] +mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP] +mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA] +mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR] +mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR] +mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR] +mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM] +mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV] +mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA] +mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR] +mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID] +mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] +mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV] +mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA] +mov-from-CR-rv; IC:none +mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR] +mov-from-IND; mov_indirect[Format in {M43}] +mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid] +mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr] +mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr] +mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr] +mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr] +mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc] +mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd] +mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr pkr pmc rr}] +mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr] +mov-from-interruption-CR; IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIB, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA +mov-from-PR; mov_pr[Format in {I25}] +mov-from-PSR; mov_psr[Format in {M36}] +mov-from-PSR-um; mov_um[Format in {M36}] +mov-ip; mov_ip[Format in {I25}] +mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I +mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] +mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] +mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] +mov-to-AR-CFLG; IC:mov-to-AR-M[Field(ar3) == CFLG] +mov-to-AR-CSD; IC:mov-to-AR-M[Field(ar3) == CSD] +mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] +mov-to-AR-EFLAG; IC:mov-to-AR-M[Field(ar3) == EFLAG] +mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR] +mov-to-AR-FDR; IC:mov-to-AR-M[Field(ar3) == FDR] +mov-to-AR-FIR; IC:mov-to-AR-M[Field(ar3) == FIR] +mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] +mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR] +mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] +mov-to-AR-I; mov_ar[Format in {I26 I27}] +mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] +mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] +mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC] +mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC] +mov-to-AR-M; mov_ar[Format in {M29 M30}] +mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] +mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] +mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-RUC; IC:mov-to-AR-M[Field(ar3) == RUC] +mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) == SSD] +mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] +mov-to-BR; mov_br[Format in {I21}] +mov-to-CR; mov_cr[Format in {M32}] +mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV] +mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR] +mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI] +mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA] +mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA] +mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS] +mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA] +mov-to-CR-IIB; IC:mov-to-CR[Field(cr3) in {IIB0 IIB1}] +mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM] +mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP] +mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA] +mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR] +mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR] +mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR] +mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM] +mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV] +mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA] +mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR] +mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID] +mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] +mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV] +mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA] +mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR] +mov-to-IND; mov_indirect[Format in {M42}] +mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid] +mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr] +mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr] +mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr] +mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr] +mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc] +mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd] +mov-to-IND-priv; IC:mov-to-IND +mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr] +mov-to-interruption-CR; IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIB, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA +mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg +mov-to-PR-allreg; mov_pr[Format in {I23}] +mov-to-PR-rotreg; mov_pr[Format in {I24}] +mov-to-PSR-l; mov_psr[Format in {M35}] +mov-to-PSR-um; mov_um[Format in {M35}] +mux; mux1, mux2 +non-access; fc, lfetch, IC:probe-all, tpa, tak +none; - +pack; pack2, pack4 +padd; padd1, padd2, padd4 +pavg; pavg1, pavg2 +pavgsub; pavgsub1, pavgsub2 +pcmp; pcmp1, pcmp2, pcmp4 +pmax; pmax1, pmax2 +pmin; pmin1, pmin2 +pmpy; pmpy2 +pmpyshr; pmpyshr2 +pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-gen-writers-fp; fclass, fcmp +pr-gen-writers-int; cmp, cmp4, tbit, tf, tnat +pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] +pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] +pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, hint.b, nop.b, IC:ReservedBQP +pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, clz, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, shrp4, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, tf, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt +pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11 +pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11 +pr-writers; IC:pr-writers-int, IC:pr-writers-fp +pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp +pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-writers, IC:pr-or-writers +predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br, IC:pr-readers-nobr-nomovpr +priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa, vmsw +probe-all; IC:probe-fault, IC:probe-nofault +probe-fault; probe[Format in {M40}] +probe-nofault; probe[Format in {M38 M39}] +psad; psad1 +pshl; pshl2, pshl4 +pshladd; pshladd2 +pshr; pshr2, pshr4 +pshradd; pshradd2 +psub; psub1, psub2, psub4 +ReservedBQP; -+15 +ReservedQP; -+16 +rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi +rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi +st; st1, st2, st4, st8, st8.spill, st16 +st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] +stf; stfs, stfd, stfe, stf8, stf.spill +sxt; sxt1, sxt2, sxt4 +sys-mask-writers-partial; rsm, ssm +unpack; unpack1, unpack2, unpack4 +unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi, vmsw +user-mask-writers-partial; rum, sum +xchg; xchg1, xchg2, xchg4, xchg8 +zxt; zxt1, zxt2, zxt4 diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-a.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-a.c new file mode 100644 index 000000000000..848587201ca9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-a.c @@ -0,0 +1,419 @@ +/* ia64-opc-a.c -- IA-64 `A' opcode table. + Copyright 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define A IA64_TYPE_A, 1 +#define A2 IA64_TYPE_A, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ + (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ + (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) +#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) +#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mImm14 bImm14 (-1) +#define mR3a bR3a (-1) +#define mR3b bR3b (-1) +#define mTa bTa (-1) +#define mTb bTb (-1) +#define mVe bVe (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX4 bX4 (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) +#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ + (mOp | mX2a | mVe) +#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ + (mOp | mX2a | mVe | mR3a) +#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ + (mOp | mX2a | mVe | mImm14) +#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ + (mOp | mX2a | mVe | mX4) +#define OpX2aVeX4X2b(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ + (mOp | mX2a | mVe | mX4 | mX2b) +#define OpX2TbTaC(a,b,c,d,e) \ + (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ + (mOp | mX2 | mTb | mTa | mC) +#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ + (mOp | mX2 | mTa | mC) +#define OpX2aZaZbX4(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ + (mOp | mX2a | mZa | mZb | mX4) +#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ + (mOp | mX2a | mZa | mZb | mX4 | mX2b) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_a[] = + { + /* A-type instruction encodings (sorted according to major opcode). */ + + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY}, + /* A mov immediate pseudo for adds was deleted. It failed for immediate + operands requiring relocs, e.g. @pltoff(a). */ + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY}, + + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL}, + {"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY}, + + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef A +#undef A2 +#undef bC +#undef bImm14 +#undef bR3a +#undef bR3b +#undef bTa +#undef bTb +#undef bVe +#undef bX +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX4 +#undef bZa +#undef bZb +#undef mC +#undef mImm14 +#undef mR3a +#undef mR3b +#undef mTa +#undef mTb +#undef mVe +#undef mX +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX4 +#undef mZa +#undef mZb +#undef OpR3a +#undef OpR3b +#undef OpX2aVe +#undef OpX2aVeImm14 +#undef OpX2aVeX4 +#undef OpX2aVeX4X2b +#undef OpX2TbTaC +#undef OpX2TaC +#undef OpX2aZaZbX4 +#undef OpX2aZaZbX4X2b +#undef EMPTY diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-b.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-b.c new file mode 100644 index 000000000000..a00260ed2d3c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-b.c @@ -0,0 +1,512 @@ +/* ia64-opc-b.c -- IA-64 `B' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define B0 IA64_TYPE_B, 0 +#define B IA64_TYPE_B, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mIh bIh (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mWha bWha (-1) +#define mWhb bWhb (-1) +#define mWhc bWhc (-1) +#define mX6 bX6 (-1) + +#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpPaWhcD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) +#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD) +#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) +#define OpIhWhb(a,b,c) \ + (bOp (a) | bIh (b) | bWhb (c)), \ + (mOp | mIh | mWhb) +#define OpX6IhWhb(a,b,c,d) \ + (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ + (mOp | mX6 | mIh | mWhb) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_b[] = + { + /* B-type instruction encodings (sorted according to major opcode) */ + +#define BR(a,b) \ + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY +#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUDO, 0, NULL +#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, 0, NULL + {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, + {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, + {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, + {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, + {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.sptk", BRP (0x20, 0, 0, 0, 0)}, + {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, + {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.spnt", BRP (0x20, 0, 0, 1, 0)}, + {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, + {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.dptk", BRP (0x20, 0, 0, 2, 0)}, + {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, + {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.dpnt", BRP (0x20, 0, 0, 3, 0)}, + {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, + {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, + {"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)}, + {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, + {"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)}, + {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, + {"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)}, + {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, + {"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)}, + {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, + {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, + {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, + {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, + {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, + {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, + {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, + {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, + {"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)}, + {"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)}, + {"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)}, + {"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)}, + {"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)}, + {"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)}, + {"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)}, + {"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)}, + {"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)}, + {"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)}, + {"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)}, + {"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)}, + {"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)}, + {"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)}, +#undef BR +#undef BRP +#undef BRT + + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, 0, NULL}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL}, + {"vmsw.0", B0, OpX6 (0, 0x18), {0, }, NO_PRED | PRIV, 0, NULL}, + {"vmsw.1", B0, OpX6 (0, 0x19), {0, }, NO_PRED | PRIV, 0, NULL}, + + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY}, + + {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY}, + +#define BRP(a,b,c) \ + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL + {"brp.sptk", BRP (0x10, 0, 0)}, + {"brp.dptk", BRP (0x10, 0, 2)}, + {"brp.sptk.imp", BRP (0x10, 1, 0)}, + {"brp.dptk.imp", BRP (0x10, 1, 2)}, + {"brp.ret.sptk", BRP (0x11, 0, 0)}, + {"brp.ret.dptk", BRP (0x11, 0, 2)}, + {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, + {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, +#undef BRP + + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY}, + {"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY}, + +#define BR(a,b) \ + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY +#define BRP(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL + {"br.cond.sptk.few", BR (0, 0, 0)}, + {"br.cond.sptk", BRP (0, 0, 0)}, + {"br.cond.sptk.few.clr", BR (0, 0, 1)}, + {"br.cond.sptk.clr", BRP (0, 0, 1)}, + {"br.cond.spnt.few", BR (0, 1, 0)}, + {"br.cond.spnt", BRP (0, 1, 0)}, + {"br.cond.spnt.few.clr", BR (0, 1, 1)}, + {"br.cond.spnt.clr", BRP (0, 1, 1)}, + {"br.cond.dptk.few", BR (0, 2, 0)}, + {"br.cond.dptk", BRP (0, 2, 0)}, + {"br.cond.dptk.few.clr", BR (0, 2, 1)}, + {"br.cond.dptk.clr", BRP (0, 2, 1)}, + {"br.cond.dpnt.few", BR (0, 3, 0)}, + {"br.cond.dpnt", BRP (0, 3, 0)}, + {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, + {"br.cond.dpnt.clr", BRP (0, 3, 1)}, + {"br.cond.sptk.many", BR (1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (1, 0, 1)}, + {"br.cond.spnt.many", BR (1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (1, 1, 1)}, + {"br.cond.dptk.many", BR (1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (1, 2, 1)}, + {"br.cond.dpnt.many", BR (1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, + {"br.sptk.few", BR (0, 0, 0)}, + {"br.sptk", BRP (0, 0, 0)}, + {"br.sptk.few.clr", BR (0, 0, 1)}, + {"br.sptk.clr", BRP (0, 0, 1)}, + {"br.spnt.few", BR (0, 1, 0)}, + {"br.spnt", BRP (0, 1, 0)}, + {"br.spnt.few.clr", BR (0, 1, 1)}, + {"br.spnt.clr", BRP (0, 1, 1)}, + {"br.dptk.few", BR (0, 2, 0)}, + {"br.dptk", BRP (0, 2, 0)}, + {"br.dptk.few.clr", BR (0, 2, 1)}, + {"br.dptk.clr", BRP (0, 2, 1)}, + {"br.dpnt.few", BR (0, 3, 0)}, + {"br.dpnt", BRP (0, 3, 0)}, + {"br.dpnt.few.clr", BR (0, 3, 1)}, + {"br.dpnt.clr", BRP (0, 3, 1)}, + {"br.sptk.many", BR (1, 0, 0)}, + {"br.sptk.many.clr", BR (1, 0, 1)}, + {"br.spnt.many", BR (1, 1, 0)}, + {"br.spnt.many.clr", BR (1, 1, 1)}, + {"br.dptk.many", BR (1, 2, 0)}, + {"br.dptk.many.clr", BR (1, 2, 1)}, + {"br.dpnt.many", BR (1, 3, 0)}, + {"br.dpnt.many.clr", BR (1, 3, 1)}, +#undef BR +#undef BRP + +#define BR(a,b,c,d, e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL + {"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL +#define BRT(a,b,c,d,e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL + {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, + {"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)}, + {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, + {"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)}, + {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, + {"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)}, + {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, + {"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)}, + {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, + {"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)}, + {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, + {"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)}, + {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, + {"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)}, + {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, + {"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)}, + {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, + {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, + {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, + {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, + {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, + {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, + {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, + {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, + {"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)}, + {"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)}, + {"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)}, + {"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)}, + {"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)}, + {"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)}, + {"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)}, + {"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)}, + {"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)}, + {"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)}, + {"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)}, + {"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)}, + {"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)}, + {"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)}, + {"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)}, + {"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)}, +#undef BR +#undef BRT + + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPTY}, + + /* Branch predict. */ +#define BRP(a,b) \ + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL + {"brp.sptk", BRP (0, 0)}, + {"brp.loop", BRP (0, 1)}, + {"brp.dptk", BRP (0, 2)}, + {"brp.exit", BRP (0, 3)}, + {"brp.sptk.imp", BRP (1, 0)}, + {"brp.loop.imp", BRP (1, 1)}, + {"brp.dptk.imp", BRP (1, 2)}, + {"brp.exit.imp", BRP (1, 3)}, +#undef BRP + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef B0 +#undef B +#undef bBtype +#undef bD +#undef bIh +#undef bPa +#undef bPr +#undef bWha +#undef bWhb +#undef bWhc +#undef bX6 +#undef mBtype +#undef mD +#undef mIh +#undef mPa +#undef mPr +#undef mWha +#undef mWhb +#undef mWhc +#undef mX6 +#undef OpX6 +#undef OpPaWhaD +#undef OpPaWhcD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr +#undef OpX6BtypePaWhaD +#undef OpX6BtypePaWhaDPr +#undef OpIhWhb +#undef OpX6IhWhb +#undef EMPTY diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-d.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-d.c new file mode 100644 index 000000000000..c11c34843b5d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-d.c @@ -0,0 +1,35 @@ +/* ia64-opc-d.c -- IA-64 `D' opcode table. + Copyright 1998, 1999, 2000, 2001, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +struct ia64_opcode ia64_opcodes_d[] = + { + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}, 0, 0, NULL}, + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL}, + {"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-f.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-f.c new file mode 100644 index 000000000000..474a1c8a2ac1 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-f.c @@ -0,0 +1,657 @@ +/* ia64-opc-f.c -- IA-64 `F' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define f0 IA64_TYPE_F, 0 +#define f IA64_TYPE_F, 1 +#define f2 IA64_TYPE_F, 2 + +#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) +#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) +#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) + +#define mF2 bF2 (-1) +#define mF4 bF4 (-1) +#define mQ bQ (-1) +#define mRa bRa (-1) +#define mRb bRb (-1) +#define mSf bSf (-1) +#define mTa bTa (-1) +#define mXa bXa (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX6 bX6 (-1) +#define mY bY (-1) + +#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) +#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) +#define OpXaSfF2(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) +#define OpXaSfF4(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) +#define OpXaSfF2F4(a,b,c,d,e) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ + (mOp | mXa | mSf | mF2 | mF4) +#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) +#define OpXaX2F2(a,b,c,d) \ + (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) +#define OpRaRbTaSf(a,b,c,d,e) \ + (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ + (mOp | mRa | mRb | mTa | mSf) +#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) +#define OpXbQSf(a,b,c,d) \ + (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) +#define OpXbX6(a,b,c) \ + (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6Y(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) +#define OpXbX6F2(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) +#define OpXbX6Sf(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_f[] = + { + /* F-type instruction encodings (sorted according to major opcode). */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, NULL}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, + {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, + {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, + + /* pseudo-ops of the above */ + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, + + /* note: fnorm and fcvt.xuf have identical encodings! */ + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef f0 +#undef f +#undef f2 +#undef bF2 +#undef bF4 +#undef bQ +#undef bRa +#undef bRb +#undef bSf +#undef bTa +#undef bXa +#undef bXb +#undef bX2 +#undef bX6 +#undef mF2 +#undef mF4 +#undef mQ +#undef mRa +#undef mRb +#undef mSf +#undef mTa +#undef mXa +#undef mXb +#undef mX2 +#undef mX6 +#undef OpXa +#undef OpXaSf +#undef OpXaSfF2 +#undef OpXaSfF4 +#undef OpXaSfF2F4 +#undef OpXaX2 +#undef OpRaRbTaSf +#undef OpTa +#undef OpXbQSf +#undef OpXbX6 +#undef OpXbX6F2 +#undef OpXbX6Sf +#undef EMPTY diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-i.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-i.c new file mode 100644 index 000000000000..1db6f66c9265 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-i.c @@ -0,0 +1,338 @@ +/* ia64-opc-i.c -- IA-64 `I' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define I0 IA64_TYPE_I, 0 +#define I IA64_TYPE_I, 1 +#define I2 IA64_TYPE_I, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) +#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) +#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) +#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mIh bIh (-1) +#define mTa bTa (-1) +#define mTag13 bTag13 (-1) +#define mTb bTb (-1) +#define mVc bVc (-1) +#define mVe bVe (-1) +#define mWh bWh (-1) +#define mX bX (-1) +#define mXb bXb (-1) +#define mXc bXc (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX2c bX2c (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mYa bYa (-1) +#define mYb bYb (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b) +#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) +#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) +#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ + (mOp | mX2 | mX | mYa) +#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ + (mOp | mX2 | mX | mYb) +#define OpX2TaTbYaC(a,b,c,d,e,f) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ + (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \ + (mOp | mX2 | mTa | mTb | mYa | mXc | mC) +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ + (mOp | mX3 | mX6 | mYb) +#define OpX3XbIhWh(a,b,c,d,e) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ + (mOp | mX3 | mXb | mIh | mWh) +#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ + (mOp | mX3 | mXb | mIh | mWh | mTag13) + +#define FULL17 ((ia64_insn)0x10ff001fc0LL) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_i[] = + { + /* I-type instruction encodings (sorted according to major opcode). */ + + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, + {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, + {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, + + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL}, +#define MOV(a,b,c,d) \ + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY + {"mov.sptk", MOV (7, 0, 0, 0)}, + {"mov.sptk.imp", MOV (7, 0, 1, 0)}, + {"mov", MOV (7, 0, 0, 1)}, + {"mov.imp", MOV (7, 0, 1, 1)}, + {"mov.dptk", MOV (7, 0, 0, 2)}, + {"mov.dptk.imp", MOV (7, 0, 1, 2)}, + {"mov.ret.sptk", MOV (7, 1, 0, 0)}, + {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, + {"mov.ret", MOV (7, 1, 0, 1)}, + {"mov.ret.imp", MOV (7, 1, 1, 1)}, + {"mov.ret.dptk", MOV (7, 1, 0, 2)}, + {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, +#undef MOV + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, + /* Don't remove one of the seemingly redundant FULL17-s. */ + {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY}, + + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY}, + + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY}, + + {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY}, + + {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY}, + + {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, +#define TF(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY +#define TFCM(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL + {"tf.z", TF (0, 0, 0)}, + {"tf.nz", TFCM (0, 0, 0)}, + {"tf.z.unc", TF (0, 0, 1)}, + {"tf.nz.unc", TFCM (0, 0, 1)}, + {"tf.z.and", TF (0, 1, 0)}, + {"tf.nz.andcm", TFCM (0, 1, 0)}, + {"tf.nz.and", TF (0, 1, 1)}, + {"tf.z.andcm", TFCM (0, 1, 1)}, + {"tf.z.or", TF (1, 0, 0)}, + {"tf.nz.orcm", TFCM (1, 0, 0)}, + {"tf.nz.or", TF (1, 0, 1)}, + {"tf.z.orcm", TFCM (1, 0, 1)}, + {"tf.z.or.andcm", TF (1, 1, 0)}, + {"tf.nz.and.orcm", TFCM (1, 1, 0)}, + {"tf.nz.or.andcm", TF (1, 1, 1)}, + {"tf.z.and.orcm", TFCM (1, 1, 1)}, +#undef TF +#undef TFCM +#define TBIT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY +#define TBITCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL + {"tbit.z", TBIT (0, 0, 0, 0)}, + {"tbit.nz", TBITCM (0, 0, 0, 0)}, + {"tbit.z.unc", TBIT (0, 0, 0, 1)}, + {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, + {"tbit.z.and", TBIT (0, 1, 0, 0)}, + {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, + {"tbit.nz.and", TBIT (0, 1, 0, 1)}, + {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, + {"tbit.z.or", TBIT (1, 0, 0, 0)}, + {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, + {"tbit.nz.or", TBIT (1, 0, 0, 1)}, + {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, + {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, + {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, + {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, + {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, +#undef TBIT +#undef TBITCM +#define TNAT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY +#define TNATCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL + {"tnat.z", TNAT (0, 0, 1, 0)}, + {"tnat.nz", TNATCM (0, 0, 1, 0)}, + {"tnat.z.unc", TNAT (0, 0, 1, 1)}, + {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, + {"tnat.z.and", TNAT (0, 1, 1, 0)}, + {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, + {"tnat.nz.and", TNAT (0, 1, 1, 1)}, + {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, + {"tnat.z.or", TNAT (1, 0, 1, 0)}, + {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, + {"tnat.nz.or", TNAT (1, 0, 1, 1)}, + {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, + {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, + {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, + {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, + {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, +#undef TNAT +#undef TNATCM + + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef I0 +#undef I +#undef I2 +#undef L +#undef bC +#undef bIh +#undef bTa +#undef bTag13 +#undef bTb +#undef bVc +#undef bVe +#undef bWh +#undef bX +#undef bXb +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX2c +#undef bX3 +#undef bX6 +#undef bY +#undef bZa +#undef bZb +#undef mC +#undef mIh +#undef mTa +#undef mTag13 +#undef mTb +#undef mVc +#undef mVe +#undef mWh +#undef mX +#undef mXb +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX2c +#undef mX3 +#undef mX6 +#undef mY +#undef mZa +#undef mZb +#undef OpZaZbVeX2aX2b +#undef OpZaZbVeX2aX2bX2c +#undef OpX2X +#undef OpX2XYa +#undef OpX2XYb +#undef OpX2TaTbYaC +#undef OpX3 +#undef OpX3X6 +#undef OpX3XbIhWh +#undef OpX3XbIhWhTag13 +#undef EMPTY diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-m.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-m.c new file mode 100644 index 000000000000..4764c711e616 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-m.c @@ -0,0 +1,1119 @@ +/* ia64-opc-m.c -- IA-64 `M' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +#define M0 IA64_TYPE_M, 0 +#define M IA64_TYPE_M, 1 +#define M2 IA64_TYPE_M, 2 + +/* instruction bit fields: */ +#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) +#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) +#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */ +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) + +#define mM bM (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX3 bX3 (-1) +#define mX4 bX4 (-1) +#define mX6a bX6a (-1) +#define mX6b bX6b (-1) +#define mX7 bX7 (-1) +#define mY bY (-1) +#define mHint bHint (-1) + +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ + (mOp | mX3 | mX6b) +#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \ + (mOp | mX3 | mX6b | mX7) +#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ + (mOp | mX3 | mX4) +#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ + (mOp | mX3 | mX4 | mX2) +#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \ + (mOp | mX3 | mX4 | mX2 | mY) +#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ + (mOp | mX6a | mHint) +#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ + (mOp | mX | mX6a | mHint) +#define OpMXX6a(a,b,c,d) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) +#define OpMXX6aHint(a,b,c,d,e) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ + (mOp | mM | mX | mX6a | mHint) + +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + +struct ia64_opcode ia64_opcodes_m[] = + { + /* M-type instruction encodings (sorted according to major opcode). */ + + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, + + {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY}, + + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY}, + {"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY}, + {"hint.m", M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY}, + + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL}, + + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL}, + + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL}, + {"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MOD_RRBS, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV, 0, NULL}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV, 0, NULL}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV, 0, NULL}, + + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}, EMPTY}, + + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL}, + + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}, EMPTY}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}, EMPTY}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV, 0, NULL}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV, 0, NULL}, + + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY}, + + {"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY}, + {"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL}, + + /* integer load */ + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}, EMPTY}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}, EMPTY}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}, EMPTY}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}, EMPTY}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}, EMPTY}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}, EMPTY}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}, EMPTY}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}, EMPTY}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY}, + {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16", M, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nt1", M, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nta", M, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}, EMPTY}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}, EMPTY}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}, EMPTY}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}, EMPTY}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}, EMPTY}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}, EMPTY}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}, EMPTY}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}, EMPTY}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}, EMPTY}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}, EMPTY}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}, EMPTY}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}, EMPTY}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}, EMPTY}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}, EMPTY}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}, EMPTY}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}, EMPTY}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}, EMPTY}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}, EMPTY}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}, EMPTY}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}, EMPTY}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}, EMPTY}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}, EMPTY}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}, EMPTY}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}, EMPTY}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}, EMPTY}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}, EMPTY}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}, EMPTY}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}, EMPTY}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}, EMPTY}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}, EMPTY}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}, EMPTY}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}, EMPTY}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}, EMPTY}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}, EMPTY}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}, EMPTY}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}, EMPTY}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}, EMPTY}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}, EMPTY}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}, EMPTY}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}, EMPTY}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}, EMPTY}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}, EMPTY}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}, EMPTY}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}, EMPTY}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}, EMPTY}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}, EMPTY}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}, EMPTY}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}, EMPTY}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}, EMPTY}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}, EMPTY}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}, EMPTY}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}, EMPTY}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}, EMPTY}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}, EMPTY}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY}, + {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq", M, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, MR3}, PSEUDO, 0, NULL}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}, EMPTY}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}, EMPTY}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}, EMPTY}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}, EMPTY}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EMPTY}, + + /* Pseudo-op that generates ldxmov relocation. */ + {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0), + {R1, MR3, IA64_OPND_LDXMOV}, EMPTY}, + + /* Integer load w/increment by register. */ +#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL + {"ld1", LDINCREG (0x00, 0)}, + {"ld1.nt1", LDINCREG (0x00, 1)}, + {"ld1.nta", LDINCREG (0x00, 3)}, + {"ld2", LDINCREG (0x01, 0)}, + {"ld2.nt1", LDINCREG (0x01, 1)}, + {"ld2.nta", LDINCREG (0x01, 3)}, + {"ld4", LDINCREG (0x02, 0)}, + {"ld4.nt1", LDINCREG (0x02, 1)}, + {"ld4.nta", LDINCREG (0x02, 3)}, + {"ld8", LDINCREG (0x03, 0)}, + {"ld8.nt1", LDINCREG (0x03, 1)}, + {"ld8.nta", LDINCREG (0x03, 3)}, + {"ld1.s", LDINCREG (0x04, 0)}, + {"ld1.s.nt1", LDINCREG (0x04, 1)}, + {"ld1.s.nta", LDINCREG (0x04, 3)}, + {"ld2.s", LDINCREG (0x05, 0)}, + {"ld2.s.nt1", LDINCREG (0x05, 1)}, + {"ld2.s.nta", LDINCREG (0x05, 3)}, + {"ld4.s", LDINCREG (0x06, 0)}, + {"ld4.s.nt1", LDINCREG (0x06, 1)}, + {"ld4.s.nta", LDINCREG (0x06, 3)}, + {"ld8.s", LDINCREG (0x07, 0)}, + {"ld8.s.nt1", LDINCREG (0x07, 1)}, + {"ld8.s.nta", LDINCREG (0x07, 3)}, + {"ld1.a", LDINCREG (0x08, 0)}, + {"ld1.a.nt1", LDINCREG (0x08, 1)}, + {"ld1.a.nta", LDINCREG (0x08, 3)}, + {"ld2.a", LDINCREG (0x09, 0)}, + {"ld2.a.nt1", LDINCREG (0x09, 1)}, + {"ld2.a.nta", LDINCREG (0x09, 3)}, + {"ld4.a", LDINCREG (0x0a, 0)}, + {"ld4.a.nt1", LDINCREG (0x0a, 1)}, + {"ld4.a.nta", LDINCREG (0x0a, 3)}, + {"ld8.a", LDINCREG (0x0b, 0)}, + {"ld8.a.nt1", LDINCREG (0x0b, 1)}, + {"ld8.a.nta", LDINCREG (0x0b, 3)}, + {"ld1.sa", LDINCREG (0x0c, 0)}, + {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, + {"ld1.sa.nta", LDINCREG (0x0c, 3)}, + {"ld2.sa", LDINCREG (0x0d, 0)}, + {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, + {"ld2.sa.nta", LDINCREG (0x0d, 3)}, + {"ld4.sa", LDINCREG (0x0e, 0)}, + {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, + {"ld4.sa.nta", LDINCREG (0x0e, 3)}, + {"ld8.sa", LDINCREG (0x0f, 0)}, + {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, + {"ld8.sa.nta", LDINCREG (0x0f, 3)}, + {"ld1.bias", LDINCREG (0x10, 0)}, + {"ld1.bias.nt1", LDINCREG (0x10, 1)}, + {"ld1.bias.nta", LDINCREG (0x10, 3)}, + {"ld2.bias", LDINCREG (0x11, 0)}, + {"ld2.bias.nt1", LDINCREG (0x11, 1)}, + {"ld2.bias.nta", LDINCREG (0x11, 3)}, + {"ld4.bias", LDINCREG (0x12, 0)}, + {"ld4.bias.nt1", LDINCREG (0x12, 1)}, + {"ld4.bias.nta", LDINCREG (0x12, 3)}, + {"ld8.bias", LDINCREG (0x13, 0)}, + {"ld8.bias.nt1", LDINCREG (0x13, 1)}, + {"ld8.bias.nta", LDINCREG (0x13, 3)}, + {"ld1.acq", LDINCREG (0x14, 0)}, + {"ld1.acq.nt1", LDINCREG (0x14, 1)}, + {"ld1.acq.nta", LDINCREG (0x14, 3)}, + {"ld2.acq", LDINCREG (0x15, 0)}, + {"ld2.acq.nt1", LDINCREG (0x15, 1)}, + {"ld2.acq.nta", LDINCREG (0x15, 3)}, + {"ld4.acq", LDINCREG (0x16, 0)}, + {"ld4.acq.nt1", LDINCREG (0x16, 1)}, + {"ld4.acq.nta", LDINCREG (0x16, 3)}, + {"ld8.acq", LDINCREG (0x17, 0)}, + {"ld8.acq.nt1", LDINCREG (0x17, 1)}, + {"ld8.acq.nta", LDINCREG (0x17, 3)}, + {"ld8.fill", LDINCREG (0x1b, 0)}, + {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, + {"ld8.fill.nta", LDINCREG (0x1b, 3)}, + {"ld1.c.clr", LDINCREG (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, + {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, + {"ld2.c.clr", LDINCREG (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, + {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, + {"ld4.c.clr", LDINCREG (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, + {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, + {"ld8.c.clr", LDINCREG (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, + {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, + {"ld1.c.nc", LDINCREG (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, + {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, + {"ld2.c.nc", LDINCREG (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, + {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, + {"ld4.c.nc", LDINCREG (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, + {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, + {"ld8.c.nc", LDINCREG (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, + {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, + {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, + {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, + {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, +#undef LDINCREG + + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}, EMPTY}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}, EMPTY}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}, EMPTY}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}, EMPTY}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY}, + {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2}, PSEUDO, 0, NULL}, + {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2}, PSEUDO, 0, NULL}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}, EMPTY}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}, EMPTY}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY}, + {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2}, PSEUDO, 0, NULL}, + {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2}, PSEUDO, 0, NULL}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY}, + +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY +#define CMPXCHG_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL +#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY +#define CMPXCHG16_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL +#define CMPXCHG_acq 0 +#define CMPXCHG_rel 4 +#define CMPXCHG_1 0 +#define CMPXCHG_2 1 +#define CMPXCHG_4 2 +#define CMPXCHG_8 3 +#define CMPXCHGn(n, s) \ + {"cmpxchg"#n"."#s, CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ + {"cmpxchg"#n"."#s, CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ + {"cmpxchg"#n"."#s".nt1", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ + {"cmpxchg"#n"."#s".nt1", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ + {"cmpxchg"#n"."#s".nta", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 3)}, \ + {"cmpxchg"#n"."#s".nta", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 3)} +#define CMP8XCHG16(s) \ + {"cmp8xchg16."#s, CMPXCHG16 (0x20|CMPXCHG_##s, 0)}, \ + {"cmp8xchg16."#s, CMPXCHG16_P (0x20|CMPXCHG_##s, 0)}, \ + {"cmp8xchg16."#s".nt1", CMPXCHG16 (0x20|CMPXCHG_##s, 1)}, \ + {"cmp8xchg16."#s".nt1", CMPXCHG16_P (0x20|CMPXCHG_##s, 1)}, \ + {"cmp8xchg16."#s".nta", CMPXCHG16 (0x20|CMPXCHG_##s, 3)}, \ + {"cmp8xchg16."#s".nta", CMPXCHG16_P (0x20|CMPXCHG_##s, 3)} +#define CMPXCHG_ALL(s) CMPXCHGn(1, s), \ + CMPXCHGn(2, s), \ + CMPXCHGn(4, s), \ + CMPXCHGn(8, s), \ + CMP8XCHG16(s) + CMPXCHG_ALL(acq), + CMPXCHG_ALL(rel), +#undef CMPXCHG +#undef CMPXCHG_P +#undef CMPXCHG16 +#undef CMPXCHG16_P +#undef CMPXCHG_acq +#undef CMPXCHG_rel +#undef CMPXCHG_1 +#undef CMPXCHG_2 +#undef CMPXCHG_4 +#undef CMPXCHG_8 +#undef CMPXCHGn +#undef CMPXCHG16 +#undef CMPXCHG_ALL + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}, EMPTY}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}, EMPTY}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}, EMPTY}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}, EMPTY}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}, EMPTY}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}, EMPTY}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}, EMPTY}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}, EMPTY}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}, EMPTY}, + + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}, EMPTY}, + + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}, EMPTY}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}, EMPTY}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}, EMPTY}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}, EMPTY}, + + /* Integer load w/increment by immediate. */ +#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL + {"ld1", LDINCIMMED (0x00, 0)}, + {"ld1.nt1", LDINCIMMED (0x00, 1)}, + {"ld1.nta", LDINCIMMED (0x00, 3)}, + {"ld2", LDINCIMMED (0x01, 0)}, + {"ld2.nt1", LDINCIMMED (0x01, 1)}, + {"ld2.nta", LDINCIMMED (0x01, 3)}, + {"ld4", LDINCIMMED (0x02, 0)}, + {"ld4.nt1", LDINCIMMED (0x02, 1)}, + {"ld4.nta", LDINCIMMED (0x02, 3)}, + {"ld8", LDINCIMMED (0x03, 0)}, + {"ld8.nt1", LDINCIMMED (0x03, 1)}, + {"ld8.nta", LDINCIMMED (0x03, 3)}, + {"ld1.s", LDINCIMMED (0x04, 0)}, + {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, + {"ld1.s.nta", LDINCIMMED (0x04, 3)}, + {"ld2.s", LDINCIMMED (0x05, 0)}, + {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, + {"ld2.s.nta", LDINCIMMED (0x05, 3)}, + {"ld4.s", LDINCIMMED (0x06, 0)}, + {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, + {"ld4.s.nta", LDINCIMMED (0x06, 3)}, + {"ld8.s", LDINCIMMED (0x07, 0)}, + {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, + {"ld8.s.nta", LDINCIMMED (0x07, 3)}, + {"ld1.a", LDINCIMMED (0x08, 0)}, + {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, + {"ld1.a.nta", LDINCIMMED (0x08, 3)}, + {"ld2.a", LDINCIMMED (0x09, 0)}, + {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, + {"ld2.a.nta", LDINCIMMED (0x09, 3)}, + {"ld4.a", LDINCIMMED (0x0a, 0)}, + {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, + {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, + {"ld8.a", LDINCIMMED (0x0b, 0)}, + {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, + {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, + {"ld1.sa", LDINCIMMED (0x0c, 0)}, + {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, + {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, + {"ld2.sa", LDINCIMMED (0x0d, 0)}, + {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, + {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, + {"ld4.sa", LDINCIMMED (0x0e, 0)}, + {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, + {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, + {"ld8.sa", LDINCIMMED (0x0f, 0)}, + {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, + {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, + {"ld1.bias", LDINCIMMED (0x10, 0)}, + {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, + {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, + {"ld2.bias", LDINCIMMED (0x11, 0)}, + {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, + {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, + {"ld4.bias", LDINCIMMED (0x12, 0)}, + {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, + {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, + {"ld8.bias", LDINCIMMED (0x13, 0)}, + {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, + {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, + {"ld1.acq", LDINCIMMED (0x14, 0)}, + {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, + {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, + {"ld2.acq", LDINCIMMED (0x15, 0)}, + {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, + {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, + {"ld4.acq", LDINCIMMED (0x16, 0)}, + {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, + {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, + {"ld8.acq", LDINCIMMED (0x17, 0)}, + {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, + {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, + {"ld8.fill", LDINCIMMED (0x1b, 0)}, + {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, + {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, + {"ld1.c.clr", LDINCIMMED (0x20, 0)}, + {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, + {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, + {"ld2.c.clr", LDINCIMMED (0x21, 0)}, + {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, + {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, + {"ld4.c.clr", LDINCIMMED (0x22, 0)}, + {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, + {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, + {"ld8.c.clr", LDINCIMMED (0x23, 0)}, + {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, + {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, + {"ld1.c.nc", LDINCIMMED (0x24, 0)}, + {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, + {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, + {"ld2.c.nc", LDINCIMMED (0x25, 0)}, + {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, + {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, + {"ld4.c.nc", LDINCIMMED (0x26, 0)}, + {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, + {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, + {"ld8.c.nc", LDINCIMMED (0x27, 0)}, + {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, + {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, + {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, + {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, + {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, + {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, + {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, + {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, + {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, + {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, + {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, + {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, + {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, + {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, +#undef LDINCIMMED + + /* Store w/increment by immediate. */ +#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL + {"st1", STINCIMMED (0x30, 0)}, + {"st1.nta", STINCIMMED (0x30, 3)}, + {"st2", STINCIMMED (0x31, 0)}, + {"st2.nta", STINCIMMED (0x31, 3)}, + {"st4", STINCIMMED (0x32, 0)}, + {"st4.nta", STINCIMMED (0x32, 3)}, + {"st8", STINCIMMED (0x33, 0)}, + {"st8.nta", STINCIMMED (0x33, 3)}, + {"st1.rel", STINCIMMED (0x34, 0)}, + {"st1.rel.nta", STINCIMMED (0x34, 3)}, + {"st2.rel", STINCIMMED (0x35, 0)}, + {"st2.rel.nta", STINCIMMED (0x35, 3)}, + {"st4.rel", STINCIMMED (0x36, 0)}, + {"st4.rel.nta", STINCIMMED (0x36, 3)}, + {"st8.rel", STINCIMMED (0x37, 0)}, + {"st8.rel.nta", STINCIMMED (0x37, 3)}, + {"st8.spill", STINCIMMED (0x3b, 0)}, + {"st8.spill.nta", STINCIMMED (0x3b, 3)}, +#undef STINCIMMED + + /* Floating-point load. */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}, EMPTY}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}, EMPTY}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}, EMPTY}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}, EMPTY}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}, EMPTY}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}, EMPTY}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}, EMPTY}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}, EMPTY}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}, EMPTY}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}, EMPTY}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}, EMPTY}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}, EMPTY}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}, EMPTY}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}, EMPTY}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}, EMPTY}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}, EMPTY}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}, EMPTY}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}, EMPTY}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}, EMPTY}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}, EMPTY}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}, EMPTY}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}, EMPTY}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}, EMPTY}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}, EMPTY}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}, EMPTY}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}, EMPTY}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}, EMPTY}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}, EMPTY}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}, EMPTY}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}, EMPTY}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}, EMPTY}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}, EMPTY}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}, EMPTY}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}, EMPTY}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}, EMPTY}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}, EMPTY}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}, EMPTY}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}, EMPTY}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}, EMPTY}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}, EMPTY}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}, EMPTY}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}, EMPTY}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}, EMPTY}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}, EMPTY}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}, EMPTY}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}, EMPTY}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}, EMPTY}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}, EMPTY}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}, EMPTY}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}, EMPTY}, + + /* Floating-point load w/increment by register. */ +#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL + {"ldfs", FLDINCREG (0x02, 0)}, + {"ldfs.nt1", FLDINCREG (0x02, 1)}, + {"ldfs.nta", FLDINCREG (0x02, 3)}, + {"ldfd", FLDINCREG (0x03, 0)}, + {"ldfd.nt1", FLDINCREG (0x03, 1)}, + {"ldfd.nta", FLDINCREG (0x03, 3)}, + {"ldf8", FLDINCREG (0x01, 0)}, + {"ldf8.nt1", FLDINCREG (0x01, 1)}, + {"ldf8.nta", FLDINCREG (0x01, 3)}, + {"ldfe", FLDINCREG (0x00, 0)}, + {"ldfe.nt1", FLDINCREG (0x00, 1)}, + {"ldfe.nta", FLDINCREG (0x00, 3)}, + {"ldfs.s", FLDINCREG (0x06, 0)}, + {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, + {"ldfs.s.nta", FLDINCREG (0x06, 3)}, + {"ldfd.s", FLDINCREG (0x07, 0)}, + {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, + {"ldfd.s.nta", FLDINCREG (0x07, 3)}, + {"ldf8.s", FLDINCREG (0x05, 0)}, + {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, + {"ldf8.s.nta", FLDINCREG (0x05, 3)}, + {"ldfe.s", FLDINCREG (0x04, 0)}, + {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, + {"ldfe.s.nta", FLDINCREG (0x04, 3)}, + {"ldfs.a", FLDINCREG (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, + {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, + {"ldfd.a", FLDINCREG (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, + {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, + {"ldf8.a", FLDINCREG (0x09, 0)}, + {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, + {"ldf8.a.nta", FLDINCREG (0x09, 3)}, + {"ldfe.a", FLDINCREG (0x08, 0)}, + {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, + {"ldfe.a.nta", FLDINCREG (0x08, 3)}, + {"ldfs.sa", FLDINCREG (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, + {"ldfd.sa", FLDINCREG (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, + {"ldf8.sa", FLDINCREG (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, + {"ldfe.sa", FLDINCREG (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, + {"ldf.fill", FLDINCREG (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, + {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, + {"ldfs.c.clr", FLDINCREG (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, + {"ldfd.c.clr", FLDINCREG (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, + {"ldf8.c.clr", FLDINCREG (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, + {"ldfe.c.clr", FLDINCREG (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, + {"ldfs.c.nc", FLDINCREG (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, + {"ldfd.c.nc", FLDINCREG (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, + {"ldf8.c.nc", FLDINCREG (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, + {"ldfe.c.nc", FLDINCREG (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, +#undef FLDINCREG + + /* Floating-point store. */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}, EMPTY}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}, EMPTY}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}, EMPTY}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}, EMPTY}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}, EMPTY}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}, EMPTY}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}, EMPTY}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}, EMPTY}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}, EMPTY}, + + /* Floating-point load pair. */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}, EMPTY}, + + /* Floating-point load pair w/increment by immediate. */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL + {"ldfps", LD (0x02, 0, C8)}, + {"ldfps.nt1", LD (0x02, 1, C8)}, + {"ldfps.nta", LD (0x02, 3, C8)}, + {"ldfpd", LD (0x03, 0, C16)}, + {"ldfpd.nt1", LD (0x03, 1, C16)}, + {"ldfpd.nta", LD (0x03, 3, C16)}, + {"ldfp8", LD (0x01, 0, C16)}, + {"ldfp8.nt1", LD (0x01, 1, C16)}, + {"ldfp8.nta", LD (0x01, 3, C16)}, + {"ldfps.s", LD (0x06, 0, C8)}, + {"ldfps.s.nt1", LD (0x06, 1, C8)}, + {"ldfps.s.nta", LD (0x06, 3, C8)}, + {"ldfpd.s", LD (0x07, 0, C16)}, + {"ldfpd.s.nt1", LD (0x07, 1, C16)}, + {"ldfpd.s.nta", LD (0x07, 3, C16)}, + {"ldfp8.s", LD (0x05, 0, C16)}, + {"ldfp8.s.nt1", LD (0x05, 1, C16)}, + {"ldfp8.s.nta", LD (0x05, 3, C16)}, + {"ldfps.a", LD (0x0a, 0, C8)}, + {"ldfps.a.nt1", LD (0x0a, 1, C8)}, + {"ldfps.a.nta", LD (0x0a, 3, C8)}, + {"ldfpd.a", LD (0x0b, 0, C16)}, + {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, + {"ldfpd.a.nta", LD (0x0b, 3, C16)}, + {"ldfp8.a", LD (0x09, 0, C16)}, + {"ldfp8.a.nt1", LD (0x09, 1, C16)}, + {"ldfp8.a.nta", LD (0x09, 3, C16)}, + {"ldfps.sa", LD (0x0e, 0, C8)}, + {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, + {"ldfps.sa.nta", LD (0x0e, 3, C8)}, + {"ldfpd.sa", LD (0x0f, 0, C16)}, + {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, + {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, + {"ldfp8.sa", LD (0x0d, 0, C16)}, + {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, + {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, + {"ldfps.c.clr", LD (0x22, 0, C8)}, + {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, + {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, + {"ldfpd.c.clr", LD (0x23, 0, C16)}, + {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, + {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, + {"ldfp8.c.clr", LD (0x21, 0, C16)}, + {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, + {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, + {"ldfps.c.nc", LD (0x26, 0, C8)}, + {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, + {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, + {"ldfpd.c.nc", LD (0x27, 0, C16)}, + {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, + {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, + {"ldfp8.c.nc", LD (0x25, 0, C16)}, + {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, + {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, +#undef LD + + /* Line prefetch. */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}, EMPTY}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}, EMPTY}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}, EMPTY}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}, EMPTY}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}, EMPTY}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}, EMPTY}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}, EMPTY}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}, EMPTY}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}, EMPTY}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}, EMPTY}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}, EMPTY}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}, EMPTY}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}, EMPTY}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}, EMPTY}, + + /* Line prefetch w/increment by register. */ +#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL + {"lfetch", LFETCHINCREG (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, + {"lfetch.nta", LFETCHINCREG (0x2c, 3)}, + {"lfetch.excl", LFETCHINCREG (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)}, + {"lfetch.fault", LFETCHINCREG (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, +#undef LFETCHINCREG + + /* Semaphore operations. */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}, EMPTY}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}, EMPTY}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}, EMPTY}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}, EMPTY}, + + /* Floating-point load w/increment by immediate. */ +#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL + {"ldfs", FLDINCIMMED (0x02, 0)}, + {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, + {"ldfs.nta", FLDINCIMMED (0x02, 3)}, + {"ldfd", FLDINCIMMED (0x03, 0)}, + {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, + {"ldfd.nta", FLDINCIMMED (0x03, 3)}, + {"ldf8", FLDINCIMMED (0x01, 0)}, + {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, + {"ldf8.nta", FLDINCIMMED (0x01, 3)}, + {"ldfe", FLDINCIMMED (0x00, 0)}, + {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, + {"ldfe.nta", FLDINCIMMED (0x00, 3)}, + {"ldfs.s", FLDINCIMMED (0x06, 0)}, + {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, + {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, + {"ldfd.s", FLDINCIMMED (0x07, 0)}, + {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, + {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, + {"ldf8.s", FLDINCIMMED (0x05, 0)}, + {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, + {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, + {"ldfe.s", FLDINCIMMED (0x04, 0)}, + {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, + {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, + {"ldfs.a", FLDINCIMMED (0x0a, 0)}, + {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, + {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, + {"ldfd.a", FLDINCIMMED (0x0b, 0)}, + {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, + {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, + {"ldf8.a", FLDINCIMMED (0x09, 0)}, + {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, + {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, + {"ldfe.a", FLDINCIMMED (0x08, 0)}, + {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, + {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, + {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, + {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, + {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, + {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, + {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, + {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, + {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, + {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, + {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, + {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, + {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, + {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, + {"ldf.fill", FLDINCIMMED (0x1b, 0)}, + {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, + {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, + {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, + {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, + {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, + {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, + {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, + {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, + {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, + {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, + {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, + {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, + {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, + {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, + {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, + {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, + {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, + {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, + {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, + {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, + {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, + {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, + {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, + {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, + {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, + {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, +#undef FLDINCIMMED + + /* Floating-point store w/increment by immediate. */ +#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL + {"stfs", FSTINCIMMED (0x32, 0)}, + {"stfs.nta", FSTINCIMMED (0x32, 3)}, + {"stfd", FSTINCIMMED (0x33, 0)}, + {"stfd.nta", FSTINCIMMED (0x33, 3)}, + {"stf8", FSTINCIMMED (0x31, 0)}, + {"stf8.nta", FSTINCIMMED (0x31, 3)}, + {"stfe", FSTINCIMMED (0x30, 0)}, + {"stfe.nta", FSTINCIMMED (0x30, 3)}, + {"stf.spill", FSTINCIMMED (0x3b, 0)}, + {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, +#undef FSTINCIMMED + + /* Line prefetch w/increment by immediate. */ +#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL + {"lfetch", LFETCHINCIMMED (0x2c, 0)}, + {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, + {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, + {"lfetch.nta", LFETCHINCIMMED (0x2c, 3)}, + {"lfetch.excl", LFETCHINCIMMED (0x2d, 0)}, + {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)}, + {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)}, + {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)}, + {"lfetch.fault", LFETCHINCIMMED (0x2e, 0)}, + {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)}, + {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)}, + {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)}, + {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)}, + {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)}, + {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)}, + {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, +#undef LFETCHINCIMMED + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef M0 +#undef M +#undef M2 +#undef bM +#undef bX +#undef bX2 +#undef bX3 +#undef bX4 +#undef bX6a +#undef bX6b +#undef bHint +#undef mM +#undef mX +#undef mX2 +#undef mX3 +#undef mX4 +#undef mX6a +#undef mX6b +#undef mHint +#undef OpX3 +#undef OpX3X6b +#undef OpX3X4 +#undef OpX3X4X2 +#undef OpX6aHint +#undef OpXX6aHint +#undef OpMXX6a +#undef OpMXX6aHint +#undef EMPTY diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc-x.c b/external/gpl3/gdb/dist/opcodes/ia64-opc-x.c new file mode 100644 index 000000000000..44f4e5066a62 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc-x.c @@ -0,0 +1,188 @@ +/* ia64-opc-x.c -- IA-64 `X' opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. + Contributed by Timothy Wall + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ia64-opc.h" + +/* Identify the specific X-unit type. */ +#define X0 IA64_TYPE_X, 0 +#define X IA64_TYPE_X, 1 + +/* Instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mVc bVc (-1) +#define mWha bWha (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mY bY (-1) + +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \ + (mOp | mX3 | mX6 | mY) +#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) + +struct ia64_opcode ia64_opcodes_x[] = + { + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, + {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, + {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL}, +#define BRL(a,b) \ + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL + {"brl.few", BRL (0, 0)}, + {"brl", BRL (0, 0)}, + {"brl.few.clr", BRL (0, 1)}, + {"brl.clr", BRL (0, 1)}, + {"brl.many", BRL (1, 0)}, + {"brl.many.clr", BRL (1, 1)}, +#undef BRL +#define BRL(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL +#define BRLP(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL + {"brl.cond.sptk.few", BRL (0, 0, 0)}, + {"brl.cond.sptk", BRLP (0, 0, 0)}, + {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.cond.sptk.clr", BRLP (0, 0, 1)}, + {"brl.cond.spnt.few", BRL (0, 1, 0)}, + {"brl.cond.spnt", BRLP (0, 1, 0)}, + {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.cond.spnt.clr", BRLP (0, 1, 1)}, + {"brl.cond.dptk.few", BRL (0, 2, 0)}, + {"brl.cond.dptk", BRLP (0, 2, 0)}, + {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.cond.dptk.clr", BRLP (0, 2, 1)}, + {"brl.cond.dpnt.few", BRL (0, 3, 0)}, + {"brl.cond.dpnt", BRLP (0, 3, 0)}, + {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.cond.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.cond.sptk.many", BRL (1, 0, 0)}, + {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.cond.spnt.many", BRL (1, 1, 0)}, + {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.cond.dptk.many", BRL (1, 2, 0)}, + {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.cond.dpnt.many", BRL (1, 3, 0)}, + {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, + {"brl.sptk.few", BRL (0, 0, 0)}, + {"brl.sptk", BRLP (0, 0, 0)}, + {"brl.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.sptk.clr", BRLP (0, 0, 1)}, + {"brl.spnt.few", BRL (0, 1, 0)}, + {"brl.spnt", BRLP (0, 1, 0)}, + {"brl.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.spnt.clr", BRLP (0, 1, 1)}, + {"brl.dptk.few", BRL (0, 2, 0)}, + {"brl.dptk", BRLP (0, 2, 0)}, + {"brl.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.dptk.clr", BRLP (0, 2, 1)}, + {"brl.dpnt.few", BRL (0, 3, 0)}, + {"brl.dpnt", BRLP (0, 3, 0)}, + {"brl.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.sptk.many", BRL (1, 0, 0)}, + {"brl.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.spnt.many", BRL (1, 1, 0)}, + {"brl.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.dptk.many", BRL (1, 2, 0)}, + {"brl.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.dpnt.many", BRL (1, 3, 0)}, + {"brl.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#undef BRLP +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL +#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NULL + {"brl.call.sptk.few", BRL (0, 0, 0)}, + {"brl.call.sptk", BRLP (0, 0, 0)}, + {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.call.sptk.clr", BRLP (0, 0, 1)}, + {"brl.call.spnt.few", BRL (0, 1, 0)}, + {"brl.call.spnt", BRLP (0, 1, 0)}, + {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.call.spnt.clr", BRLP (0, 1, 1)}, + {"brl.call.dptk.few", BRL (0, 2, 0)}, + {"brl.call.dptk", BRLP (0, 2, 0)}, + {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.call.dptk.clr", BRLP (0, 2, 1)}, + {"brl.call.dpnt.few", BRL (0, 3, 0)}, + {"brl.call.dpnt", BRLP (0, 3, 0)}, + {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.call.dpnt.clr", BRLP (0, 3, 1)}, + {"brl.call.sptk.many", BRL (1, 0, 0)}, + {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.call.spnt.many", BRL (1, 1, 0)}, + {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.call.dptk.many", BRL (1, 2, 0)}, + {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.call.dpnt.many", BRL (1, 3, 0)}, + {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#undef BRLP + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} + }; + +#undef X0 +#undef X + +#undef bBtype +#undef bD +#undef bPa +#undef bPr +#undef bVc +#undef bWha +#undef bX3 +#undef bX6 + +#undef mBtype +#undef mD +#undef mPa +#undef mPr +#undef mVc +#undef mWha +#undef mX3 +#undef mX6 + +#undef OpX3X6 +#undef OpVc +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc.c b/external/gpl3/gdb/dist/opcodes/ia64-opc.c new file mode 100644 index 000000000000..539fa9b2d765 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc.c @@ -0,0 +1,730 @@ +/* ia64-opc.c -- Functions to access the compacted opcode table + Copyright 1999, 2000, 2001, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. + Written by Bob Manson of Cygnus Solutions, + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ansidecl.h" +#include "sysdep.h" +#include "libiberty.h" +#include "ia64-asmtab.h" +#include "ia64-asmtab.c" + +static void get_opc_prefix (const char **, char *); +static short int find_string_ent (const char *); +static short int find_main_ent (short int); +static short int find_completer (short int, short int, const char *); +static ia64_insn apply_completer (ia64_insn, int); +static int extract_op_bits (int, int, int); +static int extract_op (int, int *, unsigned int *); +static int opcode_verify (ia64_insn, int, enum ia64_insn_type); +static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); +static struct ia64_opcode *make_ia64_opcode + (ia64_insn, const char *, int, int); +static struct ia64_opcode *ia64_find_matching_opcode + (const char *, short int); + +const struct ia64_templ_desc ia64_templ_desc[16] = + { + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ + { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, + { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, + { 0, { 0, }, "-3-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ + { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ + { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, + { 0, { 0, }, "-a-" }, + { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ + { 0, { 0, }, "-d-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, + { 0, { 0, }, "-f-" }, + }; + + +/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. + PTR will be adjusted to point to the start of the next portion + of the opcode, or at the NUL character. */ + +static void +get_opc_prefix (const char **ptr, char *dest) +{ + char *c = strchr (*ptr, '.'); + if (c != NULL) + { + memcpy (dest, *ptr, c - *ptr); + dest[c - *ptr] = '\0'; + *ptr = c + 1; + } + else + { + int l = strlen (*ptr); + memcpy (dest, *ptr, l); + dest[l] = '\0'; + *ptr += l; + } +} + +/* Find the index of the entry in the string table corresponding to + STR; return -1 if one does not exist. */ + +static short +find_string_ent (const char *str) +{ + short start = 0; + short end = sizeof (ia64_strings) / sizeof (const char *); + short i = (start + end) / 2; + + if (strcmp (str, ia64_strings[end - 1]) > 0) + { + return -1; + } + while (start <= end) + { + int c = strcmp (str, ia64_strings[i]); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the opcode in the main opcode table whose name is STRINGINDEX, or + return -1 if one does not exist. */ + +static short +find_main_ent (short nameindex) +{ + short start = 0; + short end = sizeof (main_table) / sizeof (struct ia64_main_table); + short i = (start + end) / 2; + + if (nameindex < main_table[0].name_index + || nameindex > main_table[end - 1].name_index) + { + return -1; + } + while (start <= end) + { + if (nameindex < main_table[i].name_index) + { + end = i - 1; + } + else if (nameindex == main_table[i].name_index) + { + while (i > 0 && main_table[i - 1].name_index == nameindex) + { + i--; + } + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the index of the entry in the completer table that is part of + MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or + return -1 if one does not exist. */ + +static short +find_completer (short main_ent, short prev_completer, const char *name) +{ + short name_index = find_string_ent (name); + + if (name_index < 0) + { + return -1; + } + + if (prev_completer == -1) + { + prev_completer = main_table[main_ent].completers; + } + else + { + prev_completer = completer_table[prev_completer].subentries; + } + + while (prev_completer != -1) + { + if (completer_table[prev_completer].name_index == name_index) + { + return prev_completer; + } + prev_completer = completer_table[prev_completer].alternative; + } + return -1; +} + +/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and + return the result. */ + +static ia64_insn +apply_completer (ia64_insn opcode, int completer_index) +{ + ia64_insn mask = completer_table[completer_index].mask; + ia64_insn bits = completer_table[completer_index].bits; + int shiftamt = (completer_table[completer_index].offset & 63); + + mask = mask << shiftamt; + bits = bits << shiftamt; + opcode = (opcode & ~mask) | bits; + return opcode; +} + +/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in + the dis_table array, and return its value. (BITOFFSET is numbered + starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the + first byte in OP_POINTER.) */ + +static int +extract_op_bits (int op_pointer, int bitoffset, int bits) +{ + int res = 0; + + op_pointer += (bitoffset / 8); + + if (bitoffset % 8) + { + unsigned int op = dis_table[op_pointer++]; + int numb = 8 - (bitoffset % 8); + int mask = (1 << numb) - 1; + int bata = (bits < numb) ? bits : numb; + int delta = numb - bata; + + res = (res << bata) | ((op & mask) >> delta); + bitoffset += bata; + bits -= bata; + } + while (bits >= 8) + { + res = (res << 8) | (dis_table[op_pointer++] & 255); + bits -= 8; + } + if (bits > 0) + { + unsigned int op = (dis_table[op_pointer++] & 255); + res = (res << bits) | (op >> (8 - bits)); + } + return res; +} + +/* Examine the state machine entry at OP_POINTER in the dis_table + array, and extract its values into OPVAL and OP. The length of the + state entry in bits is returned. */ + +static int +extract_op (int op_pointer, int *opval, unsigned int *op) +{ + int oplen = 5; + + *op = dis_table[op_pointer]; + + if ((*op) & 0x40) + { + opval[0] = extract_op_bits (op_pointer, oplen, 5); + oplen += 5; + } + switch ((*op) & 0x30) + { + case 0x10: + { + opval[1] = extract_op_bits (op_pointer, oplen, 8); + oplen += 8; + opval[1] += op_pointer; + break; + } + case 0x20: + { + opval[1] = extract_op_bits (op_pointer, oplen, 16); + if (! (opval[1] & 32768)) + { + opval[1] += op_pointer; + } + oplen += 16; + break; + } + case 0x30: + { + oplen--; + opval[2] = extract_op_bits (op_pointer, oplen, 12); + oplen += 12; + opval[2] |= 32768; + break; + } + } + if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) + { + opval[2] = extract_op_bits (op_pointer, oplen, 16); + oplen += 16; + if (! (opval[2] & 32768)) + { + opval[2] += op_pointer; + } + } + return oplen; +} + +/* Returns a non-zero value if the opcode in the main_table list at + PLACE matches OPCODE and is of type TYPE. */ + +static int +opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) +{ + if (main_table[place].opcode_type != type) + { + return 0; + } + if (main_table[place].flags + & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) + { + const struct ia64_operand *o1, *o2; + ia64_insn f2, f3; + + if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) + { + o1 = elf64_ia64_operands + IA64_OPND_F2; + o2 = elf64_ia64_operands + IA64_OPND_F3; + (*o1->extract) (o1, opcode, &f2); + (*o2->extract) (o2, opcode, &f3); + if (f2 != f3) + return 0; + } + else + { + ia64_insn len, count; + + /* length must equal 64-count: */ + o1 = elf64_ia64_operands + IA64_OPND_LEN6; + o2 = elf64_ia64_operands + main_table[place].operands[2]; + (*o1->extract) (o1, opcode, &len); + (*o2->extract) (o2, opcode, &count); + if (len != 64 - count) + return 0; + } + } + return 1; +} + +/* Find an instruction entry in the ia64_dis_names array that matches + opcode OPCODE and is of type TYPE. Returns either a positive index + into the array, or a negative value if an entry for OPCODE could + not be found. Checks all matches and returns the one with the highest + priority. */ + +static int +locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) +{ + int currtest[41]; + int bitpos[41]; + int op_ptr[41]; + int currstatenum = 0; + short found_disent = -1; + short found_priority = -1; + + currtest[currstatenum] = 0; + op_ptr[currstatenum] = 0; + bitpos[currstatenum] = 40; + + while (1) + { + int op_pointer = op_ptr[currstatenum]; + unsigned int op; + int currbitnum = bitpos[currstatenum]; + int oplen; + int opval[3] = {0}; + int next_op; + int currbit; + + oplen = extract_op (op_pointer, opval, &op); + + bitpos[currstatenum] = currbitnum; + + /* Skip opval[0] bits in the instruction. */ + if (op & 0x40) + { + currbitnum -= opval[0]; + } + + /* The value of the current bit being tested. */ + currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; + next_op = -1; + + /* We always perform the tests specified in the current state in + a particular order, falling through to the next test if the + previous one failed. */ + switch (currtest[currstatenum]) + { + case 0: + currtest[currstatenum]++; + if (currbit == 0 && (op & 0x80)) + { + /* Check for a zero bit. If this test solely checks for + a zero bit, we can check for up to 8 consecutive zero + bits (the number to check is specified by the lower 3 + bits in the state code.) + + If the state instruction matches, we go to the very + next state instruction; otherwise, try the next test. */ + + if ((op & 0xf8) == 0x80) + { + int count = op & 0x7; + int x; + + for (x = 0; x <= count; x++) + { + int i = + opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; + if (i) + { + break; + } + } + if (x > count) + { + next_op = op_pointer + ((oplen + 7) / 8); + currbitnum -= count; + break; + } + } + else if (! currbit) + { + next_op = op_pointer + ((oplen + 7) / 8); + break; + } + } + /* FALLTHROUGH */ + case 1: + /* If the bit in the instruction is one, go to the state + instruction specified by opval[1]. */ + currtest[currstatenum]++; + if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) + { + next_op = opval[1]; + break; + } + /* FALLTHROUGH */ + case 2: + /* Don't care. Skip the current bit and go to the state + instruction specified by opval[2]. + + An encoding of 0x30 is special; this means that a 12-bit + offset into the ia64_dis_names[] array is specified. */ + currtest[currstatenum]++; + if ((op & 0x08) || ((op & 0x30) == 0x30)) + { + next_op = opval[2]; + break; + } + } + + /* If bit 15 is set in the address of the next state, an offset + in the ia64_dis_names array was specified instead. We then + check to see if an entry in the list of opcodes matches the + opcode we were given; if so, we have succeeded. */ + + if ((next_op >= 0) && (next_op & 32768)) + { + short disent = next_op & 32767; + short priority = -1; + + if (next_op > 65535) + { + abort (); + } + + /* Run through the list of opcodes to check, trying to find + one that matches. */ + while (disent >= 0) + { + int place = ia64_dis_names[disent].insn_index; + + priority = ia64_dis_names[disent].priority; + + if (opcode_verify (opcode, place, type) + && priority > found_priority) + { + break; + } + if (ia64_dis_names[disent].next_flag) + { + disent++; + } + else + { + disent = -1; + } + } + + if (disent >= 0) + { + found_disent = disent; + found_priority = priority; + } + /* Try the next test in this state, regardless of whether a match + was found. */ + next_op = -2; + } + + /* next_op == -1 is "back up to the previous state". + next_op == -2 is "stay in this state and try the next test". + Otherwise, transition to the state indicated by next_op. */ + + if (next_op == -1) + { + currstatenum--; + if (currstatenum < 0) + { + return found_disent; + } + } + else if (next_op >= 0) + { + currstatenum++; + bitpos[currstatenum] = currbitnum - 1; + op_ptr[currstatenum] = next_op; + currtest[currstatenum] = 0; + } + } +} + +/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ + +static struct ia64_opcode * +make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) +{ + struct ia64_opcode *res = + (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); + res->name = xstrdup (name); + res->type = main_table[place].opcode_type; + res->num_outputs = main_table[place].num_outputs; + res->opcode = opcode; + res->mask = main_table[place].mask; + res->operands[0] = main_table[place].operands[0]; + res->operands[1] = main_table[place].operands[1]; + res->operands[2] = main_table[place].operands[2]; + res->operands[3] = main_table[place].operands[3]; + res->operands[4] = main_table[place].operands[4]; + res->flags = main_table[place].flags; + res->ent_index = place; + res->dependencies = &op_dependencies[depind]; + return res; +} + +/* Determine the ia64_opcode entry for the opcode specified by INSN + and TYPE. If a valid entry is not found, return NULL. */ +struct ia64_opcode * +ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) +{ + int disent = locate_opcode_ent (insn, type); + + if (disent < 0) + { + return NULL; + } + else + { + unsigned int cb = ia64_dis_names[disent].completer_index; + static char name[128]; + int place = ia64_dis_names[disent].insn_index; + int ci = main_table[place].completers; + ia64_insn tinsn = main_table[place].opcode; + + strcpy (name, ia64_strings [main_table[place].name_index]); + + while (cb) + { + if (cb & 1) + { + int cname = completer_table[ci].name_index; + + tinsn = apply_completer (tinsn, ci); + + if (ia64_strings[cname][0] != '\0') + { + strcat (name, "."); + strcat (name, ia64_strings[cname]); + } + if (cb != 1) + { + ci = completer_table[ci].subentries; + } + } + else + { + ci = completer_table[ci].alternative; + } + if (ci < 0) + { + abort (); + } + cb = cb >> 1; + } + if (tinsn != (insn & main_table[place].mask)) + { + abort (); + } + return make_ia64_opcode (insn, name, place, + completer_table[ci].dependencies); + } +} + +/* Search the main_opcode table starting from PLACE for an opcode that + matches NAME. Return NULL if one is not found. */ + +static struct ia64_opcode * +ia64_find_matching_opcode (const char *name, short place) +{ + char op[129]; + const char *suffix; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + while (main_table[place].name_index == name_index) + { + const char *curr_suffix = suffix; + ia64_insn curr_insn = main_table[place].opcode; + short completer = -1; + + do { + if (suffix[0] == '\0') + { + completer = find_completer (place, completer, suffix); + } + else + { + get_opc_prefix (&curr_suffix, op); + completer = find_completer (place, completer, op); + } + if (completer != -1) + { + curr_insn = apply_completer (curr_insn, completer); + } + } while (completer != -1 && curr_suffix[0] != '\0'); + + if (completer != -1 && curr_suffix[0] == '\0' + && completer_table[completer].terminal_completer) + { + int depind = completer_table[completer].dependencies; + return make_ia64_opcode (curr_insn, name, place, depind); + } + else + { + place++; + } + } + return NULL; +} + +/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL + if one does not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_next_opcode (struct ia64_opcode *prev_ent) +{ + return ia64_find_matching_opcode (prev_ent->name, + prev_ent->ent_index + 1); +} + +/* Find the first opcode that matches NAME, or return NULL if it does + not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_opcode (const char *name) +{ + char op[129]; + const char *suffix; + short place; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + place = find_main_ent (name_index); + + if (place < 0) + { + return NULL; + } + return ia64_find_matching_opcode (name, place); +} + +/* Free any resources used by ENT. */ +void +ia64_free_opcode (struct ia64_opcode *ent) +{ + free ((void *)ent->name); + free (ent); +} + +const struct ia64_dependency * +ia64_find_dependency (int dep_index) +{ + dep_index = DEP(dep_index); + + if (dep_index < 0 + || dep_index >= (int) ARRAY_SIZE (dependencies)) + return NULL; + + return &dependencies[dep_index]; +} diff --git a/external/gpl3/gdb/dist/opcodes/ia64-opc.h b/external/gpl3/gdb/dist/opcodes/ia64-opc.h new file mode 100644 index 000000000000..0724219e9ca5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-opc.h @@ -0,0 +1,133 @@ +/* ia64-opc.h -- IA-64 opcode table. + Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef IA64_OPC_H +#define IA64_OPC_H + +#include "opcode/ia64.h" + +/* define a couple of abbreviations: */ + +#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) +#define mOp bOp (-1) +#define Op(x) bOp (x), mOp + +#define FIRST IA64_OPCODE_FIRST +#define X_IN_MLX IA64_OPCODE_X_IN_MLX +#define LAST IA64_OPCODE_LAST +#define PRIV IA64_OPCODE_PRIV +#define NO_PRED IA64_OPCODE_NO_PRED +#define SLOT2 IA64_OPCODE_SLOT2 +#define PSEUDO IA64_OPCODE_PSEUDO +#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 +#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT +#define MOD_RRBS IA64_OPCODE_MOD_RRBS +#define POSTINC IA64_OPCODE_POSTINC + +#define AR_CCV IA64_OPND_AR_CCV +#define AR_PFS IA64_OPND_AR_PFS +#define AR_CSD IA64_OPND_AR_CSD +#define C1 IA64_OPND_C1 +#define C8 IA64_OPND_C8 +#define C16 IA64_OPND_C16 +#define GR0 IA64_OPND_GR0 +#define IP IA64_OPND_IP +#define PR IA64_OPND_PR +#define PR_ROT IA64_OPND_PR_ROT +#define PSR IA64_OPND_PSR +#define PSR_L IA64_OPND_PSR_L +#define PSR_UM IA64_OPND_PSR_UM + +#define AR3 IA64_OPND_AR3 +#define B1 IA64_OPND_B1 +#define B2 IA64_OPND_B2 +#define CR3 IA64_OPND_CR3 +#define F1 IA64_OPND_F1 +#define F2 IA64_OPND_F2 +#define F3 IA64_OPND_F3 +#define F4 IA64_OPND_F4 +#define P1 IA64_OPND_P1 +#define P2 IA64_OPND_P2 +#define R1 IA64_OPND_R1 +#define R2 IA64_OPND_R2 +#define R3 IA64_OPND_R3 +#define R3_2 IA64_OPND_R3_2 + +#define CPUID_R3 IA64_OPND_CPUID_R3 +#define DBR_R3 IA64_OPND_DBR_R3 +#define DTR_R3 IA64_OPND_DTR_R3 +#define ITR_R3 IA64_OPND_ITR_R3 +#define IBR_R3 IA64_OPND_IBR_R3 +#define MR3 IA64_OPND_MR3 +#define MSR_R3 IA64_OPND_MSR_R3 +#define PKR_R3 IA64_OPND_PKR_R3 +#define PMC_R3 IA64_OPND_PMC_R3 +#define PMD_R3 IA64_OPND_PMD_R3 +#define RR_R3 IA64_OPND_RR_R3 + +#define CCNT5 IA64_OPND_CCNT5 +#define CNT2a IA64_OPND_CNT2a +#define CNT2b IA64_OPND_CNT2b +#define CNT2c IA64_OPND_CNT2c +#define CNT5 IA64_OPND_CNT5 +#define CNT6 IA64_OPND_CNT6 +#define CPOS6a IA64_OPND_CPOS6a +#define CPOS6b IA64_OPND_CPOS6b +#define CPOS6c IA64_OPND_CPOS6c +#define IMM1 IA64_OPND_IMM1 +#define IMM14 IA64_OPND_IMM14 +#define IMM17 IA64_OPND_IMM17 +#define IMM22 IA64_OPND_IMM22 +#define IMM44 IA64_OPND_IMM44 +#define SOF IA64_OPND_SOF +#define SOL IA64_OPND_SOL +#define SOR IA64_OPND_SOR +#define IMM8 IA64_OPND_IMM8 +#define IMM8U4 IA64_OPND_IMM8U4 +#define IMM8M1 IA64_OPND_IMM8M1 +#define IMM8M1U4 IA64_OPND_IMM8M1U4 +#define IMM8M1U8 IA64_OPND_IMM8M1U8 +#define IMM9a IA64_OPND_IMM9a +#define IMM9b IA64_OPND_IMM9b +#define IMMU2 IA64_OPND_IMMU2 +#define IMMU21 IA64_OPND_IMMU21 +#define IMMU24 IA64_OPND_IMMU24 +#define IMMU62 IA64_OPND_IMMU62 +#define IMMU64 IA64_OPND_IMMU64 +#define IMMU5b IA64_OPND_IMMU5b +#define IMMU7a IA64_OPND_IMMU7a +#define IMMU7b IA64_OPND_IMMU7b +#define IMMU9 IA64_OPND_IMMU9 +#define INC3 IA64_OPND_INC3 +#define LEN4 IA64_OPND_LEN4 +#define LEN6 IA64_OPND_LEN6 +#define MBTYPE4 IA64_OPND_MBTYPE4 +#define MHTYPE8 IA64_OPND_MHTYPE8 +#define POS6 IA64_OPND_POS6 +#define TAG13 IA64_OPND_TAG13 +#define TAG13b IA64_OPND_TAG13b +#define TGT25 IA64_OPND_TGT25 +#define TGT25b IA64_OPND_TGT25b +#define TGT25c IA64_OPND_TGT25c +#define TGT64 IA64_OPND_TGT64 + +#endif diff --git a/external/gpl3/gdb/dist/opcodes/ia64-raw.tbl b/external/gpl3/gdb/dist/opcodes/ia64-raw.tbl new file mode 100644 index 000000000000..7eca3e3c08ab --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-raw.tbl @@ -0,0 +1,198 @@ +Resource Name; Writers; Readers; Semantics of Dependency +ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF +AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF +AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF +AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF +AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF +AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF +AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF +AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF +AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; br.ret; none +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF +AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[RUC]; IC:mov-to-AR-RUC; br.ia, IC:mov-from-AR-RUC; impliedF +AR[SSD]; IC:mov-to-AR-SSD; br.ia, IC:mov-from-AR-SSD; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none +AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF +CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF +CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF +CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF +CFM; alloc; IC:cfm-readers; none +CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data +CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 5.8.3.4, "End of External Interrupt Register (EOI Ð CR67)" on page 2:119 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data +CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data +CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data +CR[IFS]; IC:mov-to-CR-IFS; rfi; implied +CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data +CR[IIB%], % in 0 - 1; IC:mov-to-CR-IIB; IC:mov-from-CR-IIB; data +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data +CR[IIP]; IC:mov-to-CR-IIP; rfi; implied +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data +CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data +CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr +CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 5.8.3.2, "External Interrupt Vector Register (IVR Ð CR65)" on page 2:118 +CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 5.8.3.1, "Local ID (LID Ð CR64)" on page 2:117 +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, IC:mem-readers, IC:mem-writers, IC:non-access, thash; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l+17, ssm+17; SC Section 5.8.3.3, "Task Priority Register (TPR Ð CR66)" on page 2:119 +CR[TPR]; IC:mov-to-CR-TPR; rfi; implied +CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF +DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, IC:non-access; data +DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; IC:mem-readers, IC:mem-writers, IC:non-access; data +DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF +DTR; ptr.d; IC:mem-readers, IC:mem-writers, IC:non-access; data +DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none +DTR; ptr.d; itr.d, itc.d; impliedF +FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none +FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF +FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none +GR0; IC:none; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data +InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc, vmsw; instr +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none +ITC; itc.i, itc.d, itr.i, itr.d; epc, vmsw; instr +ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF +ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF +ITR; itr.i; epc, vmsw; instr +ITR; ptr.i; itc.i, itr.i; impliedF +ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none +ITR; ptr.i; epc, vmsw; instr +memory; IC:mem-writers; IC:mem-readers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific +PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC Section 7.2.1, "Generic Performance Counter Registers" for PMC[0].fr on page 2:150 +PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR+12, IC:mov-to-PR+12; none +PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-readers-br+1; none +PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF +PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers; data +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.ac; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers; data +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.be; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF +PSR.cpl; epc, br.ret; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-RUC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied +PSR.cpl; rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-RUC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; impliedF +PSR.da; rfi; IC:mem-readers, IC:lfetch-all, IC:mem-writers, IC:probe-fault; impliedF +PSR.db; IC:mov-to-PSR-l; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.db; rfi; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; impliedF +PSR.dd; rfi; IC:lfetch-all, IC:mem-readers, IC:probe-fault, IC:mem-writers; impliedF +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:fr-readers+8, IC:fr-writers+8; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.dfh; rfi; IC:fr-readers+8, IC:fr-writers+8, IC:mov-from-PSR; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:fr-writers+8, IC:fr-readers+8; data +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.dfl; rfi; IC:fr-writers+8, IC:fr-readers+8, IC:mov-from-PSR; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; br.ia; data +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.di; rfi; br.ia, IC:mov-from-PSR; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:non-access; data +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.dt; rfi; IC:mem-readers, IC:mem-writers, IC:non-access, IC:mov-from-PSR; impliedF +PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; impliedF +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ia; rfi; IC:all; none +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-interruption-CR, IC:mov-to-interruption-CR; data +PSR.ic; rfi; IC:mov-from-PSR, cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-interruption-CR, IC:mov-to-interruption-CR; impliedF +PSR.id; rfi; IC:all; none +PSR.is; br.ia, rfi; IC:none; none +PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf, vmsw; impliedF +PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.lp; IC:mov-to-PSR-l; br.ret; data +PSR.lp; rfi; IC:mov-from-PSR, br.ret; impliedF +PSR.mc; rfi; IC:mov-from-PSR; impliedF +PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:probe-all; data +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.pk; rfi; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-all; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ri; rfi; IC:all; none +PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data +PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-AR-ITC, IC:mov-from-AR-RUC; data +PSR.si; rfi; IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-from-PSR; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data +PSR.sp; rfi; IC:mov-from-IND-PMD, IC:mov-from-PSR, IC:mov-to-PSR-um, rum, sum; impliedF +PSR.ss; rfi; IC:all; impliedF +PSR.tb; IC:mov-to-PSR-l; IC:branches, chk, fchkf; data +PSR.tb; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.tb; rfi; IC:branches, chk, fchkf, IC:mov-from-PSR; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.vm; vmsw; IC:mem-readers, IC:mem-writers, IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-from-IND-CPUID, IC:mov-to-AR-ITC, IC:priv-ops\vmsw, cover, thash, ttag; implied +PSR.vm; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-from-IND-CPUID, IC:mov-to-AR-ITC, IC:priv-ops\vmsw, cover, thash, ttag; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:non-access, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, thash, ttag; data +RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/external/gpl3/gdb/dist/opcodes/ia64-war.tbl b/external/gpl3/gdb/dist/opcodes/ia64-war.tbl new file mode 100644 index 000000000000..8cdfac5b485f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-war.tbl @@ -0,0 +1,2 @@ +Resource Name; Readers; Writers; Semantics of Dependency +PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop diff --git a/external/gpl3/gdb/dist/opcodes/ia64-waw.tbl b/external/gpl3/gdb/dist/opcodes/ia64-waw.tbl new file mode 100644 index 000000000000..82b9e839a58e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ia64-waw.tbl @@ -0,0 +1,139 @@ +Resource Name; Writers; Writers; Semantics of Dependency +ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF +AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF +AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF +AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF +AR[EFLAG]; IC:mov-to-AR-EFLAG; IC:mov-to-AR-EFLAG; impliedF +AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF +AR[FDR]; IC:mov-to-AR-FDR; IC:mov-to-AR-FDR; impliedF +AR[FIR]; IC:mov-to-AR-FIR; IC:mov-to-AR-FIR; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none +AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none +AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none +AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none +AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF +AR[PFS]; br.call, brl.call; br.call, brl.call; none +AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF +AR[RUC]; IC:mov-to-AR-RUC; IC:mov-to-AR-RUC; impliedF +AR[SSD]; IC:mov-to-AR-SSD; IC:mov-to-AR-SSD; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111; IC:none; IC:none; none +AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none +CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF +CPUID#; IC:none; IC:none; none +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF +CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 5.8.3.4, "End of External Interrupt Register (EOI Ð CR67)" on page 2:119 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF +CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF +CR[IIB%], % in 0 - 1; IC:mov-to-CR-IIB; IC:mov-to-CR-IIB; impliedF +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF +CR[IVR]; IC:none; IC:none; SC +CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF +CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127; IC:none; IC:none; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; itr.d; impliedF +DTR; itr.d; ptr.d; impliedF +DTR; ptr.d; ptr.d; none +FR%, % in 0 - 1; IC:none; IC:none; none +FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF +GR0; IC:none; IC:none; none +GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITR; itr.i; itr.i, ptr.i; impliedF +ITR; ptr.i; ptr.i; none +memory; IC:mem-writers; IC:mem-writers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF +PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-writers+1; none +PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF +PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.bn; bsw, rfi; bsw, rfi; impliedF +PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF +PSR.da; rfi; rfi; impliedF +PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.dd; rfi; rfi; impliedF +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ed; rfi; rfi; impliedF +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ia; rfi; rfi; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.id; rfi; rfi; impliedF +PSR.is; br.ia, rfi; br.ia, rfi; impliedF +PSR.it; rfi; rfi; impliedF +PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.mc; rfi; rfi; impliedF +PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ri; rfi; rfi; impliedF +PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ss; rfi; rfi; impliedF +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.vm; rfi, vmsw; rfi, vmsw; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-asm.c b/external/gpl3/gdb/dist/opcodes/ip2k-asm.c new file mode 100644 index 000000000000..03e219c55447 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-asm.c @@ -0,0 +1,919 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +static const char * +parse_fr (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + const char *old_strp; + char *afteroffset; + enum cgen_parse_operand_result result_type; + bfd_vma value; + extern CGEN_KEYWORD ip2k_cgen_opval_register_names; + bfd_vma tempvalue; + + old_strp = *strp; + afteroffset = NULL; + + /* Check here to see if you're about to try parsing a w as the first arg + and return an error if you are. */ + if ((strncmp (*strp, "w", 1) == 0) || (strncmp (*strp, "W", 1) == 0)) + { + (*strp)++; + + if ((strncmp (*strp, ",", 1) == 0) || ISSPACE (**strp)) + { + /* We've been passed a w. Return with an error message so that + cgen will try the next parsing option. */ + errmsg = _("W keyword invalid in FR operand slot."); + return errmsg; + } + *strp = old_strp; + } + + /* Attempt parse as register keyword. */ + errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, + (long *) valuep); + if (*strp != NULL + && errmsg == NULL) + return errmsg; + + /* Attempt to parse for "(IP)". */ + afteroffset = strstr (*strp, "(IP)"); + + if (afteroffset == NULL) + /* Make sure it's not in lower case. */ + afteroffset = strstr (*strp, "(ip)"); + + if (afteroffset != NULL) + { + if (afteroffset != *strp) + { + /* Invalid offset present. */ + errmsg = _("offset(IP) is not a valid form"); + return errmsg; + } + else + { + *strp += 4; + *valuep = 0; + errmsg = NULL; + return errmsg; + } + } + + /* Attempt to parse for DP. ex: mov w, offset(DP) + mov offset(DP),w */ + + /* Try parsing it as an address and see what comes back. */ + afteroffset = strstr (*strp, "(DP)"); + + if (afteroffset == NULL) + /* Maybe it's in lower case. */ + afteroffset = strstr (*strp, "(dp)"); + + if (afteroffset != NULL) + { + if (afteroffset == *strp) + { + /* No offset present. Use 0 by default. */ + tempvalue = 0; + errmsg = NULL; + } + else + errmsg = cgen_parse_address (cd, strp, opindex, + BFD_RELOC_IP2K_FR_OFFSET, + & result_type, & tempvalue); + + if (errmsg == NULL) + { + if (tempvalue <= 127) + { + /* Value is ok. Fix up the first 2 bits and return. */ + *valuep = 0x0100 | tempvalue; + *strp += 4; /* Skip over the (DP) in *strp. */ + return errmsg; + } + else + { + /* Found something there in front of (DP) but it's out + of range. */ + errmsg = _("(DP) offset out of range."); + return errmsg; + } + } + } + + + /* Attempt to parse for SP. ex: mov w, offset(SP) + mov offset(SP), w. */ + afteroffset = strstr (*strp, "(SP)"); + + if (afteroffset == NULL) + /* Maybe it's in lower case. */ + afteroffset = strstr (*strp, "(sp)"); + + if (afteroffset != NULL) + { + if (afteroffset == *strp) + { + /* No offset present. Use 0 by default. */ + tempvalue = 0; + errmsg = NULL; + } + else + errmsg = cgen_parse_address (cd, strp, opindex, + BFD_RELOC_IP2K_FR_OFFSET, + & result_type, & tempvalue); + + if (errmsg == NULL) + { + if (tempvalue <= 127) + { + /* Value is ok. Fix up the first 2 bits and return. */ + *valuep = 0x0180 | tempvalue; + *strp += 4; /* Skip over the (SP) in *strp. */ + return errmsg; + } + else + { + /* Found something there in front of (SP) but it's out + of range. */ + errmsg = _("(SP) offset out of range."); + return errmsg; + } + } + } + + /* Attempt to parse as an address. */ + *strp = old_strp; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9, + & result_type, & value); + if (errmsg == NULL) + { + *valuep = value; + + /* If a parenthesis is found, warn about invalid form. */ + if (**strp == '(') + errmsg = _("illegal use of parentheses"); + + /* If a numeric value is specified, ensure that it is between + 1 and 255. */ + else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + if (value < 0x1 || value > 0xff) + errmsg = _("operand out of range (not between 1 and 255)"); + } + } + return errmsg; +} + +static const char * +parse_addr16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16H) + code = BFD_RELOC_IP2K_HI8DATA; + else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16L) + code = BFD_RELOC_IP2K_LO8DATA; + else + { + /* Something is very wrong. opindex has to be one of the above. */ + errmsg = _("parse_addr16: invalid opindex."); + return errmsg; + } + + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + /* We either have a relocation or a number now. */ + if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* We got a number back. */ + if (code == BFD_RELOC_IP2K_HI8DATA) + value >>= 8; + else + /* code = BFD_RELOC_IP2K_LOW8DATA. */ + value &= 0x00FF; + } + *valuep = value; + } + + return errmsg; +} + +static const char * +parse_addr16_cjp (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) + code = BFD_RELOC_IP2K_ADDR16CJP; + else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) + code = BFD_RELOC_IP2K_PAGE3; + + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + if ((value & 0x1) == 0) /* If the address is even .... */ + { + if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) + *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ + else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) + *valuep = (value >> 14) & 0x7; + } + else + errmsg = _("Byte address required. - must be even."); + } + else if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) + { + /* This will happen for things like (s2-s1) where s2 and s1 + are labels. */ + *valuep = value; + } + else + errmsg = _("cgen_parse_address returned a symbol. Literal required."); + } + return errmsg; +} + +static const char * +parse_lit8 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + /* Parse %OP relocating operators. */ + if (strncmp (*strp, "%bank", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_IP2K_BANK; + } + else if (strncmp (*strp, "%lo8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_LO8DATA; + } + else if (strncmp (*strp, "%hi8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_HI8DATA; + } + else if (strncmp (*strp, "%ex8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_EX8DATA; + } + else if (strncmp (*strp, "%lo8insn", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_LO8INSN; + } + else if (strncmp (*strp, "%hi8insn", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_HI8INSN; + } + + /* Parse %op operand. */ + if (code != BFD_RELOC_NONE) + { + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if ((errmsg == NULL) && + (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED)) + errmsg = _("percent-operator operand is not a symbol"); + + *valuep = value; + } + /* Parse as a number. */ + else + { + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + + /* Truncate to eight bits to accept both signed and unsigned input. */ + if (errmsg == NULL) + *valuep &= 0xFF; + } + + return errmsg; +} + +static const char * +parse_bit3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + char mode = 0; + long count = 0; + unsigned long value; + + if (strncmp (*strp, "%bit", 4) == 0) + { + *strp += 4; + mode = 1; + } + else if (strncmp (*strp, "%msbbit", 7) == 0) + { + *strp += 7; + mode = 1; + } + else if (strncmp (*strp, "%lsbbit", 7) == 0) + { + *strp += 7; + mode = 2; + } + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + if (errmsg) + return errmsg; + + if (mode) + { + value = * valuep; + if (value == 0) + { + errmsg = _("Attempt to find bit index of 0"); + return errmsg; + } + + if (mode == 1) + { + count = 31; + while ((value & 0x80000000) == 0) + { + count--; + value <<= 1; + } + } + else if (mode == 2) + { + count = 0; + while ((value & 0x00000001) == 0) + { + count++; + value >>= 1; + } + } + + *valuep = count; + } + + return errmsg; +} + +/* -- dis.c */ + +const char * ip2k_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +ip2k_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16CJP, (unsigned long *) (& fields->f_addr16cjp)); + break; + case IP2K_OPERAND_ADDR16H : + errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16H, (unsigned long *) (& fields->f_imm8)); + break; + case IP2K_OPERAND_ADDR16L : + errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16L, (unsigned long *) (& fields->f_imm8)); + break; + case IP2K_OPERAND_ADDR16P : + errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16P, (unsigned long *) (& fields->f_page3)); + break; + case IP2K_OPERAND_BITNO : + errmsg = parse_bit3 (cd, strp, IP2K_OPERAND_BITNO, (unsigned long *) (& fields->f_bitno)); + break; + case IP2K_OPERAND_CBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_CBIT, (unsigned long *) (& junk)); + break; + case IP2K_OPERAND_DCBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_DCBIT, (unsigned long *) (& junk)); + break; + case IP2K_OPERAND_FR : + errmsg = parse_fr (cd, strp, IP2K_OPERAND_FR, (unsigned long *) (& fields->f_reg)); + break; + case IP2K_OPERAND_LIT8 : + errmsg = parse_lit8 (cd, strp, IP2K_OPERAND_LIT8, (long *) (& fields->f_imm8)); + break; + case IP2K_OPERAND_PABITS : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_PABITS, (unsigned long *) (& junk)); + break; + case IP2K_OPERAND_RETI3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_RETI3, (unsigned long *) (& fields->f_reti3)); + break; + case IP2K_OPERAND_ZBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_ZBIT, (unsigned long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const ip2k_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +ip2k_cgen_init_asm (CGEN_CPU_DESC cd) +{ + ip2k_cgen_init_opcode_table (cd); + ip2k_cgen_init_ibld_table (cd); + cd->parse_handlers = & ip2k_cgen_parse_handlers[0]; + cd->parse_operand = ip2k_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by ip2k_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +ip2k_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! ip2k_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-desc.c b/external/gpl3/gdb/dist/opcodes/ip2k-desc.c new file mode 100644 index 000000000000..4a90db5b63af --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-desc.c @@ -0,0 +1,1177 @@ +/* CPU data for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "ip2022", MACH_IP2022 }, + { "ip2022ext", MACH_IP2022EXT }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "ip2k", ISA_IP2K }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] }, + { "SKIPA", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA ip2k_cgen_isa_table[] = { + { "ip2k", 16, 16, 16, 16 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH ip2k_cgen_mach_table[] = { + { "ip2022", "ip2022", MACH_IP2022, 0 }, + { "ip2022ext", "ip2022ext", MACH_IP2022EXT, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] = +{ + { "ADDRSEL", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRX", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "IPH", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "IPL", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "SPH", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "SPL", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "PCH", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "PCL", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "WREG", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "STATUS", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "DPH", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "DPL", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "SPDREG", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "MULH", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRH", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "ADDRL", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "DATAH", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "DATAL", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "INTVECH", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "INTVECL", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "INTSPD", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "INTF", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "INTE", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "INTED", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "FCFG", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "TCTRL", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "XCFG", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "EMCFG", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "IPCH", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "IPCL", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "RAIN", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "RAOUT", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "RADIR", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRH", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "RBIN", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "RBOUT", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "RBDIR", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRL", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "RCIN", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "RCOUT", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "RCDIR", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "LFSRA", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "RDIN", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "RDOUT", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "RDDIR", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "REIN", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "REOUT", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "REDIR", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "RFIN", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "RFOUT", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "RFDIR", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "RGOUT", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "RGDIR", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "RTTMR", 64, {0, {{{0, 0}}}}, 0, 0 }, + { "RTCFG", 65, {0, {{{0, 0}}}}, 0, 0 }, + { "T0TMR", 66, {0, {{{0, 0}}}}, 0, 0 }, + { "T0CFG", 67, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CNTH", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CNTL", 69, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP1H", 70, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP1L", 71, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP2H", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP2H", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CAP2L", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP2L", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP1H", 74, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CMP1L", 75, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG1H", 76, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG1L", 77, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG2H", 78, {0, {{{0, 0}}}}, 0, 0 }, + { "T1CFG2L", 79, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCH", 80, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCL", 81, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCCFG", 82, {0, {{{0, 0}}}}, 0, 0 }, + { "ADCTMR", 83, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CNTH", 84, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CNTL", 85, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP1H", 86, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP1L", 87, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP2H", 88, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP2H", 88, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CAP2L", 89, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP2L", 89, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP1H", 90, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CMP1L", 91, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG1H", 92, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG1L", 93, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG2H", 94, {0, {{{0, 0}}}}, 0, 0 }, + { "T2CFG2L", 95, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TMRH", 96, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TMRL", 97, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TBUFH", 98, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TBUFL", 99, {0, {{{0, 0}}}}, 0, 0 }, + { "S1TCFG", 100, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RCNT", 101, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RBUFH", 102, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RBUFL", 103, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RCFG", 104, {0, {{{0, 0}}}}, 0, 0 }, + { "S1RSYNC", 105, {0, {{{0, 0}}}}, 0, 0 }, + { "S1INTF", 106, {0, {{{0, 0}}}}, 0, 0 }, + { "S1INTE", 107, {0, {{{0, 0}}}}, 0, 0 }, + { "S1MODE", 108, {0, {{{0, 0}}}}, 0, 0 }, + { "S1SMASK", 109, {0, {{{0, 0}}}}, 0, 0 }, + { "PSPCFG", 110, {0, {{{0, 0}}}}, 0, 0 }, + { "CMPCFG", 111, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TMRH", 112, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TMRL", 113, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TBUFH", 114, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TBUFL", 115, {0, {{{0, 0}}}}, 0, 0 }, + { "S2TCFG", 116, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RCNT", 117, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RBUFH", 118, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RBUFL", 119, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RCFG", 120, {0, {{{0, 0}}}}, 0, 0 }, + { "S2RSYNC", 121, {0, {{{0, 0}}}}, 0, 0 }, + { "S2INTF", 122, {0, {{{0, 0}}}}, 0, 0 }, + { "S2INTE", 123, {0, {{{0, 0}}}}, 0, 0 }, + { "S2MODE", 124, {0, {{{0, 0}}}}, 0, 0 }, + { "S2SMASK", 125, {0, {{{0, 0}}}}, 0, 0 }, + { "CALLH", 126, {0, {{{0, 0}}}}, 0, 0 }, + { "CALLL", 127, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD ip2k_cgen_opval_register_names = +{ + & ip2k_cgen_opval_register_names_entries[0], + 121, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY ip2k_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & ip2k_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & ip2k_cgen_ifld_table[0]; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & ip2k_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */ + +static void +ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & ip2k_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & ip2k_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "ip2k_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (ip2k_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "ip2k_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "ip2k_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = ip2k_cgen_rebuild_tables; + ip2k_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to ip2k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +ip2k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +ip2k_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-desc.h b/external/gpl3/gdb/dist/opcodes/ip2k-desc.h new file mode 100644 index 000000000000..35a38d3ba88b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-desc.h @@ -0,0 +1,290 @@ +/* CPU data header for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef IP2K_CPU_H +#define IP2K_CPU_H + +#define CGEN_ARCH ip2k + +/* Given symbol S, return ip2k_cgen_. */ +#define CGEN_SYM(s) ip2k##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_IP2KBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 2 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3 + +/* Enums. */ + +/* Enum declaration for op6 enums. */ +typedef enum insn_op6 { + OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC + , OP6_OR, OP6_AND, OP6_XOR, OP6_ADD + , OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ + , OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ + , OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ + , OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC +} INSN_OP6; + +/* Enum declaration for dir enums. */ +typedef enum insn_dir { + DIR_TO_W, DIR_NOTTO_W +} INSN_DIR; + +/* Enum declaration for op4 enums. */ +typedef enum insn_op4 { + OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10 + , OP4_SB = 11 +} INSN_OP4; + +/* Enum declaration for op4mid enums. */ +typedef enum insn_op4mid { + OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3 + , OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8 + , OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12 + , OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15 +} INSN_OP4MID; + +/* Enum declaration for op3 enums. */ +typedef enum insn_op3 { + OP3_CALL = 6, OP3_JMP = 7 +} INSN_OP3; + +/* Enum declaration for . */ +typedef enum register_names { + H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5 + , H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9 + , H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13 + , H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17 + , H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21 + , H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25 + , H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29 + , H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33 + , H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37 + , H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41 + , H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45 + , H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50 + , H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57 + , H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66 + , H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70 + , H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73 + , H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76 + , H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80 + , H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84 + , H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88 + , H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90 + , H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94 + , H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98 + , H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102 + , H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106 + , H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110 + , H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114 + , H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118 + , H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122 + , H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126 + , H_REGISTERS_CALLL = 127 +} REGISTER_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_IP2K, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for ip2k ifield types. */ +typedef enum ifield_type { + IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG + , IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3 + , IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8 + , IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB + , IP2K_F_PAGE3, IP2K_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) IP2K_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for ip2k hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK + , HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT + , HW_H_PC, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for ip2k operand types. */ +typedef enum cgen_operand_type { + IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8 + , IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L + , IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT + , IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 13 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIPA)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld ip2k_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[]; + +/* Hardware decls. */ + + +extern const CGEN_HW_ENTRY ip2k_cgen_hw_table[]; + + + +#endif /* IP2K_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-dis.c b/external/gpl3/gdb/dist/opcodes/ip2k-dis.c new file mode 100644 index 000000000000..10d94da1b690 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-dis.c @@ -0,0 +1,709 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +static void +print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + extern CGEN_KEYWORD ip2k_cgen_opval_register_names; + long offsettest; + long offsetvalue; + + if (value == 0) /* This is (IP). */ + { + (*info->fprintf_func) (info->stream, "%s", "(IP)"); + return; + } + + offsettest = value >> 7; + offsetvalue = value & 0x7F; + + /* Check to see if first two bits are 10 -> (DP). */ + if (offsettest == 2) + { + if (offsetvalue == 0) + (*info->fprintf_func) (info->stream, "%s","(DP)"); + else + (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue, "(DP)"); + return; + } + + /* Check to see if first two bits are 11 -> (SP). */ + if (offsettest == 3) + { + if (offsetvalue == 0) + (*info->fprintf_func) (info->stream, "%s", "(SP)"); + else + (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue,"(SP)"); + return; + } + + /* Attempt to print as a register keyword. */ + ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value); + + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + /* Print as an address literal. */ + (*info->fprintf_func) (info->stream, "$%02lx", value); +} + +static void +print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%lx", value); +} + +static void +print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%02lx", value); +} + +static void +print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* This is a loadh instruction. Shift the value to the left + by 8 bits so that disassembled code will reassemble properly. */ + value = ((value << 8) & 0xFF00); + + (*info->fprintf_func) (info->stream, "$%04lx", value); +} + +static void +print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%04lx", value); +} + +static void +print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + value = ((value << 14) & 0x1C000); + ;value = (value & 0x1FFFF); + (*info->fprintf_func) (info->stream, "$%05lx", value); +} + +static void +print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + value = ((value << 1) & 0x1FFFF); + (*info->fprintf_func) (info->stream, "$%05lx", value); +} + +static void +print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "%ld", value); +} + + + +/* -- */ + +void ip2k_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +ip2k_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + print_dollarhex_cj (cd, info, fields->f_addr16cjp, 0|(1<f_imm8, 0, pc, length); + break; + case IP2K_OPERAND_ADDR16L : + print_dollarhex_addr16l (cd, info, fields->f_imm8, 0, pc, length); + break; + case IP2K_OPERAND_ADDR16P : + print_dollarhex_p (cd, info, fields->f_page3, 0, pc, length); + break; + case IP2K_OPERAND_BITNO : + print_decimal (cd, info, fields->f_bitno, 0, pc, length); + break; + case IP2K_OPERAND_CBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case IP2K_OPERAND_DCBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case IP2K_OPERAND_FR : + print_fr (cd, info, fields->f_reg, 0|(1<f_imm8, 0|(1<f_reti3, 0, pc, length); + break; + case IP2K_OPERAND_ZBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const ip2k_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +ip2k_cgen_init_dis (CGEN_CPU_DESC cd) +{ + ip2k_cgen_init_opcode_table (cd); + ip2k_cgen_init_ibld_table (cd); + cd->print_handlers = & ip2k_cgen_print_handlers[0]; + cd->print_operand = ip2k_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + ip2k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! ip2k_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_ip2k (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_ip2k +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + ip2k_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-ibld.c b/external/gpl3/gdb/dist/opcodes/ip2k-ibld.c new file mode 100644 index 000000000000..46c159a3e0b4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-ibld.c @@ -0,0 +1,938 @@ +/* Instruction building/extraction support for ip2k. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * ip2k_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +ip2k_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + errmsg = insert_normal (cd, fields->f_addr16cjp, 0|(1<f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_ADDR16L : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_ADDR16P : + errmsg = insert_normal (cd, fields->f_page3, 0, 0, 2, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_BITNO : + errmsg = insert_normal (cd, fields->f_bitno, 0, 0, 11, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + errmsg = insert_normal (cd, fields->f_reg, 0|(1<f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + errmsg = insert_normal (cd, fields->f_reti3, 0, 0, 2, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int ip2k_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +ip2k_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_addr16cjp); + break; + case IP2K_OPERAND_ADDR16H : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16L : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16P : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_page3); + break; + case IP2K_OPERAND_BITNO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 16, total_length, pc, & fields->f_bitno); + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_reg); + break; + case IP2K_OPERAND_LIT8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_reti3); + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const ip2k_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const ip2k_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int ip2k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma ip2k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +ip2k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + value = fields->f_addr16cjp; + break; + case IP2K_OPERAND_ADDR16H : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16L : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16P : + value = fields->f_page3; + break; + case IP2K_OPERAND_BITNO : + value = fields->f_bitno; + break; + case IP2K_OPERAND_CBIT : + value = 0; + break; + case IP2K_OPERAND_DCBIT : + value = 0; + break; + case IP2K_OPERAND_FR : + value = fields->f_reg; + break; + case IP2K_OPERAND_LIT8 : + value = fields->f_imm8; + break; + case IP2K_OPERAND_PABITS : + value = 0; + break; + case IP2K_OPERAND_RETI3 : + value = fields->f_reti3; + break; + case IP2K_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +ip2k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + value = fields->f_addr16cjp; + break; + case IP2K_OPERAND_ADDR16H : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16L : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16P : + value = fields->f_page3; + break; + case IP2K_OPERAND_BITNO : + value = fields->f_bitno; + break; + case IP2K_OPERAND_CBIT : + value = 0; + break; + case IP2K_OPERAND_DCBIT : + value = 0; + break; + case IP2K_OPERAND_FR : + value = fields->f_reg; + break; + case IP2K_OPERAND_LIT8 : + value = fields->f_imm8; + break; + case IP2K_OPERAND_PABITS : + value = 0; + break; + case IP2K_OPERAND_RETI3 : + value = fields->f_reti3; + break; + case IP2K_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void ip2k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void ip2k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +ip2k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + fields->f_addr16cjp = value; + break; + case IP2K_OPERAND_ADDR16H : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16L : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16P : + fields->f_page3 = value; + break; + case IP2K_OPERAND_BITNO : + fields->f_bitno = value; + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + fields->f_reg = value; + break; + case IP2K_OPERAND_LIT8 : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + fields->f_reti3 = value; + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +ip2k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + fields->f_addr16cjp = value; + break; + case IP2K_OPERAND_ADDR16H : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16L : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16P : + fields->f_page3 = value; + break; + case IP2K_OPERAND_BITNO : + fields->f_bitno = value; + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + fields->f_reg = value; + break; + case IP2K_OPERAND_LIT8 : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + fields->f_reti3 = value; + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +ip2k_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & ip2k_cgen_insert_handlers[0]; + cd->extract_handlers = & ip2k_cgen_extract_handlers[0]; + + cd->insert_operand = ip2k_cgen_insert_operand; + cd->extract_operand = ip2k_cgen_extract_operand; + + cd->get_int_operand = ip2k_cgen_get_int_operand; + cd->set_int_operand = ip2k_cgen_set_int_operand; + cd->get_vma_operand = ip2k_cgen_get_vma_operand; + cd->set_vma_operand = ip2k_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-opc.c b/external/gpl3/gdb/dist/opcodes/ip2k-opc.c new file mode 100644 index 000000000000..4391a6cf137a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-opc.c @@ -0,0 +1,903 @@ +/* Instruction opcode table for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "libiberty.h" + +/* -- opc.c */ + +#include "safe-ctype.h" + +/* A better hash function for instruction mnemonics. */ +unsigned int +ip2k_asm_hash (const char* insn) +{ + unsigned int hash; + const char* m = insn; + + for (hash = 0; *m && ! ISSPACE (*m); m++) + hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); + + /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ + + return hash % CGEN_ASM_HASH_SIZE; +} + + +/* Special check to ensure that instruction exists for given machine. */ + +int +ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + + /* No mach attribute? Assume it's supported for all machs. */ + if (machs == 0) + return 1; + + return (machs & cd->machs) != 0; +} + + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & ip2k_cgen_ifld_table[IP2K_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 16, 16, 0xe000, { { F (F_OP3) }, { F (F_ADDR16CJP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xorw_l ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loadl_a ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loadh_a ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addcfr_w ATTRIBUTE_UNUSED = { + 16, 16, 0xfe00, { { F (F_OP6) }, { F (F_DIR) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_speed ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP8) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ireadi ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP6) }, { F (F_OP6_10LOW) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_page ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_PAGE3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_RETI3) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) IP2K_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE ip2k_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* jmp $addr16cjp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16CJP), 0 } }, + & ifmt_jmp, { 0xe000 } + }, +/* call $addr16cjp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16CJP), 0 } }, + & ifmt_jmp, { 0xc000 } + }, +/* sb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0xb000 } + }, +/* snb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0xa000 } + }, +/* setb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0x9000 } + }, +/* clrb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0x8000 } + }, +/* xor W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7f00 } + }, +/* and W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7e00 } + }, +/* or W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7d00 } + }, +/* add W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7b00 } + }, +/* sub W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7a00 } + }, +/* cmp W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7900 } + }, +/* retw #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7800 } + }, +/* cse W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7700 } + }, +/* csne W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7600 } + }, +/* push #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7400 } + }, +/* muls W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7300 } + }, +/* mulu W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7200 } + }, +/* loadl #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7100 } + }, +/* loadh #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7000 } + }, +/* loadl $addr16l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16L), 0 } }, + & ifmt_loadl_a, { 0x7100 } + }, +/* loadh $addr16h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16H), 0 } }, + & ifmt_loadh_a, { 0x7000 } + }, +/* addc $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x5e00 } + }, +/* addc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5c00 } + }, +/* incsnz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5a00 } + }, +/* incsnz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5800 } + }, +/* muls W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5400 } + }, +/* mulu W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5000 } + }, +/* decsnz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4e00 } + }, +/* decsnz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4c00 } + }, +/* subc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4800 } + }, +/* subc $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x4a00 } + }, +/* pop $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4600 } + }, +/* push $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4400 } + }, +/* cse W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4200 } + }, +/* csne W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4000 } + }, +/* incsz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3e00 } + }, +/* incsz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3c00 } + }, +/* swap $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3a00 } + }, +/* swap W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3800 } + }, +/* rl $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3600 } + }, +/* rl W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3400 } + }, +/* rr $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3200 } + }, +/* rr W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3000 } + }, +/* decsz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2e00 } + }, +/* decsz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2c00 } + }, +/* inc $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2a00 } + }, +/* inc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2800 } + }, +/* not $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2600 } + }, +/* not W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2400 } + }, +/* test $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2200 } + }, +/* mov W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7c00 } + }, +/* mov $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x200 } + }, +/* mov W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2000 } + }, +/* add $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1e00 } + }, +/* add W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1c00 } + }, +/* xor $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1a00 } + }, +/* xor W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1800 } + }, +/* and $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1600 } + }, +/* and W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1400 } + }, +/* or $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1200 } + }, +/* or W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1000 } + }, +/* dec $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0xe00 } + }, +/* dec W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0xc00 } + }, +/* sub $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0xa00 } + }, +/* sub W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x800 } + }, +/* clr $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x600 } + }, +/* cmp W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x400 } + }, +/* speed #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_speed, { 0x100 } + }, +/* ireadi */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1d } + }, +/* iwritei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1c } + }, +/* fread */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1b } + }, +/* fwrite */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1a } + }, +/* iread */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x19 } + }, +/* iwrite */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x18 } + }, +/* page $addr16p */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16P), 0 } }, + & ifmt_page, { 0x10 } + }, +/* system */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0xff } + }, +/* reti #$reti3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RETI3), 0 } }, + & ifmt_reti, { 0x8 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x7 } + }, +/* int */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x6 } + }, +/* breakx */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x5 } + }, +/* cwdt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x4 } + }, +/* ferase */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x3 } + }, +/* retnp */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x2 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x0 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & ip2k_cgen_ifld_table[IP2K_##f] +static const CGEN_IFMT ifmt_sc ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_snc ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sz ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_snz ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_skip ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_skipb ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) IP2K_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE ip2k_cgen_macro_insn_table[] = +{ +/* sc */ + { + -1, "sc", "sc", 16, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + ip2k_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & ip2k_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + ip2k_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/ip2k-opc.h b/external/gpl3/gdb/dist/opcodes/ip2k-opc.h new file mode 100644 index 000000000000..77a0f3583c0c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ip2k-opc.h @@ -0,0 +1,118 @@ +/* Instruction opcode header for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef IP2K_OPC_H +#define IP2K_OPC_H + +/* -- opc.h */ + +/* Check applicability of instructions against machines. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf, value) \ + (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) + +#define CGEN_ASM_HASH_SIZE 127 +#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn) + +extern unsigned int ip2k_asm_hash (const char *); +extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +/* -- opc.c */ +/* Enum declaration for ip2k instruction types. */ +typedef enum cgen_insn_type { + IP2K_INSN_INVALID, IP2K_INSN_JMP, IP2K_INSN_CALL, IP2K_INSN_SB + , IP2K_INSN_SNB, IP2K_INSN_SETB, IP2K_INSN_CLRB, IP2K_INSN_XORW_L + , IP2K_INSN_ANDW_L, IP2K_INSN_ORW_L, IP2K_INSN_ADDW_L, IP2K_INSN_SUBW_L + , IP2K_INSN_CMPW_L, IP2K_INSN_RETW_L, IP2K_INSN_CSEW_L, IP2K_INSN_CSNEW_L + , IP2K_INSN_PUSH_L, IP2K_INSN_MULSW_L, IP2K_INSN_MULUW_L, IP2K_INSN_LOADL_L + , IP2K_INSN_LOADH_L, IP2K_INSN_LOADL_A, IP2K_INSN_LOADH_A, IP2K_INSN_ADDCFR_W + , IP2K_INSN_ADDCW_FR, IP2K_INSN_INCSNZ_FR, IP2K_INSN_INCSNZW_FR, IP2K_INSN_MULSW_FR + , IP2K_INSN_MULUW_FR, IP2K_INSN_DECSNZ_FR, IP2K_INSN_DECSNZW_FR, IP2K_INSN_SUBCW_FR + , IP2K_INSN_SUBCFR_W, IP2K_INSN_POP_FR, IP2K_INSN_PUSH_FR, IP2K_INSN_CSEW_FR + , IP2K_INSN_CSNEW_FR, IP2K_INSN_INCSZ_FR, IP2K_INSN_INCSZW_FR, IP2K_INSN_SWAP_FR + , IP2K_INSN_SWAPW_FR, IP2K_INSN_RL_FR, IP2K_INSN_RLW_FR, IP2K_INSN_RR_FR + , IP2K_INSN_RRW_FR, IP2K_INSN_DECSZ_FR, IP2K_INSN_DECSZW_FR, IP2K_INSN_INC_FR + , IP2K_INSN_INCW_FR, IP2K_INSN_NOT_FR, IP2K_INSN_NOTW_FR, IP2K_INSN_TEST_FR + , IP2K_INSN_MOVW_L, IP2K_INSN_MOVFR_W, IP2K_INSN_MOVW_FR, IP2K_INSN_ADDFR_W + , IP2K_INSN_ADDW_FR, IP2K_INSN_XORFR_W, IP2K_INSN_XORW_FR, IP2K_INSN_ANDFR_W + , IP2K_INSN_ANDW_FR, IP2K_INSN_ORFR_W, IP2K_INSN_ORW_FR, IP2K_INSN_DEC_FR + , IP2K_INSN_DECW_FR, IP2K_INSN_SUBFR_W, IP2K_INSN_SUBW_FR, IP2K_INSN_CLR_FR + , IP2K_INSN_CMPW_FR, IP2K_INSN_SPEED, IP2K_INSN_IREADI, IP2K_INSN_IWRITEI + , IP2K_INSN_FREAD, IP2K_INSN_FWRITE, IP2K_INSN_IREAD, IP2K_INSN_IWRITE + , IP2K_INSN_PAGE, IP2K_INSN_SYSTEM, IP2K_INSN_RETI, IP2K_INSN_RET + , IP2K_INSN_INT, IP2K_INSN_BREAKX, IP2K_INSN_CWDT, IP2K_INSN_FERASE + , IP2K_INSN_RETNP, IP2K_INSN_BREAK, IP2K_INSN_NOP +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID IP2K_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) IP2K_INSN_NOP + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_imm8; + long f_reg; + long f_addr16cjp; + long f_dir; + long f_bitno; + long f_op3; + long f_op4; + long f_op4mid; + long f_op6; + long f_op8; + long f_op6_10low; + long f_op6_7low; + long f_reti3; + long f_skipb; + long f_page3; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* IP2K_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-asm.c b/external/gpl3/gdb/dist/opcodes/iq2000-asm.c new file mode 100644 index 000000000000..13f1cd369980 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-asm.c @@ -0,0 +1,867 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +#include "safe-ctype.h" + +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +/* Special check to ensure that instruction exists for given machine. */ + +int +iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int machs = cd->machs; + + return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0; +} + +static int +iq2000_cgen_isa_register (const char **strp) +{ + int len; + int ch1, ch2; + + if (**strp == 'r' || **strp == 'R') + { + len = strlen (*strp); + if (len == 2) + { + ch1 = (*strp)[1]; + if ('0' <= ch1 && ch1 <= '9') + return 1; + } + else if (len == 3) + { + ch1 = (*strp)[1]; + ch2 = (*strp)[2]; + if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) + return 1; + if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) + return 1; + } + } + if (**strp == '%' + && TOLOWER ((*strp)[1]) != 'l' + && TOLOWER ((*strp)[1]) != 'h') + return 1; + return 0; +} + +/* Handle negated literal. */ + +static const char * +parse_mimm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + + /* Verify this isn't a register. */ + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = (-value) & 0xFFFF0000; + + if (x != 0 && x != (long) 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (-value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle signed/unsigned literal. */ + +static const char * +parse_imm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = value & 0xFFFF0000; + + if (x != 0 && x != (long) 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle iq10 21-bit jmp offset. */ + +static const char * +parse_jtargq10 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int reloc ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, + bfd_vma *valuep) +{ + const char *errmsg; + bfd_vma value; + enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, + & result_type, & value); + if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* Check value is within 23-bits + (remembering that 2-bit shift right will occur). */ + if (value > 0x7fffff) + return _("21-bit offset out of range"); + } + *valuep = (value & 0x7FFFFF); + return errmsg; +} + +/* Handle high(). */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* If value has top-bit of %lo on, then it will + sign-propagate and so we compensate by adding + 1 to the resultant %hi value. */ + if (value & 0x8000) + value += 0x10000; + value >>= 16; + value &= 0xffff; + } + *valuep = value; + + return errmsg; + } + + /* We add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate. */ + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + + value &= 0xffff; + *valuep = value; + + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a negated signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_mlo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (-value) & 0xffff; + *valuep = value; + return errmsg; + } + + return parse_mimm (cd, strp, opindex, valuep); +} + +/* -- */ + +const char * iq2000_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +iq2000_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND__INDEX, (unsigned long *) (& fields->f_index)); + break; + case IQ2000_OPERAND_BASE : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value); + fields->f_imm = value; + } + break; + case IQ2000_OPERAND_BITNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BITNUM, (unsigned long *) (& fields->f_rt)); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BYTECOUNT, (unsigned long *) (& fields->f_bytecount)); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Y, (unsigned long *) (& fields->f_cam_y)); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Z, (unsigned long *) (& fields->f_cam_z)); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3FUNC, (unsigned long *) (& fields->f_cm_3func)); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3Z, (unsigned long *) (& fields->f_cm_3z)); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4FUNC, (unsigned long *) (& fields->f_cm_4func)); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4Z, (unsigned long *) (& fields->f_cm_4z)); + break; + case IQ2000_OPERAND_COUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_COUNT, (unsigned long *) (& fields->f_count)); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, (unsigned long *) (& fields->f_excode)); + break; + case IQ2000_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, (unsigned long *) (& fields->f_imm)); + break; + case IQ2000_OPERAND_IMM : + errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, (unsigned long *) (& fields->f_imm)); + break; + case IQ2000_OPERAND_JMPTARG : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value); + fields->f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + bfd_vma value = 0; + errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value); + fields->f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, IQ2000_OPERAND_LO16, (unsigned long *) (& fields->f_imm)); + break; + case IQ2000_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASK, (unsigned long *) (& fields->f_mask)); + break; + case IQ2000_OPERAND_MASKL : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKL, (unsigned long *) (& fields->f_maskl)); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKQ10, (unsigned long *) (& fields->f_maskq10)); + break; + case IQ2000_OPERAND_MASKR : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKR, (unsigned long *) (& fields->f_rs)); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = parse_mlo16 (cd, strp, IQ2000_OPERAND_MLO16, (unsigned long *) (& fields->f_imm)); + break; + case IQ2000_OPERAND_OFFSET : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value); + fields->f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rs); + break; + case IQ2000_OPERAND_RD_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rt); + break; + case IQ2000_OPERAND_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt_rs); + break; + case IQ2000_OPERAND_SHAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_SHAMT, (unsigned long *) (& fields->f_shamt)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const iq2000_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +iq2000_cgen_init_asm (CGEN_CPU_DESC cd) +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->parse_handlers = & iq2000_cgen_parse_handlers[0]; + cd->parse_operand = iq2000_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by iq2000_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +iq2000_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-desc.c b/external/gpl3/gdb/dist/opcodes/iq2000-desc.c new file mode 100644 index 000000000000..6ea18c70aaa5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-desc.c @@ -0,0 +1,2182 @@ +/* CPU data for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "iq2000", MACH_IQ2000 }, + { "iq10", MACH_IQ10 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "iq2000", ISA_IQ2000 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, + { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, + { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] }, + { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] }, + { "USES-RD", &bool_attr[0], &bool_attr[0] }, + { "USES-RS", &bool_attr[0], &bool_attr[0] }, + { "USES-RT", &bool_attr[0], &bool_attr[0] }, + { "USES-R31", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA iq2000_cgen_isa_table[] = { + { "iq2000", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH iq2000_cgen_mach_table[] = { + { "iq2000", "iq2000", MACH_IQ2000, 0 }, + { "iq10", "iq10", MACH_IQ10, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "%0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "%1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "%2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "%3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "%4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "%5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "%6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "%7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "%8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "%9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "%10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "%11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "%12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "%13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "%14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "%15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "%16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "%17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "%18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "%19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "%20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "%21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "%22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "%23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "%24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "%25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "%26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "%27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "%28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "%29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "%30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "%31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD iq2000_cgen_opval_gr_names = +{ + & iq2000_cgen_opval_gr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY iq2000_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & iq2000_cgen_ifld_table[0]; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ + +static void +iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & iq2000_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & iq2000_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = iq2000_cgen_rebuild_tables; + iq2000_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +iq2000_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-desc.h b/external/gpl3/gdb/dist/opcodes/iq2000-desc.h new file mode 100644 index 000000000000..2347329d440b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-desc.h @@ -0,0 +1,347 @@ +/* CPU data header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef IQ2000_CPU_H +#define IQ2000_CPU_H + +#define CGEN_ARCH iq2000 + +/* Given symbol S, return iq2000_cgen_. */ +#define CGEN_SYM(s) iq2000##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_IQ2000BF +#define HAVE_CPU_IQ10BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1 + , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3 + , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5 + , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7 + , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9 + , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11 + , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13 + , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15 + , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17 + , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19 + , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21 + , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23 + , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25 + , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27 + , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29 + , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31 +} GR_NAMES; + +/* Enum declaration for primary opcodes. */ +typedef enum opcodes { + OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3 + , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7 + , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11 + , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15 + , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19 + , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23 + , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27 + , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31 + , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36 + , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41 + , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47 + , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63 +} OPCODES; + +/* Enum declaration for iq10-only primary opcodes. */ +typedef enum q10_opcodes { + OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47 + , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63 +} Q10_OPCODES; + +/* Enum declaration for branch sub-opcodes. */ +typedef enum regimm_functions { + FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3 + , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7 + , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16 + , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20 + , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23 +} REGIMM_FUNCTIONS; + +/* Enum declaration for function sub-opcodes. */ +typedef enum functions { + FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3 + , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7 + , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12 + , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33 + , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37 + , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42 + , FUNC_SLTU = 43, FUNC_MRGB = 45 +} FUNCTIONS; + +/* Enum declaration for iq10-only special function sub-opcodes. */ +typedef enum q10s_functions { + FUNC10_YIELD = 14, FUNC10_CNT1S = 46 +} Q10S_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_functions { + FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3 + , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7 + , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12 + , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18 + , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33 + , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37 + , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41 + , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0 + , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8 + , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20 + , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29 + , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35 + , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41 + , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48 + , FUNC10_CM32SA = 56 +} COP_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_4functions { + FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6 +} COP_CM128_4FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_3functions { + FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7 +} COP_CM128_3FUNCTIONS; + +/* Enum declaration for iq10 coprocessor sub-opcodes. */ +typedef enum cop2_functions { + FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3 + , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5 + , FUNC10_WBI = 6, FUNC10_WBIU = 7 +} COP2_FUNCTIONS; + +/* Enum declaration for iq10 coprocessor cam sub-opcodes. */ +typedef enum cop3_cam_functions { + FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19 +} COP3_CAM_FUNCTIONS; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_IQ2000, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for iq2000 ifield types. */ +typedef enum ifield_type { + IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS + , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP + , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM + , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG + , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT + , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL + , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19 + , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z + , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z + , IQ2000_F_CM_4Z, IQ2000_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) IQ2000_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for iq2000 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for iq2000 operand types. */ +typedef enum cgen_operand_type { + IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD + , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT + , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG + , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT + , IQ2000_OPERAND__INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y + , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z + , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM + , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10 + , IQ2000_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 32 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY + , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS + , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_YIELD_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_LOAD_DELAY)) != 0) +#define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNSUPPORTED)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RD)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RS)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_RT)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_R31)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld iq2000_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD iq2000_cgen_opval_gr_names; + +extern const CGEN_HW_ENTRY iq2000_cgen_hw_table[]; + + + +#endif /* IQ2000_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-dis.c b/external/gpl3/gdb/dist/opcodes/iq2000-dis.c new file mode 100644 index 000000000000..a4f27fadb921 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-dis.c @@ -0,0 +1,610 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + + +void iq2000_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +iq2000_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + print_normal (cd, info, fields->f_index, 0, pc, length); + break; + case IQ2000_OPERAND_BASE : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0); + break; + case IQ2000_OPERAND_BASEOFF : + print_address (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_BITNUM : + print_normal (cd, info, fields->f_rt, 0, pc, length); + break; + case IQ2000_OPERAND_BYTECOUNT : + print_normal (cd, info, fields->f_bytecount, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Y : + print_normal (cd, info, fields->f_cam_y, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Z : + print_normal (cd, info, fields->f_cam_z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3FUNC : + print_normal (cd, info, fields->f_cm_3func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3Z : + print_normal (cd, info, fields->f_cm_3z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4FUNC : + print_normal (cd, info, fields->f_cm_4func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4Z : + print_normal (cd, info, fields->f_cm_4z, 0, pc, length); + break; + case IQ2000_OPERAND_COUNT : + print_normal (cd, info, fields->f_count, 0, pc, length); + break; + case IQ2000_OPERAND_EXECODE : + print_normal (cd, info, fields->f_excode, 0, pc, length); + break; + case IQ2000_OPERAND_HI16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_IMM : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_JMPTARG : + print_address (cd, info, fields->f_jtarg, 0|(1<f_jtargq10, 0|(1<f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_MASK : + print_normal (cd, info, fields->f_mask, 0, pc, length); + break; + case IQ2000_OPERAND_MASKL : + print_normal (cd, info, fields->f_maskl, 0, pc, length); + break; + case IQ2000_OPERAND_MASKQ10 : + print_normal (cd, info, fields->f_maskq10, 0, pc, length); + break; + case IQ2000_OPERAND_MASKR : + print_normal (cd, info, fields->f_rs, 0, pc, length); + break; + case IQ2000_OPERAND_MLO16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_OFFSET : + print_address (cd, info, fields->f_offset, 0|(1<f_rd, 0); + break; + case IQ2000_OPERAND_RD_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<f_rd_rt, 0|(1<f_rs, 0); + break; + case IQ2000_OPERAND_RT : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0); + break; + case IQ2000_OPERAND_RT_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<f_shamt, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const iq2000_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +iq2000_cgen_init_dis (CGEN_CPU_DESC cd) +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->print_handlers = & iq2000_cgen_print_handlers[0]; + cd->print_operand = iq2000_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_iq2000 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_iq2000 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + iq2000_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-ibld.c b/external/gpl3/gdb/dist/opcodes/iq2000-ibld.c new file mode 100644 index 000000000000..8f5673309fa6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-ibld.c @@ -0,0 +1,1380 @@ +/* Instruction building/extraction support for iq2000. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * iq2000_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +iq2000_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BASE : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BASEOFF : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BITNUM : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = insert_normal (cd, fields->f_bytecount, 0, 0, 7, 8, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = insert_normal (cd, fields->f_cam_y, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = insert_normal (cd, fields->f_cam_z, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = insert_normal (cd, fields->f_cm_3func, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = insert_normal (cd, fields->f_cm_3z, 0, 0, 1, 2, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = insert_normal (cd, fields->f_cm_4func, 0, 0, 5, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = insert_normal (cd, fields->f_cm_4z, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_COUNT : + errmsg = insert_normal (cd, fields->f_count, 0, 0, 15, 7, 32, total_length, buffer); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer); + break; + case IQ2000_OPERAND_HI16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_IMM : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value = fields->f_jtarg; + value = ((USI) (((value) & (262143))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_jtargq10; + value = ((USI) (((value) & (8388607))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASK : + errmsg = insert_normal (cd, fields->f_mask, 0, 0, 9, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKL : + errmsg = insert_normal (cd, fields->f_maskl, 0, 0, 4, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = insert_normal (cd, fields->f_maskq10, 0, 0, 10, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKR : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_OFFSET : + { + long value = fields->f_offset; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_rd, 0, 0, 15, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RD_RS : + { +{ + FLD (f_rd) = FLD (f_rd_rs); + FLD (f_rs) = FLD (f_rd_rs); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RD_RT : + { +{ + FLD (f_rd) = FLD (f_rd_rt); + FLD (f_rt) = FLD (f_rd_rt); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RS : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT_RS : + { +{ + FLD (f_rt) = FLD (f_rt_rs); + FLD (f_rs) = FLD (f_rt_rs); +} + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_SHAMT : + errmsg = insert_normal (cd, fields->f_shamt, 0, 0, 10, 5, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int iq2000_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +iq2000_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index); + break; + case IQ2000_OPERAND_BASE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_BITNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_BYTECOUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & fields->f_bytecount); + break; + case IQ2000_OPERAND_CAM_Y : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cam_y); + break; + case IQ2000_OPERAND_CAM_Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cam_z); + break; + case IQ2000_OPERAND_CM_3FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cm_3func); + break; + case IQ2000_OPERAND_CM_3Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_cm_3z); + break; + case IQ2000_OPERAND_CM_4FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 4, 32, total_length, pc, & fields->f_cm_4func); + break; + case IQ2000_OPERAND_CM_4Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cm_4z); + break; + case IQ2000_OPERAND_COUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 7, 32, total_length, pc, & fields->f_count); + break; + case IQ2000_OPERAND_EXECODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode); + break; + case IQ2000_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_IMM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_MASK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 4, 32, total_length, pc, & fields->f_mask); + break; + case IQ2000_OPERAND_MASKL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_maskl); + break; + case IQ2000_OPERAND_MASKQ10 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_maskq10); + break; + case IQ2000_OPERAND_MASKR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_MLO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_OFFSET : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_RD_RT : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; +{ + FLD (f_rd_rt) = FLD (f_rt); +} + } + break; + case IQ2000_OPERAND_RS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_SHAMT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_shamt); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const iq2000_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const iq2000_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int iq2000_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma iq2000_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +iq2000_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +iq2000_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void iq2000_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void iq2000_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +iq2000_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +iq2000_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case IQ2000_OPERAND__INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +iq2000_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & iq2000_cgen_insert_handlers[0]; + cd->extract_handlers = & iq2000_cgen_extract_handlers[0]; + + cd->insert_operand = iq2000_cgen_insert_operand; + cd->extract_operand = iq2000_cgen_extract_operand; + + cd->get_int_operand = iq2000_cgen_get_int_operand; + cd->set_int_operand = iq2000_cgen_set_int_operand; + cd->get_vma_operand = iq2000_cgen_get_vma_operand; + cd->set_vma_operand = iq2000_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-opc.c b/external/gpl3/gdb/dist/opcodes/iq2000-opc.c new file mode 100644 index 000000000000..dbce4c0cc84d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-opc.c @@ -0,0 +1,3457 @@ +/* Instruction opcode table for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ram ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000020, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_5) }, { F (F_MASKL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sll ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sllv2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sra2 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbv ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgez ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1f07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lui ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_syscall ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_EXCODE) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc0f ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfc0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10_11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_chkhdr ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lulck ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pkrlr1 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { F (F_INDEX) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rfe ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_25) }, { F (F_24_19) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_j ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RSRVD) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq10 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq102 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jq10 ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalq10 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_avail ATTRIBUTE_UNUSED = { + 32, 32, 0xffff07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000700, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cam36 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007c0, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32and ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32rd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007fc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria4 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007f8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ctc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) IQ2000_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x20 } + }, +/* add $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x20 } + }, +/* addi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x20000000 } + }, +/* addi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x20000000 } + }, +/* addiu ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x24000000 } + }, +/* addiu $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x24000000 } + }, +/* addu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x21 } + }, +/* addu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x21 } + }, +/* ado16 ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x29 } + }, +/* ado16 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x29 } + }, +/* and ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x24 } + }, +/* and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x24 } + }, +/* andi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x30000000 } + }, +/* andi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x30000000 } + }, +/* andoi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0xb0000000 } + }, +/* andoi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0xb0000000 } + }, +/* nor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x27 } + }, +/* nor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x27 } + }, +/* or ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x25 } + }, +/* or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x25 } + }, +/* ori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x34000000 } + }, +/* ori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x34000000 } + }, +/* ram $rd,$rt,$shamt,$maskl,$maskr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), ',', OP (MASKL), ',', OP (MASKR), 0 } }, + & ifmt_ram, { 0x9c000000 } + }, +/* sll $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x0 } + }, +/* sllv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x4 } + }, +/* sllv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x4 } + }, +/* slmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x1 } + }, +/* slmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x1 } + }, +/* slt ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2a } + }, +/* slt $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2a } + }, +/* slti ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x28000000 } + }, +/* slti $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x28000000 } + }, +/* sltiu ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x2c000000 } + }, +/* sltiu $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x2c000000 } + }, +/* sltu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2b } + }, +/* sltu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2b } + }, +/* sra ${rd-rt},$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (SHAMT), 0 } }, + & ifmt_sra2, { 0x3 } + }, +/* sra $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x3 } + }, +/* srav ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x7 } + }, +/* srav $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x7 } + }, +/* srl $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x2 } + }, +/* srlv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x6 } + }, +/* srlv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x6 } + }, +/* srmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x5 } + }, +/* srmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x5 } + }, +/* sub ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x22 } + }, +/* sub $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x22 } + }, +/* subu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x23 } + }, +/* subu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x23 } + }, +/* xor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x26 } + }, +/* xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x26 } + }, +/* xori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x38000000 } + }, +/* xori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x38000000 } + }, +/* bbi $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x70000000 } + }, +/* bbin $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x78000000 } + }, +/* bbv $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x74000000 } + }, +/* bbvn $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x7c000000 } + }, +/* beq $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x10000000 } + }, +/* beql $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x50000000 } + }, +/* bgez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4010000 } + }, +/* bgezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4110000 } + }, +/* bgezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4130000 } + }, +/* bgezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4030000 } + }, +/* bltz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4000000 } + }, +/* bltzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4020000 } + }, +/* bltzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4100000 } + }, +/* bltzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4120000 } + }, +/* bmb0 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x60000000 } + }, +/* bmb1 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x64000000 } + }, +/* bmb2 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x68000000 } + }, +/* bmb3 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x6c000000 } + }, +/* bne $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x14000000 } + }, +/* bnel $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x54000000 } + }, +/* jalr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x9 } + }, +/* jr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0x8 } + }, +/* lb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x80000000 } + }, +/* lbu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x90000000 } + }, +/* lh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x84000000 } + }, +/* lhu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x94000000 } + }, +/* lui $rt,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (HI16), 0 } }, + & ifmt_lui, { 0x3c000000 } + }, +/* lw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x8c000000 } + }, +/* sb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa0000000 } + }, +/* sh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa4000000 } + }, +/* sw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xac000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xd } + }, +/* syscall */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xc } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xfc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xfc000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x1c000000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x5c000000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x18000000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x58000000 } + }, +/* mrgb $rd,$rs,$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb2, { 0x2d } + }, +/* bctxt $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bc0f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41000000 } + }, +/* bc0fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41020000 } + }, +/* bc3f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d000000 } + }, +/* bc3fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d020000 } + }, +/* bc0t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41010000 } + }, +/* bc0tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41030000 } + }, +/* bc3t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d010000 } + }, +/* bc3tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d030000 } + }, +/* cfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40400000 } + }, +/* cfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44400000 } + }, +/* cfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48400000 } + }, +/* cfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c400000 } + }, +/* chkhdr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4d200000 } + }, +/* ctc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40c00000 } + }, +/* ctc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44c00000 } + }, +/* ctc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48c00000 } + }, +/* ctc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4cc00000 } + }, +/* jcr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0xa } + }, +/* luc32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200003 } + }, +/* luc32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200007 } + }, +/* luc64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000b } + }, +/* luc64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000f } + }, +/* luk $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200008 } + }, +/* lulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200004 } + }, +/* lum32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200002 } + }, +/* lum32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200006 } + }, +/* lum64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000a } + }, +/* lum64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000e } + }, +/* lur $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200001 } + }, +/* lurl $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200005 } + }, +/* luulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200000 } + }, +/* mfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40000000 } + }, +/* mfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44000000 } + }, +/* mfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48000000 } + }, +/* mfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c000000 } + }, +/* mtc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40800000 } + }, +/* mtc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44800000 } + }, +/* mtc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48800000 } + }, +/* mtc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c800000 } + }, +/* pkrl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200007 } + }, +/* pkrlr1 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fa00000 } + }, +/* pkrlr30 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fe00000 } + }, +/* rb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200004 } + }, +/* rbr1 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f000000 } + }, +/* rbr30 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f400000 } + }, +/* rfe */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_rfe, { 0x42000010 } + }, +/* rx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200006 } + }, +/* rxr1 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f800000 } + }, +/* rxr30 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fc00000 } + }, +/* sleep */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xe } + }, +/* srrd $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200010 } + }, +/* srrdl $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200014 } + }, +/* srulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200016 } + }, +/* srwr $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200011 } + }, +/* srwru $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200015 } + }, +/* trapqfl */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200008 } + }, +/* trapqne */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200009 } + }, +/* traprel $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x4c20000a } + }, +/* wb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200000 } + }, +/* wbu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200001 } + }, +/* wbr1 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e000000 } + }, +/* wbr1u $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e200000 } + }, +/* wbr30 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e400000 } + }, +/* wbr30u $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e600000 } + }, +/* wx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200002 } + }, +/* wxu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200003 } + }, +/* wxr1 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e800000 } + }, +/* wxr1u $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ea00000 } + }, +/* wxr30 $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ec00000 } + }, +/* wxr30u $rt,$_index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (_INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ee00000 } + }, +/* ldw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xc0000000 } + }, +/* sdw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xe0000000 } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0x8000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0xc000000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xb4000000 } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0x3c000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0x3c000000 } + }, +/* mrgb $rd,$rs,$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq10, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq102, { 0x2d } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0x8000000 } + }, +/* jal $rt,$jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (JMPTARG), 0 } }, + & ifmt_jalq10, { 0xc000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0xc1f0000 } + }, +/* bbil $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf0000000 } + }, +/* bbinl $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf8000000 } + }, +/* bbvl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xf4000000 } + }, +/* bbvnl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xfc000000 } + }, +/* bgtzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4150000 } + }, +/* bgtzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4170000 } + }, +/* blezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4140000 } + }, +/* blezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4160000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4050000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4070000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4040000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x18000000 } + }, +/* bmbl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x58000000 } + }, +/* bri $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4080000 } + }, +/* brv $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4090000 } + }, +/* bctx $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x40c0000 } + }, +/* yield */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xe } + }, +/* crc32 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000014 } + }, +/* crc32b $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000015 } + }, +/* cnt1s $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_add, { 0x2e } + }, +/* avail $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000024 } + }, +/* free $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000025 } + }, +/* tstod $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000027 } + }, +/* cmphdr $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c00002c } + }, +/* mcid $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000020 } + }, +/* dba $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000022 } + }, +/* dbd $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000021 } + }, +/* dpwt $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000023 } + }, +/* chkhdr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000026 } + }, +/* rba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000008 } + }, +/* rbal $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000009 } + }, +/* rbar $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00000a } + }, +/* wba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000010 } + }, +/* wbau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000011 } + }, +/* wbac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000012 } + }, +/* rbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000200 } + }, +/* rbil $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000300 } + }, +/* rbir $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000100 } + }, +/* wbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000600 } + }, +/* wbic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000500 } + }, +/* wbiu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000700 } + }, +/* pkrli $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000000 } + }, +/* pkrlih $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000200 } + }, +/* pkrliu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000100 } + }, +/* pkrlic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000300 } + }, +/* pkrla $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000028 } + }, +/* pkrlau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000029 } + }, +/* pkrlah $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002a } + }, +/* pkrlac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002b } + }, +/* lock $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000001 } + }, +/* unlk $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000003 } + }, +/* swrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000004 } + }, +/* swrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000005 } + }, +/* swwr $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000006 } + }, +/* swwru $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000007 } + }, +/* dwrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000c } + }, +/* dwrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000d } + }, +/* cam36 $rd,$rt,${cam-z},${cam-y} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Z), ',', OP (CAM_Y), 0 } }, + & ifmt_cam36, { 0x4c000400 } + }, +/* cam72 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000440 } + }, +/* cam144 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000480 } + }, +/* cam288 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c0004c0 } + }, +/* cm32and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000ab } + }, +/* cm32andn $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a3 } + }, +/* cm32or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000aa } + }, +/* cm32ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000b0 } + }, +/* cm32rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a1 } + }, +/* cm32ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a4 } + }, +/* cm32rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000a0 } + }, +/* cm32sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000b8 } + }, +/* cm32sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a9 } + }, +/* cm32si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000ac } + }, +/* cm32ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a8 } + }, +/* cm32xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a2 } + }, +/* cm64clr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000085 } + }, +/* cm64ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000090 } + }, +/* cm64rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000081 } + }, +/* cm64ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000084 } + }, +/* cm64ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000094 } + }, +/* cm64rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000080 } + }, +/* cm64sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000098 } + }, +/* cm64sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000089 } + }, +/* cm64si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c00008c } + }, +/* cm64sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009c } + }, +/* cm64ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000088 } + }, +/* cm128ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000095 } + }, +/* cm128ria3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000090 } + }, +/* cm128ria4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b0 } + }, +/* cm128sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009d } + }, +/* cm128sia3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000098 } + }, +/* cm128sia4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b8 } + }, +/* cm128vsa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a6 } + }, +/* cfc $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000000 } + }, +/* ctc $rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), 0 } }, + & ifmt_ctc, { 0x4c000002 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_li ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_move ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lh_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lw_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_add ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_addu ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_and ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_j ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_or ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sll ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_slt ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sltu ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sra ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_srl ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sub ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_subu ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_xor ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldw_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sdw_base_0 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_avail ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam36 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam72 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam144 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam288 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32read ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64read ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32mlog ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32and ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32andn ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32or ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ra ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ri ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sa ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32si ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ss ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32xor ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64clr ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ra ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ri ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ria2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sa ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64si ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sia2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ss ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria4 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia2 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia4 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cmphdr ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dbd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m2_dbd ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dpwt ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_free ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_lock ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrla ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlac ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlah ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlau ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrli ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlic ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlih ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrliu ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rba ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbal ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbar ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbil ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbir ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwru ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_tstod ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_unlk ATTRIBUTE_UNUSED = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wba ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbac ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbau ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbic ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbiu ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) IQ2000_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE iq2000_cgen_macro_insn_table[] = +{ +/* nop */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + iq2000_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & iq2000_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + iq2000_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/iq2000-opc.h b/external/gpl3/gdb/dist/opcodes/iq2000-opc.h new file mode 100644 index 000000000000..c8fb14fc6951 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/iq2000-opc.h @@ -0,0 +1,181 @@ +/* Instruction opcode header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef IQ2000_OPC_H +#define IQ2000_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) + +/* following activates check beyond hashing since some iq2000 and iq10 + instructions have same mnemonics but different functionality. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +/* -- asm.c */ +/* Enum declaration for iq2000 instruction types. */ +typedef enum cgen_insn_type { + IQ2000_INSN_INVALID, IQ2000_INSN_ADD2, IQ2000_INSN_ADD, IQ2000_INSN_ADDI2 + , IQ2000_INSN_ADDI, IQ2000_INSN_ADDIU2, IQ2000_INSN_ADDIU, IQ2000_INSN_ADDU2 + , IQ2000_INSN_ADDU, IQ2000_INSN_ADO162, IQ2000_INSN_ADO16, IQ2000_INSN_AND2 + , IQ2000_INSN_AND, IQ2000_INSN_ANDI2, IQ2000_INSN_ANDI, IQ2000_INSN_ANDOI2 + , IQ2000_INSN_ANDOI, IQ2000_INSN_NOR2, IQ2000_INSN_NOR, IQ2000_INSN_OR2 + , IQ2000_INSN_OR, IQ2000_INSN_ORI2, IQ2000_INSN_ORI, IQ2000_INSN_RAM + , IQ2000_INSN_SLL, IQ2000_INSN_SLLV2, IQ2000_INSN_SLLV, IQ2000_INSN_SLMV2 + , IQ2000_INSN_SLMV, IQ2000_INSN_SLT2, IQ2000_INSN_SLT, IQ2000_INSN_SLTI2 + , IQ2000_INSN_SLTI, IQ2000_INSN_SLTIU2, IQ2000_INSN_SLTIU, IQ2000_INSN_SLTU2 + , IQ2000_INSN_SLTU, IQ2000_INSN_SRA2, IQ2000_INSN_SRA, IQ2000_INSN_SRAV2 + , IQ2000_INSN_SRAV, IQ2000_INSN_SRL, IQ2000_INSN_SRLV2, IQ2000_INSN_SRLV + , IQ2000_INSN_SRMV2, IQ2000_INSN_SRMV, IQ2000_INSN_SUB2, IQ2000_INSN_SUB + , IQ2000_INSN_SUBU2, IQ2000_INSN_SUBU, IQ2000_INSN_XOR2, IQ2000_INSN_XOR + , IQ2000_INSN_XORI2, IQ2000_INSN_XORI, IQ2000_INSN_BBI, IQ2000_INSN_BBIN + , IQ2000_INSN_BBV, IQ2000_INSN_BBVN, IQ2000_INSN_BEQ, IQ2000_INSN_BEQL + , IQ2000_INSN_BGEZ, IQ2000_INSN_BGEZAL, IQ2000_INSN_BGEZALL, IQ2000_INSN_BGEZL + , IQ2000_INSN_BLTZ, IQ2000_INSN_BLTZL, IQ2000_INSN_BLTZAL, IQ2000_INSN_BLTZALL + , IQ2000_INSN_BMB0, IQ2000_INSN_BMB1, IQ2000_INSN_BMB2, IQ2000_INSN_BMB3 + , IQ2000_INSN_BNE, IQ2000_INSN_BNEL, IQ2000_INSN_JALR, IQ2000_INSN_JR + , IQ2000_INSN_LB, IQ2000_INSN_LBU, IQ2000_INSN_LH, IQ2000_INSN_LHU + , IQ2000_INSN_LUI, IQ2000_INSN_LW, IQ2000_INSN_SB, IQ2000_INSN_SH + , IQ2000_INSN_SW, IQ2000_INSN_BREAK, IQ2000_INSN_SYSCALL, IQ2000_INSN_ANDOUI + , IQ2000_INSN_ANDOUI2, IQ2000_INSN_ORUI2, IQ2000_INSN_ORUI, IQ2000_INSN_BGTZ + , IQ2000_INSN_BGTZL, IQ2000_INSN_BLEZ, IQ2000_INSN_BLEZL, IQ2000_INSN_MRGB + , IQ2000_INSN_MRGB2, IQ2000_INSN_BCTXT, IQ2000_INSN_BC0F, IQ2000_INSN_BC0FL + , IQ2000_INSN_BC3F, IQ2000_INSN_BC3FL, IQ2000_INSN_BC0T, IQ2000_INSN_BC0TL + , IQ2000_INSN_BC3T, IQ2000_INSN_BC3TL, IQ2000_INSN_CFC0, IQ2000_INSN_CFC1 + , IQ2000_INSN_CFC2, IQ2000_INSN_CFC3, IQ2000_INSN_CHKHDR, IQ2000_INSN_CTC0 + , IQ2000_INSN_CTC1, IQ2000_INSN_CTC2, IQ2000_INSN_CTC3, IQ2000_INSN_JCR + , IQ2000_INSN_LUC32, IQ2000_INSN_LUC32L, IQ2000_INSN_LUC64, IQ2000_INSN_LUC64L + , IQ2000_INSN_LUK, IQ2000_INSN_LULCK, IQ2000_INSN_LUM32, IQ2000_INSN_LUM32L + , IQ2000_INSN_LUM64, IQ2000_INSN_LUM64L, IQ2000_INSN_LUR, IQ2000_INSN_LURL + , IQ2000_INSN_LUULCK, IQ2000_INSN_MFC0, IQ2000_INSN_MFC1, IQ2000_INSN_MFC2 + , IQ2000_INSN_MFC3, IQ2000_INSN_MTC0, IQ2000_INSN_MTC1, IQ2000_INSN_MTC2 + , IQ2000_INSN_MTC3, IQ2000_INSN_PKRL, IQ2000_INSN_PKRLR1, IQ2000_INSN_PKRLR30 + , IQ2000_INSN_RB, IQ2000_INSN_RBR1, IQ2000_INSN_RBR30, IQ2000_INSN_RFE + , IQ2000_INSN_RX, IQ2000_INSN_RXR1, IQ2000_INSN_RXR30, IQ2000_INSN_SLEEP + , IQ2000_INSN_SRRD, IQ2000_INSN_SRRDL, IQ2000_INSN_SRULCK, IQ2000_INSN_SRWR + , IQ2000_INSN_SRWRU, IQ2000_INSN_TRAPQFL, IQ2000_INSN_TRAPQNE, IQ2000_INSN_TRAPREL + , IQ2000_INSN_WB, IQ2000_INSN_WBU, IQ2000_INSN_WBR1, IQ2000_INSN_WBR1U + , IQ2000_INSN_WBR30, IQ2000_INSN_WBR30U, IQ2000_INSN_WX, IQ2000_INSN_WXU + , IQ2000_INSN_WXR1, IQ2000_INSN_WXR1U, IQ2000_INSN_WXR30, IQ2000_INSN_WXR30U + , IQ2000_INSN_LDW, IQ2000_INSN_SDW, IQ2000_INSN_J, IQ2000_INSN_JAL + , IQ2000_INSN_BMB, IQ2000_INSN_ANDOUI_Q10, IQ2000_INSN_ANDOUI2_Q10, IQ2000_INSN_ORUI_Q10 + , IQ2000_INSN_ORUI2_Q10, IQ2000_INSN_MRGBQ10, IQ2000_INSN_MRGBQ102, IQ2000_INSN_JQ10 + , IQ2000_INSN_JALQ10, IQ2000_INSN_JALQ10_2, IQ2000_INSN_BBIL, IQ2000_INSN_BBINL + , IQ2000_INSN_BBVL, IQ2000_INSN_BBVNL, IQ2000_INSN_BGTZAL, IQ2000_INSN_BGTZALL + , IQ2000_INSN_BLEZAL, IQ2000_INSN_BLEZALL, IQ2000_INSN_BGTZ_Q10, IQ2000_INSN_BGTZL_Q10 + , IQ2000_INSN_BLEZ_Q10, IQ2000_INSN_BLEZL_Q10, IQ2000_INSN_BMB_Q10, IQ2000_INSN_BMBL + , IQ2000_INSN_BRI, IQ2000_INSN_BRV, IQ2000_INSN_BCTX, IQ2000_INSN_YIELD + , IQ2000_INSN_CRC32, IQ2000_INSN_CRC32B, IQ2000_INSN_CNT1S, IQ2000_INSN_AVAIL + , IQ2000_INSN_FREE, IQ2000_INSN_TSTOD, IQ2000_INSN_CMPHDR, IQ2000_INSN_MCID + , IQ2000_INSN_DBA, IQ2000_INSN_DBD, IQ2000_INSN_DPWT, IQ2000_INSN_CHKHDRQ10 + , IQ2000_INSN_RBA, IQ2000_INSN_RBAL, IQ2000_INSN_RBAR, IQ2000_INSN_WBA + , IQ2000_INSN_WBAU, IQ2000_INSN_WBAC, IQ2000_INSN_RBI, IQ2000_INSN_RBIL + , IQ2000_INSN_RBIR, IQ2000_INSN_WBI, IQ2000_INSN_WBIC, IQ2000_INSN_WBIU + , IQ2000_INSN_PKRLI, IQ2000_INSN_PKRLIH, IQ2000_INSN_PKRLIU, IQ2000_INSN_PKRLIC + , IQ2000_INSN_PKRLA, IQ2000_INSN_PKRLAU, IQ2000_INSN_PKRLAH, IQ2000_INSN_PKRLAC + , IQ2000_INSN_LOCK, IQ2000_INSN_UNLK, IQ2000_INSN_SWRD, IQ2000_INSN_SWRDL + , IQ2000_INSN_SWWR, IQ2000_INSN_SWWRU, IQ2000_INSN_DWRD, IQ2000_INSN_DWRDL + , IQ2000_INSN_CAM36, IQ2000_INSN_CAM72, IQ2000_INSN_CAM144, IQ2000_INSN_CAM288 + , IQ2000_INSN_CM32AND, IQ2000_INSN_CM32ANDN, IQ2000_INSN_CM32OR, IQ2000_INSN_CM32RA + , IQ2000_INSN_CM32RD, IQ2000_INSN_CM32RI, IQ2000_INSN_CM32RS, IQ2000_INSN_CM32SA + , IQ2000_INSN_CM32SD, IQ2000_INSN_CM32SI, IQ2000_INSN_CM32SS, IQ2000_INSN_CM32XOR + , IQ2000_INSN_CM64CLR, IQ2000_INSN_CM64RA, IQ2000_INSN_CM64RD, IQ2000_INSN_CM64RI + , IQ2000_INSN_CM64RIA2, IQ2000_INSN_CM64RS, IQ2000_INSN_CM64SA, IQ2000_INSN_CM64SD + , IQ2000_INSN_CM64SI, IQ2000_INSN_CM64SIA2, IQ2000_INSN_CM64SS, IQ2000_INSN_CM128RIA2 + , IQ2000_INSN_CM128RIA3, IQ2000_INSN_CM128RIA4, IQ2000_INSN_CM128SIA2, IQ2000_INSN_CM128SIA3 + , IQ2000_INSN_CM128SIA4, IQ2000_INSN_CM128VSA, IQ2000_INSN_CFC, IQ2000_INSN_CTC +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID IQ2000_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) IQ2000_INSN_CTC + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_opcode; + long f_rs; + long f_rt; + long f_rd; + long f_shamt; + long f_cp_op; + long f_cp_op_10; + long f_cp_grp; + long f_func; + long f_imm; + long f_rd_rs; + long f_rd_rt; + long f_rt_rs; + long f_jtarg; + long f_jtargq10; + long f_offset; + long f_count; + long f_bytecount; + long f_index; + long f_mask; + long f_maskq10; + long f_maskl; + long f_excode; + long f_rsrvd; + long f_10_11; + long f_24_19; + long f_5; + long f_10; + long f_25; + long f_cam_z; + long f_cam_y; + long f_cm_3func; + long f_cm_4func; + long f_cm_3z; + long f_cm_4z; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* IQ2000_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/lm32-asm.c b/external/gpl3/gdb/dist/opcodes/lm32-asm.c new file mode 100644 index 000000000000..31f4969dc6b4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-asm.c @@ -0,0 +1,757 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "lm32-desc.h" +#include "lm32-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +/* Handle signed/unsigned literal. */ + +static const char * +parse_imm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + unsigned long x = value & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (value & 0xFFFF); + } + return errmsg; +} + +/* Handle hi() */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (strncasecmp (*strp, "hi(", 3) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 3; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (value >> 16) & 0xffff; + *valuep = value; + + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle lo() */ + +static const char * +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (strncasecmp (*strp, "lo(", 3) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 3; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle gp() */ + +static const char * +parse_gp16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + if (strncasecmp (*strp, "gp(", 3) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 3; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_GPREL16, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return _("expecting gp relative address: gp(symbol)"); +} + +/* Handle got() */ + +static const char * +parse_got16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + if (strncasecmp (*strp, "got(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_16_GOT, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return _("expecting got relative address: got(symbol)"); +} + +/* Handle gotoffhi16() */ + +static const char * +parse_gotoff_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + if (strncasecmp (*strp, "gotoffhi16(", 11) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 11; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_HI16, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return _("expecting got relative address: gotoffhi16(symbol)"); +} + +/* Handle gotofflo16() */ + +static const char * +parse_gotoff_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + if (strncasecmp (*strp, "gotofflo16(", 11) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 11; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return _("expecting got relative address: gotofflo16(symbol)"); +} + +const char * lm32_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +lm32_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, LM32_OPERAND_BRANCH, 0, NULL, & value); + fields->f_branch = value; + } + break; + case LM32_OPERAND_CALL : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, LM32_OPERAND_CALL, 0, NULL, & value); + fields->f_call = value; + } + break; + case LM32_OPERAND_CSR : + errmsg = cgen_parse_keyword (cd, strp, & lm32_cgen_opval_h_csr, & fields->f_csr); + break; + case LM32_OPERAND_EXCEPTION : + errmsg = cgen_parse_unsigned_integer (cd, strp, LM32_OPERAND_EXCEPTION, (unsigned long *) (& fields->f_exception)); + break; + case LM32_OPERAND_GOT16 : + errmsg = parse_got16 (cd, strp, LM32_OPERAND_GOT16, (long *) (& fields->f_imm)); + break; + case LM32_OPERAND_GOTOFFHI16 : + errmsg = parse_gotoff_hi16 (cd, strp, LM32_OPERAND_GOTOFFHI16, (long *) (& fields->f_imm)); + break; + case LM32_OPERAND_GOTOFFLO16 : + errmsg = parse_gotoff_lo16 (cd, strp, LM32_OPERAND_GOTOFFLO16, (long *) (& fields->f_imm)); + break; + case LM32_OPERAND_GP16 : + errmsg = parse_gp16 (cd, strp, LM32_OPERAND_GP16, (long *) (& fields->f_imm)); + break; + case LM32_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, LM32_OPERAND_HI16, (unsigned long *) (& fields->f_uimm)); + break; + case LM32_OPERAND_IMM : + errmsg = cgen_parse_signed_integer (cd, strp, LM32_OPERAND_IMM, (long *) (& fields->f_imm)); + break; + case LM32_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, LM32_OPERAND_LO16, (unsigned long *) (& fields->f_uimm)); + break; + case LM32_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & lm32_cgen_opval_h_gr, & fields->f_r0); + break; + case LM32_OPERAND_R1 : + errmsg = cgen_parse_keyword (cd, strp, & lm32_cgen_opval_h_gr, & fields->f_r1); + break; + case LM32_OPERAND_R2 : + errmsg = cgen_parse_keyword (cd, strp, & lm32_cgen_opval_h_gr, & fields->f_r2); + break; + case LM32_OPERAND_SHIFT : + errmsg = cgen_parse_unsigned_integer (cd, strp, LM32_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift)); + break; + case LM32_OPERAND_UIMM : + errmsg = cgen_parse_unsigned_integer (cd, strp, LM32_OPERAND_UIMM, (unsigned long *) (& fields->f_uimm)); + break; + case LM32_OPERAND_USER : + errmsg = cgen_parse_unsigned_integer (cd, strp, LM32_OPERAND_USER, (unsigned long *) (& fields->f_user)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const lm32_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +lm32_cgen_init_asm (CGEN_CPU_DESC cd) +{ + lm32_cgen_init_opcode_table (cd); + lm32_cgen_init_ibld_table (cd); + cd->parse_handlers = & lm32_cgen_parse_handlers[0]; + cd->parse_operand = lm32_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by lm32_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +lm32_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +lm32_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! lm32_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/lm32-desc.c b/external/gpl3/gdb/dist/opcodes/lm32-desc.c new file mode 100644 index 000000000000..b7420ebf881e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-desc.c @@ -0,0 +1,1159 @@ +/* CPU data for lm32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "lm32-desc.h" +#include "lm32-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "lm32", MACH_LM32 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "lm32", ISA_LM32 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA lm32_cgen_isa_table[] = { + { "lm32", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH lm32_cgen_mach_table[] = { + { "lm32", "lm32", MACH_LM32, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_gr_entries[] = +{ + { "gp", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "ra", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "ea", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "ba", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD lm32_cgen_opval_h_gr = +{ + & lm32_cgen_opval_h_gr_entries[0], + 38, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] = +{ + { "IE", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "IM", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "IP", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "ICC", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "DCC", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "CC", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "CFG", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "DC", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "BP1", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "BP2", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "BP3", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD lm32_cgen_opval_h_csr = +{ + & lm32_cgen_opval_h_csr_entries[0], + 20, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY lm32_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & lm32_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & lm32_cgen_ifld_table[0]; +} + +/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & lm32_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of lm32_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & lm32_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of lm32_cgen_cpu_open to rebuild the tables. */ + +static void +lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & lm32_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & lm32_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "lm32_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (lm32_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "lm32_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "lm32_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = lm32_cgen_rebuild_tables; + lm32_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to lm32_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +lm32_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return lm32_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +lm32_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/lm32-desc.h b/external/gpl3/gdb/dist/opcodes/lm32-desc.h new file mode 100644 index 000000000000..a757cd1e1219 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-desc.h @@ -0,0 +1,240 @@ +/* CPU data header for lm32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef LM32_CPU_H +#define LM32_CPU_H + +#define CGEN_ARCH lm32 + +/* Given symbol S, return lm32_cgen_. */ +#define CGEN_SYM(s) lm32##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_LM32BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 5 + +/* Enums. */ + +/* Enum declaration for opcodes. */ +typedef enum opcodes { + OP_ADD = 45, OP_ADDI = 13, OP_AND = 40, OP_ANDI = 8 + , OP_ANDHI = 24, OP_B = 48, OP_BI = 56, OP_BE = 17 + , OP_BG = 18, OP_BGE = 19, OP_BGEU = 20, OP_BGU = 21 + , OP_BNE = 23, OP_CALL = 54, OP_CALLI = 62, OP_CMPE = 57 + , OP_CMPEI = 25, OP_CMPG = 58, OP_CMPGI = 26, OP_CMPGE = 59 + , OP_CMPGEI = 27, OP_CMPGEU = 60, OP_CMPGEUI = 28, OP_CMPGU = 61 + , OP_CMPGUI = 29, OP_CMPNE = 63, OP_CMPNEI = 31, OP_DIVU = 35 + , OP_LB = 4, OP_LBU = 16, OP_LH = 7, OP_LHU = 11 + , OP_LW = 10, OP_MODU = 49, OP_MUL = 34, OP_MULI = 2 + , OP_NOR = 33, OP_NORI = 1, OP_OR = 46, OP_ORI = 14 + , OP_ORHI = 30, OP_RAISE = 43, OP_RCSR = 36, OP_SB = 12 + , OP_SEXTB = 44, OP_SEXTH = 55, OP_SH = 3, OP_SL = 47 + , OP_SLI = 15, OP_SR = 37, OP_SRI = 5, OP_SRU = 32 + , OP_SRUI = 0, OP_SUB = 50, OP_SW = 22, OP_USER = 51 + , OP_WCSR = 52, OP_XNOR = 41, OP_XNORI = 9, OP_XOR = 38 + , OP_XORI = 6 +} OPCODES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_LM32, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_LM32, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for lm32 ifield types. */ +typedef enum ifield_type { + LM32_F_NIL, LM32_F_ANYOF, LM32_F_OPCODE, LM32_F_R0 + , LM32_F_R1, LM32_F_R2, LM32_F_RESV0, LM32_F_SHIFT + , LM32_F_IMM, LM32_F_UIMM, LM32_F_CSR, LM32_F_USER + , LM32_F_EXCEPTION, LM32_F_BRANCH, LM32_F_CALL, LM32_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) LM32_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for lm32 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CSR + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for lm32 operand types. */ +typedef enum cgen_operand_type { + LM32_OPERAND_PC, LM32_OPERAND_R0, LM32_OPERAND_R1, LM32_OPERAND_R2 + , LM32_OPERAND_SHIFT, LM32_OPERAND_IMM, LM32_OPERAND_UIMM, LM32_OPERAND_BRANCH + , LM32_OPERAND_CALL, LM32_OPERAND_CSR, LM32_OPERAND_USER, LM32_OPERAND_EXCEPTION + , LM32_OPERAND_HI16, LM32_OPERAND_LO16, LM32_OPERAND_GP16, LM32_OPERAND_GOT16 + , LM32_OPERAND_GOTOFFHI16, LM32_OPERAND_GOTOFFLO16, LM32_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 18 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 5 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld lm32_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD lm32_cgen_opval_h_gr; +extern CGEN_KEYWORD lm32_cgen_opval_h_csr; + +extern const CGEN_HW_ENTRY lm32_cgen_hw_table[]; + + + +#endif /* LM32_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/lm32-dis.c b/external/gpl3/gdb/dist/opcodes/lm32-dis.c new file mode 100644 index 000000000000..884a572525c3 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-dis.c @@ -0,0 +1,568 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "lm32-desc.h" +#include "lm32-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + + +void lm32_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +lm32_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + print_address (cd, info, fields->f_branch, 0|(1<f_call, 0|(1<f_csr, 0); + break; + case LM32_OPERAND_EXCEPTION : + print_normal (cd, info, fields->f_exception, 0, pc, length); + break; + case LM32_OPERAND_GOT16 : + print_normal (cd, info, fields->f_imm, 0|(1<f_imm, 0|(1<f_imm, 0|(1<f_imm, 0|(1<f_uimm, 0, pc, length); + break; + case LM32_OPERAND_IMM : + print_normal (cd, info, fields->f_imm, 0|(1<f_uimm, 0, pc, length); + break; + case LM32_OPERAND_R0 : + print_keyword (cd, info, & lm32_cgen_opval_h_gr, fields->f_r0, 0); + break; + case LM32_OPERAND_R1 : + print_keyword (cd, info, & lm32_cgen_opval_h_gr, fields->f_r1, 0); + break; + case LM32_OPERAND_R2 : + print_keyword (cd, info, & lm32_cgen_opval_h_gr, fields->f_r2, 0); + break; + case LM32_OPERAND_SHIFT : + print_normal (cd, info, fields->f_shift, 0, pc, length); + break; + case LM32_OPERAND_UIMM : + print_normal (cd, info, fields->f_uimm, 0, pc, length); + break; + case LM32_OPERAND_USER : + print_normal (cd, info, fields->f_user, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const lm32_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +lm32_cgen_init_dis (CGEN_CPU_DESC cd) +{ + lm32_cgen_init_opcode_table (cd); + lm32_cgen_init_ibld_table (cd); + cd->print_handlers = & lm32_cgen_print_handlers[0]; + cd->print_operand = lm32_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + lm32_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! lm32_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_lm32 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_lm32 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = lm32_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + lm32_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/lm32-ibld.c b/external/gpl3/gdb/dist/opcodes/lm32-ibld.c new file mode 100644 index 000000000000..9a1f8bbae076 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-ibld.c @@ -0,0 +1,1062 @@ +/* Instruction building/extraction support for lm32. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "lm32-desc.h" +#include "lm32-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * lm32_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +lm32_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + { + long value = fields->f_branch; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_call; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_csr, 0, 0, 25, 5, 32, total_length, buffer); + break; + case LM32_OPERAND_EXCEPTION : + errmsg = insert_normal (cd, fields->f_exception, 0, 0, 25, 26, 32, total_length, buffer); + break; + case LM32_OPERAND_GOT16 : + errmsg = insert_normal (cd, fields->f_imm, 0|(1<f_imm, 0|(1<f_imm, 0|(1<f_imm, 0|(1<f_uimm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case LM32_OPERAND_IMM : + errmsg = insert_normal (cd, fields->f_imm, 0|(1<f_uimm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case LM32_OPERAND_R0 : + errmsg = insert_normal (cd, fields->f_r0, 0, 0, 25, 5, 32, total_length, buffer); + break; + case LM32_OPERAND_R1 : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 20, 5, 32, total_length, buffer); + break; + case LM32_OPERAND_R2 : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 15, 5, 32, total_length, buffer); + break; + case LM32_OPERAND_SHIFT : + errmsg = insert_normal (cd, fields->f_shift, 0, 0, 4, 5, 32, total_length, buffer); + break; + case LM32_OPERAND_UIMM : + errmsg = insert_normal (cd, fields->f_uimm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case LM32_OPERAND_USER : + errmsg = insert_normal (cd, fields->f_user, 0, 0, 10, 11, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int lm32_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +lm32_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (14)))); + fields->f_branch = value; + } + break; + case LM32_OPERAND_CALL : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (4)))); + fields->f_call = value; + } + break; + case LM32_OPERAND_CSR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_csr); + break; + case LM32_OPERAND_EXCEPTION : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 26, 32, total_length, pc, & fields->f_exception); + break; + case LM32_OPERAND_GOT16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm); + break; + case LM32_OPERAND_GOTOFFHI16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm); + break; + case LM32_OPERAND_GOTOFFLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm); + break; + case LM32_OPERAND_GP16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm); + break; + case LM32_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); + break; + case LM32_OPERAND_IMM : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm); + break; + case LM32_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); + break; + case LM32_OPERAND_R0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r0); + break; + case LM32_OPERAND_R1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r1); + break; + case LM32_OPERAND_R2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r2); + break; + case LM32_OPERAND_SHIFT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_shift); + break; + case LM32_OPERAND_UIMM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); + break; + case LM32_OPERAND_USER : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_user); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const lm32_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const lm32_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int lm32_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma lm32_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +lm32_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + value = fields->f_branch; + break; + case LM32_OPERAND_CALL : + value = fields->f_call; + break; + case LM32_OPERAND_CSR : + value = fields->f_csr; + break; + case LM32_OPERAND_EXCEPTION : + value = fields->f_exception; + break; + case LM32_OPERAND_GOT16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GOTOFFHI16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GOTOFFLO16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GP16 : + value = fields->f_imm; + break; + case LM32_OPERAND_HI16 : + value = fields->f_uimm; + break; + case LM32_OPERAND_IMM : + value = fields->f_imm; + break; + case LM32_OPERAND_LO16 : + value = fields->f_uimm; + break; + case LM32_OPERAND_R0 : + value = fields->f_r0; + break; + case LM32_OPERAND_R1 : + value = fields->f_r1; + break; + case LM32_OPERAND_R2 : + value = fields->f_r2; + break; + case LM32_OPERAND_SHIFT : + value = fields->f_shift; + break; + case LM32_OPERAND_UIMM : + value = fields->f_uimm; + break; + case LM32_OPERAND_USER : + value = fields->f_user; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +lm32_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case LM32_OPERAND_BRANCH : + value = fields->f_branch; + break; + case LM32_OPERAND_CALL : + value = fields->f_call; + break; + case LM32_OPERAND_CSR : + value = fields->f_csr; + break; + case LM32_OPERAND_EXCEPTION : + value = fields->f_exception; + break; + case LM32_OPERAND_GOT16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GOTOFFHI16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GOTOFFLO16 : + value = fields->f_imm; + break; + case LM32_OPERAND_GP16 : + value = fields->f_imm; + break; + case LM32_OPERAND_HI16 : + value = fields->f_uimm; + break; + case LM32_OPERAND_IMM : + value = fields->f_imm; + break; + case LM32_OPERAND_LO16 : + value = fields->f_uimm; + break; + case LM32_OPERAND_R0 : + value = fields->f_r0; + break; + case LM32_OPERAND_R1 : + value = fields->f_r1; + break; + case LM32_OPERAND_R2 : + value = fields->f_r2; + break; + case LM32_OPERAND_SHIFT : + value = fields->f_shift; + break; + case LM32_OPERAND_UIMM : + value = fields->f_uimm; + break; + case LM32_OPERAND_USER : + value = fields->f_user; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void lm32_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void lm32_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +lm32_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case LM32_OPERAND_BRANCH : + fields->f_branch = value; + break; + case LM32_OPERAND_CALL : + fields->f_call = value; + break; + case LM32_OPERAND_CSR : + fields->f_csr = value; + break; + case LM32_OPERAND_EXCEPTION : + fields->f_exception = value; + break; + case LM32_OPERAND_GOT16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GOTOFFHI16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GOTOFFLO16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GP16 : + fields->f_imm = value; + break; + case LM32_OPERAND_HI16 : + fields->f_uimm = value; + break; + case LM32_OPERAND_IMM : + fields->f_imm = value; + break; + case LM32_OPERAND_LO16 : + fields->f_uimm = value; + break; + case LM32_OPERAND_R0 : + fields->f_r0 = value; + break; + case LM32_OPERAND_R1 : + fields->f_r1 = value; + break; + case LM32_OPERAND_R2 : + fields->f_r2 = value; + break; + case LM32_OPERAND_SHIFT : + fields->f_shift = value; + break; + case LM32_OPERAND_UIMM : + fields->f_uimm = value; + break; + case LM32_OPERAND_USER : + fields->f_user = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +lm32_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case LM32_OPERAND_BRANCH : + fields->f_branch = value; + break; + case LM32_OPERAND_CALL : + fields->f_call = value; + break; + case LM32_OPERAND_CSR : + fields->f_csr = value; + break; + case LM32_OPERAND_EXCEPTION : + fields->f_exception = value; + break; + case LM32_OPERAND_GOT16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GOTOFFHI16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GOTOFFLO16 : + fields->f_imm = value; + break; + case LM32_OPERAND_GP16 : + fields->f_imm = value; + break; + case LM32_OPERAND_HI16 : + fields->f_uimm = value; + break; + case LM32_OPERAND_IMM : + fields->f_imm = value; + break; + case LM32_OPERAND_LO16 : + fields->f_uimm = value; + break; + case LM32_OPERAND_R0 : + fields->f_r0 = value; + break; + case LM32_OPERAND_R1 : + fields->f_r1 = value; + break; + case LM32_OPERAND_R2 : + fields->f_r2 = value; + break; + case LM32_OPERAND_SHIFT : + fields->f_shift = value; + break; + case LM32_OPERAND_UIMM : + fields->f_uimm = value; + break; + case LM32_OPERAND_USER : + fields->f_user = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +lm32_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & lm32_cgen_insert_handlers[0]; + cd->extract_handlers = & lm32_cgen_extract_handlers[0]; + + cd->insert_operand = lm32_cgen_insert_operand; + cd->extract_operand = lm32_cgen_extract_operand; + + cd->get_int_operand = lm32_cgen_get_int_operand; + cd->set_int_operand = lm32_cgen_set_int_operand; + cd->get_vma_operand = lm32_cgen_get_vma_operand; + cd->set_vma_operand = lm32_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/lm32-opc.c b/external/gpl3/gdb/dist/opcodes/lm32-opc.c new file mode 100644 index 000000000000..b4dbd079dd32 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-opc.c @@ -0,0 +1,855 @@ +/* Instruction opcode table for lm32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "lm32-desc.h" +#include "lm32-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & lm32_cgen_ifld_table[LM32_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_UIMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andhii ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_UIMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_b ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_CALL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_be ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_BRANCH) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ori ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_UIMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcsr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1f07ff, { { F (F_OPCODE) }, { F (F_CSR) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sextb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc1f07ff, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_user ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_R2) }, { F (F_USER) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wcsr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_CSR) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_EXCEPTION) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bret ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_R2) }, { F (F_RESV0) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvi ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvui ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_UIMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvhi ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_UIMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mva ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lwgotrel ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_orhigotoffi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addgotoff ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_R0) }, { F (F_R1) }, { F (F_IMM) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) LM32_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE lm32_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xb4000000 } + }, +/* addi $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x34000000 } + }, +/* and $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xa0000000 } + }, +/* andi $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x20000000 } + }, +/* andhi $r1,$r0,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (HI16), 0 } }, + & ifmt_andhii, { 0x60000000 } + }, +/* b $r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), 0 } }, + & ifmt_b, { 0xc0000000 } + }, +/* bi $call */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CALL), 0 } }, + & ifmt_bi, { 0xe0000000 } + }, +/* be $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x44000000 } + }, +/* bg $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x48000000 } + }, +/* bge $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x4c000000 } + }, +/* bgeu $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x50000000 } + }, +/* bgu $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x54000000 } + }, +/* bne $r0,$r1,$branch */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), ',', OP (R1), ',', OP (BRANCH), 0 } }, + & ifmt_be, { 0x5c000000 } + }, +/* call $r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R0), 0 } }, + & ifmt_b, { 0xd8000000 } + }, +/* calli $call */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CALL), 0 } }, + & ifmt_bi, { 0xf8000000 } + }, +/* cmpe $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xe4000000 } + }, +/* cmpei $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x64000000 } + }, +/* cmpg $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xe8000000 } + }, +/* cmpgi $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x68000000 } + }, +/* cmpge $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xec000000 } + }, +/* cmpgei $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x6c000000 } + }, +/* cmpgeu $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xf0000000 } + }, +/* cmpgeui $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x70000000 } + }, +/* cmpgu $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xf4000000 } + }, +/* cmpgui $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x74000000 } + }, +/* cmpne $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xfc000000 } + }, +/* cmpnei $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x7c000000 } + }, +/* divu $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x8c000000 } + }, +/* lb $r1,($r0+$imm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (IMM), ')', 0 } }, + & ifmt_addi, { 0x10000000 } + }, +/* lbu $r1,($r0+$imm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (IMM), ')', 0 } }, + & ifmt_addi, { 0x40000000 } + }, +/* lh $r1,($r0+$imm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (IMM), ')', 0 } }, + & ifmt_addi, { 0x1c000000 } + }, +/* lhu $r1,($r0+$imm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (IMM), ')', 0 } }, + & ifmt_addi, { 0x2c000000 } + }, +/* lw $r1,($r0+$imm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (IMM), ')', 0 } }, + & ifmt_addi, { 0x28000000 } + }, +/* modu $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xc4000000 } + }, +/* mul $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x88000000 } + }, +/* muli $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x8000000 } + }, +/* nor $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x84000000 } + }, +/* nori $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x4000000 } + }, +/* or $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xb8000000 } + }, +/* ori $r1,$r0,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (LO16), 0 } }, + & ifmt_ori, { 0x38000000 } + }, +/* orhi $r1,$r0,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (HI16), 0 } }, + & ifmt_andhii, { 0x78000000 } + }, +/* rcsr $r2,$csr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } }, + & ifmt_rcsr, { 0x90000000 } + }, +/* sb ($r0+$imm),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (IMM), ')', ',', OP (R1), 0 } }, + & ifmt_addi, { 0x30000000 } + }, +/* sextb $r2,$r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), 0 } }, + & ifmt_sextb, { 0xb0000000 } + }, +/* sexth $r2,$r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), 0 } }, + & ifmt_sextb, { 0xdc000000 } + }, +/* sh ($r0+$imm),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (IMM), ')', ',', OP (R1), 0 } }, + & ifmt_addi, { 0xc000000 } + }, +/* sl $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xbc000000 } + }, +/* sli $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x3c000000 } + }, +/* sr $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x94000000 } + }, +/* sri $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x14000000 } + }, +/* sru $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x80000000 } + }, +/* srui $r1,$r0,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (IMM), 0 } }, + & ifmt_addi, { 0x0 } + }, +/* sub $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xc8000000 } + }, +/* sw ($r0+$imm),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (IMM), ')', ',', OP (R1), 0 } }, + & ifmt_addi, { 0x58000000 } + }, +/* user $r2,$r0,$r1,$user */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), ',', OP (USER), 0 } }, + & ifmt_user, { 0xcc000000 } + }, +/* wcsr $csr,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } }, + & ifmt_wcsr, { 0xd0000000 } + }, +/* xor $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0x98000000 } + }, +/* xori $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x18000000 } + }, +/* xnor $r2,$r0,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), ',', OP (R1), 0 } }, + & ifmt_add, { 0xa4000000 } + }, +/* xnori $r1,$r0,$uimm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (UIMM), 0 } }, + & ifmt_andi, { 0x24000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xac000002 } + }, +/* scall */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xac000007 } + }, +/* bret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_bret, { 0xc3e00000 } + }, +/* eret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_bret, { 0xc3c00000 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_bret, { 0xc3a00000 } + }, +/* mv $r2,$r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), 0 } }, + & ifmt_sextb, { 0xb8000000 } + }, +/* mvi $r1,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (IMM), 0 } }, + & ifmt_mvi, { 0x34000000 } + }, +/* mvu $r1,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (LO16), 0 } }, + & ifmt_mvui, { 0x38000000 } + }, +/* mvhi $r1,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (HI16), 0 } }, + & ifmt_mvhi, { 0x78000000 } + }, +/* mva $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x37400000 } + }, +/* not $r2,$r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R2), ',', OP (R0), 0 } }, + & ifmt_sextb, { 0xa4000000 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x34000000 } + }, +/* lb $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x13400000 } + }, +/* lbu $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x43400000 } + }, +/* lh $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x1f400000 } + }, +/* lhu $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x2f400000 } + }, +/* lw $r1,$gp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (GP16), 0 } }, + & ifmt_mva, { 0x2b400000 } + }, +/* sb $gp16,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GP16), ',', OP (R1), 0 } }, + & ifmt_mva, { 0x33400000 } + }, +/* sh $gp16,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GP16), ',', OP (R1), 0 } }, + & ifmt_mva, { 0xf400000 } + }, +/* sw $gp16,$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GP16), ',', OP (R1), 0 } }, + & ifmt_mva, { 0x5b400000 } + }, +/* lw $r1,(gp+$got16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', 'g', 'p', '+', OP (GOT16), ')', 0 } }, + & ifmt_lwgotrel, { 0x2b400000 } + }, +/* orhi $r1,$r0,$gotoffhi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (GOTOFFHI16), 0 } }, + & ifmt_orhigotoffi, { 0x78000000 } + }, +/* addi $r1,$r0,$gotofflo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', OP (R0), ',', OP (GOTOFFLO16), 0 } }, + & ifmt_addgotoff, { 0x34000000 } + }, +/* sw ($r0+$gotofflo16),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (GOTOFFLO16), ')', ',', OP (R1), 0 } }, + & ifmt_addgotoff, { 0x58000000 } + }, +/* lw $r1,($r0+$gotofflo16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (GOTOFFLO16), ')', 0 } }, + & ifmt_addgotoff, { 0x28000000 } + }, +/* sh ($r0+$gotofflo16),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (GOTOFFLO16), ')', ',', OP (R1), 0 } }, + & ifmt_addgotoff, { 0xc000000 } + }, +/* lh $r1,($r0+$gotofflo16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (GOTOFFLO16), ')', 0 } }, + & ifmt_addgotoff, { 0x1c000000 } + }, +/* lhu $r1,($r0+$gotofflo16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (GOTOFFLO16), ')', 0 } }, + & ifmt_addgotoff, { 0x2c000000 } + }, +/* sb ($r0+$gotofflo16),$r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (R0), '+', OP (GOTOFFLO16), ')', ',', OP (R1), 0 } }, + & ifmt_addgotoff, { 0x30000000 } + }, +/* lb $r1,($r0+$gotofflo16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (GOTOFFLO16), ')', 0 } }, + & ifmt_addgotoff, { 0x10000000 } + }, +/* lbu $r1,($r0+$gotofflo16) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R1), ',', '(', OP (R0), '+', OP (GOTOFFLO16), ')', 0 } }, + & ifmt_addgotoff, { 0x40000000 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & lm32_cgen_ifld_table[LM32_##f] +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) LM32_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE lm32_cgen_macro_insn_table[] = +{ +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE lm32_cgen_macro_insn_opcode_table[] = +{ +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +lm32_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (lm32_cgen_macro_insn_table) / + sizeof (lm32_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & lm32_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & lm32_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + /* This test has been added to avoid a warning generated + if memset is called with a third argument of value zero. */ + if (num_macros >= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + lm32_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & lm32_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + lm32_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/lm32-opc.h b/external/gpl3/gdb/dist/opcodes/lm32-opc.h new file mode 100644 index 000000000000..ea0dd95b3d42 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-opc.h @@ -0,0 +1,105 @@ +/* Instruction opcode header for lm32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef LM32_OPC_H +#define LM32_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +#define CGEN_DIS_HASH_SIZE 64 +#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f) + +/* -- asm.c */ +/* Enum declaration for lm32 instruction types. */ +typedef enum cgen_insn_type { + LM32_INSN_INVALID, LM32_INSN_ADD, LM32_INSN_ADDI, LM32_INSN_AND + , LM32_INSN_ANDI, LM32_INSN_ANDHII, LM32_INSN_B, LM32_INSN_BI + , LM32_INSN_BE, LM32_INSN_BG, LM32_INSN_BGE, LM32_INSN_BGEU + , LM32_INSN_BGU, LM32_INSN_BNE, LM32_INSN_CALL, LM32_INSN_CALLI + , LM32_INSN_CMPE, LM32_INSN_CMPEI, LM32_INSN_CMPG, LM32_INSN_CMPGI + , LM32_INSN_CMPGE, LM32_INSN_CMPGEI, LM32_INSN_CMPGEU, LM32_INSN_CMPGEUI + , LM32_INSN_CMPGU, LM32_INSN_CMPGUI, LM32_INSN_CMPNE, LM32_INSN_CMPNEI + , LM32_INSN_DIVU, LM32_INSN_LB, LM32_INSN_LBU, LM32_INSN_LH + , LM32_INSN_LHU, LM32_INSN_LW, LM32_INSN_MODU, LM32_INSN_MUL + , LM32_INSN_MULI, LM32_INSN_NOR, LM32_INSN_NORI, LM32_INSN_OR + , LM32_INSN_ORI, LM32_INSN_ORHII, LM32_INSN_RCSR, LM32_INSN_SB + , LM32_INSN_SEXTB, LM32_INSN_SEXTH, LM32_INSN_SH, LM32_INSN_SL + , LM32_INSN_SLI, LM32_INSN_SR, LM32_INSN_SRI, LM32_INSN_SRU + , LM32_INSN_SRUI, LM32_INSN_SUB, LM32_INSN_SW, LM32_INSN_USER + , LM32_INSN_WCSR, LM32_INSN_XOR, LM32_INSN_XORI, LM32_INSN_XNOR + , LM32_INSN_XNORI, LM32_INSN_BREAK, LM32_INSN_SCALL, LM32_INSN_BRET + , LM32_INSN_ERET, LM32_INSN_RET, LM32_INSN_MV, LM32_INSN_MVI + , LM32_INSN_MVUI, LM32_INSN_MVHI, LM32_INSN_MVA, LM32_INSN_NOT + , LM32_INSN_NOP, LM32_INSN_LBGPREL, LM32_INSN_LBUGPREL, LM32_INSN_LHGPREL + , LM32_INSN_LHUGPREL, LM32_INSN_LWGPREL, LM32_INSN_SBGPREL, LM32_INSN_SHGPREL + , LM32_INSN_SWGPREL, LM32_INSN_LWGOTREL, LM32_INSN_ORHIGOTOFFI, LM32_INSN_ADDGOTOFF + , LM32_INSN_SWGOTOFF, LM32_INSN_LWGOTOFF, LM32_INSN_SHGOTOFF, LM32_INSN_LHGOTOFF + , LM32_INSN_LHUGOTOFF, LM32_INSN_SBGOTOFF, LM32_INSN_LBGOTOFF, LM32_INSN_LBUGOTOFF +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID LM32_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) LM32_INSN_LBUGOTOFF + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_opcode; + long f_r0; + long f_r1; + long f_r2; + long f_resv0; + long f_shift; + long f_imm; + long f_uimm; + long f_csr; + long f_user; + long f_exception; + long f_branch; + long f_call; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* LM32_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/lm32-opinst.c b/external/gpl3/gdb/dist/opcodes/lm32-opinst.c new file mode 100644 index 000000000000..24007cfded2b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/lm32-opinst.c @@ -0,0 +1,476 @@ +/* Semantic operand instances for lm32. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "lm32-desc.h" +#include "lm32-opc.h" + +/* Operand references. */ + +#define OP_ENT(op) LM32_OPERAND_##op +#define INPUT CGEN_OPINST_INPUT +#define OUTPUT CGEN_OPINST_OUTPUT +#define END CGEN_OPINST_END +#define COND_REF CGEN_OPINST_COND_REF + +static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_andi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "uimm", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_andhii_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "hi16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (HI16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_b_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_r0", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "call", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (CALL), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_be_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "branch", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (BRANCH), 0, COND_REF }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_call_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "h_gr_SI_29", HW_H_GR, CGEN_MODE_SI, 0, 29, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_calli_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "call", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (CALL), 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_gr_SI_29", HW_H_GR, CGEN_MODE_SI, 0, 29, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_r0", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_r1", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_r2", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lh_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ori_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "lo16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (LO16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rcsr_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "csr", HW_H_CSR, CGEN_MODE_SI, OP_ENT (CSR), 0, 0 }, + { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sextb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sh_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_imm", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_user_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { INPUT, "user", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (USER), 0, 0 }, + { OUTPUT, "r2", HW_H_GR, CGEN_MODE_SI, OP_ENT (R2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_wcsr_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_csr", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_break_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bret_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "imm", HW_H_SINT, CGEN_MODE_INT, OP_ENT (IMM), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvui_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "lo16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (LO16), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvhi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "hi16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (HI16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mva_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_nop_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lbgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lhgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lwgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sbgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_shgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_swgprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gp16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GP16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_gp16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lwgotrel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "got16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOT16), 0, 0 }, + { INPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_got16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_orhigotoffi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotoffhi16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFHI16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_swgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lwgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "h_memory_SI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_shgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lhgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "h_memory_HI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sbgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { INPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { OUTPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lbgotoff_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "gotofflo16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (GOTOFFLO16), 0, 0 }, + { INPUT, "h_memory_QI_add__SI_r0_ext__SI_trunc__HI_gotofflo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "r0", HW_H_GR, CGEN_MODE_SI, OP_ENT (R0), 0, 0 }, + { OUTPUT, "r1", HW_H_GR, CGEN_MODE_SI, OP_ENT (R1), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +#undef OP_ENT +#undef INPUT +#undef OUTPUT +#undef END +#undef COND_REF + +/* Operand instance lookup table. */ + +static const CGEN_OPINST *lm32_cgen_opinst_table[MAX_INSNS] = { + 0, + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_andhii_ops[0], + & sfmt_b_ops[0], + & sfmt_bi_ops[0], + & sfmt_be_ops[0], + & sfmt_be_ops[0], + & sfmt_be_ops[0], + & sfmt_be_ops[0], + & sfmt_be_ops[0], + & sfmt_be_ops[0], + & sfmt_call_ops[0], + & sfmt_calli_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_divu_ops[0], + & sfmt_lb_ops[0], + & sfmt_lb_ops[0], + & sfmt_lh_ops[0], + & sfmt_lh_ops[0], + & sfmt_lw_ops[0], + & sfmt_divu_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_add_ops[0], + & sfmt_ori_ops[0], + & sfmt_andhii_ops[0], + & sfmt_rcsr_ops[0], + & sfmt_sb_ops[0], + & sfmt_sextb_ops[0], + & sfmt_sextb_ops[0], + & sfmt_sh_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_addi_ops[0], + & sfmt_add_ops[0], + & sfmt_sw_ops[0], + & sfmt_user_ops[0], + & sfmt_wcsr_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_add_ops[0], + & sfmt_andi_ops[0], + & sfmt_break_ops[0], + & sfmt_break_ops[0], + & sfmt_bret_ops[0], + & sfmt_bret_ops[0], + & sfmt_bret_ops[0], + & sfmt_sextb_ops[0], + & sfmt_mvi_ops[0], + & sfmt_mvui_ops[0], + & sfmt_mvhi_ops[0], + & sfmt_mva_ops[0], + & sfmt_sextb_ops[0], + & sfmt_nop_ops[0], + & sfmt_lbgprel_ops[0], + & sfmt_lbgprel_ops[0], + & sfmt_lhgprel_ops[0], + & sfmt_lhgprel_ops[0], + & sfmt_lwgprel_ops[0], + & sfmt_sbgprel_ops[0], + & sfmt_shgprel_ops[0], + & sfmt_swgprel_ops[0], + & sfmt_lwgotrel_ops[0], + & sfmt_orhigotoffi_ops[0], + & sfmt_addgotoff_ops[0], + & sfmt_swgotoff_ops[0], + & sfmt_lwgotoff_ops[0], + & sfmt_shgotoff_ops[0], + & sfmt_lhgotoff_ops[0], + & sfmt_lhgotoff_ops[0], + & sfmt_sbgotoff_ops[0], + & sfmt_lbgotoff_ops[0], + & sfmt_lbgotoff_ops[0], +}; + +/* Function to call before using the operand instance table. */ + +void +lm32_cgen_init_opinst_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + const CGEN_OPINST **oi = & lm32_cgen_opinst_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + insns[i].opinst = oi[i]; +} diff --git a/external/gpl3/gdb/dist/opcodes/m10200-dis.c b/external/gpl3/gdb/dist/opcodes/m10200-dis.c new file mode 100644 index 000000000000..6c69c0016ce6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m10200-dis.c @@ -0,0 +1,335 @@ +/* Disassemble MN10200 instructions. + Copyright 1996, 1997, 1998, 2000, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/mn10200.h" +#include "dis-asm.h" +#include "opintl.h" + +static void +disassemble (bfd_vma memaddr, + struct disassemble_info *info, + unsigned long insn, + unsigned long extension, + unsigned int size) +{ + struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes; + const struct mn10200_operand *operand; + int match = 0; + + /* Find the opcode. */ + while (op->name) + { + int mysize, extra_shift; + + if (op->format == FMT_1) + mysize = 1; + else if (op->format == FMT_2 + || op->format == FMT_4) + mysize = 2; + else if (op->format == FMT_3 + || op->format == FMT_5) + mysize = 3; + else if (op->format == FMT_6) + mysize = 4; + else if (op->format == FMT_7) + mysize = 5; + else + abort (); + + if (op->format == FMT_2 || op->format == FMT_5) + extra_shift = 8; + else if (op->format == FMT_3 + || op->format == FMT_6 + || op->format == FMT_7) + extra_shift = 16; + else + extra_shift = 0; + + if ((op->mask & insn) == op->opcode + && size == (unsigned int) mysize) + { + const unsigned char *opindex_ptr; + unsigned int nocomma; + int paren = 0; + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + /* Now print the operands. */ + for (opindex_ptr = op->operands, nocomma = 1; + *opindex_ptr != 0; + opindex_ptr++) + { + unsigned long value; + + operand = &mn10200_operands[*opindex_ptr]; + + if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0) + { + value = (insn & 0xffff) << 8; + value |= extension; + } + else + { + value = ((insn >> (operand->shift)) + & ((1L << operand->bits) - 1L)); + } + + if ((operand->flags & MN10200_OPERAND_SIGNED) != 0) + value = ((long)(value << (32 - operand->bits)) + >> (32 - operand->bits)); + + if (!nocomma + && (!paren + || ((operand->flags & MN10200_OPERAND_PAREN) == 0))) + (*info->fprintf_func) (info->stream, ","); + + nocomma = 0; + + if ((operand->flags & MN10200_OPERAND_DREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "d%ld", value); + } + + else if ((operand->flags & MN10200_OPERAND_AREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "a%ld", value); + } + + else if ((operand->flags & MN10200_OPERAND_PSW) != 0) + (*info->fprintf_func) (info->stream, "psw"); + + else if ((operand->flags & MN10200_OPERAND_MDR) != 0) + (*info->fprintf_func) (info->stream, "mdr"); + + else if ((operand->flags & MN10200_OPERAND_PAREN) != 0) + { + if (paren) + (*info->fprintf_func) (info->stream, ")"); + else + { + (*info->fprintf_func) (info->stream, "("); + nocomma = 1; + } + paren = !paren; + } + + else if ((operand->flags & MN10200_OPERAND_PCREL) != 0) + (*info->print_address_func) + ((value + memaddr + mysize) & 0xffffff, info); + + else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0) + (*info->print_address_func) (value, info); + + else + (*info->fprintf_func) (info->stream, "%ld", value); + } + /* All done. */ + break; + } + op++; + } + + if (!match) + (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); +} + +int +print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + unsigned long extension = 0; + unsigned int consume; + + /* First figure out how big the opcode is. */ + status = (*info->read_memory_func) (memaddr, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = *(unsigned char *) buffer; + + /* These are one byte insns. */ + if ((insn & 0xf0) == 0x00 + || (insn & 0xf0) == 0x10 + || (insn & 0xf0) == 0x20 + || (insn & 0xf0) == 0x30 + || ((insn & 0xf0) == 0x80 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || (insn & 0xf0) == 0x90 + || (insn & 0xf0) == 0xa0 + || (insn & 0xf0) == 0xb0 + || (insn & 0xff) == 0xeb + || (insn & 0xff) == 0xf6 + || (insn & 0xff) == 0xfe + || (insn & 0xff) == 0xff) + { + extension = 0; + consume = 1; + } + + /* These are two byte insns. */ + else if ((insn & 0xf0) == 0x40 + || (insn & 0xf0) == 0x50 + || (insn & 0xf0) == 0x60 + || (insn & 0xf0) == 0x70 + || (insn & 0xf0) == 0x80 + || (insn & 0xfc) == 0xd0 + || (insn & 0xfc) == 0xd4 + || (insn & 0xfc) == 0xd8 + || (insn & 0xfc) == 0xe0 + || (insn & 0xfc) == 0xe4 + || (insn & 0xff) == 0xe8 + || (insn & 0xff) == 0xe9 + || (insn & 0xff) == 0xea + || (insn & 0xff) == 0xf0 + || (insn & 0xff) == 0xf1 + || (insn & 0xff) == 0xf2 + || (insn & 0xff) == 0xf3) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + consume = 2; + } + + /* These are three byte insns with a 16bit operand in little + endian form. */ + else if ((insn & 0xf0) == 0xc0 + || (insn & 0xfc) == 0xdc + || (insn & 0xfc) == 0xec + || (insn & 0xff) == 0xf8 + || (insn & 0xff) == 0xf9 + || (insn & 0xff) == 0xfa + || (insn & 0xff) == 0xfb + || (insn & 0xff) == 0xfc + || (insn & 0xff) == 0xfd) + { + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn <<= 16; + insn |= bfd_getl16 (buffer); + extension = 0; + consume = 3; + } + /* These are three byte insns too, but we don't have to mess with + endianness stuff. */ + else if ((insn & 0xff) == 0xf5) + { + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn <<= 16; + insn |= bfd_getb16 (buffer); + extension = 0; + consume = 3; + } + + /* These are four byte insns. */ + else if ((insn & 0xff) == 0xf7) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 16; + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= bfd_getl16 (buffer); + extension = 0; + consume = 4; + } + + /* These are five byte insns. */ + else if ((insn & 0xff) == 0xf4) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 16; + + status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= (*(unsigned char *)buffer << 8) & 0xff00; + + status = (*info->read_memory_func) (memaddr + 3, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= (*(unsigned char *)buffer) & 0xff; + + status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + extension = (*(unsigned char *)buffer) & 0xff; + consume = 5; + } + else + { + (*info->fprintf_func) (info->stream, _("unknown\t0x%02lx"), insn); + return 1; + } + + disassemble (memaddr, info, insn, extension, consume); + + return consume; +} diff --git a/external/gpl3/gdb/dist/opcodes/m10200-opc.c b/external/gpl3/gdb/dist/opcodes/m10200-opc.c new file mode 100644 index 000000000000..7cb1bfe24849 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m10200-opc.c @@ -0,0 +1,363 @@ +/* Assemble Matsushita MN10200 instructions. + Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "opcode/mn10200.h" + + +const struct mn10200_operand mn10200_operands[] = { +#define UNUSED 0 + {0, 0, 0}, + +/* dn register in the first register operand position. */ +#define DN0 (UNUSED+1) + {2, 0, MN10200_OPERAND_DREG}, + +/* dn register in the second register operand position. */ +#define DN1 (DN0+1) + {2, 2, MN10200_OPERAND_DREG}, + +/* dm register in the first register operand position. */ +#define DM0 (DN1+1) + {2, 0, MN10200_OPERAND_DREG}, + +/* dm register in the second register operand position. */ +#define DM1 (DM0+1) + {2, 2, MN10200_OPERAND_DREG}, + +/* an register in the first register operand position. */ +#define AN0 (DM1+1) + {2, 0, MN10200_OPERAND_AREG}, + +/* an register in the second register operand position. */ +#define AN1 (AN0+1) + {2, 2, MN10200_OPERAND_AREG}, + +/* am register in the first register operand position. */ +#define AM0 (AN1+1) + {2, 0, MN10200_OPERAND_AREG}, + +/* am register in the second register operand position. */ +#define AM1 (AM0+1) + {2, 2, MN10200_OPERAND_AREG}, + +/* 8 bit unsigned immediate which may promote to a 16bit + unsigned immediate. */ +#define IMM8 (AM1+1) + {8, 0, MN10200_OPERAND_PROMOTE}, + +/* 16 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM16 (IMM8+1) + {16, 0, MN10200_OPERAND_PROMOTE}, + +/* 16 bit pc-relative immediate which may promote to a 16bit + pc-relative immediate. */ +#define IMM16_PCREL (IMM16+1) + {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, + +/* 16bit unsigned dispacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM16_MEM (IMM16_PCREL+1) + {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, + +/* 24 immediate, low 16 bits in the main instruction + word, 8 in the extension word. */ + +#define IMM24 (IMM16_MEM+1) + {24, 0, MN10200_OPERAND_EXTENDED}, + +/* 32bit pc-relative offset. */ +#define IMM24_PCREL (IMM24+1) + {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, + +/* 32bit memory offset. */ +#define IMM24_MEM (IMM24_PCREL+1) + {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, + +/* Processor status word. */ +#define PSW (IMM24_MEM+1) + {0, 0, MN10200_OPERAND_PSW}, + +/* MDR register. */ +#define MDR (PSW+1) + {0, 0, MN10200_OPERAND_MDR}, + +/* Index register. */ +#define DI (MDR+1) + {2, 4, MN10200_OPERAND_DREG}, + +/* 8 bit signed displacement, may promote to 16bit signed dispacement. */ +#define SD8 (DI+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed displacement, may promote to 32bit dispacement. */ +#define SD16 (SD8+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 8 bit pc-relative displacement. */ +#define SD8N_PCREL (SD16+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, + +/* 8 bit signed immediate which may promote to 16bit signed immediate. */ +#define SIMM8 (SD8N_PCREL+1) + {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may promote to 32bit immediate. */ +#define SIMM16 (SIMM8+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may not promote. */ +#define SIMM16N (SIMM16+1) + {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, + +/* Either an open paren or close paren. */ +#define PAREN (SIMM16N+1) + {0, 0, MN10200_OPERAND_PAREN}, + +/* dn register that appears in the first and second register positions. */ +#define DN01 (PAREN+1) + {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, + +/* an register that appears in the first and second register positions. */ +#define AN01 (DN01+1) + {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, +} ; + +#define MEM(ADDR) PAREN, ADDR, PAREN +#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct mn10200_opcode mn10200_opcodes[] = { +{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, +{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, +{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, +{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, +{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, +{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, +{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, +{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, +{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, +{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, +{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, +{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, +{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, +{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, +{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, +{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, +{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, +{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, +{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, +{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, +{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, +{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, +{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, +{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, +{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, +{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, +{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, +{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, +{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, +{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, +{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, +{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, +{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, +{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, +{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, + +{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, +{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, + +{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, +{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, +{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, +{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, +{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, +{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, +{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, +{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, + +{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, +{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, +{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, +{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, +{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, +{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, +{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, + +{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, +{ "extx", 0xb0, 0xfc, FMT_1, {DN0}}, +{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, +{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, +{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, + +{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, +{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, +{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, +{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, +{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, +{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, +{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, +{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, +{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, +{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, + +{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, +{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, +{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, +{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, +{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, +{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, +{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, +{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, + +{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, +{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, +{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, +{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, +{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, +{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, +{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, +{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, +{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, + +{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, +{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, +{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, +{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, +{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, +{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, + +{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, +{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, +{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, +{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, + +{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, +{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, +{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, +{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, + +{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, +{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, + +{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, +{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, + +{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, +{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, +{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, +{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, +{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, +{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, + +{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, + +{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, +{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, + +/* Extension. We need some instruction to trigger "emulated syscalls" + for our simulator. */ +{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, + +/* Extension. When talking to the simulator, gdb requires some instruction + that will trigger a "breakpoint" (really just an instruction that isn't + otherwise used by the tools. This instruction must be the same size + as the smallest instruction on the target machine. In the case of the + mn10x00 the "break" instruction must be one byte. 0xff is available on + both mn10x00 architectures. */ +{ "break", 0xff, 0xff, FMT_1, {UNUSED}}, + +{ 0, 0, 0, 0, {0}}, + +} ; + +const int mn10200_num_opcodes = + sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); + + diff --git a/external/gpl3/gdb/dist/opcodes/m10300-dis.c b/external/gpl3/gdb/dist/opcodes/m10300-dis.c new file mode 100644 index 000000000000..1ed50f174273 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m10300-dis.c @@ -0,0 +1,762 @@ +/* Disassemble MN10300 instructions. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/mn10300.h" +#include "dis-asm.h" +#include "opintl.h" + +#define HAVE_AM33_2 (info->mach == AM33_2) +#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2) +#define HAVE_AM30 (info->mach == AM30) + +static void +disassemble (bfd_vma memaddr, + struct disassemble_info *info, + unsigned long insn, + unsigned int size) +{ + struct mn10300_opcode *op = (struct mn10300_opcode *) mn10300_opcodes; + const struct mn10300_operand *operand; + bfd_byte buffer[4]; + unsigned long extension = 0; + int status, match = 0; + + /* Find the opcode. */ + while (op->name) + { + int mysize, extra_shift; + + if (op->format == FMT_S0) + mysize = 1; + else if (op->format == FMT_S1 + || op->format == FMT_D0) + mysize = 2; + else if (op->format == FMT_S2 + || op->format == FMT_D1) + mysize = 3; + else if (op->format == FMT_S4) + mysize = 5; + else if (op->format == FMT_D2) + mysize = 4; + else if (op->format == FMT_D3) + mysize = 5; + else if (op->format == FMT_D4) + mysize = 6; + else if (op->format == FMT_D6) + mysize = 3; + else if (op->format == FMT_D7 || op->format == FMT_D10) + mysize = 4; + else if (op->format == FMT_D8) + mysize = 6; + else if (op->format == FMT_D9) + mysize = 7; + else + mysize = 7; + + if ((op->mask & insn) == op->opcode + && size == (unsigned int) mysize + && (op->machine == 0 + || (op->machine == AM33_2 && HAVE_AM33_2) + || (op->machine == AM33 && HAVE_AM33) + || (op->machine == AM30 && HAVE_AM30))) + { + const unsigned char *opindex_ptr; + unsigned int nocomma; + int paren = 0; + + if (op->format == FMT_D1 || op->format == FMT_S1) + extra_shift = 8; + else if (op->format == FMT_D2 || op->format == FMT_D4 + || op->format == FMT_S2 || op->format == FMT_S4 + || op->format == FMT_S6 || op->format == FMT_D5) + extra_shift = 16; + else if (op->format == FMT_D7 + || op->format == FMT_D8 + || op->format == FMT_D9) + extra_shift = 8; + else + extra_shift = 0; + + if (size == 1 || size == 2) + extension = 0; + + else if (size == 3 + && (op->format == FMT_D1 + || op->opcode == 0xdf0000 + || op->opcode == 0xde0000)) + extension = 0; + + else if (size == 3 + && op->format == FMT_D6) + extension = 0; + + else if (size == 3) + { + insn &= 0xff0000; + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + + insn |= bfd_getl16 (buffer); + extension = 0; + } + else if (size == 4 + && (op->opcode == 0xfaf80000 + || op->opcode == 0xfaf00000 + || op->opcode == 0xfaf40000)) + extension = 0; + + else if (size == 4 + && (op->format == FMT_D7 + || op->format == FMT_D10)) + extension = 0; + + else if (size == 4) + { + insn &= 0xffff0000; + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + + insn |= bfd_getl16 (buffer); + extension = 0; + } + else if (size == 5 && op->opcode == 0xdc000000) + { + unsigned long temp = 0; + + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xff000000; + insn |= (temp & 0xffffff00) >> 8; + extension = temp & 0xff; + } + else if (size == 5 && op->format == FMT_D3) + { + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + insn &= 0xffff0000; + insn |= bfd_getl16 (buffer); + + status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = *(unsigned char *) buffer; + } + else if (size == 5) + { + unsigned long temp = 0; + + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl16 (buffer); + + insn &= 0xff0000ff; + insn |= temp << 8; + + status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = *(unsigned char *) buffer; + } + else if (size == 6 && op->format == FMT_D8) + { + insn &= 0xffffff00; + status = (*info->read_memory_func) (memaddr + 5, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + insn |= *(unsigned char *) buffer; + + status = (*info->read_memory_func) (memaddr + 3, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = bfd_getl16 (buffer); + } + else if (size == 6) + { + unsigned long temp = 0; + + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xffff0000; + insn |= (temp >> 16) & 0xffff; + extension = temp & 0xffff; + } + else if (size == 7 && op->format == FMT_D9) + { + insn &= 0xffffff00; + status = (*info->read_memory_func) (memaddr + 3, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension = bfd_getl32 (buffer); + insn |= (extension & 0xff000000) >> 24; + extension &= 0xffffff; + } + else if (size == 7 && op->opcode == 0xdd000000) + { + unsigned long temp = 0; + + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xff000000; + insn |= (temp >> 8) & 0xffffff; + extension = (temp & 0xff) << 16; + + status = (*info->read_memory_func) (memaddr + 5, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension |= bfd_getb16 (buffer); + } + else if (size == 7) + { + unsigned long temp = 0; + + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + temp |= bfd_getl32 (buffer); + + insn &= 0xffff0000; + insn |= (temp >> 16) & 0xffff; + extension = (temp & 0xffff) << 8; + + status = (*info->read_memory_func) (memaddr + 6, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return; + } + extension |= *(unsigned char *) buffer; + } + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + /* Now print the operands. */ + for (opindex_ptr = op->operands, nocomma = 1; + *opindex_ptr != 0; + opindex_ptr++) + { + unsigned long value; + + operand = &mn10300_operands[*opindex_ptr]; + + /* If this operand is a PLUS (autoincrement), then do not emit + a comma before emitting the plus. */ + if ((operand->flags & MN10300_OPERAND_PLUS) != 0) + nocomma = 1; + + if ((operand->flags & MN10300_OPERAND_SPLIT) != 0) + { + unsigned long temp; + + value = insn & ((1 << operand->bits) - 1); + value <<= (32 - operand->bits); + temp = extension >> operand->shift; + temp &= ((1 << (32 - operand->bits)) - 1); + value |= temp; + value = ((value ^ (((unsigned long) 1) << 31)) + - (((unsigned long) 1) << 31)); + } + else if ((operand->flags & MN10300_OPERAND_24BIT) != 0) + { + unsigned long temp; + + value = insn & ((1 << operand->bits) - 1); + value <<= (24 - operand->bits); + temp = extension >> operand->shift; + temp &= ((1 << (24 - operand->bits)) - 1); + value |= temp; + if ((operand->flags & MN10300_OPERAND_SIGNED) != 0) + value = ((value & 0xffffff) ^ 0x800000) - 0x800000; + } + else if ((operand->flags & (MN10300_OPERAND_FSREG + | MN10300_OPERAND_FDREG))) + { + /* See m10300-opc.c just before #define FSM0 for an + explanation of these variables. Note that + FMT-implied shifts are not taken into account for + FP registers. */ + unsigned long mask_low, mask_high; + int shl_low, shr_high, shl_high; + + switch (operand->bits) + { + case 5: + /* Handle regular FP registers. */ + if (operand->shift >= 0) + { + /* This is an `m' register. */ + shl_low = operand->shift; + shl_high = 8 + (8 & shl_low) + (shl_low & 4) / 4; + } + else + { + /* This is an `n' register. */ + shl_low = -operand->shift; + shl_high = shl_low / 4; + } + mask_low = 0x0f; + mask_high = 0x10; + shr_high = 4; + break; + + case 3: + /* Handle accumulators. */ + shl_low = -operand->shift; + shl_high = 0; + mask_low = 0x03; + mask_high = 0x04; + shr_high = 2; + break; + + default: + abort (); + } + value = ((((insn >> shl_high) << shr_high) & mask_high) + | ((insn >> shl_low) & mask_low)); + } + else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0) + value = ((extension >> (operand->shift)) + & ((1 << operand->bits) - 1)); + + else + value = ((insn >> (operand->shift)) + & ((1 << operand->bits) - 1)); + + if ((operand->flags & MN10300_OPERAND_SIGNED) != 0 + /* These are properly extended by the code above. */ + && ((operand->flags & MN10300_OPERAND_24BIT) == 0)) + value = ((value ^ (((unsigned long) 1) << (operand->bits - 1))) + - (((unsigned long) 1) << (operand->bits - 1))); + + if (!nocomma + && (!paren + || ((operand->flags & MN10300_OPERAND_PAREN) == 0))) + (*info->fprintf_func) (info->stream, ","); + + nocomma = 0; + + if ((operand->flags & MN10300_OPERAND_DREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "d%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_AREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "a%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_SP) != 0) + (*info->fprintf_func) (info->stream, "sp"); + + else if ((operand->flags & MN10300_OPERAND_PSW) != 0) + (*info->fprintf_func) (info->stream, "psw"); + + else if ((operand->flags & MN10300_OPERAND_MDR) != 0) + (*info->fprintf_func) (info->stream, "mdr"); + + else if ((operand->flags & MN10300_OPERAND_RREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + if (value < 8) + (*info->fprintf_func) (info->stream, "r%d", (int) value); + else if (value < 12) + (*info->fprintf_func) (info->stream, "a%d", (int) value - 8); + else + (*info->fprintf_func) (info->stream, "d%d", (int) value - 12); + } + + else if ((operand->flags & MN10300_OPERAND_XRREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + if (value == 0) + (*info->fprintf_func) (info->stream, "sp"); + else + (*info->fprintf_func) (info->stream, "xr%d", (int) value); + } + + else if ((operand->flags & MN10300_OPERAND_FSREG) != 0) + (*info->fprintf_func) (info->stream, "fs%d", (int) value); + + else if ((operand->flags & MN10300_OPERAND_FDREG) != 0) + (*info->fprintf_func) (info->stream, "fd%d", (int) value); + + else if ((operand->flags & MN10300_OPERAND_FPCR) != 0) + (*info->fprintf_func) (info->stream, "fpcr"); + + else if ((operand->flags & MN10300_OPERAND_USP) != 0) + (*info->fprintf_func) (info->stream, "usp"); + + else if ((operand->flags & MN10300_OPERAND_SSP) != 0) + (*info->fprintf_func) (info->stream, "ssp"); + + else if ((operand->flags & MN10300_OPERAND_MSP) != 0) + (*info->fprintf_func) (info->stream, "msp"); + + else if ((operand->flags & MN10300_OPERAND_PC) != 0) + (*info->fprintf_func) (info->stream, "pc"); + + else if ((operand->flags & MN10300_OPERAND_EPSW) != 0) + (*info->fprintf_func) (info->stream, "epsw"); + + else if ((operand->flags & MN10300_OPERAND_PLUS) != 0) + (*info->fprintf_func) (info->stream, "+"); + + else if ((operand->flags & MN10300_OPERAND_PAREN) != 0) + { + if (paren) + (*info->fprintf_func) (info->stream, ")"); + else + { + (*info->fprintf_func) (info->stream, "("); + nocomma = 1; + } + paren = !paren; + } + + else if ((operand->flags & MN10300_OPERAND_PCREL) != 0) + (*info->print_address_func) ((long) value + memaddr, info); + + else if ((operand->flags & MN10300_OPERAND_MEMADDR) != 0) + (*info->print_address_func) (value, info); + + else if ((operand->flags & MN10300_OPERAND_REG_LIST) != 0) + { + int comma = 0; + + (*info->fprintf_func) (info->stream, "["); + if (value & 0x80) + { + (*info->fprintf_func) (info->stream, "d2"); + comma = 1; + } + + if (value & 0x40) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "d3"); + comma = 1; + } + + if (value & 0x20) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "a2"); + comma = 1; + } + + if (value & 0x10) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "a3"); + comma = 1; + } + + if (value & 0x08) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "other"); + comma = 1; + } + + if (value & 0x04) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exreg0"); + comma = 1; + } + if (value & 0x02) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exreg1"); + comma = 1; + } + if (value & 0x01) + { + if (comma) + (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, "exother"); + comma = 1; + } + (*info->fprintf_func) (info->stream, "]"); + } + + else + (*info->fprintf_func) (info->stream, "%ld", (long) value); + } + /* All done. */ + break; + } + op++; + } + + if (!match) + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); +} + +int +print_insn_mn10300 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + unsigned int consume; + + /* First figure out how big the opcode is. */ + status = (*info->read_memory_func) (memaddr, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = *(unsigned char *) buffer; + + /* These are one byte insns. */ + if ((insn & 0xf3) == 0x00 + || (insn & 0xf0) == 0x10 + || (insn & 0xfc) == 0x3c + || (insn & 0xf3) == 0x41 + || (insn & 0xf3) == 0x40 + || (insn & 0xfc) == 0x50 + || (insn & 0xfc) == 0x54 + || (insn & 0xf0) == 0x60 + || (insn & 0xf0) == 0x70 + || ((insn & 0xf0) == 0x80 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0x90 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xa0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xb0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || (insn & 0xff) == 0xcb + || (insn & 0xfc) == 0xd0 + || (insn & 0xfc) == 0xd4 + || (insn & 0xfc) == 0xd8 + || (insn & 0xf0) == 0xe0 + || (insn & 0xff) == 0xff) + { + consume = 1; + } + + /* These are two byte insns. */ + else if ((insn & 0xf0) == 0x80 + || (insn & 0xf0) == 0x90 + || (insn & 0xf0) == 0xa0 + || (insn & 0xf0) == 0xb0 + || (insn & 0xfc) == 0x20 + || (insn & 0xfc) == 0x28 + || (insn & 0xf3) == 0x43 + || (insn & 0xf3) == 0x42 + || (insn & 0xfc) == 0x58 + || (insn & 0xfc) == 0x5c + || ((insn & 0xf0) == 0xc0 + && (insn & 0xff) != 0xcb + && (insn & 0xff) != 0xcc + && (insn & 0xff) != 0xcd) + || (insn & 0xff) == 0xf0 + || (insn & 0xff) == 0xf1 + || (insn & 0xff) == 0xf2 + || (insn & 0xff) == 0xf3 + || (insn & 0xff) == 0xf4 + || (insn & 0xff) == 0xf5 + || (insn & 0xff) == 0xf6) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + consume = 2; + } + + /* These are three byte insns. */ + else if ((insn & 0xff) == 0xf8 + || (insn & 0xff) == 0xcc + || (insn & 0xff) == 0xf9 + || (insn & 0xf3) == 0x01 + || (insn & 0xf3) == 0x02 + || (insn & 0xf3) == 0x03 + || (insn & 0xfc) == 0x24 + || (insn & 0xfc) == 0x2c + || (insn & 0xfc) == 0x30 + || (insn & 0xfc) == 0x34 + || (insn & 0xfc) == 0x38 + || (insn & 0xff) == 0xde + || (insn & 0xff) == 0xdf + || (insn & 0xff) == 0xf9 + || (insn & 0xff) == 0xcc) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 8; + status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= *(unsigned char *) buffer; + consume = 3; + } + + /* These are four byte insns. */ + else if ((insn & 0xff) == 0xfa + || (insn & 0xff) == 0xf7 + || (insn & 0xff) == 0xfb) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 4; + } + + /* These are five byte insns. */ + else if ((insn & 0xff) == 0xcd + || (insn & 0xff) == 0xdc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 5; + } + + /* These are six byte insns. */ + else if ((insn & 0xff) == 0xfd + || (insn & 0xff) == 0xfc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 6; + } + + /* Else its a seven byte insns (in theory). */ + else + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 7; + /* Handle the 5-byte extended instruction codes. */ + if ((insn & 0xfff80000) == 0xfe800000) + consume = 5; + } + + disassemble (memaddr, info, insn, consume); + + return consume; +} diff --git a/external/gpl3/gdb/dist/opcodes/m10300-opc.c b/external/gpl3/gdb/dist/opcodes/m10300-opc.c new file mode 100644 index 000000000000..0691a9ff084d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m10300-opc.c @@ -0,0 +1,1678 @@ +/* Assemble Matsushita MN10300 instructions. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is formatted at > 80 columns. Attempting to read it + on a screeen with less than 80 columns will be difficult. */ +#include "sysdep.h" +#include "opcode/mn10300.h" + + +const struct mn10300_operand mn10300_operands[] = { +#define UNUSED 0 + {0, 0, 0}, + +/* dn register in the first register operand position. */ +#define DN0 (UNUSED+1) + {2, 0, MN10300_OPERAND_DREG}, + +/* dn register in the second register operand position. */ +#define DN1 (DN0+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* dn register in the third register operand position. */ +#define DN2 (DN1+1) + {2, 4, MN10300_OPERAND_DREG}, + +/* dm register in the first register operand position. */ +#define DM0 (DN2+1) + {2, 0, MN10300_OPERAND_DREG}, + +/* dm register in the second register operand position. */ +#define DM1 (DM0+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* dm register in the third register operand position. */ +#define DM2 (DM1+1) + {2, 4, MN10300_OPERAND_DREG}, + +/* an register in the first register operand position. */ +#define AN0 (DM2+1) + {2, 0, MN10300_OPERAND_AREG}, + +/* an register in the second register operand position. */ +#define AN1 (AN0+1) + {2, 2, MN10300_OPERAND_AREG}, + +/* an register in the third register operand position. */ +#define AN2 (AN1+1) + {2, 4, MN10300_OPERAND_AREG}, + +/* am register in the first register operand position. */ +#define AM0 (AN2+1) + {2, 0, MN10300_OPERAND_AREG}, + +/* am register in the second register operand position. */ +#define AM1 (AM0+1) + {2, 2, MN10300_OPERAND_AREG}, + +/* am register in the third register operand position. */ +#define AM2 (AM1+1) + {2, 4, MN10300_OPERAND_AREG}, + +/* 8 bit unsigned immediate which may promote to a 16bit + unsigned immediate. */ +#define IMM8 (AM2+1) + {8, 0, MN10300_OPERAND_PROMOTE}, + +/* 16 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM16 (IMM8+1) + {16, 0, MN10300_OPERAND_PROMOTE}, + +/* 16 bit pc-relative immediate which may promote to a 16bit + pc-relative immediate. */ +#define IMM16_PCREL (IMM16+1) + {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, + +/* 16bit unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM16_MEM (IMM16_PCREL+1) + {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 16 bits in the main instruction + word, 16bits in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32 (IMM16_MEM+1) + {16, 0, MN10300_OPERAND_SPLIT}, + +/* 32bit pc-relative offset. */ +#define IMM32_PCREL (IMM32+1) + {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* 32bit memory offset. */ +#define IMM32_MEM (IMM32_PCREL+1) + {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 16 bits in the main instruction + word, 16bits in the extension word, low 16bits are left + shifted 8 places. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_LOWSHIFT8 (IMM32_MEM+1) + {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* 32bit immediate, high 24 bits in the main instruction + word, 8 in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) + {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* 32bit immediate, high 24 bits in the main instruction + word, 8 in the extension word, low 8 bits are left + shifted 16 places. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) + {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, + +/* Stack pointer. */ +#define SP (IMM32_HIGH24_LOWSHIFT16+1) + {8, 0, MN10300_OPERAND_SP}, + +/* Processor status word. */ +#define PSW (SP+1) + {0, 0, MN10300_OPERAND_PSW}, + +/* MDR register. */ +#define MDR (PSW+1) + {0, 0, MN10300_OPERAND_MDR}, + +/* Index register. */ +#define DI (MDR+1) + {2, 2, MN10300_OPERAND_DREG}, + +/* 8 bit signed displacement, may promote to 16bit signed displacement. */ +#define SD8 (DI+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 16 bit signed displacement, may promote to 32bit displacement. */ +#define SD16 (SD8+1) + {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 8 bit signed displacement that can not promote. */ +#define SD8N (SD16+1) + {8, 0, MN10300_OPERAND_SIGNED}, + +/* 8 bit pc-relative displacement. */ +#define SD8N_PCREL (SD8N+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, + +/* 8 bit signed displacement shifted left 8 bits in the instruction. */ +#define SD8N_SHIFT8 (SD8N_PCREL+1) + {8, 8, MN10300_OPERAND_SIGNED}, + +/* 8 bit signed immediate which may promote to 16bit signed immediate. */ +#define SIMM8 (SD8N_SHIFT8+1) + {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 16 bit signed immediate which may promote to 32bit immediate. */ +#define SIMM16 (SIMM8+1) + {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* Either an open paren or close paren. */ +#define PAREN (SIMM16+1) + {0, 0, MN10300_OPERAND_PAREN}, + +/* dn register that appears in the first and second register positions. */ +#define DN01 (PAREN+1) + {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, + +/* an register that appears in the first and second register positions. */ +#define AN01 (DN01+1) + {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, + +/* 16bit pc-relative displacement which may promote to 32bit pc-relative + displacement. */ +#define D16_SHIFT (AN01+1) + {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, + +/* 8 bit immediate found in the extension word. */ +#define IMM8E (D16_SHIFT+1) + {8, 0, MN10300_OPERAND_EXTENDED}, + +/* Register list found in the extension word shifted 8 bits left. */ +#define REGSE_SHIFT8 (IMM8E+1) + {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, + +/* Register list shifted 8 bits left. */ +#define REGS_SHIFT8 (REGSE_SHIFT8 + 1) + {8, 8, MN10300_OPERAND_REG_LIST}, + +/* Reigster list. */ +#define REGS (REGS_SHIFT8+1) + {8, 0, MN10300_OPERAND_REG_LIST}, + +/* UStack pointer. */ +#define USP (REGS+1) + {0, 0, MN10300_OPERAND_USP}, + +/* SStack pointer. */ +#define SSP (USP+1) + {0, 0, MN10300_OPERAND_SSP}, + +/* MStack pointer. */ +#define MSP (SSP+1) + {0, 0, MN10300_OPERAND_MSP}, + +/* PC . */ +#define PC (MSP+1) + {0, 0, MN10300_OPERAND_PC}, + +/* 4 bit immediate for syscall. */ +#define IMM4 (PC+1) + {4, 0, 0}, + +/* Processor status word. */ +#define EPSW (IMM4+1) + {0, 0, MN10300_OPERAND_EPSW}, + +/* rn register in the first register operand position. */ +#define RN0 (EPSW+1) + {4, 0, MN10300_OPERAND_RREG}, + +/* rn register in the fourth register operand position. */ +#define RN2 (RN0+1) + {4, 4, MN10300_OPERAND_RREG}, + +/* rm register in the first register operand position. */ +#define RM0 (RN2+1) + {4, 0, MN10300_OPERAND_RREG}, + +/* rm register in the second register operand position. */ +#define RM1 (RM0+1) + {4, 2, MN10300_OPERAND_RREG}, + +/* rm register in the third register operand position. */ +#define RM2 (RM1+1) + {4, 4, MN10300_OPERAND_RREG}, + +#define RN02 (RM2+1) + {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, + +#define XRN0 (RN02+1) + {4, 0, MN10300_OPERAND_XRREG}, + +#define XRM2 (XRN0+1) + {4, 4, MN10300_OPERAND_XRREG}, + +/* + for autoincrement */ +#define PLUS (XRM2+1) + {0, 0, MN10300_OPERAND_PLUS}, + +#define XRN02 (PLUS+1) + {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, + +/* Ick */ +#define RD0 (XRN02+1) + {4, -8, MN10300_OPERAND_RREG}, + +#define RD2 (RD0+1) + {4, -4, MN10300_OPERAND_RREG}, + +/* 8 unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM8_MEM (RD2+1) + {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, + +/* Index register. */ +#define RI (IMM8_MEM+1) + {4, 4, MN10300_OPERAND_RREG}, + +/* 24 bit signed displacement, may promote to 32bit displacement. */ +#define SD24 (RI+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, + +/* 24 bit unsigned immediate which may promote to a 32bit + unsigned immediate. */ +#define IMM24 (SD24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, + +/* 24 bit signed immediate which may promote to a 32bit + signed immediate. */ +#define SIMM24 (IMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, + +/* 24bit unsigned displacement in a memory operation which + may promote to a 32bit displacement. */ +#define IMM24_MEM (SIMM24+1) + {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, +/* 32bit immediate, high 8 bits in the main instruction + word, 24 in the extension word. + + The "bits" field indicates how many bits are in the + main instruction word for MN10300_OPERAND_SPLIT! */ +#define IMM32_HIGH8 (IMM24_MEM+1) + {8, 0, MN10300_OPERAND_SPLIT}, + +/* Similarly, but a memory address. */ +#define IMM32_HIGH8_MEM (IMM32_HIGH8+1) + {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, + +/* rm register in the seventh register operand position. */ +#define RM6 (IMM32_HIGH8_MEM+1) + {4, 12, MN10300_OPERAND_RREG}, + +/* rm register in the fifth register operand position. */ +#define RN4 (RM6+1) + {4, 8, MN10300_OPERAND_RREG}, + +/* 4 bit immediate for dsp instructions. */ +#define IMM4_2 (RN4+1) + {4, 4, 0}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_2 (IMM4_2+1) + {4, 4, MN10300_OPERAND_SIGNED}, + +/* 4 bit immediate for dsp instructions. */ +#define SIMM4_6 (SIMM4_2+1) + {4, 12, MN10300_OPERAND_SIGNED}, + +#define FPCR (SIMM4_6+1) + {0, 0, MN10300_OPERAND_FPCR}, + +/* We call f[sd]m registers those whose most significant bit is stored + * within the opcode half-word, i.e., in a bit on the left of the 4 + * least significant bits, and f[sd]n registers those whose most + * significant bit is stored at the end of the full word, after the 4 + * least significant bits. They're not numbered after their position + * in the mnemonic asm instruction, but after their position in the + * opcode word, i.e., depending on the amount of shift they need. + * + * The additional bit is shifted as follows: for `n' registers, it + * will be shifted by (|shift|/4); for `m' registers, it will be + * shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose + * specifications are only 3-bits long, the two least-significant bits + * are shifted by 16, and the most-significant bit is shifted by -2 + * (i.e., it's stored in the least significant bit of the full + * word). */ + +/* fsm register in the first register operand position. */ +#define FSM0 (FPCR+1) + {5, 0, MN10300_OPERAND_FSREG }, + +/* fsm register in the second register operand position. */ +#define FSM1 (FSM0+1) + {5, 4, MN10300_OPERAND_FSREG }, + +/* fsm register in the third register operand position. */ +#define FSM2 (FSM1+1) + {5, 8, MN10300_OPERAND_FSREG }, + +/* fsm register in the fourth register operand position. */ +#define FSM3 (FSM2+1) + {5, 12, MN10300_OPERAND_FSREG }, + +/* fsn register in the first register operand position. */ +#define FSN1 (FSM3+1) + {5, -4, MN10300_OPERAND_FSREG }, + +/* fsn register in the second register operand position. */ +#define FSN2 (FSN1+1) + {5, -8, MN10300_OPERAND_FSREG }, + +/* fsm register in the third register operand position. */ +#define FSN3 (FSN2+1) + {5, -12, MN10300_OPERAND_FSREG }, + +/* fsm accumulator, in the fourth register operand position. */ +#define FSACC (FSN3+1) + {3, -16, MN10300_OPERAND_FSREG }, + +/* fdm register in the first register operand position. */ +#define FDM0 (FSACC+1) + {5, 0, MN10300_OPERAND_FDREG }, + +/* fdm register in the second register operand position. */ +#define FDM1 (FDM0+1) + {5, 4, MN10300_OPERAND_FDREG }, + +/* fdm register in the third register operand position. */ +#define FDM2 (FDM1+1) + {5, 8, MN10300_OPERAND_FDREG }, + +/* fdm register in the fourth register operand position. */ +#define FDM3 (FDM2+1) + {5, 12, MN10300_OPERAND_FDREG }, + +/* fdn register in the first register operand position. */ +#define FDN1 (FDM3+1) + {5, -4, MN10300_OPERAND_FDREG }, + +/* fdn register in the second register operand position. */ +#define FDN2 (FDN1+1) + {5, -8, MN10300_OPERAND_FDREG }, + +/* fdn register in the third register operand position. */ +#define FDN3 (FDN2+1) + {5, -12, MN10300_OPERAND_FDREG }, + +} ; + +#define MEM(ADDR) PAREN, ADDR, PAREN +#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN +#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN +#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS } + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. */ + +const struct mn10300_opcode mn10300_opcodes[] = { +{ "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, +{ "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, +{ "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, +{ "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, +{ "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}}, +{ "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}}, +{ "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}}, +{ "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}}, +{ "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}}, +{ "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}}, +{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}}, +{ "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}}, +{ "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}}, +{ "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}}, +{ "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}}, +{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}}, +{ "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}}, +{ "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}}, +{ "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}}, +{ "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}}, +{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}}, +{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}}, +{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, +{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}}, +{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}}, +{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}}, +{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}}, +{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, +{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}}, +{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}}, +{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}}, + +{ "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}}, +{ "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}}, +{ "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}}, +{ "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}}, +{ "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}}, +{ "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}}, +{ "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}}, +{ "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}}, +{ "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}}, +{ "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}}, +{ "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}}, +{ "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}}, +{ "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}}, +{ "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}}, +{ "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}}, +{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, +{ "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, +{ "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, +{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, +{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, +{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, +/* These must come after most of the other move instructions to avoid matching + a symbolic name with IMMxx operands. Ugh. */ +{ "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}}, +{ "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}}, +{ "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}}, +{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}}, +{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}}, +{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}}, +{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}}, +{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}}, +/* These non-promoting variants need to come after all the other memory + moves. */ +{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}}, +/* These are the same as the previous non-promoting versions. The am33 + does not have restrictions on the offsets used to load/store the stack + pointer. */ +{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, +{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, +/* These must come last so that we favor shorter move instructions for + loading immediates into d0-d3/a0-a3. */ +{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}}, +{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}}, +{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}}, +{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, + +{ "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, +{ "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}}, +{ "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}}, +{ "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, +{ "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, +{ "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, +{ "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, +{ "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}}, +{ "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, +{ "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, + +{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}}, +{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}}, +{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}}, +{ "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}}, +{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}}, +{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}}, +{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}}, +{ "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}}, +{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, +{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}}, +{ "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}}, +{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}}, +{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}}, +{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}}, +{ "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}}, +{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, +{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, +{ "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}}, +{ "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}}, +{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, +{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}}, +{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}}, +{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}}, +{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}}, +{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}}, +{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}}, +{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}}, +{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}}, +{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}}, +{ "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}}, +{ "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}}, +{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}}, +{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}}, +{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}}, +{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}}, +{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}}, +{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}}, +{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}}, +{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}}, +{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}}, +{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}}, +{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}}, +{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}}, +{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}}, +{ "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}}, +{ "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}}, +{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}}, +{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}}, +{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}}, +{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}}, +{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}}, +{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}}, +{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}}, + +{ "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, +{ "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, +{ "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, +{ "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, + +{ "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}}, +{ "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}}, +{ "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, +{ "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}}, +{ "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}}, +{ "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}}, +{ "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}}, +{ "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}}, +{ "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}}, +{ "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}}, +{ "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}, +{ "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}}, +{ "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}}, +{ "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}}, +{ "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}}, +{ "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}}, +{ "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}}, +{ "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}}, +{ "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}}, +{ "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}}, +{ "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}}, +{ "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}}, +{ "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}}, +{ "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, +{ "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, +{ "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}}, +{ "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}}, +{ "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, + +{ "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the + them to match last since they do not promote. */ +{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "btst", 0xfe820000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, +{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, + +{ "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "bset", 0xfe800000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, +{ "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}}, + +{ "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}}, +{ "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}}, +{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}}, +{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, + +{ "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}}, +{ "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, +{ "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}}, +{ "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}}, +{ "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}}, +{ "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}}, +{ "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}}, + +{ "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}}, +{ "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}}, +{ "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}}, + +{ "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, +{ "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}}, +{ "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}}, + +{ "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}}, +{ "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +{ "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbne", 0xf8d100, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbge", 0xf8d300, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fblt", 0xf8d400, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fble", 0xf8d500, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fblg", 0xf8d700, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbug", 0xf8d900, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbul", 0xf8db00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, +{ "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}}, + +{ "fleq", 0xf0d0, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flne", 0xf0d1, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flgt", 0xf0d2, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flge", 0xf0d3, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "fllt", 0xf0d4, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flle", 0xf0d5, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "fluo", 0xf0d6, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "fllg", 0xf0d7, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flleg", 0xf0d8, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flug", 0xf0d9, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "fluge", 0xf0da, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flul", 0xf0db, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flule", 0xf0dc, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, +{ "flue", 0xf0dd, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}}, + +{ "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, +{ "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}}, +{ "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}}, +{ "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}}, +{ "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}}, +{ "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}}, +{ "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}}, +{ "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}}, + +{ "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, +{ "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}}, +{ "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}}, +{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +{ "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6, AM33_2, {MEM (RM2)}}, +{ "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6, AM33_2, {MEM (SP)}}, +{ "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}}, +{ "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7, AM33_2, {MEM2 (SD8,RM2)}}, +{ "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8, AM33_2, {MEM2 (SD24,RM2)}}, +{ "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8,RM2)}}, + +{ "fmov", 0xf92000, 0xfffe00, 0, FMT_D6, AM33_2, {MEM (RM2), FSM0}}, +{ "fmov", 0xf92200, 0xfffe00, 0, FMT_D6, AM33_2, {MEMINC (RM2), FSM0}}, +{ "fmov", 0xf92400, 0xfffef0, 0, FMT_D6, AM33_2, {MEM (SP), FSM0}}, +{ "fmov", 0xf92600, 0xfffe00, 0, FMT_D6, AM33_2, {RM2, FSM0}}, +{ "fmov", 0xf93000, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEM (RM0)}}, +{ "fmov", 0xf93100, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEMINC (RM0)}}, +{ "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6, AM33_2, {FSM1, MEM (SP)}}, +{ "fmov", 0xf93500, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, RM0}}, +{ "fmov", 0xf94000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6, AM33_2, {MEM (RM2), FDM0}}, +{ "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6, AM33_2, {MEMINC (RM2), FDM0}}, +{ "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6, AM33_2, {MEM (SP), FDM0}}, +{ "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEM (RM0)}}, +{ "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEMINC (RM0)}}, +{ "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6, AM33_2, {FDM1, MEM (SP)}}, +{ "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}}, +{ "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}}, +{ "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FSM2}}, +{ "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FSM2}}, +{ "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FSM2}}, +{ "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}}, +{ "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEM2 (SD8, RM0)}}, +{ "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEMINC2 (RM0, SIMM8)}}, +{ "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7, AM33_2, {FSM3, MEM2 (IMM8, SP)}}, +{ "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7, AM33_2, {FSN1, MEM2(RI, RM0)}}, + /* FIXME: the spec doesn't say the fd register must be even for the + * next two insns. Assuming it was a mistake in the spec. */ +{ "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FDN1}}, +{ "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7, AM33_2, {FDN1, MEM2(RI, RM0)}}, + /* END of FIXME */ +{ "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FDM2}}, +{ "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FDM2}}, +{ "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FDM2}}, +{ "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEM2 (SD8, RM0)}}, +{ "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEMINC2 (RM0, SIMM8)}}, +{ "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7, AM33_2, {FDM3, MEM2 (IMM8, SP)}}, +{ "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}}, +{ "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}}, +{ "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FSM2}}, +{ "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}}, +{ "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}}, +{ "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8, AM33_2, {FSM3, MEM2 (IMM24, SP)}}, +{ "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}}, +{ "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}}, +{ "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FDM2}}, +{ "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}}, +{ "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}}, +{ "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8, AM33_2, {FDM3, MEM2 (IMM24, SP)}}, +{ "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}}, +{ "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FSM2}}, +{ "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FSM2}}, +{ "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FSM2}}, +{ "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM2}}, +{ "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, RM0)}}, +{ "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}}, +{ "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, SP)}}, +{ "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FDM2}}, +{ "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FDM2}}, +{ "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FDM2}}, +{ "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, RM0)}}, +{ "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}}, +{ "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, SP)}}, + + /* FIXME: these are documented in the instruction bitmap, but not in + * the instruction manual. */ +{ "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10,AM33_2, {FSN3, FDN1}}, +{ "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10,AM33_2, {FDN3, FSN1}}, + /* END of FIXME */ + +{ "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, +{ "fabs", 0xf94400, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, +{ "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, + +{ "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, +{ "fneg", 0xf94600, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, +{ "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, + +{ "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, +{ "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, +{ "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, + + /* FIXME: this is documented in the instruction bitmap, but not in + * the instruction manual. */ +{ "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}}, +{ "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}}, +{ "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}}, +{ "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}}, + /* END of FIXME */ + +{ "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3}}, + +{ "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, +{ "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, +{ "fadd", 0xf96000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, + +{ "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, +{ "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, +{ "fsub", 0xf96400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, + +{ "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, +{ "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, +{ "fmul", 0xf97000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, + +{ "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}}, +{ "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}}, +{ "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}}, +{ "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}}, +{ "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}}, + +{ "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, +{ "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, +{ "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, +{ "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}}, + +/* UDF instructions. */ +{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}}, +{ "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}}, +{ "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}}, +{ "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, +{ "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}}, +{ "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}}, +{ "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}}, + +{ "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}}, +{ "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}}, +{ "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, +{ "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, +{ "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, +{ "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}}, +{ "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}}, +{ "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}}, +{ "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +{ "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}}, + +{ "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}}, +{ "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}}, +{ "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}}, + +/* Extension. We need some instruction to trigger "emulated syscalls" + for our simulator. */ +{ "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}}, +{ "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}}, + +/* Extension. When talking to the simulator, gdb requires some instruction + that will trigger a "breakpoint" (really just an instruction that isn't + otherwise used by the tools. This instruction must be the same size + as the smallest instruction on the target machine. In the case of the + mn10x00 the "break" instruction must be one byte. 0xff is available on + both mn10x00 architectures. */ +{ "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}}, + +{ "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}}, +{ "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}}, +{ "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}}, +{ "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}}, +{ "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +{ "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}}, +{ "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}}, +/* Ugh. Synthetic instructions. */ +{ "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }}, +{ "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}}, +{ "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}}, +{ "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}}, +{ "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}}, +{ "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}}, +{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, +{ "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}}, + +{ 0, 0, 0, 0, 0, 0, {0}}, + +} ; + +const int mn10300_num_opcodes = + sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); + + diff --git a/external/gpl3/gdb/dist/opcodes/m32c-asm.c b/external/gpl3/gdb/dist/opcodes/m32c-asm.c new file mode 100644 index 000000000000..13ab3ca187eb --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-asm.c @@ -0,0 +1,1992 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +#include "safe-ctype.h" + +#define MACH_M32C 5 /* Must match md_begin. */ + +static int +m32c_cgen_isa_register (const char **strp) + { + int u; + const char *s = *strp; + static char * m32c_register_names [] = + { + "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h", + "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf", + "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0", + "dma1", "dra0", "dra1", "dsa0", "dsa1", 0 + }; + + for (u = 0; m32c_register_names[u]; u++) + { + int len = strlen (m32c_register_names[u]); + + if (memcmp (m32c_register_names[u], s, len) == 0 + && (s[len] == 0 || ! ISALNUM (s[len]))) + return 1; + } + return 0; +} + +#define PARSE_UNSIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +#define PARSE_SIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +static const char * +parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + PARSE_UNSIGNED; + + if (value > 0x3f) + return _("imm:6 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value = 0; + long have_zero = 0; + + if (strncasecmp (*strp, "%dsp8(", 6) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma val; + + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8, + & result_type, & val); + if (**strp != ')') + return _("missing `)'"); + (*strp) ++; + + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + return _("%dsp8() takes a symbolic address, not a number"); + + value = val; + *valuep = value; + return errmsg; + } + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_UNSIGNED; + + if (value > 0xff) + return _("dsp:8 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed4 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_SIGNED; + + if (value < -8 || value > 7) + return _("Immediate is out of range -8 to 7"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("Immediate is out of range -8 to 7"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed4n (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_SIGNED; + + if (value < -7 || value > 8) + return _("Immediate is out of range -7 to 8"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("Immediate is out of range -7 to 8"); + + *valuep = -value; + return 0; +} + +static const char * +parse_signed8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value = 0; + + if (strncasecmp (*strp, "%hi8(", 5) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma val; + + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8, + & result_type, & val); + if (**strp != ')') + return _("missing `)'"); + (*strp) ++; + + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + val >>= 16; + + value = val; + *valuep = value; + return errmsg; + } + + PARSE_SIGNED; + + if (value <= 255 && value > 127) + value -= 0x100; + + if (value < -128 || value > 127) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value = 0; + long have_zero = 0; + + if (strncasecmp (*strp, "%dsp16(", 7) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma val; + + *strp += 7; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, + & result_type, & val); + if (**strp != ')') + return _("missing `)'"); + (*strp) ++; + + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + return _("%dsp16() takes a symbolic address, not a number"); + + value = val; + *valuep = value; + return errmsg; + } + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffff) + return _("dsp:16 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp24. */ + if (cd->machs == MACH_M32C && ! have_zero && value == 0 + && (strncmp (*strp, "[a", 2) == 0 + || **strp == ',' + || **strp == 0)) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value = 0; + + if (strncasecmp (*strp, "%lo16(", 6) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma val; + + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + & result_type, & val); + if (**strp != ')') + return _("missing `)'"); + (*strp) ++; + + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + val &= 0xffff; + + value = val; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%hi16(", 6) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma val; + + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + & result_type, & val); + if (**strp != ')') + return _("missing `)'"); + (*strp) ++; + + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + val >>= 16; + + value = val; + *valuep = value; + return errmsg; + } + + PARSE_SIGNED; + + if (value <= 65535 && value > 32767) + value -= 0x10000; + + if (value < -32768 || value > 32767) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xfffff) + return _("dsp:20 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffffff) + return _("dsp:24 immediate is out of range"); + + *valuep = value; + return 0; +} + +/* This should only be used for #imm->reg. */ +static const char * +parse_signed24 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 0xffffff && value > 0x7fffff) + value -= 0x1000000; + + if (value > 0xffffff) + return _("dsp:24 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed32 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + *valuep = value; + return 0; +} + +static const char * +parse_imm1_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 2) + return _("immediate is out of range 1-2"); + + *valuep = value; + return 0; +} + +static const char * +parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 8) + return _("immediate is out of range 1-8"); + + *valuep = value; + return 0; +} + +static const char * +parse_bit3_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 0 || value > 7) + return _("immediate is out of range 0-7"); + + *valuep = value; + return 0; +} + +static const char * +parse_lab_5_3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + int opinfo, + enum cgen_parse_operand_result *type_addr, + bfd_vma *valuep) +{ + const char *errmsg = 0; + bfd_vma value; + enum cgen_parse_operand_result op_res; + + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, + opinfo, & op_res, & value); + + if (type_addr) + *type_addr = op_res; + + if (op_res == CGEN_PARSE_OPERAND_RESULT_QUEUED) + { + /* This is a hack; the field cannot handle near-zero signed + offsets that CGEN wants to put in to indicate an "empty" + operand at first. */ + *valuep = 2; + return 0; + } + if (errmsg) + return errmsg; + + if (value < 2 || value > 9) + return _("immediate is out of range 2-9"); + + *valuep = value; + return 0; +} + +static const char * +parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 15) + return _("Bit number for indexing general register is out of range 0-15"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep, + unsigned bits, int allow_syms) +{ + const char *errmsg = 0; + unsigned long bit; + unsigned long base; + const char *newp = *strp; + unsigned long long bitbase; + long have_zero = 0; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + + if (strncmp (newp, "0x0", 3) == 0 + || (newp[0] == '0' && newp[1] != 'x')) + have_zero = 1; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (unsigned long long) bit + ((unsigned long long) base * 8); + + if (bitbase >= (1ull << bits)) + return _("bit,base is out of range"); + + /* If this field may require a relocation then use larger displacement. */ + if (! have_zero && base == 0) + { + switch (allow_syms) { + case 0: + return _("bit,base out of range for symbol"); + case 1: + break; + case 2: + if (strncmp (newp, "[sb]", 4) != 0) + return _("bit,base out of range for symbol"); + break; + } + } + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep, + unsigned bits, int allow_syms) +{ + const char *errmsg = 0; + unsigned long bit; + signed long base; + const char *newp = *strp; + long long bitbase; + long long limit; + long have_zero = 0; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + + if (strncmp (newp, "0x0", 3) == 0 + || (newp[0] == '0' && newp[1] != 'x')) + have_zero = 1; + + errmsg = cgen_parse_signed_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (long long)bit + ((long long)base * 8); + + limit = 1ll << (bits - 1); + if (bitbase < -limit || bitbase >= limit) + return _("bit,base is out of range"); + + /* If this field may require a relocation then use larger displacement. */ + if (! have_zero && base == 0 && ! allow_syms) + return _("bit,base out of range for symbol"); + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_unsigned_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 8, 0); +} + +static const char * +parse_unsigned_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 11, 0); +} + +static const char * +parse_unsigned_bitbase16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 16, 1); +} + +static const char * +parse_unsigned_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 19, 2); +} + +static const char * +parse_unsigned_bitbase27 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 27, 1); +} + +static const char * +parse_signed_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 8, 1); +} + +static const char * +parse_signed_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 11, 0); +} + +static const char * +parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 19, 1); +} + +/* Parse the suffix as : or as nothing followed by a whitespace. */ + +static const char * +parse_suffix (const char **strp, char suffix) +{ + const char *newp = *strp; + + if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix) + newp = *strp + 2; + + if (ISSPACE (*newp)) + { + *strp = newp; + return 0; + } + + return "Invalid suffix"; /* Anything -- will not be seen. */ +} + +static const char * +parse_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 's'); +} + +static const char * +parse_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'g'); +} + +static const char * +parse_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'q'); +} + +static const char * +parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'z'); +} + +/* Parse an empty suffix. Fail if the next char is ':'. */ + +static const char * +parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == ':') + return "Unexpected suffix"; + return 0; +} + +static const char * +parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep) +{ + const char *errmsg; + signed long value; + signed long junk; + const char *newp = *strp; + + /* Parse r0[hl]. */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value); + if (errmsg) + return errmsg; + + if (*newp != ',') + return _("not a valid r0l/r0h pair"); + ++newp; + + /* Parse the second register in the pair. */ + if (value == 0) /* r0l */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk); + else + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l, & junk); + if (errmsg) + return errmsg; + + *strp = newp; + *valuep = ! value; + return 0; +} + +/* Accept .b or .w in any case. */ + +static const char * +parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '.' + && (*(*strp + 1) == 'b' || *(*strp + 1) == 'B' + || *(*strp + 1) == 'w' || *(*strp + 1) == 'W')) + { + *strp += 2; + return NULL; + } + + return _("Invalid size specifier"); +} + +/* Special check to ensure that instruction exists for given machine. */ + +int +m32c_cgen_insn_supported (CGEN_CPU_DESC cd, + const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); + + /* If attributes are absent, assume no restriction. */ + if (machs == 0) + machs = ~0; + + return ((machs & cd->machs) + && cgen_bitset_intersect_p (& isas, cd->isas)); +} + +/* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ + +static const char * +parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep, + int push) +{ + const char *errmsg = 0; + int regno = 0; + + *valuep = 0; + while (**strp && **strp != ')') + { + if (**strp == 'r' || **strp == 'R') + { + ++*strp; + regno = **strp - '0'; + if (regno > 4) + errmsg = _("Register number is not valid"); + } + else if (**strp == 'a' || **strp == 'A') + { + ++*strp; + regno = **strp - '0'; + if (regno > 2) + errmsg = _("Register number is not valid"); + regno = **strp - '0' + 4; + } + + else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0) + { + regno = 6; + ++*strp; + } + + else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0) + { + regno = 7; + ++*strp; + } + + if (push) /* Mask is reversed for push. */ + *valuep |= 0x80 >> regno; + else + *valuep |= 1 << regno; + + ++*strp; + if (**strp == ',') + { + if (*(*strp + 1) == ')') + break; + ++*strp; + } + } + + if (!*strp) + errmsg = _("Register list is not valid"); + + return errmsg; +} + +#define POP 0 +#define PUSH 1 + +static const char * +parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, POP); +} + +static const char * +parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, PUSH); +} + +/* -- dis.c */ + +const char * m32c_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +m32c_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case M32C_OPERAND_A0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a0, & junk); + break; + case M32C_OPERAND_A1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk); + break; + case M32C_OPERAND_AN16_PUSH_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1); + break; + case M32C_OPERAND_BIT16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst16_an); + break; + case M32C_OPERAND_BIT16RN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_BIT3_S : + errmsg = parse_bit3_S (cd, strp, M32C_OPERAND_BIT3_S, (long *) (& fields->f_imm3_S)); + break; + case M32C_OPERAND_BIT32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_prefixed_QI); + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI); + break; + case M32C_OPERAND_BITBASE16_16_S8 : + errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_BITBASE16_16_U16 : + errmsg = parse_unsigned_bitbase16 (cd, strp, M32C_OPERAND_BITBASE16_16_U16, (unsigned long *) (& fields->f_dsp_16_u16)); + break; + case M32C_OPERAND_BITBASE16_16_U8 : + errmsg = parse_unsigned_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_U8, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (unsigned long *) (& fields->f_bitbase16_u11_S)); + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s11_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + errmsg = parse_signed_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s19_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u11_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + errmsg = parse_unsigned_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u19_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + errmsg = parse_unsigned_bitbase27 (cd, strp, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u27_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, (long *) (& fields->f_bitbase32_24_s11_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + errmsg = parse_signed_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, (long *) (& fields->f_bitbase32_24_s19_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u11_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + errmsg = parse_unsigned_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u19_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + errmsg = parse_unsigned_bitbase27 (cd, strp, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u27_prefixed)); + break; + case M32C_OPERAND_BITNO16R : + errmsg = parse_Bitno16R (cd, strp, M32C_OPERAND_BITNO16R, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_BITNO32PREFIXED : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32C_OPERAND_BITNO32PREFIXED, (unsigned long *) (& fields->f_bitno32_prefixed)); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32C_OPERAND_BITNO32UNPREFIXED, (unsigned long *) (& fields->f_bitno32_unprefixed)); + break; + case M32C_OPERAND_DSP_10_U6 : + errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_10_U6, (unsigned long *) (& fields->f_dsp_10_u6)); + break; + case M32C_OPERAND_DSP_16_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_16_S16, (long *) (& fields->f_dsp_16_s16)); + break; + case M32C_OPERAND_DSP_16_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_16_S8, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_DSP_16_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_16_U16, (unsigned long *) (& fields->f_dsp_16_u16)); + break; + case M32C_OPERAND_DSP_16_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_16_U20, (unsigned long *) (& fields->f_dsp_16_u24)); + break; + case M32C_OPERAND_DSP_16_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_16_U24, (unsigned long *) (& fields->f_dsp_16_u24)); + break; + case M32C_OPERAND_DSP_16_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_16_U8, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_DSP_24_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_24_S16, (long *) (& fields->f_dsp_24_s16)); + break; + case M32C_OPERAND_DSP_24_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_24_S8, (long *) (& fields->f_dsp_24_s8)); + break; + case M32C_OPERAND_DSP_24_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_24_U16, (unsigned long *) (& fields->f_dsp_24_u16)); + break; + case M32C_OPERAND_DSP_24_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_24_U20, (unsigned long *) (& fields->f_dsp_24_u24)); + break; + case M32C_OPERAND_DSP_24_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_24_U24, (unsigned long *) (& fields->f_dsp_24_u24)); + break; + case M32C_OPERAND_DSP_24_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_24_U8, (unsigned long *) (& fields->f_dsp_24_u8)); + break; + case M32C_OPERAND_DSP_32_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_32_S16, (long *) (& fields->f_dsp_32_s16)); + break; + case M32C_OPERAND_DSP_32_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_32_S8, (long *) (& fields->f_dsp_32_s8)); + break; + case M32C_OPERAND_DSP_32_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_32_U16, (unsigned long *) (& fields->f_dsp_32_u16)); + break; + case M32C_OPERAND_DSP_32_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_32_U20, (unsigned long *) (& fields->f_dsp_32_u24)); + break; + case M32C_OPERAND_DSP_32_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_32_U24, (unsigned long *) (& fields->f_dsp_32_u24)); + break; + case M32C_OPERAND_DSP_32_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_32_U8, (unsigned long *) (& fields->f_dsp_32_u8)); + break; + case M32C_OPERAND_DSP_40_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (long *) (& fields->f_dsp_40_s16)); + break; + case M32C_OPERAND_DSP_40_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (long *) (& fields->f_dsp_40_s8)); + break; + case M32C_OPERAND_DSP_40_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_40_U16, (unsigned long *) (& fields->f_dsp_40_u16)); + break; + case M32C_OPERAND_DSP_40_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_40_U20, (unsigned long *) (& fields->f_dsp_40_u20)); + break; + case M32C_OPERAND_DSP_40_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_40_U24, (unsigned long *) (& fields->f_dsp_40_u24)); + break; + case M32C_OPERAND_DSP_40_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_40_U8, (unsigned long *) (& fields->f_dsp_40_u8)); + break; + case M32C_OPERAND_DSP_48_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (long *) (& fields->f_dsp_48_s16)); + break; + case M32C_OPERAND_DSP_48_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (long *) (& fields->f_dsp_48_s8)); + break; + case M32C_OPERAND_DSP_48_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_48_U16, (unsigned long *) (& fields->f_dsp_48_u16)); + break; + case M32C_OPERAND_DSP_48_U20 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_48_U20, (unsigned long *) (& fields->f_dsp_48_u20)); + break; + case M32C_OPERAND_DSP_48_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_48_U24, (unsigned long *) (& fields->f_dsp_48_u24)); + break; + case M32C_OPERAND_DSP_48_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_48_U8, (unsigned long *) (& fields->f_dsp_48_u8)); + break; + case M32C_OPERAND_DSP_8_S24 : + errmsg = parse_signed24 (cd, strp, M32C_OPERAND_DSP_8_S24, (long *) (& fields->f_dsp_8_s24)); + break; + case M32C_OPERAND_DSP_8_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_8_S8, (long *) (& fields->f_dsp_8_s8)); + break; + case M32C_OPERAND_DSP_8_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_8_U16, (unsigned long *) (& fields->f_dsp_8_u16)); + break; + case M32C_OPERAND_DSP_8_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_8_U24, (unsigned long *) (& fields->f_dsp_8_u24)); + break; + case M32C_OPERAND_DSP_8_U6 : + errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_8_U6, (unsigned long *) (& fields->f_dsp_8_u6)); + break; + case M32C_OPERAND_DSP_8_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_8_U8, (unsigned long *) (& fields->f_dsp_8_u8)); + break; + case M32C_OPERAND_DST16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16AN_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst16_an_s); + break; + case M32C_OPERAND_DST16ANHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16ANSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16RNEXTQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_QI, & fields->f_dst16_rn_ext); + break; + case M32C_OPERAND_DST16RNHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l_r0h, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16RNSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32R0HI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0, & junk); + break; + case M32C_OPERAND_DST32R0QI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l, & junk); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_HI, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_QI, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst32_rn_prefixed_HI); + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_prefixed_QI); + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst32_rn_prefixed_SI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst32_rn_unprefixed_HI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst32_rn_unprefixed_SI); + break; + case M32C_OPERAND_G : + errmsg = parse_G (cd, strp, M32C_OPERAND_G, (long *) (& junk)); + break; + case M32C_OPERAND_IMM_12_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4)); + break; + case M32C_OPERAND_IMM_12_S4N : + errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_12_S4N, (long *) (& fields->f_imm_12_s4)); + break; + case M32C_OPERAND_IMM_13_U3 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3)); + break; + case M32C_OPERAND_IMM_16_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_16_HI, (long *) (& fields->f_dsp_16_s16)); + break; + case M32C_OPERAND_IMM_16_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_16_QI, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_IMM_16_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_16_SI, (long *) (& fields->f_dsp_16_s32)); + break; + case M32C_OPERAND_IMM_20_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_20_S4, (long *) (& fields->f_imm_20_s4)); + break; + case M32C_OPERAND_IMM_24_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_24_HI, (long *) (& fields->f_dsp_24_s16)); + break; + case M32C_OPERAND_IMM_24_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_24_QI, (long *) (& fields->f_dsp_24_s8)); + break; + case M32C_OPERAND_IMM_24_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_24_SI, (long *) (& fields->f_dsp_24_s32)); + break; + case M32C_OPERAND_IMM_32_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_32_HI, (long *) (& fields->f_dsp_32_s16)); + break; + case M32C_OPERAND_IMM_32_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_32_QI, (long *) (& fields->f_dsp_32_s8)); + break; + case M32C_OPERAND_IMM_32_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_32_SI, (long *) (& fields->f_dsp_32_s32)); + break; + case M32C_OPERAND_IMM_40_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_40_HI, (long *) (& fields->f_dsp_40_s16)); + break; + case M32C_OPERAND_IMM_40_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_40_QI, (long *) (& fields->f_dsp_40_s8)); + break; + case M32C_OPERAND_IMM_40_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_40_SI, (long *) (& fields->f_dsp_40_s32)); + break; + case M32C_OPERAND_IMM_48_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_48_HI, (long *) (& fields->f_dsp_48_s16)); + break; + case M32C_OPERAND_IMM_48_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_48_QI, (long *) (& fields->f_dsp_48_s8)); + break; + case M32C_OPERAND_IMM_48_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_48_SI, (long *) (& fields->f_dsp_48_s32)); + break; + case M32C_OPERAND_IMM_56_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_56_HI, (long *) (& fields->f_dsp_56_s16)); + break; + case M32C_OPERAND_IMM_56_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_56_QI, (long *) (& fields->f_dsp_56_s8)); + break; + case M32C_OPERAND_IMM_64_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_64_HI, (long *) (& fields->f_dsp_64_s16)); + break; + case M32C_OPERAND_IMM_8_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_8_HI, (long *) (& fields->f_dsp_8_s16)); + break; + case M32C_OPERAND_IMM_8_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_8_QI, (long *) (& fields->f_dsp_8_s8)); + break; + case M32C_OPERAND_IMM_8_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_8_S4, (long *) (& fields->f_imm_8_s4)); + break; + case M32C_OPERAND_IMM_8_S4N : + errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_8_S4N, (long *) (& fields->f_imm_8_s4)); + break; + case M32C_OPERAND_IMM_SH_12_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_12_s4); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_20_s4); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_8_s4); + break; + case M32C_OPERAND_IMM1_S : + errmsg = parse_imm1_S (cd, strp, M32C_OPERAND_IMM1_S, (long *) (& fields->f_imm1_S)); + break; + case M32C_OPERAND_IMM3_S : + errmsg = parse_imm3_S (cd, strp, M32C_OPERAND_IMM3_S, (long *) (& fields->f_imm3_S)); + break; + case M32C_OPERAND_LAB_16_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_16_8, 0, NULL, & value); + fields->f_lab_16_8 = value; + } + break; + case M32C_OPERAND_LAB_24_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_24_8, 0, NULL, & value); + fields->f_lab_24_8 = value; + } + break; + case M32C_OPERAND_LAB_32_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_32_8, 0, NULL, & value); + fields->f_lab_32_8 = value; + } + break; + case M32C_OPERAND_LAB_40_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_40_8, 0, NULL, & value); + fields->f_lab_40_8 = value; + } + break; + case M32C_OPERAND_LAB_5_3 : + { + bfd_vma value = 0; + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value); + fields->f_lab_5_3 = value; + } + break; + case M32C_OPERAND_LAB_8_16 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_16, 0, NULL, & value); + fields->f_lab_8_16 = value; + } + break; + case M32C_OPERAND_LAB_8_24 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_24, 0, NULL, & value); + fields->f_lab_8_24 = value; + } + break; + case M32C_OPERAND_LAB_8_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_8, 0, NULL, & value); + fields->f_lab_8_8 = value; + } + break; + case M32C_OPERAND_LAB32_JMP_S : + { + bfd_vma value = 0; + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value); + fields->f_lab32_jmp_s = value; + } + break; + case M32C_OPERAND_Q : + errmsg = parse_Q (cd, strp, M32C_OPERAND_Q, (long *) (& junk)); + break; + case M32C_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0, & junk); + break; + case M32C_OPERAND_R0H : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0h, & junk); + break; + case M32C_OPERAND_R0L : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l, & junk); + break; + case M32C_OPERAND_R1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r1, & junk); + break; + case M32C_OPERAND_R1R2R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r1r2r0, & junk); + break; + case M32C_OPERAND_R2 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r2, & junk); + break; + case M32C_OPERAND_R2R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r2r0, & junk); + break; + case M32C_OPERAND_R3 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r3, & junk); + break; + case M32C_OPERAND_R3R1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r3r1, & junk); + break; + case M32C_OPERAND_REGSETPOP : + errmsg = parse_pop_regset (cd, strp, M32C_OPERAND_REGSETPOP, (unsigned long *) (& fields->f_8_8)); + break; + case M32C_OPERAND_REGSETPUSH : + errmsg = parse_push_regset (cd, strp, M32C_OPERAND_REGSETPUSH, (unsigned long *) (& fields->f_8_8)); + break; + case M32C_OPERAND_RN16_PUSH_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_4_1); + break; + case M32C_OPERAND_S : + errmsg = parse_S (cd, strp, M32C_OPERAND_S, (long *) (& junk)); + break; + case M32C_OPERAND_SRC16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16RNHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC16RNQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src32_rn_prefixed_HI); + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src32_rn_prefixed_QI); + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_src32_rn_prefixed_SI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src32_rn_unprefixed_HI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src32_rn_unprefixed_QI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_src32_rn_unprefixed_SI); + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + errmsg = parse_r0l_r0h (cd, strp, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, (long *) (& fields->f_5_1)); + break; + case M32C_OPERAND_X : + errmsg = parse_X (cd, strp, M32C_OPERAND_X, (long *) (& junk)); + break; + case M32C_OPERAND_Z : + errmsg = parse_Z (cd, strp, M32C_OPERAND_Z, (long *) (& junk)); + break; + case M32C_OPERAND_COND16_16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND16_24 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND16_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND16C : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16c, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16j, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J5 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16j_5, & fields->f_cond16j_5); + break; + case M32C_OPERAND_COND32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond32); + break; + case M32C_OPERAND_COND32_16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND32_24 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND32_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND32_40 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_COND32J : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond32j); + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr1_32, & fields->f_21_3); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr1_32, & fields->f_13_3); + break; + case M32C_OPERAND_CR16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr_16, & fields->f_9_3); + break; + case M32C_OPERAND_CR2_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr2_32, & fields->f_13_3); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr3_32, & fields->f_21_3); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr3_32, & fields->f_13_3); + break; + case M32C_OPERAND_FLAGS16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_flags, & fields->f_9_3); + break; + case M32C_OPERAND_FLAGS32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_flags, & fields->f_13_3); + break; + case M32C_OPERAND_SCCOND32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond16); + break; + case M32C_OPERAND_SIZE : + errmsg = parse_size (cd, strp, M32C_OPERAND_SIZE, (long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const m32c_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +m32c_cgen_init_asm (CGEN_CPU_DESC cd) +{ + m32c_cgen_init_opcode_table (cd); + m32c_cgen_init_ibld_table (cd); + cd->parse_handlers = & m32c_cgen_parse_handlers[0]; + cd->parse_operand = m32c_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by m32c_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +m32c_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +m32c_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! m32c_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/m32c-desc.c b/external/gpl3/gdb/dist/opcodes/m32c-desc.c new file mode 100644 index 000000000000..39643915272c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-desc.c @@ -0,0 +1,63195 @@ +/* CPU data for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "m16c", MACH_M16C }, + { "m32c", MACH_M32C }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "m16c", ISA_M16C }, + { "m32c", ISA_M32C }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY RL_TYPE_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", RL_TYPE_NONE }, + { "JUMP", RL_TYPE_JUMP }, + { "1ADDR", RL_TYPE_1ADDR }, + { "2ADDR", RL_TYPE_2ADDR }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA m32c_cgen_isa_table[] = { + { "m16c", 32, 32, 8, 56 }, + { "m32c", 32, 32, 8, 80 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH m32c_cgen_mach_table[] = { + { "m16c", "m16c", MACH_M16C, 0 }, + { "m32c", "m32c", MACH_M32C, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr = +{ + & m32c_cgen_opval_h_gr_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] = +{ + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r1h", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = +{ + & m32c_cgen_opval_h_gr_QI_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = +{ + & m32c_cgen_opval_h_gr_HI_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] = +{ + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = +{ + & m32c_cgen_opval_h_gr_SI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] = +{ + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1l", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = +{ + & m32c_cgen_opval_h_gr_ext_QI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = +{ + & m32c_cgen_opval_h_gr_ext_HI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] = +{ + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0l = +{ + & m32c_cgen_opval_h_r0l_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] = +{ + { "r0h", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0h = +{ + & m32c_cgen_opval_h_r0h_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] = +{ + { "r1l", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1l = +{ + & m32c_cgen_opval_h_r1l_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] = +{ + { "r1h", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1h = +{ + & m32c_cgen_opval_h_r1h_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0 = +{ + & m32c_cgen_opval_h_r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] = +{ + { "r1", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1 = +{ + & m32c_cgen_opval_h_r1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] = +{ + { "r2", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r2 = +{ + & m32c_cgen_opval_h_r2_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] = +{ + { "r3", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r3 = +{ + & m32c_cgen_opval_h_r3_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] = +{ + { "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r0h", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = +{ + & m32c_cgen_opval_h_r0l_r0h_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] = +{ + { "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = +{ + & m32c_cgen_opval_h_r2r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] = +{ + { "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = +{ + & m32c_cgen_opval_h_r3r1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] = +{ + { "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = +{ + & m32c_cgen_opval_h_r1r2r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] = +{ + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar = +{ + & m32c_cgen_opval_h_ar_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] = +{ + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = +{ + & m32c_cgen_opval_h_ar_QI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] = +{ + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = +{ + & m32c_cgen_opval_h_ar_HI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] = +{ + { "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = +{ + & m32c_cgen_opval_h_ar_SI_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] = +{ + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_a0 = +{ + & m32c_cgen_opval_h_a0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] = +{ + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_a1 = +{ + & m32c_cgen_opval_h_a1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] = +{ + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 254, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16 = +{ + & m32c_cgen_opval_h_cond16_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] = +{ + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16c = +{ + & m32c_cgen_opval_h_cond16c_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] = +{ + { "le", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16j = +{ + & m32c_cgen_opval_h_cond16j_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] = +{ + { "geu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "ltu", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = +{ + & m32c_cgen_opval_h_cond16j_5_entries[0], + 12, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] = +{ + { "ltu", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "leu", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "pz", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "no", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "geu", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gtu", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond32 = +{ + & m32c_cgen_opval_h_cond32_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] = +{ + { "dct0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dct1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "svf", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "drc0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "drc1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = +{ + & m32c_cgen_opval_h_cr1_32_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] = +{ + { "intb", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "svp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vct", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = +{ + & m32c_cgen_opval_h_cr2_32_entries[0], + 7, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] = +{ + { "dma0", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "dra0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dra1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = +{ + & m32c_cgen_opval_h_cr3_32_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] = +{ + { "intbl", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "intbh", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "flg", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "isp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "sb", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fb", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = +{ + & m32c_cgen_opval_h_cr_16_entries[0], + 7, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] = +{ + { "c", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "d", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "s", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "b", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "o", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "i", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "u", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_flags = +{ + & m32c_cgen_opval_h_flags_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] = +{ + { "1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "5", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "6", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "7", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "8", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "-1", -8, {0, {{{0, 0}}}}, 0, 0 }, + { "-2", -7, {0, {{{0, 0}}}}, 0, 0 }, + { "-3", -6, {0, {{{0, 0}}}}, 0, 0 }, + { "-4", -5, {0, {{{0, 0}}}}, 0, 0 }, + { "-5", -4, {0, {{{0, 0}}}}, 0, 0 }, + { "-6", -3, {0, {{{0, 0}}}}, 0, 0 }, + { "-7", -2, {0, {{{0, 0}}}}, 0, 0 }, + { "-8", -1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_shimm = +{ + & m32c_cgen_opval_h_shimm_entries[0], + 16, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY m32c_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & m32c_cgen_ifld_table[0]; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & m32c_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & m32c_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */ + +static void +m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & m32c_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & m32c_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (m32c_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = m32c_cgen_rebuild_tables; + m32c_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +m32c_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/m32c-desc.h b/external/gpl3/gdb/dist/opcodes/m32c-desc.h new file mode 100644 index 000000000000..662a530bb57a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-desc.h @@ -0,0 +1,540 @@ +/* CPU data header for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32C_CPU_H +#define M32C_CPU_H + +#define CGEN_ARCH m32c + +/* Given symbol S, return m32c_cgen_. */ +#define CGEN_SYM(s) m32c##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_M16CBF +#define HAVE_CPU_M32CBF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 1 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 10 + +#define CGEN_INT_INSN_P 0 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 21 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 13 + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_M16C, MACH_M32C, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_M16C, ISA_M32C, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for . */ +typedef enum rl_type_attr { + RL_TYPE_NONE, RL_TYPE_JUMP, RL_TYPE_1ADDR, RL_TYPE_2ADDR +} RL_TYPE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS ((int) ISA_MAX) +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_RL_TYPE, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_RL_TYPE-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for m32c ifield types. */ +typedef enum ifield_type { + M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2 + , M32C_F_0_3, M32C_F_0_4, M32C_F_1_3, M32C_F_2_2 + , M32C_F_3_4, M32C_F_3_1, M32C_F_4_1, M32C_F_4_3 + , M32C_F_4_4, M32C_F_4_6, M32C_F_5_1, M32C_F_5_3 + , M32C_F_6_2, M32C_F_7_1, M32C_F_8_1, M32C_F_8_2 + , M32C_F_8_3, M32C_F_8_4, M32C_F_8_8, M32C_F_9_3 + , M32C_F_9_1, M32C_F_10_1, M32C_F_10_2, M32C_F_10_3 + , M32C_F_11_1, M32C_F_12_1, M32C_F_12_2, M32C_F_12_3 + , M32C_F_12_4, M32C_F_12_6, M32C_F_13_3, M32C_F_14_1 + , M32C_F_14_2, M32C_F_15_1, M32C_F_16_1, M32C_F_16_2 + , M32C_F_16_4, M32C_F_16_8, M32C_F_18_1, M32C_F_18_2 + , M32C_F_18_3, M32C_F_20_1, M32C_F_20_3, M32C_F_20_2 + , M32C_F_20_4, M32C_F_21_3, M32C_F_24_2, M32C_F_24_8 + , M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN, M32C_F_SRC32_AN_UNPREFIXED + , M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI, M32C_F_SRC32_RN_UNPREFIXED_HI + , M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI, M32C_F_DST32_RN_EXT_UNPREFIXED + , M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S, M32C_F_DST16_AN + , M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED, M32C_F_DST32_RN_UNPREFIXED_QI + , M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI, M32C_F_DST32_RN_UNPREFIXED_SI + , M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4, M32C_F_IMM_12_S4 + , M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S, M32C_F_IMM3_S + , M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8, M32C_F_DSP_10_U6 + , M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8, M32C_F_DSP_24_S8 + , M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8, M32C_F_DSP_40_S8 + , M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8, M32C_F_DSP_56_S8 + , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16 + , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16 + , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16 + , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_S24 + , M32C_F_DSP_8_U24, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24 + , M32C_F_DSP_40_U20, M32C_F_DSP_40_U24, M32C_F_DSP_40_S32, M32C_F_DSP_48_U20 + , M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32, M32C_F_DSP_32_S32 + , M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16, M32C_F_DSP_64_S16 + , M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED, M32C_F_BITNO32_UNPREFIXED, M32C_F_BITBASE16_U11_S + , M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED, M32C_F_BITBASE32_16_U19_UNPREFIXED, M32C_F_BITBASE32_16_S19_UNPREFIXED + , M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED, M32C_F_BITBASE32_24_S11_PREFIXED, M32C_F_BITBASE32_24_U19_PREFIXED + , M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED, M32C_F_LAB_5_3, M32C_F_LAB32_JMP_S + , M32C_F_LAB_8_8, M32C_F_LAB_8_16, M32C_F_LAB_8_24, M32C_F_LAB_16_8 + , M32C_F_LAB_24_8, M32C_F_LAB_32_8, M32C_F_LAB_40_8, M32C_F_COND16 + , M32C_F_COND16J_5, M32C_F_COND32, M32C_F_COND32J, M32C_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) M32C_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA + , CGEN_HW_RL_TYPE, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_RL_TYPE-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for m32c hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI + , HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI + , HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H + , HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3 + , HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0 + , HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI + , HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB + , HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT + , HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT + , HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF + , HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1 + , HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP + , HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1 + , HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C + , HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32 + , HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS + , HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX + , HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA + , CGEN_OPERAND_RL_TYPE, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_RL_TYPE-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for m32c operand types. */ +typedef enum cgen_operand_type { + M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI + , M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI + , M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI + , M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI + , M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI + , M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI + , M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI + , M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI + , M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S + , M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0 + , M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L + , M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0 + , M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI + , M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI + , M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI + , M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED + , M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB + , M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP + , M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6 + , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24 + , M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16 + , M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16 + , M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24 + , M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16 + , M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16 + , M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16 + , M32C_OPERAND_DSP_40_U20, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8 + , M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U20, M32C_OPERAND_DSP_48_U24 + , M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI + , M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4 + , M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI + , M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI + , M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI + , M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI + , M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI + , M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BIT3_S + , M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8 + , M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED + , M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED + , M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED + , M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8 + , M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8 + , M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT + , M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT + , M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24 + , M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32 + , M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5 + , M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16 + , M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32 + , M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z + , M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X + , M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX + , M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI + , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI + , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI + , M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI + , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI + , M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI + , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI + , M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI + , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI + , M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI + , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI + , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI + , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI + , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI + , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI + , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI + , M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI + , M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI + , M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI + , M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI + , M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI + , M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI + , M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI + , M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI + , M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI + , M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI + , M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI + , M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI + , M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI + , M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI + , M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI + , M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED + , M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT + , M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE + , M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED + , M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED + , M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED + , M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI + , M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI + , M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI + , M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI + , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI + , M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI + , M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI + , M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI + , M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI + , M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI + , M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI + , M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI + , M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI + , M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI + , M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_16SA_QI, M32C_OPERAND_DST16_16_20AR_QI + , M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_16SA_HI + , M32C_OPERAND_DST16_16_20AR_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI + , M32C_OPERAND_DST16_16_16SA_SI, M32C_OPERAND_DST16_16_20AR_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI + , M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI + , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI + , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI + , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI + , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC + , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED + , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED + , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8 + , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI + , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI + , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S + , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 902 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_RL_TYPE, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_RL_TYPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld m32c_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD m32c_cgen_opval_h_gr; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_SI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0l; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1l; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1; +extern CGEN_KEYWORD m32c_cgen_opval_h_r2; +extern CGEN_KEYWORD m32c_cgen_opval_h_r3; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r2r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_r3r1; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_SI; +extern CGEN_KEYWORD m32c_cgen_opval_h_a0; +extern CGEN_KEYWORD m32c_cgen_opval_h_a1; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16c; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr1_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr2_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr3_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr_16; +extern CGEN_KEYWORD m32c_cgen_opval_h_flags; +extern CGEN_KEYWORD m32c_cgen_opval_h_shimm; + +extern const CGEN_HW_ENTRY m32c_cgen_hw_table[]; + + + +#endif /* M32C_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/m32c-dis.c b/external/gpl3/gdb/dist/opcodes/m32c-dis.c new file mode 100644 index 000000000000..728333327e4e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-dis.c @@ -0,0 +1,1312 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +#include "elf/m32c.h" +#include "elf-bfd.h" + +/* Always print the short insn format suffix as ':'. */ + +static void +print_suffix (void * dis_info, char suffix) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ":%c", suffix); +} + +static void +print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 's'); +} + + +static void +print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'g'); +} + +static void +print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'q'); +} + +static void +print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'z'); +} + +/* Print the empty suffix. */ + +static void +print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + return; +} + +static void +print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + if (value == 0) + (*info->fprintf_func) (info->stream, "r0h,r0l"); + else + (*info->fprintf_func) (info->stream, "r0l,r0h"); +} + +static void +print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + unsigned long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); +} + +static void +print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); +} + +static void +print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + /* Always print the size as '.w'. */ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ".w"); +} + +#define POP 0 +#define PUSH 1 + +static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); + +/* Print a set of registers, R0,R1,A0,A1,SB,FB. */ + +static void +print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED, + int push) +{ + static char * m16c_register_names [] = + { + "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" + }; + disassemble_info *info = dis_info; + int mask; + int reg_index = 0; + char* comma = ""; + + if (push) + mask = 0x80; + else + mask = 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); + comma = ","; + } + + for (reg_index = 1; reg_index <= 7; ++reg_index) + { + if (push) + mask >>= 1; + else + mask <<= 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s%s", comma, + m16c_register_names [reg_index]); + comma = ","; + } + } +} + +static void +print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, POP); +} + +static void +print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, PUSH); +} + +static void +print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld", -value); +} + +void m32c_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +m32c_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case M32C_OPERAND_A0 : + print_keyword (cd, info, & m32c_cgen_opval_h_a0, 0, 0); + break; + case M32C_OPERAND_A1 : + print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0); + break; + case M32C_OPERAND_AN16_PUSH_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0); + break; + case M32C_OPERAND_BIT16AN : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_BIT16RN : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_BIT3_S : + print_normal (cd, info, fields->f_imm3_S, 0|(1<f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_BITBASE16_16_S8 : + print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<f_dsp_16_u16, 0, pc, length); + break; + case M32C_OPERAND_BITBASE16_16_U8 : + print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<f_bitbase32_16_s11_unprefixed, 0|(1<f_bitbase32_16_s19_unprefixed, 0|(1<f_bitbase32_16_u11_unprefixed, 0|(1<f_bitbase32_16_u19_unprefixed, 0|(1<f_bitbase32_16_u27_unprefixed, 0|(1<f_bitbase32_24_s11_prefixed, 0|(1<f_bitbase32_24_s19_prefixed, 0|(1<f_bitbase32_24_u11_prefixed, 0|(1<f_bitbase32_24_u19_prefixed, 0|(1<f_bitbase32_24_u27_prefixed, 0|(1<f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_BITNO32PREFIXED : + print_normal (cd, info, fields->f_bitno32_prefixed, 0, pc, length); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + print_normal (cd, info, fields->f_bitno32_unprefixed, 0, pc, length); + break; + case M32C_OPERAND_DSP_10_U6 : + print_normal (cd, info, fields->f_dsp_10_u6, 0, pc, length); + break; + case M32C_OPERAND_DSP_16_S16 : + print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_16_U20 : + print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<f_dsp_16_u24, 0|(1<f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_24_S16 : + print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<f_dsp_24_s8, 0|(1<f_dsp_24_u16, 0|(1<f_dsp_24_u24, 0|(1<f_dsp_24_u24, 0|(1<f_dsp_24_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_S16 : + print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U20 : + print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U24 : + print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U8 : + print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_S16 : + print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_U20 : + print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_U24 : + print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_U8 : + print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_48_S16 : + print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_48_U20 : + print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<f_dsp_48_u24, 0|(1<f_dsp_48_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_S24 : + print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<f_dsp_8_s8, 0|(1<f_dsp_8_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U24 : + print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U6 : + print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U8 : + print_normal (cd, info, fields->f_dsp_8_u8, 0, pc, length); + break; + case M32C_OPERAND_DST16AN : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16AN_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an_s, 0); + break; + case M32C_OPERAND_DST16ANHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16ANQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16ANQI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_rn_QI_s, 0); + break; + case M32C_OPERAND_DST16ANSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16RNEXTQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst16_rn_ext, 0); + break; + case M32C_OPERAND_DST16RNHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST16RNQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST16RNQI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0l_r0h, fields->f_dst16_rn_QI_s, 0); + break; + case M32C_OPERAND_DST16RNSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32R0HI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); + break; + case M32C_OPERAND_DST32R0QI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_HI, fields->f_dst32_rn_ext_unprefixed, 0); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst32_rn_ext_unprefixed, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_prefixed_HI, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_prefixed_SI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_unprefixed_HI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_unprefixed_SI, 0); + break; + case M32C_OPERAND_G : + print_G (cd, info, 0, 0|(1<f_imm_12_s4, 0|(1<f_imm_12_s4, 0|(1<f_imm_13_u3, 0|(1<f_dsp_16_s16, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_s32, 0|(1<f_imm_20_s4, 0|(1<f_dsp_24_s16, 0|(1<f_dsp_24_s8, 0|(1<f_dsp_24_s32, 0|(1<f_dsp_32_s16, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_s32, 0|(1<f_dsp_40_s16, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_s32, 0|(1<f_dsp_48_s16, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_s32, 0|(1<f_dsp_56_s16, 0|(1<f_dsp_56_s8, 0|(1<f_dsp_64_s16, 0|(1<f_dsp_8_s16, 0|(1<f_dsp_8_s8, 0|(1<f_imm_8_s4, 0|(1<f_imm_8_s4, 0|(1<f_imm_12_s4, 0); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_20_s4, 0); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_8_s4, 0); + break; + case M32C_OPERAND_IMM1_S : + print_normal (cd, info, fields->f_imm1_S, 0|(1<f_imm3_S, 0|(1<f_lab_16_8, 0|(1<f_lab_24_8, 0|(1<f_lab_32_8, 0|(1<f_lab_40_8, 0|(1<f_lab_5_3, 0|(1<f_lab_8_16, 0|(1<f_lab_8_24, 0|(1<f_lab_8_8, 0|(1<f_lab32_jmp_s, 0|(1<f_8_8, 0, pc, length); + break; + case M32C_OPERAND_REGSETPUSH : + print_push_regset (cd, info, fields->f_8_8, 0, pc, length); + break; + case M32C_OPERAND_RN16_PUSH_S : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_4_1, 0); + break; + case M32C_OPERAND_S : + print_S (cd, info, 0, 0|(1<f_src16_an, 0); + break; + case M32C_OPERAND_SRC16ANHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src16_an, 0); + break; + case M32C_OPERAND_SRC16ANQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src16_an, 0); + break; + case M32C_OPERAND_SRC16RNHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src16_rn, 0); + break; + case M32C_OPERAND_SRC16RNQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src16_rn, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_prefixed_HI, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_prefixed_SI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_unprefixed_HI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_unprefixed_SI, 0); + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + print_r0l_r0h (cd, info, fields->f_5_1, 0|(1<f_dsp_16_u8, 0); + break; + case M32C_OPERAND_COND16_24 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_24_u8, 0); + break; + case M32C_OPERAND_COND16_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_32_u8, 0); + break; + case M32C_OPERAND_COND16C : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16c, fields->f_cond16, 0); + break; + case M32C_OPERAND_COND16J : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16j, fields->f_cond16, 0); + break; + case M32C_OPERAND_COND16J5 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16j_5, fields->f_cond16j_5, 0); + break; + case M32C_OPERAND_COND32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32, 0|(1<f_dsp_16_u8, 0); + break; + case M32C_OPERAND_COND32_24 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_24_u8, 0); + break; + case M32C_OPERAND_COND32_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_32_u8, 0); + break; + case M32C_OPERAND_COND32_40 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_40_u8, 0); + break; + case M32C_OPERAND_COND32J : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32j, 0|(1<f_21_3, 0); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_CR16 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr_16, fields->f_9_3, 0); + break; + case M32C_OPERAND_CR2_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr2_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_21_3, 0); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_FLAGS16 : + print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_9_3, 0); + break; + case M32C_OPERAND_FLAGS32 : + print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_13_3, 0); + break; + case M32C_OPERAND_SCCOND32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond16, 0); + break; + case M32C_OPERAND_SIZE : + print_size (cd, info, 0, 0|(1<print_handlers = & m32c_cgen_print_handlers[0]; + cd->print_operand = m32c_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + m32c_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! m32c_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_m32c (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_m32c +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + m32c_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32c-ibld.c b/external/gpl3/gdb/dist/opcodes/m32c-ibld.c new file mode 100644 index 000000000000..e83d8e0e5c76 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-ibld.c @@ -0,0 +1,5290 @@ +/* Instruction building/extraction support for m32c. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * m32c_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +m32c_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT16AN : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT16RN : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT3_S : + { +{ + FLD (f_7_1) = ((((FLD (f_imm3_S)) - (1))) & (1)); + FLD (f_2_2) = ((((UINT) (((FLD (f_imm3_S)) - (1))) >> (1))) & (3)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BIT32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + { + long value = fields->f_dst32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + { + long value = fields->f_dst32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BITBASE16_16_S8 : + errmsg = insert_normal (cd, fields->f_dsp_16_s8, 0|(1<f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BITBASE16_16_U8 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + { +{ + FLD (f_bitno16_S) = ((FLD (f_bitbase16_u11_S)) & (7)); + FLD (f_dsp_8_u8) = ((((UINT) (FLD (f_bitbase16_u11_S)) >> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno16_S, 0, 0, 5, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_8_u8, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_s11_unprefixed)) & (7)); + FLD (f_dsp_16_s8) = ((INT) (FLD (f_bitbase32_16_s11_unprefixed)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_16_s8, 0|(1<> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_u19_unprefixed)) & (7)); + FLD (f_dsp_16_u16) = ((((UINT) (FLD (f_bitbase32_16_u19_unprefixed)) >> (3))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_u27_unprefixed)) & (7)); + FLD (f_dsp_16_u16) = ((((UINT) (FLD (f_bitbase32_16_u27_unprefixed)) >> (3))) & (65535)); + FLD (f_dsp_32_u8) = ((((UINT) (FLD (f_bitbase32_16_u27_unprefixed)) >> (19))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_s11_prefixed)) & (7)); + FLD (f_dsp_24_s8) = ((INT) (FLD (f_bitbase32_24_s11_prefixed)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (3))) & (255)); + FLD (f_dsp_32_s8) = ((INT) (FLD (f_bitbase32_24_s19_prefixed)) >> (11)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_s8, 0|(1<> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_u19_prefixed)) & (7)); + FLD (f_dsp_24_u8) = ((((UINT) (FLD (f_bitbase32_24_u19_prefixed)) >> (3))) & (255)); + FLD (f_dsp_32_u8) = ((((UINT) (FLD (f_bitbase32_24_u19_prefixed)) >> (11))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_u27_prefixed)) & (7)); + FLD (f_dsp_24_u8) = ((((UINT) (FLD (f_bitbase32_24_u27_prefixed)) >> (3))) & (255)); + FLD (f_dsp_32_u16) = ((((UINT) (FLD (f_bitbase32_24_u27_prefixed)) >> (11))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITNO16R : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_BITNO32PREFIXED : + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_10_U6 : + errmsg = insert_normal (cd, fields->f_dsp_10_u6, 0, 0, 10, 6, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_16_S16 : + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_16_U20 : + { +{ + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_u24)) & (65535)); + FLD (f_dsp_32_u8) = ((((UINT) (FLD (f_dsp_16_u24)) >> (16))) & (255)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_16_U24 : + { +{ + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_u24)) & (65535)); + FLD (f_dsp_32_u8) = ((((UINT) (FLD (f_dsp_16_u24)) >> (16))) & (255)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_16_U8 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_24_S16 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_s16)) & (255)); + FLD (f_dsp_32_u8) = ((((UINT) (FLD (f_dsp_24_s16)) >> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_S8 : + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U20 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_u24)) & (255)); + FLD (f_dsp_32_u16) = ((((UINT) (FLD (f_dsp_24_u24)) >> (8))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U24 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_u24)) & (255)); + FLD (f_dsp_32_u16) = ((((UINT) (FLD (f_dsp_24_u24)) >> (8))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U8 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_32_S16 : + { + long value = fields->f_dsp_32_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U20 : + { + long value = fields->f_dsp_32_u24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U24 : + { + long value = fields->f_dsp_32_u24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U8 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_40_S16 : + { + long value = fields->f_dsp_40_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_40_U20 : + { + long value = fields->f_dsp_40_u20; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 20, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_40_U24 : + { + long value = fields->f_dsp_40_u24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_40_U8 : + errmsg = insert_normal (cd, fields->f_dsp_40_u8, 0, 32, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_48_S16 : + { + long value = fields->f_dsp_48_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_48_U20 : + { +{ + FLD (f_dsp_64_u8) = ((((UINT) (FLD (f_dsp_48_u20)) >> (16))) & (15)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_u20)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_48_U24 : + { +{ + FLD (f_dsp_64_u8) = ((((UINT) (FLD (f_dsp_48_u24)) >> (16))) & (255)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_u24)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_48_U8 : + errmsg = insert_normal (cd, fields->f_dsp_48_u8, 0, 32, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_8_S24 : + { + long value = fields->f_dsp_8_s24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16)))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_8_s8, 0|(1<f_dsp_8_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_8_U24 : + { + long value = fields->f_dsp_8_u24; + value = ((((((USI) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_8_U6 : + errmsg = insert_normal (cd, fields->f_dsp_8_u6, 0, 0, 8, 6, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_8_U8 : + errmsg = insert_normal (cd, fields->f_dsp_8_u8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16AN : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16AN_S : + errmsg = insert_normal (cd, fields->f_dst16_an_s, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANHI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANQI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANQI_S : + errmsg = insert_normal (cd, fields->f_dst16_rn_QI_s, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANSI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNEXTQI : + errmsg = insert_normal (cd, fields->f_dst16_rn_ext, 0, 0, 14, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNHI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNQI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNQI_S : + errmsg = insert_normal (cd, fields->f_dst16_rn_QI_s, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNSI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_rn_ext_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_rn_ext_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + { + long value = fields->f_dst32_rn_prefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + { + long value = fields->f_dst32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + { + long value = fields->f_dst32_rn_prefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + { + long value = fields->f_dst32_rn_unprefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + { + long value = fields->f_dst32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + { + long value = fields->f_dst32_rn_unprefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<f_imm_12_s4, 0|(1<f_imm_13_u3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_IMM_16_HI : + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_16_s8, 0|(1<> (16))) & (65535)); + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_s32)) & (65535)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_20_S4 : + errmsg = insert_normal (cd, fields->f_imm_20_s4, 0|(1<> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_24_QI : + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (8))) & (16777215)); + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_s32)) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_32_HI : + { + long value = fields->f_dsp_32_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_s32; + value = EXTSISI (((((((((UINT) (value) >> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s8, 0|(1<> (24))) & (255)); + FLD (f_dsp_40_u24) = ((FLD (f_dsp_40_s32)) & (16777215)); +} + { + long value = fields->f_dsp_40_u24; + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 24, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_48_HI : + { + long value = fields->f_dsp_48_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_48_s8, 0|(1<> (16))) & (65535)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_s32)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + { + long value = fields->f_dsp_64_u16; + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 64, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_56_HI : + { +{ + FLD (f_dsp_56_u8) = ((FLD (f_dsp_56_s16)) & (255)); + FLD (f_dsp_64_u8) = ((((UINT) (FLD (f_dsp_56_s16)) >> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_56_u8, 0, 32, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_56_QI : + errmsg = insert_normal (cd, fields->f_dsp_56_s8, 0|(1<f_dsp_64_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_8_s16; + value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_8_s8, 0|(1<f_imm_8_s4, 0|(1<f_imm_8_s4, 0|(1<f_imm_12_s4, 0|(1<f_imm_20_s4, 0|(1<f_imm_8_s4, 0|(1<f_imm1_S; + value = ((value) - (1)); + errmsg = insert_normal (cd, value, 0, 0, 2, 1, 32, total_length, buffer); + } + break; + case M32C_OPERAND_IMM3_S : + { +{ + FLD (f_7_1) = ((((FLD (f_imm3_S)) - (1))) & (1)); + FLD (f_2_2) = ((((UINT) (((FLD (f_imm3_S)) - (1))) >> (1))) & (3)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_LAB_16_8 : + { + long value = fields->f_lab_16_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_24_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_32_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_40_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_5_3; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_16; + value = ((((((((value) - (((pc) + (1))))) & (255))) << (8))) | (((USI) (((((value) - (((pc) + (1))))) & (65535))) >> (8)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_24; + value = ((((((USI) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_8; + value = ((value) - (((pc) + (1)))); + errmsg = insert_normal (cd, value, 0|(1<> (1)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + errmsg = insert_normal (cd, fields->f_8_8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_REGSETPUSH : + errmsg = insert_normal (cd, fields->f_8_8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_RN16_PUSH_S : + errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16ANHI : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16ANQI : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16RNHI : + errmsg = insert_normal (cd, fields->f_src16_rn, 0, 0, 10, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16RNQI : + errmsg = insert_normal (cd, fields->f_src16_rn, 0, 0, 10, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + { + long value = fields->f_src32_rn_prefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + { + long value = fields->f_src32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + { + long value = fields->f_src32_rn_prefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + { + long value = fields->f_src32_rn_unprefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + { + long value = fields->f_src32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((USI) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + { + long value = fields->f_src32_rn_unprefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + errmsg = insert_normal (cd, fields->f_5_1, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16_24 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16_32 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16C : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16J : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16J5 : + errmsg = insert_normal (cd, fields->f_cond16j_5, 0, 0, 5, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32 : + { +{ + FLD (f_9_1) = ((((UINT) (FLD (f_cond32)) >> (3))) & (1)); + FLD (f_13_3) = ((FLD (f_cond32)) & (7)); +} + errmsg = insert_normal (cd, fields->f_9_1, 0, 0, 9, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_COND32_16 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_24 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_32 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_40 : + errmsg = insert_normal (cd, fields->f_dsp_40_u8, 0, 32, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32J : + { +{ + FLD (f_1_3) = ((((UINT) (FLD (f_cond32j)) >> (1))) & (7)); + FLD (f_7_1) = ((FLD (f_cond32j)) & (1)); +} + errmsg = insert_normal (cd, fields->f_1_3, 0, 0, 1, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + errmsg = insert_normal (cd, fields->f_21_3, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR16 : + errmsg = insert_normal (cd, fields->f_9_3, 0, 0, 9, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR2_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + errmsg = insert_normal (cd, fields->f_21_3, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_FLAGS16 : + errmsg = insert_normal (cd, fields->f_9_3, 0, 0, 9, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_FLAGS32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_SCCOND32 : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int m32c_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +m32c_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); + break; + case M32C_OPERAND_BIT16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_BIT16RN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_BIT3_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_imm3_S) = ((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (1)); +} + } + break; + case M32C_OPERAND_BIT32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_BITBASE16_16_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_BITBASE16_16_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + break; + case M32C_OPERAND_BITBASE16_16_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_bitno16_S); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_u8); + if (length <= 0) break; +{ + FLD (f_bitbase16_u11_S) = ((((FLD (f_dsp_8_u8)) << (3))) | (FLD (f_bitno16_S))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_16_s19_unprefixed) = ((((FLD (f_dsp_16_s16)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u11_unprefixed) = ((((FLD (f_dsp_16_u8)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u19_unprefixed) = ((((FLD (f_dsp_16_u16)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u27_unprefixed) = ((((FLD (f_dsp_16_u16)) << (3))) | (((((FLD (f_dsp_32_u8)) << (19))) | (FLD (f_bitno32_unprefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) << (3))) | (FLD (f_bitno32_prefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u11_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (FLD (f_bitno32_prefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_u8)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u27_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_u16)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITNO16R : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_BITNO32PREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + break; + case M32C_OPERAND_DSP_10_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 6, 32, total_length, pc, & fields->f_dsp_10_u6); + break; + case M32C_OPERAND_DSP_16_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + break; + case M32C_OPERAND_DSP_16_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_DSP_16_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + break; + case M32C_OPERAND_DSP_16_U20 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_16_u24) = ((((FLD (f_dsp_32_u8)) << (16))) | (FLD (f_dsp_16_u16))); +} + } + break; + case M32C_OPERAND_DSP_16_U24 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_16_u24) = ((((FLD (f_dsp_32_u8)) << (16))) | (FLD (f_dsp_16_u16))); +} + } + break; + case M32C_OPERAND_DSP_16_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_DSP_24_S16 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8)))))); +} + } + break; + case M32C_OPERAND_DSP_24_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + break; + case M32C_OPERAND_DSP_24_U16 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_u16) = ((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U20 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_u24) = ((((FLD (f_dsp_32_u16)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_u24) = ((((FLD (f_dsp_32_u16)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_DSP_32_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_32_s16 = value; + } + break; + case M32C_OPERAND_DSP_32_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + break; + case M32C_OPERAND_DSP_32_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + break; + case M32C_OPERAND_DSP_32_U20 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + break; + case M32C_OPERAND_DSP_32_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + break; + case M32C_OPERAND_DSP_32_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_DSP_40_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_40_s16 = value; + } + break; + case M32C_OPERAND_DSP_40_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_40_s8); + break; + case M32C_OPERAND_DSP_40_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_40_u16 = value; + } + break; + case M32C_OPERAND_DSP_40_U20 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 20, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040)))); + fields->f_dsp_40_u20 = value; + } + break; + case M32C_OPERAND_DSP_40_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 24, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_40_u24 = value; + } + break; + case M32C_OPERAND_DSP_40_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 8, 32, total_length, pc, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_DSP_48_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_48_s16 = value; + } + break; + case M32C_OPERAND_DSP_48_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_48_s8); + break; + case M32C_OPERAND_DSP_48_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + break; + case M32C_OPERAND_DSP_48_U20 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_48_u20) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u8)) << (16))) & (983040)))); +} + } + break; + case M32C_OPERAND_DSP_48_U24 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_48_u24) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u8)) << (16))) & (16711680)))); +} + } + break; + case M32C_OPERAND_DSP_48_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 8, 32, total_length, pc, & fields->f_dsp_48_u8); + break; + case M32C_OPERAND_DSP_8_S24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (16))) & (255))) | (((value) & (65280))))) | (((EXTQISI (TRUNCSIQI (((value) & (255))))) << (16)))); + fields->f_dsp_8_s24 = value; + } + break; + case M32C_OPERAND_DSP_8_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_8_s8); + break; + case M32C_OPERAND_DSP_8_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_8_u16 = value; + } + break; + case M32C_OPERAND_DSP_8_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 24, 32, total_length, pc, & value); + value = ((((((USI) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + fields->f_dsp_8_u24 = value; + } + break; + case M32C_OPERAND_DSP_8_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_dsp_8_u6); + break; + case M32C_OPERAND_DSP_8_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_u8); + break; + case M32C_OPERAND_DST16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16AN_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_dst16_an_s); + break; + case M32C_OPERAND_DST16ANHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16ANSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16RNEXTQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_dst16_rn_ext); + break; + case M32C_OPERAND_DST16RNHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16RNSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_dst32_rn_prefixed_HI = value; + } + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_dst32_rn_prefixed_SI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_dst32_rn_unprefixed_HI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_dst32_rn_unprefixed_SI = value; + } + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_12_s4); + break; + case M32C_OPERAND_IMM_12_S4N : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_12_s4); + break; + case M32C_OPERAND_IMM_13_U3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_imm_13_u3); + break; + case M32C_OPERAND_IMM_16_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + break; + case M32C_OPERAND_IMM_16_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_IMM_16_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_16_s32) = ((((FLD (f_dsp_16_u16)) & (65535))) | (((((FLD (f_dsp_32_u16)) << (16))) & (0xffff0000)))); +} + } + break; + case M32C_OPERAND_IMM_20_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_20_s4); + break; + case M32C_OPERAND_IMM_24_HI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8)))))); +} + } + break; + case M32C_OPERAND_IMM_24_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + break; + case M32C_OPERAND_IMM_24_SI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_s32) = ((((FLD (f_dsp_24_u8)) & (255))) | (((((FLD (f_dsp_32_u24)) << (8))) & (0xffffff00)))); +} + } + break; + case M32C_OPERAND_IMM_32_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_32_s16 = value; + } + break; + case M32C_OPERAND_IMM_32_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + break; + case M32C_OPERAND_IMM_32_SI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (24))) & (255))) | (((((UINT) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + fields->f_dsp_32_s32 = value; + } + break; + case M32C_OPERAND_IMM_40_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_40_s16 = value; + } + break; + case M32C_OPERAND_IMM_40_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_40_s8); + break; + case M32C_OPERAND_IMM_40_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 24, 32, total_length, pc, & value); + value = ((((((((USI) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_40_u24 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_40_s32) = ((((FLD (f_dsp_40_u24)) & (16777215))) | (((((FLD (f_dsp_64_u8)) << (24))) & (0xff000000)))); +} + } + break; + case M32C_OPERAND_IMM_48_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_48_s16 = value; + } + break; + case M32C_OPERAND_IMM_48_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_48_s8); + break; + case M32C_OPERAND_IMM_48_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 16, 32, total_length, pc, & value); + value = ((((((UHI) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_64_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) << (16))) & (0xffff0000)))); +} + } + break; + case M32C_OPERAND_IMM_56_HI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 32, 24, 8, 32, total_length, pc, & fields->f_dsp_56_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_56_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_64_u8)) << (8))) | (FLD (f_dsp_56_u8)))))); +} + } + break; + case M32C_OPERAND_IMM_56_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_56_s8); + break; + case M32C_OPERAND_IMM_64_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_64_s16 = value; + } + break; + case M32C_OPERAND_IMM_8_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_8_s16 = value; + } + break; + case M32C_OPERAND_IMM_8_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_8_s8); + break; + case M32C_OPERAND_IMM_8_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_8_s4); + break; + case M32C_OPERAND_IMM_8_S4N : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_8_s4); + break; + case M32C_OPERAND_IMM_SH_12_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_12_s4); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_20_s4); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_8_s4); + break; + case M32C_OPERAND_IMM1_S : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 1, 32, total_length, pc, & value); + value = ((value) + (1)); + fields->f_imm1_S = value; + } + break; + case M32C_OPERAND_IMM3_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_imm3_S) = ((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (1)); +} + } + break; + case M32C_OPERAND_LAB_16_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_16_8 = value; + } + break; + case M32C_OPERAND_LAB_24_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_24_8 = value; + } + break; + case M32C_OPERAND_LAB_32_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_32_8 = value; + } + break; + case M32C_OPERAND_LAB_40_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_40_8 = value; + } + break; + case M32C_OPERAND_LAB_5_3 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_5_3 = value; + } + break; + case M32C_OPERAND_LAB_8_16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) | (((SI) (((((value) & (255))) << (24))) >> (16))))) + (((pc) + (1)))); + fields->f_lab_8_16 = value; + } + break; + case M32C_OPERAND_LAB_8_24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + fields->f_lab_8_24 = value; + } + break; + case M32C_OPERAND_LAB_8_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_8_8 = value; + } + break; + case M32C_OPERAND_LAB32_JMP_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_lab32_jmp_s) = ((pc) + (((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (2)))); +} + } + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_8_8); + break; + case M32C_OPERAND_REGSETPUSH : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_8_8); + break; + case M32C_OPERAND_RN16_PUSH_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16RNHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC16RNQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_src32_rn_prefixed_HI = value; + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_src32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_src32_rn_prefixed_SI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_src32_rn_unprefixed_HI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = (((((~ (((USI) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_src32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_src32_rn_unprefixed_SI = value; + } + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5_1); + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND16_24 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND16_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND16C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cond16j_5); + break; + case M32C_OPERAND_COND32 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_9_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + if (length <= 0) break; +{ + FLD (f_cond32) = ((((FLD (f_9_1)) << (3))) | (FLD (f_13_3))); +} + } + break; + case M32C_OPERAND_COND32_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND32_24 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND32_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND32_40 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 8, 32, total_length, pc, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_COND32J : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 3, 32, total_length, pc, & fields->f_1_3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_cond32j) = ((((FLD (f_1_3)) << (1))) | (FLD (f_7_1))); +} + } + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_21_3); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_CR16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_9_3); + break; + case M32C_OPERAND_CR2_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_21_3); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_FLAGS16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_9_3); + break; + case M32C_OPERAND_FLAGS32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_SCCOND32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const m32c_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const m32c_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int m32c_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma m32c_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case M32C_OPERAND_A0 : + value = 0; + break; + case M32C_OPERAND_A1 : + value = 0; + break; + case M32C_OPERAND_AN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_BIT16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_BIT16RN : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_BIT3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + value = fields->f_bitbase16_u11_S; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + value = fields->f_bitbase32_16_s11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + value = fields->f_bitbase32_16_s19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + value = fields->f_bitbase32_16_u11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + value = fields->f_bitbase32_16_u19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + value = fields->f_bitbase32_16_u27_unprefixed; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + value = fields->f_bitbase32_24_s11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + value = fields->f_bitbase32_24_s19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + value = fields->f_bitbase32_24_u11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + value = fields->f_bitbase32_24_u19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + value = fields->f_bitbase32_24_u27_prefixed; + break; + case M32C_OPERAND_BITNO16R : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITNO32PREFIXED : + value = fields->f_bitno32_prefixed; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + value = fields->f_bitno32_unprefixed; + break; + case M32C_OPERAND_DSP_10_U6 : + value = fields->f_dsp_10_u6; + break; + case M32C_OPERAND_DSP_16_S16 : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_DSP_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_DSP_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_DSP_16_U20 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U24 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_DSP_24_S16 : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_DSP_24_S8 : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_DSP_24_U16 : + value = fields->f_dsp_24_u16; + break; + case M32C_OPERAND_DSP_24_U20 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U24 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U8 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_DSP_32_S16 : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_DSP_32_S8 : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_DSP_32_U16 : + value = fields->f_dsp_32_u16; + break; + case M32C_OPERAND_DSP_32_U20 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U24 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U8 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_DSP_40_S16 : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_DSP_40_S8 : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_DSP_40_U16 : + value = fields->f_dsp_40_u16; + break; + case M32C_OPERAND_DSP_40_U20 : + value = fields->f_dsp_40_u20; + break; + case M32C_OPERAND_DSP_40_U24 : + value = fields->f_dsp_40_u24; + break; + case M32C_OPERAND_DSP_40_U8 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_DSP_48_S16 : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_DSP_48_S8 : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_DSP_48_U16 : + value = fields->f_dsp_48_u16; + break; + case M32C_OPERAND_DSP_48_U20 : + value = fields->f_dsp_48_u20; + break; + case M32C_OPERAND_DSP_48_U24 : + value = fields->f_dsp_48_u24; + break; + case M32C_OPERAND_DSP_48_U8 : + value = fields->f_dsp_48_u8; + break; + case M32C_OPERAND_DSP_8_S24 : + value = fields->f_dsp_8_s24; + break; + case M32C_OPERAND_DSP_8_S8 : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_DSP_8_U16 : + value = fields->f_dsp_8_u16; + break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; + case M32C_OPERAND_DSP_8_U6 : + value = fields->f_dsp_8_u6; + break; + case M32C_OPERAND_DSP_8_U8 : + value = fields->f_dsp_8_u8; + break; + case M32C_OPERAND_DST16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16AN_S : + value = fields->f_dst16_an_s; + break; + case M32C_OPERAND_DST16ANHI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16ANSI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16RNEXTQI : + value = fields->f_dst16_rn_ext; + break; + case M32C_OPERAND_DST16RNHI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16RNSI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32R0HI_S : + value = 0; + break; + case M32C_OPERAND_DST32R0QI_S : + value = 0; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + value = fields->f_dst32_rn_prefixed_HI; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + value = fields->f_dst32_rn_prefixed_SI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + value = fields->f_dst32_rn_unprefixed_HI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + value = fields->f_dst32_rn_unprefixed_SI; + break; + case M32C_OPERAND_G : + value = 0; + break; + case M32C_OPERAND_IMM_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_12_S4N : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_13_U3 : + value = fields->f_imm_13_u3; + break; + case M32C_OPERAND_IMM_16_HI : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_IMM_16_QI : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_IMM_16_SI : + value = fields->f_dsp_16_s32; + break; + case M32C_OPERAND_IMM_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_24_HI : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_IMM_24_QI : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_IMM_24_SI : + value = fields->f_dsp_24_s32; + break; + case M32C_OPERAND_IMM_32_HI : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_IMM_32_QI : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_IMM_32_SI : + value = fields->f_dsp_32_s32; + break; + case M32C_OPERAND_IMM_40_HI : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_IMM_40_QI : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_IMM_40_SI : + value = fields->f_dsp_40_s32; + break; + case M32C_OPERAND_IMM_48_HI : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_IMM_48_QI : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_IMM_48_SI : + value = fields->f_dsp_48_s32; + break; + case M32C_OPERAND_IMM_56_HI : + value = fields->f_dsp_56_s16; + break; + case M32C_OPERAND_IMM_56_QI : + value = fields->f_dsp_56_s8; + break; + case M32C_OPERAND_IMM_64_HI : + value = fields->f_dsp_64_s16; + break; + case M32C_OPERAND_IMM_8_HI : + value = fields->f_dsp_8_s16; + break; + case M32C_OPERAND_IMM_8_QI : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_IMM_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_8_S4N : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM1_S : + value = fields->f_imm1_S; + break; + case M32C_OPERAND_IMM3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_LAB_16_8 : + value = fields->f_lab_16_8; + break; + case M32C_OPERAND_LAB_24_8 : + value = fields->f_lab_24_8; + break; + case M32C_OPERAND_LAB_32_8 : + value = fields->f_lab_32_8; + break; + case M32C_OPERAND_LAB_40_8 : + value = fields->f_lab_40_8; + break; + case M32C_OPERAND_LAB_5_3 : + value = fields->f_lab_5_3; + break; + case M32C_OPERAND_LAB_8_16 : + value = fields->f_lab_8_16; + break; + case M32C_OPERAND_LAB_8_24 : + value = fields->f_lab_8_24; + break; + case M32C_OPERAND_LAB_8_8 : + value = fields->f_lab_8_8; + break; + case M32C_OPERAND_LAB32_JMP_S : + value = fields->f_lab32_jmp_s; + break; + case M32C_OPERAND_Q : + value = 0; + break; + case M32C_OPERAND_R0 : + value = 0; + break; + case M32C_OPERAND_R0H : + value = 0; + break; + case M32C_OPERAND_R0L : + value = 0; + break; + case M32C_OPERAND_R1 : + value = 0; + break; + case M32C_OPERAND_R1R2R0 : + value = 0; + break; + case M32C_OPERAND_R2 : + value = 0; + break; + case M32C_OPERAND_R2R0 : + value = 0; + break; + case M32C_OPERAND_R3 : + value = 0; + break; + case M32C_OPERAND_R3R1 : + value = 0; + break; + case M32C_OPERAND_REGSETPOP : + value = fields->f_8_8; + break; + case M32C_OPERAND_REGSETPUSH : + value = fields->f_8_8; + break; + case M32C_OPERAND_RN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_S : + value = 0; + break; + case M32C_OPERAND_SRC16AN : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANHI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANQI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16RNHI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC16RNQI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + value = fields->f_src32_rn_prefixed_HI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + value = fields->f_src32_rn_prefixed_QI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + value = fields->f_src32_rn_prefixed_SI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + value = fields->f_src32_rn_unprefixed_HI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + value = fields->f_src32_rn_unprefixed_QI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + value = fields->f_src32_rn_unprefixed_SI; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + value = fields->f_5_1; + break; + case M32C_OPERAND_X : + value = 0; + break; + case M32C_OPERAND_Z : + value = 0; + break; + case M32C_OPERAND_COND16_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND16_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND16_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND16C : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J5 : + value = fields->f_cond16j_5; + break; + case M32C_OPERAND_COND32 : + value = fields->f_cond32; + break; + case M32C_OPERAND_COND32_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND32_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND32_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND32_40 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_COND32J : + value = fields->f_cond32j; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_CR2_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_FLAGS16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_FLAGS32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_SCCOND32 : + value = fields->f_cond16; + break; + case M32C_OPERAND_SIZE : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case M32C_OPERAND_A0 : + value = 0; + break; + case M32C_OPERAND_A1 : + value = 0; + break; + case M32C_OPERAND_AN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_BIT16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_BIT16RN : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_BIT3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + value = fields->f_bitbase16_u11_S; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + value = fields->f_bitbase32_16_s11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + value = fields->f_bitbase32_16_s19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + value = fields->f_bitbase32_16_u11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + value = fields->f_bitbase32_16_u19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + value = fields->f_bitbase32_16_u27_unprefixed; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + value = fields->f_bitbase32_24_s11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + value = fields->f_bitbase32_24_s19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + value = fields->f_bitbase32_24_u11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + value = fields->f_bitbase32_24_u19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + value = fields->f_bitbase32_24_u27_prefixed; + break; + case M32C_OPERAND_BITNO16R : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITNO32PREFIXED : + value = fields->f_bitno32_prefixed; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + value = fields->f_bitno32_unprefixed; + break; + case M32C_OPERAND_DSP_10_U6 : + value = fields->f_dsp_10_u6; + break; + case M32C_OPERAND_DSP_16_S16 : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_DSP_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_DSP_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_DSP_16_U20 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U24 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_DSP_24_S16 : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_DSP_24_S8 : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_DSP_24_U16 : + value = fields->f_dsp_24_u16; + break; + case M32C_OPERAND_DSP_24_U20 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U24 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U8 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_DSP_32_S16 : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_DSP_32_S8 : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_DSP_32_U16 : + value = fields->f_dsp_32_u16; + break; + case M32C_OPERAND_DSP_32_U20 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U24 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U8 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_DSP_40_S16 : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_DSP_40_S8 : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_DSP_40_U16 : + value = fields->f_dsp_40_u16; + break; + case M32C_OPERAND_DSP_40_U20 : + value = fields->f_dsp_40_u20; + break; + case M32C_OPERAND_DSP_40_U24 : + value = fields->f_dsp_40_u24; + break; + case M32C_OPERAND_DSP_40_U8 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_DSP_48_S16 : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_DSP_48_S8 : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_DSP_48_U16 : + value = fields->f_dsp_48_u16; + break; + case M32C_OPERAND_DSP_48_U20 : + value = fields->f_dsp_48_u20; + break; + case M32C_OPERAND_DSP_48_U24 : + value = fields->f_dsp_48_u24; + break; + case M32C_OPERAND_DSP_48_U8 : + value = fields->f_dsp_48_u8; + break; + case M32C_OPERAND_DSP_8_S24 : + value = fields->f_dsp_8_s24; + break; + case M32C_OPERAND_DSP_8_S8 : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_DSP_8_U16 : + value = fields->f_dsp_8_u16; + break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; + case M32C_OPERAND_DSP_8_U6 : + value = fields->f_dsp_8_u6; + break; + case M32C_OPERAND_DSP_8_U8 : + value = fields->f_dsp_8_u8; + break; + case M32C_OPERAND_DST16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16AN_S : + value = fields->f_dst16_an_s; + break; + case M32C_OPERAND_DST16ANHI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16ANSI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16RNEXTQI : + value = fields->f_dst16_rn_ext; + break; + case M32C_OPERAND_DST16RNHI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16RNSI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32R0HI_S : + value = 0; + break; + case M32C_OPERAND_DST32R0QI_S : + value = 0; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + value = fields->f_dst32_rn_prefixed_HI; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + value = fields->f_dst32_rn_prefixed_SI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + value = fields->f_dst32_rn_unprefixed_HI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + value = fields->f_dst32_rn_unprefixed_SI; + break; + case M32C_OPERAND_G : + value = 0; + break; + case M32C_OPERAND_IMM_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_12_S4N : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_13_U3 : + value = fields->f_imm_13_u3; + break; + case M32C_OPERAND_IMM_16_HI : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_IMM_16_QI : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_IMM_16_SI : + value = fields->f_dsp_16_s32; + break; + case M32C_OPERAND_IMM_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_24_HI : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_IMM_24_QI : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_IMM_24_SI : + value = fields->f_dsp_24_s32; + break; + case M32C_OPERAND_IMM_32_HI : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_IMM_32_QI : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_IMM_32_SI : + value = fields->f_dsp_32_s32; + break; + case M32C_OPERAND_IMM_40_HI : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_IMM_40_QI : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_IMM_40_SI : + value = fields->f_dsp_40_s32; + break; + case M32C_OPERAND_IMM_48_HI : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_IMM_48_QI : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_IMM_48_SI : + value = fields->f_dsp_48_s32; + break; + case M32C_OPERAND_IMM_56_HI : + value = fields->f_dsp_56_s16; + break; + case M32C_OPERAND_IMM_56_QI : + value = fields->f_dsp_56_s8; + break; + case M32C_OPERAND_IMM_64_HI : + value = fields->f_dsp_64_s16; + break; + case M32C_OPERAND_IMM_8_HI : + value = fields->f_dsp_8_s16; + break; + case M32C_OPERAND_IMM_8_QI : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_IMM_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_8_S4N : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM1_S : + value = fields->f_imm1_S; + break; + case M32C_OPERAND_IMM3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_LAB_16_8 : + value = fields->f_lab_16_8; + break; + case M32C_OPERAND_LAB_24_8 : + value = fields->f_lab_24_8; + break; + case M32C_OPERAND_LAB_32_8 : + value = fields->f_lab_32_8; + break; + case M32C_OPERAND_LAB_40_8 : + value = fields->f_lab_40_8; + break; + case M32C_OPERAND_LAB_5_3 : + value = fields->f_lab_5_3; + break; + case M32C_OPERAND_LAB_8_16 : + value = fields->f_lab_8_16; + break; + case M32C_OPERAND_LAB_8_24 : + value = fields->f_lab_8_24; + break; + case M32C_OPERAND_LAB_8_8 : + value = fields->f_lab_8_8; + break; + case M32C_OPERAND_LAB32_JMP_S : + value = fields->f_lab32_jmp_s; + break; + case M32C_OPERAND_Q : + value = 0; + break; + case M32C_OPERAND_R0 : + value = 0; + break; + case M32C_OPERAND_R0H : + value = 0; + break; + case M32C_OPERAND_R0L : + value = 0; + break; + case M32C_OPERAND_R1 : + value = 0; + break; + case M32C_OPERAND_R1R2R0 : + value = 0; + break; + case M32C_OPERAND_R2 : + value = 0; + break; + case M32C_OPERAND_R2R0 : + value = 0; + break; + case M32C_OPERAND_R3 : + value = 0; + break; + case M32C_OPERAND_R3R1 : + value = 0; + break; + case M32C_OPERAND_REGSETPOP : + value = fields->f_8_8; + break; + case M32C_OPERAND_REGSETPUSH : + value = fields->f_8_8; + break; + case M32C_OPERAND_RN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_S : + value = 0; + break; + case M32C_OPERAND_SRC16AN : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANHI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANQI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16RNHI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC16RNQI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + value = fields->f_src32_rn_prefixed_HI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + value = fields->f_src32_rn_prefixed_QI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + value = fields->f_src32_rn_prefixed_SI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + value = fields->f_src32_rn_unprefixed_HI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + value = fields->f_src32_rn_unprefixed_QI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + value = fields->f_src32_rn_unprefixed_SI; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + value = fields->f_5_1; + break; + case M32C_OPERAND_X : + value = 0; + break; + case M32C_OPERAND_Z : + value = 0; + break; + case M32C_OPERAND_COND16_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND16_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND16_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND16C : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J5 : + value = fields->f_cond16j_5; + break; + case M32C_OPERAND_COND32 : + value = fields->f_cond32; + break; + case M32C_OPERAND_COND32_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND32_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND32_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND32_40 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_COND32J : + value = fields->f_cond32j; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_CR2_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_FLAGS16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_FLAGS32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_SCCOND32 : + value = fields->f_cond16; + break; + case M32C_OPERAND_SIZE : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void m32c_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void m32c_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_BIT16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_BIT16RN : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_BIT3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + fields->f_bitbase16_u11_S = value; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + fields->f_bitbase32_16_s11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + fields->f_bitbase32_16_s19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + fields->f_bitbase32_16_u11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + fields->f_bitbase32_16_u19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + fields->f_bitbase32_16_u27_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + fields->f_bitbase32_24_s11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + fields->f_bitbase32_24_s19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + fields->f_bitbase32_24_u11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + fields->f_bitbase32_24_u19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + fields->f_bitbase32_24_u27_prefixed = value; + break; + case M32C_OPERAND_BITNO16R : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITNO32PREFIXED : + fields->f_bitno32_prefixed = value; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + fields->f_bitno32_unprefixed = value; + break; + case M32C_OPERAND_DSP_10_U6 : + fields->f_dsp_10_u6 = value; + break; + case M32C_OPERAND_DSP_16_S16 : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_DSP_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_DSP_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_DSP_16_U20 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U24 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_DSP_24_S16 : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_DSP_24_S8 : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_DSP_24_U16 : + fields->f_dsp_24_u16 = value; + break; + case M32C_OPERAND_DSP_24_U20 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U24 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U8 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_DSP_32_S16 : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_DSP_32_S8 : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_DSP_32_U16 : + fields->f_dsp_32_u16 = value; + break; + case M32C_OPERAND_DSP_32_U20 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U24 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U8 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_DSP_40_S16 : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_DSP_40_S8 : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_DSP_40_U16 : + fields->f_dsp_40_u16 = value; + break; + case M32C_OPERAND_DSP_40_U20 : + fields->f_dsp_40_u20 = value; + break; + case M32C_OPERAND_DSP_40_U24 : + fields->f_dsp_40_u24 = value; + break; + case M32C_OPERAND_DSP_40_U8 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_DSP_48_S16 : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_DSP_48_S8 : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_DSP_48_U16 : + fields->f_dsp_48_u16 = value; + break; + case M32C_OPERAND_DSP_48_U20 : + fields->f_dsp_48_u20 = value; + break; + case M32C_OPERAND_DSP_48_U24 : + fields->f_dsp_48_u24 = value; + break; + case M32C_OPERAND_DSP_48_U8 : + fields->f_dsp_48_u8 = value; + break; + case M32C_OPERAND_DSP_8_S24 : + fields->f_dsp_8_s24 = value; + break; + case M32C_OPERAND_DSP_8_S8 : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_DSP_8_U16 : + fields->f_dsp_8_u16 = value; + break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; + case M32C_OPERAND_DSP_8_U6 : + fields->f_dsp_8_u6 = value; + break; + case M32C_OPERAND_DSP_8_U8 : + fields->f_dsp_8_u8 = value; + break; + case M32C_OPERAND_DST16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16AN_S : + fields->f_dst16_an_s = value; + break; + case M32C_OPERAND_DST16ANHI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16ANSI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16RNEXTQI : + fields->f_dst16_rn_ext = value; + break; + case M32C_OPERAND_DST16RNHI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16RNSI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + fields->f_dst32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + fields->f_dst32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + fields->f_dst32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + fields->f_dst32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_12_S4N : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_13_U3 : + fields->f_imm_13_u3 = value; + break; + case M32C_OPERAND_IMM_16_HI : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_IMM_16_QI : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_IMM_16_SI : + fields->f_dsp_16_s32 = value; + break; + case M32C_OPERAND_IMM_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_24_HI : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_IMM_24_QI : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_IMM_24_SI : + fields->f_dsp_24_s32 = value; + break; + case M32C_OPERAND_IMM_32_HI : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_IMM_32_QI : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_IMM_32_SI : + fields->f_dsp_32_s32 = value; + break; + case M32C_OPERAND_IMM_40_HI : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_IMM_40_QI : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_IMM_40_SI : + fields->f_dsp_40_s32 = value; + break; + case M32C_OPERAND_IMM_48_HI : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_IMM_48_QI : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_IMM_48_SI : + fields->f_dsp_48_s32 = value; + break; + case M32C_OPERAND_IMM_56_HI : + fields->f_dsp_56_s16 = value; + break; + case M32C_OPERAND_IMM_56_QI : + fields->f_dsp_56_s8 = value; + break; + case M32C_OPERAND_IMM_64_HI : + fields->f_dsp_64_s16 = value; + break; + case M32C_OPERAND_IMM_8_HI : + fields->f_dsp_8_s16 = value; + break; + case M32C_OPERAND_IMM_8_QI : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_IMM_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_8_S4N : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM1_S : + fields->f_imm1_S = value; + break; + case M32C_OPERAND_IMM3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_LAB_16_8 : + fields->f_lab_16_8 = value; + break; + case M32C_OPERAND_LAB_24_8 : + fields->f_lab_24_8 = value; + break; + case M32C_OPERAND_LAB_32_8 : + fields->f_lab_32_8 = value; + break; + case M32C_OPERAND_LAB_40_8 : + fields->f_lab_40_8 = value; + break; + case M32C_OPERAND_LAB_5_3 : + fields->f_lab_5_3 = value; + break; + case M32C_OPERAND_LAB_8_16 : + fields->f_lab_8_16 = value; + break; + case M32C_OPERAND_LAB_8_24 : + fields->f_lab_8_24 = value; + break; + case M32C_OPERAND_LAB_8_8 : + fields->f_lab_8_8 = value; + break; + case M32C_OPERAND_LAB32_JMP_S : + fields->f_lab32_jmp_s = value; + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + fields->f_8_8 = value; + break; + case M32C_OPERAND_REGSETPUSH : + fields->f_8_8 = value; + break; + case M32C_OPERAND_RN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANHI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANQI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16RNHI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC16RNQI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + fields->f_src32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + fields->f_src32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + fields->f_src32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + fields->f_src32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + fields->f_src32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + fields->f_src32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + fields->f_5_1 = value; + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND16_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND16_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND16C : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J5 : + fields->f_cond16j_5 = value; + break; + case M32C_OPERAND_COND32 : + fields->f_cond32 = value; + break; + case M32C_OPERAND_COND32_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND32_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND32_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND32_40 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_COND32J : + fields->f_cond32j = value; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_CR2_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_FLAGS16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_FLAGS32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_SCCOND32 : + fields->f_cond16 = value; + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_BIT16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_BIT16RN : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_BIT3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + fields->f_bitbase16_u11_S = value; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + fields->f_bitbase32_16_s11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + fields->f_bitbase32_16_s19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + fields->f_bitbase32_16_u11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + fields->f_bitbase32_16_u19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + fields->f_bitbase32_16_u27_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + fields->f_bitbase32_24_s11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + fields->f_bitbase32_24_s19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + fields->f_bitbase32_24_u11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + fields->f_bitbase32_24_u19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + fields->f_bitbase32_24_u27_prefixed = value; + break; + case M32C_OPERAND_BITNO16R : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITNO32PREFIXED : + fields->f_bitno32_prefixed = value; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + fields->f_bitno32_unprefixed = value; + break; + case M32C_OPERAND_DSP_10_U6 : + fields->f_dsp_10_u6 = value; + break; + case M32C_OPERAND_DSP_16_S16 : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_DSP_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_DSP_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_DSP_16_U20 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U24 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_DSP_24_S16 : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_DSP_24_S8 : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_DSP_24_U16 : + fields->f_dsp_24_u16 = value; + break; + case M32C_OPERAND_DSP_24_U20 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U24 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U8 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_DSP_32_S16 : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_DSP_32_S8 : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_DSP_32_U16 : + fields->f_dsp_32_u16 = value; + break; + case M32C_OPERAND_DSP_32_U20 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U24 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U8 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_DSP_40_S16 : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_DSP_40_S8 : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_DSP_40_U16 : + fields->f_dsp_40_u16 = value; + break; + case M32C_OPERAND_DSP_40_U20 : + fields->f_dsp_40_u20 = value; + break; + case M32C_OPERAND_DSP_40_U24 : + fields->f_dsp_40_u24 = value; + break; + case M32C_OPERAND_DSP_40_U8 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_DSP_48_S16 : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_DSP_48_S8 : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_DSP_48_U16 : + fields->f_dsp_48_u16 = value; + break; + case M32C_OPERAND_DSP_48_U20 : + fields->f_dsp_48_u20 = value; + break; + case M32C_OPERAND_DSP_48_U24 : + fields->f_dsp_48_u24 = value; + break; + case M32C_OPERAND_DSP_48_U8 : + fields->f_dsp_48_u8 = value; + break; + case M32C_OPERAND_DSP_8_S24 : + fields->f_dsp_8_s24 = value; + break; + case M32C_OPERAND_DSP_8_S8 : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_DSP_8_U16 : + fields->f_dsp_8_u16 = value; + break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; + case M32C_OPERAND_DSP_8_U6 : + fields->f_dsp_8_u6 = value; + break; + case M32C_OPERAND_DSP_8_U8 : + fields->f_dsp_8_u8 = value; + break; + case M32C_OPERAND_DST16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16AN_S : + fields->f_dst16_an_s = value; + break; + case M32C_OPERAND_DST16ANHI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16ANSI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16RNEXTQI : + fields->f_dst16_rn_ext = value; + break; + case M32C_OPERAND_DST16RNHI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16RNSI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + fields->f_dst32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + fields->f_dst32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + fields->f_dst32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + fields->f_dst32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_12_S4N : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_13_U3 : + fields->f_imm_13_u3 = value; + break; + case M32C_OPERAND_IMM_16_HI : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_IMM_16_QI : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_IMM_16_SI : + fields->f_dsp_16_s32 = value; + break; + case M32C_OPERAND_IMM_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_24_HI : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_IMM_24_QI : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_IMM_24_SI : + fields->f_dsp_24_s32 = value; + break; + case M32C_OPERAND_IMM_32_HI : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_IMM_32_QI : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_IMM_32_SI : + fields->f_dsp_32_s32 = value; + break; + case M32C_OPERAND_IMM_40_HI : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_IMM_40_QI : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_IMM_40_SI : + fields->f_dsp_40_s32 = value; + break; + case M32C_OPERAND_IMM_48_HI : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_IMM_48_QI : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_IMM_48_SI : + fields->f_dsp_48_s32 = value; + break; + case M32C_OPERAND_IMM_56_HI : + fields->f_dsp_56_s16 = value; + break; + case M32C_OPERAND_IMM_56_QI : + fields->f_dsp_56_s8 = value; + break; + case M32C_OPERAND_IMM_64_HI : + fields->f_dsp_64_s16 = value; + break; + case M32C_OPERAND_IMM_8_HI : + fields->f_dsp_8_s16 = value; + break; + case M32C_OPERAND_IMM_8_QI : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_IMM_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_8_S4N : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM1_S : + fields->f_imm1_S = value; + break; + case M32C_OPERAND_IMM3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_LAB_16_8 : + fields->f_lab_16_8 = value; + break; + case M32C_OPERAND_LAB_24_8 : + fields->f_lab_24_8 = value; + break; + case M32C_OPERAND_LAB_32_8 : + fields->f_lab_32_8 = value; + break; + case M32C_OPERAND_LAB_40_8 : + fields->f_lab_40_8 = value; + break; + case M32C_OPERAND_LAB_5_3 : + fields->f_lab_5_3 = value; + break; + case M32C_OPERAND_LAB_8_16 : + fields->f_lab_8_16 = value; + break; + case M32C_OPERAND_LAB_8_24 : + fields->f_lab_8_24 = value; + break; + case M32C_OPERAND_LAB_8_8 : + fields->f_lab_8_8 = value; + break; + case M32C_OPERAND_LAB32_JMP_S : + fields->f_lab32_jmp_s = value; + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + fields->f_8_8 = value; + break; + case M32C_OPERAND_REGSETPUSH : + fields->f_8_8 = value; + break; + case M32C_OPERAND_RN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANHI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANQI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16RNHI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC16RNQI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + fields->f_src32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + fields->f_src32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + fields->f_src32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + fields->f_src32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + fields->f_src32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + fields->f_src32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + fields->f_5_1 = value; + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND16_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND16_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND16C : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J5 : + fields->f_cond16j_5 = value; + break; + case M32C_OPERAND_COND32 : + fields->f_cond32 = value; + break; + case M32C_OPERAND_COND32_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND32_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND32_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND32_40 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_COND32J : + fields->f_cond32j = value; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_CR2_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_FLAGS16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_FLAGS32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_SCCOND32 : + fields->f_cond16 = value; + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +m32c_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & m32c_cgen_insert_handlers[0]; + cd->extract_handlers = & m32c_cgen_extract_handlers[0]; + + cd->insert_operand = m32c_cgen_insert_operand; + cd->extract_operand = m32c_cgen_extract_operand; + + cd->get_int_operand = m32c_cgen_get_int_operand; + cd->set_int_operand = m32c_cgen_set_int_operand; + cd->get_vma_operand = m32c_cgen_get_vma_operand; + cd->set_vma_operand = m32c_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32c-opc.c b/external/gpl3/gdb/dist/opcodes/m32c-opc.c new file mode 100644 index 000000000000..2f5ed073d811 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-opc.c @@ -0,0 +1,80224 @@ +/* Instruction opcode table for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +static unsigned int +m32c_asm_hash (const char *mnem) +{ + unsigned int h; + + /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */ + if (mnem[0] == 'j' && mnem[1] != 's') + return 'j'; + + /* Don't hash scCND */ + if (mnem[0] == 's' && mnem[1] == 'c') + return 's'; + + /* Don't hash bmCND */ + if (mnem[0] == 'b' && mnem[1] == 'm') + return 'b'; + + for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem) + h += *mnem; + return h % CGEN_ASM_HASH_SIZE; +} + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & m32c_cgen_ifld_table[M32C_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffd, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN_EXT) }, { F (F_15_1) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16b_r1h_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff000000, { { F (F_0_2) }, { F (F_DSP_24_S16) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_S8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U16) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push16_b_s_an_An16_push_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xfb, { { F (F_0_4) }, { F (F_6_2) }, { F (F_5_1) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 80, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 80, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_Rn_direct ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_direct ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_indirect ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_absolute ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S ATTRIBUTE_UNUSED = { + 16, 16, 0xf800, { { F (F_0_2) }, { F (F_BITBASE16_U11_S) }, { F (F_2_2) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xff3800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_wQ_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_b_G_sp ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_w_G_sp ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm3_Q ATTRIBUTE_UNUSED = { + 8, 8, 0xce, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm8_S ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm16_G ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dadc16_b_r0h_r0l ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_c ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_c ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_COND32) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btst_s ATTRIBUTE_UNUSED = { + 24, 24, 0xce0000, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { F (F_DSP_8_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div32_b_Imm_16_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div32_w_Imm_16_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter16 ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter32 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fclr16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fclr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int16 ATTRIBUTE_UNUSED = { + 16, 16, 0xffc0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_2) }, { F (F_DSP_10_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int32 ATTRIBUTE_UNUSED = { + 16, 16, 0xff03, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U6) }, { F (F_14_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd16_5 ATTRIBUTE_UNUSED = { + 16, 16, 0xf800, { { F (F_0_4) }, { F (F_4_1) }, { F (F_COND16J_5) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd16 ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd32 ATTRIBUTE_UNUSED = { + 16, 16, 0x8e00, { { F (F_0_1) }, { F (F_COND32J) }, { F (F_4_3) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_s ATTRIBUTE_UNUSED = { + 8, 8, 0xf8, { { F (F_0_4) }, { F (F_4_1) }, { F (F_LAB_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_b ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_w ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_a ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmps16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp32_s ATTRIBUTE_UNUSED = { + 8, 8, 0xce, { { F (F_0_2) }, { F (F_LAB32_JMP_S) }, { F (F_4_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc16_imm16 ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr2 ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr3 ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldctx16 ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldipl16_imm ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_IMM_13_U3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc32_imm16_cr1 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc32_imm16_cr2 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pushm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push32_l_imm ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sha16_L_imm_r2r0 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_r0h ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8fb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = { + 32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) M32C_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980b00 } + }, +/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982b00 } + }, +/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908b00 } + }, +/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190ab00 } + }, +/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900b00 } + }, +/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902b00 } + }, +/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80b00 } + }, +/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82b00 } + }, +/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83b00 } + }, +/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08b00 } + }, +/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0ab00 } + }, +/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0bb00 } + }, +/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00b00 } + }, +/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02b00 } + }, +/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03b00 } + }, +/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6bb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80b00 } + }, +/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08b00 } + }, +/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00b00 } + }, +/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6ab00 } + }, +/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c80b } + }, +/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1880b } + }, +/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c08b } + }, +/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1808b } + }, +/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c00b } + }, +/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1800b } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868b00 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980700 } + }, +/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982700 } + }, +/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908700 } + }, +/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900700 } + }, +/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902700 } + }, +/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80700 } + }, +/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82700 } + }, +/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83700 } + }, +/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08700 } + }, +/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0b700 } + }, +/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00700 } + }, +/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02700 } + }, +/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03700 } + }, +/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6b700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80700 } + }, +/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08700 } + }, +/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00700 } + }, +/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6a700 } + }, +/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c807 } + }, +/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x18807 } + }, +/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c087 } + }, +/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x18087 } + }, +/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c007 } + }, +/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x18007 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868700 } + }, +/* exts.w $Dst32RnExtUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDHI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI, { 0xc99e } + }, +/* exts.w $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc19e } + }, +/* exts.w [$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI, { 0xc11e } + }, +/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI, { 0xc31e00 } + }, +/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI, { 0xc51e0000 } + }, +/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI, { 0xc71e0000 } + }, +/* exts.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI, { 0xc39e00 } + }, +/* exts.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI, { 0xc59e0000 } + }, +/* exts.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI, { 0xc3de00 } + }, +/* exts.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI, { 0xc5de0000 } + }, +/* exts.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI, { 0xc7de0000 } + }, +/* exts.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI, { 0xc79e0000 } + }, +/* exts.b $Dst32RnExtUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDQI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI, { 0xc89e } + }, +/* exts.b $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc09e } + }, +/* exts.b [$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI, { 0xc01e } + }, +/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI, { 0xc21e00 } + }, +/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI, { 0xc41e0000 } + }, +/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI, { 0xc61e0000 } + }, +/* exts.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI, { 0xc29e00 } + }, +/* exts.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI, { 0xc49e0000 } + }, +/* exts.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI, { 0xc2de00 } + }, +/* exts.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI, { 0xc4de0000 } + }, +/* exts.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI, { 0xc6de0000 } + }, +/* exts.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI, { 0xc69e0000 } + }, +/* exts.b $Dst16RnExtQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNEXTQI), 0 } }, + & ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI, { 0x7c60 } + }, +/* exts.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI, { 0x7c66 } + }, +/* exts.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI, { 0x7c6800 } + }, +/* exts.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI, { 0x7c6c0000 } + }, +/* exts.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI, { 0x7c6a00 } + }, +/* exts.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI, { 0x7c6e0000 } + }, +/* exts.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI, { 0x7c6b00 } + }, +/* exts.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI, { 0x7c6f0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9390000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1390000 } + }, +/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9090000 } + }, +/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1890000 } + }, +/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1090000 } + }, +/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc909 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8929 } + }, +/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8909 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc189 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a9 } + }, +/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8189 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc109 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8129 } + }, +/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8109 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5090000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85290000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85090000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7090000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87290000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87090000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5890000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85890000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c90000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c90000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7890000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8390000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0390000 } + }, +/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8090000 } + }, +/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0890000 } + }, +/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0090000 } + }, +/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc809 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8829 } + }, +/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8809 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc089 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a9 } + }, +/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8089 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc009 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8029 } + }, +/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8009 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4090000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84290000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84090000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6090000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86290000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86090000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4890000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84890000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c90000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c90000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6890000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x898000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x89a000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x89b000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x898400 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x89a400 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x89b400 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x898600 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x89a600 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x89b600 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x89880000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x89a80000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x89b80000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x898c0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x89ac0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x89bc0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x898a0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89aa0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89ba0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x898e0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89ae0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89be0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x898b0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89ab0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89bb0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x898f0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x89af0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x89bf0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x89c00000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x89e00000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x89f00000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x89c40000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x89e40000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x89f40000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x89c60000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x89e60000 } + }, +/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x89f60000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x89c80000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x89e80000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x89f80000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x89cc0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x89ec0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x89fc0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ca0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ea0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x89fa0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ce0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ee0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x89fe0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x89cb0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x89eb0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x89fb0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x89cf0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x89ef0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x89ff0000 } + }, +/* xor.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8900 } + }, +/* xor.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8940 } + }, +/* xor.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8960 } + }, +/* xor.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8904 } + }, +/* xor.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8944 } + }, +/* xor.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8964 } + }, +/* xor.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8906 } + }, +/* xor.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8946 } + }, +/* xor.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8966 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x890800 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x894800 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x896800 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x890c0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x894c0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x896c0000 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x890a00 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x894a00 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x896a00 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x890e0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x894e0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x896e0000 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x890b00 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x894b00 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x896b00 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x890f0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x894f0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x896f0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x888000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x88a000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x88b000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x888400 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x88a400 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x88b400 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x888600 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x88a600 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x88b600 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x88880000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x88a80000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x88b80000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x888c0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x88ac0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x88bc0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x888a0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88aa0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88ba0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x888e0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88ae0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88be0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x888b0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88ab0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88bb0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x888f0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x88af0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x88bf0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x88c00000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x88e00000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x88f00000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x88c40000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x88e40000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x88f40000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x88c60000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x88e60000 } + }, +/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x88f60000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x88c80000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x88e80000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x88f80000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x88cc0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x88ec0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x88fc0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ca0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ea0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x88fa0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ce0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ee0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x88fe0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x88cb0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x88eb0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x88fb0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x88cf0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x88ef0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x88ff0000 } + }, +/* xor.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8800 } + }, +/* xor.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8840 } + }, +/* xor.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8860 } + }, +/* xor.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8804 } + }, +/* xor.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8844 } + }, +/* xor.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8864 } + }, +/* xor.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8806 } + }, +/* xor.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8846 } + }, +/* xor.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8866 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x880800 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x884800 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x886800 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x880c0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x884c0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x886c0000 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x880a00 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x884a00 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x886a00 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x880e0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x884e0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x886e0000 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x880b00 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x884b00 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x886b00 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x880f0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x884f0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x886f0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990e0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918e0000 } + }, +/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ce0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ce0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ce0000 } + }, +/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970e0000 } + }, +/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978e0000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980e00 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908e00 } + }, +/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900e00 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920e0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928e0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ce0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ce0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ce0000 } + }, +/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960e0000 } + }, +/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968e0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77100000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77140000 } + }, +/* xor.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77160000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77180000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x771a0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x771b0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x771c0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x771e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x771f0000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x761000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x761400 } + }, +/* xor.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x761600 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76180000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x761a0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x761b0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x761c0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x761e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x761f0000 } + }, +/* xchg.w r3,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90d } + }, +/* xchg.w r3,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18d } + }, +/* xchg.w r3,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10d } + }, +/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30d00 } + }, +/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50d0000 } + }, +/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70d0000 } + }, +/* xchg.w r3,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38d00 } + }, +/* xchg.w r3,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58d0000 } + }, +/* xchg.w r3,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cd00 } + }, +/* xchg.w r3,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cd0000 } + }, +/* xchg.w r3,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cd0000 } + }, +/* xchg.w r3,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78d0000 } + }, +/* xchg.w r2,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90c } + }, +/* xchg.w r2,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18c } + }, +/* xchg.w r2,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10c } + }, +/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30c00 } + }, +/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50c0000 } + }, +/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70c0000 } + }, +/* xchg.w r2,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38c00 } + }, +/* xchg.w r2,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58c0000 } + }, +/* xchg.w r2,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cc00 } + }, +/* xchg.w r2,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cc0000 } + }, +/* xchg.w r2,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cc0000 } + }, +/* xchg.w r2,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78c0000 } + }, +/* xchg.w a1,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90b } + }, +/* xchg.w a1,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18b } + }, +/* xchg.w a1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10b } + }, +/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30b00 } + }, +/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50b0000 } + }, +/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70b0000 } + }, +/* xchg.w a1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38b00 } + }, +/* xchg.w a1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58b0000 } + }, +/* xchg.w a1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cb00 } + }, +/* xchg.w a1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cb0000 } + }, +/* xchg.w a1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cb0000 } + }, +/* xchg.w a1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78b0000 } + }, +/* xchg.w a0,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90a } + }, +/* xchg.w a0,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18a } + }, +/* xchg.w a0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10a } + }, +/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30a00 } + }, +/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50a0000 } + }, +/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70a0000 } + }, +/* xchg.w a0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38a00 } + }, +/* xchg.w a0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58a0000 } + }, +/* xchg.w a0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3ca00 } + }, +/* xchg.w a0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5ca0000 } + }, +/* xchg.w a0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7ca0000 } + }, +/* xchg.w a0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78a0000 } + }, +/* xchg.w r1,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd909 } + }, +/* xchg.w r1,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd189 } + }, +/* xchg.w r1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd109 } + }, +/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30900 } + }, +/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5090000 } + }, +/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7090000 } + }, +/* xchg.w r1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38900 } + }, +/* xchg.w r1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5890000 } + }, +/* xchg.w r1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c900 } + }, +/* xchg.w r1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c90000 } + }, +/* xchg.w r1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c90000 } + }, +/* xchg.w r1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7890000 } + }, +/* xchg.w r0,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd908 } + }, +/* xchg.w r0,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd188 } + }, +/* xchg.w r0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd108 } + }, +/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30800 } + }, +/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5080000 } + }, +/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7080000 } + }, +/* xchg.w r0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38800 } + }, +/* xchg.w r0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5880000 } + }, +/* xchg.w r0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c800 } + }, +/* xchg.w r0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c80000 } + }, +/* xchg.w r0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c80000 } + }, +/* xchg.w r0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7880000 } + }, +/* xchg.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80d } + }, +/* xchg.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08d } + }, +/* xchg.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00d } + }, +/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20d00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40d0000 } + }, +/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60d0000 } + }, +/* xchg.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28d00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48d0000 } + }, +/* xchg.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cd00 } + }, +/* xchg.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cd0000 } + }, +/* xchg.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cd0000 } + }, +/* xchg.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68d0000 } + }, +/* xchg.b r0h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80c } + }, +/* xchg.b r0h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08c } + }, +/* xchg.b r0h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00c } + }, +/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20c00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40c0000 } + }, +/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60c0000 } + }, +/* xchg.b r0h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28c00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48c0000 } + }, +/* xchg.b r0h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cc00 } + }, +/* xchg.b r0h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cc0000 } + }, +/* xchg.b r0h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cc0000 } + }, +/* xchg.b r0h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68c0000 } + }, +/* xchg.b a1,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80b } + }, +/* xchg.b a1,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08b } + }, +/* xchg.b a1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00b } + }, +/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20b00 } + }, +/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40b0000 } + }, +/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60b0000 } + }, +/* xchg.b a1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28b00 } + }, +/* xchg.b a1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48b0000 } + }, +/* xchg.b a1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cb00 } + }, +/* xchg.b a1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cb0000 } + }, +/* xchg.b a1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cb0000 } + }, +/* xchg.b a1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68b0000 } + }, +/* xchg.b a0,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80a } + }, +/* xchg.b a0,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08a } + }, +/* xchg.b a0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00a } + }, +/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20a00 } + }, +/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40a0000 } + }, +/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60a0000 } + }, +/* xchg.b a0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28a00 } + }, +/* xchg.b a0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48a0000 } + }, +/* xchg.b a0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2ca00 } + }, +/* xchg.b a0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4ca0000 } + }, +/* xchg.b a0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6ca0000 } + }, +/* xchg.b a0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68a0000 } + }, +/* xchg.b r1l,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd809 } + }, +/* xchg.b r1l,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd089 } + }, +/* xchg.b r1l,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd009 } + }, +/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20900 } + }, +/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4090000 } + }, +/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6090000 } + }, +/* xchg.b r1l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28900 } + }, +/* xchg.b r1l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4890000 } + }, +/* xchg.b r1l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c900 } + }, +/* xchg.b r1l,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c90000 } + }, +/* xchg.b r1l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c90000 } + }, +/* xchg.b r1l,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6890000 } + }, +/* xchg.b r0l,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd808 } + }, +/* xchg.b r0l,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd088 } + }, +/* xchg.b r0l,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd008 } + }, +/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4080000 } + }, +/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6080000 } + }, +/* xchg.b r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4880000 } + }, +/* xchg.b r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c800 } + }, +/* xchg.b r0l,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c80000 } + }, +/* xchg.b r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c80000 } + }, +/* xchg.b r0l,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6880000 } + }, +/* xchg.w r3,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b30 } + }, +/* xchg.w r3,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b34 } + }, +/* xchg.w r3,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b36 } + }, +/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b3800 } + }, +/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b3c0000 } + }, +/* xchg.w r3,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b3a00 } + }, +/* xchg.w r3,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b3e0000 } + }, +/* xchg.w r3,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b3b00 } + }, +/* xchg.w r3,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b3f0000 } + }, +/* xchg.w r2,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b20 } + }, +/* xchg.w r2,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b24 } + }, +/* xchg.w r2,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b26 } + }, +/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b2800 } + }, +/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b2c0000 } + }, +/* xchg.w r2,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b2a00 } + }, +/* xchg.w r2,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b2e0000 } + }, +/* xchg.w r2,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b2b00 } + }, +/* xchg.w r2,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b2f0000 } + }, +/* xchg.w r1,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b10 } + }, +/* xchg.w r1,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b14 } + }, +/* xchg.w r1,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b16 } + }, +/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b1800 } + }, +/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b1c0000 } + }, +/* xchg.w r1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b1a00 } + }, +/* xchg.w r1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b1e0000 } + }, +/* xchg.w r1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b1b00 } + }, +/* xchg.w r1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 } + }, +/* xchg.w r0,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b00 } + }, +/* xchg.w r0,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b04 } + }, +/* xchg.w r0,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b06 } + }, +/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b0800 } + }, +/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b0c0000 } + }, +/* xchg.w r0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b0a00 } + }, +/* xchg.w r0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b0e0000 } + }, +/* xchg.w r0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b0b00 } + }, +/* xchg.w r0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b0f0000 } + }, +/* xchg.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a30 } + }, +/* xchg.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a34 } + }, +/* xchg.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a36 } + }, +/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a3800 } + }, +/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a3c0000 } + }, +/* xchg.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a3a00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a3e0000 } + }, +/* xchg.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a3b00 } + }, +/* xchg.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a3f0000 } + }, +/* xchg.b r1l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a20 } + }, +/* xchg.b r1l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a24 } + }, +/* xchg.b r1l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a26 } + }, +/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a2800 } + }, +/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a2c0000 } + }, +/* xchg.b r1l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a2a00 } + }, +/* xchg.b r1l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a2e0000 } + }, +/* xchg.b r1l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a2b00 } + }, +/* xchg.b r1l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a2f0000 } + }, +/* xchg.b r0h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a10 } + }, +/* xchg.b r0h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a14 } + }, +/* xchg.b r0h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a16 } + }, +/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a1800 } + }, +/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a1c0000 } + }, +/* xchg.b r0h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a1a00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a1e0000 } + }, +/* xchg.b r0h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a1b00 } + }, +/* xchg.b r0h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a1f0000 } + }, +/* xchg.b r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_Rn_direct_QI, { 0x7a00 } + }, +/* xchg.b r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16b_r1h_dst16_An_direct_QI, { 0x7a04 } + }, +/* xchg.b r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_An_indirect_QI, { 0x7a06 } + }, +/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_An_relative_QI, { 0x7a0800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_An_relative_QI, { 0x7a0c0000 } + }, +/* xchg.b r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_SB_relative_QI, { 0x7a0a00 } + }, +/* xchg.b r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_SB_relative_QI, { 0x7a0e0000 } + }, +/* xchg.b r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16b_r1h_dst16_16_8_FB_relative_QI, { 0x7a0b00 } + }, +/* xchg.b r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16b_r1h_dst16_16_16_absolute_QI, { 0x7a0f0000 } + }, +/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2d000000 } + }, +/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3d000000 } + }, +/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1d000000 } + }, +/* tst.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xd0000 } + }, +/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2c0000 } + }, +/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3c0000 } + }, +/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1c000000 } + }, +/* tst.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 } + }, +/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 } + }, +/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 } + }, +/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 } + }, +/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 } + }, +/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 } + }, +/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 } + }, +/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 } + }, +/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 } + }, +/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 } + }, +/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 } + }, +/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 } + }, +/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 } + }, +/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 } + }, +/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 } + }, +/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 } + }, +/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 } + }, +/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 } + }, +/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 } + }, +/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 } + }, +/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 } + }, +/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 } + }, +/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 } + }, +/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 } + }, +/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 } + }, +/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 } + }, +/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 } + }, +/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 } + }, +/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 } + }, +/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 } + }, +/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 } + }, +/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 } + }, +/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 } + }, +/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 } + }, +/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 } + }, +/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 } + }, +/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 } + }, +/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 } + }, +/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 } + }, +/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 } + }, +/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 } + }, +/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 } + }, +/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 } + }, +/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 } + }, +/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 } + }, +/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 } + }, +/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 } + }, +/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 } + }, +/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 } + }, +/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 } + }, +/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 } + }, +/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 } + }, +/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x818000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x81a000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x81b000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x818400 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x81a400 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x81b400 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x818600 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x81a600 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x81b600 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x81880000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x81a80000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x81b80000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x818c0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x81ac0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x81bc0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x818a0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81aa0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81ba0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x818e0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81ae0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81be0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x818b0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81ab0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81bb0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x818f0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x81af0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x81bf0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x81c00000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x81e00000 } + }, +/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x81f00000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x81c40000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x81e40000 } + }, +/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x81f40000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x81c60000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x81e60000 } + }, +/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x81f60000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x81c80000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x81e80000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x81f80000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x81cc0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x81ec0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x81fc0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ca0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ea0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x81fa0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ce0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ee0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x81fe0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x81cb0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x81eb0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x81fb0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x81cf0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x81ef0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x81ff0000 } + }, +/* tst.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8100 } + }, +/* tst.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8140 } + }, +/* tst.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8160 } + }, +/* tst.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8104 } + }, +/* tst.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8144 } + }, +/* tst.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8164 } + }, +/* tst.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8106 } + }, +/* tst.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8146 } + }, +/* tst.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8166 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x810800 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x814800 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x816800 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x810c0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x814c0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x816c0000 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x810a00 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x814a00 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x816a00 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x810e0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x814e0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x816e0000 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x810b00 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x814b00 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x816b00 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x810f0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x814f0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x816f0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x808000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x80a000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x80b000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x808400 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x80a400 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x80b400 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x808600 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x80a600 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x80b600 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x80880000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x80a80000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x80b80000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x808c0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x80ac0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x80bc0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x808a0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80aa0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80ba0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x808e0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80ae0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80be0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x808b0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80ab0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80bb0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x808f0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x80af0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x80bf0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x80c00000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x80e00000 } + }, +/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x80f00000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x80c40000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x80e40000 } + }, +/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x80f40000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x80c60000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x80e60000 } + }, +/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x80f60000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x80c80000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x80e80000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x80f80000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x80cc0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x80ec0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x80fc0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ca0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ea0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x80fa0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ce0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ee0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x80fe0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x80cb0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x80eb0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x80fb0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x80cf0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x80ef0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x80ff0000 } + }, +/* tst.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8000 } + }, +/* tst.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8040 } + }, +/* tst.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8060 } + }, +/* tst.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8004 } + }, +/* tst.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8044 } + }, +/* tst.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8064 } + }, +/* tst.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8006 } + }, +/* tst.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8046 } + }, +/* tst.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8066 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x800800 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x804800 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x806800 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x800c0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x804c0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x806c0000 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x800a00 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x804a00 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x806a00 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x800e0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x804e0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x806e0000 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x800b00 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x804b00 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x806b00 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x800f0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x804f0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 } + }, +/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 } + }, +/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 } + }, +/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 } + }, +/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 } + }, +/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 } + }, +/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 } + }, +/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 } + }, +/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 } + }, +/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 } + }, +/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 } + }, +/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 } + }, +/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 } + }, +/* tst.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 } + }, +/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 } + }, +/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 } + }, +/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 } + }, +/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 } + }, +/* tst.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 } + }, +/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 } + }, +/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8300000 } + }, +/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b00000 } + }, +/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0300000 } + }, +/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8000000 } + }, +/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0800000 } + }, +/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0000000 } + }, +/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc800 } + }, +/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8820 } + }, +/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8800 } + }, +/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc080 } + }, +/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a0 } + }, +/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8080 } + }, +/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc000 } + }, +/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8020 } + }, +/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4000000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84200000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84000000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6000000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86200000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86000000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4800000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84800000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c00000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c00000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6800000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86800000 } + }, +/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x981100 } + }, +/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x909100 } + }, +/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x901100 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92110000 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92910000 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92d10000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94110000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94910000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94d10000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96d10000 } + }, +/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96110000 } + }, +/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96910000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993f0000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91bf0000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913f0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933f0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93bf0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ff0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953f0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95bf0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ff0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ff0000 } + }, +/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973f0000 } + }, +/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97bf0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983f0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90bf0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903f0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923f0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92bf0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ff0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943f0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94bf0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ff0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ff0000 } + }, +/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963f0000 } + }, +/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96bf0000 } + }, +/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990f0000 } + }, +/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918f0000 } + }, +/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93cf0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950f0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958f0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95cf0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97cf0000 } + }, +/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970f0000 } + }, +/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978f0000 } + }, +/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980f00 } + }, +/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908f00 } + }, +/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900f00 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920f0000 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928f0000 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92cf0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940f0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948f0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94cf0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96cf0000 } + }, +/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960f0000 } + }, +/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968f0000 } + }, +/* stz${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xcc00 } + }, +/* stz${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xcb00 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xcd0000 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xce0000 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xcf000000 } + }, +/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x991f0000 } + }, +/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x919f0000 } + }, +/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x911f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x931f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93df0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x951f0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959f0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95df0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97df0000 } + }, +/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x971f0000 } + }, +/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x979f0000 } + }, +/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x981f00 } + }, +/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x909f00 } + }, +/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x901f00 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x921f0000 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929f0000 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92df0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x941f0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949f0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94df0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96df0000 } + }, +/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x961f0000 } + }, +/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x969f0000 } + }, +/* stnz${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xd400 } + }, +/* stnz${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xd300 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xd50000 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xd60000 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xd7000000 } + }, +/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x882100 } + }, +/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80a100 } + }, +/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x802100 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82210000 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a10000 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84210000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86e10000 } + }, +/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86210000 } + }, +/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86a10000 } + }, +/* shl.l r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc801 } + }, +/* shl.l r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc081 } + }, +/* shl.l r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc001 } + }, +/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20100 } + }, +/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4010000 } + }, +/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6010000 } + }, +/* shl.l r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28100 } + }, +/* shl.l r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4810000 } + }, +/* shl.l r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c100 } + }, +/* shl.l r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c10000 } + }, +/* shl.l r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c10000 } + }, +/* shl.l r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6810000 } + }, +/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x982100 } + }, +/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90a100 } + }, +/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x902100 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92210000 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92a10000 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92e10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94210000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94a10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94e10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96e10000 } + }, +/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96210000 } + }, +/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96a10000 } + }, +/* shl.w r1h,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93e } + }, +/* shl.w r1h,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1be } + }, +/* shl.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13e } + }, +/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33e00 } + }, +/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53e0000 } + }, +/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73e0000 } + }, +/* shl.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3be00 } + }, +/* shl.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5be0000 } + }, +/* shl.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3fe00 } + }, +/* shl.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5fe0000 } + }, +/* shl.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7fe0000 } + }, +/* shl.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7be0000 } + }, +/* shl.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83e } + }, +/* shl.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0be } + }, +/* shl.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03e } + }, +/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23e00 } + }, +/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43e0000 } + }, +/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63e0000 } + }, +/* shl.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2be00 } + }, +/* shl.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4be0000 } + }, +/* shl.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2fe00 } + }, +/* shl.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4fe0000 } + }, +/* shl.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6fe0000 } + }, +/* shl.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6be0000 } + }, +/* shl.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75e0 } + }, +/* shl.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75e4 } + }, +/* shl.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75e6 } + }, +/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75e800 } + }, +/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75ec0000 } + }, +/* shl.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75ea00 } + }, +/* shl.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75ee0000 } + }, +/* shl.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75eb00 } + }, +/* shl.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ef0000 } + }, +/* shl.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74e0 } + }, +/* shl.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74e4 } + }, +/* shl.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74e6 } + }, +/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74e800 } + }, +/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74ec0000 } + }, +/* shl.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74ea00 } + }, +/* shl.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74ee0000 } + }, +/* shl.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74eb00 } + }, +/* shl.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ef0000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe900 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe180 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe100 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe30000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5000000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7000000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe38000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5800000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3c000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5c00000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7c00000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7800000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe800 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe080 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe20000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4000000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6000000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe28000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4800000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2c000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4c00000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6c00000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6800000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe900 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe904 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe906 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe90800 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe90c0000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe90a00 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe90e0000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe90b00 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe90f0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe800 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe804 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe806 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe80800 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe80c0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe80a00 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe80e0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe80b00 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe80f0000 } + }, +/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xc82100 } + }, +/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xc0a100 } + }, +/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xc02100 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xc2210000 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc2a10000 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2e10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4210000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4a10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4e10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xc6e10000 } + }, +/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6210000 } + }, +/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xc6a10000 } + }, +/* sha.l r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc811 } + }, +/* sha.l r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc091 } + }, +/* sha.l r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc011 } + }, +/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc21100 } + }, +/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4110000 } + }, +/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6110000 } + }, +/* sha.l r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc29100 } + }, +/* sha.l r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4910000 } + }, +/* sha.l r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2d100 } + }, +/* sha.l r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4d10000 } + }, +/* sha.l r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6d10000 } + }, +/* sha.l r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6910000 } + }, +/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa82100 } + }, +/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0a100 } + }, +/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa02100 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2210000 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2a10000 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2e10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4210000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4a10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4e10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6e10000 } + }, +/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6210000 } + }, +/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6a10000 } + }, +/* sha.w r1h,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb93e } + }, +/* sha.w r1h,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1be } + }, +/* sha.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb13e } + }, +/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33e00 } + }, +/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb53e0000 } + }, +/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb73e0000 } + }, +/* sha.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3be00 } + }, +/* sha.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5be0000 } + }, +/* sha.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3fe00 } + }, +/* sha.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5fe0000 } + }, +/* sha.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7fe0000 } + }, +/* sha.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7be0000 } + }, +/* sha.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb83e } + }, +/* sha.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0be } + }, +/* sha.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb03e } + }, +/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb23e00 } + }, +/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb43e0000 } + }, +/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb63e0000 } + }, +/* sha.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2be00 } + }, +/* sha.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4be0000 } + }, +/* sha.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2fe00 } + }, +/* sha.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4fe0000 } + }, +/* sha.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6fe0000 } + }, +/* sha.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6be0000 } + }, +/* sha.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75f0 } + }, +/* sha.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75f4 } + }, +/* sha.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75f6 } + }, +/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75f800 } + }, +/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75fc0000 } + }, +/* sha.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75fa00 } + }, +/* sha.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75fe0000 } + }, +/* sha.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75fb00 } + }, +/* sha.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ff0000 } + }, +/* sha.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74f0 } + }, +/* sha.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74f4 } + }, +/* sha.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74f6 } + }, +/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74f800 } + }, +/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74fc0000 } + }, +/* sha.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74fa00 } + }, +/* sha.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74fe0000 } + }, +/* sha.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74fb00 } + }, +/* sha.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ff0000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf900 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf180 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf100 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf30000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5000000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7000000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf38000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5800000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3c000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5c00000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7c00000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7800000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf800 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf080 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf20000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4000000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6000000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf28000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4800000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2c000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4c00000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6c00000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6800000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xf100 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xf104 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xf106 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xf10800 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xf10c0000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xf10a00 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xf10e0000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xf10b00 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xf10f0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xf000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xf004 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xf006 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xf00800 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xf00c0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xf00a00 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xf00e0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xf00b00 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xf00f0000 } + }, +/* sc${sccond32} $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI, { 0xd930 } + }, +/* sc${sccond32} $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_sccnd_dst32_An_direct_Unprefixed_HI, { 0xd1b0 } + }, +/* sc${sccond32} [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_An_indirect_Unprefixed_HI, { 0xd130 } + }, +/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI, { 0xd33000 } + }, +/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5300000 } + }, +/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7300000 } + }, +/* sc${sccond32} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd3b000 } + }, +/* sc${sccond32} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5b00000 } + }, +/* sc${sccond32} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3f000 } + }, +/* sc${sccond32} ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5f00000 } + }, +/* sc${sccond32} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI, { 0xd7f00000 } + }, +/* sc${sccond32} ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } }, + & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 } + }, +/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 } + }, +/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 } + }, +/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 } + }, +/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 } + }, +/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 } + }, +/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 } + }, +/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 } + }, +/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4N), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 } + }, +/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 } + }, +/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 } + }, +/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 } + }, +/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 } + }, +/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 } + }, +/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 } + }, +/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 } + }, +/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4N), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93600 } + }, +/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13600 } + }, +/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90600 } + }, +/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18600 } + }, +/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10600 } + }, +/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c906 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18926 } + }, +/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18906 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c186 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a6 } + }, +/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18186 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c106 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18126 } + }, +/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18106 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83600 } + }, +/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03600 } + }, +/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80600 } + }, +/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08600 } + }, +/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00600 } + }, +/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c806 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18826 } + }, +/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18806 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c086 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a6 } + }, +/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18086 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c006 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18026 } + }, +/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18006 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb98000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9a000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb9b000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb98400 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb9a400 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb9b400 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb98600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb9a600 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb9b600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb9880000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9a80000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9b80000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb98c0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9ac0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9bc0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb98a0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9aa0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9ba0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb98e0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9ae0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9be0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb98b0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9ab0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9bb0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb98f0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb9af0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb9bf0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb9c00000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9e00000 } + }, +/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb9f00000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb9c40000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb9e40000 } + }, +/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb9f40000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb9c60000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb9e60000 } + }, +/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb9f60000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb9c80000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb9e80000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb9f80000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb9cc0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb9ec0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb9fc0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ca0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ea0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb9fa0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ce0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ee0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb9fe0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9cb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9eb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb9fb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb9cf0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb9ef0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb9ff0000 } + }, +/* sbb.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb900 } + }, +/* sbb.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb940 } + }, +/* sbb.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb960 } + }, +/* sbb.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb904 } + }, +/* sbb.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb944 } + }, +/* sbb.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb964 } + }, +/* sbb.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb906 } + }, +/* sbb.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb946 } + }, +/* sbb.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb966 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb90800 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb94800 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb96800 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb90c0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb94c0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb96c0000 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb90a00 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb94a00 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb96a00 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb90e0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb94e0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb96e0000 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb90b00 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb94b00 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb96b00 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb90f0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb94f0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb96f0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb88000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8a000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb8b000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb88400 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb8a400 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb8b400 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb88600 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb8a600 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb8b600 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb8880000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8a80000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8b80000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb88c0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8ac0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8bc0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb88a0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8aa0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8ba0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb88e0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8ae0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8be0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb88b0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8ab0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8bb0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb88f0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb8af0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb8bf0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb8c00000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8e00000 } + }, +/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb8f00000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb8c40000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb8e40000 } + }, +/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb8f40000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb8c60000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb8e60000 } + }, +/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb8f60000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb8c80000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb8e80000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb8f80000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb8cc0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb8ec0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb8fc0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ca0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ea0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb8fa0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ce0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ee0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb8fe0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8cb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8eb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb8fb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb8cf0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb8ef0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb8ff0000 } + }, +/* sbb.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb800 } + }, +/* sbb.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb840 } + }, +/* sbb.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb860 } + }, +/* sbb.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb804 } + }, +/* sbb.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb844 } + }, +/* sbb.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb864 } + }, +/* sbb.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb806 } + }, +/* sbb.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb846 } + }, +/* sbb.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb866 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb80800 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb84800 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb86800 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb80c0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb84c0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb86c0000 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb80a00 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb84a00 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb86a00 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb80e0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb84e0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb86e0000 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb80b00 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb84b00 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb86b00 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb80f0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb84f0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb86f0000 } + }, +/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1992e00 } + }, +/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x191ae00 } + }, +/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1912e00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1932e00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x193ae00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ee00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1952e00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x195ae00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ee00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ee00 } + }, +/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1972e00 } + }, +/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x197ae00 } + }, +/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1982e00 } + }, +/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x190ae00 } + }, +/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1902e00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1922e00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x192ae00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ee00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1942e00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x194ae00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ee00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ee00 } + }, +/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1962e00 } + }, +/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x196ae00 } + }, +/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77700000 } + }, +/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77740000 } + }, +/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77760000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77780000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x777a0000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x777b0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x777c0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x777e0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x777f0000 } + }, +/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x767000 } + }, +/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x767400 } + }, +/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x767600 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76780000 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x767a0000 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x767b0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x767c0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x767e0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 } + }, +/* rot.w r1h,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93f } + }, +/* rot.w r1h,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1bf } + }, +/* rot.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13f } + }, +/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33f00 } + }, +/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53f0000 } + }, +/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73f0000 } + }, +/* rot.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3bf00 } + }, +/* rot.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5bf0000 } + }, +/* rot.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ff00 } + }, +/* rot.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ff0000 } + }, +/* rot.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ff0000 } + }, +/* rot.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7bf0000 } + }, +/* rot.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83f } + }, +/* rot.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0bf } + }, +/* rot.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03f } + }, +/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23f00 } + }, +/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43f0000 } + }, +/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63f0000 } + }, +/* rot.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2bf00 } + }, +/* rot.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4bf0000 } + }, +/* rot.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ff00 } + }, +/* rot.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ff0000 } + }, +/* rot.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ff0000 } + }, +/* rot.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6bf0000 } + }, +/* rot.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7560 } + }, +/* rot.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7564 } + }, +/* rot.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7566 } + }, +/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x756800 } + }, +/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x756c0000 } + }, +/* rot.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x756a00 } + }, +/* rot.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x756e0000 } + }, +/* rot.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x756b00 } + }, +/* rot.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 } + }, +/* rot.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7460 } + }, +/* rot.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7464 } + }, +/* rot.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7466 } + }, +/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x746800 } + }, +/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x746c0000 } + }, +/* rot.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x746a00 } + }, +/* rot.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x746e0000 } + }, +/* rot.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x746b00 } + }, +/* rot.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x746f0000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe920 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1a0 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe120 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe32000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5200000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7200000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3a000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5a00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3e000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5e00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7e00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7a00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe820 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0a0 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe020 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe22000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4200000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6200000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2a000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4a00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2e000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4e00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6e00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6a00000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe100 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe104 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe106 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe10800 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe10c0000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe10a00 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe10e0000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe10b00 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe10f0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe004 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe006 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe00800 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe00c0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe00a00 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe00e0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe00b00 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe00f0000 } + }, +/* rorc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92e } + }, +/* rorc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1ae } + }, +/* rorc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12e } + }, +/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32e00 } + }, +/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52e0000 } + }, +/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72e0000 } + }, +/* rorc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3ae00 } + }, +/* rorc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5ae0000 } + }, +/* rorc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ee00 } + }, +/* rorc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ee0000 } + }, +/* rorc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ee0000 } + }, +/* rorc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7ae0000 } + }, +/* rorc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82e } + }, +/* rorc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0ae } + }, +/* rorc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02e } + }, +/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22e00 } + }, +/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42e0000 } + }, +/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62e0000 } + }, +/* rorc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2ae00 } + }, +/* rorc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4ae0000 } + }, +/* rorc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ee00 } + }, +/* rorc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ee0000 } + }, +/* rorc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ee0000 } + }, +/* rorc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6ae0000 } + }, +/* rorc.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77b0 } + }, +/* rorc.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77b4 } + }, +/* rorc.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77b6 } + }, +/* rorc.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77b800 } + }, +/* rorc.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77bc0000 } + }, +/* rorc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ba00 } + }, +/* rorc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77be0000 } + }, +/* rorc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77bb00 } + }, +/* rorc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77bf0000 } + }, +/* rorc.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76b0 } + }, +/* rorc.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76b4 } + }, +/* rorc.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76b6 } + }, +/* rorc.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76b800 } + }, +/* rorc.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76bc0000 } + }, +/* rorc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ba00 } + }, +/* rorc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76be0000 } + }, +/* rorc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76bb00 } + }, +/* rorc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76bf0000 } + }, +/* rolc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92e } + }, +/* rolc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1ae } + }, +/* rolc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12e } + }, +/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32e00 } + }, +/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52e0000 } + }, +/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72e0000 } + }, +/* rolc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3ae00 } + }, +/* rolc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5ae0000 } + }, +/* rolc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ee00 } + }, +/* rolc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ee0000 } + }, +/* rolc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ee0000 } + }, +/* rolc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7ae0000 } + }, +/* rolc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82e } + }, +/* rolc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0ae } + }, +/* rolc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02e } + }, +/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22e00 } + }, +/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42e0000 } + }, +/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62e0000 } + }, +/* rolc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2ae00 } + }, +/* rolc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4ae0000 } + }, +/* rolc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ee00 } + }, +/* rolc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ee0000 } + }, +/* rolc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ee0000 } + }, +/* rolc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6ae0000 } + }, +/* rolc.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77a0 } + }, +/* rolc.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77a4 } + }, +/* rolc.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77a6 } + }, +/* rolc.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77a800 } + }, +/* rolc.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ac0000 } + }, +/* rolc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77aa00 } + }, +/* rolc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ae0000 } + }, +/* rolc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77ab00 } + }, +/* rolc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77af0000 } + }, +/* rolc.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76a0 } + }, +/* rolc.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76a4 } + }, +/* rolc.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76a6 } + }, +/* rolc.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76a800 } + }, +/* rolc.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ac0000 } + }, +/* rolc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76aa00 } + }, +/* rolc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ae0000 } + }, +/* rolc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76ab00 } + }, +/* rolc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76af0000 } + }, +/* pusha [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI, { 0xb001 } + }, +/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xb20100 } + }, +/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xb4010000 } + }, +/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xb6010000 } + }, +/* pusha ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xb28100 } + }, +/* pusha ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xb4810000 } + }, +/* pusha ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xb2c100 } + }, +/* pusha ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xb4c10000 } + }, +/* pusha ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xb6c10000 } + }, +/* pusha ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xb6810000 } + }, +/* pusha [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0x7d96 } + }, +/* pusha ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0x7d9800 } + }, +/* pusha ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0x7d9c0000 } + }, +/* pusha ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0x7d9a00 } + }, +/* pusha ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0x7d9e0000 } + }, +/* pusha ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0x7d9b00 } + }, +/* pusha ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0x7d9f0000 } + }, +/* push.l $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa801 } + }, +/* push.l $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa081 } + }, +/* push.l [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa001 } + }, +/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa20100 } + }, +/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4010000 } + }, +/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6010000 } + }, +/* push.l ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa28100 } + }, +/* push.l ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4810000 } + }, +/* push.l ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2c100 } + }, +/* push.l ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4c10000 } + }, +/* push.l ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6c10000 } + }, +/* push.l ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6810000 } + }, +/* push.w${S} ${An16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_an_An16_push_S_derived, { 0xc2 } + }, +/* push.b${S} ${Rn16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x82 } + }, +/* push.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90e } + }, +/* push.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18e } + }, +/* push.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10e } + }, +/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30e00 } + }, +/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50e0000 } + }, +/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70e0000 } + }, +/* push.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38e00 } + }, +/* push.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58e0000 } + }, +/* push.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ce00 } + }, +/* push.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ce0000 } + }, +/* push.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ce0000 } + }, +/* push.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78e0000 } + }, +/* push.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc80e } + }, +/* push.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc08e } + }, +/* push.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc00e } + }, +/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20e00 } + }, +/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40e0000 } + }, +/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60e0000 } + }, +/* push.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28e00 } + }, +/* push.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48e0000 } + }, +/* push.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ce00 } + }, +/* push.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ce0000 } + }, +/* push.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ce0000 } + }, +/* push.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 } + }, +/* push.w${G} $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 } + }, +/* push.w${G} $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 } + }, +/* push.w${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 } + }, +/* push.w${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 } + }, +/* push.w${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 } + }, +/* push.w${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 } + }, +/* push.w${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 } + }, +/* push.w${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 } + }, +/* push.w${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 } + }, +/* push.b${G} $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 } + }, +/* push.b${G} $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 } + }, +/* push.b${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 } + }, +/* push.b${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 } + }, +/* push.b${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 } + }, +/* push.b${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 } + }, +/* push.b${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 } + }, +/* push.b${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 } + }, +/* push.b${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 } + }, +/* pop.w${S} ${An16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_an_An16_push_S_derived, { 0xd2 } + }, +/* pop.b${S} ${Rn16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x92 } + }, +/* pop.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92f } + }, +/* pop.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1af } + }, +/* pop.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12f } + }, +/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32f00 } + }, +/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52f0000 } + }, +/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72f0000 } + }, +/* pop.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3af00 } + }, +/* pop.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5af0000 } + }, +/* pop.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ef00 } + }, +/* pop.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ef0000 } + }, +/* pop.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ef0000 } + }, +/* pop.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7af0000 } + }, +/* pop.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82f } + }, +/* pop.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0af } + }, +/* pop.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02f } + }, +/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22f00 } + }, +/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42f0000 } + }, +/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62f0000 } + }, +/* pop.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2af00 } + }, +/* pop.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4af0000 } + }, +/* pop.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ef00 } + }, +/* pop.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ef0000 } + }, +/* pop.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ef0000 } + }, +/* pop.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6af0000 } + }, +/* pop.w${G} $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75d0 } + }, +/* pop.w${G} $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75d4 } + }, +/* pop.w${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75d6 } + }, +/* pop.w${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75d800 } + }, +/* pop.w${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75dc0000 } + }, +/* pop.w${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75da00 } + }, +/* pop.w${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75de0000 } + }, +/* pop.w${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75db00 } + }, +/* pop.w${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75df0000 } + }, +/* pop.b${G} $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74d0 } + }, +/* pop.b${G} $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74d4 } + }, +/* pop.b${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74d6 } + }, +/* pop.b${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74d800 } + }, +/* pop.b${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74dc0000 } + }, +/* pop.b${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74da00 } + }, +/* pop.b${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74de0000 } + }, +/* pop.b${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74db00 } + }, +/* pop.b${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74df0000 } + }, +/* or.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x18 } + }, +/* or.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1900 } + }, +/* or.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1a00 } + }, +/* or.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x1b0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9350000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b50000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1350000 } + }, +/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9050000 } + }, +/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1850000 } + }, +/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1050000 } + }, +/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc905 } + }, +/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8925 } + }, +/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8905 } + }, +/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc185 } + }, +/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a5 } + }, +/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8185 } + }, +/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc105 } + }, +/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8125 } + }, +/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8105 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5050000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85250000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85050000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7050000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87250000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87050000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5850000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85850000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c50000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c50000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7850000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87850000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8350000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b50000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0350000 } + }, +/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8050000 } + }, +/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0850000 } + }, +/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0050000 } + }, +/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc805 } + }, +/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8825 } + }, +/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8805 } + }, +/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc085 } + }, +/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a5 } + }, +/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8085 } + }, +/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc005 } + }, +/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8025 } + }, +/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8005 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4050000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84250000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84050000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6050000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86250000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86050000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4850000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84850000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c50000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c50000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6850000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86850000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x998000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x99a000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x99b000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x998400 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x99a400 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x99b400 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x998600 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x99a600 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x99b600 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x99880000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x99a80000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x99b80000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x998c0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x99ac0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x99bc0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x998a0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99aa0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99ba0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x998e0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99ae0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99be0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x998b0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99ab0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99bb0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x998f0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x99af0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x99bf0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x99c00000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x99e00000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x99f00000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x99c40000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x99e40000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x99f40000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x99c60000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x99e60000 } + }, +/* or.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x99f60000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x99c80000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x99e80000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x99f80000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x99cc0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x99ec0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x99fc0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ca0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ea0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x99fa0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ce0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ee0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x99fe0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x99cb0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x99eb0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x99fb0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x99cf0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x99ef0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x99ff0000 } + }, +/* or.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9900 } + }, +/* or.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9940 } + }, +/* or.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9960 } + }, +/* or.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9904 } + }, +/* or.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9944 } + }, +/* or.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9964 } + }, +/* or.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9906 } + }, +/* or.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9946 } + }, +/* or.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9966 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x990800 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x994800 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x996800 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x990c0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x994c0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x996c0000 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x990a00 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x994a00 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x996a00 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x990e0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x994e0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x996e0000 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x990b00 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x994b00 } + }, +/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x996b00 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x990f0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x994f0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x996f0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x988000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x98a000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x98b000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x988400 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x98a400 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x98b400 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x988600 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x98a600 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x98b600 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x98880000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x98a80000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x98b80000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x988c0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x98ac0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x98bc0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x988a0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98aa0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98ba0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x988e0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98ae0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98be0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x988b0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98ab0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98bb0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x988f0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x98af0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x98bf0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x98c00000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x98e00000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x98f00000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x98c40000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x98e40000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x98f40000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x98c60000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x98e60000 } + }, +/* or.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x98f60000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x98c80000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x98e80000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x98f80000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x98cc0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x98ec0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x98fc0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ca0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ea0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x98fa0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ce0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ee0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x98fe0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x98cb0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x98eb0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x98fb0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x98cf0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x98ef0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x98ff0000 } + }, +/* or.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9800 } + }, +/* or.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9840 } + }, +/* or.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9860 } + }, +/* or.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9804 } + }, +/* or.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9844 } + }, +/* or.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9864 } + }, +/* or.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9806 } + }, +/* or.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9846 } + }, +/* or.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9866 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x980800 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x984800 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x986800 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x980c0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x984c0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x986c0000 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x980a00 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x984a00 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x986a00 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x980e0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x984e0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x986e0000 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x980b00 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x984b00 } + }, +/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x986b00 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x980f0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x984f0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x986f0000 } + }, +/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x65000000 } + }, +/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x75000000 } + }, +/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x55000000 } + }, +/* or.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x450000 } + }, +/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x640000 } + }, +/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x740000 } + }, +/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x54000000 } + }, +/* or.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4400 } + }, +/* or.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9c00 } + }, +/* or.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9b00 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x9d0000 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x9e0000 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x9f000000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892f0000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81af0000 } + }, +/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812f0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832f0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83af0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ef0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852f0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85af0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ef0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ef0000 } + }, +/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872f0000 } + }, +/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87af0000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882f00 } + }, +/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80af00 } + }, +/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802f00 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822f0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82af0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ef0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842f0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84af0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ef0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ef0000 } + }, +/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862f0000 } + }, +/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86af0000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77300000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77340000 } + }, +/* or.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77360000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77380000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x773a0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x773b0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x773c0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x773e0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x773f0000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x763000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x763400 } + }, +/* or.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x763600 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76380000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x763a0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x763b0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x763c0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x763e0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 } + }, +/* not.b:s r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xbc } + }, +/* not.b:s r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xbb } + }, +/* not.b:s ${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xbd00 } + }, +/* not.b:s ${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xbe00 } + }, +/* not.b:s ${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U16), 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xbf0000 } + }, +/* not.w${G} $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e } + }, +/* not.w${G} $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e } + }, +/* not.w${G} [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e } + }, +/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 } + }, +/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 } + }, +/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 } + }, +/* not.w${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 } + }, +/* not.w${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 } + }, +/* not.w${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 } + }, +/* not.w${G} ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 } + }, +/* not.w${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 } + }, +/* not.w${G} ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 } + }, +/* not.b${G} $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e } + }, +/* not.b${G} $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e } + }, +/* not.b${G} [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e } + }, +/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 } + }, +/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 } + }, +/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 } + }, +/* not.b${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 } + }, +/* not.b${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 } + }, +/* not.b${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 } + }, +/* not.b${G} ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 } + }, +/* not.b${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 } + }, +/* not.b${G} ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 } + }, +/* not.w${G} $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 } + }, +/* not.w${G} $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 } + }, +/* not.w${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 } + }, +/* not.w${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 } + }, +/* not.w${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 } + }, +/* not.w${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 } + }, +/* not.w${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 } + }, +/* not.w${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 } + }, +/* not.w${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 } + }, +/* not.b${G} $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 } + }, +/* not.b${G} $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 } + }, +/* not.b${G} [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 } + }, +/* not.b${G} ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 } + }, +/* not.b${G} ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 } + }, +/* not.b${G} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 } + }, +/* not.b${G} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 } + }, +/* not.b${G} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 } + }, +/* not.b${G} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 } + }, +/* neg.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92f } + }, +/* neg.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1af } + }, +/* neg.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12f } + }, +/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32f00 } + }, +/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52f0000 } + }, +/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72f0000 } + }, +/* neg.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3af00 } + }, +/* neg.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5af0000 } + }, +/* neg.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ef00 } + }, +/* neg.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ef0000 } + }, +/* neg.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ef0000 } + }, +/* neg.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7af0000 } + }, +/* neg.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82f } + }, +/* neg.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0af } + }, +/* neg.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02f } + }, +/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22f00 } + }, +/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42f0000 } + }, +/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62f0000 } + }, +/* neg.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2af00 } + }, +/* neg.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4af0000 } + }, +/* neg.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ef00 } + }, +/* neg.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ef0000 } + }, +/* neg.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ef0000 } + }, +/* neg.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6af0000 } + }, +/* neg.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7550 } + }, +/* neg.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7554 } + }, +/* neg.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7556 } + }, +/* neg.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x755800 } + }, +/* neg.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x755c0000 } + }, +/* neg.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x755a00 } + }, +/* neg.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x755e0000 } + }, +/* neg.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x755b00 } + }, +/* neg.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x755f0000 } + }, +/* neg.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7450 } + }, +/* neg.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7454 } + }, +/* neg.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7456 } + }, +/* neg.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x745800 } + }, +/* neg.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x745c0000 } + }, +/* neg.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x745a00 } + }, +/* neg.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x745e0000 } + }, +/* neg.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x745b00 } + }, +/* neg.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x745f0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc904 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8924 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8904 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc184 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a4 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8184 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc104 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8124 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8104 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5040000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85240000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85040000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7040000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87240000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87040000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5840000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85840000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c40000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c40000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7840000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc804 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8824 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8804 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc084 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a4 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8084 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc004 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8024 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8004 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4040000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84240000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84040000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6040000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86240000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86040000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4840000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84840000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c40000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c40000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6840000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x718000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x71a000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x71b000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x718400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x71a400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x71b400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x718600 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x71a600 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x71b600 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x71880000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x71a80000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x71b80000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x718c0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x71ac0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x71bc0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x718a0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71aa0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71ba0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x718e0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71ae0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71be0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x718b0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71ab0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71bb0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x718f0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x71af0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x71bf0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x71c00000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x71e00000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x71f00000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x71c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x71e40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x71f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x71c60000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x71e60000 } + }, +/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x71f60000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x71c80000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x71e80000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x71f80000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x71cc0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x71ec0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x71fc0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ca0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ea0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x71fa0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ce0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ee0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x71fe0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x71cb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x71eb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x71fb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x71cf0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x71ef0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x71ff0000 } + }, +/* mulu.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7100 } + }, +/* mulu.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7140 } + }, +/* mulu.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7160 } + }, +/* mulu.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7104 } + }, +/* mulu.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7144 } + }, +/* mulu.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7164 } + }, +/* mulu.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7106 } + }, +/* mulu.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7146 } + }, +/* mulu.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7166 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x710800 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x714800 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x716800 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x710c0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x714c0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x716c0000 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x710a00 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x714a00 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x716a00 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x710e0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x714e0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x716e0000 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x710b00 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x714b00 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x716b00 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x710f0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x714f0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x716f0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x708000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x70a000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x70b000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x708400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x70a400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x70b400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x708600 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x70a600 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x70b600 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x70880000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x70a80000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x70b80000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x708c0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x70ac0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x70bc0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x708a0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70aa0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70ba0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x708e0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70ae0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70be0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x708b0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70ab0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70bb0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x708f0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x70af0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x70bf0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x70c00000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x70e00000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x70f00000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x70c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x70e40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x70f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x70c60000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x70e60000 } + }, +/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x70f60000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x70c80000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x70e80000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x70f80000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x70cc0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x70ec0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x70fc0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ca0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ea0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x70fa0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ce0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ee0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x70fe0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x70cb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x70eb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x70fb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x70cf0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x70ef0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x70ff0000 } + }, +/* mulu.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7000 } + }, +/* mulu.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7040 } + }, +/* mulu.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7060 } + }, +/* mulu.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7004 } + }, +/* mulu.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7044 } + }, +/* mulu.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7064 } + }, +/* mulu.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7006 } + }, +/* mulu.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7046 } + }, +/* mulu.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7066 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x700800 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x704800 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x706800 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x700c0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x704c0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x706c0000 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x700a00 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x704a00 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x706a00 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x700e0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x704e0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x706e0000 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x700b00 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x704b00 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x706b00 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x700f0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x704f0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x706f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x890f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x818f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x810f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x830f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cf0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x850f0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858f0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cf0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87cf0000 } + }, +/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x870f0000 } + }, +/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x878f0000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x880f00 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x808f00 } + }, +/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x800f00 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x820f0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828f0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cf0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x840f0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848f0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cf0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86cf0000 } + }, +/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x860f0000 } + }, +/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x868f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d400000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d440000 } + }, +/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d460000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d480000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d4a0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d4b0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d4c0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d4e0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d4f0000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c4000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c4400 } + }, +/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c4600 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c480000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c4a0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c4b0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c4c0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c4e0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c4f0000 } + }, +/* mulex $R3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R3), 0 } }, + & ifmt_mulex_dst32_R3_direct_Unprefixed_HI, { 0xc97e } + }, +/* mulex $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1be } + }, +/* mulex [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc13e } + }, +/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33e00 } + }, +/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc53e0000 } + }, +/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc73e0000 } + }, +/* mulex ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3be00 } + }, +/* mulex ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5be0000 } + }, +/* mulex ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3fe00 } + }, +/* mulex ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5fe0000 } + }, +/* mulex ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7fe0000 } + }, +/* mulex ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7be0000 } + }, +/* mulu.l $Dst32RnPrefixedSI,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1890f } + }, +/* mulu.l $Dst32AnPrefixedSI,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1818f } + }, +/* mulu.l [$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1810f } + }, +/* mulu.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1830f00 } + }, +/* mulu.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1850f00 } + }, +/* mulu.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1870f00 } + }, +/* mulu.l ${Dsp-24-u8}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1838f00 } + }, +/* mulu.l ${Dsp-24-u16}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1858f00 } + }, +/* mulu.l ${Dsp-24-s8}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183cf00 } + }, +/* mulu.l ${Dsp-24-s16}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185cf00 } + }, +/* mulu.l ${Dsp-24-u16},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187cf00 } + }, +/* mulu.l ${Dsp-24-u24},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1878f00 } + }, +/* mul.l $Dst32RnPrefixedSI,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1891f } + }, +/* mul.l $Dst32AnPrefixedSI,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1819f } + }, +/* mul.l [$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1811f } + }, +/* mul.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1831f00 } + }, +/* mul.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1851f00 } + }, +/* mul.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1871f00 } + }, +/* mul.l ${Dsp-24-u8}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1839f00 } + }, +/* mul.l ${Dsp-24-u16}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1859f00 } + }, +/* mul.l ${Dsp-24-s8}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x183df00 } + }, +/* mul.l ${Dsp-24-s16}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x185df00 } + }, +/* mul.l ${Dsp-24-u16},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x187df00 } + }, +/* mul.l ${Dsp-24-u24},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1879f00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992c00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ac00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bc00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912c00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bc0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ac0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892c } + }, +/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ac } + }, +/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812c } + }, +/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30c00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832c00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830c00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852c0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872c0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38c00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ac00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838c00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ac0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cc00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ec00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cc00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cc0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ec0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cc0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cc0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ec0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cc0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ac0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982c00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ac00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bc00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902c00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bc0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ac0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882c } + }, +/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ac } + }, +/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802c } + }, +/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20c00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822c00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820c00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842c0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862c0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28c00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ac00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828c00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ac0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cc00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ec00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cc00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cc0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ec0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cc0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cc0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ec0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cc0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ac0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x798000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x79a000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x79b000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x798400 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x79a400 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x79b400 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x798600 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x79a600 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x79b600 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x79880000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x79a80000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x79b80000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x798c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x79ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x79bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x798a0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79aa0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79ba0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x798e0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79ae0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79be0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x798b0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79ab0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79bb0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x798f0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x79af0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x79bf0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x79c00000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x79e00000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x79f00000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x79c40000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x79e40000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x79f40000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x79c60000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x79e60000 } + }, +/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x79f60000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x79c80000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x79e80000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x79f80000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x79cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x79ec0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x79fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ca0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ea0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x79fa0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ce0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ee0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x79fe0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x79cb0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x79eb0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x79fb0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x79cf0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x79ef0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x79ff0000 } + }, +/* mul.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7900 } + }, +/* mul.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7940 } + }, +/* mul.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7960 } + }, +/* mul.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7904 } + }, +/* mul.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7944 } + }, +/* mul.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7964 } + }, +/* mul.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7906 } + }, +/* mul.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7946 } + }, +/* mul.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7966 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x790800 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x794800 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x796800 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x790c0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x794c0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x796c0000 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x790a00 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x794a00 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x796a00 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x790e0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x794e0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x796e0000 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x790b00 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x794b00 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x796b00 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x790f0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x794f0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x796f0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x788000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x78a000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x78b000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x788400 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x78a400 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x78b400 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x788600 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x78a600 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x78b600 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x78880000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x78a80000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x78b80000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x788c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x78ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x78bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x788a0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78aa0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78ba0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x788e0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78ae0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78be0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x788b0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78ab0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78bb0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x788f0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x78af0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x78bf0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x78c00000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x78e00000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x78f00000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x78c40000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x78e40000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x78f40000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x78c60000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x78e60000 } + }, +/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x78f60000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x78c80000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x78e80000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x78f80000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x78cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x78ec0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x78fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ca0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ea0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x78fa0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ce0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ee0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x78fe0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x78cb0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x78eb0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x78fb0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x78cf0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x78ef0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x78ff0000 } + }, +/* mul.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7800 } + }, +/* mul.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7840 } + }, +/* mul.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7860 } + }, +/* mul.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7804 } + }, +/* mul.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7844 } + }, +/* mul.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7864 } + }, +/* mul.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7806 } + }, +/* mul.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7846 } + }, +/* mul.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7866 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x780800 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x784800 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x786800 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x780c0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x784c0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x786c0000 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x780a00 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x784a00 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x786a00 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x780e0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x784e0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x786e0000 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x780b00 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x784b00 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x786b00 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x780f0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x784f0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x786f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x891f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x819f0000 } + }, +/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x811f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x831f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83df0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x851f0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859f0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85df0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87df0000 } + }, +/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x871f0000 } + }, +/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x879f0000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x881f00 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x809f00 } + }, +/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x801f00 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x821f0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829f0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82df0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x841f0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849f0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84df0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86df0000 } + }, +/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x861f0000 } + }, +/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x869f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d500000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d540000 } + }, +/* mul.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d560000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d580000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d5a0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d5b0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d5c0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d5e0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d5f0000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c5000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c5400 } + }, +/* mul.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c5600 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c580000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c5a0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c5b0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c5c0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c5e0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c5f0000 } + }, +/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb81100 } + }, +/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb09100 } + }, +/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb01100 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2110000 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2910000 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2d10000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4110000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4910000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4d10000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6d10000 } + }, +/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6110000 } + }, +/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6910000 } + }, +/* movhh $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a83e } + }, +/* movhh $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0be } + }, +/* movhh [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a03e } + }, +/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a23e00 } + }, +/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a43e00 } + }, +/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a63e00 } + }, +/* movhh ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2be00 } + }, +/* movhh ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4be00 } + }, +/* movhh ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2fe00 } + }, +/* movhh ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4fe00 } + }, +/* movhh ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6fe00 } + }, +/* movhh ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6be00 } + }, +/* movhl $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a82e } + }, +/* movhl $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0ae } + }, +/* movhl [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a02e } + }, +/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a22e00 } + }, +/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a42e00 } + }, +/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a62e00 } + }, +/* movhl ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2ae00 } + }, +/* movhl ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4ae00 } + }, +/* movhl ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ee00 } + }, +/* movhl ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ee00 } + }, +/* movhl ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ee00 } + }, +/* movhl ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6ae00 } + }, +/* movlh $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a81e } + }, +/* movlh $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a09e } + }, +/* movlh [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a01e } + }, +/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a21e00 } + }, +/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a41e00 } + }, +/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a61e00 } + }, +/* movlh ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a29e00 } + }, +/* movlh ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a49e00 } + }, +/* movlh ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2de00 } + }, +/* movlh ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4de00 } + }, +/* movlh ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6de00 } + }, +/* movlh ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a69e00 } + }, +/* movll $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a80e } + }, +/* movll $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a08e } + }, +/* movll [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a00e } + }, +/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a20e00 } + }, +/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a40e00 } + }, +/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a60e00 } + }, +/* movll ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a28e00 } + }, +/* movll ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a48e00 } + }, +/* movll ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ce00 } + }, +/* movll ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ce00 } + }, +/* movll ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ce00 } + }, +/* movll ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a68e00 } + }, +/* movhh r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b83e } + }, +/* movhh r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0be } + }, +/* movhh r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b03e } + }, +/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b23e00 } + }, +/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b43e00 } + }, +/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b63e00 } + }, +/* movhh r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2be00 } + }, +/* movhh r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4be00 } + }, +/* movhh r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2fe00 } + }, +/* movhh r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4fe00 } + }, +/* movhh r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6fe00 } + }, +/* movhh r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6be00 } + }, +/* movhl r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b82e } + }, +/* movhl r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0ae } + }, +/* movhl r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b02e } + }, +/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b22e00 } + }, +/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b42e00 } + }, +/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b62e00 } + }, +/* movhl r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2ae00 } + }, +/* movhl r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4ae00 } + }, +/* movhl r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ee00 } + }, +/* movhl r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ee00 } + }, +/* movhl r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ee00 } + }, +/* movhl r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6ae00 } + }, +/* movlh r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b81e } + }, +/* movlh r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b09e } + }, +/* movlh r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b01e } + }, +/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b21e00 } + }, +/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b41e00 } + }, +/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b61e00 } + }, +/* movlh r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b29e00 } + }, +/* movlh r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b49e00 } + }, +/* movlh r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2de00 } + }, +/* movlh r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4de00 } + }, +/* movlh r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6de00 } + }, +/* movlh r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b69e00 } + }, +/* movll r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b80e } + }, +/* movll r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b08e } + }, +/* movll r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b00e } + }, +/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b20e00 } + }, +/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b40e00 } + }, +/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b60e00 } + }, +/* movll r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b28e00 } + }, +/* movll r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b48e00 } + }, +/* movll r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ce00 } + }, +/* movll r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ce00 } + }, +/* movll r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ce00 } + }, +/* movll r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b68e00 } + }, +/* movhh $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c30 } + }, +/* movhh $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c34 } + }, +/* movhh [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c36 } + }, +/* movhh ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c3800 } + }, +/* movhh ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c3c0000 } + }, +/* movhh ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c3a00 } + }, +/* movhh ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c3e0000 } + }, +/* movhh ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c3b00 } + }, +/* movhh ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c3f0000 } + }, +/* movhl $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c10 } + }, +/* movhl $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c14 } + }, +/* movhl [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c16 } + }, +/* movhl ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c1800 } + }, +/* movhl ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c1c0000 } + }, +/* movhl ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c1a00 } + }, +/* movhl ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c1e0000 } + }, +/* movhl ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c1b00 } + }, +/* movhl ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c1f0000 } + }, +/* movlh $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c20 } + }, +/* movlh $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c24 } + }, +/* movlh [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c26 } + }, +/* movlh ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c2800 } + }, +/* movlh ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c2c0000 } + }, +/* movlh ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c2a00 } + }, +/* movlh ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c2e0000 } + }, +/* movlh ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c2b00 } + }, +/* movlh ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c2f0000 } + }, +/* movll $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c00 } + }, +/* movll $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c04 } + }, +/* movll [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c06 } + }, +/* movll ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c0800 } + }, +/* movll ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c0c0000 } + }, +/* movll ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c0a00 } + }, +/* movll ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c0e0000 } + }, +/* movll ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c0b00 } + }, +/* movll ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c0f0000 } + }, +/* movhh r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7cb0 } + }, +/* movhh r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7cb4 } + }, +/* movhh r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7cb6 } + }, +/* movhh r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7cb800 } + }, +/* movhh r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cbc0000 } + }, +/* movhh r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7cba00 } + }, +/* movhh r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cbe0000 } + }, +/* movhh r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cbb00 } + }, +/* movhh r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7cbf0000 } + }, +/* movhl r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c90 } + }, +/* movhl r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c94 } + }, +/* movhl r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c96 } + }, +/* movhl r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c9800 } + }, +/* movhl r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c9c0000 } + }, +/* movhl r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c9a00 } + }, +/* movhl r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c9e0000 } + }, +/* movhl r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c9b00 } + }, +/* movhl r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c9f0000 } + }, +/* movlh r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7ca0 } + }, +/* movlh r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7ca4 } + }, +/* movlh r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7ca6 } + }, +/* movlh r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7ca800 } + }, +/* movlh r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cac0000 } + }, +/* movlh r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7caa00 } + }, +/* movlh r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cae0000 } + }, +/* movlh r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cab00 } + }, +/* movlh r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7caf0000 } + }, +/* movll r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c80 } + }, +/* movll r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c84 } + }, +/* movll r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c86 } + }, +/* movll r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c8800 } + }, +/* movll r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c8c0000 } + }, +/* movll r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c8a00 } + }, +/* movll r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c8e0000 } + }, +/* movll r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c8b00 } + }, +/* movll r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c8f0000 } + }, +/* mova [$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11b } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31b00 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51b0000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71b0000 } + }, +/* mova ${Dsp-16-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39b00 } + }, +/* mova ${Dsp-16-u16}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59b0000 } + }, +/* mova ${Dsp-16-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3db00 } + }, +/* mova ${Dsp-16-s16}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5db0000 } + }, +/* mova ${Dsp-16-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7db0000 } + }, +/* mova ${Dsp-16-u24},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79b0000 } + }, +/* mova [$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11a } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31a00 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51a0000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71a0000 } + }, +/* mova ${Dsp-16-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39a00 } + }, +/* mova ${Dsp-16-u16}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59a0000 } + }, +/* mova ${Dsp-16-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3da00 } + }, +/* mova ${Dsp-16-s16}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5da0000 } + }, +/* mova ${Dsp-16-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7da0000 } + }, +/* mova ${Dsp-16-u24},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79a0000 } + }, +/* mova [$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd119 } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31900 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5190000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7190000 } + }, +/* mova ${Dsp-16-u8}[sb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39900 } + }, +/* mova ${Dsp-16-u16}[sb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5990000 } + }, +/* mova ${Dsp-16-s8}[fb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d900 } + }, +/* mova ${Dsp-16-s16}[fb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d90000 } + }, +/* mova ${Dsp-16-u16},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d90000 } + }, +/* mova ${Dsp-16-u24},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7990000 } + }, +/* mova [$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd118 } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31800 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5180000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7180000 } + }, +/* mova ${Dsp-16-u8}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39800 } + }, +/* mova ${Dsp-16-u16}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5980000 } + }, +/* mova ${Dsp-16-s8}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d800 } + }, +/* mova ${Dsp-16-s16}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d80000 } + }, +/* mova ${Dsp-16-u16},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d80000 } + }, +/* mova ${Dsp-16-u24},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7980000 } + }, +/* mova [$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb56 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb5800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb5c0000 } + }, +/* mova ${Dsp-16-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb5a00 } + }, +/* mova ${Dsp-16-u16}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb5e0000 } + }, +/* mova ${Dsp-16-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb5b00 } + }, +/* mova ${Dsp-16-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb5f0000 } + }, +/* mova [$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb46 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb4800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb4c0000 } + }, +/* mova ${Dsp-16-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb4a00 } + }, +/* mova ${Dsp-16-u16}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb4e0000 } + }, +/* mova ${Dsp-16-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb4b00 } + }, +/* mova ${Dsp-16-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb4f0000 } + }, +/* mova [$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb36 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb3800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb3c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb3a00 } + }, +/* mova ${Dsp-16-u16}[sb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb3e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb3b00 } + }, +/* mova ${Dsp-16-u16},r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb3f0000 } + }, +/* mova [$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb26 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb2800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb2c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb2a00 } + }, +/* mova ${Dsp-16-u16}[sb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb2e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb2b00 } + }, +/* mova ${Dsp-16-u16},r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb2f0000 } + }, +/* mova [$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb16 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb1800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb1c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb1a00 } + }, +/* mova ${Dsp-16-u16}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb1e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb1b00 } + }, +/* mova ${Dsp-16-u16},r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb1f0000 } + }, +/* mova [$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb06 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb0800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb0c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb0a00 } + }, +/* mova ${Dsp-16-u16}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb0e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb0b00 } + }, +/* mova ${Dsp-16-u16},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 } + }, +/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 } + }, +/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 } + }, +/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 } + }, +/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 } + }, +/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 } + }, +/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 } + }, +/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 } + }, +/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANHI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 } + }, +/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 } + }, +/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16RNQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 } + }, +/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DST16ANQI), ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 } + }, +/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_S8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 } + }, +/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 } + }, +/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 } + }, +/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 } + }, +/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_40_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 } + }, +/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 } + }, +/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 } + }, +/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 } + }, +/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_24_S8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 } + }, +/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_32_S8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 } + }, +/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 } + }, +/* mov.l${S} ${Dsp-8-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6900 } + }, +/* mov.l${S} ${Dsp-8-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7900 } + }, +/* mov.l${S} ${Dsp-8-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6800 } + }, +/* mov.l${S} ${Dsp-8-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7800 } + }, +/* mov.l${S} ${Dsp-8-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x590000 } + }, +/* mov.l${S} ${Dsp-8-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x580000 } + }, +/* mov.w${S} r0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2100 } + }, +/* mov.w${S} r0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3100 } + }, +/* mov.b${S} r0l,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2000 } + }, +/* mov.b${S} r0l,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3000 } + }, +/* mov.w${S} r0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x110000 } + }, +/* mov.b${S} r0l,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x100000 } + }, +/* mov.w${S} ${Dsp-8-u8}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6f00 } + }, +/* mov.w${S} ${Dsp-8-s8}[fb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7f00 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6e00 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7e00 } + }, +/* mov.w${S} ${Dsp-8-u16},r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x5f0000 } + }, +/* mov.b${S} ${Dsp-8-u16},r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 } + }, +/* mov.w${S} r0,r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 0 } }, + & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x4f } + }, +/* mov.b${S} r0l,r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x4e } + }, +/* mov.w${S} ${Dsp-8-u8}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2900 } + }, +/* mov.w${S} ${Dsp-8-s8}[fb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3900 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2800 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3800 } + }, +/* mov.w${S} ${Dsp-8-u16},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x190000 } + }, +/* mov.b${S} ${Dsp-8-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x180000 } + }, +/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x8 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x900 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0xa00 } + }, +/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0xb0000 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x100 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x200 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U16), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9330000 } + }, +/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1330000 } + }, +/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9030000 } + }, +/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1830000 } + }, +/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1030000 } + }, +/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc903 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8923 } + }, +/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8903 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc183 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a3 } + }, +/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8183 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc103 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8123 } + }, +/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8103 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5030000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85230000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85030000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7030000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87230000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87030000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5830000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85830000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c30000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c30000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7830000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87830000 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI, { 0x3100 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI, { 0x3200 } + }, +/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI, { 0x330000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992b00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ab00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bb00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912b00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ab0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892b } + }, +/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ab } + }, +/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812b } + }, +/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30b00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832b00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830b00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852b0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872b0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38b00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ab00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838b00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ab0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cb00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83eb00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cb00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cb0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85eb0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cb0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cb0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87eb0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cb0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ab0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982b00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ab00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bb00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902b00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ab0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882b } + }, +/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ab } + }, +/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802b } + }, +/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20b00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822b00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820b00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842b0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862b0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28b00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ab00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828b00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ab0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cb00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82eb00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cb00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cb0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84eb0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cb0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cb0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86eb0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cb0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ab0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x738000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x73a000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x73b000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x738400 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x73a400 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x73b400 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x738600 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x73a600 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x73b600 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x73880000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x73a80000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x73b80000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x738c0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x73ac0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x73bc0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x738a0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73aa0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73ba0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x738e0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73ae0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73be0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x738b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x738f0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x73af0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x73bf0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x73c00000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x73e00000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x73f00000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x73c40000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x73e40000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x73f40000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x73c60000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x73e60000 } + }, +/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x73f60000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x73c80000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x73e80000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x73f80000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x73cc0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x73ec0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x73fc0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ca0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ea0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x73fa0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ce0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ee0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x73fe0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x73cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x73eb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x73fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x73cf0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x73ef0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x73ff0000 } + }, +/* mov.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7300 } + }, +/* mov.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7340 } + }, +/* mov.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7360 } + }, +/* mov.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7304 } + }, +/* mov.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7344 } + }, +/* mov.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7364 } + }, +/* mov.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7306 } + }, +/* mov.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7346 } + }, +/* mov.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7366 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x730800 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x734800 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x736800 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x730c0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x734c0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x736c0000 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x730a00 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x734a00 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x736a00 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x730e0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x734e0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x736e0000 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x730b00 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x734b00 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x736b00 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x730f0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x734f0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x736f0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x728000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x72a000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x72b000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x728400 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x72a400 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x72b400 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x728600 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x72a600 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x72b600 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x72880000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x72a80000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x72b80000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x728c0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x72ac0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x72bc0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x728a0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72aa0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72ba0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x728e0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72ae0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72be0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x728b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x728f0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x72af0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x72bf0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x72c00000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x72e00000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x72f00000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x72c40000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x72e40000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x72f40000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x72c60000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x72e60000 } + }, +/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x72f60000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x72c80000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x72e80000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x72f80000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x72cc0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x72ec0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x72fc0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ca0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ea0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x72fa0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ce0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ee0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x72fe0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x72cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x72eb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x72fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x72cf0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x72ef0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x72ff0000 } + }, +/* mov.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7200 } + }, +/* mov.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7240 } + }, +/* mov.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7260 } + }, +/* mov.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7204 } + }, +/* mov.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7244 } + }, +/* mov.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7264 } + }, +/* mov.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7206 } + }, +/* mov.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7246 } + }, +/* mov.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7266 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x720800 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x724800 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x726800 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x720c0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x724c0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x726c0000 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x720a00 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x724a00 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x726a00 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x720e0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x724e0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x726e0000 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x720b00 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x724b00 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x726b00 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x720f0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x724f0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x726f0000 } + }, +/* mov.w${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2300 } + }, +/* mov.w${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3300 } + }, +/* mov.w${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x130000 } + }, +/* mov.w${Z} #0,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_dst32_2_S_basic_r1_dst32_2_S_R0_direct_HI, { 0x3 } + }, +/* mov.b${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2200 } + }, +/* mov.b${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3200 } + }, +/* mov.b${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x120000 } + }, +/* mov.b${Z} #0,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x2 } + }, +/* mov.b${Z} #0,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xb4 } + }, +/* mov.b${Z} #0,r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xb3 } + }, +/* mov.b${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xb500 } + }, +/* mov.b${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xb600 } + }, +/* mov.b${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xb70000 } + }, +/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf920 } + }, +/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf1a0 } + }, +/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf120 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf32000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5200000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7200000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3a000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5a00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3e000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5e00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7e00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7a00000 } + }, +/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf820 } + }, +/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf0a0 } + }, +/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf020 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf22000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4200000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6200000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2a000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4a00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2e000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4e00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6e00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6a00000 } + }, +/* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd900 } + }, +/* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd904 } + }, +/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd906 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd90800 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd90c0000 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd90a00 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd90e0000 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd90b00 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd90f0000 } + }, +/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd800 } + }, +/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd804 } + }, +/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd806 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd80800 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd80c0000 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd80a00 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd80e0000 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd80b00 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 } + }, +/* mov.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 } + }, +/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 } + }, +/* mov.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 } + }, +/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 } + }, +/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb8310000 } + }, +/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb0b10000 } + }, +/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb0310000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2310000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2b10000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2f10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4310000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4b10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4f10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6f10000 } + }, +/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6310000 } + }, +/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6b10000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992f0000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91af0000 } + }, +/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912f0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932f0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93af0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ef0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952f0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95af0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ef0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ef0000 } + }, +/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972f0000 } + }, +/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97af0000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982f00 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90af00 } + }, +/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902f00 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922f0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92af0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ef0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942f0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94af0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ef0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ef0000 } + }, +/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962f0000 } + }, +/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96af0000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x75c00000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x75c40000 } + }, +/* mov.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x75c60000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x75c80000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x75ca0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x75cb0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x75cc0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x75ce0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x75cf0000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x74c000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x74c400 } + }, +/* mov.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x74c600 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x74c80000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x74ca0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x74cb0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x74cc0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x74ce0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x74cf0000 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93c00 } + }, +/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bc00 } + }, +/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13c00 } + }, +/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bc00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90c00 } + }, +/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18c00 } + }, +/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10c00 } + }, +/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ac00 } + }, +/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90c } + }, +/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892c } + }, +/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890c } + }, +/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18c } + }, +/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ac } + }, +/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818c } + }, +/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10c } + }, +/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812c } + }, +/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810c } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83c00 } + }, +/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bc00 } + }, +/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03c00 } + }, +/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bc00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80c00 } + }, +/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08c00 } + }, +/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00c00 } + }, +/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ac00 } + }, +/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80c } + }, +/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882c } + }, +/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880c } + }, +/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08c } + }, +/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ac } + }, +/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808c } + }, +/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00c } + }, +/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802c } + }, +/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800c } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868c00 } + }, +/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892f00 } + }, +/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181af00 } + }, +/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812f00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832f00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183af00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ef00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852f00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185af00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ef00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ef00 } + }, +/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872f00 } + }, +/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187af00 } + }, +/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882f00 } + }, +/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180af00 } + }, +/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802f00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822f00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182af00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ef00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842f00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184af00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ef00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ef00 } + }, +/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862f00 } + }, +/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186af00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93d00 } + }, +/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bd00 } + }, +/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13d00 } + }, +/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bd00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90d00 } + }, +/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18d00 } + }, +/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10d00 } + }, +/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ad00 } + }, +/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90d } + }, +/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892d } + }, +/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890d } + }, +/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18d } + }, +/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ad } + }, +/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818d } + }, +/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10d } + }, +/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812d } + }, +/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810d } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83d00 } + }, +/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bd00 } + }, +/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03d00 } + }, +/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bd00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80d00 } + }, +/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08d00 } + }, +/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00d00 } + }, +/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ad00 } + }, +/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80d } + }, +/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882d } + }, +/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880d } + }, +/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08d } + }, +/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ad } + }, +/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808d } + }, +/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00d } + }, +/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802d } + }, +/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800d } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868d00 } + }, +/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893f00 } + }, +/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181bf00 } + }, +/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813f00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833f00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183bf00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ff00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853f00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185bf00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ff00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ff00 } + }, +/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873f00 } + }, +/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187bf00 } + }, +/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883f00 } + }, +/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180bf00 } + }, +/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803f00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823f00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182bf00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ff00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843f00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184bf00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ff00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ff00 } + }, +/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863f00 } + }, +/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 } + }, +/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x752c0000 } + }, +/* ste.w ${Dsp-16-u16}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x752e0000 } + }, +/* ste.w ${Dsp-16-u16},[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x752f0000 } + }, +/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x751c0000 } + }, +/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x751e0000 } + }, +/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x751f0000 } + }, +/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x750c0000 } + }, +/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x750e0000 } + }, +/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x750f0000 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x752800 } + }, +/* ste.w ${Dsp-16-u8}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x752a00 } + }, +/* ste.w ${Dsp-16-s8}[fb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x752b00 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75180000 } + }, +/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x751a0000 } + }, +/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x751b0000 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75080000 } + }, +/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x750a0000 } + }, +/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x750b0000 } + }, +/* ste.w $Dst16RnHI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7520 } + }, +/* ste.w $Dst16AnHI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7524 } + }, +/* ste.w [$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7526 } + }, +/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75100000 } + }, +/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75140000 } + }, +/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75160000 } + }, +/* ste.w $Dst16RnHI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75000000 } + }, +/* ste.w $Dst16AnHI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75040000 } + }, +/* ste.w [$Dst16An],${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75060000 } + }, +/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x742c0000 } + }, +/* ste.b ${Dsp-16-u16}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x742e0000 } + }, +/* ste.b ${Dsp-16-u16},[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x742f0000 } + }, +/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x741c0000 } + }, +/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x741e0000 } + }, +/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x741f0000 } + }, +/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x740c0000 } + }, +/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x740e0000 } + }, +/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x740f0000 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x742800 } + }, +/* ste.b ${Dsp-16-u8}[sb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x742a00 } + }, +/* ste.b ${Dsp-16-s8}[fb],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x742b00 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74180000 } + }, +/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x741a0000 } + }, +/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x741b0000 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74080000 } + }, +/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x740a0000 } + }, +/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x740b0000 } + }, +/* ste.b $Dst16RnQI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7420 } + }, +/* ste.b $Dst16AnQI,[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7424 } + }, +/* ste.b [$Dst16An],[a1a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', '[', 'a', '1', 'a', '0', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7426 } + }, +/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74100000 } + }, +/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74140000 } + }, +/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), '[', 'a', '0', ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74160000 } + }, +/* ste.b $Dst16RnQI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74000000 } + }, +/* ste.b $Dst16AnQI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74040000 } + }, +/* ste.b [$Dst16An],${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74060000 } + }, +/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75ac0000 } + }, +/* lde.w [a1a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75ae0000 } + }, +/* lde.w [a1a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75af0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x759c0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x759e0000 } + }, +/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x759f0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_An_relative_HI, { 0x758c0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_SB_relative_HI, { 0x758e0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_w_16_16_u20a0_dst16_16_16_absolute_HI, { 0x758f0000 } + }, +/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75a800 } + }, +/* lde.w [a1a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75aa00 } + }, +/* lde.w [a1a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75ab00 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75980000 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x759a0000 } + }, +/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x759b0000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_An_relative_HI, { 0x75880000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_SB_relative_HI, { 0x758a0000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_w_16_8_u20a0_dst16_16_8_FB_relative_HI, { 0x758b0000 } + }, +/* lde.w [a1a0],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75a0 } + }, +/* lde.w [a1a0],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75a4 } + }, +/* lde.w [a1a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75a6 } + }, +/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75900000 } + }, +/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75940000 } + }, +/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75960000 } + }, +/* lde.w ${Dsp-16-u20},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_Rn_direct_HI, { 0x75800000 } + }, +/* lde.w ${Dsp-16-u20},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_direct_HI, { 0x75840000 } + }, +/* lde.w ${Dsp-16-u20},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_w_basic_u20a0_dst16_An_indirect_HI, { 0x75860000 } + }, +/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74ac0000 } + }, +/* lde.b [a1a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74ae0000 } + }, +/* lde.b [a1a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74af0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x749c0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x749e0000 } + }, +/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x749f0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_An_relative_QI, { 0x748c0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_SB_relative_QI, { 0x748e0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste_b_16_16_u20a0_dst16_16_16_absolute_QI, { 0x748f0000 } + }, +/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74a800 } + }, +/* lde.b [a1a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74aa00 } + }, +/* lde.b [a1a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74ab00 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74980000 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x749a0000 } + }, +/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), '[', 'a', '0', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x749b0000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_An_relative_QI, { 0x74880000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_SB_relative_QI, { 0x748a0000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste_b_16_8_u20a0_dst16_16_8_FB_relative_QI, { 0x748b0000 } + }, +/* lde.b [a1a0],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74a0 } + }, +/* lde.b [a1a0],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74a4 } + }, +/* lde.b [a1a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', 'a', '1', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74a6 } + }, +/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74900000 } + }, +/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74940000 } + }, +/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', 'a', '0', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74960000 } + }, +/* lde.b ${Dsp-16-u20},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_Rn_direct_QI, { 0x74800000 } + }, +/* lde.b ${Dsp-16-u20},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_direct_QI, { 0x74840000 } + }, +/* lde.b ${Dsp-16-u20},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste_b_basic_u20a0_dst16_An_indirect_QI, { 0x74860000 } + }, +/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d910 } + }, +/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d190 } + }, +/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d110 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d31000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d51000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d71000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d39000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d59000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d79000 } + }, +/* stc ${cr2-32},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd910 } + }, +/* stc ${cr2-32},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd190 } + }, +/* stc ${cr2-32},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd110 } + }, +/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd31000 } + }, +/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5100000 } + }, +/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7100000 } + }, +/* stc ${cr2-32},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd39000 } + }, +/* stc ${cr2-32},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5900000 } + }, +/* stc ${cr2-32},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3d000 } + }, +/* stc ${cr2-32},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5d00000 } + }, +/* stc ${cr2-32},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7d00000 } + }, +/* stc ${cr2-32},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7900000 } + }, +/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d918 } + }, +/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d198 } + }, +/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d118 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d31800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d51800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d71800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d39800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d59800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d79800 } + }, +/* stc pc,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7cc0 } + }, +/* stc pc,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7cc4 } + }, +/* stc pc,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7cc6 } + }, +/* stc pc,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7cc800 } + }, +/* stc pc,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7ccc0000 } + }, +/* stc pc,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7cca00 } + }, +/* stc pc,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7cce0000 } + }, +/* stc pc,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7ccb00 } + }, +/* stc pc,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7ccf0000 } + }, +/* stc ${cr16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DST16RNHI), 0 } }, + & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7b80 } + }, +/* stc ${cr16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DST16ANHI), 0 } }, + & ifmt_stc16_src_dst16_An_direct_HI, { 0x7b84 } + }, +/* stc ${cr16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7b86 } + }, +/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7b8800 } + }, +/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7b8c0000 } + }, +/* stc ${cr16},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7b8a00 } + }, +/* stc ${cr16},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7b8e0000 } + }, +/* stc ${cr16},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7b8b00 } + }, +/* stc ${cr16},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7b8f0000 } + }, +/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d900 } + }, +/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d180 } + }, +/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d100 } + }, +/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d30000 } + }, +/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d50000 } + }, +/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d70000 } + }, +/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d38000 } + }, +/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d58000 } + }, +/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3c000 } + }, +/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5c000 } + }, +/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7c000 } + }, +/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d78000 } + }, +/* ldc $Dst32RnUnprefixedSI,${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd900 } + }, +/* ldc $Dst32AnUnprefixedSI,${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd180 } + }, +/* ldc [$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd100 } + }, +/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd30000 } + }, +/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5000000 } + }, +/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7000000 } + }, +/* ldc ${Dsp-16-u8}[sb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd38000 } + }, +/* ldc ${Dsp-16-u16}[sb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5800000 } + }, +/* ldc ${Dsp-16-s8}[fb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3c000 } + }, +/* ldc ${Dsp-16-s16}[fb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5c00000 } + }, +/* ldc ${Dsp-16-u16},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7c00000 } + }, +/* ldc ${Dsp-16-u24},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7800000 } + }, +/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d908 } + }, +/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d188 } + }, +/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d108 } + }, +/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d30800 } + }, +/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d50800 } + }, +/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d70800 } + }, +/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d38800 } + }, +/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d58800 } + }, +/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3c800 } + }, +/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5c800 } + }, +/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7c800 } + }, +/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d78800 } + }, +/* ldc $Dst16RnHI,${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7a80 } + }, +/* ldc $Dst16AnHI,${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_An_direct_HI, { 0x7a84 } + }, +/* ldc [$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7a86 } + }, +/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7a8800 } + }, +/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7a8c0000 } + }, +/* ldc ${Dsp-16-u8}[sb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7a8a00 } + }, +/* ldc ${Dsp-16-u16}[sb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7a8e0000 } + }, +/* ldc ${Dsp-16-s8}[fb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7a8b00 } + }, +/* ldc ${Dsp-16-u16},${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 } + }, +/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 } + }, +/* jsri.a ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 } + }, +/* jsri.a $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 } + }, +/* jsri.a $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 } + }, +/* jsri.a [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 } + }, +/* jsri.a $Dst16RnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 } + }, +/* jsri.a $Dst16AnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 } + }, +/* jsri.a [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 } + }, +/* jsri.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94810000 } + }, +/* jsri.a ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94c10000 } + }, +/* jsri.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 } + }, +/* jsri.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 } + }, +/* jsri.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 } + }, +/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x920100 } + }, +/* jsri.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x928100 } + }, +/* jsri.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92c100 } + }, +/* jsri.a ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d1800 } + }, +/* jsri.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d1a00 } + }, +/* jsri.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 } + }, +/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 } + }, +/* jsri.a ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 } + }, +/* jsri.a ${Dsp-16-u20}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI, { 0x7d1c0000 } + }, +/* jsri.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f } + }, +/* jsri.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f } + }, +/* jsri.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f } + }, +/* jsri.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 } + }, +/* jsri.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 } + }, +/* jsri.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 } + }, +/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 } + }, +/* jsri.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 } + }, +/* jsri.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc59f0000 } + }, +/* jsri.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5df0000 } + }, +/* jsri.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 } + }, +/* jsri.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d3e0000 } + }, +/* jsri.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 } + }, +/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 } + }, +/* jsri.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 } + }, +/* jsri.w ${Dsp-16-u20}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI, { 0x7d3c0000 } + }, +/* jmpi.a $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x8801 } + }, +/* jmpi.a $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x8081 } + }, +/* jmpi.a [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x8001 } + }, +/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x820100 } + }, +/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x84010000 } + }, +/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x86010000 } + }, +/* jmpi.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828100 } + }, +/* jmpi.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84810000 } + }, +/* jmpi.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c100 } + }, +/* jmpi.a ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c10000 } + }, +/* jmpi.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x86c10000 } + }, +/* jmpi.a ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x86810000 } + }, +/* jmpi.a $Dst16RnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d00 } + }, +/* jmpi.a $Dst16AnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d04 } + }, +/* jmpi.a [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d06 } + }, +/* jmpi.a ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d0800 } + }, +/* jmpi.a ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI, { 0x7d0c0000 } + }, +/* jmpi.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d0a00 } + }, +/* jmpi.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 } + }, +/* jmpi.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d0b00 } + }, +/* jmpi.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 } + }, +/* jmpi.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90f } + }, +/* jmpi.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18f } + }, +/* jmpi.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10f } + }, +/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30f00 } + }, +/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50f0000 } + }, +/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70f0000 } + }, +/* jmpi.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38f00 } + }, +/* jmpi.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58f0000 } + }, +/* jmpi.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cf00 } + }, +/* jmpi.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cf0000 } + }, +/* jmpi.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cf0000 } + }, +/* jmpi.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78f0000 } + }, +/* jmpi.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d20 } + }, +/* jmpi.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d24 } + }, +/* jmpi.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d26 } + }, +/* jmpi.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d2800 } + }, +/* jmpi.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d2c0000 } + }, +/* jmpi.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d2a00 } + }, +/* jmpi.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d2e0000 } + }, +/* jmpi.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d2b00 } + }, +/* jmpi.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d2f0000 } + }, +/* indexws.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 } + }, +/* indexws.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 } + }, +/* indexws.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 } + }, +/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 } + }, +/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 } + }, +/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 } + }, +/* indexws.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 } + }, +/* indexws.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 } + }, +/* indexws.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 } + }, +/* indexws.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 } + }, +/* indexws.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 } + }, +/* indexws.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 } + }, +/* indexws.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc823 } + }, +/* indexws.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0a3 } + }, +/* indexws.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc023 } + }, +/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22300 } + }, +/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4230000 } + }, +/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6230000 } + }, +/* indexws.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2a300 } + }, +/* indexws.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4a30000 } + }, +/* indexws.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2e300 } + }, +/* indexws.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4e30000 } + }, +/* indexws.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6e30000 } + }, +/* indexws.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6a30000 } + }, +/* indexwd.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 } + }, +/* indexwd.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 } + }, +/* indexwd.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 } + }, +/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 } + }, +/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 } + }, +/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 } + }, +/* indexwd.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 } + }, +/* indexwd.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 } + }, +/* indexwd.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 } + }, +/* indexwd.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 } + }, +/* indexwd.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 } + }, +/* indexwd.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 } + }, +/* indexwd.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa823 } + }, +/* indexwd.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0a3 } + }, +/* indexwd.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa023 } + }, +/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22300 } + }, +/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4230000 } + }, +/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6230000 } + }, +/* indexwd.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2a300 } + }, +/* indexwd.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4a30000 } + }, +/* indexwd.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2e300 } + }, +/* indexwd.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4e30000 } + }, +/* indexwd.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6e30000 } + }, +/* indexwd.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6a30000 } + }, +/* indexw.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 } + }, +/* indexw.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 } + }, +/* indexw.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 } + }, +/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 } + }, +/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 } + }, +/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 } + }, +/* indexw.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 } + }, +/* indexw.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 } + }, +/* indexw.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 } + }, +/* indexw.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 } + }, +/* indexw.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 } + }, +/* indexw.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 } + }, +/* indexw.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8823 } + }, +/* indexw.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x80a3 } + }, +/* indexw.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8023 } + }, +/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x822300 } + }, +/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84230000 } + }, +/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86230000 } + }, +/* indexw.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a300 } + }, +/* indexw.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a30000 } + }, +/* indexw.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e300 } + }, +/* indexw.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e30000 } + }, +/* indexw.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86e30000 } + }, +/* indexw.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86a30000 } + }, +/* indexls.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 } + }, +/* indexls.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 } + }, +/* indexls.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 } + }, +/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 } + }, +/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 } + }, +/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 } + }, +/* indexls.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 } + }, +/* indexls.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 } + }, +/* indexls.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 } + }, +/* indexls.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 } + }, +/* indexls.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 } + }, +/* indexls.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 } + }, +/* indexls.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9803 } + }, +/* indexls.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x9083 } + }, +/* indexls.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9003 } + }, +/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x920300 } + }, +/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94030000 } + }, +/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96030000 } + }, +/* indexls.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928300 } + }, +/* indexls.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94830000 } + }, +/* indexls.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92c300 } + }, +/* indexls.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94c30000 } + }, +/* indexls.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96c30000 } + }, +/* indexls.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96830000 } + }, +/* indexld.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 } + }, +/* indexld.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 } + }, +/* indexld.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 } + }, +/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 } + }, +/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 } + }, +/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 } + }, +/* indexld.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 } + }, +/* indexld.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 } + }, +/* indexld.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 } + }, +/* indexld.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 } + }, +/* indexld.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 } + }, +/* indexld.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 } + }, +/* indexld.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb823 } + }, +/* indexld.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0a3 } + }, +/* indexld.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb023 } + }, +/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22300 } + }, +/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb4230000 } + }, +/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb6230000 } + }, +/* indexld.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2a300 } + }, +/* indexld.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4a30000 } + }, +/* indexld.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2e300 } + }, +/* indexld.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4e30000 } + }, +/* indexld.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6e30000 } + }, +/* indexld.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6a30000 } + }, +/* indexl.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 } + }, +/* indexl.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 } + }, +/* indexl.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 } + }, +/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 } + }, +/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 } + }, +/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 } + }, +/* indexl.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 } + }, +/* indexl.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 } + }, +/* indexl.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 } + }, +/* indexl.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 } + }, +/* indexl.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 } + }, +/* indexl.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 } + }, +/* indexl.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9823 } + }, +/* indexl.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x90a3 } + }, +/* indexl.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9023 } + }, +/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x922300 } + }, +/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94230000 } + }, +/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96230000 } + }, +/* indexl.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92a300 } + }, +/* indexl.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94a30000 } + }, +/* indexl.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92e300 } + }, +/* indexl.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94e30000 } + }, +/* indexl.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96e30000 } + }, +/* indexl.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96a30000 } + }, +/* indexbs.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 } + }, +/* indexbs.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 } + }, +/* indexbs.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 } + }, +/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 } + }, +/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 } + }, +/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 } + }, +/* indexbs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 } + }, +/* indexbs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 } + }, +/* indexbs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 } + }, +/* indexbs.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 } + }, +/* indexbs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 } + }, +/* indexbs.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 } + }, +/* indexbs.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc803 } + }, +/* indexbs.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc083 } + }, +/* indexbs.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc003 } + }, +/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20300 } + }, +/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4030000 } + }, +/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6030000 } + }, +/* indexbs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28300 } + }, +/* indexbs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4830000 } + }, +/* indexbs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c300 } + }, +/* indexbs.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c30000 } + }, +/* indexbs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c30000 } + }, +/* indexbs.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6830000 } + }, +/* indexbd.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 } + }, +/* indexbd.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 } + }, +/* indexbd.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 } + }, +/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 } + }, +/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 } + }, +/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 } + }, +/* indexbd.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 } + }, +/* indexbd.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 } + }, +/* indexbd.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 } + }, +/* indexbd.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 } + }, +/* indexbd.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 } + }, +/* indexbd.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 } + }, +/* indexbd.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa803 } + }, +/* indexbd.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa083 } + }, +/* indexbd.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa003 } + }, +/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20300 } + }, +/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4030000 } + }, +/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6030000 } + }, +/* indexbd.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28300 } + }, +/* indexbd.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4830000 } + }, +/* indexbd.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2c300 } + }, +/* indexbd.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4c30000 } + }, +/* indexbd.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6c30000 } + }, +/* indexbd.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6830000 } + }, +/* indexb.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 } + }, +/* indexb.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 } + }, +/* indexb.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 } + }, +/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 } + }, +/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 } + }, +/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 } + }, +/* indexb.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 } + }, +/* indexb.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 } + }, +/* indexb.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 } + }, +/* indexb.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 } + }, +/* indexb.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 } + }, +/* indexb.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 } + }, +/* indexb.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8803 } + }, +/* indexb.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x8083 } + }, +/* indexb.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8003 } + }, +/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820300 } + }, +/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84030000 } + }, +/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86030000 } + }, +/* indexb.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828300 } + }, +/* indexb.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84830000 } + }, +/* indexb.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c300 } + }, +/* indexb.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c30000 } + }, +/* indexb.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86c30000 } + }, +/* indexb.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86830000 } + }, +/* inc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa90e } + }, +/* inc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18e } + }, +/* inc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa10e } + }, +/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30e00 } + }, +/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50e0000 } + }, +/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70e0000 } + }, +/* inc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38e00 } + }, +/* inc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58e0000 } + }, +/* inc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ce00 } + }, +/* inc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ce0000 } + }, +/* inc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ce0000 } + }, +/* inc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa78e0000 } + }, +/* inc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa80e } + }, +/* inc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa08e } + }, +/* inc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa00e } + }, +/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20e00 } + }, +/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40e0000 } + }, +/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60e0000 } + }, +/* inc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28e00 } + }, +/* inc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48e0000 } + }, +/* inc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ce00 } + }, +/* inc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ce0000 } + }, +/* inc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ce0000 } + }, +/* inc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa68e0000 } + }, +/* inc.b r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xa4 } + }, +/* inc.b r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xa3 } + }, +/* inc.b ${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xa500 } + }, +/* inc.b ${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xa600 } + }, +/* inc.b ${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U16), 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xa70000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9300000 } + }, +/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1300000 } + }, +/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9000000 } + }, +/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1800000 } + }, +/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1000000 } + }, +/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc900 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8920 } + }, +/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8900 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc180 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a0 } + }, +/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8180 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc100 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8120 } + }, +/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8100 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5000000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85200000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85000000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7000000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87200000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87000000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5800000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85800000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c00000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c00000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7800000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87800000 } + }, +/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2f000000 } + }, +/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3f000000 } + }, +/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1f000000 } + }, +/* sub.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xf0000 } + }, +/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2e0000 } + }, +/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3e0000 } + }, +/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1e000000 } + }, +/* sub.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xe00 } + }, +/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x98310000 } + }, +/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90b10000 } + }, +/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x90310000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92310000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92b10000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92f10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94310000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94b10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94f10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96f10000 } + }, +/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96310000 } + }, +/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96b10000 } + }, +/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x28 } + }, +/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2900 } + }, +/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2a00 } + }, +/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x2b0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992a00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91aa00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ba00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912a00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7ba0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7aa0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892a } + }, +/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81aa } + }, +/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812a } + }, +/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30a00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832a00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830a00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852a0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872a0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38a00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83aa00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838a00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85aa0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ca00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ea00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ca00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ca0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ea0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ca0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ca0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ea0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ca0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87aa0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982a00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90aa00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ba00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902a00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6ba0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6aa0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882a } + }, +/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80aa } + }, +/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802a } + }, +/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20a00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822a00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820a00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842a0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862a0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28a00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82aa00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828a00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84aa0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ca00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ea00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ca00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ca0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ea0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ca0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ca0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ea0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ca0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86aa0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa98000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9a000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa9b000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa98400 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa9a400 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa9b400 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa98600 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa9a600 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa9b600 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa9880000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9a80000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9b80000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa98c0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9ac0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9bc0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa98a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa98e0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9ae0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9be0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa98b0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9ab0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9bb0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa98f0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa9af0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa9bf0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa9c00000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9e00000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa9f00000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa9c40000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa9e40000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa9f40000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa9c60000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa9e60000 } + }, +/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa9f60000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa9c80000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa9e80000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa9f80000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa9cc0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa9ec0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa9fc0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ea0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa9fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ce0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ee0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa9fe0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9cb0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9eb0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa9fb0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa9cf0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa9ef0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa9ff0000 } + }, +/* sub.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa900 } + }, +/* sub.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa940 } + }, +/* sub.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa960 } + }, +/* sub.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa904 } + }, +/* sub.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa944 } + }, +/* sub.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa964 } + }, +/* sub.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa906 } + }, +/* sub.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa946 } + }, +/* sub.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa966 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa90800 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa94800 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa96800 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa90c0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa94c0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa96c0000 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa90a00 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa94a00 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa96a00 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa90e0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa94e0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa96e0000 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa90b00 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa94b00 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa96b00 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa90f0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa94f0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa96f0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa88000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8a000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa8b000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa88400 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa8a400 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa8b400 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa88600 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa8a600 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa8b600 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa8880000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8a80000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8b80000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa88c0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8ac0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8bc0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa88a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa88e0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8ae0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8be0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa88b0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8ab0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8bb0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa88f0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa8af0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa8bf0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa8c00000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8e00000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa8f00000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa8c40000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa8e40000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa8f40000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa8c60000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa8e60000 } + }, +/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa8f60000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa8c80000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa8e80000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa8f80000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa8cc0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa8ec0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa8fc0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ea0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa8fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ce0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ee0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa8fe0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8cb0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8eb0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa8fb0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa8cf0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa8ef0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa8ff0000 } + }, +/* sub.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa800 } + }, +/* sub.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa840 } + }, +/* sub.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa860 } + }, +/* sub.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa804 } + }, +/* sub.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa844 } + }, +/* sub.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa864 } + }, +/* sub.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa806 } + }, +/* sub.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa846 } + }, +/* sub.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa866 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa80800 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa84800 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa86800 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa80c0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa84c0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa86c0000 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa80a00 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa84a00 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa86a00 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa80e0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa84e0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa86e0000 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa80b00 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa84b00 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa86b00 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa80f0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa84f0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa86f0000 } + }, +/* sub.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8c00 } + }, +/* sub.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8b00 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x8d0000 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x8e0000 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x8f000000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893e0000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81be0000 } + }, +/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813e0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833e0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83be0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83fe0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853e0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85be0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85fe0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87fe0000 } + }, +/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873e0000 } + }, +/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87be0000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883e00 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80be00 } + }, +/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803e00 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823e0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82be0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82fe0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843e0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84be0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84fe0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86fe0000 } + }, +/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863e0000 } + }, +/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86be0000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77500000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77540000 } + }, +/* sub.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77560000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77580000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x775a0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x775b0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x775c0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x775e0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x775f0000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x765000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x765400 } + }, +/* sub.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x765600 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76580000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x765a0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x765b0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x765c0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x765e0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x765f0000 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93200 } + }, +/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13200 } + }, +/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90200 } + }, +/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18200 } + }, +/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10200 } + }, +/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c902 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18922 } + }, +/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18902 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c182 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a2 } + }, +/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18182 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c102 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18122 } + }, +/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18102 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83200 } + }, +/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03200 } + }, +/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80200 } + }, +/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08200 } + }, +/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00200 } + }, +/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c802 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18822 } + }, +/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18802 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c082 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a2 } + }, +/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18082 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c002 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18022 } + }, +/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18002 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868200 } + }, +/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1991e00 } + }, +/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1919e00 } + }, +/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1911e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1931e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1939e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193de00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1951e00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1959e00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195de00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197de00 } + }, +/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1971e00 } + }, +/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1979e00 } + }, +/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1981e00 } + }, +/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1909e00 } + }, +/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1901e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1921e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1929e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192de00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1941e00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1949e00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194de00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196de00 } + }, +/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1961e00 } + }, +/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1969e00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7aa00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892a } + }, +/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181aa } + }, +/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812a } + }, +/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6aa00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882a } + }, +/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180aa } + }, +/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802a } + }, +/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868a00 } + }, +/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1990e00 } + }, +/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1918e00 } + }, +/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1910e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1930e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1938e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ce00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1950e00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1958e00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ce00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ce00 } + }, +/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1970e00 } + }, +/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1978e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1980e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1908e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1900e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1920e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1928e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ce00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1940e00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1948e00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ce00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ce00 } + }, +/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1960e00 } + }, +/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1968e00 } + }, +/* divx.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a92f } + }, +/* divx.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a1af } + }, +/* divx.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a12f } + }, +/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a32f00 } + }, +/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a52f00 } + }, +/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a72f00 } + }, +/* divx.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a3af00 } + }, +/* divx.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a5af00 } + }, +/* divx.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3ef00 } + }, +/* divx.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5ef00 } + }, +/* divx.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7ef00 } + }, +/* divx.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a7af00 } + }, +/* divu.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a90f } + }, +/* divu.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a18f } + }, +/* divu.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a10f } + }, +/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a30f00 } + }, +/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a50f00 } + }, +/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a70f00 } + }, +/* divu.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a38f00 } + }, +/* divu.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a58f00 } + }, +/* divu.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3cf00 } + }, +/* divu.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5cf00 } + }, +/* divu.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7cf00 } + }, +/* divu.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a78f00 } + }, +/* div.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_Rn_direct_Prefixed_SI, { 0x1a91f } + }, +/* div.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_mulu_l_dst32_An_direct_Prefixed_SI, { 0x1a19f } + }, +/* div.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_An_indirect_Prefixed_SI, { 0x1a11f } + }, +/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_An_relative_Prefixed_SI, { 0x1a31f00 } + }, +/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_An_relative_Prefixed_SI, { 0x1a51f00 } + }, +/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_mulu_l_dst32_24_24_An_relative_Prefixed_SI, { 0x1a71f00 } + }, +/* div.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a39f00 } + }, +/* div.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a59f00 } + }, +/* div.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3df00 } + }, +/* div.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mulu_l_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5df00 } + }, +/* div.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_mulu_l_dst32_24_16_absolute_Prefixed_SI, { 0x1a7df00 } + }, +/* div.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_mulu_l_dst32_24_24_absolute_Prefixed_SI, { 0x1a79f00 } + }, +/* divx.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x991e } + }, +/* divx.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x919e } + }, +/* divx.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x911e } + }, +/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931e00 } + }, +/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x951e0000 } + }, +/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x971e0000 } + }, +/* divx.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939e00 } + }, +/* divx.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959e0000 } + }, +/* divx.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93de00 } + }, +/* divx.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95de0000 } + }, +/* divx.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97de0000 } + }, +/* divx.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x979e0000 } + }, +/* divx.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x981e } + }, +/* divx.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x909e } + }, +/* divx.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x901e } + }, +/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x921e00 } + }, +/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x941e0000 } + }, +/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x961e0000 } + }, +/* divx.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929e00 } + }, +/* divx.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949e0000 } + }, +/* divx.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92de00 } + }, +/* divx.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94de0000 } + }, +/* divx.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96de0000 } + }, +/* divx.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x969e0000 } + }, +/* divx.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7790 } + }, +/* divx.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7794 } + }, +/* divx.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7796 } + }, +/* divx.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x779800 } + }, +/* divx.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x779c0000 } + }, +/* divx.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x779a00 } + }, +/* divx.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x779e0000 } + }, +/* divx.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x779b00 } + }, +/* divx.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x779f0000 } + }, +/* divx.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7690 } + }, +/* divx.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7694 } + }, +/* divx.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7696 } + }, +/* divx.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x769800 } + }, +/* divx.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x769c0000 } + }, +/* divx.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x769a00 } + }, +/* divx.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x769e0000 } + }, +/* divx.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x769b00 } + }, +/* divx.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x769f0000 } + }, +/* divu.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x890e } + }, +/* divu.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x818e } + }, +/* divu.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x810e } + }, +/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x830e00 } + }, +/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x850e0000 } + }, +/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x870e0000 } + }, +/* divu.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838e00 } + }, +/* divu.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858e0000 } + }, +/* divu.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ce00 } + }, +/* divu.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ce0000 } + }, +/* divu.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87ce0000 } + }, +/* divu.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x878e0000 } + }, +/* divu.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x880e } + }, +/* divu.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x808e } + }, +/* divu.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x800e } + }, +/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820e00 } + }, +/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x840e0000 } + }, +/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x860e0000 } + }, +/* divu.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828e00 } + }, +/* divu.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848e0000 } + }, +/* divu.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ce00 } + }, +/* divu.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ce0000 } + }, +/* divu.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86ce0000 } + }, +/* divu.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x868e0000 } + }, +/* divu.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77c0 } + }, +/* divu.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77c4 } + }, +/* divu.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77c6 } + }, +/* divu.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77c800 } + }, +/* divu.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77cc0000 } + }, +/* divu.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ca00 } + }, +/* divu.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ce0000 } + }, +/* divu.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77cb00 } + }, +/* divu.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77cf0000 } + }, +/* divu.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76c0 } + }, +/* divu.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76c4 } + }, +/* divu.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76c6 } + }, +/* divu.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76c800 } + }, +/* divu.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76cc0000 } + }, +/* divu.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ca00 } + }, +/* divu.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ce0000 } + }, +/* divu.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76cb00 } + }, +/* divu.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76cf0000 } + }, +/* div.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x891e } + }, +/* div.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x819e } + }, +/* div.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x811e } + }, +/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831e00 } + }, +/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x851e0000 } + }, +/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x871e0000 } + }, +/* div.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839e00 } + }, +/* div.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859e0000 } + }, +/* div.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83de00 } + }, +/* div.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85de0000 } + }, +/* div.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87de0000 } + }, +/* div.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x879e0000 } + }, +/* div.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x881e } + }, +/* div.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x809e } + }, +/* div.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x801e } + }, +/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x821e00 } + }, +/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x841e0000 } + }, +/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x861e0000 } + }, +/* div.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829e00 } + }, +/* div.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849e0000 } + }, +/* div.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82de00 } + }, +/* div.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84de0000 } + }, +/* div.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86de0000 } + }, +/* div.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x869e0000 } + }, +/* div.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77d0 } + }, +/* div.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77d4 } + }, +/* div.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77d6 } + }, +/* div.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77d800 } + }, +/* div.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77dc0000 } + }, +/* div.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77da00 } + }, +/* div.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77de0000 } + }, +/* div.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77db00 } + }, +/* div.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77df0000 } + }, +/* div.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76d0 } + }, +/* div.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76d4 } + }, +/* div.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76d6 } + }, +/* div.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76d800 } + }, +/* div.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76dc0000 } + }, +/* div.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76da00 } + }, +/* div.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76de0000 } + }, +/* div.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76db00 } + }, +/* div.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76df0000 } + }, +/* dec.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb90e } + }, +/* dec.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18e } + }, +/* dec.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb10e } + }, +/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30e00 } + }, +/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50e0000 } + }, +/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70e0000 } + }, +/* dec.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38e00 } + }, +/* dec.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58e0000 } + }, +/* dec.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ce00 } + }, +/* dec.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ce0000 } + }, +/* dec.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ce0000 } + }, +/* dec.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb78e0000 } + }, +/* dec.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb80e } + }, +/* dec.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb08e } + }, +/* dec.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb00e } + }, +/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20e00 } + }, +/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40e0000 } + }, +/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60e0000 } + }, +/* dec.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28e00 } + }, +/* dec.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48e0000 } + }, +/* dec.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ce00 } + }, +/* dec.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ce0000 } + }, +/* dec.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ce0000 } + }, +/* dec.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb68e0000 } + }, +/* dec.b r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0l_direct_QI, { 0xac } + }, +/* dec.b r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', 0 } }, + & ifmt_not16_b_s_dst16_3_S_R0h_direct_QI, { 0xab } + }, +/* dec.b ${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_SB_relative_QI, { 0xad00 } + }, +/* dec.b ${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_8_FB_relative_QI, { 0xae00 } + }, +/* dec.b ${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U16), 0 } }, + & ifmt_not16_b_s_dst16_3_S_8_16_absolute_QI, { 0xaf0000 } + }, +/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa81100 } + }, +/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa09100 } + }, +/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa01100 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2110000 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2910000 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2d10000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4110000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4910000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4d10000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6d10000 } + }, +/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6110000 } + }, +/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6910000 } + }, +/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI, { 0x6100 } + }, +/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI, { 0x7100 } + }, +/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI, { 0x510000 } + }, +/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI, { 0x6000 } + }, +/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI, { 0x7000 } + }, +/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI, { 0x500000 } + }, +/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x67000000 } + }, +/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x77000000 } + }, +/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x57000000 } + }, +/* cmp.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x470000 } + }, +/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x660000 } + }, +/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x760000 } + }, +/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x56000000 } + }, +/* cmp.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4600 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc901 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8921 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8901 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc181 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a1 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8181 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc101 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8121 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8101 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5010000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85210000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85010000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7010000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87210000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87010000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5810000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85810000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c10000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c10000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7810000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87810000 } + }, +/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x38 } + }, +/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x3900 } + }, +/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x3a00 } + }, +/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x3b0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc906 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8926 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8906 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc186 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a6 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8186 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc106 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8126 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8106 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5060000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85260000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85060000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7060000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87260000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87060000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5860000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85860000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c60000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c60000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7860000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc806 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8826 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8806 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc086 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a6 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8086 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc006 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8026 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8006 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4060000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84260000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84060000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6060000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86260000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86060000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4860000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84860000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c60000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c60000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6860000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xc18000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1a000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xc1b000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xc18400 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xc1a400 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xc1b400 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xc18600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xc1a600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xc1b600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xc1880000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1a80000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1b80000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xc18c0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1ac0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1bc0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xc18a0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1aa0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1ba0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xc18e0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1ae0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1be0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xc18b0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1ab0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1bb0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xc18f0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xc1af0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xc1bf0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xc1c00000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1e00000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xc1f00000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xc1c40000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xc1e40000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xc1f40000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xc1c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xc1e60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xc1f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xc1c80000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xc1e80000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xc1f80000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xc1cc0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xc1ec0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xc1fc0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ca0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ea0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xc1fa0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ce0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ee0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xc1fe0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1cb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1eb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xc1fb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xc1cf0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xc1ef0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xc1ff0000 } + }, +/* cmp.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xc100 } + }, +/* cmp.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xc140 } + }, +/* cmp.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xc160 } + }, +/* cmp.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xc104 } + }, +/* cmp.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xc144 } + }, +/* cmp.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xc164 } + }, +/* cmp.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xc106 } + }, +/* cmp.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xc146 } + }, +/* cmp.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xc166 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xc10800 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xc14800 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xc16800 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xc10c0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xc14c0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xc16c0000 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xc10a00 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xc14a00 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xc16a00 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xc10e0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xc14e0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xc16e0000 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xc10b00 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xc14b00 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xc16b00 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xc10f0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xc14f0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xc16f0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xc08000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0a000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xc0b000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xc08400 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xc0a400 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xc0b400 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xc08600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xc0a600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xc0b600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xc0880000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0a80000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0b80000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xc08c0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0ac0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0bc0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xc08a0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0aa0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0ba0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xc08e0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0ae0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0be0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xc08b0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0ab0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0bb0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xc08f0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xc0af0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xc0bf0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xc0c00000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0e00000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xc0f00000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xc0c40000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xc0e40000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xc0f40000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xc0c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xc0e60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xc0f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xc0c80000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xc0e80000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xc0f80000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xc0cc0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xc0ec0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xc0fc0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ca0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ea0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xc0fa0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ce0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ee0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xc0fe0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0cb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0eb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xc0fb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xc0cf0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xc0ef0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xc0ff0000 } + }, +/* cmp.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xc000 } + }, +/* cmp.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xc040 } + }, +/* cmp.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xc060 } + }, +/* cmp.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xc004 } + }, +/* cmp.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xc044 } + }, +/* cmp.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xc064 } + }, +/* cmp.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xc006 } + }, +/* cmp.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xc046 } + }, +/* cmp.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xc066 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xc00800 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xc04800 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xc06800 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xc00c0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xc04c0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xc06c0000 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xc00a00 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xc04a00 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xc06a00 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xc00e0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xc04e0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xc06e0000 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xc00b00 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xc04b00 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xc06b00 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xc00f0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xc04f0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xc06f0000 } + }, +/* cmp.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xe400 } + }, +/* cmp.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xe300 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xe50000 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xe60000 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xe7000000 } + }, +/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe910 } + }, +/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe190 } + }, +/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe110 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe31000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5100000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7100000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe39000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5900000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3d000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5d00000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7d00000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7900000 } + }, +/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe810 } + }, +/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe090 } + }, +/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe010 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe21000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4100000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6100000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe29000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4900000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2d000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4d00000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6d00000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6900000 } + }, +/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd100 } + }, +/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd104 } + }, +/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd106 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd10800 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd10c0000 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd10a00 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd10e0000 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd10b00 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd10f0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xd000 } + }, +/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xd004 } + }, +/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xd006 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd00800 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd00c0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd00a00 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd00e0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd00b00 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd00f0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992e0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91ae0000 } + }, +/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912e0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932e0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93ae0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ee0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952e0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95ae0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ee0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ee0000 } + }, +/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972e0000 } + }, +/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97ae0000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982e00 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90ae00 } + }, +/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902e00 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922e0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92ae0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ee0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942e0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94ae0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ee0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ee0000 } + }, +/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962e0000 } + }, +/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96ae0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77800000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77840000 } + }, +/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77860000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77880000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x778a0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x778b0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x778c0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x778e0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x778f0000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x768000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x768400 } + }, +/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x768600 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76880000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x768a0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x768b0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x768c0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x768e0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x768f0000 } + }, +/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa8310000 } + }, +/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0b10000 } + }, +/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa0310000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2310000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2b10000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2f10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4310000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4b10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4f10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6f10000 } + }, +/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6310000 } + }, +/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6b10000 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893e00 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181be00 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813e00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833e00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183be00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183fe00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853e00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185be00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185fe00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187fe00 } + }, +/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873e00 } + }, +/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187be00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883e00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180be00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803e00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823e00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182be00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182fe00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843e00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184be00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184fe00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186fe00 } + }, +/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863e00 } + }, +/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186be00 } + }, +/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d828 } + }, +/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a8 } + }, +/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d028 } + }, +/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42800 } + }, +/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62800 } + }, +/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a800 } + }, +/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e800 } + }, +/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e800 } + }, +/* bxor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a800 } + }, +/* bxor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ec000 } + }, +/* bxor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ec400 } + }, +/* bxor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ec6 } + }, +/* bxor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ec800 } + }, +/* bxor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ecc0000 } + }, +/* bxor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eca00 } + }, +/* bxor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ece0000 } + }, +/* bxor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ecb00 } + }, +/* bxor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ecf0000 } + }, +/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd828 } + }, +/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a8 } + }, +/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd028 } + }, +/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22800 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4280000 } + }, +/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6280000 } + }, +/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a800 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a80000 } + }, +/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e800 } + }, +/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e80000 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e80000 } + }, +/* btsts${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a80000 } + }, +/* btsts${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e1000 } + }, +/* btsts${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e1400 } + }, +/* btsts${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e16 } + }, +/* btsts${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e1800 } + }, +/* btsts${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e1c0000 } + }, +/* btsts${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e1a00 } + }, +/* btsts${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e1e0000 } + }, +/* btsts${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e1b00 } + }, +/* btsts${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e1f0000 } + }, +/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd820 } + }, +/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a0 } + }, +/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd020 } + }, +/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4200000 } + }, +/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6200000 } + }, +/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a00000 } + }, +/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e000 } + }, +/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e00000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e00000 } + }, +/* btstc${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a00000 } + }, +/* btstc${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e0000 } + }, +/* btstc${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e0400 } + }, +/* btstc${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e06 } + }, +/* btstc${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e0800 } + }, +/* btstc${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e0c0000 } + }, +/* btstc${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e0a00 } + }, +/* btstc${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e0e0000 } + }, +/* btstc${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e0b00 } + }, +/* btstc${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e0f0000 } + }, +/* btst${G} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd800 } + }, +/* btst${G} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd080 } + }, +/* btst${G} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd000 } + }, +/* btst${G} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd20000 } + }, +/* btst${G} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4000000 } + }, +/* btst${G} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6000000 } + }, +/* btst${G} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd28000 } + }, +/* btst${G} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4800000 } + }, +/* btst${G} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2c000 } + }, +/* btst${G} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4c00000 } + }, +/* btst${G} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6c00000 } + }, +/* btst${G} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6800000 } + }, +/* btst${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7eb000 } + }, +/* btst${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7eb400 } + }, +/* btst${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7eb800 } + }, +/* btst${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eba00 } + }, +/* btst${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ebb00 } + }, +/* btst${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5800 } + }, +/* btst${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ebc0000 } + }, +/* btst${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ebe0000 } + }, +/* btst${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ebf0000 } + }, +/* btst${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7eb6 } + }, +/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd838 } + }, +/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b8 } + }, +/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd038 } + }, +/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23800 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4380000 } + }, +/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6380000 } + }, +/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b800 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b80000 } + }, +/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f800 } + }, +/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f80000 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f80000 } + }, +/* bset${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b80000 } + }, +/* bset${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e9000 } + }, +/* bset${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e9400 } + }, +/* bset${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e9800 } + }, +/* bset${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e9a00 } + }, +/* bset${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e9b00 } + }, +/* bset${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4800 } + }, +/* bset${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e9c0000 } + }, +/* bset${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e9e0000 } + }, +/* bset${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e9f0000 } + }, +/* bset${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e96 } + }, +/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d820 } + }, +/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a0 } + }, +/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d020 } + }, +/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42000 } + }, +/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62000 } + }, +/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a000 } + }, +/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e000 } + }, +/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e000 } + }, +/* bor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a000 } + }, +/* bor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e6000 } + }, +/* bor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e6400 } + }, +/* bor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e66 } + }, +/* bor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e6800 } + }, +/* bor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e6c0000 } + }, +/* bor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e6a00 } + }, +/* bor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e6e0000 } + }, +/* bor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e6b00 } + }, +/* bor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e6f0000 } + }, +/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d838 } + }, +/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b8 } + }, +/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d038 } + }, +/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43800 } + }, +/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63800 } + }, +/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b800 } + }, +/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f800 } + }, +/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f800 } + }, +/* bnxor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b800 } + }, +/* bnxor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ed000 } + }, +/* bnxor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ed400 } + }, +/* bnxor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ed6 } + }, +/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ed800 } + }, +/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7edc0000 } + }, +/* bnxor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eda00 } + }, +/* bnxor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ede0000 } + }, +/* bnxor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7edb00 } + }, +/* bnxor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7edf0000 } + }, +/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d800 } + }, +/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d080 } + }, +/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d000 } + }, +/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40000 } + }, +/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60000 } + }, +/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48000 } + }, +/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c000 } + }, +/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c000 } + }, +/* bntst${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68000 } + }, +/* bntst${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e3000 } + }, +/* bntst${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e3400 } + }, +/* bntst${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e36 } + }, +/* bntst${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e3800 } + }, +/* bntst${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e3c0000 } + }, +/* bntst${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e3a00 } + }, +/* bntst${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e3e0000 } + }, +/* bntst${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e3b00 } + }, +/* bntst${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e3f0000 } + }, +/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd818 } + }, +/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd098 } + }, +/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd018 } + }, +/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd21800 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4180000 } + }, +/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6180000 } + }, +/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd29800 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4980000 } + }, +/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2d800 } + }, +/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4d80000 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6d80000 } + }, +/* bnot${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6980000 } + }, +/* bnot${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ea000 } + }, +/* bnot${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ea400 } + }, +/* bnot${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ea800 } + }, +/* bnot${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eaa00 } + }, +/* bnot${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7eab00 } + }, +/* bnot${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5000 } + }, +/* bnot${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7eac0000 } + }, +/* bnot${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7eae0000 } + }, +/* bnot${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7eaf0000 } + }, +/* bnot${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ea6 } + }, +/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d830 } + }, +/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b0 } + }, +/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d030 } + }, +/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43000 } + }, +/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63000 } + }, +/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b000 } + }, +/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f000 } + }, +/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f000 } + }, +/* bnor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b000 } + }, +/* bnor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e7000 } + }, +/* bnor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e7400 } + }, +/* bnor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e76 } + }, +/* bnor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e7800 } + }, +/* bnor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e7c0000 } + }, +/* bnor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e7a00 } + }, +/* bnor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e7e0000 } + }, +/* bnor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e7b00 } + }, +/* bnor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e7f0000 } + }, +/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d818 } + }, +/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d098 } + }, +/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d018 } + }, +/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d21800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d41800 } + }, +/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d61800 } + }, +/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d29800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d49800 } + }, +/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2d800 } + }, +/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4d800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6d800 } + }, +/* bnand${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d69800 } + }, +/* bnand${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e5000 } + }, +/* bnand${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e5400 } + }, +/* bnand${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e56 } + }, +/* bnand${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e5800 } + }, +/* bnand${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e5c0000 } + }, +/* bnand${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e5a00 } + }, +/* bnand${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e5e0000 } + }, +/* bnand${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e5b00 } + }, +/* bnand${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e5f0000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed, { 0xd81000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed, { 0xd09000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed, { 0xd01000 } + }, +/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed, { 0xd2100000 } + }, +/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed, { 0xd2900000 } + }, +/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed, { 0xd2d00000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed, { 0xd4100000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed, { 0xd4900000 } + }, +/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed, { 0xd4d00000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed, { 0xd6d00000 } + }, +/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed, { 0xd6100000 } + }, +/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed, { 0xd6900000 } + }, +/* bm${cond16-24} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct, { 0x7e200000 } + }, +/* bm${cond16-24} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct, { 0x7e240000 } + }, +/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative, { 0x7e280000 } + }, +/* bm${cond16-24} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative, { 0x7e2a0000 } + }, +/* bm${cond16-24} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative, { 0x7e2b0000 } + }, +/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative, { 0x7e2c0000 } + }, +/* bm${cond16-32} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative, { 0x7e2e0000 } + }, +/* bm${cond16-32} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute, { 0x7e2f0000 } + }, +/* bm${cond16-16} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_16), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect, { 0x7e2600 } + }, +/* bitindex.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc92e } + }, +/* bitindex.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1ae } + }, +/* bitindex.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc12e } + }, +/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc32e00 } + }, +/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc52e0000 } + }, +/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc72e0000 } + }, +/* bitindex.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3ae00 } + }, +/* bitindex.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5ae0000 } + }, +/* bitindex.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ee00 } + }, +/* bitindex.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ee0000 } + }, +/* bitindex.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ee0000 } + }, +/* bitindex.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7ae0000 } + }, +/* bitindex.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc82e } + }, +/* bitindex.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0ae } + }, +/* bitindex.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc02e } + }, +/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22e00 } + }, +/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc42e0000 } + }, +/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc62e0000 } + }, +/* bitindex.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2ae00 } + }, +/* bitindex.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4ae0000 } + }, +/* bitindex.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ee00 } + }, +/* bitindex.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ee0000 } + }, +/* bitindex.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ee0000 } + }, +/* bitindex.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6ae0000 } + }, +/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd830 } + }, +/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b0 } + }, +/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd030 } + }, +/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4300000 } + }, +/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6300000 } + }, +/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b00000 } + }, +/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f000 } + }, +/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f00000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f00000 } + }, +/* bclr${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b00000 } + }, +/* bclr${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e8000 } + }, +/* bclr${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e8400 } + }, +/* bclr${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e8800 } + }, +/* bclr${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e8a00 } + }, +/* bclr${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e8b00 } + }, +/* bclr${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4000 } + }, +/* bclr${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e8c0000 } + }, +/* bclr${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e8e0000 } + }, +/* bclr${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e8f0000 } + }, +/* bclr${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e86 } + }, +/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d808 } + }, +/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d088 } + }, +/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d008 } + }, +/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40800 } + }, +/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60800 } + }, +/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48800 } + }, +/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c800 } + }, +/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c800 } + }, +/* band${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68800 } + }, +/* band${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e4000 } + }, +/* band${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e4400 } + }, +/* band${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e46 } + }, +/* band${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e4800 } + }, +/* band${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e4c0000 } + }, +/* band${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e4a00 } + }, +/* band${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e4e0000 } + }, +/* band${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e4b00 } + }, +/* band${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e4f0000 } + }, +/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6d000000 } + }, +/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7d000000 } + }, +/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x5d000000 } + }, +/* and.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x4d0000 } + }, +/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6c0000 } + }, +/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7c0000 } + }, +/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x5c000000 } + }, +/* and.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4c00 } + }, +/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x10 } + }, +/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1100 } + }, +/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1200 } + }, +/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x130000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992d00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993d00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ad00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bd00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912d00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913d00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93d0000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13d0000 } + }, +/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bd0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90d0000 } + }, +/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18d0000 } + }, +/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10d0000 } + }, +/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ad0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90d } + }, +/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892d } + }, +/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890d } + }, +/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18d } + }, +/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ad } + }, +/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818d } + }, +/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10d } + }, +/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812d } + }, +/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810d } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30d00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832d00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830d00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852d0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872d0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38d00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ad00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838d00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ad0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cd00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ed00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cd00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cd0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ed0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cd0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cd0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ed0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cd0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ad0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982d00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983d00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ad00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bd00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902d00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903d00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83d0000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03d0000 } + }, +/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bd0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80d0000 } + }, +/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08d0000 } + }, +/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00d0000 } + }, +/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ad0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80d } + }, +/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882d } + }, +/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880d } + }, +/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08d } + }, +/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ad } + }, +/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808d } + }, +/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00d } + }, +/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802d } + }, +/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800d } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20d00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822d00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820d00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842d0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862d0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28d00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ad00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828d00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ad0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cd00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ed00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cd00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cd0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ed0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cd0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cd0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ed0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cd0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ad0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x918000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x91a000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x91b000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x918400 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x91a400 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x91b400 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x918600 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x91a600 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x91b600 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x91880000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x91a80000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x91b80000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x918c0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x91ac0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x91bc0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x918a0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91aa0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91ba0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x918e0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91ae0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91be0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x918b0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91ab0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91bb0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x918f0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x91af0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x91bf0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x91c00000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x91e00000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x91f00000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x91c40000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x91e40000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x91f40000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x91c60000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x91e60000 } + }, +/* and.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x91f60000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x91c80000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x91e80000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x91f80000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x91cc0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x91ec0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x91fc0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ca0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ea0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x91fa0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ce0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ee0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x91fe0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x91cb0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x91eb0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x91fb0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x91cf0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x91ef0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x91ff0000 } + }, +/* and.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9100 } + }, +/* and.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9140 } + }, +/* and.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9160 } + }, +/* and.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9104 } + }, +/* and.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9144 } + }, +/* and.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9164 } + }, +/* and.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9106 } + }, +/* and.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9146 } + }, +/* and.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9166 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x910800 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x914800 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x916800 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x910c0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x914c0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x916c0000 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x910a00 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x914a00 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x916a00 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x910e0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x914e0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x916e0000 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x910b00 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x914b00 } + }, +/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x916b00 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x910f0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x914f0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x916f0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x908000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x90a000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x90b000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x908400 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x90a400 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x90b400 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x908600 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x90a600 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x90b600 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x90880000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x90a80000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x90b80000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x908c0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x90ac0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x90bc0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x908a0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90aa0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90ba0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x908e0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90ae0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90be0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x908b0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90ab0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90bb0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x908f0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x90af0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x90bf0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x90c00000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x90e00000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x90f00000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x90c40000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x90e40000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x90f40000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x90c60000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x90e60000 } + }, +/* and.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x90f60000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x90c80000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x90e80000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x90f80000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x90cc0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x90ec0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x90fc0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ca0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ea0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x90fa0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ce0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ee0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x90fe0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x90cb0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x90eb0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x90fb0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x90cf0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x90ef0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x90ff0000 } + }, +/* and.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9000 } + }, +/* and.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9040 } + }, +/* and.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9060 } + }, +/* and.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9004 } + }, +/* and.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9044 } + }, +/* and.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9064 } + }, +/* and.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9006 } + }, +/* and.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9046 } + }, +/* and.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9066 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x900800 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x904800 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x906800 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x900c0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x904c0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x906c0000 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x900a00 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x904a00 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x906a00 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x900e0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x904e0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x906e0000 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x900b00 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x904b00 } + }, +/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x906b00 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x900f0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x904f0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x906f0000 } + }, +/* and.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9400 } + }, +/* and.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9300 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x950000 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x960000 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x97000000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893f0000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81bf0000 } + }, +/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813f0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833f0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83bf0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ff0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853f0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85bf0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ff0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ff0000 } + }, +/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873f0000 } + }, +/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87bf0000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883f00 } + }, +/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80bf00 } + }, +/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803f00 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823f0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82bf0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ff0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843f0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84bf0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ff0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ff0000 } + }, +/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863f0000 } + }, +/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86bf0000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77200000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77240000 } + }, +/* and.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77260000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77280000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x772a0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x772b0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x772c0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x772e0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x772f0000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x762000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x762400 } + }, +/* and.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x762600 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76280000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x762a0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x762b0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x762c0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x762e0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x762f0000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_adjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 } + }, +/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 } + }, +/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 } + }, +/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_adjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 } + }, +/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 } + }, +/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 } + }, +/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 } + }, +/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 } + }, +/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 } + }, +/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_adjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 } + }, +/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 } + }, +/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 } + }, +/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_adjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8320000 } + }, +/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b20000 } + }, +/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0320000 } + }, +/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8020000 } + }, +/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0820000 } + }, +/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0020000 } + }, +/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc802 } + }, +/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8822 } + }, +/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8802 } + }, +/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc082 } + }, +/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a2 } + }, +/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8082 } + }, +/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc002 } + }, +/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8022 } + }, +/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8002 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4020000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84220000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84020000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6020000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86220000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86020000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4820000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84820000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c20000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c20000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6820000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86820000 } + }, +/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x881100 } + }, +/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x809100 } + }, +/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x801100 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82110000 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82910000 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82d10000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84110000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84910000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84d10000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86d10000 } + }, +/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86110000 } + }, +/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86910000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93000 } + }, +/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13000 } + }, +/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90000 } + }, +/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18000 } + }, +/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10000 } + }, +/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c900 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18920 } + }, +/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18900 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c180 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a0 } + }, +/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18180 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c100 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18120 } + }, +/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18100 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83000 } + }, +/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03000 } + }, +/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80000 } + }, +/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08000 } + }, +/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00000 } + }, +/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c800 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18820 } + }, +/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18800 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c080 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a0 } + }, +/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18080 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18020 } + }, +/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868000 } + }, +/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1891e00 } + }, +/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1819e00 } + }, +/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1811e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1831e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1839e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183de00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1851e00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1859e00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185de00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187de00 } + }, +/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1871e00 } + }, +/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1879e00 } + }, +/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1881e00 } + }, +/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1809e00 } + }, +/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1801e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1821e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1829e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182de00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1841e00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1849e00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184de00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186de00 } + }, +/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1861e00 } + }, +/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1869e00 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93800 } + }, +/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13800 } + }, +/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90800 } + }, +/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18800 } + }, +/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10800 } + }, +/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c908 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18928 } + }, +/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18908 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c188 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a8 } + }, +/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18188 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c108 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18128 } + }, +/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18108 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83800 } + }, +/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03800 } + }, +/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80800 } + }, +/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08800 } + }, +/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00800 } + }, +/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c808 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18828 } + }, +/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18808 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c088 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a8 } + }, +/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18088 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c008 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18028 } + }, +/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18008 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868800 } + }, +/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1890e00 } + }, +/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1818e00 } + }, +/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1810e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1830e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ce00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1850e00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858e00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ce00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ce00 } + }, +/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1870e00 } + }, +/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1878e00 } + }, +/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1880e00 } + }, +/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1808e00 } + }, +/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1800e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1820e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ce00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1840e00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848e00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ce00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ce00 } + }, +/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1860e00 } + }, +/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1868e00 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93400 } + }, +/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b400 } + }, +/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13400 } + }, +/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90400 } + }, +/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18400 } + }, +/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10400 } + }, +/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c904 } + }, +/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18924 } + }, +/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18904 } + }, +/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c184 } + }, +/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a4 } + }, +/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18184 } + }, +/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c104 } + }, +/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18124 } + }, +/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18104 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83400 } + }, +/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b400 } + }, +/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03400 } + }, +/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80400 } + }, +/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08400 } + }, +/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00400 } + }, +/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c804 } + }, +/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18824 } + }, +/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18804 } + }, +/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c084 } + }, +/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a4 } + }, +/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18084 } + }, +/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c004 } + }, +/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18024 } + }, +/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18004 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868400 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb18000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1a000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb1b000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb18400 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb1a400 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb1b400 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb18600 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb1a600 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb1b600 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb1880000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1a80000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1b80000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb18c0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1ac0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1bc0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb18a0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1aa0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1ba0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb18e0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1ae0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1be0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb18b0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1ab0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1bb0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb18f0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb1af0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb1bf0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb1c00000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1e00000 } + }, +/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb1f00000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb1c40000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb1e40000 } + }, +/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb1f40000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb1c60000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb1e60000 } + }, +/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb1f60000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb1c80000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb1e80000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb1f80000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb1cc0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb1ec0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb1fc0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ca0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ea0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb1fa0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ce0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ee0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb1fe0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1cb0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1eb0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb1fb0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb1cf0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb1ef0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb1ff0000 } + }, +/* adc.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb100 } + }, +/* adc.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb140 } + }, +/* adc.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb160 } + }, +/* adc.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb104 } + }, +/* adc.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb144 } + }, +/* adc.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb164 } + }, +/* adc.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb106 } + }, +/* adc.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb146 } + }, +/* adc.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb166 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb10800 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb14800 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb16800 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb10c0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb14c0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb16c0000 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb10a00 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb14a00 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb16a00 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb10e0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb14e0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb16e0000 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb10b00 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb14b00 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb16b00 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb10f0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb14f0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb16f0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb08000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0a000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb0b000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb08400 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb0a400 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb0b400 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb08600 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb0a600 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb0b600 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb0880000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0a80000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0b80000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb08c0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0ac0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0bc0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb08a0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0aa0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0ba0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb08e0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0ae0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0be0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb08b0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0ab0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0bb0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb08f0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb0af0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb0bf0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb0c00000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0e00000 } + }, +/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb0f00000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb0c40000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb0e40000 } + }, +/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb0f40000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb0c60000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb0e60000 } + }, +/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb0f60000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb0c80000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb0e80000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb0f80000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb0cc0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb0ec0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb0fc0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ca0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ea0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb0fa0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ce0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ee0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb0fe0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0cb0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0eb0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb0fb0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb0cf0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb0ef0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb0ff0000 } + }, +/* adc.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb000 } + }, +/* adc.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb040 } + }, +/* adc.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb060 } + }, +/* adc.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb004 } + }, +/* adc.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb044 } + }, +/* adc.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb064 } + }, +/* adc.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb006 } + }, +/* adc.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb046 } + }, +/* adc.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb066 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb00800 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb04800 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb06800 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb00c0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb04c0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb06c0000 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb00a00 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb04a00 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb06a00 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb00e0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb04e0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb06e0000 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb00b00 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb04b00 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb06b00 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb00f0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb04f0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb06f0000 } + }, +/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892e00 } + }, +/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181ae00 } + }, +/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812e00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832e00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ae00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ee00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852e00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ae00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ee00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ee00 } + }, +/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872e00 } + }, +/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187ae00 } + }, +/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882e00 } + }, +/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180ae00 } + }, +/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802e00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822e00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ae00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ee00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842e00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ae00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ee00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ee00 } + }, +/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862e00 } + }, +/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186ae00 } + }, +/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77600000 } + }, +/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77640000 } + }, +/* adc.w${X} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77660000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77680000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x776a0000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x776b0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x776c0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x776e0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x776f0000 } + }, +/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x766000 } + }, +/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x766400 } + }, +/* adc.b${X} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x766600 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76680000 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x766a0000 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x766b0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x766c0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x766e0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x766f0000 } + }, +/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x27000000 } + }, +/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x37000000 } + }, +/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x17000000 } + }, +/* add.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x70000 } + }, +/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x260000 } + }, +/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x360000 } + }, +/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x16000000 } + }, +/* add.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x600 } + }, +/* add.l${S} #${Imm1-S},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '0', 0 } }, + & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI, { 0x8c } + }, +/* add.l${S} #${Imm1-S},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '1', 0 } }, + & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI, { 0x8d } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9320000 } + }, +/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b20000 } + }, +/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1320000 } + }, +/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9020000 } + }, +/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1820000 } + }, +/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1020000 } + }, +/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc902 } + }, +/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8922 } + }, +/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8902 } + }, +/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc182 } + }, +/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a2 } + }, +/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8182 } + }, +/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc102 } + }, +/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8122 } + }, +/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8102 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5020000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85220000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85020000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7020000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87220000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87020000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5820000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85820000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c20000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c20000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7820000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87820000 } + }, +/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_or16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x20 } + }, +/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2100 } + }, +/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2200 } + }, +/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_or16_b_S_src2_src16_2_S_16_absolute_QI, { 0x230000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9380000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b80000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1380000 } + }, +/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9080000 } + }, +/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1880000 } + }, +/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1080000 } + }, +/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc908 } + }, +/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8928 } + }, +/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8908 } + }, +/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc188 } + }, +/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a8 } + }, +/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8188 } + }, +/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc108 } + }, +/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8128 } + }, +/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8108 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5080000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85280000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85080000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7080000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87280000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87080000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5880000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85880000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c80000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c80000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7880000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87880000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8380000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b80000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0380000 } + }, +/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8080000 } + }, +/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0880000 } + }, +/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0080000 } + }, +/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc808 } + }, +/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8828 } + }, +/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8808 } + }, +/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc088 } + }, +/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a8 } + }, +/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8088 } + }, +/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc008 } + }, +/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8028 } + }, +/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8008 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4080000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84280000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84080000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6080000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86280000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86080000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4880000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84880000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c80000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c80000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6880000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86880000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa18000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1a000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa1b000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa18400 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa1a400 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa1b400 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa18600 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa1a600 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa1b600 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa1880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa18c0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1ac0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1bc0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa18a0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1aa0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1ba0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa18e0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1ae0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1be0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa18b0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1ab0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1bb0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa18f0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa1af0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa1bf0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa1c00000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1e00000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa1f00000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa1c40000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa1e40000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa1f40000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa1c60000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa1e60000 } + }, +/* add.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa1f60000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa1c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa1e80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa1f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa1cc0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa1ec0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa1fc0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ca0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ea0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa1fa0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ce0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ee0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa1fe0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1cb0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1eb0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa1fb0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa1cf0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa1ef0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa1ff0000 } + }, +/* add.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa100 } + }, +/* add.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa140 } + }, +/* add.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa160 } + }, +/* add.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa104 } + }, +/* add.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa144 } + }, +/* add.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa164 } + }, +/* add.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa106 } + }, +/* add.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa146 } + }, +/* add.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa166 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa10800 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa14800 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa16800 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa10c0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa14c0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa16c0000 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa10a00 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa14a00 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa16a00 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa10e0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa14e0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa16e0000 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa10b00 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa14b00 } + }, +/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa16b00 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa10f0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa14f0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa16f0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa08000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0a000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa0b000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa08400 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa0a400 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa0b400 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa08600 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa0a600 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa0b600 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa0880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa08c0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0ac0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0bc0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa08a0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0aa0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0ba0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa08e0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0ae0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0be0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa08b0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0ab0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0bb0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa08f0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa0af0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa0bf0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa0c00000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0e00000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa0f00000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa0c40000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa0e40000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa0f40000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa0c60000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa0e60000 } + }, +/* add.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa0f60000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa0c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa0e80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa0f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa0cc0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa0ec0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa0fc0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ca0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ea0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa0fa0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ce0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ee0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa0fe0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0cb0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0eb0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa0fb0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa0cf0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa0ef0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa0ff0000 } + }, +/* add.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa000 } + }, +/* add.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa040 } + }, +/* add.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa060 } + }, +/* add.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa004 } + }, +/* add.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa044 } + }, +/* add.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa064 } + }, +/* add.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa006 } + }, +/* add.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa046 } + }, +/* add.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa066 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa00800 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa04800 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa06800 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa00c0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa04c0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa06c0000 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa00a00 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa04a00 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa06a00 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa00e0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa04e0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa06e0000 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa00b00 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa04b00 } + }, +/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa06b00 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa00f0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa04f0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa06f0000 } + }, +/* add.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8400 } + }, +/* add.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8300 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x850000 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x860000 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x87000000 } + }, +/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xf830 } + }, +/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xf0b0 } + }, +/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xf030 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xf23000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xf4300000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xf6300000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xf2b000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xf4b00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xf2f000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xf4f00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xf6f00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xf6b00000 } + }, +/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe930 } + }, +/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1b0 } + }, +/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe130 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe33000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5300000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7300000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3b000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5b00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3f000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5f00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7f00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7b00000 } + }, +/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe830 } + }, +/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0b0 } + }, +/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe030 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe23000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4300000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6300000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2b000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4b00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2f000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4f00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6f00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6b00000 } + }, +/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xc900 } + }, +/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_HI, { 0xc904 } + }, +/* add.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xc906 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xc90800 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xc90c0000 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xc90a00 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xc90e0000 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xc90b00 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xc90f0000 } + }, +/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xc800 } + }, +/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_direct_QI, { 0xc804 } + }, +/* add.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xc806 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xc80800 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xc80c0000 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xc80a00 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xc80e0000 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xc80b00 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xc80f0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892e0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81ae0000 } + }, +/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812e0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832e0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ae0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ee0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852e0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ae0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ee0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ee0000 } + }, +/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872e0000 } + }, +/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87ae0000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882e00 } + }, +/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80ae00 } + }, +/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802e00 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822e0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ae0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ee0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842e0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ae0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ee0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ee0000 } + }, +/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862e0000 } + }, +/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86ae0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77400000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77440000 } + }, +/* add.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77460000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77480000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x774a0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x774b0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x774c0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x774e0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x774f0000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x764000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x764400 } + }, +/* add.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x764600 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76480000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x764a0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x764b0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x764c0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x764e0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x764f0000 } + }, +/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x88310000 } + }, +/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80b10000 } + }, +/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x80310000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82310000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82b10000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82f10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84310000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84b10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84f10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86f10000 } + }, +/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86310000 } + }, +/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86b10000 } + }, +/* adcf.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb91e } + }, +/* adcf.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb19e } + }, +/* adcf.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb11e } + }, +/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb31e00 } + }, +/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb51e0000 } + }, +/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb71e0000 } + }, +/* adcf.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb39e00 } + }, +/* adcf.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb59e0000 } + }, +/* adcf.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3de00 } + }, +/* adcf.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5de0000 } + }, +/* adcf.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7de0000 } + }, +/* adcf.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb79e0000 } + }, +/* adcf.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb81e } + }, +/* adcf.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb09e } + }, +/* adcf.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb01e } + }, +/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb21e00 } + }, +/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb41e0000 } + }, +/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb61e0000 } + }, +/* adcf.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb29e00 } + }, +/* adcf.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb49e0000 } + }, +/* adcf.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2de00 } + }, +/* adcf.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4de0000 } + }, +/* adcf.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6de0000 } + }, +/* adcf.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb69e0000 } + }, +/* adcf.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77e0 } + }, +/* adcf.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77e4 } + }, +/* adcf.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77e6 } + }, +/* adcf.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77e800 } + }, +/* adcf.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ec0000 } + }, +/* adcf.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ea00 } + }, +/* adcf.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ee0000 } + }, +/* adcf.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77eb00 } + }, +/* adcf.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ef0000 } + }, +/* adcf.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76e0 } + }, +/* adcf.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76e4 } + }, +/* adcf.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76e6 } + }, +/* adcf.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76e800 } + }, +/* adcf.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ec0000 } + }, +/* adcf.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ea00 } + }, +/* adcf.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ee0000 } + }, +/* adcf.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76eb00 } + }, +/* adcf.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ef0000 } + }, +/* abs.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91f } + }, +/* abs.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19f } + }, +/* abs.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11f } + }, +/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31f00 } + }, +/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51f0000 } + }, +/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71f0000 } + }, +/* abs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39f00 } + }, +/* abs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59f0000 } + }, +/* abs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3df00 } + }, +/* abs.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5df0000 } + }, +/* abs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7df0000 } + }, +/* abs.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79f0000 } + }, +/* abs.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81f } + }, +/* abs.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09f } + }, +/* abs.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01f } + }, +/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21f00 } + }, +/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41f0000 } + }, +/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61f0000 } + }, +/* abs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29f00 } + }, +/* abs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49f0000 } + }, +/* abs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2df00 } + }, +/* abs.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4df0000 } + }, +/* abs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6df0000 } + }, +/* abs.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69f0000 } + }, +/* abs.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77f0 } + }, +/* abs.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77f4 } + }, +/* abs.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77f6 } + }, +/* abs.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77f800 } + }, +/* abs.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77fc0000 } + }, +/* abs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77fa00 } + }, +/* abs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77fe0000 } + }, +/* abs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77fb00 } + }, +/* abs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ff0000 } + }, +/* abs.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76f0 } + }, +/* abs.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76f4 } + }, +/* abs.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76f6 } + }, +/* abs.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76f800 } + }, +/* abs.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76fc0000 } + }, +/* abs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76fa00 } + }, +/* abs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76fe0000 } + }, +/* abs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76fb00 } + }, +/* abs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 } + }, +/* add.w$Q #${Imm-12-s4},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, + & ifmt_add16_wQ_sp, { 0x7db0 } + }, +/* add.b$G #${Imm-16-QI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } }, + & ifmt_add16_b_G_sp, { 0x7ceb00 } + }, +/* add.w$G #${Imm-16-HI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } }, + & ifmt_add16_w_G_sp, { 0x7deb0000 } + }, +/* add.l$Q #${Imm3-S},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM3_S), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm3_Q, { 0x42 } + }, +/* add.l$S #${Imm-16-QI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm8_S, { 0xb60300 } + }, +/* add.l$G #${Imm-16-HI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm16_G, { 0xb6130000 } + }, +/* dadc.b #${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cee00 } + }, +/* dadc.w #${Imm-16-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } }, + & ifmt_add32_l_imm16_G, { 0x7dee0000 } + }, +/* dadc.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce6 } + }, +/* dadc.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de6 } + }, +/* dadd.b #${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cec00 } + }, +/* dadd.w #${Imm-16-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } }, + & ifmt_add32_l_imm16_G, { 0x7dec0000 } + }, +/* dadd.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce4 } + }, +/* dadd.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de4 } + }, +/* bm$cond16c c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16C), ' ', 'c', 0 } }, + & ifmt_bm16_c, { 0x7dd0 } + }, +/* bm$cond32 c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32), ' ', 'c', 0 } }, + & ifmt_bm32_c, { 0xd928 } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x0 } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x0 } + }, +/* brk2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x8 } + }, +/* btst:s ${Bit3-S},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (BIT3_S), ',', OP (DSP_8_U16), 0 } }, + & ifmt_btst_s, { 0xa0000 } + }, +/* dec.w ${Dst16An-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16AN_S), 0 } }, + & ifmt_dec16_w, { 0xf2 } + }, +/* div.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce100 } + }, +/* div.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de10000 } + }, +/* div.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb04300 } + }, +/* div.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb0530000 } + }, +/* divu.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce000 } + }, +/* divu.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de00000 } + }, +/* divu.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb00300 } + }, +/* divu.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb0130000 } + }, +/* divx.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce300 } + }, +/* divx.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de30000 } + }, +/* divx.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb24300 } + }, +/* divx.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb2530000 } + }, +/* dsbb.b #${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cef00 } + }, +/* dsbb.w #${Imm-16-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } }, + & ifmt_add32_l_imm16_G, { 0x7def0000 } + }, +/* dsbb.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce7 } + }, +/* dsbb.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de7 } + }, +/* dsub.b #${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_add32_l_imm8_S, { 0x7ced00 } + }, +/* dsub.w #${Imm-16-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', 'r', '0', 0 } }, + & ifmt_add32_l_imm16_G, { 0x7ded0000 } + }, +/* dsub.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce5 } + }, +/* dsub.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de5 } + }, +/* enter #${Dsp-16-u8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U8), 0 } }, + & ifmt_enter16, { 0x7cf200 } + }, +/* exitd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df2 } + }, +/* enter #${Dsp-8-u8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_8_U8), 0 } }, + & ifmt_enter32, { 0xec00 } + }, +/* exitd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xfc } + }, +/* fclr ${flags16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS16), 0 } }, + & ifmt_fclr16, { 0xeb05 } + }, +/* fset ${flags16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS16), 0 } }, + & ifmt_fclr16, { 0xeb04 } + }, +/* fclr ${flags32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS32), 0 } }, + & ifmt_fclr, { 0xd3e8 } + }, +/* fset ${flags32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS32), 0 } }, + & ifmt_fclr, { 0xd1e8 } + }, +/* inc.w ${Dst16An-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16AN_S), 0 } }, + & ifmt_dec16_w, { 0xb2 } + }, +/* freit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9f } + }, +/* int #${Dsp-10-u6} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_10_U6), 0 } }, + & ifmt_int16, { 0xebc0 } + }, +/* into */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xf6 } + }, +/* int #${Dsp-8-u6} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_8_U6), 0 } }, + & ifmt_int32, { 0xbe00 } + }, +/* into */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xbf } + }, +/* j$cond16j5 ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16J5), ' ', OP (LAB_8_8), 0 } }, + & ifmt_jcnd16_5, { 0x6800 } + }, +/* j$cond16j ${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16J), ' ', OP (LAB_16_8), 0 } }, + & ifmt_jcnd16, { 0x7dc000 } + }, +/* j$cond32j ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32J), ' ', OP (LAB_8_8), 0 } }, + & ifmt_jcnd32, { 0x8a00 } + }, +/* jmp.s ${Lab-5-3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_5_3), 0 } }, + & ifmt_jmp16_s, { 0x60 } + }, +/* jmp.b ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_8), 0 } }, + & ifmt_jmp16_b, { 0xfe00 } + }, +/* jmp.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xf40000 } + }, +/* jmp.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xfc000000 } + }, +/* jmps #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xee00 } + }, +/* jmp.s ${Lab32-jmp-s} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB32_JMP_S), 0 } }, + & ifmt_jmp32_s, { 0x4a } + }, +/* jmp.b ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_8), 0 } }, + & ifmt_jmp16_b, { 0xbb00 } + }, +/* jmp.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xce0000 } + }, +/* jmp.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xcc000000 } + }, +/* jmps #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xdc00 } + }, +/* jsr.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xf50000 } + }, +/* jsr.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xfd000000 } + }, +/* jsr.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xcf0000 } + }, +/* jsr.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xcd000000 } + }, +/* jsrs #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xef00 } + }, +/* jsrs #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xdd00 } + }, +/* ldc #${Imm-16-HI},${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR16), 0 } }, + & ifmt_ldc16_imm16, { 0xeb000000 } + }, +/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_ldc32_imm16_cr1, { 0xd5a80000 } + }, +/* ldc #${Dsp-16-u24},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR2_32), 0 } }, + & ifmt_ldc32_imm16_cr2, { 0xd5280000 } + }, +/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR3_UNPREFIXED_32), 0 } }, + & ifmt_ldc32_imm16_cr3, { 0xd5680000 } + }, +/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0x7cf00000 } + }, +/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0xb6c30000 } + }, +/* stctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0x7df00000 } + }, +/* stctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0xb6d30000 } + }, +/* ldipl #${Imm-13-u3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } }, + & ifmt_ldipl16_imm, { 0x7da0 } + }, +/* ldipl #${Imm-13-u3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } }, + & ifmt_ldipl16_imm, { 0xd5e8 } + }, +/* mov.b$S #${Imm-8-QI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '0', 0 } }, + & ifmt_jmps16, { 0xe200 } + }, +/* mov.b$S #${Imm-8-QI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '1', 0 } }, + & ifmt_jmps16, { 0xea00 } + }, +/* mov.w$S #${Imm-8-HI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xa20000 } + }, +/* mov.w$S #${Imm-8-HI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xaa0000 } + }, +/* mov.w$S #${Imm-8-HI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0x9c0000 } + }, +/* mov.w$S #${Imm-8-HI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0x9d0000 } + }, +/* mov.l$S #${Dsp-8-s24},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '0', 0 } }, + & ifmt_mov32_l_a0, { 0xbc000000 } + }, +/* mov.l$S #${Dsp-8-s24},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_S24), ',', 'a', '1', 0 } }, + & ifmt_mov32_l_a0, { 0xbd000000 } + }, +/* mov.b$S r0l,a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'a', '1', 0 } }, + & ifmt_brk16, { 0x34 } + }, +/* mov.b$S r0h,a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'h', ',', 'a', '0', 0 } }, + & ifmt_brk16, { 0x30 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x4 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xde } + }, +/* popc ${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), 0 } }, + & ifmt_popc16_imm16, { 0xeb03 } + }, +/* popc ${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_popc32_imm16_cr1, { 0xd3a8 } + }, +/* popc ${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), 0 } }, + & ifmt_popc32_imm16_cr2, { 0xd328 } + }, +/* pushc ${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), 0 } }, + & ifmt_popc16_imm16, { 0xeb02 } + }, +/* pushc ${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_popc32_imm16_cr1, { 0xd1a8 } + }, +/* pushc ${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), 0 } }, + & ifmt_popc32_imm16_cr2, { 0xd128 } + }, +/* popm ${Regsetpop} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPOP), 0 } }, + & ifmt_popm16, { 0xed00 } + }, +/* pushm ${Regsetpush} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPUSH), 0 } }, + & ifmt_pushm16, { 0xec00 } + }, +/* popm ${Regsetpop} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPOP), 0 } }, + & ifmt_popm16, { 0x8e00 } + }, +/* pushm ${Regsetpush} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPUSH), 0 } }, + & ifmt_pushm16, { 0x8f00 } + }, +/* push.b$G #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7ce200 } + }, +/* push.w$G #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7de20000 } + }, +/* push.b #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xae00 } + }, +/* push.w #${Imm-8-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_HI), 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xaf0000 } + }, +/* push.l #${Imm-16-SI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_SI), 0 } }, + & ifmt_push32_l_imm, { 0xb6530000 } + }, +/* reit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xfb } + }, +/* reit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9e } + }, +/* rmpa.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cf1 } + }, +/* rmpa.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df1 } + }, +/* rmpa.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb843 } + }, +/* rmpa.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb853 } + }, +/* rts */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xf3 } + }, +/* rts */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xdf } + }, +/* scmpu.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb8c3 } + }, +/* scmpu.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb8d3 } + }, +/* sha.l #${Imm-sh-12-s4},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeba0 } + }, +/* sha.l #${Imm-sh-12-s4},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xebb0 } + }, +/* sha.l r1h,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb21 } + }, +/* sha.l r1h,r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb31 } + }, +/* shl.l #${Imm-sh-12-s4},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeb80 } + }, +/* shl.l #${Imm-sh-12-s4},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeb90 } + }, +/* shl.l r1h,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb01 } + }, +/* shl.l r1h,r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb11 } + }, +/* sin.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb283 } + }, +/* sin.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb293 } + }, +/* smovb.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce9 } + }, +/* smovb.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de9 } + }, +/* smovb.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb683 } + }, +/* smovb.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb693 } + }, +/* smovf.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce8 } + }, +/* smovf.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de8 } + }, +/* smovf.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb083 } + }, +/* smovf.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb093 } + }, +/* smovu.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb883 } + }, +/* smovu.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb893 } + }, +/* sout.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb483 } + }, +/* sout.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb493 } + }, +/* sstr.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cea } + }, +/* sstr.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7dea } + }, +/* sstr.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb803 } + }, +/* sstr.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb813 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stzx16_imm8_imm8_r0h, { 0xdb0000 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 } + }, +/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 } + }, +/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx16_imm8_imm8_dsp8fb, { 0xde000000 } + }, +/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stzx16_imm8_imm8_abs16, { 0xdf000000 } + }, +/* und */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xff } + }, +/* und */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xff } + }, +/* wait */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df3 } + }, +/* wait */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb203 } + }, +/* exts.w r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cf3 } + }, +/* src-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x41 } + }, +/* dest-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9 } + }, +/* src-dest-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x49 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & m32c_cgen_ifld_table[M32C_##f] +static const CGEN_IFMT ifmt_add16_bQ_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) M32C_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE m32c_cgen_macro_insn_table[] = +{ +/* add.b:q #${Imm-12-s4},sp */ + { + -1, "add16-bQ-sp", "add.b:q", 16, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + m32c_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & m32c_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + m32c_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32c-opc.h b/external/gpl3/gdb/dist/opcodes/m32c-opc.h new file mode 100644 index 000000000000..6c8a4ad56079 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32c-opc.h @@ -0,0 +1,3244 @@ +/* Instruction opcode header for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32C_OPC_H +#define M32C_OPC_H + +/* -- opc.h */ + +/* Needed for RTL's 'ext' and 'trunc' operators. */ +#include "cgen/basic-modes.h" +#include "cgen/basic-ops.h" + +/* We can't use the default hash size because many bits are used by + operands. */ +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +#define CGEN_VERBOSE_ASSEMBLER_ERRORS +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +#define CGEN_ASM_HASH_SIZE 0xffff +#define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem)) + +/* -- */ +/* Enum declaration for m32c instruction types. */ +typedef enum cgen_insn_type { + M32C_INSN_INVALID, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI + , M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI + , M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI + , M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI + , M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI + , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI + , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI + , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI + , M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI + , M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI + , M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI + , M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI + , M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI + , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI + , M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI + , M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI + , M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI + , M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI + , M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI + , M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI + , M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI + , M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU_L_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_MULU_L_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_MULU_L_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_8_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_MULU_L_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_16_SB_RELATIVE_PREFIXED_SI + , M32C_INSN_MULU_L_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_MULU_L_DST32_24_24_ABSOLUTE_PREFIXED_SI + , M32C_INSN_MUL_L_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_MUL_L_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_MUL_L_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_8_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_MUL_L_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_16_SB_RELATIVE_PREFIXED_SI + , M32C_INSN_MUL_L_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_MUL_L_DST32_24_24_ABSOLUTE_PREFIXED_SI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI + , M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI + , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI + , M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI + , M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI + , M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI + , M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI + , M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI + , M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI + , M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI + , M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI + , M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI + , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI + , M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI + , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI + , M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI + , M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI + , M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI + , M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI + , M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI + , M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI + , M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI + , M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI + , M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI + , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI + , M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_20AR_SI_DST16_16_20_AN_RELATIVE_SI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI + , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_20AR_HI_DST16_16_20_AN_RELATIVE_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI + , M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI + , M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI + , M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI + , M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI + , M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI + , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI + , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI + , M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI + , M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI + , M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI + , M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT + , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE + , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED + , M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED + , M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT + , M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S + , M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE + , M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT + , M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED + , M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED + , M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED + , M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE + , M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT + , M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S + , M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED + , M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI + , M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI + , M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI + , M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI + , M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI + , M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI + , M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_WQ_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP + , M32C_INSN_ADD32_L_IMM3_Q, M32C_INSN_ADD32_L_IMM8_S, M32C_INSN_ADD32_L_IMM16_G, M32C_INSN_DADC16_B_IMM8 + , M32C_INSN_DADC16_W_IMM16, M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8 + , M32C_INSN_DADD16_W_IMM16, M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C + , M32C_INSN_BM32_C, M32C_INSN_BRK16, M32C_INSN_BRK32, M32C_INSN_BRK232 + , M32C_INSN_BTST_S, M32C_INSN_DEC16_W, M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI + , M32C_INSN_DIV32_B_IMM_16_QI, M32C_INSN_DIV32_W_IMM_16_HI, M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI + , M32C_INSN_DIVU32_B_IMM_16_QI, M32C_INSN_DIVU32_W_IMM_16_HI, M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI + , M32C_INSN_DIVX32_B_IMM_16_QI, M32C_INSN_DIVX32_W_IMM_16_HI, M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16 + , M32C_INSN_DSBB16_B_R0H_R0L, M32C_INSN_DSBB16_W_R1_R0, M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16 + , M32C_INSN_DSUB16_B_R0H_R0L, M32C_INSN_DSUB16_W_R1_R0, M32C_INSN_ENTER16, M32C_INSN_EXITD16 + , M32C_INSN_ENTER32, M32C_INSN_EXITD32, M32C_INSN_FCLR16, M32C_INSN_FSET16 + , M32C_INSN_FCLR, M32C_INSN_FSET, M32C_INSN_INC16_W, M32C_INSN_FREIT32 + , M32C_INSN_INT16, M32C_INSN_INTO16, M32C_INSN_INT32, M32C_INSN_INTO32 + , M32C_INSN_JCND16_5, M32C_INSN_JCND16, M32C_INSN_JCND32, M32C_INSN_JMP16_S + , M32C_INSN_JMP16_B, M32C_INSN_JMP16_W, M32C_INSN_JMP16_A, M32C_INSN_JMPS16 + , M32C_INSN_JMP32_S, M32C_INSN_JMP32_B, M32C_INSN_JMP32_W, M32C_INSN_JMP32_A + , M32C_INSN_JMPS32, M32C_INSN_JSR16_W, M32C_INSN_JSR16_A, M32C_INSN_JSR32_W + , M32C_INSN_JSR32_A, M32C_INSN_JSRS16, M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16 + , M32C_INSN_LDC32_IMM16_CR1, M32C_INSN_LDC32_IMM16_CR2, M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16 + , M32C_INSN_LDCTX32, M32C_INSN_STCTX16, M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM + , M32C_INSN_LDIPL32_IMM, M32C_INSN_MOV16_B_S_IMM_A0, M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0 + , M32C_INSN_MOV16_W_S_IMM_A1, M32C_INSN_MOV32_W_A0, M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0 + , M32C_INSN_MOV32_L_A1, M32C_INSN_MOV16_B_S_R0L_A1, M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16 + , M32C_INSN_NOP32, M32C_INSN_POPC16_IMM16, M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2 + , M32C_INSN_PUSHC16_IMM16, M32C_INSN_PUSHC32_IMM16_CR1, M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16 + , M32C_INSN_PUSHM16, M32C_INSN_POPM, M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM + , M32C_INSN_PUSH16_W_G_IMM, M32C_INSN_PUSH32_B_IMM, M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM + , M32C_INSN_REIT16, M32C_INSN_REIT32, M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W + , M32C_INSN_RMPA32_B, M32C_INSN_RMPA32_W, M32C_INSN_RTS16, M32C_INSN_RTS32 + , M32C_INSN_SCMPU_B, M32C_INSN_SCMPU_W, M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1 + , M32C_INSN_SHA16_L_R1H_R2R0, M32C_INSN_SHA16_L_R1H_R3R1, M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1 + , M32C_INSN_SHL16_L_R1H_R2R0, M32C_INSN_SHL16_L_R1H_R3R1, M32C_INSN_SIN32_B, M32C_INSN_SIN32_W + , M32C_INSN_SMOVB16_B, M32C_INSN_SMOVB16_W, M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W + , M32C_INSN_SMOVF16_B, M32C_INSN_SMOVF16_W, M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W + , M32C_INSN_SMOVU_B, M32C_INSN_SMOVU_W, M32C_INSN_SOUT_B, M32C_INSN_SOUT_W + , M32C_INSN_SSTR16_B, M32C_INSN_SSTR16_W, M32C_INSN_SSTR_B, M32C_INSN_SSTR_W + , M32C_INSN_STZX16_IMM8_IMM8_R0H, M32C_INSN_STZX16_IMM8_IMM8_R0L, M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB + , M32C_INSN_STZX16_IMM8_IMM8_ABS16, M32C_INSN_UND16, M32C_INSN_UND32, M32C_INSN_WAIT16 + , M32C_INSN_WAIT, M32C_INSN_EXTS16_W_R0, M32C_INSN_SRCIND, M32C_INSN_DESTIND + , M32C_INSN_SRCDESTIND +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID M32C_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) M32C_INSN_SRCDESTIND + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_0_1; + long f_0_2; + long f_0_3; + long f_0_4; + long f_1_3; + long f_2_2; + long f_3_4; + long f_3_1; + long f_4_1; + long f_4_3; + long f_4_4; + long f_4_6; + long f_5_1; + long f_5_3; + long f_6_2; + long f_7_1; + long f_8_1; + long f_8_2; + long f_8_3; + long f_8_4; + long f_8_8; + long f_9_3; + long f_9_1; + long f_10_1; + long f_10_2; + long f_10_3; + long f_11_1; + long f_12_1; + long f_12_2; + long f_12_3; + long f_12_4; + long f_12_6; + long f_13_3; + long f_14_1; + long f_14_2; + long f_15_1; + long f_16_1; + long f_16_2; + long f_16_4; + long f_16_8; + long f_18_1; + long f_18_2; + long f_18_3; + long f_20_1; + long f_20_3; + long f_20_2; + long f_20_4; + long f_21_3; + long f_24_2; + long f_24_8; + long f_32_16; + long f_src16_rn; + long f_src16_an; + long f_src32_an_unprefixed; + long f_src32_an_prefixed; + long f_src32_rn_unprefixed_QI; + long f_src32_rn_prefixed_QI; + long f_src32_rn_unprefixed_HI; + long f_src32_rn_prefixed_HI; + long f_src32_rn_unprefixed_SI; + long f_src32_rn_prefixed_SI; + long f_dst32_rn_ext_unprefixed; + long f_dst16_rn; + long f_dst16_rn_ext; + long f_dst16_rn_QI_s; + long f_dst16_an; + long f_dst16_an_s; + long f_dst32_an_unprefixed; + long f_dst32_an_prefixed; + long f_dst32_rn_unprefixed_QI; + long f_dst32_rn_prefixed_QI; + long f_dst32_rn_unprefixed_HI; + long f_dst32_rn_prefixed_HI; + long f_dst32_rn_unprefixed_SI; + long f_dst32_rn_prefixed_SI; + long f_dst16_1_S; + long f_imm_8_s4; + long f_imm_12_s4; + long f_imm_13_u3; + long f_imm_20_s4; + long f_imm1_S; + long f_imm3_S; + long f_dsp_8_u6; + long f_dsp_8_u8; + long f_dsp_8_s8; + long f_dsp_10_u6; + long f_dsp_16_u8; + long f_dsp_16_s8; + long f_dsp_24_u8; + long f_dsp_24_s8; + long f_dsp_32_u8; + long f_dsp_32_s8; + long f_dsp_40_u8; + long f_dsp_40_s8; + long f_dsp_48_u8; + long f_dsp_48_s8; + long f_dsp_56_u8; + long f_dsp_56_s8; + long f_dsp_64_u8; + long f_dsp_64_s8; + long f_dsp_8_u16; + long f_dsp_8_s16; + long f_dsp_16_u16; + long f_dsp_16_s16; + long f_dsp_24_u16; + long f_dsp_24_s16; + long f_dsp_32_u16; + long f_dsp_32_s16; + long f_dsp_40_u16; + long f_dsp_40_s16; + long f_dsp_48_u16; + long f_dsp_48_s16; + long f_dsp_64_u16; + long f_dsp_8_s24; + long f_dsp_8_u24; + long f_dsp_16_u24; + long f_dsp_24_u24; + long f_dsp_32_u24; + long f_dsp_40_u20; + long f_dsp_40_u24; + long f_dsp_40_s32; + long f_dsp_48_u20; + long f_dsp_48_u24; + long f_dsp_16_s32; + long f_dsp_24_s32; + long f_dsp_32_s32; + long f_dsp_48_u32; + long f_dsp_48_s32; + long f_dsp_56_s16; + long f_dsp_64_s16; + long f_bitno16_S; + long f_bitno32_prefixed; + long f_bitno32_unprefixed; + long f_bitbase16_u11_S; + long f_bitbase32_16_u11_unprefixed; + long f_bitbase32_16_s11_unprefixed; + long f_bitbase32_16_u19_unprefixed; + long f_bitbase32_16_s19_unprefixed; + long f_bitbase32_16_u27_unprefixed; + long f_bitbase32_24_u11_prefixed; + long f_bitbase32_24_s11_prefixed; + long f_bitbase32_24_u19_prefixed; + long f_bitbase32_24_s19_prefixed; + long f_bitbase32_24_u27_prefixed; + long f_lab_5_3; + long f_lab32_jmp_s; + long f_lab_8_8; + long f_lab_8_16; + long f_lab_8_24; + long f_lab_16_8; + long f_lab_24_8; + long f_lab_32_8; + long f_lab_40_8; + long f_cond16; + long f_cond16j_5; + long f_cond32; + long f_cond32j; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* M32C_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/m32r-asm.c b/external/gpl3/gdb/dist/opcodes/m32r-asm.c new file mode 100644 index 000000000000..eff6da093073 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-asm.c @@ -0,0 +1,736 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +/* Handle '#' prefixes (i.e. skip over them). */ + +static const char * +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '#') + ++*strp; + return NULL; +} + +/* Handle shigh(), high(). */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "high(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp, "shigh(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value += 0x8000; + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in a signed context. Also handle sda(). + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = ((value & 0xffff) ^ 0x8000) - 0x8000; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "sda(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, + NULL, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + *valuep = value; + return errmsg; + } + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in an unsigned context. + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* -- */ + +const char * m32r_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +m32r_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case M32R_OPERAND_ACC : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_acc); + break; + case M32R_OPERAND_ACCD : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accd); + break; + case M32R_OPERAND_ACCS : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_h_accums, & fields->f_accs); + break; + case M32R_OPERAND_DCR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r1); + break; + case M32R_OPERAND_DISP16 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value); + fields->f_disp16 = value; + } + break; + case M32R_OPERAND_DISP24 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value); + fields->f_disp24 = value; + } + break; + case M32R_OPERAND_DISP8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value); + fields->f_disp8 = value; + } + break; + case M32R_OPERAND_DR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); + break; + case M32R_OPERAND_HASH : + errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, (long *) (& junk)); + break; + case M32R_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, (unsigned long *) (& fields->f_hi16)); + break; + case M32R_OPERAND_IMM1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_IMM1, (unsigned long *) (& fields->f_imm1)); + break; + case M32R_OPERAND_SCR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2); + break; + case M32R_OPERAND_SIMM16 : + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, (long *) (& fields->f_simm16)); + break; + case M32R_OPERAND_SIMM8 : + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, (long *) (& fields->f_simm8)); + break; + case M32R_OPERAND_SLO16 : + errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, (long *) (& fields->f_simm16)); + break; + case M32R_OPERAND_SR : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); + break; + case M32R_OPERAND_SRC1 : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); + break; + case M32R_OPERAND_SRC2 : + errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); + break; + case M32R_OPERAND_UIMM16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16)); + break; + case M32R_OPERAND_UIMM24 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); + fields->f_uimm24 = value; + } + break; + case M32R_OPERAND_UIMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, (unsigned long *) (& fields->f_uimm3)); + break; + case M32R_OPERAND_UIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, (unsigned long *) (& fields->f_uimm4)); + break; + case M32R_OPERAND_UIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, (unsigned long *) (& fields->f_uimm5)); + break; + case M32R_OPERAND_UIMM8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, (unsigned long *) (& fields->f_uimm8)); + break; + case M32R_OPERAND_ULO16 : + errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, (unsigned long *) (& fields->f_uimm16)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const m32r_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +m32r_cgen_init_asm (CGEN_CPU_DESC cd) +{ + m32r_cgen_init_opcode_table (cd); + m32r_cgen_init_ibld_table (cd); + cd->parse_handlers = & m32r_cgen_parse_handlers[0]; + cd->parse_operand = m32r_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by m32r_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +m32r_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +m32r_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! m32r_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/m32r-desc.c b/external/gpl3/gdb/dist/opcodes/m32r-desc.c new file mode 100644 index 000000000000..599cc9f8a599 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-desc.c @@ -0,0 +1,1527 @@ +/* CPU data for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "m32r", MACH_M32R }, + { "m32rx", MACH_M32RX }, + { "m32r2", MACH_M32R2 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "m32r", ISA_M32R }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", PIPE_NONE }, + { "O", PIPE_O }, + { "S", PIPE_S }, + { "OS", PIPE_OS }, + { "O_OS", PIPE_O_OS }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, + { "SPECIAL", &bool_attr[0], &bool_attr[0] }, + { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] }, + { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA m32r_cgen_isa_table[] = { + { "m32r", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH m32r_cgen_mach_table[] = { + { "m32r", "m32r", MACH_M32R, 0 }, + { "m32rx", "m32rx", MACH_M32RX, 0 }, + { "m32r2", "m32r2", MACH_M32R2, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = +{ + { "fp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_gr_names = +{ + & m32r_cgen_opval_gr_names_entries[0], + 19, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = +{ + { "psw", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "spi", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "spu", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "evb", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_cr_names = +{ + & m32r_cgen_opval_cr_names_entries[0], + 24, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = +{ + { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD m32r_cgen_opval_h_accums = +{ + & m32r_cgen_opval_h_accums_entries[0], + 2, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY m32r_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & m32r_cgen_ifld_table[0]; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & m32r_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of m32r_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & m32r_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */ + +static void +m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & m32r_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (m32r_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = m32r_cgen_rebuild_tables; + m32r_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +m32r_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/m32r-desc.h b/external/gpl3/gdb/dist/opcodes/m32r-desc.h new file mode 100644 index 000000000000..1140e7e8688f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-desc.h @@ -0,0 +1,283 @@ +/* CPU data header for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32R_CPU_H +#define M32R_CPU_H + +#define CGEN_ARCH m32r + +/* Given symbol S, return m32r_cgen_. */ +#define CGEN_SYM(s) m32r##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_M32RBF +#define HAVE_CPU_M32RXF +#define HAVE_CPU_M32R2F + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 + +/* Enums. */ + +/* Enum declaration for insn format enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_10, OP1_11 + , OP1_12, OP1_13, OP1_14, OP1_15 +} INSN_OP1; + +/* Enum declaration for op2 enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_10, OP2_11 + , OP2_12, OP2_13, OP2_14, OP2_15 +} INSN_OP2; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 + , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 + , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 + , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 + , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 + , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 + , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 + , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 + , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 + , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 +} CR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 + , MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_M32R, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum pipe_attr { + PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS + , PIPE_O_OS +} PIPE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS + , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) + +/* Enum declaration for m32r ifield types. */ +typedef enum ifield_type { + M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 + , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 + , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 + , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 + , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 + , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS + , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 + , M32R_F_IMM1, M32R_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) M32R_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for m32r hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 + , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM + , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW + , HW_H_BBPSW, HW_H_LOCK, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) + +/* Enum declaration for m32r operand types. */ +typedef enum cgen_operand_type { + M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 + , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 + , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 + , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD + , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 + , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 + , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM + , M32R_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 28 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 11 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL + , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FILL_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) +#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld m32r_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD m32r_cgen_opval_gr_names; +extern CGEN_KEYWORD m32r_cgen_opval_cr_names; +extern CGEN_KEYWORD m32r_cgen_opval_h_accums; + +extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; + + + +#endif /* M32R_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/m32r-dis.c b/external/gpl3/gdb/dist/opcodes/m32r-dis.c new file mode 100644 index 000000000000..25b4127524e0 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-dis.c @@ -0,0 +1,700 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +/* Print signed operands with '#' prefixes. */ + +static void +print_signed_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "#"); + (*info->fprintf_func) (info->stream, "%ld", value); +} + +/* Print unsigned operands with '#' prefixes. */ + +static void +print_unsigned_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "#"); + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Handle '#' prefixes as operands. */ + +static void +print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "#"); +} + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN my_print_insn + +static int +my_print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info) +{ + bfd_byte buffer[CGEN_MAX_INSN_SIZE]; + bfd_byte *buf = buffer; + int status; + int buflen = (pc & 3) == 0 ? 4 : 2; + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; + bfd_byte *x; + + /* Read the base part of the insn. */ + + status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0), + buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* 32 bit insn? */ + x = (big_p ? &buf[0] : &buf[3]); + if ((pc & 3) == 0 && (*x & 0x80) != 0) + return print_insn (cd, pc, info, buf, buflen); + + /* Print the first insn. */ + if ((pc & 3) == 0) + { + buf += (big_p ? 0 : 2); + if (print_insn (cd, pc, info, buf, 2) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + buf += (big_p ? 2 : -2); + } + + x = (big_p ? &buf[0] : &buf[1]); + if (*x & 0x80) + { + /* Parallel. */ + (*info->fprintf_func) (info->stream, " || "); + *x &= 0x7f; + } + else + (*info->fprintf_func) (info->stream, " -> "); + + /* The "& 3" is to pass a consistent address. + Parallel insns arguably both begin on the word boundary. + Also, branch insns are calculated relative to the word boundary. */ + if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + + return (pc & 3) ? 2 : 4; +} + +/* -- */ + +void m32r_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +m32r_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case M32R_OPERAND_ACC : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0); + break; + case M32R_OPERAND_ACCD : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0); + break; + case M32R_OPERAND_ACCS : + print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0); + break; + case M32R_OPERAND_DCR : + print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0); + break; + case M32R_OPERAND_DISP16 : + print_address (cd, info, fields->f_disp16, 0|(1<f_disp24, 0|(1<f_disp8, 0|(1<f_r1, 0); + break; + case M32R_OPERAND_HASH : + print_hash (cd, info, 0, 0|(1<f_hi16, 0|(1<f_imm1, 0, pc, length); + break; + case M32R_OPERAND_SCR : + print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0); + break; + case M32R_OPERAND_SIMM16 : + print_signed_with_hash_prefix (cd, info, fields->f_simm16, 0|(1<f_simm8, 0|(1<f_simm16, 0|(1<f_r2, 0); + break; + case M32R_OPERAND_SRC1 : + print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); + break; + case M32R_OPERAND_SRC2 : + print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0); + break; + case M32R_OPERAND_UIMM16 : + print_unsigned_with_hash_prefix (cd, info, fields->f_uimm16, 0, pc, length); + break; + case M32R_OPERAND_UIMM24 : + print_address (cd, info, fields->f_uimm24, 0|(1<f_uimm3, 0, pc, length); + break; + case M32R_OPERAND_UIMM4 : + print_unsigned_with_hash_prefix (cd, info, fields->f_uimm4, 0, pc, length); + break; + case M32R_OPERAND_UIMM5 : + print_unsigned_with_hash_prefix (cd, info, fields->f_uimm5, 0, pc, length); + break; + case M32R_OPERAND_UIMM8 : + print_unsigned_with_hash_prefix (cd, info, fields->f_uimm8, 0, pc, length); + break; + case M32R_OPERAND_ULO16 : + print_normal (cd, info, fields->f_uimm16, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const m32r_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +m32r_cgen_init_dis (CGEN_CPU_DESC cd) +{ + m32r_cgen_init_opcode_table (cd); + m32r_cgen_init_ibld_table (cd); + cd->print_handlers = & m32r_cgen_print_handlers[0]; + cd->print_operand = m32r_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! m32r_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_m32r (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_m32r +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + m32r_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32r-ibld.c b/external/gpl3/gdb/dist/opcodes/m32r-ibld.c new file mode 100644 index 000000000000..bb8cc07495bf --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-ibld.c @@ -0,0 +1,1220 @@ +/* Instruction building/extraction support for m32r. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * m32r_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +m32r_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32R_OPERAND_ACC : + errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer); + break; + case M32R_OPERAND_ACCD : + errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer); + break; + case M32R_OPERAND_ACCS : + errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer); + break; + case M32R_OPERAND_DCR : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_DISP16 : + { + long value = fields->f_disp16; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp24; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp8; + value = ((SI) (((value) - (((pc) & (-4))))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + errmsg = insert_normal (cd, fields->f_hi16, 0|(1<f_imm1; + value = ((value) - (1)); + errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer); + } + break; + case M32R_OPERAND_SCR : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SIMM16 : + errmsg = insert_normal (cd, fields->f_simm16, 0|(1<f_simm8, 0|(1<f_simm16, 0|(1<f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SRC1 : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_SRC2 : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM24 : + errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<f_uimm3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM4 : + errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM5 : + errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer); + break; + case M32R_OPERAND_UIMM8 : + errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32R_OPERAND_ULO16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int m32r_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +m32r_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32R_OPERAND_ACC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc); + break; + case M32R_OPERAND_ACCD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd); + break; + case M32R_OPERAND_ACCS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs); + break; + case M32R_OPERAND_DCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_DISP16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp16 = value; + } + break; + case M32R_OPERAND_DISP24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp24 = value; + } + break; + case M32R_OPERAND_DISP8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp8 = value; + } + break; + case M32R_OPERAND_DR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_hi16); + break; + case M32R_OPERAND_IMM1 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value); + value = ((value) + (1)); + fields->f_imm1 = value; + } + break; + case M32R_OPERAND_SCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_SIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case M32R_OPERAND_SIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm8); + break; + case M32R_OPERAND_SLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case M32R_OPERAND_SR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_SRC1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); + break; + case M32R_OPERAND_SRC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); + break; + case M32R_OPERAND_UIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case M32R_OPERAND_UIMM24 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_uimm24); + break; + case M32R_OPERAND_UIMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3); + break; + case M32R_OPERAND_UIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); + break; + case M32R_OPERAND_UIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); + break; + case M32R_OPERAND_UIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8); + break; + case M32R_OPERAND_ULO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const m32r_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const m32r_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case M32R_OPERAND_ACC : + value = fields->f_acc; + break; + case M32R_OPERAND_ACCD : + value = fields->f_accd; + break; + case M32R_OPERAND_ACCS : + value = fields->f_accs; + break; + case M32R_OPERAND_DCR : + value = fields->f_r1; + break; + case M32R_OPERAND_DISP16 : + value = fields->f_disp16; + break; + case M32R_OPERAND_DISP24 : + value = fields->f_disp24; + break; + case M32R_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case M32R_OPERAND_DR : + value = fields->f_r1; + break; + case M32R_OPERAND_HASH : + value = 0; + break; + case M32R_OPERAND_HI16 : + value = fields->f_hi16; + break; + case M32R_OPERAND_IMM1 : + value = fields->f_imm1; + break; + case M32R_OPERAND_SCR : + value = fields->f_r2; + break; + case M32R_OPERAND_SIMM16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case M32R_OPERAND_SLO16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SR : + value = fields->f_r2; + break; + case M32R_OPERAND_SRC1 : + value = fields->f_r1; + break; + case M32R_OPERAND_SRC2 : + value = fields->f_r2; + break; + case M32R_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case M32R_OPERAND_UIMM24 : + value = fields->f_uimm24; + break; + case M32R_OPERAND_UIMM3 : + value = fields->f_uimm3; + break; + case M32R_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case M32R_OPERAND_UIMM5 : + value = fields->f_uimm5; + break; + case M32R_OPERAND_UIMM8 : + value = fields->f_uimm8; + break; + case M32R_OPERAND_ULO16 : + value = fields->f_uimm16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case M32R_OPERAND_ACC : + value = fields->f_acc; + break; + case M32R_OPERAND_ACCD : + value = fields->f_accd; + break; + case M32R_OPERAND_ACCS : + value = fields->f_accs; + break; + case M32R_OPERAND_DCR : + value = fields->f_r1; + break; + case M32R_OPERAND_DISP16 : + value = fields->f_disp16; + break; + case M32R_OPERAND_DISP24 : + value = fields->f_disp24; + break; + case M32R_OPERAND_DISP8 : + value = fields->f_disp8; + break; + case M32R_OPERAND_DR : + value = fields->f_r1; + break; + case M32R_OPERAND_HASH : + value = 0; + break; + case M32R_OPERAND_HI16 : + value = fields->f_hi16; + break; + case M32R_OPERAND_IMM1 : + value = fields->f_imm1; + break; + case M32R_OPERAND_SCR : + value = fields->f_r2; + break; + case M32R_OPERAND_SIMM16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case M32R_OPERAND_SLO16 : + value = fields->f_simm16; + break; + case M32R_OPERAND_SR : + value = fields->f_r2; + break; + case M32R_OPERAND_SRC1 : + value = fields->f_r1; + break; + case M32R_OPERAND_SRC2 : + value = fields->f_r2; + break; + case M32R_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case M32R_OPERAND_UIMM24 : + value = fields->f_uimm24; + break; + case M32R_OPERAND_UIMM3 : + value = fields->f_uimm3; + break; + case M32R_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case M32R_OPERAND_UIMM5 : + value = fields->f_uimm5; + break; + case M32R_OPERAND_UIMM8 : + value = fields->f_uimm8; + break; + case M32R_OPERAND_ULO16 : + value = fields->f_uimm16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_UIMM3 : + fields->f_uimm3 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_UIMM8 : + fields->f_uimm8 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_HASH : + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_UIMM3 : + fields->f_uimm3 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_UIMM8 : + fields->f_uimm8 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & m32r_cgen_insert_handlers[0]; + cd->extract_handlers = & m32r_cgen_extract_handlers[0]; + + cd->insert_operand = m32r_cgen_insert_operand; + cd->extract_operand = m32r_cgen_extract_operand; + + cd->get_int_operand = m32r_cgen_get_int_operand; + cd->set_int_operand = m32r_cgen_set_int_operand; + cd->get_vma_operand = m32r_cgen_get_vma_operand; + cd->set_vma_operand = m32r_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32r-opc.c b/external/gpl3/gdb/dist/opcodes/m32r-opc.c new file mode 100644 index 000000000000..fdc9f50ed863 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-opc.c @@ -0,0 +1,1808 @@ +/* Instruction opcode table for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +unsigned int +m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value) +{ + unsigned int x; + + if (value & 0xffff0000) /* 32bit instructions. */ + value = (value >> 16) & 0xffff; + + x = (value >> 8) & 0xf0; + if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) + return x; + + if (x == 0x70 || x == 0xf0) + return x | ((value >> 8) & 0x0f); + + if (x == 0x30) + return x | ((value & 0x70) >> 4); + else + return x | ((value & 0xf0) >> 4); +} + +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & m32r_cgen_ifld_table[M32R_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_and3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_or3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addv3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc8 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc24 ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpz ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jc ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_machi_a ATTRIBUTE_UNUSED = { + 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfachi ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfachi_a ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvfc ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtachi ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtachi_a ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mvtc ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_dsi ATTRIBUTE_UNUSED = { + 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_seth ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slli ATTRIBUTE_UNUSED = { + 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_d ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_satb ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrpsw ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bset ATTRIBUTE_UNUSED = { + 32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = { + 16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) M32R_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xa0 } + }, +/* add3 $dr,$sr,$hash$slo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, + & ifmt_add3, { 0x80a00000 } + }, +/* and $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xc0 } + }, +/* and3 $dr,$sr,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, + & ifmt_and3, { 0x80c00000 } + }, +/* or $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xe0 } + }, +/* or3 $dr,$sr,$hash$ulo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, + & ifmt_or3, { 0x80e00000 } + }, +/* xor $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xd0 } + }, +/* xor3 $dr,$sr,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, + & ifmt_and3, { 0x80d00000 } + }, +/* addi $dr,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, + & ifmt_addi, { 0x4000 } + }, +/* addv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x80 } + }, +/* addv3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x80800000 } + }, +/* addx $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x90 } + }, +/* bc.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7c00 } + }, +/* bc.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfc000000 } + }, +/* beq $src1,$src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beq, { 0xb0000000 } + }, +/* beqz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0800000 } + }, +/* bgez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0b00000 } + }, +/* bgtz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0d00000 } + }, +/* blez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0c00000 } + }, +/* bltz $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0a00000 } + }, +/* bnez $src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beqz, { 0xb0900000 } + }, +/* bl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7e00 } + }, +/* bl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfe000000 } + }, +/* bcl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7800 } + }, +/* bcl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xf8000000 } + }, +/* bnc.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7d00 } + }, +/* bnc.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xfd000000 } + }, +/* bne $src1,$src2,$disp16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, + & ifmt_beq, { 0xb0100000 } + }, +/* bra.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7f00 } + }, +/* bra.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xff000000 } + }, +/* bncl.s $disp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP8), 0 } }, + & ifmt_bc8, { 0x7900 } + }, +/* bncl.l $disp24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP24), 0 } }, + & ifmt_bc24, { 0xf9000000 } + }, +/* cmp $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x40 } + }, +/* cmpi $src2,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, + & ifmt_cmpi, { 0x80400000 } + }, +/* cmpu $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50 } + }, +/* cmpui $src2,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, + & ifmt_cmpi, { 0x80500000 } + }, +/* cmpeq $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x60 } + }, +/* cmpz $src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), 0 } }, + & ifmt_cmpz, { 0x70 } + }, +/* div $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90000000 } + }, +/* divu $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90100000 } + }, +/* rem $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90200000 } + }, +/* remu $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90300000 } + }, +/* remh $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90200010 } + }, +/* remuh $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90300010 } + }, +/* remb $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90200018 } + }, +/* remub $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90300018 } + }, +/* divuh $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90100010 } + }, +/* divb $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90000018 } + }, +/* divub $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90100018 } + }, +/* divh $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_div, { 0x90000010 } + }, +/* jc $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1cc0 } + }, +/* jnc $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1dc0 } + }, +/* jl $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1ec0 } + }, +/* jmp $sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), 0 } }, + & ifmt_jc, { 0x1fc0 } + }, +/* ld $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20c0 } + }, +/* ld $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0c00000 } + }, +/* ldb $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x2080 } + }, +/* ldb $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0800000 } + }, +/* ldh $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20a0 } + }, +/* ldh $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0a00000 } + }, +/* ldub $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x2090 } + }, +/* ldub $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0900000 } + }, +/* lduh $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20b0 } + }, +/* lduh $dr,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_add3, { 0xa0b00000 } + }, +/* ld $dr,@$sr+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, + & ifmt_add, { 0x20e0 } + }, +/* ld24 $dr,$uimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, + & ifmt_ld24, { 0xe0000000 } + }, +/* ldi8 $dr,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, + & ifmt_addi, { 0x6000 } + }, +/* ldi16 $dr,$hash$slo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, + & ifmt_ldi16, { 0x90f00000 } + }, +/* lock $dr,@$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, + & ifmt_add, { 0x20d0 } + }, +/* machi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3040 } + }, +/* machi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3040 } + }, +/* maclo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3050 } + }, +/* maclo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3050 } + }, +/* macwhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3060 } + }, +/* macwhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3060 } + }, +/* macwlo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3070 } + }, +/* macwlo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3070 } + }, +/* mul $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1060 } + }, +/* mulhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3000 } + }, +/* mulhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3000 } + }, +/* mullo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3010 } + }, +/* mullo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3010 } + }, +/* mulwhi $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3020 } + }, +/* mulwhi $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3020 } + }, +/* mulwlo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x3030 } + }, +/* mulwlo $src1,$src2,$acc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, + & ifmt_machi_a, { 0x3030 } + }, +/* mv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1080 } + }, +/* mvfachi $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f0 } + }, +/* mvfachi $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f0 } + }, +/* mvfaclo $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f1 } + }, +/* mvfaclo $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f1 } + }, +/* mvfacmi $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_mvfachi, { 0x50f2 } + }, +/* mvfacmi $dr,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, + & ifmt_mvfachi_a, { 0x50f2 } + }, +/* mvfc $dr,$scr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, + & ifmt_mvfc, { 0x1090 } + }, +/* mvtachi $src1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), 0 } }, + & ifmt_mvtachi, { 0x5070 } + }, +/* mvtachi $src1,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, + & ifmt_mvtachi_a, { 0x5070 } + }, +/* mvtaclo $src1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), 0 } }, + & ifmt_mvtachi, { 0x5071 } + }, +/* mvtaclo $src1,$accs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, + & ifmt_mvtachi_a, { 0x5071 } + }, +/* mvtc $sr,$dcr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, + & ifmt_mvtc, { 0x10a0 } + }, +/* neg $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x30 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7000 } + }, +/* not $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0xb0 } + }, +/* rac */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x5090 } + }, +/* rac $accd,$accs,$imm1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, + & ifmt_rac_dsi, { 0x5090 } + }, +/* rach */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x5080 } + }, +/* rach $accd,$accs,$imm1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, + & ifmt_rac_dsi, { 0x5080 } + }, +/* rte */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x10d6 } + }, +/* seth $dr,$hash$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, + & ifmt_seth, { 0xd0c00000 } + }, +/* sll $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1040 } + }, +/* sll3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90c00000 } + }, +/* slli $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5040 } + }, +/* sra $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1020 } + }, +/* sra3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90a00000 } + }, +/* srai $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5020 } + }, +/* srl $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x1000 } + }, +/* srl3 $dr,$sr,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, + & ifmt_addv3, { 0x90800000 } + }, +/* srli $dr,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, + & ifmt_slli, { 0x5000 } + }, +/* st $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2040 } + }, +/* st $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0400000 } + }, +/* stb $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2000 } + }, +/* stb $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0000000 } + }, +/* sth $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2020 } + }, +/* sth $src1,@($slo16,$src2) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, + & ifmt_st_d, { 0xa0200000 } + }, +/* st $src1,@+$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2060 } + }, +/* sth $src1,@$src2+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } }, + & ifmt_cmp, { 0x2030 } + }, +/* stb $src1,@$src2+ */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } }, + & ifmt_cmp, { 0x2010 } + }, +/* st $src1,@-$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2070 } + }, +/* sub $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x20 } + }, +/* subv $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x0 } + }, +/* subx $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_add, { 0x10 } + }, +/* trap $uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM4), 0 } }, + & ifmt_trap, { 0x10f0 } + }, +/* unlock $src1,@$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x2050 } + }, +/* satb $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600300 } + }, +/* sath $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600200 } + }, +/* sat $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_satb, { 0x80600000 } + }, +/* pcmpbz $src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC2), 0 } }, + & ifmt_cmpz, { 0x370 } + }, +/* sadd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x50e4 } + }, +/* macwu1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50b0 } + }, +/* msblo $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50d0 } + }, +/* mulwu1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50a0 } + }, +/* maclh1 $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_cmp, { 0x50c0 } + }, +/* sc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7401 } + }, +/* snc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x7501 } + }, +/* clrpsw $uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM8), 0 } }, + & ifmt_clrpsw, { 0x7200 } + }, +/* setpsw $uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM8), 0 } }, + & ifmt_clrpsw, { 0x7100 } + }, +/* bset $uimm3,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_bset, { 0xa0600000 } + }, +/* bclr $uimm3,@($slo16,$sr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, + & ifmt_bset, { 0xa0700000 } + }, +/* btst $uimm3,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } }, + & ifmt_btst, { 0xf0 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & m32r_cgen_ifld_table[M32R_##f] +static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bl8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bl24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcl8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcl24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnc8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnc24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bncl8r ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bncl24r ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ld_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldb_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldb_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldh_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldh_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldub_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldub_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lduh_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lduh_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pop ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi8a ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = { + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = { + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = { + 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = { + 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = { + 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) M32R_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE m32r_cgen_macro_insn_table[] = +{ +/* bc $disp8 */ + { + -1, "bc8r", "bc", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + m32r_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & m32r_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + m32r_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/m32r-opc.h b/external/gpl3/gdb/dist/opcodes/m32r-opc.h new file mode 100644 index 000000000000..988eff94e44c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-opc.h @@ -0,0 +1,144 @@ +/* Instruction opcode header for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32R_OPC_H +#define M32R_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 256 +#undef CGEN_DIS_HASH +#if 0 +#define X(b) (((unsigned char *) (b))[0] & 0xf0) +#define CGEN_DIS_HASH(buffer, value) \ +(X (buffer) | \ + (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ + : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ + : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ + : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) +#else +#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value) +extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT); +#endif + +/* -- */ +/* Enum declaration for m32r instruction types. */ +typedef enum cgen_insn_type { + M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND + , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR + , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3 + , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ + , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ + , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24 + , M32R_INSN_BCL8, M32R_INSN_BCL24, M32R_INSN_BNC8, M32R_INSN_BNC24 + , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8 + , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU + , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV + , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH + , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH + , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC + , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD + , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH + , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH + , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8 + , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A + , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A + , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI + , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI + , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV + , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A + , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI + , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC + , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC + , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE + , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI + , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL + , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D + , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D + , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS + , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP + , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT + , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO + , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC + , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR + , M32R_INSN_BTST +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID M32R_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) M32R_INSN_BTST + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_op1; + long f_op2; + long f_cond; + long f_r1; + long f_r2; + long f_simm8; + long f_simm16; + long f_shift_op2; + long f_uimm3; + long f_uimm4; + long f_uimm5; + long f_uimm8; + long f_uimm16; + long f_uimm24; + long f_hi16; + long f_disp8; + long f_disp16; + long f_disp24; + long f_op23; + long f_op3; + long f_acc; + long f_accs; + long f_accd; + long f_bits67; + long f_bit4; + long f_bit14; + long f_imm1; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* M32R_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/m32r-opinst.c b/external/gpl3/gdb/dist/opcodes/m32r-opinst.c new file mode 100644 index 000000000000..3814be894c16 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m32r-opinst.c @@ -0,0 +1,762 @@ +/* Semantic operand instances for m32r. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32r-desc.h" +#include "m32r-opc.h" + +/* Operand references. */ + +#define OP_ENT(op) M32R_OPERAND_##op +#define INPUT CGEN_OPINST_INPUT +#define OUTPUT CGEN_OPINST_OUTPUT +#define END CGEN_OPINST_END +#define COND_REF CGEN_OPINST_COND_REF + +static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_or3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addv_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addv3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_addx_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bc8_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bc24_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_beq_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_beqz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bl8_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bl24_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bcl8_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bcl24_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bra8_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bra24_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmpi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmpz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_div_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jmp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_add__SI_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_add__SI_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldh_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldh_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_HI_add__SI_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_plus_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld24_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldi8_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldi16_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lock_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machi_a_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mulhi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mulhi_a_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mv_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvfachi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvfachi_a_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvfc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvtachi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvtachi_a_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mvtc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_nop_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rac_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rac_dsi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 }, + { INPUT, "imm1", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (IMM1), 0, 0 }, + { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rte_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 }, + { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_seth_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "hi16", HW_H_HI16, CGEN_MODE_UINT, OP_ENT (HI16), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sll3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_slli_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM5), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_add__SI_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_QI_add__SI_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sth_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sth_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_HI_add__SI_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_plus_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sth_plus_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_plus_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_trap_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { INPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 }, + { OUTPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 }, + { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_unlock_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, COND_REF }, + { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_satb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sat_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF }, + { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sadd_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_macwu1_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mulwu1_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_clrpsw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM8), 0, 0 }, + { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_setpsw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM8), 0, 0 }, + { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bset_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_add__SI_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 }, + { OUTPUT, "h_memory_QI_add__SI_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_btst_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, + { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 }, + { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +#undef OP_ENT +#undef INPUT +#undef OUTPUT +#undef END +#undef COND_REF + +/* Operand instance lookup table. */ + +static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = { + 0, + & sfmt_add_ops[0], + & sfmt_add3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_add_ops[0], + & sfmt_or3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_addi_ops[0], + & sfmt_addv_ops[0], + & sfmt_addv3_ops[0], + & sfmt_addx_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_bl8_ops[0], + & sfmt_bl24_ops[0], + & sfmt_bcl8_ops[0], + & sfmt_bcl24_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_bra8_ops[0], + & sfmt_bra24_ops[0], + & sfmt_bcl8_ops[0], + & sfmt_bcl24_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpz_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_jc_ops[0], + & sfmt_jc_ops[0], + & sfmt_jl_ops[0], + & sfmt_jmp_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ldb_ops[0], + & sfmt_ldb_d_ops[0], + & sfmt_ldh_ops[0], + & sfmt_ldh_d_ops[0], + & sfmt_ldb_ops[0], + & sfmt_ldb_d_ops[0], + & sfmt_ldh_ops[0], + & sfmt_ldh_d_ops[0], + & sfmt_ld_plus_ops[0], + & sfmt_ld24_ops[0], + & sfmt_ldi8_ops[0], + & sfmt_ldi16_ops[0], + & sfmt_lock_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_a_ops[0], + & sfmt_add_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_a_ops[0], + & sfmt_mv_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_a_ops[0], + & sfmt_mvfc_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtachi_a_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtachi_a_ops[0], + & sfmt_mvtc_ops[0], + & sfmt_mv_ops[0], + & sfmt_nop_ops[0], + & sfmt_mv_ops[0], + & sfmt_rac_ops[0], + & sfmt_rac_dsi_ops[0], + & sfmt_rac_ops[0], + & sfmt_rac_dsi_ops[0], + & sfmt_rte_ops[0], + & sfmt_seth_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_st_ops[0], + & sfmt_st_d_ops[0], + & sfmt_stb_ops[0], + & sfmt_stb_d_ops[0], + & sfmt_sth_ops[0], + & sfmt_sth_d_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_sth_plus_ops[0], + & sfmt_stb_plus_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_add_ops[0], + & sfmt_addv_ops[0], + & sfmt_addx_ops[0], + & sfmt_trap_ops[0], + & sfmt_unlock_ops[0], + & sfmt_satb_ops[0], + & sfmt_satb_ops[0], + & sfmt_sat_ops[0], + & sfmt_cmpz_ops[0], + & sfmt_sadd_ops[0], + & sfmt_macwu1_ops[0], + & sfmt_machi_ops[0], + & sfmt_mulwu1_ops[0], + & sfmt_macwu1_ops[0], + & sfmt_sc_ops[0], + & sfmt_sc_ops[0], + & sfmt_clrpsw_ops[0], + & sfmt_setpsw_ops[0], + & sfmt_bset_ops[0], + & sfmt_bset_ops[0], + & sfmt_btst_ops[0], +}; + +/* Function to call before using the operand instance table. */ + +void +m32r_cgen_init_opinst_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + insns[i].opinst = oi[i]; +} diff --git a/external/gpl3/gdb/dist/opcodes/m68hc11-dis.c b/external/gpl3/gdb/dist/opcodes/m68hc11-dis.c new file mode 100644 index 000000000000..f6d6184d9ea6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m68hc11-dis.c @@ -0,0 +1,742 @@ +/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly + Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007 + Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "ansidecl.h" +#include "opcode/m68hc11.h" +#include "dis-asm.h" + +#define PC_REGNUM 3 + +static const char *const reg_name[] = { + "X", "Y", "SP", "PC" +}; + +static const char *const reg_src_table[] = { + "A", "B", "CCR", "TMP3", "D", "X", "Y", "SP" +}; + +static const char *const reg_dst_table[] = { + "A", "B", "CCR", "TMP2", "D", "X", "Y", "SP" +}; + +#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4) + +/* Prototypes for local functions. */ +static int read_memory (bfd_vma, bfd_byte *, int, struct disassemble_info *); +static int print_indexed_operand (bfd_vma, struct disassemble_info *, + int*, int, int, bfd_vma); +static int print_insn (bfd_vma, struct disassemble_info *, int); + +static int +read_memory (bfd_vma memaddr, bfd_byte* buffer, int size, + struct disassemble_info* info) +{ + int status; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = (*info->read_memory_func) (memaddr, buffer, size, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + return 0; +} + + +/* Read the 68HC12 indexed operand byte and print the corresponding mode. + Returns the number of bytes read or -1 if failure. */ +static int +print_indexed_operand (bfd_vma memaddr, struct disassemble_info* info, + int* indirect, int mov_insn, int pc_offset, + bfd_vma endaddr) +{ + bfd_byte buffer[4]; + int reg; + int status; + short sval; + int pos = 1; + + if (indirect) + *indirect = 0; + + status = read_memory (memaddr, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + /* n,r with 5-bits signed constant. */ + if ((buffer[0] & 0x20) == 0) + { + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x1f); + if (sval & 0x10) + sval |= 0xfff0; + /* 68HC12 requires an adjustment for movb/movw pc relative modes. */ + if (reg == PC_REGNUM && info->mach == bfd_mach_m6812 && mov_insn) + sval += pc_offset; + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + + if (reg == PC_REGNUM) + { + (* info->fprintf_func) (info->stream, " {"); + (* info->print_address_func) (endaddr + sval, info); + (* info->fprintf_func) (info->stream, "}"); + } + } + + /* Auto pre/post increment/decrement. */ + else if ((buffer[0] & 0xc0) != 0xc0) + { + const char *mode; + + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x0f); + if (sval & 0x8) + { + sval |= 0xfff0; + sval = -sval; + mode = "-"; + } + else + { + sval = sval + 1; + mode = "+"; + } + (*info->fprintf_func) (info->stream, "%d,%s%s%s", + (int) sval, + (buffer[0] & 0x10 ? "" : mode), + reg_name[reg], (buffer[0] & 0x10 ? mode : "")); + } + + /* [n,r] 16-bits offset indexed indirect. */ + else if ((buffer[0] & 0x07) == 3) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + (*info->fprintf_func) (info->stream, "[%u,%s]", + sval & 0x0ffff, reg_name[reg]); + if (indirect) + *indirect = 1; + } + + /* n,r with 9 and 16 bit signed constant. */ + else if ((buffer[0] & 0x4) == 0) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, + &buffer[1], (buffer[0] & 0x2 ? 2 : 1), info); + if (status != 0) + { + return status; + } + if (buffer[0] & 2) + { + sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF)); + sval &= 0x0FFFF; + pos += 2; + endaddr += 2; + } + else + { + sval = buffer[1] & 0x00ff; + if (buffer[0] & 0x01) + sval |= 0xff00; + pos++; + endaddr++; + } + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + if (reg == PC_REGNUM) + { + (* info->fprintf_func) (info->stream, " {"); + (* info->print_address_func) (endaddr + sval, info); + (* info->fprintf_func) (info->stream, "}"); + } + } + else + { + reg = (buffer[0] >> 3) & 0x03; + switch (buffer[0] & 3) + { + case 0: + (*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]); + break; + case 1: + (*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]); + break; + case 2: + (*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]); + break; + case 3: + default: + (*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]); + if (indirect) + *indirect = 1; + break; + } + } + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +static int +print_insn (bfd_vma memaddr, struct disassemble_info* info, int arch) +{ + int status; + bfd_byte buffer[4]; + unsigned char code; + long format, pos, i; + short sval; + const struct m68hc11_opcode *opcode; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = read_memory (memaddr, buffer, 1, info); + if (status != 0) + { + return status; + } + + format = 0; + code = buffer[0]; + pos = 0; + + /* Look for page2,3,4 opcodes. */ + if (code == M6811_OPCODE_PAGE2) + { + pos++; + format = M6811_OP_PAGE2; + } + else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE3; + } + else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE4; + } + + /* We are in page2,3,4; get the real opcode. */ + if (pos == 1) + { + status = read_memory (memaddr + pos, &buffer[1], 1, info); + if (status != 0) + { + return status; + } + code = buffer[1]; + } + + + /* Look first for a 68HC12 alias. All of them are 2-bytes long and + in page 1. There is no operand to print. We read the second byte + only when we have a possible match. */ + if ((arch & cpu6812) && format == 0) + { + int must_read = 1; + + /* Walk the alias table to find a code1+code2 match. */ + for (i = 0; i < m68hc12_num_alias; i++) + { + if (m68hc12_alias[i].code1 == code) + { + if (must_read) + { + status = read_memory (memaddr + pos + 1, + &buffer[1], 1, info); + if (status != 0) + break; + + must_read = 1; + } + if (m68hc12_alias[i].code2 == (unsigned char) buffer[1]) + { + (*info->fprintf_func) (info->stream, "%s", + m68hc12_alias[i].name); + return 2; + } + } + } + } + + pos++; + + /* Scan the opcode table until we find the opcode + with the corresponding page. */ + opcode = m68hc11_opcodes; + for (i = 0; i < m68hc11_num_opcodes; i++, opcode++) + { + int offset; + int pc_src_offset; + int pc_dst_offset = 0; + + if ((opcode->arch & arch) == 0) + continue; + if (opcode->opcode != code) + continue; + if ((opcode->format & OP_PAGE_MASK) != format) + continue; + + if (opcode->format & M6812_OP_REG) + { + int j; + int is_jump; + + if (opcode->format & M6811_OP_JUMP_REL) + is_jump = 1; + else + is_jump = 0; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + for (j = 0; i + j < m68hc11_num_opcodes; j++) + { + if ((opcode[j].arch & arch) == 0) + continue; + if (opcode[j].opcode != code) + continue; + if (is_jump) + { + if (!(opcode[j].format & M6811_OP_JUMP_REL)) + continue; + + if ((opcode[j].format & M6812_OP_IBCC_MARKER) + && (buffer[0] & 0xc0) != 0x80) + continue; + if ((opcode[j].format & M6812_OP_TBCC_MARKER) + && (buffer[0] & 0xc0) != 0x40) + continue; + if ((opcode[j].format & M6812_OP_DBCC_MARKER) + && (buffer[0] & 0xc0) != 0) + continue; + if ((opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) == 0) + break; + if (!(opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) != 0) + break; + continue; + } + if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80) + break; + if ((opcode[j].format & M6812_OP_SEX_MARKER) + && (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7)) + && ((buffer[0] & 0x0f0) <= 0x20)) + break; + if (opcode[j].format & M6812_OP_TFR_MARKER + && !(buffer[0] & 0x80)) + break; + } + if (i + j < m68hc11_num_opcodes) + opcode = &opcode[j]; + } + + /* We have found the opcode. Extract the operand and print it. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + format = opcode->format; + if (format & (M6811_OP_MASK | M6811_OP_BITMASK + | M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + { + (*info->fprintf_func) (info->stream, "\t"); + } + + /* The movb and movw must be handled in a special way... + The source constant 'ii' is not always at the same place. + This is the same for the destination for the post-indexed byte. + The 'offset' is used to do the appropriate correction. + + offset offset + for constant for destination + movb 18 OB ii hh ll 0 0 + 18 08 xb ii 1 -1 + 18 0C hh ll hh ll 0 0 + 18 09 xb hh ll 1 -1 + 18 0D xb hh ll 0 0 + 18 0A xb xb 0 0 + + movw 18 03 jj kk hh ll 0 0 + 18 00 xb jj kk 1 -1 + 18 04 hh ll hh ll 0 0 + 18 01 xb hh ll 1 -1 + 18 05 xb hh ll 0 0 + 18 02 xb xb 0 0 + + After the source operand is read, the position 'pos' is incremented + this explains the negative offset for destination. + + movb/movw above are the only instructions with this matching + format. */ + offset = ((format & M6812_OP_IDX_P2) + && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | + M6811_OP_IND16))); + + /* Operand with one more byte: - immediate, offset, + direct-low address. */ + if (format & + (M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT)) + { + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + + /* This movb/movw is special (see above). */ + offset = -offset; + + pc_dst_offset = 2; + if (format & M6811_OP_IMM8) + { + (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]); + format &= ~M6811_OP_IMM8; + /* Set PC destination offset. */ + pc_dst_offset = 1; + } + else if (format & M6811_OP_IX) + { + /* Offsets are in range 0..255, print them unsigned. */ + (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF); + format &= ~M6811_OP_IX; + } + else if (format & M6811_OP_IY) + { + (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF); + format &= ~M6811_OP_IY; + } + else if (format & M6811_OP_DIRECT) + { + (*info->fprintf_func) (info->stream, "*"); + (*info->print_address_func) (buffer[0] & 0x0FF, info); + format &= ~M6811_OP_DIRECT; + } + } + +#define M6812_DST_MOVE (M6812_OP_IND16_P2 | M6812_OP_IDX_P2) +#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2) + /* Analyze the 68HC12 indexed byte. */ + if (format & M6812_INDEXED_FLAGS) + { + int indirect; + bfd_vma endaddr; + + endaddr = memaddr + pos + 1; + if (format & M6811_OP_IND16) + endaddr += 2; + pc_src_offset = -1; + pc_dst_offset = 1; + status = print_indexed_operand (memaddr + pos, info, &indirect, + (format & M6812_DST_MOVE), + pc_src_offset, endaddr); + if (status < 0) + { + return status; + } + pos += status; + + /* The indirect addressing mode of the call instruction does + not need the page code. */ + if ((format & M6812_OP_PAGE) && indirect) + format &= ~M6812_OP_PAGE; + } + + /* 68HC12 dbcc/ibcc/tbcc operands. */ + if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL)) + { + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + (*info->fprintf_func) (info->stream, "%s,", + reg_src_table[buffer[0] & 0x07]); + sval = buffer[1] & 0x0ff; + if (buffer[0] & 0x10) + sval |= 0xff00; + + pos += 2; + (*info->print_address_func) (memaddr + pos + sval, info); + format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL); + } + else if (format & (M6812_OP_REG | M6812_OP_REG_2)) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + (*info->fprintf_func) (info->stream, "%s,%s", + reg_src_table[(buffer[0] >> 4) & 7], + reg_dst_table[(buffer[0] & 7)]); + } + + if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) + { + int val; + bfd_vma addr; + unsigned page = 0; + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + if (format & M6812_OP_IDX_P2) + offset = -2; + else + offset = 0; + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + addr = val; + pc_dst_offset = 2; + if (format & M6812_OP_PAGE) + { + status = read_memory (memaddr + pos + offset, buffer, 1, info); + if (status != 0) + return status; + + page = (unsigned) buffer[0]; + if (addr >= M68HC12_BANK_BASE && addr < 0x0c000) + addr = ((val - M68HC12_BANK_BASE) + | (page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + } + else if ((arch & cpu6812) + && addr >= M68HC12_BANK_BASE && addr < 0x0c000) + { + int cur_page; + bfd_vma vaddr; + + if (memaddr >= M68HC12_BANK_VIRT) + cur_page = ((memaddr - M68HC12_BANK_VIRT) + >> M68HC12_BANK_SHIFT); + else + cur_page = 0; + + vaddr = ((addr - M68HC12_BANK_BASE) + + (cur_page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + if (!info->symbol_at_address_func (addr, info) + && info->symbol_at_address_func (vaddr, info)) + addr = vaddr; + } + if (format & M6811_OP_IMM16) + { + format &= ~M6811_OP_IMM16; + (*info->fprintf_func) (info->stream, "#"); + } + else + format &= ~M6811_OP_IND16; + + (*info->print_address_func) (addr, info); + if (format & M6812_OP_PAGE) + { + (* info->fprintf_func) (info->stream, " {"); + (* info->print_address_func) (val, info); + (* info->fprintf_func) (info->stream, ", %d}", page); + format &= ~M6812_OP_PAGE; + pos += 1; + } + } + + if (format & M6812_OP_IDX_P2) + { + (*info->fprintf_func) (info->stream, ", "); + status = print_indexed_operand (memaddr + pos + offset, info, + 0, 1, pc_dst_offset, + memaddr + pos + offset + 1); + if (status < 0) + return status; + pos += status; + } + + if (format & M6812_OP_IND16_P2) + { + int val; + + (*info->fprintf_func) (info->stream, ", "); + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + (*info->print_address_func) (val, info); + } + + /* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately + and in that order. The brset/brclr insn have a bitmask and then + a relative branch offset. */ + if (format & M6811_OP_BITMASK) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos++; + (*info->fprintf_func) (info->stream, " #$%02x%s", + buffer[0] & 0x0FF, + (format & M6811_OP_JUMP_REL ? " " : "")); + format &= ~M6811_OP_BITMASK; + } + if (format & M6811_OP_JUMP_REL) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0]; + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6811_OP_JUMP_REL; + } + else if (format & M6812_OP_JUMP_REL16) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + if (val & 0x8000) + val |= 0xffff0000; + + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6812_OP_JUMP_REL16; + } + + if (format & M6812_OP_PAGE) + { + int val; + + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos += 1; + + val = buffer[0] & 0x0ff; + (*info->fprintf_func) (info->stream, ", %d", val); + } + +#ifdef DEBUG + /* Consistency check. 'format' must be 0, so that we have handled + all formats; and the computed size of the insn must match the + opcode table content. */ + if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2)) + { + (*info->fprintf_func) (info->stream, "; Error, format: %lx", format); + } + if (pos != opcode->size) + { + (*info->fprintf_func) (info->stream, "; Error, size: %ld expect %d", + pos, opcode->size); + } +#endif + return pos; + } + + /* Opcode not recognized. */ + if (format == M6811_OP_PAGE2 && arch & cpu6812 + && ((code >= 0x30 && code <= 0x39) || (code >= 0x40))) + (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff); + + else if (format == M6811_OP_PAGE2) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE2, code); + else if (format == M6811_OP_PAGE3) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE3, code); + else if (format == M6811_OP_PAGE4) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE4, code); + else + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", code); + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +int +print_insn_m68hc11 (bfd_vma memaddr, struct disassemble_info* info) +{ + return print_insn (memaddr, info, cpu6811); +} + +int +print_insn_m68hc12 (bfd_vma memaddr, struct disassemble_info* info) +{ + return print_insn (memaddr, info, cpu6812); +} diff --git a/external/gpl3/gdb/dist/opcodes/m68hc11-opc.c b/external/gpl3/gdb/dist/opcodes/m68hc11-opc.c new file mode 100644 index 000000000000..ac6259d00fe5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m68hc11-opc.c @@ -0,0 +1,1082 @@ +/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list + Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/m68hc11.h" + +#define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) + +/* Combination of CCR flags. */ +#define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT +#define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT +#define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT +#define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT +#define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT +#define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT +#define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT +#define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT + +/* Flags when the insn only changes some CCR flags. */ +#define CHG_NONE 0,0,0 +#define CHG_Z 0,0,M6811_Z_BIT +#define CHG_C 0,0,M6811_C_BIT +#define CHG_ZVC 0,0,M6811_ZVC_BIT +#define CHG_NZC 0,0,M6811_NZC_BIT +#define CHG_NZV 0,0,M6811_NZV_BIT +#define CHG_NZVC 0,0,M6811_NZVC_BIT +#define CHG_HNZVC 0,0,M6811_HNZVC_BIT +#define CHG_ALL 0,0,0xff + +/* The insn clears and changes some flags. */ +#define CLR_I 0,M6811_I_BIT,0 +#define CLR_C 0,M6811_C_BIT,0 +#define CLR_V 0,M6811_V_BIT,0 +#define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT +#define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT +#define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT +#define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */ +#define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT + +/* The insn sets some flags. */ +#define SET_I M6811_I_BIT,0,0 +#define SET_C M6811_C_BIT,0,0 +#define SET_V M6811_V_BIT,0,0 +#define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0 +#define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT +#define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT + +#define _M 0xff +#define OP_NONE M6811_OP_NONE +#define OP_PAGE2 M6811_OP_PAGE2 +#define OP_PAGE3 M6811_OP_PAGE3 +#define OP_PAGE4 M6811_OP_PAGE4 +#define OP_IMM8 M6811_OP_IMM8 +#define OP_IMM16 M6811_OP_IMM16 +#define OP_IX M6811_OP_IX +#define OP_IY M6811_OP_IY +#define OP_IND16 M6811_OP_IND16 +#define OP_PAGE M6812_OP_PAGE +#define OP_IDX M6812_OP_IDX +#define OP_IDX_1 M6812_OP_IDX_1 +#define OP_IDX_2 M6812_OP_IDX_2 +#define OP_D_IDX M6812_OP_D_IDX +#define OP_D_IDX_2 M6812_OP_D_IDX_2 +#define OP_DIRECT M6811_OP_DIRECT +#define OP_BITMASK M6811_OP_BITMASK +#define OP_BRANCH M6811_OP_BRANCH +#define OP_JUMP_REL (M6811_OP_JUMP_REL|OP_BRANCH) +#define OP_JUMP_REL16 (M6812_OP_JUMP_REL16|OP_BRANCH) +#define OP_REG M6812_OP_REG +#define OP_REG_1 M6812_OP_REG +#define OP_REG_2 M6812_OP_REG_2 +#define OP_IDX_p2 M6812_OP_IDX_P2 +#define OP_IND16_p2 M6812_OP_IND16_P2 +#define OP_TRAP_ID M6812_OP_TRAP_ID +#define OP_EXG_MARKER M6812_OP_EXG_MARKER +#define OP_TFR_MARKER M6812_OP_TFR_MARKER +#define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER) +#define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER) +#define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER) + +/* + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + +-- cpu + Name -+ +------- Insn CCR changes + Format ------+ +----------- Max # cycles + Size --------------------+ +--------------- Min # cycles + +--------------------- Opcode +*/ +const struct m68hc11_opcode m68hc11_opcodes[] = { + { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 }, + { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 }, + { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 }, + { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 }, + + { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 }, + { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 }, + { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 }, + { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 }, + { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 }, + { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 }, + { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + + { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 }, + + { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 }, + { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 }, + { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + + { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811}, + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK + | OP_JUMP_REL + | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 }, + + { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK + | OP_JUMP_REL + | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 }, + + + { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 }, + { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 }, + + { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "call", OP_IND16 | OP_PAGE + | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX | OP_PAGE + | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_1 | OP_PAGE + | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_2 | OP_PAGE + | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX + | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX_2 + | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + + { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, + { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, + + { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 }, + { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 }, + + { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + + { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + + { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 }, + + { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + + { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + + { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 }, + { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 }, + { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 }, + { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + + { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 }, + { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 }, + { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 }, + { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 }, + { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 }, + { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + + /* After 'daa', the Z flag is undefined. Mark it as changed. */ + { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 }, + { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 }, + + { "dbeq", OP_DBEQ_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "dbne", OP_DBNE_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 }, + + { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 }, + + { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 }, + { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 }, + { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 }, + { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 }, + + { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 }, + { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 }, + { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 }, + + { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 }, + { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 }, + { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 }, + + { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + + { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + + { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + + { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + + { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 }, + { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 }, + + { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 }, + + { "exg", OP_EXG_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811}, + { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 }, + + { "ibeq", OP_IBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "ibne", OP_IBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811}, + { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 }, + { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 }, + + { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 }, + + { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 }, + { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 }, + { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 }, + { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 }, + + { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 }, + + { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 }, + { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, + { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, + + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, + + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 }, + + { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 }, + { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 }, + { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 }, + { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 }, + { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 }, + { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 }, + { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 }, + { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 }, + { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 }, + { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 }, + { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 }, + { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 }, + { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 }, + { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 }, + + { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + + { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + + { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 }, + + { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 }, + { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 }, + { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + + { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 }, + { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 }, + + { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + + { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + + { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 }, + + { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + + { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + + { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 }, + { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 }, + + { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 }, + + { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 }, + { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 }, + + { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 }, + { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 }, + { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + + { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 }, + { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 }, + + { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 }, + + { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 }, + { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 }, + { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 }, + { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 }, + { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 }, + { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 }, + + { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 }, + { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 }, + { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 }, + { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 }, + { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 }, + { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 }, + + { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 }, + { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 }, + + { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 }, + { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + + { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 }, + { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 }, + { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 }, + { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 }, + + { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 }, + { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 }, + { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + + { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 }, + { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811}, + { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812}, + { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 }, + { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 }, + + { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 }, + { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 }, + + { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 }, + { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 }, + { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 }, + + { "sex", M6812_OP_SEX_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 }, + { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 }, + + { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 }, + { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 }, + { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 }, + { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 }, + { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 }, + { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + + { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 }, + + { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 }, + + { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + + { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 }, + + { "tbeq", OP_TBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 }, + + { "tbne", OP_TBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tfr", OP_TFR_MARKER + | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 }, + + { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 }, + { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 }, + { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 }, + { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 }, + + { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 }, + + { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 }, + + { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 }, + { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 } +}; + +const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes); + +/* The following alias table provides source compatibility to + move from 68HC11 assembly to 68HC12. */ +const struct m68hc12_opcode_alias m68hc12_alias[] = { + { "abx", "leax b,x", 2, 0x1a, 0xe5 }, + { "aby", "leay b,y", 2, 0x19, 0xed }, + { "clc", "andcc #$fe", 2, 0x10, 0xfe }, + { "cli", "andcc #$ef", 2, 0x10, 0xef }, + { "clv", "andcc #$fd", 2, 0x10, 0xfd }, + { "des", "leas -1,sp", 2, 0x1b, 0x9f }, + { "ins", "leas 1,sp", 2, 0x1b, 0x81 }, + { "sec", "orcc #$01", 2, 0x14, 0x01 }, + { "sei", "orcc #$10", 2, 0x14, 0x10 }, + { "sev", "orcc #$02", 2, 0x14, 0x02 }, + { "tap", "tfr a,ccr", 2, 0xb7, 0x02 }, + { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 }, + { "tsx", "tfr sp,x", 2, 0xb7, 0x75 }, + { "tsy", "tfr sp,y", 2, 0xb7, 0x76 }, + { "txs", "tfr x,sp", 2, 0xb7, 0x57 }, + { "tys", "tfr y,sp", 2, 0xb7, 0x67 }, + { "xgdx","exg d,x", 2, 0xb7, 0xc5 }, + { "xgdy","exg d,y", 2, 0xb7, 0xc6 } +}; +const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias); diff --git a/external/gpl3/gdb/dist/opcodes/m68k-dis.c b/external/gpl3/gdb/dist/opcodes/m68k-dis.c new file mode 100644 index 000000000000..0bbf0379d89a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m68k-dis.c @@ -0,0 +1,1632 @@ +/* Print Motorola 68k instructions. + Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, + 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "floatformat.h" +#include "libiberty.h" +#include "opintl.h" + +#include "opcode/m68k.h" + +/* Local function prototypes. */ + +const char * const fpcr_names[] = +{ + "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", + "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" +}; + +static char *const reg_names[] = +{ + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", + "%ps", "%pc" +}; + +/* Name of register halves for MAC/EMAC. + Seperate from reg_names since 'spu', 'fpl' look weird. */ +static char *const reg_half_names[] = +{ + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", + "%ps", "%pc" +}; + +/* Sign-extend an (unsigned char). */ +#if __STDC__ == 1 +#define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) +#else +#define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) +#endif + +/* Get a 1 byte signed integer. */ +#define NEXTBYTE(p, val) \ + do \ + { \ + p += 2; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + val = COERCE_SIGNED_CHAR (p[-1]); \ + } \ + while (0) + +/* Get a 2 byte signed integer. */ +#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) + +#define NEXTWORD(p, val, ret_val) \ + do \ + { \ + p += 2; \ + if (!FETCH_DATA (info, p)) \ + return ret_val; \ + val = COERCE16 ((p[-2] << 8) + p[-1]); \ + } \ + while (0) + +/* Get a 4 byte signed integer. */ +#define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000) + +#define NEXTLONG(p, val, ret_val) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return ret_val; \ + val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \ + } \ + while (0) + +/* Get a 4 byte unsigned integer. */ +#define NEXTULONG(p, val) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \ + } \ + while (0) + +/* Get a single precision float. */ +#define NEXTSINGLE(val, p) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + floatformat_to_double (& floatformat_ieee_single_big, \ + (char *) p - 4, & val); \ + } \ + while (0) + +/* Get a double precision float. */ +#define NEXTDOUBLE(val, p) \ + do \ + { \ + p += 8; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + floatformat_to_double (& floatformat_ieee_double_big, \ + (char *) p - 8, & val); \ + } \ + while (0) + +/* Get an extended precision float. */ +#define NEXTEXTEND(val, p) \ + do \ + { \ + p += 12; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + floatformat_to_double (& floatformat_m68881_ext, \ + (char *) p - 12, & val); \ + } \ + while (0) + +/* Need a function to convert from packed to double + precision. Actually, it's easier to print a + packed number than a double anyway, so maybe + there should be a special case to handle this... */ +#define NEXTPACKED(p, val) \ + do \ + { \ + p += 12; \ + if (!FETCH_DATA (info, p)) \ + return -3; \ + val = 0.0; \ + } \ + while (0) + + +/* Maximum length of an instruction. */ +#define MAXLEN 22 + +#include + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + struct private *priv = (struct private *)info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + return 0; + } + else + priv->max_fetched = addr; + return 1; +} + +/* This function is used to print to the bit-bucket. */ +static int +dummy_printer (FILE *file ATTRIBUTE_UNUSED, + const char *format ATTRIBUTE_UNUSED, + ...) +{ + return 0; +} + +static void +dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ +} + +/* Fetch BITS bits from a position in the instruction specified by CODE. + CODE is a "place to put an argument", or 'x' for a destination + that is a general address (mode and register). + BUFFER contains the instruction. + Returns -1 on failure. */ + +static int +fetch_arg (unsigned char *buffer, + int code, + int bits, + disassemble_info *info) +{ + int val = 0; + + switch (code) + { + case '/': /* MAC/EMAC mask bit. */ + val = buffer[3] >> 5; + break; + + case 'G': /* EMAC ACC load. */ + val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); + break; + + case 'H': /* EMAC ACC !load. */ + val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); + break; + + case ']': /* EMAC ACCEXT bit. */ + val = buffer[0] >> 2; + break; + + case 'I': /* MAC/EMAC scale factor. */ + val = buffer[2] >> 1; + break; + + case 'F': /* EMAC ACCx. */ + val = buffer[0] >> 1; + break; + + case 'f': + val = buffer[1]; + break; + + case 's': + val = buffer[1]; + break; + + case 'd': /* Destination, for register or quick. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 9; + break; + + case 'x': /* Destination, for general arg. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 6; + break; + + case 'k': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[3] >> 4); + break; + + case 'C': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = buffer[3]; + break; + + case '1': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 12; + break; + + case '2': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 6; + break; + + case '3': + case 'j': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + break; + + case '4': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + val >>= 12; + break; + + case '5': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + val >>= 6; + break; + + case '6': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + break; + + case '7': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 7; + break; + + case '8': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 10; + break; + + case '9': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 5; + break; + + case 'e': + val = (buffer[1] >> 6); + break; + + case 'E': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] >> 1); + break; + + case 'm': + val = (buffer[1] & 0x40 ? 0x8 : 0) + | ((buffer[0] >> 1) & 0x7) + | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'n': + val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); + break; + + case 'o': + val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'M': + val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'N': + val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'h': + val = buffer[2] >> 2; + break; + + default: + abort (); + } + + /* bits is never too big. */ + return val & ((1 << bits) - 1); +} + +/* Check if an EA is valid for a particular code. This is required + for the EMAC instructions since the type of source address determines + if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it + is a non-load EMAC instruction and the bits mean register Ry. + A similar case exists for the movem instructions where the register + mask is interpreted differently for different EAs. */ + +static bfd_boolean +m68k_valid_ea (char code, int val) +{ + int mode, mask; +#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ + (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ + | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) + + switch (code) + { + case '*': + mask = M (1,1,1,1,1,1,1,1,1,1,1,1); + break; + case '~': + mask = M (0,0,1,1,1,1,1,1,1,0,0,0); + break; + case '%': + mask = M (1,1,1,1,1,1,1,1,1,0,0,0); + break; + case ';': + mask = M (1,0,1,1,1,1,1,1,1,1,1,1); + break; + case '@': + mask = M (1,0,1,1,1,1,1,1,1,1,1,0); + break; + case '!': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); + break; + case '&': + mask = M (0,0,1,0,0,1,1,1,1,0,0,0); + break; + case '$': + mask = M (1,0,1,1,1,1,1,1,1,0,0,0); + break; + case '?': + mask = M (1,0,1,0,0,1,1,1,1,0,0,0); + break; + case '/': + mask = M (1,0,1,0,0,1,1,1,1,1,1,0); + break; + case '|': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); + break; + case '>': + mask = M (0,0,1,0,1,1,1,1,1,0,0,0); + break; + case '<': + mask = M (0,0,1,1,0,1,1,1,1,1,1,0); + break; + case 'm': + mask = M (1,1,1,1,1,0,0,0,0,0,0,0); + break; + case 'n': + mask = M (0,0,0,0,0,1,0,0,0,1,0,0); + break; + case 'o': + mask = M (0,0,0,0,0,0,1,1,1,0,1,1); + break; + case 'p': + mask = M (1,1,1,1,1,1,0,0,0,0,0,0); + break; + case 'q': + mask = M (1,0,1,1,1,1,0,0,0,0,0,0); + break; + case 'v': + mask = M (1,0,1,1,1,1,0,1,1,0,0,0); + break; + case 'b': + mask = M (1,0,1,1,1,1,0,0,0,1,0,0); + break; + case 'w': + mask = M (0,0,1,1,1,1,0,0,0,1,0,0); + break; + case 'y': + mask = M (0,0,1,0,0,1,0,0,0,0,0,0); + break; + case 'z': + mask = M (0,0,1,0,0,1,0,0,0,1,0,0); + break; + case '4': + mask = M (0,0,1,1,1,1,0,0,0,0,0,0); + break; + default: + abort (); + } +#undef M + + mode = (val >> 3) & 7; + if (mode == 7) + mode += val & 7; + return (mask & (1 << mode)) != 0; +} + +/* Print a base register REGNO and displacement DISP, on INFO->STREAM. + REGNO = -1 for pc, -2 for none (suppressed). */ + +static void +print_base (int regno, bfd_vma disp, disassemble_info *info) +{ + if (regno == -1) + { + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (disp, info); + } + else + { + char buf[50]; + + if (regno == -2) + (*info->fprintf_func) (info->stream, "@("); + else if (regno == -3) + (*info->fprintf_func) (info->stream, "%%zpc@("); + else + (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); + + sprintf_vma (buf, disp); + (*info->fprintf_func) (info->stream, "%s", buf); + } +} + +/* Print an indexed argument. The base register is BASEREG (-1 for pc). + P points to extension word, in buffer. + ADDR is the nominal core address of that extension word. + Returns NULL upon error. */ + +static unsigned char * +print_indexed (int basereg, + unsigned char *p, + bfd_vma addr, + disassemble_info *info) +{ + int word; + static char *const scales[] = { "", ":2", ":4", ":8" }; + bfd_vma base_disp; + bfd_vma outer_disp; + char buf[40]; + char vmabuf[50]; + + NEXTWORD (p, word, NULL); + + /* Generate the text for the index register. + Where this will be output is not yet determined. */ + sprintf (buf, "%s:%c%s", + reg_names[(word >> 12) & 0xf], + (word & 0x800) ? 'l' : 'w', + scales[(word >> 9) & 3]); + + /* Handle the 68000 style of indexing. */ + + if ((word & 0x100) == 0) + { + base_disp = word & 0xff; + if ((base_disp & 0x80) != 0) + base_disp -= 0x100; + if (basereg == -1) + base_disp += addr; + print_base (basereg, base_disp, info); + (*info->fprintf_func) (info->stream, ",%s)", buf); + return p; + } + + /* Handle the generalized kind. */ + /* First, compute the displacement to add to the base register. */ + if (word & 0200) + { + if (basereg == -1) + basereg = -3; + else + basereg = -2; + } + if (word & 0100) + buf[0] = '\0'; + base_disp = 0; + switch ((word >> 4) & 3) + { + case 2: + NEXTWORD (p, base_disp, NULL); + break; + case 3: + NEXTLONG (p, base_disp, NULL); + } + if (basereg == -1) + base_disp += addr; + + /* Handle single-level case (not indirect). */ + if ((word & 7) == 0) + { + print_base (basereg, base_disp, info); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + return p; + } + + /* Two level. Compute displacement to add after indirection. */ + outer_disp = 0; + switch (word & 3) + { + case 2: + NEXTWORD (p, outer_disp, NULL); + break; + case 3: + NEXTLONG (p, outer_disp, NULL); + } + + print_base (basereg, base_disp, info); + if ((word & 4) == 0 && buf[0] != '\0') + { + (*info->fprintf_func) (info->stream, ",%s", buf); + buf[0] = '\0'; + } + sprintf_vma (vmabuf, outer_disp); + (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + + return p; +} + +#define FETCH_ARG(size, val) \ + do \ + { \ + val = fetch_arg (buffer, place, size, info); \ + if (val < 0) \ + return -3; \ + } \ + while (0) + +/* Returns number of bytes "eaten" by the operand, or + return -1 if an invalid operand was found, or -2 if + an opcode tabe error was found or -3 to simply abort. + ADDR is the pc for this arg to be relative to. */ + +static int +print_insn_arg (const char *d, + unsigned char *buffer, + unsigned char *p0, + bfd_vma addr, + disassemble_info *info) +{ + int val = 0; + int place = d[1]; + unsigned char *p = p0; + int regno; + const char *regname; + unsigned char *p1; + double flval; + int flt_p; + bfd_signed_vma disp; + unsigned int uval; + + switch (*d) + { + case 'c': /* Cache identifier. */ + { + static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; + FETCH_ARG (2, val); + (*info->fprintf_func) (info->stream, cacheFieldName[val]); + break; + } + + case 'a': /* Address register indirect only. Cf. case '+'. */ + { + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@", reg_names[val + 8]); + break; + } + + case '_': /* 32-bit absolute address for move16. */ + { + NEXTULONG (p, uval); + (*info->print_address_func) (uval, info); + break; + } + + case 'C': + (*info->fprintf_func) (info->stream, "%%ccr"); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "%%sr"); + break; + + case 'U': + (*info->fprintf_func) (info->stream, "%%usp"); + break; + + case 'E': + (*info->fprintf_func) (info->stream, "%%acc"); + break; + + case 'G': + (*info->fprintf_func) (info->stream, "%%macsr"); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%%mask"); + break; + + case 'J': + { + /* FIXME: There's a problem here, different m68k processors call the + same address different names. The tables below try to get it right + using info->mach, but only for v4e. */ + struct regname { char * name; int value; }; + static const struct regname names[] = + { + {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, + {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, + {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, + {"%rgpiobar", 0x009}, {"%acr4",0x00c}, + {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f}, + {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, + {"%msp", 0x803}, {"%isp", 0x804}, + {"%pc", 0x80f}, + /* Reg c04 is sometimes called flashbar or rambar. + Reg c05 is also sometimes called rambar. */ + {"%rambar0", 0xc04}, {"%rambar1", 0xc05}, + + /* reg c0e is sometimes called mbar2 or secmbar. + reg c0f is sometimes called mbar. */ + {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f}, + + /* Should we be calling this psr like we do in case 'Y'? */ + {"%mmusr",0x805}, + + {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}, + + /* Fido added these. */ + {"%cac", 0xffe}, {"%mbo", 0xfff} + }; + /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */ + static const struct regname names_v4e[] = + { + {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005}, + {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008}, + }; + unsigned int arch_mask; + + arch_mask = bfd_m68k_mach_to_features (info->mach); + FETCH_ARG (12, val); + if (arch_mask & (mcfisa_b | mcfisa_c)) + { + for (regno = ARRAY_SIZE (names_v4e); --regno >= 0;) + if (names_v4e[regno].value == val) + { + (*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name); + break; + } + if (regno >= 0) + break; + } + for (regno = ARRAY_SIZE (names) - 1; regno >= 0; regno--) + if (names[regno].value == val) + { + (*info->fprintf_func) (info->stream, "%s", names[regno].name); + break; + } + if (regno < 0) + (*info->fprintf_func) (info->stream, "0x%x", val); + } + break; + + case 'Q': + FETCH_ARG (3, val); + /* 0 means 8, except for the bkpt instruction... */ + if (val == 0 && d[1] != 's') + val = 8; + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'x': + FETCH_ARG (3, val); + /* 0 means -1. */ + if (val == 0) + val = -1; + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'j': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "#%d", val+1); + break; + + case 'K': + FETCH_ARG (9, val); + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'M': + if (place == 'h') + { + static char *const scalefactor_name[] = { "<<", ">>" }; + + FETCH_ARG (1, val); + (*info->fprintf_func) (info->stream, scalefactor_name[val]); + } + else + { + FETCH_ARG (8, val); + if (val & 0x80) + val = val - 0x100; + (*info->fprintf_func) (info->stream, "#%d", val); + } + break; + + case 'T': + FETCH_ARG (4, val); + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'D': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); + break; + + case 'A': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val + 010]); + break; + + case 'R': + FETCH_ARG (4, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); + break; + + case 'r': + FETCH_ARG (4, regno); + if (regno > 7) + (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); + else + (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); + break; + + case 'F': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%%fp%d", val); + break; + + case 'O': + FETCH_ARG (6, val); + if (val & 0x20) + (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); + else + (*info->fprintf_func) (info->stream, "%d", val); + break; + + case '+': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@+", reg_names[val + 8]); + break; + + case '-': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@-", reg_names[val + 8]); + break; + + case 'k': + if (place == 'k') + { + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "{%s}", reg_names[val]); + } + else if (place == 'C') + { + FETCH_ARG (7, val); + if (val > 63) /* This is a signed constant. */ + val -= 128; + (*info->fprintf_func) (info->stream, "{#%d}", val); + } + else + return -1; + break; + + case '#': + case '^': + p1 = buffer + (*d == '#' ? 2 : 4); + if (place == 's') + FETCH_ARG (4, val); + else if (place == 'C') + FETCH_ARG (7, val); + else if (place == '8') + FETCH_ARG (3, val); + else if (place == '3') + FETCH_ARG (8, val); + else if (place == 'b') + NEXTBYTE (p1, val); + else if (place == 'w' || place == 'W') + NEXTWORD (p1, val, -3); + else if (place == 'l') + NEXTLONG (p1, val, -3); + else + return -2; + + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'B': + if (place == 'b') + NEXTBYTE (p, disp); + else if (place == 'B') + disp = COERCE_SIGNED_CHAR (buffer[1]); + else if (place == 'w' || place == 'W') + NEXTWORD (p, disp, -3); + else if (place == 'l' || place == 'L' || place == 'C') + NEXTLONG (p, disp, -3); + else if (place == 'g') + { + NEXTBYTE (buffer, disp); + if (disp == 0) + NEXTWORD (p, disp, -3); + else if (disp == -1) + NEXTLONG (p, disp, -3); + } + else if (place == 'c') + { + if (buffer[1] & 0x40) /* If bit six is one, long offset. */ + NEXTLONG (p, disp, -3); + else + NEXTWORD (p, disp, -3); + } + else + return -2; + + (*info->print_address_func) (addr + disp, info); + break; + + case 'd': + { + int val1; + + NEXTWORD (p, val, -3); + FETCH_ARG (3, val1); + (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[val1 + 8], val); + break; + } + + case 's': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); + break; + + case 'e': + FETCH_ARG (2, val); + (*info->fprintf_func) (info->stream, "%%acc%d", val); + break; + + case 'g': + FETCH_ARG (1, val); + (*info->fprintf_func) (info->stream, "%%accext%s", val == 0 ? "01" : "23"); + break; + + case 'i': + FETCH_ARG (2, val); + if (val == 1) + (*info->fprintf_func) (info->stream, "<<"); + else if (val == 3) + (*info->fprintf_func) (info->stream, ">>"); + else + return -1; + break; + + case 'I': + /* Get coprocessor ID... */ + val = fetch_arg (buffer, 'd', 3, info); + if (val < 0) + return -3; + if (val != 1) /* Unusual coprocessor ID? */ + (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); + break; + + case '4': + case '*': + case '~': + case '%': + case ';': + case '@': + case '!': + case '$': + case '?': + case '/': + case '&': + case '|': + case '<': + case '>': + case 'm': + case 'n': + case 'o': + case 'p': + case 'q': + case 'v': + case 'b': + case 'w': + case 'y': + case 'z': + if (place == 'd') + { + val = fetch_arg (buffer, 'x', 6, info); + if (val < 0) + return -3; + val = ((val & 7) << 3) + ((val >> 3) & 7); + } + else + { + val = fetch_arg (buffer, 's', 6, info); + if (val < 0) + return -3; + } + + /* If the is invalid for *d, then reject this match. */ + if (!m68k_valid_ea (*d, val)) + return -1; + + /* Get register number assuming address register. */ + regno = (val & 7) + 8; + regname = reg_names[regno]; + switch (val >> 3) + { + case 0: + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); + break; + + case 1: + (*info->fprintf_func) (info->stream, "%s", regname); + break; + + case 2: + (*info->fprintf_func) (info->stream, "%s@", regname); + break; + + case 3: + (*info->fprintf_func) (info->stream, "%s@+", regname); + break; + + case 4: + (*info->fprintf_func) (info->stream, "%s@-", regname); + break; + + case 5: + NEXTWORD (p, val, -3); + (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); + break; + + case 6: + p = print_indexed (regno, p, addr, info); + if (p == NULL) + return -3; + break; + + case 7: + switch (val & 7) + { + case 0: + NEXTWORD (p, val, -3); + (*info->print_address_func) (val, info); + break; + + case 1: + NEXTULONG (p, uval); + (*info->print_address_func) (uval, info); + break; + + case 2: + NEXTWORD (p, val, -3); + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (addr + val, info); + (*info->fprintf_func) (info->stream, ")"); + break; + + case 3: + p = print_indexed (-1, p, addr, info); + if (p == NULL) + return -3; + break; + + case 4: + flt_p = 1; /* Assume it's a float... */ + switch (place) + { + case 'b': + NEXTBYTE (p, val); + flt_p = 0; + break; + + case 'w': + NEXTWORD (p, val, -3); + flt_p = 0; + break; + + case 'l': + NEXTLONG (p, val, -3); + flt_p = 0; + break; + + case 'f': + NEXTSINGLE (flval, p); + break; + + case 'F': + NEXTDOUBLE (flval, p); + break; + + case 'x': + NEXTEXTEND (flval, p); + break; + + case 'p': + NEXTPACKED (p, flval); + break; + + default: + return -1; + } + if (flt_p) /* Print a float? */ + (*info->fprintf_func) (info->stream, "#0e%g", flval); + else + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + default: + return -1; + } + } + + /* If place is '/', then this is the case of the mask bit for + mac/emac loads. Now that the arg has been printed, grab the + mask bit and if set, add a '&' to the arg. */ + if (place == '/') + { + FETCH_ARG (1, val); + if (val) + info->fprintf_func (info->stream, "&"); + } + break; + + case 'L': + case 'l': + if (place == 'w') + { + char doneany; + p1 = buffer + 2; + NEXTWORD (p1, val, -3); + /* Move the pointer ahead if this point is farther ahead + than the last. */ + p = p1 > p ? p1 : p; + if (val == 0) + { + (*info->fprintf_func) (info->stream, "#0"); + break; + } + if (*d == 'l') + { + int newval = 0; + + for (regno = 0; regno < 16; ++regno) + if (val & (0x8000 >> regno)) + newval |= 1 << regno; + val = newval; + } + val &= 0xffff; + doneany = 0; + for (regno = 0; regno < 16; ++regno) + if (val & (1 << regno)) + { + int first_regno; + + if (doneany) + (*info->fprintf_func) (info->stream, "/"); + doneany = 1; + (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); + first_regno = regno; + while (val & (1 << (regno + 1))) + ++regno; + if (regno > first_regno) + (*info->fprintf_func) (info->stream, "-%s", + reg_names[regno]); + } + } + else if (place == '3') + { + /* `fmovem' insn. */ + char doneany; + + FETCH_ARG (8, val); + if (val == 0) + { + (*info->fprintf_func) (info->stream, "#0"); + break; + } + if (*d == 'l') + { + int newval = 0; + + for (regno = 0; regno < 8; ++regno) + if (val & (0x80 >> regno)) + newval |= 1 << regno; + val = newval; + } + val &= 0xff; + doneany = 0; + for (regno = 0; regno < 8; ++regno) + if (val & (1 << regno)) + { + int first_regno; + if (doneany) + (*info->fprintf_func) (info->stream, "/"); + doneany = 1; + (*info->fprintf_func) (info->stream, "%%fp%d", regno); + first_regno = regno; + while (val & (1 << (regno + 1))) + ++regno; + if (regno > first_regno) + (*info->fprintf_func) (info->stream, "-%%fp%d", regno); + } + } + else if (place == '8') + { + FETCH_ARG (3, val); + /* fmoveml for FP status registers. */ + (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); + } + else + return -2; + break; + + case 'X': + place = '8'; + case 'Y': + case 'Z': + case 'W': + case '0': + case '1': + case '2': + case '3': + { + char *name = 0; + + FETCH_ARG (5, val); + switch (val) + { + case 2: name = "%tt0"; break; + case 3: name = "%tt1"; break; + case 0x10: name = "%tc"; break; + case 0x11: name = "%drp"; break; + case 0x12: name = "%srp"; break; + case 0x13: name = "%crp"; break; + case 0x14: name = "%cal"; break; + case 0x15: name = "%val"; break; + case 0x16: name = "%scc"; break; + case 0x17: name = "%ac"; break; + case 0x18: name = "%psr"; break; + case 0x19: name = "%pcsr"; break; + case 0x1c: + case 0x1d: + { + int break_reg = ((buffer[3] >> 2) & 7); + + (*info->fprintf_func) + (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", + break_reg); + } + break; + default: + (*info->fprintf_func) (info->stream, "", val); + } + if (name) + (*info->fprintf_func) (info->stream, "%s", name); + } + break; + + case 'f': + { + int fc; + + FETCH_ARG (5, fc); + if (fc == 1) + (*info->fprintf_func) (info->stream, "%%dfc"); + else if (fc == 0) + (*info->fprintf_func) (info->stream, "%%sfc"); + else + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _(""), fc); + } + break; + + case 'V': + (*info->fprintf_func) (info->stream, "%%val"); + break; + + case 't': + { + int level; + + FETCH_ARG (3, level); + (*info->fprintf_func) (info->stream, "%d", level); + } + break; + + case 'u': + { + short is_upper = 0; + int reg; + + FETCH_ARG (5, reg); + if (reg & 0x10) + { + is_upper = 1; + reg &= 0xf; + } + (*info->fprintf_func) (info->stream, "%s%s", + reg_half_names[reg], + is_upper ? "u" : "l"); + } + break; + + default: + return -2; + } + + return p - p0; +} + +/* Try to match the current instruction to best and if so, return the + number of bytes consumed from the instruction stream, else zero. */ + +static int +match_insn_m68k (bfd_vma memaddr, + disassemble_info * info, + const struct m68k_opcode * best) +{ + unsigned char *save_p; + unsigned char *p; + const char *d; + const char *args = best->args; + + struct private *priv = (struct private *) info->private_data; + bfd_byte *buffer = priv->the_buffer; + fprintf_ftype save_printer = info->fprintf_func; + void (* save_print_address) (bfd_vma, struct disassemble_info *) + = info->print_address_func; + + if (*args == '.') + args++; + + /* Point at first word of argument data, + and at descriptor for first argument. */ + p = buffer + 2; + + /* Figure out how long the fixed-size portion of the instruction is. + The only place this is stored in the opcode table is + in the arguments--look for arguments which specify fields in the 2nd + or 3rd words of the instruction. */ + for (d = args; *d; d += 2) + { + /* I don't think it is necessary to be checking d[0] here; + I suspect all this could be moved to the case statement below. */ + if (d[0] == '#') + { + if (d[1] == 'l' && p - buffer < 6) + p = buffer + 6; + else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') + p = buffer + 4; + } + + if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) + p = buffer + 4; + + switch (d[1]) + { + case '1': + case '2': + case '3': + case '7': + case '8': + case '9': + case 'i': + if (p - buffer < 4) + p = buffer + 4; + break; + case '4': + case '5': + case '6': + if (p - buffer < 6) + p = buffer + 6; + break; + default: + break; + } + } + + /* pflusha is an exceptions. It takes no arguments but is two words + long. Recognize it by looking at the lower 16 bits of the mask. */ + if (p - buffer < 4 && (best->match & 0xFFFF) != 0) + p = buffer + 4; + + /* lpstop is another exception. It takes a one word argument but is + three words long. */ + if (p - buffer < 6 + && (best->match & 0xffff) == 0xffff + && args[0] == '#' + && args[1] == 'w') + { + /* Copy the one word argument into the usual location for a one + word argument, to simplify printing it. We can get away with + this because we know exactly what the second word is, and we + aren't going to print anything based on it. */ + p = buffer + 6; + FETCH_DATA (info, p); + buffer[2] = buffer[4]; + buffer[3] = buffer[5]; + } + + FETCH_DATA (info, p); + + save_p = p; + info->print_address_func = dummy_print_address; + info->fprintf_func = (fprintf_ftype) dummy_printer; + + /* We scan the operands twice. The first time we don't print anything, + but look for errors. */ + for (d = args; *d; d += 2) + { + int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + + if (eaten >= 0) + p += eaten; + else if (eaten == -1 || eaten == -3) + { + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + return 0; + } + else + { + /* We must restore the print functions before trying to print the + error message. */ + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + info->fprintf_func (info->stream, + /* xgettext:c-format */ + _("\n"), + best->name, best->args); + return 2; + } + } + + p = save_p; + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + + d = args; + + info->fprintf_func (info->stream, "%s", best->name); + + if (*d) + info->fprintf_func (info->stream, " "); + + while (*d) + { + p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + d += 2; + + if (*d && *(d - 2) != 'I' && *d != 'k') + info->fprintf_func (info->stream, ","); + } + + return p - buffer; +} + +/* Try to interpret the instruction at address MEMADDR as one that + can execute on a processor with the features given by ARCH_MASK. + If successful, print the instruction to INFO->STREAM and return + its length in bytes. Return 0 otherwise. */ + +static int +m68k_scan_mask (bfd_vma memaddr, disassemble_info *info, + unsigned int arch_mask) +{ + int i; + const char *d; + static const struct m68k_opcode **opcodes[16]; + static int numopcodes[16]; + int val; + int major_opcode; + + struct private *priv = (struct private *) info->private_data; + bfd_byte *buffer = priv->the_buffer; + + if (!opcodes[0]) + { + /* Speed up the matching by sorting the opcode + table on the upper four bits of the opcode. */ + const struct m68k_opcode **opc_pointer[16]; + + /* First count how many opcodes are in each of the sixteen buckets. */ + for (i = 0; i < m68k_numopcodes; i++) + numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; + + /* Then create a sorted table of pointers + that point into the unsorted table. */ + opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *) + * m68k_numopcodes); + opcodes[0] = opc_pointer[0]; + + for (i = 1; i < 16; i++) + { + opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; + opcodes[i] = opc_pointer[i]; + } + + for (i = 0; i < m68k_numopcodes; i++) + *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; + } + + FETCH_DATA (info, buffer + 2); + major_opcode = (buffer[0] >> 4) & 15; + + for (i = 0; i < numopcodes[major_opcode]; i++) + { + const struct m68k_opcode *opc = opcodes[major_opcode][i]; + unsigned long opcode = opc->opcode; + unsigned long match = opc->match; + const char *args = opc->args; + + if (*args == '.') + args++; + + if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) + && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) + /* Only fetch the next two bytes if we need to. */ + && (((0xffff & match) == 0) + || + (FETCH_DATA (info, buffer + 4) + && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) + && ((0xff & buffer[3] & match) == (0xff & opcode))) + ) + && (opc->arch & arch_mask) != 0) + { + /* Don't use for printout the variants of divul and divsl + that have the same register number in two places. + The more general variants will match instead. */ + for (d = args; *d; d += 2) + if (d[1] == 'D') + break; + + /* Don't use for printout the variants of most floating + point coprocessor instructions which use the same + register number in two places, as above. */ + if (*d == '\0') + for (d = args; *d; d += 2) + if (d[1] == 't') + break; + + /* Don't match fmovel with more than one register; + wait for fmoveml. */ + if (*d == '\0') + { + for (d = args; *d; d += 2) + { + if (d[0] == 's' && d[1] == '8') + { + val = fetch_arg (buffer, d[1], 3, info); + if (val < 0) + return 0; + if ((val & (val - 1)) != 0) + break; + } + } + } + + /* Don't match FPU insns with non-default coprocessor ID. */ + if (*d == '\0') + { + for (d = args; *d; d += 2) + { + if (d[0] == 'I') + { + val = fetch_arg (buffer, 'd', 3, info); + if (val != 1) + break; + } + } + } + + if (*d == '\0') + if ((val = match_insn_m68k (memaddr, info, opc))) + return val; + } + } + return 0; +} + +/* Print the m68k instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_m68k (bfd_vma memaddr, disassemble_info *info) +{ + unsigned int arch_mask; + struct private priv; + int val; + + bfd_byte *buffer = priv.the_buffer; + + info->private_data = & priv; + /* Tell objdump to use two bytes per chunk + and six bytes per line for displaying raw data. */ + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + + arch_mask = bfd_m68k_mach_to_features (info->mach); + if (!arch_mask) + { + /* First try printing an m680x0 instruction. Try printing a Coldfire + one if that fails. */ + val = m68k_scan_mask (memaddr, info, m68k_mask); + if (val == 0) + val = m68k_scan_mask (memaddr, info, mcf_mask); + } + else + { + val = m68k_scan_mask (memaddr, info, arch_mask); + } + + if (val == 0) + /* Handle undefined instructions. */ + info->fprintf_func (info->stream, ".short 0x%04x", (buffer[0] << 8) + buffer[1]); + + return val ? val : 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/m68k-opc.c b/external/gpl3/gdb/dist/opcodes/m68k-opc.c new file mode 100644 index 000000000000..0f6852f14709 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m68k-opc.c @@ -0,0 +1,2469 @@ +/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2009, 2010 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "opcode/m68k.h" + +#define one(x) ((unsigned int) (x) << 16) +#define two(x, y) (((unsigned int) (x) << 16) + (y)) + +/* The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler will bomb at + runtime. */ + +/* Format strings consist of pairs of characters. The first describes + the type of the operand and the second describes the encoding. + include/opcodes/m68k.h describes them in detail. */ + +const struct m68k_opcode m68k_opcodes[] = +{ +{"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, +{"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, + +{"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, +{"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, + +{"addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, +{"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, +{"addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, +{"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, + +{"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, +{"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, +{"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, + +/* The add opcode can generate the adda, addi, and addq instructions. */ +{"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, +{"addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, +{"addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, +{"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, +{"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, +{"addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, +{"addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, +{"addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, +{"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, +{"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, +{"addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, +{"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, +{"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, + +{"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, +{"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, +{"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, +{"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, +{"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, +{"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, + +{"andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, +{"andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{"andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, +{"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, +{"andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{"andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{"andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, + +/* The and opcode can generate the andi instruction. */ +{"andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, +{"andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{"andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, +{"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, +{"andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, +{"andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{"andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, +{"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, +{"andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, +{"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, +{"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, +{"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, +{"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, +{"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, +{"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, + +{"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, +{"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, +{"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, +{"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, +{"aslw", 2, one(0160700), one(0177700), "~s", m68000up }, +{"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, + +{"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, +{"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, +{"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, +{"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, +{"asrw", 2, one(0160300), one(0177700), "~s", m68000up }, +{"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, + +{"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, +{"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, +{"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, +{"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, + +{"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, + +{"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, +{"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, +{"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, +{"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, +{"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, +{"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, + +{"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, +{"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, + +{"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, +{"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, + +{"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, +{"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, + +{"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, +{"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, +{"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, +{"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, + +{"bgnd", 2, one(0045372), one(0177777), "", cpu32 | fido_a }, + +{"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, + +{"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, + +{"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, +{"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b}, +{"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, + +{"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, +{"bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, +{"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, + +{"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, +{"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | fido_a | mcfisa_b | mcfisa_c}, +{"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, + +{"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, +{"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, +{"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, + +{"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, + +{"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, + +{"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, +{"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, +{"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, + +{"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, +{"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, + +{"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, + +{"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up }, +{"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, + +#define SCOPE_LINE (0x1 << 3) +#define SCOPE_PAGE (0x2 << 3) +#define SCOPE_ALL (0x3 << 3) + +{"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, +{"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, + +{"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, +{"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, +{"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, + +#undef SCOPE_LINE +#undef SCOPE_PAGE +#undef SCOPE_ALL + +{"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, +{"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, +{"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, + +{"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, +{"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 | fido_a }, + +{"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, + +{"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up }, +{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, +{"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up }, +{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, +{"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up }, +{"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, + +{"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, + +/* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ +{"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up }, +{"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b | mcfisa_c }, +{"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, +{"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, +{"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b | mcfisa_c }, +{"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, +{"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up }, +{"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b | mcfisa_c }, +{"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, +{"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b | mcfisa_c }, +{"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up }, +{"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, +{"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, +{"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, + +{"cp0bcbusy",2, one (0176300), one (01777770), "BW", mcfisa_a}, +{"cp1bcbusy",2, one (0177300), one (01777770), "BW", mcfisa_a}, +{"cp0nop", 4, two (0176000,0), two (01777477,0170777), "jE", mcfisa_a}, +{"cp1nop", 4, two (0177000,0), two (01777477,0170777), "jE", mcfisa_a}, +/* These all have 2 opcode words, but no fixed bits in the second + word. We use a leading ' ' in the args string to indicate the + extra opcode word. */ +{"cp0ldb", 6, one (0176000), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp1ldb", 6, one (0177000), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp0ldw", 6, one (0176100), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp1ldw", 6, one (0177100), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp0ldl", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp1ldl", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp0ld", 6, one (0176200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp1ld", 6, one (0177200), one (01777700), ".pwR1jEK3", mcfisa_a}, +{"cp0stb", 6, one (0176400), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp1stb", 6, one (0177400), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp0stw", 6, one (0176500), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp1stw", 6, one (0177500), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp0stl", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp1stl", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp0st", 6, one (0176600), one (01777700), ".R1pwjEK3", mcfisa_a}, +{"cp1st", 6, one (0177600), one (01777700), ".R1pwjEK3", mcfisa_a}, + +{"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, +{"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, +{"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, +{"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, +{"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, +{"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, +{"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, +{"dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, +{"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, +{"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, +{"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, +{"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, +{"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, +{"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, +{"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, +{"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, + +{"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, + +{"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, +{"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, + +{"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, +{"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, + +{"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, + +{"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up | cpu32 | fido_a }, +{"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, +{"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, + +{"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up | cpu32 | fido_a }, +{"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up | cpu32 | fido_a }, + +{"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, +{"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, +{"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, +{"eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{"eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{"eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, + +/* The eor opcode can generate the eori instruction. */ +{"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, +{"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, +{"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, +{"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, +{"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, +{"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, +{"eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, +{"eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, +{"eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, +{"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, + +{"exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, +{"exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, +{"exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, +{"exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, + +{"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, +{"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, +{"extbl", 2, one(0044700), one(0177770), "Ds", m68020up | cpu32 | fido_a | mcfisa_a }, + +{"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa | mcfisa_c}, + +/* float stuff starts here */ + +{"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, +{"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, +{"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, +{"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, +{"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, +{"fdabss", 4, two(0xF000, 0x445C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, +{"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, +{"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, +{"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, +{"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, + +{"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsaddd", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +/* This is the same as `fbf .+2'. */ +{"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat }, + +{"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, +{"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, + +{"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, +{"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, + +{"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, +{"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, + +{"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, +{"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, + +{"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, +{"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, +{"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, +{"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, +{"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, +/* FIXME: the next two variants should not permit moving an address + register to anything but the floating point instruction register. */ +{"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, +{"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, + /* Move the FP control registers. */ +{"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, +{"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, +{"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, +{"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, +{"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, +{"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, +{"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, +{"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, + +{"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, +{"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, + +{"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, +{"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, + +{"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, + +{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, +{"fmovemd", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, +{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, +{"fmovemd", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, + +{"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, + +{"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +/* FIXME: In the next instruction, we should only permit %dn if the + target is a single register. We should only permit %an if the + target is a single %fpiar. */ +{"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, + +{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizsl3", cfloat }, +{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Iizs#3", cfloat }, +{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Iil3ys", cfloat }, +{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Ii#3ys", cfloat }, + +{"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, +{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, +{"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, +{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, +{"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, +{"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, +{"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, +{"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, +{"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, +{"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, +{"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, +{"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, +{"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, +{"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, +{"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, +{"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, + +{"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, + +{"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +{"frestore", 2, one(0xF140), one(0xF1C0), "Ids", mfloat }, +{"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat }, + +{"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, + +/* $ is necessary to prevent the assembler from using PC-relative. + If @ were used, "label: fseq label" could produce "ftrapeq", 2, + because "label" became "pc@label". */ +{"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, +{"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, + +{"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, +{"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, +{"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, +{"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, +{"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, +{"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, +{"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, +{"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, + +{"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat }, +{"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, +{"fdsubd", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, +{"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, +{"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, +{"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, +{"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, +{"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, +{"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, +{"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, +{"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, +{"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, +{"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, + +{"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, +{"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, + +{"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, +{"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, + +{"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, +{"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, + +{"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, +{"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat }, +{"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, +{"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, +{"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, +{"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, +{"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, +{"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, +{"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, +{"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, + +{"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, +{"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, +{"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, +{"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, +{"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, +{"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, +{"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, +{"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, +{"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, + +{"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, + +{"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, +{"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b | mcfisa_c }, + +{"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, + +{"jra", 2, one(0060000), one(0177400), "Bb", m68000up | mcfisa_a }, +{"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, + +{"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, + +{"jbsr", 2, one(0060400), one(0177400), "Bs", m68000up | mcfisa_a }, +{"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, + +{"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, + +{"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32 | fido_a | m68060 }, + +{"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, +{"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, +{"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, +{"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 | fido_a }, + +{"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up }, +{"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up }, +{"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up }, +{"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up }, +{"lslw", 2, one(0161700), one(0177700), "~s", m68000up }, +{"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, + +{"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up }, +{"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up }, +{"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up }, +{"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up }, +{"lsrw", 2, one(0161300), one(0177700), "~s", m68000up }, +{"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, +{"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, + +{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, +{"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, +{"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, +{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, +{"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, +{"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac }, + +{"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,,accX. */ +{"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ +{"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ +{"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ +{"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ +{"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ + +{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, +{"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, +{"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, +{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, +{"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, +{"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0900), "RMRm", mcfmac }, + +{"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, +{"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, +{"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, +{"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, +{"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, +{"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, + +/* NOTE: The mcf5200 family programmer's reference manual does not + indicate the byte form of the movea instruction is invalid (as it + is on 68000 family cpus). However, experiments on the 5202 yeild + unexpected results. The value is copied, but it is not sign extended + (as is done with movea.w) and the top three bytes in the address + register are not disturbed. I don't know if this is the intended + behavior --- it could be a hole in instruction decoding (Motorola + decided not to trap all invalid instructions for performance reasons) + --- but I suspect that it is not. + + I reported this to Motorola ISD Technical Communications Support, + which replied that other coldfire assemblers reject movea.b. For + this reason I've decided to not allow moveab. + + jtc@cygnus.com - 97/01/24. */ + +{"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, + +{"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, + +{"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, +{"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, +{"movec", 4, one(0047172), one(0177777), "JjR1", m68010up }, +{"movec", 4, one(0047172), one(0177777), "#jR1", m68010up }, + +{"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up }, +{"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up }, +{"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up }, +{"movemw", 4, one(0046200), one(0177700), "s", m68000up }, +{"moveml", 4, one(0046300), one(0177700), ",accX. */ +{"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,,accX. */ +{"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,,accX. */ +{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ +{"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ +{"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ + +{"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, +{"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, +{"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, +{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, +{"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, +{"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0900), "RMRm", mcfmac }, + +{"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, +{"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, +{"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, +{"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, +{"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, +{"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, + +{"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a }, +{"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, +{"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a }, +{"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, + +{"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a }, +{"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up | cpu32 | fido_a }, +{"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a }, +{"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up | cpu32 | fido_a }, + +{"nbcd", 2, one(0044000), one(0177700), "$s", m68000up }, + +{"negb", 2, one(0042000), one(0177700), "$s", m68000up }, +{"negw", 2, one(0042100), one(0177700), "$s", m68000up }, +{"negl", 2, one(0042200), one(0177700), "$s", m68000up }, +{"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a}, + +{"negxb", 2, one(0040000), one(0177700), "$s", m68000up }, +{"negxw", 2, one(0040100), one(0177700), "$s", m68000up }, +{"negxl", 2, one(0040200), one(0177700), "$s", m68000up }, +{"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a}, + +{"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a}, + +{"notb", 2, one(0043000), one(0177700), "$s", m68000up }, +{"notw", 2, one(0043100), one(0177700), "$s", m68000up }, +{"notl", 2, one(0043200), one(0177700), "$s", m68000up }, +{"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a}, + +{"orib", 4, one(0000000), one(0177700), "#b$s", m68000up }, +{"orib", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{"oril", 6, one(0000200), one(0177700), "#l$s", m68000up }, +{"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, +{"ori", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{"ori", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{"ori", 4, one(0000174), one(0177777), "#wSs", m68000up }, + +/* The or opcode can generate the ori instruction. */ +{"orb", 4, one(0000000), one(0177700), "#b$s", m68000up }, +{"orb", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{"orb", 2, one(0100000), one(0170700), ";bDd", m68000up }, +{"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up }, +{"orw", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{"orw", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{"orw", 2, one(0100100), one(0170700), ";wDd", m68000up }, +{"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up }, +{"orl", 6, one(0000200), one(0177700), "#l$s", m68000up }, +{"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, +{"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a }, +{"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a }, +{"or", 4, one(0000074), one(0177777), "#bCs", m68000up }, +{"or", 4, one(0000100), one(0177700), "#w$s", m68000up }, +{"or", 4, one(0000174), one(0177777), "#wSs", m68000up }, +{"or", 2, one(0100100), one(0170700), ";wDd", m68000up }, +{"or", 2, one(0100500), one(0170700), "Dd~s", m68000up }, + +{"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up }, +{"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up }, + +{"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 }, +{"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 }, +{"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 }, +{"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 }, +{"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 }, +{"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 }, +{"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 }, +{"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 }, +{"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 }, +{"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 }, +{"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 }, +{"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 }, +{"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 }, +{"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 }, +{"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 }, +{"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 }, +{"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 }, +{"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 }, +{"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 }, +{"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 }, +{"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 }, +{"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 }, +{"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 }, +{"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 }, +{"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 }, +{"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 }, +{"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 }, +{"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 }, +{"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 }, +{"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 }, +{"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 }, +{"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 }, + +{"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, +{"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, + +{"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a }, + +{"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up }, +{"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, + +{"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, +{"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, +{"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, +{"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, +{"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, +{"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, +{"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up }, +{"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up }, + +{"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up }, +{"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up }, +{"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up }, + +{"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, + +{"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, +{"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, +{"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, +{"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, +{"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, +{"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, + +{"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, +{"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, +{"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, +{"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, + +{"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 }, +{"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 }, + +{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, +{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, +{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, +{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, +{"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 }, +{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 }, +{"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, +{"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, +{"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, +{"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, + +{"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, +{"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, +{"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, + +{"prestore", 2, one(0xf140), one(0xffc0), "s", m68851 }, + +{"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, +{"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, +{"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, +{"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, +{"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, +{"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, +{"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, +{"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, +{"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, +{"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, +{"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, +{"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, +{"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, +{"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, +{"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, +{"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, + +{"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, +{"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 }, + +{"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, +{"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, +{"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, +{"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, +{"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, +{"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, +{"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 }, + +{"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, + +{"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, +{"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, +{"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, + +{"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, +{"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, + +{"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, +{"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, +{"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, + +{"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a }, + +{"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, +{"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, + + /* FIXME: don't allow Dw==Dx. */ +{"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, +{"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, + +{"reset", 2, one(0047160), one(0177777), "", m68000up }, + +{"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up }, +{"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up }, +{"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up }, +{"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up }, +{"rolw", 2, one(0163700), one(0177700), "~s", m68000up }, +{"roll", 2, one(0160630), one(0170770), "QdDs", m68000up }, +{"roll", 2, one(0160670), one(0170770), "DdDs", m68000up }, + +{"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up }, +{"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up }, +{"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up }, +{"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up }, +{"rorw", 2, one(0163300), one(0177700), "~s", m68000up }, +{"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up }, +{"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up }, + +{"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up }, +{"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up }, +{"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up }, +{"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up }, +{"roxlw", 2, one(0162700), one(0177700), "~s", m68000up }, +{"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up }, +{"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up }, + +{"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up }, +{"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up }, +{"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up }, +{"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up }, +{"roxrw", 2, one(0162300), one(0177700), "~s", m68000up }, +{"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up }, +{"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up }, + +{"rtd", 4, one(0047164), one(0177777), "#w", m68010up }, + +{"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a }, + +{"rtm", 2, one(0003300), one(0177760), "Rs", m68020 }, + +{"rtr", 2, one(0047167), one(0177777), "", m68000up }, + +{"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, + +{"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b | mcfisa_c }, + +{"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, +{"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, + +{"stldsr", 6, two(0x40e7, 0x46fc), two(0xffff, 0xffff), "#w", mcfisa_aa | mcfisa_c }, + + /* Traps have to come before conditional sets, as they have a more + specific opcode. */ +{"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"tpf", 2, one(0050774), one(0177777), "", mcfisa_a }, +{"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | fido_a | mcfisa_a }, +{"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 | fido_a }, +{"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 | fido_a }, + +{"trapccw", 4, one(0052372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"tpfw", 4, one(0050772), one(0177777), "#w", mcfisa_a}, +{"trapfw", 4, one(0050772), one(0177777), "#w", m68020up | cpu32 | fido_a | mcfisa_a}, +{"trapgew", 4, one(0056372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"traphiw", 4, one(0051372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"traplew", 4, one(0057772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"traplsw", 4, one(0051772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapltw", 4, one(0056772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapnew", 4, one(0053372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapplw", 4, one(0055372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"traptw", 4, one(0050372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up | cpu32 | fido_a }, +{"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up | cpu32 | fido_a }, + +{"trapccl", 6, one(0052373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapeql", 6, one(0053773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"tpfl", 6, one(0050773), one(0177777), "#l", mcfisa_a}, +{"trapfl", 6, one(0050773), one(0177777), "#l", m68020up | cpu32 | fido_a | mcfisa_a}, +{"trapgel", 6, one(0056373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"traphil", 6, one(0051373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"traplel", 6, one(0057773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"traplsl", 6, one(0051773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapltl", 6, one(0056773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapmil", 6, one(0055773), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapnel", 6, one(0053373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trappll", 6, one(0055373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"traptl", 6, one(0050373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up | cpu32 | fido_a }, +{"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up | cpu32 | fido_a }, + +{"trapv", 2, one(0047166), one(0177777), "", m68000up }, + +{"scc", 2, one(0052300), one(0177700), "$s", m68000up }, +{"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a }, +{"scs", 2, one(0052700), one(0177700), "$s", m68000up }, +{"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a }, +{"seq", 2, one(0053700), one(0177700), "$s", m68000up }, +{"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a }, +{"sf", 2, one(0050700), one(0177700), "$s", m68000up }, +{"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a }, +{"sge", 2, one(0056300), one(0177700), "$s", m68000up }, +{"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a }, +{"sgt", 2, one(0057300), one(0177700), "$s", m68000up }, +{"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a }, +{"shi", 2, one(0051300), one(0177700), "$s", m68000up }, +{"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a }, +{"sle", 2, one(0057700), one(0177700), "$s", m68000up }, +{"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a }, +{"sls", 2, one(0051700), one(0177700), "$s", m68000up }, +{"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a }, +{"slt", 2, one(0056700), one(0177700), "$s", m68000up }, +{"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a }, +{"smi", 2, one(0055700), one(0177700), "$s", m68000up }, +{"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a }, +{"sne", 2, one(0053300), one(0177700), "$s", m68000up }, +{"sne", 2, one(0053300), one(0177770), "Ds", mcfisa_a }, +{"spl", 2, one(0055300), one(0177700), "$s", m68000up }, +{"spl", 2, one(0055300), one(0177770), "Ds", mcfisa_a }, +{"st", 2, one(0050300), one(0177700), "$s", m68000up }, +{"st", 2, one(0050300), one(0177770), "Ds", mcfisa_a }, +{"svc", 2, one(0054300), one(0177700), "$s", m68000up }, +{"svc", 2, one(0054300), one(0177770), "Ds", mcfisa_a }, +{"svs", 2, one(0054700), one(0177700), "$s", m68000up }, +{"svs", 2, one(0054700), one(0177770), "Ds", mcfisa_a }, + +{"sleep", 2, one(0047170), one(0177777), "", fido_a }, + +{"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a }, + +{"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa}, + +{"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up }, + +{"subib", 4, one(0002000), one(0177700), "#b$s", m68000up }, +{"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up }, +{"subil", 6, one(0002200), one(0177700), "#l$s", m68000up }, +{"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, + +{"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, +{"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, +{"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, + +/* The sub opcode can generate the suba, subi, and subq instructions. */ +{"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, +{"subb", 4, one(0002000), one(0177700), "#b$s", m68000up }, +{"subb", 2, one(0110000), one(0170700), ";bDd", m68000up }, +{"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up }, +{"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, +{"subw", 4, one(0002100), one(0177700), "#w$s", m68000up }, +{"subw", 2, one(0110300), one(0170700), "*wAd", m68000up }, +{"subw", 2, one(0110100), one(0170700), "*wDd", m68000up }, +{"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up }, +{"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, +{"subl", 6, one(0002200), one(0177700), "#l$s", m68000up }, +{"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, +{"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, +{"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a }, +{"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a }, + +{"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up }, +{"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up }, +{"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up }, +{"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up }, +{"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a }, +{"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up }, + +{"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a }, + +/* swbeg and swbegl are magic constants used on sysV68. The compiler + generates them before a switch table. They tell the debugger and + disassembler that a switch table follows. The parameter is the + number of elements in the table. swbeg means that the entries in + the table are word (2 byte) sized, and swbegl means that the + entries in the table are longword (4 byte) sized. */ +{"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, +{"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, + +{"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b | mcfisa_c}, + +#define TBL1(name,insn_size,signed,round,size) \ + {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ + two(0177700,0107777), "!sD1", cpu32 }, \ + {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \ + two(0177770,0107770), "DsD3D1", cpu32 } +#define TBL(name1, name2, name3, s, r) \ + TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2) +TBL("tblsb", "tblsw", "tblsl", 1, 1), +TBL("tblsnb", "tblsnw", "tblsnl", 1, 0), +TBL("tblub", "tbluw", "tblul", 0, 1), +TBL("tblunb", "tblunw", "tblunl", 0, 0), + +{"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a }, + +{"trapx", 2, one(0047060), one(0177760), "Ts", fido_a }, + +{"tstb", 2, one(0045000), one(0177700), ";b", m68020up | cpu32 | fido_a | mcfisa_a }, +{"tstb", 2, one(0045000), one(0177700), "$b", m68000up }, +{"tstw", 2, one(0045100), one(0177700), "*w", m68020up | cpu32 | fido_a | mcfisa_a }, +{"tstw", 2, one(0045100), one(0177700), "$w", m68000up }, +{"tstl", 2, one(0045200), one(0177700), "*l", m68020up | cpu32 | fido_a | mcfisa_a }, +{"tstl", 2, one(0045200), one(0177700), "$l", m68000up }, + +{"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a }, + +{"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up }, +{"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up }, + +{"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a }, +{"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a }, +{"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a }, + +{"wdebugl", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, +{"wdebugl", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, +{"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, +{"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, +}; + +const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; + +/* These aliases used to be in the above table, each one duplicating + all of the entries for its primary exactly. This table was + constructed by mechanical processing of the opcode table, with a + small number of tweaks done by hand. There are probably a lot more + aliases above that could be moved down here, except for very minor + differences. */ + +const struct m68k_opcode_alias m68k_opcode_aliases[] = +{ + { "add", "addw", }, + { "adda", "addaw", }, + { "addi", "addiw", }, + { "addq", "addqw", }, + { "addx", "addxw", }, + { "asl", "aslw", }, + { "asr", "asrw", }, + { "bhi", "bhiw", }, + { "bls", "blsw", }, + { "bcc", "bccw", }, + { "bcs", "bcsw", }, + { "bne", "bnew", }, + { "beq", "beqw", }, + { "bvc", "bvcw", }, + { "bvs", "bvsw", }, + { "bpl", "bplw", }, + { "bmi", "bmiw", }, + { "bge", "bgew", }, + { "blt", "bltw", }, + { "bgt", "bgtw", }, + { "ble", "blew", }, + { "bra", "braw", }, + { "bsr", "bsrw", }, + { "bhib", "bhis", }, + { "blsb", "blss", }, + { "bccb", "bccs", }, + { "bcsb", "bcss", }, + { "bneb", "bnes", }, + { "beqb", "beqs", }, + { "bvcb", "bvcs", }, + { "bvsb", "bvss", }, + { "bplb", "bpls", }, + { "bmib", "bmis", }, + { "bgeb", "bges", }, + { "bltb", "blts", }, + { "bgtb", "bgts", }, + { "bleb", "bles", }, + { "brab", "bras", }, + { "bsrb", "bsrs", }, + { "bhs", "bccw" }, + { "bhss", "bccs" }, + { "bhsb", "bccs" }, + { "bhsw", "bccw" }, + { "bhsl", "bccl" }, + { "blo", "bcsw" }, + { "blos", "bcss" }, + { "blob", "bcss" }, + { "blow", "bcsw" }, + { "blol", "bcsl" }, + { "br", "braw", }, + { "brs", "bras", }, + { "brb", "bras", }, + { "brw", "braw", }, + { "brl", "bral", }, + { "jfnlt", "bcc", }, /* Apparently a sun alias. */ + { "jfngt", "ble", }, /* Apparently a sun alias. */ + { "jfeq", "beqs", }, /* Apparently a sun alias. */ + { "bchgb", "bchg", }, + { "bchgl", "bchg", }, + { "bclrb", "bclr", }, + { "bclrl", "bclr", }, + { "bsetb", "bset", }, + { "bsetl", "bset", }, + { "btstb", "btst", }, + { "btstl", "btst", }, + { "cas2", "cas2w", }, + { "cas", "casw", }, + { "chk2", "chk2w", }, + { "chk", "chkw", }, + { "clr", "clrw", }, + { "cmp2", "cmp2w", }, + { "cmpa", "cmpaw", }, + { "cmpi", "cmpiw", }, + { "cmpm", "cmpmw", }, + { "cmp", "cmpw", }, + { "dbccw", "dbcc", }, + { "dbcsw", "dbcs", }, + { "dbeqw", "dbeq", }, + { "dbfw", "dbf", }, + { "dbgew", "dbge", }, + { "dbgtw", "dbgt", }, + { "dbhiw", "dbhi", }, + { "dblew", "dble", }, + { "dblsw", "dbls", }, + { "dbltw", "dblt", }, + { "dbmiw", "dbmi", }, + { "dbnew", "dbne", }, + { "dbplw", "dbpl", }, + { "dbtw", "dbt", }, + { "dbvcw", "dbvc", }, + { "dbvsw", "dbvs", }, + { "dbhs", "dbcc", }, + { "dbhsw", "dbcc", }, + { "dbra", "dbf", }, + { "dbraw", "dbf", }, + { "tdivsl", "divsl", }, + { "divs", "divsw", }, + { "divu", "divuw", }, + { "ext", "extw", }, + { "extbw", "extw", }, + { "extwl", "extl", }, + { "fbneq", "fbne", }, + { "fbsneq", "fbsne", }, + { "fdbneq", "fdbne", }, + { "fdbsneq", "fdbsne", }, + { "fmovecr", "fmovecrx", }, + { "fmovm", "fmovem", }, + { "fsneq", "fsne", }, + { "fssneq", "fssne", }, + { "ftrapneq", "ftrapne", }, + { "ftrapsneq", "ftrapsne", }, + { "fjneq", "fjne", }, + { "fjsneq", "fjsne", }, + { "jmpl", "jmp", }, + { "jmps", "jmp", }, + { "jsrl", "jsr", }, + { "jsrs", "jsr", }, + { "leal", "lea", }, + { "lsl", "lslw", }, + { "lsr", "lsrw", }, + { "mac", "macw" }, + { "movea", "moveaw", }, + { "movem", "movemw", }, + { "movml", "moveml", }, + { "movmw", "movemw", }, + { "movm", "movemw", }, + { "movep", "movepw", }, + { "movpw", "movepw", }, + { "moves", "movesw" }, + { "muls", "mulsw", }, + { "mulu", "muluw", }, + { "msac", "msacw" }, + { "nbcdb", "nbcd" }, + { "neg", "negw", }, + { "negx", "negxw", }, + { "not", "notw", }, + { "peal", "pea", }, + { "rol", "rolw", }, + { "ror", "rorw", }, + { "roxl", "roxlw", }, + { "roxr", "roxrw", }, + { "sats", "satsl", }, + { "sbcdb", "sbcd", }, + { "sccb", "scc", }, + { "scsb", "scs", }, + { "seqb", "seq", }, + { "sfb", "sf", }, + { "sgeb", "sge", }, + { "sgtb", "sgt", }, + { "shib", "shi", }, + { "sleb", "sle", }, + { "slsb", "sls", }, + { "sltb", "slt", }, + { "smib", "smi", }, + { "sneb", "sne", }, + { "splb", "spl", }, + { "stb", "st", }, + { "svcb", "svc", }, + { "svsb", "svs", }, + { "sfge", "sge", }, + { "sfgt", "sgt", }, + { "sfle", "sle", }, + { "sflt", "slt", }, + { "sfneq", "sne", }, + { "suba", "subaw", }, + { "subi", "subiw", }, + { "subq", "subqw", }, + { "sub", "subw", }, + { "subx", "subxw", }, + { "swapw", "swap", }, + { "tasb", "tas", }, + { "tpcc", "trapcc", }, + { "tcc", "trapcc", }, + { "tst", "tstw", }, + { "jbra", "jra", }, + { "jbhi", "jhi", }, + { "jbls", "jls", }, + { "jbcc", "jcc", }, + { "jbcs", "jcs", }, + { "jbne", "jne", }, + { "jbeq", "jeq", }, + { "jbvc", "jvc", }, + { "jbvs", "jvs", }, + { "jbpl", "jpl", }, + { "jbmi", "jmi", }, + { "jbge", "jge", }, + { "jblt", "jlt", }, + { "jbgt", "jgt", }, + { "jble", "jle", }, + { "movql", "moveq", }, + { "moveql", "moveq", }, + { "movl", "movel", }, + { "movq", "moveq", }, + { "moval", "moveal", }, + { "movaw", "moveaw", }, + { "movb", "moveb", }, + { "movc", "movec", }, + { "movecl", "movec", }, + { "movpl", "movepl", }, + { "movw", "movew", }, + { "movsb", "movesb", }, + { "movsl", "movesl", }, + { "movsw", "movesw", }, + { "mov3q", "mov3ql", }, + + { "tdivul", "divul", }, /* For m68k-svr4. */ + { "fmovb", "fmoveb", }, + { "fsmovb", "fsmoveb", }, + { "fdmovb", "fdmoveb", }, + { "fmovd", "fmoved", }, + { "fsmovd", "fsmoved", }, + { "fmovl", "fmovel", }, + { "fsmovl", "fsmovel", }, + { "fdmovl", "fdmovel", }, + { "fmovp", "fmovep", }, + { "fsmovp", "fsmovep", }, + { "fdmovp", "fdmovep", }, + { "fmovs", "fmoves", }, + { "fsmovs", "fsmoves", }, + { "fdmovs", "fdmoves", }, + { "fmovw", "fmovew", }, + { "fsmovw", "fsmovew", }, + { "fdmovw", "fdmovew", }, + { "fmovx", "fmovex", }, + { "fsmovx", "fsmovex", }, + { "fdmovx", "fdmovex", }, + { "fmovcr", "fmovecr", }, + { "fmovcrx", "fmovecrx", }, + { "ftestb", "ftstb", }, + { "ftestd", "ftstd", }, + { "ftestl", "ftstl", }, + { "ftestp", "ftstp", }, + { "ftests", "ftsts", }, + { "ftestw", "ftstw", }, + { "ftestx", "ftstx", }, + + { "bitrevl", "bitrev", }, + { "byterevl", "byterev", }, + { "ff1l", "ff1", }, + +}; + +const int m68k_numaliases = + sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0]; diff --git a/external/gpl3/gdb/dist/opcodes/m88k-dis.c b/external/gpl3/gdb/dist/opcodes/m88k-dis.c new file mode 100644 index 000000000000..181ae3076c2b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/m88k-dis.c @@ -0,0 +1,763 @@ +/* Print instructions for the Motorola 88000, for GDB and GNU Binutils. + Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001, + 2002, 2005, 2007, 2008 Free Software Foundation, Inc. + Contributed by Data General Corporation, November 1989. + Partially derived from an earlier printcmd.c. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/m88k.h" +#include "opintl.h" +#include "libiberty.h" + +typedef struct HASHTAB +{ + const INSTAB *instr; + struct HASHTAB *next; +} HASHTAB; + +/* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec Simflags Next */ + +const INSTAB instructions[] = +{ + {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} }, + {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} }, + {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} }, + {0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0} }, + {0xc8000000,"bsr ",{0,26,PCREL},NO_OPERAND ,NO_OPERAND , {2,2,NA,BSR , i26bit,0,0,0,0,0,0,1,0,0,0,0} }, + {0xcc000000,"bsr.n ",{0,26,PCREL},NO_OPERAND ,NO_OPERAND , {1,1,NA,BSR , i26bit,0,0,0,0,0,1,1,0,0,0,0} }, + {0xc0000000,"br ",{0,26,PCREL},NO_OPERAND ,NO_OPERAND , {2,2,NA,BR , i26bit,0,0,0,0,0,0,1,0,0,0,0} }, + {0xc4000000,"br.n ",{0,26,PCREL},NO_OPERAND ,NO_OPERAND , {1,1,NA,BR , i26bit,0,0,0,0,0,1,1,0,0,0,0} }, + {0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, + {0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, + {0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB1 , i10bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xe8000000,"bcnd ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND, i16bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xec000000,"bcnd.n ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND, i16bit,0,1,0,0,0,1,1,0,0,0,0} }, + {0xf000e800,"tcnd ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND, i10bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xf8000000,"tbnd ",{16,5,REG} ,{0,16,HEX} ,NO_OPERAND , {2,2,NA,TBND, i10bit,1,0,0,0,0,0,1,0,0,0,0} }, + {0xf400f800,"tbnd ",{16,5,REG} ,{0,5,REG} ,NO_OPERAND , {2,2,NA,TBND, 0,1,1,0,0,0,0,1,0,0,0,0} }, + {0xf400fc00,"rte ",NO_OPERAND ,NO_OPERAND ,NO_OPERAND , {2,2,NA,RTE , 0,0,0,0,0,0,0,1,0,0,0,0} }, + {0x1c000000,"ld.b ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDB ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4001c00,"ld.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDB , 0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x0c000000,"ld.bu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDBU, i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4000c00,"ld.bu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDBU ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x18000000,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDH ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4001800,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDH ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4001a00,"ld.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDH ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x08000000,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDHU, i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4000800,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDHU ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4000a00,"ld.hu ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDHU ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x14000000,"ld ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LD ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4001400,"ld ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4001600,"ld ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x10000000,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,LDD ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4001000,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LDD ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4001200,"ld.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LDD ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0xf4001500,"ld.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4001700,"ld.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,LD ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x2c000000,"st.b ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STB ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4002c00,"st.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STB ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x28000000,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STH ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4002800,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STH ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4002a00,"st.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,STH ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x24000000,"st ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,ST ,i16bit,1,0,1,0,0,0,1,0,0,0,0} }, + {0xf4002400,"st ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4002600,"st ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0x20000000,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,NA,STD ,i16bit,0,1,0,0,0,0,1,0,0,0,0} }, + {0xf4002000,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,STD ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4002200,"st.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,STD ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0xf4002500,"st.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4002700,"st.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,NA,ST ,0,1,1,1,0,0,0,1,0,0,0,1} }, +/* m88100 only: + {0x00000000,"xmem.bu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0} }, + */ + {0xf4000000,"xmem.bu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} }, +/* m88100 only: + {0x04000000,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {3,1,PMEM,XMEM ,i16bit,1,1,1,0,0,0,1,0,0,0,0} }, + */ + {0xf4000400,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4000600,"xmem ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,1} }, + {0xf4000500,"xmem.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0xf4000700,"xmem.usr ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{3,1,PMEM,XMEM ,0,1,1,1,0,0,0,1,0,0,0,1} }, +/* m88100 only: + {0xf4003e00,"lda.b ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} }, + */ + {0xf4003e00,"lda.x ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} }, + {0xf4003a00,"lda.h ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAH, 0,1,1,1,0,0,0,0,0,0,0,1} }, + {0xf4003600,"lda ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDA , 0,1,1,1,0,0,0,0,0,0,0,1} }, + {0xf4003200,"lda.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REGSC},{1,1,PINT,LDAD, 0,1,1,1,0,0,0,0,0,0,0,1} }, + + {0x80004000,"ldcr ",{21,5,REG} ,{5,6,CRREG} ,NO_OPERAND ,{1,1,PINT,LDCR, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0x80008000,"stcr ",{16,5,REG} ,{5,6,CRREG} ,NO_OPERAND ,{1,1,PINT,STCR, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0x8000c000,"xcr ",{21,5,REG} ,{16,5,REG} ,{5,6,CRREG},{1,1,PINT,XCR, 0,1,1,1,0,0,0,0,0,0,0,0} }, + + {0xf4006000,"addu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006200,"addu.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006100,"addu.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006300,"addu.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADDU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006400,"subu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006600,"subu.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006500,"subu.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006700,"subu.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUBU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006800,"divu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {32,32,PINT,DIVU, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4006900,"divu.d ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,} }, + {0xf4006e00,"muls ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,} }, + {0xf4006c00,"mulu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,4,PINT,MUL, 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007000,"add ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007200,"add.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007100,"add.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007300,"add.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ADD , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007400,"sub ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007600,"sub.ci ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007500,"sub.co ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007700,"sub.cio ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SUB , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007800,"divs ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {32,32,PINT,DIV , 0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4007c00,"cmp ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,CMP, 0,1,1,1,0,0,0,0,0,0,0,0} }, + + {0x60000000,"addu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,ADDU, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x64000000,"subu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,SUBU, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + + {0x68000000,"divu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x6c000000,"mulu ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {4,1,PINT,MUL, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x70000000,"add ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,ADD, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x74000000,"sub ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,SUB, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x78000000,"divs ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {32,32,PINT,DIV, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x7c000000,"cmp ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,CMP, i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + + {0xf4004000,"and ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,AND_ ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4004400,"and.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,AND_ ,0,1,1,1,1,0,0,0,0,0,0,0} }, + {0xf4005800,"or ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,OR ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4005c00,"or.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,OR ,0,1,1,1,1,0,0,0,0,0,0,0} }, + {0xf4005000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4005400,"xor.c ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,XOR ,0,1,1,1,1,0,0,0,0,0,0,0} }, + {0x40000000,"and ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,AND_ ,i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x44000000,"and.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,AND_ ,i16bit,1,0,1,0,1,0,0,0,0,0,0} }, + {0x58000000,"or ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,OR ,i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x5c000000,"or.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,OR ,i16bit,1,0,1,0,1,0,0,0,0,0,0} }, + {0x50000000,"xor ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x54000000,"xor.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,XOR ,i16bit,1,0,1,0,1,0,0,0,0,0,0} }, + {0x48000000,"mask ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,MASK ,i16bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0x4c000000,"mask.u ",{21,5,REG} ,{16,5,REG} ,{0,16,HEX}, {1,1,PINT,MASK ,i16bit,1,0,1,0,1,0,0,0,0,0,0} }, + {0xf400ec00,"ff0 ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {1,1,PINT,FF0 ,0,0,1,1,0,0,0,0,0,0,0,0} }, + {0xf400e800,"ff1 ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {1,1,PINT,FF1 ,0,0,1,1,0,0,0,0,0,0,0,0} }, + {0xf0008000,"clr ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,CLR ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf0008800,"set ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,SET ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf0009000,"ext ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,EXT ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf0009800,"extu ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,EXTU ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf000a000,"mak ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,MAK ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf000a800,"rot ",{21,5,REG} ,{16,5,REG} ,{0,10,BF} , {1,1,PINT,ROT ,i10bit,1,0,1,0,0,0,0,0,0,0,0} }, + {0xf4008000,"clr ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,CLR ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4008800,"set ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,SET ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4009000,"ext ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,EXT ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf4009800,"extu ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,EXTU ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf400a000,"mak ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,MAK ,0,1,1,1,0,0,0,0,0,0,0,0} }, + {0xf400a800,"rot ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {1,1,PINT,ROT ,0,1,1,1,0,0,0,0,0,0,0,0} }, + + {0x84002800,"fadd.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FADD ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x84002880,"fadd.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,0,1,0} }, + {0x84002a00,"fadd.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,1,0,0} }, + {0x84002a80,"fadd.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,0,1,1,0} }, + {0x84002820,"fadd.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,0,0,0} }, + {0x840028a0,"fadd.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,0,1,0} }, + {0x84002a20,"fadd.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,1,0,0} }, + {0x84002aa0,"fadd.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FADD ,0,1,1,1,0,0,0,1,1,1,1,0} }, + {0x84003000,"fsub.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x84003080,"fsub.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,1,0} }, + {0x84003200,"fsub.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,0,0} }, + {0x84003280,"fsub.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,1,0} }, + {0x84003020,"fsub.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,0,0} }, + {0x840030a0,"fsub.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,1,0} }, + {0x84003220,"fsub.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,0,0} }, + {0x840032a0,"fsub.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,1,1,0} }, + {0x84000000,"fmul.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x84000080,"fmul.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,0,1,0} }, + {0x84000200,"fmul.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,0,0} }, + {0x84000280,"fmul.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,0,1,1,0} }, + {0x84000020,"fmul.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,0,0} }, + {0x840000a0,"fmul.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,0,1,0} }, + {0x84000220,"fmul.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,0,0} }, + {0x840002a0,"fmul.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {9,2,PFLT,FMUL ,0,1,1,1,0,0,0,1,1,1,1,0} }, + {0x84007000,"fdiv.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {30,30,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x84007080,"fdiv.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,0,1,0} }, + {0x84007200,"fdiv.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,1,0,0} }, + {0x84007280,"fdiv.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,0,1,1,0} }, + {0x84007020,"fdiv.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,0,0,0} }, + {0x840070a0,"fdiv.dsd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,0,1,0} }, + {0x84007220,"fdiv.dds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,1,0,0} }, + {0x840072a0,"fdiv.ddd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {60,60,PFLT,FDIV ,0,1,1,1,0,0,0,1,1,1,1,0} }, + {0x84007800,"fsqrt.ss ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84007820,"fsqrt.sd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84007880,"fsqrt.ds ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x840078a0,"fsqrt.dd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,FLT ,0,0,1,1,0,0,0,1,1,0,0,0} }, + {0x84003800,"fcmp.ss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,0,0,0,0} }, + {0x84003880,"fcmp.sd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,0,1,0,0} }, + {0x84003a00,"fcmp.ds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,1,0,0,0} }, + {0x84003a80,"fcmp.dd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,1,PFLT,FCMP ,0,1,1,1,0,0,0,1,1,1,0,0} }, + {0x84002000,"flt.s ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84002020,"flt.d ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,FLT ,0,0,1,1,0,0,0,1,1,0,0,0} }, + {0x84004800,"int.s ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,INT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84004880,"int.d ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,INT ,0,0,1,1,0,0,0,1,1,0,0,0} }, + {0x84005000,"nint.s ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,INT ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84005080,"nint.d ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,INT ,0,0,1,1,0,0,0,1,1,0,0,0} }, + {0x84005800,"trnc.s ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,TRNC ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x84005880,"trnc.d ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,TRNC ,0,0,1,1,0,0,0,1,1,0,0,0} }, + + {0x80004800,"fldcr ",{21,5,REG} ,{5,6,FCRREG} ,NO_OPERAND , {1,1,PFLT,FLDC ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x80008800,"fstcr ",{16,5,REG} ,{5,6,FCRREG} ,NO_OPERAND , {1,1,PFLT,FSTC ,0,0,1,1,0,0,0,1,0,0,0,0} }, + {0x8000c800,"fxcr ",{21,5,REG} ,{16,5,REG} ,{5,6,FCRREG} , {1,1,PFLT,FXC ,0,0,1,1,0,0,0,1,0,0,0,0} }, + +/* The following are new for the 88110. */ + + {0x8400aaa0,"fadd.ddd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aa80,"fadd.dds ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aac0,"fadd.ddx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aa20,"fadd.dsd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aa00,"fadd.dss ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aa40,"fadd.dsx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ab20,"fadd.dxd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ab00,"fadd.dxs ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ab40,"fadd.dxx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a8a0,"fadd.sdd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a880,"fadd.sds ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a8c0,"fadd.sdx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a820,"fadd.ssd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a800,"fadd.sss ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a840,"fadd.ssx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a920,"fadd.sxd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a900,"fadd.sxs ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400a940,"fadd.sxx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400aca0,"fadd.xdd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ac80,"fadd.xds ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400acc0,"fadd.xdx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ac20,"fadd.xsd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ac00,"fadd.xss ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ac40,"fadd.xsx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ad20,"fadd.xxd ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ad00,"fadd.xxs ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ad40,"fadd.xxx ",{21,5,XREG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x8400ba80,"fcmp.sdd ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ba00,"fcmp.sds ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400bb00,"fcmp.sdx ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400b880,"fcmp.ssd ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400b800,"fcmp.sss ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400b900,"fcmp.ssx ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400bc80,"fcmp.sxd ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400bc00,"fcmp.sxs ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400bd00,"fcmp.sxx ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x8400baa0,"fcmpu.sdd ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400ba20,"fcmpu.sds ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400bb20,"fcmpu.sdx ",{21,5,REG} ,{16,5,XREG} ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400b8a0,"fcmpu.ssd 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{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x88003060,"psub ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x880031e0,"psubs.s ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x880031a0,"psubs.s.b ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x880031c0,"psubs.s.h ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x880030e0,"psubs.u ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x880030a0,"psubs.u.b ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x880030c0,"psubs.u.h ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x88003160,"psubs.us ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x88003120,"psubs.us.b ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x88003140,"psubs.us.h ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x88006800,"punpk.n ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x88006820,"punpk.b ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x34000000,"st ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x30000000,"st.d ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x38000000,"st.x ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0xf4002c80,"st.b.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002880,"st.h.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002480,"st.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002080,"st.d.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002d80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002980,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002580,"st.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002180,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0xf0002400,"st ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002000,"st.d ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002100,"st.d.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002180,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002080,"st.d.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002500,"st.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002580,"st.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002480,"st.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002800,"st.x ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002900,"st.x.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002980,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002880,"st.x.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0xf4002f80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002e80,"st.b.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002380,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002280,"st.d.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002b80,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002a80,"st.h.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002780,"st.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf4002680,"st.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0xf0002600,"st ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002200,"st.d ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002300,"st.d.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002380,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002280,"st.d.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002700,"st.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002780,"st.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002680,"st.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002a00,"st.x ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002b00,"st.x.usr ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002b80,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0xf0002a80,"st.x.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + + {0x8400d880,"trnc.sd ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400d800,"trnc.ss ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + {0x8400d900,"trnc.sx ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }, + +}; + +HASHTAB *hashtable[HASHVAL] = {0}; + + +/* Initialize the disassembler instruction table. + + Initialize the hash table and instruction table for the + disassembler. This should be called once before the first call to + disasm(). */ + +static void +init_disasm (void) +{ + unsigned int hashvalue, hashsize; + struct HASHTAB *hashentries; + unsigned int i; + + hashsize = sizeof (instructions) / sizeof (INSTAB); + + hashentries = xmalloc (hashsize * sizeof (struct HASHTAB)); + + for (i = 0; i < HASHVAL; i++) + hashtable[i] = NULL; + + for (i = 0; i < hashsize; i++) + { + hashvalue = (instructions[i].opcode) % HASHVAL; + hashentries[i].instr = &instructions[i]; + hashentries[i].next = hashtable[hashvalue]; + hashtable[hashvalue] = &hashentries[i]; + } +} + +/* Decode an Operand of an instruction. + + This function formats and writes an operand of an instruction to + info based on the operand specification. When the `first' flag is + set this is the first operand of an instruction. Undefined operand + types cause a message. + + Parameters: + disassemble_info where the operand may be printed + OPSPEC *opptr pointer to an operand specification + UINT inst instruction from which operand is extracted + UINT pc pc of instruction; used for pc-relative disp. + int first flag which if nonzero indicates the first + operand of an instruction + + The operand specified is extracted from the instruction and is + written to buf in the format specified. The operand is preceded by + a comma if it is not the first operand of an instruction and it is + not a register indirect form. Registers are preceded by 'r' and + hex values by '0x'. */ + +static void +printop (struct disassemble_info *info, + const OPSPEC *opptr, + unsigned long inst, + bfd_vma pc, + int first) +{ + int extracted_field; + char *cond_mask_sym; + + if (opptr->width == 0) + return; + + if (! first) + { + switch (opptr->type) + { + case REGSC: + case CONT: + break; + default: + (*info->fprintf_func) (info->stream, ","); + break; + } + } + + switch (opptr->type) + { + case CRREG: + (*info->fprintf_func) (info->stream, "cr%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case FCRREG: + (*info->fprintf_func) (info->stream, "fcr%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case REGSC: + (*info->fprintf_func) (info->stream, "[r%d]", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case REG: + (*info->fprintf_func) (info->stream, "r%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case XREG: + (*info->fprintf_func) (info->stream, "x%d", + UEXT (inst, opptr->offset, opptr->width)); + break; + + case HEX: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + if (extracted_field == 0) + (*info->fprintf_func) (info->stream, "0"); + else + (*info->fprintf_func) (info->stream, "0x%02x", extracted_field); + break; + + case DEC: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + (*info->fprintf_func) (info->stream, "%d", extracted_field); + break; + + case CONDMASK: + extracted_field = UEXT (inst, opptr->offset, opptr->width); + switch (extracted_field & 0x0f) + { + case 0x1: cond_mask_sym = "gt0"; break; + case 0x2: cond_mask_sym = "eq0"; break; + case 0x3: cond_mask_sym = "ge0"; break; + case 0xc: cond_mask_sym = "lt0"; break; + case 0xd: cond_mask_sym = "ne0"; break; + case 0xe: cond_mask_sym = "le0"; break; + default: cond_mask_sym = NULL; break; + } + if (cond_mask_sym != NULL) + (*info->fprintf_func) (info->stream, "%s", cond_mask_sym); + else + (*info->fprintf_func) (info->stream, "%x", extracted_field); + break; + + case PCREL: + (*info->print_address_func) + (pc + (4 * (SEXT (inst, opptr->offset, opptr->width))), + info); + break; + + case CONT: + (*info->fprintf_func) (info->stream, "%d,r%d", + UEXT (inst, opptr->offset, 5), + UEXT (inst, (opptr->offset) + 5, 5)); + break; + + case BF: + (*info->fprintf_func) (info->stream, "%d<%d>", + UEXT (inst, (opptr->offset) + 5, 5), + UEXT (inst, opptr->offset, 5)); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _("# "), inst); + } +} + +/* Disassemble the instruction in `instruction'. + `pc' should be the address of this instruction, it will be used to + print the target address if this is a relative jump or call the + disassembled instruction is written to `info'. + + The function returns the length of this instruction in bytes. */ + +static int +m88kdis (bfd_vma pc, + unsigned long instruction, + struct disassemble_info *info) +{ + static int ihashtab_initialized = 0; + unsigned int opcode; + const HASHTAB *entry_ptr; + int opmask; + unsigned int in_class; + + if (! ihashtab_initialized) + { + init_disasm (); + ihashtab_initialized = 1; + } + + /* Create the appropriate mask to isolate the opcode. */ + opmask = DEFMASK; + in_class = instruction & DEFMASK; + if ((in_class >= SFU0) && (in_class <= SFU7)) + { + if (instruction < SFU1) + opmask = CTRLMASK; + else + opmask = SFUMASK; + } + else if (in_class == RRR) + opmask = RRRMASK; + else if (in_class == RRI10) + opmask = RRI10MASK; + + /* Isolate the opcode. */ + opcode = instruction & opmask; + + /* Search the hash table with the isolated opcode. */ + for (entry_ptr = hashtable[opcode % HASHVAL]; + (entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode); + entry_ptr = entry_ptr->next) + ; + + if (entry_ptr == NULL) + (*info->fprintf_func) (info->stream, "word\t%08lx", instruction); + else + { + (*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic); + printop (info, &(entry_ptr->instr->op1), instruction, pc, 1); + printop (info, &(entry_ptr->instr->op2), instruction, pc, 0); + printop (info, &(entry_ptr->instr->op3), instruction, pc, 0); + } + + return 4; +} + +/* Disassemble an M88000 instruction at `memaddr'. */ + +int +print_insn_m88k (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int status; + + /* Instruction addresses may have low two bits set. Clear them. */ + memaddr &=~ (bfd_vma) 3; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + return m88kdis (memaddr, bfd_getb32 (buffer), info); +} diff --git a/external/gpl3/gdb/dist/opcodes/makefile.vms b/external/gpl3/gdb/dist/opcodes/makefile.vms new file mode 100644 index 000000000000..d11d54f665ac --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/makefile.vms @@ -0,0 +1,42 @@ +# +# Makefile for libopcodes under openVMS +# +# For use with gnu-make for vms +# +# Created by Klaus K"ampf, kkaempf@progis.de +# +# + +ifeq ($(ARCH),IA64) +OBJS=ia64-dis.obj,ia64-opc.obj +ARCHDEF="ARCH_ia64" +endif +ifeq ($(ARCH),ALPHA) +OBJS=alpha-dis.obj,alpha-opc.obj +ARCHDEF="ARCH_alpha" +endif +ifeq ($(ARCH),VAX) +OBJS=vax-dis.obj +ARCHDEF="ARCH_vax" +endif + +OBJS:=$(OBJS),dis-init.obj,dis-buf.obj,disassemble.obj + +ifeq ($(CC),gcc) +DEFS=/define=($(ARCHDEF)) +CFLAGS=/include=([],[-.include],[-.bfd])$(DEFS) +else +DEFS=/define=($(ARCHDEF)) +OPT=/noopt/debug +CFLAGS=$(OPT)/include=([],"../include",[-.bfd])$(DEFS)\ + /name=(as_is,shortened) +endif + +libopcodes.olb: $(OBJS) + purge + lib/create libopcodes *.obj + +clean: + $$ purge + $(RM) *.obj; + $(RM) libopcodes.olb; diff --git a/external/gpl3/gdb/dist/opcodes/mcore-dis.c b/external/gpl3/gdb/dist/opcodes/mcore-dis.c new file mode 100644 index 000000000000..39412663e540 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mcore-dis.c @@ -0,0 +1,318 @@ +/* Disassemble Motorola M*Core instructions. + Copyright 1993, 1999, 2000, 2001, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "mcore-opc.h" +#include "dis-asm.h" + +/* Mask for each mcore_opclass: */ +static const unsigned short imsk[] = { + /* O0 */ 0xFFFF, + /* OT */ 0xFFFC, + /* O1 */ 0xFFF0, + /* OC */ 0xFE00, + /* O2 */ 0xFF00, + /* X1 */ 0xFFF0, + /* OI */ 0xFE00, + /* OB */ 0xFE00, + + /* OMa */ 0xFFF0, + /* SI */ 0xFE00, + /* I7 */ 0xF800, + /* LS */ 0xF000, + /* BR */ 0xF800, + /* BL */ 0xFF00, + /* LR */ 0xF000, + /* LJ */ 0xFF00, + + /* RM */ 0xFFF0, + /* RQ */ 0xFFF0, + /* JSR */ 0xFFF0, + /* JMP */ 0xFFF0, + /* OBRa*/ 0xFFF0, + /* OBRb*/ 0xFF80, + /* OBRc*/ 0xFF00, + /* OBR2*/ 0xFE00, + + /* O1R1*/ 0xFFF0, + /* OMb */ 0xFF80, + /* OMc */ 0xFF00, + /* SIa */ 0xFE00, + + /* MULSH */ 0xFF00, + /* OPSR */ 0xFFF8, /* psrset/psrclr */ + + /* JC */ 0, /* JC,JU,JL don't appear in object */ + /* JU */ 0, + /* JL */ 0, + /* RSI */ 0, + /* DO21*/ 0, + /* OB2 */ 0 /* OB2 won't appear in object. */ +}; + +static const char *grname[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" +}; + +static const char X[] = "??"; + +static const char *crname[] = { + "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1", + "ss2", "ss3", "ss4", "gcr", "gsr", X, X, X, + X, X, X, X, X, X, X, X, + X, X, X, X, X, X, X, X +}; + +static const unsigned isiz[] = { 2, 0, 1, 0 }; + +int +print_insn_mcore (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + unsigned char ibytes[4]; + fprintf_ftype print_func = info->fprintf_func; + void *stream = info->stream; + unsigned short inst; + const mcore_opcode_info *op; + int status; + + info->bytes_per_chunk = 2; + + status = info->read_memory_func (memaddr, ibytes, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + inst = (ibytes[0] << 8) | ibytes[1]; + else if (info->endian == BFD_ENDIAN_LITTLE) + inst = (ibytes[1] << 8) | ibytes[0]; + else + abort (); + + /* Just a linear search of the table. */ + for (op = mcore_table; op->name != 0; op++) + if (op->inst == (inst & imsk[op->opclass])) + break; + + if (op->name == 0) + (*print_func) (stream, ".short 0x%04x", inst); + else + { + const char *name = grname[inst & 0x0F]; + + (*print_func) (stream, "%s", op->name); + + switch (op->opclass) + { + case O0: + break; + + case OT: + (*print_func) (stream, "\t%d", inst & 0x3); + break; + + case O1: + case JMP: + case JSR: + (*print_func) (stream, "\t%s", name); + break; + + case OC: + (*print_func) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); + break; + + case O1R1: + (*print_func) (stream, "\t%s, r1", name); + break; + + case MULSH: + case O2: + (*print_func) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); + break; + + case X1: + (*print_func) (stream, "\tr1, %s", name); + break; + + case OI: + (*print_func) (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); + break; + + case RM: + (*print_func) (stream, "\t%s-r15, (r0)", name); + break; + + case RQ: + (*print_func) (stream, "\tr4-r7, (%s)", name); + break; + + case OB: + case OBRa: + case OBRb: + case OBRc: + case SI: + case SIa: + case OMa: + case OMb: + case OMc: + (*print_func) (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); + break; + + case I7: + (*print_func) (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); + break; + + case LS: + (*print_func) (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF], + name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]); + break; + + case BR: + { + long val = inst & 0x3FF; + + if (inst & 0x400) + val |= 0xFFFFFC00; + + (*print_func) (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1))); + + if (strcmp (op->name, "bsr") == 0) + { + /* For bsr, we'll try to get a symbol for the target. */ + val = memaddr + 2 + (val << 1); + + if (info->print_address_func && val != 0) + { + (*print_func) (stream, "\t// "); + info->print_address_func (val, info); + } + } + } + break; + + case BL: + { + long val; + val = (inst & 0x000F); + (*print_func) (stream, "\t%s, 0x%lx", + grname[(inst >> 4) & 0xF], + (long) (memaddr - (val << 1))); + } + break; + + case LR: + { + unsigned long val; + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + break; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + val = (ibytes[3] << 24) | (ibytes[2] << 16) + | (ibytes[1] << 8) | (ibytes[0]); + else + val = (ibytes[0] << 24) | (ibytes[1] << 16) + | (ibytes[2] << 8) | (ibytes[3]); + + /* Removed [] around literal value to match ABI syntax 12/95. */ + (*print_func) (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val); + + if (val == 0) + (*print_func) (stream, "\t// from address pool at 0x%lx", + (long) (memaddr + 2 + + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + } + break; + + case LJ: + { + unsigned long val; + + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; + + status = info->read_memory_func (val, ibytes, 4, info); + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + break; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + val = (ibytes[3] << 24) | (ibytes[2] << 16) + | (ibytes[1] << 8) | (ibytes[0]); + else + val = (ibytes[0] << 24) | (ibytes[1] << 16) + | (ibytes[2] << 8) | (ibytes[3]); + + /* Removed [] around literal value to match ABI syntax 12/95. */ + (*print_func) (stream, "\t0x%lX", val); + /* For jmpi/jsri, we'll try to get a symbol for the target. */ + if (info->print_address_func && val != 0) + { + (*print_func) (stream, "\t// "); + info->print_address_func (val, info); + } + else + { + (*print_func) (stream, "\t// from address pool at 0x%lx", + (long) (memaddr + 2 + + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + } + } + break; + + case OPSR: + { + static char *fields[] = { + "af", "ie", "fe", "fe,ie", + "ee", "ee,ie", "ee,fe", "ee,fe,ie" + }; + + (*print_func) (stream, "\t%s", fields[inst & 0x7]); + } + break; + + default: + /* If the disassembler lags the instruction set. */ + (*print_func) (stream, "\tundecoded operands, inst is 0x%04x", inst); + break; + } + } + + /* Say how many bytes we consumed. */ + return 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/mcore-opc.h b/external/gpl3/gdb/dist/opcodes/mcore-opc.h new file mode 100644 index 000000000000..f69246f08871 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mcore-opc.h @@ -0,0 +1,211 @@ +/* Assembler instructions for Motorola's Mcore processor + Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "ansidecl.h" + +typedef enum +{ + O0, OT, O1, OC, O2, X1, OI, OB, + OMa, SI, I7, LS, BR, BL, LR, LJ, + RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2, + O1R1, OMb, OMc, SIa, + MULSH, OPSR, + JC, JU, JL, RSI, DO21, OB2 +} +mcore_opclass; + +typedef struct inst +{ + char * name; + mcore_opclass opclass; + unsigned char transfer; + unsigned short inst; +} +mcore_opcode_info; + +#ifdef DEFINE_TABLE +const mcore_opcode_info mcore_table[] = +{ + { "bkpt", O0, 0, 0x0000 }, + { "sync", O0, 0, 0x0001 }, + { "rte", O0, 1, 0x0002 }, + { "rfe", O0, 1, 0x0002 }, + { "rfi", O0, 1, 0x0003 }, + { "stop", O0, 0, 0x0004 }, + { "wait", O0, 0, 0x0005 }, + { "doze", O0, 0, 0x0006 }, + { "idly4", O0, 0, 0x0007 }, + { "trap", OT, 0, 0x0008 }, +/* SPACE: 0x000C - 0x000F */ +/* SPACE: 0x0010 - 0x001F */ + { "mvc", O1, 0, 0x0020 }, + { "mvcv", O1, 0, 0x0030 }, + { "ldq", RQ, 0, 0x0040 }, + { "stq", RQ, 0, 0x0050 }, + { "ldm", RM, 0, 0x0060 }, + { "stm", RM, 0, 0x0070 }, + { "dect", O1, 0, 0x0080 }, + { "decf", O1, 0, 0x0090 }, + { "inct", O1, 0, 0x00A0 }, + { "incf", O1, 0, 0x00B0 }, + { "jmp", JMP, 2, 0x00C0 }, +#define MCORE_INST_JMP 0x00C0 + { "jsr", JSR, 0, 0x00D0 }, +#define MCORE_INST_JSR 0x00E0 + { "ff1", O1, 0, 0x00E0 }, + { "brev", O1, 0, 0x00F0 }, + { "xtrb3", X1, 0, 0x0100 }, + { "xtrb2", X1, 0, 0x0110 }, + { "xtrb1", X1, 0, 0x0120 }, + { "xtrb0", X1, 0, 0x0130 }, + { "zextb", O1, 0, 0x0140 }, + { "sextb", O1, 0, 0x0150 }, + { "zexth", O1, 0, 0x0160 }, + { "sexth", O1, 0, 0x0170 }, + { "declt", O1, 0, 0x0180 }, + { "tstnbz", O1, 0, 0x0190 }, + { "decgt", O1, 0, 0x01A0 }, + { "decne", O1, 0, 0x01B0 }, + { "clrt", O1, 0, 0x01C0 }, + { "clrf", O1, 0, 0x01D0 }, + { "abs", O1, 0, 0x01E0 }, + { "not", O1, 0, 0x01F0 }, + { "movt", O2, 0, 0x0200 }, + { "mult", O2, 0, 0x0300 }, + { "loopt", BL, 0, 0x0400 }, + { "subu", O2, 0, 0x0500 }, + { "sub", O2, 0, 0x0500 }, /* Official alias. */ + { "addc", O2, 0, 0x0600 }, + { "subc", O2, 0, 0x0700 }, +/* SPACE: 0x0800-0x08ff for a diadic operation */ +/* SPACE: 0x0900-0x09ff for a diadic operation */ + { "movf", O2, 0, 0x0A00 }, + { "lsr", O2, 0, 0x0B00 }, + { "cmphs", O2, 0, 0x0C00 }, + { "cmplt", O2, 0, 0x0D00 }, + { "tst", O2, 0, 0x0E00 }, + { "cmpne", O2, 0, 0x0F00 }, + { "mfcr", OC, 0, 0x1000 }, + { "psrclr", OPSR, 0, 0x11F0 }, + { "psrset", OPSR, 0, 0x11F8 }, + { "mov", O2, 0, 0x1200 }, + { "bgenr", O2, 0, 0x1300 }, + { "rsub", O2, 0, 0x1400 }, + { "ixw", O2, 0, 0x1500 }, + { "and", O2, 0, 0x1600 }, + { "xor", O2, 0, 0x1700 }, + { "mtcr", OC, 0, 0x1800 }, + { "asr", O2, 0, 0x1A00 }, + { "lsl", O2, 0, 0x1B00 }, + { "addu", O2, 0, 0x1C00 }, + { "add", O2, 0, 0x1C00 }, /* Official alias. */ + { "ixh", O2, 0, 0x1D00 }, + { "or", O2, 0, 0x1E00 }, + { "andn", O2, 0, 0x1F00 }, + { "addi", OI, 0, 0x2000 }, +#define MCORE_INST_ADDI 0x2000 + { "cmplti", OI, 0, 0x2200 }, + { "subi", OI, 0, 0x2400 }, +/* SPACE: 0x2600-0x27ff open for a register+immediate operation */ + { "rsubi", OB, 0, 0x2800 }, + { "cmpnei", OB, 0, 0x2A00 }, + { "bmaski", OMa, 0, 0x2C00 }, + { "divu", O1R1, 0, 0x2C10 }, +/* SPACE: 0x2c20 - 0x2c7f */ + { "bmaski", OMb, 0, 0x2C80 }, + { "bmaski", OMc, 0, 0x2D00 }, + { "andi", OB, 0, 0x2E00 }, + { "bclri", OB, 0, 0x3000 }, +/* SPACE: 0x3200 - 0x320f */ + { "divs", O1R1, 0, 0x3210 }, +/* SPACE: 0x3220 - 0x326f */ + { "bgeni", OBRa, 0, 0x3270 }, + { "bgeni", OBRb, 0, 0x3280 }, + { "bgeni", OBRc, 0, 0x3300 }, + { "bseti", OB, 0, 0x3400 }, + { "btsti", OB, 0, 0x3600 }, + { "xsr", O1, 0, 0x3800 }, + { "rotli", SIa, 0, 0x3800 }, + { "asrc", O1, 0, 0x3A00 }, + { "asri", SIa, 0, 0x3A00 }, + { "lslc", O1, 0, 0x3C00 }, + { "lsli", SIa, 0, 0x3C00 }, + { "lsrc", O1, 0, 0x3E00 }, + { "lsri", SIa, 0, 0x3E00 }, +/* SPACE: 0x4000 - 0x5fff */ + { "movi", I7, 0, 0x6000 }, +#define MCORE_INST_BMASKI_ALT 0x6000 +#define MCORE_INST_BGENI_ALT 0x6000 + { "mulsh", MULSH, 0, 0x6800 }, + { "muls.h", MULSH, 0, 0x6800 }, +/* SPACE: 0x6900 - 0x6FFF */ + { "jmpi", LJ, 1, 0x7000 }, + { "jsri", LJ, 0, 0x7F00 }, +#define MCORE_INST_JMPI 0x7000 + { "lrw", LR, 0, 0x7000 }, +#define MCORE_INST_JSRI 0x7F00 + { "ld", LS, 0, 0x8000 }, + { "ldw", LS, 0, 0x8000 }, + { "ld.w", LS, 0, 0x8000 }, + { "st", LS, 0, 0x9000 }, + { "stw", LS, 0, 0x9000 }, + { "st.w", LS, 0, 0x9000 }, + { "ldb", LS, 0, 0xA000 }, + { "ld.b", LS, 0, 0xA000 }, + { "stb", LS, 0, 0xB000 }, + { "st.b", LS, 0, 0xB000 }, + { "ldh", LS, 0, 0xC000 }, + { "ld.h", LS, 0, 0xC000 }, + { "sth", LS, 0, 0xD000 }, + { "st.h", LS, 0, 0xD000 }, + { "bt", BR, 0, 0xE000 }, + { "bf", BR, 0, 0xE800 }, + { "br", BR, 1, 0xF000 }, +#define MCORE_INST_BR 0xF000 + { "bsr", BR, 0, 0xF800 }, +#define MCORE_INST_BSR 0xF800 + +/* The following are relaxable branches */ + { "jbt", JC, 0, 0xE000 }, + { "jbf", JC, 0, 0xE800 }, + { "jbr", JU, 1, 0xF000 }, + { "jbsr", JL, 0, 0xF800 }, + +/* The following are aliases for other instructions */ + { "rts", O0, 2, 0x00CF }, /* jmp r15 */ + { "rolc", DO21, 0, 0x0600 }, /* addc rd,rd */ + { "rotlc", DO21, 0, 0x0600 }, /* addc rd,rd */ + { "setc", O0, 0, 0x0C00 }, /* cmphs r0,r0 */ + { "clrc", O0, 0, 0x0F00 }, /* cmpne r0,r0 */ + { "tstle", O1, 0, 0x2200 }, /* cmplti rd,1 */ + { "cmplei", OB, 0, 0x2200 }, /* cmplei rd,X -> cmplti rd,X+1 */ + { "neg", O1, 0, 0x2800 }, /* rsubi rd,0 */ + { "tstne", O1, 0, 0x2A00 }, /* cmpnei rd,0 */ + { "tstlt", O1, 0, 0x37F0 }, /* btsti rx,31 */ + { "mclri", OB2, 0, 0x3000 }, /* bclri rx,log2(imm) */ + { "mgeni", OBR2, 0, 0x3200 }, /* bgeni rx,log2(imm) */ + { "mseti", OB2, 0, 0x3400 }, /* bseti rx,log2(imm) */ + { "mtsti", OB2, 0, 0x3600 }, /* btsti rx,log2(imm) */ + { "rori", RSI, 0, 0x3800 }, + { "rotri", RSI, 0, 0x3800 }, + { "nop", O0, 0, 0x1200 }, /* mov r0, r0 */ + { 0, 0, 0, 0 } +}; +#endif diff --git a/external/gpl3/gdb/dist/opcodes/mep-asm.c b/external/gpl3/gdb/dist/opcodes/mep-asm.c new file mode 100644 index 000000000000..2fc3087215ce --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-asm.c @@ -0,0 +1,1694 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +#include "elf/mep.h" + +#define CGEN_VALIDATE_INSN_SUPPORTED +#define mep_cgen_insn_supported mep_cgen_insn_supported_asm + + const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); + const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); +static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; +static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); +static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; +static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); +static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); +static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); + +const char * +parse_csrn (CGEN_CPU_DESC cd, const char **strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + unsigned long value; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (!err) + return NULL; + + err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); + if (err) + return err; + *field = value; + return NULL; +} + +/* begin-cop-ip-parse-handlers */ +static const char * +parse_ivc2_cr (CGEN_CPU_DESC, + const char **, + CGEN_KEYWORD *, + long *) ATTRIBUTE_UNUSED; +static const char * +parse_ivc2_cr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long *field) +{ + return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); +} +static const char * +parse_ivc2_ccr (CGEN_CPU_DESC, + const char **, + CGEN_KEYWORD *, + long *) ATTRIBUTE_UNUSED; +static const char * +parse_ivc2_ccr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long *field) +{ + return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); +} +/* end-cop-ip-parse-handlers */ + +const char * +parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (err) + return err; + if (*field != 13) + return _("Only $tp or $13 allowed for this opcode"); + return NULL; +} + +const char * +parse_spreg (CGEN_CPU_DESC cd, const char ** strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (err) + return err; + if (*field != 15) + return _("Only $sp or $15 allowed for this opcode"); + return NULL; +} + +const char * +parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, + enum cgen_operand_type type, long *field) +{ + long lsbs = 0; + const char *err; + + switch (type) + { + case MEP_OPERAND_PCREL8A2: + case MEP_OPERAND_PCREL12A2: + case MEP_OPERAND_PCREL17A2: + case MEP_OPERAND_PCREL24A2: + err = cgen_parse_signed_integer (cd, strp, type, field); + break; + case MEP_OPERAND_PCABS24A2: + case MEP_OPERAND_UDISP7: + case MEP_OPERAND_UDISP7A2: + case MEP_OPERAND_UDISP7A4: + case MEP_OPERAND_UIMM7A4: + case MEP_OPERAND_ADDR24A4: + err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); + break; + default: + abort(); + } + if (err) + return err; + switch (type) + { + case MEP_OPERAND_UDISP7: + lsbs = 0; + break; + case MEP_OPERAND_PCREL8A2: + case MEP_OPERAND_PCREL12A2: + case MEP_OPERAND_PCREL17A2: + case MEP_OPERAND_PCREL24A2: + case MEP_OPERAND_PCABS24A2: + case MEP_OPERAND_UDISP7A2: + lsbs = *field & 1; + break; + case MEP_OPERAND_UDISP7A4: + case MEP_OPERAND_UIMM7A4: + case MEP_OPERAND_ADDR24A4: + lsbs = *field & 3; + break; + lsbs = *field & 7; + break; + default: + /* Safe assumption? */ + abort (); + } + if (lsbs) + return "Value is not aligned enough"; + return NULL; +} + +const char * +parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, + enum cgen_operand_type type, unsigned long *field) +{ + return parse_mep_align (cd, strp, type, (long *) field); +} + + +/* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed + constants in a signed context. */ + +static const char * +parse_signed16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + return parse_lo16 (cd, strp, opindex, valuep, 1); +} + +static const char * +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep, + long signedp) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + if (signedp) + *valuep = (long)(short) value; + else + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (value + 0x8000) >> 16; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = value >> 16; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%sdaoff(", 8) == 0) + { + *strp += 8; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, + NULL, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + *strp += 7; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, + NULL, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return _("invalid %function() here"); + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_unsigned16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); +} + +static const char * +parse_signed16_range (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < -32768 || value > 32767) + return _("Immediate is out of range -32768 to 32767"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned16_range (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 65535) + return _("Immediate is out of range 0 to 65535"); + + *valuep = value; + return 0; +} + +/* A special case of parse_signed16 which accepts only the value zero. */ + +static const char * +parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ + + /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. + It will fail and cause ry to be listed as an undefined symbol in the + listing. */ + if (strncmp (*strp, "($", 2) == 0) + return "not zero"; /* any string will do -- will never be seen. */ + + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%sdaoff(", 8) == 0) + { + *strp += 8; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + *strp += 7; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return "invalid %function() here"; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, + &result_type, &value); + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + + return errmsg; +} + +static const char * +parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, + enum cgen_operand_type opindex, unsigned long *valuep) +{ + const char *errmsg; + bfd_vma value; + + /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + int reloc; + *strp += 7; + switch (opindex) + { + case MEP_OPERAND_UDISP7: + reloc = BFD_RELOC_MEP_TPREL7; + break; + case MEP_OPERAND_UDISP7A2: + reloc = BFD_RELOC_MEP_TPREL7A2; + break; + case MEP_OPERAND_UDISP7A4: + reloc = BFD_RELOC_MEP_TPREL7A4; + break; + default: + /* Safe assumption? */ + abort (); + } + errmsg = cgen_parse_address (cd, strp, opindex, reloc, + NULL, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return _("invalid %function() here"); + + return parse_mep_alignu (cd, strp, opindex, valuep); +} + +static ATTRIBUTE_UNUSED const char * +parse_cdisp10 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + int wide = 0; + int alignment; + + switch (opindex) + { + case MEP_OPERAND_CDISP10A4: + alignment = 2; + break; + case MEP_OPERAND_CDISP10A2: + alignment = 1; + break; + case MEP_OPERAND_CDISP10: + default: + alignment = 0; + break; + } + + if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) + wide = 1; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (wide) + { + if (value < -512 || value > 511) + return _("Immediate is out of range -512 to 511"); + } + else + { + if (value < -128 || value > 127) + return _("Immediate is out of range -128 to 127"); + } + + if (value & ((1<>16) & 0xffff)" }, */ +/*{ "lo", "(`1 & 0xffff)" }, */ +/*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ +/*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ + { 0,0 } +}; + +static char * expand_string (const char *, int); + +static const char * +mep_cgen_expand_macros_and_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +static char * +str_append (char *dest, const char *input, int len) +{ + char *new_dest; + int oldlen; + + if (len == 0) + return dest; + /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ + oldlen = (dest ? strlen(dest) : 0); + new_dest = realloc (dest, oldlen + len + 1); + memset (new_dest + oldlen, 0, len + 1); + return strncat (new_dest, input, len); +} + +static macro * +lookup_macro (const char *name) +{ + macro *m; + + for (m = macros; m->name; ++m) + if (strncmp (m->name, name, strlen(m->name)) == 0) + return m; + + return 0; +} + +static char * +expand_macro (arg *args, int narg, macro *mac) +{ + char *result = 0, *rescanned_result = 0; + char *e = mac->expansion; + char *mark = e; + int mac_arg = 0; + + /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ + while (*e) + { + if (*e == '`' && + (*e+1) && + ((*(e + 1) - '1') <= MAXARGS) && + ((*(e + 1) - '1') <= narg)) + { + result = str_append (result, mark, e - mark); + mac_arg = (*(e + 1) - '1'); + /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ + result = str_append (result, args[mac_arg].start, args[mac_arg].len); + ++e; + mark = e+1; + } + ++e; + } + + if (mark != e) + result = str_append (result, mark, e - mark); + + if (result) + { + rescanned_result = expand_string (result, 0); + free (result); + return rescanned_result; + } + else + return result; +} + +#define IN_TEXT 0 +#define IN_ARGS 1 + +static char * +expand_string (const char *in, int first_only) +{ + int num_expansions = 0; + int depth = 0; + int narg = -1; + arg args[MAXARGS]; + int state = IN_TEXT; + const char *mark = in; + macro *pmacro = NULL; + char *expansion = 0; + char *result = 0; + + while (*in) + { + switch (state) + { + case IN_TEXT: + if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) + { + pmacro = lookup_macro (in + 1); + if (pmacro) + { + /* printf("entering state %d at '%s'...\n", state, in); */ + result = str_append (result, mark, in - mark); + mark = in; + in += 1 + strlen (pmacro->name); + while (*in == ' ') ++in; + if (*in != '(') + { + state = IN_TEXT; + pmacro = NULL; + } + else + { + state = IN_ARGS; + narg = 0; + args[narg].start = in + 1; + args[narg].len = 0; + mark = in + 1; + } + } + } + break; + case IN_ARGS: + if (depth == 0) + { + switch (*in) + { + case ',': + narg++; + args[narg].start = (in + 1); + args[narg].len = 0; + break; + case ')': + state = IN_TEXT; + /* printf("entering state %d at '%s'...\n", state, in); */ + if (pmacro) + { + expansion = 0; + expansion = expand_macro (args, narg, pmacro); + num_expansions++; + if (expansion) + { + result = str_append (result, expansion, strlen (expansion)); + free (expansion); + } + } + else + { + result = str_append (result, mark, in - mark); + } + pmacro = NULL; + mark = in + 1; + break; + case '(': + depth++; + default: + args[narg].len++; + break; + } + } + else + { + if (*in == ')') + depth--; + if (narg > -1) + args[narg].len++; + } + + } + ++in; + } + + if (mark != in) + result = str_append (result, mark, in - mark); + + return result; +} + +#undef IN_ARGS +#undef IN_TEXT +#undef MAXARGS + + +/* END LIGHTWEIGHT MACRO PROCESSOR. */ + +const char * mep_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +const char * +mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, + const char ** strp_in, CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + char *str = 0, *hold = 0; + const char **strp = 0; + + /* Set up a new pointer to macro-expanded string. */ + str = expand_string (*strp_in, 1); + /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ + + hold = str; + strp = (const char **)(&str); + + errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); + + /* Now work out the advance. */ + if (strlen (str) == 0) + *strp_in += strlen (*strp_in); + + else + { + if (strstr (*strp_in, str)) + /* A macro-expansion was pulled off the front. */ + *strp_in = strstr (*strp_in, str); + else + /* A non-macro-expansion was pulled off the front. */ + *strp_in += (str - hold); + } + + if (hold) + free (hold); + + return errmsg; +} + +#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); + +/* -- dis.c */ + +const char * mep_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +mep_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_ADDR24A4, (unsigned long *) (& fields->f_24u8a4n)); + break; + case MEP_OPERAND_C5RMUIMM20 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RMUIMM20, (unsigned long *) (& fields->f_c5_rmuimm20)); + break; + case MEP_OPERAND_C5RNMUIMM24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_C5RNMUIMM24, (unsigned long *) (& fields->f_c5_rnmuimm24)); + break; + case MEP_OPERAND_CALLNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CALLNUM, (unsigned long *) (& fields->f_callnum)); + break; + case MEP_OPERAND_CCCC : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CCCC, (unsigned long *) (& fields->f_rm)); + break; + case MEP_OPERAND_CCRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ccrn); + break; + case MEP_OPERAND_CDISP10 : + errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10, (long *) (& fields->f_cdisp10)); + break; + case MEP_OPERAND_CDISP10A2 : + errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A2, (long *) (& fields->f_cdisp10)); + break; + case MEP_OPERAND_CDISP10A4 : + errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A4, (long *) (& fields->f_cdisp10)); + break; + case MEP_OPERAND_CDISP10A8 : + errmsg = parse_cdisp10 (cd, strp, MEP_OPERAND_CDISP10A8, (long *) (& fields->f_cdisp10)); + break; + case MEP_OPERAND_CDISP12 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP12, (long *) (& fields->f_12s20)); + break; + case MEP_OPERAND_CIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM4, (unsigned long *) (& fields->f_rn)); + break; + case MEP_OPERAND_CIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM5, (unsigned long *) (& fields->f_5u24)); + break; + case MEP_OPERAND_CODE16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CODE16, (unsigned long *) (& fields->f_16u16)); + break; + case MEP_OPERAND_CODE24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CODE24, (unsigned long *) (& fields->f_24u4n)); + break; + case MEP_OPERAND_CP_FLAG : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & junk); + break; + case MEP_OPERAND_CRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr, & fields->f_crn); + break; + case MEP_OPERAND_CRN64 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_crn); + break; + case MEP_OPERAND_CRNX : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr, & fields->f_crnx); + break; + case MEP_OPERAND_CRNX64 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_crnx); + break; + case MEP_OPERAND_CROC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u7); + break; + case MEP_OPERAND_CROP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u23); + break; + case MEP_OPERAND_CRPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u26); + break; + case MEP_OPERAND_CRPP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u18); + break; + case MEP_OPERAND_CRQC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u21); + break; + case MEP_OPERAND_CRQP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u13); + break; + case MEP_OPERAND_CSRN : + errmsg = parse_csrn (cd, strp, & mep_cgen_opval_h_csr, & fields->f_csrn); + break; + case MEP_OPERAND_CSRN_IDX : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, (unsigned long *) (& fields->f_csrn)); + break; + case MEP_OPERAND_DBG : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_DEPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_EPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_EXC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_HI : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_IMM16P0 : + errmsg = parse_unsigned16_range (cd, strp, MEP_OPERAND_IMM16P0, (unsigned long *) (& fields->f_ivc2_imm16p0)); + break; + case MEP_OPERAND_IMM3P12 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P12, (unsigned long *) (& fields->f_ivc2_3u12)); + break; + case MEP_OPERAND_IMM3P25 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P25, (unsigned long *) (& fields->f_ivc2_3u25)); + break; + case MEP_OPERAND_IMM3P4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P4, (unsigned long *) (& fields->f_ivc2_3u4)); + break; + case MEP_OPERAND_IMM3P5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P5, (unsigned long *) (& fields->f_ivc2_3u5)); + break; + case MEP_OPERAND_IMM3P9 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P9, (unsigned long *) (& fields->f_ivc2_3u9)); + break; + case MEP_OPERAND_IMM4P10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P10, (unsigned long *) (& fields->f_ivc2_4u10)); + break; + case MEP_OPERAND_IMM4P4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P4, (unsigned long *) (& fields->f_ivc2_4u4)); + break; + case MEP_OPERAND_IMM4P8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P8, (unsigned long *) (& fields->f_ivc2_4u8)); + break; + case MEP_OPERAND_IMM5P23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P23, (unsigned long *) (& fields->f_ivc2_5u23)); + break; + case MEP_OPERAND_IMM5P3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P3, (unsigned long *) (& fields->f_ivc2_5u3)); + break; + case MEP_OPERAND_IMM5P7 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P7, (unsigned long *) (& fields->f_ivc2_5u7)); + break; + case MEP_OPERAND_IMM5P8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P8, (unsigned long *) (& fields->f_ivc2_5u8)); + break; + case MEP_OPERAND_IMM6P2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM6P2, (unsigned long *) (& fields->f_ivc2_6u2)); + break; + case MEP_OPERAND_IMM6P6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM6P6, (unsigned long *) (& fields->f_ivc2_6u6)); + break; + case MEP_OPERAND_IMM8P0 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P0, (unsigned long *) (& fields->f_ivc2_8u0)); + break; + case MEP_OPERAND_IMM8P20 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P20, (unsigned long *) (& fields->f_ivc2_8u20)); + break; + case MEP_OPERAND_IMM8P4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P4, (unsigned long *) (& fields->f_ivc2_8u4)); + break; + case MEP_OPERAND_IVC_X_0_2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_2, (unsigned long *) (& fields->f_ivc2_2u0)); + break; + case MEP_OPERAND_IVC_X_0_3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_3, (unsigned long *) (& fields->f_ivc2_3u0)); + break; + case MEP_OPERAND_IVC_X_0_4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_4, (unsigned long *) (& fields->f_ivc2_4u0)); + break; + case MEP_OPERAND_IVC_X_0_5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_5, (unsigned long *) (& fields->f_ivc2_5u0)); + break; + case MEP_OPERAND_IVC_X_6_1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_1, (unsigned long *) (& fields->f_ivc2_1u6)); + break; + case MEP_OPERAND_IVC_X_6_2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_2, (unsigned long *) (& fields->f_ivc2_2u6)); + break; + case MEP_OPERAND_IVC_X_6_3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6)); + break; + case MEP_OPERAND_IVC2_ACC0_0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_2 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_3 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_4 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_5 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_6 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC0_7 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_2 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_3 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_4 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_5 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_6 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_ACC1_7 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_CC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_COFA0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_COFA1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_COFR0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_COFR1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_CSAR0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2_CSAR1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk); + break; + case MEP_OPERAND_IVC2C3CCRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn_c3); + break; + case MEP_OPERAND_IVC2CCRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn); + break; + case MEP_OPERAND_IVC2CRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_crnx); + break; + case MEP_OPERAND_IVC2RM : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_ivc2_crm); + break; + case MEP_OPERAND_LO : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_LP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_MB0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_MB1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_ME0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_ME1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_NPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_OPT : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_PCABS24A2 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_PCABS24A2, (unsigned long *) (& fields->f_24u5a2n)); + break; + case MEP_OPERAND_PCREL12A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL12A2, (long *) (& fields->f_12s4a2)); + break; + case MEP_OPERAND_PCREL17A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL17A2, (long *) (& fields->f_17s16a2)); + break; + case MEP_OPERAND_PCREL24A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL24A2, (long *) (& fields->f_24s5a2n)); + break; + case MEP_OPERAND_PCREL8A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL8A2, (long *) (& fields->f_8s8a2)); + break; + case MEP_OPERAND_PSW : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_R1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_RL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl); + break; + case MEP_OPERAND_RL5 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl5); + break; + case MEP_OPERAND_RM : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm); + break; + case MEP_OPERAND_RMA : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm); + break; + case MEP_OPERAND_RN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RN3 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3C : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3L : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3S : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3US : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RNC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNS : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUS : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_SAR : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_SDISP16 : + errmsg = parse_signed16 (cd, strp, MEP_OPERAND_SDISP16, (long *) (& fields->f_16s16)); + break; + case MEP_OPERAND_SIMM16 : + errmsg = parse_signed16 (cd, strp, MEP_OPERAND_SIMM16, (long *) (& fields->f_16s16)); + break; + case MEP_OPERAND_SIMM16P0 : + errmsg = parse_signed16_range (cd, strp, MEP_OPERAND_SIMM16P0, (long *) (& fields->f_ivc2_simm16p0)); + break; + case MEP_OPERAND_SIMM6 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM6, (long *) (& fields->f_6s8)); + break; + case MEP_OPERAND_SIMM8 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8, (long *) (& fields->f_8s8)); + break; + case MEP_OPERAND_SIMM8P0 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P0, (long *) (& fields->f_ivc2_8s0)); + break; + case MEP_OPERAND_SIMM8P20 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P20, (long *) (& fields->f_ivc2_8s20)); + break; + case MEP_OPERAND_SIMM8P4 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P4, (long *) (& fields->f_ivc2_8s4)); + break; + case MEP_OPERAND_SP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_SPR : + errmsg = parse_spreg (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_TP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_TPR : + errmsg = parse_tpreg (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_UDISP2 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_UDISP2, (long *) (& fields->f_2u6)); + break; + case MEP_OPERAND_UDISP7 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7, (unsigned long *) (& fields->f_7u9)); + break; + case MEP_OPERAND_UDISP7A2 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7A2, (unsigned long *) (& fields->f_7u9a2)); + break; + case MEP_OPERAND_UDISP7A4 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7A4, (unsigned long *) (& fields->f_7u9a4)); + break; + case MEP_OPERAND_UIMM16 : + errmsg = parse_unsigned16 (cd, strp, MEP_OPERAND_UIMM16, (unsigned long *) (& fields->f_16u16)); + break; + case MEP_OPERAND_UIMM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM2, (unsigned long *) (& fields->f_2u10)); + break; + case MEP_OPERAND_UIMM24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM24, (unsigned long *) (& fields->f_24u8n)); + break; + case MEP_OPERAND_UIMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM3, (unsigned long *) (& fields->f_3u5)); + break; + case MEP_OPERAND_UIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM4, (unsigned long *) (& fields->f_4u8)); + break; + case MEP_OPERAND_UIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM5, (unsigned long *) (& fields->f_5u8)); + break; + case MEP_OPERAND_UIMM7A4 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_UIMM7A4, (unsigned long *) (& fields->f_7u9a4)); + break; + case MEP_OPERAND_ZERO : + errmsg = parse_zero (cd, strp, MEP_OPERAND_ZERO, (long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const mep_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +mep_cgen_init_asm (CGEN_CPU_DESC cd) +{ + mep_cgen_init_opcode_table (cd); + mep_cgen_init_ibld_table (cd); + cd->parse_handlers = & mep_cgen_parse_handlers[0]; + cd->parse_operand = mep_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by mep_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +mep_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +mep_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! mep_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/mep-desc.c b/external/gpl3/gdb/dist/opcodes/mep-desc.c new file mode 100644 index 000000000000..c72f038911f6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-desc.c @@ -0,0 +1,6388 @@ +/* CPU data for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "mep", MACH_MEP }, + { "h1", MACH_H1 }, + { "c5", MACH_C5 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "mep", ISA_MEP }, + { "ext_core1", ISA_EXT_CORE1 }, + { "ext_cop1_16", ISA_EXT_COP1_16 }, + { "ext_cop1_32", ISA_EXT_COP1_32 }, + { "ext_cop1_48", ISA_EXT_COP1_48 }, + { "ext_cop1_64", ISA_EXT_COP1_64 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED = +{ + { "LABEL", CDATA_LABEL }, + { "REGNUM", CDATA_REGNUM }, + { "FMAX_FLOAT", CDATA_FMAX_FLOAT }, + { "FMAX_INT", CDATA_FMAX_INT }, + { "POINTER", CDATA_POINTER }, + { "LONG", CDATA_LONG }, + { "ULONG", CDATA_ULONG }, + { "SHORT", CDATA_SHORT }, + { "USHORT", CDATA_USHORT }, + { "CHAR", CDATA_CHAR }, + { "UCHAR", CDATA_UCHAR }, + { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CPTYPE_attr[] ATTRIBUTE_UNUSED = +{ + { "CP_DATA_BUS_INT", CPTYPE_CP_DATA_BUS_INT }, + { "VECT", CPTYPE_VECT }, + { "V2SI", CPTYPE_V2SI }, + { "V4HI", CPTYPE_V4HI }, + { "V8QI", CPTYPE_V8QI }, + { "V2USI", CPTYPE_V2USI }, + { "V4UHI", CPTYPE_V4UHI }, + { "V8UQI", CPTYPE_V8UQI }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED = +{ + { "VOID", CRET_VOID }, + { "FIRST", CRET_FIRST }, + { "FIRSTCOPY", CRET_FIRSTCOPY }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED = +{ + {"integer", 1}, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED = +{ + {"integer", 0}, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", CONFIG_NONE }, + { "default", CONFIG_DEFAULT }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED = +{ + { "CORE", SLOTS_CORE }, + { "C3", SLOTS_C3 }, + { "P0S", SLOTS_P0S }, + { "P0", SLOTS_P0 }, + { "P1", SLOTS_P1 }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { "IS_FLOAT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "CDATA", & CDATA_attr[0], & CDATA_attr[0] }, + { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "CPTYPE", & CPTYPE_attr[0], & CPTYPE_attr[0] }, + { "CRET", & CRET_attr[0], & CRET_attr[0] }, + { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] }, + { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] }, + { "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] }, + { "MAY_TRAP", &bool_attr[0], &bool_attr[0] }, + { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] }, + { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] }, + { "VOLATILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA mep_cgen_isa_table[] = { + { "mep", 32, 32, 16, 32 }, + { "ext_core1", 32, 32, 16, 32 }, + { "ext_cop1_16", 32, 32, 32, 32 }, + { "ext_cop1_32", 32, 32, 32, 32 }, + { "ext_cop1_48", 32, 32, 32, 32 }, + { "ext_cop1_64", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH mep_cgen_mach_table[] = { + { "mep", "mep", MACH_MEP, 16 }, + { "h1", "h1", MACH_H1, 16 }, + { "c5", "c5", MACH_C5, 16 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] = +{ + { "$0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_gpr = +{ + & mep_cgen_opval_h_gpr_entries[0], + 20, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] = +{ + { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$id", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$vid", 22, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_csr = +{ + & mep_cgen_opval_h_csr_entries[0], + 25, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] = +{ + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr64 = +{ + & mep_cgen_opval_h_cr64_entries[0], + 32, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] = +{ + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr = +{ + & mep_cgen_opval_h_cr_entries[0], + 32, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] = +{ + { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_ccr = +{ + & mep_cgen_opval_h_ccr_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_ivc2_entries[] = +{ + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 = +{ + & mep_cgen_opval_h_cr_ivc2_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] = +{ + { "$csar0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$cc", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$cofr0", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$cofr1", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 = +{ + & mep_cgen_opval_h_ccr_ivc2_entries[0], + 55, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY mep_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & mep_cgen_ifld_table[0]; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & mep_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & mep_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of mep_cgen_cpu_open to rebuild the tables. */ + +static void +mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & mep_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & mep_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (mep_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = mep_cgen_rebuild_tables; + mep_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +mep_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/mep-desc.h b/external/gpl3/gdb/dist/opcodes/mep-desc.h new file mode 100644 index 000000000000..e95b3e192e62 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-desc.h @@ -0,0 +1,377 @@ +/* CPU data header for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MEP_CPU_H +#define MEP_CPU_H + +#define CGEN_ARCH mep + +/* Given symbol S, return mep_cgen_. */ +#define CGEN_SYM(s) mep##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_MEPF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 + +/* Enums. */ + +/* Enum declaration for major opcodes. */ +typedef enum major { + MAJ_0, MAJ_1, MAJ_2, MAJ_3 + , MAJ_4, MAJ_5, MAJ_6, MAJ_7 + , MAJ_8, MAJ_9, MAJ_10, MAJ_11 + , MAJ_12, MAJ_13, MAJ_14, MAJ_15 +} MAJOR; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_MEP, MACH_H1, MACH_C5 + , MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32 + , ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for datatype to use for C intrinsics mapping. */ +typedef enum cdata_attr { + CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT + , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT + , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT +} CDATA_ATTR; + +/* Enum declaration for datatype to use for coprocessor values. */ +typedef enum cptype_attr { + CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI + , CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI +} CPTYPE_ATTR; + +/* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */ +typedef enum cret_attr { + CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY +} CRET_ATTR; + +/* Enum declaration for . */ +typedef enum config_attr { + CONFIG_NONE, CONFIG_DEFAULT +} CONFIG_ATTR; + +/* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */ +typedef enum slots_attr { + SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0 + , SLOTS_P1 +} SLOTS_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS ((int) ISA_MAX) +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for mep ifield types. */ +typedef enum ifield_type { + MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN + , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 + , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_EXT4 + , MEP_F_EXT62, MEP_F_CRN, MEP_F_CSRN_HI, MEP_F_CSRN_LO + , MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO, MEP_F_CRNX + , MEP_F_0, MEP_F_1, MEP_F_2, MEP_F_3 + , MEP_F_4, MEP_F_5, MEP_F_6, MEP_F_7 + , MEP_F_8, MEP_F_9, MEP_F_10, MEP_F_11 + , MEP_F_12, MEP_F_13, MEP_F_14, MEP_F_15 + , MEP_F_16, MEP_F_17, MEP_F_18, MEP_F_19 + , MEP_F_20, MEP_F_21, MEP_F_22, MEP_F_23 + , MEP_F_24, MEP_F_25, MEP_F_26, MEP_F_27 + , MEP_F_28, MEP_F_29, MEP_F_30, MEP_F_31 + , MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2, MEP_F_24S5A2N_HI + , MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO + , MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9, MEP_F_7U9A2 + , MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10, MEP_F_3U5 + , MEP_F_4U8, MEP_F_5U8, MEP_F_5U24, MEP_F_6S8 + , MEP_F_8S8, MEP_F_16U16, MEP_F_12U16, MEP_F_3U29 + , MEP_F_CDISP10, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N + , MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI + , MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI + , MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5 + , MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20 + , MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20 + , MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4 + , MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6 + , MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9 + , MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31 + , MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28 + , MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0 + , MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3 + , MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10 + , MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18 + , MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23 + , MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CCRN_C3HI + , MEP_F_IVC2_CCRN_C3LO, MEP_F_IVC2_CRN, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1 + , MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2 + , MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN_C3, MEP_F_IVC2_CCRN, MEP_F_IVC2_CRNX + , MEP_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) MEP_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH + , CGEN_HW_ISA, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) +#define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_IS_FLOAT)) != 0) + +/* Enum declaration for mep hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR + , HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR + , HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) + +/* Enum declaration for mep operand types. */ +typedef enum cgen_operand_type { + MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM + , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC + , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL + , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S + , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP + , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 + , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW + , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG + , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP + , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN + , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 + , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 + , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 + , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 + , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 + , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 + , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 + , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 + , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4 + , MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12 + , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_IVC2_CSAR0 + , MEP_OPERAND_IVC2_CC, MEP_OPERAND_IVC2_COFR0, MEP_OPERAND_IVC2_COFR1, MEP_OPERAND_IVC2_COFA0 + , MEP_OPERAND_IVC2_COFA1, MEP_OPERAND_IVC2_CSAR1, MEP_OPERAND_IVC2_ACC0_0, MEP_OPERAND_IVC2_ACC0_1 + , MEP_OPERAND_IVC2_ACC0_2, MEP_OPERAND_IVC2_ACC0_3, MEP_OPERAND_IVC2_ACC0_4, MEP_OPERAND_IVC2_ACC0_5 + , MEP_OPERAND_IVC2_ACC0_6, MEP_OPERAND_IVC2_ACC0_7, MEP_OPERAND_IVC2_ACC1_0, MEP_OPERAND_IVC2_ACC1_1 + , MEP_OPERAND_IVC2_ACC1_2, MEP_OPERAND_IVC2_ACC1_3, MEP_OPERAND_IVC2_ACC1_4, MEP_OPERAND_IVC2_ACC1_5 + , MEP_OPERAND_IVC2_ACC1_6, MEP_OPERAND_IVC2_ACC1_7, MEP_OPERAND_CROC, MEP_OPERAND_CRQC + , MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2, MEP_OPERAND_IVC_X_6_3 + , MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8, MEP_OPERAND_IMM5P7 + , MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4, MEP_OPERAND_IMM3P5 + , MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10, MEP_OPERAND_IMM5P8 + , MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23, MEP_OPERAND_IMM3P25 + , MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20, MEP_OPERAND_IMM8P20 + , MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2 + , MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0 + , MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN + , MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 145 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN + , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN + , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN + , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN + , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP + , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA + , CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG + , CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_CPTYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CPTYPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_CRET_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CRET-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) +#define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_MAY_TRAP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_ALONE)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VOLATILE)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld mep_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD mep_cgen_opval_h_gpr; +extern CGEN_KEYWORD mep_cgen_opval_h_csr; +extern CGEN_KEYWORD mep_cgen_opval_h_cr64; +extern CGEN_KEYWORD mep_cgen_opval_h_cr; +extern CGEN_KEYWORD mep_cgen_opval_h_ccr; +extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2; +extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2; + +extern const CGEN_HW_ENTRY mep_cgen_hw_table[]; + + + +#endif /* MEP_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/mep-dis.c b/external/gpl3/gdb/dist/opcodes/mep-dis.c new file mode 100644 index 000000000000..24fab18738fa --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-dis.c @@ -0,0 +1,1608 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +#include "elf/mep.h" +#include "elf-bfd.h" + +#define CGEN_VALIDATE_INSN_SUPPORTED + +static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); +static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); + +static void +print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, + CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, + unsigned int flags ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$tp"); +} + +static void +print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, + CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, + unsigned int flags ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$sp"); +} + +/* begin-cop-ip-print-handlers */ +static void +print_ivc2_cr (CGEN_CPU_DESC, + void *, + CGEN_KEYWORD *, + long, + unsigned int) ATTRIBUTE_UNUSED; +static void +print_ivc2_cr (CGEN_CPU_DESC cd, + void *dis_info, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long value, + unsigned int attrs) +{ + print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); +} +static void +print_ivc2_ccr (CGEN_CPU_DESC, + void *, + CGEN_KEYWORD *, + long, + unsigned int) ATTRIBUTE_UNUSED; +static void +print_ivc2_ccr (CGEN_CPU_DESC cd, + void *dis_info, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long value, + unsigned int attrs) +{ + print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); +} +/* end-cop-ip-print-handlers */ + +/************************************************************\ +*********************** Experimental ************************* +\************************************************************/ + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN mep_print_insn + +static int +mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, + bfd_byte *buf, int corelength, int copro1length, + int copro2length ATTRIBUTE_UNUSED) +{ + int i; + int status = 0; + /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ + bfd_byte insnbuf[64]; + + /* If corelength > 0 then there is a core insn present. It + will be at the beginning of the buffer. After printing + the core insn, we need to print the + on the next line. */ + if (corelength > 0) + { + int my_status = 0; + + for (i = 0; i < corelength; i++ ) + insnbuf[i] = buf[i]; + cd->isas = & MEP_CORE_ISA; + + my_status = print_insn (cd, pc, info, insnbuf, corelength); + if (my_status != corelength) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = corelength; + } + status += my_status; + + /* Print the + to indicate that the following copro insn is */ + /* part of a vliw group. */ + if (copro1length > 0) + (*info->fprintf_func) (info->stream, " + "); + } + + /* Now all that is left to be processed is the coprocessor insns + In vliw mode, there will always be one. Its positioning will + be from byte corelength to byte corelength+copro1length -1. + No need to check for existence. Also, the first vliw insn, + will, as spec'd, always be at least as long as the core insn + so we don't need to flush the buffer. */ + if (copro1length > 0) + { + int my_status = 0; + + for (i = corelength; i < corelength + copro1length; i++ ) + insnbuf[i - corelength] = buf[i]; + + switch (copro1length) + { + case 0: + break; + case 2: + cd->isas = & MEP_COP16_ISA; + break; + case 4: + cd->isas = & MEP_COP32_ISA; + break; + case 6: + cd->isas = & MEP_COP48_ISA; + break; + case 8: + cd->isas = & MEP_COP64_ISA; + break; + default: + /* Shouldn't be anything but 16,32,48,64. */ + break; + } + + my_status = print_insn (cd, pc, info, insnbuf, copro1length); + + if (my_status != copro1length) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = copro1length; + } + status += my_status; + } + +#if 0 + /* Now we need to process the second copro insn if it exists. We + have no guarantee that the second copro insn will be longer + than the first, so we have to flush the buffer if we are have + a second copro insn to process. If present, this insn will + be in the position from byte corelength+copro1length to byte + corelength+copro1length+copro2length-1 (which better equal 8 + or else we're in big trouble. */ + if (copro2length > 0) + { + int my_status = 0; + + for (i = 0; i < 64 ; i++) + insnbuf[i] = 0; + + for (i = corelength + copro1length; i < 64; i++) + insnbuf[i - (corelength + copro1length)] = buf[i]; + + switch (copro2length) + { + case 2: + cd->isas = 1 << ISA_EXT_COP1_16; + break; + case 4: + cd->isas = 1 << ISA_EXT_COP1_32; + break; + case 6: + cd->isas = 1 << ISA_EXT_COP1_48; + break; + case 8: + cd->isas = 1 << ISA_EXT_COP1_64; + break; + default: + /* Shouldn't be anything but 16,32,48,64. */ + break; + } + + my_status = print_insn (cd, pc, info, insnbuf, copro2length); + + if (my_status != copro2length) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = copro2length; + } + + status += my_status; + } +#endif + + /* Status should now be the number of bytes that were printed + which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ + + if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) + return -1; + else + return status; +} + +/* The two functions mep_examine_vliw[32,64]_insns are used find out + which vliw combinaion (16 bit core with 48 bit copro, 32 bit core + with 32 bit copro, etc.) is present. Later on, when internally + parallel coprocessors are handled, only these functions should + need to be changed. + + At this time only the following combinations are supported: + + VLIW32 Mode: + 16 bit core insn (core) and 16 bit coprocessor insn (cop1) + 32 bit core insn (core) + 32 bit coprocessor insn (cop1) + Note: As of this time, I do not believe we have enough information + to distinguish a 32 bit core insn from a 32 bit cop insn. Also, + no 16 bit coprocessor insns have been specified. + + VLIW64 Mode: + 16 bit core insn (core) and 48 bit coprocessor insn (cop1) + 32 bit core insn (core) and 32 bit coprocessor insn (cop1) + 64 bit coprocessor insn (cop1) + + The framework for an internally parallel coprocessor is also + present (2nd coprocessor insn is cop2), but at this time it + is not used. This only appears to be valid in VLIW64 mode. */ + +static int +mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + int buflength; + int corebuflength; + int cop1buflength; + int cop2buflength; + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + char indicator16[1]; + char indicatorcop32[2]; + + /* At this time we're not supporting internally parallel coprocessors, + so cop2buflength will always be 0. */ + cop2buflength = 0; + + /* Read in 32 bits. */ + buflength = 4; /* VLIW insn spans 4 bytes. */ + status = (*info->read_memory_func) (pc, buf, buflength, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* Put the big endian representation of the bytes to be examined + in the temporary buffers for examination. */ + + if (info->endian == BFD_ENDIAN_BIG) + { + indicator16[0] = buf[0]; + indicatorcop32[0] = buf[0]; + indicatorcop32[1] = buf[1]; + } + else + { + indicator16[0] = buf[1]; + indicatorcop32[0] = buf[1]; + indicatorcop32[1] = buf[0]; + } + + /* If the two high order bits are 00, 01 or 10, we have a 16 bit + core insn and a 48 bit copro insn. */ + + if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) + { + if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) + { + /* We have a 32 bit copro insn. */ + corebuflength = 0; + /* All 4 4ytes are one copro insn. */ + cop1buflength = 4; + } + else + { + /* We have a 32 bit core. */ + corebuflength = 4; + cop1buflength = 0; + } + } + else + { + /* We have a 16 bit core insn and a 16 bit copro insn. */ + corebuflength = 2; + cop1buflength = 2; + } + + /* Now we have the distrubution set. Print them out. */ + status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, + cop1buflength, cop2buflength); + + return status; +} + +static int +mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + int buflength; + int corebuflength; + int cop1buflength; + int cop2buflength; + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + char indicator16[1]; + char indicator64[4]; + + /* At this time we're not supporting internally parallel + coprocessors, so cop2buflength will always be 0. */ + cop2buflength = 0; + + /* Read in 64 bits. */ + buflength = 8; /* VLIW insn spans 8 bytes. */ + status = (*info->read_memory_func) (pc, buf, buflength, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* We have all 64 bits in the buffer now. We have to figure out + what combination of instruction sizes are present. The two + high order bits will indicate whether or not we have a 16 bit + core insn or not. If not, then we have to look at the 7,8th + bytes to tell whether we have 64 bit copro insn or a 32 bit + core insn with a 32 bit copro insn. Endianness will make a + difference here. */ + + /* Put the big endian representation of the bytes to be examined + in the temporary buffers for examination. */ + + /* indicator16[0] = buf[0]; */ + if (info->endian == BFD_ENDIAN_BIG) + { + indicator16[0] = buf[0]; + indicator64[0] = buf[0]; + indicator64[1] = buf[1]; + indicator64[2] = buf[2]; + indicator64[3] = buf[3]; + } + else + { + indicator16[0] = buf[1]; + indicator64[0] = buf[1]; + indicator64[1] = buf[0]; + indicator64[2] = buf[3]; + indicator64[3] = buf[2]; + } + + /* If the two high order bits are 00, 01 or 10, we have a 16 bit + core insn and a 48 bit copro insn. */ + + if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) + { + if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 + && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) + { + /* We have a 64 bit copro insn. */ + corebuflength = 0; + /* All 8 bytes are one copro insn. */ + cop1buflength = 8; + } + else + { + /* We have a 32 bit core insn and a 32 bit copro insn. */ + corebuflength = 4; + cop1buflength = 4; + } + } + else + { + /* We have a 16 bit core insn and a 48 bit copro insn. */ + corebuflength = 2; + cop1buflength = 6; + } + + /* Now we have the distrubution set. Print them out. */ + status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, + cop1buflength, cop2buflength); + + return status; +} + +#ifdef MEP_IVC2_SUPPORTED + +static int +print_slot_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + SLOTS_ATTR slot, + bfd_byte *buf) +{ + const CGEN_INSN_LIST *insn_list; + CGEN_INSN_INT insn_value; + CGEN_EXTRACT_INFO ex_info; + + insn_value = cgen_get_insn_value (cd, buf, 32); + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << 8) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + + if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) + && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) + || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } + + if ((insn_value & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + if (slot == SLOTS_P0S) + (*info->fprintf_func) (info->stream, "*unknown-p0s*"); + else if (slot == SLOTS_P0) + (*info->fprintf_func) (info->stream, "*unknown-p0*"); + else if (slot == SLOTS_P1) + (*info->fprintf_func) (info->stream, "*unknown-p1*"); + else if (slot == SLOTS_C3) + (*info->fprintf_func) (info->stream, "*unknown-c3*"); + return 0; +} + +static int +mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) +{ + int status; + int buflength; + bfd_byte buf[8]; + bfd_byte insn[8]; + int e; + + /* Read in 64 bits. */ + buflength = 8; /* VLIW insn spans 8 bytes. */ + status = (*info->read_memory_func) (pc, buf, buflength, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + e = 1; + else + e = 0; + + if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) + { + /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ + /* V1 [-----core-----][--------p0s-------][------------p1------------] */ + + print_insn (cd, pc, info, buf, 2); + + insn[0^e] = 0; + insn[1^e] = buf[2^e]; + insn[2^e] = buf[3^e]; + insn[3^e] = buf[4^e] & 0xf0; + (*info->fprintf_func) (info->stream, " + "); + print_slot_insn (cd, pc, info, SLOTS_P0S, insn); + + insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; + insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; + insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; + insn[3^e] = buf[7^e] << 4; + (*info->fprintf_func) (info->stream, " + "); + print_slot_insn (cd, pc, info, SLOTS_P1, insn); + } + else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) + { + /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ + /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ + /* 00000000111111112222222233333333 */ + + insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; + insn[1^e] = buf[2^e]; + insn[2^e] = buf[3^e]; + insn[3^e] = buf[4^e] & 0xf0; + print_slot_insn (cd, pc, info, SLOTS_P0, insn); + + insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; + insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; + insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; + insn[3^e] = buf[7^e] << 4; + (*info->fprintf_func) (info->stream, " + "); + print_slot_insn (cd, pc, info, SLOTS_P1, insn); + } + else + { + /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ + /* V2 [-------------core-------------]xxxx[------------p1------------] */ + print_insn (cd, pc, info, buf, 4); + + insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; + insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; + insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; + insn[3^e] = buf[7^e] << 4; + (*info->fprintf_func) (info->stream, " + "); + print_slot_insn (cd, pc, info, SLOTS_P1, insn); + } + + return 8; +} + +#endif /* MEP_IVC2_SUPPORTED */ + +/* This is a hack. SID calls this to update the disassembler as the + CPU changes modes. */ +static int mep_ivc2_disassemble_p = 0; +static int mep_ivc2_vliw_disassemble_p = 0; + +void +mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); +void +mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) +{ + mep_ivc2_disassemble_p = ivc2_p; + mep_ivc2_vliw_disassemble_p = vliw_p; + mep_config_index = cfg_idx; +} + +static int +mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + int cop_type; + int ivc2 = 0; + static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; + + if (ivc2_core_isa == NULL) + { + /* IVC2 has some core-only coprocessor instructions. We + use COP32 to flag those, and COP64 for the VLIW ones, + since they have the same names. */ + ivc2_core_isa = cgen_bitset_create (MAX_ISAS); + } + + /* Extract and adapt to configuration number, if available. */ + if (info->section && info->section->owner) + { + bfd *abfd = info->section->owner; + mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; + /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ + + cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; + if (cop_type == EF_MEP_COP_IVC2) + ivc2 = 1; + } + + /* Picking the right ISA bitmask for the current context is tricky. */ + if (info->section) + { + if (info->section->flags & SEC_MEP_VLIW) + { +#ifdef MEP_IVC2_SUPPORTED + if (ivc2) + { + /* ivc2 has its own way of selecting its functions. */ + cd->isas = & MEP_CORE_ISA; + status = mep_examine_ivc2_insns (cd, pc, info); + } + else +#endif + /* Are we in 32 or 64 bit vliw mode? */ + if (MEP_VLIW64) + status = mep_examine_vliw64_insns (cd, pc, info); + else + status = mep_examine_vliw32_insns (cd, pc, info); + /* Both the above branches set their own isa bitmasks. */ + } + else + { + if (ivc2) + { + cgen_bitset_clear (ivc2_core_isa); + cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); + cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); + cd->isas = ivc2_core_isa; + } + else + cd->isas = & MEP_CORE_ISA; + status = default_print_insn (cd, pc, info); + } + } + else /* sid or gdb */ + { +#ifdef MEP_IVC2_SUPPORTED + if (mep_ivc2_disassemble_p) + { + if (mep_ivc2_vliw_disassemble_p) + { + cd->isas = & MEP_CORE_ISA; + status = mep_examine_ivc2_insns (cd, pc, info); + return status; + } + else + { + if (ivc2) + cd->isas = ivc2_core_isa; + } + } +#endif + + status = default_print_insn (cd, pc, info); + } + + return status; +} + + +/* -- opc.c */ + +void mep_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +mep_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + print_normal (cd, info, fields->f_24u8a4n, 0|(1<f_c5_rmuimm20, 0|(1<f_c5_rnmuimm24, 0|(1<f_callnum, 0|(1<f_rm, 0, pc, length); + break; + case MEP_OPERAND_CCRN : + print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<f_cdisp10, 0|(1<f_cdisp10, 0|(1<f_cdisp10, 0|(1<f_cdisp10, 0|(1<f_12s20, 0|(1<f_rn, 0, pc, length); + break; + case MEP_OPERAND_CIMM5 : + print_normal (cd, info, fields->f_5u24, 0, pc, length); + break; + case MEP_OPERAND_CODE16 : + print_normal (cd, info, fields->f_16u16, 0, pc, length); + break; + case MEP_OPERAND_CODE24 : + print_normal (cd, info, fields->f_24u4n, 0|(1<f_crn, 0); + break; + case MEP_OPERAND_CRN64 : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0); + break; + case MEP_OPERAND_CRNX : + print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<f_crnx, 0|(1<f_ivc2_5u7, 0); + break; + case MEP_OPERAND_CROP : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0); + break; + case MEP_OPERAND_CRPC : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0); + break; + case MEP_OPERAND_CRPP : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0); + break; + case MEP_OPERAND_CRQC : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0); + break; + case MEP_OPERAND_CRQP : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0); + break; + case MEP_OPERAND_CSRN : + print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<f_csrn, 0|(1<f_ivc2_imm16p0, 0|(1<f_ivc2_3u12, 0, pc, length); + break; + case MEP_OPERAND_IMM3P25 : + print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length); + break; + case MEP_OPERAND_IMM3P4 : + print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length); + break; + case MEP_OPERAND_IMM3P5 : + print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length); + break; + case MEP_OPERAND_IMM3P9 : + print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length); + break; + case MEP_OPERAND_IMM4P10 : + print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length); + break; + case MEP_OPERAND_IMM4P4 : + print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length); + break; + case MEP_OPERAND_IMM4P8 : + print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length); + break; + case MEP_OPERAND_IMM5P23 : + print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length); + break; + case MEP_OPERAND_IMM5P3 : + print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length); + break; + case MEP_OPERAND_IMM5P7 : + print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length); + break; + case MEP_OPERAND_IMM5P8 : + print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length); + break; + case MEP_OPERAND_IMM6P2 : + print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length); + break; + case MEP_OPERAND_IMM6P6 : + print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length); + break; + case MEP_OPERAND_IMM8P0 : + print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length); + break; + case MEP_OPERAND_IMM8P20 : + print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length); + break; + case MEP_OPERAND_IMM8P4 : + print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_0_2 : + print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_0_3 : + print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_0_4 : + print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_0_5 : + print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_6_1 : + print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_6_2 : + print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length); + break; + case MEP_OPERAND_IVC_X_6_3 : + print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length); + break; + case MEP_OPERAND_IVC2_ACC0_0 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_1 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_2 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_3 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_4 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_5 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_6 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC0_7 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_0 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_1 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_2 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_3 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_4 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_5 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_6 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_ACC1_7 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_CC : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_COFA0 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_COFA1 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_COFR0 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_COFR1 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_CSAR0 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2_CSAR1 : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); + break; + case MEP_OPERAND_IVC2C3CCRN : + print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<f_ivc2_ccrn, 0|(1<f_ivc2_crnx, 0|(1<f_ivc2_crm, 0); + break; + case MEP_OPERAND_LO : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_LP : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_MB0 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_MB1 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_ME0 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_ME1 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_NPC : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_OPT : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_PCABS24A2 : + print_address (cd, info, fields->f_24u5a2n, 0|(1<f_12s4a2, 0|(1<f_17s16a2, 0|(1<f_24s5a2n, 0|(1<f_8s8a2, 0|(1<f_rl, 0); + break; + case MEP_OPERAND_RL5 : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0); + break; + case MEP_OPERAND_RM : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); + break; + case MEP_OPERAND_RMA : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); + break; + case MEP_OPERAND_RN : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RN3 : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3C : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3L : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3S : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3UC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3UL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3US : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RNC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNS : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUS : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_SAR : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_SDISP16 : + print_normal (cd, info, fields->f_16s16, 0|(1<f_16s16, 0|(1<f_ivc2_simm16p0, 0|(1<f_6s8, 0|(1<f_8s8, 0|(1<f_ivc2_8s0, 0|(1<f_ivc2_8s20, 0|(1<f_ivc2_8s4, 0|(1<f_2u6, 0|(1<f_7u9, 0, pc, length); + break; + case MEP_OPERAND_UDISP7A2 : + print_normal (cd, info, fields->f_7u9a2, 0, pc, length); + break; + case MEP_OPERAND_UDISP7A4 : + print_normal (cd, info, fields->f_7u9a4, 0, pc, length); + break; + case MEP_OPERAND_UIMM16 : + print_normal (cd, info, fields->f_16u16, 0, pc, length); + break; + case MEP_OPERAND_UIMM2 : + print_normal (cd, info, fields->f_2u10, 0, pc, length); + break; + case MEP_OPERAND_UIMM24 : + print_normal (cd, info, fields->f_24u8n, 0|(1<f_3u5, 0, pc, length); + break; + case MEP_OPERAND_UIMM4 : + print_normal (cd, info, fields->f_4u8, 0, pc, length); + break; + case MEP_OPERAND_UIMM5 : + print_normal (cd, info, fields->f_5u8, 0, pc, length); + break; + case MEP_OPERAND_UIMM7A4 : + print_normal (cd, info, fields->f_7u9a4, 0, pc, length); + break; + case MEP_OPERAND_ZERO : + print_normal (cd, info, 0, 0|(1<print_handlers = & mep_cgen_print_handlers[0]; + cd->print_operand = mep_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! mep_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_mep (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_mep +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + mep_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/mep-ibld.c b/external/gpl3/gdb/dist/opcodes/mep-ibld.c new file mode 100644 index 000000000000..907cff4c2d66 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-ibld.c @@ -0,0 +1,3563 @@ +/* Instruction building/extraction support for mep. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * mep_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +mep_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + { +{ + FLD (f_24u8a4n_hi) = ((UINT) (FLD (f_24u8a4n)) >> (8)); + FLD (f_24u8a4n_lo) = ((UINT) (((FLD (f_24u8a4n)) & (252))) >> (2)); +} + errmsg = insert_normal (cd, fields->f_24u8a4n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u8a4n_lo, 0, 0, 8, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_C5RMUIMM20 : + { +{ + FLD (f_c5_rm) = ((UINT) (FLD (f_c5_rmuimm20)) >> (16)); + FLD (f_c5_16u16) = ((FLD (f_c5_rmuimm20)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_c5_rm, 0, 0, 8, 4, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_C5RNMUIMM24 : + { +{ + FLD (f_c5_rnm) = ((UINT) (FLD (f_c5_rnmuimm24)) >> (16)); + FLD (f_c5_16u16) = ((FLD (f_c5_rnmuimm24)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_c5_rnm, 0, 0, 4, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_c5_16u16, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CALLNUM : + { +{ + FLD (f_5) = ((((UINT) (FLD (f_callnum)) >> (3))) & (1)); + FLD (f_6) = ((((UINT) (FLD (f_callnum)) >> (2))) & (1)); + FLD (f_7) = ((((UINT) (FLD (f_callnum)) >> (1))) & (1)); + FLD (f_11) = ((FLD (f_callnum)) & (1)); +} + errmsg = insert_normal (cd, fields->f_5, 0, 0, 5, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_6, 0, 0, 6, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_11, 0, 0, 11, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CCCC : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CCRN : + { +{ + FLD (f_ccrn_hi) = ((((UINT) (FLD (f_ccrn)) >> (4))) & (3)); + FLD (f_ccrn_lo) = ((FLD (f_ccrn)) & (15)); +} + errmsg = insert_normal (cd, fields->f_ccrn_hi, 0, 0, 28, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ccrn_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CDISP10 : + { + long value = fields->f_cdisp10; + value = (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (512))) ? (((((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))) - (1024))) : (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))); + errmsg = insert_normal (cd, value, 0|(1<f_cdisp10; + value = (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (512))) ? (((((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))) - (1024))) : (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))); + errmsg = insert_normal (cd, value, 0|(1<f_cdisp10; + value = (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (512))) ? (((((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))) - (1024))) : (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))); + errmsg = insert_normal (cd, value, 0|(1<f_cdisp10; + value = (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (512))) ? (((((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))) - (1024))) : (((((((((value) & (128))) ? (((value) ^ (768))) : (value)) & (512))) ? ((((((value) & (128))) ? (((value) ^ (768))) : (value)) - (1024))) : ((((value) & (128))) ? (((value) ^ (768))) : (value))) & (1023))); + errmsg = insert_normal (cd, value, 0|(1<f_12s20, 0|(1<f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CIMM5 : + errmsg = insert_normal (cd, fields->f_5u24, 0, 0, 24, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CODE16 : + errmsg = insert_normal (cd, fields->f_16u16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_CODE24 : + { +{ + FLD (f_24u4n_hi) = ((UINT) (FLD (f_24u4n)) >> (16)); + FLD (f_24u4n_lo) = ((FLD (f_24u4n)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_24u4n_hi, 0, 0, 4, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u4n_lo, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + errmsg = insert_normal (cd, fields->f_crn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CRN64 : + errmsg = insert_normal (cd, fields->f_crn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CRNX : + { +{ + FLD (f_crnx_lo) = ((FLD (f_crnx)) & (15)); + FLD (f_crnx_hi) = ((UINT) (FLD (f_crnx)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_crnx_hi, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_crnx_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CRNX64 : + { +{ + FLD (f_crnx_lo) = ((FLD (f_crnx)) & (15)); + FLD (f_crnx_hi) = ((UINT) (FLD (f_crnx)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_crnx_hi, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_crnx_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CROC : + errmsg = insert_normal (cd, fields->f_ivc2_5u7, 0, 0, 7, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CROP : + errmsg = insert_normal (cd, fields->f_ivc2_5u23, 0, 0, 23, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CRPC : + errmsg = insert_normal (cd, fields->f_ivc2_5u26, 0, 0, 26, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CRPP : + errmsg = insert_normal (cd, fields->f_ivc2_5u18, 0, 0, 18, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CRQC : + errmsg = insert_normal (cd, fields->f_ivc2_5u21, 0, 0, 21, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CRQP : + errmsg = insert_normal (cd, fields->f_ivc2_5u13, 0, 0, 13, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CSRN : + { +{ + FLD (f_csrn_lo) = ((FLD (f_csrn)) & (15)); + FLD (f_csrn_hi) = ((UINT) (FLD (f_csrn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_csrn_hi, 0, 0, 15, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_csrn_lo, 0, 0, 8, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CSRN_IDX : + { +{ + FLD (f_csrn_lo) = ((FLD (f_csrn)) & (15)); + FLD (f_csrn_hi) = ((UINT) (FLD (f_csrn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_csrn_hi, 0, 0, 15, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_csrn_lo, 0, 0, 8, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_IMM16P0 : + { +{ + FLD (f_ivc2_8u0) = ((((UINT) (FLD (f_ivc2_imm16p0)) >> (8))) & (255)); + FLD (f_ivc2_8u20) = ((FLD (f_ivc2_imm16p0)) & (255)); +} + errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_IMM3P12 : + errmsg = insert_normal (cd, fields->f_ivc2_3u12, 0, 0, 12, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM3P25 : + errmsg = insert_normal (cd, fields->f_ivc2_3u25, 0, 0, 25, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM3P4 : + errmsg = insert_normal (cd, fields->f_ivc2_3u4, 0, 0, 4, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM3P5 : + errmsg = insert_normal (cd, fields->f_ivc2_3u5, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM3P9 : + errmsg = insert_normal (cd, fields->f_ivc2_3u9, 0, 0, 9, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM4P10 : + errmsg = insert_normal (cd, fields->f_ivc2_4u10, 0, 0, 10, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM4P4 : + errmsg = insert_normal (cd, fields->f_ivc2_4u4, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM4P8 : + errmsg = insert_normal (cd, fields->f_ivc2_4u8, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM5P23 : + errmsg = insert_normal (cd, fields->f_ivc2_5u23, 0, 0, 23, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM5P3 : + errmsg = insert_normal (cd, fields->f_ivc2_5u3, 0, 0, 3, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM5P7 : + errmsg = insert_normal (cd, fields->f_ivc2_5u7, 0, 0, 7, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM5P8 : + errmsg = insert_normal (cd, fields->f_ivc2_5u8, 0, 0, 8, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM6P2 : + errmsg = insert_normal (cd, fields->f_ivc2_6u2, 0, 0, 2, 6, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM6P6 : + errmsg = insert_normal (cd, fields->f_ivc2_6u6, 0, 0, 6, 6, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM8P0 : + errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM8P20 : + errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer); + break; + case MEP_OPERAND_IMM8P4 : + errmsg = insert_normal (cd, fields->f_ivc2_8u4, 0, 0, 4, 8, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_0_2 : + errmsg = insert_normal (cd, fields->f_ivc2_2u0, 0, 0, 0, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_0_3 : + errmsg = insert_normal (cd, fields->f_ivc2_3u0, 0, 0, 0, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_0_4 : + errmsg = insert_normal (cd, fields->f_ivc2_4u0, 0, 0, 0, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_0_5 : + errmsg = insert_normal (cd, fields->f_ivc2_5u0, 0, 0, 0, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_6_1 : + errmsg = insert_normal (cd, fields->f_ivc2_1u6, 0, 0, 6, 1, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_6_2 : + errmsg = insert_normal (cd, fields->f_ivc2_2u6, 0, 0, 6, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC_X_6_3 : + errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_IVC2_ACC0_0 : + break; + case MEP_OPERAND_IVC2_ACC0_1 : + break; + case MEP_OPERAND_IVC2_ACC0_2 : + break; + case MEP_OPERAND_IVC2_ACC0_3 : + break; + case MEP_OPERAND_IVC2_ACC0_4 : + break; + case MEP_OPERAND_IVC2_ACC0_5 : + break; + case MEP_OPERAND_IVC2_ACC0_6 : + break; + case MEP_OPERAND_IVC2_ACC0_7 : + break; + case MEP_OPERAND_IVC2_ACC1_0 : + break; + case MEP_OPERAND_IVC2_ACC1_1 : + break; + case MEP_OPERAND_IVC2_ACC1_2 : + break; + case MEP_OPERAND_IVC2_ACC1_3 : + break; + case MEP_OPERAND_IVC2_ACC1_4 : + break; + case MEP_OPERAND_IVC2_ACC1_5 : + break; + case MEP_OPERAND_IVC2_ACC1_6 : + break; + case MEP_OPERAND_IVC2_ACC1_7 : + break; + case MEP_OPERAND_IVC2_CC : + break; + case MEP_OPERAND_IVC2_COFA0 : + break; + case MEP_OPERAND_IVC2_COFA1 : + break; + case MEP_OPERAND_IVC2_COFR0 : + break; + case MEP_OPERAND_IVC2_COFR1 : + break; + case MEP_OPERAND_IVC2_CSAR0 : + break; + case MEP_OPERAND_IVC2_CSAR1 : + break; + case MEP_OPERAND_IVC2C3CCRN : + { +{ + FLD (f_ivc2_ccrn_c3hi) = ((((UINT) (FLD (f_ivc2_ccrn_c3)) >> (4))) & (3)); + FLD (f_ivc2_ccrn_c3lo) = ((FLD (f_ivc2_ccrn_c3)) & (15)); +} + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_c3hi, 0, 0, 28, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_c3lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_IVC2CCRN : + { +{ + FLD (f_ivc2_ccrn_h2) = ((((UINT) (FLD (f_ivc2_ccrn)) >> (4))) & (3)); + FLD (f_ivc2_ccrn_lo) = ((FLD (f_ivc2_ccrn)) & (15)); +} + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_h2, 0, 0, 20, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_lo, 0, 0, 0, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_IVC2CRN : + { +{ + FLD (f_ivc2_ccrn_h1) = ((((UINT) (FLD (f_ivc2_crnx)) >> (4))) & (1)); + FLD (f_ivc2_ccrn_lo) = ((FLD (f_ivc2_crnx)) & (15)); +} + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_h1, 0, 0, 20, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ivc2_ccrn_lo, 0, 0, 0, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_IVC2RM : + errmsg = insert_normal (cd, fields->f_ivc2_crm, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + { +{ + FLD (f_24u5a2n_lo) = ((UINT) (((FLD (f_24u5a2n)) & (255))) >> (1)); + FLD (f_24u5a2n_hi) = ((UINT) (FLD (f_24u5a2n)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_24u5a2n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u5a2n_lo, 0, 0, 5, 7, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_PCREL12A2 : + { + long value = fields->f_12s4a2; + value = ((SI) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_17s16a2; + value = ((SI) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<> (1)); + FLD (f_24s5a2n_hi) = ((INT) (FLD (f_24s5a2n)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_24s5a2n_hi, 0|(1<f_24s5a2n_lo, 0|(1<f_8s8a2; + value = ((SI) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_rl, 0, 0, 12, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RL5 : + errmsg = insert_normal (cd, fields->f_rl5, 0, 0, 20, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RM : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RMA : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RN : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3 : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3C : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3L : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3S : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3UC : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3UL : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3US : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RNC : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNL : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNS : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUC : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUL : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUS : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + errmsg = insert_normal (cd, fields->f_16s16, 0|(1<f_16s16, 0|(1<> (8))) & (255)); + FLD (f_ivc2_8u20) = ((FLD (f_ivc2_simm16p0)) & (255)); +} + errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_SIMM6 : + errmsg = insert_normal (cd, fields->f_6s8, 0|(1<f_8s8, 0|(1<f_ivc2_8s0, 0|(1<f_ivc2_8s20, 0|(1<f_ivc2_8s4, 0|(1<f_2u6, 0, 0, 6, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_UDISP7 : + errmsg = insert_normal (cd, fields->f_7u9, 0, 0, 9, 7, 32, total_length, buffer); + break; + case MEP_OPERAND_UDISP7A2 : + { + long value = fields->f_7u9a2; + value = ((USI) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 9, 6, 32, total_length, buffer); + } + break; + case MEP_OPERAND_UDISP7A4 : + { + long value = fields->f_7u9a4; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 9, 5, 32, total_length, buffer); + } + break; + case MEP_OPERAND_UIMM16 : + errmsg = insert_normal (cd, fields->f_16u16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM2 : + errmsg = insert_normal (cd, fields->f_2u10, 0, 0, 10, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM24 : + { +{ + FLD (f_24u8n_hi) = ((UINT) (FLD (f_24u8n)) >> (8)); + FLD (f_24u8n_lo) = ((FLD (f_24u8n)) & (255)); +} + errmsg = insert_normal (cd, fields->f_24u8n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u8n_lo, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_UIMM3 : + errmsg = insert_normal (cd, fields->f_3u5, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM4 : + errmsg = insert_normal (cd, fields->f_4u8, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM5 : + errmsg = insert_normal (cd, fields->f_5u8, 0, 0, 8, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM7A4 : + { + long value = fields->f_7u9a4; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 9, 5, 32, total_length, buffer); + } + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int mep_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +mep_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u8a4n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_24u8a4n_lo); + if (length <= 0) break; + FLD (f_24u8a4n) = ((((FLD (f_24u8a4n_hi)) << (8))) | (((FLD (f_24u8a4n_lo)) << (2)))); + } + break; + case MEP_OPERAND_C5RMUIMM20 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_c5_rm); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16); + if (length <= 0) break; +{ + FLD (f_c5_rmuimm20) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rm)) << (16)))); +} + } + break; + case MEP_OPERAND_C5RNMUIMM24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_c5_rnm); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_c5_16u16); + if (length <= 0) break; +{ + FLD (f_c5_rnmuimm24) = ((FLD (f_c5_16u16)) | (((FLD (f_c5_rnm)) << (16)))); +} + } + break; + case MEP_OPERAND_CALLNUM : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_11); + if (length <= 0) break; + FLD (f_callnum) = ((((FLD (f_5)) << (3))) | (((((FLD (f_6)) << (2))) | (((((FLD (f_7)) << (1))) | (FLD (f_11))))))); + } + break; + case MEP_OPERAND_CCCC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_CCRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ccrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ccrn_lo); + if (length <= 0) break; + FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo))); + } + break; + case MEP_OPERAND_CDISP10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cdisp10 = value; + } + break; + case MEP_OPERAND_CDISP10A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cdisp10 = value; + } + break; + case MEP_OPERAND_CDISP10A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cdisp10 = value; + } + break; + case MEP_OPERAND_CDISP10A8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cdisp10 = value; + } + break; + case MEP_OPERAND_CDISP12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_12s20); + break; + case MEP_OPERAND_CIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_CIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 5, 32, total_length, pc, & fields->f_5u24); + break; + case MEP_OPERAND_CODE16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_16u16); + break; + case MEP_OPERAND_CODE24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_24u4n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u4n_lo); + if (length <= 0) break; + FLD (f_24u4n) = ((((FLD (f_24u4n_hi)) << (16))) | (FLD (f_24u4n_lo))); + } + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crn); + break; + case MEP_OPERAND_CRN64 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crn); + break; + case MEP_OPERAND_CRNX : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_crnx_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crnx_lo); + if (length <= 0) break; + FLD (f_crnx) = ((((FLD (f_crnx_hi)) << (4))) | (FLD (f_crnx_lo))); + } + break; + case MEP_OPERAND_CRNX64 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_crnx_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crnx_lo); + if (length <= 0) break; + FLD (f_crnx) = ((((FLD (f_crnx_hi)) << (4))) | (FLD (f_crnx_lo))); + } + break; + case MEP_OPERAND_CROC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 5, 32, total_length, pc, & fields->f_ivc2_5u7); + break; + case MEP_OPERAND_CROP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 5, 32, total_length, pc, & fields->f_ivc2_5u23); + break; + case MEP_OPERAND_CRPC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 5, 32, total_length, pc, & fields->f_ivc2_5u26); + break; + case MEP_OPERAND_CRPP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 5, 32, total_length, pc, & fields->f_ivc2_5u18); + break; + case MEP_OPERAND_CRQC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 5, 32, total_length, pc, & fields->f_ivc2_5u21); + break; + case MEP_OPERAND_CRQP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 5, 32, total_length, pc, & fields->f_ivc2_5u13); + break; + case MEP_OPERAND_CSRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_csrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_csrn_lo); + if (length <= 0) break; + FLD (f_csrn) = ((((FLD (f_csrn_hi)) << (4))) | (FLD (f_csrn_lo))); + } + break; + case MEP_OPERAND_CSRN_IDX : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_csrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_csrn_lo); + if (length <= 0) break; + FLD (f_csrn) = ((((FLD (f_csrn_hi)) << (4))) | (FLD (f_csrn_lo))); + } + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_IMM16P0 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20); + if (length <= 0) break; +{ + FLD (f_ivc2_imm16p0) = ((FLD (f_ivc2_8u20)) | (((FLD (f_ivc2_8u0)) << (8)))); +} + } + break; + case MEP_OPERAND_IMM3P12 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_ivc2_3u12); + break; + case MEP_OPERAND_IMM3P25 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_ivc2_3u25); + break; + case MEP_OPERAND_IMM3P4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_ivc2_3u4); + break; + case MEP_OPERAND_IMM3P5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_ivc2_3u5); + break; + case MEP_OPERAND_IMM3P9 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_ivc2_3u9); + break; + case MEP_OPERAND_IMM4P10 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 4, 32, total_length, pc, & fields->f_ivc2_4u10); + break; + case MEP_OPERAND_IMM4P4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_4u4); + break; + case MEP_OPERAND_IMM4P8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_ivc2_4u8); + break; + case MEP_OPERAND_IMM5P23 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 5, 32, total_length, pc, & fields->f_ivc2_5u23); + break; + case MEP_OPERAND_IMM5P3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 5, 32, total_length, pc, & fields->f_ivc2_5u3); + break; + case MEP_OPERAND_IMM5P7 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 5, 32, total_length, pc, & fields->f_ivc2_5u7); + break; + case MEP_OPERAND_IMM5P8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 5, 32, total_length, pc, & fields->f_ivc2_5u8); + break; + case MEP_OPERAND_IMM6P2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 6, 32, total_length, pc, & fields->f_ivc2_6u2); + break; + case MEP_OPERAND_IMM6P6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 6, 32, total_length, pc, & fields->f_ivc2_6u6); + break; + case MEP_OPERAND_IMM8P0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0); + break; + case MEP_OPERAND_IMM8P20 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20); + break; + case MEP_OPERAND_IMM8P4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_ivc2_8u4); + break; + case MEP_OPERAND_IVC_X_0_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 2, 32, total_length, pc, & fields->f_ivc2_2u0); + break; + case MEP_OPERAND_IVC_X_0_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 3, 32, total_length, pc, & fields->f_ivc2_3u0); + break; + case MEP_OPERAND_IVC_X_0_4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_4u0); + break; + case MEP_OPERAND_IVC_X_0_5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 5, 32, total_length, pc, & fields->f_ivc2_5u0); + break; + case MEP_OPERAND_IVC_X_6_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_ivc2_1u6); + break; + case MEP_OPERAND_IVC_X_6_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 2, 32, total_length, pc, & fields->f_ivc2_2u6); + break; + case MEP_OPERAND_IVC_X_6_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6); + break; + case MEP_OPERAND_IVC2_ACC0_0 : + break; + case MEP_OPERAND_IVC2_ACC0_1 : + break; + case MEP_OPERAND_IVC2_ACC0_2 : + break; + case MEP_OPERAND_IVC2_ACC0_3 : + break; + case MEP_OPERAND_IVC2_ACC0_4 : + break; + case MEP_OPERAND_IVC2_ACC0_5 : + break; + case MEP_OPERAND_IVC2_ACC0_6 : + break; + case MEP_OPERAND_IVC2_ACC0_7 : + break; + case MEP_OPERAND_IVC2_ACC1_0 : + break; + case MEP_OPERAND_IVC2_ACC1_1 : + break; + case MEP_OPERAND_IVC2_ACC1_2 : + break; + case MEP_OPERAND_IVC2_ACC1_3 : + break; + case MEP_OPERAND_IVC2_ACC1_4 : + break; + case MEP_OPERAND_IVC2_ACC1_5 : + break; + case MEP_OPERAND_IVC2_ACC1_6 : + break; + case MEP_OPERAND_IVC2_ACC1_7 : + break; + case MEP_OPERAND_IVC2_CC : + break; + case MEP_OPERAND_IVC2_COFA0 : + break; + case MEP_OPERAND_IVC2_COFA1 : + break; + case MEP_OPERAND_IVC2_COFR0 : + break; + case MEP_OPERAND_IVC2_COFR1 : + break; + case MEP_OPERAND_IVC2_CSAR0 : + break; + case MEP_OPERAND_IVC2_CSAR1 : + break; + case MEP_OPERAND_IVC2C3CCRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_c3hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_c3lo); + if (length <= 0) break; + FLD (f_ivc2_ccrn_c3) = ((((FLD (f_ivc2_ccrn_c3hi)) << (4))) | (FLD (f_ivc2_ccrn_c3lo))); + } + break; + case MEP_OPERAND_IVC2CCRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_h2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_lo); + if (length <= 0) break; + FLD (f_ivc2_ccrn) = ((((FLD (f_ivc2_ccrn_h2)) << (4))) | (FLD (f_ivc2_ccrn_lo))); + } + break; + case MEP_OPERAND_IVC2CRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_ivc2_ccrn_h1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_lo); + if (length <= 0) break; + FLD (f_ivc2_crnx) = ((((FLD (f_ivc2_ccrn_h1)) << (4))) | (FLD (f_ivc2_ccrn_lo))); + } + break; + case MEP_OPERAND_IVC2RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_crm); + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u5a2n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 7, 32, total_length, pc, & fields->f_24u5a2n_lo); + if (length <= 0) break; + FLD (f_24u5a2n) = ((((FLD (f_24u5a2n_hi)) << (8))) | (((FLD (f_24u5a2n_lo)) << (1)))); + } + break; + case MEP_OPERAND_PCREL12A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_12s4a2 = value; + } + break; + case MEP_OPERAND_PCREL17A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_17s16a2 = value; + } + break; + case MEP_OPERAND_PCREL24A2 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_24s5a2n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_24s5a2n_lo); + if (length <= 0) break; + FLD (f_24s5a2n) = ((((((FLD (f_24s5a2n_hi)) << (8))) | (((FLD (f_24s5a2n_lo)) << (1))))) + (pc)); + } + break; + case MEP_OPERAND_PCREL8A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_8s8a2 = value; + } + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_rl); + break; + case MEP_OPERAND_RL5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_rl5); + break; + case MEP_OPERAND_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_RMA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_RN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RN3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3L : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3US : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_16s16); + break; + case MEP_OPERAND_SIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_16s16); + break; + case MEP_OPERAND_SIMM16P0 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20); + if (length <= 0) break; +{ + FLD (f_ivc2_simm16p0) = ((FLD (f_ivc2_8u20)) | (((FLD (f_ivc2_8u0)) << (8)))); +} + } + break; + case MEP_OPERAND_SIMM6 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_6s8); + break; + case MEP_OPERAND_SIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_8s8); + break; + case MEP_OPERAND_SIMM8P0 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_ivc2_8s0); + break; + case MEP_OPERAND_SIMM8P20 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_ivc2_8s20); + break; + case MEP_OPERAND_SIMM8P4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_ivc2_8s4); + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 2, 32, total_length, pc, & fields->f_2u6); + break; + case MEP_OPERAND_UDISP7 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 7, 32, total_length, pc, & fields->f_7u9); + break; + case MEP_OPERAND_UDISP7A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 6, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_7u9a2 = value; + } + break; + case MEP_OPERAND_UDISP7A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_7u9a4 = value; + } + break; + case MEP_OPERAND_UIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_16u16); + break; + case MEP_OPERAND_UIMM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_2u10); + break; + case MEP_OPERAND_UIMM24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u8n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_24u8n_lo); + if (length <= 0) break; + FLD (f_24u8n) = ((((FLD (f_24u8n_hi)) << (8))) | (FLD (f_24u8n_lo))); + } + break; + case MEP_OPERAND_UIMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_3u5); + break; + case MEP_OPERAND_UIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_4u8); + break; + case MEP_OPERAND_UIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 5, 32, total_length, pc, & fields->f_5u8); + break; + case MEP_OPERAND_UIMM7A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_7u9a4 = value; + } + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const mep_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const mep_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int mep_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma mep_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + value = fields->f_24u8a4n; + break; + case MEP_OPERAND_C5RMUIMM20 : + value = fields->f_c5_rmuimm20; + break; + case MEP_OPERAND_C5RNMUIMM24 : + value = fields->f_c5_rnmuimm24; + break; + case MEP_OPERAND_CALLNUM : + value = fields->f_callnum; + break; + case MEP_OPERAND_CCCC : + value = fields->f_rm; + break; + case MEP_OPERAND_CCRN : + value = fields->f_ccrn; + break; + case MEP_OPERAND_CDISP10 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A2 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A4 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A8 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP12 : + value = fields->f_12s20; + break; + case MEP_OPERAND_CIMM4 : + value = fields->f_rn; + break; + case MEP_OPERAND_CIMM5 : + value = fields->f_5u24; + break; + case MEP_OPERAND_CODE16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_CODE24 : + value = fields->f_24u4n; + break; + case MEP_OPERAND_CP_FLAG : + value = 0; + break; + case MEP_OPERAND_CRN : + value = fields->f_crn; + break; + case MEP_OPERAND_CRN64 : + value = fields->f_crn; + break; + case MEP_OPERAND_CRNX : + value = fields->f_crnx; + break; + case MEP_OPERAND_CRNX64 : + value = fields->f_crnx; + break; + case MEP_OPERAND_CROC : + value = fields->f_ivc2_5u7; + break; + case MEP_OPERAND_CROP : + value = fields->f_ivc2_5u23; + break; + case MEP_OPERAND_CRPC : + value = fields->f_ivc2_5u26; + break; + case MEP_OPERAND_CRPP : + value = fields->f_ivc2_5u18; + break; + case MEP_OPERAND_CRQC : + value = fields->f_ivc2_5u21; + break; + case MEP_OPERAND_CRQP : + value = fields->f_ivc2_5u13; + break; + case MEP_OPERAND_CSRN : + value = fields->f_csrn; + break; + case MEP_OPERAND_CSRN_IDX : + value = fields->f_csrn; + break; + case MEP_OPERAND_DBG : + value = 0; + break; + case MEP_OPERAND_DEPC : + value = 0; + break; + case MEP_OPERAND_EPC : + value = 0; + break; + case MEP_OPERAND_EXC : + value = 0; + break; + case MEP_OPERAND_HI : + value = 0; + break; + case MEP_OPERAND_IMM16P0 : + value = fields->f_ivc2_imm16p0; + break; + case MEP_OPERAND_IMM3P12 : + value = fields->f_ivc2_3u12; + break; + case MEP_OPERAND_IMM3P25 : + value = fields->f_ivc2_3u25; + break; + case MEP_OPERAND_IMM3P4 : + value = fields->f_ivc2_3u4; + break; + case MEP_OPERAND_IMM3P5 : + value = fields->f_ivc2_3u5; + break; + case MEP_OPERAND_IMM3P9 : + value = fields->f_ivc2_3u9; + break; + case MEP_OPERAND_IMM4P10 : + value = fields->f_ivc2_4u10; + break; + case MEP_OPERAND_IMM4P4 : + value = fields->f_ivc2_4u4; + break; + case MEP_OPERAND_IMM4P8 : + value = fields->f_ivc2_4u8; + break; + case MEP_OPERAND_IMM5P23 : + value = fields->f_ivc2_5u23; + break; + case MEP_OPERAND_IMM5P3 : + value = fields->f_ivc2_5u3; + break; + case MEP_OPERAND_IMM5P7 : + value = fields->f_ivc2_5u7; + break; + case MEP_OPERAND_IMM5P8 : + value = fields->f_ivc2_5u8; + break; + case MEP_OPERAND_IMM6P2 : + value = fields->f_ivc2_6u2; + break; + case MEP_OPERAND_IMM6P6 : + value = fields->f_ivc2_6u6; + break; + case MEP_OPERAND_IMM8P0 : + value = fields->f_ivc2_8u0; + break; + case MEP_OPERAND_IMM8P20 : + value = fields->f_ivc2_8u20; + break; + case MEP_OPERAND_IMM8P4 : + value = fields->f_ivc2_8u4; + break; + case MEP_OPERAND_IVC_X_0_2 : + value = fields->f_ivc2_2u0; + break; + case MEP_OPERAND_IVC_X_0_3 : + value = fields->f_ivc2_3u0; + break; + case MEP_OPERAND_IVC_X_0_4 : + value = fields->f_ivc2_4u0; + break; + case MEP_OPERAND_IVC_X_0_5 : + value = fields->f_ivc2_5u0; + break; + case MEP_OPERAND_IVC_X_6_1 : + value = fields->f_ivc2_1u6; + break; + case MEP_OPERAND_IVC_X_6_2 : + value = fields->f_ivc2_2u6; + break; + case MEP_OPERAND_IVC_X_6_3 : + value = fields->f_ivc2_3u6; + break; + case MEP_OPERAND_IVC2_ACC0_0 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_1 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_2 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_3 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_4 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_5 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_6 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_7 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_0 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_1 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_2 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_3 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_4 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_5 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_6 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_7 : + value = 0; + break; + case MEP_OPERAND_IVC2_CC : + value = 0; + break; + case MEP_OPERAND_IVC2_COFA0 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFA1 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFR0 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFR1 : + value = 0; + break; + case MEP_OPERAND_IVC2_CSAR0 : + value = 0; + break; + case MEP_OPERAND_IVC2_CSAR1 : + value = 0; + break; + case MEP_OPERAND_IVC2C3CCRN : + value = fields->f_ivc2_ccrn_c3; + break; + case MEP_OPERAND_IVC2CCRN : + value = fields->f_ivc2_ccrn; + break; + case MEP_OPERAND_IVC2CRN : + value = fields->f_ivc2_crnx; + break; + case MEP_OPERAND_IVC2RM : + value = fields->f_ivc2_crm; + break; + case MEP_OPERAND_LO : + value = 0; + break; + case MEP_OPERAND_LP : + value = 0; + break; + case MEP_OPERAND_MB0 : + value = 0; + break; + case MEP_OPERAND_MB1 : + value = 0; + break; + case MEP_OPERAND_ME0 : + value = 0; + break; + case MEP_OPERAND_ME1 : + value = 0; + break; + case MEP_OPERAND_NPC : + value = 0; + break; + case MEP_OPERAND_OPT : + value = 0; + break; + case MEP_OPERAND_PCABS24A2 : + value = fields->f_24u5a2n; + break; + case MEP_OPERAND_PCREL12A2 : + value = fields->f_12s4a2; + break; + case MEP_OPERAND_PCREL17A2 : + value = fields->f_17s16a2; + break; + case MEP_OPERAND_PCREL24A2 : + value = fields->f_24s5a2n; + break; + case MEP_OPERAND_PCREL8A2 : + value = fields->f_8s8a2; + break; + case MEP_OPERAND_PSW : + value = 0; + break; + case MEP_OPERAND_R0 : + value = 0; + break; + case MEP_OPERAND_R1 : + value = 0; + break; + case MEP_OPERAND_RL : + value = fields->f_rl; + break; + case MEP_OPERAND_RL5 : + value = fields->f_rl5; + break; + case MEP_OPERAND_RM : + value = fields->f_rm; + break; + case MEP_OPERAND_RMA : + value = fields->f_rm; + break; + case MEP_OPERAND_RN : + value = fields->f_rn; + break; + case MEP_OPERAND_RN3 : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3C : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3L : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3S : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UC : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UL : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3US : + value = fields->f_rn3; + break; + case MEP_OPERAND_RNC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNS : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUS : + value = fields->f_rn; + break; + case MEP_OPERAND_SAR : + value = 0; + break; + case MEP_OPERAND_SDISP16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16P0 : + value = fields->f_ivc2_simm16p0; + break; + case MEP_OPERAND_SIMM6 : + value = fields->f_6s8; + break; + case MEP_OPERAND_SIMM8 : + value = fields->f_8s8; + break; + case MEP_OPERAND_SIMM8P0 : + value = fields->f_ivc2_8s0; + break; + case MEP_OPERAND_SIMM8P20 : + value = fields->f_ivc2_8s20; + break; + case MEP_OPERAND_SIMM8P4 : + value = fields->f_ivc2_8s4; + break; + case MEP_OPERAND_SP : + value = 0; + break; + case MEP_OPERAND_SPR : + value = 0; + break; + case MEP_OPERAND_TP : + value = 0; + break; + case MEP_OPERAND_TPR : + value = 0; + break; + case MEP_OPERAND_UDISP2 : + value = fields->f_2u6; + break; + case MEP_OPERAND_UDISP7 : + value = fields->f_7u9; + break; + case MEP_OPERAND_UDISP7A2 : + value = fields->f_7u9a2; + break; + case MEP_OPERAND_UDISP7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_UIMM16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_UIMM2 : + value = fields->f_2u10; + break; + case MEP_OPERAND_UIMM24 : + value = fields->f_24u8n; + break; + case MEP_OPERAND_UIMM3 : + value = fields->f_3u5; + break; + case MEP_OPERAND_UIMM4 : + value = fields->f_4u8; + break; + case MEP_OPERAND_UIMM5 : + value = fields->f_5u8; + break; + case MEP_OPERAND_UIMM7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_ZERO : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + value = fields->f_24u8a4n; + break; + case MEP_OPERAND_C5RMUIMM20 : + value = fields->f_c5_rmuimm20; + break; + case MEP_OPERAND_C5RNMUIMM24 : + value = fields->f_c5_rnmuimm24; + break; + case MEP_OPERAND_CALLNUM : + value = fields->f_callnum; + break; + case MEP_OPERAND_CCCC : + value = fields->f_rm; + break; + case MEP_OPERAND_CCRN : + value = fields->f_ccrn; + break; + case MEP_OPERAND_CDISP10 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A2 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A4 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP10A8 : + value = fields->f_cdisp10; + break; + case MEP_OPERAND_CDISP12 : + value = fields->f_12s20; + break; + case MEP_OPERAND_CIMM4 : + value = fields->f_rn; + break; + case MEP_OPERAND_CIMM5 : + value = fields->f_5u24; + break; + case MEP_OPERAND_CODE16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_CODE24 : + value = fields->f_24u4n; + break; + case MEP_OPERAND_CP_FLAG : + value = 0; + break; + case MEP_OPERAND_CRN : + value = fields->f_crn; + break; + case MEP_OPERAND_CRN64 : + value = fields->f_crn; + break; + case MEP_OPERAND_CRNX : + value = fields->f_crnx; + break; + case MEP_OPERAND_CRNX64 : + value = fields->f_crnx; + break; + case MEP_OPERAND_CROC : + value = fields->f_ivc2_5u7; + break; + case MEP_OPERAND_CROP : + value = fields->f_ivc2_5u23; + break; + case MEP_OPERAND_CRPC : + value = fields->f_ivc2_5u26; + break; + case MEP_OPERAND_CRPP : + value = fields->f_ivc2_5u18; + break; + case MEP_OPERAND_CRQC : + value = fields->f_ivc2_5u21; + break; + case MEP_OPERAND_CRQP : + value = fields->f_ivc2_5u13; + break; + case MEP_OPERAND_CSRN : + value = fields->f_csrn; + break; + case MEP_OPERAND_CSRN_IDX : + value = fields->f_csrn; + break; + case MEP_OPERAND_DBG : + value = 0; + break; + case MEP_OPERAND_DEPC : + value = 0; + break; + case MEP_OPERAND_EPC : + value = 0; + break; + case MEP_OPERAND_EXC : + value = 0; + break; + case MEP_OPERAND_HI : + value = 0; + break; + case MEP_OPERAND_IMM16P0 : + value = fields->f_ivc2_imm16p0; + break; + case MEP_OPERAND_IMM3P12 : + value = fields->f_ivc2_3u12; + break; + case MEP_OPERAND_IMM3P25 : + value = fields->f_ivc2_3u25; + break; + case MEP_OPERAND_IMM3P4 : + value = fields->f_ivc2_3u4; + break; + case MEP_OPERAND_IMM3P5 : + value = fields->f_ivc2_3u5; + break; + case MEP_OPERAND_IMM3P9 : + value = fields->f_ivc2_3u9; + break; + case MEP_OPERAND_IMM4P10 : + value = fields->f_ivc2_4u10; + break; + case MEP_OPERAND_IMM4P4 : + value = fields->f_ivc2_4u4; + break; + case MEP_OPERAND_IMM4P8 : + value = fields->f_ivc2_4u8; + break; + case MEP_OPERAND_IMM5P23 : + value = fields->f_ivc2_5u23; + break; + case MEP_OPERAND_IMM5P3 : + value = fields->f_ivc2_5u3; + break; + case MEP_OPERAND_IMM5P7 : + value = fields->f_ivc2_5u7; + break; + case MEP_OPERAND_IMM5P8 : + value = fields->f_ivc2_5u8; + break; + case MEP_OPERAND_IMM6P2 : + value = fields->f_ivc2_6u2; + break; + case MEP_OPERAND_IMM6P6 : + value = fields->f_ivc2_6u6; + break; + case MEP_OPERAND_IMM8P0 : + value = fields->f_ivc2_8u0; + break; + case MEP_OPERAND_IMM8P20 : + value = fields->f_ivc2_8u20; + break; + case MEP_OPERAND_IMM8P4 : + value = fields->f_ivc2_8u4; + break; + case MEP_OPERAND_IVC_X_0_2 : + value = fields->f_ivc2_2u0; + break; + case MEP_OPERAND_IVC_X_0_3 : + value = fields->f_ivc2_3u0; + break; + case MEP_OPERAND_IVC_X_0_4 : + value = fields->f_ivc2_4u0; + break; + case MEP_OPERAND_IVC_X_0_5 : + value = fields->f_ivc2_5u0; + break; + case MEP_OPERAND_IVC_X_6_1 : + value = fields->f_ivc2_1u6; + break; + case MEP_OPERAND_IVC_X_6_2 : + value = fields->f_ivc2_2u6; + break; + case MEP_OPERAND_IVC_X_6_3 : + value = fields->f_ivc2_3u6; + break; + case MEP_OPERAND_IVC2_ACC0_0 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_1 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_2 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_3 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_4 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_5 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_6 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC0_7 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_0 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_1 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_2 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_3 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_4 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_5 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_6 : + value = 0; + break; + case MEP_OPERAND_IVC2_ACC1_7 : + value = 0; + break; + case MEP_OPERAND_IVC2_CC : + value = 0; + break; + case MEP_OPERAND_IVC2_COFA0 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFA1 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFR0 : + value = 0; + break; + case MEP_OPERAND_IVC2_COFR1 : + value = 0; + break; + case MEP_OPERAND_IVC2_CSAR0 : + value = 0; + break; + case MEP_OPERAND_IVC2_CSAR1 : + value = 0; + break; + case MEP_OPERAND_IVC2C3CCRN : + value = fields->f_ivc2_ccrn_c3; + break; + case MEP_OPERAND_IVC2CCRN : + value = fields->f_ivc2_ccrn; + break; + case MEP_OPERAND_IVC2CRN : + value = fields->f_ivc2_crnx; + break; + case MEP_OPERAND_IVC2RM : + value = fields->f_ivc2_crm; + break; + case MEP_OPERAND_LO : + value = 0; + break; + case MEP_OPERAND_LP : + value = 0; + break; + case MEP_OPERAND_MB0 : + value = 0; + break; + case MEP_OPERAND_MB1 : + value = 0; + break; + case MEP_OPERAND_ME0 : + value = 0; + break; + case MEP_OPERAND_ME1 : + value = 0; + break; + case MEP_OPERAND_NPC : + value = 0; + break; + case MEP_OPERAND_OPT : + value = 0; + break; + case MEP_OPERAND_PCABS24A2 : + value = fields->f_24u5a2n; + break; + case MEP_OPERAND_PCREL12A2 : + value = fields->f_12s4a2; + break; + case MEP_OPERAND_PCREL17A2 : + value = fields->f_17s16a2; + break; + case MEP_OPERAND_PCREL24A2 : + value = fields->f_24s5a2n; + break; + case MEP_OPERAND_PCREL8A2 : + value = fields->f_8s8a2; + break; + case MEP_OPERAND_PSW : + value = 0; + break; + case MEP_OPERAND_R0 : + value = 0; + break; + case MEP_OPERAND_R1 : + value = 0; + break; + case MEP_OPERAND_RL : + value = fields->f_rl; + break; + case MEP_OPERAND_RL5 : + value = fields->f_rl5; + break; + case MEP_OPERAND_RM : + value = fields->f_rm; + break; + case MEP_OPERAND_RMA : + value = fields->f_rm; + break; + case MEP_OPERAND_RN : + value = fields->f_rn; + break; + case MEP_OPERAND_RN3 : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3C : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3L : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3S : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UC : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UL : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3US : + value = fields->f_rn3; + break; + case MEP_OPERAND_RNC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNS : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUS : + value = fields->f_rn; + break; + case MEP_OPERAND_SAR : + value = 0; + break; + case MEP_OPERAND_SDISP16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16P0 : + value = fields->f_ivc2_simm16p0; + break; + case MEP_OPERAND_SIMM6 : + value = fields->f_6s8; + break; + case MEP_OPERAND_SIMM8 : + value = fields->f_8s8; + break; + case MEP_OPERAND_SIMM8P0 : + value = fields->f_ivc2_8s0; + break; + case MEP_OPERAND_SIMM8P20 : + value = fields->f_ivc2_8s20; + break; + case MEP_OPERAND_SIMM8P4 : + value = fields->f_ivc2_8s4; + break; + case MEP_OPERAND_SP : + value = 0; + break; + case MEP_OPERAND_SPR : + value = 0; + break; + case MEP_OPERAND_TP : + value = 0; + break; + case MEP_OPERAND_TPR : + value = 0; + break; + case MEP_OPERAND_UDISP2 : + value = fields->f_2u6; + break; + case MEP_OPERAND_UDISP7 : + value = fields->f_7u9; + break; + case MEP_OPERAND_UDISP7A2 : + value = fields->f_7u9a2; + break; + case MEP_OPERAND_UDISP7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_UIMM16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_UIMM2 : + value = fields->f_2u10; + break; + case MEP_OPERAND_UIMM24 : + value = fields->f_24u8n; + break; + case MEP_OPERAND_UIMM3 : + value = fields->f_3u5; + break; + case MEP_OPERAND_UIMM4 : + value = fields->f_4u8; + break; + case MEP_OPERAND_UIMM5 : + value = fields->f_5u8; + break; + case MEP_OPERAND_UIMM7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_ZERO : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void mep_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void mep_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + fields->f_24u8a4n = value; + break; + case MEP_OPERAND_C5RMUIMM20 : + fields->f_c5_rmuimm20 = value; + break; + case MEP_OPERAND_C5RNMUIMM24 : + fields->f_c5_rnmuimm24 = value; + break; + case MEP_OPERAND_CALLNUM : + fields->f_callnum = value; + break; + case MEP_OPERAND_CCCC : + fields->f_rm = value; + break; + case MEP_OPERAND_CCRN : + fields->f_ccrn = value; + break; + case MEP_OPERAND_CDISP10 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A2 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A4 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A8 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP12 : + fields->f_12s20 = value; + break; + case MEP_OPERAND_CIMM4 : + fields->f_rn = value; + break; + case MEP_OPERAND_CIMM5 : + fields->f_5u24 = value; + break; + case MEP_OPERAND_CODE16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_CODE24 : + fields->f_24u4n = value; + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + fields->f_crn = value; + break; + case MEP_OPERAND_CRN64 : + fields->f_crn = value; + break; + case MEP_OPERAND_CRNX : + fields->f_crnx = value; + break; + case MEP_OPERAND_CRNX64 : + fields->f_crnx = value; + break; + case MEP_OPERAND_CROC : + fields->f_ivc2_5u7 = value; + break; + case MEP_OPERAND_CROP : + fields->f_ivc2_5u23 = value; + break; + case MEP_OPERAND_CRPC : + fields->f_ivc2_5u26 = value; + break; + case MEP_OPERAND_CRPP : + fields->f_ivc2_5u18 = value; + break; + case MEP_OPERAND_CRQC : + fields->f_ivc2_5u21 = value; + break; + case MEP_OPERAND_CRQP : + fields->f_ivc2_5u13 = value; + break; + case MEP_OPERAND_CSRN : + fields->f_csrn = value; + break; + case MEP_OPERAND_CSRN_IDX : + fields->f_csrn = value; + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_IMM16P0 : + fields->f_ivc2_imm16p0 = value; + break; + case MEP_OPERAND_IMM3P12 : + fields->f_ivc2_3u12 = value; + break; + case MEP_OPERAND_IMM3P25 : + fields->f_ivc2_3u25 = value; + break; + case MEP_OPERAND_IMM3P4 : + fields->f_ivc2_3u4 = value; + break; + case MEP_OPERAND_IMM3P5 : + fields->f_ivc2_3u5 = value; + break; + case MEP_OPERAND_IMM3P9 : + fields->f_ivc2_3u9 = value; + break; + case MEP_OPERAND_IMM4P10 : + fields->f_ivc2_4u10 = value; + break; + case MEP_OPERAND_IMM4P4 : + fields->f_ivc2_4u4 = value; + break; + case MEP_OPERAND_IMM4P8 : + fields->f_ivc2_4u8 = value; + break; + case MEP_OPERAND_IMM5P23 : + fields->f_ivc2_5u23 = value; + break; + case MEP_OPERAND_IMM5P3 : + fields->f_ivc2_5u3 = value; + break; + case MEP_OPERAND_IMM5P7 : + fields->f_ivc2_5u7 = value; + break; + case MEP_OPERAND_IMM5P8 : + fields->f_ivc2_5u8 = value; + break; + case MEP_OPERAND_IMM6P2 : + fields->f_ivc2_6u2 = value; + break; + case MEP_OPERAND_IMM6P6 : + fields->f_ivc2_6u6 = value; + break; + case MEP_OPERAND_IMM8P0 : + fields->f_ivc2_8u0 = value; + break; + case MEP_OPERAND_IMM8P20 : + fields->f_ivc2_8u20 = value; + break; + case MEP_OPERAND_IMM8P4 : + fields->f_ivc2_8u4 = value; + break; + case MEP_OPERAND_IVC_X_0_2 : + fields->f_ivc2_2u0 = value; + break; + case MEP_OPERAND_IVC_X_0_3 : + fields->f_ivc2_3u0 = value; + break; + case MEP_OPERAND_IVC_X_0_4 : + fields->f_ivc2_4u0 = value; + break; + case MEP_OPERAND_IVC_X_0_5 : + fields->f_ivc2_5u0 = value; + break; + case MEP_OPERAND_IVC_X_6_1 : + fields->f_ivc2_1u6 = value; + break; + case MEP_OPERAND_IVC_X_6_2 : + fields->f_ivc2_2u6 = value; + break; + case MEP_OPERAND_IVC_X_6_3 : + fields->f_ivc2_3u6 = value; + break; + case MEP_OPERAND_IVC2_ACC0_0 : + break; + case MEP_OPERAND_IVC2_ACC0_1 : + break; + case MEP_OPERAND_IVC2_ACC0_2 : + break; + case MEP_OPERAND_IVC2_ACC0_3 : + break; + case MEP_OPERAND_IVC2_ACC0_4 : + break; + case MEP_OPERAND_IVC2_ACC0_5 : + break; + case MEP_OPERAND_IVC2_ACC0_6 : + break; + case MEP_OPERAND_IVC2_ACC0_7 : + break; + case MEP_OPERAND_IVC2_ACC1_0 : + break; + case MEP_OPERAND_IVC2_ACC1_1 : + break; + case MEP_OPERAND_IVC2_ACC1_2 : + break; + case MEP_OPERAND_IVC2_ACC1_3 : + break; + case MEP_OPERAND_IVC2_ACC1_4 : + break; + case MEP_OPERAND_IVC2_ACC1_5 : + break; + case MEP_OPERAND_IVC2_ACC1_6 : + break; + case MEP_OPERAND_IVC2_ACC1_7 : + break; + case MEP_OPERAND_IVC2_CC : + break; + case MEP_OPERAND_IVC2_COFA0 : + break; + case MEP_OPERAND_IVC2_COFA1 : + break; + case MEP_OPERAND_IVC2_COFR0 : + break; + case MEP_OPERAND_IVC2_COFR1 : + break; + case MEP_OPERAND_IVC2_CSAR0 : + break; + case MEP_OPERAND_IVC2_CSAR1 : + break; + case MEP_OPERAND_IVC2C3CCRN : + fields->f_ivc2_ccrn_c3 = value; + break; + case MEP_OPERAND_IVC2CCRN : + fields->f_ivc2_ccrn = value; + break; + case MEP_OPERAND_IVC2CRN : + fields->f_ivc2_crnx = value; + break; + case MEP_OPERAND_IVC2RM : + fields->f_ivc2_crm = value; + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + fields->f_24u5a2n = value; + break; + case MEP_OPERAND_PCREL12A2 : + fields->f_12s4a2 = value; + break; + case MEP_OPERAND_PCREL17A2 : + fields->f_17s16a2 = value; + break; + case MEP_OPERAND_PCREL24A2 : + fields->f_24s5a2n = value; + break; + case MEP_OPERAND_PCREL8A2 : + fields->f_8s8a2 = value; + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + fields->f_rl = value; + break; + case MEP_OPERAND_RL5 : + fields->f_rl5 = value; + break; + case MEP_OPERAND_RM : + fields->f_rm = value; + break; + case MEP_OPERAND_RMA : + fields->f_rm = value; + break; + case MEP_OPERAND_RN : + fields->f_rn = value; + break; + case MEP_OPERAND_RN3 : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3C : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3L : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3S : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UC : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UL : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3US : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RNC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNS : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUS : + fields->f_rn = value; + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16P0 : + fields->f_ivc2_simm16p0 = value; + break; + case MEP_OPERAND_SIMM6 : + fields->f_6s8 = value; + break; + case MEP_OPERAND_SIMM8 : + fields->f_8s8 = value; + break; + case MEP_OPERAND_SIMM8P0 : + fields->f_ivc2_8s0 = value; + break; + case MEP_OPERAND_SIMM8P20 : + fields->f_ivc2_8s20 = value; + break; + case MEP_OPERAND_SIMM8P4 : + fields->f_ivc2_8s4 = value; + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + fields->f_2u6 = value; + break; + case MEP_OPERAND_UDISP7 : + fields->f_7u9 = value; + break; + case MEP_OPERAND_UDISP7A2 : + fields->f_7u9a2 = value; + break; + case MEP_OPERAND_UDISP7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_UIMM16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_UIMM2 : + fields->f_2u10 = value; + break; + case MEP_OPERAND_UIMM24 : + fields->f_24u8n = value; + break; + case MEP_OPERAND_UIMM3 : + fields->f_3u5 = value; + break; + case MEP_OPERAND_UIMM4 : + fields->f_4u8 = value; + break; + case MEP_OPERAND_UIMM5 : + fields->f_5u8 = value; + break; + case MEP_OPERAND_UIMM7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + fields->f_24u8a4n = value; + break; + case MEP_OPERAND_C5RMUIMM20 : + fields->f_c5_rmuimm20 = value; + break; + case MEP_OPERAND_C5RNMUIMM24 : + fields->f_c5_rnmuimm24 = value; + break; + case MEP_OPERAND_CALLNUM : + fields->f_callnum = value; + break; + case MEP_OPERAND_CCCC : + fields->f_rm = value; + break; + case MEP_OPERAND_CCRN : + fields->f_ccrn = value; + break; + case MEP_OPERAND_CDISP10 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A2 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A4 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP10A8 : + fields->f_cdisp10 = value; + break; + case MEP_OPERAND_CDISP12 : + fields->f_12s20 = value; + break; + case MEP_OPERAND_CIMM4 : + fields->f_rn = value; + break; + case MEP_OPERAND_CIMM5 : + fields->f_5u24 = value; + break; + case MEP_OPERAND_CODE16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_CODE24 : + fields->f_24u4n = value; + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + fields->f_crn = value; + break; + case MEP_OPERAND_CRN64 : + fields->f_crn = value; + break; + case MEP_OPERAND_CRNX : + fields->f_crnx = value; + break; + case MEP_OPERAND_CRNX64 : + fields->f_crnx = value; + break; + case MEP_OPERAND_CROC : + fields->f_ivc2_5u7 = value; + break; + case MEP_OPERAND_CROP : + fields->f_ivc2_5u23 = value; + break; + case MEP_OPERAND_CRPC : + fields->f_ivc2_5u26 = value; + break; + case MEP_OPERAND_CRPP : + fields->f_ivc2_5u18 = value; + break; + case MEP_OPERAND_CRQC : + fields->f_ivc2_5u21 = value; + break; + case MEP_OPERAND_CRQP : + fields->f_ivc2_5u13 = value; + break; + case MEP_OPERAND_CSRN : + fields->f_csrn = value; + break; + case MEP_OPERAND_CSRN_IDX : + fields->f_csrn = value; + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_IMM16P0 : + fields->f_ivc2_imm16p0 = value; + break; + case MEP_OPERAND_IMM3P12 : + fields->f_ivc2_3u12 = value; + break; + case MEP_OPERAND_IMM3P25 : + fields->f_ivc2_3u25 = value; + break; + case MEP_OPERAND_IMM3P4 : + fields->f_ivc2_3u4 = value; + break; + case MEP_OPERAND_IMM3P5 : + fields->f_ivc2_3u5 = value; + break; + case MEP_OPERAND_IMM3P9 : + fields->f_ivc2_3u9 = value; + break; + case MEP_OPERAND_IMM4P10 : + fields->f_ivc2_4u10 = value; + break; + case MEP_OPERAND_IMM4P4 : + fields->f_ivc2_4u4 = value; + break; + case MEP_OPERAND_IMM4P8 : + fields->f_ivc2_4u8 = value; + break; + case MEP_OPERAND_IMM5P23 : + fields->f_ivc2_5u23 = value; + break; + case MEP_OPERAND_IMM5P3 : + fields->f_ivc2_5u3 = value; + break; + case MEP_OPERAND_IMM5P7 : + fields->f_ivc2_5u7 = value; + break; + case MEP_OPERAND_IMM5P8 : + fields->f_ivc2_5u8 = value; + break; + case MEP_OPERAND_IMM6P2 : + fields->f_ivc2_6u2 = value; + break; + case MEP_OPERAND_IMM6P6 : + fields->f_ivc2_6u6 = value; + break; + case MEP_OPERAND_IMM8P0 : + fields->f_ivc2_8u0 = value; + break; + case MEP_OPERAND_IMM8P20 : + fields->f_ivc2_8u20 = value; + break; + case MEP_OPERAND_IMM8P4 : + fields->f_ivc2_8u4 = value; + break; + case MEP_OPERAND_IVC_X_0_2 : + fields->f_ivc2_2u0 = value; + break; + case MEP_OPERAND_IVC_X_0_3 : + fields->f_ivc2_3u0 = value; + break; + case MEP_OPERAND_IVC_X_0_4 : + fields->f_ivc2_4u0 = value; + break; + case MEP_OPERAND_IVC_X_0_5 : + fields->f_ivc2_5u0 = value; + break; + case MEP_OPERAND_IVC_X_6_1 : + fields->f_ivc2_1u6 = value; + break; + case MEP_OPERAND_IVC_X_6_2 : + fields->f_ivc2_2u6 = value; + break; + case MEP_OPERAND_IVC_X_6_3 : + fields->f_ivc2_3u6 = value; + break; + case MEP_OPERAND_IVC2_ACC0_0 : + break; + case MEP_OPERAND_IVC2_ACC0_1 : + break; + case MEP_OPERAND_IVC2_ACC0_2 : + break; + case MEP_OPERAND_IVC2_ACC0_3 : + break; + case MEP_OPERAND_IVC2_ACC0_4 : + break; + case MEP_OPERAND_IVC2_ACC0_5 : + break; + case MEP_OPERAND_IVC2_ACC0_6 : + break; + case MEP_OPERAND_IVC2_ACC0_7 : + break; + case MEP_OPERAND_IVC2_ACC1_0 : + break; + case MEP_OPERAND_IVC2_ACC1_1 : + break; + case MEP_OPERAND_IVC2_ACC1_2 : + break; + case MEP_OPERAND_IVC2_ACC1_3 : + break; + case MEP_OPERAND_IVC2_ACC1_4 : + break; + case MEP_OPERAND_IVC2_ACC1_5 : + break; + case MEP_OPERAND_IVC2_ACC1_6 : + break; + case MEP_OPERAND_IVC2_ACC1_7 : + break; + case MEP_OPERAND_IVC2_CC : + break; + case MEP_OPERAND_IVC2_COFA0 : + break; + case MEP_OPERAND_IVC2_COFA1 : + break; + case MEP_OPERAND_IVC2_COFR0 : + break; + case MEP_OPERAND_IVC2_COFR1 : + break; + case MEP_OPERAND_IVC2_CSAR0 : + break; + case MEP_OPERAND_IVC2_CSAR1 : + break; + case MEP_OPERAND_IVC2C3CCRN : + fields->f_ivc2_ccrn_c3 = value; + break; + case MEP_OPERAND_IVC2CCRN : + fields->f_ivc2_ccrn = value; + break; + case MEP_OPERAND_IVC2CRN : + fields->f_ivc2_crnx = value; + break; + case MEP_OPERAND_IVC2RM : + fields->f_ivc2_crm = value; + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + fields->f_24u5a2n = value; + break; + case MEP_OPERAND_PCREL12A2 : + fields->f_12s4a2 = value; + break; + case MEP_OPERAND_PCREL17A2 : + fields->f_17s16a2 = value; + break; + case MEP_OPERAND_PCREL24A2 : + fields->f_24s5a2n = value; + break; + case MEP_OPERAND_PCREL8A2 : + fields->f_8s8a2 = value; + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + fields->f_rl = value; + break; + case MEP_OPERAND_RL5 : + fields->f_rl5 = value; + break; + case MEP_OPERAND_RM : + fields->f_rm = value; + break; + case MEP_OPERAND_RMA : + fields->f_rm = value; + break; + case MEP_OPERAND_RN : + fields->f_rn = value; + break; + case MEP_OPERAND_RN3 : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3C : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3L : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3S : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UC : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UL : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3US : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RNC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNS : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUS : + fields->f_rn = value; + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16P0 : + fields->f_ivc2_simm16p0 = value; + break; + case MEP_OPERAND_SIMM6 : + fields->f_6s8 = value; + break; + case MEP_OPERAND_SIMM8 : + fields->f_8s8 = value; + break; + case MEP_OPERAND_SIMM8P0 : + fields->f_ivc2_8s0 = value; + break; + case MEP_OPERAND_SIMM8P20 : + fields->f_ivc2_8s20 = value; + break; + case MEP_OPERAND_SIMM8P4 : + fields->f_ivc2_8s4 = value; + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + fields->f_2u6 = value; + break; + case MEP_OPERAND_UDISP7 : + fields->f_7u9 = value; + break; + case MEP_OPERAND_UDISP7A2 : + fields->f_7u9a2 = value; + break; + case MEP_OPERAND_UDISP7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_UIMM16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_UIMM2 : + fields->f_2u10 = value; + break; + case MEP_OPERAND_UIMM24 : + fields->f_24u8n = value; + break; + case MEP_OPERAND_UIMM3 : + fields->f_3u5 = value; + break; + case MEP_OPERAND_UIMM4 : + fields->f_4u8 = value; + break; + case MEP_OPERAND_UIMM5 : + fields->f_5u8 = value; + break; + case MEP_OPERAND_UIMM7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +mep_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & mep_cgen_insert_handlers[0]; + cd->extract_handlers = & mep_cgen_extract_handlers[0]; + + cd->insert_operand = mep_cgen_insert_operand; + cd->extract_operand = mep_cgen_extract_operand; + + cd->get_int_operand = mep_cgen_get_int_operand; + cd->set_int_operand = mep_cgen_set_int_operand; + cd->get_vma_operand = mep_cgen_get_vma_operand; + cd->set_vma_operand = mep_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/mep-opc.c b/external/gpl3/gdb/dist/opcodes/mep-opc.c new file mode 100644 index 000000000000..98fce1be857f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-opc.c @@ -0,0 +1,6429 @@ +/* Instruction opcode table for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "elf/mep.h" + +/* A mask for all ISAs executed by the core. */ +CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; + +void +init_mep_all_core_isas_mask (void) +{ + if (mep_all_core_isas_mask.length != 0) + return; + cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); + cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); + /* begin-all-core-isas */ + cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); + /* end-all-core-isas */ +} + +CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; + +void +init_mep_all_cop_isas_mask (void) +{ + if (mep_all_cop_isas_mask.length != 0) + return; + cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); + /* begin-all-cop-isas */ + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); + /* end-all-cop-isas */ +} + +int +mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) +{ + CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); + return cgen_bitset_intersect_p (& insn_isas, isa_mask); +} + +#define OPTION_MASK \ + ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) + + +mep_config_map_struct mep_config_map[] = +{ + /* config-map-start */ + /* Default entry: first module, with all options enabled. */ + { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, + { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, + 0 + | (1 << CGEN_INSN_OPTIONAL_CP_INSN) + | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) + | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) + | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) + | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) + | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) + | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) + | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) + | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) + | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) + | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, + /* config-map-end */ + { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } +}; + +int mep_config_index = 0; + +static int +check_configured_mach (int machs) +{ + /* All base insns are supported. */ + int mach = 1 << MACH_BASE; + switch (MEP_CPU & EF_MEP_CPU_MASK) + { + case EF_MEP_CPU_C2: + case EF_MEP_CPU_C3: + mach |= (1 << MACH_MEP); + break; + case EF_MEP_CPU_H1: + mach |= (1 << MACH_H1); + break; + case EF_MEP_CPU_C5: + mach |= (1 << MACH_MEP); + mach |= (1 << MACH_C5); + break; + default: + break; + } + return machs & mach; +} + +int +mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); + int ok1; + int ok2; + int ok3; + + /* If the insn has an option bit set that we don't want, + reject it. */ + if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) + return 0; + + /* If attributes are absent, assume no restriction. */ + if (machs == 0) + machs = ~0; + + ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); + /* If the insn is config-specific, make sure it matches. */ + ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); + /* Make sure the insn is supported by the configured mach */ + ok3 = check_configured_mach (machs); + + return (ok1 && ok2 && ok3); +} + +int +mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ +#ifdef MEP_IVC2_SUPPORTED + /* If we're assembling VLIW packets, ignore the 12-bit BSR as we + can't relax that. The 24-bit BSR is matched instead. */ + if (insn->base->num == MEP_INSN_BSR12 + && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) + return 0; +#endif + + return mep_cgen_insn_supported (cd, insn); +} +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & mep_cgen_ifld_table[MEP_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_stcb_r ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pref ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_prefd ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_casb3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_C5N4) }, { F (F_RL5) }, { F (F_C5N6) }, { F (F_C5N7) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbcp ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_12S20) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbucpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhucpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_uci ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dsp ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dsp0 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_C5_RNMUIMM24) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dsp1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_C5_RMUIMM20) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xf083, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf880, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf881, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf883, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf880, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf881, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0030000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_24U8A4N) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extb ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ssarb ATTRIBUTE_UNUSED = { + 16, 16, 0xfc0f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_5) }, { F (F_2U6) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movi8 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movi16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movu24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_24U8N) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_RL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 16, 16, 0xf003, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_6S8) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3i ATTRIBUTE_UNUSED = { + 16, 16, 0xf083, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slt3i ATTRIBUTE_UNUSED = { + 16, 16, 0xf007, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_5U8) }, { F (F_SUB3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra ATTRIBUTE_UNUSED = { + 16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_12S4A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = { + 16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8S8A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqi ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_4U8) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bsr24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf80f0000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_24S5A2N) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf80f0000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_24U5A2N) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_repeat ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_erepeat ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc_lp ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_CSRN_LO) }, { F (F_12) }, { F (F_13) }, { F (F_14) }, { F (F_CSRN_HI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc ATTRIBUTE_UNUSED = { + 16, 16, 0xf00e, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_CSRN) }, { F (F_12) }, { F (F_13) }, { F (F_14) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = { + 16, 16, 0xffcf, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_9) }, { F (F_2U10) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bsetm ATTRIBUTE_UNUSED = { + 16, 16, 0xf80f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_3U5) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_madd ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ffff07, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_5U24) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffc00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT4) }, { F (F_EXT62) }, { F (F_CDISP10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcpeq ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sim_syscall ATTRIBUTE_UNUSED = { + 16, 16, 0xf8ef, { { F (F_MAJOR) }, { F (F_4) }, { F (F_CALLNUM) }, { F (F_8) }, { F (F_9) }, { F (F_10) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_crn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffff7, { { F (F_MAJOR) }, { F (F_CRNX) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovc_ccrn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffff3, { { F (F_MAJOR) }, { F (F_IVC2_CCRN_C3) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_crn_rm_p0 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff7ff, { { F (F_IVC2_CRNX) }, { F (F_IVC2_CRM) }, { F (F_IVC2_CMOV1) }, { F (F_21) }, { F (F_IVC2_CMOV2) }, { F (F_IVC2_CMOV3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovc_ccrn_rm_p0 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff3ff, { { F (F_IVC2_CCRN) }, { F (F_IVC2_CRM) }, { F (F_IVC2_CMOV1) }, { F (F_IVC2_CMOV2) }, { F (F_IVC2_CMOV3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpadd3_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0ff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfsftbi_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovfrcsar0_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0fffff, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovtocsar0_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff83f, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmov_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0ff83f, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpcmpeqz_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_3U6) }, { F (F_IVC2_3U9) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_h_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_2U6) }, { F (F_IVC2_4U8) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_w_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_1U6) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cdsrli3_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_6U6) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff83f, { { F (F_MAJOR) }, { F (F_IVC2_8S4) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmoviu_h_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff83f, { { F (F_MAJOR) }, { F (F_IVC2_8U4) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrlia1_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0fffff, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_1U6) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_c0nop_P0_P0S ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpadd3_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff8000f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmov_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff83e0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpccadd_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff83fff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovfrcsar0_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffffe0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpcmpeqz_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff801ff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrlia0_P0S ATTRIBUTE_UNUSED = { + 32, 32, 0xfffffe0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfsftbi_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000f, { { F (F_IVC2_5U0) }, { F (F_IVC2_3U5) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_b_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_5U0) }, { F (F_IVC2_3U5) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_h_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_4U0) }, { F (F_IVC2_4U4) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_w_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_3U0) }, { F (F_IVC2_5U3) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cdsrli3_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_2U0) }, { F (F_IVC2_6U2) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_h_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8300f, { { F (F_IVC2_SIMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmoviu_w_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8300f, { { F (F_IVC2_IMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff8300f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_8U20) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfmulia1s0u_b_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf801ff, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfmulia1u_b_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8018f, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_2U23) }, { F (F_IVC2_3U25) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) MEP_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* stcb $rn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_stcb_r, { 0x700c } + }, +/* ldcb $rn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_stcb_r, { 0x700d } + }, +/* pref $cimm4,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_pref, { 0x7005 } + }, +/* pref $cimm4,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CIMM4), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_prefd, { 0xf0030000 } + }, +/* casb3 $rl5,$rn,($rm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } }, + & ifmt_casb3, { 0xf0012000 } + }, +/* cash3 $rl5,$rn,($rm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } }, + & ifmt_casb3, { 0xf0012001 } + }, +/* casw3 $rl5,$rn,($rm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RL5), ',', OP (RN), ',', '(', OP (RM), ')', 0 } }, + & ifmt_casb3, { 0xf0012002 } + }, +/* sbcp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf0060000 } + }, +/* lbcp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf0064000 } + }, +/* lbucp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf006c000 } + }, +/* shcp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf0061000 } + }, +/* lhcp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf0065000 } + }, +/* lhucp $crn,$cdisp12($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (CDISP12), '(', OP (RMA), ')', 0 } }, + & ifmt_sbcp, { 0xf006d000 } + }, +/* lbucpa $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf005c000 } + }, +/* lhucpa $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf005d000 } + }, +/* lbucpm0 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf005c800 } + }, +/* lhucpm0 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf005d800 } + }, +/* lbucpm1 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf005cc00 } + }, +/* lhucpm1 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf005dc00 } + }, +/* uci $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_uci, { 0xf0020000 } + }, +/* dsp $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_dsp, { 0xf0000000 } + }, +/* dsp0 $c5rnmuimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (C5RNMUIMM24), 0 } }, + & ifmt_dsp0, { 0xf0000000 } + }, +/* dsp1 $rn,$c5rmuimm20 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (C5RMUIMM20), 0 } }, + & ifmt_dsp1, { 0xf0000000 } + }, +/* sb $rnc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sb, { 0x8 } + }, +/* sh $rns,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sh, { 0x9 } + }, +/* sw $rnl,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sw, { 0xa } + }, +/* lb $rnc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sb, { 0xc } + }, +/* lh $rns,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sh, { 0xd } + }, +/* lw $rnl,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sw, { 0xe } + }, +/* lbu $rnuc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_lbu, { 0xb } + }, +/* lhu $rnus,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_lhu, { 0xf } + }, +/* sw $rnl,$udisp7a4($spr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } }, + & ifmt_sw_sp, { 0x4002 } + }, +/* lw $rnl,$udisp7a4($spr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } }, + & ifmt_sw_sp, { 0x4003 } + }, +/* sb $rn3c,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3C), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_sb_tp, { 0x8000 } + }, +/* sh $rn3s,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3S), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_sh_tp, { 0x8080 } + }, +/* sw $rn3l,$udisp7a4($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3L), ',', OP (UDISP7A4), '(', OP (TPR), ')', 0 } }, + & ifmt_sw_tp, { 0x4082 } + }, +/* lb $rn3c,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3C), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_sb_tp, { 0x8800 } + }, +/* lh $rn3s,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3S), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_sh_tp, { 0x8880 } + }, +/* lw $rn3l,$udisp7a4($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3L), ',', OP (UDISP7A4), '(', OP (TPR), ')', 0 } }, + & ifmt_sw_tp, { 0x4083 } + }, +/* lbu $rn3uc,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3UC), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_lbu_tp, { 0x4880 } + }, +/* lhu $rn3us,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3US), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_lhu_tp, { 0x8881 } + }, +/* sb $rnc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sb16, { 0xc0080000 } + }, +/* sh $rns,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sh16, { 0xc0090000 } + }, +/* sw $rnl,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sw16, { 0xc00a0000 } + }, +/* lb $rnc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sb16, { 0xc00c0000 } + }, +/* lh $rns,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sh16, { 0xc00d0000 } + }, +/* lw $rnl,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sw16, { 0xc00e0000 } + }, +/* lbu $rnuc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_lbu16, { 0xc00b0000 } + }, +/* lhu $rnus,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_lhu16, { 0xc00f0000 } + }, +/* sw $rnl,($addr24a4) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (ADDR24A4), ')', 0 } }, + & ifmt_sw24, { 0xe0020000 } + }, +/* lw $rnl,($addr24a4) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (ADDR24A4), ')', 0 } }, + & ifmt_sw24, { 0xe0030000 } + }, +/* extb $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x100d } + }, +/* exth $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x102d } + }, +/* extub $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x108d } + }, +/* extuh $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x10ad } + }, +/* ssarb $udisp2($rm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UDISP2), '(', OP (RM), ')', 0 } }, + & ifmt_ssarb, { 0x100c } + }, +/* mov $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x0 } + }, +/* mov $rn,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM8), 0 } }, + & ifmt_movi8, { 0x5000 } + }, +/* mov $rn,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM16), 0 } }, + & ifmt_movi16, { 0xc0010000 } + }, +/* movu $rn3,$uimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3), ',', OP (UIMM24), 0 } }, + & ifmt_movu24, { 0xd0000000 } + }, +/* movu $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xc0110000 } + }, +/* movh $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xc0210000 } + }, +/* add3 $rl,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RL), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add3, { 0x9000 } + }, +/* add $rn,$simm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM6), 0 } }, + & ifmt_add, { 0x6000 } + }, +/* add3 $rn,$spr,$uimm7a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } }, + & ifmt_add3i, { 0x4000 } + }, +/* advck3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x7 } + }, +/* sub $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x4 } + }, +/* sbvck3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x5 } + }, +/* neg $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1 } + }, +/* slt3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2 } + }, +/* sltu3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x3 } + }, +/* slt3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6001 } + }, +/* sltu3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6005 } + }, +/* sl1ad3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2006 } + }, +/* sl2ad3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2007 } + }, +/* add3 $rn,$rm,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } }, + & ifmt_uci, { 0xc0000000 } + }, +/* slt3 $rn,$rm,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } }, + & ifmt_uci, { 0xc0020000 } + }, +/* sltu3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_dsp, { 0xc0030000 } + }, +/* or $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1000 } + }, +/* and $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1001 } + }, +/* xor $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1002 } + }, +/* nor $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1003 } + }, +/* or3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_dsp, { 0xc0040000 } + }, +/* and3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_dsp, { 0xc0050000 } + }, +/* xor3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_dsp, { 0xc0060000 } + }, +/* sra $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200d } + }, +/* srl $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200c } + }, +/* sll $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200e } + }, +/* sra $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6003 } + }, +/* srl $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6002 } + }, +/* sll $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6006 } + }, +/* sll3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6007 } + }, +/* fsft $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200f } + }, +/* bra $pcrel12a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL12A2), 0 } }, + & ifmt_bra, { 0xb000 } + }, +/* beqz $rn,$pcrel8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL8A2), 0 } }, + & ifmt_beqz, { 0xa000 } + }, +/* bnez $rn,$pcrel8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL8A2), 0 } }, + & ifmt_beqz, { 0xa001 } + }, +/* beqi $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0000000 } + }, +/* bnei $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0040000 } + }, +/* blti $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe00c0000 } + }, +/* bgei $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0080000 } + }, +/* beq $rn,$rm,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (PCREL17A2), 0 } }, + & ifmt_beq, { 0xe0010000 } + }, +/* bne $rn,$rm,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (PCREL17A2), 0 } }, + & ifmt_beq, { 0xe0050000 } + }, +/* bsr $pcrel12a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL12A2), 0 } }, + & ifmt_bra, { 0xb001 } + }, +/* bsr $pcrel24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL24A2), 0 } }, + & ifmt_bsr24, { 0xd8090000 } + }, +/* jmp $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x100e } + }, +/* jmp $pcabs24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCABS24A2), 0 } }, + & ifmt_jmp24, { 0xd8080000 } + }, +/* jsr $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x100f } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7002 } + }, +/* repeat $rn,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL17A2), 0 } }, + & ifmt_repeat, { 0xe0090000 } + }, +/* erepeat $pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL17A2), 0 } }, + & ifmt_erepeat, { 0xe0190000 } + }, +/* stc $rn,\$lp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'p', 0 } }, + & ifmt_stc_lp, { 0x7018 } + }, +/* stc $rn,\$hi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'h', 'i', 0 } }, + & ifmt_stc_lp, { 0x7078 } + }, +/* stc $rn,\$lo */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'o', 0 } }, + & ifmt_stc_lp, { 0x7088 } + }, +/* stc $rn,$csrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CSRN), 0 } }, + & ifmt_stc, { 0x7008 } + }, +/* ldc $rn,\$lp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'p', 0 } }, + & ifmt_stc_lp, { 0x701a } + }, +/* ldc $rn,\$hi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'h', 'i', 0 } }, + & ifmt_stc_lp, { 0x707a } + }, +/* ldc $rn,\$lo */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'o', 0 } }, + & ifmt_stc_lp, { 0x708a } + }, +/* ldc $rn,$csrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CSRN), 0 } }, + & ifmt_stc, { 0x700a } + }, +/* di */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7000 } + }, +/* ei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7010 } + }, +/* reti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7012 } + }, +/* halt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7022 } + }, +/* sleep */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7062 } + }, +/* swi $uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM2), 0 } }, + & ifmt_swi, { 0x7006 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7032 } + }, +/* syncm */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7011 } + }, +/* stcb $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xf0040000 } + }, +/* ldcb $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xf0140000 } + }, +/* bsetm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2000 } + }, +/* bclrm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2001 } + }, +/* bnotm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2002 } + }, +/* btstm \$0,($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2003 } + }, +/* tas $rn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_stcb_r, { 0x2004 } + }, +/* cache $cimm4,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_pref, { 0x7004 } + }, +/* mul $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1004 } + }, +/* mulu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1005 } + }, +/* mulr $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1006 } + }, +/* mulru $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1007 } + }, +/* madd $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013004 } + }, +/* maddu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013005 } + }, +/* maddr $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013006 } + }, +/* maddru $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013007 } + }, +/* div $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1008 } + }, +/* divu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1009 } + }, +/* dret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7013 } + }, +/* dbreak */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7033 } + }, +/* ldz $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010000 } + }, +/* abs $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010003 } + }, +/* ave $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010002 } + }, +/* min $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010004 } + }, +/* max $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010005 } + }, +/* minu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010006 } + }, +/* maxu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010007 } + }, +/* clip $rn,$cimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CIMM5), 0 } }, + & ifmt_clip, { 0xf0011000 } + }, +/* clipu $rn,$cimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CIMM5), 0 } }, + & ifmt_clip, { 0xf0011001 } + }, +/* sadd $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010008 } + }, +/* ssub $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf001000a } + }, +/* saddu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010009 } + }, +/* ssubu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf001000b } + }, +/* swcp $crn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_swcp, { 0x3008 } + }, +/* lwcp $crn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_swcp, { 0x3009 } + }, +/* smcp $crn64,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_smcp, { 0x300a } + }, +/* lmcp $crn64,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_smcp, { 0x300b } + }, +/* swcpi $crn,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_swcp, { 0x3000 } + }, +/* lwcpi $crn,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_swcp, { 0x3001 } + }, +/* smcpi $crn64,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_smcp, { 0x3002 } + }, +/* lmcpi $crn64,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_smcp, { 0x3003 } + }, +/* swcp $crn,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_swcp16, { 0xf00c0000 } + }, +/* lwcp $crn,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_swcp16, { 0xf00d0000 } + }, +/* smcp $crn64,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_smcp16, { 0xf00e0000 } + }, +/* lmcp $crn64,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_smcp16, { 0xf00f0000 } + }, +/* sbcpa $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0050000 } + }, +/* lbcpa $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0054000 } + }, +/* shcpa $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0051000 } + }, +/* lhcpa $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0055000 } + }, +/* swcpa $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0052000 } + }, +/* lwcpa $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0056000 } + }, +/* smcpa $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0053000 } + }, +/* lmcpa $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0057000 } + }, +/* sbcpm0 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0050800 } + }, +/* lbcpm0 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0054800 } + }, +/* shcpm0 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0051800 } + }, +/* lhcpm0 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0055800 } + }, +/* swcpm0 $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0052800 } + }, +/* lwcpm0 $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0056800 } + }, +/* smcpm0 $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0053800 } + }, +/* lmcpm0 $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0057800 } + }, +/* sbcpm1 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0050c00 } + }, +/* lbcpm1 $crn,($rma+),$cdisp10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10), 0 } }, + & ifmt_lbucpa, { 0xf0054c00 } + }, +/* shcpm1 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0051c00 } + }, +/* lhcpm1 $crn,($rma+),$cdisp10a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A2), 0 } }, + & ifmt_lhucpa, { 0xf0055c00 } + }, +/* swcpm1 $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0052c00 } + }, +/* lwcpm1 $crn,($rma+),$cdisp10a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A4), 0 } }, + & ifmt_swcpa, { 0xf0056c00 } + }, +/* smcpm1 $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0053c00 } + }, +/* lmcpm1 $crn64,($rma+),$cdisp10a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP10A8), 0 } }, + & ifmt_smcpa, { 0xf0057c00 } + }, +/* bcpeq $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8040000 } + }, +/* bcpne $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8050000 } + }, +/* bcpat $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8060000 } + }, +/* bcpaf $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8070000 } + }, +/* synccp */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7021 } + }, +/* jsrv $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x180f } + }, +/* bsrv $pcrel24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL24A2), 0 } }, + & ifmt_bsr24, { 0xd80b0000 } + }, +/* --syscall-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_sim_syscall, { 0x7800 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x6 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x100a } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x100b } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2005 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2008 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2009 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x200a } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x200b } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3004 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3005 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3006 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300c } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300d } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300e } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300f } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x7007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700e } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700f } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xc007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xe00d } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xf008 } + }, +/* cmov $crnx64,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRNX64), ',', OP (RM), 0 } }, + & ifmt_cmov_crn_rm, { 0xf007f000 } + }, +/* cmov $rm,$crnx64 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), ',', OP (CRNX64), 0 } }, + & ifmt_cmov_crn_rm, { 0xf007f001 } + }, +/* cmovc $ivc2c3ccrn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2C3CCRN), ',', OP (RM), 0 } }, + & ifmt_cmovc_ccrn_rm, { 0xf007f002 } + }, +/* cmovc $rm,$ivc2c3ccrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), ',', OP (IVC2C3CCRN), 0 } }, + & ifmt_cmovc_ccrn_rm, { 0xf007f003 } + }, +/* cmovh $crnx64,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRNX64), ',', OP (RM), 0 } }, + & ifmt_cmov_crn_rm, { 0xf007f100 } + }, +/* cmovh $rm,$crnx64 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), ',', OP (CRNX64), 0 } }, + & ifmt_cmov_crn_rm, { 0xf007f101 } + }, +/* cmov $ivc2crn,$ivc2rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2CRN), ',', OP (IVC2RM), 0 } }, + & ifmt_cmov_crn_rm_p0, { 0xf00000 } + }, +/* cmov $ivc2rm,$ivc2crn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2RM), ',', OP (IVC2CRN), 0 } }, + & ifmt_cmov_crn_rm_p0, { 0xf00100 } + }, +/* cmovc $ivc2ccrn,$ivc2rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2CCRN), ',', OP (IVC2RM), 0 } }, + & ifmt_cmovc_ccrn_rm_p0, { 0xf00200 } + }, +/* cmovc $ivc2rm,$ivc2ccrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2RM), ',', OP (IVC2CCRN), 0 } }, + & ifmt_cmovc_ccrn_rm_p0, { 0xf00300 } + }, +/* cmovh $ivc2crn,$ivc2rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2CRN), ',', OP (IVC2RM), 0 } }, + & ifmt_cmov_crn_rm_p0, { 0xf10000 } + }, +/* cmovh $ivc2rm,$ivc2crn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IVC2RM), ',', OP (IVC2CRN), 0 } }, + & ifmt_cmov_crn_rm_p0, { 0xf10100 } + }, +/* cpadd3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0070000 } + }, +/* cpadd3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2070000 } + }, +/* cpadd3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4070000 } + }, +/* cdadd3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6070000 } + }, +/* cpsub3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8070000 } + }, +/* cpsub3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa070000 } + }, +/* cpsub3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc070000 } + }, +/* cdsub3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe070000 } + }, +/* cpand3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0070800 } + }, +/* cpor3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2070800 } + }, +/* cpnor3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4070800 } + }, +/* cpxor3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6070800 } + }, +/* cpsel $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8070800 } + }, +/* cpfsftbi $croc,$crqc,$crpc,$imm3p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), ',', OP (IMM3P4), 0 } }, + & ifmt_cpfsftbi_C3, { 0xf007e800 } + }, +/* cpfsftbs0 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc070800 } + }, +/* cpfsftbs1 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe070800 } + }, +/* cpunpacku.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0071000 } + }, +/* cpunpacku.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2071000 } + }, +/* cpunpacku.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4071000 } + }, +/* cpunpackl.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8071000 } + }, +/* cpunpackl.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa071000 } + }, +/* cpunpackl.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc071000 } + }, +/* cppacku.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8071800 } + }, +/* cppack.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa071800 } + }, +/* cppack.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe071800 } + }, +/* cpsrl3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0072000 } + }, +/* cpssrl3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2072000 } + }, +/* cpsrl3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4072000 } + }, +/* cpssrl3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6072000 } + }, +/* cpsrl3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8072000 } + }, +/* cpssrl3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa072000 } + }, +/* cdsrl3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc072000 } + }, +/* cpsra3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0072800 } + }, +/* cpssra3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2072800 } + }, +/* cpsra3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4072800 } + }, +/* cpssra3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6072800 } + }, +/* cpsra3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8072800 } + }, +/* cpssra3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa072800 } + }, +/* cdsra3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc072800 } + }, +/* cpsll3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0073000 } + }, +/* cpssll3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2073000 } + }, +/* cpsll3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4073000 } + }, +/* cpssll3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6073000 } + }, +/* cpsll3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8073000 } + }, +/* cpssll3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa073000 } + }, +/* cdsll3 $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc073000 } + }, +/* cpsla3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4073800 } + }, +/* cpsla3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8073800 } + }, +/* cpsadd3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4074000 } + }, +/* cpsadd3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6074000 } + }, +/* cpssub3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc074000 } + }, +/* cpssub3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe074000 } + }, +/* cpextuaddu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0074800 } + }, +/* cpextuadd3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2074800 } + }, +/* cpextladdu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4074800 } + }, +/* cpextladd3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6074800 } + }, +/* cpextusubu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8074800 } + }, +/* cpextusub3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa074800 } + }, +/* cpextlsubu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc074800 } + }, +/* cpextlsub3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe074800 } + }, +/* cpaveu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0075000 } + }, +/* cpave3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2075000 } + }, +/* cpave3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4075000 } + }, +/* cpave3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6075000 } + }, +/* cpaddsru3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8075000 } + }, +/* cpaddsr3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa075000 } + }, +/* cpaddsr3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfc075000 } + }, +/* cpaddsr3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfe075000 } + }, +/* cpabsu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0075800 } + }, +/* cpabs3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2075800 } + }, +/* cpabs3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf4075800 } + }, +/* cpmaxu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0076000 } + }, +/* cpmax3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2076000 } + }, +/* cpmax3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6076000 } + }, +/* cpmaxu3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8076000 } + }, +/* cpmax3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa076000 } + }, +/* cpminu3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf0076800 } + }, +/* cpmin3.b $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf2076800 } + }, +/* cpmin3.h $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf6076800 } + }, +/* cpminu3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xf8076800 } + }, +/* cpmin3.w $croc,$crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpadd3_b_C3, { 0xfa076800 } + }, +/* cpmovfrcsar0 $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0078000 } + }, +/* cpmovfrcsar1 $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007801e } + }, +/* cpmovfrcc $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0078002 } + }, +/* cpmovtocsar0 $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf0078020 } + }, +/* cpmovtocsar1 $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf007803e } + }, +/* cpmovtocc $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf0078022 } + }, +/* cpmov $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078800 } + }, +/* cpabsz.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078802 } + }, +/* cpabsz.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078804 } + }, +/* cpabsz.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078806 } + }, +/* cpldz.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078808 } + }, +/* cpldz.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007880a } + }, +/* cpnorm.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007880c } + }, +/* cpnorm.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007880e } + }, +/* cphaddu.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078810 } + }, +/* cphadd.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078812 } + }, +/* cphadd.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078814 } + }, +/* cphadd.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078816 } + }, +/* cpccadd.b $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078818 } + }, +/* cpbcast.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007881a } + }, +/* cpbcast.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007881c } + }, +/* cpbcast.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007881e } + }, +/* cpextuu.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078820 } + }, +/* cpextu.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078822 } + }, +/* cpextuu.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078824 } + }, +/* cpextu.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078826 } + }, +/* cpextlu.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078828 } + }, +/* cpextl.b $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007882a } + }, +/* cpextlu.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007882c } + }, +/* cpextl.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007882e } + }, +/* cpcastub.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078830 } + }, +/* cpcastb.h $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078832 } + }, +/* cpcastub.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078838 } + }, +/* cpcastb.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007883a } + }, +/* cpcastuh.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007883c } + }, +/* cpcasth.w $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf007883e } + }, +/* cdcastuw $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078834 } + }, +/* cdcastw $croc,$crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), ',', OP (CRQC), 0 } }, + & ifmt_cpmov_C3, { 0xf0078836 } + }, +/* cpcmpeqz.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0079000 } + }, +/* cpcmpeq.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0179000 } + }, +/* cpcmpeq.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0379000 } + }, +/* cpcmpeq.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0579000 } + }, +/* cpcmpne.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0979000 } + }, +/* cpcmpne.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0b79000 } + }, +/* cpcmpne.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0d79000 } + }, +/* cpcmpgtu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1079000 } + }, +/* cpcmpgt.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1179000 } + }, +/* cpcmpgt.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1379000 } + }, +/* cpcmpgtu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1479000 } + }, +/* cpcmpgt.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1579000 } + }, +/* cpcmpgeu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1879000 } + }, +/* cpcmpge.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1979000 } + }, +/* cpcmpge.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1b79000 } + }, +/* cpcmpgeu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1c79000 } + }, +/* cpcmpge.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1d79000 } + }, +/* cpacmpeq.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2179000 } + }, +/* cpacmpeq.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2379000 } + }, +/* cpacmpeq.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2579000 } + }, +/* cpacmpne.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2979000 } + }, +/* cpacmpne.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2b79000 } + }, +/* cpacmpne.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2d79000 } + }, +/* cpacmpgtu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3079000 } + }, +/* cpacmpgt.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3179000 } + }, +/* cpacmpgt.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3379000 } + }, +/* cpacmpgtu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3479000 } + }, +/* cpacmpgt.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3579000 } + }, +/* cpacmpgeu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3879000 } + }, +/* cpacmpge.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3979000 } + }, +/* cpacmpge.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3b79000 } + }, +/* cpacmpgeu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3c79000 } + }, +/* cpacmpge.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3d79000 } + }, +/* cpocmpeq.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4179000 } + }, +/* cpocmpeq.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4379000 } + }, +/* cpocmpeq.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4579000 } + }, +/* cpocmpne.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4979000 } + }, +/* cpocmpne.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4b79000 } + }, +/* cpocmpne.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4d79000 } + }, +/* cpocmpgtu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5079000 } + }, +/* cpocmpgt.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5179000 } + }, +/* cpocmpgt.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5379000 } + }, +/* cpocmpgtu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5479000 } + }, +/* cpocmpgt.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5579000 } + }, +/* cpocmpgeu.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5879000 } + }, +/* cpocmpge.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5979000 } + }, +/* cpocmpge.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5b79000 } + }, +/* cpocmpgeu.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5c79000 } + }, +/* cpocmpge.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf5d79000 } + }, +/* cpsrli3.b $crqc,$crpc,$imm3p9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM3P9), 0 } }, + & ifmt_cpsrli3_b_C3, { 0xf007a000 } + }, +/* cpsrli3.h $crqc,$crpc,$imm4p8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM4P8), 0 } }, + & ifmt_cpsrli3_h_C3, { 0xf407a000 } + }, +/* cpsrli3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf807a000 } + }, +/* cdsrli3 $crqc,$crpc,$imm6p6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM6P6), 0 } }, + & ifmt_cdsrli3_C3, { 0xfc07a000 } + }, +/* cpsrai3.b $crqc,$crpc,$imm3p9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM3P9), 0 } }, + & ifmt_cpsrli3_b_C3, { 0xf007a800 } + }, +/* cpsrai3.h $crqc,$crpc,$imm4p8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM4P8), 0 } }, + & ifmt_cpsrli3_h_C3, { 0xf407a800 } + }, +/* cpsrai3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf807a800 } + }, +/* cdsrai3 $crqc,$crpc,$imm6p6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM6P6), 0 } }, + & ifmt_cdsrli3_C3, { 0xfc07a800 } + }, +/* cpslli3.b $crqc,$crpc,$imm3p9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM3P9), 0 } }, + & ifmt_cpsrli3_b_C3, { 0xf007b000 } + }, +/* cpslli3.h $crqc,$crpc,$imm4p8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM4P8), 0 } }, + & ifmt_cpsrli3_h_C3, { 0xf407b000 } + }, +/* cpslli3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf807b000 } + }, +/* cdslli3 $crqc,$crpc,$imm6p6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM6P6), 0 } }, + & ifmt_cdsrli3_C3, { 0xfc07b000 } + }, +/* cpslai3.h $crqc,$crpc,$imm4p8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM4P8), 0 } }, + & ifmt_cpsrli3_h_C3, { 0xf407b800 } + }, +/* cpslai3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf807b800 } + }, +/* cpclipiu3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf007c000 } + }, +/* cpclipi3.w $crqc,$crpc,$imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM5P7), 0 } }, + & ifmt_cpsrli3_w_C3, { 0xf407c000 } + }, +/* cdclipiu3 $crqc,$crpc,$imm6p6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM6P6), 0 } }, + & ifmt_cdsrli3_C3, { 0xf807c000 } + }, +/* cdclipi3 $crqc,$crpc,$imm6p6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), ',', OP (IMM6P6), 0 } }, + & ifmt_cdsrli3_C3, { 0xfc07c000 } + }, +/* cpmovi.b $crqc,$simm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (SIMM8P4), 0 } }, + & ifmt_cpmovi_b_C3, { 0xf007c800 } + }, +/* cpmoviu.h $crqc,$imm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (IMM8P4), 0 } }, + & ifmt_cpmoviu_h_C3, { 0xf007c804 } + }, +/* cpmovi.h $crqc,$simm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (SIMM8P4), 0 } }, + & ifmt_cpmovi_b_C3, { 0xf007c806 } + }, +/* cpmoviu.w $crqc,$imm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (IMM8P4), 0 } }, + & ifmt_cpmoviu_h_C3, { 0xf007c808 } + }, +/* cpmovi.w $crqc,$simm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (SIMM8P4), 0 } }, + & ifmt_cpmovi_b_C3, { 0xf007c80a } + }, +/* cdmoviu $crqc,$imm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (IMM8P4), 0 } }, + & ifmt_cpmoviu_h_C3, { 0xf007c80c } + }, +/* cdmovi $crqc,$simm8p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (SIMM8P4), 0 } }, + & ifmt_cpmovi_b_C3, { 0xf007c80e } + }, +/* cpadda1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0070001 } + }, +/* cpadda1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0170001 } + }, +/* cpaddua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0270001 } + }, +/* cpaddla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0370001 } + }, +/* cpaddaca1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0470001 } + }, +/* cpaddaca1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0570001 } + }, +/* cpaddacua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0670001 } + }, +/* cpaddacla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0770001 } + }, +/* cpsuba1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0870001 } + }, +/* cpsuba1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0970001 } + }, +/* cpsubua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0a70001 } + }, +/* cpsubla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0b70001 } + }, +/* cpsubaca1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0c70001 } + }, +/* cpsubaca1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0d70001 } + }, +/* cpsubacua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0e70001 } + }, +/* cpsubacla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0f70001 } + }, +/* cpabsa1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1070001 } + }, +/* cpabsa1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1170001 } + }, +/* cpabsua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1270001 } + }, +/* cpabsla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1370001 } + }, +/* cpsada1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1470001 } + }, +/* cpsada1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1570001 } + }, +/* cpsadua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1670001 } + }, +/* cpsadla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1770001 } + }, +/* cpseta1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2070001 } + }, +/* cpsetua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2270001 } + }, +/* cpsetla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf2370001 } + }, +/* cpmova1.b $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072001 } + }, +/* cpmovua1.h $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072005 } + }, +/* cpmovla1.h $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072007 } + }, +/* cpmovuua1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072009 } + }, +/* cpmovula1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007200b } + }, +/* cpmovlua1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007200d } + }, +/* cpmovlla1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007200f } + }, +/* cppacka1u.b $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072021 } + }, +/* cppacka1.b $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072023 } + }, +/* cppackua1.h $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072025 } + }, +/* cppackla1.h $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072027 } + }, +/* cppackua1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf0072029 } + }, +/* cppackla1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007202b } + }, +/* cpmovhua1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007202d } + }, +/* cpmovhla1.w $croc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROC), 0 } }, + & ifmt_cpmovfrcsar0_C3, { 0xf007202f } + }, +/* cpsrla1 $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf0071001 } + }, +/* cpsraa1 $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf0171001 } + }, +/* cpslla1 $crqc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), 0 } }, + & ifmt_cpmovtocsar0_C3, { 0xf0271001 } + }, +/* cpsrlia1 $imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P7), 0 } }, + & ifmt_cpsrlia1_P1, { 0xf0071801 } + }, +/* cpsraia1 $imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P7), 0 } }, + & ifmt_cpsrlia1_P1, { 0xf4071801 } + }, +/* cpsllia1 $imm5p7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P7), 0 } }, + & ifmt_cpsrlia1_P1, { 0xf8071801 } + }, +/* cpssqa1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0070801 } + }, +/* cpssqa1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0170801 } + }, +/* cpssda1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0470801 } + }, +/* cpssda1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0570801 } + }, +/* cpmula1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0870801 } + }, +/* cpmula1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0970801 } + }, +/* cpmulua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0a70801 } + }, +/* cpmulla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0b70801 } + }, +/* cpmulua1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0c70801 } + }, +/* cpmulla1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0d70801 } + }, +/* cpmulua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0e70801 } + }, +/* cpmulla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf0f70801 } + }, +/* cpmada1u.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1070801 } + }, +/* cpmada1.b $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1170801 } + }, +/* cpmadua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1270801 } + }, +/* cpmadla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1370801 } + }, +/* cpmadua1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1470801 } + }, +/* cpmadla1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1570801 } + }, +/* cpmadua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1670801 } + }, +/* cpmadla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1770801 } + }, +/* cpmsbua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1a70801 } + }, +/* cpmsbla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1b70801 } + }, +/* cpmsbua1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1c70801 } + }, +/* cpmsbla1u.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1d70801 } + }, +/* cpmsbua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1e70801 } + }, +/* cpmsbla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf1f70801 } + }, +/* cpsmadua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3270801 } + }, +/* cpsmadla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3370801 } + }, +/* cpsmadua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3670801 } + }, +/* cpsmadla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3770801 } + }, +/* cpsmsbua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3a70801 } + }, +/* cpsmsbla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3b70801 } + }, +/* cpsmsbua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3e70801 } + }, +/* cpsmsbla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf3f70801 } + }, +/* cpmulslua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4a70801 } + }, +/* cpmulslla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4b70801 } + }, +/* cpmulslua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4e70801 } + }, +/* cpmulslla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf4f70801 } + }, +/* cpsmadslua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7270801 } + }, +/* cpsmadslla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7370801 } + }, +/* cpsmadslua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7670801 } + }, +/* cpsmadslla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7770801 } + }, +/* cpsmsbslua1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7a70801 } + }, +/* cpsmsbslla1.h $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7b70801 } + }, +/* cpsmsbslua1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7e70801 } + }, +/* cpsmsbslla1.w $crqc,$crpc */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQC), ',', OP (CRPC), 0 } }, + & ifmt_cpcmpeqz_b_C3, { 0xf7f70801 } + }, +/* c0nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0x0 } + }, +/* cpadd3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x80000 } + }, +/* cpadd3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x100000 } + }, +/* cpadd3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x180000 } + }, +/* cpunpacku.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x280000 } + }, +/* cpunpacku.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x300000 } + }, +/* cpunpacku.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x380000 } + }, +/* cpunpackl.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x480000 } + }, +/* cpunpackl.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x500000 } + }, +/* cpunpackl.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x580000 } + }, +/* cpsel $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x200000 } + }, +/* cpfsftbs0 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x600000 } + }, +/* cpfsftbs1 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x680000 } + }, +/* cpmov $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800000 } + }, +/* cpabsz.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800200 } + }, +/* cpabsz.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800400 } + }, +/* cpabsz.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800600 } + }, +/* cpldz.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800800 } + }, +/* cpldz.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800a00 } + }, +/* cpnorm.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800c00 } + }, +/* cpnorm.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x800e00 } + }, +/* cphaddu.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801000 } + }, +/* cphadd.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801200 } + }, +/* cphadd.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801400 } + }, +/* cphadd.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801600 } + }, +/* cpccadd.b $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0x801800 } + }, +/* cpbcast.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801a00 } + }, +/* cpbcast.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801c00 } + }, +/* cpbcast.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x801e00 } + }, +/* cpextuu.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802000 } + }, +/* cpextu.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802200 } + }, +/* cpextuu.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802400 } + }, +/* cpextu.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802600 } + }, +/* cpextlu.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802800 } + }, +/* cpextl.b $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802a00 } + }, +/* cpextlu.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802c00 } + }, +/* cpextl.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x802e00 } + }, +/* cpcastub.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803000 } + }, +/* cpcastb.h $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803200 } + }, +/* cpcastub.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803800 } + }, +/* cpcastb.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803a00 } + }, +/* cpcastuh.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803c00 } + }, +/* cpcasth.w $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803e00 } + }, +/* cdcastuw $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803400 } + }, +/* cdcastw $crop,$crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), 0 } }, + & ifmt_cpmov_P0S_P1, { 0x803600 } + }, +/* cpmovfrcsar0 $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0x880000 } + }, +/* cpmovfrcsar1 $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0x881e00 } + }, +/* cpmovfrcc $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0x880200 } + }, +/* cpmovtocsar0 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0x882000 } + }, +/* cpmovtocsar1 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0x883e00 } + }, +/* cpmovtocc $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0x882200 } + }, +/* cpcmpeqz.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900000 } + }, +/* cpcmpeq.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900010 } + }, +/* cpcmpeq.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900030 } + }, +/* cpcmpeq.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900050 } + }, +/* cpcmpne.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900090 } + }, +/* cpcmpne.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9000b0 } + }, +/* cpcmpne.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9000d0 } + }, +/* cpcmpgtu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900100 } + }, +/* cpcmpgt.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900110 } + }, +/* cpcmpgt.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900130 } + }, +/* cpcmpgtu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900140 } + }, +/* cpcmpgt.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900150 } + }, +/* cpcmpgeu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900180 } + }, +/* cpcmpge.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x900190 } + }, +/* cpcmpge.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9001b0 } + }, +/* cpcmpgeu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9001c0 } + }, +/* cpcmpge.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9001d0 } + }, +/* cpadda0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00000 } + }, +/* cpadda0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00010 } + }, +/* cpaddua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00020 } + }, +/* cpaddla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00030 } + }, +/* cpaddaca0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00040 } + }, +/* cpaddaca0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00050 } + }, +/* cpaddacua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00060 } + }, +/* cpaddacla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00070 } + }, +/* cpsuba0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00080 } + }, +/* cpsuba0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00090 } + }, +/* cpsubua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000a0 } + }, +/* cpsubla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000b0 } + }, +/* cpsubaca0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000c0 } + }, +/* cpsubaca0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000d0 } + }, +/* cpsubacua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000e0 } + }, +/* cpsubacla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000f0 } + }, +/* cpabsa0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00100 } + }, +/* cpabsa0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00110 } + }, +/* cpabsua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00120 } + }, +/* cpabsla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00130 } + }, +/* cpsada0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00140 } + }, +/* cpsada0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00150 } + }, +/* cpsadua0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00160 } + }, +/* cpsadla0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00170 } + }, +/* cpseta0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001b0 } + }, +/* cpsetua0.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001c0 } + }, +/* cpsetla0.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001d0 } + }, +/* cpmova0.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80200 } + }, +/* cpmovua0.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80400 } + }, +/* cpmovla0.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80600 } + }, +/* cpmovuua0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80800 } + }, +/* cpmovula0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80a00 } + }, +/* cpmovlua0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80c00 } + }, +/* cpmovlla0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80e00 } + }, +/* cppacka0u.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81000 } + }, +/* cppacka0.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81200 } + }, +/* cppackua0.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81400 } + }, +/* cppackla0.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81600 } + }, +/* cppackua0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81800 } + }, +/* cppackla0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81a00 } + }, +/* cpmovhua0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81c00 } + }, +/* cpmovhla0.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81e00 } + }, +/* cpacsuma0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0xc82000 } + }, +/* cpaccpa0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0xc82200 } + }, +/* cpsrla0 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83000 } + }, +/* cpsraa0 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83200 } + }, +/* cpslla0 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83400 } + }, +/* cpsrlia0 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83800 } + }, +/* cpsraia0 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83a00 } + }, +/* cpsllia0 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83c00 } + }, +/* cpfsftba0s0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80000 } + }, +/* cpfsftba0s0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80010 } + }, +/* cpfsftbua0s0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80020 } + }, +/* cpfsftbla0s0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80030 } + }, +/* cpfaca0s0u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80040 } + }, +/* cpfaca0s0.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80050 } + }, +/* cpfacua0s0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80060 } + }, +/* cpfacla0s0.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80070 } + }, +/* cpfsftba0s1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80080 } + }, +/* cpfsftba0s1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf80090 } + }, +/* cpfsftbua0s1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800a0 } + }, +/* cpfsftbla0s1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800b0 } + }, +/* cpfaca0s1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800c0 } + }, +/* cpfaca0s1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800d0 } + }, +/* cpfacua0s1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800e0 } + }, +/* cpfacla0s1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf800f0 } + }, +/* cpfsftbi $crop,$crqp,$crpp,$imm3p5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P5), 0 } }, + & ifmt_cpfsftbi_P0_P1, { 0x400000 } + }, +/* cpacmpeq.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980010 } + }, +/* cpacmpeq.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980030 } + }, +/* cpacmpeq.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980050 } + }, +/* cpacmpne.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980090 } + }, +/* cpacmpne.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9800b0 } + }, +/* cpacmpne.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9800d0 } + }, +/* cpacmpgtu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980100 } + }, +/* cpacmpgt.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980110 } + }, +/* cpacmpgt.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980130 } + }, +/* cpacmpgtu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980140 } + }, +/* cpacmpgt.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980150 } + }, +/* cpacmpgeu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980180 } + }, +/* cpacmpge.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x980190 } + }, +/* cpacmpge.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9801b0 } + }, +/* cpacmpgeu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9801c0 } + }, +/* cpacmpge.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x9801d0 } + }, +/* cpocmpeq.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980010 } + }, +/* cpocmpeq.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980030 } + }, +/* cpocmpeq.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980050 } + }, +/* cpocmpne.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980090 } + }, +/* cpocmpne.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x19800b0 } + }, +/* cpocmpne.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x19800d0 } + }, +/* cpocmpgtu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980100 } + }, +/* cpocmpgt.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980110 } + }, +/* cpocmpgt.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980130 } + }, +/* cpocmpgtu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980140 } + }, +/* cpocmpgt.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980150 } + }, +/* cpocmpgeu.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980180 } + }, +/* cpocmpge.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1980190 } + }, +/* cpocmpge.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x19801b0 } + }, +/* cpocmpgeu.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x19801c0 } + }, +/* cpocmpge.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x19801d0 } + }, +/* cdadd3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x3a00000 } + }, +/* cpsub3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4a00000 } + }, +/* cpsub3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x5a00000 } + }, +/* cpsub3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x6a00000 } + }, +/* cdsub3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x7a00000 } + }, +/* cpsadd3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0xaa00000 } + }, +/* cpsadd3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0xba00000 } + }, +/* cpssub3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0xea00000 } + }, +/* cpssub3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0xfa00000 } + }, +/* cpextuaddu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x10a00000 } + }, +/* cpextuadd3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x11a00000 } + }, +/* cpextladdu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x12a00000 } + }, +/* cpextladd3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x13a00000 } + }, +/* cpextusubu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x14a00000 } + }, +/* cpextusub3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x15a00000 } + }, +/* cpextlsubu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x16a00000 } + }, +/* cpextlsub3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x17a00000 } + }, +/* cpaveu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x18a00000 } + }, +/* cpave3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x19a00000 } + }, +/* cpave3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1aa00000 } + }, +/* cpave3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1ba00000 } + }, +/* cpaddsru3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1ca00000 } + }, +/* cpaddsr3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1da00000 } + }, +/* cpaddsr3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1ea00000 } + }, +/* cpaddsr3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x1fa00000 } + }, +/* cpabsu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x20a00000 } + }, +/* cpabs3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x21a00000 } + }, +/* cpabs3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x22a00000 } + }, +/* cpand3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x24a00000 } + }, +/* cpor3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x25a00000 } + }, +/* cpnor3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x26a00000 } + }, +/* cpxor3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x27a00000 } + }, +/* cppacku.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x2ca00000 } + }, +/* cppack.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x2da00000 } + }, +/* cppack.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x2fa00000 } + }, +/* cpmaxu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x30a00000 } + }, +/* cpmax3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x31a00000 } + }, +/* cpmax3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x33a00000 } + }, +/* cpmaxu3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x34a00000 } + }, +/* cpmax3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x35a00000 } + }, +/* cpminu3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x38a00000 } + }, +/* cpmin3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x39a00000 } + }, +/* cpmin3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x3ba00000 } + }, +/* cpminu3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x3ca00000 } + }, +/* cpmin3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x3da00000 } + }, +/* cpsrl3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x40a00000 } + }, +/* cpssrl3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x41a00000 } + }, +/* cpsrl3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x42a00000 } + }, +/* cpssrl3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x43a00000 } + }, +/* cpsrl3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x44a00000 } + }, +/* cpssrl3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x45a00000 } + }, +/* cdsrl3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x46a00000 } + }, +/* cpsra3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x48a00000 } + }, +/* cpssra3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x49a00000 } + }, +/* cpsra3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4aa00000 } + }, +/* cpssra3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4ba00000 } + }, +/* cpsra3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4ca00000 } + }, +/* cpssra3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4da00000 } + }, +/* cdsra3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x4ea00000 } + }, +/* cpsll3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x50a00000 } + }, +/* cpssll3.b $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x51a00000 } + }, +/* cpsll3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x52a00000 } + }, +/* cpssll3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x53a00000 } + }, +/* cpsll3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x54a00000 } + }, +/* cpssll3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x55a00000 } + }, +/* cdsll3 $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x56a00000 } + }, +/* cpsla3.h $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x5aa00000 } + }, +/* cpsla3.w $crop,$crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpadd3_b_P0S_P1, { 0x5ca00000 } + }, +/* cpsrli3.b $crop,$crqp,$imm3p5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM3P5), 0 } }, + & ifmt_cpsrli3_b_P0_P1, { 0xa80000 } + }, +/* cpsrli3.h $crop,$crqp,$imm4p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM4P4), 0 } }, + & ifmt_cpsrli3_h_P0_P1, { 0xa80200 } + }, +/* cpsrli3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa80400 } + }, +/* cdsrli3 $crop,$crqp,$imm6p2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM6P2), 0 } }, + & ifmt_cdsrli3_P0_P1, { 0xa80600 } + }, +/* cpsrai3.b $crop,$crqp,$imm3p5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM3P5), 0 } }, + & ifmt_cpsrli3_b_P0_P1, { 0xa80800 } + }, +/* cpsrai3.h $crop,$crqp,$imm4p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM4P4), 0 } }, + & ifmt_cpsrli3_h_P0_P1, { 0xa80a00 } + }, +/* cpsrai3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa80c00 } + }, +/* cdsrai3 $crop,$crqp,$imm6p2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM6P2), 0 } }, + & ifmt_cdsrli3_P0_P1, { 0xa80e00 } + }, +/* cpslli3.b $crop,$crqp,$imm3p5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM3P5), 0 } }, + & ifmt_cpsrli3_b_P0_P1, { 0xa81000 } + }, +/* cpslli3.h $crop,$crqp,$imm4p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM4P4), 0 } }, + & ifmt_cpsrli3_h_P0_P1, { 0xa81200 } + }, +/* cpslli3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa81400 } + }, +/* cdslli3 $crop,$crqp,$imm6p2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM6P2), 0 } }, + & ifmt_cdsrli3_P0_P1, { 0xa81600 } + }, +/* cpslai3.h $crop,$crqp,$imm4p4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM4P4), 0 } }, + & ifmt_cpsrli3_h_P0_P1, { 0xa81a00 } + }, +/* cpslai3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa81c00 } + }, +/* cpclipiu3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa82000 } + }, +/* cpclipi3.w $crop,$crqp,$imm5p3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM5P3), 0 } }, + & ifmt_cpsrli3_w_P0_P1, { 0xa82200 } + }, +/* cdclipiu3 $crop,$crqp,$imm6p2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM6P2), 0 } }, + & ifmt_cdsrli3_P0_P1, { 0xa82400 } + }, +/* cdclipi3 $crop,$crqp,$imm6p2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), ',', OP (CRQP), ',', OP (IMM6P2), 0 } }, + & ifmt_cdsrli3_P0_P1, { 0xa82600 } + }, +/* cpmovi.h $crqp,$simm16p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (SIMM16P0), 0 } }, + & ifmt_cpmovi_h_P0_P1, { 0xb01000 } + }, +/* cpmoviu.w $crqp,$imm16p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (IMM16P0), 0 } }, + & ifmt_cpmoviu_w_P0_P1, { 0xb80000 } + }, +/* cpmovi.w $crqp,$simm16p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (SIMM16P0), 0 } }, + & ifmt_cpmovi_h_P0_P1, { 0xb81000 } + }, +/* cdmoviu $crqp,$imm16p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (IMM16P0), 0 } }, + & ifmt_cpmoviu_w_P0_P1, { 0xb82000 } + }, +/* cdmovi $crqp,$simm16p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (SIMM16P0), 0 } }, + & ifmt_cpmovi_h_P0_P1, { 0xb83000 } + }, +/* c1nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0x0 } + }, +/* cpmovi.b $crqp,$simm8p20 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (SIMM8P20), 0 } }, + & ifmt_cpmovi_b_P0S_P1, { 0xb00000 } + }, +/* cpadda1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00000 } + }, +/* cpadda1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00010 } + }, +/* cpaddua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00020 } + }, +/* cpaddla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00030 } + }, +/* cpaddaca1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00040 } + }, +/* cpaddaca1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00050 } + }, +/* cpaddacua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00060 } + }, +/* cpaddacla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00070 } + }, +/* cpsuba1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00080 } + }, +/* cpsuba1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00090 } + }, +/* cpsubua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000a0 } + }, +/* cpsubla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000b0 } + }, +/* cpsubaca1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000c0 } + }, +/* cpsubaca1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000d0 } + }, +/* cpsubacua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000e0 } + }, +/* cpsubacla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc000f0 } + }, +/* cpabsa1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00100 } + }, +/* cpabsa1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00110 } + }, +/* cpabsua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00120 } + }, +/* cpabsla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00130 } + }, +/* cpsada1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00140 } + }, +/* cpsada1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00150 } + }, +/* cpsadua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00160 } + }, +/* cpsadla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc00170 } + }, +/* cpseta1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001b0 } + }, +/* cpsetua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001c0 } + }, +/* cpsetla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xc001d0 } + }, +/* cpmova1.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80200 } + }, +/* cpmovua1.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80400 } + }, +/* cpmovla1.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80600 } + }, +/* cpmovuua1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80800 } + }, +/* cpmovula1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80a00 } + }, +/* cpmovlua1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80c00 } + }, +/* cpmovlla1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc80e00 } + }, +/* cppacka1u.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81000 } + }, +/* cppacka1.b $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81200 } + }, +/* cppackua1.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81400 } + }, +/* cppackla1.h $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81600 } + }, +/* cppackua1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81800 } + }, +/* cppackla1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81a00 } + }, +/* cpmovhua1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81c00 } + }, +/* cpmovhla1.w $crop */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CROP), 0 } }, + & ifmt_cpmovfrcsar0_P0S_P1, { 0xc81e00 } + }, +/* cpacsuma1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0xc82000 } + }, +/* cpaccpa1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0xc82200 } + }, +/* cpacswp */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_c0nop_P0_P0S, { 0xc82400 } + }, +/* cpsrla1 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83000 } + }, +/* cpsraa1 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83200 } + }, +/* cpslla1 $crqp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), 0 } }, + & ifmt_cpccadd_b_P0S_P1, { 0xc83400 } + }, +/* cpsrlia1 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83800 } + }, +/* cpsraia1 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83a00 } + }, +/* cpsllia1 $imm5p23 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM5P23), 0 } }, + & ifmt_cpsrlia0_P0S, { 0xc83c00 } + }, +/* cpfmulia1s0u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80000 } + }, +/* cpfmulia1s0.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80010 } + }, +/* cpfmuliua1s0.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80020 } + }, +/* cpfmulila1s0.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80030 } + }, +/* cpfmadia1s0u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80040 } + }, +/* cpfmadia1s0.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80050 } + }, +/* cpfmadiua1s0.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80060 } + }, +/* cpfmadila1s0.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80070 } + }, +/* cpfmulia1s1u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80080 } + }, +/* cpfmulia1s1.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80090 } + }, +/* cpfmuliua1s1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800a0 } + }, +/* cpfmulila1s1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800b0 } + }, +/* cpfmadia1s1u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800c0 } + }, +/* cpfmadia1s1.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800d0 } + }, +/* cpfmadiua1s1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800e0 } + }, +/* cpfmadila1s1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf800f0 } + }, +/* cpamulia1u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80100 } + }, +/* cpamulia1.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80110 } + }, +/* cpamuliua1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80120 } + }, +/* cpamulila1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80130 } + }, +/* cpamadia1u.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80140 } + }, +/* cpamadia1.b $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80150 } + }, +/* cpamadiua1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80160 } + }, +/* cpamadila1.h $crqp,$crpp,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1s0u_b_P1, { 0xf80170 } + }, +/* cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe00000 } + }, +/* cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe00080 } + }, +/* cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe00100 } + }, +/* cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe00180 } + }, +/* cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe80000 } + }, +/* cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe80080 } + }, +/* cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe80100 } + }, +/* cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), ',', OP (IMM3P25), ',', OP (SIMM8P0), 0 } }, + & ifmt_cpfmulia1u_b_P1, { 0xe80180 } + }, +/* cpssqa1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00000 } + }, +/* cpssqa1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00010 } + }, +/* cpssda1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00040 } + }, +/* cpssda1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00050 } + }, +/* cpmula1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00080 } + }, +/* cpmula1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00090 } + }, +/* cpmulua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000a0 } + }, +/* cpmulla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000b0 } + }, +/* cpmulua1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000c0 } + }, +/* cpmulla1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000d0 } + }, +/* cpmulua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000e0 } + }, +/* cpmulla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf000f0 } + }, +/* cpmada1u.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00100 } + }, +/* cpmada1.b $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00110 } + }, +/* cpmadua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00120 } + }, +/* cpmadla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00130 } + }, +/* cpmadua1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00140 } + }, +/* cpmadla1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00150 } + }, +/* cpmadua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00160 } + }, +/* cpmadla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf00170 } + }, +/* cpmsbua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001a0 } + }, +/* cpmsbla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001b0 } + }, +/* cpmsbua1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001c0 } + }, +/* cpmsbla1u.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001d0 } + }, +/* cpmsbua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001e0 } + }, +/* cpmsbla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0xf001f0 } + }, +/* cpsmadua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f00120 } + }, +/* cpsmadla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f00130 } + }, +/* cpsmadua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f00160 } + }, +/* cpsmadla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f00170 } + }, +/* cpsmsbua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f001a0 } + }, +/* cpsmsbla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f001b0 } + }, +/* cpsmsbua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f001e0 } + }, +/* cpsmsbla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x1f001f0 } + }, +/* cpmulslua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x2f000a0 } + }, +/* cpmulslla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x2f000b0 } + }, +/* cpmulslua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x2f000e0 } + }, +/* cpmulslla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x2f000f0 } + }, +/* cpsmadslua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f00120 } + }, +/* cpsmadslla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f00130 } + }, +/* cpsmadslua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f00160 } + }, +/* cpsmadslla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f00170 } + }, +/* cpsmsbslua1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f001a0 } + }, +/* cpsmsbslla1.h $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f001b0 } + }, +/* cpsmsbslua1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f001e0 } + }, +/* cpsmsbslla1.w $crqp,$crpp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRQP), ',', OP (CRPP), 0 } }, + & ifmt_cpcmpeqz_b_P0S_P1, { 0x3f001f0 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & mep_cgen_ifld_table[MEP_##f] +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lh16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lw16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lwcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lmcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) MEP_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE mep_cgen_macro_insn_table[] = +{ +/* nop */ + { + -1, "nop", "nop", 16, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + mep_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & mep_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + mep_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/mep-opc.h b/external/gpl3/gdb/dist/opcodes/mep-opc.h new file mode 100644 index 000000000000..8a626ee2128e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mep-opc.h @@ -0,0 +1,517 @@ +/* Instruction opcode header for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MEP_OPC_H +#define MEP_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 1 + +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, insn) 0 + +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +typedef struct +{ + char * name; + int config_enum; + unsigned cpu_flag; + int big_endian; + int vliw_bits; + CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; + CGEN_ATTR_VALUE_BITSET_TYPE core_isa; + unsigned int option_mask; +} mep_config_map_struct; + +extern mep_config_map_struct mep_config_map[]; +extern int mep_config_index; + +extern void init_mep_all_core_isas_mask (void); +extern void init_mep_all_cop_isas_mask (void); +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); + +#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) +#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) +#define MEP_OMASK (mep_config_map[mep_config_index].option_mask) +#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) +#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) +#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) +#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) +#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) +#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) +#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) +#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) +#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) + +/* begin-cop-ip-supported-defines */ +#define MEP_IVC2_SUPPORTED 1 +/* end-cop-ip-supported-defines */ + +extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); + +/* A mask for all ISAs executed by the core. */ +#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; + +#define MEP_INSN_CORE_P(insn) ( \ + init_mep_all_core_isas_mask (), \ + mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ +) + +/* A mask for all ISAs executed by a VLIW coprocessor. */ +#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; + +#define MEP_INSN_COP_P(insn) ( \ + init_mep_all_cop_isas_mask (), \ + mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ +) + +extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); +extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); + +/* -- asm.c */ +/* Enum declaration for mep instruction types. */ +typedef enum cgen_insn_type { + MEP_INSN_INVALID, MEP_INSN_STCB_R, MEP_INSN_LDCB_R, MEP_INSN_PREF + , MEP_INSN_PREFD, MEP_INSN_CASB3, MEP_INSN_CASH3, MEP_INSN_CASW3 + , MEP_INSN_SBCP, MEP_INSN_LBCP, MEP_INSN_LBUCP, MEP_INSN_SHCP + , MEP_INSN_LHCP, MEP_INSN_LHUCP, MEP_INSN_LBUCPA, MEP_INSN_LHUCPA + , MEP_INSN_LBUCPM0, MEP_INSN_LHUCPM0, MEP_INSN_LBUCPM1, MEP_INSN_LHUCPM1 + , MEP_INSN_UCI, MEP_INSN_DSP, MEP_INSN_DSP0, MEP_INSN_DSP1 + , MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW, MEP_INSN_LB + , MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU, MEP_INSN_LHU + , MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP, MEP_INSN_SH_TP + , MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP, MEP_INSN_LW_TP + , MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16, MEP_INSN_SH16 + , MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16, MEP_INSN_LW16 + , MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24, MEP_INSN_LW24 + , MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB, MEP_INSN_EXTUH + , MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8, MEP_INSN_MOVI16 + , MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH, MEP_INSN_ADD3 + , MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3, MEP_INSN_SUB + , MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3, MEP_INSN_SLTU3 + , MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3, MEP_INSN_SL2AD3 + , MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X, MEP_INSN_OR + , MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR, MEP_INSN_OR3 + , MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA, MEP_INSN_SRL + , MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI, MEP_INSN_SLLI + , MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA, MEP_INSN_BEQZ + , MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI, MEP_INSN_BLTI + , MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE, MEP_INSN_BSR12 + , MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24, MEP_INSN_JSR + , MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT, MEP_INSN_STC_LP + , MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC, MEP_INSN_LDC_LP + , MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC, MEP_INSN_DI + , MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT, MEP_INSN_SLEEP + , MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM, MEP_INSN_STCB + , MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM, MEP_INSN_BNOTM + , MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE, MEP_INSN_MUL + , MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU, MEP_INSN_MADD + , MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU, MEP_INSN_DIV + , MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK, MEP_INSN_LDZ + , MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN, MEP_INSN_MAX + , MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP, MEP_INSN_CLIPU + , MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU, MEP_INSN_SSUBU + , MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP, MEP_INSN_LMCP + , MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI, MEP_INSN_LMCPI + , MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16, MEP_INSN_LMCP16 + , MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA, MEP_INSN_LHCPA + , MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA, MEP_INSN_LMCPA + , MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0, MEP_INSN_LHCPM0 + , MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0, MEP_INSN_LMCPM0 + , MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1, MEP_INSN_LHCPM1 + , MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1, MEP_INSN_LMCPM1 + , MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT, MEP_INSN_BCPAF + , MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV, MEP_INSN_SIM_SYSCALL + , MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2, MEP_INSN_RI_3 + , MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6, MEP_INSN_RI_7 + , MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10, MEP_INSN_RI_11 + , MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14, MEP_INSN_RI_15 + , MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21, MEP_INSN_RI_22 + , MEP_INSN_RI_23, MEP_INSN_RI_26, MEP_INSN_CMOV_CRN_RM, MEP_INSN_CMOV_RN_CRM + , MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RN_CCRM, MEP_INSN_CMOVH_CRN_RM, MEP_INSN_CMOVH_RN_CRM + , MEP_INSN_CMOV_CRN_RM_P0, MEP_INSN_CMOV_RN_CRM_P0, MEP_INSN_CMOVC_CCRN_RM_P0, MEP_INSN_CMOVC_RN_CCRM_P0 + , MEP_INSN_CMOVH_CRN_RM_P0, MEP_INSN_CMOVH_RN_CRM_P0, MEP_INSN_CPADD3_B_C3, MEP_INSN_CPADD3_H_C3 + , MEP_INSN_CPADD3_W_C3, MEP_INSN_CDADD3_C3, MEP_INSN_CPSUB3_B_C3, MEP_INSN_CPSUB3_H_C3 + , MEP_INSN_CPSUB3_W_C3, MEP_INSN_CDSUB3_C3, MEP_INSN_CPAND3_C3, MEP_INSN_CPOR3_C3 + , MEP_INSN_CPNOR3_C3, MEP_INSN_CPXOR3_C3, MEP_INSN_CPSEL_C3, MEP_INSN_CPFSFTBI_C3 + , MEP_INSN_CPFSFTBS0_C3, MEP_INSN_CPFSFTBS1_C3, MEP_INSN_CPUNPACKU_B_C3, MEP_INSN_CPUNPACKU_H_C3 + , MEP_INSN_CPUNPACKU_W_C3, MEP_INSN_CPUNPACKL_B_C3, MEP_INSN_CPUNPACKL_H_C3, MEP_INSN_CPUNPACKL_W_C3 + , MEP_INSN_CPPACKU_B_C3, MEP_INSN_CPPACK_B_C3, MEP_INSN_CPPACK_H_C3, MEP_INSN_CPSRL3_B_C3 + , MEP_INSN_CPSSRL3_B_C3, MEP_INSN_CPSRL3_H_C3, MEP_INSN_CPSSRL3_H_C3, MEP_INSN_CPSRL3_W_C3 + , MEP_INSN_CPSSRL3_W_C3, MEP_INSN_CDSRL3_C3, MEP_INSN_CPSRA3_B_C3, MEP_INSN_CPSSRA3_B_C3 + , MEP_INSN_CPSRA3_H_C3, MEP_INSN_CPSSRA3_H_C3, MEP_INSN_CPSRA3_W_C3, MEP_INSN_CPSSRA3_W_C3 + , MEP_INSN_CDSRA3_C3, MEP_INSN_CPSLL3_B_C3, MEP_INSN_CPSSLL3_B_C3, MEP_INSN_CPSLL3_H_C3 + , MEP_INSN_CPSSLL3_H_C3, MEP_INSN_CPSLL3_W_C3, MEP_INSN_CPSSLL3_W_C3, MEP_INSN_CDSLL3_C3 + , MEP_INSN_CPSLA3_H_C3, MEP_INSN_CPSLA3_W_C3, MEP_INSN_CPSADD3_H_C3, MEP_INSN_CPSADD3_W_C3 + , MEP_INSN_CPSSUB3_H_C3, MEP_INSN_CPSSUB3_W_C3, MEP_INSN_CPEXTUADDU3_B_C3, MEP_INSN_CPEXTUADD3_B_C3 + , MEP_INSN_CPEXTLADDU3_B_C3, MEP_INSN_CPEXTLADD3_B_C3, MEP_INSN_CPEXTUSUBU3_B_C3, MEP_INSN_CPEXTUSUB3_B_C3 + , MEP_INSN_CPEXTLSUBU3_B_C3, MEP_INSN_CPEXTLSUB3_B_C3, MEP_INSN_CPAVEU3_B_C3, MEP_INSN_CPAVE3_B_C3 + , MEP_INSN_CPAVE3_H_C3, MEP_INSN_CPAVE3_W_C3, MEP_INSN_CPADDSRU3_B_C3, MEP_INSN_CPADDSR3_B_C3 + , MEP_INSN_CPADDSR3_H_C3, MEP_INSN_CPADDSR3_W_C3, MEP_INSN_CPABSU3_B_C3, MEP_INSN_CPABS3_B_C3 + , MEP_INSN_CPABS3_H_C3, MEP_INSN_CPMAXU3_B_C3, MEP_INSN_CPMAX3_B_C3, MEP_INSN_CPMAX3_H_C3 + , MEP_INSN_CPMAXU3_W_C3, MEP_INSN_CPMAX3_W_C3, MEP_INSN_CPMINU3_B_C3, MEP_INSN_CPMIN3_B_C3 + , MEP_INSN_CPMIN3_H_C3, MEP_INSN_CPMINU3_W_C3, MEP_INSN_CPMIN3_W_C3, MEP_INSN_CPMOVFRCSAR0_C3 + , MEP_INSN_CPMOVFRCSAR1_C3, MEP_INSN_CPMOVFRCC_C3, MEP_INSN_CPMOVTOCSAR0_C3, MEP_INSN_CPMOVTOCSAR1_C3 + , MEP_INSN_CPMOVTOCC_C3, MEP_INSN_CPMOV_C3, MEP_INSN_CPABSZ_B_C3, MEP_INSN_CPABSZ_H_C3 + , MEP_INSN_CPABSZ_W_C3, MEP_INSN_CPLDZ_H_C3, MEP_INSN_CPLDZ_W_C3, MEP_INSN_CPNORM_H_C3 + , MEP_INSN_CPNORM_W_C3, MEP_INSN_CPHADDU_B_C3, MEP_INSN_CPHADD_B_C3, MEP_INSN_CPHADD_H_C3 + , MEP_INSN_CPHADD_W_C3, MEP_INSN_CPCCADD_B_C3, MEP_INSN_CPBCAST_B_C3, MEP_INSN_CPBCAST_H_C3 + , MEP_INSN_CPBCAST_W_C3, MEP_INSN_CPEXTUU_B_C3, MEP_INSN_CPEXTU_B_C3, MEP_INSN_CPEXTUU_H_C3 + , MEP_INSN_CPEXTU_H_C3, MEP_INSN_CPEXTLU_B_C3, MEP_INSN_CPEXTL_B_C3, MEP_INSN_CPEXTLU_H_C3 + , MEP_INSN_CPEXTL_H_C3, MEP_INSN_CPCASTUB_H_C3, MEP_INSN_CPCASTB_H_C3, MEP_INSN_CPCASTUB_W_C3 + , MEP_INSN_CPCASTB_W_C3, MEP_INSN_CPCASTUH_W_C3, MEP_INSN_CPCASTH_W_C3, MEP_INSN_CDCASTUW_C3 + , MEP_INSN_CDCASTW_C3, MEP_INSN_CPCMPEQZ_B_C3, MEP_INSN_CPCMPEQ_B_C3, MEP_INSN_CPCMPEQ_H_C3 + , MEP_INSN_CPCMPEQ_W_C3, MEP_INSN_CPCMPNE_B_C3, MEP_INSN_CPCMPNE_H_C3, MEP_INSN_CPCMPNE_W_C3 + , MEP_INSN_CPCMPGTU_B_C3, MEP_INSN_CPCMPGT_B_C3, MEP_INSN_CPCMPGT_H_C3, MEP_INSN_CPCMPGTU_W_C3 + , MEP_INSN_CPCMPGT_W_C3, MEP_INSN_CPCMPGEU_B_C3, MEP_INSN_CPCMPGE_B_C3, MEP_INSN_CPCMPGE_H_C3 + , MEP_INSN_CPCMPGEU_W_C3, MEP_INSN_CPCMPGE_W_C3, MEP_INSN_CPACMPEQ_B_C3, MEP_INSN_CPACMPEQ_H_C3 + , MEP_INSN_CPACMPEQ_W_C3, MEP_INSN_CPACMPNE_B_C3, MEP_INSN_CPACMPNE_H_C3, MEP_INSN_CPACMPNE_W_C3 + , MEP_INSN_CPACMPGTU_B_C3, MEP_INSN_CPACMPGT_B_C3, MEP_INSN_CPACMPGT_H_C3, MEP_INSN_CPACMPGTU_W_C3 + , MEP_INSN_CPACMPGT_W_C3, MEP_INSN_CPACMPGEU_B_C3, MEP_INSN_CPACMPGE_B_C3, MEP_INSN_CPACMPGE_H_C3 + , MEP_INSN_CPACMPGEU_W_C3, MEP_INSN_CPACMPGE_W_C3, MEP_INSN_CPOCMPEQ_B_C3, MEP_INSN_CPOCMPEQ_H_C3 + , MEP_INSN_CPOCMPEQ_W_C3, MEP_INSN_CPOCMPNE_B_C3, MEP_INSN_CPOCMPNE_H_C3, MEP_INSN_CPOCMPNE_W_C3 + , MEP_INSN_CPOCMPGTU_B_C3, MEP_INSN_CPOCMPGT_B_C3, MEP_INSN_CPOCMPGT_H_C3, MEP_INSN_CPOCMPGTU_W_C3 + , MEP_INSN_CPOCMPGT_W_C3, MEP_INSN_CPOCMPGEU_B_C3, MEP_INSN_CPOCMPGE_B_C3, MEP_INSN_CPOCMPGE_H_C3 + , MEP_INSN_CPOCMPGEU_W_C3, MEP_INSN_CPOCMPGE_W_C3, MEP_INSN_CPSRLI3_B_C3, MEP_INSN_CPSRLI3_H_C3 + , MEP_INSN_CPSRLI3_W_C3, MEP_INSN_CDSRLI3_C3, MEP_INSN_CPSRAI3_B_C3, MEP_INSN_CPSRAI3_H_C3 + , MEP_INSN_CPSRAI3_W_C3, MEP_INSN_CDSRAI3_C3, MEP_INSN_CPSLLI3_B_C3, MEP_INSN_CPSLLI3_H_C3 + , MEP_INSN_CPSLLI3_W_C3, MEP_INSN_CDSLLI3_C3, MEP_INSN_CPSLAI3_H_C3, MEP_INSN_CPSLAI3_W_C3 + , MEP_INSN_CPCLIPIU3_W_C3, MEP_INSN_CPCLIPI3_W_C3, MEP_INSN_CDCLIPIU3_C3, MEP_INSN_CDCLIPI3_C3 + , MEP_INSN_CPMOVI_B_C3, MEP_INSN_CPMOVIU_H_C3, MEP_INSN_CPMOVI_H_C3, MEP_INSN_CPMOVIU_W_C3 + , MEP_INSN_CPMOVI_W_C3, MEP_INSN_CDMOVIU_C3, MEP_INSN_CDMOVI_C3, MEP_INSN_CPADDA1U_B_C3 + , MEP_INSN_CPADDA1_B_C3, MEP_INSN_CPADDUA1_H_C3, MEP_INSN_CPADDLA1_H_C3, MEP_INSN_CPADDACA1U_B_C3 + , MEP_INSN_CPADDACA1_B_C3, MEP_INSN_CPADDACUA1_H_C3, MEP_INSN_CPADDACLA1_H_C3, MEP_INSN_CPSUBA1U_B_C3 + , MEP_INSN_CPSUBA1_B_C3, MEP_INSN_CPSUBUA1_H_C3, MEP_INSN_CPSUBLA1_H_C3, MEP_INSN_CPSUBACA1U_B_C3 + , MEP_INSN_CPSUBACA1_B_C3, MEP_INSN_CPSUBACUA1_H_C3, MEP_INSN_CPSUBACLA1_H_C3, MEP_INSN_CPABSA1U_B_C3 + , MEP_INSN_CPABSA1_B_C3, MEP_INSN_CPABSUA1_H_C3, MEP_INSN_CPABSLA1_H_C3, MEP_INSN_CPSADA1U_B_C3 + , MEP_INSN_CPSADA1_B_C3, MEP_INSN_CPSADUA1_H_C3, MEP_INSN_CPSADLA1_H_C3, MEP_INSN_CPSETA1_H_C3 + , MEP_INSN_CPSETUA1_W_C3, MEP_INSN_CPSETLA1_W_C3, MEP_INSN_CPMOVA1_B_C3, MEP_INSN_CPMOVUA1_H_C3 + , MEP_INSN_CPMOVLA1_H_C3, MEP_INSN_CPMOVUUA1_W_C3, MEP_INSN_CPMOVULA1_W_C3, MEP_INSN_CPMOVLUA1_W_C3 + , MEP_INSN_CPMOVLLA1_W_C3, MEP_INSN_CPPACKA1U_B_C3, MEP_INSN_CPPACKA1_B_C3, MEP_INSN_CPPACKUA1_H_C3 + , MEP_INSN_CPPACKLA1_H_C3, MEP_INSN_CPPACKUA1_W_C3, MEP_INSN_CPPACKLA1_W_C3, MEP_INSN_CPMOVHUA1_W_C3 + , MEP_INSN_CPMOVHLA1_W_C3, MEP_INSN_CPSRLA1_C3, MEP_INSN_CPSRAA1_C3, MEP_INSN_CPSLLA1_C3 + , MEP_INSN_CPSRLIA1_P1, MEP_INSN_CPSRAIA1_P1, MEP_INSN_CPSLLIA1_P1, MEP_INSN_CPSSQA1U_B_C3 + , MEP_INSN_CPSSQA1_B_C3, MEP_INSN_CPSSDA1U_B_C3, MEP_INSN_CPSSDA1_B_C3, MEP_INSN_CPMULA1U_B_C3 + , MEP_INSN_CPMULA1_B_C3, MEP_INSN_CPMULUA1_H_C3, MEP_INSN_CPMULLA1_H_C3, MEP_INSN_CPMULUA1U_W_C3 + , MEP_INSN_CPMULLA1U_W_C3, MEP_INSN_CPMULUA1_W_C3, MEP_INSN_CPMULLA1_W_C3, MEP_INSN_CPMADA1U_B_C3 + , MEP_INSN_CPMADA1_B_C3, MEP_INSN_CPMADUA1_H_C3, MEP_INSN_CPMADLA1_H_C3, MEP_INSN_CPMADUA1U_W_C3 + , MEP_INSN_CPMADLA1U_W_C3, MEP_INSN_CPMADUA1_W_C3, MEP_INSN_CPMADLA1_W_C3, MEP_INSN_CPMSBUA1_H_C3 + , MEP_INSN_CPMSBLA1_H_C3, MEP_INSN_CPMSBUA1U_W_C3, MEP_INSN_CPMSBLA1U_W_C3, MEP_INSN_CPMSBUA1_W_C3 + , MEP_INSN_CPMSBLA1_W_C3, MEP_INSN_CPSMADUA1_H_C3, MEP_INSN_CPSMADLA1_H_C3, MEP_INSN_CPSMADUA1_W_C3 + , MEP_INSN_CPSMADLA1_W_C3, MEP_INSN_CPSMSBUA1_H_C3, MEP_INSN_CPSMSBLA1_H_C3, MEP_INSN_CPSMSBUA1_W_C3 + , MEP_INSN_CPSMSBLA1_W_C3, MEP_INSN_CPMULSLUA1_H_C3, MEP_INSN_CPMULSLLA1_H_C3, MEP_INSN_CPMULSLUA1_W_C3 + , MEP_INSN_CPMULSLLA1_W_C3, MEP_INSN_CPSMADSLUA1_H_C3, MEP_INSN_CPSMADSLLA1_H_C3, MEP_INSN_CPSMADSLUA1_W_C3 + , MEP_INSN_CPSMADSLLA1_W_C3, MEP_INSN_CPSMSBSLUA1_H_C3, MEP_INSN_CPSMSBSLLA1_H_C3, MEP_INSN_CPSMSBSLUA1_W_C3 + , MEP_INSN_CPSMSBSLLA1_W_C3, MEP_INSN_C0NOP_P0_P0S, MEP_INSN_CPADD3_B_P0S_P1, MEP_INSN_CPADD3_H_P0S_P1 + , MEP_INSN_CPADD3_W_P0S_P1, MEP_INSN_CPUNPACKU_B_P0S_P1, MEP_INSN_CPUNPACKU_H_P0S_P1, MEP_INSN_CPUNPACKU_W_P0S_P1 + , MEP_INSN_CPUNPACKL_B_P0S_P1, MEP_INSN_CPUNPACKL_H_P0S_P1, MEP_INSN_CPUNPACKL_W_P0S_P1, MEP_INSN_CPSEL_P0S_P1 + , MEP_INSN_CPFSFTBS0_P0S_P1, MEP_INSN_CPFSFTBS1_P0S_P1, MEP_INSN_CPMOV_P0S_P1, MEP_INSN_CPABSZ_B_P0S_P1 + , MEP_INSN_CPABSZ_H_P0S_P1, MEP_INSN_CPABSZ_W_P0S_P1, MEP_INSN_CPLDZ_H_P0S_P1, MEP_INSN_CPLDZ_W_P0S_P1 + , MEP_INSN_CPNORM_H_P0S_P1, MEP_INSN_CPNORM_W_P0S_P1, MEP_INSN_CPHADDU_B_P0S_P1, MEP_INSN_CPHADD_B_P0S_P1 + , MEP_INSN_CPHADD_H_P0S_P1, MEP_INSN_CPHADD_W_P0S_P1, MEP_INSN_CPCCADD_B_P0S_P1, MEP_INSN_CPBCAST_B_P0S_P1 + , MEP_INSN_CPBCAST_H_P0S_P1, MEP_INSN_CPBCAST_W_P0S_P1, MEP_INSN_CPEXTUU_B_P0S_P1, MEP_INSN_CPEXTU_B_P0S_P1 + , MEP_INSN_CPEXTUU_H_P0S_P1, MEP_INSN_CPEXTU_H_P0S_P1, MEP_INSN_CPEXTLU_B_P0S_P1, MEP_INSN_CPEXTL_B_P0S_P1 + , MEP_INSN_CPEXTLU_H_P0S_P1, MEP_INSN_CPEXTL_H_P0S_P1, MEP_INSN_CPCASTUB_H_P0S_P1, MEP_INSN_CPCASTB_H_P0S_P1 + , MEP_INSN_CPCASTUB_W_P0S_P1, MEP_INSN_CPCASTB_W_P0S_P1, MEP_INSN_CPCASTUH_W_P0S_P1, MEP_INSN_CPCASTH_W_P0S_P1 + , MEP_INSN_CDCASTUW_P0S_P1, MEP_INSN_CDCASTW_P0S_P1, MEP_INSN_CPMOVFRCSAR0_P0S_P1, MEP_INSN_CPMOVFRCSAR1_P0S_P1 + , MEP_INSN_CPMOVFRCC_P0S_P1, MEP_INSN_CPMOVTOCSAR0_P0S_P1, MEP_INSN_CPMOVTOCSAR1_P0S_P1, MEP_INSN_CPMOVTOCC_P0S_P1 + , MEP_INSN_CPCMPEQZ_B_P0S_P1, MEP_INSN_CPCMPEQ_B_P0S_P1, MEP_INSN_CPCMPEQ_H_P0S_P1, MEP_INSN_CPCMPEQ_W_P0S_P1 + , MEP_INSN_CPCMPNE_B_P0S_P1, MEP_INSN_CPCMPNE_H_P0S_P1, MEP_INSN_CPCMPNE_W_P0S_P1, MEP_INSN_CPCMPGTU_B_P0S_P1 + , MEP_INSN_CPCMPGT_B_P0S_P1, MEP_INSN_CPCMPGT_H_P0S_P1, MEP_INSN_CPCMPGTU_W_P0S_P1, MEP_INSN_CPCMPGT_W_P0S_P1 + , MEP_INSN_CPCMPGEU_B_P0S_P1, MEP_INSN_CPCMPGE_B_P0S_P1, MEP_INSN_CPCMPGE_H_P0S_P1, MEP_INSN_CPCMPGEU_W_P0S_P1 + , MEP_INSN_CPCMPGE_W_P0S_P1, MEP_INSN_CPADDA0U_B_P0S, MEP_INSN_CPADDA0_B_P0S, MEP_INSN_CPADDUA0_H_P0S + , MEP_INSN_CPADDLA0_H_P0S, MEP_INSN_CPADDACA0U_B_P0S, MEP_INSN_CPADDACA0_B_P0S, MEP_INSN_CPADDACUA0_H_P0S + , MEP_INSN_CPADDACLA0_H_P0S, MEP_INSN_CPSUBA0U_B_P0S, MEP_INSN_CPSUBA0_B_P0S, MEP_INSN_CPSUBUA0_H_P0S + , MEP_INSN_CPSUBLA0_H_P0S, MEP_INSN_CPSUBACA0U_B_P0S, MEP_INSN_CPSUBACA0_B_P0S, MEP_INSN_CPSUBACUA0_H_P0S + , MEP_INSN_CPSUBACLA0_H_P0S, MEP_INSN_CPABSA0U_B_P0S, MEP_INSN_CPABSA0_B_P0S, MEP_INSN_CPABSUA0_H_P0S + , MEP_INSN_CPABSLA0_H_P0S, MEP_INSN_CPSADA0U_B_P0S, MEP_INSN_CPSADA0_B_P0S, MEP_INSN_CPSADUA0_H_P0S + , MEP_INSN_CPSADLA0_H_P0S, MEP_INSN_CPSETA0_H_P0S, MEP_INSN_CPSETUA0_W_P0S, MEP_INSN_CPSETLA0_W_P0S + , MEP_INSN_CPMOVA0_B_P0S, MEP_INSN_CPMOVUA0_H_P0S, MEP_INSN_CPMOVLA0_H_P0S, MEP_INSN_CPMOVUUA0_W_P0S + , MEP_INSN_CPMOVULA0_W_P0S, MEP_INSN_CPMOVLUA0_W_P0S, MEP_INSN_CPMOVLLA0_W_P0S, MEP_INSN_CPPACKA0U_B_P0S + , MEP_INSN_CPPACKA0_B_P0S, MEP_INSN_CPPACKUA0_H_P0S, MEP_INSN_CPPACKLA0_H_P0S, MEP_INSN_CPPACKUA0_W_P0S + , MEP_INSN_CPPACKLA0_W_P0S, MEP_INSN_CPMOVHUA0_W_P0S, MEP_INSN_CPMOVHLA0_W_P0S, MEP_INSN_CPACSUMA0_P0S + , MEP_INSN_CPACCPA0_P0S, MEP_INSN_CPSRLA0_P0S, MEP_INSN_CPSRAA0_P0S, MEP_INSN_CPSLLA0_P0S + , MEP_INSN_CPSRLIA0_P0S, MEP_INSN_CPSRAIA0_P0S, MEP_INSN_CPSLLIA0_P0S, MEP_INSN_CPFSFTBA0S0U_B_P0S + , MEP_INSN_CPFSFTBA0S0_B_P0S, MEP_INSN_CPFSFTBUA0S0_H_P0S, MEP_INSN_CPFSFTBLA0S0_H_P0S, MEP_INSN_CPFACA0S0U_B_P0S + , MEP_INSN_CPFACA0S0_B_P0S, MEP_INSN_CPFACUA0S0_H_P0S, MEP_INSN_CPFACLA0S0_H_P0S, MEP_INSN_CPFSFTBA0S1U_B_P0S + , MEP_INSN_CPFSFTBA0S1_B_P0S, MEP_INSN_CPFSFTBUA0S1_H_P0S, MEP_INSN_CPFSFTBLA0S1_H_P0S, MEP_INSN_CPFACA0S1U_B_P0S + , MEP_INSN_CPFACA0S1_B_P0S, MEP_INSN_CPFACUA0S1_H_P0S, MEP_INSN_CPFACLA0S1_H_P0S, MEP_INSN_CPFSFTBI_P0_P1 + , MEP_INSN_CPACMPEQ_B_P0_P1, MEP_INSN_CPACMPEQ_H_P0_P1, MEP_INSN_CPACMPEQ_W_P0_P1, MEP_INSN_CPACMPNE_B_P0_P1 + , MEP_INSN_CPACMPNE_H_P0_P1, MEP_INSN_CPACMPNE_W_P0_P1, MEP_INSN_CPACMPGTU_B_P0_P1, MEP_INSN_CPACMPGT_B_P0_P1 + , MEP_INSN_CPACMPGT_H_P0_P1, MEP_INSN_CPACMPGTU_W_P0_P1, MEP_INSN_CPACMPGT_W_P0_P1, MEP_INSN_CPACMPGEU_B_P0_P1 + , MEP_INSN_CPACMPGE_B_P0_P1, MEP_INSN_CPACMPGE_H_P0_P1, MEP_INSN_CPACMPGEU_W_P0_P1, MEP_INSN_CPACMPGE_W_P0_P1 + , MEP_INSN_CPOCMPEQ_B_P0_P1, MEP_INSN_CPOCMPEQ_H_P0_P1, MEP_INSN_CPOCMPEQ_W_P0_P1, MEP_INSN_CPOCMPNE_B_P0_P1 + , MEP_INSN_CPOCMPNE_H_P0_P1, MEP_INSN_CPOCMPNE_W_P0_P1, MEP_INSN_CPOCMPGTU_B_P0_P1, MEP_INSN_CPOCMPGT_B_P0_P1 + , MEP_INSN_CPOCMPGT_H_P0_P1, MEP_INSN_CPOCMPGTU_W_P0_P1, MEP_INSN_CPOCMPGT_W_P0_P1, MEP_INSN_CPOCMPGEU_B_P0_P1 + , MEP_INSN_CPOCMPGE_B_P0_P1, MEP_INSN_CPOCMPGE_H_P0_P1, MEP_INSN_CPOCMPGEU_W_P0_P1, MEP_INSN_CPOCMPGE_W_P0_P1 + , MEP_INSN_CDADD3_P0_P1, MEP_INSN_CPSUB3_B_P0_P1, MEP_INSN_CPSUB3_H_P0_P1, MEP_INSN_CPSUB3_W_P0_P1 + , MEP_INSN_CDSUB3_P0_P1, MEP_INSN_CPSADD3_H_P0_P1, MEP_INSN_CPSADD3_W_P0_P1, MEP_INSN_CPSSUB3_H_P0_P1 + , MEP_INSN_CPSSUB3_W_P0_P1, MEP_INSN_CPEXTUADDU3_B_P0_P1, MEP_INSN_CPEXTUADD3_B_P0_P1, MEP_INSN_CPEXTLADDU3_B_P0_P1 + , MEP_INSN_CPEXTLADD3_B_P0_P1, MEP_INSN_CPEXTUSUBU3_B_P0_P1, MEP_INSN_CPEXTUSUB3_B_P0_P1, MEP_INSN_CPEXTLSUBU3_B_P0_P1 + , MEP_INSN_CPEXTLSUB3_B_P0_P1, MEP_INSN_CPAVEU3_B_P0_P1, MEP_INSN_CPAVE3_B_P0_P1, MEP_INSN_CPAVE3_H_P0_P1 + , MEP_INSN_CPAVE3_W_P0_P1, MEP_INSN_CPADDSRU3_B_P0_P1, MEP_INSN_CPADDSR3_B_P0_P1, MEP_INSN_CPADDSR3_H_P0_P1 + , MEP_INSN_CPADDSR3_W_P0_P1, MEP_INSN_CPABSU3_B_P0_P1, MEP_INSN_CPABS3_B_P0_P1, MEP_INSN_CPABS3_H_P0_P1 + , MEP_INSN_CPAND3_P0_P1, MEP_INSN_CPOR3_P0_P1, MEP_INSN_CPNOR3_P0_P1, MEP_INSN_CPXOR3_P0_P1 + , MEP_INSN_CPPACKU_B_P0_P1, MEP_INSN_CPPACK_B_P0_P1, MEP_INSN_CPPACK_H_P0_P1, MEP_INSN_CPMAXU3_B_P0_P1 + , MEP_INSN_CPMAX3_B_P0_P1, MEP_INSN_CPMAX3_H_P0_P1, MEP_INSN_CPMAXU3_W_P0_P1, MEP_INSN_CPMAX3_W_P0_P1 + , MEP_INSN_CPMINU3_B_P0_P1, MEP_INSN_CPMIN3_B_P0_P1, MEP_INSN_CPMIN3_H_P0_P1, MEP_INSN_CPMINU3_W_P0_P1 + , MEP_INSN_CPMIN3_W_P0_P1, MEP_INSN_CPSRL3_B_P0_P1, MEP_INSN_CPSSRL3_B_P0_P1, MEP_INSN_CPSRL3_H_P0_P1 + , MEP_INSN_CPSSRL3_H_P0_P1, MEP_INSN_CPSRL3_W_P0_P1, MEP_INSN_CPSSRL3_W_P0_P1, MEP_INSN_CDSRL3_P0_P1 + , MEP_INSN_CPSRA3_B_P0_P1, MEP_INSN_CPSSRA3_B_P0_P1, MEP_INSN_CPSRA3_H_P0_P1, MEP_INSN_CPSSRA3_H_P0_P1 + , MEP_INSN_CPSRA3_W_P0_P1, MEP_INSN_CPSSRA3_W_P0_P1, MEP_INSN_CDSRA3_P0_P1, MEP_INSN_CPSLL3_B_P0_P1 + , MEP_INSN_CPSSLL3_B_P0_P1, MEP_INSN_CPSLL3_H_P0_P1, MEP_INSN_CPSSLL3_H_P0_P1, MEP_INSN_CPSLL3_W_P0_P1 + , MEP_INSN_CPSSLL3_W_P0_P1, MEP_INSN_CDSLL3_P0_P1, MEP_INSN_CPSLA3_H_P0_P1, MEP_INSN_CPSLA3_W_P0_P1 + , MEP_INSN_CPSRLI3_B_P0_P1, MEP_INSN_CPSRLI3_H_P0_P1, MEP_INSN_CPSRLI3_W_P0_P1, MEP_INSN_CDSRLI3_P0_P1 + , MEP_INSN_CPSRAI3_B_P0_P1, MEP_INSN_CPSRAI3_H_P0_P1, MEP_INSN_CPSRAI3_W_P0_P1, MEP_INSN_CDSRAI3_P0_P1 + , MEP_INSN_CPSLLI3_B_P0_P1, MEP_INSN_CPSLLI3_H_P0_P1, MEP_INSN_CPSLLI3_W_P0_P1, MEP_INSN_CDSLLI3_P0_P1 + , MEP_INSN_CPSLAI3_H_P0_P1, MEP_INSN_CPSLAI3_W_P0_P1, MEP_INSN_CPCLIPIU3_W_P0_P1, MEP_INSN_CPCLIPI3_W_P0_P1 + , MEP_INSN_CDCLIPIU3_P0_P1, MEP_INSN_CDCLIPI3_P0_P1, MEP_INSN_CPMOVI_H_P0_P1, MEP_INSN_CPMOVIU_W_P0_P1 + , MEP_INSN_CPMOVI_W_P0_P1, MEP_INSN_CDMOVIU_P0_P1, MEP_INSN_CDMOVI_P0_P1, MEP_INSN_C1NOP_P1 + , MEP_INSN_CPMOVI_B_P0S_P1, MEP_INSN_CPADDA1U_B_P1, MEP_INSN_CPADDA1_B_P1, MEP_INSN_CPADDUA1_H_P1 + , MEP_INSN_CPADDLA1_H_P1, MEP_INSN_CPADDACA1U_B_P1, MEP_INSN_CPADDACA1_B_P1, MEP_INSN_CPADDACUA1_H_P1 + , MEP_INSN_CPADDACLA1_H_P1, MEP_INSN_CPSUBA1U_B_P1, MEP_INSN_CPSUBA1_B_P1, MEP_INSN_CPSUBUA1_H_P1 + , MEP_INSN_CPSUBLA1_H_P1, MEP_INSN_CPSUBACA1U_B_P1, MEP_INSN_CPSUBACA1_B_P1, MEP_INSN_CPSUBACUA1_H_P1 + , MEP_INSN_CPSUBACLA1_H_P1, MEP_INSN_CPABSA1U_B_P1, MEP_INSN_CPABSA1_B_P1, MEP_INSN_CPABSUA1_H_P1 + , MEP_INSN_CPABSLA1_H_P1, MEP_INSN_CPSADA1U_B_P1, MEP_INSN_CPSADA1_B_P1, MEP_INSN_CPSADUA1_H_P1 + , MEP_INSN_CPSADLA1_H_P1, MEP_INSN_CPSETA1_H_P1, MEP_INSN_CPSETUA1_W_P1, MEP_INSN_CPSETLA1_W_P1 + , MEP_INSN_CPMOVA1_B_P1, MEP_INSN_CPMOVUA1_H_P1, MEP_INSN_CPMOVLA1_H_P1, MEP_INSN_CPMOVUUA1_W_P1 + , MEP_INSN_CPMOVULA1_W_P1, MEP_INSN_CPMOVLUA1_W_P1, MEP_INSN_CPMOVLLA1_W_P1, MEP_INSN_CPPACKA1U_B_P1 + , MEP_INSN_CPPACKA1_B_P1, MEP_INSN_CPPACKUA1_H_P1, MEP_INSN_CPPACKLA1_H_P1, MEP_INSN_CPPACKUA1_W_P1 + , MEP_INSN_CPPACKLA1_W_P1, MEP_INSN_CPMOVHUA1_W_P1, MEP_INSN_CPMOVHLA1_W_P1, MEP_INSN_CPACSUMA1_P1 + , MEP_INSN_CPACCPA1_P1, MEP_INSN_CPACSWP_P1, MEP_INSN_CPSRLA1_P1, MEP_INSN_CPSRAA1_P1 + , MEP_INSN_CPSLLA1_P1, MEP_INSN_CPSRLIA1_1_P1, MEP_INSN_CPSRAIA1_1_P1, MEP_INSN_CPSLLIA1_1_P1 + , MEP_INSN_CPFMULIA1S0U_B_P1, MEP_INSN_CPFMULIA1S0_B_P1, MEP_INSN_CPFMULIUA1S0_H_P1, MEP_INSN_CPFMULILA1S0_H_P1 + , MEP_INSN_CPFMADIA1S0U_B_P1, MEP_INSN_CPFMADIA1S0_B_P1, MEP_INSN_CPFMADIUA1S0_H_P1, MEP_INSN_CPFMADILA1S0_H_P1 + , MEP_INSN_CPFMULIA1S1U_B_P1, MEP_INSN_CPFMULIA1S1_B_P1, MEP_INSN_CPFMULIUA1S1_H_P1, MEP_INSN_CPFMULILA1S1_H_P1 + , MEP_INSN_CPFMADIA1S1U_B_P1, MEP_INSN_CPFMADIA1S1_B_P1, MEP_INSN_CPFMADIUA1S1_H_P1, MEP_INSN_CPFMADILA1S1_H_P1 + , MEP_INSN_CPAMULIA1U_B_P1, MEP_INSN_CPAMULIA1_B_P1, MEP_INSN_CPAMULIUA1_H_P1, MEP_INSN_CPAMULILA1_H_P1 + , MEP_INSN_CPAMADIA1U_B_P1, MEP_INSN_CPAMADIA1_B_P1, MEP_INSN_CPAMADIUA1_H_P1, MEP_INSN_CPAMADILA1_H_P1 + , MEP_INSN_CPFMULIA1U_B_P1, MEP_INSN_CPFMULIA1_B_P1, MEP_INSN_CPFMULIUA1_H_P1, MEP_INSN_CPFMULILA1_H_P1 + , MEP_INSN_CPFMADIA1U_B_P1, MEP_INSN_CPFMADIA1_B_P1, MEP_INSN_CPFMADIUA1_H_P1, MEP_INSN_CPFMADILA1_H_P1 + , MEP_INSN_CPSSQA1U_B_P1, MEP_INSN_CPSSQA1_B_P1, MEP_INSN_CPSSDA1U_B_P1, MEP_INSN_CPSSDA1_B_P1 + , MEP_INSN_CPMULA1U_B_P1, MEP_INSN_CPMULA1_B_P1, MEP_INSN_CPMULUA1_H_P1, MEP_INSN_CPMULLA1_H_P1 + , MEP_INSN_CPMULUA1U_W_P1, MEP_INSN_CPMULLA1U_W_P1, MEP_INSN_CPMULUA1_W_P1, MEP_INSN_CPMULLA1_W_P1 + , MEP_INSN_CPMADA1U_B_P1, MEP_INSN_CPMADA1_B_P1, MEP_INSN_CPMADUA1_H_P1, MEP_INSN_CPMADLA1_H_P1 + , MEP_INSN_CPMADUA1U_W_P1, MEP_INSN_CPMADLA1U_W_P1, MEP_INSN_CPMADUA1_W_P1, MEP_INSN_CPMADLA1_W_P1 + , MEP_INSN_CPMSBUA1_H_P1, MEP_INSN_CPMSBLA1_H_P1, MEP_INSN_CPMSBUA1U_W_P1, MEP_INSN_CPMSBLA1U_W_P1 + , MEP_INSN_CPMSBUA1_W_P1, MEP_INSN_CPMSBLA1_W_P1, MEP_INSN_CPSMADUA1_H_P1, MEP_INSN_CPSMADLA1_H_P1 + , MEP_INSN_CPSMADUA1_W_P1, MEP_INSN_CPSMADLA1_W_P1, MEP_INSN_CPSMSBUA1_H_P1, MEP_INSN_CPSMSBLA1_H_P1 + , MEP_INSN_CPSMSBUA1_W_P1, MEP_INSN_CPSMSBLA1_W_P1, MEP_INSN_CPMULSLUA1_H_P1, MEP_INSN_CPMULSLLA1_H_P1 + , MEP_INSN_CPMULSLUA1_W_P1, MEP_INSN_CPMULSLLA1_W_P1, MEP_INSN_CPSMADSLUA1_H_P1, MEP_INSN_CPSMADSLLA1_H_P1 + , MEP_INSN_CPSMADSLUA1_W_P1, MEP_INSN_CPSMADSLLA1_W_P1, MEP_INSN_CPSMSBSLUA1_H_P1, MEP_INSN_CPSMSBSLLA1_H_P1 + , MEP_INSN_CPSMSBSLUA1_W_P1, MEP_INSN_CPSMSBSLLA1_W_P1 +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID MEP_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) MEP_INSN_CPSMSBSLLA1_W_P1 + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_major; + long f_rn; + long f_rn3; + long f_rm; + long f_rl; + long f_sub2; + long f_sub3; + long f_sub4; + long f_ext; + long f_ext4; + long f_ext62; + long f_crn; + long f_csrn_hi; + long f_csrn_lo; + long f_csrn; + long f_crnx_hi; + long f_crnx_lo; + long f_crnx; + long f_0; + long f_1; + long f_2; + long f_3; + long f_4; + long f_5; + long f_6; + long f_7; + long f_8; + long f_9; + long f_10; + long f_11; + long f_12; + long f_13; + long f_14; + long f_15; + long f_16; + long f_17; + long f_18; + long f_19; + long f_20; + long f_21; + long f_22; + long f_23; + long f_24; + long f_25; + long f_26; + long f_27; + long f_28; + long f_29; + long f_30; + long f_31; + long f_8s8a2; + long f_12s4a2; + long f_17s16a2; + long f_24s5a2n_hi; + long f_24s5a2n_lo; + long f_24s5a2n; + long f_24u5a2n_hi; + long f_24u5a2n_lo; + long f_24u5a2n; + long f_2u6; + long f_7u9; + long f_7u9a2; + long f_7u9a4; + long f_16s16; + long f_2u10; + long f_3u5; + long f_4u8; + long f_5u8; + long f_5u24; + long f_6s8; + long f_8s8; + long f_16u16; + long f_12u16; + long f_3u29; + long f_cdisp10; + long f_24u8a4n_hi; + long f_24u8a4n_lo; + long f_24u8a4n; + long f_24u8n_hi; + long f_24u8n_lo; + long f_24u8n; + long f_24u4n_hi; + long f_24u4n_lo; + long f_24u4n; + long f_callnum; + long f_ccrn_hi; + long f_ccrn_lo; + long f_ccrn; + long f_c5n4; + long f_c5n5; + long f_c5n6; + long f_c5n7; + long f_rl5; + long f_12s20; + long f_c5_rnm; + long f_c5_rm; + long f_c5_16u16; + long f_c5_rmuimm20; + long f_c5_rnmuimm24; + long f_ivc2_2u4; + long f_ivc2_3u4; + long f_ivc2_8u4; + long f_ivc2_8s4; + long f_ivc2_1u6; + long f_ivc2_2u6; + long f_ivc2_3u6; + long f_ivc2_6u6; + long f_ivc2_5u7; + long f_ivc2_4u8; + long f_ivc2_3u9; + long f_ivc2_5u16; + long f_ivc2_5u21; + long f_ivc2_5u26; + long f_ivc2_1u31; + long f_ivc2_4u16; + long f_ivc2_4u20; + long f_ivc2_4u24; + long f_ivc2_4u28; + long f_ivc2_2u0; + long f_ivc2_3u0; + long f_ivc2_4u0; + long f_ivc2_5u0; + long f_ivc2_8u0; + long f_ivc2_8s0; + long f_ivc2_6u2; + long f_ivc2_5u3; + long f_ivc2_4u4; + long f_ivc2_3u5; + long f_ivc2_5u8; + long f_ivc2_4u10; + long f_ivc2_3u12; + long f_ivc2_5u13; + long f_ivc2_2u18; + long f_ivc2_5u18; + long f_ivc2_8u20; + long f_ivc2_8s20; + long f_ivc2_5u23; + long f_ivc2_2u23; + long f_ivc2_3u25; + long f_ivc2_imm16p0; + long f_ivc2_simm16p0; + long f_ivc2_ccrn_c3hi; + long f_ivc2_ccrn_c3lo; + long f_ivc2_crn; + long f_ivc2_crm; + long f_ivc2_ccrn_h1; + long f_ivc2_ccrn_h2; + long f_ivc2_ccrn_lo; + long f_ivc2_cmov1; + long f_ivc2_cmov2; + long f_ivc2_cmov3; + long f_ivc2_ccrn_c3; + long f_ivc2_ccrn; + long f_ivc2_crnx; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* MEP_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/microblaze-dis.c b/external/gpl3/gdb/dist/opcodes/microblaze-dis.c new file mode 100644 index 000000000000..1bbeeaddc008 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/microblaze-dis.c @@ -0,0 +1,514 @@ +/* Disassemble Xilinx microblaze instructions. + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "dis-asm.h" +#include +#include "microblaze-opc.h" +#include "microblaze-dis.h" + +#define get_field_rd(instr) get_field (instr, RD_MASK, RD_LOW) +#define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW) +#define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW) +#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) +#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + + + +static char * +get_field (long instr, long mask, unsigned short low) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm5 (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_rfsl (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%s%d", fsl_register_prefix, + (short)((instr & RFSL_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_imm15 (long instr) +{ + char tmpstr[25]; + + sprintf (tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); +} + +static char * +get_field_special (long instr, struct op_code_struct * op) +{ + char tmpstr[25]; + char spr[6]; + + switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask)) + { + case REG_MSR_MASK : + strcpy (spr, "msr"); + break; + case REG_PC_MASK : + strcpy (spr, "pc"); + break; + case REG_EAR_MASK : + strcpy (spr, "ear"); + break; + case REG_ESR_MASK : + strcpy (spr, "esr"); + break; + case REG_FSR_MASK : + strcpy (spr, "fsr"); + break; + case REG_BTR_MASK : + strcpy (spr, "btr"); + break; + case REG_EDR_MASK : + strcpy (spr, "edr"); + break; + case REG_PID_MASK : + strcpy (spr, "pid"); + break; + case REG_ZPR_MASK : + strcpy (spr, "zpr"); + break; + case REG_TLBX_MASK : + strcpy (spr, "tlbx"); + break; + case REG_TLBLO_MASK : + strcpy (spr, "tlblo"); + break; + case REG_TLBHI_MASK : + strcpy (spr, "tlbhi"); + break; + case REG_TLBSX_MASK : + strcpy (spr, "tlbsx"); + break; + default : + if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) + == REG_PVR_MASK) + { + sprintf (tmpstr, "%spvr%d", register_prefix, + (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) + ^ op->immval_mask) ^ REG_PVR_MASK); + return (strdup (tmpstr)); + } + else + strcpy (spr, "pc"); + break; + } + + sprintf (tmpstr, "%s%s", register_prefix, spr); + return (strdup (tmpstr)); +} + +static unsigned long +read_insn_microblaze (bfd_vma memaddr, + struct disassemble_info *info, + struct op_code_struct **opr) +{ + unsigned char ibytes[4]; + int status; + struct op_code_struct * op; + unsigned long inst; + + status = info->read_memory_func (memaddr, ibytes, 4, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return 0; + } + + if (info->endian == BFD_ENDIAN_BIG) + inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3]; + else if (info->endian == BFD_ENDIAN_LITTLE) + inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0]; + else + abort (); + + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + *opr = op; + return inst; +} + + +int +print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) +{ + fprintf_ftype print_func = info->fprintf_func; + void * stream = info->stream; + unsigned long inst, prev_inst; + struct op_code_struct * op, *pop; + int immval = 0; + bfd_boolean immfound = FALSE; + static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */ + static int prev_insn_vma = -1; /* Init the prev insn vma. */ + int curr_insn_vma = info->buffer_vma; + + info->bytes_per_chunk = 4; + + inst = read_insn_microblaze (memaddr, info, &op); + if (inst == 0) + return -1; + + if (prev_insn_vma == curr_insn_vma) + { + if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) + { + prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop); + if (prev_inst == 0) + return -1; + if (pop->instr == imm) + { + immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000; + immfound = TRUE; + } + else + { + immval = 0; + immfound = FALSE; + } + } + } + + /* Make curr insn as prev insn. */ + prev_insn_addr = memaddr; + prev_insn_vma = curr_insn_vma; + + if (op->name == NULL) + print_func (stream, ".short 0x%04x", inst); + else + { + print_func (stream, "%s", op->name); + + switch (op->inst_type) + { + case INST_TYPE_RD_R1_R2: + print_func (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_r2 (inst)); + break; + case INST_TYPE_RD_R1_IMM: + print_func (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_imm (inst)); + if (info->print_address_func && get_int_field_r1 (inst) == 0 + && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + print_func (stream, "\t// "); + info->print_address_func (immval, info); + } + } + break; + case INST_TYPE_RD_R1_IMM5: + print_func (stream, "\t%s, %s, %s", get_field_rd (inst), + get_field_r1(inst), get_field_imm5 (inst)); + break; + case INST_TYPE_RD_RFSL: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst)); + break; + case INST_TYPE_R1_RFSL: + print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst)); + break; + case INST_TYPE_RD_SPECIAL: + print_func (stream, "\t%s, %s", get_field_rd (inst), + get_field_special (inst, op)); + break; + case INST_TYPE_SPECIAL_R1: + print_func (stream, "\t%s, %s", get_field_special (inst, op), + get_field_r1(inst)); + break; + case INST_TYPE_RD_R1: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst)); + break; + case INST_TYPE_R1_R2: + print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst)); + break; + case INST_TYPE_R1_IMM: + print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst)); + /* The non-pc relative instructions are returns, which shouldn't + have a label printed. */ + if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET + && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + immval += memaddr; + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + print_func (stream, "\t// "); + info->print_address_func (immval, info); + } + else + { + print_func (stream, "\t\t// "); + print_func (stream, "%x", immval); + } + } + break; + case INST_TYPE_RD_IMM: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst)); + if (info->print_address_func && info->symbol_at_address_func) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + immval += (int) memaddr; + if (info->symbol_at_address_func (immval, info)) + { + print_func (stream, "\t// "); + info->print_address_func (immval, info); + } + } + break; + case INST_TYPE_IMM: + print_func (stream, "\t%s", get_field_imm (inst)); + if (info->print_address_func && info->symbol_at_address_func + && op->instr != imm) + { + if (immfound) + immval |= (get_int_field_imm (inst) & 0x0000ffff); + else + { + immval = get_int_field_imm (inst); + if (immval & 0x8000) + immval |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + immval += (int) memaddr; + if (immval > 0 && info->symbol_at_address_func (immval, info)) + { + print_func (stream, "\t// "); + info->print_address_func (immval, info); + } + else if (op->inst_offset_type == INST_PC_OFFSET) + { + print_func (stream, "\t\t// "); + print_func (stream, "%x", immval); + } + } + break; + case INST_TYPE_RD_R2: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; + case INST_TYPE_R2: + print_func (stream, "\t%s", get_field_r2 (inst)); + break; + case INST_TYPE_R1: + print_func (stream, "\t%s", get_field_r1 (inst)); + break; + case INST_TYPE_RD_R1_SPECIAL: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; + case INST_TYPE_RD_IMM15: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst)); + break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (inst)); + break; + case INST_TYPE_RFSL: + print_func (stream, "\t%s", get_field_rfsl (inst)); + break; + default: + /* If the disassembler lags the instruction set. */ + print_func (stream, "\tundecoded operands, inst is 0x%04x", inst); + break; + } + } + + /* Say how many bytes we consumed. */ + return 4; +} + +enum microblaze_instr +get_insn_microblaze (long inst, + bfd_boolean *isunsignedimm, + enum microblaze_instr_type *insn_type, + short *delay_slots) +{ + struct op_code_struct * op; + *isunsignedimm = FALSE; + + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + if (op->name == 0) + return invalid_inst; + else + { + *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM); + *insn_type = op->instr_type; + *delay_slots = op->delay_slots; + return op->instr; + } +} + +enum microblaze_instr +microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed) +{ + enum microblaze_instr op; + bfd_boolean t1; + enum microblaze_instr_type t2; + short t3; + + op = get_insn_microblaze (insn, &t1, &t2, &t3); + *rd = (insn & RD_MASK) >> RD_LOW; + *ra = (insn & RA_MASK) >> RA_LOW; + *rb = (insn & RB_MASK) >> RB_LOW; + t3 = (insn & IMM_MASK) >> IMM_LOW; + *immed = (int) t3; + return (op); +} + +unsigned long +microblaze_get_target_address (long inst, bfd_boolean immfound, int immval, + long pcval, long r1val, long r2val, + bfd_boolean *targetvalid, + bfd_boolean *unconditionalbranch) +{ + struct op_code_struct * op; + long targetaddr = 0; + + *unconditionalbranch = FALSE; + /* Just a linear search of the table. */ + for (op = opcodes; op->name != 0; op ++) + if (op->bit_sequence == (inst & op->opcode_mask)) + break; + + if (op->name == 0) + { + *targetvalid = FALSE; + } + else if (op->instr_type == branch_inst) + { + switch (op->inst_type) + { + case INST_TYPE_R2: + *unconditionalbranch = TRUE; + /* Fall through. */ + case INST_TYPE_RD_R2: + case INST_TYPE_R1_R2: + targetaddr = r2val; + *targetvalid = TRUE; + if (op->inst_offset_type == INST_PC_OFFSET) + targetaddr += pcval; + break; + case INST_TYPE_IMM: + *unconditionalbranch = TRUE; + /* Fall through. */ + case INST_TYPE_RD_IMM: + case INST_TYPE_R1_IMM: + if (immfound) + { + targetaddr = (immval << 16) & 0xffff0000; + targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); + } + else + { + targetaddr = get_int_field_imm (inst); + if (targetaddr & 0x8000) + targetaddr |= 0xFFFF0000; + } + if (op->inst_offset_type == INST_PC_OFFSET) + targetaddr += pcval; + *targetvalid = TRUE; + break; + default: + *targetvalid = FALSE; + break; + } + } + else if (op->instr_type == return_inst) + { + if (immfound) + { + targetaddr = (immval << 16) & 0xffff0000; + targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); + } + else + { + targetaddr = get_int_field_imm (inst); + if (targetaddr & 0x8000) + targetaddr |= 0xFFFF0000; + } + targetaddr += r1val; + *targetvalid = TRUE; + } + else + *targetvalid = FALSE; + return targetaddr; +} diff --git a/external/gpl3/gdb/dist/opcodes/microblaze-dis.h b/external/gpl3/gdb/dist/opcodes/microblaze-dis.h new file mode 100644 index 000000000000..4742bbcc0590 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/microblaze-dis.h @@ -0,0 +1,34 @@ +/* Disassemble Xilinx microblaze instructions. + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef MICROBLAZE_DIS_H +#define MICROBLAZE_DIS_H 1 + +extern enum microblaze_instr microblaze_decode_insn (long, int *, int *, + int *, int *); +extern unsigned long microblaze_get_target_address (long, bfd_boolean, int, + long, long, long, bfd_boolean *, bfd_boolean *); + +extern enum microblaze_instr get_insn_microblaze (long, bfd_boolean *, + enum microblaze_instr_type *, + short *); + +#endif /* microblaze-dis.h */ diff --git a/external/gpl3/gdb/dist/opcodes/microblaze-opc.h b/external/gpl3/gdb/dist/opcodes/microblaze-opc.h new file mode 100644 index 000000000000..02ac83f5695e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/microblaze-opc.h @@ -0,0 +1,409 @@ +/* microblaze-opc.h -- MicroBlaze Opcodes + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#ifndef MICROBLAZE_OPC +#define MICROBLAZE_OPC + +#include "microblaze-opcm.h" + + +#define INST_TYPE_RD_R1_R2 0 +#define INST_TYPE_RD_R1_IMM 1 +#define INST_TYPE_RD_R1_UNSIGNED_IMM 2 +#define INST_TYPE_RD_R1 3 +#define INST_TYPE_RD_R2 4 +#define INST_TYPE_RD_IMM 5 +#define INST_TYPE_R2 6 +#define INST_TYPE_R1_R2 7 +#define INST_TYPE_R1_IMM 8 +#define INST_TYPE_IMM 9 +#define INST_TYPE_SPECIAL_R1 10 +#define INST_TYPE_RD_SPECIAL 11 +#define INST_TYPE_R1 12 +/* New instn type for barrel shift imms. */ +#define INST_TYPE_RD_R1_IMM5 13 +#define INST_TYPE_RD_RFSL 14 +#define INST_TYPE_R1_RFSL 15 + +/* New insn type for insn cache. */ +#define INST_TYPE_RD_R1_SPECIAL 16 + +/* New insn type for msrclr, msrset insns. */ +#define INST_TYPE_RD_IMM15 17 + +/* New insn type for tuqula rd - addik rd, r0, 42. */ +#define INST_TYPE_RD 18 + +/* New insn type for t*put. */ +#define INST_TYPE_RFSL 19 + +#define INST_TYPE_NONE 25 + + + +/* Instructions where the label address is resolved as a PC offset + (for branch label). */ +#define INST_PC_OFFSET 1 +/* Instructions where the label address is resolved as an absolute + value (for data mem or abs address). */ +#define INST_NO_OFFSET 0 + +#define IMMVAL_MASK_NON_SPECIAL 0x0000 +#define IMMVAL_MASK_MTS 0x4000 +#define IMMVAL_MASK_MFS 0x0000 + +#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */ +#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */ +#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */ +#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */ +#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */ +#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last + nibble of last byte for spr. */ +#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last + nibble of last byte for spr. */ +#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */ +#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */ +#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ +#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ +#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ +#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ + +/* New Mask for msrset, msrclr insns. */ +#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ + +#define DELAY_SLOT 1 +#define NO_DELAY_SLOT 0 + +#define MAX_OPCODES 280 + +struct op_code_struct +{ + char * name; + short inst_type; /* Registers and immediate values involved. */ + short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */ + short delay_slots; /* Info about delay slots needed after this instr. */ + short immval_mask; + unsigned long bit_sequence; /* All the fixed bits for the op are set and + all the variable bits (reg names, imm vals) + are set to 0. */ + unsigned long opcode_mask; /* Which bits define the opcode. */ + enum microblaze_instr instr; + enum microblaze_instr_type instr_type; + /* More info about output format here. */ +} opcodes[MAX_OPCODES] = +{ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, + {"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst }, + {"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst }, + {"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst }, + {"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst }, + {"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst }, + {"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst }, + {"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst }, + {"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst }, + {"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst }, + {"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst }, + {"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst }, + {"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst }, + {"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst }, + {"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst }, + {"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst }, + {"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst }, + {"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst }, + {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst }, + {"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst }, + {"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst }, + {"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst }, + {"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst }, + {"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst }, + {"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst }, + {"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst }, + {"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst }, + {"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst }, + {"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst }, + {"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst }, + {"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst }, + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, + {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, + {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, + {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst }, + {"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst }, + {"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst }, + {"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst }, + {"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst }, + {"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst }, + {"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst }, + {"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst }, + {"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst }, + {"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst }, + {"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst }, + {"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst }, + {"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst }, + {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst }, + {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, + {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst }, + {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, + {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, + {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst }, + {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst }, + {"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst }, + {"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst }, + {"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst }, + {"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst }, + {"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst }, + {"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst }, + {"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst }, + {"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst }, + {"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst }, + {"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst }, + {"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst }, + {"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst }, + {"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst }, + {"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst }, + {"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst }, + {"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst }, + {"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst }, + {"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst }, + {"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst }, + {"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst }, + {"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst }, + {"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst }, + {"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst }, + {"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst }, + {"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst }, + {"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst }, + {"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst }, + {"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst }, + {"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst }, + {"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst }, + {"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst }, + {"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst }, + {"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst }, + {"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst }, + {"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst }, + {"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst }, + {"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst }, + {"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst }, + {"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst }, + {"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst }, + {"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst }, + {"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst }, + {"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst }, + {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst }, + {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst }, + {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst }, + {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst }, + {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst }, + {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst }, + {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst }, + {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst }, + {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst }, + {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst }, + {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst }, + {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst }, + {"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst }, + {"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst }, + {"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst }, + {"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0. */ + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ + {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ + {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, + {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst }, + {"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst }, + {"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst }, + {"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst }, + {"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst }, + {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst }, + {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst }, + {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst }, + {"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst }, + {"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst }, + {"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst }, + {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst }, + {"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst }, + {"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst }, + {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst }, + {"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst }, + {"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst }, + {"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst }, + {"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst }, + {"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst }, + {"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst }, + {"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst }, + {"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst }, + + {"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst }, + {"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst }, + {"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst }, + {"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst }, + {"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst }, + {"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst }, + {"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst }, + {"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst }, + + {"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst }, + {"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst }, + {"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst }, + {"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst }, + {"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst }, + {"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst }, + {"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst }, + {"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst }, + + {"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst }, + {"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst }, + {"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst }, + {"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst }, + {"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst }, + {"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst }, + {"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst }, + {"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst }, + + {"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst }, + {"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst }, + {"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst }, + {"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst }, + {"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst }, + {"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst }, + {"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst }, + {"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst }, + + {"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst }, + {"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst }, + {"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst }, + {"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst }, + {"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst }, + {"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst }, + {"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst }, + {"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst }, + + {"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst }, + {"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst }, + {"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst }, + {"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst }, + {"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst }, + {"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst }, + {"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst }, + {"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst }, + + {"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst }, + {"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst }, + {"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst }, + {"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst }, + {"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst }, + {"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst }, + {"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst }, + {"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst }, + {"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst }, + {"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst }, + {"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst }, + {"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst }, + {"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst }, + {"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst }, + {"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst }, + {"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst }, + + {"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst }, + {"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst }, + {"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst }, + {"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst }, + {"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst }, + {"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst }, + {"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst }, + {"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst }, + {"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst }, + {"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst }, + {"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst }, + {"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst }, + {"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst }, + {"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst }, + {"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst }, + {"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst }, + + {"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst }, + {"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst }, + {"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst }, + {"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst }, + {"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst }, + {"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst }, + {"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst }, + {"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst }, + {"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst }, + {"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst }, + {"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst }, + {"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst }, + {"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst }, + {"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst }, + {"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst }, + {"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst }, + + {"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst }, + {"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst }, + {"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst }, + {"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst }, + {"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst }, + {"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst }, + {"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst }, + {"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst }, + {"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst }, + {"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst }, + {"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst }, + {"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst }, + {"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst }, + {"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst }, + {"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst }, + {"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst }, + {"", 0, 0, 0, 0, 0, 0, 0, 0}, +}; + +/* Prefix for register names. */ +char register_prefix[] = "r"; +char special_register_prefix[] = "spr"; +char fsl_register_prefix[] = "rfsl"; +char pvr_register_prefix[] = "rpvr"; + + +/* #defines for valid immediate range. */ +#define MIN_IMM ((int) 0x80000000) +#define MAX_IMM ((int) 0x7fffffff) + +#define MIN_IMM15 ((int) 0x0000) +#define MAX_IMM15 ((int) 0x7fff) + +#endif /* MICROBLAZE_OPC */ + diff --git a/external/gpl3/gdb/dist/opcodes/microblaze-opcm.h b/external/gpl3/gdb/dist/opcodes/microblaze-opcm.h new file mode 100644 index 000000000000..10acacfee29e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/microblaze-opcm.h @@ -0,0 +1,139 @@ +/* microblaze-opcm.h -- Header used in microblaze-opc.h + + Copyright 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#ifndef MICROBLAZE_OPCM +#define MICROBLAZE_OPCM + +enum microblaze_instr +{ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu, + idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, + ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor, + andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, + wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd, + brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt, + bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi, + sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + fint, fsqrt, + tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, + eget, ecget, neget, necget, eput, ecput, neput, necput, + teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput, + aget, caget, naget, ncaget, aput, caput, naput, ncaput, + taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput, + eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput, + teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput, + getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd, + putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd, + egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd, + eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd, + agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd, + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, + invalid_inst +}; + +enum microblaze_instr_type +{ + arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, + return_inst, immediate_inst, special_inst, memory_load_inst, + memory_store_inst, barrel_shift_inst, anyware_inst +}; + +#define INST_WORD_SIZE 4 + +/* Gen purpose regs go from 0 to 31. */ +/* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */ + +#define REG_PC_MASK 0x8000 +#define REG_MSR_MASK 0x8001 +#define REG_EAR_MASK 0x8003 +#define REG_ESR_MASK 0x8005 +#define REG_FSR_MASK 0x8007 +#define REG_BTR_MASK 0x800b +#define REG_EDR_MASK 0x800d +#define REG_PVR_MASK 0xa000 + +#define REG_PID_MASK 0x9000 +#define REG_ZPR_MASK 0x9001 +#define REG_TLBX_MASK 0x9002 +#define REG_TLBLO_MASK 0x9003 +#define REG_TLBHI_MASK 0x9004 +#define REG_TLBSX_MASK 0x9005 + +#define MIN_REGNUM 0 +#define MAX_REGNUM 31 + +#define MIN_PVR_REGNUM 0 +#define MAX_PVR_REGNUM 15 + +#define REG_PC 32 /* PC. */ +#define REG_MSR 33 /* Machine status reg. */ +#define REG_EAR 35 /* Exception reg. */ +#define REG_ESR 37 /* Exception reg. */ +#define REG_FSR 39 /* FPU Status reg. */ +#define REG_BTR 43 /* Branch Target reg. */ +#define REG_EDR 45 /* Exception reg. */ +#define REG_PVR 40960 /* Program Verification reg. */ + +#define REG_PID 36864 /* MMU: Process ID reg. */ +#define REG_ZPR 36865 /* MMU: Zone Protect reg. */ +#define REG_TLBX 36866 /* MMU: TLB Index reg. */ +#define REG_TLBLO 36867 /* MMU: TLB Low reg. */ +#define REG_TLBHI 36868 /* MMU: TLB High reg. */ +#define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */ + +/* Alternate names for gen purpose regs. */ +#define REG_SP 1 /* stack pointer. */ +#define REG_ROSDP 2 /* read-only small data pointer. */ +#define REG_RWSDP 13 /* read-write small data pointer. */ + +/* Assembler Register - Used in Delay Slot Optimization. */ +#define REG_AS 18 +#define REG_ZERO 0 + +#define RD_LOW 21 /* Low bit for RD. */ +#define RA_LOW 16 /* Low bit for RA. */ +#define RB_LOW 11 /* Low bit for RB. */ +#define IMM_LOW 0 /* Low bit for immediate. */ + +#define RD_MASK 0x03E00000 +#define RA_MASK 0x001F0000 +#define RB_MASK 0x0000F800 +#define IMM_MASK 0x0000FFFF + +/* Imm mask for barrel shifts. */ +#define IMM5_MASK 0x0000001F + +/* FSL imm mask for get, put instructions. */ +#define RFSL_MASK 0x000000F + +/* Imm mask for msrset, msrclr instructions. */ +#define IMM15_MASK 0x00007FFF + +#endif /* MICROBLAZE-OPCM */ diff --git a/external/gpl3/gdb/dist/opcodes/mips-dis.c b/external/gpl3/gdb/dist/opcodes/mips-dis.c new file mode 100644 index 000000000000..c38a7e164c1c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mips-dis.c @@ -0,0 +1,2259 @@ +/* Print mips instructions for GDB, the GNU debugger, or for objdump. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 + Free Software Foundation, Inc. + Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opcode/mips.h" +#include "opintl.h" + +/* FIXME: These are needed to figure out if the code is mips16 or + not. The low bit of the address is often a good indicator. No + symbol table is available when this code runs out in an embedded + system as when it is used for disassembler support in a monitor. */ + +#if !defined(EMBEDDED_ENV) +#define SYMTAB_AVAILABLE 1 +#include "elf-bfd.h" +#include "elf/mips.h" +#endif + +/* Mips instructions are at maximum this many bytes long. */ +#define INSNLEN 4 + + +/* FIXME: These should be shared with gdb somehow. */ + +struct mips_cp0sel_name +{ + unsigned int cp0reg; + unsigned int sel; + const char * const name; +}; + +/* The mips16 registers. */ +static const unsigned int mips16_to_32_reg_map[] = +{ + 16, 17, 2, 3, 4, 5, 6, 7 +}; + +#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] + + +static const char * const mips_gpr_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_gpr_names_oldabi[32] = +{ + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" +}; + +static const char * const mips_gpr_names_newabi[32] = +{ + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" +}; + +static const char * const mips_fpr_names_numeric[32] = +{ + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +static const char * const mips_fpr_names_32[32] = +{ + "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", + "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", + "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", + "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" +}; + +static const char * const mips_fpr_names_n32[32] = +{ + "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", + "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" +}; + +static const char * const mips_fpr_names_64[32] = +{ + "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", + "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" +}; + +static const char * const mips_cp0_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_cp0_names_r3000[32] = +{ + "c0_index", "c0_random", "c0_entrylo", "$3", + "c0_context", "$5", "$6", "$7", + "c0_badvaddr", "$9", "c0_entryhi", "$11", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "$16", "$17", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", + "$28", "$29", "$30", "$31", +}; + +static const char * const mips_cp0_names_r4000[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "$23", + "$24", "$25", "c0_ecc", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "$31", +}; + +static const char * const mips_cp0_names_mips3264[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = +{ + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 29, 1, "c0_datahi" } +}; + +static const char * const mips_cp0_names_mips3264r2[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = +{ + { 4, 1, "c0_contextconfig" }, + { 0, 1, "c0_mvpcontrol" }, + { 0, 2, "c0_mvpconf0" }, + { 0, 3, "c0_mvpconf1" }, + { 1, 1, "c0_vpecontrol" }, + { 1, 2, "c0_vpeconf0" }, + { 1, 3, "c0_vpeconf1" }, + { 1, 4, "c0_yqmask" }, + { 1, 5, "c0_vpeschedule" }, + { 1, 6, "c0_vpeschefback" }, + { 2, 1, "c0_tcstatus" }, + { 2, 2, "c0_tcbind" }, + { 2, 3, "c0_tcrestart" }, + { 2, 4, "c0_tchalt" }, + { 2, 5, "c0_tccontext" }, + { 2, 6, "c0_tcschedule" }, + { 2, 7, "c0_tcschefback" }, + { 5, 1, "c0_pagegrain" }, + { 6, 1, "c0_srsconf0" }, + { 6, 2, "c0_srsconf1" }, + { 6, 3, "c0_srsconf2" }, + { 6, 4, "c0_srsconf3" }, + { 6, 5, "c0_srsconf4" }, + { 12, 1, "c0_intctl" }, + { 12, 2, "c0_srsctl" }, + { 12, 3, "c0_srsmap" }, + { 15, 1, "c0_ebase" }, + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 23, 1, "c0_tracecontrol" }, + { 23, 2, "c0_tracecontrol2" }, + { 23, 3, "c0_usertracedata" }, + { 23, 4, "c0_tracebpc" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 28, 2, "c0_taglo1" }, + { 28, 3, "c0_datalo1" }, + { 28, 4, "c0_taglo2" }, + { 28, 5, "c0_datalo2" }, + { 28, 6, "c0_taglo3" }, + { 28, 7, "c0_datalo3" }, + { 29, 1, "c0_datahi" }, + { 29, 2, "c0_taghi1" }, + { 29, 3, "c0_datahi1" }, + { 29, 4, "c0_taghi2" }, + { 29, 5, "c0_datahi2" }, + { 29, 6, "c0_taghi3" }, + { 29, 7, "c0_datahi3" }, +}; + +/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ +static const char * const mips_cp0_names_sb1[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", + "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", +}; + +static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = +{ + { 16, 1, "c0_config1" }, + { 18, 1, "c0_watchlo,1" }, + { 19, 1, "c0_watchhi,1" }, + { 22, 0, "c0_perftrace" }, + { 23, 3, "c0_edebug" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 26, 1, "c0_buserr_pa" }, + { 27, 1, "c0_cacheerr_d" }, + { 27, 3, "c0_cacheerr_d_pa" }, + { 28, 1, "c0_datalo_i" }, + { 28, 2, "c0_taglo_d" }, + { 28, 3, "c0_datalo_d" }, + { 29, 1, "c0_datahi_i" }, + { 29, 2, "c0_taghi_d" }, + { 29, 3, "c0_datahi_d" }, +}; + +/* Xlr cop0 register names. */ +static const char * const mips_cp0_names_xlr[32] = { + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_status", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "c0_debug", + "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", + "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", +}; + +/* XLR's CP0 Select Registers. */ + +static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = { + { 9, 6, "c0_extintreq" }, + { 9, 7, "c0_extintmask" }, + { 15, 1, "c0_ebase" }, + { 16, 1, "c0_config1" }, + { 16, 2, "c0_config2" }, + { 16, 3, "c0_config3" }, + { 16, 7, "c0_procid2" }, + { 18, 1, "c0_watchlo,1" }, + { 18, 2, "c0_watchlo,2" }, + { 18, 3, "c0_watchlo,3" }, + { 18, 4, "c0_watchlo,4" }, + { 18, 5, "c0_watchlo,5" }, + { 18, 6, "c0_watchlo,6" }, + { 18, 7, "c0_watchlo,7" }, + { 19, 1, "c0_watchhi,1" }, + { 19, 2, "c0_watchhi,2" }, + { 19, 3, "c0_watchhi,3" }, + { 19, 4, "c0_watchhi,4" }, + { 19, 5, "c0_watchhi,5" }, + { 19, 6, "c0_watchhi,6" }, + { 19, 7, "c0_watchhi,7" }, + { 25, 1, "c0_perfcnt,1" }, + { 25, 2, "c0_perfcnt,2" }, + { 25, 3, "c0_perfcnt,3" }, + { 25, 4, "c0_perfcnt,4" }, + { 25, 5, "c0_perfcnt,5" }, + { 25, 6, "c0_perfcnt,6" }, + { 25, 7, "c0_perfcnt,7" }, + { 27, 1, "c0_cacheerr,1" }, + { 27, 2, "c0_cacheerr,2" }, + { 27, 3, "c0_cacheerr,3" }, + { 28, 1, "c0_datalo" }, + { 29, 1, "c0_datahi" } +}; + +static const char * const mips_hwr_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const mips_hwr_names_mips3264r2[32] = +{ + "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", + "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +struct mips_abi_choice +{ + const char * name; + const char * const *gpr_names; + const char * const *fpr_names; +}; + +struct mips_abi_choice mips_abi_choices[] = +{ + { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, + { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, + { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, + { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, +}; + +struct mips_arch_choice +{ + const char *name; + int bfd_mach_valid; + unsigned long bfd_mach; + int processor; + int isa; + const char * const *cp0_names; + const struct mips_cp0sel_name *cp0sel_names; + unsigned int cp0sel_names_len; + const char * const *hwr_names; +}; + +const struct mips_arch_choice mips_arch_choices[] = +{ + { "numeric", 0, 0, 0, 0, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + + { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, + mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, + { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, + mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, + mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + + /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. + Note that MIPS-3D and MDMX are not applicable to MIPS32. (See + _MIPS32 Architecture For Programmers Volume I: Introduction to the + MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), + page 1. */ + { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, + ISA_MIPS32 | INSN_SMARTMIPS, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + + { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, + (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 + | INSN_MIPS3D | INSN_MT), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + + /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ + { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, + ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX, + mips_cp0_names_mips3264, + mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), + mips_hwr_names_numeric }, + + { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, + (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 + | INSN_DSP64 | INSN_MT | INSN_MDMX), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + + { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, + ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, + mips_cp0_names_sb1, + mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), + mips_hwr_names_numeric }, + + { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, + ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, + NULL, 0, mips_hwr_names_numeric }, + + { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, + ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, + NULL, 0, mips_hwr_names_numeric }, + + { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, + ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric, + NULL, 0, mips_hwr_names_numeric }, + + { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, + ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, + mips_hwr_names_numeric }, + + { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, + ISA_MIPS64 | INSN_XLR, + mips_cp0_names_xlr, + mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), + mips_hwr_names_numeric }, + + /* This entry, mips16, is here only for ISA/processor selection; do + not print its name. */ + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, + mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, +}; + +/* ISA and processor type to disassemble for, and register names to use. + set_default_mips_dis_options and parse_mips_dis_options fill in these + values. */ +static int mips_processor; +static int mips_isa; +static const char * const *mips_gpr_names; +static const char * const *mips_fpr_names; +static const char * const *mips_cp0_names; +static const struct mips_cp0sel_name *mips_cp0sel_names; +static int mips_cp0sel_names_len; +static const char * const *mips_hwr_names; + +/* Other options */ +static int no_aliases; /* If set disassemble as most general inst. */ + +static const struct mips_abi_choice * +choose_abi_by_name (const char *name, unsigned int namelen) +{ + const struct mips_abi_choice *c; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) + if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 + && strlen (mips_abi_choices[i].name) == namelen) + c = &mips_abi_choices[i]; + + return c; +} + +static const struct mips_arch_choice * +choose_arch_by_name (const char *name, unsigned int namelen) +{ + const struct mips_arch_choice *c = NULL; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) + if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 + && strlen (mips_arch_choices[i].name) == namelen) + c = &mips_arch_choices[i]; + + return c; +} + +static const struct mips_arch_choice * +choose_arch_by_number (unsigned long mach) +{ + static unsigned long hint_bfd_mach; + static const struct mips_arch_choice *hint_arch_choice; + const struct mips_arch_choice *c; + unsigned int i; + + /* We optimize this because even if the user specifies no + flags, this will be done for every instruction! */ + if (hint_bfd_mach == mach + && hint_arch_choice != NULL + && hint_arch_choice->bfd_mach == hint_bfd_mach) + return hint_arch_choice; + + for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) + { + if (mips_arch_choices[i].bfd_mach_valid + && mips_arch_choices[i].bfd_mach == mach) + { + c = &mips_arch_choices[i]; + hint_bfd_mach = mach; + hint_arch_choice = c; + } + } + return c; +} + +/* Check if the object uses NewABI conventions. */ + +static int +is_newabi (Elf_Internal_Ehdr *header) +{ + /* There are no old-style ABIs which use 64-bit ELF. */ + if (header->e_ident[EI_CLASS] == ELFCLASS64) + return 1; + + /* If a 32-bit ELF file, n32 is a new-style ABI. */ + if ((header->e_flags & EF_MIPS_ABI2) != 0) + return 1; + + return 0; +} + +static void +set_default_mips_dis_options (struct disassemble_info *info) +{ + const struct mips_arch_choice *chosen_arch; + + /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, + and numeric FPR, CP0 register, and HWR names. */ + mips_isa = ISA_MIPS3; + mips_processor = CPU_R3000; + mips_gpr_names = mips_gpr_names_oldabi; + mips_fpr_names = mips_fpr_names_numeric; + mips_cp0_names = mips_cp0_names_numeric; + mips_cp0sel_names = NULL; + mips_cp0sel_names_len = 0; + mips_hwr_names = mips_hwr_names_numeric; + no_aliases = 0; + + /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ + if (info->flavour == bfd_target_elf_flavour && info->section != NULL) + { + Elf_Internal_Ehdr *header; + + header = elf_elfheader (info->section->owner); + if (is_newabi (header)) + mips_gpr_names = mips_gpr_names_newabi; + } + + /* Set ISA, architecture, and cp0 register names as best we can. */ +#if ! SYMTAB_AVAILABLE + /* This is running out on a target machine, not in a host tool. + FIXME: Where does mips_target_info come from? */ + target_processor = mips_target_info.processor; + mips_isa = mips_target_info.isa; +#else + chosen_arch = choose_arch_by_number (info->mach); + if (chosen_arch != NULL) + { + mips_processor = chosen_arch->processor; + mips_isa = chosen_arch->isa; + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; + } +#endif +} + +static void +parse_mips_dis_option (const char *option, unsigned int len) +{ + unsigned int i, optionlen, vallen; + const char *val; + const struct mips_abi_choice *chosen_abi; + const struct mips_arch_choice *chosen_arch; + + /* Try to match options that are simple flags */ + if (CONST_STRNEQ (option, "no-aliases")) + { + no_aliases = 1; + return; + } + + /* Look for the = that delimits the end of the option name. */ + for (i = 0; i < len; i++) + if (option[i] == '=') + break; + + if (i == 0) /* Invalid option: no name before '='. */ + return; + if (i == len) /* Invalid option: no '='. */ + return; + if (i == (len - 1)) /* Invalid option: no value after '='. */ + return; + + optionlen = i; + val = option + (optionlen + 1); + vallen = len - (optionlen + 1); + + if (strncmp ("gpr-names", option, optionlen) == 0 + && strlen ("gpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + mips_gpr_names = chosen_abi->gpr_names; + return; + } + + if (strncmp ("fpr-names", option, optionlen) == 0 + && strlen ("fpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + mips_fpr_names = chosen_abi->fpr_names; + return; + } + + if (strncmp ("cp0-names", option, optionlen) == 0 + && strlen ("cp0-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + } + return; + } + + if (strncmp ("hwr-names", option, optionlen) == 0 + && strlen ("hwr-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + mips_hwr_names = chosen_arch->hwr_names; + return; + } + + if (strncmp ("reg-names", option, optionlen) == 0 + && strlen ("reg-names") == optionlen) + { + /* We check both ABI and ARCH here unconditionally, so + that "numeric" will do the desirable thing: select + numeric register names for all registers. Other than + that, a given name probably won't match both. */ + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + { + mips_gpr_names = chosen_abi->gpr_names; + mips_fpr_names = chosen_abi->fpr_names; + } + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + mips_cp0_names = chosen_arch->cp0_names; + mips_cp0sel_names = chosen_arch->cp0sel_names; + mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_hwr_names = chosen_arch->hwr_names; + } + return; + } + + /* Invalid option. */ +} + +static void +parse_mips_dis_options (const char *options) +{ + const char *option_end; + + if (options == NULL) + return; + + while (*options != '\0') + { + /* Skip empty options. */ + if (*options == ',') + { + options++; + continue; + } + + /* We know that *options is neither NUL or a comma. */ + option_end = options + 1; + while (*option_end != ',' && *option_end != '\0') + option_end++; + + parse_mips_dis_option (options, option_end - options); + + /* Go on to the next one. If option_end points to a comma, it + will be skipped above. */ + options = option_end; + } +} + +static const struct mips_cp0sel_name * +lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, + unsigned int len, + unsigned int cp0reg, + unsigned int sel) +{ + unsigned int i; + + for (i = 0; i < len; i++) + if (names[i].cp0reg == cp0reg && names[i].sel == sel) + return &names[i]; + return NULL; +} + +/* Print insn arguments for 32/64-bit code. */ + +static void +print_insn_args (const char *d, + register unsigned long int l, + bfd_vma pc, + struct disassemble_info *info, + const struct mips_opcode *opp) +{ + int op, delta; + unsigned int lsb, msb, msbd; + + lsb = 0; + + for (; *d != '\0'; d++) + { + switch (*d) + { + case ',': + case '(': + case ')': + case '[': + case ']': + (*info->fprintf_func) (info->stream, "%c", *d); + break; + + case '+': + /* Extension character; switch for second char. */ + d++; + switch (*d) + { + case '\0': + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, incomplete extension sequence (+)")); + return; + + case 'A': + lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'B': + msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case '1': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI1) & OP_MASK_UDI1); + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI2) & OP_MASK_UDI2); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI3) & OP_MASK_UDI3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI4) & OP_MASK_UDI4); + break; + + case 'C': + case 'H': + msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + + case 'D': + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mtcN (et al.), to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + + case 'E': + lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'F': + msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case 'G': + msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + + case 't': /* Coprocessor 0 reg name */ + (*info->fprintf_func) (info->stream, "%s", + mips_cp0_names[(l >> OP_SH_RT) & + OP_MASK_RT]); + break; + + case 'T': /* Coprocessor 0 reg name */ + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mftc0, to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + + case 'x': /* bbit bit index */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BBITIND) & OP_MASK_BBITIND); + break; + + case 'p': /* cins, cins32, exts and exts32 position */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS); + break; + + case 's': /* cins and exts length-minus-one */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); + break; + + case 'S': /* cins32 and exts32 length-minus-one field */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); + break; + + case 'Q': /* seqi/snei immediate field */ + op = (l >> OP_SH_SEQI) & OP_MASK_SEQI; + /* Sign-extend it. */ + op = (op ^ 512) - 512; + (*info->fprintf_func) (info->stream, "%d", op); + break; + + case 'a': /* 8-bit signed offset in bit 6 */ + delta = (l >> OP_SH_OFFSET_A) & OP_MASK_OFFSET_A; + if (delta & 0x80) + delta |= ~OP_MASK_OFFSET_A; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case 'b': /* 8-bit signed offset in bit 3 */ + delta = (l >> OP_SH_OFFSET_B) & OP_MASK_OFFSET_B; + if (delta & 0x80) + delta |= ~OP_MASK_OFFSET_B; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case 'c': /* 9-bit signed offset in bit 6 */ + delta = (l >> OP_SH_OFFSET_C) & OP_MASK_OFFSET_C; + if (delta & 0x100) + delta |= ~OP_MASK_OFFSET_C; + /* Left shift 4 bits to print the real offset. */ + (*info->fprintf_func) (info->stream, "%d", delta << 4); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RZ) & OP_MASK_RZ]); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, undefined extension sequence (+%c)"), + *d); + return; + } + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BP) & OP_MASK_BP); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SA3) & OP_MASK_SA3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SA4) & OP_MASK_SA4); + break; + + case '5': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_IMM8) & OP_MASK_IMM8); + break; + + case '6': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_RS) & OP_MASK_RS); + break; + + case '7': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); + break; + + case '8': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); + break; + + case '9': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); + break; + + case '0': /* dsp 6-bit signed immediate in bit 20 */ + delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); + if (delta & 0x20) /* test sign bit */ + delta |= ~OP_MASK_DSPSFT; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case ':': /* dsp 7-bit signed immediate in bit 19 */ + delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); + if (delta & 0x40) /* test sign bit */ + delta |= ~OP_MASK_DSPSFT_7; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case '\'': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); + break; + + case '@': /* dsp 10-bit signed immediate in bit 16 */ + delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); + if (delta & 0x200) /* test sign bit */ + delta |= ~OP_MASK_IMM10; + (*info->fprintf_func) (info->stream, "%d", delta); + break; + + case '!': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_U) & OP_MASK_MT_U); + break; + + case '$': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_H) & OP_MASK_MT_H); + break; + + case '*': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); + break; + + case '&': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); + break; + + case 'g': + /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 's': + case 'b': + case 'r': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); + break; + + case 't': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + break; + + case 'i': + case 'u': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); + break; + + case 'j': /* Same as i, but sign-extended. */ + case 'o': + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + (*info->fprintf_func) (info->stream, "%d", + delta); + break; + + case 'h': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_PREFX) + & OP_MASK_PREFX)); + break; + + case 'k': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_CACHE) + & OP_MASK_CACHE)); + break; + + case 'a': + info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) + | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + /* For gdb disassembler, force odd address on jalx. */ + if (info->flavour == bfd_target_unknown_flavour + && strcmp (opp->name, "jalx") == 0) + info->target |= 1; + (*info->print_address_func) (info->target, info); + break; + + case 'p': + /* Sign extend the displacement. */ + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + info->target = (delta << 2) + pc + INSNLEN; + (*info->print_address_func) (info->target, info); + break; + + case 'd': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'U': + { + /* First check for both rd and rt being equal. */ + unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; + if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[reg]); + else + { + /* If one is zero use the other. */ + if (reg == 0) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[reg]); + else /* Bogus, result depends on processor. */ + (*info->fprintf_func) (info->stream, "%s or %s", + mips_gpr_names[reg], + mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); + } + } + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); + break; + + case '<': + case '1': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); + break; + + case 'c': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE) & OP_MASK_CODE); + break; + + case 'q': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE2) & OP_MASK_CODE2); + break; + + case 'C': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_COPZ) & OP_MASK_COPZ); + break; + + case 'B': + (*info->fprintf_func) (info->stream, "0x%lx", + + (l >> OP_SH_CODE20) & OP_MASK_CODE20); + break; + + case 'J': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE19) & OP_MASK_CODE19); + break; + + case 'S': + case 'V': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); + break; + + case 'T': + case 'W': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); + break; + + case 'D': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "%s", + mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); + break; + + case 'E': + /* Coprocessor register for lwcN instructions, et al. + + Note that there is no load/store cp0 instructions, and + that FPU (cp1) instructions disassemble this field using + 'T' format. Therefore, until we gain understanding of + cp2 register names, we can simply print the register + numbers. */ + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RT) & OP_MASK_RT); + break; + + case 'G': + /* Coprocessor register for mtcN instructions, et al. Note + that FPU (cp1) instructions disassemble this field using + 'S' format. Therefore, we only need to worry about cp0, + cp2, and cp3. */ + op = (l >> OP_SH_OP) & OP_MASK_OP; + if (op == OP_OP_COP0) + (*info->fprintf_func) (info->stream, "%s", + mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); + else + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 'K': + (*info->fprintf_func) (info->stream, "%s", + mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'N': + (*info->fprintf_func) (info->stream, + ((opp->pinfo & (FP_D | FP_S)) != 0 + ? "$fcc%ld" : "$cc%ld"), + (l >> OP_SH_BCC) & OP_MASK_BCC); + break; + + case 'M': + (*info->fprintf_func) (info->stream, "$fcc%ld", + (l >> OP_SH_CCC) & OP_MASK_CCC); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); + break; + + case 'e': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); + break; + + case '%': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_SEL) & OP_MASK_SEL); + break; + + case 'O': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_ALN) & OP_MASK_ALN); + break; + + case 'Q': + { + unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; + + if ((vsel & 0x10) == 0) + { + int fmt; + + vsel &= 0x0f; + for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) + if ((vsel & 1) == 0) + break; + (*info->fprintf_func) (info->stream, "$v%ld[%d]", + (l >> OP_SH_FT) & OP_MASK_FT, + vsel >> 1); + } + else if ((vsel & 0x08) == 0) + { + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FT) & OP_MASK_FT); + } + else + { + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_FT) & OP_MASK_FT); + } + } + break; + + case 'X': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FD) & OP_MASK_FD); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FS) & OP_MASK_FS); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "$v%ld", + (l >> OP_SH_FT) & OP_MASK_FT); + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, + _("# internal error, undefined modifier (%c)"), + *d); + return; + } + } +} + +/* Print the mips instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes, which is + always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +print_insn_mips (bfd_vma memaddr, + unsigned long int word, + struct disassemble_info *info) +{ + const struct mips_opcode *op; + static bfd_boolean init = 0; + static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; + + /* Build a hash table to shorten the search time. */ + if (! init) + { + unsigned int i; + + for (i = 0; i <= OP_MASK_OP; i++) + { + for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo == INSN_MACRO + || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) + continue; + if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) + { + mips_hash[i] = op; + break; + } + } + } + + init = 1; + } + + info->bytes_per_chunk = INSNLEN; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; + if (op != NULL) + { + for (; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (word & op->mask) == op->match) + { + const char *d; + + /* We always allow to disassemble the jalx instruction. */ + if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) + && strcmp (op->name, "jalx")) + continue; + + /* Figure out instruction type and branch delay information. */ + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + if ((op->pinfo & (INSN_WRITE_GPR_31 + | INSN_WRITE_GPR_D)) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_COND_BRANCH_DELAY + | INSN_COND_BRANCH_LIKELY)) != 0) + { + if ((op->pinfo & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_condbranch; + info->branch_delay_insns = 1; + } + else if ((op->pinfo & (INSN_STORE_MEMORY + | INSN_LOAD_MEMORY_DELAY)) != 0) + info->insn_type = dis_dref; + + (*info->fprintf_func) (info->stream, "%s", op->name); + + d = op->args; + if (d != NULL && *d != '\0') + { + (*info->fprintf_func) (info->stream, "\t"); + print_insn_args (d, word, memaddr, info, op); + } + + return INSNLEN; + } + } + } + + /* Handle undefined instructions. */ + info->insn_type = dis_noninsn; + (*info->fprintf_func) (info->stream, "0x%lx", word); + return INSNLEN; +} + +/* Disassemble an operand for a mips16 instruction. */ + +static void +print_mips16_insn_arg (char type, + const struct mips_opcode *op, + int l, + bfd_boolean use_extend, + int extend, + bfd_vma memaddr, + struct disassemble_info *info) +{ + switch (type) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", type); + break; + + case 'y': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY))); + break; + + case 'x': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX))); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ))); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z))); + break; + + case '0': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "$pc"); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); + break; + + case 'X': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[((l >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32)]); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); + break; + + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '6': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + { + int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; + + shift = 0; + signedp = 0; + extbits = 16; + pcrel = 0; + extu = 0; + branch = 0; + switch (type) + { + case '<': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 5; + extu = 1; + break; + case '>': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 5; + extu = 1; + break; + case '[': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 6; + extu = 1; + break; + case ']': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 6; + extu = 1; + break; + case '4': + nbits = 4; + immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; + signedp = 1; + extbits = 15; + break; + case '5': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 1; + break; + case 'H': + nbits = 5; + shift = 1; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 2; + break; + case 'W': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 + && (op->pinfo & MIPS16_INSN_READ_SP) == 0) + { + info->insn_type = dis_dref; + info->data_size = 4; + } + break; + case 'D': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'j': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + signedp = 1; + break; + case '6': + nbits = 6; + immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + break; + case '8': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + break; + case 'V': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + /* FIXME: This might be lw, or it might be addiu to $sp or + $pc. We assume it's load. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'C': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'U': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + extu = 1; + break; + case 'k': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'K': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'p': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + pcrel = 1; + branch = 1; + break; + case 'q': + nbits = 11; + immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; + signedp = 1; + pcrel = 1; + branch = 1; + break; + case 'A': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + pcrel = 1; + /* FIXME: This can be lw or la. We assume it is lw. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'B': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'E': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + break; + default: + abort (); + } + + if (! use_extend) + { + if (signedp && immed >= (1 << (nbits - 1))) + immed -= 1 << nbits; + immed <<= shift; + if ((type == '<' || type == '>' || type == '[' || type == ']') + && immed == 0) + immed = 8; + } + else + { + if (extbits == 16) + immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); + else if (extbits == 15) + immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); + else + immed = ((extend >> 6) & 0x1f) | (extend & 0x20); + immed &= (1 << extbits) - 1; + if (! extu && immed >= (1 << (extbits - 1))) + immed -= 1 << extbits; + } + + if (! pcrel) + (*info->fprintf_func) (info->stream, "%d", immed); + else + { + bfd_vma baseaddr; + + if (branch) + { + immed *= 2; + baseaddr = memaddr + 2; + } + else if (use_extend) + baseaddr = memaddr - 2; + else + { + int status; + bfd_byte buffer[2]; + + baseaddr = memaddr; + + /* If this instruction is in the delay slot of a jr + instruction, the base address is the address of the + jr instruction. If it is in the delay slot of jalr + instruction, the base address is the address of the + jalr instruction. This test is unreliable: we have + no way of knowing whether the previous word is + instruction or data. */ + status = (*info->read_memory_func) (memaddr - 4, buffer, 2, + info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf800) == 0x1800)) + baseaddr = memaddr - 4; + else + { + status = (*info->read_memory_func) (memaddr - 2, buffer, + 2, info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf81f) == 0xe800)) + baseaddr = memaddr - 2; + } + } + info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + if (pcrel && branch + && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + info->target |= 1; + (*info->print_address_func) (info->target, info); + } + } + break; + + case 'a': + { + int jalx = l & 0x400; + + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + if (!jalx && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + l |= 1; + } + info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; + (*info->print_address_func) (info->target, info); + break; + + case 'l': + case 'L': + { + int need_comma, amask, smask; + + need_comma = 0; + + l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + + amask = (l >> 3) & 7; + + if (amask > 0 && amask < 5) + { + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); + if (amask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[amask + 3]); + need_comma = 1; + } + + smask = (l >> 1) & 3; + if (smask == 3) + { + (*info->fprintf_func) (info->stream, "%s??", + need_comma ? "," : ""); + need_comma = 1; + } + else if (smask > 0) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips_gpr_names[16]); + if (smask > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[smask + 15]); + need_comma = 1; + } + + if (l & 1) + { + (*info->fprintf_func) (info->stream, "%s%s", + need_comma ? "," : "", + mips_gpr_names[31]); + need_comma = 1; + } + + if (amask == 5 || amask == 6) + { + (*info->fprintf_func) (info->stream, "%s$f0", + need_comma ? "," : ""); + if (amask == 6) + (*info->fprintf_func) (info->stream, "-$f1"); + } + } + break; + + case 'm': + case 'M': + /* MIPS16e save/restore. */ + { + int need_comma = 0; + int amask, args, statics; + int nsreg, smask; + int framesz; + int i, j; + + l = l & 0x7f; + if (use_extend) + l |= extend << 16; + + amask = (l >> 16) & 0xf; + if (amask == MIPS16_ALL_ARGS) + { + args = 4; + statics = 0; + } + else if (amask == MIPS16_ALL_STATICS) + { + args = 0; + statics = 4; + } + else + { + args = amask >> 2; + statics = amask & 3; + } + + if (args > 0) { + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); + if (args > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[4 + args - 1]); + need_comma = 1; + } + + framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; + if (framesz == 0 && !use_extend) + framesz = 128; + + (*info->fprintf_func) (info->stream, "%s%d", + need_comma ? "," : "", + framesz); + + if (l & 0x40) /* $ra */ + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); + + nsreg = (l >> 24) & 0x7; + smask = 0; + if (l & 0x20) /* $s0 */ + smask |= 1 << 0; + if (l & 0x10) /* $s1 */ + smask |= 1 << 1; + if (nsreg > 0) /* $s2-$s8 */ + smask |= ((1 << nsreg) - 1) << 2; + + /* Find first set static reg bit. */ + for (i = 0; i < 9; i++) + { + if (smask & (1 << i)) + { + (*info->fprintf_func) (info->stream, ",%s", + mips_gpr_names[i == 8 ? 30 : (16 + i)]); + /* Skip over string of set bits. */ + for (j = i; smask & (2 << j); j++) + continue; + if (j > i) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[j == 8 ? 30 : (16 + j)]); + i = j + 1; + } + } + + /* Statics $ax - $a3. */ + if (statics == 1) + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); + else if (statics > 0) + (*info->fprintf_func) (info->stream, ",%s-%s", + mips_gpr_names[7 - statics + 1], + mips_gpr_names[7]); + } + break; + + default: + /* xgettext:c-format */ + (*info->fprintf_func) + (info->stream, + _("# internal disassembler error, unrecognised modifier (%c)"), + type); + abort (); + } +} + +/* Disassemble mips16 instructions. */ + +static int +print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[2]; + int length; + int insn; + bfd_boolean use_extend; + int extend = 0; + const struct mips_opcode *op, *opend; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Handle the extend opcode specially. */ + use_extend = FALSE; + if ((insn & 0xf800) == 0xf000) + { + use_extend = TRUE; + extend = insn & 0x7ff; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Check for an extend opcode followed by an extend opcode. */ + if ((insn & 0xf800) == 0xf000) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length; + } + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + + opend = mips16_opcodes + bfd_mips16_num_opcodes; + for (op = mips16_opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (insn & op->mask) == op->match) + { + const char *s; + + if (strchr (op->args, 'a') != NULL) + { + if (use_extend) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length - 2; + } + + use_extend = FALSE; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, + info); + if (status == 0) + { + use_extend = TRUE; + if (info->endian == BFD_ENDIAN_BIG) + extend = bfd_getb16 (buffer); + else + extend = bfd_getl16 (buffer); + length += 2; + } + } + + (*info->fprintf_func) (info->stream, "%s", op->name); + if (op->args[0] != '\0') + (*info->fprintf_func) (info->stream, "\t"); + + for (s = op->args; *s != '\0'; s++) + { + if (*s == ',' + && s[1] == 'w' + && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) + == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + if (*s == ',' + && s[1] == 'v' + && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) + == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, + info); + } + + /* Figure out branch instruction type and delay slot information. */ + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + info->branch_delay_insns = 1; + if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY + | MIPS16_INSN_UNCOND_BRANCH)) != 0) + { + if ((op->pinfo & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + } + else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0) + info->insn_type = dis_condbranch; + + return length; + } + } + + if (use_extend) + (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); + (*info->fprintf_func) (info->stream, "0x%x", insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* In an environment where we do not know the symbol type of the + instruction we are forced to assume that the low order bit of the + instructions' address may mark it as a mips16 instruction. If we + are single stepping, or the pc is within the disassembled function, + this works. Otherwise, we need a clue. Sometimes. */ + +static int +_print_insn_mips (bfd_vma memaddr, + struct disassemble_info *info, + enum bfd_endian endianness) +{ + bfd_byte buffer[INSNLEN]; + int status; + + set_default_mips_dis_options (info); + parse_mips_dis_options (info->disassembler_options); + +#if 1 + /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ + /* Only a few tools will work this way. */ + if (memaddr & 0x01) + return print_insn_mips16 (memaddr, info); +#endif + +#if SYMTAB_AVAILABLE + if (info->mach == bfd_mach_mips16 + || (info->symbols != NULL + && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour + && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols) + ->internal_elf_sym.st_other))) + return print_insn_mips16 (memaddr, info); +#endif + + status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); + if (status == 0) + { + unsigned long insn; + + if (endianness == BFD_ENDIAN_BIG) + insn = (unsigned long) bfd_getb32 (buffer); + else + insn = (unsigned long) bfd_getl32 (buffer); + + return print_insn_mips (memaddr, insn, info); + } + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +int +print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); +} + +int +print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); +} + +void +print_mips_disassembler_options (FILE *stream) +{ + unsigned int i; + + fprintf (stream, _("\n\ +The following MIPS specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _("\n\ + gpr-names=ABI Print GPR names according to specified ABI.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + fpr-names=ABI Print FPR names according to specified ABI.\n\ + Default: numeric.\n")); + + fprintf (stream, _("\n\ + cp0-names=ARCH Print CP0 register names according to\n\ + specified architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + hwr-names=ARCH Print HWR names according to specified \n\ + architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + reg-names=ABI Print GPR and FPR names according to\n\ + specified ABI.\n")); + + fprintf (stream, _("\n\ + reg-names=ARCH Print CP0 register and HWR names according to\n\ + specified architecture.\n")); + + fprintf (stream, _("\n\ + For the options above, the following values are supported for \"ABI\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) + fprintf (stream, " %s", mips_abi_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n\ + For the options above, The following values are supported for \"ARCH\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) + if (*mips_arch_choices[i].name != '\0') + fprintf (stream, " %s", mips_arch_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n")); +} diff --git a/external/gpl3/gdb/dist/opcodes/mips-opc.c b/external/gpl3/gdb/dist/opcodes/mips-opc.c new file mode 100644 index 000000000000..8f51643ee471 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mips-opc.c @@ -0,0 +1,2082 @@ +/* mips-opc.c -- MIPS opcode list. + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. + MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom + Corporation (SiByte). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/mips.h" + +/* Short hand so the lines aren't too long. */ + +#define LDD INSN_LOAD_MEMORY_DELAY +#define LCD INSN_LOAD_COPROC_DELAY +#define UBD INSN_UNCOND_BRANCH_DELAY +#define CBD INSN_COND_BRANCH_DELAY +#define COD INSN_COPROC_MOVE_DELAY +#define CLD INSN_COPROC_MEMORY_DELAY +#define CBL INSN_COND_BRANCH_LIKELY +#define TRAP INSN_TRAP +#define SM INSN_STORE_MEMORY + +#define WR_d INSN_WRITE_GPR_D +#define WR_t INSN_WRITE_GPR_T +#define WR_31 INSN_WRITE_GPR_31 +#define WR_D INSN_WRITE_FPR_D +#define WR_T INSN_WRITE_FPR_T +#define WR_S INSN_WRITE_FPR_S +#define RD_s INSN_READ_GPR_S +#define RD_b INSN_READ_GPR_S +#define RD_t INSN_READ_GPR_T +#define RD_S INSN_READ_FPR_S +#define RD_T INSN_READ_FPR_T +#define RD_R INSN_READ_FPR_R +#define WR_CC INSN_WRITE_COND_CODE +#define RD_CC INSN_READ_COND_CODE +#define RD_C0 INSN_COP +#define RD_C1 INSN_COP +#define RD_C2 INSN_COP +#define RD_C3 INSN_COP +#define WR_C0 INSN_COP +#define WR_C1 INSN_COP +#define WR_C2 INSN_COP +#define WR_C3 INSN_COP +#define CP INSN_COP + +#define WR_HI INSN_WRITE_HI +#define RD_HI INSN_READ_HI +#define MOD_HI WR_HI|RD_HI + +#define WR_LO INSN_WRITE_LO +#define RD_LO INSN_READ_LO +#define MOD_LO WR_LO|RD_LO + +#define WR_HILO WR_HI|WR_LO +#define RD_HILO RD_HI|RD_LO +#define MOD_HILO WR_HILO|RD_HILO + +#define IS_M INSN_MULT + +#define WR_MACC INSN2_WRITE_MDMX_ACC +#define RD_MACC INSN2_READ_MDMX_ACC + +#define I1 INSN_ISA1 +#define I2 INSN_ISA2 +#define I3 INSN_ISA3 +#define I4 INSN_ISA4 +#define I5 INSN_ISA5 +#define I32 INSN_ISA32 +#define I64 INSN_ISA64 +#define I33 INSN_ISA32R2 +#define I65 INSN_ISA64R2 +#define I3_32 INSN_ISA3_32 +#define I3_33 INSN_ISA3_32R2 +#define I4_32 INSN_ISA4_32 +#define I4_33 INSN_ISA4_32R2 +#define I5_33 INSN_ISA5_32R2 + +/* MIPS64 MIPS-3D ASE support. */ +#define M3D INSN_MIPS3D + +/* MIPS32 SmartMIPS ASE support. */ +#define SMT INSN_SMARTMIPS + +/* MIPS64 MDMX ASE support. */ +#define MX INSN_MDMX + +#define IL2E (INSN_LOONGSON_2E) +#define IL2F (INSN_LOONGSON_2F) +#define IL3A (INSN_LOONGSON_3A) + +#define P3 INSN_4650 +#define L1 INSN_4010 +#define V1 (INSN_4100 | INSN_4111 | INSN_4120) +#define T3 INSN_3900 +#define M1 INSN_10000 +#define SB1 INSN_SB1 +#define N411 INSN_4111 +#define N412 INSN_4120 +#define N5 (INSN_5400 | INSN_5500) +#define N54 INSN_5400 +#define N55 INSN_5500 +#define IOCT INSN_OCTEON +#define XLR INSN_XLR + +#define G1 (T3 \ + ) + +#define G2 (T3 \ + ) + +#define G3 (I4 \ + ) + +/* MIPS DSP ASE support. + NOTE: + 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair + of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have + the same structure as $ac0 (HI + LO). For DSP instructions that write or + read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a + (RD_HILO) attributes, such that HILO dependencies are maintained + conservatively. + + 2. For some mul. instructions that use integer registers as destinations + but destroy HI+LO as side-effect, we add WR_HILO to their attributes. + + 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields + (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write + certain fields of the DSP control register. For simplicity, we decide not + to track dependencies of these fields. + However, "bposge32" is a branch instruction that depends on the "pos" + field. In order to make sure that GAS does not reorder DSP instructions + that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) + attribute to those instructions that write the "pos" field. */ + +#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ +#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ +#define MOD_a WR_a|RD_a +#define DSP_VOLA INSN_TRAP +#define D32 INSN_DSP +#define D33 INSN_DSPR2 +#define D64 INSN_DSP64 + +/* MIPS MT ASE support. */ +#define MT32 INSN_MT + +/* Loongson support. */ +#define WR_z INSN2_WRITE_GPR_Z +#define WR_Z INSN2_WRITE_FPR_Z +#define RD_z INSN2_READ_GPR_Z +#define RD_Z INSN2_READ_FPR_Z +#define RD_d INSN2_READ_GPR_D + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. + + Many instructions are short hand for other instructions (i.e., The + jal instruction is short for jalr ). */ + +const struct mips_opcode mips_builtin_opcodes[] = +{ +/* These instructions appear first so that the disassembler will find + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ +/* name, args, match, mask, pinfo, pinfo2, membership */ +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 }, +{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 }, +{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ +{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ +{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ +{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, +{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, +{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ +{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ +{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ +{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ +{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ +{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ + +/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 + instructions. Put them here so that disassembler will find them first. + The assemblers uses a hash table based on the instruction name anyhow. */ +{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_s|RD_t, RD_d, IL3A }, +{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_d|RD_s, 0, IL3A }, +{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, +{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_s|RD_t, 0, IL3A }, +{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_t|RD_b|SM, RD_d, IL3A }, +{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_T|RD_b|SM, RD_d, IL3A }, +{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_T|RD_b|LDD, 0, IL3A }, +{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_T|RD_b|SM, 0, IL3A }, +{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_t|RD_b|LDD, RD_d, IL3A }, +{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_t|RD_b|SM, RD_d, IL3A }, +{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_T|RD_b|LDD, RD_d, IL3A }, +{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, +{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_T|RD_b|SM, RD_d, IL3A }, +{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_t|RD_b|LDD, WR_z, IL3A }, +{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_t|RD_b|SM, RD_z, IL3A }, +{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_T|RD_b|LDD, WR_Z, IL3A }, +{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_T|RD_b|SM, RD_Z, IL3A }, + +{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, +{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, +{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +{"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, +{"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, +{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, I5_33 }, +{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, +{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, +{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, +{"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +/* b is at the top of the table. */ +/* bal is at the top of the table. */ +{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */ +{"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +{"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +{"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit132 */ +{"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, +/* bc0[tf]l? are at the bottom of the table. */ +{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, +{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, +{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, +{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, +{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4_32 }, +{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, +{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4_32 }, +/* bc2* are at the bottom of the table. */ +/* bc3* are at the bottom of the table. */ +{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, +{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, +{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, +{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, +{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, +{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, +{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, +{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, +{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, +{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, +{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, +{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, +{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, +{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, +{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, +{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, +{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, +{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, +{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, +{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, +{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, +{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, +{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, +{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, +{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, +{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ueq.ps","S,T", 0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.olt.ps","S,T", 0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ult.ps","S,T", 0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ole.ps","S,T", 0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ule.ps","S,T", 0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ngle.ps","S,T", 0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.seq.ps","S,T", 0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ngl.ps","S,T", 0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.nge.ps","S,T", 0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, +{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, +{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4_32 }, +{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, +{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4_32 }, +{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33|IL2F }, +{"c.ngt.ps","S,T", 0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5_33 }, +{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, +{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +/* CW4010 instructions which are aliases for the cache instruction. */ +{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, +{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, +{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, +{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3}, +{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3}, +{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, +{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, +/* cfc2 is at the bottom of the table. */ +/* cfc3 is at the bottom of the table. */ +{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, +{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */ +{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, +{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, +/* ctc2 is at the bottom of the table. */ +/* ctc3 is at the bottom of the table. */ +{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, +{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, +{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, +{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5_33 }, +{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, +{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 }, +{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, +{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, +{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, +{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, +{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR }, +{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, +{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, +{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, +/* dctr and dctw are used on the r5000. */ +{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, +{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, +{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, +{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, +{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, +/* For ddiv, see the comments about div. */ +{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, +{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, +/* For ddivu, see the comments about div. */ +{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, +{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, +{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT}, +{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, +{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, +{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, +{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, +/* The MIPS assembler treats the div opcode with two operands as + though the first operand appeared twice (the first operand is both + a source and a destination). To get the div machine instruction, + you must use an explicit destination of $0. */ +{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, +{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, +{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +/* For divu, see the comments about div. */ +{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, +{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, +{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, +{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, +{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ +{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ +{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, +{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, +{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, +{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT }, +{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT}, +{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT}, +{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, +{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT }, +{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT}, +{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT}, +{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, +{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, +/* dmfc2 is at the bottom of the table. */ +/* dmtc2 is at the bottom of the table. */ +/* dmfc3 is at the bottom of the table. */ +/* dmtc3 is at the bottom of the table. */ +{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCT }, +{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, +{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, +{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, +{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, +{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, +{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, +{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ +{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ +{"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, +{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 }, +{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, +{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, +{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, +{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, +{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, +{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, +{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, +{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, +{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, +{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, +{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, +{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, +{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, +{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, +{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, +{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, +{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, +{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, +{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, +{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ +{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ +{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ +{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ +{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, +{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ +{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ +{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, +{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, +{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, +{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, +{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, +{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT}, +{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, +{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, +{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 }, +{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, +{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, +{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */ +{"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, +{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, +{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, +/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with + the same hazard barrier effect. */ +{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, +{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ +/* SVR4 PIC code requires special handling for j, so it must be a + macro. */ +{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, +/* This form of j is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, +{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, +{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, +/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr + with the same hazard barrier effect. */ +{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, +{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, +/* SVR4 PIC code requires special handling for jal, so it must be a + macro. */ +{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, +{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, +{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, +/* This form of jal is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 }, +{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, +{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, +{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, +{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, +/* The macro has to be first to handle o32 correctly. */ +{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, +{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, +{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ +{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, +{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, +{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, +{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4_33 }, +{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, +{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, +/* li is at the start of the table. */ +{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, +{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, +{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, +{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, +{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55}, +{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, +{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, +{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ +{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, +{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ +{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, +{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, +{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ +{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ +{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, +{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, +{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, +{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0, I4_33 }, +{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, +{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, +{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, +{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +{"madd.d", "D,S,T", 0x46200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"madd.d", "D,S,T", 0x72200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +{"madd.s", "D,S,T", 0x46000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"madd.s", "D,S,T", 0x72000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +{"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, +{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, +{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, +{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, +{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, +{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, +{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, +{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, +{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, +{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT }, +{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT}, +{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT}, +{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, +{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, +/* mfc2 is at the bottom of the table. */ +/* mfhc2 is at the bottom of the table. */ +/* mfc3 is at the bottom of the table. */ +{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, +{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, +{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, +{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, +{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t, 0, XLR }, +{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +{"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, +{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, +{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, +{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, +{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A }, +{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, +{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, +{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, +{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4_32 }, +{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4_32 }, +{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, +{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 }, +{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F }, +{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, +{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 }, +{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, +{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4_32 }, +{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5_33 }, +{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +/* move is at the top of the table. */ +{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR }, +{"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR }, +{"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR }, +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR }, +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR }, +{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +{"msub.d", "D,S,T", 0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"msub.d", "D,S,T", 0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +{"msub.s", "D,S,T", 0x46000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"msub.s", "D,S,T", 0x72000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +{"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, +{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT }, +{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT}, +{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT}, +{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, +{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, +/* mtc2 is at the bottom of the table. */ +/* mthc2 is at the bottom of the table. */ +/* mtc3 is at the bottom of the table. */ +{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, +{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, +{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, +{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, +{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_t, 0, XLR }, +{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCT }, +{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCT }, +{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCT }, +{"mtp0", "s", 0x70000009, 0xfc1fffff, RD_s, 0, IOCT }, +{"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_s, 0, IOCT }, +{"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_s, 0, IOCT }, +{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, +{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, +{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, +{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, +{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, +{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, +{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, +{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, +{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +{"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, +{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, +{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, +{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, +{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, +{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, +{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, +{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, +{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, +{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, +{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D32 }, +{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, +{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ +{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ +{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, +{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, +{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, +{"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, +{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +{"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +{"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +{"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"nmadd.ps", "D,S,T", 0x7160001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4_33 }, +{"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4_33 }, +{"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F }, +{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5_33 }, +{"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"nmsub.ps", "D,S,T", 0x7160001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F }, +/* nop is at the start of the table. */ +{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, +{"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ +{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, +{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, +{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, +{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +{"pop", "d,v", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCT }, + /* pref and prefx are at the start of the table. */ +{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33 }, +{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, +{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, +{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, +{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, +{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, +{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, +{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, +{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, +{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, +{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, +{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, +{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, +{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, +{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, +{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, +{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, +{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, +{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, +{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, +{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4_33 }, +{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4_33 }, +{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, +{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, +{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, +{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, +{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, +{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, +{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, +{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, +{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, +{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, +{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, +{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, +/* The macro has to be first to handle o32 correctly. */ +{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, +{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, +{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, +{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, +{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, +{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, +{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, +{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, +{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, +{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, +{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, +{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, +{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 }, +{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, +{"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, +{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, +{"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +{"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, +{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, +{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, +{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, +{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, +{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, +{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, +{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, +{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, +{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, +{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, +{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, +{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, +{"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ +{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, +{"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, +{"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +{"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, +{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, +{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT }, +{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, +{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, +{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ +{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, +{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ +{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, +{"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +/* ssnop is at the start of the table. */ +{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, +{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, +{"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, +{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, +{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5_33|IL2F }, +{"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, IL2E }, +{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +{"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E }, +{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A }, +{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, +{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55}, +{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, +{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, +{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, +{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ +{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, +{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, +{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ +{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, +{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, +{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ +{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ +{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 }, +{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT }, +{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT }, +{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT }, +{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT }, +{"sync_acquire", "", 0x0000044f, 0xffffffff, INSN_SYNC, 0, I33 }, +{"sync_mb", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I33 }, +{"sync_release", "", 0x0000048f, 0xffffffff, INSN_SYNC, 0, I33 }, +{"sync_rmb", "", 0x000004cf, 0xffffffff, INSN_SYNC, 0, I33 }, +{"sync_wmb", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, I33 }, +{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, +{"sync", "1", 0x0000000f, 0xfffff83f, INSN_SYNC, 0, I32 }, +{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, +{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, +{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, +{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, +{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, +{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, +{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, +{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, +{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 }, +{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 }, +{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, +{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, I1 }, +{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, +{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, +{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, +{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, +{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, +{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, +{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, +{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, +{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, +{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, +{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, +{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, +{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, +{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, +{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, +{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, +{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, +{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, +{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, +{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3_32 }, +{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, +{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, +{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, +{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, +{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, +{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, +{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, +{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, +{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, +{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, +{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, + +/* User Defined Instruction. */ +{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, + +/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format + instructions so they are here for the latters to take precedence. */ +{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, +{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, +{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT }, +{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, +{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, +{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT }, +{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, +{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, +{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, +{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, +{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, +{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, +{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, +{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, +{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, +{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, + +/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X + instructions, so they are here for the latters to take precedence. */ +{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, + + /* Conflicts with the 4650's "mul" instruction. Nobody's using the + 4010 any more, so move this insn out of the way. If the object + format gave us more info, we could do this right. */ +{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, +/* MIPS DSP ASE */ +{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, +{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, +{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, +{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, +{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, +{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, +{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, +{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, +{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, +{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, +{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, +{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, +{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, +{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, +{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, +{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, +{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, +{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, +{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, +{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, +{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, +{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, +{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, +{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, +{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, +{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, +{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, +{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, +{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, +{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, +/* MIPS DSP ASE Rev2 */ +{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, +{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, +{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, +{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, +{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +/* Move bc0* after mftr and mttr to avoid opcode collision. */ +{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +/* ST Microelectronics Loongson-2E and -2F. */ +{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, +{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, +{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A }, +{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, +{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E }, +{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A }, +{"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E }, +{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, +{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, +{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +/* No hazard protection on coprocessor instructions--they shouldn't + change the state of the processor and if they do it's up to the + user to put in nops as necessary. These are at the end so that the + disassembler recognizes more specific versions first. */ +{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 }, +{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 }, +{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 }, +{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 }, +{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, +{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 }, +{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 } +}; + +#define MIPS_NUM_OPCODES \ + ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) +const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; + +/* const removed from the following to allow for dynamic extensions to the + * built-in instruction set. */ +struct mips_opcode *mips_opcodes = + (struct mips_opcode *) mips_builtin_opcodes; +int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; +#undef MIPS_NUM_OPCODES diff --git a/external/gpl3/gdb/dist/opcodes/mips16-opc.c b/external/gpl3/gdb/dist/opcodes/mips16-opc.c new file mode 100644 index 000000000000..c42ab272f84f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mips16-opc.c @@ -0,0 +1,246 @@ +/* mips16-opc.c. Mips16 opcode table. + Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007 + Free Software Foundation, Inc. + Contributed by Ian Lance Taylor, Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/mips.h" + +/* This is the opcodes table for the mips16 processor. The format of + this table is intentionally identical to the one in mips-opc.c. + However, the special letters that appear in the argument string are + different, and the table uses some different flags. */ + +/* Use some short hand macros to keep down the length of the lines in + the opcodes table. */ + +#define UBD INSN_UNCOND_BRANCH_DELAY +#define UBR MIPS16_INSN_UNCOND_BRANCH +#define CBR MIPS16_INSN_COND_BRANCH + +#define WR_x MIPS16_INSN_WRITE_X +#define WR_y MIPS16_INSN_WRITE_Y +#define WR_z MIPS16_INSN_WRITE_Z +#define WR_T MIPS16_INSN_WRITE_T +#define WR_SP MIPS16_INSN_WRITE_SP +#define WR_31 MIPS16_INSN_WRITE_31 +#define WR_Y MIPS16_INSN_WRITE_GPR_Y + +#define RD_x MIPS16_INSN_READ_X +#define RD_y MIPS16_INSN_READ_Y +#define RD_Z MIPS16_INSN_READ_Z +#define RD_T MIPS16_INSN_READ_T +#define RD_SP MIPS16_INSN_READ_SP +#define RD_31 MIPS16_INSN_READ_31 +#define RD_PC MIPS16_INSN_READ_PC +#define RD_X MIPS16_INSN_READ_GPR_X + +#define WR_HI INSN_WRITE_HI +#define WR_LO INSN_WRITE_LO +#define RD_HI INSN_READ_HI +#define RD_LO INSN_READ_LO + +#define TRAP INSN_TRAP + +#define I1 INSN_ISA1 +#define I3 INSN_ISA3 +#define I32 INSN_ISA32 +#define I64 INSN_ISA64 +#define T3 INSN_3900 + +const struct mips_opcode mips16_opcodes[] = +{ +/* name, args, match, mask, pinfo, pinfo2, membership */ +{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1 }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, +{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 }, +{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 }, +{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1 }, +{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 }, +{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 }, +{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 }, +{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, +{"b", "q", 0x1000, 0xf800, UBR, 0, I1 }, +{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 }, +{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 }, +{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, +{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, +{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, +{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, +{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, +{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, +{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, +{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, +{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 }, +{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 }, +{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 }, +{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 }, +{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1 }, +{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, +{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, +{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 }, +{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 }, +{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 }, +{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 }, +{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 }, +{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 }, +{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 }, +{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 }, +{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 }, +{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 }, +{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 }, +{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 }, +{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 }, +{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 }, +{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1 }, +{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1 }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, +{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, +{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1 }, +{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1 }, +{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 }, +{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3 }, +{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 }, +{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, +{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 }, +{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 }, +{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 }, +{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 }, +{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 }, +{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1 }, +{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1 }, +{"extend", "e", 0xf000, 0xf800, 0, 0, I1 }, +{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1 }, +{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 }, +{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 }, +{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 }, +{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 }, +{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 }, +{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 }, +{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 }, +{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 }, +{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 }, +{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 }, +{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 }, +{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1 }, +{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1 }, +{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1 }, +{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1 }, +{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 }, +{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 }, +{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1 }, +{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1 }, +{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1 }, +{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1 }, +{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1 }, +{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, +{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1 }, +{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1 }, +{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, +{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1 }, +{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1 }, +{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1 }, +{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1 }, +{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 }, +{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 }, +{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 }, +{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 }, +{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1 }, +{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1 }, +{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1 }, +{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 }, +{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 }, +{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 }, +{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 }, +{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, + /* MIPS16e additions */ +{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, +{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, +{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 }, +{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 }, +{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 }, +{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 }, +{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 }, +{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 }, +{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64 }, +}; + +const int bfd_mips16_num_opcodes = + ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0]))); diff --git a/external/gpl3/gdb/dist/opcodes/mmix-dis.c b/external/gpl3/gdb/dist/opcodes/mmix-dis.c new file mode 100644 index 000000000000..22db268af90f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mmix-dis.c @@ -0,0 +1,518 @@ +/* mmix-dis.c -- Disassemble MMIX instructions. + Copyright 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include +#include "opcode/mmix.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "bfd.h" +#include "opintl.h" + +#define BAD_CASE(x) \ + do \ + { \ + fprintf (stderr, \ + _("Bad case %d (%s) in %s:%d\n"), \ + x, #x, __FILE__, __LINE__); \ + abort (); \ + } \ + while (0) + +#define FATAL_DEBUG \ + do \ + { \ + fprintf (stderr, \ + _("Internal: Non-debugged code (test-case missing): %s:%d"),\ + __FILE__, __LINE__); \ + abort (); \ + } \ + while (0) + +#define ROUND_MODE(n) \ + ((n) == 1 ? "ROUND_OFF" : (n) == 2 ? "ROUND_UP" : \ + (n) == 3 ? "ROUND_DOWN" : (n) == 4 ? "ROUND_NEAR" : \ + _("(unknown)")) + +#define INSN_IMMEDIATE_BIT (IMM_OFFSET_BIT << 24) +#define INSN_BACKWARD_OFFSET_BIT (1 << 24) + +struct mmix_dis_info + { + const char *reg_name[256]; + const char *spec_reg_name[32]; + + /* Waste a little memory so we don't have to allocate each separately. + We could have an array with static contents for these, but on the + other hand, we don't have to. */ + char basic_reg_name[256][sizeof ("$255")]; + }; + +/* Initialize a target-specific array in INFO. */ + +static bfd_boolean +initialize_mmix_dis_info (struct disassemble_info *info) +{ + struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info)); + long i; + + if (minfop == NULL) + return FALSE; + + memset (minfop, 0, sizeof (*minfop)); + + /* Initialize register names from register symbols. If there's no + register section, then there are no register symbols. */ + if ((info->section != NULL && info->section->owner != NULL) + || (info->symbols != NULL + && info->symbols[0] != NULL + && bfd_asymbol_bfd (info->symbols[0]) != NULL)) + { + bfd *abfd = info->section && info->section->owner != NULL + ? info->section->owner + : bfd_asymbol_bfd (info->symbols[0]); + asection *reg_section = bfd_get_section_by_name (abfd, "*REG*"); + + if (reg_section != NULL) + { + /* The returned symcount *does* include the ending NULL. */ + long symsize = bfd_get_symtab_upper_bound (abfd); + asymbol **syms = malloc (symsize); + long nsyms; + + if (syms == NULL) + { + FATAL_DEBUG; + free (minfop); + return FALSE; + } + nsyms = bfd_canonicalize_symtab (abfd, syms); + + /* We use the first name for a register. If this is MMO, then + it's the name with the first sequence number, presumably the + first in the source. */ + for (i = 0; i < nsyms && syms[i] != NULL; i++) + { + if (syms[i]->section == reg_section + && syms[i]->value < 256 + && minfop->reg_name[syms[i]->value] == NULL) + minfop->reg_name[syms[i]->value] = syms[i]->name; + } + } + } + + /* Fill in the rest with the canonical names. */ + for (i = 0; i < 256; i++) + if (minfop->reg_name[i] == NULL) + { + sprintf (minfop->basic_reg_name[i], "$%ld", i); + minfop->reg_name[i] = minfop->basic_reg_name[i]; + } + + /* We assume it's actually a one-to-one mapping of number-to-name. */ + for (i = 0; mmix_spec_regs[i].name != NULL; i++) + minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name; + + info->private_data = (void *) minfop; + return TRUE; +} + +/* A table indexed by the first byte is constructed as we disassemble each + tetrabyte. The contents is a pointer into mmix_insns reflecting the + first found entry with matching match-bits and lose-bits. Further + entries are considered one after one until the operand constraints + match or the match-bits and lose-bits do not match. Normally a + "further entry" will just show that there was no other match. */ + +static const struct mmix_opcode * +get_opcode (unsigned long insn) +{ + static const struct mmix_opcode **opcodes = NULL; + const struct mmix_opcode *opcodep = mmix_opcodes; + unsigned int opcode_part = (insn >> 24) & 255; + + if (opcodes == NULL) + opcodes = xcalloc (256, sizeof (struct mmix_opcode *)); + + opcodep = opcodes[opcode_part]; + if (opcodep == NULL + || (opcodep->match & insn) != opcodep->match + || (opcodep->lose & insn) != 0) + { + /* Search through the table. */ + for (opcodep = mmix_opcodes; opcodep->name != NULL; opcodep++) + { + /* FIXME: Break out this into an initialization function. */ + if ((opcodep->match & (opcode_part << 24)) == opcode_part + && (opcodep->lose & (opcode_part << 24)) == 0) + opcodes[opcode_part] = opcodep; + + if ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0) + break; + } + } + + if (opcodep->name == NULL) + return NULL; + + /* Check constraints. If they don't match, loop through the next opcode + entries. */ + do + { + switch (opcodep->operands) + { + /* These have no restraint on what can be in the lower three + bytes. */ + case mmix_operands_regs: + case mmix_operands_reg_yz: + case mmix_operands_regs_z_opt: + case mmix_operands_regs_z: + case mmix_operands_jmp: + case mmix_operands_pushgo: + case mmix_operands_pop: + case mmix_operands_sync: + case mmix_operands_x_regs_z: + case mmix_operands_neg: + case mmix_operands_pushj: + case mmix_operands_regaddr: + case mmix_operands_get: + case mmix_operands_set: + case mmix_operands_save: + case mmix_operands_unsave: + case mmix_operands_xyz_opt: + return opcodep; + + /* For a ROUND_MODE, the middle byte must be 0..4. */ + case mmix_operands_roundregs_z: + case mmix_operands_roundregs: + { + int midbyte = (insn >> 8) & 255; + + if (midbyte <= 4) + return opcodep; + } + break; + + case mmix_operands_put: + /* A "PUT". If it is "immediate", then no restrictions, + otherwise we have to make sure the register number is < 32. */ + if ((insn & INSN_IMMEDIATE_BIT) + || ((insn >> 16) & 255) < 32) + return opcodep; + break; + + case mmix_operands_resume: + /* Middle bytes must be zero. */ + if ((insn & 0x00ffff00) == 0) + return opcodep; + break; + + default: + BAD_CASE (opcodep->operands); + } + + opcodep++; + } + while ((opcodep->match & insn) == opcodep->match + && (opcodep->lose & insn) == 0); + + /* If we got here, we had no match. */ + return NULL; +} + +/* The main disassembly function. */ + +int +print_insn_mmix (bfd_vma memaddr, struct disassemble_info *info) +{ + unsigned char buffer[4]; + unsigned long insn; + unsigned int x, y, z; + const struct mmix_opcode *opcodep; + int status = (*info->read_memory_func) (memaddr, buffer, 4, info); + struct mmix_dis_info *minfop; + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* FIXME: Is -1 suitable? */ + if (info->private_data == NULL + && ! initialize_mmix_dis_info (info)) + return -1; + + minfop = (struct mmix_dis_info *) info->private_data; + x = buffer[1]; + y = buffer[2]; + z = buffer[3]; + + insn = bfd_getb32 (buffer); + + opcodep = get_opcode (insn); + + if (opcodep == NULL) + { + (*info->fprintf_func) (info->stream, _("*unknown*")); + return 4; + } + + (*info->fprintf_func) (info->stream, "%s ", opcodep->name); + + /* Present bytes in the order they are laid out in memory. */ + info->display_endian = BFD_ENDIAN_BIG; + + info->insn_info_valid = 1; + info->bytes_per_chunk = 4; + info->branch_delay_insns = 0; + info->target = 0; + switch (opcodep->type) + { + case mmix_type_normal: + case mmix_type_memaccess_block: + info->insn_type = dis_nonbranch; + break; + + case mmix_type_branch: + info->insn_type = dis_branch; + break; + + case mmix_type_condbranch: + info->insn_type = dis_condbranch; + break; + + case mmix_type_memaccess_octa: + info->insn_type = dis_dref; + info->data_size = 8; + break; + + case mmix_type_memaccess_tetra: + info->insn_type = dis_dref; + info->data_size = 4; + break; + + case mmix_type_memaccess_wyde: + info->insn_type = dis_dref; + info->data_size = 2; + break; + + case mmix_type_memaccess_byte: + info->insn_type = dis_dref; + info->data_size = 1; + break; + + case mmix_type_jsr: + info->insn_type = dis_jsr; + break; + + default: + BAD_CASE(opcodep->type); + } + + switch (opcodep->operands) + { + case mmix_operands_regs: + /* All registers: "$X,$Y,$Z". */ + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_reg_yz: + /* Like SETH - "$X,YZ". */ + (*info->fprintf_func) (info->stream, "%s,0x%x", + minfop->reg_name[x], y * 256 + z); + break; + + case mmix_operands_regs_z_opt: + case mmix_operands_regs_z: + case mmix_operands_pushgo: + /* The regular "$X,$Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%s,%d", + minfop->reg_name[x], minfop->reg_name[y], z); + else + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_jmp: + /* Address; only JMP. */ + { + bfd_signed_vma offset = (x * 65536 + y * 256 + z) * 4; + + if (insn & INSN_BACKWARD_OFFSET_BIT) + offset -= (256 * 65536) * 4; + + info->target = memaddr + offset; + (*info->print_address_func) (memaddr + offset, info); + } + break; + + case mmix_operands_roundregs_z: + /* Two registers, like FLOT, possibly with rounding: "$X,$Z|Z" + "$X,ROUND_MODE,$Z|Z". */ + if (y != 0) + { + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%s,%d", + minfop->reg_name[x], + ROUND_MODE (y), z); + else + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + ROUND_MODE (y), + minfop->reg_name[z]); + } + else + { + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d", + minfop->reg_name[x], z); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[z]); + } + break; + + case mmix_operands_pop: + /* Like POP - "X,YZ". */ + (*info->fprintf_func) (info->stream, "%d,%d", x, y*256 + z); + break; + + case mmix_operands_roundregs: + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + if (y != 0) + (*info->fprintf_func) (info->stream, "%s,%s,%s", + minfop->reg_name[x], + ROUND_MODE (y), + minfop->reg_name[z]); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[z]); + break; + + case mmix_operands_sync: + /* Like SYNC - "XYZ". */ + (*info->fprintf_func) (info->stream, "%u", + x * 65536 + y * 256 + z); + break; + + case mmix_operands_x_regs_z: + /* Like SYNCD - "X,$Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%d,%s,%d", + x, minfop->reg_name[y], z); + else + (*info->fprintf_func) (info->stream, "%d,%s,%s", + x, minfop->reg_name[y], + minfop->reg_name[z]); + break; + + case mmix_operands_neg: + /* Like NEG and NEGU - "$X,Y,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d,%d", + minfop->reg_name[x], y, z); + else + (*info->fprintf_func) (info->stream, "%s,%d,%s", + minfop->reg_name[x], y, + minfop->reg_name[z]); + break; + + case mmix_operands_pushj: + case mmix_operands_regaddr: + /* Like GETA or branches - "$X,Address". */ + { + bfd_signed_vma offset = (y * 256 + z) * 4; + + if (insn & INSN_BACKWARD_OFFSET_BIT) + offset -= 65536 * 4; + + info->target = memaddr + offset; + + (*info->fprintf_func) (info->stream, "%s,", minfop->reg_name[x]); + (*info->print_address_func) (memaddr + offset, info); + } + break; + + case mmix_operands_get: + /* GET - "X,spec_reg". */ + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->spec_reg_name[z]); + break; + + case mmix_operands_put: + /* PUT - "spec_reg,$Z|Z". */ + if (insn & INSN_IMMEDIATE_BIT) + (*info->fprintf_func) (info->stream, "%s,%d", + minfop->spec_reg_name[x], z); + else + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->spec_reg_name[x], + minfop->reg_name[z]); + break; + + case mmix_operands_set: + /* Two registers, "$X,$Y". */ + (*info->fprintf_func) (info->stream, "%s,%s", + minfop->reg_name[x], + minfop->reg_name[y]); + break; + + case mmix_operands_save: + /* SAVE - "$X,0". */ + (*info->fprintf_func) (info->stream, "%s,0", minfop->reg_name[x]); + break; + + case mmix_operands_unsave: + /* UNSAVE - "0,$Z". */ + (*info->fprintf_func) (info->stream, "0,%s", minfop->reg_name[z]); + break; + + case mmix_operands_xyz_opt: + /* Like SWYM or TRAP - "X,Y,Z". */ + (*info->fprintf_func) (info->stream, "%d,%d,%d", x, y, z); + break; + + case mmix_operands_resume: + /* Just "Z", like RESUME. */ + (*info->fprintf_func) (info->stream, "%d", z); + break; + + default: + (*info->fprintf_func) (info->stream, _("*unknown operands type: %d*"), + opcodep->operands); + break; + } + + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/mmix-opc.c b/external/gpl3/gdb/dist/opcodes/mmix-opc.c new file mode 100644 index 000000000000..37a28414d209 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mmix-opc.c @@ -0,0 +1,348 @@ +/* mmix-opc.c -- MMIX opcode table + Copyright (C) 2001, 2003, 2005, 2007 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "opcode/mmix.h" +#include "symcat.h" + +/* Register-name-table for special registers. */ +const struct mmix_spec_reg mmix_spec_regs[] = + { + /* Keep rJ at top; it's the most frequently used one. */ + {"rJ", 4}, + {"rA", 21}, + {"rB", 0}, + {"rC", 8}, + {"rD", 1}, + {"rE", 2}, + {"rF", 22}, + {"rG", 19}, + {"rH", 3}, + {"rI", 12}, + {"rK", 15}, + {"rL", 20}, + {"rM", 5}, + {"rN", 9}, + {"rO", 10}, + {"rP", 23}, + {"rQ", 16}, + {"rR", 6}, + {"rS", 11}, + {"rT", 13}, + {"rU", 17}, + {"rV", 18}, + {"rW", 24}, + {"rX", 25}, + {"rY", 26}, + {"rZ", 27}, + {"rBB", 7}, + {"rTT", 14}, + {"rWW", 28}, + {"rXX", 29}, + {"rYY", 30}, + {"rZZ", 31}, + {NULL, 0} + }; + +/* Opcode-table. In order to cut down on redundant contents, we use helper + macros. */ + +/* All bits in the opcode-byte are significant. Add "| ..." expressions + to add zero-bits. */ +#undef O +#define O(m) ((unsigned long) (m) << 24UL), ((~(unsigned long) (m) & 255) << 24) + +/* Bits 7..1 of the opcode are significant. */ +#undef Z +#define Z(m) ((unsigned long) (m) << 24), ((~(unsigned long) (m) & 254) << 24) + +/* For easier overview of the table. */ +#define N mmix_type_normal +#define B mmix_type_branch +#define C mmix_type_condbranch +#define MB mmix_type_memaccess_byte +#define MW mmix_type_memaccess_wyde +#define MT mmix_type_memaccess_tetra +#define MO mmix_type_memaccess_octa +#define M mmix_type_memaccess_block +#define J mmix_type_jsr +#define P mmix_type_pseudo + +#define OP(y) XCONCAT2 (mmix_operands_,y) + +/* Groups of instructions specified here must, if all are matching the + same instruction, be consecutive, in order more-specific to + less-specific match. */ + +const struct mmix_opcode mmix_opcodes[] = + { + {"trap", O (0), OP (xyz_opt), J}, + {"fcmp", O (1), OP (regs), N}, + {"flot", Z (8), OP (roundregs_z), N}, + + {"fun", O (2), OP (regs), N}, + {"feql", O (3), OP (regs), N}, + {"flotu", Z (10), OP (roundregs_z), N}, + + {"fadd", O (4), OP (regs), N}, + {"fix", O (5), OP (roundregs), N}, + {"sflot", Z (12), OP (roundregs_z), N}, + + {"fsub", O (6), OP (regs), N}, + {"fixu", O (7), OP (roundregs), N}, + {"sflotu", Z (14), OP (roundregs_z), N}, + + {"fmul", O (16), OP (regs), N}, + {"fcmpe", O (17), OP (regs), N}, + {"mul", Z (24), OP (regs_z), N}, + + {"fune", O (18), OP (regs), N}, + {"feqle", O (19), OP (regs), N}, + {"mulu", Z (26), OP (regs_z), N}, + + {"fdiv", O (20), OP (regs), N}, + {"fsqrt", O (21), OP (roundregs), N}, + {"div", Z (28), OP (regs_z), N}, + + {"frem", O (22), OP (regs), N}, + {"fint", O (23), OP (roundregs), N}, + {"divu", Z (30), OP (regs_z), N}, + + {"add", Z (0x20), OP (regs_z), N}, + {"2addu", Z (0x28), OP (regs_z), N}, + + {"addu", Z (0x22), OP (regs_z), N}, + /* Synonym for ADDU. Put after ADDU, since we don't prefer it for + disassembly. It's supposed to be used for addresses, so we make it + a memory block reference for purposes of assembly. */ + {"lda", Z (0x22), OP (regs_z_opt), M}, + {"4addu", Z (0x2a), OP (regs_z), N}, + + {"sub", Z (0x24), OP (regs_z), N}, + {"8addu", Z (0x2c), OP (regs_z), N}, + + {"subu", Z (0x26), OP (regs_z), N}, + {"16addu", Z (0x2e), OP (regs_z), N}, + + {"cmp", Z (0x30), OP (regs_z), N}, + {"sl", Z (0x38), OP (regs_z), N}, + + {"cmpu", Z (0x32), OP (regs_z), N}, + {"slu", Z (0x3a), OP (regs_z), N}, + + {"neg", Z (0x34), OP (neg), N}, + {"sr", Z (0x3c), OP (regs_z), N}, + + {"negu", Z (0x36), OP (neg), N}, + {"sru", Z (0x3e), OP (regs_z), N}, + + {"bn", Z (0x40), OP (regaddr), C}, + {"bnn", Z (0x48), OP (regaddr), C}, + + {"bz", Z (0x42), OP (regaddr), C}, + {"bnz", Z (0x4a), OP (regaddr), C}, + + {"bp", Z (0x44), OP (regaddr), C}, + {"bnp", Z (0x4c), OP (regaddr), C}, + + {"bod", Z (0x46), OP (regaddr), C}, + {"bev", Z (0x4e), OP (regaddr), C}, + + {"pbn", Z (0x50), OP (regaddr), C}, + {"pbnn", Z (0x58), OP (regaddr), C}, + + {"pbz", Z (0x52), OP (regaddr), C}, + {"pbnz", Z (0x5a), OP (regaddr), C}, + + {"pbp", Z (0x54), OP (regaddr), C}, + {"pbnp", Z (0x5c), OP (regaddr), C}, + + {"pbod", Z (0x56), OP (regaddr), C}, + {"pbev", Z (0x5e), OP (regaddr), C}, + + {"csn", Z (0x60), OP (regs_z), N}, + {"csnn", Z (0x68), OP (regs_z), N}, + + {"csz", Z (0x62), OP (regs_z), N}, + {"csnz", Z (0x6a), OP (regs_z), N}, + + {"csp", Z (0x64), OP (regs_z), N}, + {"csnp", Z (0x6c), OP (regs_z), N}, + + {"csod", Z (0x66), OP (regs_z), N}, + {"csev", Z (0x6e), OP (regs_z), N}, + + {"zsn", Z (0x70), OP (regs_z), N}, + {"zsnn", Z (0x78), OP (regs_z), N}, + + {"zsz", Z (0x72), OP (regs_z), N}, + {"zsnz", Z (0x7a), OP (regs_z), N}, + + {"zsp", Z (0x74), OP (regs_z), N}, + {"zsnp", Z (0x7c), OP (regs_z), N}, + + {"zsod", Z (0x76), OP (regs_z), N}, + {"zsev", Z (0x7e), OP (regs_z), N}, + + {"ldb", Z (0x80), OP (regs_z_opt), MB}, + {"ldt", Z (0x88), OP (regs_z_opt), MT}, + + {"ldbu", Z (0x82), OP (regs_z_opt), MB}, + {"ldtu", Z (0x8a), OP (regs_z_opt), MT}, + + {"ldw", Z (0x84), OP (regs_z_opt), MW}, + {"ldo", Z (0x8c), OP (regs_z_opt), MO}, + + {"ldwu", Z (0x86), OP (regs_z_opt), MW}, + {"ldou", Z (0x8e), OP (regs_z_opt), MO}, + + {"ldsf", Z (0x90), OP (regs_z_opt), MT}, + + /* This doesn't seem to access memory, just the TLB. */ + {"ldvts", Z (0x98), OP (regs_z_opt), M}, + + {"ldht", Z (0x92), OP (regs_z_opt), MT}, + + /* Neither does this per-se. */ + {"preld", Z (0x9a), OP (x_regs_z), N}, + + {"cswap", Z (0x94), OP (regs_z_opt), MO}, + {"prego", Z (0x9c), OP (x_regs_z), N}, + + {"ldunc", Z (0x96), OP (regs_z_opt), MO}, + {"go", Z (GO_INSN_BYTE), + OP (regs_z_opt), B}, + + {"stb", Z (0xa0), OP (regs_z_opt), MB}, + {"stt", Z (0xa8), OP (regs_z_opt), MT}, + + {"stbu", Z (0xa2), OP (regs_z_opt), MB}, + {"sttu", Z (0xaa), OP (regs_z_opt), MT}, + + {"stw", Z (0xa4), OP (regs_z_opt), MW}, + {"sto", Z (0xac), OP (regs_z_opt), MO}, + + {"stwu", Z (0xa6), OP (regs_z_opt), MW}, + {"stou", Z (0xae), OP (regs_z_opt), MO}, + + {"stsf", Z (0xb0), OP (regs_z_opt), MT}, + {"syncd", Z (0xb8), OP (x_regs_z), M}, + + {"stht", Z (0xb2), OP (regs_z_opt), MT}, + {"prest", Z (0xba), OP (x_regs_z), M}, + + {"stco", Z (0xb4), OP (x_regs_z), MO}, + {"syncid", Z (0xbc), OP (x_regs_z), M}, + + {"stunc", Z (0xb6), OP (regs_z_opt), MO}, + {"pushgo", Z (PUSHGO_INSN_BYTE), + OP (pushgo), J}, + + /* Synonym for OR with a zero Z. */ + {"set", O (0xc1) + | 0xff, OP (set), N}, + + {"or", Z (0xc0), OP (regs_z), N}, + {"and", Z (0xc8), OP (regs_z), N}, + + {"orn", Z (0xc2), OP (regs_z), N}, + {"andn", Z (0xca), OP (regs_z), N}, + + {"nor", Z (0xc4), OP (regs_z), N}, + {"nand", Z (0xcc), OP (regs_z), N}, + + {"xor", Z (0xc6), OP (regs_z), N}, + {"nxor", Z (0xce), OP (regs_z), N}, + + {"bdif", Z (0xd0), OP (regs_z), N}, + {"mux", Z (0xd8), OP (regs_z), N}, + + {"wdif", Z (0xd2), OP (regs_z), N}, + {"sadd", Z (0xda), OP (regs_z), N}, + + {"tdif", Z (0xd4), OP (regs_z), N}, + {"mor", Z (0xdc), OP (regs_z), N}, + + {"odif", Z (0xd6), OP (regs_z), N}, + {"mxor", Z (0xde), OP (regs_z), N}, + + {"seth", O (0xe0), OP (reg_yz), N}, + {"setmh", O (0xe1), OP (reg_yz), N}, + {"orh", O (0xe8), OP (reg_yz), N}, + {"ormh", O (0xe9), OP (reg_yz), N}, + + {"setml", O (0xe2), OP (reg_yz), N}, + {"setl", O (SETL_INSN_BYTE), + OP (reg_yz), N}, + {"orml", O (0xea), OP (reg_yz), N}, + {"orl", O (0xeb), OP (reg_yz), N}, + + {"inch", O (INCH_INSN_BYTE), + OP (reg_yz), N}, + {"incmh", O (INCMH_INSN_BYTE), + OP (reg_yz), N}, + {"andnh", O (0xec), OP (reg_yz), N}, + {"andnmh", O (0xed), OP (reg_yz), N}, + + {"incml", O (INCML_INSN_BYTE), + OP (reg_yz), N}, + {"incl", O (0xe7), OP (reg_yz), N}, + {"andnml", O (0xee), OP (reg_yz), N}, + {"andnl", O (0xef), OP (reg_yz), N}, + + {"jmp", Z (0xf0), OP (jmp), B}, + {"pop", O (0xf8), OP (pop), B}, + {"resume", O (0xf9) + | 0xffff00, OP (resume), B}, + + {"pushj", Z (0xf2), OP (pushj), J}, + {"save", O (0xfa) + | 0xffff, OP (save), M}, + {"unsave", O (0xfb) + | 0xffff00, OP (unsave), M}, + + {"geta", Z (0xf4), OP (regaddr), N}, + {"sync", O (0xfc), OP (sync), N}, + {"swym", O (SWYM_INSN_BYTE), + OP (xyz_opt), N}, + + {"put", Z (0xf6) | 0xff00, OP (put), N}, + {"get", O (0xfe) | 0xffe0, OP (get), N}, + {"trip", O (0xff), OP (xyz_opt), J}, + + /* We have mmixal pseudos in the ordinary instruction table so we can + avoid the "set" vs. ".set" ambiguity that would be the effect if we + had pseudos handled "normally" and defined NO_PSEUDO_DOT. + + Note that IS and GREG are handled fully by md_start_line_hook, so + they're not here. */ + {"loc", ~0, ~0, OP (loc), P}, + {"prefix", ~0, ~0, OP (prefix), P}, + {"byte", ~0, ~0, OP (byte), P}, + {"wyde", ~0, ~0, OP (wyde), P}, + {"tetra", ~0, ~0, OP (tetra), P}, + {"octa", ~0, ~0, OP (octa), P}, + {"local", ~0, ~0, OP (local), P}, + {"bspec", ~0, ~0, OP (bspec), P}, + {"espec", ~0, ~0, OP (espec), P}, + + {NULL, ~0, ~0, OP (none), N} + }; diff --git a/external/gpl3/gdb/dist/opcodes/moxie-dis.c b/external/gpl3/gdb/dist/opcodes/moxie-dis.c new file mode 100644 index 000000000000..4e67e2c55514 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/moxie-dis.c @@ -0,0 +1,198 @@ +/* Disassemble moxie instructions. + Copyright 2009 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "opcode/moxie.h" +#include "dis-asm.h" + +static fprintf_ftype fpr; +static void *stream; + +/* Macros to extract operands from the instruction word. */ +#define OP_A(i) ((i >> 4) & 0xf) +#define OP_B(i) (i & 0xf) +#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1) + +static const char * reg_names[16] = + { "$fp", "$sp", "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", + "$r6", "$r7", "$r8", "$r9", "$r10", "$r11", "$r12", "$r13" }; + +int +print_insn_moxie (bfd_vma addr, struct disassemble_info * info) +{ + int length = 2; + int status; + stream = info->stream; + const moxie_opc_info_t * opcode; + bfd_byte buffer[4]; + unsigned short iword; + fpr = info->fprintf_func; + + if ((status = info->read_memory_func (addr, buffer, 2, info))) + goto fail; + iword = bfd_getb16 (buffer); + + /* Form 1 instructions have the high bit set to 0. */ + if ((iword & (1<<15)) == 0) + { + /* Extract the Form 1 opcode. */ + opcode = &moxie_form1_opc_info[iword >> 8]; + switch (opcode->itype) + { + case MOXIE_F1_NARG: + fpr (stream, "%s", opcode->name); + break; + case MOXIE_F1_A: + fpr (stream, "%s\t%s", opcode->name, + reg_names[OP_A(iword)]); + break; + case MOXIE_F1_AB: + fpr (stream, "%s\t%s, %s", opcode->name, + reg_names[OP_A(iword)], + reg_names[OP_B(iword)]); + break; + case MOXIE_F1_A4: + { + unsigned imm; + if ((status = info->read_memory_func (addr + 2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t%s, 0x%x", opcode->name, + reg_names[OP_A(iword)], imm); + length = 6; + } + break; + case MOXIE_F1_4: + { + unsigned imm; + if ((status = info->read_memory_func (addr + 2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t0x%x", opcode->name, imm); + length = 6; + } + break; + case MOXIE_F1_M: + { + unsigned imm; + if ((status = info->read_memory_func (addr + 2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t", opcode->name); + info->print_address_func ((bfd_vma) imm, info); + length = 6; + } + break; + case MOXIE_F1_AiB: + fpr (stream, "%s\t(%s), %s", opcode->name, + reg_names[OP_A(iword)], reg_names[OP_B(iword)]); + break; + case MOXIE_F1_ABi: + fpr (stream, "%s\t%s, (%s)", opcode->name, + reg_names[OP_A(iword)], reg_names[OP_B(iword)]); + break; + case MOXIE_F1_4A: + { + unsigned imm; + if ((status = info->read_memory_func (addr + 2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t0x%x, %s", + opcode->name, imm, reg_names[OP_A(iword)]); + length = 6; + } + break; + case MOXIE_F1_AiB4: + { + unsigned imm; + if ((status = info->read_memory_func (addr+2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t0x%x(%s), %s", opcode->name, + imm, + reg_names[OP_A(iword)], + reg_names[OP_B(iword)]); + length = 6; + } + break; + case MOXIE_F1_ABi4: + { + unsigned imm; + if ((status = info->read_memory_func (addr+2, buffer, 4, info))) + goto fail; + imm = bfd_getb32 (buffer); + fpr (stream, "%s\t%s, 0x%x(%s)", + opcode->name, + reg_names[OP_A(iword)], + imm, + reg_names[OP_B(iword)]); + length = 6; + } + break; + default: + abort (); + } + } + else if ((iword & (1<<14)) == 0) + { + /* Extract the Form 2 opcode. */ + opcode = &moxie_form2_opc_info[(iword >> 12) & 3]; + switch (opcode->itype) + { + case MOXIE_F2_A8V: + fpr (stream, "%s\t%s, 0x%x", + opcode->name, + reg_names[(iword >> 8) & 0xf], + iword & ((1 << 8) - 1)); + break; + case MOXIE_F2_NARG: + fpr (stream, "%s", opcode->name); + break; + default: + abort(); + } + } + else + { + /* Extract the Form 3 opcode. */ + opcode = &moxie_form3_opc_info[(iword >> 10) & 15]; + switch (opcode->itype) + { + case MOXIE_F3_PCREL: + fpr (stream, "%s\t", opcode->name); + info->print_address_func ((bfd_vma) (addr + INST2OFFSET(iword)), + info); + break; + default: + abort(); + } + } + + return length; + + fail: + info->memory_error_func (status, addr, info); + return -1; +} diff --git a/external/gpl3/gdb/dist/opcodes/moxie-opc.c b/external/gpl3/gdb/dist/opcodes/moxie-opc.c new file mode 100644 index 000000000000..b493d1fb36f4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/moxie-opc.c @@ -0,0 +1,152 @@ +/* moxie-opc.c -- Definitions for moxie opcodes. + Copyright 2009 Free Software Foundation, Inc. + Contributed by Anthony Green (green@moxielogic.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "opcode/moxie.h" + +/* The moxie processor's 16-bit instructions come in two forms: + + FORM 1 instructions start with a 0 bit... + + 0oooooooaaaabbbb + 0 F + + ooooooo - form 1 opcode number + aaaa - operand A + bbbb - operand B + + FORM 2 instructions start with bits "10"... + + 10ooaaaavvvvvvvv + 0 F + + oo - form 2 opcode number + aaaa - operand A + vvvvvvvv - 8-bit immediate value + + FORM 3 instructions start with a bits "11"... + + 11oooovvvvvvvvvv + 0 F + + oooo - form 3 opcode number + vvvvvvvvvv - 10-bit immediate value. */ + +/* Note that currently two opcodes are reserved as bad, so that all + instructions starting with 0x00 and 0xff fault. */ + +const moxie_opc_info_t moxie_form1_opc_info[64] = + { + { 0x00, MOXIE_F1_NARG, "bad" }, // Reserved as bad. + { 0x01, MOXIE_F1_A4, "ldi.l" }, + { 0x02, MOXIE_F1_AB, "mov" }, + { 0x03, MOXIE_F1_M, "jsra" }, + { 0x04, MOXIE_F1_NARG, "ret" }, + { 0x05, MOXIE_F1_AB, "add.l" }, + { 0x06, MOXIE_F1_AB, "push" }, + { 0x07, MOXIE_F1_AB, "pop" }, + { 0x08, MOXIE_F1_A4, "lda.l" }, + { 0x09, MOXIE_F1_4A, "sta.l" }, + { 0x0a, MOXIE_F1_ABi, "ld.l" }, + { 0x0b, MOXIE_F1_AiB, "st.l" }, + { 0x0c, MOXIE_F1_ABi4, "ldo.l" }, + { 0x0d, MOXIE_F1_AiB4, "sto.l" }, + { 0x0e, MOXIE_F1_AB, "cmp" }, + { 0x0f, MOXIE_F1_NARG, "nop" }, + { 0x10, MOXIE_F1_NARG, "bad" }, + { 0x11, MOXIE_F1_NARG, "bad" }, + { 0x12, MOXIE_F1_NARG, "bad" }, + { 0x13, MOXIE_F1_NARG, "bad" }, + { 0x14, MOXIE_F1_NARG, "bad" }, + { 0x15, MOXIE_F1_NARG, "bad" }, + { 0x16, MOXIE_F1_NARG, "bad" }, + { 0x17, MOXIE_F1_NARG, "bad" }, + { 0x18, MOXIE_F1_NARG, "bad" }, + { 0x19, MOXIE_F1_A, "jsr" }, + { 0x1a, MOXIE_F1_M, "jmpa" }, + { 0x1b, MOXIE_F1_A4, "ldi.b" }, + { 0x1c, MOXIE_F1_ABi, "ld.b" }, + { 0x1d, MOXIE_F1_A4, "lda.b" }, + { 0x1e, MOXIE_F1_AiB, "st.b" }, + { 0x1f, MOXIE_F1_4A, "sta.b" }, + { 0x20, MOXIE_F1_A4, "ldi.s" }, + { 0x21, MOXIE_F1_ABi, "ld.s" }, + { 0x22, MOXIE_F1_A4, "lda.s" }, + { 0x23, MOXIE_F1_AiB, "st.s" }, + { 0x24, MOXIE_F1_4A, "sta.s" }, + { 0x25, MOXIE_F1_A, "jmp" }, + { 0x26, MOXIE_F1_AB, "and" }, + { 0x27, MOXIE_F1_AB, "lshr" }, + { 0x28, MOXIE_F1_AB, "ashl" }, + { 0x29, MOXIE_F1_AB, "sub.l" }, + { 0x2a, MOXIE_F1_AB, "neg" }, + { 0x2b, MOXIE_F1_AB, "or" }, + { 0x2c, MOXIE_F1_AB, "not" }, + { 0x2d, MOXIE_F1_AB, "ashr" }, + { 0x2e, MOXIE_F1_AB, "xor" }, + { 0x2f, MOXIE_F1_AB, "mul.l" }, + { 0x30, MOXIE_F1_4, "swi" }, + { 0x31, MOXIE_F1_AB, "div.l" }, + { 0x32, MOXIE_F1_AB, "udiv.l" }, + { 0x33, MOXIE_F1_AB, "mod.l" }, + { 0x34, MOXIE_F1_AB, "umod.l" }, + { 0x35, MOXIE_F1_NARG, "brk" }, + { 0x36, MOXIE_F1_ABi4, "ldo.b" }, + { 0x37, MOXIE_F1_AiB4, "sto.b" }, + { 0x38, MOXIE_F1_ABi4, "ldo.s" }, + { 0x39, MOXIE_F1_AiB4, "sto.s" }, + { 0x3a, MOXIE_F1_NARG, "bad" }, + { 0x3b, MOXIE_F1_NARG, "bad" }, + { 0x3c, MOXIE_F1_NARG, "bad" }, + { 0x3d, MOXIE_F1_NARG, "bad" }, + { 0x3e, MOXIE_F1_NARG, "bad" }, + { 0x3f, MOXIE_F1_NARG, "bad" } + }; + +const moxie_opc_info_t moxie_form2_opc_info[4] = + { + { 0x00, MOXIE_F2_A8V, "inc" }, + { 0x01, MOXIE_F2_A8V, "dec" }, + { 0x02, MOXIE_F2_A8V, "gsr" }, + { 0x03, MOXIE_F2_A8V, "ssr" } + }; + +const moxie_opc_info_t moxie_form3_opc_info[16] = + { + { 0x00, MOXIE_F3_PCREL,"beq" }, + { 0x01, MOXIE_F3_PCREL,"bne" }, + { 0x02, MOXIE_F3_PCREL,"blt" }, + { 0x03, MOXIE_F3_PCREL,"bgt" }, + { 0x04, MOXIE_F3_PCREL,"bltu" }, + { 0x05, MOXIE_F3_PCREL,"bgtu" }, + { 0x06, MOXIE_F3_PCREL,"bge" }, + { 0x07, MOXIE_F3_PCREL,"ble" }, + { 0x08, MOXIE_F3_PCREL,"bgeu" }, + { 0x09, MOXIE_F3_PCREL,"bleu" }, + { 0x0a, MOXIE_F3_NARG, "bad" }, + { 0x0b, MOXIE_F3_NARG, "bad" }, + { 0x0c, MOXIE_F3_NARG, "bad" }, + { 0x0d, MOXIE_F3_NARG, "bad" }, + { 0x0e, MOXIE_F3_NARG, "bad" }, + { 0x0f, MOXIE_F3_NARG, "bad" } // Reserved as bad. + }; + + diff --git a/external/gpl3/gdb/dist/opcodes/msp430-dis.c b/external/gpl3/gdb/dist/opcodes/msp430-dis.c new file mode 100644 index 000000000000..9d7edbeb9039 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/msp430-dis.c @@ -0,0 +1,787 @@ +/* Disassemble MSP430 instructions. + Copyright (C) 2002, 2004, 2005, 2007, 2009, 2010 + Free Software Foundation, Inc. + + Contributed by Dmitry Diky + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include +#include + +#include "dis-asm.h" +#include "opintl.h" +#include "libiberty.h" + +#define DASM_SECTION +#include "opcode/msp430.h" +#undef DASM_SECTION + + +#define PS(x) (0xffff & (x)) + +static unsigned short +msp430dis_opcode (bfd_vma addr, disassemble_info *info) +{ + bfd_byte buffer[2]; + int status; + + status = info->read_memory_func (addr, buffer, 2, info); + if (status != 0) + { + info->memory_error_func (status, addr, info); + return -1; + } + return bfd_getl16 (buffer); +} + +static int +msp430_nooperands (struct msp430_opcode_s *opcode, + bfd_vma addr ATTRIBUTE_UNUSED, + unsigned short insn ATTRIBUTE_UNUSED, + char *comm, + int *cycles) +{ + /* Pop with constant. */ + if (insn == 0x43b2) + return 0; + if (insn == opcode->bin_opcode) + return 2; + + if (opcode->fmt == 0) + { + if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2) + return 0; + + strcpy (comm, "emulated..."); + *cycles = 1; + } + else + { + strcpy (comm, "return from interupt"); + *cycles = 5; + } + + return 2; +} + +static int +msp430_singleoperand (disassemble_info *info, + struct msp430_opcode_s *opcode, + bfd_vma addr, + unsigned short insn, + char *op, + char *comm, + int *cycles) +{ + int regs = 0, regd = 0; + int ad = 0, as = 0; + int where = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + ad = (insn & 0x0080) >> 7; + + switch (opcode->fmt) + { + case 0: /* Emulated work with dst register. */ + if (regs != 2 && regs != 3 && regs != 1) + return 0; + + /* Check if not clr insn. */ + if (opcode->bin_opcode == 0x4300 && (ad || as)) + return 0; + + /* Check if really inc, incd insns. */ + if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3) + return 0; + + if (ad == 0) + { + *cycles = 1; + + /* Register. */ + if (regd == 0) + { + *cycles += 1; + sprintf (op, "r0"); + } + else if (regd == 1) + sprintf (op, "r1"); + + else if (regd == 2) + sprintf (op, "r2"); + + else + sprintf (op, "r%d", regd); + } + else /* ad == 1 msp430dis_opcode. */ + { + if (regd == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "0x%04x", dst); + sprintf (comm, "PC rel. abs addr 0x%04x", + PS ((short) (addr + 2) + dst)); + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "&0x%04x", PS (dst)); + } + else + { + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + *cycles = 4; + sprintf (op, "%d(r%d)", dst, regd); + } + } + break; + + case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */ + if (as == 0) + { + if (regd == 3) + { + /* Constsnts. */ + sprintf (op, "#0"); + sprintf (comm, "r3 As==00"); + } + else + { + /* Register. */ + sprintf (op, "r%d", regd); + } + *cycles = 1; + } + else if (as == 2) + { + *cycles = 1; + if (regd == 2) + { + sprintf (op, "#4"); + sprintf (comm, "r2 As==10"); + } + else if (regd == 3) + { + sprintf (op, "#2"); + sprintf (comm, "r3 As==10"); + } + else + { + *cycles = 3; + /* Indexed register mode @Rn. */ + sprintf (op, "@r%d", regd); + } + } + else if (as == 3) + { + *cycles = 1; + if (regd == 2) + { + sprintf (op, "#8"); + sprintf (comm, "r2 As==11"); + } + else if (regd == 3) + { + sprintf (op, "#-1"); + sprintf (comm, "r3 As==11"); + } + else if (regd == 0) + { + *cycles = 3; + /* absolute. @pc+ */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "#%d", dst); + sprintf (comm, "#0x%04x", PS (dst)); + } + else + { + *cycles = 3; + sprintf (op, "@r%d+", regd); + } + } + else if (as == 1) + { + *cycles = 4; + if (regd == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "0x%04x", PS (dst)); + sprintf (comm, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "&0x%04x", PS (dst)); + } + else if (regd == 3) + { + *cycles = 1; + sprintf (op, "#1"); + sprintf (comm, "r3 As==01"); + } + else + { + /* Indexd. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op, "%d(r%d)", dst, regd); + } + } + break; + + case 3: /* Jumps. */ + where = insn & 0x03ff; + if (where & 0x200) + where |= ~0x03ff; + if (where > 512 || where < -511) + return 0; + + where *= 2; + sprintf (op, "$%+-8d", where + 2); + sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + where)); + *cycles = 2; + return 2; + break; + default: + cmd_len = 0; + } + + return cmd_len; +} + +static int +msp430_doubleoperand (disassemble_info *info, + struct msp430_opcode_s *opcode, + bfd_vma addr, + unsigned short insn, + char *op1, + char *op2, + char *comm1, + char *comm2, + int *cycles) +{ + int regs = 0, regd = 0; + int ad = 0, as = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + ad = (insn & 0x0080) >> 7; + + if (opcode->fmt == 0) + { + /* Special case: rla and rlc are the only 2 emulated instructions that + fall into two operand instructions. */ + /* With dst, there are only: + Rm Register, + x(Rm) Indexed, + 0xXXXX Relative, + &0xXXXX Absolute + emulated_ins dst + basic_ins dst, dst. */ + + if (regd != regs || as != ad) + return 0; /* May be 'data' section. */ + + if (ad == 0) + { + /* Register mode. */ + if (regd == 3) + { + strcpy (comm1, _("Illegal as emulation instr")); + return -1; + } + + sprintf (op1, "r%d", regd); + *cycles = 1; + } + else /* ad == 1 */ + { + if (regd == 0) + { + /* PC relative, Symbolic. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 4; + *cycles = 6; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + /* If the 'src' field is not the same as the dst + then this is not an rla instruction. */ + if (dst != msp430dis_opcode (addr + 4, info)) + return 0; + cmd_len += 4; + *cycles = 6; + sprintf (op1, "&0x%04x", PS (dst)); + } + else + { + /* Indexed. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 4; + *cycles = 6; + sprintf (op1, "%d(r%d)", dst, regd); + } + } + + *op2 = 0; + *comm2 = 0; + return cmd_len; + } + + /* Two operands exactly. */ + if (ad == 0 && regd == 3) + { + /* R2/R3 are illegal as dest: may be data section. */ + strcpy (comm1, _("Illegal as 2-op instr")); + return -1; + } + + /* Source. */ + if (as == 0) + { + *cycles = 1; + if (regs == 3) + { + /* Constsnts. */ + sprintf (op1, "#0"); + sprintf (comm1, "r3 As==00"); + } + else + { + /* Register. */ + sprintf (op1, "r%d", regs); + } + } + else if (as == 2) + { + *cycles = 1; + + if (regs == 2) + { + sprintf (op1, "#4"); + sprintf (comm1, "r2 As==10"); + } + else if (regs == 3) + { + sprintf (op1, "#2"); + sprintf (comm1, "r3 As==10"); + } + else + { + *cycles = 2; + + /* Indexed register mode @Rn. */ + sprintf (op1, "@r%d", regs); + } + if (!regs) + *cycles = 3; + } + else if (as == 3) + { + if (regs == 2) + { + sprintf (op1, "#8"); + sprintf (comm1, "r2 As==11"); + *cycles = 1; + } + else if (regs == 3) + { + sprintf (op1, "#-1"); + sprintf (comm1, "r3 As==11"); + *cycles = 1; + } + else if (regs == 0) + { + *cycles = 3; + /* Absolute. @pc+. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "#%d", dst); + sprintf (comm1, "#0x%04x", PS (dst)); + } + else + { + *cycles = 2; + sprintf (op1, "@r%d+", regs); + } + } + else if (as == 1) + { + if (regs == 0) + { + *cycles = 4; + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regs == 2) + { + *cycles = 2; + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "&0x%04x", PS (dst)); + sprintf (comm1, "0x%04x", PS (dst)); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#1"); + sprintf (comm1, "r3 As==01"); + } + else + { + *cycles = 3; + /* Indexed. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "%d(r%d)", dst, regs); + } + } + + /* Destination. Special care needed on addr + XXXX. */ + + if (ad == 0) + { + /* Register. */ + if (regd == 0) + { + *cycles += 1; + sprintf (op2, "r0"); + } + else if (regd == 1) + sprintf (op2, "r1"); + + else if (regd == 2) + sprintf (op2, "r2"); + + else + sprintf (op2, "r%d", regd); + } + else /* ad == 1. */ + { + * cycles += 3; + + if (regd == 0) + { + /* PC relative. */ + *cycles += 1; + dst = msp430dis_opcode (addr + cmd_len, info); + sprintf (op2, "0x%04x", PS (dst)); + sprintf (comm2, "PC rel. 0x%04x", + PS ((short) addr + cmd_len + dst)); + cmd_len += 2; + } + else if (regd == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + cmd_len, info); + cmd_len += 2; + sprintf (op2, "&0x%04x", PS (dst)); + } + else + { + dst = msp430dis_opcode (addr + cmd_len, info); + cmd_len += 2; + sprintf (op2, "%d(r%d)", dst, regd); + } + } + + return cmd_len; +} + +static int +msp430_branchinstr (disassemble_info *info, + struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED, + bfd_vma addr ATTRIBUTE_UNUSED, + unsigned short insn, + char *op1, + char *comm1, + int *cycles) +{ + int regs = 0, regd = 0; + int as = 0; + int cmd_len = 2; + short dst = 0; + + regd = insn & 0x0f; + regs = (insn & 0x0f00) >> 8; + as = (insn & 0x0030) >> 4; + + if (regd != 0) /* Destination register is not a PC. */ + return 0; + + /* dst is a source register. */ + if (as == 0) + { + /* Constants. */ + if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#0"); + sprintf (comm1, "r3 As==00"); + } + else + { + /* Register. */ + *cycles = 1; + sprintf (op1, "r%d", regs); + } + } + else if (as == 2) + { + if (regs == 2) + { + *cycles = 2; + sprintf (op1, "#4"); + sprintf (comm1, "r2 As==10"); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#2"); + sprintf (comm1, "r3 As==10"); + } + else + { + /* Indexed register mode @Rn. */ + *cycles = 2; + sprintf (op1, "@r%d", regs); + } + } + else if (as == 3) + { + if (regs == 2) + { + *cycles = 1; + sprintf (op1, "#8"); + sprintf (comm1, "r2 As==11"); + } + else if (regs == 3) + { + *cycles = 1; + sprintf (op1, "#-1"); + sprintf (comm1, "r3 As==11"); + } + else if (regs == 0) + { + /* Absolute. @pc+ */ + *cycles = 3; + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "#0x%04x", PS (dst)); + } + else + { + *cycles = 2; + sprintf (op1, "@r%d+", regs); + } + } + else if (as == 1) + { + * cycles = 3; + + if (regs == 0) + { + /* PC relative. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + (*cycles)++; + sprintf (op1, "0x%04x", PS (dst)); + sprintf (comm1, "PC rel. 0x%04x", + PS ((short) addr + 2 + dst)); + } + else if (regs == 2) + { + /* Absolute. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "&0x%04x", PS (dst)); + } + else if (regs == 3) + { + (*cycles)--; + sprintf (op1, "#1"); + sprintf (comm1, "r3 As==01"); + } + else + { + /* Indexd. */ + dst = msp430dis_opcode (addr + 2, info); + cmd_len += 2; + sprintf (op1, "%d(r%d)", dst, regs); + } + } + + return cmd_len; +} + +int +print_insn_msp430 (bfd_vma addr, disassemble_info *info) +{ + void *stream = info->stream; + fprintf_ftype prin = info->fprintf_func; + struct msp430_opcode_s *opcode; + char op1[32], op2[32], comm1[64], comm2[64]; + int cmd_len = 0; + unsigned short insn; + int cycles = 0; + char *bc = ""; + char dinfo[32]; /* Debug purposes. */ + + insn = msp430dis_opcode (addr, info); + sprintf (dinfo, "0x%04x", insn); + + if (((int) addr & 0xffff) > 0xffdf) + { + (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn); + return 2; + } + + *comm1 = 0; + *comm2 = 0; + + for (opcode = msp430_opcodes; opcode->name; opcode++) + { + if ((insn & opcode->bin_mask) == opcode->bin_opcode + && opcode->bin_opcode != 0x9300) + { + *op1 = 0; + *op2 = 0; + *comm1 = 0; + *comm2 = 0; + + /* r0 as destination. Ad should be zero. */ + if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0 + && (0x0080 & insn) == 0) + { + cmd_len = + msp430_branchinstr (info, opcode, addr, insn, op1, comm1, + &cycles); + if (cmd_len) + break; + } + + switch (opcode->insn_opnumb) + { + case 0: + cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles); + break; + case 2: + cmd_len = + msp430_doubleoperand (info, opcode, addr, insn, op1, op2, + comm1, comm2, &cycles); + if (insn & BYTE_OPERATION) + bc = ".b"; + break; + case 1: + cmd_len = + msp430_singleoperand (info, opcode, addr, insn, op1, comm1, + &cycles); + if (insn & BYTE_OPERATION && opcode->fmt != 3) + bc = ".b"; + break; + default: + break; + } + } + + if (cmd_len) + break; + } + + dinfo[5] = 0; + + if (cmd_len < 1) + { + /* Unknown opcode, or invalid combination of operands. */ + (*prin) (stream, ".word 0x%04x; ????", PS (insn)); + return 2; + } + + (*prin) (stream, "%s%s", opcode->name, bc); + + if (*op1) + (*prin) (stream, "\t%s", op1); + if (*op2) + (*prin) (stream, ","); + + if (strlen (op1) < 7) + (*prin) (stream, "\t"); + if (!strlen (op1)) + (*prin) (stream, "\t"); + + if (*op2) + (*prin) (stream, "%s", op2); + if (strlen (op2) < 8) + (*prin) (stream, "\t"); + + if (*comm1 || *comm2) + (*prin) (stream, ";"); + else if (cycles) + { + if (*op2) + (*prin) (stream, ";"); + else + { + if (strlen (op1) < 7) + (*prin) (stream, ";"); + else + (*prin) (stream, "\t;"); + } + } + if (*comm1) + (*prin) (stream, "%s", comm1); + if (*comm1 && *comm2) + (*prin) (stream, ","); + if (*comm2) + (*prin) (stream, " %s", comm2); + return cmd_len; +} diff --git a/external/gpl3/gdb/dist/opcodes/mt-asm.c b/external/gpl3/gdb/dist/opcodes/mt-asm.c new file mode 100644 index 000000000000..8dbbabf3fd9e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-asm.c @@ -0,0 +1,1003 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mt-desc.h" +#include "mt-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +/* Range checking for signed numbers. Returns 0 if acceptable + and 1 if the value is out of bounds for a signed quantity. */ + +static int +signed_out_of_bounds (long val) +{ + if ((val < -32768) || (val > 32767)) + return 1; + return 0; +} + +static const char * +parse_loopsize (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + void *arg) +{ + signed long * valuep = (signed long *) arg; + const char *errmsg; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Is it a control transfer instructions? */ + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE) + { + code = BFD_RELOC_MT_PCINSN8; + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + *valuep = value; + return errmsg; + } + + abort (); +} + +static const char * +parse_imm16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + void *arg) +{ + signed long * valuep = (signed long *) arg; + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + /* Is it a control transfer instructions? */ + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O) + { + code = BFD_RELOC_16_PCREL; + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + if (signed_out_of_bounds (value)) + errmsg = _("Operand out of range. Must be between -32768 and 32767."); + } + *valuep = value; + return errmsg; + } + + /* If it's not a control transfer instruction, then + we have to check for %OP relocating operators. */ + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L) + ; + else if (strncmp (*strp, "%hi16", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_HI16; + } + else if (strncmp (*strp, "%lo16", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_LO16; + } + + /* If we found a %OP relocating operator, then parse it as an address. + If not, we need to parse it as an integer, either signed or unsigned + depending on which operand type we have. */ + if (code != BFD_RELOC_NONE) + { + /* %OP relocating operator found. */ + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + switch (result_type) + { + case (CGEN_PARSE_OPERAND_RESULT_NUMBER): + if (code == BFD_RELOC_HI16) + value = (value >> 16) & 0xFFFF; + else if (code == BFD_RELOC_LO16) + value = value & 0xFFFF; + else + errmsg = _("Biiiig Trouble in parse_imm16!"); + break; + + case (CGEN_PARSE_OPERAND_RESULT_QUEUED): + /* No special processing for this case. */ + break; + + default: + errmsg = _("The percent-operator's operand is not a symbol"); + break; + } + } + *valuep = value; + } + else + { + /* Parse hex values like 0xffff as unsigned, and sign extend + them manually. */ + int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16); + + if ((*strp)[0] == '0' + && ((*strp)[1] == 'x' || (*strp)[1] == 'X')) + parse_signed = 0; + + /* No relocating operator. Parse as an number. */ + if (parse_signed) + { + /* Parse as as signed integer. */ + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + + if (errmsg == NULL) + { +#if 0 + /* Manual range checking is needed for the signed case. */ + if (*valuep & 0x8000) + value = 0xffff0000 | *valuep; + else + value = *valuep; + + if (signed_out_of_bounds (value)) + errmsg = _("Operand out of range. Must be between -32768 and 32767."); + /* Truncate to 16 bits. This is necessary + because cgen will have sign extended *valuep. */ + *valuep &= 0xFFFF; +#endif + } + } + else + { + /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); + + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16 + && *valuep >= 0x8000 + && *valuep <= 0xffff) + *valuep -= 0x10000; + } + } + + return errmsg; +} + + +static const char * +parse_dup (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + + +static const char * +parse_ball (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0) + { + *strp += 3; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_xmode (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0) + { + *strp += 2; + *valuep = 1; + } + else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_rc (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0) + { + *strp += 1; + *valuep = 1; + } + else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0) + { + *strp += 1; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_cbrb (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0) + { + *strp += 2; + *valuep = 1; + } + else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_rbbc (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0) + { + *strp += 2; + *valuep = 0; + } + else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0) + { + *strp += 3; + *valuep = 1; + } + else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0) + { + *strp += 3; + *valuep = 2; + } + else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0) + { + *strp += 2; + *valuep = 3; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + return errmsg; +} + +static const char * +parse_type (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg = NULL; + + if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0) + { + *strp += 3; + *valuep = 0; + } + else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0) + { + *strp += 4; + *valuep = 1; + } + else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0) + { + *strp += 2; + *valuep = 2; + } + else + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + + if ((errmsg == NULL) && (*valuep == 3)) + errmsg = _("invalid operand. type may have values 0,1,2 only."); + + return errmsg; +} + +/* -- dis.c */ + +const char * mt_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +mt_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case MT_OPERAND_A23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_A23, (unsigned long *) (& fields->f_a23)); + break; + case MT_OPERAND_BALL : + errmsg = parse_ball (cd, strp, MT_OPERAND_BALL, (unsigned long *) (& fields->f_ball)); + break; + case MT_OPERAND_BALL2 : + errmsg = parse_ball (cd, strp, MT_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2)); + break; + case MT_OPERAND_BANKADDR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr)); + break; + case MT_OPERAND_BRC : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC, (unsigned long *) (& fields->f_brc)); + break; + case MT_OPERAND_BRC2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2)); + break; + case MT_OPERAND_CB1INCR : + errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr)); + break; + case MT_OPERAND_CB1SEL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel)); + break; + case MT_OPERAND_CB2INCR : + errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr)); + break; + case MT_OPERAND_CB2SEL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel)); + break; + case MT_OPERAND_CBRB : + errmsg = parse_cbrb (cd, strp, MT_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb)); + break; + case MT_OPERAND_CBS : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBS, (unsigned long *) (& fields->f_cbs)); + break; + case MT_OPERAND_CBX : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBX, (unsigned long *) (& fields->f_cbx)); + break; + case MT_OPERAND_CCB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CCB, (unsigned long *) (& fields->f_ccb)); + break; + case MT_OPERAND_CDB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CDB, (unsigned long *) (& fields->f_cdb)); + break; + case MT_OPERAND_CELL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CELL, (unsigned long *) (& fields->f_cell)); + break; + case MT_OPERAND_COLNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum)); + break; + case MT_OPERAND_CONTNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum)); + break; + case MT_OPERAND_CR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CR, (unsigned long *) (& fields->f_cr)); + break; + case MT_OPERAND_CTXDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp)); + break; + case MT_OPERAND_DUP : + errmsg = parse_dup (cd, strp, MT_OPERAND_DUP, (unsigned long *) (& fields->f_dup)); + break; + case MT_OPERAND_FBDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp)); + break; + case MT_OPERAND_FBINCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr)); + break; + case MT_OPERAND_FRDR : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_dr); + break; + case MT_OPERAND_FRDRRR : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_drrr); + break; + case MT_OPERAND_FRSR1 : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr1); + break; + case MT_OPERAND_FRSR2 : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr2); + break; + case MT_OPERAND_ID : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ID, (unsigned long *) (& fields->f_id)); + break; + case MT_OPERAND_IMM16 : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16, (long *) (& fields->f_imm16s)); + break; + case MT_OPERAND_IMM16L : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l)); + break; + case MT_OPERAND_IMM16O : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s)); + break; + case MT_OPERAND_IMM16Z : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u)); + break; + case MT_OPERAND_INCAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt)); + break; + case MT_OPERAND_INCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCR, (unsigned long *) (& fields->f_incr)); + break; + case MT_OPERAND_LENGTH : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_LENGTH, (unsigned long *) (& fields->f_length)); + break; + case MT_OPERAND_LOOPSIZE : + errmsg = parse_loopsize (cd, strp, MT_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo)); + break; + case MT_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK, (unsigned long *) (& fields->f_mask)); + break; + case MT_OPERAND_MASK1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1)); + break; + case MT_OPERAND_MODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MODE, (unsigned long *) (& fields->f_mode)); + break; + case MT_OPERAND_PERM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_PERM, (unsigned long *) (& fields->f_perm)); + break; + case MT_OPERAND_RBBC : + errmsg = parse_rbbc (cd, strp, MT_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc)); + break; + case MT_OPERAND_RC : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC, (unsigned long *) (& fields->f_rc)); + break; + case MT_OPERAND_RC1 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC1, (unsigned long *) (& fields->f_rc1)); + break; + case MT_OPERAND_RC2 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC2, (unsigned long *) (& fields->f_rc2)); + break; + case MT_OPERAND_RC3 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC3, (unsigned long *) (& fields->f_rc3)); + break; + case MT_OPERAND_RCNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum)); + break; + case MT_OPERAND_RDA : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RDA, (unsigned long *) (& fields->f_rda)); + break; + case MT_OPERAND_ROWNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum)); + break; + case MT_OPERAND_ROWNUM1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1)); + break; + case MT_OPERAND_ROWNUM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2)); + break; + case MT_OPERAND_SIZE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_SIZE, (unsigned long *) (& fields->f_size)); + break; + case MT_OPERAND_TYPE : + errmsg = parse_type (cd, strp, MT_OPERAND_TYPE, (unsigned long *) (& fields->f_type)); + break; + case MT_OPERAND_WR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_WR, (unsigned long *) (& fields->f_wr)); + break; + case MT_OPERAND_XMODE : + errmsg = parse_xmode (cd, strp, MT_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const mt_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +mt_cgen_init_asm (CGEN_CPU_DESC cd) +{ + mt_cgen_init_opcode_table (cd); + mt_cgen_init_ibld_table (cd); + cd->parse_handlers = & mt_cgen_parse_handlers[0]; + cd->parse_operand = mt_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by mt_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +mt_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +mt_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! mt_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/mt-desc.c b/external/gpl3/gdb/dist/opcodes/mt-desc.c new file mode 100644 index 000000000000..e14d1f0811fc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-desc.c @@ -0,0 +1,1308 @@ +/* CPU data for mt. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mt-desc.h" +#include "mt-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "ms1", MACH_MS1 }, + { "ms1_003", MACH_MS1_003 }, + { "ms2", MACH_MS2 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "mt", ISA_MT }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, + { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] }, + { "AL-INSN", &bool_attr[0], &bool_attr[0] }, + { "IO-INSN", &bool_attr[0], &bool_attr[0] }, + { "BR-INSN", &bool_attr[0], &bool_attr[0] }, + { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] }, + { "USES-FRDR", &bool_attr[0], &bool_attr[0] }, + { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] }, + { "USES-FRSR1", &bool_attr[0], &bool_attr[0] }, + { "USES-FRSR2", &bool_attr[0], &bool_attr[0] }, + { "SKIPA", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA mt_cgen_isa_table[] = { + { "mt", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH mt_cgen_mach_table[] = { + { "ms1", "ms1", MACH_MS1, 0 }, + { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, + { "ms2", "ms2", MACH_MS2, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] = +{ + { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "XX", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mt_cgen_opval_msys_syms = +{ + & mt_cgen_opval_msys_syms_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] = +{ + { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "ra", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "R15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "ira", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mt_cgen_opval_h_spr = +{ + & mt_cgen_opval_h_spr_entries[0], + 20, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY mt_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & mt_cgen_ifld_table[0]; +} + +/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & mt_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of mt_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & mt_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of mt_cgen_cpu_open to rebuild the tables. */ + +static void +mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & mt_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & mt_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (mt_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = mt_cgen_rebuild_tables; + mt_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +mt_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/mt-desc.h b/external/gpl3/gdb/dist/opcodes/mt-desc.h new file mode 100644 index 000000000000..ddeae4ec4f19 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-desc.h @@ -0,0 +1,299 @@ +/* CPU data header for mt. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MT_CPU_H +#define MT_CPU_H + +#define CGEN_ARCH mt + +/* Given symbol S, return mt_cgen_. */ +#define CGEN_SYM(s) mt##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_MS1BF +#define HAVE_CPU_MS1_003BF +#define HAVE_CPU_MS2BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14 + +/* Enums. */ + +/* Enum declaration for msys enums. */ +typedef enum insn_msys { + MSYS_NO, MSYS_YES +} INSN_MSYS; + +/* Enum declaration for opc enums. */ +typedef enum insn_opc { + OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3 + , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10 + , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14 + , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24 + , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28 + , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32 + , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50 + , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53 +} INSN_OPC; + +/* Enum declaration for msopc enums. */ +typedef enum insn_msopc { + MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB + , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI + , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI + , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB + , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB + , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR + , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR + , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS +} INSN_MSOPC; + +/* Enum declaration for imm enums. */ +typedef enum insn_imm { + IMM_NO, IMM_YES +} INSN_IMM; + +/* Enum declaration for . */ +typedef enum msys_syms { + H_NIL_DUP = 1, H_NIL_XX = 0 +} MSYS_SYMS; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2 + , MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_MT, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for mt ifield types. */ +typedef enum ifield_type { + MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC + , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2 + , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S + , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12 + , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC + , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA + , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE + , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23 + , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR + , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19 + , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR + , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15 + , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX + , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11 + , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB + , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM + , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP + , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL + , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2 + , MT_F_BRC2, MT_F_BALL2, MT_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) MT_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for mt hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for mt operand types. */ +typedef enum cgen_operand_type { + MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR + , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O + , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC + , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2 + , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL + , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE + , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE + , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA + , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM + , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR + , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB + , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR + , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL + , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 55 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS + , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD + , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2 + , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH + , CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_LOAD_DELAY)) != 0) +#define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0) +#define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_AL_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IO_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_BR_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_JAL_HAZARD)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRDR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRDRRR)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRSR1)) != 0) +#define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRSR2)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIPA)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld mt_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD mt_cgen_opval_h_spr; + +extern const CGEN_HW_ENTRY mt_cgen_hw_table[]; + + + +#endif /* MT_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/mt-dis.c b/external/gpl3/gdb/dist/opcodes/mt-dis.c new file mode 100644 index 000000000000..28f4655e268f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-dis.c @@ -0,0 +1,711 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "mt-desc.h" +#include "mt-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ +static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); +static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); + +static void +print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "$%lx", value); + + if (0) + print_normal (cd, dis_info, value, attrs, pc, length); +} + +static void +print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_address (cd, dis_info, value + pc, attrs, pc, length); +} + +/* -- */ + +void mt_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +mt_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case MT_OPERAND_A23 : + print_dollarhex (cd, info, fields->f_a23, 0, pc, length); + break; + case MT_OPERAND_BALL : + print_dollarhex (cd, info, fields->f_ball, 0, pc, length); + break; + case MT_OPERAND_BALL2 : + print_dollarhex (cd, info, fields->f_ball2, 0, pc, length); + break; + case MT_OPERAND_BANKADDR : + print_dollarhex (cd, info, fields->f_bankaddr, 0, pc, length); + break; + case MT_OPERAND_BRC : + print_dollarhex (cd, info, fields->f_brc, 0, pc, length); + break; + case MT_OPERAND_BRC2 : + print_dollarhex (cd, info, fields->f_brc2, 0, pc, length); + break; + case MT_OPERAND_CB1INCR : + print_dollarhex (cd, info, fields->f_cb1incr, 0|(1<f_cb1sel, 0, pc, length); + break; + case MT_OPERAND_CB2INCR : + print_dollarhex (cd, info, fields->f_cb2incr, 0|(1<f_cb2sel, 0, pc, length); + break; + case MT_OPERAND_CBRB : + print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length); + break; + case MT_OPERAND_CBS : + print_dollarhex (cd, info, fields->f_cbs, 0, pc, length); + break; + case MT_OPERAND_CBX : + print_dollarhex (cd, info, fields->f_cbx, 0, pc, length); + break; + case MT_OPERAND_CCB : + print_dollarhex (cd, info, fields->f_ccb, 0, pc, length); + break; + case MT_OPERAND_CDB : + print_dollarhex (cd, info, fields->f_cdb, 0, pc, length); + break; + case MT_OPERAND_CELL : + print_dollarhex (cd, info, fields->f_cell, 0, pc, length); + break; + case MT_OPERAND_COLNUM : + print_dollarhex (cd, info, fields->f_colnum, 0, pc, length); + break; + case MT_OPERAND_CONTNUM : + print_dollarhex (cd, info, fields->f_contnum, 0, pc, length); + break; + case MT_OPERAND_CR : + print_dollarhex (cd, info, fields->f_cr, 0, pc, length); + break; + case MT_OPERAND_CTXDISP : + print_dollarhex (cd, info, fields->f_ctxdisp, 0, pc, length); + break; + case MT_OPERAND_DUP : + print_dollarhex (cd, info, fields->f_dup, 0, pc, length); + break; + case MT_OPERAND_FBDISP : + print_dollarhex (cd, info, fields->f_fbdisp, 0, pc, length); + break; + case MT_OPERAND_FBINCR : + print_dollarhex (cd, info, fields->f_fbincr, 0, pc, length); + break; + case MT_OPERAND_FRDR : + print_keyword (cd, info, & mt_cgen_opval_h_spr, fields->f_dr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_id, 0, pc, length); + break; + case MT_OPERAND_IMM16 : + print_dollarhex (cd, info, fields->f_imm16s, 0|(1<f_imm16l, 0, pc, length); + break; + case MT_OPERAND_IMM16O : + print_pcrel (cd, info, fields->f_imm16s, 0|(1<f_imm16u, 0, pc, length); + break; + case MT_OPERAND_INCAMT : + print_dollarhex (cd, info, fields->f_incamt, 0, pc, length); + break; + case MT_OPERAND_INCR : + print_dollarhex (cd, info, fields->f_incr, 0, pc, length); + break; + case MT_OPERAND_LENGTH : + print_dollarhex (cd, info, fields->f_length, 0, pc, length); + break; + case MT_OPERAND_LOOPSIZE : + print_pcrel (cd, info, fields->f_loopo, 0|(1<f_mask, 0, pc, length); + break; + case MT_OPERAND_MASK1 : + print_dollarhex (cd, info, fields->f_mask1, 0, pc, length); + break; + case MT_OPERAND_MODE : + print_dollarhex (cd, info, fields->f_mode, 0, pc, length); + break; + case MT_OPERAND_PERM : + print_dollarhex (cd, info, fields->f_perm, 0, pc, length); + break; + case MT_OPERAND_RBBC : + print_dollarhex (cd, info, fields->f_rbbc, 0, pc, length); + break; + case MT_OPERAND_RC : + print_dollarhex (cd, info, fields->f_rc, 0, pc, length); + break; + case MT_OPERAND_RC1 : + print_dollarhex (cd, info, fields->f_rc1, 0, pc, length); + break; + case MT_OPERAND_RC2 : + print_dollarhex (cd, info, fields->f_rc2, 0, pc, length); + break; + case MT_OPERAND_RC3 : + print_dollarhex (cd, info, fields->f_rc3, 0, pc, length); + break; + case MT_OPERAND_RCNUM : + print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length); + break; + case MT_OPERAND_RDA : + print_dollarhex (cd, info, fields->f_rda, 0, pc, length); + break; + case MT_OPERAND_ROWNUM : + print_dollarhex (cd, info, fields->f_rownum, 0, pc, length); + break; + case MT_OPERAND_ROWNUM1 : + print_dollarhex (cd, info, fields->f_rownum1, 0, pc, length); + break; + case MT_OPERAND_ROWNUM2 : + print_dollarhex (cd, info, fields->f_rownum2, 0, pc, length); + break; + case MT_OPERAND_SIZE : + print_dollarhex (cd, info, fields->f_size, 0, pc, length); + break; + case MT_OPERAND_TYPE : + print_dollarhex (cd, info, fields->f_type, 0, pc, length); + break; + case MT_OPERAND_WR : + print_dollarhex (cd, info, fields->f_wr, 0, pc, length); + break; + case MT_OPERAND_XMODE : + print_dollarhex (cd, info, fields->f_xmode, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const mt_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +mt_cgen_init_dis (CGEN_CPU_DESC cd) +{ + mt_cgen_init_opcode_table (cd); + mt_cgen_init_ibld_table (cd); + cd->print_handlers = & mt_cgen_print_handlers[0]; + cd->print_operand = mt_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + mt_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! mt_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_mt (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_mt +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = mt_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + mt_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/mt-ibld.c b/external/gpl3/gdb/dist/opcodes/mt-ibld.c new file mode 100644 index 000000000000..00110de79348 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-ibld.c @@ -0,0 +1,1737 @@ +/* Instruction building/extraction support for mt. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "mt-desc.h" +#include "mt-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * mt_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +mt_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MT_OPERAND_A23 : + errmsg = insert_normal (cd, fields->f_a23, 0, 0, 23, 1, 32, total_length, buffer); + break; + case MT_OPERAND_BALL : + errmsg = insert_normal (cd, fields->f_ball, 0, 0, 19, 1, 32, total_length, buffer); + break; + case MT_OPERAND_BALL2 : + errmsg = insert_normal (cd, fields->f_ball2, 0, 0, 15, 1, 32, total_length, buffer); + break; + case MT_OPERAND_BANKADDR : + errmsg = insert_normal (cd, fields->f_bankaddr, 0, 0, 25, 13, 32, total_length, buffer); + break; + case MT_OPERAND_BRC : + errmsg = insert_normal (cd, fields->f_brc, 0, 0, 18, 3, 32, total_length, buffer); + break; + case MT_OPERAND_BRC2 : + errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CB1INCR : + errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CB2INCR : + errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CBRB : + errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer); + break; + case MT_OPERAND_CBS : + errmsg = insert_normal (cd, fields->f_cbs, 0, 0, 19, 2, 32, total_length, buffer); + break; + case MT_OPERAND_CBX : + errmsg = insert_normal (cd, fields->f_cbx, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CCB : + errmsg = insert_normal (cd, fields->f_ccb, 0, 0, 11, 1, 32, total_length, buffer); + break; + case MT_OPERAND_CDB : + errmsg = insert_normal (cd, fields->f_cdb, 0, 0, 10, 1, 32, total_length, buffer); + break; + case MT_OPERAND_CELL : + errmsg = insert_normal (cd, fields->f_cell, 0, 0, 9, 3, 32, total_length, buffer); + break; + case MT_OPERAND_COLNUM : + errmsg = insert_normal (cd, fields->f_colnum, 0, 0, 18, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CONTNUM : + errmsg = insert_normal (cd, fields->f_contnum, 0, 0, 8, 9, 32, total_length, buffer); + break; + case MT_OPERAND_CR : + errmsg = insert_normal (cd, fields->f_cr, 0, 0, 22, 3, 32, total_length, buffer); + break; + case MT_OPERAND_CTXDISP : + errmsg = insert_normal (cd, fields->f_ctxdisp, 0, 0, 5, 6, 32, total_length, buffer); + break; + case MT_OPERAND_DUP : + errmsg = insert_normal (cd, fields->f_dup, 0, 0, 6, 1, 32, total_length, buffer); + break; + case MT_OPERAND_FBDISP : + errmsg = insert_normal (cd, fields->f_fbdisp, 0, 0, 15, 6, 32, total_length, buffer); + break; + case MT_OPERAND_FBINCR : + errmsg = insert_normal (cd, fields->f_fbincr, 0, 0, 23, 4, 32, total_length, buffer); + break; + case MT_OPERAND_FRDR : + errmsg = insert_normal (cd, fields->f_dr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_id, 0, 0, 14, 1, 32, total_length, buffer); + break; + case MT_OPERAND_IMM16 : + { + long value = fields->f_imm16s; + value = ((value) + (0)); + errmsg = insert_normal (cd, value, 0|(1<f_imm16l, 0, 0, 23, 16, 32, total_length, buffer); + break; + case MT_OPERAND_IMM16O : + { + long value = fields->f_imm16s; + value = ((value) + (0)); + errmsg = insert_normal (cd, value, 0|(1<f_imm16u, 0, 0, 15, 16, 32, total_length, buffer); + break; + case MT_OPERAND_INCAMT : + errmsg = insert_normal (cd, fields->f_incamt, 0, 0, 19, 8, 32, total_length, buffer); + break; + case MT_OPERAND_INCR : + errmsg = insert_normal (cd, fields->f_incr, 0, 0, 17, 6, 32, total_length, buffer); + break; + case MT_OPERAND_LENGTH : + errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer); + break; + case MT_OPERAND_LOOPSIZE : + { + long value = fields->f_loopo; + value = ((USI) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer); + } + break; + case MT_OPERAND_MASK : + errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer); + break; + case MT_OPERAND_MASK1 : + errmsg = insert_normal (cd, fields->f_mask1, 0, 0, 22, 3, 32, total_length, buffer); + break; + case MT_OPERAND_MODE : + errmsg = insert_normal (cd, fields->f_mode, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MT_OPERAND_PERM : + errmsg = insert_normal (cd, fields->f_perm, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MT_OPERAND_RBBC : + errmsg = insert_normal (cd, fields->f_rbbc, 0, 0, 25, 2, 32, total_length, buffer); + break; + case MT_OPERAND_RC : + errmsg = insert_normal (cd, fields->f_rc, 0, 0, 15, 1, 32, total_length, buffer); + break; + case MT_OPERAND_RC1 : + errmsg = insert_normal (cd, fields->f_rc1, 0, 0, 11, 1, 32, total_length, buffer); + break; + case MT_OPERAND_RC2 : + errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer); + break; + case MT_OPERAND_RC3 : + errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer); + break; + case MT_OPERAND_RCNUM : + errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MT_OPERAND_RDA : + errmsg = insert_normal (cd, fields->f_rda, 0, 0, 25, 1, 32, total_length, buffer); + break; + case MT_OPERAND_ROWNUM : + errmsg = insert_normal (cd, fields->f_rownum, 0, 0, 14, 3, 32, total_length, buffer); + break; + case MT_OPERAND_ROWNUM1 : + errmsg = insert_normal (cd, fields->f_rownum1, 0, 0, 12, 3, 32, total_length, buffer); + break; + case MT_OPERAND_ROWNUM2 : + errmsg = insert_normal (cd, fields->f_rownum2, 0, 0, 9, 3, 32, total_length, buffer); + break; + case MT_OPERAND_SIZE : + errmsg = insert_normal (cd, fields->f_size, 0, 0, 13, 14, 32, total_length, buffer); + break; + case MT_OPERAND_TYPE : + errmsg = insert_normal (cd, fields->f_type, 0, 0, 21, 2, 32, total_length, buffer); + break; + case MT_OPERAND_WR : + errmsg = insert_normal (cd, fields->f_wr, 0, 0, 24, 1, 32, total_length, buffer); + break; + case MT_OPERAND_XMODE : + errmsg = insert_normal (cd, fields->f_xmode, 0, 0, 23, 1, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int mt_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +mt_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MT_OPERAND_A23 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_a23); + break; + case MT_OPERAND_BALL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_ball); + break; + case MT_OPERAND_BALL2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_ball2); + break; + case MT_OPERAND_BANKADDR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 13, 32, total_length, pc, & fields->f_bankaddr); + break; + case MT_OPERAND_BRC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_brc); + break; + case MT_OPERAND_BRC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2); + break; + case MT_OPERAND_CB1INCR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cb1incr); + break; + case MT_OPERAND_CB1SEL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel); + break; + case MT_OPERAND_CB2INCR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cb2incr); + break; + case MT_OPERAND_CB2SEL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel); + break; + case MT_OPERAND_CBRB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb); + break; + case MT_OPERAND_CBS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 2, 32, total_length, pc, & fields->f_cbs); + break; + case MT_OPERAND_CBX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_cbx); + break; + case MT_OPERAND_CCB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_ccb); + break; + case MT_OPERAND_CDB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cdb); + break; + case MT_OPERAND_CELL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_cell); + break; + case MT_OPERAND_COLNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_colnum); + break; + case MT_OPERAND_CONTNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_contnum); + break; + case MT_OPERAND_CR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cr); + break; + case MT_OPERAND_CTXDISP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_ctxdisp); + break; + case MT_OPERAND_DUP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_dup); + break; + case MT_OPERAND_FBDISP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_fbdisp); + break; + case MT_OPERAND_FBINCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 4, 32, total_length, pc, & fields->f_fbincr); + break; + case MT_OPERAND_FRDR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dr); + break; + case MT_OPERAND_FRDRRR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_drrr); + break; + case MT_OPERAND_FRSR1 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr1); + break; + case MT_OPERAND_FRSR2 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr2); + break; + case MT_OPERAND_ID : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_id); + break; + case MT_OPERAND_IMM16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; + } + break; + case MT_OPERAND_IMM16L : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l); + break; + case MT_OPERAND_IMM16O : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; + } + break; + case MT_OPERAND_IMM16Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm16u); + break; + case MT_OPERAND_INCAMT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 8, 32, total_length, pc, & fields->f_incamt); + break; + case MT_OPERAND_INCR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_incr); + break; + case MT_OPERAND_LENGTH : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length); + break; + case MT_OPERAND_LOOPSIZE : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value); + value = ((((value) << (2))) + (8)); + fields->f_loopo = value; + } + break; + case MT_OPERAND_MASK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask); + break; + case MT_OPERAND_MASK1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_mask1); + break; + case MT_OPERAND_MODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_mode); + break; + case MT_OPERAND_PERM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_perm); + break; + case MT_OPERAND_RBBC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_rbbc); + break; + case MT_OPERAND_RC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_rc); + break; + case MT_OPERAND_RC1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_rc1); + break; + case MT_OPERAND_RC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2); + break; + case MT_OPERAND_RC3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3); + break; + case MT_OPERAND_RCNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum); + break; + case MT_OPERAND_RDA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_rda); + break; + case MT_OPERAND_ROWNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rownum); + break; + case MT_OPERAND_ROWNUM1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rownum1); + break; + case MT_OPERAND_ROWNUM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rownum2); + break; + case MT_OPERAND_SIZE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 14, 32, total_length, pc, & fields->f_size); + break; + case MT_OPERAND_TYPE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 2, 32, total_length, pc, & fields->f_type); + break; + case MT_OPERAND_WR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_wr); + break; + case MT_OPERAND_XMODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_xmode); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const mt_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const mt_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int mt_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma mt_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +mt_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case MT_OPERAND_A23 : + value = fields->f_a23; + break; + case MT_OPERAND_BALL : + value = fields->f_ball; + break; + case MT_OPERAND_BALL2 : + value = fields->f_ball2; + break; + case MT_OPERAND_BANKADDR : + value = fields->f_bankaddr; + break; + case MT_OPERAND_BRC : + value = fields->f_brc; + break; + case MT_OPERAND_BRC2 : + value = fields->f_brc2; + break; + case MT_OPERAND_CB1INCR : + value = fields->f_cb1incr; + break; + case MT_OPERAND_CB1SEL : + value = fields->f_cb1sel; + break; + case MT_OPERAND_CB2INCR : + value = fields->f_cb2incr; + break; + case MT_OPERAND_CB2SEL : + value = fields->f_cb2sel; + break; + case MT_OPERAND_CBRB : + value = fields->f_cbrb; + break; + case MT_OPERAND_CBS : + value = fields->f_cbs; + break; + case MT_OPERAND_CBX : + value = fields->f_cbx; + break; + case MT_OPERAND_CCB : + value = fields->f_ccb; + break; + case MT_OPERAND_CDB : + value = fields->f_cdb; + break; + case MT_OPERAND_CELL : + value = fields->f_cell; + break; + case MT_OPERAND_COLNUM : + value = fields->f_colnum; + break; + case MT_OPERAND_CONTNUM : + value = fields->f_contnum; + break; + case MT_OPERAND_CR : + value = fields->f_cr; + break; + case MT_OPERAND_CTXDISP : + value = fields->f_ctxdisp; + break; + case MT_OPERAND_DUP : + value = fields->f_dup; + break; + case MT_OPERAND_FBDISP : + value = fields->f_fbdisp; + break; + case MT_OPERAND_FBINCR : + value = fields->f_fbincr; + break; + case MT_OPERAND_FRDR : + value = fields->f_dr; + break; + case MT_OPERAND_FRDRRR : + value = fields->f_drrr; + break; + case MT_OPERAND_FRSR1 : + value = fields->f_sr1; + break; + case MT_OPERAND_FRSR2 : + value = fields->f_sr2; + break; + case MT_OPERAND_ID : + value = fields->f_id; + break; + case MT_OPERAND_IMM16 : + value = fields->f_imm16s; + break; + case MT_OPERAND_IMM16L : + value = fields->f_imm16l; + break; + case MT_OPERAND_IMM16O : + value = fields->f_imm16s; + break; + case MT_OPERAND_IMM16Z : + value = fields->f_imm16u; + break; + case MT_OPERAND_INCAMT : + value = fields->f_incamt; + break; + case MT_OPERAND_INCR : + value = fields->f_incr; + break; + case MT_OPERAND_LENGTH : + value = fields->f_length; + break; + case MT_OPERAND_LOOPSIZE : + value = fields->f_loopo; + break; + case MT_OPERAND_MASK : + value = fields->f_mask; + break; + case MT_OPERAND_MASK1 : + value = fields->f_mask1; + break; + case MT_OPERAND_MODE : + value = fields->f_mode; + break; + case MT_OPERAND_PERM : + value = fields->f_perm; + break; + case MT_OPERAND_RBBC : + value = fields->f_rbbc; + break; + case MT_OPERAND_RC : + value = fields->f_rc; + break; + case MT_OPERAND_RC1 : + value = fields->f_rc1; + break; + case MT_OPERAND_RC2 : + value = fields->f_rc2; + break; + case MT_OPERAND_RC3 : + value = fields->f_rc3; + break; + case MT_OPERAND_RCNUM : + value = fields->f_rcnum; + break; + case MT_OPERAND_RDA : + value = fields->f_rda; + break; + case MT_OPERAND_ROWNUM : + value = fields->f_rownum; + break; + case MT_OPERAND_ROWNUM1 : + value = fields->f_rownum1; + break; + case MT_OPERAND_ROWNUM2 : + value = fields->f_rownum2; + break; + case MT_OPERAND_SIZE : + value = fields->f_size; + break; + case MT_OPERAND_TYPE : + value = fields->f_type; + break; + case MT_OPERAND_WR : + value = fields->f_wr; + break; + case MT_OPERAND_XMODE : + value = fields->f_xmode; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +mt_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case MT_OPERAND_A23 : + value = fields->f_a23; + break; + case MT_OPERAND_BALL : + value = fields->f_ball; + break; + case MT_OPERAND_BALL2 : + value = fields->f_ball2; + break; + case MT_OPERAND_BANKADDR : + value = fields->f_bankaddr; + break; + case MT_OPERAND_BRC : + value = fields->f_brc; + break; + case MT_OPERAND_BRC2 : + value = fields->f_brc2; + break; + case MT_OPERAND_CB1INCR : + value = fields->f_cb1incr; + break; + case MT_OPERAND_CB1SEL : + value = fields->f_cb1sel; + break; + case MT_OPERAND_CB2INCR : + value = fields->f_cb2incr; + break; + case MT_OPERAND_CB2SEL : + value = fields->f_cb2sel; + break; + case MT_OPERAND_CBRB : + value = fields->f_cbrb; + break; + case MT_OPERAND_CBS : + value = fields->f_cbs; + break; + case MT_OPERAND_CBX : + value = fields->f_cbx; + break; + case MT_OPERAND_CCB : + value = fields->f_ccb; + break; + case MT_OPERAND_CDB : + value = fields->f_cdb; + break; + case MT_OPERAND_CELL : + value = fields->f_cell; + break; + case MT_OPERAND_COLNUM : + value = fields->f_colnum; + break; + case MT_OPERAND_CONTNUM : + value = fields->f_contnum; + break; + case MT_OPERAND_CR : + value = fields->f_cr; + break; + case MT_OPERAND_CTXDISP : + value = fields->f_ctxdisp; + break; + case MT_OPERAND_DUP : + value = fields->f_dup; + break; + case MT_OPERAND_FBDISP : + value = fields->f_fbdisp; + break; + case MT_OPERAND_FBINCR : + value = fields->f_fbincr; + break; + case MT_OPERAND_FRDR : + value = fields->f_dr; + break; + case MT_OPERAND_FRDRRR : + value = fields->f_drrr; + break; + case MT_OPERAND_FRSR1 : + value = fields->f_sr1; + break; + case MT_OPERAND_FRSR2 : + value = fields->f_sr2; + break; + case MT_OPERAND_ID : + value = fields->f_id; + break; + case MT_OPERAND_IMM16 : + value = fields->f_imm16s; + break; + case MT_OPERAND_IMM16L : + value = fields->f_imm16l; + break; + case MT_OPERAND_IMM16O : + value = fields->f_imm16s; + break; + case MT_OPERAND_IMM16Z : + value = fields->f_imm16u; + break; + case MT_OPERAND_INCAMT : + value = fields->f_incamt; + break; + case MT_OPERAND_INCR : + value = fields->f_incr; + break; + case MT_OPERAND_LENGTH : + value = fields->f_length; + break; + case MT_OPERAND_LOOPSIZE : + value = fields->f_loopo; + break; + case MT_OPERAND_MASK : + value = fields->f_mask; + break; + case MT_OPERAND_MASK1 : + value = fields->f_mask1; + break; + case MT_OPERAND_MODE : + value = fields->f_mode; + break; + case MT_OPERAND_PERM : + value = fields->f_perm; + break; + case MT_OPERAND_RBBC : + value = fields->f_rbbc; + break; + case MT_OPERAND_RC : + value = fields->f_rc; + break; + case MT_OPERAND_RC1 : + value = fields->f_rc1; + break; + case MT_OPERAND_RC2 : + value = fields->f_rc2; + break; + case MT_OPERAND_RC3 : + value = fields->f_rc3; + break; + case MT_OPERAND_RCNUM : + value = fields->f_rcnum; + break; + case MT_OPERAND_RDA : + value = fields->f_rda; + break; + case MT_OPERAND_ROWNUM : + value = fields->f_rownum; + break; + case MT_OPERAND_ROWNUM1 : + value = fields->f_rownum1; + break; + case MT_OPERAND_ROWNUM2 : + value = fields->f_rownum2; + break; + case MT_OPERAND_SIZE : + value = fields->f_size; + break; + case MT_OPERAND_TYPE : + value = fields->f_type; + break; + case MT_OPERAND_WR : + value = fields->f_wr; + break; + case MT_OPERAND_XMODE : + value = fields->f_xmode; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void mt_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void mt_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +mt_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case MT_OPERAND_A23 : + fields->f_a23 = value; + break; + case MT_OPERAND_BALL : + fields->f_ball = value; + break; + case MT_OPERAND_BALL2 : + fields->f_ball2 = value; + break; + case MT_OPERAND_BANKADDR : + fields->f_bankaddr = value; + break; + case MT_OPERAND_BRC : + fields->f_brc = value; + break; + case MT_OPERAND_BRC2 : + fields->f_brc2 = value; + break; + case MT_OPERAND_CB1INCR : + fields->f_cb1incr = value; + break; + case MT_OPERAND_CB1SEL : + fields->f_cb1sel = value; + break; + case MT_OPERAND_CB2INCR : + fields->f_cb2incr = value; + break; + case MT_OPERAND_CB2SEL : + fields->f_cb2sel = value; + break; + case MT_OPERAND_CBRB : + fields->f_cbrb = value; + break; + case MT_OPERAND_CBS : + fields->f_cbs = value; + break; + case MT_OPERAND_CBX : + fields->f_cbx = value; + break; + case MT_OPERAND_CCB : + fields->f_ccb = value; + break; + case MT_OPERAND_CDB : + fields->f_cdb = value; + break; + case MT_OPERAND_CELL : + fields->f_cell = value; + break; + case MT_OPERAND_COLNUM : + fields->f_colnum = value; + break; + case MT_OPERAND_CONTNUM : + fields->f_contnum = value; + break; + case MT_OPERAND_CR : + fields->f_cr = value; + break; + case MT_OPERAND_CTXDISP : + fields->f_ctxdisp = value; + break; + case MT_OPERAND_DUP : + fields->f_dup = value; + break; + case MT_OPERAND_FBDISP : + fields->f_fbdisp = value; + break; + case MT_OPERAND_FBINCR : + fields->f_fbincr = value; + break; + case MT_OPERAND_FRDR : + fields->f_dr = value; + break; + case MT_OPERAND_FRDRRR : + fields->f_drrr = value; + break; + case MT_OPERAND_FRSR1 : + fields->f_sr1 = value; + break; + case MT_OPERAND_FRSR2 : + fields->f_sr2 = value; + break; + case MT_OPERAND_ID : + fields->f_id = value; + break; + case MT_OPERAND_IMM16 : + fields->f_imm16s = value; + break; + case MT_OPERAND_IMM16L : + fields->f_imm16l = value; + break; + case MT_OPERAND_IMM16O : + fields->f_imm16s = value; + break; + case MT_OPERAND_IMM16Z : + fields->f_imm16u = value; + break; + case MT_OPERAND_INCAMT : + fields->f_incamt = value; + break; + case MT_OPERAND_INCR : + fields->f_incr = value; + break; + case MT_OPERAND_LENGTH : + fields->f_length = value; + break; + case MT_OPERAND_LOOPSIZE : + fields->f_loopo = value; + break; + case MT_OPERAND_MASK : + fields->f_mask = value; + break; + case MT_OPERAND_MASK1 : + fields->f_mask1 = value; + break; + case MT_OPERAND_MODE : + fields->f_mode = value; + break; + case MT_OPERAND_PERM : + fields->f_perm = value; + break; + case MT_OPERAND_RBBC : + fields->f_rbbc = value; + break; + case MT_OPERAND_RC : + fields->f_rc = value; + break; + case MT_OPERAND_RC1 : + fields->f_rc1 = value; + break; + case MT_OPERAND_RC2 : + fields->f_rc2 = value; + break; + case MT_OPERAND_RC3 : + fields->f_rc3 = value; + break; + case MT_OPERAND_RCNUM : + fields->f_rcnum = value; + break; + case MT_OPERAND_RDA : + fields->f_rda = value; + break; + case MT_OPERAND_ROWNUM : + fields->f_rownum = value; + break; + case MT_OPERAND_ROWNUM1 : + fields->f_rownum1 = value; + break; + case MT_OPERAND_ROWNUM2 : + fields->f_rownum2 = value; + break; + case MT_OPERAND_SIZE : + fields->f_size = value; + break; + case MT_OPERAND_TYPE : + fields->f_type = value; + break; + case MT_OPERAND_WR : + fields->f_wr = value; + break; + case MT_OPERAND_XMODE : + fields->f_xmode = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +mt_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case MT_OPERAND_A23 : + fields->f_a23 = value; + break; + case MT_OPERAND_BALL : + fields->f_ball = value; + break; + case MT_OPERAND_BALL2 : + fields->f_ball2 = value; + break; + case MT_OPERAND_BANKADDR : + fields->f_bankaddr = value; + break; + case MT_OPERAND_BRC : + fields->f_brc = value; + break; + case MT_OPERAND_BRC2 : + fields->f_brc2 = value; + break; + case MT_OPERAND_CB1INCR : + fields->f_cb1incr = value; + break; + case MT_OPERAND_CB1SEL : + fields->f_cb1sel = value; + break; + case MT_OPERAND_CB2INCR : + fields->f_cb2incr = value; + break; + case MT_OPERAND_CB2SEL : + fields->f_cb2sel = value; + break; + case MT_OPERAND_CBRB : + fields->f_cbrb = value; + break; + case MT_OPERAND_CBS : + fields->f_cbs = value; + break; + case MT_OPERAND_CBX : + fields->f_cbx = value; + break; + case MT_OPERAND_CCB : + fields->f_ccb = value; + break; + case MT_OPERAND_CDB : + fields->f_cdb = value; + break; + case MT_OPERAND_CELL : + fields->f_cell = value; + break; + case MT_OPERAND_COLNUM : + fields->f_colnum = value; + break; + case MT_OPERAND_CONTNUM : + fields->f_contnum = value; + break; + case MT_OPERAND_CR : + fields->f_cr = value; + break; + case MT_OPERAND_CTXDISP : + fields->f_ctxdisp = value; + break; + case MT_OPERAND_DUP : + fields->f_dup = value; + break; + case MT_OPERAND_FBDISP : + fields->f_fbdisp = value; + break; + case MT_OPERAND_FBINCR : + fields->f_fbincr = value; + break; + case MT_OPERAND_FRDR : + fields->f_dr = value; + break; + case MT_OPERAND_FRDRRR : + fields->f_drrr = value; + break; + case MT_OPERAND_FRSR1 : + fields->f_sr1 = value; + break; + case MT_OPERAND_FRSR2 : + fields->f_sr2 = value; + break; + case MT_OPERAND_ID : + fields->f_id = value; + break; + case MT_OPERAND_IMM16 : + fields->f_imm16s = value; + break; + case MT_OPERAND_IMM16L : + fields->f_imm16l = value; + break; + case MT_OPERAND_IMM16O : + fields->f_imm16s = value; + break; + case MT_OPERAND_IMM16Z : + fields->f_imm16u = value; + break; + case MT_OPERAND_INCAMT : + fields->f_incamt = value; + break; + case MT_OPERAND_INCR : + fields->f_incr = value; + break; + case MT_OPERAND_LENGTH : + fields->f_length = value; + break; + case MT_OPERAND_LOOPSIZE : + fields->f_loopo = value; + break; + case MT_OPERAND_MASK : + fields->f_mask = value; + break; + case MT_OPERAND_MASK1 : + fields->f_mask1 = value; + break; + case MT_OPERAND_MODE : + fields->f_mode = value; + break; + case MT_OPERAND_PERM : + fields->f_perm = value; + break; + case MT_OPERAND_RBBC : + fields->f_rbbc = value; + break; + case MT_OPERAND_RC : + fields->f_rc = value; + break; + case MT_OPERAND_RC1 : + fields->f_rc1 = value; + break; + case MT_OPERAND_RC2 : + fields->f_rc2 = value; + break; + case MT_OPERAND_RC3 : + fields->f_rc3 = value; + break; + case MT_OPERAND_RCNUM : + fields->f_rcnum = value; + break; + case MT_OPERAND_RDA : + fields->f_rda = value; + break; + case MT_OPERAND_ROWNUM : + fields->f_rownum = value; + break; + case MT_OPERAND_ROWNUM1 : + fields->f_rownum1 = value; + break; + case MT_OPERAND_ROWNUM2 : + fields->f_rownum2 = value; + break; + case MT_OPERAND_SIZE : + fields->f_size = value; + break; + case MT_OPERAND_TYPE : + fields->f_type = value; + break; + case MT_OPERAND_WR : + fields->f_wr = value; + break; + case MT_OPERAND_XMODE : + fields->f_xmode = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +mt_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & mt_cgen_insert_handlers[0]; + cd->extract_handlers = & mt_cgen_extract_handlers[0]; + + cd->insert_operand = mt_cgen_insert_operand; + cd->extract_operand = mt_cgen_extract_operand; + + cd->get_int_operand = mt_cgen_get_int_operand; + cd->set_int_operand = mt_cgen_set_int_operand; + cd->get_vma_operand = mt_cgen_get_vma_operand; + cd->set_vma_operand = mt_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/mt-opc.c b/external/gpl3/gdb/dist/opcodes/mt-opc.c new file mode 100644 index 000000000000..498eeacbc6ff --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-opc.c @@ -0,0 +1,926 @@ +/* Instruction opcode table for mt. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mt-desc.h" +#include "mt-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "safe-ctype.h" + +/* Special check to ensure that instruction exists for given machine. */ + +int +mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + + /* No mach attribute? Assume it's supported for all machs. */ + if (machs == 0) + return 1; + + return ((machs & cd->machs) != 0); +} + +/* A better hash function for instruction mnemonics. */ + +unsigned int +mt_asm_hash (const char* insn) +{ + unsigned int hash; + const char* m = insn; + + for (hash = 0; *m && ! ISSPACE (*m); m++) + hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); + + /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ + + return hash % CGEN_ASM_HASH_SIZE; +} + + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & mt_cgen_ifld_table[MT_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addui ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldui ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brlt ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jal ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dbnz ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ei ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_si ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = { + 32, 32, 0xff0fffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stw ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldctxt ATTRIBUTE_UNUSED = { + 32, 32, 0xff000e00, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_RC) }, { F (F_RCNUM) }, { F (F_UU_3_11) }, { F (F_CONTNUM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldfb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16U) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_4_15) }, { F (F_RC) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_4_15) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcci ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcci ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbdr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_BALL2) }, { F (F_BRC2) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrcfbcb ATTRIBUTE_UNUSED = { + 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cbcast ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000380, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_UU_3_9) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dupcbcast ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_CELL) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_BANKADDR) }, { F (F_ROWNUM1) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000040, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_UU_1_6) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcrisc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc080000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_UU_1_19) }, { F (F_COLNUM) }, { F (F_DRRR) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_INCAMT) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rcxmode ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_XMODE) }, { F (F_MASK1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_interleaver ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MODE) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ID) }, { F (F_SIZE) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwfbinc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_wfbincr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwfbincr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbincs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_A23) }, { F (F_CR) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcbincs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbcbincrs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = { + 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loop ATTRIBUTE_UNUSED = { + 32, 32, 0xff0fff00, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU8) }, { F (F_LOOPO) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loopi ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_IMM16L) }, { F (F_LOOPO) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dfbc ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_RC3) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dwfb ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000080, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_UU1) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) MT_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE mt_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x0 } + }, +/* addu $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x2000000 } + }, +/* addi $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x1000000 } + }, +/* addui $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x3000000 } + }, +/* sub $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x4000000 } + }, +/* subu $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x6000000 } + }, +/* subi $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x5000000 } + }, +/* subui $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x7000000 } + }, +/* mul $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x8000000 } + }, +/* muli $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x9000000 } + }, +/* and $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x10000000 } + }, +/* andi $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x11000000 } + }, +/* or $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x12000000 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x12000000 } + }, +/* ori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x13000000 } + }, +/* xor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x14000000 } + }, +/* xori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x15000000 } + }, +/* nand $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x16000000 } + }, +/* nandi $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x17000000 } + }, +/* nor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x18000000 } + }, +/* nori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x19000000 } + }, +/* xnor $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x1a000000 } + }, +/* xnori $frdr,$frsr1,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_addui, { 0x1b000000 } + }, +/* ldui $frdr,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldui, { 0x1d000000 } + }, +/* lsl $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x20000000 } + }, +/* lsli $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x21000000 } + }, +/* lsr $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x22000000 } + }, +/* lsri $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x23000000 } + }, +/* asr $frdrrr,$frsr1,$frsr2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, + & ifmt_add, { 0x24000000 } + }, +/* asri $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x25000000 } + }, +/* brlt $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x31000000 } + }, +/* brle $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x33000000 } + }, +/* breq $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x35000000 } + }, +/* brne $frsr1,$frsr2,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, + & ifmt_brlt, { 0x3b000000 } + }, +/* jmp $imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (IMM16O), 0 } }, + & ifmt_jmp, { 0x37000000 } + }, +/* jal $frdrrr,$frsr1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), 0 } }, + & ifmt_jal, { 0x38000000 } + }, +/* dbnz $frsr1,$imm16o */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (IMM16O), 0 } }, + & ifmt_dbnz, { 0x3d000000 } + }, +/* ei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ei, { 0x60000000 } + }, +/* di */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ei, { 0x62000000 } + }, +/* si $frdrrr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), 0 } }, + & ifmt_si, { 0x64000000 } + }, +/* reti $frsr1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), 0 } }, + & ifmt_reti, { 0x66000000 } + }, +/* ldw $frdr,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_addi, { 0x41000000 } + }, +/* stw $frsr2,$frsr1,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, + & ifmt_stw, { 0x43000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x68000000 } + }, +/* iflush */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x6a000000 } + }, +/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RC), ',', '#', OP (RCNUM), ',', '#', OP (CONTNUM), 0 } }, + & ifmt_ldctxt, { 0x80000000 } + }, +/* ldfb $frsr1,$frsr2,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldfb, { 0x84000000 } + }, +/* stfb $frsr1,$frsr2,#$imm16z */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, + & ifmt_ldfb, { 0x88000000 } + }, +/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcb, { 0x8c000000 } + }, +/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcb, { 0x90000000 } + }, +/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x94000000 } + }, +/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x98000000 } + }, +/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0x9c000000 } + }, +/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcci, { 0xa0000000 } + }, +/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xa4000000 } + }, +/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xa8000000 } + }, +/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xac000000 } + }, +/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcci, { 0xb0000000 } + }, +/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbdr, { 0xb4000000 } + }, +/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcfbcb, { 0xb8000000 } + }, +/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mrcfbcb, { 0xbc000000 } + }, +/* cbcast #$mask,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_cbcast, { 0xc0000000 } + }, +/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (CELL), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dupcbcast, { 0xc4000000 } + }, +/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (BANKADDR), ',', '#', OP (ROWNUM1), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbi, { 0xc8000000 } + }, +/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfb, { 0xcc000000 } + }, +/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRDRRR), ',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcrisc, { 0xd0000000 } + }, +/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbinc, { 0xd4000000 } + }, +/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_rcxmode, { 0xd8000000 } + }, +/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (MODE), ',', OP (FRSR2), ',', '#', OP (ID), ',', '#', OP (SIZE), 0 } }, + & ifmt_interleaver, { 0xdc000000 } + }, +/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbinc, { 0xe0000000 } + }, +/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mwfbinc, { 0xe4000000 } + }, +/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_wfbincr, { 0xe8000000 } + }, +/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mwfbincr, { 0xec000000 } + }, +/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (PERM), ',', '#', OP (A23), ',', '#', OP (CR), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbincs, { 0xf0000000 } + }, +/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcbincs, { 0xf4000000 } + }, +/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_fbcbincrs, { 0xf8000000 } + }, +/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_mfbcbincrs, { 0xfc000000 } + }, +/* loop $frsr1,$loopsize */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRSR1), ',', OP (LOOPSIZE), 0 } }, + & ifmt_loop, { 0x3e000000 } + }, +/* loopi #$imm16l,$loopsize */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM16L), ',', OP (LOOPSIZE), 0 } }, + & ifmt_loopi, { 0x3f000000 } + }, +/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dfbc, { 0x80000000 } + }, +/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dwfb, { 0x84000000 } + }, +/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dfbc, { 0x88000000 } + }, +/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', OP (FRSR2), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, + & ifmt_dfbr, { 0x8c000000 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & mt_cgen_ifld_table[MT_##f] +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) MT_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE mt_cgen_macro_insn_table[] = +{ +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE mt_cgen_macro_insn_opcode_table[] = +{ +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +mt_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (mt_cgen_macro_insn_table) / + sizeof (mt_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & mt_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & mt_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + /* This test has been added to avoid a warning generated + if memset is called with a third argument of value zero. */ + if (num_macros >= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + mt_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & mt_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + mt_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/mt-opc.h b/external/gpl3/gdb/dist/opcodes/mt-opc.h new file mode 100644 index 000000000000..58b2ee96cf4a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/mt-opc.h @@ -0,0 +1,179 @@ +/* Instruction opcode header for mt. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MT_OPC_H +#define MT_OPC_H + +/* -- opc.h */ + +/* Check applicability of instructions against machines. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) + +#define CGEN_ASM_HASH_SIZE 127 +#define CGEN_ASM_HASH(insn) mt_asm_hash (insn) + +extern unsigned int mt_asm_hash (const char *); + +extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + + +/* -- opc.c */ +/* Enum declaration for mt instruction types. */ +typedef enum cgen_insn_type { + MT_INSN_INVALID, MT_INSN_ADD, MT_INSN_ADDU, MT_INSN_ADDI + , MT_INSN_ADDUI, MT_INSN_SUB, MT_INSN_SUBU, MT_INSN_SUBI + , MT_INSN_SUBUI, MT_INSN_MUL, MT_INSN_MULI, MT_INSN_AND + , MT_INSN_ANDI, MT_INSN_OR, MT_INSN_NOP, MT_INSN_ORI + , MT_INSN_XOR, MT_INSN_XORI, MT_INSN_NAND, MT_INSN_NANDI + , MT_INSN_NOR, MT_INSN_NORI, MT_INSN_XNOR, MT_INSN_XNORI + , MT_INSN_LDUI, MT_INSN_LSL, MT_INSN_LSLI, MT_INSN_LSR + , MT_INSN_LSRI, MT_INSN_ASR, MT_INSN_ASRI, MT_INSN_BRLT + , MT_INSN_BRLE, MT_INSN_BREQ, MT_INSN_BRNE, MT_INSN_JMP + , MT_INSN_JAL, MT_INSN_DBNZ, MT_INSN_EI, MT_INSN_DI + , MT_INSN_SI, MT_INSN_RETI, MT_INSN_LDW, MT_INSN_STW + , MT_INSN_BREAK, MT_INSN_IFLUSH, MT_INSN_LDCTXT, MT_INSN_LDFB + , MT_INSN_STFB, MT_INSN_FBCB, MT_INSN_MFBCB, MT_INSN_FBCCI + , MT_INSN_FBRCI, MT_INSN_FBCRI, MT_INSN_FBRRI, MT_INSN_MFBCCI + , MT_INSN_MFBRCI, MT_INSN_MFBCRI, MT_INSN_MFBRRI, MT_INSN_FBCBDR + , MT_INSN_RCFBCB, MT_INSN_MRCFBCB, MT_INSN_CBCAST, MT_INSN_DUPCBCAST + , MT_INSN_WFBI, MT_INSN_WFB, MT_INSN_RCRISC, MT_INSN_FBCBINC + , MT_INSN_RCXMODE, MT_INSN_INTERLEAVER, MT_INSN_WFBINC, MT_INSN_MWFBINC + , MT_INSN_WFBINCR, MT_INSN_MWFBINCR, MT_INSN_FBCBINCS, MT_INSN_MFBCBINCS + , MT_INSN_FBCBINCRS, MT_INSN_MFBCBINCRS, MT_INSN_LOOP, MT_INSN_LOOPI + , MT_INSN_DFBC, MT_INSN_DWFB, MT_INSN_FBWFB, MT_INSN_DFBR +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID MT_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) MT_INSN_DFBR + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_msys; + long f_opc; + long f_imm; + long f_uu24; + long f_sr1; + long f_sr2; + long f_dr; + long f_drrr; + long f_imm16u; + long f_imm16s; + long f_imm16a; + long f_uu4a; + long f_uu4b; + long f_uu12; + long f_uu8; + long f_uu16; + long f_uu1; + long f_msopc; + long f_uu_26_25; + long f_mask; + long f_bankaddr; + long f_rda; + long f_uu_2_25; + long f_rbbc; + long f_perm; + long f_mode; + long f_uu_1_24; + long f_wr; + long f_fbincr; + long f_uu_2_23; + long f_xmode; + long f_a23; + long f_mask1; + long f_cr; + long f_type; + long f_incamt; + long f_cbs; + long f_uu_1_19; + long f_ball; + long f_colnum; + long f_brc; + long f_incr; + long f_fbdisp; + long f_uu_4_15; + long f_length; + long f_uu_1_15; + long f_rc; + long f_rcnum; + long f_rownum; + long f_cbx; + long f_id; + long f_size; + long f_rownum1; + long f_uu_3_11; + long f_rc1; + long f_ccb; + long f_cbrb; + long f_cdb; + long f_rownum2; + long f_cell; + long f_uu_3_9; + long f_contnum; + long f_uu_1_6; + long f_dup; + long f_rc2; + long f_ctxdisp; + long f_imm16l; + long f_loopo; + long f_cb1sel; + long f_cb2sel; + long f_cb1incr; + long f_cb2incr; + long f_rc3; + long f_msysfrsr2; + long f_brc2; + long f_ball2; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* MT_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/ns32k-dis.c b/external/gpl3/gdb/dist/opcodes/ns32k-dis.c new file mode 100644 index 000000000000..ed6e165073cc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ns32k-dis.c @@ -0,0 +1,866 @@ +/* Print National Semiconductor 32000 instructions. + Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002, 2005, 2007, + 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "dis-asm.h" +#if !defined(const) && !defined(__STDC__) +#define const +#endif +#include "opcode/ns32k.h" +#include "opintl.h" + +static disassemble_info *dis_info; + +/* Hacks to get it to compile <= READ THESE AS FIXES NEEDED. */ +#define INVALID_FLOAT(val, size) invalid_float ((bfd_byte *) val, size) + +static long +read_memory_integer (unsigned char * addr, int nr) +{ + long val; + int i; + + for (val = 0, i = nr - 1; i >= 0; i--) + { + val = (val << 8); + val |= (0xff & *(addr + i)); + } + return val; +} + +/* 32000 instructions are never longer than this. */ +#define MAXLEN 62 + +#include + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte *max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + struct private *priv = (struct private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + return 1; +} + +/* Number of elements in the opcode table. */ +#define NOPCODES (sizeof ns32k_opcodes / sizeof ns32k_opcodes[0]) + +#define NEXT_IS_ADDR '|' + + +struct ns32k_option +{ + char *pattern; /* The option itself. */ + unsigned long value; /* Binary value of the option. */ + unsigned long match; /* These bits must match. */ +}; + + +static const struct ns32k_option opt_u[]= /* Restore, exit. */ +{ + { "r0", 0x80, 0x80 }, + { "r1", 0x40, 0x40 }, + { "r2", 0x20, 0x20 }, + { "r3", 0x10, 0x10 }, + { "r4", 0x08, 0x08 }, + { "r5", 0x04, 0x04 }, + { "r6", 0x02, 0x02 }, + { "r7", 0x01, 0x01 }, + { 0 , 0x00, 0x00 } +}; + +static const struct ns32k_option opt_U[]= /* Save, enter. */ +{ + { "r0", 0x01, 0x01 }, + { "r1", 0x02, 0x02 }, + { "r2", 0x04, 0x04 }, + { "r3", 0x08, 0x08 }, + { "r4", 0x10, 0x10 }, + { "r5", 0x20, 0x20 }, + { "r6", 0x40, 0x40 }, + { "r7", 0x80, 0x80 }, + { 0 , 0x00, 0x00 } +}; + +static const struct ns32k_option opt_O[]= /* Setcfg. */ +{ + { "c", 0x8, 0x8 }, + { "m", 0x4, 0x4 }, + { "f", 0x2, 0x2 }, + { "i", 0x1, 0x1 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option opt_C[]= /* Cinv. */ +{ + { "a", 0x4, 0x4 }, + { "i", 0x2, 0x2 }, + { "d", 0x1, 0x1 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option opt_S[]= /* String inst. */ +{ + { "b", 0x1, 0x1 }, + { "u", 0x6, 0x6 }, + { "w", 0x2, 0x2 }, + { 0 , 0x0, 0x0 } +}; + +static const struct ns32k_option list_P532[]= /* Lpr spr. */ +{ + { "us", 0x0, 0xf }, + { "dcr", 0x1, 0xf }, + { "bpc", 0x2, 0xf }, + { "dsr", 0x3, 0xf }, + { "car", 0x4, 0xf }, + { "fp", 0x8, 0xf }, + { "sp", 0x9, 0xf }, + { "sb", 0xa, 0xf }, + { "usp", 0xb, 0xf }, + { "cfg", 0xc, 0xf }, + { "psr", 0xd, 0xf }, + { "intbase", 0xe, 0xf }, + { "mod", 0xf, 0xf }, + { 0 , 0x00, 0xf } +}; + +static const struct ns32k_option list_M532[]= /* Lmr smr. */ +{ + { "mcr", 0x9, 0xf }, + { "msr", 0xa, 0xf }, + { "tear", 0xb, 0xf }, + { "ptb0", 0xc, 0xf }, + { "ptb1", 0xd, 0xf }, + { "ivar0", 0xe, 0xf }, + { "ivar1", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + +static const struct ns32k_option list_P032[]= /* Lpr spr. */ +{ + { "upsr", 0x0, 0xf }, + { "fp", 0x8, 0xf }, + { "sp", 0x9, 0xf }, + { "sb", 0xa, 0xf }, + { "psr", 0xb, 0xf }, + { "intbase", 0xe, 0xf }, + { "mod", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + +static const struct ns32k_option list_M032[]= /* Lmr smr. */ +{ + { "bpr0", 0x0, 0xf }, + { "bpr1", 0x1, 0xf }, + { "pf0", 0x4, 0xf }, + { "pf1", 0x5, 0xf }, + { "sc", 0x8, 0xf }, + { "msr", 0xa, 0xf }, + { "bcnt", 0xb, 0xf }, + { "ptb0", 0xc, 0xf }, + { "ptb1", 0xd, 0xf }, + { "eia", 0xf, 0xf }, + { 0 , 0x0, 0xf } +}; + + +/* Figure out which options are present. */ + +static void +optlist (int options, const struct ns32k_option * optionP, char * result) +{ + if (options == 0) + { + sprintf (result, "[]"); + return; + } + + sprintf (result, "["); + + for (; (options != 0) && optionP->pattern; optionP++) + { + if ((options & optionP->match) == optionP->value) + { + /* We found a match, update result and options. */ + strcat (result, optionP->pattern); + options &= ~optionP->value; + if (options != 0) /* More options to come. */ + strcat (result, ","); + } + } + + if (options != 0) + strcat (result, "undefined"); + + strcat (result, "]"); +} + +static void +list_search (int reg_value, const struct ns32k_option *optionP, char *result) +{ + for (; optionP->pattern; optionP++) + { + if ((reg_value & optionP->match) == optionP->value) + { + sprintf (result, "%s", optionP->pattern); + return; + } + } + sprintf (result, "undefined"); +} + +/* Extract "count" bits starting "offset" bits into buffer. */ + +static int +bit_extract (bfd_byte *buffer, int offset, int count) +{ + int result; + int bit; + + buffer += offset >> 3; + offset &= 7; + bit = 1; + result = 0; + while (count--) + { + FETCH_DATA (dis_info, buffer + 1); + if ((*buffer & (1 << offset))) + result |= bit; + if (++offset == 8) + { + offset = 0; + buffer++; + } + bit <<= 1; + } + return result; +} + +/* Like bit extract but the buffer is valid and doen't need to be fetched. */ + +static int +bit_extract_simple (bfd_byte *buffer, int offset, int count) +{ + int result; + int bit; + + buffer += offset >> 3; + offset &= 7; + bit = 1; + result = 0; + while (count--) + { + if ((*buffer & (1 << offset))) + result |= bit; + if (++offset == 8) + { + offset = 0; + buffer++; + } + bit <<= 1; + } + return result; +} + +static void +bit_copy (bfd_byte *buffer, int offset, int count, char *to) +{ + for (; count > 8; count -= 8, to++, offset += 8) + *to = bit_extract (buffer, offset, 8); + *to = bit_extract (buffer, offset, count); +} + +static int +sign_extend (int value, int bits) +{ + value = value & ((1 << bits) - 1); + return (value & (1 << (bits - 1)) + ? value | (~((1 << bits) - 1)) + : value); +} + +static void +flip_bytes (char *ptr, int count) +{ + char tmp; + + while (count > 0) + { + tmp = ptr[0]; + ptr[0] = ptr[count - 1]; + ptr[count - 1] = tmp; + ptr++; + count -= 2; + } +} + +/* Given a character C, does it represent a general addressing mode? */ +#define Is_gen(c) \ + ((c) == 'F' || (c) == 'L' || (c) == 'B' \ + || (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z') + +/* Adressing modes. */ +#define Adrmod_index_byte 0x1c +#define Adrmod_index_word 0x1d +#define Adrmod_index_doubleword 0x1e +#define Adrmod_index_quadword 0x1f + +/* Is MODE an indexed addressing mode? */ +#define Adrmod_is_index(mode) \ + ( mode == Adrmod_index_byte \ + || mode == Adrmod_index_word \ + || mode == Adrmod_index_doubleword \ + || mode == Adrmod_index_quadword) + + +static int +get_displacement (bfd_byte *buffer, int *aoffsetp) +{ + int Ivalue; + short Ivalue2; + + Ivalue = bit_extract (buffer, *aoffsetp, 8); + switch (Ivalue & 0xc0) + { + case 0x00: + case 0x40: + Ivalue = sign_extend (Ivalue, 7); + *aoffsetp += 8; + break; + case 0x80: + Ivalue2 = bit_extract (buffer, *aoffsetp, 16); + flip_bytes ((char *) & Ivalue2, 2); + Ivalue = sign_extend (Ivalue2, 14); + *aoffsetp += 16; + break; + case 0xc0: + Ivalue = bit_extract (buffer, *aoffsetp, 32); + flip_bytes ((char *) & Ivalue, 4); + Ivalue = sign_extend (Ivalue, 30); + *aoffsetp += 32; + break; + } + return Ivalue; +} + +#if 1 /* A version that should work on ns32k f's&d's on any machine. */ +static int +invalid_float (bfd_byte *p, int len) +{ + int val; + + if (len == 4) + val = (bit_extract_simple (p, 23, 8)/*exponent*/ == 0xff + || (bit_extract_simple (p, 23, 8)/*exponent*/ == 0 + && bit_extract_simple (p, 0, 23)/*mantisa*/ != 0)); + else if (len == 8) + val = (bit_extract_simple (p, 52, 11)/*exponent*/ == 0x7ff + || (bit_extract_simple (p, 52, 11)/*exponent*/ == 0 + && (bit_extract_simple (p, 0, 32)/*low mantisa*/ != 0 + || bit_extract_simple (p, 32, 20)/*high mantisa*/ != 0))); + else + val = 1; + return (val); +} +#else +/* Assumes the bytes have been swapped to local order. */ +typedef union +{ + double d; + float f; + struct { unsigned m:23, e:8, :1;} sf; + struct { unsigned lm; unsigned m:20, e:11, :1;} sd; +} float_type_u; + +static int +invalid_float (float_type_u *p, int len) +{ + int val; + + if (len == sizeof (float)) + val = (p->sf.e == 0xff + || (p->sf.e == 0 && p->sf.m != 0)); + else if (len == sizeof (double)) + val = (p->sd.e == 0x7ff + || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0))); + else + val = 1; + return val; +} +#endif + +/* Print an instruction operand of category given by d. IOFFSET is + the bit position below which small (<1 byte) parts of the operand can + be found (usually in the basic instruction, but for indexed + addressing it can be in the index byte). AOFFSETP is a pointer to the + bit position of the addressing extension. BUFFER contains the + instruction. ADDR is where BUFFER was read from. Put the disassembled + version of the operand in RESULT. INDEX_OFFSET is the bit position + of the index byte (it contains garbage if this operand is not a + general operand using scaled indexed addressing mode). */ + +static int +print_insn_arg (int d, + int ioffset, + int *aoffsetp, + bfd_byte *buffer, + bfd_vma addr, + char *result, + int index_offset) +{ + union + { + float f; + double d; + int i[2]; + } value; + int Ivalue; + int addr_mode; + int disp1, disp2; + int size; + + switch (d) + { + case 'f': + /* A "gen" operand but 5 bits from the end of instruction. */ + ioffset -= 5; + case 'Z': + case 'F': + case 'L': + case 'I': + case 'B': + case 'W': + case 'D': + case 'A': + addr_mode = bit_extract (buffer, ioffset - 5, 5); + ioffset -= 5; + switch (addr_mode) + { + case 0x0: case 0x1: case 0x2: case 0x3: + case 0x4: case 0x5: case 0x6: case 0x7: + /* Register mode R0 -- R7. */ + switch (d) + { + case 'F': + case 'L': + case 'Z': + sprintf (result, "f%d", addr_mode); + break; + default: + sprintf (result, "r%d", addr_mode); + } + break; + case 0x8: case 0x9: case 0xa: case 0xb: + case 0xc: case 0xd: case 0xe: case 0xf: + /* Register relative disp(R0 -- R7). */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(r%d)", disp1, addr_mode & 7); + break; + case 0x10: + case 0x11: + case 0x12: + /* Memory relative disp2(disp1(FP, SP, SB)). */ + disp1 = get_displacement (buffer, aoffsetp); + disp2 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(%d(%s))", disp2, disp1, + addr_mode == 0x10 ? "fp" : addr_mode == 0x11 ? "sp" : "sb"); + break; + case 0x13: + /* Reserved. */ + sprintf (result, "reserved"); + break; + case 0x14: + /* Immediate. */ + switch (d) + { + case 'I': + case 'Z': + case 'A': + /* I and Z are output operands and can`t be immediate + A is an address and we can`t have the address of + an immediate either. We don't know how much to increase + aoffsetp by since whatever generated this is broken + anyway! */ + sprintf (result, _("$")); + break; + case 'B': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + Ivalue = sign_extend (Ivalue, 8); + *aoffsetp += 8; + sprintf (result, "$%d", Ivalue); + break; + case 'W': + Ivalue = bit_extract (buffer, *aoffsetp, 16); + flip_bytes ((char *) & Ivalue, 2); + *aoffsetp += 16; + Ivalue = sign_extend (Ivalue, 16); + sprintf (result, "$%d", Ivalue); + break; + case 'D': + Ivalue = bit_extract (buffer, *aoffsetp, 32); + flip_bytes ((char *) & Ivalue, 4); + *aoffsetp += 32; + sprintf (result, "$%d", Ivalue); + break; + case 'F': + bit_copy (buffer, *aoffsetp, 32, (char *) &value.f); + flip_bytes ((char *) &value.f, 4); + *aoffsetp += 32; + if (INVALID_FLOAT (&value.f, 4)) + sprintf (result, "<>", value.i[0]); + else /* Assume host has ieee float. */ + sprintf (result, "$%g", value.f); + break; + case 'L': + bit_copy (buffer, *aoffsetp, 64, (char *) &value.d); + flip_bytes ((char *) &value.d, 8); + *aoffsetp += 64; + if (INVALID_FLOAT (&value.d, 8)) + sprintf (result, "<>", + value.i[1], value.i[0]); + else /* Assume host has ieee float. */ + sprintf (result, "$%g", value.d); + break; + } + break; + case 0x15: + /* Absolute @disp. */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "@|%d|", disp1); + break; + case 0x16: + /* External EXT(disp1) + disp2 (Mod table stuff). */ + disp1 = get_displacement (buffer, aoffsetp); + disp2 = get_displacement (buffer, aoffsetp); + sprintf (result, "EXT(%d) + %d", disp1, disp2); + break; + case 0x17: + /* Top of stack tos. */ + sprintf (result, "tos"); + break; + case 0x18: + /* Memory space disp(FP). */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(fp)", disp1); + break; + case 0x19: + /* Memory space disp(SP). */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(sp)", disp1); + break; + case 0x1a: + /* Memory space disp(SB). */ + disp1 = get_displacement (buffer, aoffsetp); + sprintf (result, "%d(sb)", disp1); + break; + case 0x1b: + /* Memory space disp(PC). */ + disp1 = get_displacement (buffer, aoffsetp); + *result++ = NEXT_IS_ADDR; + sprintf_vma (result, addr + disp1); + result += strlen (result); + *result++ = NEXT_IS_ADDR; + *result = '\0'; + break; + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + int bit_index; + static const char *ind = "bwdq"; + char *off; + + /* Scaled index basemode[R0 -- R7:B,W,D,Q]. */ + bit_index = bit_extract (buffer, index_offset - 8, 3); + print_insn_arg (d, index_offset, aoffsetp, buffer, addr, + result, 0); + off = result + strlen (result); + sprintf (off, "[r%d:%c]", bit_index, ind[addr_mode & 3]); + } + break; + } + break; + case 'H': + case 'q': + Ivalue = bit_extract (buffer, ioffset-4, 4); + Ivalue = sign_extend (Ivalue, 4); + sprintf (result, "%d", Ivalue); + ioffset -= 4; + break; + case 'r': + Ivalue = bit_extract (buffer, ioffset-3, 3); + sprintf (result, "r%d", Ivalue&7); + ioffset -= 3; + break; + case 'd': + sprintf (result, "%d", get_displacement (buffer, aoffsetp)); + break; + case 'b': + Ivalue = get_displacement (buffer, aoffsetp); + /* Warning!! HACK ALERT! + Operand type 'b' is only used by the cmp{b,w,d} and + movm{b,w,d} instructions; we need to know whether + it's a `b' or `w' or `d' instruction; and for both + cmpm and movm it's stored at the same place so we + just grab two bits of the opcode and look at it... */ + size = bit_extract(buffer, ioffset-6, 2); + if (size == 0) /* 00 => b. */ + size = 1; + else if (size == 1) /* 01 => w. */ + size = 2; + else + size = 4; /* 11 => d. */ + + sprintf (result, "%d", (Ivalue / size) + 1); + break; + case 'p': + *result++ = NEXT_IS_ADDR; + sprintf_vma (result, addr + get_displacement (buffer, aoffsetp)); + result += strlen (result); + *result++ = NEXT_IS_ADDR; + *result = '\0'; + break; + case 'i': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + *aoffsetp += 8; + sprintf (result, "0x%x", Ivalue); + break; + case 'u': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + optlist (Ivalue, opt_u, result); + *aoffsetp += 8; + break; + case 'U': + Ivalue = bit_extract (buffer, *aoffsetp, 8); + optlist (Ivalue, opt_U, result); + *aoffsetp += 8; + break; + case 'O': + Ivalue = bit_extract (buffer, ioffset - 9, 9); + optlist (Ivalue, opt_O, result); + ioffset -= 9; + break; + case 'C': + Ivalue = bit_extract (buffer, ioffset - 4, 4); + optlist (Ivalue, opt_C, result); + ioffset -= 4; + break; + case 'S': + Ivalue = bit_extract (buffer, ioffset - 8, 8); + optlist (Ivalue, opt_S, result); + ioffset -= 8; + break; + case 'M': + Ivalue = bit_extract (buffer, ioffset - 4, 4); + list_search (Ivalue, 0 ? list_M032 : list_M532, result); + ioffset -= 4; + break; + case 'P': + Ivalue = bit_extract (buffer, ioffset - 4, 4); + list_search (Ivalue, 0 ? list_P032 : list_P532, result); + ioffset -= 4; + break; + case 'g': + Ivalue = bit_extract (buffer, *aoffsetp, 3); + sprintf (result, "%d", Ivalue); + *aoffsetp += 3; + break; + case 'G': + Ivalue = bit_extract(buffer, *aoffsetp, 5); + sprintf (result, "%d", Ivalue + 1); + *aoffsetp += 5; + break; + } + return ioffset; +} + + +/* Print the 32000 instruction at address MEMADDR in debugged memory, + on STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_ns32k (bfd_vma memaddr, disassemble_info *info) +{ + unsigned int i; + const char *d; + unsigned short first_word; + int ioffset; /* Bits into instruction. */ + int aoffset; /* Bits into arguments. */ + char arg_bufs[MAX_ARGS+1][ARG_LEN]; + int argnum; + int maxarg; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + dis_info = info; + + info->private_data = & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Look for 8bit opcodes first. Other wise, fetching two bytes could take + us over the end of accessible data unnecessarilly. */ + FETCH_DATA (info, buffer + 1); + for (i = 0; i < NOPCODES; i++) + if (ns32k_opcodes[i].opcode_id_size <= 8 + && ((buffer[0] + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed)) + break; + if (i == NOPCODES) + { + /* Maybe it is 9 to 16 bits big. */ + FETCH_DATA (info, buffer + 2); + first_word = read_memory_integer(buffer, 2); + + for (i = 0; i < NOPCODES; i++) + if ((first_word + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed) + break; + + /* Handle undefined instructions. */ + if (i == NOPCODES) + { + (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]); + return 1; + } + } + + (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name); + + ioffset = ns32k_opcodes[i].opcode_size; + aoffset = ns32k_opcodes[i].opcode_size; + d = ns32k_opcodes[i].operands; + + if (*d) + { + /* Offset in bits of the first thing beyond each index byte. + Element 0 is for operand A and element 1 is for operand B. + The rest are irrelevant, but we put them here so we don't + index outside the array. */ + int index_offset[MAX_ARGS]; + + /* 0 for operand A, 1 for operand B, greater for other args. */ + int whicharg = 0; + + (*dis_info->fprintf_func)(dis_info->stream, "\t"); + + maxarg = 0; + + /* First we have to find and keep track of the index bytes, + if we are using scaled indexed addressing mode, since the index + bytes occur right after the basic instruction, not as part + of the addressing extension. */ + if (Is_gen(d[1])) + { + int addr_mode = bit_extract (buffer, ioffset - 5, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[0] = aoffset; + } + } + + if (d[2] && Is_gen(d[3])) + { + int addr_mode = bit_extract (buffer, ioffset - 10, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[1] = aoffset; + } + } + + while (*d) + { + argnum = *d - '1'; + d++; + if (argnum > maxarg && argnum < MAX_ARGS) + maxarg = argnum; + ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer, + memaddr, arg_bufs[argnum], + index_offset[whicharg]); + d++; + whicharg++; + } + for (argnum = 0; argnum <= maxarg; argnum++) + { + bfd_vma addr; + char *ch; + + for (ch = arg_bufs[argnum]; *ch;) + { + if (*ch == NEXT_IS_ADDR) + { + ++ch; + addr = bfd_scan_vma (ch, NULL, 16); + (*dis_info->print_address_func) (addr, dis_info); + while (*ch && *ch != NEXT_IS_ADDR) + ++ch; + if (*ch) + ++ch; + } + else + (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++); + } + if (argnum < maxarg) + (*dis_info->fprintf_func)(dis_info->stream, ", "); + } + } + return aoffset / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/opc2c.c b/external/gpl3/gdb/dist/opcodes/opc2c.c new file mode 100644 index 000000000000..7ed4c30d2359 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/opc2c.c @@ -0,0 +1,812 @@ +/* opc2c.c --- generate C opcode decoder code from from .opc file + + Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by Red Hat, Inc. + + This file is part of the GNU opcode library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + + +#include +#include +#include +#include +#include +#include "libiberty.h" + +static char * line_buf = NULL; +static int line_buf_size = 0; + +#define LBUFINCR 100 + +char * +safe_fgets (FILE * f) +{ + char * line_ptr; + + if (line_buf == NULL) + { + line_buf = (char *) malloc (LBUFINCR); + line_buf_size = LBUFINCR; + } + + /* Points to last byte. */ + line_ptr = line_buf + line_buf_size - 1; + + /* So we can see if fgets put a 0 there. */ + *line_ptr = 1; + if (fgets (line_buf, line_buf_size, f) == 0) + return NULL; + + /* We filled the buffer? */ + while (line_ptr[0] == 0 && line_ptr[-1] != '\n') + { + /* Make the buffer bigger and read more of the line. */ + line_buf_size += LBUFINCR; + line_buf = (char *) realloc (line_buf, line_buf_size); + + /* Points to last byte again. */ + line_ptr = line_buf + line_buf_size - 1; + /* So we can see if fgets put a 0 there. */ + *line_ptr = 1; + + if (fgets (line_buf + line_buf_size - LBUFINCR - 1, LBUFINCR + 1, f) == 0) + return NULL; + } + + return line_buf; +} + + +static int errors = 0; + +#define MAX_BYTES 10 + +typedef struct +{ + int varyno:16; + int byte:8; + int shift:8; +} VaryRef; + +typedef struct +{ + char nbytes; + char dbytes; + char id[MAX_BYTES * 8 + 1]; + unsigned char var_start[MAX_BYTES * 8 + 1]; + struct + { + unsigned char decodable_mask; + unsigned char decodable_bits; + } b[MAX_BYTES]; + char * comment; + char * syntax; + int lineno; + int nlines; + char ** lines; + struct Indirect * last_ind; + int semantics_label; + int nvaries; + VaryRef * vary; +} opcode; + +int n_opcodes; +opcode ** opcodes; +opcode * op; + +typedef struct +{ + char * name; + int nlen; + unsigned char mask; + int n_patterns; + unsigned char * patterns; +} Vary; + +Vary ** vary = 0; +int n_varies = 0; + +unsigned char cur_bits[MAX_BYTES + 1]; + +char * orig_filename; + +FILE * sim_log = NULL; +#define lprintf if (sim_log) fprintf + +opcode prefix_text, suffix_text; + +typedef enum +{ + T_unused, + T_op, + T_indirect, + T_done +} OpType; + +typedef struct Indirect +{ + OpType type; + union + { + struct Indirect * ind; + opcode * op; + } u; +} Indirect; + +Indirect indirect[256]; + +static int +next_varybits (int bits, opcode * op, int byte) +{ + int mask = op->b[byte].decodable_mask; + int i; + + for (i = 0; i < 8; i++) + if (!(mask & (1 << i))) + { + if (bits & (1 << i)) + { + bits &= ~(1 << i); + } + else + { + bits |= (1 << i); + return bits; + } + } + return 0; +} + +static int +valid_varybits (int bits, opcode * op, int byte) +{ + if (op->nvaries) + { + int vn; + + for (vn = 0; vn < op->nvaries; vn++) + { + Vary * v; + int found = 0; + int i; + int ob; + + if (byte != op->vary[vn].byte) + continue; + v = vary[op->vary[vn].varyno]; + ob = (bits >> op->vary[vn].shift) & v->mask; + lprintf (sim_log, "varybits: vary %s ob %x\n", v->name, ob); + + for (i = 0; i < v->n_patterns; i++) + if (ob == v->patterns[i]) + { + lprintf (sim_log, " found at %d\n", i); + found = 1; + break; + } + if (!found) + return 0; + } + } + return 1; +} + +char * +prmb (int mask, int bits) +{ + static char buf[8][30]; + static int bn = 0; + char * bp; + + bn = (bn + 1) % 8; + bp = buf[bn]; + int i; + for (i = 0; i < 8; i++) + { + int bit = 0x80 >> i; + + if (!(mask & bit)) + *bp++ = '-'; + else if (bits & bit) + *bp++ = '1'; + else + *bp++ = '0'; + if (i % 4 == 3) + *bp++ = ' '; + } + *--bp = 0; + return buf[bn]; +} + +static int +op_cmp (const void *va, const void *vb) +{ + const opcode * a = *(const opcode **) va; + const opcode * b = *(const opcode **) vb; + + if (a->nbytes != b->nbytes) + return a->nbytes - b->nbytes; + + return strcmp (a->id, b->id); +} + +void +dump_lines (opcode * op, int level, Indirect * ind) +{ + char * varnames[40]; + int i, vn = 0; + + if (op->semantics_label) + { + printf ("%*sgoto op_semantics_%d;\n", level, "", op->semantics_label); + return; + } + + if (ind != op->last_ind) + { + static int labelno = 0; + labelno++; + printf ("%*sop_semantics_%d:\n", level, "", labelno); + op->semantics_label = labelno; + } + + if (op->comment) + { + level += 2; + printf ("%*s{\n", level, ""); + printf ("%*s %s\n", level, "", op->comment); + } + + for (i = 0; i < op->nbytes * 8;) + { + if (isalpha (op->id[i])) + { + int byte = i >> 3; + int mask = 0; + int shift = 0; + char name[33]; + char * np = name; + + while (op->id[i] && isalpha (op->id[i])) + { + mask = (mask << 1) | 1; + shift = 7 - (i & 7); + *np++ = op->id[i++]; + if (op->var_start[i]) + break; + } + *np = 0; + varnames[vn++] = strdup (name); + printf ("#line %d \"%s\"\n", op->lineno + 1, orig_filename); + if (mask & ~0xff) + { + fprintf (stderr, "Error: variable %s spans bytes: %s\n", + name, op->comment); + errors++; + } + else if (shift && (mask != 0xff)) + printf ("%*s int %s AU = (op[%d] >> %d) & 0x%02x;\n", + level, "", name, byte, shift, mask); + else if (mask != 0xff) + printf ("%*s int %s AU = op[%d] & 0x%02x;\n", + level, "", name, byte, mask); + else + printf ("%*s int %s AU = op[%d];\n", level, "", name, byte); + } + else + i++; + } + + if (op->comment) + { + printf ("%*s if (trace)\n", level, ""); + printf ("%*s {\n", level, ""); + printf ("%*s printf (\"\\033[33m%%s\\033[0m ", level, ""); + for (i = 0; i < op->nbytes; i++) + printf (" %%02x"); + printf ("\\n\""); + printf (",\n%*s \"%s\"", level, "", op->comment); + for (i = 0; i < op->nbytes; i++) + { + if (i == 0) + printf (",\n%*s op[%d]", level, "", i); + else + printf (", op[%d]", i); + } + printf (");\n"); + for (i = 0; i < vn; i++) + printf ("%*s printf (\" %s = 0x%%x%s\", %s);\n", level, "", + varnames[i], (i < vn - 1) ? "," : "\\n", varnames[i]); + printf ("%*s }\n", level, ""); + } + + if (op->syntax) + printf ("%*s SYNTAX(\"%s\");\n", level, "", op->syntax); + + printf ("#line %d \"%s\"\n", op->lineno + 1, orig_filename); + + for (i = 0; i < op->nlines; i++) + printf ("%*s%s", level, "", op->lines[i]); + + if (op->comment) + printf ("%*s}\n", level, ""); +} + +void +store_opcode_bits (opcode * op, int byte, Indirect * ind) +{ + int bits = op->b[byte].decodable_bits; + + do + { + if (!valid_varybits (bits, op, byte)) + continue; + + switch (ind[bits].type) + { + case T_unused: + if (byte == op->dbytes - 1) + { + ind[bits].type = T_op; + ind[bits].u.op = op; + op->last_ind = ind; + break; + } + else + { + int i2; + + ind[bits].type = T_indirect; + ind[bits].u.ind = (Indirect *) malloc (256 * sizeof (Indirect)); + for (i2 = 0; i2 < 256; i2++) + ind[bits].u.ind[i2].type = T_unused; + store_opcode_bits (op, byte + 1, ind[bits].u.ind); + } + break; + + case T_indirect: + if (byte < op->dbytes - 1) + store_opcode_bits (op, byte + 1, ind[bits].u.ind); + break; + + case T_op: + break; + + case T_done: + break; + } + } + while ((bits = next_varybits (bits, op, byte)) != 0); +} + +void +emit_indirect (Indirect * ind, int byte) +{ + int unsup = 0; + int j, n, mask; + + mask = 0; + for (j = 0; j < 256; j++) + { + switch (ind[j].type) + { + case T_indirect: + mask = 0xff; + break; + case T_op: + mask |= ind[j].u.op->b[byte].decodable_mask; + break; + case T_done: + case T_unused: + break; + } + } + + printf ("%*s GETBYTE ();\n", byte * 6, ""); + printf ("%*s switch (op[%d] & 0x%02x)\n", byte * 6, "", byte, mask); + printf ("%*s {\n", byte * 6, ""); + + for (j = 0; j < 256; j++) + if ((j & ~mask) == 0) + { + switch (ind[j].type) + { + case T_done: + break; + case T_unused: + unsup = 1; + break; + case T_op: + for (n = j; n < 256; n++) + if ((n & ~mask) == 0 + && ind[n].type == T_op && ind[n].u.op == ind[j].u.op) + { + ind[n].type = T_done; + printf ("%*s case 0x%02x:\n", byte * 6, "", n); + } + for (n = byte; n < ind[j].u.op->nbytes - 1; n++) + printf ("%*s GETBYTE();\n", byte * 6, ""); + dump_lines (ind[j].u.op, byte * 6 + 6, ind); + printf ("%*s break;\n", byte * 6, ""); + break; + case T_indirect: + printf ("%*s case 0x%02x:\n", byte * 6, "", j); + emit_indirect (ind[j].u.ind, byte + 1); + printf ("%*s break;\n", byte * 6, ""); + break; + } + } + if (unsup) + printf ("%*s default: UNSUPPORTED(); break;\n", byte * 6, ""); + printf ("%*s }\n", byte * 6, ""); +} + +static char * +pv_dup (char * p, char * ep) +{ + int n = ep - p; + char *rv = (char *) malloc (n + 1); + + memcpy (rv, p, n); + rv[n] = 0; + return rv; +} + +static unsigned char +str2mask (char * str, char * ep) +{ + unsigned char rv = 0; + + while (str < ep) + { + rv *= 2; + if (*str == '1') + rv += 1; + str++; + } + return rv; +} + +static void +process_vary (char * line) +{ + char * cp; + char * ep; + Vary * v = (Vary *) malloc (sizeof (Vary)); + + n_varies++; + if (vary) + vary = (Vary **) realloc (vary, n_varies * sizeof (Vary *)); + else + vary = (Vary **) malloc (n_varies * sizeof (Vary *)); + vary[n_varies - 1] = v; + + cp = line; + + for (cp = line; isspace (*cp); cp++); + for (ep = cp; *ep && !isspace (*ep); ep++); + + v->name = pv_dup (cp, ep); + v->nlen = strlen (v->name); + v->mask = (1 << v->nlen) - 1; + + v->n_patterns = 0; + v->patterns = (unsigned char *) malloc (1); + while (1) + { + for (cp = ep; isspace (*cp); cp++); + if (!isdigit (*cp)) + break; + for (ep = cp; *ep && !isspace (*ep); ep++); + v->n_patterns++; + v->patterns = (unsigned char *) realloc (v->patterns, v->n_patterns); + v->patterns[v->n_patterns - 1] = str2mask (cp, ep); + } +} + +static int +fieldcmp (opcode * op, int bit, char *name) +{ + int n = strlen (name); + + if (memcmp (op->id + bit, name, n) == 0 + && (!isalpha (op->id[bit + n]) || op->var_start[bit + n])) + return 1; + return 0; +} + +static void +log_indirect (Indirect * ind, int byte) +{ + int i, j; + char * last_c = 0; + + for (i = 0; i < 256; i++) + { + + for (j = 0; j < byte; j++) + fprintf (sim_log, "%s ", prmb (255, cur_bits[j])); + fprintf (sim_log, "%s ", prmb (255, i)); + + switch (ind[i].type) + { + case T_op: + case T_done: + if (last_c && (ind[i].u.op->comment == last_c)) + fprintf (sim_log, "''\n"); + else + fprintf (sim_log, "%s\n", ind[i].u.op->comment); + last_c = ind[i].u.op->comment; + break; + case T_unused: + fprintf (sim_log, "unused\n"); + break; + case T_indirect: + fprintf (sim_log, "indirect\n"); + cur_bits[byte] = i; + log_indirect (ind[i].u.ind, byte + 1); + last_c = 0; + break; + } + } +} + +int +main (int argc, char ** argv) +{ + char * line; + FILE * in; + int lineno = 0; + int i; + VaryRef * vlist; + int skipping_section = 0; + + if (argc > 2 && strcmp (argv[1], "-l") == 0) + { + sim_log = fopen (argv[2], "w"); + fprintf (stderr, "sim_log: %s\n", argv[2]); + argc -= 2; + argv += 2; + } + + if (argc < 2) + { + fprintf (stderr, "usage: opc2c infile.opc > outfile.opc\n"); + exit (1); + } + + orig_filename = lbasename (argv[1]); + in = fopen (argv[1], "r"); + if (!in) + { + fprintf (stderr, "Unable to open file %s for reading: %s\n", argv[1], + xstrerror (errno)); + exit (1); + } + + n_opcodes = 0; + opcodes = (opcode **) malloc (sizeof (opcode *)); + op = &prefix_text; + op->lineno = 0; + while ((line = safe_fgets (in)) != 0) + { + lineno++; + if (strncmp (line, "/*?* ", 5) == 0) + { + skipping_section = 1; + continue; + } + if (strncmp (line, " /** ", 6) == 0 + && (isdigit (line[6]) || memcmp (line + 6, "VARY", 4) == 0)) + line += 2; + if (line[0] == '/' && line[1] == '*' && line[2] == '*') + { + skipping_section = 0; + if (strncmp (line, "/** */", 6) == 0) + { + op = &suffix_text; + op->lineno = lineno; + } + else if (strncmp (line, "/** VARY ", 9) == 0) + process_vary (line + 9); + else + { + char * lp; + int i, bit, byte; + int var_start = 1; + + n_opcodes++; + opcodes = + (opcode **) realloc (opcodes, n_opcodes * sizeof (opcode *)); + op = (opcode *) malloc (sizeof (opcode)); + opcodes[n_opcodes - 1] = op; + + op->nbytes = op->dbytes = 0; + memset (op->id, 0, sizeof (op->id)); + memset (op->var_start, 0, sizeof (op->var_start)); + for (i = 0; i < MAX_BYTES; i++) + { + op->b[i].decodable_mask = 0; + op->b[i].decodable_bits = 0; + } + op->comment = strdup (line); + op->comment[strlen (op->comment) - 1] = 0; + while (op->comment[0] && isspace (op->comment[0])) + op->comment++; + op->lineno = lineno; + op->nlines = 0; + op->lines = 0; + op->last_ind = 0; + op->semantics_label = 0; + op->nvaries = 0; + op->vary = 0; + + i = 0; + for (lp = line + 4; *lp; lp++) + { + bit = 7 - (i & 7); + byte = i >> 3; + + if (strncmp (lp, "*/", 2) == 0) + break; + else if ((lp[0] == ' ' && lp[1] == ' ') || (lp[0] == '\t')) + { + while (*lp == ' ' || *lp == '\t') + lp ++; + op->syntax = strdup (lp); + lp = strstr (op->syntax, "*/"); + if (lp) + { + *lp-- = 0; + while ((*lp == ' ' || *lp == '\t') + && lp > op->syntax) + *lp-- = 0; + } + break; + } + else if (*lp == ' ') + var_start = 1; + else + { + if (*lp == '0' || *lp == '1') + { + op->b[byte].decodable_mask |= 1 << bit; + var_start = 1; + if (op->dbytes < byte + 1) + op->dbytes = byte + 1; + } + else if (var_start) + { + op->var_start[i] = 1; + var_start = 0; + if (op->dbytes < byte + 1) + op->dbytes = byte + 1; + } + if (*lp == '1') + op->b[byte].decodable_bits |= 1 << bit; + + op->nbytes = byte + 1; + op->id[i++] = *lp; + } + } + } + } + else if (!skipping_section) + { + op->nlines++; + if (op->lines) + op->lines = + (char **) realloc (op->lines, op->nlines * sizeof (char *)); + else + op->lines = (char **) malloc (op->nlines * sizeof (char *)); + op->lines[op->nlines - 1] = strdup (line); + } + } + + { + int i, j; + for (i = 0; i < n_varies; i++) + { + Vary *v = vary[i]; + lprintf (sim_log, "V[%s] %d\n", v->name, v->nlen); + for (j = 0; j < v->n_patterns; j++) + lprintf (sim_log, " P %02x\n", v->patterns[j]); + } + } + + for (i = n_opcodes - 2; i >= 0; i--) + { + if (opcodes[i]->nlines == 0) + { + opcodes[i]->nlines = opcodes[i + 1]->nlines; + opcodes[i]->lines = opcodes[i + 1]->lines; + } + } + + for (i = 0; i < 256; i++) + indirect[i].type = T_unused; + + qsort (opcodes, n_opcodes, sizeof (opcodes[0]), op_cmp); + + vlist = (VaryRef *) malloc (n_varies * sizeof (VaryRef)); + + for (i = 0; i < n_opcodes; i++) + { + int j, b, v; + + for (j = 0; j < opcodes[i]->nbytes; j++) + lprintf (sim_log, "%s ", + prmb (opcodes[i]->b[j].decodable_mask, + opcodes[i]->b[j].decodable_bits)); + lprintf (sim_log, " %s\n", opcodes[i]->comment); + + for (j = 0; j < opcodes[i]->nbytes; j++) + { + for (b = 0; b < 8; b++) + if (isalpha (opcodes[i]->id[j * 8 + b])) + for (v = 0; v < n_varies; v++) + if (fieldcmp (opcodes[i], j * 8 + b, vary[v]->name)) + { + int nv = opcodes[i]->nvaries++; + if (nv) + opcodes[i]->vary = + (VaryRef *) realloc (opcodes[i]->vary, + (nv + 1) * sizeof (VaryRef)); + else + opcodes[i]->vary = + (VaryRef *) malloc ((nv + 1) * sizeof (VaryRef)); + + opcodes[i]->vary[nv].varyno = v; + opcodes[i]->vary[nv].byte = j; + opcodes[i]->vary[nv].shift = 8 - b - vary[v]->nlen; + lprintf (sim_log, "[vary %s shift %d]\n", + vary[v]->name, opcodes[i]->vary[nv].shift); + } + + } + } + + for (i = 0; i < n_opcodes; i++) + { + int i2; + int bytes = opcodes[i]->dbytes; + + lprintf (sim_log, "\nmask:"); + for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) + lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_mask); + lprintf (sim_log, "%*s%s\n", 13 - 3 * opcodes[i]->nbytes, "", + opcodes[i]->comment); + + lprintf (sim_log, "bits:"); + for (i2 = 0; i2 < opcodes[i]->nbytes; i2++) + lprintf (sim_log, " %02x", opcodes[i]->b[i2].decodable_bits); + lprintf (sim_log, "%*s(%s) %d byte%s\n", 13 - 3 * opcodes[i]->nbytes, + "", opcodes[i]->id, bytes, bytes == 1 ? "" : "s"); + + store_opcode_bits (opcodes[i], 0, indirect); + } + + dump_lines (&prefix_text, 0, 0); + + emit_indirect (indirect, 0); + + dump_lines (&suffix_text, 0, 0); + + if (sim_log) + log_indirect (indirect, 0); + + return errors; +} diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-asm.c b/external/gpl3/gdb/dist/opcodes/openrisc-asm.c new file mode 100644 index 000000000000..8aaf3746119b --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-asm.c @@ -0,0 +1,649 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +long +openrisc_sign_extend_16bit (long value) +{ + return ((value & 0xffff) ^ 0x8000) - 0x8000; +} + +/* Handle hi(). */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + unsigned long ret; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "hi(", 3) == 0) + { + bfd_vma value; + + *strp += 3; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + ret = value; + } + else + { + if (**strp == '-') + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); + ret = value; + } + else + { + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); + ret = value; + } + } + + *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; + return errmsg; +} + +/* Handle lo(). */ + +static const char * +parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + unsigned long ret; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "lo(", 3) == 0) + { + bfd_vma value; + + *strp += 3; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + + ++*strp; + ret = value; + } + else + { + if (**strp == '-') + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); + ret = value; + } + else + { + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); + ret = value; + } + } + + *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; + return errmsg; +} + +/* -- */ + +const char * openrisc_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +openrisc_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value); + fields->f_abs26 = value; + } + break; + case OPENRISC_OPERAND_DISP_26 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value); + fields->f_disp26 = value; + } + break; + case OPENRISC_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, OPENRISC_OPERAND_HI16, (long *) (& fields->f_simm16)); + break; + case OPENRISC_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_LO16, (long *) (& fields->f_lo16)); + break; + case OPENRISC_OPERAND_OP_F_23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_23, (unsigned long *) (& fields->f_op4)); + break; + case OPENRISC_OPERAND_OP_F_3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_3, (unsigned long *) (& fields->f_op5)); + break; + case OPENRISC_OPERAND_RA : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r2); + break; + case OPENRISC_OPERAND_RB : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r3); + break; + case OPENRISC_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r1); + break; + case OPENRISC_OPERAND_SIMM_16 : + errmsg = cgen_parse_signed_integer (cd, strp, OPENRISC_OPERAND_SIMM_16, (long *) (& fields->f_simm16)); + break; + case OPENRISC_OPERAND_UI16NC : + errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_UI16NC, (long *) (& fields->f_i16nc)); + break; + case OPENRISC_OPERAND_UIMM_16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_16, (unsigned long *) (& fields->f_uimm16)); + break; + case OPENRISC_OPERAND_UIMM_5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_5, (unsigned long *) (& fields->f_uimm5)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const openrisc_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +openrisc_cgen_init_asm (CGEN_CPU_DESC cd) +{ + openrisc_cgen_init_opcode_table (cd); + openrisc_cgen_init_ibld_table (cd); + cd->parse_handlers = & openrisc_cgen_parse_handlers[0]; + cd->parse_operand = openrisc_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by openrisc_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +openrisc_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! openrisc_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-desc.c b/external/gpl3/gdb/dist/opcodes/openrisc-desc.c new file mode 100644 index 000000000000..2be68f9bdb5d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-desc.c @@ -0,0 +1,1018 @@ +/* CPU data for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "openrisc", MACH_OPENRISC }, + { "or1300", MACH_OR1300 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "or32", ISA_OR32 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] ATTRIBUTE_UNUSED = +{ + { "DATA_CACHE", HAS_CACHE_DATA_CACHE }, + { "INSN_CACHE", HAS_CACHE_INSN_CACHE }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA openrisc_cgen_isa_table[] = { + { "or32", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH openrisc_cgen_mach_table[] = { + { "openrisc", "openrisc", MACH_OPENRISC, 0 }, + { "or1300", "openrisc:1300", MACH_OR1300, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD openrisc_cgen_opval_h_gr = +{ + & openrisc_cgen_opval_h_gr_entries[0], + 35, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY openrisc_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & openrisc_cgen_ifld_table[0]; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */ + +static void +openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & openrisc_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & openrisc_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = openrisc_cgen_rebuild_tables; + openrisc_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +openrisc_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-desc.h b/external/gpl3/gdb/dist/opcodes/openrisc-desc.h new file mode 100644 index 000000000000..24dcb6dcdbf5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-desc.h @@ -0,0 +1,288 @@ +/* CPU data header for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef OPENRISC_CPU_H +#define OPENRISC_CPU_H + +#define CGEN_ARCH openrisc + +/* Given symbol S, return openrisc_cgen_. */ +#define CGEN_SYM(s) openrisc##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_OPENRISCBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 + +/* Enums. */ + +/* Enum declaration for exception vectors. */ +typedef enum e_exception { + E_RESET, E_BUSERR, E_DPF, E_IPF + , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT + , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL + , E_BREAK, E_RESERVED +} E_EXCEPTION; + +/* Enum declaration for FIXME. */ +typedef enum insn_class { + OP1_0, OP1_1, OP1_2, OP1_3 +} INSN_CLASS; + +/* Enum declaration for FIXME. */ +typedef enum insn_sub { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_10, OP2_11 + , OP2_12, OP2_13, OP2_14, OP2_15 +} INSN_SUB; + +/* Enum declaration for FIXME. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 +} INSN_OP3; + +/* Enum declaration for FIXME. */ +typedef enum insn_op4 { + OP4_0, OP4_1, OP4_2, OP4_3 + , OP4_4, OP4_5, OP4_6, OP4_7 +} INSN_OP4; + +/* Enum declaration for FIXME. */ +typedef enum insn_op5 { + OP5_0, OP5_1, OP5_2, OP5_3 + , OP5_4, OP5_5, OP5_6, OP5_7 + , OP5_8, OP5_9, OP5_10, OP5_11 + , OP5_12, OP5_13, OP5_14, OP5_15 + , OP5_16, OP5_17, OP5_18, OP5_19 + , OP5_20, OP5_21, OP5_22, OP5_23 + , OP5_24, OP5_25, OP5_26, OP5_27 + , OP5_28, OP5_29, OP5_30, OP5_31 +} INSN_OP5; + +/* Enum declaration for FIXME. */ +typedef enum insn_op6 { + OP6_0, OP6_1, OP6_2, OP6_3 + , OP6_4, OP6_5, OP6_6, OP6_7 +} INSN_OP6; + +/* Enum declaration for FIXME. */ +typedef enum insn_op7 { + OP7_0, OP7_1, OP7_2, OP7_3 + , OP7_4, OP7_5, OP7_6, OP7_7 + , OP7_8, OP7_9, OP7_10, OP7_11 + , OP7_12, OP7_13, OP7_14, OP7_15 +} INSN_OP7; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_OR32, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for if this model has caches. */ +typedef enum has_cache_attr { + HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE +} HAS_CACHE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for openrisc ifield types. */ +typedef enum ifield_type { + OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB + , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16 + , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16 + , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4 + , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1 + , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC + , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3 + , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) OPENRISC_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for openrisc hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR + , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for openrisc operand types. */ +typedef enum cgen_operand_type { + OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16 + , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5 + , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23 + , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC + , OPENRISC_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 16 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld openrisc_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD openrisc_cgen_opval_h_gr; + +extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[]; + + + +#endif /* OPENRISC_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-dis.c b/external/gpl3/gdb/dist/opcodes/openrisc-dis.c new file mode 100644 index 000000000000..2c442f964a24 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-dis.c @@ -0,0 +1,556 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + + +void openrisc_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +openrisc_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + print_address (cd, info, fields->f_abs26, 0|(1<f_disp26, 0|(1<f_simm16, 0|(1<f_lo16, 0|(1<f_op4, 0, pc, length); + break; + case OPENRISC_OPERAND_OP_F_3 : + print_normal (cd, info, fields->f_op5, 0, pc, length); + break; + case OPENRISC_OPERAND_RA : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0); + break; + case OPENRISC_OPERAND_RB : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0); + break; + case OPENRISC_OPERAND_RD : + print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0); + break; + case OPENRISC_OPERAND_SIMM_16 : + print_normal (cd, info, fields->f_simm16, 0|(1<f_i16nc, 0|(1<f_uimm16, 0, pc, length); + break; + case OPENRISC_OPERAND_UIMM_5 : + print_normal (cd, info, fields->f_uimm5, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const openrisc_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +openrisc_cgen_init_dis (CGEN_CPU_DESC cd) +{ + openrisc_cgen_init_opcode_table (cd); + openrisc_cgen_init_ibld_table (cd); + cd->print_handlers = & openrisc_cgen_print_handlers[0]; + cd->print_operand = openrisc_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! openrisc_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_openrisc (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_openrisc +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + openrisc_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-ibld.c b/external/gpl3/gdb/dist/opcodes/openrisc-ibld.c new file mode 100644 index 000000000000..6a84f3275159 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-ibld.c @@ -0,0 +1,1009 @@ +/* Instruction building/extraction support for openrisc. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * openrisc_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +openrisc_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + long value = fields->f_abs26; + value = ((SI) (pc) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_disp26; + value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_simm16, 0|(1<f_lo16, 0|(1<f_op4, 0, 0, 23, 3, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_OP_F_3 : + errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RA : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RB : + errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_RD : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_SIMM_16 : + errmsg = insert_normal (cd, fields->f_simm16, 0|(1<> (11))) & (31)); + FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047)); +} + errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case OPENRISC_OPERAND_UIMM_16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case OPENRISC_OPERAND_UIMM_5 : + errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int openrisc_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +openrisc_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_abs26 = value; + } + break; + case OPENRISC_OPERAND_DISP_26 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_disp26 = value; + } + break; + case OPENRISC_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case OPENRISC_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lo16); + break; + case OPENRISC_OPERAND_OP_F_23 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4); + break; + case OPENRISC_OPERAND_OP_F_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5); + break; + case OPENRISC_OPERAND_RA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); + break; + case OPENRISC_OPERAND_RB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); + break; + case OPENRISC_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); + break; + case OPENRISC_OPERAND_SIMM_16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_simm16); + break; + case OPENRISC_OPERAND_UI16NC : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); + if (length <= 0) break; +{ + FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); +} + } + break; + case OPENRISC_OPERAND_UIMM_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case OPENRISC_OPERAND_UIMM_5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const openrisc_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const openrisc_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + value = fields->f_abs26; + break; + case OPENRISC_OPERAND_DISP_26 : + value = fields->f_disp26; + break; + case OPENRISC_OPERAND_HI16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_LO16 : + value = fields->f_lo16; + break; + case OPENRISC_OPERAND_OP_F_23 : + value = fields->f_op4; + break; + case OPENRISC_OPERAND_OP_F_3 : + value = fields->f_op5; + break; + case OPENRISC_OPERAND_RA : + value = fields->f_r2; + break; + case OPENRISC_OPERAND_RB : + value = fields->f_r3; + break; + case OPENRISC_OPERAND_RD : + value = fields->f_r1; + break; + case OPENRISC_OPERAND_SIMM_16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_UI16NC : + value = fields->f_i16nc; + break; + case OPENRISC_OPERAND_UIMM_16 : + value = fields->f_uimm16; + break; + case OPENRISC_OPERAND_UIMM_5 : + value = fields->f_uimm5; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + value = fields->f_abs26; + break; + case OPENRISC_OPERAND_DISP_26 : + value = fields->f_disp26; + break; + case OPENRISC_OPERAND_HI16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_LO16 : + value = fields->f_lo16; + break; + case OPENRISC_OPERAND_OP_F_23 : + value = fields->f_op4; + break; + case OPENRISC_OPERAND_OP_F_3 : + value = fields->f_op5; + break; + case OPENRISC_OPERAND_RA : + value = fields->f_r2; + break; + case OPENRISC_OPERAND_RB : + value = fields->f_r3; + break; + case OPENRISC_OPERAND_RD : + value = fields->f_r1; + break; + case OPENRISC_OPERAND_SIMM_16 : + value = fields->f_simm16; + break; + case OPENRISC_OPERAND_UI16NC : + value = fields->f_i16nc; + break; + case OPENRISC_OPERAND_UIMM_16 : + value = fields->f_uimm16; + break; + case OPENRISC_OPERAND_UIMM_5 : + value = fields->f_uimm5; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + fields->f_abs26 = value; + break; + case OPENRISC_OPERAND_DISP_26 : + fields->f_disp26 = value; + break; + case OPENRISC_OPERAND_HI16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_LO16 : + fields->f_lo16 = value; + break; + case OPENRISC_OPERAND_OP_F_23 : + fields->f_op4 = value; + break; + case OPENRISC_OPERAND_OP_F_3 : + fields->f_op5 = value; + break; + case OPENRISC_OPERAND_RA : + fields->f_r2 = value; + break; + case OPENRISC_OPERAND_RB : + fields->f_r3 = value; + break; + case OPENRISC_OPERAND_RD : + fields->f_r1 = value; + break; + case OPENRISC_OPERAND_SIMM_16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_UI16NC : + fields->f_i16nc = value; + break; + case OPENRISC_OPERAND_UIMM_16 : + fields->f_uimm16 = value; + break; + case OPENRISC_OPERAND_UIMM_5 : + fields->f_uimm5 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case OPENRISC_OPERAND_ABS_26 : + fields->f_abs26 = value; + break; + case OPENRISC_OPERAND_DISP_26 : + fields->f_disp26 = value; + break; + case OPENRISC_OPERAND_HI16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_LO16 : + fields->f_lo16 = value; + break; + case OPENRISC_OPERAND_OP_F_23 : + fields->f_op4 = value; + break; + case OPENRISC_OPERAND_OP_F_3 : + fields->f_op5 = value; + break; + case OPENRISC_OPERAND_RA : + fields->f_r2 = value; + break; + case OPENRISC_OPERAND_RB : + fields->f_r3 = value; + break; + case OPENRISC_OPERAND_RD : + fields->f_r1 = value; + break; + case OPENRISC_OPERAND_SIMM_16 : + fields->f_simm16 = value; + break; + case OPENRISC_OPERAND_UI16NC : + fields->f_i16nc = value; + break; + case OPENRISC_OPERAND_UIMM_16 : + fields->f_uimm16 = value; + break; + case OPENRISC_OPERAND_UIMM_5 : + fields->f_uimm5 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; + cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; + + cd->insert_operand = openrisc_cgen_insert_operand; + cd->extract_operand = openrisc_cgen_extract_operand; + + cd->get_int_operand = openrisc_cgen_get_int_operand; + cd->set_int_operand = openrisc_cgen_set_int_operand; + cd->get_vma_operand = openrisc_cgen_get_vma_operand; + cd->set_vma_operand = openrisc_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-opc.c b/external/gpl3/gdb/dist/opcodes/openrisc-opc.c new file mode 100644 index 000000000000..e6b75a378654 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-opc.c @@ -0,0 +1,682 @@ +/* Instruction opcode table for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "openrisc-desc.h" +#include "openrisc-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_l_j ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_ABS26) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_jr ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_bal ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_DISP26) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_movhi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_mfsr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_mtsr ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_I16_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_lw ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R3) }, { F (F_I16NC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_3) }, { F (F_OP6) }, { F (F_F_4_1) }, { F (F_OP7) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_slli ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffe0, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_F_15_8) }, { F (F_OP6) }, { F (F_UIMM5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_add ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_7) }, { F (F_OP7) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_addi ATTRIBUTE_UNUSED = { + 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_LO16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgts ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgtsi ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_l_sfgtui ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) OPENRISC_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE openrisc_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* l.j ${abs-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS_26), 0 } }, + & ifmt_l_j, { 0x0 } + }, +/* l.jal ${abs-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS_26), 0 } }, + & ifmt_l_j, { 0x4000000 } + }, +/* l.jr $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14000000 } + }, +/* l.jalr $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14200000 } + }, +/* l.bal ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0x8000000 } + }, +/* l.bnf ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0xc000000 } + }, +/* l.bf ${disp-26} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DISP_26), 0 } }, + & ifmt_l_bal, { 0x10000000 } + }, +/* l.brk ${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM_16), 0 } }, + & ifmt_l_jr, { 0x17000000 } + }, +/* l.rfe $rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), 0 } }, + & ifmt_l_jr, { 0x14400000 } + }, +/* l.sys ${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM_16), 0 } }, + & ifmt_l_jr, { 0x16000000 } + }, +/* l.nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_l_jr, { 0x15000000 } + }, +/* l.movhi $rD,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (HI16), 0 } }, + & ifmt_l_movhi, { 0x18000000 } + }, +/* l.mfsr $rD,$rA */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } }, + & ifmt_l_mfsr, { 0x1c000000 } + }, +/* l.mtsr $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_mtsr, { 0x40000000 } + }, +/* l.lw $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x80000000 } + }, +/* l.lbz $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x84000000 } + }, +/* l.lbs $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x88000000 } + }, +/* l.lhz $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x8c000000 } + }, +/* l.lhs $rD,${simm-16}($rA) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } }, + & ifmt_l_lw, { 0x90000000 } + }, +/* l.sw ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xd4000000 } + }, +/* l.sb ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xd8000000 } + }, +/* l.sh ${ui16nc}($rA),$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } }, + & ifmt_l_sw, { 0xdc000000 } + }, +/* l.sll $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000008 } + }, +/* l.slli $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000000 } + }, +/* l.srl $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000028 } + }, +/* l.srli $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000020 } + }, +/* l.sra $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000048 } + }, +/* l.srai $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000040 } + }, +/* l.ror $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sll, { 0xe0000088 } + }, +/* l.rori $rD,$rA,${uimm-5} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } }, + & ifmt_l_slli, { 0xb4000080 } + }, +/* l.add $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000000 } + }, +/* l.addi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0x94000000 } + }, +/* l.sub $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000002 } + }, +/* l.subi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0x9c000000 } + }, +/* l.and $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000003 } + }, +/* l.andi $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa0000000 } + }, +/* l.or $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000004 } + }, +/* l.ori $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa4000000 } + }, +/* l.xor $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000005 } + }, +/* l.xori $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xa8000000 } + }, +/* l.mul $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000006 } + }, +/* l.muli $rD,$rA,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } }, + & ifmt_l_addi, { 0xac000000 } + }, +/* l.div $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe0000009 } + }, +/* l.divu $rD,$rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_add, { 0xe000000a } + }, +/* l.sfgts $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4c00000 } + }, +/* l.sfgtu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4400000 } + }, +/* l.sfges $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4e00000 } + }, +/* l.sfgeu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4600000 } + }, +/* l.sflts $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe5000000 } + }, +/* l.sfltu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4800000 } + }, +/* l.sfles $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe5200000 } + }, +/* l.sfleu $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4a00000 } + }, +/* l.sfgtsi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8c00000 } + }, +/* l.sfgtui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8400000 } + }, +/* l.sfgesi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8e00000 } + }, +/* l.sfgeui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8600000 } + }, +/* l.sfltsi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb9000000 } + }, +/* l.sfltui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8800000 } + }, +/* l.sflesi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb9200000 } + }, +/* l.sfleui $rA,${uimm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } }, + & ifmt_l_sfgtui, { 0xb8a00000 } + }, +/* l.sfeq $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4000000 } + }, +/* l.sfeqi $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8000000 } + }, +/* l.sfne $rA,$rB */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } }, + & ifmt_l_sfgts, { 0xe4200000 } + }, +/* l.sfnei $rA,${simm-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } }, + & ifmt_l_sfgtsi, { 0xb8200000 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f] +static const CGEN_IFMT ifmt_l_ret ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) OPENRISC_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE openrisc_cgen_macro_insn_table[] = +{ +/* l.ret */ + { + -1, "l-ret", "l.ret", 32, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + openrisc_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & openrisc_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + openrisc_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/openrisc-opc.h b/external/gpl3/gdb/dist/opcodes/openrisc-opc.h new file mode 100644 index 000000000000..31fa152bd151 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/openrisc-opc.h @@ -0,0 +1,113 @@ +/* Instruction opcode header for openrisc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef OPENRISC_OPC_H +#define OPENRISC_OPC_H + +/* -- opc.h */ +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 64 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) + +extern long openrisc_sign_extend_16bit (long); +/* -- */ +/* Enum declaration for openrisc instruction types. */ +typedef enum cgen_insn_type { + OPENRISC_INSN_INVALID, OPENRISC_INSN_L_J, OPENRISC_INSN_L_JAL, OPENRISC_INSN_L_JR + , OPENRISC_INSN_L_JALR, OPENRISC_INSN_L_BAL, OPENRISC_INSN_L_BNF, OPENRISC_INSN_L_BF + , OPENRISC_INSN_L_BRK, OPENRISC_INSN_L_RFE, OPENRISC_INSN_L_SYS, OPENRISC_INSN_L_NOP + , OPENRISC_INSN_L_MOVHI, OPENRISC_INSN_L_MFSR, OPENRISC_INSN_L_MTSR, OPENRISC_INSN_L_LW + , OPENRISC_INSN_L_LBZ, OPENRISC_INSN_L_LBS, OPENRISC_INSN_L_LHZ, OPENRISC_INSN_L_LHS + , OPENRISC_INSN_L_SW, OPENRISC_INSN_L_SB, OPENRISC_INSN_L_SH, OPENRISC_INSN_L_SLL + , OPENRISC_INSN_L_SLLI, OPENRISC_INSN_L_SRL, OPENRISC_INSN_L_SRLI, OPENRISC_INSN_L_SRA + , OPENRISC_INSN_L_SRAI, OPENRISC_INSN_L_ROR, OPENRISC_INSN_L_RORI, OPENRISC_INSN_L_ADD + , OPENRISC_INSN_L_ADDI, OPENRISC_INSN_L_SUB, OPENRISC_INSN_L_SUBI, OPENRISC_INSN_L_AND + , OPENRISC_INSN_L_ANDI, OPENRISC_INSN_L_OR, OPENRISC_INSN_L_ORI, OPENRISC_INSN_L_XOR + , OPENRISC_INSN_L_XORI, OPENRISC_INSN_L_MUL, OPENRISC_INSN_L_MULI, OPENRISC_INSN_L_DIV + , OPENRISC_INSN_L_DIVU, OPENRISC_INSN_L_SFGTS, OPENRISC_INSN_L_SFGTU, OPENRISC_INSN_L_SFGES + , OPENRISC_INSN_L_SFGEU, OPENRISC_INSN_L_SFLTS, OPENRISC_INSN_L_SFLTU, OPENRISC_INSN_L_SFLES + , OPENRISC_INSN_L_SFLEU, OPENRISC_INSN_L_SFGTSI, OPENRISC_INSN_L_SFGTUI, OPENRISC_INSN_L_SFGESI + , OPENRISC_INSN_L_SFGEUI, OPENRISC_INSN_L_SFLTSI, OPENRISC_INSN_L_SFLTUI, OPENRISC_INSN_L_SFLESI + , OPENRISC_INSN_L_SFLEUI, OPENRISC_INSN_L_SFEQ, OPENRISC_INSN_L_SFEQI, OPENRISC_INSN_L_SFNE + , OPENRISC_INSN_L_SFNEI +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID OPENRISC_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) OPENRISC_INSN_L_SFNEI + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_class; + long f_sub; + long f_r1; + long f_r2; + long f_r3; + long f_simm16; + long f_uimm16; + long f_uimm5; + long f_hi16; + long f_lo16; + long f_op1; + long f_op2; + long f_op3; + long f_op4; + long f_op5; + long f_op6; + long f_op7; + long f_i16_1; + long f_i16_2; + long f_disp26; + long f_abs26; + long f_i16nc; + long f_f_15_8; + long f_f_10_3; + long f_f_4_1; + long f_f_7_3; + long f_f_10_7; + long f_f_10_11; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* OPENRISC_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/opintl.h b/external/gpl3/gdb/dist/opcodes/opintl.h new file mode 100644 index 000000000000..8ae869087d7a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/opintl.h @@ -0,0 +1,52 @@ +/* opintl.h - opcodes specific header for gettext code. + Copyright 1998, 1999, 2000, 2005, 2007, 2009 Free Software Foundation, Inc. + + Written by Tom Tromey + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifdef ENABLE_NLS +# include +/* Note the use of dgetext() and PACKAGE here, rather than gettext(). + + This is because the code in this directory is used to build a library which + will be linked with code in other directories to form programs. We want to + maintain a seperate translation file for this directory however, rather + than being forced to merge it with that of any program linked to + libopcodes. This is a library, so it cannot depend on the catalog + currently loaded. + + In order to do this, we have to make sure that when we extract messages we + use the OPCODES domain rather than the domain of the program that included + the opcodes library, (eg OBJDUMP). Hence we use dgettext (PACKAGE, String) + and define PACKAGE to be 'opcodes'. (See the code in configure). */ +# define _(String) dgettext (PACKAGE, String) +# ifdef gettext_noop +# define N_(String) gettext_noop (String) +# else +# define N_(String) (String) +# endif +#else +# define gettext(Msgid) (Msgid) +# define dgettext(Domainname, Msgid) (Msgid) +# define dcgettext(Domainname, Msgid, Category) (Msgid) +# define textdomain(Domainname) while (0) /* nothing */ +# define bindtextdomain(Domainname, Dirname) while (0) /* nothing */ +# define _(String) (String) +# define N_(String) (String) +#endif diff --git a/external/gpl3/gdb/dist/opcodes/or32-dis.c b/external/gpl3/gdb/dist/opcodes/or32-dis.c new file mode 100644 index 000000000000..a0dc92a731e3 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/or32-dis.c @@ -0,0 +1,326 @@ +/* Instruction printing code for the OpenRISC 1000 + Copyright (C) 2002, 2005, 2007 Free Software Foundation, Inc. + Contributed by Damjan Lampret . + Modified from a29k port. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef DEBUG +#define DEBUG 0 +#endif + +#include "dis-asm.h" +#include "opcode/or32.h" +#include "safe-ctype.h" +#include +#include + +#define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x))) + +/* Now find the four bytes of INSN_CH and put them in *INSN. */ + +static void +find_bytes_big (unsigned char *insn_ch, unsigned long *insn) +{ + *insn = + ((unsigned long) insn_ch[0] << 24) + + ((unsigned long) insn_ch[1] << 16) + + ((unsigned long) insn_ch[2] << 8) + + ((unsigned long) insn_ch[3]); +#if DEBUG + printf ("find_bytes_big3: %lx\n", *insn); +#endif +} + +static void +find_bytes_little (unsigned char *insn_ch, unsigned long *insn) +{ + *insn = + ((unsigned long) insn_ch[3] << 24) + + ((unsigned long) insn_ch[2] << 16) + + ((unsigned long) insn_ch[1] << 8) + + ((unsigned long) insn_ch[0]); +} + +typedef void (*find_byte_func_type) (unsigned char *, unsigned long *); + +static unsigned long +or32_extract (char param_ch, char *enc_initial, unsigned long insn) +{ + char *enc; + unsigned long ret = 0; + int opc_pos = 0; + int param_pos = 0; + + for (enc = enc_initial; *enc != '\0'; enc++) + if (*enc == param_ch) + { + if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) + continue; + else + param_pos++; + } + +#if DEBUG + printf ("or32_extract: %c %x ", param_ch, param_pos); +#endif + opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + opc_pos -= 4; + + if ((param_ch == '0') || (param_ch == '1')) + { + unsigned long tmp = strtoul (enc, NULL, 16); +#if DEBUG + printf (" enc=%s, tmp=%lx ", enc, tmp); +#endif + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else if ((*enc == '0') || (*enc == '1')) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + enc++; + } + else if (*enc == param_ch) + { + opc_pos--; + param_pos--; +#if DEBUG + printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); +#endif + ret += ((insn >> opc_pos) & 0x1) << param_pos; + + if (!param_pos + && letter_signed (param_ch) + && ret >> (letter_range (param_ch) - 1)) + { +#if DEBUG + printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", + ret, opc_pos, param_pos); +#endif + ret |= 0xffffffff << letter_range(param_ch); +#if DEBUG + printf ("\n after conversion to signed: ret=%lx\n", ret); +#endif + } + enc++; + } + else if (ISALPHA (*enc)) + { + opc_pos--; + enc++; + } + else if (*enc == '-') + { + opc_pos--; + enc++; + } + else + enc++; + +#if DEBUG + printf ("ret=%lx\n", ret); +#endif + return ret; +} + +static int +or32_opcode_match (unsigned long insn, char *encoding) +{ + unsigned long ones, zeros; + +#if DEBUG + printf ("or32_opcode_match: %.8lx\n", insn); +#endif + ones = or32_extract ('1', encoding, insn); + zeros = or32_extract ('0', encoding, insn); + +#if DEBUG + printf ("ones: %lx \n", ones); + printf ("zeros: %lx \n", zeros); +#endif + if ((insn & ones) != ones) + { +#if DEBUG + printf ("ret1\n"); +#endif + return 0; + } + + if ((~insn & zeros) != zeros) + { +#if DEBUG + printf ("ret2\n"); +#endif + return 0; + } + +#if DEBUG + printf ("ret3\n"); +#endif + return 1; +} + +/* Print register to INFO->STREAM. Used only by print_insn. */ + +static void +or32_print_register (char param_ch, + char *encoding, + unsigned long insn, + struct disassemble_info *info) +{ + int regnum = or32_extract (param_ch, encoding, insn); + +#if DEBUG + printf ("or32_print_register: %c, %s, %lx\n", param_ch, encoding, insn); +#endif + if (param_ch == 'A') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (param_ch == 'B') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (param_ch == 'D') + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (regnum < 16) + (*info->fprintf_func) (info->stream, "r%d", regnum); + else if (regnum < 32) + (*info->fprintf_func) (info->stream, "r%d", regnum-16); + else + (*info->fprintf_func) (info->stream, "X%d", regnum); +} + +/* Print immediate to INFO->STREAM. Used only by print_insn. */ + +static void +or32_print_immediate (char param_ch, + char *encoding, + unsigned long insn, + struct disassemble_info *info) +{ + int imm = or32_extract(param_ch, encoding, insn); + + if (letter_signed(param_ch)) + (*info->fprintf_func) (info->stream, "0x%x", imm); +/* (*info->fprintf_func) (info->stream, "%d", imm); */ + else + (*info->fprintf_func) (info->stream, "0x%x", imm); +} + +/* Print one instruction from MEMADDR on INFO->STREAM. + Return the size of the instruction (always 4 on or32). */ + +static int +print_insn (bfd_vma memaddr, struct disassemble_info *info) +{ + /* The raw instruction. */ + unsigned char insn_ch[4]; + /* Address. Will be sign extened 27-bit. */ + unsigned long addr; + /* The four bytes of the instruction. */ + unsigned long insn; + find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data; + struct or32_opcode const * opcode; + + { + int status = + (*info->read_memory_func) (memaddr, (bfd_byte *) &insn_ch[0], 4, info); + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + (*find_byte_func) (&insn_ch[0], &insn); + + for (opcode = &or32_opcodes[0]; + opcode < &or32_opcodes[or32_num_opcodes]; + ++opcode) + { + if (or32_opcode_match (insn, opcode->encoding)) + { + char *s; + + (*info->fprintf_func) (info->stream, "%s ", opcode->name); + + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case '\0': + return 4; + + case 'r': + or32_print_register (*++s, opcode->encoding, insn, info); + break; + + case 'X': + addr = or32_extract ('X', opcode->encoding, insn) << 2; + + /* Calulate the correct address. XXX is this really correct ?? */ + addr = memaddr + EXTEND29 (addr); + + (*info->print_address_func) + (addr, info); + break; + + default: + if (strchr (opcode->encoding, *s)) + or32_print_immediate (*s, opcode->encoding, insn, info); + else + (*info->fprintf_func) (info->stream, "%c", *s); + } + } + + return 4; + } + } + + /* This used to be %8x for binutils. */ + (*info->fprintf_func) + (info->stream, ".word 0x%08lx", insn); + return 4; +} + +/* Disassemble a big-endian or32 instruction. */ + +int +print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info) +{ + info->private_data = find_bytes_big; + + return print_insn (memaddr, info); +} + +/* Disassemble a little-endian or32 instruction. */ + +int +print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info) +{ + info->private_data = find_bytes_little; + return print_insn (memaddr, info); +} diff --git a/external/gpl3/gdb/dist/opcodes/or32-opc.c b/external/gpl3/gdb/dist/opcodes/or32-opc.c new file mode 100644 index 000000000000..94a1ace82d60 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/or32-opc.c @@ -0,0 +1,1031 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ +#include +#include +#include +#include "safe-ctype.h" +#include "ansidecl.h" +#ifdef HAVE_CONFIG_H +# include "config.h" +#endif +#include "opcode/or32.h" + +const struct or32_letter or32_letters[] = +{ + { 'A', NUM_UNSIGNED }, + { 'B', NUM_UNSIGNED }, + { 'D', NUM_UNSIGNED }, + { 'I', NUM_SIGNED }, + { 'K', NUM_UNSIGNED }, + { 'L', NUM_UNSIGNED }, + { 'N', NUM_SIGNED }, + { '0', NUM_UNSIGNED }, + { '\0', 0 } /* Dummy entry. */ +}; + +/* Opcode encoding: + machine[31:30]: first two bits of opcode + 00 - neither of source operands is GPR + 01 - second source operand is GPR (rB) + 10 - first source operand is GPR (rA) + 11 - both source operands are GPRs (rA and rB) + machine[29:26]: next four bits of opcode + machine[25:00]: instruction operands (specific to individual instruction) + + Recommendation: irrelevant instruction bits should be set with a value of + bits in same positions of instruction preceding current instruction in the + code (when assembling). */ + +#define EFN &l_none + +#ifdef HAS_EXECUTION +#define EF(func) &(func) +#define EFI &l_invalid +#else /* HAS_EXECUTION */ +#define EF(func) EFN +#define EFI EFN +#endif /* HAS_EXECUTION */ + +const struct or32_opcode or32_opcodes[] = +{ + { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, + { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, + { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, + { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, + { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, + { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ + { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ + + { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, + { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ + { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, + + { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, + { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, + { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, + { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, + { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, + { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, + { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, + { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, + { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, + { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, + { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, + { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, + { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, + { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, + { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, + { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, + { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, + { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, + { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, + { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, + { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, + { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, + { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, + { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, + { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, + { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, + { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, + { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, + { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, + { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, + { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, + { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, + { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, + { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, + { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, + { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, + { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, + { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, + { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, + { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, + { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, + { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, + { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, + { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, + { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, + { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, + { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, + { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, + { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, + { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, + { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, + { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, + { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, + { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, + { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, + { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, + { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, + { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, + { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, + { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, + { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, + { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, + { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, + { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, + { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, + { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, + { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, + { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, + { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, + { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, + { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, + { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, + { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, + { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, + { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, + { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, + { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, + { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, + { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, + + { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 }, + { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 }, + { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + + { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, + { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, + { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, + { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, + { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, + { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, + { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, + + { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, + { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, + { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, + { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, + { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, + + { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 }, + { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 }, + { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, + { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, + { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, + { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, + { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, + { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, + { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, + + { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, + { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, + { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, + + { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, + { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ + { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ + + { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 }, + { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 }, + { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 }, + { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 }, + + { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 }, + { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 }, + { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, + { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 }, + { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, + { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, + { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, + + { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, + { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, + { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, + { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, + { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 }, + { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 }, + { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, + { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 }, + { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 }, + { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 }, + { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 }, + { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 }, + { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 }, + { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 }, + { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 }, + + { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, + { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, + { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, + + { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, + + /* This section should not be defined in or1ksim, since it contains duplicates, + which would cause machine builder to complain. */ +#ifdef HAS_CUST + { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, +#endif + + /* Dummy entry, not included in num_opcodes. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", "", "", EFI, 0 } +}; + +#undef EFI +#undef EFN +#undef EF + +/* Define dummy, if debug is not defined. */ + +#if !defined HAS_DEBUG +static void ATTRIBUTE_PRINTF_2 +debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...) +{ +} +#endif + +const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ + +int +insn_len (int i_index ATTRIBUTE_UNUSED) +{ + return 4; +} + +/* Is individual insn's operand signed or unsigned? */ + +int +letter_signed (char l) +{ + const struct or32_letter *pletter; + + for (pletter = or32_letters; pletter->letter != '\0'; pletter++) + if (pletter->letter == l) + return pletter->sign; + + printf ("letter_signed(%c): Unknown letter.\n", l); + return 0; +} + +/* Number of letters in the individual lettered operand. */ + +int +letter_range (char l) +{ + const struct or32_opcode *pinsn; + char *enc; + int range = 0; + + for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++) + { + if (strchr (pinsn->encoding,l)) + { + for (enc = pinsn->encoding; *enc != '\0'; enc ++) + if ((*enc == '0') && (*(enc + 1) == 'x')) + enc += 2; + else if (*enc == l) + range++; + return range; + } + } + + printf ("\nABORT: letter_range(%c): Never used letter.\n", l); + exit (1); +} + +/* MM: Returns index of given instruction name. */ + +int +insn_index (char *insn) +{ + unsigned int i; + int found = -1; + + for (i = 0; i < or32_num_opcodes; i++) + if (!strcmp (or32_opcodes[i].name, insn)) + { + found = i; + break; + } + return found; +} + +const char * +insn_name (int op_index) +{ + if (op_index >= 0 && op_index < (int) or32_num_opcodes) + return or32_opcodes[op_index].name; + else + return "???"; +} + +void +l_none (void) +{ +} + +/* Finite automata for instruction decoding building code. */ + +/* Find simbols in encoding. */ + +static unsigned long +insn_extract (char param_ch, char *enc_initial) +{ + char *enc; + unsigned long ret = 0; + unsigned opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + unsigned long tmp = strtol (enc+2, NULL, 16); + + opc_pos -= 4; + if (param_ch == '0' || param_ch == '1') + { + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else + { + if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc)) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + } + enc++; + } + return ret; +} + +#define MAX_AUTOMATA_SIZE 1200 +#define MAX_OP_TABLE_SIZE 1200 +#define LEAF_FLAG 0x80000000 +#define MAX_LEN 8 + +#ifndef MIN +#define MIN(x, y) ((x) < (y) ? (x) : (y)) +#endif + +unsigned long *automata; +int nuncovered; +int curpass = 0; + +/* MM: Struct that hold runtime build information about instructions. */ +struct temp_insn_struct +{ + unsigned long insn; + unsigned long insn_mask; + int in_pass; +} *ti; + +struct insn_op_struct *op_data, **op_start; + +/* Recursive utility function used to find best match and to build automata. */ + +static unsigned long * +cover_insn (unsigned long * cur, int pass, unsigned int mask) +{ + int best_first = 0, last_match = -1, ninstr = 0; + unsigned int best_len = 0; + unsigned int i; + unsigned long cur_mask = mask; + unsigned long *next; + + for (i = 0; i < or32_num_opcodes; i++) + if (ti[i].in_pass == pass) + { + cur_mask &= ti[i].insn_mask; + ninstr++; + last_match = i; + } + + debug (8, "%08X %08lX\n", mask, cur_mask); + + if (ninstr == 0) + return 0; + + if (ninstr == 1) + { + /* Leaf holds instruction index. */ + debug (8, "%li>I%i %s\n", + (long)(cur - automata), last_match, or32_opcodes[last_match].name); + + *cur = LEAF_FLAG | last_match; + cur++; + nuncovered--; + } + else + { + /* Find longest match. */ + for (i = 0; i < 32; i++) + { + unsigned int len; + + for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++) + { + unsigned long m = (1UL << ((unsigned long) len)) - 1; + + debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", + len,m, cur_mask, i, (cur_mask >> (unsigned)i), + (cur_mask >> (unsigned) i) & m); + + if ((m & (cur_mask >> (unsigned) i)) == m) + { + best_len = len; + best_first = i; + debug (9, "!"); + } + else + break; + } + } + + debug (9, "\n"); + + if (!best_len) + { + fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask); + + for (i = 0; i < or32_num_opcodes; i++) + if (ti[i].in_pass == pass) + fprintf (stderr, "%s ", or32_opcodes[i].name); + + fprintf (stderr, "\n"); + exit (1); + } + + debug (8, "%li> #### %i << %i (%i) ####\n", + (long)(cur - automata), best_len, best_first, ninstr); + + *cur = best_first; + cur++; + *cur = (1 << best_len) - 1; + cur++; + next = cur; + + /* Allocate space for pointers. */ + cur += 1 << best_len; + cur_mask = (1 << (unsigned long) best_len) - 1; + + for (i = 0; i < ((unsigned) 1 << best_len); i++) + { + unsigned int j; + unsigned long *c; + + curpass++; + for (j = 0; j < or32_num_opcodes; j++) + if (ti[j].in_pass == pass + && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i + && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask) + ti[j].in_pass = curpass; + + debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first); + c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first))); + if (c) + { + debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i, + (unsigned long)(cur - automata)); + *next = cur - automata; + cur = c; + } + else + { + debug (8, "%li> N/A\n", (long)(next - automata)); + *next = 0; + } + next++; + } + } + return cur; +} + +/* Returns number of nonzero bits. */ + +static int +num_ones (unsigned long value) +{ + int c = 0; + + while (value) + { + if (value & 1) + c++; + value >>= 1; + } + return c; +} + +/* Utility function, which converts parameters from or32_opcode + format to more binary form. Parameters are stored in ti struct. */ + +static struct insn_op_struct * +parse_params (const struct or32_opcode * opcode, + struct insn_op_struct * cur) +{ + char *args = opcode->args; + int i, type; + + i = 0; + type = 0; + /* In case we don't have any parameters, we add dummy read from r0. */ + + if (!(*args)) + { + cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST; + cur->data = 0; + debug (9, "#%08lX %08lX\n", cur->type, cur->data); + cur++; + return cur; + } + + while (*args != '\0') + { + if (*args == 'r') + { + args++; + type |= OPTYPE_REG; + } + else if (ISALPHA (*args)) + { + unsigned long arg; + + arg = insn_extract (*args, opcode->encoding); + debug (9, "%s : %08lX ------\n", opcode->name, arg); + if (letter_signed (*args)) + { + type |= OPTYPE_SIG; + type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT; + } + + /* Split argument to sequences of consecutive ones. */ + while (arg) + { + int shr = 0; + unsigned long tmp = arg, mask = 0; + + while ((tmp & 1) == 0) + { + shr++; + tmp >>= 1; + } + while (tmp & 1) + { + mask++; + tmp >>= 1; + } + cur->type = type | shr; + cur->data = mask; + arg &= ~(((1 << mask) - 1) << shr); + debug (6, "|%08lX %08lX\n", cur->type, cur->data); + cur++; + } + args++; + } + else if (*args == '(') + { + /* Next param is displacement. + Later we will treat them as one operand. */ + cur--; + cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP; + debug (9, ">%08lX %08lX\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == OPERAND_DELIM) + { + cur--; + cur->type = type | cur->type | OPTYPE_OP; + debug (9, ">%08lX %08lX\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == '0') + { + cur->type = type; + cur->data = 0; + debug (9, ">%08lX %08lX\n", cur->type, cur->data); + cur++; + type = 0; + i++; + args++; + } + else if (*args == ')') + args++; + else + { + fprintf (stderr, "%s : parse error in args.\n", opcode->name); + exit (1); + } + } + + cur--; + cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST; + debug (9, "#%08lX %08lX\n", cur->type, cur->data); + cur++; + + return cur; +} + +/* Constructs new automata based on or32_opcodes array. */ + +void +build_automata (void) +{ + unsigned int i; + unsigned long *end; + struct insn_op_struct *cur; + + automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long)); + ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes); + + nuncovered = or32_num_opcodes; + printf ("Building automata... "); + /* Build temporary information about instructions. */ + for (i = 0; i < or32_num_opcodes; i++) + { + unsigned long ones, zeros; + char *encoding = or32_opcodes[i].encoding; + + ones = insn_extract('1', encoding); + zeros = insn_extract('0', encoding); + + ti[i].insn_mask = ones | zeros; + ti[i].insn = ones; + ti[i].in_pass = curpass = 0; + + /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name, + or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/ + } + + /* Until all are covered search for best criteria to separate them. */ + end = cover_insn (automata, curpass, 0xFFFFFFFF); + + if (end - automata > MAX_AUTOMATA_SIZE) + { + fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE."); + exit (1); + } + + printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes); + printf ("Parsing operands data... "); + + op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct)); + op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *)); + cur = op_data; + + for (i = 0; i < or32_num_opcodes; i++) + { + op_start[i] = cur; + cur = parse_params (&or32_opcodes[i], cur); + + if (cur - op_data > MAX_OP_TABLE_SIZE) + { + fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n"); + exit (1); + } + } + printf ("done.\n"); +} + +void +destruct_automata (void) +{ + free (ti); + free (automata); + free (op_data); + free (op_start); +} + +/* Decodes instruction and returns instruction index. */ + +int +insn_decode (unsigned int insn) +{ + unsigned long *a = automata; + int i; + + while (!(*a & LEAF_FLAG)) + { + unsigned int first = *a; + + debug (9, "%li ", (long)(a - automata)); + + a++; + i = (insn >> first) & *a; + a++; + if (!*(a + i)) + { + /* Invalid instruction found? */ + debug (9, "XXX\n"); + return -1; + } + a = automata + *(a + i); + } + + i = *a & ~LEAF_FLAG; + + debug (9, "%i\n", i); + + /* Final check - do we have direct match? + (based on or32_opcodes this should be the only possibility, + but in case of invalid/missing instruction we must perform a check) */ + if ((ti[i].insn_mask & insn) == ti[i].insn) + return i; + else + return -1; +} + +static char disassembled_str[50]; +char *disassembled = &disassembled_str[0]; + +/* Automagically does zero- or sign- extension and also finds correct + sign bit position if sign extension is correct extension. Which extension + is proper is figured out from letter description. */ + +static unsigned long +extend_imm (unsigned long imm, char l) +{ + unsigned long mask; + int letter_bits; + + /* First truncate all bits above valid range for this letter + in case it is zero extend. */ + letter_bits = letter_range (l); + mask = (1 << letter_bits) - 1; + imm &= mask; + + /* Do sign extend if this is the right one. */ + if (letter_signed(l) && (imm >> (letter_bits - 1))) + imm |= (~mask); + + return imm; +} + +static unsigned long +or32_extract (char param_ch, char *enc_initial, unsigned long insn) +{ + char *enc; + unsigned long ret = 0; + int opc_pos = 0; + int param_pos = 0; + + for (enc = enc_initial; *enc != '\0'; enc++) + if (*enc == param_ch) + { + if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) + continue; + else + param_pos++; + } + +#if DEBUG + printf ("or32_extract: %x ", param_pos); +#endif + opc_pos = 32; + + for (enc = enc_initial; *enc != '\0'; ) + if ((*enc == '0') && (*(enc + 1) == 'x')) + { + opc_pos -= 4; + if ((param_ch == '0') || (param_ch == '1')) + { + unsigned long tmp = strtol (enc, NULL, 16); +#if DEBUG + printf (" enc=%s, tmp=%lx ", enc, tmp); +#endif + if (param_ch == '0') + tmp = 15 - tmp; + ret |= tmp << opc_pos; + } + enc += 3; + } + else if ((*enc == '0') || (*enc == '1')) + { + opc_pos--; + if (param_ch == *enc) + ret |= 1 << opc_pos; + enc++; + } + else if (*enc == param_ch) + { + opc_pos--; + param_pos--; +#if DEBUG + printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos); +#endif + if (ISLOWER (param_ch)) + ret -= ((insn >> opc_pos) & 0x1) << param_pos; + else + ret += ((insn >> opc_pos) & 0x1) << param_pos; + enc++; + } + else if (ISALPHA (*enc)) + { + opc_pos--; + enc++; + } + else if (*enc == '-') + { + opc_pos--; + enc++; + } + else + enc++; + +#if DEBUG + printf ("ret=%lx\n", ret); +#endif + return ret; +} + +/* Print register. Used only by print_insn. */ + +static void +or32_print_register (char param_ch, char *encoding, unsigned long insn) +{ + int regnum = or32_extract(param_ch, encoding, insn); + char s_regnum[20]; + + sprintf (s_regnum, "r%d", regnum); + strcat (disassembled, s_regnum); +} + +/* Print immediate. Used only by print_insn. */ + +static void +or32_print_immediate (char param_ch, char *encoding, unsigned long insn) +{ + int imm = or32_extract (param_ch, encoding, insn); + char s_imm[20]; + + imm = extend_imm (imm, param_ch); + + if (letter_signed (param_ch)) + { + if (imm < 0) + sprintf (s_imm, "%d", imm); + else + sprintf (s_imm, "0x%x", imm); + } + else + sprintf (s_imm, "%#x", imm); + strcat (disassembled, s_imm); +} + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ + +int +disassemble_insn (unsigned long insn) +{ + int op_index; + op_index = insn_decode (insn); + + if (op_index >= 0) + { + struct or32_opcode const *opcode = &or32_opcodes[op_index]; + char *s; + + sprintf (disassembled, "%s ", opcode->name); + for (s = opcode->args; *s != '\0'; ++s) + { + switch (*s) + { + case '\0': + return 4; + + case 'r': + or32_print_register (*++s, opcode->encoding, insn); + break; + + default: + if (strchr (opcode->encoding, *s)) + or32_print_immediate (*s, opcode->encoding, insn); + else + { + char s_encoding[2] = { *s, '\0' }; + + strcat (disassembled, s_encoding); + } + + } + } + } + else + { + char s_insn[20]; + + /* This used to be %8x for binutils. */ + sprintf (s_insn, ".word 0x%08lx", insn); + strcat (disassembled, s_insn); + } + + return insn_len (insn); +} diff --git a/external/gpl3/gdb/dist/opcodes/pdp11-dis.c b/external/gpl3/gdb/dist/opcodes/pdp11-dis.c new file mode 100644 index 000000000000..a149374220e7 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/pdp11-dis.c @@ -0,0 +1,373 @@ +/* Print DEC PDP-11 instructions. + Copyright 2001, 2002, 2004, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/pdp11.h" + +#define AFTER_INSTRUCTION "\t" +#define OPERAND_SEPARATOR ", " + +#define JUMP 0x1000 /* Flag that this operand is used in a jump. */ + +#define FPRINTF (*info->fprintf_func) +#define F info->stream + +/* Sign-extend a 16-bit number in an int. */ +#define SIGN_BITS (8 * sizeof (int) - 16) +#define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS) + +static int +read_word (bfd_vma memaddr, int *word, disassemble_info *info) +{ + int status; + bfd_byte x[2]; + + status = (*info->read_memory_func) (memaddr, x, 2, info); + if (status != 0) + return -1; + + *word = x[1] << 8 | x[0]; + return 0; +} + +static void +print_signed_octal (int n, disassemble_info *info) +{ + if (n < 0) + FPRINTF (F, "-%o", -n); + else + FPRINTF (F, "%o", n); +} + +static void +print_reg (int reg, disassemble_info *info) +{ + /* Mask off the addressing mode, if any. */ + reg &= 7; + + switch (reg) + { + case 0: case 1: case 2: case 3: case 4: case 5: + FPRINTF (F, "r%d", reg); break; + case 6: FPRINTF (F, "sp"); break; + case 7: FPRINTF (F, "pc"); break; + default: ; /* error */ + } +} + +static void +print_freg (int freg, disassemble_info *info) +{ + FPRINTF (F, "fr%d", freg); +} + +static int +print_operand (bfd_vma *memaddr, int code, disassemble_info *info) +{ + int mode = (code >> 3) & 7; + int reg = code & 7; + int disp; + + switch (mode) + { + case 0: + print_reg (reg, info); + break; + case 1: + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 2: + if (reg == 7) + { + int data; + + if (read_word (*memaddr, &data, info) < 0) + return -1; + FPRINTF (F, "$"); + print_signed_octal (sign_extend (data), info); + *memaddr += 2; + } + else + { + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")+"); + } + break; + case 3: + if (reg == 7) + { + int address; + + if (read_word (*memaddr, &address, info) < 0) + return -1; + FPRINTF (F, "*$%o", address); + *memaddr += 2; + } + else + { + FPRINTF (F, "*("); + print_reg (reg, info); + FPRINTF (F, ")+"); + } + break; + case 4: + FPRINTF (F, "-("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 5: + FPRINTF (F, "*-("); + print_reg (reg, info); + FPRINTF (F, ")"); + break; + case 6: + case 7: + if (read_word (*memaddr, &disp, info) < 0) + return -1; + *memaddr += 2; + if (reg == 7) + { + bfd_vma address = *memaddr + sign_extend (disp); + + if (mode == 7) + FPRINTF (F, "*"); + if (!(code & JUMP)) + FPRINTF (F, "$"); + (*info->print_address_func) (address, info); + } + else + { + if (mode == 7) + FPRINTF (F, "*"); + print_signed_octal (sign_extend (disp), info); + FPRINTF (F, "("); + print_reg (reg, info); + FPRINTF (F, ")"); + } + break; + } + + return 0; +} + +static int +print_foperand (bfd_vma *memaddr, int code, disassemble_info *info) +{ + int mode = (code >> 3) & 7; + int reg = code & 7; + + if (mode == 0) + print_freg (reg, info); + else + return print_operand (memaddr, code, info); + + return 0; +} + +/* Print the PDP-11 instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_pdp11 (bfd_vma memaddr, disassemble_info *info) +{ + bfd_vma start_memaddr = memaddr; + int opcode; + int src, dst; + int i; + + info->bytes_per_line = 6; + info->bytes_per_chunk = 2; + info->display_endian = BFD_ENDIAN_LITTLE; + + if (read_word (memaddr, &opcode, info) != 0) + return -1; + memaddr += 2; + + src = (opcode >> 6) & 0x3f; + dst = opcode & 0x3f; + + for (i = 0; i < pdp11_num_opcodes; i++) + { +#define OP pdp11_opcodes[i] + if ((opcode & OP.mask) == OP.opcode) + switch (OP.type) + { + case PDP11_OPCODE_NO_OPS: + FPRINTF (F, OP.name); + goto done; + case PDP11_OPCODE_REG: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (dst, info); + goto done; + case PDP11_OPCODE_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (strcmp (OP.name, "jmp") == 0) + dst |= JUMP; + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_FOP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (strcmp (OP.name, "jmp") == 0) + dst |= JUMP; + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_REG_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (src, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (strcmp (OP.name, "jsr") == 0) + dst |= JUMP; + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_REG_OP_REV: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_reg (src, info); + goto done; + case PDP11_OPCODE_AC_FOP: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_freg (ac, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + goto done; + } + case PDP11_OPCODE_FOP_AC: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_foperand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_freg (ac, info); + goto done; + } + case PDP11_OPCODE_AC_OP: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_freg (ac, info); + FPRINTF (F, OPERAND_SEPARATOR); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + } + case PDP11_OPCODE_OP_AC: + { + int ac = (opcode & 0xe0) >> 6; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + print_freg (ac, info); + goto done; + } + case PDP11_OPCODE_OP_OP: + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + if (print_operand (&memaddr, src, info) < 0) + return -1; + FPRINTF (F, OPERAND_SEPARATOR); + if (print_operand (&memaddr, dst, info) < 0) + return -1; + goto done; + case PDP11_OPCODE_DISPL: + { + int displ = (opcode & 0xff) << 8; + bfd_vma address = memaddr + (sign_extend (displ) >> 7); + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + (*info->print_address_func) (address, info); + goto done; + } + case PDP11_OPCODE_REG_DISPL: + { + int displ = (opcode & 0x3f) << 10; + bfd_vma address = memaddr - (displ >> 9); + + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + print_reg (src, info); + FPRINTF (F, OPERAND_SEPARATOR); + (*info->print_address_func) (address, info); + goto done; + } + case PDP11_OPCODE_IMM8: + { + int code = opcode & 0xff; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_IMM6: + { + int code = opcode & 0x3f; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_IMM3: + { + int code = opcode & 7; + FPRINTF (F, OP.name); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", code); + goto done; + } + case PDP11_OPCODE_ILLEGAL: + { + FPRINTF (F, ".word"); + FPRINTF (F, AFTER_INSTRUCTION); + FPRINTF (F, "%o", opcode); + goto done; + } + default: + /* TODO: is this a proper way of signalling an error? */ + FPRINTF (F, ""); + return -1; + } +#undef OP + } + done: + + return memaddr - start_memaddr; +} diff --git a/external/gpl3/gdb/dist/opcodes/pdp11-opc.c b/external/gpl3/gdb/dist/opcodes/pdp11-opc.c new file mode 100644 index 000000000000..fa7932fddaac --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/pdp11-opc.c @@ -0,0 +1,275 @@ +/* Opcode table for PDP-11. + Copyright 2001, 2002, 2005, 2006, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "opcode/pdp11.h" + +const struct pdp11_opcode pdp11_opcodes[] = +{ + /* name, pattern, mask, opcode type, insn type, alias */ + { "halt", 0x0000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "wait", 0x0001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "rti", 0x0002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "bpt", 0x0003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "iot", 0x0004, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "reset", 0x0005, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "rtt", 0x0006, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_LEIS }, + { "mfpt", 0x0007, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_MFPT }, + { "jmp", 0x0040, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rts", 0x0080, 0xfff8, PDP11_OPCODE_REG, PDP11_BASIC }, + { "", 0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, + { "", 0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, + { "spl", 0x0098, 0xfff8, PDP11_OPCODE_IMM3, PDP11_SPL }, + { "nop", 0x00a0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clc", 0x00a1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clv", 0x00a2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_3", 0x00a3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "clz", 0x00a4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_5", 0x00a5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_6", 0x00a6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_7", 0x00a7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cln", 0x00a8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_9", 0x00a9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_a", 0x00aa, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_b", 0x00ab, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_c", 0x00ac, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_d", 0x00ad, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "cl_e", 0x00ae, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "ccc", 0x00af, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_0", 0x00b0, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sec", 0x00b1, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sev", 0x00b2, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_3", 0x00b3, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sez", 0x00b4, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_5", 0x00b5, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_6", 0x00b6, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_7", 0x00b7, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "sen", 0x00b8, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_9", 0x00b9, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_a", 0x00ba, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_b", 0x00bb, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_c", 0x00bc, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_d", 0x00bd, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "se_e", 0x00be, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "scc", 0x00bf, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_BASIC }, + { "swab", 0x00c0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "br", 0x0100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bne", 0x0200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "beq", 0x0300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bge", 0x0400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blt", 0x0500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bgt", 0x0600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "ble", 0x0700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "jsr", 0x0800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_BASIC }, + { "clr", 0x0a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "com", 0x0a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "inc", 0x0a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "dec", 0x0ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "neg", 0x0b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "adc", 0x0b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sbc", 0x0b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "tst", 0x0bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "ror", 0x0c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rol", 0x0c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asr", 0x0c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asl", 0x0cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mark", 0x0d00, 0xffc0, PDP11_OPCODE_IMM6, PDP11_LEIS }, + { "mfpi", 0x0d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtpi", 0x0d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sxt", 0x0dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_LEIS }, + { "csm", 0x0e00, 0xffc0, PDP11_OPCODE_OP, PDP11_CSM }, + { "tstset", 0x0e40, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC }, + { "wrtlck", 0x0e80, 0xffc0, PDP11_OPCODE_OP, PDP11_MPROC }, +/*{ "", 0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ + { "mov", 0x1000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cmp", 0x2000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bit", 0x3000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bic", 0x4000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bis", 0x5000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "add", 0x6000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "mul", 0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "div", 0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "ash", 0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "ashc", 0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, + { "xor", 0x7800, 0xfe00, PDP11_OPCODE_REG_OP, PDP11_LEIS }, + { "fadd", 0x7a00, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fsub", 0x7a08, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fmul", 0x7a10, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, + { "fdiv", 0x7a18, 0xfff8, PDP11_OPCODE_REG, PDP11_FIS }, +/*{ "", 0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ +/*{ "", 0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL, PDP11_NONE },*/ + { "l2dr", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l2d*/ + { "movc", 0x7c18, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movrc", 0x7c19, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movtc", 0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "locc", 0x7c20, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "skpc", 0x7c21, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "scanc", 0x7c22, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "spanc", 0x7c23, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpc", 0x7c24, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "matc", 0x7c25, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addn", 0x7c28, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subn", 0x7c29, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpn", 0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnl", 0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpn", 0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnp", 0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashn", 0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtln", 0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "l3dr", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS },/*l3d*/ + { "addp", 0x7c38, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subp", 0x7c39, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpp", 0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpl", 0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "mulp", 0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "divp", 0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashp", 0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlp", 0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movci", 0x7c58, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movrci", 0x7c59, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "movtci", 0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "locci", 0x7c60, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "skpci", 0x7c61, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "scanci", 0x7c62, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "spanci", 0x7c63, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpci", 0x7c64, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "matci", 0x7c65, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addni", 0x7c68, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subni", 0x7c69, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmpni", 0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnli", 0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpni", 0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtnpi", 0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashni", 0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlni", 0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "addpi", 0x7c78, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "subpi", 0x7c79, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cmppi", 0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtpli", 0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "mulpi", 0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "divpi", 0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "ashpi", 0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "cvtlpi", 0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_CIS }, + { "med", 0x7d80, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE }, + { "xfc", 0x7dc0, 0xffc0, PDP11_OPCODE_IMM6, PDP11_UCODE }, + { "sob", 0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL, PDP11_LEIS }, + { "bpl", 0x8000, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bmi", 0x8100, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bhi", 0x8200, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blos", 0x8300, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bvc", 0x8400, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bvs", 0x8500, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "bcc", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*bhis*/ + { "bcs", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC },/*blo*/ + { "emt", 0x8800, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC }, + { "sys", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC },/*trap*/ + { "clrb", 0x8a00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "comb", 0x8a40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "incb", 0x8a80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "decb", 0x8ac0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "negb", 0x8b00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "adcb", 0x8b40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "sbcb", 0x8b80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "tstb", 0x8bc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rorb", 0x8c00, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "rolb", 0x8c40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "asrb", 0x8c80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "aslb", 0x8cc0, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtps", 0x8d00, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS }, + { "mfpd", 0x8d40, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mtpd", 0x8d80, 0xffc0, PDP11_OPCODE_OP, PDP11_BASIC }, + { "mfps", 0x8dc0, 0xffc0, PDP11_OPCODE_OP, PDP11_MXPS }, + { "movb", 0x9000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cmpb", 0xa000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bitb", 0xb000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bicb", 0xc000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "bisb", 0xd000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "sub", 0xe000, 0xf000, PDP11_OPCODE_OP_OP, PDP11_BASIC }, + { "cfcc", 0xf000, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "setf", 0xf001, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "seti", 0xf002, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "ldub", 0xf003, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_UCODE }, + /* fpp trap 0xf004..0xf008 */ + { "setd", 0xf009, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + { "setl", 0xf00a, 0xffff, PDP11_OPCODE_NO_OPS, PDP11_FPP }, + /* fpp trap 0xf00b..0xf03f */ + { "ldfps", 0xf040, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "stfps", 0xf080, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "stst", 0xf0c0, 0xffc0, PDP11_OPCODE_OP, PDP11_FPP }, + { "clrf", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "tstf", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "absf", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "negf", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "mulf", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "modf", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "addf", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "ldf", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/ + { "subf", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "cmpf", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stf", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/ + { "divf", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stexp", 0xfa00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcfi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcff", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "ldexp", 0xfd00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcif", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcff", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ +/* This entry MUST be last; it is a "catch-all" entry that will match when no + * other opcode entry matches during disassembly. + */ + { "", 0x0000, 0x0000, PDP11_OPCODE_ILLEGAL, PDP11_NONE }, +}; + +const struct pdp11_opcode pdp11_aliases[] = +{ + /* name, pattern, mask, opcode type, insn type */ + { "l2d", 0x7c10, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS }, + { "l3d", 0x7c30, 0xfff8, PDP11_OPCODE_REG, PDP11_CIS }, + { "bhis", 0x8600, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "blo", 0x8700, 0xff00, PDP11_OPCODE_DISPL, PDP11_BASIC }, + { "trap", 0x8900, 0xff00, PDP11_OPCODE_IMM8, PDP11_BASIC }, + /* fpp xxxd alternate names to xxxf opcodes */ + { "clrd", 0xf100, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "tstd", 0xf140, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "absd", 0xf180, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "negd", 0xf1c0, 0xffc0, PDP11_OPCODE_FOP, PDP11_FPP }, + { "muld", 0xf200, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "modd", 0xf300, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "addd", 0xf400, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "ldd", 0xf500, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/*movif*/ + { "subd", 0xf600, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "cmpd", 0xf700, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "std", 0xf800, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/*movfi*/ + { "divd", 0xf900, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP }, + { "stcfl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcdi", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcdl", 0xfb00, 0xff00, PDP11_OPCODE_AC_OP, PDP11_FPP }, + { "stcfd", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "stcdf", 0xfc00, 0xff00, PDP11_OPCODE_AC_FOP, PDP11_FPP },/* ? */ + { "ldcid", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldclf", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcld", 0xfe00, 0xff00, PDP11_OPCODE_OP_AC, PDP11_FPP }, + { "ldcfd", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ + { "ldcdf", 0xff00, 0xff00, PDP11_OPCODE_FOP_AC, PDP11_FPP },/* ? */ +}; + +const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0]; +const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0]; diff --git a/external/gpl3/gdb/dist/opcodes/pj-dis.c b/external/gpl3/gdb/dist/opcodes/pj-dis.c new file mode 100644 index 000000000000..477f406ae2b4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/pj-dis.c @@ -0,0 +1,177 @@ +/* pj-dis.c -- Disassemble picoJava instructions. + Copyright 1999, 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. + Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/pj.h" +#include "dis-asm.h" + +extern const pj_opc_info_t pj_opc_info[512]; + +static int +get_int (bfd_vma memaddr, int *iptr, struct disassemble_info *info) +{ + unsigned char ival[4]; + int status = info->read_memory_func (memaddr, ival, 4, info); + + *iptr = (ival[0] << 24) + | (ival[1] << 16) + | (ival[2] << 8) + | (ival[3] << 0); + + return status; +} + +int +print_insn_pj (bfd_vma addr, struct disassemble_info *info) +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned char opcode; + int status; + + if ((status = info->read_memory_func (addr, &opcode, 1, info))) + goto fail; + + if (opcode == 0xff) + { + unsigned char byte_2; + + if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info))) + goto fail; + fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].u.name); + return 2; + } + else + { + char *sep = "\t"; + int insn_start = addr; + const pj_opc_info_t *op = &pj_opc_info[opcode]; + int a; + + addr++; + fprintf_fn (stream, "%s", op->u.name); + + /* The tableswitch instruction is followed by the default + address, low value, high value and the destinations. */ + + if (strcmp (op->u.name, "tableswitch") == 0) + { + int lowval; + int highval; + int val; + + addr = (addr + 3) & ~3; + if ((status = get_int (addr, &val, info))) + goto fail; + + fprintf_fn (stream, " default: "); + (*info->print_address_func) (val + insn_start, info); + addr += 4; + + if ((status = get_int (addr, &lowval, info))) + goto fail; + addr += 4; + + if ((status = get_int (addr, &highval, info))) + goto fail; + addr += 4; + + while (lowval <= highval) + { + if ((status = get_int (addr, &val, info))) + goto fail; + fprintf_fn (stream, " %d:[", lowval); + (*info->print_address_func) (val + insn_start, info); + fprintf_fn (stream, " ]"); + addr += 4; + lowval++; + } + return addr - insn_start; + } + + /* The lookupswitch instruction is followed by the default + address, element count and pairs of values and + addresses. */ + if (strcmp (op->u.name, "lookupswitch") == 0) + { + int count; + int val; + + addr = (addr + 3) & ~3; + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + + fprintf_fn (stream, " default: "); + (*info->print_address_func) (val + insn_start, info); + + if ((status = get_int (addr, &count, info))) + goto fail; + addr += 4; + + while (count--) + { + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + fprintf_fn (stream, " %d:[", val); + + if ((status = get_int (addr, &val, info))) + goto fail; + addr += 4; + + (*info->print_address_func) (val + insn_start, info); + fprintf_fn (stream, " ]"); + } + return addr - insn_start; + } + + for (a = 0; op->arg[a]; a++) + { + unsigned char data[4]; + int val = 0; + int i; + int size = ASIZE (op->arg[a]); + + if ((status = info->read_memory_func (addr, data, size, info))) + goto fail; + + val = (UNS (op->arg[0]) || ((data[0] & 0x80) == 0)) ? 0 : -1; + + for (i = 0; i < size; i++) + val = (val << 8) | (data[i] & 0xff); + + if (PCREL (op->arg[a])) + (*info->print_address_func) (val + insn_start, info); + else + fprintf_fn (stream, "%s%d", sep, val); + + sep = ","; + addr += size; + } + return op->len; + } + + fail: + info->memory_error_func (status, addr, info); + return -1; +} diff --git a/external/gpl3/gdb/dist/opcodes/pj-opc.c b/external/gpl3/gdb/dist/opcodes/pj-opc.c new file mode 100644 index 000000000000..60a8b96448e9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/pj-opc.c @@ -0,0 +1,539 @@ +/* pj-opc.c -- Definitions for picoJava opcodes. + Copyright 1999, 2000, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "opcode/pj.h" + +const pj_opc_info_t pj_opc_info[512] = +{ +{ 0x00, -1, 1, {O_N, O_N}, {"nop"}}, +{ 0x01, -1, 1, {O_N, O_N}, {"aconst_null"}}, +{ 0x02, -1, 1, {O_N, O_N}, {"iconst_m1"}}, +{ 0x03, -1, 1, {O_N, O_N}, {"iconst_0"}}, +{ 0x04, -1, 1, {O_N, O_N}, {"iconst_1"}}, +{ 0x05, -1, 1, {O_N, O_N}, {"iconst_2"}}, +{ 0x06, -1, 1, {O_N, O_N}, {"iconst_3"}}, +{ 0x07, -1, 1, {O_N, O_N}, {"iconst_4"}}, +{ 0x08, -1, 1, {O_N, O_N}, {"iconst_5"}}, +{ 0x09, -1, 1, {O_N, O_N}, {"lconst_0"}}, +{ 0x0a, -1, 1, {O_N, O_N}, {"lconst_1"}}, +{ 0x0b, -1, 1, {O_N, O_N}, {"fconst_0"}}, +{ 0x0c, -1, 1, {O_N, O_N}, {"fconst_1"}}, +{ 0x0d, -1, 1, {O_N, O_N}, {"fconst_2"}}, +{ 0x0e, -1, 1, {O_N, O_N}, {"dconst_0"}}, +{ 0x0f, -1, 1, {O_N, O_N}, {"dconst_1"}}, +{ 0x10, -1, 2, {O_8, O_N}, {"bipush"}}, +{ 0x11, -1, 3, {O_16, O_N}, {"sipush"}}, +{ 0x12, -1, 2, {O_N, O_N}, {"ldc"}}, +{ 0x13, -1, 3, {O_N, O_N}, {"ldc_w"}}, +{ 0x14, -1, 3, {O_N, O_N}, {"ldc2_w"}}, +{ 0x15, -1, 2, {O_U8, O_N}, {"iload"}}, +{ 0x16, -1, 2, {O_U8, O_N}, {"lload"}}, +{ 0x17, -1, 2, {O_U8, O_N}, {"fload"}}, +{ 0x18, -1, 2, {O_U8, O_N}, {"dload"}}, +{ 0x19, -1, 2, {O_U8, O_N}, {"aload"}}, +{ 0x1a, -1, 1, {O_N, O_N}, {"iload_0"}}, +{ 0x1b, -1, 1, {O_N, O_N}, {"iload_1"}}, +{ 0x1c, -1, 1, {O_N, O_N}, {"iload_2"}}, +{ 0x1d, -1, 1, {O_N, O_N}, {"iload_3"}}, +{ 0x1e, -1, 1, {O_N, O_N}, {"lload_0"}}, +{ 0x1f, -1, 1, {O_N, O_N}, {"lload_1"}}, +{ 0x20, -1, 1, {O_N, O_N}, {"lload_2"}}, +{ 0x21, -1, 1, {O_N, O_N}, {"lload_3"}}, +{ 0x22, -1, 1, {O_N, O_N}, {"fload_0"}}, +{ 0x23, -1, 1, {O_N, O_N}, {"fload_1"}}, +{ 0x24, -1, 1, {O_N, O_N}, {"fload_2"}}, +{ 0x25, -1, 1, {O_N, O_N}, {"fload_3"}}, +{ 0x26, -1, 1, {O_N, O_N}, {"dload_0"}}, +{ 0x27, -1, 1, {O_N, O_N}, {"dload_1"}}, +{ 0x28, -1, 1, {O_N, O_N}, {"dload_2"}}, +{ 0x29, -1, 1, {O_N, O_N}, {"dload_3"}}, +{ 0x2a, -1, 1, {O_N, O_N}, {"aload_0"}}, +{ 0x2b, -1, 1, {O_N, O_N}, {"aload_1"}}, +{ 0x2c, -1, 1, {O_N, O_N}, {"aload_2"}}, +{ 0x2d, -1, 1, {O_N, O_N}, {"aload_3"}}, +{ 0x2e, -1, 1, {O_N, O_N}, {"iaload"}}, +{ 0x2f, -1, 1, {O_N, O_N}, {"laload"}}, +{ 0x30, -1, 1, {O_N, O_N}, {"faload"}}, +{ 0x31, -1, 1, {O_N, O_N}, {"daload"}}, +{ 0x32, -1, 1, {O_N, O_N}, {"aaload"}}, +{ 0x33, -1, 1, {O_N, O_N}, {"baload"}}, +{ 0x34, -1, 1, {O_N, O_N}, {"caload"}}, +{ 0x35, -1, 1, {O_N, O_N}, {"saload"}}, +{ 0x36, -1, 2, {O_U8, O_N}, {"istore"}}, +{ 0x37, -1, 2, {O_U8, O_N}, {"lstore"}}, +{ 0x38, -1, 2, {O_U8, O_N}, {"fstore"}}, +{ 0x39, -1, 2, {O_U8, O_N}, {"dstore"}}, +{ 0x3a, -1, 2, {O_U8, O_N}, {"astore"}}, +{ 0x3b, -1, 1, {O_N, O_N}, {"istore_0"}}, +{ 0x3c, -1, 1, {O_N, O_N}, {"istore_1"}}, +{ 0x3d, -1, 1, {O_N, O_N}, {"istore_2"}}, +{ 0x3e, -1, 1, {O_N, O_N}, {"istore_3"}}, +{ 0x3f, -1, 1, {O_N, O_N}, {"lstore_0"}}, +{ 0x40, -1, 1, {O_N, O_N}, {"lstore_1"}}, +{ 0x41, -1, 1, {O_N, O_N}, {"lstore_2"}}, +{ 0x42, -1, 1, {O_N, O_N}, {"lstore_3"}}, +{ 0x43, -1, 1, {O_N, O_N}, {"fstore_0"}}, +{ 0x44, -1, 1, {O_N, O_N}, {"fstore_1"}}, +{ 0x45, -1, 1, {O_N, O_N}, {"fstore_2"}}, +{ 0x46, -1, 1, {O_N, O_N}, {"fstore_3"}}, +{ 0x47, -1, 1, {O_N, O_N}, {"dstore_0"}}, +{ 0x48, -1, 1, {O_N, O_N}, {"dstore_1"}}, +{ 0x49, -1, 1, {O_N, O_N}, {"dstore_2"}}, +{ 0x4a, -1, 1, {O_N, O_N}, {"dstore_3"}}, +{ 0x4b, -1, 1, {O_N, O_N}, {"astore_0"}}, +{ 0x4c, -1, 1, {O_N, O_N}, {"astore_1"}}, +{ 0x4d, -1, 1, {O_N, O_N}, {"astore_2"}}, +{ 0x4e, -1, 1, {O_N, O_N}, {"astore_3"}}, +{ 0x4f, -1, 1, {O_N, O_N}, {"iastore"}}, +{ 0x50, -1, 1, {O_N, O_N}, {"lastore"}}, +{ 0x51, -1, 1, {O_N, O_N}, {"fastore"}}, +{ 0x52, -1, 1, {O_N, O_N}, {"dastore"}}, +{ 0x53, -1, 1, {O_N, O_N}, {"aastore"}}, +{ 0x54, -1, 1, {O_N, O_N}, {"bastore"}}, +{ 0x55, -1, 1, {O_N, O_N}, {"castore"}}, +{ 0x56, -1, 1, {O_N, O_N}, {"sastore"}}, +{ 0x57, -1, 1, {O_N, O_N}, {"pop"}}, +{ 0x58, -1, 1, {O_N, O_N}, {"pop2"}}, +{ 0x59, -1, 1, {O_N, O_N}, {"dup"}}, +{ 0x5a, -1, 1, {O_N, O_N}, {"dup_x1"}}, +{ 0x5b, -1, 1, {O_N, O_N}, {"dup_x2"}}, +{ 0x5c, -1, 1, {O_N, O_N}, {"dup2"}}, +{ 0x5d, -1, 1, {O_N, O_N}, {"dup2_x1"}}, +{ 0x5e, -1, 1, {O_N, O_N}, {"dup2_x2"}}, +{ 0x5f, -1, 1, {O_N, O_N}, {"swap"}}, +{ 0x60, -1, 1, {O_N, O_N}, {"iadd"}}, +{ 0x61, -1, 1, {O_N, O_N}, {"ladd"}}, +{ 0x62, -1, 1, {O_N, O_N}, {"fadd"}}, +{ 0x63, -1, 1, {O_N, O_N}, {"dadd"}}, +{ 0x64, -1, 1, {O_N, O_N}, {"isub"}}, +{ 0x65, -1, 1, {O_N, O_N}, {"lsub"}}, +{ 0x66, -1, 1, {O_N, O_N}, {"fsub"}}, +{ 0x67, -1, 1, {O_N, O_N}, {"dsub"}}, +{ 0x68, -1, 1, {O_N, O_N}, {"imul"}}, +{ 0x69, -1, 1, {O_N, O_N}, {"lmul"}}, +{ 0x6a, -1, 1, {O_N, O_N}, {"fmul"}}, +{ 0x6b, -1, 1, {O_N, O_N}, {"dmul"}}, +{ 0x6c, -1, 1, {O_N, O_N}, {"idiv"}}, +{ 0x6d, -1, 1, {O_N, O_N}, {"ldiv"}}, +{ 0x6e, -1, 1, {O_N, O_N}, {"fdiv"}}, +{ 0x6f, -1, 1, {O_N, O_N}, {"ddiv"}}, +{ 0x70, -1, 1, {O_N, O_N}, {"irem"}}, +{ 0x71, -1, 1, {O_N, O_N}, {"lrem"}}, +{ 0x72, -1, 1, {O_N, O_N}, {"frem"}}, +{ 0x73, -1, 1, {O_N, O_N}, {"drem"}}, +{ 0x74, -1, 1, {O_N, O_N}, {"ineg"}}, +{ 0x75, -1, 1, {O_N, O_N}, {"lneg"}}, +{ 0x76, -1, 1, {O_N, O_N}, {"fneg"}}, +{ 0x77, -1, 1, {O_N, O_N}, {"dneg"}}, +{ 0x78, -1, 1, {O_N, O_N}, {"ishl"}}, +{ 0x79, -1, 1, {O_N, O_N}, {"lshl"}}, +{ 0x7a, -1, 1, {O_N, O_N}, {"ishr"}}, +{ 0x7b, -1, 1, {O_N, O_N}, {"lshr"}}, +{ 0x7c, -1, 1, {O_N, O_N}, {"iushr"}}, +{ 0x7d, -1, 1, {O_N, O_N}, {"lushr"}}, +{ 0x7e, -1, 1, {O_N, O_N}, {"iand"}}, +{ 0x7f, -1, 1, {O_N, O_N}, {"land"}}, +{ 0x80, -1, 1, {O_N, O_N}, {"ior"}}, +{ 0x81, -1, 1, {O_N, O_N}, {"lor"}}, +{ 0x82, -1, 1, {O_N, O_N}, {"ixor"}}, +{ 0x83, -1, 1, {O_N, O_N}, {"lxor"}}, +{ 0x84, -1, 3, {O_U8, O_8}, {"iinc"}}, +{ 0x85, -1, 1, {O_N, O_N}, {"i2l"}}, +{ 0x86, -1, 1, {O_N, O_N}, {"i2f"}}, +{ 0x87, -1, 1, {O_N, O_N}, {"i2d"}}, +{ 0x88, -1, 1, {O_N, O_N}, {"l2i"}}, +{ 0x89, -1, 1, {O_N, O_N}, {"l2f"}}, +{ 0x8a, -1, 1, {O_N, O_N}, {"l2d"}}, +{ 0x8b, -1, 1, {O_N, O_N}, {"f2i"}}, +{ 0x8c, -1, 1, {O_N, O_N}, {"f2l"}}, +{ 0x8d, -1, 1, {O_N, O_N}, {"f2d"}}, +{ 0x8e, -1, 1, {O_N, O_N}, {"d2i"}}, +{ 0x8f, -1, 1, {O_N, O_N}, {"d2l"}}, +{ 0x90, -1, 1, {O_N, O_N}, {"d2f"}}, +{ 0x91, -1, 1, {O_N, O_N}, {"i2b"}}, +{ 0x92, -1, 1, {O_N, O_N}, {"i2c"}}, +{ 0x93, -1, 1, {O_N, O_N}, {"i2s"}}, +{ 0x94, -1, 1, {O_N, O_N}, {"lcmp"}}, +{ 0x95, -1, 1, {O_N, O_N}, {"fcmpl"}}, +{ 0x96, -1, 1, {O_N, O_N}, {"fcmpg"}}, +{ 0x97, -1, 1, {O_N, O_N}, {"dcmpl"}}, +{ 0x98, -1, 1, {O_N, O_N}, {"dcmpg"}}, +{ 0x99, -1, 3, {O_R16, O_N}, {"ifeq"}}, +{ 0x9a, -1, 3, {O_R16, O_N}, {"ifne"}}, +{ 0x9b, -1, 3, {O_R16, O_N}, {"iflt"}}, +{ 0x9c, -1, 3, {O_R16, O_N}, {"ifge"}}, +{ 0x9d, -1, 3, {O_R16, O_N}, {"ifgt"}}, +{ 0x9e, -1, 3, {O_R16, O_N}, {"ifle"}}, +{ 0x9f, -1, 3, {O_R16, O_N}, {"if_icmpeq"}}, +{ 0xa0, -1, 3, {O_R16, O_N}, {"if_icmpne"}}, +{ 0xa1, -1, 3, {O_R16, O_N}, {"if_icmplt"}}, +{ 0xa2, -1, 3, {O_R16, O_N}, {"if_icmpge"}}, +{ 0xa3, -1, 3, {O_R16, O_N}, {"if_icmpgt"}}, +{ 0xa4, -1, 3, {O_R16, O_N}, {"if_icmple"}}, +{ 0xa5, -1, 3, {O_R16, O_N}, {"if_acmpeq"}}, +{ 0xa6, -1, 3, {O_R16, O_N}, {"if_acmpne"}}, +{ 0xa7, -1, 3, {O_R16, O_N}, {"goto"}}, +{ 0xa8, -1, 3, {O_R16, O_N}, {"jsr"}}, +{ 0xa9, -1, 2, {O_U8, O_N}, {"ret"}}, +{ 0xaa, -1, 1, {O_N, O_N}, {"tableswitch"}}, +{ 0xab, -1, 1, {O_N, O_N}, {"lookupswitch"}}, +{ 0xac, -1, 1, {O_N, O_N}, {"ireturn"}}, +{ 0xad, -1, 1, {O_N, O_N}, {"lreturn"}}, +{ 0xae, -1, 1, {O_N, O_N}, {"freturn"}}, +{ 0xaf, -1, 1, {O_N, O_N}, {"dreturn"}}, +{ 0xb0, -1, 1, {O_N, O_N}, {"areturn"}}, +{ 0xb1, -1, 1, {O_N, O_N}, {"return"}}, +{ 0xb2, -1, 3, {O_U16, O_N}, {"getstatic"}}, +{ 0xb3, -1, 3, {O_U16, O_N}, {"putstatic"}}, +{ 0xb4, -1, 3, {O_U16, O_N}, {"getfield"}}, +{ 0xb5, -1, 3, {O_U16, O_N}, {"putfield"}}, +{ 0xb6, -1, 3, {O_U16, O_N}, {"invokevirtual"}}, +{ 0xb7, -1, 3, {O_U16, O_N}, {"invokespecial"}}, +{ 0xb8, -1, 3, {O_U16, O_N}, {"invokestatic"}}, +{ 0xb9, -1, 5, {O_U16, O_U8}, {"invokeinterface"}}, +{ 0xba, -1, 1, {O_N, O_N}, {"bad_ba"}}, +{ 0xbb, -1, 3, {O_N, O_N}, {"new"}}, +{ 0xbc, -1, 2, {O_N, O_N}, {"newarray"}}, +{ 0xbd, -1, 3, {O_N, O_N}, {"anewarray"}}, +{ 0xbe, -1, 1, {O_N, O_N}, {"arraylength"}}, +{ 0xbf, -1, 1, {O_N, O_N}, {"athrow"}}, +{ 0xc0, -1, 3, {O_N, O_N}, {"checkcast"}}, +{ 0xc1, -1, 3, {O_N, O_N}, {"instanceof"}}, +{ 0xc2, -1, 1, {O_N, O_N}, {"monitorenter"}}, +{ 0xc3, -1, 1, {O_N, O_N}, {"monitorexit"}}, +{ 0xc4, -1, 1, {O_N, O_N}, {"wide"}}, +{ 0xc5, -1, 4, {O_N, O_N}, {"multianewarray"}}, +{ 0xc6, -1, 3, {O_N, O_N}, {"ifnull"}}, +{ 0xc7, -1, 3, {O_N, O_N}, {"ifnonnull"}}, +{ 0xc8, -1, 5, {O_R32, O_N}, {"goto_w"}}, +{ 0xc9, -1, 5, {O_R32, O_N}, {"jsr_w"}}, +{ 0xca, -1, 3, {O_N, O_N}, {"breakpoint"}}, +{ 0xcb, -1, 2, {O_U8, O_N}, {"ldc_quick"}}, +{ 0xcc, -1, 3, {O_U16, O_N}, {"ldc_w_quick"}}, +{ 0xcd, -1, 3, {O_U16, O_N}, {"ldc2_w_quick"}}, +{ 0xce, -1, 3, {O_U16, O_N}, {"getfield_quick"}}, +{ 0xcf, -1, 3, {O_U16, O_N}, {"putfield_quick"}}, +{ 0xd0, -1, 3, {O_U16, O_N}, {"getfield2_quick"}}, +{ 0xd1, -1, 3, {O_U16, O_N}, {"putfield2_quick"}}, +{ 0xd2, -1, 3, {O_U16, O_N}, {"getstatic_quick"}}, +{ 0xd3, -1, 3, {O_U16, O_N}, {"putstatic_quick"}}, +{ 0xd4, -1, 3, {O_U16, O_N}, {"getstatic2_quick"}}, +{ 0xd5, -1, 3, {O_U16, O_N}, {"putstatic2_quick"}}, +{ 0xd6, -1, 3, {O_U16, O_N}, {"invokevirtual_quick"}}, +{ 0xd7, -1, 3, {O_U16, O_N}, {"invokenonvirtual_quick"}}, +{ 0xd8, -1, 3, {O_U16, O_N}, {"invokesuper_quick"}}, +{ 0xd9, -1, 3, {O_U16, O_N}, {"invokestatic_quick"}}, +{ 0xda, -1, 3, {O_U16, O_N}, {"invokeinterface_quick"}}, +{ 0xdb, -1, 1, {O_N, O_N}, {"bad_db"}}, +{ 0xdc, -1, 1, {O_N, O_N}, {"aastore_quick"}}, +{ 0xdd, -1, 3, {O_U16, O_N}, {"new_quick"}}, +{ 0xde, -1, 3, {O_U16, O_N}, {"anewarray_quick"}}, +{ 0xdf, -1, 3, {O_U16, O_N}, {"multianewarray_quick"}}, +{ 0xe0, -1, 3, {O_U16, O_N}, {"checkcast_quick"}}, +{ 0xe1, -1, 3, {O_U16, O_N}, {"instanceof_quick"}}, +{ 0xe2, -1, 3, {O_U16, O_N}, {"invokevirtiual_quick_w"}}, +{ 0xe3, -1, 3, {O_U16, O_N}, {"getfield_quick_w"}}, +{ 0xe4, -1, 3, {O_U16, O_N}, {"putfield_quick_w"}}, +{ 0xe5, -1, 1, {O_N, O_N}, {"nonnull_quick"}}, +{ 0xe6, -1, 3, {O_U16, O_N}, {"agetfield_quick"}}, +{ 0xe7, -1, 3, {O_U16, O_N}, {"aputfield_quick"}}, +{ 0xe8, -1, 3, {O_U16, O_N}, {"agetstatic_quick"}}, +{ 0xe9, -1, 3, {O_U16, O_N}, {"aputstatic_quick"}}, +{ 0xea, -1, 2, {O_U8, O_N}, {"aldc_quick"}}, +{ 0xeb, -1, 3, {O_U16, O_N}, {"aldc_w_quick"}}, +{ 0xec, -1, 1, {O_N, O_N}, {"exit_sync_method"}}, +{ 0xed, -1, 3, {O_16, O_N}, {"sethi"}}, +{ 0xee, -1, 3, {O_U8, O_8}, {"load_word_index"}}, +{ 0xef, -1, 3, {O_U8, O_8}, {"load_short_index"}}, +{ 0xf0, -1, 3, {O_U8, O_8}, {"load_char_index"}}, +{ 0xf1, -1, 3, {O_U8, O_8}, {"load_byte_index"}}, +{ 0xf2, -1, 3, {O_U8, O_8}, {"load_ubyte_index"}}, +{ 0xf3, -1, 3, {O_U8, O_8}, {"store_word_index"}}, +{ 0xf4, -1, 3, {O_U8, O_8}, {"na_store_word_index"}}, +{ 0xf5, -1, 3, {O_U8, O_8}, {"store_short_index"}}, +{ 0xf6, -1, 3, {O_U8, O_8}, {"store_byte_index"}}, +{ 0xf7, -1, 1, {O_N, O_N}, {"bad_f7"}}, +{ 0xf8, -1, 1, {O_N, O_N}, {"bad_f8"}}, +{ 0xf9, -1, 1, {O_N, O_N}, {"bad_f9"}}, +{ 0xfa, -1, 1, {O_N, O_N}, {"bad_fa"}}, +{ 0xfb, -1, 1, {O_N, O_N}, {"bad_fb"}}, +{ 0xfc, -1, 1, {O_N, O_N}, {"bad_fc"}}, +{ 0xfd, -1, 1, {O_N, O_N}, {"bad_fd"}}, +{ 0xfe, -1, 1, {O_N, O_N}, {"bad_fe"}}, + +{ 0xff, 0x00, 2, {O_N, O_N}, {"load_ubyte"}}, +{ 0xff, 0x01, 2, {O_N, O_N}, {"load_byte"}}, +{ 0xff, 0x02, 2, {O_N, O_N}, {"load_char"}}, +{ 0xff, 0x03, 2, {O_N, O_N}, {"load_short"}}, +{ 0xff, 0x04, 2, {O_N, O_N}, {"load_word"}}, +{ 0xff, 0x05, 2, {O_N, O_N}, {"priv_ret_from_trap"}}, +{ 0xff, 0x06, 2, {O_N, O_N}, {"priv_read_dcache_tag"}}, +{ 0xff, 0x07, 2, {O_N, O_N}, {"priv_read_dcache_data"}}, +{ 0xff, 0x08, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x09, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x0a, 2, {O_N, O_N}, {"load_char_oe"}}, +{ 0xff, 0x0b, 2, {O_N, O_N}, {"load_short_oe"}}, +{ 0xff, 0x0c, 2, {O_N, O_N}, {"load_word_oe"}}, +{ 0xff, 0x0d, 2, {O_N, O_N}, {"return0"}}, +{ 0xff, 0x0e, 2, {O_N, O_N}, {"priv_read_icache_tag"}}, +{ 0xff, 0x0f, 2, {O_N, O_N}, {"priv_read_icache_data"}}, +{ 0xff, 0x10, 2, {O_N, O_N}, {"ncload_ubyte"}}, +{ 0xff, 0x11, 2, {O_N, O_N}, {"ncload_byte"}}, +{ 0xff, 0x12, 2, {O_N, O_N}, {"ncload_char"}}, +{ 0xff, 0x13, 2, {O_N, O_N}, {"ncload_short"}}, +{ 0xff, 0x14, 2, {O_N, O_N}, {"ncload_word"}}, +{ 0xff, 0x15, 2, {O_N, O_N}, {"iucmp"}}, +{ 0xff, 0x16, 2, {O_N, O_N}, {"priv_powerdown"}}, +{ 0xff, 0x17, 2, {O_N, O_N}, {"cache_invalidate"}}, +{ 0xff, 0x18, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x19, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x1a, 2, {O_N, O_N}, {"ncload_char_oe"}}, +{ 0xff, 0x1b, 2, {O_N, O_N}, {"ncload_short_oe"}}, +{ 0xff, 0x1c, 2, {O_N, O_N}, {"ncload_word_oe"}}, +{ 0xff, 0x1d, 2, {O_N, O_N}, {"return1"}}, +{ 0xff, 0x1e, 2, {O_N, O_N}, {"cache_flush"}}, +{ 0xff, 0x1f, 2, {O_N, O_N}, {"cache_index_flush"}}, +{ 0xff, 0x20, 2, {O_N, O_N}, {"store_byte"}}, +{ 0xff, 0x21, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x22, 2, {O_N, O_N}, {"store_short"}}, +{ 0xff, 0x23, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x24, 2, {O_N, O_N}, {"store_word"}}, +{ 0xff, 0x25, 2, {O_N, O_N}, {"soft_trap"}}, +{ 0xff, 0x26, 2, {O_N, O_N}, {"priv_write_dcache_tag"}}, +{ 0xff, 0x27, 2, {O_N, O_N}, {"priv_write_dcache_data"}}, +{ 0xff, 0x28, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x29, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x2a, 2, {O_N, O_N}, {"store_short_oe"}}, +{ 0xff, 0x2b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x2c, 2, {O_N, O_N}, {"store_word_oe"}}, +{ 0xff, 0x2d, 2, {O_N, O_N}, {"return2"}}, +{ 0xff, 0x2e, 2, {O_N, O_N}, {"priv_write_icache_tag"}}, +{ 0xff, 0x2f, 2, {O_N, O_N}, {"priv_write_icache_data"}}, +{ 0xff, 0x30, 2, {O_N, O_N}, {"ncstore_byte"}}, +{ 0xff, 0x31, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x32, 2, {O_N, O_N}, {"ncstore_short"}}, +{ 0xff, 0x33, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x34, 2, {O_N, O_N}, {"ncstore_word"}}, +{ 0xff, 0x35, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x36, 2, {O_N, O_N}, {"priv_reset"}}, +{ 0xff, 0x37, 2, {O_N, O_N}, {"get_current_class"}}, +{ 0xff, 0x38, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x39, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x3a, 2, {O_N, O_N}, {"ncstore_short_oe"}}, +{ 0xff, 0x3b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x3c, 2, {O_N, O_N}, {"ncstore_word_oe"}}, +{ 0xff, 0x3d, 2, {O_N, O_N}, {"call"}}, +{ 0xff, 0x3e, 2, {O_N, O_N}, {"zero_line"}}, +{ 0xff, 0x3f, 2, {O_N, O_N}, {"priv_update_optop"}}, +{ 0xff, 0x40, 2, {O_N, O_N}, {"read_pc"}}, +{ 0xff, 0x41, 2, {O_N, O_N}, {"read_vars"}}, +{ 0xff, 0x42, 2, {O_N, O_N}, {"read_frame"}}, +{ 0xff, 0x43, 2, {O_N, O_N}, {"read_optop"}}, +{ 0xff, 0x44, 2, {O_N, O_N}, {"priv_read_oplim"}}, +{ 0xff, 0x45, 2, {O_N, O_N}, {"read_const_pool"}}, +{ 0xff, 0x46, 2, {O_N, O_N}, {"priv_read_psr"}}, +{ 0xff, 0x47, 2, {O_N, O_N}, {"priv_read_trapbase"}}, +{ 0xff, 0x48, 2, {O_N, O_N}, {"priv_read_lockcount0"}}, +{ 0xff, 0x49, 2, {O_N, O_N}, {"priv_read_lockcount1"}}, +{ 0xff, 0x4a, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x4b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x4c, 2, {O_N, O_N}, {"priv_read_lockaddr0"}}, +{ 0xff, 0x4d, 2, {O_N, O_N}, {"priv_read_lockaddr1"}}, +{ 0xff, 0x4e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x4f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x50, 2, {O_N, O_N}, {"priv_read_userrange1"}}, +{ 0xff, 0x51, 2, {O_N, O_N}, {"priv_read_gc_config"}}, +{ 0xff, 0x52, 2, {O_N, O_N}, {"priv_read_brk1a"}}, +{ 0xff, 0x53, 2, {O_N, O_N}, {"priv_read_brk2a"}}, +{ 0xff, 0x54, 2, {O_N, O_N}, {"priv_read_brk12c"}}, +{ 0xff, 0x55, 2, {O_N, O_N}, {"priv_read_userrange2"}}, +{ 0xff, 0x56, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x57, 2, {O_N, O_N}, {"priv_read_versionid"}}, +{ 0xff, 0x58, 2, {O_N, O_N}, {"priv_read_hcr"}}, +{ 0xff, 0x59, 2, {O_N, O_N}, {"priv_read_sc_bottom"}}, +{ 0xff, 0x5a, 2, {O_N, O_N}, {"read_global0"}}, +{ 0xff, 0x5b, 2, {O_N, O_N}, {"read_global1"}}, +{ 0xff, 0x5c, 2, {O_N, O_N}, {"read_global2"}}, +{ 0xff, 0x5d, 2, {O_N, O_N}, {"read_global3"}}, +{ 0xff, 0x5e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x5f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x60, 2, {O_N, O_N}, {"write_pc"}}, +{ 0xff, 0x61, 2, {O_N, O_N}, {"write_vars"}}, +{ 0xff, 0x62, 2, {O_N, O_N}, {"write_frame"}}, +{ 0xff, 0x63, 2, {O_N, O_N}, {"write_optop"}}, +{ 0xff, 0x64, 2, {O_N, O_N}, {"priv_write_oplim"}}, +{ 0xff, 0x65, 2, {O_N, O_N}, {"write_const_pool"}}, +{ 0xff, 0x66, 2, {O_N, O_N}, {"priv_write_psr"}}, +{ 0xff, 0x67, 2, {O_N, O_N}, {"priv_write_trapbase"}}, +{ 0xff, 0x68, 2, {O_N, O_N}, {"priv_write_lockcount0"}}, +{ 0xff, 0x69, 2, {O_N, O_N}, {"priv_write_lockcount1"}}, +{ 0xff, 0x6a, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x6b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x6c, 2, {O_N, O_N}, {"priv_write_lockaddr0"}}, +{ 0xff, 0x6d, 2, {O_N, O_N}, {"priv_write_lockaddr1"}}, +{ 0xff, 0x6e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x6f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x70, 2, {O_N, O_N}, {"priv_write_userrange1"}}, +{ 0xff, 0x71, 2, {O_N, O_N}, {"priv_write_gc_config"}}, +{ 0xff, 0x72, 2, {O_N, O_N}, {"priv_write_brk1a"}}, +{ 0xff, 0x73, 2, {O_N, O_N}, {"priv_write_brk2a"}}, +{ 0xff, 0x74, 2, {O_N, O_N}, {"priv_write_brk12c"}}, +{ 0xff, 0x75, 2, {O_N, O_N}, {"priv_write_userrange2"}}, +{ 0xff, 0x76, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x77, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x78, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x79, 2, {O_N, O_N}, {"priv_write_sc_bottom"}}, +{ 0xff, 0x7a, 2, {O_N, O_N}, {"write_global0"}}, +{ 0xff, 0x7b, 2, {O_N, O_N}, {"write_global1"}}, +{ 0xff, 0x7c, 2, {O_N, O_N}, {"write_global2"}}, +{ 0xff, 0x7d, 2, {O_N, O_N}, {"write_global3"}}, +{ 0xff, 0x7e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x7f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x80, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x81, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x82, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x83, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x84, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x85, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x86, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x87, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x88, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x89, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8a, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8c, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8d, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x8f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x90, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x91, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x92, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x93, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x94, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x95, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x96, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x97, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x98, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x99, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9a, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9b, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9c, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9d, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9e, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0x9f, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa0, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa1, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xa9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xaa, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xab, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xac, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xad, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xae, 2, {O_N, O_N}, {"bad"}}, /*LM_FIXED*/ +{ 0xff, 0xaf, 2, {O_N, O_N}, {"bad"}}, /*LM_FIXED*/ +{ 0xff, 0xb0, 2, {O_N, O_N}, {"bad"}}, /*LM_FIXED*/ +{ 0xff, 0xb1, 2, {O_N, O_N}, {"bad"}}, /*LM_FIXED*/ +{ 0xff, 0xb2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xb9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xba, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xbb, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xbc, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xbd, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xbe, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xbf, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc0, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc1, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xc9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xca, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xcb, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xcc, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xcd, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xce, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xcf, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd0, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd1, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xd9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xda, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xdb, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xdc, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xdd, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xde, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xdf, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe0, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe1, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xe9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xea, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xeb, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xec, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xed, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xee, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xef, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf0, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf1, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf2, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf3, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf4, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf5, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf6, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf7, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf8, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xf9, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xfa, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xfb, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xfc, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xfd, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xfe, 2, {O_N, O_N}, {"bad"}}, +{ 0xff, 0xff, 2, {O_N, O_N}, {"bad"}}, +}; diff --git a/external/gpl3/gdb/dist/opcodes/po/Make-in b/external/gpl3/gdb/dist/opcodes/po/Make-in new file mode 100644 index 000000000000..7d5556f568e8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper +# Copyright (C) 2003, 2006, 2007, 2009 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +PACKAGE = @PACKAGE@ +VERSION = @VERSION@ + +SHELL = /bin/sh +@SET_MAKE@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +top_builddir = @top_builddir@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +datadir = $(prefix)/@DATADIRNAME@ +localedir = $(datadir)/locale +gnulocaledir = $(prefix)/share/locale +gettextsrcdir = $(prefix)/share/gettext/po +subdir = po + +DESTDIR = + +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +MKINSTALLDIRS = @MKINSTALLDIRS@ + +CC = @CC@ +GENCAT = @GENCAT@ +GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ +MSGFMT = @MSGFMT@ +XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ +MSGMERGE = PATH=../src:$$PATH msgmerge + +DEFS = @DEFS@ +CFLAGS = @CFLAGS@ +CPPFLAGS = @CPPFLAGS@ + +INCLUDES = -I.. -I$(top_srcdir)/intl + +COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) + +SOURCES = cat-id-tbl.c +POFILES = @POFILES@ +GMOFILES = @GMOFILES@ +DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ +stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) + +POTFILES = \ + +CATALOGS = @CATALOGS@ +CATOBJEXT = @CATOBJEXT@ +INSTOBJEXT = @INSTOBJEXT@ + +.SUFFIXES: +.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat + +.c.o: + $(COMPILE) $< + +.po.pox: + $(MAKE) $(PACKAGE).pot + $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox + +.po.mo: + $(MSGFMT) -o $@ $< + +.po.gmo: + file=`echo $* | sed 's,.*/,,'`.gmo \ + && rm -f $$file && $(GMSGFMT) -o $$file $< + +.po.cat: + sed -f ../intl/po2msg.sed < $< > $*.msg \ + && rm -f $@ && $(GENCAT) $@ $*.msg + + +all: all-@USE_NLS@ + +all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot +all-no: + +$(srcdir)/$(PACKAGE).pot: $(POTFILES) + $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ + --add-comments --keyword=_ --keyword=N_ \ + --msgid-bugs-address=bug-binutils@gnu.org \ + --files-from=$(srcdir)/POTFILES.in + rm -f $(srcdir)/$(PACKAGE).pot + mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot + +$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: +$(srcdir)/stamp-cat-id: $(PACKAGE).pot + rm -f cat-id-tbl.tmp + sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ + | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp + if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ + rm cat-id-tbl.tmp; \ + else \ + echo cat-id-tbl.c changed; \ + rm -f $(srcdir)/cat-id-tbl.c; \ + mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ + fi + cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id + + +install: install-exec install-data +install-exec: +install-info: +install-html: +install-pdf: +install-data: install-data-@USE_NLS@ +install-data-no: all +install-data-yes: all + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \ + else \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \ + fi + @catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + case "$$cat" in \ + *.gmo) destdir=$(gnulocaledir);; \ + *) destdir=$(localedir);; \ + esac; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $$dir; \ + else \ + $(top_srcdir)/mkinstalldirs $$dir; \ + fi; \ + if test -r $$cat; then \ + $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + else \ + $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ + fi; \ + if test -r $$cat.m; then \ + $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + if test -r $(srcdir)/$$cat.m ; then \ + $(INSTALL_DATA) $(srcdir)/$$cat.m \ + $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ + echo "installing $(srcdir)/$$cat as" \ + "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ + else \ + true; \ + fi; \ + fi; \ + done + if test "$(PACKAGE)" = "gettext"; then \ + if test -r $(MKINSTALLDIRS); then \ + $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \ + else \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \ + fi; \ + $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ + $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \ + else \ + : ; \ + fi + +# Define this as empty until I found a useful application. +installcheck: + +uninstall: + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + done + rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in + +check: all + +cat-id-tbl.o: ../intl/libgettext.h + +html dvi pdf ps info tags TAGS ID: + +mostlyclean: + rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp + rm -fr *.o + +clean: mostlyclean + +distclean: clean + rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m + +maintainer-clean: distclean + @echo "This command is intended for maintainers to use;" + @echo "it deletes files that may require special tools to rebuild." + rm -f $(GMOFILES) + +distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) +dist distdir: update-po $(DISTFILES) + dists="$(DISTFILES)"; \ + for file in $$dists; do \ + ln $(srcdir)/$$file $(distdir) 2> /dev/null \ + || cp -p $(srcdir)/$$file $(distdir); \ + done + +update-po: Makefile + $(MAKE) $(PACKAGE).pot + PATH=`pwd`/../src:$$PATH; \ + cd $(srcdir); \ + catalogs='$(CATALOGS)'; \ + for cat in $$catalogs; do \ + cat=`basename $$cat`; \ + lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ + mv $$lang.po $$lang.old.po; \ + echo "$$lang:"; \ + if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ + rm -f $$lang.old.po; \ + else \ + echo "msgmerge for $$cat failed!"; \ + rm -f $$lang.po; \ + mv $$lang.old.po $$lang.po; \ + fi; \ + done + +POTFILES: POTFILES.in + ( if test 'x$(srcdir)' != 'x.'; then \ + posrcprefix='$(top_srcdir)/'; \ + else \ + posrcprefix="../"; \ + fi; \ + rm -f $@-t $@ \ + && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ + -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ + | sed -e '$$s/\\$$//') > $@-t \ + && chmod a-w $@-t \ + && mv $@-t $@ ) + +POTFILES.in: @MAINT@ ../Makefile + cd .. && $(MAKE) po/POTFILES.in + +Makefile: Make-in ../config.status POTFILES + cd .. \ + && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ + CONFIG_HEADERS= $(SHELL) ./config.status + +# Tell versions [3.59,3.63) of GNU make not to export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/external/gpl3/gdb/dist/opcodes/po/POTFILES.in b/external/gpl3/gdb/dist/opcodes/po/POTFILES.in new file mode 100644 index 000000000000..9496c87ca378 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/POTFILES.in @@ -0,0 +1,203 @@ +alpha-dis.c +alpha-opc.c +arc-dis.c +arc-ext.c +arc-opc.c +arm-dis.c +avr-dis.c +bfin-dis.c +cgen-asm.c +cgen-bitset.c +cgen-dis.c +cgen-opc.c +cr16-dis.c +cr16-opc.c +cris-dis.c +cris-opc.c +crx-dis.c +crx-opc.c +d10v-dis.c +d10v-opc.c +d30v-dis.c +d30v-opc.c +dis-buf.c +dis-init.c +disassemble.c +dlx-dis.c +fr30-asm.c +fr30-desc.c +fr30-desc.h +fr30-dis.c +fr30-ibld.c +fr30-opc.c +fr30-opc.h +frv-asm.c +frv-desc.c +frv-desc.h +frv-dis.c +frv-ibld.c +frv-opc.c +frv-opc.h +h8300-dis.c +h8500-dis.c +h8500-opc.h +hppa-dis.c +i370-dis.c +i370-opc.c +i386-dis.c +i386-gen.c +i386-init.h +i386-opc.c +i386-opc.h +i386-tbl.h +i860-dis.c +i960-dis.c +ia64-asmtab.c +ia64-asmtab.h +ia64-dis.c +ia64-gen.c +ia64-opc-a.c +ia64-opc-b.c +ia64-opc-d.c +ia64-opc-f.c +ia64-opc-i.c +ia64-opc-m.c +ia64-opc.c +ia64-opc.h +ip2k-asm.c +ip2k-desc.c +ip2k-desc.h +ip2k-dis.c +ip2k-ibld.c +ip2k-opc.c +ip2k-opc.h +iq2000-asm.c +iq2000-desc.c +iq2000-desc.h +iq2000-dis.c +iq2000-ibld.c +iq2000-opc.c +iq2000-opc.h +lm32-asm.c +lm32-desc.c +lm32-desc.h +lm32-dis.c +lm32-ibld.c +lm32-opc.c +lm32-opc.h +lm32-opinst.c +m10200-dis.c +m10200-opc.c +m10300-dis.c +m10300-opc.c +m32c-asm.c +m32c-desc.c +m32c-desc.h +m32c-dis.c +m32c-ibld.c +m32c-opc.c +m32c-opc.h +m32r-asm.c +m32r-desc.c +m32r-desc.h +m32r-dis.c +m32r-ibld.c +m32r-opc.c +m32r-opc.h +m32r-opinst.c +m68hc11-dis.c +m68hc11-opc.c +m68k-dis.c +m68k-opc.c +m88k-dis.c +mcore-dis.c +mcore-opc.h +mep-asm.c +mep-desc.c +mep-desc.h +mep-dis.c +mep-ibld.c +mep-opc.c +mep-opc.h +microblaze-dis.c +microblaze-opc.h +mips-dis.c +mips-opc.c +mips16-opc.c +mmix-dis.c +mmix-opc.c +moxie-dis.c +moxie-opc.c +msp430-dis.c +mt-asm.c +mt-desc.c +mt-desc.h +mt-dis.c +mt-ibld.c +mt-opc.c +mt-opc.h +ns32k-dis.c +openrisc-asm.c +openrisc-desc.c +openrisc-desc.h +openrisc-dis.c +openrisc-ibld.c +openrisc-opc.c +openrisc-opc.h +or32-dis.c +or32-opc.c +pdp11-dis.c +pdp11-opc.c +pj-dis.c +pj-opc.c +ppc-dis.c +ppc-opc.c +rx-decode.c +rx-dis.c +s390-dis.c +s390-mkopc.c +s390-opc.c +score-dis.c +score-opc.h +score7-dis.c +sh-dis.c +sh-opc.h +sh64-dis.c +sh64-opc.c +sh64-opc.h +sparc-dis.c +sparc-opc.c +spu-dis.c +spu-opc.c +sysdep.h +tic30-dis.c +tic4x-dis.c +tic54x-dis.c +tic54x-opc.c +tic6x-dis.c +tic80-dis.c +tic80-opc.c +v850-dis.c +v850-opc.c +vax-dis.c +w65-dis.c +w65-opc.h +xc16x-asm.c +xc16x-desc.c +xc16x-desc.h +xc16x-dis.c +xc16x-ibld.c +xc16x-opc.c +xc16x-opc.h +xstormy16-asm.c +xstormy16-desc.c +xstormy16-desc.h +xstormy16-dis.c +xstormy16-ibld.c +xstormy16-opc.c +xstormy16-opc.h +xtensa-dis.c +z80-dis.c +z8k-dis.c +z8k-opc.h +z8kgen.c diff --git a/external/gpl3/gdb/dist/opcodes/po/da.gmo b/external/gpl3/gdb/dist/opcodes/po/da.gmo new file mode 100644 index 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BSWW-{ literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/opcodes/po/da.po b/external/gpl3/gdb/dist/opcodes/po/da.po new file mode 100644 index 000000000000..253f22806216 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/da.po @@ -0,0 +1,1260 @@ +# Danish messages for opcodes. +# Copyright (C) 2001 Free Software Foundation, Inc. +# This file is distributed under the same license as the binutils package. +# Keld Simonsen , 2002,2011. +# Christian Rose , 2001. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:32+0100\n" +"PO-Revision-Date: 2011-01-26 09:35+0100\n" +"Last-Translator: Keld Simonsen \n" +"Language-Team: Danish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "operanden for betinget hop ligger på skæv adresse" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "hopperådet ligger på skæv adresse" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ugyldig limm-reference i sidste instruktion!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "" + +#: arc-opc.c:395 +#, fuzzy +msgid "auxiliary register not allowed here" +msgstr "indeksregistret er i indlæsningsintervallet" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "forsøg på at skrive i register, der kun kan læses fra" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "forsøg på at læse register, der kun kan skrives i" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "ugyldigt registerummer '%d'" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "for mange lange konstanter" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "" + +#: arc-opc.c:822 +#, fuzzy +msgid "store value must be zero" +msgstr "umiddelbar værdi skal være lige" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "fejl bed ld-operand" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Ukendt registernavn er angivet: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Ukendt disassembleralternativ: %s\n" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "udefineret" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Intern fejl i disassembleren" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "ukendt begrænsning \"%c\"" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operanden er uden for intervallet (%lu er ikke mellem %lu og %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "Ukendt fejl %d\n" + +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Adressen 0x%s ligger uden for tilladt område.\n" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "Registernummer er ikke gyldig " + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Register skal være mellem r0 og r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Register skal være mellem r0 og r15" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "Registerliste er ugyldig" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Ukendt felt %d ved tolkning.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "Mangler mnemonic i syntaksstreng" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "ukendt instruktion" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt \"%c\")" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaksfejl (tegnet \"%c\" forventedes, fandt slut på instruktion)" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "snavs ved slutning på linjen" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "ukendt form af instruktion" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "fejlagtig instruktion \"%.50s...\"" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "fejlagtig instruktion \"%.50s\"" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*ukendt*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Ukendt felt %d ved udskrift af instruktion.\n" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operanden er uden for intervallet (%ld er ikke mellem %ld og %lu)" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "operanden uden for intervallet (0x%lx ikke mellem 0 og 0x%lx)" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Ukendt felt %d ved konstruktion af instruktion.\n" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Ukendt felt %d ved afkodning af instruktion.\n" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Ukendt felt %d ved hentning af heltalsoperand.\n" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Ukendt felt %d ved hentning af vma-operand.\n" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Ukendt felt %d ved indstilling af heltalsoperand.\n" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Ukendt felt %d ved indstilling af vma-operand.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "manglende ']'" + +#: frv-asm.c:611 frv-asm.c:621 +#, fuzzy +msgid "Special purpose register number is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "Værdi af A-operand skal være 0 eller 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "registernummer skal være lige" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "manglende ')'" + +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Forstår ikke 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan ikke indsætte %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*ukendt*" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, fuzzy, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr "" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr "" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr "" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr "" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr "" + +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" + +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr "" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr "" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr "" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr "" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr "" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr "" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "" + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "" + +#: i386-gen.c:593 +#, fuzzy, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Ukendt fejl %d\n" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "" + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "" + +#. Invalid offset present. +#: ip2k-asm.c:106 +#, fuzzy +msgid "offset(IP) is not a valid form" +msgstr "afsæt ikke et produkt af 4" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +#, fuzzy +msgid "(DP) offset out of range." +msgstr "værdien er uden for intervallet" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +#, fuzzy +msgid "(SP) offset out of range." +msgstr "værdien er uden for intervallet" + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "" + +#: ip2k-asm.c:218 +#, fuzzy +msgid "operand out of range (not between 1 and 255)" +msgstr "operanden uden for intervallet (%lu ikke mellem 0 og %lu)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "" + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "" + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "" + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +#, fuzzy +msgid "immediate value cannot be register" +msgstr "umiddelbar værdi skal være lige" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +#, fuzzy +msgid "immediate value out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: iq2000-asm.c:182 +#, fuzzy +msgid "21-bit offset out of range" +msgstr "værdien er uden for intervallet" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "ukendt\t0x%04lx" + +#: m10200-dis.c:328 +#, fuzzy, c-format +msgid "unknown\t0x%02lx" +msgstr "ukendt\t0x%02x" + +#: m32c-asm.c:117 +#, fuzzy +msgid "imm:6 immediate is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "" + +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +#, fuzzy +msgid "dsp:8 immediate is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:184 m32c-asm.c:188 +#, fuzzy +msgid "Immediate is out of range -8 to 7" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:209 m32c-asm.c:213 +#, fuzzy +msgid "Immediate is out of range -7 to 8" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "" + +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +#, fuzzy +msgid "dsp:16 immediate is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:399 +#, fuzzy +msgid "dsp:20 immediate is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:425 m32c-asm.c:445 +#, fuzzy +msgid "dsp:24 immediate is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:478 +#, fuzzy +msgid "immediate is out of range 1-2" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:496 +#, fuzzy +msgid "immediate is out of range 1-8" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:514 +#, fuzzy +msgid "immediate is out of range 0-7" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:550 +#, fuzzy +msgid "immediate is out of range 2-9" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "" + +#: m32c-asm.c:606 m32c-asm.c:662 +#, fuzzy +msgid "bit,base is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +#, fuzzy +msgid "bit,base out of range for symbol" +msgstr "værdien er uden for intervallet" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, fuzzy, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "" + +#: mep-asm.c:336 +#, fuzzy +msgid "Immediate is out of range -32768 to 32767" +msgstr "umiddelbar værdi er uden for intervallet" + +#: mep-asm.c:356 +#, fuzzy +msgid "Immediate is out of range 0 to 65535" +msgstr "umiddelbar værdi er uden for intervallet" + +#: mep-asm.c:549 mep-asm.c:562 +#, fuzzy +msgid "Immediate is out of range -512 to 511" +msgstr "umiddelbar værdi er uden for intervallet" + +#: mep-asm.c:554 mep-asm.c:563 +#, fuzzy +msgid "Immediate is out of range -128 to 127" +msgstr "umiddelbar værdi er uden for intervallet" + +#: mep-asm.c:558 +#, fuzzy +msgid "Value is not aligned enough" +msgstr "forskydningsværdien ligger ikke på lige adresse" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "" + +#: mips-dis.c:975 +#, fuzzy, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# intern fejl, ukendt modifikator(%c)" + +#: mips-dis.c:1335 +#, fuzzy, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# intern fejl, ukendt modifikator(%c)" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# intern disassembler-fejl, ukendt modifikator (%c)" + +#: mips-dis.c:2177 +#, fuzzy, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Fejlagtig 'case' %d (%s) i %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Internt: ikke-fejltestet kode (test-tilfælde mangler): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(ukendt)" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*ukendt operandstype: %d*" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "" + +#: mt-asm.c:110 mt-asm.c:190 +#, fuzzy +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "operanden uden for intervallet (%lu ikke mellem 0 og %lu)" + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "" + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "" + +#: ppc-dis.c:523 +#, fuzzy, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "ugyldigt betinget flag" + +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "forsøg på at sætte y-bitten når modifikatoren + eller - blev brugt" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "ugyldig bitmaske" + +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "indeksregistret er i indlæsningsintervallet" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "ugyldig registeroperand ved opdatering" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "" + +#: ppc-opc.c:1451 +#, fuzzy +msgid "invalid constant" +msgstr "ugyldigt betinget flag" + +#: s390-dis.c:301 +#, fuzzy, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Følgende ARM-specifikke disassembleralternativ understøttes for brug\n" +"sammen med flaget -M:\n" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr "" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr "" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +#, fuzzy +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Intern fejl: dårlig sparc-opcode.h: \"%s\" == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "ukendt" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "ukendt operandskiftning: %x\n" + +#: v850-dis.c:377 +#, fuzzy, c-format +msgid "unknown reg: %d\n" +msgstr "ukendt pop-register: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "forskydningsværdien er ikke indenfor intervallet og ligger ikke på lige adresse" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "forskydningsværdien er uden for intervallet" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "forskydningsværdien ligger ikke på lige adresse" + +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "umiddelbar værdi er uden for intervallet" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "værdien for betinget hop er uden for intervallet" + +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "værdien for betinget hop er ikke inden for intervallet og til et ulige afsæt" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "betinget hop til ulige afsæt" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "ugyldigt register for stakjustering" + +#: v850-opc.c:518 +#, fuzzy +msgid "invalid register name" +msgstr "Forkert registernavn" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Forkert register i præinkrement" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Forkert register i postinkrement" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Forkert registernavn" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Etikette konflikter med registernavn" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Etikette konflikter med 'Rx'" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Forkert umiddelbart udtryk" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Lille operand var ikke et umiddelbart tal" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "" + +#~ msgid "unknown\t0x%04x" +#~ msgstr "ukendt\t0x%04x" + +#~ msgid "offset not between -2048 and 2047" +#~ msgstr "afsæt ikke mellem -2048 og 2047" + +#~ msgid "offset not between -8192 and 8191" +#~ msgstr "afsæt ikke mellem -8192 og 8191" + +#~ msgid "ignoring least significant bits in branch offset" +#~ msgstr "ignorerer mindste betydende bit i afsæt for betinget hop" + +#~ msgid "branch value not in range and to an odd offset" +#~ msgstr "værdien for betinget hop er ikke indenfor intervallet og til et ulige afsæt" + +#~ msgid "immediate value not in range and not even" +#~ msgstr "umiddelbar værdi er ikke indenfor intervallet og ikke lige" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "ukendt navn på nøgleord/register" diff --git a/external/gpl3/gdb/dist/opcodes/po/de.gmo b/external/gpl3/gdb/dist/opcodes/po/de.gmo new file mode 100644 index 0000000000000000000000000000000000000000..acd983f25e6427c1252ef5c52275a7edee3f35a5 GIT binary patch literal 16919 zcmd6udyr&TUB^$9huaB(ghzPiB+D=}yVFh2>}InWHcMt_9~pKxJIwB8LjvsH?!MD~ zGu^j4_uift8bdHZ5>Sa!Qe~U>Zic(fp>xJXDRg#@Xx_#gJ-W& z>LxG*cYz-OcY}Wqj)2d*S}BH7uL9{p9RsfeUk6?e-U~9cdI)?0_->0I0%ZxG1YZPx z-adaDd?C+20Qsk`VG=Tr9sGF-xF3{pUk5%Hd;q)_{AKW^;CWEme-V5>_+3!iUHP1t zeq$h0S2N(t!Mng6;Qin=;0M4Q_)+j6_-Sw&d@h6S1YZkEy9dBA@cp37{|n$G_+4-u zEIu!$TM695^P`}w|Fhur;6H&vr)M#!j61=fQSjBE%r^pMo{xY-;A7x+@DrfS)>hdzrgQ+r`V+Xz*`~4pMW0+zX3in%-p~?BJ@84 zeha(@Y_s_Hf?o$&l6nV1{3`H+;9l@wK;gd;Hc#Z^94PB~1iT7-56D0D1b;3E{}vQI z_DxXu{QDM%A-a6O9Ta{j+2{K}q1)R*S?2{%*8M3^>V3n0e;P!W{n!KU24_LphX?q> z($o{6(D6$kOH==9-(Sllgs+Z(EJeKml=VFbO8*}RbKuv(v*5SE*MoCRO4j>3AX89Z z0e6AVgo%VdromglbD+@aJ@)yF;2xe|L}Qk&=0M?}dqLr|-vg!nmqC%I{{Usa*TJ+h z&sT$Nv2rXv01AD66Qrv80?0pgIg=6G56Zgk0U2673i40=DSzbqWe{s0xEs6)yazlA zJ`M^!zX!^Eu40l>zW{2`0bc{&Z}Bfc>G$OZw{ zfXBi6KzaXX{J8~u8bs6J5m44w1D_4P8$=Y;`$1XPr$Fid-$5B~m_^(S9tCB+4}wD1 z-v?#?zhxH^AqC9|Nxj{{|F#d<(n`e1P(Nid-v{Uodyr0dSha zG}Vt$Rw*(cS+nfR6_iIP$tAQpNBKF*-IRwYPo>E9Vv4L`fg-eBro4@^NV%UP*9_%$ z$~}}Chbb?V2YbB{e7e1VC;0Oe;Sb^2?UXsnTPSh~UuCatJj_yl zky59eq3ox;hO(Q|riiR3m(R`HDTgR6$}Wo7s3nT%4!J~DucACx9=P5?5k8koQ-lX! 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Löwis , 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2004-02-28 12:30+0100\n" +"Last-Translator: Roland Illig \n" +"Language-Team: German \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "Sprung-Operand ist nicht ausgerichtet (unaligned)." + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "Sprunghinweis ist nicht ausgerichtet (unaligned)." + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ungültige limm-Referenz in der letzten Anweisung!\n" + +#: arm-dis.c:554 +msgid "" +msgstr "" + +#: arm-dis.c:1162 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Unbekannte Registernamensmenge: %s\n" + +#: arm-dis.c:1169 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Unbekannte Disassembler-Option: %s\n" + +#: arm-dis.c:1343 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Die folgenden ARM-spezifischen Disassembleroptionen werden in Kombination\n" +"mit dem Schalter »-M« unterstützt:\n" + +#: avr-dis.c:117 avr-dis.c:127 +msgid "undefined" +msgstr "undefiniert" + +#: avr-dis.c:179 +msgid "Internal disassembler error" +msgstr "Interner Disassemblerfehler." + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "Unbekannte Einschränkung »%c«" + +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %ld)" + +#: cgen-asm.c:369 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen %lu und %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +# Can't happen. +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Unbekannter Fehler %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adresse 0x%x ist außerhalb des gültigen Bereichs.\n" + +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Unbekanntes Feld %d beim Parsen entdeckt.\n" + +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 +msgid "missing mnemonic in syntax string" +msgstr "Fehlender Mnemonic im Syntaxstring" + +# We couldn't parse it. +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 +msgid "unrecognized instruction" +msgstr "Unbekannter Befehl" + +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "Syntaxfehler (erwartetes Zeichen »%c«, gefunden »%c«)" + +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "Syntaxfehler (Zeichen »%c« erwartet, Befehlsende bekommen)" + +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 +msgid "junk at end of line" +msgstr "Müll am Ende der Zeile" + +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 +msgid "unrecognized form of instruction" +msgstr "Unbekannte Befehlsform" + +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "Falscher Befehl »%.50s...«" + +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "Falscher Befehl »%.50s«" + +# Default text to print if an instruction isn't recognized. +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*unbekannt*" + +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Unbekanntes Feld %d beim Schreiben des Befehls.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen 0 und %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Unbekanntes Feld %d beim Erzeugen des Befehls.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Unbekannted Feld %d beim Decodieren des Befehls.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Unbekanntes Feld %d beim Holen des int-Operanden.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Unbekanntes Feld %d beim Setzen des int-Operanden.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "Die Registernummer muss gerade sein." + +#: h8300-dis.c:377 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:760 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Ich verstehe »0x%x« nicht.\n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "Kann nicht mit »inserv %d« umgehen.\n" + +# Couldn't understand anything. +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*unbekannt*" + +#: i386-dis.c:1699 +msgid "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Fehler:" + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Warnung:" + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "Mehrfache Bemerkung »%s« nicht verarbeitet.\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "Kann »ia64-ic.tbl« nicht zum Lesen finden\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "Kann »%s« nicht zum Lesen finden\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "Das letzte Format »%s« scheint strenger zu sein als »%s«.\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "Ãœberlappendes Feld »%s->%s«.\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "Ãœberschreibe Bemerkung %d mit Bemerkung %d (IC:%s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "Keine Ahnung, wie ich die Abhängigkeit »%% %s« angeben soll.\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Keine Ahnung, wie ich die Abhängigkeit »# %s« angeben soll.\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] hat weder Terminale noch Unterklassen\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s hat weder Terminale noch Unterklassen\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "Kein Befehl ist dem Terminal-IC »%s [%s]« direkt zugeordnet" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "Kein Befehl ist dem Terminal-IC »%s« direkt zugeordnet.\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "Die Klasse »%s« wurde definiert, aber nicht benutzt.\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Warnung: Die Ressource »%s (%s)« hat keine »chks%s«.\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "Die Ressource »%s (%s)« hat keine Register\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC Bemerkung %d in Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC Bemerkung %d für Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "Opcode %s hat keine Klasse (Operanden %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "Kann nicht in das Verzeichnis »%s« wechseln, errno = %s\n" + +# We've been passed a w. Return with an error message so that +# cgen will try the next parsing option. +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "Schlüsselwort »W« ist im Operandenplatz »FR« ungültig." + +# Invalid offset present. +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "»offset(IP)« ist keine gültige Form." + +# Found something there in front of (DP) but it's out +# of range. +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) Offset außerhalb des gültigen Bereichs." + +# Found something there in front of (SP) but it's out +# of range. +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) Offset außerhalb des gültigen Bereichs." + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "Unerlaubte Benutzung von Klammern." + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "Operand außerhalb des gültigen Bereichs (1 bis 255)." + +# Something is very wrong. opindex has to be one of the above. +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: Ungültiger Operatorindex." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Byteadresse benötigt -- muss gerade sein." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address: Gebe Symbol zurück. Sollte eigentlich ein Literal sein." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "Der Operand %operator muss ein Symbol sein." + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "Versuch, ein gesetztes Bit von 0 zu bestimmen" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "Ein Direktoperand kann kein Register sein." + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "Direktoperand außerhalb des gültigen Bereichs." + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "21-Bit-Offset außerhalb des gültigen Bereichs" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "Fehlende »)«." + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "unbekannt\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "unbekannt\t0x%04lx" + +#: m10300-dis.c:766 +#, c-format +msgid "unknown\t0x%04x" +msgstr "unbekannt\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# Interner Fehler, unvollständige Erweiterungsfolge (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# Interner Fehler, undefinierte Erweiterungsfolge (+%c)" + +#: mips-dis.c:1000 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# Interner Fehler, undefinierter Modifikator (%c)" + +#: mips-dis.c:1751 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# Interner Fehler im Disassembler: unerkannter Modifikator (%c)" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Die folgenden MIPS-spezifischen Disassembleroptionen werden zusammen\n" +"mit dem Schalter »-M« unterstützt (mehrere Optionen sollten durch\n" +"Kommata getrennt werden):\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Gib GPR-Namen entsprechend des angegebenen ABI aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" disassembliert wird.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Gib FPR-Namen entsprechend des angegebenen ABI aus.\n" +" Standard: numerisch.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Gib CP0-Registernamen entsprechend der angegebenen\n" +" Architektur aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" disassembliert wird.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Gib HWR-Namen entsprechend der angegebenen\n" +" Architektur aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" verarbeitet wird.\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Gib GPR- und FPR-Namen entsprechend des\n" +" angegebenen ABI aus.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Gib CP0-Register und HWR-Namen entsprechend der\n" +" angegebenen Architektur aus.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Für die obigen Optionen werden die folgenden Werte für »ABI« unterstützt:\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Für die obigen Optionen werden die folgenden Werte für »ARCH« unterstützt:\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Interner Fehler: case %d (%s) in %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Intern: Nicht gedebuggter Code (Testfall fehlt): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(unbekannt)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "Unbekannter Operandentyp: %d*" + +# I and Z are output operands and can`t be immediate +# * A is an address and we can`t have the address of +# * an immediate either. We don't know how much to increase +# * aoffsetp by since whatever generated this is broken +# * anyway! +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +msgid "$" +msgstr "$" + +#: ppc-opc.c:781 ppc-opc.c:809 +msgid "invalid conditional option" +msgstr "Ungültige bedingte Option" + +#: ppc-opc.c:811 +msgid "attempt to set y bit when using + or - modifier" +msgstr "Versuch, das y-Bit zusammen mit dem Modifikator »+« oder »-« zu setzen." + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "Offset muss ein Vielfaches von 16 sein" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "Offset muss ein Vielfaches von 2 sein" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "Offset darf nicht größer als 62 sein" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 +msgid "offset not a multiple of 4" +msgstr "Offset muss ein Vielfaches von 4 sein" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "Offset darf nicht größer als 124 sein" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "Offset muss ein Vielfaches von 8 sein" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "Offset darf nicht größer als 248 sein" + +#: ppc-opc.c:950 +msgid "offset not between -2048 and 2047" +msgstr "Offset muss im Bereich von -2048 bis 2047 liegen" + +#: ppc-opc.c:973 +msgid "offset not between -8192 and 8191" +msgstr "Offset muss im Bereich von -8192 bis 8191 liegen" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "Ignoriere ungültige mfcr-Maske." + +#: ppc-opc.c:1059 +msgid "ignoring least significant bits in branch offset" +msgstr "Ignoriere niedrigste Bits im Verzweigungsoffset" + +#: ppc-opc.c:1090 ppc-opc.c:1125 +msgid "illegal bitmask" +msgstr "Ungültige Bitmaske" + +#: ppc-opc.c:1192 +msgid "value out of range" +msgstr "Wert außerhalb des gültigen Bereichs" + +#: ppc-opc.c:1262 +msgid "index register in load range" +msgstr "Indexregister im Ladebereich (load range)" + +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "Die Operanden für das Quell- und Zielregister müssen verschieden sein" + +#: ppc-opc.c:1294 +msgid "invalid register operand when updating" +msgstr "Ungültiger Registeroperand beim Aktualisieren" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "Der Zielregisteroperand muss gerade sein" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "Der Quellregisteroperand muss gerade sein" + +# Mark as non-valid instruction. +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "unbekannt" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\" == \"%s\"\n" + +#: v850-dis.c:221 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "Unbekannte Operandenverschiebung: %x\n" + +#: v850-dis.c:233 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "Unbekanntes pop-Register: %d\n" + +# The functions used to insert and extract complicated operands. +# Note: There is a conspiracy between these functions and +# v850_insert_operand() in gas/config/tc-v850.c. Error messages +# containing the string 'out of range' will be ignored unless a +# specific command line option is given to GAS. +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "Der Abstandswert ist außerhalb des gültigen Bereichs und nicht ausgerichtet" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "Der Abstandswert ist außerhalb des fültigen Bereichs." + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "Der Abstandswert ist nicht ausgerichtet." + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "Direktwert außerhalb des gültigen Bereichs" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset." + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs." + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "Verzweigung auf ungeraden Offset" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset." + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "Ungültiges Register für Stackanpassung." + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "Direktwert außerhalb des gültigen Bereichs und nicht gerade" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "Der Direktoperand muss gerade sein." + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Ungültiges Register beim Pre-Increment" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Ungültiges Register beim Post-Increment" + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Falscher Registername." + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Sprungmarke verträgt sich nicht mit dem Registername" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Sprungmarke verträgt sich nicht mit »Rx«" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Ungültiger Direktausdruck" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Keine Verlagerung für kleine Direktwerte" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Kleiner Operand war keine Direktzahl." + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operand muss ein Symbol sein" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaxfehler: Kein abschließendes »)«" diff --git a/external/gpl3/gdb/dist/opcodes/po/es.gmo b/external/gpl3/gdb/dist/opcodes/po/es.gmo new file mode 100644 index 0000000000000000000000000000000000000000..82b773a2385a7c2a0646f0fdd7603d3988f9c434 GIT binary patch literal 25770 zcmc(n3z!^Nb?2`af>&c3jKKyQjLVV+jb!y`X7uoAED7snTVPp=B;y!kTQ%J^Gc9*_ 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+"Project-Id-Version: opcodes 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:32+0100\n" +"PO-Revision-Date: 2010-11-18 11:53-0600\n" +"Last-Translator: Cristian Othón Martínez Vera \n" +"Language-Team: Spanish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "operando de ramificación sin alinear" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "pista de salto sin alinear" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "¡Referencia limm ilegal en la última instrucción!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "no se pueden ajustar las constantes de valores diferentes en la instrucción" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "no se permite un registro auxiliar aquí" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "se intentó cambiar un registro de sólo lectura" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "se intentó leer un registro de sólo escritura" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "número de registro `%d' inválido" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "demasiadas constantes long" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "demasiados shimms en load" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "almacenamiento imposible" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "error de operando st" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "no se permite la escritura hacia atrás de dirección" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "el valor de almacenamiento debe ser cero" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "instrucción load/shimm inválida" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "error de operando ld" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "opciones de salto, pero no se ve .f" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "opciones de salto, pero no hay una dirección limm" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "se perdieron los bits de opción de dirección de salto limm" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "se intentó cambiar los bits HR" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "valor de opciones de salto erróneo" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "la dirección de ramificación no está en un límite de 4 bytes" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "se debe especificar un sufijo .jd o no nullify" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "No se reconoce el conjunto de nombres de registro: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "No se reconoce la opción de desensamblador: %s\n" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Las siguientes opciones de desensamblador específicas de ARM se admiten\n" +"para usarse con el interruptor -M:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "sin definir" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Error interno del desensamblador" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "restricción `%c' desconocida" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operando fuera de rango (%ld no está entre %ld y %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operando fuera de rango (%lu no está entre %lu y %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "Error desconocido %d\n" + +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "La dirección 0x%s está fuera de los límites.\n" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "El número de registro no es válido" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "El registro debe estar entre r0 y r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "El registro debe estar entre r8 y r15" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "La lista de registros no es válida" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "No se reconoció el campo %d al decodificar.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "falta el mnemónico en la cadena sintáctica" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "no se reconoce la instrucción" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "error sintáctico (se esperaba el carácter `%c', se encontró `%c')" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "error sintáctico (se esperaba el carácter `%c', se encontró el final de la instrucción)" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "basura al final de la línea" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "no se reconoce la forma de instrucción" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrucción errónea `%.50s...'" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrucción errónea `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*desconocida*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "No se reconoció el campo %d al mostrar insn.\n" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operando fuera de rango (%ld no está entre %ld y %lu)" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "operando fuera de rango (0x%lu no está entre 0 y %lx)" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "No se reconoció el campo %d al construir insn.\n" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "No se reconoció el campo %d al decodificar insn.\n" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "No se reconoció el campo %d al obtener el operando int.\n" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "No se reconoció el campo %d al obtener el operando vma.\n" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "No se reconoció el campo %d al establecer el operando int.\n" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "No se reconoció el campo %d al establecer el operando vma.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "falta un `]'" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "El número de registro de propósito especial está fuera de rango" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "El valor del operando A debe ser 0 o 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "el número de registro debe ser par" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "falta un `)'" + +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "No se entiende 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "no se puede lidiar con insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*desconocido*" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Se admiten las siguientes opciones de desensamblador específicas de i386/x86-64\n" +"con el interruptor -M (las opciones múltiples se deben separar con comas):\n" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Desensambla en modo 64bit\n" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Desensambla en modo 32bit\n" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Desensambla en modo 16bit\n" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Muestra las instrucciones con sintaxis AT&T\n" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Muestra las instrucciones con sintaxis Intel\n" + +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Muestra las instrucciones con mnemónicos AT&T\n" + +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Muestra las instrucciones con mnemónicos Intel\n" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Asume un tamaño de dirección de 64bit\n" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Asume un tamaño de dirección de 32bit\n" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Asume un tamaño de dirección de 16bit\n" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Asume un tamaño de datos de 32bit\n" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Asume un tamaño de datos de 16bit\n" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Siempre muestra el sufijo de instrucción con sintaxis AT&T\n" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Error: " + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: Campo de bits desconocido: %s\n" + +#: i386-gen.c:593 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Campo de bits desconocido: %s\n" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s: %d: Falta un `)' en el campo de bits: %s\n" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "no se puede encontrar i386-opc.tbl para lectura, errno =%s\n" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "no se puede encontrar i386-reg.tbl para lectura, errno = %s\n" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "no se puede crear i386-init.h, errno = %s\n" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "no se puede cambiar el directorio a \"%s\", errno = %s\n" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d bits sin usar en i386_cpu_flags.\n" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d bits sin usar en i386_operand_type.\n" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "no se puede crear i386-tbl.h, errno = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Aviso: " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "no se maneja la nota múltiple %s\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "no se puede encontrar ia64-ic.tbl para lectura\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "no se puede encontrar %s para lectura\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"el formato más reciente '%s'\n" +"parece más restrictivo que '%s'\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "campo traslapado %s->%s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "se sobreescribe la nota %d con la nota %d (IC:%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "no se sabe cómo especificar la dependencia %% %s\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "No se sabe cómo especificar la dependencia # %s\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] no tiene terminales o sub-clases\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s no tiene terminales o sub-clases\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "no hay insns mapeadas directamente al IC terminal %s [%s]" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "no hay insns mapeadas directamente al IC terminal %s\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "se define la clase %s pero no se utiliza\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Aviso: el rsrc %s (%s) no tiene chks\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Aviso: el rsrc %s (%s) no tiene chks o regs\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "el rsrc %s (%s) no tiene registros\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "la nota IC %d en el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "la nota IC %d para el código de operación %s (IC:%s) tiene conflictos con el recurso %s nota %d\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "el código de operación %s no tiene clase (ops %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "la palabra clave W es inválida en la ranura del operando FR." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "offset(IP) no es una forma válida" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "desplazamiento (DP) fuera de rango." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "desplazamiento (SP) fuera de rango." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "uso ilegal de paréntesis" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "operando fuera de rango (no está entre 1 y 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: índice de operador inválido." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Se requiere una dirección de byte. - debe ser par." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address devolvió un símbolo. Se requiere una literal." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "el operando operador-porcentaje no es un símbolo" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Se intentó encontrar un índice de bit de 0" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "el valor inmediato no puede ser un registro" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "el valor inmediato está fuera de rango" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "desplazamiento de 21-bit fuera de rango" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "se espera una dirección relativa a gp: gp(símbolo)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "se espera una dirección relativa a got: got(símbolo)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "se espera una dirección relativa a got: gotoffhi16(símbolo)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "se espera una dirección relativa a got: gotofflo16(símbolo)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "desconocido\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "desconocido\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "el inmediato imm:6 está fuera de rango" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() toma una dirección simbólica, no un número" + +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +msgid "dsp:8 immediate is out of range" +msgstr "el inmediato dsp:8 está fuera de rango" + +#: m32c-asm.c:184 m32c-asm.c:188 +msgid "Immediate is out of range -8 to 7" +msgstr "El inmediato está fuera del rango -8 a 7" + +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "El inmediato está fuera del rango -7 a 8" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() toma una dirección simbólica, no un número" + +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +msgid "dsp:16 immediate is out of range" +msgstr "el inmediato dsp:16 está fuera de rango" + +#: m32c-asm.c:399 +msgid "dsp:20 immediate is out of range" +msgstr "el inmediato dsp:20 está fuera de rango" + +#: m32c-asm.c:425 m32c-asm.c:445 +msgid "dsp:24 immediate is out of range" +msgstr "el inmediato dsp:24 está fuera de rango" + +#: m32c-asm.c:478 +msgid "immediate is out of range 1-2" +msgstr "el inmediato está fuera del rango 1-2" + +#: m32c-asm.c:496 +msgid "immediate is out of range 1-8" +msgstr "el inmediato está fuera del rango 1-8" + +#: m32c-asm.c:514 +msgid "immediate is out of range 0-7" +msgstr "el inmediato está fuera del rango 0-7" + +#: m32c-asm.c:550 +msgid "immediate is out of range 2-9" +msgstr "el inmediato está fuera del rango 2-9" + +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "El número de bit para el registro general de indización está fuera del rango 0-15" + +#: m32c-asm.c:606 m32c-asm.c:662 +msgid "bit,base is out of range" +msgstr "bit,base está fuera de rango" + +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +msgid "bit,base out of range for symbol" +msgstr "bit,base está fuera de rango para el símbolo" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "no es un par r0l/r0h válido" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "Especificador de tamaño inválido" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Sólo se permite $tp o $13 para este código de operación" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Sólo se permite $sp o $15 para este código de operación" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "%funcion() inválida aquí" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "El inmediato está fuera del rango -32768 a 32767" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "El inmediato está fuera del rango 0 a 65535" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "El inmediato está fuera del rango -512 a 511" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "El inmediato está fuera del rango -128 a 127" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "El valor no está suficientemente alineado" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# error interno, secuencia de extensión incompleta (+)" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# error interno, secuencia de extensión sin definir (+%c)" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# error interno, modificador (%c) sin definir" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# error interno del desensamblador, no se reconoce el modificador (%c)" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Las siguientes opciones de desensamblador específicas de MIPS se admiten\n" +"para usarse con el interruptor -M (las opciones múltiples se deben separar con comas):\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Muestra los nombres GPR de acuerdo a la ABI especificada.\n" +" Por defecto: basado en el binario a desensamblar.\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Muestra los nombres FPR de acuerdo a la ABI especificada.\n" +" Por defecto: numérico.\n" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Muestra los nombres de registro CP0 de acuerdo a\n" +" la arquitectura especificada.\n" +" Por defecto: basado en el binario a desensamblar.\n" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Muestra los nombres HWR de acuerdo a la arquitectura \n" +" especificada.\n" +" Por defecto: basado en el binario a desensamblar.\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Muestra los nombres GPR y FPR de acuerdo a\n" +" la ABI especificada.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Muestra el registro CP0 y los nombres HWR de acuerdo a\n" +" la arquitectura especificada.\n" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Para las opciones anteriores, se admiten los siguientes valores de \"ABI\":\n" +" " + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Para las opciones anteriores, se admiten los siguientes valores de \"ARCH\":\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case %d erróneo (%s) en %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interno: Código sin depurar (falta el caso de prueba): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(desconocido)" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipo de operandos desconocido: %d*" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "Instrucción de emulación as ilegal" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "Instrucción 2-op as ilegal" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Operando fuera de rango. Debe estar entre -32768 y 32767." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "¡Graaaan Problema en parse_imm16!" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "el operando de operador-porcentaje no es un símbolo" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "operando inválid. El tipo sólo puede tener valores 0,1,2." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "aviso: se descarta la opción -M%s desconocida\n" + +#: ppc-dis.c:523 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Las siguientes opciones de desensamblador específicas de PPC se admiten con\n" +"el interruptor -M:\n" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "opción condicional inválida" + +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "intento de establecer el bit y al usar el modificador + ó -" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "campo de máscara inválido" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "se descarta la máscara mfcr inválida" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "máscara de bits ilegal" + +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "registro índice en el rango de carga" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "los operandos de registros fuente y objetivo deben ser diferentes" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "operando de registro inválido al actualizar" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "número sprg inválido" + +#: ppc-opc.c:1451 +msgid "invalid constant" +msgstr "constante inválida" + +#: s390-dis.c:301 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Las siguientes opciones de desensamblador específicas de S/390 se admiten\n" +"para usarse con el interruptor -M (las opciones múltiples se deben\n" +"separar con comas):\n" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Desensambla en modo de arquitectura ESA\n" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Desensambla en modo de z/Architecture\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Error interno: sparc-opcode.h erróneo: \"%s\" == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "desconocida" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "operando de desplazamiento desconocido: %x\n" + +#: v850-dis.c:377 +#, c-format +msgid "unknown reg: %d\n" +msgstr "registro desconocido: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "el valor de desubicación no está en el rango y no está alineado" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "el valor de desubicación está fuera de rango" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "el valor de desubicación no está alineado" + +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "el valor inmediato está fuera de rango" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "el valor de ramificación está fuera de rango" + +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "ramificación a un desplazamiento impar" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "registro inválido para el ajuste de la pila" + +#: v850-opc.c:518 +msgid "invalid register name" +msgstr "nombre de registro inválido" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Falta el prefijo '#'" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Falta el prefijo '.'" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Falta el prefijo 'pof:'" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Falta el prefijo 'pag:'" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Falta el prefijo 'sof:'" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Falta el prefijo 'seg:'" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Registro erróneo en el preincremento" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Registro erróneo en el postincremento" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Nombre de registro erróneo" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "La etiqueta tiene conflictos con el nombre de registro" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "La etiqueta tiene conflictos con `Rx'" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Expresión inmediata errónea" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "No hay reubicaciones para inmediatos small" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "El operando small no era un número inmediato" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "El operando no es un símbolo" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Error sintáctico: No hay ')' al final" + +#~ msgid "branch value not in range and to an odd offset" +#~ msgstr "el valor de ramificación no está en rango e indica un desplazamiento impar" + +#~ msgid "immediate value not in range and not even" +#~ msgstr "el valor inmediato no está en rango y no es par" + +#~ msgid "immediate value must be even" +#~ msgstr "el valor inmediato debe ser par" + +#~ msgid "%operator operand is not a symbol" +#~ msgstr "el operando %operator no es un símbolo" + +#~ msgid "offset not a multiple of 16" +#~ msgstr "el desplazamiento no es un múltiplo de 16" + +#~ msgid "offset not a multiple of 2" +#~ msgstr "el desplazamiento no es un múltiplo de 2" + +#~ msgid "offset greater than 62" +#~ msgstr "el desplazamiento es mayor que 62" + +#~ msgid "offset not a multiple of 4" +#~ msgstr "el desplazamiento no es un múltiplo de 4" + +#~ msgid "offset greater than 124" +#~ msgstr "el desplazamiento es mayor que 124" + +#~ msgid "offset not a multiple of 8" +#~ msgstr "el desplazamiento no es un múltiplo de 8" + +#~ msgid "offset greater than 248" +#~ msgstr "el desplazamiento es mayor que 248" + +#~ msgid "offset not between -2048 and 2047" +#~ msgstr "el desplazamiento no está entre -2048 y 2047" + +#~ msgid "offset not between -8192 and 8191" +#~ msgstr "el desplazamiento no está entre -8192 y 8191" + +#~ msgid "ignoring least significant bits in branch offset" +#~ msgstr "ignorando los bits menos significativos en el desplazamiento de la rama" + +#~ msgid "value out of range" +#~ msgstr "valor fuera de rango" + +#~ msgid "target register operand must be even" +#~ msgstr "el operando de registro objetivo debe ser par" + +#~ msgid "source register operand must be even" +#~ msgstr "el operando de registro fuente debe ser par" + +#~ msgid "unknown\t0x%04x" +#~ msgstr "desconocido\t0x%04x" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "nombre clave/de registro no reconocido" diff --git a/external/gpl3/gdb/dist/opcodes/po/fi.gmo b/external/gpl3/gdb/dist/opcodes/po/fi.gmo new file mode 100644 index 0000000000000000000000000000000000000000..e7973141b475a051fb354267971ec5542759b30d GIT binary patch literal 26403 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zJEca>^sTMtr!wo!-4obc#>(<>H|i@jiM1K2n19`1@vO;t>cm8j+qwuAHy$DLBXdP% zVcKV2Pn!2EEwY}}F=(VN#W^9EA7|Dd6L@Y%X1!wi-5K|YI>t;th(hlzt)&J{USn?b z1!(5Vv4QDk&1lb#IX@d)$y^M{YgdE2QRkRx|rJSbIUbnnwqI;oc zE!<%~2B$5pa{wNB15lj1SVxj~3?Bnp?aK2hyme~0W@%4~{+ z^NN0$??BP(+r+FpryzeFp^Zs>GO%;a!TB)}9 zi-&p`iVdJQbb{1KrE$HZCMeuoVty};7f|nYUwiKuJlnJ%60OHAIozxAKl0%5knmJJ z3~@B*MWQ{D>7a8VY!-t@7;U>m0ag&6+GsAcj*CuHx&0{@zoC-MH=6sI1= z@4nL4;wbBk+xfKa#v@8E5nm{g^!dV0fF#VIU=^O*PRQ5wze=g@lN}B`bG|axtX3Cn c+{}q, 2006-2010. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:32+0100\n" +"PO-Revision-Date: 2010-11-09 16:40+0200\n" +"Last-Translator: Jorma Karvonen \n" +"Language-Team: Finnish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=2; plural=(n != 1);\n" +"X-Generator: KBabel 1.11.2\n" +"X-Poedit-Language: Finnish\n" +"X-Poedit-Country: FINLAND\n" +"X-Poedit-SourceCharset: utf-8\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "haaroitusoperandi ei ole tasarajalla" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "hyppyvihje ei ole tasarajalla" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Viimeisimmän käskyn virheellinen long-tyyppinen suora muistiosoiteviittaus!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "eriarvoiset vakiot eivät sovi käskyyn" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "apurekisteriä ei sallita tässä" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "yritettiin asettaa kirjoittamiselta suojattua rekisteriä" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "yritettiin lukea lukemiselta suojattua rekisteriä" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "virheellinen rekisterinimi â€%dâ€" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "liian monta pitkää vakiota" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "liian monta short-tyyppistä suoraa muistiosoitetta ladattavana" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "mahdotonta tallentaa" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "st-operandivirhe" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "osoitteen kirjoitus takaisin ei ole sallittu" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "tallennettavan arvon on oltava nolla" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "virheellinen lataus/short-tyyppinen suora muistiosoitekäsky" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "ld-käskyn operandin virhe" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "hyppyliput, mutta .f-määritettä ei ole" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "hyppyliput, mutta long-tyyppistä suoraa muistiosoitetta ei ole" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "long-tyyppisen suoran muistiosoituksen hyppyosoitteen lippubitit puuttuvat" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "yritettiin asettaa HR-bitit" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "virheellinen hyppylippujen arvo" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "haaroitusosoite ei ole 4-tavurajalla" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "on määriteltävä .jd tai nollattava suffiksi" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Tuntematon rekisterinimijoukko: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Tunnistamaton disassembler-valinta: %s\n" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Seuraavia ARM-kohtaisia disassembler-valintoja tuetaan käytössä\n" +"-M -valinnan kanssa:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "määrittelemätön" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Sisäinen disassembler-virhe" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "tuntematon rajoite â€%câ€" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operandi ei ole rajojen sisällä (%ld ei ole %ld:n ja %ld:n välillä)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operandi ei ole rajojen sisällä (%lu ei ole %lu:n ja %lu:n välillä)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "Tuntematon virhe %d\n" + +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Osoite 0x%s ei ole sallittujen rajojen sisällä.\n" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "Rekisterinumero ei ole oikea" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Rekisterin on oltava r0:n ja r7:n välillä" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Rekisterin on oltava r8:n ja r15:n välillä" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "Rekisteriluettelo ei ole oikea" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Tunnistamaton kenttä %d jäsentämisen aikana.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "syntaksimerkkijonosta puuttuu muistikas" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "tunnistamaton käsky" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaksivirhe (odotettiin merkkiä â€%câ€, löydettiin â€%câ€)" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaksivirhe (odotettiin merkkiä â€%câ€, löydettiin käskyn loppu)" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "roskaa rivin lopussa" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "käskyn muoto tunnistamaton" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "väärä käsky â€%.50s...â€" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "väärä käsky â€%.50sâ€" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*tuntematon*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Tunnistamaton kenttä %d käskyä tulostettaessa.\n" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operandi ei ole rajojen sisällä (%ld ei ole %ld:n ja %lu:n välillä)" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "operandi ei ole rajojen sisällä (0x%lx ei ole 0:n ja 0x%lx:n välillä)" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Tunnistamaton kenttä %d käskyä muodostettaessa.\n" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Tunnistamaton kenttä %d käskyä dekoodattaessa.\n" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Tunnistamaton kenttä %d kokonaislukuoperandia haettaessa.\n" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Tunnistamaton kenttä %d vma-operandia haettaessa.\n" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Tunnistamaton kenttä %d kokonaislukuoperandia asetettaessa.\n" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Tunnistamaton kenttä %d vma-operandia asetettaessa.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "â€]†puuttuu" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Erityiskäyttörekisterin numero ei ole rajojen sisällä" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "A-operandin arvon on oltava 0 tai 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "rekisterinumeron on oltava parillinen" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "â€)†puuttuu" + +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "0x%x ei ole ymmärrettävä \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kohteen %d sijoittamisesta ei selviydytty\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*tuntematon*" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Seuraavat i386/x86-64-kohtaiset disassembler-valinnat ovat tuettuja käyttöön\n" +"-M -valinnan kanssa (monivalinnat pitää erottaa pilkulla):\n" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Disassembloi 64-bittitilassa\n" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Disassembloi 32-bittitilassa\n" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Disassembloi 16-bittitilassa\n" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Näyttää käskyn AT&T-syntaksissa\n" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Näyttää käskyn Intel-syntaksissa\n" + +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Näyttää käskyn AT&T-syntaksissa\n" + +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Näyttää käskyn Intel-syntaksissa\n" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Otaksuu osoitekooksi 64 bittiä\n" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Otaksuu osoitekooksi 32 bittiä\n" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Otaksuu osoitekooksi 16 bittiä\n" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Otaksuu datakooksi 32 bittiä\n" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Otaksuu datakooksi 16 bittiä\n" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Näyttää käskysuffiksin aina AT&T-syntaksissa\n" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Virhe: " + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: Tuntematon bittikenttä: %s\n" + +#: i386-gen.c:593 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Tuntematon bittikenttä: %s\n" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s: %d: Puuttuva â€)†bittikentässä: %s\n" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "i386-opc.tbl ei löytynyt luettavaksi, virhenumero = %s\n" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "i386-reg.tbl ei löytynyt luettavaksi, virhenumero = %s\n" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "ei voi luoda tiedostoa i386-init.h, virhenumero = %s\n" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "vaihtaminen hakemistoon â€%s†ei onnistu, virhenumero = %s\n" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d käyttämätöntä bittiä i386_cpu_flags-lipussa.\n" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d käyttämätöntä bittiä i386_operand_type-lipussa.\n" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "ei voi luoda tiedostoa i386-tbl.h, virhenumero = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Varoitus: " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "monimerkkejä %s ei käsitelty\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "ia64-ic.tbl ei löytynyt luettavaksi\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "%s ei löytynyt luettavaksi\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"viimeisin muoto ’%s’\n" +"näyttää rajoittavammalta kuin ’%s’\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "päällekkäinen kenttä %s->%s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "merkki %d kirjoitetaan merkin %d päälle (IC:%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "kohteen %% riippuvuutta %s ei osattu määritellä\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Kohteen # riippuvuutta %s ei osattu määritellä\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "Kohteella IC:%s [%s] ei ole päätepisteitä tai alaluokkia\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "Kohteella IC:%s ei ole päätepisteitä tai alaluokkia\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "yhtään käskyä ei ole mapattu suoraan päätepisteeseen IC %s [%s]" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "yhtään käskyä ei ole mapattu suoraan päätepisteeseen IC %s\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "luokka %s on määritelty mutta käyttämätön\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Varoitus: kohteessa rsrc %s (%s) ei ole tarkistuksia\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Varoitus: kohteessa rsrc %s (%s) ei ole tarkistuksia tai rekistereitä\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "kohteessa rsrc %s (%s) ei ole rekistereitä\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC-merkintä %d käskyssä %s (IC:%s) on ristiriidassa resurssin %s merkinnän %d kanssa\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC-merkintä %d käskyyn %s (IC:%s) on ristiriidassa resurssin %s merkinnän %d kanssa\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "käskyssä %s ei ole luokkaa (toiminnat %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "avainsana W virheellinen FR-operandivälissä." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "siirrososoite(IP) ei ole virheetön muoto" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "(DP)-siirrososoite ei ole rajojen sisällä." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "(SP)-siirrososoite ei ole rajojen sisällä." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "sulkeiden virheellinen käyttö" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "operandi ei ole rajojen sisällä (ei 1:n ja 255:n välillä)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: virheellinen käskyindeksi" + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Vaaditaan tavuosoite - täytyy olla parillinen." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address palautti symbolin. Vaaditaan literaali." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "prosenttioperaattori-operandi ei ole symboli." + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Yritettiin löytää 0-bitti-indeksi" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "suoraan muistiosoitettu arvo ei voi olla rekisteri" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "suoraan muistiosoitettu arvo ei ole rajojen sisällä" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "21-bittinen siirrososoite ei ole rajojen sisällä" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "odotetaan gp-suhteellista osoitetta: gp(symboli)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "odotetaan got-suhteellista osoitetta: got(symboli)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "odotetaan got-suhteellista osoitetta: gotoffhi16(symboli)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "odotetaan got-suhteellinen osoite: gotofflo16(symboli)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "tuntematon\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "tuntematon\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "suora muistiosoitusarvo imm:6 ei ole rajojen sisällä" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() hyväksyy symbolisen osoitteen, ei numeroa" + +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +msgid "dsp:8 immediate is out of range" +msgstr "suora muistiosoitusarvo dsp:8 ei ole rajojen sisällä" + +#: m32c-asm.c:184 m32c-asm.c:188 +msgid "Immediate is out of range -8 to 7" +msgstr "Suora muistiosoitusarvo ei ole rajojen -8 ... 7 sisällä" + +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "Suora muistiosoitusarvo ei ole rajojen -7 ... 8 sisällä" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() hyväksyy symbolisen osoitteen, ei numeroa" + +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +msgid "dsp:16 immediate is out of range" +msgstr "suora muistiosoitusarvo dsp:16 ei ole rajojen sisällä" + +#: m32c-asm.c:399 +msgid "dsp:20 immediate is out of range" +msgstr "suora muistiosoitusarvo dsp:20 ei ole rajojen sisällä" + +#: m32c-asm.c:425 m32c-asm.c:445 +msgid "dsp:24 immediate is out of range" +msgstr "suora muistiosoitusarvo dsp:24 ei ole rajojen sisällä" + +#: m32c-asm.c:478 +msgid "immediate is out of range 1-2" +msgstr "suora muistiosoitusarvo ei ole rajojen 1-2 sisällä" + +#: m32c-asm.c:496 +msgid "immediate is out of range 1-8" +msgstr "suora muistiosoitusarvo ei ole rajojen 1-8 sisällä" + +#: m32c-asm.c:514 +msgid "immediate is out of range 0-7" +msgstr "suora muistiosoitusarvo ei ole rajojen 0-7 sisällä" + +#: m32c-asm.c:550 +msgid "immediate is out of range 2-9" +msgstr "suora muistiosoitusarvo ei ole rajojen 2-9 sisällä" + +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Indeksoivan yleisrekisterin bittinumero ei ole alueella 0-15" + +#: m32c-asm.c:606 m32c-asm.c:662 +msgid "bit,base is out of range" +msgstr "bitti, kanta ei ole rajojen sisällä" + +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +msgid "bit,base out of range for symbol" +msgstr "bitti, kanta ei ole symbolin rajojen sisällä" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "r0l/r0h-pari ei ole oikea" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "Virheellinen kokomäärite" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Vain $tp tai $13 sallittu tälle käskykoodille" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Vain $sp tai $15 sallittu tälle käskykoodille" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "virheellinen %function() tässä" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "Suora muistiosoitusarvo ei ole rajojen -32768 ... 32767 sisällä" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "Suora muistiosoitusarvo ei ole rajojen 0 ... 65535 sisällä" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "Suora muistiosoitusarvo ei ole rajojen -512 ... 511 sisällä" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "Suora muistiosoitusarvo ei ole rajojen -128 ... 127 sisällä" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "Uudelleensijoitusarvo ei ole tasarajalla" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# sisäinen virhe, epätäydellinen laajennussekvenssi (+)" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# sisäinen virhe, määrittelemätön laajennussekvenssi (+%c)" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# sisäinen virhe, määrittelemätön määrite (%c)" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# sisäinen disassembler-virhe, tunnistamaton määrite (%c)" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Seuraavat MIPS-kohtaiset disassembler-valinnat ovat tuettuja käyttöön\n" +"-M -valinnan kanssa (monivalinnat pitää erottaa pilkulla):\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Tulosta GPR-nimet määritellyn ABI:n mukaisesti.\n" +" Oletus: perustuu disassembloitavaan binääritiedostoon.\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Tulosta FPR-nimet määritellyn ABI:n mukaisesti.\n" +" Oletus: numeerinen.\n" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Tulosta CP0-rekisterinimet\n" +" määritellyn arkkitehtuurin mukaisesti.\n" +" Oletus: perustuu disassemloitavaan binääritiedostoon.\n" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Tulosta HWR-nimet määritellyn\n" +"\t\t\t arkkitehtuurin mukaisesti.\n" +" Oletus: perustuu disassembloitavaan binääritiedostoon.\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Tulosta GPR- ja FPR-nimet määritellyn\n" +" ABI:n mukaisesti.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Tulosta CP0-rekisteri ja HWR-nimet määritellyn\n" +" arkkitehtuurin mukaisesti.\n" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Ylläolevista valinnoista â€ABI†tukee seuraavia arvoja:\n" +" " + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Ylläolevista valinnoista â€ARCH†tukee seuraavia arvoja:\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "%d (%s) on virheellinen tapaus kohteessa %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Sisäinen: Vikajäljittämätön koodi (testitapaus puuttuu): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(tuntematon)" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tuntematon operandityyppi: %d*" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "Virheellinen emulointikäskynä" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "Virheellinen kaksikäskykoodina" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Operandi ei ole rajojen sisällä. Täytyy olla -32768:n ja 32767:n välillä." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "Iso pulma parse_imm16-käskyssä!" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "Prosenttioperaattori-operandi ei ole symboli" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "virheellinen operandi. tyypin arvo saa olla vain 0,1 tai 2." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "varoitus: ei välitetä tuntemattomasta -M%s-valitsimesta\n" + +#: ppc-dis.c:523 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Seuraavia PPC-kohtaisia disassembler-valintoja tuetaan käytössä\n" +"-M -valinnan kanssa:\n" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "virheellinen ehdollinen valinta" + +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "yritys asettaa y-bitti kun käytetään + tai - määritettä" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "virheellinen peitekenttä" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "virheellistä mfcr-peitettä ei oteta huomioon" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "virheellinen bittipeite" + +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "indeksirekisteri on latauslukurajojen sisällä" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "lähde- ja kohderekisterin kohdemuuttujien on oltava erilaiset" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "rekisterin operandi virheellinen päivitettäessä" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "virheellinen sprg-numero" + +#: ppc-opc.c:1451 +msgid "invalid constant" +msgstr "virheellinen vakio" + +#: s390-dis.c:301 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Seuraavat S/390-kohtaiset disassembler-valinnat ovat tuettuja käyttöön\n" +"-M -valinnan kanssa (monivalinnat pitää erottaa pilkulla):\n" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Disassembloi ESA-arkkitehtuuritilassa\n" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Disassembloi z/Arkkitehtuuritilassa\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Sisäinen virhe: virheellinen sparc-opcode.h: â€%sâ€, %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Sisäinen virhe: virheellinen sparc-opcode.h: â€%sâ€, %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Sisäinen virhe: virheellinen sparc-opcode.h: â€%s†== â€%sâ€\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "tuntematon" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "tuntematon operandin siirto: %x\n" + +#: v850-dis.c:377 +#, c-format +msgid "unknown reg: %d\n" +msgstr "tuntematon rekisteri: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "uudelleensijoitusarvo ei ole rajojen sisällä eikä sijaitse tasarajalla" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "uudelleensijoitusarvo ei ole rajojen sisällä" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "uudelleensijoitusarvo ei ole tasarajalla" + +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "suora muistiosoitusarvo ei ole rajojen sisällä" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "haaroitusarvo ei ole rajojen sisällä" + +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "haaroitusarvo ei ole rajojen sisällä ja kohdistuu parittomaan siirrososoitteeseen" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "haaroitus parittomaan siirrososoitteeseen" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "virheellinen rekisteri pinosäädössä" + +#: v850-opc.c:518 +msgid "invalid register name" +msgstr "virheellinen rekisterinimi" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Puuttuva ’#’ prefiksi" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Puuttuva ’.’ prefiksi" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Puuttuva ’pof:’ prefiksi" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Puuttuva ’pag:’ prefiksi" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Puuttuva ’sof:’ prefiksi" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Puuttuva ’seg:’ prefiksi" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Väärä rekisteri ennakkokasvatuksessa" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Väärä rekisteri jälkikasvatuksessa" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Väärä rekisterinimi" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Otsikko ristiriidassa rekisterin nimen kanssa" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Otsikko ristiriidassa kohteen â€Rx†kanssa" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Virheellinen suora muistiosoituslauseke" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Ei sijoitusta pienikokoiselle suoralle muistiosoitukselle" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Pieni operandi ei ollut suora muistiosoitusnumero" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "Kohdemuuttuja ei ole symboli" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaksivirhe: loppukaarisulku ’)’ puuttuu" + +#~ msgid "branch value not in range and to an odd offset" +#~ msgstr "haaroitusarvo ei ole rajojen sisällä ja sijaitsee parittomassa siirrososoitteessa" + +#~ msgid "immediate value not in range and not even" +#~ msgstr "suora muistiosoitusarvo ei ole rajojen sisällä eikä ole parillinen" + +#~ msgid "immediate value must be even" +#~ msgstr "suoran muistiosoitusarvon täytyy olla parillinen" + +#~ msgid "%operator operand is not a symbol" +#~ msgstr "%operaattori-operandi ei ole symboli." diff --git a/external/gpl3/gdb/dist/opcodes/po/fr.gmo b/external/gpl3/gdb/dist/opcodes/po/fr.gmo new file mode 100644 index 0000000000000000000000000000000000000000..8d6122358a40099abff80aedc7abe45e9a46a834 GIT binary patch literal 25313 zcmd6v3wR_~b?2`aCyr&~w+%J{mu1V6Y;}*Md1>UCu{96dV`e;qB#&bZwp-mLsb^YU z?XK<_$;8BFc|X^HNx}vKVM%ZtHW(AKYXc?;!~{$TkX>M7h=GJyh7a~z$g&Ax+28-( zTh-N4OQV@2yW8I!{ky8peVu#mx#ylbJ>NLzR%SpyOafa?1^PzK% z;nF+=?gbwPU#JJ?8S`;qFW3aT&Nt>h@E-6z;5iod()>bzsj6jLCyHftP`=1bJj008axS2cHdo8Dz-jn;w4xp33$47aK!Y&BdUuuL2pW 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z9aN^P5_;0jhiq5>$hsEpR|Ze{J+992tXQb|w_UnP)~hmSutV~0*ieWrlF8X2`L*3` zpX2OJ!9<>IJ?ON(X@NVRx{u!bm{Edh60E;(uayMLsCf0Fb2kQyiz*h-3E89vv5b}W zJPJjT4x1=UQdGA&F3I9x?ApYt-X-BKI@L0bZ4Wrcaq80l+=d3(HDS+SHX}Cep7Zdq G!~X~1SuDB$ literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/opcodes/po/fr.po b/external/gpl3/gdb/dist/opcodes/po/fr.po new file mode 100644 index 000000000000..2f5186b2ff09 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/fr.po @@ -0,0 +1,1295 @@ +# Messages français pour opcodes. +# Copyright (C) 2008 Free Software Foundation, Inc. +# This file is distributed under the same license as the binutils package. +# Michel Robitaille , traducteur depuis/since 1996. +# Nicolas Provost , 2009. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.20.90\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 11:32+0100\n" +"PO-Revision-Date: 2010-11-23 12:01+0100\n" +"Last-Translator: Nicolas Provost \n" +"Language-Team: French \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" +"Plural-Forms: nplurals=2; plural=(n > 1);\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "opérande de branchement non aligné" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "saut indicé non aligné" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Référence limm illégale dans la dernière instruction!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "impossible de méler différentes constantes dans l'instruction" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "registre auxiliaire non autorisé ici" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "tentative d'écriture sur un registre en lecture seule" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "tentative de lire un registre en écriture seule" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "numéro de registre non valide \"%d\"" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "trop de longues constantes" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "trop de bits shimm à charger" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "stockage impossible" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "Erreur d'opérande st" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "cache \"writeback\" d'adresses interdit" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "la valeur de stockage doit être 0" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "load/shimm non valide dans l'instruction" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "Erreur d'opérande ld" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "drapeaux de saut, mais pas de .f" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "drapeaux de saut, mais pas d'adresse limm" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "perte de drapeaux pour l'adresse de saut" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "tentative de modifier les bits HR" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "mauvais drapeaux de saut" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "adresse de branchement non multiple de 16" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "suffixe .jd ou validant attendu" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Nom de jeu de registres inconnu : %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Option du désassembleur non reconnue : %s\n" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Les options spécifiques ARM suivantes sont supportées avec l'utilisation de\n" +"l'option -M:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "non défini(e)" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Erreur interne du désassembleur" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "contrainte inconnue « %c »" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "opérande hors limites (%ld n'est pas entre %ld et %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "opérande hors limites (%lu n'est pas entre %lu et %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "Erreur inconnue %d\n" + +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Adresse 0x%s hors limites.\n" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "Numéro de registre non valide" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Le numéro de registre doit être entre r0 et r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Le numéro de registre doit être entre r8 et r15" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "Liste de registres non valide" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Champ non reconnu %d lors de l'analyse.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "mnémonique manquante dans la syntaxe de la chaîne" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "instruction non reconnue" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "erreur de syntaxe (caractère « %c » attendu, « %c » obtenu)" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "erreur de syntaxe (caractère « %c » attendu, fin de l'instruction trouvée)" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "rebut à la fin de la ligne" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "forme d'instruction non reconnue" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instruction erronée « %.50s... »" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instruction erronée « %.50s »" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*inconnu*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Champ non reconnu %d lors de l'affichage d'instructions.\n" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "opérande hors limites (%ld n'est pas entre %ld et %lu)" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "opérande hors limite (0x%lx n'est pas entre 0 et 0x%lx)" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Champ non reconnu %d lors de la construction d'instruction.\n" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Champ non reconnu %d lors du décodage d'instructions.\n" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Champ non reconnu %d lors de l'obtention d'un opérande int.\n" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Champ non reconnu %d lors de l'obtention d'un opérande vma.\n" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Champ non reconnu %d lors de l'initialisation d'un opérande int.\n" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Champ non reconnu %d lors de l'initialisation d'un opérande vma.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "\"]\"' manquant" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Numéro de registre spécial hors des limites" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "La valeur de l'opérande A doit être 0 ou 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "Le numéro de registre doit être pair" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "\")\" manquante" + +# h8300-dis.c:380Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hummmm 0x%x" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Incompréhensible : 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "Impossible de gérer l'insertion %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*inconnu*" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Les options spécifiques i386/x86-64 du désassembleur sont supportées avec l'utilisation\n" +"de l'option -M (les options multiples doivent être séparées par des virgules):\n" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Désassembler en mode 64 bits\n" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Désassembler en mode 32 bits\n" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Désassembler en mode 16 bits\n" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Afficher les instructions en syntaxe AT&T\n" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Afficher les instructions en syntaxe Intel\n" + +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Afficher les instructions mnémoniques AT&T\n" + +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Afficher les instructions mnémoniques Intel\n" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Taille des adresses : 64 bits\n" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Taille des adresses : 32 bits\n" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Taille des adresses : 16 bits\n" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Taille de données : 32 bits\n" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Taille de données : 16 bits\n" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Toujours afficher les suffixes d'instruction en syntaxe AT&T\n" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s : ERREUR : " + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: champ de bits inconnu : %s\n" + +#: i386-gen.c:593 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Champ de bits inconnu : %s\n" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s : %d : `)' manquante dans le champ de bits : %s\n" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "impossible de lire i386-opc.tbl, errno = %s\n" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "impossible de lire i386-reg.tbl, errno = %s\n" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "impossible de créer i386-init.h, errno = %s\n" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "incapable de changer de répertoire vers \"%s\", errno = %s\n" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d bits inutilisés dans i386_cpu_flags.\n" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d bits inutilisés dans i386_operand_type.\n" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "impossible de créer i386-tbl.h, errno = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s : AVERTISSEMENT : " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "note multiple %s non gérée\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "impossible de trouver ia64-ic.tbl pour la lecture\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "impossible de trouver %s pour la lecture\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"le plus récent format '%s'\n" +"apparaît plus restrictif que '%s'\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "chevauchement de champ %s->%s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "écrasement de la note %d par la note %d (IC :%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "Comment spécifier %% pour la dépendance %s ?\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Impossible de spécifier le n° de dépendance %s\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC :%s [%s] n'a pas de terminal ou de sous-classe\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC :%s n'a pas de terminal ou de sous-classe\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "aucun instruction mappée directement à l'UC %s [%s]" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "aucun instruction mappée directement à l'UC %s\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "classe %s définie mais non utilisée\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Attention : reg. source %s (%s) sans sélecteur \"chks\"\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Attention : reg. source %s (%s) sans sélecteur \"chks\" ou \"regs\"\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) n'a pas de registres\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "note IC %d dans l'opcode %s (IC : %s) entrant en conflit avec la ressource %s note %d\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "note IC %d pour l'opcode %s (IC : %s) entrant en conflit avec la ressource %s note %d\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "L'opcode %s n'a pas de classe (ops %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "mot clé W non valide dans le slot de l'opérande FR." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "décalage(IP) de format non valide" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "décalage (DP) est hors limites." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "décalage (SP) est hors limites." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "usage illégal des parenthèses" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "opérande hors limites (pas entre 1 et 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16 : opindex non valide." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Adresse d'octet requise - doit être paire." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address a retourné un symbole. Littéral requis." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "L'opérande de l'opérateur % n'est pas un symbole" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Tentative de repérage d'un index de bit de 0" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "La valeur immédiate ne doit pas être un registre" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "valeur immédiate hors limites" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "décalage de 21 bits hors limites" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "adresse relative GP attendue : gp(symbole)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "adresse relative GOT attendue : got(symbole)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "adresse relative GOT attendue : gotoffhi16(symbole)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "adresse relative GOT attendue : gotofflo16(symbole)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "inconnu\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "inconnu\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "valeur immédiate imm:6 hors limites" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() prend une adresse symbolique, pas un nombre" + +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +msgid "dsp:8 immediate is out of range" +msgstr "valeur immédiate dsp:8 hors limites" + +#: m32c-asm.c:184 m32c-asm.c:188 +msgid "Immediate is out of range -8 to 7" +msgstr "Valeur immédiate hors limistes (-8 à 7)" + +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "Valeur immédiate hors limites (-7 à 8)" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() prend une adresse symbolique, pas un nombre" + +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +msgid "dsp:16 immediate is out of range" +msgstr "valeur immédiate dsp:16 hors limites" + +#: m32c-asm.c:399 +msgid "dsp:20 immediate is out of range" +msgstr "valeur immédiate dsp:20 hors limites" + +#: m32c-asm.c:425 m32c-asm.c:445 +msgid "dsp:24 immediate is out of range" +msgstr "valeur immédiate dsp:24 hors limites" + +#: m32c-asm.c:478 +msgid "immediate is out of range 1-2" +msgstr "valeur immédiate hors limites 1-2" + +#: m32c-asm.c:496 +msgid "immediate is out of range 1-8" +msgstr "valeur immédiate hors limites 1-8" + +#: m32c-asm.c:514 +msgid "immediate is out of range 0-7" +msgstr "valeur immédiate hors limites 0-7" + +#: m32c-asm.c:550 +msgid "immediate is out of range 2-9" +msgstr "valeur immédiate hors limites 2-9" + +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Bits pour indexer les registres généraux hors limites (0-15)" + +#: m32c-asm.c:606 m32c-asm.c:662 +msgid "bit,base is out of range" +msgstr "bit,base hors des limites" + +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +msgid "bit,base out of range for symbol" +msgstr "bit,base hors des limites pour un symbole" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "couple r0l/r0h non valide" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "Spécifieur de taille non valide" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Seuls $tp ou $13 sont autorisés avec cet opcode" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Seuls $sp ou $15 sont autorisés avec cet opcode" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "%function() non valide ici" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "Valeur immédiate hors limites (-32768 à 32767)" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "Valeur immédiate hors limites (0 à 65535)" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "Valeur immédiate hors limites (-512 à 511)" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "Valeur immédiate hors limites (-128 à 127)" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "Valeur mal alignée" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# erreur interne, séquence d'extension incomplète (+)" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# erreur interne, séquence d'extension indéfinie (+%c)" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# erreur interne, modificateur non défini (%c)" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# erreur interne du désassembleur, modificateur non reconnu (%c)" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Les options spécifiques MIPS du désassembleur sont supportées avec l'utilisation de\n" +"l'option -M (les options multiples doivent être séparées par des virgules):\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Afficher les noms GPR selon l'ABI spécifié.\n" +" Par défaut : basé sur le binaire désassemblé.\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Afficher les noms FPR selon l'ABI spécifié.\n" +" Par défaut : numérique.\n" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Afficher les noms des registres CP0 selon\n" +" l'architecture spécifiée.\n" +" Par défaut : basé sur le binaire désassemblé.\n" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Afficher les noms HWR selon \n" +"\t\t\t l'architecture spécifiée.\n" +" Par défaut : basé sur le binaire désassemblé.\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Afficher les noms GPR et FPR selon l'ABI\n" +" spécifié.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Afficher les noms des registres CP0 et HWR selon\n" +" l'architecture spécifiée.\n" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Pour les options ci-dessus, les valeurs suivantes sont supportées pour l'\"ABI\":\n" +" " + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Pour les options ci-dessus, les valeurs suivantes sont supportées pour \"ARCH\":\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Cas erroné %d (%s) dans %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interne : code non débogué (test manquant) : %s : %d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(inconnu)" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*type d'opérande inconnu : %d*" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "Non valable comme instr. d'émulation" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "Non valable comme instr. 2-op" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Opérande hors limite. Doit être entre -32768 et 32767." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "GROS problème dans parse_imm16 !" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "L'opérande de l'opérateur % n'est pas un symbole" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "opérande non valide. type doit valoir 0,1 ou 2 seulement." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "avertissement : option -M%s inconnue ignorée\n" + +#: ppc-dis.c:523 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Les options spécifiques PPC suivantes sont supportées avec l'utilisation de\n" +"l'option -M :\n" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "option conditionnelle non valide" + +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "tentative d'initialisation du bit y lors de l'utilisation du modificateur + ou -" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "masque non valide" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "masque mfcr non valide et ignoré" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "masque de bits illégal" + +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "Le registre index n'est pas dans la plage de chargement" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "les opérandes des registres source et cible doivent être différents" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "opérande registre invalide lors de la mise à jour" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "n° de registre spécial non valide" + +#: ppc-opc.c:1451 +msgid "invalid constant" +msgstr "constante non valide" + +#: s390-dis.c:301 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Les options spécifiques S/390 du désassembleur sont supportées avec l'utilisation de\n" +"l'option -M (les options multiples doivent être séparées par des virgules):\n" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Désassemble en mode architecture ESA\n" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Désassemble en mode z/Architecture\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erreur interne : sparc-opcode.h erroné : « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erreur interne : sparc-opcode.h erroné : « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Erreur interne : sparc-opcode.h erroné : « %s » == « %s »\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "inconnu" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "décalage d'opérande inconnu : %x\n" + +#: v850-dis.c:377 +#, c-format +msgid "unknown reg: %d\n" +msgstr "registre inconnu : %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "La valeur de déplacement hors limite et non alignée" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "valeur de déplacement hors limite" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "valeur de déplacement non alignée" + +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "valeur immédiate hors limite" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "valeur de branchement hors limite" + +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "valeur de branchement hors limite et avec un décalage impair" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "branchement avec un décalage impair" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "registre non valide pour l'ajustement de la pile" + +#: v850-opc.c:518 +msgid "invalid register name" +msgstr "nom de registre non valide" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Préfixe manquant \"#\"" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Préfixe manquant \".\"" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Préfixe \"pof:\" manquant" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Préfixe \"pag:\" manquant" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Préfixe \"sof:\" manquant" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Préfixe \"seg:\" manquant" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Registre erroné dans un préincrément" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Registre erroné dans un postincrément" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Nom erroné de registre" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Conflits d'étiquette avec le nom de registre" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Conflit d'étiquette avec « Rx »" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Expression immédiate erronée" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Aucune relocalisation pour une petite valeur immédiate" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Le petit opérande n'était pas un nombre immédiat" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "L'opérande n'est pas un symbol" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Erreur de syntaxe : pas de ')' en suffixe" + +#~ msgid "branch value not in range and to an odd offset" +#~ msgstr "valeur de branchement hors limite et avec un décalage impair" + +#~ msgid "immediate value not in range and not even" +#~ msgstr "La valeur immédiate est hors limite et non paire" + +#~ msgid "immediate value must be even" +#~ msgstr "La valeur immédiate doit être paire" + +#~ msgid "unknown\t0x%04x" +#~ msgstr "inconnu\t0x%04x" + +#~ msgid "offset not a multiple of 16" +#~ msgstr "décalage n'est pas un multiple de 16" + +#~ msgid "offset not a multiple of 2" +#~ msgstr "décalage n'est pas un multiple de 2" + +#~ msgid "offset greater than 62" +#~ msgstr "décalage plus grand que 62" + +#~ msgid "offset not a multiple of 4" +#~ msgstr "décalage n'est pas un multiple de 4" + +#~ msgid "offset greater than 124" +#~ msgstr "décalage plus grand que 124" + +#~ msgid "offset not a multiple of 8" +#~ msgstr "décalage n'est pas un multiple de 8" + +#~ msgid "offset greater than 248" +#~ msgstr "décalage plus grand que 248" + +#~ msgid "offset not between -2048 and 2047" +#~ msgstr "décalage n'est pas entre -2048 et 2047" + +#~ msgid "offset not between -8192 and 8191" +#~ msgstr "décalage n'est pas entre -8192 et 8191" + +#~ msgid "ignoring least significant bits in branch offset" +#~ msgstr "Les derniers bits les moins significatifs sont ignorés dans le décalage de branchement" + +#~ msgid "value out of range" +#~ msgstr "valeur hors limite" + +#~ msgid "target register operand must be even" +#~ msgstr "opérande du registre cible doit être pair" + +#~ msgid "source register operand must be even" +#~ msgstr "opérande du registre source doit être pair" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "nom de mot clé ou de registre non reconnu" diff --git a/external/gpl3/gdb/dist/opcodes/po/ga.gmo b/external/gpl3/gdb/dist/opcodes/po/ga.gmo new file mode 100644 index 0000000000000000000000000000000000000000..fef67102cebd653e592a6b9ff27fe337e27b41bb GIT binary patch literal 24028 zcmd6v3zQsJdFQWz7&I7Tj4>EvC|e$nBu}?yMz7Hz3ymH|VafSyn!r>VRI&%oUC#fvaGVZ=V-(3 z{=WODuI}j`NrpX}KDzU-$9;bHd)==-`#)X&tY1|8zDs!-5G&)3Vs@V6F7FIQm+S3fo}&d zda+XP0N)9|7kv3klv)FR+~RjE{=`*EP4c`9?gWp3qu_5^d;;9S{Xc-xe)UTY?gOW| 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bug-binutils@gnu.org\n" +"POT-Creation-Date: 2008-09-09 15:56+0930\n" +"PO-Revision-Date: 2008-12-10 18:42-0500\n" +"Last-Translator: Kevin Scannell \n" +"Language-Team: Irish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "oibreann brainse gan ailíniú" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "leid léime gan ailíniú" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Tagairt neamhcheadaithe limm sa treoir is déanaí!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "ní féidir tairisigh le luachanna difriúla a chur isteach sa treoir" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "ní cheadaítear tabhall cúntach anseo" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "rinneadh iarracht ar thabhall inléite amháin a shocrú" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "rinneadh iarracht ar thabhall inscríofa amháin a léamh" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "uimhir neamhbhailí `%d' ar thabhall" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "an iomarca tairiseach fada" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "an iomarca shimmeanna le linn luchtaithe" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "stóráil dhodhéanta" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "earráid le hoibreann st" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "ní cheadaítear ais-scríobh an tseolta" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "caithfidh luach an stóir a bheith nialas" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "insn luchtaithe/shimm neamhbhailí" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "earráid le hoibreann ld" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "bratacha léime, ach ní fhacthas .f ar bith" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "bratacha léime, ach gan seoladh limm" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "cailleadh giotáin bhrataí den seoladh léime limm" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "rinneadh iarracht giotáin HR a shocrú" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "luach neamhbhailí ar bhratacha léime" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "seoladh brainse gan a bheith ar theorainn 4 bheart" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "ní mór duit .jd nó iarmhír gan neamhniú a shonrú" + +#: arm-dis.c:1808 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:3818 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Tacar anaithnid d'ainmneacha taibhle: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:3826 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Rogha anaithnid dídhíolamóra: %s\n" + +#: arm-dis.c:4238 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Tacaítear leis na roghanna seo a leanas, atá sainiúil do ARM agus le húsáid in éineacht\n" +"leis an rogha -M:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "gan sainmhíniú" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Earráid inmheánach dídhíolamóra" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "iallach anaithnid `%c'" + +#: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200 +#: iq2000-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 mep-ibld.c:200 +#: mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 xstormy16-ibld.c:200 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "oibreann as raon (níl %ld idir %ld agus %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "oibreann as raon (níl %lu idir %lu agus %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:59 +#, c-format +msgid "Unknown error %d\n" +msgstr "Earráid anaithnid %d\n" + +#: dis-buf.c:68 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Tá an seoladh 0x%s thar teorainn.\n" + +#: fr30-asm.c:93 m32c-asm.c:877 m32c-asm.c:884 +msgid "Register number is not valid" +msgstr "uimhir neamhbhailí ar an tabhall" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Caithfidh an tabhall a bheith idir r0 agus r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Caithfidh an tabhall a bheith idir r8 agus r15" + +#: fr30-asm.c:116 m32c-asm.c:915 +msgid "Register list is not valid" +msgstr "Níl liosta na dtaibhle bailí" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1001 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Réimse anaithnid %d le linn parsála.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1052 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "neamónach ar iarraidh i dteaghrán comhréire" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:736 iq2000-asm.c:837 m32c-asm.c:1775 m32c-asm.c:1779 +#: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1187 mep-asm.c:1191 mep-asm.c:1278 +#: mep-asm.c:1379 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553 +#: xstormy16-asm.c:654 +msgid "unrecognized instruction" +msgstr "treoir anaithnid" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1234 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "earráid chomhréire (bhíothas ag súil le `%c', fuarthas `%c')" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1244 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "earráid chomhréire (bhíothas ag súil le `%c', fuarthas deireadh na treorach)" + +#: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730 +#: m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1272 mt-asm.c:866 +#: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547 +msgid "junk at end of line" +msgstr "bruscar ag deireadh na líne" + +#: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836 +#: m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1378 mt-asm.c:972 +#: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653 +msgid "unrecognized form of instruction" +msgstr "foirm anaithnid de threoir" + +#: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848 +#: m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1390 mt-asm.c:984 +#: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "drochthreoir `%.50s...'" + +#: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851 +#: m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1393 mt-asm.c:987 +#: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "drochthreoir `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41 +#: m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 openrisc-dis.c:41 +#: xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*anaithnid*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:891 +#: m32r-dis.c:256 mep-dis.c:776 mt-dis.c:290 openrisc-dis.c:135 +#: xc16x-dis.c:375 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Réimse anaithnid %d le linn priontála insn.\n" + +#: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163 +#: m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 mt-ibld.c:163 +#: openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "oibreann as raon (níl %ld idir %ld agus %lu)" + +#: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184 +#: m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 mt-ibld.c:184 +#: openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "oibreann as raon (níl 0x%lx idir 0 agus 0x%lx)" + +#: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709 +#: m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1024 mt-ibld.c:745 +#: openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Réimse anaithnid %d le linn tógála insn.\n" + +#: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884 +#: m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1444 mt-ibld.c:965 +#: openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Réimse anaithnid %d le linn díchódaithe insn.\n" + +#: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015 +#: m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:1737 mt-ibld.c:1165 +#: openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Réimse anaithnid %d agus oibreann slánuimhriúil á fháil.\n" + +#: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128 +#: m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2012 mt-ibld.c:1347 +#: openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Réimse anaithnid %d agus oibreann vma á fháil.\n" + +#: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248 +#: m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:2271 mt-ibld.c:1536 +#: openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Réimse anaithnid %d agus oibreann slánuimhriúil á shocrú.\n" + +#: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358 +#: m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:2520 mt-ibld.c:1715 +#: openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Réimse anaithnid %d agus oibreann vma á shocrú.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "`]' ar iarraidh" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Uimhir thabhall sainchuspóirigh as raon" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "caithfidh luach an oibrinn A a bheith 0 nó 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "caithfidh uimhir an tabhaill a bheith cothrom" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 m32c-asm.c:141 m32c-asm.c:237 m32c-asm.c:279 +#: m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:232 mep-asm.c:250 +#: mep-asm.c:265 mep-asm.c:280 mep-asm.c:292 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "`)' ar iarraidh" + +#: h8300-dis.c:327 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:708 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Ní thuigim 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "ní féidir déileáil le hionsá %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*anaithnid*" + +#: i386-dis.c:9545 +msgid "" +msgstr "" + +#: i386-dis.c:9776 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Tacaítear leis na roghanna dídhíolamóra seo a leanas, atá sainiúil do\n" +"i386/x86-64 agus le húsáid in éineacht leis an rogha -M (ba chóir roghanna\n" +"iomadúla a bheith scartha le camóga):\n" + +#: i386-dis.c:9780 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Dídhíolaim sa mhód 64-giotán\n" + +#: i386-dis.c:9781 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Dídhíolaim sa mhód 32-giotán\n" + +#: i386-dis.c:9782 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Dídhíolaim sa mhód 16-giotán\n" + +#: i386-dis.c:9783 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Taispeáin treoir de réir comhréire AT&T\n" + +#: i386-dis.c:9784 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Taispeáin treoir de réir comhréire Intel\n" + +#: i386-dis.c:9785 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Taispeáin treoir de réir neamónach AT&T\n" + +#: i386-dis.c:9787 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Taispeáin treoir de réir neamónach Intel\n" + +#: i386-dis.c:9789 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Glac le seoltaí 64-giotán\n" + +#: i386-dis.c:9790 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Glac le seoltaí 32-giotán\n" + +#: i386-dis.c:9791 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Glac le seoltaí 16-giotán\n" + +#: i386-dis.c:9792 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Glac le sonraí 32-giotán\n" + +#: i386-dis.c:9793 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Glac le sonraí 16-giotán\n" + +#: i386-dis.c:9794 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Taispeáin iarmhír threorach i gcomhréir AT&T i gcónaí\n" + +#: i386-gen.c:411 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Earráid: " + +#: i386-gen.c:510 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: Réimse anaithnid giotán: %s\n" + +#: i386-gen.c:674 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "ní féidir i386-opc.tbl a aimsiú chun é a léamh, errno = %s\n" + +#: i386-gen.c:851 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "ní féidir i386-reg.tbl a aimsiú chun é a léamh, errno = %s\n" + +#: i386-gen.c:943 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "ní féidir i386-init.h a chruthú, errno = %s\n" + +#: i386-gen.c:1032 ia64-gen.c:2850 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "ní féidir an chomhadlann reatha a athrú go \"%s\", errno = %s\n" + +#: i386-gen.c:1039 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d giotán neamhúsáidte i i386_cpu_flags.\n" + +#: i386-gen.c:1046 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d giotán neamhúsáidte i i386_operand_type.\n" + +#: i386-gen.c:1060 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "ní féidir i386-tbl.h a chruthú, errno = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Rabhadh: " + +#: ia64-gen.c:506 ia64-gen.c:740 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "ilnóta %s gan láimhseáil\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "ní féidir ia64-ic.tbl a oscailt chun é a léamh\n" + +#: ia64-gen.c:822 +#, c-format +msgid "can't find %s for reading\n" +msgstr "ní féidir %s a oscailt chun é a léamh\n" + +#: ia64-gen.c:1046 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"is cosúil go bhfuil an fhormáid is\n" +"déanaí '%s' níos sriantaí ná '%s'\n" + +#: ia64-gen.c:1057 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "réimse forluite %s->%s\n" + +#: ia64-gen.c:1254 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "nóta %d á fhorscríobh le nóta %d (IC:%s)\n" + +#: ia64-gen.c:1459 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "níl a fhios agam conas a shonraítear spleáchas %% %s\n" + +#: ia64-gen.c:1481 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Níl a fhios agam conas a shonraítear spleáchas # %s\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "níl teirminéil ná fo-aicmí ag IC:%s [%s]\n" + +#: ia64-gen.c:1523 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "níl teirminéil ná fo-aicmí ag IC:%s\n" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "níl aon insn mapáilte go díreach go IC teirminéalach %s [%s]" + +#: ia64-gen.c:1535 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "níl aon insn mapáilte go díreach go IC teirminéalach %s\n" + +#: ia64-gen.c:1546 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "sainmhíníodh an aicme %s, ach níor baineadh úsáid as\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Rabhadh: níl aon tástálacha ag rsrc %s (%s)\n" + +#: ia64-gen.c:1562 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Rabhadh: níl aon tástálacha ná clárúcháin ag rsrc %s (%s)\n" + +#: ia64-gen.c:1566 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "níl aon tabhall ag acmhainn %s (%s)\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nóta IC %d sa chód oibríochta %s (IC:%s) i gcoinbhleacht le hacmhainn %s nóta %d\n" + +#: ia64-gen.c:2506 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nóta IC %d le haghaidh cóid oibríochta %s (IC:%s) i gcoinbhleacht le hacmhainn %s nóta %d\n" + +#: ia64-gen.c:2520 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "níl aicme ar bith ag cód oibríochta %s (oibrinn %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "is neamhbhailí é lorgfhocal W i sliotán oibrinn FR." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "is neamhbhailí é an fhoirm fritháireamh(IP)" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "fritháireamh (DP) as raon." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "fritháireamh (SP) as raon." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "úsáid neamhcheadaithe de lúibíní" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "oibreann as raon (nach bhfuil idir 1 agus 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: innéacs neamhbhailí oibrinn." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Seoladh birt de dhíth. - ní mór dó a bheith cothrom." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "d'fhill cgen_parse_address siombail. Tá gá le teaghrán litriúil." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "níl an t-oibreann céatadáin ina shiombail" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Rinneadh iarracht innéacs giotáin 0 a aimsiú" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "ní féidir an luach láithreach a bheith tabhall" + +#: iq2000-asm.c:123 iq2000-asm.c:153 +msgid "immediate value out of range" +msgstr "luach láithreach as raon" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "fritháireamh 21-giotán as raon" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "anaithnid\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "anaithnid\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "luach láithreach imm:6 as raon" + +#: m32c-asm.c:147 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "glacann %dsp8() le seoladh siombalach, ní ghlacann sé le huimhir" + +#: m32c-asm.c:160 m32c-asm.c:164 m32c-asm.c:255 +msgid "dsp:8 immediate is out of range" +msgstr "luach láithreach dsp:8 as raon" + +#: m32c-asm.c:185 m32c-asm.c:189 +msgid "Immediate is out of range -8 to 7" +msgstr "Luach láithreach as raon -8 go dtí 7" + +#: m32c-asm.c:210 m32c-asm.c:214 +msgid "Immediate is out of range -7 to 8" +msgstr "Luach láithreach as raon -7 go dtí 8" + +#: m32c-asm.c:285 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "glacann %dsp16() le seoladh siombalach, ní ghlacann sé le huimhir" + +#: m32c-asm.c:308 m32c-asm.c:315 m32c-asm.c:378 +msgid "dsp:16 immediate is out of range" +msgstr "luach láithreach dsp:16 as raon" + +#: m32c-asm.c:404 +msgid "dsp:20 immediate is out of range" +msgstr "luach láithreach dsp:20 as raon" + +#: m32c-asm.c:430 m32c-asm.c:450 +msgid "dsp:24 immediate is out of range" +msgstr "luach láithreach dsp:24 as raon" + +#: m32c-asm.c:483 +msgid "immediate is out of range 1-2" +msgstr "luach láithreach as raon 1-2" + +#: m32c-asm.c:501 +msgid "immediate is out of range 1-8" +msgstr "luach láithreach as raon 1-8" + +#: m32c-asm.c:519 +msgid "immediate is out of range 0-7" +msgstr "luach láithreach as raon 0-7" + +#: m32c-asm.c:555 +msgid "immediate is out of range 2-9" +msgstr "luach láithreach as raon 2-9" + +#: m32c-asm.c:573 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Uimhir ghiotáin le haghaidh innéacsú tabhall ginearálta as raon 0-15" + +#: m32c-asm.c:611 m32c-asm.c:667 +msgid "bit,base is out of range" +msgstr "giotán,bunuimhir as raon" + +#: m32c-asm.c:618 m32c-asm.c:623 m32c-asm.c:671 +msgid "bit,base out of range for symbol" +msgstr "giotán,bunuimhir as raon le haghaidh na siombaile" + +#: m32c-asm.c:807 +msgid "not a valid r0l/r0h pair" +msgstr "cúpla neamhbhailí r0l/r0h" + +#: m32c-asm.c:837 +msgid "Invalid size specifier" +msgstr "Sonraitheoir neamhbhailí méide" + +#: m68k-dis.c:1163 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1320 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:114 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Ní cheadaítear ach $tp nó $13 leis an gcód oibríochta seo" + +#: mep-asm.c:128 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Ní cheadaítear ach $sp nó $15 leis an gcód oibríochta seo" + +#: mep-asm.c:299 mep-asm.c:455 +#, c-format +msgid "invalid %function() here" +msgstr "%function() neamhbhailí anseo" + +#: mips-dis.c:781 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# earráid inmheánach, seicheamh neamhiomlán sínte (+)" + +#: mips-dis.c:915 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# earráid inmheánach, seicheamh sínte gan sainmhíniú (+%c)" + +#: mips-dis.c:1274 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# earráid inmheánach, mionathraitheoir gan sainmhíniú (%c)" + +#: mips-dis.c:1881 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# earráid inmheánach dídhíolamóra, mionathraitheoir anaithnid (%c)" + +#: mips-dis.c:2112 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Tacaítear leis na roghanna dídhíolamóra seo a leanas, atá sainiúil do MIPS\n" +"agus le húsáid in éineacht leis an rogha -M (ba chóir roghanna iomadúla\n" +"a bheith scartha le camóga):\n" + +#: mips-dis.c:2116 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Taispeáin ainmneacha GPR de réir an ABI sonraithe.\n" +" Réamhshocrú: bunaithe ar chlár dénártha dídhíolaimithe.\n" + +#: mips-dis.c:2120 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Taispeáin ainmneacha FPR de réir an ABI sonraithe.\n" +" Réamhshocrú: uimhriúil.\n" + +#: mips-dis.c:2124 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=AILTIREACHT Taispeáin ainmneacha na dtaibhle CP0 de réir na\n" +" hailtireachta sonraithe.\n" +" Réamhshocrú: bunaithe ar chlár dénártha dídhíolaimithe.\n" + +#: mips-dis.c:2129 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=AILTIREACHT Taispeáin ainmneacha HWR de réir na\n" +" hailtireachta sonraithe.\n" +" Réamhshocrú: bunaithe ar chlár dénártha dídhíolaimithe.\n" + +#: mips-dis.c:2134 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Taispeáin ainmneacha GPR agus FPR de réir an\n" +" ABI sonraithe.\n" + +#: mips-dis.c:2138 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=AILTIREACHT Taispeáin ainmneacha HWR agus ainmneacha na dtaibhle\n" +" CP0 de réir na hailtireachta sonraithe.\n" + +#: mips-dis.c:2142 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Le haghaidh na roghanna thuas, tacaítear leis na luachanna seo a leanas ar \"ABI\":\n" +" " + +#: mips-dis.c:2147 mips-dis.c:2155 mips-dis.c:2157 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2149 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Le haghaidh na roghanna thuas, tacaítear leis na luachanna seo a leanas ar \"ARCH\":\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Droch-chás %d (%s) i %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Inmheánach: cód gan dífhabhtú (cás tástála ar iarraidh): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(anaithnid)" + +#: mmix-dis.c:513 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*cineál anaithnid oibrinn: %d*" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Oibreann as raon. Caithfidh sé a bheith idir -32768 agus 32767." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "Trioblóid An-An-Mhór i parse_imm16!" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "ní siombail é oibreann an oibreora céatadáin" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "oibreann neamhbhailí. ní cheadaítear ach na luachanna 0,1,2." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:534 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-opc.c:862 ppc-opc.c:890 +msgid "invalid conditional option" +msgstr "rogha neamhbhailí choinníollach" + +#: ppc-opc.c:892 +msgid "attempt to set y bit when using + or - modifier" +msgstr "rinneadh iarracht y-giotán a shocrú agus mionathraitheoir + nó - in úsáid" + +#: ppc-opc.c:924 +msgid "invalid mask field" +msgstr "réimse neamhbhailí maisc" + +#: ppc-opc.c:950 +msgid "ignoring invalid mfcr mask" +msgstr "ag déanamh neamhshuim ar mhasc neamhbhailí mfcr" + +#: ppc-opc.c:1000 ppc-opc.c:1035 +msgid "illegal bitmask" +msgstr "giotánmhasc neamhcheadaithe" + +#: ppc-opc.c:1155 +msgid "index register in load range" +msgstr "tabhall innéacs i raon luchtaithe" + +#: ppc-opc.c:1171 +msgid "source and target register operands must be different" +msgstr "caithfidh oibreann an tabhaill fhoinsigh agus oibreann an spriocthabhaill a bheith difriúil" + +#: ppc-opc.c:1186 +msgid "invalid register operand when updating" +msgstr "oibreann neamhbhailí tabhaill le linn nuashonraithe" + +#: ppc-opc.c:1265 +msgid "invalid sprg number" +msgstr "uimhir neamhbhailí sprg" + +#: s390-dis.c:276 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Tacaítear leis na roghanna dídhíolamóra seo a leanas, atá sainiúil do S/390\n" +"agus le húsáid in éineacht leis an rogha -M (ba chóir roghanna a scaradh\n" +"le camóga):\n" + +#: s390-dis.c:280 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Dídhíolaim i mód ailtireachta ESA\n" + +#: s390-dis.c:281 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Dídhíolaim sa mhód z-Ailtireachta\n" + +#: score-dis.c:220 score-dis.c:383 +msgid "" +msgstr "" + +#: sparc-dis.c:282 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Earráid inmheánach: sparc-opcode.h go holc: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:293 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Earráid inmheánach: sparc-opcode.h go holc: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:343 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Earráid inmheánach: sparc-opcode.h go holc: \"%s\" == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1013 +msgid "unknown" +msgstr "anaithnid" + +#: v850-dis.c:239 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "iomlaoid anaithnid oibrinn: %x\n" + +#: v850-dis.c:253 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "tabhall anaithnid plobtha: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:48 +msgid "displacement value is not in range and is not aligned" +msgstr "tá an luach díláithrithe as raon, agus ní ailínithe é" + +#: v850-opc.c:49 +msgid "displacement value is out of range" +msgstr "luach díláithrithe as raon" + +#: v850-opc.c:50 +msgid "displacement value is not aligned" +msgstr "luach díláithrithe gan ailíniú" + +#: v850-opc.c:52 +msgid "immediate value is out of range" +msgstr "luach láithreach as raon" + +#: v850-opc.c:60 +msgid "branch value not in range and to odd offset" +msgstr "luach brainse as raon, agus brainse go dtí fritháireamh corr" + +#: v850-opc.c:62 v850-opc.c:89 +msgid "branch value out of range" +msgstr "luach an bhrainse as raon" + +#: v850-opc.c:65 v850-opc.c:92 +msgid "branch to odd offset" +msgstr "brainse go dtí fritháireamh corr" + +#: v850-opc.c:87 +msgid "branch value not in range and to an odd offset" +msgstr "luach brainse as raon agus brainse go dtí fritháireamh corr" + +#: v850-opc.c:279 +msgid "invalid register for stack adjustment" +msgstr "tabhall neamhbhailí le haghaidh coigeartaithe na cruaiche" + +#: v850-opc.c:299 +msgid "immediate value not in range and not even" +msgstr "luach láithreach as raon, agus ní cothrom é" + +#: v850-opc.c:304 +msgid "immediate value must be even" +msgstr "caithfidh luach láithreach a bheith cothrom" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Réimír '#' ar iarraidh" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Réimír '.' ar iarraidh" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Réimír 'pof:' ar iarraidh" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Réimír 'pag:' ar iarraidh" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Réimír 'sof:' ar iarraidh" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Réimír 'seg:' ar iarraidh" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Drochthabhall i réamhincrimint" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Drochthabhall i iarincrimint" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Drochainm ar thabhall" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Lipéad i gcoinbhleacht le hainm tabhaill" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Lipéad i gcoinbhleacht le `Rx'" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Drochshlonn láithreach" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Luach beag láithreach gan athshuí" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Ní uimhir láithreach é an t-oibreann beag" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "Ní siombail é an t-oibreann" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Earráid chomhréire: gan ')' chun deiridh" + +#~ msgid "%operator operand is not a symbol" +#~ msgstr "ní siombail é oibreann an %oibreora\"" + +#~ msgid "offset not a multiple of 16" +#~ msgstr "ní iolraí de 16 é an fritháireamh" + +#~ msgid "offset not a multiple of 2" +#~ msgstr "ní cothrom é an fritháireamh" + +#~ msgid "offset greater than 62" +#~ msgstr "is níos mó ná 62 é an fritháireamh" + +#~ msgid "offset not a multiple of 4" +#~ msgstr "ní iolraí de 4 é an fritháireamh" + +#~ msgid "offset greater than 124" +#~ msgstr "is níos mó ná 124 é an fritháireamh" + +#~ msgid "offset not a multiple of 8" +#~ msgstr "ní iolraí de 8 é an fritháireamh" + +#~ msgid "offset greater than 248" +#~ msgstr "is níos mó ná 248 é an fritháireamh" + +#~ msgid "offset not between -2048 and 2047" +#~ msgstr "ní idir -2048 agus 2047 é an fritháireamh" + +#~ msgid "offset not between -8192 and 8191" +#~ msgstr "ní idir -8192 agus 8191 é an fritháireamh" + +#~ msgid "ignoring least significant bits in branch offset" +#~ msgstr "ag déanamh neamhshuim ar na giotáin is lú suntas i bhfritháireamh brainse" + +#~ msgid "value out of range" +#~ msgstr "luach as raon" + +#~ msgid "target register operand must be even" +#~ msgstr "caithfidh oibreann an spriocthabhaill a bheith cothrom" + +#~ msgid "source register operand must be even" +#~ msgstr "caithfidh oibreann an tabhaill fhoinsigh a bheith cothrom" + +#~ msgid "unknown\t0x%04x" +#~ msgstr "anaithnid\t0x%04x" diff --git a/external/gpl3/gdb/dist/opcodes/po/id.gmo b/external/gpl3/gdb/dist/opcodes/po/id.gmo new file mode 100644 index 0000000000000000000000000000000000000000..4ad376403f6e86244cfb21131ecfb712476e609e GIT binary patch literal 25350 zcmc(n37lnDUFQ!&1iK&vNC*%Ta(gMNtGixxRrOY>bT{cO=_cuP(+gn>>09sJs(Ss_ zy!&2vSBz0-l7Xl}7-2|oA_Nc}g$Riw0b$f&6vPmak>^`61>Op_z^NA*^LFqf;CsP67aLOo9|wOBJp5u~-T*!d-USZ7#JztE zd@Ju4zSNj^fbRp>gWE50c+%sY;5gqO0QZ330tdmNmpMEHZst7&mH%fwegT}|{r`ab z!4W$7O0WTn?*UNd{ys=o%=woYa|O5tRC#X%w}5X0hrvg{=YoF;UI6|*xCVUg%UwG* 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Arif E. Nugroho , 2009. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.20\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2009-09-07 14:08+0200\n" +"PO-Revision-Date: 2009-11-11 11:00+0700\n" +"Last-Translator: Arif E. Nugroho \n" +"Language-Team: Indonesian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "operand cabang tidak rata" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "petunjuk lompat tidak rata" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "referensi limm ilegal dalam instruksi terakhir!\n" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "tidak dapat memasukan nilai konstanta berbeda kedalam instruksi" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "register tambahan tidak diperbolehkan disini" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "mencoba untuk menset register baca-saja" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "mencoba untuk membaca register tulis-saja" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "nomor register tidak valid `%d'" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "terlalu banyak konstanta panjang" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "terlalu banyak shimm dalam load" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "store tidak memungkinkan" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "operand st error" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "alamat writeback tidak diijinkan" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "nilai simpan harus nol" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "insn load/shimm tidak valid" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "operand ld error" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "tanda jump, tetapi tidak ada .f yang terlihat" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "tanda jump, tetapi tidak ada alamat limm" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "tanda bit dari alamat jump limm hilang" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "mencoba menset bit HR" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "nilai tanda jump buruk" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "alamat cabang tidak dalam kelipatan 4 byte" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "harus menspesifikasikan .jd atau tidak ada akhiran nullify" + +#: arm-dis.c:1915 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4014 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Set nama register tidak dikenal: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4022 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Pilihan disasembler tidak dikenal: %s\n" + +#: arm-dis.c:4519 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Option disablembler khusus ARM berikut ini didukung untuk digunakan dengan\n" +"switch -M:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "tidak didefinisikan" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Kesalahan disasembler internal" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "konstrain tidak dikenal `%c'" + +#: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200 +#: iq2000-ibld.c:200 lm32-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 +#: mep-ibld.c:200 mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 +#: xstormy16-ibld.c:200 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand keluar batas (%ld tidak antara %ld dan %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand keluar batas (%lu tidak antara %lu dan %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:59 +#, c-format +msgid "Unknown error %d\n" +msgstr "Kesalahan tidak dikenal %d\n" + +#: dis-buf.c:68 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Alamat 0x%s di luar jangkauan.\n" + +#: fr30-asm.c:93 m32c-asm.c:877 m32c-asm.c:884 +msgid "Register number is not valid" +msgstr "Nomor register tidak valid" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Register harus berada diantara r0 dan r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Register harus berada diantara r8 dan r15" + +#: fr30-asm.c:116 m32c-asm.c:915 +msgid "Register list is not valid" +msgstr "Daftar register tidak valid" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1287 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Field tidak dikenal %d saat parsing.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1338 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "mnemonik hilang dalam string sintaks" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:736 iq2000-asm.c:837 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:626 lm32-asm.c:727 m32c-asm.c:1775 m32c-asm.c:1779 +#: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1473 mep-asm.c:1477 mep-asm.c:1564 +#: mep-asm.c:1665 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553 +#: xstormy16-asm.c:654 +msgid "unrecognized instruction" +msgstr "instruksti tidak dikenal" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1520 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan `%c')" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1530 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan akhir instruksi)" + +#: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730 +#: lm32-asm.c:620 m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1558 mt-asm.c:866 +#: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547 +msgid "junk at end of line" +msgstr "sampah di akhir baris" + +#: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836 +#: lm32-asm.c:726 m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1664 mt-asm.c:972 +#: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653 +msgid "unrecognized form of instruction" +msgstr "bentuk instruksi tidak dikenal" + +#: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848 +#: lm32-asm.c:738 m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1676 mt-asm.c:984 +#: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instruksi buruk `%.50s...'" + +#: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851 +#: lm32-asm.c:741 m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1679 mt-asm.c:987 +#: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instruksi buruk `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*tidak dikenal*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:256 mep-dis.c:1192 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:375 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Field tidak dikenal %d saat mencetak insn.\n" + +#: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163 +#: lm32-ibld.c:163 m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 +#: mt-ibld.c:163 openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand di luar batas (%ld tidak antara %ld dan %lu)" + +#: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184 +#: lm32-ibld.c:184 m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 +#: mt-ibld.c:184 openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "operand di luar batas (0x%lx tidak antara 0 dan 0x%lx)" + +#: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709 +#: lm32-ibld.c:630 m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1204 +#: mt-ibld.c:745 openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Field tidak dikenal %d saat membuild insn.\n" + +#: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884 +#: lm32-ibld.c:734 m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1803 +#: mt-ibld.c:965 openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Field tidak dikenal %d saat mendekode insn.\n" + +#: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015 +#: lm32-ibld.c:823 m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:2273 +#: mt-ibld.c:1165 openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Field tidak dikenal %d saat memperoleh operand int.\n" + +#: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128 +#: lm32-ibld.c:894 m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2725 +#: mt-ibld.c:1347 openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Field tidak dikenal %d saat memperoleh operand vma.\n" + +#: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248 +#: lm32-ibld.c:972 m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:3138 +#: mt-ibld.c:1536 openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Field tidak dikenal %d saat menset operand int.\n" + +#: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358 +#: lm32-ibld.c:1040 m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:3541 +#: mt-ibld.c:1715 openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Field tidak dikenal %d saat menset operand vma.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "hilang `]'" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Nomor register tujuan spesial di luar batas" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "Nilai dari operand A harus berupa 0 atau 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "nomor register harus genap" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:141 m32c-asm.c:237 +#: m32c-asm.c:279 m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "hilang `)'" + +#: h8300-dis.c:327 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:708 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Tidak mengerti 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "tidak dapat menangani insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*tidak dikenal*" + +#: i386-dis.c:8924 +msgid "" +msgstr "" + +#: i386-dis.c:9155 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Pilihan disablembler khusus i386/x86-64 berikut ini didukung untuk digunakan dengan\n" +"pilihan -M (pilihan double seharusnya dipisahkan dengan koma):\n" + +#: i386-dis.c:9159 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Disasemble dalam mode 64bit\n" + +#: i386-dis.c:9160 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Disassemble dalam mode 32bit\n" + +#: i386-dis.c:9161 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Disassemble dalam mode 16bit\n" + +#: i386-dis.c:9162 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Tampilkan instruksi dalam sintaks AT&T\n" + +#: i386-dis.c:9163 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Tampilkan instruksi dalam sintaks Intel\n" + +#: i386-dis.c:9164 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Tampilkan instruksi dalam mnemonic AT&T\n" + +#: i386-dis.c:9166 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Tampilkan instruksi dalam mnemonic Intel\n" + +#: i386-dis.c:9168 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Asumsikan ukuran alamat 64bit\n" + +#: i386-dis.c:9169 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Asumsikan ukuran alamat 32bit\n" + +#: i386-dis.c:9170 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Asumsikan ukuran alamat 16bit\n" + +#: i386-dis.c:9171 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Asumsikan ukuran data 32bit\n" + +#: i386-dis.c:9172 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Asumsikan ukuran data 16bit\n" + +#: i386-dis.c:9173 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " akhiran Selalu tampilkan akhiran instruksi dalam sintaks AT&T\n" + +#: i386-gen.c:435 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Error: " + +#: i386-gen.c:544 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: bitfield tidak diketahui: %s\n" + +#: i386-gen.c:546 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Bitfield tidak diketahui: %s\n" + +#: i386-gen.c:602 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s: %d: Hilang `)' dalam bitfield: %s\n" + +#: i386-gen.c:867 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "tidak dapat menemukan i386-opc.tbl untuk pembacaan, nomor error = %s\n" + +#: i386-gen.c:998 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "tidak dapat menemukan i386-reg.tbl untuk pembacaan, nomor error = %s\n" + +#: i386-gen.c:1075 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "tidak dapat membuat i386-init.h, nomor error = %s\n" + +#: i386-gen.c:1164 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "tidak dapat mengubah direktori ke \"%s\", nomor error = %s\n" + +#: i386-gen.c:1171 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d bit tidak digunakan dalam i386_cpu_flags.\n" + +#: i386-gen.c:1178 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d bit tidak digunakan dalam i386_operand_type.\n" + +#: i386-gen.c:1192 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "tidak dapat membuat i386-tbl.h, nomor error = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Peringatan: " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "catatan ganda %s tidak ditangani\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "tidak dapat menemukan ia64-ic.tbl untuk pembacaan\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "tidak dapat menemukan %s untuk pembacaan\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"format paling baru '%s'\n" +"tampak lebih terbatas dari '%s'\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "daerah saling menimpa %s->%s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "catatan saling menulis %d dengan catatan %d (IC:%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "tidak tahu bagaimana menspesifikasikan %% ketergantungan %s\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Tidak tahu bagaimana menspesifikasikan # ketergantungan %s\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] tidak memiliki terminal atau sub-kelas\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s tidak memiliki terminal atau sub-kelas\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "tidak ada insns terpetakan secara langsung ke terminal IC %s [%s]" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "tidak ada insns terpetakan langsung ke terminal IC %s\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "kelas %s didefinisikan tetapi tidak digunakan\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Peringatan: rsrc %s (%s) tidak memiliki chks\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Peringatan: rsrc %s (%s) tidak memiliki chks atau regs\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) tidak memiliki regs\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC catatan %d dalam opcode %s (IC:%s) konflik dengan sumber daya %s catatan %d\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC catatan %d untuk opcode %s (IC:%s) konflik dengan sumber data %s catatan %d\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode %s tidak memiliki kelas (ops %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "W kata kunci tidak valid dalam FR operand slot." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "offset(IP) bukan sebuah bentuk valid" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "(DP) ofset di luar batas." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "(SP) ofset di luar batas." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "penggunaan tidak legal dari tanda petik" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "operand di luar batas (tidak antara 1 dan 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: opindex tidak valid." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Alamat byte dibutuhkan. - harus genap." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address mengembalikan sebuah simbol. Literal dibutuhkan." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "percent-operator operand bukan sebuah simbol" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Mencoba untuk menemukan bit index dari 0" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "nilai langsung tidak dapat berupa register" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "nilai langsung di luar batas" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "21-bit ofset di luar batas" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "mengharapkan alamat relatif gp: gp(simbol)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "mengharapkan alamat relatif got: got(simbol)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "mengharapkan alamat relatif got: gotoffhi16(simbol)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "mengharapkan alamat relatif got: gotofflo16(simbol)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "tidak dikenal\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "tidak dikenal\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "imm:6 nilai langsung di luar batas" + +#: m32c-asm.c:147 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() mengambil sebuah alamat simbolik, bukan sebuah angka" + +#: m32c-asm.c:160 m32c-asm.c:164 m32c-asm.c:255 +msgid "dsp:8 immediate is out of range" +msgstr "dsp:8 nilai langsung di luar batas" + +#: m32c-asm.c:185 m32c-asm.c:189 +msgid "Immediate is out of range -8 to 7" +msgstr "nilai langsung di luar dari jangkauan -8 ke 7" + +#: m32c-asm.c:210 m32c-asm.c:214 +msgid "Immediate is out of range -7 to 8" +msgstr "nilai langsung di luar dari jangkauan -7 ke 8" + +#: m32c-asm.c:285 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() mengambil sebuah alamat simbolik, tetapi bukan sebuah angka" + +#: m32c-asm.c:308 m32c-asm.c:315 m32c-asm.c:378 +msgid "dsp:16 immediate is out of range" +msgstr "dsp:16 nilai langsung di luar batas" + +#: m32c-asm.c:404 +msgid "dsp:20 immediate is out of range" +msgstr "dsp:20 nilai langsung di luar batas" + +#: m32c-asm.c:430 m32c-asm.c:450 +msgid "dsp:24 immediate is out of range" +msgstr "dsp:24 nilai langsung di luar batas" + +#: m32c-asm.c:483 +msgid "immediate is out of range 1-2" +msgstr "nilai langsung di luar dari jangkauan 1-2" + +#: m32c-asm.c:501 +msgid "immediate is out of range 1-8" +msgstr "nilai langsung di luar dari jangkauan 1-8" + +#: m32c-asm.c:519 +msgid "immediate is out of range 0-7" +msgstr "nilai langsung di luar dari jangkauan 0-7" + +#: m32c-asm.c:555 +msgid "immediate is out of range 2-9" +msgstr "nilai langsung di luar dari jangkauan 2-9" + +#: m32c-asm.c:573 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Nomor bit untuk register umum pengindeksan diluar dari jangkauan 0-15" + +#: m32c-asm.c:611 m32c-asm.c:667 +msgid "bit,base is out of range" +msgstr "bit,bas di luar batas" + +#: m32c-asm.c:618 m32c-asm.c:623 m32c-asm.c:671 +msgid "bit,base out of range for symbol" +msgstr "bit,base di luar dari jangkauan untuk simbol" + +#: m32c-asm.c:807 +msgid "not a valid r0l/r0h pair" +msgstr "bukan sebuah valid pasangan r0l/r0h" + +#: m32c-asm.c:837 +msgid "Invalid size specifier" +msgstr "Ukuran penspesifikasi tidak valid" + +#: m68k-dis.c:1278 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1437 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Hanya $tp atau $13 diperbolehkan untuk opcode ini" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Hanya $sp atau $15 diperbolehkan untuk opcode ini" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "%function disini tidak valid" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "Nilai langsung di luar dari jangkauan -32768 ke 32767" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "Nilai langsung di luar dari jangkauan 0 ke 65535" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "Nilai langsung di luar dari jangkauan -512 ke 511" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "Nilai langsung di luar dari jangkauan -128 ke 127" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "Nilai tidak teralign secara mencukupi" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# internal error, urutan ekstensi (+) tidak lengkap" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# kesalahan internal, tidak terdefinisi urutan ekstensi(+%c)" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# kesalahan internal, tidak terdefinisi pemodifikasi(%c)" + +#: mips-dis.c:1942 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# kesalahan internal disasembler, modifier tidak dikenal (%c)" + +#: mips-dis.c:2173 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Pilihan disablembler khusus MIPS berikut ini didukung untuk digunakan dengan\n" +"pilihan -M (pilihan ganda seharusnya dipisahkan dengan koma):\n" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Tampilkan nama GPR menurut ABI yang dispesifikasikan.\n" +" Baku: berdasar dari binari yang sedang diassembled.\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Tampilkan nama FPR menurut ABI yang dispesifikasikan.\n" +" Baku: numerik.\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Tampilkan nama register CP0 menurut arsitektur\n" +" yang dispesifikasikan.\n" +" Baku: berdasar dari binari yang sedang diassembled.\n" + +#: mips-dis.c:2190 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Tampilkan nama HWR menurut arsitektur\n" +"\t\t\t yang dispesifikasikan.\n" +" Baku: berdasar dari binari yang sedang diassembled.\n" + +#: mips-dis.c:2195 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Tampilkan nama GPR dan FPR menurut ABI yang\n" +" dispesifikasikan.\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Tampilkan nama register CP0 dan HWR menurut\n" +" arsitektur yang dispesifikasikan.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Untuk pilihan diatas, nilai berikut didukung untuk \"ABI\":\n" +" " + +#: mips-dis.c:2208 mips-dis.c:2216 mips-dis.c:2218 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2210 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Untuk pilihan diatas, nilai berikut didukung untuk \"ARCH\":\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case buruk %d (%s) dalam %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Internal: Kode belum didebug (tidak ada test-case): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(tidak dikenal)" + +#: mmix-dis.c:513 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipe operand tidak dikenal: %d*" + +#: msp430-dis.c:327 +msgid "Illegal as emulation instr" +msgstr "Tidak legal karena emulasi instr" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:378 +msgid "Illegal as 2-op instr" +msgstr "Tidak legal karena 2-op instr" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Operand di luar batas. Harus berada diantara -32768 dan 32767." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "Masalah BESAR dalam parse_imm16!" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "Operand percent-operator bukan sebuah simbol" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "operand tidak valid. tipe mungkin hanya memiliki nilai 0,1,2." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:534 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:222 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "peringatan: mengabaikan pilihan -M%s yang tidak diketahui\n" + +#: ppc-dis.c:511 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Pilihan disablembler khusus PPC berikut ini didukung untuk digunakan dengan\n" +"pilihan -M:\n" + +#: ppc-opc.c:870 ppc-opc.c:898 +msgid "invalid conditional option" +msgstr "pilihan kondisional tidak valid" + +#: ppc-opc.c:900 +msgid "attempt to set y bit when using + or - modifier" +msgstr "berusaha menset bit y saat menggunakan modifier + atau -" + +#: ppc-opc.c:932 +msgid "invalid mask field" +msgstr "topeng daerah tidak valid" + +#: ppc-opc.c:958 +msgid "ignoring invalid mfcr mask" +msgstr "mengabaikan topeng mfcr tidak valid" + +#: ppc-opc.c:1008 ppc-opc.c:1043 +msgid "illegal bitmask" +msgstr "bitmask ilegal" + +#: ppc-opc.c:1163 +msgid "index register in load range" +msgstr "register indeks dalam daerah pemuatan" + +#: ppc-opc.c:1179 +msgid "source and target register operands must be different" +msgstr "sumber dan target operand register harus berbeda" + +#: ppc-opc.c:1194 +msgid "invalid register operand when updating" +msgstr "operand register tidak valid saat mengupdate" + +#: ppc-opc.c:1273 +msgid "invalid sprg number" +msgstr "nomor sprg tidak valid" + +#: ppc-opc.c:1443 +msgid "invalid constant" +msgstr "konstanta tidak valid" + +#: s390-dis.c:277 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Pilihan disablembler khusus S/390 berikut ini didukung untuk digunakan dengan\n" +"pilihan -M (pilihan ganda seharusnya dipisahkan dengan koma):\n" + +#: s390-dis.c:281 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Disassemble dalam mode arsitektur ESA\n" + +#: s390-dis.c:282 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Disassemble dalam mode z/Architecture\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\" == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1014 +msgid "unknown" +msgstr "tidak dikenal" + +#: v850-dis.c:239 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "shift operand tidak dikenal: %x\n" + +#: v850-dis.c:253 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "reg pop tidak dikenal: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:48 +msgid "displacement value is not in range and is not aligned" +msgstr "nilai displacement tidak dalam jangkauan dan tidak rata" + +#: v850-opc.c:49 +msgid "displacement value is out of range" +msgstr "nilai displacement di luar batas" + +#: v850-opc.c:50 +msgid "displacement value is not aligned" +msgstr "nilai displacement tidak rata" + +#: v850-opc.c:52 +msgid "immediate value is out of range" +msgstr "nilai langsung di luar batas" + +#: v850-opc.c:60 +msgid "branch value not in range and to odd offset" +msgstr "nilai cabang tidak dalam jangkauan" + +#: v850-opc.c:62 v850-opc.c:89 +msgid "branch value out of range" +msgstr "nilai cabang di luar jangkauan" + +#: v850-opc.c:65 v850-opc.c:92 +msgid "branch to odd offset" +msgstr "cabang offset ganjil" + +#: v850-opc.c:87 +msgid "branch value not in range and to an odd offset" +msgstr "nilai cabang di luar jangkauan dan offset ganjil" + +#: v850-opc.c:279 +msgid "invalid register for stack adjustment" +msgstr "register tidak valid untuk penyesuaian stack" + +#: v850-opc.c:299 +msgid "immediate value not in range and not even" +msgstr "nilai langsung tidak dalam jangkauan dan tidak genap" + +#: v850-opc.c:304 +msgid "immediate value must be even" +msgstr "nilai langsung harus genap" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Hilang awalan '#'" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Hilang awalan '.'" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Hilang awalan 'pof:'" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Hilang awalan 'pag:'" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Hilang awalan 'sof:'" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Hilanga awalan 'seg:'" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "register buruk dalam preinkremen" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Register buruk dalam pascainkremen" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Nama register buruk" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Label konflik dengan nama register" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Label konflik dengan `Rx'" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Ekspresi langsung yang buruk" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Tidak ada relokasi untuk immediate kecil" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Operand kecil bukan sebuah angka immediate" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "Operand bukan sebuah simbol" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Sintaks error: Tidak ada akhiran ')'" + +#~ msgid "unknown\t0x%04x" +#~ msgstr "tidak dikenal\t0x%04x" + +#~ msgid "offset not between -2048 and 2047" +#~ msgstr "offset tidak berada antara -2048 dan 2047" + +#~ msgid "offset not between -8192 and 8191" +#~ msgstr "offset tidak berada antara -8192 dan 8191" + +#~ msgid "ignoring least significant bits in branch offset" +#~ msgstr "mengabaikan least significant bit dalam offset cabang" diff --git a/external/gpl3/gdb/dist/opcodes/po/nl.gmo b/external/gpl3/gdb/dist/opcodes/po/nl.gmo new file mode 100644 index 0000000000000000000000000000000000000000..8e26600c2dbc9c3d79fd52dad874209e75c28098 GIT binary patch literal 25236 zcmd6u3!Ge6ecz7@!O_}|A7C4shp%ie+Lbk{-POa=S`yaFwqnUvB-ySp#+seEJ2Tpu zx#K%`b|vu$rUb&nP(z#q62NXk2{8#FxU}H#a7r)~)9^@IpoB+FNP!kUN!q$;=qLUD z&N=tao!Oby$}ykze)QLG?mhqW`k!A41QEk~59jdWJEN|D3)W z^9Rp1hF9|;a6kBA@J1y($C!@;`@s%4a-lKzfv*N1057=6n0fHS;48t)E;i;4@Lk}& z;NSW8*FV>oxA6W1_$y$1i7{i~nU^}8^mscs#rM~MyTFIRQSeERFL<6Y8+hLhD*vL# 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+"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=utf-8\n" +"Content-Transfer-Encoding: 8-bit\n" +"Plural-Forms: nplurals=2; plural=(n != 1);\n" + +# misschien 'branch' vertalen (vertakking? aftakking?) +# en unaligned vertalen als 'niet uitgelijnd'? +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "branch-operand niet uitgelijnd" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "jump-hint niet uitgelijnd" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Ongeldige limm-verwijzing in de laatste instructie!\n" + +# klinkt niet echt geweldig... +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "kan constantes met verschillende waarden niet in instructie inpassen" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "hulpregister hier niet toegestaan" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "poging tot het instellen van een alleen-lezen register" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "poging tot uitlezen van alleen-schrijven register" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "Ongeldig registernummer `%d'" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "te veel lange constantes" + +# of "bij opladen" ipv "in load"? +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "te veel shimms in load" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "onmogelijke store" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "st operand-fout" + +# of "terugschrijven van adres"? +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "address writeback niet toegestaan" + +# of beter 'store-waarde'? +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "opslagwaarde moet nul zijn" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "ongeldige load/shimm insn" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "ld operand-fout" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "jump-vlaggen, maar geen .f gezien" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "jump-vlaggen, maar geen limm addr" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "vlagbits van jump-adres limm gaan verloren" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "poging tot instellen van HR bits" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "slechte waarde van de jump-vlaggen" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "branch-adres niet op 4-byte grens" + +# klinkt wankel... +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "moet .jd of geen nullify-suffix opgeven" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +# Hoort set bij 'name', of bij 'register name' - of is het een voltood deelwoord? +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Registernaam-verzameling niet herkend: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Disassembler-optie niet herkend: %s\n" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"De volgende ARM-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "niet gedefinieerd" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "Interne fout in de disassembler" + +# Vertaling voor constraint? 'begrenzing' misschien? +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "onbekende constraint `%c'" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand buiten bereik (%ld niet tussen %ld en %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand buiten bereik (%lu niet tussen %lu en %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "Onbekende fout %d\n" + +# Slecht vertaald. Wat is de geijkte vertaling voor 'out of bounds'? +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Adres 0x%s is buiten de perken.\n" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "Registernummer is ongeldig" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Register moet tussen r0 en r7 liggen" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Register moet tussen r8 en r15 liggen" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "Registerlijst is ongeldig" + +# Klinkt niet echt geweldig, maar ja... +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Veld %d niet herkend tijdens analyse.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "mnemonic ontbreekt in syntaxstring" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "instructie niet herkend" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaxfout (verwachtte `%c', vond `%c')" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaxfout (verwachtte `%c', vond het einde van de instructie)" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "rommel aan einde van lijn" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "instructievorm niet herkend" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "slechte instructie `%s.50s...'" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "slechte instructie `%s.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*onbekend*" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Veld %d niet herkend bij het afdrukken van een insn.\n" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand buiten bereik (%ld niet tussen %ld en %lu)" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "operand buiten bereik (0x%lx niet tussen 0 en 0x%lx)" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Veld %d niet herkend bij het opbouwen van een insn.\n" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Veld %d niet herkend bij het decoderen van een insn.\n" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Veld %d niet herkend bij het ophalen van een int-operand.\n" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Veld %d niet herkend bij het ophalen van een vma-operand.\n" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Veld %d niet herkend bij het instellen van een int-operand.\n" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Veld %d niet herkend bij het instellen van een vma-operand.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "`]' ontbreekt" + +# of moet 'immediate' behouden worden? +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Nummer van special-purpose register is buiten bereik" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "Waarde van A-operand moet 0 of 1 zijn" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "registernummer moet even zijn" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "`)' ontbreekt" + +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Ik begrijp 0x%x niet\n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan niet omgaan met insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*onbekend*" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"De volgende i386/x86-64-specifieke disassembler-opties worden ondersteund voor\n" +"gebruik via de -M optie (meerdere opties moeten door komma's gescheiden\n" +"worden):\n" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Disassembleer in 64-bits modus\n" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Disassembleer in 32-bits modus\n" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Disassembleer in 16-bits modus\n" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Toon instructie in AT&T syntax\n" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Toon instructie in Intel syntax\n" + +# Of "... in AT&T mnemonic syntax"? +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Toon instructie in verkorte AT&T syntax\n" + +# Of "... in Intel mnemonic syntax"? +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Toon instructie in verkorte Intel syntax\n" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Ga uit van een 64-bits adresgrootte\n" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Ga uit van een 32-bits adresgrootte\n" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Ga uit van een 16-bits adresgrootte\n" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Ga uit van een 32-bits datagrootte\n" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Ga uit van een 16-bits datagrootte\n" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Toon altijd de instructiesuffix in AT&T syntax\n" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Fout: " + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: Onbekend bitveld: %s\n" + +#: i386-gen.c:593 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Onbekend bitveld: %s\n" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s: %d: `)' ontbreekt in bitveld: %s\n" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "kan invoerbestand i386-opc.tbl niet vinden; errno = %s\n" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "kan invoerbestand i386-reg.tbl niet vinden; errno = %s\n" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "kan i386-init.h niet aanmaken; errno = %s\n" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "kan niet naar directory \"%s\" gaan, errno = %s\n" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d ongebruikte bits in i386_cpu_flags.\n" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d ongebruikte bits in i386_operand_type.\n" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "kan i386-tbl.h niet aanmaken; errno = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Let Op: " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "meervoudige noot %s wordt niet opgevangen\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "kan invoerbestand ia64-ic.tbl niet vinden\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "kan invoerbestand %s niet vinden\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"het meest recente formaat '%s'\n" +"lijkt meer beperkend dan '%s'\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "overlappend veld %s->%s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "noot %d wordt overschreven door noot %d (IC:%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "ik weet niet hoe ik de %%-dependency %s moet opgeven\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Ik weet niet hoe ik de #-dependency %s moet opgeven\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] heeft geen eindsymbolen of subklassen\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s heeft geen eindsymbolen of subklassen\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s [%s] vertaald worden" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "er zijn geen insns die rechtstreeks naar eindsymbool IC %s vertaald worden\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "klasse %s is gedefinieerd maar wordt niet gebruikt\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Let Op: rsrc %s (%s) heeft geen chks\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Let Op: rsrc %s (%s) heeft geen chks of regs\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) heeft geen regs\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC noot %d in opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC noot %d voor opcode %s (IC:%s) geeft een conflict met resource %s noot %d\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode %s heeft geen klasse (ops %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "keyword W is ongeldig in operand-slot FR" + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "offset(IP) is geen geldige vorm" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "(DP) offset buiten bereik" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "(SP) offset buiten bereik" + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "ongeldig gebruik van haakjes" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "operand buiten bereik (niet tussen 1 en 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: ongeldige opindex." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Byte-adres vereist. - moet even zijn." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address gaf een symbool terug terwijl een letterlijke waarde vereist is." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "operand van percent-operator is geen symbool" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Poging tot vinden van bit-index van 0" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "onmiddellijke waarde kan geen register zijn" + +# of moet 'immediate' behouden worden? +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "onmiddellijke waarde is buiten bereik" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "21-bit offset is buiten bereik" + +# of gp-relatief? +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "relatief gp-adres verwacht: gp(symbool)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "relatief got-adres verwacht: got(symbool)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "relatief got-adres verwacht: gotoffhi16(symbool)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "relatief got-adres verwacht: gotofflo16(symbool)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "onbekend\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "onbekend\t0x%02lx" + +# Correcte vertaling van "imm:6 immediate"? +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "onmiddellijke waarde van imm:6 is buiten bereik" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() verwacht een symbolisch adres als argument, geen getal" + +# Correcte vertaling van "dsp:8 immediate"? +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +msgid "dsp:8 immediate is out of range" +msgstr "onmiddellijke waarde van dsp:8 is buiten bereik" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:184 m32c-asm.c:188 +msgid "Immediate is out of range -8 to 7" +msgstr "onmiddellijke waarde is buiten bereik (-8 tot 7)" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "onmiddellijke waarde is buiten bereik (-7 tot 8)" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() verwacht een symbolisch adres als argument, geen getal" + +# Correcte vertaling van "dsp:16 immediate"? +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +msgid "dsp:16 immediate is out of range" +msgstr "onmiddellijke waarde van dsp:16 is buiten bereik" + +# Correcte vertaling van "dsp:20 immediate"? +#: m32c-asm.c:399 +msgid "dsp:20 immediate is out of range" +msgstr "onmiddellijke waarde van dsp:20 is buiten bereik" + +# Correcte vertaling van "dsp:24 immediate"? +#: m32c-asm.c:425 m32c-asm.c:445 +msgid "dsp:24 immediate is out of range" +msgstr "onmiddellijke waarde van dsp:24 is buiten bereik" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:478 +msgid "immediate is out of range 1-2" +msgstr "onmiddellijke waarde is buiten bereik (1-2)" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:496 +msgid "immediate is out of range 1-8" +msgstr "onmiddellijke waarde is buiten bereik (1-8)" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:514 +msgid "immediate is out of range 0-7" +msgstr "onmiddellijke waarde is buiten bereik (0-7)" + +# of moet 'immediate' behouden worden? +#: m32c-asm.c:550 +msgid "immediate is out of range 2-9" +msgstr "onmiddellijke waarde is buiten bereik (2-9)" + +# Is dit de juiste interpretatie van "indexing general register" +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Bitnummer voor het indexeren van een general register is buiten bereik (0-15)" + +#: m32c-asm.c:606 m32c-asm.c:662 +msgid "bit,base is out of range" +msgstr "bit,base is buiten bereik" + +# klinkt niet geweldig, maar de originele boodschap is ook niet veel soeps :D +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +msgid "bit,base out of range for symbol" +msgstr "bit,base is buiten bereik voor een symbool" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "geen geldig r0l/r0h koppel" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "Ongeldige grootte-specificatie" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Deze opcode laat alleen $tp of $13 toe" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Deze opcode laat alleen stp of $15 toe" + +# "hier" wrong een beetje in dit geval, dus gebruik ik "op deze plek" +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "ongeldige %function() op deze plek" + +# of moet 'immediate' behouden worden? +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "Onmiddellijke waarde is buiten bereik (-32768 tot 32767)" + +# of moet 'immediate' behouden worden? +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "Onmiddellijke waarde is buiten bereik (0 tot 65535)" + +# of moet 'immediate' behouden worden? +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "Onmiddellijke waarde is buiten bereik (-512 tot 511)" + +# of moet 'immediate' behouden worden? +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "Onmiddellijke waarde is buiten bereik (-128 tot 127)" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "Waarde is onvoldoende uitgelijnd" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# interne fout, onvolledige extension sequence (+)" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# interne fout, extension sequence (+%c) niet gedefinieerd" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# interne fout, modifier (%c) niet gedefinieerd" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# interne fout in disassembler, modifier (%c) niet herkend" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"De volgende MIPS-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie (meerdere opties moeten door komma's gescheiden worden):\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Druk GPR-namen af volgens de opgegeven ABI.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Druk FPR-namen af volgens de opgegeven ABI.\n" +" Standaard: numeriek.\n" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Druk CP0 registernamen af volgens de opgegeven\n" +" architectuur.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Druk HWR-namen af volgens de opgegeven architectuur.\n" +" Standaard: gebaseerd op het binair bestand dat\n" +" gedesassembleerd wordt.\n" +"\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Druk GPR- en FPR-namen af volgens de opgegeven ABI.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Druk CP0 registernamen en HWR-namen af volgens de\n" +" opgegeven architectuur.\n" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ABI\":\n" +" " + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Voor de bovenstaande opties zijn dit de ondersteunde waarden voor \"ARCH\":\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Ongeldige case %d (%s) in %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Intern: Code niet gedebugd (test-case ontbreekt): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(onbekend)" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "onbekend type operanden: %d" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "Niet toegestaan als emulatie-instructie" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "Niet toegestaan als instructie met 2 operanden" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Operand buiten bereik. Moet tussen -32768 en 32767 liggen." + +# Should this even be here? +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "Groooooooot Probleem in parse_imm16!" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "Operand van percent-operator is geen symbool" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "ongeldige operand. type mag alleen 0,1,2 als waarde hebben." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "let op: onbekende -M%s optie wordt genegeerd\n" + +#: ppc-dis.c:523 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"De volgende PPC-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie:\n" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "ongeldige voorwaardelijke optie" + +# Dit kan waarschijnlijk beter +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "poging om y bit in te stellen wanneer + of - modifier gebruikt wordt" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "ongeldig maskerveld" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "ongeldig mfcr-masker wordt genegeerd" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "ongeldig bitmasker" + +# of is laadbereik beter? +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "indexregister in load-bereik" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "bron- en doel-registeroperanden moeten verschillen" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "ongeldige register-operand bij update" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "ongeldig sprg-nummer" + +#: ppc-opc.c:1451 +msgid "invalid constant" +msgstr "ongeldige constante" + +#: s390-dis.c:301 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"De volgende S/390-specifieke disassembler-opties worden ondersteund voor gebruik\n" +"via de -M optie (meerdere opties moeten door komma's gescheiden worden):\n" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Disassembleer in ESA-architectuur modus\n" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Disassembleer in z/Archiecture modus\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +# Looks like this is a typo (two spaces after the ':') +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interne fout: sparc-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Interne fout: sparc-opcode.h is verkeerd: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Interne fout: sparc-opcode.h is verkeerd: \"%s\" == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "onbekend" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "onbekende operand-shift: %x\n" + +#: v850-dis.c:377 +#, c-format +msgid "unknown reg: %d\n" +msgstr "onbekend reg: %d\n" + +# Wat is een goede vertaling voor 'displacement'? +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "displacement-waarde is niet in bereik en is niet uitgelijnd" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "displacement-waarde is buiten bereik" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "displacement-waarde is niet uitgelijnd" + +# of moet 'immediate' behouden worden? +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "onmiddellijke waarde is buiten bereik" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "branch-waarde buiten bereik" + +# Repeated message..., use 'to an odd...' to merge it +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "branch-waarde niet in bereik en naar onpare offset" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "branch naar onpare offset" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "ongeldig register voor stack-aanpassing" + +#: v850-opc.c:518 +msgid "invalid register name" +msgstr "Ongeldige registernaam" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "'#' prefix ontbreekt" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "'.' prefix ontbreekt" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "'pof.' prefix ontbreekt" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "'pag:' prefix ontbreekt" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "'sof:' prefix ontbreekt" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "'seg:' prefix ontbreekt" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Ongeldig register in preincrement" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Ongeldig register in postincrement" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Ongeldige registernaam" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Label geeft conflict met registernaam" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Label geeft conflict met `Rx'" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Slechte onmiddelijke expressie" + +# immediate what? 'value' assumed +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Geen relocatie voor kleine onmiddelijke waarde" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Kleine operand was geen onmiddellijk getal" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "Operand is geen symbool" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaxfout: Geen sluithaakje" diff --git a/external/gpl3/gdb/dist/opcodes/po/opcodes.pot b/external/gpl3/gdb/dist/opcodes/po/opcodes.pot new file mode 100644 index 000000000000..52865b58c5ad --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/opcodes.pot @@ -0,0 +1,1193 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. +# FIRST AUTHOR , YEAR. +# +#, fuzzy +msgid "" +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" +"POT-Creation-Date: 2010-11-05 10:27+0100\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=CHARSET\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:155 +msgid "branch operand unaligned" +msgstr "" + +#: alpha-opc.c:171 alpha-opc.c:187 +msgid "jump hint unaligned" +msgstr "" + +#: arc-dis.c:77 +msgid "Illegal limm reference in last instruction!\n" +msgstr "" + +#: arc-opc.c:386 +msgid "unable to fit different valued constants into instruction" +msgstr "" + +#: arc-opc.c:395 +msgid "auxiliary register not allowed here" +msgstr "" + +#: arc-opc.c:401 arc-opc.c:418 +msgid "attempt to set readonly register" +msgstr "" + +#: arc-opc.c:406 arc-opc.c:423 +msgid "attempt to read writeonly register" +msgstr "" + +#: arc-opc.c:428 +#, c-format +msgid "invalid register number `%d'" +msgstr "" + +#: arc-opc.c:594 arc-opc.c:645 arc-opc.c:673 +msgid "too many long constants" +msgstr "" + +#: arc-opc.c:668 +msgid "too many shimms in load" +msgstr "" + +#. Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "" + +#: arm-dis.c:1990 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4357 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4365 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "" + +#: arm-dis.c:4950 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + +#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 +#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 +#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 +#: xstormy16-ibld.c:201 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:60 +#, c-format +msgid "Unknown error %d\n" +msgstr "" + +#: dis-buf.c:69 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "" + +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774 +#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565 +#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555 +#: xstormy16-asm.c:662 +msgid "unrecognized instruction" +msgstr "" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "" + +#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 +#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 +#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +msgid "junk at end of line" +msgstr "" + +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 +#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 +#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +msgid "unrecognized form of instruction" +msgstr "" + +#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 +#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 +#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "" + +#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 +#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 +#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "" + +#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 +#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 +#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "" + +#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 +#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 +#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "" + +#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 +#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 +#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "" + +#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 +#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 +#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "" + +#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 +#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 +#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 +#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 +#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "" + +#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 +#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 +#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 +#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 +#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 +#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "" + +#: h8300-dis.c:314 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "" + +#: h8300-dis.c:695 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "" + +#: i386-dis.c:10671 +msgid "" +msgstr "" + +#: i386-dis.c:10968 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for " +"use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: i386-dis.c:10972 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr "" + +#: i386-dis.c:10973 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr "" + +#: i386-dis.c:10974 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr "" + +#: i386-dis.c:10975 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr "" + +#: i386-dis.c:10976 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr "" + +#: i386-dis.c:10977 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" + +#: i386-dis.c:10979 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" + +#: i386-dis.c:10981 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr "" + +#: i386-dis.c:10982 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr "" + +#: i386-dis.c:10983 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr "" + +#: i386-dis.c:10984 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr "" + +#: i386-dis.c:10985 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr "" + +#: i386-dis.c:10986 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr "" + +#: i386-gen.c:459 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "" + +#: i386-gen.c:591 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "" + +#: i386-gen.c:593 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "" + +#: i386-gen.c:649 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "" + +#: i386-gen.c:914 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "" + +#: i386-gen.c:1045 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "" + +#: i386-gen.c:1122 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "" + +#: i386-gen.c:1211 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "" + +#: i386-gen.c:1218 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "" + +#: i386-gen.c:1225 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "" + +#: i386-gen.c:1239 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "" + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "" + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "" + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "" + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "" + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "" + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "" + +#: m32c-asm.c:145 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "" + +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:253 +msgid "dsp:8 immediate is out of range" +msgstr "" + +#: m32c-asm.c:184 m32c-asm.c:188 +msgid "Immediate is out of range -8 to 7" +msgstr "" + +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "" + +#: m32c-asm.c:281 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "" + +#: m32c-asm.c:305 m32c-asm.c:312 m32c-asm.c:373 +msgid "dsp:16 immediate is out of range" +msgstr "" + +#: m32c-asm.c:399 +msgid "dsp:20 immediate is out of range" +msgstr "" + +#: m32c-asm.c:425 m32c-asm.c:445 +msgid "dsp:24 immediate is out of range" +msgstr "" + +#: m32c-asm.c:478 +msgid "immediate is out of range 1-2" +msgstr "" + +#: m32c-asm.c:496 +msgid "immediate is out of range 1-8" +msgstr "" + +#: m32c-asm.c:514 +msgid "immediate is out of range 0-7" +msgstr "" + +#: m32c-asm.c:550 +msgid "immediate is out of range 2-9" +msgstr "" + +#: m32c-asm.c:568 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "" + +#: m32c-asm.c:606 m32c-asm.c:662 +msgid "bit,base is out of range" +msgstr "" + +#: m32c-asm.c:613 m32c-asm.c:618 m32c-asm.c:666 +msgid "bit,base out of range for symbol" +msgstr "" + +#: m32c-asm.c:802 +msgid "not a valid r0l/r0h pair" +msgstr "" + +#: m32c-asm.c:832 +msgid "Invalid size specifier" +msgstr "" + +#: m68k-dis.c:1281 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1440 +#, c-format +msgid "\n" +msgstr "" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "" + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "" + +#: mips-dis.c:1939 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" + +#: mips-dis.c:2189 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2194 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" + +#: mips-dis.c:2207 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" + +#: mips-dis.c:2212 mips-dis.c:2220 mips-dis.c:2222 +#, c-format +msgid "\n" +msgstr "" + +#: mips-dis.c:2214 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "" + +#: mmix-dis.c:512 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "" + +#: msp430-dis.c:328 +msgid "Illegal as emulation instr" +msgstr "" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:379 +msgid "Illegal as 2-op instr" +msgstr "" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "" + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "" + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "" + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:533 +#, c-format +msgid "$" +msgstr "" + +#: ppc-dis.c:234 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "" + +#: ppc-dis.c:523 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" + +#: ppc-opc.c:878 ppc-opc.c:906 +msgid "invalid conditional option" +msgstr "" + +#: ppc-opc.c:908 +msgid "attempt to set y bit when using + or - modifier" +msgstr "" + +#: ppc-opc.c:940 +msgid "invalid mask field" +msgstr "" + +#: ppc-opc.c:966 +msgid "ignoring invalid mfcr mask" +msgstr "" + +#: ppc-opc.c:1016 ppc-opc.c:1051 +msgid "illegal bitmask" +msgstr "" + +#: ppc-opc.c:1171 +msgid "index register in load range" +msgstr "" + +#: ppc-opc.c:1187 +msgid "source and target register operands must be different" +msgstr "" + +#: ppc-opc.c:1202 +msgid "invalid register operand when updating" +msgstr "" + +#: ppc-opc.c:1281 +msgid "invalid sprg number" +msgstr "" + +#: ppc-opc.c:1451 +msgid "invalid constant" +msgstr "" + +#: s390-dis.c:301 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: s390-dis.c:305 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr "" + +#: s390-dis.c:306 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr "" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1015 +msgid "unknown" +msgstr "" + +#: v850-dis.c:365 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "" + +#: v850-dis.c:377 +#, c-format +msgid "unknown reg: %d\n" +msgstr "" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:55 +msgid "displacement value is not in range and is not aligned" +msgstr "" + +#: v850-opc.c:56 +msgid "displacement value is out of range" +msgstr "" + +#: v850-opc.c:57 +msgid "displacement value is not aligned" +msgstr "" + +#: v850-opc.c:59 +msgid "immediate value is out of range" +msgstr "" + +#: v850-opc.c:60 +msgid "branch value out of range" +msgstr "" + +#: v850-opc.c:61 +msgid "branch value not in range and to odd offset" +msgstr "" + +#: v850-opc.c:62 +msgid "branch to odd offset" +msgstr "" + +#: v850-opc.c:497 +msgid "invalid register for stack adjustment" +msgstr "" + +#: v850-opc.c:518 +msgid "invalid register name" +msgstr "" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "" diff --git a/external/gpl3/gdb/dist/opcodes/po/pt_BR.gmo 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z%u>b_PAR<|tPoqpl73>kULBw8i-SudCR^Hmsa0jhZ`+E4u|;1XE#qSvdx>)Z#6mnO zIj2$XyhAXhn#D{^{v%5YBmYVn31Ea8$ICJ<9gO%OY%f zS&lK!O86n|Zn>pIe6M=Ar@~;7XpG+m_9HMK1d_+|U_Mro(Y;4TM^UjU$gEsaC)(zF z23ej_0}kr+g1dKQEA6sxP;-2F9cvF(5$EJ38Q-$*s#RA^{mM1RhjY8;T=Iv3DlH}d z!lrqM5`6KK9}v!-UWB$SdZe`{LkSeJJz8W$z?OT>f$qpB9Ia4N$~n#9qgq)bGb1 xWT|*{ua+EG$sVgqLo&!pKT?BKk_F1atvaJ6+quUCi@7c, 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-07-24 04:00-0300\n" +"Last-Translator: Alexandre Folle de Menezes \n" +"Language-Team: Brazilian Portuguese \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8-bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "operando de desvio desalinhado" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "dica de salto desalinhada" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Referência limm ilegal na última instrução!\n" + +#: arm-dis.c:507 +msgid "" +msgstr "" + +#: arm-dis.c:1010 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Conjunto de nomes de registrador desconhecido: %s\n" + +#: arm-dis.c:1017 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Opção do desmontador desconhecida: %s\n" + +#: arm-dis.c:1191 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"As opções do desmontador espcíficas para ARM a seguir não são suportadas para\n" +"uso com a opção -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "indefinido" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Erro interno do desmontador" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "restrição `%c' desconhecida" + +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operando fora de faixa (%ld não está entre %ld e %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operando fora de faixa (%lu não está entre %lu e %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Erro %d desconhecido\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Endereço 0x%x está fora dos limites.\n" + +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Campo %d desconhecido durante análise.\n" + +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 +msgid "missing mnemonic in syntax string" +msgstr "mnemônico faltando na string de sintaxe" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 +msgid "unrecognized instruction" +msgstr "instrução não reconhecida" + +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "erro de sintaxe (esperado char `%c', encontrado `%c')" + +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "erro de sintaxe (esperado char `%c', encontrado fim de instrução)" + +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 +msgid "junk at end of line" +msgstr "lixo no final do arquivo" + +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 +msgid "unrecognized form of instruction" +msgstr "forma de instrução não reconhecida" + +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrução `%.50s...' errada" + +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrução `%.50s' errada" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 +msgid "*unknown*" +msgstr "*desconecida*" + +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Campo %d não reconhecido durante impressão de insn.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operando fora de faixa (%ld não está entre %ld e %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operando fora de faixa (%lu não está entre 0 e %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Campo %d não reconhecido durante construção de insn.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Campo %d não reconhecido durante decodificação de insn.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Campo %d não reconhecido ao obter operando int.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Campo %d não reconhecido ao obter operando vma.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Campo %d não reconhecido ao definir operando int.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Campo %d não reconhecido ao definir operando vma.\n" + +#: h8300-dis.c:385 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:396 +#, c-format +msgid "Don't understand %x \n" +msgstr "Não entendo %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "impossível lidar com insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*desconhecido*" + +#: i386-dis.c:1649 +msgid "" +msgstr "" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "desconhecido\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "desconhecido\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "desconhecido\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:255 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:337 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# erro interno, modificador (%c) indefinido" + +#: mips-dis.c:1209 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# erro interno do desmontador, modificador (%c) não reconhecido" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case %d errado (%s) em %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interno: Código não depurado (test-case faltando): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(desconhecido)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipo de operandos desconhecidos: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$" +msgstr "$" + +#: ppc-opc.c:777 ppc-opc.c:810 +msgid "invalid conditional option" +msgstr "opção condicional inválida" + +#: ppc-opc.c:812 +msgid "attempt to set y bit when using + or - modifier" +msgstr "tentativa de setar bit y ao usar modificador + ou -" + +#: ppc-opc.c:844 ppc-opc.c:896 +msgid "offset not a multiple of 4" +msgstr "deslocamento não é um múltiplo de 4" + +#: ppc-opc.c:869 +msgid "offset not between -2048 and 2047" +msgstr "deslocamento não está entre -2048 and 2047" + +#: ppc-opc.c:894 +msgid "offset not between -8192 and 8191" +msgstr "deslocamento não está entre -8192 and 8191" + +#: ppc-opc.c:922 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorando os bits menos significatiovs no deslocamento do desvio" + +#: ppc-opc.c:956 ppc-opc.c:993 +msgid "illegal bitmask" +msgstr "máscara de bits ilegal" + +#: ppc-opc.c:1066 +msgid "value out of range" +msgstr "valor fora de faixa" + +#: ppc-opc.c:1142 +msgid "index register in load range" +msgstr "registrador de índice na faixa de carregamento" + +#: ppc-opc.c:1158 +msgid "invalid register operand when updating" +msgstr "operando de registro inválido durante atualização" + +#. Mark as non-valid instruction +#: sparc-dis.c:750 +msgid "unknown" +msgstr "desconhecido" + +#: sparc-dis.c:825 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:836 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:885 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "deslocamento de operando desconhecido: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "registrador pop desconhecido: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "valor do deslocamento está fora da faixa e não está alinhado" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "valor do deslocamento está fora da faixa" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "valor do deslocamento não está alinhado" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "valor imediato está fora da faixa" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "valor do desvio fora da faixa e para deslocamento ímpar" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "valor do desvio fora da faixa" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "desvio para um deslocamento ímpar" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "valor do desvio fora da faixa e para um deslocamento ímpar" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registrador inválido para ajuste da pilha" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "valor imediato fora da faixa e não é par" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "o valor imediato deve ser par" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "Registrador errado no pré-incremento" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Registrador errado no pós-incremento" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Nome de registrador errado" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "O rótulo conflita com nome de registrador" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "O rótulo conflita com `Rx'" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Expressão imediata errada" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "O operando pequeno não era um número imediato" diff --git a/external/gpl3/gdb/dist/opcodes/po/ro.gmo b/external/gpl3/gdb/dist/opcodes/po/ro.gmo new file mode 100644 index 0000000000000000000000000000000000000000..6125448e6239616cafbf080d266beb8198c3f98a GIT binary patch literal 15986 zcmc(l3y>vOS;tQlguNl*oj`!l>}Ikvo4v!#>}Io>Y?kb9c9VhZgWU}aCM4;(w`Zoa z_jX^p`_9g+JQU;^0uoJOl~|=^N-Y!-QA&eRs}QJCuuxD0ABDMEmRh7NEd-QW{QXa# z?%Vgyoyjah*|lf>xBI-l^PTT?&bNR6oTof&c=YGRls|roF`ornTlmBCu4fo?3HWaC z4)6i+Rp4KPkAc@*W=t1+9Q*+I+RKgk1@K?Nv)}{IH0Dj6nrzt)aE_l3&Edt_*i<>n1>iS8^}GCe zIsbNokZ$I{Yr(s~9pGERE5VO|HSp8mt>72HL*Vn7>^ksup!&TX+zI|VDEhww&Vt_n zr@^T!a=y)jdwBm4sP%sl+zNgj6rY~Oq?&hzKNH|9LD8FmqVpke415IK2L1^sI-YQN z6^qn-M;xwzYX4zS?Y`i?f5+h@M5z8g@EY(P;LE{Z0~yl%4JiKoCrB4_IWMrlYzHU7 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b/external/gpl3/gdb/dist/opcodes/po/ro.po new file mode 100644 index 000000000000..ca0b870ee2e6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/ro.po @@ -0,0 +1,788 @@ +# Mesajele în limba românã pentru pachetul opcodes +# Copyright (C) 2003 Free Software Foundation, Inc. +# Eugen Hoanca , 2003 +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2003-07-21 16:53+0300\n" +"Last-Translator: Eugen Hoanca \n" +"Language-Team: Romanian \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-2\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "ramurã operand nealiniatã" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "sugestie salt(jump) nealiniat" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "referinþã limm ilegalã în ultima instrucþiune!\n" + +#: arm-dis.c:554 +msgid "" +msgstr "" + +#: arm-dis.c:1162 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Setare nume registru necunoscutã: %s\n" + +#: arm-dis.c:1169 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Opþiune dezasamblor necunsocutã: %s\n" + +#: arm-dis.c:1343 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Opþiunile ARM de dezasamblor specifice urmãtoare sunt permise cu folosirea\n" +"switch-ului -M:\n" + +#: avr-dis.c:117 avr-dis.c:127 +msgid "undefined" +msgstr "nedefinit(ã)" + +#: avr-dis.c:179 +msgid "Internal disassembler error" +msgstr "Eroare internã de dezasamblor" + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "constrângere necunoscutã `%c'" + +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operand în afara intervalului (%ld nu este între %ld ºi %ld)" + +#: cgen-asm.c:369 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operand în afara intervalului (%lu nu este între %lu ºi %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Eroare necunoscutã %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Adresa 0x%x este peste limite (out of bounds).\n" + +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Câmp necunoscut %d în analizã(parsing).\n" + +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 +msgid "missing mnemonic in syntax string" +msgstr "mnemonicã lipsã în sintaxã" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 +msgid "unrecognized instruction" +msgstr "instrucþiune necunoscutã" + +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "eroare de sintaxã ( se aºtepta %c', s-a primit `%c')" + +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "eroare de sintaxã (s-a aºteptat char `%c' s-a primit sfârºit de instrucþiune)" + +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 +msgid "junk at end of line" +msgstr "resturi(junk) la sfârºit de linie" + +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 +msgid "unrecognized form of instruction" +msgstr "formã de instrucþiune necunoscutã" + +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrucþiune greºitã ``%.50s...'" + +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrucþiune greºitã `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*necunoscut(ã)*" + +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Câmp necunoscut %d în tipãrire insn.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operand în afara limitelor (%ld nu este între %ld ºi %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operand în afara limitelor (%lu nu este între 0 ºi %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Câmp necunoscut %d în construire(building) insn.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Câmp necunoscut %d în decodare insn.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Câmp necunoscut %d în preluare operand int.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Câmp necunoscut %d în preluare operand vma.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Câmp necunoscut %d în setare operand int.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Câmp necunoscut %d în setare operand vma.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "numãrul registrului trebuie sã fie par" + +#: h8300-dis.c:377 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:760 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Nu înþeleg 0x%x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "nu fac faþã la inserarea %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*necunoscut(ã)*" + +#: i386-dis.c:1699 +msgid "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Eroare: " + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Avertisment: " + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "notele multiple %s nerezolvabile(handled)\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "nu pot gãsi ia64-ic.tbl pentru citire\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "nu pot gãsi %s pentru citire\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"cel mai recent format %s \n" +"pare mai restrictiv decât '%s'\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "câmp suprapus %s -> %s\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "suprascriere nota %d cu nota %d (IC:%s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "nu ºtiu cum se specificã dependinþele %% %s\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "nu ºtiu cum se specificã dependinþele # %s\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] nu are terminale sau sublclase\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s nu are terminale sau subclase\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "nici un insns mapat direct la terminalul IC %s [%s]" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "nici un insns mapat direct la terminalul IC %s\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "clasa %s este definitã dar nefolositã\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Avertisment: rsrc %s (%s) nu are chks%s\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) nu areo regs\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nota IC %d din opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Nota IC %d pentru opcode %s (IC:%s) e în conflict cu resursa %s nota %d\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode %s nu are clasã (ops %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "nu am putut schimba directorul în \"%s\", errno = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "Cuvânt cheie W invalidv în slotul operand FR." + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "offsetul(IP) nu are formã validã" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) offset în afara intervalului" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) offset în afara intervalului" + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "Folosire ilegalã de paranteze" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "operand în afara limitelor (nu este între 0 ºi 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: opindex invalid." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Se necesitã adresã byte. -trebuie sã fie parã (even)." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address a returnat un simbol. Se necesitã literal." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "%operator operandulk nu este un simbol" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "Se încearcã gãsirea bitului index de 0" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "valoarea directã(immediate) nu poate fi înregistratã" + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "valoare directã(immediate) în afara intervalului" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "offsetul 21 bit în afara intervalului" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "`)' lipsã" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "necunoscut(ã)\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "necunoscut(ã)\t0x%04lx" + +#: m10300-dis.c:766 +#, c-format +msgid "unknown\t0x%04x" +msgstr "necunoscut(ã)\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# eroare internã, secvenþã incompletã de extensie (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# eroare internã, secvenþã de extensie nedefinitã (+%c)" + +#: mips-dis.c:1000 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# eroare internã, modificator nedefinit(%c)" + +#: mips-dis.c:1751 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# eroare internã de dezasamblor, modificator necunoscut (%c)" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Opþiunile MIPS de dezasamblor specifice urmãtoare sunt permise cu folosirea\n" +"switch-ului -M (opþiunile multiple trebuie separate prin virgulã:\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Afiºeazã numele GPR potrivit ABI specificat.\n" +" Implicit: bazat pe binar ce este dezasamblat.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Afiºeazã numele FPR potrivit ABI specificat.\n" +" Implicit: numeric.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Afiºeazã numele de regiºtri CP0 potrivit\n" +" arhitecturii specifice.\n" +" Implicit: bazat pe binar în dezasamblare.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Afiºeazã numele HWR potrivit arhitecturii \n" +"\t\t\t specifice.\n" +" Implicit: bazat pe binar în dezasamblare.\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Afiºeazã numele GPR ºi FPR potriviti\n" +" ABI specificat.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Afiºeazã regiºtrii CP0 ºi numele HWR potrivit\n" +" arhitecturii specifice.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ABI\":\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Pentru opþiunile de mai sus, urmatoarele valori sunt suportate pentru \"ARCH\":\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Caz greºit %d (%s) in %s: %d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Intern: cod non debugged (caz test lipsã) %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(necunoscut)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tip necunoscut de operanzi: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +msgid "$" +msgstr "$" + +#: ppc-opc.c:781 ppc-opc.c:809 +msgid "invalid conditional option" +msgstr "opþiune condiþionalã invalidã" + +#: ppc-opc.c:811 +msgid "attempt to set y bit when using + or - modifier" +msgstr "se încearcã setarea bitului y în folosirea modificatorilor + sau -" + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "offsetul nu este multiplu de 16" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "offsetul nu este multiplu de 2" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "offset mai mare decât 62" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 +msgid "offset not a multiple of 4" +msgstr "offsetul nu este multiplu de 4" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "offset mai mare decât 124" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "offsetul nu este multiplu de 8" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "offset mai mare de 248" + +#: ppc-opc.c:950 +msgid "offset not between -2048 and 2047" +msgstr "offsetul nu este între -2048 ºi 2047" + +#: ppc-opc.c:973 +msgid "offset not between -8192 and 8191" +msgstr "offsetul nu este între -8192 ºi 8191" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "se ignorã mascã mfcr invalidã" + +#: ppc-opc.c:1059 +msgid "ignoring least significant bits in branch offset" +msgstr "se ignorã cei mai puþin semnificanþi biþi în offsetul ramurii(branch)" + +#: ppc-opc.c:1090 ppc-opc.c:1125 +msgid "illegal bitmask" +msgstr "bitmask ilegal" + +#: ppc-opc.c:1192 +msgid "value out of range" +msgstr "valoare în afara intervalului" + +#: ppc-opc.c:1262 +msgid "index register in load range" +msgstr "registru index în interval de încãrcare" + +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "operanzii regiºtri sursã ºi destinaþie trebuie sã fie diferiþi" + +#: ppc-opc.c:1294 +msgid "invalid register operand when updating" +msgstr "registru de operand invalid în updatare" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "operandul registru destinaþie trebuie sã fie par" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "operandul registru sursã trebuie sã fie par" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "necunoscut(ã)" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Eroare internã: opcode.h sparc greºit: \"%s\" == \"%s\"\n" + +#: v850-dis.c:221 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "schimbare(shift) de oberand necunoscutã: %x\n" + +#: v850-dis.c:233 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "pop reg necunoscut: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "valoarea deplasãrii în afara intervalului ºi nealiniatã" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "deplasare" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "valoarea deplasãrii nu este aliniatã" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "valoare directã(immediate) în afara intervalului" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "valoare ramurã(branch) în afara intervalului" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "ramurã(branch) la offset impar" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "valoare ramurã(branch) în afara intervalului ºi la offset impar" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registru invalid pentru modificare stivã" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "valoare directã(immediate) în afara intervalului ºi imparã" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "valoarea directã(immediate) trebuie sã fie parã" + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Registru greºit în preincrementare" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Registru greºit în postincrementare" + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Nume registru greºit" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Eticheta(label) se aflã în conflict cu numele de registru" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Eticheta(label) se aflã în conflict cu `Rx'" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Expresie directã(immediate) greºitã" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Nici o relocare pentru mai mic directã(immediate)" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Operandul redus nu a fost un numãr direct(immediate)" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operandul nu este simbol" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Eroare de sintaxã:Nu existã ')'" diff --git a/external/gpl3/gdb/dist/opcodes/po/sv.gmo b/external/gpl3/gdb/dist/opcodes/po/sv.gmo new file mode 100644 index 0000000000000000000000000000000000000000..2347bdcdad1204497037e0598e95888db63f3591 GIT binary patch literal 16004 zcmc(ldyE}deaBBI3HV|l2@nX6aSsP=cs@yaIpv$rH0JNX`?v6m=dZUKa~b$` z@C5h`@OJPe&o$;Rz$VxS$DU`*$H7m54}&|OZ%haL2KX-U#w(4v7yJVFQShp(jCle0 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zwUNwuo{3V#&&h|Qu`@}HFJKIH^z$O)h4?PY-UBYC(POftf8!Q zf^*Bb+m1&lALXH5mcN1mI4Pr<<*+K(RYo@|&FpuP!E&G6i}F{MxBP`{vAa%jVYyc7 v+LZre#myhbC5}C$uGASn5cSH01K)|@+@MtxoMh=@5mWta2BGN)NjLusRgFlS literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/opcodes/po/sv.po b/external/gpl3/gdb/dist/opcodes/po/sv.po new file mode 100644 index 000000000000..c0533d4186b9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/sv.po @@ -0,0 +1,830 @@ +# Swedish messages for opcodes. +# Copyright (C) 2006 Free Software Foundation, Inc. +# Christian Rose , 2001, 2002, 2003. +# Daniel Nylander , 2006. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.15.96\n" +"Report-Msgid-Bugs-To: \n" +"POT-Creation-Date: 2005-03-05 20:32+1030\n" +"PO-Revision-Date: 2006-02-13 22:58+0100\n" +"Last-Translator: Daniel Nylander \n" +"Language-Team: Swedish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=iso-8859-1\n" +"Content-Transfer-Encoding: 8bit\n" + +#: alpha-opc.c:331 +msgid "branch operand unaligned" +msgstr "grenoperanden ligger inte på jämn gräns" + +#: alpha-opc.c:353 alpha-opc.c:374 +msgid "jump hint unaligned" +msgstr "hopptipset ligger inte på jämn gräns" + +#: arc-dis.c:76 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Otillåten limm-referens i sista instruktionen!\n" + +#: arm-dis.c:1267 +msgid "" +msgstr "" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:1912 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Okänt registernamn är angivet: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:1920 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Okänt disassembleralternativ: %s\n" + +#: arm-dis.c:2093 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Följande ARM-specifika disassembleralternativ stöds för användning\n" +"tillsammans med flaggan -M:\n" + +#: avr-dis.c:112 avr-dis.c:122 +#, c-format +msgid "undefined" +msgstr "odefinierad" + +#: avr-dis.c:179 +#, c-format +msgid "Internal disassembler error" +msgstr "Internt fel i disassembleraren" + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "okänd begränsning \"%c\"" + +#: cgen-asm.c:336 fr30-ibld.c:197 frv-ibld.c:197 ip2k-ibld.c:197 +#: iq2000-ibld.c:197 m32r-ibld.c:197 openrisc-ibld.c:197 xstormy16-ibld.c:197 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operanden är utanför intervallet (%lu är inte mellan %lu och %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Okänt fel %d\n" + +#: dis-buf.c:66 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Adressen 0x%s ligger utanför tillåtna gränser.\n" + +#: fr30-asm.c:323 frv-asm.c:1298 ip2k-asm.c:530 iq2000-asm.c:465 +#: m32r-asm.c:338 openrisc-asm.c:252 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Okänt fält %d vid tolkning.\n" + +#: fr30-asm.c:372 frv-asm.c:1347 ip2k-asm.c:579 iq2000-asm.c:514 +#: m32r-asm.c:387 openrisc-asm.c:301 xstormy16-asm.c:333 +msgid "missing mnemonic in syntax string" +msgstr "instruktion saknas i syntaxsträng" + +#. We couldn't parse it. +#: fr30-asm.c:507 fr30-asm.c:511 fr30-asm.c:598 fr30-asm.c:699 frv-asm.c:1482 +#: frv-asm.c:1486 frv-asm.c:1573 frv-asm.c:1674 ip2k-asm.c:714 ip2k-asm.c:718 +#: ip2k-asm.c:805 ip2k-asm.c:906 iq2000-asm.c:649 iq2000-asm.c:653 +#: iq2000-asm.c:740 iq2000-asm.c:841 m32r-asm.c:522 m32r-asm.c:526 +#: m32r-asm.c:613 m32r-asm.c:714 openrisc-asm.c:436 openrisc-asm.c:440 +#: openrisc-asm.c:527 openrisc-asm.c:628 xstormy16-asm.c:468 +#: xstormy16-asm.c:472 xstormy16-asm.c:559 xstormy16-asm.c:660 +msgid "unrecognized instruction" +msgstr "okänd instruktion" + +#: fr30-asm.c:554 frv-asm.c:1529 ip2k-asm.c:761 iq2000-asm.c:696 +#: m32r-asm.c:569 openrisc-asm.c:483 xstormy16-asm.c:515 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")" + +#: fr30-asm.c:564 frv-asm.c:1539 ip2k-asm.c:771 iq2000-asm.c:706 +#: m32r-asm.c:579 openrisc-asm.c:493 xstormy16-asm.c:525 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade slutet på instruktion)" + +#: fr30-asm.c:592 frv-asm.c:1567 ip2k-asm.c:799 iq2000-asm.c:734 +#: m32r-asm.c:607 openrisc-asm.c:521 xstormy16-asm.c:553 +msgid "junk at end of line" +msgstr "skräp vid slutet på raden" + +#: fr30-asm.c:698 frv-asm.c:1673 ip2k-asm.c:905 iq2000-asm.c:840 +#: m32r-asm.c:713 openrisc-asm.c:627 xstormy16-asm.c:659 +msgid "unrecognized form of instruction" +msgstr "okänd instruktionsform" + +#: fr30-asm.c:710 frv-asm.c:1685 ip2k-asm.c:917 iq2000-asm.c:852 +#: m32r-asm.c:725 openrisc-asm.c:639 xstormy16-asm.c:671 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "felaktig instruktion \"%.50s...\"" + +#: fr30-asm.c:713 frv-asm.c:1688 ip2k-asm.c:920 iq2000-asm.c:855 +#: m32r-asm.c:728 openrisc-asm.c:642 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "felaktig instruktion \"%.50s\"" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*okänd*" + +#: fr30-dis.c:319 frv-dis.c:410 ip2k-dis.c:313 iq2000-dis.c:191 m32r-dis.c:262 +#: openrisc-dis.c:137 xstormy16-dis.c:170 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Okänt fält %d vid utskrift av instruktion.\n" + +#: fr30-ibld.c:168 frv-ibld.c:168 ip2k-ibld.c:168 iq2000-ibld.c:168 +#: m32r-ibld.c:168 openrisc-ibld.c:168 xstormy16-ibld.c:168 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %lu)" + +#: fr30-ibld.c:181 frv-ibld.c:181 ip2k-ibld.c:181 iq2000-ibld.c:181 +#: m32r-ibld.c:181 openrisc-ibld.c:181 xstormy16-ibld.c:181 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operanden utanför intervallet (%lu inte mellan 0 och %lu)" + +#: fr30-ibld.c:732 frv-ibld.c:858 ip2k-ibld.c:609 iq2000-ibld.c:715 +#: m32r-ibld.c:667 openrisc-ibld.c:635 xstormy16-ibld.c:680 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Okänt fält %d vid konstruktion av instruktion.\n" + +#: fr30-ibld.c:939 frv-ibld.c:1177 ip2k-ibld.c:686 iq2000-ibld.c:892 +#: m32r-ibld.c:806 openrisc-ibld.c:737 xstormy16-ibld.c:828 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Okänt fält %d vid avkodning av instruktion.\n" + +#: fr30-ibld.c:1088 frv-ibld.c:1458 ip2k-ibld.c:763 iq2000-ibld.c:1026 +#: m32r-ibld.c:922 openrisc-ibld.c:817 xstormy16-ibld.c:941 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Okänt fält %d vid hämtning av heltalsoperand.\n" + +#: fr30-ibld.c:1217 frv-ibld.c:1719 ip2k-ibld.c:820 iq2000-ibld.c:1140 +#: m32r-ibld.c:1018 openrisc-ibld.c:877 xstormy16-ibld.c:1034 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Okänt fält %d vid hämtning av vma-operand.\n" + +#: fr30-ibld.c:1351 frv-ibld.c:1989 ip2k-ibld.c:882 iq2000-ibld.c:1263 +#: m32r-ibld.c:1122 openrisc-ibld.c:946 xstormy16-ibld.c:1136 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Okänt fält %d vid inställning av heltalsoperand.\n" + +#: fr30-ibld.c:1473 frv-ibld.c:2247 ip2k-ibld.c:932 iq2000-ibld.c:1374 +#: m32r-ibld.c:1214 openrisc-ibld.c:1003 xstormy16-ibld.c:1226 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Okänt fält %d vid inställning av vma-operand.\n" + +#: frv-asm.c:978 +msgid "register number must be even" +msgstr "registernumret måste vara jämnt" + +#: h8300-dis.c:358 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:744 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Förstår inte 0x%x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "kan inte sätta in %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:342 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*okänd*" + +#: i386-dis.c:1733 +msgid "" +msgstr "" + +#: ia64-gen.c:297 +#, c-format +msgid "%s: Error: " +msgstr "%s: Fel: " + +#: ia64-gen.c:310 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Varning: " + +#: ia64-gen.c:496 ia64-gen.c:730 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "multipel anteckning %s hanteras inte\n" + +#: ia64-gen.c:607 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "kan inte hitta ia64-ic.tbl för läsning\n" + +#: ia64-gen.c:812 +#, c-format +msgid "can't find %s for reading\n" +msgstr "kan inte hitta %s för läsning\n" + +#: ia64-gen.c:1036 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"allra senaste formatet \"%s\"\n" +"verkar mer restriktivt än \"%s\"\n" + +#: ia64-gen.c:1047 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "överlappande fält %s->%s\n" + +#: ia64-gen.c:1244 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "skriver över anteckning %d med anteckning %d (IC:%s)\n" + +#: ia64-gen.c:1443 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "vet inte hur %%-beroende %s ska anges\n" + +#: ia64-gen.c:1465 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Vet inte hur #-beroende %s ska anges\n" + +#: ia64-gen.c:1504 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] har inga terminaler eller underklasser\n" + +#: ia64-gen.c:1507 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s har inga terminaler eller underklasser\n" + +#: ia64-gen.c:1516 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "inga instruktioner mappade direkt till terminal-IC %s [%s]" + +#: ia64-gen.c:1519 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "inga instruktioner mappade direkt till terminal-IC %s\n" + +#: ia64-gen.c:1530 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "klassen %s är definierad men inte använd\n" + +# Misstänkt pluralhack! +#: ia64-gen.c:1541 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Varning: rsrc %s (%s) har inga kontroller%s\n" + +#: ia64-gen.c:1545 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) har inga register\n" + +#: ia64-gen.c:2444 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" +"IC-anteckning %d i instruktion %s (IC:%s) står i konflikt med resurs %s\n" +"anteckning %d\n" + +#: ia64-gen.c:2472 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" +"IC-anteckning %d för instruktion %s (IC:%s) står i konflikt med resurs %s\n" +"anteckning %d\n" + +#: ia64-gen.c:2486 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "instruktion %s har ingen klass (operationer %d %d %d)\n" + +#: ia64-gen.c:2816 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "kan inte byta katalog till \"%s\", felnummer = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "W-nyckelord ogiltigt i FR-operandlucka." + +#. Invalid offset present. +#: ip2k-asm.c:117 +msgid "offset(IP) is not a valid form" +msgstr "avståndet(IP) är inte en giltig form" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:165 +msgid "(DP) offset out of range." +msgstr "(DP) avståndet är utanför intervallet." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:206 +msgid "(SP) offset out of range." +msgstr "(SP) avståndet är utanför intervallet." + +#: ip2k-asm.c:222 +msgid "illegal use of parentheses" +msgstr "otillåten användning av parenteser" + +#: ip2k-asm.c:229 +msgid "operand out of range (not between 1 and 255)" +msgstr "operanden utanför intervallet (inte mellan 1 och 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:254 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: ogiltigt opindex." + +#: ip2k-asm.c:309 +msgid "Byte address required. - must be even." +msgstr "Byteadress krävs - måste vara jämn." + +#: ip2k-asm.c:318 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address returnerade en symbol. Literal krävs." + +#: ip2k-asm.c:376 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "%operator-operand är inte en symbol" + +#: ip2k-asm.c:430 +msgid "Attempt to find bit index of 0" +msgstr "Försök att hitta 0-bitindex" + +#: iq2000-asm.c:115 iq2000-asm.c:146 +msgid "immediate value cannot be register" +msgstr "omedelbart värde kan inte vara register" + +#: iq2000-asm.c:126 iq2000-asm.c:156 +msgid "immediate value out of range" +msgstr "omedelbart värde är utanför intervallet" + +#: iq2000-asm.c:185 +msgid "21-bit offset out of range" +msgstr "21-bitars avstånd utanför intervallet" + +#: iq2000-asm.c:210 iq2000-asm.c:240 iq2000-asm.c:277 iq2000-asm.c:310 +#: openrisc-asm.c:90 openrisc-asm.c:144 +msgid "missing `)'" +msgstr "\")\" saknas" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "okänd\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "okänd\t0x%04lx" + +#: m10300-dis.c:767 +#, c-format +msgid "unknown\t0x%04x" +msgstr "okänd\t0x%04x" + +#: m68k-dis.c:295 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1089 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# " + +#: mips-dis.c:720 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# internt fel, ofullständig ändelsesekvens (+)" + +#: mips-dis.c:779 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# internt fel, odefinierad ändelsesekvens (+%c)" + +#: mips-dis.c:1037 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# internt fel, okänd modifierare(%c)" + +#: mips-dis.c:1793 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# internt disassemblerfel, okänd modifierare (%c)" + +#: mips-dis.c:1805 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Följande MIPS-specifika disassembleralternativ stöds för användning\n" +"tillsammans med flaggan -M (flera alternativ kan skiljas åt med komman):\n" + +#: mips-dis.c:1809 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Skriv ut GPR-namn enligt det angivna ABI:t.\n" +" Standard: baserat på den binärfil som\n" +" disassembleras.\n" + +#: mips-dis.c:1813 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Skriv ut FPR-namn enligt det angivna ABI:t.\n" +" Standard: numeriskt.\n" + +#: mips-dis.c:1817 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARK Skriv ut CP0-registernamn enligt den angivna\n" +" arkitekturen.\n" +" Standard: baserat på den binärfil som\n" +" disassembleras.\n" + +#: mips-dis.c:1822 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARK Skriv ut HWR-namn enligt den angivna \n" +"\t\t\t arkitekturen.\n" +" Standard: baserat på den binärfil som\n" +" disassembleras.\n" + +#: mips-dis.c:1827 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Skriv ut GPR- och FPR-namn enligt det angivna\n" +" ABI:t.\n" + +#: mips-dis.c:1831 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARK Skriv ut CP0-register med HWR-namn enligt\n" +" angiven arkitektur.\n" + +#: mips-dis.c:1835 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" För flaggorna ovan stöds följande värden på \"ABI\":\n" +" " + +#: mips-dis.c:1840 mips-dis.c:1848 mips-dis.c:1850 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1842 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" För flaggorna ovan stöds följande värden på \"ARK\":\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Felaktigt fall %d (%s) i %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Internt: Ej felsökt kod (testfall saknas): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(okänd)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*okänd operandtyp: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-opc.c:794 ppc-opc.c:822 +msgid "invalid conditional option" +msgstr "ogiltig villkorlig flagga" + +#: ppc-opc.c:824 +msgid "attempt to set y bit when using + or - modifier" +msgstr "försök att ställa in y-biten då modifieraren + eller - användes" + +#: ppc-opc.c:852 +msgid "offset not a multiple of 16" +msgstr "avståndet är inte en multipel av 16" + +#: ppc-opc.c:871 +msgid "offset not a multiple of 2" +msgstr "avståndet är inte en multipel av 2" + +#: ppc-opc.c:873 +msgid "offset greater than 62" +msgstr "avståndet är större än 62" + +#: ppc-opc.c:892 ppc-opc.c:937 ppc-opc.c:981 +msgid "offset not a multiple of 4" +msgstr "avståndet är inte en multipel av 4" + +#: ppc-opc.c:894 +msgid "offset greater than 124" +msgstr "avståndet är större än 124" + +#: ppc-opc.c:913 +msgid "offset not a multiple of 8" +msgstr "avståndet är inte en multipel av 8" + +#: ppc-opc.c:915 +msgid "offset greater than 248" +msgstr "avståndet är större än 248" + +#: ppc-opc.c:958 +msgid "offset not between -2048 and 2047" +msgstr "avståndet är inte mellan -2048 och 2047" + +#: ppc-opc.c:979 +msgid "offset not between -8192 and 8191" +msgstr "avståndet är inte mellan -8192 och 8191" + +#: ppc-opc.c:1007 +msgid "invalid mask field" +msgstr "ogiltigt maskfält" + +#: ppc-opc.c:1033 +msgid "ignoring invalid mfcr mask" +msgstr "ignorerar ogiltig mfcr-mask" + +#: ppc-opc.c:1075 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorerar minst signifikanta bitarna i grenavstånd" + +#: ppc-opc.c:1105 ppc-opc.c:1140 +msgid "illegal bitmask" +msgstr "otillåten bitmask" + +#: ppc-opc.c:1205 +msgid "value out of range" +msgstr "värdet är utanför intervallet" + +#: ppc-opc.c:1273 +msgid "index register in load range" +msgstr "indexregistret är i inläsningsintervallet" + +#: ppc-opc.c:1289 +msgid "source and target register operands must be different" +msgstr "käll- och målregisteroperander måste vara olika" + +#: ppc-opc.c:1304 +msgid "invalid register operand when updating" +msgstr "ogiltig registeroperand vid uppdatering" + +#: ppc-opc.c:1343 +msgid "target register operand must be even" +msgstr "målregisteroperand måste vara jämn" + +#: ppc-opc.c:1357 +msgid "source register operand must be even" +msgstr "källregisteroperand måste vara jämn" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "okänd" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\" == \"%s\"\n" + +#: v850-dis.c:225 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "okänt operandskifte: %x\n" + +#: v850-dis.c:237 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "okänt pop-register: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:69 +msgid "displacement value is not in range and is not aligned" +msgstr "förskjutningsvärdet är inte inom intervallet och ligger inte på jämn gräns" + +#: v850-opc.c:70 +msgid "displacement value is out of range" +msgstr "förskjutningsvärdet är utanför intervallet" + +#: v850-opc.c:71 +msgid "displacement value is not aligned" +msgstr "förskjutningsvärdet ligger inte på jämn gräns" + +#: v850-opc.c:73 +msgid "immediate value is out of range" +msgstr "omedelbara värdet är utanför intervallet" + +#: v850-opc.c:84 +msgid "branch value not in range and to odd offset" +msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd" + +#: v850-opc.c:86 v850-opc.c:118 +msgid "branch value out of range" +msgstr "grenvärdet är utanför intervallet" + +#: v850-opc.c:89 v850-opc.c:121 +msgid "branch to odd offset" +msgstr "grening till udda avstånd" + +#: v850-opc.c:116 +msgid "branch value not in range and to an odd offset" +msgstr "grenvärdet är inte inom intervallet och till ett udda avstånd" + +#: v850-opc.c:347 +msgid "invalid register for stack adjustment" +msgstr "ogiltigt register för stackjustering" + +#: v850-opc.c:371 +msgid "immediate value not in range and not even" +msgstr "omedelbara värdet är inte inom intervallet och inte jämnt" + +#: v850-opc.c:376 +msgid "immediate value must be even" +msgstr "omedelbara värdet måste vara jämnt" + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Felaktigt register i förhandsökning" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Felaktigt register i efterhandsökning" + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Felaktigt registernamn" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Etiketten står i konflikt med registernamn" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Etiketten står i konflikt med \"Rx\"" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Felaktigt omedelbart uttryck" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Ingen omlokalisering för litet omedelbart tal" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Liten operand var inte ett omedelbart tal" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operanden är inte en symbol" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaxfel: Inget eftersläpande \")\"" + +#~ msgid "Hmmmm %x" +#~ msgstr "Hmmmm %x" + +#~ msgid "Don't understand %x \n" +#~ msgstr "Förstår inte %x \n" + +#~ msgid "No relocation for small immediate number" +#~ msgstr "Ingen omlokalisering för litet omedelbart tal" + +#~ msgid "unrecognized keyword/register name" +#~ msgstr "okänt namn på nyckelord/register" diff --git a/external/gpl3/gdb/dist/opcodes/po/tr.gmo b/external/gpl3/gdb/dist/opcodes/po/tr.gmo new file mode 100644 index 0000000000000000000000000000000000000000..98b9df15351bb968b81b4e2d65c0bf9170d80498 GIT binary patch literal 16094 zcmd6tYmgjQb;mEn#Ay7$53sQT`&!nryOL(TyLwn&B!OPGWl6T8hacEj>Y3@CZBI}4 zxF6Ea226k$8#_*7CnQwjiueFgK_Ib6;SV4RD!am!lq&_HVhnj2LZw2=u2fq^Zz6gE|Ty>FBDfk2MN$~EAmHIUJW3T}}{uZS^1pYgCFPL7U)Dz&h!OOuT zmnwA=7=!D;FM{jAm%t(Lip!K@DD_^DF4SJ|I`BU50`MV_q19vHRp6&AehHK*JP*DD ze8Il|D|j{UuYvqiSHgtwv6?^c0=I%P?tS3fz=y$W!QTb10lx}L`|pEq2Y&)eyNlnN z$!{$P>uNXnZtz}kHTY5RO7M$d2|NSt1iuCD0N=)7YruOzY4a1a!I zx*L@5Q=ruU7%1!g`yl_+H~AxS`=Ncm2;s^1)u6Py1(f+#Kv}m(K~zHhk;Pf?0^Yw1 z3ZFj&-vho0W#XsW1`2;iK#|kqpvdW~7QX|slBrl8&kb29EV7H_h62$cRqi%)_y zQGW~yUw;9Pga2u9t2234utV(@Y~>Lz-W-UfLF5VKL|bw z9s%FPPo0*~1VNm4O21Rc_56ZfK4-~#$2CoBUaZA8TQ0!P4WC_#+ zDC_@z`+eGef7rf%78Jeu5_k#tA}DhBCs2bw1sOtJ%c2Q?w}GC5 zgKI$fz84gId&Itf1-y~>pMauIWrQd5+Y8G05h(iodmu}qzGCqQpvbj^5rPGE4Jh;5 z3yS`Q;70JX_WiFdUdG^3ek&;D4}t5!FI)UE$Uk-Mx=im6fHJQSgQ8zw2Zf&(LDBnH zLH?;r>0}SM%i@!u%;#@FsrMQv>v|P~i=1x+ZvyWJrTwQsncwr^X7E)|)^Q9bW&Ha< z(XXdLss9b|GVoRV{d|Nd{+|O8z50=Tzk*4?f?5yC{%(L*f+sD09lV0~?}9SkE1>M(3s45ZcY{}f z+d$##UW*?E*{bSupseqogAA!&17(~I{1JX11QC_`94K=6J5cz)93cu{{Nai#RJqjIzJ_^aR8@dyE5SoHM0*M}q>~DqSVXH29 z#`tm%Br=mn*5($-fnq3sKFE)U>`T?+uYw|@!}eX)-GhD(y3T$RNFb3dOQk*l-3`ej z`X)N?A?PMZo{vGU`IXtH`}sWyT@1ozpUA$59?J7p=yB+3 zd9lwgg6G@cPlCS=iN4$pT@M|AJ`TwvcCq`B{k0$ZO~{Atf=~-%Uqwe#=yE830)G4o zvc9f$To@`&zOLQjvFRQcdyE}bVTchQ`X}a+i8G`}xXMf}ciQch)R7Y;zixW4}rk-}H)iA0F zzey+@E%wAMx9UxLOu>n&Q(od$lQeQimTI!oope$^na~v{rd=55iWfLhTUT5euja*0 z9J|em@76|)SSMRi&i(e?-Hc@1-@N}oAEtGOvu)dVFOQ)hZMu{jy#|t_1Tg6-NI*S}iD^{#PeE)k3g$^yXP$DuXsOkO-wv@`uTT9s(YYRKvg^E--?2~eRG9iT_MML1mJ>N*i7IVf4Vz6T9)_Fi^=7uCcB3ea zCiKAQrs=JG!(_No;P}0hHI>%tG>F`4SPwke+s&{h#v#%}1J&W~mbS7NFcusou6Cyr zH;6Ht@bX~l231!Nt?Ab$4QlSB7tnj(CjAHMG|E{r9Ie`16l_%kqvO*nR;*5gMi3qk zR;z)qv8vl9AhAfC{>GTE5lcR5jj37gPrXy^W69ZpWhZlc2! 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zanPJFup@Gw$}E3A#<&Ti`xdPqWNk6=eOhfABy8_nk|nrMUdeBX8j4{<1?LT0Hd!vJ zNs?>PY9{TKsS@r;R+JN7X6bNVVzlLylLjeEKJS#UAO*Ik$5my4l1YIPDUX}m7S-(O zn9B$5U=c6JOs;sch}7oEI6!6xLvwDFJz}JtwF-#aof#9x;YG9mbSH<;`AM^mG04(p zjd(=mW}(~0*<*5V+RRuU7CmoZc9%K1He^;)F8>RoD9op9PLPvM)R1r{@76ZTJId>N zJ$5#)Y|V$9(oiiuRHV;z#byX3wwBCN9=glTjxjlBX=BE1TGN(A{llvNH2Sk9IWu#) z#@RVL#BvcS|G#ssIm;B8v`!$A#SHM5Uxju3%+qR}Li0s3Yx6%%t8BhSH@PjvrF80A vZAID=ku4e)n8OnJwyshuq3lv@VS%x&;^ccT;naTvc58;7 literal 0 HcmV?d00001 diff --git a/external/gpl3/gdb/dist/opcodes/po/tr.po b/external/gpl3/gdb/dist/opcodes/po/tr.po new file mode 100644 index 000000000000..f01f58dbf159 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/po/tr.po @@ -0,0 +1,788 @@ +# translation of opcodes-2.14rel030712.tr.po to Turkish +# Copyright (C) 2003 Free Software Foundation, Inc. +# Deniz Akkus Kanca , 2001,2003. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2003-07-13 22:58+0300\n" +"Last-Translator: Deniz Akkus Kanca \n" +"Language-Team: Turkish \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: KBabel 1.0\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "dal iÅŸleneni hizalı deÄŸil" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "atlama iÅŸareti hizalı deÄŸil" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Son iÅŸlemde geçersiz limm referansı!\n" + +#: arm-dis.c:554 +msgid "" +msgstr "" + +#: arm-dis.c:1162 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Bilinmeyen yazmaç ad kümesi: %s\n" + +#: arm-dis.c:1169 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Bilinmeyen karşıt-çevirici seçeneÄŸi: %s\n" + +#: arm-dis.c:1343 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"AÅŸağıdaki ARM'a özgü karşıt-çevirici seçenekleri \n" +"-M seçeneÄŸi ile kullanılabilir:\n" + +#: avr-dis.c:117 avr-dis.c:127 +msgid "undefined" +msgstr "tanımlanmamış" + +#: avr-dis.c:179 +msgid "Internal disassembler error" +msgstr "İç karşıt-çevirici hatası " + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "`%c' bilinmeyen kısıtı" + +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "Kapsam dışı terim (%ld, %ld ve %ld arasında deÄŸil) " + +#: cgen-asm.c:369 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "Kapsam dışı terim (%lu, %lu ve %lu arasında deÄŸil)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Bilinmeyen hata %d\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "0x%x adresi sınırların dışında.\n" + +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Ayrıştırma esnasında bilinmeyen alan %d bulundu.\n" + +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 +msgid "missing mnemonic in syntax string" +msgstr "biçem dizgesinde ipucu eksik" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 +msgid "unrecognized instruction" +msgstr "bilinmeyen iÅŸlem" + +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "biçem hatası (char `%c' beklenirken `%c' bulundu)" + +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "biçem hatası (char `%c' beklenirken iÅŸlem sonu bulundu)" + +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 +msgid "junk at end of line" +msgstr "Satır sonu bozuk " + +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 +msgid "unrecognized form of instruction" +msgstr "bilinmeyen iÅŸlem türü" + +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "geçersiz iÅŸlem `%.50s...'" + +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "geçersiz iÅŸlem `%.50s'" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*bilinmeyen*" + +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "yönerge yazdırılırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "Kapsam dışı iÅŸlenen (%ld, %ld ve %lu arasında deÄŸil) " + +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "kapsam dışı terim (%lu 0 ve %lu arasında deÄŸil) " + +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Yönerge oluÅŸturulurken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Yönerge çözümlenirken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "`int' terimi alınırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "`vma' terimi alınırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "`int' terimi atanırken bilinmeyen alan %d bulundu.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "`vma' terimi atanırken bilinmeyen alan %d bulundu.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "yazmaç çift sayı olmalı" + +#: h8300-dis.c:377 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:760 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "0x%x anlaşılamadı\n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "insert %d yaptırılamıyor\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*bilinmeyen*" + +#: i386-dis.c:1699 +msgid "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Hata: " + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Uyarı: " + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "çoklu not %s desteklenmiyor\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "ia64-ic.tbl okunmak için bulunamadı\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "%s okunmak için bulunamadı\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"en son biçem '%s'\n" +"'%s'dan daha kısıtlayıcı\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "üstüste binmiÅŸ alan %s->%s\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "%2$d notu %1$d notunun üstüne yazılıyor (IC:%3$s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "%% %s bağımlılığının nasıl tanımlanacağı bilinmiyor\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "# %s bağımlılığının nasıl tanımlanacağı bilinmiyor\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC: %s [%s]'nin deÄŸiÅŸmez simgeleri veya alt sınıfları yok\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC: %s'nin deÄŸiÅŸmez simgeleri veya alt sınıfları yok\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "deÄŸiÅŸmez simge IC %s [%s]'ye direkt eÅŸleÅŸen iÅŸlem yok " + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "deÄŸiÅŸmez simge IC %s'ye direkt eÅŸleÅŸen iÅŸlem yok\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "%s sınıfı tanımlanmış fakat kullanılmamış\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Uyarı: rsrc %s (%s) içinde kontrol yok %s\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "rsrc %s (%s) içinde yazmaç yok\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "(IC:%3$s) opkod %2$s içinde IC notu %1$d, %4$s kaynağı %5$d notuyla çeliÅŸiyor\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "(IC:%3$s) opkod %2$s için IC notu %1$d, %4$s kaynağı %5$d notuyla çeliÅŸiyor\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "%s opkodunun sınıfları yok (ops %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "\"%s\" dizinine geçilemedi, hatano = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "FR iÅŸlenen slotunda W anahtar kelimesi geçersiz." + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "görece(IP) geçerli biçimde deÄŸil" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) görecesi aralık dışı." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) görece aralık dışı." + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "parantezlerin geçersiz kullanımı" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "kapsam dışı iÅŸlenen (1 ve 255 arasında deÄŸil)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: geçersiz opindeks." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Bayt adresi gerekli. - çift sayı olmalı." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address bir sembol döndürdü. Sabit gerekli." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "%operator iÅŸleneni sembol deÄŸil" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "0'ın bit indeksini bulma denemesi" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "ÅŸimdiki deÄŸer yazmaç olamaz" + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "ÅŸimdiki deÄŸer kapsam dışı" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "21 bit görece deÄŸer aralık dışı" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "eksik `)'" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "bilinmeyen\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "bilinmeyen\t0x%04lx" + +#: m10300-dis.c:766 +#, c-format +msgid "unknown\t0x%04x" +msgstr "bilinmeyen\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "\n" +msgstr "\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "" +msgstr "" + +#: m88k-dis.c:746 +#, c-format +msgid "# " +msgstr "# <`dis' hatası: %08x>" + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# iç hata, eksik uzatma dizisi (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# iç hata, tanımlanmamış uzatma dizisi (+%c)" + +#: mips-dis.c:1000 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "#iç hata, tanımlanmamış deÄŸiÅŸtirici (%c)" + +#: mips-dis.c:1751 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "#iç karşıt-çevirici hatası, tanımlanmamış deÄŸiÅŸtirici (%c)" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"AÅŸağıdaki MIPS'e özgü karşıt-çevirici seçenekleri \n" +"-M seçeneÄŸi ile kullanılabilir (birden fazla seçenek virgülle ayrılmalıdır):\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI Belirtilen ABI'ye göre GPR isimlerini gösterir.\n" +" Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Belirtilen ABI'ye göre FPR isimlerini gösterir.\n" +" Öntanımlı: sayısal.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=MÄ°MARÄ° Belirtilen mimariye göre CP0 yazmaç isimlerini\n" +" gösterir.\n" +" Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=MÄ°MARÄ° Belirtilen mimariye göre HWR isimlerini gösterir.\n" +" Öntanımlı: karşıt-çevrilen ikilik dosyaya göre.\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Belirtilen ABI'ye göre GPR ve FPR isimlerini\n" +" gösterir.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=MÄ°MARÄ° Belirtilen mimariye göre CP0 yazmaç ve HWR\n" +" isimlerini gösterir.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Yukarıdaki seçeneklere göre \"ABI\" için aÅŸağıdaki deÄŸerler desteklenir:\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Yukarıdaki seçeneklere göre \"ARCH\" için aÅŸağıdaki deÄŸerler desteklenir:\n" +" " + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Hatalı durum %d (%s), %s içerisinde:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "İç Hata: Hata ayıklanmamış kod (test eksik): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(bilinmeyen)" + +#: mmix-dis.c:519 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "bilinmeyen iÅŸlenen türü: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +msgid "$" +msgstr "$" + +#: ppc-opc.c:781 ppc-opc.c:809 +msgid "invalid conditional option" +msgstr "koÅŸullu seçenek geçersiz " + +#: ppc-opc.c:811 +msgid "attempt to set y bit when using + or - modifier" +msgstr "+ veya - deÄŸiÅŸtiricisini kullanırken y bitini atama denemesi" + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "görece 16'nın katı deÄŸil" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "görece 2'nin katı deÄŸil" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "görece 62'den büyük" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 +msgid "offset not a multiple of 4" +msgstr "görece 4'ün katı deÄŸil" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "görece 124'ten büyük" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "görece 8'in katı deÄŸil" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "görece 248'den büyük" + +#: ppc-opc.c:950 +msgid "offset not between -2048 and 2047" +msgstr "görece -2048 ve 2047 arasında deÄŸil" + +#: ppc-opc.c:973 +msgid "offset not between -8192 and 8191" +msgstr "görece -8192 ve 8191 arasında deÄŸil" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "geçersiz mfcr maskesi yoksayıldı" + +#: ppc-opc.c:1059 +msgid "ignoring least significant bits in branch offset" +msgstr "Dal göreli konumunda en önemsiz bitler atlanıyor" + +#: ppc-opc.c:1090 ppc-opc.c:1125 +msgid "illegal bitmask" +msgstr "geçersiz bitmask " + +#: ppc-opc.c:1192 +msgid "value out of range" +msgstr "deÄŸer aralık dışı" + +#: ppc-opc.c:1262 +msgid "index register in load range" +msgstr "yükleme aralığında endeks yazmacı" + +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "kaynak ve hedef yazmaç iÅŸlenenleri farklı olmalı" + +#: ppc-opc.c:1294 +msgid "invalid register operand when updating" +msgstr "güncelleme esnasında geçersiz yazmaç terimi bulundu" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "hedef yazmaç iÅŸleneni çift sayı olmalı" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "kaynak yazmaç iÅŸleneni çift sayı olmalı" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "bilinmeyen" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:895 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\" == \"%s\"\n" + +#: v850-dis.c:221 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "bilinmeyen terim kaydırması: %x\n" + +#: v850-dis.c:233 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "bilinmeyen çek yazmacı: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "yer deÄŸiÅŸtirme deÄŸeri kapsam dışında ve hizalanmamış" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "yer deÄŸiÅŸtirme deÄŸeri kapsam dışında" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "yer deÄŸiÅŸtirme deÄŸeri hizalanmamış" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "ÅŸimdiki deÄŸer kapsam dışı" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "dal deÄŸeri kapsam dışında ve tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "dal deÄŸeri kapsam dışında " + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "dallanma tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "dal deÄŸeri kapsam dışında ve tek sayılı göreli konuma iÅŸaret ediyor" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "yığıt düzeltmesi için geçersiz yazmaç " + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "ÅŸimdiki deÄŸer kapsam dışı ve çift sayı deÄŸil" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "ÅŸimdiki deÄŸer çift sayı olmalı" + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "Arttırma öncesinde geçersiz yazmaç" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "Arttırma sonrasında geçersiz yazmaç " + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "Geçersiz yazmaç adı" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "Etiket, yazmaç adıyla çakışıyor" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "Etiket, `Rx' ile çakışıyor" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "Hatalı ÅŸimdiki ifade" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Küçük ÅŸimdiki için yerdeÄŸiÅŸtirme yok" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "Küçük iÅŸlenen ÅŸimdiki sayı deÄŸil" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Ä°ÅŸlenen bir sembol deÄŸil" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Sözdizim hatası: Sonlandıran ')' yok" diff --git a/external/gpl3/gdb/dist/opcodes/po/vi.gmo b/external/gpl3/gdb/dist/opcodes/po/vi.gmo new file mode 100644 index 0000000000000000000000000000000000000000..28974e4c82ba6c15fe58492472b920a065748603 GIT binary patch literal 27675 zcmd6v3!L0lmFKUkj;6&yUMh(2htQ;(q&nT5SJQcr_d^oMBmo4(P+j%!t|HY{MLm*k zbPxs=S>)xDEV7VfGYA+Ur~{;B*`)z>Ty~t%86Pvw+M@H)Vb_lUp;3}F80s6K!$9p;ECX! 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Do we have a limm already? +#: arc-opc.c:781 +msgid "impossible store" +msgstr "việc cất giữ không thể" + +#: arc-opc.c:814 +msgid "st operand error" +msgstr "lá»—i cất giữ tác tá»­" + +#: arc-opc.c:818 arc-opc.c:860 +msgid "address writeback not allowed" +msgstr "không cho phép ghi lùi địa chỉ" + +#: arc-opc.c:822 +msgid "store value must be zero" +msgstr "giá trị cất giữ phải là số không" + +#: arc-opc.c:847 +msgid "invalid load/shimm insn" +msgstr "câu lệnh nạp/shimm không hợp lệ" + +#: arc-opc.c:856 +msgid "ld operand error" +msgstr "lá»—i nạp tác tá»­" + +#: arc-opc.c:943 +msgid "jump flags, but no .f seen" +msgstr "có cá» nhảy, mà không thấy .f" + +#: arc-opc.c:946 +msgid "jump flags, but no limm addr" +msgstr "có cá» nhảy, mà không có địa chỉ limm" + +#: arc-opc.c:949 +msgid "flag bits of jump address limm lost" +msgstr "mất các bit cá» của limm địa chỉ nhảy" + +#: arc-opc.c:952 +msgid "attempt to set HR bits" +msgstr "thá»­ đặt các bit HR" + +#: arc-opc.c:955 +msgid "bad jump flags value" +msgstr "giá trị cá» nhảy sai" + +#: arc-opc.c:988 +msgid "branch address not on 4 byte boundary" +msgstr "địa chỉ nhánh không phải nằm trên ranh giá»›i 4 byte" + +#: arc-opc.c:1024 +msgid "must specify .jd or no nullify suffix" +msgstr "phải xác định .jd, không thì không hủy bá» hậu phÆ°Æ¡ng" + +#: arm-dis.c:1915 +msgid "" +msgstr "<Ä‘á»™ chính xác cấm>" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4018 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Không nhận ra tập hợp tên thanh ghi: %s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:4026 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Không nhận ra tùy chá»n rã: %s\n" + +#: arm-dis.c:4522 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Những tùy chá»n rã đặc trÆ°ng cho ARM theo đây được há»— trợ để sá»­ dụng vá»›i đối số « -M »:\n" + +#: avr-dis.c:115 avr-dis.c:125 +#, c-format +msgid "undefined" +msgstr "chÆ°a xác định" + +#: avr-dis.c:187 +#, c-format +msgid "Internal disassembler error" +msgstr "lá»—i rã ná»™i bá»™" + +#: avr-dis.c:236 +#, c-format +msgid "unknown constraint `%c'" +msgstr "không rõ ràng buá»™c « %c »" + +#: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200 +#: iq2000-ibld.c:200 lm32-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 +#: mep-ibld.c:200 mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 +#: xstormy16-ibld.c:200 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "tác tá»­ ở ngoại phạm vi (%ld không nằm giữa %ld và %ld)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "tác tá»­ ở ngoại phạm vi (%lu không nằm giữa %lu và %lu)" + +#: d30v-dis.c:255 +#, c-format +msgid "" +msgstr "" + +#. Can't happen. +#: dis-buf.c:59 +#, c-format +msgid "Unknown error %d\n" +msgstr "Lá»—i không rõ %d\n" + +#: dis-buf.c:68 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "Äịa chỉ 0x%s ở ngoại phạm vi. \n" + +#: fr30-asm.c:93 m32c-asm.c:877 m32c-asm.c:884 +msgid "Register number is not valid" +msgstr "Số thanh ghi không hợp lệ" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "Thanh ghi phải nằm giữa r0 và r7" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "Thanh ghi phải nằm giữa r8 và r15" + +#: fr30-asm.c:116 m32c-asm.c:915 +msgid "Register list is not valid" +msgstr "Danh sách thanh ghi không hợp lệ" + +#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 +#: lm32-asm.c:349 m32c-asm.c:1589 m32r-asm.c:328 mep-asm.c:1287 mt-asm.c:595 +#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi phân tách.\n" + +#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 +#: lm32-asm.c:400 m32c-asm.c:1640 m32r-asm.c:379 mep-asm.c:1338 mt-asm.c:646 +#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +msgid "missing mnemonic in syntax string" +msgstr "thiếu Ä‘iá»u giúp trí nhá»› trong chuá»—i cú pháp" + +#. We couldn't parse it. +#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:587 fr30-asm.c:688 frv-asm.c:1449 +#: frv-asm.c:1453 frv-asm.c:1540 frv-asm.c:1641 ip2k-asm.c:697 ip2k-asm.c:701 +#: ip2k-asm.c:788 ip2k-asm.c:889 iq2000-asm.c:645 iq2000-asm.c:649 +#: iq2000-asm.c:736 iq2000-asm.c:837 lm32-asm.c:535 lm32-asm.c:539 +#: lm32-asm.c:626 lm32-asm.c:727 m32c-asm.c:1775 m32c-asm.c:1779 +#: m32c-asm.c:1866 m32c-asm.c:1967 m32r-asm.c:514 m32r-asm.c:518 +#: m32r-asm.c:605 m32r-asm.c:706 mep-asm.c:1473 mep-asm.c:1477 mep-asm.c:1564 +#: mep-asm.c:1665 mt-asm.c:781 mt-asm.c:785 mt-asm.c:872 mt-asm.c:973 +#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:518 openrisc-asm.c:619 +#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:653 xc16x-asm.c:754 +#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:553 +#: xstormy16-asm.c:654 +msgid "unrecognized instruction" +msgstr "không nhận ra câu lệnh" + +#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 +#: lm32-asm.c:582 m32c-asm.c:1822 m32r-asm.c:561 mep-asm.c:1520 mt-asm.c:828 +#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "gặp lá»—i cú pháp (mong đợi ký tá»± « %c », còn tìm « %c »)" + +#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 +#: lm32-asm.c:592 m32c-asm.c:1832 m32r-asm.c:571 mep-asm.c:1530 mt-asm.c:838 +#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "gặp lá»—i cú pháp (ngá» ký tá»± « %c », còn tìm kết thúc câu lệnh)" + +#: fr30-asm.c:581 frv-asm.c:1534 ip2k-asm.c:782 iq2000-asm.c:730 +#: lm32-asm.c:620 m32c-asm.c:1860 m32r-asm.c:599 mep-asm.c:1558 mt-asm.c:866 +#: openrisc-asm.c:512 xc16x-asm.c:647 xstormy16-asm.c:547 +msgid "junk at end of line" +msgstr "gặp rác tại kết thúc dòng" + +#: fr30-asm.c:687 frv-asm.c:1640 ip2k-asm.c:888 iq2000-asm.c:836 +#: lm32-asm.c:726 m32c-asm.c:1966 m32r-asm.c:705 mep-asm.c:1664 mt-asm.c:972 +#: openrisc-asm.c:618 xc16x-asm.c:753 xstormy16-asm.c:653 +msgid "unrecognized form of instruction" +msgstr "không nhận ra dạng câu lệnh" + +#: fr30-asm.c:699 frv-asm.c:1652 ip2k-asm.c:900 iq2000-asm.c:848 +#: lm32-asm.c:738 m32c-asm.c:1978 m32r-asm.c:717 mep-asm.c:1676 mt-asm.c:984 +#: openrisc-asm.c:630 xc16x-asm.c:765 xstormy16-asm.c:665 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "câu lệnh sai « %.50s »" + +#: fr30-asm.c:702 frv-asm.c:1655 ip2k-asm.c:903 iq2000-asm.c:851 +#: lm32-asm.c:741 m32c-asm.c:1981 m32r-asm.c:720 mep-asm.c:1679 mt-asm.c:987 +#: openrisc-asm.c:633 xc16x-asm.c:768 xstormy16-asm.c:668 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "câu lệnh sai « %.50s »" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 +#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 +#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "• không rõ •" + +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 +#: m32c-dis.c:891 m32r-dis.c:256 mep-dis.c:1192 mt-dis.c:290 +#: openrisc-dis.c:135 xc16x-dis.c:375 xstormy16-dis.c:168 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi in ra câu lệnh.\n" + +#: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163 +#: lm32-ibld.c:163 m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 +#: mt-ibld.c:163 openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "tác tá»­ ở ngoại phạm vi (%ld không nằm giữa %ld và %lu)" + +#: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184 +#: lm32-ibld.c:184 m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 +#: mt-ibld.c:184 openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184 +#, c-format +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" +msgstr "tác tá»­ ở ngoại phạm vi (0x%lx không nằm giữa 0 và 0x%lx)" + +#: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709 +#: lm32-ibld.c:630 m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1204 +#: mt-ibld.c:745 openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi xây dá»±ng câu lệnh.\n" + +#: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884 +#: lm32-ibld.c:734 m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1803 +#: mt-ibld.c:965 openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi giải mã câu lệnh.\n" + +#: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015 +#: lm32-ibld.c:823 m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:2273 +#: mt-ibld.c:1165 openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi lấy tác tá»­ số nguyên.\n" + +#: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128 +#: lm32-ibld.c:894 m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2725 +#: mt-ibld.c:1347 openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi lấy tác tá»­ vma.\n" + +#: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248 +#: lm32-ibld.c:972 m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:3138 +#: mt-ibld.c:1536 openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi đặt tác tá»­ số nguyên.\n" + +#: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358 +#: lm32-ibld.c:1040 m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:3541 +#: mt-ibld.c:1715 openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Không nhận ra trÆ°á»ng %d trong khi đặt tác tá»­ vma.\n" + +#: frv-asm.c:608 +msgid "missing `]'" +msgstr "thiếu dấu ngoặc vụ đóng « ] »" + +#: frv-asm.c:611 frv-asm.c:621 +msgid "Special purpose register number is out of range" +msgstr "Số thanh ghi mục đích đặc biệt ở ngoại phạm vi" + +#: frv-asm.c:908 +msgid "Value of A operand must be 0 or 1" +msgstr "Giá trị của tác tá»­ A phải là 0 hay 1" + +#: frv-asm.c:944 +msgid "register number must be even" +msgstr "số thanh ghi phải là số chẵn" + +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 +#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:141 m32c-asm.c:237 +#: m32c-asm.c:279 m32c-asm.c:338 m32c-asm.c:360 m32r-asm.c:53 mep-asm.c:241 +#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" +msgstr "thiếu dấu ngoặc đóng « ) »" + +#: h8300-dis.c:327 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Ừm 0x%x" + +#: h8300-dis.c:708 +#, c-format +msgid "Don't understand 0x%x \n" +msgstr "Không hiểu 0x%x \n" + +#: h8500-dis.c:124 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "không thể xá»­ lý Ä‘iá»u chèn %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:324 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t • không rõ •" + +#: i386-dis.c:8924 +msgid "" +msgstr "" + +#: i386-dis.c:9155 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Những tùy chá»n rã đặc trÆ°ng cho i386/x86-64 theo đây được há»— trợ\n" +"để sá»­ dụng vá»›i đối số « -M » (phân cách nhiá»u tùy chá»n bằng dấu phẩy):\n" + +#: i386-dis.c:9159 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr " x86-64 Rã trong chế Ä‘á»™ 64-bit\n" + +#: i386-dis.c:9160 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr " i386 Rã trong chế Ä‘á»™ 32-bit\n" + +#: i386-dis.c:9161 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr " i8086 Rã trong chế Ä‘á»™ 16-bit\n" + +#: i386-dis.c:9162 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr " att Hiển thị câu lệnh theo cú pháp AT&T\n" + +#: i386-dis.c:9163 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr " intel Hiển thị câu lệnh theo cú pháp Intel\n" + +#: i386-dis.c:9164 +#, c-format +msgid "" +" att-mnemonic\n" +" Display instruction in AT&T mnemonic\n" +msgstr "" +" att-mnemonic\n" +" Hiển thị câu lệnh theo Ä‘iá»u giúp trí nhá»› AT&T\n" + +#: i386-dis.c:9166 +#, c-format +msgid "" +" intel-mnemonic\n" +" Display instruction in Intel mnemonic\n" +msgstr "" +" intel-mnemonic\n" +" Hiển thị câu lệnh theo Ä‘iá»u giúp trí nhá»› Intel\n" + +#: i386-dis.c:9168 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr " addr64 Giả sá»­ kích cỡ địa chỉ 64-bit\n" + +#: i386-dis.c:9169 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr " addr32 Giả sá»­ kích cỡ địa chỉ 32-bit\n" + +#: i386-dis.c:9170 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr " addr16 Giả sá»­ kích cỡ địa chỉ 16-bit\n" + +#: i386-dis.c:9171 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr " data32 Giả sá»­ kích cỡ dữ liệu 32-bit\n" + +#: i386-dis.c:9172 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr " data16 Giả sá»­ kích cỡ dữ liệu 16-bit\n" + +#: i386-dis.c:9173 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr " suffix Luôn luôn hiển thị hậu tố câu lệnh theo cú pháp AT&T\n" + +#: i386-gen.c:435 ia64-gen.c:307 +#, c-format +msgid "%s: Error: " +msgstr "%s: Lá»—i: " + +#: i386-gen.c:544 +#, c-format +msgid "%s: %d: Unknown bitfield: %s\n" +msgstr "%s: %d: Không rõ trÆ°á»ng bit: %s\n" + +#: i386-gen.c:546 +#, c-format +msgid "Unknown bitfield: %s\n" +msgstr "Không rõ trÆ°á»ng bit: %s\n" + +#: i386-gen.c:602 +#, c-format +msgid "%s: %d: Missing `)' in bitfield: %s\n" +msgstr "%s: %d: Thiếu « ) » trong trÆ°á»ng bit: %s\n" + +#: i386-gen.c:867 +#, c-format +msgid "can't find i386-opc.tbl for reading, errno = %s\n" +msgstr "không tìm thấy i386-opc.tbl để Ä‘á»c; số thứ tá»± lá»—i = %s\n" + +#: i386-gen.c:998 +#, c-format +msgid "can't find i386-reg.tbl for reading, errno = %s\n" +msgstr "không tìm thấy i386-reg.tbl để Ä‘á»c; số thứ tá»± lá»—i = %s\n" + +#: i386-gen.c:1075 +#, c-format +msgid "can't create i386-init.h, errno = %s\n" +msgstr "không thể tạo i386-init.h, số thứ tá»± lá»—i = %s\n" + +#: i386-gen.c:1164 ia64-gen.c:2820 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "không thể chuyển đổi thÆ° mục sang « %s », số lá»—i = %s\n" + +#: i386-gen.c:1171 +#, c-format +msgid "%d unused bits in i386_cpu_flags.\n" +msgstr "%d bit chÆ°a dùng trong i386_cpu_flags.\n" + +#: i386-gen.c:1178 +#, c-format +msgid "%d unused bits in i386_operand_type.\n" +msgstr "%d bit chÆ°a dùng trong i386_operand_type.\n" + +#: i386-gen.c:1192 +#, c-format +msgid "can't create i386-tbl.h, errno = %s\n" +msgstr "không thể tạo i386-tbl.h, số thứ tá»± lá»—i = %s\n" + +#: ia64-gen.c:320 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Cảnh báo : " + +#: ia64-gen.c:506 ia64-gen.c:737 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "không xá»­ lý được Ä‘a ghi chú %s\n" + +#: ia64-gen.c:617 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "không tìm thấy ia64-ic.tbl để Ä‘á»c\n" + +#: ia64-gen.c:819 +#, c-format +msgid "can't find %s for reading\n" +msgstr "không tìm thấy %s để Ä‘á»c\n" + +#: ia64-gen.c:1043 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" +"định dạng vừa nhất « %s »\n" +"có vẻ hạn hẹp hÆ¡n « %s »\n" + +#: ia64-gen.c:1054 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "trÆ°á»ng chồng lấp %s -> %s\n" + +#: ia64-gen.c:1251 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "Ä‘ang ghi đè lên ghi chú %d bằng ghi chú %d (IC:%s)\n" + +#: ia64-gen.c:1456 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "không biết cách ghi rõ %% quan hệ phụ thuá»™c %s\n" + +#: ia64-gen.c:1478 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Không biết cách ghi rõ # quan hệ phụ thuá»™c %s\n" + +#: ia64-gen.c:1517 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] không có Ä‘iá»u mở rá»™ng hoàn thành hay hạng con\n" + +#: ia64-gen.c:1520 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s không có Ä‘iá»u mở rá»™ng hoàn thành hay hạng con\n" + +#: ia64-gen.c:1529 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "không có câu lệnh được ánh xạ trá»±c tiếp vào IC mở rá»™ng hoàn thành %s [%s]" + +#: ia64-gen.c:1532 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "không có câu lệnh được ánh xạ trá»±c tiếp vào IC mở rá»™ng hoàn thành %s\n" + +#: ia64-gen.c:1543 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "hạng %s được xác định nhÆ°ng chÆ°a được dùng\n" + +#: ia64-gen.c:1556 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks\n" +msgstr "Cảnh báo : rsrc %s (%s) không có chks\n" + +#: ia64-gen.c:1559 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks or regs\n" +msgstr "Cảnh báo : rsrc %s (%s) không có chks hay regs\n" + +#: ia64-gen.c:1563 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "Tài nguyên %s (%s) không có regs\n" + +#: ia64-gen.c:2455 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Ghi chú IC %d trong opcode (mã thao tác) %s (IC:%s) thì xung Ä‘á»™t vá»›i tài nguyên %s ghi chú %d\n" + +#: ia64-gen.c:2483 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "Ghi chú IC %d cho opcode (mã thao tác) %s (IC:%s) thì xung Ä‘á»™t vá»›i tài nguyên %s ghi chú %d\n" + +#: ia64-gen.c:2497 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "opcode (mã thao tác) %s không có hạng (những tác tá»­ %d %d %d)\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:81 +msgid "W keyword invalid in FR operand slot." +msgstr "Tá»­ khoá W không hợp lệ trong khe tác tá»­ FR." + +#. Invalid offset present. +#: ip2k-asm.c:106 +msgid "offset(IP) is not a valid form" +msgstr "offset(IP) (hiệu số) không có dạng hợp lệ" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:154 +msgid "(DP) offset out of range." +msgstr "(DP) hiệu ở ngoại phạm vi." + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:195 +msgid "(SP) offset out of range." +msgstr "(SP) hiệu ở ngoại phạm vi." + +#: ip2k-asm.c:211 +msgid "illegal use of parentheses" +msgstr "không cho phép cách sá»­ dụng dấu ngoặc" + +#: ip2k-asm.c:218 +msgid "operand out of range (not between 1 and 255)" +msgstr "tác tá»­ ở ngoại phạm vi (không nằm giữa 1 và 255)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:242 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: (địa chỉ phân tách) opindex (chỉ mục kiểu tác tá»­) không hợp lệ." + +#: ip2k-asm.c:296 +msgid "Byte address required. - must be even." +msgstr "Cần thiết địa chỉ byte: phải là số chẵn." + +#: ip2k-asm.c:305 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address (địa chỉ phân tách cgen) đã trả lại má»™t ký hiệu : còn cần thiết Ä‘iá»u nghÄ©a chữ." + +#: ip2k-asm.c:360 +msgid "percent-operator operand is not a symbol" +msgstr "toán tá»­ tác tá»­ phần trăm không phải là má»™t ký hiệu" + +#: ip2k-asm.c:413 +msgid "Attempt to find bit index of 0" +msgstr "Thá»­ tìm ra chỉ mục bit của số 0" + +#: iq2000-asm.c:112 iq2000-asm.c:142 +msgid "immediate value cannot be register" +msgstr "giá trị trá»±c tiếp không thể là thanh ghi" + +#: iq2000-asm.c:123 iq2000-asm.c:153 lm32-asm.c:70 +msgid "immediate value out of range" +msgstr "giá trị trá»±c tiếp ở ngoại pham vi" + +#: iq2000-asm.c:182 +msgid "21-bit offset out of range" +msgstr "hiệu 21-bit ở ngoại phạm vi" + +#: lm32-asm.c:166 +msgid "expecting gp relative address: gp(symbol)" +msgstr "mong đợi địa chỉ tÆ°Æ¡ng đối vá»›i gp: gp(ký_hiệu)" + +#: lm32-asm.c:196 +msgid "expecting got relative address: got(symbol)" +msgstr "mong đợi địa chỉ tÆ°Æ¡ng đối vá»›i got: got(ký_hiệu)" + +#: lm32-asm.c:226 +msgid "expecting got relative address: gotoffhi16(symbol)" +msgstr "mong đợi địa chỉ tÆ°Æ¡ng đối vá»›i got: gotoffhi16(ký_hiệu)" + +#: lm32-asm.c:256 +msgid "expecting got relative address: gotofflo16(symbol)" +msgstr "mong đợi địa chỉ tÆ°Æ¡ng đối vá»›i got: gotofflo16(ký_hiệu)" + +#: m10200-dis.c:158 m10300-dis.c:582 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "không rõ\t0x%04lx" + +#: m10200-dis.c:328 +#, c-format +msgid "unknown\t0x%02lx" +msgstr "không rõ\t0x%02lx" + +#: m32c-asm.c:117 +msgid "imm:6 immediate is out of range" +msgstr "Ä‘iá»u ngay « imm:6 » ở ngoại phạm vi" + +#: m32c-asm.c:147 +#, c-format +msgid "%dsp8() takes a symbolic address, not a number" +msgstr "%dsp8() chấp nhận địa chỉ tÆ°Æ¡ng trÆ°ng, không phải con số" + +#: m32c-asm.c:160 m32c-asm.c:164 m32c-asm.c:255 +msgid "dsp:8 immediate is out of range" +msgstr "Ä‘iá»u ngay « dsp:8 » ở ngoại phạm vi" + +#: m32c-asm.c:185 m32c-asm.c:189 +msgid "Immediate is out of range -8 to 7" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi -8 đến +7" + +#: m32c-asm.c:210 m32c-asm.c:214 +msgid "Immediate is out of range -7 to 8" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi -7 đến +8" + +#: m32c-asm.c:285 +#, c-format +msgid "%dsp16() takes a symbolic address, not a number" +msgstr "%dsp16() chấp nhận địa chỉ tÆ°Æ¡ng trÆ°ng, không phải con số" + +#: m32c-asm.c:308 m32c-asm.c:315 m32c-asm.c:378 +msgid "dsp:16 immediate is out of range" +msgstr "Ä‘iá»u ngay « dsp:16 » ở ngoại phạm vi" + +#: m32c-asm.c:404 +msgid "dsp:20 immediate is out of range" +msgstr "Ä‘iá»u ngay « dsp:20 » ở ngoại phạm vi" + +#: m32c-asm.c:430 m32c-asm.c:450 +msgid "dsp:24 immediate is out of range" +msgstr "Ä‘iá»u ngay « dsp:24 » ở ngoại phạm vi" + +#: m32c-asm.c:483 +msgid "immediate is out of range 1-2" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi 1-2" + +#: m32c-asm.c:501 +msgid "immediate is out of range 1-8" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi 1-8" + +#: m32c-asm.c:519 +msgid "immediate is out of range 0-7" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi 0-7" + +#: m32c-asm.c:555 +msgid "immediate is out of range 2-9" +msgstr "Ä‘iá»u ngay ở ngoại phạm vi 2-9" + +#: m32c-asm.c:573 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "Số bit để phụ lục thanh ghi chung nằm ở ngoại phạm vi 0-15" + +#: m32c-asm.c:611 m32c-asm.c:667 +msgid "bit,base is out of range" +msgstr "« bit,base » ở ngoại phạm vi" + +#: m32c-asm.c:618 m32c-asm.c:623 m32c-asm.c:671 +msgid "bit,base out of range for symbol" +msgstr "« bit,base » ở ngoại phạm vi đối vá»›i ký hiệu" + +#: m32c-asm.c:807 +msgid "not a valid r0l/r0h pair" +msgstr "không phải là má»™t cặp « r0l/r0h » hợp lệ" + +#: m32c-asm.c:837 +msgid "Invalid size specifier" +msgstr "đặc tả kích cỡ không hợp lệ" + +#: m68k-dis.c:1278 +#, c-format +msgid "" +msgstr "" + +#: m68k-dis.c:1437 +#, c-format +msgid "\n" +msgstr "\n" + +#: m88k-dis.c:679 +#, c-format +msgid "# " +msgstr "# " + +#: mep-asm.c:129 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "Chỉ cho phép $tp hay $13 cho mã thao tác này" + +#: mep-asm.c:143 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "Chỉ cho phép $sp hay $15 cho mã thao tác này" + +#: mep-asm.c:308 mep-asm.c:504 +#, c-format +msgid "invalid %function() here" +msgstr "hàm %function() không hợp lệ ở đây" + +#: mep-asm.c:336 +msgid "Immediate is out of range -32768 to 32767" +msgstr "Äiá»u ngay ở ngoại phạm vi -32768 đến 32767" + +#: mep-asm.c:356 +msgid "Immediate is out of range 0 to 65535" +msgstr "Äiá»u ngay ở ngoại phạm vi 0 đến 65535" + +#: mep-asm.c:549 mep-asm.c:562 +msgid "Immediate is out of range -512 to 511" +msgstr "Äiá»u ngay ở ngoại phạm vi -512 đến 511" + +#: mep-asm.c:554 mep-asm.c:563 +msgid "Immediate is out of range -128 to 127" +msgstr "Äiá»u ngay ở ngoại phạm vi -128 đến 127" + +#: mep-asm.c:558 +msgid "Value is not aligned enough" +msgstr "Giá trị chÆ°a đủ sắp hàng" + +#: mips-dis.c:841 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# lá»—i ná»™i bá»™, dãy mở rá»™ng chÆ°a hoàn thành (+)" + +#: mips-dis.c:975 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# lá»—i ná»™i bá»™, chÆ°a xác định dãy mở rá»™ng (+%c)" + +#: mips-dis.c:1335 +#, c-format +msgid "# internal error, undefined modifier (%c)" +msgstr "# lá»—i ná»™i bá»™, chÆ°a xác định Ä‘iá»u sá»­a đổi (%c)" + +#: mips-dis.c:1942 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# lá»—i rã ná»™i bá»™, không nhận ra Ä‘iá»u sá»­a đổi (%c)" + +#: mips-dis.c:2173 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Nững tùy chá»n rã đặc trÆ°ng cho MIPS theo đây được há»— trợ để sá»­ dụng\n" +"vá»›i đối số « -M » (phân cách nhiá»u tùy chá»n bằng dấu phẩy):\n" + +#: mips-dis.c:2177 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI In ra các tên GPR theo ABI đã ghi rõ.\n" +" Mặc định: dá»±a vào mã nhi phân Ä‘ang bị rã\n" + +#: mips-dis.c:2181 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI In ra các tên FPR theo ABI đã ghi rõ.\n" +" Mặc định: thuá»™c số\n" + +#: mips-dis.c:2185 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH In ra các tên CP0 theo kiến trúc đã ghi rõ\n" +" Mặc định: dá»±a vào mã nhi phân Ä‘ang bị rã.\n" + +#: mips-dis.c:2190 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH In ra các tên HWR theo kiến trúc đã ghi rõ.\n" +" Mặc định: dá»±a vào mã nhi phân Ä‘ang bị rã.\n" + +#: mips-dis.c:2195 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI In ra các tên GPR và FPR theo ABI đã ghi rõ.\n" + +#: mips-dis.c:2199 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH\n" +"\t In ra các tên HWR và thanh ghi CP0 theo kiến trúc đã ghi rõ.\n" + +#: mips-dis.c:2203 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Äối vá»›i các tùy chá»n trên, những giá trị theo đây được há»— trợ cho « ABI »:\n" +" " + +#: mips-dis.c:2208 mips-dis.c:2216 mips-dis.c:2218 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:2210 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Äối vá»›i các tùy chá»n trên, những giá trị theo đây được há»— trợ cho « ARCH »:\n" +" " + +#: mmix-dis.c:35 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Chữ hoa/thÆ°á»ng sai %d (%s) trong %s:%d\n" + +#: mmix-dis.c:45 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Ná»™i bá»™ : chÆ°a gỡ lá»—i mã (thiếu trÆ°á»ng hợp thá»­): %s:%d" + +#: mmix-dis.c:54 +msgid "(unknown)" +msgstr "(không rõ)" + +#: mmix-dis.c:513 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "• không rõ kiểu tác tá»­ : %d •" + +#: msp430-dis.c:327 +msgid "Illegal as emulation instr" +msgstr "Không được phép dÆ°á»›i dạng chỉ dẫn mô phá»ng" + +#. R2/R3 are illegal as dest: may be data section. +#: msp430-dis.c:378 +msgid "Illegal as 2-op instr" +msgstr "Không được phép dÆ°á»›i dạng chỉ dẫn 2-op" + +#: mt-asm.c:110 mt-asm.c:190 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "Tác tá»­ ở ngoại phạm vi (phải nằm giữa -32768 và +32767." + +#: mt-asm.c:149 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "Gặp lá»—i nghiêm trá»ng trong « parse_imm16 »." + +#: mt-asm.c:157 +msgid "The percent-operator's operand is not a symbol" +msgstr "Toán hạng của toán tá»­ phần trăm không phải là má»™t ký hiệu" + +#: mt-asm.c:395 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "tác tá»­ không hợp lệ. kiểu chỉ có thể có giá trị 0,1,2." + +#. I and Z are output operands and can`t be immediate +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:534 +#, c-format +msgid "$" +msgstr "$" + +#: ppc-dis.c:248 +#, c-format +msgid "warning: ignoring unknown -M%s option\n" +msgstr "cảnh báo : Ä‘ang bở qua tuỳ chá»n « -M%s » không rõ\n" + +#: ppc-dis.c:537 +#, c-format +msgid "" +"\n" +"The following PPC specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"Những tùy chá»n rã đặc trÆ°ng cho PPC theo đây được há»— trợ để sá»­ dụng vá»›i đối số « -M »:\n" + +#: ppc-opc.c:873 ppc-opc.c:901 +msgid "invalid conditional option" +msgstr "tùy chá»n Ä‘iá»u kiện không hợp lệ" + +#: ppc-opc.c:903 +msgid "attempt to set y bit when using + or - modifier" +msgstr "thá»­ đặt « bit y » khi sá»­ dụng Ä‘iá»u sá»­a đổi + hay -" + +#: ppc-opc.c:935 +msgid "invalid mask field" +msgstr "trÆ°á»ng mặt nạ không hợp lệ" + +#: ppc-opc.c:961 +msgid "ignoring invalid mfcr mask" +msgstr "Ä‘ang bá» qua mặt nạ mfcr không hợp lệ" + +#: ppc-opc.c:1011 ppc-opc.c:1046 +msgid "illegal bitmask" +msgstr "gặp mặt nặ bit cấm" + +#: ppc-opc.c:1166 +msgid "index register in load range" +msgstr "thanh ghi cÆ¡ số trong phạm vi nạp" + +#: ppc-opc.c:1182 +msgid "source and target register operands must be different" +msgstr "tác tá»­ thanh ghi kiểu nguồn và đích phải là khác nhau" + +#: ppc-opc.c:1197 +msgid "invalid register operand when updating" +msgstr "gặp tác tá»­ thanh ghi không hợp lệ khi cập nhật" + +#: ppc-opc.c:1276 +msgid "invalid sprg number" +msgstr "số sprg không hợp lệ" + +#: ppc-opc.c:1446 +msgid "invalid constant" +msgstr "hằng không hợp lệ" + +#: s390-dis.c:277 +#, c-format +msgid "" +"\n" +"The following S/390 specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Theo đây có những tùy chá»n rã đặc trÆ°ng cho S/390 được há»— trợ để sá»­ dụng\n" +"vá»›i đối số « -M » (phân cách nhiá»u tùy chá»n bằng dấu phẩy):\n" + +#: s390-dis.c:281 +#, c-format +msgid " esa Disassemble in ESA architecture mode\n" +msgstr " esa Rã ở chế Ä‘á»™ kiến trúc ESA\n" + +#: s390-dis.c:282 +#, c-format +msgid " zarch Disassemble in z/Architecture mode\n" +msgstr " zarch Rã ở chế Ä‘á»™ z/kiến trúc\n" + +#: score-dis.c:662 score-dis.c:869 score-dis.c:1030 score-dis.c:1144 +#: score-dis.c:1151 score-dis.c:1158 score7-dis.c:694 score7-dis.c:857 +msgid "" +msgstr "<Ä‘á»™ chính xác cấm>" + +#: sparc-dis.c:283 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Lá»—i ná»™i bá»™ : sparc-opcode.h sai: « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:294 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Lá»—i ná»™i bá»™ : sparc-opcode.h sai: « %s », %#.8lx, %#.8lx\n" + +#: sparc-dis.c:344 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Lá»—i ná»™i bá»™ : sparc-opcode.h sai: « %s » == \"%s\"\n" + +#. Mark as non-valid instruction. +#: sparc-dis.c:1014 +msgid "unknown" +msgstr "không rõ" + +#: v850-dis.c:239 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "không rõ sá»± dịch tác tá»­ : %x\n" + +#: v850-dis.c:253 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "không rõ pop reg: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:48 +msgid "displacement value is not in range and is not aligned" +msgstr "giá trị di chuyển ở ngoại phạm vi và chÆ°a được chỉnh canh" + +#: v850-opc.c:49 +msgid "displacement value is out of range" +msgstr "giá trị di chuyển ở ngoại phạm vi" + +#: v850-opc.c:50 +msgid "displacement value is not aligned" +msgstr "chÆ°a chỉnh canh giá trị di chuyển" + +#: v850-opc.c:52 +msgid "immediate value is out of range" +msgstr "giá trị trá»±c tiếp ở ngoại phạm vi" + +#: v850-opc.c:60 +msgid "branch value not in range and to odd offset" +msgstr "giá trị nhánh ở ngoại phạm vi và đối vá»›i hiệu số lẻ" + +#: v850-opc.c:62 v850-opc.c:89 +msgid "branch value out of range" +msgstr "giá trị nhánh ở ngoại phạm vi" + +#: v850-opc.c:65 v850-opc.c:92 +msgid "branch to odd offset" +msgstr "nhánh đối vá»›i hiệu số lẻ" + +#: v850-opc.c:87 +msgid "branch value not in range and to an odd offset" +msgstr "giá trị nhánh ở ngoại phạm vi và đối vá»›i hiệu số lẻ" + +#: v850-opc.c:279 +msgid "invalid register for stack adjustment" +msgstr "thanh ghi không hợp lệ để Ä‘iá»u chỉnh đống" + +#: v850-opc.c:299 +msgid "immediate value not in range and not even" +msgstr "giá trị trá»±c tiếp ở ngoạị phạm vi và không phải số chẵn" + +#: v850-opc.c:304 +msgid "immediate value must be even" +msgstr "giá trị trá»±c tiếp phải là số chẵn" + +#: xc16x-asm.c:66 +msgid "Missing '#' prefix" +msgstr "Thiếu tiá»n tố « # »" + +#: xc16x-asm.c:82 +msgid "Missing '.' prefix" +msgstr "Thiếu tiá»n tố « . »" + +#: xc16x-asm.c:98 +msgid "Missing 'pof:' prefix" +msgstr "Thiếu tiá»n tố « pof: »" + +#: xc16x-asm.c:114 +msgid "Missing 'pag:' prefix" +msgstr "Thiếu tiá»n tố « pag: »" + +#: xc16x-asm.c:130 +msgid "Missing 'sof:' prefix" +msgstr "Thiếu tiá»n tố « sof: »" + +#: xc16x-asm.c:146 +msgid "Missing 'seg:' prefix" +msgstr "Thiếu tiá»n tố « seg: »" + +#: xstormy16-asm.c:71 +msgid "Bad register in preincrement" +msgstr "Thanh ghi sai trong tiá»n lượng gia" + +#: xstormy16-asm.c:76 +msgid "Bad register in postincrement" +msgstr "Thanh ghi sai trong hậu lượng gia" + +#: xstormy16-asm.c:78 +msgid "Bad register name" +msgstr "Tên thanh ghi sai" + +#: xstormy16-asm.c:82 +msgid "Label conflicts with register name" +msgstr "Nhãn xung Ä‘á»™t vá»›i tên thanh ghi" + +#: xstormy16-asm.c:86 +msgid "Label conflicts with `Rx'" +msgstr "Nhãn xung Ä‘á»™t vá»›i « Rx »" + +#: xstormy16-asm.c:88 +msgid "Bad immediate expression" +msgstr "Biểu thức trá»±c tiếp sai" + +#: xstormy16-asm.c:109 +msgid "No relocation for small immediate" +msgstr "Không có sá»± định vị lại cho Ä‘iá»u nhá» ngay" + +#: xstormy16-asm.c:119 +msgid "Small operand was not an immediate number" +msgstr "Tác tá»­ nhá» không phải số ngay" + +#: xstormy16-asm.c:157 +msgid "Operand is not a symbol" +msgstr "Tác tá»­ không phải ký hiệu" + +#: xstormy16-asm.c:165 +msgid "Syntax error: No trailing ')'" +msgstr "Lá»—i cú pháp: không có dấu ngoặc đóng « ) » Ä‘i theo" diff --git a/external/gpl3/gdb/dist/opcodes/po/zh_CN.gmo b/external/gpl3/gdb/dist/opcodes/po/zh_CN.gmo new file mode 100644 index 0000000000000000000000000000000000000000..2bf6751c43556025e3d7a423ba3fc28f6f45bb15 GIT binary patch literal 9039 zcmcJSdvp}l9mlV)B8#o9*1lV>U`!%x*o22+4Jc2Eg2sqotF=saC!2xYneEK3B%Im? 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XXX - should break 'option' at following delimiter. +#: arm-dis.c:1912 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "无法识别的寄存器å称集：%s\n" + +#. XXX - should break 'option' at following delimiter. +#: arm-dis.c:1920 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "无法识别的å汇编器选项：%s\n" + +#: arm-dis.c:2093 +#, c-format +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"下列 ARM 特定的å汇编器选项在使用 -M 开关时å¯ç”¨ï¼š\n" + +#: avr-dis.c:112 avr-dis.c:122 +#, c-format +msgid "undefined" +msgstr "未定义" + +#: avr-dis.c:179 +#, c-format +msgid "Internal disassembler error" +msgstr "å汇编器内部错误" + +#: avr-dis.c:227 +#, c-format +msgid "unknown constraint `%c'" +msgstr "未知的约æŸâ€˜%c’" + +#: cgen-asm.c:336 fr30-ibld.c:197 frv-ibld.c:197 ip2k-ibld.c:197 +#: iq2000-ibld.c:197 m32r-ibld.c:197 openrisc-ibld.c:197 xstormy16-ibld.c:197 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "æ“作数越界(%ld ä¸åœ¨ %ld å’Œ %ld 之间)" + +#: cgen-asm.c:358 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "æ“作数越界(%lu ä¸åœ¨ %lu å’Œ %lu 之间)" + +#: d30v-dis.c:312 +#, c-format +msgid "" +msgstr "<未知的寄存器 %d>" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "未知错误 %d\n" + +#: dis-buf.c:66 +#, c-format +msgid "Address 0x%s is out of bounds.\n" +msgstr "åœ°å€ 0x%s 越界。\n" + +#: fr30-asm.c:323 frv-asm.c:1298 ip2k-asm.c:530 iq2000-asm.c:465 +#: m32r-asm.c:338 openrisc-asm.c:252 xstormy16-asm.c:284 +#, fuzzy, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "è¯æ³•åˆ†æžå­—段时出错\n" + +#: fr30-asm.c:372 frv-asm.c:1347 ip2k-asm.c:579 iq2000-asm.c:514 +#: m32r-asm.c:387 openrisc-asm.c:301 xstormy16-asm.c:333 +msgid "missing mnemonic in syntax string" +msgstr "语法字符串中没有助记符" + +#. We couldn't parse it. +#: fr30-asm.c:507 fr30-asm.c:511 fr30-asm.c:598 fr30-asm.c:699 frv-asm.c:1482 +#: frv-asm.c:1486 frv-asm.c:1573 frv-asm.c:1674 ip2k-asm.c:714 ip2k-asm.c:718 +#: ip2k-asm.c:805 ip2k-asm.c:906 iq2000-asm.c:649 iq2000-asm.c:653 +#: iq2000-asm.c:740 iq2000-asm.c:841 m32r-asm.c:522 m32r-asm.c:526 +#: m32r-asm.c:613 m32r-asm.c:714 openrisc-asm.c:436 openrisc-asm.c:440 +#: openrisc-asm.c:527 openrisc-asm.c:628 xstormy16-asm.c:468 +#: xstormy16-asm.c:472 xstormy16-asm.c:559 xstormy16-asm.c:660 +msgid "unrecognized instruction" +msgstr "无法识别的指令" + +#: fr30-asm.c:554 frv-asm.c:1529 ip2k-asm.c:761 iq2000-asm.c:696 +#: m32r-asm.c:569 openrisc-asm.c:483 xstormy16-asm.c:515 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "语法错误(需è¦å­—符‘%c’，得到‘%c’)" + +#: fr30-asm.c:564 frv-asm.c:1539 ip2k-asm.c:771 iq2000-asm.c:706 +#: m32r-asm.c:579 openrisc-asm.c:493 xstormy16-asm.c:525 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "语法错误(需è¦å­—符‘%c’，å´åˆ°è¾¾æŒ‡ä»¤å°¾)" + +#: fr30-asm.c:592 frv-asm.c:1567 ip2k-asm.c:799 iq2000-asm.c:734 +#: m32r-asm.c:607 openrisc-asm.c:521 xstormy16-asm.c:553 +msgid "junk at end of line" +msgstr "行尾有垃圾字符" + +#: fr30-asm.c:698 frv-asm.c:1673 ip2k-asm.c:905 iq2000-asm.c:840 +#: m32r-asm.c:713 openrisc-asm.c:627 xstormy16-asm.c:659 +msgid "unrecognized form of instruction" +msgstr "无法识别的指令格å¼" + +#: fr30-asm.c:710 frv-asm.c:1685 ip2k-asm.c:917 iq2000-asm.c:852 +#: m32r-asm.c:725 openrisc-asm.c:639 xstormy16-asm.c:671 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "错误的指令‘%.50s...’" + +#: fr30-asm.c:713 frv-asm.c:1688 ip2k-asm.c:920 iq2000-asm.c:855 +#: m32r-asm.c:728 openrisc-asm.c:642 xstormy16-asm.c:674 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "错误的指令‘%.50s’" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +msgid "*unknown*" +msgstr "*未知*" + +#: fr30-dis.c:319 frv-dis.c:410 ip2k-dis.c:313 iq2000-dis.c:191 m32r-dis.c:262 +#: openrisc-dis.c:137 xstormy16-dis.c:170 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "" + +#: fr30-ibld.c:168 frv-ibld.c:168 ip2k-ibld.c:168 iq2000-ibld.c:168 +#: m32r-ibld.c:168 openrisc-ibld.c:168 xstormy16-ibld.c:168 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "æ“作数越界(%ld ä¸åœ¨ %ld å’Œ %lu 之间)" + +#: fr30-ibld.c:181 frv-ibld.c:181 ip2k-ibld.c:181 iq2000-ibld.c:181 +#: m32r-ibld.c:181 openrisc-ibld.c:181 xstormy16-ibld.c:181 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "æ“作数越界(%lu ä¸åœ¨ 0 å’Œ %lu 之间)" + +#: fr30-ibld.c:732 frv-ibld.c:858 ip2k-ibld.c:609 iq2000-ibld.c:715 +#: m32r-ibld.c:667 openrisc-ibld.c:635 xstormy16-ibld.c:680 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "" + +#: fr30-ibld.c:939 frv-ibld.c:1177 ip2k-ibld.c:686 iq2000-ibld.c:892 +#: m32r-ibld.c:806 openrisc-ibld.c:737 xstormy16-ibld.c:828 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "" + +#: fr30-ibld.c:1088 frv-ibld.c:1458 ip2k-ibld.c:763 iq2000-ibld.c:1026 +#: m32r-ibld.c:922 openrisc-ibld.c:817 xstormy16-ibld.c:941 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1217 frv-ibld.c:1719 ip2k-ibld.c:820 iq2000-ibld.c:1140 +#: m32r-ibld.c:1018 openrisc-ibld.c:877 xstormy16-ibld.c:1034 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "" + +#: fr30-ibld.c:1351 frv-ibld.c:1989 ip2k-ibld.c:882 iq2000-ibld.c:1263 +#: m32r-ibld.c:1122 openrisc-ibld.c:946 xstormy16-ibld.c:1136 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "" + +#: fr30-ibld.c:1473 frv-ibld.c:2247 ip2k-ibld.c:932 iq2000-ibld.c:1374 +#: m32r-ibld.c:1214 openrisc-ibld.c:1003 xstormy16-ibld.c:1226 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "" + +#: frv-asm.c:978 +msgid "register number must be even" +msgstr "寄存器数必须是å¶æ•°" + +#: h8300-dis.c:358 +#, c-format +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" + +#: h8300-dis.c:744 +#, fuzzy, c-format +msgid "Don't understand 0x%x \n" +msgstr "ä¸ç†è§£ç±»åž‹â€œ%sâ€\n" + +#: h8500-dis.c:143 +#, fuzzy, c-format +msgid "can't cope with insert %d\n" +msgstr "用下列通é…符æ’入文件(&M)：" + +#. Couldn't understand anything. +#: h8500-dis.c:342 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*未知*" + +#: i386-dis.c:1733 +msgid "" +msgstr "<å汇编器内部错误>" + +#: ia64-gen.c:297 +#, c-format +msgid "%s: Error: " +msgstr "%s：错误：" + +#: ia64-gen.c:310 +#, c-format +msgid "%s: Warning: " +msgstr "%s：警告：" + +#: ia64-gen.c:496 ia64-gen.c:730 +#, fuzzy, c-format +msgid "multiple note %s not handled\n" +msgstr "æœªå¤„ç† move 指令" + +#: ia64-gen.c:607 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "" + +#: ia64-gen.c:812 +#, fuzzy, c-format +msgid "can't find %s for reading\n" +msgstr "无法打开 %1 进行读å–" + +#: ia64-gen.c:1036 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" + +#: ia64-gen.c:1047 +#, fuzzy, c-format +msgid "overlapping field %s->%s\n" +msgstr "域宽" + +#: ia64-gen.c:1244 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "" + +#: ia64-gen.c:1443 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "ä¸çŸ¥é“如何指定 %% ä¾èµ– %s\n" + +#: ia64-gen.c:1465 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "ä¸çŸ¥é“如何指定 # ä¾èµ– %s\n" + +#: ia64-gen.c:1504 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1507 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1516 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "" + +#: ia64-gen.c:1519 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "" + +#: ia64-gen.c:1530 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "" + +#: ia64-gen.c:1541 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "" + +#: ia64-gen.c:1545 +#, fuzzy, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "指数部分没有数字" + +#: ia64-gen.c:2444 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2472 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2486 +#, fuzzy, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "尚未定义å为“%sâ€çš„ " + +#: ia64-gen.c:2816 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "无法将当å‰ç›®å½•åˆ‡æ¢è‡³â€œ%sâ€ï¼Œerrno = %s\n" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "" + +#. Invalid offset present. +#: ip2k-asm.c:117 +msgid "offset(IP) is not a valid form" +msgstr "" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:165 +msgid "(DP) offset out of range." +msgstr "(DP) å移é‡è¶Šç•Œ" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:206 +msgid "(SP) offset out of range." +msgstr "(SP) å移é‡è¶Šç•Œã€‚" + +#: ip2k-asm.c:222 +msgid "illegal use of parentheses" +msgstr "括å·çš„使用éžæ³•" + +#: ip2k-asm.c:229 +#, fuzzy +msgid "operand out of range (not between 1 and 255)" +msgstr "æ“作数越界(%lu ä¸åœ¨ 0 å’Œ %lu 之间)" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:254 +#, fuzzy +msgid "parse_addr16: invalid opindex." +msgstr "分æžé”™è¯¯ï¼šéžæ³• UTF-8 åºåˆ—" + +#: ip2k-asm.c:309 +msgid "Byte address required. - must be even." +msgstr "" + +#: ip2k-asm.c:318 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "" + +#: ip2k-asm.c:376 +#, fuzzy, c-format +msgid "%operator operand is not a symbol" +msgstr "使用寄存器栈传递å‚数和返回值" + +#: ip2k-asm.c:430 +msgid "Attempt to find bit index of 0" +msgstr "" + +#: iq2000-asm.c:115 iq2000-asm.c:146 +msgid "immediate value cannot be register" +msgstr "ç«‹å³æ•°ä¸èƒ½æ˜¯å¯„存器" + +#: iq2000-asm.c:126 iq2000-asm.c:156 +msgid "immediate value out of range" +msgstr "ç«‹å³æ•°è¶Šç•Œ" + +#: iq2000-asm.c:185 +msgid "21-bit offset out of range" +msgstr "21ä½é•¿çš„å移é‡è¶Šç•Œ" + +#: iq2000-asm.c:210 iq2000-asm.c:240 iq2000-asm.c:277 iq2000-asm.c:310 +#: openrisc-asm.c:90 openrisc-asm.c:144 +msgid "missing `)'" +msgstr "缺少‘)’" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "未知\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "未知\t0x%04lx" + +#: m10300-dis.c:767 +#, c-format +msgid "unknown\t0x%04x" +msgstr "未知\t0x%04x" + +#: m68k-dis.c:295 +#, c-format +msgid "\n" +msgstr "<æ“作数表中出现内部错误：%s %s>\n" + +#: m68k-dis.c:1089 +#, c-format +msgid "" +msgstr "<å‡½æ•°ä»£ç  %d>" + +#: m88k-dis.c:746 +#, fuzzy, c-format +msgid "# " +msgstr "语法错误，éžé¢„期的 %s" + +#: mips-dis.c:720 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "" + +#: mips-dis.c:779 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "" + +#: mips-dis.c:1037 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# 内部错误，未定义的修饰符(%c)" + +#: mips-dis.c:1793 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + +#: mips-dis.c:1805 +#, c-format +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: mips-dis.c:1809 +#, c-format +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" gpr-names=ABI æ ¹æ®æŒ‡å®šçš„ ABI 打å°é€šç”¨å¯„存器å。\n" +" 默认：根æ®è¢«å汇编的二进制文件。\n" + +#: mips-dis.c:1813 +#, c-format +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI æ ¹æ®æŒ‡å®šçš„ ABI 打å°æµ®ç‚¹å¯„存器å。\n" +" 默认：数字。\n" + +#: mips-dis.c:1817 +#, c-format +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH æ ¹æ®æŒ‡å®šçš„æž¶æž„æ‰“å° CP0 寄存器å。\n" +" 默认：根æ®è¢«å汇编的二进制代ç ã€‚\n" + +#: mips-dis.c:1822 +#, c-format +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH æ ¹æ®æŒ‡å®šçš„æž¶æž„æ‰“å° HWR 寄存器å。\n" +" 默认：根æ®è¢«å汇编的二进制代ç ã€‚\n" + +#: mips-dis.c:1827 +#, c-format +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI æ ¹æ®æŒ‡å®šçš„ ABI 打å°é€šç”¨å¯„存器和浮点寄存\n" +" 器å。\n" + +#: mips-dis.c:1831 +#, c-format +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH æ ¹æ®æŒ‡å®šçš„æž¶æž„æ‰“å° CP0 å’Œ HWR 寄存器å。\n" + +#: mips-dis.c:1835 +#, c-format +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" + +#: mips-dis.c:1840 mips-dis.c:1848 mips-dis.c:1850 +#, c-format +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1842 +#, c-format +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" + +#: mmix-dis.c:34 +#, fuzzy, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "忽略大å°å†™å˜åŒ–(&I)" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(未知)" + +#: mmix-dis.c:519 +#, fuzzy, c-format +msgid "*unknown operands type: %d*" +msgstr "未知的签å类型‘%s’\n" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:631 +#, c-format +msgid "$" +msgstr "$<未定义>" + +#: ppc-opc.c:794 ppc-opc.c:822 +msgid "invalid conditional option" +msgstr "无效的æ¡ä»¶é€‰é¡¹" + +#: ppc-opc.c:824 +msgid "attempt to set y bit when using + or - modifier" +msgstr "" + +#: ppc-opc.c:852 +msgid "offset not a multiple of 16" +msgstr "å移é‡ä¸æ˜¯ 16 çš„å€æ•°" + +#: ppc-opc.c:871 +msgid "offset not a multiple of 2" +msgstr "å移é‡ä¸æ˜¯ 2 çš„å€æ•°" + +#: ppc-opc.c:873 +msgid "offset greater than 62" +msgstr "å移é‡å¤§äºŽ 62" + +#: ppc-opc.c:892 ppc-opc.c:937 ppc-opc.c:981 +msgid "offset not a multiple of 4" +msgstr "å移é‡ä¸æ˜¯ 4 çš„å€æ•°" + +#: ppc-opc.c:894 +msgid "offset greater than 124" +msgstr "å移é‡å¤§äºŽ 124" + +#: ppc-opc.c:913 +msgid "offset not a multiple of 8" +msgstr "å移é‡ä¸æ˜¯ 8 çš„å€æ•°" + +#: ppc-opc.c:915 +msgid "offset greater than 248" +msgstr "å移é‡å¤§äºŽ 248" + +#: ppc-opc.c:958 +msgid "offset not between -2048 and 2047" +msgstr "å移é‡ä¸åœ¨ -2048 å’Œ 2047 之间" + +#: ppc-opc.c:979 +msgid "offset not between -8192 and 8191" +msgstr "å移é‡ä¸åœ¨ -8192 å’Œ 8191 之间" + +#: ppc-opc.c:1007 +msgid "invalid mask field" +msgstr "无效的掩ç å­—段" + +#: ppc-opc.c:1033 +#, fuzzy +msgid "ignoring invalid mfcr mask" +msgstr "忽略 schema å称“%sâ€ï¼Œæ— æ•ˆï¼š%s" + +#: ppc-opc.c:1075 +msgid "ignoring least significant bits in branch offset" +msgstr "" + +#: ppc-opc.c:1105 ppc-opc.c:1140 +msgid "illegal bitmask" +msgstr "éžæ³•çš„ä½æŽ©ç " + +#: ppc-opc.c:1205 +msgid "value out of range" +msgstr "值越界" + +#: ppc-opc.c:1273 +#, fuzzy +msgid "index register in load range" +msgstr "åˆå§‹å€¼è®¾å®šé¡¹ä¸­ç´¢å¼•èŒƒå›´ä¸ºç©º" + +#: ppc-opc.c:1289 +msgid "source and target register operands must be different" +msgstr "" + +#: ppc-opc.c:1304 +msgid "invalid register operand when updating" +msgstr "" + +#: ppc-opc.c:1343 +msgid "target register operand must be even" +msgstr "目的寄存器æ“作数必须是å¶æ•°" + +#: ppc-opc.c:1357 +msgid "source register operand must be even" +msgstr "æºå¯„存器æ“作数必须是å¶æ•°" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 +msgid "unknown" +msgstr "未知" + +#: sparc-dis.c:835 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "内部错误：错误的 sparc-opcode.h：“%sâ€ï¼Œ%#.8lx，%#.8lx\n" + +#: sparc-dis.c:846 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "内部错误：错误的 sparc-opcode.h：“%sâ€ï¼Œ%#.8lx，%#.8lx\n" + +#: sparc-dis.c:895 +#, fuzzy, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "内部错误：错误的 sparc-opcode.h：“%sâ€ï¼Œ%#.8lx，%#.8lx\n" + +#: v850-dis.c:225 +#, fuzzy, c-format +msgid "unknown operand shift: %x\n" +msgstr "PRINT_OPERAND：未知的标点‘%c’" + +#: v850-dis.c:237 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "未知的弹栈寄存器：%d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:69 +msgid "displacement value is not in range and is not aligned" +msgstr "" + +#: v850-opc.c:70 +msgid "displacement value is out of range" +msgstr "å移值越界" + +#: v850-opc.c:71 +msgid "displacement value is not aligned" +msgstr "å移值未对é½" + +#: v850-opc.c:73 +msgid "immediate value is out of range" +msgstr "ç«‹å³æ•°è¶Šç•Œ" + +#: v850-opc.c:84 +msgid "branch value not in range and to odd offset" +msgstr "跳转越界且跳转å移é‡ä¸ºå¥‡æ•°" + +#: v850-opc.c:86 v850-opc.c:118 +msgid "branch value out of range" +msgstr "跳转越界" + +#: v850-opc.c:89 v850-opc.c:121 +msgid "branch to odd offset" +msgstr "跳转å移é‡ä¸ºå¥‡æ•°" + +#: v850-opc.c:116 +msgid "branch value not in range and to an odd offset" +msgstr "跳转越界且跳转å移é‡ä¸ºå¥‡æ•°" + +#: v850-opc.c:347 +msgid "invalid register for stack adjustment" +msgstr "用于调整堆栈的寄存器无效" + +#: v850-opc.c:371 +msgid "immediate value not in range and not even" +msgstr "ç«‹å³æ•°è¶Šç•Œä¸”ä¸æ˜¯å¶æ•°" + +#: v850-opc.c:376 +msgid "immediate value must be even" +msgstr "必须给出立å³æ•°" + +#: xstormy16-asm.c:76 +msgid "Bad register in preincrement" +msgstr "å‰ç½®è‡ªå¢žä¸­ä½¿ç”¨äº†é”™è¯¯çš„寄存器" + +#: xstormy16-asm.c:81 +msgid "Bad register in postincrement" +msgstr "åŽç½®è‡ªå¢žä¸­ä½¿ç”¨äº†é”™è¯¯çš„寄存器" + +#: xstormy16-asm.c:83 +msgid "Bad register name" +msgstr "错误的寄存器å" + +#: xstormy16-asm.c:87 +msgid "Label conflicts with register name" +msgstr "æ ‡å·ä¸Žå¯„存器å冲çª" + +#: xstormy16-asm.c:91 +msgid "Label conflicts with `Rx'" +msgstr "æ ‡å·ä¸Žâ€˜Rx’冲çª" + +#: xstormy16-asm.c:93 +msgid "Bad immediate expression" +msgstr "错误的立å³æ•°è¡¨è¾¾å¼" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "" + +#: xstormy16-asm.c:125 +msgid "Small operand was not an immediate number" +msgstr "" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "æ“作数ä¸æ˜¯ä¸€ä¸ªç¬¦å·" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "语法错误：没有结尾的‘)’" diff --git a/external/gpl3/gdb/dist/opcodes/ppc-dis.c b/external/gpl3/gdb/dist/opcodes/ppc-dis.c new file mode 100644 index 000000000000..8771f95b15b6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ppc-dis.c @@ -0,0 +1,537 @@ +/* ppc-dis.c -- Disassemble PowerPC instructions + Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, + 2008, 2009, 2010 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opintl.h" +#include "opcode/ppc.h" + +/* This file provides several disassembler functions, all of which use + the disassembler interface defined in dis-asm.h. Several functions + are provided because this file handles disassembly for the PowerPC + in both big and little endian mode and also for the POWER (RS/6000) + chip. */ +static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, + ppc_cpu_t); + +struct dis_private +{ + /* Stash the result of parsing disassembler_options here. */ + ppc_cpu_t dialect; +}; + +#define POWERPC_DIALECT(INFO) \ + (((struct dis_private *) ((INFO)->private_data))->dialect) + +struct ppc_mopt { + const char *opt; + ppc_cpu_t cpu; + ppc_cpu_t sticky; +}; + +struct ppc_mopt ppc_opts[] = { + { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403), + 0 }, + { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405), + 0 }, + { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 + | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), + 0 }, + { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 + | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), + 0 }, + { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440 + | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), + 0 }, + { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601), + 0 }, + { "603", (PPC_OPCODE_PPC), + 0 }, + { "604", (PPC_OPCODE_PPC), + 0 }, + { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64), + 0 }, + { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), + 0 }, + { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), + 0 }, + { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), + 0 }, + { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC), + 0 }, + { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS) + , 0 }, + { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 + | PPC_OPCODE_A2), + 0 }, + { "altivec", (PPC_OPCODE_PPC), + PPC_OPCODE_ALTIVEC }, + { "any", 0, + PPC_OPCODE_ANY }, + { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), + 0 }, + { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE), + 0 }, + { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), + 0 }, + { "com", (PPC_OPCODE_COMMON), + 0 }, + { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300), + 0 }, + { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE + | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500), + 0 }, + { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500MC), + 0 }, + { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 + | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), + 0 }, + { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE + | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500), + 0 }, + { "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), + 0 }, + { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), + 0 }, + { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5), + 0 }, + { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), + 0 }, + { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + 0 }, + { "ppc", (PPC_OPCODE_PPC), + 0 }, + { "ppc32", (PPC_OPCODE_PPC), + 0 }, + { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64), + 0 }, + { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE), + 0 }, + { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS), + 0 }, + { "pwr", (PPC_OPCODE_POWER), + 0 }, + { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), + 0 }, + { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4), + 0 }, + { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5), + 0 }, + { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5), + 0 }, + { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), + 0 }, + { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + 0 }, + { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2), + 0 }, + { "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS), + PPC_OPCODE_SPE }, + { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR + | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), + 0 }, + { "vsx", (PPC_OPCODE_PPC), + PPC_OPCODE_VSX }, +}; + +/* Handle -m and -M options that set cpu type, and .machine arg. */ + +ppc_cpu_t +ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg) +{ + /* Sticky bits. */ + ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX + | PPC_OPCODE_SPE | PPC_OPCODE_ANY); + unsigned int i; + + for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) + if (strcmp (ppc_opts[i].opt, arg) == 0) + { + if (ppc_opts[i].sticky) + { + retain_flags |= ppc_opts[i].sticky; + if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX + | PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0) + break; + } + ppc_cpu = ppc_opts[i].cpu; + break; + } + if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0])) + return 0; + + ppc_cpu |= retain_flags; + return ppc_cpu; +} + +/* Determine which set of machines to disassemble for. */ + +static int +powerpc_init_dialect (struct disassemble_info *info) +{ + ppc_cpu_t dialect = 0; + char *arg; + struct dis_private *priv = calloc (sizeof (*priv), 1); + + if (priv == NULL) + return FALSE; + + arg = info->disassembler_options; + while (arg != NULL) + { + ppc_cpu_t new_cpu = 0; + char *end = strchr (arg, ','); + + if (end != NULL) + *end = 0; + + if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0) + dialect = new_cpu; + else if (strcmp (arg, "32") == 0) + dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; + else if (strcmp (arg, "64") == 0) + dialect |= PPC_OPCODE_64; + else + fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg); + + if (end != NULL) + *end++ = ','; + arg = end; + } + + if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0) + { + if (info->mach == bfd_mach_ppc64) + dialect |= PPC_OPCODE_64; + else + dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; + /* Choose a reasonable default. */ + dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601 + | PPC_OPCODE_ALTIVEC); + } + + info->private_data = priv; + POWERPC_DIALECT(info) = dialect; + + return TRUE; +} + +/* Print a big endian PowerPC instruction. */ + +int +print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) +{ + if (info->private_data == NULL && !powerpc_init_dialect (info)) + return -1; + return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info)); +} + +/* Print a little endian PowerPC instruction. */ + +int +print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) +{ + if (info->private_data == NULL && !powerpc_init_dialect (info)) + return -1; + return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info)); +} + +/* Print a POWER (RS/6000) instruction. */ + +int +print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) +{ + return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); +} + +/* Extract the operand value from the PowerPC or POWER instruction. */ + +static long +operand_value_powerpc (const struct powerpc_operand *operand, + unsigned long insn, ppc_cpu_t dialect) +{ + long value; + int invalid; + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, dialect, &invalid); + else + { + value = (insn >> operand->shift) & operand->bitm; + if ((operand->flags & PPC_OPERAND_SIGNED) != 0) + { + /* BITM is always some number of zeros followed by some + number of ones, followed by some numer of zeros. */ + unsigned long top = operand->bitm; + /* top & -top gives the rightmost 1 bit, so this + fills in any trailing zeros. */ + top |= (top & -top) - 1; + top &= ~(top >> 1); + value = (value ^ top) - top; + } + } + + return value; +} + +/* Determine whether the optional operand(s) should be printed. */ + +static int +skip_optional_operands (const unsigned char *opindex, + unsigned long insn, ppc_cpu_t dialect) +{ + const struct powerpc_operand *operand; + + for (; *opindex != 0; opindex++) + { + operand = &powerpc_operands[*opindex]; + if ((operand->flags & PPC_OPERAND_NEXT) != 0 + || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 + && operand_value_powerpc (operand, insn, dialect) != 0)) + return 0; + } + + return 1; +} + +/* Print a PowerPC or POWER instruction. */ + +static int +print_insn_powerpc (bfd_vma memaddr, + struct disassemble_info *info, + int bigendian, + ppc_cpu_t dialect) +{ + bfd_byte buffer[4]; + int status; + unsigned long insn; + const struct powerpc_opcode *opcode; + const struct powerpc_opcode *opcode_end; + unsigned long op; + ppc_cpu_t dialect_orig = dialect; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (bigendian) + insn = bfd_getb32 (buffer); + else + insn = bfd_getl32 (buffer); + + /* Get the major opcode of the instruction. */ + op = PPC_OP (insn); + + /* Find the first match in the opcode table. We could speed this up + a bit by doing a binary search on the major opcode. */ + opcode_end = powerpc_opcodes + powerpc_num_opcodes; + again: + for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) + { + unsigned long table_op; + const unsigned char *opindex; + const struct powerpc_operand *operand; + int invalid; + int need_comma; + int need_paren; + int skip_optional; + + table_op = PPC_OP (opcode->opcode); + if (op < table_op) + break; + if (op > table_op) + continue; + + if ((insn & opcode->mask) != opcode->opcode + || (opcode->flags & dialect) == 0 + || (opcode->deprecated & dialect_orig) != 0) + continue; + + /* Make two passes over the operands. First see if any of them + have extraction functions, and, if they do, make sure the + instruction is valid. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, dialect, &invalid); + } + if (invalid) + continue; + + /* The instruction is valid. */ + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Now extract and print the operands. */ + need_comma = 0; + need_paren = 0; + skip_optional = -1; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + long value; + + operand = powerpc_operands + *opindex; + + /* Operands that are marked FAKE are simply ignored. We + already made sure that the extract function considered + the instruction to be valid. */ + if ((operand->flags & PPC_OPERAND_FAKE) != 0) + continue; + + /* If all of the optional operands have the value zero, + then don't print any of them. */ + if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) + { + if (skip_optional < 0) + skip_optional = skip_optional_operands (opindex, insn, + dialect); + if (skip_optional) + continue; + } + + value = operand_value_powerpc (operand, insn, dialect); + + if (need_comma) + { + (*info->fprintf_func) (info->stream, ","); + need_comma = 0; + } + + /* Print the operand as directed by the flags. */ + if ((operand->flags & PPC_OPERAND_GPR) != 0 + || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) + (*info->fprintf_func) (info->stream, "r%ld", value); + else if ((operand->flags & PPC_OPERAND_FPR) != 0) + (*info->fprintf_func) (info->stream, "f%ld", value); + else if ((operand->flags & PPC_OPERAND_VR) != 0) + (*info->fprintf_func) (info->stream, "v%ld", value); + else if ((operand->flags & PPC_OPERAND_VSR) != 0) + (*info->fprintf_func) (info->stream, "vs%ld", value); + else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) + (*info->print_address_func) (memaddr + value, info); + else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) + (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); + else if ((operand->flags & PPC_OPERAND_FSL) != 0) + (*info->fprintf_func) (info->stream, "fsl%ld", value); + else if ((operand->flags & PPC_OPERAND_FCR) != 0) + (*info->fprintf_func) (info->stream, "fcr%ld", value); + else if ((operand->flags & PPC_OPERAND_UDI) != 0) + (*info->fprintf_func) (info->stream, "%ld", value); + else if ((operand->flags & PPC_OPERAND_CR) != 0 + && (dialect & PPC_OPCODE_PPC) != 0) + { + if (operand->bitm == 7) + (*info->fprintf_func) (info->stream, "cr%ld", value); + else + { + static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; + int cr; + int cc; + + cr = value >> 2; + if (cr != 0) + (*info->fprintf_func) (info->stream, "4*cr%d+", cr); + cc = value & 3; + (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); + } + } + else + (*info->fprintf_func) (info->stream, "%ld", value); + + if (need_paren) + { + (*info->fprintf_func) (info->stream, ")"); + need_paren = 0; + } + + if ((operand->flags & PPC_OPERAND_PARENS) == 0) + need_comma = 1; + else + { + (*info->fprintf_func) (info->stream, "("); + need_paren = 1; + } + } + + /* We have found and printed an instruction; return. */ + return 4; + } + + if ((dialect & PPC_OPCODE_ANY) != 0) + { + dialect = ~(ppc_cpu_t) PPC_OPCODE_ANY; + goto again; + } + + /* We could not find a match. */ + (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); + + return 4; +} + +void +print_ppc_disassembler_options (FILE *stream) +{ + unsigned int i, col; + + fprintf (stream, _("\n\ +The following PPC specific disassembler options are supported for use with\n\ +the -M switch:\n")); + + for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) + { + col += fprintf (stream, " %s,", ppc_opts[i].opt); + if (col > 66) + { + fprintf (stream, "\n"); + col = 0; + } + } + fprintf (stream, " 32, 64\n"); +} diff --git a/external/gpl3/gdb/dist/opcodes/ppc-opc.c b/external/gpl3/gdb/dist/opcodes/ppc-opc.c new file mode 100644 index 000000000000..f877a54001cd --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/ppc-opc.c @@ -0,0 +1,5420 @@ +/* ppc-opc.c -- PowerPC opcode list + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, + 2005, 2006, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/ppc.h" +#include "opintl.h" + +/* This file holds the PowerPC opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* Local insertion and extraction functions. */ + +static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); +static long extract_bat (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); +static long extract_bba (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); +static long extract_bdm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); +static long extract_bdp (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); +static long extract_bo (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); +static long extract_boe (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); +static long extract_fxm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); +static long extract_mbe (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_mb6 (unsigned long, ppc_cpu_t, int *); +static long extract_nb (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); +static long extract_nsi (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); +static long extract_rbs (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sh6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); +static long extract_spr (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sprg (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); +static long extract_tbr (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xt6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xa6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xb6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xb6s (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xc6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); +static long extract_dm (unsigned long, ppc_cpu_t, int *); + +/* The operands table. + + The fields are bitm, shift, insert, extract, flags. + + We used to put parens around the various additions, like the one + for BA just below. However, that caused trouble with feeble + compilers with a limit on depth of a parenthesized expression, like + (reportedly) the compiler in Microsoft Developer Studio 5. So we + omit the parens, since the macros are never used in a context where + the addition will be ambiguous. */ + +const struct powerpc_operand powerpc_operands[] = +{ + /* The zero index is used to indicate the end of the list of + operands. */ +#define UNUSED 0 + { 0, 0, NULL, NULL, 0 }, + + /* The BA field in an XL form instruction. */ +#define BA UNUSED + 1 + /* The BI field in a B form or XL form instruction. */ +#define BI BA +#define BI_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, + + /* The BA field in an XL form instruction when it must be the same + as the BT field in the same instruction. */ +#define BAT BA + 1 + { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, + + /* The BB field in an XL form instruction. */ +#define BB BAT + 1 +#define BB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, + + /* The BB field in an XL form instruction when it must be the same + as the BA field in the same instruction. */ +#define BBA BB + 1 + { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, + + /* The BD field in a B form instruction. The lower two bits are + forced to zero. */ +#define BD BBA + 1 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when absolute addressing is + used. */ +#define BDA BD + 1 + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used. + This sets the y bit of the BO field appropriately. */ +#define BDM BDA + 1 + { 0xfffc, 0, insert_bdm, extract_bdm, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the - modifier is used + and absolute address is used. */ +#define BDMA BDM + 1 + { 0xfffc, 0, insert_bdm, extract_bdm, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used. + This sets the y bit of the BO field appropriately. */ +#define BDP BDMA + 1 + { 0xfffc, 0, insert_bdp, extract_bdp, + PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The BD field in a B form instruction when the + modifier is used + and absolute addressing is used. */ +#define BDPA BDP + 1 + { 0xfffc, 0, insert_bdp, extract_bdp, + PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The BF field in an X or XL form instruction. */ +#define BF BDPA + 1 + /* The CRFD field in an X form instruction. */ +#define CRFD BF + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, + + /* The BF field in an X or XL form instruction. */ +#define BFF BF + 1 + { 0x7, 23, NULL, NULL, 0 }, + + /* An optional BF field. This is used for comparison instructions, + in which an omitted BF field is taken as zero. */ +#define OBF BFF + 1 + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The BFA field in an X or XL form instruction. */ +#define BFA OBF + 1 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, + + /* The BO field in a B form instruction. Certain values are + illegal. */ +#define BO BFA + 1 +#define BO_MASK (0x1f << 21) + { 0x1f, 21, insert_bo, extract_bo, 0 }, + + /* The BO field in a B form instruction when the + or - modifier is + used. This is like the BO field, but it must be even. */ +#define BOE BO + 1 + { 0x1e, 21, insert_boe, extract_boe, 0 }, + +#define BH BOE + 1 + { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The BT field in an X or XL form instruction. */ +#define BT BH + 1 + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, + + /* The condition register number portion of the BI field in a B form + or XL form instruction. This is used for the extended + conditional branch mnemonics, which set the lower two bits of the + BI field. This field is optional. */ +#define CR BT + 1 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + + /* The CRB field in an X form instruction. */ +#define CRB CR + 1 + /* The MB field in an M form instruction. */ +#define MB CRB +#define MB_MASK (0x1f << 6) + { 0x1f, 6, NULL, NULL, 0 }, + + /* The CRFS field in an X form instruction. */ +#define CRFS CRB + 1 + { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, + + /* The CT field in an X form instruction. */ +#define CT CRFS + 1 + /* The MO field in an mbar instruction. */ +#define MO CT + { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The D field in a D form instruction. This is a displacement off + a register, and implies that the next operand is a register in + parentheses. */ +#define D CT + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ +#define DQ D + 1 + { 0xfff0, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + + /* The DS field in a DS form instruction. This is like D, but the + lower two bits are forced to zero. */ +#define DS DQ + 1 + { 0xfffc, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, + + /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */ +#define DUIS DS + 1 + { 0x3ff, 11, NULL, NULL, 0 }, + + /* The E field in a wrteei instruction. */ + /* And the W bit in the pair singles instructions. */ +#define E DUIS + 1 +#define PSW E + { 0x1, 15, NULL, NULL, 0 }, + + /* The FL1 field in a POWER SC form instruction. */ +#define FL1 E + 1 + /* The U field in an X form instruction. */ +#define U FL1 + { 0xf, 12, NULL, NULL, 0 }, + + /* The FL2 field in a POWER SC form instruction. */ +#define FL2 FL1 + 1 + { 0x7, 2, NULL, NULL, 0 }, + + /* The FLM field in an XFL form instruction. */ +#define FLM FL2 + 1 + { 0xff, 17, NULL, NULL, 0 }, + + /* The FRA field in an X or A form instruction. */ +#define FRA FLM + 1 +#define FRA_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRB field in an X or A form instruction. */ +#define FRB FRA + 1 +#define FRB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRC field in an A form instruction. */ +#define FRC FRB + 1 +#define FRC_MASK (0x1f << 6) + { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FRS field in an X form instruction or the FRT field in a D, X + or A form instruction. */ +#define FRS FRC + 1 +#define FRT FRS + { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, + + /* The FXM field in an XFX instruction. */ +#define FXM FRS + 1 + { 0xff, 12, insert_fxm, extract_fxm, 0 }, + + /* Power4 version for mfcr. */ +#define FXM4 FXM + 1 + { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, + + /* The L field in a D or X form instruction. */ +#define L FXM4 + 1 + { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The LEV field in a POWER SVC form instruction. */ +#define SVC_LEV L + 1 + { 0x7f, 5, NULL, NULL, 0 }, + + /* The LEV field in an SC form instruction. */ +#define LEV SVC_LEV + 1 + { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The LI field in an I form instruction. The lower two bits are + forced to zero. */ +#define LI LEV + 1 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The LI field in an I form instruction when used as an absolute + address. */ +#define LIA LI + 1 + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + + /* The LS or WC field in an X (sync or wait) form instruction. */ +#define LS LIA + 1 +#define WC LS + { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The ME field in an M form instruction. */ +#define ME LS + 1 +#define ME_MASK (0x1f << 1) + { 0x1f, 1, NULL, NULL, 0 }, + + /* The MB and ME fields in an M form instruction expressed a single + operand which is a bitmask indicating which bits to select. This + is a two operand form using PPC_OPERAND_NEXT. See the + description in opcode/ppc.h for what this means. */ +#define MBE ME + 1 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, + { -1, 0, insert_mbe, extract_mbe, 0 }, + + /* The MB or ME field in an MD or MDS form instruction. The high + bit is wrapped to the low end. */ +#define MB6 MBE + 2 +#define ME6 MB6 +#define MB6_MASK (0x3f << 5) + { 0x3f, 5, insert_mb6, extract_mb6, 0 }, + + /* The NB field in an X form instruction. The value 32 is stored as + 0. */ +#define NB MB6 + 1 + { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, + + /* The NSI field in a D form instruction. This is the same as the + SI field, only negated. */ +#define NSI NB + 1 + { 0xffff, 0, insert_nsi, extract_nsi, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + + /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ +#define RA NSI + 1 +#define RA_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, + + /* As above, but 0 in the RA field means zero, not r0. */ +#define RA0 RA + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ +#define RAQ RA0 + 1 + { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in a D or X form instruction which is an updating + load, which means that the RA field may not be zero and may not + equal the RT field. */ +#define RAL RAQ + 1 + { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in an lmw instruction, which has special value + restrictions. */ +#define RAM RAL + 1 + { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field in a D or X form instruction which is an updating + store or an updating floating point load, which means that the RA + field may not be zero. */ +#define RAS RAM + 1 + { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, + + /* The RA field of the tlbwe, dccci and iccci instructions, + which are optional. */ +#define RAOPT RAS + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + + /* The RB field in an X, XO, M, or MDS form instruction. */ +#define RB RAOPT + 1 +#define RB_MASK (0x1f << 11) + { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, + + /* The RB field in an X form instruction when it must be the same as + the RS field in the instruction. This is used for extended + mnemonics like mr. */ +#define RBS RB + 1 + { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, + + /* The RB field of the dccci and iccci instructions, which are optional. */ +#define RBOPT RBS + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + + /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form + instruction or the RT field in a D, DS, X, XFX or XO form + instruction. */ +#define RS RBOPT + 1 +#define RT RS +#define RT_MASK (0x1f << 21) + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, + + /* The RS and RT fields of the DS form stq instruction, which have + special value restrictions. */ +#define RSQ RS + 1 +#define RTQ RSQ + { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, + + /* The RS field of the tlbwe instruction, which is optional. */ +#define RSO RSQ + 1 +#define RTO RSO + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + + /* The SH field in an X or M form instruction. */ +#define SH RSO + 1 +#define SH_MASK (0x1f << 11) + /* The other UIMM field in a EVX form instruction. */ +#define EVUIMM SH + { 0x1f, 11, NULL, NULL, 0 }, + + /* The SH field in an MD form instruction. This is split. */ +#define SH6 SH + 1 +#define SH6_MASK ((0x1f << 11) | (1 << 1)) + { 0x3f, -1, insert_sh6, extract_sh6, 0 }, + + /* The SH field of the tlbwe instruction, which is optional. */ +#define SHO SH6 + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The SI field in a D form instruction. */ +#define SI SHO + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, + + /* The SI field in a D form instruction when we accept a wide range + of positive values. */ +#define SISIGNOPT SI + 1 + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + + /* The SPR field in an XFX form instruction. This is flipped--the + lower 5 bits are stored in the upper 5 and vice- versa. */ +#define SPR SISIGNOPT + 1 +#define PMR SPR +#define SPR_MASK (0x3ff << 11) + { 0x3ff, 11, insert_spr, extract_spr, 0 }, + + /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ +#define SPRBAT SPR + 1 +#define SPRBAT_MASK (0x3 << 17) + { 0x3, 17, NULL, NULL, 0 }, + + /* The SPRG register number in an XFX form m[ft]sprg instruction. */ +#define SPRG SPRBAT + 1 + { 0x1f, 16, insert_sprg, extract_sprg, 0 }, + + /* The SR field in an X form instruction. */ +#define SR SPRG + 1 + { 0xf, 16, NULL, NULL, 0 }, + + /* The STRM field in an X AltiVec form instruction. */ +#define STRM SR + 1 + /* The T field in a tlbilx form instruction. */ +#define T STRM + { 0x3, 21, NULL, NULL, 0 }, + + /* The SV field in a POWER SC form instruction. */ +#define SV STRM + 1 + { 0x3fff, 2, NULL, NULL, 0 }, + + /* The TBR field in an XFX form instruction. This is like the SPR + field, but it is optional. */ +#define TBR SV + 1 + { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, + + /* The TO field in a D or X form instruction. */ +#define TO TBR + 1 +#define DUI TO +#define TO_MASK (0x1f << 21) + { 0x1f, 21, NULL, NULL, 0 }, + + /* The UI field in a D form instruction. */ +#define UI TO + 1 + { 0xffff, 0, NULL, NULL, 0 }, + + /* The VA field in a VA, VX or VXR form instruction. */ +#define VA UI + 1 + { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, + + /* The VB field in a VA, VX or VXR form instruction. */ +#define VB VA + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, + + /* The VC field in a VA form instruction. */ +#define VC VB + 1 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, + + /* The VD or VS field in a VA, VX, VXR or X form instruction. */ +#define VD VC + 1 +#define VS VD + { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, + + /* The SIMM field in a VX form instruction, and TE in Z form. */ +#define SIMM VD + 1 +#define TE SIMM + { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, + + /* The UIMM field in a VX form instruction. */ +#define UIMM SIMM + 1 + { 0x1f, 16, NULL, NULL, 0 }, + + /* The SHB field in a VA form instruction. */ +#define SHB UIMM + 1 + { 0xf, 6, NULL, NULL, 0 }, + + /* The other UIMM field in a half word EVX form instruction. */ +#define EVUIMM_2 SHB + 1 + { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a word EVX form instruction. */ +#define EVUIMM_4 EVUIMM_2 + 1 + { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a double EVX form instruction. */ +#define EVUIMM_8 EVUIMM_4 + 1 + { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The WS field. */ +#define WS EVUIMM_8 + 1 + { 0x7, 11, NULL, NULL, 0 }, + + /* PowerPC paired singles extensions. */ + /* W bit in the pair singles instructions for x type instructions. */ +#define PSWM WS + 1 + { 0x1, 10, 0, 0, 0 }, + + /* IDX bits for quantization in the pair singles instructions. */ +#define PSQ PSWM + 1 + { 0x7, 12, 0, 0, 0 }, + + /* IDX bits for quantization in the pair singles x-type instructions. */ +#define PSQM PSQ + 1 + { 0x7, 7, 0, 0, 0 }, + + /* Smaller D field for quantization in the pair singles instructions. */ +#define PSD PSQM + 1 + { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + +#define A_L PSD + 1 +#define W A_L +#define MTMSRD_L W + { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, + +#define RMC MTMSRD_L + 1 + { 0x3, 9, NULL, NULL, 0 }, + +#define R RMC + 1 + { 0x1, 16, NULL, NULL, 0 }, + +#define SP R + 1 + { 0x3, 19, NULL, NULL, 0 }, + +#define S SP + 1 + { 0x1, 20, NULL, NULL, 0 }, + + /* SH field starting at bit position 16. */ +#define SH16 S + 1 + /* The DCM and DGM fields in a Z form instruction. */ +#define DCM SH16 +#define DGM DCM + { 0x3f, 10, NULL, NULL, 0 }, + + /* The EH field in larx instruction. */ +#define EH SH16 + 1 + { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The L field in an mtfsf or XFL form instruction. */ +#define XFL_L EH + 1 + { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, + + /* Xilinx APU related masks and macros */ +#define FCRT XFL_L + 1 +#define FCRT_MASK (0x1f << 21) + { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, + + /* Xilinx FSL related masks and macros */ +#define FSL FCRT + 1 +#define FSL_MASK (0x1f << 11) + { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, + + /* Xilinx UDI related masks and macros */ +#define URT FSL + 1 + { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, + +#define URA URT + 1 + { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, + +#define URB URA + 1 + { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, + +#define URC URB + 1 + { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, + + /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ +#define XS6 URC + 1 +#define XT6 XS6 + { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, + + /* The XA field in an XX3 form instruction. This is split. */ +#define XA6 XT6 + 1 + { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, + + /* The XB field in an XX2 or XX3 form instruction. This is split. */ +#define XB6 XA6 + 1 + { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, + + /* The XB field in an XX3 form instruction when it must be the same as + the XA field in the instruction. This is used in extended mnemonics + like xvmovdp. This is split. */ +#define XB6S XB6 + 1 + { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, + + /* The XC field in an XX4 form instruction. This is split. */ +#define XC6 XB6S + 1 + { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, + + /* The DM or SHW field in an XX3 form instruction. */ +#define DM XC6 + 1 +#define SHW DM + { 0x3, 8, NULL, NULL, 0 }, + + /* The DM field in an extended mnemonic XX3 form instruction. */ +#define DMEX DM + 1 + { 0x3, 8, insert_dm, extract_dm, 0 }, + + /* The UIM field in an XX2 form instruction. */ +#define UIM DMEX + 1 + { 0x3, 16, NULL, NULL, 0 }, + +#define ERAT_T UIM + 1 + { 0x7, 21, NULL, NULL, 0 }, +}; + +const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) + / sizeof (powerpc_operands[0])); + +/* The functions used to insert and extract complicated operands. */ + +/* The BA field in an XL form instruction when it must be the same as + the BT field in the same instruction. This operand is marked FAKE. + The insertion function just copies the BT field into the BA field, + and the extraction function just checks that the fields are the + same. */ + +static unsigned long +insert_bat (unsigned long insn, + long value ATTRIBUTE_UNUSED, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 21) & 0x1f) << 16); +} + +static long +extract_bat (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The BB field in an XL form instruction when it must be the same as + the BA field in the same instruction. This operand is marked FAKE. + The insertion function just copies the BA field into the BB field, + and the extraction function just checks that the fields are the + same. */ + +static unsigned long +insert_bba (unsigned long insn, + long value ATTRIBUTE_UNUSED, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 16) & 0x1f) << 11); +} + +static long +extract_bba (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The BD field in a B form instruction when the - modifier is used. + This modifier means that the branch is not expected to be taken. + For chips built to versions of the architecture prior to version 2 + (ie. not Power4 compatible), we set the y bit of the BO field to 1 + if the offset is negative. When extracting, we require that the y + bit be 1 and that the offset be positive, since if the y bit is 0 + we just want to print the normal form of the instruction. + Power4 compatible targets use two bits, "a", and "t", instead of + the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, + "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 + in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 + for branch on CTR. We only handle the taken/not-taken hint here. + Note that we don't relax the conditions tested here when + disassembling with -Many because insns using extract_bdm and + extract_bdp always occur in pairs. One or the other will always + be valid. */ + +static unsigned long +insert_bdm (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if ((value & 0x8000) != 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x02 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x08 << 21; + } + return insn | (value & 0xfffc); +} + +static long +extract_bdm (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x06 << 21) + && (insn & (0x1d << 21)) != (0x18 << 21)) + *invalid = 1; + } + + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* The BD field in a B form instruction when the + modifier is used. + This is like BDM, above, except that the branch is expected to be + taken. */ + +static unsigned long +insert_bdp (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if ((value & 0x8000) == 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x03 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x09 << 21; + } + return insn | (value & 0xfffc); +} + +static long +extract_bdp (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x07 << 21) + && (insn & (0x1d << 21)) != (0x19 << 21)) + *invalid = 1; + } + + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* Check for legal values of a BO field. */ + +static int +valid_bo (long value, ppc_cpu_t dialect, int extract) +{ + if ((dialect & PPC_OPCODE_POWER4) == 0) + { + int valid; + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, y may be anything): + 001zy + 011zy + 1z00y + 1z01y + 1z1zz + */ + switch (value & 0x14) + { + default: + case 0: + valid = 1; + break; + case 0x4: + valid = (value & 0x2) == 0; + break; + case 0x10: + valid = (value & 0x8) == 0; + break; + case 0x14: + valid = value == 0x14; + break; + } + /* When disassembling with -Many, accept power4 encodings too. */ + if (valid + || (dialect & PPC_OPCODE_ANY) == 0 + || !extract) + return valid; + } + + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, a & t may be anything): + 0000z + 0001z + 0100z + 0101z + 001at + 011at + 1a00t + 1a01t + 1z1zz + */ + if ((value & 0x14) == 0) + return (value & 0x1) == 0; + else if ((value & 0x14) == 0x14) + return value == 0x14; + else + return 1; +} + +/* The BO field in a B form instruction. Warn about attempts to set + the field to an illegal value. */ + +static unsigned long +insert_bo (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + if (!valid_bo (value, dialect, 0)) + *errmsg = _("invalid conditional option"); + return insn | ((value & 0x1f) << 21); +} + +static long +extract_bo (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + long value; + + value = (insn >> 21) & 0x1f; + if (!valid_bo (value, dialect, 1)) + *invalid = 1; + return value; +} + +/* The BO field in a B form instruction when the + or - modifier is + used. This is like the BO field, but it must be even. When + extracting it, we force it to be even. */ + +static unsigned long +insert_boe (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + if (!valid_bo (value, dialect, 0)) + *errmsg = _("invalid conditional option"); + else if ((value & 1) != 0) + *errmsg = _("attempt to set y bit when using + or - modifier"); + + return insn | ((value & 0x1f) << 21); +} + +static long +extract_boe (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + long value; + + value = (insn >> 21) & 0x1f; + if (!valid_bo (value, dialect, 1)) + *invalid = 1; + return value & 0x1e; +} + +/* FXM mask in mfcr and mtcrf instructions. */ + +static unsigned long +insert_fxm (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + /* If we're handling the mfocrf and mtocrf insns ensure that exactly + one bit of the mask field is set. */ + if ((insn & (1 << 20)) != 0) + { + if (value == 0 || (value & -value) != value) + { + *errmsg = _("invalid mask field"); + value = 0; + } + } + + /* If the optional field on mfcr is missing that means we want to use + the old form of the instruction that moves the whole cr. In that + case we'll have VALUE zero. There doesn't seem to be a way to + distinguish this from the case where someone writes mfcr %r3,0. */ + else if (value == 0) + ; + + /* If only one bit of the FXM field is set, we can use the new form + of the instruction, which is faster. Unlike the Power4 branch hint + encoding, this is not backward compatible. Do not generate the + new form unless -mpower4 has been given, or -many and the two + operand form of mfcr was used. */ + else if ((value & -value) == value + && ((dialect & PPC_OPCODE_POWER4) != 0 + || ((dialect & PPC_OPCODE_ANY) != 0 + && (insn & (0x3ff << 1)) == 19 << 1))) + insn |= 1 << 20; + + /* Any other value on mfcr is an error. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) + { + *errmsg = _("ignoring invalid mfcr mask"); + value = 0; + } + + return insn | ((value & 0xff) << 12); +} + +static long +extract_fxm (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long mask = (insn >> 12) & 0xff; + + /* Is this a Power4 insn? */ + if ((insn & (1 << 20)) != 0) + { + /* Exactly one bit of MASK should be set. */ + if (mask == 0 || (mask & -mask) != mask) + *invalid = 1; + } + + /* Check that non-power4 form of mfcr has a zero MASK. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) + { + if (mask != 0) + *invalid = 1; + } + + return mask; +} + +/* The MB and ME fields in an M form instruction expressed as a single + operand which is itself a bitmask. The extraction function always + marks it as invalid, since we never want to recognize an + instruction which uses a field of this type. */ + +static unsigned long +insert_mbe (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + unsigned long uval, mask; + int mb, me, mx, count, last; + + uval = value; + + if (uval == 0) + { + *errmsg = _("illegal bitmask"); + return insn; + } + + mb = 0; + me = 32; + if ((uval & 1) != 0) + last = 1; + else + last = 0; + count = 0; + + /* mb: location of last 0->1 transition */ + /* me: location of last 1->0 transition */ + /* count: # transitions */ + + for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) + { + if ((uval & mask) && !last) + { + ++count; + mb = mx; + last = 1; + } + else if (!(uval & mask) && last) + { + ++count; + me = mx; + last = 0; + } + } + if (me == 0) + me = 32; + + if (count != 2 && (count != 0 || ! last)) + *errmsg = _("illegal bitmask"); + + return insn | (mb << 6) | ((me - 1) << 1); +} + +static long +extract_mbe (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long ret; + int mb, me; + int i; + + *invalid = 1; + + mb = (insn >> 6) & 0x1f; + me = (insn >> 1) & 0x1f; + if (mb < me + 1) + { + ret = 0; + for (i = mb; i <= me; i++) + ret |= 1L << (31 - i); + } + else if (mb == me + 1) + ret = ~0; + else /* (mb > me + 1) */ + { + ret = ~0; + for (i = me + 1; i < mb; i++) + ret &= ~(1L << (31 - i)); + } + return ret; +} + +/* The MB or ME field in an MD or MDS form instruction. The high bit + is wrapped to the low end. */ + +static unsigned long +insert_mb6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 6) | (value & 0x20); +} + +static long +extract_mb6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 6) & 0x1f) | (insn & 0x20); +} + +/* The NB field in an X form instruction. The value 32 is stored as + 0. */ + +static long +extract_nb (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long ret; + + ret = (insn >> 11) & 0x1f; + if (ret == 0) + ret = 32; + return ret; +} + +/* The NSI field in a D form instruction. This is the same as the SI + field, only negated. The extraction function always marks it as + invalid, since we never want to recognize an instruction which uses + a field of this type. */ + +static unsigned long +insert_nsi (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (-value & 0xffff); +} + +static long +extract_nsi (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + *invalid = 1; + return -(((insn & 0xffff) ^ 0x8000) - 0x8000); +} + +/* The RA field in a D or X form instruction which is an updating + load, which means that the RA field may not be zero and may not + equal the RT field. */ + +static unsigned long +insert_ral (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value == 0 + || (unsigned long) value == ((insn >> 21) & 0x1f)) + *errmsg = "invalid register operand when updating"; + return insn | ((value & 0x1f) << 16); +} + +/* The RA field in an lmw instruction, which has special value + restrictions. */ + +static unsigned long +insert_ram (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((unsigned long) value >= ((insn >> 21) & 0x1f)) + *errmsg = _("index register in load range"); + return insn | ((value & 0x1f) << 16); +} + +/* The RA field in the DQ form lq instruction, which has special + value restrictions. */ + +static unsigned long +insert_raq (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + long rtvalue = (insn & RT_MASK) >> 21; + + if (value == rtvalue) + *errmsg = _("source and target register operands must be different"); + return insn | ((value & 0x1f) << 16); +} + +/* The RA field in a D or X form instruction which is an updating + store or an updating floating point load, which means that the RA + field may not be zero. */ + +static unsigned long +insert_ras (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value == 0) + *errmsg = _("invalid register operand when updating"); + return insn | ((value & 0x1f) << 16); +} + +/* The RB field in an X form instruction when it must be the same as + the RS field in the instruction. This is used for extended + mnemonics like mr. This operand is marked FAKE. The insertion + function just copies the BT field into the BA field, and the + extraction function just checks that the fields are the same. */ + +static unsigned long +insert_rbs (unsigned long insn, + long value ATTRIBUTE_UNUSED, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 21) & 0x1f) << 11); +} + +static long +extract_rbs (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The SH field in an MD form instruction. This is split. */ + +static unsigned long +insert_sh6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); +} + +static long +extract_sh6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); +} + +/* The SPR field in an XFX form instruction. This is flipped--the + lower 5 bits are stored in the upper 5 and vice- versa. */ + +static unsigned long +insert_spr (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); +} + +static long +extract_spr (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); +} + +/* Some dialects have 8 SPRG registers instead of the standard 4. */ + +static unsigned long +insert_sprg (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + if (value > 7 + || (value > 3 + && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)) + *errmsg = _("invalid sprg number"); + + /* If this is mfsprg4..7 then use spr 260..263 which can be read in + user mode. Anything else must use spr 272..279. */ + if (value <= 3 || (insn & 0x100) != 0) + value |= 0x10; + + return insn | ((value & 0x17) << 16); +} + +static long +extract_sprg (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + unsigned long val = (insn >> 16) & 0x1f; + + /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 + If not BOOKE or 405, then both use only 272..275. */ + if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0) + || (val - 0x10 > 7 && (insn & 0x100) != 0) + || val <= 3 + || (val & 8) != 0) + *invalid = 1; + return val & 7; +} + +/* The TBR field in an XFX instruction. This is just like SPR, but it + is optional. When TBR is omitted, it must be inserted as 268 (the + magic number of the TB register). These functions treat 0 + (indicating an omitted optional operand) as 268. This means that + ``mftb 4,0'' is not handled correctly. This does not matter very + much, since the architecture manual does not define mftb as + accepting any values other than 268 or 269. */ + +#define TB (268) + +static unsigned long +insert_tbr (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value == 0) + value = TB; + return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); +} + +static long +extract_tbr (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long ret; + + ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); + if (ret == TB) + ret = 0; + return ret; +} + +/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ + +static unsigned long +insert_xt6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); +} + +static long +extract_xt6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); +} + +/* The XA field in an XX3 form instruction. This is split. */ + +static unsigned long +insert_xa6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); +} + +static long +extract_xa6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); +} + +/* The XB field in an XX3 form instruction. This is split. */ + +static unsigned long +insert_xb6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); +} + +static long +extract_xb6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); +} + +/* The XB field in an XX3 form instruction when it must be the same as + the XA field in the instruction. This is used for extended + mnemonics like xvmovdp. This operand is marked FAKE. The insertion + function just copies the XA field into the XB field, and the + extraction function just checks that the fields are the same. */ + +static unsigned long +insert_xb6s (unsigned long insn, + long value ATTRIBUTE_UNUSED, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); +} + +static long +extract_xb6s (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) + *invalid = 1; + return 0; +} + +/* The XC field in an XX4 form instruction. This is split. */ + +static unsigned long +insert_xc6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); +} + +static long +extract_xc6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); +} + +static unsigned long +insert_dm (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value != 0 && value != 1) + *errmsg = _("invalid constant"); + return insn | (((value) ? 3 : 0) << 8); +} + +static long +extract_dm (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value; + + value = (insn >> 8) & 3; + if (value != 0 && value != 3) + *invalid = 1; + return (value) ? 1 : 0; +} + +/* Macros used to form opcodes. */ + +/* The main opcode. */ +#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) +#define OP_MASK OP (0x3f) + +/* The main opcode combined with a trap code in the TO field of a D + form instruction. Used for extended mnemonics for the trap + instructions. */ +#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) +#define OPTO_MASK (OP_MASK | TO_MASK) + +/* The main opcode combined with a comparison size bit in the L field + of a D form or X form instruction. Used for extended mnemonics for + the comparison instructions. */ +#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) +#define OPL_MASK OPL (0x3f,1) + +/* An A form instruction. */ +#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) +#define A_MASK A (0x3f, 0x1f, 1) + +/* An A_MASK with the FRB field fixed. */ +#define AFRB_MASK (A_MASK | FRB_MASK) + +/* An A_MASK with the FRC field fixed. */ +#define AFRC_MASK (A_MASK | FRC_MASK) + +/* An A_MASK with the FRA and FRC fields fixed. */ +#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) + +/* An AFRAFRC_MASK, but with L bit clear. */ +#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) + +/* A B form instruction. */ +#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) +#define B_MASK B (0x3f, 1, 1) + +/* A B form instruction setting the BO field. */ +#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) +#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) + +/* A BBO_MASK with the y bit of the BO field removed. This permits + matching a conditional branch regardless of the setting of the y + bit. Similarly for the 'at' bits used for power4 branch hints. */ +#define Y_MASK (((unsigned long) 1) << 21) +#define AT1_MASK (((unsigned long) 3) << 21) +#define AT2_MASK (((unsigned long) 9) << 21) +#define BBOY_MASK (BBO_MASK &~ Y_MASK) +#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) + +/* A B form instruction setting the BO field and the condition bits of + the BI field. */ +#define BBOCB(op, bo, cb, aa, lk) \ + (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) +#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) + +/* A BBOCB_MASK with the y bit of the BO field removed. */ +#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) +#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) +#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) + +/* A BBOYCB_MASK in which the BI field is fixed. */ +#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) +#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) + +/* An Context form instruction. */ +#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) +#define CTX_MASK CTX(0x3f, 0x7) + +/* An User Context form instruction. */ +#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define UCTX_MASK UCTX(0x3f, 0x1f) + +/* The main opcode mask with the RA field clear. */ +#define DRA_MASK (OP_MASK | RA_MASK) + +/* A DS form instruction. */ +#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) +#define DS_MASK DSO (0x3f, 3) + +/* An EVSEL form instruction. */ +#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) +#define EVSEL_MASK EVSEL(0x3f, 0xff) + +/* An M form instruction. */ +#define M(op, rc) (OP (op) | ((rc) & 1)) +#define M_MASK M (0x3f, 1) + +/* An M form instruction with the ME field specified. */ +#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) + +/* An M_MASK with the MB and ME fields fixed. */ +#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) + +/* An M_MASK with the SH and ME fields fixed. */ +#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) + +/* An MD form instruction. */ +#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) +#define MD_MASK MD (0x3f, 0x7, 1) + +/* An MD_MASK with the MB field fixed. */ +#define MDMB_MASK (MD_MASK | MB6_MASK) + +/* An MD_MASK with the SH field fixed. */ +#define MDSH_MASK (MD_MASK | SH6_MASK) + +/* An MDS form instruction. */ +#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) +#define MDS_MASK MDS (0x3f, 0xf, 1) + +/* An MDS_MASK with the MB field fixed. */ +#define MDSMB_MASK (MDS_MASK | MB6_MASK) + +/* An SC form instruction. */ +#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) +#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) + +/* An VX form instruction. */ +#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) + +/* The mask for an VX form instruction. */ +#define VX_MASK VX(0x3f, 0x7ff) + +/* An VA form instruction. */ +#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) + +/* The mask for an VA form instruction. */ +#define VXA_MASK VXA(0x3f, 0x3f) + +/* An VXR form instruction. */ +#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) + +/* The mask for a VXR form instruction. */ +#define VXR_MASK VXR(0x3f, 0x3ff, 1) + +/* An X form instruction. */ +#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) + +/* An XX2 form instruction. */ +#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) + +/* An XX3 form instruction. */ +#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) + +/* An XX3 form instruction with the RC bit specified. */ +#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) + +/* An XX4 form instruction. */ +#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) + +/* A Z form instruction. */ +#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) + +/* An X form instruction with the RC bit specified. */ +#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) + +/* A Z form instruction with the RC bit specified. */ +#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) + +/* The mask for an X form instruction. */ +#define X_MASK XRC (0x3f, 0x3ff, 1) + +/* An X form wait instruction with everything filled in except the WC field. */ +#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) + +/* The mask for an XX1 form instruction. */ +#define XX1_MASK X (0x3f, 0x3ff) + +/* The mask for an XX2 form instruction. */ +#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) + +/* The mask for an XX2 form instruction with the UIM bits specified. */ +#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) + +/* The mask for an XX2 form instruction with the BF bits specified. */ +#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) + +/* The mask for an XX3 form instruction. */ +#define XX3_MASK XX3 (0x3f, 0xff) + +/* The mask for an XX3 form instruction with the BF bits specified. */ +#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) + +/* The mask for an XX3 form instruction with the DM or SHW bits specified. */ +#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) +#define XX3SHW_MASK XX3DM_MASK + +/* The mask for an XX4 form instruction. */ +#define XX4_MASK XX4 (0x3f, 0x3) + +/* An X form wait instruction with everything filled in except the WC field. */ +#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) + +/* The mask for a Z form instruction. */ +#define Z_MASK ZRC (0x3f, 0x1ff, 1) +#define Z2_MASK ZRC (0x3f, 0xff, 1) + +/* An X_MASK with the RA field fixed. */ +#define XRA_MASK (X_MASK | RA_MASK) + +/* An XRA_MASK with the W field clear. */ +#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) + +/* An X_MASK with the RB field fixed. */ +#define XRB_MASK (X_MASK | RB_MASK) + +/* An X_MASK with the RT field fixed. */ +#define XRT_MASK (X_MASK | RT_MASK) + +/* An XRT_MASK mask with the L bits clear. */ +#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) + +/* An X_MASK with the RA and RB fields fixed. */ +#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) + +/* An XRARB_MASK, but with the L bit clear. */ +#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) + +/* An X_MASK with the RT and RA fields fixed. */ +#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) + +/* An XRTRA_MASK, but with L bit clear. */ +#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) + +/* An X form instruction with the L bit specified. */ +#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) + +/* An X form instruction with the L bits specified. */ +#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) + +/* An X form instruction with RT fields specified */ +#define XRT(op, xop, rt) (X ((op), (xop)) \ + | ((((unsigned long)(rt)) & 0x1f) << 21)) + +/* An X form instruction with RT and RA fields specified */ +#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ + | ((((unsigned long)(rt)) & 0x1f) << 21) \ + | ((((unsigned long)(ra)) & 0x1f) << 16)) + +/* The mask for an X form comparison instruction. */ +#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) + +/* The mask for an X form comparison instruction with the L field + fixed. */ +#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) + +/* An X form trap instruction with the TO field specified. */ +#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) +#define XTO_MASK (X_MASK | TO_MASK) + +/* An X form tlb instruction with the SH field specified. */ +#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) +#define XTLB_MASK (X_MASK | SH_MASK) + +/* An X form sync instruction. */ +#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) + +/* An X form sync instruction with everything filled in except the LS field. */ +#define XSYNC_MASK (0xff9fffff) + +/* An X_MASK, but with the EH bit clear. */ +#define XEH_MASK (X_MASK & ~((unsigned long )1)) + +/* An X form AltiVec dss instruction. */ +#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) +#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) + +/* An XFL form instruction. */ +#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) +#define XFL_MASK XFL (0x3f, 0x3ff, 1) + +/* An X form isel instruction. */ +#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) +#define XISEL_MASK XISEL(0x3f, 0x1f) + +/* An XL form instruction with the LK field set to 0. */ +#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) + +/* An XL form instruction which uses the LK field. */ +#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) + +/* The mask for an XL form instruction. */ +#define XL_MASK XLLK (0x3f, 0x3ff, 1) + +/* An XL form instruction which explicitly sets the BO field. */ +#define XLO(op, bo, xop, lk) \ + (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) +#define XLO_MASK (XL_MASK | BO_MASK) + +/* An XL form instruction which explicitly sets the y bit of the BO + field. */ +#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) +#define XLYLK_MASK (XL_MASK | Y_MASK) + +/* An XL form instruction which sets the BO field and the condition + bits of the BI field. */ +#define XLOCB(op, bo, cb, xop, lk) \ + (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) +#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) + +/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ +#define XLBB_MASK (XL_MASK | BB_MASK) +#define XLYBB_MASK (XLYLK_MASK | BB_MASK) +#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) + +/* A mask for branch instructions using the BH field. */ +#define XLBH_MASK (XL_MASK | (0x1c << 11)) + +/* An XL_MASK with the BO and BB fields fixed. */ +#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) + +/* An XL_MASK with the BO, BI and BB fields fixed. */ +#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) + +/* An X form mbar instruction with MO field. */ +#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) + +/* An XO form instruction. */ +#define XO(op, xop, oe, rc) \ + (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) +#define XO_MASK XO (0x3f, 0x1ff, 1, 1) + +/* An XO_MASK with the RB field fixed. */ +#define XORB_MASK (XO_MASK | RB_MASK) + +/* An XOPS form instruction for paired singles. */ +#define XOPS(op, xop, rc) \ + (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) +#define XOPS_MASK XOPS (0x3f, 0x3ff, 1) + + +/* An XS form instruction. */ +#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) +#define XS_MASK XS (0x3f, 0x1ff, 1) + +/* A mask for the FXM version of an XFX form instruction. */ +#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) + +/* An XFX form instruction with the FXM field filled in. */ +#define XFXM(op, xop, fxm, p4) \ + (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ + | ((unsigned long)(p4) << 20)) + +/* An XFX form instruction with the SPR field filled in. */ +#define XSPR(op, xop, spr) \ + (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) +#define XSPR_MASK (X_MASK | SPR_MASK) + +/* An XFX form instruction with the SPR field filled in except for the + SPRBAT field. */ +#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) + +/* An XFX form instruction with the SPR field filled in except for the + SPRG field. */ +#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) + +/* An X form instruction with everything filled in except the E field. */ +#define XE_MASK (0xffff7fff) + +/* An X form user context instruction. */ +#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define XUC_MASK XUC(0x3f, 0x1f) + +/* An XW form instruction. */ +#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) +/* The mask for a G form instruction. rc not supported at present. */ +#define XW_MASK XW (0x3f, 0x3f, 0) + +/* An APU form instruction. */ +#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) + +/* The mask for an APU form instruction. */ +#define APU_MASK APU (0x3f, 0x3ff, 1) +#define APU_RT_MASK (APU_MASK | RT_MASK) +#define APU_RA_MASK (APU_MASK | RA_MASK) + +/* The BO encodings used in extended conditional branch mnemonics. */ +#define BODNZF (0x0) +#define BODNZFP (0x1) +#define BODZF (0x2) +#define BODZFP (0x3) +#define BODNZT (0x8) +#define BODNZTP (0x9) +#define BODZT (0xa) +#define BODZTP (0xb) + +#define BOF (0x4) +#define BOFP (0x5) +#define BOFM4 (0x6) +#define BOFP4 (0x7) +#define BOT (0xc) +#define BOTP (0xd) +#define BOTM4 (0xe) +#define BOTP4 (0xf) + +#define BODNZ (0x10) +#define BODNZP (0x11) +#define BODZ (0x12) +#define BODZP (0x13) +#define BODNZM4 (0x18) +#define BODNZP4 (0x19) +#define BODZM4 (0x1a) +#define BODZP4 (0x1b) + +#define BOU (0x14) + +/* The BI condition bit encodings used in extended conditional branch + mnemonics. */ +#define CBLT (0) +#define CBGT (1) +#define CBEQ (2) +#define CBSO (3) + +/* The TO encodings used in extended trap mnemonics. */ +#define TOLGT (0x1) +#define TOLLT (0x2) +#define TOEQ (0x4) +#define TOLGE (0x5) +#define TOLNL (0x5) +#define TOLLE (0x6) +#define TOLNG (0x6) +#define TOGT (0x8) +#define TOGE (0xc) +#define TONL (0xc) +#define TOLT (0x10) +#define TOLE (0x14) +#define TONG (0x14) +#define TONE (0x18) +#define TOU (0x1f) + +/* Smaller names for the flags so each entry in the opcodes table will + fit on a single line. */ +#define PPCNONE 0 +#undef PPC +#define PPC PPC_OPCODE_PPC +#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON +#define POWER4 PPC_OPCODE_POWER4 +#define POWER5 PPC_OPCODE_POWER5 +#define POWER6 PPC_OPCODE_POWER6 +#define POWER7 PPC_OPCODE_POWER7 +#define CELL PPC_OPCODE_CELL +#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE +#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ + | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) +#define PPC403 PPC_OPCODE_403 +#define PPC405 PPC_OPCODE_405 +#define PPC440 PPC_OPCODE_440 +#define PPC464 PPC440 +#define PPC476 PPC_OPCODE_476 +#define PPC750 PPC +#define PPC7450 PPC +#define PPC860 PPC +#define PPCPS PPC_OPCODE_PPCPS +#define PPCVEC PPC_OPCODE_ALTIVEC +#define PPCVSX PPC_OPCODE_VSX +#define POWER PPC_OPCODE_POWER +#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON +#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON +#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON +#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 +#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON +#define MFDEC1 PPC_OPCODE_POWER +#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN +#define BOOKE PPC_OPCODE_BOOKE +#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS +#define PPCE300 PPC_OPCODE_E300 +#define PPCSPE PPC_OPCODE_SPE +#define PPCISEL PPC_OPCODE_ISEL +#define PPCEFS PPC_OPCODE_EFS +#define PPCBRLK PPC_OPCODE_BRLOCK +#define PPCPMR PPC_OPCODE_PMR +#define PPCCHLK PPC_OPCODE_CACHELCK +#define PPCRFMCI PPC_OPCODE_RFMCI +#define E500MC PPC_OPCODE_E500MC +#define PPCA2 PPC_OPCODE_A2 +#define TITAN PPC_OPCODE_TITAN +#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN +#define E500 PPC_OPCODE_E500 + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK FLAGS {OPERANDS} + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + FLAGS are flags indicated what processors support the instruction. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. + + This table must be sorted by major opcode. Please try to keep it + vaguely sorted within major opcode too, except of course where + constrained otherwise by disassembler operation. */ + +const struct powerpc_opcode powerpc_opcodes[] = { +{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476, {0}}, +{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}}, + +{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, +{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, + +{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, +{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, +{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}}, +{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, +{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, +{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, +{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, +{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, +{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhw", XO (4, 44,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"macchws", XO (4, 236,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, +{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}}, +{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}}, +{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, +{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, +{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, +{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, +{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, +{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, +{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, +{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, +{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, +{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, +{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, +{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, +{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, +{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}}, +{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, +{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, +{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, +{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, +{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, +{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, +{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, +{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, +{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, +{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, +{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"mullhw", XRC(4, 424,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, +{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, +{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, +{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, +{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}}, +{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}}, +{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}}, + +{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, +{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, + +{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, +{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, + +{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}}, + +{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, +{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, +{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, +{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}}, + +{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, +{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, +{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}}, +{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}}, + +{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, +{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, +{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, + +{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, +{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, +{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, + +{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, +{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}}, +{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}}, +{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, +{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, +{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, + +{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}}, +{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}}, +{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, +{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, +{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, + +{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, +{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, +{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, +{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, +{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, +{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, +{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, +{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, +{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, +{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, +{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, +{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, +{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, +{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, +{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, +{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, +{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, +{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, +{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}}, +{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, +{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, +{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}}, +{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, +{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, +{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}}, +{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, +{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, +{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}}, + +{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, +{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, +{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, +{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, + +{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, +{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, +{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, +{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, +{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, +{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, +{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, +{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, +{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, +{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, + +{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, + +{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, +{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, +{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, +{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, +{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, +{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, +{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, +{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, +{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, +{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, +{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, +{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, + +{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, +{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, +{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, +{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, +{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, + +{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, +{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, +{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, +{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, +{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, +{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, +{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, +{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, +{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, +{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, +{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, +{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, +{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, +{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, + +{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, +{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, +{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}}, +{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, +{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, +{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}}, +{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, +{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, +{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, +{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, +{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, +{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, + +{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, +{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, +{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}}, +{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}}, +{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}}, + +{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}}, +{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}}, +{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}}, +{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}}, + +{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, + +{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, +{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, +{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, +{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, +{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, +{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, + +{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, +{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, + +{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, +{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, +{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, +{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, +{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, + +{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, +{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, +{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, +{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, + +{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}}, + +{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, +{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, +{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}}, + +{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}}, +{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}}, +{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}}, + +{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}}, + +{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, + +{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, +{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}}, + +{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, +{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}}, + +{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476, {0}}, + +{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, +{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}}, + +{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}}, + +{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, +{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, + +{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}}, +{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}}, + +{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}}, +{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}}, + +{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, +{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, +{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, +{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, + +{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, +{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, +{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, +{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, + +{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, +{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, +{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, +{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, +{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, + +{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, +{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, + +{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, +{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, + +{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, +{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, +{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, +{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, +{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, +{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, + +{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, +{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, + +{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, +{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, +{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, +{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, + +{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, +{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, +{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, + +{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, +{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, +{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, +{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, +{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, +{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, + +{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, +{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, + +{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, +{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, + +{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, +{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, + +{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, +{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, +{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, +{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, + +{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, +{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, + +{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, +{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, +{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, +{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, + +{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, +{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}}, +{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}}, +{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, + +{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, +{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, +{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, +{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, + +{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, + +{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}}, +{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}}, +{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}}, +{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}}, + +{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, +{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}}, +{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}}, + +{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}}, + +{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, + +{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}}, + +{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, +{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, +{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, + +{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, +{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, + +{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, +{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, + +{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, +{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, + +{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, +{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, +{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, +{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, +{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, + +{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, +{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, +{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, + +{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, + +{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}}, + +{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, + +{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA, RB, CRB}}, + +{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, +{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, + +{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, + +{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, + +{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, + +{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}}, + +{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}}, +{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, +{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, + +{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, +{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, +{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}}, + +{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, + +{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}}, + +{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, +{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}}, +{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}}, + +{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}}, + +{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}}, + +{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}}, + +{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA, RB}}, +{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}}, + +{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, + +{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, +{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, +{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, + +{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, + +{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, + +{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, + +{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, + +{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}}, + +{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, +{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, +{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, + +{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}}, + +{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, + +{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, +{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, + +{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, +{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, +{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, + +{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}}, + +{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, +{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, + +{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, + +{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}}, + +{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, +{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}}, + +{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}}, + +{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, + +{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, + +{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}}, + +{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, + +{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, +{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, + +{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, + +{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}}, + +{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}}, + +{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}}, + +{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}}, +{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, + +{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + +{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, + +{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, +{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}}, + +{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, + +{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}}, + +{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, + +{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, + +{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, + +{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, + +{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, + +{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, +{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, +{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}}, +{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, +{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, + +{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, +{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, +{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}}, + +{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, + +{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + +{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}}, + +{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, +{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}}, + +{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, + +{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, +{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, + +{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}}, + +{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}}, + +{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, +{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, +{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}}, + +{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, + +{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, + +{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, + +{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}}, +{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, + +{"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA, RB}}, + +{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, + +{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, + +{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}}, +{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}}, + +{"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}}, + +{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, + +{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, + +{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, +{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, +{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, +{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, +{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, +{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, +{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, +{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, +{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}}, +{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, +{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}}, +{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}}, +{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}}, +{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, +{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, +{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, +{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, +{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}}, +{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, +{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, +{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, +{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, +{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, +{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, +{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, +{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}}, +{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, +{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, +{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, +{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, +{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, +{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}}, +{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, PPCNONE, {RT}}, +{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RT}}, +{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE, {RT}}, +{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}}, +{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}}, +{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}}, +{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}}, + +{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, + +{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, + +{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, + +{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, + +{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, +{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, + +{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}}, + +{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}}, +{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}}, +{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}}, + +{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, + +{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, + +{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, + +{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}}, + +{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, +{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}}, + +{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, + +{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, + +{"icswx", XRC(31,406,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, +{"icswx.", XRC(31,406,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, + +{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, + +{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, + +{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, + +{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, + +{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA, RB}}, + +{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, + +{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, + +{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, +{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, +{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}}, +{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}}, + +{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, +{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, + +{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}}, + +{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, +{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, +{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, +{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, +{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, +{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, +{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}}, +{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, +{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}}, +{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}}, +{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}}, +{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}}, +{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, +{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, +{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, +{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, +{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}}, +{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, +{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}}, +{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, +{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, +{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, +{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, +{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, +{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, +{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}}, +{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, +{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, +{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, +{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, +{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE, {RS}}, +{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, PPCNONE, {RS}}, +{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}}, +{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}}, +{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}}, +{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}}, + +{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}}, + +{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + +{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, + +{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA, RB}}, + +{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, + +{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, + +{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, +{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, + +{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, + +{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, + +{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}}, + +{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}}, + +{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}}, + +{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}}, + +{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + +{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}}, + +{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, +{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, + +{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}}, + +{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}}, + +{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, RB}}, +{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, +{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, + +{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, +{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, + +{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, +{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, + +{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + +{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, + +{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, +{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, + +{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}}, + +{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, + +{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + +{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, + +{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, + +{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, NB}}, +{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, + +{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, +{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, +{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, +{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, +{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}}, +{"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, +{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, + +{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, + +{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, +{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}}, + +{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + +{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, +{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, + +{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"mfsri", X(31,627), X_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"dclst", X(31,630), XRB_MASK, M601, PPCNONE, {RS, RA}}, + +{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, + +{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + +{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, +{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, + +{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}}, + +{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, +{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, + +{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, +{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, + +{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, + +{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + +{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, +{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, + +{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, + +{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + +{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + +{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, + +{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, +{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, + +{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, + +{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, + +{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, +{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}}, + +{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + +{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, +{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, + +{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}}, +{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, + +{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, + +{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + +{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, + +{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}}, + +{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, + +{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, + +{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}}, +{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, + +{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, +{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, + +{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, +{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, + +{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, + +{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, + +{"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}}, + +{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, + +{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}}, + +{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, + +{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, +{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, + +{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, +{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, + +{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, + +{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA, RB}}, + +{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, + +{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, + +{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, +{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}}, +{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}}, +{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}}, + +{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, + +{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, +{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, + +{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, + +{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}}, + +{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, +{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, + +{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}}, +{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}}, + +{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, + +{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, + +{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, + +{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}}, +{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, + +{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, + +{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, +{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, + +{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, + +{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, +{"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}}, +{"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}}, + +{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, + +{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + +{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, +{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, +{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}}, + +{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, + +{"icswepx", XRC(31,950,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, +{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}}, + +{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, + +{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + +{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, +{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, + +{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, +{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, + +{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, + +{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, +{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, +{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, +{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}}, + +{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, + +{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}}, + +{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, + +{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, +{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, + +{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, + +{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}}, + +{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, +{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, + +{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, + +{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, + +{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, + +{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, +{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, + +{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, + +{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA, RB}}, + +{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}}, +{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}}, +{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}}, + +{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, +{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, +{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}}, + +{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}}, +{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}}, +{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}}, +{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}}, + +{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, +{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, + +{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}}, +{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, + +{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, + +{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, + +{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, +{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, + +{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}}, +{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, + +{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, + +{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, + +{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, + +{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, + +{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, + +{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, + +{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, + +{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, + +{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}}, +{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, + +{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, +{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, + +{"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, + +{"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, + +{"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, + +{"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, + +{"stfs", OP(52), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, + +{"stfsu", OP(53), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, + +{"stfd", OP(54), OP_MASK, COM, PPCEFS, {FRS, D, RA0}}, + +{"stfdu", OP(55), OP_MASK, COM, PPCEFS, {FRS, D, RAS}}, + +{"lq", OP(56), OP_MASK, POWER4, PPC476, {RTQ, DQ, RAQ}}, +{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, +{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, + +{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, +{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, +{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, + +{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, +{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, +{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, + +{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, +{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, + +{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, + +{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, + +{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, +{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS, {FRT, FRA, FRB}}, + +{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}}, +{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN, {FRT, FRB}}, + +{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, +{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, + +{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, +{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS, {FRT, FRA, FRC}}, + +{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, +{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, + +{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, + +{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, + +{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, + +{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, + +{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, +{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, + +{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, +{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, + +{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, +{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, + +{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, +{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, + +{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, +{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, + +{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, +{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, +{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, + +{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, +{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, + +{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, +{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, + +{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, + +{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, +{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, + +{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, + +{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, + +{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, +{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, +{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, +{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, +{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}}, +{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, +{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, +{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, +{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, + +{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, +{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, + +{"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}}, +{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, +{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, + +{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, +{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, +{"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}}, + +{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, + +{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, +{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, + +{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, +{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, + +{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, + +{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, +{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, +{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, +{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, + +{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, +{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, +{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS, {FRT, FRB}}, +{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCNONE, {FRT, FRB}}, + +{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, + +{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, + +{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, +{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRB}}, +{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, + +{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}}, +{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN, {FRT, FRB}}, + +{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS, {FRT, FRA, FRC, FRB}}, + +{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, +{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, + +{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, +{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, +{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC}}, +{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, + +{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, +{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, + +{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, + +{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, + +{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, + +{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, +{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, +{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, + +{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, + +{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, +{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, + +{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, +{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, + +{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, + +{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, + +{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, +{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, + +{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, +{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, + +{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}}, +{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}}, + +{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, + +{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, +{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, + +{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, +{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, + +{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}}, + +{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, +{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, +{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, +{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, + +{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, + +{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, +{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, + +{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, + +{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, +{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, +{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, + +{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, +{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, + +{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, +{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, + +{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, +{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, + +{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, +{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, + +{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}}, +{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}}, + +{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, + +{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, +{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, +{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, +{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, + +{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, +{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, + +{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, +{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, + +{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, +{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, + +{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, +{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, + +{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, +{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, +{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, + +{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, +{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, + +{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, + +{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, + +{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, +}; + +const int powerpc_num_opcodes = + sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); + +/* The macro table. This is only used by the assembler. */ + +/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 + when x=0; 32-x when x is between 1 and 31; are negative if x is + negative; and are 32 or more otherwise. This is what you want + when, for instance, you are emulating a right shift by a + rotate-left-and-mask, because the underlying instructions support + shifts of size 0 but not shifts of size 32. By comparison, when + extracting x bits from some word you want to use just 32-x, because + the underlying instructions don't support extracting 0 bits but do + support extracting the whole word (32 bits in this case). */ + +const struct powerpc_macro powerpc_macros[] = { +{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, +{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, +{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, +{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, +{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, +{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, +{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, +{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, +{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, +{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, +{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, +{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, +{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, +{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, +{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, +{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, + +{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, +{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, +{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, +{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, +{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, +{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, +{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, +{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, +{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, +{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, +{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, +{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, +{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, +{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, +{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, +{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, +{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, +{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, +{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, +{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, +{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, +{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, +}; + +const int powerpc_num_macros = + sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); diff --git a/external/gpl3/gdb/dist/opcodes/rx-decode.c b/external/gpl3/gdb/dist/opcodes/rx-decode.c new file mode 100644 index 000000000000..8797b1baef28 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/rx-decode.c @@ -0,0 +1,14832 @@ +#line 1 "rx-decode.opc" +/* -*- c -*- */ +#include +#include +#include + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rx.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +typedef struct +{ + RX_Opcode_Decoded * rx; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +static int trace = 0; + +#define BSIZE 0 +#define WSIZE 1 +#define LSIZE 2 + +/* These are for when the upper bits are "don't care" or "undefined". */ +static int bwl[] = +{ + RX_Byte, + RX_Word, + RX_Long +}; + +static int sbwl[] = +{ + RX_SByte, + RX_SWord, + RX_Long +}; + +static int ubwl[] = +{ + RX_UByte, + RX_UWord, + RX_Long +}; + +static int memex[] = +{ + RX_SByte, + RX_SWord, + RX_Long, + RX_UWord +}; + +#define ID(x) rx->id = RXO_##x +#define OP(n,t,r,a) (rx->op[n].type = t, \ + rx->op[n].reg = r, \ + rx->op[n].addend = a ) +#define OPs(n,t,r,a,s) (OP (n,t,r,a), \ + rx->op[n].size = s ) + +/* This is for the BWL and BW bitfields. */ +static int SCALE[] = { 1, 2, 4 }; +/* This is for the prefix size enum. */ +static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; + +static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, + 16, 17, 0, 0, 0, 0, 0, 0 }; + +static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; + +/* + *C a constant (immediate) c + *R A register + *I Register indirect, no offset + *Is Register indirect, with offset + *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code + *P standard displacement: type (r,[r]), reg, assumes UByte + *Pm memex displacement: type (r,[r]), reg, memex code + *cc condition code. */ + +#define DC(c) OP (0, RX_Operand_Immediate, 0, c) +#define DR(r) OP (0, RX_Operand_Register, r, 0) +#define DI(r,a) OP (0, RX_Operand_Indirect, r, a) +#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); +#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) + +#define SC(i) OP (1, RX_Operand_Immediate, 0, i) +#define SR(r) OP (1, RX_Operand_Register, r, 0) +#define SRR(r) OP (1, RX_Operand_TwoReg, r, 0) +#define SI(r,a) OP (1, RX_Operand_Indirect, r, a) +#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); +#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); +#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; +#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) + +#define S2C(i) OP (2, RX_Operand_Immediate, 0, i) +#define S2R(r) OP (2, RX_Operand_Register, r, 0) +#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) +#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); +#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); +#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; +#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) + +#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] +#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] +#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] +#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; + +#define F(f) store_flags(rx, f) + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr)) + +#define SYNTAX(x) rx->syntax = x + +#define UNSUPPORTED() \ + rx->syntax = "*unknown*" + +#define IMM(sf) immediate (sf, 0, ld) +#define IMMex(sf) immediate (sf, 1, ld) + +static int +immediate (int sfield, int ex, LocalData * ld) +{ + unsigned long i = 0, j; + + switch (sfield) + { +#define B ((unsigned long) GETBYTE()) + case 0: +#if RX_OPCODE_BIG_ENDIAN + i = B; + if (ex && (i & 0x80)) + i -= 0x100; + i <<= 24; + i |= B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; + j = B; + if (ex && (j & 0x80)) + j -= 0x100; + i |= j << 24; +#endif + break; + case 3: +#if RX_OPCODE_BIG_ENDIAN + i = B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; +#endif + if (ex && (i & 0x800000)) + i -= 0x1000000; + break; + case 2: +#if RX_OPCODE_BIG_ENDIAN + i |= B << 8; + i |= B; +#else + i |= B; + i |= B << 8; +#endif + if (ex && (i & 0x8000)) + i -= 0x10000; + break; + case 1: + i |= B; + if (ex && (i & 0x80)) + i -= 0x100; + break; + default: + abort(); + } + return i; +} + +static void +rx_disp (int n, int type, int reg, int size, LocalData * ld) +{ + int disp; + + ld->rx->op[n].reg = reg; + switch (type) + { + case 3: + ld->rx->op[n].type = RX_Operand_Register; + break; + case 0: + ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].addend = 0; + break; + case 1: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + case 2: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); +#if RX_OPCODE_BIG_ENDIAN + disp = disp * 256 + GETBYTE (); +#else + disp = disp + GETBYTE () * 256; +#endif + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + default: + abort (); + } +} + +#define xO 8 +#define xS 4 +#define xZ 2 +#define xC 1 + +#define F_____ +#define F___ZC rx->flags_0 = rx->flags_s = xZ|xC; +#define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ; +#define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC; +#define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC; +#define F_O___ rx->flags_0 = rx->flags_s = xO; +#define F_OS__ rx->flags_0 = rx->flags_s = xO|xS; +#define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ; +#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC; + +int +rx_decode_opcode (unsigned long pc AU, + RX_Opcode_Decoded * rx, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op[20] = {0}; + + lds.rx = rx; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rx, 0, sizeof (*rx)); + BWL(LSIZE); + + +/*----------------------------------------------------------------------*/ +/* MOV */ + + GETBYTE (); + switch (op[0] & 0xff) + { + case 0x00: + { + /** 0000 0000 brk */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0000 brk */", + op[0]); + } + SYNTAX("brk"); +#line 941 "rx-decode.opc" + ID(brk); + + } + break; + case 0x01: + { + /** 0000 0001 dbt */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0001 dbt */", + op[0]); + } + SYNTAX("dbt"); +#line 944 "rx-decode.opc" + ID(dbt); + + } + break; + case 0x02: + { + /** 0000 0010 rts */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0010 rts */", + op[0]); + } + SYNTAX("rts"); +#line 730 "rx-decode.opc" + ID(rts); + + /*----------------------------------------------------------------------*/ + /* NOP */ + + } + break; + case 0x03: + { + /** 0000 0011 nop */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0011 nop */", + op[0]); + } + SYNTAX("nop"); +#line 736 "rx-decode.opc" + ID(nop); + + /*----------------------------------------------------------------------*/ + /* STRING FUNCTIONS */ + + } + break; + case 0x04: + { + /** 0000 0100 bra.a %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0100 bra.a %a0 */", + op[0]); + } + SYNTAX("bra.a %a0"); +#line 708 "rx-decode.opc" + ID(branch); DC(pc + IMMex(3)); + + } + break; + case 0x05: + { + /** 0000 0101 bsr.a %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 0101 bsr.a %a0 */", + op[0]); + } + SYNTAX("bsr.a %a0"); +#line 724 "rx-decode.opc" + ID(jsr); DC(pc + IMMex(3)); + + } + break; + case 0x06: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_1: + { + /** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */ +#line 505 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 505 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 505 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 505 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub %2%S2, %1"); +#line 505 "rx-decode.opc" + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_2: + { + /** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */ +#line 493 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 493 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 493 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 493 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp %2%S2, %1"); +#line 493 "rx-decode.opc" + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* SUB */ + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_3: + { + /** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */ +#line 469 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 469 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 469 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 469 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add %1%S1, %0"); +#line 469 "rx-decode.opc" + ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_4: + { + /** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */ +#line 573 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 573 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 573 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 573 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul %1%S1, %0"); +#line 573 "rx-decode.opc" + ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____; + + } + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_5: + { + /** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */ +#line 382 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 382 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 382 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 382 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and %1%S1, %0"); +#line 382 "rx-decode.opc" + ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_6: + { + /** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */ +#line 400 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 400 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 400 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 400 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or %1%S1, %0"); +#line 400 "rx-decode.opc" + ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_7: + { + /** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */ +#line 518 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 518 "rx-decode.opc" + int sp AU = op[1] & 0x03; +#line 518 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 518 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" sp = 0x%x,", sp); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sbb %1%S1, %0"); +#line 518 "rx-decode.opc" + ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* ABS */ + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_8: + { + /** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */ +#line 546 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 546 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 546 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 546 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max %1%S1, %0"); +#line 546 "rx-decode.opc" + ID(max); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* MIN */ + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_9: + { + /** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */ +#line 558 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 558 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 558 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 558 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min %1%S1, %0"); +#line 558 "rx-decode.opc" + ID(min); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* MUL */ + + } + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_10: + { + /** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */ +#line 588 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 588 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 588 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 588 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul %1%S1, %0"); +#line 588 "rx-decode.opc" + ID(emul); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* EMULU */ + + } + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_11: + { + /** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */ +#line 600 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 600 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 600 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 600 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu %1%S1, %0"); +#line 600 "rx-decode.opc" + ID(emulu); SPm(ss, rsrc, mx); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* DIV */ + + } + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_12: + { + /** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */ +#line 612 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 612 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 612 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 612 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div %1%S1, %0"); +#line 612 "rx-decode.opc" + ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___; + + /*----------------------------------------------------------------------*/ + /* DIVU */ + + } + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_13: + { + /** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */ +#line 624 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 624 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 624 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 624 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu %1%S1, %0"); +#line 624 "rx-decode.opc" + ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___; + + /*----------------------------------------------------------------------*/ + /* SHIFT */ + + } + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_14: + { + /** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */ +#line 436 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 436 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 436 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 436 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst %1%S1, %2"); +#line 436 "rx-decode.opc" + ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* NEG */ + + } + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_15: + { + /** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */ +#line 415 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 415 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 415 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 415 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor %1%S1, %0"); +#line 415 "rx-decode.opc" + ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* NOT */ + + } + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_16: + { + /** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */ +#line 349 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 349 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 349 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 349 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xchg %1%S1, %0"); +#line 349 "rx-decode.opc" + ID(xchg); DR(rdst); SPm(ss, rsrc, mx); + + /*----------------------------------------------------------------------*/ + /* STZ/STNZ */ + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_17: + { + /** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */ +#line 853 "rx-decode.opc" + int mx AU = (op[1] >> 6) & 0x03; +#line 853 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 853 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 853 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" mx = 0x%x,", mx); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("itof %1%S1, %0"); +#line 853 "rx-decode.opc" + ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* BIT OPS */ + + } + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + op_semantics_18: + { + /** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */ +#line 457 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 457 "rx-decode.opc" + int rsrc AU = (op[3] >> 4) & 0x0f; +#line 457 "rx-decode.opc" + int rdst AU = op[3] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x %02x\n", + "/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */", + op[0], op[1], op[2], op[3]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc %1%S1, %0"); +#line 457 "rx-decode.opc" + ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* ADD */ + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_18; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_1; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_2; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_3; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_4; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_5; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_6; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_7; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_8; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_9; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_10; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_11; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_12; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_13; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_14; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_15; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_16; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[3] & 0x00) + { + case 0x00: + goto op_semantics_17; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + { + /** 0000 1dsp bra.s %a0 */ +#line 699 "rx-decode.opc" + int dsp AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0000 1dsp bra.s %a0 */", + op[0]); + printf (" dsp = 0x%x\n", dsp); + } + SYNTAX("bra.s %a0"); +#line 699 "rx-decode.opc" + ID(branch); DC(pc + dsp3map[dsp]); + + } + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + /** 0001 n dsp b%1.s %a0 */ +#line 689 "rx-decode.opc" + int n AU = (op[0] >> 3) & 0x01; +#line 689 "rx-decode.opc" + int dsp AU = op[0] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0001 n dsp b%1.s %a0 */", + op[0]); + printf (" n = 0x%x,", n); + printf (" dsp = 0x%x\n", dsp); + } + SYNTAX("b%1.s %a0"); +#line 689 "rx-decode.opc" + ID(branch); Scc(n); DC(pc + dsp3map[dsp]); + + } + break; + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2f: + { + /** 0010 cond b%1.b %a0 */ +#line 692 "rx-decode.opc" + int cond AU = op[0] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 cond b%1.b %a0 */", + op[0]); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("b%1.b %a0"); +#line 692 "rx-decode.opc" + ID(branch); Scc(cond); DC(pc + IMMex (1)); + + } + break; + case 0x2e: + { + /** 0010 1110 bra.b %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0010 1110 bra.b %a0 */", + op[0]); + } + SYNTAX("bra.b %a0"); +#line 702 "rx-decode.opc" + ID(branch); DC(pc + IMMex(1)); + + } + break; + case 0x38: + { + /** 0011 1000 bra.w %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1000 bra.w %a0 */", + op[0]); + } + SYNTAX("bra.w %a0"); +#line 705 "rx-decode.opc" + ID(branch); DC(pc + IMMex(2)); + + } + break; + case 0x39: + { + /** 0011 1001 bsr.w %a0 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 1001 bsr.w %a0 */", + op[0]); + } + SYNTAX("bsr.w %a0"); +#line 721 "rx-decode.opc" + ID(jsr); DC(pc + IMMex(2)); + + } + break; + case 0x3a: + case 0x3b: + { + /** 0011 101c b%1.w %a0 */ +#line 695 "rx-decode.opc" + int c AU = op[0] & 0x01; + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0011 101c b%1.w %a0 */", + op[0]); + printf (" c = 0x%x\n", c); + } + SYNTAX("b%1.w %a0"); +#line 695 "rx-decode.opc" + ID(branch); Scc(c); DC(pc + IMMex (2)); + + + } + break; + case 0x3c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_19: + { + /** 0011 11sz d dst sppp mov%s #%1, %0 */ +#line 271 "rx-decode.opc" + int sz AU = op[0] & 0x03; +#line 271 "rx-decode.opc" + int d AU = (op[1] >> 7) & 0x01; +#line 271 "rx-decode.opc" + int dst AU = (op[1] >> 4) & 0x07; +#line 271 "rx-decode.opc" + int sppp AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 11sz d dst sppp mov%s #%1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" d = 0x%x,", d); + printf (" dst = 0x%x,", dst); + printf (" sppp = 0x%x\n", sppp); + } + SYNTAX("mov%s #%1, %0"); +#line 271 "rx-decode.opc" + ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; + + } + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_19; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_19; + break; + } + break; + case 0x3f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0011 1111 rega regb rtsd #%1, %2-%0 */ +#line 367 "rx-decode.opc" + int rega AU = (op[1] >> 4) & 0x0f; +#line 367 "rx-decode.opc" + int regb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0011 1111 rega regb rtsd #%1, %2-%0 */", + op[0], op[1]); + printf (" rega = 0x%x,", rega); + printf (" regb = 0x%x\n", regb); + } + SYNTAX("rtsd #%1, %2-%0"); +#line 367 "rx-decode.opc" + ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); + + /*----------------------------------------------------------------------*/ + /* AND */ + + } + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_20: + { + /** 0100 00ss rsrc rdst sub %2%S2, %1 */ +#line 502 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 502 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 502 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 00ss rsrc rdst sub %2%S2, %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub %2%S2, %1"); +#line 502 "rx-decode.opc" + ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_20; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_21: + { + /** 0100 01ss rsrc rdst cmp %2%S2, %1 */ +#line 490 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 490 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 490 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 01ss rsrc rdst cmp %2%S2, %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp %2%S2, %1"); +#line 490 "rx-decode.opc" + ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC; + + } + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_21; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_22: + { + /** 0100 10ss rsrc rdst add %1%S1, %0 */ +#line 466 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 466 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 466 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 10ss rsrc rdst add %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add %1%S1, %0"); +#line 466 "rx-decode.opc" + ID(add); SP(ss, rsrc); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_22; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_23: + { + /** 0100 11ss rsrc rdst mul %1%S1, %0 */ +#line 570 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 570 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 570 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0100 11ss rsrc rdst mul %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul %1%S1, %0"); +#line 570 "rx-decode.opc" + ID(mul); SP(ss, rsrc); DR(rdst); F_____; + + } + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_23; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_24: + { + /** 0101 00ss rsrc rdst and %1%S1, %0 */ +#line 379 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 379 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 379 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 00ss rsrc rdst and %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and %1%S1, %0"); +#line 379 "rx-decode.opc" + ID(and); SP(ss, rsrc); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_24; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_25: + { + /** 0101 01ss rsrc rdst or %1%S1, %0 */ +#line 397 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 397 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 397 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 01ss rsrc rdst or %1%S1, %0 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or %1%S1, %0"); +#line 397 "rx-decode.opc" + ID(or); SP(ss, rsrc); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_25; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_26: + { + /** 0101 1 s ss rsrc rdst movu%s %1, %0 */ +#line 318 "rx-decode.opc" + int s AU = (op[0] >> 2) & 0x01; +#line 318 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 318 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 318 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0101 1 s ss rsrc rdst movu%s %1, %0 */", + op[0], op[1]); + printf (" s = 0x%x,", s); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s %1, %0"); +#line 318 "rx-decode.opc" + ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____; + + } + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_26; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0000 immm rdst sub #%2, %0 */ +#line 499 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 499 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0000 immm rdst sub #%2, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sub #%2, %0"); +#line 499 "rx-decode.opc" + ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0001 immm rdst cmp #%2, %1 */ +#line 481 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 481 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0001 immm rdst cmp #%2, %1 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("cmp #%2, %1"); +#line 481 "rx-decode.opc" + ID(sub); S2C(immm); SR(rdst); F_OSZC; + + } + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0010 immm rdst add #%1, %0 */ +#line 463 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 463 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0010 immm rdst add #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add #%1, %0"); +#line 463 "rx-decode.opc" + ID(add); SC(immm); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0011 immm rdst mul #%1, %0 */ +#line 564 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 564 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0011 immm rdst mul #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul #%1, %0"); +#line 564 "rx-decode.opc" + ID(mul); DR(rdst); SC(immm); F_____; + + } + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0100 immm rdst and #%1, %0 */ +#line 373 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 373 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0100 immm rdst and #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and #%1, %0"); +#line 373 "rx-decode.opc" + ID(and); SC(immm); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0101 immm rdst or #%1, %0 */ +#line 391 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 391 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0101 immm rdst or #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or #%1, %0"); +#line 391 "rx-decode.opc" + ID(or); SC(immm); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 0110 immm rdst mov%s #%1, %0 */ +#line 268 "rx-decode.opc" + int immm AU = (op[1] >> 4) & 0x0f; +#line 268 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 0110 immm rdst mov%s #%1, %0 */", + op[0], op[1]); + printf (" immm = 0x%x,", immm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s #%1, %0"); +#line 268 "rx-decode.opc" + ID(mov); DR(rdst); SC(immm); F_____; + + } + break; + } + break; + case 0x67: + { + /** 0110 0111 rtsd #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x\n", + "/** 0110 0111 rtsd #%1 */", + op[0]); + } + SYNTAX("rtsd #%1"); +#line 364 "rx-decode.opc" + ID(rtsd); SC(IMM(1) * 4); + + } + break; + case 0x68: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_27: + { + /** 0110 100i mmmm rdst shlr #%2, %0 */ +#line 650 "rx-decode.opc" + int i AU = op[0] & 0x01; +#line 650 "rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 650 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 100i mmmm rdst shlr #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr #%2, %0"); +#line 650 "rx-decode.opc" + ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_27; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_28: + { + /** 0110 101i mmmm rdst shar #%2, %0 */ +#line 640 "rx-decode.opc" + int i AU = op[0] & 0x01; +#line 640 "rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 640 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 101i mmmm rdst shar #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar #%2, %0"); +#line 640 "rx-decode.opc" + ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC; + + } + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_28; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_29: + { + /** 0110 110i mmmm rdst shll #%2, %0 */ +#line 630 "rx-decode.opc" + int i AU = op[0] & 0x01; +#line 630 "rx-decode.opc" + int mmmm AU = (op[1] >> 4) & 0x0f; +#line 630 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 110i mmmm rdst shll #%2, %0 */", + op[0], op[1]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll #%2, %0"); +#line 630 "rx-decode.opc" + ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_29; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 1110 dsta dstb pushm %1-%2 */ +#line 331 "rx-decode.opc" + int dsta AU = (op[1] >> 4) & 0x0f; +#line 331 "rx-decode.opc" + int dstb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 1110 dsta dstb pushm %1-%2 */", + op[0], op[1]); + printf (" dsta = 0x%x,", dsta); + printf (" dstb = 0x%x\n", dstb); + } + SYNTAX("pushm %1-%2"); +#line 331 "rx-decode.opc" + ID(pushm); SR(dsta); S2R(dstb); F_____; + + } + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + { + /** 0110 1111 dsta dstb popm %1-%2 */ +#line 328 "rx-decode.opc" + int dsta AU = (op[1] >> 4) & 0x0f; +#line 328 "rx-decode.opc" + int dstb AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0110 1111 dsta dstb popm %1-%2 */", + op[0], op[1]); + printf (" dsta = 0x%x,", dsta); + printf (" dstb = 0x%x\n", dstb); + } + SYNTAX("popm %1-%2"); +#line 328 "rx-decode.opc" + ID(popm); SR(dsta); S2R(dstb); F_____; + + } + break; + } + break; + case 0x70: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_30: + { + /** 0111 00im rsrc rdst add #%1, %2, %0 */ +#line 472 "rx-decode.opc" + int im AU = op[0] & 0x03; +#line 472 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 472 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 00im rsrc rdst add #%1, %2, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("add #%1, %2, %0"); +#line 472 "rx-decode.opc" + ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x71: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x72: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x73: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_30; + break; + } + break; + case 0x74: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + op_semantics_31: + { + /** 0111 01im 0000 rsrc cmp #%2, %1%S1 */ +#line 484 "rx-decode.opc" + int im AU = op[0] & 0x03; +#line 484 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("cmp #%2, %1%S1"); +#line 484 "rx-decode.opc" + ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC; + + } + break; + case 0x10: + op_semantics_32: + { + /** 0111 01im 0001rdst mul #%1, %0 */ +#line 567 "rx-decode.opc" + int im AU = op[0] & 0x03; +#line 567 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0001rdst mul #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mul #%1, %0"); +#line 567 "rx-decode.opc" + ID(mul); DR(rdst); SC(IMMex(im)); F_____; + + } + break; + case 0x20: + op_semantics_33: + { + /** 0111 01im 0010 rdst and #%1, %0 */ +#line 376 "rx-decode.opc" + int im AU = op[0] & 0x03; +#line 376 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0010 rdst and #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("and #%1, %0"); +#line 376 "rx-decode.opc" + ID(and); SC(IMMex(im)); DR(rdst); F__SZ_; + + } + break; + case 0x30: + op_semantics_34: + { + /** 0111 01im 0011 rdst or #%1, %0 */ +#line 394 "rx-decode.opc" + int im AU = op[0] & 0x03; +#line 394 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 01im 0011 rdst or #%1, %0 */", + op[0], op[1]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("or #%1, %0"); +#line 394 "rx-decode.opc" + ID(or); SC(IMMex(im)); DR(rdst); F__SZ_; + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x75: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + goto op_semantics_31; + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + goto op_semantics_32; + break; + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + goto op_semantics_33; + break; + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + case 0x3c: + case 0x3d: + case 0x3e: + case 0x3f: + goto op_semantics_34; + break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + { + /** 0111 0101 0100 rdst mov%s #%1, %0 */ +#line 262 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0100 rdst mov%s #%1, %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s #%1, %0"); +#line 262 "rx-decode.opc" + ID(mov); DR(rdst); SC(IMM (1)); F_____; + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + { + /** 0111 0101 0101 rsrc cmp #%2, %1 */ +#line 487 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0101 rsrc cmp #%2, %1 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("cmp #%2, %1"); +#line 487 "rx-decode.opc" + ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC; + + } + break; + case 0x60: + { + /** 0111 0101 0110 0000 int #%1 */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 0101 0110 0000 int #%1 */", + op[0], op[1]); + } + SYNTAX("int #%1"); +#line 947 "rx-decode.opc" + ID(int); SC(IMM(1)); + + } + break; + case 0x70: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 0111 0101 0111 0000 0000 immm mvtipl #%1 */ +#line 914 "rx-decode.opc" + int immm AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 0111 0101 0111 0000 0000 immm mvtipl #%1 */", + op[0], op[1], op[2]); + printf (" immm = 0x%x\n", immm); + } + SYNTAX("mvtipl #%1"); +#line 914 "rx-decode.opc" + ID(mvtipl); SC(immm); + + } + break; + default: UNSUPPORTED(); break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x76: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + goto op_semantics_31; + break; + case 0x10: + goto op_semantics_32; + break; + case 0x20: + goto op_semantics_33; + break; + case 0x30: + goto op_semantics_34; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x77: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + goto op_semantics_31; + break; + case 0x10: + goto op_semantics_32; + break; + case 0x20: + goto op_semantics_33; + break; + case 0x30: + goto op_semantics_34; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x78: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_35: + { + /** 0111 100b ittt rdst bset #%1, %0 */ +#line 865 "rx-decode.opc" + int b AU = op[0] & 0x01; +#line 865 "rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 865 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 100b ittt rdst bset #%1, %0 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bset #%1, %0"); +#line 865 "rx-decode.opc" + ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; + + + } + break; + } + break; + case 0x79: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_35; + break; + } + break; + case 0x7a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_36: + { + /** 0111 101b ittt rdst bclr #%1, %0 */ +#line 875 "rx-decode.opc" + int b AU = op[0] & 0x01; +#line 875 "rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 875 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 101b ittt rdst bclr #%1, %0 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bclr #%1, %0"); +#line 875 "rx-decode.opc" + ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; + + + } + break; + } + break; + case 0x7b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_36; + break; + } + break; + case 0x7c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_37: + { + /** 0111 110b ittt rdst btst #%2, %1 */ +#line 885 "rx-decode.opc" + int b AU = op[0] & 0x01; +#line 885 "rx-decode.opc" + int ittt AU = (op[1] >> 4) & 0x0f; +#line 885 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 110b ittt rdst btst #%2, %1 */", + op[0], op[1]); + printf (" b = 0x%x,", b); + printf (" ittt = 0x%x,", ittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("btst #%2, %1"); +#line 885 "rx-decode.opc" + ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC; + + + } + break; + } + break; + case 0x7d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_37; + break; + } + break; + case 0x7e: + GETBYTE (); + switch (op[1] & 0xf0) + { + case 0x00: + { + /** 0111 1110 0000 rdst not %0 */ +#line 421 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0000 rdst not %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("not %0"); +#line 421 "rx-decode.opc" + ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_; + + } + break; + case 0x10: + { + /** 0111 1110 0001 rdst neg %0 */ +#line 442 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0001 rdst neg %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("neg %0"); +#line 442 "rx-decode.opc" + ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC; + + } + break; + case 0x20: + { + /** 0111 1110 0010 rdst abs %0 */ +#line 524 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0010 rdst abs %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("abs %0"); +#line 524 "rx-decode.opc" + ID(abs); DR(rdst); SR(rdst); F_OSZ_; + + } + break; + case 0x30: + { + /** 0111 1110 0011 rdst sat %0 */ +#line 805 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0011 rdst sat %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sat %0"); +#line 805 "rx-decode.opc" + ID(sat); DR (rdst); + + } + break; + case 0x40: + { + /** 0111 1110 0100 rdst rorc %0 */ +#line 665 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0100 rdst rorc %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rorc %0"); +#line 665 "rx-decode.opc" + ID(rorc); DR(rdst); F__SZC; + + } + break; + case 0x50: + { + /** 0111 1110 0101 rdst rolc %0 */ +#line 662 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 0101 rdst rolc %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rolc %0"); +#line 662 "rx-decode.opc" + ID(rolc); DR(rdst); F__SZC; + + } + break; + case 0x80: + case 0x90: + case 0xa0: + { + /** 0111 1110 10sz rsrc push%s %1 */ +#line 337 "rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 337 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 10sz rsrc push%s %1 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("push%s %1"); +#line 337 "rx-decode.opc" + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____; + + } + break; + case 0xb0: + { + /** 0111 1110 1011 rdst pop %0 */ +#line 334 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 1011 rdst pop %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("pop %0"); +#line 334 "rx-decode.opc" + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____; + + } + break; + case 0xc0: + case 0xd0: + { + /** 0111 1110 110 crsrc pushc %1 */ +#line 920 "rx-decode.opc" + int crsrc AU = op[1] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 110 crsrc pushc %1 */", + op[0], op[1]); + printf (" crsrc = 0x%x\n", crsrc); + } + SYNTAX("pushc %1"); +#line 920 "rx-decode.opc" + ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16); + + } + break; + case 0xe0: + case 0xf0: + { + /** 0111 1110 111 crdst popc %0 */ +#line 917 "rx-decode.opc" + int crdst AU = op[1] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1110 111 crdst popc %0 */", + op[0], op[1]); + printf (" crdst = 0x%x\n", crdst); + } + SYNTAX("popc %0"); +#line 917 "rx-decode.opc" + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7f: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + { + /** 0111 1111 0000 rsrc jmp %0 */ +#line 715 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0000 rsrc jmp %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("jmp %0"); +#line 715 "rx-decode.opc" + ID(branch); DR(rsrc); + + } + break; + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + { + /** 0111 1111 0001 rsrc jsr %0 */ +#line 718 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0001 rsrc jsr %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("jsr %0"); +#line 718 "rx-decode.opc" + ID(jsr); DR(rsrc); + + } + break; + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + { + /** 0111 1111 0100 rsrc bra.l %0 */ +#line 711 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0100 rsrc bra.l %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bra.l %0"); +#line 711 "rx-decode.opc" + ID(branchrel); DR(rsrc); + + + } + break; + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + { + /** 0111 1111 0101 rsrc bsr.l %0 */ +#line 727 "rx-decode.opc" + int rsrc AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 0101 rsrc bsr.l %0 */", + op[0], op[1]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bsr.l %0"); +#line 727 "rx-decode.opc" + ID(jsrrel); DR(rsrc); + + } + break; + case 0x80: + case 0x81: + case 0x82: + { + /** 0111 1111 1000 00sz suntil%s */ +#line 751 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 00sz suntil%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("suntil%s"); +#line 751 "rx-decode.opc" + ID(suntil); BWL(sz); F___ZC; + + } + break; + case 0x83: + { + /** 0111 1111 1000 0011 scmpu */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 0011 scmpu */", + op[0], op[1]); + } + SYNTAX("scmpu"); +#line 742 "rx-decode.opc" + ID(scmpu); F___ZC; + + } + break; + case 0x84: + case 0x85: + case 0x86: + { + /** 0111 1111 1000 01sz swhile%s */ +#line 754 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 01sz swhile%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("swhile%s"); +#line 754 "rx-decode.opc" + ID(swhile); BWL(sz); F___ZC; + + } + break; + case 0x87: + { + /** 0111 1111 1000 0111 smovu */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 0111 smovu */", + op[0], op[1]); + } + SYNTAX("smovu"); +#line 745 "rx-decode.opc" + ID(smovu); + + } + break; + case 0x88: + case 0x89: + case 0x8a: + { + /** 0111 1111 1000 10sz sstr%s */ +#line 760 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 10sz sstr%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("sstr%s"); +#line 760 "rx-decode.opc" + ID(sstr); BWL(sz); + + /*----------------------------------------------------------------------*/ + /* RMPA */ + + } + break; + case 0x8b: + { + /** 0111 1111 1000 1011 smovb */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 1011 smovb */", + op[0], op[1]); + } + SYNTAX("smovb"); +#line 748 "rx-decode.opc" + ID(smovb); + + } + break; + case 0x8c: + case 0x8d: + case 0x8e: + { + /** 0111 1111 1000 11sz rmpa%s */ +#line 766 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 11sz rmpa%s */", + op[0], op[1]); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("rmpa%s"); +#line 766 "rx-decode.opc" + ID(rmpa); BWL(sz); F_OS__; + + /*----------------------------------------------------------------------*/ + /* HI/LO stuff */ + + } + break; + case 0x8f: + { + /** 0111 1111 1000 1111 smovf */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1000 1111 smovf */", + op[0], op[1]); + } + SYNTAX("smovf"); +#line 757 "rx-decode.opc" + ID(smovf); + + } + break; + case 0x93: + { + /** 0111 1111 1001 0011 satr */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0011 satr */", + op[0], op[1]); + } + SYNTAX("satr"); +#line 808 "rx-decode.opc" + ID(satr); + + /*----------------------------------------------------------------------*/ + /* FLOAT */ + + } + break; + case 0x94: + { + /** 0111 1111 1001 0100 rtfi */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0100 rtfi */", + op[0], op[1]); + } + SYNTAX("rtfi"); +#line 935 "rx-decode.opc" + ID(rtfi); + + } + break; + case 0x95: + { + /** 0111 1111 1001 0101 rte */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0101 rte */", + op[0], op[1]); + } + SYNTAX("rte"); +#line 938 "rx-decode.opc" + ID(rte); + + } + break; + case 0x96: + { + /** 0111 1111 1001 0110 wait */ + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1001 0110 wait */", + op[0], op[1]); + } + SYNTAX("wait"); +#line 950 "rx-decode.opc" + ID(wait); + + /*----------------------------------------------------------------------*/ + /* SCcnd */ + + } + break; + case 0xa0: + case 0xa1: + case 0xa2: + case 0xa3: + case 0xa4: + case 0xa5: + case 0xa6: + case 0xa7: + case 0xa8: + case 0xa9: + case 0xaa: + case 0xab: + case 0xac: + case 0xad: + case 0xae: + case 0xaf: + { + /** 0111 1111 1010 rdst setpsw %0 */ +#line 911 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1010 rdst setpsw %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("setpsw %0"); +#line 911 "rx-decode.opc" + ID(setpsw); DF(rdst); + + } + break; + case 0xb0: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + case 0xb8: + case 0xb9: + case 0xba: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + case 0xbf: + { + /** 0111 1111 1011 rdst clrpsw %0 */ +#line 908 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 0111 1111 1011 rdst clrpsw %0 */", + op[0], op[1]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("clrpsw %0"); +#line 908 "rx-decode.opc" + ID(clrpsw); DF(rdst); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_38: + { + /** 10sz 0dsp a dst b src mov%s %1, %0 */ +#line 295 "rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 295 "rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 295 "rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 295 "rx-decode.opc" + int dst AU = (op[1] >> 4) & 0x07; +#line 295 "rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 295 "rx-decode.opc" + int src AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 10sz 0dsp a dst b src mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" dst = 0x%x,", dst); + printf (" b = 0x%x,", b); + printf (" src = 0x%x\n", src); + } + SYNTAX("mov%s %1, %0"); +#line 295 "rx-decode.opc" + ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____; + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_39: + { + /** 10sz 1dsp a src b dst mov%s %1, %0 */ +#line 292 "rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 292 "rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 292 "rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 292 "rx-decode.opc" + int src AU = (op[1] >> 4) & 0x07; +#line 292 "rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 292 "rx-decode.opc" + int dst AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 10sz 1dsp a src b dst mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" src = 0x%x,", src); + printf (" b = 0x%x,", b); + printf (" dst = 0x%x\n", dst); + } + SYNTAX("mov%s %1, %0"); +#line 292 "rx-decode.opc" + ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____; + + } + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9c: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9d: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9e: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0x9f: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_38; + break; + } + break; + case 0xa8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xa9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xaa: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xab: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xac: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xad: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xae: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xaf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_39; + break; + } + break; + case 0xb0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_40: + { + /** 1011 w dsp a src b dst movu%s %1, %0 */ +#line 315 "rx-decode.opc" + int w AU = (op[0] >> 3) & 0x01; +#line 315 "rx-decode.opc" + int dsp AU = op[0] & 0x07; +#line 315 "rx-decode.opc" + int a AU = (op[1] >> 7) & 0x01; +#line 315 "rx-decode.opc" + int src AU = (op[1] >> 4) & 0x07; +#line 315 "rx-decode.opc" + int b AU = (op[1] >> 3) & 0x01; +#line 315 "rx-decode.opc" + int dst AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1011 w dsp a src b dst movu%s %1, %0 */", + op[0], op[1]); + printf (" w = 0x%x,", w); + printf (" dsp = 0x%x,", dsp); + printf (" a = 0x%x,", a); + printf (" src = 0x%x,", src); + printf (" b = 0x%x,", b); + printf (" dst = 0x%x\n", dst); + } + SYNTAX("movu%s %1, %0"); +#line 315 "rx-decode.opc" + ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; + + } + break; + } + break; + case 0xb1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xb9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xba: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbe: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xbf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_40; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_41: + { + /** 11sz sd ss rsrc rdst mov%s %1, %0 */ +#line 274 "rx-decode.opc" + int sz AU = (op[0] >> 4) & 0x03; +#line 274 "rx-decode.opc" + int sd AU = (op[0] >> 2) & 0x03; +#line 274 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 274 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 274 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 11sz sd ss rsrc rdst mov%s %1, %0 */", + op[0], op[1]); + printf (" sz = 0x%x,", sz); + printf (" sd = 0x%x,", sd); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %1, %0"); +#line 274 "rx-decode.opc" + if (ss == 3 && sz == 2 && rsrc == 0 && rdst == 0) + { + ID(nop2); + } + else + { + ID(mov); sBWL(sz); F_____; + if ((ss == 3) && (sd != 3)) + { + SD(ss, rdst, sz); DD(sd, rsrc, sz); + } + else + { + SD(ss, rsrc, sz); DD(sd, rdst, sz); + } + } + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_41; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + op_semantics_42: + { + /** 1111 00sd rdst 0bit bset #%1, %0%S0 */ +#line 859 "rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 859 "rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 859 "rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 00sd rdst 0bit bset #%1, %0%S0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bset #%1, %0%S0"); +#line 859 "rx-decode.opc" + ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; + + } + break; + case 0x08: + op_semantics_43: + { + /** 1111 00sd rdst 1bit bclr #%1, %0%S0 */ +#line 869 "rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 869 "rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 869 "rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("bclr #%1, %0%S0"); +#line 869 "rx-decode.opc" + ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; + + } + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[1] & 0x08) + { + case 0x00: + goto op_semantics_42; + break; + case 0x08: + goto op_semantics_43; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + op_semantics_44: + { + /** 1111 01sd rdst 0bit btst #%2, %1%S1 */ +#line 879 "rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 879 "rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 879 "rx-decode.opc" + int bit AU = op[1] & 0x07; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 01sd rdst 0bit btst #%2, %1%S1 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" bit = 0x%x\n", bit); + } + SYNTAX("btst #%2, %1%S1"); +#line 879 "rx-decode.opc" + ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC; + + } + break; + case 0x08: + op_semantics_45: + { + /** 1111 01ss rsrc 10sz push%s %1 */ +#line 340 "rx-decode.opc" + int ss AU = op[0] & 0x03; +#line 340 "rx-decode.opc" + int rsrc AU = (op[1] >> 4) & 0x0f; +#line 340 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 01ss rsrc 10sz push%s %1 */", + op[0], op[1]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("push%s %1"); +#line 340 "rx-decode.opc" + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____; + + /*----------------------------------------------------------------------*/ + /* XCHG */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[1] & 0x0c) + { + case 0x00: + case 0x04: + goto op_semantics_44; + break; + case 0x08: + goto op_semantics_45; + break; + default: UNSUPPORTED(); break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + op_semantics_46: + { + /** 1111 10sd rdst im sz mov%s #%1, %0 */ +#line 265 "rx-decode.opc" + int sd AU = op[0] & 0x03; +#line 265 "rx-decode.opc" + int rdst AU = (op[1] >> 4) & 0x0f; +#line 265 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 265 "rx-decode.opc" + int sz AU = op[1] & 0x03; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x\n", + "/** 1111 10sd rdst im sz mov%s #%1, %0 */", + op[0], op[1]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" im = 0x%x,", im); + printf (" sz = 0x%x\n", sz); + } + SYNTAX("mov%s #%1, %0"); +#line 265 "rx-decode.opc" + ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F_____; + + } + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[1] & 0x00) + { + case 0x00: + goto op_semantics_46; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */ +#line 514 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 514 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("sbb %1, %0"); +#line 514 "rx-decode.opc" + ID(sbb); SR (rsrc); DR(rdst); F_OSZC; + + /* FIXME: only supports .L */ + } + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */ +#line 445 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 445 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("neg %2, %0"); +#line 445 "rx-decode.opc" + ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* ADC */ + + } + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */ +#line 454 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 454 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc %1, %0"); +#line 454 "rx-decode.opc" + ID(adc); SR(rsrc); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */ +#line 527 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 527 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("abs %1, %0"); +#line 527 "rx-decode.opc" + ID(abs); DR(rdst); SR(rsrc); F_OSZ_; + + /*----------------------------------------------------------------------*/ + /* MAX */ + + } + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_47: + { + /** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ +#line 536 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 536 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 536 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max %1%S1, %0"); +#line 536 "rx-decode.opc" + if (ss == 3 && rsrc == 0 && rdst == 0) + { + ID(nop3); + } + else + { + ID(max); SP(ss, rsrc); DR(rdst); + } + + } + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_47; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_48: + { + /** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */ +#line 555 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 555 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 555 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min %1%S1, %0"); +#line 555 "rx-decode.opc" + ID(min); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_48; + break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_49: + { + /** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */ +#line 585 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 585 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 585 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul %1%S1, %0"); +#line 585 "rx-decode.opc" + ID(emul); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x19: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_49; + break; + } + break; + case 0x1c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_50: + { + /** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */ +#line 597 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 597 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 597 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu %1%S1, %0"); +#line 597 "rx-decode.opc" + ID(emulu); SP(ss, rsrc); DR(rdst); + + } + break; + } + break; + case 0x1d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x1e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_50; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_51: + { + /** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */ +#line 609 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 609 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 609 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div %1%S1, %0"); +#line 609 "rx-decode.opc" + ID(div); SP(ss, rsrc); DR(rdst); F_O___; + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_51; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_52: + { + /** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */ +#line 621 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 621 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 621 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu %1%S1, %0"); +#line 621 "rx-decode.opc" + ID(divu); SP(ss, rsrc); DR(rdst); F_O___; + + } + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_52; + break; + } + break; + case 0x30: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_53: + { + /** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */ +#line 433 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 433 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 433 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst %1%S1, %2"); +#line 433 "rx-decode.opc" + ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_; + + } + break; + } + break; + case 0x31: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x32: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x33: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_53; + break; + } + break; + case 0x34: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_54: + { + /** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */ +#line 412 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 412 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 412 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor %1%S1, %0"); +#line 412 "rx-decode.opc" + ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_; + + } + break; + } + break; + case 0x35: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x36: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x37: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_54; + break; + } + break; + case 0x3b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1100 0011 1011 rsrc rdst not %1, %0 */ +#line 424 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 424 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("not %1, %0"); +#line 424 "rx-decode.opc" + ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* TST */ + + } + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_55: + { + /** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */ +#line 346 "rx-decode.opc" + int ss AU = op[1] & 0x03; +#line 346 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 346 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" ss = 0x%x,", ss); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xchg %1%S1, %0"); +#line 346 "rx-decode.opc" + ID(xchg); DR(rdst); SP(ss, rsrc); + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_55; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_56: + { + /** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */ +#line 850 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 850 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 850 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("itof %1%S1, %0"); +#line 850 "rx-decode.opc" + ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_; + + } + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_56; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_57: + { + /** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ +#line 862 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 862 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 862 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bset %1, %0%S0"); +#line 862 "rx-decode.opc" + ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_57; + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_58: + { + /** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ +#line 872 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 872 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 872 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bclr %1, %0%S0"); +#line 872 "rx-decode.opc" + ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_58; + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_59: + { + /** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ +#line 882 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 882 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 882 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("btst %2, %1%S1"); +#line 882 "rx-decode.opc" + ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC; + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_59; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_60: + { + /** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ +#line 892 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 892 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 892 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("bnot %1, %0%S0"); +#line 892 "rx-decode.opc" + ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_60; + break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_61: + { + /** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */ +#line 829 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 829 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 829 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fsub %1%S1, %0"); +#line 829 "rx-decode.opc" + ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_61; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_62: + { + /** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */ +#line 823 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 823 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 823 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fcmp %1%S1, %0"); +#line 823 "rx-decode.opc" + ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_; + + } + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_62; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_63: + { + /** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */ +#line 817 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 817 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 817 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fadd %1%S1, %0"); +#line 817 "rx-decode.opc" + ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_63; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_64: + { + /** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */ +#line 838 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 838 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 838 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fmul %1%S1, %0"); +#line 838 "rx-decode.opc" + ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_64; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_65: + { + /** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */ +#line 844 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 844 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 844 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fdiv %1%S1, %0"); +#line 844 "rx-decode.opc" + ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_65; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_66: + { + /** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */ +#line 832 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 832 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 832 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("ftoi %1%S1, %0"); +#line 832 "rx-decode.opc" + ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_66; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_67: + { + /** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */ +#line 847 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 847 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 847 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */", + op[0], op[1], op[2]); + printf (" sd = 0x%x,", sd); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("round %1%S1, %0"); +#line 847 "rx-decode.opc" + ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + + } + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_67; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_68: + { + /** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ +#line 956 "rx-decode.opc" + int sz AU = (op[1] >> 2) & 0x03; +#line 956 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 956 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 956 "rx-decode.opc" + int cond AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("sc%1%s %0"); +#line 956 "rx-decode.opc" + ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); + + } + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_68; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + op_semantics_69: + { + /** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */ +#line 899 "rx-decode.opc" + int bit AU = (op[1] >> 2) & 0x07; +#line 899 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 899 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 899 "rx-decode.opc" + int cond AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bit = 0x%x,", bit); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x,", rdst); + printf (" cond = 0x%x\n", cond); + } + SYNTAX("bm%2 #%1, %0%S0"); +#line 899 "rx-decode.opc" + ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE); + + } + break; + case 0x0f: + op_semantics_70: + { + /** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */ +#line 889 "rx-decode.opc" + int bit AU = (op[1] >> 2) & 0x07; +#line 889 "rx-decode.opc" + int sd AU = op[1] & 0x03; +#line 889 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bit = 0x%x,", bit); + printf (" sd = 0x%x,", sd); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bnot #%1, %0%S0"); +#line 889 "rx-decode.opc" + ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); + + } + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + case 0xff: + GETBYTE (); + switch (op[2] & 0x0f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + goto op_semantics_69; + break; + case 0x0f: + goto op_semantics_70; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ +#line 772 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 772 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mulhi %1, %2"); +#line 772 "rx-decode.opc" + ID(mulhi); SR(srca); S2R(srcb); F_____; + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ +#line 775 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 775 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mullo %1, %2"); +#line 775 "rx-decode.opc" + ID(mullo); SR(srca); S2R(srcb); F_____; + + } + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0100 srca srcb machi %1, %2 */ +#line 778 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 778 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0100 srca srcb machi %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("machi %1, %2"); +#line 778 "rx-decode.opc" + ID(machi); SR(srca); S2R(srcb); F_____; + + } + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ +#line 781 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 781 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */", + op[0], op[1], op[2]); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("maclo %1, %2"); +#line 781 "rx-decode.opc" + ID(maclo); SR(srca); S2R(srcb); F_____; + + } + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ +#line 784 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mvtachi %1"); +#line 784 "rx-decode.opc" + ID(mvtachi); SR(rsrc); F_____; + + } + break; + case 0x10: + { + /** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ +#line 787 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mvtaclo %1"); +#line 787 "rx-decode.opc" + ID(mvtaclo); SR(rsrc); F_____; + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0xef) + { + case 0x00: + { + /** 1111 1101 0001 1000 000i 0000 racw #%1 */ +#line 799 "rx-decode.opc" + int i AU = (op[2] >> 4) & 0x01; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1000 000i 0000 racw #%1 */", + op[0], op[1], op[2]); + printf (" i = 0x%x\n", i); + } + SYNTAX("racw #%1"); +#line 799 "rx-decode.opc" + ID(racw); SC(i+1); F_____; + + /*----------------------------------------------------------------------*/ + /* SAT */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ +#line 790 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfachi %0"); +#line 790 "rx-decode.opc" + ID(mvfachi); DR(rdst); F_____; + + } + break; + case 0x10: + { + /** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ +#line 796 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfaclo %0"); +#line 796 "rx-decode.opc" + ID(mvfaclo); DR(rdst); F_____; + + } + break; + case 0x20: + { + /** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ +#line 793 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfacmi %0"); +#line 793 "rx-decode.opc" + ID(mvfacmi); DR(rdst); F_____; + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_71: + { + /** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ +#line 307 "rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 307 "rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 307 "rx-decode.opc" + int rdst AU = (op[2] >> 4) & 0x0f; +#line 307 "rx-decode.opc" + int rsrc AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rdst = 0x%x,", rdst); + printf (" rsrc = 0x%x\n", rsrc); + } + SYNTAX("mov%s %1, %0"); +#line 307 "rx-decode.opc" + ID(mov); sBWL (sz); SR(rsrc); F_____; + OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0); + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_71; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_72: + { + /** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */ +#line 311 "rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 311 "rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 311 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 311 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %1, %0"); +#line 311 "rx-decode.opc" + ID(mov); sBWL (sz); DR(rdst); F_____; + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + + } + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_72; + break; + } + break; + case 0x38: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_73: + { + /** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ +#line 321 "rx-decode.opc" + int p AU = (op[1] >> 2) & 0x01; +#line 321 "rx-decode.opc" + int sz AU = op[1] & 0x03; +#line 321 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 321 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */", + op[0], op[1], op[2]); + printf (" p = 0x%x,", p); + printf (" sz = 0x%x,", sz); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s %1, %0"); +#line 321 "rx-decode.opc" + ID(mov); uBWL (sz); DR(rdst); F_____; + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + + /*----------------------------------------------------------------------*/ + /* PUSH/POP */ + + } + break; + } + break; + case 0x39: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_73; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */ +#line 653 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 653 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr %2, %0"); +#line 653 "rx-decode.opc" + ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */ +#line 643 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 643 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar %2, %0"); +#line 643 "rx-decode.opc" + ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC; + + } + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */ +#line 633 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 633 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll %2, %0"); +#line 633 "rx-decode.opc" + ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC; + + } + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */ +#line 677 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 677 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotr %1, %0"); +#line 677 "rx-decode.opc" + ID(rotr); SR(rsrc); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */ +#line 680 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 680 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("revw %1, %0"); +#line 680 "rx-decode.opc" + ID(revw); SR(rsrc); DR(rdst); + + } + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */ +#line 671 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 671 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotl %1, %0"); +#line 671 "rx-decode.opc" + ID(rotl); SR(rsrc); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + { + /** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */ +#line 683 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 683 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */", + op[0], op[1], op[2]); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("revl %1, %0"); +#line 683 "rx-decode.opc" + ID(revl); SR(rsrc); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* BRANCH */ + + } + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_74: + { + /** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */ +#line 926 "rx-decode.opc" + int c AU = op[1] & 0x01; +#line 926 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 926 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */", + op[0], op[1], op[2]); + printf (" c = 0x%x,", c); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvtc %1, %0"); +#line 926 "rx-decode.opc" + ID(mov); SR(rsrc); DR(c*16+rdst + 16); + + } + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_74; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_75: + { + /** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */ +#line 929 "rx-decode.opc" + int s AU = op[1] & 0x01; +#line 929 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 929 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */", + op[0], op[1], op[2]); + printf (" s = 0x%x,", s); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mvfc %1, %0"); +#line 929 "rx-decode.opc" + ID(mov); SR((s*16+rsrc) + 16); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* INTERRUPTS */ + + } + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_75; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_76: + { + /** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */ +#line 674 "rx-decode.opc" + int i AU = op[1] & 0x01; +#line 674 "rx-decode.opc" + int mmmm AU = (op[2] >> 4) & 0x0f; +#line 674 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */", + op[0], op[1], op[2]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotr #%1, %0"); +#line 674 "rx-decode.opc" + ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_76; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_77: + { + /** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */ +#line 668 "rx-decode.opc" + int i AU = op[1] & 0x01; +#line 668 "rx-decode.opc" + int mmmm AU = (op[2] >> 4) & 0x0f; +#line 668 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */", + op[0], op[1], op[2]); + printf (" i = 0x%x,", i); + printf (" mmmm = 0x%x,", mmmm); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("rotl #%1, %0"); +#line 668 "rx-decode.opc" + ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC; + + } + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_77; + break; + } + break; + case 0x70: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + op_semantics_78: + { + /** 1111 1101 0111 im00 0010rdst adc #%1, %0 */ +#line 451 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 451 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("adc #%1, %0"); +#line 451 "rx-decode.opc" + ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC; + + } + break; + case 0x40: + op_semantics_79: + { + /** 1111 1101 0111 im00 0100rdst max #%1, %0 */ +#line 533 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 533 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0100rdst max #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("max #%1, %0"); +#line 533 "rx-decode.opc" + ID(max); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x50: + op_semantics_80: + { + /** 1111 1101 0111 im00 0101rdst min #%1, %0 */ +#line 552 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 552 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0101rdst min #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("min #%1, %0"); +#line 552 "rx-decode.opc" + ID(min); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x60: + op_semantics_81: + { + /** 1111 1101 0111 im00 0110rdst emul #%1, %0 */ +#line 582 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 582 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emul #%1, %0"); +#line 582 "rx-decode.opc" + ID(emul); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x70: + op_semantics_82: + { + /** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */ +#line 594 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 594 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("emulu #%1, %0"); +#line 594 "rx-decode.opc" + ID(emulu); DR(rdst); SC(IMMex(im)); + + } + break; + case 0x80: + op_semantics_83: + { + /** 1111 1101 0111 im00 1000rdst div #%1, %0 */ +#line 606 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 606 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1000rdst div #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("div #%1, %0"); +#line 606 "rx-decode.opc" + ID(div); DR(rdst); SC(IMMex(im)); F_O___; + + } + break; + case 0x90: + op_semantics_84: + { + /** 1111 1101 0111 im00 1001rdst divu #%1, %0 */ +#line 618 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 618 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("divu #%1, %0"); +#line 618 "rx-decode.opc" + ID(divu); DR(rdst); SC(IMMex(im)); F_O___; + + } + break; + case 0xc0: + op_semantics_85: + { + /** 1111 1101 0111 im00 1100rdst tst #%1, %2 */ +#line 430 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 430 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("tst #%1, %2"); +#line 430 "rx-decode.opc" + ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_; + + } + break; + case 0xd0: + op_semantics_86: + { + /** 1111 1101 0111 im00 1101rdst xor #%1, %0 */ +#line 409 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 409 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("xor #%1, %0"); +#line 409 "rx-decode.opc" + ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_; + + } + break; + case 0xe0: + op_semantics_87: + { + /** 1111 1101 0111 im00 1110rdst stz #%1, %0 */ +#line 355 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 355 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("stz #%1, %0"); +#line 355 "rx-decode.opc" + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z); + + } + break; + case 0xf0: + op_semantics_88: + { + /** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */ +#line 358 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 358 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("stnz #%1, %0"); +#line 358 "rx-decode.opc" + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz); + + /*----------------------------------------------------------------------*/ + /* RTSD */ + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x72: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + { + /** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */ +#line 826 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fsub #%1, %0"); +#line 826 "rx-decode.opc" + ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_; + + } + break; + case 0x10: + { + /** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */ +#line 820 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fcmp #%1, %0"); +#line 820 "rx-decode.opc" + ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_; + + } + break; + case 0x20: + { + /** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */ +#line 814 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fadd #%1, %0"); +#line 814 "rx-decode.opc" + ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_; + + } + break; + case 0x30: + { + /** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */ +#line 835 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fmul #%1, %0"); +#line 835 "rx-decode.opc" + ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_; + + } + break; + case 0x40: + { + /** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */ +#line 841 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("fdiv #%1, %0"); +#line 841 "rx-decode.opc" + ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_; + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x73: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + op_semantics_89: + { + /** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */ +#line 923 "rx-decode.opc" + int im AU = (op[1] >> 2) & 0x03; +#line 923 "rx-decode.opc" + int crdst AU = op[2] & 0x1f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */", + op[0], op[1], op[2]); + printf (" im = 0x%x,", im); + printf (" crdst = 0x%x\n", crdst); + } + SYNTAX("mvtc #%1, %0"); +#line 923 "rx-decode.opc" + ID(mov); SC(IMMex(im)); DR(crdst + 16); + + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0x74: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x77: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x78: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7b: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7c: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x20: + goto op_semantics_78; + break; + case 0x40: + goto op_semantics_79; + break; + case 0x50: + goto op_semantics_80; + break; + case 0x60: + goto op_semantics_81; + break; + case 0x70: + goto op_semantics_82; + break; + case 0x80: + goto op_semantics_83; + break; + case 0x90: + goto op_semantics_84; + break; + case 0xc0: + goto op_semantics_85; + break; + case 0xd0: + goto op_semantics_86; + break; + case 0xe0: + goto op_semantics_87; + break; + case 0xf0: + goto op_semantics_88; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x7f: + GETBYTE (); + switch (op[2] & 0xe0) + { + case 0x00: + goto op_semantics_89; + break; + default: UNSUPPORTED(); break; + } + break; + case 0x80: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_90: + { + /** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */ +#line 656 "rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 656 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 656 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shlr #%2, %1, %0"); +#line 656 "rx-decode.opc" + ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC; + + /*----------------------------------------------------------------------*/ + /* ROTATE */ + + } + break; + } + break; + case 0x81: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x82: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x83: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x84: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x85: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x86: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x87: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x88: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x89: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x8f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x90: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x91: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x92: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x93: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x94: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x95: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x96: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x97: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x98: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x99: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0x9f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_90; + break; + } + break; + case 0xa0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_91: + { + /** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */ +#line 646 "rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 646 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 646 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shar #%2, %1, %0"); +#line 646 "rx-decode.opc" + ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC; + + + } + break; + } + break; + case 0xa1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xa9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xaa: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xab: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xac: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xad: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xae: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xaf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xb9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xba: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbe: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xbf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_91; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_92: + { + /** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */ +#line 636 "rx-decode.opc" + int immmm AU = op[1] & 0x1f; +#line 636 "rx-decode.opc" + int rsrc AU = (op[2] >> 4) & 0x0f; +#line 636 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */", + op[0], op[1], op[2]); + printf (" immmm = 0x%x,", immmm); + printf (" rsrc = 0x%x,", rsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("shll #%2, %1, %0"); +#line 636 "rx-decode.opc" + ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC; + + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_92; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + op_semantics_93: + { + /** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */ +#line 902 "rx-decode.opc" + int bittt AU = op[1] & 0x1f; +#line 902 "rx-decode.opc" + int cond AU = (op[2] >> 4) & 0x0f; +#line 902 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */", + op[0], op[1], op[2]); + printf (" bittt = 0x%x,", bittt); + printf (" cond = 0x%x,", cond); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bm%2 #%1, %0%S0"); +#line 902 "rx-decode.opc" + ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst); + + /*----------------------------------------------------------------------*/ + /* CONTROL REGISTERS */ + + } + break; + case 0xf0: + op_semantics_94: + { + /** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ +#line 895 "rx-decode.opc" + int bittt AU = op[1] & 0x1f; +#line 895 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */", + op[0], op[1], op[2]); + printf (" bittt = 0x%x,", bittt); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("bnot #%1, %0"); +#line 895 "rx-decode.opc" + ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); + + + } + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf0: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf1: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf2: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf3: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf4: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf5: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf6: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf7: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf8: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xf9: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfa: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfb: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfc: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfd: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + case 0xff: + GETBYTE (); + switch (op[2] & 0xf0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + case 0x80: + case 0x90: + case 0xa0: + case 0xb0: + case 0xc0: + case 0xd0: + case 0xe0: + goto op_semantics_93; + break; + case 0xf0: + goto op_semantics_94; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xfe: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_95: + { + /** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */ +#line 301 "rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 301 "rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 301 "rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 301 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s %0, [%1, %2]"); +#line 301 "rx-decode.opc" + ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x10: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x11: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x12: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x13: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x14: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x15: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x16: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x17: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x18: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x19: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x1f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x2f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_95; + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_96: + { + /** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */ +#line 298 "rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 298 "rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 298 "rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 298 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("mov%s [%1, %2], %0"); +#line 298 "rx-decode.opc" + ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x60: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x61: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x62: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x63: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x64: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x65: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x66: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x67: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x68: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x69: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0x6f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_96; + break; + } + break; + case 0xc0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_97: + { + /** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ +#line 304 "rx-decode.opc" + int sz AU = (op[1] >> 4) & 0x03; +#line 304 "rx-decode.opc" + int isrc AU = op[1] & 0x0f; +#line 304 "rx-decode.opc" + int bsrc AU = (op[2] >> 4) & 0x0f; +#line 304 "rx-decode.opc" + int rdst AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */", + op[0], op[1], op[2]); + printf (" sz = 0x%x,", sz); + printf (" isrc = 0x%x,", isrc); + printf (" bsrc = 0x%x,", bsrc); + printf (" rdst = 0x%x\n", rdst); + } + SYNTAX("movu%s [%1, %2], %0"); +#line 304 "rx-decode.opc" + ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + + } + break; + } + break; + case 0xc1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xc9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xca: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xce: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xcf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xd9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xda: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdc: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdd: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xde: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xdf: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe0: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe1: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe2: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe3: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe4: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe5: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe6: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe7: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe8: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xe9: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xea: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xeb: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xec: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xed: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xee: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + case 0xef: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_97; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + case 0xff: + GETBYTE (); + switch (op[1] & 0xff) + { + case 0x00: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_98: + { + /** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */ +#line 508 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 508 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 508 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("sub %2, %1, %0"); +#line 508 "rx-decode.opc" + ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* SBB */ + + } + break; + } + break; + case 0x01: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x02: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x03: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x04: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x05: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x06: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x07: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x08: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x09: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x0f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_98; + break; + } + break; + case 0x20: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_99: + { + /** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */ +#line 475 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 475 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 475 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("add %2, %1, %0"); +#line 475 "rx-decode.opc" + ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC; + + /*----------------------------------------------------------------------*/ + /* CMP */ + + } + break; + } + break; + case 0x21: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x22: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x23: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x24: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x25: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x26: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x27: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x28: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x29: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x2f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_99; + break; + } + break; + case 0x30: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_100: + { + /** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */ +#line 576 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 576 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 576 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("mul %2, %1, %0"); +#line 576 "rx-decode.opc" + ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____; + + /*----------------------------------------------------------------------*/ + /* EMUL */ + + } + break; + } + break; + case 0x31: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x32: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x33: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x34: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x35: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x36: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x37: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x38: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x39: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x3f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_100; + break; + } + break; + case 0x40: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_101: + { + /** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */ +#line 385 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 385 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 385 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("and %2, %1, %0"); +#line 385 "rx-decode.opc" + ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* OR */ + + } + break; + } + break; + case 0x41: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x42: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x43: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x44: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x45: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x46: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x47: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x48: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x49: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x4f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_101; + break; + } + break; + case 0x50: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + op_semantics_102: + { + /** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */ +#line 403 "rx-decode.opc" + int rdst AU = op[1] & 0x0f; +#line 403 "rx-decode.opc" + int srca AU = (op[2] >> 4) & 0x0f; +#line 403 "rx-decode.opc" + int srcb AU = op[2] & 0x0f; + if (trace) + { + printf ("\033[33m%s\033[0m %02x %02x %02x\n", + "/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */", + op[0], op[1], op[2]); + printf (" rdst = 0x%x,", rdst); + printf (" srca = 0x%x,", srca); + printf (" srcb = 0x%x\n", srcb); + } + SYNTAX("or %2, %1, %0"); +#line 403 "rx-decode.opc" + ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + + /*----------------------------------------------------------------------*/ + /* XOR */ + + } + break; + } + break; + case 0x51: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x52: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x53: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x54: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x55: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x56: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x57: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x58: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x59: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5a: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5b: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5c: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5d: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5e: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + case 0x5f: + GETBYTE (); + switch (op[2] & 0x00) + { + case 0x00: + goto op_semantics_102; + break; + } + break; + default: UNSUPPORTED(); break; + } + break; + default: UNSUPPORTED(); break; + } +#line 959 "rx-decode.opc" + + return rx->n_bytes; +} diff --git a/external/gpl3/gdb/dist/opcodes/rx-decode.opc b/external/gpl3/gdb/dist/opcodes/rx-decode.opc new file mode 100644 index 000000000000..0c89cb99a899 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/rx-decode.opc @@ -0,0 +1,961 @@ +/* -*- c -*- */ +#include +#include +#include + +#include "config.h" +#include "ansidecl.h" +#include "opcode/rx.h" + +#define RX_OPCODE_BIG_ENDIAN 0 + +typedef struct +{ + RX_Opcode_Decoded * rx; + int (* getbyte)(void *); + void * ptr; + unsigned char * op; +} LocalData; + +static int trace = 0; + +#define BSIZE 0 +#define WSIZE 1 +#define LSIZE 2 + +/* These are for when the upper bits are "don't care" or "undefined". */ +static int bwl[] = +{ + RX_Byte, + RX_Word, + RX_Long +}; + +static int sbwl[] = +{ + RX_SByte, + RX_SWord, + RX_Long +}; + +static int ubwl[] = +{ + RX_UByte, + RX_UWord, + RX_Long +}; + +static int memex[] = +{ + RX_SByte, + RX_SWord, + RX_Long, + RX_UWord +}; + +#define ID(x) rx->id = RXO_##x +#define OP(n,t,r,a) (rx->op[n].type = t, \ + rx->op[n].reg = r, \ + rx->op[n].addend = a ) +#define OPs(n,t,r,a,s) (OP (n,t,r,a), \ + rx->op[n].size = s ) + +/* This is for the BWL and BW bitfields. */ +static int SCALE[] = { 1, 2, 4 }; +/* This is for the prefix size enum. */ +static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; + +static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, + 16, 17, 0, 0, 0, 0, 0, 0 }; + +static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; + +/* + *C a constant (immediate) c + *R A register + *I Register indirect, no offset + *Is Register indirect, with offset + *D standard displacement: type (r,[r],dsp8,dsp16 code), register, BWL code + *P standard displacement: type (r,[r]), reg, assumes UByte + *Pm memex displacement: type (r,[r]), reg, memex code + *cc condition code. */ + +#define DC(c) OP (0, RX_Operand_Immediate, 0, c) +#define DR(r) OP (0, RX_Operand_Register, r, 0) +#define DI(r,a) OP (0, RX_Operand_Indirect, r, a) +#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); +#define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) + +#define SC(i) OP (1, RX_Operand_Immediate, 0, i) +#define SR(r) OP (1, RX_Operand_Register, r, 0) +#define SRR(r) OP (1, RX_Operand_TwoReg, r, 0) +#define SI(r,a) OP (1, RX_Operand_Indirect, r, a) +#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); +#define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); +#define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; +#define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) + +#define S2C(i) OP (2, RX_Operand_Immediate, 0, i) +#define S2R(r) OP (2, RX_Operand_Register, r, 0) +#define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) +#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); +#define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); +#define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; +#define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) + +#define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] +#define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] +#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] +#define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; + +#define F(f) store_flags(rx, f) + +#define AU ATTRIBUTE_UNUSED +#define GETBYTE() (ld->op [ld->rx->n_bytes++] = ld->getbyte (ld->ptr)) + +#define SYNTAX(x) rx->syntax = x + +#define UNSUPPORTED() \ + rx->syntax = "*unknown*" + +#define IMM(sf) immediate (sf, 0, ld) +#define IMMex(sf) immediate (sf, 1, ld) + +static int +immediate (int sfield, int ex, LocalData * ld) +{ + unsigned long i = 0, j; + + switch (sfield) + { +#define B ((unsigned long) GETBYTE()) + case 0: +#if RX_OPCODE_BIG_ENDIAN + i = B; + if (ex && (i & 0x80)) + i -= 0x100; + i <<= 24; + i |= B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; + j = B; + if (ex && (j & 0x80)) + j -= 0x100; + i |= j << 24; +#endif + break; + case 3: +#if RX_OPCODE_BIG_ENDIAN + i = B << 16; + i |= B << 8; + i |= B; +#else + i = B; + i |= B << 8; + i |= B << 16; +#endif + if (ex && (i & 0x800000)) + i -= 0x1000000; + break; + case 2: +#if RX_OPCODE_BIG_ENDIAN + i |= B << 8; + i |= B; +#else + i |= B; + i |= B << 8; +#endif + if (ex && (i & 0x8000)) + i -= 0x10000; + break; + case 1: + i |= B; + if (ex && (i & 0x80)) + i -= 0x100; + break; + default: + abort(); + } + return i; +} + +static void +rx_disp (int n, int type, int reg, int size, LocalData * ld) +{ + int disp; + + ld->rx->op[n].reg = reg; + switch (type) + { + case 3: + ld->rx->op[n].type = RX_Operand_Register; + break; + case 0: + ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].addend = 0; + break; + case 1: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + case 2: + ld->rx->op[n].type = RX_Operand_Indirect; + disp = GETBYTE (); +#if RX_OPCODE_BIG_ENDIAN + disp = disp * 256 + GETBYTE (); +#else + disp = disp + GETBYTE () * 256; +#endif + ld->rx->op[n].addend = disp * PSCALE[size]; + break; + default: + abort (); + } +} + +#define xO 8 +#define xS 4 +#define xZ 2 +#define xC 1 + +#define F_____ +#define F___ZC rx->flags_0 = rx->flags_s = xZ|xC; +#define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ; +#define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC; +#define F_0SZC rx->flags_0 = xO|xS|xZ|xC; rx->flags_s = xS|xZ|xC; +#define F_O___ rx->flags_0 = rx->flags_s = xO; +#define F_OS__ rx->flags_0 = rx->flags_s = xO|xS; +#define F_OSZ_ rx->flags_0 = rx->flags_s = xO|xS|xZ; +#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC; + +int +rx_decode_opcode (unsigned long pc AU, + RX_Opcode_Decoded * rx, + int (* getbyte)(void *), + void * ptr) +{ + LocalData lds, * ld = &lds; + unsigned char op[20] = {0}; + + lds.rx = rx; + lds.getbyte = getbyte; + lds.ptr = ptr; + lds.op = op; + + memset (rx, 0, sizeof (*rx)); + BWL(LSIZE); + +/** VARY sz 00 01 10 */ + +/*----------------------------------------------------------------------*/ +/* MOV */ + +/** 0111 0101 0100 rdst mov%s #%1, %0 */ + ID(mov); DR(rdst); SC(IMM (1)); F_____; + +/** 1111 10sd rdst im sz mov%s #%1, %0 */ + ID(mov); sBWL (sz); DD(sd, rdst, sz); SC(IMMex(im)); F_____; + +/** 0110 0110 immm rdst mov%s #%1, %0 */ + ID(mov); DR(rdst); SC(immm); F_____; + +/** 0011 11sz d dst sppp mov%s #%1, %0 */ + ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; + +/** 11sz sd ss rsrc rdst mov%s %1, %0 */ + if (ss == 3 && sz == 2 && rsrc == 0 && rdst == 0) + { + ID(nop2); + } + else + { + ID(mov); sBWL(sz); F_____; + if ((ss == 3) && (sd != 3)) + { + SD(ss, rdst, sz); DD(sd, rsrc, sz); + } + else + { + SD(ss, rsrc, sz); DD(sd, rdst, sz); + } + } + +/** 10sz 1dsp a src b dst mov%s %1, %0 */ + ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____; + +/** 10sz 0dsp a dst b src mov%s %1, %0 */ + ID(mov); sBWL(sz); DIs(dst, dsp*4+a*2+b, sz); SR(src); F_____; + +/** 1111 1110 01sz isrc bsrc rdst mov%s [%1, %2], %0 */ + ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + +/** 1111 1110 00sz isrc bsrc rdst mov%s %0, [%1, %2] */ + ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + +/** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ + ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + +/** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ + ID(mov); sBWL (sz); SR(rsrc); F_____; + OP(0, p ? RX_Operand_Predec : RX_Operand_Postinc, rdst, 0); + +/** 1111 1101 0010 1p sz rsrc rdst mov%s %1, %0 */ + ID(mov); sBWL (sz); DR(rdst); F_____; + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + +/** 1011 w dsp a src b dst movu%s %1, %0 */ + ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; + +/** 0101 1 s ss rsrc rdst movu%s %1, %0 */ + ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____; + +/** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ + ID(mov); uBWL (sz); DR(rdst); F_____; + OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); + +/*----------------------------------------------------------------------*/ +/* PUSH/POP */ + +/** 0110 1111 dsta dstb popm %1-%2 */ + ID(popm); SR(dsta); S2R(dstb); F_____; + +/** 0110 1110 dsta dstb pushm %1-%2 */ + ID(pushm); SR(dsta); S2R(dstb); F_____; + +/** 0111 1110 1011 rdst pop %0 */ + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____; + +/** 0111 1110 10sz rsrc push%s %1 */ + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____; + +/** 1111 01ss rsrc 10sz push%s %1 */ + ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SD(ss, rsrc, sz); F_____; + +/*----------------------------------------------------------------------*/ +/* XCHG */ + +/** 1111 1100 0100 00ss rsrc rdst xchg %1%S1, %0 */ + ID(xchg); DR(rdst); SP(ss, rsrc); + +/** 0000 0110 mx10 00ss 0001 0000 rsrc rdst xchg %1%S1, %0 */ + ID(xchg); DR(rdst); SPm(ss, rsrc, mx); + +/*----------------------------------------------------------------------*/ +/* STZ/STNZ */ + +/** 1111 1101 0111 im00 1110rdst stz #%1, %0 */ + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_z); + +/** 1111 1101 0111 im00 1111rdst stnz #%1, %0 */ + ID(stcc); SC(IMMex(im)); DR(rdst); S2cc(RXC_nz); + +/*----------------------------------------------------------------------*/ +/* RTSD */ + +/** 0110 0111 rtsd #%1 */ + ID(rtsd); SC(IMM(1) * 4); + +/** 0011 1111 rega regb rtsd #%1, %2-%0 */ + ID(rtsd); SC(IMM(1) * 4); S2R(rega); DR(regb); + +/*----------------------------------------------------------------------*/ +/* AND */ + +/** 0110 0100 immm rdst and #%1, %0 */ + ID(and); SC(immm); DR(rdst); F__SZ_; + +/** 0111 01im 0010 rdst and #%1, %0 */ + ID(and); SC(IMMex(im)); DR(rdst); F__SZ_; + +/** 0101 00ss rsrc rdst and %1%S1, %0 */ + ID(and); SP(ss, rsrc); DR(rdst); F__SZ_; + +/** 0000 0110 mx01 00ss rsrc rdst and %1%S1, %0 */ + ID(and); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + +/** 1111 1111 0100 rdst srca srcb and %2, %1, %0 */ + ID(and); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* OR */ + +/** 0110 0101 immm rdst or #%1, %0 */ + ID(or); SC(immm); DR(rdst); F__SZ_; + +/** 0111 01im 0011 rdst or #%1, %0 */ + ID(or); SC(IMMex(im)); DR(rdst); F__SZ_; + +/** 0101 01ss rsrc rdst or %1%S1, %0 */ + ID(or); SP(ss, rsrc); DR(rdst); F__SZ_; + +/** 0000 0110 mx01 01ss rsrc rdst or %1%S1, %0 */ + ID(or); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + +/** 1111 1111 0101 rdst srca srcb or %2, %1, %0 */ + ID(or); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* XOR */ + +/** 1111 1101 0111 im00 1101rdst xor #%1, %0 */ + ID(xor); SC(IMMex(im)); DR(rdst); F__SZ_; + +/** 1111 1100 0011 01ss rsrc rdst xor %1%S1, %0 */ + ID(xor); SP(ss, rsrc); DR(rdst); F__SZ_; + +/** 0000 0110 mx10 00ss 0000 1101 rsrc rdst xor %1%S1, %0 */ + ID(xor); SPm(ss, rsrc, mx); DR(rdst); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* NOT */ + +/** 0111 1110 0000 rdst not %0 */ + ID(xor); DR(rdst); SR(rdst); S2C(~0); F__SZ_; + +/** 1111 1100 0011 1011 rsrc rdst not %1, %0 */ + ID(xor); DR(rdst); SR(rsrc); S2C(~0); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* TST */ + +/** 1111 1101 0111 im00 1100rdst tst #%1, %2 */ + ID(and); SC(IMMex(im)); S2R(rdst); F__SZ_; + +/** 1111 1100 0011 00ss rsrc rdst tst %1%S1, %2 */ + ID(and); SP(ss, rsrc); S2R(rdst); F__SZ_; + +/** 0000 0110 mx10 00ss 0000 1100 rsrc rdst tst %1%S1, %2 */ + ID(and); SPm(ss, rsrc, mx); S2R(rdst); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* NEG */ + +/** 0111 1110 0001 rdst neg %0 */ + ID(sub); DR(rdst); SC(0); S2R(rdst); F_OSZC; + +/** 1111 1100 0000 0111 rsrc rdst neg %2, %0 */ + ID(sub); DR(rdst); SC(0); S2R(rsrc); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* ADC */ + +/** 1111 1101 0111 im00 0010rdst adc #%1, %0 */ + ID(adc); SC(IMMex(im)); DR(rdst); F_OSZC; + +/** 1111 1100 0000 1011 rsrc rdst adc %1, %0 */ + ID(adc); SR(rsrc); DR(rdst); F_OSZC; + +/** 0000 0110 1010 00ss 0000 0010 rsrc rdst adc %1%S1, %0 */ + ID(adc); SPm(ss, rsrc, 2); DR(rdst); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* ADD */ + +/** 0110 0010 immm rdst add #%1, %0 */ + ID(add); SC(immm); DR(rdst); F_OSZC; + +/** 0100 10ss rsrc rdst add %1%S1, %0 */ + ID(add); SP(ss, rsrc); DR(rdst); F_OSZC; + +/** 0000 0110 mx00 10ss rsrc rdst add %1%S1, %0 */ + ID(add); SPm(ss, rsrc, mx); DR(rdst); F_OSZC; + +/** 0111 00im rsrc rdst add #%1, %2, %0 */ + ID(add); SC(IMMex(im)); S2R(rsrc); DR(rdst); F_OSZC; + +/** 1111 1111 0010 rdst srca srcb add %2, %1, %0 */ + ID(add); DR(rdst); SR(srcb); S2R(srca); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* CMP */ + +/** 0110 0001 immm rdst cmp #%2, %1 */ + ID(sub); S2C(immm); SR(rdst); F_OSZC; + +/** 0111 01im 0000 rsrc cmp #%2, %1%S1 */ + ID(sub); SR(rsrc); S2C(IMMex(im)); F_OSZC; + +/** 0111 0101 0101 rsrc cmp #%2, %1 */ + ID(sub); SR(rsrc); S2C(IMM(1)); F_OSZC; + +/** 0100 01ss rsrc rdst cmp %2%S2, %1 */ + ID(sub); S2P(ss, rsrc); SR(rdst); F_OSZC; + +/** 0000 0110 mx00 01ss rsrc rdst cmp %2%S2, %1 */ + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* SUB */ + +/** 0110 0000 immm rdst sub #%2, %0 */ + ID(sub); S2C(immm); SR(rdst); DR(rdst); F_OSZC; + +/** 0100 00ss rsrc rdst sub %2%S2, %1 */ + ID(sub); S2P(ss, rsrc); SR(rdst); DR(rdst); F_OSZC; + +/** 0000 0110 mx00 00ss rsrc rdst sub %2%S2, %1 */ + ID(sub); S2Pm(ss, rsrc, mx); SR(rdst); DR(rdst); F_OSZC; + +/** 1111 1111 0000 rdst srca srcb sub %2, %1, %0 */ + ID(sub); DR(rdst); SR(srcb); S2R(srca); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* SBB */ + +/** 1111 1100 0000 0011 rsrc rdst sbb %1, %0 */ + ID(sbb); SR (rsrc); DR(rdst); F_OSZC; + + /* FIXME: only supports .L */ +/** 0000 0110 mx10 00sp 0000 0000 rsrc rdst sbb %1%S1, %0 */ + ID(sbb); SPm(sp, rsrc, mx); DR(rdst); F_OSZC; + +/*----------------------------------------------------------------------*/ +/* ABS */ + +/** 0111 1110 0010 rdst abs %0 */ + ID(abs); DR(rdst); SR(rdst); F_OSZ_; + +/** 1111 1100 0000 1111 rsrc rdst abs %1, %0 */ + ID(abs); DR(rdst); SR(rsrc); F_OSZ_; + +/*----------------------------------------------------------------------*/ +/* MAX */ + +/** 1111 1101 0111 im00 0100rdst max #%1, %0 */ + ID(max); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ + if (ss == 3 && rsrc == 0 && rdst == 0) + { + ID(nop3); + } + else + { + ID(max); SP(ss, rsrc); DR(rdst); + } + +/** 0000 0110 mx10 00ss 0000 0100 rsrc rdst max %1%S1, %0 */ + ID(max); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* MIN */ + +/** 1111 1101 0111 im00 0101rdst min #%1, %0 */ + ID(min); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 01ss rsrc rdst min %1%S1, %0 */ + ID(min); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0101 rsrc rdst min %1%S1, %0 */ + ID(min); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* MUL */ + +/** 0110 0011 immm rdst mul #%1, %0 */ + ID(mul); DR(rdst); SC(immm); F_____; + +/** 0111 01im 0001rdst mul #%1, %0 */ + ID(mul); DR(rdst); SC(IMMex(im)); F_____; + +/** 0100 11ss rsrc rdst mul %1%S1, %0 */ + ID(mul); SP(ss, rsrc); DR(rdst); F_____; + +/** 0000 0110 mx00 11ss rsrc rdst mul %1%S1, %0 */ + ID(mul); SPm(ss, rsrc, mx); DR(rdst); F_____; + +/** 1111 1111 0011 rdst srca srcb mul %2, %1, %0 */ + ID(mul); DR(rdst); SR(srcb); S2R(srca); F_____; + +/*----------------------------------------------------------------------*/ +/* EMUL */ + +/** 1111 1101 0111 im00 0110rdst emul #%1, %0 */ + ID(emul); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 10ss rsrc rdst emul %1%S1, %0 */ + ID(emul); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0110 rsrc rdst emul %1%S1, %0 */ + ID(emul); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* EMULU */ + +/** 1111 1101 0111 im00 0111rdst emulu #%1, %0 */ + ID(emulu); DR(rdst); SC(IMMex(im)); + +/** 1111 1100 0001 11ss rsrc rdst emulu %1%S1, %0 */ + ID(emulu); SP(ss, rsrc); DR(rdst); + +/** 0000 0110 mx10 00ss 0000 0111 rsrc rdst emulu %1%S1, %0 */ + ID(emulu); SPm(ss, rsrc, mx); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* DIV */ + +/** 1111 1101 0111 im00 1000rdst div #%1, %0 */ + ID(div); DR(rdst); SC(IMMex(im)); F_O___; + +/** 1111 1100 0010 00ss rsrc rdst div %1%S1, %0 */ + ID(div); SP(ss, rsrc); DR(rdst); F_O___; + +/** 0000 0110 mx10 00ss 0000 1000 rsrc rdst div %1%S1, %0 */ + ID(div); SPm(ss, rsrc, mx); DR(rdst); F_O___; + +/*----------------------------------------------------------------------*/ +/* DIVU */ + +/** 1111 1101 0111 im00 1001rdst divu #%1, %0 */ + ID(divu); DR(rdst); SC(IMMex(im)); F_O___; + +/** 1111 1100 0010 01ss rsrc rdst divu %1%S1, %0 */ + ID(divu); SP(ss, rsrc); DR(rdst); F_O___; + +/** 0000 0110 mx10 00ss 0000 1001 rsrc rdst divu %1%S1, %0 */ + ID(divu); SPm(ss, rsrc, mx); DR(rdst); F_O___; + +/*----------------------------------------------------------------------*/ +/* SHIFT */ + +/** 0110 110i mmmm rdst shll #%2, %0 */ + ID(shll); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_OSZC; + +/** 1111 1101 0110 0010 rsrc rdst shll %2, %0 */ + ID(shll); S2R(rsrc); SR(rdst); DR(rdst); F_OSZC; + +/** 1111 1101 110immmm rsrc rdst shll #%2, %1, %0 */ + ID(shll); S2C(immmm); SR(rsrc); DR(rdst); F_OSZC; + + +/** 0110 101i mmmm rdst shar #%2, %0 */ + ID(shar); S2C(i*16+mmmm); SR(rdst); DR(rdst); F_0SZC; + +/** 1111 1101 0110 0001 rsrc rdst shar %2, %0 */ + ID(shar); S2R(rsrc); SR(rdst); DR(rdst); F_0SZC; + +/** 1111 1101 101immmm rsrc rdst shar #%2, %1, %0 */ + ID(shar); S2C(immmm); SR(rsrc); DR(rdst); F_0SZC; + + +/** 0110 100i mmmm rdst shlr #%2, %0 */ + ID(shlr); S2C(i*16+mmmm); SR(rdst); DR(rdst); F__SZC; + +/** 1111 1101 0110 0000 rsrc rdst shlr %2, %0 */ + ID(shlr); S2R(rsrc); SR(rdst); DR(rdst); F__SZC; + +/** 1111 1101 100immmm rsrc rdst shlr #%2, %1, %0 */ + ID(shlr); S2C(immmm); SR(rsrc); DR(rdst); F__SZC; + +/*----------------------------------------------------------------------*/ +/* ROTATE */ + +/** 0111 1110 0101 rdst rolc %0 */ + ID(rolc); DR(rdst); F__SZC; + +/** 0111 1110 0100 rdst rorc %0 */ + ID(rorc); DR(rdst); F__SZC; + +/** 1111 1101 0110 111i mmmm rdst rotl #%1, %0 */ + ID(rotl); SC(i*16+mmmm); DR(rdst); F__SZC; + +/** 1111 1101 0110 0110 rsrc rdst rotl %1, %0 */ + ID(rotl); SR(rsrc); DR(rdst); F__SZC; + +/** 1111 1101 0110 110i mmmm rdst rotr #%1, %0 */ + ID(rotr); SC(i*16+mmmm); DR(rdst); F__SZC; + +/** 1111 1101 0110 0100 rsrc rdst rotr %1, %0 */ + ID(rotr); SR(rsrc); DR(rdst); F__SZC; + +/** 1111 1101 0110 0101 rsrc rdst revw %1, %0 */ + ID(revw); SR(rsrc); DR(rdst); + +/** 1111 1101 0110 0111 rsrc rdst revl %1, %0 */ + ID(revl); SR(rsrc); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* BRANCH */ + +/** 0001 n dsp b%1.s %a0 */ + ID(branch); Scc(n); DC(pc + dsp3map[dsp]); + +/** 0010 cond b%1.b %a0 */ + ID(branch); Scc(cond); DC(pc + IMMex (1)); + +/** 0011 101c b%1.w %a0 */ + ID(branch); Scc(c); DC(pc + IMMex (2)); + + +/** 0000 1dsp bra.s %a0 */ + ID(branch); DC(pc + dsp3map[dsp]); + +/** 0010 1110 bra.b %a0 */ + ID(branch); DC(pc + IMMex(1)); + +/** 0011 1000 bra.w %a0 */ + ID(branch); DC(pc + IMMex(2)); + +/** 0000 0100 bra.a %a0 */ + ID(branch); DC(pc + IMMex(3)); + +/** 0111 1111 0100 rsrc bra.l %0 */ + ID(branchrel); DR(rsrc); + + +/** 0111 1111 0000 rsrc jmp %0 */ + ID(branch); DR(rsrc); + +/** 0111 1111 0001 rsrc jsr %0 */ + ID(jsr); DR(rsrc); + +/** 0011 1001 bsr.w %a0 */ + ID(jsr); DC(pc + IMMex(2)); + +/** 0000 0101 bsr.a %a0 */ + ID(jsr); DC(pc + IMMex(3)); + +/** 0111 1111 0101 rsrc bsr.l %0 */ + ID(jsrrel); DR(rsrc); + +/** 0000 0010 rts */ + ID(rts); + +/*----------------------------------------------------------------------*/ +/* NOP */ + +/** 0000 0011 nop */ + ID(nop); + +/*----------------------------------------------------------------------*/ +/* STRING FUNCTIONS */ + +/** 0111 1111 1000 0011 scmpu */ + ID(scmpu); F___ZC; + +/** 0111 1111 1000 0111 smovu */ + ID(smovu); + +/** 0111 1111 1000 1011 smovb */ + ID(smovb); + +/** 0111 1111 1000 00sz suntil%s */ + ID(suntil); BWL(sz); F___ZC; + +/** 0111 1111 1000 01sz swhile%s */ + ID(swhile); BWL(sz); F___ZC; + +/** 0111 1111 1000 1111 smovf */ + ID(smovf); + +/** 0111 1111 1000 10sz sstr%s */ + ID(sstr); BWL(sz); + +/*----------------------------------------------------------------------*/ +/* RMPA */ + +/** 0111 1111 1000 11sz rmpa%s */ + ID(rmpa); BWL(sz); F_OS__; + +/*----------------------------------------------------------------------*/ +/* HI/LO stuff */ + +/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ + ID(mulhi); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ + ID(mullo); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 0100 srca srcb machi %1, %2 */ + ID(machi); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ + ID(maclo); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ + ID(mvtachi); SR(rsrc); F_____; + +/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ + ID(mvtaclo); SR(rsrc); F_____; + +/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ + ID(mvfachi); DR(rdst); F_____; + +/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ + ID(mvfacmi); DR(rdst); F_____; + +/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ + ID(mvfaclo); DR(rdst); F_____; + +/** 1111 1101 0001 1000 000i 0000 racw #%1 */ + ID(racw); SC(i+1); F_____; + +/*----------------------------------------------------------------------*/ +/* SAT */ + +/** 0111 1110 0011 rdst sat %0 */ + ID(sat); DR (rdst); + +/** 0111 1111 1001 0011 satr */ + ID(satr); + +/*----------------------------------------------------------------------*/ +/* FLOAT */ + +/** 1111 1101 0111 0010 0010 rdst fadd #%1, %0 */ + ID(fadd); DR(rdst); SC(IMM(0)); F__SZ_; + +/** 1111 1100 1000 10sd rsrc rdst fadd %1%S1, %0 */ + ID(fadd); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1101 0111 0010 0001 rdst fcmp #%1, %0 */ + ID(fcmp); DR(rdst); SC(IMM(0)); F_OSZ_; + +/** 1111 1100 1000 01sd rsrc rdst fcmp %1%S1, %0 */ + ID(fcmp); DR(rdst); SD(sd, rsrc, LSIZE); F_OSZ_; + +/** 1111 1101 0111 0010 0000 rdst fsub #%1, %0 */ + ID(fsub); DR(rdst); SC(IMM(0)); F__SZ_; + +/** 1111 1100 1000 00sd rsrc rdst fsub %1%S1, %0 */ + ID(fsub); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1100 1001 01sd rsrc rdst ftoi %1%S1, %0 */ + ID(ftoi); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1101 0111 0010 0011 rdst fmul #%1, %0 */ + ID(fmul); DR(rdst); SC(IMM(0)); F__SZ_; + +/** 1111 1100 1000 11sd rsrc rdst fmul %1%S1, %0 */ + ID(fmul); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1101 0111 0010 0100 rdst fdiv #%1, %0 */ + ID(fdiv); DR(rdst); SC(IMM(0)); F__SZ_; + +/** 1111 1100 1001 00sd rsrc rdst fdiv %1%S1, %0 */ + ID(fdiv); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1100 1001 10sd rsrc rdst round %1%S1, %0 */ + ID(round); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1100 0100 01sd rsrc rdst itof %1%S1, %0 */ + ID(itof); DR (rdst); SP(sd, rsrc); F__SZ_; + +/** 0000 0110 mx10 00sd 0001 0001 rsrc rdst itof %1%S1, %0 */ + ID(itof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* BIT OPS */ + +/** 1111 00sd rdst 0bit bset #%1, %0%S0 */ + ID(bset); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; + +/** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ + ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + +/** 0111 100b ittt rdst bset #%1, %0 */ + ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; + + +/** 1111 00sd rdst 1bit bclr #%1, %0%S0 */ + ID(bclr); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); F_____; + +/** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ + ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + +/** 0111 101b ittt rdst bclr #%1, %0 */ + ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; + + +/** 1111 01sd rdst 0bit btst #%2, %1%S1 */ + ID(btst); BWL(BSIZE); S2C(bit); SD(sd, rdst, BSIZE); F___ZC; + +/** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ + ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC; + +/** 0111 110b ittt rdst btst #%2, %1 */ + ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC; + + +/** 1111 1100 111bit sd rdst 1111 bnot #%1, %0%S0 */ + ID(bnot); BWL(BSIZE); SC(bit); DD(sd, rdst, BSIZE); + +/** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ + ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); + +/** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ + ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); + + +/** 1111 1100 111bit sd rdst cond bm%2 #%1, %0%S0 */ + ID(bmcc); BWL(BSIZE); S2cc(cond); SC(bit); DD(sd, rdst, BSIZE); + +/** 1111 1101 111 bittt cond rdst bm%2 #%1, %0%S0 */ + ID(bmcc); BWL(LSIZE); S2cc(cond); SC(bittt); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* CONTROL REGISTERS */ + +/** 0111 1111 1011 rdst clrpsw %0 */ + ID(clrpsw); DF(rdst); + +/** 0111 1111 1010 rdst setpsw %0 */ + ID(setpsw); DF(rdst); + +/** 0111 0101 0111 0000 0000 immm mvtipl #%1 */ + ID(mvtipl); SC(immm); + +/** 0111 1110 111 crdst popc %0 */ + ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(crdst + 16); + +/** 0111 1110 110 crsrc pushc %1 */ + ID(mov); OP(0, RX_Operand_Predec, 0, 0); SR(crsrc + 16); + +/** 1111 1101 0111 im11 000crdst mvtc #%1, %0 */ + ID(mov); SC(IMMex(im)); DR(crdst + 16); + +/** 1111 1101 0110 100c rsrc rdst mvtc %1, %0 */ + ID(mov); SR(rsrc); DR(c*16+rdst + 16); + +/** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */ + ID(mov); SR((s*16+rsrc) + 16); DR(rdst); + +/*----------------------------------------------------------------------*/ +/* INTERRUPTS */ + +/** 0111 1111 1001 0100 rtfi */ + ID(rtfi); + +/** 0111 1111 1001 0101 rte */ + ID(rte); + +/** 0000 0000 brk */ + ID(brk); + +/** 0000 0001 dbt */ + ID(dbt); + +/** 0111 0101 0110 0000 int #%1 */ + ID(int); SC(IMM(1)); + +/** 0111 1111 1001 0110 wait */ + ID(wait); + +/*----------------------------------------------------------------------*/ +/* SCcnd */ + +/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ + ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); + +/** */ + + return rx->n_bytes; +} diff --git a/external/gpl3/gdb/dist/opcodes/rx-dis.c b/external/gpl3/gdb/dist/opcodes/rx-dis.c new file mode 100644 index 000000000000..1cdb710047f0 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/rx-dis.c @@ -0,0 +1,200 @@ +/* Disassembler code for Renesas RX. + Copyright 2008, 2009 Free Software Foundation, Inc. + Contributed by Red Hat. + Written by DJ Delorie. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "bfd.h" +#include "dis-asm.h" +#include "opcode/rx.h" + +typedef struct +{ + bfd_vma pc; + disassemble_info * dis; +} RX_Data; + +static int +rx_get_byte (void * vdata) +{ + bfd_byte buf[1]; + RX_Data *rx_data = (RX_Data *) vdata; + + rx_data->dis->read_memory_func (rx_data->pc, + buf, + 1, + rx_data->dis); + + rx_data->pc ++; + return buf[0]; +} + +static char const * size_names[] = +{ + "", ".b", ".ub", ".b", ".w", ".uw", ".w", ".a", ".l" +}; + +static char const * opsize_names[] = +{ + "", ".b", ".b", ".b", ".w", ".w", ".w", ".a", ".l" +}; + +static char const * register_names[] = +{ + /* general registers */ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + /* control register */ + "psw", "pc", "usp", "fpsw", "", "", "", "wr", + "bpsw", "bpc", "isp", "fintv", "intb", "", "", "", + "pbp", "pben", "", "", "", "", "", "", + "bbpsw", "bbpc", "", "", "", "", "", "" +}; + +static char const * condition_names[] = +{ + /* condition codes */ + "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n", + "ge", "lt", "gt", "le", "o", "no", "always", "never" +}; + +static const char * flag_names[] = +{ + "c", "z", "s", "o", "", "", "", "", + "", "", "", "", "", "", "", "", + "i", "u", "", "", "", "", "", "" + "", "", "", "", "", "", "", "", +}; + +int +print_insn_rx (bfd_vma addr, disassemble_info * dis) +{ + int rv; + RX_Data rx_data; + RX_Opcode_Decoded opcode; + const char * s; + + rx_data.pc = addr; + rx_data.dis = dis; + + rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data); + + dis->bytes_per_line = 10; + +#define PR (dis->fprintf_func) +#define PS (dis->stream) +#define PC(c) PR (PS, "%c", c) + + for (s = opcode.syntax; *s; s++) + { + if (*s != '%') + { + PC (*s); + } + else + { + RX_Opcode_Operand * oper; + int do_size = 0; + int do_hex = 0; + int do_addr = 0; + + s ++; + + if (*s == 'S') + { + do_size = 1; + s++; + } + if (*s == 'x') + { + do_hex = 1; + s++; + } + if (*s == 'a') + { + do_addr = 1; + s++; + } + + switch (*s) + { + case '%': + PC ('%'); + break; + + case 's': + PR (PS, "%s", opsize_names[opcode.size]); + break; + + case '0': + case '1': + case '2': + oper = opcode.op + *s - '0'; + if (do_size) + { + if (oper->type == RX_Operand_Indirect) + PR (PS, "%s", size_names[oper->size]); + } + else + switch (oper->type) + { + case RX_Operand_Immediate: + if (do_addr) + dis->print_address_func (oper->addend, dis); + else if (do_hex + || oper->addend > 999 + || oper->addend < -999) + PR (PS, "%#x", oper->addend); + else + PR (PS, "%d", oper->addend); + break; + case RX_Operand_Register: + case RX_Operand_TwoReg: + PR (PS, "%s", register_names[oper->reg]); + break; + case RX_Operand_Indirect: + if (oper->addend) + PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]); + else + PR (PS, "[%s]", register_names[oper->reg]); + break; + case RX_Operand_Postinc: + PR (PS, "[%s+]", register_names[oper->reg]); + break; + case RX_Operand_Predec: + PR (PS, "[-%s]", register_names[oper->reg]); + break; + case RX_Operand_Condition: + PR (PS, "%s", condition_names[oper->reg]); + break; + case RX_Operand_Flag: + PR (PS, "%s", flag_names[oper->reg]); + break; + default: + PR (PS, "[???]"); + break; + } + } + } + } + + return rv; +} diff --git a/external/gpl3/gdb/dist/opcodes/s390-dis.c b/external/gpl3/gdb/dist/opcodes/s390-dis.c new file mode 100644 index 000000000000..37ed2e7d8865 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/s390-dis.c @@ -0,0 +1,307 @@ +/* s390-dis.c -- Disassemble S390 instructions + Copyright 2000, 2001, 2002, 2003, 2005, 2007, 2008 + Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "ansidecl.h" +#include "sysdep.h" +#include "dis-asm.h" +#include "opintl.h" +#include "opcode/s390.h" + +static int init_flag = 0; +static int opc_index[256]; +static int current_arch_mask = 0; + +/* Set up index table for first opcode byte. */ + +static void +init_disasm (struct disassemble_info *info) +{ + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + const char *p; + + memset (opc_index, 0, sizeof (opc_index)); + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes; opcode < opcode_end; opcode++) + { + opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; + while ((opcode < opcode_end) && + (opcode[1].opcode[0] == opcode->opcode[0])) + opcode++; + } + + for (p = info->disassembler_options; p != NULL; ) + { + if (CONST_STRNEQ (p, "esa")) + current_arch_mask = 1 << S390_OPCODE_ESA; + else if (CONST_STRNEQ (p, "zarch")) + current_arch_mask = 1 << S390_OPCODE_ZARCH; + else + fprintf (stderr, "Unknown S/390 disassembler option: %s\n", p); + + p = strchr (p, ','); + if (p != NULL) + p++; + } + + if (!current_arch_mask) + switch (info->mach) + { + case bfd_mach_s390_31: + current_arch_mask = 1 << S390_OPCODE_ESA; + break; + case bfd_mach_s390_64: + current_arch_mask = 1 << S390_OPCODE_ZARCH; + break; + default: + abort (); + } + + init_flag = 1; +} + +/* Extracts an operand value from an instruction. */ +/* We do not perform the shift operation for larl-type address + operands here since that would lead to an overflow of the 32 bit + integer value. Instead the shift operation is done when printing + the operand in print_insn_s390. */ + +static inline unsigned int +s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) +{ + unsigned int val; + int bits; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; + bits = (operand->shift & 7) + operand->bits; + val = 0; + do + { + val <<= 8; + val |= (unsigned int) *insn++; + bits -= 8; + } + while (bits > 0); + val >>= -bits; + val &= ((1U << (operand->bits - 1)) << 1) - 1; + + /* Check for special long displacement case. */ + if (operand->bits == 20 && operand->shift == 20) + val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; + + /* Sign extend value if the operand is signed or pc relative. */ + if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) + && (val & (1U << (operand->bits - 1)))) + val |= (-1U << (operand->bits - 1)) << 1; + + /* Length x in an instructions has real length x + 1. */ + if (operand->flags & S390_OPERAND_LENGTH) + val++; + return val; +} + +/* Print a S390 instruction. */ + +int +print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[6]; + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + unsigned int value; + int status, opsize, bufsize; + char separator; + + if (init_flag == 0) + init_disasm (info); + + /* The output looks better if we put 6 bytes on a line. */ + info->bytes_per_line = 6; + + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); + status = (*info->read_memory_func) (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) + if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* Opsize calculation looks strange but it works + 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, + 11xxxxxx -> 6 bytes. */ + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + status = opsize > bufsize; + } + else + { + bufsize = 6; + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + } + + if (status == 0) + { + const struct s390_opcode *op; + + /* Find the first match in the opcode table. */ + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; + (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); + opcode++) + { + const struct s390_operand *operand; + const unsigned char *opindex; + + /* Check architecture. */ + if (!(opcode->modes & current_arch_mask)) + continue; + + /* Check signature of the opcode. */ + if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] + || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] + || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] + || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] + || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) + continue; + + /* Advance to an opcode with a more specific mask. */ + for (op = opcode + 1; op < opcode_end; op++) + { + if ((buffer[0] & op->mask[0]) != op->opcode[0]) + break; + + if ((buffer[1] & op->mask[1]) != op->opcode[1] + || (buffer[2] & op->mask[2]) != op->opcode[2] + || (buffer[3] & op->mask[3]) != op->opcode[3] + || (buffer[4] & op->mask[4]) != op->opcode[4] + || (buffer[5] & op->mask[5]) != op->opcode[5]) + continue; + + if (((int)opcode->mask[0] + opcode->mask[1] + + opcode->mask[2] + opcode->mask[3] + + opcode->mask[4] + opcode->mask[5]) < + ((int)op->mask[0] + op->mask[1] + + op->mask[2] + op->mask[3] + + op->mask[4] + op->mask[5])) + opcode = op; + } + + /* The instruction is valid. */ + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Extract the operands. */ + separator = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = s390_operands + *opindex; + value = s390_extract_operand (buffer, operand); + + if ((operand->flags & S390_OPERAND_INDEX) && value == 0) + continue; + if ((operand->flags & S390_OPERAND_BASE) && + value == 0 && separator == '(') + { + separator = ','; + continue; + } + + if (separator) + (*info->fprintf_func) (info->stream, "%c", separator); + + if (operand->flags & S390_OPERAND_GPR) + (*info->fprintf_func) (info->stream, "%%r%i", value); + else if (operand->flags & S390_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%%f%i", value); + else if (operand->flags & S390_OPERAND_AR) + (*info->fprintf_func) (info->stream, "%%a%i", value); + else if (operand->flags & S390_OPERAND_CR) + (*info->fprintf_func) (info->stream, "%%c%i", value); + else if (operand->flags & S390_OPERAND_PCREL) + (*info->print_address_func) (memaddr + (int)value + (int)value, + info); + else if (operand->flags & S390_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%i", (int) value); + else + (*info->fprintf_func) (info->stream, "%u", value); + + if (operand->flags & S390_OPERAND_DISP) + { + separator = '('; + } + else if (operand->flags & S390_OPERAND_BASE) + { + (*info->fprintf_func) (info->stream, ")"); + separator = ','; + } + else + separator = ','; + } + + /* Found instruction, printed it, return its size. */ + return opsize; + } + /* No matching instruction found, fall through to hex print. */ + } + + if (bufsize >= 4) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; + (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); + return 4; + } + else if (bufsize >= 2) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); + return 2; + } + else + { + value = (unsigned int) buffer[0]; + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); + return 1; + } +} + +void +print_s390_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following S/390 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _(" esa Disassemble in ESA architecture mode\n")); + fprintf (stream, _(" zarch Disassemble in z/Architecture mode\n")); +} diff --git a/external/gpl3/gdb/dist/opcodes/s390-mkopc.c b/external/gpl3/gdb/dist/opcodes/s390-mkopc.c new file mode 100644 index 000000000000..b3f13ab53685 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/s390-mkopc.c @@ -0,0 +1,404 @@ +/* s390-mkopc.c -- Generates opcode table out of s390-opc.txt + Copyright 2000, 2001, 2003, 2005, 2007, 2008 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include + +/* Taken from opcodes/s390.h */ +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990, + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC, + S390_OPCODE_Z10, + S390_OPCODE_Z196 + }; + +struct op_struct + { + char opcode[16]; + char mnemonic[16]; + char format[16]; + int mode_bits; + int min_cpu; + + unsigned long long sort_value; + int no_nibbles; + }; + +struct op_struct *op_array; +int max_ops; +int no_ops; + +static void +createTable (void) +{ + max_ops = 256; + op_array = malloc (max_ops * sizeof (struct op_struct)); + no_ops = 0; +} + +/* `insertOpcode': insert an op_struct into sorted opcode array. */ + +static void +insertOpcode (char *opcode, char *mnemonic, char *format, + int min_cpu, int mode_bits) +{ + char *str; + unsigned long long sort_value; + int no_nibbles; + int ix, k; + + while (no_ops >= max_ops) + { + max_ops = max_ops * 2; + op_array = realloc (op_array, max_ops * sizeof (struct op_struct)); + } + + sort_value = 0; + str = opcode; + for (ix = 0; ix < 16; ix++) + { + if (*str >= '0' && *str <= '9') + sort_value = (sort_value << 4) + (*str - '0'); + else if (*str >= 'a' && *str <= 'f') + sort_value = (sort_value << 4) + (*str - 'a' + 10); + else if (*str >= 'A' && *str <= 'F') + sort_value = (sort_value << 4) + (*str - 'A' + 10); + else if (*str == '?') + sort_value <<= 4; + else + break; + str ++; + } + sort_value <<= 4*(16 - ix); + sort_value += (min_cpu << 8) + mode_bits; + no_nibbles = ix; + for (ix = 0; ix < no_ops; ix++) + if (sort_value > op_array[ix].sort_value) + break; + for (k = no_ops; k > ix; k--) + op_array[k] = op_array[k-1]; + strcpy(op_array[ix].opcode, opcode); + strcpy(op_array[ix].mnemonic, mnemonic); + strcpy(op_array[ix].format, format); + op_array[ix].sort_value = sort_value; + op_array[ix].no_nibbles = no_nibbles; + op_array[ix].min_cpu = min_cpu; + op_array[ix].mode_bits = mode_bits; + no_ops++; +} + +struct s390_cond_ext_format +{ + char nibble; + char extension[4]; +}; + +/* The mnemonic extensions for conditional jumps used to replace + the '*' tag. */ +#define NUM_COND_EXTENSIONS 20 +const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] = +{ { '1', "o" }, /* jump on overflow / if ones */ + { '2', "h" }, /* jump on A high */ + { '2', "p" }, /* jump on plus */ + { '3', "nle" }, /* jump on not low or equal */ + { '4', "l" }, /* jump on A low */ + { '4', "m" }, /* jump on minus / if mixed */ + { '5', "nhe" }, /* jump on not high or equal */ + { '6', "lh" }, /* jump on low or high */ + { '7', "ne" }, /* jump on A not equal B */ + { '7', "nz" }, /* jump on not zero / if not zeros */ + { '8', "e" }, /* jump on A equal B */ + { '8', "z" }, /* jump on zero / if zeros */ + { '9', "nlh" }, /* jump on not low or high */ + { 'a', "he" }, /* jump on high or equal */ + { 'b', "nl" }, /* jump on A not low */ + { 'b', "nm" }, /* jump on not minus / if not mixed */ + { 'c', "le" }, /* jump on low or equal */ + { 'd', "nh" }, /* jump on A not high */ + { 'd', "np" }, /* jump on not plus */ + { 'e', "no" }, /* jump on not overflow / if not ones */ +}; + +/* The mnemonic extensions for conditional branches used to replace + the '$' tag. */ +#define NUM_CRB_EXTENSIONS 12 +const struct s390_cond_ext_format s390_crb_extensions[NUM_CRB_EXTENSIONS] = +{ { '2', "h" }, /* jump on A high */ + { '2', "nle" }, /* jump on not low or equal */ + { '4', "l" }, /* jump on A low */ + { '4', "nhe" }, /* jump on not high or equal */ + { '6', "ne" }, /* jump on A not equal B */ + { '6', "lh" }, /* jump on low or high */ + { '8', "e" }, /* jump on A equal B */ + { '8', "nlh" }, /* jump on not low or high */ + { 'a', "nl" }, /* jump on A not low */ + { 'a', "he" }, /* jump on high or equal */ + { 'c', "nh" }, /* jump on A not high */ + { 'c', "le" }, /* jump on low or equal */ +}; + +/* As with insertOpcode instructions are added to the sorted opcode + array. Additionally mnemonics containing the '*' tag are + expanded to the set of conditional instructions described by + s390_cond_extensions with the tag replaced by the respective + mnemonic extensions. */ + +static void +insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, + int min_cpu, int mode_bits) +{ + char *tag; + char prefix[15]; + char suffix[15]; + char number[15]; + int mask_start, i = 0, tag_found = 0, reading_number = 0; + int number_p = 0, suffix_p = 0, prefix_p = 0; + const struct s390_cond_ext_format *ext_table; + int ext_table_length; + + if (!(tag = strpbrk (mnemonic, "*$"))) + { + insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits); + return; + } + + while (mnemonic[i] != '\0') + { + if (mnemonic[i] == *tag) + { + if (tag_found) + goto malformed_mnemonic; + + tag_found = 1; + reading_number = 1; + } + else + switch (mnemonic[i]) + { + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + if (!tag_found || !reading_number) + goto malformed_mnemonic; + + number[number_p++] = mnemonic[i]; + break; + + default: + if (reading_number) + { + if (!number_p) + goto malformed_mnemonic; + else + reading_number = 0; + } + + if (tag_found) + suffix[suffix_p++] = mnemonic[i]; + else + prefix[prefix_p++] = mnemonic[i]; + } + i++; + } + + prefix[prefix_p] = '\0'; + suffix[suffix_p] = '\0'; + number[number_p] = '\0'; + + if (sscanf (number, "%d", &mask_start) != 1) + goto malformed_mnemonic; + + if (mask_start & 3) + { + fprintf (stderr, "Conditional mask not at nibble boundary in: %s\n", + mnemonic); + return; + } + + mask_start >>= 2; + + switch (*tag) + { + case '*': + ext_table = s390_cond_extensions; + ext_table_length = NUM_COND_EXTENSIONS; + break; + case '$': + ext_table = s390_crb_extensions; + ext_table_length = NUM_CRB_EXTENSIONS; + break; + default: fprintf (stderr, "Unknown tag char: %c\n", *tag); + } + + for (i = 0; i < ext_table_length; i++) + { + char new_mnemonic[15]; + + strcpy (new_mnemonic, prefix); + opcode[mask_start] = ext_table[i].nibble; + strcat (new_mnemonic, ext_table[i].extension); + strcat (new_mnemonic, suffix); + insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits); + } + return; + + malformed_mnemonic: + fprintf (stderr, "Malformed mnemonic: %s\n", mnemonic); +} + +static char file_header[] = + "/* The opcode table. This file was generated by s390-mkopc.\n\n" + " The format of the opcode table is:\n\n" + " NAME OPCODE MASK OPERANDS\n\n" + " Name is the name of the instruction.\n" + " OPCODE is the instruction opcode.\n" + " MASK is the opcode mask; this is used to tell the disassembler\n" + " which bits in the actual opcode must match OPCODE.\n" + " OPERANDS is the list of operands.\n\n" + " The disassembler reads the table in order and prints the first\n" + " instruction which matches. */\n\n" + "const struct s390_opcode s390_opcodes[] =\n {\n"; + +/* `dumpTable': write opcode table. */ + +static void +dumpTable (void) +{ + char *str; + int ix; + + /* Write hash table entries (slots). */ + printf (file_header); + + for (ix = 0; ix < no_ops; ix++) + { + printf (" { \"%s\", ", op_array[ix].mnemonic); + for (str = op_array[ix].opcode; *str != 0; str++) + if (*str == '?') + *str = '0'; + printf ("OP%i(0x%sLL), ", + op_array[ix].no_nibbles*4, op_array[ix].opcode); + printf ("MASK_%s, INSTR_%s, ", + op_array[ix].format, op_array[ix].format); + printf ("%i, ", op_array[ix].mode_bits); + printf ("%i}", op_array[ix].min_cpu); + if (ix < no_ops-1) + printf (",\n"); + else + printf ("\n"); + } + printf ("};\n\n"); + printf ("const int s390_num_opcodes =\n"); + printf (" sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);\n\n"); +} + +int +main (void) +{ + char currentLine[256]; + + createTable (); + + /* Read opcode descriptions from `stdin'. For each mnemonic, + make an entry into the opcode table. */ + while (fgets (currentLine, sizeof (currentLine), stdin) != NULL) + { + char opcode[16]; + char mnemonic[16]; + char format[16]; + char description[80]; + char cpu_string[16]; + char modes_string[16]; + int min_cpu; + int mode_bits; + char *str; + + if (currentLine[0] == '#') + continue; + memset (opcode, 0, 8); + if (sscanf (currentLine, "%15s %15s %15s \"%79[^\"]\" %15s %15s", + opcode, mnemonic, format, description, + cpu_string, modes_string) == 6) + { + if (strcmp (cpu_string, "g5") == 0) + min_cpu = S390_OPCODE_G5; + else if (strcmp (cpu_string, "g6") == 0) + min_cpu = S390_OPCODE_G6; + else if (strcmp (cpu_string, "z900") == 0) + min_cpu = S390_OPCODE_Z900; + else if (strcmp (cpu_string, "z990") == 0) + min_cpu = S390_OPCODE_Z990; + else if (strcmp (cpu_string, "z9-109") == 0) + min_cpu = S390_OPCODE_Z9_109; + else if (strcmp (cpu_string, "z9-ec") == 0) + min_cpu = S390_OPCODE_Z9_EC; + else if (strcmp (cpu_string, "z10") == 0) + min_cpu = S390_OPCODE_Z10; + else if (strcmp (cpu_string, "z196") == 0) + min_cpu = S390_OPCODE_Z196; + else { + fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); + exit (1); + } + + str = modes_string; + mode_bits = 0; + do { + if (strncmp (str, "esa", 3) == 0 + && (str[3] == 0 || str[3] == ',')) { + mode_bits |= 1 << S390_OPCODE_ESA; + str += 3; + } else if (strncmp (str, "zarch", 5) == 0 + && (str[5] == 0 || str[5] == ',')) { + mode_bits |= 1 << S390_OPCODE_ZARCH; + str += 5; + } else { + fprintf (stderr, "Couldn't parse modes string %s\n", + modes_string); + exit (1); + } + if (*str == ',') + str++; + } while (*str != 0); + + insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits); + } + else + { + fprintf (stderr, "Couldn't scan line %s\n", currentLine); + exit (1); + } + } + + dumpTable (); + return 0; +} diff --git a/external/gpl3/gdb/dist/opcodes/s390-opc.c b/external/gpl3/gdb/dist/opcodes/s390-opc.c new file mode 100644 index 000000000000..2f1487d56960 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/s390-opc.c @@ -0,0 +1,495 @@ +/* s390-opc.c -- S390 opcode list + Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 + Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/s390.h" + +/* This file holds the S390 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* The operands table. + The fields are bits, shift, insert, extract, flags. */ + +const struct s390_operand s390_operands[] = +{ +#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + +/* General purpose register operands. */ + +#define R_8 1 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +#define R_12 2 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +#define RO_12 3 /* optional GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR|S390_OPERAND_OPTIONAL }, +#define R_16 4 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +#define R_20 5 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +#define R_24 6 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +#define R_28 7 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +#define RO_28 8 /* optional GPR starting at position 28 */ + { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) }, +#define R_32 9 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + +/* Floating point register operands. */ + +#define F_8 10 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +#define F_12 11 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +#define F_16 12 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_20 13 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_24 14 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +#define F_28 15 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +#define F_32 16 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + +/* Access register operands. */ + +#define A_8 17 /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +#define A_12 18 /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +#define A_24 19 /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +#define A_28 20 /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + +/* Control register operands. */ + +#define C_8 21 /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +#define C_12 22 /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + +/* Base register operands. */ + +#define B_16 23 /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, +#define B_32 24 /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, + +#define X_12 25 /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, + +/* Address displacement operands. */ + +#define D_20 26 /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +#define DO_20 27 /* optional Displ. starting at position 20 */ + { 12, 20, S390_OPERAND_DISP|S390_OPERAND_OPTIONAL }, +#define D_36 28 /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, +#define D20_20 29 /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, + +/* Length operands. */ + +#define L4_8 30 /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +#define L4_12 31 /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +#define L8_8 32 /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + +/* Signed immediate operands. */ + +#define I8_8 33 /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +#define I8_32 34 /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +#define I16_16 35 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define I16_32 36 /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +#define I32_16 37 /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + +/* Unsigned immediate operands. */ + +#define U4_8 38 /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +#define U4_12 39 /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +#define U4_16 40 /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +#define U4_20 41 /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +#define U4_32 42 /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +#define U8_8 43 /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +#define U8_16 44 /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +#define U8_24 45 /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +#define U8_32 46 /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +#define U16_16 47 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +#define U16_32 48 /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +#define U32_16 49 /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + +/* PC-relative address operands. */ + +#define J16_16 50 /* PC relative jump offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +#define J32_16 51 /* PC relative long offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + +/* Conditional mask operands. */ + +#define M_16OPT 52 /* 4 bit optional mask starting at 16 */ + { 4, 16, S390_OPERAND_OPTIONAL }, + +}; + + +/* Macros used to form opcodes. */ + +/* 8/16/48 bit opcodes. */ +#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } +#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ + (x >> 16) & 255, (x >> 8) & 255, x & 255} + +/* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: + 1) the middle part of the definition (x in INSTR_x_y) is the official + names of the instruction format that you can find in the principals + of operation. + 2) the last part of the definition (y in INSTR_x_y) gives you an idea + which operands the binary represenation of the instruction has. + The meanings of the letters in y are: + a - access register + c - control register + d - displacement, 12 bit + f - floating pointer register + i - signed integer, 4, 8, 16 or 32 bit + l - length, 4 or 8 bit + p - pc relative + r - general purpose register + u - unsigned integer, 4, 8, 16 or 32 bit + m - mode field, 4 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in + storage and not the order of the paramaters of the instructions. + The use of the letters is not a 100% match with the PoP but it is + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: + + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- + | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | + -------------------------------------- + 0 8 12 16 20 32 36 + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ +#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ +#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ +#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ +#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ +#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ +#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ +#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ +#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ +#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ +#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ +#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ +#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ +#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ +#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ +#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ +#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ +#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ +#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ +#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ +/* Actually efpc and sfpc do not take an optional operand. + This is just a workaround for existing code e.g. glibc. */ +#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ +#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ +#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ +#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ +#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ +#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ +#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */ +#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ +#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ +#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ +#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_0R_OPT 2, { RO_12, 0,0,0,0,0 } /* e.g. nopr */ +#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ +#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ +#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ +#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ +#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ +#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ +#define INSTR_RSY_RDRM 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +#define INSTR_RSY_RDR0 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. loc */ +#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ +#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ +#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ +#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ +#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_0RRD_OPT 4, { DO_20,X_12,B_16,0,0,0 } /* e.g. nop */ +#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ +#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ +#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ +#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ +#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ +#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ +#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ +#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ + +#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PI { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_0R_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_0RRD_OPT { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + + +/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + +const struct s390_opcode s390_opformats[] = + { + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, +}; + +const int s390_num_opformats = + sizeof (s390_opformats) / sizeof (s390_opformats[0]); + +#include "s390-opc.tab" diff --git a/external/gpl3/gdb/dist/opcodes/s390-opc.txt b/external/gpl3/gdb/dist/opcodes/s390-opc.txt new file mode 100644 index 000000000000..4aa0da7ca78e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/s390-opc.txt @@ -0,0 +1,1095 @@ +# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table. +# Copyright 2000, 2001, 2003, 2004, 2005, 2007, 2008, 2009 +# Free Software Foundation, Inc. +# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). +5a a RX_RRRD "add" g5 esa,zarch +6a ad RX_FRRD "add normalized (long)" g5 esa,zarch +2a adr RR_FF "add normalized (long)" g5 esa,zarch +7a ae RX_FRRD "add normalized (short)" g5 esa,zarch +3a aer RR_FF "add normalized (short)" g5 esa,zarch +4a ah RX_RRRD "add halfword" g5 esa,zarch +5e al RX_RRRD "add logical" g5 esa,zarch +1e alr RR_RR "add logical" g5 esa,zarch +fa ap SS_LLRDRD "add decimal" g5 esa,zarch +1a ar RR_RR "add" g5 esa,zarch +7e au RX_FRRD "add unnormalized (short)" g5 esa,zarch +3e aur RR_FF "add unnormalized (short)" g5 esa,zarch +6e aw RX_FRRD "add unnormalized (long)" g5 esa,zarch +2e awr RR_FF "add unnormalized (long)" g5 esa,zarch +36 axr RR_FF "add normalized" g5 esa,zarch +b240 bakr RRE_RR "branch and stack" g5 esa,zarch +45 bal RX_RRRD "branch and link" g5 esa,zarch +05 balr RR_RR "branch and link" g5 esa,zarch +4d bas RX_RRRD "branch and save" g5 esa,zarch +0d basr RR_RR "branch and save" g5 esa,zarch +0c bassm RR_RR "branch and save and set mode" g5 esa,zarch +47 bc RX_URRD "branch on condition" g5 esa,zarch +07 bcr RR_UR "branch on condition" g5 esa,zarch +46 bct RX_RRRD "branch on count" g5 esa,zarch +06 bctr RR_RR "branch on count" g5 esa,zarch +b258 bsg RRE_RR "branch in subspace group" g5 esa,zarch +0b bsm RR_RR "branch and set mode" g5 esa,zarch +86 bxh RS_RRRD "branch on index high" g5 esa,zarch +87 bxle RS_RRRD "branch on index low or equal" g5 esa,zarch +59 c RX_RRRD "compare" g5 esa,zarch +69 cd RX_FRRD "compare (long)" g5 esa,zarch +29 cdr RR_FF "compare (long)" g5 esa,zarch +bb cds RS_RRRD "compare double and swap" g5 esa,zarch +79 ce RX_FRRD "compare (short)" g5 esa,zarch +39 cer RR_FF "compare (short)" g5 esa,zarch +b21a cfc S_RD "compare and form codeword" g5 esa,zarch +49 ch RX_RRRD "compare halfword" g5 esa,zarch +55 cl RX_RRRD "compare logical" g5 esa,zarch +d5 clc SS_L0RDRD "compare logical" g5 esa,zarch +0f clcl RR_RR "compare logical long" g5 esa,zarch +95 cli SI_URD "compare logical" g5 esa,zarch +bd clm RS_RURD "compare logical characters under mask" g5 esa,zarch +15 clr RR_RR "compare logical" g5 esa,zarch +b25d clst RRE_RR "compare logical string" g5 esa,zarch +f9 cp SS_LLRDRD "compare decimal" g5 esa,zarch +b24d cpya RRE_AA "copy access" g5 esa,zarch +19 cr RR_RR "compare" g5 esa,zarch +ba cs RS_RRRD "compare and swap" g5 esa,zarch +b230 csch S_00 "clear subchannel" g5 esa,zarch +b257 cuse RRE_RR "compare until substring equal" g5 esa,zarch +b250 csp RRE_RR "compare and swap and purge" g5 esa,zarch +4f cvb RX_RRRD "convert to binary" g5 esa,zarch +4e cvd RX_RRRD "convert to decimal" g5 esa,zarch +5d d RX_RRRD "divide" g5 esa,zarch +6d dd RX_FRRD "divide (long)" g5 esa,zarch +2d ddr RR_FF "divide (long)" g5 esa,zarch +7d de RX_FRRD "divide (short)" g5 esa,zarch +3d der RR_FF "divide (short)" g5 esa,zarch +83 diag RS_RRRD "diagnose" g5 esa,zarch +fd dp SS_LLRDRD "divide decimal" g5 esa,zarch +1d dr RR_RR "divide" g5 esa,zarch +b22d dxr RRE_FF "divide (ext.)" g5 esa,zarch +b24f ear RRE_RA "extract access" g5 esa,zarch +de ed SS_L0RDRD "edit" g5 esa,zarch +df edmk SS_L0RDRD "edit and mark" g5 esa,zarch +b226 epar RRE_R0 "extract primary ASN" g5 esa,zarch +b249 ereg RRE_RR "extract stacked registers" g5 esa,zarch +b227 esar RRE_R0 "extract secondary ASN" g5 esa,zarch +b24a esta RRE_RR "extract stacked state" g5 esa,zarch +44 ex RX_RRRD "execute" g5 esa,zarch +24 hdr RR_FF "halve (long)" g5 esa,zarch +34 her RR_FF "halve (short)" g5 esa,zarch +b231 hsch S_00 "halt subchannel" g5 esa,zarch +b224 iac RRE_R0 "insert address space control" g5 esa,zarch +43 ic RX_RRRD "insert character" g5 esa,zarch +bf icm RS_RURD "insert characters under mask" g5 esa,zarch +b20b ipk S_00 "insert PSW key" g5 esa,zarch +b222 ipm RRE_R0 "insert program mask" g5 esa,zarch +b221 ipte RRE_RR "invalidate page table entry" g5 esa,zarch +b229 iske RRE_RR "insert storage key extended" g5 esa,zarch +b223 ivsk RRE_RR "insert virtual storage key" g5 esa,zarch +58 l RX_RRRD "load" g5 esa,zarch +41 la RX_RRRD "load address" g5 esa,zarch +51 lae RX_RRRD "load address extended" g5 esa,zarch +9a lam RS_AARD "load access multiple" g5 esa,zarch +e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch +23 lcdr RR_FF "load complement (long)" g5 esa,zarch +33 lcer RR_FF "load complement (short)" g5 esa,zarch +13 lcr RR_RR "load complement" g5 esa,zarch +b7 lctl RS_CCRD "load control" g5 esa,zarch +68 ld RX_FRRD "load (long)" g5 esa,zarch +28 ldr RR_FF "load (long)" g5 esa,zarch +78 le RX_FRRD "load (short)" g5 esa,zarch +38 ler RR_FF "load (short)" g5 esa,zarch +48 lh RX_RRRD "load halfword" g5 esa,zarch +98 lm RS_RRRD "load multiple" g5 esa,zarch +21 lndr RR_FF "load negative (long)" g5 esa,zarch +31 lner RR_FF "load negative (short)" g5 esa,zarch +11 lnr RR_RR "load negative" g5 esa,zarch +20 lpdr RR_FF "load positive (long)" g5 esa,zarch +30 lper RR_FF "load positive (short)" g5 esa,zarch +10 lpr RR_RR "load positive" g5 esa,zarch +82 lpsw S_RD "load PSW" g5 esa,zarch +18 lr RR_RR "load" g5 esa,zarch +b1 lra RX_RRRD "load real address" g5 esa,zarch +25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch +25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch +35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch +35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch +22 ltdr RR_FF "load and test (long)" g5 esa,zarch +32 lter RR_FF "load and test (short)" g5 esa,zarch +12 ltr RR_RR "load and test" g5 esa,zarch +b24b lura RRE_RR "load using real address" g5 esa,zarch +5c m RX_RRRD "multiply" g5 esa,zarch +af mc SI_URD "monitor call" g5 esa,zarch +6c md RX_FRRD "multiply (long)" g5 esa,zarch +2c mdr RR_FF "multiply (long)" g5 esa,zarch +7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch +7c me RX_FRRD "multiply (short to long)" g5 esa,zarch +3c mder RR_FF "multiply short to long hfp" g5 esa,zarch +3c mer RR_FF "multiply (short to long)" g5 esa,zarch +4c mh RX_RRRD "multiply halfword" g5 esa,zarch +fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch +1c mr RR_RR "multiply" g5 esa,zarch +b232 msch S_RD "modify subchannel" g5 esa,zarch +b247 msta RRE_R0 "modify stacked state" g5 esa,zarch +d2 mvc SS_L0RDRD "move" g5 esa,zarch +e50f mvcdk SSE_RDRD "move with destination key" g5 esa,zarch +e8 mvcin SS_L0RDRD "move inverse" g5 esa,zarch +d9 mvck SS_RRRDRD "move with key" g5 esa,zarch +0e mvcl RR_RR "move long" g5 esa,zarch +da mvcp SS_RRRDRD "move to primary" g5 esa,zarch +db mvcs SS_RRRDRD "move to secondary" g5 esa,zarch +e50e mvcsk SSE_RDRD "move with source key" g5 esa,zarch +92 mvi SI_URD "move" g5 esa,zarch +d1 mvn SS_L0RDRD "move numerics" g5 esa,zarch +f1 mvo SS_LLRDRD "move with offset" g5 esa,zarch +b254 mvpg RRE_RR "move page" g5 esa,zarch +b255 mvst RRE_RR "move string" g5 esa,zarch +d3 mvz SS_L0RDRD "move zones" g5 esa,zarch +67 mxd RX_FRRD "multiply (long to ext.)" g5 esa,zarch +27 mxdr RR_FF "multiply (long to ext.)" g5 esa,zarch +26 mxr RR_FF "multiply (ext.)" g5 esa,zarch +54 n RX_RRRD "AND" g5 esa,zarch +d4 nc SS_L0RDRD "AND" g5 esa,zarch +94 ni SI_URD "AND" g5 esa,zarch +14 nr RR_RR "AND" g5 esa,zarch +56 o RX_RRRD "OR" g5 esa,zarch +d6 oc SS_L0RDRD "OR" g5 esa,zarch +96 oi SI_URD "OR" g5 esa,zarch +16 or RR_RR "OR" g5 esa,zarch +f2 pack SS_LLRDRD "pack" g5 esa,zarch +b248 palb RRE_00 "purge ALB" g5 esa,zarch +b218 pc S_RD "program call" g5 esa,zarch +0101 pr E "program return" g5 esa,zarch +b228 pt RRE_RR "program transfer" g5 esa,zarch +b20d ptlb S_00 "purge TLB" g5 esa,zarch +b23b rchp S_00 "reset channel path" g5 esa,zarch +b22a rrbe RRE_RR "reset reference bit extended" g5 esa,zarch +b238 rsch S_00 "resume subchannel" g5 esa,zarch +5b s RX_RRRD "subtract" g5 esa,zarch +b219 sac S_RD "set address space control" g5 esa,zarch +b279 sacf S_RD "set address space control fast" g5 esa,zarch +b237 sal S_00 "set address limit" g5 esa,zarch +b24e sar RRE_AR "set access" g5 esa,zarch +b23c schm S_00 "set channel monitor" g5 esa,zarch +b204 sck S_RD "set clock" g5 esa,zarch +b206 sckc S_RD "set clock comparator" g5 esa,zarch +6b sd RX_FRRD "subtract normalized (long)" g5 esa,zarch +2b sdr RR_FF "subtract normalized (long)" g5 esa,zarch +7b se RX_FRRD "subtract normalized (short)" g5 esa,zarch +3b ser RR_FF "subtract normalized (short)" g5 esa,zarch +4b sh RX_RRRD "subtract halfword" g5 esa,zarch +b214 sie S_RD "start interpretive execution" g5 esa,zarch +ae sigp RS_RRRD "signal processor" g5 esa,zarch +5f sl RX_RRRD "subtract logical" g5 esa,zarch +8b sla RS_R0RD "shift left single" g5 esa,zarch +8f slda RS_R0RD "shift left double (long)" g5 esa,zarch +8d sldl RS_R0RD "shift left double logical (long)" g5 esa,zarch +89 sll RS_R0RD "shift left single logical" g5 esa,zarch +1f slr RR_RR "subtract logical" g5 esa,zarch +fb sp SS_LLRDRD "subtract decimal" g5 esa,zarch +b20a spka S_RD "set PSW key from address" g5 esa,zarch +04 spm RR_R0 "set program mask" g5 esa,zarch +b208 spt S_RD "set CPU timer" g5 esa,zarch +b210 spx S_RD "set prefix" g5 esa,zarch +b244 sqdr RRE_FF "square root (long)" g5 esa,zarch +b245 sqer RRE_FF "square root (short)" g5 esa,zarch +1b sr RR_RR "subtract" g5 esa,zarch +8a sra RS_R0RD "shift right single" g5 esa,zarch +8e srda RS_R0RD "shift right double (long)" g5 esa,zarch +8c srdl RS_R0RD "shift right double logical (long)" g5 esa,zarch +88 srl RS_R0RD "shift right single logical" g5 esa,zarch +f0 srp SS_LIRDRD "shift and round decimal" g5 esa,zarch +b25e srst RRE_RR "search string" g5 esa,zarch +b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch +b233 ssch S_RD "start subchannel" g5 esa,zarch +b22b sske RRE_RR "set storage key extended" g5 esa,zarch +80 ssm S_RD "set system mask" g5 esa,zarch +50 st RX_RRRD "store" g5 esa,zarch +9b stam RS_AARD "store access multiple" g5 esa,zarch +b212 stap S_RD "store CPU address" g5 esa,zarch +42 stc RX_RRRD "store character" g5 esa,zarch +b205 stck S_RD "store clock" g5 esa,zarch +b207 stckc S_RD "store clock comparator" g5 esa,zarch +be stcm RS_RURD "store characters under mask" g5 esa,zarch +b23a stcps S_RD "store channel path status" g5 esa,zarch +b239 stcrw S_RD "store channel report word" g5 esa,zarch +b6 stctl RS_CCRD "store control" g5 esa,zarch +60 std RX_FRRD "store (long)" g5 esa,zarch +70 ste RX_FRRD "store (short)" g5 esa,zarch +40 sth RX_RRRD "store halfword" g5 esa,zarch +b202 stidp S_RD "store CPU id" g5 esa,zarch +90 stm RS_RRRD "store multiple" g5 esa,zarch +ac stnsm SI_URD "store then AND system mask" g5 esa,zarch +ad stosm SI_URD "store then OR system mask" g5 esa,zarch +b209 stpt S_RD "store CPU timer" g5 esa,zarch +b211 stpx S_RD "store prefix" g5 esa,zarch +b234 stsch S_RD "store subchannel" g5 esa,zarch +b246 stura RRE_RR "store using real address" g5 esa,zarch +7f su RX_FRRD "subtract unnormalized (short)" g5 esa,zarch +3f sur RR_FF "subtract unnormalized (short)" g5 esa,zarch +0a svc RR_U0 "supervisor call" g5 esa,zarch +6f sw RX_FRRD "subtract unnormalized (long)" g5 esa,zarch +2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch +37 sxr RR_FF "subtract normalized (ext.)" g5 esa,zarch +b24c tar RRE_AR "test access" g5 esa,zarch +b22c tb RRE_0R "test block" g5 esa,zarch +91 tm SI_URD "test under mask" g5 esa,zarch +b236 tpi S_RD "test pending interruption" g5 esa,zarch +e501 tprot SSE_RDRD "test protection" g5 esa,zarch +dc tr SS_L0RDRD "translate" g5 esa,zarch +99 trace RS_RRRD "trace" g5 esa,zarch +dd trt SS_L0RDRD "translate and test" g5 esa,zarch +93 ts S_RD "test and set" g5 esa,zarch +b235 tsch S_RD "test subchannel" g5 esa,zarch +f3 unpk SS_LLRDRD "unpack" g5 esa,zarch +0102 upt E "update tree" g5 esa,zarch +57 x RX_RRRD "exclusive OR" g5 esa,zarch +d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch +97 xi SI_URD "exclusive OR" g5 esa,zarch +17 xr RR_RR "exclusive OR" g5 esa,zarch +f8 zap SS_LLRDRD "zero and add" g5 esa,zarch +a70a ahi RI_RI "add halfword immediate" g5 esa,zarch +84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch +85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch +a705 bras RI_RP "branch relative and save" g5 esa,zarch +a704 brc RI_UP "branch relative on condition" g5 esa,zarch +a706 brct RI_RP "branch relative on count" g5 esa,zarch +b241 cksm RRE_RR "checksum" g5 esa,zarch +a70e chi RI_RI "compare halfword immediate" g5 esa,zarch +a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch +a708 lhi RI_RI "load halfword immediate" g5 esa,zarch +a8 mvcle RS_RRRD "move long extended" g5 esa,zarch +a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch +b252 msr RRE_RR "multiply single" g5 esa,zarch +71 ms RX_RRRD "multiply single" g5 esa,zarch +a700 tmlh RI_RU "test under mask low high" g5 esa,zarch +a700 tmh RI_RU "test under mask high" g5 esa,zarch +a701 tmll RI_RU "test under mask low low" g5 esa,zarch +a701 tml RI_RU "test under mask low" g5 esa,zarch +0700 nopr RR_0R_OPT "no operation" g5 esa,zarch +0700 b*8r RR_0R "conditional branch" g5 esa,zarch +07f0 br RR_0R "unconditional branch" g5 esa,zarch +4700 nop RX_0RRD_OPT "no operation" g5 esa,zarch +4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch +47f0 b RX_0RRD "unconditional branch" g5 esa,zarch +a704 j*8 RI_0P "conditional jump" g5 esa,zarch +a7f4 j RI_0P "unconditional jump" g5 esa,zarch +b34a axbr RRE_FF "add extended bfp" g5 esa,zarch +b31a adbr RRE_FF "add long bfp" g5 esa,zarch +ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch +b30a aebr RRE_FF "add short bfp" g5 esa,zarch +ed000000000a aeb RXE_FRRD "add short bfp" g5 esa,zarch +b349 cxbr RRE_FF "compare extended bfp" g5 esa,zarch +b319 cdbr RRE_FF "compare long bfp" g5 esa,zarch +ed0000000019 cdb RXE_FRRD "compare long bfp" g5 esa,zarch +b309 cebr RRE_FF "compare short bfp" g5 esa,zarch +ed0000000009 ceb RXE_FRRD "compare short bfp" g5 esa,zarch +b348 kxbr RRE_FF "compare and signal extended bfp" g5 esa,zarch +b318 kdbr RRE_FF "compare and signal long bfp" g5 esa,zarch +ed0000000018 kdb RXE_FRRD "compare and signal long bfp" g5 esa,zarch +b308 kebr RRE_FF "compare and signal short bfp" g5 esa,zarch +ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch +b396 cxfbr RRE_FR "convert from fixed 32 to extended bfp" g5 esa,zarch +b395 cdfbr RRE_FR "convert from fixed 32 to long bfp" g5 esa,zarch +b394 cefbr RRE_FR "convert from fixed 32 to short bfp" g5 esa,zarch +b39a cfxbr RRF_U0RF "convert to fixed extended bfp to 32" g5 esa,zarch +b399 cfdbr RRF_U0RF "convert to fixed long bfp to 32" g5 esa,zarch +b398 cfebr RRF_U0RF "convert to fixed short bfp to 32" g5 esa,zarch +b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch +b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch +ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch +b30d debr RRE_FF "divide short bfp" g5 esa,zarch +ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch +b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch +b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch +b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch +b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch +b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch +b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch +b343 lcxbr RRE_FF "load complement extended bfp" g5 esa,zarch +b313 lcdbr RRE_FF "load complement long bfp" g5 esa,zarch +b303 lcebr RRE_FF "load complement short bfp" g5 esa,zarch +b347 fixbr RRF_U0FF "load fp integer extended bfp" g5 esa,zarch +b35f fidbr RRF_U0FF "load fp integer long bfp" g5 esa,zarch +b357 fiebr RRF_U0FF "load fp integer short bfp" g5 esa,zarch +b29d lfpc S_RD "load fpc" g5 esa,zarch +b305 lxdbr RRE_FF "load lengthened long to extended bfp" g5 esa,zarch +ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" g5 esa,zarch +b306 lxebr RRE_FF "load lengthened short to extended bfp" g5 esa,zarch +ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" g5 esa,zarch +b304 ldebr RRE_FF "load lengthened short to long bfp" g5 esa,zarch +ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" g5 esa,zarch +b341 lnxbr RRE_FF "load negative extended bfp" g5 esa,zarch +b311 lndbr RRE_FF "load negative long bfp" g5 esa,zarch +b301 lnebr RRE_FF "load negative short bfp" g5 esa,zarch +b340 lpxbr RRE_FF "load positive extended bfp" g5 esa,zarch +b310 lpdbr RRE_FF "load positive long bfp" g5 esa,zarch +b300 lpebr RRE_FF "load positive short bfp" g5 esa,zarch +b345 ldxbr RRE_FF "load rounded extended to long bfp" g5 esa,zarch +b346 lexbr RRE_FF "load rounded extended to short bfp" g5 esa,zarch +b344 ledbr RRE_FF "load rounded long to short bfp" g5 esa,zarch +b34c mxbr RRE_FF "multiply extended bfp" g5 esa,zarch +b31c mdbr RRE_FF "multiply long bfp" g5 esa,zarch +ed000000001c mdb RXE_FRRD "multiply long bfp" g5 esa,zarch +b307 mxdbr RRE_FF "multiply long to extended bfp" g5 esa,zarch +ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" g5 esa,zarch +b317 meebr RRE_FF "multiply short bfp" g5 esa,zarch +ed0000000017 meeb RXE_FRRD "multiply short bfp" g5 esa,zarch +b30c mdebr RRE_FF "multiply short to long bfp" g5 esa,zarch +ed000000000c mdeb RXE_FRRD "multiply short to long bfp" g5 esa,zarch +b31e madbr RRF_F0FF "multiply and add long bfp" g5 esa,zarch +ed000000001e madb RXF_FRRDF "multiply and add long bfp" g5 esa,zarch +b30e maebr RRF_F0FF "multiply and add short bfp" g5 esa,zarch +ed000000000e maeb RXF_FRRDF "multiply and add short bfp" g5 esa,zarch +b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch +ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch +b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch +ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch +b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch +b299 srnm S_RD "set rounding mode" g5 esa,zarch +b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch +b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch +ed0000000015 sqdb RXE_FRRD "square root long bfp" g5 esa,zarch +b314 sqebr RRE_FF "square root short bfp" g5 esa,zarch +ed0000000014 sqeb RXE_FRRD "square root short bfp" g5 esa,zarch +b29c stfpc S_RD "store fpc" g5 esa,zarch +b34b sxbr RRE_FF "subtract extended bfp" g5 esa,zarch +b31b sdbr RRE_FF "subtract long bfp" g5 esa,zarch +ed000000001b sdb RXE_FRRD "subtract long bfp" g5 esa,zarch +b30b sebr RRE_FF "subtract short bfp" g5 esa,zarch +ed000000000b seb RXE_FRRD "subtract short bfp" g5 esa,zarch +ed0000000012 tcxb RXE_FRRD "test data class extended bfp" g5 esa,zarch +ed0000000011 tcdb RXE_FRRD "test data class long bfp" g5 esa,zarch +ed0000000010 tceb RXE_FRRD "test data class short bfp" g5 esa,zarch +b274 siga S_RD "signal adapter" g5 esa,zarch +b2a6 cuutf RRE_RR "convert unicode to utf-8" g5 esa,zarch +b2a7 cutfu RRE_RR "convert utf-8 to unicode" g5 esa,zarch +ee plo SS_RRRDRD2 "perform locked operation" g5 esa,zarch +b25a bsa RRE_RR "branch and set authority" g5 esa,zarch +b277 rp S_RD "resume program" g5 esa,zarch +0107 sckpf E "set clock programmable field" g5 esa,zarch +b27d stsi S_RD "store system information" g5 esa,zarch +01ff trap2 E "trap" g5 esa,zarch +b2ff trap4 S_RD "trap4" g5 esa,zarch +b278 stcke S_RD "store clock extended" g5 esa,zarch +b2a5 tre RRE_RR "translate extended" g5 esa,zarch +eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch +e9 pka SS_L2RDRD "pack ascii" g5 esa,zarch +e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch +b993 troo RRE_RR "translate one to one" g5 esa,zarch +b992 trot RRE_RR "translate one to two" g5 esa,zarch +b991 trto RRE_RR "translate two to one" g5 esa,zarch +b990 trtt RRE_RR "translate two to two" g5 esa,zarch +ea unpka SS_L0RDRD "unpack ascii" g5 esa,zarch +e2 unpku SS_L0RDRD "unpack unicode" g5 esa,zarch +b358 thder RRE_FF "convert short bfp to long hfp" g5 esa,zarch +b359 thdr RRE_FF "convert long bfp to long hfp" g5 esa,zarch +b350 tbedr RRF_U0FF "convert long hfp to short bfp" g5 esa,zarch +b351 tbdr RRF_U0FF "convert long hfp to long bfp" g5 esa,zarch +b374 lzer RRE_F0 "load short zero" g5 esa,zarch +b375 lzdr RRE_F0 "load long zero" g5 esa,zarch +b376 lzxr RRE_F0 "load extended zero" g5 esa,zarch +# Here are the new esame instructions: +b946 bctgr RRE_RR "branch on count 64" z900 zarch +b900 lpgr RRE_RR "load positive 64" z900 zarch +b910 lpgfr RRE_RR "load positive 64<32" z900 zarch +b901 lngr RRE_RR "load negative 64" z900 zarch +b911 lngfr RRE_RR "load negative 64<32" z900 zarch +b902 ltgr RRE_RR "load and test 64" z900 zarch +b912 ltgfr RRE_RR "load and test 64<32" z900 zarch +b903 lcgr RRE_RR "load complement 64" z900 zarch +b913 lcgfr RRE_RR "load complement 64<32" z900 zarch +b980 ngr RRE_RR "and 64" z900 zarch +b921 clgr RRE_RR "compare logical 64" z900 zarch +b931 clgfr RRE_RR "compare logical 64<32" z900 zarch +b981 ogr RRE_RR "or 64" z900 zarch +b982 xgr RRE_RR "exclusive or 64" z900 zarch +b904 lgr RRE_RR "load 64" z900 zarch +b914 lgfr RRE_RR "load 64<32" z900 zarch +b920 cgr RRE_RR "compare 64" z900 zarch +b930 cgfr RRE_RR "compare 64<32" z900 zarch +b908 agr RRE_RR "add 64" z900 zarch +b918 agfr RRE_RR "add 64<32" z900 zarch +b909 sgr RRE_RR "subtract 64" z900 zarch +b919 sgfr RRE_RR "subtract 64<32" z900 zarch +b90a algr RRE_RR "add logical 64" z900 zarch +b91a algfr RRE_RR "add logical 64<32" z900 zarch +b90b slgr RRE_RR "subtract logical 64" z900 zarch +b91b slgfr RRE_RR "subtract logical 64<32" z900 zarch +e30000000046 bctg RXE_RRRD "branch on count 64" z900 zarch +e3000000002e cvdg RXE_RRRD "convert to decimal 64" z900 zarch +e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch +e30000000024 stg RXE_RRRD "store 64" z900 zarch +e30000000080 ng RXE_RRRD "and 64" z900 zarch +e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch +e30000000031 clgf RXE_RRRD "compare logical 64<32" z900 zarch +e30000000081 og RXE_RRRD "or 64" z900 zarch +e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch +e30000000004 lg RXE_RRRD "load 64" z900 zarch +e30000000014 lgf RXE_RRRD "load 64<32" z900 zarch +e30000000015 lgh RXE_RRRD "load halfword 64" z900 zarch +e30000000020 cg RXE_RRRD "compare 64" z900 zarch +e30000000030 cgf RXE_RRRD "compare 64<32" z900 zarch +e30000000008 ag RXE_RRRD "add 64" z900 zarch +e30000000018 agf RXE_RRRD "add 64<32" z900 zarch +e30000000009 sg RXE_RRRD "subtract 64" z900 zarch +e30000000019 sgf RXE_RRRD "subtract 64<32" z900 zarch +e3000000000a alg RXE_RRRD "add logical 64" z900 zarch +e3000000001a algf RXE_RRRD "add logical 64<32" z900 zarch +e3000000000b slg RXE_RRRD "subtract logical 64" z900 zarch +e3000000001b slgf RXE_RRRD "subtract logical 64<32" z900 zarch +e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch +e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch +ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch +ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch +eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch +eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch +eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch +eb000000000d sllg RSE_RRRD "shift left single logical 64" z900 zarch +eb000000000a srag RSE_RRRD "shift right single 64" z900 zarch +eb000000000b slag RSE_RRRD "shift left single 64" z900 zarch +eb0000000024 stmg RSE_RRRD "store multiple 64" z900 zarch +eb0000000026 stmh RSE_RRRD "store multiple high" z900 zarch +eb0000000004 lmg RSE_RRRD "load multiple 64" z900 zarch +eb0000000096 lmh RSE_RRRD "load multiple high" z900 zarch +ef lmd SS_RRRDRD3 "load multiple disjoint" z900 zarch +eb000000000f tracg RSE_RRRD "trace 64" z900 zarch +e30000000003 lrag RXE_RRRD "load real address 64" z900 zarch +e50000000002 strag SSE_RDRD "store read address" z900 zarch +eb0000000025 stctg RSE_CCRD "store control 64" z900 zarch +eb000000002f lctlg RSE_CCRD "load control 64" z900 zarch +eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch +eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch +eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch +eb000000002c stcmh RSE_RURD "store characters under mask high" z900 zarch +eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch +a702 tmhh RI_RU "test under mask high high" z900 zarch +a703 tmhl RI_RU "test under mask high low" z900 zarch +c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch +c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch +c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch +c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch +a707 brctg RI_RP "branch relative on count 64" z900 zarch +a709 lghi RI_RI "load halfword immediate 64" z900 zarch +a70b aghi RI_RI "add halfword immediate 64" z900 zarch +a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch +a70f cghi RI_RI "compare halfword immediate 64" z900 zarch +b925 sturg RRE_RR "store using real address 64" z900 zarch +b90e eregg RRE_RR "extract stacked registers 64" z900 zarch +b905 lurag RRE_RR "load using real address 64" z900 zarch +b90c msgr RRE_RR "multiply single 64" z900 zarch +b91c msgfr RRE_RR "multiply single 64<32" z900 zarch +b3a4 cegbr RRE_FR "convert from fixed 64 to short bfp" z900 zarch +b3a5 cdgbr RRE_FR "convert from fixed 64 to long bfp" z900 zarch +b3a6 cxgbr RRE_FR "convert from fixed 64 to extended bfp" z900 zarch +b3a8 cgebr RRF_U0RF "convert to fixed short bfd to 64" z900 zarch +b3a9 cgdbr RRF_U0RF "convert to fixed long bfp to 64" z900 zarch +b3aa cgxbr RRF_U0RF "convert to fixed extended bfp to 64" z900 zarch +b3c4 cegr RRE_FR "convert from fixed 64 to short hfp" z900 zarch +b3c5 cdgr RRE_FR "convert from fixed 64 to long hfp" z900 zarch +b3c6 cxgr RRE_FR "convert from fixed 64 to extended hfp" z900 zarch +b3c8 cger RRF_U0RF "convert to fixed short hfp to 64" z900 zarch +b3c9 cgdr RRF_U0RF "convert to fixed long hfp to 64" z900 zarch +b3ca cgxr RRF_U0RF "convert to fixed extended hfp to 64" z900 zarch +010b tam E "test addressing mode" z900 esa,zarch +010c sam24 E "set addressing mode 24" z900 esa,zarch +010d sam31 E "set addressing mode 31" z900 esa,zarch +010e sam64 E "set addressing mode 64" z900 zarch +a500 iihh RI_RU "insert immediate high high" z900 zarch +a501 iihl RI_RU "insert immediate high low" z900 zarch +a502 iilh RI_RU "insert immediate low high" z900 zarch +a503 iill RI_RU "insert immediate low low" z900 zarch +a504 nihh RI_RU "and immediate high high" z900 zarch +a505 nihl RI_RU "and immediate high low" z900 zarch +a506 nilh RI_RU "and immediate low high" z900 zarch +a507 nill RI_RU "and immediate low low" z900 zarch +a508 oihh RI_RU "or immediate high high" z900 zarch +a509 oihl RI_RU "or immediate high low" z900 zarch +a50a oilh RI_RU "or immediate low high" z900 zarch +a50b oill RI_RU "or immediate low low" z900 zarch +a50c llihh RI_RU "load logical immediate high high" z900 zarch +a50d llihl RI_RU "load logical immediate high low" z900 zarch +a50e llilh RI_RU "load logical immediate low high" z900 zarch +a50f llill RI_RU "load logical immediate low low" z900 zarch +b2b1 stfl S_RD "store facility list" z900 esa,zarch +b2b2 lpswe S_RD "load psw extended" z900 zarch +b90d dsgr RRE_RR "divide single 64" z900 zarch +b90f lrvgr RRE_RR "load reversed 64" z900 zarch +b916 llgfr RRE_RR "load logical 64<32" z900 zarch +b917 llgtr RRE_RR "load logical thirty one bits" z900 zarch +b91d dsgfr RRE_RR "divide single 64<32" z900 zarch +b91f lrvr RRE_RR "load reversed 32" z900 esa,zarch +b986 mlgr RRE_RR "multiply logical 64" z900 zarch +b987 dlgr RRE_RR "divide logical 64" z900 zarch +b988 alcgr RRE_RR "add logical with carry 64" z900 zarch +b989 slbgr RRE_RR "subtract logical with borrow 64" z900 zarch +b98d epsw RRE_RR "extract psw" z900 esa,zarch +b996 mlr RRE_RR "multiply logical 32" z900 esa,zarch +b997 dlr RRE_RR "divide logical 32" z900 esa,zarch +b998 alcr RRE_RR "add logical with carry 32" z900 esa,zarch +b999 slbr RRE_RR "subtract logical with borrow 32" z900 esa,zarch +b99d esea RRE_R0 "extract and set extended authority" z900 zarch +c000 larl RIL_RP "load address relative long" z900 esa,zarch +e3000000000d dsg RXE_RRRD "divide single 64" z900 zarch +e3000000000f lrvg RXE_RRRD "load reversed 64" z900 zarch +e30000000016 llgf RXE_RRRD "load logical 64<32" z900 zarch +e30000000017 llgt RXE_RRRD "load logical thirty one bits" z900 zarch +e3000000001d dsgf RXE_RRRD "divide single 64<32" z900 zarch +e3000000001e lrv RXE_RRRD "load reversed 32" z900 esa,zarch +e3000000001f lrvh RXE_RRRD "load reversed 16" z900 esa,zarch +e3000000002f strvg RXE_RRRD "store reversed 64" z900 zarch +e3000000003e strv RXE_RRRD "store reversed 32" z900 esa,zarch +e3000000003f strvh RXE_RRRD "store reversed 64" z900 esa,zarch +e30000000086 mlg RXE_RRRD "multiply logical 64" z900 zarch +e30000000087 dlg RXE_RRRD "divide logical 64" z900 zarch +e30000000088 alcg RXE_RRRD "add logical with carry 64" z900 zarch +e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" z900 zarch +e3000000008e stpq RXE_RRRD "store pair to quadword" z900 zarch +e3000000008f lpq RXE_RRRD "load pair from quadword" z900 zarch +e30000000096 ml RXE_RRRD "multiply logical 32" z900 esa,zarch +e30000000097 dl RXE_RRRD "divide logical 32" z900 esa,zarch +e30000000098 alc RXE_RRRD "add logical with carry 32" z900 esa,zarch +e30000000099 slb RXE_RRRD "subtract logical with borrow 32" z900 esa,zarch +e30000000090 llgc RXE_RRRD "load logical character" z900 zarch +e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch +eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch +eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch +b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch +b3b6 cxfr RRE_FR "convert from fixed 32 to extended hfp" g5 esa,zarch +b3b5 cdfr RRE_FR "convert from fixed 32 to long hfp" g5 esa,zarch +b3b4 cefr RRE_FR "convert from fixed 32 to short hfp" g5 esa,zarch +b3ba cfxr RRF_U0RF "convert to fixed extended hfp to 32" g5 esa,zarch +b3b9 cfdr RRF_U0RF "convert to fixed long hfp to 32" g5 esa,zarch +b3b8 cfer RRF_U0RF "convert to fixed short hfp to 32" g5 esa,zarch +b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch +b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch +b367 fixr RRE_FF "load fp integer extended hfp" g5 esa,zarch +b37f fidr RRE_FF "load fp integer long hfp" g5 esa,zarch +b377 fier RRE_FF "load fp integer short hfp" g5 esa,zarch +b325 lxdr RRE_FF "load lengthened long to extended hfp" g5 esa,zarch +ed0000000025 lxd RXE_FRRD "load lengthened long to extended hfp" g5 esa,zarch +b326 lxer RRE_FF "load lengthened short to extended hfp" g5 esa,zarch +ed0000000026 lxe RXE_FRRD "load lengthened short to extended hfp" g5 esa,zarch +b324 lder RRE_FF "load lengthened short to long hfp" g5 esa,zarch +ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch +b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch +b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch +b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch +b337 meer RRE_FF "multiply short hfp" g5 esa,zarch +ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch +b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch +ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch +ed0000000035 sqd RXE_FRRD "square root long hfp" g5 esa,zarch +b263 cmpsc RRE_RR "compression call" g5 esa,zarch +eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch +b365 lxr RRE_FF "load extended fp" g5 esa,zarch +b22e pgin RRE_RR "page in" g5 esa,zarch +b22f pgout RRE_RR "page out" g5 esa,zarch +b276 xsch S_00 "cancel subchannel" g5 esa,zarch +# New long displacement instructions on z990 +e3000000005a ay RXY_RRRD "add with long offset" z990 zarch +e3000000007a ahy RXY_RRRD "add halfword with long offset" z990 zarch +e3000000005e aly RXY_RRRD "add logical with long offset" z990 zarch +eb0000000054 niy SIY_URD "and immediate with long offset" z990 zarch +e30000000054 ny RXY_RRRD "and with long offset" z990 zarch +e30000000059 cy RXY_RRRD "compare with long offset" z990 zarch +eb0000000014 csy RSY_RRRD "compare and swap with long offset" z990 zarch +eb0000000031 cdsy RSY_RRRD "compare double and swap with long offset" z990 zarch +e30000000079 chy RXY_RRRD "compare halfword with long offset" z990 zarch +e30000000055 cly RXY_RRRD "compare logical with long offset" z990 zarch +eb0000000055 cliy SIY_URD "compare logical immediate with long offset" z990 zarch +eb0000000021 clmy RSY_RURD "compare logical characters under mask with long offset" z990 zarch +e30000000006 cvby RXY_RRRD "convert to binary with long offset" z990 zarch +e30000000026 cvdy RXY_RRRD "convert to decimal with long offset" z990 zarch +eb0000000057 xiy SIY_URD "exclusive or immediate with long offset" z990 zarch +e30000000057 xy RXY_RRRD "exclusive or with long offset" z990 zarch +e30000000073 icy RXY_RRRD "insert character with long offset" z990 zarch +eb0000000081 icmy RSY_RURD "insert characters with long offset" z990 zarch +ed0000000065 ldy RXY_FRRD "load (long) with long offset" z990 zarch +ed0000000064 ley RXY_FRRD "load (short) with long offset" z990 zarch +e30000000058 ly RXY_RRRD "load with long offset" z990 zarch +eb000000009a lamy RSY_AARD "load access multiple" z990 zarch +e30000000071 lay RXY_RRRD "load address with long offset" z990 zarch +e30000000076 lb RXY_RRRD "load byte with long offset" z990 zarch +e30000000077 lgb RXY_RRRD "load byte with long offset 64" z990 zarch +e30000000078 lhy RXY_RRRD "load halfword with long offset" z990 zarch +eb0000000098 lmy RSY_RRRD "load multiple with long offset" z990 zarch +e30000000013 lray RXY_RRRD "load real address with long offset" z990 zarch +eb0000000052 mviy SIY_URD "move immediate with long offset" z990 zarch +e30000000051 msy RXY_RRRD "multiply single with long offset" z990 zarch +eb0000000056 oiy SIY_URD "or immediate with long offset" z990 zarch +e30000000056 oy RXY_RRRD "or with long offset" z990 zarch +ed0000000067 stdy RXY_FRRD "store (long) with long offset" z990 zarch +ed0000000066 stey RXY_FRRD "store (short) with long offset" z990 zarch +e30000000050 sty RXY_RRRD "store with long offset" z990 zarch +eb000000009b stamy RSY_AARD "store access multiple with long offset" z990 zarch +e30000000072 stcy RXY_RRRD "store character with long offset" z990 zarch +eb000000002d stcmy RSY_RURD "store characters under mask with long offset" z990 zarch +e30000000070 sthy RXY_RRRD "store halfword with long offset" z990 zarch +eb0000000090 stmy RSY_RRRD "store multiple with long offset" z990 zarch +e3000000005b sy RXY_RRRD "subtract with long offset" z990 zarch +e3000000007b shy RXY_RRRD "subtract halfword with long offset" z990 zarch +e3000000005f sly RXY_RRRD "subtract logical with long offset" z990 zarch +eb0000000051 tmy SIY_URD "test under mask with long offset" z990 zarch +# 'old' instructions extended to long displacement +# these instructions are entered into the opcode table twice. +e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch +e30000000004 lg RXY_RRRD " load 64" z990 zarch +e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch +e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch +e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch +e3000000000b slg RXY_RRRD "subtract logical with long offset 64" z990 zarch +e3000000000c msg RXY_RRRD "multiply single with long offset 64" z990 zarch +e3000000000d dsg RXY_RRRD "divide single 64" z990 zarch +e3000000000e cvbg RXY_RRRD "convert to binary with long offset 64" z990 zarch +e3000000000f lrvg RXY_RRRD "load reversed 64" z990 zarch +e30000000014 lgf RXY_RRRD "load 64<32" z990 zarch +e30000000015 lgh RXY_RRRD "load halfword 64" z990 zarch +e30000000016 llgf RXY_RRRD "load logical 64<32" z990 zarch +e30000000017 llgt RXY_RRRD "load logical thirty one bits" z990 zarch +e30000000018 agf RXY_RRRD "add with long offset 64<32" z990 zarch +e30000000019 sgf RXY_RRRD "subtract with long offset 64<32" z990 zarch +e3000000001a algf RXY_RRRD "add logical with long offset 64<32" z990 zarch +e3000000001b slgf RXY_RRRD "subtract logical with long offset 64<32" z990 zarch +e3000000001c msgf RXY_RRRD "multiply single with long offset 64<32" z990 zarch +e3000000001d dsgf RXY_RRRD "divide single 64<32" z990 zarch +e3000000001e lrv RXY_RRRD "load reversed 32" z990 esa,zarch +e3000000001f lrvh RXY_RRRD "load reversed 16" z990 esa,zarch +e30000000020 cg RXY_RRRD "compare with long offset 64" z990 zarch +e30000000021 clg RXY_RRRD "compare logical with long offset 64" z990 zarch +e30000000024 stg RXY_RRRD "store with long offset 64" z990 zarch +e3000000002e cvdg RXY_RRRD "convert to decimal with long offset 64" z990 zarch +e3000000002f strvg RXY_RRRD "store reversed 64" z990 zarch +e30000000030 cgf RXY_RRRD "compare with long offset 64<32" z990 zarch +e30000000031 clgf RXY_RRRD "compare logical with long offset 64<32" z990 zarch +e3000000003e strv RXY_RRRD "store reversed 32" z990 esa,zarch +e3000000003f strvh RXY_RRRD "store reversed 64" z990 zarch +e30000000046 bctg RXY_RRRD "branch on count 64" z990 zarch +e30000000080 ng RXY_RRRD "and with long offset 64" z990 zarch +e30000000081 og RXY_RRRD "or with long offset 64" z990 zarch +e30000000082 xg RXY_RRRD "exclusive or with long offset 64" z990 zarch +e30000000086 mlg RXY_RRRD "multiply logical 64" z990 zarch +e30000000087 dlg RXY_RRRD "divide logical 64" z990 zarch +e30000000088 alcg RXY_RRRD "add logical with carry 64" z990 zarch +e30000000089 slbg RXY_RRRD "subtract logical with borrow 64" z990 zarch +e3000000008e stpq RXY_RRRD "store pair to quadword" z990 zarch +e3000000008f lpq RXY_RRRD "load pair from quadword" z990 zarch +e30000000090 llgc RXY_RRRD "load logical character" z990 zarch +e30000000091 llgh RXY_RRRD "load logical halfword" z990 zarch +e30000000096 ml RXY_RRRD "multiply logical 32" z990 esa,zarch +e30000000097 dl RXY_RRRD "divide logical 32" z990 esa,zarch +e30000000098 alc RXY_RRRD "add logical with carry 32" z990 esa,zarch +e30000000099 slb RXY_RRRD "subtract logical with borrow 32" z990 esa,zarch +eb0000000004 lmg RSY_RRRD "load multiple with long offset 64" z990 zarch +eb000000000a srag RSY_RRRD "shift right single 64" z990 zarch +eb000000000b slag RSY_RRRD "shift left single 64" z990 zarch +eb000000000c srlg RSY_RRRD "shift right single logical 64" z990 zarch +eb000000000d sllg RSY_RRRD "shift left single logical 64" z990 zarch +eb000000000f tracg RSY_RRRD "trace 64" z990 zarch +eb000000001c rllg RSY_RRRD "rotate left single logical 64" z990 zarch +eb000000001d rll RSY_RRRD "rotate left single logical 32" z990 esa,zarch +eb0000000020 clmh RSY_RURD "compare logical characters under mask high with long offset" z990 zarch +eb0000000024 stmg RSY_RRRD "store multiple with long offset 64" z990 zarch +eb0000000025 stctg RSY_CCRD "store control 64" z990 zarch +eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch +eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch +eb000000002f lctlg RSY_CCRD "load control 64" z990 zarch +eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch +eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch +eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch +eb0000000045 bxleg RSY_RRRD "branch on index low or equal 64" z990 zarch +eb0000000080 icmh RSY_RURD "insert characters under mask high with long offset" z990 zarch +eb000000008e mvclu RSY_RRRD "move long unicode" z990 esa,zarch +eb000000008f clclu RSY_RRRD "compare logical long unicode with long offset" z990 esa,zarch +eb0000000096 lmh RSY_RRRD "load multiple high" z990 zarch +# new z990 instructions +b98a cspg RRE_RR "compare and swap and purge" z990 zarch +b98e idte RRF_R0RR "invalidate dat table entry" z990 zarch +b33e madr RRF_F0FF "multiply and add long hfp" z990 esa,zarch +ed000000003e mad RXF_FRRDF "multiply and add long hfp" z990 esa,zarch +b32e maer RRF_F0FF "multiply and add short hfp" z990 esa,zarch +ed000000002e mae RXF_FRRDF "multiply and add short hfp" z990 esa,zarch +b33f msdr RRF_F0FF "multiply and subtract long hfp" z990 esa,zarch +ed000000003f msd RXF_FRRDF "multiply and subtract long hfp" z990 esa,zarch +b32f mser RRF_F0FF "mutliply and subtract short hfp" z990 esa,zarch +ed000000002f mse RXF_FRRDF "multiply and subttract short hfp" z990 esa,zarch +b92e km RRE_RR "cipher message" z990 esa,zarch +b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch +b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch +b93f klmd RRE_RR "compute last message digest" z990 esa,zarch +b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch +# z9-109 extended immediate instructions +c209 afi RIL_RI "add immediate 32" z9-109 zarch +c208 agfi RIL_RI "add immediate 64<32" z9-109 zarch +c20b alfi RIL_RU "add logical immediate 32" z9-109 zarch +c20a algfi RIL_RU "add logical immediate 64<32" z9-109 zarch +c00a nihf RIL_RU "and immediate high" z9-109 zarch +c00b nilf RIL_RU "and immediate low" z9-109 zarch +c20d cfi RIL_RI "compare immediate 32" z9-109 zarch +c20c cgfi RIL_RI "compare immediate 64<32" z9-109 zarch +c20f clfi RIL_RU "compare logical immediate 32" z9-109 zarch +c20e clgfi RIL_RU "compare logical immediate 64<32" z9-109 zarch +c006 xihf RIL_RU "exclusive or immediate high" z9-109 zarch +c007 xilf RIL_RU "exclusive or immediate low" z9-109 zarch +c008 iihf RIL_RU "insert immediate high" z9-109 zarch +c009 iilf RIL_RU "insert immediate low" z9-109 zarch +# z9-109 misc instruction +b983 flogr RRE_RR "find leftmost one" z9-109 zarch +e30000000012 lt RXY_RRRD "load and test 32" z9-109 zarch +e30000000002 ltg RXY_RRRD "load and test 64" z9-109 zarch +b926 lbr RRE_RR "load byte 32" z9-109 zarch +b906 lgbr RRE_RR "load byte 64" z9-109 zarch +b927 lhr RRE_RR "load halfword 32" z9-109 zarch +b907 lghr RRE_RR "load halfword 64" z9-109 zarch +c001 lgfi RIL_RI "load immediate 64<32" z9-109 zarch +e30000000094 llc RXY_RRRD "load logical character 32" z9-109 zarch +b994 llcr RRE_RR "load logical character 32" z9-109 zarch +b984 llgcr RRE_RR "load logical character 64" z9-109 zarch +e30000000095 llh RXY_RRRD "load logical halfword 32" z9-109 zarch +b995 llhr RRE_RR "load logical halfword 32" z9-109 zarch +b985 llghr RRE_RR "load logical halfword 64" z9-109 zarch +c00e llihf RIL_RU "load logical immediate high" z9-109 zarch +c00f llilf RIL_RU "load logical immediate low" z9-109 zarch +c00c oihf RIL_RU "or immediate high" z9-109 zarch +c00d oilf RIL_RU "or immediate low" z9-109 zarch +c205 slfi RIL_RU "subtract logical immediate 32" z9-109 zarch +c204 slgfi RIL_RU "subtract logical immediate 64<32" z9-109 zarch +0104 ptff E "perform timing facility function" z9-109 zarch +# z9-109 store facility list extended +b2b0 stfle S_RD "store facility list extended" z9-109 zarch +# z9-109 store clock fast +b27c stckf S_RD "store clock fast" z9-109 zarch +# z9-109 move with optional specifications instruction +c800 mvcos SSF_RRDRD "move with optional specifications" z9-109 zarch +# z9-109 load page-table-entry address instruction +b9aa lptea RRF_RURR "load page-table-entry address" z9-109 zarch +# z9-109 conditional sske facility, sske instruction entered twice +b22b sske RRF_M0RR "set storage key extended" z9-109 zarch +# z9-109 etf2-enhancement facility, instructions entered twice +b993 troo RRF_M0RR "translate one to one" z9-109 esa,zarch +b992 trot RRF_M0RR "translate one to two" z9-109 esa,zarch +b991 trto RRF_M0RR "translate two to one" z9-109 esa,zarch +b990 trtt RRF_M0RR "translate two to two" z9-109 esa,zarch +# z9-109 etf3-enhancement facility, some instructions entered twice +b9b1 cu24 RRF_M0RR "convert utf-16 to utf-32" z9-109 zarch +b2a6 cu21 RRF_M0RR "convert utf-16 to utf-8" z9-109 zarch +b2a6 cuutf RRF_M0RR "convert unicode to utf-8" z9-109 zarch +b9b3 cu42 RRE_RR "convert utf-32 to utf-16" z9-109 zarch +b9b2 cu41 RRE_RR "convert utf-32 to utf-8" z9-109 zarch +b2a7 cu12 RRF_M0RR "convert utf-8 to utf-16" z9-109 zarch +b2a7 cutfu RRF_M0RR "convert utf-8 to unicode" z9-109 zarch +b9b0 cu14 RRF_M0RR "convert utf-8 to utf-32" z9-109 zarch +b9eb srstu RRE_RR "search string unicode" z9-109 zarch +d0 trtr SS_L0RDRD "tranlate and test reverse" z9-109 zarch +# z9-109 unnormalized hfp multiply & multiply and add +b33b myr RRF_F0FF "multiply unnormalized long hfp" z9-109 zarch +b33d myhr RRF_F0FF "multiply unnormalized long hfp high" z9-109 zarch +b339 mylr RRF_F0FF "multiply unnormalized long hfp low" z9-109 zarch +ed000000003b my RXF_FRRDF "multiply unnormalized long hfp" z9-109 zarch +ed000000003d myh RXF_FRRDF "multiply unnormalized long hfp high" z9-109 zarch +ed0000000039 myl RXF_FRRDF "multiply unnormalized long hfp low" z9-109 zarch +b33a mayr RRF_F0FF "multiply and add unnormalized long hfp" z9-109 zarch +b33c mayhr RRF_F0FF "multiply and add unnormalized long hfp high" z9-109 zarch +b338 maylr RRF_F0FF "multiply and add unnormalized long hfp low" z9-109 zarch +ed000000003a may RXF_FRRDF "multiply and add unnormalized long hfp" z9-109 zarch +ed000000003c mayh RXF_FRRDF "multiply and add unnormalized long hfp high" z9-109 zarch +ed0000000038 mayl RXF_FRRDF "multiply and add unnormalized long hfp low" z9-109 zarch +b370 lpdfr RRE_FF "load positive no cc" z9-ec zarch +b371 lndfr RRE_FF "load negative no cc" z9-ec zarch +b372 cpsdr RRF_F0FF2 "copy sign" z9-ec zarch +b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch +b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch +b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch +b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch +b3da axtr RRR_F0FF "add extended dfp" z9-ec zarch +b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch +b3ec cxtr RRE_FF "compare extended dfp" z9-ec zarch +b3e0 kdtr RRE_FF "compare and signal long dfp" z9-ec zarch +b3e8 kxtr RRE_FF "compare and signal extended dfp" z9-ec zarch +b3f4 cedtr RRE_FF "compare exponent long dfp" z9-ec zarch +b3fc cextr RRE_FF "compare exponent extended dfp" z9-ec zarch +b3f1 cdgtr RRE_FR "convert from fixed long dfp" z9-ec zarch +b3f9 cxgtr RRE_FR "convert from fixed extended dfp" z9-ec zarch +b3f3 cdstr RRE_FR "convert from signed bcd long dfp" z9-ec zarch +b3fb cxstr RRE_FR "convert from signed bcd extended dfp" z9-ec zarch +b3f2 cdutr RRE_FR "convert from unsigned bcd to long dfp" z9-ec zarch +b3fa cxutr RRE_FR "convert from unsigned bcd to extended dfp" z9-ec zarch +b3e1 cgdtr RRF_U0RF "convert from long dfp to fixed" z9-ec zarch +b3e9 cgxtr RRF_U0RF "convert from extended dfp to fixed" z9-ec zarch +b3e3 csdtr RRE_RF "convert from long dfp to signed bcd" z9-ec zarch +b3eb csxtr RRE_RF "convert from extended dfp to signed bcd" z9-ec zarch +b3e2 cudtr RRE_RF "convert from long dfp to unsigned bcd" z9-ec zarch +b3ea cuxtr RRE_RF "convert from extended dfp to unsigned bcd" z9-ec zarch +b3d1 ddtr RRR_F0FF "divide long dfp" z9-ec zarch +b3d9 dxtr RRR_F0FF "divide extended dfp" z9-ec zarch +b3e5 eedtr RRE_RF "extract biased exponent from long dfp" z9-ec zarch +b3ed eextr RRE_RF "extract biased exponent from extended dfp" z9-ec zarch +b3e7 esdtr RRE_RF "extract significance from long dfp" z9-ec zarch +b3ef esxtr RRE_RF "extract significance from extended dfp" z9-ec zarch +b3f6 iedtr RRF_F0FR "insert biased exponent long dfp" z9-ec zarch +b3fe iextr RRF_F0FR "insert biased exponent extended dfp" z9-ec zarch +b3d6 ltdtr RRE_FF "load and test long dfp" z9-ec zarch +b3de ltxtr RRE_FF "load and test extended dfp" z9-ec zarch +b3d7 fidtr RRF_UUFF "load fp integer long dfp" z9-ec zarch +b3df fixtr RRF_UUFF "load fp integer extended dfp" z9-ec zarch +b2bd lfas S_RD "load fpd and signal" z9-ec zarch +b3d4 ldetr RRF_0UFF "load lengthened long dfp" z9-ec zarch +b3dc lxdtr RRF_0UFF "load lengthened extended dfp" z9-ec zarch +b3d5 ledtr RRF_UUFF "load rounded long dfp" z9-ec zarch +b3dd ldxtr RRF_UUFF "load rounded extended dfp" z9-ec zarch +b3d0 mdtr RRR_F0FF "multiply long dfp" z9-ec zarch +b3d8 mxtr RRR_F0FF "multiply extended dfp" z9-ec zarch +b3f5 qadtr RRF_FUFF "Quantize long dfp" z9-ec zarch +b3fd qaxtr RRF_FUFF "Quantize extended dfp" z9-ec zarch +b3f7 rrdtr RRF_FFRU "Reround long dfp" z9-ec zarch +b3ff rrxtr RRF_FFRU "Reround extended dfp" z9-ec zarch +b2b9 srnmt S_RD "set rounding mode dfp" z9-ec zarch +b385 sfasr RRE_R0 "set fpc and signal" z9-ec zarch +ed0000000040 sldt RXF_FRRDF "shift coefficient left long dfp" z9-ec zarch +ed0000000048 slxt RXF_FRRDF "shift coefficient left extended dfp" z9-ec zarch +ed0000000041 srdt RXF_FRRDF "shift coefficient right long dfp" z9-ec zarch +ed0000000049 srxt RXF_FRRDF "shift coefficient right extended dfp" z9-ec zarch +b3d3 sdtr RRR_F0FF "subtract long dfp" z9-ec zarch +b3db sxtr RRR_F0FF "subtract extended dfp" z9-ec zarch +ed0000000050 tdcet RXE_FRRD "test data class short dfp" z9-ec zarch +ed0000000054 tdcdt RXE_FRRD "test data class long dfp" z9-ec zarch +ed0000000058 tdcxt RXE_FRRD "test data class extended dfp" z9-ec zarch +ed0000000051 tdget RXE_FRRD "test data group short dfp" z9-ec zarch +ed0000000055 tdgdt RXE_FRRD "test data group long dfp" z9-ec zarch +ed0000000059 tdgxt RXE_FRRD "test data group extended dfp" z9-ec zarch +010a pfpo E "perform floating point operation" z9-ec zarch +c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch +c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch +# The new instructions of the System z10 Enterprise Class +eb000000006a asi SIY_IRD "add immediate (32<8)" z10 zarch +eb000000007a agsi SIY_IRD "add immediate (64<8)" z10 zarch +eb000000006e alsi SIY_IRD "add logical with signed immediate (32<8)" z10 zarch +eb000000007e algsi SIY_IRD "add logical with signed immediate (64<8)" z10 zarch +c60d crl RIL_RP "compare relative long (32)" z10 zarch +c608 cgrl RIL_RP "compare relative long (64)" z10 zarch +c60c cgfrl RIL_RP "compare relative long (64<32)" z10 zarch +ec00000000f6 crb$32 RRS_RRRD0 "compare and branch (32)" z10 zarch +ec00000000f6 crb RRS_RRRDU "compare and branch (32)" z10 zarch +ec00000000e4 cgrb$32 RRS_RRRD0 "compare and branch (64)" z10 zarch +ec00000000e4 cgrb RRS_RRRDU "compare and branch (64)" z10 zarch +ec0000000076 crj$32 RIE_RRP "compare and branch relative (32)" z10 zarch +ec0000000076 crj RIE_RRPU "compare and branch relative (32)" z10 zarch +ec0000000064 cgrj$32 RIE_RRP0 "compare and branch relative (64)" z10 zarch +ec0000000064 cgrj RIE_RRPU "compare and branch relative (64)" z10 zarch +ec00000000fe cib$12 RIS_R0RDI "compare immediate and branch (32<8)" z10 zarch +ec00000000fe cib RIS_RURDI "compare immediate and branch (32<8)" z10 zarch +ec00000000fc cgib$12 RIS_R0RDI "compare immediate and branch (64<8)" z10 zarch +ec00000000fc cgib RIS_RURDI "compare immediate and branch (64<8)" z10 zarch +ec000000007e cij$12 RIE_R0PI "compare immediate and branch relative (32<8)" z10 zarch +ec000000007e cij RIE_RUPI "compare immediate and branch relative (32<8)" z10 zarch +ec000000007c cgij$12 RIE_R0PI "compare immediate and branch relative (64<8)" z10 zarch +ec000000007c cgij RIE_RUPI "compare immediate and branch relative (64<8)" z10 zarch +b97200000000 crt$16 RRF_00RR "compare and trap" z10 zarch +b972 crt RRF_U0RR "compare and trap" z10 zarch +b96000000000 cgrt$16 RRF_00RR "compare and trap 64" z10 zarch +b960 cgrt RRF_U0RR "compare and trap 64" z10 zarch +ec0000000072 cit$32 RIE_R0I0 "compare immediate and trap (32<16)" z10 zarch +ec0000000072 cit RIE_R0IU "compare immediate and trap (32<16)" z10 zarch +ec0000000070 cgit$32 RIE_R0I0 "compare immediate and trap (64<16)" z10 zarch +ec0000000070 cgit RIE_R0IU "compare immediate and trap (64<16)" z10 zarch +e30000000034 cgh RXY_RRRD "compare halfword (64<16)" z10 zarch +e554 chhsi SIL_RDI "compare halfword immediate (16<16)" z10 zarch +e55c chsi SIL_RDI "compare halfword immediate (32<16)" z10 zarch +e558 cghsi SIL_RDI "compare halfword immediate (64<16)" z10 zarch +c605 chrl RIL_RP "compare halfword relative long (32<8)" z10 zarch +c604 cghrl RIL_RP "compare halfword relative long (64<8)" z10 zarch +e555 clhhsi SIL_RDU "compare logical immediate (16<16)" z10 zarch +e55d clfhsi SIL_RDU "compare logical immediate (32<16)" z10 zarch +e559 clghsi SIL_RDU "compare logical immediate (64<16)" z10 zarch +c60f clrl RIL_RP "compare logical relative long (32)" z10 zarch +c60a clgrl RIL_RP "compare logical relative long (64)" z10 zarch +c60e clgfrl RIL_RP "compare logical relative long (64<32)" z10 zarch +c607 clhrl RIL_RP "compare logical relative long (32<16)" z10 zarch +c606 clghrl RIL_RP "compare logical relative long (64<16)" z10 zarch +ec00000000f7 clrb$32 RRS_RRRD0 "compare logical and branch (32)" z10 zarch +ec00000000f7 clrb RRS_RRRDU "compare logical and branch (32)" z10 zarch +ec00000000e5 clgrb$32 RRS_RRRD0 "compare logical and branch (64)" z10 zarch +ec00000000e5 clgrb RRS_RRRDU "compare logical and branch (64)" z10 zarch +ec0000000077 clrj$32 RIE_RRP "compare logical and branch relative (32)" z10 zarch +ec0000000077 clrj RIE_RRPU "compare logical and branch relative (32)" z10 zarch +ec0000000065 clgrj$32 RIE_RRP "compare logical and branch relative (64)" z10 zarch +ec0000000065 clgrj RIE_RRPU "compare logical and branch relative (64)" z10 zarch +ec00000000ff clib$12 RIS_R0RDU "compare logical immediate and branch (32<8)" z10 zarch +ec00000000ff clib RIS_RURDU "compare logical immediate and branch (32<8)" z10 zarch +ec00000000fd clgib$12 RIS_R0RDU "compare logical immediate and branch (64<8)" z10 zarch +ec00000000fd clgib RIS_RURDU "compare logical immediate and branch (64<8)" z10 zarch +ec000000007f clij$12 RIE_R0PU "compare logical immediate and branch relative (32<8)" z10 zarch +ec000000007f clij RIE_RUPU "compare logical immediate and branch relative (32<8)" z10 zarch +ec000000007d clgij$12 RIE_R0PU "compare logical immediate and branch relative (64<8)" z10 zarch +ec000000007d clgij RIE_RUPU "compare logical immediate and branch relative (64<8)" z10 zarch +b97300000000 clrt$16 RRF_00RR "compare logical and trap (32)" z10 zarch +b973 clrt RRF_U0RR "compare logical and trap (32)" z10 zarch +b96100000000 clgrt$16 RRF_00RR "compare logical and trap (64)" z10 zarch +b961 clgrt RRF_U0RR "compare logical and trap (64)" z10 zarch +ec0000000073 clfit$32 RIE_R0U0 "compare logical and trap (32<16)" z10 zarch +ec0000000073 clfit RIE_R0UU "compare logical and trap (32<16)" z10 zarch +ec0000000071 clgit$32 RIE_R0U0 "compare logical and trap (64<16)" z10 zarch +ec0000000071 clgit RIE_R0UU "compare logical and trap (64<16)" z10 zarch +eb000000004c ecag RSY_RRRD "extract cache attribute" z10 zarch +c40d lrl RIL_RP "load relative long (32)" z10 zarch +c408 lgrl RIL_RP "load relative long (64)" z10 zarch +c40c lgfrl RIL_RP "load relative long (64<32)" z10 zarch +e30000000075 laey RXY_RRRD "load address extended" z10 zarch +e30000000032 ltgf RXY_RRRD "load and test (64<32)" z10 zarch +c405 lhrl RIL_RP "load halfword relative long (32<16)" z10 zarch +c404 lghrl RIL_RP "load halfword relative long (64<16)" z10 zarch +c40e llgfrl RIL_RP "load logical relative long (64<32)" z10 zarch +c402 llhrl RIL_RP "load logical halfword relative long (32<16)" z10 zarch +c406 llghrl RIL_RP "load logical halfword relative long (64<16)" z10 zarch +e544 mvhhi SIL_RDI "move (16<16)" z10 zarch +e54c mvhi SIL_RDI "move (32<16)" z10 zarch +e548 mvghi SIL_RDI "move (64<16)" z10 zarch +e3000000005c mfy RXY_RRRD "multiply" z10 zarch +e3000000007c mhy RXY_RRRD "multiply halfword" z10 zarch +c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch +c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch +e30000000036 pfd RXY_URRD "prefetch data" z10 zarch +c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch +ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch +ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch +ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch +ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch +c40f strl RIL_RP "store relative long (32)" z10 zarch +c40b stgrl RIL_RP "store relative long (64)" z10 zarch +c407 sthrl RIL_RP "store halfword relative long" z10 zarch +c600 exrl RIL_RP "execute relative long" z10 zarch +af00 mc SI_URD "monitor call" z10 zarch +b9a2 ptf RRE_R0 "perform topology function" z10 zarch +b9af pfmf RRE_RR "perform frame management function" z10 zarch +b9bf trte RRF_M0RR "translate and test extended" z10 zarch +b9bd trtre RRF_M0RR "translate and test reverse extended" z10 zarch +b9c8 ahhhr RRF_R0RR2 "add high high" z196 zarch +b9d8 ahhlr RRF_R0RR2 "add high low" z196 zarch +cc08 aih RIL_RI "add immediate high" z196 zarch +b9ca alhhhr RRF_R0RR2 "add logical high high" z196 zarch +b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch +cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch +cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch +cc06 brcth RIL_RP "branch relative on count high" z196 zarch +b9cd chhr RRE_RR "compare high high" z196 zarch +b9dd chlr RRE_RR "compare high low" z196 zarch +e300000000cd chf RXY_RRRD "compare high" z196 zarch +cc0d cih RIL_RI "compare immediate high" z196 zarch +b9cf clhhr RRE_RR "compare logical high high" z196 zarch +b9df clhlr RRE_RR "compare logical high low" z196 zarch +e300000000cf clhf RXY_RRRD "compare logical high" z196 zarch +cc0f clih RIL_RI "compare logical immediate" z196 zarch +e300000000c0 lbh RXY_RRRD "load byte high" z196 zarch +e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch +e300000000ca lfh RXY_RRRD "load high" z196 zarch +e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch +e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch +ec000000005D risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch +ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch +e300000000c3 stch RXY_RRRD "store character high" z196 zarch +e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch +e300000000cb stfh RXY_RRRD "store high" z196 zarch +b9c9 shhhr RRF_R0RR2 "subtract high high" z196 zarch +b9d9 shhlr RRF_R0RR2 "subtract high low" z196 zarch +b9cb slhhhr RRF_R0RR2 "subtract logical high high" z196 zarch +b9db slhhlr RRF_R0RR2 "subtract logical high low" z196 zarch +eb00000000f8 laa RSY_RRRD "load and add 32 bit" z196 zarch +eb00000000e8 laag RSY_RRRD "load and add 64 bit" z196 zarch +eb00000000fa laal RSY_RRRD "load and add logical 32 bit" z196 zarch +eb00000000ea laalg RSY_RRRD "load and add logical 64 bit" z196 zarch +eb00000000f4 lan RSY_RRRD "load and and 32 bit" z196 zarch +eb00000000e4 lang RSY_RRRD "load and and 64 bit" z196 zarch +eb00000000f7 lax RSY_RRRD "load and exclusive or 32 bit" z196 zarch +eb00000000e7 laxg RSY_RRRD "load and exclusive or 64 bit" z196 zarch +eb00000000f6 lao RSY_RRRD "load and or 32 bit" z196 zarch +eb00000000e6 laog RSY_RRRD "load and or 64 bit" z196 zarch +c804 lpd SSF_RRDRD2 "load pair disjoint 32 bit" z196 zarch +c805 lpdg SSF_RRDRD2 "load pair disjoint 64 bit" z196 zarch +b9f2 locr RRF_U0RR "load on condition 32 bit" z196 zarch +b9f200000000 locr*16 RRF_00RR "load on condition 32 bit" z196 zarch +b9e2 locgr RRF_U0RR "load on condition 64 bit" z196 zarch +b9e200000000 locgr*16 RRF_00RR "load on condition 64 bit" z196 zarch +eb00000000f2 loc RSY_RDRM "load on condition 32 bit" z196 zarch +eb00000000f2 loc*12 RSY_RDR0 "load on condition 32 bit" z196 zarch +eb00000000e2 locg RSY_RDRM "load on condition 64 bit" z196 zarch +eb00000000e2 locg*12 RSY_RDR0 "load on condition 64 bit" z196 zarch +eb00000000f3 stoc RSY_RDRM "store on condition 32 bit" z196 zarch +eb00000000f3 stoc*12 RSY_RDR0 "store on condition 32 bit" z196 zarch +eb00000000e3 stocg RSY_RDRM "store on condition 64 bit" z196 zarch +eb00000000e3 stocg*12 RSY_RDR0 "store on condition 64 bit" z196 zarch +b9f8 ark RRF_R0RR2 "add 3 operands 32 bit" z196 zarch +b9e8 agrk RRF_R0RR2 "add 3 operands 64 bit" z196 zarch +ec00000000d8 ahik RIE_RRI0 "add immediate 3 operands 32 bit" z196 zarch +ec00000000d9 aghik RIE_RRI0 "add immediate 3 operands 64 bit" z196 zarch +b9fa alrk RRF_R0RR2 "add logical 3 operands 32 bit" z196 zarch +b9ea algrk RRF_R0RR2 "add logical 3 operands 64 bit" z196 zarch +ec00000000da alhsik RIE_RRI0 "add logical immediate 3 operands 32 bit" z196 zarch +ec00000000db alghsik RIE_RRI0 "add logical immediate 3 operands 64 bit" z196 zarch +b9f4 nrk RRF_R0RR2 "and 3 operands 32 bit" z196 zarch +b9e4 ngrk RRF_R0RR2 "and 3 operands 64 bit" z196 zarch +b9f7 xrk RRF_R0RR2 "xor 3 operands 32 bit" z196 zarch +b9e7 xgrk RRF_R0RR2 "xor 3 operands 64 bit" z196 zarch +b9f6 ork RRF_R0RR2 "or 3 operands 32 bit" z196 zarch +b9e6 ogrk RRF_R0RR2 "or 3 operands 64 bit" z196 zarch +eb00000000dd slak RSY_RRRD "shift left single 3 operands 32 bit" z196 zarch +eb00000000df sllk RSY_RRRD "shift left single logical 3 operands 32 bit" z196 zarch +eb00000000dc srak RSY_RRRD "shift right single 3 operands 32 bit" z196 zarch +eb00000000de srlk RSY_RRRD "shift right single logical 3 operands 32 bit" z196 zarch +b9f9 srk RRF_R0RR2 "subtract 3 operands 32 bit" z196 zarch +b9e9 sgrk RRF_R0RR2 "subtract 3 operands 64 bit" z196 zarch +b9fb slrk RRF_R0RR2 "subtract logical 3 operands 32 bit" z196 zarch +b9eb slgrk RRF_R0RR2 "subtract logical 3 operands 64 bit" z196 zarch +b9e1 popcnt RRE_RR "population count" z196 zarch +b9ae rrbm RRE_RR "reset reference bits multiple" z196 zarch +b394 cefbra RRF_UUFR "convert from 32 bit fixed to short bfp with rounding mode" z196 zarch +b395 cdfbra RRF_UUFR "convert from 32 bit fixed to long bfp with rounding mode" z196 zarch +b396 cxfbra RRF_UUFR "convert from 32 bit fixed to extended bfp with rounding mode" z196 zarch +b3a4 cegbra RRF_UUFR "convert from 64 bit fixed to short bfp with rounding mode" z196 zarch +b3a5 cdgbra RRF_UUFR "convert from 64 bit fixed to long bfp with rounding mode" z196 zarch +b3a6 cxgbra RRF_UUFR "convert from 64 bit fixed to extended bfp with rounding mode" z196 zarch +b390 celfbr RRF_UUFR "convert from 32 bit logical fixed to short bfp with rounding mode" z196 zarch +b391 cdlfbr RRF_UUFR "convert from 32 bit logical fixed to long bfp with rounding mode" z196 zarch +b392 cxlfbr RRF_UUFR "convert from 32 bit logical fixed to extended bfp with rounding mode" z196 zarch +b3a0 celgbr RRF_UUFR "convert from 64 bit logical fixed to short bfp with rounding mode" z196 zarch +b3a1 cdlgbr RRF_UUFR "convert from 64 bit logical fixed to long bfp with rounding mode" z196 zarch +b3a2 cxlgbr RRF_UUFR "convert from 64 bit logical fixed to extended bfp with rounding mode" z196 zarch +b398 cfebra RRF_UURF "convert to 32 bit fixed from short bfp with rounding mode" z196 zarch +b399 cfdbra RRF_UURF "convert to 32 bit fixed from long bfp with rounding mode" z196 zarch +b39a cfxbra RRF_UURF "convert to 32 bit fixed from extended bfp with rounding mode" z196 zarch +b3a8 cgebra RRF_UURF "convert to 64 bit fixed from short bfp with rounding mode" z196 zarch +b3a9 cgdbra RRF_UURF "convert to 64 bit fixed from long bfp with rounding mode" z196 zarch +b3aa cgxbra RRF_UURF "convert to 64 bit fixed from extended bfp with rounding mode" z196 zarch +b39c clfebr RRF_UURF "convert to 32 bit fixed logical from short bfp with rounding mode" z196 zarch +b39d clfdbr RRF_UURF "convert to 32 bit fixed logical from long bfp with rounding mode" z196 zarch +b39e clfxbr RRF_UURF "convert to 32 bit fixed logical from extended bfp with rounding mode" z196 zarch +b3ac clgebr RRF_UURF "convert to 64 bit fixed logical from short bfp with rounding mode" z196 zarch +b3ad clgdbr RRF_UURF "convert to 64 bit fixed logical from long bfp with rounding mode" z196 zarch +b3ae clgxbr RRF_UURF "convert to 64 bit fixed logical from extended bfp with rounding mode" z196 zarch +b357 fiebra RRF_UUFF "load fp integer short bfp with rounding mode" z196 zarch +b35f fidbra RRF_UUFF "load fp integer long bfp with rounding mode" z196 zarch +b347 fixbra RRF_UUFF "load fp integer extended bfp with rounding mode" z196 zarch +b344 ledbra RRF_UUFF "load rounded short/long bfp to short/long bfp with rounding mode" z196 zarch +b345 ldxbra RRF_UUFF "load rounded long/extended bfp to long/extended bfp with rounding mode" z196 zarch +b346 lexbra RRF_UUFF "load rounded short/extended bfp to short/extended bfp with rounding mode" z196 zarch +b3d2 adtra RRF_FUFF2 "add long dfp with rounding mode" z196 zarch +b3da axtra RRF_FUFF2 "add extended dfp with rounding mode" z196 zarch +b3f1 cdgtra RRF_UUFR "convert from fixed long dfp with rounding mode" z196 zarch +b951 cdftr RRF_UUFR "convert from 32 bit fixed to long dfp with rounding mode" z196 zarch +b959 cxftr RRF_UUFR "convert from 32 bit fixed to extended dfp with rounding mode" z196 zarch +b3f9 cxgtra RRF_UUFR "convert from fixed extended dfp with rounding mode" z196 zarch +b952 cdlgtr RRF_UUFR "convert from 64 bit fixed logical to long dfp with rounding mode" z196 zarch +b95a cxlgtr RRF_UUFR "convert from 64 bit fixed logical to extended dfp with rounding mode" z196 zarch +b953 cdlftr RRF_UUFR "convert from 32 bit fixed logical to long dfp with rounding mode" z196 zarch +b95b cxlftr RRF_UUFR "convert from 32 bit fixed logical to extended dfp with rounding mode" z196 zarch +b3e1 cgdtra RRF_UURF "convert to 64 bit fixed from long dfp with rounding mode" z196 zarch +b3e9 cgxtra RRF_UURF "convert to 64 bit fixed from extended dfp with rounding mode" z196 zarch +b941 cfdtr RRF_UURF "convert to 32 bit fixed from long dfp source with rounding mode" z196 zarch +b949 cfxtr RRF_UURF "convert to 32 bit fixed from extended dfp source with rounding mode" z196 zarch +b942 clgdtr RRF_UURF "convert to 64 bit fixed logical from long dfp with rounding mode" z196 zarch +b94a clgxtr RRF_UURF "convert to 64 bit fixed logical from extended dfp with rounding mode" z196 zarch +b943 clfdtr RRF_UURF "convert to 32 bit fixed logical from long dfp with rounding mode" z196 zarch +b94b clfxtr RRF_UURF "convert to 32 bit fixed logical from extended dfp with rounding mode" z196 zarch +b3d1 ddtra RRF_FUFF2 "divide long dfp with rounding mode" z196 zarch +b3d9 dxtra RRF_FUFF2 "divide extended dfp with rounding mode" z196 zarch +b3d0 mdtra RRF_FUFF2 "multiply long dfp with rounding mode" z196 zarch +b3d8 mxtra RRF_FUFF2 "multiply extended dfp with rounding mode" z196 zarch +b3d3 sdtra RRF_FUFF2 "subtract long dfp with rounding mode" z196 zarch +b3db sxtra RRF_FUFF2 "subtract extended dfp with rounding mode" z196 zarch +b2b8 srnmb S_RD "set 3 bit bfp rounding mode" z196 zarch diff --git a/external/gpl3/gdb/dist/opcodes/score-dis.c b/external/gpl3/gdb/dist/opcodes/score-dis.c new file mode 100644 index 000000000000..900c1c131fa0 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/score-dis.c @@ -0,0 +1,1208 @@ +/* Instruction printing code for Score + Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#define DEFINE_TABLE +#include "opintl.h" +#include "bfd.h" + +/* FIXME: This shouldn't be done here. */ +#include "elf-bfd.h" +#include "elf/internal.h" +#include "elf/score.h" + +#ifdef BFD64 +/* s3_s7: opcodes and export prototypes. */ +extern int +s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little); + +struct score_opcode +{ + bfd_vma value; + bfd_vma mask; /* Recognise instruction if (op & mask) == value. */ + char *assembler; /* Disassembly string. */ +}; + +/* Note: There is a partial ordering in this table - it must be searched from + the top to obtain a correct match. */ + +static struct score_opcode score_opcodes[] = +{ + /* Score Instructions. */ + {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, + {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, + {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"}, + {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"}, + {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"}, + {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"}, + {0x00004800, 0x00007f00, "add!\t\t%4-7r, %0-3r"}, + {0x00005c00, 0x00007c00, "addi!\t\t%6-9r, %0-5i"}, + {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x040000000000LL, 0x1c0000000003LL, "andri48\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x040000000001LL, 0x1c0000000003LL, "andri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"}, + {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"}, + {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"}, + {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"}, + {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"}, + {0x00004b00, 0x00007f00, "and!\t\t%4-7r, %0-3r"}, + {0x08000000, 0x3e007c01, "bcs\t\t%b"}, + {0x08000400, 0x3e007c01, "bcc\t\t%b"}, + {0x08003800, 0x3e007c01, "bcnz\t\t%b"}, + {0x08000001, 0x3e007c01, "bcsl\t\t%b"}, + {0x08000401, 0x3e007c01, "bccl\t\t%b"}, + {0x08003801, 0x3e007c01, "bcnzl\t\t%b"}, + {0x0000004c, 0x3e00007e, "bcmpeqz\t\t%15-19r, %z"}, + {0x0000004c, 0x3e00007e, "bcmpeq\t\t%15-19r, %z"}, + {0x0000004e, 0x3e00007e, "bcmpnez\t\t%15-19r, %z"}, + {0x0000004e, 0x3e00007e, "bcmpne\t\t%15-19r, %z"}, + {0x00003200, 0x00007e00, "bcnz!\t\t%b"}, + {0x08001000, 0x3e007c01, "beq\t\t%b"}, + {0x08001001, 0x3e007c01, "beql\t\t%b"}, + {0x00003800, 0x00007e00, "beq!\t\t%b"}, + {0x08000800, 0x3e007c01, "bgtu\t\t%b"}, + {0x08001800, 0x3e007c01, "bgt\t\t%b"}, + {0x08002000, 0x3e007c01, "bge\t\t%b"}, + {0x08000801, 0x3e007c01, "bgtul\t\t%b"}, + {0x08001801, 0x3e007c01, "bgtl\t\t%b"}, + {0x08002001, 0x3e007c01, "bgel\t\t%b"}, + {0x00003400, 0x00007e00, "bgtu!\t\t%b"}, + {0x00003c00, 0x00007e00, "bgt!\t\t%b"}, + {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00000028, 0x3e0003ff, "bitclr\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002a, 0x3e0003ff, "bitset\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"}, + {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002e, 0x3e0003ff, "bittgl\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00005000, 0x00007e00, "bitclr!\t\t%5-8r, 0x%0-4x"}, + {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"}, + {0x00005200, 0x00007e00, "bitset!\t\t%5-8r, 0x%0-4x"}, + {0x00005400, 0x00007e00, "bittst!\t\t%5-8r, 0x%0-4x"}, + {0x00005600, 0x00007e00, "bittgl!\t\t%5-8r, 0x%0-4x"}, + {0x08000c00, 0x3e007c01, "bleu\t\t%b"}, + {0x08001c00, 0x3e007c01, "ble\t\t%b"}, + {0x08002400, 0x3e007c01, "blt\t\t%b"}, + {0x08000c01, 0x3e007c01, "bleul\t\t%b"}, + {0x08001c01, 0x3e007c01, "blel\t\t%b"}, + {0x08002401, 0x3e007c01, "bltl\t\t%b"}, + {0x08003c01, 0x3e007c01, "bl\t\t%b"}, + {0x00003600, 0x00007e00, "bleu!\t\t%b"}, + {0x00003e00, 0x00007e00, "ble!\t\t%b"}, + {0x08002800, 0x3e007c01, "bmi\t\t%b"}, + {0x08002801, 0x3e007c01, "bmil\t\t%b"}, + {0x08001400, 0x3e007c01, "bne\t\t%b"}, + {0x08001401, 0x3e007c01, "bnel\t\t%b"}, + {0x00003a00, 0x00007e00, "bne!\t\t%b"}, + {0x08002c00, 0x3e007c01, "bpl\t\t%b"}, + {0x08002c01, 0x3e007c01, "bpll\t\t%b"}, + {0x00000008, 0x3e007fff, "brcs\t\t%15-19r"}, + {0x00000408, 0x3e007fff, "brcc\t\t%15-19r"}, + {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"}, + {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"}, + {0x00001008, 0x3e007fff, "breq\t\t%15-19r"}, + {0x00001408, 0x3e007fff, "brne\t\t%15-19r"}, + {0x00001808, 0x3e007fff, "brgt\t\t%15-19r"}, + {0x00001c08, 0x3e007fff, "brle\t\t%15-19r"}, + {0x00002008, 0x3e007fff, "brge\t\t%15-19r"}, + {0x00002408, 0x3e007fff, "brlt\t\t%15-19r"}, + {0x00002808, 0x3e007fff, "brmi\t\t%15-19r"}, + {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"}, + {0x00003008, 0x3e007fff, "brvs\t\t%15-19r"}, + {0x00003408, 0x3e007fff, "brvc\t\t%15-19r"}, + {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"}, + {0x00003c08, 0x3e007fff, "br\t\t%15-19r"}, + {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"}, + {0x00000409, 0x3e007fff, "brccl\t\t%15-19r"}, + {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"}, + {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"}, + {0x00001009, 0x3e007fff, "breql\t\t%15-19r"}, + {0x00001409, 0x3e007fff, "brnel\t\t%15-19r"}, + {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"}, + {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"}, + {0x00002009, 0x3e007fff, "brgel\t\t%15-19r"}, + {0x00002409, 0x3e007fff, "brltl\t\t%15-19r"}, + {0x00002809, 0x3e007fff, "brmil\t\t%15-19r"}, + {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"}, + {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"}, + {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"}, + {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"}, + {0x00003c09, 0x3e007fff, "brl\t\t%15-19r"}, + {0x00000080, 0x00007fe0, "br!\t\t%0-4r"}, + {0x000000a0, 0x00007fe0, "brl!\t\t%0-4r"}, + {0x000000c0, 0x00007fe0, "brr!\t\t%0-4r"}, + {0x08003000, 0x3e007c01, "bvs\t\t%b"}, + {0x08003400, 0x3e007c01, "bvc\t\t%b"}, + {0x08003001, 0x3e007c01, "bvsl\t\t%b"}, + {0x08003401, 0x3e007c01, "bvcl\t\t%b"}, + {0x00003000, 0x00007e00, "b!\t\t%b"}, + {0x08003c00, 0x3e007c01, "b\t\t%b"}, + {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, + {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, + {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, + {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, + {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, + {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, + {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, + {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, + {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, + {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, + {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, + {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, + {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, + {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, + {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, + + {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"}, + {0x0000006c, 0x3e00007e, "mbitset\t\t[%15-19r, %m], %10-14d"}, + + {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, + {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, + {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, + {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, + {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, + {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, + {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, + {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, + {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, + {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, + {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, + {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, + {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"}, + {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"}, + {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"}, + {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"}, + {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"}, + {0x00004400, 0x00007c00, "cmp!\t\t%5-9r, %0-4r"}, + {0x00006000, 0x00007c00, "cmpi!\t\t%5-9r, %0-4i"}, + {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"}, + {0x00000144, 0x3e0003ff, "divr.q\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000244, 0x3e0003ff, "divr.r\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000344, 0x3e0003ff, "divr\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"}, + {0x00000146, 0x3e0003ff, "divur.q\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000246, 0x3e0003ff, "divur.r\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000346, 0x3e0003ff, "divur\t\t%20-24r,%15-19r, %10-14r"}, + {0x0c0000a4, 0x3e0003ff, "drte"}, + {0x00e0, 0xffe1, "disint!"}, + {0x00e1, 0xffe1, "enint!"}, + {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"}, + {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"}, + {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"}, + {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"}, + {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"}, + {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"}, + {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"}, + {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"}, + {0x04000001, 0x3e000001, "jl\t\t%j"}, + {0x04000000, 0x3e000001, "j\t\t%j"}, + {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"}, + {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"}, + {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"}, + {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x000000000001LL, 0x1c000000001fLL, "ldi48\t\t%37-41r, %5-36i"}, + {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x00006400, 0x00007c00, "ldiu!\t\t%5-9r, %0-4d"}, + {0x00000032, 0x3e0003ff, "ltbw\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x00000132, 0x3e0003ff, "ltbh\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x00000332, 0x3e0003ff, "ltbb\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"}, + {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"}, + {0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"}, + {0x00007a00, 0x00007f00, "madl.fs!\t\t%4-7r, %0-3r"}, + {0x00007500, 0x00007f00, "madu!\t\t%4-7r, %0-3r"}, + {0x00007400, 0x00007f00, "mad.f!\t\t%4-7r, %0-3r"}, + {0x00007900, 0x00007f00, "mazh.f!\t\t%4-7r, %0-3r"}, + {0x00007800, 0x00007f00, "mazl.f!\t\t%4-7r, %0-3r"}, + {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, + {0x00007100, 0x00007ff0, "mfcel!\t\t%0-3r"}, + {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, + {0x00007110, 0x00007ff0, "mfceh!\t\t%0-3r"}, + {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, + {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, + {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, + {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"}, + {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"}, + {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"}, + {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"}, + {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"}, + {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, + /* confilct: push! mhfl!. */ + {0x00000040, 0x00007fe0, "pop!\t\t%0-4r"}, + {0x00000060, 0x00007fe0, "push!\t\t%0-4r"}, + {0x00006800, 0x00007c00, "rpop!\t\t%5-9r, %0-4d"}, + {0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"}, + {0x00007600, 0x00007f00, "msb.f!\t\t%4-7r, %0-3r"}, + {0x00007f00, 0x00007f00, "msbh.fs!\t\t%4-7r, %0-3r"}, + {0x00007e00, 0x00007f00, "msbl.fs!\t\t%4-7r, %0-3r"}, + {0x00007700, 0x00007f00, "msbu!\t\t%4-7r, %0-3r"}, + {0x00007d00, 0x00007f00, "mszh.f!\t\t%4-7r, %0-3r"}, + {0x00007c00, 0x00007f00, "mszl.f!\t\t%4-7r, %0-3r"}, + {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"}, + {0x00007000, 0x00007ff0, "mtcel!\t\t%0-3r"}, + {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"}, + {0x00007010, 0x00007ff0, "mtceh!\t\t%0-3r"}, + {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"}, + {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"}, + {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"}, + {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"}, + {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"}, + {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"}, + {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"}, + {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"}, + {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"}, + {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, + {0x00000140, 0x3e0003ff, "mulr.l\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000240, 0x3e0003ff, "mulr.h\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000340, 0x3e0003ff, "mulr\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000141, 0x3e0003ff, "mulr.lf\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000241, 0x3e0003ff, "mulr.hf\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, + {0x00007200, 0x00007f00, "mul.f!\t\t%4-7r, %0-3r"}, + {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, + {0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, + {0x00007300, 0x00007f00, "mulu!\t\t%4-7r, %0-3r"}, + {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, + {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, + {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, + {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"}, + {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"}, + {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"}, + {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"}, + {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"}, + {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"}, + {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"}, + {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"}, + {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"}, + {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"}, + {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"}, + {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"}, + {0x00004000, 0x00007c00, "mv!\t\t%5-9r, %0-4r"}, + {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"}, + {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"}, + {0x00000000, 0x3e0003ff, "nop"}, + {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"}, + {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"}, + {0x00000000, 0x00007fff, "nop!"}, + {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, + {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, + {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x00004a00, 0x00007f00, "or!\t\t%4-7r, %0-3r"}, + {0x040000000002LL, 0x1c0000000003LL, "orri48\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x040000000003LL, 0x1c0000000003LL, "orri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x0000000a, 0x3e0003ff, "pflush"}, + {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0c000084, 0x3e0003ff, "rte"}, + {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"}, + {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"}, + {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"}, + {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"}, + {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"}, + {0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"}, + {0x000000000000LL, 0x1c000000001fLL, "sdbbp48\t\t%5-9d"}, + {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0c0000c4, 0x3e0003ff, "sleep"}, + {0x0c0000e4, 0x3e0003ff, "rti"}, + {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00005800, 0x00007e00, "slli!\t\t%5-8r, %0-4d"}, + {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00005a00, 0x00007e00, "srli!\t\t%5-8r, %0-4d"}, + {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00004900, 0x00007f00, "sub!\t\t%4-7r, %0-3r"}, + {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002000, 0x00007000, "sw!\t\t%8-11r, [%5-7r,%0-4d2]"}, + {0x000000000003LL, 0x1c000000001fLL, "sw48\t\t%37-41r, [0x%7-36w]"}, + {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"}, + {0x00000054, 0x3e007fff, "tcs"}, + {0x00000454, 0x3e007fff, "tcc"}, + {0x00003854, 0x3e007fff, "tcnz"}, + {0x00001054, 0x3e007fff, "teq"}, + {0x00000854, 0x3e007fff, "tgtu"}, + {0x00001854, 0x3e007fff, "tgt"}, + {0x00002054, 0x3e007fff, "tge"}, + {0x00000c54, 0x3e007fff, "tleu"}, + {0x00001c54, 0x3e007fff, "tle"}, + {0x00002454, 0x3e007fff, "tlt"}, + {0x0c000004, 0x3e0003ff, "stlb"}, + {0x0c000024, 0x3e0003ff, "mftlb"}, + {0x0c000044, 0x3e0003ff, "mtptlb"}, + {0x0c000064, 0x3e0003ff, "mtrtlb"}, + {0x00002854, 0x3e007fff, "tmi"}, + {0x00001454, 0x3e007fff, "tne"}, + {0x00002c54, 0x3e007fff, "tpl"}, + {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"}, + {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"}, + {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"}, + {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"}, + {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"}, + {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"}, + {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"}, + {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"}, + {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"}, + {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"}, + {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"}, + {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"}, + {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"}, + {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"}, + {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"}, + {0x00003c54, 0x3e007fff, "tset"}, + {0x00003054, 0x3e007fff, "tvs"}, + {0x00003454, 0x3e007fff, "tvc"}, + {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, +}; + + +#ifndef streq +#define streq(a,b) (strcmp ((a), (b)) == 0) +#endif + +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +typedef struct +{ + const char *name; + const char *description; + const char *reg_names[32]; +} score_regname; + +static score_regname regnames[] = +{ + {"gcc", "Select register names used by GCC", + {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", + "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}}, +}; + +static unsigned int regname_selected = 0; + +#define NUM_SCORE_REGNAMES NUM_ELEM (regnames) +#define score_regnames regnames[regname_selected].reg_names + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score48 (struct disassemble_info *info, bfd_vma given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = score_opcodes; insn->assembler; insn++) + { + /* Using insn->mask &0xff00000000 to distinguish 48/32 bit. */ + if (((insn->mask & 0xff0000000000LL)!=0) && (given & insn->mask) == insn->value) + { + info->bytes_per_chunk = 2; + info->bytes_per_line =6; + + char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", score_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'i': + { + long reg; + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + reg = ((reg ^ (1 << (bitend - bitstart))) - + (1 << (bitend - bitstart))); + /* Fix bug: s3_testsuite 64-bit. + Remove high 32 bits. */ + reg = (int) reg; + + if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ + || ((given & insn->mask) == 0x0c000012) /* ldc2 */ + || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ + || ((given & insn->mask) == 0x0c00000b) /* stc1 */ + || ((given & insn->mask) == 0x0c000013) /* stc2 */ + || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ + reg <<= 2; + + func (stream, "%ld", reg); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + /* Fix bug: s3_testsuite 64-bit. + Remove high 32 bits. */ + reg = (int) reg; + + func (stream, "%lx", reg); + } + break; + case 'w': + { + long reg; + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + reg <<=2; + func (stream, "%lx", reg); + } + break; + + default: + abort (); + } + break; + + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + break; + } + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + return 6; + } + } + +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 6; +#endif + + abort (); +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + int rb_equal_zero=1; + fprintf_ftype func = info->fprintf_func; + + for (insn = score_opcodes; insn->assembler; insn++) + { + if (((insn->mask & 0xff0000000000LL)==0)&&(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + /* check for bcmpeq / bcmpeqz / bcmpne / bcmpnez */ + /* given &0x7c00 is for to test if rb is zero , + rb_equal_zero =1 : index to bcmpeqz + rb_equal_zero =0 , index to bcmpeq + this checking rule only for branch compare ( insn->mask ==0x3e00007e*/ + if (((given & 0x7c00) !=0)&&(rb_equal_zero ==1)&&(insn->mask == 0x3e00007e) + && (insn->value == 0x0000004c || insn->value == 0x0000004e)) + { + rb_equal_zero =0; + continue; + } + + char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + target = (pc & 0xfe000000) | (given & 0x01fffffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 20-bit number. */ +#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) + int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); + int target = (pc + SEXT20 (disp)); + + (*info->print_address_func) (target, info); + } + break; + case 'z': + { +#define SEXT10(x) ((((x) & 0x3ff) ^ (~ 0x1ff)) + 0x200) + if ((given & 0x7c00 ) == 0) + { + /* Sign-extend a 20-bit number. */ + /* disp : [24 -20] , [9-7 ] , [0] */ + int disp = (given&1)<<1 |((given>>7)&7)<<2 |((given>>20)&0x1f)<<5; + int target = (pc + SEXT10 (disp)); + (*info->print_address_func) (target, info); + } + else + { + long reg; + int bitstart = 10; + int bitend = 14; + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + /* Sign-extend a 20-bit number. */ + int disp = (given&1)<<1 |((given>>7)&7)<<2 |((given>>20)&0x1f)<<5; + int target = (pc + SEXT10 (disp)); + func (stream, "%s ,", score_regnames[reg] ); + (*info->print_address_func) (target, info); + + } + + } + break; + case 'm': + { + /* disp : [24 -20] , [9-7 ] , [0] */ + int disp = (given&1)<<2 |((given>>7)&7)<<3 |((given>>20)&0x1f)<<6; + (*info->print_address_func) (disp, info); + } + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", score_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'i': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + reg = ((reg ^ (1 << (bitend - bitstart))) - + (1 << (bitend - bitstart))); + + if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ + || ((given & insn->mask) == 0x0c000012) /* ldc2 */ + || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ + || ((given & insn->mask) == 0x0c00000b) /* stc1 */ + || ((given & insn->mask) == 0x0c000013) /* stc2 */ + || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ + reg <<= 2; + + func (stream, "%ld", reg); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%lx", reg); + } + break; + default: + abort (); + } + break; + + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + break; + } + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + return 4; + } + } + +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 4; +#endif + + abort (); +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + given &= 0xffff; + for (insn = score_opcodes; insn->assembler; insn++) + { + if (((insn->mask & 0xff0000000000LL)==0) &&!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + char *c = insn->assembler; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 4; + given &= 0xffff; + + for (; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + + target = (pc & 0xfffff000) | (given & 0x00000ffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 9-bit number. */ +#define SEXT10(x) ((((x) & 0x3ff) ^ (~ 0x1ff)) + 0x200) + int disp = (given & 0x1ff) << 1; + int target = (pc + SEXT10 (disp)); + + (*info->print_address_func) (target, info); + } + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + /* Check rpush rd, 0 and rpop! rd, 0. + If reg = 0, then set to 32. */ + if (((given & 0x00007c00) == 0x00006c00 + || (given & 0x00007c00) == 0x00006800) + && reg == 0) + { + reg = 32; + } + + switch (*c) + { + case 'R': + func (stream, "%s", score_regnames[reg + 16]); + break; + case 'r': + func (stream, "%s", score_regnames[reg]); + break; + case 'd': + if (*(c + 1) == '\0') + func (stream, "%ld", reg); + else + { + c++; + if (*c == '1') + func (stream, "%ld", reg << 1); + else if (*c == '2') + func (stream, "%ld", reg << 2); + } + break; + + case 'x': + if (*(c + 1) == '\0') + func (stream, "%lx", reg); + else + { + c++; + if (*c == '1') + func (stream, "%lx", reg << 1); + else if (*c == '2') + func (stream, "%lx", reg << 2); + } + break; + case 'i': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%ld", reg); + break; + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + } + break; + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + return 2; + } + } +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 2; +#endif + + /* No match. */ + abort (); +} + +/* NOTE: There are no checks in these routines that + the relevant number of data bytes exist. */ +static int +s3_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) +{ + unsigned char b[6]; + bfd_vma given,given_h , given_l, given_16, given_32, given_48; + bfd_vma ridparity; + int status; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); + if (status != 0) + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + } + if (little) + { + given = b[0] | (b[1] << 8); + } + else + { + given = (b[0] << 8) | b[1]; + } + + /* Set given_16. */ + given_16 = given; + + /* Judge if now is insn_16_p. */ + if ((given & 0x8000)==0) + return print_insn_score16 (pc, info, given); + + else + { + if (little) + { + given = ((bfd_vma)b[2]) | ((bfd_vma)b[3] << 8) | ((bfd_vma)b[0] << 16) | ((bfd_vma)b[1] << 24); + } + else + { + given = ((bfd_vma)b[0] << 24) | ((bfd_vma)b[1] << 16) | ((bfd_vma)b[2] << 8) | ((bfd_vma)b[3]); + } + + /* Set given_32. */ + given_32 = given; + + /* Judge if now is insn_32. */ + if ((given &0x80008000)==0x80000000) + { + /* Get rid of parity. */ + ridparity = (given & 0x7FFF); + ridparity |= (given & 0x7FFF0000) >> 1; + given = ridparity; + return print_insn_score32 (pc, info, given); + } + } + + /* The insn is 48 bit. */ + status = info->read_memory_func (pc, (bfd_byte *) & b[0], 6, info); + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + + if (little) + { + given = ((bfd_vma)b[4]) | ((bfd_vma)b[5] << 8) | ((bfd_vma)b[2] << 16) | ((bfd_vma)b[3] << 24) + | ((bfd_vma)b[0] << 32) | ((bfd_vma)b[1] << 40); + } + else + { + given_l = ((bfd_vma)b[5]) | ((bfd_vma)b[4] << 8) | ((bfd_vma)b[3] << 16) | ((bfd_vma)b[2] << 24) ; + given_h = ((bfd_vma)b[1] )|((bfd_vma)b[0] <<8); + given = ((bfd_vma)given_h<<32) | (bfd_vma)given_l ; + + } + + /* Set given_48. */ + given_48 = given; + + if ((given & 0x800080008000LL) == 0x800080000000LL) + { + /* Get rid of parity. */ + ridparity = (given & 0x7FFF); + ridparity |= (given & 0x7FFF0000) >> 1; + ridparity |= (given & 0x7FFF00000000LL) >> 2; + given = ridparity; + status = print_insn_score48 (info, given); + return status; + } + + /* Check 0x800080008000, 0x80008000, 0x8000. */ + if ((given_48 & 0x800080008000LL) != 0x800080000000LL) + { +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 6; +#endif + } + if (((given_32 & 0xffff00000000LL) == 0) && ((given_32 & 0x80008000) != 0x80000000)) + { +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 4; +#endif + } + if (((given_16 & 0xffffffff0000LL) == 0) && ((given_16 & 0x8000) != 0)) + { +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 2; +#endif + } + else + { + return 0; + } +} + +static unsigned long +score_get_arch (disassemble_info *info) +{ + if (info->arch == bfd_arch_score) + return info->mach; + else + return 0; +} + +int +print_insn_big_score (bfd_vma pc, struct disassemble_info *info) +{ + if (score_get_arch (info) == bfd_mach_score3) + return s3_print_insn (pc, info, FALSE); + else + return s7_print_insn (pc, info, FALSE); +} + +int +print_insn_little_score (bfd_vma pc, struct disassemble_info *info) +{ + if (score_get_arch (info) == bfd_mach_score3) + return s3_print_insn (pc, info, TRUE); + else + return s7_print_insn (pc, info, TRUE); +} +#else /* not BFD64 */ +int +print_insn_big_score (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info * info ATTRIBUTE_UNUSED) +{ + abort (); +} + +int +print_insn_little_score (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info * info ATTRIBUTE_UNUSED) +{ + abort (); +} +#endif diff --git a/external/gpl3/gdb/dist/opcodes/score-opc.h b/external/gpl3/gdb/dist/opcodes/score-opc.h new file mode 100644 index 000000000000..c98cb728891e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/score-opc.h @@ -0,0 +1,455 @@ +/* Copyright 2006, 2007, 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +struct score_opcode +{ + bfd_vma value; + bfd_vma mask; /* Recognise instruction if (op & mask) == value. */ + char *assembler; /* Disassembly string. */ +}; + +/* Note: There is a partial ordering in this table - it must be searched from + the top to obtain a correct match. */ + +static struct score_opcode score_opcodes[] = +{ + /* Score Instructions. */ + {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, + {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, + {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"}, + {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"}, + {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"}, + {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"}, + {0x00004800, 0x00007f00, "add!\t\t%4-7r, %0-3r"}, + {0x00005c00, 0x00007c00, "addi!\t\t%6-9r, %0-5i"}, + {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x040000000000LL, 0x1c0000000003LL, "andri48\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x040000000001LL, 0x1c0000000003LL, "andri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"}, + {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"}, + {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"}, + {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"}, + {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"}, + {0x00004b00, 0x00007f00, "and!\t\t%4-7r, %0-3r"}, + {0x08000000, 0x3e007c01, "bcs\t\t%b"}, + {0x08000400, 0x3e007c01, "bcc\t\t%b"}, + {0x08003800, 0x3e007c01, "bcnz\t\t%b"}, + {0x08000001, 0x3e007c01, "bcsl\t\t%b"}, + {0x08000401, 0x3e007c01, "bccl\t\t%b"}, + {0x08003801, 0x3e007c01, "bcnzl\t\t%b"}, + {0x0000004c, 0x3e00007e, "bcmpeqz\t\t%15-19r, %z"}, + {0x0000004c, 0x3e00007e, "bcmpeq\t\t%15-19r, %z"}, + {0x0000004e, 0x3e00007e, "bcmpnez\t\t%15-19r, %z"}, + {0x0000004e, 0x3e00007e, "bcmpne\t\t%15-19r, %z"}, + {0x00003200, 0x00007e00, "bcnz!\t\t%b"}, + {0x08001000, 0x3e007c01, "beq\t\t%b"}, + {0x08001001, 0x3e007c01, "beql\t\t%b"}, + {0x00003800, 0x00007e00, "beq!\t\t%b"}, + {0x08000800, 0x3e007c01, "bgtu\t\t%b"}, + {0x08001800, 0x3e007c01, "bgt\t\t%b"}, + {0x08002000, 0x3e007c01, "bge\t\t%b"}, + {0x08000801, 0x3e007c01, "bgtul\t\t%b"}, + {0x08001801, 0x3e007c01, "bgtl\t\t%b"}, + {0x08002001, 0x3e007c01, "bgel\t\t%b"}, + {0x00003400, 0x00007e00, "bgtu!\t\t%b"}, + {0x00003c00, 0x00007e00, "bgt!\t\t%b"}, + {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00000028, 0x3e0003ff, "bitclr\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002a, 0x3e0003ff, "bitset\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"}, + {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002e, 0x3e0003ff, "bittgl\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00005000, 0x00007e00, "bitclr!\t\t%5-8r, 0x%0-4x"}, + {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"}, + {0x00005200, 0x00007e00, "bitset!\t\t%5-8r, 0x%0-4x"}, + {0x00005400, 0x00007e00, "bittst!\t\t%5-8r, 0x%0-4x"}, + {0x00005600, 0x00007e00, "bittgl!\t\t%5-8r, 0x%0-4x"}, + {0x08000c00, 0x3e007c01, "bleu\t\t%b"}, + {0x08001c00, 0x3e007c01, "ble\t\t%b"}, + {0x08002400, 0x3e007c01, "blt\t\t%b"}, + {0x08000c01, 0x3e007c01, "bleul\t\t%b"}, + {0x08001c01, 0x3e007c01, "blel\t\t%b"}, + {0x08002401, 0x3e007c01, "bltl\t\t%b"}, + {0x08003c01, 0x3e007c01, "bl\t\t%b"}, + {0x00003600, 0x00007e00, "bleu!\t\t%b"}, + {0x00003e00, 0x00007e00, "ble!\t\t%b"}, + {0x08002800, 0x3e007c01, "bmi\t\t%b"}, + {0x08002801, 0x3e007c01, "bmil\t\t%b"}, + {0x08001400, 0x3e007c01, "bne\t\t%b"}, + {0x08001401, 0x3e007c01, "bnel\t\t%b"}, + {0x00003a00, 0x00007e00, "bne!\t\t%b"}, + {0x08002c00, 0x3e007c01, "bpl\t\t%b"}, + {0x08002c01, 0x3e007c01, "bpll\t\t%b"}, + {0x00000008, 0x3e007fff, "brcs\t\t%15-19r"}, + {0x00000408, 0x3e007fff, "brcc\t\t%15-19r"}, + {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"}, + {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"}, + {0x00001008, 0x3e007fff, "breq\t\t%15-19r"}, + {0x00001408, 0x3e007fff, "brne\t\t%15-19r"}, + {0x00001808, 0x3e007fff, "brgt\t\t%15-19r"}, + {0x00001c08, 0x3e007fff, "brle\t\t%15-19r"}, + {0x00002008, 0x3e007fff, "brge\t\t%15-19r"}, + {0x00002408, 0x3e007fff, "brlt\t\t%15-19r"}, + {0x00002808, 0x3e007fff, "brmi\t\t%15-19r"}, + {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"}, + {0x00003008, 0x3e007fff, "brvs\t\t%15-19r"}, + {0x00003408, 0x3e007fff, "brvc\t\t%15-19r"}, + {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"}, + {0x00003c08, 0x3e007fff, "br\t\t%15-19r"}, + {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"}, + {0x00000409, 0x3e007fff, "brccl\t\t%15-19r"}, + {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"}, + {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"}, + {0x00001009, 0x3e007fff, "breql\t\t%15-19r"}, + {0x00001409, 0x3e007fff, "brnel\t\t%15-19r"}, + {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"}, + {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"}, + {0x00002009, 0x3e007fff, "brgel\t\t%15-19r"}, + {0x00002409, 0x3e007fff, "brltl\t\t%15-19r"}, + {0x00002809, 0x3e007fff, "brmil\t\t%15-19r"}, + {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"}, + {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"}, + {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"}, + {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"}, + {0x00003c09, 0x3e007fff, "brl\t\t%15-19r"}, + {0x00000080, 0x00007fe0, "br!\t\t%0-4r"}, + {0x000000a0, 0x00007fe0, "brl!\t\t%0-4r"}, + {0x000000c0, 0x00007fe0, "brr!\t\t%0-4r"}, + {0x08003000, 0x3e007c01, "bvs\t\t%b"}, + {0x08003400, 0x3e007c01, "bvc\t\t%b"}, + {0x08003001, 0x3e007c01, "bvsl\t\t%b"}, + {0x08003401, 0x3e007c01, "bvcl\t\t%b"}, + {0x00003000, 0x00007e00, "b!\t\t%b"}, + {0x08003c00, 0x3e007c01, "b\t\t%b"}, + {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, + {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, + {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, + {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, + {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, + {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, + {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, + {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, + {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, + {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, + {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, + {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, + {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, + {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, + {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, + + {0x00000064, 0x3e00007e, "mbitclr\t\t[%15-19r, %m], %10-14d"}, + {0x0000006c, 0x3e00007e, "mbitset\t\t[%20-24r, %m], %10-14d"}, + + {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, + {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, + {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, + {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, + {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, + {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, + {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, + {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, + {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000001c, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, + {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, + {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, + {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, + {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"}, + {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"}, + {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"}, + {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"}, + {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"}, + {0x00004400, 0x00007c00, "cmp!\t\t%5-9r, %0-4r"}, + {0x00006000, 0x00007c00, "cmpi!\t\t%5-9r, %0-4i"}, + {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"}, + {0x00000144, 0x3e0003ff, "divr.q\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000244, 0x3e0003ff, "divr.r\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000344, 0x3e0003ff, "divr\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"}, + {0x00000146, 0x3e0003ff, "divur.q\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000246, 0x3e0003ff, "divur.r\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000346, 0x3e0003ff, "divur\t\t%20-24r,%15-19r, %10-14r"}, + {0x0c0000a4, 0x3e0003ff, "drte"}, + {0x00e0, 0xffe1, "disint!"}, + {0x00e1, 0xffe1, "enint!"}, + {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"}, + {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"}, + {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"}, + {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"}, + {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"}, + {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"}, + {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"}, + {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"}, + {0x04000001, 0x3e000001, "jl\t\t%j"}, + {0x04000000, 0x3e000001, "j\t\t%j"}, + {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"}, + {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"}, + {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"}, + {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x000000000001LL, 0x1c000000001fLL, "ldi48\t\t%37-41r, %5-36i"}, + {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x00006400, 0x00007c00, "ldiu!\t\t%5-9r, %0-4d"}, + {0x00000032, 0x3e0003ff, "ltbw\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x00000132, 0x3e0003ff, "ltbh\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x00000332, 0x3e0003ff, "ltbb\t\t%20-24r, [%15-19r, %10-14r]"}, + {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"}, + {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00001000, 0x00007000, "lw!\t\t%8-11r, [%5-7r,%0-4d2]"}, + {0x000000000002LL, 0x1c000000001fLL, "lw48\t\t%37-41r,[0x%7-36w]"}, + {0x00007b00, 0x00007f00, "madh.fs!\t\t%8-11r, %4-7r"}, + {0x00007a00, 0x00007f00, "madl.fs!\t\t%8-11r, %4-7r"}, + {0x00007500, 0x00007f00, "madu!\t\t%8-11r, %4-7r"}, + {0x00007400, 0x00007f00, "mad.f!\t\t%8-11r, %4-7r"}, + {0x00007900, 0x00007f00, "mazh.f!\t\t%8-11r, %4-7r"}, + {0x00007800, 0x00007f00, "mazl.f!\t\t%8-11r, %4-7r"}, + {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, + {0x00007100, 0x00007ff0, "mfcel!\t\t%4-7r"}, + {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, + {0x00007110, 0x00007ff0, "mfceh!\t\t%4-7r"}, + {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, + {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, + {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, + {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"}, + {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"}, + {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"}, + {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"}, + {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"}, + {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, + /* confilct: push! mhfl!. */ + {0x00000040, 0x00007fe0, "pop!\t\t%0-4r"}, + {0x00000060, 0x00007fe0, "push!\t\t%0-4r"}, + {0x00006800, 0x00007c00, "rpop!\t\t%5-9r, %0-4d"}, + {0x00006c00, 0x00007c00, "rpush!\t\t%5-9r, %0-4d"}, + {0x00007600, 0x00007f00, "msb.f!\t\t%8-11r, %4-7r"}, + {0x00007f00, 0x00007f00, "msbh.fs!\t\t%8-11r, %4-7r"}, + {0x00007e00, 0x00007f00, "msbl.fs!\t\t%8-11r, %4-7r"}, + {0x00007700, 0x00007f00, "msbu!\t\t%8-11r, %4-7r"}, + {0x00007d00, 0x00007f00, "mszh.f!\t\t%8-11r, %4-7r"}, + {0x00007c00, 0x00007f00, "mszl.f!\t\t%8-11r, %4-7r"}, + {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"}, + {0x00007000, 0x00007ff0, "mtcel!\t\t%4-7r"}, + {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"}, + {0x00007010, 0x00007ff0, "mtceh!\t\t%4-7r"}, + {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"}, + {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"}, + {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"}, + {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"}, + {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"}, + {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"}, + {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"}, + {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"}, + {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"}, + {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, + {0x00000140, 0x3e0003ff, "mulr.l\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000240, 0x3e0003ff, "mulr.h\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000340, 0x3e0003ff, "mulr\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, + {0x00000141, 0x3e0003ff, "mulr.lf\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000241, 0x3e0003ff, "mulr.hf\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000341, 0x3e0003ff, "mulr.f\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, + {0x00007200, 0x00007f00, "mul.f!\t\t%8-11r, %4-7r"}, + {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, + {0x00000142, 0x3e0003ff, "mulur.l\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000242, 0x3e0003ff, "mulur.h\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000342, 0x3e0003ff, "mulur\t\t%20-24r,%15-19r, %10-14r"}, + {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, + {0x00007300, 0x00007f00, "mulu!\t\t%8-11r, %4-7r"}, + {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, + {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, + {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, + {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"}, + {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"}, + {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"}, + {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"}, + {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"}, + {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"}, + {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"}, + {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"}, + {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"}, + {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"}, + {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"}, + {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"}, + {0x00004000, 0x00007c00, "mv!\t\t%5-9r, %0-4r"}, + {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"}, + {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"}, + {0x00000000, 0x3e0003ff, "nop"}, + {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"}, + {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"}, + {0x00000000, 0x00007fff, "nop!"}, + {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, + {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, + {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x00004a00, 0x00007f00, "or!\t\t%4-7r, %0-3r"}, + {0x040000000002LL, 0x1c0000000003LL, "orri48\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x040000000003LL, 0x1c0000000003LL, "orri48.c\t\t%38-41r,%34-37r, 0x%2-33x"}, + {0x0000000a, 0x3e0003ff, "pflush"}, + {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0c000084, 0x3e0003ff, "rte"}, + {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"}, + {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"}, + {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"}, + {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"}, + {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"}, + {0x00000020, 0x00007fe0, "sdbbp!\t\t%0-4d"}, + {0x000000000000LL, 0x1c000000001fLL, "sdbbp48\t\t%5-9d"}, + {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0c0000c4, 0x3e0003ff, "sleep"}, + {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00005800, 0x00007e00, "slli!\t\t%5-8r, %0-4d"}, + {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00005a00, 0x00007e00, "srli!\t\t%5-8r, %0-4d"}, + {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00004900, 0x00007f00, "sub!\t\t%4-7r, %0-3r"}, + {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002000, 0x00007000, "sw!\t\t%8-11r, [%5-7r,%0-4d2]"}, + {0x000000000003LL, 0x1c000000001fLL, "sw48\t\t%37-41r, [0x%7-36w]"}, + {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"}, + {0x00000054, 0x3e007fff, "tcs"}, + {0x00000454, 0x3e007fff, "tcc"}, + {0x00003854, 0x3e007fff, "tcnz"}, + {0x00001054, 0x3e007fff, "teq"}, + {0x00000854, 0x3e007fff, "tgtu"}, + {0x00001854, 0x3e007fff, "tgt"}, + {0x00002054, 0x3e007fff, "tge"}, + {0x00000c54, 0x3e007fff, "tleu"}, + {0x00001c54, 0x3e007fff, "tle"}, + {0x00002454, 0x3e007fff, "tlt"}, + {0x0c000004, 0x3e0003ff, "stlb"}, + {0x0c000024, 0x3e0003ff, "mftlb"}, + {0x0c000044, 0x3e0003ff, "mtptlb"}, + {0x0c000064, 0x3e0003ff, "mtrtlb"}, + {0x00002854, 0x3e007fff, "tmi"}, + {0x00001454, 0x3e007fff, "tne"}, + {0x00002c54, 0x3e007fff, "tpl"}, + {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"}, + {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"}, + {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"}, + {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"}, + {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"}, + {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"}, + {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"}, + {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"}, + {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"}, + {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"}, + {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"}, + {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"}, + {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"}, + {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"}, + {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"}, + {0x00003c54, 0x3e007fff, "tset"}, + {0x00003054, 0x3e007fff, "tvs"}, + {0x00003454, 0x3e007fff, "tvc"}, + {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, +}; diff --git a/external/gpl3/gdb/dist/opcodes/score7-dis.c b/external/gpl3/gdb/dist/opcodes/score7-dis.c new file mode 100644 index 000000000000..b48d1786b772 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/score7-dis.c @@ -0,0 +1,971 @@ +/* Instruction printing code for Score + Copyright 2009 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#define DEFINE_TABLE +#include "opintl.h" +#include "bfd.h" + +/* FIXME: This shouldn't be done here. */ +#include "elf-bfd.h" +#include "elf/internal.h" +#include "elf/score.h" + +#ifndef streq +#define streq(a,b) (strcmp ((a), (b)) == 0) +#endif + +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +struct score_opcode +{ + unsigned long value; + unsigned long mask; /* Recognise instruction if (op & mask) == value. */ + char *assembler; /* Disassembly string. */ +}; + +/* Note: There is a partial ordering in this table - it must be searched from + the top to obtain a correct match. */ + +static struct score_opcode score_opcodes[] = +{ + /* Score Instructions. */ + {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, + {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, + {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"}, + {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"}, + {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"}, + {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"}, + {0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"}, + {0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"}, + {0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"}, + {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"}, + {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"}, + {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"}, + {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"}, + {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"}, + {0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"}, + {0x08000000, 0x3e007c01, "bcs\t\t%b"}, + {0x08000400, 0x3e007c01, "bcc\t\t%b"}, + {0x08003800, 0x3e007c01, "bcnz\t\t%b"}, + {0x08000001, 0x3e007c01, "bcsl\t\t%b"}, + {0x08000401, 0x3e007c01, "bccl\t\t%b"}, + {0x08003801, 0x3e007c01, "bcnzl\t\t%b"}, + {0x00004000, 0x00007f00, "bcs!\t\t%b"}, + {0x00004100, 0x00007f00, "bcc!\t\t%b"}, + {0x00004e00, 0x00007f00, "bcnz!\t\t%b"}, + {0x08001000, 0x3e007c01, "beq\t\t%b"}, + {0x08001001, 0x3e007c01, "beql\t\t%b"}, + {0x00004400, 0x00007f00, "beq!\t\t%b"}, + {0x08000800, 0x3e007c01, "bgtu\t\t%b"}, + {0x08001800, 0x3e007c01, "bgt\t\t%b"}, + {0x08002000, 0x3e007c01, "bge\t\t%b"}, + {0x08000801, 0x3e007c01, "bgtul\t\t%b"}, + {0x08001801, 0x3e007c01, "bgtl\t\t%b"}, + {0x08002001, 0x3e007c01, "bgel\t\t%b"}, + {0x00004200, 0x00007f00, "bgtu!\t\t%b"}, + {0x00004600, 0x00007f00, "bgt!\t\t%b"}, + {0x00004800, 0x00007f00, "bge!\t\t%b"}, + {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"}, + {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"}, + {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"}, + {0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"}, + {0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"}, + {0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"}, + {0x08000c00, 0x3e007c01, "bleu\t\t%b"}, + {0x08001c00, 0x3e007c01, "ble\t\t%b"}, + {0x08002400, 0x3e007c01, "blt\t\t%b"}, + {0x08000c01, 0x3e007c01, "bleul\t\t%b"}, + {0x08001c01, 0x3e007c01, "blel\t\t%b"}, + {0x08002401, 0x3e007c01, "bltl\t\t%b"}, + {0x08003c01, 0x3e007c01, "bl\t\t%b"}, + {0x00004300, 0x00007f00, "bleu!\t\t%b"}, + {0x00004700, 0x00007f00, "ble!\t\t%b"}, + {0x00004900, 0x00007f00, "blt!\t\t%b"}, + {0x08002800, 0x3e007c01, "bmi\t\t%b"}, + {0x08002801, 0x3e007c01, "bmil\t\t%b"}, + {0x00004a00, 0x00007f00, "bmi!\t\t%b"}, + {0x08001400, 0x3e007c01, "bne\t\t%b"}, + {0x08001401, 0x3e007c01, "bnel\t\t%b"}, + {0x00004500, 0x00007f00, "bne!\t\t%b"}, + {0x08002c00, 0x3e007c01, "bpl\t\t%b"}, + {0x08002c01, 0x3e007c01, "bpll\t\t%b"}, + {0x00004b00, 0x00007f00, "bpl!\t\t%b"}, + {0x00000008, 0x3e007fff, "brcs\t\t%15-19r"}, + {0x00000408, 0x3e007fff, "brcc\t\t%15-19r"}, + {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r"}, + {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r"}, + {0x00001008, 0x3e007fff, "breq\t\t%15-19r"}, + {0x00001408, 0x3e007fff, "brne\t\t%15-19r"}, + {0x00001808, 0x3e007fff, "brgt\t\t%15-19r"}, + {0x00001c08, 0x3e007fff, "brle\t\t%15-19r"}, + {0x00002008, 0x3e007fff, "brge\t\t%15-19r"}, + {0x00002408, 0x3e007fff, "brlt\t\t%15-19r"}, + {0x00002808, 0x3e007fff, "brmi\t\t%15-19r"}, + {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r"}, + {0x00003008, 0x3e007fff, "brvs\t\t%15-19r"}, + {0x00003408, 0x3e007fff, "brvc\t\t%15-19r"}, + {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r"}, + {0x00003c08, 0x3e007fff, "br\t\t%15-19r"}, + {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r"}, + {0x00000409, 0x3e007fff, "brccl\t\t%15-19r"}, + {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r"}, + {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r"}, + {0x00001009, 0x3e007fff, "breql\t\t%15-19r"}, + {0x00001409, 0x3e007fff, "brnel\t\t%15-19r"}, + {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r"}, + {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r"}, + {0x00002009, 0x3e007fff, "brgel\t\t%15-19r"}, + {0x00002409, 0x3e007fff, "brltl\t\t%15-19r"}, + {0x00002809, 0x3e007fff, "brmil\t\t%15-19r"}, + {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r"}, + {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r"}, + {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r"}, + {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r"}, + {0x00003c09, 0x3e007fff, "brl\t\t%15-19r"}, + {0x00000004, 0x00007f0f, "brcs!\t\t%4-7r"}, + {0x00000104, 0x00007f0f, "brcc!\t\t%4-7r"}, + {0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r"}, + {0x00000304, 0x00007f0f, "brleu!\t\t%4-7r"}, + {0x00000404, 0x00007f0f, "breq!\t\t%4-7r"}, + {0x00000504, 0x00007f0f, "brne!\t\t%4-7r"}, + {0x00000604, 0x00007f0f, "brgt!\t\t%4-7r"}, + {0x00000704, 0x00007f0f, "brle!\t\t%4-7r"}, + {0x00000804, 0x00007f0f, "brge!\t\t%4-7r"}, + {0x00000904, 0x00007f0f, "brlt!\t\t%4-7r"}, + {0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r"}, + {0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r"}, + {0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r"}, + {0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r"}, + {0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r"}, + {0x00000f04, 0x00007f0f, "br!\t\t%4-7r"}, + {0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r"}, + {0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r"}, + {0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r"}, + {0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r"}, + {0x0000040c, 0x00007f0f, "breql!\t\t%4-7r"}, + {0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r"}, + {0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r"}, + {0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r"}, + {0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r"}, + {0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r"}, + {0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r"}, + {0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r"}, + {0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r"}, + {0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r"}, + {0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r"}, + {0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r"}, + {0x08003000, 0x3e007c01, "bvs\t\t%b"}, + {0x08003400, 0x3e007c01, "bvc\t\t%b"}, + {0x08003001, 0x3e007c01, "bvsl\t\t%b"}, + {0x08003401, 0x3e007c01, "bvcl\t\t%b"}, + {0x00004c00, 0x00007f00, "bvs!\t\t%b"}, + {0x00004d00, 0x00007f00, "bvc!\t\t%b"}, + {0x00004f00, 0x00007f00, "b!\t\t%b"}, + {0x08003c00, 0x3e007c01, "b\t\t%b"}, + {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, + {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, + {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, + {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, + {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, + {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, + {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, + {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, + {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, + {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, + {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, + {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, + {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, + {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, + {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, + {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, + {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, + {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, + {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, + {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, + {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, + {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, + {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, + {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, + {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, + {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, + {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"}, + {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"}, + {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"}, + {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"}, + {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"}, + {0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"}, + {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"}, + {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"}, + {0x0c0000a4, 0x3e0003ff, "drte"}, + {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"}, + {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"}, + {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"}, + {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"}, + {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"}, + {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"}, + {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"}, + {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"}, + {0x04000001, 0x3e000001, "jl\t\t%j"}, + {0x00003001, 0x00007001, "jl!\t\t%j"}, + {0x00003000, 0x00007001, "j!\t\t%j"}, + {0x04000000, 0x3e000001, "j\t\t%j"}, + {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"}, + {0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"}, + {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"}, + {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"}, + {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"}, + {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"}, + {0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"}, + {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"}, + {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"}, + {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"}, + {0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"}, + {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"}, + {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"}, + {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"}, + {0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"}, + {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"}, + {0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"}, + {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, + {0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"}, + {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, + {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"}, + {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, + {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, + {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, + {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"}, + {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"}, + {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"}, + {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"}, + {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"}, + {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, + {0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"}, + {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"}, + {0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"}, + {0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"}, + {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"}, + {0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"}, + {0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"}, + {0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"}, + {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"}, + {0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"}, + {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"}, + {0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"}, + {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"}, + {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"}, + {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"}, + {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"}, + {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"}, + {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"}, + {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"}, + {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"}, + {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"}, + {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, + {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, + {0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"}, + {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, + {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, + {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"}, + {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, + {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, + {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, + {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"}, + {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"}, + {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"}, + {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"}, + {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"}, + {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"}, + {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"}, + {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"}, + {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"}, + {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"}, + {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"}, + {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"}, + {0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"}, + {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r"}, + {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r"}, + {0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"}, + {0x00000000, 0x3e0003ff, "nop"}, + {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r"}, + {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r"}, + {0x00000000, 0x0000700f, "nop!"}, + {0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"}, + {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, + {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, + {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"}, + {0x0000000a, 0x3e0003ff, "pflush"}, + {0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"}, + {0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"}, + {0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"}, + {0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"}, + {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0c000084, 0x3e0003ff, "rte"}, + {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"}, + {0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"}, + {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"}, + {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"}, + {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"}, + {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"}, + {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"}, + {0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"}, + {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"}, + {0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"}, + {0x0c0000c4, 0x3e0003ff, "sleep"}, + {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"}, + {0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"}, + {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"}, + {0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"}, + {0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"}, + {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"}, + {0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"}, + {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"}, + {0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"}, + {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"}, + {0x00000054, 0x3e007fff, "tcs"}, + {0x00000454, 0x3e007fff, "tcc"}, + {0x00003854, 0x3e007fff, "tcnz"}, + {0x00000005, 0x00007f0f, "tcs!"}, + {0x00000105, 0x00007f0f, "tcc!"}, + {0x00000e05, 0x00007f0f, "tcnz!"}, + {0x00001054, 0x3e007fff, "teq"}, + {0x00000405, 0x00007f0f, "teq!"}, + {0x00000854, 0x3e007fff, "tgtu"}, + {0x00001854, 0x3e007fff, "tgt"}, + {0x00002054, 0x3e007fff, "tge"}, + {0x00000205, 0x00007f0f, "tgtu!"}, + {0x00000605, 0x00007f0f, "tgt!"}, + {0x00000805, 0x00007f0f, "tge!"}, + {0x00000c54, 0x3e007fff, "tleu"}, + {0x00001c54, 0x3e007fff, "tle"}, + {0x00002454, 0x3e007fff, "tlt"}, + {0x0c000004, 0x3e0003ff, "stlb"}, + {0x0c000024, 0x3e0003ff, "mftlb"}, + {0x0c000044, 0x3e0003ff, "mtptlb"}, + {0x0c000064, 0x3e0003ff, "mtrtlb"}, + {0x00000305, 0x00007f0f, "tleu!"}, + {0x00000705, 0x00007f0f, "tle!"}, + {0x00000905, 0x00007f0f, "tlt!"}, + {0x00002854, 0x3e007fff, "tmi"}, + {0x00000a05, 0x00007f0f, "tmi!"}, + {0x00001454, 0x3e007fff, "tne"}, + {0x00000505, 0x00007f0f, "tne!"}, + {0x00002c54, 0x3e007fff, "tpl"}, + {0x00000b05, 0x00007f0f, "tpl!"}, + {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"}, + {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"}, + {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"}, + {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"}, + {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"}, + {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"}, + {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"}, + {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"}, + {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"}, + {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"}, + {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"}, + {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"}, + {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"}, + {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"}, + {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"}, + {0x00003c54, 0x3e007fff, "tset"}, + {0x00000f05, 0x00007f0f, "tset!"}, + {0x00003054, 0x3e007fff, "tvs"}, + {0x00003454, 0x3e007fff, "tvc"}, + {0x00000c05, 0x00007f0f, "tvs!"}, + {0x00000d05, 0x00007f0f, "tvc!"}, + {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"} +}; + +typedef struct +{ + const char *name; + const char *description; + const char *reg_names[32]; +} score_regname; + +static score_regname regnames[] = +{ + {"gcc", "Select register names used by GCC", + {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", + "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}}, +}; + +static unsigned int regname_selected = 0; + +#define NUM_SCORE_REGNAMES NUM_ELEM (regnames) +#define score_regnames regnames[regname_selected].reg_names + +/* s3_s7: opcodes and export prototypes. */ +int +s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little); + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = score_opcodes; insn->assembler; insn++) + { + if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + target = (pc & 0xfe000000) | (given & 0x01fffffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 20-bit number. */ +#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) + int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); + int target = (pc + SEXT20 (disp)); + + (*info->print_address_func) (target, info); + } + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", score_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'i': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + reg = ((reg ^ (1 << (bitend - bitstart))) - + (1 << (bitend - bitstart))); + + if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ + || ((given & insn->mask) == 0x0c000012) /* ldc2 */ + || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ + || ((given & insn->mask) == 0x0c00000b) /* stc1 */ + || ((given & insn->mask) == 0x0c000013) /* stc2 */ + || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ + reg <<= 2; + + func (stream, "%ld", reg); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%lx", reg); + } + break; + default: + abort (); + } + break; + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + break; + } + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + return 4; + } + } + +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 4; +#endif + + abort (); +} + +static void +print_insn_parallel_sym (struct disassemble_info *info) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + /* 10: 0000 nop! + 4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab. + FIXME: the space number is not accurate. */ + func (stream, "%s", " ||\n \t \t"); +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + given &= 0xffff; + for (insn = score_opcodes; insn->assembler; insn++) + { + if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + char *c = insn->assembler; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 4; + given &= 0xffff; + + for (; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + + target = (pc & 0xfffff000) | (given & 0x00000ffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 9-bit number. */ +#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100) + int disp = (given & 0xff) << 1; + int target = (pc + SEXT9 (disp)); + + (*info->print_address_func) (target, info); + } + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + switch (*c) + { + case 'R': + func (stream, "%s", score_regnames[reg + 16]); + break; + case 'r': + func (stream, "%s", score_regnames[reg]); + break; + case 'd': + if (*(c + 1) == '\0') + func (stream, "%ld", reg); + else + { + c++; + if (*c == '1') + func (stream, "%ld", reg << 1); + else if (*c == '2') + func (stream, "%ld", reg << 2); + } + break; + + case 'x': + if (*(c + 1) == '\0') + func (stream, "%lx", reg); + else + { + c++; + if (*c == '1') + func (stream, "%lx", reg << 1); + else if (*c == '2') + func (stream, "%lx", reg << 2); + } + break; + case 'i': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%ld", reg); + break; + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + } + break; + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + return 2; + } + } +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("")); + return 2; +#endif + /* No match. */ + abort (); +} + +/*****************************************************************************/ +/* s3_s7: exported functions. */ + +/* NOTE: There are no checks in these routines that + the relevant number of data bytes exist. */ +int +s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) +{ + unsigned char b[4]; + long given; + long ridparity; + int status; + bfd_boolean insn_pce_p = FALSE; + bfd_boolean insn_16_p = FALSE; + + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + + if (pc & 0x2) + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + insn_16_p = TRUE; + } + else + { + info->bytes_per_chunk = 4; + status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); + if (status != 0) + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + insn_16_p = TRUE; + } + } + + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + + if (little) + { + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + } + else + { + given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); + } + + if ((given & 0x80008000) == 0x80008000) + { + insn_pce_p = FALSE; + insn_16_p = FALSE; + } + else if ((given & 0x8000) == 0x8000) + { + insn_pce_p = TRUE; + } + else + { + insn_16_p = TRUE; + } + + /* 16 bit instruction. */ + if (insn_16_p) + { + if (little) + { + given = b[0] | (b[1] << 8); + } + else + { + given = (b[0] << 8) | b[1]; + } + + status = print_insn_score16 (pc, info, given); + } + /* pce instruction. */ + else if (insn_pce_p) + { + long other; + + other = given & 0xFFFF; + given = (given & 0xFFFF0000) >> 16; + + status = print_insn_score16 (pc, info, given); + print_insn_parallel_sym (info); + status += print_insn_score16 (pc, info, other); + /* disassemble_bytes() will output 4 byte per chunk for pce instructio. */ + info->bytes_per_chunk = 4; + } + /* 32 bit instruction. */ + else + { + /* Get rid of parity. */ + ridparity = (given & 0x7FFF); + ridparity |= (given & 0x7FFF0000) >> 1; + given = ridparity; + status = print_insn_score32 (pc, info, given); + } + + return status; +} + +/*****************************************************************************/ diff --git a/external/gpl3/gdb/dist/opcodes/sh-dis.c b/external/gpl3/gdb/dist/opcodes/sh-dis.c new file mode 100644 index 000000000000..76d123334200 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sh-dis.c @@ -0,0 +1,944 @@ +/* Disassemble SH instructions. + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005, + 2006, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "sh-opc.h" +#include "dis-asm.h" + +#ifdef ARCH_all +#define INCLUDE_SHMEDIA +#endif + +static void +print_movxy (const sh_opcode_info *op, + int rn, + int rm, + fprintf_ftype fprintf_fn, + void *stream) +{ + int n; + + fprintf_fn (stream, "%s\t", op->name); + for (n = 0; n < 2; n++) + { + switch (op->arg[n]) + { + case A_IND_N: + case AX_IND_N: + case AXY_IND_N: + case AY_IND_N: + case AYX_IND_N: + fprintf_fn (stream, "@r%d", rn); + break; + case A_INC_N: + case AX_INC_N: + case AXY_INC_N: + case AY_INC_N: + case AYX_INC_N: + fprintf_fn (stream, "@r%d+", rn); + break; + case AX_PMOD_N: + case AXY_PMOD_N: + fprintf_fn (stream, "@r%d+r8", rn); + break; + case AY_PMOD_N: + case AYX_PMOD_N: + fprintf_fn (stream, "@r%d+r9", rn); + break; + case DSP_REG_A_M: + fprintf_fn (stream, "a%c", '0' + rm); + break; + case DSP_REG_X: + fprintf_fn (stream, "x%c", '0' + rm); + break; + case DSP_REG_Y: + fprintf_fn (stream, "y%c", '0' + rm); + break; + case DSP_REG_AX: + fprintf_fn (stream, "%c%c", + (rm & 1) ? 'x' : 'a', + (rm & 2) ? '1' : '0'); + break; + case DSP_REG_XY: + fprintf_fn (stream, "%c%c", + (rm & 1) ? 'y' : 'x', + (rm & 2) ? '1' : '0'); + break; + case DSP_REG_AY: + fprintf_fn (stream, "%c%c", + (rm & 2) ? 'y' : 'a', + (rm & 1) ? '1' : '0'); + break; + case DSP_REG_YX: + fprintf_fn (stream, "%c%c", + (rm & 2) ? 'x' : 'y', + (rm & 1) ? '1' : '0'); + break; + default: + abort (); + } + if (n == 0) + fprintf_fn (stream, ","); + } +} + +/* Print a double data transfer insn. INSN is just the lower three + nibbles of the insn, i.e. field a and the bit that indicates if + a parallel processing insn follows. + Return nonzero if a field b of a parallel processing insns follows. */ + +static void +print_insn_ddt (int insn, struct disassemble_info *info) +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + + /* If this is just a nop, make sure to emit something. */ + if (insn == 0x000) + fprintf_fn (stream, "nopx\tnopy"); + + /* If a parallel processing insn was printed before, + and we got a non-nop, emit a tab. */ + if ((insn & 0x800) && (insn & 0x3ff)) + fprintf_fn (stream, "\t"); + + /* Check if either the x or y part is invalid. */ + if (((insn & 0xc) == 0 && (insn & 0x2a0)) + || ((insn & 3) == 0 && (insn & 0x150))) + if (info->mach != bfd_mach_sh_dsp + && info->mach != bfd_mach_sh3_dsp) + { + static const sh_opcode_info *first_movx, *first_movy; + const sh_opcode_info *op; + int is_movy; + + if (! first_movx) + { + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) + first_movx++; + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) + first_movy++; + } + + is_movy = ((insn & 3) != 0); + + if (is_movy) + op = first_movy; + else + op = first_movx; + + while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) + || op->nibbles[3] != (unsigned) (insn & 0xf)) + op++; + + print_movxy (op, + (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0) + + 2 * is_movy + + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)), + (insn >> 6) & 3, + fprintf_fn, stream); + } + else + fprintf_fn (stream, ".word 0x%x", insn); + else + { + static const sh_opcode_info *first_movx, *first_movy; + const sh_opcode_info *opx, *opy; + unsigned int insn_x, insn_y; + + if (! first_movx) + { + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) + first_movx++; + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) + first_movy++; + } + insn_x = (insn >> 2) & 0xb; + if (insn_x) + { + for (opx = first_movx; opx->nibbles[2] != insn_x;) + opx++; + print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, + fprintf_fn, stream); + } + insn_y = (insn & 3) | ((insn >> 1) & 8); + if (insn_y) + { + if (insn_x) + fprintf_fn (stream, "\t"); + for (opy = first_movy; opy->nibbles[2] != insn_y;) + opy++; + print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, + fprintf_fn, stream); + } + } +} + +static void +print_dsp_reg (int rm, fprintf_ftype fprintf_fn, void *stream) +{ + switch (rm) + { + case A_A1_NUM: + fprintf_fn (stream, "a1"); + break; + case A_A0_NUM: + fprintf_fn (stream, "a0"); + break; + case A_X0_NUM: + fprintf_fn (stream, "x0"); + break; + case A_X1_NUM: + fprintf_fn (stream, "x1"); + break; + case A_Y0_NUM: + fprintf_fn (stream, "y0"); + break; + case A_Y1_NUM: + fprintf_fn (stream, "y1"); + break; + case A_M0_NUM: + fprintf_fn (stream, "m0"); + break; + case A_A1G_NUM: + fprintf_fn (stream, "a1g"); + break; + case A_M1_NUM: + fprintf_fn (stream, "m1"); + break; + case A_A0G_NUM: + fprintf_fn (stream, "a0g"); + break; + default: + fprintf_fn (stream, "0x%x", rm); + break; + } +} + +static void +print_insn_ppi (int field_b, struct disassemble_info *info) +{ + static char *sx_tab[] = { "x0", "x1", "a0", "a1" }; + static char *sy_tab[] = { "y0", "y1", "m0", "m1" }; + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned int nib1, nib2, nib3; + unsigned int altnib1, nib4; + char *dc = NULL; + const sh_opcode_info *op; + + if ((field_b & 0xe800) == 0) + { + fprintf_fn (stream, "psh%c\t#%d,", + field_b & 0x1000 ? 'a' : 'l', + (field_b >> 4) & 127); + print_dsp_reg (field_b & 0xf, fprintf_fn, stream); + return; + } + if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) + { + static char *du_tab[] = { "x0", "y0", "a0", "a1" }; + static char *se_tab[] = { "x0", "x1", "y0", "a1" }; + static char *sf_tab[] = { "y0", "y1", "x0", "a1" }; + static char *sg_tab[] = { "m0", "m1", "a0", "a1" }; + + if (field_b & 0x2000) + fprintf_fn (stream, "p%s %s,%s,%s\t", + (field_b & 0x1000) ? "add" : "sub", + sx_tab[(field_b >> 6) & 3], + sy_tab[(field_b >> 4) & 3], + du_tab[(field_b >> 0) & 3]); + + else if ((field_b & 0xf0) == 0x10 + && info->mach != bfd_mach_sh_dsp + && info->mach != bfd_mach_sh3_dsp) + fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); + + else if ((field_b & 0xf3) != 0) + fprintf_fn (stream, ".word 0x%x\t", field_b); + + fprintf_fn (stream, "pmuls%c%s,%s,%s", + field_b & 0x2000 ? ' ' : '\t', + se_tab[(field_b >> 10) & 3], + sf_tab[(field_b >> 8) & 3], + sg_tab[(field_b >> 2) & 3]); + return; + } + + nib1 = PPIC; + nib2 = field_b >> 12 & 0xf; + nib3 = field_b >> 8 & 0xf; + nib4 = field_b >> 4 & 0xf; + switch (nib3 & 0x3) + { + case 0: + dc = ""; + nib1 = PPI3; + break; + case 1: + dc = ""; + break; + case 2: + dc = "dct "; + nib3 -= 1; + break; + case 3: + dc = "dcf "; + nib3 -= 2; + break; + } + if (nib1 == PPI3) + altnib1 = PPI3NC; + else + altnib1 = nib1; + for (op = sh_table; op->name; op++) + { + if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) + && op->nibbles[2] == nib2 + && op->nibbles[3] == nib3) + { + int n; + + switch (op->nibbles[4]) + { + case HEX_0: + break; + case HEX_XX00: + if ((nib4 & 3) != 0) + continue; + break; + case HEX_1: + if ((nib4 & 3) != 1) + continue; + break; + case HEX_00YY: + if ((nib4 & 0xc) != 0) + continue; + break; + case HEX_4: + if ((nib4 & 0xc) != 4) + continue; + break; + default: + abort (); + } + fprintf_fn (stream, "%s%s\t", dc, op->name); + for (n = 0; n < 3 && op->arg[n] != A_END; n++) + { + if (n && op->arg[1] != A_END) + fprintf_fn (stream, ","); + switch (op->arg[n]) + { + case DSP_REG_N: + print_dsp_reg (field_b & 0xf, fprintf_fn, stream); + break; + case DSP_REG_X: + fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); + break; + case DSP_REG_Y: + fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); + break; + case A_MACH: + fprintf_fn (stream, "mach"); + break; + case A_MACL: + fprintf_fn (stream, "macl"); + break; + default: + abort (); + } + } + return; + } + } + /* Not found. */ + fprintf_fn (stream, ".word 0x%x", field_b); +} + +/* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff + (ie. the upper nibble is missing). */ + +int +print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned char insn[4]; + unsigned char nibs[8]; + int status; + bfd_vma relmask = ~(bfd_vma) 0; + const sh_opcode_info *op; + unsigned int target_arch; + int allow_op32; + + switch (info->mach) + { + case bfd_mach_sh: + target_arch = arch_sh1; + /* SH coff object files lack information about the machine type, so + we end up with bfd_mach_sh unless it was set explicitly (which + could have happended if this is a call from gdb or the simulator.) */ + if (info->symbols + && bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour) + target_arch = arch_sh4; + break; + case bfd_mach_sh5: +#ifdef INCLUDE_SHMEDIA + status = print_insn_sh64 (memaddr, info); + if (status != -2) + return status; +#endif + /* When we get here for sh64, it's because we want to disassemble + SHcompact, i.e. arch_sh4. */ + target_arch = arch_sh4; + break; + default: + target_arch = sh_get_arch_from_bfd_mach (info->mach); + } + + status = info->read_memory_func (memaddr, insn, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + { + nibs[0] = (insn[1] >> 4) & 0xf; + nibs[1] = insn[1] & 0xf; + + nibs[2] = (insn[0] >> 4) & 0xf; + nibs[3] = insn[0] & 0xf; + } + else + { + nibs[0] = (insn[0] >> 4) & 0xf; + nibs[1] = insn[0] & 0xf; + + nibs[2] = (insn[1] >> 4) & 0xf; + nibs[3] = insn[1] & 0xf; + } + status = info->read_memory_func (memaddr + 2, insn + 2, 2, info); + if (status != 0) + allow_op32 = 0; + else + { + allow_op32 = 1; + + if (info->endian == BFD_ENDIAN_LITTLE) + { + nibs[4] = (insn[3] >> 4) & 0xf; + nibs[5] = insn[3] & 0xf; + + nibs[6] = (insn[2] >> 4) & 0xf; + nibs[7] = insn[2] & 0xf; + } + else + { + nibs[4] = (insn[2] >> 4) & 0xf; + nibs[5] = insn[2] & 0xf; + + nibs[6] = (insn[3] >> 4) & 0xf; + nibs[7] = insn[3] & 0xf; + } + } + + if (nibs[0] == 0xf && (nibs[1] & 4) == 0 + && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up)) + { + if (nibs[1] & 8) + { + int field_b; + + status = info->read_memory_func (memaddr + 2, insn, 2, info); + + if (status != 0) + { + info->memory_error_func (status, memaddr + 2, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_LITTLE) + field_b = insn[1] << 8 | insn[0]; + else + field_b = insn[0] << 8 | insn[1]; + + print_insn_ppi (field_b, info); + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); + return 4; + } + print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); + return 2; + } + for (op = sh_table; op->name; op++) + { + int n; + int imm = 0; + int rn = 0; + int rm = 0; + int rb = 0; + int disp_pc; + bfd_vma disp_pc_addr = 0; + int disp = 0; + int has_disp = 0; + int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4; + + if (!allow_op32 + && SH_MERGE_ARCH_SET (op->arch, arch_op32)) + goto fail; + + if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch)) + goto fail; + for (n = 0; n < max_n; n++) + { + int i = op->nibbles[n]; + + if (i < 16) + { + if (nibs[n] == i) + continue; + goto fail; + } + switch (i) + { + case BRANCH_8: + imm = (nibs[2] << 4) | (nibs[3]); + if (imm & 0x80) + imm |= ~0xff; + imm = ((char) imm) * 2 + 4; + goto ok; + case BRANCH_12: + imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); + if (imm & 0x800) + imm |= ~0xfff; + imm = imm * 2 + 4; + goto ok; + case IMM0_3c: + if (nibs[3] & 0x8) + goto fail; + imm = nibs[3] & 0x7; + break; + case IMM0_3s: + if (!(nibs[3] & 0x8)) + goto fail; + imm = nibs[3] & 0x7; + break; + case IMM0_3Uc: + if (nibs[2] & 0x8) + goto fail; + imm = nibs[2] & 0x7; + break; + case IMM0_3Us: + if (!(nibs[2] & 0x8)) + goto fail; + imm = nibs[2] & 0x7; + break; + case DISP0_12: + case DISP1_12: + disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7]; + has_disp = 1; + goto ok; + case DISP0_12BY2: + case DISP1_12BY2: + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1; + relmask = ~(bfd_vma) 1; + has_disp = 1; + goto ok; + case DISP0_12BY4: + case DISP1_12BY4: + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2; + relmask = ~(bfd_vma) 3; + has_disp = 1; + goto ok; + case DISP0_12BY8: + case DISP1_12BY8: + disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3; + relmask = ~(bfd_vma) 7; + has_disp = 1; + goto ok; + case IMM0_20_4: + break; + case IMM0_20: + imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) + | (nibs[6] << 4) | nibs[7]); + if (imm & 0x80000) + imm -= 0x100000; + goto ok; + case IMM0_20BY8: + imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) + | (nibs[6] << 4) | nibs[7]); + imm <<= 8; + if (imm & 0x8000000) + imm -= 0x10000000; + goto ok; + case IMM0_4: + case IMM1_4: + imm = nibs[3]; + goto ok; + case IMM0_4BY2: + case IMM1_4BY2: + imm = nibs[3] << 1; + goto ok; + case IMM0_4BY4: + case IMM1_4BY4: + imm = nibs[3] << 2; + goto ok; + case IMM0_8: + case IMM1_8: + imm = (nibs[2] << 4) | nibs[3]; + disp = imm; + has_disp = 1; + if (imm & 0x80) + imm -= 0x100; + goto ok; + case PCRELIMM_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) << 1; + relmask = ~(bfd_vma) 1; + goto ok; + case PCRELIMM_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) << 2; + relmask = ~(bfd_vma) 3; + goto ok; + case IMM0_8BY2: + case IMM1_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) << 1; + goto ok; + case IMM0_8BY4: + case IMM1_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) << 2; + goto ok; + case REG_N_D: + if ((nibs[n] & 1) != 0) + goto fail; + /* Fall through. */ + case REG_N: + rn = nibs[n]; + break; + case REG_M: + rm = nibs[n]; + break; + case REG_N_B01: + if ((nibs[n] & 0x3) != 1 /* binary 01 */) + goto fail; + rn = (nibs[n] & 0xc) >> 2; + break; + case REG_NM: + rn = (nibs[n] & 0xc) >> 2; + rm = (nibs[n] & 0x3); + break; + case REG_B: + rb = nibs[n] & 0x07; + break; + case SDT_REG_N: + /* sh-dsp: single data transfer. */ + rn = nibs[n]; + if ((rn & 0xc) != 4) + goto fail; + rn = rn & 0x3; + rn |= (!(rn & 2)) << 2; + break; + case PPI: + case REPEAT: + goto fail; + default: + abort (); + } + } + + ok: + /* sh2a has D_REG but not X_REG. We don't know the pattern + doesn't match unless we check the output args to see if they + make sense. */ + if (target_arch == arch_sh2a + && ((op->arg[0] == DX_REG_M && (rm & 1) != 0) + || (op->arg[1] == DX_REG_N && (rn & 1) != 0))) + goto fail; + + fprintf_fn (stream, "%s\t", op->name); + disp_pc = 0; + for (n = 0; n < 3 && op->arg[n] != A_END; n++) + { + if (n && op->arg[1] != A_END) + fprintf_fn (stream, ","); + switch (op->arg[n]) + { + case A_IMM: + fprintf_fn (stream, "#%d", imm); + break; + case A_R0: + fprintf_fn (stream, "r0"); + break; + case A_REG_N: + fprintf_fn (stream, "r%d", rn); + break; + case A_INC_N: + case AS_INC_N: + fprintf_fn (stream, "@r%d+", rn); + break; + case A_DEC_N: + case AS_DEC_N: + fprintf_fn (stream, "@-r%d", rn); + break; + case A_IND_N: + case AS_IND_N: + fprintf_fn (stream, "@r%d", rn); + break; + case A_DISP_REG_N: + fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn); + break; + case AS_PMOD_N: + fprintf_fn (stream, "@r%d+r8", rn); + break; + case A_REG_M: + fprintf_fn (stream, "r%d", rm); + break; + case A_INC_M: + fprintf_fn (stream, "@r%d+", rm); + break; + case A_DEC_M: + fprintf_fn (stream, "@-r%d", rm); + break; + case A_IND_M: + fprintf_fn (stream, "@r%d", rm); + break; + case A_DISP_REG_M: + fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm); + break; + case A_REG_B: + fprintf_fn (stream, "r%d_bank", rb); + break; + case A_DISP_PC: + disp_pc = 1; + disp_pc_addr = imm + 4 + (memaddr & relmask); + (*info->print_address_func) (disp_pc_addr, info); + break; + case A_IND_R0_REG_N: + fprintf_fn (stream, "@(r0,r%d)", rn); + break; + case A_IND_R0_REG_M: + fprintf_fn (stream, "@(r0,r%d)", rm); + break; + case A_DISP_GBR: + fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm); + break; + case A_TBR: + fprintf_fn (stream, "tbr"); + break; + case A_DISP2_TBR: + fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm); + break; + case A_INC_R15: + fprintf_fn (stream, "@r15+"); + break; + case A_DEC_R15: + fprintf_fn (stream, "@-r15"); + break; + case A_R0_GBR: + fprintf_fn (stream, "@(r0,gbr)"); + break; + case A_BDISP12: + case A_BDISP8: + (*info->print_address_func) (imm + memaddr, info); + break; + case A_SR: + fprintf_fn (stream, "sr"); + break; + case A_GBR: + fprintf_fn (stream, "gbr"); + break; + case A_VBR: + fprintf_fn (stream, "vbr"); + break; + case A_DSR: + fprintf_fn (stream, "dsr"); + break; + case A_MOD: + fprintf_fn (stream, "mod"); + break; + case A_RE: + fprintf_fn (stream, "re"); + break; + case A_RS: + fprintf_fn (stream, "rs"); + break; + case A_A0: + fprintf_fn (stream, "a0"); + break; + case A_X0: + fprintf_fn (stream, "x0"); + break; + case A_X1: + fprintf_fn (stream, "x1"); + break; + case A_Y0: + fprintf_fn (stream, "y0"); + break; + case A_Y1: + fprintf_fn (stream, "y1"); + break; + case DSP_REG_M: + print_dsp_reg (rm, fprintf_fn, stream); + break; + case A_SSR: + fprintf_fn (stream, "ssr"); + break; + case A_SPC: + fprintf_fn (stream, "spc"); + break; + case A_MACH: + fprintf_fn (stream, "mach"); + break; + case A_MACL: + fprintf_fn (stream, "macl"); + break; + case A_PR: + fprintf_fn (stream, "pr"); + break; + case A_SGR: + fprintf_fn (stream, "sgr"); + break; + case A_DBR: + fprintf_fn (stream, "dbr"); + break; + case F_REG_N: + fprintf_fn (stream, "fr%d", rn); + break; + case F_REG_M: + fprintf_fn (stream, "fr%d", rm); + break; + case DX_REG_N: + if (rn & 1) + { + fprintf_fn (stream, "xd%d", rn & ~1); + break; + } + case D_REG_N: + fprintf_fn (stream, "dr%d", rn); + break; + case DX_REG_M: + if (rm & 1) + { + fprintf_fn (stream, "xd%d", rm & ~1); + break; + } + case D_REG_M: + fprintf_fn (stream, "dr%d", rm); + break; + case FPSCR_M: + case FPSCR_N: + fprintf_fn (stream, "fpscr"); + break; + case FPUL_M: + case FPUL_N: + fprintf_fn (stream, "fpul"); + break; + case F_FR0: + fprintf_fn (stream, "fr0"); + break; + case V_REG_N: + fprintf_fn (stream, "fv%d", rn * 4); + break; + case V_REG_M: + fprintf_fn (stream, "fv%d", rm * 4); + break; + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; + default: + abort (); + } + } + +#if 0 + /* This code prints instructions in delay slots on the same line + as the instruction which needs the delay slots. This can be + confusing, since other disassembler don't work this way, and + it means that the instructions are not all in a line. So I + disabled it. Ian. */ + if (!(info->flags & 1) + && (op->name[0] == 'j' + || (op->name[0] == 'b' + && (op->name[1] == 'r' + || op->name[1] == 's')) + || (op->name[0] == 'r' && op->name[1] == 't') + || (op->name[0] == 'b' && op->name[2] == '.'))) + { + info->flags |= 1; + fprintf_fn (stream, "\t(slot "); + print_insn_sh (memaddr + 2, info); + info->flags &= ~1; + fprintf_fn (stream, ")"); + return 4; + } +#endif + + if (disp_pc && strcmp (op->name, "mova") != 0) + { + int size; + bfd_byte bytes[4]; + + if (relmask == ~(bfd_vma) 1) + size = 2; + else + size = 4; + status = info->read_memory_func (disp_pc_addr, bytes, size, info); + if (status == 0) + { + unsigned int val; + + if (size == 2) + { + if (info->endian == BFD_ENDIAN_LITTLE) + val = bfd_getl16 (bytes); + else + val = bfd_getb16 (bytes); + } + else + { + if (info->endian == BFD_ENDIAN_LITTLE) + val = bfd_getl32 (bytes); + else + val = bfd_getb32 (bytes); + } + if ((*info->symbol_at_address_func) (val, info)) + { + fprintf_fn (stream, "\t! "); + (*info->print_address_func) (val, info); + } + else + fprintf_fn (stream, "\t! %x", val); + } + } + + return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2; + fail: + ; + + } + fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); + return 2; +} diff --git a/external/gpl3/gdb/dist/opcodes/sh-opc.h b/external/gpl3/gdb/dist/opcodes/sh-opc.h new file mode 100644 index 000000000000..62e290e3bc1c --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sh-opc.h @@ -0,0 +1,1201 @@ +/* Definitions for SH opcodes. + Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2002, 2003, 2004, + 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "bfd.h" + +typedef enum + { + HEX_0, + HEX_1, + HEX_2, + HEX_3, + HEX_4, + HEX_5, + HEX_6, + HEX_7, + HEX_8, + HEX_9, + HEX_A, + HEX_B, + HEX_C, + HEX_D, + HEX_E, + HEX_F, + HEX_XX00, + HEX_00YY, + REG_N, + REG_N_D, /* nnn0 */ + REG_N_B01, /* nn01 */ + REG_M, + SDT_REG_N, + REG_NM, + REG_B, + BRANCH_12, + BRANCH_8, + IMM0_4, + IMM0_4BY2, + IMM0_4BY4, + IMM1_4, + IMM1_4BY2, + IMM1_4BY4, + PCRELIMM_8BY2, + PCRELIMM_8BY4, + IMM0_8, + IMM0_8BY2, + IMM0_8BY4, + IMM1_8, + IMM1_8BY2, + IMM1_8BY4, + PPI, + NOPX, + NOPY, + MOVX, + MOVY, + MOVX_NOPY, + MOVY_NOPX, + PSH, + PMUL, + PPI3, + PPI3NC, + PDC, + PPIC, + REPEAT, + IMM0_3c, /* xxxx 0iii */ + IMM0_3s, /* xxxx 1iii */ + IMM0_3Uc, /* 0iii xxxx */ + IMM0_3Us, /* 1iii xxxx */ + IMM0_20_4, + IMM0_20, /* follows IMM0_20_4 */ + IMM0_20BY8, /* follows IMM0_20_4 */ + DISP0_12, + DISP0_12BY2, + DISP0_12BY4, + DISP0_12BY8, + DISP1_12, + DISP1_12BY2, + DISP1_12BY4, + DISP1_12BY8 + } +sh_nibble_type; + +typedef enum + { + A_END, + A_BDISP12, + A_BDISP8, + A_DEC_M, + A_DEC_N, + A_DISP_GBR, + A_PC, + A_DISP_PC, + A_DISP_PC_ABS, + A_DISP_REG_M, + A_DISP_REG_N, + A_GBR, + A_IMM, + A_INC_M, + A_INC_N, + A_IND_M, + A_IND_N, + A_IND_R0_REG_M, + A_IND_R0_REG_N, + A_MACH, + A_MACL, + A_PR, + A_R0, + A_R0_GBR, + A_REG_M, + A_REG_N, + A_REG_B, + A_SR, + A_VBR, + A_TBR, + A_DISP_TBR, + A_DISP2_TBR, + A_DEC_R15, + A_INC_R15, + A_MOD, + A_RE, + A_RS, + A_DSR, + DSP_REG_M, + DSP_REG_N, + DSP_REG_X, + DSP_REG_Y, + DSP_REG_E, + DSP_REG_F, + DSP_REG_G, + DSP_REG_A_M, + DSP_REG_AX, + DSP_REG_XY, + DSP_REG_AY, + DSP_REG_YX, + AX_INC_N, + AY_INC_N, + AXY_INC_N, + AYX_INC_N, + AX_IND_N, + AY_IND_N, + AXY_IND_N, + AYX_IND_N, + AX_PMOD_N, + AXY_PMOD_N, + AY_PMOD_N, + AYX_PMOD_N, + AS_DEC_N, + AS_INC_N, + AS_IND_N, + AS_PMOD_N, + A_A0, + A_X0, + A_X1, + A_Y0, + A_Y1, + A_SSR, + A_SPC, + A_SGR, + A_DBR, + F_REG_N, + F_REG_M, + D_REG_N, + D_REG_M, + X_REG_N, /* Only used for argument parsing. */ + X_REG_M, /* Only used for argument parsing. */ + DX_REG_N, + DX_REG_M, + V_REG_N, + V_REG_M, + XMTRX_M4, + F_FR0, + FPUL_N, + FPUL_M, + FPSCR_N, + FPSCR_M + } +sh_arg_type; + +typedef enum + { + A_A1_NUM = 5, + A_A0_NUM = 7, + A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, + A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM + } +sh_dsp_reg_nums; + +/* Return a mask with bits LO to HI (inclusive) set. */ +#define MASK(LO,HI) ( LO < 1 ? ((1 << (HI + 1)) - 1) \ + : HI > 30 ? (-1 << LO) \ + : LO == HI ? (1 << LO) \ + : (((1 << (HI + 1)) - 1) & (-1 << LO))) + +#define arch_sh1_base (1 << 0) +#define arch_sh2_base (1 << 1) +#define arch_sh2a_sh3_base (1 << 2) +#define arch_sh3_base (1 << 3) +#define arch_sh2a_sh4_base (1 << 4) +#define arch_sh4_base (1 << 5) +#define arch_sh4a_base (1 << 6) +#define arch_sh2a_base (1 << 7) +#define arch_sh_base_mask MASK (0, 7) + +/* Bits 8 ... 24 are currently free. */ + +/* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +#define arch_op32 (1 << 25) /* This is a 32-bit opcode. */ +#define arch_opann_mask MASK (25, 25) + +#define arch_sh_no_mmu (1 << 26) +#define arch_sh_has_mmu (1 << 27) +#define arch_sh_mmu_mask MASK (26, 27) + +#define arch_sh_no_co (1 << 28) /* Neither FPU nor DSP co-processor. */ +#define arch_sh_sp_fpu (1 << 29) /* Single precision FPU. */ +#define arch_sh_dp_fpu (1 << 30) /* Double precision FPU. */ +#define arch_sh_has_dsp (1 << 31) +#define arch_sh_co_mask MASK (28, 31) + + +#define arch_sh1 (arch_sh1_base |arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2 (arch_sh2_base |arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2a (arch_sh2a_base |arch_sh_no_mmu |arch_sh_dp_fpu) +#define arch_sh2a_nofpu (arch_sh2a_base |arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2e (arch_sh2_base |arch_sh_no_mmu |arch_sh_sp_fpu) +#define arch_sh_dsp (arch_sh2_base |arch_sh_no_mmu |arch_sh_has_dsp) +#define arch_sh3_nommu (arch_sh3_base |arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh3 (arch_sh3_base |arch_sh_has_mmu|arch_sh_no_co) +#define arch_sh3e (arch_sh3_base |arch_sh_has_mmu|arch_sh_sp_fpu) +#define arch_sh3_dsp (arch_sh3_base |arch_sh_has_mmu|arch_sh_has_dsp) +#define arch_sh4 (arch_sh4_base |arch_sh_has_mmu|arch_sh_dp_fpu) +#define arch_sh4a (arch_sh4a_base |arch_sh_has_mmu|arch_sh_dp_fpu) +#define arch_sh4al_dsp (arch_sh4a_base |arch_sh_has_mmu|arch_sh_has_dsp) +#define arch_sh4_nofpu (arch_sh4_base |arch_sh_has_mmu|arch_sh_no_co) +#define arch_sh4a_nofpu (arch_sh4a_base |arch_sh_has_mmu|arch_sh_no_co) +#define arch_sh4_nommu_nofpu (arch_sh4_base |arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) +#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) +#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) + +#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) +#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +#define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0) +#define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0) +#define SH_VALID_ARCH_SET(SET) \ + (SH_VALID_BASE_ARCH_SET (SET) \ + && SH_VALID_MMU_ARCH_SET (SET) \ + && SH_VALID_CO_ARCH_SET (SET)) +#define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \ + SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2)) + +#define SH_ARCH_SET_HAS_FPU(SET) \ + (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0) +#define SH_ARCH_SET_HAS_DSP(SET) \ + (((SET) & arch_sh_has_dsp) != 0) + +/* This is returned from the functions below when an error occurs + (in addition to a call to BFD_FAIL). The value should allow + the tools to continue to function in most cases - there may + be some confusion between DSP and FPU etc. */ +#define SH_ARCH_UNKNOWN_ARCH 0xffffffff + +/* These are defined in bfd/cpu-sh.c . */ +unsigned int sh_get_arch_from_bfd_mach (unsigned long mach); +unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach); +unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set); +bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); + +/* Below are the 'architecture sets'. + They describe the following inheritance graph: + + SH1 + | + SH2 + .------------'|`--------------------------------. + / | \ +SH-DSP SH3-nommu/SH2A-nofpu SH2E + | | |`--------------------. | + | | | \| + | SH3-nommu SH4-nm-nf/SH2A-nofpu SH3E/SH2A + | |\ | | \ | | + | | `------. | SH2A-nofpu `----+---.| + | | \| \ | SH4/SH2A + | SH3 SH4-nommu-nofpu `---------+--. | | + | /|\ | | \| | + | .-----------' | `--------+---------------------. | SH2A | + |/ | / \| | + | | .-------' | | + | |/ | | +SH3-dsp SH4-nofpu SH3E | + | |`-------------------------------. | .-----' + | | \|/ + | SH4A-nofpu SH4 + | .------------' `-------------------------------. | + |/ \| +SH4AL-dsp SH4A +*/ + +/* Central branches. */ +#define arch_sh_up (arch_sh1 \ + | arch_sh2_up) +#define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ + | arch_sh_dsp_up) +#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ + | arch_sh3_nommu_up) +#define arch_sh2a_nofpu_or_sh4_nommu_nofpu_up (arch_sh2a_nofpu_or_sh4_nommu_nofpu \ + | arch_sh2a_nofpu_up \ + | arch_sh2a_or_sh4_up \ + | arch_sh4_nommu_nofpu_up) +#define arch_sh2a_nofpu_up (arch_sh2a_nofpu \ + | arch_sh2a_up) +#define arch_sh3_nommu_up (arch_sh3_nommu \ + | arch_sh3_up \ + | arch_sh4_nommu_nofpu_up) +#define arch_sh3_up (arch_sh3 \ + | arch_sh3e_up \ + | arch_sh3_dsp_up \ + | arch_sh4_nofpu_up) +#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu \ + | arch_sh4_nofpu_up) +#define arch_sh4_nofpu_up (arch_sh4_nofpu \ + | arch_sh4_up \ + | arch_sh4a_nofpu_up) +#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) + +/* Right branches. */ +#define arch_sh2e_up (arch_sh2e \ + | arch_sh2a_or_sh3e_up) +#define arch_sh2a_or_sh3e_up (arch_sh2a_or_sh3e \ + | arch_sh2a_or_sh4_up \ + | arch_sh3e_up) +#define arch_sh2a_or_sh4_up (arch_sh2a_or_sh4 \ + | arch_sh2a_up \ + | arch_sh4_up) +#define arch_sh2a_up (arch_sh2a) +#define arch_sh3e_up (arch_sh3e \ + | arch_sh4_up) +#define arch_sh4_up (arch_sh4 \ + | arch_sh4a_up) +#define arch_sh4a_up (arch_sh4a) + +/* Left branch. */ +#define arch_sh_dsp_up (arch_sh_dsp \ + | arch_sh3_dsp_up) +#define arch_sh3_dsp_up (arch_sh3_dsp \ + | arch_sh4al_dsp_up) +#define arch_sh4al_dsp_up (arch_sh4al_dsp) + +typedef struct +{ + char *name; + sh_arg_type arg[4]; + sh_nibble_type nibbles[9]; + unsigned int arch; +} sh_opcode_info; + +#ifdef DEFINE_TABLE + +const sh_opcode_info sh_table[] = + { +/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}, + +/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}, + +/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}, + +/* 0011nnnnmmmm1111 addv ,*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}, + +/* 11001001i8*1.... and #,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}, + +/* 0010nnnnmmmm1001 and , */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}, + +/* 11001101i8*1.... and.b #,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}, + +/* 1010i12......... bra */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}, + +/* 1011i12......... bsr */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}, + +/* 10001001i8p1.... bt */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}, + +/* 10001011i8p1.... bf */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}, + +/* 10001101i8p1.... bt.s */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, + +/* 10001101i8p1.... bt/s */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, + +/* 10001111i8p1.... bf.s */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, + +/* 10001111i8p1.... bf/s */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, + +/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}, + +/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}, + +/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}, + +/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}, + +/* 10001000i8*1.... cmp/eq #,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}, + +/* 0011nnnnmmmm0000 cmp/eq ,*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}, + +/* 0011nnnnmmmm0011 cmp/ge ,*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}, + +/* 0011nnnnmmmm0111 cmp/gt ,*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}, + +/* 0011nnnnmmmm0110 cmp/hi ,*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}, + +/* 0011nnnnmmmm0010 cmp/hs ,*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}, + +/* 0100nnnn00010101 cmp/pl */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}, + +/* 0100nnnn00010001 cmp/pz */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}, + +/* 0010nnnnmmmm1100 cmp/str ,*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}, + +/* 0010nnnnmmmm0111 div0s ,*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}, + +/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}, + +/* 0011nnnnmmmm0100 div1 ,*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}, + +/* 0110nnnnmmmm1110 exts.b ,*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}, + +/* 0110nnnnmmmm1111 exts.w ,*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}, + +/* 0110nnnnmmmm1100 extu.b ,*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}, + +/* 0110nnnnmmmm1101 extu.w ,*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}, + +/* 0000nnnn11100011 icbi @ */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}, + +/* 0100nnnn00101011 jmp @ */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}, + +/* 0100nnnn00001011 jsr @ */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}, + +/* 0100nnnn00001110 ldc ,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}, + +/* 0100nnnn00011110 ldc ,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}, + +/* 0100nnnn00111010 ldc ,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, + +/* 0100mmmm01001010 ldc ,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, + +/* 0100nnnn00101110 ldc ,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}, + +/* 0100nnnn01011110 ldc ,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn01111110 ldc ,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn01101110 ldc ,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, + +/* 0100nnnn00111110 ldc ,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}, + +/* 0100nnnn01001110 ldc ,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}, + +/* 0100nnnn11111010 ldc ,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, + +/* 0100nnnn1xxx1110 ldc ,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}, + +/* 0100nnnn00000111 ldc.l @+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}, + +/* 0100nnnn00010111 ldc.l @+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}, + +/* 0100nnnn00100111 ldc.l @+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}, + +/* 0100nnnn00110110 ldc.l @+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}, + +/* 0100nnnn01010111 ldc.l @+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn01110111 ldc.l @+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn01100111 ldc.l @+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, + +/* 0100nnnn00110111 ldc.l @+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}, + +/* 0100nnnn01000111 ldc.l @+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}, + +/* 0100nnnn11110110 ldc.l @+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}, + +/* 0100nnnn1xxx0111 ldc.l @+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}, + +/* 0100mmmm00110100 ldrc */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, +/* 10001010i8*1.... ldrc # */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, + +/* 10001110i8p2.... ldre @(,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, + +/* 10001100i8p2.... ldrs @(,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, + +/* 0100nnnn00001010 lds ,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}, + +/* 0100nnnn00011010 lds ,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}, + +/* 0100nnnn00101010 lds ,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}, + +/* 0100nnnn01101010 lds ,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn01111010 lds ,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10001010 lds ,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10011010 lds ,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10101010 lds ,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn10111010 lds ,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, + +/* 0100nnnn01011010 lds ,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, + +/* 0100nnnn01101010 lds ,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, + +/* 0100nnnn00000110 lds.l @+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}, + +/* 0100nnnn00010110 lds.l @+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}, + +/* 0100nnnn00100110 lds.l @+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}, + +/* 0100nnnn01100110 lds.l @+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn01110110 lds.l @+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10000110 lds.l @+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10010110 lds.l @+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10100110 lds.l @+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn10110110 lds.l @+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, + +/* 0100nnnn01010110 lds.l @+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, + +/* 0100nnnn01100110 lds.l @+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, + +/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, + +/* 0100nnnnmmmm1111 mac.w @+,@+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}, + +/* 1110nnnni8*1.... mov #, */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}, + +/* 0110nnnnmmmm0011 mov , */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}, + +/* 0000nnnnmmmm0100 mov.b ,@(R0,)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}, + +/* 0010nnnnmmmm0100 mov.b ,@-*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}, + +/* 0010nnnnmmmm0000 mov.b ,@*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}, + +/* 10000100mmmmi4*1 mov.b @(,),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}, + +/* 11000100i8*1.... mov.b @(,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}, + +/* 0000nnnnmmmm1100 mov.b @(R0,),*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}, + +/* 0110nnnnmmmm0100 mov.b @+,*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}, + +/* 0110nnnnmmmm0000 mov.b @,*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}, + +/* 10000000mmmmi4*1 mov.b R0,@(,)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}, + +/* 11000000i8*1.... mov.b R0,@(,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}, + +/* 0100nnnn10001011 mov.b R0,@+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}, +/* 0100nnnn11001011 mov.b @-,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}, +/* 0011nnnnmmmm0001 0000dddddddddddd mov.b ,@(,) */ +{"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(,), */ +{"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0001nnnnmmmmi4*4 mov.l ,@(,)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}, + +/* 0000nnnnmmmm0110 mov.l ,@(R0,)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}, + +/* 0010nnnnmmmm0110 mov.l ,@-*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}, + +/* 0010nnnnmmmm0010 mov.l ,@*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}, + +/* 0101nnnnmmmmi4*4 mov.l @(,),*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}, + +/* 11000110i8*4.... mov.l @(,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}, + +/* 1101nnnni8p4.... mov.l @(,PC),*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}, + +/* 0000nnnnmmmm1110 mov.l @(R0,),*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}, + +/* 0110nnnnmmmm0110 mov.l @+,*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}, + +/* 0110nnnnmmmm0010 mov.l @,*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}, + +/* 11000010i8*4.... mov.l R0,@(,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}, + +/* 0100nnnn10101011 mov.l R0,@+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}, +/* 0100nnnn11001011 mov.l @-,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}, +/* 0011nnnnmmmm0001 0010dddddddddddd mov.l ,@(,) */ +{"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(,), */ +{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}, +/* 0000nnnnmmmm0101 mov.w ,@(R0,)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}, + +/* 0010nnnnmmmm0101 mov.w ,@-*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}, + +/* 0010nnnnmmmm0001 mov.w ,@*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}, + +/* 10000101mmmmi4*2 mov.w @(,),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}, + +/* 11000101i8*2.... mov.w @(,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}, + +/* 1001nnnni8p2.... mov.w @(,PC),*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}, + +/* 0000nnnnmmmm1101 mov.w @(R0,),*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}, + +/* 0110nnnnmmmm0101 mov.w @+,*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}, + +/* 0110nnnnmmmm0001 mov.w @,*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}, + +/* 10000001mmmmi4*2 mov.w R0,@(,)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}, + +/* 11000001i8*2.... mov.w R0,@(,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}, + +/* 0100nnnn10011011 mov.w R0,@+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}, +/* 0100nnnn11011011 mov.w @-,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}, +/* 0011nnnnmmmm0001 0001dddddddddddd mov.w ,@(,) */ +{"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(,), */ +{"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +/* 11000111i8p4.... mova @(,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}, +/* 0000nnnn11000011 movca.l R0,@ */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}, + +/* 0000nnnn01110011 movco.l r0,@ */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}, +/* 0000mmmm01100011 movli.l @,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}, + +/* 0000nnnn00101001 movt */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}, + +/* 0100mmmm10101001 movua.l @,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}, +/* 0100mmmm11101001 movua.l @+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}, + +/* 0010nnnnmmmm1111 muls.w ,*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}, +/* 0010nnnnmmmm1111 muls ,*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}, + +/* 0000nnnnmmmm0111 mul.l ,*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, + +/* 0010nnnnmmmm1110 mulu.w ,*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}, +/* 0010nnnnmmmm1110 mulu ,*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}, + +/* 0110nnnnmmmm1011 neg , */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}, + +/* 0110nnnnmmmm1010 negc ,*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}, + +/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}, + +/* 0110nnnnmmmm0111 not , */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}, +/* 0000nnnn10010011 ocbi @ */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}, + +/* 0000nnnn10100011 ocbp @ */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}, + +/* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, + + +/* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}, + +/* 0010nnnnmmmm1011 or , */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}, + +/* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}, + +/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}, + +/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}, + +/* 0100nnnn00100100 rotcl */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}, + +/* 0100nnnn00100101 rotcr */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}, + +/* 0100nnnn00000100 rotl */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}, + +/* 0100nnnn00000101 rotr */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}, + +/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}, + +/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}, + +/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, +/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, + +/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}, +/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}, + +/* 0100nnnn00010100 setrc */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, + +/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, + +/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, + +/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, + +/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, + +/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}, + +/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}, + +/* 0100nnnn00101000 shll16 */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}, + +/* 0100nnnn00001000 shll2 */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}, + +/* 0100nnnn00011000 shll8 */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}, + +/* 0100nnnn00000001 shlr */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}, + +/* 0100nnnn00101001 shlr16 */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}, + +/* 0100nnnn00001001 shlr2 */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}, + +/* 0100nnnn00011001 shlr8 */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}, + +/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}, + +/* 0000nnnn00000010 stc SR, */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}, + +/* 0000nnnn00010010 stc GBR, */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}, + +/* 0000nnnn00100010 stc VBR, */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}, + +/* 0000nnnn01010010 stc MOD, */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn01110010 stc RE, */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn01100010 stc RS, */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, + +/* 0000nnnn00110010 stc SSR, */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}, + +/* 0000nnnn01000010 stc SPC, */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}, + +/* 0000nnnn00111010 stc SGR, */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, + +/* 0000nnnn11111010 stc DBR, */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, + +/* 0000nnnn1xxx0010 stc Rn_BANK, */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}, + +/* 0000nnnn01001010 stc TBR, */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, + +/* 0100nnnn00000011 stc.l SR,@- */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}, + +/* 0100nnnn00100011 stc.l VBR,@- */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}, + +/* 0100nnnn01010011 stc.l MOD,@- */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn01110011 stc.l RE,@- */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn01100011 stc.l RS,@- */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, + +/* 0100nnnn00110011 stc.l SSR,@- */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}, + +/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}, + +/* 0100nnnn00010011 stc.l GBR,@- */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}, + +/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}, + +/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}, + +/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}, + +/* 0000nnnn00001010 sts MACH, */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}, + +/* 0000nnnn00011010 sts MACL, */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}, + +/* 0000nnnn00101010 sts PR, */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}, + +/* 0000nnnn01101010 sts DSR, */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn01111010 sts A0, */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10001010 sts X0, */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10011010 sts X1, */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10101010 sts Y0, */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn10111010 sts Y1, */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, + +/* 0000nnnn01011010 sts FPUL, */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, + +/* 0000nnnn01101010 sts FPSCR, */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, + +/* 0100nnnn00000010 sts.l MACH,@-*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}, + +/* 0100nnnn00010010 sts.l MACL,@-*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}, + +/* 0100nnnn00100010 sts.l PR,@- */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}, + +/* 0100nnnn01100110 sts.l DSR,@- */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn01110110 sts.l A0,@- */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10000110 sts.l X0,@- */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10010110 sts.l X1,@- */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10100110 sts.l Y0,@- */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn10110110 sts.l Y1,@- */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, + +/* 0100nnnn01010010 sts.l FPUL,@-*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, + +/* 0100nnnn01100010 sts.l FPSCR,@-*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, + +/* 0011nnnnmmmm1000 sub , */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}, + +/* 0011nnnnmmmm1010 subc ,*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}, + +/* 0011nnnnmmmm1011 subv ,*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}, + +/* 0110nnnnmmmm1000 swap.b ,*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}, + +/* 0110nnnnmmmm1001 swap.w ,*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}, + +/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}, + +/* 0100nnnn00011011 tas.b @ */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}, + +/* 11000011i8*1.... trapa # */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}, + +/* 11001000i8*1.... tst #,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}, + +/* 0010nnnnmmmm1000 tst , */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}, + +/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}, + +/* 11001010i8*1.... xor #,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}, + +/* 0010nnnnmmmm1010 xor , */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}, + +/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}, + +/* 0010nnnnmmmm1101 xtrct ,*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}, + +/* 0100nnnn00010000 dt */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, + +/* 0011nnnnmmmm1101 dmuls.l ,*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, + +/* 0011nnnnmmmm0101 dmulu.l ,*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, + +/* 0000nnnnmmmm1111 mac.l @+,@+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, + +/* 0000nnnn00100011 braf */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, + +/* 0000nnnn00000011 bsrf */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, + +/* 111101nnmmmm0000 movs.w @-, */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, + +/* 111101nnmmmm0001 movs.w @, */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, + +/* 111101nnmmmm0010 movs.w @+, */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, + +/* 111101nnmmmm0011 movs.w @+r8, */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, + +/* 111101nnmmmm0100 movs.w ,@- */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, + +/* 111101nnmmmm0101 movs.w ,@ */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, + +/* 111101nnmmmm0110 movs.w ,@+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, + +/* 111101nnmmmm0111 movs.w ,@+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, + +/* 111101nnmmmm1000 movs.l @-, */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, + +/* 111101nnmmmm1001 movs.l @, */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, + +/* 111101nnmmmm1010 movs.l @+, */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, + +/* 111101nnmmmm1011 movs.l @+r8, */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, + +/* 111101nnmmmm1100 movs.l ,@- */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, + +/* 111101nnmmmm1101 movs.l ,@ */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, + +/* 111101nnmmmm1110 movs.l ,@+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, + +/* 111101nnmmmm1111 movs.l ,@+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, + +/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, +/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, +/* n*m*0*01** movx.w @, */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, +/* n*m*0*10** movx.w @+, */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, +/* n*m*0*11** movx.w @+r8, */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, +/* n*m*1*01** movx.w ,@ */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, +/* n*m*1*10** movx.w ,@+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, +/* n*m*1*11** movx.w ,@+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, + +/* nnmm000100 movx.w @, */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm001000 movx.w @+, */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm001100 movx.w @+r8, */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}, +/* nnmm100100 movx.w ,@ */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm101000 movx.w ,@+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm101100 movx.w ,@+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}, + +/* nnmm010100 movx.l @, */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm011000 movx.l @+, */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm011100 movx.l @+r8, */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}, +/* nnmm110100 movx.l ,@ */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm111000 movx.l ,@+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm111100 movx.l ,@+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}, + +/* *n*m*0**01 movy.w @, */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, +/* *n*m*0**10 movy.w @+, */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, +/* *n*m*0**11 movy.w @+r9, */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, +/* *n*m*1**01 movy.w ,@ */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, +/* *n*m*1**10 movy.w ,@+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, +/* *n*m*1**11 movy.w ,@+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, + +/* nnmm000001 movy.w @, */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm000010 movy.w @+, */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm000011 movy.w @+r9, */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}, +/* nnmm010001 movy.w ,@ */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm010010 movy.w ,@+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm010011 movy.w ,@+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}, + +/* nnmm100001 movy.l @, */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm100010 movy.l @+, */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm100011 movy.l @+r9, */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}, +/* nnmm110001 movy.l ,@ */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm110010 movy.l ,@+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm110011 movy.l ,@+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}, + +/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, +/* 10100000xxyynnnn psubc ,, */ +{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, +/* 10110000xxyynnnn paddc ,, */ +{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, +/* 10000100xxyynnnn pcmp , */ +{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, +/* 10100100xxyynnnn pwsb ,, */ +{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, +/* 10110100xxyynnnn pwad ,, */ +{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, +/* 10001000xxyynnnn pabs , */ +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}, +/* 1000100!xx01nnnn pabs , */ +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}, +/* 10101000xxyynnnn pabs , */ +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}, +/* 1010100!01yynnnn pabs , */ +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}, +/* 10011000xxyynnnn prnd , */ +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}, +/* 1001100!xx01nnnn prnd , */ +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}, +/* 10111000xxyynnnn prnd , */ +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}, +/* 1011100!01yynnnn prnd , */ +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}, + +{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, +{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, + +/* 10000001xxyynnnn pshl ,, */ +{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, +/* 00000iiiiiiinnnn pshl #, */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, +/* 10010001xxyynnnn psha ,, */ +{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, +/* 00010iiiiiiinnnn psha #, */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, +/* 10100001xxyynnnn psub ,, */ +{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, +/* 10000101xxyynnnn psub ,, */ +{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}, +/* 10110001xxyynnnn padd ,, */ +{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, +/* 10010101xxyynnnn pand ,, */ +{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, +/* 10100101xxyynnnn pxor ,, */ +{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, +/* 10110101xxyynnnn por ,, */ +{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, +/* 10001001xxyynnnn pdec , */ +{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, +/* 10101001xxyynnnn pdec , */ +{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, +/* 10011001xx00nnnn pinc , */ +{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}, +/* 1011100100yynnnn pinc , */ +{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}, +/* 10001101xxyynnnn pclr */ +{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, +/* 10011101xx00nnnn pdmsb , */ +{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}, +/* 1011110100yynnnn pdmsb , */ +{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}, +/* 11001001xxyynnnn pneg , */ +{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, +/* 11101001xxyynnnn pneg , */ +{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, +/* 11011001xxyynnnn pcopy , */ +{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, +/* 11111001xxyynnnn pcopy , */ +{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, +/* 11001101xxyynnnn psts MACH, */ +{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, +/* 11011101xxyynnnn psts MACL, */ +{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, +/* 11101101xxyynnnn plds ,MACH */ +{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, +/* 11111101xxyynnnn plds ,MACL */ +{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, +/* 10011101xx01zzzz pswap , */ +{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}, +/* 1011110101yyzzzz pswap , */ +{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, + +/* 1111nnnn01011101 fabs */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, +/* 1111nnn001011101 fabs */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0000 fadd ,*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, +/* 1111nnn0mmm00000 fadd ,*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0100 fcmp/eq ,*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, +/* 1111nnn0mmm00100 fcmp/eq ,*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0101 fcmp/gt ,*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, +/* 1111nnn0mmm00101 fcmp/gt ,*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}, + +/* 1111nnn010111101 fcnvds ,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnn010101101 fcnvsd FPUL,*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0011 fdiv ,*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, +/* 1111nnn0mmm00011 fdiv ,*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}, + +/* 1111nnmm11101101 fipr ,*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, + +/* 1111nnnn10001101 fldi0 */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}, + +/* 1111nnnn10011101 fldi1 */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}, + +/* 1111nnnn00011101 flds ,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, + +/* 1111nnnn00101101 float FPUL,*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, +/* 1111nnn000101101 float FPUL,*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm1110 fmac FR0,,*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, + +/* 1111nnnnmmmm1100 fmov ,*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, +/* 1111nnn1mmmm1100 fmov ,*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm1000 fmov @,*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, +/* 1111nnn1mmmm1000 fmov @,*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm1010 fmov ,@*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, +/* 1111nnnnmmm11010 fmov ,@*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm1001 fmov @+,*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, +/* 1111nnn1mmmm1001 fmov @+,*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm1011 fmov ,@-*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, +/* 1111nnnnmmm11011 fmov ,@-*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, +/* 1111nnn1mmmm0110 fmov @(R0,),*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, + +/* 1111nnnnmmmm0111 fmov ,@(R0,)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, +/* 1111nnnnmmm10111 fmov ,@(R0,)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, + +/* 1111nnn1mmmm1000 fmov.d @,*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}, +/* 1111nnnnmmm11010 fmov.d ,@*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}, +/* 1111nnn1mmmm1001 fmov.d @+,*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}, +/* 1111nnnnmmm11011 fmov.d ,@-*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}, +/* 1111nnn1mmmm0110 fmov.d @(R0,),*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}, +/* 1111nnnnmmm10111 fmov.d ,@(R0,)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}, +/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d ,@(,) */ +{"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, +/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(,), */ +{"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}, + +/* 1111nnnnmmmm1000 fmov.s @,*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, + +/* 1111nnnnmmmm1010 fmov.s ,@*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, + +/* 1111nnnnmmmm1001 fmov.s @+,*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, + +/* 1111nnnnmmmm1011 fmov.s ,@-*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, + +/* 1111nnnnmmmm0110 fmov.s @(R0,),*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, + +/* 1111nnnnmmmm0111 fmov.s ,@(R0,)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, +/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ +{"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}, +/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ +{"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, + +/* 1111nnnnmmmm0010 fmul ,*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, +/* 1111nnn0mmm00010 fmul ,*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}, + +/* 1111nnnn01001101 fneg */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, +/* 1111nnn001001101 fneg */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, + +/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, + +/* 1111nnn011111101 fsca FPUL, */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, + +/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}, +/* 1111nnn001101101 fsqrt */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, + +/* 1111nnnn00001101 fsts FPUL,*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, + +/* 1111nnnnmmmm0001 fsub ,*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, +/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}, + +/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, +/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}, + +/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, + + /* 10000110nnnn0iii bclr #, */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, + /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #,@(,) */ +{"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 10000111nnnn1iii bld #, */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, + /* 0011nnnn0iii1001 0011dddddddddddd bld.b #,@(,) */ +{"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 10000110nnnn1iii bset #, */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, + /* 0011nnnn0iii1001 0001dddddddddddd bset.b #,@(,) */ +{"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 10000111nnnn0iii bst #, */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, + /* 0011nnnn0iii1001 0010dddddddddddd bst.b #,@(,) */ +{"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0100nnnn10010001 clips.b */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}, + /* 0100nnnn10010101 clips.w */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}, + /* 0100nnnn10000001 clipu.b */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}, + /* 0100nnnn10000101 clipu.w */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}, + /* 0100nnnn10010100 divs R0, */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}, + /* 0100nnnn10000100 divu R0, */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}, + /* 0100mmmm01001011 jsr/n @ */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}, + /* 10000011dddddddd jsr/n @@(,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}, + /* 0100mmmm11100101 ldbank @,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}, + /* 0100mmmm11110001 movml.l ,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}, + /* 0100mmmm11110101 movml.l @R15+, */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}, + /* 0100mmmm11110000 movml.l ,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}, + /* 0100mmmm11110100 movml.l @R15+, */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}, + /* 0000nnnn00111001 movrt */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}, + /* 0100nnnn10000000 mulr R0, */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}, + /* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}, + /* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}, + /* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}, + /* 0000mmmm01111011 rtv/n */ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}, + /* 0100nnnn11100001 stbank R0,@*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}, + +/* 0011nnnn0iii1001 0100dddddddddddd band.b #,@(,) */ +{"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #,@(,) */ +{"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #,@(,) */ +{"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnn0iii1001 0101dddddddddddd bor.b #,@(,) */ +{"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #,@(,) */ +{"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #,@(,) */ +{"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #, */ +{"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}, +/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #, */ +{"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ +{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, +/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ +{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, + +{ 0, {0}, {0}, 0 } +}; + +#endif diff --git a/external/gpl3/gdb/dist/opcodes/sh64-dis.c b/external/gpl3/gdb/dist/opcodes/sh64-dis.c new file mode 100644 index 000000000000..60963e7fc9ce --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sh64-dis.c @@ -0,0 +1,620 @@ +/* Disassemble SH64 instructions. + Copyright 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "dis-asm.h" +#include "sysdep.h" +#include "sh64-opc.h" +#include "libiberty.h" +/* We need to refer to the ELF header structure. */ +#include "elf-bfd.h" +#include "elf/sh.h" +#include "elf32-sh64.h" + +#define ELF_MODE32_CODE_LABEL_P(SYM) \ + (((elf_symbol_type *) (SYM))->internal_elf_sym.st_other & STO_SH5_ISA32) + +#define SAVED_MOVI_R(INFO) \ + (((struct sh64_disassemble_info *) ((INFO)->private_data))->address_reg) + +#define SAVED_MOVI_IMM(INFO) \ + (((struct sh64_disassemble_info *) ((INFO)->private_data))->built_address) + +struct sh64_disassemble_info + { + /* When we see a MOVI, we save the register and the value, and merge a + subsequent SHORI and display the address, if there is one. */ + unsigned int address_reg; + bfd_signed_vma built_address; + + /* This is the range decriptor for the current address. It is kept + around for the next call. */ + sh64_elf_crange crange; + }; + +/* Each item in the table is a mask to indicate which bits to be set + to determine an instruction's operator. + The index is as same as the instruction in the opcode table. + Note that some archs have this as a field in the opcode table. */ +static unsigned long *shmedia_opcode_mask_table; + +/* Initialize the SH64 opcode mask table for each instruction in SHmedia + mode. */ + +static void +initialize_shmedia_opcode_mask_table (void) +{ + int n_opc; + int n; + + /* Calculate number of opcodes. */ + for (n_opc = 0; shmedia_table[n_opc].name != NULL; n_opc++) + ; + + shmedia_opcode_mask_table + = xmalloc (sizeof (shmedia_opcode_mask_table[0]) * n_opc); + + for (n = 0; n < n_opc; n++) + { + int i; + + unsigned long mask = 0; + + for (i = 0; shmedia_table[n].arg[i] != A_NONE; i++) + { + int offset = shmedia_table[n].nibbles[i]; + int length; + + switch (shmedia_table[n].arg[i]) + { + case A_GREG_M: + case A_GREG_N: + case A_GREG_D: + case A_CREG_K: + case A_CREG_J: + case A_FREG_G: + case A_FREG_H: + case A_FREG_F: + case A_DREG_G: + case A_DREG_H: + case A_DREG_F: + case A_FMREG_G: + case A_FMREG_H: + case A_FMREG_F: + case A_FPREG_G: + case A_FPREG_H: + case A_FPREG_F: + case A_FVREG_G: + case A_FVREG_H: + case A_FVREG_F: + case A_REUSE_PREV: + length = 6; + break; + + case A_TREG_A: + case A_TREG_B: + length = 3; + break; + + case A_IMMM: + abort (); + break; + + case A_IMMU5: + length = 5; + break; + + case A_IMMS6: + case A_IMMU6: + case A_IMMS6BY32: + length = 6; + break; + + case A_IMMS10: + case A_IMMS10BY1: + case A_IMMS10BY2: + case A_IMMS10BY4: + case A_IMMS10BY8: + length = 10; + break; + + case A_IMMU16: + case A_IMMS16: + case A_PCIMMS16BY4: + case A_PCIMMS16BY4_PT: + length = 16; + break; + + default: + abort (); + length = 0; + break; + } + + if (length != 0) + mask |= (0xffffffff >> (32 - length)) << offset; + } + shmedia_opcode_mask_table[n] = 0xffffffff & ~mask; + } +} + +/* Get a predefined control-register-name, or return NULL. */ + +static const char * +creg_name (int cregno) +{ + const shmedia_creg_info *cregp; + + /* If control register usage is common enough, change this to search a + hash-table. */ + for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++) + if (cregp->cregno == cregno) + return cregp->name; + + return NULL; +} + +/* Main function to disassemble SHmedia instructions. */ + +static int +print_insn_shmedia (bfd_vma memaddr, struct disassemble_info *info) +{ + fprintf_ftype fprintf_fn = info->fprintf_func; + void *stream = info->stream; + unsigned char insn[4]; + unsigned long instruction; + int status; + int n; + const shmedia_opcode_info *op; + int i; + unsigned int r = 0; + long imm = 0; + bfd_vma disp_pc_addr; + + status = info->read_memory_func (memaddr, insn, 4, info); + + /* If we can't read four bytes, something is wrong. Display any data we + can get as .byte:s. */ + if (status != 0) + { + for (i = 0; i < 3; i++) + { + status = info->read_memory_func (memaddr + i, insn, 1, info); + if (status != 0) + break; + (*fprintf_fn) (stream, "%s0x%02x", + i == 0 ? ".byte " : ", ", + insn[0]); + } + + return i ? i : -1; + } + + /* Rearrange the bytes to make up an instruction. */ + if (info->endian == BFD_ENDIAN_LITTLE) + instruction = bfd_getl32 (insn); + else + instruction = bfd_getb32 (insn); + + /* FIXME: Searching could be implemented using a hash on relevant + fields. */ + for (n = 0, op = shmedia_table; + op->name != NULL + && ((instruction & shmedia_opcode_mask_table[n]) != op->opcode_base); + n++, op++) + ; + + /* FIXME: We should also check register number constraints. */ + if (op->name == NULL) + { + fprintf_fn (stream, ".long 0x%08lx", instruction); + return 4; + } + + fprintf_fn (stream, "%s\t", op->name); + + for (i = 0; i < 3 && op->arg[i] != A_NONE; i++) + { + unsigned long temp = instruction >> op->nibbles[i]; + int by_number = 0; + + if (i > 0 && op->arg[i] != A_REUSE_PREV) + fprintf_fn (stream, ","); + + switch (op->arg[i]) + { + case A_REUSE_PREV: + continue; + + case A_GREG_M: + case A_GREG_N: + case A_GREG_D: + r = temp & 0x3f; + fprintf_fn (stream, "r%d", r); + break; + + case A_FVREG_F: + case A_FVREG_G: + case A_FVREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "fv%d", r); + break; + + case A_FPREG_F: + case A_FPREG_G: + case A_FPREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "fp%d", r); + break; + + case A_FMREG_F: + case A_FMREG_G: + case A_FMREG_H: + r = temp & 0x3f; + fprintf_fn (stream, "mtrx%d", r); + break; + + case A_CREG_K: + case A_CREG_J: + { + const char *name; + + r = temp & 0x3f; + + name = creg_name (r); + + if (name != NULL) + fprintf_fn (stream, "%s", name); + else + fprintf_fn (stream, "cr%d", r); + } + break; + + case A_FREG_G: + case A_FREG_H: + case A_FREG_F: + r = temp & 0x3f; + fprintf_fn (stream, "fr%d", r); + break; + + case A_DREG_G: + case A_DREG_H: + case A_DREG_F: + r = temp & 0x3f; + fprintf_fn (stream, "dr%d", r); + break; + + case A_TREG_A: + case A_TREG_B: + r = temp & 0x7; + fprintf_fn (stream, "tr%d", r); + break; + + /* A signed 6-bit number. */ + case A_IMMS6: + imm = temp & 0x3f; + if (imm & (unsigned long) 0x20) + imm |= ~(unsigned long) 0x3f; + fprintf_fn (stream, "%ld", imm); + break; + + /* A signed 6-bit number, multiplied by 32 when used. */ + case A_IMMS6BY32: + imm = temp & 0x3f; + if (imm & (unsigned long) 0x20) + imm |= ~(unsigned long) 0x3f; + fprintf_fn (stream, "%ld", imm * 32); + break; + + /* A signed 10-bit number, multiplied by 8 when used. */ + case A_IMMS10BY8: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number, multiplied by 4 when used. */ + case A_IMMS10BY4: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number, multiplied by 2 when used. */ + case A_IMMS10BY2: + by_number++; + /* Fall through. */ + + /* A signed 10-bit number. */ + case A_IMMS10: + case A_IMMS10BY1: + imm = temp & 0x3ff; + if (imm & (unsigned long) 0x200) + imm |= ~(unsigned long) 0x3ff; + imm <<= by_number; + fprintf_fn (stream, "%ld", imm); + break; + + /* A signed 16-bit number. */ + case A_IMMS16: + imm = temp & 0xffff; + if (imm & (unsigned long) 0x8000) + imm |= ~((unsigned long) 0xffff); + fprintf_fn (stream, "%ld", imm); + break; + + /* A PC-relative signed 16-bit number, multiplied by 4 when + used. */ + case A_PCIMMS16BY4: + imm = temp & 0xffff; /* 16 bits */ + if (imm & (unsigned long) 0x8000) + imm |= ~(unsigned long) 0xffff; + imm <<= 2; + disp_pc_addr = (bfd_vma) imm + memaddr; + (*info->print_address_func) (disp_pc_addr, info); + break; + + /* An unsigned 5-bit number. */ + case A_IMMU5: + imm = temp & 0x1f; + fprintf_fn (stream, "%ld", imm); + break; + + /* An unsigned 6-bit number. */ + case A_IMMU6: + imm = temp & 0x3f; + fprintf_fn (stream, "%ld", imm); + break; + + /* An unsigned 16-bit number. */ + case A_IMMU16: + imm = temp & 0xffff; + fprintf_fn (stream, "%ld", imm); + break; + + default: + abort (); + break; + } + } + + /* FIXME: Looks like 32-bit values only are handled. + FIXME: PC-relative numbers aren't handled correctly. */ + if (op->opcode_base == (unsigned long) SHMEDIA_SHORI_OPC + && SAVED_MOVI_R (info) == r) + { + asection *section = info->section; + + /* Most callers do not set the section field correctly yet. Revert + to getting the section from symbols, if any. */ + if (section == NULL + && info->symbols != NULL + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && ! bfd_is_und_section (bfd_get_section (info->symbols[0])) + && ! bfd_is_abs_section (bfd_get_section (info->symbols[0]))) + section = bfd_get_section (info->symbols[0]); + + /* Only guess addresses when the contents of this section is fully + relocated. Otherwise, the value will be zero or perhaps even + bogus. */ + if (section == NULL + || section->owner == NULL + || elf_elfheader (section->owner)->e_type == ET_EXEC) + { + bfd_signed_vma shori_addr; + + shori_addr = SAVED_MOVI_IMM (info) << 16; + shori_addr |= imm; + + fprintf_fn (stream, "\t! 0x"); + (*info->print_address_func) (shori_addr, info); + } + } + + if (op->opcode_base == SHMEDIA_MOVI_OPC) + { + SAVED_MOVI_IMM (info) = imm; + SAVED_MOVI_R (info) = r; + } + else + { + SAVED_MOVI_IMM (info) = 0; + SAVED_MOVI_R (info) = 255; + } + + return 4; +} + +/* Check the type of contents about to be disassembled. This is like + sh64_get_contents_type (which may be called from here), except that it + takes the same arguments as print_insn_* and does what can be done if + no section is available. */ + +static enum sh64_elf_cr_type +sh64_get_contents_type_disasm (bfd_vma memaddr, struct disassemble_info *info) +{ + struct sh64_disassemble_info *sh64_infop = info->private_data; + + /* Perhaps we have a region from a previous probe and it still counts + for this address? */ + if (sh64_infop->crange.cr_type != CRT_NONE + && memaddr >= sh64_infop->crange.cr_addr + && memaddr < sh64_infop->crange.cr_addr + sh64_infop->crange.cr_size) + return sh64_infop->crange.cr_type; + + /* If we have a section, try and use it. */ + if (info->section + && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour) + { + enum sh64_elf_cr_type cr_type + = sh64_get_contents_type (info->section, memaddr, + &sh64_infop->crange); + + if (cr_type != CRT_NONE) + return cr_type; + } + + /* If we have symbols, we can try and get at a section from *that*. */ + if (info->symbols != NULL + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && ! bfd_is_und_section (bfd_get_section (info->symbols[0])) + && ! bfd_is_abs_section (bfd_get_section (info->symbols[0]))) + { + enum sh64_elf_cr_type cr_type + = sh64_get_contents_type (bfd_get_section (info->symbols[0]), + memaddr, &sh64_infop->crange); + + if (cr_type != CRT_NONE) + return cr_type; + } + + /* We can make a reasonable guess based on the st_other field of a + symbol; for a BranchTarget this is marked as STO_SH5_ISA32 and then + it's most probably code there. */ + if (info->symbols + && bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour + && elf_symbol_from (bfd_asymbol_bfd (info->symbols[0]), + info->symbols[0])->internal_elf_sym.st_other + == STO_SH5_ISA32) + return CRT_SH5_ISA32; + + /* If all else fails, guess this is code and guess on the low bit set. */ + return (memaddr & 1) == 1 ? CRT_SH5_ISA32 : CRT_SH5_ISA16; +} + +/* Initialize static and dynamic disassembly state. */ + +static bfd_boolean +init_sh64_disasm_info (struct disassemble_info *info) +{ + struct sh64_disassemble_info *sh64_infop + = calloc (sizeof (*sh64_infop), 1); + + if (sh64_infop == NULL) + return FALSE; + + info->private_data = sh64_infop; + + SAVED_MOVI_IMM (info) = 0; + SAVED_MOVI_R (info) = 255; + + if (shmedia_opcode_mask_table == NULL) + initialize_shmedia_opcode_mask_table (); + + return TRUE; +} + +/* Main entry to disassemble SHmedia instructions, given an endian set in + INFO. Note that the simulator uses this as the main entry and does not + use any of the functions further below. */ + +int +print_insn_sh64x_media (bfd_vma memaddr, struct disassemble_info *info) +{ + if (info->private_data == NULL && ! init_sh64_disasm_info (info)) + return -1; + + /* Make reasonable output. */ + info->bytes_per_line = 4; + info->bytes_per_chunk = 4; + + return print_insn_shmedia (memaddr, info); +} + +/* Main entry to disassemble SHmedia insns. + If we see an SHcompact instruction, return -2. */ + +int +print_insn_sh64 (bfd_vma memaddr, struct disassemble_info *info) +{ + enum bfd_endian endian = info->endian; + enum sh64_elf_cr_type cr_type; + + if (info->private_data == NULL && ! init_sh64_disasm_info (info)) + return -1; + + cr_type = sh64_get_contents_type_disasm (memaddr, info); + if (cr_type != CRT_SH5_ISA16) + { + int length = 4 - (memaddr % 4); + info->display_endian = endian; + + /* If we got an uneven address to indicate SHmedia, adjust it. */ + if (cr_type == CRT_SH5_ISA32 && length == 3) + memaddr--, length = 4; + + /* Only disassemble on four-byte boundaries. Addresses that are not + a multiple of four can happen after a data region. */ + if (cr_type == CRT_SH5_ISA32 && length == 4) + return print_insn_sh64x_media (memaddr, info); + + /* We get CRT_DATA *only* for data regions in a mixed-contents + section. For sections with data only, we get indication of one + of the ISA:s. You may think that we shouldn't disassemble + section with only data if we can figure that out. However, the + disassembly function is by default not called for data-only + sections, so if the user explicitly specified disassembly of a + data section, that's what we should do. */ + if (cr_type == CRT_DATA || length != 4) + { + int status; + unsigned char data[4]; + struct sh64_disassemble_info *sh64_infop = info->private_data; + + if (length == 4 + && sh64_infop->crange.cr_type != CRT_NONE + && memaddr >= sh64_infop->crange.cr_addr + && memaddr < (sh64_infop->crange.cr_addr + + sh64_infop->crange.cr_size)) + length + = (sh64_infop->crange.cr_addr + + sh64_infop->crange.cr_size - memaddr); + + status + = (*info->read_memory_func) (memaddr, data, + length >= 4 ? 4 : length, info); + + if (status == 0 && length >= 4) + { + (*info->fprintf_func) (info->stream, ".long 0x%08lx", + endian == BFD_ENDIAN_BIG + ? (long) (bfd_getb32 (data)) + : (long) (bfd_getl32 (data))); + return 4; + } + else + { + int i; + + for (i = 0; i < length; i++) + { + status = info->read_memory_func (memaddr + i, data, 1, info); + if (status != 0) + break; + (*info->fprintf_func) (info->stream, "%s0x%02x", + i == 0 ? ".byte " : ", ", + data[0]); + } + + return i ? i : -1; + } + } + } + + /* SH1 .. SH4 instruction, let caller handle it. */ + return -2; +} diff --git a/external/gpl3/gdb/dist/opcodes/sh64-opc.c b/external/gpl3/gdb/dist/opcodes/sh64-opc.c new file mode 100644 index 000000000000..701724f9e27e --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sh64-opc.c @@ -0,0 +1,777 @@ +/* Definitions for SH64 opcodes. + Copyright (C) 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sh64-opc.h" +#include + +/* Users currently assume that no mnemonic appears twice. For + disassembly, the first complete match is displayed. */ +const shmedia_opcode_info shmedia_table[] = { + +/* 000000mmmmmm1001nnnnnndddddd0000 add ,, */ + { "add", {A_GREG_M,A_GREG_N,A_GREG_D}, + {OFFSET_20,OFFSET_10,OFFSET_4}, SHMEDIA_ADD_OPC + }, +/* 000000mmmmmm1000nnnnnndddddd0000 add.l ,, */ + { "add.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000 + }, +/* 110100mmmmmmssssssssssdddddd0000 addi ,, */ + { "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, + SHMEDIA_ADDI_OPC + }, +/* 110101mmmmmmssssssssssdddddd0000 addi.l ,, */ + { "addi.l", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd4000000 + }, +/* 000000mmmmmm1100nnnnnndddddd0000 addz.l ,, */ + { "addz.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000c0000 + }, +/* 111000mmmmmm0100ssssss1111110000 alloco , */ + { "alloco", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00403f0 + }, +/* 000001mmmmmm1011nnnnnndddddd0000 and ,, */ + { "and", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040b0000 + }, +/* 000001mmmmmm1111nnnnnndddddd0000 andc ,, */ + { "andc", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040f0000 + }, +/* 110110mmmmmmssssssssssdddddd0000 andi ,, */ + { "andi", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000 + }, +/* 011001mmmmmm0001nnnnnnl00ccc0000 beq ,, */ + { "beq/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200 + }, +/* 011001mmmmmm0001nnnnnnl00ccc0000 beq ,, */ + { "beq", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200 + }, +/* 011001mmmmmm0001nnnnnn000ccc0000 beq/u ,, */ + { "beq/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010000 + }, +/* 111001mmmmmm0001ssssssl00ccc0000 beqi ,, */ + { "beqi/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200 + }, +/* 111001mmmmmm0001ssssssl00ccc0000 beqi ,, */ + { "beqi", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200 + }, +/* 111001mmmmmm0001ssssss000ccc0000 beqi/u ,, */ + { "beqi/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010000 + }, +/* 011001mmmmmm0011nnnnnnl00ccc0000 bge ,, */ + { "bge/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200 + }, +/* 011001mmmmmm0011nnnnnnl00ccc0000 bge ,, */ + { "bge", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200 + }, +/* 011001mmmmmm0011nnnnnn000ccc0000 bge/u ,, */ + { "bge/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030000 + }, +/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu ,, */ + { "bgeu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200 + }, +/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu ,, */ + { "bgeu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200 + }, +/* 011001mmmmmm1011nnnnnn000ccc0000 bgeu/u ,, */ + { "bgeu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0000 + }, +/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt ,, */ + { "bgt/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200 + }, +/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt ,, */ + { "bgt", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200 + }, +/* 011001mmmmmm0111nnnnnn000ccc0000 bgt/u ,, */ + { "bgt/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070000 + }, +/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu ,, */ + { "bgtu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200 + }, +/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu ,, */ + { "bgtu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200 + }, +/* 011001mmmmmm1111nnnnnn000ccc0000 bgtu/u ,, */ + { "bgtu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0000 + }, +/* 010001000bbb0001111111dddddd0000 blink , */ + { "blink", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4401fc00 + }, +/* 011001mmmmmm0101nnnnnnl00ccc0000 bne ,, */ + { "bne/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200 + }, +/* 011001mmmmmm0101nnnnnnl00ccc0000 bne ,, */ + { "bne", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200 + }, +/* 011001mmmmmm0101nnnnnn000ccc0000 bne/u ,, */ + { "bne/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050000 + }, +/* 111001mmmmmm0101ssssssl00ccc0000 bnei ,, */ + { "bnei/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200 + }, +/* 111001mmmmmm0101ssssssl00ccc0000 bnei ,, */ + { "bnei", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200 + }, +/* 111001mmmmmm0101ssssss000ccc0000 bnei/u ,, */ + { "bnei/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050000 + }, +/* 01101111111101011111111111110000 brk */ + { "brk", {A_NONE}, {OFFSET_NONE}, 0x6ff5fff0 + }, +/* 000000mmmmmm1111111111dddddd0000 byterev , */ + { "byterev", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000ffc00 + }, +/* 000000mmmmmm0001nnnnnndddddd0000 cmpeq ,, */ + { "cmpeq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00010000 + }, +/* 000000mmmmmm0011nnnnnndddddd0000 cmpgt ,, */ + { "cmpgt", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00030000 + }, +/* 000000mmmmmm0111nnnnnndddddd0000 cmpgtu ,, */ + { "cmpgtu", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00070000 + }, +/* 001000mmmmmm0001nnnnnnwwwwww0000 cmveq ,, */ + { "cmveq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20010000 + }, +/* 001000mmmmmm0101nnnnnnwwwwww0000 cmvne ,, */ + { "cmvne", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20050000 + }, +/* 000110gggggg0001ggggggffffff0000 fabs.d , */ + { "fabs.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18010000 + }, +/* 000110gggggg0000ggggggffffff0000 fabs.s , */ + { "fabs.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18000000 + }, +/* 001101gggggg0001hhhhhhffffff0000 fadd.s ,, */ + { "fadd.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34010000 + }, +/* 001101gggggg0000hhhhhhffffff0000 fadd.s ,, */ + { "fadd.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34000000 + }, +/* 001100gggggg1001hhhhhhdddddd0000 fcmpeq.s ,, */ + { "fcmpeq.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30090000 + }, +/* 001100gggggg1000hhhhhhdddddd0000 fcmpeq.s ,, */ + { "fcmpeq.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30080000 + }, +/* 001100gggggg1111hhhhhhdddddd0000 fcmpge.d ,, */ + { "fcmpge.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300f0000 + }, +/* 001100gggggg1110hhhhhhdddddd0000 fcmpge.s ,, */ + { "fcmpge.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300e0000 + }, +/* 001100gggggg1101hhhhhhdddddd0000 fcmpgt.d ,, */ + { "fcmpgt.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300d0000 + }, +/* 001100gggggg1100hhhhhhdddddd0000 fcmpgt.s ,, */ + { "fcmpgt.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300c0000 + }, +/* 001100gggggg1011hhhhhhdddddd0000 fcmpun.d ,, */ + { "fcmpun.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300b0000 + }, +/* 001100gggggg1010hhhhhhdddddd0000 fcmpun.s ,, */ + { "fcmpun.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300a0000 + }, +/* 001110gggggg0111ggggggffffff0000 fcnv.ds , */ + { "fcnv.ds", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38070000 + }, +/* 001110gggggg0110ggggggffffff0000 fcnv.sd , */ + { "fcnv.sd", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38060000 + }, +/* 001101gggggg0101hhhhhhffffff0000 fdiv.d ,, */ + { "fdiv.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34050000 + }, +/* 001101gggggg0100hhhhhhffffff0000 fdiv.s ,, */ + { "fdiv.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34040000 + }, +/* 0001111111110010111111ffffff0000 fgetscr */ + { "fgetscr", {A_FREG_F}, {OFFSET_4}, 0x1ff2fc00 + }, +/* 000101gggggg0110hhhhhhffffff0000 fipr.s ,, */ + { "fipr.s", {A_FVREG_G,A_FVREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x14060000 + }, +/* 100111mmmmmmssssssssssffffff0000 fld.d ,, */ + { "fld.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x9c000000 + }, +/* 100110mmmmmmssssssssssffffff0000 fld.p ,, */ + { "fld.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x98000000 + }, +/* 100101mmmmmmssssssssssffffff0000 fld.s ,, */ + { "fld.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x94000000 + }, +/* 000111mmmmmm1001nnnnnnffffff0000 fldx.d ,, */ + { "fldx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c090000 + }, +/* 000111mmmmmm1101nnnnnnffffff0000 fldx.p ,, */ + { "fldx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c0d0000 + }, +/* 000111mmmmmm1000nnnnnnffffff0000 fldx.s ,, */ + { "fldx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c080000 + }, +/* 001110gggggg1110ggggggffffff0000 float.ld , */ + { "float.ld", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380e0000 + }, +/* 001110gggggg1100ggggggffffff0000 float.ls , */ + { "float.ls", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380c0000 + }, +/* 001110gggggg1101ggggggffffff0000 float.qd , */ + { "float.qd", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380d0000 + }, +/* 001110gggggg1111ggggggffffff0000 float.qs , */ + { "float.qs", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380f0000 + }, +/* 001101gggggg1110hhhhhhqqqqqq0000 fmac.s ,, */ + { "fmac.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x340e0000 + }, +/* 001110gggggg0001ggggggffffff0000 fmov.d , */ + { "fmov.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38010000 + }, +/* 001100gggggg0001ggggggdddddd0000 fmov.dq , */ + { "fmov.dq", {A_DREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30010000 + }, +/* 000111mmmmmm0000111111ffffff0000 fmov.ls , */ + { "fmov.ls", {A_GREG_M,A_FREG_F}, {OFFSET_20,OFFSET_4}, 0x1c00fc00 + }, +/* 000111mmmmmm0001111111ffffff0000 fmov.qd , */ + { "fmov.qd", {A_GREG_M,A_DREG_F}, {OFFSET_20,OFFSET_4}, 0x1c01fc00 + }, +/* 001110gggggg0000ggggggffffff0000 fmov.s , */ + { "fmov.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38000000 + }, +/* 001100gggggg0000ggggggdddddd0000 fmov.sl , */ + { "fmov.sl", {A_FREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30000000 + }, +/* 001101gggggg0111hhhhhhffffff0000 fmul.d ,, */ + { "fmul.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34070000 + }, +/* 001101gggggg0110hhhhhhffffff0000 fmul.s ,, */ + { "fmul.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34060000 + }, +/* 000110gggggg0011ggggggffffff0000 fneg.d , */ + { "fneg.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18030000 + }, +/* 000110gggggg0010ggggggffffff0000 fneg.s , */ + { "fneg.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18020000 + }, +/* 001100gggggg0010gggggg1111110000 fputscr */ + { "fputscr", {A_FREG_G,A_REUSE_PREV}, {OFFSET_20,OFFSET_10}, 0x300203f0 + }, +/* 001110gggggg0101ggggggffffff0000 fsqrt.d , */ + { "fsqrt.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000 + }, +/* 001110gggggg0100ggggggffffff0000 fsqrt.s , */ + { "fsqrt.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000 + }, +/* 101111mmmmmmsssssssssszzzzzz0000 fst.d ,, */ + { "fst.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xbc000000 + }, +/* 101110mmmmmmsssssssssszzzzzz0000 fst.p ,, */ + { "fst.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb8000000 + }, +/* 101101mmmmmmsssssssssszzzzzz0000 fst.s ,, */ + { "fst.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb4000000 + }, +/* 001111mmmmmm1001nnnnnnzzzzzz0000 fstx.d ,, */ + { "fstx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c090000 + }, +/* 001111mmmmmm1101nnnnnnzzzzzz0000 fstx.p ,, */ + { "fstx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c0d0000 + }, +/* 001111mmmmmm1000nnnnnnzzzzzz0000 fstx.s ,, */ + { "fstx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c080000 + }, +/* 001101gggggg0011hhhhhhffffff0000 fsub.d ,, */ + { "fsub.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34030000 + }, +/* 001101gggggg0010hhhhhhffffff0000 fsub.s ,, */ + { "fsub.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34020000 + }, +/* 001110gggggg1011ggggggffffff0000 ftrc.dl , */ + { "ftrc.dl", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380b0000 + }, +/* 001110gggggg1001ggggggffffff0000 ftrc.dq , */ + { "ftrc.dq", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38090000 + }, +/* 001110gggggg1000ggggggffffff0000 ftrc.sl , */ + { "ftrc.sl", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38080000 + }, +/* 001110gggggg1010ggggggffffff0000 ftrc.sq , */ + { "ftrc.sq", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380a0000 + }, +/* 000101gggggg1110hhhhhhffffff0000 ftrv.s ,, */ + { "ftrv.s", {A_FMREG_G,A_FVREG_H,A_FVREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x140e0000 + }, +/* 110000mmmmmm1111ssssssdddddd0000 getcfg ,, */ + { "getcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc00f0000 + }, +/* 001001kkkkkk1111111111dddddd0000 getcon , */ + { "getcon", {A_CREG_K,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x240ffc00 + }, +/* 010001rrrbbb0101111111dddddd0000 gettr , */ + { "gettr", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4405fc00 + }, +/* 111000mmmmmm0101ssssss1111110000 icbi , */ + { "icbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00503f0 + }, +/* 100000mmmmmmssssssssssdddddd0000 ld.b ,, */ + { "ld.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x80000000 + }, +/* 100010mmmmmmssssssssssdddddd0000 ld.l ,, */ + { "ld.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x88000000 + }, +/* 100011mmmmmmssssssssssdddddd0000 ld.q ,, */ + { "ld.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x8c000000 + }, +/* 100100mmmmmmssssssssssdddddd0000 ld.ub ,, */ + { "ld.ub", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x90000000 + }, +/* 101100mmmmmmssssssssssdddddd0000 ld.uw ,, */ + { "ld.uw", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb0000000 + }, +/* 100001mmmmmmssssssssssdddddd0000 ld.w ,, */ + { "ld.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x84000000 + }, +/* 110000mmmmmm0110ssssssdddddd0000 ldhi.l ,, */ + { "ldhi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0060000 + }, +/* 110000mmmmmm0111ssssssdddddd0000 ldhi.q ,, */ + { "ldhi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0070000 + }, +/* 110000mmmmmm0010ssssssdddddd0000 ldlo.l ,, */ + { "ldlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0020000 + }, +/* 110000mmmmmm0011ssssssdddddd0000 ldlo.q ,, */ + { "ldlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0030000 + }, +/* 010000mmmmmm0000nnnnnndddddd0000 ldx.b ,, */ + { "ldx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40000000 + }, +/* 010000mmmmmm0010nnnnnndddddd0000 ldx.l ,, */ + { "ldx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40020000 + }, +/* 010000mmmmmm0011nnnnnndddddd0000 ldx.q ,, */ + { "ldx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40030000 + }, +/* 010000mmmmmm0100nnnnnndddddd0000 ldx.ub ,, */ + { "ldx.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40040000 + }, +/* 010000mmmmmm0101nnnnnndddddd0000 ldx.uw ,, */ + { "ldx.uw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40050000 + }, +/* 010000mmmmmm0001nnnnnndddddd0000 ldx.w ,, */ + { "ldx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40010000 + }, +/* 001010mmmmmm1010111111dddddd0000 mabs.l , */ + { "mabs.l", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x280afc00 + }, +/* 001010mmmmmm1001111111dddddd0000 mabs.w , */ + { "mabs.w", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x2809fc00 + }, +/* 000010mmmmmm0010nnnnnndddddd0000 madd.l ,, */ + { "madd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08020000 + }, +/* 000010mmmmmm0001nnnnnndddddd0000 madd.w ,, */ + { "madd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08010000 + }, +/* 000010mmmmmm0110nnnnnndddddd0000 madds.l ,, */ + { "madds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08060000 + }, +/* 000010mmmmmm0100nnnnnndddddd0000 madds.ub ,, */ + { "madds.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08040000 + }, +/* 000010mmmmmm0101nnnnnndddddd0000 madds.w ,, */ + { "madds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08050000 + }, +/* 001010mmmmmm0000nnnnnndddddd0000 mcmpeq.b ,, */ + { "mcmpeq.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28000000 + }, +/* 001010mmmmmm0010nnnnnndddddd0000 mcmpeq.l ,, */ + { "mcmpeq.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28020000 + }, +/* 001010mmmmmm0001nnnnnndddddd0000 mcmpeq.w ,, */ + { "mcmpeq.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28010000 + }, +/* 001010mmmmmm0110nnnnnndddddd0000 mcmpgt.l ,, */ + { "mcmpgt.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28060000 + }, +/* 001010mmmmmm0100nnnnnndddddd0000 mcmpgt.ub ,, */ + { "mcmpgt.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28040000 + }, +/* 001010mmmmmm0101nnnnnndddddd0000 mcmpgt.w ,, */ + { "mcmpgt.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28050000 + }, +/* 010010mmmmmm0011nnnnnnwwwwww0000 mcmv ,, */ + { "mcmv", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48030000 + }, +/* 010011mmmmmm1101nnnnnndddddd0000 mcnvs.lw ,, */ + { "mcnvs.lw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0d0000 + }, +/* 010011mmmmmm1000nnnnnndddddd0000 mcnvs.wb ,, */ + { "mcnvs.wb", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c080000 + }, +/* 010011mmmmmm1100nnnnnndddddd0000 mcnvs.wub ,, */ + { "mcnvs.wub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0c0000 + }, +/* 001010mmmmmm0111nnnnnndddddd0000 mextr1 ,, */ + { "mextr1", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28070000 + }, +/* 001010mmmmmm1011nnnnnndddddd0000 mextr2 ,, */ + { "mextr2", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280b0000 + }, +/* 001010mmmmmm1111nnnnnndddddd0000 mextr3 ,, */ + { "mextr3", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280f0000 + }, +/* 001011mmmmmm0011nnnnnndddddd0000 mextr4 ,, */ + { "mextr4", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c030000 + }, +/* 001011mmmmmm0111nnnnnndddddd0000 mextr5 ,, */ + { "mextr5", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c070000 + }, +/* 001011mmmmmm1011nnnnnndddddd0000 mextr6 ,, */ + { "mextr6", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0b0000 + }, +/* 001011mmmmmm1111nnnnnndddddd0000 mextr7 ,, */ + { "mextr7", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0f0000 + }, +/* 010010mmmmmm0001nnnnnnwwwwww0000 mmacfx.wl ,, */ + { "mmacfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48010000 + }, +/* 010010mmmmmm0101nnnnnnwwwwww0000 mmacnfx.wl ,, */ + { "mmacnfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48050000 + }, +/* 010011mmmmmm0010nnnnnndddddd0000 mmul.l ,, */ + { "mmul.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c020000 + }, +/* 010011mmmmmm0001nnnnnndddddd0000 mmul.m ,, */ + { "mmul.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c010000 + }, +/* 010011mmmmmm0110nnnnnndddddd0000 mmulfx.l ,, */ + { "mmulfx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c060000 + }, +/* 010011mmmmmm0101nnnnnndddddd0000 mmulfx.w ,, */ + { "mmulfx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c050000 + }, +/* 010011mmmmmm1001nnnnnndddddd0000 mmulfxrp.w ,, */ + { "mmulfxrp.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c090000 + }, +/* 010011mmmmmm1110nnnnnndddddd0000 mmulhi.wl ,, */ + { "mmulhi.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0e0000 + }, +/* 010011mmmmmm1010nnnnnndddddd0000 mmullo.wl ,, */ + { "mmullo.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0a0000 + }, +/* 010010mmmmmm1001nnnnnnwwwwww0000 mmulsum.wq ,, */ + { "mmulsum.wq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48090000 + }, +/* 110011ssssssssssssssssdddddd0000 movi , */ + { "movi", {A_IMMS16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_MOVI_OPC + }, +/* 001010mmmmmm1101nnnnnndddddd0000 mperm.w ,, */ + { "mperm.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280d0000 + }, +/* 010010mmmmmm0000nnnnnnwwwwww0000 msad.ubq ,, */ + { "msad.ubq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48000000 + }, +/* 000011mmmmmm1010nnnnnndddddd0000 mshard.l ,, */ + { "mshard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0a0000 + }, +/* 000011mmmmmm1001nnnnnndddddd0000 mshard.w ,, */ + { "mshard.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c090000 + }, +/* 000011mmmmmm1011nnnnnndddddd0000 mshards.q ,, */ + { "mshards.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0b0000 + }, +/* 001011mmmmmm0100nnnnnndddddd0000 mshfhi.b ,, */ + { "mshfhi.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c040000 + }, +/* 001011mmmmmm0110nnnnnndddddd0000 mshfhi.l ,, */ + { "mshfhi.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c060000 + }, +/* 001011mmmmmm0101nnnnnndddddd0000 mshfhi.w ,, */ + { "mshfhi.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c050000 + }, +/* 001011mmmmmm0000nnnnnndddddd0000 mshflo.b ,, */ + { "mshflo.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c000000 + }, +/* 001011mmmmmm0010nnnnnndddddd0000 mshflo.l ,, */ + { "mshflo.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c020000 + }, +/* 001011mmmmmm0001nnnnnndddddd0000 mshflo.w ,, */ + { "mshflo.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c010000 + }, +/* 000011mmmmmm0010nnnnnndddddd0000 mshlld.l ,, */ + { "mshlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c020000 + }, +/* 000011mmmmmm0001nnnnnndddddd0000 mshlld.w ,, */ + { "mshlld.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c010000 + }, +/* 000011mmmmmm0110nnnnnndddddd0000 mshalds.l ,, */ + { "mshalds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c060000 + }, +/* 000011mmmmmm0101nnnnnndddddd0000 mshalds.w ,, */ + { "mshalds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c050000 + }, +/* 000011mmmmmm1110nnnnnndddddd0000 mshlrd.l ,, */ + { "mshlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0e0000 + }, +/* 000011mmmmmm1101nnnnnndddddd0000 mshlrd.w ,, */ + { "mshlrd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0d0000 + }, +/* 000010mmmmmm1010nnnnnndddddd0000 msub.l ,, */ + { "msub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080a0000 + }, +/* 000010mmmmmm1001nnnnnndddddd0000 msub.w ,, */ + { "msub.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08090000 + }, +/* 000010mmmmmm1110nnnnnndddddd0000 msubs.l ,, */ + { "msubs.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080e0000 + }, +/* 000010mmmmmm1100nnnnnndddddd0000 msubs.ub ,, */ + { "msubs.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080c0000 + }, +/* 000010mmmmmm1101nnnnnndddddd0000 msubs.w ,, */ + { "msubs.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080d0000 + }, +/* 000001mmmmmm1110nnnnnndddddd0000 muls.l ,, */ + { "muls.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000 + }, +/* 000000mmmmmm1110nnnnnndddddd0000 mulu.l ,, */ + { "mulu.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000e0000 + }, +/* 01101111111100001111111111110000 nop */ + { "nop", {A_NONE}, {OFFSET_NONE}, + SHMEDIA_NOP_OPC + }, +/* 000000mmmmmm1101111111dddddd0000 nsb , */ + { "nsb", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000dfc00 + }, +/* 111000mmmmmm1001ssssss1111110000 ocbi , */ + { "ocbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00903f0 + }, +/* 111000mmmmmm1000ssssss1111110000 ocbp , */ + { "ocbp", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00803f0 + }, +/* 111000mmmmmm1100ssssss1111110000 ocbwb , */ + { "ocbwb", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00c03f0 + }, +/* 000001mmmmmm1001nnnnnndddddd0000 or ,, */ + { "or", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04090000 + }, +/* 110111mmmmmmssssssssssdddddd0000 ori ,, */ + { "ori", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xdc000000 + }, +/* 111000mmmmmm0001ssssss1111110000 prefi , */ + { "prefi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00103f0 + }, +/* 111010sssssssssssssssslrraaa0000 pta , */ + { "pta/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010sssssssssssssssslrraaa0000 pta , */ + { "pta", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010ssssssssssssssss0rraaa0000 pta/u , */ + { "pta/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTA_OPC + }, +/* 0110101111110001nnnnnnl00aaa0000 ptabs , */ + { "ptabs/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200 + }, +/* 0110101111110001nnnnnnl00aaa0000 ptabs , */ + { "ptabs", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200 + }, +/* 0110101111110001nnnnnn000aaa0000 ptabs/u , */ + { "ptabs/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10000 + }, +/* 111011sssssssssssssssslrraaa0000 ptb , */ + { "ptb/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111011sssssssssssssssslrraaa0000 ptb , */ + { "ptb", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111011ssssssssssssssss0rraaa0000 ptb/u , */ + { "ptb/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTB_OPC + }, +/* 111010sssssssssssssssslrraaa0000 pt/l , */ + { "pt/l", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010sssssssssssssssslrraaa0000 pt , */ + { "pt", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT + }, +/* 111010ssssssssssssssss0rraaa0000 pt/u , */ + { "pt/u", {A_PCIMMS16BY4_PT,A_TREG_A}, + {OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC + }, +/* 0110101111110101nnnnnnl00aaa0000 ptrel , */ + { "ptrel/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT + }, +/* 0110101111110101nnnnnnl00aaa0000 ptrel , */ + { "ptrel", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT + }, +/* 0110101111110101nnnnnn000aaa0000 ptrel/u , */ + { "ptrel/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, + SHMEDIA_PTREL_OPC + }, +/* 111000mmmmmm1111ssssssyyyyyy0000 putcfg ,, */ + { "putcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe00f0000 + }, +/* 011011mmmmmm1111111111jjjjjj0000 putcon , */ + { "putcon", {A_GREG_M,A_CREG_J}, {OFFSET_20,OFFSET_4}, 0x6c0ffc00 + }, +/* 01101111111100111111111111110000 rte */ + { "rte", {A_NONE}, {OFFSET_NONE}, 0x6ff3fff0 + }, +/* 000001mmmmmm0111nnnnnndddddd0000 shard ,, */ + { "shard", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04070000 + }, +/* 000001mmmmmm0110nnnnnndddddd0000 shard.l ,, */ + { "shard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04060000 + }, +/* 110001mmmmmm0111ssssssdddddd0000 shari ,, */ + { "shari", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4070000 + }, +/* 110001mmmmmm0110ssssssdddddd0000 shari ,, */ + { "shari.l", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4060000 + }, +/* 000001mmmmmm0001nnnnnndddddd0000 shlld ,, */ + { "shlld", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04010000 + }, +/* 000001mmmmmm0000nnnnnndddddd0000 shlld.l ,, */ + { "shlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04000000 + }, +/* 110001mmmmmm0001ssssssdddddd0000 shlli ,, */ + { "shlli", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4010000 + }, +/* 110001mmmmmm0000ssssssdddddd0000 shlli.l ,, */ + { "shlli.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4000000 + }, +/* 000001mmmmmm0011nnnnnndddddd0000 shlrd ,, */ + { "shlrd", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04030000 + }, +/* 000001mmmmmm0010nnnnnndddddd0000 shlrd.l ,, */ + { "shlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04020000 + }, +/* 110001mmmmmm0011ssssssdddddd0000 shlri ,, */ + { "shlri", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4030000 + }, +/* 110001mmmmmm0010ssssssdddddd0000 shlri.l ,, */ + { "shlri.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4020000 + }, +/* 110010sssssssssssssssswwwwww0000 shori , */ + { "shori", {A_IMMU16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_SHORI_OPC + }, +/* 01101111111101111111111111110000 sleep */ + { "sleep", {A_NONE}, {OFFSET_NONE}, 0x6ff7fff0 + }, +/* 101000mmmmmmssssssssssdddddd0000 st.b ,, */ + { "st.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa0000000 + }, +/* 101010mmmmmmssssssssssdddddd0000 st.l ,, */ + { "st.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa8000000 + }, +/* 101011mmmmmmssssssssssdddddd0000 st.q ,, */ + { "st.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xac000000 + }, +/* 101001mmmmmmssssssssssdddddd0000 st.w ,, */ + { "st.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa4000000 + }, +/* 111000mmmmmm0110ssssssdddddd0000 sthi.l ,, */ + { "sthi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0060000 + }, +/* 111000mmmmmm0111ssssssdddddd0000 sthi.q ,, */ + { "sthi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0070000 + }, +/* 111000mmmmmm0010ssssssdddddd0000 stlo.l ,, */ + { "stlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0020000 + }, +/* 111000mmmmmm0011ssssssdddddd0000 stlo.q ,, */ + { "stlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0030000 + }, +/* 011000mmmmmm0000nnnnnndddddd0000 stx.b ,, */ + { "stx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60000000 + }, +/* 011000mmmmmm0010nnnnnndddddd0000 stx.l ,, */ + { "stx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60020000 + }, +/* 011000mmmmmm0011nnnnnndddddd0000 stx.q ,, */ + { "stx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60030000 + }, +/* 011000mmmmmm0001nnnnnndddddd0000 stx.w ,, */ + { "stx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60010000 + }, +/* 000000mmmmmm1011nnnnnndddddd0000 sub ,, */ + { "sub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000b0000 + }, +/* 000000mmmmmm1010nnnnnndddddd0000 sub.l ,, */ + { "sub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000a0000 + }, +/* 001000mmmmmm0011nnnnnnwwwwww0000 swap.q ,, */ + { "swap.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20030000 + }, +/* 01101111111100101111111111110000 synci */ + { "synci", {A_NONE}, {OFFSET_NONE}, 0x6ff2fff0 + }, +/* 01101111111101101111111111110000 synco */ + { "synco", {A_NONE}, {OFFSET_NONE}, 0x6ff6fff0 + }, +/* 011011mmmmmm00011111111111110000 trapa */ + { "trapa", {A_GREG_M}, {OFFSET_20}, 0x6c01fff0 + }, +/* 000001mmmmmm1101nnnnnndddddd0000 xor ,, */ + { "xor", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040d0000 + }, +/* 110001mmmmmm1101ssssssdddddd0000 xori ,, */ + { "xori", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc40d0000 + }, + + { NULL, {}, {}, 0 } +}; + +/* Predefined control register names as per SH-5/ST50-005-08. */ +const shmedia_creg_info shmedia_creg_table[] = { + { 0, "sr" }, + { 1, "ssr" }, + { 2, "pssr" }, + + { 4, "intevt" }, + { 5, "expevt" }, + { 6, "pexpevt" }, + { 7, "tra" }, + { 8, "spc" }, + { 9, "pspc" }, + { 10, "resvec" }, + { 11, "vbr" }, + + { 13, "tea" }, + + { 16, "dcr" }, + { 17, "kcr0" }, + { 18, "kcr1" }, + + { 62, "ctc" }, + { 63, "usr" }, + { -1, (char *) 0 } +}; + diff --git a/external/gpl3/gdb/dist/opcodes/sh64-opc.h b/external/gpl3/gdb/dist/opcodes/sh64-opc.h new file mode 100644 index 000000000000..a12035a8bb37 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sh64-opc.h @@ -0,0 +1,142 @@ +/* Declarations for SH64 opcodes. + Copyright (C) 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _SH64_OPC_INCLUDED_H +#define _SH64_OPC_INCLUDED_H + +typedef enum +{ + /* A placeholder. */ + OFFSET_NONE = 0, + + /* Bit number for where to insert operand. */ + OFFSET_4 = 4, + OFFSET_9 = 9, + OFFSET_10 = 10, + OFFSET_20 = 20 +} shmedia_nibble_type; + +typedef enum { + /* First a placeholder. */ + A_NONE = 0, + + /* Registers. */ + A_GREG_M, + A_GREG_N, + A_GREG_D, + A_FREG_G, + A_FREG_H, + A_FREG_F, + A_DREG_G, + A_DREG_H, + A_DREG_F, + A_FVREG_G, + A_FVREG_H, + A_FVREG_F, + A_FMREG_G, + A_FMREG_H, + A_FMREG_F, + A_FPREG_G, + A_FPREG_H, + A_FPREG_F, + A_TREG_A, + A_TREG_B, + A_CREG_K, + A_CREG_J, + + /* This one is only used in a shmedia_get_operand. */ + A_IMMM, + + /* Copy of previous register. */ + A_REUSE_PREV, + + /* Unsigned 5-bit operand. */ + A_IMMU5, + + /* Signed 6-bit operand. */ + A_IMMS6, + + /* Signed operand, 6 bits << 5. */ + A_IMMS6BY32, + + /* Unsigned 6-bit operand. */ + A_IMMU6, + + /* Signed 10-bit operand. */ + A_IMMS10, + + /* Signed operand, 10 bits << 0. */ + A_IMMS10BY1, + + /* Signed operand, 10 bits << 1. */ + A_IMMS10BY2, + + /* Signed operand, 10 bits << 2. */ + A_IMMS10BY4, + + /* Signed operand, 10 bits << 3. */ + A_IMMS10BY8, + + /* Signed 16-bit operand. */ + A_IMMS16, + + /* Unsigned 16-bit operand. */ + A_IMMU16, + + /* PC-relative signed operand, 16 bits << 2, for PTA and PTB insns. */ + A_PCIMMS16BY4, + + /* PC relative signed operand, 16 bits << 2, for PT insns. Also adjusts + the opcode to be PTA or PTB. */ + A_PCIMMS16BY4_PT, +} shmedia_arg_type; + +typedef struct { + char *name; + shmedia_arg_type arg[4]; + shmedia_nibble_type nibbles[4]; + unsigned long opcode_base; +} shmedia_opcode_info; + +extern const shmedia_opcode_info shmedia_table[]; + +typedef struct { + int cregno; + char *name; +} shmedia_creg_info; + +extern const shmedia_creg_info shmedia_creg_table[]; + +#define SHMEDIA_LIKELY_BIT 0x00000200 +#define SHMEDIA_PT_OPC 0xe8000000 +#define SHMEDIA_PTB_BIT 0x04000000 +#define SHMEDIA_PTA_OPC 0xe8000000 +#define SHMEDIA_PTB_OPC 0xec000000 + +/* Note that this is ptrel/u. "Or" in SHMEDIA_LIKELY_BIT for ptrel/l. */ +#define SHMEDIA_PTREL_OPC 0x6bf50000 +#define SHMEDIA_MOVI_OPC 0xcc000000 +#define SHMEDIA_SHORI_OPC 0xc8000000 +#define SHMEDIA_ADDI_OPC 0xd0000000 +#define SHMEDIA_ADD_OPC 0x00090000 +#define SHMEDIA_NOP_OPC 0x6ff0fff0 +#define SHMEDIA_TEMP_REG 25 + +#endif /* _SH64_OPC_INCLUDED_H */ diff --git a/external/gpl3/gdb/dist/opcodes/sparc-dis.c b/external/gpl3/gdb/dist/opcodes/sparc-dis.c new file mode 100644 index 000000000000..8dec272fb2b4 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sparc-dis.c @@ -0,0 +1,1017 @@ +/* Print SPARC instructions. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/sparc.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opintl.h" + +/* Bitmask of v9 architectures. */ +#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ + | (1 << SPARC_OPCODE_ARCH_V9A) \ + | (1 << SPARC_OPCODE_ARCH_V9B)) +/* 1 if INSN is for v9 only. */ +#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) +/* 1 if INSN is for v9. */ +#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) + +/* The sorted opcode table. */ +static const sparc_opcode **sorted_opcodes; + +/* For faster lookup, after insns are sorted they are hashed. */ +/* ??? I think there is room for even more improvement. */ + +#define HASH_SIZE 256 +/* It is important that we only look at insn code bits as that is how the + opcode table is hashed. OPCODE_BITS is a table of valid bits for each + of the main types (0,1,2,3). */ +static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; +#define HASH_INSN(INSN) \ + ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) +typedef struct sparc_opcode_hash +{ + struct sparc_opcode_hash *next; + const sparc_opcode *opcode; +} sparc_opcode_hash; + +static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; + +/* Sign-extend a value which is N bits long. */ +#define SEX(value, bits) \ + ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ + >> ((8 * sizeof (int)) - bits) ) + +static char *reg_names[] = +{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", + "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", + "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", + "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", + "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", +/* psr, wim, tbr, fpsr, cpsr are v8 only. */ + "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" +}; + +#define freg_names (®_names[4 * 8]) + +/* These are ordered according to there register number in + rdpr and wrpr insns. */ +static char *v9_priv_reg_names[] = +{ + "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", + "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", + "wstate", "fq", "gl" + /* "ver" - special cased */ +}; + +/* These are ordered according to there register number in + rdhpr and wrhpr insns. */ +static char *v9_hpriv_reg_names[] = +{ + "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", + "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", + "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", + "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27", + "resv28", "resv29", "resv30", "hstick_cmpr" +}; + +/* These are ordered according to there register number in + rd and wr insns (-16). */ +static char *v9a_asr_reg_names[] = +{ + "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", + "softint", "tick_cmpr", "stick", "stick_cmpr" +}; + +/* Macros used to extract instruction fields. Not all fields have + macros defined here, only those which are actually used. */ + +#define X_RD(i) (((i) >> 25) & 0x1f) +#define X_RS1(i) (((i) >> 14) & 0x1f) +#define X_LDST_I(i) (((i) >> 13) & 1) +#define X_ASI(i) (((i) >> 5) & 0xff) +#define X_RS2(i) (((i) >> 0) & 0x1f) +#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) +#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) +#define X_DISP22(i) (((i) >> 0) & 0x3fffff) +#define X_IMM22(i) X_DISP22 (i) +#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) + +/* These are for v9. */ +#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) +#define X_DISP19(i) (((i) >> 0) & 0x7ffff) +#define X_MEMBAR(i) ((i) & 0x7f) + +/* Here is the union which was used to extract instruction fields + before the shift and mask macros were written. + + union sparc_insn + { + unsigned long int code; + struct + { + unsigned int anop:2; + #define op ldst.anop + unsigned int anrd:5; + #define rd ldst.anrd + unsigned int op3:6; + unsigned int anrs1:5; + #define rs1 ldst.anrs1 + unsigned int i:1; + unsigned int anasi:8; + #define asi ldst.anasi + unsigned int anrs2:5; + #define rs2 ldst.anrs2 + #define shcnt rs2 + } ldst; + struct + { + unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; + unsigned int IMM13:13; + #define imm13 IMM13.IMM13 + } IMM13; + struct + { + unsigned int anop:2; + unsigned int a:1; + unsigned int cond:4; + unsigned int op2:3; + unsigned int DISP22:22; + #define disp22 branch.DISP22 + #define imm22 disp22 + } branch; + struct + { + unsigned int anop:2; + unsigned int a:1; + unsigned int z:1; + unsigned int rcond:3; + unsigned int op2:3; + unsigned int DISP16HI:2; + unsigned int p:1; + unsigned int _rs1:5; + unsigned int DISP16LO:14; + } branch16; + struct + { + unsigned int anop:2; + unsigned int adisp30:30; + #define disp30 call.adisp30 + } call; + }; */ + +/* Nonzero if INSN is the opcode for a delayed branch. */ + +static int +is_delayed_branch (unsigned long insn) +{ + sparc_opcode_hash *op; + + for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) + { + const sparc_opcode *opcode = op->opcode; + + if ((opcode->match & insn) == opcode->match + && (opcode->lose & insn) == 0) + return opcode->flags & F_DELAYED; + } + return 0; +} + +/* extern void qsort (); */ + +/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value + to compare_opcodes. */ +static unsigned int current_arch_mask; + +/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ + +static int +compute_arch_mask (unsigned long mach) +{ + switch (mach) + { + case 0 : + case bfd_mach_sparc : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); + case bfd_mach_sparc_sparclet : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); + case bfd_mach_sparc_sparclite : + case bfd_mach_sparc_sparclite_le : + /* sparclites insns are recognized by default (because that's how + they've always been treated, for better or worse). Kludge this by + indicating generic v8 is also selected. */ + return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) + | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); + case bfd_mach_sparc_v8plus : + case bfd_mach_sparc_v9 : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); + case bfd_mach_sparc_v8plusa : + case bfd_mach_sparc_v9a : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); + case bfd_mach_sparc_v8plusb : + case bfd_mach_sparc_v9b : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); + } + abort (); +} + +/* Compare opcodes A and B. */ + +static int +compare_opcodes (const void * a, const void * b) +{ + sparc_opcode *op0 = * (sparc_opcode **) a; + sparc_opcode *op1 = * (sparc_opcode **) b; + unsigned long int match0 = op0->match, match1 = op1->match; + unsigned long int lose0 = op0->lose, lose1 = op1->lose; + register unsigned int i; + + /* If one (and only one) insn isn't supported by the current architecture, + prefer the one that is. If neither are supported, but they're both for + the same architecture, continue processing. Otherwise (both unsupported + and for different architectures), prefer lower numbered arch's (fudged + by comparing the bitmasks). */ + if (op0->architecture & current_arch_mask) + { + if (! (op1->architecture & current_arch_mask)) + return -1; + } + else + { + if (op1->architecture & current_arch_mask) + return 1; + else if (op0->architecture != op1->architecture) + return op0->architecture - op1->architecture; + } + + /* If a bit is set in both match and lose, there is something + wrong with the opcode table. */ + if (match0 & lose0) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op0->name, match0, lose0); + op0->lose &= ~op0->match; + lose0 = op0->lose; + } + + if (match1 & lose1) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op1->name, match1, lose1); + op1->lose &= ~op1->match; + lose1 = op1->lose; + } + + /* Because the bits that are variable in one opcode are constant in + another, it is important to order the opcodes in the right order. */ + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (match0 & x) != 0; + int x1 = (match1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (lose0 & x) != 0; + int x1 = (lose1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + /* They are functionally equal. So as long as the opcode table is + valid, we can put whichever one first we want, on aesthetic grounds. */ + + /* Our first aesthetic ground is that aliases defer to real insns. */ + { + int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); + + if (alias_diff != 0) + /* Put the one that isn't an alias first. */ + return alias_diff; + } + + /* Except for aliases, two "identical" instructions had + better have the same opcode. This is a sanity check on the table. */ + i = strcmp (op0->name, op1->name); + if (i) + { + if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ + return i; + else + fprintf (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), + op0->name, op1->name); + } + + /* Fewer arguments are preferred. */ + { + int length_diff = strlen (op0->args) - strlen (op1->args); + + if (length_diff != 0) + /* Put the one with fewer arguments first. */ + return length_diff; + } + + /* Put 1+i before i+1. */ + { + char *p0 = (char *) strchr (op0->args, '+'); + char *p1 = (char *) strchr (op1->args, '+'); + + if (p0 && p1) + { + /* There is a plus in both operands. Note that a plus + sign cannot be the first character in args, + so the following [-1]'s are valid. */ + if (p0[-1] == 'i' && p1[1] == 'i') + /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ + return 1; + if (p0[1] == 'i' && p1[-1] == 'i') + /* op0 is 1+i and op1 is i+1, so op0 goes first. */ + return -1; + } + } + + /* Put 1,i before i,1. */ + { + int i0 = strncmp (op0->args, "i,1", 3) == 0; + int i1 = strncmp (op1->args, "i,1", 3) == 0; + + if (i0 ^ i1) + return i0 - i1; + } + + /* They are, as far as we can tell, identical. + Since qsort may have rearranged the table partially, there is + no way to tell which one was first in the opcode table as + written, so just say there are equal. */ + /* ??? This is no longer true now that we sort a vector of pointers, + not the table itself. */ + return 0; +} + +/* Build a hash table from the opcode table. + OPCODE_TABLE is a sorted list of pointers into the opcode table. */ + +static void +build_hash_table (const sparc_opcode **opcode_table, + sparc_opcode_hash **hash_table, + int num_opcodes) +{ + int i; + int hash_count[HASH_SIZE]; + static sparc_opcode_hash *hash_buf = NULL; + + /* Start at the end of the table and work backwards so that each + chain is sorted. */ + + memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); + memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); + if (hash_buf != NULL) + free (hash_buf); + hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); + for (i = num_opcodes - 1; i >= 0; --i) + { + int hash = HASH_INSN (opcode_table[i]->match); + sparc_opcode_hash *h = &hash_buf[i]; + + h->next = hash_table[hash]; + h->opcode = opcode_table[i]; + hash_table[hash] = h; + ++hash_count[hash]; + } + +#if 0 /* for debugging */ + { + int min_count = num_opcodes, max_count = 0; + int total; + + for (i = 0; i < HASH_SIZE; ++i) + { + if (hash_count[i] < min_count) + min_count = hash_count[i]; + if (hash_count[i] > max_count) + max_count = hash_count[i]; + total += hash_count[i]; + } + + printf ("Opcode hash table stats: min %d, max %d, ave %f\n", + min_count, max_count, (double) total / HASH_SIZE); + } +#endif +} + +/* Print one instruction from MEMADDR on INFO->STREAM. + + We suffix the instruction with a comment that gives the absolute + address involved, as well as its symbolic form, if the instruction + is preceded by a findable `sethi' and it either adds an immediate + displacement to that register, or it is an `add' or `or' instruction + on that register. */ + +int +print_insn_sparc (bfd_vma memaddr, disassemble_info *info) +{ + FILE *stream = info->stream; + bfd_byte buffer[4]; + unsigned long insn; + sparc_opcode_hash *op; + /* Nonzero of opcode table has been initialized. */ + static int opcodes_initialized = 0; + /* bfd mach number of last call. */ + static unsigned long current_mach = 0; + bfd_vma (*getword) (const void *); + + if (!opcodes_initialized + || info->mach != current_mach) + { + int i; + + current_arch_mask = compute_arch_mask (info->mach); + + if (!opcodes_initialized) + sorted_opcodes = + xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); + /* Reset the sorted table so we can resort it. */ + for (i = 0; i < sparc_num_opcodes; ++i) + sorted_opcodes[i] = &sparc_opcodes[i]; + qsort ((char *) sorted_opcodes, sparc_num_opcodes, + sizeof (sorted_opcodes[0]), compare_opcodes); + + build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); + current_mach = info->mach; + opcodes_initialized = 1; + } + + { + int status = + (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); + + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + + /* On SPARClite variants such as DANlite (sparc86x), instructions + are always big-endian even when the machine is in little-endian mode. */ + if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) + getword = bfd_getb32; + else + getword = bfd_getl32; + + insn = getword (buffer); + + info->insn_info_valid = 1; /* We do return this info. */ + info->insn_type = dis_nonbranch; /* Assume non branch insn. */ + info->branch_delay_insns = 0; /* Assume no delay. */ + info->target = 0; /* Assume no target known. */ + + for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) + { + const sparc_opcode *opcode = op->opcode; + + /* If the insn isn't supported by the current architecture, skip it. */ + if (! (opcode->architecture & current_arch_mask)) + continue; + + if ((opcode->match & insn) == opcode->match + && (opcode->lose & insn) == 0) + { + /* Nonzero means that we have found an instruction which has + the effect of adding or or'ing the imm13 field to rs1. */ + int imm_added_to_rs1 = 0; + int imm_ored_to_rs1 = 0; + + /* Nonzero means that we have found a plus sign in the args + field of the opcode table. */ + int found_plus = 0; + + /* Nonzero means we have an annulled branch. */ + int is_annulled = 0; + + /* Do we have an `add' or `or' instruction combining an + immediate with rs1? */ + if (opcode->match == 0x80102000) /* or */ + imm_ored_to_rs1 = 1; + if (opcode->match == 0x80002000) /* add */ + imm_added_to_rs1 = 1; + + if (X_RS1 (insn) != X_RD (insn) + && strchr (opcode->args, 'r') != 0) + /* Can't do simple format if source and dest are different. */ + continue; + if (X_RS2 (insn) != X_RD (insn) + && strchr (opcode->args, 'O') != 0) + /* Can't do simple format if source and dest are different. */ + continue; + + (*info->fprintf_func) (stream, opcode->name); + + { + const char *s; + + if (opcode->args[0] != ',') + (*info->fprintf_func) (stream, " "); + + for (s = opcode->args; *s != '\0'; ++s) + { + while (*s == ',') + { + (*info->fprintf_func) (stream, ","); + ++s; + switch (*s) + { + case 'a': + (*info->fprintf_func) (stream, "a"); + is_annulled = 1; + ++s; + continue; + case 'N': + (*info->fprintf_func) (stream, "pn"); + ++s; + continue; + + case 'T': + (*info->fprintf_func) (stream, "pt"); + ++s; + continue; + + default: + break; + } + } + + (*info->fprintf_func) (stream, " "); + + switch (*s) + { + case '+': + found_plus = 1; + /* Fall through. */ + + default: + (*info->fprintf_func) (stream, "%c", *s); + break; + + case '#': + (*info->fprintf_func) (stream, "0"); + break; + +#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) + case '1': + case 'r': + reg (X_RS1 (insn)); + break; + + case '2': + case 'O': + reg (X_RS2 (insn)); + break; + + case 'd': + reg (X_RD (insn)); + break; +#undef reg + +#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) +#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) + case 'e': + freg (X_RS1 (insn)); + break; + case 'v': /* Double/even. */ + case 'V': /* Quad/multiple of 4. */ + fregx (X_RS1 (insn)); + break; + + case 'f': + freg (X_RS2 (insn)); + break; + case 'B': /* Double/even. */ + case 'R': /* Quad/multiple of 4. */ + fregx (X_RS2 (insn)); + break; + + case 'g': + freg (X_RD (insn)); + break; + case 'H': /* Double/even. */ + case 'J': /* Quad/multiple of 4. */ + fregx (X_RD (insn)); + break; +#undef freg +#undef fregx + +#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) + case 'b': + creg (X_RS1 (insn)); + break; + + case 'c': + creg (X_RS2 (insn)); + break; + + case 'D': + creg (X_RD (insn)); + break; +#undef creg + + case 'h': + (*info->fprintf_func) (stream, "%%hi(%#x)", + ((unsigned) 0xFFFFFFFF + & ((int) X_IMM22 (insn) << 10))); + break; + + case 'i': /* 13 bit immediate. */ + case 'I': /* 11 bit immediate. */ + case 'j': /* 10 bit immediate. */ + { + int imm; + + if (*s == 'i') + imm = X_SIMM (insn, 13); + else if (*s == 'I') + imm = X_SIMM (insn, 11); + else + imm = X_SIMM (insn, 10); + + /* Check to see whether we have a 1+i, and take + note of that fact. + + Note: because of the way we sort the table, + we will be matching 1+i rather than i+1, + so it is OK to assume that i is after +, + not before it. */ + if (found_plus) + imm_added_to_rs1 = 1; + + if (imm <= 9) + (*info->fprintf_func) (stream, "%d", imm); + else + (*info->fprintf_func) (stream, "%#x", imm); + } + break; + + case 'X': /* 5 bit unsigned immediate. */ + case 'Y': /* 6 bit unsigned immediate. */ + { + int imm = X_IMM (insn, *s == 'X' ? 5 : 6); + + if (imm <= 9) + (info->fprintf_func) (stream, "%d", imm); + else + (info->fprintf_func) (stream, "%#x", (unsigned) imm); + } + break; + + case '3': + (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); + break; + + case 'K': + { + int mask = X_MEMBAR (insn); + int bit = 0x40, printed_one = 0; + const char *name; + + if (mask == 0) + (info->fprintf_func) (stream, "0"); + else + while (bit) + { + if (mask & bit) + { + if (printed_one) + (info->fprintf_func) (stream, "|"); + name = sparc_decode_membar (bit); + (info->fprintf_func) (stream, "%s", name); + printed_one = 1; + } + bit >>= 1; + } + break; + } + + case 'k': + info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'G': + info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; + (*info->print_address_func) (info->target, info); + break; + + case '6': + case '7': + case '8': + case '9': + (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); + break; + + case 'z': + (*info->fprintf_func) (stream, "%%icc"); + break; + + case 'Z': + (*info->fprintf_func) (stream, "%%xcc"); + break; + + case 'E': + (*info->fprintf_func) (stream, "%%ccr"); + break; + + case 's': + (*info->fprintf_func) (stream, "%%fprs"); + break; + + case 'o': + (*info->fprintf_func) (stream, "%%asi"); + break; + + case 'W': + (*info->fprintf_func) (stream, "%%tick"); + break; + + case 'P': + (*info->fprintf_func) (stream, "%%pc"); + break; + + case '?': + if (X_RS1 (insn) == 31) + (*info->fprintf_func) (stream, "%%ver"); + else if ((unsigned) X_RS1 (insn) < 17) + (*info->fprintf_func) (stream, "%%%s", + v9_priv_reg_names[X_RS1 (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '!': + if ((unsigned) X_RD (insn) < 17) + (*info->fprintf_func) (stream, "%%%s", + v9_priv_reg_names[X_RD (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '$': + if ((unsigned) X_RS1 (insn) < 32) + (*info->fprintf_func) (stream, "%%%s", + v9_hpriv_reg_names[X_RS1 (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '%': + if ((unsigned) X_RD (insn) < 32) + (*info->fprintf_func) (stream, "%%%s", + v9_hpriv_reg_names[X_RD (insn)]); + else + (*info->fprintf_func) (stream, "%%reserved"); + break; + + case '/': + if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) + (*info->fprintf_func) (stream, "%%reserved"); + else + (*info->fprintf_func) (stream, "%%%s", + v9a_asr_reg_names[X_RS1 (insn)-16]); + break; + + case '_': + if (X_RD (insn) < 16 || X_RD (insn) > 25) + (*info->fprintf_func) (stream, "%%reserved"); + else + (*info->fprintf_func) (stream, "%%%s", + v9a_asr_reg_names[X_RD (insn)-16]); + break; + + case '*': + { + const char *name = sparc_decode_prefetch (X_RD (insn)); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "%ld", X_RD (insn)); + break; + } + + case 'M': + (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); + break; + + case 'm': + (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); + break; + + case 'L': + info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'n': + (*info->fprintf_func) + (stream, "%#x", SEX (X_DISP22 (insn), 22)); + break; + + case 'l': + info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; + (*info->print_address_func) (info->target, info); + break; + + case 'A': + { + const char *name = sparc_decode_asi (X_ASI (insn)); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); + break; + } + + case 'C': + (*info->fprintf_func) (stream, "%%csr"); + break; + + case 'F': + (*info->fprintf_func) (stream, "%%fsr"); + break; + + case 'p': + (*info->fprintf_func) (stream, "%%psr"); + break; + + case 'q': + (*info->fprintf_func) (stream, "%%fq"); + break; + + case 'Q': + (*info->fprintf_func) (stream, "%%cq"); + break; + + case 't': + (*info->fprintf_func) (stream, "%%tbr"); + break; + + case 'w': + (*info->fprintf_func) (stream, "%%wim"); + break; + + case 'x': + (*info->fprintf_func) (stream, "%ld", + ((X_LDST_I (insn) << 8) + + X_ASI (insn))); + break; + + case 'y': + (*info->fprintf_func) (stream, "%%y"); + break; + + case 'u': + case 'U': + { + int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); + const char *name = sparc_decode_sparclet_cpreg (val); + + if (name) + (*info->fprintf_func) (stream, "%s", name); + else + (*info->fprintf_func) (stream, "%%cpreg(%d)", val); + break; + } + } + } + } + + /* If we are adding or or'ing something to rs1, then + check to see whether the previous instruction was + a sethi to the same register as in the sethi. + If so, attempt to print the result of the add or + or (in this context add and or do the same thing) + and its symbolic value. */ + if (imm_ored_to_rs1 || imm_added_to_rs1) + { + unsigned long prev_insn; + int errcode; + + if (memaddr >= 4) + errcode = + (*info->read_memory_func) + (memaddr - 4, buffer, sizeof (buffer), info); + else + errcode = 1; + + prev_insn = getword (buffer); + + if (errcode == 0) + { + /* If it is a delayed branch, we need to look at the + instruction before the delayed branch. This handles + sequences such as: + + sethi %o1, %hi(_foo), %o1 + call _printf + or %o1, %lo(_foo), %o1 */ + + if (is_delayed_branch (prev_insn)) + { + if (memaddr >= 8) + errcode = (*info->read_memory_func) + (memaddr - 8, buffer, sizeof (buffer), info); + else + errcode = 1; + + prev_insn = getword (buffer); + } + } + + /* If there was a problem reading memory, then assume + the previous instruction was not sethi. */ + if (errcode == 0) + { + /* Is it sethi to the same register? */ + if ((prev_insn & 0xc1c00000) == 0x01000000 + && X_RD (prev_insn) == X_RS1 (insn)) + { + (*info->fprintf_func) (stream, "\t! "); + info->target = + ((unsigned) 0xFFFFFFFF + & ((int) X_IMM22 (prev_insn) << 10)); + if (imm_added_to_rs1) + info->target += X_SIMM (insn, 13); + else + info->target |= X_SIMM (insn, 13); + (*info->print_address_func) (info->target, info); + info->insn_type = dis_dref; + info->data_size = 4; /* FIXME!!! */ + } + } + } + + if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) + { + /* FIXME -- check is_annulled flag. */ + (void) is_annulled; + if (opcode->flags & F_UNBR) + info->insn_type = dis_branch; + if (opcode->flags & F_CONDBR) + info->insn_type = dis_condbranch; + if (opcode->flags & F_JSR) + info->insn_type = dis_jsr; + if (opcode->flags & F_DELAYED) + info->branch_delay_insns = 1; + } + + return sizeof (buffer); + } + } + + info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ + (*info->fprintf_func) (stream, _("unknown")); + return sizeof (buffer); +} diff --git a/external/gpl3/gdb/dist/opcodes/sparc-opc.c b/external/gpl3/gdb/dist/opcodes/sparc-opc.c new file mode 100644 index 000000000000..ad29dac6d789 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sparc-opc.c @@ -0,0 +1,2141 @@ +/* Table of opcodes for the sparc. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2002, 2004, 2005, 2006, 2007, 2008 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +/* FIXME-someday: perhaps the ,a's and such should be embedded in the + instruction's name rather than the args. This would make gas faster, pinsn + slower, but would mess up some macros a bit. xoxorich. */ + +#include +#include "sysdep.h" +#include "opcode/sparc.h" + +/* Some defines to make life easy. */ +#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) +#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) +#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) +#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) +#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) +#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) +#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) +#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) + +/* Bit masks of architectures supporting the insn. */ + +#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +/* v6 insns not supported on the sparclet. */ +#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ + | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) +/* Although not all insns are implemented in hardware, sparclite is defined + to be a superset of v8. Unimplemented insns trap and are then theoretically + implemented in software. + It's not clear that the same is true for sparclet, although the docs + suggest it is. Rather than complicating things, the sparclet assembler + recognizes all v8 insns. */ +#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ + | MASK_V9 | MASK_V9A | MASK_V9B) +#define sparclet (MASK_SPARCLET) +#define sparclite (MASK_SPARCLITE) +#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) +#define v9a (MASK_V9A | MASK_V9B) +#define v9b (MASK_V9B) +/* v6 insns not supported by v9. */ +#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ + | MASK_SPARCLET | MASK_SPARCLITE) +/* v9a instructions which would appear to be aliases to v9's impdep's + otherwise. */ +#define v9notv9a (MASK_V9) + +/* Table of opcode architectures. + The order is defined in opcode/sparc.h. */ + +const struct sparc_opcode_arch sparc_opcode_archs[] = +{ + { "v6", MASK_V6 }, + { "v7", MASK_V6 | MASK_V7 }, + { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, + { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, + { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, + /* ??? Don't some v8 priviledged insns conflict with v9? */ + { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, + /* v9 with ultrasparc additions */ + { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, + /* v9 with cheetah additions */ + { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, + { NULL, 0 } +}; + +/* Given NAME, return it's architecture entry. */ + +enum sparc_opcode_arch_val +sparc_opcode_lookup_arch (const char *name) +{ + const struct sparc_opcode_arch *p; + + for (p = &sparc_opcode_archs[0]; p->name; ++p) + if (strcmp (name, p->name) == 0) + return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); + + return SPARC_OPCODE_ARCH_BAD; +} + +/* Branch condition field. */ +#define COND(x) (((x) & 0xf) << 25) + +/* v9: Move (MOVcc and FMOVcc) condition field. */ +#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ + +/* v9: Move register (MOVRcc and FMOVRcc) condition field. */ +#define RCOND(x) (((x) & 0x7) << 10) /* v9 */ + +#define CONDA (COND (0x8)) +#define CONDCC (COND (0xd)) +#define CONDCS (COND (0x5)) +#define CONDE (COND (0x1)) +#define CONDG (COND (0xa)) +#define CONDGE (COND (0xb)) +#define CONDGU (COND (0xc)) +#define CONDL (COND (0x3)) +#define CONDLE (COND (0x2)) +#define CONDLEU (COND (0x4)) +#define CONDN (COND (0x0)) +#define CONDNE (COND (0x9)) +#define CONDNEG (COND (0x6)) +#define CONDPOS (COND (0xe)) +#define CONDVC (COND (0xf)) +#define CONDVS (COND (0x7)) + +#define CONDNZ CONDNE +#define CONDZ CONDE +#define CONDGEU CONDCC +#define CONDLU CONDCS + +#define FCONDA (COND (0x8)) +#define FCONDE (COND (0x9)) +#define FCONDG (COND (0x6)) +#define FCONDGE (COND (0xb)) +#define FCONDL (COND (0x4)) +#define FCONDLE (COND (0xd)) +#define FCONDLG (COND (0x2)) +#define FCONDN (COND (0x0)) +#define FCONDNE (COND (0x1)) +#define FCONDO (COND (0xf)) +#define FCONDU (COND (0x7)) +#define FCONDUE (COND (0xa)) +#define FCONDUG (COND (0x5)) +#define FCONDUGE (COND (0xc)) +#define FCONDUL (COND (0x3)) +#define FCONDULE (COND (0xe)) + +#define FCONDNZ FCONDNE +#define FCONDZ FCONDE + +#define ICC (0) /* v9 */ +#define XCC (1 << 12) /* v9 */ +#define FCC(x) (((x) & 0x3) << 11) /* v9 */ +#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ + +/* The order of the opcodes in the table is significant: + + * The assembler requires that all instances of the same mnemonic must + be consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. */ + +/* Entries for commutative arithmetic operations. */ +/* ??? More entries can make use of this. */ +#define COMMUTEOP(opcode, op3, arch_mask) \ +{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ +{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } + +const struct sparc_opcode sparc_opcodes[] = { + +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, +{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, +{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, +{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ + +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, +{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, +{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ + +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, +{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, +{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ + +/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the + 'ld' pseudo-op in v9. */ +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, +{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, +{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ + +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, +{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ + +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, +{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ + +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ + +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ +{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ + +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ + +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ + +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ + +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, +{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ + +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, +{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ + +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, +{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ + +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, +{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, +{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, +{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, +{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, +{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, +{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ + +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, +{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, +{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, +{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, +{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ +{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, +{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ + +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ + +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, +{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, +{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ + +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, +{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, +{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ + +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, +{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, +{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ + +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, +{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ + +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, +{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ + +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, +{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, +{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ + +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ + +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ + +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ + +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, +{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ + +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ + +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ + +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, +{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, +{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ + +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, +{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ + +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ + +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, +{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, +{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ + +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, +{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, +{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ + +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, +{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ + +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, +{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ + +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, +{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, +{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ + +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, +{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, +{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, +{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, +{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, +{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, +{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ + +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, +{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, +{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ + +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, +{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, +{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ + +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, +{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ + +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, +{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, +{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ + +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, +{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ + +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ + +{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, +{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, + +{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ +{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ + +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, +{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, + +{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 }, +{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, + +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, +{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, +{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, + +/* IFLUSH was renamed to FLUSH in v8. */ +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, +{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, + +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, +{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, +{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, + +{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, + +{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, +{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, + +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, +{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, +{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ + +{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, +{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, +{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, +{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, + +{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, +{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, +{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, + +{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, + +{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, +{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, + +{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, +{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, + +{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, +{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, + +{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ +{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ + +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ + +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, +{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ + +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, +{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ + +{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, +{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, + +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ +{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ +{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ + +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ +{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ +{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ +{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ +{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ +{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ +{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ +{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ +{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ + +{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ +{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ +{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ +{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ +{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ +{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ + +{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ +{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ +{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ +{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ +{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ +{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ +{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ +{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ +{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ +{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ +{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ +{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ +{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ +{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ +{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ +{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ +{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ +{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ +{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ +{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ + +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ +{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ +{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ +{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ +{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ + +{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ +{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ +{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ +{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ + +{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ +{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ +{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ +{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ +{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ + +{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ +{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ +{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ + +{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */ +{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */ +{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */ +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */ +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */ +{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */ + +/* ??? This group seems wrong. A three operand move? */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ + +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ +{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ +{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ +{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ +{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ + +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ +{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ +{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ +{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ +{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ +{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ +{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ +{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ +{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ + +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ +{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ +{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ + +{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, +{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, + +{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ +{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ + +/* This is not a commutative instruction. */ +{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, + +/* This is not a commutative instruction. */ +{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, + +{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ +{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ + +{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ +{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ + +{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, + +{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, + +{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, +{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, + +{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, +{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, + +{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, +{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, + +{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, +{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, + +{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ +{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ +{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ +{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ +{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ +{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ +{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ +{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ + +{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ +{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ + +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ +{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ + +{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, +{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, +{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, + +{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, +{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, +{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, +{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, + +{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, +{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, +{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, +{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, + +{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, +{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, +{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, +{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, +{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, +{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, +{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, +{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, +{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, + +{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, +{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, +{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, + +{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, +{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, + +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ +{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ +{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, + + +/* Conditional instructions. + + Because this part of the table was such a mess earlier, I have + macrofied it so that all the branches and traps are generated from + a single-line description of each condition value. John Gilmore. */ + +/* Define branches -- one annulled, one without, etc. */ +#define br(opcode, mask, lose, flags) \ + { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ + { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } + +#define brx(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ + { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ + { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ + { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } + +/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ +#define tr(opcode, mask, lose, flags) \ + { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ + { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ + { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ + { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ + { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ + { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ + { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ + { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ + { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ + { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ + +/* v9: We must put `brx' before `br', to ensure that we never match something + v9: against an expression unless it is an expression. Otherwise, we end + v9: up with undefined symbol tables entries, because they get added, but + v9: are not deleted if the pattern fails to match. */ + +/* Define both branches and traps based on condition mask */ +#define cond(bop, top, mask, flags) \ + brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ + br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ + tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) + +/* Define all the conditions, all the branches, all the traps. */ + +/* Standard branch, trap mnemonics */ +cond ("b", "ta", CONDA, F_UNBR), +/* Alternative form (just for assembly, not for disassembly) */ +cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), + +cond ("bcc", "tcc", CONDCC, F_CONDBR), +cond ("bcs", "tcs", CONDCS, F_CONDBR), +cond ("be", "te", CONDE, F_CONDBR), +cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), +cond ("bg", "tg", CONDG, F_CONDBR), +cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), +cond ("bge", "tge", CONDGE, F_CONDBR), +cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ +cond ("bgu", "tgu", CONDGU, F_CONDBR), +cond ("bl", "tl", CONDL, F_CONDBR), +cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), +cond ("ble", "tle", CONDLE, F_CONDBR), +cond ("bleu", "tleu", CONDLEU, F_CONDBR), +cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ +cond ("bn", "tn", CONDN, F_CONDBR), +cond ("bne", "tne", CONDNE, F_CONDBR), +cond ("bneg", "tneg", CONDNEG, F_CONDBR), +cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ +cond ("bpos", "tpos", CONDPOS, F_CONDBR), +cond ("bvc", "tvc", CONDVC, F_CONDBR), +cond ("bvs", "tvs", CONDVS, F_CONDBR), +cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ + +#undef cond +#undef br +#undef brr /* v9 */ +#undef tr + +#define brr(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ + { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } + +#define condr(bop, mask, flags) /* v9 */ \ + brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ + +/* v9 */ condr("brnz", 0x5, F_CONDBR), +/* v9 */ condr("brz", 0x1, F_CONDBR), +/* v9 */ condr("brgez", 0x7, F_CONDBR), +/* v9 */ condr("brlz", 0x3, F_CONDBR), +/* v9 */ condr("brlez", 0x2, F_CONDBR), +/* v9 */ condr("brgz", 0x6, F_CONDBR), + +#undef condr /* v9 */ +#undef brr /* v9 */ + +#define movr(opcode, mask, flags) /* v9 */ \ + { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ + { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } + +#define fmrrs(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } +#define fmrrd(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } +#define fmrrq(opcode, mask, lose, flags) /* v9 */ \ + { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } + +#define fmovrs(mop, mask, flags) /* v9 */ \ + fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ +#define fmovrd(mop, mask, flags) /* v9 */ \ + fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ +#define fmovrq(mop, mask, flags) /* v9 */ \ + fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ + +/* v9 */ movr("movrne", 0x5, 0), +/* v9 */ movr("movre", 0x1, 0), +/* v9 */ movr("movrgez", 0x7, 0), +/* v9 */ movr("movrlz", 0x3, 0), +/* v9 */ movr("movrlez", 0x2, 0), +/* v9 */ movr("movrgz", 0x6, 0), +/* v9 */ movr("movrnz", 0x5, F_ALIAS), +/* v9 */ movr("movrz", 0x1, F_ALIAS), + +/* v9 */ fmovrs("fmovrsne", 0x5, 0), +/* v9 */ fmovrs("fmovrse", 0x1, 0), +/* v9 */ fmovrs("fmovrsgez", 0x7, 0), +/* v9 */ fmovrs("fmovrslz", 0x3, 0), +/* v9 */ fmovrs("fmovrslez", 0x2, 0), +/* v9 */ fmovrs("fmovrsgz", 0x6, 0), +/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), +/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), + +/* v9 */ fmovrd("fmovrdne", 0x5, 0), +/* v9 */ fmovrd("fmovrde", 0x1, 0), +/* v9 */ fmovrd("fmovrdgez", 0x7, 0), +/* v9 */ fmovrd("fmovrdlz", 0x3, 0), +/* v9 */ fmovrd("fmovrdlez", 0x2, 0), +/* v9 */ fmovrd("fmovrdgz", 0x6, 0), +/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), +/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), + +/* v9 */ fmovrq("fmovrqne", 0x5, 0), +/* v9 */ fmovrq("fmovrqe", 0x1, 0), +/* v9 */ fmovrq("fmovrqgez", 0x7, 0), +/* v9 */ fmovrq("fmovrqlz", 0x3, 0), +/* v9 */ fmovrq("fmovrqlez", 0x2, 0), +/* v9 */ fmovrq("fmovrqgz", 0x6, 0), +/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), +/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), + +#undef movr /* v9 */ +#undef fmovr /* v9 */ +#undef fmrr /* v9 */ + +#define movicc(opcode, cond, flags) /* v9 */ \ + { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } + +#define movfcc(opcode, fcond, flags) /* v9 */ \ + { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ + { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } + +#define movcc(opcode, cond, fcond, flags) /* v9 */ \ + movfcc (opcode, fcond, flags), /* v9 */ \ + movicc (opcode, cond, flags) /* v9 */ + +/* v9 */ movcc ("mova", CONDA, FCONDA, 0), +/* v9 */ movicc ("movcc", CONDCC, 0), +/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), +/* v9 */ movicc ("movcs", CONDCS, 0), +/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), +/* v9 */ movcc ("move", CONDE, FCONDE, 0), +/* v9 */ movcc ("movg", CONDG, FCONDG, 0), +/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), +/* v9 */ movicc ("movgu", CONDGU, 0), +/* v9 */ movcc ("movl", CONDL, FCONDL, 0), +/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), +/* v9 */ movicc ("movleu", CONDLEU, 0), +/* v9 */ movfcc ("movlg", FCONDLG, 0), +/* v9 */ movcc ("movn", CONDN, FCONDN, 0), +/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), +/* v9 */ movicc ("movneg", CONDNEG, 0), +/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ movfcc ("movo", FCONDO, 0), +/* v9 */ movicc ("movpos", CONDPOS, 0), +/* v9 */ movfcc ("movu", FCONDU, 0), +/* v9 */ movfcc ("movue", FCONDUE, 0), +/* v9 */ movfcc ("movug", FCONDUG, 0), +/* v9 */ movfcc ("movuge", FCONDUGE, 0), +/* v9 */ movfcc ("movul", FCONDUL, 0), +/* v9 */ movfcc ("movule", FCONDULE, 0), +/* v9 */ movicc ("movvc", CONDVC, 0), +/* v9 */ movicc ("movvs", CONDVS, 0), +/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), + +#undef movicc /* v9 */ +#undef movfcc /* v9 */ +#undef movcc /* v9 */ + +#define FM_SF 1 /* v9 - values for fpsize */ +#define FM_DF 2 /* v9 */ +#define FM_QF 3 /* v9 */ + +#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 } + +#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \ +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 } + +/* FIXME: use fmovicc/fmovfcc? */ /* v9 */ +#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ +{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \ +{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 } + +#define fmovicc(suffix, cond, flags) /* v9 */ \ +fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ +fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ +fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) + +#define fmovfcc(suffix, fcond, flags) /* v9 */ \ +fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ +fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ +fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) + +#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ +fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ +fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ +fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) + +/* v9 */ fmovcc ("a", CONDA, FCONDA, 0), +/* v9 */ fmovicc ("cc", CONDCC, 0), +/* v9 */ fmovicc ("cs", CONDCS, 0), +/* v9 */ fmovcc ("e", CONDE, FCONDE, 0), +/* v9 */ fmovcc ("g", CONDG, FCONDG, 0), +/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), +/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), +/* v9 */ fmovicc ("gu", CONDGU, 0), +/* v9 */ fmovcc ("l", CONDL, FCONDL, 0), +/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), +/* v9 */ fmovicc ("leu", CONDLEU, 0), +/* v9 */ fmovfcc ("lg", FCONDLG, 0), +/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), +/* v9 */ fmovcc ("n", CONDN, FCONDN, 0), +/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), +/* v9 */ fmovicc ("neg", CONDNEG, 0), +/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), +/* v9 */ fmovfcc ("o", FCONDO, 0), +/* v9 */ fmovicc ("pos", CONDPOS, 0), +/* v9 */ fmovfcc ("u", FCONDU, 0), +/* v9 */ fmovfcc ("ue", FCONDUE, 0), +/* v9 */ fmovfcc ("ug", FCONDUG, 0), +/* v9 */ fmovfcc ("uge", FCONDUGE, 0), +/* v9 */ fmovfcc ("ul", FCONDUL, 0), +/* v9 */ fmovfcc ("ule", FCONDULE, 0), +/* v9 */ fmovicc ("vc", CONDVC, 0), +/* v9 */ fmovicc ("vs", CONDVS, 0), +/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), + +#undef fmoviccx /* v9 */ +#undef fmovfccx /* v9 */ +#undef fmovccx /* v9 */ +#undef fmovicc /* v9 */ +#undef fmovfcc /* v9 */ +#undef fmovcc /* v9 */ +#undef FM_DF /* v9 */ +#undef FM_QF /* v9 */ +#undef FM_SF /* v9 */ + +/* Coprocessor branches. */ +#define CBR(opcode, mask, lose, flags, arch) \ + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \ + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch } + +/* Floating point branches. */ +#define FBR(opcode, mask, lose, flags) \ + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \ + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 } + +/* V9 extended floating point branches. */ +#define FBRX(opcode, mask, lose, flags) /* v9 */ \ + { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ + { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } + +/* v9: We must put `FBRX' before `FBR', to ensure that we never match + v9: something against an expression unless it is an expression. Otherwise, + v9: we end up with undefined symbol tables entries, because they get added, + v9: but are not deleted if the pattern fails to match. */ + +#define CONDFC(fop, cop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ + CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) + +#define CONDFCL(fop, cop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ + CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) + +#define CONDF(fop, mask, flags) \ + FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ + FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) + +CONDFC ("fb", "cb", 0x8, F_UNBR), +CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), +CONDFC ("fbe", "cb0", 0x9, F_CONDBR), +CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), +CONDFC ("fbg", "cb2", 0x6, F_CONDBR), +CONDFC ("fbge", "cb02", 0xb, F_CONDBR), +CONDFC ("fbl", "cb1", 0x4, F_CONDBR), +CONDFC ("fble", "cb01", 0xd, F_CONDBR), +CONDFC ("fblg", "cb12", 0x2, F_CONDBR), +CONDFCL ("fbn", "cbn", 0x0, F_UNBR), +CONDFC ("fbne", "cb123", 0x1, F_CONDBR), +CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), +CONDFC ("fbo", "cb012", 0xf, F_CONDBR), +CONDFC ("fbu", "cb3", 0x7, F_CONDBR), +CONDFC ("fbue", "cb03", 0xa, F_CONDBR), +CONDFC ("fbug", "cb23", 0x5, F_CONDBR), +CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), +CONDFC ("fbul", "cb13", 0x3, F_CONDBR), +CONDFC ("fbule", "cb013", 0xe, F_CONDBR), + +#undef CONDFC +#undef CONDFCL +#undef CONDF +#undef CBR +#undef FBR +#undef FBRX /* v9 */ + +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ +{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ +{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ + +{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ + +{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, +{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, +{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, +{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, + +{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, + +{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, +{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, +{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, + +{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, + +{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, +{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, + +/* This *is* a commutative instruction. */ +{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, +{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, +/* This *is* a commutative instruction. */ +{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, +{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, +{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, +{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, +{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, + +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ +{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ + +{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ +{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ + +/* FPop1 and FPop2 are not instructions. Don't accept them. */ + +{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, +{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, + +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 }, +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 }, + +{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, +{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, + +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 }, +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 }, + +{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, +{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, +{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, +{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, +{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, +{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, + +{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, +{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, +{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, +{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, +{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, +{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, + +{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, +{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, + +{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, +{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, +{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, + +{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, +{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, +{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, +{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, + +{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, +{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, +{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, +{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, +{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, +{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, +{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, + +#define CMPFCC(x) (((x)&0x3)<<25) + +{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, +{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, +{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, +{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, +{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, +{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, +{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, +{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, +{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, +{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, +{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, +{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, +{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, +{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, +{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, +{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, +{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, +{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, +{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, +{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, +{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, + +/* These Extended FPop (FIFO) instructions are new in the Fujitsu + MB86934, replacing the CPop instructions from v6 and later + processors. */ + +#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } +#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } +#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } + +EFPOP1_2 ("efitod", 0x0c8, "f,H"), +EFPOP1_2 ("efitos", 0x0c4, "f,g"), +EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), +EFPOP1_2 ("efstoi", 0x0d1, "f,g"), +EFPOP1_2 ("efstod", 0x0c9, "f,H"), +EFPOP1_2 ("efdtos", 0x0c6, "B,g"), +EFPOP1_2 ("efmovs", 0x001, "f,g"), +EFPOP1_2 ("efnegs", 0x005, "f,g"), +EFPOP1_2 ("efabss", 0x009, "f,g"), +EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), +EFPOP1_2 ("efsqrts", 0x029, "f,g"), +EFPOP1_3 ("efaddd", 0x042, "v,B,H"), +EFPOP1_3 ("efadds", 0x041, "e,f,g"), +EFPOP1_3 ("efsubd", 0x046, "v,B,H"), +EFPOP1_3 ("efsubs", 0x045, "e,f,g"), +EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), +EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), +EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), +EFPOP1_3 ("efmuls", 0x049, "e,f,g"), +EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), +EFPOP2_2 ("efcmpd", 0x052, "v,B"), +EFPOP2_2 ("efcmped", 0x056, "v,B"), +EFPOP2_2 ("efcmps", 0x051, "e,f"), +EFPOP2_2 ("efcmpes", 0x055, "e,f"), + +#undef EFPOP1_2 +#undef EFPOP1_3 +#undef EFPOP2_2 + +/* These are marked F_ALIAS, so that they won't conflict with sparclite insns + present. Otherwise, the F_ALIAS flag is ignored. */ +{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, +{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, + +/* sparclet specific insns */ + +COMMUTEOP ("umac", 0x3e, sparclet), +COMMUTEOP ("smac", 0x3f, sparclet), +COMMUTEOP ("umacd", 0x2e, sparclet), +COMMUTEOP ("smacd", 0x2f, sparclet), +COMMUTEOP ("umuld", 0x09, sparclet), +COMMUTEOP ("smuld", 0x0d, sparclet), + +{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, +{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, + +/* The manual isn't completely accurate on these insns. The `rs2' field is + treated as being 6 bits to account for 6 bit immediates to cpush. It is + assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ +#define BIT5 (1<<5) +{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, +{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, +{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, +{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, +{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, +{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, +{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, +#undef BIT5 + +/* sparclet coprocessor branch insns */ +#define SLCBCC2(opcode, mask, lose) \ + { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ + { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } +#define SLCBCC(opcode, mask) \ + SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) + +/* cbn,cba can't be defined here because they're defined elsewhere and GAS + requires all mnemonics of the same name to be consecutive. */ +/*SLCBCC("cbn", 0), - already defined */ +SLCBCC("cbe", 1), +SLCBCC("cbf", 2), +SLCBCC("cbef", 3), +SLCBCC("cbr", 4), +SLCBCC("cber", 5), +SLCBCC("cbfr", 6), +SLCBCC("cbefr", 7), +/*SLCBCC("cba", 8), - already defined */ +SLCBCC("cbne", 9), +SLCBCC("cbnf", 10), +SLCBCC("cbnef", 11), +SLCBCC("cbnr", 12), +SLCBCC("cbner", 13), +SLCBCC("cbnfr", 14), +SLCBCC("cbnefr", 15), + +#undef SLCBCC2 +#undef SLCBCC + +{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, +{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, +{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, +{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, + +/* v9 synthetic insns */ +{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ +{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ +{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ +{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ +{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ +{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ +{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ + +/* Ultrasparc extensions */ +{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, + +/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ +{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, +{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, +{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, +{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, +{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, +{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, +{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, +{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, + +{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, +{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, +{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, +{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, +{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, + +/* Note that the mixing of 32/64 bit regs is intentional. */ +{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, +{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, +{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, +{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, +{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, +{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, +{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, + +{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, +{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, +{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, + +{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, +{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, +{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, +{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, +{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, +{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, +{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, +{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, +{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, +{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, +{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, +{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, +{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, +{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, +{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, +{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, +{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, +{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, +{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, +{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, +{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, +{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, +{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, +{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, +{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, +{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, +{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, +{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, +{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, +{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, +{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, +{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, + +{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, +{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, +{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, +{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, +{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, +{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, +{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, +{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, + +{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, +{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, +{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, +{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, +{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, +{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, + +{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, + +{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, +{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, +{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, + +/* Cheetah instructions */ +{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, +{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, +{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, +{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, +{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, +{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, + +{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, +{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, + +{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, + +/* More v9 specific insns, these need to come last so they do not clash + with v9a instructions such as "edge8" which looks like impdep1. */ + +#define IMPDEP(name, code) \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ +{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ +{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } + +IMPDEP ("impdep1", 0x36), +IMPDEP ("impdep2", 0x37), + +#undef IMPDEP + +}; + +const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); + +/* Utilities for argument parsing. */ + +typedef struct +{ + int value; + const char *name; +} arg; + +/* Look up NAME in TABLE. */ + +static int +lookup_name (const arg *table, const char *name) +{ + const arg *p; + + for (p = table; p->name; ++p) + if (strcmp (name, p->name) == 0) + return p->value; + + return -1; +} + +/* Look up VALUE in TABLE. */ + +static const char * +lookup_value (const arg *table, int value) +{ + const arg *p; + + for (p = table; p->name; ++p) + if (value == p->value) + return p->name; + + return NULL; +} + +/* Handle ASI's. */ + +static arg asi_table[] = +{ + /* These are in the v9 architecture manual. */ + /* The shorter versions appear first, they're here because Sun's as has them. + Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the + UltraSPARC architecture manual). */ + { 0x04, "#ASI_N" }, + { 0x0c, "#ASI_N_L" }, + { 0x10, "#ASI_AIUP" }, + { 0x11, "#ASI_AIUS" }, + { 0x18, "#ASI_AIUP_L" }, + { 0x19, "#ASI_AIUS_L" }, + { 0x80, "#ASI_P" }, + { 0x81, "#ASI_S" }, + { 0x82, "#ASI_PNF" }, + { 0x83, "#ASI_SNF" }, + { 0x88, "#ASI_P_L" }, + { 0x89, "#ASI_S_L" }, + { 0x8a, "#ASI_PNF_L" }, + { 0x8b, "#ASI_SNF_L" }, + { 0x04, "#ASI_NUCLEUS" }, + { 0x0c, "#ASI_NUCLEUS_LITTLE" }, + { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, + { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, + { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, + { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, + { 0x80, "#ASI_PRIMARY" }, + { 0x81, "#ASI_SECONDARY" }, + { 0x82, "#ASI_PRIMARY_NOFAULT" }, + { 0x83, "#ASI_SECONDARY_NOFAULT" }, + { 0x88, "#ASI_PRIMARY_LITTLE" }, + { 0x89, "#ASI_SECONDARY_LITTLE" }, + { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, + { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, + /* These are UltraSPARC and Niagara extensions. */ + { 0x14, "#ASI_PHYS_USE_EC" }, + { 0x15, "#ASI_PHYS_BYPASS_EC_E" }, + { 0x16, "#ASI_BLK_AIUP_4V" }, + { 0x17, "#ASI_BLK_AIUS_4V" }, + { 0x1c, "#ASI_PHYS_USE_EC_L" }, + { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" }, + { 0x1e, "#ASI_BLK_AIUP_L_4V" }, + { 0x1f, "#ASI_BLK_AIUS_L_4V" }, + { 0x20, "#ASI_SCRATCHPAD" }, + { 0x21, "#ASI_MMU" }, + { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" }, + { 0x24, "#ASI_NUCLEUS_QUAD_LDD" }, + { 0x25, "#ASI_QUEUE" }, + { 0x26, "#ASI_QUAD_LDD_PHYS_4V" }, + { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" }, + { 0x30, "#ASI_PCACHE_DATA_STATUS" }, + { 0x31, "#ASI_PCACHE_DATA" }, + { 0x32, "#ASI_PCACHE_TAG" }, + { 0x33, "#ASI_PCACHE_SNOOP_TAG" }, + { 0x34, "#ASI_QUAD_LDD_PHYS" }, + { 0x38, "#ASI_WCACHE_VALID_BITS" }, + { 0x39, "#ASI_WCACHE_DATA" }, + { 0x3a, "#ASI_WCACHE_TAG" }, + { 0x3b, "#ASI_WCACHE_SNOOP_TAG" }, + { 0x3c, "#ASI_QUAD_LDD_PHYS_L" }, + { 0x40, "#ASI_SRAM_FAST_INIT" }, + { 0x41, "#ASI_CORE_AVAILABLE" }, + { 0x41, "#ASI_CORE_ENABLE_STAT" }, + { 0x41, "#ASI_CORE_ENABLE" }, + { 0x41, "#ASI_XIR_STEERING" }, + { 0x41, "#ASI_CORE_RUNNING_RW" }, + { 0x41, "#ASI_CORE_RUNNING_W1S" }, + { 0x41, "#ASI_CORE_RUNNING_W1C" }, + { 0x41, "#ASI_CORE_RUNNING_STAT" }, + { 0x41, "#ASI_CMT_ERROR_STEERING" }, + { 0x41, "#ASI_DCACHE_INVALIDATE" }, + { 0x41, "#ASI_DCACHE_UTAG" }, + { 0x41, "#ASI_DCACHE_SNOOP_TAG" }, + { 0x42, "#ASI_DCACHE_INVALIDATE" }, + { 0x43, "#ASI_DCACHE_UTAG" }, + { 0x44, "#ASI_DCACHE_SNOOP_TAG" }, + { 0x45, "#ASI_LSU_CONTROL_REG" }, + { 0x45, "#ASI_DCU_CONTROL_REG" }, + { 0x46, "#ASI_DCACHE_DATA" }, + { 0x47, "#ASI_DCACHE_TAG" }, + { 0x48, "#ASI_INTR_DISPATCH_STAT" }, + { 0x49, "#ASI_INTR_RECEIVE" }, + { 0x4a, "#ASI_UPA_CONFIG" }, + { 0x4a, "#ASI_JBUS_CONFIG" }, + { 0x4a, "#ASI_SAFARI_CONFIG" }, + { 0x4a, "#ASI_SAFARI_ADDRESS" }, + { 0x4b, "#ASI_ESTATE_ERROR_EN" }, + { 0x4c, "#ASI_AFSR" }, + { 0x4d, "#ASI_AFAR" }, + { 0x4e, "#ASI_EC_TAG_DATA" }, + { 0x50, "#ASI_IMMU" }, + { 0x51, "#ASI_IMMU_TSB_8KB_PTR" }, + { 0x52, "#ASI_IMMU_TSB_16KB_PTR" }, + { 0x54, "#ASI_ITLB_DATA_IN" }, + { 0x55, "#ASI_ITLB_DATA_ACCESS" }, + { 0x56, "#ASI_ITLB_TAG_READ" }, + { 0x57, "#ASI_IMMU_DEMAP" }, + { 0x58, "#ASI_DMMU" }, + { 0x59, "#ASI_DMMU_TSB_8KB_PTR" }, + { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" }, + { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" }, + { 0x5c, "#ASI_DTLB_DATA_IN" }, + { 0x5d, "#ASI_DTLB_DATA_ACCESS" }, + { 0x5e, "#ASI_DTLB_TAG_READ" }, + { 0x5f, "#ASI_DMMU_DEMAP" }, + { 0x60, "#ASI_IIU_INST_TRAP" }, + { 0x63, "#ASI_INTR_ID" }, + { 0x63, "#ASI_CORE_ID" }, + { 0x63, "#ASI_CESR_ID" }, + { 0x66, "#ASI_IC_INSTR" }, + { 0x67, "#ASI_IC_TAG" }, + { 0x68, "#ASI_IC_STAG" }, + { 0x6e, "#ASI_IC_PRE_DECODE" }, + { 0x6f, "#ASI_IC_NEXT_FIELD" }, + { 0x6f, "#ASI_BRPRED_ARRAY" }, + { 0x70, "#ASI_BLK_AIUP" }, + { 0x71, "#ASI_BLK_AIUS" }, + { 0x72, "#ASI_MCU_CTRL_REG" }, + { 0x74, "#ASI_EC_DATA" }, + { 0x75, "#ASI_EC_CTRL" }, + { 0x76, "#ASI_EC_W" }, + { 0x77, "#ASI_UDB_ERROR_W" }, + { 0x77, "#ASI_UDB_CONTROL_W" }, + { 0x77, "#ASI_INTR_W" }, + { 0x77, "#ASI_INTR_DATAN_W" }, + { 0x77, "#ASI_INTR_DISPATCH_W" }, + { 0x78, "#ASI_BLK_AIUPL" }, + { 0x79, "#ASI_BLK_AIUSL" }, + { 0x7e, "#ASI_EC_R" }, + { 0x7f, "#ASI_UDBH_ERROR_R" }, + { 0x7f, "#ASI_UDBL_ERROR_R" }, + { 0x7f, "#ASI_UDBH_CONTROL_R" }, + { 0x7f, "#ASI_UDBL_CONTROL_R" }, + { 0x7f, "#ASI_INTR_R" }, + { 0x7f, "#ASI_INTR_DATAN_R" }, + { 0xc0, "#ASI_PST8_P" }, + { 0xc1, "#ASI_PST8_S" }, + { 0xc2, "#ASI_PST16_P" }, + { 0xc3, "#ASI_PST16_S" }, + { 0xc4, "#ASI_PST32_P" }, + { 0xc5, "#ASI_PST32_S" }, + { 0xc8, "#ASI_PST8_PL" }, + { 0xc9, "#ASI_PST8_SL" }, + { 0xca, "#ASI_PST16_PL" }, + { 0xcb, "#ASI_PST16_SL" }, + { 0xcc, "#ASI_PST32_PL" }, + { 0xcd, "#ASI_PST32_SL" }, + { 0xd0, "#ASI_FL8_P" }, + { 0xd1, "#ASI_FL8_S" }, + { 0xd2, "#ASI_FL16_P" }, + { 0xd3, "#ASI_FL16_S" }, + { 0xd8, "#ASI_FL8_PL" }, + { 0xd9, "#ASI_FL8_SL" }, + { 0xda, "#ASI_FL16_PL" }, + { 0xdb, "#ASI_FL16_SL" }, + { 0xe0, "#ASI_BLK_COMMIT_P", }, + { 0xe1, "#ASI_BLK_COMMIT_S", }, + { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" }, + { 0xf0, "#ASI_BLK_P", }, + { 0xf1, "#ASI_BLK_S", }, + { 0xf8, "#ASI_BLK_PL", }, + { 0xf9, "#ASI_BLK_SL", }, + { 0, 0 } +}; + +/* Return the value for ASI NAME, or -1 if not found. */ + +int +sparc_encode_asi (const char *name) +{ + return lookup_name (asi_table, name); +} + +/* Return the name for ASI value VALUE or NULL if not found. */ + +const char * +sparc_decode_asi (int value) +{ + return lookup_value (asi_table, value); +} + +/* Handle membar masks. */ + +static arg membar_table[] = +{ + { 0x40, "#Sync" }, + { 0x20, "#MemIssue" }, + { 0x10, "#Lookaside" }, + { 0x08, "#StoreStore" }, + { 0x04, "#LoadStore" }, + { 0x02, "#StoreLoad" }, + { 0x01, "#LoadLoad" }, + { 0, 0 } +}; + +/* Return the value for membar arg NAME, or -1 if not found. */ + +int +sparc_encode_membar (const char *name) +{ + return lookup_name (membar_table, name); +} + +/* Return the name for membar value VALUE or NULL if not found. */ + +const char * +sparc_decode_membar (int value) +{ + return lookup_value (membar_table, value); +} + +/* Handle prefetch args. */ + +static arg prefetch_table[] = +{ + { 0, "#n_reads" }, + { 1, "#one_read" }, + { 2, "#n_writes" }, + { 3, "#one_write" }, + { 4, "#page" }, + { 16, "#invalidate" }, + { 17, "#unified", }, + { 20, "#n_reads_strong", }, + { 21, "#one_read_strong", }, + { 22, "#n_writes_strong", }, + { 23, "#one_write_strong", }, + { 0, 0 } +}; + +/* Return the value for prefetch arg NAME, or -1 if not found. */ + +int +sparc_encode_prefetch (const char *name) +{ + return lookup_name (prefetch_table, name); +} + +/* Return the name for prefetch value VALUE or NULL if not found. */ + +const char * +sparc_decode_prefetch (int value) +{ + return lookup_value (prefetch_table, value); +} + +/* Handle sparclet coprocessor registers. */ + +static arg sparclet_cpreg_table[] = +{ + { 0, "%ccsr" }, + { 1, "%ccfr" }, + { 2, "%cccrcr" }, + { 3, "%ccpr" }, + { 4, "%ccsr2" }, + { 5, "%cccrr" }, + { 6, "%ccrstr" }, + { 0, 0 } +}; + +/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ + +int +sparc_encode_sparclet_cpreg (const char *name) +{ + return lookup_name (sparclet_cpreg_table, name); +} + +/* Return the name for sparclet cpreg value VALUE or NULL if not found. */ + +const char * +sparc_decode_sparclet_cpreg (int value) +{ + return lookup_value (sparclet_cpreg_table, value); +} diff --git a/external/gpl3/gdb/dist/opcodes/spu-dis.c b/external/gpl3/gdb/dist/opcodes/spu-dis.c new file mode 100644 index 000000000000..3e6a7620f2c3 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/spu-dis.c @@ -0,0 +1,261 @@ +/* Disassemble SPU instructions + + Copyright 2006, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/spu.h" + +/* This file provides a disassembler function which uses + the disassembler interface defined in dis-asm.h. */ + +extern const struct spu_opcode spu_opcodes[]; +extern const int spu_num_opcodes; + +static const struct spu_opcode *spu_disassemble_table[(1<<11)]; + +static void +init_spu_disassemble (void) +{ + int i; + + /* If two instructions have the same opcode then we prefer the first + * one. In most cases it is just an alternate mnemonic. */ + for (i = 0; i < spu_num_opcodes; i++) + { + int o = spu_opcodes[i].opcode; + if (o >= (1 << 11)) + abort (); + if (spu_disassemble_table[o] == 0) + spu_disassemble_table[o] = &spu_opcodes[i]; + } +} + +/* Determine the instruction from the 10 least significant bits. */ +static const struct spu_opcode * +get_index_for_opcode (unsigned int insn) +{ + const struct spu_opcode *op_index; + unsigned int opcode = insn >> (32-11); + + /* Init the table. This assumes that element 0/opcode 0 (currently + * NOP) is always used */ + if (spu_disassemble_table[0] == 0) + init_spu_disassemble (); + + if ((op_index = spu_disassemble_table[opcode & 0x780]) != 0 + && op_index->insn_type == RRR) + return op_index; + + if ((op_index = spu_disassemble_table[opcode & 0x7f0]) != 0 + && (op_index->insn_type == RI18 || op_index->insn_type == LBT)) + return op_index; + + if ((op_index = spu_disassemble_table[opcode & 0x7f8]) != 0 + && op_index->insn_type == RI10) + return op_index; + + if ((op_index = spu_disassemble_table[opcode & 0x7fc]) != 0 + && (op_index->insn_type == RI16)) + return op_index; + + if ((op_index = spu_disassemble_table[opcode & 0x7fe]) != 0 + && (op_index->insn_type == RI8)) + return op_index; + + if ((op_index = spu_disassemble_table[opcode & 0x7ff]) != 0) + return op_index; + + return 0; +} + +/* Print a Spu instruction. */ + +int +print_insn_spu (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int value; + int hex_value; + int status; + unsigned int insn; + const struct spu_opcode *op_index; + enum spu_insns tag; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + + op_index = get_index_for_opcode (insn); + + if (op_index == 0) + { + (*info->fprintf_func) (info->stream, ".long 0x%x", insn); + } + else + { + int i; + int paren = 0; + tag = (enum spu_insns)(op_index - spu_opcodes); + (*info->fprintf_func) (info->stream, "%s", op_index->mnemonic); + if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED + || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ + || tag == M_SYNC || tag == M_HBR) + { + int fb = (insn >> (32-18)) & 0x7f; + if (fb & 0x40) + (*info->fprintf_func) (info->stream, tag == M_SYNC ? "c" : "p"); + if (fb & 0x20) + (*info->fprintf_func) (info->stream, "d"); + if (fb & 0x10) + (*info->fprintf_func) (info->stream, "e"); + } + if (op_index->arg[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + hex_value = 0; + for (i = 1; i <= op_index->arg[0]; i++) + { + int arg = op_index->arg[i]; + if (arg != A_P && !paren && i > 1) + (*info->fprintf_func) (info->stream, ","); + + switch (arg) + { + case A_T: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RT (insn)); + break; + case A_A: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RA (insn)); + break; + case A_B: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RB (insn)); + break; + case A_C: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RC (insn)); + break; + case A_S: + (*info->fprintf_func) (info->stream, "$sp%d", + DECODE_INSN_RA (insn)); + break; + case A_H: + (*info->fprintf_func) (info->stream, "$ch%d", + DECODE_INSN_RA (insn)); + break; + case A_P: + paren++; + (*info->fprintf_func) (info->stream, "("); + break; + case A_U7A: + (*info->fprintf_func) (info->stream, "%d", + 173 - DECODE_INSN_U8 (insn)); + break; + case A_U7B: + (*info->fprintf_func) (info->stream, "%d", + 155 - DECODE_INSN_U8 (insn)); + break; + case A_S3: + case A_S6: + case A_S7: + case A_S7N: + case A_U3: + case A_U5: + case A_U6: + case A_U7: + hex_value = DECODE_INSN_I7 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S11: + (*info->print_address_func) (memaddr + DECODE_INSN_I9a (insn) * 4, + info); + break; + case A_S11I: + (*info->print_address_func) (memaddr + DECODE_INSN_I9b (insn) * 4, + info); + break; + case A_S10: + case A_S10B: + hex_value = DECODE_INSN_I10 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S14: + hex_value = DECODE_INSN_I10 (insn) * 16; + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S16: + hex_value = DECODE_INSN_I16 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_X16: + hex_value = DECODE_INSN_U16 (insn); + (*info->fprintf_func) (info->stream, "%u", hex_value); + break; + case A_R18: + value = DECODE_INSN_I16 (insn) * 4; + if (value == 0) + (*info->fprintf_func) (info->stream, "%d", value); + else + { + hex_value = memaddr + value; + (*info->print_address_func) (hex_value & 0x3ffff, info); + } + break; + case A_S18: + value = DECODE_INSN_U16 (insn) * 4; + if (value == 0) + (*info->fprintf_func) (info->stream, "%d", value); + else + (*info->print_address_func) (value, info); + break; + case A_U18: + value = DECODE_INSN_U18 (insn); + if (value == 0 || !(*info->symbol_at_address_func)(0, info)) + { + hex_value = value; + (*info->fprintf_func) (info->stream, "%u", value); + } + else + (*info->print_address_func) (value, info); + break; + case A_U14: + hex_value = DECODE_INSN_U14 (insn); + (*info->fprintf_func) (info->stream, "%u", hex_value); + break; + } + if (arg != A_P && paren) + { + (*info->fprintf_func) (info->stream, ")"); + paren--; + } + } + if (hex_value > 16) + (*info->fprintf_func) (info->stream, "\t# %x", hex_value); + } + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/spu-opc.c b/external/gpl3/gdb/dist/opcodes/spu-opc.c new file mode 100644 index 000000000000..bd1a844d9ac6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/spu-opc.c @@ -0,0 +1,45 @@ +/* SPU opcode list + + Copyright 2006, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "opcode/spu.h" + +/* This file holds the Spu opcode table */ + + +/* + Example contents of spu-insn.h + id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction + QUAD WORD (0,RC,RB,RA,RT) latency + APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form + */ + +const struct spu_opcode spu_opcodes[] = { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT }, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT }, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB +}; + +const int spu_num_opcodes = + sizeof (spu_opcodes) / sizeof (spu_opcodes[0]); diff --git a/external/gpl3/gdb/dist/opcodes/stamp-h.in b/external/gpl3/gdb/dist/opcodes/stamp-h.in new file mode 100644 index 000000000000..9788f70238c9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/stamp-h.in @@ -0,0 +1 @@ +timestamp diff --git a/external/gpl3/gdb/dist/opcodes/sysdep.h b/external/gpl3/gdb/dist/opcodes/sysdep.h new file mode 100644 index 000000000000..2ca393506752 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/sysdep.h @@ -0,0 +1,48 @@ +/* Random host-dependent support code. + Copyright 1995, 1997, 2000, 2005, 2007 Free Software Foundation, Inc. + Written by Ken Raeburn. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +/* Do system-dependent stuff, mainly driven by autoconf-detected info. + + Well, some generic common stuff is done here too, like including + ansidecl.h. That's because the .h files in bfd/hosts files I'm + trying to replace often did that. If it can be dropped from this + file (check in a non-ANSI environment!), it should be. */ + +#include "config.h" + +#include "ansidecl.h" + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +#if !HAVE_DECL_STPCPY +extern char *stpcpy (char *__dest, const char *__src); +#endif diff --git a/external/gpl3/gdb/dist/opcodes/tic30-dis.c b/external/gpl3/gdb/dist/opcodes/tic30-dis.c new file mode 100644 index 000000000000..c6d0e3ed7238 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic30-dis.c @@ -0,0 +1,717 @@ +/* Disassembly routines for TMS320C30 architecture + Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic30.h" + +#define NORMAL_INSN 1 +#define PARALLEL_INSN 2 + +/* Gets the type of instruction based on the top 2 or 3 bits of the + instruction word. */ +#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) + +/* Instruction types. */ +#define TWO_OPERAND_1 0x00000000 +#define TWO_OPERAND_2 0x40000000 +#define THREE_OPERAND 0x20000000 +#define PAR_STORE 0xC0000000 +#define MUL_ADDS 0x80000000 +#define BRANCHES 0x60000000 + +/* Specific instruction id bits. */ +#define NORMAL_IDEN 0x1F800000 +#define PAR_STORE_IDEN 0x3E000000 +#define MUL_ADD_IDEN 0x2C000000 +#define BR_IMM_IDEN 0x1F000000 +#define BR_COND_IDEN 0x1C3F0000 + +/* Addressing modes. */ +#define AM_REGISTER 0x00000000 +#define AM_DIRECT 0x00200000 +#define AM_INDIRECT 0x00400000 +#define AM_IMM 0x00600000 + +#define P_FIELD 0x03000000 + +#define REG_AR0 0x08 +#define LDP_INSN 0x08700000 + +/* TMS320C30 program counter for current instruction. */ +static unsigned int _pc; + +struct instruction +{ + int type; + insn_template *tm; + partemplate *ptm; +}; + +static int +get_tic30_instruction (unsigned long insn_word, struct instruction *insn) +{ + switch (GET_TYPE (insn_word)) + { + case TWO_OPERAND_1: + case TWO_OPERAND_2: + case THREE_OPERAND: + insn->type = NORMAL_INSN; + { + insn_template *current_optab = (insn_template *) tic30_optab; + + for (; current_optab < tic30_optab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if (current_optab->operands == 0) + { + if (current_optab->base_opcode == insn_word) + { + insn->tm = current_optab; + break; + } + } + else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) + { + insn->tm = current_optab; + break; + } + } + } + } + break; + + case PAR_STORE: + insn->type = PARALLEL_INSN; + { + partemplate *current_optab = (partemplate *) tic30_paroptab; + + for (; current_optab < tic30_paroptab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if ((current_optab->base_opcode & PAR_STORE_IDEN) + == (insn_word & PAR_STORE_IDEN)) + { + insn->ptm = current_optab; + break; + } + } + } + } + break; + + case MUL_ADDS: + insn->type = PARALLEL_INSN; + { + partemplate *current_optab = (partemplate *) tic30_paroptab; + + for (; current_optab < tic30_paroptab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if ((current_optab->base_opcode & MUL_ADD_IDEN) + == (insn_word & MUL_ADD_IDEN)) + { + insn->ptm = current_optab; + break; + } + } + } + } + break; + + case BRANCHES: + insn->type = NORMAL_INSN; + { + insn_template *current_optab = (insn_template *) tic30_optab; + + for (; current_optab < tic30_optab_end; current_optab++) + { + if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) + { + if (current_optab->operand_types[0] & Imm24) + { + if ((current_optab->base_opcode & BR_IMM_IDEN) + == (insn_word & BR_IMM_IDEN)) + { + insn->tm = current_optab; + break; + } + } + else if (current_optab->operands > 0) + { + if ((current_optab->base_opcode & BR_COND_IDEN) + == (insn_word & BR_COND_IDEN)) + { + insn->tm = current_optab; + break; + } + } + else + { + if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) + == (insn_word & (BR_COND_IDEN | 0x00800000))) + { + insn->tm = current_optab; + break; + } + } + } + } + } + break; + default: + return 0; + } + return 1; +} + +static int +get_register_operand (unsigned char fragment, char *buffer) +{ + const reg *current_reg = tic30_regtab; + + if (buffer == NULL) + return 0; + for (; current_reg < tic30_regtab_end; current_reg++) + { + if ((fragment & 0x1F) == current_reg->opcode) + { + strcpy (buffer, current_reg->name); + return 1; + } + } + return 0; +} + +static int +get_indirect_operand (unsigned short fragment, + int size, + char *buffer) +{ + unsigned char mod; + unsigned arnum; + unsigned char disp; + + if (buffer == NULL) + return 0; + /* Determine which bits identify the sections of the indirect + operand based on the size in bytes. */ + switch (size) + { + case 1: + mod = (fragment & 0x00F8) >> 3; + arnum = (fragment & 0x0007); + disp = 0; + break; + case 2: + mod = (fragment & 0xF800) >> 11; + arnum = (fragment & 0x0700) >> 8; + disp = (fragment & 0x00FF); + break; + default: + return 0; + } + { + const ind_addr_type *current_ind = tic30_indaddr_tab; + + for (; current_ind < tic30_indaddrtab_end; current_ind++) + { + if (current_ind->modfield == mod) + { + if (current_ind->displacement == IMPLIED_DISP && size == 2) + continue; + + else + { + size_t i, len; + int bufcnt; + + len = strlen (current_ind->syntax); + for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) + { + buffer[bufcnt] = current_ind->syntax[i]; + if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') + buffer[++bufcnt] = arnum + '0'; + if (buffer[bufcnt] == '(' + && current_ind->displacement == DISP_REQUIRED) + { + sprintf (&buffer[bufcnt + 1], "%u", disp); + bufcnt += strlen (&buffer[bufcnt + 1]); + } + } + buffer[bufcnt + 1] = '\0'; + break; + } + } + } + } + return 1; +} + +static int +cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat) +{ + unsigned long exponent, sign, mant; + union + { + unsigned long l; + float f; + } val; + + if (size == 2) + { + if ((tmsfloat & 0x0000F000) == 0x00008000) + tmsfloat = 0x80000000; + else + { + tmsfloat <<= 16; + tmsfloat = (long) tmsfloat >> 4; + } + } + exponent = tmsfloat & 0xFF000000; + if (exponent == 0x80000000) + { + *ieeefloat = 0.0; + return 1; + } + exponent += 0x7F000000; + sign = (tmsfloat & 0x00800000) << 8; + mant = tmsfloat & 0x007FFFFF; + if (exponent == 0xFF000000) + { + if (mant == 0) + *ieeefloat = ERANGE; +#ifdef HUGE_VALF + if (sign == 0) + *ieeefloat = HUGE_VALF; + else + *ieeefloat = -HUGE_VALF; +#else + if (sign == 0) + *ieeefloat = 1.0 / 0.0; + else + *ieeefloat = -1.0 / 0.0; +#endif + return 1; + } + exponent >>= 1; + if (sign) + { + mant = (~mant) & 0x007FFFFF; + mant += 1; + exponent += mant & 0x00800000; + exponent &= 0x7F800000; + mant &= 0x007FFFFF; + } + if (tmsfloat == 0x80000000) + sign = mant = exponent = 0; + tmsfloat = sign | exponent | mant; + val.l = tmsfloat; + *ieeefloat = val.f; + return 1; +} + +static int +print_two_operand (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) +{ + char name[12]; + char operand[2][13] = + { + {0}, + {0} + }; + float f_number; + + if (insn->tm == NULL) + return 0; + strcpy (name, insn->tm->name); + if (insn->tm->opcode_modifier == AddressMode) + { + int src_op, dest_op; + /* Determine whether instruction is a store or a normal instruction. */ + if ((insn->tm->operand_types[1] & (Direct | Indirect)) + == (Direct | Indirect)) + { + src_op = 1; + dest_op = 0; + } + else + { + src_op = 0; + dest_op = 1; + } + /* Get the destination register. */ + if (insn->tm->operands == 2) + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); + /* Get the source operand based on addressing mode. */ + switch (insn_word & AddressMode) + { + case AM_REGISTER: + /* Check for the NOP instruction before getting the operand. */ + if ((insn->tm->operand_types[0] & NotReq) == 0) + get_register_operand ((insn_word & 0x0000001F), operand[src_op]); + break; + case AM_DIRECT: + sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); + break; + case AM_INDIRECT: + get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); + break; + case AM_IMM: + /* Get the value of the immediate operand based on variable type. */ + switch (insn->tm->imm_arg_type) + { + case Imm_Float: + cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); + sprintf (operand[src_op], "%2.2f", f_number); + break; + case Imm_SInt: + sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); + break; + case Imm_UInt: + sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); + break; + default: + return 0; + } + /* Handle special case for LDP instruction. */ + if ((insn_word & 0xFFFFFF00) == LDP_INSN) + { + strcpy (name, "ldp"); + sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); + operand[1][0] = '\0'; + } + } + } + /* Handle case for stack and rotate instructions. */ + else if (insn->tm->operands == 1) + { + if (insn->tm->opcode_modifier == StackOp) + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); + } + /* Output instruction to stream. */ + info->fprintf_func (info->stream, " %s %s%c%s", name, + operand[0][0] ? operand[0] : "", + operand[1][0] ? ',' : ' ', + operand[1][0] ? operand[1] : ""); + return 1; +} + +static int +print_three_operand (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) +{ + char operand[3][13] = + { + {0}, + {0}, + {0} + }; + + if (insn->tm == NULL) + return 0; + switch (insn_word & AddressMode) + { + case AM_REGISTER: + get_register_operand ((insn_word & 0x000000FF), operand[0]); + get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); + break; + case AM_DIRECT: + get_register_operand ((insn_word & 0x000000FF), operand[0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); + break; + case AM_INDIRECT: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); + get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); + break; + case AM_IMM: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); + break; + default: + return 0; + } + if (insn->tm->operands == 3) + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); + info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, + operand[0], operand[1], + operand[2][0] ? ',' : ' ', + operand[2][0] ? operand[2] : ""); + return 1; +} + +static int +print_par_insn (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) +{ + size_t i, len; + char *name1, *name2; + char operand[2][3][13] = + { + { + {0}, + {0}, + {0} + }, + { + {0}, + {0}, + {0} + } + }; + + if (insn->ptm == NULL) + return 0; + /* Parse out the names of each of the parallel instructions from the + q_insn1_insn2 format. */ + name1 = (char *) strdup (insn->ptm->name + 2); + name2 = ""; + len = strlen (name1); + for (i = 0; i < len; i++) + { + if (name1[i] == '_') + { + name2 = &name1[i + 1]; + name1[i] = '\0'; + break; + } + } + /* Get the operands of the instruction based on the operand order. */ + switch (insn->ptm->oporder) + { + case OO_4op1: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); + break; + case OO_4op2: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); + break; + case OO_4op3: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); + break; + case OO_5op1: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); + break; + case OO_5op2: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); + get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); + break; + case OO_PField: + if (insn_word & 0x00800000) + get_register_operand (0x01, operand[0][2]); + else + get_register_operand (0x00, operand[0][2]); + if (insn_word & 0x00400000) + get_register_operand (0x03, operand[1][2]); + else + get_register_operand (0x02, operand[1][2]); + switch (insn_word & P_FIELD) + { + case 0x00000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); + break; + case 0x01000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + break; + case 0x02000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); + break; + case 0x03000000: + get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); + get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); + get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); + get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); + break; + } + break; + default: + return 0; + } + info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, + operand[0][0], operand[0][1], + operand[0][2][0] ? ',' : ' ', + operand[0][2][0] ? operand[0][2] : ""); + info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, + operand[1][0], operand[1][1], + operand[1][2][0] ? ',' : ' ', + operand[1][2][0] ? operand[1][2] : ""); + free (name1); + return 1; +} + +static int +print_branch (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) +{ + char operand[2][13] = + { + {0}, + {0} + }; + unsigned long address; + int print_label = 0; + + if (insn->tm == NULL) + return 0; + /* Get the operands for 24-bit immediate jumps. */ + if (insn->tm->operand_types[0] & Imm24) + { + address = insn_word & 0x00FFFFFF; + sprintf (operand[0], "0x%lX", address); + print_label = 1; + } + /* Get the operand for the trap instruction. */ + else if (insn->tm->operand_types[0] & IVector) + { + address = insn_word & 0x0000001F; + sprintf (operand[0], "0x%lX", address); + } + else + { + address = insn_word & 0x0000FFFF; + /* Get the operands for the DB instructions. */ + if (insn->tm->operands == 2) + { + get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); + if (insn_word & PCRel) + { + sprintf (operand[1], "%d", (short) address); + print_label = 1; + } + else + get_register_operand (insn_word & 0x0000001F, operand[1]); + } + /* Get the operands for the standard branches. */ + else if (insn->tm->operands == 1) + { + if (insn_word & PCRel) + { + address = (short) address; + sprintf (operand[0], "%ld", address); + print_label = 1; + } + else + get_register_operand (insn_word & 0x0000001F, operand[0]); + } + } + info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, + operand[0][0] ? operand[0] : "", + operand[1][0] ? ',' : ' ', + operand[1][0] ? operand[1] : ""); + /* Print destination of branch in relation to current symbol. */ + if (print_label && info->symbols) + { + asymbol *sym = *info->symbols; + + if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) + { + address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); + /* Check for delayed instruction, if so adjust destination. */ + if (insn_word & 0x00200000) + address += 2; + } + else + { + address -= ((sym->section->vma + sym->value) / 4); + } + if (address == 0) + info->fprintf_func (info->stream, " <%s>", sym->name); + else + info->fprintf_func (info->stream, " <%s %c %d>", sym->name, + ((short) address < 0) ? '-' : '+', + abs (address)); + } + return 1; +} + +int +print_insn_tic30 (bfd_vma pc, disassemble_info *info) +{ + unsigned long insn_word; + struct instruction insn = { 0, NULL, NULL }; + bfd_vma bufaddr = pc - info->buffer_vma; + + /* Obtain the current instruction word from the buffer. */ + insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | + (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); + _pc = pc / 4; + /* Get the instruction refered to by the current instruction word + and print it out based on its type. */ + if (!get_tic30_instruction (insn_word, &insn)) + return -1; + switch (GET_TYPE (insn_word)) + { + case TWO_OPERAND_1: + case TWO_OPERAND_2: + if (!print_two_operand (info, insn_word, &insn)) + return -1; + break; + case THREE_OPERAND: + if (!print_three_operand (info, insn_word, &insn)) + return -1; + break; + case PAR_STORE: + case MUL_ADDS: + if (!print_par_insn (info, insn_word, &insn)) + return -1; + break; + case BRANCHES: + if (!print_branch (info, insn_word, &insn)) + return -1; + break; + } + return 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/tic4x-dis.c b/external/gpl3/gdb/dist/opcodes/tic4x-dis.c new file mode 100644 index 000000000000..4e15070c5948 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic4x-dis.c @@ -0,0 +1,771 @@ +/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. + + Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "libiberty.h" +#include "dis-asm.h" +#include "opcode/tic4x.h" + +#define TIC4X_DEBUG 0 + +#define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */ +#define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */ + +typedef enum +{ + IMMED_SINT, + IMMED_SUINT, + IMMED_SFLOAT, + IMMED_INT, + IMMED_UINT, + IMMED_FLOAT +} +immed_t; + +typedef enum +{ + INDIRECT_SHORT, + INDIRECT_LONG, + INDIRECT_TIC4X +} +indirect_t; + +static int tic4x_version = 0; +static int tic4x_dp = 0; + +static int +tic4x_pc_offset (unsigned int op) +{ + /* Determine the PC offset for a C[34]x instruction. + This could be simplified using some boolean algebra + but at the expense of readability. */ + switch (op >> 24) + { + case 0x60: /* br */ + case 0x62: /* call (C4x) */ + case 0x64: /* rptb (C4x) */ + return 1; + case 0x61: /* brd */ + case 0x63: /* laj */ + case 0x65: /* rptbd (C4x) */ + return 3; + case 0x66: /* swi */ + case 0x67: + return 0; + default: + break; + } + + switch ((op & 0xffe00000) >> 20) + { + case 0x6a0: /* bB */ + case 0x720: /* callB */ + case 0x740: /* trapB */ + return 1; + + case 0x6a2: /* bBd */ + case 0x6a6: /* bBat */ + case 0x6aa: /* bBaf */ + case 0x722: /* lajB */ + case 0x748: /* latB */ + case 0x798: /* rptbd */ + return 3; + + default: + break; + } + + switch ((op & 0xfe200000) >> 20) + { + case 0x6e0: /* dbB */ + return 1; + + case 0x6e2: /* dbBd */ + return 3; + + default: + break; + } + + return 0; +} + +static int +tic4x_print_char (struct disassemble_info * info, char ch) +{ + if (info != NULL) + (*info->fprintf_func) (info->stream, "%c", ch); + return 1; +} + +static int +tic4x_print_str (struct disassemble_info *info, char *str) +{ + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", str); + return 1; +} + +static int +tic4x_print_register (struct disassemble_info *info, unsigned long regno) +{ + static tic4x_register_t ** registertable = NULL; + unsigned int i; + + if (registertable == NULL) + { + registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE); + for (i = 0; i < tic3x_num_registers; i++) + registertable[tic3x_registers[i].regno] = (tic4x_register_t *) (tic3x_registers + i); + if (IS_CPU_TIC4X (tic4x_version)) + { + /* Add C4x additional registers, overwriting + any C3x registers if necessary. */ + for (i = 0; i < tic4x_num_registers; i++) + registertable[tic4x_registers[i].regno] = + (tic4x_register_t *)(tic4x_registers + i); + } + } + if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX)) + return 0; + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name); + return 1; +} + +static int +tic4x_print_addr (struct disassemble_info *info, unsigned long addr) +{ + if (info != NULL) + (*info->print_address_func)(addr, info); + return 1; +} + +static int +tic4x_print_relative (struct disassemble_info *info, + unsigned long pc, + long offset, + unsigned long opcode) +{ + return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode)); +} + +static int +tic4x_print_direct (struct disassemble_info *info, unsigned long arg) +{ + if (info != NULL) + { + (*info->fprintf_func) (info->stream, "@"); + tic4x_print_addr (info, arg + (tic4x_dp << 16)); + } + return 1; +} +#if 0 +/* FIXME: make the floating point stuff not rely on host + floating point arithmetic. */ + +static void +tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc) +{ + int e; + int s; + int f; + double num = 0.0; + + e = EXTRS (val, 31, 24); /* Exponent. */ + if (e != -128) + { + s = EXTRU (val, 23, 23); /* Sign bit. */ + f = EXTRU (val, 22, 0); /* Mantissa. */ + if (s) + f += -2 * (1 << 23); + else + f += (1 << 23); + num = f / (double)(1 << 23); + num = ldexp (num, e); + } + (*pfunc)(stream, "%.9g", num); +} +#endif + +static int +tic4x_print_immed (struct disassemble_info *info, + immed_t type, + unsigned long arg) +{ + int s; + int f; + int e; + double num = 0.0; + + if (info == NULL) + return 1; + switch (type) + { + case IMMED_SINT: + case IMMED_INT: + (*info->fprintf_func) (info->stream, "%ld", (long) arg); + break; + + case IMMED_SUINT: + case IMMED_UINT: + (*info->fprintf_func) (info->stream, "%lu", arg); + break; + + case IMMED_SFLOAT: + e = EXTRS (arg, 15, 12); + if (e != -8) + { + s = EXTRU (arg, 11, 11); + f = EXTRU (arg, 10, 0); + if (s) + f += -2 * (1 << 11); + else + f += (1 << 11); + num = f / (double)(1 << 11); + num = ldexp (num, e); + } + (*info->fprintf_func) (info->stream, "%f", num); + break; + case IMMED_FLOAT: + e = EXTRS (arg, 31, 24); + if (e != -128) + { + s = EXTRU (arg, 23, 23); + f = EXTRU (arg, 22, 0); + if (s) + f += -2 * (1 << 23); + else + f += (1 << 23); + num = f / (double)(1 << 23); + num = ldexp (num, e); + } + (*info->fprintf_func) (info->stream, "%f", num); + break; + } + return 1; +} + +static int +tic4x_print_cond (struct disassemble_info *info, unsigned int cond) +{ + static tic4x_cond_t **condtable = NULL; + unsigned int i; + + if (condtable == NULL) + { + condtable = xmalloc (sizeof (tic4x_cond_t *) * 32); + for (i = 0; i < tic4x_num_conds; i++) + condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i); + } + if (cond > 31 || condtable[cond] == NULL) + return 0; + if (info != NULL) + (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name); + return 1; +} + +static int +tic4x_print_indirect (struct disassemble_info *info, + indirect_t type, + unsigned long arg) +{ + unsigned int aregno; + unsigned int modn; + unsigned int disp; + char *a; + + aregno = 0; + modn = 0; + disp = 1; + switch(type) + { + case INDIRECT_TIC4X: /* *+ARn(disp) */ + disp = EXTRU (arg, 7, 3); + aregno = EXTRU (arg, 2, 0) + REG_AR0; + modn = 0; + break; + case INDIRECT_SHORT: + disp = 1; + aregno = EXTRU (arg, 2, 0) + REG_AR0; + modn = EXTRU (arg, 7, 3); + break; + case INDIRECT_LONG: + disp = EXTRU (arg, 7, 0); + aregno = EXTRU (arg, 10, 8) + REG_AR0; + modn = EXTRU (arg, 15, 11); + if (modn > 7 && disp != 0) + return 0; + break; + default: + (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type); + return 0; + } + if (modn > TIC3X_MODN_MAX) + return 0; + a = tic4x_indirects[modn].name; + while (*a) + { + switch (*a) + { + case 'a': + tic4x_print_register (info, aregno); + break; + case 'd': + tic4x_print_immed (info, IMMED_UINT, disp); + break; + case 'y': + tic4x_print_str (info, "ir0"); + break; + case 'z': + tic4x_print_str (info, "ir1"); + break; + default: + tic4x_print_char (info, *a); + break; + } + a++; + } + return 1; +} + +static int +tic4x_print_op (struct disassemble_info *info, + unsigned long instruction, + tic4x_inst_t *p, + unsigned long pc) +{ + int val; + char *s; + char *parallel = NULL; + + /* Print instruction name. */ + s = p->name; + while (*s && parallel == NULL) + { + switch (*s) + { + case 'B': + if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16))) + return 0; + break; + case 'C': + if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23))) + return 0; + break; + case '_': + parallel = s + 1; /* Skip past `_' in name. */ + break; + default: + tic4x_print_char (info, *s); + break; + } + s++; + } + + /* Print arguments. */ + s = p->args; + if (*s) + tic4x_print_char (info, ' '); + + while (*s) + { + switch (*s) + { + case '*': /* Indirect 0--15. */ + if (! tic4x_print_indirect (info, INDIRECT_LONG, + EXTRU (instruction, 15, 0))) + return 0; + break; + + case '#': /* Only used for ldp, ldpk. */ + tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); + break; + + case '@': /* Direct 0--15. */ + tic4x_print_direct (info, EXTRU (instruction, 15, 0)); + break; + + case 'A': /* Address register 24--22. */ + if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) + + REG_AR0)) + return 0; + break; + + case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb + address 0--23. */ + if (IS_CPU_TIC4X (tic4x_version)) + tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0), + p->opcode); + else + tic4x_print_addr (info, EXTRU (instruction, 23, 0)); + break; + + case 'C': /* Indirect (short C4x) 0--7. */ + if (! IS_CPU_TIC4X (tic4x_version)) + return 0; + if (! tic4x_print_indirect (info, INDIRECT_TIC4X, + EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'D': + /* Cockup if get here... */ + break; + + case 'E': /* Register 0--7. */ + case 'e': + if (! tic4x_print_register (info, EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'F': /* 16-bit float immediate 0--15. */ + tic4x_print_immed (info, IMMED_SFLOAT, + EXTRU (instruction, 15, 0)); + break; + + case 'i': /* Extended indirect 0--7. */ + if (EXTRU (instruction, 7, 5) == 7) + { + if (!tic4x_print_register (info, EXTRU (instruction, 4, 0))) + return 0; + break; + } + /* Fallthrough */ + + case 'I': /* Indirect (short) 0--7. */ + if (! tic4x_print_indirect (info, INDIRECT_SHORT, + EXTRU (instruction, 7, 0))) + return 0; + break; + + case 'j': /* Extended indirect 8--15 */ + if (EXTRU (instruction, 15, 13) == 7) + { + if (! tic4x_print_register (info, EXTRU (instruction, 12, 8))) + return 0; + break; + } + + case 'J': /* Indirect (short) 8--15. */ + if (! tic4x_print_indirect (info, INDIRECT_SHORT, + EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'G': /* Register 8--15. */ + case 'g': + if (! tic4x_print_register (info, EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'H': /* Register 16--18. */ + if (! tic4x_print_register (info, EXTRU (instruction, 18, 16))) + return 0; + break; + + case 'K': /* Register 19--21. */ + if (! tic4x_print_register (info, EXTRU (instruction, 21, 19))) + return 0; + break; + + case 'L': /* Register 22--24. */ + if (! tic4x_print_register (info, EXTRU (instruction, 24, 22))) + return 0; + break; + + case 'M': /* Register 22--22. */ + tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); + break; + + case 'N': /* Register 23--23. */ + tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0); + break; + + case 'O': /* Indirect (short C4x) 8--15. */ + if (! IS_CPU_TIC4X (tic4x_version)) + return 0; + if (! tic4x_print_indirect (info, INDIRECT_TIC4X, + EXTRU (instruction, 15, 8))) + return 0; + break; + + case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */ + tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0), + p->opcode); + break; + + case 'Q': /* Register 0--15. */ + case 'q': + if (! tic4x_print_register (info, EXTRU (instruction, 15, 0))) + return 0; + break; + + case 'R': /* Register 16--20. */ + case 'r': + if (! tic4x_print_register (info, EXTRU (instruction, 20, 16))) + return 0; + break; + + case 'S': /* 16-bit signed immediate 0--15. */ + tic4x_print_immed (info, IMMED_SINT, + EXTRS (instruction, 15, 0)); + break; + + case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */ + if (! IS_CPU_TIC4X (tic4x_version)) + return 0; + if (! tic4x_print_immed (info, IMMED_SUINT, + EXTRU (instruction, 20, 16))) + return 0; + break; + + case 'U': /* 16-bit unsigned int immediate 0--15. */ + tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); + break; + + case 'V': /* 5/9-bit unsigned vector 0--4/8. */ + tic4x_print_immed (info, IMMED_SUINT, + IS_CPU_TIC4X (tic4x_version) ? + EXTRU (instruction, 8, 0) : + EXTRU (instruction, 4, 0) & ~0x20); + break; + + case 'W': /* 8-bit signed immediate 0--7. */ + if (! IS_CPU_TIC4X (tic4x_version)) + return 0; + tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); + break; + + case 'X': /* Expansion register 4--0. */ + val = EXTRU (instruction, 4, 0) + REG_IVTP; + if (val < REG_IVTP || val > REG_TVTP) + return 0; + if (! tic4x_print_register (info, val)) + return 0; + break; + + case 'Y': /* Address register 16--20. */ + val = EXTRU (instruction, 20, 16); + if (val < REG_AR0 || val > REG_SP) + return 0; + if (! tic4x_print_register (info, val)) + return 0; + break; + + case 'Z': /* Expansion register 16--20. */ + val = EXTRU (instruction, 20, 16) + REG_IVTP; + if (val < REG_IVTP || val > REG_TVTP) + return 0; + if (! tic4x_print_register (info, val)) + return 0; + break; + + case '|': /* Parallel instruction. */ + tic4x_print_str (info, " || "); + tic4x_print_str (info, parallel); + tic4x_print_char (info, ' '); + break; + + case ';': + tic4x_print_char (info, ','); + break; + + default: + tic4x_print_char (info, *s); + break; + } + s++; + } + return 1; +} + +static void +tic4x_hash_opcode_special (tic4x_inst_t **optable_special, + const tic4x_inst_t *inst) +{ + int i; + + for (i = 0;i < TIC4X_SPESOP_SIZE; i++) + if (optable_special[i] != NULL + && optable_special[i]->opcode == inst->opcode) + { + /* Collision (we have it already) - overwrite. */ + optable_special[i] = (tic4x_inst_t *) inst; + return; + } + + for (i = 0; i < TIC4X_SPESOP_SIZE; i++) + if (optable_special[i] == NULL) + { + /* Add the new opcode. */ + optable_special[i] = (tic4x_inst_t *) inst; + return; + } + + /* This should never occur. This happens if the number of special + instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable + of this variable */ +#if TIC4X_DEBUG + printf ("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n"); +#endif +} + +static void +tic4x_hash_opcode (tic4x_inst_t **optable, + tic4x_inst_t **optable_special, + const tic4x_inst_t *inst, + const unsigned long tic4x_oplevel) +{ + int j; + int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE); + int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE); + + /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should + have unique entries so there's no point having a linked list + for each entry? */ + for (j = opcode; j < opmask; j++) + if ((j & opmask) == opcode + && inst->oplevel & tic4x_oplevel) + { +#if TIC4X_DEBUG + /* We should only have collisions for synonyms like + ldp for ldi. */ + if (optable[j] != NULL) + printf ("Collision at index %d, %s and %s\n", + j, optable[j]->name, inst->name); +#endif + /* Catch those ops that collide with others already inside the + hash, and have a opmask greater than the one we use in the + hash. Store them in a special-list, that will handle full + 32-bit INSN, not only the first 11-bit (or so). */ + if (optable[j] != NULL + && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE))) + { + /* Add the instruction already on the list. */ + tic4x_hash_opcode_special (optable_special, optable[j]); + + /* Add the new instruction. */ + tic4x_hash_opcode_special (optable_special, inst); + } + + optable[j] = (tic4x_inst_t *) inst; + } +} + +/* Disassemble the instruction in 'instruction'. + 'pc' should be the address of this instruction, it will + be used to print the target address if this is a relative jump or call + the disassembled instruction is written to 'info'. + The function returns the length of this instruction in words. */ + +static int +tic4x_disassemble (unsigned long pc, + unsigned long instruction, + struct disassemble_info *info) +{ + static tic4x_inst_t **optable = NULL; + static tic4x_inst_t **optable_special = NULL; + tic4x_inst_t *p; + int i; + unsigned long tic4x_oplevel; + + tic4x_version = info->mach; + + tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0; + tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH; + + if (optable == NULL) + { + optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE)); + + optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE); + + /* Install opcodes in reverse order so that preferred + forms overwrite synonyms. */ + for (i = tic4x_num_insts - 1; i >= 0; i--) + tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], + tic4x_oplevel); + + /* We now need to remove the insn that are special from the + "normal" optable, to make the disasm search this extra list + for them. */ + for (i = 0; i < TIC4X_SPESOP_SIZE; i++) + if (optable_special[i] != NULL) + optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL; + } + + /* See if we can pick up any loading of the DP register... */ + if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) + tic4x_dp = EXTRU (instruction, 15, 0); + + p = optable[instruction >> (32 - TIC4X_HASH_SIZE)]; + if (p != NULL) + { + if (((instruction & p->opmask) == p->opcode) + && tic4x_print_op (NULL, instruction, p, pc)) + tic4x_print_op (info, instruction, p, pc); + else + (*info->fprintf_func) (info->stream, "%08lx", instruction); + } + else + { + for (i = 0; iopcode == instruction) + { + (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name); + break; + } + if (i == TIC4X_SPESOP_SIZE) + (*info->fprintf_func) (info->stream, "%08lx", instruction); + } + + /* Return size of insn in words. */ + return 1; +} + +/* The entry point from objdump and gdb. */ +int +print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + unsigned long pc; + unsigned long op; + bfd_byte buffer[4]; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + pc = memaddr; + op = bfd_getl32 (buffer); + info->bytes_per_line = 4; + info->bytes_per_chunk = 4; + info->octets_per_byte = 4; + info->display_endian = BFD_ENDIAN_LITTLE; + return tic4x_disassemble (pc, op, info) * 4; +} diff --git a/external/gpl3/gdb/dist/opcodes/tic54x-dis.c b/external/gpl3/gdb/dist/opcodes/tic54x-dis.c new file mode 100644 index 000000000000..578af10f7e26 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic54x-dis.c @@ -0,0 +1,603 @@ +/* Disassembly routines for TMS320C54X architecture + Copyright 1999, 2000, 2001, 2005, 2007, 2009 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic54x.h" +#include "coff/tic54x.h" + +static int has_lkaddr (unsigned short, const insn_template *); +static int get_insn_size (unsigned short, const insn_template *); +static int print_instruction (disassemble_info *, bfd_vma, + unsigned short, const char *, + const enum optype [], int, int); +static int print_parallel_instruction (disassemble_info *, bfd_vma, + unsigned short, + const insn_template *, int); +static int sprint_dual_address (disassemble_info *,char [], + unsigned short); +static int sprint_indirect_address (disassemble_info *,char [], + unsigned short); +static int sprint_direct_address (disassemble_info *,char [], + unsigned short); +static int sprint_mmr (disassemble_info *,char [],int); +static int sprint_condition (disassemble_info *,char *,unsigned short); +static int sprint_cc2 (disassemble_info *,char *,unsigned short); + +int +print_insn_tic54x (bfd_vma memaddr, disassemble_info *info) +{ + bfd_byte opbuf[2]; + unsigned short opcode; + int status, size; + const insn_template* tm; + + status = (*info->read_memory_func) (memaddr, opbuf, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + opcode = bfd_getl16 (opbuf); + tm = tic54x_get_insn (info, memaddr, opcode, &size); + + info->bytes_per_line = 2; + info->bytes_per_chunk = 2; + info->octets_per_byte = 2; + info->display_endian = BFD_ENDIAN_LITTLE; + + if (tm->flags & FL_PAR) + { + if (!print_parallel_instruction (info, memaddr, opcode, tm, size)) + return -1; + } + else + { + if (!print_instruction (info, memaddr, opcode, + (char *) tm->name, + tm->operand_types, + size, (tm->flags & FL_EXT))) + return -1; + } + + return size * 2; +} + +static int +has_lkaddr (unsigned short memdata, const insn_template *tm) +{ + return (IS_LKADDR (memdata) + && (OPTYPE (tm->operand_types[0]) == OP_Smem + || OPTYPE (tm->operand_types[1]) == OP_Smem + || OPTYPE (tm->operand_types[2]) == OP_Smem + || OPTYPE (tm->operand_types[1]) == OP_Sind + || OPTYPE (tm->operand_types[0]) == OP_Lmem + || OPTYPE (tm->operand_types[1]) == OP_Lmem)); +} + +/* always returns 1 (whether an insn template was found) since we provide an + "unknown instruction" template */ +const insn_template* +tic54x_get_insn (disassemble_info *info, bfd_vma addr, + unsigned short memdata, int *size) +{ + const insn_template *tm = NULL; + + for (tm = tic54x_optab; tm->name; tm++) + { + if (tm->opcode == (memdata & tm->mask)) + { + /* a few opcodes span two words */ + if (tm->flags & FL_EXT) + { + /* if lk addressing is used, the second half of the opcode gets + pushed one word later */ + bfd_byte opbuf[2]; + bfd_vma addr2 = addr + 1 + has_lkaddr (memdata, tm); + int status = (*info->read_memory_func) (addr2, opbuf, 2, info); + // FIXME handle errors + if (status == 0) + { + unsigned short data2 = bfd_getl16 (opbuf); + if (tm->opcode2 == (data2 & tm->mask2)) + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + } + else + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + } + for (tm = (insn_template *) tic54x_paroptab; tm->name; tm++) + { + if (tm->opcode == (memdata & tm->mask)) + { + if (size) *size = get_insn_size (memdata, tm); + return tm; + } + } + + if (size) *size = 1; + return &tic54x_unknown_opcode; +} + +static int +get_insn_size (unsigned short memdata, const insn_template *insn) +{ + int size; + + if (insn->flags & FL_PAR) + { + /* only non-parallel instructions support lk addressing */ + size = insn->words; + } + else + { + size = insn->words + has_lkaddr (memdata, insn); + } + + return size; +} + +int +print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + const char *tm_name; + const enum optype tm_operands[]; + int size; + int ext; +{ + static int n; + /* string storage for multiple operands */ + char operand[4][64] = { {0},{0},{0},{0}, }; + bfd_byte buf[2]; + unsigned long opcode2 = 0; + unsigned long lkaddr = 0; + enum optype src = OP_None; + enum optype dst = OP_None; + int i, shift; + char *comma = ""; + + info->fprintf_func (info->stream, "%-7s", tm_name); + + if (size > 1) + { + int status = (*info->read_memory_func) (memaddr + 1, buf, 2, info); + if (status != 0) + return 0; + lkaddr = opcode2 = bfd_getl16 (buf); + if (size > 2) + { + status = (*info->read_memory_func) (memaddr + 2, buf, 2, info); + if (status != 0) + return 0; + opcode2 = bfd_getl16 (buf); + } + } + + for (i = 0; i < MAX_OPERANDS && OPTYPE (tm_operands[i]) != OP_None; i++) + { + char *next_comma = ","; + int optional = (tm_operands[i] & OPT) != 0; + + switch (OPTYPE (tm_operands[i])) + { + case OP_Xmem: + sprint_dual_address (info, operand[i], XMEM (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Ymem: + sprint_dual_address (info, operand[i], YMEM (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_Smem: + case OP_Sind: + case OP_Lmem: + info->fprintf_func (info->stream, "%s", comma); + if (INDIRECT (opcode)) + { + if (MOD (opcode) >= 12) + { + bfd_vma addr = lkaddr; + int arf = ARF (opcode); + int mod = MOD (opcode); + if (mod == 15) + info->fprintf_func (info->stream, "*("); + else + info->fprintf_func (info->stream, "*%sar%d(", + (mod == 13 || mod == 14 ? "+" : ""), + arf); + (*(info->print_address_func)) ((bfd_vma) addr, info); + info->fprintf_func (info->stream, ")%s", + mod == 14 ? "%" : ""); + } + else + { + sprint_indirect_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + } + else + { + /* FIXME -- use labels (print_address_func) */ + /* in order to do this, we need to guess what DP is */ + sprint_direct_address (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s", operand[i]); + } + break; + case OP_dmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func)) ((bfd_vma) opcode2, info); + break; + case OP_xpmad: + /* upper 7 bits of address are in the opcode */ + opcode2 += ((unsigned long) opcode & 0x7F) << 16; + /* fall through */ + case OP_pmad: + info->fprintf_func (info->stream, "%s", comma); + (*(info->print_address_func)) ((bfd_vma) opcode2, info); + break; + case OP_MMRX: + sprint_mmr (info, operand[i], MMRX (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMRY: + sprint_mmr (info, operand[i], MMRY (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_MMR: + sprint_mmr (info, operand[i], MMR (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_PA: + sprintf (operand[i], "pa%d", (unsigned) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC: + src = SRC (ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SRC1: + src = SRC1 (ext ? opcode2 : opcode) ? OP_B : OP_A; + sprintf (operand[i], (src == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_RND: + dst = DST (opcode) ? OP_B : OP_A; + sprintf (operand[i], (dst == OP_B) ? "a" : "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DST: + dst = DST (ext ? opcode2 : opcode) ? OP_B : OP_A; + if (!optional || dst != src) + { + sprintf (operand[i], (dst == OP_B) ? "b" : "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_B: + sprintf (operand[i], "b"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_A: + sprintf (operand[i], "a"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARX: + sprintf (operand[i], "ar%d", (int) ARX (opcode)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SHIFT: + shift = SHIFT (ext ? opcode2 : opcode); + if (!optional || shift != 0) + { + sprintf (operand[i], "%d", shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_SHFT: + shift = SHFT (opcode); + if (!optional || shift != 0) + { + sprintf (operand[i], "%d", (unsigned) shift); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + } + else + next_comma = comma; + break; + case OP_lk: + sprintf (operand[i], "#%d", (int) (short) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_T: + sprintf (operand[i], "t"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TS: + sprintf (operand[i], "ts"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8: + sprintf (operand[i], "%d", (int) ((signed char) (opcode & 0xFF))); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_16: + sprintf (operand[i], "16"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ASM: + sprintf (operand[i], "asm"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_BITC: + sprintf (operand[i], "%d", (int) (opcode & 0xF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC: + /* put all CC operands in the same operand */ + sprint_condition (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + i = MAX_OPERANDS; + break; + case OP_CC2: + sprint_cc2 (info, operand[i], opcode); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_CC3: + { + const char *code[] = { "eq", "lt", "gt", "neq" }; + + /* Do not use sprintf with only two parameters as a + compiler warning could be generated in such conditions. */ + sprintf (operand[i], "%s", code[CC3 (opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_123: + { + int code = (opcode >> 8) & 0x3; + sprintf (operand[i], "%d", (code == 0) ? 1 : (code == 2) ? 2 : 3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_k5: + sprintf (operand[i], "#%d", + (int) (((signed char) opcode & 0x1F) << 3) >> 3); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k8u: + sprintf (operand[i], "#%d", (unsigned) (opcode & 0xFF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k3: + sprintf (operand[i], "#%d", (int) (opcode & 0x7)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_lku: + sprintf (operand[i], "#%d", (unsigned) opcode2); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_N: + n = (opcode >> 9) & 0x1; + sprintf (operand[i], "st%d", n); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_SBIT: + { + const char *status0[] = { + "0", "1", "2", "3", "4", "5", "6", "7", "8", + "ovb", "ova", "c", "tc", "13", "14", "15" + }; + const char *status1[] = { + "0", "1", "2", "3", "4", + "cmpt", "frct", "c16", "sxm", "ovm", "10", + "intm", "hm", "xf", "cpl", "braf" + }; + sprintf (operand[i], "%s", + n ? status1[SBIT (opcode)] : status0[SBIT (opcode)]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + case OP_12: + sprintf (operand[i], "%d", (int) ((opcode >> 9) & 1) + 1); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_TRN: + sprintf (operand[i], "trn"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_DP: + sprintf (operand[i], "dp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_k9: + /* FIXME-- this is DP, print the original address? */ + sprintf (operand[i], "#%d", (int) (opcode & 0x1FF)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_ARP: + sprintf (operand[i], "arp"); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + case OP_031: + sprintf (operand[i], "%d", (int) (opcode & 0x1F)); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + default: + sprintf (operand[i], "??? (0x%x)", tm_operands[i]); + info->fprintf_func (info->stream, "%s%s", comma, operand[i]); + break; + } + comma = next_comma; + } + return 1; +} + +static int +print_parallel_instruction (info, memaddr, opcode, ptm, size) + disassemble_info *info; + bfd_vma memaddr; + unsigned short opcode; + const insn_template *ptm; + int size; +{ + print_instruction (info, memaddr, opcode, + ptm->name, ptm->operand_types, size, 0); + info->fprintf_func (info->stream, " || "); + return print_instruction (info, memaddr, opcode, + ptm->parname, ptm->paroperand_types, size, 0); +} + +static int +sprint_dual_address (info, buf, code) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short code; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*ar%d+0%%", + }; + return sprintf (buf, formats[XMOD (code)], XARX (code)); +} + +static int +sprint_indirect_address (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short opcode; +{ + const char *formats[] = { + "*ar%d", + "*ar%d-", + "*ar%d+", + "*+ar%d", + "*ar%d-0B", + "*ar%d-0", + "*ar%d+0", + "*ar%d+0B", + "*ar%d-%%", + "*ar%d-0%%", + "*ar%d+%%", + "*ar%d+0%%", + }; + return sprintf (buf, formats[MOD (opcode)], ARF (opcode)); +} + +static int +sprint_direct_address (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + unsigned short opcode; +{ + /* FIXME -- look up relocation if available */ + return sprintf (buf, "DP+0x%02x", (int) (opcode & 0x7F)); +} + +static int +sprint_mmr (info, buf, mmr) + disassemble_info *info ATTRIBUTE_UNUSED; + char buf[]; + int mmr; +{ + symbol *reg = (symbol *) mmregs; + while (reg->name != NULL) + { + if (mmr == reg->value) + { + sprintf (buf, "%s", (reg + 1)->name); + return 1; + } + ++reg; + } + sprintf (buf, "MMR(%d)", mmr); /* FIXME -- different targets. */ + return 0; +} + +static int +sprint_cc2 (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char *buf; + unsigned short opcode; +{ + const char *cc2[] = { + "??", "??", "ageq", "alt", "aneq", "aeq", "agt", "aleq", + "??", "??", "bgeq", "blt", "bneq", "beq", "bgt", "bleq", + }; + return sprintf (buf, "%s", cc2[opcode & 0xF]); +} + +static int +sprint_condition (info, buf, opcode) + disassemble_info *info ATTRIBUTE_UNUSED; + char *buf; + unsigned short opcode; +{ + char *start = buf; + const char *cmp[] = { + "??", "??", "geq", "lt", "neq", "eq", "gt", "leq" + }; + if (opcode & 0x40) + { + char acc = (opcode & 0x8) ? 'b' : 'a'; + if (opcode & 0x7) + buf += sprintf (buf, "%c%s%s", acc, cmp[(opcode & 0x7)], + (opcode & 0x20) ? ", " : ""); + if (opcode & 0x20) + buf += sprintf (buf, "%c%s", acc, (opcode & 0x10) ? "ov" : "nov"); + } + else if (opcode & 0x3F) + { + if (opcode & 0x30) + buf += sprintf (buf, "%s%s", + ((opcode & 0x30) == 0x30) ? "tc" : "ntc", + (opcode & 0x0F) ? ", " : ""); + if (opcode & 0x0C) + buf += sprintf (buf, "%s%s", + ((opcode & 0x0C) == 0x0C) ? "c" : "nc", + (opcode & 0x03) ? ", " : ""); + if (opcode & 0x03) + buf += sprintf (buf, "%s", + ((opcode & 0x03) == 0x03) ? "bio" : "nbio"); + } + else + buf += sprintf (buf, "unc"); + + return buf - start; +} diff --git a/external/gpl3/gdb/dist/opcodes/tic54x-opc.c b/external/gpl3/gdb/dist/opcodes/tic54x-opc.c new file mode 100644 index 000000000000..78c55fe58475 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic54x-opc.c @@ -0,0 +1,496 @@ +/* Table of opcodes for the Texas Instruments TMS320C54X + Copyright 1999, 2000, 2001, 2005, 2007, 2009 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic54x.h" + +/* these are the only register names not found in mmregs */ +const symbol regs[] = { + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { NULL, 0} +}; + +/* status bits, MM registers, condition codes, etc */ +/* some symbols are only valid for certain chips... */ +const symbol mmregs[] = { + { "IMR", 0 }, { "imr", 0 }, + { "IFR", 1 }, { "ifr", 1 }, + { "ST0", 6 }, { "st0", 6 }, + { "ST1", 7 }, { "st1", 7 }, + { "AL", 8 }, { "al", 8 }, + { "AH", 9 }, { "ah", 9 }, + { "AG", 10 }, { "ag", 10 }, + { "BL", 11 }, { "bl", 11 }, + { "BH", 12 }, { "bh", 12 }, + { "BG", 13 }, { "bg", 13 }, + { "T", 14 }, { "t", 14 }, + { "TRN", 15 }, { "trn", 15 }, + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { "SP", 24 }, { "sp", 24 }, + { "BK", 25 }, { "bk", 25 }, + { "BRC", 26 }, { "brc", 26 }, + { "RSA", 27 }, { "rsa", 27 }, + { "REA", 28 }, { "rea", 28 }, + { "PMST",29 }, { "pmst",29 }, + { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ + /* optional peripherals */ /* optional peripherals */ + { "M1F", 31 }, { "m1f", 31 }, + { "DRR0",0x20 }, { "drr0",0x20 }, + { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ + { "DXR0",0x21 }, { "dxr0",0x21 }, + { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ + { "SPC0",0x22 }, { "spc0",0x22 }, + { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ + { "SPCE0",0x23 }, { "spce0",0x23 }, + { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ + { "TIM", 0x24 }, { "tim", 0x24 }, + { "PRD", 0x25 }, { "prd", 0x25 }, + { "TCR", 0x26 }, { "tcr", 0x26 }, + { "SWWSR",0x28 }, { "swwsr",0x28 }, + { "BSCR",0x29 }, { "bscr",0x29 }, + { "HPIC",0x2C }, { "hpic",0x2c }, + /* 'c541, 'c545 */ /* 'c541, 'c545 */ + { "DRR1",0x30 }, { "drr1",0x30 }, + { "DXR1",0x31 }, { "dxr1",0x31 }, + { "SPC1",0x32 }, { "spc1",0x32 }, + /* 'c542, 'c543 */ /* 'c542, 'c543 */ + { "TRCV",0x30 }, { "trcv",0x30 }, + { "TDXR",0x31 }, { "tdxr",0x31 }, + { "TSPC",0x32 }, { "tspc",0x32 }, + { "TCSR",0x33 }, { "tcsr",0x33 }, + { "TRTA",0x34 }, { "trta",0x34 }, + { "TRAD",0x35 }, { "trad",0x35 }, + { "AXR0",0x38 }, { "axr0",0x38 }, + { "BKX0",0x39 }, { "bkx0",0x39 }, + { "ARR0",0x3A }, { "arr0",0x3a }, + { "BKR0",0x3B }, { "bkr0",0x3b }, + /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ + { "CLKMD",0x58 }, { "clkmd",0x58 }, + /* 'c548 */ /* 'c548 */ + { "AXR1",0x3C }, { "axr1",0x3c }, + { "BKX1",0x3D }, { "bkx1",0x3d }, + { "ARR1",0x3E }, { "arr1",0x3e }, + { "BKR1",0x3F }, { "bkr1",0x3f }, + { "BDRR1",0x40 }, { "bdrr1",0x40 }, + { "BDXR1",0x41 }, { "bdxr1",0x41 }, + { "BSPC1",0x42 }, { "bspc1",0x42 }, + { "BSPCE1",0x43 }, { "bspce1",0x43 }, + { NULL, 0}, +}; + +const symbol condition_codes[] = { + /* condition codes */ + { "UNC", 0 }, { "unc", 0 }, +#define CC1 0x40 +#define CCB 0x08 +#define CCEQ 0x05 +#define CCNEQ 0x04 +#define CCLT 0x03 +#define CCLEQ 0x07 +#define CCGT 0x06 +#define CCGEQ 0x02 +#define CCOV 0x70 +#define CCNOV 0x60 +#define CCBIO 0x03 +#define CCNBIO 0x02 +#define CCTC 0x30 +#define CCNTC 0x20 +#define CCC 0x0C +#define CCNC 0x08 + { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ }, + { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ }, + { "alt", CC1|CCLT }, { "ALT", CC1|CCLT }, + { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ }, + { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, + { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, + { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, + { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, + { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, + { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, + { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, + { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, + { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, + { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, + { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, + { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, + { "tc", CCTC }, { "TC", CCTC }, + { "ntc", CCNTC }, { "NTC", CCNTC }, + { "c", CCC }, { "C", CCC }, + { "nc", CCNC }, { "NC", CCNC }, + { "bio", CCBIO }, { "BIO", CCBIO }, + { "nbio", CCNBIO }, { "NBIO", CCNBIO }, + { NULL, 0 } +}; + +const symbol cc2_codes[] = { + { "UNC", 0 }, { "unc", 0 }, + { "AEQ", 5 }, { "aeq", 5 }, + { "ANEQ", 4 }, { "aneq", 4 }, + { "AGT", 6 }, { "agt", 6 }, + { "ALT", 3 }, { "alt", 3 }, + { "ALEQ", 7 }, { "aleq", 7 }, + { "AGEQ", 2 }, { "ageq", 2 }, + { "BEQ", 13 }, { "beq", 13 }, + { "BNEQ", 12 },{ "bneq", 12 }, + { "BGT", 14 }, { "bgt", 14 }, + { "BLT", 11 }, { "blt", 11 }, + { "BLEQ", 15 },{ "bleq", 15 }, + { "BGEQ", 10 },{ "bgeq", 10 }, + { NULL, 0 }, +}; + +const symbol cc3_codes[] = { + { "EQ", 0x0000 }, { "eq", 0x0000 }, + { "LT", 0x0100 }, { "lt", 0x0100 }, + { "GT", 0x0200 }, { "gt", 0x0200 }, + { "NEQ", 0x0300 }, { "neq", 0x0300 }, + { "0", 0x0000 }, + { "1", 0x0100 }, + { "2", 0x0200 }, + { "3", 0x0300 }, + { "00", 0x0000 }, + { "01", 0x0100 }, + { "10", 0x0200 }, + { "11", 0x0300 }, + { NULL, 0 }, +}; + +/* FIXME -- also allow decimal digits */ +const symbol status_bits[] = { + /* status register 0 */ + { "TC", 12 }, { "tc", 12 }, + { "C", 11 }, { "c", 11 }, + { "OVA", 10 }, { "ova", 10 }, + { "OVB", 9 }, { "ovb", 9 }, + /* status register 1 */ + { "BRAF",15 }, { "braf",15 }, + { "CPL", 14 }, { "cpl", 14 }, + { "XF", 13 }, { "xf", 13 }, + { "HM", 12 }, { "hm", 12 }, + { "INTM",11 }, { "intm",11 }, + { "OVM", 9 }, { "ovm", 9 }, + { "SXM", 8 }, { "sxm", 8 }, + { "C16", 7 }, { "c16", 7 }, + { "FRCT", 6 }, { "frct", 6 }, + { "CMPT", 5 }, { "cmpt", 5 }, + { NULL, 0 }, +}; + +const char *misc_symbols[] = { + "ARP", "arp", + "DP", "dp", + "ASM", "asm", + "TS", "ts", + NULL +}; + +/* Due to the way instructions are hashed and scanned in + gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively + placed + + Items marked with "PREFER" have been moved prior to a more costly + instruction with a similar operand format. + + Mnemonics which can take either a predefined symbol or a memory reference + as an argument are arranged so that the more restrictive (predefined + symbol) version is checked first (marked "SRC"). +*/ +#define ZPAR 0,{OP_None} +#define REST 0,0,ZPAR +#define XREST ZPAR +const insn_template tic54x_unknown_opcode = + { "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST}; +const insn_template tic54x_optab[] = { + /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */ + { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST}, + { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST}, + { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST}, + { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST}, + + { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST}, + { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/ + { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST}, + { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST}, + { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST }, + { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST}, + { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST}, + { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST}, + { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST}, + { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST}, + { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, REST}, + { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, REST}, + { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST}, + { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST}, + { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST}, + { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST}, + { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST}, + { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST}, + { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, REST}, + { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_DELAY|FL_NR, REST}, + { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST}, + { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST}, + { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST}, + { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST}, + { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST}, + { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST}, + { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */ + { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST}, + { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST}, + { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST}, + { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST}, + { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST}, + { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST}, + { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST}, + { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST}, + { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST}, + { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST}, + { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST}, + { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST}, + { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST}, + { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/ + /* alternate syntax */ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/ + { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/ + { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */ + { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/ + { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST}, + { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/ + { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, + FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST}, + { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST}, + { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST}, + { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST}, + { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/ + { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST}, + { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST}, + { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/ + { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/ + { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST}, + { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST}, + { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST}, + { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST}, + { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST}, + { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/ + { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST}, + { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST}, + { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST}, + { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST}, + { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST}, + { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST}, + { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/ + { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST}, + { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST}, + { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST}, + { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST}, + { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST}, + { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST}, + { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST}, + { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST}, + { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST}, + { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST}, + { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST}, + { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST}, + { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST}, + { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST}, + { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST}, + { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_NR, REST}, + { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_DELAY|FL_NR, REST}, + { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST}, + { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST}, + { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST}, + { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST}, + { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST}, + { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST}, + { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST}, + { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST}, + { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST}, + { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST}, + { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST}, + { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST}, + { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST}, + { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST}, + { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST}, + { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST}, + { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST}, + { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST}, + { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST}, + { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST}, + { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/ + { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST}, + { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST}, + { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST}, + { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST}, + { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST}, + { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST}, + { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST}, + { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST}, + { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C60, 0xFEE0, XREST}, + { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST}, + { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST}, + { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST}, + { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + FL_EXT, 0x0C80, 0xFEE0, XREST }, + { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST}, + { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST}, + { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST}, + { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/ + { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST}, + { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST}, + { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/ + { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST}, + { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST}, + { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST}, + { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST}, + { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST}, + { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/ + { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST}, + { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST}, + { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST}, + { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST}, + { NULL, 0,0,0,0,0, {}, 0, REST}, +}; + +/* assume all parallel instructions have at least three operands */ +const insn_template tic54x_paroptab[] = { + { "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "mac", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "macr", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "mas", {OP_Ymem,OPT|OP_RND},}, + { "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0, + "masr", {OP_Ymem,OPT|OP_RND},}, + { "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "add", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "ld", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "ld", {OP_Xmem,OP_T}, }, + { "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mac", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "macr", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mas", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "masr", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "mpy", {OP_Xmem,OP_DST}, }, + { "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0, + "sub", {OP_Xmem,OP_DST}, }, + { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST }, +}; diff --git a/external/gpl3/gdb/dist/opcodes/tic6x-dis.c b/external/gpl3/gdb/dist/opcodes/tic6x-dis.c new file mode 100644 index 000000000000..05626df2275f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic6x-dis.c @@ -0,0 +1,1114 @@ +/* TI C6X disassembler. + Copyright 2010 + Free Software Foundation, Inc. + Contributed by Joseph Myers + Bernd Schmidt + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/tic6x.h" +#include "libiberty.h" + +/* Define the instruction format table. */ +const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max] = + { +#define FMT(name, num_bits, cst_bits, mask, fields) \ + { num_bits, cst_bits, mask, fields }, +#include "opcode/tic6x-insn-formats.h" +#undef FMT + }; + +/* Define the control register table. */ +const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max] = + { +#define CTRL(name, isa, rw, crlo, crhi_mask) \ + { \ + STRINGX(name), \ + CONCAT2(TIC6X_INSN_,isa), \ + CONCAT2(tic6x_rw_,rw), \ + crlo, \ + crhi_mask \ + }, +#include "opcode/tic6x-control-registers.h" +#undef CTRL + }; + +/* Define the opcode table. */ +const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max] = + { +#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \ + { \ + STRINGX(name), \ + CONCAT2(tic6x_func_unit_,func_unit), \ + CONCAT4(tic6x_insn_format_,func_unit,_,format), \ + CONCAT2(tic6x_pipeline_,type), \ + CONCAT2(TIC6X_INSN_,isa), \ + flags, \ + fixed, \ + ops, \ + var \ + }, +#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ + { \ + STRINGX(name), \ + CONCAT2(tic6x_func_unit_,func_unit), \ + CONCAT4(tic6x_insn_format_,func_unit,_,format), \ + CONCAT2(tic6x_pipeline_,type), \ + CONCAT2(TIC6X_INSN_,isa), \ + flags, \ + fixed, \ + ops, \ + var \ + }, +#include "opcode/tic6x-opcode-table.h" +#undef INSN +#undef INSNE + }; + +/* If instruction format FMT has a field FIELD, return a pointer to + the description of that field; otherwise return NULL. */ + +const tic6x_insn_field * +tic6x_field_from_fmt (const tic6x_insn_format *fmt, tic6x_insn_field_id field) +{ + unsigned int f; + + for (f = 0; f < fmt->num_fields; f++) + if (fmt->fields[f].field_id == field) + return &fmt->fields[f]; + + return NULL; +} + +/* Extract the bits corresponding to FIELD from OPCODE. */ + +static unsigned int +tic6x_field_bits (unsigned int opcode, const tic6x_insn_field *field) +{ + return (opcode >> field->low_pos) & ((1u << field->width) - 1); +} + +/* Extract a 32-bit value read from the instruction stream. */ + +static unsigned int +tic6x_extract_32 (unsigned char *p, struct disassemble_info *info) +{ + if (info->endian == BFD_ENDIAN_LITTLE) + return (p[0]) | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); + else + return (p[3]) | (p[2] << 8) | (p[1] << 16) | (p[0] << 24); +} + +/* Extract a 16-bit value read from the instruction stream. */ + +static unsigned int +tic6x_extract_16 (unsigned char *p, struct disassemble_info *info) +{ + if (info->endian == BFD_ENDIAN_LITTLE) + return (p[0]) | (p[1] << 8); + else + return (p[1]) | (p[0] << 8); +} + +/* FP points to a fetch packet. Return whether it is header-based; if + it is, fill in HEADER. */ + +static bfd_boolean +tic6x_check_fetch_packet_header (unsigned char *fp, + tic6x_fetch_packet_header *header, + struct disassemble_info *info) +{ + int i; + + header->header = tic6x_extract_32 (fp + 28, info); + if ((header->header & 0xf0000000) != 0xe0000000) + return FALSE; + + for (i = 0; i < 7; i++) + header->word_compact[i] + = (header->header & (1u << (21 + i))) ? TRUE : FALSE; + + header->prot = (header->header & (1u << 20)) ? TRUE : FALSE; + header->rs = (header->header & (1u << 19)) ? TRUE : FALSE; + header->dsz = (header->header >> 16) & 0x7; + header->br = (header->header & (1u << 15)) ? TRUE : FALSE; + header->sat = (header->header & (1u << 14)) ? TRUE : FALSE; + + for (i = 0; i < 14; i++) + header->p_bits[i] + = (header->header & (1u << i)) ? TRUE : FALSE; + + return TRUE; +} + +/* Disassemble the instruction at ADDR and print it using + INFO->FPRINTF_FUNC and INFO->STREAM, returning the number of bytes + consumed. */ + +int +print_insn_tic6x (bfd_vma addr, struct disassemble_info *info) +{ + int status; + bfd_vma fp_addr; + bfd_vma fp_offset; + unsigned char fp[32]; + unsigned int opcode; + tic6x_opcode_id opcode_id; + bfd_boolean fetch_packet_header_based; + tic6x_fetch_packet_header header; + unsigned int num_bits; + bfd_boolean bad_offset = FALSE; + + fp_offset = addr & 0x1f; + fp_addr = addr - fp_offset; + status = info->read_memory_func (fp_addr, fp, 32, info); + if (status) + { + info->memory_error_func (status, addr, info); + return -1; + } + + fetch_packet_header_based + = tic6x_check_fetch_packet_header (fp, &header, info); + if (fetch_packet_header_based) + { + if (fp_offset & 0x1) + bad_offset = TRUE; + if ((fp_offset & 0x3) && (fp_offset >= 28 + || !header.word_compact[fp_offset >> 2])) + bad_offset = TRUE; + if (fp_offset == 28) + { + info->bytes_per_chunk = 4; + info->fprintf_func (info->stream, "", + header.header); + return 4; + } + num_bits = (header.word_compact[fp_offset >> 2] ? 16 : 32); + } + else + { + num_bits = 32; + if (fp_offset & 0x3) + bad_offset = TRUE; + } + + if (bad_offset) + { + info->bytes_per_chunk = 1; + info->fprintf_func (info->stream, ".byte 0x%.2x", fp[fp_offset]); + return 1; + } + + if (num_bits == 16) + { + /* The least-significant part of a 32-bit word comes logically + before the most-significant part. For big-endian, follow the + TI assembler in showing instructions in logical order by + pretending that the two halves of the word are in opposite + locations to where they actually are. */ + if (info->endian == BFD_ENDIAN_LITTLE) + opcode = tic6x_extract_16 (fp + fp_offset, info); + else + opcode = tic6x_extract_16 (fp + (fp_offset ^ 2), info); + } + else + opcode = tic6x_extract_32 (fp + fp_offset, info); + + for (opcode_id = 0; opcode_id < tic6x_opcode_max; opcode_id++) + { + const tic6x_opcode *const opc = &tic6x_opcode_table[opcode_id]; + const tic6x_insn_format *const fmt + = &tic6x_insn_format_table[opc->format]; + const tic6x_insn_field *creg_field; + bfd_boolean p_bit; + const char *parallel; + const char *cond = ""; + const char *func_unit; + char func_unit_buf[7]; + unsigned int func_unit_side = 0; + unsigned int func_unit_data_side = 0; + unsigned int func_unit_cross = 0; + /* The maximum length of the text of a non-PC-relative operand + is 24 bytes (SPMASK masking all eight functional units, with + separating commas and trailing NUL). */ + char operands[TIC6X_MAX_OPERANDS][24] = { { 0 } }; + bfd_vma operands_addresses[TIC6X_MAX_OPERANDS] = { 0 }; + bfd_boolean operands_text[TIC6X_MAX_OPERANDS] = { FALSE }; + bfd_boolean operands_pcrel[TIC6X_MAX_OPERANDS] = { FALSE }; + unsigned int fix; + unsigned int num_operands; + unsigned int op_num; + bfd_boolean fixed_ok; + bfd_boolean operands_ok; + + if (opc->flags & TIC6X_FLAG_MACRO) + continue; + if (fmt->num_bits != num_bits) + continue; + if ((opcode & fmt->mask) != fmt->cst_bits) + continue; + + /* If the format has a creg field, it is only a candidate for a + match if the creg and z fields have values indicating a valid + condition; reserved values indicate either an instruction + format without a creg field, or an invalid instruction. */ + creg_field = tic6x_field_from_fmt (fmt, tic6x_field_creg); + if (creg_field) + { + const tic6x_insn_field *z_field; + unsigned int creg_value, z_value; + static const char *const conds[8][2] = + { + { "", NULL }, + { "[b0] ", "[!b0] " }, + { "[b1] ", "[!b1] " }, + { "[b2] ", "[!b2] " }, + { "[a1] ", "[!a1] " }, + { "[a2] ", "[!a2] " }, + { "[a0] ", "[!a0] " }, + { NULL, NULL } + }; + + /* A creg field is not meaningful without a z field, so if + the z field is not present this is an error in the format + table. */ + z_field = tic6x_field_from_fmt (fmt, tic6x_field_z); + if (!z_field) + abort (); + + creg_value = tic6x_field_bits (opcode, creg_field); + z_value = tic6x_field_bits (opcode, z_field); + cond = conds[creg_value][z_value]; + if (cond == NULL) + continue; + } + + /* All fixed fields must have matching values; all fields with + restricted ranges must have values within those ranges. */ + fixed_ok = TRUE; + for (fix = 0; fix < opc->num_fixed_fields; fix++) + { + unsigned int field_bits; + const tic6x_insn_field *const field + = tic6x_field_from_fmt (fmt, opc->fixed_fields[fix].field_id); + + if (!field) + abort (); + field_bits = tic6x_field_bits (opcode, field); + if (field_bits < opc->fixed_fields[fix].min_val + || field_bits > opc->fixed_fields[fix].max_val) + { + fixed_ok = FALSE; + break; + } + } + if (!fixed_ok) + continue; + + /* The instruction matches. */ + + /* The p-bit indicates whether this instruction is in parallel + with the *next* instruction, whereas the parallel bars + indicate the instruction is in parallel with the *previous* + instruction. Thus, we must find the p-bit for the previous + instruction. */ + if (num_bits == 16 && (fp_offset & 0x2) == 2) + { + /* This is the logically second (most significant; second in + fp_offset terms because fp_offset relates to logical not + physical addresses) instruction of a compact pair; find + the p-bit for the first (least significant). */ + p_bit = header.p_bits[(fp_offset >> 2) << 1]; + } + else if (fp_offset >= 4) + { + /* Find the last instruction of the previous word in this + fetch packet. For compact instructions, this is the most + significant 16 bits. */ + if (fetch_packet_header_based + && header.word_compact[(fp_offset >> 2) - 1]) + p_bit = header.p_bits[(fp_offset >> 1) - 1]; + else + { + unsigned int prev_opcode + = tic6x_extract_32 (fp + (fp_offset & 0x1c) - 4, info); + p_bit = (prev_opcode & 0x1) ? TRUE : FALSE; + } + } + else + { + /* Find the last instruction of the previous fetch + packet. */ + unsigned char fp_prev[32]; + status = info->read_memory_func (fp_addr - 32, fp_prev, 32, info); + if (status) + /* No previous instruction to be parallel with. */ + p_bit = FALSE; + else + { + bfd_boolean prev_header_based; + tic6x_fetch_packet_header prev_header; + + prev_header_based + = tic6x_check_fetch_packet_header (fp_prev, &prev_header, info); + if (prev_header_based && prev_header.word_compact[6]) + p_bit = prev_header.p_bits[13]; + else + { + unsigned int prev_opcode = tic6x_extract_32 (fp_prev + 28, + info); + p_bit = (prev_opcode & 0x1) ? TRUE : FALSE; + } + } + } + parallel = p_bit ? "|| " : ""; + + if (opc->func_unit == tic6x_func_unit_nfu) + func_unit = ""; + else + { + unsigned int fld_num; + char func_unit_char; + const char *data_str; + bfd_boolean have_areg = FALSE; + bfd_boolean have_cross = FALSE; + + func_unit_side = (opc->flags & TIC6X_FLAG_SIDE_B_ONLY) ? 2 : 0; + func_unit_cross = 0; + func_unit_data_side = (opc->flags & TIC6X_FLAG_SIDE_T2_ONLY) ? 2 : 0; + + for (fld_num = 0; fld_num < opc->num_variable_fields; fld_num++) + { + const tic6x_coding_field *const enc = &opc->variable_fields[fld_num]; + const tic6x_insn_field *field; + unsigned int fld_val; + + field = tic6x_field_from_fmt (fmt, enc->field_id); + if (!field) + abort (); + fld_val = tic6x_field_bits (opcode, field); + switch (enc->coding_method) + { + case tic6x_coding_fu: + /* The side must be specified exactly once. */ + if (func_unit_side) + abort (); + func_unit_side = (fld_val ? 2 : 1); + break; + + case tic6x_coding_data_fu: + /* The data side must be specified exactly once. */ + if (func_unit_data_side) + abort (); + func_unit_data_side = (fld_val ? 2 : 1); + break; + + case tic6x_coding_xpath: + /* Cross path use must be specified exactly + once. */ + if (have_cross) + abort (); + have_cross = TRUE; + func_unit_cross = fld_val; + break; + + case tic6x_coding_areg: + have_areg = TRUE; + break; + + default: + /* Don't relate to functional units. */ + break; + } + } + + /* The side of the functional unit used must now have been + determined either from the flags or from an instruction + field. */ + if (func_unit_side != 1 && func_unit_side != 2) + abort (); + + /* Cross paths are not applicable when sides are specified + for both address and data paths. */ + if (func_unit_data_side && have_cross) + abort (); + + /* Separate address and data paths are only applicable for + the D unit. */ + if (func_unit_data_side && opc->func_unit != tic6x_func_unit_d) + abort (); + + /* If an address register is being used but in ADDA rather + than a load or store, it uses a cross path for side-A + instructions, and the cross path use is not specified by + an instruction field. */ + if (have_areg && !func_unit_data_side) + { + if (have_cross) + abort (); + func_unit_cross = (func_unit_side == 1 ? TRUE : FALSE); + } + + switch (opc->func_unit) + { + case tic6x_func_unit_d: + func_unit_char = 'D'; + break; + + case tic6x_func_unit_l: + func_unit_char = 'L'; + break; + + case tic6x_func_unit_m: + func_unit_char = 'M'; + break; + + case tic6x_func_unit_s: + func_unit_char = 'S'; + break; + + default: + abort (); + } + + switch (func_unit_data_side) + { + case 0: + data_str = ""; + break; + + case 1: + data_str = "T1"; + break; + + case 2: + data_str = "T2"; + break; + + default: + abort (); + } + + snprintf (func_unit_buf, 7, " .%c%u%s%s", func_unit_char, + func_unit_side, (func_unit_cross ? "X" : ""), data_str); + func_unit = func_unit_buf; + } + + /* For each operand there must be one or more fields set based + on that operand, that can together be used to derive the + operand value. */ + operands_ok = TRUE; + num_operands = opc->num_operands; + for (op_num = 0; op_num < num_operands; op_num++) + { + unsigned int fld_num; + unsigned int mem_base_reg = 0; + bfd_boolean mem_base_reg_known = FALSE; + bfd_boolean mem_base_reg_known_long = FALSE; + unsigned int mem_offset = 0; + bfd_boolean mem_offset_known = FALSE; + bfd_boolean mem_offset_known_long = FALSE; + unsigned int mem_mode = 0; + bfd_boolean mem_mode_known = FALSE; + unsigned int mem_scaled = 0; + bfd_boolean mem_scaled_known = FALSE; + unsigned int crlo = 0; + bfd_boolean crlo_known = FALSE; + unsigned int crhi = 0; + bfd_boolean crhi_known = FALSE; + bfd_boolean spmask_skip_operand = FALSE; + unsigned int fcyc_bits = 0; + bfd_boolean prev_sploop_found = FALSE; + + switch (opc->operand_info[op_num].form) + { + case tic6x_operand_retreg: + /* Fully determined by the functional unit. */ + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%c3", + (func_unit_side == 2 ? 'b' : 'a')); + continue; + + case tic6x_operand_irp: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "irp"); + continue; + + case tic6x_operand_nrp: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "nrp"); + continue; + + default: + break; + } + + for (fld_num = 0; fld_num < opc->num_variable_fields; fld_num++) + { + const tic6x_coding_field *const enc + = &opc->variable_fields[fld_num]; + const tic6x_insn_field *field; + unsigned int fld_val; + signed int signed_fld_val; + + if (enc->operand_num != op_num) + continue; + field = tic6x_field_from_fmt (fmt, enc->field_id); + if (!field) + abort (); + fld_val = tic6x_field_bits (opcode, field); + switch (enc->coding_method) + { + case tic6x_coding_ucst: + case tic6x_coding_ulcst_dpr_byte: + case tic6x_coding_ulcst_dpr_half: + case tic6x_coding_ulcst_dpr_word: + case tic6x_coding_lcst_low16: + switch (opc->operand_info[op_num].form) + { + case tic6x_operand_asm_const: + case tic6x_operand_link_const: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%u", fld_val); + break; + + case tic6x_operand_mem_long: + mem_offset = fld_val; + mem_offset_known_long = TRUE; + break; + + default: + abort (); + } + break; + + case tic6x_coding_lcst_high16: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%u", fld_val << 16); + break; + + case tic6x_coding_scst: + operands_text[op_num] = TRUE; + signed_fld_val = (signed int) fld_val; + signed_fld_val ^= (1 << (field->width - 1)); + signed_fld_val -= (1 << (field->width - 1)); + snprintf (operands[op_num], 24, "%d", signed_fld_val); + break; + + case tic6x_coding_ucst_minus_one: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%u", fld_val + 1); + break; + + case tic6x_coding_pcrel: + case tic6x_coding_pcrel_half: + signed_fld_val = (signed int) fld_val; + signed_fld_val ^= (1 << (field->width - 1)); + signed_fld_val -= (1 << (field->width - 1)); + if (fetch_packet_header_based + && enc->coding_method == tic6x_coding_pcrel_half) + signed_fld_val *= 2; + else + signed_fld_val *= 4; + operands_pcrel[op_num] = TRUE; + operands_addresses[op_num] = fp_addr + signed_fld_val; + break; + + case tic6x_coding_reg_shift: + fld_val <<= 1; + /* Fall through. */ + case tic6x_coding_reg: + switch (opc->operand_info[op_num].form) + { + case tic6x_operand_reg: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%c%u", + (func_unit_side == 2 ? 'b' : 'a'), fld_val); + break; + + case tic6x_operand_xreg: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%c%u", + (((func_unit_side == 2) ^ func_unit_cross) + ? 'b' + : 'a'), fld_val); + break; + + case tic6x_operand_dreg: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%c%u", + (func_unit_data_side == 2 ? 'b' : 'a'), + fld_val); + break; + + case tic6x_operand_regpair: + operands_text[op_num] = TRUE; + if (fld_val & 1) + operands_ok = FALSE; + snprintf (operands[op_num], 24, "%c%u:%c%u", + (func_unit_side == 2 ? 'b' : 'a'), fld_val + 1, + (func_unit_side == 2 ? 'b' : 'a'), fld_val); + break; + + case tic6x_operand_xregpair: + operands_text[op_num] = TRUE; + if (fld_val & 1) + operands_ok = FALSE; + snprintf (operands[op_num], 24, "%c%u:%c%u", + (((func_unit_side == 2) ^ func_unit_cross) + ? 'b' + : 'a'), fld_val + 1, + (((func_unit_side == 2) ^ func_unit_cross) + ? 'b' + : 'a'), fld_val); + break; + + case tic6x_operand_dregpair: + operands_text[op_num] = TRUE; + if (fld_val & 1) + operands_ok = FALSE; + snprintf (operands[op_num], 24, "%c%u:%c%u", + (func_unit_data_side == 2 ? 'b' : 'a'), + fld_val + 1, + (func_unit_data_side == 2 ? 'b' : 'a'), + fld_val); + break; + + case tic6x_operand_mem_deref: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "*%c%u", + (func_unit_side == 2 ? 'b' : 'a'), fld_val); + break; + + case tic6x_operand_mem_short: + case tic6x_operand_mem_ndw: + mem_base_reg = fld_val; + mem_base_reg_known = TRUE; + break; + + default: + abort (); + } + break; + + case tic6x_coding_areg: + switch (opc->operand_info[op_num].form) + { + case tic6x_operand_areg: + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "b%u", + fld_val ? 15u : 14u); + break; + + case tic6x_operand_mem_long: + mem_base_reg = fld_val ? 15u : 14u; + mem_base_reg_known_long = TRUE; + break; + + default: + abort (); + } + break; + + case tic6x_coding_mem_offset: + case tic6x_coding_mem_offset_noscale: + mem_offset = fld_val; + mem_offset_known = TRUE; + break; + + case tic6x_coding_mem_mode: + mem_mode = fld_val; + mem_mode_known = TRUE; + break; + + case tic6x_coding_scaled: + mem_scaled = fld_val; + mem_scaled_known = TRUE; + break; + + case tic6x_coding_crlo: + crlo = fld_val; + crlo_known = TRUE; + break; + + case tic6x_coding_crhi: + crhi = fld_val; + crhi_known = TRUE; + break; + + case tic6x_coding_fstg: + case tic6x_coding_fcyc: + if (!prev_sploop_found) + { + bfd_vma search_fp_addr = fp_addr; + bfd_vma search_fp_offset = fp_offset; + bfd_boolean search_fp_header_based + = fetch_packet_header_based; + tic6x_fetch_packet_header search_fp_header = header; + unsigned char search_fp[32]; + unsigned int search_num_bits; + unsigned int search_opcode; + unsigned int sploop_ii = 0; + int i; + + memcpy (search_fp, fp, 32); + + /* To interpret these bits in an SPKERNEL + instruction, we must find the previous + SPLOOP-family instruction. It may come up to + 48 execute packets earlier. */ + for (i = 0; i < 48 * 8; i++) + { + /* Find the previous instruction. */ + if (search_fp_offset & 2) + search_fp_offset -= 2; + else if (search_fp_offset >= 4) + { + if (search_fp_header_based + && (search_fp_header.word_compact + [(search_fp_offset >> 2) - 1])) + search_fp_offset -= 2; + else + search_fp_offset -= 4; + } + else + { + search_fp_addr -= 32; + status = info->read_memory_func (search_fp_addr, + search_fp, + 32, info); + if (status) + /* No previous SPLOOP instruction. */ + break; + search_fp_header_based + = (tic6x_check_fetch_packet_header + (search_fp, &search_fp_header, info)); + if (search_fp_header_based) + search_fp_offset + = search_fp_header.word_compact[6] ? 26 : 24; + else + search_fp_offset = 28; + } + + /* Extract the previous instruction. */ + if (search_fp_header_based) + search_num_bits + = (search_fp_header.word_compact[search_fp_offset + >> 2] + ? 16 + : 32); + else + search_num_bits = 32; + if (search_num_bits == 16) + { + if (info->endian == BFD_ENDIAN_LITTLE) + search_opcode + = (tic6x_extract_16 + (search_fp + search_fp_offset, info)); + else + search_opcode + = (tic6x_extract_16 + (search_fp + (search_fp_offset ^ 2), + info)); + } + else + search_opcode + = tic6x_extract_32 (search_fp + search_fp_offset, + info); + + /* Check whether it is an SPLOOP-family + instruction. */ + if (search_num_bits == 32 + && ((search_opcode & 0x003ffffe) == 0x00038000 + || (search_opcode & 0x003ffffe) == 0x0003a000 + || ((search_opcode & 0x003ffffe) + == 0x0003e000))) + { + prev_sploop_found = TRUE; + sploop_ii = ((search_opcode >> 23) & 0x1f) + 1; + } + else if (search_num_bits == 16 + && (search_opcode & 0x3c7e) == 0x0c66) + { + prev_sploop_found = TRUE; + sploop_ii + = (((search_opcode >> 7) & 0x7) + | ((search_opcode >> 11) & 0x8)) + 1; + } + if (prev_sploop_found) + { + if (sploop_ii <= 0) + abort (); + else if (sploop_ii <= 1) + fcyc_bits = 0; + else if (sploop_ii <= 2) + fcyc_bits = 1; + else if (sploop_ii <= 4) + fcyc_bits = 2; + else if (sploop_ii <= 8) + fcyc_bits = 3; + else if (sploop_ii <= 14) + fcyc_bits = 4; + else + prev_sploop_found = FALSE; + } + if (prev_sploop_found) + break; + } + } + if (!prev_sploop_found) + { + operands_ok = FALSE; + operands_text[op_num] = TRUE; + break; + } + if (fcyc_bits > field->width) + abort (); + if (enc->coding_method == tic6x_coding_fstg) + { + int i, t; + for (t = 0, i = fcyc_bits; i < 6; i++) + t = (t << 1) | ((fld_val >> i) & 1); + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%u", t); + } + else + { + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%u", + fld_val & ((1 << fcyc_bits) - 1)); + } + break; + + case tic6x_coding_spmask: + if (fld_val == 0) + spmask_skip_operand = TRUE; + else + { + char *p; + unsigned int i; + + operands_text[op_num] = TRUE; + p = operands[op_num]; + for (i = 0; i < 8; i++) + if (fld_val & (1 << i)) + { + *p++ = "LSDM"[i/2]; + *p++ = '1' + (i & 1); + *p++ = ','; + } + p[-1] = 0; + } + break; + + case tic6x_coding_fu: + case tic6x_coding_data_fu: + case tic6x_coding_xpath: + /* Don't relate to operands, so operand number is + meaningless. */ + break; + + default: + abort (); + } + + if (mem_base_reg_known_long && mem_offset_known_long) + { + if (operands_text[op_num] || operands_pcrel[op_num]) + abort (); + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "*+b%u(%u)", mem_base_reg, + mem_offset * opc->operand_info[op_num].size); + } + + if (mem_base_reg_known && mem_offset_known && mem_mode_known + && (mem_scaled_known + || (opc->operand_info[op_num].form + != tic6x_operand_mem_ndw))) + { + char side; + char base[4]; + bfd_boolean offset_is_reg; + bfd_boolean offset_scaled; + char offset[4]; + char offsetp[6]; + + if (operands_text[op_num] || operands_pcrel[op_num]) + abort (); + + side = func_unit_side == 2 ? 'b' : 'a'; + snprintf (base, 4, "%c%u", side, mem_base_reg); + + offset_is_reg = ((mem_mode & 4) ? TRUE : FALSE); + if (offset_is_reg) + { + snprintf (offset, 4, "%c%u", side, mem_offset); + if (opc->operand_info[op_num].form + == tic6x_operand_mem_ndw) + offset_scaled = mem_scaled ? TRUE : FALSE; + else + offset_scaled = TRUE; + } + else + { + if (opc->operand_info[op_num].form + == tic6x_operand_mem_ndw) + { + offset_scaled = mem_scaled ? TRUE : FALSE; + snprintf (offset, 4, "%u", mem_offset); + } + else + { + offset_scaled = FALSE; + snprintf (offset, 4, "%u", + (mem_offset + * opc->operand_info[op_num].size)); + } + } + + if (offset_scaled) + snprintf (offsetp, 6, "[%s]", offset); + else + snprintf (offsetp, 6, "(%s)", offset); + + operands_text[op_num] = TRUE; + switch (mem_mode & ~4u) + { + case 0: + snprintf (operands[op_num], 24, "*-%s%s", base, offsetp); + break; + + case 1: + snprintf (operands[op_num], 24, "*+%s%s", base, offsetp); + break; + + case 2: + case 3: + operands_ok = FALSE; + break; + + case 8: + snprintf (operands[op_num], 24, "*--%s%s", base, + offsetp); + break; + + case 9: + snprintf (operands[op_num], 24, "*++%s%s", base, + offsetp); + break; + + case 10: + snprintf (operands[op_num], 24, "*%s--%s", base, + offsetp); + break; + + case 11: + snprintf (operands[op_num], 24, "*%s++%s", base, + offsetp); + break; + + default: + abort (); + } + } + + if (crlo_known && crhi_known) + { + tic6x_rw rw; + tic6x_ctrl_id crid; + + if (operands_text[op_num] || operands_pcrel[op_num]) + abort (); + + rw = opc->operand_info[op_num].rw; + if (rw != tic6x_rw_read + && rw != tic6x_rw_write) + abort (); + + for (crid = 0; crid < tic6x_ctrl_max; crid++) + { + if (crlo == tic6x_ctrl_table[crid].crlo + && (crhi & tic6x_ctrl_table[crid].crhi_mask) == 0 + && (rw == tic6x_rw_read + ? (tic6x_ctrl_table[crid].rw == tic6x_rw_read + || (tic6x_ctrl_table[crid].rw + == tic6x_rw_read_write)) + : (tic6x_ctrl_table[crid].rw == tic6x_rw_write + || (tic6x_ctrl_table[crid].rw + == tic6x_rw_read_write)))) + break; + } + if (crid == tic6x_ctrl_max) + { + operands_text[op_num] = TRUE; + operands_ok = FALSE; + } + else + { + operands_text[op_num] = TRUE; + snprintf (operands[op_num], 24, "%s", + tic6x_ctrl_table[crid].name); + } + } + + if (operands_text[op_num] || operands_pcrel[op_num] + || spmask_skip_operand) + break; + } + if (spmask_skip_operand) + { + /* SPMASK operands are only valid as the single operand + in the opcode table. */ + if (num_operands != 1) + abort (); + num_operands = 0; + break; + } + /* The operand must by now have been decoded. */ + if (!operands_text[op_num] && !operands_pcrel[op_num]) + abort (); + } + + if (!operands_ok) + continue; + + info->bytes_per_chunk = num_bits / 8; + info->fprintf_func (info->stream, "%s%s%s%s", parallel, cond, + opc->name, func_unit); + for (op_num = 0; op_num < num_operands; op_num++) + { + info->fprintf_func (info->stream, "%c", (op_num == 0 ? ' ' : ',')); + if (operands_pcrel[op_num]) + info->print_address_func (operands_addresses[op_num], info); + else + info->fprintf_func (info->stream, "%s", operands[op_num]); + } + if (fetch_packet_header_based && header.prot) + info->fprintf_func (info->stream, " || nop 5"); + + return num_bits / 8; + } + + info->bytes_per_chunk = num_bits / 8; + info->fprintf_func (info->stream, "", + (int) num_bits / 4, opcode); + return num_bits / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/tic80-dis.c b/external/gpl3/gdb/dist/opcodes/tic80-dis.c new file mode 100644 index 000000000000..3089acca7294 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic80-dis.c @@ -0,0 +1,316 @@ +/* Print TI TMS320C80 (MVP) instructions + Copyright 1996, 1997, 1998, 2000, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include + +#include "sysdep.h" +#include "opcode/tic80.h" +#include "dis-asm.h" + +static int length; + +/* Print an integer operand. Try to be somewhat smart about the + format by assuming that small positive or negative integers are + probably loop increment values, structure offsets, or similar + values that are more meaningful printed as signed decimal values. + Larger numbers are probably better printed as hex values. */ + +static void +print_operand_integer (struct disassemble_info *info, long value) +{ + if ((value > 9999 || value < -9999)) + (*info->fprintf_func) (info->stream, "%#lx", value); + else + (*info->fprintf_func) (info->stream, "%ld", value); +} + +/* FIXME: depends upon sizeof (long) == sizeof (float) and + also upon host floating point format matching target + floating point format. */ + +static void +print_operand_float (struct disassemble_info *info, long value) +{ + union { float f; long l; } fval; + + fval.l = value; + (*info->fprintf_func) (info->stream, "%g", fval.f); +} + +static void +print_operand_control_register (struct disassemble_info *info, long value) +{ + const char *tmp; + + tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); + if (tmp != NULL) + (*info->fprintf_func) (info->stream, "%s", tmp); + else + (*info->fprintf_func) (info->stream, "%#lx", value); +} + +static void +print_operand_condition_code (struct disassemble_info *info, long value) +{ + const char *tmp; + + tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); + if (tmp != NULL) + (*info->fprintf_func) (info->stream, "%s", tmp); + else + (*info->fprintf_func) (info->stream, "%ld", value); +} + +static void +print_operand_bitnum (struct disassemble_info *info, long value) +{ + int bitnum; + const char *tmp; + + bitnum = ~value & 0x1F; + tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); + if (tmp != NULL) + (*info->fprintf_func) (info->stream, "%s", tmp); + else + (*info->fprintf_func) (info->stream, "%d", bitnum); +} + +/* Print the operand as directed by the flags. */ + +#define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) +#define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) +#define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) + +static void +print_operand (struct disassemble_info *info, + long value, + unsigned long insn, + const struct tic80_operand *operand, + bfd_vma memaddr) +{ + if ((operand->flags & TIC80_OPERAND_GPR) != 0) + { + (*info->fprintf_func) (info->stream, "r%ld", value); + if (M_SI (insn, operand) || M_LI (insn, operand)) + { + (*info->fprintf_func) (info->stream, ":m"); + } + } + else if ((operand->flags & TIC80_OPERAND_FPA) != 0) + (*info->fprintf_func) (info->stream, "a%ld", value); + + else if ((operand->flags & TIC80_OPERAND_PCREL) != 0) + (*info->print_address_func) (memaddr + 4 * value, info); + + else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0) + (*info->print_address_func) (value, info); + + else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0) + print_operand_bitnum (info, value); + + else if ((operand->flags & TIC80_OPERAND_CC) != 0) + print_operand_condition_code (info, value); + + else if ((operand->flags & TIC80_OPERAND_CR) != 0) + print_operand_control_register (info, value); + + else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0) + print_operand_float (info, value); + + else if ((operand->flags & TIC80_OPERAND_BITFIELD)) + (*info->fprintf_func) (info->stream, "%#lx", value); + + else + print_operand_integer (info, value); + + /* If this is a scaled operand, then print the modifier. */ + if (R_SCALED (insn, operand)) + (*info->fprintf_func) (info->stream, ":s"); +} + +/* Get the next 32 bit word from the instruction stream and convert it + into internal format in the unsigned long INSN, for which we are + passed the address. Return 0 on success, -1 on error. */ + +static int +fill_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long *insnp) +{ + bfd_byte buffer[4]; + int status; + + /* Get the bits for the next 32 bit word and put in buffer. */ + status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Read was successful, so increment count of bytes read and convert + the bits into internal format. */ + + length += 4; + if (info->endian == BFD_ENDIAN_LITTLE) + *insnp = bfd_getl32 (buffer); + + else if (info->endian == BFD_ENDIAN_BIG) + *insnp = bfd_getb32 (buffer); + + else + /* FIXME: Should probably just default to one or the other. */ + abort (); + + return 0; +} + +/* We have chosen an opcode table entry. */ + +static int +print_one_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long insn, + const struct tic80_opcode *opcode) +{ + const struct tic80_operand *operand; + long value; + int status; + const unsigned char *opindex; + int close_paren; + + (*info->fprintf_func) (info->stream, "%-10s", opcode->name); + + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + operand = tic80_operands + *opindex; + + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, NULL); + + else if (operand->bits == 32) + { + status = fill_instruction (info, memaddr, (unsigned long *) &value); + if (status == -1) + return status; + } + else + { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + + if ((operand->flags & TIC80_OPERAND_SIGNED) != 0 + && (value & (1 << (operand->bits - 1))) != 0) + value -= 1 << operand->bits; + } + + /* If this operand is enclosed in parenthesis, then print + the open paren, otherwise just print the regular comma + separator, except for the first operand. */ + if ((operand->flags & TIC80_OPERAND_PARENS) == 0) + { + close_paren = 0; + if (opindex != opcode->operands) + (*info->fprintf_func) (info->stream, ","); + } + else + { + close_paren = 1; + (*info->fprintf_func) (info->stream, "("); + } + + print_operand (info, value, insn, operand, memaddr); + + /* If we printed an open paren before printing this operand, close + it now. The flag gets reset on each loop. */ + if (close_paren) + (*info->fprintf_func) (info->stream, ")"); + } + + return length; +} + +/* There are no specific bits that tell us for certain whether a vector + instruction opcode contains one or two instructions. However since + a destination register of r0 is illegal, we can check for nonzero + values in both destination register fields. Only opcodes that have + two valid instructions will have non-zero in both. */ + +#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) + +static int +print_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long insn, + const struct tic80_opcode *vec_opcode) +{ + const struct tic80_opcode *opcode; + const struct tic80_opcode *opcode_end; + + /* Find the first opcode match in the opcodes table. For vector + opcodes (vec_opcode != NULL) find the first match that is not the + previously found match. FIXME: there should be faster ways to + search (hash table or binary search), but don't worry too much + about it until other TIc80 support is finished. */ + + opcode_end = tic80_opcodes + tic80_num_opcodes; + for (opcode = tic80_opcodes; opcode < opcode_end; opcode++) + { + if ((insn & opcode->mask) == opcode->opcode && + opcode != vec_opcode) + break; + } + + if (opcode == opcode_end) + { + /* No match found, just print the bits as a .word directive. */ + (*info->fprintf_func) (info->stream, ".word %#08lx", insn); + } + else + { + /* Match found, decode the instruction. */ + length = print_one_instruction (info, memaddr, insn, opcode); + if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) + { + /* There is another instruction to print from the same opcode. + Print the separator and then find and print the other + instruction. */ + (*info->fprintf_func) (info->stream, " || "); + length = print_instruction (info, memaddr, insn, opcode); + } + } + + return length; +} + +int +print_insn_tic80 (bfd_vma memaddr, struct disassemble_info *info) +{ + unsigned long insn; + int status; + + length = 0; + info->bytes_per_line = 8; + status = fill_instruction (info, memaddr, &insn); + if (status != -1) + status = print_instruction (info, memaddr, insn, NULL); + + return status; +} diff --git a/external/gpl3/gdb/dist/opcodes/tic80-opc.c b/external/gpl3/gdb/dist/opcodes/tic80-opc.c new file mode 100644 index 000000000000..70e38ec511f8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/tic80-opc.c @@ -0,0 +1,1216 @@ +/* Opcode table for TI TMS320C80 (MVP). + Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/tic80.h" + +/* This file holds various tables for the TMS320C80 (MVP). + + The opcode table is strictly constant data, so the compiler should + be able to put it in the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. + + The predefined register table maps from register names to register + values. */ + + +/* Table of predefined symbol names, such as general purpose registers, + floating point registers, condition codes, control registers, and bit + numbers. + + The table is sorted case independently by name so that it is suitable for + searching via a binary search using a case independent comparison + function. + + Note that the type of the symbol is stored in the upper bits of the value + field, which allows the value and type to be passed around as a unit in a + single int. The types have to be masked off before using the numeric + value as a number. +*/ + +const struct predefined_symbol tic80_predefined_symbols[] = +{ + { "a0", TIC80_OPERAND_FPA | 0 }, + { "a1", TIC80_OPERAND_FPA | 1 }, + { "alw.b", TIC80_OPERAND_CC | 7 }, + { "alw.h", TIC80_OPERAND_CC | 15 }, + { "alw.w", TIC80_OPERAND_CC | 23 }, + { "ANASTAT", TIC80_OPERAND_CR | 0x34 }, + { "BRK1", TIC80_OPERAND_CR | 0x39 }, + { "BRK2", TIC80_OPERAND_CR | 0x3A }, + { "CONFIG", TIC80_OPERAND_CR | 2 }, + { "DLRU", TIC80_OPERAND_CR | 0x500 }, + { "DTAG0", TIC80_OPERAND_CR | 0x400 }, + { "DTAG1", TIC80_OPERAND_CR | 0x401 }, + { "DTAG10", TIC80_OPERAND_CR | 0x40A }, + { "DTAG11", TIC80_OPERAND_CR | 0x40B }, + { "DTAG12", TIC80_OPERAND_CR | 0x40C }, + { "DTAG13", TIC80_OPERAND_CR | 0x40D }, + { "DTAG14", TIC80_OPERAND_CR | 0x40E }, + { "DTAG15", TIC80_OPERAND_CR | 0x40F }, + { "DTAG2", TIC80_OPERAND_CR | 0x402 }, + { "DTAG3", TIC80_OPERAND_CR | 0x403 }, + { "DTAG4", TIC80_OPERAND_CR | 0x404 }, + { "DTAG5", TIC80_OPERAND_CR | 0x405 }, + { "DTAG6", TIC80_OPERAND_CR | 0x406 }, + { "DTAG7", TIC80_OPERAND_CR | 0x407 }, + { "DTAG8", TIC80_OPERAND_CR | 0x408 }, + { "DTAG9", TIC80_OPERAND_CR | 0x409 }, + { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 }, + { "EIP", TIC80_OPERAND_CR | 1 }, + { "EPC", TIC80_OPERAND_CR | 0 }, + { "eq.b", TIC80_OPERAND_BITNUM | 0 }, + { "eq.f", TIC80_OPERAND_BITNUM | 20 }, + { "eq.h", TIC80_OPERAND_BITNUM | 10 }, + { "eq.w", TIC80_OPERAND_BITNUM | 20 }, + { "eq0.b", TIC80_OPERAND_CC | 2 }, + { "eq0.h", TIC80_OPERAND_CC | 10 }, + { "eq0.w", TIC80_OPERAND_CC | 18 }, + { "FLTADR", TIC80_OPERAND_CR | 0x11 }, + { "FLTDTH", TIC80_OPERAND_CR | 0x14 }, + { "FLTDTL", TIC80_OPERAND_CR | 0x13 }, + { "FLTOP", TIC80_OPERAND_CR | 0x10 }, + { "FLTTAG", TIC80_OPERAND_CR | 0x12 }, + { "FPST", TIC80_OPERAND_CR | 8 }, + { "ge.b", TIC80_OPERAND_BITNUM | 5 }, + { "ge.f", TIC80_OPERAND_BITNUM | 25 }, + { "ge.h", TIC80_OPERAND_BITNUM | 15 }, + { "ge.w", TIC80_OPERAND_BITNUM | 25 }, + { "ge0.b", TIC80_OPERAND_CC | 3 }, + { "ge0.h", TIC80_OPERAND_CC | 11 }, + { "ge0.w", TIC80_OPERAND_CC | 19 }, + { "gt.b", TIC80_OPERAND_BITNUM | 2 }, + { "gt.f", TIC80_OPERAND_BITNUM | 22 }, + { "gt.h", TIC80_OPERAND_BITNUM | 12 }, + { "gt.w", TIC80_OPERAND_BITNUM | 22 }, + { "gt0.b", TIC80_OPERAND_CC | 1 }, + { "gt0.h", TIC80_OPERAND_CC | 9 }, + { "gt0.w", TIC80_OPERAND_CC | 17 }, + { "hi.b", TIC80_OPERAND_BITNUM | 6 }, + { "hi.h", TIC80_OPERAND_BITNUM | 16 }, + { "hi.w", TIC80_OPERAND_BITNUM | 26 }, + { "hs.b", TIC80_OPERAND_BITNUM | 9 }, + { "hs.h", TIC80_OPERAND_BITNUM | 19 }, + { "hs.w", TIC80_OPERAND_BITNUM | 29 }, + { "ib.f", TIC80_OPERAND_BITNUM | 28 }, + { "IE", TIC80_OPERAND_CR | 6 }, + { "ILRU", TIC80_OPERAND_CR | 0x300 }, + { "in.f", TIC80_OPERAND_BITNUM | 27 }, + { "IN0P", TIC80_OPERAND_CR | 0x4000 }, + { "IN1P", TIC80_OPERAND_CR | 0x4001 }, + { "INTPEN", TIC80_OPERAND_CR | 4 }, + { "ITAG0", TIC80_OPERAND_CR | 0x200 }, + { "ITAG1", TIC80_OPERAND_CR | 0x201 }, + { "ITAG10", TIC80_OPERAND_CR | 0x20A }, + { "ITAG11", TIC80_OPERAND_CR | 0x20B }, + { "ITAG12", TIC80_OPERAND_CR | 0x20C }, + { "ITAG13", TIC80_OPERAND_CR | 0x20D }, + { "ITAG14", TIC80_OPERAND_CR | 0x20E }, + { "ITAG15", TIC80_OPERAND_CR | 0x20F }, + { "ITAG2", TIC80_OPERAND_CR | 0x202 }, + { "ITAG3", TIC80_OPERAND_CR | 0x203 }, + { "ITAG4", TIC80_OPERAND_CR | 0x204 }, + { "ITAG5", TIC80_OPERAND_CR | 0x205 }, + { "ITAG6", TIC80_OPERAND_CR | 0x206 }, + { "ITAG7", TIC80_OPERAND_CR | 0x207 }, + { "ITAG8", TIC80_OPERAND_CR | 0x208 }, + { "ITAG9", TIC80_OPERAND_CR | 0x209 }, + { "le.b", TIC80_OPERAND_BITNUM | 3 }, + { "le.f", TIC80_OPERAND_BITNUM | 23 }, + { "le.h", TIC80_OPERAND_BITNUM | 13 }, + { "le.w", TIC80_OPERAND_BITNUM | 23 }, + { "le0.b", TIC80_OPERAND_CC | 6 }, + { "le0.h", TIC80_OPERAND_CC | 14 }, + { "le0.w", TIC80_OPERAND_CC | 22 }, + { "lo.b", TIC80_OPERAND_BITNUM | 8 }, + { "lo.h", TIC80_OPERAND_BITNUM | 18 }, + { "lo.w", TIC80_OPERAND_BITNUM | 28 }, + { "ls.b", TIC80_OPERAND_BITNUM | 7 }, + { "ls.h", TIC80_OPERAND_BITNUM | 17 }, + { "ls.w", TIC80_OPERAND_BITNUM | 27 }, + { "lt.b", TIC80_OPERAND_BITNUM | 4 }, + { "lt.f", TIC80_OPERAND_BITNUM | 24 }, + { "lt.h", TIC80_OPERAND_BITNUM | 14 }, + { "lt.w", TIC80_OPERAND_BITNUM | 24 }, + { "lt0.b", TIC80_OPERAND_CC | 4 }, + { "lt0.h", TIC80_OPERAND_CC | 12 }, + { "lt0.w", TIC80_OPERAND_CC | 20 }, + { "MIP", TIC80_OPERAND_CR | 0x31 }, + { "MPC", TIC80_OPERAND_CR | 0x30 }, + { "ne.b", TIC80_OPERAND_BITNUM | 1 }, + { "ne.f", TIC80_OPERAND_BITNUM | 21 }, + { "ne.h", TIC80_OPERAND_BITNUM | 11 }, + { "ne.w", TIC80_OPERAND_BITNUM | 21 }, + { "ne0.b", TIC80_OPERAND_CC | 5 }, + { "ne0.h", TIC80_OPERAND_CC | 13 }, + { "ne0.w", TIC80_OPERAND_CC | 21 }, + { "nev.b", TIC80_OPERAND_CC | 0 }, + { "nev.h", TIC80_OPERAND_CC | 8 }, + { "nev.w", TIC80_OPERAND_CC | 16 }, + { "ob.f", TIC80_OPERAND_BITNUM | 29 }, + { "or.f", TIC80_OPERAND_BITNUM | 31 }, + { "ou.f", TIC80_OPERAND_BITNUM | 26 }, + { "OUTP", TIC80_OPERAND_CR | 0x4002 }, + { "PKTREQ", TIC80_OPERAND_CR | 0xD }, + { "PPERROR", TIC80_OPERAND_CR | 0xA }, + { "r0", TIC80_OPERAND_GPR | 0 }, + { "r1", TIC80_OPERAND_GPR | 1 }, + { "r10", TIC80_OPERAND_GPR | 10 }, + { "r11", TIC80_OPERAND_GPR | 11 }, + { "r12", TIC80_OPERAND_GPR | 12 }, + { "r13", TIC80_OPERAND_GPR | 13 }, + { "r14", TIC80_OPERAND_GPR | 14 }, + { "r15", TIC80_OPERAND_GPR | 15 }, + { "r16", TIC80_OPERAND_GPR | 16 }, + { "r17", TIC80_OPERAND_GPR | 17 }, + { "r18", TIC80_OPERAND_GPR | 18 }, + { "r19", TIC80_OPERAND_GPR | 19 }, + { "r2", TIC80_OPERAND_GPR | 2 }, + { "r20", TIC80_OPERAND_GPR | 20 }, + { "r21", TIC80_OPERAND_GPR | 21 }, + { "r22", TIC80_OPERAND_GPR | 22 }, + { "r23", TIC80_OPERAND_GPR | 23 }, + { "r24", TIC80_OPERAND_GPR | 24 }, + { "r25", TIC80_OPERAND_GPR | 25 }, + { "r26", TIC80_OPERAND_GPR | 26 }, + { "r27", TIC80_OPERAND_GPR | 27 }, + { "r28", TIC80_OPERAND_GPR | 28 }, + { "r29", TIC80_OPERAND_GPR | 29 }, + { "r3", TIC80_OPERAND_GPR | 3 }, + { "r30", TIC80_OPERAND_GPR | 30 }, + { "r31", TIC80_OPERAND_GPR | 31 }, + { "r4", TIC80_OPERAND_GPR | 4 }, + { "r5", TIC80_OPERAND_GPR | 5 }, + { "r6", TIC80_OPERAND_GPR | 6 }, + { "r7", TIC80_OPERAND_GPR | 7 }, + { "r8", TIC80_OPERAND_GPR | 8 }, + { "r9", TIC80_OPERAND_GPR | 9 }, + { "SYSSTK", TIC80_OPERAND_CR | 0x20 }, + { "SYSTMP", TIC80_OPERAND_CR | 0x21 }, + { "TCOUNT", TIC80_OPERAND_CR | 0xE }, + { "TSCALE", TIC80_OPERAND_CR | 0xF }, + { "uo.f", TIC80_OPERAND_BITNUM | 30 }, +}; + +const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol); + +/* This function takes a predefined symbol name in NAME, symbol class + in CLASS, and translates it to a numeric value, which it returns. + + If CLASS is zero, any symbol that matches NAME is translated. If + CLASS is non-zero, then only a symbol that has symbol_class CLASS is + matched. + + If no translation is possible, it returns -1, a value not used by + any predefined symbol. Note that the predefined symbol array is + presorted case independently by name. + + This function is implemented with the assumption that there are no + duplicate names in the predefined symbol array, which happens to be + true at the moment. + + */ + +int +tic80_symbol_to_value (name, symbol_class) + char *name; + int symbol_class; +{ + const struct predefined_symbol *pdsp; + int low = 0; + int middle; + int high = tic80_num_predefined_symbols - 1; + int cmp; + int rtnval = -1; + + while (low <= high) + { + middle = (low + high) / 2; + cmp = strcasecmp (name, tic80_predefined_symbols[middle].name); + if (cmp < 0) + { + high = middle - 1; + } + else if (cmp > 0) + { + low = middle + 1; + } + else + { + pdsp = &tic80_predefined_symbols[middle]; + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) + { + rtnval = PDS_VALUE (pdsp); + } + /* For now we assume that there are no duplicate names */ + break; + } + } + return (rtnval); +} + +/* This function takes a value VAL and finds a matching predefined + symbol that is in the operand symbol_class specified by CLASS. If CLASS + is zero, the first matching symbol is returned. */ + +const char * +tic80_value_to_symbol (val, symbol_class) + int val; + int symbol_class; +{ + const struct predefined_symbol *pdsp; + int ival; + char *name; + + name = NULL; + for (pdsp = tic80_predefined_symbols; + pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols; + pdsp++) + { + ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; + if (ival == val) + { + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) + { + /* Found the desired match */ + name = PDS_NAME (pdsp); + break; + } + } + } + return (name); +} + +/* This function returns a pointer to the next symbol in the predefined + symbol table after PDSP, or NULL if PDSP points to the last symbol. If + PDSP is NULL, it returns the first symbol in the table. Thus it can be + used to walk through the table by first calling it with NULL and then + calling it with each value it returned on the previous call, until it + returns NULL. */ + +const struct predefined_symbol * +tic80_next_predefined_symbol (pdsp) + const struct predefined_symbol *pdsp; +{ + if (pdsp == NULL) + { + pdsp = tic80_predefined_symbols; + } + else if (pdsp >= tic80_predefined_symbols && + pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1) + { + pdsp++; + } + else + { + pdsp = NULL; + } + return (pdsp); +} + + + +/* The operands table. The fields are: + + bits, shift, insertion function, extraction function, flags + */ + +const struct tic80_operand tic80_operands[] = +{ + + /* The zero index is used to indicate the end of the list of operands. */ + +#define UNUSED (0) + { 0, 0, 0, 0, 0 }, + + /* Short signed immediate value in bits 14-0. */ + +#define SSI (UNUSED + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, + + /* Short unsigned immediate value in bits 14-0 */ + +#define SUI (SSI + 1) + { 15, 0, NULL, NULL, 0 }, + + /* Short unsigned bitfield in bits 14-0. We distinguish this + from a regular unsigned immediate value only for the convenience + of the disassembler and the user. */ + +#define SUBF (SUI + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, + + /* Long signed immediate in following 32 bit word */ + +#define LSI (SUBF + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, + + /* Long unsigned immediate in following 32 bit word */ + +#define LUI (LSI + 1) + { 32, 0, NULL, NULL, 0 }, + + /* Long unsigned bitfield in following 32 bit word. We distinguish + this from a regular unsigned immediate value only for the + convenience of the disassembler and the user. */ + +#define LUBF (LUI + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, + + /* Single precision floating point immediate in following 32 bit + word. */ + +#define SPFI (LUBF + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT }, + + /* Register in bits 4-0 */ + +#define REG_0 (SPFI + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 4-0 */ + +#define REG_0_E (REG_0 + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Register in bits 26-22 */ + +#define REG_22 (REG_0_E + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 26-22 */ + +#define REG_22_E (REG_22 + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Register in bits 31-27 */ + +#define REG_DEST (REG_22_E + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_GPR }, + + /* Even register in bits 31-27 */ + +#define REG_DEST_E (REG_DEST + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, + + /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB) + and bit 11 (LSB) */ + /* FIXME! Needs to use functions to insert and extract the register + number in bits 16 and 11. */ + +#define REG_FPA (REG_DEST_E + 1) + { 0, 0, NULL, NULL, TIC80_OPERAND_FPA }, + + /* Short signed PC word offset in bits 14-0 */ + +#define OFF_SS_PC (REG_FPA + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, + + /* Long signed PC word offset in following 32 bit word */ + +#define OFF_SL_PC (OFF_SS_PC + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, + + /* Short signed base relative byte offset in bits 14-0 */ + +#define OFF_SS_BR (OFF_SL_PC + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + + /* Long signed base relative byte offset in following 32 bit word */ + +#define OFF_SL_BR (OFF_SS_BR + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + + /* Long signed base relative byte offset in following 32 bit word + with optional ":s" modifier flag in bit 11 */ + +#define OFF_SL_BR_SCALED (OFF_SL_BR + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, + + /* BITNUM in bits 31-27 */ + +#define BITNUM (OFF_SL_BR_SCALED + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, + + /* Condition code in bits 31-27 */ + +#define CC (BITNUM + 1) + { 5, 27, NULL, NULL, TIC80_OPERAND_CC }, + + /* Control register number in bits 14-0 */ + +#define CR_SI (CC + 1) + { 15, 0, NULL, NULL, TIC80_OPERAND_CR }, + + /* Control register number in next 32 bit word */ + +#define CR_LI (CR_SI + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, + + /* A base register in bits 26-22, enclosed in parens */ + +#define REG_BASE (CR_LI + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS }, + + /* A base register in bits 26-22, enclosed in parens, with optional ":m" + flag in bit 17 (short immediate instructions only) */ + +#define REG_BASE_M_SI (REG_BASE + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, + + /* A base register in bits 26-22, enclosed in parens, with optional ":m" + flag in bit 15 (long immediate and register instructions only) */ + +#define REG_BASE_M_LI (REG_BASE_M_SI + 1) + { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, + + /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */ + +#define REG_SCALED (REG_BASE_M_LI + 1) + { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, + + /* Unsigned immediate in bits 4-0, used only for shift instructions */ + +#define ROTATE (REG_SCALED + 1) + { 5, 0, NULL, NULL, 0 }, + + /* Unsigned immediate in bits 9-5, used only for shift instructions */ +#define ENDMASK (ROTATE + 1) + { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK }, + +}; + +const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); + + +/* Macros used to generate entries for the opcodes table. */ + +#define FIXME 0 + +/* Short-Immediate Format Instructions - basic opcode */ +#define OP_SI(x) (((x) & 0x7F) << 15) +#define MASK_SI OP_SI(0x7F) + +/* Long-Immediate Format Instructions - basic opcode */ +#define OP_LI(x) (((x) & 0x3FF) << 12) +#define MASK_LI OP_LI(0x3FF) + +/* Register Format Instructions - basic opcode */ +#define OP_REG(x) OP_LI(x) /* For readability */ +#define MASK_REG MASK_LI /* For readability */ + +/* The 'n' bit at bit 10 */ +#define n(x) ((x) << 10) + +/* The 'i' bit at bit 11 */ +#define i(x) ((x) << 11) + +/* The 'F' bit at bit 27 */ +#define F(x) ((x) << 27) + +/* The 'E' bit at bit 27 */ +#define E(x) ((x) << 27) + +/* The 'M' bit at bit 15 in register and long immediate opcodes */ +#define M_REG(x) ((x) << 15) +#define M_LI(x) ((x) << 15) + +/* The 'M' bit at bit 17 in short immediate opcodes */ +#define M_SI(x) ((x) << 17) + +/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ +#define SZ_REG(x) ((x) << 13) +#define SZ_LI(x) ((x) << 13) + +/* The 'SZ' field at bits 16-15 in short immediate opcodes */ +#define SZ_SI(x) ((x) << 15) + +/* The 'D' (direct external memory access) bit at bit 10 in long immediate + and register opcodes. */ +#define D(x) ((x) << 10) + +/* The 'S' (scale offset by data size) bit at bit 11 in long immediate + and register opcodes. */ +#define S(x) ((x) << 11) + +/* The 'PD' field at bits 10-9 in floating point instructions */ +#define PD(x) ((x) << 9) + +/* The 'P2' field at bits 8-7 in floating point instructions */ +#define P2(x) ((x) << 7) + +/* The 'P1' field at bits 6-5 in floating point instructions */ +#define P1(x) ((x) << 5) + +/* The 'a' field at bit 16 in vector instructions */ +#define V_a1(x) ((x) << 16) + +/* The 'a' field at bit 11 in vector instructions */ +#define V_a0(x) ((x) << 11) + +/* The 'm' field at bit 10 in vector instructions */ +#define V_m(x) ((x) << 10) + +/* The 'S' field at bit 9 in vector instructions */ +#define V_S(x) ((x) << 9) + +/* The 'Z' field at bit 8 in vector instructions */ +#define V_Z(x) ((x) << 8) + +/* The 'p' field at bit 6 in vector instructions */ +#define V_p(x) ((x) << 6) + +/* The opcode field at bits 21-17 for vector instructions */ +#define OP_V(x) ((x) << 17) +#define MASK_V OP_V(0x1F) + + +/* The opcode table. Formatted for better readability on a wide screen. Also, all + entries with the same mnemonic are sorted so that they are adjacent in the table, + allowing the use of a hash table to locate the first of a sequence of opcodes that have + a particular name. The short immediate forms also come before the long immediate forms + so that the assembler will pick the "best fit" for the size of the operand, except for + the case of the PC relative forms, where the long forms come first and are the default + forms. */ + +const struct tic80_opcode tic80_opcodes[] = { + + /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this + specific bit pattern will get disassembled as a nop rather than an rdcr. The + mask of all ones ensures that this will happen. */ + + {"nop", OP_SI(0x4), ~0, 0, {0} }, + + /* The "br" instruction is really "bbz target,r0,31". We put it first so that + this specific bit pattern will get disassembled as a br rather than bbz. */ + + {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, + {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, + {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, + {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, + + /* Signed integer ADD */ + + {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Unsigned integer ADD */ + + {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND */ + + {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of both sources */ + + {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of source 1 */ + + {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Bitwise AND with ones complement of source 2 */ + + {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Branch Bit One - nonannulled */ + + {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit One - annulled */ + + {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit Zero - nonannulled */ + + {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Bit Zero - annulled */ + + {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, + {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, + + /* Branch Conditional - nonannulled */ + + {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, + {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, + + /* Branch Conditional - annulled */ + + {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, + {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, + + /* Branch Control Register */ + + {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, + {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, + {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, + + /* Branch and save return - nonannulled */ + + {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, + {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, + + /* Branch and save return - annulled */ + + {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, + {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, + + /* Send command */ + + {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, + {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, + {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, + + /* Integer compare */ + + {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Flush data cache subblock - don't clear subblock preset flag */ + + {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, + {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, + {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, + + /* Flush data cache subblock - clear subblock preset flag */ + + {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, + {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, + {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, + + /* Direct load signed data into register */ + + {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Direct load unsigned data into register */ + + {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Direct store data into memory */ + + {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Emulation stop */ + + {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} }, + + /* Emulation trap */ + + {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, + {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, + {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, + + /* Floating-point addition */ + + {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point compare */ + + {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} }, + {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} }, + {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} }, + {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} }, + {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point divide */ + + {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Floating point multiply */ + + {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} }, + {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} }, + {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Convert/Round to Minus Infinity */ + + {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Nearest */ + + {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Positive Infinity */ + + {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Convert/Round to Zero */ + + {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, + {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, + {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, + {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Floating point square root */ + + {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, + {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, + {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, + {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, + {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, + + /* Floating point subtraction */ + + { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, + { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, + { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, + { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, + { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, + { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, + { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, + { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, + + /* Illegal instructions */ + + {"illop0", OP_SI(0x0), MASK_SI, 0, {0} }, + {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} }, + + /* Jump and save return */ + + {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, + {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, + {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, + {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, + {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, + {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, + + /* Load Signed Data Into Register */ + + {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Load Unsigned Data Into Register */ + + {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Leftmost one */ + + {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, + + /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */ + + {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, + {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Read Control Register */ + + {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, + {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, + {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, + + /* Rightmost one */ + + {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, + + /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions. + They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */ + + + {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Left With Inverted Endmask */ + + {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions. + They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */ + + {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Shift Register Right With Inverted Endmask */ + + {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, + {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, + + /* Store Data into Memory */ + + {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + + /* Signed Integer Subtract */ + + {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Unsigned Integer Subtract */ + + {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, + {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, + {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Write Control Register + Is a special form of the "swcr" instruction so comes before it in the table. */ + + {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, + {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, + {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, + + /* Swap Control Register */ + + {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, + {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, + {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + /* Trap */ + + {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, + {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, + {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, + + /* Vector Floating-Point Add */ + + {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, + {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, + {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, + {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, + {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, + + /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented. + From the documentation there appears to be no way to tell the difference between the opcodes for + instructions that have register destinations and instructions that have accumulator destinations. + Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up + and running, it is defered until later. */ + + /* Vector Floating-Point Multiply + Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */ + + {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} }, + {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} }, + {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} }, + {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, + {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, + + /* Vector Floating-Point Multiply and Subtract from Accumulator + FIXME: See note above for vmac instruction */ + + /* Vector Floating-Point Subtract Accumulator From Source + FIXME: See note above for vmac instruction */ + + /* Vector Round With Floating-Point Input + FIXME: See note above for vmac instruction */ + + /* Vector Round with Integer Input */ + + {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}}, + {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, + {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, + {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, + {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}}, + {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, + {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, + {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, + + /* Vector Floating-Point Subtract */ + + {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, + {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, + {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, + {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, + {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, + + /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other + vector instructions so that the disassembler will always print the load/store instruction second for + vector instructions that have two instructions in the same opcode. */ + + {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + + /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other + vector instructions so that the disassembler will always print the load/store instruction second for + vector instructions that have two instructions in the same opcode. */ + + {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, + {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + + {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + + {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, + {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, + +}; + +const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]); diff --git a/external/gpl3/gdb/dist/opcodes/v850-dis.c b/external/gpl3/gdb/dist/opcodes/v850-dis.c new file mode 100644 index 000000000000..c3624b21f4be --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/v850-dis.c @@ -0,0 +1,635 @@ +/* Disassemble V850 instructions. + Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + + +#include + +#include "sysdep.h" +#include "opcode/v850.h" +#include "dis-asm.h" +#include "opintl.h" + +static const char *const v850_reg_names[] = +{ + "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" +}; + +static const char *const v850_sreg_names[] = +{ + "eipc/vip/mpm", "eipsw/mpc", "fepc/tid", "fepsw/ppa", "ecr/vmecr", "psw/vmtid", + "sr6/fpsr/vmadr/dcc", "sr7/fpepc/dc0", + "sr8/fpst/vpecr/dcv1", "sr9/fpcc/vptid", "sr10/fpcfg/vpadr/spal", "sr11/spau", + "sr12/vdecr/ipa0l", "eiic/vdtid/ipa0u", "feic/ipa1l", "dbic/ipa1u", + "ctpc/ipa2l", "ctpsw/ipa2u", "dbpc/ipa3l", "dbpsw/ipa3u", "ctbp/dpa0l", + "dir/dpa0u", "bpc/dpa0u", "asid/dpa1l", + "bpav/dpa1u", "bpam/dpa2l", "bpdv/dpa2u", "bpdm/dpa3l", "eiwr/dpa3u", + "fewr", "dbwr", "bsel" +}; + +static const char *const v850_cc_names[] = +{ + "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", + "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" +}; + +static const char *const v850_float_cc_names[] = +{ + "f/t", "un/or", "eq/neq", "ueq/ogl", "olt/uge", "ult/oge", "ole/ugt", "ule/ogt", + "sf/st", "ngle/gle", "seq/sne", "ngl/gl", "lt/nlt", "nge/ge", "le/nle", "ngt/gt" +}; + + +static void +print_value (int flags, bfd_vma memaddr, struct disassemble_info *info, long value) +{ + if (flags & V850_PCREL) + { + bfd_vma addr = value + memaddr; + info->print_address_func (addr, info); + } + else if (flags & V850_OPERAND_DISP) + { + if (flags & V850_OPERAND_SIGNED) + { + info->fprintf_func (info->stream, "%ld", value); + } + else + { + info->fprintf_func (info->stream, "%lu", value); + } + } + else if (flags & V850E_IMMEDIATE32) + { + info->fprintf_func (info->stream, "0x%lx", value); + } + else + { + if (flags & V850_OPERAND_SIGNED) + { + info->fprintf_func (info->stream, "%ld", value); + } + else + { + info->fprintf_func (info->stream, "%lu", value); + } + } +} + +static long +get_operand_value (const struct v850_operand *operand, + unsigned long insn, + int bytes_read, + bfd_vma memaddr, + struct disassemble_info * info, + bfd_boolean noerror, + int *invalid) +{ + long value; + bfd_byte buffer[4]; + + if ((operand->flags & V850E_IMMEDIATE16) + || (operand->flags & V850E_IMMEDIATE16HI)) + { + int status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); + + if (status == 0) + { + value = bfd_getl16 (buffer); + + if (operand->flags & V850E_IMMEDIATE16HI) + value <<= 16; + + return value; + } + + if (!noerror) + info->memory_error_func (status, memaddr + bytes_read, info); + + return 0; + } + + if (operand->flags & V850E_IMMEDIATE23) + { + int status = info->read_memory_func (memaddr + 2, buffer, 4, info); + + if (status == 0) + { + value = bfd_getl32 (buffer); + + value = (operand->extract) (value, invalid); + + return value; + } + + if (!noerror) + info->memory_error_func (status, memaddr + bytes_read, info); + + return 0; + } + + if (operand->flags & V850E_IMMEDIATE32) + { + int status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); + + if (status == 0) + { + bytes_read += 4; + value = bfd_getl32 (buffer); + + return value; + } + + if (!noerror) + info->memory_error_func (status, memaddr + bytes_read, info); + + return 0; + } + + if (operand->extract) + value = (operand->extract) (insn, invalid); + else + { + if (operand->bits == -1) + value = (insn & operand->shift); + else + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + + if (operand->flags & V850_OPERAND_SIGNED) + value = ((long)(value << (sizeof (long)*8 - operand->bits)) + >> (sizeof (long)*8 - operand->bits)); + } + + return value; +} + + +static int +disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, unsigned long insn) +{ + struct v850_opcode *op = (struct v850_opcode *)v850_opcodes; + const struct v850_operand *operand; + int match = 0; + int target_processor; + + switch (info->mach) + { + case 0: + default: + target_processor = PROCESSOR_V850; + break; + + case bfd_mach_v850e: + target_processor = PROCESSOR_V850E; + break; + + case bfd_mach_v850e1: + target_processor = PROCESSOR_V850E; + break; + + case bfd_mach_v850e2: + target_processor = PROCESSOR_V850E2; + break; + + case bfd_mach_v850e2v3: + target_processor = PROCESSOR_V850E2V3; + break; + } + + /* If this is a two byte insn, then mask off the high bits. */ + if (bytes_read == 2) + insn &= 0xffff; + + /* Find the opcode. */ + while (op->name) + { + if ((op->mask & insn) == op->opcode + && (op->processors & target_processor) + && !(op->processors & PROCESSOR_OPTION_ALIAS)) + { + /* Code check start. */ + const unsigned char *opindex_ptr; + unsigned int opnum; + unsigned int memop; + + for (opindex_ptr = op->operands, opnum = 1; + *opindex_ptr != 0; + opindex_ptr++, opnum++) + { + int invalid = 0; + long value; + + operand = &v850_operands[*opindex_ptr]; + + value = get_operand_value (operand, insn, bytes_read, memaddr, info, 1, &invalid); + + if (invalid) + goto next_opcode; + + if ((operand->flags & V850_NOT_R0) && value == 0 && (op->memop) <=2) + goto next_opcode; + + if ((operand->flags & V850_NOT_SA) && value == 0xd) + goto next_opcode; + + if ((operand->flags & V850_NOT_IMM0) && value == 0) + goto next_opcode; + } + + /* Code check end. */ + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); +#if 0 + fprintf (stderr, "match: insn: %lx, mask: %lx, opcode: %lx, name: %s\n", + insn, op->mask, op->opcode, op->name ); +#endif + + memop = op->memop; + /* Now print the operands. + + MEMOP is the operand number at which a memory + address specification starts, or zero if this + instruction has no memory addresses. + + A memory address is always two arguments. + + This information allows us to determine when to + insert commas into the output stream as well as + when to insert disp[reg] expressions onto the + output stream. */ + + for (opindex_ptr = op->operands, opnum = 1; + *opindex_ptr != 0; + opindex_ptr++, opnum++) + { + long value; + int flag; + char *prefix; + + operand = &v850_operands[*opindex_ptr]; + + value = get_operand_value (operand, insn, bytes_read, memaddr, info, 0, 0); + + /* The first operand is always output without any + special handling. + + For the following arguments: + + If memop && opnum == memop + 1, then we need '[' since + we're about to output the register used in a memory + reference. + + If memop && opnum == memop + 2, then we need ']' since + we just finished the register in a memory reference. We + also need a ',' before this operand. + + Else we just need a comma. + + We may need to output a trailing ']' if the last operand + in an instruction is the register for a memory address. + + The exception (and there's always an exception) is the + "jmp" insn which needs square brackets around it's only + register argument. */ + prefix = ""; + if (operand->flags & V850_OPERAND_BANG) + { + prefix = "!"; + } + else if (operand->flags & V850_OPERAND_PERCENT) + { + prefix = "%"; + } + + if (opnum == 1 && opnum == memop) + info->fprintf_func (info->stream, "%s[", prefix); + else if (opnum > 1 + && (v850_operands[*(opindex_ptr - 1)].flags & V850_OPERAND_DISP) != 0 + && opnum == memop) + info->fprintf_func (info->stream, "%s[", prefix); + else if (opnum > 1) + info->fprintf_func (info->stream, ", %s", prefix); + + /* Extract the flags, ignoring ones which do not effect disassembly output. */ + flag = operand->flags & (V850_OPERAND_REG + | V850_REG_EVEN + | V850_OPERAND_EP + | V850_OPERAND_SRG + | V850E_OPERAND_REG_LIST + | V850_OPERAND_CC + | V850_OPERAND_FLOAT_CC); + + switch (flag) + { + case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; + case (V850_OPERAND_REG|V850_REG_EVEN): info->fprintf_func (info->stream, "%s", v850_reg_names[value*2]); break; + case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; + case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; + + case V850E_OPERAND_REG_LIST: + { + static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; + int *regs; + int i; + unsigned long int mask = 0; + int pc = 0; + + + switch (operand->shift) + { + case 0xffe00001: regs = list12_regs; break; + default: + /* xgettext:c-format */ + fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift ); + abort (); + } + + for (i = 0; i < 32; i++) + { + if (value & (1 << i)) + { + switch (regs[ i ]) + { + default: mask |= (1 << regs[ i ]); break; + /* xgettext:c-format */ + case 0: fprintf (stderr, _("unknown reg: %d\n"), i ); abort (); + case -1: pc = 1; break; + } + } + } + + info->fprintf_func (info->stream, "{"); + + if (mask || pc) + { + if (mask) + { + unsigned int bit; + int shown_one = 0; + + for (bit = 0; bit < 32; bit++) + if (mask & (1 << bit)) + { + unsigned long int first = bit; + unsigned long int last; + + if (shown_one) + info->fprintf_func (info->stream, ", "); + else + shown_one = 1; + + info->fprintf_func (info->stream, v850_reg_names[first]); + + for (bit++; bit < 32; bit++) + if ((mask & (1 << bit)) == 0) + break; + + last = bit; + + if (last > first + 1) + { + info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); + } + } + } + + if (pc) + info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); + } + + info->fprintf_func (info->stream, "}"); + } + break; + + case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; + case V850_OPERAND_FLOAT_CC: info->fprintf_func (info->stream, "%s", v850_float_cc_names[value]); break; + + default: + print_value (operand->flags, memaddr, info, value); + break; + } + + if (opnum == 2 && opnum == memop) + (*info->fprintf_func) (info->stream, "]"); + } + + /* All done. */ + break; + } + next_opcode: + op++; + } + + return match; +} + +int +print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info) +{ + int status, status2, match; + bfd_byte buffer[8]; + int length = 0, code_length = 0; + unsigned long insn = 0, insn2 = 0; + int target_processor; + + switch (info->mach) + { + case 0: + default: + target_processor = PROCESSOR_V850; + break; + + case bfd_mach_v850e: + target_processor = PROCESSOR_V850E; + break; + + case bfd_mach_v850e1: + target_processor = PROCESSOR_V850E; + break; + + case bfd_mach_v850e2: + target_processor = PROCESSOR_V850E2; + break; + + case bfd_mach_v850e2v3: + target_processor = PROCESSOR_V850E2V3; + break; + } + + status = info->read_memory_func (memaddr, buffer, 2, info); + + if (status) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + + insn = bfd_getl16 (buffer); + + status2 = info->read_memory_func (memaddr+2, buffer, 2 , info); + + if (!status2) + { + insn2 = bfd_getl16 (buffer); + /* fprintf (stderr, "insn2 0x%08lx\n", insn2); */ + } + + /* Special case. */ + if (length == 0 + && (target_processor == PROCESSOR_V850E2 + || target_processor == PROCESSOR_V850E2V3)) + { + if ((insn & 0xffff) == 0x02e0 /* jr 32bit */ + && !status2 && (insn2 & 0x1) == 0) + { + length = 2; + code_length = 6; + } + else if ((insn & 0xffe0) == 0x02e0 /* jarl 32bit */ + && !status2 && (insn2 & 0x1) == 0) + { + length = 2; + code_length = 6; + } + else if ((insn & 0xffe0) == 0x06e0 /* jmp 32bit */ + && !status2 && (insn2 & 0x1) == 0) + { + length = 2; + code_length = 6; + } + } + + if (length == 0 + && target_processor == PROCESSOR_V850E2V3) + { + if (((insn & 0xffe0) == 0x0780 /* ld.b 23bit */ + && !status2 && (insn2 & 0x000f) == 0x0005) + || ((insn & 0xffe0) == 0x07a0 /* ld.bu 23bit */ + && !status2 && (insn2 & 0x000f) == 0x0005) + || ((insn & 0xffe0) == 0x0780 /* ld.h 23bit */ + && !status2 && (insn2 & 0x000f) == 0x0007) + || ((insn & 0xffe0) == 0x07a0 /* ld.hu 23bit */ + && !status2 && (insn2 & 0x000f) == 0x0007) + || ((insn & 0xffe0) == 0x0780 /* ld.w 23bit */ + && !status2 && (insn2 & 0x000f) == 0x0009)) + { + length = 4; + code_length = 6; + } + else if (((insn & 0xffe0) == 0x0780 /* st.b 23bit */ + && !status2 && (insn2 & 0x000f) == 0x000d) + || ((insn & 0xffe0) == 0x07a0 /* st.h 23bit */ + && !status2 && (insn2 & 0x000f) == 0x000d) + || ((insn & 0xffe0) == 0x0780 /* st.w 23bit */ + && !status2 && (insn2 & 0x000f) == 0x000f)) + { + length = 4; + code_length = 6; + } + } + + if (length == 0 + && target_processor != PROCESSOR_V850) + { + if ((insn & 0xffe0) == 0x0620) /* 32 bit MOV */ + { + length = 2; + code_length = 6; + } + else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16<<16 */ + && !status2 && (insn2 & 0x001f) == 0x0013) + { + length = 4; + code_length = 6; + } + else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm16 */ + && !status2 && (insn2 & 0x001f) == 0x000b) + { + length = 4; + code_length = 6; + } + else if ((insn & 0xffc0) == 0x0780 /* prepare {list}, imm5, imm32 */ + && !status2 && (insn2 & 0x001f) == 0x001b) + { + length = 4; + code_length = 8; + } + } + + if (length == 4 + || (length == 0 + && (insn & 0x0600) == 0x0600)) + { + /* This is a 4 byte insn. */ + status = info->read_memory_func (memaddr, buffer, 4, info); + if (!status) + { + insn = bfd_getl32 (buffer); + + if (!length) + length = code_length = 4; + } + } + + if (code_length > length) + { + status = info->read_memory_func (memaddr + length, buffer, code_length - length, info); + if (status) + length = 0; + } + + if (length == 0 && !status) + length = code_length = 2; + + if (length == 2) + insn &= 0xffff; + + match = disassemble (memaddr, info, length, insn); + + if (!match) + { + int l = 0; + + status = info->read_memory_func (memaddr, buffer, code_length, info); + + while (l < code_length) + { + if (code_length - l == 2) + { + insn = bfd_getl16 (buffer + l) & 0xffff; + info->fprintf_func (info->stream, ".short\t0x%04lx", insn); + l += 2; + } + else + { + insn = bfd_getl32 (buffer + l); + info->fprintf_func (info->stream, ".long\t0x%08lx", insn); + l += 4; + } + } + } + + return code_length; +} diff --git a/external/gpl3/gdb/dist/opcodes/v850-opc.c b/external/gpl3/gdb/dist/opcodes/v850-opc.c new file mode 100644 index 000000000000..eea427c881fd --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/v850-opc.c @@ -0,0 +1,1301 @@ +/* Assemble V850 instructions. + Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2010 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#include "opcode/v850.h" +#include "bfd.h" +#include "opintl.h" + + +/* Regular opcodes. */ +#define OP(x) ((x & 0x3f) << 5) +#define OP_MASK OP (0x3f) + +/* Conditional branch opcodes (Format III). */ +#define BOP(x) ((0x58 << 4) | (x & 0x0f)) +#define BOP_MASK ((0x78 << 4) | 0x0f) + +/* Conditional branch opcodes (Format VII). */ +#define BOP7(x) (0x107e0 | (x & 0xf)) +#define BOP7_MASK (0x1ffe0 | 0xf) + +/* One-word opcodes. */ +#define one(x) ((unsigned int) (x)) + +/* Two-word opcodes. */ +#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) + + +/* The functions used to insert and extract complicated operands. */ + +/* Note: There is a conspiracy between these functions and + v850_insert_operand() in gas/config/tc-v850.c. Error messages + containing the string 'out of range' will be ignored unless a + specific command line option is given to GAS. */ + +static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); +static const char * out_of_range = N_ ("displacement value is out of range"); +static const char * not_aligned = N_ ("displacement value is not aligned"); + +static const char * immediate_out_of_range = N_ ("immediate value is out of range"); +static const char * branch_out_of_range = N_ ("branch value out of range"); +static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); +static const char * branch_to_odd_offset = N_ ("branch to odd offset"); + + +int +v850_msg_is_out_of_range (const char* msg) +{ + return msg == out_of_range + || msg == immediate_out_of_range + || msg == branch_out_of_range; +} + +static unsigned long +insert_i5div1 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 30 || value < 2) + { + if (value & 1) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); + + value = (32 - value)/2; + + return (insn | ((value << (2+16)) & 0x3c0000)); +} + +static unsigned long +extract_i5div1 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x003c0000) >> (16+2); + ret = 32 - (ret * 2); + + if (invalid != 0) + *invalid = (ret > 30 || ret < 2) ? 1 : 0; + return ret; +} + +static unsigned long +insert_i5div2 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 30 || value < 4) + { + if (value & 1) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); + + value = (32 - value)/2; + + return (insn | ((value << (2+16)) & 0x3c0000)); +} + +static unsigned long +extract_i5div2 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x003c0000) >> (16+2); + ret = 32 - (ret * 2); + + if (invalid != 0) + *invalid = (ret > 30 || ret < 4) ? 1 : 0; + return ret; +} + +static unsigned long +insert_i5div3 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 32 || value < 2) + { + if (value & 1) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); + + value = (32 - value)/2; + + return (insn | ((value << (2+16)) & 0x3c0000)); +} + +static unsigned long +extract_i5div3 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x003c0000) >> (16+2); + ret = 32 - (ret * 2); + + if (invalid != 0) + *invalid = (ret > 32 || ret < 2) ? 1 : 0; + return ret; +} + +static unsigned long +insert_d5_4 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0x1f || value < 0) + { + if (value & 1) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); + + value >>= 1; + + return insn | (value & 0x0f); +} + +static unsigned long +extract_d5_4 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x0f); + + ret <<= 1; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d8_6 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0xff || value < 0) + { + if ((value % 4) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 4) != 0) + * errmsg = _(not_aligned); + + value >>= 1; + + return insn | (value & 0x7e); +} + +static unsigned long +extract_d8_6 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x7e); + + ret <<= 1; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d8_7 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0xff || value < 0) + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); + + value >>= 1; + + return insn | (value & 0x7f); +} + +static unsigned long +extract_d8_7 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x7f); + + ret <<= 1; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_v8 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0xff || value < 0) + * errmsg = _(immediate_out_of_range); + + return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); +} + +static unsigned long +extract_v8 (unsigned long insn, int * invalid) +{ + unsigned long ret = (insn & 0x1f) | ((insn & 0x38000000) >> (27-5)); + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d9 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0xff || value < -0x100) + { + if ((value % 2) != 0) + * errmsg = branch_out_of_range_and_odd_offset; + else + * errmsg = branch_out_of_range; + } + else if ((value % 2) != 0) + * errmsg = branch_to_odd_offset; + + return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); +} + +static unsigned long +extract_d9 (unsigned long insn, int * invalid) +{ + unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); + + if ((insn & 0x8000) != 0) + ret -= 0x0200; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_u16_loop (unsigned long insn, long value, const char ** errmsg) +{ + if (value < -0xffff || value > 0) + { + if ((value % 2) != 0) + * errmsg = branch_out_of_range_and_odd_offset; + else + * errmsg = branch_out_of_range; + } + else if ((value % 2) != 0) + * errmsg = branch_to_odd_offset; + + return insn | ((-value & 0xfffe) << 16); +} + +static unsigned long +extract_u16_loop (unsigned long insn, int * invalid) +{ + long ret = (insn >> 16) & 0xfffe; + ret = -ret; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d16_15 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0x7fff || value < -0x8000) + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); + + return insn | ((value & 0xfffe) << 16); +} + +static unsigned long +extract_d16_15 (unsigned long insn, int * invalid) +{ + signed long ret = (insn & 0xfffe0000); + ret >>= 16; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) +{ + if (value > 0x7fff || value < -0x8000) + * errmsg = _(out_of_range); + + return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); +} + +static unsigned long +extract_d16_16 (unsigned long insn, int * invalid) +{ + signed long ret = insn & 0xfffe0000; + ret >>= 16; + ret |= ((insn & 0x20) >> 5); + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_d17_16 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0xffff || value < -0x10000) + * errmsg = _(out_of_range); + + return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); +} + +static unsigned long +extract_d17_16 (unsigned long insn, int * invalid) +{ + signed long ret = (insn >> 16) & 0xfffe; + ret |= (insn << (16 - 4)) & 0x10000; + ret = (ret << ((sizeof ret)*8 - 17)) >> ((sizeof ret)*8 - 17); + + if (invalid != 0) + *invalid = 0; + return (unsigned long)ret; +} + +static unsigned long +insert_d22 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0x1fffff || value < -0x200000) + { + if ((value % 2) != 0) + * errmsg = branch_out_of_range_and_odd_offset; + else + * errmsg = branch_out_of_range; + } + else if ((value % 2) != 0) + * errmsg = branch_to_odd_offset; + + return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); +} + +static unsigned long +extract_d22 (unsigned long insn, int * invalid) +{ + signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); + + ret = (ret << ((sizeof ret)*8 - 22)) >> ((sizeof ret)*8 - 22); + + if (invalid != 0) + *invalid = 0; + return (unsigned long) ret; +} + +static unsigned long +insert_d23 (unsigned long insn, long value, const char ** errmsg) +{ + if (value > 0x3fffff || value < -0x400000) + * errmsg = out_of_range; + + return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); +} + +static unsigned long +extract_d23 (unsigned long insn, int * invalid) +{ + signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fffff80); + + ret = ((ret << ((sizeof ret)*8 - 23)) >> ((sizeof ret)*8 - 23)); + + if (invalid != 0) + *invalid = 0; + return (unsigned long) ret; +} + +static unsigned long +insert_i9 (unsigned long insn, signed long value, const char ** errmsg) +{ + if (value > 0xff || value < -0x100) + * errmsg = _(immediate_out_of_range); + + return insn | ((value & 0x1e0) << 13) | (value & 0x1f); +} + +static unsigned long +extract_i9 (unsigned long insn, int * invalid) +{ + signed long ret = insn & 0x003c0000; + + ret <<= 10; + ret >>= 23; + ret |= (insn & 0x1f); + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_u9 (unsigned long insn, long v, const char ** errmsg) +{ + unsigned long value = (unsigned long) v; + + if (value > 0x1ff) + * errmsg = _(immediate_out_of_range); + + return insn | ((value & 0x1e0) << 13) | (value & 0x1f); +} + +static unsigned long +extract_u9 (unsigned long insn, int * invalid) +{ + unsigned long ret = insn & 0x003c0000; + + ret >>= 13; + + ret |= (insn & 0x1f); + + if (invalid != 0) + *invalid = 0; + return ret; +} + +static unsigned long +insert_spe (unsigned long insn, long v, const char ** errmsg) +{ + unsigned long value = (unsigned long) v; + + if (value != 3) + * errmsg = _("invalid register for stack adjustment"); + + return insn & (~ 0x180000); +} + +static unsigned long +extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) +{ + if (invalid != 0) + *invalid = 0; + + return 3; +} + +static unsigned long +insert_r4 (unsigned long insn, long v, const char ** errmsg) +{ + unsigned long value = (unsigned long) v; + + if (value >= 32) + { + * errmsg = _("invalid register name"); + } + + return insn | ((value & 0x10) << (23-4)) | ((value & 0x0f) << (17)); +} + +static unsigned long +extract_r4 (unsigned long insn, int * invalid) +{ + unsigned long ret; + ret = (insn >> 17) & 0xf; + ret |= (insn >> (23-4)) & 0x10; + + if (invalid != 0) + *invalid = 0; + return ret; +} + +/* Warning: code in gas/config/tc-v850.c examines the contents of this array. + If you change any of the values here, be sure to look for side effects in + that code. */ +const struct v850_operand v850_operands[] = +{ +#define UNUSED 0 + { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The R1 field in a format 1, 6, 7, 9, C insn. */ +#define R1 (UNUSED + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, + +/* As above, but register 0 is not allowed. */ +#define R1_NOTR0 (R1 + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, + +/* Even register is allowed. */ +#define R1_EVEN (R1_NOTR0 + 1) + { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, + +/* Bang (bit reverse). */ +#define R1_BANG (R1_EVEN + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, + +/* Percent (modulo). */ +#define R1_PERCENT (R1_BANG + 1) + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, + +/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ +#define R2 (R1_PERCENT + 1) + { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, + +/* As above, but register 0 is not allowed. */ +#define R2_NOTR0 (R2 + 1) + { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, + +/* Even register is allowed. */ +#define R2_EVEN (R2_NOTR0 + 1) + { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, + +/* Reg2 in dispose instruction. */ +#define R2_DISPOSE (R2_EVEN + 1) + { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, + +/* The R3 field in a format 11, 12, C insn. */ +#define R3 (R2_DISPOSE + 1) + { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, + +/* As above, but register 0 is not allowed. */ +#define R3_NOTR0 (R3 + 1) + { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, + +/* As above, but odd number registers are not allowed. */ +#define R3_EVEN (R3_NOTR0 + 1) + { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, + +/* As above, but register 0 is not allowed. */ +#define R3_EVEN_NOTR0 (R3_EVEN + 1) + { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, + +/* Forth register in FPU Instruction. */ +#define R4 (R3_EVEN_NOTR0 + 1) + { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, + +/* As above, but odd number registers are not allowed. */ +#define R4_EVEN (R4 + 1) + { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, + +/* Stack pointer in prepare instruction. */ +#define SP (R4_EVEN + 1) + { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, + +/* EP Register. */ +#define EP (SP + 1) + { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, + +/* A list of registers in a prepare/dispose instruction. */ +#define LIST12 (EP + 1) + { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, + +/* System register operands. */ +#define SR1 (LIST12 + 1) + { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, + +/* The R2 field as a system register. */ +#define SR2 (SR1 + 1) + { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, + +/* FPU CC bit position. */ +#define FFF (SR2 + 1) + { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 4 bit condition code in a setf instruction. */ +#define CCCC (FFF + 1) + { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, + +/* Condition code in adf,sdf. */ +#define CCCC_NOTSA (CCCC + 1) + { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, + +/* Condition code in conditional moves. */ +#define MOVCC (CCCC_NOTSA + 1) + { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, + +/* Condition code in FPU. */ +#define FLOAT_CCCC (MOVCC + 1) + { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, + +/* The 1 bit immediate field in format C insn. */ +#define VI1 (FLOAT_CCCC + 1) + { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 1 bit immediate field in format C insn. */ +#define VC1 (VI1 + 1) + { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 2 bit immediate field in format C insn. */ +#define DI2 (VC1 + 1) + { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 2 bit immediate field in format C insn. */ +#define VI2 (DI2 + 1) + { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 2 bit immediate field in format C - DUP insn. */ +#define VI2DUP (VI2 + 1) + { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 3 bit immediate field in format 8 insn. */ +#define B3 (VI2DUP + 1) + { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 3 bit immediate field in format C insn. */ +#define DI3 (B3 + 1) + { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 3 bit immediate field in format C insn. */ +#define I3U (DI3 + 1) + { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 4 bit immediate field in format C insn. */ +#define I4U (I3U + 1) + { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The 4 bit immediate field in fetrap. */ +#define I4U_NOTIMM0 (I4U + 1) + { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, + +/* The unsigned disp4 field in a sld.bu. */ +#define D4U (I4U_NOTIMM0 + 1) + { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, + +/* The imm5 field in a format 2 insn. */ +#define I5 (D4U + 1) + { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, + +/* The imm5 field in a format 11 insn. */ +#define I5DIV1 (I5 + 1) + { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, + +#define I5DIV2 (I5DIV1 + 1) + { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, + +#define I5DIV3 (I5DIV2 + 1) + { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, + +/* The unsigned imm5 field in a format 2 insn. */ +#define I5U (I5DIV3 + 1) + { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The imm5 field in a prepare/dispose instruction. */ +#define IMM5 (I5U + 1) + { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, + +/* The unsigned disp5 field in a sld.hu. */ +#define D5_4U (IMM5 + 1) + { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, + +/* The IMM6 field in a callt instruction. */ +#define IMM6 (D5_4U + 1) + { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, + +/* The signed disp7 field in a format 4 insn. */ +#define D7U (IMM6 + 1) + { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define D8_7U (D7U + 1) + { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define D8_6U (D8_7U + 1) + { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, + +/* The unsigned DISP8 field in a format 4 insn. */ +#define V8 (D8_6U + 1) + { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, + +/* The imm9 field in a multiply word. */ +#define I9 (V8 + 1) + { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, + +/* The unsigned imm9 field in a multiply word. */ +#define U9 (I9 + 1) + { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, + +/* The DISP9 field in a format 3 insn. */ +#define D9 (U9 + 1) + { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, + +/* The DISP9 field in a format 3 insn, relaxable. */ +#define D9_RELAX (D9 + 1) + { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, + +/* The imm16 field in a format 6 insn. */ +#define I16 (D9_RELAX + 1) + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, + +/* The 16 bit immediate following a 32 bit instruction. */ +#define IMM16 (I16 + 1) + { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_16 }, + +/* The 16 bit immediate following a 32 bit instruction. */ +#define IMM16LO (IMM16 + 1) + { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_LO16 }, + +/* The hi 16 bit immediate following a 32 bit instruction. */ +#define IMM16HI (IMM16LO + 1) + { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, + +/* The unsigned imm16 in a format 6 insn. */ +#define I16U (IMM16HI + 1) + { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, + +/* The disp16 field in a format 8 insn. */ +#define D16 (I16U + 1) + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, + +/* The disp16 field in an format 7 unsigned byte load insn. */ +#define D16_16 (D16 + 1) + { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, + +/* The disp16 field in a format 6 insn. */ +#define D16_15 (D16_16 + 1) + { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, + +/* The unsigned DISP16 field in a format 7 insn. */ +#define D16_LOOP (D16_15 + 1) + { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL }, + +/* The DISP17 field in a format 7 insn. */ +#define D17_16 (D16_LOOP + 1) + { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, + +/* The DISP22 field in a format 4 insn, relaxable. + This _must_ follow D9_RELAX; the assembler assumes that the longer + version immediately follows the shorter version for relaxing. */ +#define D22 (D17_16 + 1) + { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, + +#define D23 (D22 + 1) + { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, + +/* The 32 bit immediate following a 32 bit instruction. */ +#define IMM32 (D23 + 1) + { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, + +#define D32_31 (IMM32 + 1) + { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, + +#define D32_31_PCREL (D32_31 + 1) + { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, + +}; + + +/* Reg - Reg instruction format (Format I). */ +#define IF1 {R1, R2} + +/* Imm - Reg instruction format (Format II). */ +#define IF2 {I5, R2} + +/* Conditional branch instruction format (Format III). */ +#define IF3 {D9_RELAX} + +/* 3 operand instruction (Format VI). */ +#define IF6 {I16, R1, R2} + +/* 3 operand instruction (Format VI). */ +#define IF6U {I16U, R1, R2} + +/* Conditional branch instruction format (Format VII). */ +#define IF7 {D17_16} + + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR + + NAME is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + MEMOP specifies which operand (if any) is a memory operand. + PROCESSORS specifies which CPU(s) support the opcode. + + The disassembler reads the table in order and prints the first + instruction which matches, so this table is sorted to put more + specific instructions before more general instructions. It is also + sorted by major opcode. + + The table is also sorted by name. This is used by the assembler. + When parsing an instruction the assembler finds the first occurance + of the name of the instruciton in this table and then attempts to + match the instruction's arguments with description of the operands + associated with the entry it has just found in this table. If the + match fails the assembler looks at the next entry in this table. + If that entry has the same name as the previous entry, then it + tries to match the instruction against that entry and so on. This + is how the assembler copes with multiple, different formats of the + same instruction. */ + +const struct v850_opcode v850_opcodes[] = +{ +/* Standard instructions. */ +{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, + +{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, + +{ "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, + + /* Signed integer. */ +{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Unsigned integer. */ +{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Common. */ +{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Others. */ +{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + +{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, + +{ "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_ALL }, + +{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, +{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, + +{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, +{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, + +{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, + +{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, + +{ "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, + +{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, + +{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, +{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, + +{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, + +{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, +{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, + +{ "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, + +{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, + +{ "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_ALL }, + +{ "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_ALL }, + +{ "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_ALL }, + +{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, + +{ "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, +{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL }, +/* Gas local alias of mov imm22(not defined in spec). */ +{ "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, +/* Gas local alias of mov imm32(not defined in spec). */ +{ "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, +{ "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL }, +{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, +/* Gas local alias of jmp disp22(not defined in spec). */ +{ "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, +/* Gas local alias of jmp disp32(not defined in spec). */ +{ "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, +{ "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, +{ "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_ALL }, +/* Gas local alias of mov imm22(not defined in spec). */ +{ "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, +/* Gas local alias of mov imm32(not defined in spec). */ +{ "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +/* Alias of bcond (same as CA850). */ +{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Unsigned integer. */ +{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Common. */ +{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + /* Others. */ +{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, +{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, + + +{ "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, + +{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, +{ "ld.b", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, +{ "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, +{ "ld.bu", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, +{ "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, +{ "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, +{ "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, +{ "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, +{ "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + + +{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, +{ "ld.w", two (0x0780, 0x0009), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL }, +{ "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, + +{ "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, + +{ "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_ALL }, + +{ "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_ALL }, + +{ "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, + +{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, +/* Gas local alias of mov imm32(not defined in spec). */ +{ "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, + +{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, +{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, + +{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, + +{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, +{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, + +{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, + +{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, +{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, + +{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, + +{ "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, +{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, + +{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, + +{ "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, +{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, +{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, +{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, + +{ "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_ALL }, + +{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, +{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, +{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, +{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, + +{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, +{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, + +{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, + +{ "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, +{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, + +{ "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_ALL }, +{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, +{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, + +{ "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, + +{ "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, + +{ "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, + +{ "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, + +{ "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, + +{ "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, + +{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, + +{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, + +{ "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, +{ "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_EXTENSION }, + +{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, +{ "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, +{ "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, +{ "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, +{ "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, +{ "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL }, +{ "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_ALL | PROCESSOR_OPTION_ALIAS }, + +{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, + +{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, + +{ "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, + +{ "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, + +{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, + +{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, +{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, + +{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, + +{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, + +{ "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, + +{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, + +/* Floating point operation. */ +{ "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3 }, +/* Default value for FFF is 0(not defined in spec). */ +{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3 }, +{ "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3 }, +/* Default value for FFF is 0(not defined in spec). */ +{ "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3 }, +{ "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R1_EVEN, R2_EVEN, FFF}, 0, PROCESSOR_V850E2V3 }, +{ "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R1_EVEN, R2_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R1, R2, FFF}, 0, PROCESSOR_V850E2V3 }, +{ "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R1, R2}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 }, +{ "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, + +{ "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, +{ "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_EXTENSION }, + +{ "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3 }, +{ "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, +{ "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3 }, + + /* Special instruction (from gdb) mov 1, r0. */ +{ "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, + + /* V850e2-v3. */ +{ "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, +{ "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, +{ "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, +{ "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3 }, + /* Alias of syncp. */ +{ "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 | PROCESSOR_OPTION_ALIAS }, +{ "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, + + +{ "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3 }, +{ "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {0}, 0, PROCESSOR_V850E2V3 }, + +{ 0, 0, 0, {0}, 0, 0 }, +} ; + +const int v850_num_opcodes = + sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); diff --git a/external/gpl3/gdb/dist/opcodes/vax-dis.c b/external/gpl3/gdb/dist/opcodes/vax-dis.c new file mode 100644 index 000000000000..a119f0540f5d --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/vax-dis.c @@ -0,0 +1,487 @@ +/* Print VAX instructions. + Copyright 1995, 1998, 2000, 2001, 2002, 2005, 2007, 2009 + Free Software Foundation, Inc. + Contributed by Pauline Middelink + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include "sysdep.h" +#include "opcode/vax.h" +#include "dis-asm.h" + +static char *reg_names[] = +{ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "ap", "fp", "sp", "pc" +}; + +/* Definitions for the function entry mask bits. */ +static char *entry_mask_bit[] = +{ + /* Registers 0 and 1 shall not be saved, since they're used to pass back + a function's result to its caller... */ + "~r0~", "~r1~", + /* Registers 2 .. 11 are normal registers. */ + "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", + /* Registers 12 and 13 are argument and frame pointer and must not + be saved by using the entry mask. */ + "~ap~", "~fp~", + /* Bits 14 and 15 control integer and decimal overflow. */ + "IntOvfl", "DecOvfl", +}; + +/* Sign-extend an (unsigned char). */ +#define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) + +/* Get a 1 byte signed integer. */ +#define NEXTBYTE(p) \ + (p += 1, FETCH_DATA (info, p), \ + COERCE_SIGNED_CHAR(p[-1])) + +/* Get a 2 byte signed integer. */ +#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) +#define NEXTWORD(p) \ + (p += 2, FETCH_DATA (info, p), \ + COERCE16 ((p[-1] << 8) + p[-2])) + +/* Get a 4 byte signed integer. */ +#define COERCE32(x) ((int) (((x) ^ 0x80000000) - 0x80000000)) +#define NEXTLONG(p) \ + (p += 4, FETCH_DATA (info, p), \ + (COERCE32 ((((((p[-1] << 8) + p[-2]) << 8) + p[-3]) << 8) + p[-4]))) + +/* Maximum length of an instruction. */ +#define MAXLEN 25 + +struct private +{ + /* Points to first byte not fetched. */ + bfd_byte * max_fetched; + bfd_byte the_buffer[MAXLEN]; + bfd_vma insn_start; + jmp_buf bailout; +}; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, addr) \ + ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (addr))) + +static int +fetch_data (struct disassemble_info *info, bfd_byte *addr) +{ + int status; + struct private *priv = (struct private *) info->private_data; + bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); + + status = (*info->read_memory_func) (start, + priv->max_fetched, + addr - priv->max_fetched, + info); + if (status != 0) + { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } + else + priv->max_fetched = addr; + + return 1; +} + +/* Entry mask handling. */ +static unsigned int entry_addr_occupied_slots = 0; +static unsigned int entry_addr_total_slots = 0; +static bfd_vma * entry_addr = NULL; + +/* Parse the VAX specific disassembler options. These contain function + entry addresses, which can be useful to disassemble ROM images, since + there's no symbol table. Returns TRUE upon success, FALSE otherwise. */ + +static bfd_boolean +parse_disassembler_options (char * options) +{ + const char * entry_switch = "entry:"; + + while ((options = strstr (options, entry_switch))) + { + options += strlen (entry_switch); + + /* The greater-than part of the test below is paranoia. */ + if (entry_addr_occupied_slots >= entry_addr_total_slots) + { + /* A guesstimate of the number of entries we will have to create. */ + entry_addr_total_slots += + strlen (options) / (strlen (entry_switch) + 5); + + entry_addr = realloc (entry_addr, sizeof (bfd_vma) + * entry_addr_total_slots); + } + + if (entry_addr == NULL) + return FALSE; + + entry_addr[entry_addr_occupied_slots] = bfd_scan_vma (options, NULL, 0); + entry_addr_occupied_slots ++; + } + + return TRUE; +} + +#if 0 /* FIXME: Ideally the disassembler should have target specific + initialisation and termination function pointers. Then + parse_disassembler_options could be the init function and + free_entry_array (below) could be the termination routine. + Until then there is no way for the disassembler to tell us + that it has finished and that we no longer need the entry + array, so this routine is suppressed for now. It does mean + that we leak memory, but only to the extent that we do not + free it just before the disassembler is about to terminate + anyway. */ + +/* Free memory allocated to our entry array. */ + +static void +free_entry_array (void) +{ + if (entry_addr) + { + free (entry_addr); + entry_addr = NULL; + entry_addr_occupied_slots = entry_addr_total_slots = 0; + } +} +#endif +/* Check if the given address is a known function entry point. This is + the case if there is a symbol of the function type at this address. + We also check for synthetic symbols as these are used for PLT entries + (weak undefined symbols may not have the function type set). Finally + the address may have been forced to be treated as an entry point. The + latter helps in disassembling ROM images, because there's no symbol + table at all. Forced entry points can be given by supplying several + -M options to objdump: -M entry:0xffbb7730. */ + +static bfd_boolean +is_function_entry (struct disassemble_info *info, bfd_vma addr) +{ + unsigned int i; + + /* Check if there's a function or PLT symbol at our address. */ + if (info->symbols + && info->symbols[0] + && (info->symbols[0]->flags & (BSF_FUNCTION | BSF_SYNTHETIC)) + && addr == bfd_asymbol_value (info->symbols[0])) + return TRUE; + + /* Check for forced function entry address. */ + for (i = entry_addr_occupied_slots; i--;) + if (entry_addr[i] == addr) + return TRUE; + + return FALSE; +} + +/* Check if the given address is the last longword of a PLT entry. + This longword is data and depending on the value it may interfere + with disassembly of further PLT entries. We make use of the fact + PLT symbols are marked BSF_SYNTHETIC. */ +static bfd_boolean +is_plt_tail (struct disassemble_info *info, bfd_vma addr) +{ + if (info->symbols + && info->symbols[0] + && (info->symbols[0]->flags & BSF_SYNTHETIC) + && addr == bfd_asymbol_value (info->symbols[0]) + 8) + return TRUE; + + return FALSE; +} + +static int +print_insn_mode (const char *d, + int size, + unsigned char *p0, + bfd_vma addr, /* PC for this arg to be relative to. */ + disassemble_info *info) +{ + unsigned char *p = p0; + unsigned char mode, reg; + + /* Fetch and interpret mode byte. */ + mode = (unsigned char) NEXTBYTE (p); + reg = mode & 0xF; + switch (mode & 0xF0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: /* Literal mode $number. */ + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + (*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]); + else + (*info->fprintf_func) (info->stream, "$0x%x", mode); + break; + case 0x40: /* Index: base-addr[Rn] */ + p += print_insn_mode (d, size, p0 + 1, addr + 1, info); + (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]); + break; + case 0x50: /* Register: Rn */ + (*info->fprintf_func) (info->stream, "%s", reg_names[reg]); + break; + case 0x60: /* Register deferred: (Rn) */ + (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]); + break; + case 0x70: /* Autodecrement: -(Rn) */ + (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]); + break; + case 0x80: /* Autoincrement: (Rn)+ */ + if (reg == 0xF) + { /* Immediate? */ + int i; + + FETCH_DATA (info, p + size); + (*info->fprintf_func) (info->stream, "$0x"); + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + { + int float_word; + + float_word = p[0] | (p[1] << 8); + if ((d[1] == 'd' || d[1] == 'f') + && (float_word & 0xff80) == 0x8000) + { + (*info->fprintf_func) (info->stream, "[invalid %c-float]", + d[1]); + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", + p[size - i - 1]); + (*info->fprintf_func) (info->stream, " [%c-float]", d[1]); + } + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]); + } + p += size; + } + else + (*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]); + break; + case 0x90: /* Autoincrement deferred: @(Rn)+ */ + if (reg == 0xF) + (*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p)); + else + (*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]); + break; + case 0xB0: /* Displacement byte deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xA0: /* Displacement byte: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 2 + NEXTBYTE (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p), + reg_names[reg]); + break; + case 0xD0: /* Displacement word deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xC0: /* Displacement word: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 3 + NEXTWORD (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p), + reg_names[reg]); + break; + case 0xF0: /* Displacement long deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xE0: /* Displacement long: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 5 + NEXTLONG (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p), + reg_names[reg]); + break; + } + + return p - p0; +} + +/* Returns number of bytes "eaten" by the operand, or return -1 if an + invalid operand was found, or -2 if an opcode tabel error was + found. */ + +static int +print_insn_arg (const char *d, + unsigned char *p0, + bfd_vma addr, /* PC for this arg to be relative to. */ + disassemble_info *info) +{ + int arg_len; + + /* Check validity of addressing length. */ + switch (d[1]) + { + case 'b' : arg_len = 1; break; + case 'd' : arg_len = 8; break; + case 'f' : arg_len = 4; break; + case 'g' : arg_len = 8; break; + case 'h' : arg_len = 16; break; + case 'l' : arg_len = 4; break; + case 'o' : arg_len = 16; break; + case 'w' : arg_len = 2; break; + case 'q' : arg_len = 8; break; + default : abort (); + } + + /* Branches have no mode byte. */ + if (d[0] == 'b') + { + unsigned char *p = p0; + + if (arg_len == 1) + (*info->print_address_func) (addr + 1 + NEXTBYTE (p), info); + else + (*info->print_address_func) (addr + 2 + NEXTWORD (p), info); + + return p - p0; + } + + return print_insn_mode (d, arg_len, p0, addr, info); +} + +/* Print the vax instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_vax (bfd_vma memaddr, disassemble_info *info) +{ + static bfd_boolean parsed_disassembler_options = FALSE; + const struct vot *votp; + const char *argp; + unsigned char *arg; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + + info->private_data = & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + + if (! parsed_disassembler_options + && info->disassembler_options != NULL) + { + parse_disassembler_options (info->disassembler_options); + + /* To avoid repeated parsing of these options. */ + parsed_disassembler_options = TRUE; + } + + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + argp = NULL; + /* Check if the info buffer has more than one byte left since + the last opcode might be a single byte with no argument data. */ + if (info->buffer_length - (memaddr - info->buffer_vma) > 1) + { + FETCH_DATA (info, buffer + 2); + } + else + { + FETCH_DATA (info, buffer + 1); + buffer[1] = 0; + } + + /* Decode function entry mask. */ + if (is_function_entry (info, memaddr)) + { + int i = 0; + int register_mask = buffer[1] << 8 | buffer[0]; + + (*info->fprintf_func) (info->stream, ".word 0x%04x # Entry mask: <", + register_mask); + + for (i = 15; i >= 0; i--) + if (register_mask & (1 << i)) + (*info->fprintf_func) (info->stream, " %s", entry_mask_bit[i]); + + (*info->fprintf_func) (info->stream, " >"); + + return 2; + } + + /* Decode PLT entry offset longword. */ + if (is_plt_tail (info, memaddr)) + { + int offset; + + FETCH_DATA (info, buffer + 4); + offset = buffer[3] << 24 | buffer[2] << 16 | buffer[1] << 8 | buffer[0]; + (*info->fprintf_func) (info->stream, ".long 0x%08x", offset); + + return 4; + } + + for (votp = &votstrs[0]; votp->name[0]; votp++) + { + vax_opcodeT opcode = votp->detail.code; + + /* 2 byte codes match 2 buffer pos. */ + if ((bfd_byte) opcode == buffer[0] + && (opcode >> 8 == 0 || opcode >> 8 == buffer[1])) + { + argp = votp->detail.args; + break; + } + } + if (argp == NULL) + { + /* Handle undefined instructions. */ + (*info->fprintf_func) (info->stream, ".word 0x%x", + (buffer[0] << 8) + buffer[1]); + return 2; + } + + /* Point at first byte of argument data, and at descriptor for first + argument. */ + arg = buffer + ((votp->detail.code >> 8) ? 2 : 1); + + /* Make sure we have it in mem */ + FETCH_DATA (info, arg); + + (*info->fprintf_func) (info->stream, "%s", votp->name); + if (*argp) + (*info->fprintf_func) (info->stream, " "); + + while (*argp) + { + arg += print_insn_arg (argp, arg, memaddr + arg - buffer, info); + argp += 2; + if (*argp) + (*info->fprintf_func) (info->stream, ","); + } + + return arg - buffer; +} + diff --git a/external/gpl3/gdb/dist/opcodes/w65-dis.c b/external/gpl3/gdb/dist/opcodes/w65-dis.c new file mode 100644 index 000000000000..60d9b0459593 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/w65-dis.c @@ -0,0 +1,98 @@ +/* Disassemble WDC 65816 instructions. + Copyright 1995, 1998, 2000, 2001, 2002, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "sysdep.h" +#define STATIC_TABLE +#define DEFINE_TABLE + +#include "w65-opc.h" +#include "dis-asm.h" + +static fprintf_ftype fpr; +static void *stream; +static struct disassemble_info *local_info; + +static void +print_operand (int lookup, char *format, int *args) +{ + int val; + int c; + + while (*format) + { + switch (c = *format++) + { + case '$': + val = args[(*format++) - '0']; + if (lookup) + local_info->print_address_func (val, local_info); + else + fpr (stream, "0x%x", val); + + break; + default: + fpr (stream, "%c", c); + break; + } + } +} + +int +print_insn_w65 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status = 0; + unsigned char insn[4]; + const struct opinfo *op; + int i; + int X = 0; + int M = 0; + int args[2]; + + stream = info->stream; + fpr = info->fprintf_func; + local_info = info; + + for (i = 0; i < 4 && status == 0; i++) + status = info->read_memory_func (memaddr + i, insn + i, 1, info); + + for (op = optable; op->val != insn[0]; op++) + ; + + fpr (stream, "%s", op->name); + + /* Prepare all the posible operand values. */ + { + int size = 1; + int asR_W65_ABS8 = insn[1]; + int asR_W65_ABS16 = (insn[2] << 8) + asR_W65_ABS8; + int asR_W65_ABS24 = (insn[3] << 16) + asR_W65_ABS16; + int asR_W65_PCR8 = ((char) (asR_W65_ABS8)) + memaddr + 2; + int asR_W65_PCR16 = ((short) (asR_W65_ABS16)) + memaddr + 3; + + switch (op->amode) + { + DISASM (); + } + + return size; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/w65-opc.h b/external/gpl3/gdb/dist/opcodes/w65-opc.h new file mode 100644 index 000000000000..ddef8a6e4426 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/w65-opc.h @@ -0,0 +1,568 @@ +/* Instruction opcode header for WDC 65816 + (generated by the program sim/w65/gencode -a) + + Copyright 2001, 2002, 2005, 2007 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define ADDR_IMMTOA 1 /* #a */ +#define ADDR_IMMCOP 2 /* #c */ +#define ADDR_IMMTOI 3 /* #i */ +#define ADDR_ACC 4 /* A */ +#define ADDR_PC_REL 5 /* r */ +#define ADDR_PC_REL_LONG 6 /* rl */ +#define ADDR_IMPLIED 7 /* i */ +#define ADDR_STACK 8 /* s */ +#define ADDR_DIR 9 /* d */ +#define ADDR_DIR_IDX_X 10 /* d,x */ +#define ADDR_DIR_IDX_Y 11 /* d,y */ +#define ADDR_DIR_IND 12 /* (d) */ +#define ADDR_DIR_IDX_IND_X 13 /* (d,x) */ +#define ADDR_DIR_IND_IDX_Y 14 /* (d),y */ +#define ADDR_DIR_IND_LONG 15 /* [d] */ +#define ADDR_DIR_IND_IDX_Y_LONG 16 /* [d],y */ +#define ADDR_ABS 17 /* a */ +#define ADDR_ABS_IDX_X 18 /* a,x */ +#define ADDR_ABS_IDX_Y 19 /* a,y */ +#define ADDR_ABS_LONG 20 /* al */ +#define ADDR_ABS_IND_LONG 21 /* [a] */ +#define ADDR_ABS_LONG_IDX_X 22 /* al,x */ +#define ADDR_STACK_REL 23 /* d,s */ +#define ADDR_STACK_REL_INDX_IDX 24 /* (d,s),y */ +#define ADDR_ABS_IND 25 /* (a) */ +#define ADDR_ABS_IND_IDX 26 /* (a,x) */ +#define ADDR_BLOCK_MOVE 27 /* xyz */ +struct opinfo { + int val; + int code; + char *name; + int amode; +}; +const struct opinfo optable[257]={ +#define O_adc 1 +#define O_and 2 +#define O_asl 3 +#define O_bcc 4 +#define O_bcs 5 +#define O_beq 6 +#define O_bit 7 +#define O_bmi 8 +#define O_bne 9 +#define O_bpl 10 +#define O_bra 11 +#define O_brk 12 +#define O_brl 13 +#define O_bvc 14 +#define O_bvs 15 +#define O_clc 16 +#define O_cld 17 +#define O_cli 18 +#define O_clv 19 +#define O_cmp 20 +#define O_cop 21 +#define O_cpx 22 +#define O_cpy 23 +#define O_dec 24 +#define O_dex 25 +#define O_dey 26 +#define O_eor 27 +#define O_inc 28 +#define O_inx 29 +#define O_iny 30 +#define O_jmp 31 +#define O_jsr 32 +#define O_lda 33 +#define O_ldx 34 +#define O_ldy 35 +#define O_lsr 36 +#define O_mvn 37 +#define O_mvp 38 +#define O_nop 39 +#define O_ora 40 +#define O_pea 41 +#define O_pei 42 +#define O_per 43 +#define O_pha 44 +#define O_phb 45 +#define O_phd 46 +#define O_phk 47 +#define O_php 48 +#define O_phx 49 +#define O_phy 50 +#define O_pla 51 +#define O_plb 52 +#define O_pld 53 +#define O_plp 54 +#define O_plx 55 +#define O_ply 56 +#define O_rep 57 +#define O_rol 58 +#define O_ror 59 +#define O_rti 60 +#define O_rtl 61 +#define O_rts 62 +#define O_sbc 63 +#define O_sec 64 +#define O_sed 65 +#define O_sei 66 +#define O_sep 67 +#define O_sta 68 +#define O_stp 69 +#define O_stx 70 +#define O_sty 71 +#define O_stz 72 +#define O_tax 73 +#define O_tay 74 +#define O_tcd 75 +#define O_tcs 76 +#define O_tdc 77 +#define O_trb 78 +#define O_tsb 79 +#define O_tsc 80 +#define O_tsx 81 +#define O_txa 82 +#define O_txs 83 +#define O_txy 84 +#define O_tya 85 +#define O_tyx 86 +#define O_wai 87 +#define O_wdm 88 +#define O_xba 89 +#define O_xce 90 +#ifdef DEFINE_TABLE + {0x69, O_adc, "adc", ADDR_IMMTOA}, + {0x72, O_adc, "adc", ADDR_DIR_IND}, + {0x71, O_adc, "adc", ADDR_DIR_IND_IDX_Y}, + {0x73, O_adc, "adc", ADDR_STACK_REL_INDX_IDX}, + {0x61, O_adc, "adc", ADDR_DIR_IDX_IND_X}, + {0x67, O_adc, "adc", ADDR_DIR_IND_LONG}, + {0x77, O_adc, "adc", ADDR_DIR_IND_IDX_Y_LONG}, + {0x6D, O_adc, "adc", ADDR_ABS}, + {0x7D, O_adc, "adc", ADDR_ABS_IDX_X}, + {0x79, O_adc, "adc", ADDR_ABS_IDX_Y}, + {0x6F, O_adc, "adc", ADDR_ABS_LONG}, + {0x7F, O_adc, "adc", ADDR_ABS_LONG_IDX_X}, + {0x65, O_adc, "adc", ADDR_DIR}, + {0x63, O_adc, "adc", ADDR_STACK_REL}, + {0x75, O_adc, "adc", ADDR_DIR_IDX_X}, + {0x29, O_and, "and", ADDR_IMMTOA}, + {0x32, O_and, "and", ADDR_DIR_IND}, + {0x31, O_and, "and", ADDR_DIR_IND_IDX_Y}, + {0x33, O_and, "and", ADDR_STACK_REL_INDX_IDX}, + {0x21, O_and, "and", ADDR_DIR_IDX_IND_X}, + {0x27, O_and, "and", ADDR_DIR_IND_LONG}, + {0x37, O_and, "and", ADDR_DIR_IND_IDX_Y_LONG}, + {0x2D, O_and, "and", ADDR_ABS}, + {0x3D, O_and, "and", ADDR_ABS_IDX_X}, + {0x39, O_and, "and", ADDR_ABS_IDX_Y}, + {0x2F, O_and, "and", ADDR_ABS_LONG}, + {0x3F, O_and, "and", ADDR_ABS_LONG_IDX_X}, + {0x25, O_and, "and", ADDR_DIR}, + {0x23, O_and, "and", ADDR_STACK_REL}, + {0x35, O_and, "and", ADDR_DIR_IDX_X}, + {0x0A, O_asl, "asl", ADDR_ACC}, + {0x0E, O_asl, "asl", ADDR_ABS}, + {0x1E, O_asl, "asl", ADDR_ABS_IDX_X}, + {0x06, O_asl, "asl", ADDR_DIR}, + {0x16, O_asl, "asl", ADDR_DIR_IDX_X}, + {0x90, O_bcc, "bcc", ADDR_PC_REL}, + {0xB0, O_bcs, "bcs", ADDR_PC_REL}, + {0xF0, O_beq, "beq", ADDR_PC_REL}, + {0x89, O_bit, "bit", ADDR_IMMTOA}, + {0x24, O_bit, "bit", ADDR_DIR_IND}, + {0x34, O_bit, "bit", ADDR_DIR_IDX_IND_X}, + {0x2C, O_bit, "bit", ADDR_ABS}, + {0x3C, O_bit, "bit", ADDR_ABS_IDX_X}, + {0x30, O_bmi, "bmi", ADDR_PC_REL}, + {0xD0, O_bne, "bne", ADDR_PC_REL}, + {0x10, O_bpl, "bpl", ADDR_PC_REL}, + {0x80, O_bra, "bra", ADDR_PC_REL}, + {0x00, O_brk, "brk", ADDR_STACK}, + {0x82, O_brl, "brl", ADDR_PC_REL_LONG}, + {0x50, O_bvc, "bvc", ADDR_PC_REL}, + {0x70, O_bvs, "bvs", ADDR_PC_REL}, + {0x18, O_clc, "clc", ADDR_IMPLIED}, + {0xD8, O_cld, "cld", ADDR_IMPLIED}, + {0x58, O_cli, "cli", ADDR_IMPLIED}, + {0xB8, O_clv, "clv", ADDR_IMPLIED}, + {0xC9, O_cmp, "cmp", ADDR_IMMTOA}, + {0xD2, O_cmp, "cmp", ADDR_DIR_IND}, + {0xD1, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y}, + {0xD3, O_cmp, "cmp", ADDR_STACK_REL_INDX_IDX}, + {0xC1, O_cmp, "cmp", ADDR_DIR_IDX_IND_X}, + {0xC7, O_cmp, "cmp", ADDR_DIR_IND_LONG}, + {0xD7, O_cmp, "cmp", ADDR_DIR_IND_IDX_Y_LONG}, + {0xCD, O_cmp, "cmp", ADDR_ABS}, + {0xDD, O_cmp, "cmp", ADDR_ABS_IDX_X}, + {0xD9, O_cmp, "cmp", ADDR_ABS_IDX_Y}, + {0xCF, O_cmp, "cmp", ADDR_ABS_LONG}, + {0xDF, O_cmp, "cmp", ADDR_ABS_LONG_IDX_X}, + {0xC5, O_cmp, "cmp", ADDR_DIR}, + {0xC3, O_cmp, "cmp", ADDR_STACK_REL}, + {0xD5, O_cmp, "cmp", ADDR_DIR_IDX_X}, + {0x02, O_cop, "cop", ADDR_IMMCOP}, + {0xE0, O_cpx, "cpx", ADDR_IMMTOI}, + {0xEC, O_cpx, "cpx", ADDR_ABS}, + {0xE4, O_cpx, "cpx", ADDR_DIR}, + {0xC0, O_cpy, "cpy", ADDR_IMMTOI}, + {0xCC, O_cpy, "cpy", ADDR_ABS}, + {0xC4, O_cpy, "cpy", ADDR_DIR}, + {0x3A, O_dec, "dec", ADDR_ACC}, + {0xCE, O_dec, "dec", ADDR_ABS}, + {0xDE, O_dec, "dec", ADDR_ABS_IDX_X}, + {0xC6, O_dec, "dec", ADDR_DIR}, + {0xD6, O_dec, "dec", ADDR_DIR_IDX_X}, + {0xCA, O_dex, "dex", ADDR_IMPLIED}, + {0x88, O_dey, "dey", ADDR_IMPLIED}, + {0x49, O_eor, "eor", ADDR_IMMTOA}, + {0x52, O_eor, "eor", ADDR_DIR_IND}, + {0x51, O_eor, "eor", ADDR_DIR_IND_IDX_Y}, + {0x53, O_eor, "eor", ADDR_STACK_REL_INDX_IDX}, + {0x41, O_eor, "eor", ADDR_DIR_IDX_IND_X}, + {0x47, O_eor, "eor", ADDR_DIR_IND_LONG}, + {0x57, O_eor, "eor", ADDR_DIR_IND_IDX_Y_LONG}, + {0x4D, O_eor, "eor", ADDR_ABS}, + {0x5D, O_eor, "eor", ADDR_ABS_IDX_X}, + {0x59, O_eor, "eor", ADDR_ABS_IDX_Y}, + {0x4F, O_eor, "eor", ADDR_ABS_LONG}, + {0x5F, O_eor, "eor", ADDR_ABS_LONG_IDX_X}, + {0x45, O_eor, "eor", ADDR_DIR}, + {0x43, O_eor, "eor", ADDR_STACK_REL}, + {0x55, O_eor, "eor", ADDR_DIR_IDX_X}, + {0x1A, O_inc, "inc", ADDR_ACC}, + {0xEE, O_inc, "inc", ADDR_ABS}, + {0xFE, O_inc, "inc", ADDR_ABS_IDX_X}, + {0xE6, O_inc, "inc", ADDR_DIR}, + {0xF6, O_inc, "inc", ADDR_DIR_IDX_X}, + {0xE8, O_inx, "inx", ADDR_IMPLIED}, + {0xC8, O_iny, "iny", ADDR_IMPLIED}, + {0x6C, O_jmp, "jmp", ADDR_ABS_IND}, + {0x7C, O_jmp, "jmp", ADDR_ABS_IND_IDX}, + {0xDC, O_jmp, "jmp", ADDR_ABS_IND_LONG}, + {0x4C, O_jmp, "jmp", ADDR_ABS}, + {0x5C, O_jmp, "jmp", ADDR_ABS_LONG}, + {0xFC, O_jsr, "jsr", ADDR_ABS_IND_IDX}, + {0x20, O_jsr, "jsr", ADDR_ABS}, + {0x22, O_jsr, "jsr", ADDR_ABS_LONG}, + {0xA9, O_lda, "lda", ADDR_IMMTOA}, + {0xB2, O_lda, "lda", ADDR_DIR_IND}, + {0xB1, O_lda, "lda", ADDR_DIR_IND_IDX_Y}, + {0xB3, O_lda, "lda", ADDR_STACK_REL_INDX_IDX}, + {0xA1, O_lda, "lda", ADDR_DIR_IDX_IND_X}, + {0xA7, O_lda, "lda", ADDR_DIR_IND_LONG}, + {0xB7, O_lda, "lda", ADDR_DIR_IND_IDX_Y_LONG}, + {0xAD, O_lda, "lda", ADDR_ABS}, + {0xBD, O_lda, "lda", ADDR_ABS_IDX_X}, + {0xB9, O_lda, "lda", ADDR_ABS_IDX_Y}, + {0xAF, O_lda, "lda", ADDR_ABS_LONG}, + {0xBF, O_lda, "lda", ADDR_ABS_LONG_IDX_X}, + {0xA5, O_lda, "lda", ADDR_DIR}, + {0xA3, O_lda, "lda", ADDR_STACK_REL}, + {0xB5, O_lda, "lda", ADDR_DIR_IDX_X}, + {0xA2, O_ldx, "ldx", ADDR_IMMTOI}, + {0xAE, O_ldx, "ldx", ADDR_ABS}, + {0xBE, O_ldx, "ldx", ADDR_ABS_IDX_Y}, + {0xA6, O_ldx, "ldx", ADDR_DIR}, + {0xB6, O_ldx, "ldx", ADDR_DIR_IDX_Y}, + {0xA0, O_ldy, "ldy", ADDR_IMMTOI}, + {0xAC, O_ldy, "ldy", ADDR_ABS}, + {0xBC, O_ldy, "ldy", ADDR_ABS_IDX_X}, + {0xA4, O_ldy, "ldy", ADDR_DIR}, + {0xB4, O_ldy, "ldy", ADDR_DIR_IDX_X}, + {0x4A, O_lsr, "lsr", ADDR_ACC}, + {0x4E, O_lsr, "lsr", ADDR_ABS}, + {0x5E, O_lsr, "lsr", ADDR_ABS_IDX_X}, + {0x46, O_lsr, "lsr", ADDR_DIR}, + {0x56, O_lsr, "lsr", ADDR_DIR_IDX_X}, + {0x54, O_mvn, "mvn", ADDR_BLOCK_MOVE}, + {0x44, O_mvp, "mvp", ADDR_BLOCK_MOVE}, + {0xEA, O_nop, "nop", ADDR_IMPLIED}, + {0x09, O_ora, "ora", ADDR_IMMTOA}, + {0x12, O_ora, "ora", ADDR_DIR_IND}, + {0x11, O_ora, "ora", ADDR_DIR_IND_IDX_Y}, + {0x13, O_ora, "ora", ADDR_STACK_REL_INDX_IDX}, + {0x01, O_ora, "ora", ADDR_DIR_IDX_IND_X}, + {0x07, O_ora, "ora", ADDR_DIR_IND_LONG}, + {0x17, O_ora, "ora", ADDR_DIR_IND_IDX_Y_LONG}, + {0x0D, O_ora, "ora", ADDR_ABS}, + {0x1D, O_ora, "ora", ADDR_ABS_IDX_X}, + {0x19, O_ora, "ora", ADDR_ABS_IDX_Y}, + {0x0F, O_ora, "ora", ADDR_ABS_LONG}, + {0x1F, O_ora, "ora", ADDR_ABS_LONG_IDX_X}, + {0x05, O_ora, "ora", ADDR_DIR}, + {0x03, O_ora, "ora", ADDR_STACK_REL}, + {0x15, O_ora, "ora", ADDR_DIR_IDX_X}, + {0xF4, O_pea, "pea", ADDR_ABS}, + {0xD4, O_pei, "pei", ADDR_DIR}, + {0x62, O_per, "per", ADDR_PC_REL_LONG}, + {0x48, O_pha, "pha", ADDR_STACK}, + {0x8B, O_phb, "phb", ADDR_STACK}, + {0x0B, O_phd, "phd", ADDR_STACK}, + {0x4B, O_phk, "phk", ADDR_STACK}, + {0x08, O_php, "php", ADDR_STACK}, + {0xDA, O_phx, "phx", ADDR_STACK}, + {0x5A, O_phy, "phy", ADDR_STACK}, + {0x68, O_pla, "pla", ADDR_STACK}, + {0xAB, O_plb, "plb", ADDR_STACK}, + {0x2B, O_pld, "pld", ADDR_STACK}, + {0x28, O_plp, "plp", ADDR_STACK}, + {0xFA, O_plx, "plx", ADDR_STACK}, + {0x7A, O_ply, "ply", ADDR_STACK}, + {0xC2, O_rep, "rep", ADDR_IMMCOP}, + {0x2A, O_rol, "rol", ADDR_ACC}, + {0x2E, O_rol, "rol", ADDR_ABS}, + {0x3E, O_rol, "rol", ADDR_ABS_IDX_X}, + {0x26, O_rol, "rol", ADDR_DIR}, + {0x36, O_rol, "rol", ADDR_DIR_IDX_X}, + {0x6A, O_ror, "ror", ADDR_ACC}, + {0x6E, O_ror, "ror", ADDR_ABS}, + {0x7E, O_ror, "ror", ADDR_ABS_IDX_X}, + {0x66, O_ror, "ror", ADDR_DIR}, + {0x76, O_ror, "ror", ADDR_DIR_IDX_X}, + {0x40, O_rti, "rti", ADDR_STACK}, + {0x6B, O_rtl, "rtl", ADDR_STACK}, + {0x60, O_rts, "rts", ADDR_STACK}, + {0xE9, O_sbc, "sbc", ADDR_IMMTOA}, + {0xF2, O_sbc, "sbc", ADDR_DIR_IND}, + {0xF1, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y}, + {0xF3, O_sbc, "sbc", ADDR_STACK_REL_INDX_IDX}, + {0xE1, O_sbc, "sbc", ADDR_DIR_IDX_IND_X}, + {0xE7, O_sbc, "sbc", ADDR_DIR_IND_LONG}, + {0xF7, O_sbc, "sbc", ADDR_DIR_IND_IDX_Y_LONG}, + {0xED, O_sbc, "sbc", ADDR_ABS}, + {0xFD, O_sbc, "sbc", ADDR_ABS_IDX_X}, + {0xF9, O_sbc, "sbc", ADDR_ABS_IDX_Y}, + {0xEF, O_sbc, "sbc", ADDR_ABS_LONG}, + {0xFF, O_sbc, "sbc", ADDR_ABS_LONG_IDX_X}, + {0xE5, O_sbc, "sbc", ADDR_DIR}, + {0xE3, O_sbc, "sbc", ADDR_STACK_REL}, + {0xF5, O_sbc, "sbc", ADDR_DIR_IDX_X}, + {0x38, O_sec, "sec", ADDR_IMPLIED}, + {0xF8, O_sed, "sed", ADDR_IMPLIED}, + {0x78, O_sei, "sei", ADDR_IMPLIED}, + {0xE2, O_sep, "sep", ADDR_IMMCOP}, + {0x92, O_sta, "sta", ADDR_DIR_IND}, + {0x91, O_sta, "sta", ADDR_DIR_IND_IDX_Y}, + {0x93, O_sta, "sta", ADDR_STACK_REL_INDX_IDX}, + {0x81, O_sta, "sta", ADDR_DIR_IDX_IND_X}, + {0x87, O_sta, "sta", ADDR_DIR_IND_LONG}, + {0x97, O_sta, "sta", ADDR_DIR_IND_IDX_Y_LONG}, + {0x8D, O_sta, "sta", ADDR_ABS}, + {0x9D, O_sta, "sta", ADDR_ABS_IDX_X}, + {0x99, O_sta, "sta", ADDR_ABS_IDX_Y}, + {0x8F, O_sta, "sta", ADDR_ABS_LONG}, + {0x9F, O_sta, "sta", ADDR_ABS_LONG_IDX_X}, + {0x85, O_sta, "sta", ADDR_DIR}, + {0x83, O_sta, "sta", ADDR_STACK_REL}, + {0x95, O_sta, "sta", ADDR_DIR_IDX_X}, + {0xDB, O_stp, "stp", ADDR_IMPLIED}, + {0x8E, O_stx, "stx", ADDR_ABS}, + {0x86, O_stx, "stx", ADDR_DIR}, + {0x96, O_stx, "stx", ADDR_DIR_IDX_X}, + {0x8C, O_sty, "sty", ADDR_ABS}, + {0x84, O_sty, "sty", ADDR_DIR}, + {0x94, O_sty, "sty", ADDR_DIR_IDX_X}, + {0x9C, O_stz, "stz", ADDR_ABS}, + {0x9E, O_stz, "stz", ADDR_ABS_IDX_X}, + {0x64, O_stz, "stz", ADDR_DIR}, + {0x74, O_stz, "stz", ADDR_DIR_IDX_X}, + {0xAA, O_tax, "tax", ADDR_IMPLIED}, + {0xA8, O_tay, "tay", ADDR_IMPLIED}, + {0x5B, O_tcd, "tcd", ADDR_IMPLIED}, + {0x1B, O_tcs, "tcs", ADDR_IMPLIED}, + {0x7B, O_tdc, "tdc", ADDR_IMPLIED}, + {0x1C, O_trb, "trb", ADDR_ABS}, + {0x14, O_trb, "trb", ADDR_DIR}, + {0x0C, O_tsb, "tsb", ADDR_ABS}, + {0x04, O_tsb, "tsb", ADDR_DIR}, + {0x3B, O_tsc, "tsc", ADDR_IMPLIED}, + {0xBA, O_tsx, "tsx", ADDR_IMPLIED}, + {0x8A, O_txa, "txa", ADDR_IMPLIED}, + {0x9A, O_txs, "txs", ADDR_IMPLIED}, + {0x9B, O_txy, "txy", ADDR_IMPLIED}, + {0x98, O_tya, "tya", ADDR_IMPLIED}, + {0xBB, O_tyx, "tyx", ADDR_IMPLIED}, + {0xCB, O_wai, "wai", ADDR_IMPLIED}, + {0x42, O_wdm, "wdm", ADDR_IMPLIED}, + {0xEB, O_xba, "xba", ADDR_IMPLIED}, + {0xFB, O_xce, "xce", ADDR_IMPLIED}, + { 0, 0, NULL, 0 } +}; +#endif +#define DISASM()\ + case ADDR_IMMTOA:\ + args[0] = M==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += M==0 ? 2:1;\ + break;\ + case ADDR_IMMCOP:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += 1;\ + break;\ + case ADDR_IMMTOI:\ + args[0] = X==0 ? asR_W65_ABS16 : asR_W65_ABS8;\ + print_operand (0, " #$0", args);\ + size += X==0 ? 2:1;\ + break;\ + case ADDR_ACC:\ + print_operand (0, " a", 0);\ + size += 0;\ + break;\ + case ADDR_PC_REL:\ + args[0] = asR_W65_PCR8;\ + print_operand (0, " $0", args);\ + size += 1;\ + break;\ + case ADDR_PC_REL_LONG:\ + args[0] = asR_W65_PCR16;\ + print_operand (0, " $0", args);\ + size += 2;\ + break;\ + case ADDR_IMPLIED:\ + size += 0;\ + break;\ + case ADDR_STACK:\ + size += 0;\ + break;\ + case ADDR_DIR:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_X:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0,x", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_Y:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " <$0,y", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0)", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IDX_IND_X:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0,x)", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_IDX_Y:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " (<$0),y", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_LONG:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " [$0]", args);\ + size += 1;\ + break;\ + case ADDR_DIR_IND_IDX_Y_LONG:\ + args[0] = asR_W65_ABS8;\ + print_operand (1, " [$0],y", args);\ + size += 1;\ + break;\ + case ADDR_ABS:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IDX_X:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0,x", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IDX_Y:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " !$0,y", args);\ + size += 2;\ + break;\ + case ADDR_ABS_LONG:\ + args[0] = asR_W65_ABS24;\ + print_operand (1, " >$0", args);\ + size += 3;\ + break;\ + case ADDR_ABS_IND_LONG:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " [>$0]", args);\ + size += 2;\ + break;\ + case ADDR_ABS_LONG_IDX_X:\ + args[0] = asR_W65_ABS24;\ + print_operand (1, " >$0,x", args);\ + size += 3;\ + break;\ + case ADDR_STACK_REL:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " $0,s", args);\ + size += 1;\ + break;\ + case ADDR_STACK_REL_INDX_IDX:\ + args[0] = asR_W65_ABS8;\ + print_operand (0, " ($0,s),y", args);\ + size += 1;\ + break;\ + case ADDR_ABS_IND:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " ($0)", args);\ + size += 2;\ + break;\ + case ADDR_ABS_IND_IDX:\ + args[0] = asR_W65_ABS16;\ + print_operand (1, " ($0,x)", args);\ + size += 2;\ + break;\ + case ADDR_BLOCK_MOVE:\ + args[0] = (asR_W65_ABS16 >>8) &0xff;\ + args[1] = ( asR_W65_ABS16 & 0xff);\ + print_operand (0," $0,$1",args);\ + size += 2;\ + break;\ + +#define GETINFO(size,type,pcrel)\ + case ADDR_IMMTOA: size = M==0 ? 2:1;type=M==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ + case ADDR_IMMCOP: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_IMMTOI: size = X==0 ? 2:1;type=X==0 ? R_W65_ABS16 : R_W65_ABS8;pcrel=0;break;\ + case ADDR_ACC: size = 0;type=-1;pcrel=0;break;\ + case ADDR_PC_REL: size = 1;type=R_W65_PCR8;pcrel=0;break;\ + case ADDR_PC_REL_LONG: size = 2;type=R_W65_PCR16;pcrel=0;break;\ + case ADDR_IMPLIED: size = 0;type=-1;pcrel=0;break;\ + case ADDR_STACK: size = 0;type=-1;pcrel=0;break;\ + case ADDR_DIR: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IDX_IND_X: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_IDX_Y: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_DIR_IND_IDX_Y_LONG: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_ABS: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IDX_X: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IDX_Y: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_LONG: size = 3;type=R_W65_ABS24;pcrel=0;break;\ + case ADDR_ABS_IND_LONG: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_LONG_IDX_X: size = 3;type=R_W65_ABS24;pcrel=0;break;\ + case ADDR_STACK_REL: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_STACK_REL_INDX_IDX: size = 1;type=R_W65_ABS8;pcrel=0;break;\ + case ADDR_ABS_IND: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_ABS_IND_IDX: size = 2;type=R_W65_ABS16;pcrel=0;break;\ + case ADDR_BLOCK_MOVE: size = 2;type=-1;pcrel=0;break;\ + diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-asm.c b/external/gpl3/gdb/dist/opcodes/xc16x-asm.c new file mode 100644 index 000000000000..c7903e1f707a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-asm.c @@ -0,0 +1,784 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xc16x-desc.h" +#include "xc16x-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +/* Handle '#' prefixes (i.e. skip over them). */ + +static const char * +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '#') + { + ++*strp; + return NULL; + } + return _("Missing '#' prefix"); +} + +/* Handle '.' prefixes (i.e. skip over them). */ + +static const char * +parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '.') + { + ++*strp; + return NULL; + } + return _("Missing '.' prefix"); +} + +/* Handle 'pof:' prefixes (i.e. skip over them). */ + +static const char * +parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (strncasecmp (*strp, "pof:", 4) == 0) + { + *strp += 4; + return NULL; + } + return _("Missing 'pof:' prefix"); +} + +/* Handle 'pag:' prefixes (i.e. skip over them). */ + +static const char * +parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (strncasecmp (*strp, "pag:", 4) == 0) + { + *strp += 4; + return NULL; + } + return _("Missing 'pag:' prefix"); +} + +/* Handle 'sof' prefixes (i.e. skip over them). */ + +static const char * +parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (strncasecmp (*strp, "sof:", 4) == 0) + { + *strp += 4; + return NULL; + } + return _("Missing 'sof:' prefix"); +} + +/* Handle 'seg' prefixes (i.e. skip over them). */ + +static const char * +parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (strncasecmp (*strp, "seg:", 4) == 0) + { + *strp += 4; + return NULL; + } + return _("Missing 'seg:' prefix"); +} +/* -- */ + +const char * xc16x_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +xc16x_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_psw_names, & fields->f_reg8); + break; + case XC16X_OPERAND_BIT01 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT01, (unsigned long *) (& fields->f_op_1bit)); + break; + case XC16X_OPERAND_BIT1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT1, (unsigned long *) (& fields->f_op_bit1)); + break; + case XC16X_OPERAND_BIT2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT2, (unsigned long *) (& fields->f_op_bit2)); + break; + case XC16X_OPERAND_BIT4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT4, (unsigned long *) (& fields->f_op_bit4)); + break; + case XC16X_OPERAND_BIT8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT8, (unsigned long *) (& fields->f_op_bit8)); + break; + case XC16X_OPERAND_BITONE : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BITONE, (unsigned long *) (& fields->f_op_onebit)); + break; + case XC16X_OPERAND_CADDR : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_CADDR, 0, NULL, & value); + fields->f_offset16 = value; + } + break; + case XC16X_OPERAND_COND : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_condcode); + break; + case XC16X_OPERAND_DATA8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATA8, (unsigned long *) (& fields->f_data8)); + break; + case XC16X_OPERAND_DATAHI8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATAHI8, (unsigned long *) (& fields->f_datahi8)); + break; + case XC16X_OPERAND_DOT : + errmsg = parse_dot (cd, strp, XC16X_OPERAND_DOT, (long *) (& junk)); + break; + case XC16X_OPERAND_DR : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1); + break; + case XC16X_OPERAND_DRB : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r1); + break; + case XC16X_OPERAND_DRI : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r4); + break; + case XC16X_OPERAND_EXTCOND : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_extconditioncode_names, & fields->f_extccode); + break; + case XC16X_OPERAND_GENREG : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regb8); + break; + case XC16X_OPERAND_HASH : + errmsg = parse_hash (cd, strp, XC16X_OPERAND_HASH, (long *) (& junk)); + break; + case XC16X_OPERAND_ICOND : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_icondcode); + break; + case XC16X_OPERAND_LBIT2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT2, (unsigned long *) (& fields->f_op_lbit2)); + break; + case XC16X_OPERAND_LBIT4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT4, (unsigned long *) (& fields->f_op_lbit4)); + break; + case XC16X_OPERAND_MASK8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASK8, (unsigned long *) (& fields->f_mask8)); + break; + case XC16X_OPERAND_MASKLO8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASKLO8, (unsigned long *) (& fields->f_datahi8)); + break; + case XC16X_OPERAND_MEMGR8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_memgr8_names, & fields->f_memgr8); + break; + case XC16X_OPERAND_MEMORY : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_MEMORY, 0, NULL, & value); + fields->f_memory = value; + } + break; + case XC16X_OPERAND_PAG : + errmsg = parse_pag (cd, strp, XC16X_OPERAND_PAG, (long *) (& junk)); + break; + case XC16X_OPERAND_PAGENUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_PAGENUM, (unsigned long *) (& fields->f_pagenum)); + break; + case XC16X_OPERAND_POF : + errmsg = parse_pof (cd, strp, XC16X_OPERAND_POF, (long *) (& junk)); + break; + case XC16X_OPERAND_QBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QBIT, (unsigned long *) (& fields->f_qbit)); + break; + case XC16X_OPERAND_QHIBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QHIBIT, (unsigned long *) (& fields->f_qhibit)); + break; + case XC16X_OPERAND_QLOBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QLOBIT, (unsigned long *) (& fields->f_qlobit)); + break; + case XC16X_OPERAND_REG8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reg8); + break; + case XC16X_OPERAND_REGB8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb8_names, & fields->f_regb8); + break; + case XC16X_OPERAND_REGBMEM8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regbmem8_names, & fields->f_regmem8); + break; + case XC16X_OPERAND_REGHI8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reghi8); + break; + case XC16X_OPERAND_REGMEM8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regmem8_names, & fields->f_regmem8); + break; + case XC16X_OPERAND_REGOFF8 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regoff8); + break; + case XC16X_OPERAND_REL : + errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_REL, (long *) (& fields->f_rel8)); + break; + case XC16X_OPERAND_RELHI : + errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_RELHI, (long *) (& fields->f_relhi8)); + break; + case XC16X_OPERAND_SEG : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEG, (unsigned long *) (& fields->f_seg8)); + break; + case XC16X_OPERAND_SEGHI8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEGHI8, (unsigned long *) (& fields->f_segnum8)); + break; + case XC16X_OPERAND_SEGM : + errmsg = parse_seg (cd, strp, XC16X_OPERAND_SEGM, (long *) (& junk)); + break; + case XC16X_OPERAND_SOF : + errmsg = parse_sof (cd, strp, XC16X_OPERAND_SOF, (long *) (& junk)); + break; + case XC16X_OPERAND_SR : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2); + break; + case XC16X_OPERAND_SR2 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r0); + break; + case XC16X_OPERAND_SRB : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r2); + break; + case XC16X_OPERAND_SRC1 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1); + break; + case XC16X_OPERAND_SRC2 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2); + break; + case XC16X_OPERAND_SRDIV : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regdiv8_names, & fields->f_reg8); + break; + case XC16X_OPERAND_U4 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name, & fields->f_uimm4); + break; + case XC16X_OPERAND_UIMM16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16)); + break; + case XC16X_OPERAND_UIMM2 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_ext_names, & fields->f_uimm2); + break; + case XC16X_OPERAND_UIMM3 : + errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name1, & fields->f_uimm3); + break; + case XC16X_OPERAND_UIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM4, (unsigned long *) (& fields->f_uimm4)); + break; + case XC16X_OPERAND_UIMM7 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM7, (unsigned long *) (& fields->f_uimm7)); + break; + case XC16X_OPERAND_UIMM8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM8, (unsigned long *) (& fields->f_uimm8)); + break; + case XC16X_OPERAND_UPAG16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UPAG16, (unsigned long *) (& fields->f_uimm16)); + break; + case XC16X_OPERAND_UPOF16 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_UPOF16, 0, NULL, & value); + fields->f_memory = value; + } + break; + case XC16X_OPERAND_USEG16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG16, (unsigned long *) (& fields->f_offset16)); + break; + case XC16X_OPERAND_USEG8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG8, (unsigned long *) (& fields->f_seg8)); + break; + case XC16X_OPERAND_USOF16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USOF16, (unsigned long *) (& fields->f_offset16)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const xc16x_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +xc16x_cgen_init_asm (CGEN_CPU_DESC cd) +{ + xc16x_cgen_init_opcode_table (cd); + xc16x_cgen_init_ibld_table (cd); + cd->parse_handlers = & xc16x_cgen_parse_handlers[0]; + cd->parse_operand = xc16x_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by xc16x_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +xc16x_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! xc16x_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-desc.c b/external/gpl3/gdb/dist/opcodes/xc16x-desc.c new file mode 100644 index 000000000000..422a08a76099 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-desc.c @@ -0,0 +1,3511 @@ +/* CPU data for xc16x. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xc16x-desc.h" +#include "xc16x-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "xc16x", MACH_XC16X }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "xc16x", ISA_XC16X }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", PIPE_NONE }, + { "OS", PIPE_OS }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] }, + { "POF-PREFIX", &bool_attr[0], &bool_attr[0] }, + { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] }, + { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] }, + { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA xc16x_cgen_isa_table[] = { + { "xc16x", 16, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH xc16x_cgen_mach_table[] = { + { "xc16x", "xc16x", MACH_XC16X, 32 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_gr_names = +{ + & xc16x_cgen_opval_gr_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] = +{ + { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_ext_names = +{ + & xc16x_cgen_opval_ext_names_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] = +{ + { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_psw_names = +{ + & xc16x_cgen_opval_psw_names_entries[0], + 17, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] = +{ + { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_grb_names = +{ + & xc16x_cgen_opval_grb_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] = +{ + { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names = +{ + & xc16x_cgen_opval_conditioncode_names_entries[0], + 20, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] = +{ + { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names = +{ + & xc16x_cgen_opval_extconditioncode_names_entries[0], + 24, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] = +{ + { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, + { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, + { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, + { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, + { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, + { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_grb8_names = +{ + & xc16x_cgen_opval_grb8_names_entries[0], + 36, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] = +{ + { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, + { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, + { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, + { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, + { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_r8_names = +{ + & xc16x_cgen_opval_r8_names_entries[0], + 36, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] = +{ + { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, + { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, + { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, + { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, + { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_regmem8_names = +{ + & xc16x_cgen_opval_regmem8_names_entries[0], + 36, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 85, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 102, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 119, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 153, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 170, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 187, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 204, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 221, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 238, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names = +{ + & xc16x_cgen_opval_regdiv8_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] = +{ + { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_reg0_name = +{ + & xc16x_cgen_opval_reg0_name_entries[0], + 30, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] = +{ + { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "7", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 = +{ + & xc16x_cgen_opval_reg0_name1_entries[0], + 14, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] = +{ + { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, + { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, + { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, + { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, + { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, + { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names = +{ + & xc16x_cgen_opval_regbmem8_names_entries[0], + 36, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] = +{ + { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 }, + { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 }, + { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 }, + { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 }, + { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 }, + { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 }, + { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 }, + { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 }, + { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 }, + { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 }, + { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 }, + { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 }, + { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 }, + { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xc16x_cgen_opval_memgr8_names = +{ + & xc16x_cgen_opval_memgr8_names_entries[0], + 20, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY xc16x_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & xc16x_cgen_ifld_table[0]; +} + +/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of xc16x_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of xc16x_cgen_cpu_open to rebuild the tables. */ + +static void +xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & xc16x_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & xc16x_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = xc16x_cgen_rebuild_tables; + xc16x_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +xc16x_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-desc.h b/external/gpl3/gdb/dist/opcodes/xc16x-desc.h new file mode 100644 index 000000000000..2f7c378dc29a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-desc.h @@ -0,0 +1,447 @@ +/* CPU data header for xc16x. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef XC16X_CPU_H +#define XC16X_CPU_H + +#define CGEN_ARCH xc16x + +/* Given symbol S, return xc16x_cgen_. */ +#define CGEN_SYM(s) xc16x##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_XC16XBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 + +/* Enums. */ + +/* Enum declaration for insn format enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_10, OP1_11 + , OP1_12, OP1_13, OP1_14, OP1_15 +} INSN_OP1; + +/* Enum declaration for op2 enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_10, OP2_11 + , OP2_12, OP2_13, OP2_14, OP2_15 +} INSN_OP2; + +/* Enum declaration for bit set/clear enums. */ +typedef enum insn_qcond { + QBIT_0, QBIT_1, QBIT_2, QBIT_3 + , QBIT_4, QBIT_5, QBIT_6, QBIT_7 + , QBIT_8, QBIT_9, QBIT_10, QBIT_11 + , QBIT_12, QBIT_13, QBIT_14, QBIT_15 +} INSN_QCOND; + +/* Enum declaration for relative jump condition code op2 enums. */ +typedef enum insn_rcond { + COND_UC = 0, COND_NET = 1, COND_Z = 2, COND_NE_NZ = 3 + , COND_V = 4, COND_NV = 5, COND_N = 6, COND_NN = 7 + , COND_C = 8, COND_NC = 9, COND_SGT = 10, COND_SLE = 11 + , COND_SLT = 12, COND_SGE = 13, COND_UGT = 14, COND_ULE = 15 + , COND_EQ = 2, COND_NE = 3, COND_ULT = 8, COND_UGE = 9 +} INSN_RCOND; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3 + , H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7 + , H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11 + , H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum ext_names { + H_EXT_0X1 = 0, H_EXT_0X2 = 1, H_EXT_0X3 = 2, H_EXT_0X4 = 3 + , H_EXT_1 = 0, H_EXT_2 = 1, H_EXT_3 = 2, H_EXT_4 = 3 +} EXT_NAMES; + +/* Enum declaration for . */ +typedef enum psw_names { + H_PSW_IEN = 136, H_PSW_R0_11 = 240, H_PSW_R1_11 = 241, H_PSW_R2_11 = 242 + , H_PSW_R3_11 = 243, H_PSW_R4_11 = 244, H_PSW_R5_11 = 245, H_PSW_R6_11 = 246 + , H_PSW_R7_11 = 247, H_PSW_R8_11 = 248, H_PSW_R9_11 = 249, H_PSW_R10_11 = 250 + , H_PSW_R11_11 = 251, H_PSW_R12_11 = 252, H_PSW_R13_11 = 253, H_PSW_R14_11 = 254 + , H_PSW_R15_11 = 255 +} PSW_NAMES; + +/* Enum declaration for . */ +typedef enum grb_names { + H_GRB_RL0, H_GRB_RH0, H_GRB_RL1, H_GRB_RH1 + , H_GRB_RL2, H_GRB_RH2, H_GRB_RL3, H_GRB_RH3 + , H_GRB_RL4, H_GRB_RH4, H_GRB_RL5, H_GRB_RH5 + , H_GRB_RL6, H_GRB_RH6, H_GRB_RL7, H_GRB_RH7 +} GRB_NAMES; + +/* Enum declaration for . */ +typedef enum conditioncode_names { + H_CC_CC_UC = 0, H_CC_CC_NET = 1, H_CC_CC_Z = 2, H_CC_CC_EQ = 2 + , H_CC_CC_NZ = 3, H_CC_CC_NE = 3, H_CC_CC_V = 4, H_CC_CC_NV = 5 + , H_CC_CC_N = 6, H_CC_CC_NN = 7, H_CC_CC_ULT = 8, H_CC_CC_UGE = 9 + , H_CC_CC_C = 8, H_CC_CC_NC = 9, H_CC_CC_SGT = 10, H_CC_CC_SLE = 11 + , H_CC_CC_SLT = 12, H_CC_CC_SGE = 13, H_CC_CC_UGT = 14, H_CC_CC_ULE = 15 +} CONDITIONCODE_NAMES; + +/* Enum declaration for . */ +typedef enum extconditioncode_names { + H_ECC_CC_UC = 0, H_ECC_CC_NET = 2, H_ECC_CC_Z = 4, H_ECC_CC_EQ = 4 + , H_ECC_CC_NZ = 6, H_ECC_CC_NE = 6, H_ECC_CC_V = 8, H_ECC_CC_NV = 10 + , H_ECC_CC_N = 12, H_ECC_CC_NN = 14, H_ECC_CC_ULT = 16, H_ECC_CC_UGE = 18 + , H_ECC_CC_C = 16, H_ECC_CC_NC = 18, H_ECC_CC_SGT = 20, H_ECC_CC_SLE = 22 + , H_ECC_CC_SLT = 24, H_ECC_CC_SGE = 26, H_ECC_CC_UGT = 28, H_ECC_CC_ULE = 30 + , H_ECC_CC_NUSR0 = 1, H_ECC_CC_NUSR1 = 3, H_ECC_CC_USR0 = 5, H_ECC_CC_USR1 = 7 +} EXTCONDITIONCODE_NAMES; + +/* Enum declaration for . */ +typedef enum grb8_names { + H_GRB8_DPP0 = 0, H_GRB8_DPP1 = 1, H_GRB8_DPP2 = 2, H_GRB8_DPP3 = 3 + , H_GRB8_PSW = 136, H_GRB8_CP = 8, H_GRB8_MDL = 7, H_GRB8_MDH = 6 + , H_GRB8_MDC = 135, H_GRB8_SP = 9, H_GRB8_CSP = 4, H_GRB8_VECSEG = 137 + , H_GRB8_STKOV = 10, H_GRB8_STKUN = 11, H_GRB8_CPUCON1 = 12, H_GRB8_CPUCON2 = 13 + , H_GRB8_ZEROS = 142, H_GRB8_ONES = 143, H_GRB8_SPSEG = 134, H_GRB8_TFR = 214 + , H_GRB8_RL0 = 240, H_GRB8_RH0 = 241, H_GRB8_RL1 = 242, H_GRB8_RH1 = 243 + , H_GRB8_RL2 = 244, H_GRB8_RH2 = 245, H_GRB8_RL3 = 246, H_GRB8_RH3 = 247 + , H_GRB8_RL4 = 248, H_GRB8_RH4 = 249, H_GRB8_RL5 = 250, H_GRB8_RH5 = 251 + , H_GRB8_RL6 = 252, H_GRB8_RH6 = 253, H_GRB8_RL7 = 254, H_GRB8_RH7 = 255 +} GRB8_NAMES; + +/* Enum declaration for . */ +typedef enum r8_names { + H_R8_DPP0 = 0, H_R8_DPP1 = 1, H_R8_DPP2 = 2, H_R8_DPP3 = 3 + , H_R8_PSW = 136, H_R8_CP = 8, H_R8_MDL = 7, H_R8_MDH = 6 + , H_R8_MDC = 135, H_R8_SP = 9, H_R8_CSP = 4, H_R8_VECSEG = 137 + , H_R8_STKOV = 10, H_R8_STKUN = 11, H_R8_CPUCON1 = 12, H_R8_CPUCON2 = 13 + , H_R8_ZEROS = 142, H_R8_ONES = 143, H_R8_SPSEG = 134, H_R8_TFR = 214 + , H_R8_R0 = 240, H_R8_R1 = 241, H_R8_R2 = 242, H_R8_R3 = 243 + , H_R8_R4 = 244, H_R8_R5 = 245, H_R8_R6 = 246, H_R8_R7 = 247 + , H_R8_R8 = 248, H_R8_R9 = 249, H_R8_R10 = 250, H_R8_R11 = 251 + , H_R8_R12 = 252, H_R8_R13 = 253, H_R8_R14 = 254, H_R8_R15 = 255 +} R8_NAMES; + +/* Enum declaration for . */ +typedef enum regmem8_names { + H_REGMEM8_DPP0 = 0, H_REGMEM8_DPP1 = 1, H_REGMEM8_DPP2 = 2, H_REGMEM8_DPP3 = 3 + , H_REGMEM8_PSW = 136, H_REGMEM8_CP = 8, H_REGMEM8_MDL = 7, H_REGMEM8_MDH = 6 + , H_REGMEM8_MDC = 135, H_REGMEM8_SP = 9, H_REGMEM8_CSP = 4, H_REGMEM8_VECSEG = 137 + , H_REGMEM8_STKOV = 10, H_REGMEM8_STKUN = 11, H_REGMEM8_CPUCON1 = 12, H_REGMEM8_CPUCON2 = 13 + , H_REGMEM8_ZEROS = 142, H_REGMEM8_ONES = 143, H_REGMEM8_SPSEG = 134, H_REGMEM8_TFR = 214 + , H_REGMEM8_R0 = 240, H_REGMEM8_R1 = 241, H_REGMEM8_R2 = 242, H_REGMEM8_R3 = 243 + , H_REGMEM8_R4 = 244, H_REGMEM8_R5 = 245, H_REGMEM8_R6 = 246, H_REGMEM8_R7 = 247 + , H_REGMEM8_R8 = 248, H_REGMEM8_R9 = 249, H_REGMEM8_R10 = 250, H_REGMEM8_R11 = 251 + , H_REGMEM8_R12 = 252, H_REGMEM8_R13 = 253, H_REGMEM8_R14 = 254, H_REGMEM8_R15 = 255 +} REGMEM8_NAMES; + +/* Enum declaration for . */ +typedef enum regdiv8_names { + H_REGDIV8_R0 = 0, H_REGDIV8_R1 = 17, H_REGDIV8_R2 = 34, H_REGDIV8_R3 = 51 + , H_REGDIV8_R4 = 68, H_REGDIV8_R5 = 85, H_REGDIV8_R6 = 102, H_REGDIV8_R7 = 119 + , H_REGDIV8_R8 = 136, H_REGDIV8_R9 = 153, H_REGDIV8_R10 = 170, H_REGDIV8_R11 = 187 + , H_REGDIV8_R12 = 204, H_REGDIV8_R13 = 221, H_REGDIV8_R14 = 238, H_REGDIV8_R15 = 255 +} REGDIV8_NAMES; + +/* Enum declaration for . */ +typedef enum reg0_name { + H_REG0_0X1 = 1, H_REG0_0X2 = 2, H_REG0_0X3 = 3, H_REG0_0X4 = 4 + , H_REG0_0X5 = 5, H_REG0_0X6 = 6, H_REG0_0X7 = 7, H_REG0_0X8 = 8 + , H_REG0_0X9 = 9, H_REG0_0XA = 10, H_REG0_0XB = 11, H_REG0_0XC = 12 + , H_REG0_0XD = 13, H_REG0_0XE = 14, H_REG0_0XF = 15, H_REG0_1 = 1 + , H_REG0_2 = 2, H_REG0_3 = 3, H_REG0_4 = 4, H_REG0_5 = 5 + , H_REG0_6 = 6, H_REG0_7 = 7, H_REG0_8 = 8, H_REG0_9 = 9 + , H_REG0_10 = 10, H_REG0_11 = 11, H_REG0_12 = 12, H_REG0_13 = 13 + , H_REG0_14 = 14, H_REG0_15 = 15 +} REG0_NAME; + +/* Enum declaration for . */ +typedef enum reg0_name1 { + H_REG01_0X1 = 1, H_REG01_0X2 = 2, H_REG01_0X3 = 3, H_REG01_0X4 = 4 + , H_REG01_0X5 = 5, H_REG01_0X6 = 6, H_REG01_0X7 = 7, H_REG01_1 = 1 + , H_REG01_2 = 2, H_REG01_3 = 3, H_REG01_4 = 4, H_REG01_5 = 5 + , H_REG01_6 = 6, H_REG01_7 = 7 +} REG0_NAME1; + +/* Enum declaration for . */ +typedef enum regbmem8_names { + H_REGBMEM8_DPP0 = 0, H_REGBMEM8_DPP1 = 1, H_REGBMEM8_DPP2 = 2, H_REGBMEM8_DPP3 = 3 + , H_REGBMEM8_PSW = 136, H_REGBMEM8_CP = 8, H_REGBMEM8_MDL = 7, H_REGBMEM8_MDH = 6 + , H_REGBMEM8_MDC = 135, H_REGBMEM8_SP = 9, H_REGBMEM8_CSP = 4, H_REGBMEM8_VECSEG = 137 + , H_REGBMEM8_STKOV = 10, H_REGBMEM8_STKUN = 11, H_REGBMEM8_CPUCON1 = 12, H_REGBMEM8_CPUCON2 = 13 + , H_REGBMEM8_ZEROS = 142, H_REGBMEM8_ONES = 143, H_REGBMEM8_SPSEG = 134, H_REGBMEM8_TFR = 214 + , H_REGBMEM8_RL0 = 240, H_REGBMEM8_RH0 = 241, H_REGBMEM8_RL1 = 242, H_REGBMEM8_RH1 = 243 + , H_REGBMEM8_RL2 = 244, H_REGBMEM8_RH2 = 245, H_REGBMEM8_RL3 = 246, H_REGBMEM8_RH3 = 247 + , H_REGBMEM8_RL4 = 248, H_REGBMEM8_RH4 = 249, H_REGBMEM8_RL5 = 250, H_REGBMEM8_RH5 = 251 + , H_REGBMEM8_RL6 = 252, H_REGBMEM8_RH6 = 253, H_REGBMEM8_RL7 = 254, H_REGBMEM8_RH7 = 255 +} REGBMEM8_NAMES; + +/* Enum declaration for . */ +typedef enum memgr8_names { + H_MEMGR8_DPP0 = 65024, H_MEMGR8_DPP1 = 65026, H_MEMGR8_DPP2 = 65028, H_MEMGR8_DPP3 = 65030 + , H_MEMGR8_PSW = 65296, H_MEMGR8_CP = 65040, H_MEMGR8_MDL = 65038, H_MEMGR8_MDH = 65036 + , H_MEMGR8_MDC = 65294, H_MEMGR8_SP = 65042, H_MEMGR8_CSP = 65032, H_MEMGR8_VECSEG = 65298 + , H_MEMGR8_STKOV = 65044, H_MEMGR8_STKUN = 65046, H_MEMGR8_CPUCON1 = 65048, H_MEMGR8_CPUCON2 = 65050 + , H_MEMGR8_ZEROS = 65308, H_MEMGR8_ONES = 65310, H_MEMGR8_SPSEG = 65292, H_MEMGR8_TFR = 65452 +} MEMGR8_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_XC16X, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_XC16X, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum pipe_attr { + PIPE_NONE, PIPE_OS +} PIPE_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS + , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) + +/* Enum declaration for xc16x ifield types. */ +typedef enum ifield_type { + XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2 + , XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND + , XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2 + , XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3 + , XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16 + , XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8 + , XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8 + , XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8 + , XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16 + , XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3 + , XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT + , XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16 + , XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2 + , XC16X_F_POF, XC16X_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) XC16X_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for xc16x hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR + , HW_H_EXT, HW_H_PSW, HW_H_GRB, HW_H_CC + , HW_H_ECC, HW_H_GRB8, HW_H_R8, HW_H_REGMEM8 + , HW_H_REGDIV8, HW_H_R0, HW_H_R01, HW_H_REGBMEM8 + , HW_H_MEMGR8, HW_H_COND, HW_H_CBIT, HW_H_SGTDIS + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX + , CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX, CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS + , CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_DOT_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_DOT_PREFIX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_POF_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_POF_PREFIX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PAG_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PAG_PREFIX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SOF_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SOF_PREFIX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEG_PREFIX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEG_PREFIX)) != 0) + +/* Enum declaration for xc16x operand types. */ +typedef enum cgen_operand_type { + XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI + , XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1 + , XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2 + , XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8 + , XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8 + , XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8 + , XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR + , XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1 + , XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2 + , XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01 + , XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY + , XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT + , XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM + , XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16 + , XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH + , XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF + , XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 65 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld xc16x_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD xc16x_cgen_opval_gr_names; +extern CGEN_KEYWORD xc16x_cgen_opval_gr_names; +extern CGEN_KEYWORD xc16x_cgen_opval_ext_names; +extern CGEN_KEYWORD xc16x_cgen_opval_psw_names; +extern CGEN_KEYWORD xc16x_cgen_opval_grb_names; +extern CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names; +extern CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names; +extern CGEN_KEYWORD xc16x_cgen_opval_grb8_names; +extern CGEN_KEYWORD xc16x_cgen_opval_r8_names; +extern CGEN_KEYWORD xc16x_cgen_opval_regmem8_names; +extern CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names; +extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name; +extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name1; +extern CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names; +extern CGEN_KEYWORD xc16x_cgen_opval_memgr8_names; + +extern const CGEN_HW_ENTRY xc16x_cgen_hw_table[]; + + + +#endif /* XC16X_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-dis.c b/external/gpl3/gdb/dist/opcodes/xc16x-dis.c new file mode 100644 index 000000000000..09bb73bf31d8 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-dis.c @@ -0,0 +1,841 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "xc16x-desc.h" +#include "xc16x-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +/* Print an operand with a "." prefix. + NOTE: This prints the operand in hex. + ??? This exists to maintain disassembler compatibility with previous + versions. Ideally we'd print the "." in print_dot. */ + +static void +print_with_dot_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "."); + info->fprintf_func (info->stream, "0x%lx", value); +} + +/* Print an operand with a "#pof:" prefix. + NOTE: This prints the operand as an address. + ??? This exists to maintain disassembler compatibility with previous + versions. Ideally we'd print "#pof:" in print_pof. */ + +static void +print_with_pof_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + bfd_vma value, + unsigned attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "#pof:"); + info->fprintf_func (info->stream, "0x%lx", (long) value); +} + +/* Print an operand with a "#pag:" prefix. + NOTE: This prints the operand in hex. + ??? This exists to maintain disassembler compatibility with previous + versions. Ideally we'd print "#pag:" in print_pag. */ + +static void +print_with_pag_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "#pag:"); + info->fprintf_func (info->stream, "0x%lx", value); +} + +/* Print a 'pof:' prefix to an operand. */ + +static void +print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ +} + +/* Print a 'pag:' prefix to an operand. */ + +static void +print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ +} + +/* Print a 'sof:' prefix to an operand. */ + +static void +print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "sof:"); +} + +/* Print a 'seg:' prefix to an operand. */ + +static void +print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "seg:"); +} + +/* Print a '#' prefix to an operand. */ + +static void +print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + info->fprintf_func (info->stream, "#"); +} + +/* Print a '.' prefix to an operand. */ + +static void +print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ +} + +/* -- */ + +void xc16x_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +xc16x_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + print_keyword (cd, info, & xc16x_cgen_opval_psw_names, fields->f_reg8, 0); + break; + case XC16X_OPERAND_BIT01 : + print_normal (cd, info, fields->f_op_1bit, 0, pc, length); + break; + case XC16X_OPERAND_BIT1 : + print_normal (cd, info, fields->f_op_bit1, 0, pc, length); + break; + case XC16X_OPERAND_BIT2 : + print_normal (cd, info, fields->f_op_bit2, 0, pc, length); + break; + case XC16X_OPERAND_BIT4 : + print_normal (cd, info, fields->f_op_bit4, 0, pc, length); + break; + case XC16X_OPERAND_BIT8 : + print_normal (cd, info, fields->f_op_bit8, 0, pc, length); + break; + case XC16X_OPERAND_BITONE : + print_normal (cd, info, fields->f_op_onebit, 0, pc, length); + break; + case XC16X_OPERAND_CADDR : + print_address (cd, info, fields->f_offset16, 0|(1<f_condcode, 0); + break; + case XC16X_OPERAND_DATA8 : + print_normal (cd, info, fields->f_data8, 0|(1<f_datahi8, 0|(1<f_r1, 0); + break; + case XC16X_OPERAND_DRB : + print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r1, 0); + break; + case XC16X_OPERAND_DRI : + print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r4, 0); + break; + case XC16X_OPERAND_EXTCOND : + print_keyword (cd, info, & xc16x_cgen_opval_extconditioncode_names, fields->f_extccode, 0); + break; + case XC16X_OPERAND_GENREG : + print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regb8, 0); + break; + case XC16X_OPERAND_HASH : + print_hash (cd, info, 0, 0|(1<f_icondcode, 0); + break; + case XC16X_OPERAND_LBIT2 : + print_normal (cd, info, fields->f_op_lbit2, 0, pc, length); + break; + case XC16X_OPERAND_LBIT4 : + print_normal (cd, info, fields->f_op_lbit4, 0, pc, length); + break; + case XC16X_OPERAND_MASK8 : + print_normal (cd, info, fields->f_mask8, 0|(1<f_datahi8, 0|(1<f_memgr8, 0); + break; + case XC16X_OPERAND_MEMORY : + print_address (cd, info, fields->f_memory, 0, pc, length); + break; + case XC16X_OPERAND_PAG : + print_pag (cd, info, 0, 0|(1<f_pagenum, 0|(1<f_qbit, 0|(1<f_qhibit, 0|(1<f_qlobit, 0|(1<f_reg8, 0); + break; + case XC16X_OPERAND_REGB8 : + print_keyword (cd, info, & xc16x_cgen_opval_grb8_names, fields->f_regb8, 0); + break; + case XC16X_OPERAND_REGBMEM8 : + print_keyword (cd, info, & xc16x_cgen_opval_regbmem8_names, fields->f_regmem8, 0); + break; + case XC16X_OPERAND_REGHI8 : + print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_reghi8, 0); + break; + case XC16X_OPERAND_REGMEM8 : + print_keyword (cd, info, & xc16x_cgen_opval_regmem8_names, fields->f_regmem8, 0); + break; + case XC16X_OPERAND_REGOFF8 : + print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regoff8, 0); + break; + case XC16X_OPERAND_REL : + print_normal (cd, info, fields->f_rel8, 0|(1<f_relhi8, 0|(1<f_seg8, 0, pc, length); + break; + case XC16X_OPERAND_SEGHI8 : + print_normal (cd, info, fields->f_segnum8, 0, pc, length); + break; + case XC16X_OPERAND_SEGM : + print_seg (cd, info, 0, 0|(1<f_r2, 0); + break; + case XC16X_OPERAND_SR2 : + print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r0, 0); + break; + case XC16X_OPERAND_SRB : + print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r2, 0); + break; + case XC16X_OPERAND_SRC1 : + print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r1, 0); + break; + case XC16X_OPERAND_SRC2 : + print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r2, 0); + break; + case XC16X_OPERAND_SRDIV : + print_keyword (cd, info, & xc16x_cgen_opval_regdiv8_names, fields->f_reg8, 0); + break; + case XC16X_OPERAND_U4 : + print_keyword (cd, info, & xc16x_cgen_opval_reg0_name, fields->f_uimm4, 0); + break; + case XC16X_OPERAND_UIMM16 : + print_normal (cd, info, fields->f_uimm16, 0|(1<f_uimm2, 0|(1<f_uimm3, 0|(1<f_uimm4, 0|(1<f_uimm7, 0|(1<f_uimm8, 0|(1<f_uimm16, 0|(1<f_memory, 0|(1<f_offset16, 0|(1<f_seg8, 0|(1<f_offset16, 0|(1<print_handlers = & xc16x_cgen_print_handlers[0]; + cd->print_operand = xc16x_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + xc16x_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! xc16x_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_xc16x (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_xc16x +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + xc16x_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-ibld.c b/external/gpl3/gdb/dist/opcodes/xc16x-ibld.c new file mode 100644 index 000000000000..a5c816cc9847 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-ibld.c @@ -0,0 +1,1812 @@ +/* Instruction building/extraction support for xc16x. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "xc16x-desc.h" +#include "xc16x-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * xc16x_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +xc16x_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_BIT01 : + errmsg = insert_normal (cd, fields->f_op_1bit, 0, 0, 8, 1, 32, total_length, buffer); + break; + case XC16X_OPERAND_BIT1 : + errmsg = insert_normal (cd, fields->f_op_bit1, 0, 0, 11, 1, 32, total_length, buffer); + break; + case XC16X_OPERAND_BIT2 : + errmsg = insert_normal (cd, fields->f_op_bit2, 0, 0, 11, 2, 32, total_length, buffer); + break; + case XC16X_OPERAND_BIT4 : + errmsg = insert_normal (cd, fields->f_op_bit4, 0, 0, 11, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_BIT8 : + errmsg = insert_normal (cd, fields->f_op_bit8, 0, 0, 31, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_BITONE : + errmsg = insert_normal (cd, fields->f_op_onebit, 0, 0, 9, 1, 32, total_length, buffer); + break; + case XC16X_OPERAND_CADDR : + errmsg = insert_normal (cd, fields->f_offset16, 0|(1<f_condcode, 0, 0, 7, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_DATA8 : + errmsg = insert_normal (cd, fields->f_data8, 0, 0, 23, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_DATAHI8 : + errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_DOT : + break; + case XC16X_OPERAND_DR : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_DRB : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_DRI : + errmsg = insert_normal (cd, fields->f_r4, 0, 0, 11, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_EXTCOND : + errmsg = insert_normal (cd, fields->f_extccode, 0, 0, 15, 5, 32, total_length, buffer); + break; + case XC16X_OPERAND_GENREG : + errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_HASH : + break; + case XC16X_OPERAND_ICOND : + errmsg = insert_normal (cd, fields->f_icondcode, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_LBIT2 : + errmsg = insert_normal (cd, fields->f_op_lbit2, 0, 0, 15, 2, 32, total_length, buffer); + break; + case XC16X_OPERAND_LBIT4 : + errmsg = insert_normal (cd, fields->f_op_lbit4, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_MASK8 : + errmsg = insert_normal (cd, fields->f_mask8, 0, 0, 23, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_MASKLO8 : + errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_MEMGR8 : + errmsg = insert_normal (cd, fields->f_memgr8, 0, 0, 31, 16, 32, total_length, buffer); + break; + case XC16X_OPERAND_MEMORY : + errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer); + break; + case XC16X_OPERAND_PAG : + break; + case XC16X_OPERAND_PAGENUM : + errmsg = insert_normal (cd, fields->f_pagenum, 0, 0, 25, 10, 32, total_length, buffer); + break; + case XC16X_OPERAND_POF : + break; + case XC16X_OPERAND_QBIT : + errmsg = insert_normal (cd, fields->f_qbit, 0, 0, 7, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_QHIBIT : + errmsg = insert_normal (cd, fields->f_qhibit, 0, 0, 27, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_QLOBIT : + errmsg = insert_normal (cd, fields->f_qlobit, 0, 0, 31, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_REG8 : + errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REGB8 : + errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REGBMEM8 : + errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REGHI8 : + errmsg = insert_normal (cd, fields->f_reghi8, 0, 0, 23, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REGMEM8 : + errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REGOFF8 : + errmsg = insert_normal (cd, fields->f_regoff8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_REL : + errmsg = insert_normal (cd, fields->f_rel8, 0|(1<f_relhi8, 0|(1<f_seg8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_SEGHI8 : + errmsg = insert_normal (cd, fields->f_segnum8, 0, 0, 23, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_SEGM : + break; + case XC16X_OPERAND_SOF : + break; + case XC16X_OPERAND_SR : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_SR2 : + errmsg = insert_normal (cd, fields->f_r0, 0, 0, 9, 2, 32, total_length, buffer); + break; + case XC16X_OPERAND_SRB : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_SRC1 : + errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_SRC2 : + errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_SRDIV : + errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_U4 : + errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_UIMM16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer); + break; + case XC16X_OPERAND_UIMM2 : + errmsg = insert_normal (cd, fields->f_uimm2, 0, 0, 13, 2, 32, total_length, buffer); + break; + case XC16X_OPERAND_UIMM3 : + errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 10, 3, 32, total_length, buffer); + break; + case XC16X_OPERAND_UIMM4 : + errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer); + break; + case XC16X_OPERAND_UIMM7 : + errmsg = insert_normal (cd, fields->f_uimm7, 0|(1<f_uimm8, 0, 0, 23, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_UPAG16 : + errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer); + break; + case XC16X_OPERAND_UPOF16 : + errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer); + break; + case XC16X_OPERAND_USEG16 : + errmsg = insert_normal (cd, fields->f_offset16, 0|(1<f_seg8, 0, 0, 15, 8, 32, total_length, buffer); + break; + case XC16X_OPERAND_USOF16 : + errmsg = insert_normal (cd, fields->f_offset16, 0|(1<0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +xc16x_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8); + break; + case XC16X_OPERAND_BIT01 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_op_1bit); + break; + case XC16X_OPERAND_BIT1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_op_bit1); + break; + case XC16X_OPERAND_BIT2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_op_bit2); + break; + case XC16X_OPERAND_BIT4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_op_bit4); + break; + case XC16X_OPERAND_BIT8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_op_bit8); + break; + case XC16X_OPERAND_BITONE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_op_onebit); + break; + case XC16X_OPERAND_CADDR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset16); + break; + case XC16X_OPERAND_COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_condcode); + break; + case XC16X_OPERAND_DATA8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_data8); + break; + case XC16X_OPERAND_DATAHI8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8); + break; + case XC16X_OPERAND_DOT : + break; + case XC16X_OPERAND_DR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1); + break; + case XC16X_OPERAND_DRB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1); + break; + case XC16X_OPERAND_DRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r4); + break; + case XC16X_OPERAND_EXTCOND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_extccode); + break; + case XC16X_OPERAND_GENREG : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8); + break; + case XC16X_OPERAND_HASH : + break; + case XC16X_OPERAND_ICOND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_icondcode); + break; + case XC16X_OPERAND_LBIT2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 2, 32, total_length, pc, & fields->f_op_lbit2); + break; + case XC16X_OPERAND_LBIT4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_op_lbit4); + break; + case XC16X_OPERAND_MASK8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_mask8); + break; + case XC16X_OPERAND_MASKLO8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8); + break; + case XC16X_OPERAND_MEMGR8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memgr8); + break; + case XC16X_OPERAND_MEMORY : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory); + break; + case XC16X_OPERAND_PAG : + break; + case XC16X_OPERAND_PAGENUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 10, 32, total_length, pc, & fields->f_pagenum); + break; + case XC16X_OPERAND_POF : + break; + case XC16X_OPERAND_QBIT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_qbit); + break; + case XC16X_OPERAND_QHIBIT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 4, 32, total_length, pc, & fields->f_qhibit); + break; + case XC16X_OPERAND_QLOBIT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 4, 32, total_length, pc, & fields->f_qlobit); + break; + case XC16X_OPERAND_REG8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8); + break; + case XC16X_OPERAND_REGB8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8); + break; + case XC16X_OPERAND_REGBMEM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8); + break; + case XC16X_OPERAND_REGHI8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_reghi8); + break; + case XC16X_OPERAND_REGMEM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8); + break; + case XC16X_OPERAND_REGOFF8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regoff8); + break; + case XC16X_OPERAND_REL : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel8); + break; + case XC16X_OPERAND_RELHI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_relhi8); + break; + case XC16X_OPERAND_SEG : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8); + break; + case XC16X_OPERAND_SEGHI8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_segnum8); + break; + case XC16X_OPERAND_SEGM : + break; + case XC16X_OPERAND_SOF : + break; + case XC16X_OPERAND_SR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2); + break; + case XC16X_OPERAND_SR2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_r0); + break; + case XC16X_OPERAND_SRB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2); + break; + case XC16X_OPERAND_SRC1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1); + break; + case XC16X_OPERAND_SRC2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2); + break; + case XC16X_OPERAND_SRDIV : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8); + break; + case XC16X_OPERAND_U4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4); + break; + case XC16X_OPERAND_UIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case XC16X_OPERAND_UIMM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 2, 32, total_length, pc, & fields->f_uimm2); + break; + case XC16X_OPERAND_UIMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 3, 32, total_length, pc, & fields->f_uimm3); + break; + case XC16X_OPERAND_UIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4); + break; + case XC16X_OPERAND_UIMM7 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_uimm7); + break; + case XC16X_OPERAND_UIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_uimm8); + break; + case XC16X_OPERAND_UPAG16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16); + break; + case XC16X_OPERAND_UPOF16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory); + break; + case XC16X_OPERAND_USEG16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset16); + break; + case XC16X_OPERAND_USEG8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8); + break; + case XC16X_OPERAND_USOF16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const xc16x_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const xc16x_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int xc16x_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma xc16x_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +xc16x_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + value = fields->f_reg8; + break; + case XC16X_OPERAND_BIT01 : + value = fields->f_op_1bit; + break; + case XC16X_OPERAND_BIT1 : + value = fields->f_op_bit1; + break; + case XC16X_OPERAND_BIT2 : + value = fields->f_op_bit2; + break; + case XC16X_OPERAND_BIT4 : + value = fields->f_op_bit4; + break; + case XC16X_OPERAND_BIT8 : + value = fields->f_op_bit8; + break; + case XC16X_OPERAND_BITONE : + value = fields->f_op_onebit; + break; + case XC16X_OPERAND_CADDR : + value = fields->f_offset16; + break; + case XC16X_OPERAND_COND : + value = fields->f_condcode; + break; + case XC16X_OPERAND_DATA8 : + value = fields->f_data8; + break; + case XC16X_OPERAND_DATAHI8 : + value = fields->f_datahi8; + break; + case XC16X_OPERAND_DOT : + value = 0; + break; + case XC16X_OPERAND_DR : + value = fields->f_r1; + break; + case XC16X_OPERAND_DRB : + value = fields->f_r1; + break; + case XC16X_OPERAND_DRI : + value = fields->f_r4; + break; + case XC16X_OPERAND_EXTCOND : + value = fields->f_extccode; + break; + case XC16X_OPERAND_GENREG : + value = fields->f_regb8; + break; + case XC16X_OPERAND_HASH : + value = 0; + break; + case XC16X_OPERAND_ICOND : + value = fields->f_icondcode; + break; + case XC16X_OPERAND_LBIT2 : + value = fields->f_op_lbit2; + break; + case XC16X_OPERAND_LBIT4 : + value = fields->f_op_lbit4; + break; + case XC16X_OPERAND_MASK8 : + value = fields->f_mask8; + break; + case XC16X_OPERAND_MASKLO8 : + value = fields->f_datahi8; + break; + case XC16X_OPERAND_MEMGR8 : + value = fields->f_memgr8; + break; + case XC16X_OPERAND_MEMORY : + value = fields->f_memory; + break; + case XC16X_OPERAND_PAG : + value = 0; + break; + case XC16X_OPERAND_PAGENUM : + value = fields->f_pagenum; + break; + case XC16X_OPERAND_POF : + value = 0; + break; + case XC16X_OPERAND_QBIT : + value = fields->f_qbit; + break; + case XC16X_OPERAND_QHIBIT : + value = fields->f_qhibit; + break; + case XC16X_OPERAND_QLOBIT : + value = fields->f_qlobit; + break; + case XC16X_OPERAND_REG8 : + value = fields->f_reg8; + break; + case XC16X_OPERAND_REGB8 : + value = fields->f_regb8; + break; + case XC16X_OPERAND_REGBMEM8 : + value = fields->f_regmem8; + break; + case XC16X_OPERAND_REGHI8 : + value = fields->f_reghi8; + break; + case XC16X_OPERAND_REGMEM8 : + value = fields->f_regmem8; + break; + case XC16X_OPERAND_REGOFF8 : + value = fields->f_regoff8; + break; + case XC16X_OPERAND_REL : + value = fields->f_rel8; + break; + case XC16X_OPERAND_RELHI : + value = fields->f_relhi8; + break; + case XC16X_OPERAND_SEG : + value = fields->f_seg8; + break; + case XC16X_OPERAND_SEGHI8 : + value = fields->f_segnum8; + break; + case XC16X_OPERAND_SEGM : + value = 0; + break; + case XC16X_OPERAND_SOF : + value = 0; + break; + case XC16X_OPERAND_SR : + value = fields->f_r2; + break; + case XC16X_OPERAND_SR2 : + value = fields->f_r0; + break; + case XC16X_OPERAND_SRB : + value = fields->f_r2; + break; + case XC16X_OPERAND_SRC1 : + value = fields->f_r1; + break; + case XC16X_OPERAND_SRC2 : + value = fields->f_r2; + break; + case XC16X_OPERAND_SRDIV : + value = fields->f_reg8; + break; + case XC16X_OPERAND_U4 : + value = fields->f_uimm4; + break; + case XC16X_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case XC16X_OPERAND_UIMM2 : + value = fields->f_uimm2; + break; + case XC16X_OPERAND_UIMM3 : + value = fields->f_uimm3; + break; + case XC16X_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case XC16X_OPERAND_UIMM7 : + value = fields->f_uimm7; + break; + case XC16X_OPERAND_UIMM8 : + value = fields->f_uimm8; + break; + case XC16X_OPERAND_UPAG16 : + value = fields->f_uimm16; + break; + case XC16X_OPERAND_UPOF16 : + value = fields->f_memory; + break; + case XC16X_OPERAND_USEG16 : + value = fields->f_offset16; + break; + case XC16X_OPERAND_USEG8 : + value = fields->f_seg8; + break; + case XC16X_OPERAND_USOF16 : + value = fields->f_offset16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +xc16x_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + value = fields->f_reg8; + break; + case XC16X_OPERAND_BIT01 : + value = fields->f_op_1bit; + break; + case XC16X_OPERAND_BIT1 : + value = fields->f_op_bit1; + break; + case XC16X_OPERAND_BIT2 : + value = fields->f_op_bit2; + break; + case XC16X_OPERAND_BIT4 : + value = fields->f_op_bit4; + break; + case XC16X_OPERAND_BIT8 : + value = fields->f_op_bit8; + break; + case XC16X_OPERAND_BITONE : + value = fields->f_op_onebit; + break; + case XC16X_OPERAND_CADDR : + value = fields->f_offset16; + break; + case XC16X_OPERAND_COND : + value = fields->f_condcode; + break; + case XC16X_OPERAND_DATA8 : + value = fields->f_data8; + break; + case XC16X_OPERAND_DATAHI8 : + value = fields->f_datahi8; + break; + case XC16X_OPERAND_DOT : + value = 0; + break; + case XC16X_OPERAND_DR : + value = fields->f_r1; + break; + case XC16X_OPERAND_DRB : + value = fields->f_r1; + break; + case XC16X_OPERAND_DRI : + value = fields->f_r4; + break; + case XC16X_OPERAND_EXTCOND : + value = fields->f_extccode; + break; + case XC16X_OPERAND_GENREG : + value = fields->f_regb8; + break; + case XC16X_OPERAND_HASH : + value = 0; + break; + case XC16X_OPERAND_ICOND : + value = fields->f_icondcode; + break; + case XC16X_OPERAND_LBIT2 : + value = fields->f_op_lbit2; + break; + case XC16X_OPERAND_LBIT4 : + value = fields->f_op_lbit4; + break; + case XC16X_OPERAND_MASK8 : + value = fields->f_mask8; + break; + case XC16X_OPERAND_MASKLO8 : + value = fields->f_datahi8; + break; + case XC16X_OPERAND_MEMGR8 : + value = fields->f_memgr8; + break; + case XC16X_OPERAND_MEMORY : + value = fields->f_memory; + break; + case XC16X_OPERAND_PAG : + value = 0; + break; + case XC16X_OPERAND_PAGENUM : + value = fields->f_pagenum; + break; + case XC16X_OPERAND_POF : + value = 0; + break; + case XC16X_OPERAND_QBIT : + value = fields->f_qbit; + break; + case XC16X_OPERAND_QHIBIT : + value = fields->f_qhibit; + break; + case XC16X_OPERAND_QLOBIT : + value = fields->f_qlobit; + break; + case XC16X_OPERAND_REG8 : + value = fields->f_reg8; + break; + case XC16X_OPERAND_REGB8 : + value = fields->f_regb8; + break; + case XC16X_OPERAND_REGBMEM8 : + value = fields->f_regmem8; + break; + case XC16X_OPERAND_REGHI8 : + value = fields->f_reghi8; + break; + case XC16X_OPERAND_REGMEM8 : + value = fields->f_regmem8; + break; + case XC16X_OPERAND_REGOFF8 : + value = fields->f_regoff8; + break; + case XC16X_OPERAND_REL : + value = fields->f_rel8; + break; + case XC16X_OPERAND_RELHI : + value = fields->f_relhi8; + break; + case XC16X_OPERAND_SEG : + value = fields->f_seg8; + break; + case XC16X_OPERAND_SEGHI8 : + value = fields->f_segnum8; + break; + case XC16X_OPERAND_SEGM : + value = 0; + break; + case XC16X_OPERAND_SOF : + value = 0; + break; + case XC16X_OPERAND_SR : + value = fields->f_r2; + break; + case XC16X_OPERAND_SR2 : + value = fields->f_r0; + break; + case XC16X_OPERAND_SRB : + value = fields->f_r2; + break; + case XC16X_OPERAND_SRC1 : + value = fields->f_r1; + break; + case XC16X_OPERAND_SRC2 : + value = fields->f_r2; + break; + case XC16X_OPERAND_SRDIV : + value = fields->f_reg8; + break; + case XC16X_OPERAND_U4 : + value = fields->f_uimm4; + break; + case XC16X_OPERAND_UIMM16 : + value = fields->f_uimm16; + break; + case XC16X_OPERAND_UIMM2 : + value = fields->f_uimm2; + break; + case XC16X_OPERAND_UIMM3 : + value = fields->f_uimm3; + break; + case XC16X_OPERAND_UIMM4 : + value = fields->f_uimm4; + break; + case XC16X_OPERAND_UIMM7 : + value = fields->f_uimm7; + break; + case XC16X_OPERAND_UIMM8 : + value = fields->f_uimm8; + break; + case XC16X_OPERAND_UPAG16 : + value = fields->f_uimm16; + break; + case XC16X_OPERAND_UPOF16 : + value = fields->f_memory; + break; + case XC16X_OPERAND_USEG16 : + value = fields->f_offset16; + break; + case XC16X_OPERAND_USEG8 : + value = fields->f_seg8; + break; + case XC16X_OPERAND_USOF16 : + value = fields->f_offset16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void xc16x_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void xc16x_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +xc16x_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_BIT01 : + fields->f_op_1bit = value; + break; + case XC16X_OPERAND_BIT1 : + fields->f_op_bit1 = value; + break; + case XC16X_OPERAND_BIT2 : + fields->f_op_bit2 = value; + break; + case XC16X_OPERAND_BIT4 : + fields->f_op_bit4 = value; + break; + case XC16X_OPERAND_BIT8 : + fields->f_op_bit8 = value; + break; + case XC16X_OPERAND_BITONE : + fields->f_op_onebit = value; + break; + case XC16X_OPERAND_CADDR : + fields->f_offset16 = value; + break; + case XC16X_OPERAND_COND : + fields->f_condcode = value; + break; + case XC16X_OPERAND_DATA8 : + fields->f_data8 = value; + break; + case XC16X_OPERAND_DATAHI8 : + fields->f_datahi8 = value; + break; + case XC16X_OPERAND_DOT : + break; + case XC16X_OPERAND_DR : + fields->f_r1 = value; + break; + case XC16X_OPERAND_DRB : + fields->f_r1 = value; + break; + case XC16X_OPERAND_DRI : + fields->f_r4 = value; + break; + case XC16X_OPERAND_EXTCOND : + fields->f_extccode = value; + break; + case XC16X_OPERAND_GENREG : + fields->f_regb8 = value; + break; + case XC16X_OPERAND_HASH : + break; + case XC16X_OPERAND_ICOND : + fields->f_icondcode = value; + break; + case XC16X_OPERAND_LBIT2 : + fields->f_op_lbit2 = value; + break; + case XC16X_OPERAND_LBIT4 : + fields->f_op_lbit4 = value; + break; + case XC16X_OPERAND_MASK8 : + fields->f_mask8 = value; + break; + case XC16X_OPERAND_MASKLO8 : + fields->f_datahi8 = value; + break; + case XC16X_OPERAND_MEMGR8 : + fields->f_memgr8 = value; + break; + case XC16X_OPERAND_MEMORY : + fields->f_memory = value; + break; + case XC16X_OPERAND_PAG : + break; + case XC16X_OPERAND_PAGENUM : + fields->f_pagenum = value; + break; + case XC16X_OPERAND_POF : + break; + case XC16X_OPERAND_QBIT : + fields->f_qbit = value; + break; + case XC16X_OPERAND_QHIBIT : + fields->f_qhibit = value; + break; + case XC16X_OPERAND_QLOBIT : + fields->f_qlobit = value; + break; + case XC16X_OPERAND_REG8 : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_REGB8 : + fields->f_regb8 = value; + break; + case XC16X_OPERAND_REGBMEM8 : + fields->f_regmem8 = value; + break; + case XC16X_OPERAND_REGHI8 : + fields->f_reghi8 = value; + break; + case XC16X_OPERAND_REGMEM8 : + fields->f_regmem8 = value; + break; + case XC16X_OPERAND_REGOFF8 : + fields->f_regoff8 = value; + break; + case XC16X_OPERAND_REL : + fields->f_rel8 = value; + break; + case XC16X_OPERAND_RELHI : + fields->f_relhi8 = value; + break; + case XC16X_OPERAND_SEG : + fields->f_seg8 = value; + break; + case XC16X_OPERAND_SEGHI8 : + fields->f_segnum8 = value; + break; + case XC16X_OPERAND_SEGM : + break; + case XC16X_OPERAND_SOF : + break; + case XC16X_OPERAND_SR : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SR2 : + fields->f_r0 = value; + break; + case XC16X_OPERAND_SRB : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case XC16X_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SRDIV : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_U4 : + fields->f_uimm4 = value; + break; + case XC16X_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case XC16X_OPERAND_UIMM2 : + fields->f_uimm2 = value; + break; + case XC16X_OPERAND_UIMM3 : + fields->f_uimm3 = value; + break; + case XC16X_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case XC16X_OPERAND_UIMM7 : + fields->f_uimm7 = value; + break; + case XC16X_OPERAND_UIMM8 : + fields->f_uimm8 = value; + break; + case XC16X_OPERAND_UPAG16 : + fields->f_uimm16 = value; + break; + case XC16X_OPERAND_UPOF16 : + fields->f_memory = value; + break; + case XC16X_OPERAND_USEG16 : + fields->f_offset16 = value; + break; + case XC16X_OPERAND_USEG8 : + fields->f_seg8 = value; + break; + case XC16X_OPERAND_USOF16 : + fields->f_offset16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +xc16x_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case XC16X_OPERAND_REGNAM : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_BIT01 : + fields->f_op_1bit = value; + break; + case XC16X_OPERAND_BIT1 : + fields->f_op_bit1 = value; + break; + case XC16X_OPERAND_BIT2 : + fields->f_op_bit2 = value; + break; + case XC16X_OPERAND_BIT4 : + fields->f_op_bit4 = value; + break; + case XC16X_OPERAND_BIT8 : + fields->f_op_bit8 = value; + break; + case XC16X_OPERAND_BITONE : + fields->f_op_onebit = value; + break; + case XC16X_OPERAND_CADDR : + fields->f_offset16 = value; + break; + case XC16X_OPERAND_COND : + fields->f_condcode = value; + break; + case XC16X_OPERAND_DATA8 : + fields->f_data8 = value; + break; + case XC16X_OPERAND_DATAHI8 : + fields->f_datahi8 = value; + break; + case XC16X_OPERAND_DOT : + break; + case XC16X_OPERAND_DR : + fields->f_r1 = value; + break; + case XC16X_OPERAND_DRB : + fields->f_r1 = value; + break; + case XC16X_OPERAND_DRI : + fields->f_r4 = value; + break; + case XC16X_OPERAND_EXTCOND : + fields->f_extccode = value; + break; + case XC16X_OPERAND_GENREG : + fields->f_regb8 = value; + break; + case XC16X_OPERAND_HASH : + break; + case XC16X_OPERAND_ICOND : + fields->f_icondcode = value; + break; + case XC16X_OPERAND_LBIT2 : + fields->f_op_lbit2 = value; + break; + case XC16X_OPERAND_LBIT4 : + fields->f_op_lbit4 = value; + break; + case XC16X_OPERAND_MASK8 : + fields->f_mask8 = value; + break; + case XC16X_OPERAND_MASKLO8 : + fields->f_datahi8 = value; + break; + case XC16X_OPERAND_MEMGR8 : + fields->f_memgr8 = value; + break; + case XC16X_OPERAND_MEMORY : + fields->f_memory = value; + break; + case XC16X_OPERAND_PAG : + break; + case XC16X_OPERAND_PAGENUM : + fields->f_pagenum = value; + break; + case XC16X_OPERAND_POF : + break; + case XC16X_OPERAND_QBIT : + fields->f_qbit = value; + break; + case XC16X_OPERAND_QHIBIT : + fields->f_qhibit = value; + break; + case XC16X_OPERAND_QLOBIT : + fields->f_qlobit = value; + break; + case XC16X_OPERAND_REG8 : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_REGB8 : + fields->f_regb8 = value; + break; + case XC16X_OPERAND_REGBMEM8 : + fields->f_regmem8 = value; + break; + case XC16X_OPERAND_REGHI8 : + fields->f_reghi8 = value; + break; + case XC16X_OPERAND_REGMEM8 : + fields->f_regmem8 = value; + break; + case XC16X_OPERAND_REGOFF8 : + fields->f_regoff8 = value; + break; + case XC16X_OPERAND_REL : + fields->f_rel8 = value; + break; + case XC16X_OPERAND_RELHI : + fields->f_relhi8 = value; + break; + case XC16X_OPERAND_SEG : + fields->f_seg8 = value; + break; + case XC16X_OPERAND_SEGHI8 : + fields->f_segnum8 = value; + break; + case XC16X_OPERAND_SEGM : + break; + case XC16X_OPERAND_SOF : + break; + case XC16X_OPERAND_SR : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SR2 : + fields->f_r0 = value; + break; + case XC16X_OPERAND_SRB : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case XC16X_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case XC16X_OPERAND_SRDIV : + fields->f_reg8 = value; + break; + case XC16X_OPERAND_U4 : + fields->f_uimm4 = value; + break; + case XC16X_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; + case XC16X_OPERAND_UIMM2 : + fields->f_uimm2 = value; + break; + case XC16X_OPERAND_UIMM3 : + fields->f_uimm3 = value; + break; + case XC16X_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case XC16X_OPERAND_UIMM7 : + fields->f_uimm7 = value; + break; + case XC16X_OPERAND_UIMM8 : + fields->f_uimm8 = value; + break; + case XC16X_OPERAND_UPAG16 : + fields->f_uimm16 = value; + break; + case XC16X_OPERAND_UPOF16 : + fields->f_memory = value; + break; + case XC16X_OPERAND_USEG16 : + fields->f_offset16 = value; + break; + case XC16X_OPERAND_USEG8 : + fields->f_seg8 = value; + break; + case XC16X_OPERAND_USOF16 : + fields->f_offset16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +xc16x_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & xc16x_cgen_insert_handlers[0]; + cd->extract_handlers = & xc16x_cgen_extract_handlers[0]; + + cd->insert_operand = xc16x_cgen_insert_operand; + cd->extract_operand = xc16x_cgen_extract_operand; + + cd->get_int_operand = xc16x_cgen_get_int_operand; + cd->set_int_operand = xc16x_cgen_set_int_operand; + cd->get_vma_operand = xc16x_cgen_get_vma_operand; + cd->set_vma_operand = xc16x_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-opc.c b/external/gpl3/gdb/dist/opcodes/xc16x-opc.c new file mode 100644 index 000000000000..7a5abc05343f --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-opc.c @@ -0,0 +1,3052 @@ +/* Instruction opcode table for xc16x. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xc16x-desc.h" +#include "xc16x-opc.h" +#include "libiberty.h" + +/* -- opc.c */ + +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & xc16x_cgen_ifld_table[XC16X_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_addrpof ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbrpof ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrpag ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbrpag ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrhpof ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrhpof3 ATTRIBUTE_UNUSED = { + 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbrhpag3 ATTRIBUTE_UNUSED = { + 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrbhpof ATTRIBUTE_UNUSED = { + 32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addr ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbr ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 ATTRIBUTE_UNUSED = { + 16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addb2 ATTRIBUTE_UNUSED = { + 16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrm2 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addrm ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbrm2 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addbrm ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_muls ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpl ATTRIBUTE_UNUSED = { + 16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cplb ATTRIBUTE_UNUSED = { + 16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movri ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movbri ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movbr2 ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov9i ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movb9i ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movri11 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff, { { F (F_MEMORY) }, { F (F_OP_LBIT4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movehm5 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movehm6 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movehm7 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movehm8 ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movehm10 ATTRIBUTE_UNUSED = { + 32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movbsrpofm ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movbspofmr ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpa0 ATTRIBUTE_UNUSED = { + 32, 32, 0x4ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpa_ ATTRIBUTE_UNUSED = { + 32, 32, 0x5ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpi ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_ICONDCODE) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpr_nenz ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REL8) }, { F (F_RCOND) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpseg ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmps ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jb ATTRIBUTE_UNUSED = { + 32, 32, 0xf0000ff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_RELHI8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_calla0 ATTRIBUTE_UNUSED = { + 32, 32, 0x6ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_2BIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_calla_ ATTRIBUTE_UNUSED = { + 32, 32, 0x7ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BIT3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callr ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REL8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callseg ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pcall ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = { + 16, 16, 0x1ff, { { F (F_UIMM7) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = { + 16, 16, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_retp ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_srstm ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OP_BIT8) }, { F (F_DATA8) }, { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_atomic ATTRIBUTE_UNUSED = { + 16, 16, 0xcfff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extp ATTRIBUTE_UNUSED = { + 16, 16, 0xc0ff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extp1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00cfff, { { F (F_QLOBIT) }, { F (F_QLOBIT2) }, { F (F_PAGENUM) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extpg1 ATTRIBUTE_UNUSED = { + 32, 32, 0xcfff, { { F (F_UIMM16) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts1 ATTRIBUTE_UNUSED = { + 32, 32, 0xff00cfff, { { F (F_OP_BIT8) }, { F (F_SEGNUM8) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bclr18 ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bclr0 ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_REG8) }, { F (F_QCOND) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bmov ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_REGHI8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bfldl ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_MASK8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bfldh ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_DATA8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpri ATTRIBUTE_UNUSED = { + 16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpd1ri ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) XC16X_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE xc16x_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x2 } + }, +/* sub $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x22 } + }, +/* addb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x3 } + }, +/* subb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x23 } + }, +/* add $reg8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addrpag, { 0x2 } + }, +/* sub $reg8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addrpag, { 0x22 } + }, +/* addb $regb8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addbrpag, { 0x3 } + }, +/* subb $regb8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addbrpag, { 0x23 } + }, +/* addc $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x12 } + }, +/* subc $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x32 } + }, +/* addcb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x13 } + }, +/* subcb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x33 } + }, +/* addc $reg8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addrpag, { 0x12 } + }, +/* subc $reg8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addrpag, { 0x32 } + }, +/* addcb $regb8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addbrpag, { 0x13 } + }, +/* subcb $regb8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addbrpag, { 0x33 } + }, +/* add $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x4 } + }, +/* sub $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x24 } + }, +/* addb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x5 } + }, +/* subb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x25 } + }, +/* addc $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x14 } + }, +/* subc $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x34 } + }, +/* addcb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x15 } + }, +/* subcb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x35 } + }, +/* add $reg8,$hash$pof$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x6 } + }, +/* sub $reg8,$hash$pof$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x26 } + }, +/* add $reg8,$hash$pag$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x6 } + }, +/* sub $reg8,$hash$pag$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x26 } + }, +/* add $dr,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x8 } + }, +/* sub $dr,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x28 } + }, +/* addb $drb,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x9 } + }, +/* subb $drb,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x29 } + }, +/* add $dr,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x8 } + }, +/* sub $dr,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x28 } + }, +/* addb $drb,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x9 } + }, +/* subb $drb,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x29 } + }, +/* addb $regb8,$hash$pof$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x7 } + }, +/* subb $regb8,$hash$pof$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x27 } + }, +/* addb $regb8,$hash$pag$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x7 } + }, +/* subb $regb8,$hash$pag$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x27 } + }, +/* addc $reg8,$hash$pof$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x16 } + }, +/* subc $reg8,$hash$pof$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x36 } + }, +/* addc $reg8,$hash$pag$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x16 } + }, +/* subc $reg8,$hash$pag$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x36 } + }, +/* addc $dr,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x18 } + }, +/* subc $dr,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x38 } + }, +/* addcb $drb,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x19 } + }, +/* subcb $drb,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x39 } + }, +/* addc $dr,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x18 } + }, +/* subc $dr,$hash$pag$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x38 } + }, +/* addcb $drb,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x19 } + }, +/* subcb $drb,$hash$pof$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x39 } + }, +/* addcb $regb8,$hash$pof$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x17 } + }, +/* subcb $regb8,$hash$pof$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x37 } + }, +/* addcb $regb8,$hash$pag$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x17 } + }, +/* subcb $regb8,$hash$pag$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x37 } + }, +/* add $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x8 } + }, +/* sub $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x28 } + }, +/* addb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x9 } + }, +/* subb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x29 } + }, +/* add $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x6 } + }, +/* sub $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x26 } + }, +/* addb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x7 } + }, +/* subb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x27 } + }, +/* addc $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x18 } + }, +/* subc $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x38 } + }, +/* addcb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x19 } + }, +/* subcb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x39 } + }, +/* addc $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x16 } + }, +/* subc $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x36 } + }, +/* addcb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x17 } + }, +/* subcb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x37 } + }, +/* add $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x0 } + }, +/* sub $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x20 } + }, +/* addb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x1 } + }, +/* subb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x21 } + }, +/* add $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x808 } + }, +/* sub $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x828 } + }, +/* addb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x809 } + }, +/* subb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x829 } + }, +/* add $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc08 } + }, +/* sub $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc28 } + }, +/* addb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc09 } + }, +/* subb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc29 } + }, +/* addc $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x10 } + }, +/* subc $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x30 } + }, +/* addcb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x11 } + }, +/* subcb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x31 } + }, +/* addc $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x818 } + }, +/* subc $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x838 } + }, +/* addcb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x819 } + }, +/* subcb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x839 } + }, +/* addc $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc18 } + }, +/* subc $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc38 } + }, +/* addcb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc19 } + }, +/* subcb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc39 } + }, +/* add $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x2 } + }, +/* add $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x4 } + }, +/* add $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x2 } + }, +/* add $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x4 } + }, +/* sub $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x22 } + }, +/* sub $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x24 } + }, +/* sub $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x22 } + }, +/* sub $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x24 } + }, +/* addb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x3 } + }, +/* addb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x5 } + }, +/* addb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x3 } + }, +/* addb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x5 } + }, +/* subb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x23 } + }, +/* subb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x25 } + }, +/* subb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x23 } + }, +/* subb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x25 } + }, +/* addc $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x12 } + }, +/* addc $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x14 } + }, +/* addc $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x12 } + }, +/* addc $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x14 } + }, +/* subc $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x32 } + }, +/* subc $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x34 } + }, +/* subc $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x32 } + }, +/* subc $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x34 } + }, +/* addcb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x13 } + }, +/* addcb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x15 } + }, +/* addcb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x13 } + }, +/* addcb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x15 } + }, +/* subcb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x33 } + }, +/* subcb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x35 } + }, +/* subcb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x33 } + }, +/* subcb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x35 } + }, +/* mul $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_muls, { 0xb } + }, +/* mulu $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_muls, { 0x1b } + }, +/* div $srdiv */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRDIV), 0 } }, + & ifmt_div, { 0x4b } + }, +/* divl $srdiv */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRDIV), 0 } }, + & ifmt_div, { 0x6b } + }, +/* divlu $srdiv */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRDIV), 0 } }, + & ifmt_div, { 0x7b } + }, +/* divu $srdiv */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRDIV), 0 } }, + & ifmt_div, { 0x5b } + }, +/* cpl $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_cpl, { 0x91 } + }, +/* cplb $drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), 0 } }, + & ifmt_cplb, { 0xb1 } + }, +/* neg $dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), 0 } }, + & ifmt_cpl, { 0x81 } + }, +/* negb $drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), 0 } }, + & ifmt_cplb, { 0xa1 } + }, +/* and $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x60 } + }, +/* or $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x70 } + }, +/* xor $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x50 } + }, +/* andb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x61 } + }, +/* orb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x71 } + }, +/* xorb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x51 } + }, +/* and $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x68 } + }, +/* or $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x78 } + }, +/* xor $dr,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addrhpof3, { 0x58 } + }, +/* andb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x69 } + }, +/* orb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x79 } + }, +/* xorb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x59 } + }, +/* and $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x66 } + }, +/* or $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x76 } + }, +/* xor $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x56 } + }, +/* andb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x67 } + }, +/* orb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x77 } + }, +/* xorb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x57 } + }, +/* and $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x868 } + }, +/* or $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x878 } + }, +/* xor $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x858 } + }, +/* andb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x869 } + }, +/* orb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x879 } + }, +/* xorb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x859 } + }, +/* and $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc68 } + }, +/* or $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc78 } + }, +/* xor $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc58 } + }, +/* andb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc69 } + }, +/* orb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc79 } + }, +/* xorb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc59 } + }, +/* and $pof$reg8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x62 } + }, +/* or $pof$reg8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x72 } + }, +/* xor $pof$reg8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x52 } + }, +/* andb $pof$regb8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x63 } + }, +/* orb $pof$regb8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x73 } + }, +/* xorb $pof$regb8,$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x53 } + }, +/* and $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x64 } + }, +/* or $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x74 } + }, +/* xor $pof$upof16,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } }, + & ifmt_addrpof, { 0x54 } + }, +/* andb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x65 } + }, +/* orb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x75 } + }, +/* xorb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0x55 } + }, +/* and $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x62 } + }, +/* and $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x64 } + }, +/* and $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x62 } + }, +/* and $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x64 } + }, +/* or $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x72 } + }, +/* or $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x74 } + }, +/* or $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x72 } + }, +/* or $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x74 } + }, +/* xor $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x52 } + }, +/* xor $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0x54 } + }, +/* xor $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x52 } + }, +/* xor $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0x54 } + }, +/* andb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x63 } + }, +/* andb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x65 } + }, +/* andb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x63 } + }, +/* andb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x65 } + }, +/* orb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x73 } + }, +/* orb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x75 } + }, +/* orb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x73 } + }, +/* orb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x75 } + }, +/* xorb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x53 } + }, +/* xorb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0x55 } + }, +/* xorb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x53 } + }, +/* xorb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0x55 } + }, +/* mov $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0xf0 } + }, +/* movb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0xf1 } + }, +/* mov $dri,$hash$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (U4), 0 } }, + & ifmt_movri, { 0xe0 } + }, +/* movb $srb,$hash$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (U4), 0 } }, + & ifmt_movbri, { 0xe1 } + }, +/* mov $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0xe6 } + }, +/* movb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0xe7 } + }, +/* mov $dr,[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR), ']', 0 } }, + & ifmt_addr, { 0xa8 } + }, +/* movb $drb,[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), ']', 0 } }, + & ifmt_movbr2, { 0xa9 } + }, +/* mov [$sr],$dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DR), 0 } }, + & ifmt_addr, { 0xb8 } + }, +/* movb [$sr],$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0xb9 } + }, +/* mov [-$sr],$dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DR), 0 } }, + & ifmt_addr, { 0x88 } + }, +/* movb [-$sr],$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0x89 } + }, +/* mov $dr,[$sr+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', ']', 0 } }, + & ifmt_addr, { 0x98 } + }, +/* movb $drb,[$sr+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', ']', 0 } }, + & ifmt_movbr2, { 0x99 } + }, +/* mov [$dr],[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } }, + & ifmt_addr, { 0xc8 } + }, +/* movb [$dr],[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } }, + & ifmt_addr, { 0xc9 } + }, +/* mov [$dr+],[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } }, + & ifmt_addr, { 0xd8 } + }, +/* movb [$dr+],[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } }, + & ifmt_addr, { 0xd9 } + }, +/* mov [$dr],[$sr+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } }, + & ifmt_addr, { 0xe8 } + }, +/* movb [$dr],[$sr+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } }, + & ifmt_addr, { 0xe9 } + }, +/* mov $dr,[$sr+$hash$uimm16] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } }, + & ifmt_mov9i, { 0xd4 } + }, +/* movb $drb,[$sr+$hash$uimm16] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } }, + & ifmt_movb9i, { 0xf4 } + }, +/* mov [$sr+$hash$uimm16],$dr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DR), 0 } }, + & ifmt_mov9i, { 0xc4 } + }, +/* movb [$sr+$hash$uimm16],$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DRB), 0 } }, + & ifmt_movb9i, { 0xe4 } + }, +/* mov [$src2],$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } }, + & ifmt_movri11, { 0x84 } + }, +/* movb [$src2],$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } }, + & ifmt_movri11, { 0xa4 } + }, +/* mov $memory,[$src2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } }, + & ifmt_movri11, { 0x94 } + }, +/* movb $memory,[$src2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } }, + & ifmt_movri11, { 0xb4 } + }, +/* mov $regoff8,$hash$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (POF), OP (UPOF16), 0 } }, + & ifmt_movehm5, { 0xe6 } + }, +/* mov $regoff8,$hash$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UPAG16), 0 } }, + & ifmt_movehm6, { 0xe6 } + }, +/* mov $regoff8,$hash$segm$useg16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SEGM), OP (USEG16), 0 } }, + & ifmt_movehm7, { 0xe6 } + }, +/* mov $regoff8,$hash$sof$usof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } }, + & ifmt_movehm8, { 0xe6 } + }, +/* movb $regb8,$hash$pof$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0xe7 } + }, +/* movb $regoff8,$hash$pag$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } }, + & ifmt_movehm10, { 0xe7 } + }, +/* mov $regoff8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_movehm5, { 0xf2 } + }, +/* movb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0xf3 } + }, +/* mov $regoff8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGOFF8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_movehm6, { 0xf2 } + }, +/* movb $regb8,$pag$upag16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } }, + & ifmt_addbrpag, { 0xf3 } + }, +/* mov $pof$upof16,$regoff8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGOFF8), 0 } }, + & ifmt_movehm5, { 0xf6 } + }, +/* movb $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0xf7 } + }, +/* mov $dri,$hash$pof$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (POF), OP (U4), 0 } }, + & ifmt_movri, { 0xe0 } + }, +/* movb $srb,$hash$pof$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (POF), OP (U4), 0 } }, + & ifmt_movbri, { 0xe1 } + }, +/* mov $dri,$hash$pag$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (PAG), OP (U4), 0 } }, + & ifmt_movri, { 0xe0 } + }, +/* movb $srb,$hash$pag$u4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (PAG), OP (U4), 0 } }, + & ifmt_movbri, { 0xe1 } + }, +/* mov $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xf2 } + }, +/* mov $memgr8,$regmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } }, + & ifmt_addrm2, { 0xf6 } + }, +/* mov $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xf2 } + }, +/* mov $memory,$reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } }, + & ifmt_addrm, { 0xf6 } + }, +/* movb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0xf3 } + }, +/* movb $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0xf7 } + }, +/* movb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0xf3 } + }, +/* movb $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0xf7 } + }, +/* movbs $sr,$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0xd0 } + }, +/* movbz $sr,$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0xc0 } + }, +/* movbs $regmem8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_movbsrpofm, { 0xd2 } + }, +/* movbs $pof$upof16,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGBMEM8), 0 } }, + & ifmt_movbspofmr, { 0xd5 } + }, +/* movbz $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0xc2 } + }, +/* movbz $pof$upof16,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } }, + & ifmt_addbrpof, { 0xc5 } + }, +/* movbs $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xd2 } + }, +/* movbs $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0xd5 } + }, +/* movbs $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xd2 } + }, +/* movbs $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0xd5 } + }, +/* movbz $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xc2 } + }, +/* movbz $memgr8,$regbmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } }, + & ifmt_addbrm2, { 0xc5 } + }, +/* movbz $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xc2 } + }, +/* movbz $memory,$regb8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } }, + & ifmt_addbrm, { 0xc5 } + }, +/* movbs $sr,$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0xd0 } + }, +/* movbz $sr,$drb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } }, + & ifmt_movbr2, { 0xc0 } + }, +/* jmpa+ $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_jmpa0, { 0xea } + }, +/* jmpa $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_jmpa0, { 0xea } + }, +/* jmpa- $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_jmpa_, { 0x1ea } + }, +/* jmpi $icond,[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } }, + & ifmt_jmpi, { 0x9c } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x3d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xad } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x2d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x4d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x5d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x6d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x7d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x8d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x9d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x2d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x3d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x8d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xfd } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x9d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xed } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xbd } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xdd } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0x1d } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xd } + }, +/* jmpr $cond,$rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } }, + & ifmt_jmpr_nenz, { 0xcd } + }, +/* jmps $hash$segm$useg8,$hash$sof$usof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } }, + & ifmt_jmpseg, { 0xfa } + }, +/* jmps $seg,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } }, + & ifmt_jmps, { 0xfa } + }, +/* jb $genreg$dot$qlobit,$relhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } }, + & ifmt_jb, { 0x8a } + }, +/* jbc $genreg$dot$qlobit,$relhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } }, + & ifmt_jb, { 0xaa } + }, +/* jnb $genreg$dot$qlobit,$relhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } }, + & ifmt_jb, { 0x9a } + }, +/* jnbs $genreg$dot$qlobit,$relhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } }, + & ifmt_jb, { 0xba } + }, +/* calla+ $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_calla0, { 0xca } + }, +/* calla $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_calla0, { 0xca } + }, +/* calla- $extcond,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } }, + & ifmt_calla_, { 0x1ca } + }, +/* calli $icond,[$sr] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } }, + & ifmt_jmpi, { 0xab } + }, +/* callr $rel */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REL), 0 } }, + & ifmt_callr, { 0xbb } + }, +/* calls $hash$segm$useg8,$hash$sof$usof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } }, + & ifmt_callseg, { 0xda } + }, +/* calls $seg,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } }, + & ifmt_jmps, { 0xda } + }, +/* pcall $reg8,$caddr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (CADDR), 0 } }, + & ifmt_pcall, { 0xe2 } + }, +/* trap $hash$uimm7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (UIMM7), 0 } }, + & ifmt_trap, { 0x9b } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0xcb } + }, +/* rets */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0xdb } + }, +/* retp $reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), 0 } }, + & ifmt_retp, { 0xeb } + }, +/* reti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_reti, { 0x88fb } + }, +/* pop $reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), 0 } }, + & ifmt_retp, { 0xfc } + }, +/* push $reg8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), 0 } }, + & ifmt_retp, { 0xec } + }, +/* scxt $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0xc6 } + }, +/* scxt $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0xd6 } + }, +/* scxt $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xd6 } + }, +/* scxt $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xd6 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0xcc } + }, +/* srst */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0xb7b748b7 } + }, +/* idle */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0x87877887 } + }, +/* pwrdn */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0x97976897 } + }, +/* diswdt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0xa5a55aa5 } + }, +/* enwdt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0x85857a85 } + }, +/* einit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0xb5b54ab5 } + }, +/* srvwdt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_srstm, { 0xa7a758a7 } + }, +/* sbrk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x8c } + }, +/* atomic $hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_atomic, { 0xd1 } + }, +/* extr $hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_atomic, { 0x80d1 } + }, +/* extp $sr,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp, { 0x40dc } + }, +/* extp $hash$pagenum,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp1, { 0x40d7 } + }, +/* extp $hash$pag$upag16,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (PAG), OP (UPAG16), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extpg1, { 0x40d7 } + }, +/* extpr $sr,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp, { 0xc0dc } + }, +/* extpr $hash$pagenum,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp1, { 0xc0d7 } + }, +/* exts $sr,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp, { 0xdc } + }, +/* exts $hash$seghi8,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_exts1, { 0xd7 } + }, +/* extsr $sr,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_extp, { 0x80dc } + }, +/* extsr $hash$seghi8,$hash$uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } }, + & ifmt_exts1, { 0x80d7 } + }, +/* prior $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x2b } + }, +/* bclr $RegNam */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGNAM), 0 } }, + & ifmt_bclr18, { 0xbe } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xe } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x1e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x2e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x3e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x4e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x5e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x6e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x7e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x8e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x9e } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xae } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xbe } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xce } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xde } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xee } + }, +/* bclr $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xfe } + }, +/* bset $RegNam */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGNAM), 0 } }, + & ifmt_bclr18, { 0xbf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x1f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x2f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x3f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x4f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x5f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x6f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x7f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x8f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0x9f } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xaf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xbf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xcf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xdf } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xef } + }, +/* bset $reg8$dot$qbit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } }, + & ifmt_bclr0, { 0xff } + }, +/* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x4a } + }, +/* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x3a } + }, +/* band $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x6a } + }, +/* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x5a } + }, +/* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x7a } + }, +/* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } }, + & ifmt_bmov, { 0x2a } + }, +/* bfldl $reg8,$hash$mask8,$hash$datahi8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASK8), ',', OP (HASH), OP (DATAHI8), 0 } }, + & ifmt_bfldl, { 0xa } + }, +/* bfldh $reg8,$hash$masklo8,$hash$data8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASKLO8), ',', OP (HASH), OP (DATA8), 0 } }, + & ifmt_bfldh, { 0x1a } + }, +/* cmp $src1,$src2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, + & ifmt_muls, { 0x40 } + }, +/* cmpb $drb,$srb */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } }, + & ifmt_addbr, { 0x41 } + }, +/* cmp $src1,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC1), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_cmpri, { 0x48 } + }, +/* cmpb $drb,$hash$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } }, + & ifmt_addbrhpag3, { 0x49 } + }, +/* cmp $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x46 } + }, +/* cmpb $regb8,$hash$uimm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } }, + & ifmt_addrbhpof, { 0x47 } + }, +/* cmp $dr,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_add2, { 0x848 } + }, +/* cmpb $drb,[$sr2] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } }, + & ifmt_addb2, { 0x849 } + }, +/* cmp $dr,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_add2, { 0xc48 } + }, +/* cmpb $drb,[$sr2+] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } }, + & ifmt_addb2, { 0xc49 } + }, +/* cmp $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x42 } + }, +/* cmpb $regb8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addbrpof, { 0x43 } + }, +/* cmp $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x42 } + }, +/* cmp $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x42 } + }, +/* cmpb $regbmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addbrm2, { 0x43 } + }, +/* cmpb $regb8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } }, + & ifmt_addbrm, { 0x43 } + }, +/* cmpd1 $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0xa0 } + }, +/* cmpd2 $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0xb0 } + }, +/* cmpi1 $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x80 } + }, +/* cmpi2 $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x90 } + }, +/* cmpd1 $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0xa6 } + }, +/* cmpd2 $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0xb6 } + }, +/* cmpi1 $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x86 } + }, +/* cmpi2 $reg8,$hash$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } }, + & ifmt_addrhpof, { 0x96 } + }, +/* cmpd1 $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0xa2 } + }, +/* cmpd2 $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0xb2 } + }, +/* cmpi1 $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x82 } + }, +/* cmpi2 $reg8,$pof$upof16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } }, + & ifmt_addrpof, { 0x92 } + }, +/* cmpd1 $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xa2 } + }, +/* cmpd2 $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0xb2 } + }, +/* cmpi1 $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x82 } + }, +/* cmpi2 $regmem8,$memgr8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } }, + & ifmt_addrm2, { 0x92 } + }, +/* cmpd1 $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xa2 } + }, +/* cmpd2 $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0xb2 } + }, +/* cmpi1 $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x82 } + }, +/* cmpi2 $reg8,$memory */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } }, + & ifmt_addrm, { 0x92 } + }, +/* shl $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x4c } + }, +/* shr $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x6c } + }, +/* rol $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0xc } + }, +/* ror $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0x2c } + }, +/* ashr $dr,$sr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, + & ifmt_addr, { 0xac } + }, +/* shl $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x5c } + }, +/* shr $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x7c } + }, +/* rol $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x1c } + }, +/* ror $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0x3c } + }, +/* ashr $sr,$hash$uimm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } }, + & ifmt_cmpd1ri, { 0xbc } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & xc16x_cgen_ifld_table[XC16X_##f] +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) XC16X_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE xc16x_cgen_macro_insn_table[] = +{ +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE xc16x_cgen_macro_insn_opcode_table[] = +{ +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +xc16x_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (xc16x_cgen_macro_insn_table) / + sizeof (xc16x_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & xc16x_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & xc16x_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + /* This test has been added to avoid a warning generated + if memset is called with a third argument of value zero. */ + if (num_macros >= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + xc16x_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & xc16x_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + xc16x_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/xc16x-opc.h b/external/gpl3/gdb/dist/opcodes/xc16x-opc.h new file mode 100644 index 000000000000..2eb47036c654 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xc16x-opc.h @@ -0,0 +1,225 @@ +/* Instruction opcode header for xc16x. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef XC16X_OPC_H +#define XC16X_OPC_H + +/* -- opc.h */ + +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE) + +/* -- */ +/* Enum declaration for xc16x instruction types. */ +typedef enum cgen_insn_type { + XC16X_INSN_INVALID, XC16X_INSN_ADDRPOF, XC16X_INSN_SUBRPOF, XC16X_INSN_ADDBRPOF + , XC16X_INSN_SUBBRPOF, XC16X_INSN_ADDRPAG, XC16X_INSN_SUBRPAG, XC16X_INSN_ADDBRPAG + , XC16X_INSN_SUBBRPAG, XC16X_INSN_ADDCRPOF, XC16X_INSN_SUBCRPOF, XC16X_INSN_ADDCBRPOF + , XC16X_INSN_SUBCBRPOF, XC16X_INSN_ADDCRPAG, XC16X_INSN_SUBCRPAG, XC16X_INSN_ADDCBRPAG + , XC16X_INSN_SUBCBRPAG, XC16X_INSN_ADDRPOFR, XC16X_INSN_SUBRPOFR, XC16X_INSN_ADDBRPOFR + , XC16X_INSN_SUBBRPOFR, XC16X_INSN_ADDCRPOFR, XC16X_INSN_SUBCRPOFR, XC16X_INSN_ADDCBRPOFR + , XC16X_INSN_SUBCBRPOFR, XC16X_INSN_ADDRHPOF, XC16X_INSN_SUBRHPOF, XC16X_INSN_ADDBRHPOF + , XC16X_INSN_SUBBRHPOF, XC16X_INSN_ADDRHPOF3, XC16X_INSN_SUBRHPOF3, XC16X_INSN_ADDBRHPAG3 + , XC16X_INSN_SUBBRHPAG3, XC16X_INSN_ADDRHPAG3, XC16X_INSN_SUBRHPAG3, XC16X_INSN_ADDBRHPOF3 + , XC16X_INSN_SUBBRHPOF3, XC16X_INSN_ADDRBHPOF, XC16X_INSN_SUBRBHPOF, XC16X_INSN_ADDBRHPAG + , XC16X_INSN_SUBBRHPAG, XC16X_INSN_ADDCRHPOF, XC16X_INSN_SUBCRHPOF, XC16X_INSN_ADDCBRHPOF + , XC16X_INSN_SUBCBRHPOF, XC16X_INSN_ADDCRHPOF3, XC16X_INSN_SUBCRHPOF3, XC16X_INSN_ADDCBRHPAG3 + , XC16X_INSN_SUBCBRHPAG3, XC16X_INSN_ADDCRHPAG3, XC16X_INSN_SUBCRHPAG3, XC16X_INSN_ADDCBRHPOF3 + , XC16X_INSN_SUBCBRHPOF3, XC16X_INSN_ADDCRBHPOF, XC16X_INSN_SUBCRBHPOF, XC16X_INSN_ADDCBRHPAG + , XC16X_INSN_SUBCBRHPAG, XC16X_INSN_ADDRI, XC16X_INSN_SUBRI, XC16X_INSN_ADDBRI + , XC16X_INSN_SUBBRI, XC16X_INSN_ADDRIM, XC16X_INSN_SUBRIM, XC16X_INSN_ADDBRIM + , XC16X_INSN_SUBBRIM, XC16X_INSN_ADDCRI, XC16X_INSN_SUBCRI, XC16X_INSN_ADDCBRI + , XC16X_INSN_SUBCBRI, XC16X_INSN_ADDCRIM, XC16X_INSN_SUBCRIM, XC16X_INSN_ADDCBRIM + , XC16X_INSN_SUBCBRIM, XC16X_INSN_ADDR, XC16X_INSN_SUBR, XC16X_INSN_ADDBR + , XC16X_INSN_SUBBR, XC16X_INSN_ADD2, XC16X_INSN_SUB2, XC16X_INSN_ADDB2 + , XC16X_INSN_SUBB2, XC16X_INSN_ADD2I, XC16X_INSN_SUB2I, XC16X_INSN_ADDB2I + , XC16X_INSN_SUBB2I, XC16X_INSN_ADDCR, XC16X_INSN_SUBCR, XC16X_INSN_ADDBCR + , XC16X_INSN_SUBBCR, XC16X_INSN_ADDCR2, XC16X_INSN_SUBCR2, XC16X_INSN_ADDBCR2 + , XC16X_INSN_SUBBCR2, XC16X_INSN_ADDCR2I, XC16X_INSN_SUBCR2I, XC16X_INSN_ADDBCR2I + , XC16X_INSN_SUBBCR2I, XC16X_INSN_ADDRM2, XC16X_INSN_ADDRM3, XC16X_INSN_ADDRM + , XC16X_INSN_ADDRM1, XC16X_INSN_SUBRM3, XC16X_INSN_SUBRM2, XC16X_INSN_SUBRM1 + , XC16X_INSN_SUBRM, XC16X_INSN_ADDBRM2, XC16X_INSN_ADDBRM3, XC16X_INSN_ADDBRM + , XC16X_INSN_ADDBRM1, XC16X_INSN_SUBBRM3, XC16X_INSN_SUBBRM2, XC16X_INSN_SUBBRM1 + , XC16X_INSN_SUBBRM, XC16X_INSN_ADDCRM2, XC16X_INSN_ADDCRM3, XC16X_INSN_ADDCRM + , XC16X_INSN_ADDCRM1, XC16X_INSN_SUBCRM3, XC16X_INSN_SUBCRM2, XC16X_INSN_SUBCRM1 + , XC16X_INSN_SUBCRM, XC16X_INSN_ADDCBRM2, XC16X_INSN_ADDCBRM3, XC16X_INSN_ADDCBRM + , XC16X_INSN_ADDCBRM1, XC16X_INSN_SUBCBRM3, XC16X_INSN_SUBCBRM2, XC16X_INSN_SUBCBRM1 + , XC16X_INSN_SUBCBRM, XC16X_INSN_MULS, XC16X_INSN_MULU, XC16X_INSN_DIV + , XC16X_INSN_DIVL, XC16X_INSN_DIVLU, XC16X_INSN_DIVU, XC16X_INSN_CPL + , XC16X_INSN_CPLB, XC16X_INSN_NEG, XC16X_INSN_NEGB, XC16X_INSN_ANDR + , XC16X_INSN_ORR, XC16X_INSN_XORR, XC16X_INSN_ANDBR, XC16X_INSN_ORBR + , XC16X_INSN_XORBR, XC16X_INSN_ANDRI, XC16X_INSN_ORRI, XC16X_INSN_XORRI + , XC16X_INSN_ANDBRI, XC16X_INSN_ORBRI, XC16X_INSN_XORBRI, XC16X_INSN_ANDRIM + , XC16X_INSN_ORRIM, XC16X_INSN_XORRIM, XC16X_INSN_ANDBRIM, XC16X_INSN_ORBRIM + , XC16X_INSN_XORBRIM, XC16X_INSN_AND2, XC16X_INSN_OR2, XC16X_INSN_XOR2 + , XC16X_INSN_ANDB2, XC16X_INSN_ORB2, XC16X_INSN_XORB2, XC16X_INSN_AND2I + , XC16X_INSN_OR2I, XC16X_INSN_XOR2I, XC16X_INSN_ANDB2I, XC16X_INSN_ORB2I + , XC16X_INSN_XORB2I, XC16X_INSN_ANDPOFR, XC16X_INSN_ORPOFR, XC16X_INSN_XORPOFR + , XC16X_INSN_ANDBPOFR, XC16X_INSN_ORBPOFR, XC16X_INSN_XORBPOFR, XC16X_INSN_ANDRPOFR + , XC16X_INSN_ORRPOFR, XC16X_INSN_XORRPOFR, XC16X_INSN_ANDBRPOFR, XC16X_INSN_ORBRPOFR + , XC16X_INSN_XORBRPOFR, XC16X_INSN_ANDRM2, XC16X_INSN_ANDRM3, XC16X_INSN_ANDRM + , XC16X_INSN_ANDRM1, XC16X_INSN_ORRM3, XC16X_INSN_ORRM2, XC16X_INSN_ORRM1 + , XC16X_INSN_ORRM, XC16X_INSN_XORRM3, XC16X_INSN_XORRM2, XC16X_INSN_XORRM1 + , XC16X_INSN_XORRM, XC16X_INSN_ANDBRM2, XC16X_INSN_ANDBRM3, XC16X_INSN_ANDBRM + , XC16X_INSN_ANDBRM1, XC16X_INSN_ORBRM3, XC16X_INSN_ORBRM2, XC16X_INSN_ORBRM1 + , XC16X_INSN_ORBRM, XC16X_INSN_XORBRM3, XC16X_INSN_XORBRM2, XC16X_INSN_XORBRM1 + , XC16X_INSN_XORBRM, XC16X_INSN_MOVR, XC16X_INSN_MOVRB, XC16X_INSN_MOVRI + , XC16X_INSN_MOVBRI, XC16X_INSN_MOVI, XC16X_INSN_MOVBI, XC16X_INSN_MOVR2 + , XC16X_INSN_MOVBR2, XC16X_INSN_MOVRI2, XC16X_INSN_MOVBRI2, XC16X_INSN_MOVRI3 + , XC16X_INSN_MOVBRI3, XC16X_INSN_MOV2I, XC16X_INSN_MOVB2I, XC16X_INSN_MOV6I + , XC16X_INSN_MOVB6I, XC16X_INSN_MOV7I, XC16X_INSN_MOVB7I, XC16X_INSN_MOV8I + , XC16X_INSN_MOVB8I, XC16X_INSN_MOV9I, XC16X_INSN_MOVB9I, XC16X_INSN_MOV10I + , XC16X_INSN_MOVB10I, XC16X_INSN_MOVRI11, XC16X_INSN_MOVBRI11, XC16X_INSN_MOVRI12 + , XC16X_INSN_MOVBRI12, XC16X_INSN_MOVEHM5, XC16X_INSN_MOVEHM6, XC16X_INSN_MOVEHM7 + , XC16X_INSN_MOVEHM8, XC16X_INSN_MOVEHM9, XC16X_INSN_MOVEHM10, XC16X_INSN_MOVRMP + , XC16X_INSN_MOVRMP1, XC16X_INSN_MOVRMP2, XC16X_INSN_MOVRMP3, XC16X_INSN_MOVRMP4 + , XC16X_INSN_MOVRMP5, XC16X_INSN_MOVEHM1, XC16X_INSN_MOVEHM2, XC16X_INSN_MOVEHM3 + , XC16X_INSN_MOVEHM4, XC16X_INSN_MVE12, XC16X_INSN_MVE13, XC16X_INSN_MOVER12 + , XC16X_INSN_MVR13, XC16X_INSN_MVER12, XC16X_INSN_MVER13, XC16X_INSN_MOVR12 + , XC16X_INSN_MOVR13, XC16X_INSN_MOVBSRR, XC16X_INSN_MOVBZRR, XC16X_INSN_MOVBSRPOFM + , XC16X_INSN_MOVBSPOFMR, XC16X_INSN_MOVBZRPOFM, XC16X_INSN_MOVBZPOFMR, XC16X_INSN_MOVEBS14 + , XC16X_INSN_MOVEBS15, XC16X_INSN_MOVERBS14, XC16X_INSN_MOVRBS15, XC16X_INSN_MOVEBZ14 + , XC16X_INSN_MOVEBZ15, XC16X_INSN_MOVERBZ14, XC16X_INSN_MOVRBZ15, XC16X_INSN_MOVRBS + , XC16X_INSN_MOVRBZ, XC16X_INSN_JMPA0, XC16X_INSN_JMPA1, XC16X_INSN_JMPA_ + , XC16X_INSN_JMPI, XC16X_INSN_JMPR_NENZ, XC16X_INSN_JMPR_SGT, XC16X_INSN_JMPR_Z + , XC16X_INSN_JMPR_V, XC16X_INSN_JMPR_NV, XC16X_INSN_JMPR_N, XC16X_INSN_JMPR_NN + , XC16X_INSN_JMPR_C, XC16X_INSN_JMPR_NC, XC16X_INSN_JMPR_EQ, XC16X_INSN_JMPR_NE + , XC16X_INSN_JMPR_ULT, XC16X_INSN_JMPR_ULE, XC16X_INSN_JMPR_UGE, XC16X_INSN_JMPR_UGT + , XC16X_INSN_JMPR_SLE, XC16X_INSN_JMPR_SGE, XC16X_INSN_JMPR_NET, XC16X_INSN_JMPR_UC + , XC16X_INSN_JMPR_SLT, XC16X_INSN_JMPSEG, XC16X_INSN_JMPS, XC16X_INSN_JB + , XC16X_INSN_JBC, XC16X_INSN_JNB, XC16X_INSN_JNBS, XC16X_INSN_CALLA0 + , XC16X_INSN_CALLA1, XC16X_INSN_CALLA_, XC16X_INSN_CALLI, XC16X_INSN_CALLR + , XC16X_INSN_CALLSEG, XC16X_INSN_CALLS, XC16X_INSN_PCALL, XC16X_INSN_TRAP + , XC16X_INSN_RET, XC16X_INSN_RETS, XC16X_INSN_RETP, XC16X_INSN_RETI + , XC16X_INSN_POP, XC16X_INSN_PUSH, XC16X_INSN_SCXTI, XC16X_INSN_SCXTRPOFM + , XC16X_INSN_SCXTMG, XC16X_INSN_SCXTM, XC16X_INSN_NOP, XC16X_INSN_SRSTM + , XC16X_INSN_IDLEM, XC16X_INSN_PWRDNM, XC16X_INSN_DISWDTM, XC16X_INSN_ENWDTM + , XC16X_INSN_EINITM, XC16X_INSN_SRVWDTM, XC16X_INSN_SBRK, XC16X_INSN_ATOMIC + , XC16X_INSN_EXTR, XC16X_INSN_EXTP, XC16X_INSN_EXTP1, XC16X_INSN_EXTPG1 + , XC16X_INSN_EXTPR, XC16X_INSN_EXTPR1, XC16X_INSN_EXTS, XC16X_INSN_EXTS1 + , XC16X_INSN_EXTSR, XC16X_INSN_EXTSR1, XC16X_INSN_PRIOR, XC16X_INSN_BCLR18 + , XC16X_INSN_BCLR0, XC16X_INSN_BCLR1, XC16X_INSN_BCLR2, XC16X_INSN_BCLR3 + , XC16X_INSN_BCLR4, XC16X_INSN_BCLR5, XC16X_INSN_BCLR6, XC16X_INSN_BCLR7 + , XC16X_INSN_BCLR8, XC16X_INSN_BCLR9, XC16X_INSN_BCLR10, XC16X_INSN_BCLR11 + , XC16X_INSN_BCLR12, XC16X_INSN_BCLR13, XC16X_INSN_BCLR14, XC16X_INSN_BCLR15 + , XC16X_INSN_BSET19, XC16X_INSN_BSET0, XC16X_INSN_BSET1, XC16X_INSN_BSET2 + , XC16X_INSN_BSET3, XC16X_INSN_BSET4, XC16X_INSN_BSET5, XC16X_INSN_BSET6 + , XC16X_INSN_BSET7, XC16X_INSN_BSET8, XC16X_INSN_BSET9, XC16X_INSN_BSET10 + , XC16X_INSN_BSET11, XC16X_INSN_BSET12, XC16X_INSN_BSET13, XC16X_INSN_BSET14 + , XC16X_INSN_BSET15, XC16X_INSN_BMOV, XC16X_INSN_BMOVN, XC16X_INSN_BAND + , XC16X_INSN_BOR, XC16X_INSN_BXOR, XC16X_INSN_BCMP, XC16X_INSN_BFLDL + , XC16X_INSN_BFLDH, XC16X_INSN_CMPR, XC16X_INSN_CMPBR, XC16X_INSN_CMPRI + , XC16X_INSN_CMPBRI, XC16X_INSN_CMPI, XC16X_INSN_CMPBI, XC16X_INSN_CMPR2 + , XC16X_INSN_CMPBR2, XC16X_INSN_CMP2I, XC16X_INSN_CMPB2I, XC16X_INSN_CMP04 + , XC16X_INSN_CMPB4, XC16X_INSN_CMP004, XC16X_INSN_CMP0004, XC16X_INSN_CMPB04 + , XC16X_INSN_CMPB004, XC16X_INSN_CMPD1RI, XC16X_INSN_CMPD2RI, XC16X_INSN_CMPI1RI + , XC16X_INSN_CMPI2RI, XC16X_INSN_CMPD1RIM, XC16X_INSN_CMPD2RIM, XC16X_INSN_CMPI1RIM + , XC16X_INSN_CMPI2RIM, XC16X_INSN_CMPD1RP, XC16X_INSN_CMPD2RP, XC16X_INSN_CMPI1RP + , XC16X_INSN_CMPI2RP, XC16X_INSN_CMPD1RM, XC16X_INSN_CMPD2RM, XC16X_INSN_CMPI1RM + , XC16X_INSN_CMPI2RM, XC16X_INSN_CMPD1RMI, XC16X_INSN_CMPD2RMI, XC16X_INSN_CMPI1RMI + , XC16X_INSN_CMPI2RMI, XC16X_INSN_SHLR, XC16X_INSN_SHRR, XC16X_INSN_ROLR + , XC16X_INSN_RORR, XC16X_INSN_ASHRR, XC16X_INSN_SHLRI, XC16X_INSN_SHRRI + , XC16X_INSN_ROLRI, XC16X_INSN_RORRI, XC16X_INSN_ASHRRI +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID XC16X_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) XC16X_INSN_ASHRRI + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_op1; + long f_op2; + long f_condcode; + long f_icondcode; + long f_rcond; + long f_qcond; + long f_extccode; + long f_r0; + long f_r1; + long f_r2; + long f_r3; + long f_r4; + long f_uimm2; + long f_uimm3; + long f_uimm4; + long f_uimm7; + long f_uimm8; + long f_uimm16; + long f_memory; + long f_memgr8; + long f_rel8; + long f_relhi8; + long f_reg8; + long f_regmem8; + long f_regoff8; + long f_reghi8; + long f_regb8; + long f_seg8; + long f_segnum8; + long f_mask8; + long f_pagenum; + long f_datahi8; + long f_data8; + long f_offset16; + long f_op_bit1; + long f_op_bit2; + long f_op_bit4; + long f_op_bit3; + long f_op_2bit; + long f_op_bitone; + long f_op_onebit; + long f_op_1bit; + long f_op_lbit4; + long f_op_lbit2; + long f_op_bit8; + long f_op_bit16; + long f_qbit; + long f_qlobit; + long f_qhibit; + long f_qlobit2; + long f_pof; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* XC16X_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-asm.c b/external/gpl3/gdb/dist/opcodes/xstormy16-asm.c new file mode 100644 index 000000000000..1191c64221f6 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-asm.c @@ -0,0 +1,684 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +/* The machine-independent code doesn't know how to disambiguate + mov (foo),r3 + and + mov (r2),r3 + where 'foo' is a label. This helps it out. */ + +static const char * +parse_mem8 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + if (**strp == '(') + { + const char *s = *strp; + + if (s[1] == '-' && s[2] == '-') + return _("Bad register in preincrement"); + + while (ISALNUM (*++s)) + ; + if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ',')) + return _("Bad register in postincrement"); + if (s[0] == ',' || s[0] == ')') + return _("Bad register name"); + } + else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, + (long *) valuep) == NULL) + return _("Label conflicts with register name"); + else if (strncasecmp (*strp, "rx,", 3) == 0 + || strncasecmp (*strp, "rxl,", 3) == 0 + || strncasecmp (*strp, "rxh,", 3) == 0) + return _("Label conflicts with `Rx'"); + else if (**strp == '#') + return _("Bad immediate expression"); + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* For the add and subtract instructions, there are two immediate forms, + one for small operands and one for large ones. We want to use + the small one when possible, but we do not want to generate relocs + of the small size. This is somewhat tricky. */ + +static const char * +parse_small_immediate (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + bfd_vma value; + enum cgen_parse_operand_result result; + const char *errmsg; + + if (**strp == '@') + return _("No relocation for small immediate"); + + errmsg = (* cd->parse_operand_fn) + (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, + & result, & value); + + if (errmsg) + return errmsg; + + if (result != CGEN_PARSE_OPERAND_RESULT_NUMBER) + return _("Small operand was not an immediate number"); + + *valuep = value; + return NULL; +} + +/* Literal scan be either a normal literal, a @hi() or @lo relocation. */ + +static const char * +parse_immediate16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + if (strncmp (*strp, "@hi(", 4) == 0) + { + *strp += 4; + code = BFD_RELOC_HI16; + } + else + if (strncmp (*strp, "@lo(", 4) == 0) + { + *strp += 4; + code = BFD_RELOC_LO16; + } + + if (code == BFD_RELOC_NONE) + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + else + { + errmsg = cgen_parse_address (cd, strp, opindex, code, &result, &value); + if ((errmsg == NULL) && + (result != CGEN_PARSE_OPERAND_RESULT_QUEUED)) + errmsg = _("Operand is not a symbol"); + + *valuep = value; + if ((code == BFD_RELOC_HI16 || code == BFD_RELOC_LO16) + && **strp == ')') + *strp += 1; + else + { + errmsg = _("Syntax error: No trailing ')'"); + return errmsg; + } + } + return errmsg; +} +/* -- */ + +const char * xstormy16_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +xstormy16_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_Rb_names, & fields->f_Rb); + break; + case XSTORMY16_OPERAND_RBJ : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_Rb_names, & fields->f_Rbj); + break; + case XSTORMY16_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rd); + break; + case XSTORMY16_OPERAND_RDM : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rdm); + break; + case XSTORMY16_OPERAND_RM : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rm); + break; + case XSTORMY16_OPERAND_RS : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, & fields->f_Rs); + break; + case XSTORMY16_OPERAND_ABS24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_ABS24, (unsigned long *) (& fields->f_abs24)); + break; + case XSTORMY16_OPERAND_BCOND2 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op2); + break; + case XSTORMY16_OPERAND_BCOND5 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_branchcond, & fields->f_op5); + break; + case XSTORMY16_OPERAND_HMEM8 : + errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_HMEM8, (unsigned long *) (& fields->f_hmem8)); + break; + case XSTORMY16_OPERAND_IMM12 : + errmsg = cgen_parse_signed_integer (cd, strp, XSTORMY16_OPERAND_IMM12, (long *) (& fields->f_imm12)); + break; + case XSTORMY16_OPERAND_IMM16 : + errmsg = parse_immediate16 (cd, strp, XSTORMY16_OPERAND_IMM16, (unsigned long *) (& fields->f_imm16)); + break; + case XSTORMY16_OPERAND_IMM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM2, (unsigned long *) (& fields->f_imm2)); + break; + case XSTORMY16_OPERAND_IMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3, (unsigned long *) (& fields->f_imm3)); + break; + case XSTORMY16_OPERAND_IMM3B : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM3B, (unsigned long *) (& fields->f_imm3b)); + break; + case XSTORMY16_OPERAND_IMM4 : + errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM4, (unsigned long *) (& fields->f_imm4)); + break; + case XSTORMY16_OPERAND_IMM8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_IMM8, (unsigned long *) (& fields->f_imm8)); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + errmsg = parse_small_immediate (cd, strp, XSTORMY16_OPERAND_IMM8SMALL, (unsigned long *) (& fields->f_imm8)); + break; + case XSTORMY16_OPERAND_LMEM8 : + errmsg = parse_mem8 (cd, strp, XSTORMY16_OPERAND_LMEM8, (unsigned long *) (& fields->f_lmem8)); + break; + case XSTORMY16_OPERAND_REL12 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12, (unsigned long *) (& fields->f_rel12)); + break; + case XSTORMY16_OPERAND_REL12A : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL12A, (unsigned long *) (& fields->f_rel12a)); + break; + case XSTORMY16_OPERAND_REL8_2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_2, (unsigned long *) (& fields->f_rel8_2)); + break; + case XSTORMY16_OPERAND_REL8_4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, XSTORMY16_OPERAND_REL8_4, (unsigned long *) (& fields->f_rel8_4)); + break; + case XSTORMY16_OPERAND_WS2 : + errmsg = cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_h_wordsize, & fields->f_op2m); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const xstormy16_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +xstormy16_cgen_init_asm (CGEN_CPU_DESC cd) +{ + xstormy16_cgen_init_opcode_table (cd); + xstormy16_cgen_init_ibld_table (cd); + cd->parse_handlers = & xstormy16_cgen_parse_handlers[0]; + cd->parse_operand = xstormy16_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by xstormy16_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +xstormy16_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +xstormy16_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! xstormy16_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-desc.c b/external/gpl3/gdb/dist/opcodes/xstormy16-desc.c new file mode 100644 index 000000000000..902e9bc79ab5 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-desc.c @@ -0,0 +1,1479 @@ +/* CPU data for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "xstormy16", MACH_XSTORMY16 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "xstormy16", ISA_XSTORMY16 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA xstormy16_cgen_isa_table[] = { + { "xstormy16", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH xstormy16_cgen_mach_table[] = { + { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_gr_names = +{ + & xstormy16_cgen_opval_gr_names_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] = +{ + { "r8", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "psw", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = +{ + & xstormy16_cgen_opval_gr_Rb_names_entries[0], + 10, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] = +{ + { "ge", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "hi", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "pl", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "nv", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "mi", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "v", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = +{ + & xstormy16_cgen_opval_h_branchcond_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] = +{ + { ".b", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".w", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = +{ + & xstormy16_cgen_opval_h_wordsize_entries[0], + 3, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & xstormy16_cgen_ifld_table[0]; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */ + +static void +xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = xstormy16_cgen_rebuild_tables; + xstormy16_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-desc.h b/external/gpl3/gdb/dist/opcodes/xstormy16-desc.h new file mode 100644 index 000000000000..edd9f801cf66 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-desc.h @@ -0,0 +1,329 @@ +/* CPU data header for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef XSTORMY16_CPU_H +#define XSTORMY16_CPU_H + +#define CGEN_ARCH xstormy16 + +/* Given symbol S, return xstormy16_cgen_. */ +#define CGEN_SYM(s) xstormy16##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_XSTORMY16 + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 + , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 + , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 + , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 + , H_GR_PSW = 14, H_GR_SP = 15 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum gr_rb_names { + H_RBJ_R8 = 0, H_RBJ_R9 = 1, H_RBJ_R10 = 2, H_RBJ_R11 = 3 + , H_RBJ_R12 = 4, H_RBJ_R13 = 5, H_RBJ_R14 = 6, H_RBJ_R15 = 7 + , H_RBJ_PSW = 6, H_RBJ_SP = 7 +} GR_RB_NAMES; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op1 { + OP1_0, OP1_1, OP1_2, OP1_3 + , OP1_4, OP1_5, OP1_6, OP1_7 + , OP1_8, OP1_9, OP1_A, OP1_B + , OP1_C, OP1_D, OP1_E, OP1_F +} INSN_OP1; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2 { + OP2_0, OP2_1, OP2_2, OP2_3 + , OP2_4, OP2_5, OP2_6, OP2_7 + , OP2_8, OP2_9, OP2_A, OP2_B + , OP2_C, OP2_D, OP2_E, OP2_F +} INSN_OP2; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2a { + OP2A_0, OP2A_2, OP2A_4, OP2A_6 + , OP2A_8, OP2A_A, OP2A_C, OP2A_E +} INSN_OP2A; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op2m { + OP2M_0, OP2M_1 +} INSN_OP2M; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3 { + OP3_0, OP3_1, OP3_2, OP3_3 + , OP3_4, OP3_5, OP3_6, OP3_7 + , OP3_8, OP3_9, OP3_A, OP3_B + , OP3_C, OP3_D, OP3_E, OP3_F +} INSN_OP3; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3a { + OP3A_0, OP3A_1, OP3A_2, OP3A_3 +} INSN_OP3A; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op3b { + OP3B_0, OP3B_2, OP3B_4, OP3B_6 + , OP3B_8, OP3B_A, OP3B_C, OP3B_E +} INSN_OP3B; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4 { + OP4_0, OP4_1, OP4_2, OP4_3 + , OP4_4, OP4_5, OP4_6, OP4_7 + , OP4_8, OP4_9, OP4_A, OP4_B + , OP4_C, OP4_D, OP4_E, OP4_F +} INSN_OP4; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4m { + OP4M_0, OP4M_1 +} INSN_OP4M; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op4b { + OP4B_0, OP4B_1 +} INSN_OP4B; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op5 { + OP5_0, OP5_1, OP5_2, OP5_3 + , OP5_4, OP5_5, OP5_6, OP5_7 + , OP5_8, OP5_9, OP5_A, OP5_B + , OP5_C, OP5_D, OP5_E, OP5_F +} INSN_OP5; + +/* Enum declaration for insn op enums. */ +typedef enum insn_op5a { + OP5A_0, OP5A_1 +} INSN_OP5A; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_XSTORMY16, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_XSTORMY16, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for xstormy16 ifield types. */ +typedef enum ifield_type { + XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM + , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ + , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M + , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4 + , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A + , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B + , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16 + , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4 + , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2 + , XSTORMY16_F_ABS24, XSTORMY16_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) XSTORMY16_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for xstormy16 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB + , HW_H_RBJ, HW_H_RPSW, HW_H_Z8, HW_H_Z16 + , HW_H_CY, HW_H_HC, HW_H_OV, HW_H_PT + , HW_H_S, HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for xstormy16 operand types. */ +typedef enum cgen_operand_type { + XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY + , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S + , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS + , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2 + , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B + , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12 + , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2 + , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24 + , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0 + , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 39 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld xstormy16_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names; +extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond; +extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize; + +extern const CGEN_HW_ENTRY xstormy16_cgen_hw_table[]; + + + +#endif /* XSTORMY16_CPU_H */ diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-dis.c b/external/gpl3/gdb/dist/opcodes/xstormy16-dis.c new file mode 100644 index 000000000000..af81ab488c26 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-dis.c @@ -0,0 +1,589 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + + +void xstormy16_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +xstormy16_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0); + break; + case XSTORMY16_OPERAND_RBJ : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0); + break; + case XSTORMY16_OPERAND_RD : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0); + break; + case XSTORMY16_OPERAND_RDM : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0); + break; + case XSTORMY16_OPERAND_RM : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0); + break; + case XSTORMY16_OPERAND_RS : + print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0); + break; + case XSTORMY16_OPERAND_ABS24 : + print_normal (cd, info, fields->f_abs24, 0|(1<f_op2, 0); + break; + case XSTORMY16_OPERAND_BCOND5 : + print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0); + break; + case XSTORMY16_OPERAND_HMEM8 : + print_normal (cd, info, fields->f_hmem8, 0|(1<f_imm12, 0|(1<f_imm16, 0|(1<f_imm2, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM3 : + print_normal (cd, info, fields->f_imm3, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM3B : + print_normal (cd, info, fields->f_imm3b, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM4 : + print_normal (cd, info, fields->f_imm4, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM8 : + print_normal (cd, info, fields->f_imm8, 0, pc, length); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + print_normal (cd, info, fields->f_imm8, 0, pc, length); + break; + case XSTORMY16_OPERAND_LMEM8 : + print_normal (cd, info, fields->f_lmem8, 0|(1<f_rel12, 0|(1<f_rel12a, 0|(1<f_rel8_2, 0|(1<f_rel8_4, 0|(1<f_op2m, 0); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const xstormy16_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +xstormy16_cgen_init_dis (CGEN_CPU_DESC cd) +{ + xstormy16_cgen_init_opcode_table (cd); + xstormy16_cgen_init_ibld_table (cd); + cd->print_handlers = & xstormy16_cgen_print_handlers[0]; + cd->print_operand = xstormy16_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! xstormy16_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_xstormy16 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + xstormy16_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-ibld.c b/external/gpl3/gdb/dist/opcodes/xstormy16-ibld.c new file mode 100644 index 000000000000..caae89ba34e0 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-ibld.c @@ -0,0 +1,1232 @@ +/* Instruction building/extraction support for xstormy16. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * xstormy16_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +xstormy16_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + errmsg = insert_normal (cd, fields->f_Rb, 0, 0, 17, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RBJ : + errmsg = insert_normal (cd, fields->f_Rbj, 0, 0, 11, 1, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RD : + errmsg = insert_normal (cd, fields->f_Rd, 0, 0, 12, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RDM : + errmsg = insert_normal (cd, fields->f_Rdm, 0, 0, 13, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RM : + errmsg = insert_normal (cd, fields->f_Rm, 0, 0, 4, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_RS : + errmsg = insert_normal (cd, fields->f_Rs, 0, 0, 8, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_ABS24 : + { +{ + FLD (f_abs24_1) = ((FLD (f_abs24)) & (255)); + FLD (f_abs24_2) = ((UINT) (FLD (f_abs24)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_abs24_1, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_abs24_2, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case XSTORMY16_OPERAND_BCOND2 : + errmsg = insert_normal (cd, fields->f_op2, 0, 0, 4, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_BCOND5 : + errmsg = insert_normal (cd, fields->f_op5, 0, 0, 16, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_HMEM8 : + { + long value = fields->f_hmem8; + value = ((value) - (32512)); + errmsg = insert_normal (cd, value, 0|(1<f_imm12, 0|(1<f_imm16, 0|(1<f_imm2, 0, 0, 10, 2, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM3 : + errmsg = insert_normal (cd, fields->f_imm3, 0, 0, 4, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM3B : + errmsg = insert_normal (cd, fields->f_imm3b, 0, 0, 17, 3, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM4 : + errmsg = insert_normal (cd, fields->f_imm4, 0, 0, 8, 4, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM8 : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case XSTORMY16_OPERAND_LMEM8 : + errmsg = insert_normal (cd, fields->f_lmem8, 0|(1<f_rel12; + value = ((value) - (((pc) + (4)))); + errmsg = insert_normal (cd, value, 0|(1<f_rel12a; + value = ((SI) (((value) - (((pc) + (2))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<f_rel8_2; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_rel8_4; + value = ((value) - (((pc) + (4)))); + errmsg = insert_normal (cd, value, 0|(1<f_op2m, 0, 0, 7, 1, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int xstormy16_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +xstormy16_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_Rb); + break; + case XSTORMY16_OPERAND_RBJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_Rbj); + break; + case XSTORMY16_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_Rd); + break; + case XSTORMY16_OPERAND_RDM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_Rdm); + break; + case XSTORMY16_OPERAND_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_Rm); + break; + case XSTORMY16_OPERAND_RS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_Rs); + break; + case XSTORMY16_OPERAND_ABS24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_abs24_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_abs24_2); + if (length <= 0) break; + FLD (f_abs24) = ((((FLD (f_abs24_2)) << (8))) | (FLD (f_abs24_1))); + } + break; + case XSTORMY16_OPERAND_BCOND2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_op2); + break; + case XSTORMY16_OPERAND_BCOND5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 4, 32, total_length, pc, & fields->f_op5); + break; + case XSTORMY16_OPERAND_HMEM8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_hmem8 = value; + } + break; + case XSTORMY16_OPERAND_IMM12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm12); + break; + case XSTORMY16_OPERAND_IMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16); + break; + case XSTORMY16_OPERAND_IMM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_imm2); + break; + case XSTORMY16_OPERAND_IMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_imm3); + break; + case XSTORMY16_OPERAND_IMM3B : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_imm3b); + break; + case XSTORMY16_OPERAND_IMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_imm4); + break; + case XSTORMY16_OPERAND_IMM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8); + break; + case XSTORMY16_OPERAND_IMM8SMALL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_imm8); + break; + case XSTORMY16_OPERAND_LMEM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lmem8); + break; + case XSTORMY16_OPERAND_REL12 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12 = value; + } + break; + case XSTORMY16_OPERAND_REL12A : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel12a = value; + } + break; + case XSTORMY16_OPERAND_REL8_2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel8_2 = value; + } + break; + case XSTORMY16_OPERAND_REL8_4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_rel8_4 = value; + } + break; + case XSTORMY16_OPERAND_WS2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_op2m); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const xstormy16_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const xstormy16_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int xstormy16_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +xstormy16_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + value = fields->f_Rb; + break; + case XSTORMY16_OPERAND_RBJ : + value = fields->f_Rbj; + break; + case XSTORMY16_OPERAND_RD : + value = fields->f_Rd; + break; + case XSTORMY16_OPERAND_RDM : + value = fields->f_Rdm; + break; + case XSTORMY16_OPERAND_RM : + value = fields->f_Rm; + break; + case XSTORMY16_OPERAND_RS : + value = fields->f_Rs; + break; + case XSTORMY16_OPERAND_ABS24 : + value = fields->f_abs24; + break; + case XSTORMY16_OPERAND_BCOND2 : + value = fields->f_op2; + break; + case XSTORMY16_OPERAND_BCOND5 : + value = fields->f_op5; + break; + case XSTORMY16_OPERAND_HMEM8 : + value = fields->f_hmem8; + break; + case XSTORMY16_OPERAND_IMM12 : + value = fields->f_imm12; + break; + case XSTORMY16_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case XSTORMY16_OPERAND_IMM2 : + value = fields->f_imm2; + break; + case XSTORMY16_OPERAND_IMM3 : + value = fields->f_imm3; + break; + case XSTORMY16_OPERAND_IMM3B : + value = fields->f_imm3b; + break; + case XSTORMY16_OPERAND_IMM4 : + value = fields->f_imm4; + break; + case XSTORMY16_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_LMEM8 : + value = fields->f_lmem8; + break; + case XSTORMY16_OPERAND_REL12 : + value = fields->f_rel12; + break; + case XSTORMY16_OPERAND_REL12A : + value = fields->f_rel12a; + break; + case XSTORMY16_OPERAND_REL8_2 : + value = fields->f_rel8_2; + break; + case XSTORMY16_OPERAND_REL8_4 : + value = fields->f_rel8_4; + break; + case XSTORMY16_OPERAND_WS2 : + value = fields->f_op2m; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + value = fields->f_Rb; + break; + case XSTORMY16_OPERAND_RBJ : + value = fields->f_Rbj; + break; + case XSTORMY16_OPERAND_RD : + value = fields->f_Rd; + break; + case XSTORMY16_OPERAND_RDM : + value = fields->f_Rdm; + break; + case XSTORMY16_OPERAND_RM : + value = fields->f_Rm; + break; + case XSTORMY16_OPERAND_RS : + value = fields->f_Rs; + break; + case XSTORMY16_OPERAND_ABS24 : + value = fields->f_abs24; + break; + case XSTORMY16_OPERAND_BCOND2 : + value = fields->f_op2; + break; + case XSTORMY16_OPERAND_BCOND5 : + value = fields->f_op5; + break; + case XSTORMY16_OPERAND_HMEM8 : + value = fields->f_hmem8; + break; + case XSTORMY16_OPERAND_IMM12 : + value = fields->f_imm12; + break; + case XSTORMY16_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case XSTORMY16_OPERAND_IMM2 : + value = fields->f_imm2; + break; + case XSTORMY16_OPERAND_IMM3 : + value = fields->f_imm3; + break; + case XSTORMY16_OPERAND_IMM3B : + value = fields->f_imm3b; + break; + case XSTORMY16_OPERAND_IMM4 : + value = fields->f_imm4; + break; + case XSTORMY16_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + value = fields->f_imm8; + break; + case XSTORMY16_OPERAND_LMEM8 : + value = fields->f_lmem8; + break; + case XSTORMY16_OPERAND_REL12 : + value = fields->f_rel12; + break; + case XSTORMY16_OPERAND_REL12A : + value = fields->f_rel12a; + break; + case XSTORMY16_OPERAND_REL8_2 : + value = fields->f_rel8_2; + break; + case XSTORMY16_OPERAND_REL8_4 : + value = fields->f_rel8_4; + break; + case XSTORMY16_OPERAND_WS2 : + value = fields->f_op2m; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void xstormy16_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void xstormy16_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +xstormy16_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + fields->f_Rb = value; + break; + case XSTORMY16_OPERAND_RBJ : + fields->f_Rbj = value; + break; + case XSTORMY16_OPERAND_RD : + fields->f_Rd = value; + break; + case XSTORMY16_OPERAND_RDM : + fields->f_Rdm = value; + break; + case XSTORMY16_OPERAND_RM : + fields->f_Rm = value; + break; + case XSTORMY16_OPERAND_RS : + fields->f_Rs = value; + break; + case XSTORMY16_OPERAND_ABS24 : + fields->f_abs24 = value; + break; + case XSTORMY16_OPERAND_BCOND2 : + fields->f_op2 = value; + break; + case XSTORMY16_OPERAND_BCOND5 : + fields->f_op5 = value; + break; + case XSTORMY16_OPERAND_HMEM8 : + fields->f_hmem8 = value; + break; + case XSTORMY16_OPERAND_IMM12 : + fields->f_imm12 = value; + break; + case XSTORMY16_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case XSTORMY16_OPERAND_IMM2 : + fields->f_imm2 = value; + break; + case XSTORMY16_OPERAND_IMM3 : + fields->f_imm3 = value; + break; + case XSTORMY16_OPERAND_IMM3B : + fields->f_imm3b = value; + break; + case XSTORMY16_OPERAND_IMM4 : + fields->f_imm4 = value; + break; + case XSTORMY16_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_LMEM8 : + fields->f_lmem8 = value; + break; + case XSTORMY16_OPERAND_REL12 : + fields->f_rel12 = value; + break; + case XSTORMY16_OPERAND_REL12A : + fields->f_rel12a = value; + break; + case XSTORMY16_OPERAND_REL8_2 : + fields->f_rel8_2 = value; + break; + case XSTORMY16_OPERAND_REL8_4 : + fields->f_rel8_4 = value; + break; + case XSTORMY16_OPERAND_WS2 : + fields->f_op2m = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +xstormy16_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case XSTORMY16_OPERAND_RB : + fields->f_Rb = value; + break; + case XSTORMY16_OPERAND_RBJ : + fields->f_Rbj = value; + break; + case XSTORMY16_OPERAND_RD : + fields->f_Rd = value; + break; + case XSTORMY16_OPERAND_RDM : + fields->f_Rdm = value; + break; + case XSTORMY16_OPERAND_RM : + fields->f_Rm = value; + break; + case XSTORMY16_OPERAND_RS : + fields->f_Rs = value; + break; + case XSTORMY16_OPERAND_ABS24 : + fields->f_abs24 = value; + break; + case XSTORMY16_OPERAND_BCOND2 : + fields->f_op2 = value; + break; + case XSTORMY16_OPERAND_BCOND5 : + fields->f_op5 = value; + break; + case XSTORMY16_OPERAND_HMEM8 : + fields->f_hmem8 = value; + break; + case XSTORMY16_OPERAND_IMM12 : + fields->f_imm12 = value; + break; + case XSTORMY16_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case XSTORMY16_OPERAND_IMM2 : + fields->f_imm2 = value; + break; + case XSTORMY16_OPERAND_IMM3 : + fields->f_imm3 = value; + break; + case XSTORMY16_OPERAND_IMM3B : + fields->f_imm3b = value; + break; + case XSTORMY16_OPERAND_IMM4 : + fields->f_imm4 = value; + break; + case XSTORMY16_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_IMM8SMALL : + fields->f_imm8 = value; + break; + case XSTORMY16_OPERAND_LMEM8 : + fields->f_lmem8 = value; + break; + case XSTORMY16_OPERAND_REL12 : + fields->f_rel12 = value; + break; + case XSTORMY16_OPERAND_REL12A : + fields->f_rel12a = value; + break; + case XSTORMY16_OPERAND_REL8_2 : + fields->f_rel8_2 = value; + break; + case XSTORMY16_OPERAND_REL8_4 : + fields->f_rel8_4 = value; + break; + case XSTORMY16_OPERAND_WS2 : + fields->f_op2m = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +xstormy16_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & xstormy16_cgen_insert_handlers[0]; + cd->extract_handlers = & xstormy16_cgen_extract_handlers[0]; + + cd->insert_operand = xstormy16_cgen_insert_operand; + cd->extract_operand = xstormy16_cgen_extract_operand; + + cd->get_int_operand = xstormy16_cgen_get_int_operand; + cd->set_int_operand = xstormy16_cgen_set_int_operand; + cd->get_vma_operand = xstormy16_cgen_get_vma_operand; + cd->set_vma_operand = xstormy16_cgen_set_vma_operand; +} diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-opc.c b/external/gpl3/gdb/dist/opcodes/xstormy16-opc.c new file mode 100644 index 000000000000..59659b3b32d9 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-opc.c @@ -0,0 +1,1176 @@ +/* Instruction opcode table for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "xstormy16-desc.h" +#include "xstormy16-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_movlmemimm ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_LMEM8) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhmemimm ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_HMEM8) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movlgrmem ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhgrmem ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgri ATTRIBUTE_UNUSED = { + 16, 16, 0xfe08, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgrii ATTRIBUTE_UNUSED = { + 32, 32, 0xfe08f000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5) }, { F (F_IMM12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrgr ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwimm8 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwgrimm8 ATTRIBUTE_UNUSED = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movwgrimm16 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movlowgr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfgrgrii ATTRIBUTE_UNUSED = { + 32, 32, 0xfe088000, { { F (F_OP1) }, { F (F_OP2A) }, { F (F_OP2M) }, { F (F_RS) }, { F (F_OP4M) }, { F (F_RDM) }, { F (F_OP5A) }, { F (F_RB) }, { F (F_IMM12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addgrimm4 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_incgrimm2 ATTRIBUTE_UNUSED = { + 16, 16, 0xffc0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_set1lmemimm ATTRIBUTE_UNUSED = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_LMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_set1hmemimm ATTRIBUTE_UNUSED = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_IMM3) }, { F (F_OP2M) }, { F (F_HMEM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccgrgr ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccgrimm8 ATTRIBUTE_UNUSED = { + 32, 32, 0xf1000000, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bccimm16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_4) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bngrimm4 ATTRIBUTE_UNUSED = { + 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM4) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bngrgr ATTRIBUTE_UNUSED = { + 32, 32, 0xff00f000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS) }, { F (F_RD) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnlmemimm ATTRIBUTE_UNUSED = { + 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_LMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnhmemimm ATTRIBUTE_UNUSED = { + 32, 32, 0xff008000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_HMEM8) }, { F (F_OP5A) }, { F (F_IMM3B) }, { F (F_REL12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcc ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REL8_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_br ATTRIBUTE_UNUSED = { + 16, 16, 0xf001, { { F (F_OP1) }, { F (F_REL12A) }, { F (F_OP4B) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 16, 16, 0xffe0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3B) }, { F (F_RBJ) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpf ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_ABS24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_iret ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_OP) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) XSTORMY16_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE xstormy16_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* mov$ws2 $lmem8,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', '#', OP (IMM16), 0 } }, + & ifmt_movlmemimm, { 0x78000000 } + }, +/* mov$ws2 $hmem8,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', '#', OP (IMM16), 0 } }, + & ifmt_movhmemimm, { 0x7a000000 } + }, +/* mov$ws2 $Rm,$lmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (LMEM8), 0 } }, + & ifmt_movlgrmem, { 0x8000 } + }, +/* mov$ws2 $Rm,$hmem8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RM), ',', OP (HMEM8), 0 } }, + & ifmt_movhgrmem, { 0xa000 } + }, +/* mov$ws2 $lmem8,$Rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (LMEM8), ',', OP (RM), 0 } }, + & ifmt_movlgrmem, { 0x9000 } + }, +/* mov$ws2 $hmem8,$Rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (HMEM8), ',', OP (RM), 0 } }, + & ifmt_movhgrmem, { 0xb000 } + }, +/* mov$ws2 $Rdm,($Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x7000 } + }, +/* mov$ws2 $Rdm,($Rs++) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } }, + & ifmt_movgrgri, { 0x6000 } + }, +/* mov$ws2 $Rdm,(--$Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x6800 } + }, +/* mov$ws2 ($Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x7200 } + }, +/* mov$ws2 ($Rs++),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6200 } + }, +/* mov$ws2 (--$Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6a00 } + }, +/* mov$ws2 $Rdm,($Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x70080000 } + }, +/* mov$ws2 $Rdm,($Rs++,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x60080000 } + }, +/* mov$ws2 $Rdm,(--$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movgrgrii, { 0x68080000 } + }, +/* mov$ws2 ($Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x72080000 } + }, +/* mov$ws2 ($Rs++,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x62080000 } + }, +/* mov$ws2 (--$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgrii, { 0x6a080000 } + }, +/* mov $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4600 } + }, +/* mov.w Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4700 } + }, +/* mov.w $Rm,#$imm8small */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), ',', '#', OP (IMM8SMALL), 0 } }, + & ifmt_movwgrimm8, { 0x2100 } + }, +/* mov.w $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31300000 } + }, +/* mov.b $Rd,RxL */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'L', 0 } }, + & ifmt_movlowgr, { 0x30c0 } + }, +/* mov.b $Rd,RxH */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', 'R', 'x', 'H', 0 } }, + & ifmt_movlowgr, { 0x30d0 } + }, +/* movf$ws2 $Rdm,($Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x7400 } + }, +/* movf$ws2 $Rdm,($Rs++) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } }, + & ifmt_movgrgri, { 0x6400 } + }, +/* movf$ws2 $Rdm,(--$Rs) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } }, + & ifmt_movgrgri, { 0x6c00 } + }, +/* movf$ws2 ($Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x7600 } + }, +/* movf$ws2 ($Rs++),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6600 } + }, +/* movf$ws2 (--$Rs),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } }, + & ifmt_movgrgri, { 0x6e00 } + }, +/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x74080000 } + }, +/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x64080000 } + }, +/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } }, + & ifmt_movfgrgrii, { 0x6c080000 } + }, +/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x76080000 } + }, +/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x66080000 } + }, +/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } }, + & ifmt_movfgrgrii, { 0x6e080000 } + }, +/* mask $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3300 } + }, +/* mask $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x30e00000 } + }, +/* push $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x80 } + }, +/* pop $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x90 } + }, +/* swpn $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x3090 } + }, +/* swpb $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x3080 } + }, +/* swpw $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3200 } + }, +/* and $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4000 } + }, +/* and Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4100 } + }, +/* and $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31000000 } + }, +/* or $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4200 } + }, +/* or Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4300 } + }, +/* or $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31100000 } + }, +/* xor $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4400 } + }, +/* xor Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x4500 } + }, +/* xor $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31200000 } + }, +/* not $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30b0 } + }, +/* add $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4900 } + }, +/* add $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5100 } + }, +/* add Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5900 } + }, +/* add $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31400000 } + }, +/* adc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4b00 } + }, +/* adc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5300 } + }, +/* adc Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5b00 } + }, +/* adc $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31500000 } + }, +/* sub $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4d00 } + }, +/* sub $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5500 } + }, +/* sub Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5d00 } + }, +/* sub $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31600000 } + }, +/* sbc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x4f00 } + }, +/* sbc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x5700 } + }, +/* sbc Rx,#$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'R', 'x', ',', '#', OP (IMM8), 0 } }, + & ifmt_movwimm8, { 0x5f00 } + }, +/* sbc $Rd,#$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM16), 0 } }, + & ifmt_movwgrimm16, { 0x31700000 } + }, +/* inc $Rd,#$imm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } }, + & ifmt_incgrimm2, { 0x3000 } + }, +/* dec $Rd,#$imm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM2), 0 } }, + & ifmt_incgrimm2, { 0x3040 } + }, +/* rrc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3800 } + }, +/* rrc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3900 } + }, +/* rlc $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3a00 } + }, +/* rlc $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3b00 } + }, +/* shr $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3c00 } + }, +/* shr $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3d00 } + }, +/* shl $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3e00 } + }, +/* shl $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3f00 } + }, +/* asr $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0x3600 } + }, +/* asr $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x3700 } + }, +/* set1 $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x900 } + }, +/* set1 $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0xb00 } + }, +/* set1 $lmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1lmemimm, { 0xe100 } + }, +/* set1 $hmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1hmemimm, { 0xf100 } + }, +/* clr1 $Rd,#$imm4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), 0 } }, + & ifmt_addgrimm4, { 0x800 } + }, +/* clr1 $Rd,$Rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_movgrgr, { 0xa00 } + }, +/* clr1 $lmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1lmemimm, { 0xe000 } + }, +/* clr1 $hmem8,#$imm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3), 0 } }, + & ifmt_set1hmemimm, { 0xf000 } + }, +/* cbw $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30a0 } + }, +/* rev $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30f0 } + }, +/* b$bcond5 $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND5), ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bccgrgr, { 0xd000000 } + }, +/* b$bcond5 $Rm,#$imm8,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND5), ' ', OP (RM), ',', '#', OP (IMM8), ',', OP (REL12), 0 } }, + & ifmt_bccgrimm8, { 0x20000000 } + }, +/* b$bcond2 Rx,#$imm16,${rel8-4} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND2), ' ', 'R', 'x', ',', '#', OP (IMM16), ',', OP (REL8_4), 0 } }, + & ifmt_bccimm16, { 0xc0000000 } + }, +/* bn $Rd,#$imm4,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } }, + & ifmt_bngrimm4, { 0x4000000 } + }, +/* bn $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bngrgr, { 0x6000000 } + }, +/* bn $lmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnlmemimm, { 0x7c000000 } + }, +/* bn $hmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnhmemimm, { 0x7e000000 } + }, +/* bp $Rd,#$imm4,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '#', OP (IMM4), ',', OP (REL12), 0 } }, + & ifmt_bngrimm4, { 0x5000000 } + }, +/* bp $Rd,$Rs,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (REL12), 0 } }, + & ifmt_bngrgr, { 0x7000000 } + }, +/* bp $lmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnlmemimm, { 0x7d000000 } + }, +/* bp $hmem8,#$imm3b,$rel12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (HMEM8), ',', '#', OP (IMM3B), ',', OP (REL12), 0 } }, + & ifmt_bnhmemimm, { 0x7f000000 } + }, +/* b$bcond2 ${rel8-2} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (BCOND2), ' ', OP (REL8_2), 0 } }, + & ifmt_bcc, { 0xd000 } + }, +/* br $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x20 } + }, +/* br $rel12a */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REL12A), 0 } }, + & ifmt_br, { 0x1000 } + }, +/* jmp $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0x40 } + }, +/* jmpf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x2000000 } + }, +/* callr $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x10 } + }, +/* callr $rel12a */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REL12A), 0 } }, + & ifmt_br, { 0x1001 } + }, +/* call $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0xa0 } + }, +/* callf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x1000000 } + }, +/* icallr $Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_movlowgr, { 0x30 } + }, +/* icall $Rbj,$Rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RBJ), ',', OP (RD), 0 } }, + & ifmt_jmp, { 0x60 } + }, +/* icallf $abs24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ABS24), 0 } }, + & ifmt_jmpf, { 0x3000000 } + }, +/* iret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x2 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x3 } + }, +/* mul */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xd0 } + }, +/* div */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xc0 } + }, +/* sdiv */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xc8 } + }, +/* sdivlh */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xe8 } + }, +/* divlh */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xe0 } + }, +/* reset */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xf } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x0 } + }, +/* halt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x8 } + }, +/* hold */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xa } + }, +/* holdx */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xb } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x5 } + }, +/* --unused-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0x1 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & xstormy16_cgen_ifld_table[XSTORMY16_##f] +static const CGEN_IFMT ifmt_movimm8 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrimm8 ATTRIBUTE_UNUSED = { + 16, 16, 0xf100, { { F (F_OP1) }, { F (F_RM) }, { F (F_OP2M) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgrimm16 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RD) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_incgr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_decgr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3A) }, { F (F_IMM2) }, { F (F_RD) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) XSTORMY16_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE xstormy16_cgen_macro_insn_table[] = +{ +/* mov Rx,#$imm8 */ + { + -1, "movimm8", "mov", 16, + { 0|A(ALIAS), { { { (1<= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + xstormy16_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & xstormy16_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + xstormy16_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/external/gpl3/gdb/dist/opcodes/xstormy16-opc.h b/external/gpl3/gdb/dist/opcodes/xstormy16-opc.h new file mode 100644 index 000000000000..765fd91707cf --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xstormy16-opc.h @@ -0,0 +1,138 @@ +/* Instruction opcode header for xstormy16. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef XSTORMY16_OPC_H +#define XSTORMY16_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* We can't use the default hash size because many bits are used by + operands. */ +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +/* -- */ +/* Enum declaration for xstormy16 instruction types. */ +typedef enum cgen_insn_type { + XSTORMY16_INSN_INVALID, XSTORMY16_INSN_MOVLMEMIMM, XSTORMY16_INSN_MOVHMEMIMM, XSTORMY16_INSN_MOVLGRMEM + , XSTORMY16_INSN_MOVHGRMEM, XSTORMY16_INSN_MOVLMEMGR, XSTORMY16_INSN_MOVHMEMGR, XSTORMY16_INSN_MOVGRGRI + , XSTORMY16_INSN_MOVGRGRIPOSTINC, XSTORMY16_INSN_MOVGRGRIPREDEC, XSTORMY16_INSN_MOVGRIGR, XSTORMY16_INSN_MOVGRIPOSTINCGR + , XSTORMY16_INSN_MOVGRIPREDECGR, XSTORMY16_INSN_MOVGRGRII, XSTORMY16_INSN_MOVGRGRIIPOSTINC, XSTORMY16_INSN_MOVGRGRIIPREDEC + , XSTORMY16_INSN_MOVGRIIGR, XSTORMY16_INSN_MOVGRIIPOSTINCGR, XSTORMY16_INSN_MOVGRIIPREDECGR, XSTORMY16_INSN_MOVGRGR + , XSTORMY16_INSN_MOVWIMM8, XSTORMY16_INSN_MOVWGRIMM8, XSTORMY16_INSN_MOVWGRIMM16, XSTORMY16_INSN_MOVLOWGR + , XSTORMY16_INSN_MOVHIGHGR, XSTORMY16_INSN_MOVFGRGRI, XSTORMY16_INSN_MOVFGRGRIPOSTINC, XSTORMY16_INSN_MOVFGRGRIPREDEC + , XSTORMY16_INSN_MOVFGRIGR, XSTORMY16_INSN_MOVFGRIPOSTINCGR, XSTORMY16_INSN_MOVFGRIPREDECGR, XSTORMY16_INSN_MOVFGRGRII + , XSTORMY16_INSN_MOVFGRGRIIPOSTINC, XSTORMY16_INSN_MOVFGRGRIIPREDEC, XSTORMY16_INSN_MOVFGRIIGR, XSTORMY16_INSN_MOVFGRIIPOSTINCGR + , XSTORMY16_INSN_MOVFGRIIPREDECGR, XSTORMY16_INSN_MASKGRGR, XSTORMY16_INSN_MASKGRIMM16, XSTORMY16_INSN_PUSHGR + , XSTORMY16_INSN_POPGR, XSTORMY16_INSN_SWPN, XSTORMY16_INSN_SWPB, XSTORMY16_INSN_SWPW + , XSTORMY16_INSN_ANDGRGR, XSTORMY16_INSN_ANDIMM8, XSTORMY16_INSN_ANDGRIMM16, XSTORMY16_INSN_ORGRGR + , XSTORMY16_INSN_ORIMM8, XSTORMY16_INSN_ORGRIMM16, XSTORMY16_INSN_XORGRGR, XSTORMY16_INSN_XORIMM8 + , XSTORMY16_INSN_XORGRIMM16, XSTORMY16_INSN_NOTGR, XSTORMY16_INSN_ADDGRGR, XSTORMY16_INSN_ADDGRIMM4 + , XSTORMY16_INSN_ADDIMM8, XSTORMY16_INSN_ADDGRIMM16, XSTORMY16_INSN_ADCGRGR, XSTORMY16_INSN_ADCGRIMM4 + , XSTORMY16_INSN_ADCIMM8, XSTORMY16_INSN_ADCGRIMM16, XSTORMY16_INSN_SUBGRGR, XSTORMY16_INSN_SUBGRIMM4 + , XSTORMY16_INSN_SUBIMM8, XSTORMY16_INSN_SUBGRIMM16, XSTORMY16_INSN_SBCGRGR, XSTORMY16_INSN_SBCGRIMM4 + , XSTORMY16_INSN_SBCGRIMM8, XSTORMY16_INSN_SBCGRIMM16, XSTORMY16_INSN_INCGRIMM2, XSTORMY16_INSN_DECGRIMM2 + , XSTORMY16_INSN_RRCGRGR, XSTORMY16_INSN_RRCGRIMM4, XSTORMY16_INSN_RLCGRGR, XSTORMY16_INSN_RLCGRIMM4 + , XSTORMY16_INSN_SHRGRGR, XSTORMY16_INSN_SHRGRIMM, XSTORMY16_INSN_SHLGRGR, XSTORMY16_INSN_SHLGRIMM + , XSTORMY16_INSN_ASRGRGR, XSTORMY16_INSN_ASRGRIMM, XSTORMY16_INSN_SET1GRIMM, XSTORMY16_INSN_SET1GRGR + , XSTORMY16_INSN_SET1LMEMIMM, XSTORMY16_INSN_SET1HMEMIMM, XSTORMY16_INSN_CLR1GRIMM, XSTORMY16_INSN_CLR1GRGR + , XSTORMY16_INSN_CLR1LMEMIMM, XSTORMY16_INSN_CLR1HMEMIMM, XSTORMY16_INSN_CBWGR, XSTORMY16_INSN_REVGR + , XSTORMY16_INSN_BCCGRGR, XSTORMY16_INSN_BCCGRIMM8, XSTORMY16_INSN_BCCIMM16, XSTORMY16_INSN_BNGRIMM4 + , XSTORMY16_INSN_BNGRGR, XSTORMY16_INSN_BNLMEMIMM, XSTORMY16_INSN_BNHMEMIMM, XSTORMY16_INSN_BPGRIMM4 + , XSTORMY16_INSN_BPGRGR, XSTORMY16_INSN_BPLMEMIMM, XSTORMY16_INSN_BPHMEMIMM, XSTORMY16_INSN_BCC + , XSTORMY16_INSN_BGR, XSTORMY16_INSN_BR, XSTORMY16_INSN_JMP, XSTORMY16_INSN_JMPF + , XSTORMY16_INSN_CALLRGR, XSTORMY16_INSN_CALLRIMM, XSTORMY16_INSN_CALLGR, XSTORMY16_INSN_CALLFIMM + , XSTORMY16_INSN_ICALLRGR, XSTORMY16_INSN_ICALLGR, XSTORMY16_INSN_ICALLFIMM, XSTORMY16_INSN_IRET + , XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_SDIV + , XSTORMY16_INSN_SDIVLH, XSTORMY16_INSN_DIVLH, XSTORMY16_INSN_RESET, XSTORMY16_INSN_NOP + , XSTORMY16_INSN_HALT, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK + , XSTORMY16_INSN_SYSCALL +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID XSTORMY16_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) XSTORMY16_INSN_SYSCALL + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_Rd; + long f_Rdm; + long f_Rm; + long f_Rs; + long f_Rb; + long f_Rbj; + long f_op1; + long f_op2; + long f_op2a; + long f_op2m; + long f_op3; + long f_op3a; + long f_op3b; + long f_op4; + long f_op4m; + long f_op4b; + long f_op5; + long f_op5a; + long f_op; + long f_imm2; + long f_imm3; + long f_imm3b; + long f_imm4; + long f_imm8; + long f_imm12; + long f_imm16; + long f_lmem8; + long f_hmem8; + long f_rel8_2; + long f_rel8_4; + long f_rel12; + long f_rel12a; + long f_abs24_1; + long f_abs24_2; + long f_abs24; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* XSTORMY16_OPC_H */ diff --git a/external/gpl3/gdb/dist/opcodes/xtensa-dis.c b/external/gpl3/gdb/dist/opcodes/xtensa-dis.c new file mode 100644 index 000000000000..768d8f327909 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/xtensa-dis.c @@ -0,0 +1,267 @@ +/* xtensa-dis.c. Disassembly functions for Xtensa. + Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc. + Contributed by Bob Wilson at Tensilica, Inc. (bwilson@tensilica.com) + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include +#include +#include +#include "xtensa-isa.h" +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "dis-asm.h" + +#include + +extern xtensa_isa xtensa_default_isa; + +#ifndef MAX +#define MAX(a,b) (a > b ? a : b) +#endif + +int show_raw_fields; + +struct dis_private +{ + bfd_byte *byte_buf; + jmp_buf bailout; +}; + + +static int +fetch_data (struct disassemble_info *info, bfd_vma memaddr) +{ + int length, status = 0; + struct dis_private *priv = (struct dis_private *) info->private_data; + int insn_size = xtensa_isa_maxlength (xtensa_default_isa); + + /* Read the maximum instruction size, padding with zeros if we go past + the end of the text section. This code will automatically adjust + length when we hit the end of the buffer. */ + + memset (priv->byte_buf, 0, insn_size); + for (length = insn_size; length > 0; length--) + { + status = (*info->read_memory_func) (memaddr, priv->byte_buf, length, + info); + if (status == 0) + return length; + } + (*info->memory_error_func) (status, memaddr, info); + longjmp (priv->bailout, 1); + /*NOTREACHED*/ +} + + +static void +print_xtensa_operand (bfd_vma memaddr, + struct disassemble_info *info, + xtensa_opcode opc, + int opnd, + unsigned operand_val) +{ + xtensa_isa isa = xtensa_default_isa; + int signed_operand_val; + + if (show_raw_fields) + { + if (operand_val < 0xa) + (*info->fprintf_func) (info->stream, "%u", operand_val); + else + (*info->fprintf_func) (info->stream, "0x%x", operand_val); + return; + } + + (void) xtensa_operand_decode (isa, opc, opnd, &operand_val); + signed_operand_val = (int) operand_val; + + if (xtensa_operand_is_register (isa, opc, opnd) == 0) + { + if (xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) + { + (void) xtensa_operand_undo_reloc (isa, opc, opnd, + &operand_val, memaddr); + info->target = operand_val; + (*info->print_address_func) (info->target, info); + } + else + { + if ((signed_operand_val > -256) && (signed_operand_val < 256)) + (*info->fprintf_func) (info->stream, "%d", signed_operand_val); + else + (*info->fprintf_func) (info->stream, "0x%x", signed_operand_val); + } + } + else + { + int i = 1; + xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); + (*info->fprintf_func) (info->stream, "%s%u", + xtensa_regfile_shortname (isa, opnd_rf), + operand_val); + while (i < xtensa_operand_num_regs (isa, opc, opnd)) + { + operand_val++; + (*info->fprintf_func) (info->stream, ":%s%u", + xtensa_regfile_shortname (isa, opnd_rf), + operand_val); + i++; + } + } +} + + +/* Print the Xtensa instruction at address MEMADDR on info->stream. + Returns length of the instruction in bytes. */ + +int +print_insn_xtensa (bfd_vma memaddr, struct disassemble_info *info) +{ + unsigned operand_val; + int bytes_fetched, size, maxsize, i, n, noperands, nslots; + xtensa_isa isa; + xtensa_opcode opc; + xtensa_format fmt; + struct dis_private priv; + static bfd_byte *byte_buf = NULL; + static xtensa_insnbuf insn_buffer = NULL; + static xtensa_insnbuf slot_buffer = NULL; + int first, first_slot, valid_insn; + + if (!xtensa_default_isa) + xtensa_default_isa = xtensa_isa_init (0, 0); + + info->target = 0; + maxsize = xtensa_isa_maxlength (xtensa_default_isa); + + /* Set bytes_per_line to control the amount of whitespace between the hex + values and the opcode. For Xtensa, we always print one "chunk" and we + vary bytes_per_chunk to determine how many bytes to print. (objdump + would apparently prefer that we set bytes_per_chunk to 1 and vary + bytes_per_line but that makes it hard to fit 64-bit instructions on + an 80-column screen.) The value of bytes_per_line here is not exactly + right, because objdump adds an extra space for each chunk so that the + amount of whitespace depends on the chunk size. Oh well, it's good + enough.... Note that we set the minimum size to 4 to accomodate + literal pools. */ + info->bytes_per_line = MAX (maxsize, 4); + + /* Allocate buffers the first time through. */ + if (!insn_buffer) + { + insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa); + slot_buffer = xtensa_insnbuf_alloc (xtensa_default_isa); + byte_buf = (bfd_byte *) xmalloc (MAX (maxsize, 4)); + } + + priv.byte_buf = byte_buf; + + info->private_data = (void *) &priv; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Don't set "isa" before the setjmp to keep the compiler from griping. */ + isa = xtensa_default_isa; + size = 0; + nslots = 0; + + /* Fetch the maximum size instruction. */ + bytes_fetched = fetch_data (info, memaddr); + + /* Copy the bytes into the decode buffer. */ + memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) * + sizeof (xtensa_insnbuf_word))); + xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf, bytes_fetched); + + fmt = xtensa_format_decode (isa, insn_buffer); + if (fmt == XTENSA_UNDEFINED + || ((size = xtensa_format_length (isa, fmt)) > bytes_fetched)) + valid_insn = 0; + else + { + /* Make sure all the opcodes are valid. */ + valid_insn = 1; + nslots = xtensa_format_num_slots (isa, fmt); + for (n = 0; n < nslots; n++) + { + xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer); + if (xtensa_opcode_decode (isa, fmt, n, slot_buffer) + == XTENSA_UNDEFINED) + { + valid_insn = 0; + break; + } + } + } + + if (!valid_insn) + { + (*info->fprintf_func) (info->stream, ".byte %#02x", priv.byte_buf[0]); + return 1; + } + + if (nslots > 1) + (*info->fprintf_func) (info->stream, "{ "); + + first_slot = 1; + for (n = 0; n < nslots; n++) + { + if (first_slot) + first_slot = 0; + else + (*info->fprintf_func) (info->stream, "; "); + + xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer); + opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer); + (*info->fprintf_func) (info->stream, "%s", + xtensa_opcode_name (isa, opc)); + + /* Print the operands (if any). */ + noperands = xtensa_opcode_num_operands (isa, opc); + first = 1; + for (i = 0; i < noperands; i++) + { + if (xtensa_operand_is_visible (isa, opc, i) == 0) + continue; + if (first) + { + (*info->fprintf_func) (info->stream, "\t"); + first = 0; + } + else + (*info->fprintf_func) (info->stream, ", "); + (void) xtensa_operand_get_field (isa, opc, i, fmt, n, + slot_buffer, &operand_val); + + print_xtensa_operand (memaddr, info, opc, i, operand_val); + } + } + + if (nslots > 1) + (*info->fprintf_func) (info->stream, " }"); + + info->bytes_per_chunk = size; + info->display_endian = info->endian; + + return size; +} + diff --git a/external/gpl3/gdb/dist/opcodes/z80-dis.c b/external/gpl3/gdb/dist/opcodes/z80-dis.c new file mode 100644 index 000000000000..bdb2a4ff08fc --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/z80-dis.c @@ -0,0 +1,626 @@ +/* Print Z80 and R800 instructions + Copyright 2005, 2006, 2007, 2008 Free Software Foundation, Inc. + Contributed by Arnold Metselaar + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include + +struct buffer +{ + bfd_vma base; + int n_fetch; + int n_used; + signed char data[4]; +} ; + +typedef int (*func)(struct buffer *, disassemble_info *, char *); + +struct tab_elt +{ + unsigned char val; + unsigned char mask; + func fp; + char * text; +} ; + +#define TXTSIZ 24 +/* Names of 16-bit registers. */ +static char * rr_str[] = { "bc", "de", "hl", "sp" }; +/* Names of 8-bit registers. */ +static char * r_str[] = { "b", "c", "d", "e", "h", "l", "(hl)", "a" }; +/* Texts for condition codes. */ +static char * cc_str[] = { "nz", "z", "nc", "c", "po", "pe", "p", "m" }; +/* Instruction names for 8-bit arithmetic, operand "a" is often implicit */ +static char * arit_str[] = +{ + "add a,", "adc a,", "sub ", "sbc a,", "and ", "xor ", "or ", "cp " +} ; + +static int +fetch_data (struct buffer *buf, disassemble_info * info, int n) +{ + int r; + + if (buf->n_fetch + n > 4) + abort (); + + r = info->read_memory_func (buf->base + buf->n_fetch, + (unsigned char*) buf->data + buf->n_fetch, + n, info); + if (r == 0) + buf->n_fetch += n; + return !r; +} + +static int +prt (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, "%s", txt); + buf->n_used = buf->n_fetch; + return 1; +} + +static int +prt_e (struct buffer *buf, disassemble_info * info, char *txt) +{ + char e; + int target_addr; + + if (fetch_data (buf, info, 1)) + { + e = buf->data[1]; + target_addr = (buf->base + 2 + e) & 0xffff; + buf->n_used = buf->n_fetch; + info->fprintf_func (info->stream, "%s0x%04x", txt, target_addr); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +static int +jr_cc (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + + snprintf (mytxt, TXTSIZ, txt, cc_str[(buf->data[0] >> 3) & 3]); + return prt_e (buf, info, mytxt); +} + +static int +prt_nn (struct buffer *buf, disassemble_info * info, char *txt) +{ + int nn; + unsigned char *p; + + p = (unsigned char*) buf->data + buf->n_fetch; + if (fetch_data (buf, info, 2)) + { + nn = p[0] + (p[1] << 8); + info->fprintf_func (info->stream, txt, nn); + buf->n_used = buf->n_fetch; + } + else + buf->n_used = -1; + return buf->n_used; +} + +static int +prt_rr_nn (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + int rr; + + rr = (buf->data[buf->n_fetch - 1] >> 4) & 3; + snprintf (mytxt, TXTSIZ, txt, rr_str[rr]); + return prt_nn (buf, info, mytxt); +} + +static int +prt_rr (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, "%s%s", txt, + rr_str[(buf->data[buf->n_fetch - 1] >> 4) & 3]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + +static int +prt_n (struct buffer *buf, disassemble_info * info, char *txt) +{ + int n; + unsigned char *p; + + p = (unsigned char*) buf->data + buf->n_fetch; + + if (fetch_data (buf, info, 1)) + { + n = p[0]; + info->fprintf_func (info->stream, txt, n); + buf->n_used = buf->n_fetch; + } + else + buf->n_used = -1; + + return buf->n_used; +} + +static int +ld_r_n (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + + snprintf (mytxt, TXTSIZ, txt, r_str[(buf->data[0] >> 3) & 7]); + return prt_n (buf, info, mytxt); +} + +static int +prt_r (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, txt, + r_str[(buf->data[buf->n_fetch - 1] >> 3) & 7]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + +static int +ld_r_r (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, txt, + r_str[(buf->data[buf->n_fetch - 1] >> 3) & 7], + r_str[buf->data[buf->n_fetch - 1] & 7]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + +static int +arit_r (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, txt, + arit_str[(buf->data[buf->n_fetch - 1] >> 3) & 7], + r_str[buf->data[buf->n_fetch - 1] & 7]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + +static int +prt_cc (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, "%s%s", txt, + cc_str[(buf->data[0] >> 3) & 7]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + +static int +pop_rr (struct buffer *buf, disassemble_info * info, char *txt) +{ + static char *rr_stack[] = { "bc","de","hl","af"}; + + info->fprintf_func (info->stream, "%s %s", txt, + rr_stack[(buf->data[0] >> 4) & 3]); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + + +static int +jp_cc_nn (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + + snprintf (mytxt,TXTSIZ, + "%s%s,0x%%04x", txt, cc_str[(buf->data[0] >> 3) & 7]); + return prt_nn (buf, info, mytxt); +} + +static int +arit_n (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + + snprintf (mytxt,TXTSIZ, txt, arit_str[(buf->data[0] >> 3) & 7]); + return prt_n (buf, info, mytxt); +} + +static int +rst (struct buffer *buf, disassemble_info * info, char *txt) +{ + info->fprintf_func (info->stream, txt, buf->data[0] & 0x38); + buf->n_used = buf->n_fetch; + return buf->n_used; +} + + +static int +cis (struct buffer *buf, disassemble_info * info, char *txt ATTRIBUTE_UNUSED) +{ + static char * opar[] = { "ld", "cp", "in", "out" }; + char * op; + char c; + + c = buf->data[1]; + op = ((0x13 & c) == 0x13) ? "ot" : (opar[c & 3]); + info->fprintf_func (info->stream, + "%s%c%s", op, + (c & 0x08) ? 'd' : 'i', + (c & 0x10) ? "r" : ""); + buf->n_used = 2; + return buf->n_used; +} + +static int +dump (struct buffer *buf, disassemble_info * info, char *txt) +{ + int i; + + info->fprintf_func (info->stream, "defb "); + for (i = 0; txt[i]; ++i) + info->fprintf_func (info->stream, i ? ", 0x%02x" : "0x%02x", + (unsigned char) buf->data[i]); + buf->n_used = i; + return buf->n_used; +} + +/* Table to disassemble machine codes with prefix 0xED. */ +struct tab_elt opc_ed[] = +{ + { 0x70, 0xFF, prt, "in f,(c)" }, + { 0x70, 0xFF, dump, "xx" }, + { 0x40, 0xC7, prt_r, "in %s,(c)" }, + { 0x71, 0xFF, prt, "out (c),0" }, + { 0x70, 0xFF, dump, "xx" }, + { 0x41, 0xC7, prt_r, "out (c),%s" }, + { 0x42, 0xCF, prt_rr, "sbc hl," }, + { 0x43, 0xCF, prt_rr_nn, "ld (0x%%04x),%s" }, + { 0x44, 0xFF, prt, "neg" }, + { 0x45, 0xFF, prt, "retn" }, + { 0x46, 0xFF, prt, "im 0" }, + { 0x47, 0xFF, prt, "ld i,a" }, + { 0x4A, 0xCF, prt_rr, "adc hl," }, + { 0x4B, 0xCF, prt_rr_nn, "ld %s,(0x%%04x)" }, + { 0x4D, 0xFF, prt, "reti" }, + { 0x4F, 0xFF, prt, "ld r,a" }, + { 0x56, 0xFF, prt, "im 1" }, + { 0x57, 0xFF, prt, "ld a,i" }, + { 0x5E, 0xFF, prt, "im 2" }, + { 0x5F, 0xFF, prt, "ld a,r" }, + { 0x67, 0xFF, prt, "rrd" }, + { 0x6F, 0xFF, prt, "rld" }, + { 0xA0, 0xE4, cis, "" }, + { 0xC3, 0xFF, prt, "muluw hl,bc" }, + { 0xC5, 0xE7, prt_r, "mulub a,%s" }, + { 0xF3, 0xFF, prt, "muluw hl,sp" }, + { 0x00, 0x00, dump, "xx" } +}; + +static int +pref_ed (struct buffer * buf, disassemble_info * info, + char* txt ATTRIBUTE_UNUSED) +{ + struct tab_elt *p; + + if (fetch_data(buf, info, 1)) + { + for (p = opc_ed; p->val != (buf->data[1] & p->mask); ++p) + ; + p->fp (buf, info, p->text); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +/* Instruction names for the instructions addressing single bits. */ +static char *cb1_str[] = { "", "bit", "res", "set"}; +/* Instruction names for shifts and rotates. */ +static char *cb2_str[] = +{ + "rlc", "rrc", "rl", "rr", "sla", "sra", "sli", "srl" +}; + +static int +pref_cb (struct buffer * buf, disassemble_info * info, + char* txt ATTRIBUTE_UNUSED) +{ + if (fetch_data (buf, info, 1)) + { + buf->n_used = 2; + if ((buf->data[1] & 0xc0) == 0) + info->fprintf_func (info->stream, "%s %s", + cb2_str[(buf->data[1] >> 3) & 7], + r_str[buf->data[1] & 7]); + else + info->fprintf_func (info->stream, "%s %d,%s", + cb1_str[(buf->data[1] >> 6) & 3], + (buf->data[1] >> 3) & 7, + r_str[buf->data[1] & 7]); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +static int +addvv (struct buffer * buf, disassemble_info * info, char* txt) +{ + info->fprintf_func (info->stream, "add %s,%s", txt, txt); + + return buf->n_used = buf->n_fetch; +} + +static int +ld_v_v (struct buffer * buf, disassemble_info * info, char* txt) +{ + char mytxt[TXTSIZ]; + + snprintf (mytxt, TXTSIZ, "ld %s%%s,%s%%s", txt, txt); + return ld_r_r (buf, info, mytxt); +} + +static int +prt_d (struct buffer *buf, disassemble_info * info, char *txt) +{ + int d; + signed char *p; + + p = buf->data + buf->n_fetch; + + if (fetch_data (buf, info, 1)) + { + d = p[0]; + info->fprintf_func (info->stream, txt, d); + buf->n_used = buf->n_fetch; + } + else + buf->n_used = -1; + + return buf->n_used; +} + +static int +prt_d_n (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + int d; + signed char *p; + + p = buf->data + buf->n_fetch; + + if (fetch_data (buf, info, 1)) + { + d = p[0]; + snprintf (mytxt, TXTSIZ, txt, d); + return prt_n (buf, info, mytxt); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +static int +arit_d (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + signed char c; + + c = buf->data[buf->n_fetch - 1]; + snprintf (mytxt, TXTSIZ, txt, arit_str[(c >> 3) & 7]); + return prt_d (buf, info, mytxt); +} + +static int +ld_r_d (struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + signed char c; + + c = buf->data[buf->n_fetch - 1]; + snprintf (mytxt, TXTSIZ, txt, r_str[(c >> 3) & 7]); + return prt_d (buf, info, mytxt); +} + +static int +ld_d_r(struct buffer *buf, disassemble_info * info, char *txt) +{ + char mytxt[TXTSIZ]; + signed char c; + + c = buf->data[buf->n_fetch - 1]; + snprintf (mytxt, TXTSIZ, txt, r_str[c & 7]); + return prt_d (buf, info, mytxt); +} + +static int +pref_xd_cb (struct buffer * buf, disassemble_info * info, char* txt) +{ + if (fetch_data (buf, info, 2)) + { + int d; + char arg[TXTSIZ]; + signed char *p; + + buf->n_used = 4; + p = buf->data; + d = p[2]; + + if (((p[3] & 0xC0) == 0x40) || ((p[3] & 7) == 0x06)) + snprintf (arg, TXTSIZ, "(%s%+d)", txt, d); + else + snprintf (arg, TXTSIZ, "(%s%+d),%s", txt, d, r_str[p[3] & 7]); + + if ((p[3] & 0xc0) == 0) + info->fprintf_func (info->stream, "%s %s", + cb2_str[(buf->data[3] >> 3) & 7], + arg); + else + info->fprintf_func (info->stream, "%s %d,%s", + cb1_str[(buf->data[3] >> 6) & 3], + (buf->data[3] >> 3) & 7, + arg); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +/* Table to disassemble machine codes with prefix 0xDD or 0xFD. */ +static struct tab_elt opc_ind[] = +{ + { 0x24, 0xF7, prt_r, "inc %s%%s" }, + { 0x25, 0xF7, prt_r, "dec %s%%s" }, + { 0x26, 0xF7, ld_r_n, "ld %s%%s,0x%%%%02x" }, + { 0x21, 0xFF, prt_nn, "ld %s,0x%%04x" }, + { 0x22, 0xFF, prt_nn, "ld (0x%%04x),%s" }, + { 0x2A, 0xFF, prt_nn, "ld %s,(0x%%04x)" }, + { 0x23, 0xFF, prt, "inc %s" }, + { 0x2B, 0xFF, prt, "dec %s" }, + { 0x29, 0xFF, addvv, "%s" }, + { 0x09, 0xCF, prt_rr, "add %s," }, + { 0x34, 0xFF, prt_d, "inc (%s%%+d)" }, + { 0x35, 0xFF, prt_d, "dec (%s%%+d)" }, + { 0x36, 0xFF, prt_d_n, "ld (%s%%+d),0x%%%%02x" }, + + { 0x76, 0xFF, dump, "h" }, + { 0x46, 0xC7, ld_r_d, "ld %%s,(%s%%%%+d)" }, + { 0x70, 0xF8, ld_d_r, "ld (%s%%%%+d),%%s" }, + { 0x64, 0xF6, ld_v_v, "%s" }, + { 0x60, 0xF0, ld_r_r, "ld %s%%s,%%s" }, + { 0x44, 0xC6, ld_r_r, "ld %%s,%s%%s" }, + + { 0x86, 0xC7, arit_d, "%%s(%s%%%%+d)" }, + { 0x84, 0xC6, arit_r, "%%s%s%%s" }, + + { 0xE1, 0xFF, prt, "pop %s" }, + { 0xE5, 0xFF, prt, "push %s" }, + { 0xCB, 0xFF, pref_xd_cb, "%s" }, + { 0xE3, 0xFF, prt, "ex (sp),%s" }, + { 0xE9, 0xFF, prt, "jp (%s)" }, + { 0xF9, 0xFF, prt, "ld sp,%s" }, + { 0x00, 0x00, dump, "?" }, +} ; + +static int +pref_ind (struct buffer * buf, disassemble_info * info, char* txt) +{ + if (fetch_data (buf, info, 1)) + { + char mytxt[TXTSIZ]; + struct tab_elt *p; + + for (p = opc_ind; p->val != (buf->data[1] & p->mask); ++p) + ; + snprintf (mytxt, TXTSIZ, p->text, txt); + p->fp (buf, info, mytxt); + } + else + buf->n_used = -1; + + return buf->n_used; +} + +/* Table to disassemble machine codes without prefix. */ +static struct tab_elt opc_main[] = +{ + { 0x00, 0xFF, prt, "nop" }, + { 0x01, 0xCF, prt_rr_nn, "ld %s,0x%%04x" }, + { 0x02, 0xFF, prt, "ld (bc),a" }, + { 0x03, 0xCF, prt_rr, "inc " }, + { 0x04, 0xC7, prt_r, "inc %s" }, + { 0x05, 0xC7, prt_r, "dec %s" }, + { 0x06, 0xC7, ld_r_n, "ld %s,0x%%02x" }, + { 0x07, 0xFF, prt, "rlca" }, + { 0x08, 0xFF, prt, "ex af,af'" }, + { 0x09, 0xCF, prt_rr, "add hl," }, + { 0x0A, 0xFF, prt, "ld a,(bc)" }, + { 0x0B, 0xCF, prt_rr, "dec " }, + { 0x0F, 0xFF, prt, "rrca" }, + { 0x10, 0xFF, prt_e, "djnz " }, + { 0x12, 0xFF, prt, "ld (de),a" }, + { 0x17, 0xFF, prt, "rla" }, + { 0x18, 0xFF, prt_e, "jr "}, + { 0x1A, 0xFF, prt, "ld a,(de)" }, + { 0x1F, 0xFF, prt, "rra" }, + { 0x20, 0xE7, jr_cc, "jr %s,"}, + { 0x22, 0xFF, prt_nn, "ld (0x%04x),hl" }, + { 0x27, 0xFF, prt, "daa"}, + { 0x2A, 0xFF, prt_nn, "ld hl,(0x%04x)" }, + { 0x2F, 0xFF, prt, "cpl" }, + { 0x32, 0xFF, prt_nn, "ld (0x%04x),a" }, + { 0x37, 0xFF, prt, "scf" }, + { 0x3A, 0xFF, prt_nn, "ld a,(0x%04x)" }, + { 0x3F, 0xFF, prt, "ccf" }, + + { 0x76, 0xFF, prt, "halt" }, + { 0x40, 0xC0, ld_r_r, "ld %s,%s"}, + + { 0x80, 0xC0, arit_r, "%s%s" }, + + { 0xC0, 0xC7, prt_cc, "ret " }, + { 0xC1, 0xCF, pop_rr, "pop" }, + { 0xC2, 0xC7, jp_cc_nn, "jp " }, + { 0xC3, 0xFF, prt_nn, "jp 0x%04x" }, + { 0xC4, 0xC7, jp_cc_nn, "call " }, + { 0xC5, 0xCF, pop_rr, "push" }, + { 0xC6, 0xC7, arit_n, "%s0x%%02x" }, + { 0xC7, 0xC7, rst, "rst 0x%02x" }, + { 0xC9, 0xFF, prt, "ret" }, + { 0xCB, 0xFF, pref_cb, "" }, + { 0xCD, 0xFF, prt_nn, "call 0x%04x" }, + { 0xD3, 0xFF, prt_n, "out (0x%02x),a" }, + { 0xD9, 0xFF, prt, "exx" }, + { 0xDB, 0xFF, prt_n, "in a,(0x%02x)" }, + { 0xDD, 0xFF, pref_ind, "ix" }, + { 0xE3, 0xFF, prt, "ex (sp),hl" }, + { 0xE9, 0xFF, prt, "jp (hl)" }, + { 0xEB, 0xFF, prt, "ex de,hl" }, + { 0xED, 0xFF, pref_ed, ""}, + { 0xF3, 0xFF, prt, "di" }, + { 0xF9, 0xFF, prt, "ld sp,hl" }, + { 0xFB, 0xFF, prt, "ei" }, + { 0xFD, 0xFF, pref_ind, "iy" }, + { 0x00, 0x00, prt, "????" }, +} ; + +int +print_insn_z80 (bfd_vma addr, disassemble_info * info) +{ + struct buffer buf; + struct tab_elt *p; + + buf.base = addr; + buf.n_fetch = 0; + buf.n_used = 0; + + if (! fetch_data (& buf, info, 1)) + return -1; + + for (p = opc_main; p->val != (buf.data[0] & p->mask); ++p) + ; + p->fp (& buf, info, p->text); + + return buf.n_used; +} diff --git a/external/gpl3/gdb/dist/opcodes/z8k-dis.c b/external/gpl3/gdb/dist/opcodes/z8k-dis.c new file mode 100644 index 000000000000..c0f24dd6993a --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/z8k-dis.c @@ -0,0 +1,644 @@ +/* Disassemble z8000 code. + Copyright 1992, 1993, 1998, 2000, 2001, 2002, 2003, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" + +#define DEFINE_TABLE +#include "z8k-opc.h" + +#include + +typedef struct +{ + /* These are all indexed by nibble number (i.e only every other entry + of bytes is used, and every 4th entry of words). */ + unsigned char nibbles[24]; + unsigned char bytes[24]; + unsigned short words[24]; + + /* Nibble number of first word not yet fetched. */ + int max_fetched; + bfd_vma insn_start; + jmp_buf bailout; + + int tabl_index; + char instr_asmsrc[80]; + unsigned long arg_reg[0x0f]; + unsigned long immediate; + unsigned long displacement; + unsigned long address; + unsigned long cond_code; + unsigned long ctrl_code; + unsigned long flags; + unsigned long interrupts; +} +instr_data_s; + +/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) + to ADDR (exclusive) are valid. Returns 1 for success, longjmps + on error. */ +#define FETCH_DATA(info, nibble) \ + ((nibble) < ((instr_data_s *) (info->private_data))->max_fetched \ + ? 1 : fetch_data ((info), (nibble))) + +static int +fetch_data (struct disassemble_info *info, int nibble) +{ + unsigned char mybuf[20]; + int status; + instr_data_s *priv = (instr_data_s *) info->private_data; + + if ((nibble % 4) != 0) + abort (); + + status = (*info->read_memory_func) (priv->insn_start, + (bfd_byte *) mybuf, + nibble / 2, + info); + if (status != 0) + { + (*info->memory_error_func) (status, priv->insn_start, info); + longjmp (priv->bailout, 1); + } + + { + int i; + unsigned char *p = mybuf; + + for (i = 0; i < nibble;) + { + priv->words[i] = (p[0] << 8) | p[1]; + + priv->bytes[i] = *p; + priv->nibbles[i++] = *p >> 4; + priv->nibbles[i++] = *p & 0xf; + + ++p; + priv->bytes[i] = *p; + priv->nibbles[i++] = *p >> 4; + priv->nibbles[i++] = *p & 0xf; + + ++p; + } + } + priv->max_fetched = nibble; + return 1; +} + +static char *codes[16] = + { + "f", + "lt", + "le", + "ule", + "ov/pe", + "mi", + "eq", + "c/ult", + "t", + "ge", + "gt", + "ugt", + "nov/po", + "pl", + "ne", + "nc/uge" + }; + +static char *ctrl_names[8] = + { + "", + "flags", + "fcw", + "refresh", + "psapseg", + "psapoff", + "nspseg", + "nspoff" + }; + +static int seg_length; +int z8k_lookup_instr (unsigned char *, disassemble_info *); +static void output_instr (instr_data_s *, unsigned long, disassemble_info *); +static void unpack_instr (instr_data_s *, int, disassemble_info *); +static void unparse_instr (instr_data_s *, int); + +static int +print_insn_z8k (bfd_vma addr, disassemble_info *info, int is_segmented) +{ + instr_data_s instr_data; + + info->private_data = (PTR) &instr_data; + instr_data.max_fetched = 0; + instr_data.insn_start = addr; + if (setjmp (instr_data.bailout) != 0) + /* Error return. */ + return -1; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + + instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); + if (instr_data.tabl_index >= 0) + { + unpack_instr (&instr_data, is_segmented, info); + unparse_instr (&instr_data, is_segmented); + output_instr (&instr_data, addr, info); + return z8k_table[instr_data.tabl_index].length + seg_length; + } + else + { + FETCH_DATA (info, 4); + (*info->fprintf_func) (info->stream, ".word %02x%02x", + instr_data.bytes[0], instr_data.bytes[2]); + return 2; + } +} + +int +print_insn_z8001 (bfd_vma addr, disassemble_info *info) +{ + return print_insn_z8k (addr, info, 1); +} + +int +print_insn_z8002 (bfd_vma addr, disassemble_info *info) +{ + return print_insn_z8k (addr, info, 0); +} + +int +z8k_lookup_instr (unsigned char *nibbles, disassemble_info *info) +{ + int nibl_index, tabl_index; + int nibl_matched; + int need_fetch = 0; + unsigned short instr_nibl; + unsigned short tabl_datum, datum_class, datum_value; + + nibl_matched = 0; + tabl_index = 0; + FETCH_DATA (info, 4); + while (!nibl_matched && z8k_table[tabl_index].name) + { + nibl_matched = 1; + for (nibl_index = 0; + nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; + nibl_index++) + { + if ((nibl_index % 4) == 0) + { + /* Fetch data only if it isn't already there. */ + if (nibl_index >= 4 || (nibl_index < 4 && need_fetch)) + FETCH_DATA (info, nibl_index + 4); /* Fetch one word at a time. */ + if (nibl_index < 4) + need_fetch = 0; + else + need_fetch = 1; + } + instr_nibl = nibbles[nibl_index]; + + tabl_datum = z8k_table[tabl_index].byte_info[nibl_index]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = ~CLASS_MASK & tabl_datum; + + switch (datum_class) + { + case CLASS_BIT: + if (datum_value != instr_nibl) + nibl_matched = 0; + break; + case CLASS_IGNORE: + break; + case CLASS_00II: + if (!((~instr_nibl) & 0x4)) + nibl_matched = 0; + break; + case CLASS_01II: + if (!(instr_nibl & 0x4)) + nibl_matched = 0; + break; + case CLASS_0CCC: + if (!((~instr_nibl) & 0x8)) + nibl_matched = 0; + break; + case CLASS_1CCC: + if (!(instr_nibl & 0x8)) + nibl_matched = 0; + break; + case CLASS_0DISP7: + if (!((~instr_nibl) & 0x8)) + nibl_matched = 0; + nibl_index += 1; + break; + case CLASS_1DISP7: + if (!(instr_nibl & 0x8)) + nibl_matched = 0; + nibl_index += 1; + break; + case CLASS_REGN0: + if (instr_nibl == 0) + nibl_matched = 0; + break; + case CLASS_BIT_1OR2: + if ((instr_nibl | 0x2) != (datum_value | 0x2)) + nibl_matched = 0; + break; + default: + break; + } + } + + if (nibl_matched) + return tabl_index; + + tabl_index++; + } + return -1; +} + +static void +output_instr (instr_data_s *instr_data, + unsigned long addr ATTRIBUTE_UNUSED, + disassemble_info *info) +{ + int num_bytes; + char out_str[100]; + + out_str[0] = 0; + + num_bytes = (z8k_table[instr_data->tabl_index].length + seg_length) * 2; + FETCH_DATA (info, num_bytes); + + strcat (out_str, instr_data->instr_asmsrc); + + (*info->fprintf_func) (info->stream, "%s", out_str); +} + +static void +unpack_instr (instr_data_s *instr_data, int is_segmented, disassemble_info *info) +{ + int nibl_count, loop; + unsigned short instr_nibl, instr_byte, instr_word; + long instr_long; + unsigned int tabl_datum, datum_class; + unsigned short datum_value; + + nibl_count = 0; + loop = 0; + seg_length = 0; + + while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0) + { + FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4)); + instr_nibl = instr_data->nibbles[nibl_count]; + instr_byte = instr_data->bytes[nibl_count & ~1]; + instr_word = instr_data->words[nibl_count & ~3]; + + tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = tabl_datum & ~CLASS_MASK; + + switch (datum_class) + { + case CLASS_DISP: + switch (datum_value) + { + case ARG_DISP16: + instr_data->displacement = instr_data->insn_start + 4 + + (signed short) (instr_word & 0xffff); + nibl_count += 3; + break; + case ARG_DISP12: + if (instr_word & 0x800) + /* Negative 12 bit displacement. */ + instr_data->displacement = instr_data->insn_start + 2 + - (signed short) ((instr_word & 0xfff) | 0xf000) * 2; + else + instr_data->displacement = instr_data->insn_start + 2 + - (instr_word & 0x0fff) * 2; + + nibl_count += 2; + break; + default: + break; + } + break; + case CLASS_IMM: + switch (datum_value) + { + case ARG_IMM4: + instr_data->immediate = instr_nibl; + break; + case ARG_NIM4: + instr_data->immediate = (- instr_nibl) & 0xf; + break; + case ARG_NIM8: + instr_data->immediate = (- instr_byte) & 0xff; + nibl_count += 1; + break; + case ARG_IMM8: + instr_data->immediate = instr_byte; + nibl_count += 1; + break; + case ARG_IMM16: + instr_data->immediate = instr_word; + nibl_count += 3; + break; + case ARG_IMM32: + FETCH_DATA (info, nibl_count + 8); + instr_long = (instr_data->words[nibl_count] << 16) + | (instr_data->words[nibl_count + 4]); + instr_data->immediate = instr_long; + nibl_count += 7; + break; + case ARG_IMMN: + instr_data->immediate = instr_nibl - 1; + break; + case ARG_IMM4M1: + instr_data->immediate = instr_nibl + 1; + break; + case ARG_IMM_1: + instr_data->immediate = 1; + break; + case ARG_IMM_2: + instr_data->immediate = 2; + break; + case ARG_IMM2: + instr_data->immediate = instr_nibl & 0x3; + break; + default: + break; + } + break; + case CLASS_CC: + instr_data->cond_code = instr_nibl; + break; + case CLASS_ADDRESS: + if (is_segmented) + { + if (instr_nibl & 0x8) + { + FETCH_DATA (info, nibl_count + 8); + instr_long = (instr_data->words[nibl_count] << 16) + | (instr_data->words[nibl_count + 4]); + instr_data->address = ((instr_word & 0x7f00) << 16) + + (instr_long & 0xffff); + nibl_count += 7; + seg_length = 2; + } + else + { + instr_data->address = ((instr_word & 0x7f00) << 16) + + (instr_word & 0x00ff); + nibl_count += 3; + } + } + else + { + instr_data->address = instr_word; + nibl_count += 3; + } + break; + case CLASS_0CCC: + case CLASS_1CCC: + instr_data->ctrl_code = instr_nibl & 0x7; + break; + case CLASS_0DISP7: + instr_data->displacement = + instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; + nibl_count += 1; + break; + case CLASS_1DISP7: + instr_data->displacement = + instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; + nibl_count += 1; + break; + case CLASS_01II: + instr_data->interrupts = instr_nibl & 0x3; + break; + case CLASS_00II: + instr_data->interrupts = instr_nibl & 0x3; + break; + case CLASS_IGNORE: + case CLASS_BIT: + instr_data->ctrl_code = instr_nibl & 0x7; + break; + case CLASS_FLAGS: + instr_data->flags = instr_nibl; + break; + case CLASS_REG: + instr_data->arg_reg[datum_value] = instr_nibl; + break; + case CLASS_REGN0: + instr_data->arg_reg[datum_value] = instr_nibl; + break; + case CLASS_DISP8: + instr_data->displacement = + instr_data->insn_start + 2 + (signed char) instr_byte * 2; + nibl_count += 1; + break; + case CLASS_BIT_1OR2: + instr_data->immediate = ((instr_nibl >> 1) & 0x1) + 1; + nibl_count += 1; + break; + default: + abort (); + break; + } + + loop += 1; + nibl_count += 1; + } +} + +static void +print_intr(char *tmp_str, unsigned long interrupts) +{ + int comma = 0; + + *tmp_str = 0; + if (! (interrupts & 2)) + { + strcat (tmp_str, "vi"); + comma = 1; + } + if (! (interrupts & 1)) + { + if (comma) strcat (tmp_str, ","); + strcat (tmp_str, "nvi"); + } +} + +static void +print_flags(char *tmp_str, unsigned long flags) +{ + int comma = 0; + + *tmp_str = 0; + if (flags & 8) + { + strcat (tmp_str, "c"); + comma = 1; + } + if (flags & 4) + { + if (comma) strcat (tmp_str, ","); + strcat (tmp_str, "z"); + comma = 1; + } + if (flags & 2) + { + if (comma) strcat (tmp_str, ","); + strcat (tmp_str, "s"); + comma = 1; + } + if (flags & 1) + { + if (comma) strcat (tmp_str, ","); + strcat (tmp_str, "p"); + } +} + +static void +unparse_instr (instr_data_s *instr_data, int is_segmented) +{ + unsigned short datum_value; + unsigned int tabl_datum, datum_class; + int loop, loop_limit; + char out_str[80], tmp_str[25]; + + sprintf (out_str, "%s\t", z8k_table[instr_data->tabl_index].name); + + loop_limit = z8k_table[instr_data->tabl_index].noperands; + for (loop = 0; loop < loop_limit; loop++) + { + if (loop) + strcat (out_str, ","); + + tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop]; + datum_class = tabl_datum & CLASS_MASK; + datum_value = tabl_datum & ~CLASS_MASK; + + switch (datum_class) + { + case CLASS_X: + sprintf (tmp_str, "0x%0lx(r%ld)", instr_data->address, + instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_BA: + if (is_segmented) + sprintf (tmp_str, "rr%ld(#0x%lx)", instr_data->arg_reg[datum_value], + instr_data->immediate); + else + sprintf (tmp_str, "r%ld(#0x%lx)", instr_data->arg_reg[datum_value], + instr_data->immediate); + strcat (out_str, tmp_str); + break; + case CLASS_BX: + if (is_segmented) + sprintf (tmp_str, "rr%ld(r%ld)", instr_data->arg_reg[datum_value], + instr_data->arg_reg[ARG_RX]); + else + sprintf (tmp_str, "r%ld(r%ld)", instr_data->arg_reg[datum_value], + instr_data->arg_reg[ARG_RX]); + strcat (out_str, tmp_str); + break; + case CLASS_DISP: + sprintf (tmp_str, "0x%0lx", instr_data->displacement); + strcat (out_str, tmp_str); + break; + case CLASS_IMM: + if (datum_value == ARG_IMM2) /* True with EI/DI instructions only. */ + { + print_intr (tmp_str, instr_data->interrupts); + strcat (out_str, tmp_str); + break; + } + sprintf (tmp_str, "#0x%0lx", instr_data->immediate); + strcat (out_str, tmp_str); + break; + case CLASS_CC: + sprintf (tmp_str, "%s", codes[instr_data->cond_code]); + strcat (out_str, tmp_str); + break; + case CLASS_CTRL: + sprintf (tmp_str, "%s", ctrl_names[instr_data->ctrl_code]); + strcat (out_str, tmp_str); + break; + case CLASS_DA: + case CLASS_ADDRESS: + sprintf (tmp_str, "0x%0lx", instr_data->address); + strcat (out_str, tmp_str); + break; + case CLASS_IR: + if (is_segmented) + sprintf (tmp_str, "@rr%ld", instr_data->arg_reg[datum_value]); + else + sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_IRO: + sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_FLAGS: + print_flags(tmp_str, instr_data->flags); + strcat (out_str, tmp_str); + break; + case CLASS_REG_BYTE: + if (instr_data->arg_reg[datum_value] >= 0x8) + sprintf (tmp_str, "rl%ld", + instr_data->arg_reg[datum_value] - 0x8); + else + sprintf (tmp_str, "rh%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_WORD: + sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_QUAD: + sprintf (tmp_str, "rq%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_REG_LONG: + sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + case CLASS_PR: + if (is_segmented) + sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); + else + sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); + strcat (out_str, tmp_str); + break; + default: + abort (); + break; + } + } + + strcpy (instr_data->instr_asmsrc, out_str); +} diff --git a/external/gpl3/gdb/dist/opcodes/z8k-opc.h b/external/gpl3/gdb/dist/opcodes/z8k-opc.h new file mode 100644 index 000000000000..acc199cacdfe --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/z8k-opc.h @@ -0,0 +1,3807 @@ +/* DO NOT EDIT! -*- buffer-read-only: t -*- + This file is automatically generated by z8kgen. */ + +/* Copyright 2007, 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#define ARG_MASK 0x0f +#define ARG_SRC 0x01 +#define ARG_DST 0x02 +#define ARG_RS 0x01 +#define ARG_RD 0x02 +#define ARG_RA 0x03 +#define ARG_RB 0x04 +#define ARG_RR 0x05 +#define ARG_RX 0x06 +#define ARG_IMM4 0x01 +#define ARG_IMM8 0x02 +#define ARG_IMM16 0x03 +#define ARG_IMM32 0x04 +#define ARG_IMMN 0x05 +#define ARG_IMMNMINUS1 0x05 +#define ARG_IMM_1 0x06 +#define ARG_IMM_2 0x07 +#define ARG_DISP16 0x08 +#define ARG_NIM8 0x09 +#define ARG_IMM2 0x0a +#define ARG_IMM1OR2 0x0b +#define ARG_DISP12 0x0b +#define ARG_NIM4 0x0c +#define ARG_DISP8 0x0c +#define ARG_IMM4M1 0x0d +#define CLASS_X 0x10 +#define CLASS_BA 0x20 +#define CLASS_DA 0x30 +#define CLASS_BX 0x40 +#define CLASS_DISP 0x50 +#define CLASS_IMM 0x60 +#define CLASS_CC 0x70 +#define CLASS_CTRL 0x80 +#define CLASS_IGNORE 0x90 +#define CLASS_ADDRESS 0xd0 +#define CLASS_0CCC 0xe0 +#define CLASS_1CCC 0xf0 +#define CLASS_0DISP7 0x100 +#define CLASS_1DISP7 0x200 +#define CLASS_01II 0x300 +#define CLASS_00II 0x400 +#define CLASS_BIT 0x500 +#define CLASS_FLAGS 0x600 +#define CLASS_IR 0x700 +#define CLASS_IRO 0x800 +#define CLASS_DISP8 0x900 +#define CLASS_BIT_1OR2 0xa00 +#define CLASS_REG 0x7000 +#define CLASS_REG_BYTE 0x2000 +#define CLASS_REG_WORD 0x3000 +#define CLASS_REG_QUAD 0x4000 +#define CLASS_REG_LONG 0x5000 +#define CLASS_REGN0 0x8000 +#define CLASS_PR 0x10000 +#define CLASS_MASK 0x1fff0 +#define OPC_adc 0 +#define OPC_adcb 1 +#define OPC_add 2 +#define OPC_addb 3 +#define OPC_addl 4 +#define OPC_and 5 +#define OPC_andb 6 +#define OPC_bit 7 +#define OPC_bitb 8 +#define OPC_call 9 +#define OPC_calr 10 +#define OPC_clr 11 +#define OPC_clrb 12 +#define OPC_com 13 +#define OPC_comb 14 +#define OPC_comflg 15 +#define OPC_cp 16 +#define OPC_cpb 17 +#define OPC_cpd 18 +#define OPC_cpdb 19 +#define OPC_cpdr 20 +#define OPC_cpdrb 21 +#define OPC_cpi 22 +#define OPC_cpib 23 +#define OPC_cpir 24 +#define OPC_cpirb 25 +#define OPC_cpl 26 +#define OPC_cpsd 27 +#define OPC_cpsdb 28 +#define OPC_cpsdr 29 +#define OPC_cpsdrb 30 +#define OPC_cpsi 31 +#define OPC_cpsib 32 +#define OPC_cpsir 33 +#define OPC_cpsirb 34 +#define OPC_dab 35 +#define OPC_dbjnz 36 +#define OPC_dec 37 +#define OPC_decb 38 +#define OPC_di 39 +#define OPC_div 40 +#define OPC_divl 41 +#define OPC_djnz 42 +#define OPC_ei 43 +#define OPC_ex 44 +#define OPC_exb 45 +#define OPC_exts 46 +#define OPC_extsb 47 +#define OPC_extsl 48 +#define OPC_halt 49 +#define OPC_in 50 +#define OPC_inb 51 +#define OPC_inc 52 +#define OPC_incb 53 +#define OPC_ind 54 +#define OPC_indb 55 +#define OPC_indr 56 +#define OPC_indrb 57 +#define OPC_ini 58 +#define OPC_inib 59 +#define OPC_inir 60 +#define OPC_inirb 61 +#define OPC_iret 62 +#define OPC_jp 63 +#define OPC_jr 64 +#define OPC_ld 65 +#define OPC_lda 66 +#define OPC_ldar 67 +#define OPC_ldb 68 +#define OPC_ldctl 69 +#define OPC_ldir 70 +#define OPC_ldirb 71 +#define OPC_ldk 72 +#define OPC_ldl 73 +#define OPC_ldm 74 +#define OPC_ldps 75 +#define OPC_ldr 76 +#define OPC_ldrb 77 +#define OPC_ldrl 78 +#define OPC_mbit 79 +#define OPC_mreq 80 +#define OPC_mres 81 +#define OPC_mset 82 +#define OPC_mult 83 +#define OPC_multl 84 +#define OPC_neg 85 +#define OPC_negb 86 +#define OPC_nop 87 +#define OPC_or 88 +#define OPC_orb 89 +#define OPC_otdr 90 +#define OPC_otdrb 91 +#define OPC_otir 92 +#define OPC_otirb 93 +#define OPC_out 94 +#define OPC_outb 95 +#define OPC_outd 96 +#define OPC_outdb 97 +#define OPC_outi 98 +#define OPC_outib 99 +#define OPC_pop 100 +#define OPC_popl 101 +#define OPC_push 102 +#define OPC_pushl 103 +#define OPC_res 104 +#define OPC_resb 105 +#define OPC_resflg 106 +#define OPC_ret 107 +#define OPC_rl 108 +#define OPC_rlb 109 +#define OPC_rlc 110 +#define OPC_rlcb 111 +#define OPC_rldb 112 +#define OPC_rr 113 +#define OPC_rrb 114 +#define OPC_rrc 115 +#define OPC_rrcb 116 +#define OPC_rrdb 117 +#define OPC_sbc 118 +#define OPC_sbcb 119 +#define OPC_sda 120 +#define OPC_sdab 121 +#define OPC_sdal 122 +#define OPC_sdl 123 +#define OPC_sdlb 124 +#define OPC_sdll 125 +#define OPC_set 126 +#define OPC_setb 127 +#define OPC_setflg 128 +#define OPC_sin 129 +#define OPC_sinb 130 +#define OPC_sind 131 +#define OPC_sindb 132 +#define OPC_sindr 133 +#define OPC_sindrb 134 +#define OPC_sini 135 +#define OPC_sinib 136 +#define OPC_sinir 137 +#define OPC_sinirb 138 +#define OPC_sla 139 +#define OPC_slab 140 +#define OPC_slal 141 +#define OPC_sll 142 +#define OPC_sllb 143 +#define OPC_slll 144 +#define OPC_sotdr 145 +#define OPC_sotdrb 146 +#define OPC_sotir 147 +#define OPC_sotirb 148 +#define OPC_sout 149 +#define OPC_soutb 150 +#define OPC_soutd 151 +#define OPC_soutdb 152 +#define OPC_souti 153 +#define OPC_soutib 154 +#define OPC_sra 155 +#define OPC_srab 156 +#define OPC_sral 157 +#define OPC_srl 158 +#define OPC_srlb 159 +#define OPC_srll 160 +#define OPC_sub 161 +#define OPC_subb 162 +#define OPC_subl 163 +#define OPC_tcc 164 +#define OPC_tccb 165 +#define OPC_test 166 +#define OPC_testb 167 +#define OPC_testl 168 +#define OPC_trdb 169 +#define OPC_trdrb 170 +#define OPC_trib 171 +#define OPC_trirb 172 +#define OPC_trtdrb 173 +#define OPC_trtib 174 +#define OPC_trtirb 175 +#define OPC_trtrb 176 +#define OPC_tset 177 +#define OPC_tsetb 178 +#define OPC_xor 179 +#define OPC_xorb 180 +#define OPC_ldd 181 +#define OPC_lddb 182 +#define OPC_lddr 183 +#define OPC_lddrb 184 +#define OPC_ldi 185 +#define OPC_ldib 186 +#define OPC_sc 187 +#define OPC_bpt 188 +#define OPC_ext0e 188 +#define OPC_ext0f 188 +#define OPC_ext8e 188 +#define OPC_ext8f 188 +#define OPC_rsvd36 188 +#define OPC_rsvd38 188 +#define OPC_rsvd78 188 +#define OPC_rsvd7e 188 +#define OPC_rsvd9d 188 +#define OPC_rsvd9f 188 +#define OPC_rsvdb9 188 +#define OPC_rsvdbf 188 +#define OPC_ldctlb 189 +#define OPC_trtdb 190 +#define OPC_brk 191 + +typedef struct { +#ifdef NICENAMES + const char *nicename; + int type; + int cycles; + int flags; +#endif + const char *name; + unsigned char opcode; + void (*func) (void); + unsigned int arg_info[4]; + unsigned int byte_info[10]; + int noperands; + int length; + int idx; +} opcode_entry_type; + +#ifdef DEFINE_TABLE +const opcode_entry_type z8k_table[] = { + +/* 1011 0101 ssss dddd *** adc rd,rs */ +{ +#ifdef NICENAMES +"adc rd,rs",16,5,0x3c, +#endif +"adc",OPC_adc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0}, + +/* 1011 0100 ssss dddd *** adcb rbd,rbs */ +{ +#ifdef NICENAMES +"adcb rbd,rbs",8,5,0x3f, +#endif +"adcb",OPC_adcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1}, + +/* 0000 0001 ssN0 dddd *** add rd,@rs */ +{ +#ifdef NICENAMES +"add rd,@rs",16,7,0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, + +/* 0100 0001 0000 dddd address_src *** add rd,address_src */ +{ +#ifdef NICENAMES +"add rd,address_src",16,9,0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,2}, + +/* 0100 0001 ssN0 dddd address_src *** add rd,address_src(rs) */ +{ +#ifdef NICENAMES +"add rd,address_src(rs)",16,10,0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,2}, + +/* 0000 0001 0000 dddd imm16 *** add rd,imm16 */ +{ +#ifdef NICENAMES +"add rd,imm16",16,7,0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,2}, + +/* 1000 0001 ssss dddd *** add rd,rs */ +{ +#ifdef NICENAMES +"add rd,rs",16,4,0x3c, +#endif +"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, + +/* 0000 0000 ssN0 dddd *** addb rbd,@rs */ +{ +#ifdef NICENAMES +"addb rbd,@rs",8,7,0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,3}, + +/* 0100 0000 0000 dddd address_src *** addb rbd,address_src */ +{ +#ifdef NICENAMES +"addb rbd,address_src",8,9,0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,3}, + +/* 0100 0000 ssN0 dddd address_src *** addb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"addb rbd,address_src(rs)",8,10,0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,3}, + +/* 0000 0000 0000 dddd imm8 imm8 *** addb rbd,imm8 */ +{ +#ifdef NICENAMES +"addb rbd,imm8",8,7,0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,3}, + +/* 1000 0000 ssss dddd *** addb rbd,rbs */ +{ +#ifdef NICENAMES +"addb rbd,rbs",8,4,0x3f, +#endif +"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,3}, + +/* 0001 0110 ssN0 dddd *** addl rrd,@rs */ +{ +#ifdef NICENAMES +"addl rrd,@rs",32,14,0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,4}, + +/* 0101 0110 0000 dddd address_src *** addl rrd,address_src */ +{ +#ifdef NICENAMES +"addl rrd,address_src",32,15,0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,4}, + +/* 0101 0110 ssN0 dddd address_src *** addl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"addl rrd,address_src(rs)",32,16,0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,4}, + +/* 0001 0110 0000 dddd imm32 *** addl rrd,imm32 */ +{ +#ifdef NICENAMES +"addl rrd,imm32",32,14,0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,4}, + +/* 1001 0110 ssss dddd *** addl rrd,rrs */ +{ +#ifdef NICENAMES +"addl rrd,rrs",32,8,0x3c, +#endif +"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,4}, + +/* 0000 0111 ssN0 dddd *** and rd,@rs */ +{ +#ifdef NICENAMES +"and rd,@rs",16,7,0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,5}, + +/* 0100 0111 0000 dddd address_src *** and rd,address_src */ +{ +#ifdef NICENAMES +"and rd,address_src",16,9,0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,5}, + +/* 0100 0111 ssN0 dddd address_src *** and rd,address_src(rs) */ +{ +#ifdef NICENAMES +"and rd,address_src(rs)",16,10,0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,5}, + +/* 0000 0111 0000 dddd imm16 *** and rd,imm16 */ +{ +#ifdef NICENAMES +"and rd,imm16",16,7,0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5}, + +/* 1000 0111 ssss dddd *** and rd,rs */ +{ +#ifdef NICENAMES +"and rd,rs",16,4,0x18, +#endif +"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,5}, + +/* 0000 0110 ssN0 dddd *** andb rbd,@rs */ +{ +#ifdef NICENAMES +"andb rbd,@rs",8,7,0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, + +/* 0100 0110 0000 dddd address_src *** andb rbd,address_src */ +{ +#ifdef NICENAMES +"andb rbd,address_src",8,9,0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,6}, + +/* 0100 0110 ssN0 dddd address_src *** andb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"andb rbd,address_src(rs)",8,10,0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,6}, + +/* 0000 0110 0000 dddd imm8 imm8 *** andb rbd,imm8 */ +{ +#ifdef NICENAMES +"andb rbd,imm8",8,7,0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,6}, + +/* 1000 0110 ssss dddd *** andb rbd,rbs */ +{ +#ifdef NICENAMES +"andb rbd,rbs",8,4,0x1c, +#endif +"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, + +/* 0010 0111 ddN0 imm4 *** bit @rd,imm4 */ +{ +#ifdef NICENAMES +"bit @rd,imm4",16,8,0x10, +#endif +"bit",OPC_bit,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,7}, + +/* 0110 0111 ddN0 imm4 address_dst *** bit address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"bit address_dst(rd),imm4",16,11,0x10, +#endif +"bit",OPC_bit,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,7}, + +/* 0110 0111 0000 imm4 address_dst *** bit address_dst,imm4 */ +{ +#ifdef NICENAMES +"bit address_dst,imm4",16,10,0x10, +#endif +"bit",OPC_bit,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,7}, + +/* 1010 0111 dddd imm4 *** bit rd,imm4 */ +{ +#ifdef NICENAMES +"bit rd,imm4",16,4,0x10, +#endif +"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,7}, + +/* 0010 0111 0000 ssss 0000 dddd 0000 0000 *** bit rd,rs */ +{ +#ifdef NICENAMES +"bit rd,rs",16,10,0x10, +#endif +"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,7}, + +/* 0010 0110 ddN0 imm4 *** bitb @rd,imm4 */ +{ +#ifdef NICENAMES +"bitb @rd,imm4",8,8,0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,8}, + +/* 0110 0110 ddN0 imm4 address_dst *** bitb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"bitb address_dst(rd),imm4",8,11,0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,8}, + +/* 0110 0110 0000 imm4 address_dst *** bitb address_dst,imm4 */ +{ +#ifdef NICENAMES +"bitb address_dst,imm4",8,10,0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,8}, + +/* 1010 0110 dddd imm4 *** bitb rbd,imm4 */ +{ +#ifdef NICENAMES +"bitb rbd,imm4",8,4,0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,8}, + +/* 0010 0110 0000 ssss 0000 dddd 0000 0000 *** bitb rbd,rs */ +{ +#ifdef NICENAMES +"bitb rbd,rs",8,10,0x10, +#endif +"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,8}, + +/* 0011 0110 0000 0000 *** bpt */ +{ +#ifdef NICENAMES +"bpt",8,2,0x00, +#endif +"bpt",OPC_bpt,0,{0}, + {CLASS_BIT+3,CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,9}, + +/* 0000 1111 0000 1100 *** brk */ +{ +#ifdef NICENAMES +"brk",8,10,0x00, +#endif +"brk",OPC_brk,0,{0}, + {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0xc,0,0,0,0,0,},0,2,10}, + +/* 0001 1111 ddN0 0000 *** call @rd */ +{ +#ifdef NICENAMES +"call @rd",32,10,0x00, +#endif +"call",OPC_call,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,11}, + +/* 0101 1111 0000 0000 address_dst *** call address_dst */ +{ +#ifdef NICENAMES +"call address_dst",32,12,0x00, +#endif +"call",OPC_call,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,11}, + +/* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */ +{ +#ifdef NICENAMES +"call address_dst(rd)",32,13,0x00, +#endif +"call",OPC_call,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,11}, + +/* 1101 disp12 *** calr disp12 */ +{ +#ifdef NICENAMES +"calr disp12",16,10,0x00, +#endif +"calr",OPC_calr,0,{CLASS_DISP,}, + {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,12}, + +/* 0000 1101 ddN0 1000 *** clr @rd */ +{ +#ifdef NICENAMES +"clr @rd",16,8,0x00, +#endif +"clr",OPC_clr,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, + +/* 0100 1101 0000 1000 address_dst *** clr address_dst */ +{ +#ifdef NICENAMES +"clr address_dst",16,11,0x00, +#endif +"clr",OPC_clr,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, + +/* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */ +{ +#ifdef NICENAMES +"clr address_dst(rd)",16,12,0x00, +#endif +"clr",OPC_clr,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,13}, + +/* 1000 1101 dddd 1000 *** clr rd */ +{ +#ifdef NICENAMES +"clr rd",16,7,0x00, +#endif +"clr",OPC_clr,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,13}, + +/* 0000 1100 ddN0 1000 *** clrb @rd */ +{ +#ifdef NICENAMES +"clrb @rd",8,8,0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,14}, + +/* 0100 1100 0000 1000 address_dst *** clrb address_dst */ +{ +#ifdef NICENAMES +"clrb address_dst",8,11,0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, + +/* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */ +{ +#ifdef NICENAMES +"clrb address_dst(rd)",8,12,0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,14}, + +/* 1000 1100 dddd 1000 *** clrb rbd */ +{ +#ifdef NICENAMES +"clrb rbd",8,7,0x00, +#endif +"clrb",OPC_clrb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,14}, + +/* 0000 1101 ddN0 0000 *** com @rd */ +{ +#ifdef NICENAMES +"com @rd",16,12,0x18, +#endif +"com",OPC_com,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, + +/* 0100 1101 0000 0000 address_dst *** com address_dst */ +{ +#ifdef NICENAMES +"com address_dst",16,15,0x18, +#endif +"com",OPC_com,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, + +/* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */ +{ +#ifdef NICENAMES +"com address_dst(rd)",16,16,0x18, +#endif +"com",OPC_com,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,15}, + +/* 1000 1101 dddd 0000 *** com rd */ +{ +#ifdef NICENAMES +"com rd",16,7,0x18, +#endif +"com",OPC_com,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,15}, + +/* 0000 1100 ddN0 0000 *** comb @rd */ +{ +#ifdef NICENAMES +"comb @rd",8,12,0x1c, +#endif +"comb",OPC_comb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,16}, + +/* 0100 1100 0000 0000 address_dst *** comb address_dst */ +{ +#ifdef NICENAMES +"comb address_dst",8,15,0x1c, +#endif +"comb",OPC_comb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,16}, + +/* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */ +{ +#ifdef NICENAMES +"comb address_dst(rd)",8,16,0x1c, +#endif +"comb",OPC_comb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,16}, + +/* 1000 1100 dddd 0000 *** comb rbd */ +{ +#ifdef NICENAMES +"comb rbd",8,7,0x1c, +#endif +"comb",OPC_comb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,16}, + +/* 1000 1101 flags 0101 *** comflg flags */ +{ +#ifdef NICENAMES +"comflg flags",16,7,0x3c, +#endif +"comflg",OPC_comflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,17}, + +/* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */ +{ +#ifdef NICENAMES +"cp @rd,imm16",16,11,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,18}, + +/* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */ +{ +#ifdef NICENAMES +"cp address_dst(rd),imm16",16,15,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,18}, + +/* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */ +{ +#ifdef NICENAMES +"cp address_dst,imm16",16,14,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,18}, + +/* 0000 1011 ssN0 dddd *** cp rd,@rs */ +{ +#ifdef NICENAMES +"cp rd,@rs",16,7,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, + +/* 0100 1011 0000 dddd address_src *** cp rd,address_src */ +{ +#ifdef NICENAMES +"cp rd,address_src",16,9,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, + +/* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */ +{ +#ifdef NICENAMES +"cp rd,address_src(rs)",16,10,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, + +/* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */ +{ +#ifdef NICENAMES +"cp rd,imm16",16,7,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,18}, + +/* 1000 1011 ssss dddd *** cp rd,rs */ +{ +#ifdef NICENAMES +"cp rd,rs",16,4,0x3c, +#endif +"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,18}, + +/* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */ +{ +#ifdef NICENAMES +"cpb @rd,imm8",8,11,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,19}, + +/* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */ +{ +#ifdef NICENAMES +"cpb address_dst(rd),imm8",8,15,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,19}, + +/* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */ +{ +#ifdef NICENAMES +"cpb address_dst,imm8",8,14,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,19}, + +/* 0000 1010 ssN0 dddd *** cpb rbd,@rs */ +{ +#ifdef NICENAMES +"cpb rbd,@rs",8,7,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,19}, + +/* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */ +{ +#ifdef NICENAMES +"cpb rbd,address_src",8,9,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, + +/* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"cpb rbd,address_src(rs)",8,10,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, + +/* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */ +{ +#ifdef NICENAMES +"cpb rbd,imm8",8,7,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,19}, + +/* 1000 1010 ssss dddd *** cpb rbd,rbs */ +{ +#ifdef NICENAMES +"cpb rbd,rbs",8,4,0x3c, +#endif +"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,19}, + +/* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpd rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpd",OPC_cpd,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,20}, + +/* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdb rbd,@rs,rr,cc",8,11,0x3c, +#endif +"cpdb",OPC_cpdb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,21}, + +/* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdr rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpdr",OPC_cpdr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,22}, + +/* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpdrb rbd,@rs,rr,cc",8,11,0x3c, +#endif +"cpdrb",OPC_cpdrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,23}, + +/* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpi rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpi",OPC_cpi,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,24}, + +/* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpib rbd,@rs,rr,cc",8,11,0x3c, +#endif +"cpib",OPC_cpib,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,25}, + +/* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpir rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpir",OPC_cpir,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,26}, + +/* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpirb rbd,@rs,rr,cc",8,11,0x3c, +#endif +"cpirb",OPC_cpirb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,27}, + +/* 0001 0000 ssN0 dddd *** cpl rrd,@rs */ +{ +#ifdef NICENAMES +"cpl rrd,@rs",32,14,0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,28}, + +/* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */ +{ +#ifdef NICENAMES +"cpl rrd,address_src",32,15,0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,28}, + +/* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"cpl rrd,address_src(rs)",32,16,0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,28}, + +/* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */ +{ +#ifdef NICENAMES +"cpl rrd,imm32",32,14,0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,28}, + +/* 1001 0000 ssss dddd *** cpl rrd,rrs */ +{ +#ifdef NICENAMES +"cpl rrd,rrs",32,8,0x3c, +#endif +"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,28}, + +/* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsd @rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpsd",OPC_cpsd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,29}, + +/* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdb @rd,@rs,rr,cc",8,11,0x3c, +#endif +"cpsdb",OPC_cpsdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,30}, + +/* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdr @rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpsdr",OPC_cpsdr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,31}, + +/* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsdrb @rd,@rs,rr,cc",8,11,0x3c, +#endif +"cpsdrb",OPC_cpsdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,32}, + +/* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsi @rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpsi",OPC_cpsi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,33}, + +/* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsib @rd,@rs,rr,cc",8,11,0x3c, +#endif +"cpsib",OPC_cpsib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,34}, + +/* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsir @rd,@rs,rr,cc",16,11,0x3c, +#endif +"cpsir",OPC_cpsir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,35}, + +/* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */ +{ +#ifdef NICENAMES +"cpsirb @rd,@rs,rr,cc",8,11,0x3c, +#endif +"cpsirb",OPC_cpsirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,36}, + +/* 1011 0000 dddd 0000 *** dab rbd */ +{ +#ifdef NICENAMES +"dab rbd",8,5,0x38, +#endif +"dab",OPC_dab,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,37}, + +/* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */ +{ +#ifdef NICENAMES +"dbjnz rbd,disp7",16,11,0x00, +#endif +"dbjnz",OPC_dbjnz,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,38}, + +/* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */ +{ +#ifdef NICENAMES +"dec @rd,imm4m1",16,11,0x1c, +#endif +"dec",OPC_dec,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, + +/* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"dec address_dst(rd),imm4m1",16,14,0x1c, +#endif +"dec",OPC_dec,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, + +/* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"dec address_dst,imm4m1",16,13,0x1c, +#endif +"dec",OPC_dec,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,39}, + +/* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */ +{ +#ifdef NICENAMES +"dec rd,imm4m1",16,4,0x1c, +#endif +"dec",OPC_dec,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,39}, + +/* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */ +{ +#ifdef NICENAMES +"decb @rd,imm4m1",8,11,0x1c, +#endif +"decb",OPC_decb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,40}, + +/* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"decb address_dst(rd),imm4m1",8,14,0x1c, +#endif +"decb",OPC_decb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,40}, + +/* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"decb address_dst,imm4m1",8,13,0x1c, +#endif +"decb",OPC_decb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,40}, + +/* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */ +{ +#ifdef NICENAMES +"decb rbd,imm4m1",8,4,0x1c, +#endif +"decb",OPC_decb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,40}, + +/* 0111 1100 0000 00ii *** di i2 */ +{ +#ifdef NICENAMES +"di i2",16,7,0x00, +#endif +"di",OPC_di,0,{CLASS_IMM+(ARG_IMM2),}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,41}, + +/* 0001 1011 ssN0 dddd *** div rrd,@rs */ +{ +#ifdef NICENAMES +"div rrd,@rs",16,107,0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, + +/* 0101 1011 0000 dddd address_src *** div rrd,address_src */ +{ +#ifdef NICENAMES +"div rrd,address_src",16,107,0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, + +/* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"div rrd,address_src(rs)",16,107,0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,42}, + +/* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */ +{ +#ifdef NICENAMES +"div rrd,imm16",16,107,0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,42}, + +/* 1001 1011 ssss dddd *** div rrd,rs */ +{ +#ifdef NICENAMES +"div rrd,rs",16,107,0x3c, +#endif +"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,42}, + +/* 0001 1010 ssN0 dddd *** divl rqd,@rs */ +{ +#ifdef NICENAMES +"divl rqd,@rs",32,744,0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,43}, + +/* 0101 1010 0000 dddd address_src *** divl rqd,address_src */ +{ +#ifdef NICENAMES +"divl rqd,address_src",32,745,0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,43}, + +/* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */ +{ +#ifdef NICENAMES +"divl rqd,address_src(rs)",32,746,0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,43}, + +/* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */ +{ +#ifdef NICENAMES +"divl rqd,imm32",32,744,0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,43}, + +/* 1001 1010 ssss dddd *** divl rqd,rrs */ +{ +#ifdef NICENAMES +"divl rqd,rrs",32,744,0x3c, +#endif +"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,43}, + +/* 1111 dddd 1disp7 *** djnz rd,disp7 */ +{ +#ifdef NICENAMES +"djnz rd,disp7",16,11,0x00, +#endif +"djnz",OPC_djnz,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,44}, + +/* 0111 1100 0000 01ii *** ei i2 */ +{ +#ifdef NICENAMES +"ei i2",16,7,0x00, +#endif +"ei",OPC_ei,0,{CLASS_IMM+(ARG_IMM2),}, + {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,45}, + +/* 0010 1101 ssN0 dddd *** ex rd,@rs */ +{ +#ifdef NICENAMES +"ex rd,@rs",16,12,0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, + +/* 0110 1101 0000 dddd address_src *** ex rd,address_src */ +{ +#ifdef NICENAMES +"ex rd,address_src",16,15,0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, + +/* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */ +{ +#ifdef NICENAMES +"ex rd,address_src(rs)",16,16,0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,46}, + +/* 1010 1101 ssss dddd *** ex rd,rs */ +{ +#ifdef NICENAMES +"ex rd,rs",16,6,0x00, +#endif +"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,46}, + +/* 0010 1100 ssN0 dddd *** exb rbd,@rs */ +{ +#ifdef NICENAMES +"exb rbd,@rs",8,12,0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,47}, + +/* 0110 1100 0000 dddd address_src *** exb rbd,address_src */ +{ +#ifdef NICENAMES +"exb rbd,address_src",8,15,0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,47}, + +/* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"exb rbd,address_src(rs)",8,16,0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,47}, + +/* 1010 1100 ssss dddd *** exb rbd,rbs */ +{ +#ifdef NICENAMES +"exb rbd,rbs",8,6,0x00, +#endif +"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,47}, + +/* 0000 1110 imm8 *** ext0e imm8 */ +{ +#ifdef NICENAMES +"ext0e imm8",8,10,0x00, +#endif +"ext0e",OPC_ext0e,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,48}, + +/* 0000 1111 imm8 *** ext0f imm8 */ +{ +#ifdef NICENAMES +"ext0f imm8",8,10,0x00, +#endif +"ext0f",OPC_ext0f,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,49}, + +/* 1000 1110 imm8 *** ext8e imm8 */ +{ +#ifdef NICENAMES +"ext8e imm8",8,10,0x00, +#endif +"ext8e",OPC_ext8e,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,50}, + +/* 1000 1111 imm8 *** ext8f imm8 */ +{ +#ifdef NICENAMES +"ext8f imm8",8,10,0x00, +#endif +"ext8f",OPC_ext8f,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,51}, + +/* 1011 0001 dddd 1010 *** exts rrd */ +{ +#ifdef NICENAMES +"exts rrd",16,11,0x00, +#endif +"exts",OPC_exts,0,{CLASS_REG_LONG+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,52}, + +/* 1011 0001 dddd 0000 *** extsb rd */ +{ +#ifdef NICENAMES +"extsb rd",8,11,0x00, +#endif +"extsb",OPC_extsb,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, + +/* 1011 0001 dddd 0111 *** extsl rqd */ +{ +#ifdef NICENAMES +"extsl rqd",32,11,0x00, +#endif +"extsl",OPC_extsl,0,{CLASS_REG_QUAD+(ARG_RD),}, + {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,54}, + +/* 0111 1010 0000 0000 *** halt */ +{ +#ifdef NICENAMES +"halt",16,8,0x00, +#endif +"halt",OPC_halt,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,55}, + +/* 0011 1101 ssss dddd *** in rd,@ri */ +{ +#ifdef NICENAMES +"in rd,@ri",16,10,0x00, +#endif +"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IRO+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,56}, + +/* 0011 1011 dddd 0100 imm16 *** in rd,imm16 */ +{ +#ifdef NICENAMES +"in rd,imm16",16,12,0x00, +#endif +"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,56}, + +/* 0011 1100 ssss dddd *** inb rbd,@ri */ +{ +#ifdef NICENAMES +"inb rbd,@ri",8,12,0x00, +#endif +"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IRO+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,57}, + +/* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */ +{ +#ifdef NICENAMES +"inb rbd,imm16",8,10,0x00, +#endif +"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,57}, + +/* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */ +{ +#ifdef NICENAMES +"inc @rd,imm4m1",16,11,0x1c, +#endif +"inc",OPC_inc,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, + +/* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"inc address_dst(rd),imm4m1",16,14,0x1c, +#endif +"inc",OPC_inc,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, + +/* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"inc address_dst,imm4m1",16,13,0x1c, +#endif +"inc",OPC_inc,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,58}, + +/* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */ +{ +#ifdef NICENAMES +"inc rd,imm4m1",16,4,0x1c, +#endif +"inc",OPC_inc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,58}, + +/* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */ +{ +#ifdef NICENAMES +"incb @rd,imm4m1",8,11,0x1c, +#endif +"incb",OPC_incb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,59}, + +/* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */ +{ +#ifdef NICENAMES +"incb address_dst(rd),imm4m1",8,14,0x1c, +#endif +"incb",OPC_incb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,59}, + +/* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */ +{ +#ifdef NICENAMES +"incb address_dst,imm4m1",8,13,0x1c, +#endif +"incb",OPC_incb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,59}, + +/* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */ +{ +#ifdef NICENAMES +"incb rbd,imm4m1",8,4,0x1c, +#endif +"incb",OPC_incb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, + {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,59}, + +/* 0011 1011 ssss 1000 0000 aaaa ddN0 1000 *** ind @rd,@ri,ra */ +{ +#ifdef NICENAMES +"ind @rd,@ri,ra",16,21,0x04, +#endif +"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,60}, + +/* 0011 1010 ssss 1000 0000 aaaa ddN0 1000 *** indb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indb @rd,@ri,ra",8,21,0x04, +#endif +"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,61}, + +/* 0011 1011 ssss 1000 0000 aaaa ddN0 0000 *** indr @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indr @rd,@ri,ra",16,11,0x04, +#endif +"indr",OPC_indr,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,62}, + +/* 0011 1010 ssss 1000 0000 aaaa ddN0 0000 *** indrb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"indrb @rd,@ri,ra",8,11,0x04, +#endif +"indrb",OPC_indrb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,63}, + +/* 0011 1011 ssss 0000 0000 aaaa ddN0 1000 *** ini @rd,@ri,ra */ +{ +#ifdef NICENAMES +"ini @rd,@ri,ra",16,21,0x04, +#endif +"ini",OPC_ini,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,64}, + +/* 0011 1010 ssss 0000 0000 aaaa ddN0 1000 *** inib @rd,@ri,ra */ +{ +#ifdef NICENAMES +"inib @rd,@ri,ra",8,21,0x04, +#endif +"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,65}, + +/* 0011 1011 ssss 0000 0000 aaaa ddN0 0000 *** inir @rd,@ri,ra */ +{ +#ifdef NICENAMES +"inir @rd,@ri,ra",16,11,0x04, +#endif +"inir",OPC_inir,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,66}, + +/* 0011 1010 ssss 0000 0000 aaaa ddN0 0000 *** inirb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"inirb @rd,@ri,ra",8,11,0x04, +#endif +"inirb",OPC_inirb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,67}, + +/* 0111 1011 0000 0000 *** iret */ +{ +#ifdef NICENAMES +"iret",16,13,0x3f, +#endif +"iret",OPC_iret,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,68}, + +/* 0001 1110 ddN0 cccc *** jp cc,@rd */ +{ +#ifdef NICENAMES +"jp cc,@rd",16,10,0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,69}, + +/* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */ +{ +#ifdef NICENAMES +"jp cc,address_dst",16,7,0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, + +/* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */ +{ +#ifdef NICENAMES +"jp cc,address_dst(rd)",16,8,0x00, +#endif +"jp",OPC_jp,0,{CLASS_CC,CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,69}, + +/* 1110 cccc disp8 *** jr cc,disp8 */ +{ +#ifdef NICENAMES +"jr cc,disp8",16,6,0x00, +#endif +"jr",OPC_jr,0,{CLASS_CC,CLASS_DISP,}, + {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,70}, + +/* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */ +{ +#ifdef NICENAMES +"ld @rd,imm16",16,7,0x00, +#endif +"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, + +/* 0010 1111 ddN0 ssss *** ld @rd,rs */ +{ +#ifdef NICENAMES +"ld @rd,rs",16,8,0x00, +#endif +"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,71}, + +/* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */ +{ +#ifdef NICENAMES +"ld address_dst(rd),imm16",16,15,0x00, +#endif +"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,71}, + +/* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */ +{ +#ifdef NICENAMES +"ld address_dst(rd),rs",16,12,0x00, +#endif +"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,71}, + +/* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */ +{ +#ifdef NICENAMES +"ld address_dst,imm16",16,14,0x00, +#endif +"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,71}, + +/* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */ +{ +#ifdef NICENAMES +"ld address_dst,rs",16,11,0x00, +#endif +"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,71}, + +/* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */ +{ +#ifdef NICENAMES +"ld rd(imm16),rs",16,14,0x00, +#endif +"ld",OPC_ld,0,{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, + +/* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */ +{ +#ifdef NICENAMES +"ld rd(rx),rs",16,14,0x00, +#endif +"ld",OPC_ld,0,{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,71}, + +/* 0010 0001 ssN0 dddd *** ld rd,@rs */ +{ +#ifdef NICENAMES +"ld rd,@rs",16,7,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,71}, + +/* 0110 0001 0000 dddd address_src *** ld rd,address_src */ +{ +#ifdef NICENAMES +"ld rd,address_src",16,9,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, + +/* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */ +{ +#ifdef NICENAMES +"ld rd,address_src(rs)",16,10,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, + +/* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */ +{ +#ifdef NICENAMES +"ld rd,imm16",16,7,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, + +/* 1010 0001 ssss dddd *** ld rd,rs */ +{ +#ifdef NICENAMES +"ld rd,rs",16,3,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,71}, + +/* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */ +{ +#ifdef NICENAMES +"ld rd,rs(imm16)",16,14,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,71}, + +/* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */ +{ +#ifdef NICENAMES +"ld rd,rs(rx)",16,14,0x00, +#endif +"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,71}, + +/* 0111 0110 0000 dddd address_src *** lda prd,address_src */ +{ +#ifdef NICENAMES +"lda prd,address_src",16,12,0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, + +/* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */ +{ +#ifdef NICENAMES +"lda prd,address_src(rs)",16,13,0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, + +/* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */ +{ +#ifdef NICENAMES +"lda prd,rs(imm16)",16,15,0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,72}, + +/* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */ +{ +#ifdef NICENAMES +"lda prd,rs(rx)",16,15,0x00, +#endif +"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,72}, + +/* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */ +{ +#ifdef NICENAMES +"ldar prd,disp16",16,15,0x00, +#endif +"ldar",OPC_ldar,0,{CLASS_PR+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,73}, + +/* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */ +{ +#ifdef NICENAMES +"ldb @rd,imm8",8,7,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74}, + +/* 0010 1110 ddN0 ssss *** ldb @rd,rbs */ +{ +#ifdef NICENAMES +"ldb @rd,rbs",8,8,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,74}, + +/* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */ +{ +#ifdef NICENAMES +"ldb address_dst(rd),imm8",8,15,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,74}, + +/* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */ +{ +#ifdef NICENAMES +"ldb address_dst(rd),rbs",8,12,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,74}, + +/* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */ +{ +#ifdef NICENAMES +"ldb address_dst,imm8",8,14,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,74}, + +/* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */ +{ +#ifdef NICENAMES +"ldb address_dst,rbs",8,11,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,74}, + +/* 0010 0000 ssN0 dddd *** ldb rbd,@rs */ +{ +#ifdef NICENAMES +"ldb rbd,@rs",8,7,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, + +/* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */ +{ +#ifdef NICENAMES +"ldb rbd,address_src",8,9,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,74}, + +/* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"ldb rbd,address_src(rs)",8,10,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,74}, + +/* 1100 dddd imm8 *** ldb rbd,imm8 */ +{ +#ifdef NICENAMES +"ldb rbd,imm8",8,5,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,74}, + +/* 0010 0000 0000 dddd imm8 imm8 *** ldb rbd,imm8 */ +{ +#ifdef NICENAMES +"ldb rbd,imm8",8,7,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74}, + +/* 1010 0000 ssss dddd *** ldb rbd,rbs */ +{ +#ifdef NICENAMES +"ldb rbd,rbs",8,3,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, + +/* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */ +{ +#ifdef NICENAMES +"ldb rbd,rs(imm16)",8,14,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,74}, + +/* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */ +{ +#ifdef NICENAMES +"ldb rbd,rs(rx)",8,14,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,74}, + +/* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */ +{ +#ifdef NICENAMES +"ldb rd(imm16),rbs",8,14,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,74}, + +/* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */ +{ +#ifdef NICENAMES +"ldb rd(rx),rbs",8,14,0x00, +#endif +"ldb",OPC_ldb,0,{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,74}, + +/* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */ +{ +#ifdef NICENAMES +"ldctl ctrl,rs",32,7,0x00, +#endif +"ldctl",OPC_ldctl,0,{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,75}, + +/* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */ +{ +#ifdef NICENAMES +"ldctl rd,ctrl",32,7,0x00, +#endif +"ldctl",OPC_ldctl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, + {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,75}, + +/* 1000 1100 ssss 1001 *** ldctlb ctrl,rbs */ +{ +#ifdef NICENAMES +"ldctlb ctrl,rbs",32,7,0x3f, +#endif +"ldctlb",OPC_ldctlb,0,{CLASS_CTRL,CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_BIT+9,0,0,0,0,0,},2,2,76}, + +/* 1000 1100 dddd 0001 *** ldctlb rbd,ctrl */ +{ +#ifdef NICENAMES +"ldctlb rbd,ctrl",32,7,0x00, +#endif +"ldctlb",OPC_ldctlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_CTRL,}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+1,0,0,0,0,0,},2,2,76}, + +/* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldd @rd,@rs,rr",16,11,0x04, +#endif +"ldd",OPC_ldd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,77}, + +/* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddb @rd,@rs,rr",8,11,0x04, +#endif +"lddb",OPC_lddb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,78}, + +/* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddr @rd,@rs,rr",16,11,0x04, +#endif +"lddr",OPC_lddr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,79}, + +/* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"lddrb @rd,@rs,rr",8,11,0x04, +#endif +"lddrb",OPC_lddrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,80}, + +/* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldi @rd,@rs,rr",16,11,0x04, +#endif +"ldi",OPC_ldi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,81}, + +/* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldib @rd,@rs,rr",8,11,0x04, +#endif +"ldib",OPC_ldib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,82}, + +/* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldir @rd,@rs,rr",16,11,0x04, +#endif +"ldir",OPC_ldir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,83}, + +/* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */ +{ +#ifdef NICENAMES +"ldirb @rd,@rs,rr",8,11,0x04, +#endif +"ldirb",OPC_ldirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,84}, + +/* 1011 1101 dddd imm4 *** ldk rd,imm4 */ +{ +#ifdef NICENAMES +"ldk rd,imm4",16,5,0x00, +#endif +"ldk",OPC_ldk,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,85}, + +/* 0001 1101 ddN0 ssss *** ldl @rd,rrs */ +{ +#ifdef NICENAMES +"ldl @rd,rrs",32,11,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,86}, + +/* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */ +{ +#ifdef NICENAMES +"ldl address_dst(rd),rrs",32,14,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,86}, + +/* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */ +{ +#ifdef NICENAMES +"ldl address_dst,rrs",32,15,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_DA+(ARG_DST),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,86}, + +/* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */ +{ +#ifdef NICENAMES +"ldl rd(imm16),rrs",32,17,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,86}, + +/* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */ +{ +#ifdef NICENAMES +"ldl rd(rx),rrs",32,17,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,86}, + +/* 0001 0100 ssN0 dddd *** ldl rrd,@rs */ +{ +#ifdef NICENAMES +"ldl rrd,@rs",32,11,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86}, + +/* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */ +{ +#ifdef NICENAMES +"ldl rrd,address_src",32,12,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,86}, + +/* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"ldl rrd,address_src(rs)",32,13,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,86}, + +/* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */ +{ +#ifdef NICENAMES +"ldl rrd,imm32",32,11,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,86}, + +/* 1001 0100 ssss dddd *** ldl rrd,rrs */ +{ +#ifdef NICENAMES +"ldl rrd,rrs",32,5,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,86}, + +/* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */ +{ +#ifdef NICENAMES +"ldl rrd,rs(imm16)",32,17,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,86}, + +/* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */ +{ +#ifdef NICENAMES +"ldl rrd,rs(rx)",32,17,0x00, +#endif +"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,86}, + +/* 0001 1100 ddN0 1001 0000 ssss 0000 imm4m1 *** ldm @rd,rs,n */ +{ +#ifdef NICENAMES +"ldm @rd,rs,n",16,11,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,87}, + +/* 0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst(rd),rs,n */ +{ +#ifdef NICENAMES +"ldm address_dst(rd),rs,n",16,15,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,87}, + +/* 0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst *** ldm address_dst,rs,n */ +{ +#ifdef NICENAMES +"ldm address_dst,rs,n",16,14,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),},3,6,87}, + +/* 0001 1100 ssN0 0001 0000 dddd 0000 imm4m1 *** ldm rd,@rs,n */ +{ +#ifdef NICENAMES +"ldm rd,@rs,n",16,11,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),0,},3,4,87}, + +/* 0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src(rs),n */ +{ +#ifdef NICENAMES +"ldm rd,address_src(rs),n",16,15,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,87}, + +/* 0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src *** ldm rd,address_src,n */ +{ +#ifdef NICENAMES +"ldm rd,address_src,n",16,14,0x00, +#endif +"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMM4M1),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_SRC),},3,6,87}, + +/* 0011 1001 ssN0 0000 *** ldps @rs */ +{ +#ifdef NICENAMES +"ldps @rs",16,12,0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_IR+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,88}, + +/* 0111 1001 0000 0000 address_src *** ldps address_src */ +{ +#ifdef NICENAMES +"ldps address_src",16,16,0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,88}, + +/* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */ +{ +#ifdef NICENAMES +"ldps address_src(rs)",16,17,0x3f, +#endif +"ldps",OPC_ldps,0,{CLASS_X+(ARG_RS),}, + {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,88}, + +/* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */ +{ +#ifdef NICENAMES +"ldr disp16,rs",16,14,0x00, +#endif +"ldr",OPC_ldr,0,{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,89}, + +/* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */ +{ +#ifdef NICENAMES +"ldr rd,disp16",16,14,0x00, +#endif +"ldr",OPC_ldr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,89}, + +/* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */ +{ +#ifdef NICENAMES +"ldrb disp16,rbs",8,14,0x00, +#endif +"ldrb",OPC_ldrb,0,{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,90}, + +/* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */ +{ +#ifdef NICENAMES +"ldrb rbd,disp16",8,14,0x00, +#endif +"ldrb",OPC_ldrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,90}, + +/* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */ +{ +#ifdef NICENAMES +"ldrl disp16,rrs",32,17,0x00, +#endif +"ldrl",OPC_ldrl,0,{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,91}, + +/* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */ +{ +#ifdef NICENAMES +"ldrl rrd,disp16",32,17,0x00, +#endif +"ldrl",OPC_ldrl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, + {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,91}, + +/* 0111 1011 0000 1010 *** mbit */ +{ +#ifdef NICENAMES +"mbit",16,7,0x38, +#endif +"mbit",OPC_mbit,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,92}, + +/* 0111 1011 dddd 1101 *** mreq rd */ +{ +#ifdef NICENAMES +"mreq rd",16,12,0x18, +#endif +"mreq",OPC_mreq,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,93}, + +/* 0111 1011 0000 1001 *** mres */ +{ +#ifdef NICENAMES +"mres",16,5,0x00, +#endif +"mres",OPC_mres,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,94}, + +/* 0111 1011 0000 1000 *** mset */ +{ +#ifdef NICENAMES +"mset",16,5,0x00, +#endif +"mset",OPC_mset,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,95}, + +/* 0001 1001 ssN0 dddd *** mult rrd,@rs */ +{ +#ifdef NICENAMES +"mult rrd,@rs",16,70,0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, + +/* 0101 1001 0000 dddd address_src *** mult rrd,address_src */ +{ +#ifdef NICENAMES +"mult rrd,address_src",16,70,0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, + +/* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"mult rrd,address_src(rs)",16,70,0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,96}, + +/* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */ +{ +#ifdef NICENAMES +"mult rrd,imm16",16,70,0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,96}, + +/* 1001 1001 ssss dddd *** mult rrd,rs */ +{ +#ifdef NICENAMES +"mult rrd,rs",16,70,0x3c, +#endif +"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,96}, + +/* 0001 1000 ssN0 dddd *** multl rqd,@rs */ +{ +#ifdef NICENAMES +"multl rqd,@rs",32,282,0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, + +/* 0101 1000 0000 dddd address_src *** multl rqd,address_src */ +{ +#ifdef NICENAMES +"multl rqd,address_src",32,282,0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, + +/* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */ +{ +#ifdef NICENAMES +"multl rqd,address_src(rs)",32,282,0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,97}, + +/* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */ +{ +#ifdef NICENAMES +"multl rqd,imm32",32,282,0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,97}, + +/* 1001 1000 ssss dddd *** multl rqd,rrs */ +{ +#ifdef NICENAMES +"multl rqd,rrs",32,282,0x3c, +#endif +"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,97}, + +/* 0000 1101 ddN0 0010 *** neg @rd */ +{ +#ifdef NICENAMES +"neg @rd",16,12,0x3c, +#endif +"neg",OPC_neg,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,98}, + +/* 0100 1101 0000 0010 address_dst *** neg address_dst */ +{ +#ifdef NICENAMES +"neg address_dst",16,15,0x3c, +#endif +"neg",OPC_neg,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,98}, + +/* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */ +{ +#ifdef NICENAMES +"neg address_dst(rd)",16,16,0x3c, +#endif +"neg",OPC_neg,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,98}, + +/* 1000 1101 dddd 0010 *** neg rd */ +{ +#ifdef NICENAMES +"neg rd",16,7,0x3c, +#endif +"neg",OPC_neg,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,98}, + +/* 0000 1100 ddN0 0010 *** negb @rd */ +{ +#ifdef NICENAMES +"negb @rd",8,12,0x3c, +#endif +"negb",OPC_negb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,99}, + +/* 0100 1100 0000 0010 address_dst *** negb address_dst */ +{ +#ifdef NICENAMES +"negb address_dst",8,15,0x3c, +#endif +"negb",OPC_negb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,99}, + +/* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */ +{ +#ifdef NICENAMES +"negb address_dst(rd)",8,16,0x3c, +#endif +"negb",OPC_negb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,99}, + +/* 1000 1100 dddd 0010 *** negb rbd */ +{ +#ifdef NICENAMES +"negb rbd",8,7,0x3c, +#endif +"negb",OPC_negb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,99}, + +/* 1000 1101 0000 0111 *** nop */ +{ +#ifdef NICENAMES +"nop",16,7,0x00, +#endif +"nop",OPC_nop,0,{0}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,100}, + +/* 0000 0101 ssN0 dddd *** or rd,@rs */ +{ +#ifdef NICENAMES +"or rd,@rs",16,7,0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,101}, + +/* 0100 0101 0000 dddd address_src *** or rd,address_src */ +{ +#ifdef NICENAMES +"or rd,address_src",16,9,0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,101}, + +/* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */ +{ +#ifdef NICENAMES +"or rd,address_src(rs)",16,10,0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,101}, + +/* 0000 0101 0000 dddd imm16 *** or rd,imm16 */ +{ +#ifdef NICENAMES +"or rd,imm16",16,7,0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,101}, + +/* 1000 0101 ssss dddd *** or rd,rs */ +{ +#ifdef NICENAMES +"or rd,rs",16,4,0x38, +#endif +"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,101}, + +/* 0000 0100 ssN0 dddd *** orb rbd,@rs */ +{ +#ifdef NICENAMES +"orb rbd,@rs",8,7,0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,102}, + +/* 0100 0100 0000 dddd address_src *** orb rbd,address_src */ +{ +#ifdef NICENAMES +"orb rbd,address_src",8,9,0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,102}, + +/* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"orb rbd,address_src(rs)",8,10,0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,102}, + +/* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */ +{ +#ifdef NICENAMES +"orb rbd,imm8",8,7,0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,102}, + +/* 1000 0100 ssss dddd *** orb rbd,rbs */ +{ +#ifdef NICENAMES +"orb rbd,rbs",8,4,0x3c, +#endif +"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,102}, + +/* 0011 1011 ssN0 1010 0000 aaaa dddd 0000 *** otdr @ro,@rs,ra */ +{ +#ifdef NICENAMES +"otdr @ro,@rs,ra",16,11,0x04, +#endif +"otdr",OPC_otdr,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,103}, + +/* 0011 1010 ssN0 1010 0000 aaaa dddd 0000 *** otdrb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"otdrb @ro,@rs,ra",8,11,0x04, +#endif +"otdrb",OPC_otdrb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,104}, + +/* 0011 1011 ssN0 0010 0000 aaaa dddd 0000 *** otir @ro,@rs,ra */ +{ +#ifdef NICENAMES +"otir @ro,@rs,ra",16,11,0x04, +#endif +"otir",OPC_otir,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,105}, + +/* 0011 1010 ssN0 0010 0000 aaaa dddd 0000 *** otirb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"otirb @ro,@rs,ra",8,11,0x04, +#endif +"otirb",OPC_otirb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,106}, + +/* 0011 1111 dddd ssss *** out @ro,rs */ +{ +#ifdef NICENAMES +"out @ro,rs",16,10,0x00, +#endif +"out",OPC_out,0,{CLASS_IRO+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,107}, + +/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ +{ +#ifdef NICENAMES +"out imm16,rs",16,12,0x00, +#endif +"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,107}, + +/* 0011 1110 dddd ssss *** outb @ro,rbs */ +{ +#ifdef NICENAMES +"outb @ro,rbs",8,10,0x00, +#endif +"outb",OPC_outb,0,{CLASS_IRO+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,108}, + +/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ +{ +#ifdef NICENAMES +"outb imm16,rbs",8,12,0x00, +#endif +"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,108}, + +/* 0011 1011 ssN0 1010 0000 aaaa dddd 1000 *** outd @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outd @ro,@rs,ra",16,21,0x04, +#endif +"outd",OPC_outd,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,109}, + +/* 0011 1010 ssN0 1010 0000 aaaa dddd 1000 *** outdb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outdb @ro,@rs,ra",8,21,0x04, +#endif +"outdb",OPC_outdb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,110}, + +/* 0011 1011 ssN0 0010 0000 aaaa dddd 1000 *** outi @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outi @ro,@rs,ra",16,21,0x04, +#endif +"outi",OPC_outi,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,111}, + +/* 0011 1010 ssN0 0010 0000 aaaa dddd 1000 *** outib @ro,@rs,ra */ +{ +#ifdef NICENAMES +"outib @ro,@rs,ra",8,21,0x04, +#endif +"outib",OPC_outib,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,112}, + +/* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */ +{ +#ifdef NICENAMES +"pop @rd,@rs",16,12,0x00, +#endif +"pop",OPC_pop,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,113}, + +/* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */ +{ +#ifdef NICENAMES +"pop address_dst(rd),@rs",16,16,0x00, +#endif +"pop",OPC_pop,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,113}, + +/* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */ +{ +#ifdef NICENAMES +"pop address_dst,@rs",16,16,0x00, +#endif +"pop",OPC_pop,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,113}, + +/* 1001 0111 ssN0 dddd *** pop rd,@rs */ +{ +#ifdef NICENAMES +"pop rd,@rs",16,8,0x00, +#endif +"pop",OPC_pop,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,113}, + +/* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */ +{ +#ifdef NICENAMES +"popl @rd,@rs",32,19,0x00, +#endif +"popl",OPC_popl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,114}, + +/* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */ +{ +#ifdef NICENAMES +"popl address_dst(rd),@rs",32,23,0x00, +#endif +"popl",OPC_popl,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,114}, + +/* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */ +{ +#ifdef NICENAMES +"popl address_dst,@rs",32,23,0x00, +#endif +"popl",OPC_popl,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,114}, + +/* 1001 0101 ssN0 dddd *** popl rrd,@rs */ +{ +#ifdef NICENAMES +"popl rrd,@rs",32,12,0x00, +#endif +"popl",OPC_popl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,114}, + +/* 0001 0011 ddN0 ssN0 *** push @rd,@rs */ +{ +#ifdef NICENAMES +"push @rd,@rs",16,13,0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,115}, + +/* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */ +{ +#ifdef NICENAMES +"push @rd,address_src",16,14,0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,115}, + +/* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */ +{ +#ifdef NICENAMES +"push @rd,address_src(rs)",16,14,0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,115}, + +/* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */ +{ +#ifdef NICENAMES +"push @rd,imm16",16,12,0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,115}, + +/* 1001 0011 ddN0 ssss *** push @rd,rs */ +{ +#ifdef NICENAMES +"push @rd,rs",16,9,0x00, +#endif +"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,115}, + +/* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */ +{ +#ifdef NICENAMES +"pushl @rd,@rs",32,20,0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,116}, + +/* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */ +{ +#ifdef NICENAMES +"pushl @rd,address_src",32,21,0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,116}, + +/* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */ +{ +#ifdef NICENAMES +"pushl @rd,address_src(rs)",32,21,0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,116}, + +/* 1001 0001 ddN0 ssss *** pushl @rd,rrs */ +{ +#ifdef NICENAMES +"pushl @rd,rrs",32,12,0x00, +#endif +"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,116}, + +/* 0010 0011 ddN0 imm4 *** res @rd,imm4 */ +{ +#ifdef NICENAMES +"res @rd,imm4",16,11,0x00, +#endif +"res",OPC_res,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,117}, + +/* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"res address_dst(rd),imm4",16,14,0x00, +#endif +"res",OPC_res,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,117}, + +/* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */ +{ +#ifdef NICENAMES +"res address_dst,imm4",16,13,0x00, +#endif +"res",OPC_res,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,117}, + +/* 1010 0011 dddd imm4 *** res rd,imm4 */ +{ +#ifdef NICENAMES +"res rd,imm4",16,4,0x00, +#endif +"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,117}, + +/* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */ +{ +#ifdef NICENAMES +"res rd,rs",16,10,0x00, +#endif +"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,117}, + +/* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */ +{ +#ifdef NICENAMES +"resb @rd,imm4",8,11,0x00, +#endif +"resb",OPC_resb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,118}, + +/* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"resb address_dst(rd),imm4",8,14,0x00, +#endif +"resb",OPC_resb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,118}, + +/* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */ +{ +#ifdef NICENAMES +"resb address_dst,imm4",8,13,0x00, +#endif +"resb",OPC_resb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,118}, + +/* 1010 0010 dddd imm4 *** resb rbd,imm4 */ +{ +#ifdef NICENAMES +"resb rbd,imm4",8,4,0x00, +#endif +"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,118}, + +/* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */ +{ +#ifdef NICENAMES +"resb rbd,rs",8,10,0x00, +#endif +"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,118}, + +/* 1000 1101 flags 0011 *** resflg flags */ +{ +#ifdef NICENAMES +"resflg flags",16,7,0x3c, +#endif +"resflg",OPC_resflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,119}, + +/* 1001 1110 0000 cccc *** ret cc */ +{ +#ifdef NICENAMES +"ret cc",16,10,0x00, +#endif +"ret",OPC_ret,0,{CLASS_CC,}, + {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,120}, + +/* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */ +{ +#ifdef NICENAMES +"rl rd,imm1or2",16,6,0x3c, +#endif +"rl",OPC_rl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,121}, + +/* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rlb rbd,imm1or2",8,6,0x3c, +#endif +"rlb",OPC_rlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,122}, + +/* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */ +{ +#ifdef NICENAMES +"rlc rd,imm1or2",16,6,0x3c, +#endif +"rlc",OPC_rlc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,123}, + +/* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rlcb rbd,imm1or2",8,9,0x10, +#endif +"rlcb",OPC_rlcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,124}, + +/* 1011 1110 aaaa bbbb *** rldb rbb,rba */ +{ +#ifdef NICENAMES +"rldb rbb,rba",8,9,0x10, +#endif +"rldb",OPC_rldb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,125}, + +/* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */ +{ +#ifdef NICENAMES +"rr rd,imm1or2",16,6,0x3c, +#endif +"rr",OPC_rr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,126}, + +/* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rrb rbd,imm1or2",8,6,0x3c, +#endif +"rrb",OPC_rrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,127}, + +/* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */ +{ +#ifdef NICENAMES +"rrc rd,imm1or2",16,6,0x3c, +#endif +"rrc",OPC_rrc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,128}, + +/* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */ +{ +#ifdef NICENAMES +"rrcb rbd,imm1or2",8,9,0x10, +#endif +"rrcb",OPC_rrcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,129}, + +/* 1011 1100 aaaa bbbb *** rrdb rbb,rba */ +{ +#ifdef NICENAMES +"rrdb rbb,rba",8,9,0x10, +#endif +"rrdb",OPC_rrdb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,130}, + +/* 0011 0110 imm8 *** rsvd36 */ +{ +#ifdef NICENAMES +"rsvd36",8,10,0x00, +#endif +"rsvd36",OPC_rsvd36,0,{0}, + {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,131}, + +/* 0011 1000 imm8 *** rsvd38 */ +{ +#ifdef NICENAMES +"rsvd38",8,10,0x00, +#endif +"rsvd38",OPC_rsvd38,0,{0}, + {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,132}, + +/* 0111 1000 imm8 *** rsvd78 */ +{ +#ifdef NICENAMES +"rsvd78",8,10,0x00, +#endif +"rsvd78",OPC_rsvd78,0,{0}, + {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,133}, + +/* 0111 1110 imm8 *** rsvd7e */ +{ +#ifdef NICENAMES +"rsvd7e",8,10,0x00, +#endif +"rsvd7e",OPC_rsvd7e,0,{0}, + {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,134}, + +/* 1001 1101 imm8 *** rsvd9d */ +{ +#ifdef NICENAMES +"rsvd9d",8,10,0x00, +#endif +"rsvd9d",OPC_rsvd9d,0,{0}, + {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,135}, + +/* 1001 1111 imm8 *** rsvd9f */ +{ +#ifdef NICENAMES +"rsvd9f",8,10,0x00, +#endif +"rsvd9f",OPC_rsvd9f,0,{0}, + {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,136}, + +/* 1011 1001 imm8 *** rsvdb9 */ +{ +#ifdef NICENAMES +"rsvdb9",8,10,0x00, +#endif +"rsvdb9",OPC_rsvdb9,0,{0}, + {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,137}, + +/* 1011 1111 imm8 *** rsvdbf */ +{ +#ifdef NICENAMES +"rsvdbf",8,10,0x00, +#endif +"rsvdbf",OPC_rsvdbf,0,{0}, + {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,138}, + +/* 1011 0111 ssss dddd *** sbc rd,rs */ +{ +#ifdef NICENAMES +"sbc rd,rs",16,5,0x3c, +#endif +"sbc",OPC_sbc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,139}, + +/* 1011 0110 ssss dddd *** sbcb rbd,rbs */ +{ +#ifdef NICENAMES +"sbcb rbd,rbs",8,5,0x3f, +#endif +"sbcb",OPC_sbcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,140}, + +/* 0111 1111 imm8 *** sc imm8 */ +{ +#ifdef NICENAMES +"sc imm8",8,33,0x3f, +#endif +"sc",OPC_sc,0,{CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,141}, + +/* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */ +{ +#ifdef NICENAMES +"sda rd,rs",16,15,0x3c, +#endif +"sda",OPC_sda,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,142}, + +/* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */ +{ +#ifdef NICENAMES +"sdab rbd,rs",8,15,0x3c, +#endif +"sdab",OPC_sdab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,143}, + +/* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */ +{ +#ifdef NICENAMES +"sdal rrd,rs",32,15,0x3c, +#endif +"sdal",OPC_sdal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,144}, + +/* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */ +{ +#ifdef NICENAMES +"sdl rd,rs",16,15,0x38, +#endif +"sdl",OPC_sdl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,145}, + +/* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */ +{ +#ifdef NICENAMES +"sdlb rbd,rs",8,15,0x38, +#endif +"sdlb",OPC_sdlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,146}, + +/* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */ +{ +#ifdef NICENAMES +"sdll rrd,rs",32,15,0x38, +#endif +"sdll",OPC_sdll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,147}, + +/* 0010 0101 ddN0 imm4 *** set @rd,imm4 */ +{ +#ifdef NICENAMES +"set @rd,imm4",16,11,0x00, +#endif +"set",OPC_set,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,148}, + +/* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"set address_dst(rd),imm4",16,14,0x00, +#endif +"set",OPC_set,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,148}, + +/* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */ +{ +#ifdef NICENAMES +"set address_dst,imm4",16,13,0x00, +#endif +"set",OPC_set,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,148}, + +/* 1010 0101 dddd imm4 *** set rd,imm4 */ +{ +#ifdef NICENAMES +"set rd,imm4",16,4,0x00, +#endif +"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,148}, + +/* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */ +{ +#ifdef NICENAMES +"set rd,rs",16,10,0x00, +#endif +"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,148}, + +/* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */ +{ +#ifdef NICENAMES +"setb @rd,imm4",8,11,0x00, +#endif +"setb",OPC_setb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,149}, + +/* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */ +{ +#ifdef NICENAMES +"setb address_dst(rd),imm4",8,14,0x00, +#endif +"setb",OPC_setb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,149}, + +/* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */ +{ +#ifdef NICENAMES +"setb address_dst,imm4",8,13,0x00, +#endif +"setb",OPC_setb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,149}, + +/* 1010 0100 dddd imm4 *** setb rbd,imm4 */ +{ +#ifdef NICENAMES +"setb rbd,imm4",8,4,0x00, +#endif +"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,149}, + +/* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */ +{ +#ifdef NICENAMES +"setb rbd,rs",8,10,0x00, +#endif +"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,149}, + +/* 1000 1101 flags 0001 *** setflg flags */ +{ +#ifdef NICENAMES +"setflg flags",16,7,0x3c, +#endif +"setflg",OPC_setflg,0,{CLASS_FLAGS,}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,150}, + +/* 0011 1011 dddd 0101 imm16 *** sin rd,imm16 */ +{ +#ifdef NICENAMES +"sin rd,imm16",16,12,0x00, +#endif +"sin",OPC_sin,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,151}, + +/* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */ +{ +#ifdef NICENAMES +"sinb rbd,imm16",8,10,0x00, +#endif +"sinb",OPC_sinb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,152}, + +/* 0011 1011 ssss 1001 0000 aaaa ddN0 1000 *** sind @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sind @rd,@ri,ra",16,21,0x04, +#endif +"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,153}, + +/* 0011 1010 ssss 1001 0000 aaaa ddN0 1000 *** sindb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindb @rd,@ri,ra",8,21,0x04, +#endif +"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,154}, + +/* 0011 1011 ssss 1001 0000 aaaa ddN0 0000 *** sindr @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindr @rd,@ri,ra",16,11,0x04, +#endif +"sindr",OPC_sindr,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,155}, + +/* 0011 1010 ssss 1001 0000 aaaa ddN0 0000 *** sindrb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sindrb @rd,@ri,ra",8,11,0x04, +#endif +"sindrb",OPC_sindrb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,156}, + +/* 0011 1011 ssss 0001 0000 aaaa ddN0 1000 *** sini @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sini @rd,@ri,ra",16,21,0x04, +#endif +"sini",OPC_sini,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,157}, + +/* 0011 1010 ssss 0001 0000 aaaa ddN0 1000 *** sinib @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sinib @rd,@ri,ra",8,21,0x04, +#endif +"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,158}, + +/* 0011 1011 ssss 0001 0000 aaaa ddN0 0000 *** sinir @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sinir @rd,@ri,ra",16,11,0x04, +#endif +"sinir",OPC_sinir,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,159}, + +/* 0011 1010 ssss 0001 0000 aaaa ddN0 0000 *** sinirb @rd,@ri,ra */ +{ +#ifdef NICENAMES +"sinirb @rd,@ri,ra",8,11,0x04, +#endif +"sinirb",OPC_sinirb,0,{CLASS_IR+(ARG_RD),CLASS_IRO+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,160}, + +/* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */ +{ +#ifdef NICENAMES +"sla rd,imm8",16,13,0x3c, +#endif +"sla",OPC_sla,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,161}, + +/* 1011 0010 dddd 1001 iiii iiii 0000 imm4 *** slab rbd,imm4 */ +{ +#ifdef NICENAMES +"slab rbd,imm4",8,13,0x3c, +#endif +"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,162}, + +/* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */ +{ +#ifdef NICENAMES +"slal rrd,imm8",32,13,0x3c, +#endif +"slal",OPC_slal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,163}, + +/* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */ +{ +#ifdef NICENAMES +"sll rd,imm8",16,13,0x38, +#endif +"sll",OPC_sll,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,164}, + +/* 1011 0010 dddd 0001 iiii iiii 0000 imm4 *** sllb rbd,imm4 */ +{ +#ifdef NICENAMES +"sllb rbd,imm4",8,13,0x38, +#endif +"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),0,},2,4,165}, + +/* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */ +{ +#ifdef NICENAMES +"slll rrd,imm8",32,13,0x38, +#endif +"slll",OPC_slll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,166}, + +/* 0011 1011 ssN0 1011 0000 aaaa dddd 0000 *** sotdr @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotdr @ro,@rs,ra",16,11,0x04, +#endif +"sotdr",OPC_sotdr,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,167}, + +/* 0011 1010 ssN0 1011 0000 aaaa dddd 0000 *** sotdrb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotdrb @ro,@rs,ra",8,11,0x04, +#endif +"sotdrb",OPC_sotdrb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,168}, + +/* 0011 1011 ssN0 0011 0000 aaaa dddd 0000 *** sotir @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotir @ro,@rs,ra",16,11,0x04, +#endif +"sotir",OPC_sotir,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,169}, + +/* 0011 1010 ssN0 0011 0000 aaaa dddd 0000 *** sotirb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"sotirb @ro,@rs,ra",8,11,0x04, +#endif +"sotirb",OPC_sotirb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,170}, + +/* 0011 1011 ssss 0110 imm16 *** sout imm16,rs */ +{ +#ifdef NICENAMES +"sout imm16,rs",16,12,0x00, +#endif +"sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,171}, + +/* 0011 1010 ssss 0110 imm16 *** soutb imm16,rbs */ +{ +#ifdef NICENAMES +"soutb imm16,rbs",8,12,0x00, +#endif +"soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,172}, + +/* 0011 1011 ssN0 1011 0000 aaaa dddd 1000 *** soutd @ro,@rs,ra */ +{ +#ifdef NICENAMES +"soutd @ro,@rs,ra",16,21,0x04, +#endif +"soutd",OPC_soutd,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,173}, + +/* 0011 1010 ssN0 1011 0000 aaaa dddd 1000 *** soutdb @ro,@rs,ra */ +{ +#ifdef NICENAMES +"soutdb @ro,@rs,ra",8,21,0x04, +#endif +"soutdb",OPC_soutdb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,174}, + +/* 0011 1011 ssN0 0011 0000 aaaa dddd 1000 *** souti @ro,@rs,ra */ +{ +#ifdef NICENAMES +"souti @ro,@rs,ra",16,21,0x04, +#endif +"souti",OPC_souti,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,175}, + +/* 0011 1010 ssN0 0011 0000 aaaa dddd 1000 *** soutib @ro,@rs,ra */ +{ +#ifdef NICENAMES +"soutib @ro,@rs,ra",8,21,0x04, +#endif +"soutib",OPC_soutib,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, + {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+8,0,},3,4,176}, + +/* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */ +{ +#ifdef NICENAMES +"sra rd,imm8",16,13,0x3c, +#endif +"sra",OPC_sra,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,177}, + +/* 1011 0010 dddd 1001 iiii iiii 1111 nim4 *** srab rbd,imm4 */ +{ +#ifdef NICENAMES +"srab rbd,imm4",8,13,0x3c, +#endif +"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,178}, + +/* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */ +{ +#ifdef NICENAMES +"sral rrd,imm8",32,13,0x3c, +#endif +"sral",OPC_sral,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,179}, + +/* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */ +{ +#ifdef NICENAMES +"srl rd,imm8",16,13,0x3c, +#endif +"srl",OPC_srl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,180}, + +/* 1011 0010 dddd 0001 iiii iiii 1111 nim4 *** srlb rbd,imm4 */ +{ +#ifdef NICENAMES +"srlb rbd,imm4",8,13,0x3c, +#endif +"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, + {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_IGNORE,CLASS_IGNORE,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM4),0,},2,4,181}, + +/* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */ +{ +#ifdef NICENAMES +"srll rrd,imm8",32,13,0x3c, +#endif +"srll",OPC_srll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,182}, + +/* 0000 0011 ssN0 dddd *** sub rd,@rs */ +{ +#ifdef NICENAMES +"sub rd,@rs",16,7,0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,183}, + +/* 0100 0011 0000 dddd address_src *** sub rd,address_src */ +{ +#ifdef NICENAMES +"sub rd,address_src",16,9,0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, + +/* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */ +{ +#ifdef NICENAMES +"sub rd,address_src(rs)",16,10,0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, + +/* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */ +{ +#ifdef NICENAMES +"sub rd,imm16",16,7,0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,183}, + +/* 1000 0011 ssss dddd *** sub rd,rs */ +{ +#ifdef NICENAMES +"sub rd,rs",16,4,0x3c, +#endif +"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,183}, + +/* 0000 0010 ssN0 dddd *** subb rbd,@rs */ +{ +#ifdef NICENAMES +"subb rbd,@rs",8,7,0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,184}, + +/* 0100 0010 0000 dddd address_src *** subb rbd,address_src */ +{ +#ifdef NICENAMES +"subb rbd,address_src",8,9,0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, + +/* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"subb rbd,address_src(rs)",8,10,0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, + +/* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */ +{ +#ifdef NICENAMES +"subb rbd,imm8",8,7,0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,184}, + +/* 1000 0010 ssss dddd *** subb rbd,rbs */ +{ +#ifdef NICENAMES +"subb rbd,rbs",8,4,0x3f, +#endif +"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,184}, + +/* 0001 0010 ssN0 dddd *** subl rrd,@rs */ +{ +#ifdef NICENAMES +"subl rrd,@rs",32,14,0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,185}, + +/* 0101 0010 0000 dddd address_src *** subl rrd,address_src */ +{ +#ifdef NICENAMES +"subl rrd,address_src",32,15,0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,185}, + +/* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */ +{ +#ifdef NICENAMES +"subl rrd,address_src(rs)",32,16,0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,185}, + +/* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */ +{ +#ifdef NICENAMES +"subl rrd,imm32",32,14,0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, + {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,185}, + +/* 1001 0010 ssss dddd *** subl rrd,rrs */ +{ +#ifdef NICENAMES +"subl rrd,rrs",32,8,0x3c, +#endif +"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, + {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,185}, + +/* 1010 1111 dddd cccc *** tcc cc,rd */ +{ +#ifdef NICENAMES +"tcc cc,rd",16,5,0x00, +#endif +"tcc",OPC_tcc,0,{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,186}, + +/* 1010 1110 dddd cccc *** tccb cc,rbd */ +{ +#ifdef NICENAMES +"tccb cc,rbd",8,5,0x00, +#endif +"tccb",OPC_tccb,0,{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,187}, + +/* 0000 1101 ddN0 0100 *** test @rd */ +{ +#ifdef NICENAMES +"test @rd",16,8,0x18, +#endif +"test",OPC_test,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,188}, + +/* 0100 1101 0000 0100 address_dst *** test address_dst */ +{ +#ifdef NICENAMES +"test address_dst",16,11,0x00, +#endif +"test",OPC_test,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,188}, + +/* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */ +{ +#ifdef NICENAMES +"test address_dst(rd)",16,12,0x00, +#endif +"test",OPC_test,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,188}, + +/* 1000 1101 dddd 0100 *** test rd */ +{ +#ifdef NICENAMES +"test rd",16,7,0x00, +#endif +"test",OPC_test,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,188}, + +/* 0000 1100 ddN0 0100 *** testb @rd */ +{ +#ifdef NICENAMES +"testb @rd",8,8,0x1c, +#endif +"testb",OPC_testb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,189}, + +/* 0100 1100 0000 0100 address_dst *** testb address_dst */ +{ +#ifdef NICENAMES +"testb address_dst",8,11,0x1c, +#endif +"testb",OPC_testb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,189}, + +/* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */ +{ +#ifdef NICENAMES +"testb address_dst(rd)",8,12,0x1c, +#endif +"testb",OPC_testb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,189}, + +/* 1000 1100 dddd 0100 *** testb rbd */ +{ +#ifdef NICENAMES +"testb rbd",8,7,0x1c, +#endif +"testb",OPC_testb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,189}, + +/* 0001 1100 ddN0 1000 *** testl @rd */ +{ +#ifdef NICENAMES +"testl @rd",32,13,0x18, +#endif +"testl",OPC_testl,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,190}, + +/* 0101 1100 0000 1000 address_dst *** testl address_dst */ +{ +#ifdef NICENAMES +"testl address_dst",32,16,0x18, +#endif +"testl",OPC_testl,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,190}, + +/* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */ +{ +#ifdef NICENAMES +"testl address_dst(rd)",32,17,0x18, +#endif +"testl",OPC_testl,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,190}, + +/* 1001 1100 dddd 1000 *** testl rrd */ +{ +#ifdef NICENAMES +"testl rrd",32,13,0x18, +#endif +"testl",OPC_testl,0,{CLASS_REG_LONG+(ARG_RD),}, + {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,190}, + +/* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"trdb @rd,@rs,rba",8,25,0x1c, +#endif +"trdb",OPC_trdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,191}, + +/* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */ +{ +#ifdef NICENAMES +"trdrb @rd,@rs,rba",8,25,0x1c, +#endif +"trdrb",OPC_trdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,192}, + +/* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */ +{ +#ifdef NICENAMES +"trib @rd,@rs,rbr",8,25,0x1c, +#endif +"trib",OPC_trib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,193}, + +/* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */ +{ +#ifdef NICENAMES +"trirb @rd,@rs,rbr",8,25,0x1c, +#endif +"trirb",OPC_trirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,194}, + +/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtdb @ra,@rb,rbr",8,25,0x1c, +#endif +"trtdb",OPC_trtdb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,195}, + +/* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtdrb @ra,@rb,rbr",8,25,0x1c, +#endif +"trtdrb",OPC_trtdrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,196}, + +/* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtib @ra,@rb,rbr",8,25,0x1c, +#endif +"trtib",OPC_trtib,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,197}, + +/* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtirb @ra,@rb,rbr",8,25,0x1c, +#endif +"trtirb",OPC_trtirb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,198}, + +/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtrb @ra,@rb,rbr */ +{ +#ifdef NICENAMES +"trtrb @ra,@rb,rbr",8,25,0x1c, +#endif +"trtrb",OPC_trtrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, + {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,199}, + +/* 0000 1101 ddN0 0110 *** tset @rd */ +{ +#ifdef NICENAMES +"tset @rd",16,11,0x08, +#endif +"tset",OPC_tset,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,200}, + +/* 0100 1101 0000 0110 address_dst *** tset address_dst */ +{ +#ifdef NICENAMES +"tset address_dst",16,14,0x08, +#endif +"tset",OPC_tset,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,200}, + +/* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */ +{ +#ifdef NICENAMES +"tset address_dst(rd)",16,15,0x08, +#endif +"tset",OPC_tset,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,200}, + +/* 1000 1101 dddd 0110 *** tset rd */ +{ +#ifdef NICENAMES +"tset rd",16,7,0x08, +#endif +"tset",OPC_tset,0,{CLASS_REG_WORD+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,200}, + +/* 0000 1100 ddN0 0110 *** tsetb @rd */ +{ +#ifdef NICENAMES +"tsetb @rd",8,11,0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_IR+(ARG_RD),}, + {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,201}, + +/* 0100 1100 0000 0110 address_dst *** tsetb address_dst */ +{ +#ifdef NICENAMES +"tsetb address_dst",8,14,0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_DA+(ARG_DST),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,201}, + +/* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */ +{ +#ifdef NICENAMES +"tsetb address_dst(rd)",8,15,0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_X+(ARG_RD),}, + {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,201}, + +/* 1000 1100 dddd 0110 *** tsetb rbd */ +{ +#ifdef NICENAMES +"tsetb rbd",8,7,0x08, +#endif +"tsetb",OPC_tsetb,0,{CLASS_REG_BYTE+(ARG_RD),}, + {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,201}, + +/* 0000 1001 ssN0 dddd *** xor rd,@rs */ +{ +#ifdef NICENAMES +"xor rd,@rs",16,7,0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,202}, + +/* 0100 1001 0000 dddd address_src *** xor rd,address_src */ +{ +#ifdef NICENAMES +"xor rd,address_src",16,9,0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,202}, + +/* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */ +{ +#ifdef NICENAMES +"xor rd,address_src(rs)",16,10,0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,202}, + +/* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */ +{ +#ifdef NICENAMES +"xor rd,imm16",16,7,0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, + {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,202}, + +/* 1000 1001 ssss dddd *** xor rd,rs */ +{ +#ifdef NICENAMES +"xor rd,rs",16,4,0x18, +#endif +"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,202}, + +/* 0000 1000 ssN0 dddd *** xorb rbd,@rs */ +{ +#ifdef NICENAMES +"xorb rbd,@rs",8,7,0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,203}, + +/* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */ +{ +#ifdef NICENAMES +"xorb rbd,address_src",8,9,0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,203}, + +/* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */ +{ +#ifdef NICENAMES +"xorb rbd,address_src(rs)",8,10,0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, + {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,203}, + +/* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */ +{ +#ifdef NICENAMES +"xorb rbd,imm8",8,7,0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, + {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,203}, + +/* 1000 1000 ssss dddd *** xorb rbd,rbs */ +{ +#ifdef NICENAMES +"xorb rbd,rbs",8,4,0x1c, +#endif +"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, + {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,203}, + +/* end marker */ +{ +#ifdef NICENAMES +NULL,0,0, +0, +#endif +NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0} +}; +#endif diff --git a/external/gpl3/gdb/dist/opcodes/z8kgen.c b/external/gpl3/gdb/dist/opcodes/z8kgen.c new file mode 100644 index 000000000000..ecb56b7eea49 --- /dev/null +++ b/external/gpl3/gdb/dist/opcodes/z8kgen.c @@ -0,0 +1,1379 @@ +/* Copyright 2001, 2002, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This program generates z8k-opc.h. */ + +#include +#include "sysdep.h" +#include "libiberty.h" + +#define BYTE_INFO_LEN 10 + +struct op +{ + char *flags; + int cycles; + char type; + char *bits; + char *name; + /* Unique number for stable sorting. */ + int id; +}; + +#define iswhite(x) ((x) == ' ' || (x) == '\t') +static struct op opt[] = +{ + {"------", 2, 8, "0011 0110 0000 0000", "bpt", 0}, /* Breakpoint used by the simulator. */ + {"------", 10, 8, "0000 1111 0000 1100", "brk", 0}, /* Breakpoint used by real hardware. + (ext0f #0x0c). */ + + {"------", 10, 8, "0000 1110 imm8", "ext0e imm8", 0}, + {"------", 10, 8, "0000 1111 imm8", "ext0f imm8", 0}, + {"------", 10, 8, "1000 1110 imm8", "ext8e imm8", 0}, + {"------", 10, 8, "1000 1111 imm8", "ext8f imm8", 0}, + + {"------", 10, 8, "0011 0110 imm8", "rsvd36", 0}, + {"------", 10, 8, "0011 1000 imm8", "rsvd38", 0}, + {"------", 10, 8, "0111 1000 imm8", "rsvd78", 0}, + {"------", 10, 8, "0111 1110 imm8", "rsvd7e", 0}, + + {"------", 10, 8, "1001 1101 imm8", "rsvd9d", 0}, + {"------", 10, 8, "1001 1111 imm8", "rsvd9f", 0}, + + {"------", 10, 8, "1011 1001 imm8", "rsvdb9", 0}, + {"------", 10, 8, "1011 1111 imm8", "rsvdbf", 0}, + + {"---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 1000", "ldd @rd,@rs,rr", 0}, + {"---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 0000", "lddr @rd,@rs,rr", 0}, + {"---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 0000", "lddrb @rd,@rs,rr", 0}, + {"---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 0000", "ldir @rd,@rs,rr", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 0000 0000 rrrr dddd cccc", "cpi rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 0100 0000 rrrr dddd cccc", "cpir rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 1100 0000 rrrr dddd cccc", "cpdr rd,@rs,rr,cc", 0}, + {"---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 1000", "ldi @rd,@rs,rr", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 1000 0000 rrrr dddd cccc", "cpd rd,@rs,rr,cc", 0}, + {"---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 0000", "ldirb @rd,@rs,rr", 0}, + {"---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 1000", "lddb @rd,@rs,rr", 0}, + {"---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 1000", "ldib @rd,@rs,rr", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 1000 0000 rrrr dddd cccc", "cpdb rbd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 1100 0000 rrrr dddd cccc", "cpdrb rbd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 0000 0000 rrrr dddd cccc", "cpib rbd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 0100 0000 rrrr dddd cccc", "cpirb rbd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 1010 0000 rrrr ddN0 cccc", "cpsd @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 1010 0000 rrrr ddN0 cccc", "cpsdb @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdr @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdrb @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 0010 0000 rrrr ddN0 cccc", "cpsi @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 0010 0000 rrrr ddN0 cccc", "cpsib @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 16, "1011 1011 ssN0 0110 0000 rrrr ddN0 cccc", "cpsir @rd,@rs,rr,cc", 0}, + {"CZSV--", 11, 8, "1011 1010 ssN0 0110 0000 rrrr ddN0 cccc", "cpsirb @rd,@rs,rr,cc", 0}, + + {"CZSV--", 5, 16, "1011 0101 ssss dddd", "adc rd,rs", 0}, + {"CZSVDH", 5, 8, "1011 0100 ssss dddd", "adcb rbd,rbs", 0}, + {"CZSV--", 7, 16, "0000 0001 ssN0 dddd", "add rd,@rs", 0}, + {"CZSV--", 9, 16, "0100 0001 0000 dddd address_src", "add rd,address_src", 0}, + {"CZSV--", 10, 16, "0100 0001 ssN0 dddd address_src", "add rd,address_src(rs)", 0}, + {"CZSV--", 7, 16, "0000 0001 0000 dddd imm16", "add rd,imm16", 0}, + {"CZSV--", 4, 16, "1000 0001 ssss dddd", "add rd,rs", 0}, + {"CZSVDH", 7, 8, "0000 0000 ssN0 dddd", "addb rbd,@rs", 0}, + {"CZSVDH", 9, 8, "0100 0000 0000 dddd address_src", "addb rbd,address_src", 0}, + {"CZSVDH", 10, 8, "0100 0000 ssN0 dddd address_src", "addb rbd,address_src(rs)", 0}, + {"CZSVDH", 7, 8, "0000 0000 0000 dddd imm8 imm8", "addb rbd,imm8", 0}, + {"CZSVDH", 4, 8, "1000 0000 ssss dddd", "addb rbd,rbs", 0}, + {"CZSV--", 14, 32, "0001 0110 ssN0 dddd", "addl rrd,@rs", 0}, + {"CZSV--", 15, 32, "0101 0110 0000 dddd address_src", "addl rrd,address_src", 0}, + {"CZSV--", 16, 32, "0101 0110 ssN0 dddd address_src", "addl rrd,address_src(rs)", 0}, + {"CZSV--", 14, 32, "0001 0110 0000 dddd imm32", "addl rrd,imm32", 0}, + {"CZSV--", 8, 32, "1001 0110 ssss dddd", "addl rrd,rrs", 0}, + + {"-ZS---", 7, 16, "0000 0111 ssN0 dddd", "and rd,@rs", 0}, + {"-ZS---", 9, 16, "0100 0111 0000 dddd address_src", "and rd,address_src", 0}, + {"-ZS---", 10, 16, "0100 0111 ssN0 dddd address_src", "and rd,address_src(rs)", 0}, + {"-ZS---", 7, 16, "0000 0111 0000 dddd imm16", "and rd,imm16", 0}, + {"-ZS---", 4, 16, "1000 0111 ssss dddd", "and rd,rs", 0}, + {"-ZSP--", 7, 8, "0000 0110 ssN0 dddd", "andb rbd,@rs", 0}, + {"-ZSP--", 9, 8, "0100 0110 0000 dddd address_src", "andb rbd,address_src", 0}, + {"-ZSP--", 10, 8, "0100 0110 ssN0 dddd address_src", "andb rbd,address_src(rs)", 0}, + {"-ZSP--", 7, 8, "0000 0110 0000 dddd imm8 imm8", "andb rbd,imm8", 0}, + {"-ZSP--", 4, 8, "1000 0110 ssss dddd", "andb rbd,rbs", 0}, + + {"-Z----", 8, 16, "0010 0111 ddN0 imm4", "bit @rd,imm4", 0}, + {"-Z----", 11, 16, "0110 0111 ddN0 imm4 address_dst", "bit address_dst(rd),imm4", 0}, + {"-Z----", 10, 16, "0110 0111 0000 imm4 address_dst", "bit address_dst,imm4", 0}, + {"-Z----", 4, 16, "1010 0111 dddd imm4", "bit rd,imm4", 0}, + {"-Z----", 10, 16, "0010 0111 0000 ssss 0000 dddd 0000 0000", "bit rd,rs", 0}, + + {"-Z----", 8, 8, "0010 0110 ddN0 imm4", "bitb @rd,imm4", 0}, + {"-Z----", 11, 8, "0110 0110 ddN0 imm4 address_dst", "bitb address_dst(rd),imm4", 0}, + {"-Z----", 10, 8, "0110 0110 0000 imm4 address_dst", "bitb address_dst,imm4", 0}, + {"-Z----", 4, 8, "1010 0110 dddd imm4", "bitb rbd,imm4", 0}, + {"-Z----", 10, 8, "0010 0110 0000 ssss 0000 dddd 0000 0000", "bitb rbd,rs", 0}, + + {"------", 10, 32, "0001 1111 ddN0 0000", "call @rd", 0}, + {"------", 12, 32, "0101 1111 0000 0000 address_dst", "call address_dst", 0}, + {"------", 13, 32, "0101 1111 ddN0 0000 address_dst", "call address_dst(rd)", 0}, + {"------", 10, 16, "1101 disp12", "calr disp12", 0}, + + {"------", 8, 16, "0000 1101 ddN0 1000", "clr @rd", 0}, + {"------", 11, 16, "0100 1101 0000 1000 address_dst", "clr address_dst", 0}, + {"------", 12, 16, "0100 1101 ddN0 1000 address_dst", "clr address_dst(rd)", 0}, + {"------", 7, 16, "1000 1101 dddd 1000", "clr rd", 0}, + {"------", 8, 8, "0000 1100 ddN0 1000", "clrb @rd", 0}, + {"------", 11, 8, "0100 1100 0000 1000 address_dst", "clrb address_dst", 0}, + {"------", 12, 8, "0100 1100 ddN0 1000 address_dst", "clrb address_dst(rd)", 0}, + {"------", 7, 8, "1000 1100 dddd 1000", "clrb rbd", 0}, + {"-ZS---", 12, 16, "0000 1101 ddN0 0000", "com @rd", 0}, + {"-ZS---", 15, 16, "0100 1101 0000 0000 address_dst", "com address_dst", 0}, + {"-ZS---", 16, 16, "0100 1101 ddN0 0000 address_dst", "com address_dst(rd)", 0}, + {"-ZS---", 7, 16, "1000 1101 dddd 0000", "com rd", 0}, + {"-ZSP--", 12, 8, "0000 1100 ddN0 0000", "comb @rd", 0}, + {"-ZSP--", 15, 8, "0100 1100 0000 0000 address_dst", "comb address_dst", 0}, + {"-ZSP--", 16, 8, "0100 1100 ddN0 0000 address_dst", "comb address_dst(rd)", 0}, + {"-ZSP--", 7, 8, "1000 1100 dddd 0000", "comb rbd", 0}, + {"CZSP--", 7, 16, "1000 1101 flags 0101", "comflg flags", 0}, + + {"CZSV--", 11, 16, "0000 1101 ddN0 0001 imm16", "cp @rd,imm16", 0}, + {"CZSV--", 15, 16, "0100 1101 ddN0 0001 address_dst imm16", "cp address_dst(rd),imm16", 0}, + {"CZSV--", 14, 16, "0100 1101 0000 0001 address_dst imm16", "cp address_dst,imm16", 0}, + + {"CZSV--", 7, 16, "0000 1011 ssN0 dddd", "cp rd,@rs", 0}, + {"CZSV--", 9, 16, "0100 1011 0000 dddd address_src", "cp rd,address_src", 0}, + {"CZSV--", 10, 16, "0100 1011 ssN0 dddd address_src", "cp rd,address_src(rs)", 0}, + {"CZSV--", 7, 16, "0000 1011 0000 dddd imm16", "cp rd,imm16", 0}, + {"CZSV--", 4, 16, "1000 1011 ssss dddd", "cp rd,rs", 0}, + + {"CZSV--", 11, 8, "0000 1100 ddN0 0001 imm8 imm8", "cpb @rd,imm8", 0}, + {"CZSV--", 15, 8, "0100 1100 ddN0 0001 address_dst imm8 imm8", "cpb address_dst(rd),imm8", 0}, + {"CZSV--", 14, 8, "0100 1100 0000 0001 address_dst imm8 imm8", "cpb address_dst,imm8", 0}, + {"CZSV--", 7, 8, "0000 1010 ssN0 dddd", "cpb rbd,@rs", 0}, + {"CZSV--", 9, 8, "0100 1010 0000 dddd address_src", "cpb rbd,address_src", 0}, + {"CZSV--", 10, 8, "0100 1010 ssN0 dddd address_src", "cpb rbd,address_src(rs)", 0}, + {"CZSV--", 7, 8, "0000 1010 0000 dddd imm8 imm8", "cpb rbd,imm8", 0}, + {"CZSV--", 4, 8, "1000 1010 ssss dddd", "cpb rbd,rbs", 0}, + + {"CZSV--", 14, 32, "0001 0000 ssN0 dddd", "cpl rrd,@rs", 0}, + {"CZSV--", 15, 32, "0101 0000 0000 dddd address_src", "cpl rrd,address_src", 0}, + {"CZSV--", 16, 32, "0101 0000 ssN0 dddd address_src", "cpl rrd,address_src(rs)", 0}, + {"CZSV--", 14, 32, "0001 0000 0000 dddd imm32", "cpl rrd,imm32", 0}, + {"CZSV--", 8, 32, "1001 0000 ssss dddd", "cpl rrd,rrs", 0}, + + {"CZS---", 5, 8, "1011 0000 dddd 0000", "dab rbd", 0}, + {"------", 11, 16, "1111 dddd 0disp7", "dbjnz rbd,disp7", 0}, + {"-ZSV--", 11, 16, "0010 1011 ddN0 imm4m1", "dec @rd,imm4m1", 0}, + {"-ZSV--", 14, 16, "0110 1011 ddN0 imm4m1 address_dst", "dec address_dst(rd),imm4m1", 0}, + {"-ZSV--", 13, 16, "0110 1011 0000 imm4m1 address_dst", "dec address_dst,imm4m1", 0}, + {"-ZSV--", 4, 16, "1010 1011 dddd imm4m1", "dec rd,imm4m1", 0}, + {"-ZSV--", 11, 8, "0010 1010 ddN0 imm4m1", "decb @rd,imm4m1", 0}, + {"-ZSV--", 14, 8, "0110 1010 ddN0 imm4m1 address_dst", "decb address_dst(rd),imm4m1", 0}, + {"-ZSV--", 13, 8, "0110 1010 0000 imm4m1 address_dst", "decb address_dst,imm4m1", 0}, + {"-ZSV--", 4, 8, "1010 1010 dddd imm4m1", "decb rbd,imm4m1", 0}, + + {"------", 7, 16, "0111 1100 0000 00ii", "di i2", 0}, + {"CZSV--", 107, 16, "0001 1011 ssN0 dddd", "div rrd,@rs", 0}, + {"CZSV--", 107, 16, "0101 1011 0000 dddd address_src", "div rrd,address_src", 0}, + {"CZSV--", 107, 16, "0101 1011 ssN0 dddd address_src", "div rrd,address_src(rs)", 0}, + {"CZSV--", 107, 16, "0001 1011 0000 dddd imm16", "div rrd,imm16", 0}, + {"CZSV--", 107, 16, "1001 1011 ssss dddd", "div rrd,rs", 0}, + {"CZSV--", 744, 32, "0001 1010 ssN0 dddd", "divl rqd,@rs", 0}, + {"CZSV--", 745, 32, "0101 1010 0000 dddd address_src", "divl rqd,address_src", 0}, + {"CZSV--", 746, 32, "0101 1010 ssN0 dddd address_src", "divl rqd,address_src(rs)", 0}, + {"CZSV--", 744, 32, "0001 1010 0000 dddd imm32", "divl rqd,imm32", 0}, + {"CZSV--", 744, 32, "1001 1010 ssss dddd", "divl rqd,rrs", 0}, + + {"------", 11, 16, "1111 dddd 1disp7", "djnz rd,disp7", 0}, + {"------", 7, 16, "0111 1100 0000 01ii", "ei i2", 0}, + {"------", 6, 16, "1010 1101 ssss dddd", "ex rd,rs", 0}, + {"------", 12, 16, "0010 1101 ssN0 dddd", "ex rd,@rs", 0}, + {"------", 15, 16, "0110 1101 0000 dddd address_src", "ex rd,address_src", 0}, + {"------", 16, 16, "0110 1101 ssN0 dddd address_src", "ex rd,address_src(rs)", 0}, + + {"------", 12, 8, "0010 1100 ssN0 dddd", "exb rbd,@rs", 0}, + {"------", 15, 8, "0110 1100 0000 dddd address_src", "exb rbd,address_src", 0}, + {"------", 16, 8, "0110 1100 ssN0 dddd address_src", "exb rbd,address_src(rs)", 0}, + {"------", 6, 8, "1010 1100 ssss dddd", "exb rbd,rbs", 0}, + + {"------", 11, 16, "1011 0001 dddd 1010", "exts rrd", 0}, + {"------", 11, 8, "1011 0001 dddd 0000", "extsb rd", 0}, + {"------", 11, 32, "1011 0001 dddd 0111", "extsl rqd", 0}, + + {"------", 8, 16, "0111 1010 0000 0000", "halt", 0}, + {"------", 10, 16, "0011 1101 ssss dddd", "in rd,@ri", 0}, + {"------", 12, 8, "0011 1100 ssss dddd", "inb rbd,@ri", 0}, + {"------", 12, 16, "0011 1011 dddd 0100 imm16", "in rd,imm16", 0}, + {"------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0}, + {"-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0}, + {"-ZSV--", 14, 16, "0110 1001 ddN0 imm4m1 address_dst", "inc address_dst(rd),imm4m1", 0}, + {"-ZSV--", 13, 16, "0110 1001 0000 imm4m1 address_dst", "inc address_dst,imm4m1", 0}, + {"-ZSV--", 4, 16, "1010 1001 dddd imm4m1", "inc rd,imm4m1", 0}, + {"-ZSV--", 11, 8, "0010 1000 ddN0 imm4m1", "incb @rd,imm4m1", 0}, + {"-ZSV--", 14, 8, "0110 1000 ddN0 imm4m1 address_dst", "incb address_dst(rd),imm4m1", 0}, + {"-ZSV--", 13, 8, "0110 1000 0000 imm4m1 address_dst", "incb address_dst,imm4m1", 0}, + {"-ZSV--", 4, 8, "1010 1000 dddd imm4m1", "incb rbd,imm4m1", 0}, + {"---V--", 21, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 1000", "ind @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 1000 0000 aaaa ddN0 1000", "indb @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 1000 0000 aaaa ddN0 0000", "indr @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 1000 0000 aaaa ddN0 0000", "indrb @rd,@ri,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssss 0000 0000 aaaa ddN0 1000", "ini @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 0000 0000 aaaa ddN0 1000", "inib @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 0000 0000 aaaa ddN0 0000", "inir @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 0000 0000 aaaa ddN0 0000", "inirb @rd,@ri,ra", 0}, + {"CZSVDH", 13, 16, "0111 1011 0000 0000", "iret", 0}, + {"------", 10, 16, "0001 1110 ddN0 cccc", "jp cc,@rd", 0}, + {"------", 7, 16, "0101 1110 0000 cccc address_dst", "jp cc,address_dst", 0}, + {"------", 8, 16, "0101 1110 ddN0 cccc address_dst", "jp cc,address_dst(rd)", 0}, + {"------", 6, 16, "1110 cccc disp8", "jr cc,disp8", 0}, + + {"------", 7, 16, "0000 1101 ddN0 0101 imm16", "ld @rd,imm16", 0}, + {"------", 8, 16, "0010 1111 ddN0 ssss", "ld @rd,rs", 0}, + {"------", 15, 16, "0100 1101 ddN0 0101 address_dst imm16", "ld address_dst(rd),imm16", 0}, + {"------", 12, 16, "0110 1111 ddN0 ssss address_dst", "ld address_dst(rd),rs", 0}, + {"------", 14, 16, "0100 1101 0000 0101 address_dst imm16", "ld address_dst,imm16", 0}, + {"------", 11, 16, "0110 1111 0000 ssss address_dst", "ld address_dst,rs", 0}, + {"------", 14, 16, "0011 0011 ddN0 ssss imm16", "ld rd(imm16),rs", 0}, + {"------", 14, 16, "0111 0011 ddN0 ssss 0000 xxxx 0000 0000", "ld rd(rx),rs", 0}, + {"------", 7, 16, "0010 0001 ssN0 dddd", "ld rd,@rs", 0}, + {"------", 9, 16, "0110 0001 0000 dddd address_src", "ld rd,address_src", 0}, + {"------", 10, 16, "0110 0001 ssN0 dddd address_src", "ld rd,address_src(rs)", 0}, + {"------", 7, 16, "0010 0001 0000 dddd imm16", "ld rd,imm16", 0}, + {"------", 3, 16, "1010 0001 ssss dddd", "ld rd,rs", 0}, + {"------", 14, 16, "0011 0001 ssN0 dddd imm16", "ld rd,rs(imm16)", 0}, + {"------", 14, 16, "0111 0001 ssN0 dddd 0000 xxxx 0000 0000", "ld rd,rs(rx)", 0}, + + {"------", 7, 8, "0000 1100 ddN0 0101 imm8 imm8", "ldb @rd,imm8", 0}, + {"------", 8, 8, "0010 1110 ddN0 ssss", "ldb @rd,rbs", 0}, + {"------", 15, 8, "0100 1100 ddN0 0101 address_dst imm8 imm8", "ldb address_dst(rd),imm8", 0}, + {"------", 12, 8, "0110 1110 ddN0 ssss address_dst", "ldb address_dst(rd),rbs", 0}, + {"------", 14, 8, "0100 1100 0000 0101 address_dst imm8 imm8", "ldb address_dst,imm8", 0}, + {"------", 11, 8, "0110 1110 0000 ssss address_dst", "ldb address_dst,rbs", 0}, + {"------", 14, 8, "0011 0010 ddN0 ssss imm16", "ldb rd(imm16),rbs", 0}, + {"------", 14, 8, "0111 0010 ddN0 ssss 0000 xxxx 0000 0000", "ldb rd(rx),rbs", 0}, + {"------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0}, + {"------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0}, + {"------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0}, + {"------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0}, + {"------", 7, 8, "0010 0000 0000 dddd imm8 imm8", "ldb rbd,imm8", 0}, + {"------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0}, + {"------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0}, + {"------", 14, 8, "0111 0000 ssN0 dddd 0000 xxxx 0000 0000", "ldb rbd,rs(rx)", 0}, + + {"------", 11, 32, "0001 1101 ddN0 ssss", "ldl @rd,rrs", 0}, + {"------", 14, 32, "0101 1101 ddN0 ssss address_dst", "ldl address_dst(rd),rrs", 0}, + {"------", 15, 32, "0101 1101 0000 ssss address_dst", "ldl address_dst,rrs", 0}, + {"------", 17, 32, "0011 0111 ddN0 ssss imm16", "ldl rd(imm16),rrs", 0}, + {"------", 17, 32, "0111 0111 ddN0 ssss 0000 xxxx 0000 0000", "ldl rd(rx),rrs", 0}, + {"------", 11, 32, "0001 0100 ssN0 dddd", "ldl rrd,@rs", 0}, + {"------", 12, 32, "0101 0100 0000 dddd address_src", "ldl rrd,address_src", 0}, + {"------", 13, 32, "0101 0100 ssN0 dddd address_src", "ldl rrd,address_src(rs)", 0}, + {"------", 11, 32, "0001 0100 0000 dddd imm32", "ldl rrd,imm32", 0}, + {"------", 5, 32, "1001 0100 ssss dddd", "ldl rrd,rrs", 0}, + {"------", 17, 32, "0011 0101 ssN0 dddd imm16", "ldl rrd,rs(imm16)", 0}, + {"------", 17, 32, "0111 0101 ssN0 dddd 0000 xxxx 0000 0000", "ldl rrd,rs(rx)", 0}, + + {"------", 12, 16, "0111 0110 0000 dddd address_src", "lda prd,address_src", 0}, + {"------", 13, 16, "0111 0110 ssN0 dddd address_src", "lda prd,address_src(rs)", 0}, + {"------", 15, 16, "0011 0100 ssN0 dddd imm16", "lda prd,rs(imm16)", 0}, + {"------", 15, 16, "0111 0100 ssN0 dddd 0000 xxxx 0000 0000", "lda prd,rs(rx)", 0}, + {"------", 15, 16, "0011 0100 0000 dddd disp16", "ldar prd,disp16", 0}, + {"------", 7, 32, "0111 1101 ssss 1ccc", "ldctl ctrl,rs", 0}, + {"------", 7, 32, "0111 1101 dddd 0ccc", "ldctl rd,ctrl", 0}, + + {"------", 5, 16, "1011 1101 dddd imm4", "ldk rd,imm4", 0}, + + {"------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 imm4m1", "ldm @rd,rs,n", 0}, + {"------", 15, 16, "0101 1100 ddN0 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst(rd),rs,n", 0}, + {"------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 imm4m1 address_dst", "ldm address_dst,rs,n", 0}, + {"------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 imm4m1", "ldm rd,@rs,n", 0}, + {"------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src(rs),n", 0}, + {"------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 imm4m1 address_src", "ldm rd,address_src,n", 0}, + + {"CZSVDH", 12, 16, "0011 1001 ssN0 0000", "ldps @rs", 0}, + {"CZSVDH", 16, 16, "0111 1001 0000 0000 address_src", "ldps address_src", 0}, + {"CZSVDH", 17, 16, "0111 1001 ssN0 0000 address_src", "ldps address_src(rs)", 0}, + + {"------", 14, 16, "0011 0011 0000 ssss disp16", "ldr disp16,rs", 0}, + {"------", 14, 16, "0011 0001 0000 dddd disp16", "ldr rd,disp16", 0}, + {"------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0}, + {"------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0}, + {"------", 17, 32, "0011 0111 0000 ssss disp16", "ldrl disp16,rrs", 0}, + {"------", 17, 32, "0011 0101 0000 dddd disp16", "ldrl rrd,disp16", 0}, + + {"CZS---", 7, 16, "0111 1011 0000 1010", "mbit", 0}, + {"-ZS---", 12, 16, "0111 1011 dddd 1101", "mreq rd", 0}, + {"------", 5, 16, "0111 1011 0000 1001", "mres", 0}, + {"------", 5, 16, "0111 1011 0000 1000", "mset", 0}, + + {"CZSV--", 70, 16, "0001 1001 ssN0 dddd", "mult rrd,@rs", 0}, + {"CZSV--", 70, 16, "0101 1001 0000 dddd address_src", "mult rrd,address_src", 0}, + {"CZSV--", 70, 16, "0101 1001 ssN0 dddd address_src", "mult rrd,address_src(rs)", 0}, + {"CZSV--", 70, 16, "0001 1001 0000 dddd imm16", "mult rrd,imm16", 0}, + {"CZSV--", 70, 16, "1001 1001 ssss dddd", "mult rrd,rs", 0}, + {"CZSV--", 282, 32, "0001 1000 ssN0 dddd", "multl rqd,@rs", 0}, + {"CZSV--", 282, 32, "0101 1000 0000 dddd address_src", "multl rqd,address_src", 0}, + {"CZSV--", 282, 32, "0101 1000 ssN0 dddd address_src", "multl rqd,address_src(rs)", 0}, + {"CZSV--", 282, 32, "0001 1000 0000 dddd imm32", "multl rqd,imm32", 0}, + {"CZSV--", 282, 32, "1001 1000 ssss dddd", "multl rqd,rrs", 0}, + {"CZSV--", 12, 16, "0000 1101 ddN0 0010", "neg @rd", 0}, + {"CZSV--", 15, 16, "0100 1101 0000 0010 address_dst", "neg address_dst", 0}, + {"CZSV--", 16, 16, "0100 1101 ddN0 0010 address_dst", "neg address_dst(rd)", 0}, + {"CZSV--", 7, 16, "1000 1101 dddd 0010", "neg rd", 0}, + {"CZSV--", 12, 8, "0000 1100 ddN0 0010", "negb @rd", 0}, + {"CZSV--", 15, 8, "0100 1100 0000 0010 address_dst", "negb address_dst", 0}, + {"CZSV--", 16, 8, "0100 1100 ddN0 0010 address_dst", "negb address_dst(rd)", 0}, + {"CZSV--", 7, 8, "1000 1100 dddd 0010", "negb rbd", 0}, + + {"------", 7, 16, "1000 1101 0000 0111", "nop", 0}, + + {"CZS---", 7, 16, "0000 0101 ssN0 dddd", "or rd,@rs", 0}, + {"CZS---", 9, 16, "0100 0101 0000 dddd address_src", "or rd,address_src", 0}, + {"CZS---", 10, 16, "0100 0101 ssN0 dddd address_src", "or rd,address_src(rs)", 0}, + {"CZS---", 7, 16, "0000 0101 0000 dddd imm16", "or rd,imm16", 0}, + {"CZS---", 4, 16, "1000 0101 ssss dddd", "or rd,rs", 0}, + + {"CZSP--", 7, 8, "0000 0100 ssN0 dddd", "orb rbd,@rs", 0}, + {"CZSP--", 9, 8, "0100 0100 0000 dddd address_src", "orb rbd,address_src", 0}, + {"CZSP--", 10, 8, "0100 0100 ssN0 dddd address_src", "orb rbd,address_src(rs)", 0}, + {"CZSP--", 7, 8, "0000 0100 0000 dddd imm8 imm8", "orb rbd,imm8", 0}, + {"CZSP--", 4, 8, "1000 0100 ssss dddd", "orb rbd,rbs", 0}, + + {"------", 10, 16, "0011 1111 dddd ssss", "out @ro,rs", 0}, + {"------", 12, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0}, + {"------", 10, 8, "0011 1110 dddd ssss", "outb @ro,rbs", 0}, + {"------", 12, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 1010 0000 aaaa dddd 1000", "outd @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 1010 0000 aaaa dddd 1000", "outdb @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 1010 0000 aaaa dddd 0000", "otdr @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 1010 0000 aaaa dddd 0000", "otdrb @ro,@rs,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 0010 0000 aaaa dddd 1000", "outi @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 0010 0000 aaaa dddd 1000", "outib @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 0010 0000 aaaa dddd 0000", "otir @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 0010 0000 aaaa dddd 0000", "otirb @ro,@rs,ra", 0}, + + {"------", 12, 16, "0001 0111 ssN0 ddN0", "pop @rd,@rs", 0}, + {"------", 16, 16, "0101 0111 ssN0 ddN0 address_dst", "pop address_dst(rd),@rs", 0}, + {"------", 16, 16, "0101 0111 ssN0 0000 address_dst", "pop address_dst,@rs", 0}, + {"------", 8, 16, "1001 0111 ssN0 dddd", "pop rd,@rs", 0}, + + {"------", 19, 32, "0001 0101 ssN0 ddN0", "popl @rd,@rs", 0}, + {"------", 23, 32, "0101 0101 ssN0 ddN0 address_dst", "popl address_dst(rd),@rs", 0}, + {"------", 23, 32, "0101 0101 ssN0 0000 address_dst", "popl address_dst,@rs", 0}, + {"------", 12, 32, "1001 0101 ssN0 dddd", "popl rrd,@rs", 0}, + + {"------", 13, 16, "0001 0011 ddN0 ssN0", "push @rd,@rs", 0}, + {"------", 14, 16, "0101 0011 ddN0 0000 address_src", "push @rd,address_src", 0}, + {"------", 14, 16, "0101 0011 ddN0 ssN0 address_src", "push @rd,address_src(rs)", 0}, + {"------", 12, 16, "0000 1101 ddN0 1001 imm16", "push @rd,imm16", 0}, + {"------", 9, 16, "1001 0011 ddN0 ssss", "push @rd,rs", 0}, + + {"------", 20, 32, "0001 0001 ddN0 ssN0", "pushl @rd,@rs", 0}, + {"------", 21, 32, "0101 0001 ddN0 ssN0 address_src", "pushl @rd,address_src(rs)", 0}, + {"------", 21, 32, "0101 0001 ddN0 0000 address_src", "pushl @rd,address_src", 0}, + {"------", 12, 32, "1001 0001 ddN0 ssss", "pushl @rd,rrs", 0}, + + {"------", 11, 16, "0010 0011 ddN0 imm4", "res @rd,imm4", 0}, + {"------", 14, 16, "0110 0011 ddN0 imm4 address_dst", "res address_dst(rd),imm4", 0}, + {"------", 13, 16, "0110 0011 0000 imm4 address_dst", "res address_dst,imm4", 0}, + {"------", 4, 16, "1010 0011 dddd imm4", "res rd,imm4", 0}, + {"------", 10, 16, "0010 0011 0000 ssss 0000 dddd 0000 0000", "res rd,rs", 0}, + + {"------", 11, 8, "0010 0010 ddN0 imm4", "resb @rd,imm4", 0}, + {"------", 14, 8, "0110 0010 ddN0 imm4 address_dst", "resb address_dst(rd),imm4", 0}, + {"------", 13, 8, "0110 0010 0000 imm4 address_dst", "resb address_dst,imm4", 0}, + {"------", 4, 8, "1010 0010 dddd imm4", "resb rbd,imm4", 0}, + {"------", 10, 8, "0010 0010 0000 ssss 0000 dddd 0000 0000", "resb rbd,rs", 0}, + + {"CZSV--", 7, 16, "1000 1101 flags 0011", "resflg flags", 0}, + {"------", 10, 16, "1001 1110 0000 cccc", "ret cc", 0}, + + {"CZSV--", 6, 16, "1011 0011 dddd 00I0", "rl rd,imm1or2", 0}, + {"CZSV--", 6, 8, "1011 0010 dddd 00I0", "rlb rbd,imm1or2", 0}, + {"CZSV--", 6, 16, "1011 0011 dddd 10I0", "rlc rd,imm1or2", 0}, + + {"-Z----", 9, 8, "1011 0010 dddd 10I0", "rlcb rbd,imm1or2", 0}, + {"-Z----", 9, 8, "1011 1110 aaaa bbbb", "rldb rbb,rba", 0}, + + {"CZSV--", 6, 16, "1011 0011 dddd 01I0", "rr rd,imm1or2", 0}, + {"CZSV--", 6, 8, "1011 0010 dddd 01I0", "rrb rbd,imm1or2", 0}, + {"CZSV--", 6, 16, "1011 0011 dddd 11I0", "rrc rd,imm1or2", 0}, + + {"-Z----", 9, 8, "1011 0010 dddd 11I0", "rrcb rbd,imm1or2", 0}, + {"-Z----", 9, 8, "1011 1100 aaaa bbbb", "rrdb rbb,rba", 0}, + {"CZSV--", 5, 16, "1011 0111 ssss dddd", "sbc rd,rs", 0}, + {"CZSVDH", 5, 8, "1011 0110 ssss dddd", "sbcb rbd,rbs", 0}, + + {"CZSVDH", 33, 8, "0111 1111 imm8", "sc imm8", 0}, + + {"CZSV--", 15, 16, "1011 0011 dddd 1011 0000 ssss 0000 0000", "sda rd,rs", 0}, + {"CZSV--", 15, 8, "1011 0010 dddd 1011 0000 ssss 0000 0000", "sdab rbd,rs", 0}, + {"CZSV--", 15, 32, "1011 0011 dddd 1111 0000 ssss 0000 0000", "sdal rrd,rs", 0}, + + {"CZS---", 15, 16, "1011 0011 dddd 0011 0000 ssss 0000 0000", "sdl rd,rs", 0}, + {"CZS---", 15, 8, "1011 0010 dddd 0011 0000 ssss 0000 0000", "sdlb rbd,rs", 0}, + {"CZS---", 15, 32, "1011 0011 dddd 0111 0000 ssss 0000 0000", "sdll rrd,rs", 0}, + + {"------", 11, 16, "0010 0101 ddN0 imm4", "set @rd,imm4", 0}, + {"------", 14, 16, "0110 0101 ddN0 imm4 address_dst", "set address_dst(rd),imm4", 0}, + {"------", 13, 16, "0110 0101 0000 imm4 address_dst", "set address_dst,imm4", 0}, + {"------", 4, 16, "1010 0101 dddd imm4", "set rd,imm4", 0}, + {"------", 10, 16, "0010 0101 0000 ssss 0000 dddd 0000 0000", "set rd,rs", 0}, + {"------", 11, 8, "0010 0100 ddN0 imm4", "setb @rd,imm4", 0}, + {"------", 14, 8, "0110 0100 ddN0 imm4 address_dst", "setb address_dst(rd),imm4", 0}, + {"------", 13, 8, "0110 0100 0000 imm4 address_dst", "setb address_dst,imm4", 0}, + {"------", 4, 8, "1010 0100 dddd imm4", "setb rbd,imm4", 0}, + {"------", 10, 8, "0010 0100 0000 ssss 0000 dddd 0000 0000", "setb rbd,rs", 0}, + + {"CZSV--", 7, 16, "1000 1101 flags 0001", "setflg flags", 0}, + + {"------", 12, 16, "0011 1011 dddd 0101 imm16", "sin rd,imm16", 0}, + {"------", 10, 8, "0011 1010 dddd 0101 imm16", "sinb rbd,imm16", 0}, + {"---V--", 21, 16, "0011 1011 ssss 1001 0000 aaaa ddN0 1000", "sind @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 1001 0000 aaaa ddN0 1000", "sindb @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 1001 0000 aaaa ddN0 0000", "sindr @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 1001 0000 aaaa ddN0 0000", "sindrb @rd,@ri,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssss 0001 0000 aaaa ddN0 1000", "sini @rd,@ri,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssss 0001 0000 aaaa ddN0 1000", "sinib @rd,@ri,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssss 0001 0000 aaaa ddN0 0000", "sinir @rd,@ri,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssss 0001 0000 aaaa ddN0 0000", "sinirb @rd,@ri,ra", 0}, + + {"CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0}, + {"CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 0000 imm4", "slab rbd,imm4", 0}, + {"CZSV--", 13, 32, "1011 0011 dddd 1101 0000 0000 imm8", "slal rrd,imm8", 0}, + + {"CZS---", 13, 16, "1011 0011 dddd 0001 0000 0000 imm8", "sll rd,imm8", 0}, + {"CZS---", 13, 8, "1011 0010 dddd 0001 iiii iiii 0000 imm4", "sllb rbd,imm4", 0}, + {"CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0}, + + {"------", 12, 16, "0011 1011 ssss 0110 imm16", "sout imm16,rs", 0}, + {"------", 12, 8, "0011 1010 ssss 0110 imm16", "soutb imm16,rbs", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 1000", "soutd @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 1011 0000 aaaa dddd 1000", "soutdb @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 0000", "sotdr @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 1011 0000 aaaa dddd 0000", "sotdrb @ro,@rs,ra", 0}, + {"---V--", 21, 16, "0011 1011 ssN0 0011 0000 aaaa dddd 1000", "souti @ro,@rs,ra", 0}, + {"---V--", 21, 8, "0011 1010 ssN0 0011 0000 aaaa dddd 1000", "soutib @ro,@rs,ra", 0}, + {"---V--", 11, 16, "0011 1011 ssN0 0011 0000 aaaa dddd 0000", "sotir @ro,@rs,ra", 0}, + {"---V--", 11, 8, "0011 1010 ssN0 0011 0000 aaaa dddd 0000", "sotirb @ro,@rs,ra", 0}, + + {"CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0}, + {"CZSV--", 13, 8, "1011 0010 dddd 1001 iiii iiii 1111 nim4", "srab rbd,imm4", 0}, + {"CZSV--", 13, 32, "1011 0011 dddd 1101 1111 1111 nim8", "sral rrd,imm8", 0}, + + {"CZSV--", 13, 16, "1011 0011 dddd 0001 1111 1111 nim8", "srl rd,imm8", 0}, + {"CZSV--", 13, 8, "1011 0010 dddd 0001 iiii iiii 1111 nim4", "srlb rbd,imm4", 0}, + {"CZSV--", 13, 32, "1011 0011 dddd 0101 1111 1111 nim8", "srll rrd,imm8", 0}, + + {"CZSV--", 7, 16, "0000 0011 ssN0 dddd", "sub rd,@rs", 0}, + {"CZSV--", 9, 16, "0100 0011 0000 dddd address_src", "sub rd,address_src", 0}, + {"CZSV--", 10, 16, "0100 0011 ssN0 dddd address_src", "sub rd,address_src(rs)", 0}, + {"CZSV--", 7, 16, "0000 0011 0000 dddd imm16", "sub rd,imm16", 0}, + {"CZSV--", 4, 16, "1000 0011 ssss dddd", "sub rd,rs", 0}, + + {"CZSVDH", 7, 8, "0000 0010 ssN0 dddd", "subb rbd,@rs", 0}, + {"CZSVDH", 9, 8, "0100 0010 0000 dddd address_src", "subb rbd,address_src", 0}, + {"CZSVDH", 10, 8, "0100 0010 ssN0 dddd address_src", "subb rbd,address_src(rs)", 0}, + {"CZSVDH", 7, 8, "0000 0010 0000 dddd imm8 imm8", "subb rbd,imm8", 0}, + {"CZSVDH", 4, 8, "1000 0010 ssss dddd", "subb rbd,rbs", 0}, + + {"CZSV--", 14, 32, "0001 0010 ssN0 dddd", "subl rrd,@rs", 0}, + {"CZSV--", 15, 32, "0101 0010 0000 dddd address_src", "subl rrd,address_src", 0}, + {"CZSV--", 16, 32, "0101 0010 ssN0 dddd address_src", "subl rrd,address_src(rs)", 0}, + {"CZSV--", 14, 32, "0001 0010 0000 dddd imm32", "subl rrd,imm32", 0}, + {"CZSV--", 8, 32, "1001 0010 ssss dddd", "subl rrd,rrs", 0}, + + {"------", 5, 16, "1010 1111 dddd cccc", "tcc cc,rd", 0}, + {"------", 5, 8, "1010 1110 dddd cccc", "tccb cc,rbd", 0}, + + {"-ZS---", 8, 16, "0000 1101 ddN0 0100", "test @rd", 0}, + {"------", 11, 16, "0100 1101 0000 0100 address_dst", "test address_dst", 0}, + {"------", 12, 16, "0100 1101 ddN0 0100 address_dst", "test address_dst(rd)", 0}, + {"------", 7, 16, "1000 1101 dddd 0100", "test rd", 0}, + + {"-ZSP--", 8, 8, "0000 1100 ddN0 0100", "testb @rd", 0}, + {"-ZSP--", 11, 8, "0100 1100 0000 0100 address_dst", "testb address_dst", 0}, + {"-ZSP--", 12, 8, "0100 1100 ddN0 0100 address_dst", "testb address_dst(rd)", 0}, + {"-ZSP--", 7, 8, "1000 1100 dddd 0100", "testb rbd", 0}, + + {"-ZS---", 13, 32, "0001 1100 ddN0 1000", "testl @rd", 0}, + {"-ZS---", 16, 32, "0101 1100 0000 1000 address_dst", "testl address_dst", 0}, + {"-ZS---", 17, 32, "0101 1100 ddN0 1000 address_dst", "testl address_dst(rd)", 0}, + {"-ZS---", 13, 32, "1001 1100 dddd 1000", "testl rrd", 0}, + + {"-ZSV--", 25, 8, "1011 1000 ddN0 1000 0000 aaaa ssN0 0000", "trdb @rd,@rs,rba", 0}, + {"-ZSV--", 25, 8, "1011 1000 ddN0 1100 0000 aaaa ssN0 0000", "trdrb @rd,@rs,rba", 0}, + {"-ZSV--", 25, 8, "1011 1000 ddN0 0000 0000 rrrr ssN0 0000", "trib @rd,@rs,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 ddN0 0100 0000 rrrr ssN0 0000", "trirb @rd,@rs,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtdb @ra,@rb,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 aaN0 1110 0000 rrrr bbN0 1110", "trtdrb @ra,@rb,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 aaN0 0010 0000 rrrr bbN0 0000", "trtib @ra,@rb,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 aaN0 0110 0000 rrrr bbN0 1110", "trtirb @ra,@rb,rbr", 0}, + {"-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtrb @ra,@rb,rbr", 0}, + + {"--S---", 11, 16, "0000 1101 ddN0 0110", "tset @rd", 0}, + {"--S---", 14, 16, "0100 1101 0000 0110 address_dst", "tset address_dst", 0}, + {"--S---", 15, 16, "0100 1101 ddN0 0110 address_dst", "tset address_dst(rd)", 0}, + {"--S---", 7, 16, "1000 1101 dddd 0110", "tset rd", 0}, + + {"--S---", 11, 8, "0000 1100 ddN0 0110", "tsetb @rd", 0}, + {"--S---", 14, 8, "0100 1100 0000 0110 address_dst", "tsetb address_dst", 0}, + {"--S---", 15, 8, "0100 1100 ddN0 0110 address_dst", "tsetb address_dst(rd)", 0}, + {"--S---", 7, 8, "1000 1100 dddd 0110", "tsetb rbd", 0}, + + {"-ZS---", 7, 16, "0000 1001 ssN0 dddd", "xor rd,@rs", 0}, + {"-ZS---", 9, 16, "0100 1001 0000 dddd address_src", "xor rd,address_src", 0}, + {"-ZS---", 10, 16, "0100 1001 ssN0 dddd address_src", "xor rd,address_src(rs)", 0}, + {"-ZS---", 7, 16, "0000 1001 0000 dddd imm16", "xor rd,imm16", 0}, + {"-ZS---", 4, 16, "1000 1001 ssss dddd", "xor rd,rs", 0}, + + {"-ZSP--", 7, 8, "0000 1000 ssN0 dddd", "xorb rbd,@rs", 0}, + {"-ZSP--", 9, 8, "0100 1000 0000 dddd address_src", "xorb rbd,address_src", 0}, + {"-ZSP--", 10, 8, "0100 1000 ssN0 dddd address_src", "xorb rbd,address_src(rs)", 0}, + {"-ZSP--", 7, 8, "0000 1000 0000 dddd imm8 imm8", "xorb rbd,imm8", 0}, + {"-ZSP--", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0}, + + {"------", 7, 32, "1000 1100 dddd 0001", "ldctlb rbd,ctrl", 0}, + {"CZSVDH", 7, 32, "1000 1100 ssss 1001", "ldctlb ctrl,rbs", 0}, + + {"*", 0, 0, 0, 0, 0} +}; + +static int +count (void) +{ + struct op *p = opt; + int r = 0; + + while (p->name) + { + r++; + p++; + } + return r; + +} + +static int +func (const void *p1, const void *p2) +{ + const struct op *a = p1; + const struct op *b = p2; + int ret = strcmp (a->name, b->name); + if (ret != 0) + return ret; + return a->id > b->id ? 1 : -1; +} + + +/* opcode + + literal 0000 nnnn insert nnn into stream + operand 0001 nnnn insert operand reg nnn into stream +*/ + +struct tok_struct +{ + char *match; + char *token; + int length; +}; + +static struct tok_struct args[] = +{ + {"address_src(rs)", "CLASS_X+(ARG_RS)",}, + {"address_dst(rd)", "CLASS_X+(ARG_RD)",}, + + {"rs(imm16)", "CLASS_BA+(ARG_RS)",}, + {"rd(imm16)", "CLASS_BA+(ARG_RD)",}, + {"prd", "CLASS_PR+(ARG_RD)",}, + {"address_src", "CLASS_DA+(ARG_SRC)",}, + {"address_dst", "CLASS_DA+(ARG_DST)",}, + {"rd(rx)", "CLASS_BX+(ARG_RD)",}, + {"rs(rx)", "CLASS_BX+(ARG_RS)",}, + + {"disp16", "CLASS_DISP",}, + {"disp12", "CLASS_DISP",}, + {"disp7", "CLASS_DISP",}, + {"disp8", "CLASS_DISP",}, + {"flags", "CLASS_FLAGS",}, + + {"imm16", "CLASS_IMM+(ARG_IMM16)",}, + {"imm1or2", "CLASS_IMM+(ARG_IMM1OR2)",}, + {"imm32", "CLASS_IMM+(ARG_IMM32)",}, + {"imm4m1", "CLASS_IMM +(ARG_IMM4M1)",}, + {"imm4", "CLASS_IMM +(ARG_IMM4)",}, + {"n", "CLASS_IMM + (ARG_IMM4M1)",}, + {"ctrl", "CLASS_CTRL",}, + {"rba", "CLASS_REG_BYTE+(ARG_RA)",}, + {"rbb", "CLASS_REG_BYTE+(ARG_RB)",}, + {"rbd", "CLASS_REG_BYTE+(ARG_RD)",}, + {"rbs", "CLASS_REG_BYTE+(ARG_RS)",}, + {"rbr", "CLASS_REG_BYTE+(ARG_RR)",}, + + {"rrd", "CLASS_REG_LONG+(ARG_RD)",}, + {"rrs", "CLASS_REG_LONG+(ARG_RS)",}, + + {"rqd", "CLASS_REG_QUAD+(ARG_RD)",}, + + {"rd", "CLASS_REG_WORD+(ARG_RD)",}, + {"rs", "CLASS_REG_WORD+(ARG_RS)",}, + + {"@rd", "CLASS_IR+(ARG_RD)",}, + {"@ra", "CLASS_IR+(ARG_RA)",}, + {"@rb", "CLASS_IR+(ARG_RB)",}, + {"@rs", "CLASS_IR+(ARG_RS)",}, + {"@ri", "CLASS_IRO+(ARG_RS)",}, + {"@ro", "CLASS_IRO+(ARG_RD)",}, + + {"imm8", "CLASS_IMM+(ARG_IMM8)",}, + {"i2", "CLASS_IMM+(ARG_IMM2)",}, + {"cc", "CLASS_CC",}, + + {"rr", "CLASS_REG_WORD+(ARG_RR)",}, + {"ra", "CLASS_REG_WORD+(ARG_RA)",}, + {"rs", "CLASS_REG_WORD+(ARG_RS)",}, + + {"1", "CLASS_IMM+(ARG_IMM_1)",}, + {"2", "CLASS_IMM+(ARG_IMM_2)",}, + + {0, 0} +}; + +static struct tok_struct toks[] = +{ + {"0000", "CLASS_BIT+0", 1}, + {"0001", "CLASS_BIT+1", 1}, + {"0010", "CLASS_BIT+2", 1}, + {"0011", "CLASS_BIT+3", 1}, + {"0100", "CLASS_BIT+4", 1}, + {"0101", "CLASS_BIT+5", 1}, + {"0110", "CLASS_BIT+6", 1}, + {"0111", "CLASS_BIT+7", 1}, + {"1000", "CLASS_BIT+8", 1}, + {"1001", "CLASS_BIT+9", 1}, + {"1010", "CLASS_BIT+0xa", 1}, + {"1011", "CLASS_BIT+0xb", 1}, + {"1100", "CLASS_BIT+0xc", 1}, + {"1101", "CLASS_BIT+0xd", 1}, + {"1110", "CLASS_BIT+0xe", 1}, + {"1111", "CLASS_BIT+0xf", 1}, + + {"00I0", "CLASS_BIT_1OR2+0", 1}, + {"00I0", "CLASS_BIT_1OR2+1", 1}, + {"00I0", "CLASS_BIT_1OR2+2", 1}, + {"00I0", "CLASS_BIT_1OR2+3", 1}, + {"01I0", "CLASS_BIT_1OR2+4", 1}, + {"01I0", "CLASS_BIT_1OR2+5", 1}, + {"01I0", "CLASS_BIT_1OR2+6", 1}, + {"01I0", "CLASS_BIT_1OR2+7", 1}, + {"10I0", "CLASS_BIT_1OR2+8", 1}, + {"10I0", "CLASS_BIT_1OR2+9", 1}, + {"10I0", "CLASS_BIT_1OR2+0xa", 1}, + {"10I0", "CLASS_BIT_1OR2+0xb", 1}, + {"11I0", "CLASS_BIT_1OR2+0xc", 1}, + {"11I0", "CLASS_BIT_1OR2+0xd", 1}, + {"11I0", "CLASS_BIT_1OR2+0xe", 1}, + {"11I0", "CLASS_BIT_1OR2+0xf", 1}, + + {"ssss", "CLASS_REG+(ARG_RS)", 1}, + {"dddd", "CLASS_REG+(ARG_RD)", 1}, + {"aaaa", "CLASS_REG+(ARG_RA)", 1}, + {"bbbb", "CLASS_REG+(ARG_RB)", 1}, + {"rrrr", "CLASS_REG+(ARG_RR)", 1}, + + {"ssN0", "CLASS_REGN0+(ARG_RS)", 1}, + {"ddN0", "CLASS_REGN0+(ARG_RD)", 1}, + {"aaN0", "CLASS_REGN0+(ARG_RA)", 1}, + {"bbN0", "CLASS_REGN0+(ARG_RB)", 1}, + {"rrN0", "CLASS_REGN0+(ARG_RR)", 1}, + + {"cccc", "CLASS_CC", 1}, + {"nnnn", "CLASS_IMM+(ARG_IMMN)", 1}, + {"xxxx", "CLASS_REG+(ARG_RX)", 1}, + {"xxN0", "CLASS_REGN0+(ARG_RX)", 1}, + {"nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)", 1}, + + {"disp16", "CLASS_DISP+(ARG_DISP16)", 4}, + {"disp12", "CLASS_DISP+(ARG_DISP12)", 3}, + {"flags", "CLASS_FLAGS", 1}, + {"address_dst", "CLASS_ADDRESS+(ARG_DST)", 4}, + {"address_src", "CLASS_ADDRESS+(ARG_SRC)", 4}, + {"imm4m1", "CLASS_IMM+(ARG_IMM4M1)", 1}, + {"imm4", "CLASS_IMM+(ARG_IMM4)", 1}, + + {"imm8", "CLASS_IMM+(ARG_IMM8)", 2}, + {"imm16", "CLASS_IMM+(ARG_IMM16)", 4}, + {"imm32", "CLASS_IMM+(ARG_IMM32)", 8}, + {"nim4", "CLASS_IMM+(ARG_NIM4)", 2}, + {"nim8", "CLASS_IMM+(ARG_NIM8)", 2}, + {"0ccc", "CLASS_0CCC", 1}, + {"1ccc", "CLASS_1CCC", 1}, + {"disp8", "CLASS_DISP8", 2}, + {"0disp7", "CLASS_0DISP7", 2}, + {"1disp7", "CLASS_1DISP7", 2}, + {"01ii", "CLASS_01II", 1}, + {"00ii", "CLASS_00II", 1}, + + {"iiii", "CLASS_IGNORE", 1}, + {0, 0} +}; + +static char * +translate (struct tok_struct *table, char *x, int *length) +{ + + int found; + + found = 0; + while (table->match) + { + int l = strlen (table->match); + + if (strncmp (table->match, x, l) == 0) + { + /* Got a hit */ + printf ("%s", table->token); + *length += table->length; + return x + l; + } + + table++; + } + fprintf (stderr, "Can't find %s\n", x); + printf ("**** Can't find %s\n", x); + while (*x) + x++; + return x; +} + +static void +chewbits (char *bits, int *length) +{ + int n = 0; + + *length = 0; + printf ("{"); + while (*bits) + { + while (*bits == ' ') + { + bits++; + } + bits = translate (toks, bits, length); + n++; + printf (","); + + } + while (n < BYTE_INFO_LEN - 1) + { + printf ("0,"); + n++; + } + printf ("}"); +} + +static int +chewname (char **name) +{ + char *n; + int nargs = 0; + + n = *name; + while (*n && !iswhite (*n)) + n++; + + if (*n) + { + size_t len = n - *name; + char *newname = xmalloc (len + 1); + memcpy (newname, *name, len); + newname[len] = 0; + *name = newname; + } + + printf ("\"%s\",OPC_%s,0,{", *name, *name); + + /* Scan the operands and make entries for them. + Remember indirect things. */ + while (*n) + { + int d; + + while (*n == ',' || iswhite (*n)) + n++; + nargs++; + n = translate (args, n, &d); + printf (","); + } + if (nargs == 0) + { + printf ("0"); + } + printf ("},"); + return nargs; +} + +static char * +sub (char *x, char c) +{ + /* Create copy. */ + char *ret = xstrdup (x); + x = ret; + while (*x) + { + if (x[0] == c && x[1] == c && + x[2] == c && x[3] == c) + { + x[2] = 'N'; + x[3] = '0'; + } + x++; + } + return ret; +} + + +#if 0 +#define D(x) ((x) == '1' || (x) =='0') +#define M(y) (strncmp(y,x,4)==0) +static void +printmangled (char *x) +{ + return; + while (*x) + { + if (D (x[0]) && D (x[1]) && D (x[2]) && D (x[3])) + { + printf ("XXXX"); + } + else if (M ("ssss")) + { + printf ("ssss"); + } + else if (M ("dddd")) + { + printf ("dddd"); + } + else + printf ("____"); + + x += 4; + + if (x[0] == ' ') + { + printf ("_"); + x++; + } + } + +} +#endif + +/*#define WORK_TYPE*/ +static void +print_type (struct op *n) +{ +#ifdef WORK_TYPE + while (*s && !iswhite (*s)) + { + l = *s; + s++; + } + switch (l) + { + case 'l': + printf ("32,"); + break; + case 'b': + printf ("8,"); + break; + default: + printf ("16,"); + break; + } +#else + printf ("%2d,", n->type); +#endif +} + +static void +internal (void) +{ + int c = count (); + int id; + struct op *new_op = xmalloc (sizeof (struct op) * (c + 1)); + struct op *p = opt; + memcpy (new_op, p, (c + 1) * sizeof (struct op)); + + /* Assign unique id. */ + for (id = 0; id < c; id++) + new_op[id].id = id; + + /* Sort all names in table alphabetically. */ + qsort (new_op, c, sizeof (struct op), func); + + p = new_op; + while (p->flags && p->flags[0] != '*') + { + /* If there are any @rs, sub the ssss into a ssn0, (rs), (ssn0). */ + int loop = 1; + + printf ("\"%s\",%2d, ", p->flags, p->cycles); + while (loop) + { + char *s = p->name; + + loop = 0; + while (*s) + { + if (s[0] == '@') + { + char c; + + /* Skip the r and sub the string. */ + s++; + c = s[1]; + p->bits = sub (p->bits, c); + } + if (s[0] == '(' && s[3] == ')') + { + p->bits = sub (p->bits, s[2]); + } + if (s[0] == '(') + { + p->bits = sub (p->bits, s[-1]); + } + + s++; + } + + } + print_type (p); + printf ("\"%s\",\"%s\",0,\n", p->bits, p->name); + p++; + } +} + +static void +gas (void) +{ + int c = count (); + int id; + struct op *p = opt; + int idx = -1; + char *oldname = ""; + struct op *new_op = xmalloc (sizeof (struct op) * (c + 1)); + + memcpy (new_op, p, (c + 1) * sizeof (struct op)); + + /* Assign unique id. */ + for (id = 0; id < c; id++) + new_op[id].id = id; + + /* Sort all names in table alphabetically. */ + qsort (new_op, c, sizeof (struct op), func); + + printf ("/* DO NOT EDIT! -*- buffer-read-only: t -*-\n"); + printf (" This file is automatically generated by z8kgen. */\n\n"); + printf ("/* Copyright 2007, 2009 Free Software Foundation, Inc.\n\ +\n\ + This file is part of the GNU opcodes library.\n\ +\n\ + This library is free software; you can redistribute it and/or modify\n\ + it under the terms of the GNU General Public License as published by\n\ + the Free Software Foundation; either version 3, or (at your option)\n\ + any later version.\n\ +\n\ + It is distributed in the hope that it will be useful, but WITHOUT\n\ + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\ + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\ + License for more details.\n\ +\n\ + You should have received a copy of the GNU General Public License\n\ + along with this file; see the file COPYING. If not, write to the\n\ + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,\n\ + MA 02110-1301, USA. */\n\n"); + + printf ("#define ARG_MASK 0x0f\n"); + + printf ("#define ARG_SRC 0x01\n"); + printf ("#define ARG_DST 0x02\n"); + + printf ("#define ARG_RS 0x01\n"); + printf ("#define ARG_RD 0x02\n"); + printf ("#define ARG_RA 0x03\n"); + printf ("#define ARG_RB 0x04\n"); + printf ("#define ARG_RR 0x05\n"); + printf ("#define ARG_RX 0x06\n"); + + printf ("#define ARG_IMM4 0x01\n"); + printf ("#define ARG_IMM8 0x02\n"); + printf ("#define ARG_IMM16 0x03\n"); + printf ("#define ARG_IMM32 0x04\n"); + printf ("#define ARG_IMMN 0x05\n"); + printf ("#define ARG_IMMNMINUS1 0x05\n"); + printf ("#define ARG_IMM_1 0x06\n"); + printf ("#define ARG_IMM_2 0x07\n"); + printf ("#define ARG_DISP16 0x08\n"); + printf ("#define ARG_NIM8 0x09\n"); + printf ("#define ARG_IMM2 0x0a\n"); + printf ("#define ARG_IMM1OR2 0x0b\n"); + + printf ("#define ARG_DISP12 0x0b\n"); + printf ("#define ARG_NIM4 0x0c\n"); + printf ("#define ARG_DISP8 0x0c\n"); + printf ("#define ARG_IMM4M1 0x0d\n"); + + printf ("#define CLASS_X 0x10\n"); + printf ("#define CLASS_BA 0x20\n"); + printf ("#define CLASS_DA 0x30\n"); + printf ("#define CLASS_BX 0x40\n"); + printf ("#define CLASS_DISP 0x50\n"); + printf ("#define CLASS_IMM 0x60\n"); + printf ("#define CLASS_CC 0x70\n"); + printf ("#define CLASS_CTRL 0x80\n"); + printf ("#define CLASS_IGNORE 0x90\n"); + printf ("#define CLASS_ADDRESS 0xd0\n"); + printf ("#define CLASS_0CCC 0xe0\n"); + printf ("#define CLASS_1CCC 0xf0\n"); + printf ("#define CLASS_0DISP7 0x100\n"); + printf ("#define CLASS_1DISP7 0x200\n"); + printf ("#define CLASS_01II 0x300\n"); + printf ("#define CLASS_00II 0x400\n"); + printf ("#define CLASS_BIT 0x500\n"); + printf ("#define CLASS_FLAGS 0x600\n"); + printf ("#define CLASS_IR 0x700\n"); + printf ("#define CLASS_IRO 0x800\n"); + printf ("#define CLASS_DISP8 0x900\n"); + + printf ("#define CLASS_BIT_1OR2 0xa00\n"); + printf ("#define CLASS_REG 0x7000\n"); + printf ("#define CLASS_REG_BYTE 0x2000\n"); + printf ("#define CLASS_REG_WORD 0x3000\n"); + printf ("#define CLASS_REG_QUAD 0x4000\n"); + printf ("#define CLASS_REG_LONG 0x5000\n"); + printf ("#define CLASS_REGN0 0x8000\n"); + printf ("#define CLASS_PR 0x10000\n"); + printf ("#define CLASS_MASK 0x1fff0\n"); + + printf ("#define OPC_adc 0\n"); + printf ("#define OPC_adcb 1\n"); + printf ("#define OPC_add 2\n"); + printf ("#define OPC_addb 3\n"); + printf ("#define OPC_addl 4\n"); + printf ("#define OPC_and 5\n"); + printf ("#define OPC_andb 6\n"); + printf ("#define OPC_bit 7\n"); + printf ("#define OPC_bitb 8\n"); + printf ("#define OPC_call 9\n"); + printf ("#define OPC_calr 10\n"); + printf ("#define OPC_clr 11\n"); + printf ("#define OPC_clrb 12\n"); + printf ("#define OPC_com 13\n"); + printf ("#define OPC_comb 14\n"); + printf ("#define OPC_comflg 15\n"); + printf ("#define OPC_cp 16\n"); + printf ("#define OPC_cpb 17\n"); + printf ("#define OPC_cpd 18\n"); + printf ("#define OPC_cpdb 19\n"); + printf ("#define OPC_cpdr 20\n"); + printf ("#define OPC_cpdrb 21\n"); + printf ("#define OPC_cpi 22\n"); + printf ("#define OPC_cpib 23\n"); + printf ("#define OPC_cpir 24\n"); + printf ("#define OPC_cpirb 25\n"); + printf ("#define OPC_cpl 26\n"); + printf ("#define OPC_cpsd 27\n"); + printf ("#define OPC_cpsdb 28\n"); + printf ("#define OPC_cpsdr 29\n"); + printf ("#define OPC_cpsdrb 30\n"); + printf ("#define OPC_cpsi 31\n"); + printf ("#define OPC_cpsib 32\n"); + printf ("#define OPC_cpsir 33\n"); + printf ("#define OPC_cpsirb 34\n"); + printf ("#define OPC_dab 35\n"); + printf ("#define OPC_dbjnz 36\n"); + printf ("#define OPC_dec 37\n"); + printf ("#define OPC_decb 38\n"); + printf ("#define OPC_di 39\n"); + printf ("#define OPC_div 40\n"); + printf ("#define OPC_divl 41\n"); + printf ("#define OPC_djnz 42\n"); + printf ("#define OPC_ei 43\n"); + printf ("#define OPC_ex 44\n"); + printf ("#define OPC_exb 45\n"); + printf ("#define OPC_exts 46\n"); + printf ("#define OPC_extsb 47\n"); + printf ("#define OPC_extsl 48\n"); + printf ("#define OPC_halt 49\n"); + printf ("#define OPC_in 50\n"); + printf ("#define OPC_inb 51\n"); + printf ("#define OPC_inc 52\n"); + printf ("#define OPC_incb 53\n"); + printf ("#define OPC_ind 54\n"); + printf ("#define OPC_indb 55\n"); + printf ("#define OPC_indr 56\n"); + printf ("#define OPC_indrb 57\n"); + printf ("#define OPC_ini 58\n"); + printf ("#define OPC_inib 59\n"); + printf ("#define OPC_inir 60\n"); + printf ("#define OPC_inirb 61\n"); + printf ("#define OPC_iret 62\n"); + printf ("#define OPC_jp 63\n"); + printf ("#define OPC_jr 64\n"); + printf ("#define OPC_ld 65\n"); + printf ("#define OPC_lda 66\n"); + printf ("#define OPC_ldar 67\n"); + printf ("#define OPC_ldb 68\n"); + printf ("#define OPC_ldctl 69\n"); + printf ("#define OPC_ldir 70\n"); + printf ("#define OPC_ldirb 71\n"); + printf ("#define OPC_ldk 72\n"); + printf ("#define OPC_ldl 73\n"); + printf ("#define OPC_ldm 74\n"); + printf ("#define OPC_ldps 75\n"); + printf ("#define OPC_ldr 76\n"); + printf ("#define OPC_ldrb 77\n"); + printf ("#define OPC_ldrl 78\n"); + printf ("#define OPC_mbit 79\n"); + printf ("#define OPC_mreq 80\n"); + printf ("#define OPC_mres 81\n"); + printf ("#define OPC_mset 82\n"); + printf ("#define OPC_mult 83\n"); + printf ("#define OPC_multl 84\n"); + printf ("#define OPC_neg 85\n"); + printf ("#define OPC_negb 86\n"); + printf ("#define OPC_nop 87\n"); + printf ("#define OPC_or 88\n"); + printf ("#define OPC_orb 89\n"); + printf ("#define OPC_otdr 90\n"); + printf ("#define OPC_otdrb 91\n"); + printf ("#define OPC_otir 92\n"); + printf ("#define OPC_otirb 93\n"); + printf ("#define OPC_out 94\n"); + printf ("#define OPC_outb 95\n"); + printf ("#define OPC_outd 96\n"); + printf ("#define OPC_outdb 97\n"); + printf ("#define OPC_outi 98\n"); + printf ("#define OPC_outib 99\n"); + printf ("#define OPC_pop 100\n"); + printf ("#define OPC_popl 101\n"); + printf ("#define OPC_push 102\n"); + printf ("#define OPC_pushl 103\n"); + printf ("#define OPC_res 104\n"); + printf ("#define OPC_resb 105\n"); + printf ("#define OPC_resflg 106\n"); + printf ("#define OPC_ret 107\n"); + printf ("#define OPC_rl 108\n"); + printf ("#define OPC_rlb 109\n"); + printf ("#define OPC_rlc 110\n"); + printf ("#define OPC_rlcb 111\n"); + printf ("#define OPC_rldb 112\n"); + printf ("#define OPC_rr 113\n"); + printf ("#define OPC_rrb 114\n"); + printf ("#define OPC_rrc 115\n"); + printf ("#define OPC_rrcb 116\n"); + printf ("#define OPC_rrdb 117\n"); + printf ("#define OPC_sbc 118\n"); + printf ("#define OPC_sbcb 119\n"); + printf ("#define OPC_sda 120\n"); + printf ("#define OPC_sdab 121\n"); + printf ("#define OPC_sdal 122\n"); + printf ("#define OPC_sdl 123\n"); + printf ("#define OPC_sdlb 124\n"); + printf ("#define OPC_sdll 125\n"); + printf ("#define OPC_set 126\n"); + printf ("#define OPC_setb 127\n"); + printf ("#define OPC_setflg 128\n"); + printf ("#define OPC_sin 129\n"); + printf ("#define OPC_sinb 130\n"); + printf ("#define OPC_sind 131\n"); + printf ("#define OPC_sindb 132\n"); + printf ("#define OPC_sindr 133\n"); + printf ("#define OPC_sindrb 134\n"); + printf ("#define OPC_sini 135\n"); + printf ("#define OPC_sinib 136\n"); + printf ("#define OPC_sinir 137\n"); + printf ("#define OPC_sinirb 138\n"); + printf ("#define OPC_sla 139\n"); + printf ("#define OPC_slab 140\n"); + printf ("#define OPC_slal 141\n"); + printf ("#define OPC_sll 142\n"); + printf ("#define OPC_sllb 143\n"); + printf ("#define OPC_slll 144\n"); + printf ("#define OPC_sotdr 145\n"); + printf ("#define OPC_sotdrb 146\n"); + printf ("#define OPC_sotir 147\n"); + printf ("#define OPC_sotirb 148\n"); + printf ("#define OPC_sout 149\n"); + printf ("#define OPC_soutb 150\n"); + printf ("#define OPC_soutd 151\n"); + printf ("#define OPC_soutdb 152\n"); + printf ("#define OPC_souti 153\n"); + printf ("#define OPC_soutib 154\n"); + printf ("#define OPC_sra 155\n"); + printf ("#define OPC_srab 156\n"); + printf ("#define OPC_sral 157\n"); + printf ("#define OPC_srl 158\n"); + printf ("#define OPC_srlb 159\n"); + printf ("#define OPC_srll 160\n"); + printf ("#define OPC_sub 161\n"); + printf ("#define OPC_subb 162\n"); + printf ("#define OPC_subl 163\n"); + printf ("#define OPC_tcc 164\n"); + printf ("#define OPC_tccb 165\n"); + printf ("#define OPC_test 166\n"); + printf ("#define OPC_testb 167\n"); + printf ("#define OPC_testl 168\n"); + printf ("#define OPC_trdb 169\n"); + printf ("#define OPC_trdrb 170\n"); + printf ("#define OPC_trib 171\n"); + printf ("#define OPC_trirb 172\n"); + printf ("#define OPC_trtdrb 173\n"); + printf ("#define OPC_trtib 174\n"); + printf ("#define OPC_trtirb 175\n"); + printf ("#define OPC_trtrb 176\n"); + printf ("#define OPC_tset 177\n"); + printf ("#define OPC_tsetb 178\n"); + printf ("#define OPC_xor 179\n"); + printf ("#define OPC_xorb 180\n"); + + printf ("#define OPC_ldd 181\n"); + printf ("#define OPC_lddb 182\n"); + printf ("#define OPC_lddr 183\n"); + printf ("#define OPC_lddrb 184\n"); + printf ("#define OPC_ldi 185\n"); + printf ("#define OPC_ldib 186\n"); + printf ("#define OPC_sc 187\n"); + printf ("#define OPC_bpt 188\n"); + printf ("#define OPC_ext0e 188\n"); + printf ("#define OPC_ext0f 188\n"); + printf ("#define OPC_ext8e 188\n"); + printf ("#define OPC_ext8f 188\n"); + printf ("#define OPC_rsvd36 188\n"); + printf ("#define OPC_rsvd38 188\n"); + printf ("#define OPC_rsvd78 188\n"); + printf ("#define OPC_rsvd7e 188\n"); + printf ("#define OPC_rsvd9d 188\n"); + printf ("#define OPC_rsvd9f 188\n"); + printf ("#define OPC_rsvdb9 188\n"); + printf ("#define OPC_rsvdbf 188\n"); + printf ("#define OPC_ldctlb 189\n"); + printf ("#define OPC_trtdb 190\n"); + printf ("#define OPC_brk 191\n"); +#if 0 + for (i = 0; toks[i].token; i++) + printf ("#define %s\t0x%x\n", toks[i].token, i * 16); +#endif + printf ("\ntypedef struct {\n"); + + printf ("#ifdef NICENAMES\n"); + printf (" const char *nicename;\n"); + printf (" int type;\n"); + printf (" int cycles;\n"); + printf (" int flags;\n"); + printf ("#endif\n"); + printf (" const char *name;\n"); + printf (" unsigned char opcode;\n"); + printf (" void (*func) (void);\n"); + printf (" unsigned int arg_info[4];\n"); + printf (" unsigned int byte_info[%d];\n", BYTE_INFO_LEN); + printf (" int noperands;\n"); + printf (" int length;\n"); + printf (" int idx;\n"); + printf ("} opcode_entry_type;\n\n"); + printf ("#ifdef DEFINE_TABLE\n"); + printf ("const opcode_entry_type z8k_table[] = {\n"); + + while (new_op->flags && new_op->flags[0] != '*') + { + int nargs; + int length; + + printf ("\n/* %s *** %s */\n", new_op->bits, new_op->name); + printf ("{\n"); + + printf ("#ifdef NICENAMES\n"); + printf ("\"%s\",%d,%d,", new_op->name, new_op->type, new_op->cycles); + { + int answer = 0; + char *p = new_op->flags; + + while (*p) + { + answer <<= 1; + + if (*p != '-') + answer |= 1; + p++; + } + printf ("0x%02x,\n", answer); + } + + printf ("#endif\n"); + + nargs = chewname (&new_op->name); + + printf ("\n\t"); + chewbits (new_op->bits, &length); + length /= 2; + if (length & 1) + abort(); + + if (strcmp (oldname, new_op->name) != 0) + idx++; + printf (",%d,%d,%d", nargs, length, idx); + oldname = new_op->name; + printf ("},\n"); + new_op++; + } + printf ("\n/* end marker */\n"); + printf ("{\n#ifdef NICENAMES\nNULL,0,0,\n0,\n#endif\n"); + printf ("NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0}\n};\n"); + printf ("#endif\n"); +} + +int +main (int ac, char **av) +{ + struct op *p = opt; + + if (ac == 2 && strcmp (av[1], "-t") == 0) + { + internal (); + } + else if (ac == 2 && strcmp (av[1], "-h") == 0) + { + while (p->name) + { + printf ("%-25s\t%s\n", p->name, p->bits); + p++; + } + } + + else if (ac == 2 && strcmp (av[1], "-a") == 0) + { + gas (); + } + else + { + printf ("Usage: %s -t\n", av[0]); + printf ("-t : generate new internal table\n"); + printf ("-a : generate new table for gas\n"); + printf ("-h : generate new table for humans\n"); + } + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/CHANGELOG b/external/gpl3/gdb/dist/readline/CHANGELOG new file mode 100644 index 000000000000..b6499c3b7162 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/CHANGELOG @@ -0,0 +1,920 @@ +[Readline-specific changelog. Descriptions of changes to the source are + found in the bash changelog.] + + 6/9 + --- +Makefile.in + - quote value of ${INSTALL_DATA} when passing it to makes in + subdirectories + + 7/1 + --- +Makefile.in + - don't pass INSTALL_DATA to a make in the `doc' subdirectory; let + autoconf set the value itself in the Makefile + - removed a stray `-' before $(RANLIB) in the `install' recipe + +doc/Makefile.in + - add a VPATH assignment so the documentation is not remade if it's + already up-to-date in the distribution + +configure.in + - call AC_SUBST(LOCAL_LDFLAGS), since Makefile.in contains + @LOCAL_LDFLAGS@ + + 7/9 + --- + +config.h.in + - add define lines for STRUCT_WINSIZE_IN_SYS_IOCTL and + STRUCT_WINSIZE_IN_TERMIOS + +configure.in + - call BASH_STRUCT_WINSIZE to look for the definition of + `struct winsize' + + 7/17 + ---- +configure.in + - call AC_MINIX + +config.h.in + - add define line for AC_MINIX + + 7/18 + ---- +Makefile.in + - add `install-shared' and `uninstall-shared' targets + + 8/4 + --- +Makefile.in + - install and uninstall libhistory.a in the `install' and + `uninstall' targets + + 9/4 + --- +configure.in + - bumped LIBVERSION up to 2.1.1, indicating that this is patch + level 1 to release 2.1 + + + 9/16 + ---- +Makefile.in + - `make distclean' now descends into the `examples' subdir + +doc/Makefile.in + - the `distclean' and `maintainer-clean' targets should remove + Makefile + +examples/Makefile.in + - added the various clean targets + + 4/2 + --- +configure.in + - bumped LIBVERSION up to 2.2 + + 4/18 + ---- +[readline-2.2 released] + + 4/20 + ---- +Makefile.in + - make `libhistory.a' a dependency of `install' + - fixed a typo in the recipe for `install' that copied libreadline.a + to libhistory.old right after installing it + + 4/27 + ---- +doc/Makefile.in + - install {readline,history}.info out of the source directory if + they are not found in the current (build) directory -- only an + issue if the libraries are built in a different directory than + the source directory + + 5/1 + --- +support/shobj-conf + - script from the bash distribution to do shared object and library + configuration + +shlib/Makefile.in + - new directory and makefile to handle building shared versions of + libreadline and libhistory, controlled by support/shobj-conf + + 5/7 + --- +doc/Makefile.in + - set SHELL to /bin/sh, rather than relying on make to be correct + + 5/14 + ---- +savestring.c + - new file, moved from shell.c, for backwards compatibility + +Makefile.in, shlib/Makefile.in + - make sure savestring.c is compiled and added to libreadline and + libhistory + +[THERE ARE NO MORE #ifdef SHELL LINES IN THE C SOURCE FILES.] + + 5/15 + ---- +README + - updated description of shared library creation for the new scheme + +[THERE ARE NO MORE #ifdef SHELL LINES IN ANY OF THE SOURCE FILES.] + +Makefile.in + - bumped SHLIB_MAJOR up to 4 since we've augmented the library + API + - rlconf.h is now one of the installed headers, so applications can + find out whether things like vi-mode are available in the installed + libreadline + + 5/20 + ---- +configure.in + - changed RL_LIBRARY_VERSION to 4.0 to match the version of the + installed shared libraries + + 6/5 + --- +rlstdc.h + - new file + +Makefile.in + - rlstdc.h is now one of the installed headers + + 8/3 + --- +shlib/Makefile.in + - made the suffix rule that creates xx.so from xx.c write the + compiler output to `a.o', which is then mv'd to xx.so, because + some compilers (Sun WSpro 4.2, for example) don't allow any + suffixes other than `.o' for `cc -c' (not even `a.out') + + 9/15 + ---- + +Makefile.in + - AR and ARFLAGS are now substituted by configure, used in recipes + that build the libraries + +configure.in + - use AC_CHECK_PROG to check for ar + - set ARFLAGS if it has not already been set in the environment + + 10/5 + ---- +Makefile.in + - removed savestring.o from object file list + + 10/28 + ----- +shlib/Makefile.in + - don't use a fixed filename in the .c.so suffix rule to avoid + problems with parallel makes + + 12/21 + ----- +support/shlib-install + - new script to install shared readline and history libraries + +shlib/Makefile.in + - changed to call shlib-install for install and uninstall targets + +[readline-4.0-beta1 frozen] + + 12/22 + ----- +configure.in + - call AC_SUBST for SHOBJ_XLDFLAGS and SHLIB_LIBS + +shlib/Makefile.in + - SHOBJ_XLDFLAGS and SHLIB_LIBS are now substituted by configure + - add $(SHLIB_LIBS) at end of command line that builds the shared + libraries (currently needed only by AIX 4.2) + + 12/31 + ----- +MANIFEST, MANIFEST.doc + - the TOC html files are no longer generated and no longer part of + the distribution + + 2/18/1999 + --------- +configure.in + - set MAKE_SHELL to /bin/sh and substitute into the Makefiles + +Makefile.in,{doc,examples,shlib}/Makefile.in + - set SHELL from @MAKE_SHELL@ + +[readline-4.0 released] + + 3/11 + ---- +doc/Makefile.in + - removed references to HTMLTOC, since separate HTML table-of-contents + files are no longer created + +examples/Makefile.in + - remove `*.exe' in clean target for MS-DOS + +Makefile.in + - make `readline' target depend on ./libreadline.a + - configure now substitutes TERMCAP_LIB into Makefile.in + - use ${TERMCAP_LIB} instead of -ltermcap in recipe for `readline' + - clean target now removes readline and readline.exe in case they + get built + +configure.in + - use `pwd.exe' to set BUILD_DIR on MS-DOS DJGPP + + 3/15 + ---- +support/shlib-install + - Irix 5.x and Irix 6.x should install shared libraries like Solaris 2 + - changes for installing on hp-ux 1[01].x + + 3/23 + ---- +configure.in + - make sure that the $CC argument to shobj-conf is quoted + + 4/8 + --- + +xmalloc.h, rlprivate.h, rlshell.h + - new files + +Makefile.in,shlib/Makefile.in + - add dependencies on xmalloc.h, rlshell.h + - add xmalloc.h, rlprivate.h, rlshell.h to list of header files + +MANIFEST + - add xmalloc.h, rlprivate.h, rlshell.h + + 4/9 + --- +Makefile.in,shlib/Makefile.in + - add dependencies on rlprivate.h + + 4/13 + ---- +doc/Makefile.in + - add variable, PSDVI, which is the desired resolution of the + generated postscript files. Set to 300 because I don't have + any 600-dpi printers + - set LANGUAGE= before calling makeinfo, so messages are in English + - add rluserman.{info,dvi,ps,html} to appropriate variables + - add rules to create rluserman.{info,dvi,ps,html} + - install and uninstall rluserman.info, but don't update the directory + file in $(infodir) yet + +MANIFEST + - add doc/rluserman.{texinfo,info,dvi,ps,html} + + 4/30 + ---- +configure.in + - updated library version to 4.1 + + 5/3 + --- +configure.in + - SHLIB_MAJOR and SHLIB_MINOR shared library version numbers are + constructed from $LIBRARY_VERSION and substituted into Makefiles + + 5/5 + --- +support/shlib-install + - OSF/1 installs shared libraries like Solaris + +Makefile.in + - broke the header file install and uninstall into two new targets: + install-headers and uninstall-headers + - install and uninstall depend on install-headers and uninstall-headers + respectively + - changed install-shared and uninstall-shared targets to depend on + install-headers and uninstall-headers, respectively, so users may + choose to install only the shared libraries. I'm not sure about + the uninstall one yet -- maybe it should check whether or not + the static libraries are installed and not remove the header files + if they are + + 9/3 + --- +configure.in, config.h.in + - added test for memmove (for later use) + - changed version to 4.1-beta1 + + 9/13 + ---- +examples/rlfe.c + - Per Bothner's `rlfe' readline front-end program + +examples/Makefile.in + - added rules to build rlfe + + 9/21 + ---- +support/shlib-install + - changes to handle FreeBSD-3.x elf or a.out shared libraries, which + have different semantics and need different naming conventions + + 1/24/2000 + --------- +doc/Makefile.in + - remove *.bt and *.bts on `make clean' + + 2/4 + --- + + +configure.in + - changed LIBVERSION to 4.1-beta5 + + 3/17/2000 + --------- +[readline-4.1 released] + + 3/23 + ---- +Makefile.in + - remove the `-t' argument to ranlib in the install recipe; some + ranlibs don't have it and attempt to create a file named `-t' + + 3/27 + ---- +support/shlib-install + - install shared libraries unwritable by anyone on HP-UX + - changed symlinks to relative pathnames on all platforms + +shlib/Makefile.in + - added missing `includedir' assignment, substituted by configure + +Makefile.in + - added missing @SET_MAKE@ so configure can set $MAKE appropriately + +configure.in + - add call to AC_PROG_MAKE_SET + + 8/30 + ---- +shlib/Makefile.in + - change the soname bound into the shared libraries, so it includes + only the major version number. If it includes the minor version, + programs depending on it must be rebuilt (which may or may not be + a bad thing) + + 9/6 + --- +examples/rlfe.c + - add -l option to log input and output (-a option appends to logfile) + - add -n option to set readline application name + - add -v, -h options for version and help information + - change a few things because getopt() is now used to parse arguments + + 9/12 + ---- +support/shlib-install + - fix up the libname on HPUX 11 + + 10/18 + ----- +configure.in + - changed library version to 4.2-alpha + + 10/30 + ----- +configure.in + - add -fsigned-char to LOCAL_CFLAGS for Linux running on the IBM + S/390 + +Makefile.in + - added new file, rltypedefs.h, installed by default with `make install' + + 11/2 + ---- +compat.c + - new file, with backwards-compatibility function definitions + +Makefile.in,shlib/Makefile.in + - make sure that compat.o/compat.so are built and linked apppropriately + +support/shobj-conf + - picked up bash version, which means that shared libs built on + linux and BSD/OS 4.x will have an soname that does not include + the minor version number + + 11/13 + ----- +examples/rlfe.c + - rlfe can perform filename completion for relative pathnames in the + inferior process's context if the OS supports /proc/PID/cwd (linux + does it OK, Solaris is slightly warped, none of the BSDs have it) + + 11/17/2000 + ---------- +[readline-4.2-alpha released] + + 11/27 + ----- +Makefile.in,shlib/Makefile.in + - added dependencies for rltypedefs.h + +shlib/Makefile.in + - changed dependencies on histlib.h to $(topdir)/histlib.h + + 1/22 + ---- +configure.in + - changed release version to 4.2-beta + + 2/2 + --- +examples/Makefile.in + - build histexamp as part of the examples + + 2/5 + --- +doc/Makefile.in + - don't remove the dvi, postscript, html, info, and text `objects' + on a `make distclean', only on a `make maintainer-clean' + + 3/6 + --- +doc/history.{0,3}, doc/history_3.ps + - new manual page for history library + +doc/Makefile.in + - rules to install and uninstall history.3 in ${man3dir} + - rules to build history.0 and history_3.ps + + 4/2 + --- +configure.in + - changed LIBVERSION to `4.2' + + 4/5 + --- +[readline-4.2 frozen] + + 4/9 + --- +[readline-4.2 released] + + 5/2 + --- +Makefile.in,{doc,examples,shlib}/Makefile.in + - added support for DESTDIR installation root prefix, to support + building packages + +doc/Makefile.in + - add an info `dir' file entry for rluserman.info on `make install' + - change man1ext to `.1' and man3ext to `.3' + - install man pages with a $(man3ext) extension in the target directory + - add support for installing html documentation if `htmldir' has a + value + +Makefile.in + - on `make install', install from the `shlib' directory, too + - on `make uninstall', uninstall in the `doc' and `shlib' + subdirectories, too + +support/shlib-install + - add `freebsdelf*', `freebsdaout*', Hurd, `sysv4*', `sysv5*', `dgux*' + targets for symlink creation + + 5/7 + --- +configure.in, config.h.in + - check for , define HAVE_LIMITS_H if found + + 5/8 + --- +aclocal.m4 + - pick up change to BASH_CHECK_LIB_TERMCAP that adds check for + libtinfo (termcap-specific portion of ncurses-5.2) + + 5/9 + --- +configure.in + - call AC_C_CONST to find out whether or not the compiler supports + `const' + +config.h.in + - placeholder for `const' define, if any + + 5/10 + ---- +configure.in + - fix AC_CHECK_PROG(ar, ...) test to specify right value for the + case where ar is not found; should produce a better error message + + 5/14 + ---- +configure.in,config.h.in + - check for vsnprintf, define HAVE_VSNPRINTF if found + + 5/21 + ---- +configure.in, config.h.in + - add checks for size_t, ssize_t + + 5/30 + ---- +configure.in + - update autoconf to version 2.50, use in AC_PREREQ + - changed AC_INIT to new flavor + - added AC_CONFIG_SRCDIR + - AC_CONFIG_HEADER -> AC_CONFIG_HEADERS + - call AC_C_PROTOTYPES + - AC_RETSIGTYPE -> AC_TYPE_SIGNAL + + 8/22 + ---- +configure.in + - updated the version number to 4.2a + +Makefile.in,shlib/Makefile.in + - make sure tilde.o is built -DREADLINE_LIBRARY when being built as + part of the standalone library, so it picks up the right include + files + + 8/23 + ---- +support/shlib-install + - support for Darwin/MacOS X shared library installation + + 9/24 + ---- +examples/readlinebuf.h + - a new file, a C++ streambuf interface that uses readline for I/O. + Donated by Dimitris Vyzovitis + + 10/9 + ---- +configure.in + - replaced call to BASH_HAVE_TIOCGWINSZ with AC_HEADER_TIOCGWINSZ + +[readline-4.2a-beta1 frozen] + + 10/15 + ----- +configure.in, config.h.in + - check for , define HAVE_MEMORY_H if found + - check for , define HAVE_STRINGS_H if found + + 10/18 + ----- +configure.in, config.h.in + - check for isascii, define HAVE_ISASCII if found + +configure.in + - changed the macro names from bash as appropriate: + BASH_SIGNAL_CHECK -> BASH_SYS_SIGNAL_VINTAGE + BASH_REINSTALL_SIGHANDLERS -> BASH_SYS_REINSTALL_SIGHANDLERS + BASH_MISC_SPEED_T -> BASH_CHECK_SPEED_T + + 10/22 + ----- +configure.in + - check for isxdigit with AC_CHECK_FUNCS + +config.h.in + - new define for HAVE_ISXDIGIT + + 10/29 + ----- +configure.in, config.h.in + - check for strpbrk with AC_CHECK_FUNCS, define HAVE_STRPBRK if found + + 11/1 + ---- +Makefile.in + - make sure DESTDIR is passed to install and uninstall makes in + subdirectories + - when saving old copies of installed libraries, make sure we use + DESTDIR for the old installation tree + +[readline-4.2a-rc1 frozen] + + 11/2 + ---- +Makefile.in, shlib/Makefile.in + - don't put -I$(includedir) into CFLAGS + + 11/15 + ----- +[readline-4.2a released] + + 11/20 + ----- +examples/rlcat.c + - new file + +examples/Makefile.in + - changes for rlcat + + 11/28 + ----- +configure.in + - default TERMCAP_LIB to -lcurses if $prefer_curses == yes (as when + --with-curses is supplied) + +examples/Makefile.in + - substitute @LDFLAGS@ in LDFLAGS assignment + + 11/29 + ----- +config.h.in + - add necessary defines for multibyte include files and functions + - add code to define HANDLE_MULTIBYTE if prerequisites are met + +configure.in + - call BASH_CHECK_MULTIBYTE + + 12/14 + ----- +config.h.in + - add #undef PROTOTYPES, filled in by AC_C_PROTOTYPES + + 12/17 + ----- +config.h.in + - moved HANDLE_MULTIBYTE code to rlmbutil.h + +rlmbutil.h, mbutil.c + - new files + +Makefile.in, shlib/Makefile.in + - added rules for mbutil.c + + 12/20 + ----- +configure.in + - added --enable-shared, --enable-static options to configure to + say which libraries are built by default (both default to yes) + - if SHLIB_STATUS == 'unsupported', turn off default shared library + building + - substitute new STATIC_TARGET, SHARED_TARGET, STATIC_INSTALL_TARGET, + and SHARED_INSTALL_TARGET + +Makefile.in + - `all' target now depends on (substituted) @STATIC_TARGET@ and + @SHARED_TARGET@ + - `install' target now depends on (substituted) @STATIC_INSTALL_TARGET@ + and @SHARED_INSTALL_TARGET@ + +INSTALL, README + - updated with new info about --enable-shared and --enable-static + + 1/10/2002 + --------- +configure.in + - bumped the library version number to 4.3 + + 1/24 + ---- +Makefile.in,shlib/Makefile.in + - changes for new file, text.c, with character and text handling + functions from readline.c + + 2/20 + ---- +{configure.config.h}.in + - call AC_C_CHAR_UNSIGNED, define __CHAR_UNSIGNED__ if chars are + unsigned by default + + 5/20 + ---- +doc/Makefile.in + - new maybe-clean target that removes the generated documentation if + the build directory differs from the source directory + - distclean target now depends on maybe-clean + + 7/17 + ---- +[readline-4.3 released] + + 7/18 + ---- +shlib/Makefile.in + - fix bad dependency: text.so: terminal.c, make it depend on text.c + + 8/7 + --- +support/shlib-install + - break `linux' out into its own stanza: it seems that linux + distributions are all moving to the following scheme: + + libreadline.so.4.3 installed version + libreadline.so.4 -> libreadline.so.4.3 symlink + libreadline.so -> libreadline.so.4 symlink + + 10/29 + ----- +support/shlib-install + - change INSTALL_LINK[12] to use `&&' instead of `;' so it only + tries the link if the cd succeeds; put ${echo} in there, too + - use $LN instead of `ln -s' so it works on machines without symlinks + - change special linux stanza to use cd before ln also + - change to use $INSTALL_LINK1 and $INSTALL_LINK2 appropriately + instead of explicit commands in various stanzas + + 2/1 + --- +config.h.in + - add HAVE_MBRTOWC and HAVE_MBRLEN + - add NO_MULTIBYTE_SUPPORT for new configure argument + - add STDC_HEADERS + +configure.in + - new argument --enable-multibyte (enabled by default), allows + multibyte support to be turned off even on systems that support it + - add check for ansi stdc headers with call to AC_HEADER_STDC + + 2/3 + --- +configure.in + - add call to BASH_FUNC_CTYPE_NONASCII + +config.h.in + - add CTYPE_NON_ASCII + + 2/20 + ---- + +doc/manvers.texinfo + - renamed to version.texi to match other GNU software + - UPDATE-MONTH variable is now `UPDATED-MONTH' + +doc/{hist,rlman,rluserman}.texinfo + - include version.texi + +doc/{rltech,rluser,hstech,hsuser}.texi + - changed the suffix from `texinfo' to `texi' + +doc/Makefile.in + - made appropriate changes for {{rl,hs}tech,{rl,hs}user}.texi + +doc/{rlman,rluserman}.texinfo + - changed the suffix from `texinfo' to `texi' + +doc/hist.texinfo + - renamed to history.texi to be more consistent + + 6/11 + ---- +shlib/Makefile.in + - have configure substitute value of `@LDFLAGS@' into the assignment + to SHLIB_XLDFLAGS + + 6/16 + ---- +configure.in + - readline and history libraries are now at version 5.0 + + 8/18 + ---- +support/shlib-install + - support for FreeBSD-gnu (from Robert Millan) + + 12/4 + ---- +Makefile.in + - add variables for localedir and the PACKAGE_* variables, auto-set + by configure + + 12/9 + ---- +Makefile.in + - use mkinstalldirs instead of mkdirs + + 4/22 + ---- +Makefile.in + - separate doc install/uninstall out into two new targets: + install-doc and uninstall-doc + - make install-doc and uninstall-doc prerequisites of appropriate + install and uninstall targets + +examples/rl-fgets.c + - new example from Harold Levy that wraps fgets replacement functions + that call readline in a shared library that can be interposed with + LD_PRELOAD + + 7/27 + ---- +[readline-5.0 released] + + 11/15 + ----- +examples/rlfe/{ChangeLog,Makefile.in,README,config.h.in,configure,configure.in,extern.h,os.h,pty.c,rlfe.c,screen.h} + - new version of rlfe, rlfe-0.4, from Per Bothner; now a standalone + application + + 11/16 + ----- +shlib/Makefile.in + - substitute TERMCAP_LIB in from configure + +configure.in + - if SHLIB_LIBS doesn't include a termcap library (curses, ncurses, + termcap, termlib), append the value of $TERMCAP_LIB to it + + 11/30 + ----- +configure.in + - take out change from 11/16; it doesn't work for some systems (e.g., + SunOS 4.x and Solaris 2.6) + - add support for --enable-purify configure argument + - pass TERMCAP_LIB in environment when calling shobj-conf + +examples/Makefile.in + - add support for building examples with purify + + 1/23/2005 + --------- +configure.in + - set BUILD_DIR to contain backslashes to escape any spaces in the + directory name -- this is what make will accept in targets and + prerequisites, so it's better than trying to use double quotes + + 2/25 + ---- +configure.in + - change check for sys/ptem.h to include sys/stream.h if present, to + avoid the `present but cannot be compiled' messages on Solaris and + SVR4.2 (does anyone still use SVR4.2?) + + 5/7 + --- +configure.in + - add cross-compiling support from the bash configure.in, which cygwin + and mingw have apparently adopted + - add check for pwd.h, fcntl.h + - add checks for fcntl, kill system calls + - add checks for getpw{ent,nam,uid} C library functions + - pass a compile-time option through to Makefiles if cross-compiling + +config.h.in + - add HAVE_PWD_H for , HAVE_FCNTL_H for + - add HAVE_FCNTL, HAVE_KILL for respective system calls + - add HAVE_GETPW{ENT,NAM,UID} for passwd functions + +Makefile.in,shlib/Makefile.in + - @CROSS_COMPILE@ is substituted into DEFS (equal to -DCROSS_COMPILING + if bash is being cross-compiled) + + 8/2 + --- +examples/Makefile.in + - use $(READLINE_LIB) instead of -lreadline to get around MacOS X 10.4's + preference for (incompatible) shared libraries over static libraries + in the load path + + 8/11 + ---- +support/shobj-conf + - new variable: SHLIB_LIBPREF, prefix for shared library name (defaults + to `lib' + - new variable: SHLIB_DLLVERSION, used on Cygwin to set the library + version number + - new variable: SHLIB_DOT, separator character between library name and + suffix and version information (defaults to `.') + - new stanza for cygwin to generate windows-compatible dll + +support/shlib-install + - add new option `-b bindir' for systems like cygwin/windows that + require it + - new stanza for cygwin that installs a dll into $bindir and an implied + link library into $libdir + +configure.in + - substitute new variables from shobj-conf + +shlib/Makefile.in + - substitute bindir, SHLIB_DOT, SHLIB_LIBPREF, SHLIB_DLLVERSION from + configure + - pass `-b $(bindir)' to shlib-install for install and uninstall targets + - library names now use $SHLIB_LIBPREF and $SHLIB_DOT + +INSTALL,README + - document new SHLIB_DOT, SHLIB_LIBPREF, and SHLIB_DLLVERSION variables + + 10/4 + ---- +[readline-5.1-beta1 frozen] + + 12/1 + ---- +configure.in + - changed release status to `release' + +[readline-5.1 frozen] diff --git a/external/gpl3/gdb/dist/readline/CHANGES b/external/gpl3/gdb/dist/readline/CHANGES new file mode 100644 index 000000000000..1ba0c1256df4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/CHANGES @@ -0,0 +1,921 @@ +This document details the changes between this version, readline-5.1, +and the previous version, readline-5.0. + +1. Changes to Readline + +a. Fixed a bug that caused multiliine prompts to be wrapped and displayed + incorrectly. + +b. Fixed a bug that caused ^P/^N in emacs mode to fail to display the current + line correctly. + +c. Fixed a problem in computing the number of invisible characters on the first + line of a prompt whose length exceeds the screen width. + +d. Fixed vi-mode searching so that failure preserves the current line rather + than the last line in the history list. + +e. Fixed the vi-mode `~' command (change-case) to have the correct behavior at + end-of-line when manipulating multibyte characters. + +f. Fixed the vi-mode `r' command (change-char) to have the correct behavior at + end-of-line when manipulating multibyte characters. + +g. Fixed multiple bugs in the redisplay of multibyte characters: displaying + prompts longer than the screen width containing multibyte characters, + +h. Fix the calculation of the number of physical characters in the prompt + string when it contains multibyte characters. + +i. A non-zero value for the `rl_complete_suppress_append' variable now causes + no `/' to be appended to a directory name. + +j. Fixed forward-word and backward-word to work when words contained + multibyte characters. + +k. Fixed a bug in finding the delimiter of a `?' substring when performing + history expansion in a locale that supports multibyte characters. + +l. Fixed a memory leak caused by not freeing the timestamp in a history entry. + +m. Fixed a bug that caused "\M-x" style key bindings to not obey the setting + of the `convert-meta' variable. + +n. Fixed saving and restoring primary prompt when prompting for incremental + and non-incremental searches; search prompts now display multibyte + characters correctly. + +o. Fixed a bug that caused keys originally bound to self-insert but shadowed + by a multi-character key sequence to not be inserted. + +p. Fixed code so rl_prep_term_function and rl_deprep_term_function aren't + dereferenced if NULL (matching the documentation). + +q. Extensive changes to readline to add enough state so that commands + requiring additional characters (searches, multi-key sequences, numeric + arguments, commands requiring an additional specifier character like + vi-mode change-char, etc.) work without synchronously waiting for + additional input. + +r. Lots of changes so readline builds and runs on MinGW. + +s. Readline no longer tries to modify the terminal settings when running in + callback mode. + +t. The Readline display code no longer sets the location of the last invisible + character in the prompt if the \[\] sequence is empty. + +u. The `change-case' command now correctly changes the case of multibyte + characters. + +v. Changes to the shared library construction scripts to deal with Windows + DLL naming conventions for Cygwin. + +w. Fixed the redisplay code to avoid core dumps resulting from a poorly-timed + SIGWINCH. + +x. Fixed the non-incremental search code in vi mode to dispose of any current + undo list when copying a line from the history into the current editing + buffer. + +y. Fixed a bug that caused reversing the incremental search direction to + not work correctly. + +z. Fixed the vi-mode `U' command to only undo up to the first time insert mode + was entered, as Posix specifies. + +aa. Fixed a bug in the vi-mode `r' command that left the cursor in the wrong + place. + +bb. Fixed a redisplay bug caused by moving the cursor vertically to a line + with invisible characters in the prompt in a multibyte locale. + +cc. Fixed a bug that could cause the terminal special chars to be bound in the + wrong keymap in vi mode. + +2. New Features in Readline + +a. The key sequence sent by the keypad `delete' key is now automatically + bound to delete-char. + +b. A negative argument to menu-complete now cycles backward through the + completion list. + +c. A new bindable readline variable: bind-tty-special-chars. If non-zero, + readline will bind the terminal special characters to their readline + equivalents when it's called (on by default). + +d. New bindable command: vi-rubout. Saves deleted text for possible + reinsertion, as with any vi-mode `text modification' command; `X' is bound + to this in vi command mode. + +e. If the rl_completion_query_items is set to a value < 0, readline never + asks the user whether or not to view the possible completions. + +f. The `C-w' binding in incremental search now understands multibyte + characters. + +g. New application-callable auxiliary function, rl_variable_value, returns + a string corresponding to a readline variable's value. + +h. When parsing inputrc files and variable binding commands, the parser + strips trailing whitespace from values assigned to boolean variables + before checking them. + +i. A new external application-controllable variable that allows the LINES + and COLUMNS environment variables to set the window size regardless of + what the kernel returns. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-5.0, +and the previous version, readline-4.3. + +1. Changes to Readline + +a. Fixes to avoid core dumps because of null pointer references in the + multibyte character code. + +b. Fix to avoid infinite recursion caused by certain key combinations. + +c. Fixed a bug that caused the vi-mode `last command' to be set incorrectly. + +d. Readline no longer tries to read ahead more than one line of input, even + when more is available. + +e. Fixed the code that adjusts the point to not mishandle null wide + characters. + +f. Fixed a bug in the history expansion `g' modifier that caused it to skip + every other match. + +g. Fixed a bug that caused the prompt to overwrite previous output when the + output doesn't contain a newline and the locale supports multibyte + characters. This same change fixes the problem of readline redisplay + slowing down dramatically as the line gets longer in multibyte locales. + +h. History traversal with arrow keys in vi insertion mode causes the cursor + to be placed at the end of the new line, like in emacs mode. + +i. The locale initialization code does a better job of using the right + precedence and defaulting when checking the appropriate environment + variables. + +j. Fixed the history word tokenizer to handle <( and >( better when used as + part of bash. + +k. The overwrite mode code received several bug fixes to improve undo. + +l. Many speedups to the multibyte character redisplay code. + +m. The callback character reading interface should not hang waiting to read + keyboard input. + +n. Fixed a bug with redoing vi-mode `s' command. + +o. The code that initializes the terminal tracks changes made to the terminal + special characters with stty(1) (or equivalent), so that these changes + are reflected in the readline bindings. New application-callable function + to make it work: rl_tty_unset_default_bindings(). + +p. Fixed a bug that could cause garbage to be inserted in the buffer when + changing character case in vi mode when using a multibyte locale. + +q. Fixed a bug in the redisplay code that caused problems on systems + supporting multibyte characters when moving between history lines when the + new line has more glyphs but fewer bytes. + +r. Undo and redo now work better after exiting vi insertion mode. + +s. Make sure system calls are restarted after a SIGWINCH is received using + SA_RESTART. + +t. Improvements to the code that displays possible completions when using + multibyte characters. + +u. Fixed a problem when parsing nested if statements in inputrc files. + +v. The completer now takes multibyte characters into account when looking for + quoted substrings on which to perform completion. + +w. The history search functions now perform better bounds checking on the + history list. + +x. Change to history expansion functions to treat `^' as equivalent to word + one, as the documention states. + +y. Some changes to the display code to improve display and redisplay of + multibyte characters. + +z. Changes to speed up the multibyte character redisplay code. + +aa. Fixed a bug in the vi-mode `E' command that caused it to skip over the + last character of a word if invoked while point was on the word's + next-to-last character. + +bb. Fixed a bug that could cause incorrect filename quoting when + case-insensitive completion was enabled and the word being completed + contained backslashes quoting word break characters. + +cc. Fixed a bug in redisplay triggered when the prompt string contains + invisible characters. + +dd. Fixed some display (and other) bugs encountered in multibyte locales + when a non-ascii character was the last character on a line. + +ee. Fixed some display bugs caused by multibyte characters in prompt strings. + +ff. Fixed a problem with history expansion caused by non-whitespace characters + used as history word delimiters. + +gg. Fixed a problem that could cause readline to refer to freed memory when + moving between history lines while doing searches. + +hh. Improvements to the code that expands and displays prompt strings + containing multibyte characters. + +ii. Fixed a problem with vi-mode not correctly remembering the numeric argument + to the last `c'hange command for later use with `.'. + +jj. Fixed a bug in vi-mode that caused multi-digit count arguments to work + incorrectly. + +kk. Fixed a problem in vi-mode that caused the last text modification command + to not be remembered across different command lines. + +ll. Fixed problems with changing characters and changing case at the end of + the line. + +mm. Fixed a problem with readline saving the contents of the current line + before beginning a non-interactive search. + +nn. Fixed a problem with EOF detection when using rl_event_hook. + +oo. Fixed a problem with the vi mode `p' and `P' commands ignoring numeric + arguments. + +2. New Features in Readline + +a. History expansion has a new `a' modifier equivalent to the `g' modifier + for compatibility with the BSD csh. + +b. History expansion has a new `G' modifier equivalent to the BSD csh `g' + modifier, which performs a substitution once per word. + +c. All non-incremental search operations may now undo the operation of + replacing the current line with the history line. + +d. The text inserted by an `a' command in vi mode can be reinserted with + `.'. + +e. New bindable variable, `show-all-if-unmodified'. If set, the readline + completer will list possible completions immediately if there is more + than one completion and partial completion cannot be performed. + +f. There is a new application-callable `free_history_entry()' function. + +g. History list entries now contain timestamp information; the history file + functions know how to read and write timestamp information associated + with each entry. + +h. Four new key binding functions have been added: + + rl_bind_key_if_unbound() + rl_bind_key_if_unbound_in_map() + rl_bind_keyseq_if_unbound() + rl_bind_keyseq_if_unbound_in_map() + +i. New application variable, rl_completion_quote_character, set to any + quote character readline finds before it calls the application completion + function. + +j. New application variable, rl_completion_suppress_quote, settable by an + application completion function. If set to non-zero, readline does not + attempt to append a closing quote to a completed word. + +k. New application variable, rl_completion_found_quote, set to a non-zero + value if readline determines that the word to be completed is quoted. + Set before readline calls any application completion function. + +l. New function hook, rl_completion_word_break_hook, called when readline + needs to break a line into words when completion is attempted. Allows + the word break characters to vary based on position in the line. + +m. New bindable command: unix-filename-rubout. Does the same thing as + unix-word-rubout, but adds `/' to the set of word delimiters. + +n. When listing completions, directories have a `/' appended if the + `mark-directories' option has been enabled. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-4.3, +and the previous version, readline-4.2a. + +1. Changes to Readline + +a. Fixed output of comment-begin character when listing variable values. + +b. Added some default key bindings for common escape sequences produced by + HOME and END keys. + +c. Fixed the mark handling code to be more emacs-compatible. + +d. A bug was fixed in the code that prints possible completions to keep it + from printing empty strings in certain circumstances. + +e. Change the key sequence printing code to print ESC as M\- if ESC is a + meta-prefix character -- it's easier for users to understand than \e. + +f. Fixed unstifle_history() to return values that match the documentation. + +g. Fixed the event loop (rl_event_hook) to handle the case where the input + file descriptor is invalidated. + +h. Fixed the prompt display code to work better when the application has a + custom redisplay function. + +i. Changes to make reading and writing the history file a little faster, and + to cope with huge history files without calling abort(3) from xmalloc. + +j. The vi-mode `S' and `s' commands are now undone correctly. + +k. Fixed a problem which caused the display to be messed up when the last + line of a multi-line prompt (possibly containing invisible characters) + was longer than the screen width. + +2. New Features in Readline + +a. Support for key `subsequences': allows, e.g., ESC and ESC-a to both + be bound to readline functions. Now the arrow keys may be used in vi + insert mode. + +b. When listing completions, and the number of lines displayed is more than + the screen length, readline uses an internal pager to display the results. + This is controlled by the `page-completions' variable (default on). + +c. New code to handle editing and displaying multibyte characters. + +d. The behavior introduced in bash-2.05a of deciding whether or not to + append a slash to a completed name that is a symlink to a directory has + been made optional, controlled by the `mark-symlinked-directories' + variable (default is the 2.05a behavior). + +e. The `insert-comment' command now acts as a toggle if given a numeric + argument: if the first characters on the line don't specify a + comment, insert one; if they do, delete the comment text + +f. New application-settable completion variable: + rl_completion_mark_symlink_dirs, allows an application's completion + function to temporarily override the user's preference for appending + slashes to names which are symlinks to directories. + +g. New function available to application completion functions: + rl_completion_mode, to tell how the completion function was invoked + and decide which argument to supply to rl_complete_internal (to list + completions, etc.). + +h. Readline now has an overwrite mode, toggled by the `overwrite-mode' + bindable command, which could be bound to `Insert'. + +i. New application-settable completion variable: + rl_completion_suppress_append, inhibits appending of + rl_completion_append_character to completed words. + +j. New key bindings when reading an incremental search string: ^W yanks + the currently-matched word out of the current line into the search + string; ^Y yanks the rest of the current line into the search string, + DEL or ^H deletes characters from the search string. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-4.2a, +and the previous version, readline-4.2. + +1. Changes to Readline + +a. More `const' and type casting fixes. + +b. Changed rl_message() to use vsnprintf(3) (if available) to fix buffer + overflow problems. + +c. The completion code no longer appends a `/' or ` ' to a match when + completing a symbolic link that resolves to a directory name, unless + the match does not add anything to the word being completed. This + means that a tab will complete the word up to the full name, but not + add anything, and a subsequent tab will add a slash. + +d. Fixed a trivial typo that made the vi-mode `dT' command not work. + +e. Fixed the tty code so that ^S and ^Q can be inserted with rl_quoted_insert. + +f. Fixed the tty code so that ^V works more than once. + +g. Changed the use of __P((...)) for function prototypes to PARAMS((...)) + because the use of __P in typedefs conflicted g++ and glibc. + +h. The completion code now attempts to do a better job of preserving the + case of the word the user typed if ignoring case in completions. + +i. Readline defaults to not echoing the input and lets the terminal + initialization code enable echoing if there is a controlling terminal. + +j. The key binding code now processes only two hex digits after a `\x' + escape sequence, and the documentation was changed to note that the + octal and hex escape sequences result in an eight-bit value rather + than strict ASCII. + +k. Fixed a few places where negative array subscripts could have occurred. + +l. Fixed the vi-mode code to use a better method to determine the bounds of + the array used to hold the marks, and to avoid out-of-bounds references. + +m. Fixed the defines in chardefs.h to work better when chars are signed. + +n. Fixed configure.in to use the new names for bash autoconf macros. + +o. Readline no longer attempts to define its own versions of some ctype + macros if they are implemented as functions in libc but not as macros in + . + +p. Fixed a problem where rl_backward could possibly set point to before + the beginning of the line. + +q. Fixed Makefile to not put -I/usr/include into CFLAGS, since it can cause + include file problems. + +2. New Features in Readline + +a. Added extern declaration for rl_get_termcap to readline.h, making it a + public function (it was always there, just not in readline.h). + +b. New #defines in readline.h: RL_READLINE_VERSION, currently 0x0402, + RL_VERSION_MAJOR, currently 4, and RL_VERSION_MINOR, currently 2. + +c. New readline variable: rl_readline_version, mirrors RL_READLINE_VERSION. + +d. New bindable boolean readline variable: match-hidden-files. Controls + completion of files beginning with a `.' (on Unix). Enabled by default. + +e. The history expansion code now allows any character to terminate a + `:first-' modifier, like csh. + +f. The incremental search code remembers the last search string and uses + it if ^R^R is typed without a search string. + +h. New bindable variable `history-preserve-point'. If set, the history + code attempts to place the user at the same location on each history + line retrived with previous-history or next-history. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-4.2, +and the previous version, readline-4.1. + +1. Changes to Readline + +a. When setting the terminal attributes on systems using `struct termio', + readline waits for output to drain before changing the attributes. + +b. A fix was made to the history word tokenization code to avoid attempts to + dereference a null pointer. + +c. Readline now defaults rl_terminal_name to $TERM if the calling application + has left it unset, and tries to initialize with the resultant value. + +d. Instead of calling (*rl_getc_function)() directly to get input in certain + places, readline now calls rl_read_key() consistently. + +e. Fixed a bug in the completion code that allowed a backslash to quote a + single quote inside a single-quoted string. + +f. rl_prompt is no longer assigned directly from the argument to readline(), + but uses memory allocated by readline. This allows constant strings to + be passed to readline without problems arising when the prompt processing + code wants to modify the string. + +g. Fixed a bug that caused non-interactive history searches to return the + wrong line when performing multiple searches backward for the same string. + +h. Many variables, function arguments, and function return values are now + declared `const' where appropriate, to improve behavior when linking with + C++ code. + +i. The control character detection code now works better on systems where + `char' is unsigned by default. + +j. The vi-mode numeric argument is now capped at 999999, just like emacs mode. + +k. The Function, CPFunction, CPPFunction, and VFunction typedefs have been + replaced with a set of specific prototyped typedefs, though they are + still in the readline header files for backwards compatibility. + +m. Nearly all of the (undocumented) internal global variables in the library + now have an _rl_ prefix -- there were a number that did not, like + screenheight, screenwidth, alphabetic, etc. + +n. The ding() convenience function has been renamed to rl_ding(), though the + old function is still defined for backwards compatibility. + +o. The completion convenience functions filename_completion_function, + username_completion_function, and completion_matches now have an rl_ + prefix, though the old names are still defined for backwards compatibility. + +p. The functions shared by readline and bash (linkage is satisfied from bash + when compiling with bash, and internally otherwise) now have an sh_ prefix. + +q. Changed the shared library creation procedure on Linux and BSD/OS 4.x so + that the `soname' contains only the major version number rather than the + major and minor numbers. + +r. Fixed a redisplay bug that occurred when the prompt spanned more than one + physical line and contained invisible characters. + +s. Added a missing `includedir' variable to the Makefile. + +t. When installing the shared libraries, make sure symbolic links are relative. + +u. Added configure test so that it can set `${MAKE}' appropriately. + +v. Fixed a bug in rl_forward that could cause the point to be set to before + the beginning of the line in vi mode. + +w. Fixed a bug in the callback read-char interface to make it work when a + readline function pushes some input onto the input stream with + rl_execute_next (like the incremental search functions). + +x. Fixed a file descriptor leak in the history file manipulation code that + was tripped when attempting to truncate a non-regular file (like + /dev/null). + +y. Changes to make all of the exported readline functions declared in + readline.h have an rl_ prefix (rltty_set_default_bindings is now + rl_tty_set_default_bindings, crlf is now rl_crlf, etc.) + +z. The formatted documentation included in the base readline distribution + is no longer removed on a `make distclean'. + +aa. Some changes were made to avoid gcc warnings with -Wall. + +bb. rl_get_keymap_by_name now finds keymaps case-insensitively, so + `set keymap EMACS' works. + +cc. The history file writing and truncation functions now return a useful + status on error. + +dd. Fixed a bug that could cause applications to dereference a NULL pointer + if a NULL second argument was passed to history_expand(). + +ee. If a hook function assigned to rl_event_hook sets rl_done to a non-zero + value, rl_read_key() now immediately returns '\n' (which is assumed to + be bound to accept-line). + +2. New Features in Readline + +a. The blink timeout for paren matching is now settable by applications, + via the rl_set_paren_blink_timeout() function. + +b. _rl_executing_macro has been renamed to rl_executing_macro, which means + it's now part of the public interface. + +c. Readline has a new variable, rl_readline_state, which is a bitmap that + encapsulates the current state of the library; intended for use by + callbacks and hook functions. + +d. rlfe has a new -l option to log input and output (-a appends to logfile), + a new -n option to set the readline application name, and -v and -h + options for version and help information. + +e. rlfe can now perform filename completion for the inferior process if the + OS has a /proc//cwd that can be read with readlink(2) to get the + inferior's current working directory. + +f. A new file, rltypedefs.h, contains the new typedefs for function pointers + and is installed by `make install'. + +g. New application-callable function rl_set_prompt(const char *prompt): + expands its prompt string argument and sets rl_prompt to the result. + +h. New application-callable function rl_set_screen_size(int rows, int cols): + public method for applications to set readline's idea of the screen + dimensions. + +i. The history example program (examples/histexamp.c) is now built as one + of the examples. + +j. The documentation has been updated to cover nearly all of the public + functions and variables declared in readline.h. + +k. New function, rl_get_screen_size (int *rows, int *columns), returns + readline's idea of the screen dimensions. + +l. The timeout in rl_gather_tyi (readline keyboard input polling function) + is now settable via a function (rl_set_keyboard_input_timeout()). + +m. Renamed the max_input_history variable to history_max_entries; the old + variable is maintained for backwards compatibility. + +n. The list of characters that separate words for the history tokenizer is + now settable with a variable: history_word_delimiters. The default + value is as before. + +o. There is a new history.3 manual page documenting the history library. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-4.1, +and the previous version, readline-4.0. + +1. Changes to Readline + +a. Changed the HTML documents so that the table-of-contents is no longer + a separate file. + +b. Changes to the shared object configuration for: Irix 5.x, Irix 6.x, + OSF/1. + +c. The shared library major and minor versions are now constructed + automatically by configure and substituted into the makefiles. + +d. It's now possible to install the shared libraries separately from the + static libraries. + +e. The history library tries to truncate the history file only if it is a + regular file. + +f. A bug that caused _rl_dispatch to address negative array indices on + systems with signed chars was fixed. + +g. rl-yank-nth-arg now leaves the history position the same as when it was + called. + +h. Changes to the completion code to handle MS-DOS drive-letter:pathname + filenames. + +i. Completion is now case-insensitive by default on MS-DOS. + +j. Fixes to the history file manipulation code for MS-DOS. + +k. Readline attempts to bind the arrow keys to appropriate defaults on MS-DOS. + +l. Some fixes were made to the redisplay code for better operation on MS-DOS. + +m. The quoted-insert code will now insert tty special chars like ^C. + +n. A bug was fixed that caused the display code to reference memory before + the start of the prompt string. + +o. More support for __EMX__ (OS/2). + +p. A bug was fixed in readline's signal handling that could cause infinite + recursion in signal handlers. + +q. A bug was fixed that caused the point to be less than zero when rl_forward + was given a very large numeric argument. + +r. The vi-mode code now gets characters via the application-settable value + of rl_getc_function rather than calling rl_getc directly. + +s. The history file code now uses O_BINARY mode when reading and writing + the history file on cygwin32. + +t. Fixed a bug in the redisplay code for lines with more than 256 line + breaks. + +u. A bug was fixed which caused invisible character markers to not be + stripped from the prompt string if the terminal was in no-echo mode. + +v. Readline no longer tries to get the variables it needs for redisplay + from the termcap entry if the calling application has specified its + own redisplay function. Readline treats the terminal as `dumb' in + this case. + +w. Fixes to the SIGWINCH code so that a multiple-line prompt with escape + sequences is redrawn correctly. + +x. Changes to the install and install-shared targets so that the libraries + and header files are installed separately. + +2. New Features in Readline + +a. A new Readline `user manual' is in doc/rluserman.texinfo. + +b. Parentheses matching is now always compiled into readline, and enabled + or disabled when the value of the `blink-matching-paren' variable is + changed. + +c. MS-DOS systems now use ~/_inputrc as the last-ditch inputrc filename. + +d. MS-DOS systems now use ~/_history as the default history file. + +e. history-search-{forward,backward} now leave the point at the end of the + line when the string to search for is empty, like + {reverse,forward}-search-history. + +f. history-search-{forward,backward} now leave the last history line found + in the readline buffer if the second or subsequent search fails. + +g. New function for use by applications: rl_on_new_line_with_prompt, used + when an application displays the prompt itself before calling readline(). + +h. New variable for use by applications: rl_already_prompted. An application + that displays the prompt itself before calling readline() must set this to + a non-zero value. + +i. A new variable, rl_gnu_readline_p, always 1. The intent is that an + application can verify whether or not it is linked with the `real' + readline library or some substitute. + +j. Per Bothner's `rlfe' (pronounced `Ralphie') readline front-end program + is included in the examples subdirectory, though it is not built + by default. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-4.0, +and the previous version, readline-2.2. + +1. Changes to Readline + +a. The version number is now 4.0, to match the major and minor version + numbers on the shared readline and history libraries. Future + releases will maintain the identical numbering. + +b. Fixed a typo in the `make install' recipe that copied libreadline.a + to libhistory.old right after installing it. + +c. The readline and history info files are now installed out of the source + directory if they are not found in the build directory. + +d. The library no longer exports a function named `savestring' -- backwards + compatibility be damned. + +e. There is no longer any #ifdef SHELL code in the source files. + +f. Some changes were made to the key binding code to fix memory leaks and + better support Win32 systems. + +g. Fixed a silly typo in the paren matching code -- it's microseconds, not + milliseconds. + +h. The readline library should be compilable by C++ compilers. + +i. The readline.h public header file now includes function prototypes for + all readline functions, and some changes were made to fix errors in the + source files uncovered by the use of prototypes. + +j. The maximum numeric argument is now clamped at 1000000. + +k. Fixes to rl_yank_last_arg to make it behave better. + +l. Fixed a bug in the display code that caused core dumps if the prompt + string length exceeded 1024 characters. + +m. The menu completion code was fixed to properly insert a single completion + if there is only one match. + +n. A bug was fixed that caused the display code to improperly display tabs + after newlines. + +o. A fix was made to the completion code in which a typo caused the wrong + value to be passed to the function that computed the longest common + prefix of the list of matches. + +p. The completion code now checks the value of rl_filename_completion_desired, + which is set by application-supplied completion functions to indicate + that filename completion is being performed, to decide whether or not to + call an application-supplied `ignore completions' function. + +q. Code was added to the history library to catch history substitutions + using `&' without a previous history substitution or search having been + performed. + + +2. New Features in Readline + +a. There is a new script, support/shobj-conf, to do system-specific shared + object and library configuration. It generates variables for configure + to substitute into makefiles. The README file provides a detailed + explanation of the shared library creation process. + +b. Shared libraries and objects are now built in the `shlib' subdirectory. + There is a shlib/Makefile.in to control the build process. `make shared' + from the top-level directory is still the right way to build shared + versions of the libraries. + +c. rlconf.h is now installed, so applications can find out which features + have been compiled into the installed readline and history libraries. + +d. rlstdc.h is now an installed header file. + +e. Many changes to the signal handling: + o Readline now catches SIGQUIT and cleans up the tty before returning; + o A new variable, rl_catch_signals, is available to application writers + to indicate to readline whether or not it should install its own + signal handlers for SIGINT, SIGTERM, SIGQUIT, SIGALRM, SIGTSTP, + SIGTTIN, and SIGTTOU; + o A new variable, rl_catch_sigwinch, is available to application + writers to indicate to readline whether or not it should install its + own signal handler for SIGWINCH, which will chain to the calling + applications's SIGWINCH handler, if one is installed; + o There is a new function, rl_free_line_state, for application signal + handlers to call to free up the state associated with the current + line after receiving a signal; + o There is a new function, rl_cleanup_after_signal, to clean up the + display and terminal state after receiving a signal; + o There is a new function, rl_reset_after_signal, to reinitialize the + terminal and display state after an application signal handler + returns and readline continues + +f. There is a new function, rl_resize_terminal, to reset readline's idea of + the screen size after a SIGWINCH. + +g. New public functions: rl_save_prompt and rl_restore_prompt. These were + previously private functions with a `_' prefix. These functions are + used when an application wants to write a message to the `message area' + with rl_message and have the prompt restored correctly when the message + is erased. + +h. New function hook: rl_pre_input_hook, called just before readline starts + reading input, after initialization. + +i. New function hook: rl_display_matches_hook, called when readline would + display the list of completion matches. The new function + rl_display_match_list is what readline uses internally, and is available + for use by application functions called via this hook. + +j. New bindable function, delete-char-or-list, like tcsh. + +k. A new variable, rl_erase_empty_line, which, if set by an application using + readline, will cause readline to erase, prompt and all, lines on which the + only thing typed was a newline. + +l. There is a new script, support/shlib-install, to install and uninstall + the shared readline and history libraries. + +m. A new bindable variable, `isearch-terminators', which is a string + containing the set of characters that should terminate an incremental + search without being executed as a command. + +n. A new bindable function, forward-backward-delete-char. + +------------------------------------------------------------------------------- +This document details the changes between this version, readline-2.2, +and the previous version, readline-2.1. + +1. Changes to Readline + +a. Added a missing `extern' to a declaration in readline.h that kept + readline from compiling cleanly on some systems. + +b. The history file is now opened with mode 0600 when it is written for + better security. + +c. Changes were made to the SIGWINCH handling code so that prompt redisplay + is done better. + +d. ^G now interrupts incremental searches correctly. + +e. A bug that caused a core dump when the set of characters to be quoted + when completing words was empty was fixed. + +f. Fixed a problem in the readline test program rltest.c that caused a core + dump. + +g. The code that handles parser directives in inputrc files now displays + more error messages. + +h. The history expansion code was fixed so that the appearance of the + history comment character at the beginning of a word inhibits history + expansion for that word and the rest of the input line. + +i. The code that prints completion listings now behaves better if one or + more of the filenames contains non-printable characters. + +j. The time delay when showing matching parentheses is now 0.5 seconds. + + +2. New Features in Readline + +a. There is now an option for `iterative' yank-last-arg handline, so a user + can keep entering `M-.', yanking the last argument of successive history + lines. + +b. New variable, `print-completions-horizontally', which causes completion + matches to be displayed across the screen (like `ls -x') rather than up + and down the screen (like `ls'). + +c. New variable, `completion-ignore-case', which causes filename completion + and matching to be performed case-insensitively. + +d. There is a new bindable command, `magic-space', which causes history + expansion to be performed on the current readline buffer and a space to + be inserted into the result. + +e. There is a new bindable command, `menu-complete', which enables tcsh-like + menu completion (successive executions of menu-complete insert a single + completion match, cycling through the list of possible completions). + +f. There is a new bindable command, `paste-from-clipboard', for use on Win32 + systems, to insert the text from the Win32 clipboard into the editing + buffer. + +g. The key sequence translation code now understands printf-style backslash + escape sequences, including \NNN octal escapes. These escape sequences + may be used in key sequence definitions or macro values. + +h. An `$include' inputrc file parser directive has been added. diff --git a/external/gpl3/gdb/dist/readline/COPYING b/external/gpl3/gdb/dist/readline/COPYING new file mode 100644 index 000000000000..1bf152638784 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + Appendix: How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/external/gpl3/gdb/dist/readline/ChangeLog.gdb b/external/gpl3/gdb/dist/readline/ChangeLog.gdb new file mode 100644 index 000000000000..476292511753 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/ChangeLog.gdb @@ -0,0 +1,1408 @@ +2011-06-27 Jan Kratochvil + + Avoid free from a signal handler. + * Makefile.in (xmalloc.o): Add readline.h. + * xmalloc.c: Include readline.h. + (xmalloc, xrealloc): Disable them by #if 0. + (xfree): Return on RL_STATE_SIGHANDLER, #undef free. + * xmalloc.h (xfree, free): New definition. + +2011-03-04 Michael Snyder + + * bind.c (rl_function_dumper): Free allocated memory. + +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + + * configure.in: m4_include toplevel config/override.m4. + * configure: Regenerate. + +2009-07-30 Ralf Wildenhues + + * Makefile.in (datarootdir): New variable. + * doc/Makefile.in (datarootdir): New variable. + * shlib/Makefile.in (datarootdir): New variable. + +2009-04-17 Carlos O'Donell + + * Makefile.in: Add html target. Add dummy install-html and + install-pdf targets. + +2008-08-10 Pedro Alves + + Build fixes for DJGPP. + + * signals.c (rl_set_sighandler): Guard access to SIGWINCH. + * wcwidth.c [__GO32__]: Include wctype.h before wchar.h. + +2008-03-24 Jan Kratochvil + + PR gdb/544 + * rltty.c (block_sigint, release_sigint): Rename to... + (_rl_block_sigint, _rl_release_sigint): ...these and make them global. + * rltty.h (_rl_block_sigint, _rl_release_sigint): New prototypes. + * display.c (rl_redisplay): Wrap the function by the calls to + _RL_BLOCK_SIGINT and _RL_RELEASE_SIGINT. + +2007-09-01 Daniel Jacobowitz + + PR gdb/2138 + From readline 5.2: + * configure.in (CROSS_COMPILE): Initialize to empty. + * configure: Regenerated. + +2007-03-27 Brooks Moses + + * Makefile.in: Add dummy "pdf" target. + +2006-11-13 Denis Pilat + + * terminal.c (_rl_get_screen_size): use wr and wc variable to store + window size. + +2006-10-21 Ulrich Weigand + + * callback.c: Include "xmalloc.h". + * Makefile.in: Add dependency. + +2006-04-24 Daniel Jacobowitz + + Imported readline 5.1, and upstream patches 001-004. + +2006-03-21 Denis Pilat + + * histfile.c (read_history_range): Remove '\r' character from + history lines. + +2005-02-10 Denis Pilat + + * readline/terminal.c (_rl_get_screen_size): Get console size from + the Windows API when compiling with MinGW. + +2005-07-25 Mark Mitchell + + * input.c (rl_getc): Use getch to read console input on + Windows. + * readline.c (bind_arrow_keys_internal): Translate + Windows keysequences into ANSI key sequences. + * rldefs.h (NO_TTY_DRIVER): Define on MinGW. + * rltty.c: Conditionalize on NO_TTY_DRIVER throughout. + +2005-07-03 Mark Kettenis + + From Martin Simmons: + * configure.in: Check for getpwnam instead of getpwname. + * configure: Regenerate. + +2005-05-09 Mark Mitchell + + * aclocal.m4: Use AC_TRY_LINK to check for mbstate_t. + * complete.c (pwd.h): Guard with HAVE_PWD_H. + (getpwent): Guard with HAVE_GETPWENT. + (rl_username_completion_function): Guard use of getpwent. + (endpwent): Likewise. + * config.h.in (HAVE_FCNTL): New macro. + (HAVE_GETPWENT): Likewise. + (HAVE_GETPWNAM): Likewise. + (HAVE_GETPWUID): Likewise. + (HAVE_KILL): Likewise. + (HAVE_PWD_H): Likewise. + * configure: Regenerated. + * configure.in: Handle MinGW when cross compiling. Check for + getpwnam, getpwent, getpwuid, kill, and pwd.h. + * display.c (rl_clear_screen): Treat Windows like DOS. + (insert_some_chars): Likewise. + (delete_chars): Likewise. + * shell.c (pwd.h): Guard with HAVE_PWD_H. + (getpwuid): Guard with HAVE_GETPWUID. + (sh_unset_nodelay_mode): Guard use of fnctl with HAVE_FNCTL_H. + * signals.c (rl_signal_handler): Don't use SIGALRM or + SIGQUIT if not defined. Use "raise" if "kill" is not available. + (rl_set_signals): Don't set handlers for SIGQUIT or SIGALRM if + they are not defined. + (rl_clear_signals): Likewise. + * tilde.c (pwd.h): Guard with HAVE_PWD_H. + (getpwuid): Guard declaration with HAVE_GETPWUID. + (getpwnam): Guard declaration with HAVE_GETPWNAM. + (tilde_expand_word): Guard use of getpwnam with HAVE_GETPWNAM. + +2004-02-19 Andrew Cagney + + * config.guess: Update from version 2003-06-12 to 2004-02-16. + * config.sub: Update from version 2003-06-13 to 2004-02-16. + +2004-01-27 Elena Zannoni + + Merge in official patches to readline-4.3 from + ftp://ftp.cwru.edu/pub/bash/readline-4.3-patches: + NOTE: Patch-ID readline-43-004 was already applied (see below). + + * bind.c (rl_generic_bind): Pressing certain key sequences + causes an infinite loop in _rl_dispatch_subseq with the `key' argument + set to 256. This eventually causes bash to exceed the stack size + limit and crash with a segmentation violation. + Patch-ID: readline43-001. + + * readline.c (_rl_dispatch_subseq): Repeating an edit in + vi-mode with `.' does not work. + Patch-ID: readline43-002. + + * mbutil.c (_rl_get_char_len, _rl_compare_chars, + _rl_adjust_point): When in a locale with multibyte characters, the + readline display updater will occasionally cause a + segmentation fault when attempting to compute the length of the first + multibyte character on the line. + Patch-ID: readline43-003. + + * vi_mode.c (_rl_vi_change_mbchar_case): Using the vi editing + mode's case-changing commands in a locale with multibyte characters + will cause garbage characters to be inserted into the editing buffer. + Patch-ID: readline43-005. + +2003-12-28 Eli Zaretskii + + * readline.c (rl_save_state, rl_restore_state): Support systems + that don't define SIGWINCH. + +2003-12-25 Eli Zaretskii + + * terminal.c (_rl_get_screen_size) [__DJGPP__]: Compute the + screen width and height using console I/O. + (_rl_init_terminal_io) [__MSDOS__]: Zero out all the _rl_term_* + variables. Convert to _rl_* naming scheme. + (_rl_set_cursor) [__MSDOS__]: Ifdef away this function. + +2003-12-23 Eli Zaretskii + + * display.c (_rl_move_vert) [__MSDOS__]: Don't use undeclared + variable `l'. Use `delta' instead recomputing its value anew. + Assign -delta to i instead of the other way around. + +2003-12-11 Michael Chastain + + * rlmbutil.h: Require HAVE_MBSTATE_T for HANDLE_MULTIBYTE. + Revert requirement of HAVE_MBRTOWC. Delete macro definitions + that attempted to fake mbstate_t if HAVE_MBSRTOCWS is defined + and HAVE_MBSTATE_T is not defined. + +2003-06-14 H.J. Lu + + * support/config.guess: Update to 2003-06-12 version. + * support/config.sub: Update to 2003-06-13 version. + +2003-05-25 Mark Kettenis + + * aclocal.m4: Don't add wcwidth.o if we don't have wchar.h. + * configure: Regenerate. + +2003-05-13 Andreas Jaeger + + * support/config.guess: Update to 2003-05-09 version. + * support/config.sub: Update to 2003-05-09 version. + +2003-03-03 Joel Brobecker + + * aclocal.m4: Add check for mbrtowc. + * config.h.in: Regenerate. + * configure: Regenerate. + * rlmbutil.h: Disable multi-byte if mbrtowc is not defined. + +2003-03-03 Kris Warkentin + + * aclocal.m4: Cause wcwidth check to substitute + HAVE_WCWIDTH for building. + * Makefile.in: Add wcwidth object to lib if required. + * shlib/Makefile.in: Likewise. + * configure: Regenerate. + +2003-01-09 Michael Chastain + + From Chet Ramey, , the readline maintainer: + ftp://ftp.cwru.edu/pub/bash/readline-4.3-patches/readline43-004 + + * display.c: Fix perverse screen refresh with UTF-8. + When running in a locale with multibyte characters, the + readline display updater will use carriage returns when + drawing the line, overwriting any partial output already on + the screen and not terminated by a newline. + Patch-ID: readline43-004 + +2003-01-08 Chris Demetriou + + * config.guess: Update to 2003-01-03 version. + * config.sub: Update to 2003-01-03 version. + +2002-12-16 Christopher Faylor + + * configure.in: Remove --enable-shared option. It shouldn't be used + for gdb. + * configure: Regenerate. + +2002-12-16 Christopher Faylor + + * config/cygwin.cache: Prime mbstate_t. + +2002-12-06 Elena Zannoni + + Import of readline 4.3. NB: This import includes those gdb + local changes that aren't in the official readline sources. + + * compat.c, mbutil.c, misc.c, rlmbutil.h, rltypedefs.h, + text.c, doc/history.0, doc/history.3, support/wcwidth.c, + examples/readlinebuf.h, examples/rlcat.c: New files. + + * CHANGELOG, CHANGES, INSTALL, MANIFEST, Makefile.in, README, + aclocal.m4, ansi_stdlib.h, bind.c, callback.c, chardefs.h, + complete.c, config.h.in, configure, configure.in, display.c, + emacs_keymap.c, funmap.c, histexpand.c, histfile.c, histlib.h, + history.c, history.h, histsearch.c, input.c, isearch.c, + keymaps.c, keymaps.h, kill.c, macro.c, nls.c, parens.c, + posixdir.h, readline.c, readline.h, rlconf.h, rldefs.h, + rlprivate.h, rlshell.h, rlstdc.h, rltty.c, savestring.c, + search.c, shell.c, signals.c, terminal.c, tilde.c, tilde.h, + undo.c, util.c, vi_keymap.c, vi_mode.c, xmalloc.c, xmalloc.h, + doc/Makefile.in, doc/hist.texinfo, doc/hstech.texinfo, + doc/hsuser.texinfo, doc/manvers.texinfo, doc/readline.3, + doc/rlman.texinfo, doc/rltech.texinfo, doc/rluser.texinfo + doc/rluserman.texinfo, doc/texi2dvi, doc/texi2html, + shlib/Makefile.in, support/install.sh, support/mkdirs, + support/mkdist, support/shlib-install, support/shobj-conf, + examples/Inputrc, examples/Makefile.in, examples/fileman.c, + examples/histexamp.c, examples/manexamp.c, examples/rl.c, + examples/rlfe.c, examples/rltest.c, examples/rlversion.c: + Modified files. + +2002-08-23 Andrew Cagney + + * support/config.guess: Import version 2002-08-23. + * support/config.sub: Import version 2002-08-22. + +2002-07-19 Chris Demetriou + + * support/config.guess: Update from ../config.guess. + * support/config.sub: Update from ../config.sub. + +2002-02-24 Elena Zannoni + + * ChangeLog.gdb: Renamed from ChangeLog.Cygnus. + +2002-02-24 Daniel Jacobowitz + + * support/config.guess: Import from master sources, rev 1.232. + * support/config.sub: Import from master sources, rev 1.246. + +2002-02-01 Ben Elliston + + * config.guess: Import from master sources, rev 1.229. + * config.sub: Import from master sources, rev 1.240. + +2002-01-17 H.J. Lu (hjl@gnu.org) + + * support/config.guess: Import from master sources, rev 1.225. + * support/config.sub: Import from master sources, rev 1.238. + +2001-07-20 Andrew Cagney + + * support/config.guess: Update using ../config.sub. + +2001-07-16 Andrew Cagney + + * support/config.sub: Update using ../config.sub. + +2001-06-15 Elena Zannoni + + * configure.in: Add -fsigned-char to LOCAL_CFLAGS for Linux + running on the IBM S/390. + * configure: Ditto. + +2001-01-07 Michael Sokolov + + * rltty.c (save_tty_chars): Fix compilation-stopping typo. + +2000-07-10 Eli Zaretskii + + * terminal.c (_rl_get_screen_size) [__DJGPP__]: Determine screen + size via DJGPP-specific calls. + (_rl_init_terminal_io) [__MSDOS__]: DJGPP-specific terminal + initialization. + (_rl_backspace) [__MSDOS__]: Don't call tputs. + (ding) [__MSDOS__]: Use DJGPP-specific calls to support visible + bell. + + * display.c (_rl_move_vert) [__MSDOS__]: Support cursor movement + upwards with DJGPP-specific calls. + (_rl_clear_to_eol) [__MSDOS__]: Don't call tputs. + (_rl_clear_screen) [__MSDOS__]: Support clear-screen with + DJGPP-specific calls. + (insert_some_chars) [__MSDOS__]: Don't call tputs. + (delete_chars) [__MSDOS__]: Don't call tputs. + +2000-07-08 Elena Zannoni + + * readline/readline.h: Ifdef out the export of savestring(). + It should not have been in the distribution. + +2000-07-07 Elena Zannoni + + * Import of readline 4.1. + + Locally modified files: Makefile.in, configure.in, configure + (regenerated), config.h.in (regenerated), rltty.c, + shell.c signals.c. + + Locally added files: acconfig.h, config/*, config.h.bot, + cross-build/*, doc/inc-hit.texinfo. + + New files: USAGE, rlprivate.h, rlshell.h, xmalloc.h. + +2000-03-16 Eli Zaretskii + + * support/shobj-conf: Shared libs are unsupported on MSDOS. + + * bind.c (_rl_read_file): Open files in binary mode. Strip CR + characters after reading the file. + (rl_re_read_init_file, rl_read_init_file): Allow for _inputrc on + DOS. + + * complete.c (username_completion_function): Don't bypass getpw* + function calls for DJGPP. + (Filename_completion_function): Handle d:foo/bar file names. + + * display.c (_rl_move_vert) [__GO32__]: fflush the stream, to make + sure cursor position is up to date. + (_rl_clear_screen) [__GO32__]: Clear screen and home the cursor. + (insert_some_characters, delete_characters) [__DJGPP__]: Don't use + memcpy. + + * histfile.c (read_history_range, history_truncate_file) + (history_do_write) [__MSDOS__]: Allow for underscore instead of + the leading dot in file names. + + * input.c: Don't use GO32-specific workarounds if HAVE_SELECT or + HAVE_TERMIOS_H are defined. + + * readline.c: Don't disable signals if __DJGPP__ is defined. + + * rltty.c: Don't disable signals and don't bypass termios code for + DJGPP (if HAVE_TERMIOS_H is defined). + + * signals.c: Don't disable signals for DJGPP. + + * terminal.c (_rl_get_screen_size) [__DJGPP__]: Initialize screen + dimensions. + (ding) [__DJGPP__]: Support visual bell. + +1999-08-13 Elena Zannoni + + From Philippe De Muyter + * shell.c (stdio.h): File included, for definition of NULL. + * readline/rltty.c (get_tty_settings): Conditionalize + call to set_winsize on TIOGWINSZ. + +1999-07-30 Elena Zannoni + + * Imported Readline 4.0. Integrated all the Cygnus + local changes since last import. + + New files: rlstdc.h, savestring.c, shlib directory, + doc/manvers.texinfo, examples/rlversion.c, + support/install-shlib, support/shobj-conf. + + Removed files: MANIFEST.doc, doc/inc-hist.texi. + +1999-07-13 Elena Zannoni + + * acconfig.h: Fix typo: it's GWINSZ_IN_SYS_IOCTL, not + TIOCGWINSZ_IN_SYS_IOCTL. + + * config.h.in: Regenerate with autoheader. + +1999-04-27 Elena Zannoni + + * ChangeLog.Cygnus: new file. It is the old Changelog. + * ChangeLog: removed. It was conflicting with CHANGELOG + on Windows. + +1999-04-22 Jason Molenda (jsm@bugshack.cygnus.com) + + * Makefile.in (install): Make comment about this change more explicit. + +1999-04-22 Jason Molenda (jsm@bugshack.cygnus.com) + + * Makefile.in (install): Don't install the final libreadline.a + or .h files. + +Tue Mar 23 10:56:08 1999 Elena Zannoni + + Patches from Robert Hoehne : + + * display.c: Change some terminal calls to work on DJGPP. + * terminal.c: Likewise. + * Makefile.in: Remove . from the VPATH directive. + +Tue Mar 9 14:58:13 1999 Geoffrey Noer + + * support/config.sub: Recognize cygwin*, not just cygwin32. + +Tue Feb 9 10:38:57 1999 Elena Zannoni + + * configure.in: Do not use the ./support directory. + * configure: Regenerate. + +Wed Jan 6 12:24:19 1999 Christopher Faylor + + * configure.in: Use LOCAL_CFLAGS rather than CFLAGS for + searching libtermcap directory. + * configure: Regenerate. + +Thu Dec 31 12:07:01 1998 Christopher Faylor + + * configure.in: Search devo libtermcap directory for termcap.h + when compiling for cygwin. + * configure: Regenerated. + +1998-12-30 Michael Meissner + + * Makefile.in (install): Only try to copy libreadline.a and + libhistory.a if they exist. + +Tue Dec 29 23:49:20 1998 Christopher Faylor + + * cross-build/cygwin.cache: Add a couple more known settings. + * configure.in: Fix typo. + * configure: Regenerated. + +Tue Dec 29 18:11:28 1998 Elena Zannoni + + * cross-build: new directory. + + * cross-build/cygwin.cache: new file. Used for Cygwin cross builds. + + * configure.in: added tests for cross-build for Cygwin. + +1998-12-24 Jason Molenda (jsm@bugshack.cygnus.com) + + * Makefile.in: Add CYGNUS LOCAL comment. + * acconfig.h: Add missing defines. + * config.h.bot: Add missing content. + * configure, config.h.in: Regenerated. + +Wed Dec 23 16:21:41 1998 Elena Zannoni + + * Makefile.in: comment out the rule to rebuild configure by + running autoconf. + +Tue Dec 22 10:00:30 1998 Elena Zannoni + + * shell.c (savestring): ifdef'd it out. + + * Imported new version of Readline 2.2.1. Removed all the Cygnus + local changes. + + New files: acconfig.h, aclocal.m4, ansi_stdlib.h, callback.c, + config.h.in, configure, histexpand.c, histfile.c, histlib.h, + histsearch.c, input.c, kill.c, macro.c, nls.c, posixdir.h, + posixjmp.h, posixstat.h, rlconf.h, rltty.h, rlwinsize.h, shell.c, + tcap.h, terminal.c, undo.c, util.c, support directory. + + Removed files: sysdep*, config directory. + + +Fri Dec 4 15:25:41 1998 David Taylor + + The following changes were made by Jim Blandy + and David Taylor + as part of a project to merge in changes + made by HP; HP did not create ChangeLog entries. + + * config/mp-enable-tui: New file. + (TUI_CFLAGS): Search devo's include directory, as long as we're + totally ruining modularity. + (INCLUDE_SRCDIR): New var. + (GDB_TUI_SRCDIR): Fix syntax error. + + * configure.in: Check the --enable-tui flag; if it's set, include + a makefile fragment that #defines TUI and adds the needed #include + directories. + (*-*-hpux*): New host; use sysdep-hpux.h. + + * Makefile.in (.c.o): Check the variable set in the makefile + fragment above. + + * display.c (term_goto): declare it. + (insert_some_chars): set it. + (delete_chars): set it. + + * readline.c: add tui include files surrounded by TUI. + (rl_reset): new function, move some of rl_abort functionality to + here. + (rl_abort): call rl_reset. + (rl_getc): tui changes. + (init_terminal_io): tui changes. + + * readline.h (tui_version, fputc_unfiltered, fputs_unfiltered, + tui_tputs): declare if TUI is defined. + + * rltty.c (prepare_terminal_settings): additional comment. + + * signals.c: add tui include files surrounded by TUI. move #if + and #endif to column 1 so HP's compiler will accept them. Remove + declaration of tuiDoAndReturnToTop since it's declared in tui.h. + (rl_handle_sigwinch): call tuiDoAndReturnToTop if TUI defined. + (rl_handle_sigwinch_on_clear): define if TUI defined. + (rl_set_signals): if TUI, avoid infinite recursion. + (rl_clear_signals): install rl_handle_sigwinch_on_clear. + + * sysdep-hpux.h: New file. + +Mon Nov 2 15:26:33 1998 Geoffrey Noer + + * configure.in: Check cygwin* instead of cygwin32*. + +Tue Jul 28 09:43:27 1998 Jeffrey A Law (law@cygnus.com) + + * sysdep-hpux11.h: New file. + * configure.in (*-*-*-hpux11*): Use sysdep-hpux11.h. + +Thu Jul 23 17:48:21 1998 Ian Lance Taylor + + * configure.bat: Remove obsolete file. + * examples/configure.bat: Remove obsolete file. + +Wed May 13 13:41:53 1998 Ian Lance Taylor + + * sysdep-6irix.h: New file. + * configure.in (*-*-irix6*): New host; use sysdep-6irix.h. + + * Makefile.in (isearch.o, search.o): Depend upon sysdep.h. + (Makefile): Depend upon $(srcdir)/configure.in. + +Thu Apr 9 11:59:38 1998 Ian Dall ( + + * configure.in (host==netbsd): Include config/mh-bsd44. + * config/mh-bsd44: New file. + +Wed Dec 3 16:48:20 1997 Michael Snyder (msnyder@cleaver.cygnus.com) + + * rltty.c: fix typos. + +Tue Oct 8 08:59:24 1996 Stu Grossman (grossman@critters.cygnus.com) + + * tilde.c (tilde_word_expand): __MSDOS___ -> __MSDOS__ + +Sat Oct 05 11:24:34 1996 Mark Alexander + + * rldefs.h: On Linux, include to fix compile error + in . + +Wed Sep 4 18:06:51 1996 Stu Grossman (grossman@critters.cygnus.com) + + * rldefs.h: Enable HANDLE_SIGNALS for cygwin32. + +Thu Aug 29 16:59:45 1996 Michael Meissner + + * configure.in (i[345]86-*-*): Recognize i686 for pentium pro. + +Fri Aug 16 17:49:57 1996 Stu Grossman (grossman@critters.cygnus.com) + + * complete.c: Include if not DOS, and if cygwin32 or not + win32. + * configure.in: Add test for *-*-cygwin32* to use config/mh-posix. + * readline.c: Move decl of tgetstr to rldefs.h. + * (_rl_set_screen_size): Remove redundant ifdef MINIMALs. + * rldefs.h: Don't do MINIMAL for cygwin32. Cygwin32 now uses + full-blown readline, except for termcap. + +Sun Aug 11 21:06:26 1996 Stu Grossman (grossman@critters.cygnus.com) + + * rldefs.c: Get rid of define of SIGALRM if _WIN32 or __MSDOS__. + * Don't define ScreenCols/ScreenRows/... if cygwin32. + * sysdep-norm.h: Don't include if cygwin32. + +Sun Aug 11 14:59:09 1996 Fred Fish + + * rldefs.h: If __osf__is defined, include instead of + . + +Fri Aug 9 08:54:26 1996 Stu Grossman (grossman@critters.cygnus.com) + + * bind.c complete.c history.c readline.c: Don't include sys/file.h. + * complete.c display.c parens.c readline.c rldefs.h rltty.c + signals.c tilde.c: Change refs to _MSC_VER and __WIN32__ to _WIN32. + * signals.c (rl_signal_handler): Ifdef out kill if _WIN32. + * sysdep-norm.h: Ifdef out include of dirent.h if _WIN32. + Include malloc.h if _WIN32. + +Thu Jul 18 15:59:35 1996 Michael Meissner + + * rldefs.h (sys/uio.h) Before sys/stream.h is included under AIX, + include sys/uio.h, which prevents an undefined structure used in a + prototype message from being generated. + +Tue Jun 25 23:05:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (datadir): Set to $(prefix)/share. + (docdir): Removed. + +Sun May 26 15:14:42 1996 Fred Fish + + From: David Mosberger-Tang + + * sysdep-linux.h: New file. + * display.c: Add include of "sysdep.h" to get HAVE_VARARGS_H. + * configure.in: Change pattern i[345]86-*-linux* into *-*-linux* to + support non-x86 based Linux platforms. + +Sun Apr 7 22:06:11 1996 Fred Fish + + From: Miles Bader + * config/mh-gnu: New file. + * configure.in (*-*-gnu*): New host. + +Sun Apr 7 13:21:51 1996 Fred Fish + + From: Robert Lipe + * configure.in: SCO OpenServer 5 (a.k.a 3.2v5*) is more like + SCO 3.2v4 than 3.2v2. + +Wed Jan 3 18:22:10 1996 steve chamberlain + + * readline.c, display.c, complete.c: Add _MSC_VER to list of + things which can't do most things. + +Thu Nov 16 15:39:05 1995 Geoffrey Noer + + * complete.c: Change WIN32 to __WIN32__, added #else return NULL + to end of that define. + +Tue Oct 31 10:38:58 1995 steve chamberlain + + * display.c, parens.c, readline.c, rldefs.h: Change use of + WIN32 to __WIN32__. + +Tue Oct 10 11:07:23 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + +Tue Oct 10 08:49:00 1995 steve chamberlain + + * complete.c (filename_completion_function): Enable for + win32 when not MSC. + +Sun Oct 8 04:17:19 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * configure.in: Handle powerpc-ibm-aix* like rs6000-ibm-aix*. + +Sat Oct 7 20:36:16 1995 Michael Meissner + + * rltty.c (outchar): Return an int, like tputs expects. + * signals.c (_rl_output_character_function): Ditto. + +Fri Sep 29 15:19:23 1995 steve chamberlain + + Fixes for when the host WIN32, but not MSC. + * complete.c: Sometimes have pwd.h + * parens.c: WIN32 has similar restrictions to __GO32__. + * readline.c (__GO32__): Some of this moved into rldefs.h + * signals.c (__GO32__): Likewise. + * rldefs.h (MSDOS||WIN32) becomes MSDOS||MSC. + (WIN32&&!WIN32): New definitions. + +Wed Sep 20 12:57:17 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Wed Mar 1 13:33:43 1995 Michael Meissner + + * rltty.c (outchar): Provide prototype for outchar, to silence + type warnings in passing outchar to tputs on systems like Linux + that have full prototypes. + + * signals.c (_rl_output_character_function): Provide prototype to + silence type warnings. + +Sun Jan 15 14:10:37 1995 Steve Chamberlain + + * rldefs.h: Define MINIMAL for __GO32__ and WIN32. + * complete.c, display.c, readline.c, rltty.c: Test MINIMAL + instead of __GO32__. + +Wed Aug 24 13:04:47 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * configure.in: Change i[34]86 to i[345]86. + +Sat Jul 16 13:26:31 1994 Stan Shebs (shebs@andros.cygnus.com) + + * configure.in (m88*-harris-cxux7*): Recognize. + * sysdep-cxux7.h: New file. + +Fri Jul 8 13:18:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * rttty.c (control_meta_key_on): Remove superfluous testing of + __GO32__. + +Thu Jun 30 15:21:54 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * rltty.c (control_meta_key_on): Don't compile if __GO32__ is + defined. + (rltty_set_default_bindings): Likewise. + * display.c (insert_some_chars, delete_chars): row_start should be + a short. + * parens.c (rl_insert_close): No FD_SET if using __GO32__. + * readline.c (rl_gather_tyi): Strip off spurious high bits. + +Sun Jun 12 03:51:52 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * history.c: Swap inclusion of rldefs.h and chardefs.h to avoid + CTRL macro redefinition. + +Mon May 9 18:29:42 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * readline.c (readline_default_bindings): Don't compile if + __GO32__ is defined. + (_rl_set_screen_size): Likewise. + * rltty.c (rltty_set_default_bindings): Likewise. + (control_meta_key): Likewise. + * display.c: If __GO32__ is defined, include . + * parens.c: If __GO32__ is defined, undefine FD_SET. + * signals.c: Include SIGWINCH handling in the set of things which + is not done if HANDLE_SIGNALS is not set. + +Fri May 6 13:38:39 1994 Steve Chamberlain (sac@cygnus.com) + + * config/mh-go32: New fragment. + * configure.in (host==go32): Use go32 fragment. + +Wed May 4 14:36:53 1994 Stu Grossman (grossman@cygnus.com) + + * chardefs.h, rldefs.h: Move decls of string funcs from chardefs.h + to rldefs.h so that they don't pollute apps that include + readline.h. + * history.c: include rldefs.h to get decls of string funcs. + +Wed May 4 12:15:11 1994 Stan Shebs (shebs@andros.cygnus.com) + + * configure.in (rs6000-bull-bosx*): New configuration, RS/6000 + variant. + +Wed Apr 20 10:43:52 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * configure.in: Use mh-posix for sunos4.1*. + +Wed Apr 13 21:28:44 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * rltty.c (set_tty_settings): Don't set readline_echoing_p. + (rl_deprep_terminal) [NEW_TTY_DRIVER]: Set readline_echoing_p. + +Sun Mar 13 09:13:12 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add TAGS target. + +Wed Mar 9 18:01:31 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * isearch.c, search.c: Include sysdep.h. + +Thu Mar 3 17:40:03 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * configure.in: For ISC, use mh-sysv, not mh-isc. + +Thu Feb 24 04:13:53 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * Merge in changes from bash-1.13.5. Merge changes from glob/tilde.c + into tilde.c and use it. Add system function declarations where + necessary. Check for __GO32__, not _GO32_ consistently. + * Makefile.in: Update dependencies. + * rltty.c: Include to match include file setup + in readline.c for rldefs.h. Otherwise we get inconsistent + TTY_DRIVER definitions in readline.c and rltty.c. + * bind.c, complete.c: Do not include , it is already + included via sysdep.h, which causes problems if has + no multiple inclusion protection. + * readline.c (_rl_set_screen_size): Reestablish test for + TIOCGWINSZ_BROKEN. + * rldefs.h: Define S_ISREG if necessary. + +Fri Feb 18 08:56:35 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add search.o rule for Sun make. + +Wed Feb 16 16:35:49 1994 Per Bothner (bothner@kalessin.cygnus.com) + + * rltty.c: #if out some code if __GO32__. + +Tue Feb 15 14:07:08 1994 Per Bothner (bothner@kalessin.cygnus.com) + + * readline.c (_rl_output_character_function), display.c: + Return int, not void, to conform with the expected arg of tputs. + * readline.c (init_terminal_io): tgetflag only takes 1 arg. + * readline.c (_rl_savestring): New function. + * chardefs.h: To avoid conflicts and/or warnings, define + savestring as a macro wrapper for _rl_savestring. + * display.c (extern term_xn): It's an int flag, not a string. + * charsdefs.h, rldefs.h: Remove HAVE_STRING_H-related junk. + +Sat Feb 5 08:32:30 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Remove obsolete rules for history.info and + readline.info. + +Thu Jan 27 17:04:01 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * chardefs.h: Only declare strrchr if it is not #define'd. + +Tue Jan 25 11:30:06 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * rldefs.h: Accept __hpux as well as hpux for HP compiler in ANSI mode. + +Fri Jan 21 17:31:26 1994 Jim Kingdon (kingdon@lisa.cygnus.com) + + * chardefs.h, tilde.c: Just declare strrchr rather than trying to + include a system header. + +Fri Jan 21 14:40:43 1994 Fred Fish (fnf@cygnus.com) + + * Makefile.in (distclean, realclean): Expand local-distclean + inline after doing recursion. You can't recurse after removing + Makefile. Make them depend on local-clean. + * Makefile.in (local-distclean): Remove now superfluous target. + +Mon Jan 17 12:42:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * readline.c (doing_an_undo): Delete second declaration, since it + confuses the alpha-osf1 native compiler. + +Sun Jan 16 12:33:11 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * complete.c, bind.c: Include . + * complete.c: Define X_OK if not defined by a system header. + + * chardefs.h: Don't declare xmalloc. + + * keymaps.h: Include "chardefs.h" not . + + * Makefile.in (clean mostlyclean distclean realclean): Recurse + into subdirectories as well as doing this directory. Add clean-dvi + target. + +Sat Jan 15 19:36:12 1994 Per Bothner (bothner@kalessin.cygnus.com) + + * readline.c, display.c: Patches to allow use of all 80 + columns on most terminals (those with am and xn). + + Merge in changes from bash-1.13. The most obvious one is + that the file readline.c has been split into multiple files. + * bind.c, complete.c, dispay.c, isearch.c, parens.c, rldefs.h, + rltty.c, search.c signals.c, tilde.c, tilde.h, xmalloc.c: New files. + +Sat Dec 11 16:29:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * readline.c (rl_getc): If GO32, trim high bit from getkey, + otherwise fancy PC keys cause grief. + +Fri Nov 5 11:49:47 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * configure.in: Add doc to configdirs. + * Makefile.in (info dvi install-info clean-info): Recurse into doc. + +Fri Oct 22 07:55:08 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * configure.in: Add * to end of all OS names. + +Tue Oct 5 12:33:51 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * readline.c: Add stuff for HIUX to place where we detect termio + vs. sgtty (ugh, but I don't see a simple better way). + +Wed Sep 29 11:02:58 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * readline.c (parser_if): Free tname when done with it (change + imported from from bash 1.12 readline). + +Tue Sep 7 17:15:37 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * configure.in (m88k-*-sysvr4*): Comment out previous change. + +Fri Jul 2 11:05:34 1993 Ian Lance Taylor (ian@cygnus.com) + + * configure.in (*-*-riscos*): New entry; use mh-sysv. + +Wed Jun 23 13:00:12 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * configure.in: Add comment. + +Mon Jun 14 14:28:55 1993 Jim Kingdon (kingdon@eric) + + * configure.in (m88k-*-sysvr4*): Use sysdep-norm.h. + +Sun Jun 13 13:04:09 1993 Jim Kingdon (kingdon@cygnus.com) + + * Makefile.in ({real,dist}clean): Remove sysdep.h. + +Thu Jun 10 11:22:41 1993 Jim Kingdon (kingdon@cygnus.com) + + * Makefile.in: Add mostlyclean, distclean, and realclean targets. + +Fri May 21 17:09:28 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * config/mh-isc: New file. + * configure.in: Use it. + +Sat Apr 17 00:40:12 1993 Jim Kingdon (kingdon at calvin) + + * readline.c, history.c: Don't include sys/types.h; sysdep.h does. + + * config/mh-sysv: Define TIOCGWINSZ_BROKEN. + readline.c: Check it. + +Wed Mar 24 02:06:15 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: add installcheck & dvi targets + +Fri Mar 12 18:36:53 1993 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: recognize *-*-solaris2* instead of *-*-solaris* (a + number of people want to call SunOS 4.1.2 "solaris1.0" + and get it right) + +Tue Mar 2 21:25:36 1993 Fred Fish (fnf@cygnus.com) + + * sysdep-sysv4.h: New file for SVR4. + * configure.in (*-*-sysv4*): Use sysdep-sysv4.h. + + * configure.in (*-*-ultrix2): Add triplet from Michael Rendell + (michael@mercury.cs.mun.ca) + +Tue Dec 15 12:38:16 1992 Ian Lance Taylor (ian@cygnus.com) + + * configure.in (i[34]86-*-sco3.2v4*): use mh-sco4. + * config/mh-sco4: New file, like mh-sco but without defining + _POSIX_SOURCE. + +Wed Nov 11 21:20:14 1992 John Gilmore (gnu@cygnus.com) + + * configure.in: Reformat to one-case-per-line. + Handle SunOS 3.5, as per Karl Berry, . + +Wed Nov 4 15:32:31 1992 Stu Grossman (grossman at cygnus.com) + + * sysdep-norm.h: Remove some crud, install dire warning. + +Thu Oct 22 01:08:13 1992 Stu Grossman (grossman at cygnus.com) + + * configure.in: Make SCO work again... + +Mon Oct 12 15:04:07 1992 Ian Lance Taylor (ian@cygnus.com) + + * readline.c (init_terminal_io): if tgetent returns 0, the + terminal type is unknown. + +Thu Oct 1 23:44:14 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use cpu-vendor-os triple instead of nested cases + +Wed Sep 30 12:58:57 1992 Stu Grossman (grossman at cygnus.com) + + * readline.c (rl_complete_internal): Cast alloca to (char *) to + avoid warning. + +Fri Sep 25 12:45:05 1992 Stu Grossman (grossman at cygnus.com) + + * readline.c (clear_to_eol, rl_generic_bind): Make static. + (rl_digit_loop): Add arg to call to rl_message(). + * vi_mode.c (rl_vi_first_print): Add arg to call to + rl_back_to_indent(). + +Wed Aug 19 14:59:07 1992 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in: always create installation directories, use full + file name for install target. + +Wed Aug 12 15:50:57 1992 John Gilmore (gnu@cygnus.com) + + * readline.c (last_readline_init_file): Fix typo made by Steve + Chamberlain/DJ Delorie. Proper control file name is ~/.inputrc, + not ~/inputrc. + +Thu Jun 25 16:15:27 1992 Stu Grossman (grossman at cygnus.com) + + * configure.in: Make bsd based systems use sysdep-obsd.h. + +Tue Jun 23 23:22:53 1992 Per Bothner (bothner@cygnus.com) + + * config/mh-posix: New file, for Posix-compliant systems. + * configure.in: Use mh-posix for Linux (free Unix clone). + +Tue Jun 23 21:59:20 1992 Fred Fish (fnf@cygnus.com) + + * sysdep-norm.h (alloca): Protect against previous definition as + a macro with arguments. + +Fri Jun 19 15:48:54 1992 Stu Grossman (grossman at cygnus.com) + + * sysdep-obsd.h: #include to make this more Kosher. + +Fri Jun 19 12:53:28 1992 John Gilmore (gnu at cygnus.com) + + * config/mh-apollo68v, mh-sco, mh-sysv, mh-sysv4}: RANLIB=true. + +Mon Jun 15 13:50:34 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * configure.in: use mh-sysv4 on solaris2 + +Mon Jun 15 12:28:24 1992 Fred Fish (fnf@cygnus.com) + + * config/mh-ncr3000 (INSTALL): Don't use /usr/ucb/install, + it is broken on ncr 3000's. + * config/mh-ncr3000 (RANLIB): Use RANLIB=true. + +Mon Jun 15 01:35:55 1992 John Gilmore (gnu at cygnus.com) + + * readline.c: Make new SIGNALS_* macros to parameterize the + ugly changes in signal blocking. Use them throughout, + reducing #ifdef HAVE_POSIX_SIGNALS and HAVE_BSD_SIGNALS clutter + significantly. Make all such places use POSIX if available, + to avoid losing with poor `sigsetmask' emulation from libiberty. + +Sun Jun 14 15:19:51 1992 Stu Grossman (grossman at cygnus.com) + + * readline.c (insert_some_chars): Return void. + +Thu Jun 11 01:27:45 1992 John Gilmore (gnu at cygnus.com) + + * readline.c: #undef PC, which Solaris2 defines in sys/types.h, + clobbering the termcap global variable PC. + +Tue Jun 9 17:30:23 1992 Fred Fish (fnf@cygnus.com) + + * config/{mh-ncr3000, mh-sysv4}: Change INSTALL to use + /usr/ucb/install. + +Mon Jun 8 23:10:07 1992 Fred Fish (fnf@cygnus.com) + + * readline.h (rl_completer_quote_characters): Add declaration. + * readline.c (rl_completer_quote_characters): Add global var. + * readline.c (strpbrk): Add prototype and function. + * readline.c (rl_complete_internal): Add code to handle + expansion of quoted strings. + +Mon May 11 12:39:30 1992 John Gilmore (gnu at cygnus.com) + + * readline.c: Can't initialize FILE *'s with stdin and stdout, + because they might not be constant. Patch from Tom Quinn, + trq@dinoysos.thphys.ox.ac.uk. + +Tue Apr 28 21:52:34 1992 John Gilmore (gnu at cygnus.com) + + * readline.h: Declare rl_event_hook (which already existed). + Suggested by Christoph Tietz . + +Wed Apr 22 18:08:01 1992 K. Richard Pixley (rich@rtl.cygnus.com) + + * configure.in: remove subdirs declaration. The obsolete semantic + for subdirs has been usurped by per's new meaning. + +Tue Apr 21 11:54:23 1992 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in: rework CFLAGS so that they can be set on the + command line to make. Remove MINUS_G. Default CFLAGS to -g. + +Fri Apr 10 23:02:27 1992 Fred Fish (fnf@cygnus.com) + + * configure.in: Recognize new ncr3000 config. + * config/mh-ncr3000: New NCR 3000 config file. + +Wed Mar 25 10:46:30 1992 John Gilmore (gnu at cygnus.com) + + * history.c (stifle_history): Negative arg treated as zero. + +Tue Mar 24 23:46:20 1992 K. Richard Pixley (rich@cygnus.com) + + * config/mh-sysv: INSTALL_PROG -> INSTALL. + +Mon Feb 10 01:41:35 1992 Brian Fox (bfox at gnuwest.fsf.org) + + * history.c (history_do_write) Build a buffer of all of the lines + to write and write them in one fell swoop (lower overhead than + calling write () for each line). Suggested by Peter Ho. + + * vi_mode.c (rl_vi_subst) Don't forget to end the undo group. + +Sat Mar 7 00:15:36 1992 K. Richard Pixley (rich@rtl.cygnus.com) + + * Makefile.in: remove FIXME's on info and install-info targets. + +Fri Mar 6 22:02:04 1992 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in: added check target. + +Wed Feb 26 18:04:40 1992 K. Richard Pixley (rich@cygnus.com) + + * Makefile.in, configure.in: removed traces of namesubdir, + -subdirs, $(subdir), $(unsubdir), some rcs triggers. Forced + copyrights to '92, changed some from Cygnus to FSF. + +Fri Feb 21 14:37:32 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * readline.c, examples/fileman.c: patches from DJ to support DOS + +Thu Feb 20 23:23:16 1992 Stu Grossman (grossman at cygnus.com) + + * readline.c (rl_read_init_file): Make sure that null filename is + not passed to open() or else we end up opening the directory, and + read a bunch of garbage into keymap[]. + +Mon Feb 17 17:15:09 1992 Fred Fish (fnf at cygnus.com) + + * readline.c (readline_default_bindings): Only make use of VLNEXT + when both VLNEXT and TERMIOS_TTY_DRIVER is defined. On SVR4 + includes , so VLNEXT is always defined. + + * sysdep-norm.h (_POSIX_VERSION): Define this for all SVR4 + systems so that gets used, instead of . + +Fri Dec 20 12:04:31 1991 Fred Fish (fnf at cygnus.com) + + * configure.in: Change svr4 references to sysv4. + +Tue Dec 10 04:07:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: infodir belongs in datadir. + +Fri Dec 6 23:23:14 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: remove spaces following hyphens, bsd make can't + cope. added clean-info. added standards.text support. Don't + know how to make info anymore. + + * configure.in: commontargets is no longer a recognized hook, so + remove it. new subdir called doc. + +Thu Dec 5 22:46:10 1991 K. Richard Pixley (rich at rtl.cygnus.com) + + * Makefile.in: idestdir and ddestdir go away. Added copyrights + and shift gpl to v2. Added ChangeLog if it didn't exist. docdir + and mandir now keyed off datadir by default. + +Fri Nov 22 09:02:32 1991 John Gilmore (gnu at cygnus.com) + + * sysdep-obsd.h: Rename from sysdep-newsos.h. + * configure.in: Use sysdep-obsd for Mach as well as NEWs. + + * sysdep-norm.h, sysdep-aix.h: Add , which POSIX + requires to make work. Improve Sun alloca decl. + +Thu Nov 21 18:48:08 1991 John Gilmore (gnu at cygnus.com) + + * Makefile.in: Clean up ../glob/tilde.c -> tilde.o path. + Clean up makefile a bit in general. + +Thu Nov 21 14:40:29 1991 Stu Grossman (grossman at cygnus.com) + + * configure.in, config/mh-svr4: Make SVR4 work. + + * readline.c: Move config stuff to sysdep.h, use typedef dirent + consistently, remove refs to d_namlen (& D_NAMLEN) to improve + portability. Also, update copyright notice. + readline.h: remove config stuff that I added erroneously in the + first place. + + * emacs_keymap.c, funmap.c, history.c, keymaps.c, vi_keymap.c, + vi_mode.c: move config stuff to sysdep.h, update copyright notices. + +Tue Nov 19 15:02:13 1991 Stu Grossman (grossman at cygnus.com) + + * history.c: #include "sysdep.h". + +Tue Nov 19 10:49:17 1991 Fred Fish (fnf at cygnus.com) + + * Makefile.in, config/hm-sysv, config/hm-sco: Change SYSV to + USG to match current usage. + + * readline.c: Add USGr4 to list of defined things to check for + to use style directory access. + + * config/hm-svr4: New file for System V Release 4 (USGr4). + +Mon Nov 18 23:59:52 1991 Stu Grossman (grossman at cygnus.com) + + * readline.c (filename_completion_function): use struct dirent + instead of struct direct. + +Fri Nov 1 07:02:13 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c (rl_translate_keyseq) Make C-? translate to RUBOUT + unconditionally. + +Mon Oct 28 11:34:52 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c; Use Posix directory routines and macros. + + * funmap.c; Add entry for call-last-kbd-macro. + + * readline.c (rl_prep_term); Use system EOF character on POSIX + systems also. + +Thu Oct 3 16:19:53 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c; Make a distinction between having a TERMIOS tty + driver, and having POSIX signal handling. You might one without + the other. New defines used HAVE_POSIX_SIGNALS, and + TERMIOS_TTY_DRIVER. + +Tue Jul 30 22:37:26 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: rl_getc () If a call to read () returns without an + error, but with zero characters, the file is empty, so return EOF. + +Thu Jul 11 20:58:38 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: (rl_get_next_history, rl_get_previous_history) + Reallocate the buffer space if the line being moved to is longer + the the current space allocated. Amazing that no one has found + this bug until now. + +Sun Jul 7 02:37:05 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c:(rl_parse_and_bind) Allow leading whitespace. + Make sure TERMIO and TERMIOS systems treat CR and NL + disctinctly. + +Tue Jun 25 04:09:27 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: Rework parsing conditionals to pay attention to the + prior states of the conditional stack. This makes $if statements + work correctly. + +Mon Jun 24 20:45:59 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: support for displaying key binding information + includes the functions rl_list_funmap_names (), + invoking_keyseqs_in_map (), rl_invoking_keyseqs (), + rl_dump_functions (), and rl_function_dumper (). + + funmap.c: support for same includes rl_funmap_names (). + + readline.c, funmap.c: no longer define STATIC_MALLOC. However, + update both version of xrealloc () to handle a null pointer. + +Thu Apr 25 12:03:49 1991 Brian Fox (bfox at gnuwest.fsf.org) + + * vi_mode.c (rl_vi_fword, fWord, etc. All functions use + the macro `isident()'. Fixed movement bug which prevents + continious movement through the text. + +Fri Jul 27 16:47:01 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c (parser_if) Allow "$if term=foo" construct. + +Wed May 23 16:10:33 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c (rl_dispatch) Correctly remember the last command + executed. Fixed typo in username_completion_function (). + +Mon Apr 9 19:55:48 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: username_completion_function (); For text passed in + with a leading `~', remember that this could be a filename (after + it is completed). + +Thu Apr 5 13:44:24 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: rl_search_history (): Correctly handle case of an + unfound search string, but a graceful exit (as with ESC). + + * readline.c: rl_restart_output (); The Apollo passes the address + of the file descriptor to TIOCSTART, not the descriptor itself. + +Tue Mar 20 05:38:55 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * readline.c: rl_complete (); second call in a row causes possible + completions to be listed. + + * readline.c: rl_redisplay (), added prompt_this_line variable + which is the first character character following \n in prompt. + +Sun Mar 11 04:32:03 1990 Brian Fox (bfox at gnuwest.fsf.org) + + * Signals are now supposedly handled inside of SYSV compilation. + +Wed Jan 17 19:24:09 1990 Brian Fox (bfox at sbphy.ucsb.edu) + + * history.c: history_expand (); fixed overwriting memory error, + added needed argument to call to get_history_event (). + +Thu Jan 11 10:54:04 1990 Brian Fox (bfox at sbphy.ucsb.edu) + + * readline.c: added mark_modified_lines to control the + display of an asterisk on modified history lines. Also + added a user variable called mark-modified-lines to the + `set' command. + +Thu Jan 4 10:38:05 1990 Brian Fox (bfox at sbphy.ucsb.edu) + + * readline.c: start_insert (). Only use IC if we don't have an im + capability. + +Fri Sep 8 09:00:45 1989 Brian Fox (bfox at aurel) + + * readline.c: rl_prep_terminal (). Only turn on 8th bit + as meta-bit iff the terminal is not using parity. + +Sun Sep 3 08:57:40 1989 Brian Fox (bfox at aurel) + + * readline.c: start_insert (). Uses multiple + insertion call in cases where that makes sense. + + rl_insert (). Read type-ahead buffer for additional + keys that are bound to rl_insert, and insert them + all at once. Make insertion of single keys given + with an argument much more efficient. + +Tue Aug 8 18:13:57 1989 Brian Fox (bfox at aurel) + + * readline.c: Changed handling of EOF. readline () returns + (char *)EOF or consed string. The EOF character is read from the + tty, or if the tty doesn't have one, defaults to C-d. + + * readline.c: Added support for event driven programs. + rl_event_hook is the address of a function you want called + while Readline is waiting for input. + + * readline.c: Cleanup time. Functions without type declarations + do not use return with a value. + + * history.c: history_expand () has new variable which is the + characters to ignore immediately following history_expansion_char. + +Sun Jul 16 08:14:00 1989 Brian Fox (bfox at aurel) + + * rl_prep_terminal () + BSD version turns off C-s, C-q, C-y, C-v. + + * readline.c -- rl_prep_terminal () + SYSV version hacks readline_echoing_p. + BSD version turns on passing of the 8th bit for the duration + of reading the line. + +Tue Jul 11 06:25:01 1989 Brian Fox (bfox at aurel) + + * readline.c: new variable rl_tilde_expander. + If non-null, this contains the address of a function to call if + the standard meaning for expanding a tilde fails. The function is + called with the text sans tilde (as in "foo"), and returns a + malloc()'ed string which is the expansion, or a NULL pointer if + there is no expansion. + + * readline.h - new file chardefs.h + Separates things that only readline.c needs from the standard + header file publishing interesting things about readline. + + * readline.c: + readline_default_bindings () now looks at terminal chararacters + and binds those as well. + +Wed Jun 28 20:20:51 1989 Brian Fox (bfox at aurel) + + * Made readline and history into independent libraries. + diff --git a/external/gpl3/gdb/dist/readline/INSTALL b/external/gpl3/gdb/dist/readline/INSTALL new file mode 100644 index 000000000000..1a73c779000d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/INSTALL @@ -0,0 +1,287 @@ +Basic Installation +================== + +These are installation instructions for Readline-5.1. + +The simplest way to compile readline is: + + 1. `cd' to the directory containing the readline source code and type + `./configure' to configure readline for your system. If you're + using `csh' on an old version of System V, you might need to type + `sh ./configure' instead to prevent `csh' from trying to execute + `configure' itself. + + Running `configure' takes some time. While running, it prints some + messages telling which features it is checking for. + + 2. Type `make' to compile readline and build the static readline + and history libraries. If supported, the shared readline and history + libraries will be built also. See below for instructions on compiling + the other parts of the distribution. Typing `make everything' will + cause the static and shared libraries (if supported) and the example + programs to be built. + + 3. Type `make install' to install the static readline and history + libraries, the readline include files, the documentation, and, if + supported, the shared readline and history libraries. + + 4. You can remove the created libraries and object files from the + build directory by typing `make clean'. To also remove the + files that `configure' created (so you can compile readline for + a different kind of computer), type `make distclean'. There is + also a `make maintainer-clean' target, but that is intended mainly + for the readline developers, and should be used with care. + +The `configure' shell script attempts to guess correct values for +various system-dependent variables used during compilation. It +uses those values to create a `Makefile' in the build directory, +and Makefiles in the `doc', `shlib', and `examples' +subdirectories. It also creates a `config.h' file containing +system-dependent definitions. Finally, it creates a shell script +`config.status' that you can run in the future to recreate the +current configuration, a file `config.cache' that saves the +results of its tests to speed up reconfiguring, and a file +`config.log' containing compiler output (useful mainly for +debugging `configure'). + +If you need to do unusual things to compile readline, please try +to figure out how `configure' could check whether to do them, and +mail diffs or instructions to so they can +be considered for the next release. If at some point +`config.cache' contains results you don't want to keep, you may +remove or edit it. + +The file `configure.in' is used to create `configure' by a +program called `autoconf'. You only need `configure.in' if you +want to change it or regenerate `configure' using a newer version +of `autoconf'. The readline `configure.in' requires autoconf +version 2.50 or newer. + +Compilers and Options +===================== + +Some systems require unusual options for compilation or linking that +the `configure' script does not know about. You can give `configure' +initial values for variables by setting them in the environment. Using +a Bourne-compatible shell, you can do that on the command line like +this: + + CC=c89 CFLAGS=-O2 LIBS=-lposix ./configure + +Or on systems that have the `env' program, you can do it like this: + + env CPPFLAGS=-I/usr/local/include LDFLAGS=-s ./configure + +Compiling For Multiple Architectures +==================================== + +You can compile readline for more than one kind of computer at the +same time, by placing the object files for each architecture in their +own directory. To do this, you must use a version of `make' that +supports the `VPATH' variable, such as GNU `make'. `cd' to the +directory where you want the object files and executables to go and run +the `configure' script. `configure' automatically checks for the +source code in the directory that `configure' is in and in `..'. + +If you have to use a `make' that does not supports the `VPATH' +variable, you have to compile readline for one architecture at a +time in the source code directory. After you have installed +readline for one architecture, use `make distclean' before +reconfiguring for another architecture. + +Installation Names +================== + +By default, `make install' will install the readline libraries in +`/usr/local/lib', the include files in +`/usr/local/include/readline', the man pages in `/usr/local/man', +and the info files in `/usr/local/info'. You can specify an +installation prefix other than `/usr/local' by giving `configure' +the option `--prefix=PATH' or by supplying a value for the +DESTDIR variable when running `make install'. + +You can specify separate installation prefixes for +architecture-specific files and architecture-independent files. +If you give `configure' the option `--exec-prefix=PATH', the +readline Makefiles will use PATH as the prefix for installing the +libraries. Documentation and other data files will still use the +regular prefix. + +Specifying the System Type +========================== + +There may be some features `configure' can not figure out +automatically, but need to determine by the type of host readline +will run on. Usually `configure' can figure that out, but if it +prints a message saying it can not guess the host type, give it +the `--host=TYPE' option. TYPE can either be a short name for +the system type, such as `sun4', or a canonical name with three +fields: CPU-COMPANY-SYSTEM (e.g., i386-unknown-freebsd4.2). + +See the file `config.sub' for the possible values of each field. + +Sharing Defaults +================ + +If you want to set default values for `configure' scripts to share, +you can create a site shell script called `config.site' that gives +default values for variables like `CC', `cache_file', and `prefix'. +`configure' looks for `PREFIX/share/config.site' if it exists, then +`PREFIX/etc/config.site' if it exists. Or, you can set the +`CONFIG_SITE' environment variable to the location of the site script. +A warning: the readline `configure' looks for a site script, but not +all `configure' scripts do. + +Operation Controls +================== + +`configure' recognizes the following options to control how it +operates. + +`--cache-file=FILE' + Use and save the results of the tests in FILE instead of + `./config.cache'. Set FILE to `/dev/null' to disable caching, for + debugging `configure'. + +`--help' + Print a summary of the options to `configure', and exit. + +`--quiet' +`--silent' +`-q' + Do not print messages saying which checks are being made. + +`--srcdir=DIR' + Look for the package's source code in directory DIR. Usually + `configure' can determine that directory automatically. + +`--version' + Print the version of Autoconf used to generate the `configure' + script, and exit. + +`configure' also accepts some other, not widely useful, options. + +Optional Features +================= + +The readline `configure' recognizes a single `--with-PACKAGE' option: + +`--with-curses' + This tells readline that it can find the termcap library functions + (tgetent, et al.) in the curses library, rather than a separate + termcap library. Readline uses the termcap functions, but does not + link with the termcap or curses library itself, allowing applications + which link with readline the to choose an appropriate library. + This option tells readline to link the example programs with the + curses library rather than libtermcap. + +`configure' also recognizes two `--enable-FEATURE' options: + +`--enable-shared' + Build the shared libraries by default on supported platforms. The + default is `yes'. + +`--enable-static' + Build the static libraries by default. The default is `yes'. + +Shared Libraries +================ + +There is support for building shared versions of the readline and +history libraries. The configure script creates a Makefile in +the `shlib' subdirectory, and typing `make shared' will cause +shared versions of the readline and history libraries to be built +on supported platforms. + +If `configure' is given the `--enable-shared' option, it will attempt +to build the shared libraries by default on supported platforms. + +Configure calls the script support/shobj-conf to test whether or +not shared library creation is supported and to generate the values +of variables that are substituted into shlib/Makefile. If you +try to build shared libraries on an unsupported platform, `make' +will display a message asking you to update support/shobj-conf for +your platform. + +If you need to update support/shobj-conf, you will need to create +a `stanza' for your operating system and compiler. The script uses +the value of host_os and ${CC} as determined by configure. For +instance, FreeBSD 4.2 with any version of gcc is identified as +`freebsd4.2-gcc*'. + +In the stanza for your operating system-compiler pair, you will need to +define several variables. They are: + +SHOBJ_CC The C compiler used to compile source files into shareable + object files. This is normally set to the value of ${CC} + by configure, and should not need to be changed. + +SHOBJ_CFLAGS Flags to pass to the C compiler ($SHOBJ_CC) to create + position-independent code. If you are using gcc, this + should probably be set to `-fpic'. + +SHOBJ_LD The link editor to be used to create the shared library from + the object files created by $SHOBJ_CC. If you are using + gcc, a value of `gcc' will probably work. + +SHOBJ_LDFLAGS Flags to pass to SHOBJ_LD to enable shared object creation. + If you are using gcc, `-shared' may be all that is necessary. + These should be the flags needed for generic shared object + creation. + +SHLIB_XLDFLAGS Additional flags to pass to SHOBJ_LD for shared library + creation. Many systems use the -R option to the link + editor to embed a path within the library for run-time + library searches. A reasonable value for such systems would + be `-R$(libdir)'. + +SHLIB_LIBS Any additional libraries that shared libraries should be + linked against when they are created. + +SHLIB_LIBPREF The prefix to use when generating the filename of the shared + library. The default is `lib'; Cygwin uses `cyg'. + +SHLIB_LIBSUFF The suffix to add to `libreadline' and `libhistory' when + generating the filename of the shared library. Many systems + use `so'; HP-UX uses `sl'. + +SHLIB_LIBVERSION The string to append to the filename to indicate the version + of the shared library. It should begin with $(SHLIB_LIBSUFF), + and possibly include version information that allows the + run-time loader to load the version of the shared library + appropriate for a particular program. Systems using shared + libraries similar to SunOS 4.x use major and minor library + version numbers; for those systems a value of + `$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' is appropriate. + Systems based on System V Release 4 don't use minor version + numbers; use `$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' on those systems. + Other Unix versions use different schemes. + +SHLIB_DLLVERSION The version number for shared libraries that determines API + compatibility between readline versions and the underlying + system. Used only on Cygwin. Defaults to $SHLIB_MAJOR, but + can be overridden at configuration time by defining DLLVERSION + in the environment. + +SHLIB_DOT The character used to separate the name of the shared library + from the suffix and version information. The default is `.'; + systems like Cygwin which don't separate version information + from the library name should set this to the empty string. + +SHLIB_STATUS Set this to `supported' when you have defined the other + necessary variables. Make uses this to determine whether + or not shared library creation should be attempted. If + shared libraries are not supported, this will be set to + `unsupported'. + +You should look at the existing stanzas in support/shobj-conf for ideas. + +Once you have updated support/shobj-conf, re-run configure and type +`make shared' or `make'. The shared libraries will be created in the +shlib subdirectory. + +If shared libraries are created, `make install' will install them. +You may install only the shared libraries by running `make +install-shared' from the top-level build directory. Running `make +install' in the shlib subdirectory will also work. If you don't want +to install any created shared libraries, run `make install-static'. diff --git a/external/gpl3/gdb/dist/readline/MANIFEST b/external/gpl3/gdb/dist/readline/MANIFEST new file mode 100644 index 000000000000..b288fb6f80a1 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/MANIFEST @@ -0,0 +1,146 @@ +# +# Master distribution manifest for the standalone readline distribution +# +doc d +examples d +examples/rlfe d +support d +shlib d +COPYING f +README f +MANIFEST f +INSTALL f +CHANGELOG f +CHANGES f +NEWS f +USAGE f +aclocal.m4 f +config.h.in f +configure f +configure.in f +Makefile.in f +ansi_stdlib.h f +chardefs.h f +history.h f +histlib.h f +keymaps.h f +posixdir.h f +posixjmp.h f +posixstat.h f +readline.h f +rlconf.h f +rldefs.h f +rlmbutil.h f +rlprivate.h f +rlshell.h f +rlstdc.h f +rltty.h f +rltypedefs.h f +rlwinsize.h f +tcap.h f +tilde.h f +xmalloc.h f +bind.c f +callback.c f +compat.c f +complete.c f +display.c f +emacs_keymap.c f +funmap.c f +input.c f +isearch.c f +keymaps.c f +kill.c f +macro.c f +mbutil.c f +misc.c f +nls.c f +parens.c f +readline.c f +rltty.c f +savestring.c f +search.c f +shell.c f +signals.c f +terminal.c f +text.c f +tilde.c f +undo.c f +util.c f +vi_keymap.c f +vi_mode.c f +xmalloc.c f +history.c f +histexpand.c f +histfile.c f +histsearch.c f +shlib/Makefile.in f +support/config.guess f +support/config.rpath f +support/config.sub f +support/install.sh f +support/mkdirs f +support/mkdist f +support/mkinstalldirs f +support/shobj-conf f +support/shlib-install f +support/wcwidth.c f +doc/Makefile.in f +doc/texinfo.tex f +doc/version.texi f +doc/fdl.texi f +doc/rlman.texi f +doc/rltech.texi f +doc/rluser.texi f +doc/rluserman.texi f +doc/history.texi f +doc/hstech.texi f +doc/hsuser.texi f +doc/readline.3 f +doc/history.3 f +doc/texi2dvi f +doc/texi2html f +examples/Makefile.in f +examples/excallback.c f +examples/fileman.c f +examples/manexamp.c f +examples/readlinebuf.h f +examples/rl-fgets.c f +examples/rlcat.c f +examples/rltest.c f +examples/rl.c f +examples/rlptytest.c f +examples/rlversion.c f +examples/histexamp.c f +examples/Inputrc f +examples/rlfe/ChangeLog f +examples/rlfe/Makefile.in f +examples/rlfe/README f +examples/rlfe/config.h.in f +examples/rlfe/configure f +examples/rlfe/configure.in f +examples/rlfe/extern.h f +examples/rlfe/os.h f +examples/rlfe/pty.c f +examples/rlfe/rlfe.c f +examples/rlfe/screen.h f +# formatted documentation, from MANIFEST.doc +doc/readline.ps f +doc/history.ps f +doc/rluserman.ps f +doc/readline.dvi f +doc/history.dvi f +doc/rluserman.dvi f +doc/readline.info f +doc/history.info f +doc/rluserman.info f +doc/readline.html f +doc/history.html f +doc/rluserman.html f +doc/readline.0 f +doc/history.0 f +doc/readline_3.ps f +doc/history_3.ps f +doc/history.pdf f +doc/readline.pdf f +doc/rluserman.pdf f diff --git a/external/gpl3/gdb/dist/readline/Makefile.in b/external/gpl3/gdb/dist/readline/Makefile.in new file mode 100644 index 000000000000..0f5607b77ad8 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/Makefile.in @@ -0,0 +1,557 @@ +## -*- text -*- ## +# Master Makefile for the GNU readline library. +# Copyright (C) 1994-2004 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. +RL_LIBRARY_VERSION = @LIBVERSION@ +RL_LIBRARY_NAME = readline + +PACKAGE = @PACKAGE_NAME@ +VERSION = @PACKAGE_VERSION@ + +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_VERSION = @PACKAGE_VERSION@ + +srcdir = @srcdir@ +VPATH = @srcdir@ +top_srcdir = @top_srcdir@ +BUILD_DIR = @BUILD_DIR@ + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +CC = @CC@ +RANLIB = @RANLIB@ +AR = @AR@ +ARFLAGS = @ARFLAGS@ +RM = rm -f +CP = cp +MV = mv + +PURIFY = @PURIFY@ + +@SET_MAKE@ +SHELL = @MAKE_SHELL@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +datarootdir = @datarootdir@ + +bindir = @bindir@ +libdir = @libdir@ +mandir = @mandir@ +includedir = @includedir@ +datadir = @datadir@ +localedir = $(datadir)/locale + +infodir = @infodir@ + +man3dir = $(mandir)/man3 + +# Support an alternate destination root directory for package building +DESTDIR = + +# Programs to make tags files. +ETAGS = etags -tw +CTAGS = ctags -tw + +CFLAGS = @CFLAGS@ +LOCAL_CFLAGS = @LOCAL_CFLAGS@ -DRL_LIBRARY_VERSION='"$(RL_LIBRARY_VERSION)"' +CPPFLAGS = @CPPFLAGS@ + +DEFS = @DEFS@ @CROSS_COMPILE@ +LOCAL_DEFS = @LOCAL_DEFS@ + +TERMCAP_LIB = @TERMCAP_LIB@ + +# For libraries which include headers from other libraries. +INCLUDES = -I. -I$(srcdir) + +XCCFLAGS = $(DEFS) $(LOCAL_DEFS) $(CPPFLAGS) $(INCLUDES) +CCFLAGS = $(XCCFLAGS) $(LOCAL_CFLAGS) $(CFLAGS) + +# could add -Werror here +GCC_LINT_FLAGS = -ansi -Wall -Wshadow -Wpointer-arith -Wcast-qual \ + -Wwrite-strings -Wstrict-prototypes \ + -Wmissing-prototypes -Wno-implicit -pedantic +GCC_LINT_CFLAGS = $(XCCFLAGS) $(GCC_LINT_FLAGS) @CFLAGS@ @LOCAL_CFLAGS@ + +.c.o: + ${RM} $@ + $(CC) -c $(CCFLAGS) $< + +# The name of the main library target. +LIBRARY_NAME = libreadline.a +STATIC_LIBS = libreadline.a libhistory.a + +WCWIDTH_OBJ = @WCWIDTH_OBJ@ + +# The C code source files for this library. +CSOURCES = $(srcdir)/readline.c $(srcdir)/funmap.c $(srcdir)/keymaps.c \ + $(srcdir)/vi_mode.c $(srcdir)/parens.c $(srcdir)/rltty.c \ + $(srcdir)/complete.c $(srcdir)/bind.c $(srcdir)/isearch.c \ + $(srcdir)/display.c $(srcdir)/signals.c $(srcdir)/emacs_keymap.c \ + $(srcdir)/vi_keymap.c $(srcdir)/util.c $(srcdir)/kill.c \ + $(srcdir)/undo.c $(srcdir)/macro.c $(srcdir)/input.c \ + $(srcdir)/callback.c $(srcdir)/terminal.c $(srcdir)/xmalloc.c \ + $(srcdir)/history.c $(srcdir)/histsearch.c $(srcdir)/histexpand.c \ + $(srcdir)/histfile.c $(srcdir)/nls.c $(srcdir)/search.c \ + $(srcdir)/shell.c $(srcdir)/savestring.c $(srcdir)/tilde.c \ + $(srcdir)/text.c $(srcdir)/misc.c $(srcdir)/compat.c \ + $(srcdir)/mbutil.c $(srcdir)/support/wcwidth.c + +# The header files for this library. +HSOURCES = readline.h rldefs.h chardefs.h keymaps.h history.h histlib.h \ + posixstat.h posixdir.h posixjmp.h tilde.h rlconf.h rltty.h \ + ansi_stdlib.h tcap.h rlstdc.h xmalloc.h rlprivate.h rlshell.h \ + rltypedefs.h rlmbutil.h + +HISTOBJ = history.o histexpand.o histfile.o histsearch.o shell.o mbutil.o +TILDEOBJ = tilde.o +OBJECTS = readline.o vi_mode.o funmap.o keymaps.o parens.o search.o \ + rltty.o complete.o bind.o isearch.o display.o signals.o \ + util.o kill.o undo.o macro.o input.o callback.o terminal.o \ + text.o nls.o misc.o compat.o xmalloc.o $(HISTOBJ) $(TILDEOBJ) \ + $(WCWIDTH_OBJ) + +# The texinfo files which document this library. +DOCSOURCE = doc/rlman.texinfo doc/rltech.texinfo doc/rluser.texinfo +DOCOBJECT = doc/readline.dvi +DOCSUPPORT = doc/Makefile +DOCUMENTATION = $(DOCSOURCE) $(DOCOBJECT) $(DOCSUPPORT) + +CREATED_MAKEFILES = Makefile doc/Makefile examples/Makefile shlib/Makefile +CREATED_CONFIGURE = config.status config.h config.cache config.log \ + stamp-config stamp-h +CREATED_TAGS = TAGS tags + +INSTALLED_HEADERS = readline.h chardefs.h keymaps.h history.h tilde.h \ + rlstdc.h rlconf.h rltypedefs.h + +########################################################################## +TARGETS = @STATIC_TARGET@ @SHARED_TARGET@ +INSTALL_TARGETS = @STATIC_INSTALL_TARGET@ @SHARED_INSTALL_TARGET@ + +all: $(TARGETS) + +everything: all examples + +static: $(STATIC_LIBS) + +libreadline.a: $(OBJECTS) + $(RM) $@ + $(AR) $(ARFLAGS) $@ $(OBJECTS) + -test -n "$(RANLIB)" && $(RANLIB) $@ + +libhistory.a: $(HISTOBJ) xmalloc.o + $(RM) $@ + $(AR) $(ARFLAGS) $@ $(HISTOBJ) xmalloc.o + -test -n "$(RANLIB)" && $(RANLIB) $@ + +wcwidth.o: $(srcdir)/support/wcwidth.c + $(RM) $@ + $(CC) $(CCFLAGS) -c $(srcdir)/support/wcwidth.c + +# Since tilde.c is shared between readline and bash, make sure we compile +# it with the right flags when it's built as part of readline +tilde.o: tilde.c + rm -f $@ + $(CC) $(CCFLAGS) -DREADLINE_LIBRARY -c $(srcdir)/tilde.c + +readline: $(OBJECTS) readline.h rldefs.h chardefs.h ./libreadline.a + $(CC) $(CCFLAGS) -o $@ ./examples/rl.c ./libreadline.a ${TERMCAP_LIB} + +lint: force + $(MAKE) $(MFLAGS) CCFLAGS='$(GCC_LINT_CFLAGS)' static + +Makefile makefile: config.status $(srcdir)/Makefile.in + CONFIG_FILES=Makefile CONFIG_HEADERS= $(SHELL) ./config.status + +Makefiles makefiles: config.status $(srcdir)/Makefile.in + @for mf in $(CREATED_MAKEFILES); do \ + CONFIG_FILES=$$mf CONFIG_HEADERS= $(SHELL) ./config.status ; \ + done + +config.status: configure + $(SHELL) ./config.status --recheck + +config.h: stamp-h + +stamp-h: config.status $(srcdir)/config.h.in + CONFIG_FILES= CONFIG_HEADERS=config.h ./config.status + echo > $@ + +#$(srcdir)/configure: $(srcdir)/configure.in ## Comment-me-out in distribution +# cd $(srcdir) && autoconf ## Comment-me-out in distribution + +shared: force + -test -d shlib || mkdir shlib + -( cd shlib ; ${MAKE} ${MFLAGS} all ) + +documentation: force + -test -d doc || mkdir doc + -( cd doc && $(MAKE) $(MFLAGS) ) + +examples: force + -test -d examples || mkdir examples + -(cd examples && ${MAKE} ${MFLAGS} all ) + +force: + +install-headers: installdirs ${INSTALLED_HEADERS} + for f in ${INSTALLED_HEADERS}; do \ + $(INSTALL_DATA) $(srcdir)/$$f $(DESTDIR)$(includedir)/readline ; \ + done + +uninstall-headers: + -test -n "$(includedir)" && cd $(DESTDIR)$(includedir)/readline && \ + ${RM} ${INSTALLED_HEADERS} + +maybe-uninstall-headers: uninstall-headers + +## GDB LOCAL +## Don't mess with people's installed readline's. +## This tries to install this version of readline over whatever +## version is already installed on the system (which could be a +## newer version). There is no real reason for us to install +## readline along with GDB. GDB links statically against readline, +## so it doesn't depend on us installing it on the system. + +install: + +#install: $(INSTALL_TARGETS) + +install-static: installdirs $(STATIC_LIBS) install-headers install-doc + -$(MV) $(DESTDIR)$(libdir)/libreadline.a $(DESTDIR)$(libdir)/libreadline.old + $(INSTALL_DATA) libreadline.a $(DESTDIR)$(libdir)/libreadline.a + -test -n "$(RANLIB)" && $(RANLIB) $(DESTDIR)$(libdir)/libreadline.a + -$(MV) $(DESTDIR)$(libdir)/libhistory.a $(DESTDIR)$(libdir)/libhistory.old + $(INSTALL_DATA) libhistory.a $(DESTDIR)$(libdir)/libhistory.a + -test -n "$(RANLIB)" && $(RANLIB) $(DESTDIR)$(libdir)/libhistory.a + +installdirs: $(srcdir)/support/mkinstalldirs + -$(SHELL) $(srcdir)/support/mkinstalldirs $(DESTDIR)$(includedir) \ + $(DESTDIR)$(includedir)/readline $(DESTDIR)$(libdir) \ + $(DESTDIR)$(infodir) $(DESTDIR)$(man3dir) + +uninstall: uninstall-headers uninstall-doc + -test -n "$(DESTDIR)$(libdir)" && cd $(DESTDIR)$(libdir) && \ + ${RM} libreadline.a libreadline.old libhistory.a libhistory.old $(SHARED_LIBS) + -( cd shlib; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} uninstall ) + +install-shared: installdirs install-headers shared install-doc + -( cd shlib ; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} install ) + +uninstall-shared: maybe-uninstall-headers + -( cd shlib; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} uninstall ) + +install-doc: installdirs + -( if test -d doc ; then \ + cd doc && \ + ${MAKE} ${MFLAGS} infodir=$(infodir) DESTDIR=${DESTDIR} install; \ + fi ) + +uninstall-doc: + -( if test -d doc ; then \ + cd doc && \ + ${MAKE} ${MFLAGS} infodir=$(infodir) DESTDIR=${DESTDIR} uninstall; \ + fi ) + +TAGS: force + $(ETAGS) $(CSOURCES) $(HSOURCES) + +tags: force + $(CTAGS) $(CSOURCES) $(HSOURCES) + +clean: force + $(RM) $(OBJECTS) $(STATIC_LIBS) + $(RM) readline readline.exe + -( cd shlib && $(MAKE) $(MFLAGS) $@ ) + -( cd doc && $(MAKE) $(MFLAGS) $@ ) + -( cd examples && $(MAKE) $(MFLAGS) $@ ) + +mostlyclean: clean + -( cd shlib && $(MAKE) $(MFLAGS) $@ ) + -( cd doc && $(MAKE) $(MFLAGS) $@ ) + -( cd examples && $(MAKE) $(MFLAGS) $@ ) + +distclean maintainer-clean: clean + -( cd shlib && $(MAKE) $(MFLAGS) $@ ) + -( cd doc && $(MAKE) $(MFLAGS) $@ ) + -( cd examples && $(MAKE) $(MFLAGS) $@ ) + $(RM) Makefile + $(RM) $(CREATED_CONFIGURE) + $(RM) $(CREATED_TAGS) + +info dvi html pdf: + -( cd doc && $(MAKE) $(MFLAGS) $@ ) + +install-info: +install-html: +install-pdf: +check: +installcheck: + +dist: force + @echo Readline distributions are created using $(srcdir)/support/mkdist. + @echo Here is a sample of the necessary commands: + @echo bash $(srcdir)/support/mkdist -m $(srcdir)/MANIFEST -s $(srcdir) -r $(RL_LIBRARY_NAME) $(RL_LIBRARY_VERSION) + @echo tar cf $(RL_LIBRARY_NAME)-${RL_LIBRARY_VERSION}.tar ${RL_LIBRARY_NAME}-$(RL_LIBRARY_VERSION) + @echo gzip $(RL_LIBRARY_NAME)-$(RL_LIBRARY_VERSION).tar + +# Tell versions [3.59,3.63) of GNU make not to export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: + +# Dependencies +bind.o: ansi_stdlib.h posixstat.h +bind.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +bind.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +bind.o: history.h +callback.o: rlconf.h +callback.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +callback.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +compat.o: rlstdc.h +complete.o: ansi_stdlib.h posixdir.h posixstat.h +complete.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +complete.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +display.o: ansi_stdlib.h posixstat.h +display.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +display.o: tcap.h +display.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +display.o: history.h rlstdc.h +funmap.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +funmap.o: rlconf.h ansi_stdlib.h rlstdc.h +funmap.o: ${BUILD_DIR}/config.h +histexpand.o: ansi_stdlib.h +histexpand.o: history.h histlib.h rlstdc.h rltypedefs.h +histexpand.o: ${BUILD_DIR}/config.h +histfile.o: ansi_stdlib.h +histfile.o: history.h histlib.h rlstdc.h rltypedefs.h +histfile.o: ${BUILD_DIR}/config.h +history.o: ansi_stdlib.h +history.o: history.h histlib.h rlstdc.h rltypedefs.h +history.o: ${BUILD_DIR}/config.h +histsearch.o: ansi_stdlib.h +histsearch.o: history.h histlib.h rlstdc.h rltypedefs.h +histsearch.o: ${BUILD_DIR}/config.h +input.o: ansi_stdlib.h +input.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +input.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +isearch.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +isearch.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +isearch.o: ansi_stdlib.h history.h rlstdc.h +keymaps.o: emacs_keymap.c vi_keymap.c +keymaps.o: keymaps.h rltypedefs.h chardefs.h rlconf.h ansi_stdlib.h +keymaps.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +keymaps.o: ${BUILD_DIR}/config.h rlstdc.h +kill.o: ansi_stdlib.h +kill.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +kill.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +kill.o: history.h rlstdc.h +macro.o: ansi_stdlib.h +macro.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +macro.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +macro.o: history.h rlstdc.h +mbutil.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +mbutil.o: readline.h keymaps.h rltypedefs.h chardefs.h rlstdc.h +misc.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +misc.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +misc.o: history.h rlstdc.h ansi_stdlib.h +nls.o: ansi_stdlib.h +nls.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +nls.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +nls.o: history.h rlstdc.h +parens.o: rlconf.h +parens.o: ${BUILD_DIR}/config.h +parens.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +readline.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +readline.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +readline.o: history.h rlstdc.h +readline.o: posixstat.h ansi_stdlib.h posixjmp.h +rltty.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +rltty.o: rltty.h +rltty.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +search.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +search.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +search.o: ansi_stdlib.h history.h rlstdc.h +shell.o: ${BUILD_DIR}/config.h +shell.o: ansi_stdlib.h +signals.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +signals.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +signals.o: history.h rlstdc.h +terminal.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +terminal.o: tcap.h +terminal.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +terminal.o: history.h rlstdc.h +text.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +text.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +text.o: history.h rlstdc.h ansi_stdlib.h +tilde.o: ansi_stdlib.h +tilde.o: ${BUILD_DIR}/config.h +tilde.o: tilde.h +undo.o: ansi_stdlib.h +undo.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +undo.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +undo.o: history.h rlstdc.h +util.o: posixjmp.h ansi_stdlib.h +util.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +util.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h rlstdc.h +vi_mode.o: rldefs.h ${BUILD_DIR}/config.h rlconf.h +vi_mode.o: readline.h keymaps.h rltypedefs.h chardefs.h tilde.h +vi_mode.o: history.h ansi_stdlib.h rlstdc.h +xmalloc.o: ${BUILD_DIR}/config.h +xmalloc.o: ansi_stdlib.h readline.h + +bind.o: rlshell.h +histfile.o: rlshell.h +nls.o: rlshell.h +readline.o: rlshell.h +shell.o: rlshell.h +terminal.o: rlshell.h +histexpand.o: rlshell.h + +bind.o: rlprivate.h +callback.o: rlprivate.h +complete.o: rlprivate.h +display.o: rlprivate.h +input.o: rlprivate.h +isearch.o: rlprivate.h +kill.o: rlprivate.h +macro.o: rlprivate.h +mbutil.o: rlprivate.h +misc.o: rlprivate.h +nls.o: rlprivate.h +parens.o: rlprivate.h +readline.o: rlprivate.h +rltty.o: rlprivate.h +search.o: rlprivate.h +signals.o: rlprivate.h +terminal.o: rlprivate.h +text.o: rlprivate.h +undo.o: rlprivate.h +util.o: rlprivate.h +vi_mode.o: rlprivate.h + +bind.o: xmalloc.h +callback.o: xmalloc.h +complete.o: xmalloc.h +display.o: xmalloc.h +funmap.o: xmalloc.h +histexpand.o: xmalloc.h +histfile.o: xmalloc.h +history.o: xmalloc.h +input.o: xmalloc.h +isearch.o: xmalloc.h +keymaps.o: xmalloc.h +kill.o: xmalloc.h +macro.o: xmalloc.h +mbutil.o: xmalloc.h +misc.o: xmalloc.h +readline.o: xmalloc.h +savestring.o: xmalloc.h +search.o: xmalloc.h +shell.o: xmalloc.h +terminal.o: xmalloc.h +text.o: xmalloc.h +tilde.o: xmalloc.h +undo.o: xmalloc.h +util.o: xmalloc.h +vi_mode.o: xmalloc.h +xmalloc.o: xmalloc.h + +complete.o: rlmbutil.h +display.o: rlmbutil.h +histexpand.o: rlmbutil.h +input.o: rlmbutil.h +isearch.o: rlmbutil.h +mbutil.o: rlmbutil.h +misc.o: rlmbutil.h +readline.o: rlmbutil.h +search.o: rlmbutil.h +text.o: rlmbutil.h +vi_mode.o: rlmbutil.h + +bind.o: $(srcdir)/bind.c +callback.o: $(srcdir)/callback.c +compat.o: $(srcdir)/compat.c +complete.o: $(srcdir)/complete.c +display.o: $(srcdir)/display.c +funmap.o: $(srcdir)/funmap.c +input.o: $(srcdir)/input.c +isearch.o: $(srcdir)/isearch.c +keymaps.o: $(srcdir)/keymaps.c $(srcdir)/emacs_keymap.c $(srcdir)/vi_keymap.c +kill.o: $(srcdir)/kill.c +macro.o: $(srcdir)/macro.c +mbutil.o: $(srcdir)/mbutil.c +misc.o: $(srcdir)/misc.c +nls.o: $(srcdir)/nls.c +parens.o: $(srcdir)/parens.c +readline.o: $(srcdir)/readline.c +rltty.o: $(srcdir)/rltty.c +savestring.o: $(srcdir)/savestring.c +search.o: $(srcdir)/search.c +shell.o: $(srcdir)/shell.c +signals.o: $(srcdir)/signals.c +terminal.o: $(srcdir)/terminal.c +text.o: $(srcdir)/text.c +tilde.o: $(srcdir)/tilde.c +undo.o: $(srcdir)/undo.c +util.o: $(srcdir)/util.c +vi_mode.o: $(srcdir)/vi_mode.c +xmalloc.o: $(srcdir)/xmalloc.c + +histexpand.o: $(srcdir)/histexpand.c +histfile.o: $(srcdir)/histfile.c +history.o: $(srcdir)/history.c +histsearch.o: $(srcdir)/histsearch.c + +bind.o: bind.c +callback.o: callback.c +compat.o: compat.c +complete.o: complete.c +display.o: display.c +funmap.o: funmap.c +input.o: input.c +isearch.o: isearch.c +keymaps.o: keymaps.c emacs_keymap.c vi_keymap.c +kill.o: kill.c +macro.o: macro.c +mbutil.o: mbutil.c +misc.o: misc.c +nls.o: nls.c +parens.o: parens.c +readline.o: readline.c +rltty.o: rltty.c +savestring.o: savestring.c +search.o: search.c +shell.o: shell.c +signals.o: signals.c +terminal.o: terminal.c +text.o: text.c +tilde.o: tilde.c +undo.o: undo.c +util.o: util.c +vi_mode.o: vi_mode.c +xmalloc.o: xmalloc.c + +histexpand.o: histexpand.c +histfile.o: histfile.c +history.o: history.c +histsearch.o: histsearch.c diff --git a/external/gpl3/gdb/dist/readline/NEWS b/external/gpl3/gdb/dist/readline/NEWS new file mode 100644 index 000000000000..c5e67dc793fa --- /dev/null +++ b/external/gpl3/gdb/dist/readline/NEWS @@ -0,0 +1,32 @@ +This is a terse description of the new features added to readline-5.1 since +the release of readline-5.0. + +1. New Features in Readline + +a. The key sequence sent by the keypad `delete' key is now automatically + bound to delete-char. + +b. A negative argument to menu-complete now cycles backward through the + completion list. + +c. A new bindable readline variable: bind-tty-special-chars. If non-zero, + readline will bind the terminal special characters to their readline + equivalents when it's called (on by default). + +d. New bindable command: vi-rubout. Saves deleted text for possible + reinsertion, as with any vi-mode `text modification' command; `X' is bound + to this in vi command mode. + +e. If the rl_completion_query_items is set to a value < 0, readline never + asks the user whether or not to view the possible completions. + +f. New application-callable auxiliary function, rl_variable_value, returns + a string corresponding to a readline variable's value. + +g. When parsing inputrc files and variable binding commands, the parser + strips trailing whitespace from values assigned to boolean variables + before checking them. + +h. A new external application-controllable variable that allows the LINES + and COLUMNS environment variables to set the window size regardless of + what the kernel returns. diff --git a/external/gpl3/gdb/dist/readline/README b/external/gpl3/gdb/dist/readline/README new file mode 100644 index 000000000000..8dd09cc5373c --- /dev/null +++ b/external/gpl3/gdb/dist/readline/README @@ -0,0 +1,186 @@ +Introduction +============ + +This is the Gnu Readline library, version 5.1. + +The Readline library provides a set of functions for use by applications +that allow users to edit command lines as they are typed in. Both +Emacs and vi editing modes are available. The Readline library includes +additional functions to maintain a list of previously-entered command +lines, to recall and perhaps reedit those lines, and perform csh-like +history expansion on previous commands. + +The history facilites are also placed into a separate library, the +History library, as part of the build process. The History library +may be used without Readline in applications which desire its +capabilities. + +The Readline library is free software, distributed under the terms of +the [GNU] General Public License, version 2. For more information, see +the file COPYING. + +To build the library, try typing `./configure', then `make'. The +configuration process is automated, so no further intervention should +be necessary. Readline builds with `gcc' by default if it is +available. If you want to use `cc' instead, type + + CC=cc ./configure + +if you are using a Bourne-style shell. If you are not, the following +may work: + + env CC=cc ./configure + +Read the file INSTALL in this directory for more information about how +to customize and control the build process. + +The file rlconf.h contains C preprocessor defines that enable and disable +certain Readline features. + +The special make target `everything' will build the static and shared +libraries (if the target platform supports them) and the examples. + +Examples +======== + +There are several example programs that use Readline features in the +examples directory. The `rl' program is of particular interest. It +is a command-line interface to Readline, suitable for use in shell +scripts in place of `read'. + +Shared Libraries +================ + +There is skeletal support for building shared versions of the +Readline and History libraries. The configure script creates +a Makefile in the `shlib' subdirectory, and typing `make shared' +will cause shared versions of the Readline and History libraries +to be built on supported platforms. + +If `configure' is given the `--enable-shared' option, it will attempt +to build the shared libraries by default on supported platforms. + +Configure calls the script support/shobj-conf to test whether or +not shared library creation is supported and to generate the values +of variables that are substituted into shlib/Makefile. If you +try to build shared libraries on an unsupported platform, `make' +will display a message asking you to update support/shobj-conf for +your platform. + +If you need to update support/shobj-conf, you will need to create +a `stanza' for your operating system and compiler. The script uses +the value of host_os and ${CC} as determined by configure. For +instance, FreeBSD 4.2 with any version of gcc is identified as +`freebsd4.2-gcc*'. + +In the stanza for your operating system-compiler pair, you will need to +define several variables. They are: + +SHOBJ_CC The C compiler used to compile source files into shareable + object files. This is normally set to the value of ${CC} + by configure, and should not need to be changed. + +SHOBJ_CFLAGS Flags to pass to the C compiler ($SHOBJ_CC) to create + position-independent code. If you are using gcc, this + should probably be set to `-fpic'. + +SHOBJ_LD The link editor to be used to create the shared library from + the object files created by $SHOBJ_CC. If you are using + gcc, a value of `gcc' will probably work. + +SHOBJ_LDFLAGS Flags to pass to SHOBJ_LD to enable shared object creation. + If you are using gcc, `-shared' may be all that is necessary. + These should be the flags needed for generic shared object + creation. + +SHLIB_XLDFLAGS Additional flags to pass to SHOBJ_LD for shared library + creation. Many systems use the -R option to the link + editor to embed a path within the library for run-time + library searches. A reasonable value for such systems would + be `-R$(libdir)'. + +SHLIB_LIBS Any additional libraries that shared libraries should be + linked against when they are created. + +SHLIB_LIBPREF The prefix to use when generating the filename of the shared + library. The default is `lib'; Cygwin uses `cyg'. + +SHLIB_LIBSUFF The suffix to add to `libreadline' and `libhistory' when + generating the filename of the shared library. Many systems + use `so'; HP-UX uses `sl'. + +SHLIB_LIBVERSION The string to append to the filename to indicate the version + of the shared library. It should begin with $(SHLIB_LIBSUFF), + and possibly include version information that allows the + run-time loader to load the version of the shared library + appropriate for a particular program. Systems using shared + libraries similar to SunOS 4.x use major and minor library + version numbers; for those systems a value of + `$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' is appropriate. + Systems based on System V Release 4 don't use minor version + numbers; use `$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' on those systems. + Other Unix versions use different schemes. + +SHLIB_DLLVERSION The version number for shared libraries that determines API + compatibility between readline versions and the underlying + system. Used only on Cygwin. Defaults to $SHLIB_MAJOR, but + can be overridden at configuration time by defining DLLVERSION + in the environment. + +SHLIB_DOT The character used to separate the name of the shared library + from the suffix and version information. The default is `.'; + systems like Cygwin which don't separate version information + from the library name should set this to the empty string. + +SHLIB_STATUS Set this to `supported' when you have defined the other + necessary variables. Make uses this to determine whether + or not shared library creation should be attempted. + +You should look at the existing stanzas in support/shobj-conf for ideas. + +Once you have updated support/shobj-conf, re-run configure and type +`make shared'. The shared libraries will be created in the shlib +subdirectory. + +If shared libraries are created, `make install' will install them. +You may install only the shared libraries by running `make +install-shared' from the top-level build directory. Running `make +install' in the shlib subdirectory will also work. If you don't want +to install any created shared libraries, run `make install-static'. + +Documentation +============= + +The documentation for the Readline and History libraries appears in +the `doc' subdirectory. There are three texinfo files and a +Unix-style manual page describing the facilities available in the +Readline library. The texinfo files include both user and +programmer's manuals. HTML versions of the manuals appear in the +`doc' subdirectory as well. + +Reporting Bugs +============== + +Bug reports for Readline should be sent to: + + bug-readline@gnu.org + +When reporting a bug, please include the following information: + + * the version number and release status of Readline (e.g., 4.2-release) + * the machine and OS that it is running on + * a list of the compilation flags or the contents of `config.h', if + appropriate + * a description of the bug + * a recipe for recreating the bug reliably + * a fix for the bug if you have one! + +If you would like to contact the Readline maintainer directly, send mail +to bash-maintainers@gnu.org. + +Since Readline is developed along with bash, the bug-bash@gnu.org mailing +list (mirrored to the Usenet newsgroup gnu.bash.bug) often contains +Readline bug reports and fixes. + +Chet Ramey +chet@po.cwru.edu diff --git a/external/gpl3/gdb/dist/readline/USAGE b/external/gpl3/gdb/dist/readline/USAGE new file mode 100644 index 000000000000..edc9f5417d4e --- /dev/null +++ b/external/gpl3/gdb/dist/readline/USAGE @@ -0,0 +1,37 @@ +From rms@gnu.org Thu Jul 22 20:37:55 1999 +Flags: 10 +Return-Path: rms@gnu.org +Received: from arthur.INS.CWRU.Edu (root@arthur.INS.CWRU.Edu [129.22.8.215]) by odin.INS.CWRU.Edu with ESMTP (8.8.6+cwru/CWRU-2.4-ins) + id UAA25349; Thu, 22 Jul 1999 20:37:54 -0400 (EDT) (from rms@gnu.org for ) +Received: from nike.ins.cwru.edu (root@nike.INS.CWRU.Edu [129.22.8.219]) by arthur.INS.CWRU.Edu with ESMTP (8.8.8+cwru/CWRU-3.6) + id UAA05311; Thu, 22 Jul 1999 20:37:51 -0400 (EDT) (from rms@gnu.org for ) +Received: from pele.santafe.edu (pele.santafe.edu [192.12.12.119]) by nike.ins.cwru.edu with ESMTP (8.8.7/CWRU-2.5-bsdi) + id UAA13350; Thu, 22 Jul 1999 20:37:50 -0400 (EDT) (from rms@gnu.org for ) +Received: from wijiji.santafe.edu (wijiji [192.12.12.5]) + by pele.santafe.edu (8.9.1/8.9.1) with ESMTP id SAA10831 + for ; Thu, 22 Jul 1999 18:37:47 -0600 (MDT) +Received: (from rms@localhost) + by wijiji.santafe.edu (8.9.1b+Sun/8.9.1) id SAA01089; + Thu, 22 Jul 1999 18:37:46 -0600 (MDT) +Date: Thu, 22 Jul 1999 18:37:46 -0600 (MDT) +Message-Id: <199907230037.SAA01089@wijiji.santafe.edu> +X-Authentication-Warning: wijiji.santafe.edu: rms set sender to rms@gnu.org using -f +From: Richard Stallman +To: chet@nike.ins.cwru.edu +Subject: Use of Readline +Reply-to: rms@gnu.org + +I think Allbery's suggestion is a good one. So please add this text +in a suitable place. Please don't put it in the GPL itself; that +should be the same as the GPL everywhere else. Putting it in the +README and/or the documentation would be a good idea. + + +====================================================================== +Our position on the use of Readline through a shared-library linking +mechanism is that there is no legal difference between shared-library +linking and static linking--either kind of linking combines various +modules into a single larger work. The conditions for using Readline +in a larger work are stated in section 3 of the GNU GPL. + + diff --git a/external/gpl3/gdb/dist/readline/aclocal.m4 b/external/gpl3/gdb/dist/readline/aclocal.m4 new file mode 100644 index 000000000000..485ca491c1dc --- /dev/null +++ b/external/gpl3/gdb/dist/readline/aclocal.m4 @@ -0,0 +1,3966 @@ +dnl +dnl Bash specific tests +dnl +dnl Some derived from PDKSH 5.1.3 autoconf tests +dnl + +AC_DEFUN(BASH_C_LONG_LONG, +[AC_CACHE_CHECK(for long long, ac_cv_c_long_long, +[if test "$GCC" = yes; then + ac_cv_c_long_long=yes +else +AC_TRY_RUN([ +int +main() +{ +long long foo = 0; +exit(sizeof(long long) < sizeof(long)); +} +], ac_cv_c_long_long=yes, ac_cv_c_long_long=no) +fi]) +if test $ac_cv_c_long_long = yes; then + AC_DEFINE(HAVE_LONG_LONG, 1, [Define if the `long long' type works.]) +fi +]) + +dnl +dnl This is very similar to AC_C_LONG_DOUBLE, with the fix for IRIX +dnl (< changed to <=) added. +dnl +AC_DEFUN(BASH_C_LONG_DOUBLE, +[AC_CACHE_CHECK(for long double, ac_cv_c_long_double, +[if test "$GCC" = yes; then + ac_cv_c_long_double=yes +else +AC_TRY_RUN([ +int +main() +{ + /* The Stardent Vistra knows sizeof(long double), but does not + support it. */ + long double foo = 0.0; + /* On Ultrix 4.3 cc, long double is 4 and double is 8. */ + /* On IRIX 5.3, the compiler converts long double to double with a warning, + but compiles this successfully. */ + exit(sizeof(long double) <= sizeof(double)); +} +], ac_cv_c_long_double=yes, ac_cv_c_long_double=no) +fi]) +if test $ac_cv_c_long_double = yes; then + AC_DEFINE(HAVE_LONG_DOUBLE, 1, [Define if the `long double' type works.]) +fi +]) + +dnl +dnl Check for . This is separated out so that it can be +dnl AC_REQUIREd. +dnl +dnl BASH_HEADER_INTTYPES +AC_DEFUN(BASH_HEADER_INTTYPES, +[ + AC_CHECK_HEADERS(inttypes.h) +]) + +dnl +dnl check for typedef'd symbols in header files, but allow the caller to +dnl specify the include files to be checked in addition to the default +dnl +dnl BASH_CHECK_TYPE(TYPE, HEADERS, DEFAULT[, VALUE-IF-FOUND]) +AC_DEFUN(BASH_CHECK_TYPE, +[ +AC_REQUIRE([AC_HEADER_STDC])dnl +AC_REQUIRE([BASH_HEADER_INTTYPES]) +AC_MSG_CHECKING(for $1) +AC_CACHE_VAL(bash_cv_type_$1, +[AC_EGREP_CPP($1, [#include +#if STDC_HEADERS +#include +#include +#endif +#if HAVE_INTTYPES_H +#include +#endif +$2 +], bash_cv_type_$1=yes, bash_cv_type_$1=no)]) +AC_MSG_RESULT($bash_cv_type_$1) +ifelse($#, 4, [if test $bash_cv_type_$1 = yes; then + AC_DEFINE($4) + fi]) +if test $bash_cv_type_$1 = no; then + AC_DEFINE_UNQUOTED($1, $3) +fi +]) + +dnl +dnl BASH_CHECK_DECL(FUNC) +dnl +dnl Check for a declaration of FUNC in stdlib.h and inttypes.h like +dnl AC_CHECK_DECL +dnl +AC_DEFUN(BASH_CHECK_DECL, +[ +AC_REQUIRE([AC_HEADER_STDC]) +AC_REQUIRE([BASH_HEADER_INTTYPES]) +AC_CACHE_CHECK([for declaration of $1], bash_cv_decl_$1, +[AC_TRY_LINK( +[ +#if STDC_HEADERS +# include +#endif +#if HAVE_INTTYPES_H +# include +#endif +], +[return !$1;], +bash_cv_decl_$1=yes, bash_cv_decl_$1=no)]) +bash_tr_func=HAVE_DECL_`echo $1 | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` +if test $bash_cv_decl_$1 = yes; then + AC_DEFINE_UNQUOTED($bash_tr_func, 1) +else + AC_DEFINE_UNQUOTED($bash_tr_func, 0) +fi +]) + +AC_DEFUN(BASH_DECL_PRINTF, +[AC_MSG_CHECKING(for declaration of printf in ) +AC_CACHE_VAL(bash_cv_printf_declared, +[AC_TRY_RUN([ +#include +#ifdef __STDC__ +typedef int (*_bashfunc)(const char *, ...); +#else +typedef int (*_bashfunc)(); +#endif +main() +{ +_bashfunc pf; +pf = (_bashfunc) printf; +exit(pf == 0); +} +], bash_cv_printf_declared=yes, bash_cv_printf_declared=no, + [AC_MSG_WARN(cannot check printf declaration if cross compiling -- defaulting to yes) + bash_cv_printf_declared=yes] +)]) +AC_MSG_RESULT($bash_cv_printf_declared) +if test $bash_cv_printf_declared = yes; then +AC_DEFINE(PRINTF_DECLARED) +fi +]) + +AC_DEFUN(BASH_DECL_SBRK, +[AC_MSG_CHECKING(for declaration of sbrk in ) +AC_CACHE_VAL(bash_cv_sbrk_declared, +[AC_EGREP_HEADER(sbrk, unistd.h, + bash_cv_sbrk_declared=yes, bash_cv_sbrk_declared=no)]) +AC_MSG_RESULT($bash_cv_sbrk_declared) +if test $bash_cv_sbrk_declared = yes; then +AC_DEFINE(SBRK_DECLARED) +fi +]) + +dnl +dnl Check for sys_siglist[] or _sys_siglist[] +dnl +AC_DEFUN(BASH_DECL_UNDER_SYS_SIGLIST, +[AC_MSG_CHECKING([for _sys_siglist in signal.h or unistd.h]) +AC_CACHE_VAL(bash_cv_decl_under_sys_siglist, +[AC_TRY_COMPILE([ +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif], [ char *msg = _sys_siglist[2]; ], + bash_cv_decl_under_sys_siglist=yes, bash_cv_decl_under_sys_siglist=no, + [AC_MSG_WARN(cannot check for _sys_siglist[] if cross compiling -- defaulting to no)])])dnl +AC_MSG_RESULT($bash_cv_decl_under_sys_siglist) +if test $bash_cv_decl_under_sys_siglist = yes; then +AC_DEFINE(UNDER_SYS_SIGLIST_DECLARED) +fi +]) + +AC_DEFUN(BASH_UNDER_SYS_SIGLIST, +[AC_REQUIRE([BASH_DECL_UNDER_SYS_SIGLIST]) +AC_MSG_CHECKING([for _sys_siglist in system C library]) +AC_CACHE_VAL(bash_cv_under_sys_siglist, +[AC_TRY_RUN([ +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#ifndef UNDER_SYS_SIGLIST_DECLARED +extern char *_sys_siglist[]; +#endif +main() +{ +char *msg = (char *)_sys_siglist[2]; +exit(msg == 0); +}], + bash_cv_under_sys_siglist=yes, bash_cv_under_sys_siglist=no, + [AC_MSG_WARN(cannot check for _sys_siglist[] if cross compiling -- defaulting to no) + bash_cv_under_sys_siglist=no])]) +AC_MSG_RESULT($bash_cv_under_sys_siglist) +if test $bash_cv_under_sys_siglist = yes; then +AC_DEFINE(HAVE_UNDER_SYS_SIGLIST) +fi +]) + +AC_DEFUN(BASH_SYS_SIGLIST, +[AC_REQUIRE([AC_DECL_SYS_SIGLIST]) +AC_MSG_CHECKING([for sys_siglist in system C library]) +AC_CACHE_VAL(bash_cv_sys_siglist, +[AC_TRY_RUN([ +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#ifndef SYS_SIGLIST_DECLARED +extern char *sys_siglist[]; +#endif +main() +{ +char *msg = sys_siglist[2]; +exit(msg == 0); +}], + bash_cv_sys_siglist=yes, bash_cv_sys_siglist=no, + [AC_MSG_WARN(cannot check for sys_siglist if cross compiling -- defaulting to no) + bash_cv_sys_siglist=no])]) +AC_MSG_RESULT($bash_cv_sys_siglist) +if test $bash_cv_sys_siglist = yes; then +AC_DEFINE(HAVE_SYS_SIGLIST) +fi +]) + +dnl Check for the various permutations of sys_siglist and make sure we +dnl compile in siglist.o if they're not defined +AC_DEFUN(BASH_CHECK_SYS_SIGLIST, [ +AC_REQUIRE([BASH_SYS_SIGLIST]) +AC_REQUIRE([BASH_DECL_UNDER_SYS_SIGLIST]) +AC_REQUIRE([BASH_FUNC_STRSIGNAL]) +if test "$bash_cv_sys_siglist" = no && test "$bash_cv_under_sys_siglist" = no && test "$bash_cv_have_strsignal" = no; then + SIGLIST_O=siglist.o +else + SIGLIST_O= +fi +AC_SUBST([SIGLIST_O]) +]) + +dnl Check for sys_errlist[] and sys_nerr, check for declaration +AC_DEFUN(BASH_SYS_ERRLIST, +[AC_MSG_CHECKING([for sys_errlist and sys_nerr]) +AC_CACHE_VAL(bash_cv_sys_errlist, +[AC_TRY_LINK([#include ], +[extern char *sys_errlist[]; + extern int sys_nerr; + char *msg = sys_errlist[sys_nerr - 1];], + bash_cv_sys_errlist=yes, bash_cv_sys_errlist=no)])dnl +AC_MSG_RESULT($bash_cv_sys_errlist) +if test $bash_cv_sys_errlist = yes; then +AC_DEFINE(HAVE_SYS_ERRLIST) +fi +]) + +dnl +dnl Check if dup2() does not clear the close on exec flag +dnl +AC_DEFUN(BASH_FUNC_DUP2_CLOEXEC_CHECK, +[AC_MSG_CHECKING(if dup2 fails to clear the close-on-exec flag) +AC_CACHE_VAL(bash_cv_dup2_broken, +[AC_TRY_RUN([ +#include +#include +main() +{ + int fd1, fd2, fl; + fd1 = open("/dev/null", 2); + if (fcntl(fd1, 2, 1) < 0) + exit(1); + fd2 = dup2(fd1, 1); + if (fd2 < 0) + exit(2); + fl = fcntl(fd2, 1, 0); + /* fl will be 1 if dup2 did not reset the close-on-exec flag. */ + exit(fl != 1); +} +], bash_cv_dup2_broken=yes, bash_cv_dup2_broken=no, + [AC_MSG_WARN(cannot check dup2 if cross compiling -- defaulting to no) + bash_cv_dup2_broken=no]) +]) +AC_MSG_RESULT($bash_cv_dup2_broken) +if test $bash_cv_dup2_broken = yes; then +AC_DEFINE(DUP2_BROKEN) +fi +]) + +AC_DEFUN(BASH_FUNC_STRSIGNAL, +[AC_MSG_CHECKING([for the existence of strsignal]) +AC_CACHE_VAL(bash_cv_have_strsignal, +[AC_TRY_LINK([#include +#include ], +[char *s = (char *)strsignal(2);], + bash_cv_have_strsignal=yes, bash_cv_have_strsignal=no)]) +AC_MSG_RESULT($bash_cv_have_strsignal) +if test $bash_cv_have_strsignal = yes; then +AC_DEFINE(HAVE_STRSIGNAL) +fi +]) + +dnl Check to see if opendir will open non-directories (not a nice thing) +AC_DEFUN(BASH_FUNC_OPENDIR_CHECK, +[AC_REQUIRE([AC_HEADER_DIRENT])dnl +AC_MSG_CHECKING(if opendir() opens non-directories) +AC_CACHE_VAL(bash_cv_opendir_not_robust, +[AC_TRY_RUN([ +#include +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ +main() +{ +DIR *dir; +int fd, err; +err = mkdir("/tmp/bash-aclocal", 0700); +if (err < 0) { + perror("mkdir"); + exit(1); +} +unlink("/tmp/bash-aclocal/not_a_directory"); +fd = open("/tmp/bash-aclocal/not_a_directory", O_WRONLY|O_CREAT|O_EXCL, 0666); +write(fd, "\n", 1); +close(fd); +dir = opendir("/tmp/bash-aclocal/not_a_directory"); +unlink("/tmp/bash-aclocal/not_a_directory"); +rmdir("/tmp/bash-aclocal"); +exit (dir == 0); +}], bash_cv_opendir_not_robust=yes,bash_cv_opendir_not_robust=no, + [AC_MSG_WARN(cannot check opendir if cross compiling -- defaulting to no) + bash_cv_opendir_not_robust=no] +)]) +AC_MSG_RESULT($bash_cv_opendir_not_robust) +if test $bash_cv_opendir_not_robust = yes; then +AC_DEFINE(OPENDIR_NOT_ROBUST) +fi +]) + +dnl +AC_DEFUN(BASH_TYPE_SIGHANDLER, +[AC_MSG_CHECKING([whether signal handlers are of type void]) +AC_CACHE_VAL(bash_cv_void_sighandler, +[AC_TRY_COMPILE([#include +#include +#ifdef signal +#undef signal +#endif +#ifdef __cplusplus +extern "C" +#endif +void (*signal ()) ();], +[int i;], bash_cv_void_sighandler=yes, bash_cv_void_sighandler=no)])dnl +AC_MSG_RESULT($bash_cv_void_sighandler) +if test $bash_cv_void_sighandler = yes; then +AC_DEFINE(VOID_SIGHANDLER) +fi +]) + +dnl +dnl A signed 16-bit integer quantity +dnl +AC_DEFUN(BASH_TYPE_BITS16_T, +[ +if test "$ac_cv_sizeof_short" = 2; then + AC_CHECK_TYPE(bits16_t, short) +elif test "$ac_cv_sizeof_char" = 2; then + AC_CHECK_TYPE(bits16_t, char) +else + AC_CHECK_TYPE(bits16_t, short) +fi +]) + +dnl +dnl An unsigned 16-bit integer quantity +dnl +AC_DEFUN(BASH_TYPE_U_BITS16_T, +[ +if test "$ac_cv_sizeof_short" = 2; then + AC_CHECK_TYPE(u_bits16_t, unsigned short) +elif test "$ac_cv_sizeof_char" = 2; then + AC_CHECK_TYPE(u_bits16_t, unsigned char) +else + AC_CHECK_TYPE(u_bits16_t, unsigned short) +fi +]) + +dnl +dnl A signed 32-bit integer quantity +dnl +AC_DEFUN(BASH_TYPE_BITS32_T, +[ +if test "$ac_cv_sizeof_int" = 4; then + AC_CHECK_TYPE(bits32_t, int) +elif test "$ac_cv_sizeof_long" = 4; then + AC_CHECK_TYPE(bits32_t, long) +else + AC_CHECK_TYPE(bits32_t, int) +fi +]) + +dnl +dnl An unsigned 32-bit integer quantity +dnl +AC_DEFUN(BASH_TYPE_U_BITS32_T, +[ +if test "$ac_cv_sizeof_int" = 4; then + AC_CHECK_TYPE(u_bits32_t, unsigned int) +elif test "$ac_cv_sizeof_long" = 4; then + AC_CHECK_TYPE(u_bits32_t, unsigned long) +else + AC_CHECK_TYPE(u_bits32_t, unsigned int) +fi +]) + +AC_DEFUN(BASH_TYPE_PTRDIFF_T, +[ +if test "$ac_cv_sizeof_int" = "$ac_cv_sizeof_char_p"; then + AC_CHECK_TYPE(ptrdiff_t, int) +elif test "$ac_cv_sizeof_long" = "$ac_cv_sizeof_char_p"; then + AC_CHECK_TYPE(ptrdiff_t, long) +elif test "$ac_cv_type_long_long" = yes && test "$ac_cv_sizeof_long_long" = "$ac_cv_sizeof_char_p"; then + AC_CHECK_TYPE(ptrdiff_t, [long long]) +else + AC_CHECK_TYPE(ptrdiff_t, int) +fi +]) + +dnl +dnl A signed 64-bit quantity +dnl +AC_DEFUN(BASH_TYPE_BITS64_T, +[ +if test "$ac_cv_sizeof_char_p" = 8; then + AC_CHECK_TYPE(bits64_t, char *) +elif test "$ac_cv_sizeof_double" = 8; then + AC_CHECK_TYPE(bits64_t, double) +elif test -n "$ac_cv_type_long_long" && test "$ac_cv_sizeof_long_long" = 8; then + AC_CHECK_TYPE(bits64_t, [long long]) +elif test "$ac_cv_sizeof_long" = 8; then + AC_CHECK_TYPE(bits64_t, long) +else + AC_CHECK_TYPE(bits64_t, double) +fi +]) + +AC_DEFUN(BASH_TYPE_LONG_LONG, +[ +AC_CACHE_CHECK([for long long], bash_cv_type_long_long, +[AC_TRY_LINK([ +long long ll = 1; int i = 63;], +[ +long long llm = (long long) -1; +return ll << i | ll >> i | llm / ll | llm % ll; +], bash_cv_type_long_long='long long', bash_cv_type_long_long='long')]) +if test "$bash_cv_type_long_long" = 'long long'; then + AC_DEFINE(HAVE_LONG_LONG, 1) +fi +]) + +AC_DEFUN(BASH_TYPE_UNSIGNED_LONG_LONG, +[ +AC_CACHE_CHECK([for unsigned long long], bash_cv_type_unsigned_long_long, +[AC_TRY_LINK([ +unsigned long long ull = 1; int i = 63;], +[ +unsigned long long ullmax = (unsigned long long) -1; +return ull << i | ull >> i | ullmax / ull | ullmax % ull; +], bash_cv_type_unsigned_long_long='unsigned long long', + bash_cv_type_unsigned_long_long='unsigned long')]) +if test "$bash_cv_type_unsigned_long_long" = 'unsigned long long'; then + AC_DEFINE(HAVE_UNSIGNED_LONG_LONG, 1) +fi +]) + +dnl +dnl Type of struct rlimit fields: some systems (OSF/1, NetBSD, RISC/os 5.0) +dnl have a rlim_t, others (4.4BSD based systems) use quad_t, others use +dnl long and still others use int (HP-UX 9.01, SunOS 4.1.3). To simplify +dnl matters, this just checks for rlim_t, quad_t, or long. +dnl +AC_DEFUN(BASH_TYPE_RLIMIT, +[AC_MSG_CHECKING(for size and type of struct rlimit fields) +AC_CACHE_VAL(bash_cv_type_rlimit, +[AC_TRY_COMPILE([#include +#include ], +[rlim_t xxx;], bash_cv_type_rlimit=rlim_t,[ +AC_TRY_RUN([ +#include +#include +#include +main() +{ +#ifdef HAVE_QUAD_T + struct rlimit rl; + if (sizeof(rl.rlim_cur) == sizeof(quad_t)) + exit(0); +#endif + exit(1); +}], bash_cv_type_rlimit=quad_t, bash_cv_type_rlimit=long, + [AC_MSG_WARN(cannot check quad_t if cross compiling -- defaulting to long) + bash_cv_type_rlimit=long])]) +]) +AC_MSG_RESULT($bash_cv_type_rlimit) +if test $bash_cv_type_rlimit = quad_t; then +AC_DEFINE(RLIMTYPE, quad_t) +elif test $bash_cv_type_rlimit = rlim_t; then +AC_DEFINE(RLIMTYPE, rlim_t) +fi +]) + +AC_DEFUN(BASH_FUNC_LSTAT, +[dnl Cannot use AC_CHECK_FUNCS(lstat) because Linux defines lstat() as an +dnl inline function in . +AC_CACHE_CHECK([for lstat], bash_cv_func_lstat, +[AC_TRY_LINK([ +#include +#include +],[ lstat(".",(struct stat *)0); ], +bash_cv_func_lstat=yes, bash_cv_func_lstat=no)]) +if test $bash_cv_func_lstat = yes; then + AC_DEFINE(HAVE_LSTAT) +fi +]) + +AC_DEFUN(BASH_FUNC_INET_ATON, +[ +AC_CACHE_CHECK([for inet_aton], bash_cv_func_inet_aton, +[AC_TRY_LINK([ +#include +#include +#include +struct in_addr ap;], [ inet_aton("127.0.0.1", &ap); ], +bash_cv_func_inet_aton=yes, bash_cv_func_inet_aton=no)]) +if test $bash_cv_func_inet_aton = yes; then + AC_DEFINE(HAVE_INET_ATON) +else + AC_LIBOBJ(inet_aton) +fi +]) + +AC_DEFUN(BASH_FUNC_GETENV, +[AC_MSG_CHECKING(to see if getenv can be redefined) +AC_CACHE_VAL(bash_cv_getenv_redef, +[AC_TRY_RUN([ +#ifdef HAVE_UNISTD_H +# include +#endif +#ifndef __STDC__ +# ifndef const +# define const +# endif +#endif +char * +getenv (name) +#if defined (__linux__) || defined (__bsdi__) || defined (convex) + const char *name; +#else + char const *name; +#endif /* !__linux__ && !__bsdi__ && !convex */ +{ +return "42"; +} +main() +{ +char *s; +/* The next allows this program to run, but does not allow bash to link + when it redefines getenv. I'm not really interested in figuring out + why not. */ +#if defined (NeXT) +exit(1); +#endif +s = getenv("ABCDE"); +exit(s == 0); /* force optimizer to leave getenv in */ +} +], bash_cv_getenv_redef=yes, bash_cv_getenv_redef=no, + [AC_MSG_WARN(cannot check getenv redefinition if cross compiling -- defaulting to yes) + bash_cv_getenv_redef=yes] +)]) +AC_MSG_RESULT($bash_cv_getenv_redef) +if test $bash_cv_getenv_redef = yes; then +AC_DEFINE(CAN_REDEFINE_GETENV) +fi +]) + +# We should check for putenv before calling this +AC_DEFUN(BASH_FUNC_STD_PUTENV, +[ +AC_REQUIRE([AC_HEADER_STDC]) +AC_REQUIRE([AC_C_PROTOTYPES]) +AC_CACHE_CHECK([for standard-conformant putenv declaration], bash_cv_std_putenv, +[AC_TRY_LINK([ +#if STDC_HEADERS +#include +#include +#endif +#ifndef __STDC__ +# ifndef const +# define const +# endif +#endif +#ifdef PROTOTYPES +extern int putenv (char *); +#else +extern int putenv (); +#endif +], +[return (putenv == 0);], +bash_cv_std_putenv=yes, bash_cv_std_putenv=no +)]) +if test $bash_cv_std_putenv = yes; then +AC_DEFINE(HAVE_STD_PUTENV) +fi +]) + +# We should check for unsetenv before calling this +AC_DEFUN(BASH_FUNC_STD_UNSETENV, +[ +AC_REQUIRE([AC_HEADER_STDC]) +AC_REQUIRE([AC_C_PROTOTYPES]) +AC_CACHE_CHECK([for standard-conformant unsetenv declaration], bash_cv_std_unsetenv, +[AC_TRY_LINK([ +#if STDC_HEADERS +#include +#include +#endif +#ifndef __STDC__ +# ifndef const +# define const +# endif +#endif +#ifdef PROTOTYPES +extern int unsetenv (const char *); +#else +extern int unsetenv (); +#endif +], +[return (unsetenv == 0);], +bash_cv_std_unsetenv=yes, bash_cv_std_unsetenv=no +)]) +if test $bash_cv_std_unsetenv = yes; then +AC_DEFINE(HAVE_STD_UNSETENV) +fi +]) + +AC_DEFUN(BASH_FUNC_ULIMIT_MAXFDS, +[AC_MSG_CHECKING(whether ulimit can substitute for getdtablesize) +AC_CACHE_VAL(bash_cv_ulimit_maxfds, +[AC_TRY_RUN([ +main() +{ +long maxfds = ulimit(4, 0L); +exit (maxfds == -1L); +} +], bash_cv_ulimit_maxfds=yes, bash_cv_ulimit_maxfds=no, + [AC_MSG_WARN(cannot check ulimit if cross compiling -- defaulting to no) + bash_cv_ulimit_maxfds=no] +)]) +AC_MSG_RESULT($bash_cv_ulimit_maxfds) +if test $bash_cv_ulimit_maxfds = yes; then +AC_DEFINE(ULIMIT_MAXFDS) +fi +]) + +AC_DEFUN(BASH_FUNC_GETCWD, +[AC_MSG_CHECKING([if getcwd() will dynamically allocate memory]) +AC_CACHE_VAL(bash_cv_getcwd_malloc, +[AC_TRY_RUN([ +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +main() +{ + char *xpwd; + xpwd = getcwd(0, 0); + exit (xpwd == 0); +} +], bash_cv_getcwd_malloc=yes, bash_cv_getcwd_malloc=no, + [AC_MSG_WARN(cannot check whether getcwd allocates memory when cross-compiling -- defaulting to no) + bash_cv_getcwd_malloc=no] +)]) +AC_MSG_RESULT($bash_cv_getcwd_malloc) +if test $bash_cv_getcwd_malloc = no; then +AC_DEFINE(GETCWD_BROKEN) +AC_LIBOBJ(getcwd) +fi +]) + +dnl +dnl This needs BASH_CHECK_SOCKLIB, but since that's not called on every +dnl system, we can't use AC_PREREQ +dnl +AC_DEFUN(BASH_FUNC_GETHOSTBYNAME, +[if test "X$bash_cv_have_gethostbyname" = "X"; then +_bash_needmsg=yes +else +AC_MSG_CHECKING(for gethostbyname in socket library) +_bash_needmsg= +fi +AC_CACHE_VAL(bash_cv_have_gethostbyname, +[AC_TRY_LINK([#include ], +[ struct hostent *hp; + hp = gethostbyname("localhost"); +], bash_cv_have_gethostbyname=yes, bash_cv_have_gethostbyname=no)] +) +if test "X$_bash_needmsg" = Xyes; then + AC_MSG_CHECKING(for gethostbyname in socket library) +fi +AC_MSG_RESULT($bash_cv_have_gethostbyname) +if test "$bash_cv_have_gethostbyname" = yes; then +AC_DEFINE(HAVE_GETHOSTBYNAME) +fi +]) + +AC_DEFUN(BASH_FUNC_FNMATCH_EXTMATCH, +[AC_MSG_CHECKING(if fnmatch does extended pattern matching with FNM_EXTMATCH) +AC_CACHE_VAL(bash_cv_fnm_extmatch, +[AC_TRY_RUN([ +#include + +main() +{ +#ifdef FNM_EXTMATCH + exit (0); +#else + exit (1); +#endif +} +], bash_cv_fnm_extmatch=yes, bash_cv_fnm_extmatch=no, + [AC_MSG_WARN(cannot check FNM_EXTMATCH if cross compiling -- defaulting to no) + bash_cv_fnm_extmatch=no]) +]) +AC_MSG_RESULT($bash_cv_fnm_extmatch) +if test $bash_cv_fnm_extmatch = yes; then +AC_DEFINE(HAVE_LIBC_FNM_EXTMATCH) +fi +]) + +AC_DEFUN(BASH_FUNC_POSIX_SETJMP, +[AC_REQUIRE([BASH_SYS_SIGNAL_VINTAGE]) +AC_MSG_CHECKING(for presence of POSIX-style sigsetjmp/siglongjmp) +AC_CACHE_VAL(bash_cv_func_sigsetjmp, +[AC_TRY_RUN([ +#ifdef HAVE_UNISTD_H +#include +#endif +#include +#include +#include + +main() +{ +#if !defined (_POSIX_VERSION) || !defined (HAVE_POSIX_SIGNALS) +exit (1); +#else + +int code; +sigset_t set, oset; +sigjmp_buf xx; + +/* get the mask */ +sigemptyset(&set); +sigemptyset(&oset); +sigprocmask(SIG_BLOCK, (sigset_t *)NULL, &set); +sigprocmask(SIG_BLOCK, (sigset_t *)NULL, &oset); + +/* save it */ +code = sigsetjmp(xx, 1); +if (code) + exit(0); /* could get sigmask and compare to oset here. */ + +/* change it */ +sigaddset(&set, SIGINT); +sigprocmask(SIG_BLOCK, &set, (sigset_t *)NULL); + +/* and siglongjmp */ +siglongjmp(xx, 10); +exit(1); +#endif +}], bash_cv_func_sigsetjmp=present, bash_cv_func_sigsetjmp=missing, + [AC_MSG_WARN(cannot check for sigsetjmp/siglongjmp if cross-compiling -- defaulting to missing) + bash_cv_func_sigsetjmp=missing] +)]) +AC_MSG_RESULT($bash_cv_func_sigsetjmp) +if test $bash_cv_func_sigsetjmp = present; then +AC_DEFINE(HAVE_POSIX_SIGSETJMP) +fi +]) + +AC_DEFUN(BASH_FUNC_STRCOLL, +[ +AC_MSG_CHECKING(whether or not strcoll and strcmp differ) +AC_CACHE_VAL(bash_cv_func_strcoll_broken, +[AC_TRY_RUN([ +#include +#if defined (HAVE_LOCALE_H) +#include +#endif + +main(c, v) +int c; +char *v[]; +{ + int r1, r2; + char *deflocale, *defcoll; + +#ifdef HAVE_SETLOCALE + deflocale = setlocale(LC_ALL, ""); + defcoll = setlocale(LC_COLLATE, ""); +#endif + +#ifdef HAVE_STRCOLL + /* These two values are taken from tests/glob-test. */ + r1 = strcoll("abd", "aXd"); +#else + r1 = 0; +#endif + r2 = strcmp("abd", "aXd"); + + /* These two should both be greater than 0. It is permissible for + a system to return different values, as long as the sign is the + same. */ + + /* Exit with 1 (failure) if these two values are both > 0, since + this tests whether strcoll(3) is broken with respect to strcmp(3) + in the default locale. */ + exit (r1 > 0 && r2 > 0); +} +], bash_cv_func_strcoll_broken=yes, bash_cv_func_strcoll_broken=no, + [AC_MSG_WARN(cannot check strcoll if cross compiling -- defaulting to no) + bash_cv_func_strcoll_broken=no] +)]) +AC_MSG_RESULT($bash_cv_func_strcoll_broken) +if test $bash_cv_func_strcoll_broken = yes; then +AC_DEFINE(STRCOLL_BROKEN) +fi +]) + +AC_DEFUN(BASH_FUNC_PRINTF_A_FORMAT, +[AC_MSG_CHECKING([for printf floating point output in hex notation]) +AC_CACHE_VAL(bash_cv_printf_a_format, +[AC_TRY_RUN([ +#include +#include + +int +main() +{ + double y = 0.0; + char abuf[1024]; + + sprintf(abuf, "%A", y); + exit(strchr(abuf, 'P') == (char *)0); +} +], bash_cv_printf_a_format=yes, bash_cv_printf_a_format=no, + [AC_MSG_WARN(cannot check printf if cross compiling -- defaulting to no) + bash_cv_printf_a_format=no] +)]) +AC_MSG_RESULT($bash_cv_printf_a_format) +if test $bash_cv_printf_a_format = yes; then +AC_DEFINE(HAVE_PRINTF_A_FORMAT) +fi +]) + +AC_DEFUN(BASH_STRUCT_TERMIOS_LDISC, +[ +AC_CHECK_MEMBER(struct termios.c_line, AC_DEFINE(TERMIOS_LDISC), ,[ +#include +#include +]) +]) + +AC_DEFUN(BASH_STRUCT_TERMIO_LDISC, +[ +AC_CHECK_MEMBER(struct termio.c_line, AC_DEFINE(TERMIO_LDISC), ,[ +#include +#include +]) +]) + +dnl +dnl Like AC_STRUCT_ST_BLOCKS, but doesn't muck with LIBOBJS +dnl +dnl sets bash_cv_struct_stat_st_blocks +dnl +dnl unused for now; we'll see how AC_CHECK_MEMBERS works +dnl +AC_DEFUN(BASH_STRUCT_ST_BLOCKS, +[ +AC_MSG_CHECKING([for struct stat.st_blocks]) +AC_CACHE_VAL(bash_cv_struct_stat_st_blocks, +[AC_TRY_COMPILE( +[ +#include +#include +], +[ +main() +{ +static struct stat a; +if (a.st_blocks) return 0; +return 0; +} +], bash_cv_struct_stat_st_blocks=yes, bash_cv_struct_stat_st_blocks=no) +]) +AC_MSG_RESULT($bash_cv_struct_stat_st_blocks) +if test "$bash_cv_struct_stat_st_blocks" = "yes"; then +AC_DEFINE(HAVE_STRUCT_STAT_ST_BLOCKS) +fi +]) + +AC_DEFUN(BASH_CHECK_LIB_TERMCAP, +[ +if test "X$bash_cv_termcap_lib" = "X"; then +_bash_needmsg=yes +else +AC_MSG_CHECKING(which library has the termcap functions) +_bash_needmsg= +fi +AC_CACHE_VAL(bash_cv_termcap_lib, +[AC_CHECK_FUNC(tgetent, bash_cv_termcap_lib=libc, + [AC_CHECK_LIB(termcap, tgetent, bash_cv_termcap_lib=libtermcap, + [AC_CHECK_LIB(tinfo, tgetent, bash_cv_termcap_lib=libtinfo, + [AC_CHECK_LIB(curses, tgetent, bash_cv_termcap_lib=libcurses, + [AC_CHECK_LIB(ncurses, tgetent, bash_cv_termcap_lib=libncurses, + bash_cv_termcap_lib=gnutermcap)])])])])]) +if test "X$_bash_needmsg" = "Xyes"; then +AC_MSG_CHECKING(which library has the termcap functions) +fi +AC_MSG_RESULT(using $bash_cv_termcap_lib) +if test $bash_cv_termcap_lib = gnutermcap && test -z "$prefer_curses"; then +LDFLAGS="$LDFLAGS -L./lib/termcap" +TERMCAP_LIB="./lib/termcap/libtermcap.a" +TERMCAP_DEP="./lib/termcap/libtermcap.a" +elif test $bash_cv_termcap_lib = libtermcap && test -z "$prefer_curses"; then +TERMCAP_LIB=-ltermcap +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libtinfo; then +TERMCAP_LIB=-ltinfo +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libncurses; then +TERMCAP_LIB=-lncurses +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libc; then +TERMCAP_LIB= +TERMCAP_DEP= +else +TERMCAP_LIB=-lcurses +TERMCAP_DEP= +fi +]) + +dnl +dnl Check for the presence of getpeername in libsocket. +dnl If libsocket is present, check for libnsl and add it to LIBS if +dnl it's there, since most systems with libsocket require linking +dnl with libnsl as well. This should only be called if getpeername +dnl was not found in libc. +dnl +dnl NOTE: IF WE FIND GETPEERNAME, WE ASSUME THAT WE HAVE BIND/CONNECT +dnl AS WELL +dnl +AC_DEFUN(BASH_CHECK_LIB_SOCKET, +[ +if test "X$bash_cv_have_socklib" = "X"; then +_bash_needmsg= +else +AC_MSG_CHECKING(for socket library) +_bash_needmsg=yes +fi +AC_CACHE_VAL(bash_cv_have_socklib, +[AC_CHECK_LIB(socket, getpeername, + bash_cv_have_socklib=yes, bash_cv_have_socklib=no, -lnsl)]) +if test "X$_bash_needmsg" = Xyes; then + AC_MSG_RESULT($bash_cv_have_socklib) + _bash_needmsg= +fi +if test $bash_cv_have_socklib = yes; then + # check for libnsl, add it to LIBS if present + if test "X$bash_cv_have_libnsl" = "X"; then + _bash_needmsg= + else + AC_MSG_CHECKING(for libnsl) + _bash_needmsg=yes + fi + AC_CACHE_VAL(bash_cv_have_libnsl, + [AC_CHECK_LIB(nsl, t_open, + bash_cv_have_libnsl=yes, bash_cv_have_libnsl=no)]) + if test "X$_bash_needmsg" = Xyes; then + AC_MSG_RESULT($bash_cv_have_libnsl) + _bash_needmsg= + fi + if test $bash_cv_have_libnsl = yes; then + LIBS="-lsocket -lnsl $LIBS" + else + LIBS="-lsocket $LIBS" + fi + AC_DEFINE(HAVE_LIBSOCKET) + AC_DEFINE(HAVE_GETPEERNAME) +fi +]) + +AC_DEFUN(BASH_STRUCT_DIRENT_D_INO, +[AC_REQUIRE([AC_HEADER_DIRENT]) +AC_MSG_CHECKING(for struct dirent.d_ino) +AC_CACHE_VAL(bash_cv_dirent_has_dino, +[AC_TRY_COMPILE([ +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ +],[ +struct dirent d; int z; z = d.d_ino; +], bash_cv_dirent_has_dino=yes, bash_cv_dirent_has_dino=no)]) +AC_MSG_RESULT($bash_cv_dirent_has_dino) +if test $bash_cv_dirent_has_dino = yes; then +AC_DEFINE(HAVE_STRUCT_DIRENT_D_INO) +fi +]) + +AC_DEFUN(BASH_STRUCT_DIRENT_D_FILENO, +[AC_REQUIRE([AC_HEADER_DIRENT]) +AC_MSG_CHECKING(for struct dirent.d_fileno) +AC_CACHE_VAL(bash_cv_dirent_has_d_fileno, +[AC_TRY_COMPILE([ +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ +],[ +struct dirent d; int z; z = d.d_fileno; +], bash_cv_dirent_has_d_fileno=yes, bash_cv_dirent_has_d_fileno=no)]) +AC_MSG_RESULT($bash_cv_dirent_has_d_fileno) +if test $bash_cv_dirent_has_d_fileno = yes; then +AC_DEFINE(HAVE_STRUCT_DIRENT_D_FILENO) +fi +]) + +AC_DEFUN(BASH_STRUCT_DIRENT_D_NAMLEN, +[AC_REQUIRE([AC_HEADER_DIRENT]) +AC_MSG_CHECKING(for struct dirent.d_namlen) +AC_CACHE_VAL(bash_cv_dirent_has_d_namlen, +[AC_TRY_COMPILE([ +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ +],[ +struct dirent d; int z; z = d.d_namlen; +], bash_cv_dirent_has_d_namlen=yes, bash_cv_dirent_has_d_namlen=no)]) +AC_MSG_RESULT($bash_cv_dirent_has_d_namlen) +if test $bash_cv_dirent_has_d_namlen = yes; then +AC_DEFINE(HAVE_STRUCT_DIRENT_D_NAMLEN) +fi +]) + +AC_DEFUN(BASH_STRUCT_TIMEVAL, +[AC_MSG_CHECKING(for struct timeval in sys/time.h and time.h) +AC_CACHE_VAL(bash_cv_struct_timeval, +[ +AC_EGREP_HEADER(struct timeval, sys/time.h, + bash_cv_struct_timeval=yes, + AC_EGREP_HEADER(struct timeval, time.h, + bash_cv_struct_timeval=yes, + bash_cv_struct_timeval=no)) +]) +AC_MSG_RESULT($bash_cv_struct_timeval) +if test $bash_cv_struct_timeval = yes; then + AC_DEFINE(HAVE_TIMEVAL) +fi +]) + +AC_DEFUN(BASH_STRUCT_TIMEZONE, +[AC_MSG_CHECKING(for struct timezone in sys/time.h and time.h) +AC_CACHE_VAL(bash_cv_struct_timezone, +[ +AC_EGREP_HEADER(struct timezone, sys/time.h, + bash_cv_struct_timezone=yes, + AC_EGREP_HEADER(struct timezone, time.h, + bash_cv_struct_timezone=yes, + bash_cv_struct_timezone=no)) +]) +AC_MSG_RESULT($bash_cv_struct_timezone) +if test $bash_cv_struct_timezone = yes; then + AC_DEFINE(HAVE_STRUCT_TIMEZONE) +fi +]) + +AC_DEFUN(BASH_STRUCT_WINSIZE, +[AC_MSG_CHECKING(for struct winsize in sys/ioctl.h and termios.h) +AC_CACHE_VAL(bash_cv_struct_winsize_header, +[AC_TRY_COMPILE([#include +#include ], [struct winsize x;], + bash_cv_struct_winsize_header=ioctl_h, + [AC_TRY_COMPILE([#include +#include ], [struct winsize x;], + bash_cv_struct_winsize_header=termios_h, bash_cv_struct_winsize_header=other) +])]) +if test $bash_cv_struct_winsize_header = ioctl_h; then + AC_MSG_RESULT(sys/ioctl.h) + AC_DEFINE(STRUCT_WINSIZE_IN_SYS_IOCTL) +elif test $bash_cv_struct_winsize_header = termios_h; then + AC_MSG_RESULT(termios.h) + AC_DEFINE(STRUCT_WINSIZE_IN_TERMIOS) +else + AC_MSG_RESULT(not found) +fi +]) + +dnl Check type of signal routines (posix, 4.2bsd, 4.1bsd or v7) +AC_DEFUN(BASH_SYS_SIGNAL_VINTAGE, +[AC_REQUIRE([AC_TYPE_SIGNAL]) +AC_MSG_CHECKING(for type of signal functions) +AC_CACHE_VAL(bash_cv_signal_vintage, +[ + AC_TRY_LINK([#include ],[ + sigset_t ss; + struct sigaction sa; + sigemptyset(&ss); sigsuspend(&ss); + sigaction(SIGINT, &sa, (struct sigaction *) 0); + sigprocmask(SIG_BLOCK, &ss, (sigset_t *) 0); + ], bash_cv_signal_vintage=posix, + [ + AC_TRY_LINK([#include ], [ + int mask = sigmask(SIGINT); + sigsetmask(mask); sigblock(mask); sigpause(mask); + ], bash_cv_signal_vintage=4.2bsd, + [ + AC_TRY_LINK([ + #include + RETSIGTYPE foo() { }], [ + int mask = sigmask(SIGINT); + sigset(SIGINT, foo); sigrelse(SIGINT); + sighold(SIGINT); sigpause(SIGINT); + ], bash_cv_signal_vintage=svr3, bash_cv_signal_vintage=v7 + )] + )] +) +]) +AC_MSG_RESULT($bash_cv_signal_vintage) +if test "$bash_cv_signal_vintage" = posix; then +AC_DEFINE(HAVE_POSIX_SIGNALS) +elif test "$bash_cv_signal_vintage" = "4.2bsd"; then +AC_DEFINE(HAVE_BSD_SIGNALS) +elif test "$bash_cv_signal_vintage" = svr3; then +AC_DEFINE(HAVE_USG_SIGHOLD) +fi +]) + +dnl Check if the pgrp of setpgrp() can't be the pid of a zombie process. +AC_DEFUN(BASH_SYS_PGRP_SYNC, +[AC_REQUIRE([AC_FUNC_GETPGRP]) +AC_MSG_CHECKING(whether pgrps need synchronization) +AC_CACHE_VAL(bash_cv_pgrp_pipe, +[AC_TRY_RUN([ +#ifdef HAVE_UNISTD_H +# include +#endif +main() +{ +# ifdef GETPGRP_VOID +# define getpgID() getpgrp() +# else +# define getpgID() getpgrp(0) +# define setpgid(x,y) setpgrp(x,y) +# endif + int pid1, pid2, fds[2]; + int status; + char ok; + + switch (pid1 = fork()) { + case -1: + exit(1); + case 0: + setpgid(0, getpid()); + exit(0); + } + setpgid(pid1, pid1); + + sleep(2); /* let first child die */ + + if (pipe(fds) < 0) + exit(2); + + switch (pid2 = fork()) { + case -1: + exit(3); + case 0: + setpgid(0, pid1); + ok = getpgID() == pid1; + write(fds[1], &ok, 1); + exit(0); + } + setpgid(pid2, pid1); + + close(fds[1]); + if (read(fds[0], &ok, 1) != 1) + exit(4); + wait(&status); + wait(&status); + exit(ok ? 0 : 5); +} +], bash_cv_pgrp_pipe=no,bash_cv_pgrp_pipe=yes, + [AC_MSG_WARN(cannot check pgrp synchronization if cross compiling -- defaulting to no) + bash_cv_pgrp_pipe=no]) +]) +AC_MSG_RESULT($bash_cv_pgrp_pipe) +if test $bash_cv_pgrp_pipe = yes; then +AC_DEFINE(PGRP_PIPE) +fi +]) + +AC_DEFUN(BASH_SYS_REINSTALL_SIGHANDLERS, +[AC_REQUIRE([AC_TYPE_SIGNAL]) +AC_REQUIRE([BASH_SYS_SIGNAL_VINTAGE]) +AC_MSG_CHECKING([if signal handlers must be reinstalled when invoked]) +AC_CACHE_VAL(bash_cv_must_reinstall_sighandlers, +[AC_TRY_RUN([ +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +typedef RETSIGTYPE sigfunc(); + +int nsigint; + +#ifdef HAVE_POSIX_SIGNALS +sigfunc * +set_signal_handler(sig, handler) + int sig; + sigfunc *handler; +{ + struct sigaction act, oact; + act.sa_handler = handler; + act.sa_flags = 0; + sigemptyset (&act.sa_mask); + sigemptyset (&oact.sa_mask); + sigaction (sig, &act, &oact); + return (oact.sa_handler); +} +#else +#define set_signal_handler(s, h) signal(s, h) +#endif + +RETSIGTYPE +sigint(s) +int s; +{ + nsigint++; +} + +main() +{ + nsigint = 0; + set_signal_handler(SIGINT, sigint); + kill((int)getpid(), SIGINT); + kill((int)getpid(), SIGINT); + exit(nsigint != 2); +} +], bash_cv_must_reinstall_sighandlers=no, bash_cv_must_reinstall_sighandlers=yes, + [AC_MSG_WARN(cannot check signal handling if cross compiling -- defaulting to no) + bash_cv_must_reinstall_sighandlers=no] +)]) +AC_MSG_RESULT($bash_cv_must_reinstall_sighandlers) +if test $bash_cv_must_reinstall_sighandlers = yes; then +AC_DEFINE(MUST_REINSTALL_SIGHANDLERS) +fi +]) + +dnl check that some necessary job control definitions are present +AC_DEFUN(BASH_SYS_JOB_CONTROL_MISSING, +[AC_REQUIRE([BASH_SYS_SIGNAL_VINTAGE]) +AC_MSG_CHECKING(for presence of necessary job control definitions) +AC_CACHE_VAL(bash_cv_job_control_missing, +[AC_TRY_RUN([ +#include +#ifdef HAVE_SYS_WAIT_H +#include +#endif +#ifdef HAVE_UNISTD_H +#include +#endif +#include + +/* Add more tests in here as appropriate. */ +main() +{ +/* signal type */ +#if !defined (HAVE_POSIX_SIGNALS) && !defined (HAVE_BSD_SIGNALS) +exit(1); +#endif + +/* signals and tty control. */ +#if !defined (SIGTSTP) || !defined (SIGSTOP) || !defined (SIGCONT) +exit (1); +#endif + +/* process control */ +#if !defined (WNOHANG) || !defined (WUNTRACED) +exit(1); +#endif + +/* Posix systems have tcgetpgrp and waitpid. */ +#if defined (_POSIX_VERSION) && !defined (HAVE_TCGETPGRP) +exit(1); +#endif + +#if defined (_POSIX_VERSION) && !defined (HAVE_WAITPID) +exit(1); +#endif + +/* Other systems have TIOCSPGRP/TIOCGPRGP and wait3. */ +#if !defined (_POSIX_VERSION) && !defined (HAVE_WAIT3) +exit(1); +#endif + +exit(0); +}], bash_cv_job_control_missing=present, bash_cv_job_control_missing=missing, + [AC_MSG_WARN(cannot check job control if cross-compiling -- defaulting to missing) + bash_cv_job_control_missing=missing] +)]) +AC_MSG_RESULT($bash_cv_job_control_missing) +if test $bash_cv_job_control_missing = missing; then +AC_DEFINE(JOB_CONTROL_MISSING) +fi +]) + +dnl check whether named pipes are present +dnl this requires a previous check for mkfifo, but that is awkward to specify +AC_DEFUN(BASH_SYS_NAMED_PIPES, +[AC_MSG_CHECKING(for presence of named pipes) +AC_CACHE_VAL(bash_cv_sys_named_pipes, +[AC_TRY_RUN([ +#include +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +/* Add more tests in here as appropriate. */ +main() +{ +int fd, err; + +#if defined (HAVE_MKFIFO) +exit (0); +#endif + +#if !defined (S_IFIFO) && (defined (_POSIX_VERSION) && !defined (S_ISFIFO)) +exit (1); +#endif + +#if defined (NeXT) +exit (1); +#endif +err = mkdir("/tmp/bash-aclocal", 0700); +if (err < 0) { + perror ("mkdir"); + exit(1); +} +fd = mknod ("/tmp/bash-aclocal/sh-np-autoconf", 0666 | S_IFIFO, 0); +if (fd == -1) { + rmdir ("/tmp/bash-aclocal"); + exit (1); +} +close(fd); +unlink ("/tmp/bash-aclocal/sh-np-autoconf"); +rmdir ("/tmp/bash-aclocal"); +exit(0); +}], bash_cv_sys_named_pipes=present, bash_cv_sys_named_pipes=missing, + [AC_MSG_WARN(cannot check for named pipes if cross-compiling -- defaulting to missing) + bash_cv_sys_named_pipes=missing] +)]) +AC_MSG_RESULT($bash_cv_sys_named_pipes) +if test $bash_cv_sys_named_pipes = missing; then +AC_DEFINE(NAMED_PIPES_MISSING) +fi +]) + +AC_DEFUN(BASH_SYS_DEFAULT_MAIL_DIR, +[AC_MSG_CHECKING(for default mail directory) +AC_CACHE_VAL(bash_cv_mail_dir, +[if test -d /var/mail; then + bash_cv_mail_dir=/var/mail + elif test -d /var/spool/mail; then + bash_cv_mail_dir=/var/spool/mail + elif test -d /usr/mail; then + bash_cv_mail_dir=/usr/mail + elif test -d /usr/spool/mail; then + bash_cv_mail_dir=/usr/spool/mail + else + bash_cv_mail_dir=unknown + fi +]) +AC_MSG_RESULT($bash_cv_mail_dir) +AC_DEFINE_UNQUOTED(DEFAULT_MAIL_DIRECTORY, "$bash_cv_mail_dir") +]) + +AC_DEFUN(BASH_HAVE_TIOCGWINSZ, +[AC_MSG_CHECKING(for TIOCGWINSZ in sys/ioctl.h) +AC_CACHE_VAL(bash_cv_tiocgwinsz_in_ioctl, +[AC_TRY_COMPILE([#include +#include ], [int x = TIOCGWINSZ;], + bash_cv_tiocgwinsz_in_ioctl=yes,bash_cv_tiocgwinsz_in_ioctl=no)]) +AC_MSG_RESULT($bash_cv_tiocgwinsz_in_ioctl) +if test $bash_cv_tiocgwinsz_in_ioctl = yes; then +AC_DEFINE(GWINSZ_IN_SYS_IOCTL) +fi +]) + +AC_DEFUN(BASH_HAVE_TIOCSTAT, +[AC_MSG_CHECKING(for TIOCSTAT in sys/ioctl.h) +AC_CACHE_VAL(bash_cv_tiocstat_in_ioctl, +[AC_TRY_COMPILE([#include +#include ], [int x = TIOCSTAT;], + bash_cv_tiocstat_in_ioctl=yes,bash_cv_tiocstat_in_ioctl=no)]) +AC_MSG_RESULT($bash_cv_tiocstat_in_ioctl) +if test $bash_cv_tiocstat_in_ioctl = yes; then +AC_DEFINE(TIOCSTAT_IN_SYS_IOCTL) +fi +]) + +AC_DEFUN(BASH_HAVE_FIONREAD, +[AC_MSG_CHECKING(for FIONREAD in sys/ioctl.h) +AC_CACHE_VAL(bash_cv_fionread_in_ioctl, +[AC_TRY_COMPILE([#include +#include ], [int x = FIONREAD;], + bash_cv_fionread_in_ioctl=yes,bash_cv_fionread_in_ioctl=no)]) +AC_MSG_RESULT($bash_cv_fionread_in_ioctl) +if test $bash_cv_fionread_in_ioctl = yes; then +AC_DEFINE(FIONREAD_IN_SYS_IOCTL) +fi +]) + +dnl +dnl See if speed_t is declared in . Some versions of linux +dnl require a definition of speed_t each time is included, +dnl but you can only get speed_t if you include (on some +dnl versions) or (on others). +dnl +AC_DEFUN(BASH_CHECK_SPEED_T, +[AC_MSG_CHECKING(for speed_t in sys/types.h) +AC_CACHE_VAL(bash_cv_speed_t_in_sys_types, +[AC_TRY_COMPILE([#include ], [speed_t x;], + bash_cv_speed_t_in_sys_types=yes,bash_cv_speed_t_in_sys_types=no)]) +AC_MSG_RESULT($bash_cv_speed_t_in_sys_types) +if test $bash_cv_speed_t_in_sys_types = yes; then +AC_DEFINE(SPEED_T_IN_SYS_TYPES) +fi +]) + +AC_DEFUN(BASH_CHECK_GETPW_FUNCS, +[AC_MSG_CHECKING(whether getpw functions are declared in pwd.h) +AC_CACHE_VAL(bash_cv_getpw_declared, +[AC_EGREP_CPP(getpwuid, +[ +#include +#ifdef HAVE_UNISTD_H +# include +#endif +#include +], +bash_cv_getpw_declared=yes,bash_cv_getpw_declared=no)]) +AC_MSG_RESULT($bash_cv_getpw_declared) +if test $bash_cv_getpw_declared = yes; then +AC_DEFINE(HAVE_GETPW_DECLS) +fi +]) + +AC_DEFUN(BASH_CHECK_DEV_FD, +[AC_MSG_CHECKING(whether /dev/fd is available) +AC_CACHE_VAL(bash_cv_dev_fd, +[if test -d /dev/fd && test -r /dev/fd/0 < /dev/null; then +# check for systems like FreeBSD 5 that only provide /dev/fd/[012] + exec 3<&0 + if test -r /dev/fd/3; then + bash_cv_dev_fd=standard + else + bash_cv_dev_fd=absent + fi + exec 3<&- + elif test -d /proc/self/fd && test -r /proc/self/fd/0 < /dev/null; then + bash_cv_dev_fd=whacky + else + bash_cv_dev_fd=absent + fi +]) +AC_MSG_RESULT($bash_cv_dev_fd) +if test $bash_cv_dev_fd = "standard"; then + AC_DEFINE(HAVE_DEV_FD) + AC_DEFINE(DEV_FD_PREFIX, "/dev/fd/") +elif test $bash_cv_dev_fd = "whacky"; then + AC_DEFINE(HAVE_DEV_FD) + AC_DEFINE(DEV_FD_PREFIX, "/proc/self/fd/") +fi +]) + +AC_DEFUN(BASH_CHECK_DEV_STDIN, +[AC_MSG_CHECKING(whether /dev/stdin stdout stderr are available) +AC_CACHE_VAL(bash_cv_dev_stdin, +[if test -d /dev/fd && test -r /dev/stdin < /dev/null; then + bash_cv_dev_stdin=present + elif test -d /proc/self/fd && test -r /dev/stdin < /dev/null; then + bash_cv_dev_stdin=present + else + bash_cv_dev_stdin=absent + fi +]) +AC_MSG_RESULT($bash_cv_dev_stdin) +if test $bash_cv_dev_stdin = "present"; then + AC_DEFINE(HAVE_DEV_STDIN) +fi +]) + +dnl +dnl Check if HPUX needs _KERNEL defined for RLIMIT_* definitions +dnl +AC_DEFUN(BASH_CHECK_KERNEL_RLIMIT, +[AC_MSG_CHECKING([whether $host_os needs _KERNEL for RLIMIT defines]) +AC_CACHE_VAL(bash_cv_kernel_rlimit, +[AC_TRY_COMPILE([ +#include +#include +], +[ + int f; + f = RLIMIT_DATA; +], bash_cv_kernel_rlimit=no, +[AC_TRY_COMPILE([ +#include +#define _KERNEL +#include +#undef _KERNEL +], +[ + int f; + f = RLIMIT_DATA; +], bash_cv_kernel_rlimit=yes, bash_cv_kernel_rlimit=no)] +)]) +AC_MSG_RESULT($bash_cv_kernel_rlimit) +if test $bash_cv_kernel_rlimit = yes; then +AC_DEFINE(RLIMIT_NEEDS_KERNEL) +fi +]) + +dnl +dnl Check for 64-bit off_t -- used for malloc alignment +dnl +dnl C does not allow duplicate case labels, so the compile will fail if +dnl sizeof(off_t) is > 4. +dnl +AC_DEFUN(BASH_CHECK_OFF_T_64, +[AC_CACHE_CHECK(for 64-bit off_t, bash_cv_off_t_64, +AC_TRY_COMPILE([ +#ifdef HAVE_UNISTD_H +#include +#endif +#include +],[ +switch (0) case 0: case (sizeof (off_t) <= 4):; +], bash_cv_off_t_64=no, bash_cv_off_t_64=yes)) +if test $bash_cv_off_t_64 = yes; then + AC_DEFINE(HAVE_OFF_T_64) +fi]) + +AC_DEFUN(BASH_CHECK_RTSIGS, +[AC_MSG_CHECKING(for unusable real-time signals due to large values) +AC_CACHE_VAL(bash_cv_unusable_rtsigs, +[AC_TRY_RUN([ +#include +#include + +#ifndef NSIG +# define NSIG 64 +#endif + +main () +{ + int n_sigs = 2 * NSIG; +#ifdef SIGRTMIN + int rtmin = SIGRTMIN; +#else + int rtmin = 0; +#endif + + exit(rtmin < n_sigs); +}], bash_cv_unusable_rtsigs=yes, bash_cv_unusable_rtsigs=no, + [AC_MSG_WARN(cannot check real-time signals if cross compiling -- defaulting to yes) + bash_cv_unusable_rtsigs=yes] +)]) +AC_MSG_RESULT($bash_cv_unusable_rtsigs) +if test $bash_cv_unusable_rtsigs = yes; then +AC_DEFINE(UNUSABLE_RT_SIGNALS) +fi +]) + +dnl +dnl check for availability of multibyte characters and functions +dnl +AC_DEFUN(BASH_CHECK_MULTIBYTE, +[ +AC_CHECK_HEADERS(wctype.h) +AC_CHECK_HEADERS(wchar.h) +AC_CHECK_HEADERS(langinfo.h) + +AC_CHECK_FUNC(mbsrtowcs, AC_DEFINE(HAVE_MBSRTOWCS)) +AC_CHECK_FUNC(mbrtowc, AC_DEFINE(HAVE_MBRTOWC)) +AC_CHECK_FUNC(mbrlen, AC_DEFINE(HAVE_MBRLEN)) +AC_CHECK_FUNC(wctomb, AC_DEFINE(HAVE_WCTOMB)) +AC_CHECK_FUNC(wcwidth, AC_DEFINE(HAVE_WCWIDTH)) +AC_CHECK_FUNC(wcsdup, AC_DEFINE(HAVE_WCSDUP)) + +if test "$ac_cv_func_wcwidth" = no && test "$ac_cv_header_wchar_h" = yes; then + WCWIDTH_OBJ=wcwidth.o +else + WCWIDTH_OBJ= +fi +AC_SUBST(WCWIDTH_OBJ) + +AC_CACHE_CHECK([for mbstate_t], bash_cv_have_mbstate_t, +[AC_TRY_COMPILE([ +#include ], [ + mbstate_t ps; + mbstate_t *psp; + psp = (mbstate_t *)0; +], bash_cv_have_mbstate_t=yes, bash_cv_have_mbstate_t=no)]) +if test $bash_cv_have_mbstate_t = yes; then + AC_DEFINE(HAVE_MBSTATE_T) +fi + +AC_CACHE_CHECK([for nl_langinfo and CODESET], bash_cv_langinfo_codeset, +[AC_TRY_LINK( +[#include ], +[char* cs = nl_langinfo(CODESET);], +bash_cv_langinfo_codeset=yes, bash_cv_langinfo_codeset=no)]) +if test $bash_cv_langinfo_codeset = yes; then + AC_DEFINE(HAVE_LANGINFO_CODESET) +fi + +]) + +dnl need: prefix exec_prefix libdir includedir CC TERMCAP_LIB +dnl require: +dnl AC_PROG_CC +dnl BASH_CHECK_LIB_TERMCAP + +AC_DEFUN(RL_LIB_READLINE_VERSION, +[ +AC_REQUIRE([BASH_CHECK_LIB_TERMCAP]) + +AC_MSG_CHECKING([version of installed readline library]) + +# What a pain in the ass this is. + +# save cpp and ld options +_save_CFLAGS="$CFLAGS" +_save_LDFLAGS="$LDFLAGS" +_save_LIBS="$LIBS" + +# Don't set ac_cv_rl_prefix if the caller has already assigned a value. This +# allows the caller to do something like $_rl_prefix=$withval if the user +# specifies --with-installed-readline=PREFIX as an argument to configure + +if test -z "$ac_cv_rl_prefix"; then +test "x$prefix" = xNONE && ac_cv_rl_prefix=$ac_default_prefix || ac_cv_rl_prefix=${prefix} +fi + +eval ac_cv_rl_includedir=${ac_cv_rl_prefix}/include +eval ac_cv_rl_libdir=${ac_cv_rl_prefix}/lib + +LIBS="$LIBS -lreadline ${TERMCAP_LIB}" +CFLAGS="$CFLAGS -I${ac_cv_rl_includedir}" +LDFLAGS="$LDFLAGS -L${ac_cv_rl_libdir}" + +AC_CACHE_VAL(ac_cv_rl_version, +[AC_TRY_RUN([ +#include +#include + +extern int rl_gnu_readline_p; + +main() +{ + FILE *fp; + fp = fopen("conftest.rlv", "w"); + if (fp == 0) + exit(1); + if (rl_gnu_readline_p != 1) + fprintf(fp, "0.0\n"); + else + fprintf(fp, "%s\n", rl_library_version ? rl_library_version : "0.0"); + fclose(fp); + exit(0); +} +], +ac_cv_rl_version=`cat conftest.rlv`, +ac_cv_rl_version='0.0', +ac_cv_rl_version='4.2')]) + +CFLAGS="$_save_CFLAGS" +LDFLAGS="$_save_LDFLAGS" +LIBS="$_save_LIBS" + +RL_MAJOR=0 +RL_MINOR=0 + +# ( +case "$ac_cv_rl_version" in +2*|3*|4*|5*|6*|7*|8*|9*) + RL_MAJOR=`echo $ac_cv_rl_version | sed 's:\..*$::'` + RL_MINOR=`echo $ac_cv_rl_version | sed -e 's:^.*\.::' -e 's:[[a-zA-Z]]*$::'` + ;; +esac + +# ((( +case $RL_MAJOR in +[[0-9][0-9]]) _RL_MAJOR=$RL_MAJOR ;; +[[0-9]]) _RL_MAJOR=0$RL_MAJOR ;; +*) _RL_MAJOR=00 ;; +esac + +# ((( +case $RL_MINOR in +[[0-9][0-9]]) _RL_MINOR=$RL_MINOR ;; +[[0-9]]) _RL_MINOR=0$RL_MINOR ;; +*) _RL_MINOR=00 ;; +esac + +RL_VERSION="0x${_RL_MAJOR}${_RL_MINOR}" + +# Readline versions greater than 4.2 have these defines in readline.h + +if test $ac_cv_rl_version = '0.0' ; then + AC_MSG_WARN([Could not test version of installed readline library.]) +elif test $RL_MAJOR -gt 4 || { test $RL_MAJOR = 4 && test $RL_MINOR -gt 2 ; } ; then + # set these for use by the caller + RL_PREFIX=$ac_cv_rl_prefix + RL_LIBDIR=$ac_cv_rl_libdir + RL_INCLUDEDIR=$ac_cv_rl_includedir + AC_MSG_RESULT($ac_cv_rl_version) +else + +AC_DEFINE_UNQUOTED(RL_READLINE_VERSION, $RL_VERSION, [encoded version of the installed readline library]) +AC_DEFINE_UNQUOTED(RL_VERSION_MAJOR, $RL_MAJOR, [major version of installed readline library]) +AC_DEFINE_UNQUOTED(RL_VERSION_MINOR, $RL_MINOR, [minor version of installed readline library]) + +AC_SUBST(RL_VERSION) +AC_SUBST(RL_MAJOR) +AC_SUBST(RL_MINOR) + +# set these for use by the caller +RL_PREFIX=$ac_cv_rl_prefix +RL_LIBDIR=$ac_cv_rl_libdir +RL_INCLUDEDIR=$ac_cv_rl_includedir + +AC_MSG_RESULT($ac_cv_rl_version) + +fi +]) + +AC_DEFUN(BASH_FUNC_CTYPE_NONASCII, +[ +AC_MSG_CHECKING(whether the ctype macros accept non-ascii characters) +AC_CACHE_VAL(bash_cv_func_ctype_nonascii, +[AC_TRY_RUN([ +#ifdef HAVE_LOCALE_H +#include +#endif +#include +#include + +main(c, v) +int c; +char *v[]; +{ + char *deflocale; + unsigned char x; + int r1, r2; + +#ifdef HAVE_SETLOCALE + /* We take a shot here. If that locale is not known, try the + system default. We try this one because '\342' (226) is + known to be a printable character in that locale. */ + deflocale = setlocale(LC_ALL, "en_US.ISO8859-1"); + if (deflocale == 0) + deflocale = setlocale(LC_ALL, ""); +#endif + + x = '\342'; + r1 = isprint(x); + x -= 128; + r2 = isprint(x); + exit (r1 == 0 || r2 == 0); +} +], bash_cv_func_ctype_nonascii=yes, bash_cv_func_ctype_nonascii=no, + [AC_MSG_WARN(cannot check ctype macros if cross compiling -- defaulting to no) + bash_cv_func_ctype_nonascii=no] +)]) +AC_MSG_RESULT($bash_cv_func_ctype_nonascii) +if test $bash_cv_func_ctype_nonascii = yes; then +AC_DEFINE(CTYPE_NON_ASCII) +fi +]) + +AC_DEFUN(BASH_CHECK_WCONTINUED, +[ +AC_MSG_CHECKING(whether WCONTINUED flag to waitpid is unavailable or available but broken) +AC_CACHE_VAL(bash_cv_wcontinued_broken, +[AC_TRY_RUN([ +#include +#include +#include +#include + +#ifndef errno +extern int errno; +#endif +main() +{ + int x; + + x = waitpid(-1, (int *)0, WNOHANG|WCONTINUED); + if (x == -1 && errno == EINVAL) + exit (1); + else + exit (0); +} +], bash_cv_wcontinued_broken=no,bash_cv_wcontinued_broken=yes, + [AC_MSG_WARN(cannot check WCONTINUED if cross compiling -- defaulting to no) + bash_cv_wcontinued_broken=no] +)]) +AC_MSG_RESULT($bash_cv_wcontinued_broken) +if test $bash_cv_wcontinued_broken = yes; then +AC_DEFINE(WCONTINUED_BROKEN) +fi +]) + +dnl +dnl tests added for bashdb +dnl + + +AC_DEFUN([AM_PATH_LISPDIR], + [AC_ARG_WITH(lispdir, AC_HELP_STRING([--with-lispdir], [override the default lisp directory]), + [ lispdir="$withval" + AC_MSG_CHECKING([where .elc files should go]) + AC_MSG_RESULT([$lispdir])], + [ + # If set to t, that means we are running in a shell under Emacs. + # If you have an Emacs named "t", then use the full path. + test x"$EMACS" = xt && EMACS= + AC_CHECK_PROGS(EMACS, emacs xemacs, no) + if test $EMACS != "no"; then + if test x${lispdir+set} != xset; then + AC_CACHE_CHECK([where .elc files should go], [am_cv_lispdir], [dnl + am_cv_lispdir=`$EMACS -batch -q -eval '(while load-path (princ (concat (car load-path) "\n")) (setq load-path (cdr load-path)))' | sed -n -e 's,/$,,' -e '/.*\/lib\/\(x\?emacs\/site-lisp\)$/{s,,${libdir}/\1,;p;q;}' -e '/.*\/share\/\(x\?emacs\/site-lisp\)$/{s,,${datadir}/\1,;p;q;}'` + if test -z "$am_cv_lispdir"; then + am_cv_lispdir='${datadir}/emacs/site-lisp' + fi + ]) + lispdir="$am_cv_lispdir" + fi + fi + ]) + AC_SUBST(lispdir) +]) + +dnl +dnl tests added for gettext +dnl +# codeset.m4 serial AM1 (gettext-0.10.40) +dnl Copyright (C) 2000-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +AC_DEFUN([AM_LANGINFO_CODESET], +[ + AC_CACHE_CHECK([for nl_langinfo and CODESET], am_cv_langinfo_codeset, + [AC_TRY_LINK([#include ], + [char* cs = nl_langinfo(CODESET);], + am_cv_langinfo_codeset=yes, + am_cv_langinfo_codeset=no) + ]) + if test $am_cv_langinfo_codeset = yes; then + AC_DEFINE(HAVE_LANGINFO_CODESET, 1, + [Define if you have and nl_langinfo(CODESET).]) + fi +]) +# gettext.m4 serial 20 (gettext-0.12) +dnl Copyright (C) 1995-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1995-2000. +dnl Bruno Haible , 2000-2003. + +dnl Macro to add for using GNU gettext. + +dnl Usage: AM_GNU_GETTEXT([INTLSYMBOL], [NEEDSYMBOL], [INTLDIR]). +dnl INTLSYMBOL can be one of 'external', 'no-libtool', 'use-libtool'. The +dnl default (if it is not specified or empty) is 'no-libtool'. +dnl INTLSYMBOL should be 'external' for packages with no intl directory, +dnl and 'no-libtool' or 'use-libtool' for packages with an intl directory. +dnl If INTLSYMBOL is 'use-libtool', then a libtool library +dnl $(top_builddir)/intl/libintl.la will be created (shared and/or static, +dnl depending on --{enable,disable}-{shared,static} and on the presence of +dnl AM-DISABLE-SHARED). If INTLSYMBOL is 'no-libtool', a static library +dnl $(top_builddir)/intl/libintl.a will be created. +dnl If NEEDSYMBOL is specified and is 'need-ngettext', then GNU gettext +dnl implementations (in libc or libintl) without the ngettext() function +dnl will be ignored. If NEEDSYMBOL is specified and is +dnl 'need-formatstring-macros', then GNU gettext implementations that don't +dnl support the ISO C 99 formatstring macros will be ignored. +dnl INTLDIR is used to find the intl libraries. If empty, +dnl the value `$(top_builddir)/intl/' is used. +dnl +dnl The result of the configuration is one of three cases: +dnl 1) GNU gettext, as included in the intl subdirectory, will be compiled +dnl and used. +dnl Catalog format: GNU --> install in $(datadir) +dnl Catalog extension: .mo after installation, .gmo in source tree +dnl 2) GNU gettext has been found in the system's C library. +dnl Catalog format: GNU --> install in $(datadir) +dnl Catalog extension: .mo after installation, .gmo in source tree +dnl 3) No internationalization, always use English msgid. +dnl Catalog format: none +dnl Catalog extension: none +dnl If INTLSYMBOL is 'external', only cases 2 and 3 can occur. +dnl The use of .gmo is historical (it was needed to avoid overwriting the +dnl GNU format catalogs when building on a platform with an X/Open gettext), +dnl but we keep it in order not to force irrelevant filename changes on the +dnl maintainers. +dnl +AC_DEFUN([AM_GNU_GETTEXT], +[ + dnl Argument checking. + ifelse([$1], [], , [ifelse([$1], [external], , [ifelse([$1], [no-libtool], , [ifelse([$1], [use-libtool], , + [errprint([ERROR: invalid first argument to AM_GNU_GETTEXT +])])])])]) + ifelse([$2], [], , [ifelse([$2], [need-ngettext], , [ifelse([$2], [need-formatstring-macros], , + [errprint([ERROR: invalid second argument to AM_GNU_GETTEXT +])])])]) + define(gt_included_intl, ifelse([$1], [external], [no], [yes])) + define(gt_libtool_suffix_prefix, ifelse([$1], [use-libtool], [l], [])) + + AC_REQUIRE([AM_PO_SUBDIRS])dnl + ifelse(gt_included_intl, yes, [ + AC_REQUIRE([AM_INTL_SUBDIR])dnl + ]) + + dnl Prerequisites of AC_LIB_LINKFLAGS_BODY. + AC_REQUIRE([AC_LIB_PREPARE_PREFIX]) + AC_REQUIRE([AC_LIB_RPATH]) + + dnl Sometimes libintl requires libiconv, so first search for libiconv. + dnl Ideally we would do this search only after the + dnl if test "$USE_NLS" = "yes"; then + dnl if test "$gt_cv_func_gnugettext_libc" != "yes"; then + dnl tests. But if configure.in invokes AM_ICONV after AM_GNU_GETTEXT + dnl the configure script would need to contain the same shell code + dnl again, outside any 'if'. There are two solutions: + dnl - Invoke AM_ICONV_LINKFLAGS_BODY here, outside any 'if'. + dnl - Control the expansions in more detail using AC_PROVIDE_IFELSE. + dnl Since AC_PROVIDE_IFELSE is only in autoconf >= 2.52 and not + dnl documented, we avoid it. + ifelse(gt_included_intl, yes, , [ + AC_REQUIRE([AM_ICONV_LINKFLAGS_BODY]) + ]) + + dnl Set USE_NLS. + AM_NLS + + ifelse(gt_included_intl, yes, [ + BUILD_INCLUDED_LIBINTL=no + USE_INCLUDED_LIBINTL=no + ]) + LIBINTL= + LTLIBINTL= + POSUB= + + dnl If we use NLS figure out what method + if test "$USE_NLS" = "yes"; then + gt_use_preinstalled_gnugettext=no + ifelse(gt_included_intl, yes, [ + AC_MSG_CHECKING([whether included gettext is requested]) + AC_ARG_WITH(included-gettext, + [ --with-included-gettext use the GNU gettext library included here], + nls_cv_force_use_gnu_gettext=$withval, + nls_cv_force_use_gnu_gettext=no) + AC_MSG_RESULT($nls_cv_force_use_gnu_gettext) + + nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" + if test "$nls_cv_force_use_gnu_gettext" != "yes"; then + ]) + dnl User does not insist on using GNU NLS library. Figure out what + dnl to use. If GNU gettext is available we use this. Else we have + dnl to fall back to GNU NLS library. + + dnl Add a version number to the cache macros. + define([gt_api_version], ifelse([$2], [need-formatstring-macros], 3, ifelse([$2], [need-ngettext], 2, 1))) + define([gt_cv_func_gnugettext_libc], [gt_cv_func_gnugettext]gt_api_version[_libc]) + define([gt_cv_func_gnugettext_libintl], [gt_cv_func_gnugettext]gt_api_version[_libintl]) + + AC_CACHE_CHECK([for GNU gettext in libc], gt_cv_func_gnugettext_libc, + [AC_TRY_LINK([#include +]ifelse([$2], [need-formatstring-macros], +[#ifndef __GNU_GETTEXT_SUPPORTED_REVISION +#define __GNU_GETTEXT_SUPPORTED_REVISION(major) ((major) == 0 ? 0 : -1) +#endif +changequote(,)dnl +typedef int array [2 * (__GNU_GETTEXT_SUPPORTED_REVISION(0) >= 1) - 1]; +changequote([,])dnl +], [])[extern int _nl_msg_cat_cntr; +extern int *_nl_domain_bindings;], + [bindtextdomain ("", ""); +return (int) gettext ("")]ifelse([$2], [need-ngettext], [ + (int) ngettext ("", "", 0)], [])[ + _nl_msg_cat_cntr + *_nl_domain_bindings], + gt_cv_func_gnugettext_libc=yes, + gt_cv_func_gnugettext_libc=no)]) + + if test "$gt_cv_func_gnugettext_libc" != "yes"; then + dnl Sometimes libintl requires libiconv, so first search for libiconv. + ifelse(gt_included_intl, yes, , [ + AM_ICONV_LINK + ]) + dnl Search for libintl and define LIBINTL, LTLIBINTL and INCINTL + dnl accordingly. Don't use AC_LIB_LINKFLAGS_BODY([intl],[iconv]) + dnl because that would add "-liconv" to LIBINTL and LTLIBINTL + dnl even if libiconv doesn't exist. + AC_LIB_LINKFLAGS_BODY([intl]) + AC_CACHE_CHECK([for GNU gettext in libintl], + gt_cv_func_gnugettext_libintl, + [gt_save_CPPFLAGS="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $INCINTL" + gt_save_LIBS="$LIBS" + LIBS="$LIBS $LIBINTL" + dnl Now see whether libintl exists and does not depend on libiconv. + AC_TRY_LINK([#include +]ifelse([$2], [need-formatstring-macros], +[#ifndef __GNU_GETTEXT_SUPPORTED_REVISION +#define __GNU_GETTEXT_SUPPORTED_REVISION(major) ((major) == 0 ? 0 : -1) +#endif +changequote(,)dnl +typedef int array [2 * (__GNU_GETTEXT_SUPPORTED_REVISION(0) >= 1) - 1]; +changequote([,])dnl +], [])[extern int _nl_msg_cat_cntr; +extern +#ifdef __cplusplus +"C" +#endif +const char *_nl_expand_alias ();], + [bindtextdomain ("", ""); +return (int) gettext ("")]ifelse([$2], [need-ngettext], [ + (int) ngettext ("", "", 0)], [])[ + _nl_msg_cat_cntr + *_nl_expand_alias (0)], + gt_cv_func_gnugettext_libintl=yes, + gt_cv_func_gnugettext_libintl=no) + dnl Now see whether libintl exists and depends on libiconv. + if test "$gt_cv_func_gnugettext_libintl" != yes && test -n "$LIBICONV"; then + LIBS="$LIBS $LIBICONV" + AC_TRY_LINK([#include +]ifelse([$2], [need-formatstring-macros], +[#ifndef __GNU_GETTEXT_SUPPORTED_REVISION +#define __GNU_GETTEXT_SUPPORTED_REVISION(major) ((major) == 0 ? 0 : -1) +#endif +changequote(,)dnl +typedef int array [2 * (__GNU_GETTEXT_SUPPORTED_REVISION(0) >= 1) - 1]; +changequote([,])dnl +], [])[extern int _nl_msg_cat_cntr; +extern +#ifdef __cplusplus +"C" +#endif +const char *_nl_expand_alias ();], + [bindtextdomain ("", ""); +return (int) gettext ("")]ifelse([$2], [need-ngettext], [ + (int) ngettext ("", "", 0)], [])[ + _nl_msg_cat_cntr + *_nl_expand_alias (0)], + [LIBINTL="$LIBINTL $LIBICONV" + LTLIBINTL="$LTLIBINTL $LTLIBICONV" + gt_cv_func_gnugettext_libintl=yes + ]) + fi + CPPFLAGS="$gt_save_CPPFLAGS" + LIBS="$gt_save_LIBS"]) + fi + + dnl If an already present or preinstalled GNU gettext() is found, + dnl use it. But if this macro is used in GNU gettext, and GNU + dnl gettext is already preinstalled in libintl, we update this + dnl libintl. (Cf. the install rule in intl/Makefile.in.) + if test "$gt_cv_func_gnugettext_libc" = "yes" \ + || { test "$gt_cv_func_gnugettext_libintl" = "yes" \ + && test "$PACKAGE" != gettext-runtime \ + && test "$PACKAGE" != gettext-tools; }; then + gt_use_preinstalled_gnugettext=yes + else + dnl Reset the values set by searching for libintl. + LIBINTL= + LTLIBINTL= + INCINTL= + fi + + ifelse(gt_included_intl, yes, [ + if test "$gt_use_preinstalled_gnugettext" != "yes"; then + dnl GNU gettext is not found in the C library. + dnl Fall back on included GNU gettext library. + nls_cv_use_gnu_gettext=yes + fi + fi + + if test "$nls_cv_use_gnu_gettext" = "yes"; then + dnl Mark actions used to generate GNU NLS library. + BUILD_INCLUDED_LIBINTL=yes + USE_INCLUDED_LIBINTL=yes + LIBINTL="ifelse([$3],[],\${top_builddir}/intl,[$3])/libintl.[]gt_libtool_suffix_prefix[]a $LIBICONV" + LTLIBINTL="ifelse([$3],[],\${top_builddir}/intl,[$3])/libintl.[]gt_libtool_suffix_prefix[]a $LTLIBICONV" + LIBS=`echo " $LIBS " | sed -e 's/ -lintl / /' -e 's/^ //' -e 's/ $//'` + fi + + if test "$gt_use_preinstalled_gnugettext" = "yes" \ + || test "$nls_cv_use_gnu_gettext" = "yes"; then + dnl Mark actions to use GNU gettext tools. + CATOBJEXT=.gmo + fi + ]) + + if test "$gt_use_preinstalled_gnugettext" = "yes" \ + || test "$nls_cv_use_gnu_gettext" = "yes"; then + AC_DEFINE(ENABLE_NLS, 1, + [Define to 1 if translation of program messages to the user's native language + is requested.]) + else + USE_NLS=no + fi + fi + + AC_MSG_CHECKING([whether to use NLS]) + AC_MSG_RESULT([$USE_NLS]) + if test "$USE_NLS" = "yes"; then + AC_MSG_CHECKING([where the gettext function comes from]) + if test "$gt_use_preinstalled_gnugettext" = "yes"; then + if test "$gt_cv_func_gnugettext_libintl" = "yes"; then + gt_source="external libintl" + else + gt_source="libc" + fi + else + gt_source="included intl directory" + fi + AC_MSG_RESULT([$gt_source]) + fi + + if test "$USE_NLS" = "yes"; then + + if test "$gt_use_preinstalled_gnugettext" = "yes"; then + if test "$gt_cv_func_gnugettext_libintl" = "yes"; then + AC_MSG_CHECKING([how to link with libintl]) + AC_MSG_RESULT([$LIBINTL]) + AC_LIB_APPENDTOVAR([CPPFLAGS], [$INCINTL]) + fi + + dnl For backward compatibility. Some packages may be using this. + AC_DEFINE(HAVE_GETTEXT, 1, + [Define if the GNU gettext() function is already present or preinstalled.]) + AC_DEFINE(HAVE_DCGETTEXT, 1, + [Define if the GNU dcgettext() function is already present or preinstalled.]) + fi + + dnl We need to process the po/ directory. + POSUB=po + fi + + ifelse(gt_included_intl, yes, [ + dnl If this is used in GNU gettext we have to set BUILD_INCLUDED_LIBINTL + dnl to 'yes' because some of the testsuite requires it. + if test "$PACKAGE" = gettext-runtime || test "$PACKAGE" = gettext-tools; then + BUILD_INCLUDED_LIBINTL=yes + fi + + dnl Make all variables we use known to autoconf. + AC_SUBST(BUILD_INCLUDED_LIBINTL) + AC_SUBST(USE_INCLUDED_LIBINTL) + AC_SUBST(CATOBJEXT) + + dnl For backward compatibility. Some configure.ins may be using this. + nls_cv_header_intl= + nls_cv_header_libgt= + + dnl For backward compatibility. Some Makefiles may be using this. + DATADIRNAME=share + AC_SUBST(DATADIRNAME) + + dnl For backward compatibility. Some Makefiles may be using this. + INSTOBJEXT=.mo + AC_SUBST(INSTOBJEXT) + + dnl For backward compatibility. Some Makefiles may be using this. + GENCAT=gencat + AC_SUBST(GENCAT) + + dnl For backward compatibility. Some Makefiles may be using this. + if test "$USE_INCLUDED_LIBINTL" = yes; then + INTLOBJS="\$(GETTOBJS)" + fi + AC_SUBST(INTLOBJS) + + dnl Enable libtool support if the surrounding package wishes it. + INTL_LIBTOOL_SUFFIX_PREFIX=gt_libtool_suffix_prefix + AC_SUBST(INTL_LIBTOOL_SUFFIX_PREFIX) + ]) + + dnl For backward compatibility. Some Makefiles may be using this. + INTLLIBS="$LIBINTL" + AC_SUBST(INTLLIBS) + + dnl Make all documented variables known to autoconf. + AC_SUBST(LIBINTL) + AC_SUBST(LTLIBINTL) + AC_SUBST(POSUB) +]) + + +dnl Checks for all prerequisites of the intl subdirectory, +dnl except for INTL_LIBTOOL_SUFFIX_PREFIX (and possibly LIBTOOL), INTLOBJS, +dnl USE_INCLUDED_LIBINTL, BUILD_INCLUDED_LIBINTL. +AC_DEFUN([AM_INTL_SUBDIR], +[ + AC_REQUIRE([AC_PROG_INSTALL])dnl + AC_REQUIRE([AM_MKINSTALLDIRS])dnl + AC_REQUIRE([AC_PROG_CC])dnl + AC_REQUIRE([AC_CANONICAL_HOST])dnl + AC_REQUIRE([AC_PROG_RANLIB])dnl + AC_REQUIRE([AC_ISC_POSIX])dnl + AC_REQUIRE([AC_HEADER_STDC])dnl + AC_REQUIRE([AC_C_CONST])dnl + AC_REQUIRE([AC_C_INLINE])dnl + AC_REQUIRE([AC_TYPE_OFF_T])dnl + AC_REQUIRE([AC_TYPE_SIZE_T])dnl + AC_REQUIRE([AC_FUNC_ALLOCA])dnl + AC_REQUIRE([AC_FUNC_MMAP])dnl + AC_REQUIRE([jm_GLIBC21])dnl + AC_REQUIRE([gt_INTDIV0])dnl + AC_REQUIRE([jm_AC_TYPE_UINTMAX_T])dnl + AC_REQUIRE([gt_HEADER_INTTYPES_H])dnl + AC_REQUIRE([gt_INTTYPES_PRI])dnl + + AC_CHECK_HEADERS([argz.h limits.h locale.h nl_types.h malloc.h stddef.h \ +stdlib.h string.h unistd.h sys/param.h]) + AC_CHECK_FUNCS([feof_unlocked fgets_unlocked getc_unlocked getcwd getegid \ +geteuid getgid getuid mempcpy munmap putenv setenv setlocale stpcpy \ +strcasecmp strdup strtoul tsearch __argz_count __argz_stringify __argz_next \ +__fsetlocking]) + + AM_ICONV + AM_LANGINFO_CODESET + if test $ac_cv_header_locale_h = yes; then + AM_LC_MESSAGES + fi + + dnl intl/plural.c is generated from intl/plural.y. It requires bison, + dnl because plural.y uses bison specific features. It requires at least + dnl bison-1.26 because earlier versions generate a plural.c that doesn't + dnl compile. + dnl bison is only needed for the maintainer (who touches plural.y). But in + dnl order to avoid separate Makefiles or --enable-maintainer-mode, we put + dnl the rule in general Makefile. Now, some people carelessly touch the + dnl files or have a broken "make" program, hence the plural.c rule will + dnl sometimes fire. To avoid an error, defines BISON to ":" if it is not + dnl present or too old. + AC_CHECK_PROGS([INTLBISON], [bison]) + if test -z "$INTLBISON"; then + ac_verc_fail=yes + else + dnl Found it, now check the version. + AC_MSG_CHECKING([version of bison]) +changequote(<<,>>)dnl + ac_prog_version=`$INTLBISON --version 2>&1 | sed -n 's/^.*GNU Bison.* \([0-9]*\.[0-9.]*\).*$/\1/p'` + case $ac_prog_version in + '') ac_prog_version="v. ?.??, bad"; ac_verc_fail=yes;; + 1.2[6-9]* | 1.[3-9][0-9]* | [2-9].*) +changequote([,])dnl + ac_prog_version="$ac_prog_version, ok"; ac_verc_fail=no;; + *) ac_prog_version="$ac_prog_version, bad"; ac_verc_fail=yes;; + esac + AC_MSG_RESULT([$ac_prog_version]) + fi + if test $ac_verc_fail = yes; then + INTLBISON=: + fi +]) + + +dnl Usage: AM_GNU_GETTEXT_VERSION([gettext-version]) +AC_DEFUN([AM_GNU_GETTEXT_VERSION], []) +# glibc21.m4 serial 2 (fileutils-4.1.3, gettext-0.10.40) +dnl Copyright (C) 2000-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +# Test for the GNU C Library, version 2.1 or newer. +# From Bruno Haible. + +AC_DEFUN([jm_GLIBC21], + [ + AC_CACHE_CHECK(whether we are using the GNU C Library 2.1 or newer, + ac_cv_gnu_library_2_1, + [AC_EGREP_CPP([Lucky GNU user], + [ +#include +#ifdef __GNU_LIBRARY__ + #if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1) || (__GLIBC__ > 2) + Lucky GNU user + #endif +#endif + ], + ac_cv_gnu_library_2_1=yes, + ac_cv_gnu_library_2_1=no) + ] + ) + AC_SUBST(GLIBC21) + GLIBC21="$ac_cv_gnu_library_2_1" + ] +) +# iconv.m4 serial AM4 (gettext-0.11.3) +dnl Copyright (C) 2000-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +AC_DEFUN([AM_ICONV_LINKFLAGS_BODY], +[ + dnl Prerequisites of AC_LIB_LINKFLAGS_BODY. + AC_REQUIRE([AC_LIB_PREPARE_PREFIX]) + AC_REQUIRE([AC_LIB_RPATH]) + + dnl Search for libiconv and define LIBICONV, LTLIBICONV and INCICONV + dnl accordingly. + AC_LIB_LINKFLAGS_BODY([iconv]) +]) + +AC_DEFUN([AM_ICONV_LINK], +[ + dnl Some systems have iconv in libc, some have it in libiconv (OSF/1 and + dnl those with the standalone portable GNU libiconv installed). + + dnl Search for libiconv and define LIBICONV, LTLIBICONV and INCICONV + dnl accordingly. + AC_REQUIRE([AM_ICONV_LINKFLAGS_BODY]) + + dnl Add $INCICONV to CPPFLAGS before performing the following checks, + dnl because if the user has installed libiconv and not disabled its use + dnl via --without-libiconv-prefix, he wants to use it. The first + dnl AC_TRY_LINK will then fail, the second AC_TRY_LINK will succeed. + am_save_CPPFLAGS="$CPPFLAGS" + AC_LIB_APPENDTOVAR([CPPFLAGS], [$INCICONV]) + + AC_CACHE_CHECK(for iconv, am_cv_func_iconv, [ + am_cv_func_iconv="no, consider installing GNU libiconv" + am_cv_lib_iconv=no + AC_TRY_LINK([#include +#include ], + [iconv_t cd = iconv_open("",""); + iconv(cd,NULL,NULL,NULL,NULL); + iconv_close(cd);], + am_cv_func_iconv=yes) + if test "$am_cv_func_iconv" != yes; then + am_save_LIBS="$LIBS" + LIBS="$LIBS $LIBICONV" + AC_TRY_LINK([#include +#include ], + [iconv_t cd = iconv_open("",""); + iconv(cd,NULL,NULL,NULL,NULL); + iconv_close(cd);], + am_cv_lib_iconv=yes + am_cv_func_iconv=yes) + LIBS="$am_save_LIBS" + fi + ]) + if test "$am_cv_func_iconv" = yes; then + AC_DEFINE(HAVE_ICONV, 1, [Define if you have the iconv() function.]) + fi + if test "$am_cv_lib_iconv" = yes; then + AC_MSG_CHECKING([how to link with libiconv]) + AC_MSG_RESULT([$LIBICONV]) + else + dnl If $LIBICONV didn't lead to a usable library, we don't need $INCICONV + dnl either. + CPPFLAGS="$am_save_CPPFLAGS" + LIBICONV= + LTLIBICONV= + fi + AC_SUBST(LIBICONV) + AC_SUBST(LTLIBICONV) +]) + +AC_DEFUN([AM_ICONV], +[ + AM_ICONV_LINK + if test "$am_cv_func_iconv" = yes; then + AC_MSG_CHECKING([for iconv declaration]) + AC_CACHE_VAL(am_cv_proto_iconv, [ + AC_TRY_COMPILE([ +#include +#include +extern +#ifdef __cplusplus +"C" +#endif +#if defined(__STDC__) || defined(__cplusplus) +size_t iconv (iconv_t cd, char * *inbuf, size_t *inbytesleft, char * *outbuf, size_t *outbytesleft); +#else +size_t iconv(); +#endif +], [], am_cv_proto_iconv_arg1="", am_cv_proto_iconv_arg1="const") + am_cv_proto_iconv="extern size_t iconv (iconv_t cd, $am_cv_proto_iconv_arg1 char * *inbuf, size_t *inbytesleft, char * *outbuf, size_t *outbytesleft);"]) + am_cv_proto_iconv=`echo "[$]am_cv_proto_iconv" | tr -s ' ' | sed -e 's/( /(/'` + AC_MSG_RESULT([$]{ac_t:- + }[$]am_cv_proto_iconv) + AC_DEFINE_UNQUOTED(ICONV_CONST, $am_cv_proto_iconv_arg1, + [Define as const if the declaration of iconv() needs const.]) + fi +]) +# intdiv0.m4 serial 1 (gettext-0.11.3) +dnl Copyright (C) 2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +AC_DEFUN([gt_INTDIV0], +[ + AC_REQUIRE([AC_PROG_CC])dnl + AC_REQUIRE([AC_CANONICAL_HOST])dnl + + AC_CACHE_CHECK([whether integer division by zero raises SIGFPE], + gt_cv_int_divbyzero_sigfpe, + [ + AC_TRY_RUN([ +#include +#include + +static void +#ifdef __cplusplus +sigfpe_handler (int sig) +#else +sigfpe_handler (sig) int sig; +#endif +{ + /* Exit with code 0 if SIGFPE, with code 1 if any other signal. */ + exit (sig != SIGFPE); +} + +int x = 1; +int y = 0; +int z; +int nan; + +int main () +{ + signal (SIGFPE, sigfpe_handler); +/* IRIX and AIX (when "xlc -qcheck" is used) yield signal SIGTRAP. */ +#if (defined (__sgi) || defined (_AIX)) && defined (SIGTRAP) + signal (SIGTRAP, sigfpe_handler); +#endif +/* Linux/SPARC yields signal SIGILL. */ +#if defined (__sparc__) && defined (__linux__) + signal (SIGILL, sigfpe_handler); +#endif + + z = x / y; + nan = y / y; + exit (1); +} +], gt_cv_int_divbyzero_sigfpe=yes, gt_cv_int_divbyzero_sigfpe=no, + [ + # Guess based on the CPU. + case "$host_cpu" in + alpha* | i[34567]86 | m68k | s390*) + gt_cv_int_divbyzero_sigfpe="guessing yes";; + *) + gt_cv_int_divbyzero_sigfpe="guessing no";; + esac + ]) + ]) + case "$gt_cv_int_divbyzero_sigfpe" in + *yes) value=1;; + *) value=0;; + esac + AC_DEFINE_UNQUOTED(INTDIV0_RAISES_SIGFPE, $value, + [Define if integer division by zero raises signal SIGFPE.]) +]) +# inttypes.m4 serial 1 (gettext-0.11.4) +dnl Copyright (C) 1997-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Paul Eggert. + +# Define HAVE_INTTYPES_H if exists and doesn't clash with +# . + +AC_DEFUN([gt_HEADER_INTTYPES_H], +[ + AC_CACHE_CHECK([for inttypes.h], gt_cv_header_inttypes_h, + [ + AC_TRY_COMPILE( + [#include +#include ], + [], gt_cv_header_inttypes_h=yes, gt_cv_header_inttypes_h=no) + ]) + if test $gt_cv_header_inttypes_h = yes; then + AC_DEFINE_UNQUOTED(HAVE_INTTYPES_H, 1, + [Define if exists and doesn't clash with .]) + fi +]) +# inttypes_h.m4 serial 5 (gettext-0.12) +dnl Copyright (C) 1997-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Paul Eggert. + +# Define HAVE_INTTYPES_H_WITH_UINTMAX if exists, +# doesn't clash with , and declares uintmax_t. + +AC_DEFUN([jm_AC_HEADER_INTTYPES_H], +[ + AC_CACHE_CHECK([for inttypes.h], jm_ac_cv_header_inttypes_h, + [AC_TRY_COMPILE( + [#include +#include ], + [uintmax_t i = (uintmax_t) -1;], + jm_ac_cv_header_inttypes_h=yes, + jm_ac_cv_header_inttypes_h=no)]) + if test $jm_ac_cv_header_inttypes_h = yes; then + AC_DEFINE_UNQUOTED(HAVE_INTTYPES_H_WITH_UINTMAX, 1, + [Define if exists, doesn't clash with , + and declares uintmax_t. ]) + fi +]) +# inttypes-pri.m4 serial 1 (gettext-0.11.4) +dnl Copyright (C) 1997-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +# Define PRI_MACROS_BROKEN if exists and defines the PRI* +# macros to non-string values. This is the case on AIX 4.3.3. + +AC_DEFUN([gt_INTTYPES_PRI], +[ + AC_REQUIRE([gt_HEADER_INTTYPES_H]) + if test $gt_cv_header_inttypes_h = yes; then + AC_CACHE_CHECK([whether the inttypes.h PRIxNN macros are broken], + gt_cv_inttypes_pri_broken, + [ + AC_TRY_COMPILE([#include +#ifdef PRId32 +char *p = PRId32; +#endif +], [], gt_cv_inttypes_pri_broken=no, gt_cv_inttypes_pri_broken=yes) + ]) + fi + if test "$gt_cv_inttypes_pri_broken" = yes; then + AC_DEFINE_UNQUOTED(PRI_MACROS_BROKEN, 1, + [Define if exists and defines unusable PRI* macros.]) + fi +]) +# isc-posix.m4 serial 2 (gettext-0.11.2) +dnl Copyright (C) 1995-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +# This file is not needed with autoconf-2.53 and newer. Remove it in 2005. + +# This test replaces the one in autoconf. +# Currently this macro should have the same name as the autoconf macro +# because gettext's gettext.m4 (distributed in the automake package) +# still uses it. Otherwise, the use in gettext.m4 makes autoheader +# give these diagnostics: +# configure.in:556: AC_TRY_COMPILE was called before AC_ISC_POSIX +# configure.in:556: AC_TRY_RUN was called before AC_ISC_POSIX + +undefine([AC_ISC_POSIX]) + +AC_DEFUN([AC_ISC_POSIX], + [ + dnl This test replaces the obsolescent AC_ISC_POSIX kludge. + AC_CHECK_LIB(cposix, strerror, [LIBS="$LIBS -lcposix"]) + ] +) +# lcmessage.m4 serial 3 (gettext-0.11.3) +dnl Copyright (C) 1995-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1995. + +# Check whether LC_MESSAGES is available in . + +AC_DEFUN([AM_LC_MESSAGES], +[ + AC_CACHE_CHECK([for LC_MESSAGES], am_cv_val_LC_MESSAGES, + [AC_TRY_LINK([#include ], [return LC_MESSAGES], + am_cv_val_LC_MESSAGES=yes, am_cv_val_LC_MESSAGES=no)]) + if test $am_cv_val_LC_MESSAGES = yes; then + AC_DEFINE(HAVE_LC_MESSAGES, 1, + [Define if your file defines LC_MESSAGES.]) + fi +]) +# lib-ld.m4 serial 2 (gettext-0.12) +dnl Copyright (C) 1996-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl Subroutines of libtool.m4, +dnl with replacements s/AC_/AC_LIB/ and s/lt_cv/acl_cv/ to avoid collision +dnl with libtool.m4. + +dnl From libtool-1.4. Sets the variable with_gnu_ld to yes or no. +AC_DEFUN([AC_LIB_PROG_LD_GNU], +[AC_CACHE_CHECK([if the linker ($LD) is GNU ld], acl_cv_prog_gnu_ld, +[# I'd rather use --version here, but apparently some GNU ld's only accept -v. +if $LD -v 2>&1 &5; then + acl_cv_prog_gnu_ld=yes +else + acl_cv_prog_gnu_ld=no +fi]) +with_gnu_ld=$acl_cv_prog_gnu_ld +]) + +dnl From libtool-1.4. Sets the variable LD. +AC_DEFUN([AC_LIB_PROG_LD], +[AC_ARG_WITH(gnu-ld, +[ --with-gnu-ld assume the C compiler uses GNU ld [default=no]], +test "$withval" = no || with_gnu_ld=yes, with_gnu_ld=no) +AC_REQUIRE([AC_PROG_CC])dnl +AC_REQUIRE([AC_CANONICAL_HOST])dnl +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi +ac_prog=ld +if test "$GCC" = yes; then + # Check if gcc -print-prog-name=ld gives a path. + AC_MSG_CHECKING([for ld used by GCC]) + case $host in + *-*-mingw*) + # gcc leaves a trailing carriage return which upsets mingw + ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; + *) + ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; + esac + case $ac_prog in + # Accept absolute paths. + [[\\/]* | [A-Za-z]:[\\/]*)] + [re_direlt='/[^/][^/]*/\.\./'] + # Canonicalize the path of ld + ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'` + while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do + ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"` + done + test -z "$LD" && LD="$ac_prog" + ;; + "") + # If it fails, then pretend we aren't using GCC. + ac_prog=ld + ;; + *) + # If it is relative, then search for the first ld in PATH. + with_gnu_ld=unknown + ;; + esac +elif test "$with_gnu_ld" = yes; then + AC_MSG_CHECKING([for GNU ld]) +else + AC_MSG_CHECKING([for non-GNU ld]) +fi +AC_CACHE_VAL(acl_cv_path_LD, +[if test -z "$LD"; then + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then + acl_cv_path_LD="$ac_dir/$ac_prog" + # Check to see if the program is GNU ld. I'd rather use --version, + # but apparently some GNU ld's only accept -v. + # Break only if it was the GNU/non-GNU ld that we prefer. + if "$acl_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then + test "$with_gnu_ld" != no && break + else + test "$with_gnu_ld" != yes && break + fi + fi + done + IFS="$ac_save_ifs" +else + acl_cv_path_LD="$LD" # Let the user override the test with a path. +fi]) +LD="$acl_cv_path_LD" +if test -n "$LD"; then + AC_MSG_RESULT($LD) +else + AC_MSG_RESULT(no) +fi +test -z "$LD" && AC_MSG_ERROR([no acceptable ld found in \$PATH]) +AC_LIB_PROG_LD_GNU +]) +# lib-link.m4 serial 4 (gettext-0.12) +dnl Copyright (C) 2001-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +dnl AC_LIB_LINKFLAGS(name [, dependencies]) searches for libname and +dnl the libraries corresponding to explicit and implicit dependencies. +dnl Sets and AC_SUBSTs the LIB${NAME} and LTLIB${NAME} variables and +dnl augments the CPPFLAGS variable. +AC_DEFUN([AC_LIB_LINKFLAGS], +[ + AC_REQUIRE([AC_LIB_PREPARE_PREFIX]) + AC_REQUIRE([AC_LIB_RPATH]) + define([Name],[translit([$1],[./-], [___])]) + define([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-], + [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])]) + AC_CACHE_CHECK([how to link with lib[]$1], [ac_cv_lib[]Name[]_libs], [ + AC_LIB_LINKFLAGS_BODY([$1], [$2]) + ac_cv_lib[]Name[]_libs="$LIB[]NAME" + ac_cv_lib[]Name[]_ltlibs="$LTLIB[]NAME" + ac_cv_lib[]Name[]_cppflags="$INC[]NAME" + ]) + LIB[]NAME="$ac_cv_lib[]Name[]_libs" + LTLIB[]NAME="$ac_cv_lib[]Name[]_ltlibs" + INC[]NAME="$ac_cv_lib[]Name[]_cppflags" + AC_LIB_APPENDTOVAR([CPPFLAGS], [$INC]NAME) + AC_SUBST([LIB]NAME) + AC_SUBST([LTLIB]NAME) + dnl Also set HAVE_LIB[]NAME so that AC_LIB_HAVE_LINKFLAGS can reuse the + dnl results of this search when this library appears as a dependency. + HAVE_LIB[]NAME=yes + undefine([Name]) + undefine([NAME]) +]) + +dnl AC_LIB_HAVE_LINKFLAGS(name, dependencies, includes, testcode) +dnl searches for libname and the libraries corresponding to explicit and +dnl implicit dependencies, together with the specified include files and +dnl the ability to compile and link the specified testcode. If found, it +dnl sets and AC_SUBSTs HAVE_LIB${NAME}=yes and the LIB${NAME} and +dnl LTLIB${NAME} variables and augments the CPPFLAGS variable, and +dnl #defines HAVE_LIB${NAME} to 1. Otherwise, it sets and AC_SUBSTs +dnl HAVE_LIB${NAME}=no and LIB${NAME} and LTLIB${NAME} to empty. +AC_DEFUN([AC_LIB_HAVE_LINKFLAGS], +[ + AC_REQUIRE([AC_LIB_PREPARE_PREFIX]) + AC_REQUIRE([AC_LIB_RPATH]) + define([Name],[translit([$1],[./-], [___])]) + define([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-], + [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])]) + + dnl Search for lib[]Name and define LIB[]NAME, LTLIB[]NAME and INC[]NAME + dnl accordingly. + AC_LIB_LINKFLAGS_BODY([$1], [$2]) + + dnl Add $INC[]NAME to CPPFLAGS before performing the following checks, + dnl because if the user has installed lib[]Name and not disabled its use + dnl via --without-lib[]Name-prefix, he wants to use it. + ac_save_CPPFLAGS="$CPPFLAGS" + AC_LIB_APPENDTOVAR([CPPFLAGS], [$INC]NAME) + + AC_CACHE_CHECK([for lib[]$1], [ac_cv_lib[]Name], [ + ac_save_LIBS="$LIBS" + LIBS="$LIBS $LIB[]NAME" + AC_TRY_LINK([$3], [$4], [ac_cv_lib[]Name=yes], [ac_cv_lib[]Name=no]) + LIBS="$ac_save_LIBS" + ]) + if test "$ac_cv_lib[]Name" = yes; then + HAVE_LIB[]NAME=yes + AC_DEFINE([HAVE_LIB]NAME, 1, [Define if you have the $1 library.]) + AC_MSG_CHECKING([how to link with lib[]$1]) + AC_MSG_RESULT([$LIB[]NAME]) + else + HAVE_LIB[]NAME=no + dnl If $LIB[]NAME didn't lead to a usable library, we don't need + dnl $INC[]NAME either. + CPPFLAGS="$ac_save_CPPFLAGS" + LIB[]NAME= + LTLIB[]NAME= + fi + AC_SUBST([HAVE_LIB]NAME) + AC_SUBST([LIB]NAME) + AC_SUBST([LTLIB]NAME) + undefine([Name]) + undefine([NAME]) +]) + +dnl Determine the platform dependent parameters needed to use rpath: +dnl libext, shlibext, hardcode_libdir_flag_spec, hardcode_libdir_separator, +dnl hardcode_direct, hardcode_minus_L. +AC_DEFUN([AC_LIB_RPATH], +[ + AC_REQUIRE([AC_PROG_CC]) dnl we use $CC, $GCC, $LDFLAGS + AC_REQUIRE([AC_LIB_PROG_LD]) dnl we use $LD, $with_gnu_ld + AC_REQUIRE([AC_CANONICAL_HOST]) dnl we use $host + AC_REQUIRE([AC_CONFIG_AUX_DIR_DEFAULT]) dnl we use $ac_aux_dir + AC_CACHE_CHECK([for shared library run path origin], acl_cv_rpath, [ + CC="$CC" GCC="$GCC" LDFLAGS="$LDFLAGS" LD="$LD" with_gnu_ld="$with_gnu_ld" \ + ${CONFIG_SHELL-/bin/sh} "$ac_aux_dir/config.rpath" "$host" > conftest.sh + . ./conftest.sh + rm -f ./conftest.sh + acl_cv_rpath=done + ]) + wl="$acl_cv_wl" + libext="$acl_cv_libext" + shlibext="$acl_cv_shlibext" + hardcode_libdir_flag_spec="$acl_cv_hardcode_libdir_flag_spec" + hardcode_libdir_separator="$acl_cv_hardcode_libdir_separator" + hardcode_direct="$acl_cv_hardcode_direct" + hardcode_minus_L="$acl_cv_hardcode_minus_L" + dnl Determine whether the user wants rpath handling at all. + AC_ARG_ENABLE(rpath, + [ --disable-rpath do not hardcode runtime library paths], + :, enable_rpath=yes) +]) + +dnl AC_LIB_LINKFLAGS_BODY(name [, dependencies]) searches for libname and +dnl the libraries corresponding to explicit and implicit dependencies. +dnl Sets the LIB${NAME}, LTLIB${NAME} and INC${NAME} variables. +AC_DEFUN([AC_LIB_LINKFLAGS_BODY], +[ + define([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-], + [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])]) + dnl By default, look in $includedir and $libdir. + use_additional=yes + AC_LIB_WITH_FINAL_PREFIX([ + eval additional_includedir=\"$includedir\" + eval additional_libdir=\"$libdir\" + ]) + AC_LIB_ARG_WITH([lib$1-prefix], +[ --with-lib$1-prefix[=DIR] search for lib$1 in DIR/include and DIR/lib + --without-lib$1-prefix don't search for lib$1 in includedir and libdir], +[ + if test "X$withval" = "Xno"; then + use_additional=no + else + if test "X$withval" = "X"; then + AC_LIB_WITH_FINAL_PREFIX([ + eval additional_includedir=\"$includedir\" + eval additional_libdir=\"$libdir\" + ]) + else + additional_includedir="$withval/include" + additional_libdir="$withval/lib" + fi + fi +]) + dnl Search the library and its dependencies in $additional_libdir and + dnl $LDFLAGS. Using breadth-first-seach. + LIB[]NAME= + LTLIB[]NAME= + INC[]NAME= + rpathdirs= + ltrpathdirs= + names_already_handled= + names_next_round='$1 $2' + while test -n "$names_next_round"; do + names_this_round="$names_next_round" + names_next_round= + for name in $names_this_round; do + already_handled= + for n in $names_already_handled; do + if test "$n" = "$name"; then + already_handled=yes + break + fi + done + if test -z "$already_handled"; then + names_already_handled="$names_already_handled $name" + dnl See if it was already located by an earlier AC_LIB_LINKFLAGS + dnl or AC_LIB_HAVE_LINKFLAGS call. + uppername=`echo "$name" | sed -e 'y|abcdefghijklmnopqrstuvwxyz./-|ABCDEFGHIJKLMNOPQRSTUVWXYZ___|'` + eval value=\"\$HAVE_LIB$uppername\" + if test -n "$value"; then + if test "$value" = yes; then + eval value=\"\$LIB$uppername\" + test -z "$value" || LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$value" + eval value=\"\$LTLIB$uppername\" + test -z "$value" || LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }$value" + else + dnl An earlier call to AC_LIB_HAVE_LINKFLAGS has determined + dnl that this library doesn't exist. So just drop it. + : + fi + else + dnl Search the library lib$name in $additional_libdir and $LDFLAGS + dnl and the already constructed $LIBNAME/$LTLIBNAME. + found_dir= + found_la= + found_so= + found_a= + if test $use_additional = yes; then + if test -n "$shlibext" && test -f "$additional_libdir/lib$name.$shlibext"; then + found_dir="$additional_libdir" + found_so="$additional_libdir/lib$name.$shlibext" + if test -f "$additional_libdir/lib$name.la"; then + found_la="$additional_libdir/lib$name.la" + fi + else + if test -f "$additional_libdir/lib$name.$libext"; then + found_dir="$additional_libdir" + found_a="$additional_libdir/lib$name.$libext" + if test -f "$additional_libdir/lib$name.la"; then + found_la="$additional_libdir/lib$name.la" + fi + fi + fi + fi + if test "X$found_dir" = "X"; then + for x in $LDFLAGS $LTLIB[]NAME; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + case "$x" in + -L*) + dir=`echo "X$x" | sed -e 's/^X-L//'` + if test -n "$shlibext" && test -f "$dir/lib$name.$shlibext"; then + found_dir="$dir" + found_so="$dir/lib$name.$shlibext" + if test -f "$dir/lib$name.la"; then + found_la="$dir/lib$name.la" + fi + else + if test -f "$dir/lib$name.$libext"; then + found_dir="$dir" + found_a="$dir/lib$name.$libext" + if test -f "$dir/lib$name.la"; then + found_la="$dir/lib$name.la" + fi + fi + fi + ;; + esac + if test "X$found_dir" != "X"; then + break + fi + done + fi + if test "X$found_dir" != "X"; then + dnl Found the library. + LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }-L$found_dir -l$name" + if test "X$found_so" != "X"; then + dnl Linking with a shared library. We attempt to hardcode its + dnl directory into the executable's runpath, unless it's the + dnl standard /usr/lib. + if test "$enable_rpath" = no || test "X$found_dir" = "X/usr/lib"; then + dnl No hardcoding is needed. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$found_so" + else + dnl Use an explicit option to hardcode DIR into the resulting + dnl binary. + dnl Potentially add DIR to ltrpathdirs. + dnl The ltrpathdirs will be appended to $LTLIBNAME at the end. + haveit= + for x in $ltrpathdirs; do + if test "X$x" = "X$found_dir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + ltrpathdirs="$ltrpathdirs $found_dir" + fi + dnl The hardcoding into $LIBNAME is system dependent. + if test "$hardcode_direct" = yes; then + dnl Using DIR/libNAME.so during linking hardcodes DIR into the + dnl resulting binary. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$found_so" + else + if test -n "$hardcode_libdir_flag_spec" && test "$hardcode_minus_L" = no; then + dnl Use an explicit option to hardcode DIR into the resulting + dnl binary. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$found_so" + dnl Potentially add DIR to rpathdirs. + dnl The rpathdirs will be appended to $LIBNAME at the end. + haveit= + for x in $rpathdirs; do + if test "X$x" = "X$found_dir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + rpathdirs="$rpathdirs $found_dir" + fi + else + dnl Rely on "-L$found_dir". + dnl But don't add it if it's already contained in the LDFLAGS + dnl or the already constructed $LIBNAME + haveit= + for x in $LDFLAGS $LIB[]NAME; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-L$found_dir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }-L$found_dir" + fi + if test "$hardcode_minus_L" != no; then + dnl FIXME: Not sure whether we should use + dnl "-L$found_dir -l$name" or "-L$found_dir $found_so" + dnl here. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$found_so" + else + dnl We cannot use $hardcode_runpath_var and LD_RUN_PATH + dnl here, because this doesn't fit in flags passed to the + dnl compiler. So give up. No hardcoding. This affects only + dnl very old systems. + dnl FIXME: Not sure whether we should use + dnl "-L$found_dir -l$name" or "-L$found_dir $found_so" + dnl here. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }-l$name" + fi + fi + fi + fi + else + if test "X$found_a" != "X"; then + dnl Linking with a static library. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$found_a" + else + dnl We shouldn't come here, but anyway it's good to have a + dnl fallback. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }-L$found_dir -l$name" + fi + fi + dnl Assume the include files are nearby. + additional_includedir= + case "$found_dir" in + */lib | */lib/) + basedir=`echo "X$found_dir" | sed -e 's,^X,,' -e 's,/lib/*$,,'` + additional_includedir="$basedir/include" + ;; + esac + if test "X$additional_includedir" != "X"; then + dnl Potentially add $additional_includedir to $INCNAME. + dnl But don't add it + dnl 1. if it's the standard /usr/include, + dnl 2. if it's /usr/local/include and we are using GCC on Linux, + dnl 3. if it's already present in $CPPFLAGS or the already + dnl constructed $INCNAME, + dnl 4. if it doesn't exist as a directory. + if test "X$additional_includedir" != "X/usr/include"; then + haveit= + if test "X$additional_includedir" = "X/usr/local/include"; then + if test -n "$GCC"; then + case $host_os in + linux*) haveit=yes;; + esac + fi + fi + if test -z "$haveit"; then + for x in $CPPFLAGS $INC[]NAME; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-I$additional_includedir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + if test -d "$additional_includedir"; then + dnl Really add $additional_includedir to $INCNAME. + INC[]NAME="${INC[]NAME}${INC[]NAME:+ }-I$additional_includedir" + fi + fi + fi + fi + fi + dnl Look for dependencies. + if test -n "$found_la"; then + dnl Read the .la file. It defines the variables + dnl dlname, library_names, old_library, dependency_libs, current, + dnl age, revision, installed, dlopen, dlpreopen, libdir. + save_libdir="$libdir" + case "$found_la" in + */* | *\\*) . "$found_la" ;; + *) . "./$found_la" ;; + esac + libdir="$save_libdir" + dnl We use only dependency_libs. + for dep in $dependency_libs; do + case "$dep" in + -L*) + additional_libdir=`echo "X$dep" | sed -e 's/^X-L//'` + dnl Potentially add $additional_libdir to $LIBNAME and $LTLIBNAME. + dnl But don't add it + dnl 1. if it's the standard /usr/lib, + dnl 2. if it's /usr/local/lib and we are using GCC on Linux, + dnl 3. if it's already present in $LDFLAGS or the already + dnl constructed $LIBNAME, + dnl 4. if it doesn't exist as a directory. + if test "X$additional_libdir" != "X/usr/lib"; then + haveit= + if test "X$additional_libdir" = "X/usr/local/lib"; then + if test -n "$GCC"; then + case $host_os in + linux*) haveit=yes;; + esac + fi + fi + if test -z "$haveit"; then + haveit= + for x in $LDFLAGS $LIB[]NAME; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-L$additional_libdir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + if test -d "$additional_libdir"; then + dnl Really add $additional_libdir to $LIBNAME. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }-L$additional_libdir" + fi + fi + haveit= + for x in $LDFLAGS $LTLIB[]NAME; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-L$additional_libdir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + if test -d "$additional_libdir"; then + dnl Really add $additional_libdir to $LTLIBNAME. + LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }-L$additional_libdir" + fi + fi + fi + fi + ;; + -R*) + dir=`echo "X$dep" | sed -e 's/^X-R//'` + if test "$enable_rpath" != no; then + dnl Potentially add DIR to rpathdirs. + dnl The rpathdirs will be appended to $LIBNAME at the end. + haveit= + for x in $rpathdirs; do + if test "X$x" = "X$dir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + rpathdirs="$rpathdirs $dir" + fi + dnl Potentially add DIR to ltrpathdirs. + dnl The ltrpathdirs will be appended to $LTLIBNAME at the end. + haveit= + for x in $ltrpathdirs; do + if test "X$x" = "X$dir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + ltrpathdirs="$ltrpathdirs $dir" + fi + fi + ;; + -l*) + dnl Handle this in the next round. + names_next_round="$names_next_round "`echo "X$dep" | sed -e 's/^X-l//'` + ;; + *.la) + dnl Handle this in the next round. Throw away the .la's + dnl directory; it is already contained in a preceding -L + dnl option. + names_next_round="$names_next_round "`echo "X$dep" | sed -e 's,^X.*/,,' -e 's,^lib,,' -e 's,\.la$,,'` + ;; + *) + dnl Most likely an immediate library name. + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$dep" + LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }$dep" + ;; + esac + done + fi + else + dnl Didn't find the library; assume it is in the system directories + dnl known to the linker and runtime loader. (All the system + dnl directories known to the linker should also be known to the + dnl runtime loader, otherwise the system is severely misconfigured.) + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }-l$name" + LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }-l$name" + fi + fi + fi + done + done + if test "X$rpathdirs" != "X"; then + if test -n "$hardcode_libdir_separator"; then + dnl Weird platform: only the last -rpath option counts, the user must + dnl pass all path elements in one option. We can arrange that for a + dnl single library, but not when more than one $LIBNAMEs are used. + alldirs= + for found_dir in $rpathdirs; do + alldirs="${alldirs}${alldirs:+$hardcode_libdir_separator}$found_dir" + done + dnl Note: hardcode_libdir_flag_spec uses $libdir and $wl. + acl_save_libdir="$libdir" + libdir="$alldirs" + eval flag=\"$hardcode_libdir_flag_spec\" + libdir="$acl_save_libdir" + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$flag" + else + dnl The -rpath options are cumulative. + for found_dir in $rpathdirs; do + acl_save_libdir="$libdir" + libdir="$found_dir" + eval flag=\"$hardcode_libdir_flag_spec\" + libdir="$acl_save_libdir" + LIB[]NAME="${LIB[]NAME}${LIB[]NAME:+ }$flag" + done + fi + fi + if test "X$ltrpathdirs" != "X"; then + dnl When using libtool, the option that works for both libraries and + dnl executables is -R. The -R options are cumulative. + for found_dir in $ltrpathdirs; do + LTLIB[]NAME="${LTLIB[]NAME}${LTLIB[]NAME:+ }-R$found_dir" + done + fi +]) + +dnl AC_LIB_APPENDTOVAR(VAR, CONTENTS) appends the elements of CONTENTS to VAR, +dnl unless already present in VAR. +dnl Works only for CPPFLAGS, not for LIB* variables because that sometimes +dnl contains two or three consecutive elements that belong together. +AC_DEFUN([AC_LIB_APPENDTOVAR], +[ + for element in [$2]; do + haveit= + for x in $[$1]; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X$element"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + [$1]="${[$1]}${[$1]:+ }$element" + fi + done +]) +# lib-prefix.m4 serial 2 (gettext-0.12) +dnl Copyright (C) 2001-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Bruno Haible. + +dnl AC_LIB_ARG_WITH is synonymous to AC_ARG_WITH in autoconf-2.13, and +dnl similar to AC_ARG_WITH in autoconf 2.52...2.57 except that is doesn't +dnl require excessive bracketing. +ifdef([AC_HELP_STRING], +[AC_DEFUN([AC_LIB_ARG_WITH], [AC_ARG_WITH([$1],[[$2]],[$3],[$4])])], +[AC_DEFUN([AC_LIB_ARG_WITH], [AC_ARG_WITH([$1],[$2],[$3],[$4])])]) + +dnl AC_LIB_PREFIX adds to the CPPFLAGS and LDFLAGS the flags that are needed +dnl to access previously installed libraries. The basic assumption is that +dnl a user will want packages to use other packages he previously installed +dnl with the same --prefix option. +dnl This macro is not needed if only AC_LIB_LINKFLAGS is used to locate +dnl libraries, but is otherwise very convenient. +AC_DEFUN([AC_LIB_PREFIX], +[ + AC_BEFORE([$0], [AC_LIB_LINKFLAGS]) + AC_REQUIRE([AC_PROG_CC]) + AC_REQUIRE([AC_CANONICAL_HOST]) + AC_REQUIRE([AC_LIB_PREPARE_PREFIX]) + dnl By default, look in $includedir and $libdir. + use_additional=yes + AC_LIB_WITH_FINAL_PREFIX([ + eval additional_includedir=\"$includedir\" + eval additional_libdir=\"$libdir\" + ]) + AC_LIB_ARG_WITH([lib-prefix], +[ --with-lib-prefix[=DIR] search for libraries in DIR/include and DIR/lib + --without-lib-prefix don't search for libraries in includedir and libdir], +[ + if test "X$withval" = "Xno"; then + use_additional=no + else + if test "X$withval" = "X"; then + AC_LIB_WITH_FINAL_PREFIX([ + eval additional_includedir=\"$includedir\" + eval additional_libdir=\"$libdir\" + ]) + else + additional_includedir="$withval/include" + additional_libdir="$withval/lib" + fi + fi +]) + if test $use_additional = yes; then + dnl Potentially add $additional_includedir to $CPPFLAGS. + dnl But don't add it + dnl 1. if it's the standard /usr/include, + dnl 2. if it's already present in $CPPFLAGS, + dnl 3. if it's /usr/local/include and we are using GCC on Linux, + dnl 4. if it doesn't exist as a directory. + if test "X$additional_includedir" != "X/usr/include"; then + haveit= + for x in $CPPFLAGS; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-I$additional_includedir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + if test "X$additional_includedir" = "X/usr/local/include"; then + if test -n "$GCC"; then + case $host_os in + linux*) haveit=yes;; + esac + fi + fi + if test -z "$haveit"; then + if test -d "$additional_includedir"; then + dnl Really add $additional_includedir to $CPPFLAGS. + CPPFLAGS="${CPPFLAGS}${CPPFLAGS:+ }-I$additional_includedir" + fi + fi + fi + fi + dnl Potentially add $additional_libdir to $LDFLAGS. + dnl But don't add it + dnl 1. if it's the standard /usr/lib, + dnl 2. if it's already present in $LDFLAGS, + dnl 3. if it's /usr/local/lib and we are using GCC on Linux, + dnl 4. if it doesn't exist as a directory. + if test "X$additional_libdir" != "X/usr/lib"; then + haveit= + for x in $LDFLAGS; do + AC_LIB_WITH_FINAL_PREFIX([eval x=\"$x\"]) + if test "X$x" = "X-L$additional_libdir"; then + haveit=yes + break + fi + done + if test -z "$haveit"; then + if test "X$additional_libdir" = "X/usr/local/lib"; then + if test -n "$GCC"; then + case $host_os in + linux*) haveit=yes;; + esac + fi + fi + if test -z "$haveit"; then + if test -d "$additional_libdir"; then + dnl Really add $additional_libdir to $LDFLAGS. + LDFLAGS="${LDFLAGS}${LDFLAGS:+ }-L$additional_libdir" + fi + fi + fi + fi + fi +]) + +dnl AC_LIB_PREPARE_PREFIX creates variables acl_final_prefix, +dnl acl_final_exec_prefix, containing the values to which $prefix and +dnl $exec_prefix will expand at the end of the configure script. +AC_DEFUN([AC_LIB_PREPARE_PREFIX], +[ + dnl Unfortunately, prefix and exec_prefix get only finally determined + dnl at the end of configure. + if test "X$prefix" = "XNONE"; then + acl_final_prefix="$ac_default_prefix" + else + acl_final_prefix="$prefix" + fi + if test "X$exec_prefix" = "XNONE"; then + acl_final_exec_prefix='${prefix}' + else + acl_final_exec_prefix="$exec_prefix" + fi + acl_save_prefix="$prefix" + prefix="$acl_final_prefix" + eval acl_final_exec_prefix=\"$acl_final_exec_prefix\" + prefix="$acl_save_prefix" +]) + +dnl AC_LIB_WITH_FINAL_PREFIX([statement]) evaluates statement, with the +dnl variables prefix and exec_prefix bound to the values they will have +dnl at the end of the configure script. +AC_DEFUN([AC_LIB_WITH_FINAL_PREFIX], +[ + acl_save_prefix="$prefix" + prefix="$acl_final_prefix" + acl_save_exec_prefix="$exec_prefix" + exec_prefix="$acl_final_exec_prefix" + $1 + exec_prefix="$acl_save_exec_prefix" + prefix="$acl_save_prefix" +]) +# nls.m4 serial 1 (gettext-0.12) +dnl Copyright (C) 1995-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1995-2000. +dnl Bruno Haible , 2000-2003. + +AC_DEFUN([AM_NLS], +[ + AC_MSG_CHECKING([whether NLS is requested]) + dnl Default is enabled NLS + AC_ARG_ENABLE(nls, + [ --disable-nls do not use Native Language Support], + USE_NLS=$enableval, USE_NLS=yes) + AC_MSG_RESULT($USE_NLS) + AC_SUBST(USE_NLS) +]) + +AC_DEFUN([AM_MKINSTALLDIRS], +[ + dnl If the AC_CONFIG_AUX_DIR macro for autoconf is used we possibly + dnl find the mkinstalldirs script in another subdir but $(top_srcdir). + dnl Try to locate it. + MKINSTALLDIRS= + if test -n "$ac_aux_dir"; then + case "$ac_aux_dir" in + /*) MKINSTALLDIRS="$ac_aux_dir/mkinstalldirs" ;; + *) MKINSTALLDIRS="\$(top_builddir)/$ac_aux_dir/mkinstalldirs" ;; + esac + fi + if test -z "$MKINSTALLDIRS"; then + MKINSTALLDIRS="\$(top_srcdir)/mkinstalldirs" + fi + AC_SUBST(MKINSTALLDIRS) +]) +# po.m4 serial 1 (gettext-0.12) +dnl Copyright (C) 1995-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1995-2000. +dnl Bruno Haible , 2000-2003. + +dnl Checks for all prerequisites of the po subdirectory. +AC_DEFUN([AM_PO_SUBDIRS], +[ + AC_REQUIRE([AC_PROG_MAKE_SET])dnl + AC_REQUIRE([AC_PROG_INSTALL])dnl + AC_REQUIRE([AM_MKINSTALLDIRS])dnl + AC_REQUIRE([AM_NLS])dnl + + dnl Perform the following tests also if --disable-nls has been given, + dnl because they are needed for "make dist" to work. + + dnl Search for GNU msgfmt in the PATH. + dnl The first test excludes Solaris msgfmt and early GNU msgfmt versions. + dnl The second test excludes FreeBSD msgfmt. + AM_PATH_PROG_WITH_TEST(MSGFMT, msgfmt, + [$ac_dir/$ac_word --statistics /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi)], + :) + AC_PATH_PROG(GMSGFMT, gmsgfmt, $MSGFMT) + + dnl Search for GNU xgettext 0.12 or newer in the PATH. + dnl The first test excludes Solaris xgettext and early GNU xgettext versions. + dnl The second test excludes FreeBSD xgettext. + AM_PATH_PROG_WITH_TEST(XGETTEXT, xgettext, + [$ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi)], + :) + dnl Remove leftover from FreeBSD xgettext call. + rm -f messages.po + + dnl Search for GNU msgmerge 0.11 or newer in the PATH. + AM_PATH_PROG_WITH_TEST(MSGMERGE, msgmerge, + [$ac_dir/$ac_word --update -q /dev/null /dev/null >/dev/null 2>&1], :) + + dnl This could go away some day; the PATH_PROG_WITH_TEST already does it. + dnl Test whether we really found GNU msgfmt. + if test "$GMSGFMT" != ":"; then + dnl If it is no GNU msgfmt we define it as : so that the + dnl Makefiles still can work. + if $GMSGFMT --statistics /dev/null >/dev/null 2>&1 && + (if $GMSGFMT --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + GMSGFMT=`echo "$GMSGFMT" | sed -e 's,^.*/,,'` + AC_MSG_RESULT( + [found $GMSGFMT program is not GNU msgfmt; ignore it]) + GMSGFMT=":" + fi + fi + + dnl This could go away some day; the PATH_PROG_WITH_TEST already does it. + dnl Test whether we really found GNU xgettext. + if test "$XGETTEXT" != ":"; then + dnl If it is no GNU xgettext we define it as : so that the + dnl Makefiles still can work. + if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + AC_MSG_RESULT( + [found xgettext program is not GNU xgettext; ignore it]) + XGETTEXT=":" + fi + dnl Remove leftover from FreeBSD xgettext call. + rm -f messages.po + fi + + AC_OUTPUT_COMMANDS([ + for ac_file in $CONFIG_FILES; do + # Support "outfile[:infile[:infile...]]" + case "$ac_file" in + *:*) ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + esac + # PO directories have a Makefile.in generated from Makefile.in.in. + case "$ac_file" in */Makefile.in) + # Adjust a relative srcdir. + ac_dir=`echo "$ac_file"|sed 's%/[^/][^/]*$%%'` + ac_dir_suffix="/`echo "$ac_dir"|sed 's%^\./%%'`" + ac_dots=`echo "$ac_dir_suffix"|sed 's%/[^/]*%../%g'` + # In autoconf-2.13 it is called $ac_given_srcdir. + # In autoconf-2.50 it is called $srcdir. + test -n "$ac_given_srcdir" || ac_given_srcdir="$srcdir" + case "$ac_given_srcdir" in + .) top_srcdir=`echo $ac_dots|sed 's%/$%%'` ;; + /*) top_srcdir="$ac_given_srcdir" ;; + *) top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + if test -f "$ac_given_srcdir/$ac_dir/POTFILES.in"; then + rm -f "$ac_dir/POTFILES" + test -n "$as_me" && echo "$as_me: creating $ac_dir/POTFILES" || echo "creating $ac_dir/POTFILES" + cat "$ac_given_srcdir/$ac_dir/POTFILES.in" | sed -e "/^#/d" -e "/^[ ]*\$/d" -e "s,.*, $top_srcdir/& \\\\," | sed -e "\$s/\(.*\) \\\\/\1/" > "$ac_dir/POTFILES" + POMAKEFILEDEPS="POTFILES.in" + # ALL_LINGUAS, POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES depend + # on $ac_dir but don't depend on user-specified configuration + # parameters. + if test -f "$ac_given_srcdir/$ac_dir/LINGUAS"; then + # The LINGUAS file contains the set of available languages. + if test -n "$OBSOLETE_ALL_LINGUAS"; then + test -n "$as_me" && echo "$as_me: setting ALL_LINGUAS in configure.in is obsolete" || echo "setting ALL_LINGUAS in configure.in is obsolete" + fi + ALL_LINGUAS_=`sed -e "/^#/d" "$ac_given_srcdir/$ac_dir/LINGUAS"` + # Hide the ALL_LINGUAS assigment from automake. + eval 'ALL_LINGUAS''=$ALL_LINGUAS_' + POMAKEFILEDEPS="$POMAKEFILEDEPS LINGUAS" + else + # The set of available languages was given in configure.in. + eval 'ALL_LINGUAS''=$OBSOLETE_ALL_LINGUAS' + fi + case "$ac_given_srcdir" in + .) srcdirpre= ;; + *) srcdirpre='$(srcdir)/' ;; + esac + POFILES= + GMOFILES= + UPDATEPOFILES= + DUMMYPOFILES= + for lang in $ALL_LINGUAS; do + POFILES="$POFILES $srcdirpre$lang.po" + GMOFILES="$GMOFILES $srcdirpre$lang.gmo" + UPDATEPOFILES="$UPDATEPOFILES $lang.po-update" + DUMMYPOFILES="$DUMMYPOFILES $lang.nop" + done + # CATALOGS depends on both $ac_dir and the user's LINGUAS + # environment variable. + INST_LINGUAS= + if test -n "$ALL_LINGUAS"; then + for presentlang in $ALL_LINGUAS; do + useit=no + if test "%UNSET%" != "$LINGUAS"; then + desiredlanguages="$LINGUAS" + else + desiredlanguages="$ALL_LINGUAS" + fi + for desiredlang in $desiredlanguages; do + # Use the presentlang catalog if desiredlang is + # a. equal to presentlang, or + # b. a variant of presentlang (because in this case, + # presentlang can be used as a fallback for messages + # which are not translated in the desiredlang catalog). + case "$desiredlang" in + "$presentlang"*) useit=yes;; + esac + done + if test $useit = yes; then + INST_LINGUAS="$INST_LINGUAS $presentlang" + fi + done + fi + CATALOGS= + if test -n "$INST_LINGUAS"; then + for lang in $INST_LINGUAS; do + CATALOGS="$CATALOGS $lang.gmo" + done + fi + test -n "$as_me" && echo "$as_me: creating $ac_dir/Makefile" || echo "creating $ac_dir/Makefile" + sed -e "/^POTFILES =/r $ac_dir/POTFILES" -e "/^# Makevars/r $ac_given_srcdir/$ac_dir/Makevars" -e "s|@POFILES@|$POFILES|g" -e "s|@GMOFILES@|$GMOFILES|g" -e "s|@UPDATEPOFILES@|$UPDATEPOFILES|g" -e "s|@DUMMYPOFILES@|$DUMMYPOFILES|g" -e "s|@CATALOGS@|$CATALOGS|g" -e "s|@POMAKEFILEDEPS@|$POMAKEFILEDEPS|g" "$ac_dir/Makefile.in" > "$ac_dir/Makefile" + for f in "$ac_given_srcdir/$ac_dir"/Rules-*; do + if test -f "$f"; then + case "$f" in + *.orig | *.bak | *~) ;; + *) cat "$f" >> "$ac_dir/Makefile" ;; + esac + fi + done + fi + ;; + esac + done], + [# Capture the value of obsolete ALL_LINGUAS because we need it to compute + # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it + # from automake. + eval 'OBSOLETE_ALL_LINGUAS''="$ALL_LINGUAS"' + # Capture the value of LINGUAS because we need it to compute CATALOGS. + LINGUAS="${LINGUAS-%UNSET%}" + ]) +]) +# progtest.m4 serial 3 (gettext-0.12) +dnl Copyright (C) 1996-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. +dnl +dnl This file can can be used in projects which are not available under +dnl the GNU General Public License or the GNU Library General Public +dnl License but which still want to provide support for the GNU gettext +dnl functionality. +dnl Please note that the actual code of the GNU gettext library is covered +dnl by the GNU Library General Public License, and the rest of the GNU +dnl gettext package package is covered by the GNU General Public License. +dnl They are *not* in the public domain. + +dnl Authors: +dnl Ulrich Drepper , 1996. + +# Search path for a program which passes the given test. + +dnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR, +dnl TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]]) +AC_DEFUN([AM_PATH_PROG_WITH_TEST], +[ +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "$2", so it can be a program name with args. +set dummy $2; ac_word=[$]2 +AC_MSG_CHECKING([for $ac_word]) +AC_CACHE_VAL(ac_cv_path_$1, +[case "[$]$1" in + [[\\/]]* | ?:[[\\/]]*) + ac_cv_path_$1="[$]$1" # Let the user override the test with a path. + ;; + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in ifelse([$5], , $PATH, [$5]); do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if [$3]; then + ac_cv_path_$1="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" +dnl If no 4th arg is given, leave the cache variable unset, +dnl so AC_PATH_PROGS will keep looking. +ifelse([$4], , , [ test -z "[$]ac_cv_path_$1" && ac_cv_path_$1="$4" +])dnl + ;; +esac])dnl +$1="$ac_cv_path_$1" +if test ifelse([$4], , [-n "[$]$1"], ["[$]$1" != "$4"]); then + AC_MSG_RESULT([$]$1) +else + AC_MSG_RESULT(no) +fi +AC_SUBST($1)dnl +]) +# stdint_h.m4 serial 3 (gettext-0.12) +dnl Copyright (C) 1997-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Paul Eggert. + +# Define HAVE_STDINT_H_WITH_UINTMAX if exists, +# doesn't clash with , and declares uintmax_t. + +AC_DEFUN([jm_AC_HEADER_STDINT_H], +[ + AC_CACHE_CHECK([for stdint.h], jm_ac_cv_header_stdint_h, + [AC_TRY_COMPILE( + [#include +#include ], + [uintmax_t i = (uintmax_t) -1;], + jm_ac_cv_header_stdint_h=yes, + jm_ac_cv_header_stdint_h=no)]) + if test $jm_ac_cv_header_stdint_h = yes; then + AC_DEFINE_UNQUOTED(HAVE_STDINT_H_WITH_UINTMAX, 1, + [Define if exists, doesn't clash with , + and declares uintmax_t. ]) + fi +]) +# uintmax_t.m4 serial 7 (gettext-0.12) +dnl Copyright (C) 1997-2003 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Paul Eggert. + +AC_PREREQ(2.13) + +# Define uintmax_t to 'unsigned long' or 'unsigned long long' +# if it is not already defined in or . + +AC_DEFUN([jm_AC_TYPE_UINTMAX_T], +[ + AC_REQUIRE([jm_AC_HEADER_INTTYPES_H]) + AC_REQUIRE([jm_AC_HEADER_STDINT_H]) + if test $jm_ac_cv_header_inttypes_h = no && test $jm_ac_cv_header_stdint_h = no; then + AC_REQUIRE([jm_AC_TYPE_UNSIGNED_LONG_LONG]) + test $ac_cv_type_unsigned_long_long = yes \ + && ac_type='unsigned long long' \ + || ac_type='unsigned long' + AC_DEFINE_UNQUOTED(uintmax_t, $ac_type, + [Define to unsigned long or unsigned long long + if and don't define.]) + else + AC_DEFINE(HAVE_UINTMAX_T, 1, + [Define if you have the 'uintmax_t' type in or .]) + fi +]) +# ulonglong.m4 serial 2 (fileutils-4.0.32, gettext-0.10.40) +dnl Copyright (C) 1999-2002 Free Software Foundation, Inc. +dnl This file is free software, distributed under the terms of the GNU +dnl General Public License. As a special exception to the GNU General +dnl Public License, this file may be distributed as part of a program +dnl that contains a configuration script generated by Autoconf, under +dnl the same distribution terms as the rest of that program. + +dnl From Paul Eggert. + +AC_DEFUN([jm_AC_TYPE_UNSIGNED_LONG_LONG], +[ + AC_CACHE_CHECK([for unsigned long long], ac_cv_type_unsigned_long_long, + [AC_TRY_LINK([unsigned long long ull = 1; int i = 63;], + [unsigned long long ullmax = (unsigned long long) -1; + return ull << i | ull >> i | ullmax / ull | ullmax % ull;], + ac_cv_type_unsigned_long_long=yes, + ac_cv_type_unsigned_long_long=no)]) + if test $ac_cv_type_unsigned_long_long = yes; then + AC_DEFINE(HAVE_UNSIGNED_LONG_LONG, 1, + [Define if you have the unsigned long long type.]) + fi +]) diff --git a/external/gpl3/gdb/dist/readline/ansi_stdlib.h b/external/gpl3/gdb/dist/readline/ansi_stdlib.h new file mode 100644 index 000000000000..db13cd234bdf --- /dev/null +++ b/external/gpl3/gdb/dist/readline/ansi_stdlib.h @@ -0,0 +1,54 @@ +/* ansi_stdlib.h -- An ANSI Standard stdlib.h. */ +/* A minimal stdlib.h containing extern declarations for those functions + that bash uses. */ + +/* Copyright (C) 1993 Free Software Foundation, Inc. + + This file is part of GNU Bash, the Bourne Again SHell. + + Bash is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + Bash is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with Bash; see the file COPYING. If not, write to the Free Software + Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_STDLIB_H_) +#define _STDLIB_H_ 1 + +/* String conversion functions. */ +extern int atoi (); + +extern double atof (); +extern double strtod (); + +/* Memory allocation functions. */ +/* Generic pointer type. */ +#ifndef PTR_T + +#if defined (__STDC__) +# define PTR_T void * +#else +# define PTR_T char * +#endif + +#endif /* PTR_T */ + +extern PTR_T malloc (); +extern PTR_T realloc (); +extern void free (); + +/* Other miscellaneous functions. */ +extern void abort (); +extern void exit (); +extern char *getenv (); +extern void qsort (); + +#endif /* _STDLIB_H */ diff --git a/external/gpl3/gdb/dist/readline/bind.c b/external/gpl3/gdb/dist/readline/bind.c new file mode 100644 index 000000000000..1ba28b4b673a --- /dev/null +++ b/external/gpl3/gdb/dist/readline/bind.c @@ -0,0 +1,2280 @@ +/* bind.c -- key binding and startup file support for the readline library. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#define READLINE_LIBRARY + +#if defined (__TANDEM) +# include +#endif + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include +#if defined (HAVE_SYS_FILE_H) +# include +#endif /* HAVE_SYS_FILE_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +#if !defined (errno) +extern int errno; +#endif /* !errno */ + +#include "posixstat.h" + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +#if !defined (strchr) && !defined (__STDC__) +extern char *strchr (), *strrchr (); +#endif /* !strchr && !__STDC__ */ + +/* Variables exported by this file. */ +Keymap rl_binding_keymap; + +static char *_rl_read_file PARAMS((char *, size_t *)); +static void _rl_init_file_error PARAMS((const char *)); +static int _rl_read_init_file PARAMS((const char *, int)); +static int glean_key_from_name PARAMS((char *)); +static int find_boolean_var PARAMS((const char *)); + +static char *_rl_get_string_variable_value PARAMS((const char *)); +static int substring_member_of_array PARAMS((char *, const char **)); + +static int currently_reading_init_file; + +/* used only in this file */ +static int _rl_prefer_visible_bell = 1; + +/* **************************************************************** */ +/* */ +/* Binding keys */ +/* */ +/* **************************************************************** */ + +/* rl_add_defun (char *name, rl_command_func_t *function, int key) + Add NAME to the list of named functions. Make FUNCTION be the function + that gets called. If KEY is not -1, then bind it. */ +int +rl_add_defun (name, function, key) + const char *name; + rl_command_func_t *function; + int key; +{ + if (key != -1) + rl_bind_key (key, function); + rl_add_funmap_entry (name, function); + return 0; +} + +/* Bind KEY to FUNCTION. Returns non-zero if KEY is out of range. */ +int +rl_bind_key (key, function) + int key; + rl_command_func_t *function; +{ + if (key < 0) + return (key); + + if (META_CHAR (key) && _rl_convert_meta_chars_to_ascii) + { + if (_rl_keymap[ESC].type == ISKMAP) + { + Keymap escmap; + + escmap = FUNCTION_TO_KEYMAP (_rl_keymap, ESC); + key = UNMETA (key); + escmap[key].type = ISFUNC; + escmap[key].function = function; + return (0); + } + return (key); + } + + _rl_keymap[key].type = ISFUNC; + _rl_keymap[key].function = function; + rl_binding_keymap = _rl_keymap; + return (0); +} + +/* Bind KEY to FUNCTION in MAP. Returns non-zero in case of invalid + KEY. */ +int +rl_bind_key_in_map (key, function, map) + int key; + rl_command_func_t *function; + Keymap map; +{ + int result; + Keymap oldmap; + + oldmap = _rl_keymap; + _rl_keymap = map; + result = rl_bind_key (key, function); + _rl_keymap = oldmap; + return (result); +} + +/* Bind key sequence KEYSEQ to DEFAULT_FUNC if KEYSEQ is unbound. Right + now, this is always used to attempt to bind the arrow keys, hence the + check for rl_vi_movement_mode. */ +int +rl_bind_key_if_unbound_in_map (key, default_func, kmap) + int key; + rl_command_func_t *default_func; + Keymap kmap; +{ + char keyseq[2]; + + keyseq[0] = (unsigned char)key; + keyseq[1] = '\0'; + return (rl_bind_keyseq_if_unbound_in_map (keyseq, default_func, kmap)); +} + +int +rl_bind_key_if_unbound (key, default_func) + int key; + rl_command_func_t *default_func; +{ + char keyseq[2]; + + keyseq[0] = (unsigned char)key; + keyseq[1] = '\0'; + return (rl_bind_keyseq_if_unbound_in_map (keyseq, default_func, _rl_keymap)); +} + +/* Make KEY do nothing in the currently selected keymap. + Returns non-zero in case of error. */ +int +rl_unbind_key (key) + int key; +{ + return (rl_bind_key (key, (rl_command_func_t *)NULL)); +} + +/* Make KEY do nothing in MAP. + Returns non-zero in case of error. */ +int +rl_unbind_key_in_map (key, map) + int key; + Keymap map; +{ + return (rl_bind_key_in_map (key, (rl_command_func_t *)NULL, map)); +} + +/* Unbind all keys bound to FUNCTION in MAP. */ +int +rl_unbind_function_in_map (func, map) + rl_command_func_t *func; + Keymap map; +{ + register int i, rval; + + for (i = rval = 0; i < KEYMAP_SIZE; i++) + { + if (map[i].type == ISFUNC && map[i].function == func) + { + map[i].function = (rl_command_func_t *)NULL; + rval = 1; + } + } + return rval; +} + +int +rl_unbind_command_in_map (command, map) + const char *command; + Keymap map; +{ + rl_command_func_t *func; + + func = rl_named_function (command); + if (func == 0) + return 0; + return (rl_unbind_function_in_map (func, map)); +} + +/* Bind the key sequence represented by the string KEYSEQ to + FUNCTION, starting in the current keymap. This makes new + keymaps as necessary. */ +int +rl_bind_keyseq (keyseq, function) + const char *keyseq; + rl_command_func_t *function; +{ + return (rl_generic_bind (ISFUNC, keyseq, (char *)function, _rl_keymap)); +} + +/* Bind the key sequence represented by the string KEYSEQ to + FUNCTION. This makes new keymaps as necessary. The initial + place to do bindings is in MAP. */ +int +rl_bind_keyseq_in_map (keyseq, function, map) + const char *keyseq; + rl_command_func_t *function; + Keymap map; +{ + return (rl_generic_bind (ISFUNC, keyseq, (char *)function, map)); +} + +/* Backwards compatibility; equivalent to rl_bind_keyseq_in_map() */ +int +rl_set_key (keyseq, function, map) + const char *keyseq; + rl_command_func_t *function; + Keymap map; +{ + return (rl_generic_bind (ISFUNC, keyseq, (char *)function, map)); +} + +/* Bind key sequence KEYSEQ to DEFAULT_FUNC if KEYSEQ is unbound. Right + now, this is always used to attempt to bind the arrow keys, hence the + check for rl_vi_movement_mode. */ +int +rl_bind_keyseq_if_unbound_in_map (keyseq, default_func, kmap) + const char *keyseq; + rl_command_func_t *default_func; + Keymap kmap; +{ + rl_command_func_t *func; + + if (keyseq) + { + func = rl_function_of_keyseq (keyseq, kmap, (int *)NULL); +#if defined (VI_MODE) + if (!func || func == rl_do_lowercase_version || func == rl_vi_movement_mode) +#else + if (!func || func == rl_do_lowercase_version) +#endif + return (rl_bind_keyseq_in_map (keyseq, default_func, kmap)); + else + return 1; + } + return 0; +} + +int +rl_bind_keyseq_if_unbound (keyseq, default_func) + const char *keyseq; + rl_command_func_t *default_func; +{ + return (rl_bind_keyseq_if_unbound_in_map (keyseq, default_func, _rl_keymap)); +} + +/* Bind the key sequence represented by the string KEYSEQ to + the string of characters MACRO. This makes new keymaps as + necessary. The initial place to do bindings is in MAP. */ +int +rl_macro_bind (keyseq, macro, map) + const char *keyseq, *macro; + Keymap map; +{ + char *macro_keys; + int macro_keys_len; + + macro_keys = (char *)xmalloc ((2 * strlen (macro)) + 1); + + if (rl_translate_keyseq (macro, macro_keys, ¯o_keys_len)) + { + free (macro_keys); + return -1; + } + rl_generic_bind (ISMACR, keyseq, macro_keys, map); + return 0; +} + +/* Bind the key sequence represented by the string KEYSEQ to + the arbitrary pointer DATA. TYPE says what kind of data is + pointed to by DATA, right now this can be a function (ISFUNC), + a macro (ISMACR), or a keymap (ISKMAP). This makes new keymaps + as necessary. The initial place to do bindings is in MAP. */ +int +rl_generic_bind (type, keyseq, data, map) + int type; + const char *keyseq; + char *data; + Keymap map; +{ + char *keys; + int keys_len; + register int i; + KEYMAP_ENTRY k; + + k.function = 0; + + /* If no keys to bind to, exit right away. */ + if (keyseq == 0 || *keyseq == 0) + { + if (type == ISMACR) + free (data); + return -1; + } + + keys = (char *)xmalloc (1 + (2 * strlen (keyseq))); + + /* Translate the ASCII representation of KEYSEQ into an array of + characters. Stuff the characters into KEYS, and the length of + KEYS into KEYS_LEN. */ + if (rl_translate_keyseq (keyseq, keys, &keys_len)) + { + free (keys); + return -1; + } + + /* Bind keys, making new keymaps as necessary. */ + for (i = 0; i < keys_len; i++) + { + unsigned char uc = keys[i]; + int ic; + + ic = uc; + if (ic < 0 || ic >= KEYMAP_SIZE) + return -1; + + if (META_CHAR (ic) && _rl_convert_meta_chars_to_ascii) + { + ic = UNMETA (ic); + if (map[ESC].type == ISKMAP) + map = FUNCTION_TO_KEYMAP (map, ESC); + } + + if ((i + 1) < keys_len) + { + if (map[ic].type != ISKMAP) + { + /* We allow subsequences of keys. If a keymap is being + created that will `shadow' an existing function or macro + key binding, we save that keybinding into the ANYOTHERKEY + index in the new map. The dispatch code will look there + to find the function to execute if the subsequence is not + matched. ANYOTHERKEY was chosen to be greater than + UCHAR_MAX. */ + k = map[ic]; + + map[ic].type = ISKMAP; + map[ic].function = KEYMAP_TO_FUNCTION (rl_make_bare_keymap()); + } + map = FUNCTION_TO_KEYMAP (map, ic); + /* The dispatch code will return this function if no matching + key sequence is found in the keymap. This (with a little + help from the dispatch code in readline.c) allows `a' to be + mapped to something, `abc' to be mapped to something else, + and the function bound to `a' to be executed when the user + types `abx', leaving `bx' in the input queue. */ + if (k.function && ((k.type == ISFUNC && k.function != rl_do_lowercase_version) || k.type == ISMACR)) + { + map[ANYOTHERKEY] = k; + k.function = 0; + } + } + else + { + if (map[ic].type == ISMACR) + free ((char *)map[ic].function); + else if (map[ic].type == ISKMAP) + { + map = FUNCTION_TO_KEYMAP (map, ic); + ic = ANYOTHERKEY; + } + + map[ic].function = KEYMAP_TO_FUNCTION (data); + map[ic].type = type; + } + + rl_binding_keymap = map; + } + free (keys); + return 0; +} + +/* Translate the ASCII representation of SEQ, stuffing the values into ARRAY, + an array of characters. LEN gets the final length of ARRAY. Return + non-zero if there was an error parsing SEQ. */ +int +rl_translate_keyseq (seq, array, len) + const char *seq; + char *array; + int *len; +{ + register int i, c, l, temp; + + for (i = l = 0; c = seq[i]; i++) + { + if (c == '\\') + { + c = seq[++i]; + + if (c == 0) + break; + + /* Handle \C- and \M- prefixes. */ + if ((c == 'C' || c == 'M') && seq[i + 1] == '-') + { + /* Handle special case of backwards define. */ + if (strncmp (&seq[i], "C-\\M-", 5) == 0) + { + array[l++] = ESC; /* ESC is meta-prefix */ + i += 5; + array[l++] = CTRL (_rl_to_upper (seq[i])); + if (seq[i] == '\0') + i--; + } + else if (c == 'M') + { + i++; + /* XXX - should obey convert-meta setting? */ + if (_rl_convert_meta_chars_to_ascii && _rl_keymap[ESC].type == ISKMAP) + array[l++] = ESC; /* ESC is meta-prefix */ + else + { + i++; + array[l++] = META (seq[i]); + } + } + else if (c == 'C') + { + i += 2; + /* Special hack for C-?... */ + array[l++] = (seq[i] == '?') ? RUBOUT : CTRL (_rl_to_upper (seq[i])); + } + continue; + } + + /* Translate other backslash-escaped characters. These are the + same escape sequences that bash's `echo' and `printf' builtins + handle, with the addition of \d -> RUBOUT. A backslash + preceding a character that is not special is stripped. */ + switch (c) + { + case 'a': + array[l++] = '\007'; + break; + case 'b': + array[l++] = '\b'; + break; + case 'd': + array[l++] = RUBOUT; /* readline-specific */ + break; + case 'e': + array[l++] = ESC; + break; + case 'f': + array[l++] = '\f'; + break; + case 'n': + array[l++] = NEWLINE; + break; + case 'r': + array[l++] = RETURN; + break; + case 't': + array[l++] = TAB; + break; + case 'v': + array[l++] = 0x0B; + break; + case '\\': + array[l++] = '\\'; + break; + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + i++; + for (temp = 2, c -= '0'; ISOCTAL (seq[i]) && temp--; i++) + c = (c * 8) + OCTVALUE (seq[i]); + i--; /* auto-increment in for loop */ + array[l++] = c & largest_char; + break; + case 'x': + i++; + for (temp = 2, c = 0; ISXDIGIT ((unsigned char)seq[i]) && temp--; i++) + c = (c * 16) + HEXVALUE (seq[i]); + if (temp == 2) + c = 'x'; + i--; /* auto-increment in for loop */ + array[l++] = c & largest_char; + break; + default: /* backslashes before non-special chars just add the char */ + array[l++] = c; + break; /* the backslash is stripped */ + } + continue; + } + + array[l++] = c; + } + + *len = l; + array[l] = '\0'; + return (0); +} + +char * +rl_untranslate_keyseq (seq) + int seq; +{ + static char kseq[16]; + int i, c; + + i = 0; + c = seq; + if (META_CHAR (c)) + { + kseq[i++] = '\\'; + kseq[i++] = 'M'; + kseq[i++] = '-'; + c = UNMETA (c); + } + else if (CTRL_CHAR (c)) + { + kseq[i++] = '\\'; + kseq[i++] = 'C'; + kseq[i++] = '-'; + c = _rl_to_lower (UNCTRL (c)); + } + else if (c == RUBOUT) + { + kseq[i++] = '\\'; + kseq[i++] = 'C'; + kseq[i++] = '-'; + c = '?'; + } + + if (c == ESC) + { + kseq[i++] = '\\'; + c = 'e'; + } + else if (c == '\\' || c == '"') + { + kseq[i++] = '\\'; + } + + kseq[i++] = (unsigned char) c; + kseq[i] = '\0'; + return kseq; +} + +static char * +_rl_untranslate_macro_value (seq) + char *seq; +{ + char *ret, *r, *s; + int c; + + r = ret = (char *)xmalloc (7 * strlen (seq) + 1); + for (s = seq; *s; s++) + { + c = *s; + if (META_CHAR (c)) + { + *r++ = '\\'; + *r++ = 'M'; + *r++ = '-'; + c = UNMETA (c); + } + else if (CTRL_CHAR (c) && c != ESC) + { + *r++ = '\\'; + *r++ = 'C'; + *r++ = '-'; + c = _rl_to_lower (UNCTRL (c)); + } + else if (c == RUBOUT) + { + *r++ = '\\'; + *r++ = 'C'; + *r++ = '-'; + c = '?'; + } + + if (c == ESC) + { + *r++ = '\\'; + c = 'e'; + } + else if (c == '\\' || c == '"') + *r++ = '\\'; + + *r++ = (unsigned char)c; + } + *r = '\0'; + return ret; +} + +/* Return a pointer to the function that STRING represents. + If STRING doesn't have a matching function, then a NULL pointer + is returned. */ +rl_command_func_t * +rl_named_function (string) + const char *string; +{ + register int i; + + rl_initialize_funmap (); + + for (i = 0; funmap[i]; i++) + if (_rl_stricmp (funmap[i]->name, string) == 0) + return (funmap[i]->function); + return ((rl_command_func_t *)NULL); +} + +/* Return the function (or macro) definition which would be invoked via + KEYSEQ if executed in MAP. If MAP is NULL, then the current keymap is + used. TYPE, if non-NULL, is a pointer to an int which will receive the + type of the object pointed to. One of ISFUNC (function), ISKMAP (keymap), + or ISMACR (macro). */ +rl_command_func_t * +rl_function_of_keyseq (keyseq, map, type) + const char *keyseq; + Keymap map; + int *type; +{ + register int i; + + if (!map) + map = _rl_keymap; + + for (i = 0; keyseq && keyseq[i]; i++) + { + unsigned char ic = keyseq[i]; + + if (META_CHAR (ic) && _rl_convert_meta_chars_to_ascii) + { + if (map[ESC].type != ISKMAP) + { + if (type) + *type = map[ESC].type; + + return (map[ESC].function); + } + else + { + map = FUNCTION_TO_KEYMAP (map, ESC); + ic = UNMETA (ic); + } + } + + if (map[ic].type == ISKMAP) + { + /* If this is the last key in the key sequence, return the + map. */ + if (!keyseq[i + 1]) + { + if (type) + *type = ISKMAP; + + return (map[ic].function); + } + else + map = FUNCTION_TO_KEYMAP (map, ic); + } + else + { + if (type) + *type = map[ic].type; + + return (map[ic].function); + } + } + return ((rl_command_func_t *) NULL); +} + +/* The last key bindings file read. */ +static char *last_readline_init_file = (char *)NULL; + +/* The file we're currently reading key bindings from. */ +static const char *current_readline_init_file; +static int current_readline_init_include_level; +static int current_readline_init_lineno; + +/* Read FILENAME into a locally-allocated buffer and return the buffer. + The size of the buffer is returned in *SIZEP. Returns NULL if any + errors were encountered. */ +static char * +_rl_read_file (filename, sizep) + char *filename; + size_t *sizep; +{ + struct stat finfo; + size_t file_size; + char *buffer; + int i, file; + + if ((stat (filename, &finfo) < 0) || (file = open (filename, O_RDONLY, 0666)) < 0) + return ((char *)NULL); + + file_size = (size_t)finfo.st_size; + + /* check for overflow on very large files */ + if (file_size != finfo.st_size || file_size + 1 < file_size) + { + if (file >= 0) + close (file); +#if defined (EFBIG) + errno = EFBIG; +#endif + return ((char *)NULL); + } + + /* Read the file into BUFFER. */ + buffer = (char *)xmalloc (file_size + 1); + i = read (file, buffer, file_size); + close (file); + + if (i < 0) + { + free (buffer); + return ((char *)NULL); + } + + buffer[i] = '\0'; + if (sizep) + *sizep = i; + + return (buffer); +} + +/* Re-read the current keybindings file. */ +int +rl_re_read_init_file (count, ignore) + int count, ignore; +{ + int r; + r = rl_read_init_file ((const char *)NULL); + rl_set_keymap_from_edit_mode (); + return r; +} + +/* Do key bindings from a file. If FILENAME is NULL it defaults + to the first non-null filename from this list: + 1. the filename used for the previous call + 2. the value of the shell variable `INPUTRC' + 3. ~/.inputrc + If the file existed and could be opened and read, 0 is returned, + otherwise errno is returned. */ +int +rl_read_init_file (filename) + const char *filename; +{ + /* Default the filename. */ + if (filename == 0) + { + filename = last_readline_init_file; + if (filename == 0) + filename = sh_get_env_value ("INPUTRC"); + if (filename == 0) + filename = DEFAULT_INPUTRC; + } + + if (*filename == 0) + filename = DEFAULT_INPUTRC; + +#if defined (__MSDOS__) + if (_rl_read_init_file (filename, 0) == 0) + return 0; + filename = "~/_inputrc"; +#endif + return (_rl_read_init_file (filename, 0)); +} + +static int +_rl_read_init_file (filename, include_level) + const char *filename; + int include_level; +{ + register int i; + char *buffer, *openname, *line, *end; + size_t file_size; + + current_readline_init_file = filename; + current_readline_init_include_level = include_level; + + openname = tilde_expand (filename); + buffer = _rl_read_file (openname, &file_size); + free (openname); + + if (buffer == 0) + return (errno); + + if (include_level == 0 && filename != last_readline_init_file) + { + FREE (last_readline_init_file); + last_readline_init_file = savestring (filename); + } + + currently_reading_init_file = 1; + + /* Loop over the lines in the file. Lines that start with `#' are + comments; all other lines are commands for readline initialization. */ + current_readline_init_lineno = 1; + line = buffer; + end = buffer + file_size; + while (line < end) + { + /* Find the end of this line. */ + for (i = 0; line + i != end && line[i] != '\n'; i++); + +#if defined (__CYGWIN__) + /* ``Be liberal in what you accept.'' */ + if (line[i] == '\n' && line[i-1] == '\r') + line[i - 1] = '\0'; +#endif + + /* Mark end of line. */ + line[i] = '\0'; + + /* Skip leading whitespace. */ + while (*line && whitespace (*line)) + { + line++; + i--; + } + + /* If the line is not a comment, then parse it. */ + if (*line && *line != '#') + rl_parse_and_bind (line); + + /* Move to the next line. */ + line += i + 1; + current_readline_init_lineno++; + } + + free (buffer); + currently_reading_init_file = 0; + return (0); +} + +static void +_rl_init_file_error (msg) + const char *msg; +{ + if (currently_reading_init_file) + fprintf (stderr, "readline: %s: line %d: %s\n", current_readline_init_file, + current_readline_init_lineno, msg); + else + fprintf (stderr, "readline: %s\n", msg); +} + +/* **************************************************************** */ +/* */ +/* Parser Directives */ +/* */ +/* **************************************************************** */ + +typedef int _rl_parser_func_t PARAMS((char *)); + +/* Things that mean `Control'. */ +const char *_rl_possible_control_prefixes[] = { + "Control-", "C-", "CTRL-", (const char *)NULL +}; + +const char *_rl_possible_meta_prefixes[] = { + "Meta", "M-", (const char *)NULL +}; + +/* Conditionals. */ + +/* Calling programs set this to have their argv[0]. */ +const char *rl_readline_name = "other"; + +/* Stack of previous values of parsing_conditionalized_out. */ +static unsigned char *if_stack = (unsigned char *)NULL; +static int if_stack_depth; +static int if_stack_size; + +/* Push _rl_parsing_conditionalized_out, and set parser state based + on ARGS. */ +static int +parser_if (args) + char *args; +{ + register int i; + + /* Push parser state. */ + if (if_stack_depth + 1 >= if_stack_size) + { + if (!if_stack) + if_stack = (unsigned char *)xmalloc (if_stack_size = 20); + else + if_stack = (unsigned char *)xrealloc (if_stack, if_stack_size += 20); + } + if_stack[if_stack_depth++] = _rl_parsing_conditionalized_out; + + /* If parsing is turned off, then nothing can turn it back on except + for finding the matching endif. In that case, return right now. */ + if (_rl_parsing_conditionalized_out) + return 0; + + /* Isolate first argument. */ + for (i = 0; args[i] && !whitespace (args[i]); i++); + + if (args[i]) + args[i++] = '\0'; + + /* Handle "$if term=foo" and "$if mode=emacs" constructs. If this + isn't term=foo, or mode=emacs, then check to see if the first + word in ARGS is the same as the value stored in rl_readline_name. */ + if (rl_terminal_name && _rl_strnicmp (args, "term=", 5) == 0) + { + char *tem, *tname; + + /* Terminals like "aaa-60" are equivalent to "aaa". */ + tname = savestring (rl_terminal_name); + tem = strchr (tname, '-'); + if (tem) + *tem = '\0'; + + /* Test the `long' and `short' forms of the terminal name so that + if someone has a `sun-cmd' and does not want to have bindings + that will be executed if the terminal is a `sun', they can put + `$if term=sun-cmd' into their .inputrc. */ + _rl_parsing_conditionalized_out = _rl_stricmp (args + 5, tname) && + _rl_stricmp (args + 5, rl_terminal_name); + free (tname); + } +#if defined (VI_MODE) + else if (_rl_strnicmp (args, "mode=", 5) == 0) + { + int mode; + + if (_rl_stricmp (args + 5, "emacs") == 0) + mode = emacs_mode; + else if (_rl_stricmp (args + 5, "vi") == 0) + mode = vi_mode; + else + mode = no_mode; + + _rl_parsing_conditionalized_out = mode != rl_editing_mode; + } +#endif /* VI_MODE */ + /* Check to see if the first word in ARGS is the same as the + value stored in rl_readline_name. */ + else if (_rl_stricmp (args, rl_readline_name) == 0) + _rl_parsing_conditionalized_out = 0; + else + _rl_parsing_conditionalized_out = 1; + return 0; +} + +/* Invert the current parser state if there is anything on the stack. */ +static int +parser_else (args) + char *args; +{ + register int i; + + if (if_stack_depth == 0) + { + _rl_init_file_error ("$else found without matching $if"); + return 0; + } + +#if 0 + /* Check the previous (n - 1) levels of the stack to make sure that + we haven't previously turned off parsing. */ + for (i = 0; i < if_stack_depth - 1; i++) +#else + /* Check the previous (n) levels of the stack to make sure that + we haven't previously turned off parsing. */ + for (i = 0; i < if_stack_depth; i++) +#endif + if (if_stack[i] == 1) + return 0; + + /* Invert the state of parsing if at top level. */ + _rl_parsing_conditionalized_out = !_rl_parsing_conditionalized_out; + return 0; +} + +/* Terminate a conditional, popping the value of + _rl_parsing_conditionalized_out from the stack. */ +static int +parser_endif (args) + char *args; +{ + if (if_stack_depth) + _rl_parsing_conditionalized_out = if_stack[--if_stack_depth]; + else + _rl_init_file_error ("$endif without matching $if"); + return 0; +} + +static int +parser_include (args) + char *args; +{ + const char *old_init_file; + char *e; + int old_line_number, old_include_level, r; + + if (_rl_parsing_conditionalized_out) + return (0); + + old_init_file = current_readline_init_file; + old_line_number = current_readline_init_lineno; + old_include_level = current_readline_init_include_level; + + e = strchr (args, '\n'); + if (e) + *e = '\0'; + r = _rl_read_init_file ((const char *)args, old_include_level + 1); + + current_readline_init_file = old_init_file; + current_readline_init_lineno = old_line_number; + current_readline_init_include_level = old_include_level; + + return r; +} + +/* Associate textual names with actual functions. */ +static struct { + const char *name; + _rl_parser_func_t *function; +} parser_directives [] = { + { "if", parser_if }, + { "endif", parser_endif }, + { "else", parser_else }, + { "include", parser_include }, + { (char *)0x0, (_rl_parser_func_t *)0x0 } +}; + +/* Handle a parser directive. STATEMENT is the line of the directive + without any leading `$'. */ +static int +handle_parser_directive (statement) + char *statement; +{ + register int i; + char *directive, *args; + + /* Isolate the actual directive. */ + + /* Skip whitespace. */ + for (i = 0; whitespace (statement[i]); i++); + + directive = &statement[i]; + + for (; statement[i] && !whitespace (statement[i]); i++); + + if (statement[i]) + statement[i++] = '\0'; + + for (; statement[i] && whitespace (statement[i]); i++); + + args = &statement[i]; + + /* Lookup the command, and act on it. */ + for (i = 0; parser_directives[i].name; i++) + if (_rl_stricmp (directive, parser_directives[i].name) == 0) + { + (*parser_directives[i].function) (args); + return (0); + } + + /* display an error message about the unknown parser directive */ + _rl_init_file_error ("unknown parser directive"); + return (1); +} + +/* Read the binding command from STRING and perform it. + A key binding command looks like: Keyname: function-name\0, + a variable binding command looks like: set variable value. + A new-style keybinding looks like "\C-x\C-x": exchange-point-and-mark. */ +int +rl_parse_and_bind (string) + char *string; +{ + char *funname, *kname; + register int c, i; + int key, equivalency; + + while (string && whitespace (*string)) + string++; + + if (!string || !*string || *string == '#') + return 0; + + /* If this is a parser directive, act on it. */ + if (*string == '$') + { + handle_parser_directive (&string[1]); + return 0; + } + + /* If we aren't supposed to be parsing right now, then we're done. */ + if (_rl_parsing_conditionalized_out) + return 0; + + i = 0; + /* If this keyname is a complex key expression surrounded by quotes, + advance to after the matching close quote. This code allows the + backslash to quote characters in the key expression. */ + if (*string == '"') + { + int passc = 0; + + for (i = 1; c = string[i]; i++) + { + if (passc) + { + passc = 0; + continue; + } + + if (c == '\\') + { + passc++; + continue; + } + + if (c == '"') + break; + } + /* If we didn't find a closing quote, abort the line. */ + if (string[i] == '\0') + { + _rl_init_file_error ("no closing `\"' in key binding"); + return 1; + } + } + + /* Advance to the colon (:) or whitespace which separates the two objects. */ + for (; (c = string[i]) && c != ':' && c != ' ' && c != '\t'; i++ ); + + equivalency = (c == ':' && string[i + 1] == '='); + + /* Mark the end of the command (or keyname). */ + if (string[i]) + string[i++] = '\0'; + + /* If doing assignment, skip the '=' sign as well. */ + if (equivalency) + string[i++] = '\0'; + + /* If this is a command to set a variable, then do that. */ + if (_rl_stricmp (string, "set") == 0) + { + char *var, *value, *e; + + var = string + i; + /* Make VAR point to start of variable name. */ + while (*var && whitespace (*var)) var++; + + /* Make VALUE point to start of value string. */ + value = var; + while (*value && !whitespace (*value)) value++; + if (*value) + *value++ = '\0'; + while (*value && whitespace (*value)) value++; + + /* Strip trailing whitespace from values to boolean variables. Temp + fix until I get a real quoted-string parser here. */ + i = find_boolean_var (var); + if (i >= 0) + { + /* remove trailing whitespace */ + e = value + strlen (value) - 1; + while (e >= value && whitespace (*e)) + e--; + e++; /* skip back to whitespace or EOS */ + if (*e && e >= value) + *e = '\0'; + } + + rl_variable_bind (var, value); + return 0; + } + + /* Skip any whitespace between keyname and funname. */ + for (; string[i] && whitespace (string[i]); i++); + funname = &string[i]; + + /* Now isolate funname. + For straight function names just look for whitespace, since + that will signify the end of the string. But this could be a + macro definition. In that case, the string is quoted, so skip + to the matching delimiter. We allow the backslash to quote the + delimiter characters in the macro body. */ + /* This code exists to allow whitespace in macro expansions, which + would otherwise be gobbled up by the next `for' loop.*/ + /* XXX - it may be desirable to allow backslash quoting only if " is + the quoted string delimiter, like the shell. */ + if (*funname == '\'' || *funname == '"') + { + int delimiter, passc; + + delimiter = string[i++]; + for (passc = 0; c = string[i]; i++) + { + if (passc) + { + passc = 0; + continue; + } + + if (c == '\\') + { + passc = 1; + continue; + } + + if (c == delimiter) + break; + } + if (c) + i++; + } + + /* Advance to the end of the string. */ + for (; string[i] && !whitespace (string[i]); i++); + + /* No extra whitespace at the end of the string. */ + string[i] = '\0'; + + /* Handle equivalency bindings here. Make the left-hand side be exactly + whatever the right-hand evaluates to, including keymaps. */ + if (equivalency) + { + return 0; + } + + /* If this is a new-style key-binding, then do the binding with + rl_bind_keyseq (). Otherwise, let the older code deal with it. */ + if (*string == '"') + { + char *seq; + register int j, k, passc; + + seq = (char *)xmalloc (1 + strlen (string)); + for (j = 1, k = passc = 0; string[j]; j++) + { + /* Allow backslash to quote characters, but leave them in place. + This allows a string to end with a backslash quoting another + backslash, or with a backslash quoting a double quote. The + backslashes are left in place for rl_translate_keyseq (). */ + if (passc || (string[j] == '\\')) + { + seq[k++] = string[j]; + passc = !passc; + continue; + } + + if (string[j] == '"') + break; + + seq[k++] = string[j]; + } + seq[k] = '\0'; + + /* Binding macro? */ + if (*funname == '\'' || *funname == '"') + { + j = strlen (funname); + + /* Remove the delimiting quotes from each end of FUNNAME. */ + if (j && funname[j - 1] == *funname) + funname[j - 1] = '\0'; + + rl_macro_bind (seq, &funname[1], _rl_keymap); + } + else + rl_bind_keyseq (seq, rl_named_function (funname)); + + free (seq); + return 0; + } + + /* Get the actual character we want to deal with. */ + kname = strrchr (string, '-'); + if (!kname) + kname = string; + else + kname++; + + key = glean_key_from_name (kname); + + /* Add in control and meta bits. */ + if (substring_member_of_array (string, _rl_possible_control_prefixes)) + key = CTRL (_rl_to_upper (key)); + + if (substring_member_of_array (string, _rl_possible_meta_prefixes)) + key = META (key); + + /* Temporary. Handle old-style keyname with macro-binding. */ + if (*funname == '\'' || *funname == '"') + { + char useq[2]; + int fl = strlen (funname); + + useq[0] = key; useq[1] = '\0'; + if (fl && funname[fl - 1] == *funname) + funname[fl - 1] = '\0'; + + rl_macro_bind (useq, &funname[1], _rl_keymap); + } +#if defined (PREFIX_META_HACK) + /* Ugly, but working hack to keep prefix-meta around. */ + else if (_rl_stricmp (funname, "prefix-meta") == 0) + { + char seq[2]; + + seq[0] = key; + seq[1] = '\0'; + rl_generic_bind (ISKMAP, seq, (char *)emacs_meta_keymap, _rl_keymap); + } +#endif /* PREFIX_META_HACK */ + else + rl_bind_key (key, rl_named_function (funname)); + return 0; +} + +/* Simple structure for boolean readline variables (i.e., those that can + have one of two values; either "On" or 1 for truth, or "Off" or 0 for + false. */ + +#define V_SPECIAL 0x1 + +static struct { + const char *name; + int *value; + int flags; +} boolean_varlist [] = { + { "bind-tty-special-chars", &_rl_bind_stty_chars, 0 }, + { "blink-matching-paren", &rl_blink_matching_paren, V_SPECIAL }, + { "byte-oriented", &rl_byte_oriented, 0 }, + { "completion-ignore-case", &_rl_completion_case_fold, 0 }, + { "convert-meta", &_rl_convert_meta_chars_to_ascii, 0 }, + { "disable-completion", &rl_inhibit_completion, 0 }, + { "enable-keypad", &_rl_enable_keypad, 0 }, + { "expand-tilde", &rl_complete_with_tilde_expansion, 0 }, + { "history-preserve-point", &_rl_history_preserve_point, 0 }, + { "horizontal-scroll-mode", &_rl_horizontal_scroll_mode, 0 }, + { "input-meta", &_rl_meta_flag, 0 }, + { "mark-directories", &_rl_complete_mark_directories, 0 }, + { "mark-modified-lines", &_rl_mark_modified_lines, 0 }, + { "mark-symlinked-directories", &_rl_complete_mark_symlink_dirs, 0 }, + { "match-hidden-files", &_rl_match_hidden_files, 0 }, + { "meta-flag", &_rl_meta_flag, 0 }, + { "output-meta", &_rl_output_meta_chars, 0 }, + { "page-completions", &_rl_page_completions, 0 }, + { "prefer-visible-bell", &_rl_prefer_visible_bell, V_SPECIAL }, + { "print-completions-horizontally", &_rl_print_completions_horizontally, 0 }, + { "show-all-if-ambiguous", &_rl_complete_show_all, 0 }, + { "show-all-if-unmodified", &_rl_complete_show_unmodified, 0 }, +#if defined (VISIBLE_STATS) + { "visible-stats", &rl_visible_stats, 0 }, +#endif /* VISIBLE_STATS */ + { (char *)NULL, (int *)NULL } +}; + +static int +find_boolean_var (name) + const char *name; +{ + register int i; + + for (i = 0; boolean_varlist[i].name; i++) + if (_rl_stricmp (name, boolean_varlist[i].name) == 0) + return i; + return -1; +} + +/* Hooks for handling special boolean variables, where a + function needs to be called or another variable needs + to be changed when they're changed. */ +static void +hack_special_boolean_var (i) + int i; +{ + const char *name; + + name = boolean_varlist[i].name; + + if (_rl_stricmp (name, "blink-matching-paren") == 0) + _rl_enable_paren_matching (rl_blink_matching_paren); + else if (_rl_stricmp (name, "prefer-visible-bell") == 0) + { + if (_rl_prefer_visible_bell) + _rl_bell_preference = VISIBLE_BELL; + else + _rl_bell_preference = AUDIBLE_BELL; + } +} + +typedef int _rl_sv_func_t PARAMS((const char *)); + +/* These *must* correspond to the array indices for the appropriate + string variable. (Though they're not used right now.) */ +#define V_BELLSTYLE 0 +#define V_COMBEGIN 1 +#define V_EDITMODE 2 +#define V_ISRCHTERM 3 +#define V_KEYMAP 4 + +#define V_STRING 1 +#define V_INT 2 + +/* Forward declarations */ +static int sv_bell_style PARAMS((const char *)); +static int sv_combegin PARAMS((const char *)); +static int sv_compquery PARAMS((const char *)); +static int sv_editmode PARAMS((const char *)); +static int sv_isrchterm PARAMS((const char *)); +static int sv_keymap PARAMS((const char *)); + +static struct { + const char *name; + int flags; + _rl_sv_func_t *set_func; +} string_varlist[] = { + { "bell-style", V_STRING, sv_bell_style }, + { "comment-begin", V_STRING, sv_combegin }, + { "completion-query-items", V_INT, sv_compquery }, + { "editing-mode", V_STRING, sv_editmode }, + { "isearch-terminators", V_STRING, sv_isrchterm }, + { "keymap", V_STRING, sv_keymap }, + { (char *)NULL, 0 } +}; + +static int +find_string_var (name) + const char *name; +{ + register int i; + + for (i = 0; string_varlist[i].name; i++) + if (_rl_stricmp (name, string_varlist[i].name) == 0) + return i; + return -1; +} + +/* A boolean value that can appear in a `set variable' command is true if + the value is null or empty, `on' (case-insenstive), or "1". Any other + values result in 0 (false). */ +static int +bool_to_int (value) + const char *value; +{ + return (value == 0 || *value == '\0' || + (_rl_stricmp (value, "on") == 0) || + (value[0] == '1' && value[1] == '\0')); +} + +char * +rl_variable_value (name) + const char *name; +{ + register int i; + int v; + char *ret; + + /* Check for simple variables first. */ + i = find_boolean_var (name); + if (i >= 0) + return (*boolean_varlist[i].value ? "on" : "off"); + + i = find_string_var (name); + if (i >= 0) + return (_rl_get_string_variable_value (string_varlist[i].name)); + + /* Unknown variable names return NULL. */ + return 0; +} + +int +rl_variable_bind (name, value) + const char *name, *value; +{ + register int i; + int v; + + /* Check for simple variables first. */ + i = find_boolean_var (name); + if (i >= 0) + { + *boolean_varlist[i].value = bool_to_int (value); + if (boolean_varlist[i].flags & V_SPECIAL) + hack_special_boolean_var (i); + return 0; + } + + i = find_string_var (name); + + /* For the time being, unknown variable names or string names without a + handler function are simply ignored. */ + if (i < 0 || string_varlist[i].set_func == 0) + return 0; + + v = (*string_varlist[i].set_func) (value); + return v; +} + +static int +sv_editmode (value) + const char *value; +{ + if (_rl_strnicmp (value, "vi", 2) == 0) + { +#if defined (VI_MODE) + _rl_keymap = vi_insertion_keymap; + rl_editing_mode = vi_mode; +#endif /* VI_MODE */ + return 0; + } + else if (_rl_strnicmp (value, "emacs", 5) == 0) + { + _rl_keymap = emacs_standard_keymap; + rl_editing_mode = emacs_mode; + return 0; + } + return 1; +} + +static int +sv_combegin (value) + const char *value; +{ + if (value && *value) + { + FREE (_rl_comment_begin); + _rl_comment_begin = savestring (value); + return 0; + } + return 1; +} + +static int +sv_compquery (value) + const char *value; +{ + int nval = 100; + + if (value && *value) + { + nval = atoi (value); + if (nval < 0) + nval = 0; + } + rl_completion_query_items = nval; + return 0; +} + +static int +sv_keymap (value) + const char *value; +{ + Keymap kmap; + + kmap = rl_get_keymap_by_name (value); + if (kmap) + { + rl_set_keymap (kmap); + return 0; + } + return 1; +} + +static int +sv_bell_style (value) + const char *value; +{ + if (value == 0 || *value == '\0') + _rl_bell_preference = AUDIBLE_BELL; + else if (_rl_stricmp (value, "none") == 0 || _rl_stricmp (value, "off") == 0) + _rl_bell_preference = NO_BELL; + else if (_rl_stricmp (value, "audible") == 0 || _rl_stricmp (value, "on") == 0) + _rl_bell_preference = AUDIBLE_BELL; + else if (_rl_stricmp (value, "visible") == 0) + _rl_bell_preference = VISIBLE_BELL; + else + return 1; + return 0; +} + +static int +sv_isrchterm (value) + const char *value; +{ + int beg, end, delim; + char *v; + + if (value == 0) + return 1; + + /* Isolate the value and translate it into a character string. */ + v = savestring (value); + FREE (_rl_isearch_terminators); + if (v[0] == '"' || v[0] == '\'') + { + delim = v[0]; + for (beg = end = 1; v[end] && v[end] != delim; end++) + ; + } + else + { + for (beg = end = 0; whitespace (v[end]) == 0; end++) + ; + } + + v[end] = '\0'; + + /* The value starts at v + beg. Translate it into a character string. */ + _rl_isearch_terminators = (char *)xmalloc (2 * strlen (v) + 1); + rl_translate_keyseq (v + beg, _rl_isearch_terminators, &end); + _rl_isearch_terminators[end] = '\0'; + + free (v); + return 0; +} + +/* Return the character which matches NAME. + For example, `Space' returns ' '. */ + +typedef struct { + const char *name; + int value; +} assoc_list; + +static assoc_list name_key_alist[] = { + { "DEL", 0x7f }, + { "ESC", '\033' }, + { "Escape", '\033' }, + { "LFD", '\n' }, + { "Newline", '\n' }, + { "RET", '\r' }, + { "Return", '\r' }, + { "Rubout", 0x7f }, + { "SPC", ' ' }, + { "Space", ' ' }, + { "Tab", 0x09 }, + { (char *)0x0, 0 } +}; + +static int +glean_key_from_name (name) + char *name; +{ + register int i; + + for (i = 0; name_key_alist[i].name; i++) + if (_rl_stricmp (name, name_key_alist[i].name) == 0) + return (name_key_alist[i].value); + + return (*(unsigned char *)name); /* XXX was return (*name) */ +} + +/* Auxiliary functions to manage keymaps. */ +static struct { + const char *name; + Keymap map; +} keymap_names[] = { + { "emacs", emacs_standard_keymap }, + { "emacs-standard", emacs_standard_keymap }, + { "emacs-meta", emacs_meta_keymap }, + { "emacs-ctlx", emacs_ctlx_keymap }, +#if defined (VI_MODE) + { "vi", vi_movement_keymap }, + { "vi-move", vi_movement_keymap }, + { "vi-command", vi_movement_keymap }, + { "vi-insert", vi_insertion_keymap }, +#endif /* VI_MODE */ + { (char *)0x0, (Keymap)0x0 } +}; + +Keymap +rl_get_keymap_by_name (name) + const char *name; +{ + register int i; + + for (i = 0; keymap_names[i].name; i++) + if (_rl_stricmp (name, keymap_names[i].name) == 0) + return (keymap_names[i].map); + return ((Keymap) NULL); +} + +char * +rl_get_keymap_name (map) + Keymap map; +{ + register int i; + for (i = 0; keymap_names[i].name; i++) + if (map == keymap_names[i].map) + return ((char *)keymap_names[i].name); + return ((char *)NULL); +} + +void +rl_set_keymap (map) + Keymap map; +{ + if (map) + _rl_keymap = map; +} + +Keymap +rl_get_keymap () +{ + return (_rl_keymap); +} + +void +rl_set_keymap_from_edit_mode () +{ + if (rl_editing_mode == emacs_mode) + _rl_keymap = emacs_standard_keymap; +#if defined (VI_MODE) + else if (rl_editing_mode == vi_mode) + _rl_keymap = vi_insertion_keymap; +#endif /* VI_MODE */ +} + +char * +rl_get_keymap_name_from_edit_mode () +{ + if (rl_editing_mode == emacs_mode) + return "emacs"; +#if defined (VI_MODE) + else if (rl_editing_mode == vi_mode) + return "vi"; +#endif /* VI_MODE */ + else + return "none"; +} + +/* **************************************************************** */ +/* */ +/* Key Binding and Function Information */ +/* */ +/* **************************************************************** */ + +/* Each of the following functions produces information about the + state of keybindings and functions known to Readline. The info + is always printed to rl_outstream, and in such a way that it can + be read back in (i.e., passed to rl_parse_and_bind ()). */ + +/* Print the names of functions known to Readline. */ +void +rl_list_funmap_names () +{ + register int i; + const char **funmap_names; + + funmap_names = rl_funmap_names (); + + if (!funmap_names) + return; + + for (i = 0; funmap_names[i]; i++) + fprintf (rl_outstream, "%s\n", funmap_names[i]); + + free (funmap_names); +} + +static char * +_rl_get_keyname (key) + int key; +{ + char *keyname; + int i, c; + + keyname = (char *)xmalloc (8); + + c = key; + /* Since this is going to be used to write out keysequence-function + pairs for possible inclusion in an inputrc file, we don't want to + do any special meta processing on KEY. */ + +#if 1 + /* XXX - Experimental */ + /* We might want to do this, but the old version of the code did not. */ + + /* If this is an escape character, we don't want to do any more processing. + Just add the special ESC key sequence and return. */ + if (c == ESC) + { + keyname[0] = '\\'; + keyname[1] = 'e'; + keyname[2] = '\0'; + return keyname; + } +#endif + + /* RUBOUT is translated directly into \C-? */ + if (key == RUBOUT) + { + keyname[0] = '\\'; + keyname[1] = 'C'; + keyname[2] = '-'; + keyname[3] = '?'; + keyname[4] = '\0'; + return keyname; + } + + i = 0; + /* Now add special prefixes needed for control characters. This can + potentially change C. */ + if (CTRL_CHAR (c)) + { + keyname[i++] = '\\'; + keyname[i++] = 'C'; + keyname[i++] = '-'; + c = _rl_to_lower (UNCTRL (c)); + } + + /* XXX experimental code. Turn the characters that are not ASCII or + ISO Latin 1 (128 - 159) into octal escape sequences (\200 - \237). + This changes C. */ + if (c >= 128 && c <= 159) + { + keyname[i++] = '\\'; + keyname[i++] = '2'; + c -= 128; + keyname[i++] = (c / 8) + '0'; + c = (c % 8) + '0'; + } + + /* Now, if the character needs to be quoted with a backslash, do that. */ + if (c == '\\' || c == '"') + keyname[i++] = '\\'; + + /* Now add the key, terminate the string, and return it. */ + keyname[i++] = (char) c; + keyname[i] = '\0'; + + return keyname; +} + +/* Return a NULL terminated array of strings which represent the key + sequences that are used to invoke FUNCTION in MAP. */ +char ** +rl_invoking_keyseqs_in_map (function, map) + rl_command_func_t *function; + Keymap map; +{ + register int key; + char **result; + int result_index, result_size; + + result = (char **)NULL; + result_index = result_size = 0; + + for (key = 0; key < KEYMAP_SIZE; key++) + { + switch (map[key].type) + { + case ISMACR: + /* Macros match, if, and only if, the pointers are identical. + Thus, they are treated exactly like functions in here. */ + case ISFUNC: + /* If the function in the keymap is the one we are looking for, + then add the current KEY to the list of invoking keys. */ + if (map[key].function == function) + { + char *keyname; + + keyname = _rl_get_keyname (key); + + if (result_index + 2 > result_size) + { + result_size += 10; + result = (char **)xrealloc (result, result_size * sizeof (char *)); + } + + result[result_index++] = keyname; + result[result_index] = (char *)NULL; + } + break; + + case ISKMAP: + { + char **seqs; + register int i; + + /* Find the list of keyseqs in this map which have FUNCTION as + their target. Add the key sequences found to RESULT. */ + if (map[key].function) + seqs = + rl_invoking_keyseqs_in_map (function, FUNCTION_TO_KEYMAP (map, key)); + else + break; + + if (seqs == 0) + break; + + for (i = 0; seqs[i]; i++) + { + char *keyname = (char *)xmalloc (6 + strlen (seqs[i])); + + if (key == ESC) +#if 0 + sprintf (keyname, "\\e"); +#else + /* XXX - experimental */ + sprintf (keyname, "\\M-"); +#endif + else if (CTRL_CHAR (key)) + sprintf (keyname, "\\C-%c", _rl_to_lower (UNCTRL (key))); + else if (key == RUBOUT) + sprintf (keyname, "\\C-?"); + else if (key == '\\' || key == '"') + { + keyname[0] = '\\'; + keyname[1] = (char) key; + keyname[2] = '\0'; + } + else + { + keyname[0] = (char) key; + keyname[1] = '\0'; + } + + strcat (keyname, seqs[i]); + free (seqs[i]); + + if (result_index + 2 > result_size) + { + result_size += 10; + result = (char **)xrealloc (result, result_size * sizeof (char *)); + } + + result[result_index++] = keyname; + result[result_index] = (char *)NULL; + } + + free (seqs); + } + break; + } + } + return (result); +} + +/* Return a NULL terminated array of strings which represent the key + sequences that can be used to invoke FUNCTION using the current keymap. */ +char ** +rl_invoking_keyseqs (function) + rl_command_func_t *function; +{ + return (rl_invoking_keyseqs_in_map (function, _rl_keymap)); +} + +/* Print all of the functions and their bindings to rl_outstream. If + PRINT_READABLY is non-zero, then print the output in such a way + that it can be read back in. */ +void +rl_function_dumper (print_readably) + int print_readably; +{ + register int i; + const char **names; + const char *name; + + names = rl_funmap_names (); + + fprintf (rl_outstream, "\n"); + + for (i = 0; name = names[i]; i++) + { + rl_command_func_t *function; + char **invokers; + + function = rl_named_function (name); + invokers = rl_invoking_keyseqs_in_map (function, _rl_keymap); + + if (print_readably) + { + if (!invokers) + fprintf (rl_outstream, "# %s (not bound)\n", name); + else + { + register int j; + + for (j = 0; invokers[j]; j++) + { + fprintf (rl_outstream, "\"%s\": %s\n", + invokers[j], name); + free (invokers[j]); + } + + free (invokers); + } + } + else + { + if (!invokers) + fprintf (rl_outstream, "%s is not bound to any keys\n", + name); + else + { + register int j; + + fprintf (rl_outstream, "%s can be found on ", name); + + for (j = 0; invokers[j] && j < 5; j++) + { + fprintf (rl_outstream, "\"%s\"%s", invokers[j], + invokers[j + 1] ? ", " : ".\n"); + } + + if (j == 5 && invokers[j]) + fprintf (rl_outstream, "...\n"); + + for (j = 0; invokers[j]; j++) + free (invokers[j]); + + free (invokers); + } + } + } + free (names); +} + +/* Print all of the current functions and their bindings to + rl_outstream. If an explicit argument is given, then print + the output in such a way that it can be read back in. */ +int +rl_dump_functions (count, key) + int count, key; +{ + if (rl_dispatching) + fprintf (rl_outstream, "\r\n"); + rl_function_dumper (rl_explicit_arg); + rl_on_new_line (); + return (0); +} + +static void +_rl_macro_dumper_internal (print_readably, map, prefix) + int print_readably; + Keymap map; + char *prefix; +{ + register int key; + char *keyname, *out; + int prefix_len; + + for (key = 0; key < KEYMAP_SIZE; key++) + { + switch (map[key].type) + { + case ISMACR: + keyname = _rl_get_keyname (key); + out = _rl_untranslate_macro_value ((char *)map[key].function); + + if (print_readably) + fprintf (rl_outstream, "\"%s%s\": \"%s\"\n", prefix ? prefix : "", + keyname, + out ? out : ""); + else + fprintf (rl_outstream, "%s%s outputs %s\n", prefix ? prefix : "", + keyname, + out ? out : ""); + free (keyname); + free (out); + break; + case ISFUNC: + break; + case ISKMAP: + prefix_len = prefix ? strlen (prefix) : 0; + if (key == ESC) + { + keyname = (char *)xmalloc (3 + prefix_len); + if (prefix) + strcpy (keyname, prefix); + keyname[prefix_len] = '\\'; + keyname[prefix_len + 1] = 'e'; + keyname[prefix_len + 2] = '\0'; + } + else + { + keyname = _rl_get_keyname (key); + if (prefix) + { + out = (char *)xmalloc (strlen (keyname) + prefix_len + 1); + strcpy (out, prefix); + strcpy (out + prefix_len, keyname); + free (keyname); + keyname = out; + } + } + + _rl_macro_dumper_internal (print_readably, FUNCTION_TO_KEYMAP (map, key), keyname); + free (keyname); + break; + } + } +} + +void +rl_macro_dumper (print_readably) + int print_readably; +{ + _rl_macro_dumper_internal (print_readably, _rl_keymap, (char *)NULL); +} + +int +rl_dump_macros (count, key) + int count, key; +{ + if (rl_dispatching) + fprintf (rl_outstream, "\r\n"); + rl_macro_dumper (rl_explicit_arg); + rl_on_new_line (); + return (0); +} + +static char * +_rl_get_string_variable_value (name) + const char *name; +{ + static char numbuf[32]; + char *ret; + int n; + + if (_rl_stricmp (name, "bell-style") == 0) + { + switch (_rl_bell_preference) + { + case NO_BELL: + return "none"; + case VISIBLE_BELL: + return "visible"; + case AUDIBLE_BELL: + default: + return "audible"; + } + } + else if (_rl_stricmp (name, "comment-begin") == 0) + return (_rl_comment_begin ? _rl_comment_begin : RL_COMMENT_BEGIN_DEFAULT); + else if (_rl_stricmp (name, "completion-query-items") == 0) + { + sprintf (numbuf, "%d", rl_completion_query_items); + return (numbuf); + } + else if (_rl_stricmp (name, "editing-mode") == 0) + return (rl_get_keymap_name_from_edit_mode ()); + else if (_rl_stricmp (name, "isearch-terminators") == 0) + { + if (_rl_isearch_terminators == 0) + return 0; + ret = _rl_untranslate_macro_value (_rl_isearch_terminators); + if (ret) + { + strncpy (numbuf, ret, sizeof (numbuf) - 1); + free (ret); + numbuf[sizeof(numbuf) - 1] = '\0'; + } + else + numbuf[0] = '\0'; + return numbuf; + } + else if (_rl_stricmp (name, "keymap") == 0) + { + ret = rl_get_keymap_name (_rl_keymap); + if (ret == 0) + ret = rl_get_keymap_name_from_edit_mode (); + return (ret ? ret : "none"); + } + else + return (0); +} + +void +rl_variable_dumper (print_readably) + int print_readably; +{ + int i; + char *v; + + for (i = 0; boolean_varlist[i].name; i++) + { + if (print_readably) + fprintf (rl_outstream, "set %s %s\n", boolean_varlist[i].name, + *boolean_varlist[i].value ? "on" : "off"); + else + fprintf (rl_outstream, "%s is set to `%s'\n", boolean_varlist[i].name, + *boolean_varlist[i].value ? "on" : "off"); + } + + for (i = 0; string_varlist[i].name; i++) + { + v = _rl_get_string_variable_value (string_varlist[i].name); + if (v == 0) /* _rl_isearch_terminators can be NULL */ + continue; + if (print_readably) + fprintf (rl_outstream, "set %s %s\n", string_varlist[i].name, v); + else + fprintf (rl_outstream, "%s is set to `%s'\n", string_varlist[i].name, v); + } +} + +/* Print all of the current variables and their values to + rl_outstream. If an explicit argument is given, then print + the output in such a way that it can be read back in. */ +int +rl_dump_variables (count, key) + int count, key; +{ + if (rl_dispatching) + fprintf (rl_outstream, "\r\n"); + rl_variable_dumper (rl_explicit_arg); + rl_on_new_line (); + return (0); +} + +/* Return non-zero if any members of ARRAY are a substring in STRING. */ +static int +substring_member_of_array (string, array) + char *string; + const char **array; +{ + while (*array) + { + if (_rl_strindex (string, *array)) + return (1); + array++; + } + return (0); +} diff --git a/external/gpl3/gdb/dist/readline/callback.c b/external/gpl3/gdb/dist/readline/callback.c new file mode 100644 index 000000000000..697066e03c5b --- /dev/null +++ b/external/gpl3/gdb/dist/readline/callback.c @@ -0,0 +1,261 @@ +/* callback.c -- functions to use readline as an X `callback' mechanism. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include "rlconf.h" + +#if defined (READLINE_CALLBACKS) + +#include + +#ifdef HAVE_STDLIB_H +# include +#else +# include "ansi_stdlib.h" +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "readline.h" +#include "rlprivate.h" +#include "xmalloc.h" + +/* Private data for callback registration functions. See comments in + rl_callback_read_char for more details. */ +_rl_callback_func_t *_rl_callback_func = 0; +_rl_callback_generic_arg *_rl_callback_data = 0; + +/* **************************************************************** */ +/* */ +/* Callback Readline Functions */ +/* */ +/* **************************************************************** */ + +/* Allow using readline in situations where a program may have multiple + things to handle at once, and dispatches them via select(). Call + rl_callback_handler_install() with the prompt and a function to call + whenever a complete line of input is ready. The user must then + call rl_callback_read_char() every time some input is available, and + rl_callback_read_char() will call the user's function with the complete + text read in at each end of line. The terminal is kept prepped and + signals handled all the time, except during calls to the user's function. */ + +rl_vcpfunc_t *rl_linefunc; /* user callback function */ +static int in_handler; /* terminal_prepped and signals set? */ + +/* Make sure the terminal is set up, initialize readline, and prompt. */ +static void +_rl_callback_newline () +{ + rl_initialize (); + + if (in_handler == 0) + { + in_handler = 1; + + if (rl_prep_term_function) + (*rl_prep_term_function) (_rl_meta_flag); + +#if defined (HANDLE_SIGNALS) + rl_set_signals (); +#endif + } + + readline_internal_setup (); +} + +/* Install a readline handler, set up the terminal, and issue the prompt. */ +void +rl_callback_handler_install (prompt, linefunc) + const char *prompt; + rl_vcpfunc_t *linefunc; +{ + rl_set_prompt (prompt); + RL_SETSTATE (RL_STATE_CALLBACK); + rl_linefunc = linefunc; + _rl_callback_newline (); +} + +/* Read one character, and dispatch to the handler if it ends the line. */ +void +rl_callback_read_char () +{ + char *line; + int eof, jcode; + static procenv_t olevel; + + if (rl_linefunc == NULL) + { + fprintf (stderr, "readline: readline_callback_read_char() called with no handler!\r\n"); + abort (); + } + + memcpy ((void *)olevel, (void *)readline_top_level, sizeof (procenv_t)); + jcode = setjmp (readline_top_level); + if (jcode) + { + (*rl_redisplay_function) (); + _rl_want_redisplay = 0; + memcpy ((void *)readline_top_level, (void *)olevel, sizeof (procenv_t)); + return; + } + + if (RL_ISSTATE (RL_STATE_ISEARCH)) + { + eof = _rl_isearch_callback (_rl_iscxt); + if (eof == 0 && (RL_ISSTATE (RL_STATE_ISEARCH) == 0) && RL_ISSTATE (RL_STATE_INPUTPENDING)) + rl_callback_read_char (); + + return; + } + else if (RL_ISSTATE (RL_STATE_NSEARCH)) + { + eof = _rl_nsearch_callback (_rl_nscxt); + return; + } + else if (RL_ISSTATE (RL_STATE_NUMERICARG)) + { + eof = _rl_arg_callback (_rl_argcxt); + if (eof == 0 && (RL_ISSTATE (RL_STATE_NUMERICARG) == 0) && RL_ISSTATE (RL_STATE_INPUTPENDING)) + rl_callback_read_char (); + /* XXX - this should handle _rl_last_command_was_kill better */ + else if (RL_ISSTATE (RL_STATE_NUMERICARG) == 0) + _rl_internal_char_cleanup (); + + return; + } + else if (RL_ISSTATE (RL_STATE_MULTIKEY)) + { + eof = _rl_dispatch_callback (_rl_kscxt); /* For now */ + while ((eof == -1 || eof == -2) && RL_ISSTATE (RL_STATE_MULTIKEY) && _rl_kscxt && (_rl_kscxt->flags & KSEQ_DISPATCHED)) + eof = _rl_dispatch_callback (_rl_kscxt); + if (RL_ISSTATE (RL_STATE_MULTIKEY) == 0) + { + _rl_internal_char_cleanup (); + _rl_want_redisplay = 1; + } + } + else if (_rl_callback_func) + { + /* This allows functions that simply need to read an additional character + (like quoted-insert) to register a function to be called when input is + available. _rl_callback_data is simply a pointer to a struct that has + the argument count originally passed to the registering function and + space for any additional parameters. */ + eof = (*_rl_callback_func) (_rl_callback_data); + /* If the function `deregisters' itself, make sure the data is cleaned + up. */ + if (_rl_callback_func == 0) + { + if (_rl_callback_data) + { + _rl_callback_data_dispose (_rl_callback_data); + _rl_callback_data = 0; + } + _rl_internal_char_cleanup (); + } + } + else + eof = readline_internal_char (); + + if (rl_done == 0 && _rl_want_redisplay) + { + (*rl_redisplay_function) (); + _rl_want_redisplay = 0; + } + + /* We loop in case some function has pushed input back with rl_execute_next. */ + for (;;) + { + if (rl_done) + { + line = readline_internal_teardown (eof); + + if (rl_deprep_term_function) + (*rl_deprep_term_function) (); +#if defined (HANDLE_SIGNALS) + rl_clear_signals (); +#endif + in_handler = 0; + (*rl_linefunc) (line); + + /* If the user did not clear out the line, do it for him. */ + if (rl_line_buffer[0]) + _rl_init_line_state (); + + /* Redisplay the prompt if readline_handler_{install,remove} + not called. */ + if (in_handler == 0 && rl_linefunc) + _rl_callback_newline (); + } + if (rl_pending_input || _rl_pushed_input_available () || RL_ISSTATE (RL_STATE_MACROINPUT)) + eof = readline_internal_char (); + else + break; + } +} + +/* Remove the handler, and make sure the terminal is in its normal state. */ +void +rl_callback_handler_remove () +{ + rl_linefunc = NULL; + RL_UNSETSTATE (RL_STATE_CALLBACK); + if (in_handler) + { + in_handler = 0; + if (rl_deprep_term_function) + (*rl_deprep_term_function) (); +#if defined (HANDLE_SIGNALS) + rl_clear_signals (); +#endif + } +} + +_rl_callback_generic_arg * +_rl_callback_data_alloc (count) + int count; +{ + _rl_callback_generic_arg *arg; + + arg = (_rl_callback_generic_arg *)xmalloc (sizeof (_rl_callback_generic_arg)); + arg->count = count; + + arg->i1 = arg->i2 = 0; + + return arg; +} + +void _rl_callback_data_dispose (arg) + _rl_callback_generic_arg *arg; +{ + if (arg) + free (arg); +} + +#endif diff --git a/external/gpl3/gdb/dist/readline/chardefs.h b/external/gpl3/gdb/dist/readline/chardefs.h new file mode 100644 index 000000000000..def3a111bd32 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/chardefs.h @@ -0,0 +1,165 @@ +/* chardefs.h -- Character definitions for readline. */ + +/* Copyright (C) 1994 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _CHARDEFS_H_ +#define _CHARDEFS_H_ + +#include + +#if defined (HAVE_CONFIG_H) +# if defined (HAVE_STRING_H) +# if ! defined (STDC_HEADERS) && defined (HAVE_MEMORY_H) +# include +# endif +# include +# endif /* HAVE_STRING_H */ +# if defined (HAVE_STRINGS_H) +# include +# endif /* HAVE_STRINGS_H */ +#else +# include +#endif /* !HAVE_CONFIG_H */ + +#ifndef whitespace +#define whitespace(c) (((c) == ' ') || ((c) == '\t')) +#endif + +#ifdef CTRL +# undef CTRL +#endif +#ifdef UNCTRL +# undef UNCTRL +#endif + +/* Some character stuff. */ +#define control_character_threshold 0x020 /* Smaller than this is control. */ +#define control_character_mask 0x1f /* 0x20 - 1 */ +#define meta_character_threshold 0x07f /* Larger than this is Meta. */ +#define control_character_bit 0x40 /* 0x000000, must be off. */ +#define meta_character_bit 0x080 /* x0000000, must be on. */ +#define largest_char 255 /* Largest character value. */ + +#define CTRL_CHAR(c) ((c) < control_character_threshold && (((c) & 0x80) == 0)) +#define META_CHAR(c) ((c) > meta_character_threshold && (c) <= largest_char) + +#define CTRL(c) ((c) & control_character_mask) +#define META(c) ((c) | meta_character_bit) + +#define UNMETA(c) ((c) & (~meta_character_bit)) +#define UNCTRL(c) _rl_to_upper(((c)|control_character_bit)) + +#if defined STDC_HEADERS || (!defined (isascii) && !defined (HAVE_ISASCII)) +# define IN_CTYPE_DOMAIN(c) 1 +#else +# define IN_CTYPE_DOMAIN(c) isascii(c) +#endif + +#if !defined (isxdigit) && !defined (HAVE_ISXDIGIT) +# define isxdigit(c) (isdigit((c)) || ((c) >= 'a' && (c) <= 'f') || ((c) >= 'A' && (c) <= 'F')) +#endif + +#if defined (CTYPE_NON_ASCII) +# define NON_NEGATIVE(c) 1 +#else +# define NON_NEGATIVE(c) ((unsigned char)(c) == (c)) +#endif + +/* Some systems define these; we want our definitions. */ +#undef ISPRINT + +/* Beware: these only work with single-byte ASCII characters. */ + +#define ISALNUM(c) (IN_CTYPE_DOMAIN (c) && isalnum (c)) +#define ISALPHA(c) (IN_CTYPE_DOMAIN (c) && isalpha (c)) +#define ISDIGIT(c) (IN_CTYPE_DOMAIN (c) && isdigit (c)) +#define ISLOWER(c) (IN_CTYPE_DOMAIN (c) && islower (c)) +#define ISPRINT(c) (IN_CTYPE_DOMAIN (c) && isprint (c)) +#define ISUPPER(c) (IN_CTYPE_DOMAIN (c) && isupper (c)) +#define ISXDIGIT(c) (IN_CTYPE_DOMAIN (c) && isxdigit (c)) + +#define _rl_lowercase_p(c) (NON_NEGATIVE(c) && ISLOWER(c)) +#define _rl_uppercase_p(c) (NON_NEGATIVE(c) && ISUPPER(c)) +#define _rl_digit_p(c) ((c) >= '0' && (c) <= '9') + +#define _rl_pure_alphabetic(c) (NON_NEGATIVE(c) && ISALPHA(c)) +#define ALPHABETIC(c) (NON_NEGATIVE(c) && ISALNUM(c)) + +#ifndef _rl_to_upper +# define _rl_to_upper(c) (_rl_lowercase_p(c) ? toupper((unsigned char)c) : (c)) +# define _rl_to_lower(c) (_rl_uppercase_p(c) ? tolower((unsigned char)c) : (c)) +#endif + +#ifndef _rl_digit_value +# define _rl_digit_value(x) ((x) - '0') +#endif + +#ifndef _rl_isident +# define _rl_isident(c) (ISALNUM(c) || (c) == '_') +#endif + +#ifndef ISOCTAL +# define ISOCTAL(c) ((c) >= '0' && (c) <= '7') +#endif +#define OCTVALUE(c) ((c) - '0') + +#define HEXVALUE(c) \ + (((c) >= 'a' && (c) <= 'f') \ + ? (c)-'a'+10 \ + : (c) >= 'A' && (c) <= 'F' ? (c)-'A'+10 : (c)-'0') + +#ifndef NEWLINE +#define NEWLINE '\n' +#endif + +#ifndef RETURN +#define RETURN CTRL('M') +#endif + +#ifndef RUBOUT +#define RUBOUT 0x7f +#endif + +#ifndef TAB +#define TAB '\t' +#endif + +#ifdef ABORT_CHAR +#undef ABORT_CHAR +#endif +#define ABORT_CHAR CTRL('G') + +#ifdef PAGE +#undef PAGE +#endif +#define PAGE CTRL('L') + +#ifdef SPACE +#undef SPACE +#endif +#define SPACE ' ' /* XXX - was 0x20 */ + +#ifdef ESC +#undef ESC +#endif +#define ESC CTRL('[') + +#endif /* _CHARDEFS_H_ */ diff --git a/external/gpl3/gdb/dist/readline/compat.c b/external/gpl3/gdb/dist/readline/compat.c new file mode 100644 index 000000000000..a66d210fd2eb --- /dev/null +++ b/external/gpl3/gdb/dist/readline/compat.c @@ -0,0 +1,113 @@ +/* compat.c -- backwards compatibility functions. */ + +/* Copyright (C) 2000 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#include "rlstdc.h" +#include "rltypedefs.h" + +extern void rl_free_undo_list PARAMS((void)); +extern int rl_maybe_save_line PARAMS((void)); +extern int rl_maybe_unsave_line PARAMS((void)); +extern int rl_maybe_replace_line PARAMS((void)); + +extern int rl_crlf PARAMS((void)); +extern int rl_ding PARAMS((void)); +extern int rl_alphabetic PARAMS((int)); + +extern char **rl_completion_matches PARAMS((const char *, rl_compentry_func_t *)); +extern char *rl_username_completion_function PARAMS((const char *, int)); +extern char *rl_filename_completion_function PARAMS((const char *, int)); + +/* Provide backwards-compatible entry points for old function names. */ + +void +free_undo_list () +{ + rl_free_undo_list (); +} + +int +maybe_replace_line () +{ + return rl_maybe_replace_line (); +} + +int +maybe_save_line () +{ + return rl_maybe_save_line (); +} + +int +maybe_unsave_line () +{ + return rl_maybe_unsave_line (); +} + +int +ding () +{ + return rl_ding (); +} + +int +crlf () +{ + return rl_crlf (); +} + +int +alphabetic (c) + int c; +{ + return rl_alphabetic (c); +} + +char ** +completion_matches (s, f) + const char *s; + rl_compentry_func_t *f; +{ + return rl_completion_matches (s, f); +} + +char * +username_completion_function (s, i) + const char *s; + int i; +{ + return rl_username_completion_function (s, i); +} + +char * +filename_completion_function (s, i) + const char *s; + int i; +{ + return rl_filename_completion_function (s, i); +} diff --git a/external/gpl3/gdb/dist/readline/complete.c b/external/gpl3/gdb/dist/readline/complete.c new file mode 100644 index 000000000000..d93c15ae55d2 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/complete.c @@ -0,0 +1,2211 @@ +/* complete.c -- filename completion for readline. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#if defined (HAVE_SYS_FILE_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +#include +#if !defined (errno) +extern int errno; +#endif /* !errno */ + +#if defined (HAVE_PWD_H) +#include +#endif + +#include "posixdir.h" +#include "posixstat.h" + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "xmalloc.h" +#include "rlprivate.h" + +#ifdef __STDC__ +typedef int QSFUNC (const void *, const void *); +#else +typedef int QSFUNC (); +#endif + +#ifdef HAVE_LSTAT +# define LSTAT lstat +#else +# define LSTAT stat +#endif + +/* Unix version of a hidden file. Could be different on other systems. */ +#define HIDDEN_FILE(fname) ((fname)[0] == '.') + +/* Most systems don't declare getpwent in if _POSIX_SOURCE is + defined. */ +#if defined (HAVE_GETPWENT) && (!defined (HAVE_GETPW_DECLS) || defined (_POSIX_SOURCE)) +extern struct passwd *getpwent PARAMS((void)); +#endif /* HAVE_GETPWENT && (!HAVE_GETPW_DECLS || _POSIX_SOURCE) */ + +/* If non-zero, then this is the address of a function to call when + completing a word would normally display the list of possible matches. + This function is called instead of actually doing the display. + It takes three arguments: (char **matches, int num_matches, int max_length) + where MATCHES is the array of strings that matched, NUM_MATCHES is the + number of strings in that array, and MAX_LENGTH is the length of the + longest string in that array. */ +rl_compdisp_func_t *rl_completion_display_matches_hook = (rl_compdisp_func_t *)NULL; + +#if defined (VISIBLE_STATS) +# if !defined (X_OK) +# define X_OK 1 +# endif +static int stat_char PARAMS((char *)); +#endif + +static int path_isdir PARAMS((const char *)); + +static char *rl_quote_filename PARAMS((char *, int, char *)); + +static void set_completion_defaults PARAMS((int)); +static int get_y_or_n PARAMS((int)); +static int _rl_internal_pager PARAMS((int)); +static char *printable_part PARAMS((char *)); +static int fnwidth PARAMS((const char *)); +static int fnprint PARAMS((const char *)); +static int print_filename PARAMS((char *, char *)); + +static char **gen_completion_matches PARAMS((char *, int, int, rl_compentry_func_t *, int, int)); + +static char **remove_duplicate_matches PARAMS((char **)); +static void insert_match PARAMS((char *, int, int, char *)); +static int append_to_match PARAMS((char *, int, int, int)); +static void insert_all_matches PARAMS((char **, int, char *)); +static void display_matches PARAMS((char **)); +static int compute_lcd_of_matches PARAMS((char **, int, const char *)); +static int postprocess_matches PARAMS((char ***, int)); + +static char *make_quoted_replacement PARAMS((char *, int, char *)); + +/* **************************************************************** */ +/* */ +/* Completion matching, from readline's point of view. */ +/* */ +/* **************************************************************** */ + +/* Variables known only to the readline library. */ + +/* If non-zero, non-unique completions always show the list of matches. */ +int _rl_complete_show_all = 0; + +/* If non-zero, non-unique completions show the list of matches, unless it + is not possible to do partial completion and modify the line. */ +int _rl_complete_show_unmodified = 0; + +/* If non-zero, completed directory names have a slash appended. */ +int _rl_complete_mark_directories = 1; + +/* If non-zero, the symlinked directory completion behavior introduced in + readline-4.2a is disabled, and symlinks that point to directories have + a slash appended (subject to the value of _rl_complete_mark_directories). + This is user-settable via the mark-symlinked-directories variable. */ +int _rl_complete_mark_symlink_dirs = 0; + +/* If non-zero, completions are printed horizontally in alphabetical order, + like `ls -x'. */ +int _rl_print_completions_horizontally; + +/* Non-zero means that case is not significant in filename completion. */ +#if defined (__MSDOS__) && !defined (__DJGPP__) +int _rl_completion_case_fold = 1; +#else +int _rl_completion_case_fold; +#endif + +/* If non-zero, don't match hidden files (filenames beginning with a `.' on + Unix) when doing filename completion. */ +int _rl_match_hidden_files = 1; + +/* Global variables available to applications using readline. */ + +#if defined (VISIBLE_STATS) +/* Non-zero means add an additional character to each filename displayed + during listing completion iff rl_filename_completion_desired which helps + to indicate the type of file being listed. */ +int rl_visible_stats = 0; +#endif /* VISIBLE_STATS */ + +/* If non-zero, then this is the address of a function to call when + completing on a directory name. The function is called with + the address of a string (the current directory name) as an arg. */ +rl_icppfunc_t *rl_directory_completion_hook = (rl_icppfunc_t *)NULL; + +rl_icppfunc_t *rl_directory_rewrite_hook = (rl_icppfunc_t *)NULL; + +/* Non-zero means readline completion functions perform tilde expansion. */ +int rl_complete_with_tilde_expansion = 0; + +/* Pointer to the generator function for completion_matches (). + NULL means to use rl_filename_completion_function (), the default filename + completer. */ +rl_compentry_func_t *rl_completion_entry_function = (rl_compentry_func_t *)NULL; + +/* Pointer to alternative function to create matches. + Function is called with TEXT, START, and END. + START and END are indices in RL_LINE_BUFFER saying what the boundaries + of TEXT are. + If this function exists and returns NULL then call the value of + rl_completion_entry_function to try to match, otherwise use the + array of strings returned. */ +rl_completion_func_t *rl_attempted_completion_function = (rl_completion_func_t *)NULL; + +/* Non-zero means to suppress normal filename completion after the + user-specified completion function has been called. */ +int rl_attempted_completion_over = 0; + +/* Set to a character indicating the type of completion being performed + by rl_complete_internal, available for use by application completion + functions. */ +int rl_completion_type = 0; + +/* Up to this many items will be displayed in response to a + possible-completions call. After that, we ask the user if + she is sure she wants to see them all. A negative value means + don't ask. */ +int rl_completion_query_items = 100; + +int _rl_page_completions = 1; + +/* The basic list of characters that signal a break between words for the + completer routine. The contents of this variable is what breaks words + in the shell, i.e. " \t\n\"\\'`@$><=" */ +const char *rl_basic_word_break_characters = " \t\n\"\\'`@$><=;|&{("; /* }) */ + +/* List of basic quoting characters. */ +const char *rl_basic_quote_characters = "\"'"; + +/* The list of characters that signal a break between words for + rl_complete_internal. The default list is the contents of + rl_basic_word_break_characters. */ +/*const*/ char *rl_completer_word_break_characters = (/*const*/ char *)NULL; + +/* Hook function to allow an application to set the completion word + break characters before readline breaks up the line. Allows + position-dependent word break characters. */ +rl_cpvfunc_t *rl_completion_word_break_hook = (rl_cpvfunc_t *)NULL; + +/* List of characters which can be used to quote a substring of the line. + Completion occurs on the entire substring, and within the substring + rl_completer_word_break_characters are treated as any other character, + unless they also appear within this list. */ +const char *rl_completer_quote_characters = (const char *)NULL; + +/* List of characters that should be quoted in filenames by the completer. */ +const char *rl_filename_quote_characters = (const char *)NULL; + +/* List of characters that are word break characters, but should be left + in TEXT when it is passed to the completion function. The shell uses + this to help determine what kind of completing to do. */ +const char *rl_special_prefixes = (const char *)NULL; + +/* If non-zero, then disallow duplicates in the matches. */ +int rl_ignore_completion_duplicates = 1; + +/* Non-zero means that the results of the matches are to be treated + as filenames. This is ALWAYS zero on entry, and can only be changed + within a completion entry finder function. */ +int rl_filename_completion_desired = 0; + +/* Non-zero means that the results of the matches are to be quoted using + double quotes (or an application-specific quoting mechanism) if the + filename contains any characters in rl_filename_quote_chars. This is + ALWAYS non-zero on entry, and can only be changed within a completion + entry finder function. */ +int rl_filename_quoting_desired = 1; + +/* This function, if defined, is called by the completer when real + filename completion is done, after all the matching names have been + generated. It is passed a (char**) known as matches in the code below. + It consists of a NULL-terminated array of pointers to potential + matching strings. The 1st element (matches[0]) is the maximal + substring that is common to all matches. This function can re-arrange + the list of matches as required, but all elements of the array must be + free()'d if they are deleted. The main intent of this function is + to implement FIGNORE a la SunOS csh. */ +rl_compignore_func_t *rl_ignore_some_completions_function = (rl_compignore_func_t *)NULL; + +/* Set to a function to quote a filename in an application-specific fashion. + Called with the text to quote, the type of match found (single or multiple) + and a pointer to the quoting character to be used, which the function can + reset if desired. */ +rl_quote_func_t *rl_filename_quoting_function = rl_quote_filename; + +/* Function to call to remove quoting characters from a filename. Called + before completion is attempted, so the embedded quotes do not interfere + with matching names in the file system. Readline doesn't do anything + with this; it's set only by applications. */ +rl_dequote_func_t *rl_filename_dequoting_function = (rl_dequote_func_t *)NULL; + +/* Function to call to decide whether or not a word break character is + quoted. If a character is quoted, it does not break words for the + completer. */ +rl_linebuf_func_t *rl_char_is_quoted_p = (rl_linebuf_func_t *)NULL; + +/* If non-zero, the completion functions don't append anything except a + possible closing quote. This is set to 0 by rl_complete_internal and + may be changed by an application-specific completion function. */ +int rl_completion_suppress_append = 0; + +/* Character appended to completed words when at the end of the line. The + default is a space. */ +int rl_completion_append_character = ' '; + +/* If non-zero, the completion functions don't append any closing quote. + This is set to 0 by rl_complete_internal and may be changed by an + application-specific completion function. */ +int rl_completion_suppress_quote = 0; + +/* Set to any quote character readline thinks it finds before any application + completion function is called. */ +int rl_completion_quote_character; + +/* Set to a non-zero value if readline found quoting anywhere in the word to + be completed; set before any application completion function is called. */ +int rl_completion_found_quote; + +/* If non-zero, a slash will be appended to completed filenames that are + symbolic links to directory names, subject to the value of the + mark-directories variable (which is user-settable). This exists so + that application completion functions can override the user's preference + (set via the mark-symlinked-directories variable) if appropriate. + It's set to the value of _rl_complete_mark_symlink_dirs in + rl_complete_internal before any application-specific completion + function is called, so without that function doing anything, the user's + preferences are honored. */ +int rl_completion_mark_symlink_dirs; + +/* If non-zero, inhibit completion (temporarily). */ +int rl_inhibit_completion; + +/* Variables local to this file. */ + +/* Local variable states what happened during the last completion attempt. */ +static int completion_changed_buffer; + +/*************************************/ +/* */ +/* Bindable completion functions */ +/* */ +/*************************************/ + +/* Complete the word at or before point. You have supplied the function + that does the initial simple matching selection algorithm (see + rl_completion_matches ()). The default is to do filename completion. */ +int +rl_complete (ignore, invoking_key) + int ignore, invoking_key; +{ + if (rl_inhibit_completion) + return (_rl_insert_char (ignore, invoking_key)); + else if (rl_last_func == rl_complete && !completion_changed_buffer) + return (rl_complete_internal ('?')); + else if (_rl_complete_show_all) + return (rl_complete_internal ('!')); + else if (_rl_complete_show_unmodified) + return (rl_complete_internal ('@')); + else + return (rl_complete_internal (TAB)); +} + +/* List the possible completions. See description of rl_complete (). */ +int +rl_possible_completions (ignore, invoking_key) + int ignore, invoking_key; +{ + return (rl_complete_internal ('?')); +} + +int +rl_insert_completions (ignore, invoking_key) + int ignore, invoking_key; +{ + return (rl_complete_internal ('*')); +} + +/* Return the correct value to pass to rl_complete_internal performing + the same tests as rl_complete. This allows consecutive calls to an + application's completion function to list possible completions and for + an application-specific completion function to honor the + show-all-if-ambiguous readline variable. */ +int +rl_completion_mode (cfunc) + rl_command_func_t *cfunc; +{ + if (rl_last_func == cfunc && !completion_changed_buffer) + return '?'; + else if (_rl_complete_show_all) + return '!'; + else if (_rl_complete_show_unmodified) + return '@'; + else + return TAB; +} + +/************************************/ +/* */ +/* Completion utility functions */ +/* */ +/************************************/ + +/* Set default values for readline word completion. These are the variables + that application completion functions can change or inspect. */ +static void +set_completion_defaults (what_to_do) + int what_to_do; +{ + /* Only the completion entry function can change these. */ + rl_filename_completion_desired = 0; + rl_filename_quoting_desired = 1; + rl_completion_type = what_to_do; + rl_completion_suppress_append = rl_completion_suppress_quote = 0; + + /* The completion entry function may optionally change this. */ + rl_completion_mark_symlink_dirs = _rl_complete_mark_symlink_dirs; +} + +/* The user must press "y" or "n". Non-zero return means "y" pressed. */ +static int +get_y_or_n (for_pager) + int for_pager; +{ + int c; + + for (;;) + { + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (c == 'y' || c == 'Y' || c == ' ') + return (1); + if (c == 'n' || c == 'N' || c == RUBOUT) + return (0); + if (c == ABORT_CHAR) + _rl_abort_internal (); + if (for_pager && (c == NEWLINE || c == RETURN)) + return (2); + if (for_pager && (c == 'q' || c == 'Q')) + return (0); + rl_ding (); + } +} + +static int +_rl_internal_pager (lines) + int lines; +{ + int i; + + fprintf (rl_outstream, "--More--"); + fflush (rl_outstream); + i = get_y_or_n (1); + _rl_erase_entire_line (); + if (i == 0) + return -1; + else if (i == 2) + return (lines - 1); + else + return 0; +} + +static int +path_isdir (filename) + const char *filename; +{ + struct stat finfo; + + return (stat (filename, &finfo) == 0 && S_ISDIR (finfo.st_mode)); +} + +#if defined (VISIBLE_STATS) +/* Return the character which best describes FILENAME. + `@' for symbolic links + `/' for directories + `*' for executables + `=' for sockets + `|' for FIFOs + `%' for character special devices + `#' for block special devices */ +static int +stat_char (filename) + char *filename; +{ + struct stat finfo; + int character, r; + +#if defined (HAVE_LSTAT) && defined (S_ISLNK) + r = lstat (filename, &finfo); +#else + r = stat (filename, &finfo); +#endif + + if (r == -1) + return (0); + + character = 0; + if (S_ISDIR (finfo.st_mode)) + character = '/'; +#if defined (S_ISCHR) + else if (S_ISCHR (finfo.st_mode)) + character = '%'; +#endif /* S_ISCHR */ +#if defined (S_ISBLK) + else if (S_ISBLK (finfo.st_mode)) + character = '#'; +#endif /* S_ISBLK */ +#if defined (S_ISLNK) + else if (S_ISLNK (finfo.st_mode)) + character = '@'; +#endif /* S_ISLNK */ +#if defined (S_ISSOCK) + else if (S_ISSOCK (finfo.st_mode)) + character = '='; +#endif /* S_ISSOCK */ +#if defined (S_ISFIFO) + else if (S_ISFIFO (finfo.st_mode)) + character = '|'; +#endif + else if (S_ISREG (finfo.st_mode)) + { + if (access (filename, X_OK) == 0) + character = '*'; + } + return (character); +} +#endif /* VISIBLE_STATS */ + +/* Return the portion of PATHNAME that should be output when listing + possible completions. If we are hacking filename completion, we + are only interested in the basename, the portion following the + final slash. Otherwise, we return what we were passed. Since + printing empty strings is not very informative, if we're doing + filename completion, and the basename is the empty string, we look + for the previous slash and return the portion following that. If + there's no previous slash, we just return what we were passed. */ +static char * +printable_part (pathname) + char *pathname; +{ + char *temp, *x; + + if (rl_filename_completion_desired == 0) /* don't need to do anything */ + return (pathname); + + temp = strrchr (pathname, '/'); +#if defined (__MSDOS__) + if (temp == 0 && ISALPHA ((unsigned char)pathname[0]) && pathname[1] == ':') + temp = pathname + 1; +#endif + + if (temp == 0 || *temp == '\0') + return (pathname); + /* If the basename is NULL, we might have a pathname like '/usr/src/'. + Look for a previous slash and, if one is found, return the portion + following that slash. If there's no previous slash, just return the + pathname we were passed. */ + else if (temp[1] == '\0') + { + for (x = temp - 1; x > pathname; x--) + if (*x == '/') + break; + return ((*x == '/') ? x + 1 : pathname); + } + else + return ++temp; +} + +/* Compute width of STRING when displayed on screen by print_filename */ +static int +fnwidth (string) + const char *string; +{ + int width, pos; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps; + int left, w; + size_t clen; + wchar_t wc; + + left = strlen (string) + 1; + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + width = pos = 0; + while (string[pos]) + { + if (CTRL_CHAR (*string) || *string == RUBOUT) + { + width += 2; + pos++; + } + else + { +#if defined (HANDLE_MULTIBYTE) + clen = mbrtowc (&wc, string + pos, left - pos, &ps); + if (MB_INVALIDCH (clen)) + { + width++; + pos++; + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (clen)) + break; + else + { + pos += clen; + w = wcwidth (wc); + width += (w >= 0) ? w : 1; + } +#else + width++; + pos++; +#endif + } + } + + return width; +} + +static int +fnprint (to_print) + const char *to_print; +{ + int printed_len; + const char *s; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps; + const char *end; + size_t tlen; + int width, w; + wchar_t wc; + + end = to_print + strlen (to_print) + 1; + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + printed_len = 0; + s = to_print; + while (*s) + { + if (CTRL_CHAR (*s)) + { + putc ('^', rl_outstream); + putc (UNCTRL (*s), rl_outstream); + printed_len += 2; + s++; +#if defined (HANDLE_MULTIBYTE) + memset (&ps, 0, sizeof (mbstate_t)); +#endif + } + else if (*s == RUBOUT) + { + putc ('^', rl_outstream); + putc ('?', rl_outstream); + printed_len += 2; + s++; +#if defined (HANDLE_MULTIBYTE) + memset (&ps, 0, sizeof (mbstate_t)); +#endif + } + else + { +#if defined (HANDLE_MULTIBYTE) + tlen = mbrtowc (&wc, s, end - s, &ps); + if (MB_INVALIDCH (tlen)) + { + tlen = 1; + width = 1; + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (tlen)) + break; + else + { + w = wcwidth (wc); + width = (w >= 0) ? w : 1; + } + fwrite (s, 1, tlen, rl_outstream); + s += tlen; + printed_len += width; +#else + putc (*s, rl_outstream); + s++; + printed_len++; +#endif + } + } + + return printed_len; +} + +/* Output TO_PRINT to rl_outstream. If VISIBLE_STATS is defined and we + are using it, check for and output a single character for `special' + filenames. Return the number of characters we output. */ + +static int +print_filename (to_print, full_pathname) + char *to_print, *full_pathname; +{ + int printed_len, extension_char, slen, tlen; + char *s, c, *new_full_pathname, *dn; + + extension_char = 0; + printed_len = fnprint (to_print); + +#if defined (VISIBLE_STATS) + if (rl_filename_completion_desired && (rl_visible_stats || _rl_complete_mark_directories)) +#else + if (rl_filename_completion_desired && _rl_complete_mark_directories) +#endif + { + /* If to_print != full_pathname, to_print is the basename of the + path passed. In this case, we try to expand the directory + name before checking for the stat character. */ + if (to_print != full_pathname) + { + /* Terminate the directory name. */ + c = to_print[-1]; + to_print[-1] = '\0'; + + /* If setting the last slash in full_pathname to a NUL results in + full_pathname being the empty string, we are trying to complete + files in the root directory. If we pass a null string to the + bash directory completion hook, for example, it will expand it + to the current directory. We just want the `/'. */ + if (full_pathname == 0 || *full_pathname == 0) + dn = "/"; + else if (full_pathname[0] != '/') + dn = full_pathname; + else if (full_pathname[1] == 0) + dn = "//"; /* restore trailing slash to `//' */ + else if (full_pathname[1] == '/' && full_pathname[2] == 0) + dn = "/"; /* don't turn /// into // */ + else + dn = full_pathname; + s = tilde_expand (dn); + if (rl_directory_completion_hook) + (*rl_directory_completion_hook) (&s); + + slen = strlen (s); + tlen = strlen (to_print); + new_full_pathname = (char *)xmalloc (slen + tlen + 2); + strcpy (new_full_pathname, s); + if (s[slen - 1] == '/') + slen--; + else + new_full_pathname[slen] = '/'; + new_full_pathname[slen] = '/'; + strcpy (new_full_pathname + slen + 1, to_print); + +#if defined (VISIBLE_STATS) + if (rl_visible_stats) + extension_char = stat_char (new_full_pathname); + else +#endif + if (path_isdir (new_full_pathname)) + extension_char = '/'; + + free (new_full_pathname); + to_print[-1] = c; + } + else + { + s = tilde_expand (full_pathname); +#if defined (VISIBLE_STATS) + if (rl_visible_stats) + extension_char = stat_char (s); + else +#endif + if (path_isdir (s)) + extension_char = '/'; + } + + free (s); + if (extension_char) + { + putc (extension_char, rl_outstream); + printed_len++; + } + } + + return printed_len; +} + +static char * +rl_quote_filename (s, rtype, qcp) + char *s; + int rtype; + char *qcp; +{ + char *r; + + r = (char *)xmalloc (strlen (s) + 2); + *r = *rl_completer_quote_characters; + strcpy (r + 1, s); + if (qcp) + *qcp = *rl_completer_quote_characters; + return r; +} + +/* Find the bounds of the current word for completion purposes, and leave + rl_point set to the end of the word. This function skips quoted + substrings (characters between matched pairs of characters in + rl_completer_quote_characters). First we try to find an unclosed + quoted substring on which to do matching. If one is not found, we use + the word break characters to find the boundaries of the current word. + We call an application-specific function to decide whether or not a + particular word break character is quoted; if that function returns a + non-zero result, the character does not break a word. This function + returns the opening quote character if we found an unclosed quoted + substring, '\0' otherwise. FP, if non-null, is set to a value saying + which (shell-like) quote characters we found (single quote, double + quote, or backslash) anywhere in the string. DP, if non-null, is set to + the value of the delimiter character that caused a word break. */ + +char +_rl_find_completion_word (fp, dp) + int *fp, *dp; +{ + int scan, end, found_quote, delimiter, pass_next, isbrk; + char quote_char, *brkchars; + + end = rl_point; + found_quote = delimiter = 0; + quote_char = '\0'; + + brkchars = 0; + if (rl_completion_word_break_hook) + brkchars = (*rl_completion_word_break_hook) (); + if (brkchars == 0) + brkchars = rl_completer_word_break_characters; + + if (rl_completer_quote_characters) + { + /* We have a list of characters which can be used in pairs to + quote substrings for the completer. Try to find the start + of an unclosed quoted substring. */ + /* FOUND_QUOTE is set so we know what kind of quotes we found. */ + for (scan = pass_next = 0; scan < end; scan = MB_NEXTCHAR (rl_line_buffer, scan, 1, MB_FIND_ANY)) + { + if (pass_next) + { + pass_next = 0; + continue; + } + + /* Shell-like semantics for single quotes -- don't allow backslash + to quote anything in single quotes, especially not the closing + quote. If you don't like this, take out the check on the value + of quote_char. */ + if (quote_char != '\'' && rl_line_buffer[scan] == '\\') + { + pass_next = 1; + found_quote |= RL_QF_BACKSLASH; + continue; + } + + if (quote_char != '\0') + { + /* Ignore everything until the matching close quote char. */ + if (rl_line_buffer[scan] == quote_char) + { + /* Found matching close. Abandon this substring. */ + quote_char = '\0'; + rl_point = end; + } + } + else if (strchr (rl_completer_quote_characters, rl_line_buffer[scan])) + { + /* Found start of a quoted substring. */ + quote_char = rl_line_buffer[scan]; + rl_point = scan + 1; + /* Shell-like quoting conventions. */ + if (quote_char == '\'') + found_quote |= RL_QF_SINGLE_QUOTE; + else if (quote_char == '"') + found_quote |= RL_QF_DOUBLE_QUOTE; + else + found_quote |= RL_QF_OTHER_QUOTE; + } + } + } + + if (rl_point == end && quote_char == '\0') + { + /* We didn't find an unclosed quoted substring upon which to do + completion, so use the word break characters to find the + substring on which to complete. */ + while (rl_point = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_ANY)) + { + scan = rl_line_buffer[rl_point]; + + if (strchr (brkchars, scan) == 0) + continue; + + /* Call the application-specific function to tell us whether + this word break character is quoted and should be skipped. */ + if (rl_char_is_quoted_p && found_quote && + (*rl_char_is_quoted_p) (rl_line_buffer, rl_point)) + continue; + + /* Convoluted code, but it avoids an n^2 algorithm with calls + to char_is_quoted. */ + break; + } + } + + /* If we are at an unquoted word break, then advance past it. */ + scan = rl_line_buffer[rl_point]; + + /* If there is an application-specific function to say whether or not + a character is quoted and we found a quote character, let that + function decide whether or not a character is a word break, even + if it is found in rl_completer_word_break_characters. Don't bother + if we're at the end of the line, though. */ + if (scan) + { + if (rl_char_is_quoted_p) + isbrk = (found_quote == 0 || + (*rl_char_is_quoted_p) (rl_line_buffer, rl_point) == 0) && + strchr (brkchars, scan) != 0; + else + isbrk = strchr (brkchars, scan) != 0; + + if (isbrk) + { + /* If the character that caused the word break was a quoting + character, then remember it as the delimiter. */ + if (rl_basic_quote_characters && + strchr (rl_basic_quote_characters, scan) && + (end - rl_point) > 1) + delimiter = scan; + + /* If the character isn't needed to determine something special + about what kind of completion to perform, then advance past it. */ + if (rl_special_prefixes == 0 || strchr (rl_special_prefixes, scan) == 0) + rl_point++; + } + } + + if (fp) + *fp = found_quote; + if (dp) + *dp = delimiter; + + return (quote_char); +} + +static char ** +gen_completion_matches (text, start, end, our_func, found_quote, quote_char) + char *text; + int start, end; + rl_compentry_func_t *our_func; + int found_quote, quote_char; +{ + char **matches, *temp; + + rl_completion_found_quote = found_quote; + rl_completion_quote_character = quote_char; + + /* If the user wants to TRY to complete, but then wants to give + up and use the default completion function, they set the + variable rl_attempted_completion_function. */ + if (rl_attempted_completion_function) + { + matches = (*rl_attempted_completion_function) (text, start, end); + + if (matches || rl_attempted_completion_over) + { + rl_attempted_completion_over = 0; + return (matches); + } + } + + /* Beware -- we're stripping the quotes here. Do this only if we know + we are doing filename completion and the application has defined a + filename dequoting function. */ + temp = (char *)NULL; + + if (found_quote && our_func == rl_filename_completion_function && + rl_filename_dequoting_function) + { + /* delete single and double quotes */ + temp = (*rl_filename_dequoting_function) (text, quote_char); + text = temp; /* not freeing text is not a memory leak */ + } + + matches = rl_completion_matches (text, our_func); + FREE (temp); + return matches; +} + +/* Filter out duplicates in MATCHES. This frees up the strings in + MATCHES. */ +static char ** +remove_duplicate_matches (matches) + char **matches; +{ + char *lowest_common; + int i, j, newlen; + char dead_slot; + char **temp_array; + + /* Sort the items. */ + for (i = 0; matches[i]; i++) + ; + + /* Sort the array without matches[0], since we need it to + stay in place no matter what. */ + if (i) + qsort (matches+1, i-1, sizeof (char *), (QSFUNC *)_rl_qsort_string_compare); + + /* Remember the lowest common denominator for it may be unique. */ + lowest_common = savestring (matches[0]); + + for (i = newlen = 0; matches[i + 1]; i++) + { + if (strcmp (matches[i], matches[i + 1]) == 0) + { + free (matches[i]); + matches[i] = (char *)&dead_slot; + } + else + newlen++; + } + + /* We have marked all the dead slots with (char *)&dead_slot. + Copy all the non-dead entries into a new array. */ + temp_array = (char **)xmalloc ((3 + newlen) * sizeof (char *)); + for (i = j = 1; matches[i]; i++) + { + if (matches[i] != (char *)&dead_slot) + temp_array[j++] = matches[i]; + } + temp_array[j] = (char *)NULL; + + if (matches[0] != (char *)&dead_slot) + free (matches[0]); + + /* Place the lowest common denominator back in [0]. */ + temp_array[0] = lowest_common; + + /* If there is one string left, and it is identical to the + lowest common denominator, then the LCD is the string to + insert. */ + if (j == 2 && strcmp (temp_array[0], temp_array[1]) == 0) + { + free (temp_array[1]); + temp_array[1] = (char *)NULL; + } + return (temp_array); +} + +/* Find the common prefix of the list of matches, and put it into + matches[0]. */ +static int +compute_lcd_of_matches (match_list, matches, text) + char **match_list; + int matches; + const char *text; +{ + register int i, c1, c2, si; + int low; /* Count of max-matched characters. */ + char *dtext; /* dequoted TEXT, if needed */ +#if defined (HANDLE_MULTIBYTE) + int v; + mbstate_t ps1, ps2; + wchar_t wc1, wc2; +#endif + + /* If only one match, just use that. Otherwise, compare each + member of the list with the next, finding out where they + stop matching. */ + if (matches == 1) + { + match_list[0] = match_list[1]; + match_list[1] = (char *)NULL; + return 1; + } + + for (i = 1, low = 100000; i < matches; i++) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + memset (&ps1, 0, sizeof (mbstate_t)); + memset (&ps2, 0, sizeof (mbstate_t)); + } +#endif + if (_rl_completion_case_fold) + { + for (si = 0; + (c1 = _rl_to_lower(match_list[i][si])) && + (c2 = _rl_to_lower(match_list[i + 1][si])); + si++) +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + v = mbrtowc (&wc1, match_list[i]+si, strlen (match_list[i]+si), &ps1); + mbrtowc (&wc2, match_list[i+1]+si, strlen (match_list[i+1]+si), &ps2); + wc1 = towlower (wc1); + wc2 = towlower (wc2); + if (wc1 != wc2) + break; + else if (v > 1) + si += v - 1; + } + else +#endif + if (c1 != c2) + break; + } + else + { + for (si = 0; + (c1 = match_list[i][si]) && + (c2 = match_list[i + 1][si]); + si++) +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + mbstate_t ps_back = ps1; + if (!_rl_compare_chars (match_list[i], si, &ps1, match_list[i+1], si, &ps2)) + break; + else if ((v = _rl_get_char_len (&match_list[i][si], &ps_back)) > 1) + si += v - 1; + } + else +#endif + if (c1 != c2) + break; + } + + if (low > si) + low = si; + } + + /* If there were multiple matches, but none matched up to even the + first character, and the user typed something, use that as the + value of matches[0]. */ + if (low == 0 && text && *text) + { + match_list[0] = (char *)xmalloc (strlen (text) + 1); + strcpy (match_list[0], text); + } + else + { + match_list[0] = (char *)xmalloc (low + 1); + + /* XXX - this might need changes in the presence of multibyte chars */ + + /* If we are ignoring case, try to preserve the case of the string + the user typed in the face of multiple matches differing in case. */ + if (_rl_completion_case_fold) + { + /* We're making an assumption here: + IF we're completing filenames AND + the application has defined a filename dequoting function AND + we found a quote character AND + the application has requested filename quoting + THEN + we assume that TEXT was dequoted before checking against + the file system and needs to be dequoted here before we + check against the list of matches + FI */ + dtext = (char *)NULL; + if (rl_filename_completion_desired && + rl_filename_dequoting_function && + rl_completion_found_quote && + rl_filename_quoting_desired) + { + dtext = (*rl_filename_dequoting_function) ((char *)text, rl_completion_quote_character); + text = dtext; + } + + /* sort the list to get consistent answers. */ + qsort (match_list+1, matches, sizeof(char *), (QSFUNC *)_rl_qsort_string_compare); + + si = strlen (text); + if (si <= low) + { + for (i = 1; i <= matches; i++) + if (strncmp (match_list[i], text, si) == 0) + { + strncpy (match_list[0], match_list[i], low); + break; + } + /* no casematch, use first entry */ + if (i > matches) + strncpy (match_list[0], match_list[1], low); + } + else + /* otherwise, just use the text the user typed. */ + strncpy (match_list[0], text, low); + + FREE (dtext); + } + else + strncpy (match_list[0], match_list[1], low); + + match_list[0][low] = '\0'; + } + + return matches; +} + +static int +postprocess_matches (matchesp, matching_filenames) + char ***matchesp; + int matching_filenames; +{ + char *t, **matches, **temp_matches; + int nmatch, i; + + matches = *matchesp; + + if (matches == 0) + return 0; + + /* It seems to me that in all the cases we handle we would like + to ignore duplicate possiblilities. Scan for the text to + insert being identical to the other completions. */ + if (rl_ignore_completion_duplicates) + { + temp_matches = remove_duplicate_matches (matches); + free (matches); + matches = temp_matches; + } + + /* If we are matching filenames, then here is our chance to + do clever processing by re-examining the list. Call the + ignore function with the array as a parameter. It can + munge the array, deleting matches as it desires. */ + if (rl_ignore_some_completions_function && matching_filenames) + { + for (nmatch = 1; matches[nmatch]; nmatch++) + ; + (void)(*rl_ignore_some_completions_function) (matches); + if (matches == 0 || matches[0] == 0) + { + FREE (matches); + *matchesp = (char **)0; + return 0; + } + else + { + /* If we removed some matches, recompute the common prefix. */ + for (i = 1; matches[i]; i++) + ; + if (i > 1 && i < nmatch) + { + t = matches[0]; + compute_lcd_of_matches (matches, i - 1, t); + FREE (t); + } + } + } + + *matchesp = matches; + return (1); +} + +/* A convenience function for displaying a list of strings in + columnar format on readline's output stream. MATCHES is the list + of strings, in argv format, LEN is the number of strings in MATCHES, + and MAX is the length of the longest string in MATCHES. */ +void +rl_display_match_list (matches, len, max) + char **matches; + int len, max; +{ + int count, limit, printed_len, lines; + int i, j, k, l; + char *temp; + + /* How many items of MAX length can we fit in the screen window? */ + max += 2; + limit = _rl_screenwidth / max; + if (limit != 1 && (limit * max == _rl_screenwidth)) + limit--; + + /* Avoid a possible floating exception. If max > _rl_screenwidth, + limit will be 0 and a divide-by-zero fault will result. */ + if (limit == 0) + limit = 1; + + /* How many iterations of the printing loop? */ + count = (len + (limit - 1)) / limit; + + /* Watch out for special case. If LEN is less than LIMIT, then + just do the inner printing loop. + 0 < len <= limit implies count = 1. */ + + /* Sort the items if they are not already sorted. */ + if (rl_ignore_completion_duplicates == 0) + qsort (matches + 1, len, sizeof (char *), (QSFUNC *)_rl_qsort_string_compare); + + rl_crlf (); + + lines = 0; + if (_rl_print_completions_horizontally == 0) + { + /* Print the sorted items, up-and-down alphabetically, like ls. */ + for (i = 1; i <= count; i++) + { + for (j = 0, l = i; j < limit; j++) + { + if (l > len || matches[l] == 0) + break; + else + { + temp = printable_part (matches[l]); + printed_len = print_filename (temp, matches[l]); + + if (j + 1 < limit) + for (k = 0; k < max - printed_len; k++) + putc (' ', rl_outstream); + } + l += count; + } + rl_crlf (); + lines++; + if (_rl_page_completions && lines >= (_rl_screenheight - 1) && i < count) + { + lines = _rl_internal_pager (lines); + if (lines < 0) + return; + } + } + } + else + { + /* Print the sorted items, across alphabetically, like ls -x. */ + for (i = 1; matches[i]; i++) + { + temp = printable_part (matches[i]); + printed_len = print_filename (temp, matches[i]); + /* Have we reached the end of this line? */ + if (matches[i+1]) + { + if (i && (limit > 1) && (i % limit) == 0) + { + rl_crlf (); + lines++; + if (_rl_page_completions && lines >= _rl_screenheight - 1) + { + lines = _rl_internal_pager (lines); + if (lines < 0) + return; + } + } + else + for (k = 0; k < max - printed_len; k++) + putc (' ', rl_outstream); + } + } + rl_crlf (); + } +} + +/* Display MATCHES, a list of matching filenames in argv format. This + handles the simple case -- a single match -- first. If there is more + than one match, we compute the number of strings in the list and the + length of the longest string, which will be needed by the display + function. If the application wants to handle displaying the list of + matches itself, it sets RL_COMPLETION_DISPLAY_MATCHES_HOOK to the + address of a function, and we just call it. If we're handling the + display ourselves, we just call rl_display_match_list. We also check + that the list of matches doesn't exceed the user-settable threshold, + and ask the user if he wants to see the list if there are more matches + than RL_COMPLETION_QUERY_ITEMS. */ +static void +display_matches (matches) + char **matches; +{ + int len, max, i; + char *temp; + + /* Move to the last visible line of a possibly-multiple-line command. */ + _rl_move_vert (_rl_vis_botlin); + + /* Handle simple case first. What if there is only one answer? */ + if (matches[1] == 0) + { + temp = printable_part (matches[0]); + rl_crlf (); + print_filename (temp, matches[0]); + rl_crlf (); + + rl_forced_update_display (); + rl_display_fixed = 1; + + return; + } + + /* There is more than one answer. Find out how many there are, + and find the maximum printed length of a single entry. */ + for (max = 0, i = 1; matches[i]; i++) + { + temp = printable_part (matches[i]); + len = fnwidth (temp); + + if (len > max) + max = len; + } + + len = i - 1; + + /* If the caller has defined a display hook, then call that now. */ + if (rl_completion_display_matches_hook) + { + (*rl_completion_display_matches_hook) (matches, len, max); + return; + } + + /* If there are many items, then ask the user if she really wants to + see them all. */ + if (rl_completion_query_items > 0 && len >= rl_completion_query_items) + { + rl_crlf (); + fprintf (rl_outstream, "Display all %d possibilities? (y or n)", len); + fflush (rl_outstream); + if (get_y_or_n (0) == 0) + { + rl_crlf (); + + rl_forced_update_display (); + rl_display_fixed = 1; + + return; + } + } + + rl_display_match_list (matches, len, max); + + rl_forced_update_display (); + rl_display_fixed = 1; +} + +static char * +make_quoted_replacement (match, mtype, qc) + char *match; + int mtype; + char *qc; /* Pointer to quoting character, if any */ +{ + int should_quote, do_replace; + char *replacement; + + /* If we are doing completion on quoted substrings, and any matches + contain any of the completer_word_break_characters, then auto- + matically prepend the substring with a quote character (just pick + the first one from the list of such) if it does not already begin + with a quote string. FIXME: Need to remove any such automatically + inserted quote character when it no longer is necessary, such as + if we change the string we are completing on and the new set of + matches don't require a quoted substring. */ + replacement = match; + + should_quote = match && rl_completer_quote_characters && + rl_filename_completion_desired && + rl_filename_quoting_desired; + + if (should_quote) + should_quote = should_quote && (!qc || !*qc || + (rl_completer_quote_characters && strchr (rl_completer_quote_characters, *qc))); + + if (should_quote) + { + /* If there is a single match, see if we need to quote it. + This also checks whether the common prefix of several + matches needs to be quoted. */ + should_quote = rl_filename_quote_characters + ? (_rl_strpbrk (match, rl_filename_quote_characters) != 0) + : 0; + + do_replace = should_quote ? mtype : NO_MATCH; + /* Quote the replacement, since we found an embedded + word break character in a potential match. */ + if (do_replace != NO_MATCH && rl_filename_quoting_function) + replacement = (*rl_filename_quoting_function) (match, do_replace, qc); + } + return (replacement); +} + +static void +insert_match (match, start, mtype, qc) + char *match; + int start, mtype; + char *qc; +{ + char *replacement; + char oqc; + + oqc = qc ? *qc : '\0'; + replacement = make_quoted_replacement (match, mtype, qc); + + /* Now insert the match. */ + if (replacement) + { + /* Don't double an opening quote character. */ + if (qc && *qc && start && rl_line_buffer[start - 1] == *qc && + replacement[0] == *qc) + start--; + /* If make_quoted_replacement changed the quoting character, remove + the opening quote and insert the (fully-quoted) replacement. */ + else if (qc && (*qc != oqc) && start && rl_line_buffer[start - 1] == oqc && + replacement[0] != oqc) + start--; + _rl_replace_text (replacement, start, rl_point - 1); + if (replacement != match) + free (replacement); + } +} + +/* Append any necessary closing quote and a separator character to the + just-inserted match. If the user has specified that directories + should be marked by a trailing `/', append one of those instead. The + default trailing character is a space. Returns the number of characters + appended. If NONTRIVIAL_MATCH is set, we test for a symlink (if the OS + has them) and don't add a suffix for a symlink to a directory. A + nontrivial match is one that actually adds to the word being completed. + The variable rl_completion_mark_symlink_dirs controls this behavior + (it's initially set to the what the user has chosen, indicated by the + value of _rl_complete_mark_symlink_dirs, but may be modified by an + application's completion function). */ +static int +append_to_match (text, delimiter, quote_char, nontrivial_match) + char *text; + int delimiter, quote_char, nontrivial_match; +{ + char temp_string[4], *filename; + int temp_string_index, s; + struct stat finfo; + + temp_string_index = 0; + if (quote_char && rl_point && rl_completion_suppress_quote == 0 && + rl_line_buffer[rl_point - 1] != quote_char) + temp_string[temp_string_index++] = quote_char; + + if (delimiter) + temp_string[temp_string_index++] = delimiter; + else if (rl_completion_suppress_append == 0 && rl_completion_append_character) + temp_string[temp_string_index++] = rl_completion_append_character; + + temp_string[temp_string_index++] = '\0'; + + if (rl_filename_completion_desired) + { + filename = tilde_expand (text); + s = (nontrivial_match && rl_completion_mark_symlink_dirs == 0) + ? LSTAT (filename, &finfo) + : stat (filename, &finfo); + if (s == 0 && S_ISDIR (finfo.st_mode)) + { + if (_rl_complete_mark_directories /* && rl_completion_suppress_append == 0 */) + { + /* This is clumsy. Avoid putting in a double slash if point + is at the end of the line and the previous character is a + slash. */ + if (rl_point && rl_line_buffer[rl_point] == '\0' && rl_line_buffer[rl_point - 1] == '/') + ; + else if (rl_line_buffer[rl_point] != '/') + rl_insert_text ("/"); + } + } +#ifdef S_ISLNK + /* Don't add anything if the filename is a symlink and resolves to a + directory. */ + else if (s == 0 && S_ISLNK (finfo.st_mode) && + stat (filename, &finfo) == 0 && S_ISDIR (finfo.st_mode)) + ; +#endif + else + { + if (rl_point == rl_end && temp_string_index) + rl_insert_text (temp_string); + } + free (filename); + } + else + { + if (rl_point == rl_end && temp_string_index) + rl_insert_text (temp_string); + } + + return (temp_string_index); +} + +static void +insert_all_matches (matches, point, qc) + char **matches; + int point; + char *qc; +{ + int i; + char *rp; + + rl_begin_undo_group (); + /* remove any opening quote character; make_quoted_replacement will add + it back. */ + if (qc && *qc && point && rl_line_buffer[point - 1] == *qc) + point--; + rl_delete_text (point, rl_point); + rl_point = point; + + if (matches[1]) + { + for (i = 1; matches[i]; i++) + { + rp = make_quoted_replacement (matches[i], SINGLE_MATCH, qc); + rl_insert_text (rp); + rl_insert_text (" "); + if (rp != matches[i]) + free (rp); + } + } + else + { + rp = make_quoted_replacement (matches[0], SINGLE_MATCH, qc); + rl_insert_text (rp); + rl_insert_text (" "); + if (rp != matches[0]) + free (rp); + } + rl_end_undo_group (); +} + +void +_rl_free_match_list (matches) + char **matches; +{ + register int i; + + if (matches == 0) + return; + + for (i = 0; matches[i]; i++) + free (matches[i]); + free (matches); +} + +/* Complete the word at or before point. + WHAT_TO_DO says what to do with the completion. + `?' means list the possible completions. + TAB means do standard completion. + `*' means insert all of the possible completions. + `!' means to do standard completion, and list all possible completions if + there is more than one. + `@' means to do standard completion, and list all possible completions if + there is more than one and partial completion is not possible. */ +int +rl_complete_internal (what_to_do) + int what_to_do; +{ + char **matches; + rl_compentry_func_t *our_func; + int start, end, delimiter, found_quote, i, nontrivial_lcd; + char *text, *saved_line_buffer; + char quote_char; + + RL_SETSTATE(RL_STATE_COMPLETING); + + set_completion_defaults (what_to_do); + + saved_line_buffer = rl_line_buffer ? savestring (rl_line_buffer) : (char *)NULL; + our_func = rl_completion_entry_function + ? rl_completion_entry_function + : rl_filename_completion_function; + /* We now look backwards for the start of a filename/variable word. */ + end = rl_point; + found_quote = delimiter = 0; + quote_char = '\0'; + + if (rl_point) + /* This (possibly) changes rl_point. If it returns a non-zero char, + we know we have an open quote. */ + quote_char = _rl_find_completion_word (&found_quote, &delimiter); + + start = rl_point; + rl_point = end; + + text = rl_copy_text (start, end); + matches = gen_completion_matches (text, start, end, our_func, found_quote, quote_char); + /* nontrivial_lcd is set if the common prefix adds something to the word + being completed. */ + nontrivial_lcd = matches && strcmp (text, matches[0]) != 0; + free (text); + + if (matches == 0) + { + rl_ding (); + FREE (saved_line_buffer); + completion_changed_buffer = 0; + RL_UNSETSTATE(RL_STATE_COMPLETING); + return (0); + } + + /* If we are matching filenames, the attempted completion function will + have set rl_filename_completion_desired to a non-zero value. The basic + rl_filename_completion_function does this. */ + i = rl_filename_completion_desired; + + if (postprocess_matches (&matches, i) == 0) + { + rl_ding (); + FREE (saved_line_buffer); + completion_changed_buffer = 0; + RL_UNSETSTATE(RL_STATE_COMPLETING); + return (0); + } + + switch (what_to_do) + { + case TAB: + case '!': + case '@': + /* Insert the first match with proper quoting. */ + if (*matches[0]) + insert_match (matches[0], start, matches[1] ? MULT_MATCH : SINGLE_MATCH, "e_char); + + /* If there are more matches, ring the bell to indicate. + If we are in vi mode, Posix.2 says to not ring the bell. + If the `show-all-if-ambiguous' variable is set, display + all the matches immediately. Otherwise, if this was the + only match, and we are hacking files, check the file to + see if it was a directory. If so, and the `mark-directories' + variable is set, add a '/' to the name. If not, and we + are at the end of the line, then add a space. */ + if (matches[1]) + { + if (what_to_do == '!') + { + display_matches (matches); + break; + } + else if (what_to_do == '@') + { + if (nontrivial_lcd == 0) + display_matches (matches); + break; + } + else if (rl_editing_mode != vi_mode) + rl_ding (); /* There are other matches remaining. */ + } + else + append_to_match (matches[0], delimiter, quote_char, nontrivial_lcd); + + break; + + case '*': + insert_all_matches (matches, start, "e_char); + break; + + case '?': + display_matches (matches); + break; + + default: + fprintf (stderr, "\r\nreadline: bad value %d for what_to_do in rl_complete\n", what_to_do); + rl_ding (); + FREE (saved_line_buffer); + RL_UNSETSTATE(RL_STATE_COMPLETING); + return 1; + } + + _rl_free_match_list (matches); + + /* Check to see if the line has changed through all of this manipulation. */ + if (saved_line_buffer) + { + completion_changed_buffer = strcmp (rl_line_buffer, saved_line_buffer) != 0; + free (saved_line_buffer); + } + + RL_UNSETSTATE(RL_STATE_COMPLETING); + return 0; +} + +/***************************************************************/ +/* */ +/* Application-callable completion match generator functions */ +/* */ +/***************************************************************/ + +/* Return an array of (char *) which is a list of completions for TEXT. + If there are no completions, return a NULL pointer. + The first entry in the returned array is the substitution for TEXT. + The remaining entries are the possible completions. + The array is terminated with a NULL pointer. + + ENTRY_FUNCTION is a function of two args, and returns a (char *). + The first argument is TEXT. + The second is a state argument; it should be zero on the first call, and + non-zero on subsequent calls. It returns a NULL pointer to the caller + when there are no more matches. + */ +char ** +rl_completion_matches (text, entry_function) + const char *text; + rl_compentry_func_t *entry_function; +{ + /* Number of slots in match_list. */ + int match_list_size; + + /* The list of matches. */ + char **match_list; + + /* Number of matches actually found. */ + int matches; + + /* Temporary string binder. */ + char *string; + + matches = 0; + match_list_size = 10; + match_list = (char **)xmalloc ((match_list_size + 1) * sizeof (char *)); + match_list[1] = (char *)NULL; + + while (string = (*entry_function) (text, matches)) + { + if (matches + 1 == match_list_size) + match_list = (char **)xrealloc + (match_list, ((match_list_size += 10) + 1) * sizeof (char *)); + + match_list[++matches] = string; + match_list[matches + 1] = (char *)NULL; + } + + /* If there were any matches, then look through them finding out the + lowest common denominator. That then becomes match_list[0]. */ + if (matches) + compute_lcd_of_matches (match_list, matches, text); + else /* There were no matches. */ + { + free (match_list); + match_list = (char **)NULL; + } + return (match_list); +} + +/* A completion function for usernames. + TEXT contains a partial username preceded by a random + character (usually `~'). */ +char * +rl_username_completion_function (text, state) + const char *text; + int state; +{ +#if defined (__WIN32__) || defined (__OPENNT) + return (char *)NULL; +#else /* !__WIN32__ && !__OPENNT) */ + static char *username = (char *)NULL; + static struct passwd *entry; + static int namelen, first_char, first_char_loc; + char *value; + + if (state == 0) + { + FREE (username); + + first_char = *text; + first_char_loc = first_char == '~'; + + username = savestring (&text[first_char_loc]); + namelen = strlen (username); + setpwent (); + } + +#if defined (HAVE_GETPWENT) + while (entry = getpwent ()) + { + /* Null usernames should result in all users as possible completions. */ + if (namelen == 0 || (STREQN (username, entry->pw_name, namelen))) + break; + } +#endif + + if (entry == 0) + { +#if defined (HAVE_GETPWENT) + endpwent (); +#endif + return ((char *)NULL); + } + else + { + value = (char *)xmalloc (2 + strlen (entry->pw_name)); + + *value = *text; + + strcpy (value + first_char_loc, entry->pw_name); + + if (first_char == '~') + rl_filename_completion_desired = 1; + + return (value); + } +#endif /* !__WIN32__ && !__OPENNT */ +} + +/* Okay, now we write the entry_function for filename completion. In the + general case. Note that completion in the shell is a little different + because of all the pathnames that must be followed when looking up the + completion for a command. */ +char * +rl_filename_completion_function (text, state) + const char *text; + int state; +{ + static DIR *directory = (DIR *)NULL; + static char *filename = (char *)NULL; + static char *dirname = (char *)NULL; + static char *users_dirname = (char *)NULL; + static int filename_len; + char *temp; + int dirlen; + struct dirent *entry; + + /* If we don't have any state, then do some initialization. */ + if (state == 0) + { + /* If we were interrupted before closing the directory or reading + all of its contents, close it. */ + if (directory) + { + closedir (directory); + directory = (DIR *)NULL; + } + FREE (dirname); + FREE (filename); + FREE (users_dirname); + + filename = savestring (text); + if (*text == 0) + text = "."; + dirname = savestring (text); + + temp = strrchr (dirname, '/'); + +#if defined (__MSDOS__) + /* special hack for //X/... */ + if (dirname[0] == '/' && dirname[1] == '/' && ISALPHA ((unsigned char)dirname[2]) && dirname[3] == '/') + temp = strrchr (dirname + 3, '/'); +#endif + + if (temp) + { + strcpy (filename, ++temp); + *temp = '\0'; + } +#if defined (__MSDOS__) + /* searches from current directory on the drive */ + else if (ISALPHA ((unsigned char)dirname[0]) && dirname[1] == ':') + { + strcpy (filename, dirname + 2); + dirname[2] = '\0'; + } +#endif + else + { + dirname[0] = '.'; + dirname[1] = '\0'; + } + + /* We aren't done yet. We also support the "~user" syntax. */ + + /* Save the version of the directory that the user typed. */ + users_dirname = savestring (dirname); + + if (*dirname == '~') + { + temp = tilde_expand (dirname); + free (dirname); + dirname = temp; + } + + if (rl_directory_rewrite_hook) + (*rl_directory_rewrite_hook) (&dirname); + + if (rl_directory_completion_hook && (*rl_directory_completion_hook) (&dirname)) + { + free (users_dirname); + users_dirname = savestring (dirname); + } + + directory = opendir (dirname); + filename_len = strlen (filename); + + rl_filename_completion_desired = 1; + } + + /* At this point we should entertain the possibility of hacking wildcarded + filenames, like /usr/man/man/te. If the directory name + contains globbing characters, then build an array of directories, and + then map over that list while completing. */ + /* *** UNIMPLEMENTED *** */ + + /* Now that we have some state, we can read the directory. */ + + entry = (struct dirent *)NULL; + while (directory && (entry = readdir (directory))) + { + /* Special case for no filename. If the user has disabled the + `match-hidden-files' variable, skip filenames beginning with `.'. + All other entries except "." and ".." match. */ + if (filename_len == 0) + { + if (_rl_match_hidden_files == 0 && HIDDEN_FILE (entry->d_name)) + continue; + + if (entry->d_name[0] != '.' || + (entry->d_name[1] && + (entry->d_name[1] != '.' || entry->d_name[2]))) + break; + } + else + { + /* Otherwise, if these match up to the length of filename, then + it is a match. */ + if (_rl_completion_case_fold) + { + if ((_rl_to_lower (entry->d_name[0]) == _rl_to_lower (filename[0])) && + (((int)D_NAMLEN (entry)) >= filename_len) && + (_rl_strnicmp (filename, entry->d_name, filename_len) == 0)) + break; + } + else + { + if ((entry->d_name[0] == filename[0]) && + (((int)D_NAMLEN (entry)) >= filename_len) && + (strncmp (filename, entry->d_name, filename_len) == 0)) + break; + } + } + } + + if (entry == 0) + { + if (directory) + { + closedir (directory); + directory = (DIR *)NULL; + } + if (dirname) + { + free (dirname); + dirname = (char *)NULL; + } + if (filename) + { + free (filename); + filename = (char *)NULL; + } + if (users_dirname) + { + free (users_dirname); + users_dirname = (char *)NULL; + } + + return (char *)NULL; + } + else + { + /* dirname && (strcmp (dirname, ".") != 0) */ + if (dirname && (dirname[0] != '.' || dirname[1])) + { + if (rl_complete_with_tilde_expansion && *users_dirname == '~') + { + dirlen = strlen (dirname); + temp = (char *)xmalloc (2 + dirlen + D_NAMLEN (entry)); + strcpy (temp, dirname); + /* Canonicalization cuts off any final slash present. We + may need to add it back. */ + if (dirname[dirlen - 1] != '/') + { + temp[dirlen++] = '/'; + temp[dirlen] = '\0'; + } + } + else + { + dirlen = strlen (users_dirname); + temp = (char *)xmalloc (2 + dirlen + D_NAMLEN (entry)); + strcpy (temp, users_dirname); + /* Make sure that temp has a trailing slash here. */ + if (users_dirname[dirlen - 1] != '/') + temp[dirlen++] = '/'; + } + + strcpy (temp + dirlen, entry->d_name); + } + else + temp = savestring (entry->d_name); + + return (temp); + } +} + +/* An initial implementation of a menu completion function a la tcsh. The + first time (if the last readline command was not rl_menu_complete), we + generate the list of matches. This code is very similar to the code in + rl_complete_internal -- there should be a way to combine the two. Then, + for each item in the list of matches, we insert the match in an undoable + fashion, with the appropriate character appended (this happens on the + second and subsequent consecutive calls to rl_menu_complete). When we + hit the end of the match list, we restore the original unmatched text, + ring the bell, and reset the counter to zero. */ +int +rl_menu_complete (count, ignore) + int count, ignore; +{ + rl_compentry_func_t *our_func; + int matching_filenames, found_quote; + + static char *orig_text; + static char **matches = (char **)0; + static int match_list_index = 0; + static int match_list_size = 0; + static int orig_start, orig_end; + static char quote_char; + static int delimiter; + + /* The first time through, we generate the list of matches and set things + up to insert them. */ + if (rl_last_func != rl_menu_complete) + { + /* Clean up from previous call, if any. */ + FREE (orig_text); + if (matches) + _rl_free_match_list (matches); + + match_list_index = match_list_size = 0; + matches = (char **)NULL; + + /* Only the completion entry function can change these. */ + set_completion_defaults ('%'); + + our_func = rl_completion_entry_function + ? rl_completion_entry_function + : rl_filename_completion_function; + + /* We now look backwards for the start of a filename/variable word. */ + orig_end = rl_point; + found_quote = delimiter = 0; + quote_char = '\0'; + + if (rl_point) + /* This (possibly) changes rl_point. If it returns a non-zero char, + we know we have an open quote. */ + quote_char = _rl_find_completion_word (&found_quote, &delimiter); + + orig_start = rl_point; + rl_point = orig_end; + + orig_text = rl_copy_text (orig_start, orig_end); + matches = gen_completion_matches (orig_text, orig_start, orig_end, + our_func, found_quote, quote_char); + + /* If we are matching filenames, the attempted completion function will + have set rl_filename_completion_desired to a non-zero value. The basic + rl_filename_completion_function does this. */ + matching_filenames = rl_filename_completion_desired; + + if (matches == 0 || postprocess_matches (&matches, matching_filenames) == 0) + { + rl_ding (); + FREE (matches); + matches = (char **)0; + FREE (orig_text); + orig_text = (char *)0; + completion_changed_buffer = 0; + return (0); + } + + for (match_list_size = 0; matches[match_list_size]; match_list_size++) + ; + /* matches[0] is lcd if match_list_size > 1, but the circular buffer + code below should take care of it. */ + } + + /* Now we have the list of matches. Replace the text between + rl_line_buffer[orig_start] and rl_line_buffer[rl_point] with + matches[match_list_index], and add any necessary closing char. */ + + if (matches == 0 || match_list_size == 0) + { + rl_ding (); + FREE (matches); + matches = (char **)0; + completion_changed_buffer = 0; + return (0); + } + + match_list_index += count; + if (match_list_index < 0) + match_list_index += match_list_size; + else + match_list_index %= match_list_size; + + if (match_list_index == 0 && match_list_size > 1) + { + rl_ding (); + insert_match (orig_text, orig_start, MULT_MATCH, "e_char); + } + else + { + insert_match (matches[match_list_index], orig_start, SINGLE_MATCH, "e_char); + append_to_match (matches[match_list_index], delimiter, quote_char, + strcmp (orig_text, matches[match_list_index])); + } + + completion_changed_buffer = 1; + return (0); +} diff --git a/external/gpl3/gdb/dist/readline/config.h.in b/external/gpl3/gdb/dist/readline/config.h.in new file mode 100644 index 000000000000..b4aae982a7b3 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/config.h.in @@ -0,0 +1,238 @@ +/* config.h.in. Maintained by hand. */ + +/* Define NO_MULTIBYTE_SUPPORT to not compile in support for multibyte + characters, even if the OS supports them. */ +#undef NO_MULTIBYTE_SUPPORT + +/* Define if on MINIX. */ +#undef _MINIX + +/* Define as the return type of signal handlers (int or void). */ +#undef RETSIGTYPE + +#undef VOID_SIGHANDLER + +/* Characteristics of the compiler. */ +#undef const + +#undef size_t + +#undef ssize_t + +#undef PROTOTYPES + +#undef __CHAR_UNSIGNED__ + +/* Define if the `S_IS*' macros in do not work properly. */ +#undef STAT_MACROS_BROKEN + +/* Define if you have the fcntl function. */ +#undef HAVE_FCNTL + +/* Define if you have the getpwent function. */ +#undef HAVE_GETPWENT + +/* Define if you have the getpwnam function. */ +#undef HAVE_GETPWNAM + +/* Define if you have the getpwuid function. */ +#undef HAVE_GETPWUID + +/* Define if you have the isascii function. */ +#undef HAVE_ISASCII + +/* Define if you have the isxdigit function. */ +#undef HAVE_ISXDIGIT + +/* Define if you have the kill function. */ +#undef HAVE_KILL + +/* Define if you have the lstat function. */ +#undef HAVE_LSTAT + +/* Define if you have the mbrlen function. */ +#undef HAVE_MBRLEN + +/* Define if you have the mbrtowc function. */ +#undef HAVE_MBRTOWC + +/* Define if you have the mbsrtowcs function. */ +#undef HAVE_MBSRTOWCS + +/* Define if you have the memmove function. */ +#undef HAVE_MEMMOVE + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the select function. */ +#undef HAVE_SELECT + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strcoll function. */ +#undef HAVE_STRCOLL + +#undef STRCOLL_BROKEN + +/* Define if you have the strpbrk function. */ +#undef HAVE_STRPBRK + +/* Define if you have the tcgetattr function. */ +#undef HAVE_TCGETATTR + +/* Define if you have the vsnprintf function. */ +#undef HAVE_VSNPRINTF + +/* Define if you have the wctomb function. */ +#undef HAVE_WCTOMB + +/* Define if you have the wcwidth function. */ +#undef HAVE_WCWIDTH + +#undef STDC_HEADERS + +/* Define if you have the header file. */ +#undef HAVE_DIRENT_H + +/* Define if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define if you have the header file. */ +#undef HAVE_LANGINFO_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define if you have the header file. */ +#undef HAVE_NDIR_H + +/* Define if you have the header file. */ +#undef HAVE_PWD_H + +/* Define if you have the header file. */ +#undef HAVE_STDARG_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_DIR_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_FILE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_NDIR_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PTE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PTEM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_SELECT_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_STREAM_H + +/* Define if you have the header file. */ +#undef HAVE_TERMCAP_H + +/* Define if you have the header file. */ +#undef HAVE_TERMIO_H + +/* Define if you have the header file. */ +#undef HAVE_TERMIOS_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_VARARGS_H + +/* Define if you have the header file. */ +#undef HAVE_WCHAR_H + +/* Define if you have the header file. */ +#undef HAVE_WCTYPE_H + +#undef HAVE_MBSTATE_T + +/* Define if you have and nl_langinfo(CODESET). */ +#undef HAVE_LANGINFO_CODESET + +/* Definitions pulled in from aclocal.m4. */ +#undef VOID_SIGHANDLER + +#undef GWINSZ_IN_SYS_IOCTL + +#undef STRUCT_WINSIZE_IN_SYS_IOCTL + +#undef STRUCT_WINSIZE_IN_TERMIOS + +#undef TIOCSTAT_IN_SYS_IOCTL + +#undef FIONREAD_IN_SYS_IOCTL + +#undef SPEED_T_IN_SYS_TYPES + +#undef HAVE_GETPW_DECLS + +#undef STRUCT_DIRENT_HAS_D_INO + +#undef STRUCT_DIRENT_HAS_D_FILENO + +#undef HAVE_BSD_SIGNALS + +#undef HAVE_POSIX_SIGNALS + +#undef HAVE_USG_SIGHOLD + +#undef MUST_REINSTALL_SIGHANDLERS + +#undef HAVE_POSIX_SIGSETJMP + +#undef CTYPE_NON_ASCII + +/* modify settings or make new ones based on what autoconf tells us. */ + +/* Ultrix botches type-ahead when switching from canonical to + non-canonical mode, at least through version 4.3 */ +#if !defined (HAVE_TERMIOS_H) || !defined (HAVE_TCGETATTR) || defined (ultrix) +# define TERMIOS_MISSING +#endif + +#if defined (STRCOLL_BROKEN) +# undef HAVE_STRCOLL +#endif + +#if defined (__STDC__) && defined (HAVE_STDARG_H) +# define PREFER_STDARG +# define USE_VARARGS +#else +# if defined (HAVE_VARARGS_H) +# define PREFER_VARARGS +# define USE_VARARGS +# endif +#endif diff --git a/external/gpl3/gdb/dist/readline/configure b/external/gpl3/gdb/dist/readline/configure new file mode 100755 index 000000000000..8a90f0f5968a --- /dev/null +++ b/external/gpl3/gdb/dist/readline/configure @@ -0,0 +1,7129 @@ +#! /bin/sh +# From configure.in for Readline 5.1, version 2.59. +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64 for readline 5.1-release. +# +# Report bugs to . +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org and +$0: bug-readline@gnu.org about your system, including any +$0: error possibly output before this message. Then install +$0: a modern shell, or manually run the script under such a +$0: shell if you do have one." + fi + exit 1 +fi +fi +fi +SHELL=${CONFIG_SHELL-/bin/sh} +export SHELL +# Unset more variables known to interfere with behavior of common tools. +CLICOLOR_FORCE= GREP_OPTIONS= +unset CLICOLOR_FORCE GREP_OPTIONS + +## --------------------- ## +## M4sh Shell Functions. ## +## --------------------- ## +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. 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" >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + + +opt_curses=no +opt_purify=no + + +# Check whether --with-curses was given. +if test "${with_curses+set}" = set; then : + withval=$with_curses; opt_curses=$withval +fi + + +# Check whether --with-purify was given. +if test "${with_purify+set}" = set; then : + withval=$with_purify; opt_purify=$withval +fi + + +if test "$opt_curses" = "yes"; then + prefer_curses=yes +fi + +if test "$opt_purify" = yes; then + PURIFY="purify" +else + PURIFY= +fi + +opt_multibyte=yes +opt_static_libs=yes +opt_shared_libs=no + +# Check whether --enable-multibyte was given. +if test "${enable_multibyte+set}" = set; then : + enableval=$enable_multibyte; opt_multibyte=$enableval +fi + +# Check whether --enable-static was given. +if test "${enable_static+set}" = set; then : + enableval=$enable_static; opt_static_libs=$enableval +fi + + +if test $opt_multibyte = no; then +$as_echo "#define NO_MULTIBYTE_SUPPORT 1" >>confdefs.h + +fi + + + +CROSS_COMPILE= +if test "x$cross_compiling" = "xyes"; then + case "${host}" in + *-cygwin*) + cross_cache=${srcdir}/cross-build/cygwin.cache + ;; + *-mingw*) + cross_cache=${srcdir}/cross-build/mingw.cache + ;; + i[3456]86-*-beos*) + cross_cache=${srcdir}/cross-build/x86-beos.cache + ;; + *) echo "configure: cross-compiling for $host is not supported" >&2 + ;; + esac + if test -n "${cross_cache}" && test -r "${cross_cache}"; then + echo "loading cross-build cache file ${cross_cache}" + . ${cross_cache} + fi + unset cross_cache + CROSS_COMPILE='-DCROSS_COMPILING' + +fi + +echo "" +echo "Beginning configuration for readline-$LIBVERSION for ${host_cpu}-${host_vendor}-${host_os}" +echo "" + +# We want these before the checks, so the checks can modify their values. +test -z "$CFLAGS" && CFLAGS=-g auto_cflags=1 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 +$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... 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" >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." 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"$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + + + ac_fn_c_check_header_mongrel "$LINENO" "minix/config.h" "ac_cv_header_minix_config_h" "$ac_includes_default" +if test "x$ac_cv_header_minix_config_h" = x""yes; then : + MINIX=yes +else + MINIX= +fi + + + if test "$MINIX" = yes; then + +$as_echo "#define _POSIX_SOURCE 1" >>confdefs.h + + +$as_echo "#define _POSIX_1_SOURCE 2" >>confdefs.h + + +$as_echo "#define _MINIX 1" >>confdefs.h + + fi + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether it is safe to define __EXTENSIONS__" >&5 +$as_echo_n "checking whether it is safe to define __EXTENSIONS__... " >&6; } +if test "${ac_cv_safe_to_define___extensions__+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +# define __EXTENSIONS__ 1 + $ac_includes_default +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_safe_to_define___extensions__=yes +else + ac_cv_safe_to_define___extensions__=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_safe_to_define___extensions__" >&5 +$as_echo "$ac_cv_safe_to_define___extensions__" >&6; } + test $ac_cv_safe_to_define___extensions__ = yes && + $as_echo "#define __EXTENSIONS__ 1" >>confdefs.h + + $as_echo "#define _ALL_SOURCE 1" >>confdefs.h + + $as_echo "#define _GNU_SOURCE 1" >>confdefs.h + + $as_echo "#define _POSIX_PTHREAD_SEMANTICS 1" >>confdefs.h + + $as_echo "#define _TANDEM_SOURCE 1" >>confdefs.h + + + + + +if test "x$cross_compiling" = "xyes"; then + case "${host}" in + *-cygwin*) + cross_cache=${srcdir}/cross-build/cygwin.cache + LOCAL_CFLAGS="$LOCAL_CFLAGS -I${srcdir}/../libtermcap" + ;; + *-mingw32*) + cross_cache=${srcdir}/cross-build/mingw.cache + ;; + *) echo "configure: cross-compiling for a non-cygwin target is not supported" >&2 + ;; + esac + + if test "x$cross_cache" != "x"; then + if test -r "${cross_cache}"; then + echo "loading cross-build cache file ${cross_cache}" + . ${cross_cache} + fi + unset cross_cache + fi +fi + +if test -z "$CC_FOR_BUILD"; then + if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' + else + CC_FOR_BUILD=gcc + fi +fi + + + +# If we're using gcc and the user hasn't specified CFLAGS, add -O to CFLAGS. +test -n "$GCC" && test -n "$auto_cflags" && CFLAGS="$CFLAGS -O" + +if test $ac_cv_c_compiler_gnu = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC needs -traditional" >&5 +$as_echo_n "checking whether $CC needs -traditional... " >&6; } +if test "${ac_cv_prog_gcc_traditional+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_pattern="Autoconf.*'x'" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +Autoconf TIOCGETP +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then : + ac_cv_prog_gcc_traditional=yes +else + ac_cv_prog_gcc_traditional=no +fi +rm -f conftest* + + + if test $ac_cv_prog_gcc_traditional = no; then + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +Autoconf TCGETA +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then : + ac_cv_prog_gcc_traditional=yes +fi +rm -f conftest* + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_gcc_traditional" >&5 +$as_echo "$ac_cv_prog_gcc_traditional" >&6; } + if test $ac_cv_prog_gcc_traditional = yes; then + CC="$CC -traditional" + fi +fi + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +# Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AR="" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_prog_AR" && ac_cv_prog_AR="ar" +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +test -n "$ARFLAGS" || ARFLAGS="cr" +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +MAKE_SHELL=/bin/sh + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for an ANSI C-conforming const" >&5 +$as_echo_n "checking for an ANSI C-conforming const... " >&6; } +if test "${ac_cv_c_const+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +/* FIXME: Include the comments suggested by Paul. */ +#ifndef __cplusplus + /* Ultrix mips cc rejects this. */ + typedef int charset[2]; + const charset cs; + /* SunOS 4.1.1 cc rejects this. */ + char const *const *pcpcc; + char **ppc; + /* NEC SVR4.0.2 mips cc rejects this. */ + struct point {int x, y;}; + static struct point const zero = {0,0}; + /* AIX XL C 1.02.0.0 rejects this. + It does not let you subtract one const X* pointer from another in + an arm of an if-expression whose if-part is not a constant + expression */ + const char *g = "string"; + pcpcc = &g + (g ? g-g : 0); + /* HPUX 7.0 cc rejects these. */ + ++pcpcc; + ppc = (char**) pcpcc; + pcpcc = (char const *const *) ppc; + { /* SCO 3.2v4 cc rejects this. */ + char *t; + char const *s = 0 ? (char *) 0 : (char const *) 0; + + *t++ = 0; + if (s) return 0; + } + { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ + int x[] = {25, 17}; + const int *foo = &x[0]; + ++foo; + } + { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ + typedef const int *iptr; + iptr p = 0; + ++p; + } + { /* AIX XL C 1.02.0.0 rejects this saying + "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ + struct s { int j; const int *ap[3]; }; + struct s *b; b->j = 5; + } + { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; + if (!foo) return 0; + } + return !cs[0] && !zero.x; +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_const=yes +else + ac_cv_c_const=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_const" >&5 +$as_echo "$ac_cv_c_const" >&6; } +if test $ac_cv_c_const = no; then + +$as_echo "#define const /**/" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for function prototypes" >&5 +$as_echo_n "checking for function prototypes... " >&6; } +if test "$ac_cv_prog_cc_c89" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define PROTOTYPES 1" >>confdefs.h + + +$as_echo "#define __PROTOTYPES 1" >>confdefs.h + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether char is unsigned" >&5 +$as_echo_n "checking whether char is unsigned... " >&6; } +if test "${ac_cv_c_char_unsigned+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ +static int test_array [1 - 2 * !(((char) -1) < 0)]; +test_array [0] = 0 + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_char_unsigned=no +else + ac_cv_c_char_unsigned=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_char_unsigned" >&5 +$as_echo "$ac_cv_c_char_unsigned" >&6; } +if test $ac_cv_c_char_unsigned = yes && test "$GCC" != yes; then + $as_echo "#define __CHAR_UNSIGNED__ 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_type_signal=int +else + ac_cv_type_signal=void +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + +ac_fn_c_check_type "$LINENO" "size_t" "ac_cv_type_size_t" "$ac_includes_default" +if test "x$ac_cv_type_size_t" = x""yes; then : + +else + +cat >>confdefs.h <<_ACEOF +#define size_t unsigned int +_ACEOF + +fi + +ac_fn_c_check_type "$LINENO" "ssize_t" "ac_cv_type_ssize_t" "$ac_includes_default" +if test "x$ac_cv_type_ssize_t" = x""yes; then : + +else + +cat >>confdefs.h <<_ACEOF +#define ssize_t int +_ACEOF + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether stat file-mode macros are broken" >&5 +$as_echo_n "checking whether stat file-mode macros are broken... " >&6; } +if test "${ac_cv_header_stat_broken+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +#if defined S_ISBLK && defined S_IFDIR +extern char c1[S_ISBLK (S_IFDIR) ? -1 : 1]; +#endif + +#if defined S_ISBLK && defined S_IFCHR +extern char c2[S_ISBLK (S_IFCHR) ? -1 : 1]; +#endif + +#if defined S_ISLNK && defined S_IFREG +extern char c3[S_ISLNK (S_IFREG) ? -1 : 1]; +#endif + +#if defined S_ISSOCK && defined S_IFREG +extern char c4[S_ISSOCK (S_IFREG) ? -1 : 1]; +#endif + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stat_broken=no +else + ac_cv_header_stat_broken=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stat_broken" >&5 +$as_echo "$ac_cv_header_stat_broken" >&6; } +if test $ac_cv_header_stat_broken = yes; then + +$as_echo "#define STAT_MACROS_BROKEN 1" >>confdefs.h + +fi + +ac_header_dirent=no +for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h; do + as_ac_Header=`$as_echo "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_hdr that defines DIR" >&5 +$as_echo_n "checking for $ac_hdr that defines DIR... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include <$ac_hdr> + +int +main () +{ +if ((DIR *) 0) +return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$as_ac_Header=yes" +else + eval "$as_ac_Header=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$as_ac_Header + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_hdr" | $as_tr_cpp` 1 +_ACEOF + +ac_header_dirent=$ac_hdr; break +fi + +done +# Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. +if test $ac_header_dirent = dirent.h; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' dir; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_opendir=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then : + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then : + +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' x; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_opendir=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then : + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then : + +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +fi + + +for ac_func in fcntl kill lstat +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +for ac_func in memmove putenv select setenv setlocale \ + strcasecmp strpbrk tcgetattr vsnprintf +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +for ac_func in isascii isxdigit +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +for ac_func in getpwent getpwnam getpwuid +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for working strcoll" >&5 +$as_echo_n "checking for working strcoll... " >&6; } +if test "${ac_cv_func_strcoll_works+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + ac_cv_func_strcoll_works=no +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ +return (strcoll ("abc", "def") >= 0 || + strcoll ("ABC", "DEF") >= 0 || + strcoll ("123", "456") >= 0) + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_func_strcoll_works=yes +else + ac_cv_func_strcoll_works=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_func_strcoll_works" >&5 +$as_echo "$ac_cv_func_strcoll_works" >&6; } +if test $ac_cv_func_strcoll_works = yes; then + +$as_echo "#define HAVE_STRCOLL 1" >>confdefs.h + +fi + + +for ac_header in fcntl.h unistd.h stdlib.h varargs.h stdarg.h string.h strings.h \ + limits.h locale.h pwd.h memory.h termcap.h termios.h termio.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in sys/pte.h sys/stream.h sys/select.h sys/file.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in sys/ptem.h +do : + ac_fn_c_check_header_compile "$LINENO" "sys/ptem.h" "ac_cv_header_sys_ptem_h" " +#if HAVE_SYS_STREAM_H +# include +#endif + +" +if test "x$ac_cv_header_sys_ptem_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_SYS_PTEM_H 1 +_ACEOF + +fi + +done + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for type of signal functions" >&5 +$as_echo_n "checking for type of signal functions... " >&6; } +if test "${bash_cv_signal_vintage+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + + sigset_t ss; + struct sigaction sa; + sigemptyset(&ss); sigsuspend(&ss); + sigaction(SIGINT, &sa, (struct sigaction *) 0); + sigprocmask(SIG_BLOCK, &ss, (sigset_t *) 0); + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + bash_cv_signal_vintage=posix +else + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ + + int mask = sigmask(SIGINT); + sigsetmask(mask); sigblock(mask); sigpause(mask); + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + bash_cv_signal_vintage=4.2bsd +else + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + #include + RETSIGTYPE foo() { } +int +main () +{ + + int mask = sigmask(SIGINT); + sigset(SIGINT, foo); sigrelse(SIGINT); + sighold(SIGINT); sigpause(SIGINT); + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + bash_cv_signal_vintage=svr3 +else + bash_cv_signal_vintage=v7 + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_signal_vintage" >&5 +$as_echo "$bash_cv_signal_vintage" >&6; } +if test "$bash_cv_signal_vintage" = posix; then +$as_echo "#define HAVE_POSIX_SIGNALS 1" >>confdefs.h + +elif test "$bash_cv_signal_vintage" = "4.2bsd"; then +$as_echo "#define HAVE_BSD_SIGNALS 1" >>confdefs.h + +elif test "$bash_cv_signal_vintage" = svr3; then +$as_echo "#define HAVE_USG_SIGHOLD 1" >>confdefs.h + +fi + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if signal handlers must be reinstalled when invoked" >&5 +$as_echo_n "checking if signal handlers must be reinstalled when invoked... " >&6; } +if test "${bash_cv_must_reinstall_sighandlers+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cannot check signal handling if cross compiling -- defaulting to no" >&5 +$as_echo "$as_me: WARNING: cannot check signal handling if cross compiling -- defaulting to no" >&2;} + bash_cv_must_reinstall_sighandlers=no + +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +typedef RETSIGTYPE sigfunc(); + +int nsigint; + +#ifdef HAVE_POSIX_SIGNALS +sigfunc * +set_signal_handler(sig, handler) + int sig; + sigfunc *handler; +{ + struct sigaction act, oact; + act.sa_handler = handler; + act.sa_flags = 0; + sigemptyset (&act.sa_mask); + sigemptyset (&oact.sa_mask); + sigaction (sig, &act, &oact); + return (oact.sa_handler); +} +#else +#define set_signal_handler(s, h) signal(s, h) +#endif + +RETSIGTYPE +sigint(s) +int s; +{ + nsigint++; +} + +main() +{ + nsigint = 0; + set_signal_handler(SIGINT, sigint); + kill((int)getpid(), SIGINT); + kill((int)getpid(), SIGINT); + exit(nsigint != 2); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + bash_cv_must_reinstall_sighandlers=no +else + bash_cv_must_reinstall_sighandlers=yes +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_must_reinstall_sighandlers" >&5 +$as_echo "$bash_cv_must_reinstall_sighandlers" >&6; } +if test $bash_cv_must_reinstall_sighandlers = yes; then +$as_echo "#define MUST_REINSTALL_SIGHANDLERS 1" >>confdefs.h + +fi + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for presence of POSIX-style sigsetjmp/siglongjmp" >&5 +$as_echo_n "checking for presence of POSIX-style sigsetjmp/siglongjmp... " >&6; } +if test "${bash_cv_func_sigsetjmp+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cannot check for sigsetjmp/siglongjmp if cross-compiling -- defaulting to missing" >&5 +$as_echo "$as_me: WARNING: cannot check for sigsetjmp/siglongjmp if cross-compiling -- defaulting to missing" >&2;} + bash_cv_func_sigsetjmp=missing + +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#ifdef HAVE_UNISTD_H +#include +#endif +#include +#include +#include + +main() +{ +#if !defined (_POSIX_VERSION) || !defined (HAVE_POSIX_SIGNALS) +exit (1); +#else + +int code; +sigset_t set, oset; +sigjmp_buf xx; + +/* get the mask */ +sigemptyset(&set); +sigemptyset(&oset); +sigprocmask(SIG_BLOCK, (sigset_t *)NULL, &set); +sigprocmask(SIG_BLOCK, (sigset_t *)NULL, &oset); + +/* save it */ +code = sigsetjmp(xx, 1); +if (code) + exit(0); /* could get sigmask and compare to oset here. */ + +/* change it */ +sigaddset(&set, SIGINT); +sigprocmask(SIG_BLOCK, &set, (sigset_t *)NULL); + +/* and siglongjmp */ +siglongjmp(xx, 10); +exit(1); +#endif +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + bash_cv_func_sigsetjmp=present +else + bash_cv_func_sigsetjmp=missing +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_func_sigsetjmp" >&5 +$as_echo "$bash_cv_func_sigsetjmp" >&6; } +if test $bash_cv_func_sigsetjmp = present; then +$as_echo "#define HAVE_POSIX_SIGSETJMP 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for lstat" >&5 +$as_echo_n "checking for lstat... " >&6; } +if test "${bash_cv_func_lstat+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include + +int +main () +{ + lstat(".",(struct stat *)0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + bash_cv_func_lstat=yes +else + bash_cv_func_lstat=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_func_lstat" >&5 +$as_echo "$bash_cv_func_lstat" >&6; } +if test $bash_cv_func_lstat = yes; then + $as_echo "#define HAVE_LSTAT 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether or not strcoll and strcmp differ" >&5 +$as_echo_n "checking whether or not strcoll and strcmp differ... " >&6; } +if test "${bash_cv_func_strcoll_broken+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cannot check strcoll if cross compiling -- defaulting to no" >&5 +$as_echo "$as_me: WARNING: cannot check strcoll if cross compiling -- defaulting to no" >&2;} + bash_cv_func_strcoll_broken=no + +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#if defined (HAVE_LOCALE_H) +#include +#endif + +main(c, v) +int c; +char *v[]; +{ + int r1, r2; + char *deflocale, *defcoll; + +#ifdef HAVE_SETLOCALE + deflocale = setlocale(LC_ALL, ""); + defcoll = setlocale(LC_COLLATE, ""); +#endif + +#ifdef HAVE_STRCOLL + /* These two values are taken from tests/glob-test. */ + r1 = strcoll("abd", "aXd"); +#else + r1 = 0; +#endif + r2 = strcmp("abd", "aXd"); + + /* These two should both be greater than 0. It is permissible for + a system to return different values, as long as the sign is the + same. */ + + /* Exit with 1 (failure) if these two values are both > 0, since + this tests whether strcoll(3) is broken with respect to strcmp(3) + in the default locale. */ + exit (r1 > 0 && r2 > 0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + bash_cv_func_strcoll_broken=yes +else + bash_cv_func_strcoll_broken=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_func_strcoll_broken" >&5 +$as_echo "$bash_cv_func_strcoll_broken" >&6; } +if test $bash_cv_func_strcoll_broken = yes; then +$as_echo "#define STRCOLL_BROKEN 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the ctype macros accept non-ascii characters" >&5 +$as_echo_n "checking whether the ctype macros accept non-ascii characters... " >&6; } +if test "${bash_cv_func_ctype_nonascii+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cannot check ctype macros if cross compiling -- defaulting to no" >&5 +$as_echo "$as_me: WARNING: cannot check ctype macros if cross compiling -- defaulting to no" >&2;} + bash_cv_func_ctype_nonascii=no + +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#ifdef HAVE_LOCALE_H +#include +#endif +#include +#include + +main(c, v) +int c; +char *v[]; +{ + char *deflocale; + unsigned char x; + int r1, r2; + +#ifdef HAVE_SETLOCALE + /* We take a shot here. If that locale is not known, try the + system default. We try this one because '\342' (226) is + known to be a printable character in that locale. */ + deflocale = setlocale(LC_ALL, "en_US.ISO8859-1"); + if (deflocale == 0) + deflocale = setlocale(LC_ALL, ""); +#endif + + x = '\342'; + r1 = isprint(x); + x -= 128; + r2 = isprint(x); + exit (r1 == 0 || r2 == 0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + bash_cv_func_ctype_nonascii=yes +else + bash_cv_func_ctype_nonascii=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_func_ctype_nonascii" >&5 +$as_echo "$bash_cv_func_ctype_nonascii" >&6; } +if test $bash_cv_func_ctype_nonascii = yes; then +$as_echo "#define CTYPE_NON_ASCII 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether getpw functions are declared in pwd.h" >&5 +$as_echo_n "checking whether getpw functions are declared in pwd.h... " >&6; } +if test "${bash_cv_getpw_declared+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#ifdef HAVE_UNISTD_H +# include +#endif +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "getpwuid" >/dev/null 2>&1; then : + bash_cv_getpw_declared=yes +else + bash_cv_getpw_declared=no +fi +rm -f conftest* + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_getpw_declared" >&5 +$as_echo "$bash_cv_getpw_declared" >&6; } +if test $bash_cv_getpw_declared = yes; then +$as_echo "#define HAVE_GETPW_DECLS 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether termios.h defines TIOCGWINSZ" >&5 +$as_echo_n "checking whether termios.h defines TIOCGWINSZ... " >&6; } +if test "${ac_cv_sys_tiocgwinsz_in_termios_h+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#ifdef TIOCGWINSZ + yes +#endif + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then : + ac_cv_sys_tiocgwinsz_in_termios_h=yes +else + ac_cv_sys_tiocgwinsz_in_termios_h=no +fi +rm -f conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sys_tiocgwinsz_in_termios_h" >&5 +$as_echo "$ac_cv_sys_tiocgwinsz_in_termios_h" >&6; } + +if test $ac_cv_sys_tiocgwinsz_in_termios_h != yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether sys/ioctl.h defines TIOCGWINSZ" >&5 +$as_echo_n "checking whether sys/ioctl.h defines TIOCGWINSZ... " >&6; } +if test "${ac_cv_sys_tiocgwinsz_in_sys_ioctl_h+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#ifdef TIOCGWINSZ + yes +#endif + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then : + ac_cv_sys_tiocgwinsz_in_sys_ioctl_h=yes +else + ac_cv_sys_tiocgwinsz_in_sys_ioctl_h=no +fi +rm -f conftest* + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_sys_tiocgwinsz_in_sys_ioctl_h" >&5 +$as_echo "$ac_cv_sys_tiocgwinsz_in_sys_ioctl_h" >&6; } + + if test $ac_cv_sys_tiocgwinsz_in_sys_ioctl_h = yes; then + +$as_echo "#define GWINSZ_IN_SYS_IOCTL 1" >>confdefs.h + + fi +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether signal handlers are of type void" >&5 +$as_echo_n "checking whether signal handlers are of type void... " >&6; } +if test "${bash_cv_void_sighandler+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#ifdef signal +#undef signal +#endif +#ifdef __cplusplus +extern "C" +#endif +void (*signal ()) (); +int +main () +{ +int i; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_void_sighandler=yes +else + bash_cv_void_sighandler=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_void_sighandler" >&5 +$as_echo "$bash_cv_void_sighandler" >&6; } +if test $bash_cv_void_sighandler = yes; then +$as_echo "#define VOID_SIGHANDLER 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for TIOCSTAT in sys/ioctl.h" >&5 +$as_echo_n "checking for TIOCSTAT in sys/ioctl.h... " >&6; } +if test "${bash_cv_tiocstat_in_ioctl+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +int +main () +{ +int x = TIOCSTAT; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_tiocstat_in_ioctl=yes +else + bash_cv_tiocstat_in_ioctl=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_tiocstat_in_ioctl" >&5 +$as_echo "$bash_cv_tiocstat_in_ioctl" >&6; } +if test $bash_cv_tiocstat_in_ioctl = yes; then +$as_echo "#define TIOCSTAT_IN_SYS_IOCTL 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for FIONREAD in sys/ioctl.h" >&5 +$as_echo_n "checking for FIONREAD in sys/ioctl.h... " >&6; } +if test "${bash_cv_fionread_in_ioctl+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +int +main () +{ +int x = FIONREAD; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_fionread_in_ioctl=yes +else + bash_cv_fionread_in_ioctl=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_fionread_in_ioctl" >&5 +$as_echo "$bash_cv_fionread_in_ioctl" >&6; } +if test $bash_cv_fionread_in_ioctl = yes; then +$as_echo "#define FIONREAD_IN_SYS_IOCTL 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for speed_t in sys/types.h" >&5 +$as_echo_n "checking for speed_t in sys/types.h... " >&6; } +if test "${bash_cv_speed_t_in_sys_types+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +speed_t x; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_speed_t_in_sys_types=yes +else + bash_cv_speed_t_in_sys_types=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_speed_t_in_sys_types" >&5 +$as_echo "$bash_cv_speed_t_in_sys_types" >&6; } +if test $bash_cv_speed_t_in_sys_types = yes; then +$as_echo "#define SPEED_T_IN_SYS_TYPES 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for struct winsize in sys/ioctl.h and termios.h" >&5 +$as_echo_n "checking for struct winsize in sys/ioctl.h and termios.h... " >&6; } +if test "${bash_cv_struct_winsize_header+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +int +main () +{ +struct winsize x; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_struct_winsize_header=ioctl_h +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +int +main () +{ +struct winsize x; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_struct_winsize_header=termios_h +else + bash_cv_struct_winsize_header=other +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +if test $bash_cv_struct_winsize_header = ioctl_h; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: sys/ioctl.h" >&5 +$as_echo "sys/ioctl.h" >&6; } + $as_echo "#define STRUCT_WINSIZE_IN_SYS_IOCTL 1" >>confdefs.h + +elif test $bash_cv_struct_winsize_header = termios_h; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: termios.h" >&5 +$as_echo "termios.h" >&6; } + $as_echo "#define STRUCT_WINSIZE_IN_TERMIOS 1" >>confdefs.h + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: not found" >&5 +$as_echo "not found" >&6; } +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for struct dirent.d_ino" >&5 +$as_echo_n "checking for struct dirent.d_ino... " >&6; } +if test "${bash_cv_dirent_has_dino+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ + +int +main () +{ + +struct dirent d; int z; z = d.d_ino; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_dirent_has_dino=yes +else + bash_cv_dirent_has_dino=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_dirent_has_dino" >&5 +$as_echo "$bash_cv_dirent_has_dino" >&6; } +if test $bash_cv_dirent_has_dino = yes; then +$as_echo "#define HAVE_STRUCT_DIRENT_D_INO 1" >>confdefs.h + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for struct dirent.d_fileno" >&5 +$as_echo_n "checking for struct dirent.d_fileno... " >&6; } +if test "${bash_cv_dirent_has_d_fileno+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include +#ifdef HAVE_UNISTD_H +# include +#endif /* HAVE_UNISTD_H */ +#if defined(HAVE_DIRENT_H) +# include +#else +# define dirent direct +# ifdef HAVE_SYS_NDIR_H +# include +# endif /* SYSNDIR */ +# ifdef HAVE_SYS_DIR_H +# include +# endif /* SYSDIR */ +# ifdef HAVE_NDIR_H +# include +# endif +#endif /* HAVE_DIRENT_H */ + +int +main () +{ + +struct dirent d; int z; z = d.d_fileno; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_dirent_has_d_fileno=yes +else + bash_cv_dirent_has_d_fileno=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_dirent_has_d_fileno" >&5 +$as_echo "$bash_cv_dirent_has_d_fileno" >&6; } +if test $bash_cv_dirent_has_d_fileno = yes; then +$as_echo "#define HAVE_STRUCT_DIRENT_D_FILENO 1" >>confdefs.h + +fi + + +case "$host_os" in +aix*) prefer_curses=yes ;; +esac + +if test "X$bash_cv_termcap_lib" = "X"; then +_bash_needmsg=yes +else +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking which library has the termcap functions" >&5 +$as_echo_n "checking which library has the termcap functions... " >&6; } +_bash_needmsg= +fi +if test "${bash_cv_termcap_lib+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_fn_c_check_func "$LINENO" "tgetent" "ac_cv_func_tgetent" +if test "x$ac_cv_func_tgetent" = x""yes; then : + bash_cv_termcap_lib=libc +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tgetent in -ltermcap" >&5 +$as_echo_n "checking for tgetent in -ltermcap... " >&6; } +if test "${ac_cv_lib_termcap_tgetent+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ltermcap $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_termcap_tgetent=yes +else + ac_cv_lib_termcap_tgetent=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_termcap_tgetent" >&5 +$as_echo "$ac_cv_lib_termcap_tgetent" >&6; } +if test "x$ac_cv_lib_termcap_tgetent" = x""yes; then : + bash_cv_termcap_lib=libtermcap +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tgetent in -ltinfo" >&5 +$as_echo_n "checking for tgetent in -ltinfo... " >&6; } +if test "${ac_cv_lib_tinfo_tgetent+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ltinfo $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_tinfo_tgetent=yes +else + ac_cv_lib_tinfo_tgetent=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tinfo_tgetent" >&5 +$as_echo "$ac_cv_lib_tinfo_tgetent" >&6; } +if test "x$ac_cv_lib_tinfo_tgetent" = x""yes; then : + bash_cv_termcap_lib=libtinfo +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tgetent in -lcurses" >&5 +$as_echo_n "checking for tgetent in -lcurses... " >&6; } +if test "${ac_cv_lib_curses_tgetent+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lcurses $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_curses_tgetent=yes +else + ac_cv_lib_curses_tgetent=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_curses_tgetent" >&5 +$as_echo "$ac_cv_lib_curses_tgetent" >&6; } +if test "x$ac_cv_lib_curses_tgetent" = x""yes; then : + bash_cv_termcap_lib=libcurses +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tgetent in -lncurses" >&5 +$as_echo_n "checking for tgetent in -lncurses... " >&6; } +if test "${ac_cv_lib_ncurses_tgetent+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lncurses $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_ncurses_tgetent=yes +else + ac_cv_lib_ncurses_tgetent=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ncurses_tgetent" >&5 +$as_echo "$ac_cv_lib_ncurses_tgetent" >&6; } +if test "x$ac_cv_lib_ncurses_tgetent" = x""yes; then : + bash_cv_termcap_lib=libncurses +else + bash_cv_termcap_lib=gnutermcap +fi + +fi + +fi + +fi + +fi + +fi + +if test "X$_bash_needmsg" = "Xyes"; then +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking which library has the termcap functions" >&5 +$as_echo_n "checking which library has the termcap functions... " >&6; } +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: using $bash_cv_termcap_lib" >&5 +$as_echo "using $bash_cv_termcap_lib" >&6; } +if test $bash_cv_termcap_lib = gnutermcap && test -z "$prefer_curses"; then +LDFLAGS="$LDFLAGS -L./lib/termcap" +TERMCAP_LIB="./lib/termcap/libtermcap.a" +TERMCAP_DEP="./lib/termcap/libtermcap.a" +elif test $bash_cv_termcap_lib = libtermcap && test -z "$prefer_curses"; then +TERMCAP_LIB=-ltermcap +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libtinfo; then +TERMCAP_LIB=-ltinfo +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libncurses; then +TERMCAP_LIB=-lncurses +TERMCAP_DEP= +elif test $bash_cv_termcap_lib = libc; then +TERMCAP_LIB= +TERMCAP_DEP= +else +TERMCAP_LIB=-lcurses +TERMCAP_DEP= +fi + +if test "$TERMCAP_LIB" = "./lib/termcap/libtermcap.a"; then + if test "$prefer_curses" = yes; then + TERMCAP_LIB=-lcurses + else + TERMCAP_LIB=-ltermcap #default + fi +fi + + +for ac_header in wctype.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "wctype.h" "ac_cv_header_wctype_h" "$ac_includes_default" +if test "x$ac_cv_header_wctype_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_WCTYPE_H 1 +_ACEOF + +fi + +done + +for ac_header in wchar.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "wchar.h" "ac_cv_header_wchar_h" "$ac_includes_default" +if test "x$ac_cv_header_wchar_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_WCHAR_H 1 +_ACEOF + +fi + +done + +for ac_header in langinfo.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "langinfo.h" "ac_cv_header_langinfo_h" "$ac_includes_default" +if test "x$ac_cv_header_langinfo_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LANGINFO_H 1 +_ACEOF + +fi + +done + + +ac_fn_c_check_func "$LINENO" "mbsrtowcs" "ac_cv_func_mbsrtowcs" +if test "x$ac_cv_func_mbsrtowcs" = x""yes; then : + $as_echo "#define HAVE_MBSRTOWCS 1" >>confdefs.h + +fi + +ac_fn_c_check_func "$LINENO" "mbrtowc" "ac_cv_func_mbrtowc" +if test "x$ac_cv_func_mbrtowc" = x""yes; then : + $as_echo "#define HAVE_MBRTOWC 1" >>confdefs.h + +fi + +ac_fn_c_check_func "$LINENO" "mbrlen" "ac_cv_func_mbrlen" +if test "x$ac_cv_func_mbrlen" = x""yes; then : + $as_echo "#define HAVE_MBRLEN 1" >>confdefs.h + +fi + +ac_fn_c_check_func "$LINENO" "wctomb" "ac_cv_func_wctomb" +if test "x$ac_cv_func_wctomb" = x""yes; then : + $as_echo "#define HAVE_WCTOMB 1" >>confdefs.h + +fi + +ac_fn_c_check_func "$LINENO" "wcwidth" "ac_cv_func_wcwidth" +if test "x$ac_cv_func_wcwidth" = x""yes; then : + $as_echo "#define HAVE_WCWIDTH 1" >>confdefs.h + +fi + +ac_fn_c_check_func "$LINENO" "wcsdup" "ac_cv_func_wcsdup" +if test "x$ac_cv_func_wcsdup" = x""yes; then : + $as_echo "#define HAVE_WCSDUP 1" >>confdefs.h + +fi + + +if test "$ac_cv_func_wcwidth" = no && test "$ac_cv_header_wchar_h" = yes; then + WCWIDTH_OBJ=wcwidth.o +else + WCWIDTH_OBJ= +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for mbstate_t" >&5 +$as_echo_n "checking for mbstate_t... " >&6; } +if test "${bash_cv_have_mbstate_t+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +int +main () +{ + + mbstate_t ps; + mbstate_t *psp; + psp = (mbstate_t *)0; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + bash_cv_have_mbstate_t=yes +else + bash_cv_have_mbstate_t=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_have_mbstate_t" >&5 +$as_echo "$bash_cv_have_mbstate_t" >&6; } +if test $bash_cv_have_mbstate_t = yes; then + $as_echo "#define HAVE_MBSTATE_T 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for nl_langinfo and CODESET" >&5 +$as_echo_n "checking for nl_langinfo and CODESET... " >&6; } +if test "${bash_cv_langinfo_codeset+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +char* cs = nl_langinfo(CODESET); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + bash_cv_langinfo_codeset=yes +else + bash_cv_langinfo_codeset=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $bash_cv_langinfo_codeset" >&5 +$as_echo "$bash_cv_langinfo_codeset" >&6; } +if test $bash_cv_langinfo_codeset = yes; then + $as_echo "#define HAVE_LANGINFO_CODESET 1" >>confdefs.h + +fi + + + +case "$host_cpu" in +*cray*) LOCAL_CFLAGS=-DCRAY ;; +*s390*) LOCAL_CFLAGS=-fsigned-char ;; +esac + +case "$host_os" in +isc*) LOCAL_CFLAGS=-Disc386 ;; +esac + +# shared library configuration section +# +# Shared object configuration section. These values are generated by +# ${srcdir}/support/shobj-conf +# +if test -f ${srcdir}/support/shobj-conf; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking configuration for building shared libraries" >&5 +$as_echo_n "checking configuration for building shared libraries... " >&6; } + eval `TERMCAP_LIB=$TERMCAP_LIB ${CONFIG_SHELL-/bin/sh} ${srcdir}/support/shobj-conf -C "${CC}" -c ${host_cpu} -o ${host_os} -v ${host_vendor}` + +# case "$SHLIB_LIBS" in +# *curses*|*termcap*|*termlib*) ;; +# *) SHLIB_LIBS="$SHLIB_LIBS $TERMCAP_LIB" ;; +# esac + + + + + + + + + + + + + + + + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $SHLIB_STATUS" >&5 +$as_echo "$SHLIB_STATUS" >&6; } + + # SHLIB_STATUS is either `supported' or `unsupported'. If it's + # `unsupported', turn off any default shared library building + if test "$SHLIB_STATUS" = 'unsupported'; then + opt_shared_libs=no + fi + + # shared library versioning + # quoted for m4 so I can use character classes + SHLIB_MAJOR=`expr "$LIBVERSION" : '\([0-9]\)\..*'` + SHLIB_MINOR=`expr "$LIBVERSION" : '[0-9]\.\([0-9]\).*'` + + +fi + +if test "$opt_static_libs" = "yes"; then + STATIC_TARGET=static + STATIC_INSTALL_TARGET=install-static +fi +if test "$opt_shared_libs" = "yes"; then + SHARED_TARGET=shared + SHARED_INSTALL_TARGET=install-shared +fi + + + + + + +case "$host_os" in +msdosdjgpp*) BUILD_DIR=`pwd.exe` ;; # to prevent //d/path/file +*) BUILD_DIR=`pwd` ;; +esac + +case "$BUILD_DIR" in +*\ *) BUILD_DIR=`echo "$BUILD_DIR" | sed 's: :\\\\ :g'` ;; +*) ;; +esac + + + + + + + + + + + + + + + + + + + +ac_config_files="$ac_config_files Makefile doc/Makefile examples/Makefile shlib/Makefile" + +ac_config_commands="$ac_config_commands default" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by readline $as_me 5.1-release, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration commands: +$config_commands + +Report bugs to ." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +readline config.status 5.1-release +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "doc/Makefile") CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;; + "examples/Makefile") CONFIG_FILES="$CONFIG_FILES examples/Makefile" ;; + "shlib/Makefile") CONFIG_FILES="$CONFIG_FILES shlib/Makefile" ;; + "default") CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). 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So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/external/gpl3/gdb/dist/readline/configure.in b/external/gpl3/gdb/dist/readline/configure.in new file mode 100644 index 000000000000..528aef50dd16 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/configure.in @@ -0,0 +1,338 @@ +dnl +dnl Configure script for readline library +dnl +dnl report bugs to chet@po.cwru.edu +dnl +dnl Process this file with autoconf to produce a configure script. + +# Copyright (C) 1987-2005 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA. + +AC_REVISION([for Readline 5.1, version 2.59]) + +m4_include([../config/override.m4]) + +AC_INIT(readline, 5.1-release, bug-readline@gnu.org) + +dnl make sure we are using a recent autoconf version +AC_PREREQ(2.50) + +AC_CONFIG_SRCDIR(readline.h) +dnl GDB LOCAL +dnl AC_CONFIG_AUX_DIR(./support) +AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/..) +AC_CONFIG_HEADERS(config.h) + +dnl update the value of RL_READLINE_VERSION in readline.h when this changes +LIBVERSION=5.1 + +AC_CANONICAL_HOST + +dnl configure defaults +opt_curses=no +opt_purify=no + +dnl arguments to configure +AC_ARG_WITH(curses, AC_HELP_STRING([--with-curses], [use the curses library instead of the termcap library]), opt_curses=$withval) +AC_ARG_WITH(purify, AC_HELP_STRING([--with-purify], [configure to postprocess with purify]), opt_purify=$withval) + +if test "$opt_curses" = "yes"; then + prefer_curses=yes +fi + +if test "$opt_purify" = yes; then + PURIFY="purify" +else + PURIFY= +fi + +dnl option parsing for optional features +opt_multibyte=yes +opt_static_libs=yes +opt_shared_libs=no + +AC_ARG_ENABLE(multibyte, AC_HELP_STRING([--enable-multibyte], [enable multibyte characters if OS supports them]), opt_multibyte=$enableval) +dnl AC_ARG_ENABLE(shared, AC_HELP_STRING([--enable-shared], [build shared libraries [[default=YES]]]), opt_shared_libs=$enableval) +AC_ARG_ENABLE(static, AC_HELP_STRING([--enable-static], [build static libraries [[default=YES]]]), opt_static_libs=$enableval) + +if test $opt_multibyte = no; then +AC_DEFINE(NO_MULTIBYTE_SUPPORT) +fi + +dnl load up the cross-building cache file -- add more cases and cache +dnl files as necessary + +dnl Note that host and target machine are the same, and different than the +dnl build machine. + +CROSS_COMPILE= +if test "x$cross_compiling" = "xyes"; then + case "${host}" in + *-cygwin*) + cross_cache=${srcdir}/cross-build/cygwin.cache + ;; + *-mingw*) + cross_cache=${srcdir}/cross-build/mingw.cache + ;; + i[[3456]]86-*-beos*) + cross_cache=${srcdir}/cross-build/x86-beos.cache + ;; + *) echo "configure: cross-compiling for $host is not supported" >&2 + ;; + esac + if test -n "${cross_cache}" && test -r "${cross_cache}"; then + echo "loading cross-build cache file ${cross_cache}" + . ${cross_cache} + fi + unset cross_cache + CROSS_COMPILE='-DCROSS_COMPILING' + AC_SUBST(CROSS_COMPILE) +fi + +echo "" +echo "Beginning configuration for readline-$LIBVERSION for ${host_cpu}-${host_vendor}-${host_os}" +echo "" + +# We want these before the checks, so the checks can modify their values. +test -z "$CFLAGS" && CFLAGS=-g auto_cflags=1 + +AC_PROG_MAKE_SET +AC_PROG_CC +dnl AC_AIX +AC_MINIX + +dnl BEGIN changes for CYGNUS cross-building for Cygwin +dnl NOTE: Some of these changes may no longer be necessary. + +dnl load up the cross-building cache file -- add more cases and cache +dnl files as necessary +if test "x$cross_compiling" = "xyes"; then + case "${host}" in + *-cygwin*) + cross_cache=${srcdir}/cross-build/cygwin.cache + LOCAL_CFLAGS="$LOCAL_CFLAGS -I${srcdir}/../libtermcap" + ;; + *-mingw32*) + cross_cache=${srcdir}/cross-build/mingw.cache + ;; + *) echo "configure: cross-compiling for a non-cygwin target is not supported" >&2 + ;; + esac + + if test "x$cross_cache" != "x"; then + if test -r "${cross_cache}"; then + echo "loading cross-build cache file ${cross_cache}" + . ${cross_cache} + fi + unset cross_cache + fi +fi + +if test -z "$CC_FOR_BUILD"; then + if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' + else + CC_FOR_BUILD=gcc + fi +fi +AC_SUBST(CC_FOR_BUILD) + +dnl END changes for CYGNUS cross-building for Cygwin + +# If we're using gcc and the user hasn't specified CFLAGS, add -O to CFLAGS. +test -n "$GCC" && test -n "$auto_cflags" && CFLAGS="$CFLAGS -O" + +AC_PROG_GCC_TRADITIONAL +AC_PROG_INSTALL +AC_CHECK_PROG(AR, ar, , ar) +dnl Set default for ARFLAGS, since autoconf does not have a macro for it. +dnl This allows people to set it when running configure or make +test -n "$ARFLAGS" || ARFLAGS="cr" +AC_PROG_RANLIB + +MAKE_SHELL=/bin/sh +AC_SUBST(MAKE_SHELL) + +AC_C_CONST +AC_C_PROTOTYPES +AC_C_CHAR_UNSIGNED + +AC_TYPE_SIGNAL + +AC_TYPE_SIZE_T +AC_CHECK_TYPE(ssize_t, int) + +AC_HEADER_STDC + +AC_HEADER_STAT +AC_HEADER_DIRENT + +AC_CHECK_FUNCS(fcntl kill lstat) +AC_CHECK_FUNCS(memmove putenv select setenv setlocale \ + strcasecmp strpbrk tcgetattr vsnprintf) +AC_CHECK_FUNCS(isascii isxdigit) +AC_CHECK_FUNCS(getpwent getpwnam getpwuid) + +AC_FUNC_STRCOLL + +AC_CHECK_HEADERS(fcntl.h unistd.h stdlib.h varargs.h stdarg.h string.h strings.h \ + limits.h locale.h pwd.h memory.h termcap.h termios.h termio.h) +AC_CHECK_HEADERS(sys/pte.h sys/stream.h sys/select.h sys/file.h) + +AC_CHECK_HEADERS(sys/ptem.h,,, +[[ +#if HAVE_SYS_STREAM_H +# include +#endif +]]) + +BASH_SYS_SIGNAL_VINTAGE +BASH_SYS_REINSTALL_SIGHANDLERS + +BASH_FUNC_POSIX_SETJMP +BASH_FUNC_LSTAT +BASH_FUNC_STRCOLL +BASH_FUNC_CTYPE_NONASCII + +BASH_CHECK_GETPW_FUNCS + +AC_HEADER_TIOCGWINSZ + +BASH_TYPE_SIGHANDLER +BASH_HAVE_TIOCSTAT +BASH_HAVE_FIONREAD +BASH_CHECK_SPEED_T +BASH_STRUCT_WINSIZE +BASH_STRUCT_DIRENT_D_INO +BASH_STRUCT_DIRENT_D_FILENO + +dnl yuck +case "$host_os" in +aix*) prefer_curses=yes ;; +esac +BASH_CHECK_LIB_TERMCAP +if test "$TERMCAP_LIB" = "./lib/termcap/libtermcap.a"; then + if test "$prefer_curses" = yes; then + TERMCAP_LIB=-lcurses + else + TERMCAP_LIB=-ltermcap #default + fi +fi + +BASH_CHECK_MULTIBYTE + +case "$host_cpu" in +*cray*) LOCAL_CFLAGS=-DCRAY ;; +*s390*) LOCAL_CFLAGS=-fsigned-char ;; +esac + +case "$host_os" in +isc*) LOCAL_CFLAGS=-Disc386 ;; +esac + +# shared library configuration section +# +# Shared object configuration section. These values are generated by +# ${srcdir}/support/shobj-conf +# +if test -f ${srcdir}/support/shobj-conf; then + AC_MSG_CHECKING(configuration for building shared libraries) + eval `TERMCAP_LIB=$TERMCAP_LIB ${CONFIG_SHELL-/bin/sh} ${srcdir}/support/shobj-conf -C "${CC}" -c ${host_cpu} -o ${host_os} -v ${host_vendor}` + +# case "$SHLIB_LIBS" in +# *curses*|*termcap*|*termlib*) ;; +# *) SHLIB_LIBS="$SHLIB_LIBS $TERMCAP_LIB" ;; +# esac + + AC_SUBST(SHOBJ_CC) + AC_SUBST(SHOBJ_CFLAGS) + AC_SUBST(SHOBJ_LD) + AC_SUBST(SHOBJ_LDFLAGS) + AC_SUBST(SHOBJ_XLDFLAGS) + AC_SUBST(SHOBJ_LIBS) + AC_SUBST(SHOBJ_STATUS) + AC_SUBST(SHLIB_STATUS) + AC_SUBST(SHLIB_XLDFLAGS) + AC_SUBST(SHLIB_DOT) + AC_SUBST(SHLIB_LIBPREF) + AC_SUBST(SHLIB_LIBSUFF) + AC_SUBST(SHLIB_LIBVERSION) + AC_SUBST(SHLIB_DLLVERSION) + AC_SUBST(SHLIB_LIBS) + AC_MSG_RESULT($SHLIB_STATUS) + + # SHLIB_STATUS is either `supported' or `unsupported'. If it's + # `unsupported', turn off any default shared library building + if test "$SHLIB_STATUS" = 'unsupported'; then + opt_shared_libs=no + fi + + # shared library versioning + # quoted for m4 so I can use character classes + SHLIB_MAJOR=[`expr "$LIBVERSION" : '\([0-9]\)\..*'`] + SHLIB_MINOR=[`expr "$LIBVERSION" : '[0-9]\.\([0-9]\).*'`] + AC_SUBST(SHLIB_MAJOR) + AC_SUBST(SHLIB_MINOR) +fi + +if test "$opt_static_libs" = "yes"; then + STATIC_TARGET=static + STATIC_INSTALL_TARGET=install-static +fi +if test "$opt_shared_libs" = "yes"; then + SHARED_TARGET=shared + SHARED_INSTALL_TARGET=install-shared +fi + +AC_SUBST(STATIC_TARGET) +AC_SUBST(SHARED_TARGET) +AC_SUBST(STATIC_INSTALL_TARGET) +AC_SUBST(SHARED_INSTALL_TARGET) + +case "$host_os" in +msdosdjgpp*) BUILD_DIR=`pwd.exe` ;; # to prevent //d/path/file +*) BUILD_DIR=`pwd` ;; +esac + +case "$BUILD_DIR" in +*\ *) BUILD_DIR=`echo "$BUILD_DIR" | sed 's: :\\\\ :g'` ;; +*) ;; +esac + +AC_SUBST(PURIFY) +AC_SUBST(BUILD_DIR) + +AC_SUBST(CFLAGS) +AC_SUBST(LOCAL_CFLAGS) +AC_SUBST(LOCAL_LDFLAGS) +AC_SUBST(LOCAL_DEFS) + +AC_SUBST(AR) +AC_SUBST(ARFLAGS) + +AC_SUBST(host_cpu) +AC_SUBST(host_os) + +AC_SUBST(LIBVERSION) + +AC_SUBST(TERMCAP_LIB) + +AC_OUTPUT([Makefile doc/Makefile examples/Makefile shlib/Makefile], +[ +# Makefile uses this timestamp file to record whether config.h is up to date. +echo > stamp-h +]) diff --git a/external/gpl3/gdb/dist/readline/cross-build/cygwin.cache b/external/gpl3/gdb/dist/readline/cross-build/cygwin.cache new file mode 100644 index 000000000000..b0bb49a83760 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/cross-build/cygwin.cache @@ -0,0 +1,46 @@ +# This file is a shell script that caches the results of configure +# tests for CYGWIN32 so they don't need to be done when cross-compiling. + +# AC_FUNC_GETPGRP should also define GETPGRP_VOID +ac_cv_func_getpgrp_void=${ac_cv_func_getpgrp_void='yes'} +# AC_FUNC_SETVBUF_REVERSED should not define anything else +ac_cv_func_setvbuf_reversed=${ac_cv_func_setvbuf_reversed='no'} +# on CYGWIN32, system calls do not restart +ac_cv_sys_restartable_syscalls=${ac_cv_sys_restartable_syscalls='no'} +bash_cv_sys_restartable_syscalls=${bash_cv_sys_restartable_syscalls='no'} + +# these may be necessary, but they are currently commented out +#ac_cv_c_bigendian=${ac_cv_c_bigendian='no'} +ac_cv_sizeof_char_p=${ac_cv_sizeof_char_p='4'} +ac_cv_sizeof_int=${ac_cv_sizeof_int='4'} +ac_cv_sizeof_long=${ac_cv_sizeof_long='4'} + +bash_cv_dup2_broken=${bash_cv_dup2_broken='no'} +bash_cv_pgrp_pipe=${bash_cv_pgrp_pipe='no'} +bash_cv_type_rlimit=${bash_cv_type_rlimit='long'} +bash_cv_decl_under_sys_siglist=${bash_cv_decl_under_sys_siglist='no'} +bash_cv_under_sys_siglist=${bash_cv_under_sys_siglist='no'} +bash_cv_sys_siglist=${bash_cv_sys_siglist='no'} +bash_cv_opendir_not_robust=${bash_cv_opendir_not_robust='no'} +bash_cv_getenv_redef=${bash_cv_getenv_redef='yes'} +bash_cv_printf_declared=${bash_cv_printf_declared='yes'} +bash_cv_ulimit_maxfds=${bash_cv_ulimit_maxfds='no'} +bash_cv_getcwd_calls_popen=${bash_cv_getcwd_calls_popen='no'} +bash_cv_must_reinstall_sighandlers=${bash_cv_must_reinstall_sighandlers='no'} +bash_cv_job_control_missing=${bash_cv_job_control_missing='present'} +bash_cv_sys_named_pipes=${bash_cv_sys_named_pipes='missing'} +bash_cv_func_sigsetjmp=${bash_cv_func_sigsetjmp='present'} +bash_cv_mail_dir=${bash_cv_mail_dir='unknown'} +bash_cv_func_strcoll_broken=${bash_cv_func_strcoll_broken='no'} +bash_cv_have_mbstate_t=${bash_cv_have_mbstate_t='yes'} + +bash_cv_type_int32_t=${bash_cv_type_int32_t='int'} +bash_cv_type_u_int32_t=${bash_cv_type_u_int32_t='int'} +ac_cv_header_termcap_h=${ac_cv_header_termcap_h='yes'} +ac_cv_header_termios_h=${ac_cv_header_termios_h='yes'} +bash_cv_termcap_lib=${bash_cv_termcap_lib='-ltermcap'} + +bash_cv_tiocgwinsz_in_ioctl=${bash_cv_tiocgwinsz_in_ioctl='yes'} +ac_cv_lib_termcap_tgetent=${ac_cv_lib_termcap_tgetent='yes'} + +# end of cross-build/cygwin32.cache diff --git a/external/gpl3/gdb/dist/readline/display.c b/external/gpl3/gdb/dist/readline/display.c new file mode 100644 index 000000000000..575b0ad0ea86 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/display.c @@ -0,0 +1,2408 @@ +/* display.c -- readline redisplay facility. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#include "posixstat.h" + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +#ifdef __MSDOS__ +# include +#endif + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +/* Termcap library stuff. */ +#include "tcap.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +#if !defined (strchr) && !defined (__STDC__) +extern char *strchr (), *strrchr (); +#endif /* !strchr && !__STDC__ */ + +#if defined (HACK_TERMCAP_MOTION) +extern char *_rl_term_forward_char; +#endif + +static void update_line PARAMS((char *, char *, int, int, int, int)); +static void space_to_eol PARAMS((int)); +static void delete_chars PARAMS((int)); +static void insert_some_chars PARAMS((char *, int, int)); +static void cr PARAMS((void)); + +#if defined (HANDLE_MULTIBYTE) +static int _rl_col_width PARAMS((const char *, int, int)); +static int *_rl_wrapped_line; +#else +# define _rl_col_width(l, s, e) (((e) <= (s)) ? 0 : (e) - (s)) +#endif + +static int *inv_lbreaks, *vis_lbreaks; +static int inv_lbsize, vis_lbsize; + +/* Heuristic used to decide whether it is faster to move from CUR to NEW + by backing up or outputting a carriage return and moving forward. */ +#define CR_FASTER(new, cur) (((new) + 1) < ((cur) - (new))) + +/* **************************************************************** */ +/* */ +/* Display stuff */ +/* */ +/* **************************************************************** */ + +/* This is the stuff that is hard for me. I never seem to write good + display routines in C. Let's see how I do this time. */ + +/* (PWP) Well... Good for a simple line updater, but totally ignores + the problems of input lines longer than the screen width. + + update_line and the code that calls it makes a multiple line, + automatically wrapping line update. Careful attention needs + to be paid to the vertical position variables. */ + +/* Keep two buffers; one which reflects the current contents of the + screen, and the other to draw what we think the new contents should + be. Then compare the buffers, and make whatever changes to the + screen itself that we should. Finally, make the buffer that we + just drew into be the one which reflects the current contents of the + screen, and place the cursor where it belongs. + + Commands that want to can fix the display themselves, and then let + this function know that the display has been fixed by setting the + RL_DISPLAY_FIXED variable. This is good for efficiency. */ + +/* Application-specific redisplay function. */ +rl_voidfunc_t *rl_redisplay_function = rl_redisplay; + +/* Global variables declared here. */ +/* What YOU turn on when you have handled all redisplay yourself. */ +int rl_display_fixed = 0; + +int _rl_suppress_redisplay = 0; +int _rl_want_redisplay = 0; + +/* The stuff that gets printed out before the actual text of the line. + This is usually pointing to rl_prompt. */ +char *rl_display_prompt = (char *)NULL; + +/* Pseudo-global variables declared here. */ + +/* The visible cursor position. If you print some text, adjust this. */ +/* NOTE: _rl_last_c_pos is used as a buffer index when not in a locale + supporting multibyte characters, and an absolute cursor position when + in such a locale. This is an artifact of the donated multibyte support. + Care must be taken when modifying its value. */ +int _rl_last_c_pos = 0; +int _rl_last_v_pos = 0; + +static int cpos_adjusted; + +/* Number of lines currently on screen minus 1. */ +int _rl_vis_botlin = 0; + +/* Variables used only in this file. */ +/* The last left edge of text that was displayed. This is used when + doing horizontal scrolling. It shifts in thirds of a screenwidth. */ +static int last_lmargin; + +/* The line display buffers. One is the line currently displayed on + the screen. The other is the line about to be displayed. */ +static char *visible_line = (char *)NULL; +static char *invisible_line = (char *)NULL; + +/* A buffer for `modeline' messages. */ +static char msg_buf[128]; + +/* Non-zero forces the redisplay even if we thought it was unnecessary. */ +static int forced_display; + +/* Default and initial buffer size. Can grow. */ +static int line_size = 1024; + +/* Variables to keep track of the expanded prompt string, which may + include invisible characters. */ + +static char *local_prompt, *local_prompt_prefix; +static int prompt_visible_length, prompt_prefix_length; + +/* The number of invisible characters in the line currently being + displayed on the screen. */ +static int visible_wrap_offset; + +/* The number of invisible characters in the prompt string. Static so it + can be shared between rl_redisplay and update_line */ +static int wrap_offset; + +/* The index of the last invisible character in the prompt string. */ +static int prompt_last_invisible; + +/* The length (buffer offset) of the first line of the last (possibly + multi-line) buffer displayed on the screen. */ +static int visible_first_line_len; + +/* Number of invisible characters on the first physical line of the prompt. + Only valid when the number of physical characters in the prompt exceeds + (or is equal to) _rl_screenwidth. */ +static int prompt_invis_chars_first_line; + +static int prompt_last_screen_line; + +static int prompt_physical_chars; + +/* Variables to save and restore prompt and display information. */ + +/* These are getting numerous enough that it's time to create a struct. */ + +static char *saved_local_prompt; +static char *saved_local_prefix; +static int saved_last_invisible; +static int saved_visible_length; +static int saved_prefix_length; +static int saved_invis_chars_first_line; +static int saved_physical_chars; + +/* Expand the prompt string S and return the number of visible + characters in *LP, if LP is not null. This is currently more-or-less + a placeholder for expansion. LIP, if non-null is a place to store the + index of the last invisible character in the returned string. NIFLP, + if non-zero, is a place to store the number of invisible characters in + the first prompt line. The previous are used as byte counts -- indexes + into a character buffer. */ + +/* Current implementation: + \001 (^A) start non-visible characters + \002 (^B) end non-visible characters + all characters except \001 and \002 (following a \001) are copied to + the returned string; all characters except those between \001 and + \002 are assumed to be `visible'. */ + +static char * +expand_prompt (pmt, lp, lip, niflp, vlp) + char *pmt; + int *lp, *lip, *niflp, *vlp; +{ + char *r, *ret, *p; + int l, rl, last, ignoring, ninvis, invfl, invflset, ind, pind, physchars; + + /* Short-circuit if we can. */ + if ((MB_CUR_MAX <= 1 || rl_byte_oriented) && strchr (pmt, RL_PROMPT_START_IGNORE) == 0) + { + r = savestring (pmt); + if (lp) + *lp = strlen (r); + if (lip) + *lip = 0; + if (niflp) + *niflp = 0; + if (vlp) + *vlp = lp ? *lp : strlen (r); + return r; + } + + l = strlen (pmt); + r = ret = (char *)xmalloc (l + 1); + + invfl = 0; /* invisible chars in first line of prompt */ + invflset = 0; /* we only want to set invfl once */ + + for (rl = ignoring = last = ninvis = physchars = 0, p = pmt; p && *p; p++) + { + /* This code strips the invisible character string markers + RL_PROMPT_START_IGNORE and RL_PROMPT_END_IGNORE */ + if (*p == RL_PROMPT_START_IGNORE) + { + ignoring++; + continue; + } + else if (ignoring && *p == RL_PROMPT_END_IGNORE) + { + ignoring = 0; + if (p[-1] != RL_PROMPT_START_IGNORE) + last = r - ret - 1; + continue; + } + else + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + pind = p - pmt; + ind = _rl_find_next_mbchar (pmt, pind, 1, MB_FIND_NONZERO); + l = ind - pind; + while (l--) + *r++ = *p++; + if (!ignoring) + { + rl += ind - pind; + physchars += _rl_col_width (pmt, pind, ind); + } + else + ninvis += ind - pind; + p--; /* compensate for later increment */ + } + else +#endif + { + *r++ = *p; + if (!ignoring) + { + rl++; /* visible length byte counter */ + physchars++; + } + else + ninvis++; /* invisible chars byte counter */ + } + + if (invflset == 0 && rl >= _rl_screenwidth) + { + invfl = ninvis; + invflset = 1; + } + } + } + + if (rl < _rl_screenwidth) + invfl = ninvis; + + *r = '\0'; + if (lp) + *lp = rl; + if (lip) + *lip = last; + if (niflp) + *niflp = invfl; + if (vlp) + *vlp = physchars; + return ret; +} + +/* Just strip out RL_PROMPT_START_IGNORE and RL_PROMPT_END_IGNORE from + PMT and return the rest of PMT. */ +char * +_rl_strip_prompt (pmt) + char *pmt; +{ + char *ret; + + ret = expand_prompt (pmt, (int *)NULL, (int *)NULL, (int *)NULL, (int *)NULL); + return ret; +} + +/* + * Expand the prompt string into the various display components, if + * necessary. + * + * local_prompt = expanded last line of string in rl_display_prompt + * (portion after the final newline) + * local_prompt_prefix = portion before last newline of rl_display_prompt, + * expanded via expand_prompt + * prompt_visible_length = number of visible characters in local_prompt + * prompt_prefix_length = number of visible characters in local_prompt_prefix + * + * This function is called once per call to readline(). It may also be + * called arbitrarily to expand the primary prompt. + * + * The return value is the number of visible characters on the last line + * of the (possibly multi-line) prompt. + */ +int +rl_expand_prompt (prompt) + char *prompt; +{ + char *p, *t; + int c; + + /* Clear out any saved values. */ + FREE (local_prompt); + FREE (local_prompt_prefix); + + local_prompt = local_prompt_prefix = (char *)0; + prompt_last_invisible = prompt_invis_chars_first_line = 0; + prompt_visible_length = prompt_physical_chars = 0; + + if (prompt == 0 || *prompt == 0) + return (0); + + p = strrchr (prompt, '\n'); + if (!p) + { + /* The prompt is only one logical line, though it might wrap. */ + local_prompt = expand_prompt (prompt, &prompt_visible_length, + &prompt_last_invisible, + &prompt_invis_chars_first_line, + &prompt_physical_chars); + local_prompt_prefix = (char *)0; + return (prompt_visible_length); + } + else + { + /* The prompt spans multiple lines. */ + t = ++p; + local_prompt = expand_prompt (p, &prompt_visible_length, + &prompt_last_invisible, + (int *)NULL, + &prompt_physical_chars); + c = *t; *t = '\0'; + /* The portion of the prompt string up to and including the + final newline is now null-terminated. */ + local_prompt_prefix = expand_prompt (prompt, &prompt_prefix_length, + (int *)NULL, + &prompt_invis_chars_first_line, + (int *)NULL); + *t = c; + return (prompt_prefix_length); + } +} + +/* Initialize the VISIBLE_LINE and INVISIBLE_LINE arrays, and their associated + arrays of line break markers. MINSIZE is the minimum size of VISIBLE_LINE + and INVISIBLE_LINE; if it is greater than LINE_SIZE, LINE_SIZE is + increased. If the lines have already been allocated, this ensures that + they can hold at least MINSIZE characters. */ +static void +init_line_structures (minsize) + int minsize; +{ + register int n; + + if (invisible_line == 0) /* initialize it */ + { + if (line_size < minsize) + line_size = minsize; + visible_line = (char *)xmalloc (line_size); + invisible_line = (char *)xmalloc (line_size); + } + else if (line_size < minsize) /* ensure it can hold MINSIZE chars */ + { + line_size *= 2; + if (line_size < minsize) + line_size = minsize; + visible_line = (char *)xrealloc (visible_line, line_size); + invisible_line = (char *)xrealloc (invisible_line, line_size); + } + + for (n = minsize; n < line_size; n++) + { + visible_line[n] = 0; + invisible_line[n] = 1; + } + + if (vis_lbreaks == 0) + { + /* should be enough. */ + inv_lbsize = vis_lbsize = 256; + inv_lbreaks = (int *)xmalloc (inv_lbsize * sizeof (int)); + vis_lbreaks = (int *)xmalloc (vis_lbsize * sizeof (int)); +#if defined (HANDLE_MULTIBYTE) + _rl_wrapped_line = (int *)xmalloc (vis_lbsize * sizeof (int)); +#endif + inv_lbreaks[0] = vis_lbreaks[0] = 0; + } +} + +/* Basic redisplay algorithm. */ +void +rl_redisplay () +{ + register int in, out, c, linenum, cursor_linenum; + register char *line; + int c_pos, inv_botlin, lb_botlin, lb_linenum, o_cpos; + int newlines, lpos, temp, modmark, n0, num; + char *prompt_this_line; +#if defined (HANDLE_MULTIBYTE) + wchar_t wc; + size_t wc_bytes; + int wc_width; + mbstate_t ps; + int _rl_wrapped_multicolumn = 0; +#endif + + if (!readline_echoing_p) + return; + + /* Signals are blocked through this function as the global data structures + could get corrupted upon modifications from an invoked signal handler. */ + _rl_block_sigint (); + + if (!rl_display_prompt) + rl_display_prompt = ""; + + if (invisible_line == 0 || vis_lbreaks == 0) + { + init_line_structures (0); + rl_on_new_line (); + } + + /* Draw the line into the buffer. */ + c_pos = -1; + + line = invisible_line; + out = inv_botlin = 0; + + /* Mark the line as modified or not. We only do this for history + lines. */ + modmark = 0; + if (_rl_mark_modified_lines && current_history () && rl_undo_list) + { + line[out++] = '*'; + line[out] = '\0'; + modmark = 1; + } + + /* If someone thought that the redisplay was handled, but the currently + visible line has a different modification state than the one about + to become visible, then correct the caller's misconception. */ + if (visible_line[0] != invisible_line[0]) + rl_display_fixed = 0; + + /* If the prompt to be displayed is the `primary' readline prompt (the + one passed to readline()), use the values we have already expanded. + If not, use what's already in rl_display_prompt. WRAP_OFFSET is the + number of non-visible characters in the prompt string. */ + if (rl_display_prompt == rl_prompt || local_prompt) + { + int local_len = local_prompt ? strlen (local_prompt) : 0; + if (local_prompt_prefix && forced_display) + _rl_output_some_chars (local_prompt_prefix, strlen (local_prompt_prefix)); + + if (local_len > 0) + { + temp = local_len + out + 2; + if (temp >= line_size) + { + line_size = (temp + 1024) - (temp % 1024); + visible_line = (char *)xrealloc (visible_line, line_size); + line = invisible_line = (char *)xrealloc (invisible_line, line_size); + } + strncpy (line + out, local_prompt, local_len); + out += local_len; + } + line[out] = '\0'; + wrap_offset = local_len - prompt_visible_length; + } + else + { + int pmtlen; + prompt_this_line = strrchr (rl_display_prompt, '\n'); + if (!prompt_this_line) + prompt_this_line = rl_display_prompt; + else + { + prompt_this_line++; + pmtlen = prompt_this_line - rl_display_prompt; /* temp var */ + if (forced_display) + { + _rl_output_some_chars (rl_display_prompt, pmtlen); + /* Make sure we are at column zero even after a newline, + regardless of the state of terminal output processing. */ + if (pmtlen < 2 || prompt_this_line[-2] != '\r') + cr (); + } + } + + prompt_physical_chars = pmtlen = strlen (prompt_this_line); + temp = pmtlen + out + 2; + if (temp >= line_size) + { + line_size = (temp + 1024) - (temp % 1024); + visible_line = (char *)xrealloc (visible_line, line_size); + line = invisible_line = (char *)xrealloc (invisible_line, line_size); + } + strncpy (line + out, prompt_this_line, pmtlen); + out += pmtlen; + line[out] = '\0'; + wrap_offset = prompt_invis_chars_first_line = 0; + } + +#define CHECK_INV_LBREAKS() \ + do { \ + if (newlines >= (inv_lbsize - 2)) \ + { \ + inv_lbsize *= 2; \ + inv_lbreaks = (int *)xrealloc (inv_lbreaks, inv_lbsize * sizeof (int)); \ + } \ + } while (0) + +#if defined (HANDLE_MULTIBYTE) +#define CHECK_LPOS() \ + do { \ + lpos++; \ + if (lpos >= _rl_screenwidth) \ + { \ + if (newlines >= (inv_lbsize - 2)) \ + { \ + inv_lbsize *= 2; \ + inv_lbreaks = (int *)xrealloc (inv_lbreaks, inv_lbsize * sizeof (int)); \ + _rl_wrapped_line = (int *)xrealloc (_rl_wrapped_line, inv_lbsize * sizeof (int)); \ + } \ + inv_lbreaks[++newlines] = out; \ + _rl_wrapped_line[newlines] = _rl_wrapped_multicolumn; \ + lpos = 0; \ + } \ + } while (0) +#else +#define CHECK_LPOS() \ + do { \ + lpos++; \ + if (lpos >= _rl_screenwidth) \ + { \ + if (newlines >= (inv_lbsize - 2)) \ + { \ + inv_lbsize *= 2; \ + inv_lbreaks = (int *)xrealloc (inv_lbreaks, inv_lbsize * sizeof (int)); \ + } \ + inv_lbreaks[++newlines] = out; \ + lpos = 0; \ + } \ + } while (0) +#endif + + /* inv_lbreaks[i] is where line i starts in the buffer. */ + inv_lbreaks[newlines = 0] = 0; +#if 0 + lpos = out - wrap_offset; +#else + lpos = prompt_physical_chars + modmark; +#endif + +#if defined (HANDLE_MULTIBYTE) + memset (_rl_wrapped_line, 0, vis_lbsize); + num = 0; +#endif + + /* prompt_invis_chars_first_line is the number of invisible characters in + the first physical line of the prompt. + wrap_offset - prompt_invis_chars_first_line is the number of invis + chars on the second line. */ + + /* what if lpos is already >= _rl_screenwidth before we start drawing the + contents of the command line? */ + while (lpos >= _rl_screenwidth) + { + /* fix from Darin Johnson for prompt string with + invisible characters that is longer than the screen width. The + prompt_invis_chars_first_line variable could be made into an array + saying how many invisible characters there are per line, but that's + probably too much work for the benefit gained. How many people have + prompts that exceed two physical lines? + Additional logic fix from Edward Catmur */ +#if defined (HANDLE_MULTIBYTE) + n0 = num; + temp = local_prompt ? strlen (local_prompt) : 0; + while (num < temp) + { + if (_rl_col_width (local_prompt, n0, num) > _rl_screenwidth) + { + num = _rl_find_prev_mbchar (local_prompt, num, MB_FIND_ANY); + break; + } + num++; + } + temp = num + +#else + temp = ((newlines + 1) * _rl_screenwidth) + +#endif /* !HANDLE_MULTIBYTE */ + ((local_prompt_prefix == 0) ? ((newlines == 0) ? prompt_invis_chars_first_line + : ((newlines == 1) ? wrap_offset : 0)) + : ((newlines == 0) ? wrap_offset :0)); + + inv_lbreaks[++newlines] = temp; +#if defined (HANDLE_MULTIBYTE) + lpos -= _rl_col_width (local_prompt, n0, num); +#else + lpos -= _rl_screenwidth; +#endif + } + + prompt_last_screen_line = newlines; + + /* Draw the rest of the line (after the prompt) into invisible_line, keeping + track of where the cursor is (c_pos), the number of the line containing + the cursor (lb_linenum), the last line number (lb_botlin and inv_botlin). + It maintains an array of line breaks for display (inv_lbreaks). + This handles expanding tabs for display and displaying meta characters. */ + lb_linenum = 0; +#if defined (HANDLE_MULTIBYTE) + in = 0; + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + memset (&ps, 0, sizeof (mbstate_t)); + wc_bytes = mbrtowc (&wc, rl_line_buffer, rl_end, &ps); + } + else + wc_bytes = 1; + while (in < rl_end) +#else + for (in = 0; in < rl_end; in++) +#endif + { + c = (unsigned char)rl_line_buffer[in]; + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + if (MB_INVALIDCH (wc_bytes)) + { + /* Byte sequence is invalid or shortened. Assume that the + first byte represents a character. */ + wc_bytes = 1; + /* Assume that a character occupies a single column. */ + wc_width = 1; + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (wc_bytes)) + break; /* Found '\0' */ + else + { + temp = wcwidth (wc); + wc_width = (temp >= 0) ? temp : 1; + } + } +#endif + + if (out + 8 >= line_size) /* XXX - 8 for \t */ + { + line_size *= 2; + visible_line = (char *)xrealloc (visible_line, line_size); + invisible_line = (char *)xrealloc (invisible_line, line_size); + line = invisible_line; + } + + if (in == rl_point) + { + c_pos = out; + lb_linenum = newlines; + } + +#if defined (HANDLE_MULTIBYTE) + if (META_CHAR (c) && _rl_output_meta_chars == 0) /* XXX - clean up */ +#else + if (META_CHAR (c)) +#endif + { + if (_rl_output_meta_chars == 0) + { + sprintf (line + out, "\\%o", c); + + if (lpos + 4 >= _rl_screenwidth) + { + temp = _rl_screenwidth - lpos; + CHECK_INV_LBREAKS (); + inv_lbreaks[++newlines] = out + temp; + lpos = 4 - temp; + } + else + lpos += 4; + + out += 4; + } + else + { + line[out++] = c; + CHECK_LPOS(); + } + } +#if defined (DISPLAY_TABS) + else if (c == '\t') + { + register int newout; + +#if 0 + newout = (out | (int)7) + 1; +#else + newout = out + 8 - lpos % 8; +#endif + temp = newout - out; + if (lpos + temp >= _rl_screenwidth) + { + register int temp2; + temp2 = _rl_screenwidth - lpos; + CHECK_INV_LBREAKS (); + inv_lbreaks[++newlines] = out + temp2; + lpos = temp - temp2; + while (out < newout) + line[out++] = ' '; + } + else + { + while (out < newout) + line[out++] = ' '; + lpos += temp; + } + } +#endif + else if (c == '\n' && _rl_horizontal_scroll_mode == 0 && _rl_term_up && *_rl_term_up) + { + line[out++] = '\0'; /* XXX - sentinel */ + CHECK_INV_LBREAKS (); + inv_lbreaks[++newlines] = out; + lpos = 0; + } + else if (CTRL_CHAR (c) || c == RUBOUT) + { + line[out++] = '^'; + CHECK_LPOS(); + line[out++] = CTRL_CHAR (c) ? UNCTRL (c) : '?'; + CHECK_LPOS(); + } + else + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + register int i; + + _rl_wrapped_multicolumn = 0; + + if (_rl_screenwidth < lpos + wc_width) + for (i = lpos; i < _rl_screenwidth; i++) + { + /* The space will be removed in update_line() */ + line[out++] = ' '; + _rl_wrapped_multicolumn++; + CHECK_LPOS(); + } + if (in == rl_point) + { + c_pos = out; + lb_linenum = newlines; + } + for (i = in; i < in+wc_bytes; i++) + line[out++] = rl_line_buffer[i]; + for (i = 0; i < wc_width; i++) + CHECK_LPOS(); + } + else + { + line[out++] = c; + CHECK_LPOS(); + } +#else + line[out++] = c; + CHECK_LPOS(); +#endif + } + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + in += wc_bytes; + wc_bytes = mbrtowc (&wc, rl_line_buffer + in, rl_end - in, &ps); + } + else + in++; +#endif + + } + line[out] = '\0'; + if (c_pos < 0) + { + c_pos = out; + lb_linenum = newlines; + } + + inv_botlin = lb_botlin = newlines; + CHECK_INV_LBREAKS (); + inv_lbreaks[newlines+1] = out; + cursor_linenum = lb_linenum; + + /* C_POS == position in buffer where cursor should be placed. + CURSOR_LINENUM == line number where the cursor should be placed. */ + + /* PWP: now is when things get a bit hairy. The visible and invisible + line buffers are really multiple lines, which would wrap every + (screenwidth - 1) characters. Go through each in turn, finding + the changed region and updating it. The line order is top to bottom. */ + + /* If we can move the cursor up and down, then use multiple lines, + otherwise, let long lines display in a single terminal line, and + horizontally scroll it. */ + + if (_rl_horizontal_scroll_mode == 0 && _rl_term_up && *_rl_term_up) + { + int nleft, pos, changed_screen_line, tx; + + if (!rl_display_fixed || forced_display) + { + forced_display = 0; + + /* If we have more than a screenful of material to display, then + only display a screenful. We should display the last screen, + not the first. */ + if (out >= _rl_screenchars) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + out = _rl_find_prev_mbchar (line, _rl_screenchars, MB_FIND_ANY); + else + out = _rl_screenchars - 1; + } + + /* The first line is at character position 0 in the buffer. The + second and subsequent lines start at inv_lbreaks[N], offset by + OFFSET (which has already been calculated above). */ + +#define W_OFFSET(line, offset) ((line) == 0 ? offset : 0) +#define VIS_LLEN(l) ((l) > _rl_vis_botlin ? 0 : (vis_lbreaks[l+1] - vis_lbreaks[l])) +#define INV_LLEN(l) (inv_lbreaks[l+1] - inv_lbreaks[l]) +#define VIS_CHARS(line) (visible_line + vis_lbreaks[line]) +#define VIS_LINE(line) ((line) > _rl_vis_botlin) ? "" : VIS_CHARS(line) +#define INV_LINE(line) (invisible_line + inv_lbreaks[line]) + + /* For each line in the buffer, do the updating display. */ + for (linenum = 0; linenum <= inv_botlin; linenum++) + { + o_cpos = _rl_last_c_pos; + cpos_adjusted = 0; + update_line (VIS_LINE(linenum), INV_LINE(linenum), linenum, + VIS_LLEN(linenum), INV_LLEN(linenum), inv_botlin); + + /* update_line potentially changes _rl_last_c_pos, but doesn't + take invisible characters into account, since _rl_last_c_pos + is an absolute cursor position in a multibyte locale. See + if compensating here is the right thing, or if we have to + change update_line itself. There is one case in which + update_line adjusts _rl_last_c_pos itself (so it can pass + _rl_move_cursor_relative accurate values); it communicates + this back by setting cpos_adjusted */ + if (linenum == 0 && (MB_CUR_MAX > 1 && rl_byte_oriented == 0) && + cpos_adjusted == 0 && + _rl_last_c_pos != o_cpos && + _rl_last_c_pos > wrap_offset && + o_cpos < prompt_last_invisible) + _rl_last_c_pos -= wrap_offset; + + /* If this is the line with the prompt, we might need to + compensate for invisible characters in the new line. Do + this only if there is not more than one new line (which + implies that we completely overwrite the old visible line) + and the new line is shorter than the old. Make sure we are + at the end of the new line before clearing. */ + if (linenum == 0 && + inv_botlin == 0 && _rl_last_c_pos == out && + (wrap_offset > visible_wrap_offset) && + (_rl_last_c_pos < visible_first_line_len)) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + nleft = _rl_screenwidth - _rl_last_c_pos; + else + nleft = _rl_screenwidth + wrap_offset - _rl_last_c_pos; + if (nleft) + _rl_clear_to_eol (nleft); + } + + /* Since the new first line is now visible, save its length. */ + if (linenum == 0) + visible_first_line_len = (inv_botlin > 0) ? inv_lbreaks[1] : out - wrap_offset; + } + + /* We may have deleted some lines. If so, clear the left over + blank ones at the bottom out. */ + if (_rl_vis_botlin > inv_botlin) + { + char *tt; + for (; linenum <= _rl_vis_botlin; linenum++) + { + tt = VIS_CHARS (linenum); + _rl_move_vert (linenum); + _rl_move_cursor_relative (0, tt); + _rl_clear_to_eol + ((linenum == _rl_vis_botlin) ? strlen (tt) : _rl_screenwidth); + } + } + _rl_vis_botlin = inv_botlin; + + /* CHANGED_SCREEN_LINE is set to 1 if we have moved to a + different screen line during this redisplay. */ + changed_screen_line = _rl_last_v_pos != cursor_linenum; + if (changed_screen_line) + { + _rl_move_vert (cursor_linenum); + /* If we moved up to the line with the prompt using _rl_term_up, + the physical cursor position on the screen stays the same, + but the buffer position needs to be adjusted to account + for invisible characters. */ + if ((MB_CUR_MAX == 1 || rl_byte_oriented) && cursor_linenum == 0 && wrap_offset) + _rl_last_c_pos += wrap_offset; + } + + /* We have to reprint the prompt if it contains invisible + characters, since it's not generally OK to just reprint + the characters from the current cursor position. But we + only need to reprint it if the cursor is before the last + invisible character in the prompt string. */ + nleft = prompt_visible_length + wrap_offset; + if (cursor_linenum == 0 && wrap_offset > 0 && _rl_last_c_pos > 0 && + _rl_last_c_pos <= prompt_last_invisible && local_prompt) + { +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + if (_rl_term_cr) + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif + _rl_output_some_chars (local_prompt, nleft); + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + _rl_last_c_pos = _rl_col_width (local_prompt, 0, nleft) - wrap_offset; + else + _rl_last_c_pos = nleft; + } + + /* Where on that line? And where does that line start + in the buffer? */ + pos = inv_lbreaks[cursor_linenum]; + /* nleft == number of characters in the line buffer between the + start of the line and the cursor position. */ + nleft = c_pos - pos; + + /* NLEFT is now a number of characters in a buffer. When in a + multibyte locale, however, _rl_last_c_pos is an absolute cursor + position that doesn't take invisible characters in the prompt + into account. We use a fudge factor to compensate. */ + + /* Since _rl_backspace() doesn't know about invisible characters in the + prompt, and there's no good way to tell it, we compensate for + those characters here and call _rl_backspace() directly. */ + if (wrap_offset && cursor_linenum == 0 && nleft < _rl_last_c_pos) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + tx = _rl_col_width (&visible_line[pos], 0, nleft) - visible_wrap_offset; + else + tx = nleft; + if (_rl_last_c_pos > tx) + { + _rl_backspace (_rl_last_c_pos - tx); /* XXX */ + _rl_last_c_pos = tx; + } + } + + /* We need to note that in a multibyte locale we are dealing with + _rl_last_c_pos as an absolute cursor position, but moving to a + point specified by a buffer position (NLEFT) that doesn't take + invisible characters into account. */ + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + _rl_move_cursor_relative (nleft, &invisible_line[pos]); + else if (nleft != _rl_last_c_pos) + _rl_move_cursor_relative (nleft, &invisible_line[pos]); + } + } + else /* Do horizontal scrolling. */ + { +#define M_OFFSET(margin, offset) ((margin) == 0 ? offset : 0) + int lmargin, ndisp, nleft, phys_c_pos, t; + + /* Always at top line. */ + _rl_last_v_pos = 0; + + /* Compute where in the buffer the displayed line should start. This + will be LMARGIN. */ + + /* The number of characters that will be displayed before the cursor. */ + ndisp = c_pos - wrap_offset; + nleft = prompt_visible_length + wrap_offset; + /* Where the new cursor position will be on the screen. This can be + longer than SCREENWIDTH; if it is, lmargin will be adjusted. */ + phys_c_pos = c_pos - (last_lmargin ? last_lmargin : wrap_offset); + t = _rl_screenwidth / 3; + + /* If the number of characters had already exceeded the screenwidth, + last_lmargin will be > 0. */ + + /* If the number of characters to be displayed is more than the screen + width, compute the starting offset so that the cursor is about + two-thirds of the way across the screen. */ + if (phys_c_pos > _rl_screenwidth - 2) + { + lmargin = c_pos - (2 * t); + if (lmargin < 0) + lmargin = 0; + /* If the left margin would be in the middle of a prompt with + invisible characters, don't display the prompt at all. */ + if (wrap_offset && lmargin > 0 && lmargin < nleft) + lmargin = nleft; + } + else if (ndisp < _rl_screenwidth - 2) /* XXX - was -1 */ + lmargin = 0; + else if (phys_c_pos < 1) + { + /* If we are moving back towards the beginning of the line and + the last margin is no longer correct, compute a new one. */ + lmargin = ((c_pos - 1) / t) * t; /* XXX */ + if (wrap_offset && lmargin > 0 && lmargin < nleft) + lmargin = nleft; + } + else + lmargin = last_lmargin; + + /* If the first character on the screen isn't the first character + in the display line, indicate this with a special character. */ + if (lmargin > 0) + line[lmargin] = '<'; + + /* If SCREENWIDTH characters starting at LMARGIN do not encompass + the whole line, indicate that with a special character at the + right edge of the screen. If LMARGIN is 0, we need to take the + wrap offset into account. */ + t = lmargin + M_OFFSET (lmargin, wrap_offset) + _rl_screenwidth; + if (t < out) + line[t - 1] = '>'; + + if (!rl_display_fixed || forced_display || lmargin != last_lmargin) + { + forced_display = 0; + update_line (&visible_line[last_lmargin], + &invisible_line[lmargin], + 0, + _rl_screenwidth + visible_wrap_offset, + _rl_screenwidth + (lmargin ? 0 : wrap_offset), + 0); + + /* If the visible new line is shorter than the old, but the number + of invisible characters is greater, and we are at the end of + the new line, we need to clear to eol. */ + t = _rl_last_c_pos - M_OFFSET (lmargin, wrap_offset); + if ((M_OFFSET (lmargin, wrap_offset) > visible_wrap_offset) && + (_rl_last_c_pos == out) && + t < visible_first_line_len) + { + nleft = _rl_screenwidth - t; + _rl_clear_to_eol (nleft); + } + visible_first_line_len = out - lmargin - M_OFFSET (lmargin, wrap_offset); + if (visible_first_line_len > _rl_screenwidth) + visible_first_line_len = _rl_screenwidth; + + _rl_move_cursor_relative (c_pos - lmargin, &invisible_line[lmargin]); + last_lmargin = lmargin; + } + } + fflush (rl_outstream); + + /* Swap visible and non-visible lines. */ + { + char *vtemp = visible_line; + int *itemp = vis_lbreaks, ntemp = vis_lbsize; + + visible_line = invisible_line; + invisible_line = vtemp; + + vis_lbreaks = inv_lbreaks; + inv_lbreaks = itemp; + + vis_lbsize = inv_lbsize; + inv_lbsize = ntemp; + + rl_display_fixed = 0; + /* If we are displaying on a single line, and last_lmargin is > 0, we + are not displaying any invisible characters, so set visible_wrap_offset + to 0. */ + if (_rl_horizontal_scroll_mode && last_lmargin) + visible_wrap_offset = 0; + else + visible_wrap_offset = wrap_offset; + } + + _rl_release_sigint (); +} + +/* PWP: update_line() is based on finding the middle difference of each + line on the screen; vis: + + /old first difference + /beginning of line | /old last same /old EOL + v v v v +old: eddie> Oh, my little gruntle-buggy is to me, as lurgid as +new: eddie> Oh, my little buggy says to me, as lurgid as + ^ ^ ^ ^ + \beginning of line | \new last same \new end of line + \new first difference + + All are character pointers for the sake of speed. Special cases for + no differences, as well as for end of line additions must be handled. + + Could be made even smarter, but this works well enough */ +static void +update_line (old, new, current_line, omax, nmax, inv_botlin) + register char *old, *new; + int current_line, omax, nmax, inv_botlin; +{ + register char *ofd, *ols, *oe, *nfd, *nls, *ne; + int temp, lendiff, wsatend, od, nd; + int current_invis_chars; + int col_lendiff, col_temp; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps_new, ps_old; + int new_offset, old_offset, tmp; +#endif + + /* If we're at the right edge of a terminal that supports xn, we're + ready to wrap around, so do so. This fixes problems with knowing + the exact cursor position and cut-and-paste with certain terminal + emulators. In this calculation, TEMP is the physical screen + position of the cursor. */ + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + temp = _rl_last_c_pos; + else + temp = _rl_last_c_pos - W_OFFSET(_rl_last_v_pos, visible_wrap_offset); + if (temp == _rl_screenwidth && _rl_term_autowrap && !_rl_horizontal_scroll_mode + && _rl_last_v_pos == current_line - 1) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + wchar_t wc; + mbstate_t ps; + int tempwidth, bytes; + size_t ret; + + /* This fixes only double-column characters, but if the wrapped + character comsumes more than three columns, spaces will be + inserted in the string buffer. */ + if (_rl_wrapped_line[current_line] > 0) + _rl_clear_to_eol (_rl_wrapped_line[current_line]); + + memset (&ps, 0, sizeof (mbstate_t)); + ret = mbrtowc (&wc, new, MB_CUR_MAX, &ps); + if (MB_INVALIDCH (ret)) + { + tempwidth = 1; + ret = 1; + } + else if (MB_NULLWCH (ret)) + tempwidth = 0; + else + tempwidth = wcwidth (wc); + + if (tempwidth > 0) + { + int count; + bytes = ret; + for (count = 0; count < bytes; count++) + putc (new[count], rl_outstream); + _rl_last_c_pos = tempwidth; + _rl_last_v_pos++; + memset (&ps, 0, sizeof (mbstate_t)); + ret = mbrtowc (&wc, old, MB_CUR_MAX, &ps); + if (ret != 0 && bytes != 0) + { + if (MB_INVALIDCH (ret)) + memmove (old+bytes, old+1, strlen (old+1)); + else + memmove (old+bytes, old+ret, strlen (old+ret)); + memcpy (old, new, bytes); + } + } + else + { + putc (' ', rl_outstream); + _rl_last_c_pos = 1; + _rl_last_v_pos++; + if (old[0] && new[0]) + old[0] = new[0]; + } + } + else +#endif + { + if (new[0]) + putc (new[0], rl_outstream); + else + putc (' ', rl_outstream); + _rl_last_c_pos = 1; + _rl_last_v_pos++; + if (old[0] && new[0]) + old[0] = new[0]; + } + } + + + /* Find first difference. */ +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + /* See if the old line is a subset of the new line, so that the + only change is adding characters. */ + temp = (omax < nmax) ? omax : nmax; + if (memcmp (old, new, temp) == 0) + { + ofd = old + temp; + nfd = new + temp; + } + else + { + memset (&ps_new, 0, sizeof(mbstate_t)); + memset (&ps_old, 0, sizeof(mbstate_t)); + + if (omax == nmax && STREQN (new, old, omax)) + { + ofd = old + omax; + nfd = new + nmax; + } + else + { + new_offset = old_offset = 0; + for (ofd = old, nfd = new; + (ofd - old < omax) && *ofd && + _rl_compare_chars(old, old_offset, &ps_old, new, new_offset, &ps_new); ) + { + old_offset = _rl_find_next_mbchar (old, old_offset, 1, MB_FIND_ANY); + new_offset = _rl_find_next_mbchar (new, new_offset, 1, MB_FIND_ANY); + ofd = old + old_offset; + nfd = new + new_offset; + } + } + } + } + else +#endif + for (ofd = old, nfd = new; + (ofd - old < omax) && *ofd && (*ofd == *nfd); + ofd++, nfd++) + ; + + /* Move to the end of the screen line. ND and OD are used to keep track + of the distance between ne and new and oe and old, respectively, to + move a subtraction out of each loop. */ + for (od = ofd - old, oe = ofd; od < omax && *oe; oe++, od++); + for (nd = nfd - new, ne = nfd; nd < nmax && *ne; ne++, nd++); + + /* If no difference, continue to next line. */ + if (ofd == oe && nfd == ne) + return; + + wsatend = 1; /* flag for trailing whitespace */ + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + ols = old + _rl_find_prev_mbchar (old, oe - old, MB_FIND_ANY); + nls = new + _rl_find_prev_mbchar (new, ne - new, MB_FIND_ANY); + while ((ols > ofd) && (nls > nfd)) + { + memset (&ps_old, 0, sizeof (mbstate_t)); + memset (&ps_new, 0, sizeof (mbstate_t)); + +#if 0 + /* On advice from jir@yamato.ibm.com */ + _rl_adjust_point (old, ols - old, &ps_old); + _rl_adjust_point (new, nls - new, &ps_new); +#endif + + if (_rl_compare_chars (old, ols - old, &ps_old, new, nls - new, &ps_new) == 0) + break; + + if (*ols == ' ') + wsatend = 0; + + ols = old + _rl_find_prev_mbchar (old, ols - old, MB_FIND_ANY); + nls = new + _rl_find_prev_mbchar (new, nls - new, MB_FIND_ANY); + } + } + else + { +#endif /* HANDLE_MULTIBYTE */ + ols = oe - 1; /* find last same */ + nls = ne - 1; + while ((ols > ofd) && (nls > nfd) && (*ols == *nls)) + { + if (*ols != ' ') + wsatend = 0; + ols--; + nls--; + } +#if defined (HANDLE_MULTIBYTE) + } +#endif + + if (wsatend) + { + ols = oe; + nls = ne; + } +#if defined (HANDLE_MULTIBYTE) + /* This may not work for stateful encoding, but who cares? To handle + stateful encoding properly, we have to scan each string from the + beginning and compare. */ + else if (_rl_compare_chars (ols, 0, NULL, nls, 0, NULL) == 0) +#else + else if (*ols != *nls) +#endif + { + if (*ols) /* don't step past the NUL */ + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + ols = old + _rl_find_next_mbchar (old, ols - old, 1, MB_FIND_ANY); + else + ols++; + } + if (*nls) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + nls = new + _rl_find_next_mbchar (new, nls - new, 1, MB_FIND_ANY); + else + nls++; + } + } + + /* count of invisible characters in the current invisible line. */ + current_invis_chars = W_OFFSET (current_line, wrap_offset); + if (_rl_last_v_pos != current_line) + { + _rl_move_vert (current_line); + if ((MB_CUR_MAX == 1 || rl_byte_oriented) && current_line == 0 && visible_wrap_offset) + _rl_last_c_pos += visible_wrap_offset; + } + + /* If this is the first line and there are invisible characters in the + prompt string, and the prompt string has not changed, and the current + cursor position is before the last invisible character in the prompt, + and the index of the character to move to is past the end of the prompt + string, then redraw the entire prompt string. We can only do this + reliably if the terminal supports a `cr' capability. + + This is not an efficiency hack -- there is a problem with redrawing + portions of the prompt string if they contain terminal escape + sequences (like drawing the `unbold' sequence without a corresponding + `bold') that manifests itself on certain terminals. */ + + lendiff = local_prompt ? strlen (local_prompt) : 0; + od = ofd - old; /* index of first difference in visible line */ + if (current_line == 0 && !_rl_horizontal_scroll_mode && + _rl_term_cr && lendiff > prompt_visible_length && _rl_last_c_pos > 0 && + od >= lendiff && _rl_last_c_pos <= prompt_last_invisible) + { +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif + _rl_output_some_chars (local_prompt, lendiff); + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + /* We take wrap_offset into account here so we can pass correct + information to _rl_move_cursor_relative. */ + _rl_last_c_pos = _rl_col_width (local_prompt, 0, lendiff) - wrap_offset; + cpos_adjusted = 1; + } + else + _rl_last_c_pos = lendiff; + } + + _rl_move_cursor_relative (od, old); + + /* if (len (new) > len (old)) + lendiff == difference in buffer + col_lendiff == difference on screen + When not using multibyte characters, these are equal */ + lendiff = (nls - nfd) - (ols - ofd); + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + col_lendiff = _rl_col_width (new, nfd - new, nls - new) - _rl_col_width (old, ofd - old, ols - old); + else + col_lendiff = lendiff; + + /* If we are changing the number of invisible characters in a line, and + the spot of first difference is before the end of the invisible chars, + lendiff needs to be adjusted. */ + if (current_line == 0 && !_rl_horizontal_scroll_mode && + current_invis_chars != visible_wrap_offset) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + lendiff += visible_wrap_offset - current_invis_chars; + col_lendiff += visible_wrap_offset - current_invis_chars; + } + else + { + lendiff += visible_wrap_offset - current_invis_chars; + col_lendiff = lendiff; + } + } + + /* Insert (diff (len (old), len (new)) ch. */ + temp = ne - nfd; + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + col_temp = _rl_col_width (new, nfd - new, ne - new); + else + col_temp = temp; + + if (col_lendiff > 0) /* XXX - was lendiff */ + { + /* Non-zero if we're increasing the number of lines. */ + int gl = current_line >= _rl_vis_botlin && inv_botlin > _rl_vis_botlin; + /* Sometimes it is cheaper to print the characters rather than + use the terminal's capabilities. If we're growing the number + of lines, make sure we actually cause the new line to wrap + around on auto-wrapping terminals. */ + if (_rl_terminal_can_insert && ((2 * col_temp) >= col_lendiff || _rl_term_IC) && (!_rl_term_autowrap || !gl)) + { + /* If lendiff > prompt_visible_length and _rl_last_c_pos == 0 and + _rl_horizontal_scroll_mode == 1, inserting the characters with + _rl_term_IC or _rl_term_ic will screw up the screen because of the + invisible characters. We need to just draw them. */ + if (*ols && (!_rl_horizontal_scroll_mode || _rl_last_c_pos > 0 || + lendiff <= prompt_visible_length || !current_invis_chars)) + { + insert_some_chars (nfd, lendiff, col_lendiff); + _rl_last_c_pos += col_lendiff; + } + else if ((MB_CUR_MAX == 1 || rl_byte_oriented != 0) && *ols == 0 && lendiff > 0) + { + /* At the end of a line the characters do not have to + be "inserted". They can just be placed on the screen. */ + /* However, this screws up the rest of this block, which + assumes you've done the insert because you can. */ + _rl_output_some_chars (nfd, lendiff); + _rl_last_c_pos += col_lendiff; + } + else + { + /* We have horizontal scrolling and we are not inserting at + the end. We have invisible characters in this line. This + is a dumb update. */ + _rl_output_some_chars (nfd, temp); + _rl_last_c_pos += col_temp; + return; + } + /* Copy (new) chars to screen from first diff to last match. */ + temp = nls - nfd; + if ((temp - lendiff) > 0) + { + _rl_output_some_chars (nfd + lendiff, temp - lendiff); +#if 1 + /* XXX -- this bears closer inspection. Fixes a redisplay bug + reported against bash-3.0-alpha by Andreas Schwab involving + multibyte characters and prompt strings with invisible + characters, but was previously disabled. */ + _rl_last_c_pos += _rl_col_width (nfd+lendiff, 0, temp-col_lendiff); +#else + _rl_last_c_pos += _rl_col_width (nfd+lendiff, 0, temp-lendiff); +#endif + } + } + else + { + /* cannot insert chars, write to EOL */ + _rl_output_some_chars (nfd, temp); + _rl_last_c_pos += col_temp; + /* If we're in a multibyte locale and were before the last invisible + char in the current line (which implies we just output some invisible + characters) we need to adjust _rl_last_c_pos, since it represents + a physical character position. */ + } + } + else /* Delete characters from line. */ + { + /* If possible and inexpensive to use terminal deletion, then do so. */ + if (_rl_term_dc && (2 * col_temp) >= -col_lendiff) + { + /* If all we're doing is erasing the invisible characters in the + prompt string, don't bother. It screws up the assumptions + about what's on the screen. */ + if (_rl_horizontal_scroll_mode && _rl_last_c_pos == 0 && + -lendiff == visible_wrap_offset) + col_lendiff = 0; + + if (col_lendiff) + delete_chars (-col_lendiff); /* delete (diff) characters */ + + /* Copy (new) chars to screen from first diff to last match */ + temp = nls - nfd; + if (temp > 0) + { + _rl_output_some_chars (nfd, temp); + _rl_last_c_pos += _rl_col_width (nfd, 0, temp);; + } + } + /* Otherwise, print over the existing material. */ + else + { + if (temp > 0) + { + _rl_output_some_chars (nfd, temp); + _rl_last_c_pos += col_temp; /* XXX */ + } + lendiff = (oe - old) - (ne - new); + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + col_lendiff = _rl_col_width (old, 0, oe - old) - _rl_col_width (new, 0, ne - new); + else + col_lendiff = lendiff; + + if (col_lendiff) + { + if (_rl_term_autowrap && current_line < inv_botlin) + space_to_eol (col_lendiff); + else + _rl_clear_to_eol (col_lendiff); + } + } + } +} + +/* Tell the update routines that we have moved onto a new (empty) line. */ +int +rl_on_new_line () +{ + if (visible_line) + visible_line[0] = '\0'; + + _rl_last_c_pos = _rl_last_v_pos = 0; + _rl_vis_botlin = last_lmargin = 0; + if (vis_lbreaks) + vis_lbreaks[0] = vis_lbreaks[1] = 0; + visible_wrap_offset = 0; + return 0; +} + +/* Tell the update routines that we have moved onto a new line with the + prompt already displayed. Code originally from the version of readline + distributed with CLISP. rl_expand_prompt must have already been called + (explicitly or implicitly). This still doesn't work exactly right. */ +int +rl_on_new_line_with_prompt () +{ + int prompt_size, i, l, real_screenwidth, newlines; + char *prompt_last_line, *lprompt; + + /* Initialize visible_line and invisible_line to ensure that they can hold + the already-displayed prompt. */ + prompt_size = strlen (rl_prompt) + 1; + init_line_structures (prompt_size); + + /* Make sure the line structures hold the already-displayed prompt for + redisplay. */ + lprompt = local_prompt ? local_prompt : rl_prompt; + strcpy (visible_line, lprompt); + strcpy (invisible_line, lprompt); + + /* If the prompt contains newlines, take the last tail. */ + prompt_last_line = strrchr (rl_prompt, '\n'); + if (!prompt_last_line) + prompt_last_line = rl_prompt; + + l = strlen (prompt_last_line); + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + _rl_last_c_pos = _rl_col_width (prompt_last_line, 0, l); /* XXX */ + else + _rl_last_c_pos = l; + + /* Dissect prompt_last_line into screen lines. Note that here we have + to use the real screenwidth. Readline's notion of screenwidth might be + one less, see terminal.c. */ + real_screenwidth = _rl_screenwidth + (_rl_term_autowrap ? 0 : 1); + _rl_last_v_pos = l / real_screenwidth; + /* If the prompt length is a multiple of real_screenwidth, we don't know + whether the cursor is at the end of the last line, or already at the + beginning of the next line. Output a newline just to be safe. */ + if (l > 0 && (l % real_screenwidth) == 0) + _rl_output_some_chars ("\n", 1); + last_lmargin = 0; + + newlines = 0; i = 0; + while (i <= l) + { + _rl_vis_botlin = newlines; + vis_lbreaks[newlines++] = i; + i += real_screenwidth; + } + vis_lbreaks[newlines] = l; + visible_wrap_offset = 0; + + rl_display_prompt = rl_prompt; /* XXX - make sure it's set */ + + return 0; +} + +/* Actually update the display, period. */ +int +rl_forced_update_display () +{ + if (visible_line) + { + register char *temp = visible_line; + + while (*temp) + *temp++ = '\0'; + } + rl_on_new_line (); + forced_display++; + (*rl_redisplay_function) (); + return 0; +} + +/* Move the cursor from _rl_last_c_pos to NEW, which are buffer indices. + (Well, when we don't have multibyte characters, _rl_last_c_pos is a + buffer index.) + DATA is the contents of the screen line of interest; i.e., where + the movement is being done. */ +void +_rl_move_cursor_relative (new, data) + int new; + const char *data; +{ + register int i; + int woff; /* number of invisible chars on current line */ + int cpos, dpos; /* current and desired cursor positions */ + + woff = W_OFFSET (_rl_last_v_pos, wrap_offset); + cpos = _rl_last_c_pos; +#if defined (HANDLE_MULTIBYTE) + /* If we have multibyte characters, NEW is indexed by the buffer point in + a multibyte string, but _rl_last_c_pos is the display position. In + this case, NEW's display position is not obvious and must be + calculated. We need to account for invisible characters in this line, + as long as we are past them and they are counted by _rl_col_width. */ + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + dpos = _rl_col_width (data, 0, new); + if (dpos > woff) + dpos -= woff; + } + else +#endif + dpos = new; + + /* If we don't have to do anything, then return. */ + if (cpos == dpos) + return; + + /* It may be faster to output a CR, and then move forwards instead + of moving backwards. */ + /* i == current physical cursor position. */ +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + i = _rl_last_c_pos; + else +#endif + i = _rl_last_c_pos - woff; + if (new == 0 || CR_FASTER (new, _rl_last_c_pos) || + (_rl_term_autowrap && i == _rl_screenwidth)) + { +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif /* !__MSDOS__ */ + cpos = _rl_last_c_pos = 0; + } + + if (cpos < dpos) + { + /* Move the cursor forward. We do it by printing the command + to move the cursor forward if there is one, else print that + portion of the output buffer again. Which is cheaper? */ + + /* The above comment is left here for posterity. It is faster + to print one character (non-control) than to print a control + sequence telling the terminal to move forward one character. + That kind of control is for people who don't know what the + data is underneath the cursor. */ +#if defined (HACK_TERMCAP_MOTION) + if (_rl_term_forward_char) + { + for (i = cpos; i < dpos; i++) + tputs (_rl_term_forward_char, 1, _rl_output_character_function); + } + else +#endif /* HACK_TERMCAP_MOTION */ + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + tputs (_rl_term_cr, 1, _rl_output_character_function); + for (i = 0; i < new; i++) + putc (data[i], rl_outstream); + } + else + for (i = cpos; i < new; i++) + putc (data[i], rl_outstream); + } + +#if defined (HANDLE_MULTIBYTE) + /* NEW points to the buffer point, but _rl_last_c_pos is the display point. + The byte length of the string is probably bigger than the column width + of the string, which means that if NEW == _rl_last_c_pos, then NEW's + display point is less than _rl_last_c_pos. */ +#endif + else if (cpos > dpos) + _rl_backspace (cpos - dpos); + + _rl_last_c_pos = dpos; +} + +/* PWP: move the cursor up or down. */ +void +_rl_move_vert (to) + int to; +{ + register int delta, i; + + if (_rl_last_v_pos == to || to > _rl_screenheight) + return; + + if ((delta = to - _rl_last_v_pos) > 0) + { + for (i = 0; i < delta; i++) + putc ('\n', rl_outstream); +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif + _rl_last_c_pos = 0; + } + else + { /* delta < 0 */ +#ifdef __MSDOS__ + int row, col; + + fflush (rl_outstream); /* make sure the cursor pos is current! */ + ScreenGetCursor (&row, &col); + ScreenSetCursor (row + delta, col); + i = -delta; /* in case someone wants to use it after the loop */ +#else /* !__MSDOS__ */ + if (_rl_term_up && *_rl_term_up) + for (i = 0; i < -delta; i++) + tputs (_rl_term_up, 1, _rl_output_character_function); +#endif /* !__MSDOS__ */ + } + + _rl_last_v_pos = to; /* Now TO is here */ +} + +/* Physically print C on rl_outstream. This is for functions which know + how to optimize the display. Return the number of characters output. */ +int +rl_show_char (c) + int c; +{ + int n = 1; + if (META_CHAR (c) && (_rl_output_meta_chars == 0)) + { + fprintf (rl_outstream, "M-"); + n += 2; + c = UNMETA (c); + } + +#if defined (DISPLAY_TABS) + if ((CTRL_CHAR (c) && c != '\t') || c == RUBOUT) +#else + if (CTRL_CHAR (c) || c == RUBOUT) +#endif /* !DISPLAY_TABS */ + { + fprintf (rl_outstream, "C-"); + n += 2; + c = CTRL_CHAR (c) ? UNCTRL (c) : '?'; + } + + putc (c, rl_outstream); + fflush (rl_outstream); + return n; +} + +int +rl_character_len (c, pos) + register int c, pos; +{ + unsigned char uc; + + uc = (unsigned char)c; + + if (META_CHAR (uc)) + return ((_rl_output_meta_chars == 0) ? 4 : 1); + + if (uc == '\t') + { +#if defined (DISPLAY_TABS) + return (((pos | 7) + 1) - pos); +#else + return (2); +#endif /* !DISPLAY_TABS */ + } + + if (CTRL_CHAR (c) || c == RUBOUT) + return (2); + + return ((ISPRINT (uc)) ? 1 : 2); +} +/* How to print things in the "echo-area". The prompt is treated as a + mini-modeline. */ +static int msg_saved_prompt = 0; + +#if defined (USE_VARARGS) +int +#if defined (PREFER_STDARG) +rl_message (const char *format, ...) +#else +rl_message (va_alist) + va_dcl +#endif +{ + va_list args; +#if defined (PREFER_VARARGS) + char *format; +#endif + +#if defined (PREFER_STDARG) + va_start (args, format); +#else + va_start (args); + format = va_arg (args, char *); +#endif + +#if defined (HAVE_VSNPRINTF) + vsnprintf (msg_buf, sizeof (msg_buf) - 1, format, args); +#else + vsprintf (msg_buf, format, args); + msg_buf[sizeof(msg_buf) - 1] = '\0'; /* overflow? */ +#endif + va_end (args); + + if (saved_local_prompt == 0) + { + rl_save_prompt (); + msg_saved_prompt = 1; + } + rl_display_prompt = msg_buf; + local_prompt = expand_prompt (msg_buf, &prompt_visible_length, + &prompt_last_invisible, + &prompt_invis_chars_first_line, + &prompt_physical_chars); + local_prompt_prefix = (char *)NULL; + (*rl_redisplay_function) (); + + return 0; +} +#else /* !USE_VARARGS */ +int +rl_message (format, arg1, arg2) + char *format; +{ + sprintf (msg_buf, format, arg1, arg2); + msg_buf[sizeof(msg_buf) - 1] = '\0'; /* overflow? */ + + rl_display_prompt = msg_buf; + if (saved_local_prompt == 0) + { + rl_save_prompt (); + msg_saved_prompt = 1; + } + local_prompt = expand_prompt (msg_buf, &prompt_visible_length, + &prompt_last_invisible, + &prompt_invis_chars_first_line, + &prompt_physical_chars); + local_prompt_prefix = (char *)NULL; + (*rl_redisplay_function) (); + + return 0; +} +#endif /* !USE_VARARGS */ + +/* How to clear things from the "echo-area". */ +int +rl_clear_message () +{ + rl_display_prompt = rl_prompt; + if (msg_saved_prompt) + { + rl_restore_prompt (); + msg_saved_prompt = 0; + } + (*rl_redisplay_function) (); + return 0; +} + +int +rl_reset_line_state () +{ + rl_on_new_line (); + + rl_display_prompt = rl_prompt ? rl_prompt : ""; + forced_display = 1; + return 0; +} + +void +rl_save_prompt () +{ + saved_local_prompt = local_prompt; + saved_local_prefix = local_prompt_prefix; + saved_prefix_length = prompt_prefix_length; + saved_last_invisible = prompt_last_invisible; + saved_visible_length = prompt_visible_length; + saved_invis_chars_first_line = prompt_invis_chars_first_line; + saved_physical_chars = prompt_physical_chars; + + local_prompt = local_prompt_prefix = (char *)0; + prompt_last_invisible = prompt_visible_length = prompt_prefix_length = 0; + prompt_invis_chars_first_line = prompt_physical_chars = 0; +} + +void +rl_restore_prompt () +{ + FREE (local_prompt); + FREE (local_prompt_prefix); + + local_prompt = saved_local_prompt; + local_prompt_prefix = saved_local_prefix; + prompt_prefix_length = saved_prefix_length; + prompt_last_invisible = saved_last_invisible; + prompt_visible_length = saved_visible_length; + prompt_invis_chars_first_line = saved_invis_chars_first_line; + prompt_physical_chars = saved_physical_chars; + + /* can test saved_local_prompt to see if prompt info has been saved. */ + saved_local_prompt = saved_local_prefix = (char *)0; + saved_last_invisible = saved_visible_length = saved_prefix_length = 0; + saved_invis_chars_first_line = saved_physical_chars = 0; +} + +char * +_rl_make_prompt_for_search (pchar) + int pchar; +{ + int len; + char *pmt, *p; + + rl_save_prompt (); + + /* We've saved the prompt, and can do anything with the various prompt + strings we need before they're restored. We want the unexpanded + portion of the prompt string after any final newline. */ + p = rl_prompt ? strrchr (rl_prompt, '\n') : 0; + if (p == 0) + { + len = (rl_prompt && *rl_prompt) ? strlen (rl_prompt) : 0; + pmt = (char *)xmalloc (len + 2); + if (len) + strcpy (pmt, rl_prompt); + pmt[len] = pchar; + pmt[len+1] = '\0'; + } + else + { + p++; + len = strlen (p); + pmt = (char *)xmalloc (len + 2); + if (len) + strcpy (pmt, p); + pmt[len] = pchar; + pmt[len+1] = '\0'; + } + + /* will be overwritten by expand_prompt, called from rl_message */ + prompt_physical_chars = saved_physical_chars + 1; + return pmt; +} + +/* Quick redisplay hack when erasing characters at the end of the line. */ +void +_rl_erase_at_end_of_line (l) + int l; +{ + register int i; + + _rl_backspace (l); + for (i = 0; i < l; i++) + putc (' ', rl_outstream); + _rl_backspace (l); + for (i = 0; i < l; i++) + visible_line[--_rl_last_c_pos] = '\0'; + rl_display_fixed++; +} + +/* Clear to the end of the line. COUNT is the minimum + number of character spaces to clear, */ +void +_rl_clear_to_eol (count) + int count; +{ +#ifndef __MSDOS__ + if (_rl_term_clreol) + tputs (_rl_term_clreol, 1, _rl_output_character_function); + else +#endif + if (count) + space_to_eol (count); +} + +/* Clear to the end of the line using spaces. COUNT is the minimum + number of character spaces to clear, */ +static void +space_to_eol (count) + int count; +{ + register int i; + + for (i = 0; i < count; i++) + putc (' ', rl_outstream); + + _rl_last_c_pos += count; +} + +void +_rl_clear_screen () +{ +#if defined (__GO32__) + ScreenClear (); /* FIXME: only works in text modes */ + ScreenSetCursor (0, 0); /* term_clrpag is "cl" which homes the cursor */ +#else + if (_rl_term_clrpag) + tputs (_rl_term_clrpag, 1, _rl_output_character_function); + else + rl_crlf (); +#endif +} + +/* Insert COUNT characters from STRING to the output stream at column COL. */ +static void +insert_some_chars (string, count, col) + char *string; + int count, col; +{ +#if defined (__MSDOS__) || defined (__MINGW32__) + _rl_output_some_chars (string, count); +#else + /* DEBUGGING */ + if (MB_CUR_MAX == 1 || rl_byte_oriented) + if (count != col) + fprintf(stderr, "readline: debug: insert_some_chars: count (%d) != col (%d)\n", count, col); + + /* If IC is defined, then we do not have to "enter" insert mode. */ + if (_rl_term_IC) + { + char *buffer; + + buffer = tgoto (_rl_term_IC, 0, col); + tputs (buffer, 1, _rl_output_character_function); + _rl_output_some_chars (string, count); + } + else + { + register int i; + + /* If we have to turn on insert-mode, then do so. */ + if (_rl_term_im && *_rl_term_im) + tputs (_rl_term_im, 1, _rl_output_character_function); + + /* If there is a special command for inserting characters, then + use that first to open up the space. */ + if (_rl_term_ic && *_rl_term_ic) + { + for (i = col; i--; ) + tputs (_rl_term_ic, 1, _rl_output_character_function); + } + + /* Print the text. */ + _rl_output_some_chars (string, count); + + /* If there is a string to turn off insert mode, we had best use + it now. */ + if (_rl_term_ei && *_rl_term_ei) + tputs (_rl_term_ei, 1, _rl_output_character_function); + } +#endif /* __MSDOS__ || __MINGW32__ */ +} + +/* Delete COUNT characters from the display line. */ +static void +delete_chars (count) + int count; +{ + if (count > _rl_screenwidth) /* XXX */ + return; + +#if !defined (__MSDOS__) && !defined (__MINGW32__) + if (_rl_term_DC && *_rl_term_DC) + { + char *buffer; + buffer = tgoto (_rl_term_DC, count, count); + tputs (buffer, count, _rl_output_character_function); + } + else + { + if (_rl_term_dc && *_rl_term_dc) + while (count--) + tputs (_rl_term_dc, 1, _rl_output_character_function); + } +#endif /* !__MSDOS__ && !__MINGW32__ */ +} + +void +_rl_update_final () +{ + int full_lines; + + full_lines = 0; + /* If the cursor is the only thing on an otherwise-blank last line, + compensate so we don't print an extra CRLF. */ + if (_rl_vis_botlin && _rl_last_c_pos == 0 && + visible_line[vis_lbreaks[_rl_vis_botlin]] == 0) + { + _rl_vis_botlin--; + full_lines = 1; + } + _rl_move_vert (_rl_vis_botlin); + /* If we've wrapped lines, remove the final xterm line-wrap flag. */ + if (full_lines && _rl_term_autowrap && (VIS_LLEN(_rl_vis_botlin) == _rl_screenwidth)) + { + char *last_line; + + last_line = &visible_line[vis_lbreaks[_rl_vis_botlin]]; + _rl_move_cursor_relative (_rl_screenwidth - 1, last_line); + _rl_clear_to_eol (0); + putc (last_line[_rl_screenwidth - 1], rl_outstream); + } + _rl_vis_botlin = 0; + rl_crlf (); + fflush (rl_outstream); + rl_display_fixed++; +} + +/* Move to the start of the current line. */ +static void +cr () +{ + if (_rl_term_cr) + { +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif + _rl_last_c_pos = 0; + } +} + +/* Redraw the last line of a multi-line prompt that may possibly contain + terminal escape sequences. Called with the cursor at column 0 of the + line to draw the prompt on. */ +static void +redraw_prompt (t) + char *t; +{ + char *oldp; + + oldp = rl_display_prompt; + rl_save_prompt (); + + rl_display_prompt = t; + local_prompt = expand_prompt (t, &prompt_visible_length, + &prompt_last_invisible, + &prompt_invis_chars_first_line, + &prompt_physical_chars); + local_prompt_prefix = (char *)NULL; + + rl_forced_update_display (); + + rl_display_prompt = oldp; + rl_restore_prompt(); +} + +/* Redisplay the current line after a SIGWINCH is received. */ +void +_rl_redisplay_after_sigwinch () +{ + char *t; + + /* Clear the current line and put the cursor at column 0. Make sure + the right thing happens if we have wrapped to a new screen line. */ + if (_rl_term_cr) + { +#if defined (__MSDOS__) + putc ('\r', rl_outstream); +#else + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif + _rl_last_c_pos = 0; +#if defined (__MSDOS__) + space_to_eol (_rl_screenwidth); + putc ('\r', rl_outstream); +#else + if (_rl_term_clreol) + tputs (_rl_term_clreol, 1, _rl_output_character_function); + else + { + space_to_eol (_rl_screenwidth); + tputs (_rl_term_cr, 1, _rl_output_character_function); + } +#endif + if (_rl_last_v_pos > 0) + _rl_move_vert (0); + } + else + rl_crlf (); + + /* Redraw only the last line of a multi-line prompt. */ + t = strrchr (rl_display_prompt, '\n'); + if (t) + redraw_prompt (++t); + else + rl_forced_update_display (); +} + +void +_rl_clean_up_for_exit () +{ + if (readline_echoing_p) + { + _rl_move_vert (_rl_vis_botlin); + _rl_vis_botlin = 0; + fflush (rl_outstream); + rl_restart_output (1, 0); + } +} + +void +_rl_erase_entire_line () +{ + cr (); + _rl_clear_to_eol (0); + cr (); + fflush (rl_outstream); +} + +/* return the `current display line' of the cursor -- the number of lines to + move up to get to the first screen line of the current readline line. */ +int +_rl_current_display_line () +{ + int ret, nleft; + + /* Find out whether or not there might be invisible characters in the + editing buffer. */ + if (rl_display_prompt == rl_prompt) + nleft = _rl_last_c_pos - _rl_screenwidth - rl_visible_prompt_length; + else + nleft = _rl_last_c_pos - _rl_screenwidth; + + if (nleft > 0) + ret = 1 + nleft / _rl_screenwidth; + else + ret = 0; + + return ret; +} + +#if defined (HANDLE_MULTIBYTE) +/* Calculate the number of screen columns occupied by STR from START to END. + In the case of multibyte characters with stateful encoding, we have to + scan from the beginning of the string to take the state into account. */ +static int +_rl_col_width (str, start, end) + const char *str; + int start, end; +{ + wchar_t wc; + mbstate_t ps = {0}; + int tmp, point, width, max; + + if (end <= start) + return 0; + + point = 0; + max = end; + + while (point < start) + { + tmp = mbrlen (str + point, max, &ps); + if (MB_INVALIDCH ((size_t)tmp)) + { + /* In this case, the bytes are invalid or too short to compose a + multibyte character, so we assume that the first byte represents + a single character. */ + point++; + max--; + + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (tmp)) + break; /* Found '\0' */ + else + { + point += tmp; + max -= tmp; + } + } + + /* If START is not a byte that starts a character, then POINT will be + greater than START. In this case, assume that (POINT - START) gives + a byte count that is the number of columns of difference. */ + width = point - start; + + while (point < end) + { + tmp = mbrtowc (&wc, str + point, max, &ps); + if (MB_INVALIDCH ((size_t)tmp)) + { + /* In this case, the bytes are invalid or too short to compose a + multibyte character, so we assume that the first byte represents + a single character. */ + point++; + max--; + + /* and assume that the byte occupies a single column. */ + width++; + + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (tmp)) + break; /* Found '\0' */ + else + { + point += tmp; + max -= tmp; + tmp = wcwidth(wc); + width += (tmp >= 0) ? tmp : 1; + } + } + + width += point - end; + + return width; +} +#endif /* HANDLE_MULTIBYTE */ diff --git a/external/gpl3/gdb/dist/readline/doc/ChangeLog.gdb b/external/gpl3/gdb/dist/readline/doc/ChangeLog.gdb new file mode 100644 index 000000000000..14d32f67c090 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/ChangeLog.gdb @@ -0,0 +1,83 @@ +2006-04-24 Daniel Jacobowitz + + Imported readline 5.1, and upstream patches 001-004. + +2003-09-14 Andrew Cagney + + * history.0: Delete generated file. + +2002-02-24 Elena Zannoni + + * ChangeLog.gdb: Renamed from ChangeLog. + +2002-01-20 Eli Zaretskii + + * rluser.texinfo (Sample Init File): Prevent overfull hboxes. + From Brian Youmans <3diff@gnu.org>. + +2000-07-09 Elena Zannoni + + * Removed generated files rluserman.{dvi, info, html, ps}. + +2000-07-07 Elena Zannoni + + * Import of readline 4.1. + + Regenerated inc-hist.texinfo as copy of hsuser.texinfo, for + inclusion in the gdb manual. + + New file: rluserman.texinfo + +Tue Apr 18 15:43:52 2000 Andrew Cagney + + * readline.0: Delete. Generated by Makefile, deleted by distclean + rule. + +Tue Mar 28 16:06:22 2000 Andrew Cagney + + * inc-hist.texinfo, rluser.texinfo: Revert change Fri Mar 24 + 18:04:32 2000 Andrew Cagney . + Unconditionally provide @chapter and @node. + +Fri Mar 24 18:04:32 2000 Andrew Cagney + + * inc-hist.texinfo: When GDBN omit the chapter/node. + * rluser.texinfo (Command Line Editing): Ditto. + +1999-08-10 Elena Zannoni + + * hsuser.texinfo (Bash History Builtins): Comment out btindex + commands. + + * inc-hist.texinfo: New file. Same as hsuser.texinfo, but w/o + cross reference to GNU History Manual. + +Tue Dec 22 10:07:58 1998 Elena Zannoni + + * hsuser.texinfo (Bash History Builtins): comment out btindex + commands. + + * Import of Readline 2.2.1. + + New files: readline.0, readline.3, texi2dvi, texi2html. + +1998-12-17 Felix Lee + + * inc-hist.texi: @node line "Using History" was wrong. + +Thu Jul 9 17:03:26 1998 Edith Epstein + + * inc-hist.texi: one line change. + +Wed Sep 20 12:57:29 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Tue Feb 2 11:40:04 1993 Roland H. Pesch (pesch@fowanton.cygnus.com) + + * Makefile.in: configurable (and useable) Makefile template + * Makefile: removed, replaced with configurable Makefile.in + * texindex.c texinfo.tex: remove, replacing w/refs to tools + elsewhere in distribution tree + * configure.in: pro forma configure stub + * ChangeLog: new file diff --git a/external/gpl3/gdb/dist/readline/doc/Makefile.in b/external/gpl3/gdb/dist/readline/doc/Makefile.in new file mode 100644 index 000000000000..096f4408496f --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/Makefile.in @@ -0,0 +1,255 @@ +# This makefile for Readline library documentation is in -*- text -*- mode. +# Emacs likes it that way. + +# Copyright (C) 1996-2004 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +topdir = @top_srcdir@ +srcdir = @srcdir@ +VPATH = .:@srcdir@ + +prefix = @prefix@ + +datarootdir = @datarootdir@ + +infodir = @infodir@ + +mandir = @mandir@ +manpfx = man + +man1ext = .1 +man1dir = $(mandir)/$(manpfx)1 +man3ext = .3 +man3dir = $(mandir)/$(manpfx)3 + +# set this to a value to have the HTML documentation installed +htmldir = + +# Support an alternate destination root directory for package building +DESTDIR = + +SHELL = @MAKE_SHELL@ +RM = rm -f + +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ + +BUILD_DIR = @BUILD_DIR@ +TEXINPUTDIR = $(srcdir) + +MAKEINFO = LANGUAGE= makeinfo +TEXI2DVI = $(srcdir)/texi2dvi +TEXI2HTML = $(srcdir)/texi2html +QUIETPS = #set this to -q to shut up dvips +PAPERSIZE = letter +PSDPI = 600 +DVIPS = dvips -D ${PSDPI} $(QUIETPS) -t ${PAPERSIZE} -o $@ # tricky + +# These tools might not be available; they're not required +DVIPDF = dvipdfm -o $@ -p ${PAPERSIZE} +PSPDF = gs -sPAPERSIZE=${PAPERSIZE} -sDEVICE=pdfwrite -dNOPAUSE -dBATCH -sOutputFile=$@ + +RLSRC = $(srcdir)/rlman.texi $(srcdir)/rluser.texi \ + $(srcdir)/rltech.texi $(srcdir)/version.texi \ + $(srcdir)/rluserman.texi +HISTSRC = $(srcdir)/history.texi $(srcdir)/hsuser.texi \ + $(srcdir)/hstech.texi $(srcdir)/version.texi + +# This should be a program that converts troff to an ascii-readable format +NROFF = groff -Tascii + +# This should be a program that converts troff to postscript +GROFF = groff + +DVIOBJ = readline.dvi history.dvi rluserman.dvi +INFOOBJ = readline.info history.info rluserman.info +PSOBJ = readline.ps history.ps rluserman.ps readline_3.ps history_3.ps +HTMLOBJ = readline.html history.html rluserman.html +TEXTOBJ = readline.0 history.0 +PDFOBJ = readline.pdf history.pdf rluserman.pdf + +INTERMEDIATE_OBJ = rlman.dvi + +DIST_DOCS = $(DVIOBJ) $(PSOBJ) $(HTMLOBJ) $(INFOOBJ) $(TEXTOBJ) + +.SUFFIXES: .0 .3 .ps .txt .dvi .html .pdf + +.3.0: + $(RM) $@ + -${NROFF} -man $< > $@ + +.ps.pdf: + $(RM) $@ + -${PSPDF} $< + +.dvi.pdf: + $(RM) $@ + -${DVIPDF} $< + +all: info dvi html ps text +nodvi: info html text + +info: $(INFOOBJ) +dvi: $(DVIOBJ) +ps: $(PSOBJ) +html: $(HTMLOBJ) +text: $(TEXTOBJ) +pdf: $(PDFOBJ) + +readline.dvi: $(RLSRC) + TEXINPUTS=.:$(TEXINPUTDIR):$$TEXINPUTS $(TEXI2DVI) $(srcdir)/rlman.texi + mv rlman.dvi readline.dvi + +readline.info: $(RLSRC) + $(MAKEINFO) --no-split -I $(TEXINPUTDIR) -o $@ $(srcdir)/rlman.texi + +rluserman.dvi: $(RLSRC) + TEXINPUTS=.:$(TEXINPUTDIR):$$TEXINPUTS $(TEXI2DVI) $(srcdir)/rluserman.texi + +rluserman.info: $(RLSRC) + $(MAKEINFO) --no-split -I $(TEXINPUTDIR) -o $@ $(srcdir)/rluserman.texi + +history.dvi: ${HISTSRC} + TEXINPUTS=.:$(TEXINPUTDIR):$$TEXINPUTS $(TEXI2DVI) $(srcdir)/history.texi + +history.info: ${HISTSRC} + $(MAKEINFO) --no-split -I $(TEXINPUTDIR) -o $@ $(srcdir)/history.texi + +readline.ps: readline.dvi + $(RM) $@ + $(DVIPS) readline.dvi + +rluserman.ps: rluserman.dvi + $(RM) $@ + $(DVIPS) rluserman.dvi + +history.ps: history.dvi + $(RM) $@ + $(DVIPS) history.dvi + +# +# This leaves readline.html and rlman.html -- rlman.html is for www.gnu.org +# +readline.html: ${RLSRC} + $(TEXI2HTML) -menu -monolithic -I $(TEXINPUTDIR) $(srcdir)/rlman.texi + sed -e 's:rlman.html:readline.html:g' rlman.html > readline.html + $(RM) rlman.html + +rluserman.html: ${RLSRC} + $(TEXI2HTML) -menu -monolithic -I $(TEXINPUTDIR) $(srcdir)/rluserman.texi + +history.html: ${HISTSRC} + $(TEXI2HTML) -menu -monolithic -I $(TEXINPUTDIR) $(srcdir)/history.texi + +readline.0: readline.3 + +readline_3.ps: readline.3 + ${RM} $@ + ${GROFF} -man < $(srcdir)/readline.3 > $@ + +history.0: history.3 + +history_3.ps: history.3 + ${RM} $@ + ${GROFF} -man < $(srcdir)/history.3 > $@ + +readline.pdf: readline.dvi +history.pdf: history.dvi +rluserman.pdf: rluserman.dvi + +clean: + $(RM) *.aux *.bak *.cp *.fn *.ky *.log *.pg *.toc *.tp *.vr *.cps \ + *.pgs *.bt *.bts *.rw *.rws *.fns *.kys *.tps *.vrs *.o \ + core *.core + +mostlyclean: clean + +distclean: clean maybe-clean + $(RM) $(INTERMEDIATE_OBJ) + $(RM) Makefile + +maybe-clean: + -if test "X$(topdir)" != "X$(BUILD_DIR)"; then \ + $(RM) $(DIST_DOCS); \ + fi + +maintainer-clean: clean + $(RM) $(DIST_DOCS) + $(RM) $(INTERMEDIATE_OBJ) + $(RM) $(PDFOBJ) + $(RM) Makefile + +installdirs: $(topdir)/support/mkdirs + -$(SHELL) $(topdir)/support/mkdirs $(DESTDIR)$(infodir) $(DESTDIR)$(man3dir) + -if test -n "${htmldir}" ; then \ + $(SHELL) $(topdir)/support/mkdirs $(DESTDIR)$(htmldir) ; \ + fi + +install: installdirs + if test -f readline.info; then \ + ${INSTALL_DATA} readline.info $(DESTDIR)$(infodir)/readline.info; \ + else \ + ${INSTALL_DATA} $(srcdir)/readline.info $(DESTDIR)$(infodir)/readline.info; \ + fi + if test -f rluserman.info; then \ + ${INSTALL_DATA} rluserman.info $(DESTDIR)$(infodir)/rluserman.info; \ + else \ + ${INSTALL_DATA} $(srcdir)/rluserman.info $(DESTDIR)$(infodir)/rluserman.info; \ + fi + if test -f history.info; then \ + ${INSTALL_DATA} history.info $(DESTDIR)$(infodir)/history.info; \ + else \ + ${INSTALL_DATA} $(srcdir)/history.info $(DESTDIR)$(infodir)/history.info; \ + fi + -if $(SHELL) -c 'install-info --version' >/dev/null 2>&1; then \ + install-info --dir-file=$(DESTDIR)$(infodir)/dir \ + $(DESTDIR)$(infodir)/readline.info ; \ + install-info --dir-file=$(DESTDIR)$(infodir)/dir \ + $(DESTDIR)$(infodir)/history.info ; \ + install-info --dir-file=$(DESTDIR)$(infodir)/dir \ + $(DESTDIR)$(infodir)/rluserman.info ; \ + else true; fi + -${INSTALL_DATA} $(srcdir)/readline.3 $(DESTDIR)$(man3dir)/readline$(man3ext) + -${INSTALL_DATA} $(srcdir)/history.3 $(DESTDIR)$(man3dir)/history$(man3ext) + -if test -n "${htmldir}" ; then \ + if test -f readline.html; then \ + ${INSTALL_DATA} readline.html $(DESTDIR)$(htmldir)/readline.html; \ + else \ + ${INSTALL_DATA} $(srcdir)/readline.html $(DESTDIR)$(htmldir)/readline.html; \ + fi ; \ + if test -f history.html; then \ + ${INSTALL_DATA} history.html $(DESTDIR)$(htmldir)/history.html; \ + else \ + ${INSTALL_DATA} $(srcdir)/history.html $(DESTDIR)$(htmldir)/history.html; \ + fi ; \ + if test -f rluserman.html; then \ + ${INSTALL_DATA} rluserman.html $(DESTDIR)$(htmldir)/rluserman.html; \ + else \ + ${INSTALL_DATA} $(srcdir)/rluserman.html $(DESTDIR)$(htmldir)/rluserman.html; \ + fi ; \ + fi + +uninstall: + $(RM) $(DESTDIR)$(infodir)/readline.info + $(RM) $(DESTDIR)$(infodir)/rluserman.info + $(RM) $(DESTDIR)$(infodir)/history.info + $(RM) $(DESTDIR)$(man3dir)/readline$(man3ext) + $(RM) $(DESTDIR)$(man3dir)/history$(man3ext) + -if test -n "${htmldir}" ; then \ + $(RM) $(DESTDIR)$(htmldir)/readline.html ; \ + $(RM) $(DESTDIR)$(htmldir)/rluserman.html ; \ + $(RM) $(DESTDIR)$(htmldir)/history.html ; \ + fi diff --git a/external/gpl3/gdb/dist/readline/doc/fdl.texi b/external/gpl3/gdb/dist/readline/doc/fdl.texi new file mode 100644 index 000000000000..47ead9f095e0 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/fdl.texi @@ -0,0 +1,452 @@ + +@node GNU Free Documentation License +@appendixsec GNU Free Documentation License + +@cindex FDL, GNU Free Documentation License +@center Version 1.2, November 2002 + +@display +Copyright @copyright{} 2000,2001,2002 Free Software Foundation, Inc. +59 Temple Place, Suite 330, Boston, MA 02111-1307, USA + +Everyone is permitted to copy and distribute verbatim copies +of this license document, but changing it is not allowed. +@end display + +@enumerate 0 +@item +PREAMBLE + +The purpose of this License is to make a manual, textbook, or other +functional and useful document @dfn{free} in the sense of freedom: to +assure everyone the effective freedom to copy and redistribute it, +with or without modifying it, either commercially or noncommercially. +Secondarily, this License preserves for the author and publisher a way +to get credit for their work, while not being considered responsible +for modifications made by others. + +This License is a kind of ``copyleft'', which means that derivative +works of the document must themselves be free in the same sense. It +complements the GNU General Public License, which is a copyleft +license designed for free software. + +We have designed this License in order to use it for manuals for free +software, because free software needs free documentation: a free +program should come with manuals providing the same freedoms that the +software does. But this License is not limited to software manuals; +it can be used for any textual work, regardless of subject matter or +whether it is published as a printed book. We recommend this License +principally for works whose purpose is instruction or reference. + +@item +APPLICABILITY AND DEFINITIONS + +This License applies to any manual or other work, in any medium, that +contains a notice placed by the copyright holder saying it can be +distributed under the terms of this License. Such a notice grants a +world-wide, royalty-free license, unlimited in duration, to use that +work under the conditions stated herein. The ``Document'', below, +refers to any such manual or work. Any member of the public is a +licensee, and is addressed as ``you''. You accept the license if you +copy, modify or distribute the work in a way requiring permission +under copyright law. + +A ``Modified Version'' of the Document means any work containing the +Document or a portion of it, either copied verbatim, or with +modifications and/or translated into another language. + +A ``Secondary Section'' is a named appendix or a front-matter section +of the Document that deals exclusively with the relationship of the +publishers or authors of the Document to the Document's overall +subject (or to related matters) and contains nothing that could fall +directly within that overall subject. (Thus, if the Document is in +part a textbook of mathematics, a Secondary Section may not explain +any mathematics.) The relationship could be a matter of historical +connection with the subject or with related matters, or of legal, +commercial, philosophical, ethical or political position regarding +them. + +The ``Invariant Sections'' are certain Secondary Sections whose titles +are designated, as being those of Invariant Sections, in the notice +that says that the Document is released under this License. If a +section does not fit the above definition of Secondary then it is not +allowed to be designated as Invariant. The Document may contain zero +Invariant Sections. If the Document does not identify any Invariant +Sections then there are none. + +The ``Cover Texts'' are certain short passages of text that are listed, +as Front-Cover Texts or Back-Cover Texts, in the notice that says that +the Document is released under this License. A Front-Cover Text may +be at most 5 words, and a Back-Cover Text may be at most 25 words. + +A ``Transparent'' copy of the Document means a machine-readable copy, +represented in a format whose specification is available to the +general public, that is suitable for revising the document +straightforwardly with generic text editors or (for images composed of +pixels) generic paint programs or (for drawings) some widely available +drawing editor, and that is suitable for input to text formatters or +for automatic translation to a variety of formats suitable for input +to text formatters. A copy made in an otherwise Transparent file +format whose markup, or absence of markup, has been arranged to thwart +or discourage subsequent modification by readers is not Transparent. +An image format is not Transparent if used for any substantial amount +of text. A copy that is not ``Transparent'' is called ``Opaque''. + +Examples of suitable formats for Transparent copies include plain +@sc{ascii} without markup, Texinfo input format, La@TeX{} input +format, @acronym{SGML} or @acronym{XML} using a publicly available +@acronym{DTD}, and standard-conforming simple @acronym{HTML}, +PostScript or @acronym{PDF} designed for human modification. Examples +of transparent image formats include @acronym{PNG}, @acronym{XCF} and +@acronym{JPG}. Opaque formats include proprietary formats that can be +read and edited only by proprietary word processors, @acronym{SGML} or +@acronym{XML} for which the @acronym{DTD} and/or processing tools are +not generally available, and the machine-generated @acronym{HTML}, +PostScript or @acronym{PDF} produced by some word processors for +output purposes only. + +The ``Title Page'' means, for a printed book, the title page itself, +plus such following pages as are needed to hold, legibly, the material +this License requires to appear in the title page. For works in +formats which do not have any title page as such, ``Title Page'' means +the text near the most prominent appearance of the work's title, +preceding the beginning of the body of the text. + +A section ``Entitled XYZ'' means a named subunit of the Document whose +title either is precisely XYZ or contains XYZ in parentheses following +text that translates XYZ in another language. (Here XYZ stands for a +specific section name mentioned below, such as ``Acknowledgements'', +``Dedications'', ``Endorsements'', or ``History''.) To ``Preserve the Title'' +of such a section when you modify the Document means that it remains a +section ``Entitled XYZ'' according to this definition. + +The Document may include Warranty Disclaimers next to the notice which +states that this License applies to the Document. These Warranty +Disclaimers are considered to be included by reference in this +License, but only as regards disclaiming warranties: any other +implication that these Warranty Disclaimers may have is void and has +no effect on the meaning of this License. + +@item +VERBATIM COPYING + +You may copy and distribute the Document in any medium, either +commercially or noncommercially, provided that this License, the +copyright notices, and the license notice saying this License applies +to the Document are reproduced in all copies, and that you add no other +conditions whatsoever to those of this License. You may not use +technical measures to obstruct or control the reading or further +copying of the copies you make or distribute. However, you may accept +compensation in exchange for copies. If you distribute a large enough +number of copies you must also follow the conditions in section 3. + +You may also lend copies, under the same conditions stated above, and +you may publicly display copies. + +@item +COPYING IN QUANTITY + +If you publish printed copies (or copies in media that commonly have +printed covers) of the Document, numbering more than 100, and the +Document's license notice requires Cover Texts, you must enclose the +copies in covers that carry, clearly and legibly, all these Cover +Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on +the back cover. Both covers must also clearly and legibly identify +you as the publisher of these copies. The front cover must present +the full title with all words of the title equally prominent and +visible. You may add other material on the covers in addition. +Copying with changes limited to the covers, as long as they preserve +the title of the Document and satisfy these conditions, can be treated +as verbatim copying in other respects. + +If the required texts for either cover are too voluminous to fit +legibly, you should put the first ones listed (as many as fit +reasonably) on the actual cover, and continue the rest onto adjacent +pages. + +If you publish or distribute Opaque copies of the Document numbering +more than 100, you must either include a machine-readable Transparent +copy along with each Opaque copy, or state in or with each Opaque copy +a computer-network location from which the general network-using +public has access to download using public-standard network protocols +a complete Transparent copy of the Document, free of added material. +If you use the latter option, you must take reasonably prudent steps, +when you begin distribution of Opaque copies in quantity, to ensure +that this Transparent copy will remain thus accessible at the stated +location until at least one year after the last time you distribute an +Opaque copy (directly or through your agents or retailers) of that +edition to the public. + +It is requested, but not required, that you contact the authors of the +Document well before redistributing any large number of copies, to give +them a chance to provide you with an updated version of the Document. + +@item +MODIFICATIONS + +You may copy and distribute a Modified Version of the Document under +the conditions of sections 2 and 3 above, provided that you release +the Modified Version under precisely this License, with the Modified +Version filling the role of the Document, thus licensing distribution +and modification of the Modified Version to whoever possesses a copy +of it. In addition, you must do these things in the Modified Version: + +@enumerate A +@item +Use in the Title Page (and on the covers, if any) a title distinct +from that of the Document, and from those of previous versions +(which should, if there were any, be listed in the History section +of the Document). You may use the same title as a previous version +if the original publisher of that version gives permission. + +@item +List on the Title Page, as authors, one or more persons or entities +responsible for authorship of the modifications in the Modified +Version, together with at least five of the principal authors of the +Document (all of its principal authors, if it has fewer than five), +unless they release you from this requirement. + +@item +State on the Title page the name of the publisher of the +Modified Version, as the publisher. + +@item +Preserve all the copyright notices of the Document. + +@item +Add an appropriate copyright notice for your modifications +adjacent to the other copyright notices. + +@item +Include, immediately after the copyright notices, a license notice +giving the public permission to use the Modified Version under the +terms of this License, in the form shown in the Addendum below. + +@item +Preserve in that license notice the full lists of Invariant Sections +and required Cover Texts given in the Document's license notice. + +@item +Include an unaltered copy of this License. + +@item +Preserve the section Entitled ``History'', Preserve its Title, and add +to it an item stating at least the title, year, new authors, and +publisher of the Modified Version as given on the Title Page. If +there is no section Entitled ``History'' in the Document, create one +stating the title, year, authors, and publisher of the Document as +given on its Title Page, then add an item describing the Modified +Version as stated in the previous sentence. + +@item +Preserve the network location, if any, given in the Document for +public access to a Transparent copy of the Document, and likewise +the network locations given in the Document for previous versions +it was based on. These may be placed in the ``History'' section. +You may omit a network location for a work that was published at +least four years before the Document itself, or if the original +publisher of the version it refers to gives permission. + +@item +For any section Entitled ``Acknowledgements'' or ``Dedications'', Preserve +the Title of the section, and preserve in the section all the +substance and tone of each of the contributor acknowledgements and/or +dedications given therein. + +@item +Preserve all the Invariant Sections of the Document, +unaltered in their text and in their titles. Section numbers +or the equivalent are not considered part of the section titles. + +@item +Delete any section Entitled ``Endorsements''. Such a section +may not be included in the Modified Version. + +@item +Do not retitle any existing section to be Entitled ``Endorsements'' or +to conflict in title with any Invariant Section. + +@item +Preserve any Warranty Disclaimers. +@end enumerate + +If the Modified Version includes new front-matter sections or +appendices that qualify as Secondary Sections and contain no material +copied from the Document, you may at your option designate some or all +of these sections as invariant. To do this, add their titles to the +list of Invariant Sections in the Modified Version's license notice. +These titles must be distinct from any other section titles. + +You may add a section Entitled ``Endorsements'', provided it contains +nothing but endorsements of your Modified Version by various +parties---for example, statements of peer review or that the text has +been approved by an organization as the authoritative definition of a +standard. + +You may add a passage of up to five words as a Front-Cover Text, and a +passage of up to 25 words as a Back-Cover Text, to the end of the list +of Cover Texts in the Modified Version. Only one passage of +Front-Cover Text and one of Back-Cover Text may be added by (or +through arrangements made by) any one entity. If the Document already +includes a cover text for the same cover, previously added by you or +by arrangement made by the same entity you are acting on behalf of, +you may not add another; but you may replace the old one, on explicit +permission from the previous publisher that added the old one. + +The author(s) and publisher(s) of the Document do not by this License +give permission to use their names for publicity for or to assert or +imply endorsement of any Modified Version. + +@item +COMBINING DOCUMENTS + +You may combine the Document with other documents released under this +License, under the terms defined in section 4 above for modified +versions, provided that you include in the combination all of the +Invariant Sections of all of the original documents, unmodified, and +list them all as Invariant Sections of your combined work in its +license notice, and that you preserve all their Warranty Disclaimers. + +The combined work need only contain one copy of this License, and +multiple identical Invariant Sections may be replaced with a single +copy. If there are multiple Invariant Sections with the same name but +different contents, make the title of each such section unique by +adding at the end of it, in parentheses, the name of the original +author or publisher of that section if known, or else a unique number. +Make the same adjustment to the section titles in the list of +Invariant Sections in the license notice of the combined work. + +In the combination, you must combine any sections Entitled ``History'' +in the various original documents, forming one section Entitled +``History''; likewise combine any sections Entitled ``Acknowledgements'', +and any sections Entitled ``Dedications''. You must delete all +sections Entitled ``Endorsements.'' + +@item +COLLECTIONS OF DOCUMENTS + +You may make a collection consisting of the Document and other documents +released under this License, and replace the individual copies of this +License in the various documents with a single copy that is included in +the collection, provided that you follow the rules of this License for +verbatim copying of each of the documents in all other respects. + +You may extract a single document from such a collection, and distribute +it individually under this License, provided you insert a copy of this +License into the extracted document, and follow this License in all +other respects regarding verbatim copying of that document. + +@item +AGGREGATION WITH INDEPENDENT WORKS + +A compilation of the Document or its derivatives with other separate +and independent documents or works, in or on a volume of a storage or +distribution medium, is called an ``aggregate'' if the copyright +resulting from the compilation is not used to limit the legal rights +of the compilation's users beyond what the individual works permit. +When the Document is included an aggregate, this License does not +apply to the other works in the aggregate which are not themselves +derivative works of the Document. + +If the Cover Text requirement of section 3 is applicable to these +copies of the Document, then if the Document is less than one half of +the entire aggregate, the Document's Cover Texts may be placed on +covers that bracket the Document within the aggregate, or the +electronic equivalent of covers if the Document is in electronic form. +Otherwise they must appear on printed covers that bracket the whole +aggregate. + +@item +TRANSLATION + +Translation is considered a kind of modification, so you may +distribute translations of the Document under the terms of section 4. +Replacing Invariant Sections with translations requires special +permission from their copyright holders, but you may include +translations of some or all Invariant Sections in addition to the +original versions of these Invariant Sections. You may include a +translation of this License, and all the license notices in the +Document, and any Warranty Disclaimers, provided that you also include +the original English version of this License and the original versions +of those notices and disclaimers. In case of a disagreement between +the translation and the original version of this License or a notice +or disclaimer, the original version will prevail. + +If a section in the Document is Entitled ``Acknowledgements'', +``Dedications'', or ``History'', the requirement (section 4) to Preserve +its Title (section 1) will typically require changing the actual +title. + +@item +TERMINATION + +You may not copy, modify, sublicense, or distribute the Document except +as expressly provided for under this License. Any other attempt to +copy, modify, sublicense or distribute the Document is void, and will +automatically terminate your rights under this License. However, +parties who have received copies, or rights, from you under this +License will not have their licenses terminated so long as such +parties remain in full compliance. + +@item +FUTURE REVISIONS OF THIS LICENSE + +The Free Software Foundation may publish new, revised versions +of the GNU Free Documentation License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. See +@uref{http://www.gnu.org/copyleft/}. + +Each version of the License is given a distinguishing version number. +If the Document specifies that a particular numbered version of this +License ``or any later version'' applies to it, you have the option of +following the terms and conditions either of that specified version or +of any later version that has been published (not as a draft) by the +Free Software Foundation. If the Document does not specify a version +number of this License, you may choose any version ever published (not +as a draft) by the Free Software Foundation. +@end enumerate + +@page +@appendixsubsec ADDENDUM: How to use this License for your documents + +To use this License in a document you have written, include a copy of +the License in the document and put the following copyright and +license notices just after the title page: + +@smallexample +@group + Copyright (C) @var{year} @var{your name}. + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.2 + or any later version published by the Free Software Foundation; + with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. + A copy of the license is included in the section entitled ``GNU + Free Documentation License''. +@end group +@end smallexample + +If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, +replace the ``with...Texts.'' line with this: + +@smallexample +@group + with the Invariant Sections being @var{list their titles}, with + the Front-Cover Texts being @var{list}, and with the Back-Cover Texts + being @var{list}. +@end group +@end smallexample + +If you have Invariant Sections without Cover Texts, or some other +combination of the three, merge those two alternatives to suit the +situation. + +If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, +to permit their use in free software. + +@c Local Variables: +@c ispell-local-pdict: "ispell-dict" +@c End: + diff --git a/external/gpl3/gdb/dist/readline/doc/history.3 b/external/gpl3/gdb/dist/readline/doc/history.3 new file mode 100644 index 000000000000..3ade839ff7d5 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/history.3 @@ -0,0 +1,663 @@ +.\" +.\" MAN PAGE COMMENTS to +.\" +.\" Chet Ramey +.\" Information Network Services +.\" Case Western Reserve University +.\" chet@ins.CWRU.Edu +.\" +.\" Last Change: Thu Jul 31 08:46:08 EDT 2003 +.\" +.TH HISTORY 3 "2003 July 31" "GNU History 5.0" +.\" +.\" File Name macro. This used to be `.PN', for Path Name, +.\" but Sun doesn't seem to like that very much. +.\" +.de FN +\fI\|\\$1\|\fP +.. +.ds lp \fR\|(\fP +.ds rp \fR\|)\fP +.\" FnN return-value fun-name N arguments +.de Fn1 +\fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3\fP\\*(rp +.br +.. +.de Fn2 +.if t \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3,\|\\$4\fP\\*(rp +.if n \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3, \\$4\fP\\*(rp +.br +.. +.de Fn3 +.if t \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3,\|\\$4,\|\\$5\fP\|\\*(rp +.if n \fI\\$1\fP \fB\\$2\fP \\*(lp\fI\\$3, \\$4, \\$5\fP\\*(rp +.br +.. +.de Vb +\fI\\$1\fP \fB\\$2\fP +.br +.. +.SH NAME +history \- GNU History Library +.SH COPYRIGHT +.if t The GNU History Library is Copyright \(co 1989-2002 by the Free Software Foundation, Inc. +.if n The GNU History Library is Copyright (C) 1989-2002 by the Free Software Foundation, Inc. +.SH DESCRIPTION +Many programs read input from the user a line at a time. The GNU +History library is able to keep track of those lines, associate arbitrary +data with each line, and utilize information from previous lines in +composing new ones. +.PP +.SH "HISTORY EXPANSION" +.PP +The history library supports a history expansion feature that +is identical to the history expansion in +.BR bash. +This section describes what syntax features are available. +.PP +History expansions introduce words from the history list into +the input stream, making it easy to repeat commands, insert the +arguments to a previous command into the current input line, or +fix errors in previous commands quickly. +.PP +History expansion is usually performed immediately after a complete line +is read. +It takes place in two parts. +The first is to determine which line from the history list +to use during substitution. +The second is to select portions of that line for inclusion into +the current one. +The line selected from the history is the \fIevent\fP, +and the portions of that line that are acted upon are \fIwords\fP. +Various \fImodifiers\fP are available to manipulate the selected words. +The line is broken into words in the same fashion as \fBbash\fP +does when reading input, +so that several words that would otherwise be separated +are considered one word when surrounded by quotes (see the +description of \fBhistory_tokenize()\fP below). +History expansions are introduced by the appearance of the +history expansion character, which is \^\fB!\fP\^ by default. +Only backslash (\^\fB\e\fP\^) and single quotes can quote +the history expansion character. +.SS Event Designators +.PP +An event designator is a reference to a command line entry in the +history list. +.PP +.PD 0 +.TP +.B ! +Start a history substitution, except when followed by a +.BR blank , +newline, = or (. +.TP +.B !\fIn\fR +Refer to command line +.IR n . +.TP +.B !\-\fIn\fR +Refer to the current command line minus +.IR n . +.TP +.B !! +Refer to the previous command. This is a synonym for `!\-1'. +.TP +.B !\fIstring\fR +Refer to the most recent command starting with +.IR string . +.TP +.B !?\fIstring\fR\fB[?]\fR +Refer to the most recent command containing +.IR string . +The trailing \fB?\fP may be omitted if +.I string +is followed immediately by a newline. +.TP +.B \d\s+2^\s-2\u\fIstring1\fP\d\s+2^\s-2\u\fIstring2\fP\d\s+2^\s-2\u +Quick substitution. Repeat the last command, replacing +.I string1 +with +.IR string2 . +Equivalent to +``!!:s/\fIstring1\fP/\fIstring2\fP/'' +(see \fBModifiers\fP below). +.TP +.B !# +The entire command line typed so far. +.PD +.SS Word Designators +.PP +Word designators are used to select desired words from the event. +A +.B : +separates the event specification from the word designator. +It may be omitted if the word designator begins with a +.BR ^ , +.BR $ , +.BR * , +.BR \- , +or +.BR % . +Words are numbered from the beginning of the line, +with the first word being denoted by 0 (zero). +Words are inserted into the current line separated by single spaces. +.PP +.PD 0 +.TP +.B 0 (zero) +The zeroth word. For the shell, this is the command +word. +.TP +.I n +The \fIn\fRth word. +.TP +.B ^ +The first argument. That is, word 1. +.TP +.B $ +The last argument. +.TP +.B % +The word matched by the most recent `?\fIstring\fR?' search. +.TP +.I x\fB\-\fPy +A range of words; `\-\fIy\fR' abbreviates `0\-\fIy\fR'. +.TP +.B * +All of the words but the zeroth. This is a synonym +for `\fI1\-$\fP'. It is not an error to use +.B * +if there is just one +word in the event; the empty string is returned in that case. +.TP +.B x* +Abbreviates \fIx\-$\fP. +.TP +.B x\- +Abbreviates \fIx\-$\fP like \fBx*\fP, but omits the last word. +.PD +.PP +If a word designator is supplied without an event specification, the +previous command is used as the event. +.SS Modifiers +.PP +After the optional word designator, there may appear a sequence of +one or more of the following modifiers, each preceded by a `:'. +.PP +.PD 0 +.PP +.TP +.B h +Remove a trailing file name component, leaving only the head. +.TP +.B t +Remove all leading file name components, leaving the tail. +.TP +.B r +Remove a trailing suffix of the form \fI.xxx\fP, leaving the +basename. +.TP +.B e +Remove all but the trailing suffix. +.TP +.B p +Print the new command but do not execute it. +.TP +.B q +Quote the substituted words, escaping further substitutions. +.TP +.B x +Quote the substituted words as with +.BR q , +but break into words at +.B blanks +and newlines. +.TP +.B s/\fIold\fP/\fInew\fP/ +Substitute +.I new +for the first occurrence of +.I old +in the event line. Any delimiter can be used in place of /. The +final delimiter is optional if it is the last character of the +event line. The delimiter may be quoted in +.I old +and +.I new +with a single backslash. If & appears in +.IR new , +it is replaced by +.IR old . +A single backslash will quote the &. If +.I old +is null, it is set to the last +.I old +substituted, or, if no previous history substitutions took place, +the last +.I string +in a +.B !?\fIstring\fR\fB[?]\fR +search. +.TP +.B & +Repeat the previous substitution. +.TP +.B g +Cause changes to be applied over the entire event line. This is +used in conjunction with `\fB:s\fP' (e.g., `\fB:gs/\fIold\fP/\fInew\fP/\fR') +or `\fB:&\fP'. If used with +`\fB:s\fP', any delimiter can be used +in place of /, and the final delimiter is optional +if it is the last character of the event line. +An \fBa\fP may be used as a synonym for \fBg\fP. +.TP +.B G +Apply the following `\fBs\fP' modifier once to each word in the event line. +.PD +.SH "PROGRAMMING WITH HISTORY FUNCTIONS" +This section describes how to use the History library in other programs. +.SS Introduction to History +.PP +The programmer using the History library has available functions +for remembering lines on a history list, associating arbitrary data +with a line, removing lines from the list, searching through the list +for a line containing an arbitrary text string, and referencing any line +in the list directly. In addition, a history \fIexpansion\fP function +is available which provides for a consistent user interface across +different programs. +.PP +The user using programs written with the History library has the +benefit of a consistent user interface with a set of well-known +commands for manipulating the text of previous lines and using that text +in new commands. The basic history manipulation commands are +identical to +the history substitution provided by \fBbash\fP. +.PP +If the programmer desires, he can use the Readline library, which +includes some history manipulation by default, and has the added +advantage of command line editing. +.PP +Before declaring any functions using any functionality the History +library provides in other code, an application writer should include +the file +.FN +in any file that uses the +History library's features. It supplies extern declarations for all +of the library's public functions and variables, and declares all of +the public data structures. + +.SS History Storage +.PP +The history list is an array of history entries. A history entry is +declared as follows: +.PP +.Vb "typedef void *" histdata_t; +.PP +.nf +typedef struct _hist_entry { + char *line; + char *timestamp; + histdata_t data; +} HIST_ENTRY; +.fi +.PP +The history list itself might therefore be declared as +.PP +.Vb "HIST_ENTRY **" the_history_list; +.PP +The state of the History library is encapsulated into a single structure: +.PP +.nf +/* + * A structure used to pass around the current state of the history. + */ +typedef struct _hist_state { + HIST_ENTRY **entries; /* Pointer to the entries themselves. */ + int offset; /* The location pointer within this array. */ + int length; /* Number of elements within this array. */ + int size; /* Number of slots allocated to this array. */ + int flags; +} HISTORY_STATE; +.fi +.PP +If the flags member includes \fBHS_STIFLED\fP, the history has been +stifled. +.SH "History Functions" +.PP +This section describes the calling sequence for the various functions +exported by the GNU History library. +.SS Initializing History and State Management +This section describes functions used to initialize and manage +the state of the History library when you want to use the history +functions in your program. + +.Fn1 void using_history void +Begin a session in which the history functions might be used. This +initializes the interactive variables. + +.Fn1 "HISTORY_STATE *" history_get_history_state void +Return a structure describing the current state of the input history. + +.Fn1 void history_set_history_state "HISTORY_STATE *state" +Set the state of the history list according to \fIstate\fP. + +.SS History List Management + +These functions manage individual entries on the history list, or set +parameters managing the list itself. + +.Fn1 void add_history "const char *string" +Place \fIstring\fP at the end of the history list. The associated data +field (if any) is set to \fBNULL\fP. + +.Fn1 void add_history_time "const char *string" +Change the time stamp associated with the most recent history entry to +\fIstring\fP. + +.Fn1 "HIST_ENTRY *" remove_history "int which" +Remove history entry at offset \fIwhich\fP from the history. The +removed element is returned so you can free the line, data, +and containing structure. + +.Fn1 "histdata_t" free_history_entry "HIST_ENTRY *histent" +Free the history entry \fIhistent\fP and any history library private +data associated with it. Returns the application-specific data +so the caller can dispose of it. + +.Fn3 "HIST_ENTRY *" replace_history_entry "int which" "const char *line" "histdata_t data" +Make the history entry at offset \fIwhich\fP have \fIline\fP and \fIdata\fP. +This returns the old entry so the caller can dispose of any +application-specific data. In the case +of an invalid \fIwhich\fP, a \fBNULL\fP pointer is returned. + +.Fn1 void clear_history "void" +Clear the history list by deleting all the entries. + +.Fn1 void stifle_history "int max" +Stifle the history list, remembering only the last \fImax\fP entries. + +.Fn1 int unstifle_history "void" +Stop stifling the history. This returns the previously-set +maximum number of history entries (as set by \fBstifle_history()\fP). +history was stifled. The value is positive if the history was +stifled, negative if it wasn't. + +.Fn1 int history_is_stifled "void" +Returns non-zero if the history is stifled, zero if it is not. + +.SS Information About the History List + +These functions return information about the entire history list or +individual list entries. + +.Fn1 "HIST_ENTRY **" history_list "void" +Return a \fBNULL\fP terminated array of \fIHIST_ENTRY *\fP which is the +current input history. Element 0 of this list is the beginning of time. +If there is no history, return \fBNULL\fP. + +.Fn1 int where_history "void" +Returns the offset of the current history element. + +.Fn1 "HIST_ENTRY *" current_history "void" +Return the history entry at the current position, as determined by +\fBwhere_history()\fP. If there is no entry there, return a \fBNULL\fP +pointer. + +.Fn1 "HIST_ENTRY *" history_get "int offset" +Return the history entry at position \fIoffset\fP, starting from +\fBhistory_base\fP. +If there is no entry there, or if \fIoffset\fP +is greater than the history length, return a \fBNULL\fP pointer. + +.Fn1 "time_t" history_get_time "HIST_ENTRY *" +Return the time stamp associated with the history entry passed as the argument. + +.Fn1 int history_total_bytes "void" +Return the number of bytes that the primary history entries are using. +This function returns the sum of the lengths of all the lines in the +history. + +.SS Moving Around the History List + +These functions allow the current index into the history list to be +set or changed. + +.Fn1 int history_set_pos "int pos" +Set the current history offset to \fIpos\fP, an absolute index +into the list. +Returns 1 on success, 0 if \fIpos\fP is less than zero or greater +than the number of history entries. + +.Fn1 "HIST_ENTRY *" previous_history "void" +Back up the current history offset to the previous history entry, and +return a pointer to that entry. If there is no previous entry, return +a \fBNULL\fP pointer. + +.Fn1 "HIST_ENTRY *" next_history "void" +Move the current history offset forward to the next history entry, and +return the a pointer to that entry. If there is no next entry, return +a \fBNULL\fP pointer. + +.SS Searching the History List + +These functions allow searching of the history list for entries containing +a specific string. Searching may be performed both forward and backward +from the current history position. The search may be \fIanchored\fP, +meaning that the string must match at the beginning of the history entry. + +.Fn2 int history_search "const char *string" "int direction" +Search the history for \fIstring\fP, starting at the current history offset. +If \fIdirection\fP is less than 0, then the search is through +previous entries, otherwise through subsequent entries. +If \fIstring\fP is found, then +the current history index is set to that history entry, and the value +returned is the offset in the line of the entry where +\fIstring\fP was found. Otherwise, nothing is changed, and a -1 is +returned. + +.Fn2 int history_search_prefix "const char *string" "int direction" +Search the history for \fIstring\fP, starting at the current history +offset. The search is anchored: matching lines must begin with +\fIstring\fP. If \fIdirection\fP is less than 0, then the search is +through previous entries, otherwise through subsequent entries. +If \fIstring\fP is found, then the +current history index is set to that entry, and the return value is 0. +Otherwise, nothing is changed, and a -1 is returned. + +.Fn3 int history_search_pos "const char *string" "int direction" "int pos" +Search for \fIstring\fP in the history list, starting at \fIpos\fP, an +absolute index into the list. If \fIdirection\fP is negative, the search +proceeds backward from \fIpos\fP, otherwise forward. Returns the absolute +index of the history element where \fIstring\fP was found, or -1 otherwise. + +.SS Managing the History File +The History library can read the history from and write it to a file. +This section documents the functions for managing a history file. + +.Fn1 int read_history "const char *filename" +Add the contents of \fIfilename\fP to the history list, a line at a time. +If \fIfilename\fP is \fBNULL\fP, then read from \fI~/.history\fP. +Returns 0 if successful, or \fBerrno\fP if not. + +.Fn3 int read_history_range "const char *filename" "int from" "int to" +Read a range of lines from \fIfilename\fP, adding them to the history list. +Start reading at line \fIfrom\fP and end at \fIto\fP. +If \fIfrom\fP is zero, start at the beginning. If \fIto\fP is less than +\fIfrom\fP, then read until the end of the file. If \fIfilename\fP is +\fBNULL\fP, then read from \fI~/.history\fP. Returns 0 if successful, +or \fBerrno\fP if not. + +.Fn1 int write_history "const char *filename" +Write the current history to \fIfilename\fP, overwriting \fIfilename\fP +if necessary. +If \fIfilename\fP is \fBNULL\fP, then write the history list to \fI~/.history\fP. +Returns 0 on success, or \fBerrno\fP on a read or write error. + + +.Fn2 int append_history "int nelements" "const char *filename" +Append the last \fInelements\fP of the history list to \fIfilename\fP. +If \fIfilename\fP is \fBNULL\fP, then append to \fI~/.history\fP. +Returns 0 on success, or \fBerrno\fP on a read or write error. + +.Fn2 int history_truncate_file "const char *filename" "int nlines" +Truncate the history file \fIfilename\fP, leaving only the last +\fInlines\fP lines. +If \fIfilename\fP is \fBNULL\fP, then \fI~/.history\fP is truncated. +Returns 0 on success, or \fBerrno\fP on failure. + +.SS History Expansion + +These functions implement history expansion. + +.Fn2 int history_expand "char *string" "char **output" +Expand \fIstring\fP, placing the result into \fIoutput\fP, a pointer +to a string. Returns: +.RS +.PD 0 +.TP +0 +If no expansions took place (or, if the only change in +the text was the removal of escape characters preceding the history expansion +character); +.TP +1 +if expansions did take place; +.TP +-1 +if there was an error in expansion; +.TP +2 +if the returned line should be displayed, but not executed, +as with the \fB:p\fP modifier. +.PD +.RE +If an error ocurred in expansion, then \fIoutput\fP contains a descriptive +error message. + +.Fn3 "char *" get_history_event "const char *string" "int *cindex" "int qchar" +Returns the text of the history event beginning at \fIstring\fP + +\fI*cindex\fP. \fI*cindex\fP is modified to point to after the event +specifier. At function entry, \fIcindex\fP points to the index into +\fIstring\fP where the history event specification begins. \fIqchar\fP +is a character that is allowed to end the event specification in addition +to the ``normal'' terminating characters. + +.Fn1 "char **" history_tokenize "const char *string" +Return an array of tokens parsed out of \fIstring\fP, much as the +shell might. +The tokens are split on the characters in the +\fBhistory_word_delimiters\fP variable, +and shell quoting conventions are obeyed. + +.Fn3 "char *" history_arg_extract "int first" "int last" "const char *string" +Extract a string segment consisting of the \fIfirst\fP through \fIlast\fP +arguments present in \fIstring\fP. Arguments are split using +\fBhistory_tokenize()\fP. + +.SS History Variables + +This section describes the externally-visible variables exported by +the GNU History Library. + +.Vb int history_base +The logical offset of the first entry in the history list. + +.Vb int history_length +The number of entries currently stored in the history list. + +.Vb int history_max_entries +The maximum number of history entries. This must be changed using +\fBstifle_history()\fP. + +.Vb int history_write_timestamps +If non-zero, timestamps are written to the history file, so they can be +preserved between sessions. The default value is 0, meaning that +timestamps are not saved. + +.Vb char history_expansion_char +The character that introduces a history event. The default is \fB!\fP. +Setting this to 0 inhibits history expansion. + +.Vb char history_subst_char +The character that invokes word substitution if found at the start of +a line. The default is \fB^\fP. + +.Vb char history_comment_char +During tokenization, if this character is seen as the first character +of a word, then it and all subsequent characters up to a newline are +ignored, suppressing history expansion for the remainder of the line. +This is disabled by default. + +.Vb "char *" history_word_delimiters +The characters that separate tokens for \fBhistory_tokenize()\fP. +The default value is \fB"\ \et\en()<>;&|"\fP. + +.Vb "char *" history_no_expand_chars +The list of characters which inhibit history expansion if found immediately +following \fBhistory_expansion_char\fP. The default is space, tab, newline, +\fB\er\fP, and \fB=\fP. + +.Vb "char *" history_search_delimiter_chars +The list of additional characters which can delimit a history search +string, in addition to space, tab, \fI:\fP and \fI?\fP in the case of +a substring search. The default is empty. + +.Vb int history_quotes_inhibit_expansion +If non-zero, single-quoted words are not scanned for the history expansion +character. The default value is 0. + +.Vb "rl_linebuf_func_t *" history_inhibit_expansion_function +This should be set to the address of a function that takes two arguments: +a \fBchar *\fP (\fIstring\fP) +and an \fBint\fP index into that string (\fIi\fP). +It should return a non-zero value if the history expansion starting at +\fIstring[i]\fP should not be performed; zero if the expansion should +be done. +It is intended for use by applications like \fBbash\fP that use the history +expansion character for additional purposes. +By default, this variable is set to \fBNULL\fP. +.SH FILES +.PD 0 +.TP +.FN ~/.history +Default filename for reading and writing saved history +.PD +.SH "SEE ALSO" +.PD 0 +.TP +\fIThe Gnu Readline Library\fP, Brian Fox and Chet Ramey +.TP +\fIThe Gnu History Library\fP, Brian Fox and Chet Ramey +.TP +\fIbash\fP(1) +.TP +\fIreadline\fP(3) +.PD +.SH AUTHORS +Brian Fox, Free Software Foundation +.br +bfox@gnu.org +.PP +Chet Ramey, Case Western Reserve University +.br +chet@ins.CWRU.Edu +.SH BUG REPORTS +If you find a bug in the +.B history +library, you should report it. But first, you should +make sure that it really is a bug, and that it appears in the latest +version of the +.B history +library that you have. +.PP +Once you have determined that a bug actually exists, mail a +bug report to \fIbug\-readline\fP@\fIgnu.org\fP. +If you have a fix, you are welcome to mail that +as well! Suggestions and `philosophical' bug reports may be mailed +to \fPbug-readline\fP@\fIgnu.org\fP or posted to the Usenet +newsgroup +.BR gnu.bash.bug . +.PP +Comments and bug reports concerning +this manual page should be directed to +.IR chet@ins.CWRU.Edu . diff --git a/external/gpl3/gdb/dist/readline/doc/history.texi b/external/gpl3/gdb/dist/readline/doc/history.texi new file mode 100644 index 000000000000..f6a3d205167c --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/history.texi @@ -0,0 +1,104 @@ +\input texinfo @c -*-texinfo-*- +@c %**start of header (This is for running Texinfo on a region.) +@setfilename history.info +@settitle GNU History Library +@c %**end of header (This is for running Texinfo on a region.) + +@setchapternewpage odd + +@include version.texi + +@copying +This document describes the GNU History library +(version @value{VERSION}, @value{UPDATED}), +a programming tool that provides a consistent user interface for +recalling lines of previously typed input. + +Copyright @copyright{} 1988-2004 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. + +@quotation +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with the Front-Cover texts being ``A GNU Manual,'' +and with the Back-Cover Texts as in (a) below. A copy of the license is +included in the section entitled ``GNU Free Documentation License.'' + +(a) The FSF's Back-Cover Text is: ``You have freedom to copy and modify +this GNU Manual, like GNU software. Copies published by the Free +Software Foundation raise funds for GNU development.'' +@end quotation +@end copying + +@dircategory Libraries +@direntry +* History: (history). The GNU history library API. +@end direntry + +@titlepage +@title GNU History Library +@subtitle Edition @value{EDITION}, for @code{History Library} Version @value{VERSION}. +@subtitle @value{UPDATED-MONTH} +@author Chet Ramey, Case Western Reserve University +@author Brian Fox, Free Software Foundation + +@page + +@vskip 0pt plus 1filll +@insertcopying + +@sp 1 +Published by the Free Software Foundation @* +59 Temple Place, Suite 330, @* +Boston, MA 02111-1307 @* +USA @* + +@end titlepage + +@contents + +@ifnottex +@node Top +@top GNU History Library + +This document describes the GNU History library, a programming tool that +provides a consistent user interface for recalling lines of previously +typed input. + +@menu +* Using History Interactively:: GNU History User's Manual. +* Programming with GNU History:: GNU History Programmer's Manual. +* Copying This Manual:: Copying This Manual. +* Concept Index:: Index of concepts described in this manual. +* Function and Variable Index:: Index of externally visible functions + and variables. +@end menu +@end ifnottex + +@syncodeindex fn vr + +@include hsuser.texi +@include hstech.texi + +@node Copying This Manual +@appendix Copying This Manual + +@menu +* GNU Free Documentation License:: License for copying this manual. +@end menu + +@include fdl.texi + +@node Concept Index +@appendix Concept Index +@printindex cp + +@node Function and Variable Index +@appendix Function and Variable Index +@printindex vr + +@bye diff --git a/external/gpl3/gdb/dist/readline/doc/hstech.texi b/external/gpl3/gdb/dist/readline/doc/hstech.texi new file mode 100644 index 000000000000..4fdda5f1c9e5 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/hstech.texi @@ -0,0 +1,573 @@ +@ignore +This file documents the user interface to the GNU History library. + +Copyright (C) 1988-2002 Free Software Foundation, Inc. +Authored by Brian Fox and Chet Ramey. + +Permission is granted to make and distribute verbatim copies of this manual +provided the copyright notice and this permission notice are preserved on +all copies. + +Permission is granted to process this file through Tex and print the +results, provided the printed document carries copying permission notice +identical to this one except for the removal of this paragraph (this +paragraph not being relevant to the printed manual). + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that the +GNU Copyright statement is available to the distributee, and provided that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end ignore + +@node Programming with GNU History +@chapter Programming with GNU History + +This chapter describes how to interface programs that you write +with the @sc{gnu} History Library. +It should be considered a technical guide. +For information on the interactive use of @sc{gnu} History, @pxref{Using +History Interactively}. + +@menu +* Introduction to History:: What is the GNU History library for? +* History Storage:: How information is stored. +* History Functions:: Functions that you can use. +* History Variables:: Variables that control behaviour. +* History Programming Example:: Example of using the GNU History Library. +@end menu + +@node Introduction to History +@section Introduction to History + +Many programs read input from the user a line at a time. The @sc{gnu} +History library is able to keep track of those lines, associate arbitrary +data with each line, and utilize information from previous lines in +composing new ones. + +The programmer using the History library has available functions +for remembering lines on a history list, associating arbitrary data +with a line, removing lines from the list, searching through the list +for a line containing an arbitrary text string, and referencing any line +in the list directly. In addition, a history @dfn{expansion} function +is available which provides for a consistent user interface across +different programs. + +The user using programs written with the History library has the +benefit of a consistent user interface with a set of well-known +commands for manipulating the text of previous lines and using that text +in new commands. The basic history manipulation commands are similar to +the history substitution provided by @code{csh}. + +If the programmer desires, he can use the Readline library, which +includes some history manipulation by default, and has the added +advantage of command line editing. + +Before declaring any functions using any functionality the History +library provides in other code, an application writer should include +the file @code{} in any file that uses the +History library's features. It supplies extern declarations for all +of the library's public functions and variables, and declares all of +the public data structures. + +@node History Storage +@section History Storage + +The history list is an array of history entries. A history entry is +declared as follows: + +@example +typedef void *histdata_t; + +typedef struct _hist_entry @{ + char *line; + char *timestamp; + histdata_t data; +@} HIST_ENTRY; +@end example + +The history list itself might therefore be declared as + +@example +HIST_ENTRY **the_history_list; +@end example + +The state of the History library is encapsulated into a single structure: + +@example +/* + * A structure used to pass around the current state of the history. + */ +typedef struct _hist_state @{ + HIST_ENTRY **entries; /* Pointer to the entries themselves. */ + int offset; /* The location pointer within this array. */ + int length; /* Number of elements within this array. */ + int size; /* Number of slots allocated to this array. */ + int flags; +@} HISTORY_STATE; +@end example + +If the flags member includes @code{HS_STIFLED}, the history has been +stifled. + +@node History Functions +@section History Functions + +This section describes the calling sequence for the various functions +exported by the @sc{gnu} History library. + +@menu +* Initializing History and State Management:: Functions to call when you + want to use history in a + program. +* History List Management:: Functions used to manage the list + of history entries. +* Information About the History List:: Functions returning information about + the history list. +* Moving Around the History List:: Functions used to change the position + in the history list. +* Searching the History List:: Functions to search the history list + for entries containing a string. +* Managing the History File:: Functions that read and write a file + containing the history list. +* History Expansion:: Functions to perform csh-like history + expansion. +@end menu + +@node Initializing History and State Management +@subsection Initializing History and State Management + +This section describes functions used to initialize and manage +the state of the History library when you want to use the history +functions in your program. + +@deftypefun void using_history (void) +Begin a session in which the history functions might be used. This +initializes the interactive variables. +@end deftypefun + +@deftypefun {HISTORY_STATE *} history_get_history_state (void) +Return a structure describing the current state of the input history. +@end deftypefun + +@deftypefun void history_set_history_state (HISTORY_STATE *state) +Set the state of the history list according to @var{state}. +@end deftypefun + +@node History List Management +@subsection History List Management + +These functions manage individual entries on the history list, or set +parameters managing the list itself. + +@deftypefun void add_history (const char *string) +Place @var{string} at the end of the history list. The associated data +field (if any) is set to @code{NULL}. +@end deftypefun + +@deftypefun void add_history_time (const char *string) +Change the time stamp associated with the most recent history entry to +@var{string}. +@end deftypefun + +@deftypefun {HIST_ENTRY *} remove_history (int which) +Remove history entry at offset @var{which} from the history. The +removed element is returned so you can free the line, data, +and containing structure. +@end deftypefun + +@deftypefun {histdata_t} free_history_entry (HIST_ENTRY *histent) +Free the history entry @var{histent} and any history library private +data associated with it. Returns the application-specific data +so the caller can dispose of it. +@end deftypefun + +@deftypefun {HIST_ENTRY *} replace_history_entry (int which, const char *line, histdata_t data) +Make the history entry at offset @var{which} have @var{line} and @var{data}. +This returns the old entry so the caller can dispose of any +application-specific data. In the case +of an invalid @var{which}, a @code{NULL} pointer is returned. +@end deftypefun + +@deftypefun void clear_history (void) +Clear the history list by deleting all the entries. +@end deftypefun + +@deftypefun void stifle_history (int max) +Stifle the history list, remembering only the last @var{max} entries. +@end deftypefun + +@deftypefun int unstifle_history (void) +Stop stifling the history. This returns the previously-set +maximum number of history entries (as set by @code{stifle_history()}). +The value is positive if the history was +stifled, negative if it wasn't. +@end deftypefun + +@deftypefun int history_is_stifled (void) +Returns non-zero if the history is stifled, zero if it is not. +@end deftypefun + +@node Information About the History List +@subsection Information About the History List + +These functions return information about the entire history list or +individual list entries. + +@deftypefun {HIST_ENTRY **} history_list (void) +Return a @code{NULL} terminated array of @code{HIST_ENTRY *} which is the +current input history. Element 0 of this list is the beginning of time. +If there is no history, return @code{NULL}. +@end deftypefun + +@deftypefun int where_history (void) +Returns the offset of the current history element. +@end deftypefun + +@deftypefun {HIST_ENTRY *} current_history (void) +Return the history entry at the current position, as determined by +@code{where_history()}. If there is no entry there, return a @code{NULL} +pointer. +@end deftypefun + +@deftypefun {HIST_ENTRY *} history_get (int offset) +Return the history entry at position @var{offset}, starting from +@code{history_base} (@pxref{History Variables}). +If there is no entry there, or if @var{offset} +is greater than the history length, return a @code{NULL} pointer. +@end deftypefun + +@deftypefun time_t history_get_time (HIST_ENTRY *entry) +Return the time stamp associated with the history entry @var{entry}. +@end deftypefun + +@deftypefun int history_total_bytes (void) +Return the number of bytes that the primary history entries are using. +This function returns the sum of the lengths of all the lines in the +history. +@end deftypefun + +@node Moving Around the History List +@subsection Moving Around the History List + +These functions allow the current index into the history list to be +set or changed. + +@deftypefun int history_set_pos (int pos) +Set the current history offset to @var{pos}, an absolute index +into the list. +Returns 1 on success, 0 if @var{pos} is less than zero or greater +than the number of history entries. +@end deftypefun + +@deftypefun {HIST_ENTRY *} previous_history (void) +Back up the current history offset to the previous history entry, and +return a pointer to that entry. If there is no previous entry, return +a @code{NULL} pointer. +@end deftypefun + +@deftypefun {HIST_ENTRY *} next_history (void) +Move the current history offset forward to the next history entry, and +return the a pointer to that entry. If there is no next entry, return +a @code{NULL} pointer. +@end deftypefun + +@node Searching the History List +@subsection Searching the History List +@cindex History Searching + +These functions allow searching of the history list for entries containing +a specific string. Searching may be performed both forward and backward +from the current history position. The search may be @dfn{anchored}, +meaning that the string must match at the beginning of the history entry. +@cindex anchored search + +@deftypefun int history_search (const char *string, int direction) +Search the history for @var{string}, starting at the current history offset. +If @var{direction} is less than 0, then the search is through +previous entries, otherwise through subsequent entries. +If @var{string} is found, then +the current history index is set to that history entry, and the value +returned is the offset in the line of the entry where +@var{string} was found. Otherwise, nothing is changed, and a -1 is +returned. +@end deftypefun + +@deftypefun int history_search_prefix (const char *string, int direction) +Search the history for @var{string}, starting at the current history +offset. The search is anchored: matching lines must begin with +@var{string}. If @var{direction} is less than 0, then the search is +through previous entries, otherwise through subsequent entries. +If @var{string} is found, then the +current history index is set to that entry, and the return value is 0. +Otherwise, nothing is changed, and a -1 is returned. +@end deftypefun + +@deftypefun int history_search_pos (const char *string, int direction, int pos) +Search for @var{string} in the history list, starting at @var{pos}, an +absolute index into the list. If @var{direction} is negative, the search +proceeds backward from @var{pos}, otherwise forward. Returns the absolute +index of the history element where @var{string} was found, or -1 otherwise. +@end deftypefun + +@node Managing the History File +@subsection Managing the History File + +The History library can read the history from and write it to a file. +This section documents the functions for managing a history file. + +@deftypefun int read_history (const char *filename) +Add the contents of @var{filename} to the history list, a line at a time. +If @var{filename} is @code{NULL}, then read from @file{~/.history}. +Returns 0 if successful, or @code{errno} if not. +@end deftypefun + +@deftypefun int read_history_range (const char *filename, int from, int to) +Read a range of lines from @var{filename}, adding them to the history list. +Start reading at line @var{from} and end at @var{to}. +If @var{from} is zero, start at the beginning. If @var{to} is less than +@var{from}, then read until the end of the file. If @var{filename} is +@code{NULL}, then read from @file{~/.history}. Returns 0 if successful, +or @code{errno} if not. +@end deftypefun + +@deftypefun int write_history (const char *filename) +Write the current history to @var{filename}, overwriting @var{filename} +if necessary. +If @var{filename} is @code{NULL}, then write the history list to +@file{~/.history}. +Returns 0 on success, or @code{errno} on a read or write error. +@end deftypefun + +@deftypefun int append_history (int nelements, const char *filename) +Append the last @var{nelements} of the history list to @var{filename}. +If @var{filename} is @code{NULL}, then append to @file{~/.history}. +Returns 0 on success, or @code{errno} on a read or write error. +@end deftypefun + +@deftypefun int history_truncate_file (const char *filename, int nlines) +Truncate the history file @var{filename}, leaving only the last +@var{nlines} lines. +If @var{filename} is @code{NULL}, then @file{~/.history} is truncated. +Returns 0 on success, or @code{errno} on failure. +@end deftypefun + +@node History Expansion +@subsection History Expansion + +These functions implement history expansion. + +@deftypefun int history_expand (char *string, char **output) +Expand @var{string}, placing the result into @var{output}, a pointer +to a string (@pxref{History Interaction}). Returns: +@table @code +@item 0 +If no expansions took place (or, if the only change in +the text was the removal of escape characters preceding the history expansion +character); +@item 1 +if expansions did take place; +@item -1 +if there was an error in expansion; +@item 2 +if the returned line should be displayed, but not executed, +as with the @code{:p} modifier (@pxref{Modifiers}). +@end table + +If an error ocurred in expansion, then @var{output} contains a descriptive +error message. +@end deftypefun + +@deftypefun {char *} get_history_event (const char *string, int *cindex, int qchar) +Returns the text of the history event beginning at @var{string} + +@var{*cindex}. @var{*cindex} is modified to point to after the event +specifier. At function entry, @var{cindex} points to the index into +@var{string} where the history event specification begins. @var{qchar} +is a character that is allowed to end the event specification in addition +to the ``normal'' terminating characters. +@end deftypefun + +@deftypefun {char **} history_tokenize (const char *string) +Return an array of tokens parsed out of @var{string}, much as the +shell might. The tokens are split on the characters in the +@var{history_word_delimiters} variable, +and shell quoting conventions are obeyed. +@end deftypefun + +@deftypefun {char *} history_arg_extract (int first, int last, const char *string) +Extract a string segment consisting of the @var{first} through @var{last} +arguments present in @var{string}. Arguments are split using +@code{history_tokenize}. +@end deftypefun + +@node History Variables +@section History Variables + +This section describes the externally-visible variables exported by +the @sc{gnu} History Library. + +@deftypevar int history_base +The logical offset of the first entry in the history list. +@end deftypevar + +@deftypevar int history_length +The number of entries currently stored in the history list. +@end deftypevar + +@deftypevar int history_max_entries +The maximum number of history entries. This must be changed using +@code{stifle_history()}. +@end deftypevar + +@deftypevar int history_write_timestamps +If non-zero, timestamps are written to the history file, so they can be +preserved between sessions. The default value is 0, meaning that +timestamps are not saved. +@end deftypevar + +@deftypevar char history_expansion_char +The character that introduces a history event. The default is @samp{!}. +Setting this to 0 inhibits history expansion. +@end deftypevar + +@deftypevar char history_subst_char +The character that invokes word substitution if found at the start of +a line. The default is @samp{^}. +@end deftypevar + +@deftypevar char history_comment_char +During tokenization, if this character is seen as the first character +of a word, then it and all subsequent characters up to a newline are +ignored, suppressing history expansion for the remainder of the line. +This is disabled by default. +@end deftypevar + +@deftypevar {char *} history_word_delimiters +The characters that separate tokens for @code{history_tokenize()}. +The default value is @code{" \t\n()<>;&|"}. +@end deftypevar + +@deftypevar {char *} history_search_delimiter_chars +The list of additional characters which can delimit a history search +string, in addition to space, TAB, @samp{:} and @samp{?} in the case of +a substring search. The default is empty. +@end deftypevar + +@deftypevar {char *} history_no_expand_chars +The list of characters which inhibit history expansion if found immediately +following @var{history_expansion_char}. The default is space, tab, newline, +carriage return, and @samp{=}. +@end deftypevar + +@deftypevar int history_quotes_inhibit_expansion +If non-zero, single-quoted words are not scanned for the history expansion +character. The default value is 0. +@end deftypevar + +@deftypevar {rl_linebuf_func_t *} history_inhibit_expansion_function +This should be set to the address of a function that takes two arguments: +a @code{char *} (@var{string}) +and an @code{int} index into that string (@var{i}). +It should return a non-zero value if the history expansion starting at +@var{string[i]} should not be performed; zero if the expansion should +be done. +It is intended for use by applications like Bash that use the history +expansion character for additional purposes. +By default, this variable is set to @code{NULL}. +@end deftypevar + +@node History Programming Example +@section History Programming Example + +The following program demonstrates simple use of the @sc{gnu} History Library. + +@smallexample +#include +#include + +main (argc, argv) + int argc; + char **argv; +@{ + char line[1024], *t; + int len, done = 0; + + line[0] = 0; + + using_history (); + while (!done) + @{ + printf ("history$ "); + fflush (stdout); + t = fgets (line, sizeof (line) - 1, stdin); + if (t && *t) + @{ + len = strlen (t); + if (t[len - 1] == '\n') + t[len - 1] = '\0'; + @} + + if (!t) + strcpy (line, "quit"); + + if (line[0]) + @{ + char *expansion; + int result; + + result = history_expand (line, &expansion); + if (result) + fprintf (stderr, "%s\n", expansion); + + if (result < 0 || result == 2) + @{ + free (expansion); + continue; + @} + + add_history (expansion); + strncpy (line, expansion, sizeof (line) - 1); + free (expansion); + @} + + if (strcmp (line, "quit") == 0) + done = 1; + else if (strcmp (line, "save") == 0) + write_history ("history_file"); + else if (strcmp (line, "read") == 0) + read_history ("history_file"); + else if (strcmp (line, "list") == 0) + @{ + register HIST_ENTRY **the_list; + register int i; + + the_list = history_list (); + if (the_list) + for (i = 0; the_list[i]; i++) + printf ("%d: %s\n", i + history_base, the_list[i]->line); + @} + else if (strncmp (line, "delete", 6) == 0) + @{ + int which; + if ((sscanf (line + 6, "%d", &which)) == 1) + @{ + HIST_ENTRY *entry = remove_history (which); + if (!entry) + fprintf (stderr, "No such entry %d\n", which); + else + @{ + free (entry->line); + free (entry); + @} + @} + else + @{ + fprintf (stderr, "non-numeric arg given to `delete'\n"); + @} + @} + @} +@} +@end smallexample diff --git a/external/gpl3/gdb/dist/readline/doc/hsuser.texi b/external/gpl3/gdb/dist/readline/doc/hsuser.texi new file mode 100644 index 000000000000..6c8918331868 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/hsuser.texi @@ -0,0 +1,457 @@ +@ignore +This file documents the user interface to the GNU History library. + +Copyright (C) 1988-2002 Free Software Foundation, Inc. +Authored by Brian Fox and Chet Ramey. + +Permission is granted to make and distribute verbatim copies of this manual +provided the copyright notice and this permission notice are preserved on +all copies. + +Permission is granted to process this file through Tex and print the +results, provided the printed document carries copying permission notice +identical to this one except for the removal of this paragraph (this +paragraph not being relevant to the printed manual). + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that the +GNU Copyright statement is available to the distributee, and provided that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end ignore + +@node Using History Interactively +@chapter Using History Interactively + +@ifclear BashFeatures +@defcodeindex bt +@end ifclear + +@ifset BashFeatures +This chapter describes how to use the @sc{gnu} History Library +interactively, from a user's standpoint. +It should be considered a user's guide. +For information on using the @sc{gnu} History Library in other programs, +see the @sc{gnu} Readline Library Manual. +@end ifset +@ifclear BashFeatures +This chapter describes how to use the @sc{gnu} History Library interactively, +from a user's standpoint. It should be considered a user's guide. For +information on using the @sc{gnu} History Library in your own programs, +@pxref{Programming with GNU History}. +@end ifclear + +@ifset BashFeatures +@menu +* Bash History Facilities:: How Bash lets you manipulate your command + history. +* Bash History Builtins:: The Bash builtin commands that manipulate + the command history. +* History Interaction:: What it feels like using History as a user. +@end menu +@end ifset +@ifclear BashFeatures +@menu +* History Interaction:: What it feels like using History as a user. +@end menu +@end ifclear + +@ifset BashFeatures +@node Bash History Facilities +@section Bash History Facilities +@cindex command history +@cindex history list + +When the @option{-o history} option to the @code{set} builtin +is enabled (@pxref{The Set Builtin}), +the shell provides access to the @dfn{command history}, +the list of commands previously typed. +The value of the @env{HISTSIZE} shell variable is used as the +number of commands to save in a history list. +The text of the last @env{$HISTSIZE} +commands (default 500) is saved. +The shell stores each command in the history list prior to +parameter and variable expansion +but after history expansion is performed, subject to the +values of the shell variables +@env{HISTIGNORE} and @env{HISTCONTROL}. + +When the shell starts up, the history is initialized from the +file named by the @env{HISTFILE} variable (default @file{~/.bash_history}). +The file named by the value of @env{HISTFILE} is truncated, if +necessary, to contain no more than the number of lines specified by +the value of the @env{HISTFILESIZE} variable. +When an interactive shell exits, the last +@env{$HISTSIZE} lines are copied from the history list to the file +named by @env{$HISTFILE}. +If the @code{histappend} shell option is set (@pxref{Bash Builtins}), +the lines are appended to the history file, +otherwise the history file is overwritten. +If @env{HISTFILE} +is unset, or if the history file is unwritable, the history is +not saved. After saving the history, the history file is truncated +to contain no more than @env{$HISTFILESIZE} +lines. If @env{HISTFILESIZE} is not set, no truncation is performed. + +If the @env{HISTTIMEFORMAT} is set, the time stamp information +associated with each history entry is written to the history file. + +The builtin command @code{fc} may be used to list or edit and re-execute +a portion of the history list. +The @code{history} builtin may be used to display or modify the history +list and manipulate the history file. +When using command-line editing, search commands +are available in each editing mode that provide access to the +history list (@pxref{Commands For History}). + +The shell allows control over which commands are saved on the history +list. The @env{HISTCONTROL} and @env{HISTIGNORE} +variables may be set to cause the shell to save only a subset of the +commands entered. +The @code{cmdhist} +shell option, if enabled, causes the shell to attempt to save each +line of a multi-line command in the same history entry, adding +semicolons where necessary to preserve syntactic correctness. +The @code{lithist} +shell option causes the shell to save the command with embedded newlines +instead of semicolons. +The @code{shopt} builtin is used to set these options. +@xref{Bash Builtins}, for a description of @code{shopt}. + +@node Bash History Builtins +@section Bash History Builtins +@cindex history builtins + +Bash provides two builtin commands which manipulate the +history list and history file. + +@table @code + +@item fc +@btindex fc +@example +@code{fc [-e @var{ename}] [-nlr] [@var{first}] [@var{last}]} +@code{fc -s [@var{pat}=@var{rep}] [@var{command}]} +@end example + +Fix Command. In the first form, a range of commands from @var{first} to +@var{last} is selected from the history list. Both @var{first} and +@var{last} may be specified as a string (to locate the most recent +command beginning with that string) or as a number (an index into the +history list, where a negative number is used as an offset from the +current command number). If @var{last} is not specified it is set to +@var{first}. If @var{first} is not specified it is set to the previous +command for editing and @minus{}16 for listing. If the @option{-l} flag is +given, the commands are listed on standard output. The @option{-n} flag +suppresses the command numbers when listing. The @option{-r} flag +reverses the order of the listing. Otherwise, the editor given by +@var{ename} is invoked on a file containing those commands. If +@var{ename} is not given, the value of the following variable expansion +is used: @code{$@{FCEDIT:-$@{EDITOR:-vi@}@}}. This says to use the +value of the @env{FCEDIT} variable if set, or the value of the +@env{EDITOR} variable if that is set, or @code{vi} if neither is set. +When editing is complete, the edited commands are echoed and executed. + +In the second form, @var{command} is re-executed after each instance +of @var{pat} in the selected command is replaced by @var{rep}. + +A useful alias to use with the @code{fc} command is @code{r='fc -s'}, so +that typing @samp{r cc} runs the last command beginning with @code{cc} +and typing @samp{r} re-executes the last command (@pxref{Aliases}). + +@item history +@btindex history +@example +history [@var{n}] +history -c +history -d @var{offset} +history [-anrw] [@var{filename}] +history -ps @var{arg} +@end example + +With no options, display the history list with line numbers. +Lines prefixed with a @samp{*} have been modified. +An argument of @var{n} lists only the last @var{n} lines. +If the shell variable @env{HISTTIMEFORMAT} is set and not null, +it is used as a format string for @var{strftime} to display +the time stamp associated with each displayed history entry. +No intervening blank is printed between the formatted time stamp +and the history line. + +Options, if supplied, have the following meanings: + +@table @code +@item -c +Clear the history list. This may be combined +with the other options to replace the history list completely. + +@item -d @var{offset} +Delete the history entry at position @var{offset}. +@var{offset} should be specified as it appears when the history is +displayed. + +@item -a +Append the new +history lines (history lines entered since the beginning of the +current Bash session) to the history file. + +@item -n +Append the history lines not already read from the history file +to the current history list. These are lines appended to the history +file since the beginning of the current Bash session. + +@item -r +Read the current history file and append its contents to +the history list. + +@item -w +Write out the current history to the history file. + +@item -p +Perform history substitution on the @var{arg}s and display the result +on the standard output, without storing the results in the history list. + +@item -s +The @var{arg}s are added to the end of +the history list as a single entry. + +@end table + +When any of the @option{-w}, @option{-r}, @option{-a}, or @option{-n} options is +used, if @var{filename} +is given, then it is used as the history file. If not, then +the value of the @env{HISTFILE} variable is used. + +@end table +@end ifset + +@node History Interaction +@section History Expansion +@cindex history expansion + +The History library provides a history expansion feature that is similar +to the history expansion provided by @code{csh}. This section +describes the syntax used to manipulate the history information. + +History expansions introduce words from the history list into +the input stream, making it easy to repeat commands, insert the +arguments to a previous command into the current input line, or +fix errors in previous commands quickly. + +History expansion takes place in two parts. The first is to determine +which line from the history list should be used during substitution. +The second is to select portions of that line for inclusion into the +current one. The line selected from the history is called the +@dfn{event}, and the portions of that line that are acted upon are +called @dfn{words}. Various @dfn{modifiers} are available to manipulate +the selected words. The line is broken into words in the same fashion +that Bash does, so that several words +surrounded by quotes are considered one word. +History expansions are introduced by the appearance of the +history expansion character, which is @samp{!} by default. +@ifset BashFeatures +Only @samp{\} and @samp{'} may be used to escape the history expansion +character. +@end ifset + +@ifset BashFeatures +Several shell options settable with the @code{shopt} +builtin (@pxref{Bash Builtins}) may be used to tailor +the behavior of history expansion. If the +@code{histverify} shell option is enabled, and Readline +is being used, history substitutions are not immediately passed to +the shell parser. +Instead, the expanded line is reloaded into the Readline +editing buffer for further modification. +If Readline is being used, and the @code{histreedit} +shell option is enabled, a failed history expansion will be +reloaded into the Readline editing buffer for correction. +The @option{-p} option to the @code{history} builtin command +may be used to see what a history expansion will do before using it. +The @option{-s} option to the @code{history} builtin may be used to +add commands to the end of the history list without actually executing +them, so that they are available for subsequent recall. +This is most useful in conjunction with Readline. + +The shell allows control of the various characters used by the +history expansion mechanism with the @code{histchars} variable. +@end ifset + +@menu +* Event Designators:: How to specify which history line to use. +* Word Designators:: Specifying which words are of interest. +* Modifiers:: Modifying the results of substitution. +@end menu + +@node Event Designators +@subsection Event Designators +@cindex event designators + +An event designator is a reference to a command line entry in the +history list. +@cindex history events + +@table @asis + +@item @code{!} +@ifset BashFeatures +Start a history substitution, except when followed by a space, tab, +the end of the line, @samp{=} or @samp{(} (when the +@code{extglob} shell option is enabled using the @code{shopt} builtin). +@end ifset +@ifclear BashFeatures +Start a history substitution, except when followed by a space, tab, +the end of the line, or @samp{=}. +@end ifclear + +@item @code{!@var{n}} +Refer to command line @var{n}. + +@item @code{!-@var{n}} +Refer to the command @var{n} lines back. + +@item @code{!!} +Refer to the previous command. This is a synonym for @samp{!-1}. + +@item @code{!@var{string}} +Refer to the most recent command starting with @var{string}. + +@item @code{!?@var{string}[?]} +Refer to the most recent command containing @var{string}. The trailing +@samp{?} may be omitted if the @var{string} is followed immediately by +a newline. + +@item @code{^@var{string1}^@var{string2}^} +Quick Substitution. Repeat the last command, replacing @var{string1} +with @var{string2}. Equivalent to +@code{!!:s/@var{string1}/@var{string2}/}. + +@item @code{!#} +The entire command line typed so far. + +@end table + +@node Word Designators +@subsection Word Designators + +Word designators are used to select desired words from the event. +A @samp{:} separates the event specification from the word designator. It +may be omitted if the word designator begins with a @samp{^}, @samp{$}, +@samp{*}, @samp{-}, or @samp{%}. Words are numbered from the beginning +of the line, with the first word being denoted by 0 (zero). Words are +inserted into the current line separated by single spaces. + +@need 0.75 +For example, + +@table @code +@item !! +designates the preceding command. When you type this, the preceding +command is repeated in toto. + +@item !!:$ +designates the last argument of the preceding command. This may be +shortened to @code{!$}. + +@item !fi:2 +designates the second argument of the most recent command starting with +the letters @code{fi}. +@end table + +@need 0.75 +Here are the word designators: + +@table @code + +@item 0 (zero) +The @code{0}th word. For many applications, this is the command word. + +@item @var{n} +The @var{n}th word. + +@item ^ +The first argument; that is, word 1. + +@item $ +The last argument. + +@item % +The word matched by the most recent @samp{?@var{string}?} search. + +@item @var{x}-@var{y} +A range of words; @samp{-@var{y}} abbreviates @samp{0-@var{y}}. + +@item * +All of the words, except the @code{0}th. This is a synonym for @samp{1-$}. +It is not an error to use @samp{*} if there is just one word in the event; +the empty string is returned in that case. + +@item @var{x}* +Abbreviates @samp{@var{x}-$} + +@item @var{x}- +Abbreviates @samp{@var{x}-$} like @samp{@var{x}*}, but omits the last word. + +@end table + +If a word designator is supplied without an event specification, the +previous command is used as the event. + +@node Modifiers +@subsection Modifiers + +After the optional word designator, you can add a sequence of one or more +of the following modifiers, each preceded by a @samp{:}. + +@table @code + +@item h +Remove a trailing pathname component, leaving only the head. + +@item t +Remove all leading pathname components, leaving the tail. + +@item r +Remove a trailing suffix of the form @samp{.@var{suffix}}, leaving +the basename. + +@item e +Remove all but the trailing suffix. + +@item p +Print the new command but do not execute it. + +@ifset BashFeatures +@item q +Quote the substituted words, escaping further substitutions. + +@item x +Quote the substituted words as with @samp{q}, +but break into words at spaces, tabs, and newlines. +@end ifset + +@item s/@var{old}/@var{new}/ +Substitute @var{new} for the first occurrence of @var{old} in the +event line. Any delimiter may be used in place of @samp{/}. +The delimiter may be quoted in @var{old} and @var{new} +with a single backslash. If @samp{&} appears in @var{new}, +it is replaced by @var{old}. A single backslash will quote +the @samp{&}. The final delimiter is optional if it is the last +character on the input line. + +@item & +Repeat the previous substitution. + +@item g +@itemx a +Cause changes to be applied over the entire event line. Used in +conjunction with @samp{s}, as in @code{gs/@var{old}/@var{new}/}, +or with @samp{&}. + +@item G +Apply the following @samp{s} modifier once to each word in the event. + +@end table diff --git a/external/gpl3/gdb/dist/readline/doc/inc-hist.texinfo b/external/gpl3/gdb/dist/readline/doc/inc-hist.texinfo new file mode 100644 index 000000000000..b5ed3cb48301 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/inc-hist.texinfo @@ -0,0 +1,457 @@ +@ignore +This file documents the user interface to the GNU History library. + +Copyright (C) 1988-2002 Free Software Foundation, Inc. +Authored by Brian Fox and Chet Ramey. + +Permission is granted to make and distribute verbatim copies of this manual +provided the copyright notice and this permission notice are preserved on +all copies. + +Permission is granted to process this file through Tex and print the +results, provided the printed document carries copying permission notice +identical to this one except for the removal of this paragraph (this +paragraph not being relevant to the printed manual). + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that the +GNU Copyright statement is available to the distributee, and provided that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end ignore + +@node Using History Interactively +@chapter Using History Interactively + +@c @ifclear BashFeatures +@c @defcodeindex bt +@c @end ifclear + +@ifset BashFeatures +This chapter describes how to use the @sc{gnu} History Library +interactively, from a user's standpoint. +It should be considered a user's guide. +For information on using the @sc{gnu} History Library in other programs, +see the @sc{gnu} Readline Library Manual. +@end ifset +@ifclear BashFeatures +This chapter describes how to use the @sc{gnu} History Library interactively, +from a user's standpoint. It should be considered a user's guide. +For information on using the @sc{gnu} History Library in other programs, +see the @sc{gnu} Readline Library Manual. +@end ifclear + +@ifset BashFeatures +@menu +* Bash History Facilities:: How Bash lets you manipulate your command + history. +* Bash History Builtins:: The Bash builtin commands that manipulate + the command history. +* History Interaction:: What it feels like using History as a user. +@end menu +@end ifset +@ifclear BashFeatures +@menu +* History Interaction:: What it feels like using History as a user. +@end menu +@end ifclear + +@ifset BashFeatures +@node Bash History Facilities +@section Bash History Facilities +@cindex command history +@cindex history list + +When the @option{-o history} option to the @code{set} builtin +is enabled (@pxref{The Set Builtin}), +the shell provides access to the @dfn{command history}, +the list of commands previously typed. +The value of the @env{HISTSIZE} shell variable is used as the +number of commands to save in a history list. +The text of the last @env{$HISTSIZE} +commands (default 500) is saved. +The shell stores each command in the history list prior to +parameter and variable expansion +but after history expansion is performed, subject to the +values of the shell variables +@env{HISTIGNORE} and @env{HISTCONTROL}. + +When the shell starts up, the history is initialized from the +file named by the @env{HISTFILE} variable (default @file{~/.bash_history}). +The file named by the value of @env{HISTFILE} is truncated, if +necessary, to contain no more than the number of lines specified by +the value of the @env{HISTFILESIZE} variable. +When an interactive shell exits, the last +@env{$HISTSIZE} lines are copied from the history list to the file +named by @env{$HISTFILE}. +If the @code{histappend} shell option is set (@pxref{Bash Builtins}), +the lines are appended to the history file, +otherwise the history file is overwritten. +If @env{HISTFILE} +is unset, or if the history file is unwritable, the history is +not saved. After saving the history, the history file is truncated +to contain no more than @env{$HISTFILESIZE} +lines. If @env{HISTFILESIZE} is not set, no truncation is performed. + +If the @env{HISTTIMEFORMAT} is set, the time stamp information +associated with each history entry is written to the history file. + +The builtin command @code{fc} may be used to list or edit and re-execute +a portion of the history list. +The @code{history} builtin may be used to display or modify the history +list and manipulate the history file. +When using command-line editing, search commands +are available in each editing mode that provide access to the +history list (@pxref{Commands For History}). + +The shell allows control over which commands are saved on the history +list. The @env{HISTCONTROL} and @env{HISTIGNORE} +variables may be set to cause the shell to save only a subset of the +commands entered. +The @code{cmdhist} +shell option, if enabled, causes the shell to attempt to save each +line of a multi-line command in the same history entry, adding +semicolons where necessary to preserve syntactic correctness. +The @code{lithist} +shell option causes the shell to save the command with embedded newlines +instead of semicolons. +The @code{shopt} builtin is used to set these options. +@xref{Bash Builtins}, for a description of @code{shopt}. + +@node Bash History Builtins +@section Bash History Builtins +@cindex history builtins + +Bash provides two builtin commands which manipulate the +history list and history file. + +@table @code + +@item fc +@btindex fc +@example +@code{fc [-e @var{ename}] [-nlr] [@var{first}] [@var{last}]} +@code{fc -s [@var{pat}=@var{rep}] [@var{command}]} +@end example + +Fix Command. In the first form, a range of commands from @var{first} to +@var{last} is selected from the history list. Both @var{first} and +@var{last} may be specified as a string (to locate the most recent +command beginning with that string) or as a number (an index into the +history list, where a negative number is used as an offset from the +current command number). If @var{last} is not specified it is set to +@var{first}. If @var{first} is not specified it is set to the previous +command for editing and @minus{}16 for listing. If the @option{-l} flag is +given, the commands are listed on standard output. The @option{-n} flag +suppresses the command numbers when listing. The @option{-r} flag +reverses the order of the listing. Otherwise, the editor given by +@var{ename} is invoked on a file containing those commands. If +@var{ename} is not given, the value of the following variable expansion +is used: @code{$@{FCEDIT:-$@{EDITOR:-vi@}@}}. This says to use the +value of the @env{FCEDIT} variable if set, or the value of the +@env{EDITOR} variable if that is set, or @code{vi} if neither is set. +When editing is complete, the edited commands are echoed and executed. + +In the second form, @var{command} is re-executed after each instance +of @var{pat} in the selected command is replaced by @var{rep}. + +A useful alias to use with the @code{fc} command is @code{r='fc -s'}, so +that typing @samp{r cc} runs the last command beginning with @code{cc} +and typing @samp{r} re-executes the last command (@pxref{Aliases}). + +@item history +@btindex history +@example +history [@var{n}] +history -c +history -d @var{offset} +history [-anrw] [@var{filename}] +history -ps @var{arg} +@end example + +With no options, display the history list with line numbers. +Lines prefixed with a @samp{*} have been modified. +An argument of @var{n} lists only the last @var{n} lines. +If the shell variable @env{HISTTIMEFORMAT} is set and not null, +it is used as a format string for @var{strftime} to display +the time stamp associated with each displayed history entry. +No intervening blank is printed between the formatted time stamp +and the history line. + +Options, if supplied, have the following meanings: + +@table @code +@item -c +Clear the history list. This may be combined +with the other options to replace the history list completely. + +@item -d @var{offset} +Delete the history entry at position @var{offset}. +@var{offset} should be specified as it appears when the history is +displayed. + +@item -a +Append the new +history lines (history lines entered since the beginning of the +current Bash session) to the history file. + +@item -n +Append the history lines not already read from the history file +to the current history list. These are lines appended to the history +file since the beginning of the current Bash session. + +@item -r +Read the current history file and append its contents to +the history list. + +@item -w +Write out the current history to the history file. + +@item -p +Perform history substitution on the @var{arg}s and display the result +on the standard output, without storing the results in the history list. + +@item -s +The @var{arg}s are added to the end of +the history list as a single entry. + +@end table + +When any of the @option{-w}, @option{-r}, @option{-a}, or @option{-n} options is +used, if @var{filename} +is given, then it is used as the history file. If not, then +the value of the @env{HISTFILE} variable is used. + +@end table +@end ifset + +@node History Interaction +@section History Expansion +@cindex history expansion + +The History library provides a history expansion feature that is similar +to the history expansion provided by @code{csh}. This section +describes the syntax used to manipulate the history information. + +History expansions introduce words from the history list into +the input stream, making it easy to repeat commands, insert the +arguments to a previous command into the current input line, or +fix errors in previous commands quickly. + +History expansion takes place in two parts. The first is to determine +which line from the history list should be used during substitution. +The second is to select portions of that line for inclusion into the +current one. The line selected from the history is called the +@dfn{event}, and the portions of that line that are acted upon are +called @dfn{words}. Various @dfn{modifiers} are available to manipulate +the selected words. The line is broken into words in the same fashion +that Bash does, so that several words +surrounded by quotes are considered one word. +History expansions are introduced by the appearance of the +history expansion character, which is @samp{!} by default. +@ifset BashFeatures +Only @samp{\} and @samp{'} may be used to escape the history expansion +character. +@end ifset + +@ifset BashFeatures +Several shell options settable with the @code{shopt} +builtin (@pxref{Bash Builtins}) may be used to tailor +the behavior of history expansion. If the +@code{histverify} shell option is enabled, and Readline +is being used, history substitutions are not immediately passed to +the shell parser. +Instead, the expanded line is reloaded into the Readline +editing buffer for further modification. +If Readline is being used, and the @code{histreedit} +shell option is enabled, a failed history expansion will be +reloaded into the Readline editing buffer for correction. +The @option{-p} option to the @code{history} builtin command +may be used to see what a history expansion will do before using it. +The @option{-s} option to the @code{history} builtin may be used to +add commands to the end of the history list without actually executing +them, so that they are available for subsequent recall. +This is most useful in conjunction with Readline. + +The shell allows control of the various characters used by the +history expansion mechanism with the @code{histchars} variable. +@end ifset + +@menu +* Event Designators:: How to specify which history line to use. +* Word Designators:: Specifying which words are of interest. +* Modifiers:: Modifying the results of substitution. +@end menu + +@node Event Designators +@subsection Event Designators +@cindex event designators + +An event designator is a reference to a command line entry in the +history list. +@cindex history events + +@table @asis + +@item @code{!} +@ifset BashFeatures +Start a history substitution, except when followed by a space, tab, +the end of the line, @samp{=} or @samp{(} (when the +@code{extglob} shell option is enabled using the @code{shopt} builtin). +@end ifset +@ifclear BashFeatures +Start a history substitution, except when followed by a space, tab, +the end of the line, or @samp{=}. +@end ifclear + +@item @code{!@var{n}} +Refer to command line @var{n}. + +@item @code{!-@var{n}} +Refer to the command @var{n} lines back. + +@item @code{!!} +Refer to the previous command. This is a synonym for @samp{!-1}. + +@item @code{!@var{string}} +Refer to the most recent command starting with @var{string}. + +@item @code{!?@var{string}[?]} +Refer to the most recent command containing @var{string}. The trailing +@samp{?} may be omitted if the @var{string} is followed immediately by +a newline. + +@item @code{^@var{string1}^@var{string2}^} +Quick Substitution. Repeat the last command, replacing @var{string1} +with @var{string2}. Equivalent to +@code{!!:s/@var{string1}/@var{string2}/}. + +@item @code{!#} +The entire command line typed so far. + +@end table + +@node Word Designators +@subsection Word Designators + +Word designators are used to select desired words from the event. +A @samp{:} separates the event specification from the word designator. It +may be omitted if the word designator begins with a @samp{^}, @samp{$}, +@samp{*}, @samp{-}, or @samp{%}. Words are numbered from the beginning +of the line, with the first word being denoted by 0 (zero). Words are +inserted into the current line separated by single spaces. + +@need 0.75 +For example, + +@table @code +@item !! +designates the preceding command. When you type this, the preceding +command is repeated in toto. + +@item !!:$ +designates the last argument of the preceding command. This may be +shortened to @code{!$}. + +@item !fi:2 +designates the second argument of the most recent command starting with +the letters @code{fi}. +@end table + +@need 0.75 +Here are the word designators: + +@table @code + +@item 0 (zero) +The @code{0}th word. For many applications, this is the command word. + +@item @var{n} +The @var{n}th word. + +@item ^ +The first argument; that is, word 1. + +@item $ +The last argument. + +@item % +The word matched by the most recent @samp{?@var{string}?} search. + +@item @var{x}-@var{y} +A range of words; @samp{-@var{y}} abbreviates @samp{0-@var{y}}. + +@item * +All of the words, except the @code{0}th. This is a synonym for @samp{1-$}. +It is not an error to use @samp{*} if there is just one word in the event; +the empty string is returned in that case. + +@item @var{x}* +Abbreviates @samp{@var{x}-$} + +@item @var{x}- +Abbreviates @samp{@var{x}-$} like @samp{@var{x}*}, but omits the last word. + +@end table + +If a word designator is supplied without an event specification, the +previous command is used as the event. + +@node Modifiers +@subsection Modifiers + +After the optional word designator, you can add a sequence of one or more +of the following modifiers, each preceded by a @samp{:}. + +@table @code + +@item h +Remove a trailing pathname component, leaving only the head. + +@item t +Remove all leading pathname components, leaving the tail. + +@item r +Remove a trailing suffix of the form @samp{.@var{suffix}}, leaving +the basename. + +@item e +Remove all but the trailing suffix. + +@item p +Print the new command but do not execute it. + +@ifset BashFeatures +@item q +Quote the substituted words, escaping further substitutions. + +@item x +Quote the substituted words as with @samp{q}, +but break into words at spaces, tabs, and newlines. +@end ifset + +@item s/@var{old}/@var{new}/ +Substitute @var{new} for the first occurrence of @var{old} in the +event line. Any delimiter may be used in place of @samp{/}. +The delimiter may be quoted in @var{old} and @var{new} +with a single backslash. If @samp{&} appears in @var{new}, +it is replaced by @var{old}. A single backslash will quote +the @samp{&}. The final delimiter is optional if it is the last +character on the input line. + +@item & +Repeat the previous substitution. + +@item g +@itemx a +Cause changes to be applied over the entire event line. Used in +conjunction with @samp{s}, as in @code{gs/@var{old}/@var{new}/}, +or with @samp{&}. + +@item G +Apply the following @samp{s} modifier once to each word in the event. + +@end table diff --git a/external/gpl3/gdb/dist/readline/doc/readline.3 b/external/gpl3/gdb/dist/readline/doc/readline.3 new file mode 100644 index 000000000000..90cd9971e8e9 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/readline.3 @@ -0,0 +1,1300 @@ +.\" +.\" MAN PAGE COMMENTS to +.\" +.\" Chet Ramey +.\" Information Network Services +.\" Case Western Reserve University +.\" chet@ins.CWRU.Edu +.\" +.\" Last Change: Tue Sep 13 12:07:26 EDT 2005 +.\" +.TH READLINE 3 "2005 Sep 13" "GNU Readline 5.1-beta1" +.\" +.\" File Name macro. This used to be `.PN', for Path Name, +.\" but Sun doesn't seem to like that very much. +.\" +.de FN +\fI\|\\$1\|\fP +.. +.SH NAME +readline \- get a line from a user with editing +.SH SYNOPSIS +.LP +.nf +.ft B +#include +#include +#include +.ft +.fi +.LP +.nf +\fIchar *\fP +.br +\fBreadline\fP (\fIconst char *prompt\fP); +.fi +.SH COPYRIGHT +.if n Readline is Copyright (C) 1989\-2004 by the Free Software Foundation, Inc. +.if t Readline is Copyright \(co 1989\-2004 by the Free Software Foundation, Inc. +.SH DESCRIPTION +.LP +.B readline +will read a line from the terminal +and return it, using +.B prompt +as a prompt. If +.B prompt +is \fBNULL\fP or the empty string, no prompt is issued. +The line returned is allocated with +.IR malloc (3); +the caller must free it when finished. The line returned +has the final newline removed, so only the text of the line +remains. +.LP +.B readline +offers editing capabilities while the user is entering the +line. +By default, the line editing commands +are similar to those of emacs. +A vi\-style line editing interface is also available. +.LP +This manual page describes only the most basic use of \fBreadline\fP. +Much more functionality is available; see +\fIThe GNU Readline Library\fP and \fIThe GNU History Library\fP +for additional information. +.SH RETURN VALUE +.LP +.B readline +returns the text of the line read. A blank line +returns the empty string. If +.B EOF +is encountered while reading a line, and the line is empty, +.B NULL +is returned. If an +.B EOF +is read with a non\-empty line, it is +treated as a newline. +.SH NOTATION +.LP +An emacs-style notation is used to denote +keystrokes. Control keys are denoted by C\-\fIkey\fR, e.g., C\-n +means Control\-N. Similarly, +.I meta +keys are denoted by M\-\fIkey\fR, so M\-x means Meta\-X. (On keyboards +without a +.I meta +key, M\-\fIx\fP means ESC \fIx\fP, i.e., press the Escape key +then the +.I x +key. This makes ESC the \fImeta prefix\fP. +The combination M\-C\-\fIx\fP means ESC\-Control\-\fIx\fP, +or press the Escape key +then hold the Control key while pressing the +.I x +key.) +.PP +Readline commands may be given numeric +.IR arguments , +which normally act as a repeat count. Sometimes, however, it is the +sign of the argument that is significant. Passing a negative argument +to a command that acts in the forward direction (e.g., \fBkill\-line\fP) +causes that command to act in a backward direction. Commands whose +behavior with arguments deviates from this are noted. +.PP +When a command is described as \fIkilling\fP text, the text +deleted is saved for possible future retrieval +(\fIyanking\fP). The killed text is saved in a +\fIkill ring\fP. Consecutive kills cause the text to be +accumulated into one unit, which can be yanked all at once. +Commands which do not kill text separate the chunks of text +on the kill ring. +.SH INITIALIZATION FILE +.LP +Readline is customized by putting commands in an initialization +file (the \fIinputrc\fP file). +The name of this file is taken from the value of the +.B INPUTRC +environment variable. If that variable is unset, the default is +.IR ~/.inputrc . +When a program which uses the readline library starts up, the +init file is read, and the key bindings and variables are set. +There are only a few basic constructs allowed in the +readline init file. Blank lines are ignored. +Lines beginning with a \fB#\fP are comments. +Lines beginning with a \fB$\fP indicate conditional constructs. +Other lines denote key bindings and variable settings. +Each program using this library may add its own commands +and bindings. +.PP +For example, placing +.RS +.PP +M\-Control\-u: universal\-argument +.RE +or +.RS +C\-Meta\-u: universal\-argument +.RE +.sp +into the +.I inputrc +would make M\-C\-u execute the readline command +.IR universal\-argument . +.PP +The following symbolic character names are recognized while +processing key bindings: +.IR DEL , +.IR ESC , +.IR ESCAPE , +.IR LFD , +.IR NEWLINE , +.IR RET , +.IR RETURN , +.IR RUBOUT , +.IR SPACE , +.IR SPC , +and +.IR TAB . +.PP +In addition to command names, readline allows keys to be bound +to a string that is inserted when the key is pressed (a \fImacro\fP). +.PP +.SS Key Bindings +.PP +The syntax for controlling key bindings in the +.I inputrc +file is simple. All that is required is the name of the +command or the text of a macro and a key sequence to which +it should be bound. The name may be specified in one of two ways: +as a symbolic key name, possibly with \fIMeta\-\fP or \fIControl\-\fP +prefixes, or as a key sequence. +.PP +When using the form \fBkeyname\fP:\^\fIfunction-name\fP or \fImacro\fP, +.I keyname +is the name of a key spelled out in English. For example: +.sp +.RS +Control\-u: universal\-argument +.br +Meta\-Rubout: backward\-kill\-word +.br +Control\-o: "> output" +.RE +.LP +In the above example, +.I C\-u +is bound to the function +.BR universal\-argument , +.I M-DEL +is bound to the function +.BR backward\-kill\-word , +and +.I C\-o +is bound to run the macro +expressed on the right hand side (that is, to insert the text +.if t \f(CW> output\fP +.if n ``> output'' +into the line). +.PP +In the second form, \fB"keyseq"\fP:\^\fIfunction\-name\fP or \fImacro\fP, +.B keyseq +differs from +.B keyname +above in that strings denoting +an entire key sequence may be specified by placing the sequence +within double quotes. Some GNU Emacs style key escapes can be +used, as in the following example, but the symbolic character names +are not recognized. +.sp +.RS +"\eC\-u": universal\-argument +.br +"\eC\-x\eC\-r": re\-read\-init\-file +.br +"\ee[11~": "Function Key 1" +.RE +.PP +In this example, +.I C-u +is again bound to the function +.BR universal\-argument . +.I "C-x C-r" +is bound to the function +.BR re\-read\-init\-file , +and +.I "ESC [ 1 1 ~" +is bound to insert the text +.if t \f(CWFunction Key 1\fP. +.if n ``Function Key 1''. +.PP +The full set of GNU Emacs style escape sequences available when specifying +key sequences is +.RS +.PD 0 +.TP +.B \eC\- +control prefix +.TP +.B \eM\- +meta prefix +.TP +.B \ee +an escape character +.TP +.B \e\e +backslash +.TP +.B \e" +literal ", a double quote +.TP +.B \e' +literal ', a single quote +.RE +.PD +.PP +In addition to the GNU Emacs style escape sequences, a second +set of backslash escapes is available: +.RS +.PD 0 +.TP +.B \ea +alert (bell) +.TP +.B \eb +backspace +.TP +.B \ed +delete +.TP +.B \ef +form feed +.TP +.B \en +newline +.TP +.B \er +carriage return +.TP +.B \et +horizontal tab +.TP +.B \ev +vertical tab +.TP +.B \e\fInnn\fP +the eight-bit character whose value is the octal value \fInnn\fP +(one to three digits) +.TP +.B \ex\fIHH\fP +the eight-bit character whose value is the hexadecimal value \fIHH\fP +(one or two hex digits) +.RE +.PD +.PP +When entering the text of a macro, single or double quotes should +be used to indicate a macro definition. Unquoted text +is assumed to be a function name. +In the macro body, the backslash escapes described above are expanded. +Backslash will quote any other character in the macro text, +including " and '. +.PP +.B Bash +allows the current readline key bindings to be displayed or modified +with the +.B bind +builtin command. The editing mode may be switched during interactive +use by using the +.B \-o +option to the +.B set +builtin command. Other programs using this library provide +similar mechanisms. The +.I inputrc +file may be edited and re-read if a program does not provide +any other means to incorporate new bindings. +.SS Variables +.PP +Readline has variables that can be used to further customize its +behavior. A variable may be set in the +.I inputrc +file with a statement of the form +.RS +.PP +\fBset\fP \fIvariable\-name\fP \fIvalue\fP +.RE +.PP +Except where noted, readline variables can take the values +.B On +or +.B Off +(without regard to case). +Unrecognized variable names are ignored. +When a variable value is read, empty or null values, "on" (case-insensitive), +and "1" are equivalent to \fBOn\fP. All other values are equivalent to +\fBOff\fP. +The variables and their default values are: +.PP +.PD 0 +.TP +.B bell\-style (audible) +Controls what happens when readline wants to ring the terminal bell. +If set to \fBnone\fP, readline never rings the bell. If set to +\fBvisible\fP, readline uses a visible bell if one is available. +If set to \fBaudible\fP, readline attempts to ring the terminal's bell. +.TP +.B bind\-tty\-special\-chars (On) +If set to \fBOn\fP, readline attempts to bind the control characters +treated specially by the kernel's terminal driver to their readline +equivalents. +.TP +.B comment\-begin (``#'') +The string that is inserted in \fBvi\fP mode when the +.B insert\-comment +command is executed. +This command is bound to +.B M\-# +in emacs mode and to +.B # +in vi command mode. +.TP +.B completion\-ignore\-case (Off) +If set to \fBOn\fP, readline performs filename matching and completion +in a case\-insensitive fashion. +.TP +.B completion\-query\-items (100) +This determines when the user is queried about viewing +the number of possible completions +generated by the \fBpossible\-completions\fP command. +It may be set to any integer value greater than or equal to +zero. If the number of possible completions is greater than +or equal to the value of this variable, the user is asked whether +or not he wishes to view them; otherwise they are simply listed +on the terminal. A negative value causes readline to never ask. +.TP +.B convert\-meta (On) +If set to \fBOn\fP, readline will convert characters with the +eighth bit set to an ASCII key sequence +by stripping the eighth bit and prefixing it with an +escape character (in effect, using escape as the \fImeta prefix\fP). +.TP +.B disable\-completion (Off) +If set to \fBOn\fP, readline will inhibit word completion. Completion +characters will be inserted into the line as if they had been +mapped to \fBself-insert\fP. +.TP +.B editing\-mode (emacs) +Controls whether readline begins with a set of key bindings similar +to emacs or vi. +.B editing\-mode +can be set to either +.B emacs +or +.BR vi . +.TP +.B enable\-keypad (Off) +When set to \fBOn\fP, readline will try to enable the application +keypad when it is called. Some systems need this to enable the +arrow keys. +.TP +.B expand\-tilde (Off) +If set to \fBon\fP, tilde expansion is performed when readline +attempts word completion. +.TP +.B history\-preserve\-point (Off) +If set to \fBon\fP, the history code attempts to place point at the +same location on each history line retrieved with \fBprevious-history\fP +or \fBnext-history\fP. +.TP +.B horizontal\-scroll\-mode (Off) +When set to \fBOn\fP, makes readline use a single line for display, +scrolling the input horizontally on a single screen line when it +becomes longer than the screen width rather than wrapping to a new line. +.TP +.B input\-meta (Off) +If set to \fBOn\fP, readline will enable eight-bit input (that is, +it will not clear the eighth bit in the characters it reads), +regardless of what the terminal claims it can support. The name +.B meta\-flag +is a synonym for this variable. +.TP +.B isearch\-terminators (``C\-[ C\-J'') +The string of characters that should terminate an incremental +search without subsequently executing the character as a command. +If this variable has not been given a value, the characters +\fIESC\fP and \fIC\-J\fP will terminate an incremental search. +.TP +.B keymap (emacs) +Set the current readline keymap. The set of legal keymap names is +\fIemacs, emacs-standard, emacs-meta, emacs-ctlx, vi, vi-move, +vi-command\fP, and +.IR vi-insert . +\fIvi\fP is equivalent to \fIvi-command\fP; \fIemacs\fP is +equivalent to \fIemacs-standard\fP. The default value is +.IR emacs . +The value of +.B editing\-mode +also affects the default keymap. +.TP +.B mark\-directories (On) +If set to \fBOn\fP, completed directory names have a slash +appended. +.TP +.B mark\-modified\-lines (Off) +If set to \fBOn\fP, history lines that have been modified are displayed +with a preceding asterisk (\fB*\fP). +.TP +.B mark\-symlinked\-directories (Off) +If set to \fBOn\fP, completed names which are symbolic links to directories +have a slash appended (subject to the value of +\fBmark\-directories\fP). +.TP +.B match\-hidden\-files (On) +This variable, when set to \fBOn\fP, causes readline to match files whose +names begin with a `.' (hidden files) when performing filename +completion, unless the leading `.' is +supplied by the user in the filename to be completed. +.TP +.B output\-meta (Off) +If set to \fBOn\fP, readline will display characters with the +eighth bit set directly rather than as a meta-prefixed escape +sequence. +.TP +.B page\-completions (On) +If set to \fBOn\fP, readline uses an internal \fImore\fP-like pager +to display a screenful of possible completions at a time. +.TP +.B print\-completions\-horizontally (Off) +If set to \fBOn\fP, readline will display completions with matches +sorted horizontally in alphabetical order, rather than down the screen. +.TP +.B show\-all\-if\-ambiguous (Off) +This alters the default behavior of the completion functions. If +set to +.BR on , +words which have more than one possible completion cause the +matches to be listed immediately instead of ringing the bell. +.TP +.B show\-all\-if\-unmodified (Off) +This alters the default behavior of the completion functions in +a fashion similar to \fBshow\-all\-if\-ambiguous\fP. +If set to +.BR on , +words which have more than one possible completion without any +possible partial completion (the possible completions don't share +a common prefix) cause the matches to be listed immediately instead +of ringing the bell. +.TP +.B visible\-stats (Off) +If set to \fBOn\fP, a character denoting a file's type as reported +by \fIstat\fP(2) is appended to the filename when listing possible +completions. +.PD +.SS Conditional Constructs +.PP +Readline implements a facility similar in spirit to the conditional +compilation features of the C preprocessor which allows key +bindings and variable settings to be performed as the result +of tests. There are four parser directives used. +.IP \fB$if\fP +The +.B $if +construct allows bindings to be made based on the +editing mode, the terminal being used, or the application using +readline. The text of the test extends to the end of the line; +no characters are required to isolate it. +.RS +.IP \fBmode\fP +The \fBmode=\fP form of the \fB$if\fP directive is used to test +whether readline is in emacs or vi mode. +This may be used in conjunction +with the \fBset keymap\fP command, for instance, to set bindings in +the \fIemacs-standard\fP and \fIemacs-ctlx\fP keymaps only if +readline is starting out in emacs mode. +.IP \fBterm\fP +The \fBterm=\fP form may be used to include terminal-specific +key bindings, perhaps to bind the key sequences output by the +terminal's function keys. The word on the right side of the +.B = +is tested against the full name of the terminal and the portion +of the terminal name before the first \fB\-\fP. This allows +.I sun +to match both +.I sun +and +.IR sun\-cmd , +for instance. +.IP \fBapplication\fP +The \fBapplication\fP construct is used to include +application-specific settings. Each program using the readline +library sets the \fIapplication name\fP, and an initialization +file can test for a particular value. +This could be used to bind key sequences to functions useful for +a specific program. For instance, the following command adds a +key sequence that quotes the current or previous word in Bash: +.sp 1 +.RS +.nf +\fB$if\fP Bash +# Quote the current or previous word +"\eC-xq": "\eeb\e"\eef\e"" +\fB$endif\fP +.fi +.RE +.RE +.IP \fB$endif\fP +This command, as seen in the previous example, terminates an +\fB$if\fP command. +.IP \fB$else\fP +Commands in this branch of the \fB$if\fP directive are executed if +the test fails. +.IP \fB$include\fP +This directive takes a single filename as an argument and reads commands +and bindings from that file. For example, the following directive +would read \fI/etc/inputrc\fP: +.sp 1 +.RS +.nf +\fB$include\fP \^ \fI/etc/inputrc\fP +.fi +.RE +.SH SEARCHING +.PP +Readline provides commands for searching through the command history +for lines containing a specified string. +There are two search modes: +.I incremental +and +.IR non-incremental . +.PP +Incremental searches begin before the user has finished typing the +search string. +As each character of the search string is typed, readline displays +the next entry from the history matching the string typed so far. +An incremental search requires only as many characters as needed to +find the desired history entry. +To search backward in the history for a particular string, type +\fBC\-r\fP. Typing \fBC\-s\fP searches forward through the history. +The characters present in the value of the \fBisearch-terminators\fP +variable are used to terminate an incremental search. +If that variable has not been assigned a value the \fIEscape\fP and +\fBC\-J\fP characters will terminate an incremental search. +\fBC\-G\fP will abort an incremental search and restore the original +line. +When the search is terminated, the history entry containing the +search string becomes the current line. +.PP +To find other matching entries in the history list, type \fBC\-s\fP or +\fBC\-r\fP as appropriate. +This will search backward or forward in the history for the next +line matching the search string typed so far. +Any other key sequence bound to a readline command will terminate +the search and execute that command. +For instance, a newline will terminate the search and accept +the line, thereby executing the command from the history list. +A movement command will terminate the search, make the last line found +the current line, and begin editing. +.PP +Non-incremental searches read the entire search string before starting +to search for matching history lines. The search string may be +typed by the user or be part of the contents of the current line. +.SH EDITING COMMANDS +.PP +The following is a list of the names of the commands and the default +key sequences to which they are bound. +Command names without an accompanying key sequence are unbound by default. +.PP +In the following descriptions, \fIpoint\fP refers to the current cursor +position, and \fImark\fP refers to a cursor position saved by the +\fBset\-mark\fP command. +The text between the point and mark is referred to as the \fIregion\fP. +.SS Commands for Moving +.PP +.PD 0 +.TP +.B beginning\-of\-line (C\-a) +Move to the start of the current line. +.TP +.B end\-of\-line (C\-e) +Move to the end of the line. +.TP +.B forward\-char (C\-f) +Move forward a character. +.TP +.B backward\-char (C\-b) +Move back a character. +.TP +.B forward\-word (M\-f) +Move forward to the end of the next word. Words are composed of +alphanumeric characters (letters and digits). +.TP +.B backward\-word (M\-b) +Move back to the start of the current or previous word. Words are +composed of alphanumeric characters (letters and digits). +.TP +.B clear\-screen (C\-l) +Clear the screen leaving the current line at the top of the screen. +With an argument, refresh the current line without clearing the +screen. +.TP +.B redraw\-current\-line +Refresh the current line. +.PD +.SS Commands for Manipulating the History +.PP +.PD 0 +.TP +.B accept\-line (Newline, Return) +Accept the line regardless of where the cursor is. +If this line is +non-empty, it may be added to the history list for future recall with +\fBadd_history()\fP. +If the line is a modified history line, the history line is restored to its original state. +.TP +.B previous\-history (C\-p) +Fetch the previous command from the history list, moving back in +the list. +.TP +.B next\-history (C\-n) +Fetch the next command from the history list, moving forward in the +list. +.TP +.B beginning\-of\-history (M\-<) +Move to the first line in the history. +.TP +.B end\-of\-history (M\->) +Move to the end of the input history, i.e., the line currently being +entered. +.TP +.B reverse\-search\-history (C\-r) +Search backward starting at the current line and moving `up' through +the history as necessary. This is an incremental search. +.TP +.B forward\-search\-history (C\-s) +Search forward starting at the current line and moving `down' through +the history as necessary. This is an incremental search. +.TP +.B non\-incremental\-reverse\-search\-history (M\-p) +Search backward through the history starting at the current line +using a non-incremental search for a string supplied by the user. +.TP +.B non\-incremental\-forward\-search\-history (M\-n) +Search forward through the history using a non-incremental search +for a string supplied by the user. +.TP +.B history\-search\-forward +Search forward through the history for the string of characters +between the start of the current line and the current cursor +position (the \fIpoint\fP). +This is a non-incremental search. +.TP +.B history\-search\-backward +Search backward through the history for the string of characters +between the start of the current line and the point. +This is a non-incremental search. +.TP +.B yank\-nth\-arg (M\-C\-y) +Insert the first argument to the previous command (usually +the second word on the previous line) at point. +With an argument +.IR n , +insert the \fIn\fPth word from the previous command (the words +in the previous command begin with word 0). A negative argument +inserts the \fIn\fPth word from the end of the previous command. +Once the argument \fIn\fP is computed, the argument is extracted +as if the "!\fIn\fP" history expansion had been specified. +.TP +.B +yank\-last\-arg (M\-.\^, M\-_\^) +Insert the last argument to the previous command (the last word of +the previous history entry). With an argument, +behave exactly like \fByank\-nth\-arg\fP. +Successive calls to \fByank\-last\-arg\fP move back through the history +list, inserting the last argument of each line in turn. +The history expansion facilities are used to extract the last argument, +as if the "!$" history expansion had been specified. +.PD +.SS Commands for Changing Text +.PP +.PD 0 +.TP +.B delete\-char (C\-d) +Delete the character at point. If point is at the +beginning of the line, there are no characters in the line, and +the last character typed was not bound to \fBdelete\-char\fP, then return +.SM +.BR EOF . +.TP +.B backward\-delete\-char (Rubout) +Delete the character behind the cursor. When given a numeric argument, +save the deleted text on the kill ring. +.TP +.B forward\-backward\-delete\-char +Delete the character under the cursor, unless the cursor is at the +end of the line, in which case the character behind the cursor is +deleted. +.TP +.B quoted\-insert (C\-q, C\-v) +Add the next character that you type to the line verbatim. This is +how to insert characters like \fBC\-q\fP, for example. +.TP +.B tab\-insert (M-TAB) +Insert a tab character. +.TP +.B self\-insert (a,\ b,\ A,\ 1,\ !,\ ...) +Insert the character typed. +.TP +.B transpose\-chars (C\-t) +Drag the character before point forward over the character at point, +moving point forward as well. +If point is at the end of the line, then this transposes +the two characters before point. +Negative arguments have no effect. +.TP +.B transpose\-words (M\-t) +Drag the word before point past the word after point, +moving point over that word as well. +If point is at the end of the line, this transposes +the last two words on the line. +.TP +.B upcase\-word (M\-u) +Uppercase the current (or following) word. With a negative argument, +uppercase the previous word, but do not move point. +.TP +.B downcase\-word (M\-l) +Lowercase the current (or following) word. With a negative argument, +lowercase the previous word, but do not move point. +.TP +.B capitalize\-word (M\-c) +Capitalize the current (or following) word. With a negative argument, +capitalize the previous word, but do not move point. +.TP +.B overwrite\-mode +Toggle overwrite mode. With an explicit positive numeric argument, +switches to overwrite mode. With an explicit non-positive numeric +argument, switches to insert mode. This command affects only +\fBemacs\fP mode; \fBvi\fP mode does overwrite differently. +Each call to \fIreadline()\fP starts in insert mode. +In overwrite mode, characters bound to \fBself\-insert\fP replace +the text at point rather than pushing the text to the right. +Characters bound to \fBbackward\-delete\-char\fP replace the character +before point with a space. By default, this command is unbound. +.PD +.SS Killing and Yanking +.PP +.PD 0 +.TP +.B kill\-line (C\-k) +Kill the text from point to the end of the line. +.TP +.B backward\-kill\-line (C\-x Rubout) +Kill backward to the beginning of the line. +.TP +.B unix\-line\-discard (C\-u) +Kill backward from point to the beginning of the line. +The killed text is saved on the kill-ring. +.\" There is no real difference between this and backward-kill-line +.TP +.B kill\-whole\-line +Kill all characters on the current line, no matter where point is. +.TP +.B kill\-word (M\-d) +Kill from point the end of the current word, or if between +words, to the end of the next word. Word boundaries are the same as +those used by \fBforward\-word\fP. +.TP +.B backward\-kill\-word (M\-Rubout) +Kill the word behind point. +Word boundaries are the same as those used by \fBbackward\-word\fP. +.TP +.B unix\-word\-rubout (C\-w) +Kill the word behind point, using white space as a word boundary. +The killed text is saved on the kill-ring. +.TP +.B unix\-filename\-rubout +Kill the word behind point, using white space and the slash character +as the word boundaries. +The killed text is saved on the kill-ring. +.TP +.B delete\-horizontal\-space (M\-\e) +Delete all spaces and tabs around point. +.TP +.B kill\-region +Kill the text between the point and \fImark\fP (saved cursor position). +This text is referred to as the \fIregion\fP. +.TP +.B copy\-region\-as\-kill +Copy the text in the region to the kill buffer. +.TP +.B copy\-backward\-word +Copy the word before point to the kill buffer. +The word boundaries are the same as \fBbackward\-word\fP. +.TP +.B copy\-forward\-word +Copy the word following point to the kill buffer. +The word boundaries are the same as \fBforward\-word\fP. +.TP +.B yank (C\-y) +Yank the top of the kill ring into the buffer at point. +.TP +.B yank\-pop (M\-y) +Rotate the kill ring, and yank the new top. Only works following +.B yank +or +.BR yank\-pop . +.PD +.SS Numeric Arguments +.PP +.PD 0 +.TP +.B digit\-argument (M\-0, M\-1, ..., M\-\-) +Add this digit to the argument already accumulating, or start a new +argument. M\-\- starts a negative argument. +.TP +.B universal\-argument +This is another way to specify an argument. +If this command is followed by one or more digits, optionally with a +leading minus sign, those digits define the argument. +If the command is followed by digits, executing +.B universal\-argument +again ends the numeric argument, but is otherwise ignored. +As a special case, if this command is immediately followed by a +character that is neither a digit or minus sign, the argument count +for the next command is multiplied by four. +The argument count is initially one, so executing this function the +first time makes the argument count four, a second time makes the +argument count sixteen, and so on. +.PD +.SS Completing +.PP +.PD 0 +.TP +.B complete (TAB) +Attempt to perform completion on the text before point. +The actual completion performed is application-specific. +.BR Bash , +for instance, attempts completion treating the text as a variable +(if the text begins with \fB$\fP), username (if the text begins with +\fB~\fP), hostname (if the text begins with \fB@\fP), or +command (including aliases and functions) in turn. If none +of these produces a match, filename completion is attempted. +.BR Gdb , +on the other hand, +allows completion of program functions and variables, and +only attempts filename completion under certain circumstances. +.TP +.B possible\-completions (M\-?) +List the possible completions of the text before point. +.TP +.B insert\-completions (M\-*) +Insert all completions of the text before point +that would have been generated by +\fBpossible\-completions\fP. +.TP +.B menu\-complete +Similar to \fBcomplete\fP, but replaces the word to be completed +with a single match from the list of possible completions. +Repeated execution of \fBmenu\-complete\fP steps through the list +of possible completions, inserting each match in turn. +At the end of the list of completions, the bell is rung +(subject to the setting of \fBbell\-style\fP) +and the original text is restored. +An argument of \fIn\fP moves \fIn\fP positions forward in the list +of matches; a negative argument may be used to move backward +through the list. +This command is intended to be bound to \fBTAB\fP, but is unbound +by default. +.TP +.B delete\-char\-or\-list +Deletes the character under the cursor if not at the beginning or +end of the line (like \fBdelete-char\fP). +If at the end of the line, behaves identically to +\fBpossible-completions\fP. +.PD +.SS Keyboard Macros +.PP +.PD 0 +.TP +.B start\-kbd\-macro (C\-x (\^) +Begin saving the characters typed into the current keyboard macro. +.TP +.B end\-kbd\-macro (C\-x )\^) +Stop saving the characters typed into the current keyboard macro +and store the definition. +.TP +.B call\-last\-kbd\-macro (C\-x e) +Re-execute the last keyboard macro defined, by making the characters +in the macro appear as if typed at the keyboard. +.PD +.SS Miscellaneous +.PP +.PD 0 +.TP +.B re\-read\-init\-file (C\-x C\-r) +Read in the contents of the \fIinputrc\fP file, and incorporate +any bindings or variable assignments found there. +.TP +.B abort (C\-g) +Abort the current editing command and +ring the terminal's bell (subject to the setting of +.BR bell\-style ). +.TP +.B do\-uppercase\-version (M\-a, M\-b, M\-\fIx\fP, ...) +If the metafied character \fIx\fP is lowercase, run the command +that is bound to the corresponding uppercase character. +.TP +.B prefix\-meta (ESC) +Metafy the next character typed. +.SM +.B ESC +.B f +is equivalent to +.BR Meta\-f . +.TP +.B undo (C\-_, C\-x C\-u) +Incremental undo, separately remembered for each line. +.TP +.B revert\-line (M\-r) +Undo all changes made to this line. This is like executing the +.B undo +command enough times to return the line to its initial state. +.TP +.B tilde\-expand (M\-&) +Perform tilde expansion on the current word. +.TP +.B set\-mark (C\-@, M\-) +Set the mark to the point. If a +numeric argument is supplied, the mark is set to that position. +.TP +.B exchange\-point\-and\-mark (C\-x C\-x) +Swap the point with the mark. The current cursor position is set to +the saved position, and the old cursor position is saved as the mark. +.TP +.B character\-search (C\-]) +A character is read and point is moved to the next occurrence of that +character. A negative count searches for previous occurrences. +.TP +.B character\-search\-backward (M\-C\-]) +A character is read and point is moved to the previous occurrence of that +character. A negative count searches for subsequent occurrences. +.TP +.B insert\-comment (M\-#) +Without a numeric argument, the value of the readline +.B comment\-begin +variable is inserted at the beginning of the current line. +If a numeric argument is supplied, this command acts as a toggle: if +the characters at the beginning of the line do not match the value +of \fBcomment\-begin\fP, the value is inserted, otherwise +the characters in \fBcomment-begin\fP are deleted from the beginning of +the line. +In either case, the line is accepted as if a newline had been typed. +The default value of +.B comment\-begin +makes the current line a shell comment. +If a numeric argument causes the comment character to be removed, the line +will be executed by the shell. +.TP +.B dump\-functions +Print all of the functions and their key bindings to the +readline output stream. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an \fIinputrc\fP file. +.TP +.B dump\-variables +Print all of the settable variables and their values to the +readline output stream. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an \fIinputrc\fP file. +.TP +.B dump\-macros +Print all of the readline key sequences bound to macros and the +strings they output. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an \fIinputrc\fP file. +.TP +.B emacs\-editing\-mode (C\-e) +When in +.B vi +command mode, this causes a switch to +.B emacs +editing mode. +.TP +.B vi\-editing\-mode (M\-C\-j) +When in +.B emacs +editing mode, this causes a switch to +.B vi +editing mode. +.PD +.SH DEFAULT KEY BINDINGS +.LP +The following is a list of the default emacs and vi bindings. +Characters with the eighth bit set are written as M\-, and +are referred to as +.I metafied +characters. +The printable ASCII characters not mentioned in the list of emacs +standard bindings are bound to the +.B self\-insert +function, which just inserts the given character into the input line. +In vi insertion mode, all characters not specifically mentioned are +bound to +.BR self\-insert . +Characters assigned to signal generation by +.IR stty (1) +or the terminal driver, such as C-Z or C-C, +retain that function. +Upper and lower case metafied characters are bound to the same function in +the emacs mode meta keymap. +The remaining characters are unbound, which causes readline +to ring the bell (subject to the setting of the +.B bell\-style +variable). +.SS Emacs Mode +.RS +.6i +.nf +.ta 2.5i +.sp +Emacs Standard bindings +.sp +"C-@" set-mark +"C-A" beginning-of-line +"C-B" backward-char +"C-D" delete-char +"C-E" end-of-line +"C-F" forward-char +"C-G" abort +"C-H" backward-delete-char +"C-I" complete +"C-J" accept-line +"C-K" kill-line +"C-L" clear-screen +"C-M" accept-line +"C-N" next-history +"C-P" previous-history +"C-Q" quoted-insert +"C-R" reverse-search-history +"C-S" forward-search-history +"C-T" transpose-chars +"C-U" unix-line-discard +"C-V" quoted-insert +"C-W" unix-word-rubout +"C-Y" yank +"C-]" character-search +"C-_" undo +"\^ " to "/" self-insert +"0" to "9" self-insert +":" to "~" self-insert +"C-?" backward-delete-char +.PP +Emacs Meta bindings +.sp +"M-C-G" abort +"M-C-H" backward-kill-word +"M-C-I" tab-insert +"M-C-J" vi-editing-mode +"M-C-M" vi-editing-mode +"M-C-R" revert-line +"M-C-Y" yank-nth-arg +"M-C-[" complete +"M-C-]" character-search-backward +"M-space" set-mark +"M-#" insert-comment +"M-&" tilde-expand +"M-*" insert-completions +"M--" digit-argument +"M-." yank-last-arg +"M-0" digit-argument +"M-1" digit-argument +"M-2" digit-argument +"M-3" digit-argument +"M-4" digit-argument +"M-5" digit-argument +"M-6" digit-argument +"M-7" digit-argument +"M-8" digit-argument +"M-9" digit-argument +"M-<" beginning-of-history +"M-=" possible-completions +"M->" end-of-history +"M-?" possible-completions +"M-B" backward-word +"M-C" capitalize-word +"M-D" kill-word +"M-F" forward-word +"M-L" downcase-word +"M-N" non-incremental-forward-search-history +"M-P" non-incremental-reverse-search-history +"M-R" revert-line +"M-T" transpose-words +"M-U" upcase-word +"M-Y" yank-pop +"M-\e" delete-horizontal-space +"M-~" tilde-expand +"M-C-?" backward-kill-word +"M-_" yank-last-arg +.PP +Emacs Control-X bindings +.sp +"C-XC-G" abort +"C-XC-R" re-read-init-file +"C-XC-U" undo +"C-XC-X" exchange-point-and-mark +"C-X(" start-kbd-macro +"C-X)" end-kbd-macro +"C-XE" call-last-kbd-macro +"C-XC-?" backward-kill-line +.sp +.RE +.SS VI Mode bindings +.RS +.6i +.nf +.ta 2.5i +.sp +.PP +VI Insert Mode functions +.sp +"C-D" vi-eof-maybe +"C-H" backward-delete-char +"C-I" complete +"C-J" accept-line +"C-M" accept-line +"C-R" reverse-search-history +"C-S" forward-search-history +"C-T" transpose-chars +"C-U" unix-line-discard +"C-V" quoted-insert +"C-W" unix-word-rubout +"C-Y" yank +"C-[" vi-movement-mode +"C-_" undo +"\^ " to "~" self-insert +"C-?" backward-delete-char +.PP +VI Command Mode functions +.sp +"C-D" vi-eof-maybe +"C-E" emacs-editing-mode +"C-G" abort +"C-H" backward-char +"C-J" accept-line +"C-K" kill-line +"C-L" clear-screen +"C-M" accept-line +"C-N" next-history +"C-P" previous-history +"C-Q" quoted-insert +"C-R" reverse-search-history +"C-S" forward-search-history +"C-T" transpose-chars +"C-U" unix-line-discard +"C-V" quoted-insert +"C-W" unix-word-rubout +"C-Y" yank +"C-_" vi-undo +"\^ " forward-char +"#" insert-comment +"$" end-of-line +"%" vi-match +"&" vi-tilde-expand +"*" vi-complete +"+" next-history +"," vi-char-search +"-" previous-history +"." vi-redo +"/" vi-search +"0" beginning-of-line +"1" to "9" vi-arg-digit +";" vi-char-search +"=" vi-complete +"?" vi-search +"A" vi-append-eol +"B" vi-prev-word +"C" vi-change-to +"D" vi-delete-to +"E" vi-end-word +"F" vi-char-search +"G" vi-fetch-history +"I" vi-insert-beg +"N" vi-search-again +"P" vi-put +"R" vi-replace +"S" vi-subst +"T" vi-char-search +"U" revert-line +"W" vi-next-word +"X" backward-delete-char +"Y" vi-yank-to +"\e" vi-complete +"^" vi-first-print +"_" vi-yank-arg +"`" vi-goto-mark +"a" vi-append-mode +"b" vi-prev-word +"c" vi-change-to +"d" vi-delete-to +"e" vi-end-word +"f" vi-char-search +"h" backward-char +"i" vi-insertion-mode +"j" next-history +"k" prev-history +"l" forward-char +"m" vi-set-mark +"n" vi-search-again +"p" vi-put +"r" vi-change-char +"s" vi-subst +"t" vi-char-search +"u" vi-undo +"w" vi-next-word +"x" vi-delete +"y" vi-yank-to +"|" vi-column +"~" vi-change-case +.RE +.SH "SEE ALSO" +.PD 0 +.TP +\fIThe Gnu Readline Library\fP, Brian Fox and Chet Ramey +.TP +\fIThe Gnu History Library\fP, Brian Fox and Chet Ramey +.TP +\fIbash\fP(1) +.PD +.SH FILES +.PD 0 +.TP +.FN ~/.inputrc +Individual \fBreadline\fP initialization file +.PD +.SH AUTHORS +Brian Fox, Free Software Foundation +.br +bfox@gnu.org +.PP +Chet Ramey, Case Western Reserve University +.br +chet@ins.CWRU.Edu +.SH BUG REPORTS +If you find a bug in +.B readline, +you should report it. But first, you should +make sure that it really is a bug, and that it appears in the latest +version of the +.B readline +library that you have. +.PP +Once you have determined that a bug actually exists, mail a +bug report to \fIbug\-readline\fP@\fIgnu.org\fP. +If you have a fix, you are welcome to mail that +as well! Suggestions and `philosophical' bug reports may be mailed +to \fPbug-readline\fP@\fIgnu.org\fP or posted to the Usenet +newsgroup +.BR gnu.bash.bug . +.PP +Comments and bug reports concerning +this manual page should be directed to +.IR chet@ins.CWRU.Edu . +.SH BUGS +.PP +It's too big and too slow. diff --git a/external/gpl3/gdb/dist/readline/doc/rlman.texi b/external/gpl3/gdb/dist/readline/doc/rlman.texi new file mode 100644 index 000000000000..f834b5826537 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/rlman.texi @@ -0,0 +1,101 @@ +\input texinfo @c -*-texinfo-*- +@comment %**start of header (This is for running Texinfo on a region.) +@setfilename readline.info +@settitle GNU Readline Library +@comment %**end of header (This is for running Texinfo on a region.) +@synindex vr fn +@setchapternewpage odd + +@include version.texi + +@copying +This manual describes the GNU Readline Library +(version @value{VERSION}, @value{UPDATED}), a library which aids in the +consistency of user interface across discrete programs which provide +a command line interface. + +Copyright @copyright{} 1988-2004 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. + +@quotation +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with the Front-Cover texts being ``A GNU Manual,'' +and with the Back-Cover Texts as in (a) below. A copy of the license is +included in the section entitled ``GNU Free Documentation License.'' + +(a) The FSF's Back-Cover Text is: ``You have freedom to copy and modify +this GNU Manual, like GNU software. Copies published by the Free +Software Foundation raise funds for GNU development.'' +@end quotation +@end copying + +@dircategory Libraries +@direntry +* Readline: (readline). The GNU readline library API. +@end direntry + +@titlepage +@title GNU Readline Library +@subtitle Edition @value{EDITION}, for @code{Readline Library} Version @value{VERSION}. +@subtitle @value{UPDATED-MONTH} +@author Chet Ramey, Case Western Reserve University +@author Brian Fox, Free Software Foundation + +@page +@vskip 0pt plus 1filll +@insertcopying + +@sp 1 +Published by the Free Software Foundation @* +59 Temple Place, Suite 330, @* +Boston, MA 02111-1307 @* +USA @* + +@end titlepage + +@contents + +@ifnottex +@node Top +@top GNU Readline Library + +This document describes the GNU Readline Library, a utility which aids +in the consistency of user interface across discrete programs which +provide a command line interface. + +@menu +* Command Line Editing:: GNU Readline User's Manual. +* Programming with GNU Readline:: GNU Readline Programmer's Manual. +* Copying This Manual:: Copying this manual. +* Concept Index:: Index of concepts described in this manual. +* Function and Variable Index:: Index of externally visible functions + and variables. +@end menu +@end ifnottex + +@include rluser.texi +@include rltech.texi + +@node Copying This Manual +@appendix Copying This Manual + +@menu +* GNU Free Documentation License:: License for copying this manual. +@end menu + +@include fdl.texi + +@node Concept Index +@unnumbered Concept Index +@printindex cp + +@node Function and Variable Index +@unnumbered Function and Variable Index +@printindex fn + +@bye diff --git a/external/gpl3/gdb/dist/readline/doc/rltech.texi b/external/gpl3/gdb/dist/readline/doc/rltech.texi new file mode 100644 index 000000000000..6f2e2ee2d345 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/rltech.texi @@ -0,0 +1,2285 @@ +@comment %**start of header (This is for running Texinfo on a region.) +@setfilename rltech.info +@comment %**end of header (This is for running Texinfo on a region.) +@setchapternewpage odd + +@ifinfo +This document describes the GNU Readline Library, a utility for aiding +in the consistency of user interface across discrete programs that need +to provide a command line interface. + +Copyright (C) 1988-2005 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +pare preserved on all copies. + +@ignore +Permission is granted to process this file through TeX and print the +results, provided the printed document carries copying permission +notice identical to this one except for the removal of this paragraph +(this paragraph not being relevant to the printed manual). +@end ignore + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided that the entire +resulting derived work is distributed under the terms of a permission +notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions, +except that this permission notice may be stated in a translation approved +by the Foundation. +@end ifinfo + +@node Programming with GNU Readline +@chapter Programming with GNU Readline + +This chapter describes the interface between the @sc{gnu} Readline Library and +other programs. If you are a programmer, and you wish to include the +features found in @sc{gnu} Readline +such as completion, line editing, and interactive history manipulation +in your own programs, this section is for you. + +@menu +* Basic Behavior:: Using the default behavior of Readline. +* Custom Functions:: Adding your own functions to Readline. +* Readline Variables:: Variables accessible to custom + functions. +* Readline Convenience Functions:: Functions which Readline supplies to + aid in writing your own custom + functions. +* Readline Signal Handling:: How Readline behaves when it receives signals. +* Custom Completers:: Supplanting or supplementing Readline's + completion functions. +@end menu + +@node Basic Behavior +@section Basic Behavior + +Many programs provide a command line interface, such as @code{mail}, +@code{ftp}, and @code{sh}. For such programs, the default behaviour of +Readline is sufficient. This section describes how to use Readline in +the simplest way possible, perhaps to replace calls in your code to +@code{gets()} or @code{fgets()}. + +@findex readline +@cindex readline, function + +The function @code{readline()} prints a prompt @var{prompt} +and then reads and returns a single line of text from the user. +If @var{prompt} is @code{NULL} or the empty string, no prompt is displayed. +The line @code{readline} returns is allocated with @code{malloc()}; +the caller should @code{free()} the line when it has finished with it. +The declaration for @code{readline} in ANSI C is + +@example +@code{char *readline (const char *@var{prompt});} +@end example + +@noindent +So, one might say +@example +@code{char *line = readline ("Enter a line: ");} +@end example +@noindent +in order to read a line of text from the user. +The line returned has the final newline removed, so only the +text remains. + +If @code{readline} encounters an @code{EOF} while reading the line, and the +line is empty at that point, then @code{(char *)NULL} is returned. +Otherwise, the line is ended just as if a newline had been typed. + +If you want the user to be able to get at the line later, (with +@key{C-p} for example), you must call @code{add_history()} to save the +line away in a @dfn{history} list of such lines. + +@example +@code{add_history (line)}; +@end example + +@noindent +For full details on the GNU History Library, see the associated manual. + +It is preferable to avoid saving empty lines on the history list, since +users rarely have a burning need to reuse a blank line. Here is +a function which usefully replaces the standard @code{gets()} library +function, and has the advantage of no static buffer to overflow: + +@example +/* A static variable for holding the line. */ +static char *line_read = (char *)NULL; + +/* Read a string, and return a pointer to it. + Returns NULL on EOF. */ +char * +rl_gets () +@{ + /* If the buffer has already been allocated, + return the memory to the free pool. */ + if (line_read) + @{ + free (line_read); + line_read = (char *)NULL; + @} + + /* Get a line from the user. */ + line_read = readline (""); + + /* If the line has any text in it, + save it on the history. */ + if (line_read && *line_read) + add_history (line_read); + + return (line_read); +@} +@end example + +This function gives the user the default behaviour of @key{TAB} +completion: completion on file names. If you do not want Readline to +complete on filenames, you can change the binding of the @key{TAB} key +with @code{rl_bind_key()}. + +@example +@code{int rl_bind_key (int @var{key}, rl_command_func_t *@var{function});} +@end example + +@code{rl_bind_key()} takes two arguments: @var{key} is the character that +you want to bind, and @var{function} is the address of the function to +call when @var{key} is pressed. Binding @key{TAB} to @code{rl_insert()} +makes @key{TAB} insert itself. +@code{rl_bind_key()} returns non-zero if @var{key} is not a valid +ASCII character code (between 0 and 255). + +Thus, to disable the default @key{TAB} behavior, the following suffices: +@example +@code{rl_bind_key ('\t', rl_insert);} +@end example + +This code should be executed once at the start of your program; you +might write a function called @code{initialize_readline()} which +performs this and other desired initializations, such as installing +custom completers (@pxref{Custom Completers}). + +@node Custom Functions +@section Custom Functions + +Readline provides many functions for manipulating the text of +the line, but it isn't possible to anticipate the needs of all +programs. This section describes the various functions and variables +defined within the Readline library which allow a user program to add +customized functionality to Readline. + +Before declaring any functions that customize Readline's behavior, or +using any functionality Readline provides in other code, an +application writer should include the file @code{} +in any file that uses Readline's features. Since some of the definitions +in @code{readline.h} use the @code{stdio} library, the file +@code{} should be included before @code{readline.h}. + +@code{readline.h} defines a C preprocessor variable that should +be treated as an integer, @code{RL_READLINE_VERSION}, which may +be used to conditionally compile application code depending on +the installed Readline version. The value is a hexadecimal +encoding of the major and minor version numbers of the library, +of the form 0x@var{MMmm}. @var{MM} is the two-digit major +version number; @var{mm} is the two-digit minor version number. +For Readline 4.2, for example, the value of +@code{RL_READLINE_VERSION} would be @code{0x0402}. + +@menu +* Readline Typedefs:: C declarations to make code readable. +* Function Writing:: Variables and calling conventions. +@end menu + +@node Readline Typedefs +@subsection Readline Typedefs + +For readabilty, we declare a number of new object types, all pointers +to functions. + +The reason for declaring these new types is to make it easier to write +code describing pointers to C functions with appropriately prototyped +arguments and return values. + +For instance, say we want to declare a variable @var{func} as a pointer +to a function which takes two @code{int} arguments and returns an +@code{int} (this is the type of all of the Readline bindable functions). +Instead of the classic C declaration + +@code{int (*func)();} + +@noindent +or the ANSI-C style declaration + +@code{int (*func)(int, int);} + +@noindent +we may write + +@code{rl_command_func_t *func;} + +The full list of function pointer types available is + +@table @code +@item typedef int rl_command_func_t (int, int); + +@item typedef char *rl_compentry_func_t (const char *, int); + +@item typedef char **rl_completion_func_t (const char *, int, int); + +@item typedef char *rl_quote_func_t (char *, int, char *); + +@item typedef char *rl_dequote_func_t (char *, int); + +@item typedef int rl_compignore_func_t (char **); + +@item typedef void rl_compdisp_func_t (char **, int, int); + +@item typedef int rl_hook_func_t (void); + +@item typedef int rl_getc_func_t (FILE *); + +@item typedef int rl_linebuf_func_t (char *, int); + +@item typedef int rl_intfunc_t (int); +@item #define rl_ivoidfunc_t rl_hook_func_t +@item typedef int rl_icpfunc_t (char *); +@item typedef int rl_icppfunc_t (char **); + +@item typedef void rl_voidfunc_t (void); +@item typedef void rl_vintfunc_t (int); +@item typedef void rl_vcpfunc_t (char *); +@item typedef void rl_vcppfunc_t (char **); + +@end table + +@node Function Writing +@subsection Writing a New Function + +In order to write new functions for Readline, you need to know the +calling conventions for keyboard-invoked functions, and the names of the +variables that describe the current state of the line read so far. + +The calling sequence for a command @code{foo} looks like + +@example +@code{int foo (int count, int key)} +@end example + +@noindent +where @var{count} is the numeric argument (or 1 if defaulted) and +@var{key} is the key that invoked this function. + +It is completely up to the function as to what should be done with the +numeric argument. Some functions use it as a repeat count, some +as a flag, and others to choose alternate behavior (refreshing the current +line as opposed to refreshing the screen, for example). Some choose to +ignore it. In general, if a +function uses the numeric argument as a repeat count, it should be able +to do something useful with both negative and positive arguments. +At the very least, it should be aware that it can be passed a +negative argument. + +A command function should return 0 if its action completes successfully, +and a non-zero value if some error occurs. +This is the convention obeyed by all of the builtin Readline bindable +command functions. + +@node Readline Variables +@section Readline Variables + +These variables are available to function writers. + +@deftypevar {char *} rl_line_buffer +This is the line gathered so far. You are welcome to modify the +contents of the line, but see @ref{Allowing Undoing}. The +function @code{rl_extend_line_buffer} is available to increase +the memory allocated to @code{rl_line_buffer}. +@end deftypevar + +@deftypevar int rl_point +The offset of the current cursor position in @code{rl_line_buffer} +(the @emph{point}). +@end deftypevar + +@deftypevar int rl_end +The number of characters present in @code{rl_line_buffer}. When +@code{rl_point} is at the end of the line, @code{rl_point} and +@code{rl_end} are equal. +@end deftypevar + +@deftypevar int rl_mark +The @var{mark} (saved position) in the current line. If set, the mark +and point define a @emph{region}. +@end deftypevar + +@deftypevar int rl_done +Setting this to a non-zero value causes Readline to return the current +line immediately. +@end deftypevar + +@deftypevar int rl_num_chars_to_read +Setting this to a positive value before calling @code{readline()} causes +Readline to return after accepting that many characters, rather +than reading up to a character bound to @code{accept-line}. +@end deftypevar + +@deftypevar int rl_pending_input +Setting this to a value makes it the next keystroke read. This is a +way to stuff a single character into the input stream. +@end deftypevar + +@deftypevar int rl_dispatching +Set to a non-zero value if a function is being called from a key binding; +zero otherwise. Application functions can test this to discover whether +they were called directly or by Readline's dispatching mechanism. +@end deftypevar + +@deftypevar int rl_erase_empty_line +Setting this to a non-zero value causes Readline to completely erase +the current line, including any prompt, any time a newline is typed as +the only character on an otherwise-empty line. The cursor is moved to +the beginning of the newly-blank line. +@end deftypevar + +@deftypevar {char *} rl_prompt +The prompt Readline uses. This is set from the argument to +@code{readline()}, and should not be assigned to directly. +The @code{rl_set_prompt()} function (@pxref{Redisplay}) may +be used to modify the prompt string after calling @code{readline()}. +@end deftypevar + +@deftypevar int rl_already_prompted +If an application wishes to display the prompt itself, rather than have +Readline do it the first time @code{readline()} is called, it should set +this variable to a non-zero value after displaying the prompt. +The prompt must also be passed as the argument to @code{readline()} so +the redisplay functions can update the display properly. +The calling application is responsible for managing the value; Readline +never sets it. +@end deftypevar + +@deftypevar {const char *} rl_library_version +The version number of this revision of the library. +@end deftypevar + +@deftypevar int rl_readline_version +An integer encoding the current version of the library. The encoding is +of the form 0x@var{MMmm}, where @var{MM} is the two-digit major version +number, and @var{mm} is the two-digit minor version number. +For example, for Readline-4.2, @code{rl_readline_version} would have the +value 0x0402. +@end deftypevar + +@deftypevar {int} rl_gnu_readline_p +Always set to 1, denoting that this is @sc{gnu} readline rather than some +emulation. +@end deftypevar + +@deftypevar {const char *} rl_terminal_name +The terminal type, used for initialization. If not set by the application, +Readline sets this to the value of the @env{TERM} environment variable +the first time it is called. +@end deftypevar + +@deftypevar {const char *} rl_readline_name +This variable is set to a unique name by each application using Readline. +The value allows conditional parsing of the inputrc file +(@pxref{Conditional Init Constructs}). +@end deftypevar + +@deftypevar {FILE *} rl_instream +The stdio stream from which Readline reads input. +If @code{NULL}, Readline defaults to @var{stdin}. +@end deftypevar + +@deftypevar {FILE *} rl_outstream +The stdio stream to which Readline performs output. +If @code{NULL}, Readline defaults to @var{stdout}. +@end deftypevar + +@deftypevar int rl_prefer_env_winsize +If non-zero, Readline gives values found in the @env{LINES} and +@env{COLUMNS} environment variables greater precedence than values fetched +from the kernel when computing the screen dimensions. +@end deftypevar + +@deftypevar {rl_command_func_t *} rl_last_func +The address of the last command function Readline executed. May be used to +test whether or not a function is being executed twice in succession, for +example. +@end deftypevar + +@deftypevar {rl_hook_func_t *} rl_startup_hook +If non-zero, this is the address of a function to call just +before @code{readline} prints the first prompt. +@end deftypevar + +@deftypevar {rl_hook_func_t *} rl_pre_input_hook +If non-zero, this is the address of a function to call after +the first prompt has been printed and just before @code{readline} +starts reading input characters. +@end deftypevar + +@deftypevar {rl_hook_func_t *} rl_event_hook +If non-zero, this is the address of a function to call periodically +when Readline is waiting for terminal input. +By default, this will be called at most ten times a second if there +is no keyboard input. +@end deftypevar + +@deftypevar {rl_getc_func_t *} rl_getc_function +If non-zero, Readline will call indirectly through this pointer +to get a character from the input stream. By default, it is set to +@code{rl_getc}, the default Readline character input function +(@pxref{Character Input}). +@end deftypevar + +@deftypevar {rl_voidfunc_t *} rl_redisplay_function +If non-zero, Readline will call indirectly through this pointer +to update the display with the current contents of the editing buffer. +By default, it is set to @code{rl_redisplay}, the default Readline +redisplay function (@pxref{Redisplay}). +@end deftypevar + +@deftypevar {rl_vintfunc_t *} rl_prep_term_function +If non-zero, Readline will call indirectly through this pointer +to initialize the terminal. The function takes a single argument, an +@code{int} flag that says whether or not to use eight-bit characters. +By default, this is set to @code{rl_prep_terminal} +(@pxref{Terminal Management}). +@end deftypevar + +@deftypevar {rl_voidfunc_t *} rl_deprep_term_function +If non-zero, Readline will call indirectly through this pointer +to reset the terminal. This function should undo the effects of +@code{rl_prep_term_function}. +By default, this is set to @code{rl_deprep_terminal} +(@pxref{Terminal Management}). +@end deftypevar + +@deftypevar {Keymap} rl_executing_keymap +This variable is set to the keymap (@pxref{Keymaps}) in which the +currently executing readline function was found. +@end deftypevar + +@deftypevar {Keymap} rl_binding_keymap +This variable is set to the keymap (@pxref{Keymaps}) in which the +last key binding occurred. +@end deftypevar + +@deftypevar {char *} rl_executing_macro +This variable is set to the text of any currently-executing macro. +@end deftypevar + +@deftypevar {int} rl_readline_state +A variable with bit values that encapsulate the current Readline state. +A bit is set with the @code{RL_SETSTATE} macro, and unset with the +@code{RL_UNSETSTATE} macro. Use the @code{RL_ISSTATE} macro to test +whether a particular state bit is set. Current state bits include: + +@table @code +@item RL_STATE_NONE +Readline has not yet been called, nor has it begun to intialize. +@item RL_STATE_INITIALIZING +Readline is initializing its internal data structures. +@item RL_STATE_INITIALIZED +Readline has completed its initialization. +@item RL_STATE_TERMPREPPED +Readline has modified the terminal modes to do its own input and redisplay. +@item RL_STATE_READCMD +Readline is reading a command from the keyboard. +@item RL_STATE_METANEXT +Readline is reading more input after reading the meta-prefix character. +@item RL_STATE_DISPATCHING +Readline is dispatching to a command. +@item RL_STATE_MOREINPUT +Readline is reading more input while executing an editing command. +@item RL_STATE_ISEARCH +Readline is performing an incremental history search. +@item RL_STATE_NSEARCH +Readline is performing a non-incremental history search. +@item RL_STATE_SEARCH +Readline is searching backward or forward through the history for a string. +@item RL_STATE_NUMERICARG +Readline is reading a numeric argument. +@item RL_STATE_MACROINPUT +Readline is currently getting its input from a previously-defined keyboard +macro. +@item RL_STATE_MACRODEF +Readline is currently reading characters defining a keyboard macro. +@item RL_STATE_OVERWRITE +Readline is in overwrite mode. +@item RL_STATE_COMPLETING +Readline is performing word completion. +@item RL_STATE_SIGHANDLER +Readline is currently executing the readline signal handler. +@item RL_STATE_UNDOING +Readline is performing an undo. +@item RL_STATE_DONE +Readline has read a key sequence bound to @code{accept-line} +and is about to return the line to the caller. +@end table + +@end deftypevar + +@deftypevar {int} rl_explicit_arg +Set to a non-zero value if an explicit numeric argument was specified by +the user. Only valid in a bindable command function. +@end deftypevar + +@deftypevar {int} rl_numeric_arg +Set to the value of any numeric argument explicitly specified by the user +before executing the current Readline function. Only valid in a bindable +command function. +@end deftypevar + +@deftypevar {int} rl_editing_mode +Set to a value denoting Readline's current editing mode. A value of +@var{1} means Readline is currently in emacs mode; @var{0} +means that vi mode is active. +@end deftypevar + + +@node Readline Convenience Functions +@section Readline Convenience Functions + +@menu +* Function Naming:: How to give a function you write a name. +* Keymaps:: Making keymaps. +* Binding Keys:: Changing Keymaps. +* Associating Function Names and Bindings:: Translate function names to + key sequences. +* Allowing Undoing:: How to make your functions undoable. +* Redisplay:: Functions to control line display. +* Modifying Text:: Functions to modify @code{rl_line_buffer}. +* Character Input:: Functions to read keyboard input. +* Terminal Management:: Functions to manage terminal settings. +* Utility Functions:: Generally useful functions and hooks. +* Miscellaneous Functions:: Functions that don't fall into any category. +* Alternate Interface:: Using Readline in a `callback' fashion. +* A Readline Example:: An example Readline function. +@end menu + +@node Function Naming +@subsection Naming a Function + +The user can dynamically change the bindings of keys while using +Readline. This is done by representing the function with a descriptive +name. The user is able to type the descriptive name when referring to +the function. Thus, in an init file, one might find + +@example +Meta-Rubout: backward-kill-word +@end example + +This binds the keystroke @key{Meta-Rubout} to the function +@emph{descriptively} named @code{backward-kill-word}. You, as the +programmer, should bind the functions you write to descriptive names as +well. Readline provides a function for doing that: + +@deftypefun int rl_add_defun (const char *name, rl_command_func_t *function, int key) +Add @var{name} to the list of named functions. Make @var{function} be +the function that gets called. If @var{key} is not -1, then bind it to +@var{function} using @code{rl_bind_key()}. +@end deftypefun + +Using this function alone is sufficient for most applications. +It is the recommended way to add a few functions to the default +functions that Readline has built in. +If you need to do something other than adding a function to Readline, +you may need to use the underlying functions described below. + +@node Keymaps +@subsection Selecting a Keymap + +Key bindings take place on a @dfn{keymap}. The keymap is the +association between the keys that the user types and the functions that +get run. You can make your own keymaps, copy existing keymaps, and tell +Readline which keymap to use. + +@deftypefun Keymap rl_make_bare_keymap (void) +Returns a new, empty keymap. The space for the keymap is allocated with +@code{malloc()}; the caller should free it by calling +@code{rl_discard_keymap()} when done. +@end deftypefun + +@deftypefun Keymap rl_copy_keymap (Keymap map) +Return a new keymap which is a copy of @var{map}. +@end deftypefun + +@deftypefun Keymap rl_make_keymap (void) +Return a new keymap with the printing characters bound to rl_insert, +the lowercase Meta characters bound to run their equivalents, and +the Meta digits bound to produce numeric arguments. +@end deftypefun + +@deftypefun void rl_discard_keymap (Keymap keymap) +Free the storage associated with @var{keymap}. +@end deftypefun + +Readline has several internal keymaps. These functions allow you to +change which keymap is active. + +@deftypefun Keymap rl_get_keymap (void) +Returns the currently active keymap. +@end deftypefun + +@deftypefun void rl_set_keymap (Keymap keymap) +Makes @var{keymap} the currently active keymap. +@end deftypefun + +@deftypefun Keymap rl_get_keymap_by_name (const char *name) +Return the keymap matching @var{name}. @var{name} is one which would +be supplied in a @code{set keymap} inputrc line (@pxref{Readline Init File}). +@end deftypefun + +@deftypefun {char *} rl_get_keymap_name (Keymap keymap) +Return the name matching @var{keymap}. @var{name} is one which would +be supplied in a @code{set keymap} inputrc line (@pxref{Readline Init File}). +@end deftypefun + +@node Binding Keys +@subsection Binding Keys + +Key sequences are associate with functions through the keymap. +Readline has several internal keymaps: @code{emacs_standard_keymap}, +@code{emacs_meta_keymap}, @code{emacs_ctlx_keymap}, +@code{vi_movement_keymap}, and @code{vi_insertion_keymap}. +@code{emacs_standard_keymap} is the default, and the examples in +this manual assume that. + +Since @code{readline()} installs a set of default key bindings the first +time it is called, there is always the danger that a custom binding +installed before the first call to @code{readline()} will be overridden. +An alternate mechanism is to install custom key bindings in an +initialization function assigned to the @code{rl_startup_hook} variable +(@pxref{Readline Variables}). + +These functions manage key bindings. + +@deftypefun int rl_bind_key (int key, rl_command_func_t *function) +Binds @var{key} to @var{function} in the currently active keymap. +Returns non-zero in the case of an invalid @var{key}. +@end deftypefun + +@deftypefun int rl_bind_key_in_map (int key, rl_command_func_t *function, Keymap map) +Bind @var{key} to @var{function} in @var{map}. +Returns non-zero in the case of an invalid @var{key}. +@end deftypefun + +@deftypefun int rl_bind_key_if_unbound (int key, rl_command_func_t *function) +Binds @var{key} to @var{function} if it is not already bound in the +currently active keymap. +Returns non-zero in the case of an invalid @var{key} or if @var{key} is +already bound. +@end deftypefun + +@deftypefun int rl_bind_key_if_unbound_in_map (int key, rl_command_func_t *function, Keymap map) +Binds @var{key} to @var{function} if it is not already bound in @var{map}. +Returns non-zero in the case of an invalid @var{key} or if @var{key} is +already bound. +@end deftypefun + +@deftypefun int rl_unbind_key (int key) +Bind @var{key} to the null function in the currently active keymap. +Returns non-zero in case of error. +@end deftypefun + +@deftypefun int rl_unbind_key_in_map (int key, Keymap map) +Bind @var{key} to the null function in @var{map}. +Returns non-zero in case of error. +@end deftypefun + +@deftypefun int rl_unbind_function_in_map (rl_command_func_t *function, Keymap map) +Unbind all keys that execute @var{function} in @var{map}. +@end deftypefun + +@deftypefun int rl_unbind_command_in_map (const char *command, Keymap map) +Unbind all keys that are bound to @var{command} in @var{map}. +@end deftypefun + +@deftypefun int rl_bind_keyseq (const char *keyseq, rl_command_func_t *function) +Bind the key sequence represented by the string @var{keyseq} to the function +@var{function}, beginning in the current keymap. +This makes new keymaps as necessary. +The return value is non-zero if @var{keyseq} is invalid. +@end deftypefun + +@deftypefun int rl_bind_keyseq_in_map (const char *keyseq, rl_command_func_t *function, Keymap map) +Bind the key sequence represented by the string @var{keyseq} to the function +@var{function}. This makes new keymaps as necessary. +Initial bindings are performed in @var{map}. +The return value is non-zero if @var{keyseq} is invalid. +@end deftypefun + +@deftypefun int rl_set_key (const char *keyseq, rl_command_func_t *function, Keymap map) +Equivalent to @code{rl_bind_keyseq_in_map}. +@end deftypefun + +@deftypefun int rl_bind_keyseq_if_unbound (const char *keyseq, rl_command_func_t *function) +Binds @var{keyseq} to @var{function} if it is not already bound in the +currently active keymap. +Returns non-zero in the case of an invalid @var{keyseq} or if @var{keyseq} is +already bound. +@end deftypefun + +@deftypefun int rl_bind_keyseq_if_unbound_in_map (const char *keyseq, rl_command_func_t *function, Keymap map) +Binds @var{keyseq} to @var{function} if it is not already bound in @var{map}. +Returns non-zero in the case of an invalid @var{keyseq} or if @var{keyseq} is +already bound. +@end deftypefun + +@deftypefun int rl_generic_bind (int type, const char *keyseq, char *data, Keymap map) +Bind the key sequence represented by the string @var{keyseq} to the arbitrary +pointer @var{data}. @var{type} says what kind of data is pointed to by +@var{data}; this can be a function (@code{ISFUNC}), a macro +(@code{ISMACR}), or a keymap (@code{ISKMAP}). This makes new keymaps as +necessary. The initial keymap in which to do bindings is @var{map}. +@end deftypefun + +@deftypefun int rl_parse_and_bind (char *line) +Parse @var{line} as if it had been read from the @code{inputrc} file and +perform any key bindings and variable assignments found +(@pxref{Readline Init File}). +@end deftypefun + +@deftypefun int rl_read_init_file (const char *filename) +Read keybindings and variable assignments from @var{filename} +(@pxref{Readline Init File}). +@end deftypefun + +@node Associating Function Names and Bindings +@subsection Associating Function Names and Bindings + +These functions allow you to find out what keys invoke named functions +and the functions invoked by a particular key sequence. You may also +associate a new function name with an arbitrary function. + +@deftypefun {rl_command_func_t *} rl_named_function (const char *name) +Return the function with name @var{name}. +@end deftypefun + +@deftypefun {rl_command_func_t *} rl_function_of_keyseq (const char *keyseq, Keymap map, int *type) +Return the function invoked by @var{keyseq} in keymap @var{map}. +If @var{map} is @code{NULL}, the current keymap is used. If @var{type} is +not @code{NULL}, the type of the object is returned in the @code{int} variable +it points to (one of @code{ISFUNC}, @code{ISKMAP}, or @code{ISMACR}). +@end deftypefun + +@deftypefun {char **} rl_invoking_keyseqs (rl_command_func_t *function) +Return an array of strings representing the key sequences used to +invoke @var{function} in the current keymap. +@end deftypefun + +@deftypefun {char **} rl_invoking_keyseqs_in_map (rl_command_func_t *function, Keymap map) +Return an array of strings representing the key sequences used to +invoke @var{function} in the keymap @var{map}. +@end deftypefun + +@deftypefun void rl_function_dumper (int readable) +Print the readline function names and the key sequences currently +bound to them to @code{rl_outstream}. If @var{readable} is non-zero, +the list is formatted in such a way that it can be made part of an +@code{inputrc} file and re-read. +@end deftypefun + +@deftypefun void rl_list_funmap_names (void) +Print the names of all bindable Readline functions to @code{rl_outstream}. +@end deftypefun + +@deftypefun {const char **} rl_funmap_names (void) +Return a NULL terminated array of known function names. The array is +sorted. The array itself is allocated, but not the strings inside. You +should @code{free()} the array when you are done, but not the pointers. +@end deftypefun + +@deftypefun int rl_add_funmap_entry (const char *name, rl_command_func_t *function) +Add @var{name} to the list of bindable Readline command names, and make +@var{function} the function to be called when @var{name} is invoked. +@end deftypefun + +@node Allowing Undoing +@subsection Allowing Undoing + +Supporting the undo command is a painless thing, and makes your +functions much more useful. It is certainly easy to try +something if you know you can undo it. + +If your function simply inserts text once, or deletes text once, and +uses @code{rl_insert_text()} or @code{rl_delete_text()} to do it, then +undoing is already done for you automatically. + +If you do multiple insertions or multiple deletions, or any combination +of these operations, you should group them together into one operation. +This is done with @code{rl_begin_undo_group()} and +@code{rl_end_undo_group()}. + +The types of events that can be undone are: + +@smallexample +enum undo_code @{ UNDO_DELETE, UNDO_INSERT, UNDO_BEGIN, UNDO_END @}; +@end smallexample + +Notice that @code{UNDO_DELETE} means to insert some text, and +@code{UNDO_INSERT} means to delete some text. That is, the undo code +tells what to undo, not how to undo it. @code{UNDO_BEGIN} and +@code{UNDO_END} are tags added by @code{rl_begin_undo_group()} and +@code{rl_end_undo_group()}. + +@deftypefun int rl_begin_undo_group (void) +Begins saving undo information in a group construct. The undo +information usually comes from calls to @code{rl_insert_text()} and +@code{rl_delete_text()}, but could be the result of calls to +@code{rl_add_undo()}. +@end deftypefun + +@deftypefun int rl_end_undo_group (void) +Closes the current undo group started with @code{rl_begin_undo_group +()}. There should be one call to @code{rl_end_undo_group()} +for each call to @code{rl_begin_undo_group()}. +@end deftypefun + +@deftypefun void rl_add_undo (enum undo_code what, int start, int end, char *text) +Remember how to undo an event (according to @var{what}). The affected +text runs from @var{start} to @var{end}, and encompasses @var{text}. +@end deftypefun + +@deftypefun void rl_free_undo_list (void) +Free the existing undo list. +@end deftypefun + +@deftypefun int rl_do_undo (void) +Undo the first thing on the undo list. Returns @code{0} if there was +nothing to undo, non-zero if something was undone. +@end deftypefun + +Finally, if you neither insert nor delete text, but directly modify the +existing text (e.g., change its case), call @code{rl_modifying()} +once, just before you modify the text. You must supply the indices of +the text range that you are going to modify. + +@deftypefun int rl_modifying (int start, int end) +Tell Readline to save the text between @var{start} and @var{end} as a +single undo unit. It is assumed that you will subsequently modify +that text. +@end deftypefun + +@node Redisplay +@subsection Redisplay + +@deftypefun void rl_redisplay (void) +Change what's displayed on the screen to reflect the current contents +of @code{rl_line_buffer}. +@end deftypefun + +@deftypefun int rl_forced_update_display (void) +Force the line to be updated and redisplayed, whether or not +Readline thinks the screen display is correct. +@end deftypefun + +@deftypefun int rl_on_new_line (void) +Tell the update functions that we have moved onto a new (empty) line, +usually after ouputting a newline. +@end deftypefun + +@deftypefun int rl_on_new_line_with_prompt (void) +Tell the update functions that we have moved onto a new line, with +@var{rl_prompt} already displayed. +This could be used by applications that want to output the prompt string +themselves, but still need Readline to know the prompt string length for +redisplay. +It should be used after setting @var{rl_already_prompted}. +@end deftypefun + +@deftypefun int rl_reset_line_state (void) +Reset the display state to a clean state and redisplay the current line +starting on a new line. +@end deftypefun + +@deftypefun int rl_crlf (void) +Move the cursor to the start of the next screen line. +@end deftypefun + +@deftypefun int rl_show_char (int c) +Display character @var{c} on @code{rl_outstream}. +If Readline has not been set to display meta characters directly, this +will convert meta characters to a meta-prefixed key sequence. +This is intended for use by applications which wish to do their own +redisplay. +@end deftypefun + +@deftypefun int rl_message (const char *, @dots{}) +The arguments are a format string as would be supplied to @code{printf}, +possibly containing conversion specifications such as @samp{%d}, and +any additional arguments necessary to satisfy the conversion specifications. +The resulting string is displayed in the @dfn{echo area}. The echo area +is also used to display numeric arguments and search strings. +You should call @code{rl_save_prompt} to save the prompt information +before calling this function. +@end deftypefun + +@deftypefun int rl_clear_message (void) +Clear the message in the echo area. If the prompt was saved with a call to +@code{rl_save_prompt} before the last call to @code{rl_message}, +call @code{rl_restore_prompt} before calling this function. +@end deftypefun + +@deftypefun void rl_save_prompt (void) +Save the local Readline prompt display state in preparation for +displaying a new message in the message area with @code{rl_message()}. +@end deftypefun + +@deftypefun void rl_restore_prompt (void) +Restore the local Readline prompt display state saved by the most +recent call to @code{rl_save_prompt}. +if @code{rl_save_prompt} was called to save the prompt before a call +to @code{rl_message}, this function should be called before the +corresponding call to @code{rl_clear_message}. +@end deftypefun + +@deftypefun int rl_expand_prompt (char *prompt) +Expand any special character sequences in @var{prompt} and set up the +local Readline prompt redisplay variables. +This function is called by @code{readline()}. It may also be called to +expand the primary prompt if the @code{rl_on_new_line_with_prompt()} +function or @code{rl_already_prompted} variable is used. +It returns the number of visible characters on the last line of the +(possibly multi-line) prompt. +Applications may indicate that the prompt contains characters that take +up no physical screen space when displayed by bracketing a sequence of +such characters with the special markers @code{RL_PROMPT_START_IGNORE} +and @code{RL_PROMPT_END_IGNORE} (declared in @file{readline.h}. This may +be used to embed terminal-specific escape sequences in prompts. +@end deftypefun + +@deftypefun int rl_set_prompt (const char *prompt) +Make Readline use @var{prompt} for subsequent redisplay. This calls +@code{rl_expand_prompt()} to expand the prompt and sets @code{rl_prompt} +to the result. +@end deftypefun + +@node Modifying Text +@subsection Modifying Text + +@deftypefun int rl_insert_text (const char *text) +Insert @var{text} into the line at the current cursor position. +Returns the number of characters inserted. +@end deftypefun + +@deftypefun int rl_delete_text (int start, int end) +Delete the text between @var{start} and @var{end} in the current line. +Returns the number of characters deleted. +@end deftypefun + +@deftypefun {char *} rl_copy_text (int start, int end) +Return a copy of the text between @var{start} and @var{end} in +the current line. +@end deftypefun + +@deftypefun int rl_kill_text (int start, int end) +Copy the text between @var{start} and @var{end} in the current line +to the kill ring, appending or prepending to the last kill if the +last command was a kill command. The text is deleted. +If @var{start} is less than @var{end}, +the text is appended, otherwise prepended. If the last command was +not a kill, a new kill ring slot is used. +@end deftypefun + +@deftypefun int rl_push_macro_input (char *macro) +Cause @var{macro} to be inserted into the line, as if it had been invoked +by a key bound to a macro. Not especially useful; use +@code{rl_insert_text()} instead. +@end deftypefun + +@node Character Input +@subsection Character Input + +@deftypefun int rl_read_key (void) +Return the next character available from Readline's current input stream. +This handles input inserted into +the input stream via @var{rl_pending_input} (@pxref{Readline Variables}) +and @code{rl_stuff_char()}, macros, and characters read from the keyboard. +While waiting for input, this function will call any function assigned to +the @code{rl_event_hook} variable. +@end deftypefun + +@deftypefun int rl_getc (FILE *stream) +Return the next character available from @var{stream}, which is assumed to +be the keyboard. +@end deftypefun + +@deftypefun int rl_stuff_char (int c) +Insert @var{c} into the Readline input stream. It will be "read" +before Readline attempts to read characters from the terminal with +@code{rl_read_key()}. Up to 512 characters may be pushed back. +@code{rl_stuff_char} returns 1 if the character was successfully inserted; +0 otherwise. +@end deftypefun + +@deftypefun int rl_execute_next (int c) +Make @var{c} be the next command to be executed when @code{rl_read_key()} +is called. This sets @var{rl_pending_input}. +@end deftypefun + +@deftypefun int rl_clear_pending_input (void) +Unset @var{rl_pending_input}, effectively negating the effect of any +previous call to @code{rl_execute_next()}. This works only if the +pending input has not already been read with @code{rl_read_key()}. +@end deftypefun + +@deftypefun int rl_set_keyboard_input_timeout (int u) +While waiting for keyboard input in @code{rl_read_key()}, Readline will +wait for @var{u} microseconds for input before calling any function +assigned to @code{rl_event_hook}. The default waiting period is +one-tenth of a second. Returns the old timeout value. +@end deftypefun + +@node Terminal Management +@subsection Terminal Management + +@deftypefun void rl_prep_terminal (int meta_flag) +Modify the terminal settings for Readline's use, so @code{readline()} +can read a single character at a time from the keyboard. +The @var{meta_flag} argument should be non-zero if Readline should +read eight-bit input. +@end deftypefun + +@deftypefun void rl_deprep_terminal (void) +Undo the effects of @code{rl_prep_terminal()}, leaving the terminal in +the state in which it was before the most recent call to +@code{rl_prep_terminal()}. +@end deftypefun + +@deftypefun void rl_tty_set_default_bindings (Keymap kmap) +Read the operating system's terminal editing characters (as would be +displayed by @code{stty}) to their Readline equivalents. +The bindings are performed in @var{kmap}. +@end deftypefun + +@deftypefun void rl_tty_unset_default_bindings (Keymap kmap) +Reset the bindings manipulated by @code{rl_tty_set_default_bindings} so +that the terminal editing characters are bound to @code{rl_insert}. +The bindings are performed in @var{kmap}. +@end deftypefun + +@deftypefun int rl_reset_terminal (const char *terminal_name) +Reinitialize Readline's idea of the terminal settings using +@var{terminal_name} as the terminal type (e.g., @code{vt100}). +If @var{terminal_name} is @code{NULL}, the value of the @code{TERM} +environment variable is used. +@end deftypefun + +@node Utility Functions +@subsection Utility Functions + +@deftypefun void rl_replace_line (const char *text, int clear_undo) +Replace the contents of @code{rl_line_buffer} with @var{text}. +The point and mark are preserved, if possible. +If @var{clear_undo} is non-zero, the undo list associated with the +current line is cleared. +@end deftypefun + +@deftypefun int rl_extend_line_buffer (int len) +Ensure that @code{rl_line_buffer} has enough space to hold @var{len} +characters, possibly reallocating it if necessary. +@end deftypefun + +@deftypefun int rl_initialize (void) +Initialize or re-initialize Readline's internal state. +It's not strictly necessary to call this; @code{readline()} calls it before +reading any input. +@end deftypefun + +@deftypefun int rl_ding (void) +Ring the terminal bell, obeying the setting of @code{bell-style}. +@end deftypefun + +@deftypefun int rl_alphabetic (int c) +Return 1 if @var{c} is an alphabetic character. +@end deftypefun + +@deftypefun void rl_display_match_list (char **matches, int len, int max) +A convenience function for displaying a list of strings in +columnar format on Readline's output stream. @code{matches} is the list +of strings, in argv format, such as a list of completion matches. +@code{len} is the number of strings in @code{matches}, and @code{max} +is the length of the longest string in @code{matches}. This function uses +the setting of @code{print-completions-horizontally} to select how the +matches are displayed (@pxref{Readline Init File Syntax}). +@end deftypefun + +The following are implemented as macros, defined in @code{chardefs.h}. +Applications should refrain from using them. + +@deftypefun int _rl_uppercase_p (int c) +Return 1 if @var{c} is an uppercase alphabetic character. +@end deftypefun + +@deftypefun int _rl_lowercase_p (int c) +Return 1 if @var{c} is a lowercase alphabetic character. +@end deftypefun + +@deftypefun int _rl_digit_p (int c) +Return 1 if @var{c} is a numeric character. +@end deftypefun + +@deftypefun int _rl_to_upper (int c) +If @var{c} is a lowercase alphabetic character, return the corresponding +uppercase character. +@end deftypefun + +@deftypefun int _rl_to_lower (int c) +If @var{c} is an uppercase alphabetic character, return the corresponding +lowercase character. +@end deftypefun + +@deftypefun int _rl_digit_value (int c) +If @var{c} is a number, return the value it represents. +@end deftypefun + +@node Miscellaneous Functions +@subsection Miscellaneous Functions + +@deftypefun int rl_macro_bind (const char *keyseq, const char *macro, Keymap map) +Bind the key sequence @var{keyseq} to invoke the macro @var{macro}. +The binding is performed in @var{map}. When @var{keyseq} is invoked, the +@var{macro} will be inserted into the line. This function is deprecated; +use @code{rl_generic_bind()} instead. +@end deftypefun + +@deftypefun void rl_macro_dumper (int readable) +Print the key sequences bound to macros and their values, using +the current keymap, to @code{rl_outstream}. +If @var{readable} is non-zero, the list is formatted in such a way +that it can be made part of an @code{inputrc} file and re-read. +@end deftypefun + +@deftypefun int rl_variable_bind (const char *variable, const char *value) +Make the Readline variable @var{variable} have @var{value}. +This behaves as if the readline command +@samp{set @var{variable} @var{value}} had been executed in an @code{inputrc} +file (@pxref{Readline Init File Syntax}). +@end deftypefun + +@deftypefun {char *} rl_variable_value (const char *variable) +Return a string representing the value of the Readline variable @var{variable}. +For boolean variables, this string is either @samp{on} or @samp{off}. +@end deftypefun + +@deftypefun void rl_variable_dumper (int readable) +Print the readline variable names and their current values +to @code{rl_outstream}. +If @var{readable} is non-zero, the list is formatted in such a way +that it can be made part of an @code{inputrc} file and re-read. +@end deftypefun + +@deftypefun int rl_set_paren_blink_timeout (int u) +Set the time interval (in microseconds) that Readline waits when showing +a balancing character when @code{blink-matching-paren} has been enabled. +@end deftypefun + +@deftypefun {char *} rl_get_termcap (const char *cap) +Retrieve the string value of the termcap capability @var{cap}. +Readline fetches the termcap entry for the current terminal name and +uses those capabilities to move around the screen line and perform other +terminal-specific operations, like erasing a line. Readline does not +use all of a terminal's capabilities, and this function will return +values for only those capabilities Readline uses. +@end deftypefun + +@node Alternate Interface +@subsection Alternate Interface + +An alternate interface is available to plain @code{readline()}. Some +applications need to interleave keyboard I/O with file, device, or +window system I/O, typically by using a main loop to @code{select()} +on various file descriptors. To accomodate this need, readline can +also be invoked as a `callback' function from an event loop. There +are functions available to make this easy. + +@deftypefun void rl_callback_handler_install (const char *prompt, rl_vcpfunc_t *lhandler) +Set up the terminal for readline I/O and display the initial +expanded value of @var{prompt}. Save the value of @var{lhandler} to +use as a function to call when a complete line of input has been entered. +The function takes the text of the line as an argument. +@end deftypefun + +@deftypefun void rl_callback_read_char (void) +Whenever an application determines that keyboard input is available, it +should call @code{rl_callback_read_char()}, which will read the next +character from the current input source. +If that character completes the line, @code{rl_callback_read_char} will +invoke the @var{lhandler} function saved by @code{rl_callback_handler_install} +to process the line. +Before calling the @var{lhandler} function, the terminal settings are +reset to the values they had before calling +@code{rl_callback_handler_install}. +If the @var{lhandler} function returns, +the terminal settings are modified for Readline's use again. +@code{EOF} is indicated by calling @var{lhandler} with a +@code{NULL} line. +@end deftypefun + +@deftypefun void rl_callback_handler_remove (void) +Restore the terminal to its initial state and remove the line handler. +This may be called from within a callback as well as independently. +If the @var{lhandler} installed by @code{rl_callback_handler_install} +does not exit the program, either this function or the function referred +to by the value of @code{rl_deprep_term_function} should be called before +the program exits to reset the terminal settings. +@end deftypefun + +@node A Readline Example +@subsection A Readline Example + +Here is a function which changes lowercase characters to their uppercase +equivalents, and uppercase characters to lowercase. If +this function was bound to @samp{M-c}, then typing @samp{M-c} would +change the case of the character under point. Typing @samp{M-1 0 M-c} +would change the case of the following 10 characters, leaving the cursor on +the last character changed. + +@example +/* Invert the case of the COUNT following characters. */ +int +invert_case_line (count, key) + int count, key; +@{ + register int start, end, i; + + start = rl_point; + + if (rl_point >= rl_end) + return (0); + + if (count < 0) + @{ + direction = -1; + count = -count; + @} + else + direction = 1; + + /* Find the end of the range to modify. */ + end = start + (count * direction); + + /* Force it to be within range. */ + if (end > rl_end) + end = rl_end; + else if (end < 0) + end = 0; + + if (start == end) + return (0); + + if (start > end) + @{ + int temp = start; + start = end; + end = temp; + @} + + /* Tell readline that we are modifying the line, + so it will save the undo information. */ + rl_modifying (start, end); + + for (i = start; i != end; i++) + @{ + if (_rl_uppercase_p (rl_line_buffer[i])) + rl_line_buffer[i] = _rl_to_lower (rl_line_buffer[i]); + else if (_rl_lowercase_p (rl_line_buffer[i])) + rl_line_buffer[i] = _rl_to_upper (rl_line_buffer[i]); + @} + /* Move point to on top of the last character changed. */ + rl_point = (direction == 1) ? end - 1 : start; + return (0); +@} +@end example + +@node Readline Signal Handling +@section Readline Signal Handling + +Signals are asynchronous events sent to a process by the Unix kernel, +sometimes on behalf of another process. They are intended to indicate +exceptional events, like a user pressing the interrupt key on his terminal, +or a network connection being broken. There is a class of signals that can +be sent to the process currently reading input from the keyboard. Since +Readline changes the terminal attributes when it is called, it needs to +perform special processing when such a signal is received in order to +restore the terminal to a sane state, or provide application writers with +functions to do so manually. + +Readline contains an internal signal handler that is installed for a +number of signals (@code{SIGINT}, @code{SIGQUIT}, @code{SIGTERM}, +@code{SIGALRM}, @code{SIGTSTP}, @code{SIGTTIN}, and @code{SIGTTOU}). +When one of these signals is received, the signal handler +will reset the terminal attributes to those that were in effect before +@code{readline()} was called, reset the signal handling to what it was +before @code{readline()} was called, and resend the signal to the calling +application. +If and when the calling application's signal handler returns, Readline +will reinitialize the terminal and continue to accept input. +When a @code{SIGINT} is received, the Readline signal handler performs +some additional work, which will cause any partially-entered line to be +aborted (see the description of @code{rl_free_line_state()} below). + +There is an additional Readline signal handler, for @code{SIGWINCH}, which +the kernel sends to a process whenever the terminal's size changes (for +example, if a user resizes an @code{xterm}). The Readline @code{SIGWINCH} +handler updates Readline's internal screen size information, and then calls +any @code{SIGWINCH} signal handler the calling application has installed. +Readline calls the application's @code{SIGWINCH} signal handler without +resetting the terminal to its original state. If the application's signal +handler does more than update its idea of the terminal size and return (for +example, a @code{longjmp} back to a main processing loop), it @emph{must} +call @code{rl_cleanup_after_signal()} (described below), to restore the +terminal state. + +Readline provides two variables that allow application writers to +control whether or not it will catch certain signals and act on them +when they are received. It is important that applications change the +values of these variables only when calling @code{readline()}, not in +a signal handler, so Readline's internal signal state is not corrupted. + +@deftypevar int rl_catch_signals +If this variable is non-zero, Readline will install signal handlers for +@code{SIGINT}, @code{SIGQUIT}, @code{SIGTERM}, @code{SIGALRM}, +@code{SIGTSTP}, @code{SIGTTIN}, and @code{SIGTTOU}. + +The default value of @code{rl_catch_signals} is 1. +@end deftypevar + +@deftypevar int rl_catch_sigwinch +If this variable is non-zero, Readline will install a signal handler for +@code{SIGWINCH}. + +The default value of @code{rl_catch_sigwinch} is 1. +@end deftypevar + +If an application does not wish to have Readline catch any signals, or +to handle signals other than those Readline catches (@code{SIGHUP}, +for example), +Readline provides convenience functions to do the necessary terminal +and internal state cleanup upon receipt of a signal. + +@deftypefun void rl_cleanup_after_signal (void) +This function will reset the state of the terminal to what it was before +@code{readline()} was called, and remove the Readline signal handlers for +all signals, depending on the values of @code{rl_catch_signals} and +@code{rl_catch_sigwinch}. +@end deftypefun + +@deftypefun void rl_free_line_state (void) +This will free any partial state associated with the current input line +(undo information, any partial history entry, any partially-entered +keyboard macro, and any partially-entered numeric argument). This +should be called before @code{rl_cleanup_after_signal()}. The +Readline signal handler for @code{SIGINT} calls this to abort the +current input line. +@end deftypefun + +@deftypefun void rl_reset_after_signal (void) +This will reinitialize the terminal and reinstall any Readline signal +handlers, depending on the values of @code{rl_catch_signals} and +@code{rl_catch_sigwinch}. +@end deftypefun + +If an application does not wish Readline to catch @code{SIGWINCH}, it may +call @code{rl_resize_terminal()} or @code{rl_set_screen_size()} to force +Readline to update its idea of the terminal size when a @code{SIGWINCH} +is received. + +@deftypefun void rl_resize_terminal (void) +Update Readline's internal screen size by reading values from the kernel. +@end deftypefun + +@deftypefun void rl_set_screen_size (int rows, int cols) +Set Readline's idea of the terminal size to @var{rows} rows and +@var{cols} columns. If either @var{rows} or @var{columns} is less than +or equal to 0, Readline's idea of that terminal dimension is unchanged. +@end deftypefun + +If an application does not want to install a @code{SIGWINCH} handler, but +is still interested in the screen dimensions, Readline's idea of the screen +size may be queried. + +@deftypefun void rl_get_screen_size (int *rows, int *cols) +Return Readline's idea of the terminal's size in the +variables pointed to by the arguments. +@end deftypefun + +@deftypefun void rl_reset_screen_size (void) +Cause Readline to reobtain the screen size and recalculate its dimensions. +@end deftypefun + +The following functions install and remove Readline's signal handlers. + +@deftypefun int rl_set_signals (void) +Install Readline's signal handler for @code{SIGINT}, @code{SIGQUIT}, +@code{SIGTERM}, @code{SIGALRM}, @code{SIGTSTP}, @code{SIGTTIN}, +@code{SIGTTOU}, and @code{SIGWINCH}, depending on the values of +@code{rl_catch_signals} and @code{rl_catch_sigwinch}. +@end deftypefun + +@deftypefun int rl_clear_signals (void) +Remove all of the Readline signal handlers installed by +@code{rl_set_signals()}. +@end deftypefun + +@node Custom Completers +@section Custom Completers +@cindex application-specific completion functions + +Typically, a program that reads commands from the user has a way of +disambiguating commands and data. If your program is one of these, then +it can provide completion for commands, data, or both. +The following sections describe how your program and Readline +cooperate to provide this service. + +@menu +* How Completing Works:: The logic used to do completion. +* Completion Functions:: Functions provided by Readline. +* Completion Variables:: Variables which control completion. +* A Short Completion Example:: An example of writing completer subroutines. +@end menu + +@node How Completing Works +@subsection How Completing Works + +In order to complete some text, the full list of possible completions +must be available. That is, it is not possible to accurately +expand a partial word without knowing all of the possible words +which make sense in that context. The Readline library provides +the user interface to completion, and two of the most common +completion functions: filename and username. For completing other types +of text, you must write your own completion function. This section +describes exactly what such functions must do, and provides an example. + +There are three major functions used to perform completion: + +@enumerate +@item +The user-interface function @code{rl_complete()}. This function is +called with the same arguments as other bindable Readline functions: +@var{count} and @var{invoking_key}. +It isolates the word to be completed and calls +@code{rl_completion_matches()} to generate a list of possible completions. +It then either lists the possible completions, inserts the possible +completions, or actually performs the +completion, depending on which behavior is desired. + +@item +The internal function @code{rl_completion_matches()} uses an +application-supplied @dfn{generator} function to generate the list of +possible matches, and then returns the array of these matches. +The caller should place the address of its generator function in +@code{rl_completion_entry_function}. + +@item +The generator function is called repeatedly from +@code{rl_completion_matches()}, returning a string each time. The +arguments to the generator function are @var{text} and @var{state}. +@var{text} is the partial word to be completed. @var{state} is zero the +first time the function is called, allowing the generator to perform +any necessary initialization, and a positive non-zero integer for +each subsequent call. The generator function returns +@code{(char *)NULL} to inform @code{rl_completion_matches()} that there are +no more possibilities left. Usually the generator function computes the +list of possible completions when @var{state} is zero, and returns them +one at a time on subsequent calls. Each string the generator function +returns as a match must be allocated with @code{malloc()}; Readline +frees the strings when it has finished with them. +Such a generator function is referred to as an +@dfn{application-specific completion function}. + +@end enumerate + +@deftypefun int rl_complete (int ignore, int invoking_key) +Complete the word at or before point. You have supplied the function +that does the initial simple matching selection algorithm (see +@code{rl_completion_matches()}). The default is to do filename completion. +@end deftypefun + +@deftypevar {rl_compentry_func_t *} rl_completion_entry_function +This is a pointer to the generator function for +@code{rl_completion_matches()}. +If the value of @code{rl_completion_entry_function} is +@code{NULL} then the default filename generator +function, @code{rl_filename_completion_function()}, is used. +An @dfn{application-specific completion function} is a function whose +address is assigned to @code{rl_completion_entry_function} and whose +return values are used to generate possible completions. +@end deftypevar + +@node Completion Functions +@subsection Completion Functions + +Here is the complete list of callable completion functions present in +Readline. + +@deftypefun int rl_complete_internal (int what_to_do) +Complete the word at or before point. @var{what_to_do} says what to do +with the completion. A value of @samp{?} means list the possible +completions. @samp{TAB} means do standard completion. @samp{*} means +insert all of the possible completions. @samp{!} means to display +all of the possible completions, if there is more than one, as well as +performing partial completion. @samp{@@} is similar to @samp{!}, but +possible completions are not listed if the possible completions share +a common prefix. +@end deftypefun + +@deftypefun int rl_complete (int ignore, int invoking_key) +Complete the word at or before point. You have supplied the function +that does the initial simple matching selection algorithm (see +@code{rl_completion_matches()} and @code{rl_completion_entry_function}). +The default is to do filename +completion. This calls @code{rl_complete_internal()} with an +argument depending on @var{invoking_key}. +@end deftypefun + +@deftypefun int rl_possible_completions (int count, int invoking_key) +List the possible completions. See description of @code{rl_complete +()}. This calls @code{rl_complete_internal()} with an argument of +@samp{?}. +@end deftypefun + +@deftypefun int rl_insert_completions (int count, int invoking_key) +Insert the list of possible completions into the line, deleting the +partially-completed word. See description of @code{rl_complete()}. +This calls @code{rl_complete_internal()} with an argument of @samp{*}. +@end deftypefun + +@deftypefun int rl_completion_mode (rl_command_func_t *cfunc) +Returns the apppriate value to pass to @code{rl_complete_internal()} +depending on whether @var{cfunc} was called twice in succession and +the values of the @code{show-all-if-ambiguous} and +@code{show-all-if-unmodified} variables. +Application-specific completion functions may use this function to present +the same interface as @code{rl_complete()}. +@end deftypefun + +@deftypefun {char **} rl_completion_matches (const char *text, rl_compentry_func_t *entry_func) +Returns an array of strings which is a list of completions for +@var{text}. If there are no completions, returns @code{NULL}. +The first entry in the returned array is the substitution for @var{text}. +The remaining entries are the possible completions. The array is +terminated with a @code{NULL} pointer. + +@var{entry_func} is a function of two args, and returns a +@code{char *}. The first argument is @var{text}. The second is a +state argument; it is zero on the first call, and non-zero on subsequent +calls. @var{entry_func} returns a @code{NULL} pointer to the caller +when there are no more matches. +@end deftypefun + +@deftypefun {char *} rl_filename_completion_function (const char *text, int state) +A generator function for filename completion in the general case. +@var{text} is a partial filename. +The Bash source is a useful reference for writing application-specific +completion functions (the Bash completion functions call this and other +Readline functions). +@end deftypefun + +@deftypefun {char *} rl_username_completion_function (const char *text, int state) +A completion generator for usernames. @var{text} contains a partial +username preceded by a random character (usually @samp{~}). As with all +completion generators, @var{state} is zero on the first call and non-zero +for subsequent calls. +@end deftypefun + +@node Completion Variables +@subsection Completion Variables + +@deftypevar {rl_compentry_func_t *} rl_completion_entry_function +A pointer to the generator function for @code{rl_completion_matches()}. +@code{NULL} means to use @code{rl_filename_completion_function()}, +the default filename completer. +@end deftypevar + +@deftypevar {rl_completion_func_t *} rl_attempted_completion_function +A pointer to an alternative function to create matches. +The function is called with @var{text}, @var{start}, and @var{end}. +@var{start} and @var{end} are indices in @code{rl_line_buffer} defining +the boundaries of @var{text}, which is a character string. +If this function exists and returns @code{NULL}, or if this variable is +set to @code{NULL}, then @code{rl_complete()} will call the value of +@code{rl_completion_entry_function} to generate matches, otherwise the +array of strings returned will be used. +If this function sets the @code{rl_attempted_completion_over} +variable to a non-zero value, Readline will not perform its default +completion even if this function returns no matches. +@end deftypevar + +@deftypevar {rl_quote_func_t *} rl_filename_quoting_function +A pointer to a function that will quote a filename in an +application-specific fashion. This is called if filename completion is being +attempted and one of the characters in @code{rl_filename_quote_characters} +appears in a completed filename. The function is called with +@var{text}, @var{match_type}, and @var{quote_pointer}. The @var{text} +is the filename to be quoted. The @var{match_type} is either +@code{SINGLE_MATCH}, if there is only one completion match, or +@code{MULT_MATCH}. Some functions use this to decide whether or not to +insert a closing quote character. The @var{quote_pointer} is a pointer +to any opening quote character the user typed. Some functions choose +to reset this character. +@end deftypevar + +@deftypevar {rl_dequote_func_t *} rl_filename_dequoting_function +A pointer to a function that will remove application-specific quoting +characters from a filename before completion is attempted, so those +characters do not interfere with matching the text against names in +the filesystem. It is called with @var{text}, the text of the word +to be dequoted, and @var{quote_char}, which is the quoting character +that delimits the filename (usually @samp{'} or @samp{"}). If +@var{quote_char} is zero, the filename was not in an embedded string. +@end deftypevar + +@deftypevar {rl_linebuf_func_t *} rl_char_is_quoted_p +A pointer to a function to call that determines whether or not a specific +character in the line buffer is quoted, according to whatever quoting +mechanism the program calling Readline uses. The function is called with +two arguments: @var{text}, the text of the line, and @var{index}, the +index of the character in the line. It is used to decide whether a +character found in @code{rl_completer_word_break_characters} should be +used to break words for the completer. +@end deftypevar + +@deftypevar {rl_compignore_func_t *} rl_ignore_some_completions_function +This function, if defined, is called by the completer when real filename +completion is done, after all the matching names have been generated. +It is passed a @code{NULL} terminated array of matches. +The first element (@code{matches[0]}) is the +maximal substring common to all matches. This function can +re-arrange the list of matches as required, but each element deleted +from the array must be freed. +@end deftypevar + +@deftypevar {rl_icppfunc_t *} rl_directory_completion_hook +This function, if defined, is allowed to modify the directory portion +of filenames Readline completes. It is called with the address of a +string (the current directory name) as an argument, and may modify that string. +If the string is replaced with a new string, the old value should be freed. +Any modified directory name should have a trailing slash. +The modified value will be displayed as part of the completion, replacing +the directory portion of the pathname the user typed. +It returns an integer that should be non-zero if the function modifies +its directory argument. +It could be used to expand symbolic links or shell variables in pathnames. +@end deftypevar + +@deftypevar {rl_compdisp_func_t *} rl_completion_display_matches_hook +If non-zero, then this is the address of a function to call when +completing a word would normally display the list of possible matches. +This function is called in lieu of Readline displaying the list. +It takes three arguments: +(@code{char **}@var{matches}, @code{int} @var{num_matches}, @code{int} @var{max_length}) +where @var{matches} is the array of matching strings, +@var{num_matches} is the number of strings in that array, and +@var{max_length} is the length of the longest string in that array. +Readline provides a convenience function, @code{rl_display_match_list}, +that takes care of doing the display to Readline's output stream. That +function may be called from this hook. +@end deftypevar + +@deftypevar {const char *} rl_basic_word_break_characters +The basic list of characters that signal a break between words for the +completer routine. The default value of this variable is the characters +which break words for completion in Bash: +@code{" \t\n\"\\'`@@$><=;|&@{("}. +@end deftypevar + +@deftypevar {const char *} rl_basic_quote_characters +A list of quote characters which can cause a word break. +@end deftypevar + +@deftypevar {const char *} rl_completer_word_break_characters +The list of characters that signal a break between words for +@code{rl_complete_internal()}. The default list is the value of +@code{rl_basic_word_break_characters}. +@end deftypevar + +@deftypevar {rl_cpvfunc_t *} rl_completion_word_break_hook +If non-zero, this is the address of a function to call when Readline is +deciding where to separate words for word completion. It should return +a character string like @code{rl_completer_word_break_characters} to be +used to perform the current completion. The function may choose to set +@code{rl_completer_word_break_characters} itself. If the function +returns @code{NULL}, @code{rl_completer_word_break_characters} is used. +@end deftypevar + +@deftypevar {const char *} rl_completer_quote_characters +A list of characters which can be used to quote a substring of the line. +Completion occurs on the entire substring, and within the substring +@code{rl_completer_word_break_characters} are treated as any other character, +unless they also appear within this list. +@end deftypevar + +@deftypevar {const char *} rl_filename_quote_characters +A list of characters that cause a filename to be quoted by the completer +when they appear in a completed filename. The default is the null string. +@end deftypevar + +@deftypevar {const char *} rl_special_prefixes +The list of characters that are word break characters, but should be +left in @var{text} when it is passed to the completion function. +Programs can use this to help determine what kind of completing to do. +For instance, Bash sets this variable to "$@@" so that it can complete +shell variables and hostnames. +@end deftypevar + +@deftypevar int rl_completion_query_items +Up to this many items will be displayed in response to a +possible-completions call. After that, readline asks the user if she is sure +she wants to see them all. The default value is 100. A negative value +indicates that Readline should never ask the user. +@end deftypevar + +@deftypevar {int} rl_completion_append_character +When a single completion alternative matches at the end of the command +line, this character is appended to the inserted completion text. The +default is a space character (@samp{ }). Setting this to the null +character (@samp{\0}) prevents anything being appended automatically. +This can be changed in application-specific completion functions to +provide the ``most sensible word separator character'' according to +an application-specific command line syntax specification. +@end deftypevar + +@deftypevar int rl_completion_suppress_append +If non-zero, @var{rl_completion_append_character} is not appended to +matches at the end of the command line, as described above. +It is set to 0 before any application-specific completion function +is called, and may only be changed within such a function. +@end deftypevar + +@deftypevar int rl_completion_quote_character +When Readline is completing quoted text, as delimited by one of the +characters in @var{rl_completer_quote_characters}, it sets this variable +to the quoting character found. +This is set before any application-specific completion function is called. +@end deftypevar + +@deftypevar int rl_completion_suppress_quote +If non-zero, Readline does not append a matching quote character when +performing completion on a quoted string. +It is set to 0 before any application-specific completion function +is called, and may only be changed within such a function. +@end deftypevar + +@deftypevar int rl_completion_found_quote +When Readline is completing quoted text, it sets this variable +to a non-zero value if the word being completed contains or is delimited +by any quoting characters, including backslashes. +This is set before any application-specific completion function is called. +@end deftypevar + +@deftypevar int rl_completion_mark_symlink_dirs +If non-zero, a slash will be appended to completed filenames that are +symbolic links to directory names, subject to the value of the +user-settable @var{mark-directories} variable. +This variable exists so that application-specific completion functions +can override the user's global preference (set via the +@var{mark-symlinked-directories} Readline variable) if appropriate. +This variable is set to the user's preference before any +application-specific completion function is called, so unless that +function modifies the value, the user's preferences are honored. +@end deftypevar + +@deftypevar int rl_ignore_completion_duplicates +If non-zero, then duplicates in the matches are removed. +The default is 1. +@end deftypevar + +@deftypevar int rl_filename_completion_desired +Non-zero means that the results of the matches are to be treated as +filenames. This is @emph{always} zero when completion is attempted, +and can only be changed +within an application-specific completion function. If it is set to a +non-zero value by such a function, directory names have a slash appended +and Readline attempts to quote completed filenames if they contain any +characters in @code{rl_filename_quote_characters} and +@code{rl_filename_quoting_desired} is set to a non-zero value. +@end deftypevar + +@deftypevar int rl_filename_quoting_desired +Non-zero means that the results of the matches are to be quoted using +double quotes (or an application-specific quoting mechanism) if the +completed filename contains any characters in +@code{rl_filename_quote_chars}. This is @emph{always} non-zero +when completion is attempted, and can only be changed within an +application-specific completion function. +The quoting is effected via a call to the function pointed to +by @code{rl_filename_quoting_function}. +@end deftypevar + +@deftypevar int rl_attempted_completion_over +If an application-specific completion function assigned to +@code{rl_attempted_completion_function} sets this variable to a non-zero +value, Readline will not perform its default filename completion even +if the application's completion function returns no matches. +It should be set only by an application's completion function. +@end deftypevar + +@deftypevar int rl_completion_type +Set to a character describing the type of completion Readline is currently +attempting; see the description of @code{rl_complete_internal()} +(@pxref{Completion Functions}) for the list of characters. +This is set to the appropriate value before any application-specific +completion function is called, allowing such functions to present +the same interface as @code{rl_complete()}. +@end deftypevar + +@deftypevar int rl_inhibit_completion +If this variable is non-zero, completion is inhibited. The completion +character will be inserted as any other bound to @code{self-insert}. +@end deftypevar + +@node A Short Completion Example +@subsection A Short Completion Example + +Here is a small application demonstrating the use of the GNU Readline +library. It is called @code{fileman}, and the source code resides in +@file{examples/fileman.c}. This sample application provides +completion of command names, line editing features, and access to the +history list. + +@page +@smallexample +/* fileman.c -- A tiny application which demonstrates how to use the + GNU Readline library. This application interactively allows users + to manipulate files and their modes. */ + +#include +#include +#include +#include +#include + +#include +#include + +extern char *xmalloc (); + +/* The names of functions that actually do the manipulation. */ +int com_list __P((char *)); +int com_view __P((char *)); +int com_rename __P((char *)); +int com_stat __P((char *)); +int com_pwd __P((char *)); +int com_delete __P((char *)); +int com_help __P((char *)); +int com_cd __P((char *)); +int com_quit __P((char *)); + +/* A structure which contains information on the commands this program + can understand. */ + +typedef struct @{ + char *name; /* User printable name of the function. */ + rl_icpfunc_t *func; /* Function to call to do the job. */ + char *doc; /* Documentation for this function. */ +@} COMMAND; + +COMMAND commands[] = @{ + @{ "cd", com_cd, "Change to directory DIR" @}, + @{ "delete", com_delete, "Delete FILE" @}, + @{ "help", com_help, "Display this text" @}, + @{ "?", com_help, "Synonym for `help'" @}, + @{ "list", com_list, "List files in DIR" @}, + @{ "ls", com_list, "Synonym for `list'" @}, + @{ "pwd", com_pwd, "Print the current working directory" @}, + @{ "quit", com_quit, "Quit using Fileman" @}, + @{ "rename", com_rename, "Rename FILE to NEWNAME" @}, + @{ "stat", com_stat, "Print out statistics on FILE" @}, + @{ "view", com_view, "View the contents of FILE" @}, + @{ (char *)NULL, (rl_icpfunc_t *)NULL, (char *)NULL @} +@}; + +/* Forward declarations. */ +char *stripwhite (); +COMMAND *find_command (); + +/* The name of this program, as taken from argv[0]. */ +char *progname; + +/* When non-zero, this means the user is done using this program. */ +int done; + +char * +dupstr (s) + int s; +@{ + char *r; + + r = xmalloc (strlen (s) + 1); + strcpy (r, s); + return (r); +@} + +main (argc, argv) + int argc; + char **argv; +@{ + char *line, *s; + + progname = argv[0]; + + initialize_readline (); /* Bind our completer. */ + + /* Loop reading and executing lines until the user quits. */ + for ( ; done == 0; ) + @{ + line = readline ("FileMan: "); + + if (!line) + break; + + /* Remove leading and trailing whitespace from the line. + Then, if there is anything left, add it to the history list + and execute it. */ + s = stripwhite (line); + + if (*s) + @{ + add_history (s); + execute_line (s); + @} + + free (line); + @} + exit (0); +@} + +/* Execute a command line. */ +int +execute_line (line) + char *line; +@{ + register int i; + COMMAND *command; + char *word; + + /* Isolate the command word. */ + i = 0; + while (line[i] && whitespace (line[i])) + i++; + word = line + i; + + while (line[i] && !whitespace (line[i])) + i++; + + if (line[i]) + line[i++] = '\0'; + + command = find_command (word); + + if (!command) + @{ + fprintf (stderr, "%s: No such command for FileMan.\n", word); + return (-1); + @} + + /* Get argument to command, if any. */ + while (whitespace (line[i])) + i++; + + word = line + i; + + /* Call the function. */ + return ((*(command->func)) (word)); +@} + +/* Look up NAME as the name of a command, and return a pointer to that + command. Return a NULL pointer if NAME isn't a command name. */ +COMMAND * +find_command (name) + char *name; +@{ + register int i; + + for (i = 0; commands[i].name; i++) + if (strcmp (name, commands[i].name) == 0) + return (&commands[i]); + + return ((COMMAND *)NULL); +@} + +/* Strip whitespace from the start and end of STRING. Return a pointer + into STRING. */ +char * +stripwhite (string) + char *string; +@{ + register char *s, *t; + + for (s = string; whitespace (*s); s++) + ; + + if (*s == 0) + return (s); + + t = s + strlen (s) - 1; + while (t > s && whitespace (*t)) + t--; + *++t = '\0'; + + return s; +@} + +/* **************************************************************** */ +/* */ +/* Interface to Readline Completion */ +/* */ +/* **************************************************************** */ + +char *command_generator __P((const char *, int)); +char **fileman_completion __P((const char *, int, int)); + +/* Tell the GNU Readline library how to complete. We want to try to + complete on command names if this is the first word in the line, or + on filenames if not. */ +initialize_readline () +@{ + /* Allow conditional parsing of the ~/.inputrc file. */ + rl_readline_name = "FileMan"; + + /* Tell the completer that we want a crack first. */ + rl_attempted_completion_function = fileman_completion; +@} + +/* Attempt to complete on the contents of TEXT. START and END + bound the region of rl_line_buffer that contains the word to + complete. TEXT is the word to complete. We can use the entire + contents of rl_line_buffer in case we want to do some simple + parsing. Returnthe array of matches, or NULL if there aren't any. */ +char ** +fileman_completion (text, start, end) + const char *text; + int start, end; +@{ + char **matches; + + matches = (char **)NULL; + + /* If this word is at the start of the line, then it is a command + to complete. Otherwise it is the name of a file in the current + directory. */ + if (start == 0) + matches = rl_completion_matches (text, command_generator); + + return (matches); +@} + +/* Generator function for command completion. STATE lets us + know whether to start from scratch; without any state + (i.e. STATE == 0), then we start at the top of the list. */ +char * +command_generator (text, state) + const char *text; + int state; +@{ + static int list_index, len; + char *name; + + /* If this is a new word to complete, initialize now. This + includes saving the length of TEXT for efficiency, and + initializing the index variable to 0. */ + if (!state) + @{ + list_index = 0; + len = strlen (text); + @} + + /* Return the next name which partially matches from the + command list. */ + while (name = commands[list_index].name) + @{ + list_index++; + + if (strncmp (name, text, len) == 0) + return (dupstr(name)); + @} + + /* If no names matched, then return NULL. */ + return ((char *)NULL); +@} + +/* **************************************************************** */ +/* */ +/* FileMan Commands */ +/* */ +/* **************************************************************** */ + +/* String to pass to system (). This is for the LIST, VIEW and RENAME + commands. */ +static char syscom[1024]; + +/* List the file(s) named in arg. */ +com_list (arg) + char *arg; +@{ + if (!arg) + arg = ""; + + sprintf (syscom, "ls -FClg %s", arg); + return (system (syscom)); +@} + +com_view (arg) + char *arg; +@{ + if (!valid_argument ("view", arg)) + return 1; + + sprintf (syscom, "more %s", arg); + return (system (syscom)); +@} + +com_rename (arg) + char *arg; +@{ + too_dangerous ("rename"); + return (1); +@} + +com_stat (arg) + char *arg; +@{ + struct stat finfo; + + if (!valid_argument ("stat", arg)) + return (1); + + if (stat (arg, &finfo) == -1) + @{ + perror (arg); + return (1); + @} + + printf ("Statistics for `%s':\n", arg); + + printf ("%s has %d link%s, and is %d byte%s in length.\n", arg, + finfo.st_nlink, + (finfo.st_nlink == 1) ? "" : "s", + finfo.st_size, + (finfo.st_size == 1) ? "" : "s"); + printf ("Inode Last Change at: %s", ctime (&finfo.st_ctime)); + printf (" Last access at: %s", ctime (&finfo.st_atime)); + printf (" Last modified at: %s", ctime (&finfo.st_mtime)); + return (0); +@} + +com_delete (arg) + char *arg; +@{ + too_dangerous ("delete"); + return (1); +@} + +/* Print out help for ARG, or for all of the commands if ARG is + not present. */ +com_help (arg) + char *arg; +@{ + register int i; + int printed = 0; + + for (i = 0; commands[i].name; i++) + @{ + if (!*arg || (strcmp (arg, commands[i].name) == 0)) + @{ + printf ("%s\t\t%s.\n", commands[i].name, commands[i].doc); + printed++; + @} + @} + + if (!printed) + @{ + printf ("No commands match `%s'. Possibilties are:\n", arg); + + for (i = 0; commands[i].name; i++) + @{ + /* Print in six columns. */ + if (printed == 6) + @{ + printed = 0; + printf ("\n"); + @} + + printf ("%s\t", commands[i].name); + printed++; + @} + + if (printed) + printf ("\n"); + @} + return (0); +@} + +/* Change to the directory ARG. */ +com_cd (arg) + char *arg; +@{ + if (chdir (arg) == -1) + @{ + perror (arg); + return 1; + @} + + com_pwd (""); + return (0); +@} + +/* Print out the current working directory. */ +com_pwd (ignore) + char *ignore; +@{ + char dir[1024], *s; + + s = getcwd (dir, sizeof(dir) - 1); + if (s == 0) + @{ + printf ("Error getting pwd: %s\n", dir); + return 1; + @} + + printf ("Current directory is %s\n", dir); + return 0; +@} + +/* The user wishes to quit using this program. Just set DONE + non-zero. */ +com_quit (arg) + char *arg; +@{ + done = 1; + return (0); +@} + +/* Function which tells you that you can't do this. */ +too_dangerous (caller) + char *caller; +@{ + fprintf (stderr, + "%s: Too dangerous for me to distribute.\n", + caller); + fprintf (stderr, "Write it yourself.\n"); +@} + +/* Return non-zero if ARG is a valid argument for CALLER, + else print an error message and return zero. */ +int +valid_argument (caller, arg) + char *caller, *arg; +@{ + if (!arg || !*arg) + @{ + fprintf (stderr, "%s: Argument required.\n", caller); + return (0); + @} + + return (1); +@} +@end smallexample diff --git a/external/gpl3/gdb/dist/readline/doc/rluser.texi b/external/gpl3/gdb/dist/readline/doc/rluser.texi new file mode 100644 index 000000000000..478b41fac3c7 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/rluser.texi @@ -0,0 +1,1846 @@ +@comment %**start of header (This is for running Texinfo on a region.) +@setfilename rluser.info +@comment %**end of header (This is for running Texinfo on a region.) +@setchapternewpage odd + +@ignore +This file documents the end user interface to the GNU command line +editing features. It is to be an appendix to manuals for programs which +use these features. There is a document entitled "readline.texinfo" +which contains both end-user and programmer documentation for the +GNU Readline Library. + +Copyright (C) 1988-2005 Free Software Foundation, Inc. + +Authored by Brian Fox and Chet Ramey. + +Permission is granted to process this file through Tex and print the +results, provided the printed document carries copying permission notice +identical to this one except for the removal of this paragraph (this +paragraph not being relevant to the printed manual). + +Permission is granted to make and distribute verbatim copies of this manual +provided the copyright notice and this permission notice are preserved on +all copies. + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that the +GNU Copyright statement is available to the distributee, and provided that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end ignore + +@comment If you are including this manual as an appendix, then set the +@comment variable readline-appendix. + +@ifclear BashFeatures +@defcodeindex bt +@end ifclear + +@node Command Line Editing +@chapter Command Line Editing + +This chapter describes the basic features of the @sc{gnu} +command line editing interface. +@ifset BashFeatures +Command line editing is provided by the Readline library, which is +used by several different programs, including Bash. +@end ifset + +@menu +* Introduction and Notation:: Notation used in this text. +* Readline Interaction:: The minimum set of commands for editing a line. +* Readline Init File:: Customizing Readline from a user's view. +* Bindable Readline Commands:: A description of most of the Readline commands + available for binding +* Readline vi Mode:: A short description of how to make Readline + behave like the vi editor. +@ifset BashFeatures +* Programmable Completion:: How to specify the possible completions for + a specific command. +* Programmable Completion Builtins:: Builtin commands to specify how to + complete arguments for a particular command. +@end ifset +@end menu + +@node Introduction and Notation +@section Introduction to Line Editing + +The following paragraphs describe the notation used to represent +keystrokes. + +The text @kbd{C-k} is read as `Control-K' and describes the character +produced when the @key{k} key is pressed while the Control key +is depressed. + +The text @kbd{M-k} is read as `Meta-K' and describes the character +produced when the Meta key (if you have one) is depressed, and the @key{k} +key is pressed. +The Meta key is labeled @key{ALT} on many keyboards. +On keyboards with two keys labeled @key{ALT} (usually to either side of +the space bar), the @key{ALT} on the left side is generally set to +work as a Meta key. +The @key{ALT} key on the right may also be configured to work as a +Meta key or may be configured as some other modifier, such as a +Compose key for typing accented characters. + +If you do not have a Meta or @key{ALT} key, or another key working as +a Meta key, the identical keystroke can be generated by typing @key{ESC} +@emph{first}, and then typing @key{k}. +Either process is known as @dfn{metafying} the @key{k} key. + +The text @kbd{M-C-k} is read as `Meta-Control-k' and describes the +character produced by @dfn{metafying} @kbd{C-k}. + +In addition, several keys have their own names. Specifically, +@key{DEL}, @key{ESC}, @key{LFD}, @key{SPC}, @key{RET}, and @key{TAB} all +stand for themselves when seen in this text, or in an init file +(@pxref{Readline Init File}). +If your keyboard lacks a @key{LFD} key, typing @key{C-j} will +produce the desired character. +The @key{RET} key may be labeled @key{Return} or @key{Enter} on +some keyboards. + +@node Readline Interaction +@section Readline Interaction +@cindex interaction, readline + +Often during an interactive session you type in a long line of text, +only to notice that the first word on the line is misspelled. The +Readline library gives you a set of commands for manipulating the text +as you type it in, allowing you to just fix your typo, and not forcing +you to retype the majority of the line. Using these editing commands, +you move the cursor to the place that needs correction, and delete or +insert the text of the corrections. Then, when you are satisfied with +the line, you simply press @key{RET}. You do not have to be at the +end of the line to press @key{RET}; the entire line is accepted +regardless of the location of the cursor within the line. + +@menu +* Readline Bare Essentials:: The least you need to know about Readline. +* Readline Movement Commands:: Moving about the input line. +* Readline Killing Commands:: How to delete text, and how to get it back! +* Readline Arguments:: Giving numeric arguments to commands. +* Searching:: Searching through previous lines. +@end menu + +@node Readline Bare Essentials +@subsection Readline Bare Essentials +@cindex notation, readline +@cindex command editing +@cindex editing command lines + +In order to enter characters into the line, simply type them. The typed +character appears where the cursor was, and then the cursor moves one +space to the right. If you mistype a character, you can use your +erase character to back up and delete the mistyped character. + +Sometimes you may mistype a character, and +not notice the error until you have typed several other characters. In +that case, you can type @kbd{C-b} to move the cursor to the left, and then +correct your mistake. Afterwards, you can move the cursor to the right +with @kbd{C-f}. + +When you add text in the middle of a line, you will notice that characters +to the right of the cursor are `pushed over' to make room for the text +that you have inserted. Likewise, when you delete text behind the cursor, +characters to the right of the cursor are `pulled back' to fill in the +blank space created by the removal of the text. A list of the bare +essentials for editing the text of an input line follows. + +@table @asis +@item @kbd{C-b} +Move back one character. +@item @kbd{C-f} +Move forward one character. +@item @key{DEL} or @key{Backspace} +Delete the character to the left of the cursor. +@item @kbd{C-d} +Delete the character underneath the cursor. +@item @w{Printing characters} +Insert the character into the line at the cursor. +@item @kbd{C-_} or @kbd{C-x C-u} +Undo the last editing command. You can undo all the way back to an +empty line. +@end table + +@noindent +(Depending on your configuration, the @key{Backspace} key be set to +delete the character to the left of the cursor and the @key{DEL} key set +to delete the character underneath the cursor, like @kbd{C-d}, rather +than the character to the left of the cursor.) + +@node Readline Movement Commands +@subsection Readline Movement Commands + + +The above table describes the most basic keystrokes that you need +in order to do editing of the input line. For your convenience, many +other commands have been added in addition to @kbd{C-b}, @kbd{C-f}, +@kbd{C-d}, and @key{DEL}. Here are some commands for moving more rapidly +about the line. + +@table @kbd +@item C-a +Move to the start of the line. +@item C-e +Move to the end of the line. +@item M-f +Move forward a word, where a word is composed of letters and digits. +@item M-b +Move backward a word. +@item C-l +Clear the screen, reprinting the current line at the top. +@end table + +Notice how @kbd{C-f} moves forward a character, while @kbd{M-f} moves +forward a word. It is a loose convention that control keystrokes +operate on characters while meta keystrokes operate on words. + +@node Readline Killing Commands +@subsection Readline Killing Commands + +@cindex killing text +@cindex yanking text + +@dfn{Killing} text means to delete the text from the line, but to save +it away for later use, usually by @dfn{yanking} (re-inserting) +it back into the line. +(`Cut' and `paste' are more recent jargon for `kill' and `yank'.) + +If the description for a command says that it `kills' text, then you can +be sure that you can get the text back in a different (or the same) +place later. + +When you use a kill command, the text is saved in a @dfn{kill-ring}. +Any number of consecutive kills save all of the killed text together, so +that when you yank it back, you get it all. The kill +ring is not line specific; the text that you killed on a previously +typed line is available to be yanked back later, when you are typing +another line. +@cindex kill ring + +Here is the list of commands for killing text. + +@table @kbd +@item C-k +Kill the text from the current cursor position to the end of the line. + +@item M-d +Kill from the cursor to the end of the current word, or, if between +words, to the end of the next word. +Word boundaries are the same as those used by @kbd{M-f}. + +@item M-@key{DEL} +Kill from the cursor the start of the current word, or, if between +words, to the start of the previous word. +Word boundaries are the same as those used by @kbd{M-b}. + +@item C-w +Kill from the cursor to the previous whitespace. This is different than +@kbd{M-@key{DEL}} because the word boundaries differ. + +@end table + +Here is how to @dfn{yank} the text back into the line. Yanking +means to copy the most-recently-killed text from the kill buffer. + +@table @kbd +@item C-y +Yank the most recently killed text back into the buffer at the cursor. + +@item M-y +Rotate the kill-ring, and yank the new top. You can only do this if +the prior command is @kbd{C-y} or @kbd{M-y}. +@end table + +@node Readline Arguments +@subsection Readline Arguments + +You can pass numeric arguments to Readline commands. Sometimes the +argument acts as a repeat count, other times it is the @i{sign} of the +argument that is significant. If you pass a negative argument to a +command which normally acts in a forward direction, that command will +act in a backward direction. For example, to kill text back to the +start of the line, you might type @samp{M-- C-k}. + +The general way to pass numeric arguments to a command is to type meta +digits before the command. If the first `digit' typed is a minus +sign (@samp{-}), then the sign of the argument will be negative. Once +you have typed one meta digit to get the argument started, you can type +the remainder of the digits, and then the command. For example, to give +the @kbd{C-d} command an argument of 10, you could type @samp{M-1 0 C-d}, +which will delete the next ten characters on the input line. + +@node Searching +@subsection Searching for Commands in the History + +Readline provides commands for searching through the command history +@ifset BashFeatures +(@pxref{Bash History Facilities}) +@end ifset +for lines containing a specified string. +There are two search modes: @dfn{incremental} and @dfn{non-incremental}. + +Incremental searches begin before the user has finished typing the +search string. +As each character of the search string is typed, Readline displays +the next entry from the history matching the string typed so far. +An incremental search requires only as many characters as needed to +find the desired history entry. +To search backward in the history for a particular string, type +@kbd{C-r}. Typing @kbd{C-s} searches forward through the history. +The characters present in the value of the @code{isearch-terminators} variable +are used to terminate an incremental search. +If that variable has not been assigned a value, the @key{ESC} and +@kbd{C-J} characters will terminate an incremental search. +@kbd{C-g} will abort an incremental search and restore the original line. +When the search is terminated, the history entry containing the +search string becomes the current line. + +To find other matching entries in the history list, type @kbd{C-r} or +@kbd{C-s} as appropriate. +This will search backward or forward in the history for the next +entry matching the search string typed so far. +Any other key sequence bound to a Readline command will terminate +the search and execute that command. +For instance, a @key{RET} will terminate the search and accept +the line, thereby executing the command from the history list. +A movement command will terminate the search, make the last line found +the current line, and begin editing. + +Readline remembers the last incremental search string. If two +@kbd{C-r}s are typed without any intervening characters defining a new +search string, any remembered search string is used. + +Non-incremental searches read the entire search string before starting +to search for matching history lines. The search string may be +typed by the user or be part of the contents of the current line. + +@node Readline Init File +@section Readline Init File +@cindex initialization file, readline + +Although the Readline library comes with a set of Emacs-like +keybindings installed by default, it is possible to use a different set +of keybindings. +Any user can customize programs that use Readline by putting +commands in an @dfn{inputrc} file, conventionally in his home directory. +The name of this +@ifset BashFeatures +file is taken from the value of the shell variable @env{INPUTRC}. If +@end ifset +@ifclear BashFeatures +file is taken from the value of the environment variable @env{INPUTRC}. If +@end ifclear +that variable is unset, the default is @file{~/.inputrc}. + +When a program which uses the Readline library starts up, the +init file is read, and the key bindings are set. + +In addition, the @code{C-x C-r} command re-reads this init file, thus +incorporating any changes that you might have made to it. + +@menu +* Readline Init File Syntax:: Syntax for the commands in the inputrc file. + +* Conditional Init Constructs:: Conditional key bindings in the inputrc file. + +* Sample Init File:: An example inputrc file. +@end menu + +@node Readline Init File Syntax +@subsection Readline Init File Syntax + +There are only a few basic constructs allowed in the +Readline init file. Blank lines are ignored. +Lines beginning with a @samp{#} are comments. +Lines beginning with a @samp{$} indicate conditional +constructs (@pxref{Conditional Init Constructs}). Other lines +denote variable settings and key bindings. + +@table @asis +@item Variable Settings +You can modify the run-time behavior of Readline by +altering the values of variables in Readline +using the @code{set} command within the init file. +The syntax is simple: + +@example +set @var{variable} @var{value} +@end example + +@noindent +Here, for example, is how to +change from the default Emacs-like key binding to use +@code{vi} line editing commands: + +@example +set editing-mode vi +@end example + +Variable names and values, where appropriate, are recognized without regard +to case. Unrecognized variable names are ignored. + +Boolean variables (those that can be set to on or off) are set to on if +the value is null or empty, @var{on} (case-insensitive), or 1. Any other +value results in the variable being set to off. + +@ifset BashFeatures +The @w{@code{bind -V}} command lists the current Readline variable names +and values. @xref{Bash Builtins}. +@end ifset + +A great deal of run-time behavior is changeable with the following +variables. + +@cindex variables, readline +@table @code + +@item bell-style +@vindex bell-style +Controls what happens when Readline wants to ring the terminal bell. +If set to @samp{none}, Readline never rings the bell. If set to +@samp{visible}, Readline uses a visible bell if one is available. +If set to @samp{audible} (the default), Readline attempts to ring +the terminal's bell. + +@item bind-tty-special-chars +@vindex bind-tty-special-chars +If set to @samp{on}, Readline attempts to bind the control characters +treated specially by the kernel's terminal driver to their Readline +equivalents. + +@item comment-begin +@vindex comment-begin +The string to insert at the beginning of the line when the +@code{insert-comment} command is executed. The default value +is @code{"#"}. + +@item completion-ignore-case +If set to @samp{on}, Readline performs filename matching and completion +in a case-insensitive fashion. +The default value is @samp{off}. + +@item completion-query-items +@vindex completion-query-items +The number of possible completions that determines when the user is +asked whether the list of possibilities should be displayed. +If the number of possible completions is greater than this value, +Readline will ask the user whether or not he wishes to view +them; otherwise, they are simply listed. +This variable must be set to an integer value greater than or equal to 0. +A negative value means Readline should never ask. +The default limit is @code{100}. + +@item convert-meta +@vindex convert-meta +If set to @samp{on}, Readline will convert characters with the +eighth bit set to an @sc{ascii} key sequence by stripping the eighth +bit and prefixing an @key{ESC} character, converting them to a +meta-prefixed key sequence. The default value is @samp{on}. + +@item disable-completion +@vindex disable-completion +If set to @samp{On}, Readline will inhibit word completion. +Completion characters will be inserted into the line as if they had +been mapped to @code{self-insert}. The default is @samp{off}. + +@item editing-mode +@vindex editing-mode +The @code{editing-mode} variable controls which default set of +key bindings is used. By default, Readline starts up in Emacs editing +mode, where the keystrokes are most similar to Emacs. This variable can be +set to either @samp{emacs} or @samp{vi}. + +@item enable-keypad +@vindex enable-keypad +When set to @samp{on}, Readline will try to enable the application +keypad when it is called. Some systems need this to enable the +arrow keys. The default is @samp{off}. + +@item expand-tilde +@vindex expand-tilde +If set to @samp{on}, tilde expansion is performed when Readline +attempts word completion. The default is @samp{off}. + +@item history-preserve-point +@vindex history-preserve-point +If set to @samp{on}, the history code attempts to place point at the +same location on each history line retrieved with @code{previous-history} +or @code{next-history}. The default is @samp{off}. + +@item horizontal-scroll-mode +@vindex horizontal-scroll-mode +This variable can be set to either @samp{on} or @samp{off}. Setting it +to @samp{on} means that the text of the lines being edited will scroll +horizontally on a single screen line when they are longer than the width +of the screen, instead of wrapping onto a new screen line. By default, +this variable is set to @samp{off}. + +@item input-meta +@vindex input-meta +@vindex meta-flag +If set to @samp{on}, Readline will enable eight-bit input (it +will not clear the eighth bit in the characters it reads), +regardless of what the terminal claims it can support. The +default value is @samp{off}. The name @code{meta-flag} is a +synonym for this variable. + +@item isearch-terminators +@vindex isearch-terminators +The string of characters that should terminate an incremental search without +subsequently executing the character as a command (@pxref{Searching}). +If this variable has not been given a value, the characters @key{ESC} and +@kbd{C-J} will terminate an incremental search. + +@item keymap +@vindex keymap +Sets Readline's idea of the current keymap for key binding commands. +Acceptable @code{keymap} names are +@code{emacs}, +@code{emacs-standard}, +@code{emacs-meta}, +@code{emacs-ctlx}, +@code{vi}, +@code{vi-move}, +@code{vi-command}, and +@code{vi-insert}. +@code{vi} is equivalent to @code{vi-command}; @code{emacs} is +equivalent to @code{emacs-standard}. The default value is @code{emacs}. +The value of the @code{editing-mode} variable also affects the +default keymap. + +@item mark-directories +If set to @samp{on}, completed directory names have a slash +appended. The default is @samp{on}. + +@item mark-modified-lines +@vindex mark-modified-lines +This variable, when set to @samp{on}, causes Readline to display an +asterisk (@samp{*}) at the start of history lines which have been modified. +This variable is @samp{off} by default. + +@item mark-symlinked-directories +@vindex mark-symlinked-directories +If set to @samp{on}, completed names which are symbolic links +to directories have a slash appended (subject to the value of +@code{mark-directories}). +The default is @samp{off}. + +@item match-hidden-files +@vindex match-hidden-files +This variable, when set to @samp{on}, causes Readline to match files whose +names begin with a @samp{.} (hidden files) when performing filename +completion, unless the leading @samp{.} is +supplied by the user in the filename to be completed. +This variable is @samp{on} by default. + +@item output-meta +@vindex output-meta +If set to @samp{on}, Readline will display characters with the +eighth bit set directly rather than as a meta-prefixed escape +sequence. The default is @samp{off}. + +@item page-completions +@vindex page-completions +If set to @samp{on}, Readline uses an internal @code{more}-like pager +to display a screenful of possible completions at a time. +This variable is @samp{on} by default. + +@item print-completions-horizontally +If set to @samp{on}, Readline will display completions with matches +sorted horizontally in alphabetical order, rather than down the screen. +The default is @samp{off}. + +@item show-all-if-ambiguous +@vindex show-all-if-ambiguous +This alters the default behavior of the completion functions. If +set to @samp{on}, +words which have more than one possible completion cause the +matches to be listed immediately instead of ringing the bell. +The default value is @samp{off}. + +@item show-all-if-unmodified +@vindex show-all-if-unmodified +This alters the default behavior of the completion functions in +a fashion similar to @var{show-all-if-ambiguous}. +If set to @samp{on}, +words which have more than one possible completion without any +possible partial completion (the possible completions don't share +a common prefix) cause the matches to be listed immediately instead +of ringing the bell. +The default value is @samp{off}. + +@item visible-stats +@vindex visible-stats +If set to @samp{on}, a character denoting a file's type +is appended to the filename when listing possible +completions. The default is @samp{off}. + +@end table + +@item Key Bindings +The syntax for controlling key bindings in the init file is +simple. First you need to find the name of the command that you +want to change. The following sections contain tables of the command +name, the default keybinding, if any, and a short description of what +the command does. + +Once you know the name of the command, simply place on a line +in the init file the name of the key +you wish to bind the command to, a colon, and then the name of the +command. The name of the key +can be expressed in different ways, depending on what you find most +comfortable. + +In addition to command names, readline allows keys to be bound +to a string that is inserted when the key is pressed (a @var{macro}). + +@ifset BashFeatures +The @w{@code{bind -p}} command displays Readline function names and +bindings in a format that can put directly into an initialization file. +@xref{Bash Builtins}. +@end ifset + +@table @asis +@item @w{@var{keyname}: @var{function-name} or @var{macro}} +@var{keyname} is the name of a key spelled out in English. For example: +@example +Control-u: universal-argument +Meta-Rubout: backward-kill-word +Control-o: "> output" +@end example + +In the above example, @kbd{C-u} is bound to the function +@code{universal-argument}, +@kbd{M-DEL} is bound to the function @code{backward-kill-word}, and +@kbd{C-o} is bound to run the macro +expressed on the right hand side (that is, to insert the text +@samp{> output} into the line). + +A number of symbolic character names are recognized while +processing this key binding syntax: +@var{DEL}, +@var{ESC}, +@var{ESCAPE}, +@var{LFD}, +@var{NEWLINE}, +@var{RET}, +@var{RETURN}, +@var{RUBOUT}, +@var{SPACE}, +@var{SPC}, +and +@var{TAB}. + +@item @w{"@var{keyseq}": @var{function-name} or @var{macro}} +@var{keyseq} differs from @var{keyname} above in that strings +denoting an entire key sequence can be specified, by placing +the key sequence in double quotes. Some @sc{gnu} Emacs style key +escapes can be used, as in the following example, but the +special character names are not recognized. + +@example +"\C-u": universal-argument +"\C-x\C-r": re-read-init-file +"\e[11~": "Function Key 1" +@end example + +In the above example, @kbd{C-u} is again bound to the function +@code{universal-argument} (just as it was in the first example), +@samp{@kbd{C-x} @kbd{C-r}} is bound to the function @code{re-read-init-file}, +and @samp{@key{ESC} @key{[} @key{1} @key{1} @key{~}} is bound to insert +the text @samp{Function Key 1}. + +@end table + +The following @sc{gnu} Emacs style escape sequences are available when +specifying key sequences: + +@table @code +@item @kbd{\C-} +control prefix +@item @kbd{\M-} +meta prefix +@item @kbd{\e} +an escape character +@item @kbd{\\} +backslash +@item @kbd{\"} +@key{"}, a double quotation mark +@item @kbd{\'} +@key{'}, a single quote or apostrophe +@end table + +In addition to the @sc{gnu} Emacs style escape sequences, a second +set of backslash escapes is available: + +@table @code +@item \a +alert (bell) +@item \b +backspace +@item \d +delete +@item \f +form feed +@item \n +newline +@item \r +carriage return +@item \t +horizontal tab +@item \v +vertical tab +@item \@var{nnn} +the eight-bit character whose value is the octal value @var{nnn} +(one to three digits) +@item \x@var{HH} +the eight-bit character whose value is the hexadecimal value @var{HH} +(one or two hex digits) +@end table + +When entering the text of a macro, single or double quotes must +be used to indicate a macro definition. +Unquoted text is assumed to be a function name. +In the macro body, the backslash escapes described above are expanded. +Backslash will quote any other character in the macro text, +including @samp{"} and @samp{'}. +For example, the following binding will make @samp{@kbd{C-x} \} +insert a single @samp{\} into the line: +@example +"\C-x\\": "\\" +@end example + +@end table + +@node Conditional Init Constructs +@subsection Conditional Init Constructs + +Readline implements a facility similar in spirit to the conditional +compilation features of the C preprocessor which allows key +bindings and variable settings to be performed as the result +of tests. There are four parser directives used. + +@table @code +@item $if +The @code{$if} construct allows bindings to be made based on the +editing mode, the terminal being used, or the application using +Readline. The text of the test extends to the end of the line; +no characters are required to isolate it. + +@table @code +@item mode +The @code{mode=} form of the @code{$if} directive is used to test +whether Readline is in @code{emacs} or @code{vi} mode. +This may be used in conjunction +with the @samp{set keymap} command, for instance, to set bindings in +the @code{emacs-standard} and @code{emacs-ctlx} keymaps only if +Readline is starting out in @code{emacs} mode. + +@item term +The @code{term=} form may be used to include terminal-specific +key bindings, perhaps to bind the key sequences output by the +terminal's function keys. The word on the right side of the +@samp{=} is tested against both the full name of the terminal and +the portion of the terminal name before the first @samp{-}. This +allows @code{sun} to match both @code{sun} and @code{sun-cmd}, +for instance. + +@item application +The @var{application} construct is used to include +application-specific settings. Each program using the Readline +library sets the @var{application name}, and you can test for +a particular value. +This could be used to bind key sequences to functions useful for +a specific program. For instance, the following command adds a +key sequence that quotes the current or previous word in Bash: +@example +$if Bash +# Quote the current or previous word +"\C-xq": "\eb\"\ef\"" +$endif +@end example +@end table + +@item $endif +This command, as seen in the previous example, terminates an +@code{$if} command. + +@item $else +Commands in this branch of the @code{$if} directive are executed if +the test fails. + +@item $include +This directive takes a single filename as an argument and reads commands +and bindings from that file. +For example, the following directive reads from @file{/etc/inputrc}: +@example +$include /etc/inputrc +@end example +@end table + +@node Sample Init File +@subsection Sample Init File + +Here is an example of an @var{inputrc} file. This illustrates key +binding, variable assignment, and conditional syntax. + +@example +@page +# This file controls the behaviour of line input editing for +# programs that use the GNU Readline library. Existing +# programs include FTP, Bash, and GDB. +# +# You can re-read the inputrc file with C-x C-r. +# Lines beginning with '#' are comments. +# +# First, include any systemwide bindings and variable +# assignments from /etc/Inputrc +$include /etc/Inputrc + +# +# Set various bindings for emacs mode. + +set editing-mode emacs + +$if mode=emacs + +Meta-Control-h: backward-kill-word Text after the function name is ignored + +# +# Arrow keys in keypad mode +# +#"\M-OD": backward-char +#"\M-OC": forward-char +#"\M-OA": previous-history +#"\M-OB": next-history +# +# Arrow keys in ANSI mode +# +"\M-[D": backward-char +"\M-[C": forward-char +"\M-[A": previous-history +"\M-[B": next-history +# +# Arrow keys in 8 bit keypad mode +# +#"\M-\C-OD": backward-char +#"\M-\C-OC": forward-char +#"\M-\C-OA": previous-history +#"\M-\C-OB": next-history +# +# Arrow keys in 8 bit ANSI mode +# +#"\M-\C-[D": backward-char +#"\M-\C-[C": forward-char +#"\M-\C-[A": previous-history +#"\M-\C-[B": next-history + +C-q: quoted-insert + +$endif + +# An old-style binding. This happens to be the default. +TAB: complete + +# Macros that are convenient for shell interaction +$if Bash +# edit the path +"\C-xp": "PATH=$@{PATH@}\e\C-e\C-a\ef\C-f" +# prepare to type a quoted word -- +# insert open and close double quotes +# and move to just after the open quote +"\C-x\"": "\"\"\C-b" +# insert a backslash (testing backslash escapes +# in sequences and macros) +"\C-x\\": "\\" +# Quote the current or previous word +"\C-xq": "\eb\"\ef\"" +# Add a binding to refresh the line, which is unbound +"\C-xr": redraw-current-line +# Edit variable on current line. +"\M-\C-v": "\C-a\C-k$\C-y\M-\C-e\C-a\C-y=" +$endif + +# use a visible bell if one is available +set bell-style visible + +# don't strip characters to 7 bits when reading +set input-meta on + +# allow iso-latin1 characters to be inserted rather +# than converted to prefix-meta sequences +set convert-meta off + +# display characters with the eighth bit set directly +# rather than as meta-prefixed characters +set output-meta on + +# if there are more than 150 possible completions for +# a word, ask the user if he wants to see all of them +set completion-query-items 150 + +# For FTP +$if Ftp +"\C-xg": "get \M-?" +"\C-xt": "put \M-?" +"\M-.": yank-last-arg +$endif +@end example + +@node Bindable Readline Commands +@section Bindable Readline Commands + +@menu +* Commands For Moving:: Moving about the line. +* Commands For History:: Getting at previous lines. +* Commands For Text:: Commands for changing text. +* Commands For Killing:: Commands for killing and yanking. +* Numeric Arguments:: Specifying numeric arguments, repeat counts. +* Commands For Completion:: Getting Readline to do the typing for you. +* Keyboard Macros:: Saving and re-executing typed characters +* Miscellaneous Commands:: Other miscellaneous commands. +@end menu + +This section describes Readline commands that may be bound to key +sequences. +@ifset BashFeatures +You can list your key bindings by executing +@w{@code{bind -P}} or, for a more terse format, suitable for an +@var{inputrc} file, @w{@code{bind -p}}. (@xref{Bash Builtins}.) +@end ifset +Command names without an accompanying key sequence are unbound by default. + +In the following descriptions, @dfn{point} refers to the current cursor +position, and @dfn{mark} refers to a cursor position saved by the +@code{set-mark} command. +The text between the point and mark is referred to as the @dfn{region}. + +@node Commands For Moving +@subsection Commands For Moving +@ftable @code +@item beginning-of-line (C-a) +Move to the start of the current line. + +@item end-of-line (C-e) +Move to the end of the line. + +@item forward-char (C-f) +Move forward a character. + +@item backward-char (C-b) +Move back a character. + +@item forward-word (M-f) +Move forward to the end of the next word. Words are composed of +letters and digits. + +@item backward-word (M-b) +Move back to the start of the current or previous word. Words are +composed of letters and digits. + +@item clear-screen (C-l) +Clear the screen and redraw the current line, +leaving the current line at the top of the screen. + +@item redraw-current-line () +Refresh the current line. By default, this is unbound. + +@end ftable + +@node Commands For History +@subsection Commands For Manipulating The History + +@ftable @code +@item accept-line (Newline or Return) +@ifset BashFeatures +Accept the line regardless of where the cursor is. +If this line is +non-empty, add it to the history list according to the setting of +the @env{HISTCONTROL} and @env{HISTIGNORE} variables. +If this line is a modified history line, then restore the history line +to its original state. +@end ifset +@ifclear BashFeatures +Accept the line regardless of where the cursor is. +If this line is +non-empty, it may be added to the history list for future recall with +@code{add_history()}. +If this line is a modified history line, the history line is restored +to its original state. +@end ifclear + +@item previous-history (C-p) +Move `back' through the history list, fetching the previous command. + +@item next-history (C-n) +Move `forward' through the history list, fetching the next command. + +@item beginning-of-history (M-<) +Move to the first line in the history. + +@item end-of-history (M->) +Move to the end of the input history, i.e., the line currently +being entered. + +@item reverse-search-history (C-r) +Search backward starting at the current line and moving `up' through +the history as necessary. This is an incremental search. + +@item forward-search-history (C-s) +Search forward starting at the current line and moving `down' through +the the history as necessary. This is an incremental search. + +@item non-incremental-reverse-search-history (M-p) +Search backward starting at the current line and moving `up' +through the history as necessary using a non-incremental search +for a string supplied by the user. + +@item non-incremental-forward-search-history (M-n) +Search forward starting at the current line and moving `down' +through the the history as necessary using a non-incremental search +for a string supplied by the user. + +@item history-search-forward () +Search forward through the history for the string of characters +between the start of the current line and the point. +This is a non-incremental search. +By default, this command is unbound. + +@item history-search-backward () +Search backward through the history for the string of characters +between the start of the current line and the point. This +is a non-incremental search. By default, this command is unbound. + +@item yank-nth-arg (M-C-y) +Insert the first argument to the previous command (usually +the second word on the previous line) at point. +With an argument @var{n}, +insert the @var{n}th word from the previous command (the words +in the previous command begin with word 0). A negative argument +inserts the @var{n}th word from the end of the previous command. +Once the argument @var{n} is computed, the argument is extracted +as if the @samp{!@var{n}} history expansion had been specified. + +@item yank-last-arg (M-. or M-_) +Insert last argument to the previous command (the last word of the +previous history entry). With an +argument, behave exactly like @code{yank-nth-arg}. +Successive calls to @code{yank-last-arg} move back through the history +list, inserting the last argument of each line in turn. +The history expansion facilities are used to extract the last argument, +as if the @samp{!$} history expansion had been specified. + +@end ftable + +@node Commands For Text +@subsection Commands For Changing Text + +@ftable @code +@item delete-char (C-d) +Delete the character at point. If point is at the +beginning of the line, there are no characters in the line, and +the last character typed was not bound to @code{delete-char}, then +return @sc{eof}. + +@item backward-delete-char (Rubout) +Delete the character behind the cursor. A numeric argument means +to kill the characters instead of deleting them. + +@item forward-backward-delete-char () +Delete the character under the cursor, unless the cursor is at the +end of the line, in which case the character behind the cursor is +deleted. By default, this is not bound to a key. + +@item quoted-insert (C-q or C-v) +Add the next character typed to the line verbatim. This is +how to insert key sequences like @kbd{C-q}, for example. + +@ifclear BashFeatures +@item tab-insert (M-@key{TAB}) +Insert a tab character. +@end ifclear + +@item self-insert (a, b, A, 1, !, @dots{}) +Insert yourself. + +@item transpose-chars (C-t) +Drag the character before the cursor forward over +the character at the cursor, moving the +cursor forward as well. If the insertion point +is at the end of the line, then this +transposes the last two characters of the line. +Negative arguments have no effect. + +@item transpose-words (M-t) +Drag the word before point past the word after point, +moving point past that word as well. +If the insertion point is at the end of the line, this transposes +the last two words on the line. + +@item upcase-word (M-u) +Uppercase the current (or following) word. With a negative argument, +uppercase the previous word, but do not move the cursor. + +@item downcase-word (M-l) +Lowercase the current (or following) word. With a negative argument, +lowercase the previous word, but do not move the cursor. + +@item capitalize-word (M-c) +Capitalize the current (or following) word. With a negative argument, +capitalize the previous word, but do not move the cursor. + +@item overwrite-mode () +Toggle overwrite mode. With an explicit positive numeric argument, +switches to overwrite mode. With an explicit non-positive numeric +argument, switches to insert mode. This command affects only +@code{emacs} mode; @code{vi} mode does overwrite differently. +Each call to @code{readline()} starts in insert mode. + +In overwrite mode, characters bound to @code{self-insert} replace +the text at point rather than pushing the text to the right. +Characters bound to @code{backward-delete-char} replace the character +before point with a space. + +By default, this command is unbound. + +@end ftable + +@node Commands For Killing +@subsection Killing And Yanking + +@ftable @code + +@item kill-line (C-k) +Kill the text from point to the end of the line. + +@item backward-kill-line (C-x Rubout) +Kill backward to the beginning of the line. + +@item unix-line-discard (C-u) +Kill backward from the cursor to the beginning of the current line. + +@item kill-whole-line () +Kill all characters on the current line, no matter where point is. +By default, this is unbound. + +@item kill-word (M-d) +Kill from point to the end of the current word, or if between +words, to the end of the next word. +Word boundaries are the same as @code{forward-word}. + +@item backward-kill-word (M-@key{DEL}) +Kill the word behind point. +Word boundaries are the same as @code{backward-word}. + +@item unix-word-rubout (C-w) +Kill the word behind point, using white space as a word boundary. +The killed text is saved on the kill-ring. + +@item unix-filename-rubout () +Kill the word behind point, using white space and the slash character +as the word boundaries. +The killed text is saved on the kill-ring. + +@item delete-horizontal-space () +Delete all spaces and tabs around point. By default, this is unbound. + +@item kill-region () +Kill the text in the current region. +By default, this command is unbound. + +@item copy-region-as-kill () +Copy the text in the region to the kill buffer, so it can be yanked +right away. By default, this command is unbound. + +@item copy-backward-word () +Copy the word before point to the kill buffer. +The word boundaries are the same as @code{backward-word}. +By default, this command is unbound. + +@item copy-forward-word () +Copy the word following point to the kill buffer. +The word boundaries are the same as @code{forward-word}. +By default, this command is unbound. + +@item yank (C-y) +Yank the top of the kill ring into the buffer at point. + +@item yank-pop (M-y) +Rotate the kill-ring, and yank the new top. You can only do this if +the prior command is @code{yank} or @code{yank-pop}. +@end ftable + +@node Numeric Arguments +@subsection Specifying Numeric Arguments +@ftable @code + +@item digit-argument (@kbd{M-0}, @kbd{M-1}, @dots{} @kbd{M--}) +Add this digit to the argument already accumulating, or start a new +argument. @kbd{M--} starts a negative argument. + +@item universal-argument () +This is another way to specify an argument. +If this command is followed by one or more digits, optionally with a +leading minus sign, those digits define the argument. +If the command is followed by digits, executing @code{universal-argument} +again ends the numeric argument, but is otherwise ignored. +As a special case, if this command is immediately followed by a +character that is neither a digit or minus sign, the argument count +for the next command is multiplied by four. +The argument count is initially one, so executing this function the +first time makes the argument count four, a second time makes the +argument count sixteen, and so on. +By default, this is not bound to a key. +@end ftable + +@node Commands For Completion +@subsection Letting Readline Type For You + +@ftable @code +@item complete (@key{TAB}) +Attempt to perform completion on the text before point. +The actual completion performed is application-specific. +@ifset BashFeatures +Bash attempts completion treating the text as a variable (if the +text begins with @samp{$}), username (if the text begins with +@samp{~}), hostname (if the text begins with @samp{@@}), or +command (including aliases and functions) in turn. If none +of these produces a match, filename completion is attempted. +@end ifset +@ifclear BashFeatures +The default is filename completion. +@end ifclear + +@item possible-completions (M-?) +List the possible completions of the text before point. + +@item insert-completions (M-*) +Insert all completions of the text before point that would have +been generated by @code{possible-completions}. + +@item menu-complete () +Similar to @code{complete}, but replaces the word to be completed +with a single match from the list of possible completions. +Repeated execution of @code{menu-complete} steps through the list +of possible completions, inserting each match in turn. +At the end of the list of completions, the bell is rung +(subject to the setting of @code{bell-style}) +and the original text is restored. +An argument of @var{n} moves @var{n} positions forward in the list +of matches; a negative argument may be used to move backward +through the list. +This command is intended to be bound to @key{TAB}, but is unbound +by default. + +@item delete-char-or-list () +Deletes the character under the cursor if not at the beginning or +end of the line (like @code{delete-char}). +If at the end of the line, behaves identically to +@code{possible-completions}. +This command is unbound by default. + +@ifset BashFeatures +@item complete-filename (M-/) +Attempt filename completion on the text before point. + +@item possible-filename-completions (C-x /) +List the possible completions of the text before point, +treating it as a filename. + +@item complete-username (M-~) +Attempt completion on the text before point, treating +it as a username. + +@item possible-username-completions (C-x ~) +List the possible completions of the text before point, +treating it as a username. + +@item complete-variable (M-$) +Attempt completion on the text before point, treating +it as a shell variable. + +@item possible-variable-completions (C-x $) +List the possible completions of the text before point, +treating it as a shell variable. + +@item complete-hostname (M-@@) +Attempt completion on the text before point, treating +it as a hostname. + +@item possible-hostname-completions (C-x @@) +List the possible completions of the text before point, +treating it as a hostname. + +@item complete-command (M-!) +Attempt completion on the text before point, treating +it as a command name. Command completion attempts to +match the text against aliases, reserved words, shell +functions, shell builtins, and finally executable filenames, +in that order. + +@item possible-command-completions (C-x !) +List the possible completions of the text before point, +treating it as a command name. + +@item dynamic-complete-history (M-@key{TAB}) +Attempt completion on the text before point, comparing +the text against lines from the history list for possible +completion matches. + +@item complete-into-braces (M-@{) +Perform filename completion and insert the list of possible completions +enclosed within braces so the list is available to the shell +(@pxref{Brace Expansion}). + +@end ifset +@end ftable + +@node Keyboard Macros +@subsection Keyboard Macros +@ftable @code + +@item start-kbd-macro (C-x () +Begin saving the characters typed into the current keyboard macro. + +@item end-kbd-macro (C-x )) +Stop saving the characters typed into the current keyboard macro +and save the definition. + +@item call-last-kbd-macro (C-x e) +Re-execute the last keyboard macro defined, by making the characters +in the macro appear as if typed at the keyboard. + +@end ftable + +@node Miscellaneous Commands +@subsection Some Miscellaneous Commands +@ftable @code + +@item re-read-init-file (C-x C-r) +Read in the contents of the @var{inputrc} file, and incorporate +any bindings or variable assignments found there. + +@item abort (C-g) +Abort the current editing command and +ring the terminal's bell (subject to the setting of +@code{bell-style}). + +@item do-uppercase-version (M-a, M-b, M-@var{x}, @dots{}) +If the metafied character @var{x} is lowercase, run the command +that is bound to the corresponding uppercase character. + +@item prefix-meta (@key{ESC}) +Metafy the next character typed. This is for keyboards +without a meta key. Typing @samp{@key{ESC} f} is equivalent to typing +@kbd{M-f}. + +@item undo (C-_ or C-x C-u) +Incremental undo, separately remembered for each line. + +@item revert-line (M-r) +Undo all changes made to this line. This is like executing the @code{undo} +command enough times to get back to the beginning. + +@ifset BashFeatures +@item tilde-expand (M-&) +@end ifset +@ifclear BashFeatures +@item tilde-expand (M-~) +@end ifclear +Perform tilde expansion on the current word. + +@item set-mark (C-@@) +Set the mark to the point. If a +numeric argument is supplied, the mark is set to that position. + +@item exchange-point-and-mark (C-x C-x) +Swap the point with the mark. The current cursor position is set to +the saved position, and the old cursor position is saved as the mark. + +@item character-search (C-]) +A character is read and point is moved to the next occurrence of that +character. A negative count searches for previous occurrences. + +@item character-search-backward (M-C-]) +A character is read and point is moved to the previous occurrence +of that character. A negative count searches for subsequent +occurrences. + +@item insert-comment (M-#) +Without a numeric argument, the value of the @code{comment-begin} +variable is inserted at the beginning of the current line. +If a numeric argument is supplied, this command acts as a toggle: if +the characters at the beginning of the line do not match the value +of @code{comment-begin}, the value is inserted, otherwise +the characters in @code{comment-begin} are deleted from the beginning of +the line. +In either case, the line is accepted as if a newline had been typed. +@ifset BashFeatures +The default value of @code{comment-begin} causes this command +to make the current line a shell comment. +If a numeric argument causes the comment character to be removed, the line +will be executed by the shell. +@end ifset + +@item dump-functions () +Print all of the functions and their key bindings to the +Readline output stream. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an @var{inputrc} file. This command is unbound by default. + +@item dump-variables () +Print all of the settable variables and their values to the +Readline output stream. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an @var{inputrc} file. This command is unbound by default. + +@item dump-macros () +Print all of the Readline key sequences bound to macros and the +strings they output. If a numeric argument is supplied, +the output is formatted in such a way that it can be made part +of an @var{inputrc} file. This command is unbound by default. + +@ifset BashFeatures +@item glob-complete-word (M-g) +The word before point is treated as a pattern for pathname expansion, +with an asterisk implicitly appended. This pattern is used to +generate a list of matching file names for possible completions. + +@item glob-expand-word (C-x *) +The word before point is treated as a pattern for pathname expansion, +and the list of matching file names is inserted, replacing the word. +If a numeric argument is supplied, a @samp{*} is appended before +pathname expansion. + +@item glob-list-expansions (C-x g) +The list of expansions that would have been generated by +@code{glob-expand-word} is displayed, and the line is redrawn. +If a numeric argument is supplied, a @samp{*} is appended before +pathname expansion. + +@item display-shell-version (C-x C-v) +Display version information about the current instance of Bash. + +@item shell-expand-line (M-C-e) +Expand the line as the shell does. +This performs alias and history expansion as well as all of the shell +word expansions (@pxref{Shell Expansions}). + +@item history-expand-line (M-^) +Perform history expansion on the current line. + +@item magic-space () +Perform history expansion on the current line and insert a space +(@pxref{History Interaction}). + +@item alias-expand-line () +Perform alias expansion on the current line (@pxref{Aliases}). + +@item history-and-alias-expand-line () +Perform history and alias expansion on the current line. + +@item insert-last-argument (M-. or M-_) +A synonym for @code{yank-last-arg}. + +@item operate-and-get-next (C-o) +Accept the current line for execution and fetch the next line +relative to the current line from the history for editing. Any +argument is ignored. + +@item edit-and-execute-command (C-xC-e) +Invoke an editor on the current command line, and execute the result as shell +commands. +Bash attempts to invoke +@code{$VISUAL}, @code{$EDITOR}, and @code{emacs} +as the editor, in that order. + +@end ifset + +@ifclear BashFeatures +@item emacs-editing-mode (C-e) +When in @code{vi} command mode, this causes a switch to @code{emacs} +editing mode. + +@item vi-editing-mode (M-C-j) +When in @code{emacs} editing mode, this causes a switch to @code{vi} +editing mode. + +@end ifclear + +@end ftable + +@node Readline vi Mode +@section Readline vi Mode + +While the Readline library does not have a full set of @code{vi} +editing functions, it does contain enough to allow simple editing +of the line. The Readline @code{vi} mode behaves as specified in +the @sc{posix} 1003.2 standard. + +@ifset BashFeatures +In order to switch interactively between @code{emacs} and @code{vi} +editing modes, use the @samp{set -o emacs} and @samp{set -o vi} +commands (@pxref{The Set Builtin}). +@end ifset +@ifclear BashFeatures +In order to switch interactively between @code{emacs} and @code{vi} +editing modes, use the command @kbd{M-C-j} (bound to emacs-editing-mode +when in @code{vi} mode and to vi-editing-mode in @code{emacs} mode). +@end ifclear +The Readline default is @code{emacs} mode. + +When you enter a line in @code{vi} mode, you are already placed in +`insertion' mode, as if you had typed an @samp{i}. Pressing @key{ESC} +switches you into `command' mode, where you can edit the text of the +line with the standard @code{vi} movement keys, move to previous +history lines with @samp{k} and subsequent lines with @samp{j}, and +so forth. + +@ifset BashFeatures +@node Programmable Completion +@section Programmable Completion +@cindex programmable completion + +When word completion is attempted for an argument to a command for +which a completion specification (a @var{compspec}) has been defined +using the @code{complete} builtin (@pxref{Programmable Completion Builtins}), +the programmable completion facilities are invoked. + +First, the command name is identified. +If a compspec has been defined for that command, the +compspec is used to generate the list of possible completions for the word. +If the command word is a full pathname, a compspec for the full +pathname is searched for first. +If no compspec is found for the full pathname, an attempt is made to +find a compspec for the portion following the final slash. + +Once a compspec has been found, it is used to generate the list of +matching words. +If a compspec is not found, the default Bash completion +described above (@pxref{Commands For Completion}) is performed. + +First, the actions specified by the compspec are used. +Only matches which are prefixed by the word being completed are +returned. +When the @option{-f} or @option{-d} option is used for filename or +directory name completion, the shell variable @env{FIGNORE} is +used to filter the matches. +@xref{Bash Variables}, for a description of @env{FIGNORE}. + +Any completions specified by a filename expansion pattern to the +@option{-G} option are generated next. +The words generated by the pattern need not match the word being completed. +The @env{GLOBIGNORE} shell variable is not used to filter the matches, +but the @env{FIGNORE} shell variable is used. + +Next, the string specified as the argument to the @option{-W} option +is considered. +The string is first split using the characters in the @env{IFS} +special variable as delimiters. +Shell quoting is honored. +Each word is then expanded using +brace expansion, tilde expansion, parameter and variable expansion, +command substitution, and arithmetic expansion, +as described above (@pxref{Shell Expansions}). +The results are split using the rules described above +(@pxref{Word Splitting}). +The results of the expansion are prefix-matched against the word being +completed, and the matching words become the possible completions. + +After these matches have been generated, any shell function or command +specified with the @option{-F} and @option{-C} options is invoked. +When the command or function is invoked, the @env{COMP_LINE} and +@env{COMP_POINT} variables are assigned values as described above +(@pxref{Bash Variables}). +If a shell function is being invoked, the @env{COMP_WORDS} and +@env{COMP_CWORD} variables are also set. +When the function or command is invoked, the first argument is the +name of the command whose arguments are being completed, the +second argument is the word being completed, and the third argument +is the word preceding the word being completed on the current command line. +No filtering of the generated completions against the word being completed +is performed; the function or command has complete freedom in generating +the matches. + +Any function specified with @option{-F} is invoked first. +The function may use any of the shell facilities, including the +@code{compgen} builtin described below +(@pxref{Programmable Completion Builtins}), to generate the matches. +It must put the possible completions in the @env{COMPREPLY} array +variable. + +Next, any command specified with the @option{-C} option is invoked +in an environment equivalent to command substitution. +It should print a list of completions, one per line, to +the standard output. +Backslash may be used to escape a newline, if necessary. + +After all of the possible completions are generated, any filter +specified with the @option{-X} option is applied to the list. +The filter is a pattern as used for pathname expansion; a @samp{&} +in the pattern is replaced with the text of the word being completed. +A literal @samp{&} may be escaped with a backslash; the backslash +is removed before attempting a match. +Any completion that matches the pattern will be removed from the list. +A leading @samp{!} negates the pattern; in this case any completion +not matching the pattern will be removed. + +Finally, any prefix and suffix specified with the @option{-P} and @option{-S} +options are added to each member of the completion list, and the result is +returned to the Readline completion code as the list of possible +completions. + +If the previously-applied actions do not generate any matches, and the +@option{-o dirnames} option was supplied to @code{complete} when the +compspec was defined, directory name completion is attempted. + +If the @option{-o plusdirs} option was supplied to @code{complete} when +the compspec was defined, directory name completion is attempted and any +matches are added to the results of the other actions. + +By default, if a compspec is found, whatever it generates is returned to +the completion code as the full set of possible completions. +The default Bash completions are not attempted, and the Readline default +of filename completion is disabled. +If the @option{-o bashdefault} option was supplied to @code{complete} when +the compspec was defined, the default Bash completions are attempted +if the compspec generates no matches. +If the @option{-o default} option was supplied to @code{complete} when the +compspec was defined, Readline's default completion will be performed +if the compspec (and, if attempted, the default Bash completions) +generate no matches. + +When a compspec indicates that directory name completion is desired, +the programmable completion functions force Readline to append a slash +to completed names which are symbolic links to directories, subject to +the value of the @var{mark-directories} Readline variable, regardless +of the setting of the @var{mark-symlinked-directories} Readline variable. + +@node Programmable Completion Builtins +@section Programmable Completion Builtins +@cindex completion builtins + +Two builtin commands are available to manipulate the programmable completion +facilities. + +@table @code +@item compgen +@btindex compgen +@example +@code{compgen [@var{option}] [@var{word}]} +@end example + +Generate possible completion matches for @var{word} according to +the @var{option}s, which may be any option accepted by the +@code{complete} +builtin with the exception of @option{-p} and @option{-r}, and write +the matches to the standard output. +When using the @option{-F} or @option{-C} options, the various shell variables +set by the programmable completion facilities, while available, will not +have useful values. + +The matches will be generated in the same way as if the programmable +completion code had generated them directly from a completion specification +with the same flags. +If @var{word} is specified, only those completions matching @var{word} +will be displayed. + +The return value is true unless an invalid option is supplied, or no +matches were generated. + +@item complete +@btindex complete +@example +@code{complete [-abcdefgjksuv] [-o @var{comp-option}] [-A @var{action}] [-G @var{globpat}] [-W @var{wordlist}] +[-P @var{prefix}] [-S @var{suffix}] [-X @var{filterpat}] [-F @var{function}] +[-C @var{command}] @var{name} [@var{name} @dots{}]} +@code{complete -pr [@var{name} @dots{}]} +@end example + +Specify how arguments to each @var{name} should be completed. +If the @option{-p} option is supplied, or if no options are supplied, existing +completion specifications are printed in a way that allows them to be +reused as input. +The @option{-r} option removes a completion specification for +each @var{name}, or, if no @var{name}s are supplied, all +completion specifications. + +The process of applying these completion specifications when word completion +is attempted is described above (@pxref{Programmable Completion}). + +Other options, if specified, have the following meanings. +The arguments to the @option{-G}, @option{-W}, and @option{-X} options +(and, if necessary, the @option{-P} and @option{-S} options) +should be quoted to protect them from expansion before the +@code{complete} builtin is invoked. + + +@table @code +@item -o @var{comp-option} +The @var{comp-option} controls several aspects of the compspec's behavior +beyond the simple generation of completions. +@var{comp-option} may be one of: + +@table @code + +@item bashdefault +Perform the rest of the default Bash completions if the compspec +generates no matches. + +@item default +Use Readline's default filename completion if the compspec generates +no matches. + +@item dirnames +Perform directory name completion if the compspec generates no matches. + +@item filenames +Tell Readline that the compspec generates filenames, so it can perform any +filename-specific processing (like adding a slash to directory names or +suppressing trailing spaces). This option is intended to be used with +shell functions specified with @option{-F}. + +@item nospace +Tell Readline not to append a space (the default) to words completed at +the end of the line. + +@item plusdirs +After any matches defined by the compspec are generated, +directory name completion is attempted and any +matches are added to the results of the other actions. + +@end table + +@item -A @var{action} +The @var{action} may be one of the following to generate a list of possible +completions: + +@table @code +@item alias +Alias names. May also be specified as @option{-a}. + +@item arrayvar +Array variable names. + +@item binding +Readline key binding names (@pxref{Bindable Readline Commands}). + +@item builtin +Names of shell builtin commands. May also be specified as @option{-b}. + +@item command +Command names. May also be specified as @option{-c}. + +@item directory +Directory names. May also be specified as @option{-d}. + +@item disabled +Names of disabled shell builtins. + +@item enabled +Names of enabled shell builtins. + +@item export +Names of exported shell variables. May also be specified as @option{-e}. + +@item file +File names. May also be specified as @option{-f}. + +@item function +Names of shell functions. + +@item group +Group names. May also be specified as @option{-g}. + +@item helptopic +Help topics as accepted by the @code{help} builtin (@pxref{Bash Builtins}). + +@item hostname +Hostnames, as taken from the file specified by the +@env{HOSTFILE} shell variable (@pxref{Bash Variables}). + +@item job +Job names, if job control is active. May also be specified as @option{-j}. + +@item keyword +Shell reserved words. May also be specified as @option{-k}. + +@item running +Names of running jobs, if job control is active. + +@item service +Service names. May also be specified as @option{-s}. + +@item setopt +Valid arguments for the @option{-o} option to the @code{set} builtin +(@pxref{The Set Builtin}). + +@item shopt +Shell option names as accepted by the @code{shopt} builtin +(@pxref{Bash Builtins}). + +@item signal +Signal names. + +@item stopped +Names of stopped jobs, if job control is active. + +@item user +User names. May also be specified as @option{-u}. + +@item variable +Names of all shell variables. May also be specified as @option{-v}. +@end table + +@item -G @var{globpat} +The filename expansion pattern @var{globpat} is expanded to generate +the possible completions. + +@item -W @var{wordlist} +The @var{wordlist} is split using the characters in the +@env{IFS} special variable as delimiters, and each resultant word +is expanded. +The possible completions are the members of the resultant list which +match the word being completed. + +@item -C @var{command} +@var{command} is executed in a subshell environment, and its output is +used as the possible completions. + +@item -F @var{function} +The shell function @var{function} is executed in the current shell +environment. +When it finishes, the possible completions are retrieved from the value +of the @env{COMPREPLY} array variable. + +@item -X @var{filterpat} +@var{filterpat} is a pattern as used for filename expansion. +It is applied to the list of possible completions generated by the +preceding options and arguments, and each completion matching +@var{filterpat} is removed from the list. +A leading @samp{!} in @var{filterpat} negates the pattern; in this +case, any completion not matching @var{filterpat} is removed. + +@item -P @var{prefix} +@var{prefix} is added at the beginning of each possible completion +after all other options have been applied. + +@item -S @var{suffix} +@var{suffix} is appended to each possible completion +after all other options have been applied. +@end table + +The return value is true unless an invalid option is supplied, an option +other than @option{-p} or @option{-r} is supplied without a @var{name} +argument, an attempt is made to remove a completion specification for +a @var{name} for which no specification exists, or +an error occurs adding a completion specification. + +@end table +@end ifset diff --git a/external/gpl3/gdb/dist/readline/doc/rluserman.texi b/external/gpl3/gdb/dist/readline/doc/rluserman.texi new file mode 100644 index 000000000000..db80b312611c --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/rluserman.texi @@ -0,0 +1,88 @@ +\input texinfo @c -*-texinfo-*- +@comment %**start of header (This is for running Texinfo on a region.) +@setfilename rluserman.info +@settitle GNU Readline Library +@comment %**end of header (This is for running Texinfo on a region.) + +@setchapternewpage odd + +@include version.texi + +@copying +This manual describes the end user interface of the GNU Readline Library +(version @value{VERSION}, @value{UPDATED}), a library which aids in the +consistency of user interface across discrete programs which provide +a command line interface. + +Copyright @copyright{} 1988-2005 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. + +@quotation +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.1 or +any later version published by the Free Software Foundation; with no +Invariant Sections, with the Front-Cover texts being ``A GNU Manual,'' +and with the Back-Cover Texts as in (a) below. A copy of the license is +included in the section entitled ``GNU Free Documentation License.'' + +(a) The FSF's Back-Cover Text is: ``You have freedom to copy and modify +this GNU Manual, like GNU software. Copies published by the Free +Software Foundation raise funds for GNU development.'' +@end quotation +@end copying + +@dircategory Libraries +@direntry +* RLuserman: (rluserman). The GNU readline library User's Manual. +@end direntry + +@titlepage +@title GNU Readline Library User Interface +@subtitle Edition @value{EDITION}, for @code{Readline Library} Version @value{VERSION}. +@subtitle @value{UPDATED-MONTH} +@author Chet Ramey, Case Western Reserve University +@author Brian Fox, Free Software Foundation + +@page +@vskip 0pt plus 1filll +@insertcopying + +@sp 1 +Published by the Free Software Foundation @* +59 Temple Place, Suite 330, @* +Boston, MA 02111-1307 @* +USA @* + +@end titlepage + +@contents + +@ifnottex +@node Top +@top GNU Readline Library + +This document describes the end user interface of the GNU Readline Library, +a utility which aids in the consistency of user interface across discrete +programs which provide a command line interface. + +@menu +* Command Line Editing:: GNU Readline User's Manual. +* Copying This Manual:: Copying This Manual. +@end menu +@end ifnottex + +@include rluser.texi + +@node Copying This Manual +@appendix Copying This Manual + +@menu +* GNU Free Documentation License:: License for copying this manual. +@end menu + +@include fdl.texi + +@bye diff --git a/external/gpl3/gdb/dist/readline/doc/texi2dvi b/external/gpl3/gdb/dist/readline/doc/texi2dvi new file mode 100755 index 000000000000..c6f11cafeff5 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/texi2dvi @@ -0,0 +1,660 @@ +#! /bin/sh +# texi2dvi --- produce DVI (or PDF) files from Texinfo (or LaTeX) sources. +# $Id: texi2dvi,v 1.1.1.1 2011/09/24 19:56:53 christos Exp $ +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, +# 2002, 2003 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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So what. + case "$1" in + -@ ) escape=@;; + # Silently and without documentation accept -b and --b[atch] as synonyms. + -b | --b*) batch=eval;; + -q | -s | --q* | --s*) quiet=t; batch=eval;; + -c | --c*) clean=t;; + -D | --d*) debug=t;; + -e | -E | --e*) expand=t;; + -h | --h*) echo "$usage"; exit 0;; + -I | --I*) + shift + miincludes="$miincludes -I $1" + txincludes="$txincludes$1$path_sep" + ;; + -l | --l*) shift; set_language=$1;; + -o | --o*) + shift + clean=t + case "$1" in + /* | ?:/*) oname=$1;; + *) oname="$orig_pwd/$1";; + esac;; + -p | --p*) oformat=pdf;; + -t | --t*) shift; textra="$textra\\ +$1";; + -v | --vers*) echo "$version"; exit 0;; + -V | --verb*) verbose=echo;; + --) # What remains are not options. + shift + while test x"$1" != x"$arg_sep"; do + set dummy ${1+"$@"} "$1"; shift + shift + done + break;; + -*) + echo "$0: Unknown or ambiguous option \`$1'." >&2 + echo "$0: Try \`--help' for more information." >&2 + exit 1;; + *) set dummy ${1+"$@"} "$1"; shift;; + esac + shift +done +# Pop the token +shift + +# Interpret remaining command line args as filenames. +case $# in + 0) + echo "$0: Missing file arguments." >&2 + echo "$0: Try \`--help' for more information." >&2 + exit 2 + ;; + 1) ;; + *) + if test -n "$oname"; then + echo "$0: Can't use option \`--output' with more than one argument." >&2 + exit 2 + fi + ;; +esac + +# Prepare the temporary directory. Remove it at exit, unless debugging. +if test -z "$debug"; then + trap "cd / && rm -rf $tmpdir" 0 1 2 15 +fi + +# Create the temporary directory with strict rights +(umask 077 && mkdir $tmpdir) || exit 1 + +# Prepare the tools we might need. This may be extra work in some +# cases, but improves the readibility of the script. +utildir=$tmpdir/utils +mkdir $utildir || exit 1 + +# A sed script that preprocesses Texinfo sources in order to keep the +# iftex sections only. We want to remove non TeX sections, and +# comment (with `@c texi2dvi') TeX sections so that makeinfo does not +# try to parse them. Nevertheless, while commenting TeX sections, +# don't comment @macro/@end macro so that makeinfo does propagate +# them. Unfortunately makeinfo --iftex --no-ifhtml --no-ifinfo +# doesn't work well enough (yet) to use that, so work around with sed. +comment_iftex_sed=$utildir/comment.sed +cat <$comment_iftex_sed +/^@tex/,/^@end tex/{ + s/^/@c texi2dvi/ +} +/^@iftex/,/^@end iftex/{ + s/^/@c texi2dvi/ + /^@c texi2dvi@macro/,/^@c texi2dvi@end macro/{ + s/^@c texi2dvi// + } +} +/^@html/,/^@end html/{ + s/^/@c (texi2dvi)/ +} +/^@ifhtml/,/^@end ifhtml/{ + s/^/@c (texi2dvi)/ +} +/^@ifnottex/,/^@end ifnottex/{ + s/^/@c (texi2dvi)/ +} +/^@ifinfo/,/^@end ifinfo/{ + /^@node/p + /^@menu/,/^@end menu/p + t + s/^/@c (texi2dvi)/ +} +s/^@ifnotinfo/@c texi2dvi@ifnotinfo/ +s/^@end ifnotinfo/@c texi2dvi@end ifnotinfo/ +EOF +# Uncommenting is simple: Remove any leading `@c texi2dvi'. +uncomment_iftex_sed=$utildir/uncomment.sed +cat <$uncomment_iftex_sed +s/^@c texi2dvi// +EOF + +# A shell script that computes the list of xref files. +# Takes the filename (without extension) of which we look for xref +# files as argument. The index files must be reported last. +get_xref_files=$utildir/get_xref.sh +cat <<\EOF >$get_xref_files +#! /bin/sh + +# Get list of xref files (indexes, tables and lists). +# Find all files having root filename with a two-letter extension, +# saves the ones that are really Texinfo-related files. .?o? catches +# many files: .toc, .log, LaTeX tables and lists, FiXme's .lox, maybe more. +for this_file in "$1".?o? "$1".aux "$1".?? "$1".idx; do + # If file is empty, skip it. + test -s "$this_file" || continue + # If the file is not suitable to be an index or xref file, don't + # process it. The file can't be if its first character is not a + # backslash or single quote. + first_character=`sed -n '1s/^\(.\).*$/\1/p;q' $this_file` + if test "x$first_character" = "x\\" \ + || test "x$first_character" = "x'"; then + xref_files="$xref_files ./$this_file" + fi +done +echo "$xref_files" +EOF +chmod 500 $get_xref_files + +# File descriptor usage: +# 0 standard input +# 1 standard output (--verbose messages) +# 2 standard error +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 5 tools output (turned off by --quiet) + +# Tools' output. If quiet, discard, else redirect to the message flow. +if test "$quiet" = t; then + exec 5>/dev/null +else + exec 5>&1 +fi + +# Enable tracing +test "$debug" = t && set -x + +# +# TeXify files. + +for command_line_filename in ${1+"$@"}; do + $verbose "Processing $command_line_filename ..." + + # If the COMMAND_LINE_FILENAME is not absolute (e.g., --debug.tex), + # prepend `./' in order to avoid that the tools take it as an option. + echo "$command_line_filename" | $EGREP '^(/|[A-z]:/)' >/dev/null \ + || command_line_filename="./$command_line_filename" + + # See if the file exists. If it doesn't we're in trouble since, even + # though the user may be able to reenter a valid filename at the tex + # prompt (assuming they're attending the terminal), this script won't + # be able to find the right xref files and so forth. + if test ! -r "$command_line_filename"; then + echo "$0: Could not read $command_line_filename, skipping." >&2 + continue + fi + + # Get the name of the current directory. We want the full path + # because in clean mode we are in tmp, in which case a relative + # path has no meaning. + filename_dir=`echo $command_line_filename | sed 's!/[^/]*$!!;s!^$!.!'` + filename_dir=`cd "$filename_dir" >/dev/null && pwd` + + # Strip directory part but leave extension. + filename_ext=`basename "$command_line_filename"` + # Strip extension. + filename_noext=`echo "$filename_ext" | sed 's/\.[^.]*$//'` + ext=`echo "$filename_ext" | sed 's/^.*\.//'` + + # _src. Use same basename since we want to generate aux files with + # the same basename as the manual. If --expand, then output the + # macro-expanded file to here, else copy the original file. + tmpdir_src=$tmpdir/src + filename_src=$tmpdir_src/$filename_noext.$ext + + # _xtr. The file with the user's extra commands. + tmpdir_xtr=$tmpdir/xtr + filename_xtr=$tmpdir_xtr/$filename_noext.$ext + + # _bak. Copies of the previous xref files (another round is run if + # they differ from the new one). + tmpdir_bak=$tmpdir/bak + + # Make all those directories and give up if we can't succeed. + mkdir $tmpdir_src $tmpdir_xtr $tmpdir_bak || exit 1 + + # Source file might include additional sources. + # We want `.:$orig_pwd' before anything else. (We'll add `.:' later + # after all other directories have been turned into absolute paths.) + # `.' goes first to ensure that any old .aux, .cps, + # etc. files in ${directory} don't get used in preference to fresher + # files in `.'. Include orig_pwd in case we are in clean mode, where + # we've cd'd to a temp directory. + common="$orig_pwd$path_sep$filename_dir$path_sep$txincludes" + TEXINPUTS="$common$TEXINPUTS_orig" + INDEXSTYLE="$common$INDEXSTYLE_orig" + + # Convert relative paths to absolute paths, so we can run in another + # directory (e.g., in --clean mode, or during the macro-support + # detection.) + # + # Empty path components are meaningful to tex. We rewrite them + # as `EMPTY' so they don't get lost when we split on $path_sep. + TEXINPUTS=`echo $TEXINPUTS |sed 's/^:/EMPTY:/;s/:$/:EMPTY/;s/::/:EMPTY:/g'` + INDEXSTYLE=`echo $INDEXSTYLE |sed 's/^:/EMPTY:/;s/:$/:EMPTY/;s/::/:EMPTY:/g'` + save_IFS=$IFS + IFS=$path_sep + set x $TEXINPUTS; shift + TEXINPUTS=. + for dir + do + case $dir in + EMPTY) + TEXINPUTS=$TEXINPUTS$path_sep + ;; + [\\/]* | ?:[\\/]*) # Absolute paths don't need to be expansed. + TEXINPUTS=$TEXINPUTS$path_sep$dir + ;; + *) + abs=`cd "$dir" && pwd` && TEXINPUTS=$TEXINPUTS$path_sep$abs + ;; + esac + done + set x $INDEXSTYLE; shift + INDEXSTYLE=. + for dir + do + case $dir in + EMPTY) + INDEXSTYLE=$INDEXSTYLE$path_sep + ;; + [\\/]* | ?:[\\/]*) # Absolute paths don't need to be expansed. + INDEXSTYLE=$INDEXSTYLE$path_sep$dir + ;; + *) + abs=`cd "$dir" && pwd` && INDEXSTYLE=$INDEXSTYLE$path_sep$abs + ;; + esac + done + IFS=$save_IFS + + # If the user explicitly specified the language, use that. + # Otherwise, if the first line is \input texinfo, assume it's texinfo. + # Otherwise, guess from the file extension. + if test -n "$set_language"; then + language=$set_language + elif sed 1q "$command_line_filename" | grep 'input texinfo' >/dev/null; then + language=texinfo + else + language= + fi + + # Get the type of the file (latex or texinfo) from the given language + # we just guessed, or from the file extension if not set yet. + case ${language:-$filename_ext} in + [lL]a[tT]e[xX] | *.ltx | *.tex) + # Assume a LaTeX file. LaTeX needs bibtex and uses latex for + # compilation. No makeinfo. + bibtex=${BIBTEX:-bibtex} + makeinfo= # no point in running makeinfo on latex source. + texindex=${MAKEINDEX:-makeindex} + if test $oformat = dvi; then + tex=${LATEX:-latex} + else + tex=${PDFLATEX:-pdflatex} + fi + ;; + + *) + # Assume a Texinfo file. Texinfo files need makeinfo, texindex and tex. + bibtex= + texindex=${TEXINDEX:-texindex} + if test $oformat = dvi; then + tex=${TEX:-tex} + else + tex=${PDFTEX:-pdftex} + fi + # Unless required by the user, makeinfo expansion is wanted only + # if texinfo.tex is too old. + if test "$expand" = t; then + makeinfo=${MAKEINFO:-makeinfo} + else + # Check if texinfo.tex performs macro expansion by looking for + # its version. The version is a date of the form YEAR-MO-DA. + # We don't need to use [0-9] to match the digits since anyway + # the comparison with $txiprereq, a number, will fail with non + # digits. + txiversion_tex=txiversion.tex + echo '\input texinfo.tex @bye' >$tmpdir/$txiversion_tex + # Run in the tmpdir to avoid leaving files. + eval `cd $tmpdir >/dev/null && + $tex $txiversion_tex 2>/dev/null | + sed -n 's/^.*\[\(.*\)version \(....\)-\(..\)-\(..\).*$/txiformat=\1 txiversion="\2\3\4"/p'` + $verbose "texinfo.tex preloaded as \`$txiformat', version is \`$txiversion' ..." + if test "$txiprereq" -le "$txiversion" >/dev/null 2>&1; then + makeinfo= + else + makeinfo=${MAKEINFO:-makeinfo} + fi + # As long as we had to run TeX, offer the user this convenience + if test "$txiformat" = Texinfo; then + escape=@ + fi + fi + ;; + esac + + # Expand macro commands in the original source file using Makeinfo. + # Always use `end' footnote style, since the `separate' style + # generates different output (arguably this is a bug in -E). + # Discard main info output, the user asked to run TeX, not makeinfo. + if test -n "$makeinfo"; then + $verbose "Macro-expanding $command_line_filename to $filename_src ..." + sed -f $comment_iftex_sed "$command_line_filename" \ + | $makeinfo --footnote-style=end -I "$filename_dir" $miincludes \ + -o /dev/null --macro-expand=- \ + | sed -f $uncomment_iftex_sed >"$filename_src" + filename_input=$filename_src + fi + + # If makeinfo failed (or was not even run), use the original file as input. + if test $? -ne 0 \ + || test ! -r "$filename_src"; then + $verbose "Reverting to $command_line_filename ..." + filename_input=$filename_dir/$filename_ext + fi + + # Used most commonly for @finalout, @smallbook, etc. + if test -n "$textra"; then + $verbose "Inserting extra commands: $textra" + sed '/^@setfilename/a\ +'"$textra" "$filename_input" >$filename_xtr + filename_input=$filename_xtr + fi + + # If clean mode was specified, then move to the temporary directory. + if test "$clean" = t; then + $verbose "cd $tmpdir_src" + cd "$tmpdir_src" || exit 1 + fi + + while :; do # will break out of loop below + orig_xref_files=`$get_xref_files "$filename_noext"` + + # Save copies of originals for later comparison. + if test -n "$orig_xref_files"; then + $verbose "Backing up xref files: `echo $orig_xref_files | sed 's|\./||g'`" + cp $orig_xref_files $tmpdir_bak + fi + + # Run bibtex on current file. + # - If its input (AUX) exists. + # - If AUX contains both `\bibdata' and `\bibstyle'. + # - If some citations are missing (LOG contains `Citation'). + # or the LOG complains of a missing .bbl + # + # We run bibtex first, because I can see reasons for the indexes + # to change after bibtex is run, but I see no reason for the + # converse. + # + # Don't try to be too smart. Running bibtex only if the bbl file + # exists and is older than the LaTeX file is wrong, since the + # document might include files that have changed. Because there + # can be several AUX (if there are \include's), but a single LOG, + # looking for missing citations in LOG is easier, though we take + # the risk to match false messages. + if test -n "$bibtex" \ + && test -r "$filename_noext.aux" \ + && test -r "$filename_noext.log" \ + && (grep '^\\bibdata[{]' "$filename_noext.aux" \ + && grep '^\\bibstyle[{]' "$filename_noext.aux" \ + && (grep 'Warning:.*Citation.*undefined' "$filename_noext.log" \ + || grep 'No file .*\.bbl\.' "$filename_noext.log")) \ + >/dev/null 2>&1; \ + then + $verbose "Running $bibtex $filename_noext ..." + if $bibtex "$filename_noext" >&5; then :; else + echo "$0: $bibtex exited with bad status, quitting." >&2 + exit 1 + fi + fi + + # What we'll run texindex on -- exclude non-index files. + # Since we know index files are last, it is correct to remove everything + # before .aux and .?o?. But don't really do o + # -- don't match whitespace as . + # Otherwise, if orig_xref_files contains something like + # foo.xo foo.whatever + # the space after the o will get matched. + index_files=`echo "$orig_xref_files" \ + | sed "s!.*\.aux!!g; + s!./$filename_noext\.[^ ]o[^ ]!!g; + s/^[ ]*//;s/[ ]*$//"` + # Run texindex (or makeindex) on current index files. If they + # already exist, and after running TeX a first time the index + # files don't change, then there's no reason to run TeX again. + # But we won't know that if the index files are out of date or + # nonexistent. + if test -n "$texindex" && test -n "$index_files"; then + $verbose "Running $texindex $index_files ..." + if $texindex $index_files 2>&5 1>&2; then :; else + echo "$0: $texindex exited with bad status, quitting." >&2 + exit 1 + fi + fi + + # Finally, run TeX. + # Prevent $ESCAPE from being interpreted by the shell if it happens + # to be `/'. + $batch tex_args="\\${escape}nonstopmode\ \\${escape}input" + cmd="$tex $tex_args $filename_input" + $verbose "Running $cmd ..." + if $cmd >&5; then :; else + echo "$0: $tex exited with bad status, quitting." >&2 + echo "$0: see $filename_noext.log for errors." >&2 + test "$clean" = t \ + && cp "$filename_noext.log" "$orig_pwd" + exit 1 + fi + + + # Decide if looping again is needed. + finished=t + + # LaTeX (and the package changebar) report in the LOG file if it + # should be rerun. This is needed for files included from + # subdirs, since texi2dvi does not try to compare xref files in + # subdirs. Performing xref files test is still good since LaTeX + # does not report changes in xref files. + if grep "Rerun to get" "$filename_noext.log" >/dev/null 2>&1; then + finished= + fi + + # Check if xref files changed. + new_xref_files=`$get_xref_files "$filename_noext"` + $verbose "Original xref files = `echo $orig_xref_files | sed 's|\./||g'`" + $verbose "New xref files = `echo $new_xref_files | sed 's|\./||g'`" + + # If old and new lists don't at least have the same file list, + # then one file or another has definitely changed. + test "x$orig_xref_files" != "x$new_xref_files" && finished= + + # File list is the same. We must compare each file until we find + # a difference. + if test -n "$finished"; then + for this_file in $new_xref_files; do + $verbose "Comparing xref file `echo $this_file | sed 's|\./||g'` ..." + # cmp -s returns nonzero exit status if files differ. + if cmp -s "$this_file" "$tmpdir_bak/$this_file"; then :; else + # We only need to keep comparing until we find one that + # differs, because we'll have to run texindex & tex again no + # matter how many more there might be. + finished= + $verbose "xref file `echo $this_file | sed 's|\./||g'` differed ..." + test "$debug" = t && diff -c "$tmpdir_bak/$this_file" "$this_file" + break + fi + done + fi + + # If finished, exit the loop, else rerun the loop. + test -n "$finished" && break + done + + # If we were in clean mode, compilation was in a tmp directory. + # Copy the DVI (or PDF) file into the directory where the compilation + # has been done. (The temp dir is about to get removed anyway.) + # We also return to the original directory so that + # - the next file is processed in correct conditions + # - the temporary file can be removed + if test -n "$clean"; then + if test -n "$oname"; then + dest=$oname + else + dest=$orig_pwd + fi + $verbose "Copying $oformat file from `pwd` to $dest" + cp -p "./$filename_noext.$oformat" "$dest" + cd / # in case $orig_pwd is on a different drive (for DOS) + cd $orig_pwd || exit 1 + fi + + # Remove temporary files. + if test "x$debug" = "x"; then + $verbose "Removing $tmpdir_src $tmpdir_xtr $tmpdir_bak ..." + cd / + rm -rf $tmpdir_src $tmpdir_xtr $tmpdir_bak + fi +done + +$verbose "$0 done." +exit 0 # exit successfully, not however we ended the loop. diff --git a/external/gpl3/gdb/dist/readline/doc/texi2html b/external/gpl3/gdb/dist/readline/doc/texi2html new file mode 100755 index 000000000000..9aa246858658 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/texi2html @@ -0,0 +1,5429 @@ +#! /usr/bin/perl +'di '; +'ig 00 '; +#+############################################################################## +# +# texi2html: Program to transform Texinfo documents to HTML +# +# Copyright (C) 1999, 2000 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +#-############################################################################## + +# This requires perl version 5 or higher +require 5.0; + +#++############################################################################## +# +# NOTE FOR DEBUGGING THIS SCRIPT: +# You can run 'perl texi2html.pl' directly, provided you have +# the environment variable T2H_HOME set to the directory containing +# the texi2html.init file +# +#--############################################################################## + +# CVS version: +# $Id: texi2html,v 1.1.1.1 2011/09/24 19:56:56 christos Exp $ + +# Homepage: +$T2H_HOMEPAGE = < (original author) + Karl Berry + Olaf Bachmann + and many others. +Maintained by: Olaf Bachmann +Send bugs and suggestions to +EOT + +# Version: set in configure.in +$THISVERSION = '1.64'; +$THISPROG = "texi2html $THISVERSION"; # program name and version + +# The man page for this program is included at the end of this file and can be +# viewed using the command 'nroff -man texi2html'. + +# Identity: + +$T2H_TODAY = &pretty_date; # like "20 September 1993" +# the eval prevents this from breaking on system which do not have +# a proper getpwuid implemented +eval { ($T2H_USER = (getpwuid ($<))[6]) =~ s/,.*//;}; # Who am i + +#+++############################################################################ +# # +# Initialization # +# Pasted content of File $(srcdir)/texi2html.init: Default initializations # +# # +#---############################################################################ + +# leave this within comments, and keep the require statement +# This way, you can directly run texi2html.pl, if $ENV{T2H_HOME}/texi2html.init +# exists. + +# +# -*-perl-*- +###################################################################### +# File: texi2html.init +# +# Sets default values for command-line arguments and for various customizable +# procedures +# +# A copy of this file is pasted into the beginning of texi2html by +# 'make texi2html' +# +# Copy this file and make changes to it, if you like. +# Afterwards, either, load it with command-line option -init_file +# +# $Id: texi2html,v 1.1.1.1 2011/09/24 19:56:56 christos Exp $ + +###################################################################### +# stuff which can also be set by command-line options +# +# +# Note: values set here, overwrite values set by the command-line +# options before -init_file and might still be overwritten by +# command-line arguments following the -init_file option +# + +# T2H_OPTIONS is a hash whose keys are the (long) names of valid +# command-line options and whose values are a hash with the following keys: +# type ==> one of !|=i|:i|=s|:s (see GetOpt::Long for more info) +# linkage ==> ref to scalar, array, or subroutine (see GetOpt::Long for more info) +# verbose ==> short description of option (displayed by -h) +# noHelp ==> if 1 -> for "not so important options": only print description on -h 1 +# 2 -> for obsolete options: only print description on -h 2 + +$T2H_DEBUG = 0; +$T2H_OPTIONS -> {debug} = +{ + type => '=i', + linkage => \$main::T2H_DEBUG, + verbose => 'output HTML with debuging information', +}; + +$T2H_DOCTYPE = ''; +$T2H_OPTIONS -> {doctype} = +{ + type => '=s', + linkage => \$main::T2H_DOCTYPE, + verbose => 'document type which is output in header of HTML files', + noHelp => 1 +}; + +$T2H_CHECK = 0; +$T2H_OPTIONS -> {check} = +{ + type => '!', + linkage => \$main::T2H_CHECK, + verbose => 'if set, only check files and output all things that may be Texinfo commands', + noHelp => 1 +}; + +# -expand +# if set to "tex" (or, "info") expand @iftex and @tex (or, @ifinfo) sections +# else, neither expand @iftex, @tex, nor @ifinfo sections +$T2H_EXPAND = "info"; +$T2H_OPTIONS -> {expand} = +{ + type => '=s', + linkage => \$T2H_EXPAND, + verbose => 'Expand info|tex|none section of texinfo source', +}; + +# - glossary +#if set, uses section named `Footnotes' for glossary +$T2H_USE_GLOSSARY = 0; +T2H_OPTIONS -> {glossary} = +{ + type => '!', + linkage => \$T2H_USE_GLOSSARY, + verbose => "if set, uses section named `Footnotes' for glossary", + noHelp => 1, +}; + + +# -invisible +# $T2H_INVISIBLE_MARK is the text used to create invisible destination +# anchors for index links (you can for instance use the invisible.xbm +# file shipped with this program). This is a workaround for a known +# bug of many WWW browsers, including netscape. +# For me, it works fine without it -- on the contrary: if there, it +# inserts space between headers and start of text (obachman 3/99) +$T2H_INVISIBLE_MARK = ''; +# $T2H_INVISIBLE_MARK = ' '; +$T2H_OPTIONS -> {invisible} = +{ + type => '=s', + linkage => \$T2H_INVISIBLE_MARK, + verbose => 'use text in invisble anchot', + noHelp => 1, +}; + +# -iso +# if set, ISO8879 characters are used for special symbols (like copyright, etc) +$T2H_USE_ISO = 0; +$T2H_OPTIONS -> {iso} = +{ + type => 'iso', + linkage => \$T2H_USE_ISO, + verbose => 'if set, ISO8879 characters are used for special symbols (like copyright, etc)', + noHelp => 1, +}; + +# -I +# list directories where @include files are searched for (besides the +# directory of the doc file) additional '-I' args add to this list +@T2H_INCLUDE_DIRS = ("."); +$T2H_OPTIONS -> {I} = +{ + type => '=s', + linkage => \@T2H_INCLUDE_DIRS, + verbose => 'append $s to the @include search path', +}; + +# -top_file +# uses file of this name for top-level file +# extension is manipulated appropriately, if necessary. +# If empty, .html is used +# Typically, you would set this to "index.html". +$T2H_TOP_FILE = ''; +$T2H_OPTIONS -> {top_file} = +{ + type => '=s', + linkage => \$T2H_TOP_FILE, + verbose => 'use $s as top file, instead of .html', +}; + + +# -toc_file +# uses file of this name for table of contents file +# extension is manipulated appropriately, if necessary. +# If empty, _toc.html is used +$T2H_TOC_FILE = ''; +$T2H_OPTIONS -> {toc_file} = +{ + type => '=s', + linkage => \$T2H_TOC_FILE, + verbose => 'use $s as ToC file, instead of _toc.html', +}; + +# -frames +# if set, output two additional files which use HTML 4.0 "frames". +$T2H_FRAMES = 0; +$T2H_OPTIONS -> {frames} = +{ + type => '!', + linkage => \$T2H_FRAMES, + verbose => 'output files which use HTML 4.0 frames (experimental)', + noHelp => 1, +}; + + +# -menu | -nomenu +# if set, show the Texinfo menus +$T2H_SHOW_MENU = 1; +$T2H_OPTIONS -> {menu} = +{ + type => '!', + linkage => \$T2H_SHOW_MENU, + verbose => 'ouput Texinfo menus', +}; + +# -number | -nonumber +# if set, number sections and show section names and numbers in references +# and menus +$T2H_NUMBER_SECTIONS = 1; +$T2H_OPTIONS -> {number} = +{ + type => '!', + linkage => \$T2H_NUMBER_SECTIONS, + verbose => 'use numbered sections' +}; + +# if set, and T2H_NUMBER_SECTIONS is set, then use node names in menu +# entries, instead of section names +$T2H_NODE_NAME_IN_MENU = 0; + +# if set and menu entry equals menu descr, then do not print menu descr. +# Likewise, if node name equals entry name, do not print entry name. +$T2H_AVOID_MENU_REDUNDANCY = 1; + +# -split section|chapter|none +# if set to 'section' (resp. 'chapter') create one html file per (sub)section +# (resp. chapter) and separate pages for Top, ToC, Overview, Index, +# Glossary, About. +# otherwise, create monolithic html file which contains whole document +#$T2H_SPLIT = 'section'; +$T2H_SPLIT = ''; +$T2H_OPTIONS -> {split} = +{ + type => '=s', + linkage => \$T2H_SPLIT, + verbose => 'split document on section|chapter else no splitting', +}; + +# -section_navigation|-no-section_navigation +# if set, then navigation panels are printed at the beginning of each section +# and, possibly at the end (depending on whether or not there were more than +# $T2H_WORDS_IN_PAGE words on page +# This is most useful if you do not want to have section navigation +# on -split chapter +$T2H_SECTION_NAVIGATION = 1; +$T2H_OPTIONS -> {sec_nav} = +{ + type => '!', + linkage => \$T2H_SECTION_NAVIGATION, + verbose => 'output navigation panels for each section', +}; + +# -subdir +# if set put result files in this directory +# if not set result files are put into current directory +#$T2H_SUBDIR = 'html'; +$T2H_SUBDIR = ''; +$T2H_OPTIONS -> {subdir} = +{ + type => '=s', + linkage => \$T2H_SUBDIR, + verbose => 'put HTML files in directory $s, instead of $cwd', +}; + +# -short_extn +# If this is set all HTML file will have extension ".htm" instead of +# ".html". This is helpful when shipping the document to PC systems. +$T2H_SHORTEXTN = 0; +$T2H_OPTIONS -> {short_ext} = +{ + type => '!', + linkage => \$T2H_SHORTEXTN, + verbose => 'use "htm" extension for output HTML files', +}; + + +# -prefix +# Set the output file prefix, prepended to all .html, .gif and .pl files. +# By default, this is the basename of the document +$T2H_PREFIX = ''; +$T2H_OPTIONS -> {prefix} = +{ + type => '=s', + linkage => \$T2H_PREFIX, + verbose => 'use as prefix for output files, instead of ', +}; + +# -o filename +# If set, generate monolithic document output html into $filename +$T2H_OUT = ''; +$T2H_OPTIONS -> {out_file} = +{ + type => '=s', + linkage => sub {$main::T2H_OUT = @_[1]; $T2H_SPLIT = '';}, + verbose => 'if set, all HTML output goes into file $s', +}; + +# -short_ref +#if set cross-references are given without section numbers +$T2H_SHORT_REF = ''; +$T2H_OPTIONS -> {short_ref} = +{ + type => '!', + linkage => \$T2H_SHORT_REF, + verbose => 'if set, references are without section numbers', +}; + +# -idx_sum +# if value is set, then for each @prinindex $what +# $docu_name_$what.idx is created which contains lines of the form +# $key\t$ref sorted alphabetically (case matters) +$T2H_IDX_SUMMARY = 0; +$T2H_OPTIONS -> {idx_sum} = +{ + type => '!', + linkage => \$T2H_IDX_SUMMARY, + verbose => 'if set, also output index summary', + noHelp => 1, +}; + +# -verbose +# if set, chatter about what we are doing +$T2H_VERBOSE = ''; +$T2H_OPTIONS -> {Verbose} = +{ + type => '!', + linkage => \$T2H_VERBOSE, + verbose => 'print progress info to stdout', +}; + +# -lang +# For page titles use $T2H_WORDS->{$T2H_LANG}->{...} as title. +# To add a new language, supply list of titles (see $T2H_WORDS below). +# and use ISO 639 language codes (see e.g. perl module Locale-Codes-1.02 +# for definitions) +# Default's to 'en' if not set or no @documentlanguage is specified +$T2H_LANG = ''; +$T2H_OPTIONS -> {lang} = +{ + type => '=s', + linkage => sub {SetDocumentLanguage($_[1])}, + verbose => 'use $s as document language (ISO 639 encoding)', +}; + +# -l2h +# if set, uses latex2html for generation of math content +$T2H_L2H = ''; +$T2H_OPTIONS -> {l2h} = +{ + type => '!', + linkage => \$T2H_L2H, + verbose => 'if set, uses latex2html for @math and @tex', +}; + +###################### +# The following options are only relevant if $T2H_L2H is set +# +# -l2h_l2h +# name/location of latex2html progam +$T2H_L2H_L2H = "latex2html"; +$T2H_OPTIONS -> {l2h_l2h} = +{ + type => '=s', + linkage => \$T2H_L2H_L2H, + verbose => 'program to use for latex2html translation', + noHelp => 1, +}; + +# -l2h_skip +# if set, skips actual call to latex2html tries to reuse previously generated +# content, instead +$T2H_L2H_SKIP = ''; +$T2H_OPTIONS -> {l2h_skip} = +{ + type => '!', + linkage => \$T2H_L2H_SKIP, + verbose => 'if set, tries to reuse previously latex2html output', + noHelp => 1, +}; + +# -l2h_tmp +# if set, l2h uses this directory for temporarary files. The path +# leading to this directory may not contain a dot (i.e., a "."), +# otherwise, l2h will fail +$T2H_L2H_TMP = ''; +$T2H_OPTIONS -> {l2h_tmp} = +{ + type => '=s', + linkage => \$T2H_L2H_TMP, + verbose => 'if set, uses $s as temporary latex2html directory', + noHelp => 1, +}; + +# if set, cleans intermediate files (they all have the prefix $doc_l2h_) +# of l2h +$T2H_L2H_CLEAN = 1; +$T2H_OPTIONS -> {l2h_clean} = +{ + type => '!', + linkage => \$T2H_L2H_CLEAN, + verbose => 'if set, do not keep intermediate latex2html files for later reuse', + noHelp => 1, +}; + +$T2H_OPTIONS -> {D} = +{ + type => '=s', + linkage => sub {$main::value{@_[1]} = 1;}, + verbose => 'equivalent to Texinfo "@set $s 1"', + noHelp => 1, +}; + +$T2H_OPTIONS -> {init_file} = +{ + type => '=s', + linkage => \&LoadInitFile, + verbose => 'load init file $s' +}; + + +############################################################################## +# +# The following can only be set in the init file +# +############################################################################## + +# if set, center @image by default +# otherwise, do not center by default +$T2H_CENTER_IMAGE = 1; + +# used as identation for block enclosing command @example, etc +# If not empty, must be enclosed in +$T2H_EXAMPLE_INDENT_CELL = ' '; +# same as above, only for @small +$T2H_SMALL_EXAMPLE_INDENT_CELL = ' '; +# font size for @small +$T2H_SMALL_FONT_SIZE = '-1'; + +# if non-empty, and no @..heading appeared in Top node, then +# use this as header for top node/section, otherwise use value of +# @settitle or @shorttitle (in that order) +$T2H_TOP_HEADING = ''; + +# if set, use this chapter for 'Index' button, else +# use first chapter whose name matches 'index' (case insensitive) +$T2H_INDEX_CHAPTER = ''; + +# if set and $T2H_SPLIT is set, then split index pages at the next letter +# after they have more than that many entries +$T2H_SPLIT_INDEX = 100; + +# if set (e.g., to index.html) replace hrefs to this file +# (i.e., to index.html) by ./ +$T2H_HREF_DIR_INSTEAD_FILE = ''; + +######################################################################## +# Language dependencies: +# To add a new language extend T2H_WORDS hash and create $T2H_<...>_WORDS hash +# To redefine one word, simply do: +# $T2H_WORDS->{}->{} = 'whatever' in your personal init file. +# +$T2H_WORDS_EN = +{ + # titles of pages + 'ToC_Title' => 'Table of Contents', + 'Overview_Title' => 'Short Table of Contents', + 'Index_Title' => 'Index', + 'About_Title' => 'About this document', + 'Footnotes_Title' => 'Footnotes', + 'See' => 'See', + 'see' => 'see', + 'section' => 'section', +# If necessary, we could extend this as follows: +# # text for buttons +# 'Top_Button' => 'Top', +# 'ToC_Button' => 'Contents', +# 'Overview_Button' => 'Overview', +# 'Index_button' => 'Index', +# 'Back_Button' => 'Back', +# 'FastBack_Button' => 'FastBack', +# 'Prev_Button' => 'Prev', +# 'Up_Button' => 'Up', +# 'Next_Button' => 'Next', +# 'Forward_Button' =>'Forward', +# 'FastWorward_Button' => 'FastForward', +# 'First_Button' => 'First', +# 'Last_Button' => 'Last', +# 'About_Button' => 'About' +}; + +$T2H_WORD_DE = +{ + 'ToC_Title' => 'Inhaltsverzeichniss', + 'Overview_Title' => 'Kurzes Inhaltsverzeichniss', + 'Index_Title' => 'Index', + 'About_Title' => 'Über dieses Dokument', + 'Footnotes_Title' => 'Fußnoten', + 'See' => 'Siehe', + 'see' => 'siehe', + 'section' => 'Abschnitt', +}; + +$T2H_WORD_NL = +{ + 'ToC_Title' => 'Inhoudsopgave', + 'Overview_Title' => 'Korte inhoudsopgave', + 'Index_Title' => 'Index', #Not sure ;-) + 'About_Title' => 'No translation available!', #No translation available! + 'Footnotes_Title' => 'No translation available!', #No translation available! + 'See' => 'Zie', + 'see' => 'zie', + 'section' => 'sectie', +}; + +$T2H_WORD_ES = +{ + 'ToC_Title' => 'índice General', + 'Overview_Title' => 'Resumen del Contenido', + 'Index_Title' => 'Index', #Not sure ;-) + 'About_Title' => 'No translation available!', #No translation available! + 'Footnotes_Title' => 'Fußnoten', + 'See' => 'Véase', + 'see' => 'véase', + 'section' => 'sección', +}; + +$T2H_WORD_NO = +{ + 'ToC_Title' => 'Innholdsfortegnelse', + 'Overview_Title' => 'Kort innholdsfortegnelse', + 'Index_Title' => 'Indeks', #Not sure ;-) + 'About_Title' => 'No translation available!', #No translation available! + 'Footnotes_Title' => 'No translation available!', + 'See' => 'Se', + 'see' => 'se', + 'section' => 'avsnitt', +}; + +$T2H_WORD_PT = +{ + 'ToC_Title' => 'Sumário', + 'Overview_Title' => 'Breve Sumário', + 'Index_Title' => 'Índice', #Not sure ;-) + 'About_Title' => 'No translation available!', #No translation available! + 'Footnotes_Title' => 'No translation available!', + 'See' => 'Veja', + 'see' => 'veja', + 'section' => 'Seção', +}; + +$T2H_WORDS = +{ + 'en' => $T2H_WORDS_EN, + 'de' => $T2H_WORDS_DE, + 'nl' => $T2H_WORDS_NL, + 'es' => $T2H_WORDS_ES, + 'no' => $T2H_WORDS_NO, + 'pt' => $T2H_WORDS_PT +}; + +@MONTH_NAMES_EN = +( + 'January', 'February', 'March', 'April', 'May', + 'June', 'July', 'August', 'September', 'October', + 'November', 'December' +); + +@MONTH_NAMES_DE = +( + 'Januar', 'Februar', 'März', 'April', 'Mai', + 'Juni', 'Juli', 'August', 'September', 'Oktober', + 'November', 'Dezember' +); + +@MONTH_NAMES_NL = +( + 'Januari', 'Februari', 'Maart', 'April', 'Mei', + 'Juni', 'Juli', 'Augustus', 'September', 'Oktober', + 'November', 'December' +); + +@MONTH_NAMES_ES = +( + 'enero', 'febrero', 'marzo', 'abril', 'mayo', + 'junio', 'julio', 'agosto', 'septiembre', 'octubre', + 'noviembre', 'diciembre' +); + +@MONTH_NAMES_NO = +( + + 'januar', 'februar', 'mars', 'april', 'mai', + 'juni', 'juli', 'august', 'september', 'oktober', + 'november', 'desember' +); + +@MONTH_NAMES_PT = +( + 'Janeiro', 'Fevereiro', 'Março', 'Abril', 'Maio', + 'Junho', 'Julho', 'Agosto', 'Setembro', 'Outubro', + 'Novembro', 'Dezembro' +); + + +$MONTH_NAMES = +{ + 'en' => \@MONTH_NAMES_EN, + 'de' => \@MONTH_NAMES_DE, + 'es' => \@MONTH_NAMES_ES, + 'nl' => \@MONTH_NAMES_NL, + 'no' => \@MONTH_NAMES_NO, + 'pt' => \@MONTH_NAMES_PT +}; +######################################################################## +# Control of Page layout: +# You can make changes of the Page layout at two levels: +# 1.) For small changes, it is often enough to change the value of +# some global string/hash/array variables +# 2.) For larger changes, reimplement one of the T2H_DEFAULT_* routines, +# give them another name, and assign them to the respective +# $T2H_ variable. + +# As a general interface, the hashes T2H_HREF, T2H_NAME, T2H_NODE hold +# href, html-name, node-name of +# This -- current section (resp. html page) +# Top -- top page ($T2H_TOP_FILE) +# Contents -- Table of contents +# Overview -- Short table of contents +# Index -- Index page +# About -- page which explain "navigation buttons" +# First -- first node +# Last -- last node +# +# Whether or not the following hash values are set, depends on the context +# (all values are w.r.t. 'This' section) +# Next -- next node of texinfo +# Prev -- previous node of texinfo +# Up -- up node of texinfo +# Forward -- next node in reading order +# Back -- previous node in reading order +# FastForward -- if leave node, up and next, else next node +# FastBackward-- if leave node, up and prev, else prev node +# +# Furthermore, the following global variabels are set: +# $T2H_THISDOC{title} -- title as set by @setttile +# $T2H_THISDOC{fulltitle} -- full title as set by @title... +# $T2H_THISDOC{subtitle} -- subtitle as set by @subtitle +# $T2H_THISDOC{author} -- author as set by @author +# +# and pointer to arrays of lines which need to be printed by t2h_print_lines +# $T2H_OVERVIEW -- lines of short table of contents +# $T2H_TOC -- lines of table of contents +# $T2H_TOP -- lines of Top texinfo node +# $T2H_THIS_SECTION -- lines of 'This' section + +# +# There are the following subs which control the layout: +# +$T2H_print_section = \&T2H_DEFAULT_print_section; +$T2H_print_Top_header = \&T2H_DEFAULT_print_Top_header; +$T2H_print_Top_footer = \&T2H_DEFAULT_print_Top_footer; +$T2H_print_Top = \&T2H_DEFAULT_print_Top; +$T2H_print_Toc = \&T2H_DEFAULT_print_Toc; +$T2H_print_Overview = \&T2H_DEFAULT_print_Overview; +$T2H_print_Footnotes = \&T2H_DEFAULT_print_Footnotes; +$T2H_print_About = \&T2H_DEFAULT_print_About; +$T2H_print_misc_header = \&T2H_DEFAULT_print_misc_header; +$T2H_print_misc_footer = \&T2H_DEFAULT_print_misc_footer; +$T2H_print_misc = \&T2H_DEFAULT_print_misc; +$T2H_print_chapter_header = \&T2H_DEFAULT_print_chapter_header; +$T2H_print_chapter_footer = \&T2H_DEFAULT_print_chapter_footer; +$T2H_print_page_head = \&T2H_DEFAULT_print_page_head; +$T2H_print_page_foot = \&T2H_DEFAULT_print_page_foot; +$T2H_print_head_navigation = \&T2H_DEFAULT_print_head_navigation; +$T2H_print_foot_navigation = \&T2H_DEFAULT_print_foot_navigation; +$T2H_button_icon_img = \&T2H_DEFAULT_button_icon_img; +$T2H_print_navigation = \&T2H_DEFAULT_print_navigation; +$T2H_about_body = \&T2H_DEFAULT_about_body; +$T2H_print_frame = \&T2H_DEFAULT_print_frame; +$T2H_print_toc_frame = \&T2H_DEFAULT_print_toc_frame; + +######################################################################## +# Layout for html for every sections +# +sub T2H_DEFAULT_print_section +{ + my $fh = shift; + local $T2H_BUTTONS = \@T2H_SECTION_BUTTONS; + &$T2H_print_head_navigation($fh) if $T2H_SECTION_NAVIGATION; + my $nw = t2h_print_lines($fh); + if ($T2H_SPLIT eq 'section' && $T2H_SECTION_NAVIGATION) + { + &$T2H_print_foot_navigation($fh, $nw); + } + else + { + print $fh '
    ' . "\n"; + } +} + +################################################################### +# Layout of top-page I recommend that you use @ifnothtml, @ifhtml, +# @html within the Top texinfo node to specify content of top-level +# page. +# +# If you enclose everything in @ifnothtml, then title, subtitle, +# author and overview is printed +# T2H_HREF of Next, Prev, Up, Forward, Back are not defined +# if $T2H_SPLIT then Top page is in its own html file +sub T2H_DEFAULT_print_Top_header +{ + &$T2H_print_page_head(@_) if $T2H_SPLIT; + t2h_print_label(@_); # this needs to be called, otherwise no label set + &$T2H_print_head_navigation(@_); +} +sub T2H_DEFAULT_print_Top_footer +{ + &$T2H_print_foot_navigation(@_); + &$T2H_print_page_foot(@_) if $T2H_SPLIT; +} +sub T2H_DEFAULT_print_Top +{ + my $fh = shift; + + # for redefining navigation buttons use: + # local $T2H_BUTTONS = [...]; + # as it is, 'Top', 'Contents', 'Index', 'About' are printed + local $T2H_BUTTONS = \@T2H_MISC_BUTTONS; + &$T2H_print_Top_header($fh); + if ($T2H_THIS_SECTION) + { + # if top-level node has content, then print it with extra header + print $fh "

    $T2H_NAME{Top}

    " + unless ($T2H_HAS_TOP_HEADING); + t2h_print_lines($fh, $T2H_THIS_SECTION) + } + else + { + # top-level node is fully enclosed in @ifnothtml + # print fulltitle, subtitle, author, Overview + print $fh + "
    \n

    " . + join("

    \n

    ", split(/\n/, $T2H_THISDOC{fulltitle})) . + "

    \n"; + print $fh "

    $T2H_THISDOC{subtitle}

    \n" if $T2H_THISDOC{subtitle}; + print $fh "$T2H_THISDOC{author}\n" if $T2H_THISDOC{author}; + print $fh < +
    +

    +

    Overview:

    +
    +EOT + t2h_print_lines($fh, $T2H_OVERVIEW); + print $fh "
    \n"; + } + &$T2H_print_Top_footer($fh); +} + +################################################################### +# Layout of Toc, Overview, and Footnotes pages +# By default, we use "normal" layout +# T2H_HREF of Next, Prev, Up, Forward, Back, etc are not defined +# use: local $T2H_BUTTONS = [...] to redefine navigation buttons +sub T2H_DEFAULT_print_Toc +{ + return &$T2H_print_misc(@_); +} +sub T2H_DEFAULT_print_Overview +{ + return &$T2H_print_misc(@_); +} +sub T2H_DEFAULT_print_Footnotes +{ + return &$T2H_print_misc(@_); +} +sub T2H_DEFAULT_print_About +{ + return &$T2H_print_misc(@_); +} + +sub T2H_DEFAULT_print_misc_header +{ + &$T2H_print_page_head(@_) if $T2H_SPLIT; + # this needs to be called, otherwise, no labels are set + t2h_print_label(@_); + &$T2H_print_head_navigation(@_); +} +sub T2H_DEFAULT_print_misc_footer +{ + &$T2H_print_foot_navigation(@_); + &$T2H_print_page_foot(@_) if $T2H_SPLIT; +} +sub T2H_DEFAULT_print_misc +{ + my $fh = shift; + local $T2H_BUTTONS = \@T2H_MISC_BUTTONS; + &$T2H_print_misc_header($fh); + print $fh "

    $T2H_NAME{This}

    \n"; + t2h_print_lines($fh); + &$T2H_print_misc_footer($fh); +} + +################################################################### +# chapter_header and chapter_footer are only called if +# T2H_SPLIT eq 'chapter' +# chapter_header: after print_page_header, before print_section +# chapter_footer: after print_section of last section, before print_page_footer +# +# If you want to get rid of navigation stuff after each section, +# redefine print_section such that it does not call print_navigation, +# and put print_navigation into print_chapter_header +@T2H_CHAPTER_BUTTONS = + ( + 'FastBack', 'FastForward', ' ', + ' ', ' ', ' ', ' ', + 'Top', 'Contents', 'Index', 'About', + ); + +sub T2H_DEFAULT_print_chapter_header +{ + # nothing to do there, by default + if (! $T2H_SECTION_NAVIGATION) + { + my $fh = shift; + local $T2H_BUTTONS = \@T2H_CHAPTER_BUTTONS; + &$T2H_print_navigation($fh); + print $fh "\n
    \n"; + } +} + +sub T2H_DEFAULT_print_chapter_footer +{ + local $T2H_BUTTONS = \@T2H_CHAPTER_BUTTONS; + &$T2H_print_navigation(@_); +} +################################################################### +$T2H_TODAY = &pretty_date; # like "20 September 1993" + +sub pretty_date { + local($sec, $min, $hour, $mday, $mon, $year, $wday, $yday, $isdst); + + ($sec, $min, $hour, $mday, $mon, $year, $wday, $yday, $isdst) = localtime(time); + $year += ($year < 70) ? 2000 : 1900; + # obachman: Let's do it as the Americans do + return($MONTH_NAMES->{$T2H_LANG}[$mon] . ", " . $mday . " " . $year); +} + + +################################################################### +# Layout of standard header and footer +# + +# Set the default body text, inserted between +###$T2H_BODYTEXT = 'LANG="EN" BGCOLOR="#FFFFFF" TEXT="#000000" LINK="#0000FF" VLINK="#800080" ALINK="#FF0000"'; +$T2H_BODYTEXT = 'LANG="' . $T2H_LANG . '" BGCOLOR="#FFFFFF" TEXT="#000000" LINK="#0000FF" VLINK="#800080" ALINK="#FF0000"'; +# text inserted after +$T2H_AFTER_BODY_OPEN = ''; +#text inserted before +$T2H_PRE_BODY_CLOSE = ''; +# this is used in footer +$T2H_ADDRESS = "by $T2H_USER " if $T2H_USER; +$T2H_ADDRESS .= "on $T2H_TODAY"; +# this is added inside after and some META NAME stuff +# can be used for <style> <script>, <meta> tags +$T2H_EXTRA_HEAD = ''; + +sub T2H_DEFAULT_print_page_head +{ + my $fh = shift; + my $longtitle = "$T2H_THISDOC{title}: $T2H_NAME{This}"; + print $fh <<EOT; +<HTML> +$T2H_DOCTYPE +<!-- Created on $T2H_TODAY by $THISPROG --> +<!-- +$T2H_AUTHORS +--> +<HEAD> +<TITLE>$longtitle + + + + + + +$T2H_EXTRA_HEAD + + + +$T2H_AFTER_BODY_OPEN +EOT +} + +sub T2H_DEFAULT_print_page_foot +{ + my $fh = shift; + print $fh < + +This document was generated +$T2H_ADDRESS +using     texi2html +$T2H_PRE_BODY_CLOSE + + +EOT +} + +################################################################### +# Layout of navigation panel + +# if this is set, then a vertical navigation panel is used +$T2H_VERTICAL_HEAD_NAVIGATION = 0; +sub T2H_DEFAULT_print_head_navigation +{ + my $fh = shift; + if ($T2H_VERTICAL_HEAD_NAVIGATION) + { + print $fh < + + +EOT + } + &$T2H_print_navigation($fh, $T2H_VERTICAL_HEAD_NAVIGATION); + if ($T2H_VERTICAL_HEAD_NAVIGATION) + { + print $fh < + +EOT + } + elsif ($T2H_SPLIT eq 'section') + { + print $fh "
    \n"; + } +} + +# Specifies the minimum page length required before a navigation panel +# is placed at the bottom of a page (the default is that of latex2html) +# T2H_THIS_WORDS_IN_PAGE holds number of words of current page +$T2H_WORDS_IN_PAGE = 300; +sub T2H_DEFAULT_print_foot_navigation +{ + my $fh = shift; + my $nwords = shift; + if ($T2H_VERTICAL_HEAD_NAVIGATION) + { + print $fh < + + +EOT + } + print $fh "
    \n"; + &$T2H_print_navigation($fh) if ($nwords >= $T2H_WORDS_IN_PAGE) +} + +###################################################################### +# navigation panel +# +# specify in this array which "buttons" should appear in which order +# in the navigation panel for sections; use ' ' for empty buttons (space) +@T2H_SECTION_BUTTONS = + ( + 'Back', 'Forward', ' ', 'FastBack', 'Up', 'FastForward', + ' ', ' ', ' ', ' ', + 'Top', 'Contents', 'Index', 'About', + ); + +# buttons for misc stuff +@T2H_MISC_BUTTONS = ('Top', 'Contents', 'Index', 'About'); + +# insert here name of icon images for buttons +# Icons are used, if $T2H_ICONS and resp. value are set +%T2H_ACTIVE_ICONS = + ( + 'Top', '', + 'Contents', '', + 'Overview', '', + 'Index', '', + 'Back', '', + 'FastBack', '', + 'Prev', '', + 'Up', '', + 'Next', '', + 'Forward', '', + 'FastForward', '', + 'About' , '', + 'First', '', + 'Last', '', + ' ', '' + ); + +# insert here name of icon images for these, if button is inactive +%T2H_PASSIVE_ICONS = + ( + 'Top', '', + 'Contents', '', + 'Overview', '', + 'Index', '', + 'Back', '', + 'FastBack', '', + 'Prev', '', + 'Up', '', + 'Next', '', + 'Forward', '', + 'FastForward', '', + 'About', '', + 'First', '', + 'Last', '', + ); + +# how to create IMG tag +sub T2H_DEFAULT_button_icon_img +{ + my $button = shift; + my $icon = shift; + my $name = shift; + return qq{$button: $name}; +} + +# Names of text as alternative for icons +%T2H_NAVIGATION_TEXT = + ( + 'Top', 'Top', + 'Contents', 'Contents', + 'Overview', 'Overview', + 'Index', 'Index', + ' ', '   ', + 'Back', ' < ', + 'FastBack', ' << ', + 'Prev', 'Prev', + 'Up', ' Up ', + 'Next', 'Next', + 'Forward', ' > ', + 'FastForward', ' >> ', + 'About', ' ? ', + 'First', ' |< ', + 'Last', ' >| ' + ); + +sub T2H_DEFAULT_print_navigation +{ + my $fh = shift; + my $vertical = shift; + my $spacing = 1; + print $fh "\n"; + + print $fh "" unless $vertical; + for $button (@$T2H_BUTTONS) + { + print $fh qq{\n} if $vertical; + print $fh qq{\n"; + print $fh "\n" if $vertical; + } + print $fh "" unless $vertical; + print $fh "
    }; + + if (ref($button) eq 'CODE') + { + &$button($fh, $vertical); + } + elsif ($button eq ' ') + { # handle space button + print $fh + $T2H_ICONS && $T2H_ACTIVE_ICONS{' '} ? + &$T2H_button_icon_img($button, $T2H_ACTIVE_ICONS{' '}) : + $T2H_NAVIGATION_TEXT{' '}; + next; + } + elsif ($T2H_HREF{$button}) + { # button is active + print $fh + $T2H_ICONS && $T2H_ACTIVE_ICONS{$button} ? # use icon ? + t2h_anchor('', $T2H_HREF{$button}, # yes + &$T2H_button_icon_img($button, + $T2H_ACTIVE_ICONS{$button}, + $T2H_NAME{$button})) + : # use text + "[" . + t2h_anchor('', $T2H_HREF{$button}, $T2H_NAVIGATION_TEXT{$button}) . + "]"; + } + else + { # button is passive + print $fh + $T2H_ICONS && $T2H_PASSIVE_ICONS{$button} ? + &$T2H_button_icon_img($button, + $T2H_PASSIVE_ICONS{$button}, + $T2H_NAME{$button}) : + + "[" . $T2H_NAVIGATION_TEXT{$button} . "]"; + } + print $fh "
    \n"; +} + +###################################################################### +# Frames: this is from "Richard Y. Kim" +# Should be improved to be more conforming to other _print* functions + +sub T2H_DEFAULT_print_frame +{ + my $fh = shift; + print $fh < +$T2H_THISDOC{title} + + + + + +EOT +} + +sub T2H_DEFAULT_print_toc_frame +{ + my $fh = shift; + &$T2H_print_page_head($fh); + print $fh <Content

    +EOT + print $fh map {s/HREF=/target=\"main\" HREF=/; $_;} @stoc_lines; + print $fh "\n"; +} + +###################################################################### +# About page +# + +# T2H_PRE_ABOUT might be a function +$T2H_PRE_ABOUT = <texi2html +

    +EOT +$T2H_AFTER_ABOUT = ''; + +sub T2H_DEFAULT_about_body +{ + my $about; + if (ref($T2H_PRE_ABOUT) eq 'CODE') + { + $about = &$T2H_PRE_ABOUT(); + } + else + { + $about = $T2H_PRE_ABOUT; + } + $about .= <

    + + + + + + + +EOT + + for $button (@T2H_SECTION_BUTTONS) + { + next if $button eq ' ' || ref($button) eq 'CODE'; + $about .= < + + + + +EOT + } + + $about .= < +

    +where the Example assumes that the current position +is at Subsubsection One-Two-Three of a document of +the following structure: +
      +
    • 1. Section One
      • +
        +
      • 1.1 Subsection One-One
        • +
          +
        • ...
          • +
        +
      • 1.2 Subsection One-Two
        • +
          +
        • 1.2.1 Subsubsection One-Two-One +
        • 1.2.2 Subsubsection One-Two-Two +
        • 1.2.3 Subsubsection One-Two-Three     +<== Current Position +
        • 1.2.4 Subsubsection One-Two-Four +
        +
      • 1.3 Subsection One-Three
        • +
          +
        • ...
          • +
        +
      • 1.4 Subsection One-Four
        • +
      +
    +$T2H_AFTER_ABOUT +EOT + return $about; +} + + +%T2H_BUTTONS_GOTO = + ( + 'Top', 'cover (top) of document', + 'Contents', 'table of contents', + 'Overview', 'short table of contents', + 'Index', 'concept index', + 'Back', 'previous section in reading order', + 'FastBack', 'previous or up-and-previous section ', + 'Prev', 'previous section same level', + 'Up', 'up section', + 'Next', 'next section same level', + 'Forward', 'next section in reading order', + 'FastForward', 'next or up-and-next section', + 'About' , 'this page', + 'First', 'first section in reading order', + 'Last', 'last section in reading order', + ); + +%T2H_BUTTONS_EXAMPLE = +( + 'Top', '   ', + 'Contents', '   ', + 'Overview', '   ', + 'Index', '   ', + 'Back', '1.2.2', + 'FastBack', '1.1', + 'Prev', '1.2.2', + 'Up', '1.2', + 'Next', '1.2.4', + 'Forward', '1.2.4', + 'FastForward', '1.3', + 'About', '   ', + 'First', '1.', + 'Last', '1.2.4', +); + + +###################################################################### +# from here on, its l2h init stuff +# + +## initialization for latex2html as for Singular manual generation +## obachman 3/99 + +# +# Options controlling Titles, File-Names, Tracing and Sectioning +# +$TITLE = ''; + +$SHORTEXTN = 0; + +$LONG_TITLES = 0; + +$DESTDIR = ''; # should be overwritten by cmd-line argument + +$NO_SUBDIR = 0;# should be overwritten by cmd-line argument + +$PREFIX = ''; # should be overwritten by cmd-line argument + +$AUTO_PREFIX = 0; # this is needed, so that prefix settings are used + +$AUTO_LINK = 0; + +$SPLIT = 0; + +$MAX_LINK_DEPTH = 0; + +$TMP = ''; # should be overwritten by cmd-line argument + +$DEBUG = 0; + +$VERBOSE = 1; + +# +# Options controlling Extensions and Special Features +# +$HTML_VERSION = "3.2"; + +$TEXDEFS = 1; # we absolutely need that + +$EXTERNAL_FILE = ''; + +$SCALABLE_FONTS = 1; + +$NO_SIMPLE_MATH = 1; + +$LOCAL_ICONS = 1; + +$SHORT_INDEX = 0; + +$NO_FOOTNODE = 1; + +$ADDRESS = ''; + +$INFO = ''; + +# +# Switches controlling Image Generation +# +$ASCII_MODE = 0; + +$NOLATEX = 0; + +$EXTERNAL_IMAGES = 0; + +$PS_IMAGES = 0; + +$NO_IMAGES = 0; + +$IMAGES_ONLY = 0; + +$REUSE = 2; + +$ANTI_ALIAS = 1; + +$ANTI_ALIAS_TEXT = 1; + +# +#Switches controlling Navigation Panels +# +$NO_NAVIGATION = 1; +$ADDRESS = ''; +$INFO = 0; # 0 = do not make a "About this document..." section + +# +#Switches for Linking to other documents +# +# actuall -- we don't care + +$MAX_SPLIT_DEPTH = 0; # Stop making separate files at this depth + +$MAX_LINK_DEPTH = 0; # Stop showing child nodes at this depth + +$NOLATEX = 0; # 1 = do not pass unknown environments to Latex + +$EXTERNAL_IMAGES = 0; # 1 = leave the images outside the document + +$ASCII_MODE = 0; # 1 = do not use any icons or internal images + +# 1 = use links to external postscript images rather than inlined bitmap +# images. +$PS_IMAGES = 0; +$SHOW_SECTION_NUMBERS = 0; + +### Other global variables ############################################### +$CHILDLINE = ""; + +# This is the line width measured in pixels and it is used to right justify +# equations and equation arrays; +$LINE_WIDTH = 500; + +# Used in conjunction with AUTO_NAVIGATION +$WORDS_IN_PAGE = 300; + +# Affects ONLY the way accents are processed +$default_language = 'english'; + +# The value of this variable determines how many words to use in each +# title that is added to the navigation panel (see below) +# +$WORDS_IN_NAVIGATION_PANEL_TITLES = 0; + +# This number will determine the size of the equations, special characters, +# and anything which will be converted into an inlined image +# *except* "image generating environments" such as "figure", "table" +# or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$MATH_SCALE_FACTOR = 1.5; + +# This number will determine the size of +# image generating environments such as "figure", "table" or "minipage". +# Effective values are those greater than 0. +# Sensible values are between 0.1 - 4. +$FIGURE_SCALE_FACTOR = 1.6; + + +# If both of the following two variables are set then the "Up" button +# of the navigation panel in the first node/page of a converted document +# will point to $EXTERNAL_UP_LINK. $EXTERNAL_UP_TITLE should be set +# to some text which describes this external link. +$EXTERNAL_UP_LINK = ""; +$EXTERNAL_UP_TITLE = ""; + +# If this is set then the resulting HTML will look marginally better if viewed +# with Netscape. +$NETSCAPE_HTML = 1; + +# Valid paper sizes are "letter", "legal", "a4","a3","a2" and "a0" +# Paper sizes has no effect other than in the time it takes to create inlined +# images and in whether large images can be created at all ie +# - larger paper sizes *MAY* help with large image problems +# - smaller paper sizes are quicker to handle +$PAPERSIZE = "a4"; + +# Replace "english" with another language in order to tell LaTeX2HTML that you +# want some generated section titles (eg "Table of Contents" or "References") +# to appear in a different language. Currently only "english" and "french" +# is supported but it is very easy to add your own. See the example in the +# file "latex2html.config" +$TITLES_LANGUAGE = "english"; + +1; # This must be the last non-comment line + +# End File texi2html.init +###################################################################### + + +require "$ENV{T2H_HOME}/texi2html.init" + if ($0 =~ /\.pl$/ && + -e "$ENV{T2H_HOME}/texi2html.init" && -r "$ENV{T2H_HOME}/texi2html.init"); + +#+++############################################################################ +# # +# Initialization # +# Pasted content of File $(srcdir)/MySimple.pm: Command-line processing # +# # +#---############################################################################ + +# leave this within comments, and keep the require statement +# This way, you can directly run texi2html.pl, if $ENV{T2H_HOME}/texi2html.init +# exists. + +# +package Getopt::MySimple; + +# Name: +# Getopt::MySimple. +# +# Documentation: +# POD-style (incomplete) documentation is in file MySimple.pod +# +# Tabs: +# 4 spaces || die. +# +# Author: +# Ron Savage rpsavage@ozemail.com.au. +# 1.00 19-Aug-97 Initial version. +# 1.10 13-Oct-97 Add arrays of switches (eg '=s@'). +# 1.20 3-Dec-97 Add 'Help' on a per-switch basis. +# 1.30 11-Dec-97 Change 'Help' to 'verbose'. Make all hash keys lowercase. +# 1.40 10-Nov-98 Change width of help report. Restructure tests. +# 1-Jul-00 Modifications for Texi2html + +# -------------------------------------------------------------------------- +# Locally modified by obachman (Display type instead of env, order by cmp) +# $Id: texi2html,v 1.1.1.1 2011/09/24 19:56:56 christos Exp $ + +# use strict; +# no strict 'refs'; + +use vars qw(@EXPORT @EXPORT_OK @ISA); +use vars qw($fieldWidth $opt $VERSION); + +use Exporter(); +use Getopt::Long; + +@ISA = qw(Exporter); +@EXPORT = qw(); +@EXPORT_OK = qw($opt); # An alias for $self -> {'opt'}. + +# -------------------------------------------------------------------------- + +$fieldWidth = 20; +$VERSION = '1.41'; + +# -------------------------------------------------------------------------- + +sub byOrder +{ + my($self) = @_; + + return uc($a) cmp (uc($b)); +} + +# -------------------------------------------------------------------------- + +sub dumpOptions +{ + my($self) = @_; + + print 'Option', ' ' x ($fieldWidth - length('Option') ), "Value\n"; + + for (sort byOrder keys(%{$self -> {'opt'} }) ) + { + print "-$_", ' ' x ($fieldWidth - (1 + length) ), "${$self->{'opt'} }{$_}\n"; + } + + print "\n"; + +} # End of dumpOptions. + +# -------------------------------------------------------------------------- +# Return: +# 0 -> Error. +# 1 -> Ok. + +sub getOptions +{ + push(@_, 0) if ($#_ == 2); # Default for $ignoreCase is 0. + push(@_, 1) if ($#_ == 3); # Default for $helpThenExit is 1. + + my($self, $default, $helpText, $versionText, + $helpThenExit, $versionThenExit, $ignoreCase) = @_; + + $helpThenExit = 1 unless (defined($helpThenExit)); + $versionThenExit = 1 unless (defined($versionThenExit)); + $ignoreCase = 0 unless (defined($ignoreCase)); + + $self -> {'default'} = $default; + $self -> {'helpText'} = $helpText; + $self -> {'versionText'} = $versionText; + $Getopt::Long::ignorecase = $ignoreCase; + + unless (defined($self -> {'default'}{'help'})) + { + $self -> {'default'}{'help'} = + { + type => ':i', + default => '', + linkage => sub {$self->helpOptions($_[1]); exit (0) if $helpThenExit;}, + verbose => "print help and exit" + }; + } + + unless (defined($self -> {'default'}{'version'})) + { + $self -> {'default'}{'version'} = + { + type => '', + default => '', + linkage => sub {print $self->{'versionText'}; exit (0) if versionTheExit;}, + verbose => "print version and exit" + }; + } + + for (keys(%{$self -> {'default'} }) ) + { + my $type = ${$self -> {'default'} }{$_}{'type'}; + push(@{$self -> {'type'} }, "$_$type"); + $self->{'opt'}->{$_} = ${$self -> {'default'} }{$_}{'linkage'} + if ${$self -> {'default'} }{$_}{'linkage'}; + } + + my($result) = &GetOptions($self -> {'opt'}, @{$self -> {'type'} }); + + return $result unless $result; + + for (keys(%{$self -> {'default'} }) ) + { + if (! defined(${$self -> {'opt'} }{$_})) #{ + { + ${$self -> {'opt'} }{$_} = ${$self -> {'default'} }{$_}{'default'}; + } + } + + $result; +} # End of getOptions. + +# -------------------------------------------------------------------------- + +sub helpOptions +{ + my($self) = shift; + my($noHelp) = shift; + $noHelp = 0 unless $noHelp; + my($optwidth, $typewidth, $defaultwidth, $maxlinewidth, $valind, $valwidth) + = (10, 5, 9, 78, 4, 11); + + print "$self->{'helpText'}" if ($self -> {'helpText'}); + + print ' Option', ' ' x ($optwidth - length('Option') -1 ), + 'Type', ' ' x ($typewidth - length('Type') + 1), + 'Default', ' ' x ($defaultwidth - length('Default') ), + "Description\n"; + + for (sort byOrder keys(%{$self -> {'default'} }) ) + { + my($line, $help, $option, $val); + $option = $_; + next if ${$self->{'default'} }{$_}{'noHelp'} && ${$self->{'default'} }{$_}{'noHelp'} > $noHelp; + $line = " -$_ " . ' ' x ($optwidth - (2 + length) ) . + "${$self->{'default'} }{$_}{'type'} ". + ' ' x ($typewidth - (1+length(${$self -> {'default'} }{$_}{'type'}) )); + + $val = ${$self->{'default'} }{$_}{'linkage'}; + if ($val) + { + if (ref($val) eq 'SCALAR') + { + $val = $$val; + } + else + { + $val = ''; + } + } + else + { + $val = ${$self->{'default'} }{$_}{'default'}; + } + $line .= "$val "; + $line .= ' ' x ($optwidth + $typewidth + $defaultwidth + 1 - length($line)); + + if (defined(${$self -> {'default'} }{$_}{'verbose'}) && + ${$self -> {'default'} }{$_}{'verbose'} ne '') + { + $help = "${$self->{'default'} }{$_}{'verbose'}"; + } + else + { + $help = ' '; + } + if ((length("$line") + length($help)) < $maxlinewidth) + { + print $line , $help, "\n"; + } + else + { + print $line, "\n", ' ' x $valind, $help, "\n"; + } + for $val (sort byOrder keys(%{${$self->{'default'}}{$option}{'values'}})) + { + print ' ' x ($valind + 2); + print $val, ' ', ' ' x ($valwidth - length($val) - 2); + print ${$self->{'default'}}{$option}{'values'}{$val}, "\n"; + } + } + + print <| ! no argument: variable is set to 1 on -foo (or, to 0 on -nofoo) + =s | :s mandatory (or, optional) string argument + =i | :i mandatory (or, optional) integer argument +EOT +} # End of helpOptions. + +#------------------------------------------------------------------- + +sub new +{ + my($class) = @_; + my($self) = {}; + $self -> {'default'} = {}; + $self -> {'helpText'} = ''; + $self -> {'opt'} = {}; + $opt = $self -> {'opt'}; # An alias for $self -> {'opt'}. + $self -> {'type'} = (); + + return bless $self, $class; + +} # End of new. + +# -------------------------------------------------------------------------- + +1; + +# End MySimple.pm + +require "$ENV{T2H_HOME}/MySimple.pm" + if ($0 =~ /\.pl$/ && + -e "$ENV{T2H_HOME}/texi2html.init" && -r "$ENV{T2H_HOME}/texi2html.init"); + +package main; + +#+++############################################################################ +# # +# Constants # +# # +#---############################################################################ + +$DEBUG_TOC = 1; +$DEBUG_INDEX = 2; +$DEBUG_BIB = 4; +$DEBUG_GLOSS = 8; +$DEBUG_DEF = 16; +$DEBUG_HTML = 32; +$DEBUG_USER = 64; +$DEBUG_L2H = 128; + + +$BIBRE = '\[[\w\/-]+\]'; # RE for a bibliography reference +$FILERE = '[\/\w.+-]+'; # RE for a file name +$VARRE = '[^\s\{\}]+'; # RE for a variable name +$NODERE = '[^,:]+'; # RE for a node name +$NODESRE = '[^:]+'; # RE for a list of node names + +$ERROR = "***"; # prefix for errors +$WARN = "**"; # prefix for warnings + + # program home page +$PROTECTTAG = "_ThisIsProtected_"; # tag to recognize protected sections + +$CHAPTEREND = "\n"; # to know where a chpater ends +$SECTIONEND = "\n"; # to know where section ends +$TOPEND = "\n"; # to know where top ends + + + +# +# pre-defined indices +# +$index_properties = +{ + 'c' => { name => 'cp'}, + 'f' => { name => 'fn', code => 1}, + 'v' => { name => 'vr', code => 1}, + 'k' => { name => 'ky', code => 1}, + 'p' => { name => 'pg', code => 1}, + 't' => { name => 'tp', code => 1} +}; + + +%predefined_index = ( + 'cp', 'c', + 'fn', 'f', + 'vr', 'v', + 'ky', 'k', + 'pg', 'p', + 'tp', 't', + ); + +# +# valid indices +# +%valid_index = ( + 'c', 1, + 'f', 1, + 'v', 1, + 'k', 1, + 'p', 1, + 't', 1, + ); + +# +# texinfo section names to level +# +%sec2level = ( + 'top', 0, + 'chapter', 1, + 'unnumbered', 1, + 'majorheading', 1, + 'chapheading', 1, + 'appendix', 1, + 'section', 2, + 'unnumberedsec', 2, + 'heading', 2, + 'appendixsec', 2, + 'appendixsection', 2, + 'subsection', 3, + 'unnumberedsubsec', 3, + 'subheading', 3, + 'appendixsubsec', 3, + 'subsubsection', 4, + 'unnumberedsubsubsec', 4, + 'subsubheading', 4, + 'appendixsubsubsec', 4, + ); + +# +# accent map, TeX command to ISO name +# +%accent_map = ( + '"', 'uml', + '~', 'tilde', + '^', 'circ', + '`', 'grave', + '\'', 'acute', + ); + +# +# texinfo "simple things" (@foo) to HTML ones +# +%simple_map = ( + # cf. makeinfo.c + "*", "
    ", # HTML+ + " ", " ", + "\t", " ", + "-", "­", # soft hyphen + "\n", "\n", + "|", "", + 'tab', '<\/TD>
    Button Name Go to From 1.2.3 go to
    +EOT + $about .= + ($T2H_ICONS && $T2H_ACTIVE_ICONS{$button} ? + &$T2H_button_icon_img($button, $T2H_ACTIVE_ICONS{$button}) : + " [" . $T2H_NAVIGATION_TEXT{$button} . "] "); + $about .= < + +$button + +$T2H_BUTTONS_GOTO{$button} + +$T2H_BUTTONS_EXAMPLE{$button} +
    ', + # spacing commands + ":", "", + "!", "!", + "?", "?", + ".", ".", + "-", "", + ); + +# +# texinfo "things" (@foo{}) to HTML ones +# +%things_map = ( + 'TeX', 'TeX', + 'br', '

    ', # paragraph break + 'bullet', '*', + 'copyright', '(C)', + 'dots', '...<\/small>', + 'enddots', '....<\/small>', + 'equiv', '==', + 'error', 'error-->', + 'expansion', '==>', + 'minus', '-', + 'point', '-!-', + 'print', '-|', + 'result', '=>', + 'today', $T2H_TODAY, + 'aa', 'å', + 'AA', 'Å', + 'ae', 'æ', + 'oe', 'œ', + 'AE', 'Æ', + 'OE', 'Œ', + 'o', 'ø', + 'O', 'Ø', + 'ss', 'ß', + 'l', '\/l', + 'L', '\/L', + 'exclamdown', '¡', + 'questiondown', '¿', + 'pounds', '£' + ); + +# +# texinfo styles (@foo{bar}) to HTML ones +# +%style_map = ( + 'acronym', '&do_acronym', + 'asis', '', + 'b', 'B', + 'cite', 'CITE', + 'code', 'CODE', + 'command', 'CODE', + 'ctrl', '&do_ctrl', # special case + 'dfn', 'EM', # DFN tag is illegal in the standard + 'dmn', '', # useless + 'email', '&do_email', # insert a clickable email address + 'emph', 'EM', + 'env', 'CODE', + 'file', '"TT', # will put quotes, cf. &apply_style + 'i', 'I', + 'kbd', 'KBD', + 'key', 'KBD', + 'math', '&do_math', + 'option', '"SAMP', # will put quotes, cf. &apply_style + 'r', '', # unsupported + 'samp', '"SAMP', # will put quotes, cf. &apply_style + 'sc', '&do_sc', # special case + 'strong', 'STRONG', + 't', 'TT', + 'titlefont', '', # useless + 'uref', '&do_uref', # insert a clickable URL + 'url', '&do_url', # insert a clickable URL + 'var', 'VAR', + 'w', '', # unsupported + 'H', '&do_accent', + 'dotaccent', '&do_accent', + 'ringaccent','&do_accent', + 'tieaccent', '&do_accent', + 'u','&do_accent', + 'ubaraccent','&do_accent', + 'udotaccent','&do_accent', + 'v', '&do_accent', + ',', '&do_accent', + 'dotless', '&do_accent' + ); + +# +# texinfo format (@foo/@end foo) to HTML ones +# +%format_map = ( + 'quotation', 'BLOCKQUOTE', + # lists + 'itemize', 'UL', + 'enumerate', 'OL', + # poorly supported + 'flushleft', 'PRE', + 'flushright', 'PRE', + ); + +# +# an eval of these $complex_format_map->{what}->[0] yields beginning +# an eval of these $complex_format_map->{what}->[1] yieleds end +$complex_format_map = +{ + example => + [ + q{"$T2H_EXAMPLE_INDENT_CELL
    "},
+  q{'
    '} + ], + smallexample => + [ + q{"$T2H_SMALL_EXAMPLE_INDENT_CELL
    "},
+  q{'
    '} + ], + display => + [ + q{"$T2H_EXAMPLE_INDENT_CELL
    '},
+  q{'
    '} + ], + smalldisplay => + [ + q{"$T2H_SMALL_EXAMPLE_INDENT_CELL
    '},
+  q{'
    '} + ] +}; + +$complex_format_map->{lisp} = $complex_format_map->{example}; +$complex_format_map->{smalllisp} = $complex_format_map->{smallexample}; +$complex_format_map->{format} = $complex_format_map->{display}; +$complex_format_map->{smallformat} = $complex_format_map->{smalldisplay}; + +# +# texinfo definition shortcuts to real ones +# +%def_map = ( + # basic commands + 'deffn', 0, + 'defvr', 0, + 'deftypefn', 0, + 'deftypevr', 0, + 'defcv', 0, + 'defop', 0, + 'deftp', 0, + # basic x commands + 'deffnx', 0, + 'defvrx', 0, + 'deftypefnx', 0, + 'deftypevrx', 0, + 'defcvx', 0, + 'defopx', 0, + 'deftpx', 0, + # shortcuts + 'defun', 'deffn Function', + 'defmac', 'deffn Macro', + 'defspec', 'deffn {Special Form}', + 'defvar', 'defvr Variable', + 'defopt', 'defvr {User Option}', + 'deftypefun', 'deftypefn Function', + 'deftypevar', 'deftypevr Variable', + 'defivar', 'defcv {Instance Variable}', + 'deftypeivar', 'defcv {Instance Variable}', # NEW: FIXME + 'defmethod', 'defop Method', + 'deftypemethod', 'defop Method', # NEW:FIXME + # x shortcuts + 'defunx', 'deffnx Function', + 'defmacx', 'deffnx Macro', + 'defspecx', 'deffnx {Special Form}', + 'defvarx', 'defvrx Variable', + 'defoptx', 'defvrx {User Option}', + 'deftypefunx', 'deftypefnx Function', + 'deftypevarx', 'deftypevrx Variable', + 'defivarx', 'defcvx {Instance Variable}', + 'defmethodx', 'defopx Method', + ); + +# +# things to skip +# +%to_skip = ( + # comments + 'c', 1, + 'comment', 1, + 'ifnotinfo', 1, + 'ifnottex', 1, + 'ifhtml', 1, + 'end ifhtml', 1, + 'end ifnotinfo', 1, + 'end ifnottex', 1, + # useless + 'detailmenu', 1, + 'direntry', 1, + 'contents', 1, + 'shortcontents', 1, + 'summarycontents', 1, + 'footnotestyle', 1, + 'end ifclear', 1, + 'end ifset', 1, + 'titlepage', 1, + 'end titlepage', 1, + # unsupported commands (formatting) + 'afourpaper', 1, + 'cropmarks', 1, + 'finalout', 1, + 'headings', 1, + 'sp', 1, + 'need', 1, + 'page', 1, + 'setchapternewpage', 1, + 'everyheading', 1, + 'everyfooting', 1, + 'evenheading', 1, + 'evenfooting', 1, + 'oddheading', 1, + 'oddfooting', 1, + 'smallbook', 1, + 'vskip', 1, + 'filbreak', 1, + 'paragraphindent', 1, + # unsupported formats + 'cartouche', 1, + 'end cartouche', 1, + 'group', 1, + 'end group', 1, + ); + +#+++############################################################################ +# # +# Argument parsing, initialisation # +# # +#---############################################################################ + +# +# flush stdout and stderr after every write +# +select(STDERR); +$| = 1; +select(STDOUT); +$| = 1; + + +%value = (); # hold texinfo variables, see also -D +$use_bibliography = 1; +$use_acc = 1; + +# +# called on -init-file +sub LoadInitFile +{ + my $init_file = shift; + # second argument is value of options + $init_file = shift; + if (-f $init_file) + { + print "# reading initialization file from $init_file\n" + if ($T2H_VERBOSE); + require($init_file); + } + else + { + print "$ERROR Error: can't read init file $int_file\n"; + $init_file = ''; + } +} + +# +# called on -lang +sub SetDocumentLanguage +{ + my $lang = shift; + if (! exists($T2H_WORDS->{$lang})) + { + warn "$ERROR: Language specs for '$lang' do not exists. Reverting to '" . + ($T2H_LANG ? T2H_LANG : "en") . "'\n"; + } + else + { + print "# using '$lang' as document language\n" if ($T2H_VERBOSE); + $T2H_LANG = $lang; + } +} + +## +## obsolete cmd line options +## +$T2H_OBSOLETE_OPTIONS -> {'no-section_navigation'} = +{ + type => '!', + linkage => sub {$main::T2H_SECTION_NAVIGATION = 0;}, + verbose => 'obsolete, use -nosec_nav', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {use_acc} = +{ + type => '!', + linkage => \$use_acc, + verbose => 'obsolete', + noHelp => 2 +}; +$T2H_OBSOLETE_OPTIONS -> {expandinfo} = +{ + type => '!', + linkage => sub {$main::T2H_EXPAND = 'info';}, + verbose => 'obsolete, use "-expand info" instead', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {expandtex} = +{ + type => '!', + linkage => sub {$main::T2H_EXPAND = 'tex';}, + verbose => 'obsolete, use "-expand tex" instead', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {monolithic} = +{ + type => '!', + linkage => sub {$main::T2H_SPLIT = '';}, + verbose => 'obsolete, use "-split no" instead', + noHelp => 2 +}; +$T2H_OBSOLETE_OPTIONS -> {split_node} = +{ + type => '!', + linkage => sub{$main::T2H_SPLIT = 'section';}, + verbose => 'obsolete, use "-split section" instead', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {split_chapter} = +{ + type => '!', + linkage => sub{$main::T2H_SPLIT = 'chapter';}, + verbose => 'obsolete, use "-split chapter" instead', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {no_verbose} = +{ + type => '!', + linkage => sub {$main::T2H_VERBOSE = 0;}, + verbose => 'obsolete, use -noverbose instead', + noHelp => 2, +}; +$T2H_OBSOLETE_OPTIONS -> {output_file} = +{ + type => '=s', + linkage => sub {$main::T2H_OUT = @_[1]; $T2H_SPLIT = '';}, + verbose => 'obsolete, use -out_file instead', + noHelp => 2 +}; + +$T2H_OBSOLETE_OPTIONS -> {section_navigation} = +{ + type => '!', + linkage => \$T2H_SECTION_NAVIGATION, + verbose => 'obsolete, use -sec_nav instead', + noHelp => 2, +}; + +$T2H_OBSOLETE_OPTIONS -> {verbose} = +{ + type => '!', + linkage => \$T2H_VERBOSE, + verbose => 'obsolete, use -Verbose instead', + noHelp => 2 +}; + +# read initialzation from $sysconfdir/texi2htmlrc or $HOME/.texi2htmlrc +my $home = $ENV{HOME}; +defined($home) or $home = ''; +foreach $i ('/usr/local/etc/texi2htmlrc', "$home/.texi2htmlrc") { + if (-f $i) { + print "# reading initialization file from $i\n" + if ($T2H_VERBOSE); + require($i); + } +} + + +#+++############################################################################ +# # +# parse command-line options +# # +#---############################################################################ +$T2H_USAGE_TEXT = <getOptions($T2H_OPTIONS, $T2H_USAGE_TEXT, "$THISVERSION\n")) +{ + print $Configure_failed if $Configure_failed; + die $T2H_FAILURE_TEXT; +} + +if (@ARGV > 1) +{ + eval {Getopt::Long::Configure("no_pass_through");}; + if (! $options->getOptions($T2H_OBSOLETE_OPTIONS, $T2H_USAGE_TEXT, "$THISVERSION\n")) + { + print $Configure_failed if $Configure_failed; + die $T2H_FAILURE_TEXT; + } +} + +if ($T2H_CHECK) { + die "Need file to check\n$T2H_FAILURE_TEXT" unless @ARGV > 0; + ✓ + exit; +} + +#+++############################################################################ +# # +# evaluation of cmd line options +# # +#---############################################################################ + +if ($T2H_EXPAND eq 'info') +{ + $to_skip{'ifinfo'} = 1; + $to_skip{'end ifinfo'} = 1; +} +elsif ($T2H_EXPAND eq 'tex') +{ + $to_skip{'iftex'} = 1; + $to_skip{'end iftex'} = 1; + +} + +$T2H_INVISIBLE_MARK = '' if $T2H_INVISIBLE_MARK eq 'xbm'; + +# +# file name buisness +# +die "Need exactly one file to translate\n$T2H_FAILURE_TEXT" unless @ARGV == 1; +$docu = shift(@ARGV); +if ($docu =~ /.*\//) { + chop($docu_dir = $&); + $docu_name = $'; +} else { + $docu_dir = '.'; + $docu_name = $docu; +} +unshift(@T2H_INCLUDE_DIRS, $docu_dir); +$docu_name =~ s/\.te?x(i|info)?$//; # basename of the document +$docu_name = $T2H_PREFIX if ($T2H_PREFIX); + +# subdir +if ($T2H_SUBDIR && ! $T2H_OUT) +{ + $T2H_SUBDIR =~ s|/*$||; + unless (-d "$T2H_SUBDIR" && -w "$T2H_SUBDIR") + { + if ( mkdir($T2H_SUBDIR, oct(755))) + { + print "# created directory $T2H_SUBDIR\n" if ($T2H_VERBOSE); + } + else + { + warn "$ERROR can't create directory $T2H_SUBDIR. Put results into current directory\n"; + $T2H_SUBDIR = ''; + } + } +} + +if ($T2H_SUBDIR && ! $T2H_OUT) +{ + $docu_rdir = "$T2H_SUBDIR/"; + print "# putting result files into directory $docu_rdir\n" if ($T2H_VERBOSE); +} +else +{ + if ($T2H_OUT && $T2H_OUT =~ m|(.*)/|) + { + $docu_rdir = "$1/"; + print "# putting result files into directory $docu_rdir\n" if ($T2H_VERBOSE); + } + else + { + print "# putting result files into current directory \n" if ($T2H_VERBOSE); + $docu_rdir = ''; + } +} + +# extension +if ($T2H_SHORTEXTN) +{ + $docu_ext = "htm"; +} +else +{ + $docu_ext = "html"; +} +if ($T2H_TOP_FILE =~ /\..*$/) +{ + $T2H_TOP_FILE = $`.".$docu_ext"; +} + +# result files +if (! $T2H_OUT && ($T2H_SPLIT =~ /section/i || $T2H_SPLIT =~ /node/i)) +{ + $T2H_SPLIT = 'section'; +} +elsif (! $T2H_OUT && $T2H_SPLIT =~ /chapter/i) +{ + $T2H_SPLIT = 'chapter' +} +else +{ + undef $T2H_SPLIT; +} + +$docu_doc = "$docu_name.$docu_ext"; # document's contents +$docu_doc_file = "$docu_rdir$docu_doc"; +if ($T2H_SPLIT) +{ + $docu_toc = $T2H_TOC_FILE || "${docu_name}_toc.$docu_ext"; # document's table of contents + $docu_stoc = "${docu_name}_ovr.$docu_ext"; # document's short toc + $docu_foot = "${docu_name}_fot.$docu_ext"; # document's footnotes + $docu_about = "${docu_name}_abt.$docu_ext"; # about this document + $docu_top = $T2H_TOP_FILE || $docu_doc; +} +else +{ + if ($T2H_OUT) + { + $docu_doc = $T2H_OUT; + $docu_doc =~ s|.*/||; + } + $docu_toc = $docu_foot = $docu_stoc = $docu_about = $docu_top = $docu_doc; +} + +$docu_toc_file = "$docu_rdir$docu_toc"; +$docu_stoc_file = "$docu_rdir$docu_stoc"; +$docu_foot_file = "$docu_rdir$docu_foot"; +$docu_about_file = "$docu_rdir$docu_about"; +$docu_top_file = "$docu_rdir$docu_top"; + +$docu_frame_file = "$docu_rdir${docu_name}_frame.$docu_ext"; +$docu_toc_frame_file = "$docu_rdir${docu_name}_toc_frame.$docu_ext"; + +# +# variables +# +$value{'html'} = 1; # predefine html (the output format) +$value{'texi2html'} = $THISVERSION; # predefine texi2html (the translator) +# _foo: internal to track @foo +foreach ('_author', '_title', '_subtitle', + '_settitle', '_setfilename', '_shorttitle') { + $value{$_} = ''; # prevent -w warnings +} +%node2sec = (); # node to section name +%sec2node = (); # section to node name +%sec2number = (); # section to number +%number2sec = (); # number to section +%idx2node = (); # index keys to node +%node2href = (); # node to HREF +%node2next = (); # node to next +%node2prev = (); # node to prev +%node2up = (); # node to up +%bib2href = (); # bibliography reference to HREF +%gloss2href = (); # glossary term to HREF +@sections = (); # list of sections +%tag2pro = (); # protected sections + +# +# initial indexes +# +$bib_num = 0; +$foot_num = 0; +$gloss_num = 0; +$idx_num = 0; +$sec_num = 0; +$doc_num = 0; +$html_num = 0; + +# +# can I use ISO8879 characters? (HTML+) +# +if ($T2H_USE_ISO) { + $things_map{'bullet'} = "•"; + $things_map{'copyright'} = "©"; + $things_map{'dots'} = "…"; + $things_map{'equiv'} = "≡"; + $things_map{'expansion'} = "→"; + $things_map{'point'} = "∗"; + $things_map{'result'} = "⇒"; +} + +# +# read texi2html extensions (if any) +# +$extensions = 'texi2html.ext'; # extensions in working directory +if (-f $extensions) { + print "# reading extensions from $extensions\n" if $T2H_VERBOSE; + require($extensions); +} +($progdir = $0) =~ s/[^\/]+$//; +if ($progdir && ($progdir ne './')) { + $extensions = "${progdir}texi2html.ext"; # extensions in texi2html directory + if (-f $extensions) { + print "# reading extensions from $extensions\n" if $T2H_VERBOSE; + require($extensions); + } +} + + +print "# reading from $docu\n" if $T2H_VERBOSE; + +######################################################################### +# +# latex2html stuff +# +# latex2html conversions consist of three stages: +# 1) ToLatex: Put "latex" code into a latex file +# 2) ToHtml: Use latex2html to generate corresponding html code and images +# 3) FromHtml: Extract generated code and images from latex2html run +# + +########################## +# default settings +# + +# defaults for files and names + +sub l2h_Init +{ + local($root) = @_; + + return 0 unless ($root); + + $l2h_name = "${root}_l2h"; + + $l2h_latex_file = "$docu_rdir${l2h_name}.tex"; + $l2h_cache_file = "${docu_rdir}l2h_cache.pm"; + $T2H_L2H_L2H = "latex2html" unless ($T2H_L2H_L2H); + + # destination dir -- generated images are put there, should be the same + # as dir of enclosing html document -- + $l2h_html_file = "$docu_rdir${l2h_name}.html"; + $l2h_prefix = "${l2h_name}_"; + return 1; +} + + +########################## +# +# First stage: Generation of Latex file +# Initialize with: l2h_InitToLatex +# Add content with: l2h_ToLatex($text) --> HTML placeholder comment +# Finish with: l2h_FinishToLatex +# + +$l2h_latex_preample = <$l2h_latex_file")) + { + warn "$ERROR Error l2h: Can't open latex file '$latex_file' for writing\n"; + return 0; + } + print "# l2h: use ${l2h_latex_file} as latex file\n" if ($T2H_VERBOSE); + print L2H_LATEX $l2h_latex_preample; + } + # open database for caching + l2h_InitCache(); + $l2h_latex_count = 0; + $l2h_to_latex_count = 0; + $l2h_cached_count = 0; + return 1; +} + +# print text (1st arg) into latex file (if not already there), return +# HTML commentary which can be later on replaced by the latex2html +# generated text +sub l2h_ToLatex +{ + my($text) = @_; + my($count); + + $l2h_to_latex_count++; + $text =~ s/(\s*)$//; + + # try whether we can cache it + my $cached_text = l2h_FromCache($text); + if ($cached_text) + { + $l2h_cached_count++; + return $cached_text; + } + + # try whether we have text already on things to do + unless ($count = $l2h_to_latex{$text}) + { + $count = $l2h_latex_count; + $l2h_latex_count++; + $l2h_to_latex{$text} = $count; + $l2h_to_latex[$count] = $text; + unless ($T2H_L2H_SKIP) + { + print L2H_LATEX "\\begin{rawhtml}\n"; + print L2H_LATEX "\n"; + print L2H_LATEX "\\end{rawhtml}\n"; + + print L2H_LATEX "$text\n"; + + print L2H_LATEX "\\begin{rawhtml}\n"; + print L2H_LATEX "\n"; + print L2H_LATEX "\\end{rawhtml}\n"; + } + } + return ""; +} + +# print closing into latex file and close it +sub l2h_FinishToLatex +{ + local ($reused); + + $reused = $l2h_to_latex_count - $l2h_latex_count - $l2h_cached_count; + unless ($T2H_L2H_SKIP) + { + print L2H_LATEX $l2h_latex_closing; + close(L2H_LATEX); + } + print "# l2h: finished to latex ($l2h_cached_count cached, $reused reused, $l2h_latex_count contents)\n" if ($T2H_VERBOSE); + unless ($l2h_latex_count) + { + l2h_Finish(); + return 0; + } + return 1; +} + +################################### +# Second stage: Use latex2html to generate corresponding html code and images +# +# l2h_ToHtml([$l2h_latex_file, [$l2h_html_dir]]): +# Call latex2html on $l2h_latex_file +# Put images (prefixed with $l2h_name."_") and html file(s) in $l2h_html_dir +# Return 1, on success +# 0, otherwise +# +sub l2h_ToHtml +{ + local($call, $ext, $root, $dotbug); + + if ($T2H_L2H_SKIP) + { + print "# l2h: skipping latex2html run\n" if ($T2H_VERBOSE); + return 1; + } + + # Check for dot in directory where dvips will work + if ($T2H_L2H_TMP) + { + if ($T2H_L2H_TMP =~ /\./) + { + warn "$ERROR Warning l2h: l2h_tmp dir contains a dot. Use /tmp, instead\n"; + $dotbug = 1; + } + } + else + { + if (&getcwd =~ /\./) + { + warn "$ERROR Warning l2h: current dir contains a dot. Use /tmp as l2h_tmp dir \n"; + $dotbug = 1; + } + } + # fix it, if necessary and hope that it works + $T2H_L2H_TMP = "/tmp" if ($dotbug); + + $call = $T2H_L2H_L2H; + # use init file, if specified + $call = $call . " -init_file " . $init_file if ($init_file && -f $init_file); + # set output dir + $call .= ($docu_rdir ? " -dir $docu_rdir" : " -no_subdir"); + # use l2h_tmp, if specified + $call = $call . " -tmp $T2H_L2H_TMP" if ($T2H_L2H_TMP); + # options we want to be sure of + $call = $call ." -address 0 -info 0 -split 0 -no_navigation -no_auto_link"; + $call = $call ." -prefix ${l2h_prefix} $l2h_latex_file"; + + print "# l2h: executing '$call'\n" if ($T2H_VERBOSE); + if (system($call)) + { + warn "l2h ***Error: '${call}' did not succeed\n"; + return 0; + } + else + { + print "# l2h: latex2html finished successfully\n" if ($T2H_VERBOSE); + return 1; + } +} + +# this is directly pasted over from latex2html +sub getcwd { + local($_) = `pwd`; + + die "'pwd' failed (out of memory?)\n" + unless length; + chop; + $_; +} + + +########################## +# Third stage: Extract generated contents from latex2html run +# Initialize with: l2h_InitFromHtml +# open $l2h_html_file for reading +# reads in contents into array indexed by numbers +# return 1, on success -- 0, otherwise +# Extract Html code with: l2h_FromHtml($text) +# replaces in $text all previosuly inserted comments by generated html code +# returns (possibly changed) $text +# Finish with: l2h_FinishFromHtml +# closes $l2h_html_dir/$l2h_name.".$docu_ext" + +sub l2h_InitFromHtml +{ + local($h_line, $h_content, $count, %l2h_img); + + if (! open(L2H_HTML, "<${l2h_html_file}")) + { + print "$ERROR Error l2h: Can't open ${l2h_html_file} for reading\n"; + return 0; + } + print "# l2h: use ${l2h_html_file} as html file\n" if ($T2H_VERBOSE); + + $l2h_html_count = 0; + + while ($h_line = ) + { + if ($h_line =~ /^/) + { + $count = $1; + $h_content = ""; + while ($h_line = ) + { + if ($h_line =~ /^/) + { + chomp $h_content; + chomp $h_content; + $l2h_html_count++; + $h_content = l2h_ToCache($count, $h_content); + $l2h_from_html[$count] = $h_content; + $h_content = ''; + last; + } + $h_content = $h_content.$h_line; + } + if ($hcontent) + { + print "$ERROR Warning l2h: l2h_end $l2h_name $count not found\n" + if ($T2H_VERBOSE); + close(L2H_HTML); + return 0; + } + } + } + print "# l2h: Got $l2h_html_count of $l2h_latex_count html contents\n" + if ($T2H_VERBOSE); + + close(L2H_HTML); + return 1; +} + +sub l2h_FromHtml +{ + local($text) = @_; + local($done, $to_do, $count); + + $to_do = $text; + + while ($to_do =~ /([^\000]*)([^\000]*)/) + { + $to_do = $1; + $count = $2; + $done = $3.$done; + + $done = "".$done + if ($T2H_DEBUG & $DEBUG_L2H); + + $done = &l2h_ExtractFromHtml($count) . $done; + + $done = "".$done + if ($T2H_DEBUG & $DEBUG_L2H); + } + return $to_do.$done; +} + + +sub l2h_ExtractFromHtml +{ + local($count) = @_; + + return $l2h_from_html[$count] if ($l2h_from_html[$count]); + + if ($count >= 0 && $count < $l2h_latex_count) + { + # now we are in trouble + local($l_l2h, $_); + + $l2h_extract_error++; + print "$ERROR l2h: can't extract content $count from html\n" + if ($T2H_VERBOSE); + # try simple (ordinary) substition (without l2h) + $l_l2h = $T2H_L2H; + $T2H_L2H = 0; + $_ = $l2h_to_latex{$count}; + $_ = &substitute_style($_); + &unprotect_texi; + $_ = "" . $_ + if ($T2H_DEBUG & $DEBUG_L2H); + $T2H_L2H = $l_l2h; + return $_; + } + else + { + # now we have been incorrectly called + $l2h_range_error++; + print "$ERROR l2h: Request of $count content which is out of valide range [0,$l2h_latex_count)\n"; + return "" + if ($T2H_DEBUG & $DEBUG_L2H); + return ""; + } +} + +sub l2h_FinishFromHtml +{ + if ($T2H_VERBOSE) + { + if ($l2h_extract_error + $l2h_range_error) + { + print "# l2h: finished from html ($l2h_extract_error extract and $l2h_range_error errors)\n"; + } + else + { + print "# l2h: finished from html (no errors)\n"; + } + } +} + +sub l2h_Finish +{ + l2h_StoreCache(); + if ($T2H_L2H_CLEAN) + { + print "# l2h: removing temporary files generated by l2h extension\n" + if $T2H_VERBOSE; + while (<"$docu_rdir$l2h_name"*>) + { + unlink $_; + } + } + print "# l2h: Finished\n" if $T2H_VERBOSE; + return 1; +} + +############################## +# stuff for l2h caching +# + +# I tried doing this with a dbm data base, but it did not store all +# keys/values. Hence, I did as latex2html does it +sub l2h_InitCache +{ + if (-r "$l2h_cache_file") + { + my $rdo = do "$l2h_cache_file"; + warn("$ERROR l2h Error: could not load $docu_rdir$l2h_cache_file: $@\n") + unless ($rdo); + } +} + +sub l2h_StoreCache +{ + return unless $l2h_latex_count; + + my ($key, $value); + open(FH, ">$l2h_cache_file") || return warn"$ERROR l2h Error: could not open $docu_rdir$l2h_cache_file for writing: $!\n"; + + + while (($key, $value) = each %l2h_cache) + { + # escape stuff + $key =~ s|/|\\/|g; + $key =~ s|\\\\/|\\/|g; + # weird, a \ at the end of the key results in an error + # maybe this also broke the dbm database stuff + $key =~ s|\\$|\\\\|; + $value =~ s/\|/\\\|/g; + $value =~ s/\\\\\|/\\\|/g; + $value =~ s|\\\\|\\\\\\\\|g; + print FH "\n\$l2h_cache_key = q/$key/;\n"; + print FH "\$l2h_cache{\$l2h_cache_key} = q|$value|;\n"; + } + print FH "1;"; + close(FH); +} + +# return cached html, if it exists for text, and if all pictures +# are there, as well +sub l2h_FromCache +{ + my $text = shift; + my $cached = $l2h_cache{$text}; + if ($cached) + { + while ($cached =~ m/SRC="(.*?)"/g) + { + unless (-e "$docu_rdir$1") + { + return undef; + } + } + return $cached; + } + return undef; +} + +# insert generated html into cache, move away images, +# return transformed html +$maximage = 1; +sub l2h_ToCache +{ + my $count = shift; + my $content = shift; + my @images = ($content =~ /SRC="(.*?)"/g); + my ($src, $dest); + + for $src (@images) + { + $dest = $l2h_img{$src}; + unless ($dest) + { + my $ext; + if ($src =~ /.*\.(.*)$/ && $1 ne $docu_ext) + { + $ext = $1; + } + else + { + warn "$ERROR: L2h image $src has invalid extension\n"; + next; + } + while (-e "$docu_rdir${docu_name}_$maximage.$ext") { $maximage++;} + $dest = "${docu_name}_$maximage.$ext"; + system("cp -f $docu_rdir$src $docu_rdir$dest"); + $l2h_img{$src} = $dest; + unlink "$docu_rdir$src" unless ($DEBUG & DEBUG_L2H); + } + $content =~ s/$src/$dest/g; + } + $l2h_cache{$l2h_to_latex[$count]} = $content; + return $content; +} + + +#+++############################################################################ +# # +# Pass 1: read source, handle command, variable, simple substitution # +# # +#---############################################################################ + +@lines = (); # whole document +@toc_lines = (); # table of contents +@stoc_lines = (); # table of contents +$curlevel = 0; # current level in TOC +$node = ''; # current node name +$node_next = ''; # current node next name +$node_prev = ''; # current node prev name +$node_up = ''; # current node up name +$in_table = 0; # am I inside a table +$table_type = ''; # type of table ('', 'f', 'v', 'multi') +@tables = (); # nested table support +$in_bibliography = 0; # am I inside a bibliography +$in_glossary = 0; # am I inside a glossary +$in_top = 0; # am I inside the top node +$has_top = 0; # did I see a top node? +$has_top_command = 0; # did I see @top for automatic pointers? +$in_pre = 0; # am I inside a preformatted section +$in_list = 0; # am I inside a list +$in_html = 0; # am I inside an HTML section +$first_line = 1; # is it the first line +$dont_html = 0; # don't protect HTML on this line +$deferred_ref = ''; # deferred reference for indexes +@html_stack = (); # HTML elements stack +$html_element = ''; # current HTML element +&html_reset; +%macros = (); # macros + +# init l2h +$T2H_L2H = &l2h_Init($docu_name) if ($T2H_L2H); +$T2H_L2H = &l2h_InitToLatex if ($T2H_L2H); + +# build code for simple substitutions +# the maps used (%simple_map and %things_map) MUST be aware of this +# watch out for regexps, / and escaped characters! +$subst_code = ''; +foreach (keys(%simple_map)) { + ($re = $_) =~ s/(\W)/\\$1/g; # protect regexp chars + $subst_code .= "s/\\\@$re/$simple_map{$_}/g;\n"; +} +foreach (keys(%things_map)) { + $subst_code .= "s/\\\@$_\\{\\}/$things_map{$_}/g;\n"; +} +if ($use_acc) { + # accentuated characters + foreach (keys(%accent_map)) { + if ($_ eq "`") { + $subst_code .= "s/$;3"; + } elsif ($_ eq "'") { + $subst_code .= "s/$;4"; + } else { + $subst_code .= "s/\\\@\\$_"; + } + $subst_code .= "([a-z])/&\${1}$accent_map{$_};/gi;\n"; + } +} +eval("sub simple_substitutions { $subst_code }"); + +&init_input; +INPUT_LINE: while ($_ = &next_line) { + # + # remove \input on the first lines only + # + if ($first_line) { + next if /^\\input/; + $first_line = 0; + } + # non-@ substitutions cf. texinfmt.el + # + # parse texinfo tags + # + $tag = ''; + $end_tag = ''; + if (/^\s*\@end\s+(\w+)\b/) { + $end_tag = $1; + } elsif (/^\s*\@(\w+)\b/) { + $tag = $1; + } + # + # handle @html / @end html + # + if ($in_html) { + if ($end_tag eq 'html') { + $in_html = 0; + } else { + $tag2pro{$in_html} .= $_; + } + next; + } elsif ($tag eq 'html') { + $in_html = $PROTECTTAG . ++$html_num; + push(@lines, $in_html); + next; + } + + # + # try to remove inlined comments + # syntax from tex-mode.el comment-start-skip + # + s/((^|[^\@])(\@\@)*)\@c(omment | |\{|$).*/$1/; + +# Sometimes I use @c right at the end of a line ( to suppress the line feed ) +# s/((^|[^\@])(\@\@)*)\@c(omment)?$/$1/; +# s/((^|[^\@])(\@\@)*)\@c(omment)? .*/$1/; +# s/(.*)\@c{.*?}(.*)/$1$2/; +# s/(.*)\@comment{.*?}(.*)/$1$2/; +# s/^(.*)\@c /$1/; +# s/^(.*)\@comment /$1/; + + ############################################################# + # value substitution before macro expansion, so that + # it works in macro arguments + s/\@value{($VARRE)}/$value{$1}/eg; + + ############################################################# + # macro substitution + while (/\@(\w+)/g) + { + if (exists($macros->{$1})) + { + my $before = $`; + my $name = $1; + my $after = $'; + my @args; + my $args; + if ($after =~ /^\s*{(.*?[^\\])}(.*)/) + { + $args = $1; + $after = $2; + } + elsif (@{$macros->{$name}->{Args}} == 1) + { + $args = $after; + $args =~ s/^\s*//; + $args =~ s/\s*$//; + $after = ''; + } + $args =~ s|\\\\|\\|g; + $args =~ s|\\{|{|g; + $args =~ s|\\}|}|g; + if (@{$macros->{$name}->{Args}} > 1) + { + $args =~ s/(^|[^\\]),/$1$;/g ; + $args =~ s|\\,|,|g; + @args = split(/$;\s*/, $args) if (@{$macros->{$name}->{Args}} > 1); + } + else + { + $args =~ s|\\,|,|g; + @args = ($args); + } + my $macrobody = $macros->{$name}->{Body}; + for ($i=0; $i<=$#args; $i++) + { + $macrobody =~ s|\\$macros->{$name}->{Args}->[$i]\\|$args[$i]|g; + } + $macrobody =~ s|\\\\|\\|g; + $_ = $before . $macrobody . $after; + unshift @input_spool, map {$_ = $_."\n"} split(/\n/, $_); + next INPUT_LINE; + } + } # + + + # + # try to skip the line + # + if ($end_tag) { + $in_titlepage = 0 if $end_tag eq 'titlepage'; + next if $to_skip{"end $end_tag"}; + } elsif ($tag) { + $in_titlepage = 1 if $tag eq 'titlepage'; + next if $to_skip{$tag}; + last if $tag eq 'bye'; + } + if ($in_top) { + # parsing the top node + if ($tag eq 'node' || + ($sec2level{$tag} && $tag !~ /unnumbered/ && $tag !~ /heading/)) + { + # no more in top + $in_top = 0; + push(@lines, $TOPEND); + } + } + unless ($in_pre) { + s/``/\"/g; + s/''/\"/g; + s/([\w ])---([\w ])/$1--$2/g; + } + # + # analyze the tag + # + if ($tag) { + # skip lines + &skip_until($tag), next if $tag eq 'ignore'; + &skip_until($tag), next if $tag eq 'ifnothtml'; + if ($tag eq 'ifinfo') + { + &skip_until($tag), next unless $T2H_EXPAND eq 'info'; + } + if ($tag eq 'iftex') + { + &skip_until($tag), next unless $T2H_EXPAND eq 'tex'; + } + if ($tag eq 'tex') + { + # add to latex2html file + if ($T2H_EXPAND eq 'tex' && $T2H_L2H && ! $in_pre) + { + # add space to the end -- tex(i2dvi) does this, as well + push(@lines, &l2h_ToLatex(&string_until($tag) . " ")); + } + else + { + &skip_until($tag); + } + next; + } + if ($tag eq 'titlepage') + { + next; + } + # handle special tables + if ($tag =~ /^(|f|v|multi)table$/) { + $table_type = $1; + $tag = 'table'; + } + # special cases + if ($tag eq 'top' || ($tag eq 'node' && /^\@node\s+top\s*,/i)) { + $in_top = 1; + $has_top = 1; + $has_top_command = 1 if $tag eq 'top'; + @lines = (); # ignore all lines before top (title page garbage) + next; + } elsif ($tag eq 'node') { + if ($in_top) + { + $in_top = 0; + push(@lines, $TOPEND); + } + warn "$ERROR Bad node line: $_" unless $_ =~ /^\@node\s$NODESRE$/o; + # request of "Richard Y. Kim" + s/^\@node\s+//; + $_ = &protect_html($_); # if node contains '&' for instance + ($node, $node_next, $node_prev, $node_up) = split(/,/); + &normalise_node($node); + &normalise_node($node_next); + &normalise_node($node_prev); + &normalise_node($node_up); + $node =~ /\"/ ? + push @lines, &html_debug("\n", __LINE__) : + push @lines, &html_debug("\n", __LINE__); + next; + } elsif ($tag eq 'include') { + if (/^\@include\s+($FILERE)\s*$/o) { + $file = LocateIncludeFile($1); + if ($file && -e $file) { + &open($file); + print "# including $file\n" if $T2H_VERBOSE; + } else { + warn "$ERROR Can't find $1, skipping"; + } + } else { + warn "$ERROR Bad include line: $_"; + } + next; + } elsif ($tag eq 'ifclear') { + if (/^\@ifclear\s+($VARRE)\s*$/o) { + next unless defined($value{$1}); + &skip_until($tag); + } else { + warn "$ERROR Bad ifclear line: $_"; + } + next; + } elsif ($tag eq 'ifset') { + if (/^\@ifset\s+($VARRE)\s*$/o) { + next if defined($value{$1}); + &skip_until($tag); + } else { + warn "$ERROR Bad ifset line: $_"; + } + next; + } elsif ($tag eq 'menu') { + unless ($T2H_SHOW_MENU) { + &skip_until($tag); + next; + } + &html_push_if($tag); + push(@lines, &html_debug('', __LINE__)); + } elsif ($format_map{$tag}) { + $in_pre = 1 if $format_map{$tag} eq 'PRE'; + &html_push_if($format_map{$tag}); + push(@lines, &html_debug('', __LINE__)); + $in_list++ if $format_map{$tag} eq 'UL' || $format_map{$tag} eq 'OL' ; +# push(@lines, &debug("

    \n", __LINE__)) +# if $tag =~ /example/i; + # sunshine@sunshineco.com: 
    bla
    looks better than + # 
    \nbla
    (at least on NeXTstep browser + push(@lines, &debug("<$format_map{$tag}>" . + ($in_pre ? '' : "\n"), __LINE__)); + next; + } + elsif (exists $complex_format_map->{$tag}) + { + my $start = eval $complex_format_map->{$tag}->[0]; + if ($@) + { + print "$ERROR: eval of complex_format_map->{$tag}->[0] $complex_format_map->{$tag}->[0]: $@"; + $start = '
    '
+	  }
+	  $in_pre = 1 if $start =~ /
    \n", __LINE__));
+		    &html_push_if('TABLE');
+		} else {
+		    push(@lines, &debug("
    \n", __LINE__));
+		    &html_push_if('DL');
+		}
+		push(@lines, &html_debug('', __LINE__));
+	    } else {
+		warn "$ERROR Bad table line: $_";
+	    }
+	    next;
+	} 
+	elsif ($tag eq 'synindex' || $tag eq 'syncodeindex') 
+	{
+	  if (/^\@$tag\s+(\w+)\s+(\w+)\s*$/) 
+	  {
+	    my $from = $1;
+	    my $to = $2;
+	    my $prefix_from = IndexName2Prefix($from);
+	    my $prefix_to = IndexName2Prefix($to);
+
+	    warn("$ERROR unknown from index name $from ind syn*index line: $_"), next
+	      unless $prefix_from;
+	    warn("$ERROR unknown to index name $to ind syn*index line: $_"), next
+	      unless $prefix_to;
+
+	    if ($tag eq 'syncodeindex')
+	    {
+	      $index_properties->{$prefix_to}->{'from_code'}->{$prefix_from} = 1;
+	    }
+	    else
+	    {
+	       $index_properties->{$prefix_to}->{'from'}->{$prefix_from} = 1;
+	    }
+	  } 
+	  else 
+	  {
+	    warn "$ERROR Bad syn*index line: $_";
+	  }
+	  next;
+	} 
+	elsif ($tag eq 'defindex' || $tag eq 'defcodeindex') 
+	{
+	  if (/^\@$tag\s+(\w+)\s*$/) 
+	  {
+	    my $name = $1;
+	    $index_properties->{$name}->{name} = $name;
+	    $index_properties->{$name}->{code} = 1 if $tag eq 'defcodeindex';
+	  } 
+	  else 
+	  {
+	    warn "$ERROR Bad defindex line: $_";
+	  }
+	  next;
+	}
+	elsif (/^\@printindex/)
+	{
+	  push (@lines, "$_");
+	  next;
+	}
+	elsif ($tag eq 'sp') {
+	    push(@lines, &debug("
    \n", __LINE__));
+	    next;
+	} elsif ($tag eq 'center') {
+	    push(@lines, &debug("
    \n", __LINE__));
+	    s/\@center//;
+	} elsif ($tag eq 'setref') {
+	    &protect_html; # if setref contains '&' for instance
+	    if (/^\@$tag\s*{($NODERE)}\s*$/) {
+		$setref = $1;
+		$setref =~ s/\s+/ /g; # normalize
+		$setref =~ s/ $//;
+		$node2sec{$setref} = $name;
+		$sec2node{$name} = $setref;
+		$node2href{$setref} = "$docu_doc#$docid";
+	    } else {
+		warn "$ERROR Bad setref line: $_";
+	    }
+	    next;
+	} elsif ($tag eq 'lowersections') {
+	    local ($sec, $level);
+	    while (($sec, $level) = each %sec2level) {
+		$sec2level{$sec} = $level + 1;
+	    }
+	    next;
+	} elsif ($tag eq 'raisesections') {
+	    local ($sec, $level);
+	    while (($sec, $level) = each %sec2level) {
+		$sec2level{$sec} = $level - 1;
+	    }
+	    next;
+	}
+	elsif ($tag eq 'macro' || $tag eq 'rmacro')
+	{
+	  if (/^\@$tag\s*(\w+)\s*(.*)/)
+	  {
+	    my $name = $1;
+	    my @args;
+	    @args = split(/\s*,\s*/ , $1)
+	      if ($2 =~ /^\s*{(.*)}\s*/);
+	    
+	    $macros->{$name}->{Args} = \@args;
+	    $macros->{$name}->{Body} = '';
+	    while (($_ = &next_line) && $_ !~ /\@end $tag/)
+	    {
+	      $macros->{$name}->{Body} .= $_;
+	    }
+	    die "ERROR: No closing '\@end $tag' found for macro definition of '$name'\n"
+	      unless (/\@end $tag/);
+	    chomp $macros->{$name}->{Body};
+	  }
+	  else
+	  {
+	    warn "$ERROR: Bad macro defintion $_"
+	  }
+	  next;
+	}
+	elsif ($tag eq 'unmacro')
+	{
+	  delete $macros->{$1} if (/^\@unmacro\s*(\w+)/);
+	  next;
+	}
+	elsif ($tag eq 'documentlanguage')
+	{
+	  SetDocumentLanguage($1) if (!$T2H_LANG && /documentlanguage\s*(\w+)/);
+	}
+	elsif (defined($def_map{$tag})) {
+	    if ($def_map{$tag}) {
+		s/^\@$tag\s+//;
+		$tag = $def_map{$tag};
+		$_ = "\@$tag $_";
+		$tag =~ s/\s.*//;
+	    }
+	} elsif (defined($user_sub{$tag})) {
+	    s/^\@$tag\s+//;
+	    $sub = $user_sub{$tag};
+	    print "# user $tag = $sub, arg: $_" if $T2H_DEBUG & $DEBUG_USER;
+	    if (defined(&$sub)) {
+		chop($_);
+		&$sub($_);
+	    } else {
+		warn "$ERROR Bad user sub for $tag: $sub\n";
+	    }
+	    next;
+	  } 
+	if (defined($def_map{$tag})) {
+	    s/^\@$tag\s+//;
+	    if ($tag =~ /x$/) {
+		# extra definition line
+		$tag = $`;
+		$is_extra = 1;
+	    } else {
+		$is_extra = 0;
+	    }
+	    while (/\{([^\{\}]*)\}/) {
+		# this is a {} construct
+		($before, $contents, $after) = ($`, $1, $');
+		# protect spaces
+		$contents =~ s/\s+/$;9/g;
+		# restore $_ protecting {}
+		$_ = "$before$;7$contents$;8$after";
+	    }
+	    @args = split(/\s+/, &protect_html($_));
+	    foreach (@args) {
+		s/$;9/ /g;	# unprotect spaces
+		s/$;7/\{/g;	# ... {
+		s/$;8/\}/g;	# ... }
+	    }
+	    $type = shift(@args);
+	    $type =~ s/^\{(.*)\}$/$1/;
+	    print "# def ($tag): {$type} ", join(', ', @args), "\n"
+		if $T2H_DEBUG & $DEBUG_DEF;
+	    $type .= ':'; # it's nicer like this
+	    my $name = shift(@args);
+	    $name =~ s/^\{(.*)\}$/$1/;
+	    if ($is_extra) {
+		$_ = &debug("
    ", __LINE__);
+	    } else {
+		$_ = &debug("
    \n
    ", __LINE__);
+	    }
+	    if ($tag eq 'deffn' || $tag eq 'defvr' || $tag eq 'deftp') {
+		$_ .= "$type $name";
+		$_ .= " @args" if @args;
+	    } elsif ($tag eq 'deftypefn' || $tag eq 'deftypevr'
+		     || $tag eq 'defcv' || $tag eq 'defop') {
+		$ftype = $name;
+		$name = shift(@args);
+		$name =~ s/^\{(.*)\}$/$1/;
+		$_ .= "$type $ftype $name";
+		$_ .= " @args" if @args;
+	    } else {
+		warn "$ERROR Unknown definition type: $tag\n";
+		$_ .= "$type $name";
+		$_ .= " @args" if @args;
+	    }
+ 	    $_ .= &debug("\n
    ", __LINE__);
+	    $name = &unprotect_html($name);
+	    if ($tag eq 'deffn' || $tag eq 'deftypefn') {
+	      EnterIndexEntry('f', $name, $docu_doc, $section, \@lines);
+#		unshift(@input_spool, "\@findex $name\n");
+	    } elsif ($tag eq 'defop') {
+	      EnterIndexEntry('f', "$name on $ftype", $docu_doc, $section, \@lines);
+#		unshift(@input_spool, "\@findex $name on $ftype\n");
+	    } elsif ($tag eq 'defvr' || $tag eq 'deftypevr' || $tag eq 'defcv') {
+	      EnterIndexEntry('v', $name, $docu_doc, $section, \@lines);
+#		unshift(@input_spool, "\@vindex $name\n");
+	    } else {
+	      EnterIndexEntry('t', $name, $docu_doc, $section, \@lines);
+#		unshift(@input_spool, "\@tindex $name\n");
+	    }
+	    $dont_html = 1;
+	}
+    } elsif ($end_tag) {
+	if ($format_map{$end_tag}) {
+	    $in_pre = 0 if $format_map{$end_tag} eq 'PRE';
+	    $in_list-- if $format_map{$end_tag} eq 'UL' || $format_map{$end_tag} eq 'OL' ;
+	    &html_pop_if('P');
+	    &html_pop_if('LI');
+	    &html_pop_if();
+	    push(@lines, &debug("\n", __LINE__));
+	    push(@lines, &html_debug('', __LINE__));
+	}
+	elsif (exists $complex_format_map->{$end_tag})
+	{
+	  my $end = eval $complex_format_map->{$end_tag}->[1];
+	  if ($@)
+	  {
+	    print "$ERROR: eval of complex_format_map->{$end_tag}->[1] $complex_format_map->{$end_tag}->[0]: $@";
+	    $end = '
    '
+	  }
+	  $in_pre = 0 if $end =~ m|
    |; + push(@lines, html_debug($end, __LINE__)); + } elsif ($end_tag =~ /^(|f|v|multi)table$/) { + unless (@tables) { + warn "$ERROR \@end $end_tag without \@*table\n"; + next; + } + &html_pop_if('P'); + ($table_type, $in_table) = split($;, shift(@tables)); + unless ($1 eq $table_type) { + warn "$ERROR \@end $end_tag without matching \@$end_tag\n"; + next; + } + if ($table_type eq "multi") { + push(@lines, "
    \n"); + &html_pop_if('TR'); + } else { + push(@lines, "\n"); + &html_pop_if('DD'); + } + &html_pop_if(); + if (@tables) { + ($table_type, $in_table) = split($;, $tables[0]); + } else { + $in_table = 0; + } + } elsif (defined($def_map{$end_tag})) { + push(@lines, &debug("\n", __LINE__)); + } elsif ($end_tag eq 'menu') { + &html_pop_if(); + push(@lines, $_); # must keep it for pass 2 + } + next; + } + ############################################################# + # anchor insertion + while (/\@anchor\s*\{(.*?)\}/) + { + $_ = $`.$'; + my $anchor = $1; + $anchor = &normalise_node($anchor); + push @lines, &html_debug("\n"); + $node2href{$anchor} = "$docu_doc#$anchor"; + next INPUT_LINE if $_ =~ /^\s*$/; + } + + ############################################################# + # index entry generation, after value substitutions + if (/^\@(\w+?)index\s+/) + { + EnterIndexEntry($1, $', $docu_doc, $section, \@lines); + next; + } + # + # protect texi and HTML things + &protect_texi; + $_ = &protect_html($_) unless $dont_html; + $dont_html = 0; + # substitution (unsupported things) + s/^\@exdent\s+//g; + s/\@noindent\s+//g; + s/\@refill\s+//g; + # other substitutions + &simple_substitutions; + s/\@footnote\{/\@footnote$docu_doc\{/g; # mark footnotes, cf. pass 4 + # + # analyze the tag again + # + if ($tag) { + if (defined($sec2level{$tag}) && $sec2level{$tag} > 0) { + if (/^\@$tag\s+(.+)$/) { + $name = $1; + $name = &normalise_node($name); + $level = $sec2level{$tag}; + # check for index + $first_index_chapter = $name + if ($level == 1 && !$first_index_chapter && + $name =~ /index/i); + if ($in_top && /heading/){ + $T2H_HAS_TOP_HEADING = 1; + $_ = &debug("$name\n", __LINE__); + &html_push_if('body'); + print "# top heading, section $name, level $level\n" + if $T2H_DEBUG & $DEBUG_TOC; + } + else + { + unless (/^\@\w*heading/) + { + unless (/^\@unnumbered/) + { + my $number = &update_sec_num($tag, $level); + $name = $number. ' ' . $name if $T2H_NUMBER_SECTIONS; + $sec2number{$name} = $number; + $number2sec{$number} = $name; + } + if (defined($toplevel)) + { + push @lines, ($level==$toplevel ? $CHAPTEREND : $SECTIONEND); + } + else + { + # first time we see a "section" + unless ($level == 1) + { + warn "$WARN The first section found is not of level 1: $_"; + } + $toplevel = $level; + } + push(@sections, $name); + next_doc() if ($T2H_SPLIT eq 'section' || + $T2H_SPLIT && $level == $toplevel); + } + $sec_num++; + $docid = "SEC$sec_num"; + $tocid = (/^\@\w*heading/ ? undef : "TOC$sec_num"); + # check biblio and glossary + $in_bibliography = ($name =~ /^([A-Z]|\d+)?(\.\d+)*\s*bibliography$/i); + $in_glossary = ($name =~ /^([A-Z]|\d+)?(\.\d+)*\s*glossary$/i); + # check node + if ($node) + { + warn "$ERROR Duplicate node found: $node\n" + if ($node2sec{$node}); + } + else + { + $name .= ' ' while ($node2sec{$name}); + $node = $name; + } + $name .= ' ' while ($sec2node{$name}); + $section = $name; + $node2sec{$node} = $name; + $sec2node{$name} = $node; + $node2href{$node} = "$docu_doc#$docid"; + $node2next{$node} = $node_next; + $node2prev{$node} = $node_prev; + $node2up{$node} = $node_up; + print "# node $node, section $name, level $level\n" + if $T2H_DEBUG & $DEBUG_TOC; + + $node = ''; + $node_next = ''; + $node_prev = ''; + $node_next = ''; + if ($tocid) + { + # update TOC + while ($level > $curlevel) { + $curlevel++; + push(@toc_lines, "
      \n"); + } + while ($level < $curlevel) { + $curlevel--; + push(@toc_lines, "
    \n"); + } + $_ = &t2h_anchor($tocid, "$docu_doc#$docid", $name, 1); + $_ = &substitute_style($_); + push(@stoc_lines, "$_
    \n") if ($level == 1); + if ($T2H_NUMBER_SECTIONS) + { + push(@toc_lines, $_ . "
    \n") + } + else + { + push(@toc_lines, "
  1. " . $_ ."
    2. "); + } + } + else + { + push(@lines, &html_debug("\n", + __LINE__)); + } + # update DOC + push(@lines, &html_debug('', __LINE__)); + &html_reset; + $_ = " $name \n\n"; + $_ = &debug($_, __LINE__); + push(@lines, &html_debug('', __LINE__)); + } + # update DOC + foreach $line (split(/\n+/, $_)) { + push(@lines, "$line\n"); + } + next; + } else { + warn "$ERROR Bad section line: $_"; + } + } else { + # track variables + $value{$1} = Unprotect_texi($2), next if /^\@set\s+($VARRE)\s+(.*)$/o; + delete $value{$1}, next if /^\@clear\s+($VARRE)\s*$/o; + # store things + $value{'_shorttitle'} = Unprotect_texi($1), next if /^\@shorttitle\s+(.*)$/; + $value{'_setfilename'} = Unprotect_texi($1), next if /^\@setfilename\s+(.*)$/; + $value{'_settitle'} = Unprotect_texi($1), next if /^\@settitle\s+(.*)$/; + $value{'_author'} .= Unprotect_texi($1)."\n", next if /^\@author\s+(.*)$/; + $value{'_subtitle'} .= Unprotect_texi($1)."\n", next if /^\@subtitle\s+(.*)$/; + $value{'_title'} .= Unprotect_texi($1)."\n", next if /^\@title\s+(.*)$/; + + # list item + if (/^\s*\@itemx?\s+/) { + $what = $'; + $what =~ s/\s+$//; + if ($in_bibliography && $use_bibliography) { + if ($what =~ /^$BIBRE$/o) { + $id = 'BIB' . ++$bib_num; + $bib2href{$what} = "$docu_doc#$id"; + print "# found bibliography for '$what' id $id\n" + if $T2H_DEBUG & $DEBUG_BIB; + $what = &t2h_anchor($id, '', $what); + } + } elsif ($in_glossary && $T2H_USE_GLOSSARY) { + $id = 'GLOSS' . ++$gloss_num; + $entry = $what; + $entry =~ tr/A-Z/a-z/ unless $entry =~ /^[A-Z\s]+$/; + $gloss2href{$entry} = "$docu_doc#$id"; + print "# found glossary for '$entry' id $id\n" + if $T2H_DEBUG & $DEBUG_GLOSS; + $what = &t2h_anchor($id, '', $what); + } + elsif ($in_table && ($table_type eq 'f' || $table_type eq 'v')) + { + EnterIndexEntry($table_type, $what, $docu_doc, $section, \@lines); + } + &html_pop_if('P'); + if ($html_element eq 'DL' || $html_element eq 'DD') { + if ($things_map{$in_table} && !$what) { + # special case to allow @table @bullet for instance + push(@lines, &debug("
    $things_map{$in_table}\n", __LINE__)); + } else { + push(@lines, &debug("
    \@$in_table\{$what\}\n", __LINE__)); + } + push(@lines, "
    "); + &html_push('DD') unless $html_element eq 'DD'; + if ($table_type) { # add also an index + unshift(@input_spool, "\@${table_type}index $what\n"); + } + } elsif ($html_element eq 'TABLE') { + push(@lines, &debug("$what\n", __LINE__)); + &html_push('TR'); + } elsif ($html_element eq 'TR') { + push(@lines, &debug("\n", __LINE__)); + push(@lines, &debug("$what\n", __LINE__)); + } else { + push(@lines, &debug("
  2. $what\n", __LINE__)); + &html_push('LI') unless $html_element eq 'LI'; + } + push(@lines, &html_debug('', __LINE__)); + if ($deferred_ref) { + push(@lines, &debug("$deferred_ref\n", __LINE__)); + $deferred_ref = ''; + } + next; + } elsif (/^\@tab\s+(.*)$/) { + push(@lines, "$1\n"); + next; + } + } + } + # paragraph separator + if ($_ eq "\n" && ! $in_pre) { + next if $#lines >= 0 && $lines[$#lines] eq "\n"; + if ($html_element eq 'P') { + push (@lines, &debug("

    \n", __LINE__)); + } +# else +# { +# push(@lines, "

    \n"); +# $_ = &debug("

    \n", __LINE__); +# } + elsif ($html_element eq 'body' || $html_element eq 'BLOCKQUOTE' || $html_element eq 'DD' || $html_element eq 'LI') + { + &html_push('P'); + push(@lines, &debug("

    \n", __LINE__)); + } + } + # otherwise + push(@lines, $_) unless $in_titlepage; + push(@lines, &debug("\n", __LINE__)) if ($tag eq 'center'); +} + +# finish TOC +$level = 0; +while ($level < $curlevel) { + $curlevel--; + push(@toc_lines, "\n"); +} + +print "# end of pass 1\n" if $T2H_VERBOSE; + +SetDocumentLanguage('en') unless ($T2H_LANG); +#+++############################################################################ +# # +# Stuff related to Index generation # +# # +#---############################################################################ + +sub EnterIndexEntry +{ + my $prefix = shift; + my $key = shift; + my $docu_doc = shift; + my $section = shift; + my $lines = shift; + local $_; + + warn "$ERROR Undefined index command: $_", next + unless (exists ($index_properties->{$prefix})); + $key =~ s/\s+$//; + $_ = $key; + &protect_texi; + $key = $_; + $_ = &protect_html($_); + my $html_key = substitute_style($_); + my $id; + $key = remove_style($key); + $key = remove_things($key); + $_ = $key; + &unprotect_texi; + $key = $_; + while (exists $index->{$prefix}->{$key}) {$key .= ' '}; + if ($lines->[$#lines] =~ /^$/) + { + $id = $1; + } + else + { + $id = 'IDX' . ++$idx_num; + push(@$lines, &t2h_anchor($id, '', $T2H_INVISIBLE_MARK, !$in_pre)); + } + $index->{$prefix}->{$key}->{html_key} = $html_key; + $index->{$prefix}->{$key}->{section} = $section; + $index->{$prefix}->{$key}->{href} = "$docu_doc#$id"; + print "# found ${prefix}index for '$key' with id $id\n" + if $T2H_DEBUG & $DEBUG_INDEX; +} + +sub IndexName2Prefix +{ + my $name = shift; + my $prefix; + + for $prefix (keys %$index_properties) + { + return $prefix if ($index_properties->{$prefix}->{name} eq $name); + } + return undef; +} + +sub GetIndexEntries +{ + my $normal = shift; + my $code = shift; + my ($entries, $prefix, $key) = ({}); + + for $prefix (keys %$normal) + { + for $key (keys %{$index->{$prefix}}) + { + $entries->{$key} = {%{$index->{$prefix}->{$key}}}; + } + } + + if (defined($code)) + { + for $prefix (keys %$code) + { + unless (exists $normal->{$keys}) + { + for $key (keys %{$index->{$prefix}}) + { + $entries->{$key} = {%{$index->{$prefix}->{$key}}}; + $entries->{$key}->{html_key} = "$entries->{$key}->{html_key}"; + } + } + } + } + return $entries; +} + +sub byAlpha +{ + if ($a =~ /^[A-Za-z]/) + { + if ($b =~ /^[A-Za-z]/) + { + return lc($a) cmp lc($b); + } + else + { + return 1; + } + } + elsif ($b =~ /^[A-Za-z]/) + { + return -1; + } + else + { + return lc($a) cmp lc($b); + } +} + +sub GetIndexPages +{ + my $entries = shift; + my (@Letters, $key); + my ($EntriesByLetter, $Pages, $page) = ({}, [], {}); + my @keys = sort byAlpha keys %$entries; + + for $key (@keys) + { + push @{$EntriesByLetter->{uc(substr($key,0, 1))}} , $entries->{$key}; + } + @Letters = sort byAlpha keys %$EntriesByLetter; + + $T2H_SPLIT_INDEX = 0 unless ($T2H_SPLIT); + + unless ($T2H_SPLIT_INDEX) + { + $page->{First} = $Letters[0]; + $page->{Last} = $Letters[$#Letters]; + $page->{Letters} = \@Letters; + $page->{EntriesByLetter} = $EntriesByLetter; + push @$Pages, $page; + return $Pages; + } + + if ($T2H_SPLIT_INDEX =~ /^\d+$/) + { + my $i = 0; + my ($prev_letter, $letter); + $page->{First} = $Letters[0]; + for $letter (@Letters) + { + if ($i > $T2H_SPLIT_INDEX) + { + $page->{Last} = $prev_letter; + push @$Pages, {%$page}; + $page->{Letters} = []; + $page->{EntriesByLetter} = {}; + $page->{First} = $letter; + $i=0; + } + push @{$page->{Letters}}, $letter; + $page->{EntriesByLetter}->{$letter} = [@{$EntriesByLetter->{$letter}}]; + $i += scalar(@{$EntriesByLetter->{$letter}}); + $prev_letter = $letter; + } + $page->{Last} = $Letters[$#Letters]; + push @$Pages, {%$page}; + } + return $Pages; +} + +sub GetIndexSummary +{ + my $first_page = shift; + my $Pages = shift; + my $name = shift; + my ($page, $letter, $summary, $i, $l1, $l2, $l); + + $i = 0; + $summary = '
    Jump to:   '; + + for $page ($first_page, @$Pages) + { + for $letter (@{$page->{Letters}}) + { + $l = t2h_anchor('', "$page->{href}#${name}_$letter", "$letter", + 0, 'style="text-decoration:none"') . "\n   \n"; + + if ($letter =~ /^[A-Za-z]/) + { + $l2 .= $l; + } + else + { + $l1 .= $l; + } + } + } + $summary .= $l1 . "
    \n" if ($l1); + $summary .= $l2 . '

    '; + return $summary; +} + +sub PrintIndexPage +{ + my $lines = shift; + my $summary = shift; + my $page = shift; + my $name = shift; + + push @$lines, $summary; + + push @$lines , <

    + + + +EOT + + for $letter (@{$page->{Letters}}) + { + push @$lines, "\n"; + for $entry (@{$page->{EntriesByLetter}->{$letter}}) + { + push @$lines, + "\n"; + } + push @$lines, "\n"; + } + push @$lines, "
    Index Entry Section
    $letter
    " . + t2h_anchor('', $entry->{href}, $entry->{html_key}) . + "" . + t2h_anchor('', sec_href($entry->{section}), clean_name($entry->{section})) . + "

    "; + push @$lines, $summary; +} + +sub PrintIndex +{ + my $lines = shift; + my $name = shift; + my $section = shift; + $section = 'Top' unless $section; + my $prefix = IndexName2Prefix($name); + + warn ("$ERROR printindex: bad index name: $name"), return + unless $prefix; + + if ($index_properties->{$prefix}->{code}) + { + $index_properties->{$prefix}->{from_code}->{$prefix} = 1; + } + else + { + $index_properties->{$prefix}->{from}->{$prefix}= 1; + } + + my $Entries = GetIndexEntries($index_properties->{$prefix}->{from}, + $index_properties->{$prefix}->{from_code}); + return unless %$Entries; + + if ($T2H_IDX_SUMMARY) + { + my $key; + open(FHIDX, ">$docu_rdir$docu_name" . "_$name.idx") + || die "Can't open > $docu_rdir$docu_name" . "_$name.idx for writing: $!\n"; + print "# writing $name index summary in $docu_rdir$docu_name" . "_$name.idx...\n" if $T2H_VERBOSE; + + for $key (sort keys %$Entries) + { + print FHIDX "$key\t$Entries->{$key}->{href}\n"; + } + } + + my $Pages = GetIndexPages($Entries); + my $page; + my $first_page = shift @$Pages; + my $sec_name = $section; + # remove section number + $sec_name =~ s/.*? // if $sec_name =~ /^([A-Z]|\d+)\./; + + ($first_page->{href} = sec_href($section)) =~ s/\#.*$//; + # Update tree structure of document + if (@$Pages) + { + my $sec; + my @after; + + while (@sections && $sections[$#sections] ne $section) + { + unshift @after, pop @sections; + } + + for $page (@$Pages) + { + my $node = ($page->{First} ne $page->{Last} ? + "$sec_name: $page->{First} -- $page->{Last}" : + "$sec_name: $page->{First}"); + push @sections, $node; + $node2sec{$node} = $node; + $sec2node{$node} = $node; + $node2up{$node} = $section; + $page->{href} = next_doc(); + $page->{name} = $node; + $node2href{$node} = $page->{href}; + if ($prev_node) + { + $node2next{$prev_node} = $node; + $node2prev{$node} = $prev_node; + } + $prev_node = $node; + } + push @sections, @after; + } + + my $summary = GetIndexSummary($first_page, $Pages, $name); + PrintIndexPage($lines, $summary, $first_page, $name); + for $page (@$Pages) + { + push @$lines, ($T2H_SPLIT eq 'chapter' ? $CHAPTEREND : $SECTIONEND); + push @$lines, "

    $page->{name}

    \n"; + PrintIndexPage($lines, $summary, $page, $name); + } +} + + +#+++############################################################################ +# # +# Pass 2/3: handle style, menu, index, cross-reference # +# # +#---############################################################################ + +@lines2 = (); # whole document (2nd pass) +@lines3 = (); # whole document (3rd pass) +$in_menu = 0; # am I inside a menu + +while (@lines) { + $_ = shift(@lines); + # + # special case (protected sections) + # + if (/^$PROTECTTAG/o) { + push(@lines2, $_); + next; + } + # + # menu + # + if (/^\@menu\b/) + { + $in_menu = 1; + $in_menu_listing = 1; + push(@lines2, &debug("
    \n", __LINE__)); + next; + } + if (/^\@end\s+menu\b/) + { + if ($in_menu_listing) + { + push(@lines2, &debug("
    \n", __LINE__)); + } + else + { + push(@lines2, &debug("\n", __LINE__)); + } + $in_menu = 0; + $in_menu_listing = 0; + next; + } + if ($in_menu) + { + my ($node, $name, $descr); + if (/^\*\s+($NODERE)::/o) + { + $node = $1; + $descr = $'; + } + elsif (/^\*\s+(.+):\s+([^\t,\.\n]+)[\t,\.\n]/) + { + $name = $1; + $node = $2; + $descr = $'; + } + elsif (/^\*/) + { + warn "$ERROR Bad menu line: $_"; + } + else + { + if ($in_menu_listing) + { + $in_menu_listing = 0; + push(@lines2, &debug("\n", __LINE__)); + } + # should be like verbatim -- preseve spaces, etc + s/ /\ /g; + $_ .= "
    \n"; + push(@lines2, $_); + } + if ($node) + { + if (! $in_menu_listing) + { + $in_menu_listing = 1; + push(@lines2, &debug("\n", __LINE__)); + } + # look for continuation + while ($lines[0] =~ /^\s+\w+/) + { + $descr .= shift(@lines); + } + &menu_entry($node, $name, $descr); + } + next; + } + # + # printindex + # + PrintIndex(\@lines2, $2, $1), next + if (/^\@printindex\s+(\w+)/); + # + # simple style substitutions + # + $_ = &substitute_style($_); + # + # xref + # + while (/\@(x|px|info|)ref{([^{}]+)(}?)/) { + # note: Texinfo may accept other characters + ($type, $nodes, $full) = ($1, $2, $3); + ($before, $after) = ($`, $'); + if (! $full && $after) { + warn "$ERROR Bad xref (no ending } on line): $_"; + $_ = "$before$;0${type}ref\{$nodes$after"; + next; # while xref + } + if ($type eq 'x') { + $type = "$T2H_WORDS->{$T2H_LANG}->{'See'} "; + } elsif ($type eq 'px') { + $type = "$T2H_WORDS->{$T2H_LANG}->{'see'} "; + } elsif ($type eq 'info') { + $type = "$T2H_WORDS->{$T2H_LANG}->{'See'} Info"; + } else { + $type = ''; + } + unless ($full) { + $next = shift(@lines); + $next = &substitute_style($next); + chop($nodes); # remove final newline + if ($next =~ /\}/) { # split on 2 lines + $nodes .= " $`"; + $after = $'; + } else { + $nodes .= " $next"; + $next = shift(@lines); + $next = &substitute_style($next); + chop($nodes); + if ($next =~ /\}/) { # split on 3 lines + $nodes .= " $`"; + $after = $'; + } else { + warn "$ERROR Bad xref (no ending }): $_"; + $_ = "$before$;0xref\{$nodes$after"; + unshift(@lines, $next); + next; # while xref + } + } + } + $nodes =~ s/\s+/ /g; # remove useless spaces + @args = split(/\s*,\s*/, $nodes); + $node = $args[0]; # the node is always the first arg + $node = &normalise_node($node); + $sec = $args[2] || $args[1] || $node2sec{$node}; + $href = $node2href{$node}; + if (@args == 5) { # reference to another manual + $sec = $args[2] || $node; + $man = $args[4] || $args[3]; + $_ = "${before}${type}$T2H_WORDS->{$T2H_LANG}->{'section'} `$sec' in \@cite{$man}$after"; + } elsif ($type =~ /Info/) { # inforef + warn "$ERROR Wrong number of arguments: $_" unless @args == 3; + ($nn, $_, $in) = @args; + $_ = "${before}${type} file `$in', node `$nn'$after"; + } elsif ($sec && $href && ! $T2H_SHORT_REF) { + $_ = "${before}${type}"; + $_ .= "$T2H_WORDS->{$T2H_LANG}->{'section'} " if ${type}; + $_ .= &t2h_anchor('', $href, $sec) . $after; + } + elsif ($href) + { + $_ = "${before}${type} " . + &t2h_anchor('', $href, $args[2] || $args[1] || $node) . + $after; + } + else { + warn "$ERROR Undefined node ($node): $_"; + $_ = "$before$;0xref{$nodes}$after"; + } + } + + # replace images + s[\@image\s*{(.+?)}] + { + my @args = split (/\s*,\s*/, $1); + my $base = $args[0]; + my $image = + LocateIncludeFile("$base.png") || + LocateIncludeFile("$base.jpg") || + LocateIncludeFile("$base.gif"); + warn "$ERROR no image file for $base: $_" unless ($image && -e $image); + "\"$base\""; + ($T2H_CENTER_IMAGE ? + "
    \"$base\"
    " : + "\"$base\""); + }eg; + + # + # try to guess bibliography references or glossary terms + # + unless (/^/) { + $done .= $pre . &t2h_anchor('', $href, $what); + } else { + $done .= "$pre$what"; + } + $_ = $post; + } + $_ = $done . $_; + } + if ($T2H_USE_GLOSSARY) { + $done = ''; + while (/\b\w+\b/) { + ($pre, $what, $post) = ($`, $&, $'); + $entry = $what; + $entry =~ tr/A-Z/a-z/ unless $entry =~ /^[A-Z\s]+$/; + $href = $gloss2href{$entry}; + if (defined($href) && $post !~ /^[^<]*<\/A>/) { + $done .= $pre . &t2h_anchor('', $href, $what); + } else { + $done .= "$pre$what"; + } + $_ = $post; + } + $_ = $done . $_; + } + } + # otherwise + push(@lines2, $_); +} +print "# end of pass 2\n" if $T2H_VERBOSE; + +# +# split style substitutions +# +while (@lines2) { + $_ = shift(@lines2); + # + # special case (protected sections) + # + if (/^$PROTECTTAG/o) { + push(@lines3, $_); + next; + } + # + # split style substitutions + # + $old = ''; + while ($old ne $_) { + $old = $_; + if (/\@(\w+)\{/) { + ($before, $style, $after) = ($`, $1, $'); + if (defined($style_map{$style})) { + $_ = $after; + $text = ''; + $after = ''; + $failed = 1; + while (@lines2) { + if (/\}/) { + $text .= $`; + $after = $'; + $failed = 0; + last; + } else { + $text .= $_; + $_ = shift(@lines2); + } + } + if ($failed) { + die "* Bad syntax (\@$style) after: $before\n"; + } else { + $text = &apply_style($style, $text); + $_ = "$before$text$after"; + } + } + } + } + # otherwise + push(@lines3, $_); +} +print "# end of pass 3\n" if $T2H_VERBOSE; + +#+++############################################################################ +# # +# Pass 4: foot notes, final cleanup # +# # +#---############################################################################ + +@foot_lines = (); # footnotes +@doc_lines = (); # final document +$end_of_para = 0; # true if last line is

    + +while (@lines3) { + $_ = shift(@lines3); + # + # special case (protected sections) + # + if (/^$PROTECTTAG/o) { + push(@doc_lines, $_); + $end_of_para = 0; + next; + } + # + # footnotes + # + while (/\@footnote([^\{\s]+)\{/) { + ($before, $d, $after) = ($`, $1, $'); + $_ = $after; + $text = ''; + $after = ''; + $failed = 1; + while (@lines3) { + if (/\}/) { + $text .= $`; + $after = $'; + $failed = 0; + last; + } else { + $text .= $_; + $_ = shift(@lines3); + } + } + if ($failed) { + die "* Bad syntax (\@footnote) after: $before\n"; + } else { + $foot_num++; + $docid = "DOCF$foot_num"; + $footid = "FOOT$foot_num"; + $foot = "($foot_num)"; + push(@foot_lines, "

    " . &t2h_anchor($footid, "$d#$docid", $foot) . "

    \n"); + $text = "

    $text" unless $text =~ /^\s*

    /; + push(@foot_lines, "$text\n"); + $_ = $before . &t2h_anchor($docid, "$docu_foot#$footid", $foot) . $after; + } + } + # + # remove unnecessary

    + # + if (/^\s*

    \s*$/) { + next if $end_of_para++; + } else { + $end_of_para = 0; + } + # otherwise + push(@doc_lines, $_); +} + +print "# end of pass 4\n" if $T2H_VERBOSE; + +#+++############################################################################ +# # +# Pass 5: print things # +# # +#---############################################################################ + +$T2H_L2H = &l2h_FinishToLatex if ($T2H_L2H); +$T2H_L2H = &l2h_ToHtml if ($T2H_L2H); +$T2H_L2H = &l2h_InitFromHtml if ($T2H_L2H); + +# fix node2up, node2prev, node2next, if desired +if ($has_top_command) +{ + for $section (keys %sec2number) + { + $node = $sec2node{$section}; + $node2up{$node} = Sec2UpNode($section) unless $node2up{$node}; + $node2prev{$node} = Sec2PrevNode($section) unless $node2prev{$node}; + $node2next{$node} = Sec2NextNode($section) unless $node2next{$node}; + } +} + +# prepare %T2H_THISDOC +$T2H_THISDOC{fulltitle} = $value{'_title'} || $value{'_settitle'} || "Untitled Document"; +$T2H_THISDOC{title} = $value{'_settitle'} || $T2H_THISDOC{fulltitle}; +$T2H_THISDOC{author} = $value{'_author'}; +$T2H_THISDOC{subtitle} = $value{'_subtitle'}; +$T2H_THISDOC{shorttitle} = $value{'_shorttitle'}; +for $key (keys %T2H_THISDOC) +{ + $_ = &substitute_style($T2H_THISDOC{$key}); + &unprotect_texi; + s/\s*$//; + $T2H_THISDOC{$key} = $_; +} + +# if no sections, then simply print document as is +unless (@sections) +{ + print "# Writing content into $docu_top_file \n" if $T2H_VERBOSE; + open(FILE, "> $docu_top_file") + || die "$ERROR: Can't open $docu_top_file for writing: $!\n"; + + &$T2H_print_page_head(\*FILE); + $T2H_THIS_SECTION = \@doc_lines; + t2h_print_lines(\*FILE); + &$T2H_print_foot_navigation(\*FILE); + &$T2H_print_page_foot(\*FILE); + close(FILE); + goto Finish; +} + +# initialize $T2H_HREF, $T2H_NAME +%T2H_HREF = + ( + 'First' , sec_href($sections[0]), + 'Last', sec_href($sections[$#sections]), + 'About', $docu_about. '#SEC_About', + ); + +# prepare TOC, OVERVIEW, TOP +$T2H_TOC = \@toc_lines; +$T2H_OVERVIEW = \@stoc_lines; +if ($has_top) +{ + while (1) + { + $_ = shift @doc_lines; + last if /$TOPEND/; + push @$T2H_TOP, $_; + } + $T2H_HREF{'Top'} = $docu_top . '#SEC_Top'; +} +else +{ + $T2H_HREF{'Top'} = $T2H_HREF{First}; +} + +$node2href{Top} = $T2H_HREF{Top}; +$T2H_HREF{Contents} = $docu_toc.'#SEC_Contents' if @toc_lines; +$T2H_HREF{Overview} = $docu_stoc.'#SEC_OVERVIEW' if @stoc_lines; + +# settle on index +if ($T2H_INDEX_CHAPTER) +{ + $T2H_HREF{Index} = $node2href{normalise_node($T2H_INDEX_CHAPTER)}; + warn "$ERROR T2H_INDEX_CHAPTER '$T2H_INDEX_CHAPTER' not found\n" + unless $T2H_HREF{Index}; +} +if (! $T2H_HREF{Index} && $first_index_chapter) +{ + $T2H_INDEX_CHAPTER = $first_index_chapter; + $T2H_HREF{Index} = $node2href{$T2H_INDEX_CHAPTER}; +} + +print "# Using '" . clean_name($T2H_INDEX_CHAPTER) . "' as index page\n" + if ($T2H_VERBOSE && $T2H_HREF{Index}); + +%T2H_NAME = + ( + 'First', clean_name($sec2node{$sections[0]}), + 'Last', clean_name($sec2node{$sections[$#sections]}), + 'About', $T2H_WORDS->{$T2H_LANG}->{'About_Title'}, + 'Contents', $T2H_WORDS->{$T2H_LANG}->{'ToC_Title'}, + 'Overview', $T2H_WORDS->{$T2H_LANG}->{'Overview_Title'}, + 'Index' , clean_name($T2H_INDEX_CHAPTER), + 'Top', clean_name($T2H_TOP_HEADING || $T2H_THISDOC{'title'} || $T2H_THISDOC{'shorttitle'}), + ); + +############################################################################# +# print frame and frame toc file +# +if ( $T2H_FRAMES ) +{ + open(FILE, "> $docu_frame_file") + || die "$ERROR: Can't open $docu_frame_file for writing: $!\n"; + print "# Creating frame in $docu_frame_file ...\n" if $T2H_VERBOSE; + &$T2H_print_frame(\*FILE); + close(FILE); + + open(FILE, "> $docu_toc_frame_file") + || die "$ERROR: Can't open $docu_toc_frame_file for writing: $!\n"; + print "# Creating toc frame in $docu_frame_file ...\n" if $T2H_VERBOSE; + &$T2H_print_toc_frame(\*FILE); + close(FILE); +} + + +############################################################################# +# print Top +# +open(FILE, "> $docu_top_file") + || die "$ERROR: Can't open $docu_top_file for writing: $!\n"; +&$T2H_print_page_head(\*FILE) unless ($T2H_SPLIT); + +if ($has_top) +{ + print "# Creating Top in $docu_top_file ...\n" if $T2H_VERBOSE; + $T2H_THIS_SECTION = $T2H_TOP; + $T2H_HREF{This} = $T2H_HREF{Top}; + $T2H_NAME{This} = $T2H_NAME{Top}; + &$T2H_print_Top(\*FILE); +} + +close(FILE) if $T2H_SPLIT; + +############################################################################# +# Print sections +# +$T2H_NODE{Forward} = $sec2node{$sections[0]}; +$T2H_NAME{Forward} = &clean_name($sec2node{$sections[0]}); +$T2H_HREF{Forward} = sec_href($sections[0]); +$T2H_NODE{This} = 'Top'; +$T2H_NAME{This} = $T2H_NAME{Top}; +$T2H_HREF{This} = $T2H_HREF{Top}; +if ($T2H_SPLIT) +{ + print "# writing " . scalar(@sections) . + " sections in $docu_rdir$docu_name"."_[1..$doc_num]" + if $T2H_VERBOSE; + $previous = ($T2H_SPLIT eq 'chapter' ? $CHAPTEREND : $SECTIONEND); + undef $FH; + $doc_num = 0; +} +else +{ + print "# writing " . scalar(@sections) . " sections in $docu_top_file ..." + if $T2H_VERBOSE; + $FH = \*FILE; + $previous = ''; +} + +$counter = 0; +# loop through sections +while ($section = shift(@sections)) +{ + if ($T2H_SPLIT && ($T2H_SPLIT eq 'section' || $previous eq $CHAPTEREND)) + { + if ($FH) + { + #close previous page + &$T2H_print_chapter_footer($FH) if $T2H_SPLIT eq 'chapter'; + &$T2H_print_page_foot($FH); + close($FH); + undef $FH; + } + } + $T2H_NAME{Back} = $T2H_NAME{This}; + $T2H_HREF{Back} = $T2H_HREF{This}; + $T2H_NODE{Back} = $T2H_NODE{This}; + $T2H_NAME{This} = $T2H_NAME{Forward}; + $T2H_HREF{This} = $T2H_HREF{Forward}; + $T2H_NODE{This} = $T2H_NODE{Forward}; + if ($sections[0]) + { + $T2H_NODE{Forward} = $sec2node{$sections[0]}; + $T2H_NAME{Forward} = &clean_name($T2H_NODE{Forward}); + $T2H_HREF{Forward} = sec_href($sections[0]); + } + else + { + undef $T2H_HREF{Forward}, $T2H_NODE{Forward}, $T2H_NAME{Forward}; + } + + $node = $node2up{$T2H_NODE{This}}; + $T2H_HREF{Up} = $node2href{$node}; + if ($T2H_HREF{Up} eq $T2H_HREF{This} || ! $T2H_HREF{Up}) + { + $T2H_NAME{Up} = $T2H_NAME{Top}; + $T2H_HREF{Up} = $T2H_HREF{Top}; + $T2H_NODE{Up} = 'Up'; + } + else + { + $T2H_NAME{Up} = &clean_name($node); + $T2H_NODE{Up} = $node; + } + + $node = $T2H_NODE{This}; + $node = $node2prev{$node}; + $T2H_NAME{Prev} = &clean_name($node); + $T2H_HREF{Prev} = $node2href{$node}; + $T2H_NODE{Prev} = $node; + + $node = $T2H_NODE{This}; + if ($node2up{$node} && $node2up{$node} ne 'Top'&& + ($node2prev{$node} eq $T2H_NODE{Back} || ! $node2prev{$node})) + { + $node = $node2up{$node}; + while ($node && $node ne $node2up{$node} && ! $node2prev{$node}) + { + $node = $node2up{$node}; + } + $node = $node2prev{$node} + unless $node2up{$node} eq 'Top' || ! $node2up{$node}; + } + else + { + $node = $node2prev{$node}; + } + $T2H_NAME{FastBack} = &clean_name($node); + $T2H_HREF{FastBack} = $node2href{$node}; + $T2H_NODE{FastBack} = $node; + + $node = $T2H_NODE{This}; + $node = $node2next{$node}; + $T2H_NAME{Next} = &clean_name($node); + $T2H_HREF{Next} = $node2href{$node}; + $T2H_NODE{Next} = $node; + + $node = $T2H_NODE{This}; + if ($node2up{$node} && $node2up{$node} ne 'Top'&& + ($node2next{$node} eq $T2H_NODE{Forward} || ! $node2next{$node})) + { + $node = $node2up{$node}; + while ($node && $node ne $node2up{$node} && ! $node2next{$node}) + { + $node = $node2up{$node}; + } + } + $node = $node2next{$node}; + $T2H_NAME{FastForward} = &clean_name($node); + $T2H_HREF{FastForward} = $node2href{$node}; + $T2H_NODE{FastForward} = $node; + + if (! defined($FH)) + { + my $file = $T2H_HREF{This}; + $file =~ s/\#.*$//; + open(FILE, "> $docu_rdir$file") || + die "$ERROR: Can't open $docu_rdir$file for writing: $!\n"; + $FH = \*FILE; + &$T2H_print_page_head($FH); + t2h_print_label($FH); + &$T2H_print_chapter_header($FH) if $T2H_SPLIT eq 'chapter'; + } + else + { + t2h_print_label($FH); + } + + $T2H_THIS_SECTION = []; + while (@doc_lines) { + $_ = shift(@doc_lines); + last if ($_ eq $SECTIONEND || $_ eq $CHAPTEREND); + push(@$T2H_THIS_SECTION, $_); + } + $previous = $_; + &$T2H_print_section($FH); + + if ($T2H_VERBOSE) + { + $counter++; + print "." if $counter =~ /00$/; + } +} +if ($T2H_SPLIT) +{ + &$T2H_print_chapter_footer($FH) if $T2H_SPLIT eq 'chapter'; + &$T2H_print_page_foot($FH); + close($FH); +} +print "\n" if $T2H_VERBOSE; + +############################################################################# +# Print ToC, Overview, Footnotes +# +undef $T2H_HREF{Prev}; +undef $T2H_HREF{Next}; +undef $T2H_HREF{Back}; +undef $T2H_HREF{Forward}; +undef $T2H_HREF{Up}; + +if (@foot_lines) +{ + print "# writing Footnotes in $docu_foot_file...\n" if $T2H_VERBOSE; + open (FILE, "> $docu_foot_file") || die "$ERROR: Can't open $docu_foot_file for writing: $!\n" + if $T2H_SPLIT; + $T2H_HREF{This} = $docu_foot; + $T2H_NAME{This} = $T2H_WORDS->{$T2H_LANG}->{'Footnotes_Title'}; + $T2H_THIS_SECTION = \@foot_lines; + &$T2H_print_Footnotes(\*FILE); + close(FILE) if $T2H_SPLIT; +} + +if (@toc_lines) +{ + print "# writing Toc in $docu_toc_file...\n" if $T2H_VERBOSE; + open (FILE, "> $docu_toc_file") || die "$ERROR: Can't open $docu_toc_file for writing: $!\n" + if $T2H_SPLIT; + $T2H_HREF{This} = $T2H_HREF{Contents}; + $T2H_NAME{This} = $T2H_NAME{Contents}; + $T2H_THIS_SECTION = \@toc_lines; + &$T2H_print_Toc(\*FILE); + close(FILE) if $T2H_SPLIT; +} + +if (@stoc_lines) +{ + print "# writing Overview in $docu_stoc_file...\n" if $T2H_VERBOSE; + open (FILE, "> $docu_stoc_file") || die "$ERROR: Can't open $docu_stoc_file for writing: $!\n" + if $T2H_SPLIT; + + $T2H_HREF{This} = $T2H_HREF{Overview}; + $T2H_NAME{This} = $T2H_NAME{Overview}; + $T2H_THIS_SECTION = \@stoc_lines; + unshift @$T2H_THIS_SECTION, "

    \n"; + push @$T2H_THIS_SECTION, "\n
    \n"; + &$T2H_print_Overview(\*FILE); + close(FILE) if $T2H_SPLIT; +} + +if ($about_body = &$T2H_about_body()) +{ + print "# writing About in $docu_about_file...\n" if $T2H_VERBOSE; + open (FILE, "> $docu_about_file") || die "$ERROR: Can't open $docu_about_file for writing: $!\n" + if $T2H_SPLIT; + + $T2H_HREF{This} = $T2H_HREF{About}; + $T2H_NAME{This} = $T2H_NAME{About}; + $T2H_THIS_SECTION = [$about_body]; + &$T2H_print_About(\*FILE); + close(FILE) if $T2H_SPLIT; +} + +unless ($T2H_SPLIT) +{ + &$T2H_print_page_foot(\*FILE); + close (FILE); +} + +Finish: +&l2h_FinishFromHtml if ($T2H_L2H); +&l2h_Finish if($T2H_L2H); +print "# that's all folks\n" if $T2H_VERBOSE; + +exit(0); + +#+++############################################################################ +# # +# Low level functions # +# # +#---############################################################################ + +sub LocateIncludeFile +{ + my $file = shift; + my $dir; + + return $file if (-e $file && -r $file); + foreach $dir (@T2H_INCLUDE_DIRS) + { + return "$dir/$file" if (-e "$dir/$file" && -r "$dir/$file"); + } + return undef; +} + +sub clean_name +{ + local ($_); + $_ = &remove_style($_[0]); + &unprotect_texi; + return $_; +} + +sub update_sec_num { + local($name, $level) = @_; + my $ret; + + $level--; # here we start at 0 + if ($name =~ /^appendix/ || defined(@appendix_sec_num)) { + # appendix style + if (defined(@appendix_sec_num)) { + &incr_sec_num($level, @appendix_sec_num); + } else { + @appendix_sec_num = ('A', 0, 0, 0); + } + $ret = join('.', @appendix_sec_num[0..$level]); + } else { + # normal style + if (defined(@normal_sec_num)) + { + &incr_sec_num($level, @normal_sec_num); + } + else + { + @normal_sec_num = (1, 0, 0, 0); + } + $ret = join('.', @normal_sec_num[0..$level]); + } + + $ret .= "." if $level == 0; + return $ret; +} + +sub incr_sec_num { + local($level, $l); + $level = shift(@_); + $_[$level]++; + foreach $l ($level+1 .. 3) { + $_[$l] = 0; + } +} + +sub Sec2UpNode +{ + my $sec = shift; + my $num = $sec2number{$sec}; + + return '' unless $num; + return 'Top' unless $num =~ /\.\d+/; + $num =~ s/\.[^\.]*$//; + $num = $num . '.' unless $num =~ /\./; + return $sec2node{$number2sec{$num}}; +} + +sub Sec2PrevNode +{ + my $sec = shift; + my $num = $sec2number{$sec}; + my ($i, $post); + + if ($num =~ /(\w+)(\.$|$)/) + { + $num = $`; + $i = $1; + $post = $2; + if ($i eq 'A') + { + $i = $normal_sec_num[0]; + } + elsif ($i ne '1') + { + # unfortunately, -- operator is not magical + $i = chr(ord($i) + 1); + } + else + { + return ''; + } + return $sec2node{$number2sec{$num . $i . $post}} + } + return ''; +} + +sub Sec2NextNode +{ + my $sec = shift; + my $num = $sec2number{$sec}; + my $i; + + if ($num =~ /(\w+)(\.$|$)/) + { + $num = $`; + $i = $1; + $post = $2; + if ($post eq '.' && $i eq $normal_sec_num[0]) + { + $i = 'A'; + } + else + { + $i++; + } + return $sec2node{$number2sec{$num . $i . $post}} + } + return ''; +} + +sub check { + local($_, %seen, %context, $before, $match, $after); + + while (<>) { + if (/\@(\*|\.|\:|\@|\{|\})/) { + $seen{$&}++; + $context{$&} .= "> $_" if $T2H_VERBOSE; + $_ = "$`XX$'"; + redo; + } + if (/\@(\w+)/) { + ($before, $match, $after) = ($`, $&, $'); + if ($before =~ /\b[\w-]+$/ && $after =~ /^[\w-.]*\b/) { # e-mail address + $seen{'e-mail address'}++; + $context{'e-mail address'} .= "> $_" if $T2H_VERBOSE; + } else { + $seen{$match}++; + $context{$match} .= "> $_" if $T2H_VERBOSE; + } + $match =~ s/^\@/X/; + $_ = "$before$match$after"; + redo; + } + } + + foreach (sort(keys(%seen))) { + if ($T2H_VERBOSE) { + print "$_\n"; + print $context{$_}; + } else { + print "$_ ($seen{$_})\n"; + } + } +} + +sub open { + local($name) = @_; + + ++$fh_name; + if (open($fh_name, $name)) { + unshift(@fhs, $fh_name); + } else { + warn "$ERROR Can't read file $name: $!\n"; + } +} + +sub init_input { + @fhs = (); # hold the file handles to read + @input_spool = (); # spooled lines to read + $fh_name = 'FH000'; + &open($docu); +} + +sub next_line { + local($fh, $line); + + if (@input_spool) { + $line = shift(@input_spool); + return($line); + } + while (@fhs) { + $fh = $fhs[0]; + $line = <$fh>; + return($line) if $line; + close($fh); + shift(@fhs); + } + return(undef); +} + +# used in pass 1, use &next_line +sub skip_until { + local($tag) = @_; + local($_); + + while ($_ = &next_line) { + return if /^\@end\s+$tag\s*$/; + } + die "* Failed to find '$tag' after: " . $lines[$#lines]; +} + +# used in pass 1 for l2h use &next_line +sub string_until { + local($tag) = @_; + local($_, $string); + + while ($_ = &next_line) { + return $string if /^\@end\s+$tag\s*$/; +# $_ =~ s/hbox/mbox/g; + $string = $string.$_; + } + die "* Failed to find '$tag' after: " . $lines[$#lines]; +} + +# +# HTML stacking to have a better HTML output +# + +sub html_reset { + @html_stack = ('html'); + $html_element = 'body'; +} + +sub html_push { + local($what) = @_; + push(@html_stack, $html_element); + $html_element = $what; +} + +sub html_push_if { + local($what) = @_; + push(@html_stack, $html_element) + if ($html_element && $html_element ne 'P'); + $html_element = $what; +} + +sub html_pop { + $html_element = pop(@html_stack); +} + +sub html_pop_if { + local($elt); + + if (@_) { + foreach $elt (@_) { + if ($elt eq $html_element) { + $html_element = pop(@html_stack) if @html_stack; + last; + } + } + } else { + $html_element = pop(@html_stack) if @html_stack; + } +} + +sub html_debug { + local($what, $line) = @_; + if ($T2H_DEBUG & $DEBUG_HTML) + { + $what = "\n" unless $what; + return("$what") + } + return($what); +} + +# to debug the output... +sub debug { + local($what, $line) = @_; + return("$what") + if $T2H_DEBUG & $DEBUG_HTML; + return($what); +} + +sub SimpleTexi2Html +{ + local $_ = $_[0]; + &protect_texi; + &protect_html; + $_ = substitute_style($_); + $_[0] = $_; +} + +sub normalise_node { + local $_ = $_[0]; + s/\s+/ /g; + s/ $//; + s/^ //; + &protect_texi; + &protect_html; + $_ = substitute_style($_); + $_[0] = $_; +} + +sub menu_entry +{ + my ($node, $name, $descr) = @_; + my ($href, $entry); + + &normalise_node($node); + $href = $node2href{$node}; + if ($href) + { + $descr =~ s/^\s+//; + $descr =~ s/\s*$//; + $descr = SimpleTexi2Html($descr); + if ($T2H_NUMBER_SECTIONS && !$T2H_NODE_NAME_IN_MENU && $node2sec{$node}) + { + $entry = $node2sec{$node}; + $name = ''; + } + else + { + &normalise_node($name); + $entry = ($name && ($name ne $node || ! $T2H_AVOID_MENU_REDUNDANCY) + ? "$name : $node" : $node); + } + + if ($T2H_AVOID_MENU_REDUNDANCY && $descr) + { + my $clean_entry = $entry; + $clean_entry =~ s/^.*? // if ($clean_entry =~ /^([A-Z]|\d+)\.[\d\.]* /); + $clean_entry =~ s/[^\w]//g; + my $clean_descr = $descr; + $clean_descr =~ s/[^\w]//g; + $descr = '' if ($clean_entry eq $clean_descr) + } + push(@lines2,&debug('    \n", __LINE__)); + } + elsif ($node =~ /^\(.*\)\w+/) + { + push(@lines2,&debug('\n", __LINE__)) + } + else + { + warn "$ERROR Undefined node of menu_entry ($node): $_"; + } +} + +sub do_ctrl { "^$_[0]" } + +sub do_email { + local($addr, $text) = split(/,\s*/, $_[0]); + + $text = $addr unless $text; + &t2h_anchor('', "mailto:$addr", $text); +} + +sub do_sc +{ + # l2h does this much better + return &l2h_ToLatex("{\\sc ".&unprotect_html($_[0])."}") if ($T2H_L2H); + return "\U$_[0]\E"; +} + +sub do_math +{ + return &l2h_ToLatex("\$".&unprotect_html($_[0])."\$") if ($T2H_L2H); + return "".$text.""; +} + +sub do_uref { + local($url, $text, $only_text) = split(/,\s*/, $_[0]); + + $text = $only_text if $only_text; + $text = $url unless $text; + &t2h_anchor('', $url, $text); +} + +sub do_url { &t2h_anchor('', $_[0], $_[0]) } + +sub do_acronym +{ + return '' . $_[0] . ''; +} + +sub do_accent +{ + return "&$_[0]acute;" if $_[1] eq 'H'; + return "$_[0]." if $_[1] eq 'dotaccent'; + return "$_[0]*" if $_[1] eq 'ringaccent'; + return "$_[0]".'[' if $_[1] eq 'tieaccent'; + return "$_[0]".'(' if $_[1] eq 'u'; + return "$_[0]_" if $_[1] eq 'ubaraccent'; + return ".$_[0]" if $_[1] eq 'udotaccent'; + return "$_[0]<" if $_[1] eq 'v'; + return "&$_[0]cedil;" if $_[1] eq ','; + return "$_[0]" if $_[1] eq 'dotless'; + return undef; +} + +sub apply_style { + local($texi_style, $text) = @_; + local($style); + + $style = $style_map{$texi_style}; + if (defined($style)) { # known style + if ($style =~ /^\"/) { # add quotes + $style = $'; + $text = "\`$text\'"; + } + if ($style =~ /^\&/) { # custom + $style = $'; + $text = &$style($text, $texi_style); + } elsif ($style) { # good style + $text = "<$style>$text"; + } else { # no style + } + } else { # unknown style + $text = undef; + } + return($text); +} + +# remove Texinfo styles +sub remove_style { + local($_) = @_; + 1 while(s/\@\w+{([^\{\}]+)}/$1/g); + return($_); +} + +sub remove_things +{ + local ($_) = @_; + s|\@(\w+)\{\}|$1|g; + return $_; +} + +sub substitute_style { + local($_) = @_; + local($changed, $done, $style, $text); + + &simple_substitutions; + $changed = 1; + while ($changed) { + $changed = 0; + $done = ''; + while (/\@(\w+){([^\{\}]+)}/ || /\@(,){([^\{\}]+)}/) { + $text = &apply_style($1, $2); + if ($text) { + $_ = "$`$text$'"; + $changed = 1; + } else { + $done .= "$`\@$1"; + $_ = "{$2}$'"; + } + } + $_ = $done . $_; + } + return($_); +} + +sub t2h_anchor { + local($name, $href, $text, $newline, $extra_attribs) = @_; + local($result); + + $result = " + $what =~ s/\&/\&\#38;/g; + $what =~ s/\/\&\#62;/g; + # restore anything in quotes + # this fixes my problem where I had: + # < IMG SRC="leftarrow.gif" ALT="<--" > but what if I wanted < in my ALT text ?? + # maybe byte stuffing or some other technique should be used. + $what =~ s/\"([^\&]+)\&\#60;(.*)\"/"$1<$2"/g; + $what =~ s/\"([^\&]+)\&\#62;(.*)\"/"$1>$2"/g; + $what =~ s/\"([^\&]+)\&\#38;(.*)\"/"$1&$2"/g; + # but recognize some HTML things + $what =~ s/\&\#60;\/A\&\#62;/<\/A>/g; # + $what =~ s/\&\#60;A ([^\&]+)\&\#62;//g; # + $what =~ s/\&\#60;IMG ([^\&]+)\&\#62;//g; # + return($what); +} + +sub unprotect_texi { + s/$;0/\@/go; + s/$;1/\{/go; + s/$;2/\}/go; + s/$;3/\`/go; + s/$;4/\'/go; +} + +sub Unprotect_texi +{ + local $_ = shift; + &unprotect_texi; + return($_); +} + +sub unprotect_html { + local($what) = @_; + $what =~ s/\&\#38;/\&/g; + $what =~ s/\&\#60;/\/g; + return($what); +} + +sub t2h_print_label +{ + my $fh = shift; + my $href = shift || $T2H_HREF{This}; + $href =~ s/.*#(.*)$/$1/; + print $fh qq{\n}; +} + +############################################################################## + + # These next few lines are legal in both Perl and nroff. + +.00 ; # finish .ig + +'di \" finish diversion--previous line must be blank +.nr nl 0-1 \" fake up transition to first page again +.nr % 0 \" start at page 1 +'; __END__ ############# From here on it's a standard manual page ############ +.so /usr/local/man/man1/texi2html.1 diff --git a/external/gpl3/gdb/dist/readline/doc/version.texi b/external/gpl3/gdb/dist/readline/doc/version.texi new file mode 100644 index 000000000000..99816bf6807e --- /dev/null +++ b/external/gpl3/gdb/dist/readline/doc/version.texi @@ -0,0 +1,10 @@ +@ignore +Copyright (C) 1988-2005 Free Software Foundation, Inc. +@end ignore + +@set EDITION 5.1-beta1 +@set VERSION 5.1-beta1 +@set UPDATED 11 November 2005 +@set UPDATED-MONTH November 2005 + +@set LASTCHANGE Fri Nov 11 19:50:51 EST 2005 diff --git a/external/gpl3/gdb/dist/readline/emacs_keymap.c b/external/gpl3/gdb/dist/readline/emacs_keymap.c new file mode 100644 index 000000000000..c7399534fdb4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/emacs_keymap.c @@ -0,0 +1,879 @@ +/* emacs_keymap.c -- the keymap for emacs_mode in readline (). */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (BUFSIZ) +#include +#endif /* !BUFSIZ */ + +#include "readline.h" + +/* An array of function pointers, one for each possible key. + If the type byte is ISKMAP, then the pointer is the address of + a keymap. */ + +KEYMAP_ENTRY_ARRAY emacs_standard_keymap = { + + /* Control keys. */ + { ISFUNC, rl_set_mark }, /* Control-@ */ + { ISFUNC, rl_beg_of_line }, /* Control-a */ + { ISFUNC, rl_backward_char }, /* Control-b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-c */ + { ISFUNC, rl_delete }, /* Control-d */ + { ISFUNC, rl_end_of_line }, /* Control-e */ + { ISFUNC, rl_forward_char }, /* Control-f */ + { ISFUNC, rl_abort }, /* Control-g */ + { ISFUNC, rl_rubout }, /* Control-h */ + { ISFUNC, rl_complete }, /* Control-i */ + { ISFUNC, rl_newline }, /* Control-j */ + { ISFUNC, rl_kill_line }, /* Control-k */ + { ISFUNC, rl_clear_screen }, /* Control-l */ + { ISFUNC, rl_newline }, /* Control-m */ + { ISFUNC, rl_get_next_history }, /* Control-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-o */ + { ISFUNC, rl_get_previous_history }, /* Control-p */ + { ISFUNC, rl_quoted_insert }, /* Control-q */ + { ISFUNC, rl_reverse_search_history }, /* Control-r */ + { ISFUNC, rl_forward_search_history }, /* Control-s */ + { ISFUNC, rl_transpose_chars }, /* Control-t */ + { ISFUNC, rl_unix_line_discard }, /* Control-u */ + { ISFUNC, rl_quoted_insert }, /* Control-v */ + { ISFUNC, rl_unix_word_rubout }, /* Control-w */ + { ISKMAP, (rl_command_func_t *)emacs_ctlx_keymap }, /* Control-x */ + { ISFUNC, rl_yank }, /* Control-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-z */ + { ISKMAP, (rl_command_func_t *)emacs_meta_keymap }, /* Control-[ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-\ */ + { ISFUNC, rl_char_search }, /* Control-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-^ */ + { ISFUNC, rl_undo_command }, /* Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, rl_insert }, /* SPACE */ + { ISFUNC, rl_insert }, /* ! */ + { ISFUNC, rl_insert }, /* " */ + { ISFUNC, rl_insert }, /* # */ + { ISFUNC, rl_insert }, /* $ */ + { ISFUNC, rl_insert }, /* % */ + { ISFUNC, rl_insert }, /* & */ + { ISFUNC, rl_insert }, /* ' */ + { ISFUNC, rl_insert }, /* ( */ + { ISFUNC, rl_insert }, /* ) */ + { ISFUNC, rl_insert }, /* * */ + { ISFUNC, rl_insert }, /* + */ + { ISFUNC, rl_insert }, /* , */ + { ISFUNC, rl_insert }, /* - */ + { ISFUNC, rl_insert }, /* . */ + { ISFUNC, rl_insert }, /* / */ + + /* Regular digits. */ + { ISFUNC, rl_insert }, /* 0 */ + { ISFUNC, rl_insert }, /* 1 */ + { ISFUNC, rl_insert }, /* 2 */ + { ISFUNC, rl_insert }, /* 3 */ + { ISFUNC, rl_insert }, /* 4 */ + { ISFUNC, rl_insert }, /* 5 */ + { ISFUNC, rl_insert }, /* 6 */ + { ISFUNC, rl_insert }, /* 7 */ + { ISFUNC, rl_insert }, /* 8 */ + { ISFUNC, rl_insert }, /* 9 */ + + /* A little more punctuation. */ + { ISFUNC, rl_insert }, /* : */ + { ISFUNC, rl_insert }, /* ; */ + { ISFUNC, rl_insert }, /* < */ + { ISFUNC, rl_insert }, /* = */ + { ISFUNC, rl_insert }, /* > */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* @ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_insert }, /* A */ + { ISFUNC, rl_insert }, /* B */ + { ISFUNC, rl_insert }, /* C */ + { ISFUNC, rl_insert }, /* D */ + { ISFUNC, rl_insert }, /* E */ + { ISFUNC, rl_insert }, /* F */ + { ISFUNC, rl_insert }, /* G */ + { ISFUNC, rl_insert }, /* H */ + { ISFUNC, rl_insert }, /* I */ + { ISFUNC, rl_insert }, /* J */ + { ISFUNC, rl_insert }, /* K */ + { ISFUNC, rl_insert }, /* L */ + { ISFUNC, rl_insert }, /* M */ + { ISFUNC, rl_insert }, /* N */ + { ISFUNC, rl_insert }, /* O */ + { ISFUNC, rl_insert }, /* P */ + { ISFUNC, rl_insert }, /* Q */ + { ISFUNC, rl_insert }, /* R */ + { ISFUNC, rl_insert }, /* S */ + { ISFUNC, rl_insert }, /* T */ + { ISFUNC, rl_insert }, /* U */ + { ISFUNC, rl_insert }, /* V */ + { ISFUNC, rl_insert }, /* W */ + { ISFUNC, rl_insert }, /* X */ + { ISFUNC, rl_insert }, /* Y */ + { ISFUNC, rl_insert }, /* Z */ + + /* Some more punctuation. */ + { ISFUNC, rl_insert }, /* [ */ + { ISFUNC, rl_insert }, /* \ */ + { ISFUNC, rl_insert }, /* ] */ + { ISFUNC, rl_insert }, /* ^ */ + { ISFUNC, rl_insert }, /* _ */ + { ISFUNC, rl_insert }, /* ` */ + + /* Lowercase alphabet. */ + { ISFUNC, rl_insert }, /* a */ + { ISFUNC, rl_insert }, /* b */ + { ISFUNC, rl_insert }, /* c */ + { ISFUNC, rl_insert }, /* d */ + { ISFUNC, rl_insert }, /* e */ + { ISFUNC, rl_insert }, /* f */ + { ISFUNC, rl_insert }, /* g */ + { ISFUNC, rl_insert }, /* h */ + { ISFUNC, rl_insert }, /* i */ + { ISFUNC, rl_insert }, /* j */ + { ISFUNC, rl_insert }, /* k */ + { ISFUNC, rl_insert }, /* l */ + { ISFUNC, rl_insert }, /* m */ + { ISFUNC, rl_insert }, /* n */ + { ISFUNC, rl_insert }, /* o */ + { ISFUNC, rl_insert }, /* p */ + { ISFUNC, rl_insert }, /* q */ + { ISFUNC, rl_insert }, /* r */ + { ISFUNC, rl_insert }, /* s */ + { ISFUNC, rl_insert }, /* t */ + { ISFUNC, rl_insert }, /* u */ + { ISFUNC, rl_insert }, /* v */ + { ISFUNC, rl_insert }, /* w */ + { ISFUNC, rl_insert }, /* x */ + { ISFUNC, rl_insert }, /* y */ + { ISFUNC, rl_insert }, /* z */ + + /* Final punctuation. */ + { ISFUNC, rl_insert }, /* { */ + { ISFUNC, rl_insert }, /* | */ + { ISFUNC, rl_insert }, /* } */ + { ISFUNC, rl_insert }, /* ~ */ + { ISFUNC, rl_rubout }, /* RUBOUT */ + +#if KEYMAP_SIZE > 128 + /* Pure 8-bit characters (128 - 159). + These might be used in some + character sets. */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + + /* ISO Latin-1 characters (160 - 255) */ + { ISFUNC, rl_insert }, /* No-break space */ + { ISFUNC, rl_insert }, /* Inverted exclamation mark */ + { ISFUNC, rl_insert }, /* Cent sign */ + { ISFUNC, rl_insert }, /* Pound sign */ + { ISFUNC, rl_insert }, /* Currency sign */ + { ISFUNC, rl_insert }, /* Yen sign */ + { ISFUNC, rl_insert }, /* Broken bar */ + { ISFUNC, rl_insert }, /* Section sign */ + { ISFUNC, rl_insert }, /* Diaeresis */ + { ISFUNC, rl_insert }, /* Copyright sign */ + { ISFUNC, rl_insert }, /* Feminine ordinal indicator */ + { ISFUNC, rl_insert }, /* Left pointing double angle quotation mark */ + { ISFUNC, rl_insert }, /* Not sign */ + { ISFUNC, rl_insert }, /* Soft hyphen */ + { ISFUNC, rl_insert }, /* Registered sign */ + { ISFUNC, rl_insert }, /* Macron */ + { ISFUNC, rl_insert }, /* Degree sign */ + { ISFUNC, rl_insert }, /* Plus-minus sign */ + { ISFUNC, rl_insert }, /* Superscript two */ + { ISFUNC, rl_insert }, /* Superscript three */ + { ISFUNC, rl_insert }, /* Acute accent */ + { ISFUNC, rl_insert }, /* Micro sign */ + { ISFUNC, rl_insert }, /* Pilcrow sign */ + { ISFUNC, rl_insert }, /* Middle dot */ + { ISFUNC, rl_insert }, /* Cedilla */ + { ISFUNC, rl_insert }, /* Superscript one */ + { ISFUNC, rl_insert }, /* Masculine ordinal indicator */ + { ISFUNC, rl_insert }, /* Right pointing double angle quotation mark */ + { ISFUNC, rl_insert }, /* Vulgar fraction one quarter */ + { ISFUNC, rl_insert }, /* Vulgar fraction one half */ + { ISFUNC, rl_insert }, /* Vulgar fraction three quarters */ + { ISFUNC, rl_insert }, /* Inverted questionk mark */ + { ISFUNC, rl_insert }, /* Latin capital letter a with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter a with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter a with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter a with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter a with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter a with ring above */ + { ISFUNC, rl_insert }, /* Latin capital letter ae */ + { ISFUNC, rl_insert }, /* Latin capital letter c with cedilla */ + { ISFUNC, rl_insert }, /* Latin capital letter e with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter e with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter e with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter e with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter i with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter i with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter i with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter i with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter eth (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin capital letter n with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter o with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter o with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter o with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter o with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter o with diaeresis */ + { ISFUNC, rl_insert }, /* Multiplication sign */ + { ISFUNC, rl_insert }, /* Latin capital letter o with stroke */ + { ISFUNC, rl_insert }, /* Latin capital letter u with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter u with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter u with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter u with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter Y with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter thorn (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin small letter sharp s (German) */ +#ifndef __MINGW32__ + { ISFUNC, rl_insert }, /* Latin small letter a with grave */ +#else + /* Temporary - this is a bug in readline 5.1 that should be fixed in + readline 5.2. */ + { ISFUNC, 0 }, /* Must leave this unbound for the arrow keys to work. */ +#endif + { ISFUNC, rl_insert }, /* Latin small letter a with acute */ + { ISFUNC, rl_insert }, /* Latin small letter a with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter a with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter a with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter a with ring above */ + { ISFUNC, rl_insert }, /* Latin small letter ae */ + { ISFUNC, rl_insert }, /* Latin small letter c with cedilla */ + { ISFUNC, rl_insert }, /* Latin small letter e with grave */ + { ISFUNC, rl_insert }, /* Latin small letter e with acute */ + { ISFUNC, rl_insert }, /* Latin small letter e with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter e with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter i with grave */ + { ISFUNC, rl_insert }, /* Latin small letter i with acute */ + { ISFUNC, rl_insert }, /* Latin small letter i with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter i with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter eth (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin small letter n with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter o with grave */ + { ISFUNC, rl_insert }, /* Latin small letter o with acute */ + { ISFUNC, rl_insert }, /* Latin small letter o with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter o with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter o with diaeresis */ + { ISFUNC, rl_insert }, /* Division sign */ + { ISFUNC, rl_insert }, /* Latin small letter o with stroke */ + { ISFUNC, rl_insert }, /* Latin small letter u with grave */ + { ISFUNC, rl_insert }, /* Latin small letter u with acute */ + { ISFUNC, rl_insert }, /* Latin small letter u with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter u with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter y with acute */ + { ISFUNC, rl_insert }, /* Latin small letter thorn (Icelandic) */ + { ISFUNC, rl_insert } /* Latin small letter y with diaeresis */ +#endif /* KEYMAP_SIZE > 128 */ +}; + +KEYMAP_ENTRY_ARRAY emacs_meta_keymap = { + + /* Meta keys. Just like above, but the high bit is set. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-@ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-c */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-d */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-f */ + { ISFUNC, rl_abort }, /* Meta-Control-g */ + { ISFUNC, rl_backward_kill_word }, /* Meta-Control-h */ + { ISFUNC, rl_tab_insert }, /* Meta-Control-i */ + { ISFUNC, rl_vi_editing_mode }, /* Meta-Control-j */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-k */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-l */ + { ISFUNC, rl_vi_editing_mode }, /* Meta-Control-m */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-o */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-q */ + { ISFUNC, rl_revert_line }, /* Meta-Control-r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-s */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-t */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-x */ + { ISFUNC, rl_yank_nth_arg }, /* Meta-Control-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-z */ + + { ISFUNC, rl_complete }, /* Meta-Control-[ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-\ */ + { ISFUNC, rl_backward_char_search }, /* Meta-Control-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-^ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, rl_set_mark }, /* Meta-SPACE */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-! */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-" */ + { ISFUNC, rl_insert_comment }, /* Meta-# */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-$ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-% */ + { ISFUNC, rl_tilde_expand }, /* Meta-& */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-' */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-( */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-) */ + { ISFUNC, rl_insert_completions }, /* Meta-* */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-+ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-, */ + { ISFUNC, rl_digit_argument }, /* Meta-- */ + { ISFUNC, rl_yank_last_arg}, /* Meta-. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-/ */ + + /* Regular digits. */ + { ISFUNC, rl_digit_argument }, /* Meta-0 */ + { ISFUNC, rl_digit_argument }, /* Meta-1 */ + { ISFUNC, rl_digit_argument }, /* Meta-2 */ + { ISFUNC, rl_digit_argument }, /* Meta-3 */ + { ISFUNC, rl_digit_argument }, /* Meta-4 */ + { ISFUNC, rl_digit_argument }, /* Meta-5 */ + { ISFUNC, rl_digit_argument }, /* Meta-6 */ + { ISFUNC, rl_digit_argument }, /* Meta-7 */ + { ISFUNC, rl_digit_argument }, /* Meta-8 */ + { ISFUNC, rl_digit_argument }, /* Meta-9 */ + + /* A little more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-: */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-; */ + { ISFUNC, rl_beginning_of_history }, /* Meta-< */ + { ISFUNC, rl_possible_completions }, /* Meta-= */ + { ISFUNC, rl_end_of_history }, /* Meta-> */ + { ISFUNC, rl_possible_completions }, /* Meta-? */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-@ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-A */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-B */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-C */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-D */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-E */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-F */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-G */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-H */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-I */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-J */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-K */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-L */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-M */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-N */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-O */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-P */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-Q */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-R */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-S */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-T */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-U */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-V */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-W */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-X */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-Y */ + { ISFUNC, rl_do_lowercase_version }, /* Meta-Z */ + + /* Some more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-[ */ /* was rl_arrow_keys */ + { ISFUNC, rl_delete_horizontal_space }, /* Meta-\ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-^ */ + { ISFUNC, rl_yank_last_arg }, /* Meta-_ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-` */ + + /* Lowercase alphabet. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-a */ + { ISFUNC, rl_backward_word }, /* Meta-b */ + { ISFUNC, rl_capitalize_word }, /* Meta-c */ + { ISFUNC, rl_kill_word }, /* Meta-d */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-e */ + { ISFUNC, rl_forward_word }, /* Meta-f */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-g */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-h */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-i */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-j */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-k */ + { ISFUNC, rl_downcase_word }, /* Meta-l */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-m */ + { ISFUNC, rl_noninc_forward_search }, /* Meta-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-o */ /* was rl_arrow_keys */ + { ISFUNC, rl_noninc_reverse_search }, /* Meta-p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-q */ + { ISFUNC, rl_revert_line }, /* Meta-r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-s */ + { ISFUNC, rl_transpose_words }, /* Meta-t */ + { ISFUNC, rl_upcase_word }, /* Meta-u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-x */ + { ISFUNC, rl_yank_pop }, /* Meta-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-z */ + + /* Final punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-{ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-| */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Meta-} */ + { ISFUNC, rl_tilde_expand }, /* Meta-~ */ + { ISFUNC, rl_backward_kill_word }, /* Meta-rubout */ + +#if KEYMAP_SIZE > 128 + /* Undefined keys. */ + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 } +#endif /* KEYMAP_SIZE > 128 */ +}; + +KEYMAP_ENTRY_ARRAY emacs_ctlx_keymap = { + + /* Control keys. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-@ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-c */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-d */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-f */ + { ISFUNC, rl_abort }, /* Control-g */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-h */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-i */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-j */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-k */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-l */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-m */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-o */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-q */ + { ISFUNC, rl_re_read_init_file }, /* Control-r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-s */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-t */ + { ISFUNC, rl_undo_command }, /* Control-u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-w */ + { ISFUNC, rl_exchange_point_and_mark }, /* Control-x */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-z */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-[ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-\ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-^ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* SPACE */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ! */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* " */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* # */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* $ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* % */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* & */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ' */ + { ISFUNC, rl_start_kbd_macro }, /* ( */ + { ISFUNC, rl_end_kbd_macro }, /* ) */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* * */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* + */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* , */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* - */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* . */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* / */ + + /* Regular digits. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 0 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 1 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 2 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 3 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 4 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 5 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 6 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 7 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 8 */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* 9 */ + + /* A little more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* : */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ; */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* < */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* = */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* > */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ? */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* @ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_do_lowercase_version }, /* A */ + { ISFUNC, rl_do_lowercase_version }, /* B */ + { ISFUNC, rl_do_lowercase_version }, /* C */ + { ISFUNC, rl_do_lowercase_version }, /* D */ + { ISFUNC, rl_do_lowercase_version }, /* E */ + { ISFUNC, rl_do_lowercase_version }, /* F */ + { ISFUNC, rl_do_lowercase_version }, /* G */ + { ISFUNC, rl_do_lowercase_version }, /* H */ + { ISFUNC, rl_do_lowercase_version }, /* I */ + { ISFUNC, rl_do_lowercase_version }, /* J */ + { ISFUNC, rl_do_lowercase_version }, /* K */ + { ISFUNC, rl_do_lowercase_version }, /* L */ + { ISFUNC, rl_do_lowercase_version }, /* M */ + { ISFUNC, rl_do_lowercase_version }, /* N */ + { ISFUNC, rl_do_lowercase_version }, /* O */ + { ISFUNC, rl_do_lowercase_version }, /* P */ + { ISFUNC, rl_do_lowercase_version }, /* Q */ + { ISFUNC, rl_do_lowercase_version }, /* R */ + { ISFUNC, rl_do_lowercase_version }, /* S */ + { ISFUNC, rl_do_lowercase_version }, /* T */ + { ISFUNC, rl_do_lowercase_version }, /* U */ + { ISFUNC, rl_do_lowercase_version }, /* V */ + { ISFUNC, rl_do_lowercase_version }, /* W */ + { ISFUNC, rl_do_lowercase_version }, /* X */ + { ISFUNC, rl_do_lowercase_version }, /* Y */ + { ISFUNC, rl_do_lowercase_version }, /* Z */ + + /* Some more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* [ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* \ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ^ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* _ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ` */ + + /* Lowercase alphabet. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* c */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* d */ + { ISFUNC, rl_call_last_kbd_macro }, /* e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* f */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* g */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* h */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* i */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* j */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* k */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* l */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* m */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* o */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* q */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* s */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* t */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* x */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* z */ + + /* Final punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* { */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* | */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* } */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ~ */ + { ISFUNC, rl_backward_kill_line }, /* RUBOUT */ + +#if KEYMAP_SIZE > 128 + /* Undefined keys. */ + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 } +#endif /* KEYMAP_SIZE > 128 */ +}; diff --git a/external/gpl3/gdb/dist/readline/examples/ChangeLog.gdb b/external/gpl3/gdb/dist/readline/examples/ChangeLog.gdb new file mode 100644 index 000000000000..48966545f7c3 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/ChangeLog.gdb @@ -0,0 +1,14 @@ +2006-04-24 Daniel Jacobowitz + + Imported readline 5.1, and upstream patches 001-004. + +2002-02-24 Elena Zannoni + + * ChangeLog.gdb: Rename from ChangeLog.Cygnus. + +2000-07-09 Elena Zannoni + + * Import of readline 4.1. + + New files: excallback.c, rlfe.c. + diff --git a/external/gpl3/gdb/dist/readline/examples/Inputrc b/external/gpl3/gdb/dist/readline/examples/Inputrc new file mode 100644 index 000000000000..d7fdb42efaae --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/Inputrc @@ -0,0 +1,81 @@ +# My ~/.inputrc file is in -*- text -*- for easy editing with Emacs. +# +# Notice the various bindings which are conditionalized depending +# on which program is running, or what terminal is active. +# + +# Copyright (C) 1989-2002 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +# In all programs, all terminals, make sure this is bound. +"\C-x\C-r": re-read-init-file + +# Hp terminals (and some others) have ugly default behaviour for C-h. +"\C-h": backward-delete-char +"\e\C-h": backward-kill-word +"\C-xd": dump-functions + +# In xterm windows, make the arrow keys do the right thing. +$if TERM=xterm +"\e[A": previous-history +"\e[B": next-history +"\e[C": forward-char +"\e[D": backward-char + +# alternate arrow key prefix +"\eOA": previous-history +"\eOB": next-history +"\eOC": forward-char +"\eOD": backward-char + +# Under Xterm in Bash, we bind local Function keys to do something useful. +$if Bash +"\e[11~": "Function Key 1" +"\e[12~": "Function Key 2" +"\e[13~": "Function Key 3" +"\e[14~": "Function Key 4" +"\e[15~": "Function Key 5" + +# I know the following escape sequence numbers are 1 greater than +# the function key. Don't ask me why, I didn't design the xterm terminal. +"\e[17~": "Function Key 6" +"\e[18~": "Function Key 7" +"\e[19~": "Function Key 8" +"\e[20~": "Function Key 9" +"\e[21~": "Function Key 10" +$endif +$endif + +# For Bash, all terminals, add some Bash specific hacks. +$if Bash +"\C-xv": show-bash-version +"\C-x\C-e": shell-expand-line + +# Here is one for editing my path. +"\C-xp": "$PATH\C-x\C-e\C-e\"\C-aPATH=\":\C-b" + +# Make C-x r read my mail in emacs. +# "\C-xr": "emacs -f rmail\C-j" +$endif + +# For FTP, different hacks: +$if Ftp +"\C-xg": "get \M-?" +"\C-xt": "put \M-?" +"\M-.": yank-last-arg +$endif + +" ": self-insert diff --git a/external/gpl3/gdb/dist/readline/examples/Makefile.in b/external/gpl3/gdb/dist/readline/examples/Makefile.in new file mode 100644 index 000000000000..e27bbc0cf6a0 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/Makefile.in @@ -0,0 +1,102 @@ +# +# This is the Makefile for the readline examples subdirectory. +# +# Copyright (C) 1994 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. +RL_LIBRARY_VERSION = @LIBVERSION@ + +SHELL = @MAKE_SHELL@ +RM = rm -f + +srcdir = @srcdir@ +VPATH = .:@srcdir@ +top_srcdir = @top_srcdir@ +BUILD_DIR = . + +# Support an alternate destination root directory for package building +DESTDIR = + +DEFS = @DEFS@ +CC = @CC@ +CFLAGS = @CFLAGS@ +LOCAL_CFLAGS = @LOCAL_CFLAGS@ -DREADLINE_LIBRARY -DRL_LIBRARY_VERSION='"$(RL_LIBRARY_VERSION)"' +CPPFLAGS = @CPPFLAGS@ + +INCLUDES = -I$(srcdir) -I$(top_srcdir) -I.. + +CCFLAGS = $(DEFS) $(LOCAL_CFLAGS) $(CPPFLAGS) $(INCLUDES) $(CFLAGS) +LDFLAGS = -g -L.. @LDFLAGS@ + +PURIFY = @PURIFY@ + +READLINE_LIB = ../libreadline.a +HISTORY_LIB = ../libhistory.a + +TERMCAP_LIB = @TERMCAP_LIB@ + +.c.o: + ${RM} $@ + $(CC) $(CCFLAGS) -c $< + +EXECUTABLES = fileman rltest rl rlcat rlversion histexamp +OBJECTS = fileman.o rltest.o rl.o rlcat.o rlversion.o histexamp.o + +all: $(EXECUTABLES) +everything: all + +rl: rl.o $(READLINE_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ rl.o $(READLINE_LIB) $(TERMCAP_LIB) + +rlcat: rlcat.o $(READLINE_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ rlcat.o $(READLINE_LIB) $(TERMCAP_LIB) + +fileman: fileman.o $(READLINE_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ fileman.o $(READLINE_LIB) $(TERMCAP_LIB) + +rltest: rltest.o $(READLINE_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ rltest.o $(READLINE_LIB) $(TERMCAP_LIB) + +rlptytest: rlptytest.o $(READLINE_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ rlptytest.o $(READLINE_LIB) $(TERMCAP_LIB) + +rlversion: rlversion.o $(READLINE_LIB) + $(CC) $(LDFLAGS) -o $@ rlversion.o $(READLINE_LIB) $(TERMCAP_LIB) + +histexamp: histexamp.o $(HISTORY_LIB) + $(PURIFY) $(CC) $(LDFLAGS) -o $@ histexamp.o -lhistory $(TERMCAP_LIB) + +clean mostlyclean: + $(RM) $(OBJECTS) + $(RM) $(EXECUTABLES) *.exe + +distclean maintainer-clean: clean + $(RM) Makefile + +fileman.o: fileman.c +rltest.o: rltest.c +rl.o: rl.c +rlversion.o: rlversion.c +histexamp.o: histexamp.c +rlcat.o: rlcat.c +rlptytest.o: rlptytest.c + +fileman.o: $(top_srcdir)/readline.h +rltest.o: $(top_srcdir)/readline.h +rl.o: $(top_srcdir)/readline.h +rlversion.o: $(top_srcdir)/readline.h +histexamp.o: $(top_srcdir)/history.h +rlcat.o: $(top_srcdir)/readline.h $(top_srcdir)/history.h +rlptytest.o: $(top_srcdir)/readline.h $(top_srcdir)/history.h diff --git a/external/gpl3/gdb/dist/readline/examples/excallback.c b/external/gpl3/gdb/dist/readline/examples/excallback.c new file mode 100644 index 000000000000..3d4bb189c691 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/excallback.c @@ -0,0 +1,188 @@ +/* +From: Jeff Solomon +Date: Fri, 9 Apr 1999 10:13:27 -0700 (PDT) +To: chet@po.cwru.edu +Subject: new readline example +Message-ID: <14094.12094.527305.199695@mrclean.Stanford.EDU> + +Chet, + +I've been using readline 4.0. Specifically, I've been using the perl +version Term::ReadLine::Gnu. It works great. + +Anyway, I've been playing around the alternate interface and I wanted +to contribute a little C program, callback.c, to you that you could +use as an example of the alternate interface in the /examples +directory of the readline distribution. + +My example shows how, using the alternate interface, you can +interactively change the prompt (which is very nice imo). Also, I +point out that you must roll your own terminal setting when using the +alternate interface because readline depreps (using your parlance) the +terminal while in the user callback. I try to demostrate what I mean +with an example. I've included the program below. + +To compile, I just put the program in the examples directory and made +the appropriate changes to the EXECUTABLES and OBJECTS line and added +an additional target 'callback'. + +I compiled on my Sun Solaris2.6 box using Sun's cc. + +Let me know what you think. + +Jeff +*/ + +#if defined (HAVE_CONFIG_H) +#include +#endif + +#include +#include + +#ifdef HAVE_UNISTD_H +#include +#endif + +#include /* xxx - should make this more general */ + +#ifdef READLINE_LIBRARY +# include "readline.h" +#else +# include +#endif + +/* This little examples demonstrates the alternate interface to using readline. + * In the alternate interface, the user maintains control over program flow and + * only calls readline when STDIN is readable. Using the alternate interface, + * you can do anything else while still using readline (like talking to a + * network or another program) without blocking. + * + * Specifically, this program highlights two importants features of the + * alternate interface. The first is the ability to interactively change the + * prompt, which can't be done using the regular interface since rl_prompt is + * read-only. + * + * The second feature really highlights a subtle point when using the alternate + * interface. That is, readline will not alter the terminal when inside your + * callback handler. So let's so, your callback executes a user command that + * takes a non-trivial amount of time to complete (seconds). While your + * executing the command, the user continues to type keystrokes and expects them + * to be re-echoed on the new prompt when it returns. Unfortunately, the default + * terminal configuration doesn't do this. After the prompt returns, the user + * must hit one additional keystroke and then will see all of his previous + * keystrokes. To illustrate this, compile and run this program. Type "sleep" at + * the prompt and then type "bar" before the prompt returns (you have 3 + * seconds). Notice how "bar" is re-echoed on the prompt after the prompt + * returns? This is what you expect to happen. Now comment out the 4 lines below + * the line that says COMMENT LINE BELOW. Recompile and rerun the program and do + * the same thing. When the prompt returns, you should not see "bar". Now type + * "f", see how "barf" magically appears? This behavior is un-expected and not + * desired. + */ + +void process_line(char *line); +int change_prompt(void); +char *get_prompt(void); + +int prompt = 1; +char prompt_buf[40], line_buf[256]; +tcflag_t old_lflag; +cc_t old_vtime; +struct termios term; + +int +main() +{ + fd_set fds; + + /* Adjust the terminal slightly before the handler is installed. Disable + * canonical mode processing and set the input character time flag to be + * non-blocking. + */ + if( tcgetattr(STDIN_FILENO, &term) < 0 ) { + perror("tcgetattr"); + exit(1); + } + old_lflag = term.c_lflag; + old_vtime = term.c_cc[VTIME]; + term.c_lflag &= ~ICANON; + term.c_cc[VTIME] = 1; + /* COMMENT LINE BELOW - see above */ + if( tcsetattr(STDIN_FILENO, TCSANOW, &term) < 0 ) { + perror("tcsetattr"); + exit(1); + } + + rl_add_defun("change-prompt", change_prompt, CTRL('t')); + rl_callback_handler_install(get_prompt(), process_line); + + while(1) { + FD_ZERO(&fds); + FD_SET(fileno(stdin), &fds); + + if( select(FD_SETSIZE, &fds, NULL, NULL, NULL) < 0) { + perror("select"); + exit(1); + } + + if( FD_ISSET(fileno(stdin), &fds) ) { + rl_callback_read_char(); + } + } +} + +void +process_line(char *line) +{ + if( line == NULL ) { + fprintf(stderr, "\n", line); + + /* reset the old terminal setting before exiting */ + term.c_lflag = old_lflag; + term.c_cc[VTIME] = old_vtime; + if( tcsetattr(STDIN_FILENO, TCSANOW, &term) < 0 ) { + perror("tcsetattr"); + exit(1); + } + exit(0); + } + + if( strcmp(line, "sleep") == 0 ) { + sleep(3); + } else { + fprintf(stderr, "|%s|\n", line); + } + + free (line); +} + +int +change_prompt(void) +{ + /* toggle the prompt variable */ + prompt = !prompt; + + /* save away the current contents of the line */ + strcpy(line_buf, rl_line_buffer); + + /* install a new handler which will change the prompt and erase the current line */ + rl_callback_handler_install(get_prompt(), process_line); + + /* insert the old text on the new line */ + rl_insert_text(line_buf); + + /* redraw the current line - this is an undocumented function. It invokes the + * redraw-current-line command. + */ + rl_refresh_line(0, 0); +} + +char * +get_prompt(void) +{ + /* The prompts can even be different lengths! */ + sprintf(prompt_buf, "%s", + prompt ? "Hit ctrl-t to toggle prompt> " : "Pretty cool huh?> "); + return prompt_buf; +} diff --git a/external/gpl3/gdb/dist/readline/examples/fileman.c b/external/gpl3/gdb/dist/readline/examples/fileman.c new file mode 100644 index 000000000000..340eee739f60 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/fileman.c @@ -0,0 +1,485 @@ +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +/* fileman.c -- A tiny application which demonstrates how to use the + GNU Readline library. This application interactively allows users + to manipulate files and their modes. */ + +#ifdef HAVE_CONFIG_H +# include +#endif + +#include +#ifdef HAVE_SYS_FILE_H +# include +#endif +#include + +#ifdef HAVE_UNISTD_H +# include +#endif + +#include +#include +#include + +#if defined (HAVE_STRING_H) +# include +#else /* !HAVE_STRING_H */ +# include +#endif /* !HAVE_STRING_H */ + +#ifdef HAVE_STDLIB_H +# include +#endif + +#ifdef READLINE_LIBRARY +# include "readline.h" +# include "history.h" +#else +# include +# include +#endif + +extern char *xmalloc (); + +/* The names of functions that actually do the manipulation. */ +int com_list PARAMS((char *)); +int com_view PARAMS((char *)); +int com_rename PARAMS((char *)); +int com_stat PARAMS((char *)); +int com_pwd PARAMS((char *)); +int com_delete PARAMS((char *)); +int com_help PARAMS((char *)); +int com_cd PARAMS((char *)); +int com_quit PARAMS((char *)); + +/* A structure which contains information on the commands this program + can understand. */ + +typedef struct { + char *name; /* User printable name of the function. */ + rl_icpfunc_t *func; /* Function to call to do the job. */ + char *doc; /* Documentation for this function. */ +} COMMAND; + +COMMAND commands[] = { + { "cd", com_cd, "Change to directory DIR" }, + { "delete", com_delete, "Delete FILE" }, + { "help", com_help, "Display this text" }, + { "?", com_help, "Synonym for `help'" }, + { "list", com_list, "List files in DIR" }, + { "ls", com_list, "Synonym for `list'" }, + { "pwd", com_pwd, "Print the current working directory" }, + { "quit", com_quit, "Quit using Fileman" }, + { "rename", com_rename, "Rename FILE to NEWNAME" }, + { "stat", com_stat, "Print out statistics on FILE" }, + { "view", com_view, "View the contents of FILE" }, + { (char *)NULL, (rl_icpfunc_t *)NULL, (char *)NULL } +}; + +/* Forward declarations. */ +char *stripwhite (); +COMMAND *find_command (); + +/* The name of this program, as taken from argv[0]. */ +char *progname; + +/* When non-zero, this global means the user is done using this program. */ +int done; + +char * +dupstr (s) + char *s; +{ + char *r; + + r = xmalloc (strlen (s) + 1); + strcpy (r, s); + return (r); +} + +main (argc, argv) + int argc; + char **argv; +{ + char *line, *s; + + progname = argv[0]; + + initialize_readline (); /* Bind our completer. */ + + /* Loop reading and executing lines until the user quits. */ + for ( ; done == 0; ) + { + line = readline ("FileMan: "); + + if (!line) + break; + + /* Remove leading and trailing whitespace from the line. + Then, if there is anything left, add it to the history list + and execute it. */ + s = stripwhite (line); + + if (*s) + { + add_history (s); + execute_line (s); + } + + free (line); + } + exit (0); +} + +/* Execute a command line. */ +int +execute_line (line) + char *line; +{ + register int i; + COMMAND *command; + char *word; + + /* Isolate the command word. */ + i = 0; + while (line[i] && whitespace (line[i])) + i++; + word = line + i; + + while (line[i] && !whitespace (line[i])) + i++; + + if (line[i]) + line[i++] = '\0'; + + command = find_command (word); + + if (!command) + { + fprintf (stderr, "%s: No such command for FileMan.\n", word); + return (-1); + } + + /* Get argument to command, if any. */ + while (whitespace (line[i])) + i++; + + word = line + i; + + /* Call the function. */ + return ((*(command->func)) (word)); +} + +/* Look up NAME as the name of a command, and return a pointer to that + command. Return a NULL pointer if NAME isn't a command name. */ +COMMAND * +find_command (name) + char *name; +{ + register int i; + + for (i = 0; commands[i].name; i++) + if (strcmp (name, commands[i].name) == 0) + return (&commands[i]); + + return ((COMMAND *)NULL); +} + +/* Strip whitespace from the start and end of STRING. Return a pointer + into STRING. */ +char * +stripwhite (string) + char *string; +{ + register char *s, *t; + + for (s = string; whitespace (*s); s++) + ; + + if (*s == 0) + return (s); + + t = s + strlen (s) - 1; + while (t > s && whitespace (*t)) + t--; + *++t = '\0'; + + return s; +} + +/* **************************************************************** */ +/* */ +/* Interface to Readline Completion */ +/* */ +/* **************************************************************** */ + +char *command_generator PARAMS((const char *, int)); +char **fileman_completion PARAMS((const char *, int, int)); + +/* Tell the GNU Readline library how to complete. We want to try to complete + on command names if this is the first word in the line, or on filenames + if not. */ +initialize_readline () +{ + /* Allow conditional parsing of the ~/.inputrc file. */ + rl_readline_name = "FileMan"; + + /* Tell the completer that we want a crack first. */ + rl_attempted_completion_function = fileman_completion; +} + +/* Attempt to complete on the contents of TEXT. START and END bound the + region of rl_line_buffer that contains the word to complete. TEXT is + the word to complete. We can use the entire contents of rl_line_buffer + in case we want to do some simple parsing. Return the array of matches, + or NULL if there aren't any. */ +char ** +fileman_completion (text, start, end) + const char *text; + int start, end; +{ + char **matches; + + matches = (char **)NULL; + + /* If this word is at the start of the line, then it is a command + to complete. Otherwise it is the name of a file in the current + directory. */ + if (start == 0) + matches = rl_completion_matches (text, command_generator); + + return (matches); +} + +/* Generator function for command completion. STATE lets us know whether + to start from scratch; without any state (i.e. STATE == 0), then we + start at the top of the list. */ +char * +command_generator (text, state) + const char *text; + int state; +{ + static int list_index, len; + char *name; + + /* If this is a new word to complete, initialize now. This includes + saving the length of TEXT for efficiency, and initializing the index + variable to 0. */ + if (!state) + { + list_index = 0; + len = strlen (text); + } + + /* Return the next name which partially matches from the command list. */ + while (name = commands[list_index].name) + { + list_index++; + + if (strncmp (name, text, len) == 0) + return (dupstr(name)); + } + + /* If no names matched, then return NULL. */ + return ((char *)NULL); +} + +/* **************************************************************** */ +/* */ +/* FileMan Commands */ +/* */ +/* **************************************************************** */ + +/* String to pass to system (). This is for the LIST, VIEW and RENAME + commands. */ +static char syscom[1024]; + +/* List the file(s) named in arg. */ +com_list (arg) + char *arg; +{ + if (!arg) + arg = ""; + + sprintf (syscom, "ls -FClg %s", arg); + return (system (syscom)); +} + +com_view (arg) + char *arg; +{ + if (!valid_argument ("view", arg)) + return 1; + +#if defined (__MSDOS__) + /* more.com doesn't grok slashes in pathnames */ + sprintf (syscom, "less %s", arg); +#else + sprintf (syscom, "more %s", arg); +#endif + return (system (syscom)); +} + +com_rename (arg) + char *arg; +{ + too_dangerous ("rename"); + return (1); +} + +com_stat (arg) + char *arg; +{ + struct stat finfo; + + if (!valid_argument ("stat", arg)) + return (1); + + if (stat (arg, &finfo) == -1) + { + perror (arg); + return (1); + } + + printf ("Statistics for `%s':\n", arg); + + printf ("%s has %d link%s, and is %d byte%s in length.\n", + arg, + finfo.st_nlink, + (finfo.st_nlink == 1) ? "" : "s", + finfo.st_size, + (finfo.st_size == 1) ? "" : "s"); + printf ("Inode Last Change at: %s", ctime (&finfo.st_ctime)); + printf (" Last access at: %s", ctime (&finfo.st_atime)); + printf (" Last modified at: %s", ctime (&finfo.st_mtime)); + return (0); +} + +com_delete (arg) + char *arg; +{ + too_dangerous ("delete"); + return (1); +} + +/* Print out help for ARG, or for all of the commands if ARG is + not present. */ +com_help (arg) + char *arg; +{ + register int i; + int printed = 0; + + for (i = 0; commands[i].name; i++) + { + if (!*arg || (strcmp (arg, commands[i].name) == 0)) + { + printf ("%s\t\t%s.\n", commands[i].name, commands[i].doc); + printed++; + } + } + + if (!printed) + { + printf ("No commands match `%s'. Possibilties are:\n", arg); + + for (i = 0; commands[i].name; i++) + { + /* Print in six columns. */ + if (printed == 6) + { + printed = 0; + printf ("\n"); + } + + printf ("%s\t", commands[i].name); + printed++; + } + + if (printed) + printf ("\n"); + } + return (0); +} + +/* Change to the directory ARG. */ +com_cd (arg) + char *arg; +{ + if (chdir (arg) == -1) + { + perror (arg); + return 1; + } + + com_pwd (""); + return (0); +} + +/* Print out the current working directory. */ +com_pwd (ignore) + char *ignore; +{ + char dir[1024], *s; + + s = getcwd (dir, sizeof(dir) - 1); + if (s == 0) + { + printf ("Error getting pwd: %s\n", dir); + return 1; + } + + printf ("Current directory is %s\n", dir); + return 0; +} + +/* The user wishes to quit using this program. Just set DONE non-zero. */ +com_quit (arg) + char *arg; +{ + done = 1; + return (0); +} + +/* Function which tells you that you can't do this. */ +too_dangerous (caller) + char *caller; +{ + fprintf (stderr, + "%s: Too dangerous for me to distribute. Write it yourself.\n", + caller); +} + +/* Return non-zero if ARG is a valid argument for CALLER, else print + an error message and return zero. */ +int +valid_argument (caller, arg) + char *caller, *arg; +{ + if (!arg || !*arg) + { + fprintf (stderr, "%s: Argument required.\n", caller); + return (0); + } + + return (1); +} diff --git a/external/gpl3/gdb/dist/readline/examples/histexamp.c b/external/gpl3/gdb/dist/readline/examples/histexamp.c new file mode 100644 index 000000000000..4f059c17cc33 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/histexamp.c @@ -0,0 +1,124 @@ +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#include + +#ifdef READLINE_LIBRARY +# include "history.h" +#else +# include +#endif + +#include + +main (argc, argv) + int argc; + char **argv; +{ + char line[1024], *t; + int len, done; + + line[0] = 0; + done = 0; + + using_history (); + while (!done) + { + printf ("history$ "); + fflush (stdout); + t = fgets (line, sizeof (line) - 1, stdin); + if (t && *t) + { + len = strlen (t); + if (t[len - 1] == '\n') + t[len - 1] = '\0'; + } + + if (!t) + strcpy (line, "quit"); + + if (line[0]) + { + char *expansion; + int result; + + using_history (); + + result = history_expand (line, &expansion); + if (result) + fprintf (stderr, "%s\n", expansion); + + if (result < 0 || result == 2) + { + free (expansion); + continue; + } + + add_history (expansion); + strncpy (line, expansion, sizeof (line) - 1); + free (expansion); + } + + if (strcmp (line, "quit") == 0) + done = 1; + else if (strcmp (line, "save") == 0) + write_history ("history_file"); + else if (strcmp (line, "read") == 0) + read_history ("history_file"); + else if (strcmp (line, "list") == 0) + { + register HIST_ENTRY **the_list; + register int i; + time_t tt; + char timestr[128]; + + the_list = history_list (); + if (the_list) + for (i = 0; the_list[i]; i++) + { + tt = history_get_time (the_list[i]); + if (tt) + strftime (timestr, sizeof (timestr), "%a %R", localtime(&tt)); + else + strcpy (timestr, "??"); + printf ("%d: %s: %s\n", i + history_base, timestr, the_list[i]->line); + } + } + else if (strncmp (line, "delete", 6) == 0) + { + int which; + if ((sscanf (line + 6, "%d", &which)) == 1) + { + HIST_ENTRY *entry = remove_history (which); + if (!entry) + fprintf (stderr, "No such entry %d\n", which); + else + { + free (entry->line); + free (entry); + } + } + else + { + fprintf (stderr, "non-numeric arg given to `delete'\n"); + } + } + } +} diff --git a/external/gpl3/gdb/dist/readline/examples/manexamp.c b/external/gpl3/gdb/dist/readline/examples/manexamp.c new file mode 100644 index 000000000000..9c6cf2c76c61 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/manexamp.c @@ -0,0 +1,112 @@ +/* manexamp.c -- The examples which appear in the documentation are here. */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#include +#include + +/* **************************************************************** */ +/* */ +/* How to Emulate gets () */ +/* */ +/* **************************************************************** */ + +/* A static variable for holding the line. */ +static char *line_read = (char *)NULL; + +/* Read a string, and return a pointer to it. Returns NULL on EOF. */ +char * +rl_gets () +{ + /* If the buffer has already been allocated, return the memory + to the free pool. */ + if (line_read) + { + free (line_read); + line_read = (char *)NULL; + } + + /* Get a line from the user. */ + line_read = readline (""); + + /* If the line has any text in it, save it on the history. */ + if (line_read && *line_read) + add_history (line_read); + + return (line_read); +} + +/* **************************************************************** */ +/* */ +/* Writing a Function to be Called by Readline. */ +/* */ +/* **************************************************************** */ + +/* Invert the case of the COUNT following characters. */ +invert_case_line (count, key) + int count, key; +{ + register int start, end; + + start = rl_point; + + if (count < 0) + { + direction = -1; + count = -count; + } + else + direction = 1; + + /* Find the end of the range to modify. */ + end = start + (count * direction); + + /* Force it to be within range. */ + if (end > rl_end) + end = rl_end; + else if (end < 0) + end = -1; + + if (start > end) + { + int temp = start; + start = end; + end = temp; + } + + if (start == end) + return; + + /* Tell readline that we are modifying the line, so save the undo + information. */ + rl_modifying (start, end); + + for (; start != end; start += direction) + { + if (_rl_uppercase_p (rl_line_buffer[start])) + rl_line_buffer[start] = _rl_to_lower (rl_line_buffer[start]); + else if (_rl_lowercase_p (rl_line_buffer[start])) + rl_line_buffer[start] = _rl_to_upper (rl_line_buffer[start]); + } + + /* Move point to on top of the last character changed. */ + rl_point = end - direction; +} diff --git a/external/gpl3/gdb/dist/readline/examples/readlinebuf.h b/external/gpl3/gdb/dist/readline/examples/readlinebuf.h new file mode 100644 index 000000000000..9ccb9e91bd62 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/readlinebuf.h @@ -0,0 +1,139 @@ +/******************************************************************************* + * $Revision: 1.1.1.1 $ + * $Date: 2011/09/24 19:56:56 $ + * $Author: christos $ + * + * Contents: A streambuf which uses the GNU readline library for line I/O + * (c) 2001 by Dimitris Vyzovitis [vyzo@media.mit.edu] + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************************/ + +#ifndef _READLINEBUF_H_ +#define _READLINEBUF_H_ + +#include +#include +#include +#include +#include + +#include +#include + +#if (defined __GNUC__) && (__GNUC__ < 3) +#include +#else +#include +using std::streamsize; +using std::streambuf; +#endif + +class readlinebuf : public streambuf { +public: +#if (defined __GNUC__) && (__GNUC__ < 3) + typedef char char_type; + typedef int int_type; + typedef streampos pos_type; + typedef streamoff off_type; +#endif + static const int_type eof = EOF; // this is -1 + static const int_type not_eof = 0; + +private: + const char* prompt_; + bool history_; + char* line_; + int low_; + int high_; + +protected: + + virtual int_type showmanyc() const { return high_ - low_; } + + virtual streamsize xsgetn( char_type* buf, streamsize n ) { + int rd = n > (high_ - low_)? (high_ - low_) : n; + memcpy( buf, line_, rd ); + low_ += rd; + + if ( rd < n ) { + low_ = high_ = 0; + free( line_ ); // free( NULL ) is a noop + line_ = readline( prompt_ ); + if ( line_ ) { + high_ = strlen( line_ ); + if ( history_ && high_ ) add_history( line_ ); + rd += xsgetn( buf + rd, n - rd ); + } + } + + return rd; + } + + virtual int_type underflow() { + if ( high_ == low_ ) { + low_ = high_ = 0; + free( line_ ); // free( NULL ) is a noop + line_ = readline( prompt_ ); + if ( line_ ) { + high_ = strlen( line_ ); + if ( history_ && high_ ) add_history( line_ ); + } + } + + if ( low_ < high_ ) return line_[low_]; + else return eof; + } + + virtual int_type uflow() { + int_type c = underflow(); + if ( c != eof ) ++low_; + return c; + } + + virtual int_type pbackfail( int_type c = eof ) { + if ( low_ > 0 ) --low_; + else if ( c != eof ) { + if ( high_ > 0 ) { + char* nl = (char*)realloc( line_, high_ + 1 ); + if ( nl ) { + line_ = (char*)memcpy( nl + 1, line_, high_ ); + high_ += 1; + line_[0] = char( c ); + } else return eof; + } else { + assert( !line_ ); + line_ = (char*)malloc( sizeof( char ) ); + *line_ = char( c ); + high_ = 1; + } + } else return eof; + + return not_eof; + } + +public: + readlinebuf( const char* prompt = NULL, bool history = true ) + : prompt_( prompt ), history_( history ), + line_( NULL ), low_( 0 ), high_( 0 ) { + setbuf( 0, 0 ); + } + + +}; + +#endif diff --git a/external/gpl3/gdb/dist/readline/examples/rl-fgets.c b/external/gpl3/gdb/dist/readline/examples/rl-fgets.c new file mode 100644 index 000000000000..5512b94ab239 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rl-fgets.c @@ -0,0 +1,374 @@ +/* +Date: Tue, 16 Mar 2004 19:38:40 -0800 +From: Harold Levy +Subject: fgets(stdin) --> readline() redirector +To: chet@po.cwru.edu + +Hi Chet, + +Here is something you may find useful enough to include in the readline +distribution. It is a shared library that redirects calls to fgets(stdin) +to readline() via LD_PRELOAD, and it supports a custom prompt and list of +command names. Many people have asked me for this file, so I thought I'd +pass it your way in hope of just including it with readline to begin with. + +Best Regards, + +-Harold +*/ + +/****************************************************************************** +******************************************************************************* + + FILE NAME: fgets.c TARGET: libfgets.so + AUTHOR: Harold Levy VERSION: 1.0 + hlevy@synopsys.com + + ABSTRACT: Customize fgets() behavior via LD_PRELOAD in the following ways: + + -- If fgets(stdin) is called, redirect to GNU readline() to obtain + command-line editing, file-name completion, history, etc. + + -- A list of commands for command-name completion can be configured by + setting the environment-variable FGETS_COMMAND_FILE to a file containing + the list of commands to be used. + + -- Command-line editing with readline() works best when the prompt string + is known; you can set this with the FGETS_PROMPT environment variable. + + -- There special strings that libfgets will interpret as internal commands: + + _fgets_reset_ reset the command list + + _fgets_dump_ dump status + + _fgets_debug_ toggle debug messages + + HOW TO BUILD: Here are examples of how to build libfgets.so on various + platforms; you will have to add -I and -L flags to configure access to + the readline header and library files. + + (32-bit builds with gcc) + AIX: gcc -fPIC fgets.c -shared -o libfgets.so -lc -ldl -lreadline -ltermcap + HP-UX: gcc -fPIC fgets.c -shared -o libfgets.so -lc -ldld -lreadline + Linux: gcc -fPIC fgets.c -shared -o libfgets.so -lc -ldl -lreadline + SunOS: gcc -fPIC fgets.c -shared -o libfgets.so -lc -ldl -lgen -lreadline + + (64-bit builds without gcc) + SunOS: SUNWspro/bin/cc -D_LARGEFILE64_SOURCE=1 -xtarget=ultra -xarch=v9 \ + -KPIC fgets.c -Bdynamic -lc -ldl -lgen -ltermcap -lreadline + + HOW TO USE: Different operating systems have different levels of support + for the LD_PRELOAD concept. The generic method for 32-bit platforms is to + put libtermcap.so, libfgets.so, and libreadline.so (with absolute paths) + in the LD_PRELOAD environment variable, and to put their parent directories + in the LD_LIBRARY_PATH environment variable. Unfortunately there is no + generic method for 64-bit platforms; e.g. for 64-bit SunOS, you would have + to build both 32-bit and 64-bit libfgets and libreadline libraries, and + use the LD_FLAGS_32 and LD_FLAGS_64 environment variables with preload and + library_path configurations (a mix of 32-bit and 64-bit calls are made under + 64-bit SunOS). + + EXAMPLE WRAPPER: Here is an example shell script wrapper around the + program "foo" that uses fgets() for command-line input: + + #!/bin/csh + #### replace this with the libtermcap.so directory: + set dir1 = "/usr/lib" + #### replace this with the libfgets.so directory: + set dir2 = "/usr/fgets" + #### replace this with the libreadline.so directory: + set dir3 = "/usr/local/lib" + set lib1 = "${dir1}/libtermcap.so" + set lib2 = "${dir2}/libfgets.so" + set lib3 = "${dir3}/libreadline.so" + if ( "${?LD_PRELOAD}" ) then + setenv LD_PRELOAD "${lib1}:${lib2}:${lib3}:${LD_PRELOAD}" + else + setenv LD_PRELOAD "${lib1}:${lib2}:${lib3}" + endif + if ( "${?LD_LIBRARY_PATH}" ) then + setenv LD_LIBRARY_PATH "${dir1}:${dir2}:${dir3}:${LD_LIBRARY_PATH}" + else + setenv LD_LIBRARY_PATH "${dir1}:${dir2}:${dir3}" + endif + setenv FGETS_COMMAND_FILE "${dir2}/foo.commands" + setenv FGETS_PROMPT "foo> " + exec "foo" $* + + Copyright (C)©2003-2004 Harold Levy. + + This code links to the GNU readline library, and as such is bound by the + terms of the GNU General Public License as published by the Free Software + Foundation, either version 2 or (at your option) any later version. + + The GNU General Public License is often shipped with GNU software, and is + generally kept in a file called COPYING or LICENSE. If you do not have a + copy of the license, write to the Free Software Foundation, 59 Temple Place, + Suite 330, Boston, MA 02111 USA. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. + +******************************************************************************* +******************************************************************************/ + + + +#include +#include +#include +#include +#include + +#include +#include + + + +/* for dynamically connecting to the native fgets() */ +#if defined(RTLD_NEXT) +#define REAL_LIBC RTLD_NEXT +#else +#define REAL_LIBC ((void *) -1L) +#endif +typedef char * ( * fgets_t ) ( char * s, int n, FILE * stream ) ; + + + +/* private data */ +/* -- writeable data is stored in the shared library's data segment + -- every process that uses the shared library gets a private memory copy of + its entire data segment + -- static data in the shared library is not copied to the application + -- only read-only (i.e. 'const') data is stored in the shared library's + text segment +*/ +static char ** my_fgets_names = NULL ; +static int my_fgets_number_of_names = 0 ; +static int my_fgets_debug_flag = 0 ; + + + +/* invoked with _fgets_reset_ */ +static void +my_fgets_reset ( + void +) { + if ( my_fgets_names && (my_fgets_number_of_names > 0) ) { + int i ; + if ( my_fgets_debug_flag ) { + printf ( "libfgets: removing command list\n" ) ; + } + for ( i = 0 ; i < my_fgets_number_of_names ; i ++ ) { + if ( my_fgets_names[i] ) free ( my_fgets_names[i] ) ; + } + free ( my_fgets_names ) ; + } + my_fgets_names = NULL ; + my_fgets_number_of_names = 0 ; +} + + + +/* invoked with _fgets_dump_ */ +static void +my_fgets_dump ( + void +) { + char * s ; + printf ( "\n" ) ; + s = getenv ( "FGETS_PROMPT" ) ; + printf ( "FGETS_PROMPT = %s\n", s ? s : "" ) ; + s = getenv ( "FGETS_COMMAND_FILE" ) ; + printf ( "FGETS_COMMAND_FILE = %s\n", s ? s : "" ) ; + printf ( "debug flag = %d\n", my_fgets_debug_flag ) ; + printf ( "#commands = %d\n", my_fgets_number_of_names ) ; + if ( my_fgets_debug_flag ) { + if ( my_fgets_names && (my_fgets_number_of_names > 0) ) { + int i ; + for ( i = 0 ; i < my_fgets_number_of_names ; i ++ ) { + printf ( "%s\n", my_fgets_names[i] ) ; + } + } + } + printf ( "\n" ) ; +} + + + +/* invoked with _fgets_debug_ */ +static void +my_fgets_debug_toggle ( + void +) { + my_fgets_debug_flag = my_fgets_debug_flag ? 0 : 1 ; + if ( my_fgets_debug_flag ) { + printf ( "libfgets: debug flag = %d\n", my_fgets_debug_flag ) ; + } +} + + + +/* read the command list if needed, return the i-th name */ +static char * +my_fgets_lookup ( + int index +) { + if ( (! my_fgets_names) || (! my_fgets_number_of_names) ) { + char * fname ; + FILE * fp ; + fgets_t _fgets ; + int i ; + char buf1[256], buf2[256] ; + fname = getenv ( "FGETS_COMMAND_FILE" ) ; + if ( ! fname ) { + if ( my_fgets_debug_flag ) { + printf ( "libfgets: empty or unset FGETS_COMMAND_FILE\n" ) ; + } + return NULL ; + } + fp = fopen ( fname, "r" ) ; + if ( ! fp ) { + if ( my_fgets_debug_flag ) { + printf ( "libfgets: cannot open '%s' for reading\n", fname ) ; + } + return NULL ; + } + _fgets = (fgets_t) dlsym ( REAL_LIBC, "fgets" ) ; + if ( ! _fgets ) { + fprintf ( stderr, + "libfgets: failed to dynamically link to native fgets()\n" + ) ; + return NULL ; + } + for ( i = 0 ; _fgets(buf1,255,fp) ; i ++ ) ; + if ( ! i ) { fclose(fp) ; return NULL ; } + my_fgets_names = (char**) calloc ( i, sizeof(char*) ) ; + rewind ( fp ) ; + i = 0 ; + while ( _fgets(buf1,255,fp) ) { + buf1[255] = 0 ; + if ( 1 == sscanf(buf1,"%s",buf2) ) { + my_fgets_names[i] = strdup(buf2) ; + i ++ ; + } + } + fclose ( fp ) ; + my_fgets_number_of_names = i ; + if ( my_fgets_debug_flag ) { + printf ( "libfgets: successfully read %d commands\n", i ) ; + } + } + if ( index < my_fgets_number_of_names ) { + return my_fgets_names[index] ; + } else { + return NULL ; + } +} + + + +/* generate a list of partial name matches for readline() */ +static char * +my_fgets_generator ( + const char * text, + int state +) +{ + static int list_index, len ; + char * name ; + if ( ! state ) { + list_index = 0 ; + len = strlen ( text ) ; + } + while ( ( name = my_fgets_lookup(list_index) ) ) { + list_index ++ ; + if ( ! strncmp ( name, text, len ) ) { + return ( strdup ( name ) ) ; + } + } + return ( NULL ) ; +} + + + +/* partial name completion callback for readline() */ +static char ** +my_fgets_completion ( + const char * text, + int start, + int end +) +{ + char ** matches ; + matches = NULL ; + if ( ! start ) { + matches = rl_completion_matches ( text, my_fgets_generator ) ; + } + return ( matches ) ; +} + + + +/* fgets() intercept */ +char * +fgets ( + char * s, + int n, + FILE * stream +) +{ + if ( ! s ) return NULL ; + if ( stream == stdin ) { + char * prompt ; + char * my_fgets_line ; + rl_already_prompted = 1 ; + rl_attempted_completion_function = my_fgets_completion ; + rl_catch_signals = 1 ; + rl_catch_sigwinch = 1 ; + rl_set_signals () ; + prompt = getenv ( "FGETS_PROMPT" ) ; + for ( + my_fgets_line = 0 ; ! my_fgets_line ; my_fgets_line=readline(prompt) + ) ; + if ( ! strncmp(my_fgets_line, "_fgets_reset_", 13) ) { + my_fgets_reset () ; + free ( my_fgets_line ) ; + strcpy ( s, "\n" ) ; + return ( s ) ; + } + if ( ! strncmp(my_fgets_line, "_fgets_dump_", 12) ) { + my_fgets_dump () ; + free ( my_fgets_line ) ; + strcpy ( s, "\n" ) ; + return ( s ) ; + } + if ( ! strncmp(my_fgets_line, "_fgets_debug_", 13) ) { + my_fgets_debug_toggle () ; + free ( my_fgets_line ) ; + strcpy ( s, "\n" ) ; + return ( s ) ; + } + (void) strncpy ( s, my_fgets_line, n-1 ) ; + (void) strcat ( s, "\n" ) ; + if ( *my_fgets_line ) add_history ( my_fgets_line ) ; + free ( my_fgets_line ) ; + return ( s ) ; + } else { + static fgets_t _fgets ; + _fgets = (fgets_t) dlsym ( REAL_LIBC, "fgets" ) ; + if ( ! _fgets ) { + fprintf ( stderr, + "libfgets: failed to dynamically link to native fgets()\n" + ) ; + strcpy ( s, "\n" ) ; + return ( s ) ; + } + return ( + _fgets ( s, n, stream ) + ) ; + } +} diff --git a/external/gpl3/gdb/dist/readline/examples/rl.c b/external/gpl3/gdb/dist/readline/examples/rl.c new file mode 100644 index 000000000000..c608c15f3d67 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rl.c @@ -0,0 +1,158 @@ +/* + * rl - command-line interface to read a line from the standard input + * (or another fd) using readline. + * + * usage: rl [-p prompt] [-u unit] [-d default] [-n nchars] + */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include + +#ifdef HAVE_STDLIB_H +# include +#else +extern void exit(); +#endif + +#if defined (READLINE_LIBRARY) +# include "posixstat.h" +# include "readline.h" +# include "history.h" +#else +# include +# include +# include +#endif + +extern int optind; +extern char *optarg; + +#if !defined (strchr) && !defined (__STDC__) +extern char *strrchr(); +#endif + +static char *progname; +static char *deftext; + +static int +set_deftext () +{ + if (deftext) + { + rl_insert_text (deftext); + deftext = (char *)NULL; + rl_startup_hook = (rl_hook_func_t *)NULL; + } + return 0; +} + +static void +usage() +{ + fprintf (stderr, "%s: usage: %s [-p prompt] [-u unit] [-d default] [-n nchars]\n", + progname, progname); +} + +int +main (argc, argv) + int argc; + char **argv; +{ + char *temp, *prompt; + struct stat sb; + int opt, fd, nch; + FILE *ifp; + + progname = strrchr(argv[0], '/'); + if (progname == 0) + progname = argv[0]; + else + progname++; + + /* defaults */ + prompt = "readline$ "; + fd = nch = 0; + deftext = (char *)0; + + while ((opt = getopt(argc, argv, "p:u:d:n:")) != EOF) + { + switch (opt) + { + case 'p': + prompt = optarg; + break; + case 'u': + fd = atoi(optarg); + if (fd < 0) + { + fprintf (stderr, "%s: bad file descriptor `%s'\n", progname, optarg); + exit (2); + } + break; + case 'd': + deftext = optarg; + break; + case 'n': + nch = atoi(optarg); + if (nch < 0) + { + fprintf (stderr, "%s: bad value for -n: `%s'\n", progname, optarg); + exit (2); + } + break; + default: + usage (); + exit (2); + } + } + + if (fd != 0) + { + if (fstat (fd, &sb) < 0) + { + fprintf (stderr, "%s: %d: bad file descriptor\n", progname, fd); + exit (1); + } + ifp = fdopen (fd, "r"); + rl_instream = ifp; + } + + if (deftext && *deftext) + rl_startup_hook = set_deftext; + + if (nch > 0) + rl_num_chars_to_read = nch; + + temp = readline (prompt); + + /* Test for EOF. */ + if (temp == 0) + exit (1); + + printf ("%s\n", temp); + exit (0); +} diff --git a/external/gpl3/gdb/dist/readline/examples/rlcat.c b/external/gpl3/gdb/dist/readline/examples/rlcat.c new file mode 100644 index 000000000000..33aea4a30077 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlcat.c @@ -0,0 +1,180 @@ +/* + * rlcat - cat(1) using readline + * + * usage: rlcat + */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#ifdef HAVE_UNISTD_H +# include +#endif + +#include +#include "posixstat.h" + +#include +#include +#include +#include + +#ifdef HAVE_STDLIB_H +# include +#else +extern void exit(); +#endif + +#ifndef errno +extern int errno; +#endif + +#if defined (READLINE_LIBRARY) +# include "readline.h" +# include "history.h" +#else +# include +# include +#endif + +extern int optind; +extern char *optarg; + +static int stdcat(); + +static char *progname; +static int vflag; + +static void +usage() +{ + fprintf (stderr, "%s: usage: %s [-vEVN] [filename]\n", progname, progname); +} + +int +main (argc, argv) + int argc; + char **argv; +{ + char *temp; + int opt, Vflag, Nflag; + + progname = strrchr(argv[0], '/'); + if (progname == 0) + progname = argv[0]; + else + progname++; + + vflag = Vflag = Nflag = 0; + while ((opt = getopt(argc, argv, "vEVN")) != EOF) + { + switch (opt) + { + case 'v': + vflag = 1; + break; + case 'V': + Vflag = 1; + break; + case 'E': + Vflag = 0; + break; + case 'N': + Nflag = 1; + break; + default: + usage (); + exit (2); + } + } + + argc -= optind; + argv += optind; + + if (isatty(0) == 0 || argc || Nflag) + return stdcat(argc, argv); + + rl_variable_bind ("editing-mode", Vflag ? "vi" : "emacs"); + while (temp = readline ("")) + { + if (*temp) + add_history (temp); + printf ("%s\n", temp); + } + + return (ferror (stdout)); +} + +static int +fcopy(fp) + FILE *fp; +{ + int c; + char *x; + + while ((c = getc(fp)) != EOF) + { + if (vflag && isascii ((unsigned char)c) && isprint((unsigned char)c) == 0) + { + x = rl_untranslate_keyseq (c); + if (fputs (x, stdout) != 0) + return 1; + } + else if (putchar (c) == EOF) + return 1; + } + return (ferror (stdout)); +} + +int +stdcat (argc, argv) + int argc; + char **argv; +{ + int i, fd, r; + char *s; + FILE *fp; + + if (argc == 0) + return (fcopy(stdin)); + + for (i = 0, r = 1; i < argc; i++) + { + if (*argv[i] == '-' && argv[i][1] == 0) + fp = stdin; + else + { + fp = fopen (argv[i], "r"); + if (fp == 0) + { + fprintf (stderr, "%s: %s: cannot open: %s\n", progname, argv[i], strerror(errno)); + continue; + } + } + r = fcopy (fp); + if (fp != stdin) + fclose(fp); + } + return r; +} diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/ChangeLog b/external/gpl3/gdb/dist/readline/examples/rlfe/ChangeLog new file mode 100644 index 000000000000..210f6ebbb99b --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/ChangeLog @@ -0,0 +1,48 @@ +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + + * configure.in: m4_include toplevel config/override.m4. + * configure: Regenerate. + +2009-07-30 Ralf Wildenhues + + * configure.in: Correctly quote AC_PROGRAM_SOURCE definition. + +2004-11-04 Per Bothner + + * pty.c: Import from screen-4.0.2. + * configure.in, Makefile.in, config.h.in: Set up autoconf handling, + copying a bunk of stuff over from screen. + * rlfe.c: Use OpenPTY from pty.c instead of get_master_pty. + +2004-11-03 Per Bothner + + * rlfe.c: Get input emphasis (boldening) more robust. + + * rlfe.c: Various cleanups on comments and names. + +2003-11-07 Wolfgang Taeuber + + * Specify a history file and the size of the history file with command + * line options; use EDITOR/VISUAL to set vi/emacs preference. + +1999-09-03 Chet Ramey + + * fep.c: Memmove is not universally available. This patch assumes + that an autoconf test has been performed, and that memcpy is + available without checking. + + * fep.c: VDISCARD is not universally available, even when termios is. + + * fep.c: If a system doesn't have TIOCSCTTY, the first `open' + performed after setsid allocates a controlling terminal. The + original code would leave the child process running on the slave pty + without a controlling tty if TIOCSCTTY was not available. + + * fep.c: Most versions of SVR4, including solaris, don't allow + terminal ioctl calls on the master side of the pty. + +1999-08-28 Per Bothner + + * fep.c: Initial release. diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/Makefile.in b/external/gpl3/gdb/dist/readline/examples/rlfe/Makefile.in new file mode 100644 index 000000000000..4653dec4e9bd --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/Makefile.in @@ -0,0 +1,176 @@ +# +# Makefile template for rlfe +# +# See machine dependant config.h for more configuration options. +# + +srcdir = @srcdir@ +VPATH = @srcdir@ + +DESTDIR = + +# Where to install screen. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +# don't forget to change mandir and infodir in doc/Makefile. +bindir = $(exec_prefix)/bin + +VERSION = @VERSION@ +SCREEN = screen-$(VERSION) + +CC = @CC@ +CFLAGS = @CFLAGS@ +CPPFLAGS = @CPPFLAGS@ +#LDFLAGS = -L$(READLINE_DIR) +LDFLAGS = @LDFLAGS@ +LIBS = -lreadline -lhistory -lncurses + +CPP=@CPP@ +CPP_DEPEND=$(CC) -MM + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +AWK = @AWK@ + +OPTIONS= +#OPTIONS= -DDEBUG + +SHELL=/bin/sh + +CFILES= rlfe.c pty.c +HFILES= extern.h os.h screen.h +EXTRA_DIST=configure.in configure Makefile.in config.h.in ChangeLog README +OFILES= rlfe.o pty.o + +all: rlfe + +rlfe: $(OFILES) + $(CC) $(LDFLAGS) -o $@ $(OFILES) $(LIBS) + +rlfe-$(VERSION).tar.gz: + tar czf $@ $(CFILES) $(HFILES) $(EXTRA_DIST) + +.c.o: + $(CC) -c -I. -I$(srcdir) $(M_CFLAGS) $(DEFS) $(OPTIONS) $(CFLAGS) $< + +install_bin: .version screen + -if [ -f $(DESTDIR)$(bindir)/$(SCREEN) ] && [ ! -f $(DESTDIR)$(bindir)/$(SCREEN).old ]; \ + then mv $(DESTDIR)$(bindir)/$(SCREEN) $(DESTDIR)$(bindir)/$(SCREEN).old; fi + $(INSTALL_PROGRAM) screen $(DESTDIR)$(bindir)/$(SCREEN) + -chown root $(DESTDIR)$(bindir)/$(SCREEN) && chmod 4755 $(DESTDIR)$(bindir)/$(SCREEN) +# This doesn't work if $(bindir)/screen is a symlink + -if [ -f $(DESTDIR)$(bindir)/screen ] && [ ! -f $(DESTDIR)$(bindir)/screen.old ]; then mv $(DESTDIR)$(bindir)/screen $(DESTDIR)$(bindir)/screen.old; fi + rm -f $(DESTDIR)$(bindir)/screen + (cd $(DESTDIR)$(bindir) && ln -sf $(SCREEN) screen) + cp $(srcdir)/utf8encodings/?? $(DESTDIR)$(SCREENENCODINGS) + + +uninstall: .version + rm -f $(DESTDIR)$(bindir)/$(SCREEN) + rm -f $(DESTDIR)$(bindir)/screen + -mv $(DESTDIR)$(bindir)/screen.old $(DESTDIR)$(bindir)/screen + rm -f $(DESTDIR)$(ETCSCREENRC) + cd doc; $(MAKE) uninstall + +shadow: + mkdir shadow; + cd shadow; ln -s ../*.[ch] ../*.in ../*.sh ../configure ../doc ../terminfo ../etc . + rm -f shadow/term.h shadow/tty.c shadow/comm.h shadow/osdef.h + echo "install all Makefiles and config:" > shadow/Makefile + echo " rm -f config.cache" >> shadow/Makefile + echo " sh ./configure" >> shadow/Makefile + +term.h: term.c term.sh + AWK=$(AWK) srcdir=$(srcdir) sh $(srcdir)/term.sh + +kmapdef.c: term.h + +tty.c: tty.sh + sh $(srcdir)/tty.sh tty.c + +mostlyclean: + rm -f $(OFILES) rlfe *.o + +clean celan: mostlyclean + rm -f tty.c term.h comm.h osdef.h kmapdef.c core + +# Delete all files from the current directory that are created by +# configuring or building the program. +# building of term.h/comm.h requires awk. Keep it in the distribution +# we keep config.h, as this file knows where 'make dist' finds the ETCSCREENRC. +#distclean: mostlyclean +# rm -f $(SCREEN).tar $(SCREEN).tar.gz +# rm -f config.status Makefile +# rm -f osdef.h doc/Makefile + +maintainer-clean: + @echo "This command is not even intended for maintainers to use;" + @echo "it deletes files that may require special tools to rebuild." + + +# Delete everything from the current directory that can be +# reconstructed with this Makefile. +realclean: .version mostlyclean + rm -f $(SCREEN).tar $(SCREEN).tar.gz + rm -f config.status Makefile doc/Makefile + rm -f tty.c term.h comm.h osdef.h kmapdef.c + rm -f config.h + echo "install all Makefiles and config:" > Makefile + echo " sh ./configure" >> Makefile + +tags TAGS: $(CFILES) + -ctags *.sh $(CFILES) *.h + -ctags -e *.sh $(CFILES) *.h + +dist: .version $(SCREEN).tar.gz + + +# Perform self-tests (if any). +check: + +config: + rm -f config.cache + sh ./configure + + +############################################################################### + +.version: + @rev=`sed < $(srcdir)/patchlevel.h -n -e '/#define REV/s/#define REV *//p'`; \ + vers=`sed < $(srcdir)/patchlevel.h -n -e '/#define VERS/s/#define VERS *//p'`; \ + pat=`sed < $(srcdir)/patchlevel.h -n -e '/#define PATCHLEVEL/s/#define PATCHLEVEL *//p'`; \ + if [ "$${rev}.$${vers}.$${pat}" != "$(VERSION)" ]; then \ + echo "This distribution is screen-$${rev}.$${vers}.$${pat}, but"; \ + echo "the Makefile is from $(VERSION). Please update!"; exit 1; fi + +############################################################################### + +mdepend: $(CFILES) term.h + @rm -f DEPEND ; \ + for i in ${CFILES} ; do \ + echo "$$i" ; \ + echo `echo "$$i" | sed -e 's/.c$$/.o/'`": $$i" `\ + cc -E $$i |\ + grep '^# .*"\./.*\.h"' |\ + (sort -t'"' -u -k 2,2 2>/dev/null || sort -t'"' -u +1 -2) |\ + sed -e 's/.*"\.\/\(.*\)".*/\1/'\ + ` >> DEPEND ; \ + done + +depend: depend.in + ./config.status || ./configure + +depend.in: $(CFILES) term.h + cp Makefile.in Makefile.in~ + sed -e '/\#\#\# Dependencies/q' < Makefile.in > tmp_make + for i in $(CFILES); do echo $$i; $(CPP_DEPEND) $$i >> tmp_make; done + mv tmp_make Makefile.in + +############################################################################### + +### Dependencies: +pty.o: pty.c config.h diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/README b/external/gpl3/gdb/dist/readline/examples/rlfe/README new file mode 100644 index 000000000000..9e1f689dc976 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/README @@ -0,0 +1,78 @@ +rlfe (ReadLine Front-End) is a "universal wrapper" around readline. +You specify an interactive program to run (typically a shell), and +readline is used to edit input lines. + +There are other such front-ends; what distinguishes this one is that +it monitors the state of the inferior pty, and if the inferior program +switches its terminal to raw mode, then rlfe passes your characters +through directly. This basically means you can run your entire +session (including bash and terminal-mode emacs) under rlfe. + +FEATURES + +* Can use all readline commands (and history) in commands that +read input lines in "canonical mode" - even 'cat'! + +* Automatically switches between "readline-editing mode" and "raw mode" +depending on the terminal mode. If the inferior program invokes +readline itself, it will do its own line editing. (The inferior +readline will not know about rlfe, and it will have its own history.) +You can even run programs like 'emavs -nw' and 'vi' under rlfe. +The goal is you could leave rlfe always on without even knowing +about it. (We're not quite there, but it works tolerably well.) + +* The input line (after any prompt) is changed to bold-face. + +INSTALL + +The usual: ./configure && make && make install + +Note so far rlfe has only been tested on GNU Linux (Fedora Core 2) +and Mac OS X (10.3). + +This assumes readline header files and libraries are in the default +places. If not, you can create a link named readline pointing to the +readline sources. To link with libreadline.a and libhistory.a +you can copy or link them, or add LDFLAGS='-/path/to/readline' to +the make command-line. + +USAGE + +Just run it. That by default runs bash. You can run some other +command by giving it as command-line arguments. + +There are a few tweaks: -h allows you to name the history file, +and -s allows you to specify its size. It default to "emacs" mode, +but if the the environment variable EDITOR is set to "vi" that +mode is chosen. + +ISSUES + +* The mode switching depends on the terminal mode set by the inferior +program. Thus ssh/telnet/screen-type programs will typically be in +raw mode, so rlfe won't be much use, even if remote programs run in +canonical mode. The work-around is to run rlfe on the remote end. + +* Echo supression and prompt recognition are somewhat fragile. +(A protocol so that the o/s tty code can reliably communicate its +state to rlfe could solve this problem, and the previous one.) + +* See the intro to rlfe.c for more notes. + +* Assumes a VT100-compatible terminal, though that could be generalized +if anybody cares. + +* Requires ncurses. + +* It would be useful to integrate rlfe's logic in a terminal emulator. +That would make it easier to reposition the edit position with a mouse, +integrate cut-and-paste with the system clipboard, and more robustly +handle escape sequence and multi-byte characters more robustly. + +AUTHOR + +Per Bothner + +LICENSE + +GPL. diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/config.h.in b/external/gpl3/gdb/dist/readline/examples/rlfe/config.h.in new file mode 100644 index 000000000000..466187469622 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/config.h.in @@ -0,0 +1,375 @@ +/* Copyright 2004 Per Bothner + * Based on config.h from screen-4.0.2. + * Copyright (c) 1993-2000 + * Juergen Weigert (jnweiger@immd4.informatik.uni-erlangen.de) + * Michael Schroeder (mlschroe@immd4.informatik.uni-erlangen.de) + * Copyright (c) 1987 Oliver Laumann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program (see the file COPYING); if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + **************************************************************** + * $Id: config.h.in,v 1.1.1.1 2011/09/24 19:56:57 christos Exp $ FAU + */ + + + + + +/********************************************************************** + * + * User Configuration Section + */ + + +/* + * define PTYMODE if you do not like the default of 0622, which allows + * public write to your pty. + * define PTYGROUP to some numerical group-id if you do not want the + * tty to be in "your" group. + * Note, screen is unable to change mode or group of the pty if it + * is not installed with sufficient privilege. (e.g. set-uid-root) + * define PTYROFS if the /dev/pty devices are mounted on a read-only + * filesystem so screen should not even attempt to set mode or group + * even if running as root (e.g. on TiVo). + */ +#undef PTYMODE +#undef PTYGROUP +#undef PTYROFS + +/* + * If screen is NOT installed set-uid root, screen can provide tty + * security by exclusively locking the ptys. While this keeps other + * users from opening your ptys, it also keeps your own subprocesses + * from being able to open /dev/tty. Define LOCKPTY to add this + * exclusive locking. + */ +#undef LOCKPTY + + +/********************************************************************** + * + * End of User Configuration Section + * + * Rest of this file is modified by 'configure' + * Change at your own risk! + * + */ + +/* + * Some defines to identify special unix variants + */ +#ifndef SVR4 +#undef SVR4 +#endif + +#ifndef _POSIX_SOURCE +#undef _POSIX_SOURCE +#endif + +/* + * Define POSIX if your system supports IEEE Std 1003.1-1988 (POSIX). + */ +#undef POSIX + +/* + * Define TERMIO if you have struct termio instead of struct sgttyb. + * This is usually the case for SVID systems, where BSD uses sgttyb. + * POSIX systems should define this anyway, even though they use + * struct termios. + */ +#undef TERMIO + +/* + * Define CYTERMIO if you have cyrillic termio modes. + */ +#undef CYTERMIO + +/* + * Define TERMINFO if your machine emulates the termcap routines + * with the terminfo database. + * Thus the .screenrc file is parsed for + * the command 'terminfo' and not 'termcap'. + */ +#undef TERMINFO + +/* + * If your library does not define ospeed, define this. + */ +#undef NEED_OSPEED + +/* + * Define SYSV if your machine is SYSV complient (Sys V, HPUX, A/UX) + */ +#ifndef SYSV +#undef SYSV +#endif + +/* + * Define SIGVOID if your signal handlers return void. On older + * systems, signal returns int, but on newer ones, it returns void. + */ +#undef SIGVOID + +/* + * Define USESIGSET if you have sigset for BSD 4.1 reliable signals. + */ +#undef USESIGSET + +/* + * Define SYSVSIGS if signal handlers must be reinstalled after + * they have been called. + */ +#undef SYSVSIGS + +/* + * Define BSDWAIT if your system defines a 'union wait' in + * + * Only allow BSDWAIT i.e. wait3 on nonposix systems, since + * posix implies wait(3) and waitpid(3). vdlinden@fwi.uva.nl + * + */ +#ifndef POSIX +#undef BSDWAIT +#endif + +/* + * On RISCOS we prefer wait2() over wait3(). rouilj@sni-usa.com + */ +#ifdef BSDWAIT +#undef USE_WAIT2 +#endif + +/* + * Define if you have the utempter utmp helper program + */ +#undef HAVE_UTEMPTER + +/* + * If ttyslot() breaks getlogin() by returning indexes to utmp entries + * of type DEAD_PROCESS, then our getlogin() replacement should be + * selected by defining BUGGYGETLOGIN. + */ +#undef BUGGYGETLOGIN + +/* + * If your system has the calls setreuid() and setregid(), + * define HAVE_SETREUID. Otherwise screen will use a forked process to + * safely create output files without retaining any special privileges. + */ +#undef HAVE_SETREUID + +/* + * If your system supports BSD4.4's seteuid() and setegid(), define + * HAVE_SETEUID. + */ +#undef HAVE_SETEUID + +/* + * If you want the "time" command to display the current load average + * define LOADAV. Maybe you must install screen with the needed + * privileges to read /dev/kmem. + * Note that NLIST_ stuff is only checked, when getloadavg() is not available. + */ +#undef LOADAV + +#undef LOADAV_NUM +#undef LOADAV_TYPE +#undef LOADAV_SCALE +#undef LOADAV_GETLOADAVG +#undef LOADAV_UNIX +#undef LOADAV_AVENRUN +#undef LOADAV_USE_NLIST64 + +#undef NLIST_DECLARED +#undef NLIST_STRUCT +#undef NLIST_NAME_UNION + +/* + * If your system has the new format /etc/ttys (like 4.3 BSD) and the + * getttyent(3) library functions, define GETTTYENT. + */ +#undef GETTTYENT + +/* + * Define USEBCOPY if the bcopy/memcpy from your system's C library + * supports the overlapping of source and destination blocks. When + * undefined, screen uses its own (probably slower) version of bcopy(). + * + * SYSV machines may have a working memcpy() -- Oh, this is + * quite unlikely. Tell me if you see one. + * "But then, memmove() should work, if at all available" he thought... + * Boing, never say "works everywhere" unless you checked SCO UNIX. + * Their memove fails the test in the configure script. Sigh. (Juergen) + */ +#undef USEBCOPY +#undef USEMEMCPY +#undef USEMEMMOVE + +/* + * If your system has vsprintf() and requires the use of the macros in + * "varargs.h" to use functions with variable arguments, + * define USEVARARGS. + */ +#undef USEVARARGS + +/* + * If your system has strerror() define this. + */ +#undef HAVE_STRERROR + +/* + * If the select return value doesn't treat a descriptor that is + * usable for reading and writing as two hits, define SELECT_BROKEN. + */ +#undef SELECT_BROKEN + +/* + * Define this if your system supports named pipes. + */ +#undef NAMEDPIPE + +/* + * Define this if your system exits select() immediatly if a pipe is + * opened read-only and no writer has opened it. + */ +#undef BROKEN_PIPE + +/* + * Define this if the unix-domain socket implementation doesn't + * create a socket in the filesystem. + */ +#undef SOCK_NOT_IN_FS + +/* + * If your system has setenv() and unsetenv() define USESETENV + */ +#undef USESETENV + +/* + * If your system does not come with a setenv()/putenv()/getenv() + * functions, you may bring in our own code by defining NEEDPUTENV. + */ +#undef NEEDPUTENV + +/* + * If the passwords are stored in a shadow file and you want the + * builtin lock to work properly, define SHADOWPW. + */ +#undef SHADOWPW + +/* + * If you are on a SYS V machine that restricts filename length to 14 + * characters, you may need to enforce that by setting NAME_MAX to 14 + */ +#undef NAME_MAX /* KEEP_UNDEF_HERE override system value */ +#undef NAME_MAX + +/* + * define HAVE_RENAME if your system has a rename() function + */ +#undef HAVE_RENAME + +/* + * define HAVE__EXIT if your system has the _exit() call. + */ +#undef HAVE__EXIT + +/* + * define HAVE_LSTAT if your system has symlinks and the lstat() call. + */ +#undef HAVE_LSTAT + +/* + * define HAVE_UTIMES if your system has the utimes() call. + */ +#undef HAVE_UTIMES + +/* + * define HAVE_FCHOWN if your system has the fchown() call. + */ +#undef HAVE_FCHOWN + +/* + * define HAVE_FCHMOD if your system has the fchmod() call. + */ +#undef HAVE_FCHMOD + +/* + * define HAVE_VSNPRINTF if your system has vsnprintf() (GNU lib). + */ +#undef HAVE_VSNPRINTF + +/* + * define HAVE_GETCWD if your system has the getcwd() call. + */ +#undef HAVE_GETCWD + +/* + * define HAVE_SETLOCALE if your system has the setlocale() call. + */ +#undef HAVE_SETLOCALE + +/* + * define HAVE_STRFTIME if your system has the strftime() call. + */ +#undef HAVE_STRFTIME + +/* + * define HAVE_NL_LANGINFO if your system has the nl_langinfo() call + * and defines CODESET. + */ +#undef HAVE_NL_LANGINFO + +/* + * Newer versions of Solaris include fdwalk, which can greatly improve + * the startup time of screen; otherwise screen spends a lot of time + * closing file descriptors. + */ +#undef HAVE_FDWALK + +/* + * define HAVE_DEV_PTC if you have a /dev/ptc character special + * device. + */ +#undef HAVE_DEV_PTC + +/* + * define HAVE_SVR4_PTYS if you have a /dev/ptmx character special + * device and support the ptsname(), grantpt(), unlockpt() functions. + */ +#undef HAVE_SVR4_PTYS + +/* + * define HAVE_GETPT if you have the getpt() function. + */ +#undef HAVE_GETPT + +/* + * define HAVE_OPENPTY if your system has the openpty() call. + */ +#undef HAVE_OPENPTY + +/* + * define PTYRANGE0 and or PTYRANGE1 if you want to adapt screen + * to unusual environments. E.g. For SunOs the defaults are "qpr" and + * "0123456789abcdef". For SunOs 4.1.2 + * #define PTYRANGE0 "pqrstuvwxyzPQRST" + * is recommended by Dan Jacobson. + */ +#undef PTYRANGE0 +#undef PTYRANGE1 + +#define USEVARARGS diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/configure b/external/gpl3/gdb/dist/readline/examples/rlfe/configure new file mode 100755 index 000000000000..1f9d38aee997 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/configure @@ -0,0 +1,5258 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. 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If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. 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We remove comments because anyway the quotes in there +# would cause problems or look ugly. +# WARNING: Use '\'' to represent an apostrophe within the trap. +# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug. +trap 'exit_status=$? + # Save into config.log some information that might help in debugging. + { + echo + + cat <<\_ASBOX +## ---------------- ## +## Cache variables. ## +## ---------------- ## +_ASBOX + echo + # The following way of writing the cache mishandles newlines in values, +( + for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + (set) 2>&1 | + case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + sed -n \ + "s/'\''/'\''\\\\'\'''\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p" + ;; #( + *) + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) + echo + + cat <<\_ASBOX +## ----------------- ## +## Output variables. ## +## ----------------- ## +_ASBOX + echo + for ac_var in $ac_subst_vars + do + eval ac_val=\$$ac_var + case $ac_val in + *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + esac + $as_echo "$ac_var='\''$ac_val'\''" + done | sort + echo + + if test -n "$ac_subst_files"; then + cat <<\_ASBOX +## ------------------- ## +## File substitutions. ## +## ------------------- ## +_ASBOX + echo + for ac_var in $ac_subst_files + do + eval ac_val=\$$ac_var + case $ac_val in + *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; + esac + $as_echo "$ac_var='\''$ac_val'\''" + done | sort + echo + fi + + if test -s confdefs.h; then + cat <<\_ASBOX +## ----------- ## +## confdefs.h. ## +## ----------- ## +_ASBOX + echo + cat confdefs.h + echo + fi + test "$ac_signal" != 0 && + $as_echo "$as_me: caught signal $ac_signal" + $as_echo "$as_me: exit $exit_status" + } >&5 + rm -f core *.core core.conftest.* && + rm -f -r conftest* confdefs* conf$$* $ac_clean_files && + exit $exit_status +' 0 +for ac_signal in 1 2 13 15; do + trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal +done +ac_signal=0 + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -f -r conftest* confdefs.h + +$as_echo "/* confdefs.h */" > confdefs.h + +# Predefined preprocessor variables. + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_NAME "$PACKAGE_NAME" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_TARNAME "$PACKAGE_TARNAME" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_VERSION "$PACKAGE_VERSION" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_STRING "$PACKAGE_STRING" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PACKAGE_URL "$PACKAGE_URL" +_ACEOF + + +# Let the site file select an alternate cache file if it wants to. +# Prefer an explicitly selected file to automatically selected ones. +ac_site_file1=NONE +ac_site_file2=NONE +if test -n "$CONFIG_SITE"; then + ac_site_file1=$CONFIG_SITE +elif test "x$prefix" != xNONE; then + ac_site_file1=$prefix/share/config.site + ac_site_file2=$prefix/etc/config.site +else + ac_site_file1=$ac_default_prefix/share/config.site + ac_site_file2=$ac_default_prefix/etc/config.site +fi +for ac_site_file in "$ac_site_file1" "$ac_site_file2" +do + test "x$ac_site_file" = xNONE && continue + if test -r "$ac_site_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 +$as_echo "$as_me: loading site script $ac_site_file" >&6;} + sed 's/^/| /' "$ac_site_file" >&5 + . "$ac_site_file" + fi +done + +if test -r "$cache_file"; then + # Some versions of bash will fail to source /dev/null (special + # files actually), so we avoid doing that. + if test -f "$cache_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +$as_echo "$as_me: loading cache $cache_file" >&6;} + case $cache_file in + [\\/]* | ?:[\\/]* ) . "$cache_file";; + *) . "./$cache_file";; + esac + fi +else + { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5 +$as_echo "$as_me: creating cache $cache_file" >&6;} + >$cache_file +fi + +# Check that the precious variables saved in the cache have kept the same +# value. +ac_cache_corrupted=false +for ac_var in $ac_precious_vars; do + eval ac_old_set=\$ac_cv_env_${ac_var}_set + eval ac_new_set=\$ac_env_${ac_var}_set + eval ac_old_val=\$ac_cv_env_${ac_var}_value + eval ac_new_val=\$ac_env_${ac_var}_value + case $ac_old_set,$ac_new_set in + set,) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,set) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,);; + *) + if test "x$ac_old_val" != "x$ac_new_val"; then + # differences in whitespace do not lead to failure. + ac_old_val_w=`echo x $ac_old_val` + ac_new_val_w=`echo x $ac_new_val` + if test "$ac_old_val_w" != "$ac_new_val_w"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 +$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} + ac_cache_corrupted=: + else + { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 +$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} + eval $ac_var=\$ac_old_val + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 +$as_echo "$as_me: former value: \`$ac_old_val'" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 +$as_echo "$as_me: current value: \`$ac_new_val'" >&2;} + fi;; + esac + # Pass precious variables to config.status. + if test "$ac_new_set" = set; then + case $ac_new_val in + *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; + *) ac_arg=$ac_var=$ac_new_val ;; + esac + case " $ac_configure_args " in + *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. + *) as_fn_append ac_configure_args " '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 +fi +## -------------------- ## +## Main body of script. ## +## -------------------- ## + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + + + +ac_config_headers="$ac_config_headers config.h" + +VERSION=0.4 + + + +old_CFLAGS="$CFLAGS" +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... 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For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +if test $ac_cv_c_compiler_gnu = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC needs -traditional" >&5 +$as_echo_n "checking whether $CC needs -traditional... " >&6; } +if test "${ac_cv_prog_gcc_traditional+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_pattern="Autoconf.*'x'" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +Autoconf TIOCGETP +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then : + ac_cv_prog_gcc_traditional=yes +else + ac_cv_prog_gcc_traditional=no +fi +rm -f conftest* + + + if test $ac_cv_prog_gcc_traditional = no; then + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +Autoconf TCGETA +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then : + ac_cv_prog_gcc_traditional=yes +fi +rm -f conftest* + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_gcc_traditional" >&5 +$as_echo "$ac_cv_prog_gcc_traditional" >&6; } + if test $ac_cv_prog_gcc_traditional = yes; then + CC="$CC -traditional" + fi +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing strerror" >&5 +$as_echo_n "checking for library containing strerror... " >&6; } +if test "${ac_cv_search_strerror+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char strerror (); +int +main () +{ +return strerror (); + ; + return 0; +} +_ACEOF +for ac_lib in '' cposix; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_strerror=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_strerror+set}" = set; then : + break +fi +done +if test "${ac_cv_search_strerror+set}" = set; then : + +else + ac_cv_search_strerror=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_strerror" >&5 +$as_echo "$ac_cv_search_strerror" >&6; } +ac_res=$ac_cv_search_strerror +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + + +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +main(){exit(0);} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + +if test $CC != cc ; then +echo "Your $CC failed - restarting with CC=cc" 1>&6 + +echo "" 1>&6 + +CC=cc +export CC +exec $0 $configure_args +fi + +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +main(){exit(0);} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + exec 5>&2 +eval $ac_link +echo "CC=$CC; CFLAGS=$CFLAGS; LIBS=$LIBS;" 1>&6 + +echo "$ac_compile" 1>&6 + +as_fn_error "Can't run the compiler - sorry" "$LINENO" 5 +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +main() +{ + int __something_strange_(); + __something_strange_(0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + as_fn_error "Your compiler does not set the exit status - sorry" "$LINENO" 5 +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + +for ac_prog in gawk mawk nawk awk +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AWK+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AWK"; then + ac_cv_prog_AWK="$AWK" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AWK="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AWK=$ac_cv_prog_AWK +if test -n "$AWK"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 +$as_echo "$AWK" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$AWK" && break +done + + +if test -f etc/toolcheck; then +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for buggy tools..." >&5 +$as_echo "$as_me: checking for buggy tools..." >&6;} +sh etc/toolcheck 1>&6 +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for System V..." >&5 +$as_echo "$as_me: checking for System V..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +int +main () +{ +int x = SIGCHLD | FNDELAY; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + $as_echo "#define SYSV 1" >>confdefs.h + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for Solaris 2.x..." >&5 +$as_echo "$as_me: checking for Solaris 2.x..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#if defined(SVR4) && defined(sun) + yes +#endif + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then : + LIBS="$LIBS -lsocket -lnsl -lkstat" +fi +rm -f conftest* + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking select..." >&5 +$as_echo "$as_me: checking select..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +select(0, 0, 0, 0, 0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + LIBS="$LIBS -lnet -lnsl" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking select with $LIBS..." >&5 +$as_echo "$as_me: checking select with $LIBS..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +select(0, 0, 0, 0, 0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + as_fn_error "!!! no select - no screen" "$LINENO" 5 +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking select return value..." >&5 +$as_echo "$as_me: checking select return value..." >&6;} +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include +#include + +char *nam = "/tmp/conftest$$"; + +#ifdef NAMEDPIPE + +#ifndef O_NONBLOCK +#define O_NONBLOCK O_NDELAY +#endif +#ifndef S_IFIFO +#define S_IFIFO 0010000 +#endif + + +main() +{ +#ifdef FD_SET + fd_set f; +#else + int f; +#endif + +#ifdef __FreeBSD__ +/* From Andrew A. Chernov (ache@astral.msk.su): + * opening RDWR fifo fails in BSD 4.4, but select return values are + * right. + */ + exit(0); +#endif + (void)alarm(5); +#ifdef POSIX + if (mkfifo(nam, 0777)) +#else + if (mknod(nam, S_IFIFO|0777, 0)) +#endif + exit(1); + close(0); + if (open(nam, O_RDWR | O_NONBLOCK)) + exit(1); + if (write(0, "TEST", 4) == -1) + exit(1); + +#else + +#include +#include +#include + +main() +{ + int s1, s2, l; + struct sockaddr_un a; +#ifdef FD_SET + fd_set f; +#else + int f; +#endif + + (void)alarm(5); + if ((s1 = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) + exit(1); + a.sun_family = AF_UNIX; + strcpy(a.sun_path, nam); + (void) unlink(nam); + if (bind(s1, (struct sockaddr *) &a, strlen(nam)+2) == -1) + exit(1); + if (listen(s1, 2)) + exit(1); + if (fork() == 0) + { + if ((s2 = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) + kill(getppid(), 3); + (void)connect(s2, (struct sockaddr *)&a, strlen(nam) + 2); + if (write(s2, "HELLO", 5) == -1) + kill(getppid(), 3); + exit(0); + } + l = sizeof(a); + close(0); + if (accept(s1, (struct sockaddr *)&a, &l)) + exit(1); +#endif + + +#ifdef FD_SET + FD_SET(0, &f); +#else + f = 1; +#endif + if (select(1, &f, 0, 0, 0) == -1) + exit(1); + if (select(1, &f, &f, 0, 0) != 2) + exit(1); + exit(0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + echo "- select is ok" 1>&6 + +else + echo "- select can't count" 1>&6 + $as_echo "#define SELECT_BROKEN 1" >>confdefs.h + +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for tgetent..." >&5 +$as_echo "$as_me: checking for tgetent..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +tgetent((char *)0, (char *)0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + olibs="$LIBS" +LIBS="-lcurses $olibs" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking libcurses..." >&5 +$as_echo "$as_me: checking libcurses..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + +#ifdef __hpux +__sorry_hpux_libcurses_is_totally_broken_in_10_10(); +#else +tgetent((char *)0, (char *)0); +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + LIBS="-ltermcap $olibs" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking libtermcap..." >&5 +$as_echo "$as_me: checking libtermcap..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +tgetent((char *)0, (char *)0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + LIBS="-ltermlib $olibs" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking libtermlib..." >&5 +$as_echo "$as_me: checking libtermlib..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +tgetent((char *)0, (char *)0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + LIBS="-lncurses $olibs" +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking libncurses..." >&5 +$as_echo "$as_me: checking libncurses..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +tgetent((char *)0, (char *)0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + as_fn_error "!!! no tgetent - no screen" "$LINENO" 5 +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +main() +{ + exit(strcmp(tgoto("%p1%d", 0, 1), "1") ? 0 : 1); +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + echo "- you use the termcap database" 1>&6 + +else + echo "- you use the terminfo database" 1>&6 + $as_echo "#define TERMINFO 1" >>confdefs.h + +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking ospeed..." >&5 +$as_echo "$as_me: checking ospeed..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +extern short ospeed; +int +main () +{ +ospeed=5; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + +else + $as_echo "#define NEED_OSPEED 1" >>confdefs.h + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for /dev/ptc..." >&5 +$as_echo "$as_me: checking for /dev/ptc..." >&6;} +if test -r /dev/ptc; then +$as_echo "#define HAVE_DEV_PTC 1" >>confdefs.h + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SVR4 ptys..." >&5 +$as_echo "$as_me: checking for SVR4 ptys..." >&6;} +sysvr4ptys= +if test -c /dev/ptmx ; then +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +ptsname(0);grantpt(0);unlockpt(0); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + $as_echo "#define HAVE_SVR4_PTYS 1" >>confdefs.h + +sysvr4ptys=1 +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi + +for ac_func in getpt +do : + ac_fn_c_check_func "$LINENO" "getpt" "ac_cv_func_getpt" +if test "x$ac_cv_func_getpt" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_GETPT 1 +_ACEOF + +fi +done + + +if test -z "$sysvr4ptys"; then +for ac_func in openpty +do : + ac_fn_c_check_func "$LINENO" "openpty" "ac_cv_func_openpty" +if test "x$ac_cv_func_openpty" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_OPENPTY 1 +_ACEOF + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for openpty in -lutil" >&5 +$as_echo_n "checking for openpty in -lutil... " >&6; } +if test "${ac_cv_lib_util_openpty+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lutil $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char openpty (); +int +main () +{ +return openpty (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_util_openpty=yes +else + ac_cv_lib_util_openpty=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_util_openpty" >&5 +$as_echo "$ac_cv_lib_util_openpty" >&6; } +if test "x$ac_cv_lib_util_openpty" = x""yes; then : + $as_echo "#define HAVE_OPENPTY 1" >>confdefs.h + LIBS="$LIBS -lutil" +fi + +fi +done + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ptyranges..." >&5 +$as_echo "$as_me: checking for ptyranges..." >&6;} +if test -d /dev/ptym ; then +pdir='/dev/ptym' +else +pdir='/dev' +fi +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef M_UNIX + yes; +#endif + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then : + ptys=`echo /dev/ptyp??` +else + ptys=`echo $pdir/pty??` +fi +rm -f conftest* + +if test "$ptys" != "$pdir/pty??" ; then +p0=`echo $ptys | tr ' ' '\012' | sed -e 's/^.*\(.\).$/\1/g' | sort -u | tr -d '\012'` +p1=`echo $ptys | tr ' ' '\012' | sed -e 's/^.*\(.\)$/\1/g' | sort -u | tr -d '\012'` +cat >>confdefs.h <<_ACEOF +#define PTYRANGE0 "$p0" +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PTYRANGE1 "$p1" +_ACEOF + +fi + + +# Check whether --with-pty-mode was given. +if test "${with_pty_mode+set}" = set; then : + withval=$with_pty_mode; ptymode="${withval}" +fi + + +# Check whether --with-pty-group was given. +if test "${with_pty_group+set}" = set; then : + withval=$with_pty_group; ptygrp="${withval}" +fi + +test -n "$ptymode" || ptymode=0620 +if test -n "$ptygrp" ; then +cat >>confdefs.h <<_ACEOF +#define PTYMODE $ptymode +_ACEOF + +cat >>confdefs.h <<_ACEOF +#define PTYGROUP $ptygrp +_ACEOF + +else + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking default tty permissions/group..." >&5 +$as_echo "$as_me: checking default tty permissions/group..." >&6;} +rm -f conftest_grp +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include +#include +main() +{ + struct stat sb; + char *x,*ttyname(); + int om, m; + FILE *fp; + + if (!(x = ttyname(0))) exit(1); + if (stat(x, &sb)) exit(1); + om = sb.st_mode; + if (om & 002) exit(0); + m = system("mesg y"); + if (m == -1 || m == 127) exit(1); + if (stat(x, &sb)) exit(1); + m = sb.st_mode; + if (chmod(x, om)) exit(1); + if (m & 002) exit(0); + if (sb.st_gid == getgid()) exit(1); + if (!(fp=fopen("conftest_grp", "w"))) + exit(1); + fprintf(fp, "%d\n", sb.st_gid); + fclose(fp); + exit(0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + + if test -f conftest_grp; then + ptygrp=`cat conftest_grp` + echo "- pty mode: $ptymode, group: $ptygrp" 1>&6 + + cat >>confdefs.h <<_ACEOF +#define PTYMODE $ptymode +_ACEOF + + cat >>confdefs.h <<_ACEOF +#define PTYGROUP $ptygrp +_ACEOF + + else + echo "- ptys are world accessable" 1>&6 + + fi + +else + + WRITEPATH='' + XTERMPATH='' + # Extract the first word of "write", so it can be a program name with args. +set dummy write; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_WRITEPATH+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $WRITEPATH in + [\\/]* | ?:[\\/]*) + ac_cv_path_WRITEPATH="$WRITEPATH" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_WRITEPATH="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + ;; +esac +fi +WRITEPATH=$ac_cv_path_WRITEPATH +if test -n "$WRITEPATH"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $WRITEPATH" >&5 +$as_echo "$WRITEPATH" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + # Extract the first word of "xterm", so it can be a program name with args. +set dummy xterm; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_XTERMPATH+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $XTERMPATH in + [\\/]* | ?:[\\/]*) + ac_cv_path_XTERMPATH="$XTERMPATH" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_XTERMPATH="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + ;; +esac +fi +XTERMPATH=$ac_cv_path_XTERMPATH +if test -n "$XTERMPATH"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $XTERMPATH" >&5 +$as_echo "$XTERMPATH" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + found= + if test -n "$WRITEPATH$XTERMPATH"; then + findfollow= + lsfollow= + found=`find $WRITEPATH $XTERMPATH -follow -print 2>/dev/null` + if test -n "$found"; then + findfollow=-follow + lsfollow=L + fi + if test -n "$XTERMPATH"; then + ptygrpn=`ls -l$lsfollow $XTERMPATH | sed -n -e 1p | $AWK '{print $4}'` + if test tty != "$ptygrpn"; then + XTERMPATH= + fi + fi + fi + if test -n "$WRITEPATH$XTERMPATH"; then + found=`find $WRITEPATH $XTERMPATH $findfollow -perm -2000 -print` + if test -n "$found"; then + ptygrp=`ls -ln$lsfollow $found | sed -n -e 1p | $AWK '{print $4}'` + echo "- pty mode: $ptymode, group: $ptygrp" 1>&6 + + cat >>confdefs.h <<_ACEOF +#define PTYMODE $ptymode +_ACEOF + + cat >>confdefs.h <<_ACEOF +#define PTYGROUP $ptygrp +_ACEOF + + else + echo "- ptys are world accessable" 1>&6 + + fi + else + echo "- can't determine - assume ptys are world accessable" 1>&6 + + fi + + +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +rm -f conftest_grp +fi + +if test -n "$posix" ; then + +echo "assuming posix signal definition" 1>&6 + +$as_echo "#define SIGVOID 1" >>confdefs.h + + +else + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers..." >&5 +$as_echo "$as_me: checking return type of signal handlers..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#ifdef signal +#undef signal +#endif +extern void (*signal ()) (); +int +main () +{ +int i; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + $as_echo "#define SIGVOID 1" >>confdefs.h + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking sigset..." >&5 +$as_echo "$as_me: checking sigset..." >&6;} +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include + +int +main () +{ + +#ifdef SIGVOID +sigset(0, (void (*)())0); +#else +sigset(0, (int (*)())0); +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + $as_echo "#define USESIGSET 1" >>confdefs.h + +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking signal implementation..." >&5 +$as_echo "$as_me: checking signal implementation..." >&6;} +if test "$cross_compiling" = yes; then : + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run test program while cross compiling +See \`config.log' for more details." "$LINENO" 5; } +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include +#include + +#ifndef SIGCLD +#define SIGCLD SIGCHLD +#endif +#ifdef USESIGSET +#define signal sigset +#endif + +int got; + +#ifdef SIGVOID +void +#endif +hand() +{ + got++; +} + +main() +{ + /* on hpux we use sigvec to get bsd signals */ +#ifdef __hpux + (void)signal(SIGCLD, hand); + kill(getpid(), SIGCLD); + kill(getpid(), SIGCLD); + if (got < 2) + exit(1); +#endif + exit(0); +} + +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + $as_echo "#define SYSVSIGS 1" >>confdefs.h + +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + +fi + +ac_config_files="$ac_config_files Makefile" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. 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[TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +AWK='$AWK' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. 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Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS " +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. Generated by config.status. */ + configure_input='Generated from '` + $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' + `' by configure.' + if test x"$ac_file" != x-; then + configure_input="$ac_file. $configure_input" + { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 +$as_echo "$as_me: creating $ac_file" >&6;} + fi + # Neutralize special characters interpreted by sed in replacement strings. + case $configure_input in #( + *\&* | *\|* | *\\* ) + ac_sed_conf_input=`$as_echo "$configure_input" | + sed 's/[\\\\&|]/\\\\&/g'`;; #( + *) ac_sed_conf_input=$configure_input;; + esac + + case $ac_tag in + *:-:* | *:-) cat >"$tmp/stdin" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 ;; + esac + ;; + esac + + ac_dir=`$as_dirname -- "$ac_file" || +$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$ac_file" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + as_dir="$ac_dir"; as_fn_mkdir_p + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + + case $ac_mode in + :F) + # + # CONFIG_FILE + # + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# If the template does not know about datarootdir, expand it. +# FIXME: This hack should be removed a few years after 2.60. +ac_datarootdir_hack=; ac_datarootdir_seen= +ac_sed_dataroot=' +/datarootdir/ { + p + q +} +/@datadir@/p +/@docdir@/p +/@infodir@/p +/@localedir@/p +/@mandir@/p' +case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in +*datarootdir*) ac_datarootdir_seen=yes;; +*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 +$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_datarootdir_hack=' + s&@datadir@&$datadir&g + s&@docdir@&$docdir&g + s&@infodir@&$infodir&g + s&@localedir@&$localedir&g + s&@mandir@&$mandir&g + s&\\\${datarootdir}&$datarootdir&g' ;; +esac +_ACEOF + +# Neutralize VPATH when `$srcdir' = `.'. +# Shell code in configure.ac might set extrasub. +# FIXME: do we really want to maintain this feature? +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_sed_extra="$ac_vpsub +$extrasub +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +:t +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b +s|@configure_input@|$ac_sed_conf_input|;t t +s&@top_builddir@&$ac_top_builddir_sub&;t t +s&@top_build_prefix@&$ac_top_build_prefix&;t t +s&@srcdir@&$ac_srcdir&;t t +s&@abs_srcdir@&$ac_abs_srcdir&;t t +s&@top_srcdir@&$ac_top_srcdir&;t t +s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t +s&@builddir@&$ac_builddir&;t t +s&@abs_builddir@&$ac_abs_builddir&;t t +s&@abs_top_builddir@&$ac_abs_top_builddir&;t t +$ac_datarootdir_hack +" +eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + +test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && + { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } && + { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } && + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + + + esac + +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/configure.in b/external/gpl3/gdb/dist/readline/examples/rlfe/configure.in new file mode 100644 index 000000000000..2bcdb1fccc39 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/configure.in @@ -0,0 +1,440 @@ +dnl Process this file with autoconf to produce a configure script. + +m4_include([../../../config/override.m4]) + +AC_INIT(rlfe.c) +AC_CONFIG_HEADER(config.h) +VERSION=0.4 +AC_SUBST(VERSION) + +dnl +dnl Define some useful macros +dnl +AC_DEFUN([AC_PROGRAM_SOURCE], +[AC_REQUIRE([AC_PROG_CPP])AC_PROVIDE([$0])cat > conftest.c <&5 | sed -e '1,/_CUT_HERE_/d' -e 's/ //g' > conftest.out" +. ./conftest.out +rm -f conftest* +])dnl +dnl +define(AC_NOTE, +[echo "$1" 1>&AC_FD_MSG +])dnl + +old_CFLAGS="$CFLAGS" +AC_PROG_CC +AC_PROG_CPP +AC_PROG_GCC_TRADITIONAL +AC_ISC_POSIX + +AC_TRY_RUN(main(){exit(0);},,[ +if test $CC != cc ; then +AC_NOTE(Your $CC failed - restarting with CC=cc) +AC_NOTE() +CC=cc +export CC +exec $0 $configure_args +fi +]) + +AC_TRY_RUN(main(){exit(0);},, +exec 5>&2 +eval $ac_link +AC_NOTE(CC=$CC; CFLAGS=$CFLAGS; LIBS=$LIBS;) +AC_NOTE($ac_compile) +AC_MSG_ERROR(Can't run the compiler - sorry)) + +AC_TRY_RUN([ +main() +{ + int __something_strange_(); + __something_strange_(0); +} +],AC_MSG_ERROR(Your compiler does not set the exit status - sorry)) + +AC_PROG_AWK + +if test -f etc/toolcheck; then +AC_CHECKING(for buggy tools) +sh etc/toolcheck 1>&AC_FD_MSG +fi + +dnl +dnl **** special unix variants **** +dnl + +AC_CHECKING(for System V) +AC_TRY_COMPILE( +[#include +#include +#include ], [int x = SIGCHLD | FNDELAY;], , AC_DEFINE(SYSV)) + +AC_CHECKING(for Solaris 2.x) +AC_EGREP_CPP(yes, +[#if defined(SVR4) && defined(sun) + yes +#endif +], LIBS="$LIBS -lsocket -lnsl -lkstat") + +dnl +dnl **** select() **** +dnl + +AC_CHECKING(select) +AC_TRY_LINK(,[select(0, 0, 0, 0, 0);],, +LIBS="$LIBS -lnet -lnsl" +AC_CHECKING(select with $LIBS) +AC_TRY_LINK(,[select(0, 0, 0, 0, 0);],, +AC_MSG_ERROR(!!! no select - no screen)) +) +dnl +dnl **** check the select implementation **** +dnl + +AC_CHECKING(select return value) +AC_TRY_RUN([ +#include +#include +#include + +char *nam = "/tmp/conftest$$"; + +#ifdef NAMEDPIPE + +#ifndef O_NONBLOCK +#define O_NONBLOCK O_NDELAY +#endif +#ifndef S_IFIFO +#define S_IFIFO 0010000 +#endif + + +main() +{ +#ifdef FD_SET + fd_set f; +#else + int f; +#endif + +#ifdef __FreeBSD__ +/* From Andrew A. Chernov (ache@astral.msk.su): + * opening RDWR fifo fails in BSD 4.4, but select return values are + * right. + */ + exit(0); +#endif + (void)alarm(5); +#ifdef POSIX + if (mkfifo(nam, 0777)) +#else + if (mknod(nam, S_IFIFO|0777, 0)) +#endif + exit(1); + close(0); + if (open(nam, O_RDWR | O_NONBLOCK)) + exit(1); + if (write(0, "TEST", 4) == -1) + exit(1); + +#else + +#include +#include +#include + +main() +{ + int s1, s2, l; + struct sockaddr_un a; +#ifdef FD_SET + fd_set f; +#else + int f; +#endif + + (void)alarm(5); + if ((s1 = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) + exit(1); + a.sun_family = AF_UNIX; + strcpy(a.sun_path, nam); + (void) unlink(nam); + if (bind(s1, (struct sockaddr *) &a, strlen(nam)+2) == -1) + exit(1); + if (listen(s1, 2)) + exit(1); + if (fork() == 0) + { + if ((s2 = socket(AF_UNIX, SOCK_STREAM, 0)) == -1) + kill(getppid(), 3); + (void)connect(s2, (struct sockaddr *)&a, strlen(nam) + 2); + if (write(s2, "HELLO", 5) == -1) + kill(getppid(), 3); + exit(0); + } + l = sizeof(a); + close(0); + if (accept(s1, (struct sockaddr *)&a, &l)) + exit(1); +#endif + + +#ifdef FD_SET + FD_SET(0, &f); +#else + f = 1; +#endif + if (select(1, &f, 0, 0, 0) == -1) + exit(1); + if (select(1, &f, &f, 0, 0) != 2) + exit(1); + exit(0); +} +],AC_NOTE(- select is ok), +AC_NOTE(- select can't count) AC_DEFINE(SELECT_BROKEN)) + +dnl +dnl **** termcap or terminfo **** +dnl +AC_CHECKING(for tgetent) +AC_TRY_LINK(,tgetent((char *)0, (char *)0);,, +olibs="$LIBS" +LIBS="-lcurses $olibs" +AC_CHECKING(libcurses) +AC_TRY_LINK(,[ +#ifdef __hpux +__sorry_hpux_libcurses_is_totally_broken_in_10_10(); +#else +tgetent((char *)0, (char *)0); +#endif +],, +LIBS="-ltermcap $olibs" +AC_CHECKING(libtermcap) +AC_TRY_LINK(,tgetent((char *)0, (char *)0);,, +LIBS="-ltermlib $olibs" +AC_CHECKING(libtermlib) +AC_TRY_LINK(,tgetent((char *)0, (char *)0);,, +LIBS="-lncurses $olibs" +AC_CHECKING(libncurses) +AC_TRY_LINK(,tgetent((char *)0, (char *)0);,, +AC_MSG_ERROR(!!! no tgetent - no screen)))))) + +AC_TRY_RUN([ +main() +{ + exit(strcmp(tgoto("%p1%d", 0, 1), "1") ? 0 : 1); +}], AC_NOTE(- you use the termcap database), +AC_NOTE(- you use the terminfo database) AC_DEFINE(TERMINFO)) +AC_CHECKING(ospeed) +AC_TRY_LINK(extern short ospeed;,ospeed=5;,,AC_DEFINE(NEED_OSPEED)) + +dnl +dnl **** PTY specific things **** +dnl +AC_CHECKING(for /dev/ptc) +if test -r /dev/ptc; then +AC_DEFINE(HAVE_DEV_PTC) +fi + +AC_CHECKING(for SVR4 ptys) +sysvr4ptys= +if test -c /dev/ptmx ; then +AC_TRY_LINK([],[ptsname(0);grantpt(0);unlockpt(0);],[AC_DEFINE(HAVE_SVR4_PTYS) +sysvr4ptys=1]) +fi + +AC_CHECK_FUNCS(getpt) + +dnl check for openpty() +if test -z "$sysvr4ptys"; then +AC_CHECK_FUNCS(openpty,, +[AC_CHECK_LIB(util,openpty, [AC_DEFINE(HAVE_OPENPTY)] [LIBS="$LIBS -lutil"])]) +fi + +AC_CHECKING(for ptyranges) +if test -d /dev/ptym ; then +pdir='/dev/ptym' +else +pdir='/dev' +fi +dnl SCO uses ptyp%d +AC_EGREP_CPP(yes, +[#ifdef M_UNIX + yes; +#endif +], ptys=`echo /dev/ptyp??`, ptys=`echo $pdir/pty??`) +dnl if test -c /dev/ptyp19; then +dnl ptys=`echo /dev/ptyp??` +dnl else +dnl ptys=`echo $pdir/pty??` +dnl fi +if test "$ptys" != "$pdir/pty??" ; then +p0=`echo $ptys | tr ' ' '\012' | sed -e 's/^.*\(.\).$/\1/g' | sort -u | tr -d '\012'` +p1=`echo $ptys | tr ' ' '\012' | sed -e 's/^.*\(.\)$/\1/g' | sort -u | tr -d '\012'` +AC_DEFINE_UNQUOTED(PTYRANGE0,"$p0") +AC_DEFINE_UNQUOTED(PTYRANGE1,"$p1") +fi + +dnl **** pty mode/group handling **** +dnl +dnl support provided by Luke Mewburn , 931222 +AC_ARG_WITH(pty-mode, [ --with-pty-mode=mode default mode for ptys], [ ptymode="${withval}" ]) +AC_ARG_WITH(pty-group, [ --with-pty-group=group default group for ptys], [ ptygrp="${withval}" ]) +test -n "$ptymode" || ptymode=0620 +if test -n "$ptygrp" ; then +AC_DEFINE_UNQUOTED(PTYMODE, $ptymode) +AC_DEFINE_UNQUOTED(PTYGROUP,$ptygrp) +else + +AC_CHECKING(default tty permissions/group) +rm -f conftest_grp +AC_TRY_RUN([ +#include +#include +#include +main() +{ + struct stat sb; + char *x,*ttyname(); + int om, m; + FILE *fp; + + if (!(x = ttyname(0))) exit(1); + if (stat(x, &sb)) exit(1); + om = sb.st_mode; + if (om & 002) exit(0); + m = system("mesg y"); + if (m == -1 || m == 127) exit(1); + if (stat(x, &sb)) exit(1); + m = sb.st_mode; + if (chmod(x, om)) exit(1); + if (m & 002) exit(0); + if (sb.st_gid == getgid()) exit(1); + if (!(fp=fopen("conftest_grp", "w"))) + exit(1); + fprintf(fp, "%d\n", sb.st_gid); + fclose(fp); + exit(0); +} +],[ + if test -f conftest_grp; then + ptygrp=`cat conftest_grp` + AC_NOTE([- pty mode: $ptymode, group: $ptygrp]) + AC_DEFINE_UNQUOTED(PTYMODE, $ptymode) + AC_DEFINE_UNQUOTED(PTYGROUP,$ptygrp) + else + AC_NOTE(- ptys are world accessable) + fi +],[ + WRITEPATH='' + XTERMPATH='' + AC_PATH_PROG(WRITEPATH, write) + AC_PATH_PROG(XTERMPATH, xterm) + found= + if test -n "$WRITEPATH$XTERMPATH"; then + findfollow= + lsfollow= + found=`find $WRITEPATH $XTERMPATH -follow -print 2>/dev/null` + if test -n "$found"; then + findfollow=-follow + lsfollow=L + fi + if test -n "$XTERMPATH"; then + ptygrpn=`ls -l$lsfollow $XTERMPATH | sed -n -e 1p | $AWK '{print $4}'` + if test tty != "$ptygrpn"; then + XTERMPATH= + fi + fi + fi + if test -n "$WRITEPATH$XTERMPATH"; then + found=`find $WRITEPATH $XTERMPATH $findfollow -perm -2000 -print` + if test -n "$found"; then + ptygrp=`ls -ln$lsfollow $found | sed -n -e 1p | $AWK '{print $4}'` + AC_NOTE([- pty mode: $ptymode, group: $ptygrp]) + AC_DEFINE_UNQUOTED(PTYMODE, $ptymode) + AC_DEFINE_UNQUOTED(PTYGROUP,$ptygrp) + else + AC_NOTE(- ptys are world accessable) + fi + else + AC_NOTE(- can't determine - assume ptys are world accessable) + fi + ] +) +rm -f conftest_grp +fi + +dnl +dnl **** signal handling **** +dnl +if test -n "$posix" ; then + +dnl POSIX has reliable signals with void return type. +AC_NOTE(assuming posix signal definition) +AC_DEFINE(SIGVOID) + +else + +AC_CHECKING(return type of signal handlers) +AC_TRY_COMPILE( +[#include +#include +#ifdef signal +#undef signal +#endif +extern void (*signal ()) ();], [int i;], AC_DEFINE(SIGVOID)) +AC_CHECKING(sigset) +AC_TRY_LINK([ +#include +#include +],[ +#ifdef SIGVOID +sigset(0, (void (*)())0); +#else +sigset(0, (int (*)())0); +#endif +], AC_DEFINE(USESIGSET)) +AC_CHECKING(signal implementation) +AC_TRY_RUN([ +#include +#include + +#ifndef SIGCLD +#define SIGCLD SIGCHLD +#endif +#ifdef USESIGSET +#define signal sigset +#endif + +int got; + +#ifdef SIGVOID +void +#endif +hand() +{ + got++; +} + +main() +{ + /* on hpux we use sigvec to get bsd signals */ +#ifdef __hpux + (void)signal(SIGCLD, hand); + kill(getpid(), SIGCLD); + kill(getpid(), SIGCLD); + if (got < 2) + exit(1); +#endif + exit(0); +} +],,AC_DEFINE(SYSVSIGS)) + +fi + +AC_OUTPUT(Makefile) diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/extern.h b/external/gpl3/gdb/dist/readline/examples/rlfe/extern.h new file mode 100644 index 000000000000..15d3ace8df1f --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/extern.h @@ -0,0 +1,33 @@ +/* Copyright (c) 1993-2002 + * Juergen Weigert (jnweiger@immd4.informatik.uni-erlangen.de) + * Michael Schroeder (mlschroe@immd4.informatik.uni-erlangen.de) + * Copyright (c) 1987 Oliver Laumann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program (see the file COPYING); if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + **************************************************************** + * $Id: extern.h,v 1.1.1.1 2011/09/24 19:57:00 christos Exp $ FAU + */ + +#if !defined(__GNUC__) || __GNUC__ < 2 +#undef __attribute__ +#define __attribute__(x) +#endif + +/* pty.c */ +extern int OpenPTY __P((char **)); +extern void InitPTY __P((int)); + diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/os.h b/external/gpl3/gdb/dist/readline/examples/rlfe/os.h new file mode 100644 index 000000000000..7a9fabe76c0b --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/os.h @@ -0,0 +1,530 @@ +/* Copyright (c) 1993-2002 + * Juergen Weigert (jnweiger@immd4.informatik.uni-erlangen.de) + * Michael Schroeder (mlschroe@immd4.informatik.uni-erlangen.de) + * Copyright (c) 1987 Oliver Laumann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program (see the file COPYING); if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + **************************************************************** + * $Id: os.h,v 1.1.1.1 2011/09/24 19:57:00 christos Exp $ FAU + */ + +#include +#include + +#include + +/* In strict ANSI mode, HP-UX machines define __hpux but not hpux */ +#if defined(__hpux) && !defined(hpux) +# define hpux +#endif + +#if defined(__bsdi__) || defined(__386BSD__) || defined(_CX_UX) || defined(hpux) || defined(_IBMR2) || defined(linux) +# include +#endif /* __bsdi__ || __386BSD__ || _CX_UX || hpux || _IBMR2 || linux */ + +#ifdef ISC +# ifdef ENAMETOOLONG +# undef ENAMETOOLONG +# endif +# ifdef ENOTEMPTY +# undef ENOTEMPTY +# endif +# include +# include +#endif + +#ifdef sun +# define getpgrp __getpgrp +# define exit __exit +#endif +#ifdef POSIX +# include +# if defined(__STDC__) +# include +# endif /* __STDC__ */ +#endif /* POSIX */ +#ifdef sun +# undef getpgrp +# undef exit +#endif /* sun */ + +#ifndef linux /* all done in */ +extern int errno; +#endif /* linux */ +#ifndef HAVE_STRERROR +/* No macros, please */ +#undef strerror +#endif + +#if !defined(SYSV) && !defined(linux) +# ifdef NEWSOS +# define strlen ___strlen___ +# include +# undef strlen +# else /* NEWSOS */ +# include +# endif /* NEWSOS */ +#else /* SYSV */ +# if defined(SVR4) || defined(NEWSOS) +# define strlen ___strlen___ +# include +# undef strlen +# if !defined(NEWSOS) && !defined(__hpux) + extern size_t strlen(const char *); +# endif +# else /* SVR4 */ +# include +# endif /* SVR4 */ +#endif /* SYSV */ + +#ifdef USEVARARGS +# if defined(__STDC__) +# include +# define VA_LIST(var) va_list var; +# define VA_DOTS ... +# define VA_DECL +# define VA_START(ap, fmt) va_start(ap, fmt) +# define VA_ARGS(ap) ap +# define VA_END(ap) va_end(ap) +# else +# include +# define VA_LIST(var) va_list var; +# define VA_DOTS va_alist +# define VA_DECL va_dcl +# define VA_START(ap, fmt) va_start(ap) +# define VA_ARGS(ap) ap +# define VA_END(ap) va_end(ap) +# endif +#else +# define VA_LIST(var) +# define VA_DOTS p1, p2, p3, p4, p5, p6 +# define VA_DECL unsigned long VA_DOTS; +# define VA_START(ap, fmt) +# define VA_ARGS(ap) VA_DOTS +# define VA_END(ap) +# undef vsnprintf +# define vsnprintf xsnprintf +#endif + +#if !defined(sun) && !defined(B43) && !defined(ISC) && !defined(pyr) && !defined(_CX_UX) +# include +#endif +#include + +#ifdef M_UNIX /* SCO */ +# include +# include +# define ftruncate(fd, s) chsize(fd, s) +#endif + +#ifdef SYSV +# define index strchr +# define rindex strrchr +# define bzero(poi,len) memset(poi,0,len) +# define bcmp memcmp +# define killpg(pgrp,sig) kill( -(pgrp), sig) +#endif + +#ifndef HAVE_GETCWD +# define getcwd(b,l) getwd(b) +#endif + +#ifndef USEBCOPY +# ifdef USEMEMMOVE +# define bcopy(s,d,len) memmove(d,s,len) +# else +# ifdef USEMEMCPY +# define bcopy(s,d,len) memcpy(d,s,len) +# else +# define NEED_OWN_BCOPY +# define bcopy xbcopy +# endif +# endif +#endif + +#ifdef hpux +# define setreuid(ruid, euid) setresuid(ruid, euid, -1) +# define setregid(rgid, egid) setresgid(rgid, egid, -1) +#endif + +#if defined(HAVE_SETEUID) || defined(HAVE_SETREUID) +# define USE_SETEUID +#endif + +#if !defined(HAVE__EXIT) && !defined(_exit) +#define _exit(x) exit(x) +#endif + +#ifndef HAVE_UTIMES +# define utimes utime +#endif + +#ifdef BUILTIN_TELNET +# include +# include +#endif + +#if defined(USE_LOCALE) && (!defined(HAVE_SETLOCALE) || !defined(HAVE_STRFTIME)) +# undef USE_LOCALE +#endif + +/***************************************************************** + * terminal handling + */ + +#ifdef POSIX +# include +# ifdef hpux +# include +# endif /* hpux */ +# ifdef NCCS +# define MAXCC NCCS +# else +# define MAXCC 256 +# endif +#else /* POSIX */ +# ifdef TERMIO +# include +# ifdef NCC +# define MAXCC NCC +# else +# define MAXCC 256 +# endif +# ifdef CYTERMIO +# include +# endif +# else /* TERMIO */ +# include +# endif /* TERMIO */ +#endif /* POSIX */ + +#ifndef VDISABLE +# ifdef _POSIX_VDISABLE +# define VDISABLE _POSIX_VDISABLE +# else +# define VDISABLE 0377 +# endif /* _POSIX_VDISABLE */ +#endif /* !VDISABLE */ + + +/* on sgi, regardless of the stream head's read mode (RNORM/RMSGN/RMSGD) + * TIOCPKT mode causes data loss if our buffer is too small (IOSIZE) + * to hold the whole packet at first read(). + * (Marc Boucher) + * + * matthew green: + * TIOCPKT is broken on dgux 5.4.1 generic AViiON mc88100 + * + * Joe Traister: On AIX4, programs like irc won't work if screen + * uses TIOCPKT (select fails to return on pty read). + */ +#if defined(sgi) || defined(DGUX) || defined(_IBMR2) +# undef TIOCPKT +#endif + +/* linux ncurses is broken, we have to use our own tputs */ +#if defined(linux) && defined(TERMINFO) +# define tputs xtputs +#endif + +/* Alexandre Oliva: SVR4 style ptys don't work with osf */ +#ifdef __osf__ +# undef HAVE_SVR4_PTYS +#endif + +/***************************************************************** + * utmp handling + */ + +#ifdef GETUTENT + typedef char *slot_t; +#else + typedef int slot_t; +#endif + +#if defined(UTMPOK) || defined(BUGGYGETLOGIN) +# if defined(SVR4) && !defined(DGUX) && !defined(__hpux) && !defined(linux) +# include +# define UTMPFILE UTMPX_FILE +# define utmp utmpx +# define getutent getutxent +# define getutid getutxid +# define getutline getutxline +# define pututline pututxline +# define setutent setutxent +# define endutent endutxent +# define ut_time ut_xtime +# else /* SVR4 */ +# include +# endif /* SVR4 */ +# ifdef apollo + /* + * We don't have GETUTENT, so we dig into utmp ourselves. + * But we save the permanent filedescriptor and + * open utmp just when we need to. + * This code supports an unsorted utmp. jw. + */ +# define UTNOKEEP +# endif /* apollo */ + +# ifndef UTMPFILE +# ifdef UTMP_FILE +# define UTMPFILE UTMP_FILE +# else +# ifdef _PATH_UTMP +# define UTMPFILE _PATH_UTMP +# else +# define UTMPFILE "/etc/utmp" +# endif /* _PATH_UTMP */ +# endif +# endif + +#endif /* UTMPOK || BUGGYGETLOGIN */ + +#if !defined(UTMPOK) && defined(USRLIMIT) +# undef USRLIMIT +#endif + +#ifdef LOGOUTOK +# ifndef LOGINDEFAULT +# define LOGINDEFAULT 0 +# endif +#else +# ifdef LOGINDEFAULT +# undef LOGINDEFAULT +# endif +# define LOGINDEFAULT 1 +#endif + + +/***************************************************************** + * file stuff + */ + +#ifndef F_OK +#define F_OK 0 +#endif +#ifndef X_OK +#define X_OK 1 +#endif +#ifndef W_OK +#define W_OK 2 +#endif +#ifndef R_OK +#define R_OK 4 +#endif + +#ifndef S_IFIFO +#define S_IFIFO 0010000 +#endif +#ifndef S_IREAD +#define S_IREAD 0000400 +#endif +#ifndef S_IWRITE +#define S_IWRITE 0000200 +#endif +#ifndef S_IEXEC +#define S_IEXEC 0000100 +#endif + +#if defined(S_IFIFO) && defined(S_IFMT) && !defined(S_ISFIFO) +#define S_ISFIFO(mode) (((mode) & S_IFMT) == S_IFIFO) +#endif +#if defined(S_IFSOCK) && defined(S_IFMT) && !defined(S_ISSOCK) +#define S_ISSOCK(mode) (((mode) & S_IFMT) == S_IFSOCK) +#endif +#if defined(S_IFCHR) && defined(S_IFMT) && !defined(S_ISCHR) +#define S_ISCHR(mode) (((mode) & S_IFMT) == S_IFCHR) +#endif +#if defined(S_IFDIR) && defined(S_IFMT) && !defined(S_ISDIR) +#define S_ISDIR(mode) (((mode) & S_IFMT) == S_IFDIR) +#endif +#if defined(S_IFLNK) && defined(S_IFMT) && !defined(S_ISLNK) +#define S_ISLNK(mode) (((mode) & S_IFMT) == S_IFLNK) +#endif + +/* + * SunOS 4.1.3: `man 2V open' has only one line that mentions O_NOBLOCK: + * + * O_NONBLOCK Same as O_NDELAY above. + * + * on the very same SunOS 4.1.3, I traced the open system call and found + * that an open("/dev/ttyy08", O_RDWR|O_NONBLOCK|O_NOCTTY) was blocked, + * whereas open("/dev/ttyy08", O_RDWR|O_NDELAY |O_NOCTTY) went through. + * + * For this simple reason I now favour O_NDELAY. jw. 4.5.95 + */ +#if defined(sun) && !defined(SVR4) +# undef O_NONBLOCK +#endif + +#if !defined(O_NONBLOCK) && defined(O_NDELAY) +# define O_NONBLOCK O_NDELAY +#endif + +#if !defined(FNBLOCK) && defined(FNONBLOCK) +# define FNBLOCK FNONBLOCK +#endif +#if !defined(FNBLOCK) && defined(FNDELAY) +# define FNBLOCK FNDELAY +#endif +#if !defined(FNBLOCK) && defined(O_NONBLOCK) +# define FNBLOCK O_NONBLOCK +#endif + +#ifndef POSIX +#undef mkfifo +#define mkfifo(n,m) mknod(n,S_IFIFO|(m),0) +#endif + +#if !defined(HAVE_LSTAT) && !defined(lstat) +# define lstat stat +#endif + +/***************************************************************** + * signal handling + */ + +#ifdef SIGVOID +# define SIGRETURN +# define sigret_t void +#else +# define SIGRETURN return 0; +# define sigret_t int +#endif + +/* Geeeee, reverse it? */ +#if defined(SVR4) || (defined(SYSV) && defined(ISC)) || defined(_AIX) || defined(linux) || defined(ultrix) || defined(__386BSD__) || defined(__bsdi__) || defined(POSIX) || defined(NeXT) +# define SIGHASARG +#endif + +#ifdef SIGHASARG +# define SIGPROTOARG (int) +# define SIGDEFARG (sigsig) int sigsig; +# define SIGARG 0 +#else +# define SIGPROTOARG (void) +# define SIGDEFARG () +# define SIGARG +#endif + +#ifndef SIGCHLD +#define SIGCHLD SIGCLD +#endif + +#if defined(POSIX) || defined(hpux) +# define signal xsignal +#else +# ifdef USESIGSET +# define signal sigset +# endif /* USESIGSET */ +#endif + +/* used in screen.c and attacher.c */ +#ifndef NSIG /* kbeal needs these w/o SYSV */ +# define NSIG 32 +#endif /* !NSIG */ + + +/***************************************************************** + * Wait stuff + */ + +#if (!defined(sysV68) && !defined(M_XENIX)) || defined(NeXT) || defined(M_UNIX) +# include +#endif + +#ifndef WTERMSIG +# ifndef BSDWAIT /* if wait is NOT a union: */ +# define WTERMSIG(status) (status & 0177) +# else +# define WTERMSIG(status) status.w_T.w_Termsig +# endif +#endif + +#ifndef WSTOPSIG +# ifndef BSDWAIT /* if wait is NOT a union: */ +# define WSTOPSIG(status) ((status >> 8) & 0377) +# else +# define WSTOPSIG(status) status.w_S.w_Stopsig +# endif +#endif + +/* NET-2 uses WCOREDUMP */ +#if defined(WCOREDUMP) && !defined(WIFCORESIG) +# define WIFCORESIG(status) WCOREDUMP(status) +#endif + +#ifndef WIFCORESIG +# ifndef BSDWAIT /* if wait is NOT a union: */ +# define WIFCORESIG(status) (status & 0200) +# else +# define WIFCORESIG(status) status.w_T.w_Coredump +# endif +#endif + +#ifndef WEXITSTATUS +# ifndef BSDWAIT /* if wait is NOT a union: */ +# define WEXITSTATUS(status) ((status >> 8) & 0377) +# else +# define WEXITSTATUS(status) status.w_T.w_Retcode +# endif +#endif + + +/***************************************************************** + * select stuff + */ + +#if defined(M_XENIX) || defined(M_UNIX) || defined(_SEQUENT_) +#include /* for timeval + FD... */ +#endif + +/* + * SunOS 3.5 - Tom Schmidt - Micron Semiconductor, Inc - 27-Jul-93 + * tschmidt@vax.micron.com + */ +#ifndef FD_SET +# ifndef SUNOS3 +typedef struct fd_set { int fds_bits[1]; } fd_set; +# endif +# define FD_ZERO(fd) ((fd)->fds_bits[0] = 0) +# define FD_SET(b, fd) ((fd)->fds_bits[0] |= 1 << (b)) +# define FD_ISSET(b, fd) ((fd)->fds_bits[0] & 1 << (b)) +# define FD_SETSIZE 32 +#endif + + +/***************************************************************** + * user defineable stuff + */ + +#ifndef TERMCAP_BUFSIZE +# define TERMCAP_BUFSIZE 2048 +#endif + +#ifndef MAXPATHLEN +# define MAXPATHLEN 1024 +#endif + +/* + * you may try to vary this value. Use low values if your (VMS) system + * tends to choke when pasting. Use high values if you want to test + * how many characters your pty's can buffer. + */ +#define IOSIZE 4096 + diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/pty.c b/external/gpl3/gdb/dist/readline/examples/rlfe/pty.c new file mode 100644 index 000000000000..f89d44ca8cc4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/pty.c @@ -0,0 +1,387 @@ +/* Copyright (c) 1993-2002 + * Juergen Weigert (jnweiger@immd4.informatik.uni-erlangen.de) + * Michael Schroeder (mlschroe@immd4.informatik.uni-erlangen.de) + * Copyright (c) 1987 Oliver Laumann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program (see the file COPYING); if not, write to the + * Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + **************************************************************** + */ + +#include +#include +#include +#include + +#include "config.h" +#include "screen.h" + +#ifndef sun +# include +#endif + +/* for solaris 2.1, Unixware (SVR4.2) and possibly others */ +#ifdef HAVE_SVR4_PTYS +# include +#endif + +#if defined(sun) && defined(LOCKPTY) && !defined(TIOCEXCL) +# include +#endif + +#ifdef ISC +# include +# include +# include +#endif + +#ifdef sgi +# include +#endif /* sgi */ + +#include "extern.h" + +/* + * if no PTYRANGE[01] is in the config file, we pick a default + */ +#ifndef PTYRANGE0 +# define PTYRANGE0 "qpr" +#endif +#ifndef PTYRANGE1 +# define PTYRANGE1 "0123456789abcdef" +#endif + +/* SVR4 pseudo ttys don't seem to work with SCO-5 */ +#ifdef M_UNIX +# undef HAVE_SVR4_PTYS +#endif + +extern int eff_uid; + +/* used for opening a new pty-pair: */ +static char PtyName[32], TtyName[32]; + +#if !(defined(sequent) || defined(_SEQUENT_) || defined(HAVE_SVR4_PTYS)) +# ifdef hpux +static char PtyProto[] = "/dev/ptym/ptyXY"; +static char TtyProto[] = "/dev/pty/ttyXY"; +# else +# ifdef M_UNIX +static char PtyProto[] = "/dev/ptypXY"; +static char TtyProto[] = "/dev/ttypXY"; +# else +static char PtyProto[] = "/dev/ptyXY"; +static char TtyProto[] = "/dev/ttyXY"; +# endif +# endif /* hpux */ +#endif + +static void initmaster __P((int)); + +#if defined(sun) +/* sun's utmp_update program opens the salve side, thus corrupting + */ +int pty_preopen = 1; +#else +int pty_preopen = 0; +#endif + +/* + * Open all ptys with O_NOCTTY, just to be on the safe side + * (RISCos mips breaks otherwise) + */ +#ifndef O_NOCTTY +# define O_NOCTTY 0 +#endif + +/***************************************************************/ + +static void +initmaster(f) +int f; +{ +#ifdef POSIX + tcflush(f, TCIOFLUSH); +#else +# ifdef TIOCFLUSH + (void) ioctl(f, TIOCFLUSH, (char *) 0); +# endif +#endif +#ifdef LOCKPTY + (void) ioctl(f, TIOCEXCL, (char *) 0); +#endif +} + +void +InitPTY(f) +int f; +{ + if (f < 0) + return; +#if defined(I_PUSH) && defined(HAVE_SVR4_PTYS) && !defined(sgi) && !defined(linux) && !defined(__osf__) && !defined(M_UNIX) + if (ioctl(f, I_PUSH, "ptem")) + Panic(errno, "InitPTY: cannot I_PUSH ptem"); + if (ioctl(f, I_PUSH, "ldterm")) + Panic(errno, "InitPTY: cannot I_PUSH ldterm"); +# ifdef sun + if (ioctl(f, I_PUSH, "ttcompat")) + Panic(errno, "InitPTY: cannot I_PUSH ttcompat"); +# endif +#endif +} + +/***************************************************************/ + +#if defined(OSX) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + register int f; + if ((f = open_controlling_pty(TtyName)) < 0) + return -1; + initmaster(f); + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#if (defined(sequent) || defined(_SEQUENT_)) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + char *m, *s; + register int f; + + if ((f = getpseudotty(&s, &m)) < 0) + return -1; +#ifdef _SEQUENT_ + fvhangup(s); +#endif + strncpy(PtyName, m, sizeof(PtyName)); + strncpy(TtyName, s, sizeof(TtyName)); + initmaster(f); + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#if defined(__sgi) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + int f; + char *name, *_getpty(); + sigret_t (*sigcld)__P(SIGPROTOARG); + + /* + * SIGCHLD set to SIG_DFL for _getpty() because it may fork() and + * exec() /usr/adm/mkpts + */ + sigcld = signal(SIGCHLD, SIG_DFL); + name = _getpty(&f, O_RDWR | O_NONBLOCK, 0600, 0); + signal(SIGCHLD, sigcld); + + if (name == 0) + return -1; + initmaster(f); + *ttyn = name; + return f; +} +#endif + +/***************************************************************/ + +#if defined(MIPS) && defined(HAVE_DEV_PTC) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + register int f; + struct stat buf; + + strcpy(PtyName, "/dev/ptc"); + if ((f = open(PtyName, O_RDWR | O_NOCTTY | O_NONBLOCK)) < 0) + return -1; + if (fstat(f, &buf) < 0) + { + close(f); + return -1; + } + sprintf(TtyName, "/dev/ttyq%d", minor(buf.st_rdev)); + initmaster(f); + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#if defined(HAVE_SVR4_PTYS) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + register int f; + char *m, *ptsname(); + int unlockpt __P((int)), grantpt __P((int)); +#if defined(HAVE_GETPT) && defined(linux) + int getpt __P((void)); +#endif + sigret_t (*sigcld)__P(SIGPROTOARG); + + strcpy(PtyName, "/dev/ptmx"); +#if defined(HAVE_GETPT) && defined(linux) + if ((f = getpt()) == -1) +#else + if ((f = open(PtyName, O_RDWR | O_NOCTTY)) == -1) +#endif + return -1; + + /* + * SIGCHLD set to SIG_DFL for grantpt() because it fork()s and + * exec()s pt_chmod + */ + sigcld = signal(SIGCHLD, SIG_DFL); + if ((m = ptsname(f)) == NULL || grantpt(f) || unlockpt(f)) + { + signal(SIGCHLD, sigcld); + close(f); + return -1; + } + signal(SIGCHLD, sigcld); + strncpy(TtyName, m, sizeof(TtyName)); + initmaster(f); + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#if defined(_AIX) && defined(HAVE_DEV_PTC) && !defined(PTY_DONE) +#define PTY_DONE + +int +OpenPTY(ttyn) +char **ttyn; +{ + register int f; + + /* a dumb looking loop replaced by mycrofts code: */ + strcpy (PtyName, "/dev/ptc"); + if ((f = open (PtyName, O_RDWR | O_NOCTTY)) < 0) + return -1; + strncpy(TtyName, ttyname(f), sizeof(TtyName)); + if (eff_uid && access(TtyName, R_OK | W_OK)) + { + close(f); + return -1; + } + initmaster(f); +# ifdef _IBMR2 + pty_preopen = 1; +# endif + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#if defined(HAVE_OPENPTY) && !defined(PTY_DONE) +#define PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + int f, s; + if (openpty(&f, &s, TtyName, NULL, NULL) != 0) + return -1; + close(s); + initmaster(f); + pty_preopen = 1; + *ttyn = TtyName; + return f; +} +#endif + +/***************************************************************/ + +#ifndef PTY_DONE +int +OpenPTY(ttyn) +char **ttyn; +{ + register char *p, *q, *l, *d; + register int f; + + debug("OpenPTY: Using BSD style ptys.\n"); + strcpy(PtyName, PtyProto); + strcpy(TtyName, TtyProto); + for (p = PtyName; *p != 'X'; p++) + ; + for (q = TtyName; *q != 'X'; q++) + ; + for (l = PTYRANGE0; (*p = *l) != '\0'; l++) + { + for (d = PTYRANGE1; (p[1] = *d) != '\0'; d++) + { + debug1("OpenPTY tries '%s'\n", PtyName); + if ((f = open(PtyName, O_RDWR | O_NOCTTY)) == -1) + continue; + q[0] = *l; + q[1] = *d; + if (eff_uid && access(TtyName, R_OK | W_OK)) + { + close(f); + continue; + } +#if defined(sun) && defined(TIOCGPGRP) && !defined(SUNOS3) + /* Hack to ensure that the slave side of the pty is + * unused. May not work in anything other than SunOS4.1 + */ + { + int pgrp; + + /* tcgetpgrp does not work (uses TIOCGETPGRP)! */ + if (ioctl(f, TIOCGPGRP, (char *)&pgrp) != -1 || errno != EIO) + { + close(f); + continue; + } + } +#endif + initmaster(f); + *ttyn = TtyName; + return f; + } + } + return -1; +} +#endif + diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/rlfe.c b/external/gpl3/gdb/dist/readline/examples/rlfe/rlfe.c new file mode 100644 index 000000000000..6d747dcb42ec --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/rlfe.c @@ -0,0 +1,780 @@ +/* A front-end using readline to "cook" input lines. + * + * Copyright (C) 2004, 1999 Per Bothner + * + * This front-end program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as published + * by the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * Some code from Johnson & Troan: "Linux Application Development" + * (Addison-Wesley, 1998) was used directly or for inspiration. + * + * 2003-11-07 Wolfgang Taeuber + * Specify a history file and the size of the history file with command + * line options; use EDITOR/VISUAL to set vi/emacs preference. + */ + +/* PROBLEMS/TODO: + * + * Only tested under GNU/Linux and Mac OS 10.x; needs to be ported. + * + * Switching between line-editing-mode vs raw-char-mode depending on + * what tcgetattr returns is inherently not robust, plus it doesn't + * work when ssh/telnetting in. A better solution is possible if the + * tty system can send in-line escape sequences indicating the current + * mode, echo'd input, etc. That would also allow a user preference + * to set different colors for prompt, input, stdout, and stderr. + * + * When running mc -c under the Linux console, mc does not recognize + * mouse clicks, which mc does when not running under rlfe. + * + * Pasting selected text containing tabs is like hitting the tab character, + * which invokes readline completion. We don't want this. I don't know + * if this is fixable without integrating rlfe into a terminal emulator. + * + * Echo suppression is a kludge, but can only be avoided with better kernel + * support: We need a tty mode to disable "real" echoing, while still + * letting the inferior think its tty driver to doing echoing. + * Stevens's book claims SCR$ and BSD4.3+ have TIOCREMOTE. + * + * The latest readline may have some hooks we can use to avoid having + * to back up the prompt. (See HAVE_ALREADY_PROMPTED.) + * + * Desirable readline feature: When in cooked no-echo mode (e.g. password), + * echo characters are they are types with '*', but remove them when done. + * + * Asynchronous output while we're editing an input line should be + * inserted in the output view *before* the input line, so that the + * lines being edited (with the prompt) float at the end of the input. + * + * A "page mode" option to emulate more/less behavior: At each page of + * output, pause for a user command. This required parsing the output + * to keep track of line lengths. It also requires remembering the + * output, if we want an option to scroll back, which suggests that + * this should be integrated with a terminal emulator like xterm. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "config.h" + +#ifdef READLINE_LIBRARY +# include "readline.h" +# include "history.h" +#else +# include +# include +#endif + +#ifndef COMMAND +#define COMMAND "/bin/bash" +#endif +#ifndef COMMAND_ARGS +#define COMMAND_ARGS COMMAND +#endif + +#ifndef ALT_COMMAND +#define ALT_COMMAND "/bin/sh" +#endif +#ifndef ALT_COMMAND_ARGS +#define ALT_COMMAND_ARGS ALT_COMMAND +#endif + +#ifndef HAVE_MEMMOVE +# if __GNUC__ > 1 +# define memmove(d, s, n) __builtin_memcpy(d, s, n) +# else +# define memmove(d, s, n) memcpy(d, s, n) +# endif +#else +# define memmove(d, s, n) memcpy(d, s, n) +#endif + +#define APPLICATION_NAME "rlfe" + +static int in_from_inferior_fd; +static int out_to_inferior_fd; +static void set_edit_mode (); +static void usage_exit (); +static char *hist_file = 0; +static int hist_size = 0; + +/* Unfortunately, we cannot safely display echo from the inferior process. + The reason is that the echo bit in the pty is "owned" by the inferior, + and if we try to turn it off, we could confuse the inferior. + Thus, when echoing, we get echo twice: First readline echoes while + we're actually editing. Then we send the line to the inferior, and the + terminal driver send back an extra echo. + The work-around is to remember the input lines, and when we see that + line come back, we supress the output. + A better solution (supposedly available on SVR4) would be a smarter + terminal driver, with more flags ... */ +#define ECHO_SUPPRESS_MAX 1024 +char echo_suppress_buffer[ECHO_SUPPRESS_MAX]; +int echo_suppress_start = 0; +int echo_suppress_limit = 0; + +/*#define DEBUG*/ + +#ifdef DEBUG +FILE *logfile = NULL; +#define DPRINT0(FMT) (fprintf(logfile, FMT), fflush(logfile)) +#define DPRINT1(FMT, V1) (fprintf(logfile, FMT, V1), fflush(logfile)) +#define DPRINT2(FMT, V1, V2) (fprintf(logfile, FMT, V1, V2), fflush(logfile)) +#else +#define DPRINT0(FMT) ((void) 0) /* Do nothing */ +#define DPRINT1(FMT, V1) ((void) 0) /* Do nothing */ +#define DPRINT2(FMT, V1, V2) ((void) 0) /* Do nothing */ +#endif + +struct termios orig_term; + +/* Pid of child process. */ +static pid_t child = -1; + +static void +sig_child (int signo) +{ + int status; + wait (&status); + if (hist_file != 0) + { + write_history (hist_file); + if (hist_size) + history_truncate_file (hist_file, hist_size); + } + DPRINT0 ("(Child process died.)\n"); + tcsetattr(STDIN_FILENO, TCSANOW, &orig_term); + exit (0); +} + +volatile int propagate_sigwinch = 0; + +/* sigwinch_handler + * propagate window size changes from input file descriptor to + * master side of pty. + */ +void sigwinch_handler(int signal) { + propagate_sigwinch = 1; +} + + +/* get_slave_pty() returns an integer file descriptor. + * If it returns < 0, an error has occurred. + * Otherwise, it has returned the slave file descriptor. + */ + +int get_slave_pty(char *name) { + struct group *gptr; + gid_t gid; + int slave = -1; + + /* chown/chmod the corresponding pty, if possible. + * This will only work if the process has root permissions. + * Alternatively, write and exec a small setuid program that + * does just this. + */ + if ((gptr = getgrnam("tty")) != 0) { + gid = gptr->gr_gid; + } else { + /* if the tty group does not exist, don't change the + * group on the slave pty, only the owner + */ + gid = -1; + } + + /* Note that we do not check for errors here. If this is code + * where these actions are critical, check for errors! + */ + chown(name, getuid(), gid); + /* This code only makes the slave read/writeable for the user. + * If this is for an interactive shell that will want to + * receive "write" and "wall" messages, OR S_IWGRP into the + * second argument below. + */ + chmod(name, S_IRUSR|S_IWUSR); + + /* open the corresponding slave pty */ + slave = open(name, O_RDWR); + return (slave); +} + +/* Certain special characters, such as ctrl/C, we want to pass directly + to the inferior, rather than letting readline handle them. */ + +static char special_chars[20]; +static int special_chars_count; + +static void +add_special_char(int ch) +{ + if (ch != 0) + special_chars[special_chars_count++] = ch; +} + +static int eof_char; + +static int +is_special_char(int ch) +{ + int i; +#if 0 + if (ch == eof_char && rl_point == rl_end) + return 1; +#endif + for (i = special_chars_count; --i >= 0; ) + if (special_chars[i] == ch) + return 1; + return 0; +} + +static char buf[1024]; +/* buf[0 .. buf_count-1] is the what has been emitted on the current line. + It is used as the readline prompt. */ +static int buf_count = 0; + +int do_emphasize_input = 1; +int current_emphasize_input; + +char *start_input_mode = "\033[1m"; +char *end_input_mode = "\033[0m"; + +int num_keys = 0; + +static void maybe_emphasize_input (int on) +{ + if (on == current_emphasize_input + || (on && ! do_emphasize_input)) + return; + fprintf (rl_outstream, on ? start_input_mode : end_input_mode); + fflush (rl_outstream); + current_emphasize_input = on; +} + +static void +null_prep_terminal (int meta) +{ +} + +static void +null_deprep_terminal () +{ + maybe_emphasize_input (0); +} + +static int +pre_input_change_mode (void) +{ + return 0; +} + +char pending_special_char; + +static void +line_handler (char *line) +{ + if (line == NULL) + { + char buf[1]; + DPRINT0("saw eof!\n"); + buf[0] = '\004'; /* ctrl/d */ + write (out_to_inferior_fd, buf, 1); + } + else + { + static char enter[] = "\r"; + /* Send line to inferior: */ + int length = strlen (line); + if (length > ECHO_SUPPRESS_MAX-2) + { + echo_suppress_start = 0; + echo_suppress_limit = 0; + } + else + { + if (echo_suppress_limit + length > ECHO_SUPPRESS_MAX - 2) + { + if (echo_suppress_limit - echo_suppress_start + length + <= ECHO_SUPPRESS_MAX - 2) + { + memmove (echo_suppress_buffer, + echo_suppress_buffer + echo_suppress_start, + echo_suppress_limit - echo_suppress_start); + echo_suppress_limit -= echo_suppress_start; + echo_suppress_start = 0; + } + else + { + echo_suppress_limit = 0; + } + echo_suppress_start = 0; + } + memcpy (echo_suppress_buffer + echo_suppress_limit, + line, length); + echo_suppress_limit += length; + echo_suppress_buffer[echo_suppress_limit++] = '\r'; + echo_suppress_buffer[echo_suppress_limit++] = '\n'; + } + write (out_to_inferior_fd, line, length); + if (pending_special_char == 0) + { + write (out_to_inferior_fd, enter, sizeof(enter)-1); + if (*line) + add_history (line); + } + free (line); + } + rl_callback_handler_remove (); + buf_count = 0; + num_keys = 0; + if (pending_special_char != 0) + { + write (out_to_inferior_fd, &pending_special_char, 1); + pending_special_char = 0; + } +} + +/* Value of rl_getc_function. + Use this because readline should read from stdin, not rl_instream, + points to the pty (so readline has monitor its terminal modes). */ + +int +my_rl_getc (FILE *dummy) +{ + int ch = rl_getc (stdin); + if (is_special_char (ch)) + { + pending_special_char = ch; + return '\r'; + } + return ch; +} + +int +main(int argc, char** argv) +{ + char *path; + int i; + int master; + char *name; + int in_from_tty_fd; + struct sigaction act; + struct winsize ws; + struct termios t; + int maxfd; + fd_set in_set; + static char empty_string[1] = ""; + char *prompt = empty_string; + int ioctl_err = 0; + int arg_base = 1; + +#ifdef DEBUG + logfile = fopen("/tmp/rlfe.log", "w"); +#endif + + while (arg_base= argc ) + usage_exit(); + switch(argv[arg_base][1]) + { + case 'h': + arg_base++; + hist_file = argv[arg_base]; + break; + case 's': + arg_base++; + hist_size = atoi(argv[arg_base]); + if (hist_size<0) + usage_exit(); + break; + default: + usage_exit(); + } + arg_base++; + } + if (hist_file) + read_history (hist_file); + + set_edit_mode (); + + rl_readline_name = APPLICATION_NAME; + + if ((master = OpenPTY (&name)) < 0) + { + perror("ptypair: could not open master pty"); + exit(1); + } + + DPRINT1("pty name: '%s'\n", name); + + /* set up SIGWINCH handler */ + act.sa_handler = sigwinch_handler; + sigemptyset(&(act.sa_mask)); + act.sa_flags = 0; + if (sigaction(SIGWINCH, &act, NULL) < 0) + { + perror("ptypair: could not handle SIGWINCH "); + exit(1); + } + + if (ioctl(STDIN_FILENO, TIOCGWINSZ, &ws) < 0) + { + perror("ptypair: could not get window size"); + exit(1); + } + + if ((child = fork()) < 0) + { + perror("cannot fork"); + exit(1); + } + + if (child == 0) + { + int slave; /* file descriptor for slave pty */ + + /* We are in the child process */ + close(master); + +#ifdef TIOCSCTTY + if ((slave = get_slave_pty(name)) < 0) + { + perror("ptypair: could not open slave pty"); + exit(1); + } +#endif + + /* We need to make this process a session group leader, because + * it is on a new PTY, and things like job control simply will + * not work correctly unless there is a session group leader + * and process group leader (which a session group leader + * automatically is). This also disassociates us from our old + * controlling tty. + */ + if (setsid() < 0) + { + perror("could not set session leader"); + } + + /* Tie us to our new controlling tty. */ +#ifdef TIOCSCTTY + if (ioctl(slave, TIOCSCTTY, NULL)) + { + perror("could not set new controlling tty"); + } +#else + if ((slave = get_slave_pty(name)) < 0) + { + perror("ptypair: could not open slave pty"); + exit(1); + } +#endif + + /* make slave pty be standard in, out, and error */ + dup2(slave, STDIN_FILENO); + dup2(slave, STDOUT_FILENO); + dup2(slave, STDERR_FILENO); + + /* at this point the slave pty should be standard input */ + if (slave > 2) + { + close(slave); + } + + /* Try to restore window size; failure isn't critical */ + if (ioctl(STDOUT_FILENO, TIOCSWINSZ, &ws) < 0) + { + perror("could not restore window size"); + } + + /* now start the shell */ + { + static char* command_args[] = { COMMAND_ARGS, NULL }; + static char* alt_command_args[] = { ALT_COMMAND_ARGS, NULL }; + if (argc <= 1) + { + execvp (COMMAND, command_args); + execvp (ALT_COMMAND, alt_command_args); + } + else + execvp (argv[arg_base], &argv[arg_base]); + } + + /* should never be reached */ + exit(1); + } + + /* parent */ + signal (SIGCHLD, sig_child); + + /* Note that we only set termios settings for standard input; + * the master side of a pty is NOT a tty. + */ + tcgetattr(STDIN_FILENO, &orig_term); + + t = orig_term; + eof_char = t.c_cc[VEOF]; + /* add_special_char(t.c_cc[VEOF]);*/ + add_special_char(t.c_cc[VINTR]); + add_special_char(t.c_cc[VQUIT]); + add_special_char(t.c_cc[VSUSP]); +#if defined (VDISCARD) + add_special_char(t.c_cc[VDISCARD]); +#endif + + t.c_lflag &= ~(ICANON | ISIG | ECHO | ECHOCTL | ECHOE | \ + ECHOK | ECHOKE | ECHONL | ECHOPRT ); + t.c_iflag &= ~ICRNL; + t.c_iflag |= IGNBRK; + t.c_cc[VMIN] = 1; + t.c_cc[VTIME] = 0; + tcsetattr(STDIN_FILENO, TCSANOW, &t); + in_from_inferior_fd = master; + out_to_inferior_fd = master; + rl_instream = fdopen (master, "r"); + rl_getc_function = my_rl_getc; + + rl_prep_term_function = null_prep_terminal; + rl_deprep_term_function = null_deprep_terminal; + rl_pre_input_hook = pre_input_change_mode; + rl_callback_handler_install (prompt, line_handler); + + in_from_tty_fd = STDIN_FILENO; + FD_ZERO (&in_set); + maxfd = in_from_inferior_fd > in_from_tty_fd ? in_from_inferior_fd + : in_from_tty_fd; + for (;;) + { + int num; + FD_SET (in_from_inferior_fd, &in_set); + FD_SET (in_from_tty_fd, &in_set); + + num = select(maxfd+1, &in_set, NULL, NULL, NULL); + + if (propagate_sigwinch) + { + struct winsize ws; + if (ioctl (STDIN_FILENO, TIOCGWINSZ, &ws) >= 0) + { + ioctl (master, TIOCSWINSZ, &ws); + } + propagate_sigwinch = 0; + continue; + } + + if (num <= 0) + { + perror ("select"); + exit (-1); + } + if (FD_ISSET (in_from_tty_fd, &in_set)) + { + extern int readline_echoing_p; + struct termios term_master; + int do_canon = 1; + int do_icrnl = 1; + int ioctl_ret; + + DPRINT1("[tty avail num_keys:%d]\n", num_keys); + + /* If we can't get tty modes for the master side of the pty, we + can't handle non-canonical-mode programs. Always assume the + master is in canonical echo mode if we can't tell. */ + ioctl_ret = tcgetattr(master, &term_master); + + if (ioctl_ret >= 0) + { + do_canon = (term_master.c_lflag & ICANON) != 0; + do_icrnl = (term_master.c_lflag & ICRNL) != 0; + readline_echoing_p = (term_master.c_lflag & ECHO) != 0; + DPRINT1 ("echo,canon,crnl:%03d\n", + 100 * readline_echoing_p + + 10 * do_canon + + 1 * do_icrnl); + } + else + { + if (ioctl_err == 0) + DPRINT1("tcgetattr on master fd failed: errno = %d\n", errno); + ioctl_err = 1; + } + + if (do_canon == 0 && num_keys == 0) + { + char ch[10]; + int count = read (STDIN_FILENO, ch, sizeof(ch)); + DPRINT1("[read %d chars from stdin: ", count); + DPRINT2(" \"%.*s\"]\n", count, ch); + if (do_icrnl) + { + int i = count; + while (--i >= 0) + { + if (ch[i] == '\r') + ch[i] = '\n'; + } + } + maybe_emphasize_input (1); + write (out_to_inferior_fd, ch, count); + } + else + { + if (num_keys == 0) + { + int i; + /* Re-install callback handler for new prompt. */ + if (prompt != empty_string) + free (prompt); + if (prompt == NULL) + { + DPRINT0("New empty prompt\n"); + prompt = empty_string; + } + else + { + if (do_emphasize_input && buf_count > 0) + { + prompt = malloc (buf_count + strlen (end_input_mode) + + strlen (start_input_mode) + 5); + sprintf (prompt, "\001%s\002%.*s\001%s\002", + end_input_mode, + buf_count, buf, + start_input_mode); + } + else + { + prompt = malloc (buf_count + 1); + memcpy (prompt, buf, buf_count); + prompt[buf_count] = '\0'; + } + DPRINT1("New prompt '%s'\n", prompt); +#if 0 /* ifdef HAVE_RL_ALREADY_PROMPTED */ + /* Doesn't quite work when do_emphasize_input is 1. */ + rl_already_prompted = buf_count > 0; +#else + if (buf_count > 0) + write (1, "\r", 1); +#endif + } + + rl_callback_handler_install (prompt, line_handler); + } + num_keys++; + maybe_emphasize_input (1); + rl_callback_read_char (); + } + } + else /* output from inferior. */ + { + int i; + int count; + int old_count; + if (buf_count > (sizeof(buf) >> 2)) + buf_count = 0; + count = read (in_from_inferior_fd, buf+buf_count, + sizeof(buf) - buf_count); + DPRINT2("read %d from inferior, buf_count=%d", count, buf_count); + DPRINT2(": \"%.*s\"", count, buf+buf_count); + maybe_emphasize_input (0); + if (count <= 0) + { + DPRINT0 ("(Connection closed by foreign host.)\n"); + tcsetattr(STDIN_FILENO, TCSANOW, &orig_term); + exit (0); + } + old_count = buf_count; + + /* Look for any pending echo that we need to suppress. */ + while (echo_suppress_start < echo_suppress_limit + && count > 0 + && buf[buf_count] == echo_suppress_buffer[echo_suppress_start]) + { + count--; + buf_count++; + echo_suppress_start++; + } + DPRINT1("suppressed %d characters of echo.\n", buf_count-old_count); + + /* Write to the terminal anything that was not suppressed. */ + if (count > 0) + write (1, buf + buf_count, count); + + /* Finally, look for a prompt candidate. + * When we get around to going input (from the keyboard), + * we will consider the prompt to be anything since the last + * line terminator. So we need to save that text in the + * initial part of buf. However, anything before the + * most recent end-of-line is not interesting. */ + buf_count += count; +#if 1 + for (i = buf_count; --i >= old_count; ) +#else + for (i = buf_count - 1; i-- >= buf_count - count; ) +#endif + { + if (buf[i] == '\n' || buf[i] == '\r') + { + i++; + memmove (buf, buf+i, buf_count - i); + buf_count -= i; + break; + } + } + DPRINT2("-> i: %d, buf_count: %d\n", i, buf_count); + } + } +} + +static void set_edit_mode () +{ + int vi = 0; + char *shellopts; + + shellopts = getenv ("SHELLOPTS"); + while (shellopts != 0) + { + if (strncmp ("vi", shellopts, 2) == 0) + { + vi = 1; + break; + } + shellopts = index (shellopts + 1, ':'); + } + + if (!vi) + { + if (getenv ("EDITOR") != 0) + vi |= strcmp (getenv ("EDITOR"), "vi") == 0; + } + + if (vi) + rl_variable_bind ("editing-mode", "vi"); + else + rl_variable_bind ("editing-mode", "emacs"); +} + + +static void usage_exit () +{ + fprintf (stderr, "Usage: rlfe [-h histfile] [-s size] cmd [arg1] [arg2] ...\n\n"); + exit (1); +} diff --git a/external/gpl3/gdb/dist/readline/examples/rlfe/screen.h b/external/gpl3/gdb/dist/readline/examples/rlfe/screen.h new file mode 100644 index 000000000000..5b040c3dacf9 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlfe/screen.h @@ -0,0 +1,2 @@ +/* Dummy header to avoid modifying pty.c */ +#include "os.h" diff --git a/external/gpl3/gdb/dist/readline/examples/rlptytest.c b/external/gpl3/gdb/dist/readline/examples/rlptytest.c new file mode 100644 index 000000000000..79257db4005f --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlptytest.c @@ -0,0 +1,337 @@ +/* + * + * Another test harness for the readline callback interface. + * + * Author: Bob Rossi + */ + +#if defined (HAVE_CONFIG_H) +#include +#endif + +#include +#include +#include +#include + +#include +#include + +#include + +#if 0 /* LINUX */ +#include +#else +#include +#endif + +#ifdef READLINE_LIBRARY +# include "readline.h" +#else +# include +#endif + +/** + * Master/Slave PTY used to keep readline off of stdin/stdout. + */ +static int masterfd = -1; +static int slavefd; + +void +sigint (s) + int s; +{ + tty_reset (STDIN_FILENO); + close (masterfd); + close (slavefd); + printf ("\n"); + exit (0); +} + +static int +user_input() +{ + int size; + const int MAX = 1024; + char *buf = (char *)malloc(MAX+1); + + size = read (STDIN_FILENO, buf, MAX); + if (size == -1) + return -1; + + size = write (masterfd, buf, size); + if (size == -1) + return -1; + + return 0; +} + +static int +readline_input() +{ + const int MAX = 1024; + char *buf = (char *)malloc(MAX+1); + int size; + + size = read (masterfd, buf, MAX); + if (size == -1) + { + free( buf ); + buf = NULL; + return -1; + } + + buf[size] = 0; + + /* Display output from readline */ + if ( size > 0 ) + fprintf(stderr, "%s", buf); + + free( buf ); + buf = NULL; + return 0; +} + +static void +rlctx_send_user_command(char *line) +{ + /* This happens when rl_callback_read_char gets EOF */ + if ( line == NULL ) + return; + + if (strcmp (line, "exit") == 0) { + tty_reset (STDIN_FILENO); + close (masterfd); + close (slavefd); + printf ("\n"); + exit (0); + } + + /* Don't add the enter command */ + if ( line && *line != '\0' ) + add_history(line); +} + +static void +custom_deprep_term_function () +{ +} + +static int +init_readline (int inputfd, int outputfd) +{ + FILE *inputFILE, *outputFILE; + + inputFILE = fdopen (inputfd, "r"); + if (!inputFILE) + return -1; + + outputFILE = fdopen (outputfd, "w"); + if (!outputFILE) + return -1; + + rl_instream = inputFILE; + rl_outstream = outputFILE; + + /* Tell readline what the prompt is if it needs to put it back */ + rl_callback_handler_install("(rltest): ", rlctx_send_user_command); + + /* Set the terminal type to dumb so the output of readline can be + * understood by tgdb */ + if ( rl_reset_terminal("dumb") == -1 ) + return -1; + + /* For some reason, readline can not deprep the terminal. + * However, it doesn't matter because no other application is working on + * the terminal besides readline */ + rl_deprep_term_function = custom_deprep_term_function; + + using_history(); + read_history(".history"); + + return 0; +} + +static int +main_loop(void) +{ + fd_set rset; + int max; + + max = (masterfd > STDIN_FILENO) ? masterfd : STDIN_FILENO; + max = (max > slavefd) ? max : slavefd; + + for (;;) + { + /* Reset the fd_set, and watch for input from GDB or stdin */ + FD_ZERO(&rset); + + FD_SET(STDIN_FILENO, &rset); + FD_SET(slavefd, &rset); + FD_SET(masterfd, &rset); + + /* Wait for input */ + if (select(max + 1, &rset, NULL, NULL, NULL) == -1) + { + if (errno == EINTR) + continue; + else + return -1; + } + + /* Input received through the pty: Handle it + * Wrote to masterfd, slave fd has that input, alert readline to read it. + */ + if (FD_ISSET(slavefd, &rset)) + rl_callback_read_char(); + + /* Input received through the pty. + * Readline read from slavefd, and it wrote to the masterfd. + */ + if (FD_ISSET(masterfd, &rset)) + if ( readline_input() == -1 ) + return -1; + + /* Input received: Handle it, write to masterfd (input to readline) */ + if (FD_ISSET(STDIN_FILENO, &rset)) + if ( user_input() == -1 ) + return -1; + } + + return 0; +} + +/* The terminal attributes before calling tty_cbreak */ +static struct termios save_termios; +static struct winsize size; +static enum { RESET, TCBREAK } ttystate = RESET; + +/* tty_cbreak: Sets terminal to cbreak mode. Also known as noncanonical mode. + * 1. Signal handling is still turned on, so the user can still type those. + * 2. echo is off + * 3. Read in one char at a time. + * + * fd - The file descriptor of the terminal + * + * Returns: 0 on sucess, -1 on error + */ +int tty_cbreak(int fd){ + struct termios buf; + int ttysavefd = -1; + + if(tcgetattr(fd, &save_termios) < 0) + return -1; + + buf = save_termios; + buf.c_lflag &= ~(ECHO | ICANON); + buf.c_iflag &= ~(ICRNL | INLCR); + buf.c_cc[VMIN] = 1; + buf.c_cc[VTIME] = 0; + +#if defined (VLNEXT) && defined (_POSIX_VDISABLE) + buf.c_cc[VLNEXT] = _POSIX_VDISABLE; +#endif + +#if defined (VDSUSP) && defined (_POSIX_VDISABLE) + buf.c_cc[VDSUSP] = _POSIX_VDISABLE; +#endif + + /* enable flow control; only stty start char can restart output */ +#if 0 + buf.c_iflag |= (IXON|IXOFF); +#ifdef IXANY + buf.c_iflag &= ~IXANY; +#endif +#endif + + /* disable flow control; let ^S and ^Q through to pty */ + buf.c_iflag &= ~(IXON|IXOFF); +#ifdef IXANY + buf.c_iflag &= ~IXANY; +#endif + + if(tcsetattr(fd, TCSAFLUSH, &buf) < 0) + return -1; + + ttystate = TCBREAK; + ttysavefd = fd; + + /* set size */ + if(ioctl(fd, TIOCGWINSZ, (char *)&size) < 0) + return -1; + +#ifdef DEBUG + err_msg("%d rows and %d cols\n", size.ws_row, size.ws_col); +#endif + + return (0); +} + +int +tty_off_xon_xoff (int fd) +{ + struct termios buf; + int ttysavefd = -1; + + if(tcgetattr(fd, &buf) < 0) + return -1; + + buf.c_iflag &= ~(IXON|IXOFF); + + if(tcsetattr(fd, TCSAFLUSH, &buf) < 0) + return -1; + + return 0; +} + +/* tty_reset: Sets the terminal attributes back to their previous state. + * PRE: tty_cbreak must have already been called. + * + * fd - The file descrioptor of the terminal to reset. + * + * Returns: 0 on success, -1 on error + */ +int tty_reset(int fd) +{ + if(ttystate != TCBREAK) + return (0); + + if(tcsetattr(fd, TCSAFLUSH, &save_termios) < 0) + return (-1); + + ttystate = RESET; + + return 0; +} + +int +main() +{ + int val; + val = openpty (&masterfd, &slavefd, NULL, NULL, NULL); + if (val == -1) + return -1; + + val = tty_off_xon_xoff (masterfd); + if (val == -1) + return -1; + + val = init_readline (slavefd, slavefd); + if (val == -1) + return -1; + + val = tty_cbreak (STDIN_FILENO); + if (val == -1) + return -1; + + signal (SIGINT, sigint); + + val = main_loop (); + + tty_reset (STDIN_FILENO); + + if (val == -1) + return -1; + + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/examples/rltest.c b/external/gpl3/gdb/dist/readline/examples/rltest.c new file mode 100644 index 000000000000..cb67bab80c50 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rltest.c @@ -0,0 +1,93 @@ +/* **************************************************************** */ +/* */ +/* Testing Readline */ +/* */ +/* **************************************************************** */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +#include +#endif + +#include +#include + +#ifdef HAVE_STDLIB_H +# include +#else +extern void exit(); +#endif + +#ifdef READLINE_LIBRARY +# include "readline.h" +# include "history.h" +#else +# include +# include +#endif + +extern HIST_ENTRY **history_list (); + +main () +{ + char *temp, *prompt; + int done; + + temp = (char *)NULL; + prompt = "readline$ "; + done = 0; + + while (!done) + { + temp = readline (prompt); + + /* Test for EOF. */ + if (!temp) + exit (1); + + /* If there is anything on the line, print it and remember it. */ + if (*temp) + { + fprintf (stderr, "%s\r\n", temp); + add_history (temp); + } + + /* Check for `command' that we handle. */ + if (strcmp (temp, "quit") == 0) + done = 1; + + if (strcmp (temp, "list") == 0) + { + HIST_ENTRY **list; + register int i; + + list = history_list (); + if (list) + { + for (i = 0; list[i]; i++) + fprintf (stderr, "%d: %s\r\n", i, list[i]->line); + } + } + free (temp); + } + exit (0); +} diff --git a/external/gpl3/gdb/dist/readline/examples/rlversion.c b/external/gpl3/gdb/dist/readline/examples/rlversion.c new file mode 100644 index 000000000000..6c8687488e96 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/examples/rlversion.c @@ -0,0 +1,49 @@ +/* + * rlversion -- print out readline's version number + */ + +/* Copyright (C) 1987-2002 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include "posixstat.h" + +#ifdef HAVE_STDLIB_H +# include +#else +extern void exit(); +#endif + +#ifdef READLINE_LIBRARY +# include "readline.h" +#else +# include +#endif + +main() +{ + printf ("%s\n", rl_library_version ? rl_library_version : "unknown"); + exit (0); +} diff --git a/external/gpl3/gdb/dist/readline/funmap.c b/external/gpl3/gdb/dist/readline/funmap.c new file mode 100644 index 000000000000..9c760cc34753 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/funmap.c @@ -0,0 +1,255 @@ +/* funmap.c -- attach names to functions. */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if !defined (BUFSIZ) +#include +#endif /* BUFSIZ */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include "rlconf.h" +#include "readline.h" + +#include "xmalloc.h" + +#ifdef __STDC__ +typedef int QSFUNC (const void *, const void *); +#else +typedef int QSFUNC (); +#endif + +extern int _rl_qsort_string_compare PARAMS((char **, char **)); + +FUNMAP **funmap; +static int funmap_size; +static int funmap_entry; + +/* After initializing the function map, this is the index of the first + program specific function. */ +int funmap_program_specific_entry_start; + +static FUNMAP default_funmap[] = { + { "abort", rl_abort }, + { "accept-line", rl_newline }, + { "arrow-key-prefix", rl_arrow_keys }, + { "backward-byte", rl_backward_byte }, + { "backward-char", rl_backward_char }, + { "backward-delete-char", rl_rubout }, + { "backward-kill-line", rl_backward_kill_line }, + { "backward-kill-word", rl_backward_kill_word }, + { "backward-word", rl_backward_word }, + { "beginning-of-history", rl_beginning_of_history }, + { "beginning-of-line", rl_beg_of_line }, + { "call-last-kbd-macro", rl_call_last_kbd_macro }, + { "capitalize-word", rl_capitalize_word }, + { "character-search", rl_char_search }, + { "character-search-backward", rl_backward_char_search }, + { "clear-screen", rl_clear_screen }, + { "complete", rl_complete }, + { "copy-backward-word", rl_copy_backward_word }, + { "copy-forward-word", rl_copy_forward_word }, + { "copy-region-as-kill", rl_copy_region_to_kill }, + { "delete-char", rl_delete }, + { "delete-char-or-list", rl_delete_or_show_completions }, + { "delete-horizontal-space", rl_delete_horizontal_space }, + { "digit-argument", rl_digit_argument }, + { "do-lowercase-version", rl_do_lowercase_version }, + { "downcase-word", rl_downcase_word }, + { "dump-functions", rl_dump_functions }, + { "dump-macros", rl_dump_macros }, + { "dump-variables", rl_dump_variables }, + { "emacs-editing-mode", rl_emacs_editing_mode }, + { "end-kbd-macro", rl_end_kbd_macro }, + { "end-of-history", rl_end_of_history }, + { "end-of-line", rl_end_of_line }, + { "exchange-point-and-mark", rl_exchange_point_and_mark }, + { "forward-backward-delete-char", rl_rubout_or_delete }, + { "forward-byte", rl_forward_byte }, + { "forward-char", rl_forward_char }, + { "forward-search-history", rl_forward_search_history }, + { "forward-word", rl_forward_word }, + { "history-search-backward", rl_history_search_backward }, + { "history-search-forward", rl_history_search_forward }, + { "insert-comment", rl_insert_comment }, + { "insert-completions", rl_insert_completions }, + { "kill-whole-line", rl_kill_full_line }, + { "kill-line", rl_kill_line }, + { "kill-region", rl_kill_region }, + { "kill-word", rl_kill_word }, + { "menu-complete", rl_menu_complete }, + { "next-history", rl_get_next_history }, + { "non-incremental-forward-search-history", rl_noninc_forward_search }, + { "non-incremental-reverse-search-history", rl_noninc_reverse_search }, + { "non-incremental-forward-search-history-again", rl_noninc_forward_search_again }, + { "non-incremental-reverse-search-history-again", rl_noninc_reverse_search_again }, + { "overwrite-mode", rl_overwrite_mode }, +#ifdef __CYGWIN__ + { "paste-from-clipboard", rl_paste_from_clipboard }, +#endif + { "possible-completions", rl_possible_completions }, + { "previous-history", rl_get_previous_history }, + { "quoted-insert", rl_quoted_insert }, + { "re-read-init-file", rl_re_read_init_file }, + { "redraw-current-line", rl_refresh_line}, + { "reverse-search-history", rl_reverse_search_history }, + { "revert-line", rl_revert_line }, + { "self-insert", rl_insert }, + { "set-mark", rl_set_mark }, + { "start-kbd-macro", rl_start_kbd_macro }, + { "tab-insert", rl_tab_insert }, + { "tilde-expand", rl_tilde_expand }, + { "transpose-chars", rl_transpose_chars }, + { "transpose-words", rl_transpose_words }, + { "tty-status", rl_tty_status }, + { "undo", rl_undo_command }, + { "universal-argument", rl_universal_argument }, + { "unix-filename-rubout", rl_unix_filename_rubout }, + { "unix-line-discard", rl_unix_line_discard }, + { "unix-word-rubout", rl_unix_word_rubout }, + { "upcase-word", rl_upcase_word }, + { "yank", rl_yank }, + { "yank-last-arg", rl_yank_last_arg }, + { "yank-nth-arg", rl_yank_nth_arg }, + { "yank-pop", rl_yank_pop }, + +#if defined (VI_MODE) + { "vi-append-eol", rl_vi_append_eol }, + { "vi-append-mode", rl_vi_append_mode }, + { "vi-arg-digit", rl_vi_arg_digit }, + { "vi-back-to-indent", rl_vi_back_to_indent }, + { "vi-bWord", rl_vi_bWord }, + { "vi-bword", rl_vi_bword }, + { "vi-change-case", rl_vi_change_case }, + { "vi-change-char", rl_vi_change_char }, + { "vi-change-to", rl_vi_change_to }, + { "vi-char-search", rl_vi_char_search }, + { "vi-column", rl_vi_column }, + { "vi-complete", rl_vi_complete }, + { "vi-delete", rl_vi_delete }, + { "vi-delete-to", rl_vi_delete_to }, + { "vi-eWord", rl_vi_eWord }, + { "vi-editing-mode", rl_vi_editing_mode }, + { "vi-end-word", rl_vi_end_word }, + { "vi-eof-maybe", rl_vi_eof_maybe }, + { "vi-eword", rl_vi_eword }, + { "vi-fWord", rl_vi_fWord }, + { "vi-fetch-history", rl_vi_fetch_history }, + { "vi-first-print", rl_vi_first_print }, + { "vi-fword", rl_vi_fword }, + { "vi-goto-mark", rl_vi_goto_mark }, + { "vi-insert-beg", rl_vi_insert_beg }, + { "vi-insertion-mode", rl_vi_insertion_mode }, + { "vi-match", rl_vi_match }, + { "vi-movement-mode", rl_vi_movement_mode }, + { "vi-next-word", rl_vi_next_word }, + { "vi-overstrike", rl_vi_overstrike }, + { "vi-overstrike-delete", rl_vi_overstrike_delete }, + { "vi-prev-word", rl_vi_prev_word }, + { "vi-put", rl_vi_put }, + { "vi-redo", rl_vi_redo }, + { "vi-replace", rl_vi_replace }, + { "vi-rubout", rl_vi_rubout }, + { "vi-search", rl_vi_search }, + { "vi-search-again", rl_vi_search_again }, + { "vi-set-mark", rl_vi_set_mark }, + { "vi-subst", rl_vi_subst }, + { "vi-tilde-expand", rl_vi_tilde_expand }, + { "vi-yank-arg", rl_vi_yank_arg }, + { "vi-yank-to", rl_vi_yank_to }, +#endif /* VI_MODE */ + + {(char *)NULL, (rl_command_func_t *)NULL } +}; + +int +rl_add_funmap_entry (name, function) + const char *name; + rl_command_func_t *function; +{ + if (funmap_entry + 2 >= funmap_size) + { + funmap_size += 64; + funmap = (FUNMAP **)xrealloc (funmap, funmap_size * sizeof (FUNMAP *)); + } + + funmap[funmap_entry] = (FUNMAP *)xmalloc (sizeof (FUNMAP)); + funmap[funmap_entry]->name = name; + funmap[funmap_entry]->function = function; + + funmap[++funmap_entry] = (FUNMAP *)NULL; + return funmap_entry; +} + +static int funmap_initialized; + +/* Make the funmap contain all of the default entries. */ +void +rl_initialize_funmap () +{ + register int i; + + if (funmap_initialized) + return; + + for (i = 0; default_funmap[i].name; i++) + rl_add_funmap_entry (default_funmap[i].name, default_funmap[i].function); + + funmap_initialized = 1; + funmap_program_specific_entry_start = i; +} + +/* Produce a NULL terminated array of known function names. The array + is sorted. The array itself is allocated, but not the strings inside. + You should free () the array when you done, but not the pointrs. */ +const char ** +rl_funmap_names () +{ + const char **result; + int result_size, result_index; + + /* Make sure that the function map has been initialized. */ + rl_initialize_funmap (); + + for (result_index = result_size = 0, result = (const char **)NULL; funmap[result_index]; result_index++) + { + if (result_index + 2 > result_size) + { + result_size += 20; + result = (const char **)xrealloc (result, result_size * sizeof (char *)); + } + + result[result_index] = funmap[result_index]->name; + result[result_index + 1] = (char *)NULL; + } + + qsort (result, result_index, sizeof (char *), (QSFUNC *)_rl_qsort_string_compare); + return (result); +} diff --git a/external/gpl3/gdb/dist/readline/histexpand.c b/external/gpl3/gdb/dist/readline/histexpand.c new file mode 100644 index 000000000000..684701469022 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/histexpand.c @@ -0,0 +1,1593 @@ +/* histexpand.c -- history expansion. */ + +/* Copyright (C) 1989-2004 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_UNISTD_H) +# ifndef _MINIX +# include +# endif +# include +#endif + +#include "rlmbutil.h" + +#include "history.h" +#include "histlib.h" + +#include "rlshell.h" +#include "xmalloc.h" + +#define HISTORY_WORD_DELIMITERS " \t\n;&()|<>" +#define HISTORY_QUOTE_CHARACTERS "\"'`" + +#define slashify_in_quotes "\\`\"$" + +typedef int _hist_search_func_t PARAMS((const char *, int)); + +extern int rl_byte_oriented; /* declared in mbutil.c */ + +static char error_pointer; + +static char *subst_lhs; +static char *subst_rhs; +static int subst_lhs_len; +static int subst_rhs_len; + +static char *get_history_word_specifier PARAMS((char *, char *, int *)); +static char *history_find_word PARAMS((char *, int)); +static int history_tokenize_word PARAMS((const char *, int)); +static char *history_substring PARAMS((const char *, int, int)); + +static char *quote_breaks PARAMS((char *)); + +/* Variables exported by this file. */ +/* The character that represents the start of a history expansion + request. This is usually `!'. */ +char history_expansion_char = '!'; + +/* The character that invokes word substitution if found at the start of + a line. This is usually `^'. */ +char history_subst_char = '^'; + +/* During tokenization, if this character is seen as the first character + of a word, then it, and all subsequent characters upto a newline are + ignored. For a Bourne shell, this should be '#'. Bash special cases + the interactive comment character to not be a comment delimiter. */ +char history_comment_char = '\0'; + +/* The list of characters which inhibit the expansion of text if found + immediately following history_expansion_char. */ +char *history_no_expand_chars = " \t\n\r="; + +/* If set to a non-zero value, single quotes inhibit history expansion. + The default is 0. */ +int history_quotes_inhibit_expansion = 0; + +/* Used to split words by history_tokenize_internal. */ +char *history_word_delimiters = HISTORY_WORD_DELIMITERS; + +/* If set, this points to a function that is called to verify that a + particular history expansion should be performed. */ +rl_linebuf_func_t *history_inhibit_expansion_function; + +/* **************************************************************** */ +/* */ +/* History Expansion */ +/* */ +/* **************************************************************** */ + +/* Hairy history expansion on text, not tokens. This is of general + use, and thus belongs in this library. */ + +/* The last string searched for by a !?string? search. */ +static char *search_string; + +/* The last string matched by a !?string? search. */ +static char *search_match; + +/* Return the event specified at TEXT + OFFSET modifying OFFSET to + point to after the event specifier. Just a pointer to the history + line is returned; NULL is returned in the event of a bad specifier. + You pass STRING with *INDEX equal to the history_expansion_char that + begins this specification. + DELIMITING_QUOTE is a character that is allowed to end the string + specification for what to search for in addition to the normal + characters `:', ` ', `\t', `\n', and sometimes `?'. + So you might call this function like: + line = get_history_event ("!echo:p", &index, 0); */ +char * +get_history_event (string, caller_index, delimiting_quote) + const char *string; + int *caller_index; + int delimiting_quote; +{ + register int i; + register char c; + HIST_ENTRY *entry; + int which, sign, local_index, substring_okay; + _hist_search_func_t *search_func; + char *temp; + + /* The event can be specified in a number of ways. + + !! the previous command + !n command line N + !-n current command-line minus N + !str the most recent command starting with STR + !?str[?] + the most recent command containing STR + + All values N are determined via HISTORY_BASE. */ + + i = *caller_index; + + if (string[i] != history_expansion_char) + return ((char *)NULL); + + /* Move on to the specification. */ + i++; + + sign = 1; + substring_okay = 0; + +#define RETURN_ENTRY(e, w) \ + return ((e = history_get (w)) ? e->line : (char *)NULL) + + /* Handle !! case. */ + if (string[i] == history_expansion_char) + { + i++; + which = history_base + (history_length - 1); + *caller_index = i; + RETURN_ENTRY (entry, which); + } + + /* Hack case of numeric line specification. */ + if (string[i] == '-') + { + sign = -1; + i++; + } + + if (_rl_digit_p (string[i])) + { + /* Get the extent of the digits and compute the value. */ + for (which = 0; _rl_digit_p (string[i]); i++) + which = (which * 10) + _rl_digit_value (string[i]); + + *caller_index = i; + + if (sign < 0) + which = (history_length + history_base) - which; + + RETURN_ENTRY (entry, which); + } + + /* This must be something to search for. If the spec begins with + a '?', then the string may be anywhere on the line. Otherwise, + the string must be found at the start of a line. */ + if (string[i] == '?') + { + substring_okay++; + i++; + } + + /* Only a closing `?' or a newline delimit a substring search string. */ + for (local_index = i; c = string[i]; i++) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int v; + mbstate_t ps; + + memset (&ps, 0, sizeof (mbstate_t)); + /* These produce warnings because we're passing a const string to a + function that takes a non-const string. */ + _rl_adjust_point ((char *)string, i, &ps); + if ((v = _rl_get_char_len ((char *)string + i, &ps)) > 1) + { + i += v - 1; + continue; + } + } + +#endif /* HANDLE_MULTIBYTE */ + if ((!substring_okay && (whitespace (c) || c == ':' || + (history_search_delimiter_chars && member (c, history_search_delimiter_chars)) || + string[i] == delimiting_quote)) || + string[i] == '\n' || + (substring_okay && string[i] == '?')) + break; + } + + which = i - local_index; + temp = (char *)xmalloc (1 + which); + if (which) + strncpy (temp, string + local_index, which); + temp[which] = '\0'; + + if (substring_okay && string[i] == '?') + i++; + + *caller_index = i; + +#define FAIL_SEARCH() \ + do { \ + history_offset = history_length; free (temp) ; return (char *)NULL; \ + } while (0) + + /* If there is no search string, try to use the previous search string, + if one exists. If not, fail immediately. */ + if (*temp == '\0' && substring_okay) + { + if (search_string) + { + free (temp); + temp = savestring (search_string); + } + else + FAIL_SEARCH (); + } + + search_func = substring_okay ? history_search : history_search_prefix; + while (1) + { + local_index = (*search_func) (temp, -1); + + if (local_index < 0) + FAIL_SEARCH (); + + if (local_index == 0 || substring_okay) + { + entry = current_history (); + history_offset = history_length; + + /* If this was a substring search, then remember the + string that we matched for word substitution. */ + if (substring_okay) + { + FREE (search_string); + search_string = temp; + + FREE (search_match); + search_match = history_find_word (entry->line, local_index); + } + else + free (temp); + + return (entry->line); + } + + if (history_offset) + history_offset--; + else + FAIL_SEARCH (); + } +#undef FAIL_SEARCH +#undef RETURN_ENTRY +} + +/* Function for extracting single-quoted strings. Used for inhibiting + history expansion within single quotes. */ + +/* Extract the contents of STRING as if it is enclosed in single quotes. + SINDEX, when passed in, is the offset of the character immediately + following the opening single quote; on exit, SINDEX is left pointing + to the closing single quote. */ +static void +hist_string_extract_single_quoted (string, sindex) + char *string; + int *sindex; +{ + register int i; + + for (i = *sindex; string[i] && string[i] != '\''; i++) + ; + + *sindex = i; +} + +static char * +quote_breaks (s) + char *s; +{ + register char *p, *r; + char *ret; + int len = 3; + + for (p = s; p && *p; p++, len++) + { + if (*p == '\'') + len += 3; + else if (whitespace (*p) || *p == '\n') + len += 2; + } + + r = ret = (char *)xmalloc (len); + *r++ = '\''; + for (p = s; p && *p; ) + { + if (*p == '\'') + { + *r++ = '\''; + *r++ = '\\'; + *r++ = '\''; + *r++ = '\''; + p++; + } + else if (whitespace (*p) || *p == '\n') + { + *r++ = '\''; + *r++ = *p++; + *r++ = '\''; + } + else + *r++ = *p++; + } + *r++ = '\''; + *r = '\0'; + return ret; +} + +static char * +hist_error(s, start, current, errtype) + char *s; + int start, current, errtype; +{ + char *temp; + const char *emsg; + int ll, elen; + + ll = current - start; + + switch (errtype) + { + case EVENT_NOT_FOUND: + emsg = "event not found"; + elen = 15; + break; + case BAD_WORD_SPEC: + emsg = "bad word specifier"; + elen = 18; + break; + case SUBST_FAILED: + emsg = "substitution failed"; + elen = 19; + break; + case BAD_MODIFIER: + emsg = "unrecognized history modifier"; + elen = 29; + break; + case NO_PREV_SUBST: + emsg = "no previous substitution"; + elen = 24; + break; + default: + emsg = "unknown expansion error"; + elen = 23; + break; + } + + temp = (char *)xmalloc (ll + elen + 3); + strncpy (temp, s + start, ll); + temp[ll] = ':'; + temp[ll + 1] = ' '; + strcpy (temp + ll + 2, emsg); + return (temp); +} + +/* Get a history substitution string from STR starting at *IPTR + and return it. The length is returned in LENPTR. + + A backslash can quote the delimiter. If the string is the + empty string, the previous pattern is used. If there is + no previous pattern for the lhs, the last history search + string is used. + + If IS_RHS is 1, we ignore empty strings and set the pattern + to "" anyway. subst_lhs is not changed if the lhs is empty; + subst_rhs is allowed to be set to the empty string. */ + +static char * +get_subst_pattern (str, iptr, delimiter, is_rhs, lenptr) + char *str; + int *iptr, delimiter, is_rhs, *lenptr; +{ + register int si, i, j, k; + char *s; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps; +#endif + + s = (char *)NULL; + i = *iptr; + +#if defined (HANDLE_MULTIBYTE) + memset (&ps, 0, sizeof (mbstate_t)); + _rl_adjust_point (str, i, &ps); +#endif + + for (si = i; str[si] && str[si] != delimiter; si++) +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int v; + if ((v = _rl_get_char_len (str + si, &ps)) > 1) + si += v - 1; + else if (str[si] == '\\' && str[si + 1] == delimiter) + si++; + } + else +#endif /* HANDLE_MULTIBYTE */ + if (str[si] == '\\' && str[si + 1] == delimiter) + si++; + + if (si > i || is_rhs) + { + s = (char *)xmalloc (si - i + 1); + for (j = 0, k = i; k < si; j++, k++) + { + /* Remove a backslash quoting the search string delimiter. */ + if (str[k] == '\\' && str[k + 1] == delimiter) + k++; + s[j] = str[k]; + } + s[j] = '\0'; + if (lenptr) + *lenptr = j; + } + + i = si; + if (str[i]) + i++; + *iptr = i; + + return s; +} + +static void +postproc_subst_rhs () +{ + char *new; + int i, j, new_size; + + new = (char *)xmalloc (new_size = subst_rhs_len + subst_lhs_len); + for (i = j = 0; i < subst_rhs_len; i++) + { + if (subst_rhs[i] == '&') + { + if (j + subst_lhs_len >= new_size) + new = (char *)xrealloc (new, (new_size = new_size * 2 + subst_lhs_len)); + strcpy (new + j, subst_lhs); + j += subst_lhs_len; + } + else + { + /* a single backslash protects the `&' from lhs interpolation */ + if (subst_rhs[i] == '\\' && subst_rhs[i + 1] == '&') + i++; + if (j >= new_size) + new = (char *)xrealloc (new, new_size *= 2); + new[j++] = subst_rhs[i]; + } + } + new[j] = '\0'; + free (subst_rhs); + subst_rhs = new; + subst_rhs_len = j; +} + +/* Expand the bulk of a history specifier starting at STRING[START]. + Returns 0 if everything is OK, -1 if an error occurred, and 1 + if the `p' modifier was supplied and the caller should just print + the returned string. Returns the new index into string in + *END_INDEX_PTR, and the expanded specifier in *RET_STRING. */ +static int +history_expand_internal (string, start, end_index_ptr, ret_string, current_line) + char *string; + int start, *end_index_ptr; + char **ret_string; + char *current_line; /* for !# */ +{ + int i, n, starting_index; + int substitute_globally, subst_bywords, want_quotes, print_only; + char *event, *temp, *result, *tstr, *t, c, *word_spec; + int result_len; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps; + + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + result = (char *)xmalloc (result_len = 128); + + i = start; + + /* If it is followed by something that starts a word specifier, + then !! is implied as the event specifier. */ + + if (member (string[i + 1], ":$*%^")) + { + char fake_s[3]; + int fake_i = 0; + i++; + fake_s[0] = fake_s[1] = history_expansion_char; + fake_s[2] = '\0'; + event = get_history_event (fake_s, &fake_i, 0); + } + else if (string[i + 1] == '#') + { + i += 2; + event = current_line; + } + else + { + int quoted_search_delimiter = 0; + + /* If the character before this `!' is a double or single + quote, then this expansion takes place inside of the + quoted string. If we have to search for some text ("!foo"), + allow the delimiter to end the search string. */ +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int c, l; + l = _rl_find_prev_mbchar (string, i, MB_FIND_ANY); + c = string[l]; + /* XXX - original patch had i - 1 ??? If i == 0 it would fail. */ + if (i && (c == '\'' || c == '"')) + quoted_search_delimiter = c; + } + else +#endif /* HANDLE_MULTIBYTE */ + if (i && (string[i - 1] == '\'' || string[i - 1] == '"')) + quoted_search_delimiter = string[i - 1]; + + event = get_history_event (string, &i, quoted_search_delimiter); + } + + if (event == 0) + { + *ret_string = hist_error (string, start, i, EVENT_NOT_FOUND); + free (result); + return (-1); + } + + /* If a word specifier is found, then do what that requires. */ + starting_index = i; + word_spec = get_history_word_specifier (string, event, &i); + + /* There is no such thing as a `malformed word specifier'. However, + it is possible for a specifier that has no match. In that case, + we complain. */ + if (word_spec == (char *)&error_pointer) + { + *ret_string = hist_error (string, starting_index, i, BAD_WORD_SPEC); + free (result); + return (-1); + } + + /* If no word specifier, than the thing of interest was the event. */ + temp = word_spec ? savestring (word_spec) : savestring (event); + FREE (word_spec); + + /* Perhaps there are other modifiers involved. Do what they say. */ + want_quotes = substitute_globally = subst_bywords = print_only = 0; + starting_index = i; + + while (string[i] == ':') + { + c = string[i + 1]; + + if (c == 'g' || c == 'a') + { + substitute_globally = 1; + i++; + c = string[i + 1]; + } + else if (c == 'G') + { + subst_bywords = 1; + i++; + c = string[i + 1]; + } + + switch (c) + { + default: + *ret_string = hist_error (string, i+1, i+2, BAD_MODIFIER); + free (result); + free (temp); + return -1; + + case 'q': + want_quotes = 'q'; + break; + + case 'x': + want_quotes = 'x'; + break; + + /* :p means make this the last executed line. So we + return an error state after adding this line to the + history. */ + case 'p': + print_only++; + break; + + /* :t discards all but the last part of the pathname. */ + case 't': + tstr = strrchr (temp, '/'); + if (tstr) + { + tstr++; + t = savestring (tstr); + free (temp); + temp = t; + } + break; + + /* :h discards the last part of a pathname. */ + case 'h': + tstr = strrchr (temp, '/'); + if (tstr) + *tstr = '\0'; + break; + + /* :r discards the suffix. */ + case 'r': + tstr = strrchr (temp, '.'); + if (tstr) + *tstr = '\0'; + break; + + /* :e discards everything but the suffix. */ + case 'e': + tstr = strrchr (temp, '.'); + if (tstr) + { + t = savestring (tstr); + free (temp); + temp = t; + } + break; + + /* :s/this/that substitutes `that' for the first + occurrence of `this'. :gs/this/that substitutes `that' + for each occurrence of `this'. :& repeats the last + substitution. :g& repeats the last substitution + globally. */ + + case '&': + case 's': + { + char *new_event; + int delimiter, failed, si, l_temp, ws, we; + + if (c == 's') + { + if (i + 2 < (int)strlen (string)) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + _rl_adjust_point (string, i + 2, &ps); + if (_rl_get_char_len (string + i + 2, &ps) > 1) + delimiter = 0; + else + delimiter = string[i + 2]; + } + else +#endif /* HANDLE_MULTIBYTE */ + delimiter = string[i + 2]; + } + else + break; /* no search delimiter */ + + i += 3; + + t = get_subst_pattern (string, &i, delimiter, 0, &subst_lhs_len); + /* An empty substitution lhs with no previous substitution + uses the last search string as the lhs. */ + if (t) + { + FREE (subst_lhs); + subst_lhs = t; + } + else if (!subst_lhs) + { + if (search_string && *search_string) + { + subst_lhs = savestring (search_string); + subst_lhs_len = strlen (subst_lhs); + } + else + { + subst_lhs = (char *) NULL; + subst_lhs_len = 0; + } + } + + FREE (subst_rhs); + subst_rhs = get_subst_pattern (string, &i, delimiter, 1, &subst_rhs_len); + + /* If `&' appears in the rhs, it's supposed to be replaced + with the lhs. */ + if (member ('&', subst_rhs)) + postproc_subst_rhs (); + } + else + i += 2; + + /* If there is no lhs, the substitution can't succeed. */ + if (subst_lhs_len == 0) + { + *ret_string = hist_error (string, starting_index, i, NO_PREV_SUBST); + free (result); + free (temp); + return -1; + } + + l_temp = strlen (temp); + /* Ignore impossible cases. */ + if (subst_lhs_len > l_temp) + { + *ret_string = hist_error (string, starting_index, i, SUBST_FAILED); + free (result); + free (temp); + return (-1); + } + + /* Find the first occurrence of THIS in TEMP. */ + /* Substitute SUBST_RHS for SUBST_LHS in TEMP. There are three + cases to consider: + + 1. substitute_globally == subst_bywords == 0 + 2. substitute_globally == 1 && subst_bywords == 0 + 3. substitute_globally == 0 && subst_bywords == 1 + + In the first case, we substitute for the first occurrence only. + In the second case, we substitute for every occurrence. + In the third case, we tokenize into words and substitute the + first occurrence of each word. */ + + si = we = 0; + for (failed = 1; (si + subst_lhs_len) <= l_temp; si++) + { + /* First skip whitespace and find word boundaries if + we're past the end of the word boundary we found + the last time. */ + if (subst_bywords && si > we) + { + for (; temp[si] && whitespace (temp[si]); si++) + ; + ws = si; + we = history_tokenize_word (temp, si); + } + + if (STREQN (temp+si, subst_lhs, subst_lhs_len)) + { + int len = subst_rhs_len - subst_lhs_len + l_temp; + new_event = (char *)xmalloc (1 + len); + strncpy (new_event, temp, si); + strncpy (new_event + si, subst_rhs, subst_rhs_len); + strncpy (new_event + si + subst_rhs_len, + temp + si + subst_lhs_len, + l_temp - (si + subst_lhs_len)); + new_event[len] = '\0'; + free (temp); + temp = new_event; + + failed = 0; + + if (substitute_globally) + { + /* Reported to fix a bug that causes it to skip every + other match when matching a single character. Was + si += subst_rhs_len previously. */ + si += subst_rhs_len - 1; + l_temp = strlen (temp); + substitute_globally++; + continue; + } + else if (subst_bywords) + { + si = we; + l_temp = strlen (temp); + continue; + } + else + break; + } + } + + if (substitute_globally > 1) + { + substitute_globally = 0; + continue; /* don't want to increment i */ + } + + if (failed == 0) + continue; /* don't want to increment i */ + + *ret_string = hist_error (string, starting_index, i, SUBST_FAILED); + free (result); + free (temp); + return (-1); + } + } + i += 2; + } + /* Done with modfiers. */ + /* Believe it or not, we have to back the pointer up by one. */ + --i; + + if (want_quotes) + { + char *x; + + if (want_quotes == 'q') + x = sh_single_quote (temp); + else if (want_quotes == 'x') + x = quote_breaks (temp); + else + x = savestring (temp); + + free (temp); + temp = x; + } + + n = strlen (temp); + if (n >= result_len) + result = (char *)xrealloc (result, n + 2); + strcpy (result, temp); + free (temp); + + *end_index_ptr = i; + *ret_string = result; + return (print_only); +} + +/* Expand the string STRING, placing the result into OUTPUT, a pointer + to a string. Returns: + + -1) If there was an error in expansion. + 0) If no expansions took place (or, if the only change in + the text was the de-slashifying of the history expansion + character) + 1) If expansions did take place + 2) If the `p' modifier was given and the caller should print the result + + If an error ocurred in expansion, then OUTPUT contains a descriptive + error message. */ + +#define ADD_STRING(s) \ + do \ + { \ + int sl = strlen (s); \ + j += sl; \ + if (j >= result_len) \ + { \ + while (j >= result_len) \ + result_len += 128; \ + result = (char *)xrealloc (result, result_len); \ + } \ + strcpy (result + j - sl, s); \ + } \ + while (0) + +#define ADD_CHAR(c) \ + do \ + { \ + if (j >= result_len - 1) \ + result = (char *)xrealloc (result, result_len += 64); \ + result[j++] = c; \ + result[j] = '\0'; \ + } \ + while (0) + +int +history_expand (hstring, output) + char *hstring; + char **output; +{ + register int j; + int i, r, l, passc, cc, modified, eindex, only_printing, dquote; + char *string; + + /* The output string, and its length. */ + int result_len; + char *result; + +#if defined (HANDLE_MULTIBYTE) + char mb[MB_LEN_MAX]; + mbstate_t ps; +#endif + + /* Used when adding the string. */ + char *temp; + + if (output == 0) + return 0; + + /* Setting the history expansion character to 0 inhibits all + history expansion. */ + if (history_expansion_char == 0) + { + *output = savestring (hstring); + return (0); + } + + /* Prepare the buffer for printing error messages. */ + result = (char *)xmalloc (result_len = 256); + result[0] = '\0'; + + only_printing = modified = 0; + l = strlen (hstring); + + /* Grovel the string. Only backslash and single quotes can quote the + history escape character. We also handle arg specifiers. */ + + /* Before we grovel forever, see if the history_expansion_char appears + anywhere within the text. */ + + /* The quick substitution character is a history expansion all right. That + is to say, "^this^that^" is equivalent to "!!:s^this^that^", and in fact, + that is the substitution that we do. */ + if (hstring[0] == history_subst_char) + { + string = (char *)xmalloc (l + 5); + + string[0] = string[1] = history_expansion_char; + string[2] = ':'; + string[3] = 's'; + strcpy (string + 4, hstring); + l += 4; + } + else + { +#if defined (HANDLE_MULTIBYTE) + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + string = hstring; + /* If not quick substitution, still maybe have to do expansion. */ + + /* `!' followed by one of the characters in history_no_expand_chars + is NOT an expansion. */ + for (i = dquote = 0; string[i]; i++) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int v; + v = _rl_get_char_len (string + i, &ps); + if (v > 1) + { + i += v - 1; + continue; + } + } +#endif /* HANDLE_MULTIBYTE */ + + cc = string[i + 1]; + /* The history_comment_char, if set, appearing at the beginning + of a word signifies that the rest of the line should not have + history expansion performed on it. + Skip the rest of the line and break out of the loop. */ + if (history_comment_char && string[i] == history_comment_char && + (i == 0 || member (string[i - 1], history_word_delimiters))) + { + while (string[i]) + i++; + break; + } + else if (string[i] == history_expansion_char) + { + if (!cc || member (cc, history_no_expand_chars)) + continue; + /* If the calling application has set + history_inhibit_expansion_function to a function that checks + for special cases that should not be history expanded, + call the function and skip the expansion if it returns a + non-zero value. */ + else if (history_inhibit_expansion_function && + (*history_inhibit_expansion_function) (string, i)) + continue; + else + break; + } + /* Shell-like quoting: allow backslashes to quote double quotes + inside a double-quoted string. */ + else if (dquote && string[i] == '\\' && cc == '"') + i++; + /* More shell-like quoting: if we're paying attention to single + quotes and letting them quote the history expansion character, + then we need to pay attention to double quotes, because single + quotes are not special inside double-quoted strings. */ + else if (history_quotes_inhibit_expansion && string[i] == '"') + { + dquote = 1 - dquote; + } + else if (dquote == 0 && history_quotes_inhibit_expansion && string[i] == '\'') + { + /* If this is bash, single quotes inhibit history expansion. */ + i++; + hist_string_extract_single_quoted (string, &i); + } + else if (history_quotes_inhibit_expansion && string[i] == '\\') + { + /* If this is bash, allow backslashes to quote single + quotes and the history expansion character. */ + if (cc == '\'' || cc == history_expansion_char) + i++; + } + + } + + if (string[i] != history_expansion_char) + { + free (result); + *output = savestring (string); + return (0); + } + } + + /* Extract and perform the substitution. */ + for (passc = dquote = i = j = 0; i < l; i++) + { + int tchar = string[i]; + + if (passc) + { + passc = 0; + ADD_CHAR (tchar); + continue; + } + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int k, c; + + c = tchar; + memset (mb, 0, sizeof (mb)); + for (k = 0; k < MB_LEN_MAX; k++) + { + mb[k] = (char)c; + memset (&ps, 0, sizeof (mbstate_t)); + if (_rl_get_char_len (mb, &ps) == -2) + c = string[++i]; + else + break; + } + if (strlen (mb) > 1) + { + ADD_STRING (mb); + break; + } + } +#endif /* HANDLE_MULTIBYTE */ + + if (tchar == history_expansion_char) + tchar = -3; + else if (tchar == history_comment_char) + tchar = -2; + + switch (tchar) + { + default: + ADD_CHAR (string[i]); + break; + + case '\\': + passc++; + ADD_CHAR (tchar); + break; + + case '"': + dquote = 1 - dquote; + ADD_CHAR (tchar); + break; + + case '\'': + { + /* If history_quotes_inhibit_expansion is set, single quotes + inhibit history expansion. */ + if (dquote == 0 && history_quotes_inhibit_expansion) + { + int quote, slen; + + quote = i++; + hist_string_extract_single_quoted (string, &i); + + slen = i - quote + 2; + temp = (char *)xmalloc (slen); + strncpy (temp, string + quote, slen); + temp[slen - 1] = '\0'; + ADD_STRING (temp); + free (temp); + } + else + ADD_CHAR (string[i]); + break; + } + + case -2: /* history_comment_char */ + if (i == 0 || member (string[i - 1], history_word_delimiters)) + { + temp = (char *)xmalloc (l - i + 1); + strcpy (temp, string + i); + ADD_STRING (temp); + free (temp); + i = l; + } + else + ADD_CHAR (string[i]); + break; + + case -3: /* history_expansion_char */ + cc = string[i + 1]; + + /* If the history_expansion_char is followed by one of the + characters in history_no_expand_chars, then it is not a + candidate for expansion of any kind. */ + if (member (cc, history_no_expand_chars)) + { + ADD_CHAR (string[i]); + break; + } + +#if defined (NO_BANG_HASH_MODIFIERS) + /* There is something that is listed as a `word specifier' in csh + documentation which means `the expanded text to this point'. + That is not a word specifier, it is an event specifier. If we + don't want to allow modifiers with `!#', just stick the current + output line in again. */ + if (cc == '#') + { + if (result) + { + temp = (char *)xmalloc (1 + strlen (result)); + strcpy (temp, result); + ADD_STRING (temp); + free (temp); + } + i++; + break; + } +#endif + + r = history_expand_internal (string, i, &eindex, &temp, result); + if (r < 0) + { + *output = temp; + free (result); + if (string != hstring) + free (string); + return -1; + } + else + { + if (temp) + { + modified++; + if (*temp) + ADD_STRING (temp); + free (temp); + } + only_printing = r == 1; + i = eindex; + } + break; + } + } + + *output = result; + if (string != hstring) + free (string); + + if (only_printing) + { +#if 0 + add_history (result); +#endif + return (2); + } + + return (modified != 0); +} + +/* Return a consed string which is the word specified in SPEC, and found + in FROM. NULL is returned if there is no spec. The address of + ERROR_POINTER is returned if the word specified cannot be found. + CALLER_INDEX is the offset in SPEC to start looking; it is updated + to point to just after the last character parsed. */ +static char * +get_history_word_specifier (spec, from, caller_index) + char *spec, *from; + int *caller_index; +{ + register int i = *caller_index; + int first, last; + int expecting_word_spec = 0; + char *result; + + /* The range of words to return doesn't exist yet. */ + first = last = 0; + result = (char *)NULL; + + /* If we found a colon, then this *must* be a word specification. If + it isn't, then it is an error. */ + if (spec[i] == ':') + { + i++; + expecting_word_spec++; + } + + /* Handle special cases first. */ + + /* `%' is the word last searched for. */ + if (spec[i] == '%') + { + *caller_index = i + 1; + return (search_match ? savestring (search_match) : savestring ("")); + } + + /* `*' matches all of the arguments, but not the command. */ + if (spec[i] == '*') + { + *caller_index = i + 1; + result = history_arg_extract (1, '$', from); + return (result ? result : savestring ("")); + } + + /* `$' is last arg. */ + if (spec[i] == '$') + { + *caller_index = i + 1; + return (history_arg_extract ('$', '$', from)); + } + + /* Try to get FIRST and LAST figured out. */ + + if (spec[i] == '-') + first = 0; + else if (spec[i] == '^') + { + first = 1; + i++; + } + else if (_rl_digit_p (spec[i]) && expecting_word_spec) + { + for (first = 0; _rl_digit_p (spec[i]); i++) + first = (first * 10) + _rl_digit_value (spec[i]); + } + else + return ((char *)NULL); /* no valid `first' for word specifier */ + + if (spec[i] == '^' || spec[i] == '*') + { + last = (spec[i] == '^') ? 1 : '$'; /* x* abbreviates x-$ */ + i++; + } + else if (spec[i] != '-') + last = first; + else + { + i++; + + if (_rl_digit_p (spec[i])) + { + for (last = 0; _rl_digit_p (spec[i]); i++) + last = (last * 10) + _rl_digit_value (spec[i]); + } + else if (spec[i] == '$') + { + i++; + last = '$'; + } +#if 0 + else if (!spec[i] || spec[i] == ':') + /* check against `:' because there could be a modifier separator */ +#else + else + /* csh seems to allow anything to terminate the word spec here, + leaving it as an abbreviation. */ +#endif + last = -1; /* x- abbreviates x-$ omitting word `$' */ + } + + *caller_index = i; + + if (last >= first || last == '$' || last < 0) + result = history_arg_extract (first, last, from); + + return (result ? result : (char *)&error_pointer); +} + +/* Extract the args specified, starting at FIRST, and ending at LAST. + The args are taken from STRING. If either FIRST or LAST is < 0, + then make that arg count from the right (subtract from the number of + tokens, so that FIRST = -1 means the next to last token on the line). + If LAST is `$' the last arg from STRING is used. */ +char * +history_arg_extract (first, last, string) + int first, last; + const char *string; +{ + register int i, len; + char *result; + int size, offset; + char **list; + + /* XXX - think about making history_tokenize return a struct array, + each struct in array being a string and a length to avoid the + calls to strlen below. */ + if ((list = history_tokenize (string)) == NULL) + return ((char *)NULL); + + for (len = 0; list[len]; len++) + ; + + if (last < 0) + last = len + last - 1; + + if (first < 0) + first = len + first - 1; + + if (last == '$') + last = len - 1; + + if (first == '$') + first = len - 1; + + last++; + + if (first >= len || last > len || first < 0 || last < 0 || first > last) + result = ((char *)NULL); + else + { + for (size = 0, i = first; i < last; i++) + size += strlen (list[i]) + 1; + result = (char *)xmalloc (size + 1); + result[0] = '\0'; + + for (i = first, offset = 0; i < last; i++) + { + strcpy (result + offset, list[i]); + offset += strlen (list[i]); + if (i + 1 < last) + { + result[offset++] = ' '; + result[offset] = 0; + } + } + } + + for (i = 0; i < len; i++) + free (list[i]); + free (list); + + return (result); +} + +static int +history_tokenize_word (string, ind) + const char *string; + int ind; +{ + register int i; + int delimiter; + + i = ind; + delimiter = 0; + + if (member (string[i], "()\n")) + { + i++; + return i; + } + + if (member (string[i], "<>;&|$")) + { + int peek = string[i + 1]; + + if (peek == string[i] && peek != '$') + { + if (peek == '<' && string[i + 2] == '-') + i++; + i += 2; + return i; + } + else + { + if ((peek == '&' && (string[i] == '>' || string[i] == '<')) || + (peek == '>' && string[i] == '&') || + (peek == '(' && (string[i] == '>' || string[i] == '<')) || /* ) */ + (peek == '(' && string[i] == '$')) /* ) */ + { + i += 2; + return i; + } + } + + if (string[i] != '$') + { + i++; + return i; + } + } + + /* Get word from string + i; */ + + if (member (string[i], HISTORY_QUOTE_CHARACTERS)) + delimiter = string[i++]; + + for (; string[i]; i++) + { + if (string[i] == '\\' && string[i + 1] == '\n') + { + i++; + continue; + } + + if (string[i] == '\\' && delimiter != '\'' && + (delimiter != '"' || member (string[i], slashify_in_quotes))) + { + i++; + continue; + } + + if (delimiter && string[i] == delimiter) + { + delimiter = 0; + continue; + } + + if (!delimiter && (member (string[i], history_word_delimiters))) + break; + + if (!delimiter && member (string[i], HISTORY_QUOTE_CHARACTERS)) + delimiter = string[i]; + } + + return i; +} + +static char * +history_substring (string, start, end) + const char *string; + int start, end; +{ + register int len; + register char *result; + + len = end - start; + result = (char *)xmalloc (len + 1); + strncpy (result, string + start, len); + result[len] = '\0'; + return result; +} + +/* Parse STRING into tokens and return an array of strings. If WIND is + not -1 and INDP is not null, we also want the word surrounding index + WIND. The position in the returned array of strings is returned in + *INDP. */ +static char ** +history_tokenize_internal (string, wind, indp) + const char *string; + int wind, *indp; +{ + char **result; + register int i, start, result_index, size; + + /* If we're searching for a string that's not part of a word (e.g., " "), + make sure we set *INDP to a reasonable value. */ + if (indp && wind != -1) + *indp = -1; + + /* Get a token, and stuff it into RESULT. The tokens are split + exactly where the shell would split them. */ + for (i = result_index = size = 0, result = (char **)NULL; string[i]; ) + { + /* Skip leading whitespace. */ + for (; string[i] && whitespace (string[i]); i++) + ; + if (string[i] == 0 || string[i] == history_comment_char) + return (result); + + start = i; + + i = history_tokenize_word (string, start); + + /* If we have a non-whitespace delimiter character (which would not be + skipped by the loop above), use it and any adjacent delimiters to + make a separate field. Any adjacent white space will be skipped the + next time through the loop. */ + if (i == start && history_word_delimiters) + { + i++; + while (string[i] && member (string[i], history_word_delimiters)) + i++; + } + + /* If we are looking for the word in which the character at a + particular index falls, remember it. */ + if (indp && wind != -1 && wind >= start && wind < i) + *indp = result_index; + + if (result_index + 2 >= size) + result = (char **)xrealloc (result, ((size += 10) * sizeof (char *))); + + result[result_index++] = history_substring (string, start, i); + result[result_index] = (char *)NULL; + } + + return (result); +} + +/* Return an array of tokens, much as the shell might. The tokens are + parsed out of STRING. */ +char ** +history_tokenize (string) + const char *string; +{ + return (history_tokenize_internal (string, -1, (int *)NULL)); +} + +/* Find and return the word which contains the character at index IND + in the history line LINE. Used to save the word matched by the + last history !?string? search. */ +static char * +history_find_word (line, ind) + char *line; + int ind; +{ + char **words, *s; + int i, wind; + + words = history_tokenize_internal (line, ind, &wind); + if (wind == -1 || words == 0) + return ((char *)NULL); + s = words[wind]; + for (i = 0; i < wind; i++) + free (words[i]); + for (i = wind + 1; words[i]; i++) + free (words[i]); + free (words); + return s; +} diff --git a/external/gpl3/gdb/dist/readline/histfile.c b/external/gpl3/gdb/dist/readline/histfile.c new file mode 100644 index 000000000000..d1e54cc4c623 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/histfile.c @@ -0,0 +1,545 @@ +/* histfile.c - functions to manipulate the history file. */ + +/* Copyright (C) 1989-2003 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +/* The goal is to make the implementation transparent, so that you + don't have to know what data types are used, just what functions + you can call. I think I have done that. */ + +#define READLINE_LIBRARY + +#if defined (__TANDEM) +# include +#endif + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#include +#if ! defined (_MINIX) && defined (HAVE_SYS_FILE_H) +# include +#endif +#include "posixstat.h" +#include + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif + +#if defined (__EMX__) || defined (__CYGWIN__) +# undef HAVE_MMAP +#endif + +#ifdef HISTORY_USE_MMAP +# include + +# ifdef MAP_FILE +# define MAP_RFLAGS (MAP_FILE|MAP_PRIVATE) +# define MAP_WFLAGS (MAP_FILE|MAP_SHARED) +# else +# define MAP_RFLAGS MAP_PRIVATE +# define MAP_WFLAGS MAP_SHARED +# endif + +# ifndef MAP_FAILED +# define MAP_FAILED ((void *)-1) +# endif + +#endif /* HISTORY_USE_MMAP */ + +/* If we're compiling for __EMX__ (OS/2) or __CYGWIN__ (cygwin32 environment + on win 95/98/nt), we want to open files with O_BINARY mode so that there + is no \n -> \r\n conversion performed. On other systems, we don't want to + mess around with O_BINARY at all, so we ensure that it's defined to 0. */ +#if defined (__EMX__) || defined (__CYGWIN__) +# ifndef O_BINARY +# define O_BINARY 0 +# endif +#else /* !__EMX__ && !__CYGWIN__ */ +# undef O_BINARY +# define O_BINARY 0 +#endif /* !__EMX__ && !__CYGWIN__ */ + +#include +#if !defined (errno) +extern int errno; +#endif /* !errno */ + +#include "history.h" +#include "histlib.h" + +#include "rlshell.h" +#include "xmalloc.h" + +/* If non-zero, we write timestamps to the history file in history_do_write() */ +int history_write_timestamps = 0; + +/* Does S look like the beginning of a history timestamp entry? Placeholder + for more extensive tests. */ +#define HIST_TIMESTAMP_START(s) (*(s) == history_comment_char) + +/* Return the string that should be used in the place of this + filename. This only matters when you don't specify the + filename to read_history (), or write_history (). */ +static char * +history_filename (filename) + const char *filename; +{ + char *return_val; + const char *home; + int home_len; + + return_val = filename ? savestring (filename) : (char *)NULL; + + if (return_val) + return (return_val); + + home = sh_get_env_value ("HOME"); + + if (home == 0) + { + home = "."; + home_len = 1; + } + else + home_len = strlen (home); + + return_val = (char *)xmalloc (2 + home_len + 8); /* strlen(".history") == 8 */ + strcpy (return_val, home); + return_val[home_len] = '/'; +#if defined (__MSDOS__) + strcpy (return_val + home_len + 1, "_history"); +#else + strcpy (return_val + home_len + 1, ".history"); +#endif + + return (return_val); +} + +/* Add the contents of FILENAME to the history list, a line at a time. + If FILENAME is NULL, then read from ~/.history. Returns 0 if + successful, or errno if not. */ +int +read_history (filename) + const char *filename; +{ + return (read_history_range (filename, 0, -1)); +} + +/* Read a range of lines from FILENAME, adding them to the history list. + Start reading at the FROM'th line and end at the TO'th. If FROM + is zero, start at the beginning. If TO is less than FROM, read + until the end of the file. If FILENAME is NULL, then read from + ~/.history. Returns 0 if successful, or errno if not. */ +int +read_history_range (filename, from, to) + const char *filename; + int from, to; +{ + register char *line_start, *line_end, *p; + char *input, *buffer, *bufend, *last_ts; + int file, current_line, chars_read; + struct stat finfo; + size_t file_size; +#if defined (EFBIG) + int overflow_errno = EFBIG; +#elif defined (EOVERFLOW) + int overflow_errno = EOVERFLOW; +#else + int overflow_errno = EIO; +#endif + + buffer = last_ts = (char *)NULL; + input = history_filename (filename); + file = open (input, O_RDONLY|O_BINARY, 0666); + + if ((file < 0) || (fstat (file, &finfo) == -1)) + goto error_and_exit; + + file_size = (size_t)finfo.st_size; + + /* check for overflow on very large files */ + if (file_size != finfo.st_size || file_size + 1 < file_size) + { + errno = overflow_errno; + goto error_and_exit; + } + +#ifdef HISTORY_USE_MMAP + /* We map read/write and private so we can change newlines to NULs without + affecting the underlying object. */ + buffer = (char *)mmap (0, file_size, PROT_READ|PROT_WRITE, MAP_RFLAGS, file, 0); + if ((void *)buffer == MAP_FAILED) + { + errno = overflow_errno; + goto error_and_exit; + } + chars_read = file_size; +#else + buffer = (char *)malloc (file_size + 1); + if (buffer == 0) + { + errno = overflow_errno; + goto error_and_exit; + } + + chars_read = read (file, buffer, file_size); +#endif + if (chars_read < 0) + { + error_and_exit: + if (errno != 0) + chars_read = errno; + else + chars_read = EIO; + if (file >= 0) + close (file); + + FREE (input); +#ifndef HISTORY_USE_MMAP + FREE (buffer); +#endif + + return (chars_read); + } + + close (file); + + /* Set TO to larger than end of file if negative. */ + if (to < 0) + to = chars_read; + + /* Start at beginning of file, work to end. */ + bufend = buffer + chars_read; + current_line = 0; + + /* Skip lines until we are at FROM. */ + for (line_start = line_end = buffer; line_end < bufend && current_line < from; line_end++) + if (*line_end == '\n') + { + p = line_end + 1; + /* If we see something we think is a timestamp, continue with this + line. We should check more extensively here... */ + if (HIST_TIMESTAMP_START(p) == 0) + current_line++; + line_start = p; + } + + /* If there are lines left to gobble, then gobble them now. */ + for (line_end = line_start; line_end < bufend; line_end++) + if (*line_end == '\n') + { + if (line_end - 1 >= line_start && *(line_end - 1) == '\r') + *(line_end - 1) = '\0'; + else + *line_end = '\0'; + + if (*line_start) + { + if (HIST_TIMESTAMP_START(line_start) == 0) + { + add_history (line_start); + if (last_ts) + { + add_history_time (last_ts); + last_ts = NULL; + } + } + else + { + last_ts = line_start; + current_line--; + } + } + + current_line++; + + if (current_line >= to) + break; + + line_start = line_end + 1; + } + + FREE (input); +#ifndef HISTORY_USE_MMAP + FREE (buffer); +#else + munmap (buffer, file_size); +#endif + + return (0); +} + +/* Truncate the history file FNAME, leaving only LINES trailing lines. + If FNAME is NULL, then use ~/.history. Returns 0 on success, errno + on failure. */ +int +history_truncate_file (fname, lines) + const char *fname; + int lines; +{ + char *buffer, *filename, *bp, *bp1; /* bp1 == bp+1 */ + int file, chars_read, rv; + struct stat finfo; + size_t file_size; + + buffer = (char *)NULL; + filename = history_filename (fname); + file = open (filename, O_RDONLY|O_BINARY, 0666); + rv = 0; + + /* Don't try to truncate non-regular files. */ + if (file == -1 || fstat (file, &finfo) == -1) + { + rv = errno; + if (file != -1) + close (file); + goto truncate_exit; + } + + if (S_ISREG (finfo.st_mode) == 0) + { + close (file); +#ifdef EFTYPE + rv = EFTYPE; +#else + rv = EINVAL; +#endif + goto truncate_exit; + } + + file_size = (size_t)finfo.st_size; + + /* check for overflow on very large files */ + if (file_size != finfo.st_size || file_size + 1 < file_size) + { + close (file); +#if defined (EFBIG) + rv = errno = EFBIG; +#elif defined (EOVERFLOW) + rv = errno = EOVERFLOW; +#else + rv = errno = EINVAL; +#endif + goto truncate_exit; + } + + buffer = (char *)malloc (file_size + 1); + if (buffer == 0) + { + close (file); + goto truncate_exit; + } + + chars_read = read (file, buffer, file_size); + close (file); + + if (chars_read <= 0) + { + rv = (chars_read < 0) ? errno : 0; + goto truncate_exit; + } + + /* Count backwards from the end of buffer until we have passed + LINES lines. bp1 is set funny initially. But since bp[1] can't + be a comment character (since it's off the end) and *bp can't be + both a newline and the history comment character, it should be OK. */ + for (bp1 = bp = buffer + chars_read - 1; lines && bp > buffer; bp--) + { + if (*bp == '\n' && HIST_TIMESTAMP_START(bp1) == 0) + lines--; + bp1 = bp; + } + + /* If this is the first line, then the file contains exactly the + number of lines we want to truncate to, so we don't need to do + anything. It's the first line if we don't find a newline between + the current value of i and 0. Otherwise, write from the start of + this line until the end of the buffer. */ + for ( ; bp > buffer; bp--) + { + if (*bp == '\n' && HIST_TIMESTAMP_START(bp1) == 0) + { + bp++; + break; + } + bp1 = bp; + } + + /* Write only if there are more lines in the file than we want to + truncate to. */ + if (bp > buffer && ((file = open (filename, O_WRONLY|O_TRUNC|O_BINARY, 0600)) != -1)) + { + write (file, bp, chars_read - (bp - buffer)); + +#if defined (__BEOS__) + /* BeOS ignores O_TRUNC. */ + ftruncate (file, chars_read - (bp - buffer)); +#endif + + close (file); + } + + truncate_exit: + + FREE (buffer); + + free (filename); + return rv; +} + +/* Workhorse function for writing history. Writes NELEMENT entries + from the history list to FILENAME. OVERWRITE is non-zero if you + wish to replace FILENAME with the entries. */ +static int +history_do_write (filename, nelements, overwrite) + const char *filename; + int nelements, overwrite; +{ + register int i; + char *output; + int file, mode, rv; +#ifdef HISTORY_USE_MMAP + size_t cursize; + + mode = overwrite ? O_RDWR|O_CREAT|O_TRUNC|O_BINARY : O_RDWR|O_APPEND|O_BINARY; +#else + mode = overwrite ? O_WRONLY|O_CREAT|O_TRUNC|O_BINARY : O_WRONLY|O_APPEND|O_BINARY; +#endif + output = history_filename (filename); + rv = 0; + + if ((file = open (output, mode, 0600)) == -1) + { + FREE (output); + return (errno); + } + +#ifdef HISTORY_USE_MMAP + cursize = overwrite ? 0 : lseek (file, 0, SEEK_END); +#endif + + if (nelements > history_length) + nelements = history_length; + + /* Build a buffer of all the lines to write, and write them in one syscall. + Suggested by Peter Ho (peter@robosts.oxford.ac.uk). */ + { + HIST_ENTRY **the_history; /* local */ + register int j; + int buffer_size; + char *buffer; + + the_history = history_list (); + /* Calculate the total number of bytes to write. */ + for (buffer_size = 0, i = history_length - nelements; i < history_length; i++) +#if 0 + buffer_size += 2 + HISTENT_BYTES (the_history[i]); +#else + { + if (history_write_timestamps && the_history[i]->timestamp && the_history[i]->timestamp[0]) + buffer_size += strlen (the_history[i]->timestamp) + 1; + buffer_size += strlen (the_history[i]->line) + 1; + } +#endif + + /* Allocate the buffer, and fill it. */ +#ifdef HISTORY_USE_MMAP + if (ftruncate (file, buffer_size+cursize) == -1) + goto mmap_error; + buffer = (char *)mmap (0, buffer_size, PROT_READ|PROT_WRITE, MAP_WFLAGS, file, cursize); + if ((void *)buffer == MAP_FAILED) + { +mmap_error: + rv = errno; + FREE (output); + close (file); + return rv; + } +#else + buffer = (char *)malloc (buffer_size); + if (buffer == 0) + { + rv = errno; + FREE (output); + close (file); + return rv; + } +#endif + + for (j = 0, i = history_length - nelements; i < history_length; i++) + { + if (history_write_timestamps && the_history[i]->timestamp && the_history[i]->timestamp[0]) + { + strcpy (buffer + j, the_history[i]->timestamp); + j += strlen (the_history[i]->timestamp); + buffer[j++] = '\n'; + } + strcpy (buffer + j, the_history[i]->line); + j += strlen (the_history[i]->line); + buffer[j++] = '\n'; + } + +#ifdef HISTORY_USE_MMAP + if (msync (buffer, buffer_size, 0) != 0 || munmap (buffer, buffer_size) != 0) + rv = errno; +#else + if (write (file, buffer, buffer_size) < 0) + rv = errno; + free (buffer); +#endif + } + + close (file); + + FREE (output); + + return (rv); +} + +/* Append NELEMENT entries to FILENAME. The entries appended are from + the end of the list minus NELEMENTs up to the end of the list. */ +int +append_history (nelements, filename) + int nelements; + const char *filename; +{ + return (history_do_write (filename, nelements, HISTORY_APPEND)); +} + +/* Overwrite FILENAME with the current history. If FILENAME is NULL, + then write the history list to ~/.history. Values returned + are as in read_history ().*/ +int +write_history (filename) + const char *filename; +{ + return (history_do_write (filename, history_length, HISTORY_OVERWRITE)); +} diff --git a/external/gpl3/gdb/dist/readline/histlib.h b/external/gpl3/gdb/dist/readline/histlib.h new file mode 100644 index 000000000000..c39af71814c8 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/histlib.h @@ -0,0 +1,82 @@ +/* histlib.h -- internal definitions for the history library. */ +/* Copyright (C) 1989, 1992 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_HISTLIB_H_) +#define _HISTLIB_H_ + +#if defined (HAVE_STRING_H) +# include +#else +# include +#endif /* !HAVE_STRING_H */ + +#if !defined (STREQ) +#define STREQ(a, b) (((a)[0] == (b)[0]) && (strcmp ((a), (b)) == 0)) +#define STREQN(a, b, n) (((n) == 0) ? (1) \ + : ((a)[0] == (b)[0]) && (strncmp ((a), (b), (n)) == 0)) +#endif + +#ifndef savestring +#define savestring(x) strcpy (xmalloc (1 + strlen (x)), (x)) +#endif + +#ifndef whitespace +#define whitespace(c) (((c) == ' ') || ((c) == '\t')) +#endif + +#ifndef _rl_digit_p +#define _rl_digit_p(c) ((c) >= '0' && (c) <= '9') +#endif + +#ifndef _rl_digit_value +#define _rl_digit_value(c) ((c) - '0') +#endif + +#ifndef member +# ifndef strchr +extern char *strchr (); +# endif +#define member(c, s) ((c) ? ((char *)strchr ((s), (c)) != (char *)NULL) : 0) +#endif + +#ifndef FREE +# define FREE(x) if (x) free (x) +#endif + +/* Possible history errors passed to hist_error. */ +#define EVENT_NOT_FOUND 0 +#define BAD_WORD_SPEC 1 +#define SUBST_FAILED 2 +#define BAD_MODIFIER 3 +#define NO_PREV_SUBST 4 + +/* Possible definitions for history starting point specification. */ +#define ANCHORED_SEARCH 1 +#define NON_ANCHORED_SEARCH 0 + +/* Possible definitions for what style of writing the history file we want. */ +#define HISTORY_APPEND 0 +#define HISTORY_OVERWRITE 1 + +/* Some variable definitions shared across history source files. */ +extern int history_offset; + +#endif /* !_HISTLIB_H_ */ diff --git a/external/gpl3/gdb/dist/readline/history.c b/external/gpl3/gdb/dist/readline/history.c new file mode 100644 index 000000000000..a538f91c0d7b --- /dev/null +++ b/external/gpl3/gdb/dist/readline/history.c @@ -0,0 +1,441 @@ +/* history.c -- standalone history library */ + +/* Copyright (C) 1989-2005 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +/* The goal is to make the implementation transparent, so that you + don't have to know what data types are used, just what functions + you can call. I think I have done that. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_UNISTD_H) +# ifdef _MINIX +# include +# endif +# include +#endif + +#include "history.h" +#include "histlib.h" + +#include "xmalloc.h" + +/* The number of slots to increase the_history by. */ +#define DEFAULT_HISTORY_GROW_SIZE 50 + +static char *hist_inittime PARAMS((void)); + +/* **************************************************************** */ +/* */ +/* History Functions */ +/* */ +/* **************************************************************** */ + +/* An array of HIST_ENTRY. This is where we store the history. */ +static HIST_ENTRY **the_history = (HIST_ENTRY **)NULL; + +/* Non-zero means that we have enforced a limit on the amount of + history that we save. */ +static int history_stifled; + +/* The current number of slots allocated to the input_history. */ +static int history_size; + +/* If HISTORY_STIFLED is non-zero, then this is the maximum number of + entries to remember. */ +int history_max_entries; +int max_input_history; /* backwards compatibility */ + +/* The current location of the interactive history pointer. Just makes + life easier for outside callers. */ +int history_offset; + +/* The number of strings currently stored in the history list. */ +int history_length; + +/* The logical `base' of the history array. It defaults to 1. */ +int history_base = 1; + +/* Return the current HISTORY_STATE of the history. */ +HISTORY_STATE * +history_get_history_state () +{ + HISTORY_STATE *state; + + state = (HISTORY_STATE *)xmalloc (sizeof (HISTORY_STATE)); + state->entries = the_history; + state->offset = history_offset; + state->length = history_length; + state->size = history_size; + state->flags = 0; + if (history_stifled) + state->flags |= HS_STIFLED; + + return (state); +} + +/* Set the state of the current history array to STATE. */ +void +history_set_history_state (state) + HISTORY_STATE *state; +{ + the_history = state->entries; + history_offset = state->offset; + history_length = state->length; + history_size = state->size; + if (state->flags & HS_STIFLED) + history_stifled = 1; +} + +/* Begin a session in which the history functions might be used. This + initializes interactive variables. */ +void +using_history () +{ + history_offset = history_length; +} + +/* Return the number of bytes that the primary history entries are using. + This just adds up the lengths of the_history->lines and the associated + timestamps. */ +int +history_total_bytes () +{ + register int i, result; + + for (i = result = 0; the_history && the_history[i]; i++) + result += HISTENT_BYTES (the_history[i]); + + return (result); +} + +/* Returns the magic number which says what history element we are + looking at now. In this implementation, it returns history_offset. */ +int +where_history () +{ + return (history_offset); +} + +/* Make the current history item be the one at POS, an absolute index. + Returns zero if POS is out of range, else non-zero. */ +int +history_set_pos (pos) + int pos; +{ + if (pos > history_length || pos < 0 || !the_history) + return (0); + history_offset = pos; + return (1); +} + +/* Return the current history array. The caller has to be carefull, since this + is the actual array of data, and could be bashed or made corrupt easily. + The array is terminated with a NULL pointer. */ +HIST_ENTRY ** +history_list () +{ + return (the_history); +} + +/* Return the history entry at the current position, as determined by + history_offset. If there is no entry there, return a NULL pointer. */ +HIST_ENTRY * +current_history () +{ + return ((history_offset == history_length) || the_history == 0) + ? (HIST_ENTRY *)NULL + : the_history[history_offset]; +} + +/* Back up history_offset to the previous history entry, and return + a pointer to that entry. If there is no previous entry then return + a NULL pointer. */ +HIST_ENTRY * +previous_history () +{ + return history_offset ? the_history[--history_offset] : (HIST_ENTRY *)NULL; +} + +/* Move history_offset forward to the next history entry, and return + a pointer to that entry. If there is no next entry then return a + NULL pointer. */ +HIST_ENTRY * +next_history () +{ + return (history_offset == history_length) ? (HIST_ENTRY *)NULL : the_history[++history_offset]; +} + +/* Return the history entry which is logically at OFFSET in the history array. + OFFSET is relative to history_base. */ +HIST_ENTRY * +history_get (offset) + int offset; +{ + int local_index; + + local_index = offset - history_base; + return (local_index >= history_length || local_index < 0 || the_history == 0) + ? (HIST_ENTRY *)NULL + : the_history[local_index]; +} + +time_t +history_get_time (hist) + HIST_ENTRY *hist; +{ + char *ts; + time_t t; + + if (hist == 0 || hist->timestamp == 0) + return 0; + ts = hist->timestamp; + if (ts[0] != history_comment_char) + return 0; + t = (time_t) atol (ts + 1); /* XXX - should use strtol() here */ + return t; +} + +static char * +hist_inittime () +{ + time_t t; + char ts[64], *ret; + + t = (time_t) time ((time_t *)0); +#if defined (HAVE_VSNPRINTF) /* assume snprintf if vsnprintf exists */ + snprintf (ts, sizeof (ts) - 1, "X%lu", (unsigned long) t); +#else + sprintf (ts, "X%lu", (unsigned long) t); +#endif + ret = savestring (ts); + ret[0] = history_comment_char; + + return ret; +} + +/* Place STRING at the end of the history list. The data field + is set to NULL. */ +void +add_history (string) + const char *string; +{ + HIST_ENTRY *temp; + + if (history_stifled && (history_length == history_max_entries)) + { + register int i; + + /* If the history is stifled, and history_length is zero, + and it equals history_max_entries, we don't save items. */ + if (history_length == 0) + return; + + /* If there is something in the slot, then remove it. */ + if (the_history[0]) + (void) free_history_entry (the_history[0]); + + /* Copy the rest of the entries, moving down one slot. */ + for (i = 0; i < history_length; i++) + the_history[i] = the_history[i + 1]; + + history_base++; + } + else + { + if (history_size == 0) + { + history_size = DEFAULT_HISTORY_GROW_SIZE; + the_history = (HIST_ENTRY **)xmalloc (history_size * sizeof (HIST_ENTRY *)); + history_length = 1; + } + else + { + if (history_length == (history_size - 1)) + { + history_size += DEFAULT_HISTORY_GROW_SIZE; + the_history = (HIST_ENTRY **) + xrealloc (the_history, history_size * sizeof (HIST_ENTRY *)); + } + history_length++; + } + } + + temp = (HIST_ENTRY *)xmalloc (sizeof (HIST_ENTRY)); + temp->line = savestring (string); + temp->data = (char *)NULL; + + temp->timestamp = hist_inittime (); + + the_history[history_length] = (HIST_ENTRY *)NULL; + the_history[history_length - 1] = temp; +} + +/* Change the time stamp of the most recent history entry to STRING. */ +void +add_history_time (string) + const char *string; +{ + HIST_ENTRY *hs; + + hs = the_history[history_length - 1]; + FREE (hs->timestamp); + hs->timestamp = savestring (string); +} + +/* Free HIST and return the data so the calling application can free it + if necessary and desired. */ +histdata_t +free_history_entry (hist) + HIST_ENTRY *hist; +{ + histdata_t x; + + if (hist == 0) + return ((histdata_t) 0); + FREE (hist->line); + FREE (hist->timestamp); + x = hist->data; + free (hist); + return (x); +} + +/* Make the history entry at WHICH have LINE and DATA. This returns + the old entry so you can dispose of the data. In the case of an + invalid WHICH, a NULL pointer is returned. */ +HIST_ENTRY * +replace_history_entry (which, line, data) + int which; + const char *line; + histdata_t data; +{ + HIST_ENTRY *temp, *old_value; + + if (which < 0 || which >= history_length) + return ((HIST_ENTRY *)NULL); + + temp = (HIST_ENTRY *)xmalloc (sizeof (HIST_ENTRY)); + old_value = the_history[which]; + + temp->line = savestring (line); + temp->data = data; + temp->timestamp = savestring (old_value->timestamp); + the_history[which] = temp; + + return (old_value); +} + +/* Remove history element WHICH from the history. The removed + element is returned to you so you can free the line, data, + and containing structure. */ +HIST_ENTRY * +remove_history (which) + int which; +{ + HIST_ENTRY *return_value; + register int i; + + if (which < 0 || which >= history_length || history_length == 0 || the_history == 0) + return ((HIST_ENTRY *)NULL); + + return_value = the_history[which]; + + for (i = which; i < history_length; i++) + the_history[i] = the_history[i + 1]; + + history_length--; + + return (return_value); +} + +/* Stifle the history list, remembering only MAX number of lines. */ +void +stifle_history (max) + int max; +{ + register int i, j; + + if (max < 0) + max = 0; + + if (history_length > max) + { + /* This loses because we cannot free the data. */ + for (i = 0, j = history_length - max; i < j; i++) + free_history_entry (the_history[i]); + + history_base = i; + for (j = 0, i = history_length - max; j < max; i++, j++) + the_history[j] = the_history[i]; + the_history[j] = (HIST_ENTRY *)NULL; + history_length = j; + } + + history_stifled = 1; + max_input_history = history_max_entries = max; +} + +/* Stop stifling the history. This returns the previous maximum + number of history entries. The value is positive if the history + was stifled, negative if it wasn't. */ +int +unstifle_history () +{ + if (history_stifled) + { + history_stifled = 0; + return (history_max_entries); + } + else + return (-history_max_entries); +} + +int +history_is_stifled () +{ + return (history_stifled); +} + +void +clear_history () +{ + register int i; + + /* This loses because we cannot free the data. */ + for (i = 0; i < history_length; i++) + { + free_history_entry (the_history[i]); + the_history[i] = (HIST_ENTRY *)NULL; + } + + history_offset = history_length = 0; +} diff --git a/external/gpl3/gdb/dist/readline/history.h b/external/gpl3/gdb/dist/readline/history.h new file mode 100644 index 000000000000..14ca2a996c72 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/history.h @@ -0,0 +1,266 @@ +/* history.h -- the names of functions that you can call in history. */ +/* Copyright (C) 1989-2003 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _HISTORY_H_ +#define _HISTORY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* XXX - for history timestamp code */ + +#if defined READLINE_LIBRARY +# include "rlstdc.h" +# include "rltypedefs.h" +#else +# include +# include +#endif + +#ifdef __STDC__ +typedef void *histdata_t; +#else +typedef char *histdata_t; +#endif + +/* The structure used to store a history entry. */ +typedef struct _hist_entry { + char *line; + char *timestamp; /* char * rather than time_t for read/write */ + histdata_t data; +} HIST_ENTRY; + +/* Size of the history-library-managed space in history entry HS. */ +#define HISTENT_BYTES(hs) (strlen ((hs)->line) + strlen ((hs)->timestamp)) + +/* A structure used to pass the current state of the history stuff around. */ +typedef struct _hist_state { + HIST_ENTRY **entries; /* Pointer to the entries themselves. */ + int offset; /* The location pointer within this array. */ + int length; /* Number of elements within this array. */ + int size; /* Number of slots allocated to this array. */ + int flags; +} HISTORY_STATE; + +/* Flag values for the `flags' member of HISTORY_STATE. */ +#define HS_STIFLED 0x01 + +/* Initialization and state management. */ + +/* Begin a session in which the history functions might be used. This + just initializes the interactive variables. */ +extern void using_history PARAMS((void)); + +/* Return the current HISTORY_STATE of the history. */ +extern HISTORY_STATE *history_get_history_state PARAMS((void)); + +/* Set the state of the current history array to STATE. */ +extern void history_set_history_state PARAMS((HISTORY_STATE *)); + +/* Manage the history list. */ + +/* Place STRING at the end of the history list. + The associated data field (if any) is set to NULL. */ +extern void add_history PARAMS((const char *)); + +/* Change the timestamp associated with the most recent history entry to + STRING. */ +extern void add_history_time PARAMS((const char *)); + +/* A reasonably useless function, only here for completeness. WHICH + is the magic number that tells us which element to delete. The + elements are numbered from 0. */ +extern HIST_ENTRY *remove_history PARAMS((int)); + +/* Free the history entry H and return any application-specific data + associated with it. */ +extern histdata_t free_history_entry PARAMS((HIST_ENTRY *)); + +/* Make the history entry at WHICH have LINE and DATA. This returns + the old entry so you can dispose of the data. In the case of an + invalid WHICH, a NULL pointer is returned. */ +extern HIST_ENTRY *replace_history_entry PARAMS((int, const char *, histdata_t)); + +/* Clear the history list and start over. */ +extern void clear_history PARAMS((void)); + +/* Stifle the history list, remembering only MAX number of entries. */ +extern void stifle_history PARAMS((int)); + +/* Stop stifling the history. This returns the previous amount the + history was stifled by. The value is positive if the history was + stifled, negative if it wasn't. */ +extern int unstifle_history PARAMS((void)); + +/* Return 1 if the history is stifled, 0 if it is not. */ +extern int history_is_stifled PARAMS((void)); + +/* Information about the history list. */ + +/* Return a NULL terminated array of HIST_ENTRY which is the current input + history. Element 0 of this list is the beginning of time. If there + is no history, return NULL. */ +extern HIST_ENTRY **history_list PARAMS((void)); + +/* Returns the number which says what history element we are now + looking at. */ +extern int where_history PARAMS((void)); + +/* Return the history entry at the current position, as determined by + history_offset. If there is no entry there, return a NULL pointer. */ +extern HIST_ENTRY *current_history PARAMS((void)); + +/* Return the history entry which is logically at OFFSET in the history + array. OFFSET is relative to history_base. */ +extern HIST_ENTRY *history_get PARAMS((int)); + +/* Return the timestamp associated with the HIST_ENTRY * passed as an + argument */ +extern time_t history_get_time PARAMS((HIST_ENTRY *)); + +/* Return the number of bytes that the primary history entries are using. + This just adds up the lengths of the_history->lines. */ +extern int history_total_bytes PARAMS((void)); + +/* Moving around the history list. */ + +/* Set the position in the history list to POS. */ +extern int history_set_pos PARAMS((int)); + +/* Back up history_offset to the previous history entry, and return + a pointer to that entry. If there is no previous entry, return + a NULL pointer. */ +extern HIST_ENTRY *previous_history PARAMS((void)); + +/* Move history_offset forward to the next item in the input_history, + and return the a pointer to that entry. If there is no next entry, + return a NULL pointer. */ +extern HIST_ENTRY *next_history PARAMS((void)); + +/* Searching the history list. */ + +/* Search the history for STRING, starting at history_offset. + If DIRECTION < 0, then the search is through previous entries, + else through subsequent. If the string is found, then + current_history () is the history entry, and the value of this function + is the offset in the line of that history entry that the string was + found in. Otherwise, nothing is changed, and a -1 is returned. */ +extern int history_search PARAMS((const char *, int)); + +/* Search the history for STRING, starting at history_offset. + The search is anchored: matching lines must begin with string. + DIRECTION is as in history_search(). */ +extern int history_search_prefix PARAMS((const char *, int)); + +/* Search for STRING in the history list, starting at POS, an + absolute index into the list. DIR, if negative, says to search + backwards from POS, else forwards. + Returns the absolute index of the history element where STRING + was found, or -1 otherwise. */ +extern int history_search_pos PARAMS((const char *, int, int)); + +/* Managing the history file. */ + +/* Add the contents of FILENAME to the history list, a line at a time. + If FILENAME is NULL, then read from ~/.history. Returns 0 if + successful, or errno if not. */ +extern int read_history PARAMS((const char *)); + +/* Read a range of lines from FILENAME, adding them to the history list. + Start reading at the FROM'th line and end at the TO'th. If FROM + is zero, start at the beginning. If TO is less than FROM, read + until the end of the file. If FILENAME is NULL, then read from + ~/.history. Returns 0 if successful, or errno if not. */ +extern int read_history_range PARAMS((const char *, int, int)); + +/* Write the current history to FILENAME. If FILENAME is NULL, + then write the history list to ~/.history. Values returned + are as in read_history (). */ +extern int write_history PARAMS((const char *)); + +/* Append NELEMENT entries to FILENAME. The entries appended are from + the end of the list minus NELEMENTs up to the end of the list. */ +extern int append_history PARAMS((int, const char *)); + +/* Truncate the history file, leaving only the last NLINES lines. */ +extern int history_truncate_file PARAMS((const char *, int)); + +/* History expansion. */ + +/* Expand the string STRING, placing the result into OUTPUT, a pointer + to a string. Returns: + + 0) If no expansions took place (or, if the only change in + the text was the de-slashifying of the history expansion + character) + 1) If expansions did take place + -1) If there was an error in expansion. + 2) If the returned line should just be printed. + + If an error ocurred in expansion, then OUTPUT contains a descriptive + error message. */ +extern int history_expand PARAMS((char *, char **)); + +/* Extract a string segment consisting of the FIRST through LAST + arguments present in STRING. Arguments are broken up as in + the shell. */ +extern char *history_arg_extract PARAMS((int, int, const char *)); + +/* Return the text of the history event beginning at the current + offset into STRING. Pass STRING with *INDEX equal to the + history_expansion_char that begins this specification. + DELIMITING_QUOTE is a character that is allowed to end the string + specification for what to search for in addition to the normal + characters `:', ` ', `\t', `\n', and sometimes `?'. */ +extern char *get_history_event PARAMS((const char *, int *, int)); + +/* Return an array of tokens, much as the shell might. The tokens are + parsed out of STRING. */ +extern char **history_tokenize PARAMS((const char *)); + +/* Exported history variables. */ +extern int history_base; +extern int history_length; +extern int history_max_entries; +extern char history_expansion_char; +extern char history_subst_char; +extern char *history_word_delimiters; +extern char history_comment_char; +extern char *history_no_expand_chars; +extern char *history_search_delimiter_chars; +extern int history_quotes_inhibit_expansion; + +extern int history_write_timestamps; + +/* Backwards compatibility */ +extern int max_input_history; + +/* If set, this function is called to decide whether or not a particular + history expansion should be treated as a special case for the calling + application and not expanded. */ +extern rl_linebuf_func_t *history_inhibit_expansion_function; + +#ifdef __cplusplus +} +#endif + +#endif /* !_HISTORY_H_ */ diff --git a/external/gpl3/gdb/dist/readline/histsearch.c b/external/gpl3/gdb/dist/readline/histsearch.c new file mode 100644 index 000000000000..1cc5875a4b41 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/histsearch.c @@ -0,0 +1,195 @@ +/* histsearch.c -- searching the history list. */ + +/* Copyright (C) 1989, 1992 Free Software Foundation, Inc. + + This file contains the GNU History Library (the Library), a set of + routines for managing the text of previously typed lines. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_UNISTD_H) +# ifdef _MINIX +# include +# endif +# include +#endif + +#include "history.h" +#include "histlib.h" + +/* The list of alternate characters that can delimit a history search + string. */ +char *history_search_delimiter_chars = (char *)NULL; + +static int history_search_internal PARAMS((const char *, int, int)); + +/* Search the history for STRING, starting at history_offset. + If DIRECTION < 0, then the search is through previous entries, else + through subsequent. If ANCHORED is non-zero, the string must + appear at the beginning of a history line, otherwise, the string + may appear anywhere in the line. If the string is found, then + current_history () is the history entry, and the value of this + function is the offset in the line of that history entry that the + string was found in. Otherwise, nothing is changed, and a -1 is + returned. */ + +static int +history_search_internal (string, direction, anchored) + const char *string; + int direction, anchored; +{ + register int i, reverse; + register char *line; + register int line_index; + int string_len; + HIST_ENTRY **the_history; /* local */ + + i = history_offset; + reverse = (direction < 0); + + /* Take care of trivial cases first. */ + if (string == 0 || *string == '\0') + return (-1); + + if (!history_length || ((i >= history_length) && !reverse)) + return (-1); + + if (reverse && (i >= history_length)) + i = history_length - 1; + +#define NEXT_LINE() do { if (reverse) i--; else i++; } while (0) + + the_history = history_list (); + string_len = strlen (string); + while (1) + { + /* Search each line in the history list for STRING. */ + + /* At limit for direction? */ + if ((reverse && i < 0) || (!reverse && i == history_length)) + return (-1); + + line = the_history[i]->line; + line_index = strlen (line); + + /* If STRING is longer than line, no match. */ + if (string_len > line_index) + { + NEXT_LINE (); + continue; + } + + /* Handle anchored searches first. */ + if (anchored == ANCHORED_SEARCH) + { + if (STREQN (string, line, string_len)) + { + history_offset = i; + return (0); + } + + NEXT_LINE (); + continue; + } + + /* Do substring search. */ + if (reverse) + { + line_index -= string_len; + + while (line_index >= 0) + { + if (STREQN (string, line + line_index, string_len)) + { + history_offset = i; + return (line_index); + } + line_index--; + } + } + else + { + register int limit; + + limit = line_index - string_len + 1; + line_index = 0; + + while (line_index < limit) + { + if (STREQN (string, line + line_index, string_len)) + { + history_offset = i; + return (line_index); + } + line_index++; + } + } + NEXT_LINE (); + } +} + +/* Do a non-anchored search for STRING through the history in DIRECTION. */ +int +history_search (string, direction) + const char *string; + int direction; +{ + return (history_search_internal (string, direction, NON_ANCHORED_SEARCH)); +} + +/* Do an anchored search for string through the history in DIRECTION. */ +int +history_search_prefix (string, direction) + const char *string; + int direction; +{ + return (history_search_internal (string, direction, ANCHORED_SEARCH)); +} + +/* Search for STRING in the history list. DIR is < 0 for searching + backwards. POS is an absolute index into the history list at + which point to begin searching. */ +int +history_search_pos (string, dir, pos) + const char *string; + int dir, pos; +{ + int ret, old; + + old = where_history (); + history_set_pos (pos); + if (history_search (string, dir) == -1) + { + history_set_pos (old); + return (-1); + } + ret = where_history (); + history_set_pos (old); + return ret; +} diff --git a/external/gpl3/gdb/dist/readline/input.c b/external/gpl3/gdb/dist/readline/input.c new file mode 100644 index 000000000000..9f8905384d27 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/input.c @@ -0,0 +1,587 @@ +/* input.c -- character input functions for readline. */ + +/* Copyright (C) 1994-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (__TANDEM) +# include +#endif + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#if defined (HAVE_SYS_FILE_H) +# include +#endif /* HAVE_SYS_FILE_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_SELECT) +# if !defined (HAVE_SYS_SELECT_H) || !defined (M_UNIX) +# include +# endif +#endif /* HAVE_SELECT */ +#if defined (HAVE_SYS_SELECT_H) +# include +#endif + +#if defined (FIONREAD_IN_SYS_IOCTL) +# include +#endif + +#include +#include + +#if !defined (errno) +extern int errno; +#endif /* !errno */ + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +/* Some standard library routines. */ +#include "readline.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +/* What kind of non-blocking I/O do we have? */ +#if !defined (O_NDELAY) && defined (O_NONBLOCK) +# define O_NDELAY O_NONBLOCK /* Posix style */ +#endif + +/* Non-null means it is a pointer to a function to run while waiting for + character input. */ +rl_hook_func_t *rl_event_hook = (rl_hook_func_t *)NULL; + +rl_getc_func_t *rl_getc_function = rl_getc; + +static int _keyboard_input_timeout = 100000; /* 0.1 seconds; it's in usec */ + +static int ibuffer_space PARAMS((void)); +static int rl_get_char PARAMS((int *)); +static int rl_gather_tyi PARAMS((void)); + +/* **************************************************************** */ +/* */ +/* Character Input Buffering */ +/* */ +/* **************************************************************** */ + +static int pop_index, push_index; +static unsigned char ibuffer[512]; +static int ibuffer_len = sizeof (ibuffer) - 1; + +#define any_typein (push_index != pop_index) + +int +_rl_any_typein () +{ + return any_typein; +} + +/* Return the amount of space available in the buffer for stuffing + characters. */ +static int +ibuffer_space () +{ + if (pop_index > push_index) + return (pop_index - push_index - 1); + else + return (ibuffer_len - (push_index - pop_index)); +} + +/* Get a key from the buffer of characters to be read. + Return the key in KEY. + Result is KEY if there was a key, or 0 if there wasn't. */ +static int +rl_get_char (key) + int *key; +{ + if (push_index == pop_index) + return (0); + + *key = ibuffer[pop_index++]; + + if (pop_index >= ibuffer_len) + pop_index = 0; + + return (1); +} + +/* Stuff KEY into the *front* of the input buffer. + Returns non-zero if successful, zero if there is + no space left in the buffer. */ +int +_rl_unget_char (key) + int key; +{ + if (ibuffer_space ()) + { + pop_index--; + if (pop_index < 0) + pop_index = ibuffer_len - 1; + ibuffer[pop_index] = key; + return (1); + } + return (0); +} + +int +_rl_pushed_input_available () +{ + return (push_index != pop_index); +} + +/* If a character is available to be read, then read it and stuff it into + IBUFFER. Otherwise, just return. Returns number of characters read + (0 if none available) and -1 on error (EIO). */ +static int +rl_gather_tyi () +{ + int tty; + register int tem, result; + int chars_avail, k; + char input; +#if defined(HAVE_SELECT) + fd_set readfds, exceptfds; + struct timeval timeout; +#endif + + tty = fileno (rl_instream); + +#if defined (HAVE_SELECT) + FD_ZERO (&readfds); + FD_ZERO (&exceptfds); + FD_SET (tty, &readfds); + FD_SET (tty, &exceptfds); + timeout.tv_sec = 0; + timeout.tv_usec = _keyboard_input_timeout; + result = select (tty + 1, &readfds, (fd_set *)NULL, &exceptfds, &timeout); + if (result <= 0) + return 0; /* Nothing to read. */ +#endif + + result = -1; +#if defined (FIONREAD) + errno = 0; + result = ioctl (tty, FIONREAD, &chars_avail); + if (result == -1 && errno == EIO) + return -1; +#endif + +#if defined (O_NDELAY) + if (result == -1) + { + tem = fcntl (tty, F_GETFL, 0); + + fcntl (tty, F_SETFL, (tem | O_NDELAY)); + chars_avail = read (tty, &input, 1); + + fcntl (tty, F_SETFL, tem); + if (chars_avail == -1 && errno == EAGAIN) + return 0; + if (chars_avail == 0) /* EOF */ + { + rl_stuff_char (EOF); + return (0); + } + } +#endif /* O_NDELAY */ + +#if defined (__MINGW32__) + /* We use getch to read console input, so use the same + mechanism to check for more. Otherwise, we don't know. */ + if (isatty (fileno (rl_instream))) + chars_avail = _kbhit (); + else + chars_avail = 0; + result = 0; +#endif + + /* If there's nothing available, don't waste time trying to read + something. */ + if (chars_avail <= 0) + return 0; + + tem = ibuffer_space (); + + if (chars_avail > tem) + chars_avail = tem; + + /* One cannot read all of the available input. I can only read a single + character at a time, or else programs which require input can be + thwarted. If the buffer is larger than one character, I lose. + Damn! */ + if (tem < ibuffer_len) + chars_avail = 0; + + if (result != -1) + { + while (chars_avail--) + { + k = (*rl_getc_function) (rl_instream); + rl_stuff_char (k); + if (k == NEWLINE || k == RETURN) + break; + } + } + else + { + if (chars_avail) + rl_stuff_char (input); + } + + return 1; +} + +int +rl_set_keyboard_input_timeout (u) + int u; +{ + int o; + + o = _keyboard_input_timeout; + if (u > 0) + _keyboard_input_timeout = u; + return (o); +} + +/* Is there input available to be read on the readline input file + descriptor? Only works if the system has select(2) or FIONREAD. + Uses the value of _keyboard_input_timeout as the timeout; if another + readline function wants to specify a timeout and not leave it up to + the user, it should use _rl_input_queued(timeout_value_in_microseconds) + instead. */ +int +_rl_input_available () +{ +#if defined(HAVE_SELECT) + fd_set readfds, exceptfds; + struct timeval timeout; +#endif +#if !defined (HAVE_SELECT) && defined(FIONREAD) + int chars_avail; +#endif + int tty; + + tty = fileno (rl_instream); + +#if defined (HAVE_SELECT) + FD_ZERO (&readfds); + FD_ZERO (&exceptfds); + FD_SET (tty, &readfds); + FD_SET (tty, &exceptfds); + timeout.tv_sec = 0; + timeout.tv_usec = _keyboard_input_timeout; + return (select (tty + 1, &readfds, (fd_set *)NULL, &exceptfds, &timeout) > 0); +#else + +#if defined (FIONREAD) + if (ioctl (tty, FIONREAD, &chars_avail) == 0) + return (chars_avail); +#endif + +#endif + +#if defined (__MINGW32__) + /* We use getch to read console input, so use the same + mechanism to check for more. Otherwise, we don't know. */ + if (isatty (fileno (rl_instream))) + return _kbhit (); +#endif + + return 0; +} + +int +_rl_input_queued (t) + int t; +{ + int old_timeout, r; + + old_timeout = rl_set_keyboard_input_timeout (t); + r = _rl_input_available (); + rl_set_keyboard_input_timeout (old_timeout); + return r; +} + +void +_rl_insert_typein (c) + int c; +{ + int key, t, i; + char *string; + + i = key = 0; + string = (char *)xmalloc (ibuffer_len + 1); + string[i++] = (char) c; + + while ((t = rl_get_char (&key)) && + _rl_keymap[key].type == ISFUNC && + _rl_keymap[key].function == rl_insert) + string[i++] = key; + + if (t) + _rl_unget_char (key); + + string[i] = '\0'; + rl_insert_text (string); + free (string); +} + +/* Add KEY to the buffer of characters to be read. Returns 1 if the + character was stuffed correctly; 0 otherwise. */ +int +rl_stuff_char (key) + int key; +{ + if (ibuffer_space () == 0) + return 0; + + if (key == EOF) + { + key = NEWLINE; + rl_pending_input = EOF; + RL_SETSTATE (RL_STATE_INPUTPENDING); + } + ibuffer[push_index++] = key; + if (push_index >= ibuffer_len) + push_index = 0; + + return 1; +} + +/* Make C be the next command to be executed. */ +int +rl_execute_next (c) + int c; +{ + rl_pending_input = c; + RL_SETSTATE (RL_STATE_INPUTPENDING); + return 0; +} + +/* Clear any pending input pushed with rl_execute_next() */ +int +rl_clear_pending_input () +{ + rl_pending_input = 0; + RL_UNSETSTATE (RL_STATE_INPUTPENDING); + return 0; +} + +/* **************************************************************** */ +/* */ +/* Character Input */ +/* */ +/* **************************************************************** */ + +/* Read a key, including pending input. */ +int +rl_read_key () +{ + int c; + + rl_key_sequence_length++; + + if (rl_pending_input) + { + c = rl_pending_input; + rl_clear_pending_input (); + } + else + { + /* If input is coming from a macro, then use that. */ + if (c = _rl_next_macro_key ()) + return (c); + + /* If the user has an event function, then call it periodically. */ + if (rl_event_hook) + { + while (rl_event_hook && rl_get_char (&c) == 0) + { + (*rl_event_hook) (); + if (rl_done) /* XXX - experimental */ + return ('\n'); + if (rl_gather_tyi () < 0) /* XXX - EIO */ + { + rl_done = 1; + return ('\n'); + } + } + } + else + { + if (rl_get_char (&c) == 0) + c = (*rl_getc_function) (rl_instream); + } + } + + return (c); +} + +int +rl_getc (stream) + FILE *stream; +{ + int result; + unsigned char c; + + while (1) + { +#if defined (__MINGW32__) + if (isatty (fileno (stream))) + return (getch ()); +#endif + result = read (fileno (stream), &c, sizeof (unsigned char)); + + if (result == sizeof (unsigned char)) + return (c); + + /* If zero characters are returned, then the file that we are + reading from is empty! Return EOF in that case. */ + if (result == 0) + return (EOF); + +#if defined (__BEOS__) + if (errno == EINTR) + continue; +#endif + +#if defined (EWOULDBLOCK) +# define X_EWOULDBLOCK EWOULDBLOCK +#else +# define X_EWOULDBLOCK -99 +#endif + +#if defined (EAGAIN) +# define X_EAGAIN EAGAIN +#else +# define X_EAGAIN -99 +#endif + + if (errno == X_EWOULDBLOCK || errno == X_EAGAIN) + { + if (sh_unset_nodelay_mode (fileno (stream)) < 0) + return (EOF); + continue; + } + +#undef X_EWOULDBLOCK +#undef X_EAGAIN + + /* If the error that we received was SIGINT, then try again, + this is simply an interrupted system call to read (). + Otherwise, some error ocurred, also signifying EOF. */ + if (errno != EINTR) + return (EOF); + } +} + +#if defined (HANDLE_MULTIBYTE) +/* read multibyte char */ +int +_rl_read_mbchar (mbchar, size) + char *mbchar; + int size; +{ + int mb_len = 0; + size_t mbchar_bytes_length; + wchar_t wc; + mbstate_t ps, ps_back; + + memset(&ps, 0, sizeof (mbstate_t)); + memset(&ps_back, 0, sizeof (mbstate_t)); + + while (mb_len < size) + { + RL_SETSTATE(RL_STATE_MOREINPUT); + mbchar[mb_len++] = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + mbchar_bytes_length = mbrtowc (&wc, mbchar, mb_len, &ps); + if (mbchar_bytes_length == (size_t)(-1)) + break; /* invalid byte sequence for the current locale */ + else if (mbchar_bytes_length == (size_t)(-2)) + { + /* shorted bytes */ + ps = ps_back; + continue; + } + else if (mbchar_bytes_length == 0) + { + mbchar[0] = '\0'; /* null wide character */ + mb_len = 1; + break; + } + else if (mbchar_bytes_length > (size_t)(0)) + break; + } + + return mb_len; +} + +/* Read a multibyte-character string whose first character is FIRST into + the buffer MB of length MBLEN. Returns the last character read, which + may be FIRST. Used by the search functions, among others. Very similar + to _rl_read_mbchar. */ +int +_rl_read_mbstring (first, mb, mblen) + int first; + char *mb; + int mblen; +{ + int i, c; + mbstate_t ps; + + c = first; + memset (mb, 0, mblen); + for (i = 0; i < mblen; i++) + { + mb[i] = (char)c; + memset (&ps, 0, sizeof (mbstate_t)); + if (_rl_get_char_len (mb, &ps) == -2) + { + /* Read more for multibyte character */ + RL_SETSTATE (RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE (RL_STATE_MOREINPUT); + } + else + break; + } + return c; +} +#endif /* HANDLE_MULTIBYTE */ diff --git a/external/gpl3/gdb/dist/readline/isearch.c b/external/gpl3/gdb/dist/readline/isearch.c new file mode 100644 index 000000000000..d7d8520ed859 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/isearch.c @@ -0,0 +1,666 @@ +/* **************************************************************** */ +/* */ +/* I-Search and Searching */ +/* */ +/* **************************************************************** */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif + +#include "rldefs.h" +#include "rlmbutil.h" + +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* Variables exported to other files in the readline library. */ +char *_rl_isearch_terminators = (char *)NULL; + +_rl_search_cxt *_rl_iscxt = 0; + +/* Variables imported from other files in the readline library. */ +extern HIST_ENTRY *_rl_saved_line_for_history; + +static int rl_search_history PARAMS((int, int)); + +static _rl_search_cxt *_rl_isearch_init PARAMS((int)); +static void _rl_isearch_fini PARAMS((_rl_search_cxt *)); +static int _rl_isearch_cleanup PARAMS((_rl_search_cxt *, int)); + +/* Last line found by the current incremental search, so we don't `find' + identical lines many times in a row. */ +static char *prev_line_found; + +/* Last search string and its length. */ +static char *last_isearch_string; +static int last_isearch_string_len; + +static char *default_isearch_terminators = "\033\012"; + +_rl_search_cxt * +_rl_scxt_alloc (type, flags) + int type, flags; +{ + _rl_search_cxt *cxt; + + cxt = (_rl_search_cxt *)xmalloc (sizeof (_rl_search_cxt)); + + cxt->type = type; + cxt->sflags = flags; + + cxt->search_string = 0; + cxt->search_string_size = cxt->search_string_index = 0; + + cxt->lines = 0; + cxt->allocated_line = 0; + cxt->hlen = cxt->hindex = 0; + + cxt->save_point = rl_point; + cxt->save_mark = rl_mark; + cxt->save_line = where_history (); + cxt->last_found_line = cxt->save_line; + cxt->prev_line_found = 0; + + cxt->save_undo_list = 0; + + cxt->history_pos = 0; + cxt->direction = 0; + + cxt->lastc = 0; + + cxt->sline = 0; + cxt->sline_len = cxt->sline_index = 0; + + cxt->search_terminators = 0; + + return cxt; +} + +void +_rl_scxt_dispose (cxt, flags) + _rl_search_cxt *cxt; + int flags; +{ + FREE (cxt->search_string); + FREE (cxt->allocated_line); + FREE (cxt->lines); + + free (cxt); +} + +/* Search backwards through the history looking for a string which is typed + interactively. Start with the current line. */ +int +rl_reverse_search_history (sign, key) + int sign, key; +{ + return (rl_search_history (-sign, key)); +} + +/* Search forwards through the history looking for a string which is typed + interactively. Start with the current line. */ +int +rl_forward_search_history (sign, key) + int sign, key; +{ + return (rl_search_history (sign, key)); +} + +/* Display the current state of the search in the echo-area. + SEARCH_STRING contains the string that is being searched for, + DIRECTION is zero for forward, or non-zero for reverse, + WHERE is the history list number of the current line. If it is + -1, then this line is the starting one. */ +static void +rl_display_search (search_string, reverse_p, where) + char *search_string; + int reverse_p, where; +{ + char *message; + int msglen, searchlen; + + searchlen = (search_string && *search_string) ? strlen (search_string) : 0; + + message = (char *)xmalloc (searchlen + 33); + msglen = 0; + +#if defined (NOTDEF) + if (where != -1) + { + sprintf (message, "[%d]", where + history_base); + msglen = strlen (message); + } +#endif /* NOTDEF */ + + message[msglen++] = '('; + + if (reverse_p) + { + strcpy (message + msglen, "reverse-"); + msglen += 8; + } + + strcpy (message + msglen, "i-search)`"); + msglen += 10; + + if (search_string) + { + strcpy (message + msglen, search_string); + msglen += searchlen; + } + + strcpy (message + msglen, "': "); + + rl_message ("%s", message); + free (message); + (*rl_redisplay_function) (); +} + +static _rl_search_cxt * +_rl_isearch_init (direction) + int direction; +{ + _rl_search_cxt *cxt; + register int i; + HIST_ENTRY **hlist; + + cxt = _rl_scxt_alloc (RL_SEARCH_ISEARCH, 0); + if (direction < 0) + cxt->sflags |= SF_REVERSE; + + cxt->search_terminators = _rl_isearch_terminators ? _rl_isearch_terminators + : default_isearch_terminators; + + /* Create an arrary of pointers to the lines that we want to search. */ + hlist = history_list (); + rl_maybe_replace_line (); + i = 0; + if (hlist) + for (i = 0; hlist[i]; i++); + + /* Allocate space for this many lines, +1 for the current input line, + and remember those lines. */ + cxt->lines = (char **)xmalloc ((1 + (cxt->hlen = i)) * sizeof (char *)); + for (i = 0; i < cxt->hlen; i++) + cxt->lines[i] = hlist[i]->line; + + if (_rl_saved_line_for_history) + cxt->lines[i] = _rl_saved_line_for_history->line; + else + { + /* Keep track of this so we can free it. */ + cxt->allocated_line = (char *)xmalloc (1 + strlen (rl_line_buffer)); + strcpy (cxt->allocated_line, &rl_line_buffer[0]); + cxt->lines[i] = cxt->allocated_line; + } + + cxt->hlen++; + + /* The line where we start the search. */ + cxt->history_pos = cxt->save_line; + + rl_save_prompt (); + + /* Initialize search parameters. */ + cxt->search_string = (char *)xmalloc (cxt->search_string_size = 128); + cxt->search_string[cxt->search_string_index = 0] = '\0'; + + /* Normalize DIRECTION into 1 or -1. */ + cxt->direction = (direction >= 0) ? 1 : -1; + + cxt->sline = rl_line_buffer; + cxt->sline_len = strlen (cxt->sline); + cxt->sline_index = rl_point; + + _rl_iscxt = cxt; /* save globally */ + + return cxt; +} + +static void +_rl_isearch_fini (cxt) + _rl_search_cxt *cxt; +{ + /* First put back the original state. */ + strcpy (rl_line_buffer, cxt->lines[cxt->save_line]); + + rl_restore_prompt (); + + /* Save the search string for possible later use. */ + FREE (last_isearch_string); + last_isearch_string = cxt->search_string; + last_isearch_string_len = cxt->search_string_index; + cxt->search_string = 0; + + if (cxt->last_found_line < cxt->save_line) + rl_get_previous_history (cxt->save_line - cxt->last_found_line, 0); + else + rl_get_next_history (cxt->last_found_line - cxt->save_line, 0); + + /* If the string was not found, put point at the end of the last matching + line. If last_found_line == orig_line, we didn't find any matching + history lines at all, so put point back in its original position. */ + if (cxt->sline_index < 0) + { + if (cxt->last_found_line == cxt->save_line) + cxt->sline_index = cxt->save_point; + else + cxt->sline_index = strlen (rl_line_buffer); + rl_mark = cxt->save_mark; + } + + rl_point = cxt->sline_index; + /* Don't worry about where to put the mark here; rl_get_previous_history + and rl_get_next_history take care of it. */ + + rl_clear_message (); +} + +int +_rl_search_getchar (cxt) + _rl_search_cxt *cxt; +{ + int c; + + /* Read a key and decide how to proceed. */ + RL_SETSTATE(RL_STATE_MOREINPUT); + c = cxt->lastc = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + c = cxt->lastc = _rl_read_mbstring (cxt->lastc, cxt->mb, MB_LEN_MAX); +#endif + + return c; +} + +/* Process just-read character C according to isearch context CXT. Return + -1 if the caller should just free the context and return, 0 if we should + break out of the loop, and 1 if we should continue to read characters. */ +int +_rl_isearch_dispatch (cxt, c) + _rl_search_cxt *cxt; + int c; +{ + int n, wstart, wlen, limit, cval; + rl_command_func_t *f; + + f = (rl_command_func_t *)NULL; + + /* Translate the keys we do something with to opcodes. */ + if (c >= 0 && _rl_keymap[c].type == ISFUNC) + { + f = _rl_keymap[c].function; + + if (f == rl_reverse_search_history) + cxt->lastc = (cxt->sflags & SF_REVERSE) ? -1 : -2; + else if (f == rl_forward_search_history) + cxt->lastc = (cxt->sflags & SF_REVERSE) ? -2 : -1; + else if (f == rl_rubout) + cxt->lastc = -3; + else if (c == CTRL ('G')) + cxt->lastc = -4; + else if (c == CTRL ('W')) /* XXX */ + cxt->lastc = -5; + else if (c == CTRL ('Y')) /* XXX */ + cxt->lastc = -6; + } + + /* The characters in isearch_terminators (set from the user-settable + variable isearch-terminators) are used to terminate the search but + not subsequently execute the character as a command. The default + value is "\033\012" (ESC and C-J). */ + if (strchr (cxt->search_terminators, cxt->lastc)) + { + /* ESC still terminates the search, but if there is pending + input or if input arrives within 0.1 seconds (on systems + with select(2)) it is used as a prefix character + with rl_execute_next. WATCH OUT FOR THIS! This is intended + to allow the arrow keys to be used like ^F and ^B are used + to terminate the search and execute the movement command. + XXX - since _rl_input_available depends on the application- + settable keyboard timeout value, this could alternatively + use _rl_input_queued(100000) */ + if (cxt->lastc == ESC && _rl_input_available ()) + rl_execute_next (ESC); + return (0); + } + +#define ENDSRCH_CHAR(c) \ + ((CTRL_CHAR (c) || META_CHAR (c) || (c) == RUBOUT) && ((c) != CTRL ('G'))) + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + if (cxt->lastc >= 0 && (cxt->mb[0] && cxt->mb[1] == '\0') && ENDSRCH_CHAR (cxt->lastc)) + { + /* This sets rl_pending_input to c; it will be picked up the next + time rl_read_key is called. */ + rl_execute_next (cxt->lastc); + return (0); + } + } + else +#endif + if (cxt->lastc >= 0 && ENDSRCH_CHAR (cxt->lastc)) + { + /* This sets rl_pending_input to LASTC; it will be picked up the next + time rl_read_key is called. */ + rl_execute_next (cxt->lastc); + return (0); + } + + /* Now dispatch on the character. `Opcodes' affect the search string or + state. Other characters are added to the string. */ + switch (cxt->lastc) + { + /* search again */ + case -1: + if (cxt->search_string_index == 0) + { + if (last_isearch_string) + { + cxt->search_string_size = 64 + last_isearch_string_len; + cxt->search_string = (char *)xrealloc (cxt->search_string, cxt->search_string_size); + strcpy (cxt->search_string, last_isearch_string); + cxt->search_string_index = last_isearch_string_len; + rl_display_search (cxt->search_string, (cxt->sflags & SF_REVERSE), -1); + break; + } + return (1); + } + else if (cxt->sflags & SF_REVERSE) + cxt->sline_index--; + else if (cxt->sline_index != cxt->sline_len) + cxt->sline_index++; + else + rl_ding (); + break; + + /* switch directions */ + case -2: + cxt->direction = -cxt->direction; + if (cxt->direction < 0) + cxt->sflags |= SF_REVERSE; + else + cxt->sflags &= ~SF_REVERSE; + break; + + /* delete character from search string. */ + case -3: /* C-H, DEL */ + /* This is tricky. To do this right, we need to keep a + stack of search positions for the current search, with + sentinels marking the beginning and end. But this will + do until we have a real isearch-undo. */ + if (cxt->search_string_index == 0) + rl_ding (); + else + cxt->search_string[--cxt->search_string_index] = '\0'; + break; + + case -4: /* C-G, abort */ + rl_replace_line (cxt->lines[cxt->save_line], 0); + rl_point = cxt->save_point; + rl_mark = cxt->save_mark; + rl_restore_prompt(); + rl_clear_message (); + + return -1; + + case -5: /* C-W */ + /* skip over portion of line we already matched and yank word */ + wstart = rl_point + cxt->search_string_index; + if (wstart >= rl_end) + { + rl_ding (); + break; + } + + /* if not in a word, move to one. */ + cval = _rl_char_value (rl_line_buffer, wstart); + if (_rl_walphabetic (cval) == 0) + { + rl_ding (); + break; + } + n = MB_NEXTCHAR (rl_line_buffer, wstart, 1, MB_FIND_NONZERO);; + while (n < rl_end) + { + cval = _rl_char_value (rl_line_buffer, n); + if (_rl_walphabetic (cval) == 0) + break; + n = MB_NEXTCHAR (rl_line_buffer, n, 1, MB_FIND_NONZERO);; + } + wlen = n - wstart + 1; + if (cxt->search_string_index + wlen + 1 >= cxt->search_string_size) + { + cxt->search_string_size += wlen + 1; + cxt->search_string = (char *)xrealloc (cxt->search_string, cxt->search_string_size); + } + for (; wstart < n; wstart++) + cxt->search_string[cxt->search_string_index++] = rl_line_buffer[wstart]; + cxt->search_string[cxt->search_string_index] = '\0'; + break; + + case -6: /* C-Y */ + /* skip over portion of line we already matched and yank rest */ + wstart = rl_point + cxt->search_string_index; + if (wstart >= rl_end) + { + rl_ding (); + break; + } + n = rl_end - wstart + 1; + if (cxt->search_string_index + n + 1 >= cxt->search_string_size) + { + cxt->search_string_size += n + 1; + cxt->search_string = (char *)xrealloc (cxt->search_string, cxt->search_string_size); + } + for (n = wstart; n < rl_end; n++) + cxt->search_string[cxt->search_string_index++] = rl_line_buffer[n]; + cxt->search_string[cxt->search_string_index] = '\0'; + break; + + /* Add character to search string and continue search. */ + default: + if (cxt->search_string_index + 2 >= cxt->search_string_size) + { + cxt->search_string_size += 128; + cxt->search_string = (char *)xrealloc (cxt->search_string, cxt->search_string_size); + } +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + int j, l; + for (j = 0, l = strlen (cxt->mb); j < l; ) + cxt->search_string[cxt->search_string_index++] = cxt->mb[j++]; + } + else +#endif + cxt->search_string[cxt->search_string_index++] = c; + cxt->search_string[cxt->search_string_index] = '\0'; + break; + } + + for (cxt->sflags &= ~(SF_FOUND|SF_FAILED);; ) + { + limit = cxt->sline_len - cxt->search_string_index + 1; + + /* Search the current line. */ + while ((cxt->sflags & SF_REVERSE) ? (cxt->sline_index >= 0) : (cxt->sline_index < limit)) + { + if (STREQN (cxt->search_string, cxt->sline + cxt->sline_index, cxt->search_string_index)) + { + cxt->sflags |= SF_FOUND; + break; + } + else + cxt->sline_index += cxt->direction; + } + if (cxt->sflags & SF_FOUND) + break; + + /* Move to the next line, but skip new copies of the line + we just found and lines shorter than the string we're + searching for. */ + do + { + /* Move to the next line. */ + cxt->history_pos += cxt->direction; + + /* At limit for direction? */ + if ((cxt->sflags & SF_REVERSE) ? (cxt->history_pos < 0) : (cxt->history_pos == cxt->hlen)) + { + cxt->sflags |= SF_FAILED; + break; + } + + /* We will need these later. */ + cxt->sline = cxt->lines[cxt->history_pos]; + cxt->sline_len = strlen (cxt->sline); + } + while ((cxt->prev_line_found && STREQ (cxt->prev_line_found, cxt->lines[cxt->history_pos])) || + (cxt->search_string_index > cxt->sline_len)); + + if (cxt->sflags & SF_FAILED) + break; + + /* Now set up the line for searching... */ + cxt->sline_index = (cxt->sflags & SF_REVERSE) ? cxt->sline_len - cxt->search_string_index : 0; + } + + if (cxt->sflags & SF_FAILED) + { + /* We cannot find the search string. Ding the bell. */ + rl_ding (); + cxt->history_pos = cxt->last_found_line; + return 1; + } + + /* We have found the search string. Just display it. But don't + actually move there in the history list until the user accepts + the location. */ + if (cxt->sflags & SF_FOUND) + { + cxt->prev_line_found = cxt->lines[cxt->history_pos]; + rl_replace_line (cxt->lines[cxt->history_pos], 0); + rl_point = cxt->sline_index; + cxt->last_found_line = cxt->history_pos; + rl_display_search (cxt->search_string, (cxt->sflags & SF_REVERSE), (cxt->history_pos == cxt->save_line) ? -1 : cxt->history_pos); + } + + return 1; +} + +static int +_rl_isearch_cleanup (cxt, r) + _rl_search_cxt *cxt; + int r; +{ + if (r >= 0) + _rl_isearch_fini (cxt); + _rl_scxt_dispose (cxt, 0); + _rl_iscxt = 0; + + RL_UNSETSTATE(RL_STATE_ISEARCH); + + return (r != 0); +} + +/* Search through the history looking for an interactively typed string. + This is analogous to i-search. We start the search in the current line. + DIRECTION is which direction to search; >= 0 means forward, < 0 means + backwards. */ +static int +rl_search_history (direction, invoking_key) + int direction, invoking_key; +{ + _rl_search_cxt *cxt; /* local for now, but saved globally */ + int c, r; + + RL_SETSTATE(RL_STATE_ISEARCH); + cxt = _rl_isearch_init (direction); + + rl_display_search (cxt->search_string, (cxt->sflags & SF_REVERSE), -1); + + /* If we are using the callback interface, all we do is set up here and + return. The key is that we leave RL_STATE_ISEARCH set. */ + if (RL_ISSTATE (RL_STATE_CALLBACK)) + return (0); + + r = -1; + for (;;) + { + c = _rl_search_getchar (cxt); + /* We might want to handle EOF here (c == 0) */ + r = _rl_isearch_dispatch (cxt, cxt->lastc); + if (r <= 0) + break; + } + + /* The searching is over. The user may have found the string that she + was looking for, or else she may have exited a failing search. If + LINE_INDEX is -1, then that shows that the string searched for was + not found. We use this to determine where to place rl_point. */ + return (_rl_isearch_cleanup (cxt, r)); +} + +#if defined (READLINE_CALLBACKS) +/* Called from the callback functions when we are ready to read a key. The + callback functions know to call this because RL_ISSTATE(RL_STATE_ISEARCH). + If _rl_isearch_dispatch finishes searching, this function is responsible + for turning off RL_STATE_ISEARCH, which it does using _rl_isearch_cleanup. */ +int +_rl_isearch_callback (cxt) + _rl_search_cxt *cxt; +{ + int c, r; + + c = _rl_search_getchar (cxt); + /* We might want to handle EOF here */ + r = _rl_isearch_dispatch (cxt, cxt->lastc); + + return (r <= 0) ? _rl_isearch_cleanup (cxt, r) : 0; +} +#endif diff --git a/external/gpl3/gdb/dist/readline/keymaps.c b/external/gpl3/gdb/dist/readline/keymaps.c new file mode 100644 index 000000000000..70d0cc08d3f1 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/keymaps.c @@ -0,0 +1,149 @@ +/* keymaps.c -- Functions and keymaps for the GNU Readline library. */ + +/* Copyright (C) 1988,1989 Free Software Foundation, Inc. + + This file is part of GNU Readline, a library for reading lines + of text with interactive input and history editing. + + Readline is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + Readline is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Readline; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include /* for FILE * definition for readline.h */ + +#include "readline.h" +#include "rlconf.h" + +#include "emacs_keymap.c" + +#if defined (VI_MODE) +#include "vi_keymap.c" +#endif + +#include "xmalloc.h" + +/* **************************************************************** */ +/* */ +/* Functions for manipulating Keymaps. */ +/* */ +/* **************************************************************** */ + + +/* Return a new, empty keymap. + Free it with free() when you are done. */ +Keymap +rl_make_bare_keymap () +{ + register int i; + Keymap keymap = (Keymap)xmalloc (KEYMAP_SIZE * sizeof (KEYMAP_ENTRY)); + + for (i = 0; i < KEYMAP_SIZE; i++) + { + keymap[i].type = ISFUNC; + keymap[i].function = (rl_command_func_t *)NULL; + } + +#if 0 + for (i = 'A'; i < ('Z' + 1); i++) + { + keymap[i].type = ISFUNC; + keymap[i].function = rl_do_lowercase_version; + } +#endif + + return (keymap); +} + +/* Return a new keymap which is a copy of MAP. */ +Keymap +rl_copy_keymap (map) + Keymap map; +{ + register int i; + Keymap temp; + + temp = rl_make_bare_keymap (); + for (i = 0; i < KEYMAP_SIZE; i++) + { + temp[i].type = map[i].type; + temp[i].function = map[i].function; + } + return (temp); +} + +/* Return a new keymap with the printing characters bound to rl_insert, + the uppercase Meta characters bound to run their lowercase equivalents, + and the Meta digits bound to produce numeric arguments. */ +Keymap +rl_make_keymap () +{ + register int i; + Keymap newmap; + + newmap = rl_make_bare_keymap (); + + /* All ASCII printing characters are self-inserting. */ + for (i = ' '; i < 127; i++) + newmap[i].function = rl_insert; + + newmap[TAB].function = rl_insert; + newmap[RUBOUT].function = rl_rubout; /* RUBOUT == 127 */ + newmap[CTRL('H')].function = rl_rubout; + +#if KEYMAP_SIZE > 128 + /* Printing characters in ISO Latin-1 and some 8-bit character sets. */ + for (i = 128; i < 256; i++) + newmap[i].function = rl_insert; +#endif /* KEYMAP_SIZE > 128 */ + + return (newmap); +} + +/* Free the storage associated with MAP. */ +void +rl_discard_keymap (map) + Keymap map; +{ + int i; + + if (!map) + return; + + for (i = 0; i < KEYMAP_SIZE; i++) + { + switch (map[i].type) + { + case ISFUNC: + break; + + case ISKMAP: + rl_discard_keymap ((Keymap)map[i].function); + break; + + case ISMACR: + free ((char *)map[i].function); + break; + } + } +} diff --git a/external/gpl3/gdb/dist/readline/keymaps.h b/external/gpl3/gdb/dist/readline/keymaps.h new file mode 100644 index 000000000000..66fa2a5ec14a --- /dev/null +++ b/external/gpl3/gdb/dist/readline/keymaps.h @@ -0,0 +1,103 @@ +/* keymaps.h -- Manipulation of readline keymaps. */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _KEYMAPS_H_ +#define _KEYMAPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (READLINE_LIBRARY) +# include "rlstdc.h" +# include "chardefs.h" +# include "rltypedefs.h" +#else +# include +# include +# include +#endif + +/* A keymap contains one entry for each key in the ASCII set. + Each entry consists of a type and a pointer. + FUNCTION is the address of a function to run, or the + address of a keymap to indirect through. + TYPE says which kind of thing FUNCTION is. */ +typedef struct _keymap_entry { + char type; + rl_command_func_t *function; +} KEYMAP_ENTRY; + +/* This must be large enough to hold bindings for all of the characters + in a desired character set (e.g, 128 for ASCII, 256 for ISO Latin-x, + and so on) plus one for subsequence matching. */ +#define KEYMAP_SIZE 257 +#define ANYOTHERKEY KEYMAP_SIZE-1 + +/* I wanted to make the above structure contain a union of: + union { rl_command_func_t *function; struct _keymap_entry *keymap; } value; + but this made it impossible for me to create a static array. + Maybe I need C lessons. */ + +typedef KEYMAP_ENTRY KEYMAP_ENTRY_ARRAY[KEYMAP_SIZE]; +typedef KEYMAP_ENTRY *Keymap; + +/* The values that TYPE can have in a keymap entry. */ +#define ISFUNC 0 +#define ISKMAP 1 +#define ISMACR 2 + +extern KEYMAP_ENTRY_ARRAY emacs_standard_keymap, emacs_meta_keymap, emacs_ctlx_keymap; +extern KEYMAP_ENTRY_ARRAY vi_insertion_keymap, vi_movement_keymap; + +/* Return a new, empty keymap. + Free it with free() when you are done. */ +extern Keymap rl_make_bare_keymap PARAMS((void)); + +/* Return a new keymap which is a copy of MAP. */ +extern Keymap rl_copy_keymap PARAMS((Keymap)); + +/* Return a new keymap with the printing characters bound to rl_insert, + the lowercase Meta characters bound to run their equivalents, and + the Meta digits bound to produce numeric arguments. */ +extern Keymap rl_make_keymap PARAMS((void)); + +/* Free the storage associated with a keymap. */ +extern void rl_discard_keymap PARAMS((Keymap)); + +/* These functions actually appear in bind.c */ + +/* Return the keymap corresponding to a given name. Names look like + `emacs' or `emacs-meta' or `vi-insert'. */ +extern Keymap rl_get_keymap_by_name PARAMS((const char *)); + +/* Return the current keymap. */ +extern Keymap rl_get_keymap PARAMS((void)); + +/* Set the current keymap to MAP. */ +extern void rl_set_keymap PARAMS((Keymap)); + +#ifdef __cplusplus +} +#endif + +#endif /* _KEYMAPS_H_ */ diff --git a/external/gpl3/gdb/dist/readline/kill.c b/external/gpl3/gdb/dist/readline/kill.c new file mode 100644 index 000000000000..1d3254c3275d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/kill.c @@ -0,0 +1,693 @@ +/* kill.c -- kill ring management. */ + +/* Copyright (C) 1994 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* **************************************************************** */ +/* */ +/* Killing Mechanism */ +/* */ +/* **************************************************************** */ + +/* What we assume for a max number of kills. */ +#define DEFAULT_MAX_KILLS 10 + +/* The real variable to look at to find out when to flush kills. */ +static int rl_max_kills = DEFAULT_MAX_KILLS; + +/* Where to store killed text. */ +static char **rl_kill_ring = (char **)NULL; + +/* Where we are in the kill ring. */ +static int rl_kill_index; + +/* How many slots we have in the kill ring. */ +static int rl_kill_ring_length; + +static int _rl_copy_to_kill_ring PARAMS((char *, int)); +static int region_kill_internal PARAMS((int)); +static int _rl_copy_word_as_kill PARAMS((int, int)); +static int rl_yank_nth_arg_internal PARAMS((int, int, int)); + +/* How to say that you only want to save a certain amount + of kill material. */ +int +rl_set_retained_kills (num) + int num; +{ + return 0; +} + +/* Add TEXT to the kill ring, allocating a new kill ring slot as necessary. + This uses TEXT directly, so the caller must not free it. If APPEND is + non-zero, and the last command was a kill, the text is appended to the + current kill ring slot, otherwise prepended. */ +static int +_rl_copy_to_kill_ring (text, append) + char *text; + int append; +{ + char *old, *new; + int slot; + + /* First, find the slot to work with. */ + if (_rl_last_command_was_kill == 0) + { + /* Get a new slot. */ + if (rl_kill_ring == 0) + { + /* If we don't have any defined, then make one. */ + rl_kill_ring = (char **) + xmalloc (((rl_kill_ring_length = 1) + 1) * sizeof (char *)); + rl_kill_ring[slot = 0] = (char *)NULL; + } + else + { + /* We have to add a new slot on the end, unless we have + exceeded the max limit for remembering kills. */ + slot = rl_kill_ring_length; + if (slot == rl_max_kills) + { + register int i; + free (rl_kill_ring[0]); + for (i = 0; i < slot; i++) + rl_kill_ring[i] = rl_kill_ring[i + 1]; + } + else + { + slot = rl_kill_ring_length += 1; + rl_kill_ring = (char **)xrealloc (rl_kill_ring, slot * sizeof (char *)); + } + rl_kill_ring[--slot] = (char *)NULL; + } + } + else + slot = rl_kill_ring_length - 1; + + /* If the last command was a kill, prepend or append. */ + if (_rl_last_command_was_kill && rl_editing_mode != vi_mode) + { + old = rl_kill_ring[slot]; + new = (char *)xmalloc (1 + strlen (old) + strlen (text)); + + if (append) + { + strcpy (new, old); + strcat (new, text); + } + else + { + strcpy (new, text); + strcat (new, old); + } + free (old); + free (text); + rl_kill_ring[slot] = new; + } + else + rl_kill_ring[slot] = text; + + rl_kill_index = slot; + return 0; +} + +/* The way to kill something. This appends or prepends to the last + kill, if the last command was a kill command. if FROM is less + than TO, then the text is appended, otherwise prepended. If the + last command was not a kill command, then a new slot is made for + this kill. */ +int +rl_kill_text (from, to) + int from, to; +{ + char *text; + + /* Is there anything to kill? */ + if (from == to) + { + _rl_last_command_was_kill++; + return 0; + } + + text = rl_copy_text (from, to); + + /* Delete the copied text from the line. */ + rl_delete_text (from, to); + + _rl_copy_to_kill_ring (text, from < to); + + _rl_last_command_was_kill++; + return 0; +} + +/* Now REMEMBER! In order to do prepending or appending correctly, kill + commands always make rl_point's original position be the FROM argument, + and rl_point's extent be the TO argument. */ + +/* **************************************************************** */ +/* */ +/* Killing Commands */ +/* */ +/* **************************************************************** */ + +/* Delete the word at point, saving the text in the kill ring. */ +int +rl_kill_word (count, key) + int count, key; +{ + int orig_point; + + if (count < 0) + return (rl_backward_kill_word (-count, key)); + else + { + orig_point = rl_point; + rl_forward_word (count, key); + + if (rl_point != orig_point) + rl_kill_text (orig_point, rl_point); + + rl_point = orig_point; + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + return 0; +} + +/* Rubout the word before point, placing it on the kill ring. */ +int +rl_backward_kill_word (count, ignore) + int count, ignore; +{ + int orig_point; + + if (count < 0) + return (rl_kill_word (-count, ignore)); + else + { + orig_point = rl_point; + rl_backward_word (count, ignore); + + if (rl_point != orig_point) + rl_kill_text (orig_point, rl_point); + + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + return 0; +} + +/* Kill from here to the end of the line. If DIRECTION is negative, kill + back to the line start instead. */ +int +rl_kill_line (direction, ignore) + int direction, ignore; +{ + int orig_point; + + if (direction < 0) + return (rl_backward_kill_line (1, ignore)); + else + { + orig_point = rl_point; + rl_end_of_line (1, ignore); + if (orig_point != rl_point) + rl_kill_text (orig_point, rl_point); + rl_point = orig_point; + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + return 0; +} + +/* Kill backwards to the start of the line. If DIRECTION is negative, kill + forwards to the line end instead. */ +int +rl_backward_kill_line (direction, ignore) + int direction, ignore; +{ + int orig_point; + + if (direction < 0) + return (rl_kill_line (1, ignore)); + else + { + if (!rl_point) + rl_ding (); + else + { + orig_point = rl_point; + rl_beg_of_line (1, ignore); + if (rl_point != orig_point) + rl_kill_text (orig_point, rl_point); + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + } + return 0; +} + +/* Kill the whole line, no matter where point is. */ +int +rl_kill_full_line (count, ignore) + int count, ignore; +{ + rl_begin_undo_group (); + rl_point = 0; + rl_kill_text (rl_point, rl_end); + rl_mark = 0; + rl_end_undo_group (); + return 0; +} + +/* The next two functions mimic unix line editing behaviour, except they + save the deleted text on the kill ring. This is safer than not saving + it, and since we have a ring, nobody should get screwed. */ + +/* This does what C-w does in Unix. We can't prevent people from + using behaviour that they expect. */ +int +rl_unix_word_rubout (count, key) + int count, key; +{ + int orig_point; + + if (rl_point == 0) + rl_ding (); + else + { + orig_point = rl_point; + if (count <= 0) + count = 1; + + while (count--) + { + while (rl_point && whitespace (rl_line_buffer[rl_point - 1])) + rl_point--; + + while (rl_point && (whitespace (rl_line_buffer[rl_point - 1]) == 0)) + rl_point--; + } + + rl_kill_text (orig_point, rl_point); + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + + return 0; +} + +/* This deletes one filename component in a Unix pathname. That is, it + deletes backward to directory separator (`/') or whitespace. */ +int +rl_unix_filename_rubout (count, key) + int count, key; +{ + int orig_point, c; + + if (rl_point == 0) + rl_ding (); + else + { + orig_point = rl_point; + if (count <= 0) + count = 1; + + while (count--) + { + c = rl_line_buffer[rl_point - 1]; + while (rl_point && (whitespace (c) || c == '/')) + { + rl_point--; + c = rl_line_buffer[rl_point - 1]; + } + + while (rl_point && (whitespace (c) == 0) && c != '/') + { + rl_point--; + c = rl_line_buffer[rl_point - 1]; + } + } + + rl_kill_text (orig_point, rl_point); + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + + return 0; +} + +/* Here is C-u doing what Unix does. You don't *have* to use these + key-bindings. We have a choice of killing the entire line, or + killing from where we are to the start of the line. We choose the + latter, because if you are a Unix weenie, then you haven't backspaced + into the line at all, and if you aren't, then you know what you are + doing. */ +int +rl_unix_line_discard (count, key) + int count, key; +{ + if (rl_point == 0) + rl_ding (); + else + { + rl_kill_text (rl_point, 0); + rl_point = 0; + if (rl_editing_mode == emacs_mode) + rl_mark = rl_point; + } + return 0; +} + +/* Copy the text in the `region' to the kill ring. If DELETE is non-zero, + delete the text from the line as well. */ +static int +region_kill_internal (delete) + int delete; +{ + char *text; + + if (rl_mark != rl_point) + { + text = rl_copy_text (rl_point, rl_mark); + if (delete) + rl_delete_text (rl_point, rl_mark); + _rl_copy_to_kill_ring (text, rl_point < rl_mark); + } + + _rl_last_command_was_kill++; + return 0; +} + +/* Copy the text in the region to the kill ring. */ +int +rl_copy_region_to_kill (count, ignore) + int count, ignore; +{ + return (region_kill_internal (0)); +} + +/* Kill the text between the point and mark. */ +int +rl_kill_region (count, ignore) + int count, ignore; +{ + int r, npoint; + + npoint = (rl_point < rl_mark) ? rl_point : rl_mark; + r = region_kill_internal (1); + _rl_fix_point (1); + rl_point = npoint; + return r; +} + +/* Copy COUNT words to the kill ring. DIR says which direction we look + to find the words. */ +static int +_rl_copy_word_as_kill (count, dir) + int count, dir; +{ + int om, op, r; + + om = rl_mark; + op = rl_point; + + if (dir > 0) + rl_forward_word (count, 0); + else + rl_backward_word (count, 0); + + rl_mark = rl_point; + + if (dir > 0) + rl_backward_word (count, 0); + else + rl_forward_word (count, 0); + + r = region_kill_internal (0); + + rl_mark = om; + rl_point = op; + + return r; +} + +int +rl_copy_forward_word (count, key) + int count, key; +{ + if (count < 0) + return (rl_copy_backward_word (-count, key)); + + return (_rl_copy_word_as_kill (count, 1)); +} + +int +rl_copy_backward_word (count, key) + int count, key; +{ + if (count < 0) + return (rl_copy_forward_word (-count, key)); + + return (_rl_copy_word_as_kill (count, -1)); +} + +/* Yank back the last killed text. This ignores arguments. */ +int +rl_yank (count, ignore) + int count, ignore; +{ + if (rl_kill_ring == 0) + { + _rl_abort_internal (); + return -1; + } + + _rl_set_mark_at_pos (rl_point); + rl_insert_text (rl_kill_ring[rl_kill_index]); + return 0; +} + +/* If the last command was yank, or yank_pop, and the text just + before point is identical to the current kill item, then + delete that text from the line, rotate the index down, and + yank back some other text. */ +int +rl_yank_pop (count, key) + int count, key; +{ + int l, n; + + if (((rl_last_func != rl_yank_pop) && (rl_last_func != rl_yank)) || + !rl_kill_ring) + { + _rl_abort_internal (); + return -1; + } + + l = strlen (rl_kill_ring[rl_kill_index]); + n = rl_point - l; + if (n >= 0 && STREQN (rl_line_buffer + n, rl_kill_ring[rl_kill_index], l)) + { + rl_delete_text (n, rl_point); + rl_point = n; + rl_kill_index--; + if (rl_kill_index < 0) + rl_kill_index = rl_kill_ring_length - 1; + rl_yank (1, 0); + return 0; + } + else + { + _rl_abort_internal (); + return -1; + } +} + +/* Yank the COUNTh argument from the previous history line, skipping + HISTORY_SKIP lines before looking for the `previous line'. */ +static int +rl_yank_nth_arg_internal (count, ignore, history_skip) + int count, ignore, history_skip; +{ + register HIST_ENTRY *entry; + char *arg; + int i, pos; + + pos = where_history (); + + if (history_skip) + { + for (i = 0; i < history_skip; i++) + entry = previous_history (); + } + + entry = previous_history (); + + history_set_pos (pos); + + if (entry == 0) + { + rl_ding (); + return -1; + } + + arg = history_arg_extract (count, count, entry->line); + if (!arg || !*arg) + { + rl_ding (); + return -1; + } + + rl_begin_undo_group (); + + _rl_set_mark_at_pos (rl_point); + +#if defined (VI_MODE) + /* Vi mode always inserts a space before yanking the argument, and it + inserts it right *after* rl_point. */ + if (rl_editing_mode == vi_mode) + { + rl_vi_append_mode (1, ignore); + rl_insert_text (" "); + } +#endif /* VI_MODE */ + + rl_insert_text (arg); + free (arg); + + rl_end_undo_group (); + return 0; +} + +/* Yank the COUNTth argument from the previous history line. */ +int +rl_yank_nth_arg (count, ignore) + int count, ignore; +{ + return (rl_yank_nth_arg_internal (count, ignore, 0)); +} + +/* Yank the last argument from the previous history line. This `knows' + how rl_yank_nth_arg treats a count of `$'. With an argument, this + behaves the same as rl_yank_nth_arg. */ +int +rl_yank_last_arg (count, key) + int count, key; +{ + static int history_skip = 0; + static int explicit_arg_p = 0; + static int count_passed = 1; + static int direction = 1; + static int undo_needed = 0; + int retval; + + if (rl_last_func != rl_yank_last_arg) + { + history_skip = 0; + explicit_arg_p = rl_explicit_arg; + count_passed = count; + direction = 1; + } + else + { + if (undo_needed) + rl_do_undo (); + if (count < 1) + direction = -direction; + history_skip += direction; + if (history_skip < 0) + history_skip = 0; + } + + if (explicit_arg_p) + retval = rl_yank_nth_arg_internal (count_passed, key, history_skip); + else + retval = rl_yank_nth_arg_internal ('$', key, history_skip); + + undo_needed = retval == 0; + return retval; +} + +/* A special paste command for users of Cygnus's cygwin32. */ +#if defined (__CYGWIN__) +#include + +int +rl_paste_from_clipboard (count, key) + int count, key; +{ + char *data, *ptr; + int len; + + if (OpenClipboard (NULL) == 0) + return (0); + + data = (char *)GetClipboardData (CF_TEXT); + if (data) + { + ptr = strchr (data, '\r'); + if (ptr) + { + len = ptr - data; + ptr = (char *)xmalloc (len + 1); + ptr[len] = '\0'; + strncpy (ptr, data, len); + } + else + ptr = data; + _rl_set_mark_at_pos (rl_point); + rl_insert_text (ptr); + if (ptr != data) + free (ptr); + CloseClipboard (); + } + return (0); +} +#endif /* __CYGWIN__ */ diff --git a/external/gpl3/gdb/dist/readline/macro.c b/external/gpl3/gdb/dist/readline/macro.c new file mode 100644 index 000000000000..2975bf1f74fa --- /dev/null +++ b/external/gpl3/gdb/dist/readline/macro.c @@ -0,0 +1,271 @@ +/* macro.c -- keyboard macros for readline. */ + +/* Copyright (C) 1994 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* **************************************************************** */ +/* */ +/* Hacking Keyboard Macros */ +/* */ +/* **************************************************************** */ + +/* The currently executing macro string. If this is non-zero, + then it is a malloc ()'ed string where input is coming from. */ +char *rl_executing_macro = (char *)NULL; + +/* The offset in the above string to the next character to be read. */ +static int executing_macro_index; + +/* The current macro string being built. Characters get stuffed + in here by add_macro_char (). */ +static char *current_macro = (char *)NULL; + +/* The size of the buffer allocated to current_macro. */ +static int current_macro_size; + +/* The index at which characters are being added to current_macro. */ +static int current_macro_index; + +/* A structure used to save nested macro strings. + It is a linked list of string/index for each saved macro. */ +struct saved_macro { + struct saved_macro *next; + char *string; + int sindex; +}; + +/* The list of saved macros. */ +static struct saved_macro *macro_list = (struct saved_macro *)NULL; + +/* Set up to read subsequent input from STRING. + STRING is free ()'ed when we are done with it. */ +void +_rl_with_macro_input (string) + char *string; +{ + _rl_push_executing_macro (); + rl_executing_macro = string; + executing_macro_index = 0; + RL_SETSTATE(RL_STATE_MACROINPUT); +} + +/* Return the next character available from a macro, or 0 if + there are no macro characters. */ +int +_rl_next_macro_key () +{ + int c; + + if (rl_executing_macro == 0) + return (0); + + if (rl_executing_macro[executing_macro_index] == 0) + { + _rl_pop_executing_macro (); + return (_rl_next_macro_key ()); + } + +#if defined (READLINE_CALLBACKS) + c = rl_executing_macro[executing_macro_index++]; + if (RL_ISSTATE (RL_STATE_CALLBACK) && RL_ISSTATE (RL_STATE_READCMD) && rl_executing_macro[executing_macro_index] == 0) + _rl_pop_executing_macro (); + return c; +#else + return (rl_executing_macro[executing_macro_index++]); +#endif +} + +/* Save the currently executing macro on a stack of saved macros. */ +void +_rl_push_executing_macro () +{ + struct saved_macro *saver; + + saver = (struct saved_macro *)xmalloc (sizeof (struct saved_macro)); + saver->next = macro_list; + saver->sindex = executing_macro_index; + saver->string = rl_executing_macro; + + macro_list = saver; +} + +/* Discard the current macro, replacing it with the one + on the top of the stack of saved macros. */ +void +_rl_pop_executing_macro () +{ + struct saved_macro *macro; + + FREE (rl_executing_macro); + rl_executing_macro = (char *)NULL; + executing_macro_index = 0; + + if (macro_list) + { + macro = macro_list; + rl_executing_macro = macro_list->string; + executing_macro_index = macro_list->sindex; + macro_list = macro_list->next; + free (macro); + } + + if (rl_executing_macro == 0) + RL_UNSETSTATE(RL_STATE_MACROINPUT); +} + +/* Add a character to the macro being built. */ +void +_rl_add_macro_char (c) + int c; +{ + if (current_macro_index + 1 >= current_macro_size) + { + if (current_macro == 0) + current_macro = (char *)xmalloc (current_macro_size = 25); + else + current_macro = (char *)xrealloc (current_macro, current_macro_size += 25); + } + + current_macro[current_macro_index++] = c; + current_macro[current_macro_index] = '\0'; +} + +void +_rl_kill_kbd_macro () +{ + if (current_macro) + { + free (current_macro); + current_macro = (char *) NULL; + } + current_macro_size = current_macro_index = 0; + + FREE (rl_executing_macro); + rl_executing_macro = (char *) NULL; + executing_macro_index = 0; + + RL_UNSETSTATE(RL_STATE_MACRODEF); +} + +/* Begin defining a keyboard macro. + Keystrokes are recorded as they are executed. + End the definition with rl_end_kbd_macro (). + If a numeric argument was explicitly typed, then append this + definition to the end of the existing macro, and start by + re-executing the existing macro. */ +int +rl_start_kbd_macro (ignore1, ignore2) + int ignore1, ignore2; +{ + if (RL_ISSTATE (RL_STATE_MACRODEF)) + { + _rl_abort_internal (); + return -1; + } + + if (rl_explicit_arg) + { + if (current_macro) + _rl_with_macro_input (savestring (current_macro)); + } + else + current_macro_index = 0; + + RL_SETSTATE(RL_STATE_MACRODEF); + return 0; +} + +/* Stop defining a keyboard macro. + A numeric argument says to execute the macro right now, + that many times, counting the definition as the first time. */ +int +rl_end_kbd_macro (count, ignore) + int count, ignore; +{ + if (RL_ISSTATE (RL_STATE_MACRODEF) == 0) + { + _rl_abort_internal (); + return -1; + } + + current_macro_index -= rl_key_sequence_length - 1; + current_macro[current_macro_index] = '\0'; + + RL_UNSETSTATE(RL_STATE_MACRODEF); + + return (rl_call_last_kbd_macro (--count, 0)); +} + +/* Execute the most recently defined keyboard macro. + COUNT says how many times to execute it. */ +int +rl_call_last_kbd_macro (count, ignore) + int count, ignore; +{ + if (current_macro == 0) + _rl_abort_internal (); + + if (RL_ISSTATE (RL_STATE_MACRODEF)) + { + rl_ding (); /* no recursive macros */ + current_macro[--current_macro_index] = '\0'; /* erase this char */ + return 0; + } + + while (count--) + _rl_with_macro_input (savestring (current_macro)); + return 0; +} + +void +rl_push_macro_input (macro) + char *macro; +{ + _rl_with_macro_input (macro); +} diff --git a/external/gpl3/gdb/dist/readline/mbutil.c b/external/gpl3/gdb/dist/readline/mbutil.c new file mode 100644 index 000000000000..17dde53ed7b4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/mbutil.c @@ -0,0 +1,373 @@ +/* mbutil.c -- readline multibyte character utility functions */ + +/* Copyright (C) 2001-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include "posixjmp.h" + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (TIOCSTAT_IN_SYS_IOCTL) +# include +#endif /* TIOCSTAT_IN_SYS_IOCTL */ + +/* Some standard library routines. */ +#include "readline.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* Declared here so it can be shared between the readline and history + libraries. */ +#if defined (HANDLE_MULTIBYTE) +int rl_byte_oriented = 0; +#else +int rl_byte_oriented = 1; +#endif + +/* **************************************************************** */ +/* */ +/* Multibyte Character Utility Functions */ +/* */ +/* **************************************************************** */ + +#if defined(HANDLE_MULTIBYTE) + +static int +_rl_find_next_mbchar_internal (string, seed, count, find_non_zero) + char *string; + int seed, count, find_non_zero; +{ + size_t tmp; + mbstate_t ps; + int point; + wchar_t wc; + + tmp = 0; + + memset(&ps, 0, sizeof (mbstate_t)); + if (seed < 0) + seed = 0; + if (count <= 0) + return seed; + + point = seed + _rl_adjust_point (string, seed, &ps); + /* if this is true, means that seed was not pointed character + started byte. So correct the point and consume count */ + if (seed < point) + count--; + + while (count > 0) + { + tmp = mbrtowc (&wc, string+point, strlen(string + point), &ps); + if (MB_INVALIDCH ((size_t)tmp)) + { + /* invalid bytes. asume a byte represents a character */ + point++; + count--; + /* reset states. */ + memset(&ps, 0, sizeof(mbstate_t)); + } + else if (MB_NULLWCH (tmp)) + break; /* found wide '\0' */ + else + { + /* valid bytes */ + point += tmp; + if (find_non_zero) + { + if (wcwidth (wc) == 0) + continue; + else + count--; + } + else + count--; + } + } + + if (find_non_zero) + { + tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps); + while (tmp > 0 && wcwidth (wc) == 0) + { + point += tmp; + tmp = mbrtowc (&wc, string + point, strlen (string + point), &ps); + if (MB_NULLWCH (tmp) || MB_INVALIDCH (tmp)) + break; + } + } + + return point; +} + +static int +_rl_find_prev_mbchar_internal (string, seed, find_non_zero) + char *string; + int seed, find_non_zero; +{ + mbstate_t ps; + int prev, non_zero_prev, point, length; + size_t tmp; + wchar_t wc; + + memset(&ps, 0, sizeof(mbstate_t)); + length = strlen(string); + + if (seed < 0) + return 0; + else if (length < seed) + return length; + + prev = non_zero_prev = point = 0; + while (point < seed) + { + tmp = mbrtowc (&wc, string + point, length - point, &ps); + if (MB_INVALIDCH ((size_t)tmp)) + { + /* in this case, bytes are invalid or shorted to compose + multibyte char, so assume that the first byte represents + a single character anyway. */ + tmp = 1; + /* clear the state of the byte sequence, because + in this case effect of mbstate is undefined */ + memset(&ps, 0, sizeof (mbstate_t)); + + /* Since we're assuming that this byte represents a single + non-zero-width character, don't forget about it. */ + prev = point; + } + else if (MB_NULLWCH (tmp)) + break; /* Found '\0' char. Can this happen? */ + else + { + if (find_non_zero) + { + if (wcwidth (wc) != 0) + prev = point; + } + else + prev = point; + } + + point += tmp; + } + + return prev; +} + +/* return the number of bytes parsed from the multibyte sequence starting + at src, if a non-L'\0' wide character was recognized. It returns 0, + if a L'\0' wide character was recognized. It returns (size_t)(-1), + if an invalid multibyte sequence was encountered. It returns (size_t)(-2) + if it couldn't parse a complete multibyte character. */ +int +_rl_get_char_len (src, ps) + char *src; + mbstate_t *ps; +{ + size_t tmp; + + tmp = mbrlen((const char *)src, (size_t)strlen (src), ps); + if (tmp == (size_t)(-2)) + { + /* shorted to compose multibyte char */ + if (ps) + memset (ps, 0, sizeof(mbstate_t)); + return -2; + } + else if (tmp == (size_t)(-1)) + { + /* invalid to compose multibyte char */ + /* initialize the conversion state */ + if (ps) + memset (ps, 0, sizeof(mbstate_t)); + return -1; + } + else if (tmp == (size_t)0) + return 0; + else + return (int)tmp; +} + +/* compare the specified two characters. If the characters matched, + return 1. Otherwise return 0. */ +int +_rl_compare_chars (buf1, pos1, ps1, buf2, pos2, ps2) + char *buf1; + int pos1; + mbstate_t *ps1; + char *buf2; + int pos2; + mbstate_t *ps2; +{ + int i, w1, w2; + + if ((w1 = _rl_get_char_len (&buf1[pos1], ps1)) <= 0 || + (w2 = _rl_get_char_len (&buf2[pos2], ps2)) <= 0 || + (w1 != w2) || + (buf1[pos1] != buf2[pos2])) + return 0; + + for (i = 1; i < w1; i++) + if (buf1[pos1+i] != buf2[pos2+i]) + return 0; + + return 1; +} + +/* adjust pointed byte and find mbstate of the point of string. + adjusted point will be point <= adjusted_point, and returns + differences of the byte(adjusted_point - point). + if point is invalied (point < 0 || more than string length), + it returns -1 */ +int +_rl_adjust_point(string, point, ps) + char *string; + int point; + mbstate_t *ps; +{ + size_t tmp = 0; + int length; + int pos = 0; + + length = strlen(string); + if (point < 0) + return -1; + if (length < point) + return -1; + + while (pos < point) + { + tmp = mbrlen (string + pos, length - pos, ps); + if (MB_INVALIDCH ((size_t)tmp)) + { + /* in this case, bytes are invalid or shorted to compose + multibyte char, so assume that the first byte represents + a single character anyway. */ + pos++; + /* clear the state of the byte sequence, because + in this case effect of mbstate is undefined */ + if (ps) + memset (ps, 0, sizeof (mbstate_t)); + } + else if (MB_NULLWCH (tmp)) + pos++; + else + pos += tmp; + } + + return (pos - point); +} + +int +_rl_is_mbchar_matched (string, seed, end, mbchar, length) + char *string; + int seed, end; + char *mbchar; + int length; +{ + int i; + + if ((end - seed) < length) + return 0; + + for (i = 0; i < length; i++) + if (string[seed + i] != mbchar[i]) + return 0; + return 1; +} + +wchar_t +_rl_char_value (buf, ind) + char *buf; + int ind; +{ + size_t tmp; + wchar_t wc; + mbstate_t ps; + int l; + + if (MB_LEN_MAX == 1 || rl_byte_oriented) + return ((wchar_t) buf[ind]); + l = strlen (buf); + if (ind >= l - 1) + return ((wchar_t) buf[ind]); + memset (&ps, 0, sizeof (mbstate_t)); + tmp = mbrtowc (&wc, buf + ind, l - ind, &ps); + if (MB_INVALIDCH (tmp) || MB_NULLWCH (tmp)) + return ((wchar_t) buf[ind]); + return wc; +} +#endif /* HANDLE_MULTIBYTE */ + +/* Find next `count' characters started byte point of the specified seed. + If flags is MB_FIND_NONZERO, we look for non-zero-width multibyte + characters. */ +#undef _rl_find_next_mbchar +int +_rl_find_next_mbchar (string, seed, count, flags) + char *string; + int seed, count, flags; +{ +#if defined (HANDLE_MULTIBYTE) + return _rl_find_next_mbchar_internal (string, seed, count, flags); +#else + return (seed + count); +#endif +} + +/* Find previous character started byte point of the specified seed. + Returned point will be point <= seed. If flags is MB_FIND_NONZERO, + we look for non-zero-width multibyte characters. */ +#undef _rl_find_prev_mbchar +int +_rl_find_prev_mbchar (string, seed, flags) + char *string; + int seed, flags; +{ +#if defined (HANDLE_MULTIBYTE) + return _rl_find_prev_mbchar_internal (string, seed, flags); +#else + return ((seed == 0) ? seed : seed - 1); +#endif +} diff --git a/external/gpl3/gdb/dist/readline/misc.c b/external/gpl3/gdb/dist/readline/misc.c new file mode 100644 index 000000000000..d4558321dec5 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/misc.c @@ -0,0 +1,601 @@ +/* misc.c -- miscellaneous bindable readline functions. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +static int rl_digit_loop PARAMS((void)); +static void _rl_history_set_point PARAMS((void)); + +/* Forward declarations used in this file */ +void _rl_free_history_entry PARAMS((HIST_ENTRY *)); + +/* If non-zero, rl_get_previous_history and rl_get_next_history attempt + to preserve the value of rl_point from line to line. */ +int _rl_history_preserve_point = 0; + +_rl_arg_cxt _rl_argcxt; + +/* Saved target point for when _rl_history_preserve_point is set. Special + value of -1 means that point is at the end of the line. */ +int _rl_history_saved_point = -1; + +/* **************************************************************** */ +/* */ +/* Numeric Arguments */ +/* */ +/* **************************************************************** */ + +int +_rl_arg_overflow () +{ + if (rl_numeric_arg > 1000000) + { + _rl_argcxt = 0; + rl_explicit_arg = rl_numeric_arg = 0; + rl_ding (); + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return 1; + } + return 0; +} + +void +_rl_arg_init () +{ + rl_save_prompt (); + _rl_argcxt = 0; + RL_SETSTATE(RL_STATE_NUMERICARG); +} + +int +_rl_arg_getchar () +{ + int c; + + rl_message ("(arg: %d) ", rl_arg_sign * rl_numeric_arg); + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + return c; +} + +/* Process C as part of the current numeric argument. Return -1 if the + argument should be aborted, 0 if we should not read any more chars, and + 1 if we should continue to read chars. */ +int +_rl_arg_dispatch (cxt, c) + _rl_arg_cxt cxt; + int c; +{ + int key, r; + + key = c; + + /* If we see a key bound to `universal-argument' after seeing digits, + it ends the argument but is otherwise ignored. */ + if (_rl_keymap[c].type == ISFUNC && _rl_keymap[c].function == rl_universal_argument) + { + if ((cxt & NUM_SAWDIGITS) == 0) + { + rl_numeric_arg *= 4; + return 1; + } + else if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_argcxt |= NUM_READONE; + return 0; /* XXX */ + } + else + { + RL_SETSTATE(RL_STATE_MOREINPUT); + key = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return (_rl_dispatch (key, _rl_keymap)); + } + } + + c = UNMETA (c); + + if (_rl_digit_p (c)) + { + r = _rl_digit_value (c); + rl_numeric_arg = rl_explicit_arg ? (rl_numeric_arg * 10) + r : r; + rl_explicit_arg = 1; + _rl_argcxt |= NUM_SAWDIGITS; + } + else if (c == '-' && rl_explicit_arg == 0) + { + rl_numeric_arg = 1; + _rl_argcxt |= NUM_SAWMINUS; + rl_arg_sign = -1; + } + else + { + /* Make M-- command equivalent to M--1 command. */ + if ((_rl_argcxt & NUM_SAWMINUS) && rl_numeric_arg == 1 && rl_explicit_arg == 0) + rl_explicit_arg = 1; + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + + r = _rl_dispatch (key, _rl_keymap); + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + /* At worst, this will cause an extra redisplay. Otherwise, + we have to wait until the next character comes in. */ + if (rl_done == 0) + (*rl_redisplay_function) (); + r = 0; + } + return r; + } + + return 1; +} + +/* Handle C-u style numeric args, as well as M--, and M-digits. */ +static int +rl_digit_loop () +{ + int c, r; + + while (1) + { + if (_rl_arg_overflow ()) + return 1; + + c = _rl_arg_getchar (); + + if (c < 0) + { + _rl_abort_internal (); + return -1; + } + + r = _rl_arg_dispatch (_rl_argcxt, c); + if (r <= 0 || (RL_ISSTATE (RL_STATE_NUMERICARG) == 0)) + break; + } +} + +/* Create a default argument. */ +void +_rl_reset_argument () +{ + rl_numeric_arg = rl_arg_sign = 1; + rl_explicit_arg = 0; + _rl_argcxt = 0; +} + +/* Start a numeric argument with initial value KEY */ +int +rl_digit_argument (ignore, key) + int ignore, key; +{ + _rl_arg_init (); + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_arg_dispatch (_rl_argcxt, key); + rl_message ("(arg: %d) ", rl_arg_sign * rl_numeric_arg); + return 0; + } + else + { + rl_execute_next (key); + return (rl_digit_loop ()); + } +} + +/* C-u, universal argument. Multiply the current argument by 4. + Read a key. If the key has nothing to do with arguments, then + dispatch on it. If the key is the abort character then abort. */ +int +rl_universal_argument (count, key) + int count, key; +{ + _rl_arg_init (); + rl_numeric_arg *= 4; + + return (RL_ISSTATE (RL_STATE_CALLBACK) ? 0 : rl_digit_loop ()); +} + +int +_rl_arg_callback (cxt) + _rl_arg_cxt cxt; +{ + int c, r; + + c = _rl_arg_getchar (); + + if (_rl_argcxt & NUM_READONE) + { + _rl_argcxt &= ~NUM_READONE; + rl_restore_prompt (); + rl_clear_message (); + RL_UNSETSTATE(RL_STATE_NUMERICARG); + rl_execute_next (c); + return 0; + } + + r = _rl_arg_dispatch (cxt, c); + return (r != 1); +} + +/* What to do when you abort reading an argument. */ +int +rl_discard_argument () +{ + rl_ding (); + rl_clear_message (); + _rl_reset_argument (); + + return 0; +} + +/* **************************************************************** */ +/* */ +/* History Utilities */ +/* */ +/* **************************************************************** */ + +/* We already have a history library, and that is what we use to control + the history features of readline. This is our local interface to + the history mechanism. */ + +/* While we are editing the history, this is the saved + version of the original line. */ +HIST_ENTRY *_rl_saved_line_for_history = (HIST_ENTRY *)NULL; + +/* Set the history pointer back to the last entry in the history. */ +void +_rl_start_using_history () +{ + using_history (); + if (_rl_saved_line_for_history) + _rl_free_history_entry (_rl_saved_line_for_history); + + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; +} + +/* Free the contents (and containing structure) of a HIST_ENTRY. */ +void +_rl_free_history_entry (entry) + HIST_ENTRY *entry; +{ + if (entry == 0) + return; + + FREE (entry->line); + FREE (entry->timestamp); + + free (entry); +} + +/* Perhaps put back the current line if it has changed. */ +int +rl_maybe_replace_line () +{ + HIST_ENTRY *temp; + + temp = current_history (); + /* If the current line has changed, save the changes. */ + if (temp && ((UNDO_LIST *)(temp->data) != rl_undo_list)) + { + temp = replace_history_entry (where_history (), rl_line_buffer, (histdata_t)rl_undo_list); + free (temp->line); + FREE (temp->timestamp); + free (temp); + } + return 0; +} + +/* Restore the _rl_saved_line_for_history if there is one. */ +int +rl_maybe_unsave_line () +{ + if (_rl_saved_line_for_history) + { + /* Can't call with `1' because rl_undo_list might point to an undo + list from a history entry, as in rl_replace_from_history() below. */ + rl_replace_line (_rl_saved_line_for_history->line, 0); + rl_undo_list = (UNDO_LIST *)_rl_saved_line_for_history->data; + _rl_free_history_entry (_rl_saved_line_for_history); + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; + rl_point = rl_end; /* rl_replace_line sets rl_end */ + } + else + rl_ding (); + return 0; +} + +/* Save the current line in _rl_saved_line_for_history. */ +int +rl_maybe_save_line () +{ + if (_rl_saved_line_for_history == 0) + { + _rl_saved_line_for_history = (HIST_ENTRY *)xmalloc (sizeof (HIST_ENTRY)); + _rl_saved_line_for_history->line = savestring (rl_line_buffer); + _rl_saved_line_for_history->timestamp = (char *)NULL; + _rl_saved_line_for_history->data = (char *)rl_undo_list; + } + + return 0; +} + +int +_rl_free_saved_history_line () +{ + if (_rl_saved_line_for_history) + { + _rl_free_history_entry (_rl_saved_line_for_history); + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; + } + return 0; +} + +static void +_rl_history_set_point () +{ + rl_point = (_rl_history_preserve_point && _rl_history_saved_point != -1) + ? _rl_history_saved_point + : rl_end; + if (rl_point > rl_end) + rl_point = rl_end; + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode && _rl_keymap != vi_insertion_keymap) + rl_point = 0; +#endif /* VI_MODE */ + + if (rl_editing_mode == emacs_mode) + rl_mark = (rl_point == rl_end ? 0 : rl_end); +} + +void +rl_replace_from_history (entry, flags) + HIST_ENTRY *entry; + int flags; /* currently unused */ +{ + /* Can't call with `1' because rl_undo_list might point to an undo list + from a history entry, just like we're setting up here. */ + rl_replace_line (entry->line, 0); + rl_undo_list = (UNDO_LIST *)entry->data; + rl_point = rl_end; + rl_mark = 0; + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + { + rl_point = 0; + rl_mark = rl_end; + } +#endif +} + +/* **************************************************************** */ +/* */ +/* History Commands */ +/* */ +/* **************************************************************** */ + +/* Meta-< goes to the start of the history. */ +int +rl_beginning_of_history (count, key) + int count, key; +{ + return (rl_get_previous_history (1 + where_history (), key)); +} + +/* Meta-> goes to the end of the history. (The current line). */ +int +rl_end_of_history (count, key) + int count, key; +{ + rl_maybe_replace_line (); + using_history (); + rl_maybe_unsave_line (); + return 0; +} + +/* Move down to the next history line. */ +int +rl_get_next_history (count, key) + int count, key; +{ + HIST_ENTRY *temp; + + if (count < 0) + return (rl_get_previous_history (-count, key)); + + if (count == 0) + return 0; + + rl_maybe_replace_line (); + + /* either not saved by rl_newline or at end of line, so set appropriately. */ + if (_rl_history_saved_point == -1 && (rl_point || rl_end)) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + temp = (HIST_ENTRY *)NULL; + while (count) + { + temp = next_history (); + if (!temp) + break; + --count; + } + + if (temp == 0) + rl_maybe_unsave_line (); + else + { + rl_replace_from_history (temp, 0); + _rl_history_set_point (); + } + return 0; +} + +/* Get the previous item out of our interactive history, making it the current + line. If there is no previous history, just ding. */ +int +rl_get_previous_history (count, key) + int count, key; +{ + HIST_ENTRY *old_temp, *temp; + + if (count < 0) + return (rl_get_next_history (-count, key)); + + if (count == 0) + return 0; + + /* either not saved by rl_newline or at end of line, so set appropriately. */ + if (_rl_history_saved_point == -1 && (rl_point || rl_end)) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + /* If we don't have a line saved, then save this one. */ + rl_maybe_save_line (); + + /* If the current line has changed, save the changes. */ + rl_maybe_replace_line (); + + temp = old_temp = (HIST_ENTRY *)NULL; + while (count) + { + temp = previous_history (); + if (temp == 0) + break; + + old_temp = temp; + --count; + } + + /* If there was a large argument, and we moved back to the start of the + history, that is not an error. So use the last value found. */ + if (!temp && old_temp) + temp = old_temp; + + if (temp == 0) + rl_ding (); + else + { + rl_replace_from_history (temp, 0); + _rl_history_set_point (); + } + + return 0; +} + +/* **************************************************************** */ +/* */ +/* Editing Modes */ +/* */ +/* **************************************************************** */ +/* How to toggle back and forth between editing modes. */ +int +rl_vi_editing_mode (count, key) + int count, key; +{ +#if defined (VI_MODE) + _rl_set_insert_mode (RL_IM_INSERT, 1); /* vi mode ignores insert mode */ + rl_editing_mode = vi_mode; + rl_vi_insertion_mode (1, key); +#endif /* VI_MODE */ + + return 0; +} + +int +rl_emacs_editing_mode (count, key) + int count, key; +{ + rl_editing_mode = emacs_mode; + _rl_set_insert_mode (RL_IM_INSERT, 1); /* emacs mode default is insert mode */ + _rl_keymap = emacs_standard_keymap; + return 0; +} + +/* Function for the rest of the library to use to set insert/overwrite mode. */ +void +_rl_set_insert_mode (im, force) + int im, force; +{ +#ifdef CURSOR_MODE + _rl_set_cursor (im, force); +#endif + + rl_insert_mode = im; +} + +/* Toggle overwrite mode. A positive explicit argument selects overwrite + mode. A negative or zero explicit argument selects insert mode. */ +int +rl_overwrite_mode (count, key) + int count, key; +{ + if (rl_explicit_arg == 0) + _rl_set_insert_mode (rl_insert_mode ^ 1, 0); + else if (count > 0) + _rl_set_insert_mode (RL_IM_OVERWRITE, 0); + else + _rl_set_insert_mode (RL_IM_INSERT, 0); + + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/nls.c b/external/gpl3/gdb/dist/readline/nls.c new file mode 100644 index 000000000000..bcee87561aaa --- /dev/null +++ b/external/gpl3/gdb/dist/readline/nls.c @@ -0,0 +1,252 @@ +/* nls.c -- skeletal internationalization code. */ + +/* Copyright (C) 1996 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +#include "rldefs.h" +#include "readline.h" +#include "rlshell.h" +#include "rlprivate.h" + +#if !defined (HAVE_SETLOCALE) +/* A list of legal values for the LANG or LC_CTYPE environment variables. + If a locale name in this list is the value for the LC_ALL, LC_CTYPE, + or LANG environment variable (using the first of those with a value), + readline eight-bit mode is enabled. */ +static char *legal_lang_values[] = +{ + "iso88591", + "iso88592", + "iso88593", + "iso88594", + "iso88595", + "iso88596", + "iso88597", + "iso88598", + "iso88599", + "iso885910", + "koi8r", + 0 +}; + +static char *normalize_codeset PARAMS((char *)); +static char *find_codeset PARAMS((char *, size_t *)); +#endif /* !HAVE_SETLOCALE */ + +static char *_rl_get_locale_var PARAMS((const char *)); + +static char * +_rl_get_locale_var (v) + const char *v; +{ + char *lspec; + + lspec = sh_get_env_value ("LC_ALL"); + if (lspec == 0 || *lspec == 0) + lspec = sh_get_env_value (v); + if (lspec == 0 || *lspec == 0) + lspec = sh_get_env_value ("LANG"); + + return lspec; +} + +/* Check for LC_ALL, LC_CTYPE, and LANG and use the first with a value + to decide the defaults for 8-bit character input and output. Returns + 1 if we set eight-bit mode. */ +int +_rl_init_eightbit () +{ +/* If we have setlocale(3), just check the current LC_CTYPE category + value, and go into eight-bit mode if it's not C or POSIX. */ +#if defined (HAVE_SETLOCALE) + char *lspec, *t; + + /* Set the LC_CTYPE locale category from environment variables. */ + lspec = _rl_get_locale_var ("LC_CTYPE"); + /* Since _rl_get_locale_var queries the right environment variables, + we query the current locale settings with setlocale(), and, if + that doesn't return anything, we set lspec to the empty string to + force the subsequent call to setlocale() to define the `native' + environment. */ + if (lspec == 0 || *lspec == 0) + lspec = setlocale (LC_CTYPE, (char *)NULL); + if (lspec == 0) + lspec = ""; + t = setlocale (LC_CTYPE, lspec); + + if (t && *t && (t[0] != 'C' || t[1]) && (STREQ (t, "POSIX") == 0)) + { + _rl_meta_flag = 1; + _rl_convert_meta_chars_to_ascii = 0; + _rl_output_meta_chars = 1; + return (1); + } + else + return (0); + +#else /* !HAVE_SETLOCALE */ + char *lspec, *t; + int i; + + /* We don't have setlocale. Finesse it. Check the environment for the + appropriate variables and set eight-bit mode if they have the right + values. */ + lspec = _rl_get_locale_var ("LC_CTYPE"); + + if (lspec == 0 || (t = normalize_codeset (lspec)) == 0) + return (0); + for (i = 0; t && legal_lang_values[i]; i++) + if (STREQ (t, legal_lang_values[i])) + { + _rl_meta_flag = 1; + _rl_convert_meta_chars_to_ascii = 0; + _rl_output_meta_chars = 1; + break; + } + free (t); + return (legal_lang_values[i] ? 1 : 0); + +#endif /* !HAVE_SETLOCALE */ +} + +#if !defined (HAVE_SETLOCALE) +static char * +normalize_codeset (codeset) + char *codeset; +{ + size_t namelen, i; + int len, all_digits; + char *wp, *retval; + + codeset = find_codeset (codeset, &namelen); + + if (codeset == 0) + return (codeset); + + all_digits = 1; + for (len = 0, i = 0; i < namelen; i++) + { + if (ISALNUM ((unsigned char)codeset[i])) + { + len++; + all_digits &= _rl_digit_p (codeset[i]); + } + } + + retval = (char *)malloc ((all_digits ? 3 : 0) + len + 1); + if (retval == 0) + return ((char *)0); + + wp = retval; + /* Add `iso' to beginning of an all-digit codeset */ + if (all_digits) + { + *wp++ = 'i'; + *wp++ = 's'; + *wp++ = 'o'; + } + + for (i = 0; i < namelen; i++) + if (ISALPHA ((unsigned char)codeset[i])) + *wp++ = _rl_to_lower (codeset[i]); + else if (_rl_digit_p (codeset[i])) + *wp++ = codeset[i]; + *wp = '\0'; + + return retval; +} + +/* Isolate codeset portion of locale specification. */ +static char * +find_codeset (name, lenp) + char *name; + size_t *lenp; +{ + char *cp, *language, *result; + + cp = language = name; + result = (char *)0; + + while (*cp && *cp != '_' && *cp != '@' && *cp != '+' && *cp != ',') + cp++; + + /* This does not make sense: language has to be specified. As + an exception we allow the variable to contain only the codeset + name. Perhaps there are funny codeset names. */ + if (language == cp) + { + *lenp = strlen (language); + result = language; + } + else + { + /* Next is the territory. */ + if (*cp == '_') + do + ++cp; + while (*cp && *cp != '.' && *cp != '@' && *cp != '+' && *cp != ',' && *cp != '_'); + + /* Now, finally, is the codeset. */ + result = cp; + if (*cp == '.') + do + ++cp; + while (*cp && *cp != '@'); + + if (cp - result > 2) + { + result++; + *lenp = cp - result; + } + else + { + *lenp = strlen (language); + result = language; + } + } + + return result; +} +#endif /* !HAVE_SETLOCALE */ diff --git a/external/gpl3/gdb/dist/readline/parens.c b/external/gpl3/gdb/dist/readline/parens.c new file mode 100644 index 000000000000..737f7675e939 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/parens.c @@ -0,0 +1,183 @@ +/* parens.c -- Implementation of matching parentheses feature. */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (__TANDEM) +# include +#endif + +#include "rlconf.h" + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif + +#if defined (FD_SET) && !defined (HAVE_SELECT) +# define HAVE_SELECT +#endif + +#if defined (HAVE_SELECT) +# include +#endif /* HAVE_SELECT */ +#if defined (HAVE_SYS_SELECT_H) +# include +#endif + +#if defined (HAVE_STRING_H) +# include +#else /* !HAVE_STRING_H */ +# include +#endif /* !HAVE_STRING_H */ + +#if !defined (strchr) && !defined (__STDC__) +extern char *strchr (), *strrchr (); +#endif /* !strchr && !__STDC__ */ + +#include "readline.h" +#include "rlprivate.h" + +static int find_matching_open PARAMS((char *, int, int)); + +/* Non-zero means try to blink the matching open parenthesis when the + close parenthesis is inserted. */ +#if defined (HAVE_SELECT) +int rl_blink_matching_paren = 1; +#else /* !HAVE_SELECT */ +int rl_blink_matching_paren = 0; +#endif /* !HAVE_SELECT */ + +static int _paren_blink_usec = 500000; + +/* Change emacs_standard_keymap to have bindings for paren matching when + ON_OR_OFF is 1, change them back to self_insert when ON_OR_OFF == 0. */ +void +_rl_enable_paren_matching (on_or_off) + int on_or_off; +{ + if (on_or_off) + { /* ([{ */ + rl_bind_key_in_map (')', rl_insert_close, emacs_standard_keymap); + rl_bind_key_in_map (']', rl_insert_close, emacs_standard_keymap); + rl_bind_key_in_map ('}', rl_insert_close, emacs_standard_keymap); + } + else + { /* ([{ */ + rl_bind_key_in_map (')', rl_insert, emacs_standard_keymap); + rl_bind_key_in_map (']', rl_insert, emacs_standard_keymap); + rl_bind_key_in_map ('}', rl_insert, emacs_standard_keymap); + } +} + +int +rl_set_paren_blink_timeout (u) + int u; +{ + int o; + + o = _paren_blink_usec; + if (u > 0) + _paren_blink_usec = u; + return (o); +} + +int +rl_insert_close (count, invoking_key) + int count, invoking_key; +{ + if (rl_explicit_arg || !rl_blink_matching_paren) + _rl_insert_char (count, invoking_key); + else + { +#if defined (HAVE_SELECT) + int orig_point, match_point, ready; + struct timeval timer; + fd_set readfds; + + _rl_insert_char (1, invoking_key); + (*rl_redisplay_function) (); + match_point = + find_matching_open (rl_line_buffer, rl_point - 2, invoking_key); + + /* Emacs might message or ring the bell here, but I don't. */ + if (match_point < 0) + return -1; + + FD_ZERO (&readfds); + FD_SET (fileno (rl_instream), &readfds); + timer.tv_sec = 0; + timer.tv_usec = _paren_blink_usec; + + orig_point = rl_point; + rl_point = match_point; + (*rl_redisplay_function) (); + ready = select (1, &readfds, (fd_set *)NULL, (fd_set *)NULL, &timer); + rl_point = orig_point; +#else /* !HAVE_SELECT */ + _rl_insert_char (count, invoking_key); +#endif /* !HAVE_SELECT */ + } + return 0; +} + +static int +find_matching_open (string, from, closer) + char *string; + int from, closer; +{ + register int i; + int opener, level, delimiter; + + switch (closer) + { + case ']': opener = '['; break; + case '}': opener = '{'; break; + case ')': opener = '('; break; + default: + return (-1); + } + + level = 1; /* The closer passed in counts as 1. */ + delimiter = 0; /* Delimited state unknown. */ + + for (i = from; i > -1; i--) + { + if (delimiter && (string[i] == delimiter)) + delimiter = 0; + else if (rl_basic_quote_characters && strchr (rl_basic_quote_characters, string[i])) + delimiter = string[i]; + else if (!delimiter && (string[i] == closer)) + level++; + else if (!delimiter && (string[i] == opener)) + level--; + + if (!level) + break; + } + return (i); +} diff --git a/external/gpl3/gdb/dist/readline/posixdir.h b/external/gpl3/gdb/dist/readline/posixdir.h new file mode 100644 index 000000000000..91f6d96111d0 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/posixdir.h @@ -0,0 +1,61 @@ +/* posixdir.h -- Posix directory reading includes and defines. */ + +/* Copyright (C) 1987,1991 Free Software Foundation, Inc. + + This file is part of GNU Bash, the Bourne Again SHell. + + Bash is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + Bash is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with Bash; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +/* This file should be included instead of or . */ + +#if !defined (_POSIXDIR_H_) +#define _POSIXDIR_H_ + +#if defined (HAVE_DIRENT_H) +# include +# if defined (HAVE_STRUCT_DIRENT_D_NAMLEN) +# define D_NAMLEN(d) ((d)->d_namlen) +# else +# define D_NAMLEN(d) (strlen ((d)->d_name)) +# endif /* !HAVE_STRUCT_DIRENT_D_NAMLEN */ +#else +# if defined (HAVE_SYS_NDIR_H) +# include +# endif +# if defined (HAVE_SYS_DIR_H) +# include +# endif +# if defined (HAVE_NDIR_H) +# include +# endif +# if !defined (dirent) +# define dirent direct +# endif /* !dirent */ +# define D_NAMLEN(d) ((d)->d_namlen) +#endif /* !HAVE_DIRENT_H */ + +#if defined (HAVE_STRUCT_DIRENT_D_INO) && !defined (HAVE_STRUCT_DIRENT_D_FILENO) +# define d_fileno d_ino +#endif + +#if defined (_POSIX_SOURCE) && (!defined (HAVE_STRUCT_DIRENT_D_INO) || defined (BROKEN_DIRENT_D_INO)) +/* Posix does not require that the d_ino field be present, and some + systems do not provide it. */ +# define REAL_DIR_ENTRY(dp) 1 +#else +# define REAL_DIR_ENTRY(dp) (dp->d_ino != 0) +#endif /* _POSIX_SOURCE */ + +#endif /* !_POSIXDIR_H_ */ diff --git a/external/gpl3/gdb/dist/readline/posixjmp.h b/external/gpl3/gdb/dist/readline/posixjmp.h new file mode 100644 index 000000000000..b52aa00332b6 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/posixjmp.h @@ -0,0 +1,40 @@ +/* posixjmp.h -- wrapper for setjmp.h with changes for POSIX systems. */ + +/* Copyright (C) 1987,1991 Free Software Foundation, Inc. + + This file is part of GNU Bash, the Bourne Again SHell. + + Bash is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + Bash is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with Bash; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _POSIXJMP_H_ +#define _POSIXJMP_H_ + +#include + +/* This *must* be included *after* config.h */ + +#if defined (HAVE_POSIX_SIGSETJMP) +# define procenv_t sigjmp_buf +# if !defined (__OPENNT) +# undef setjmp +# define setjmp(x) sigsetjmp((x), 1) +# undef longjmp +# define longjmp(x, n) siglongjmp((x), (n)) +# endif /* !__OPENNT */ +#else +# define procenv_t jmp_buf +#endif + +#endif /* _POSIXJMP_H_ */ diff --git a/external/gpl3/gdb/dist/readline/posixstat.h b/external/gpl3/gdb/dist/readline/posixstat.h new file mode 100644 index 000000000000..c93b52887e9d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/posixstat.h @@ -0,0 +1,142 @@ +/* posixstat.h -- Posix stat(2) definitions for systems that + don't have them. */ + +/* Copyright (C) 1987,1991 Free Software Foundation, Inc. + + This file is part of GNU Bash, the Bourne Again SHell. + + Bash is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + Bash is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with Bash; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +/* This file should be included instead of . + It relies on the local sys/stat.h to work though. */ +#if !defined (_POSIXSTAT_H_) +#define _POSIXSTAT_H_ + +#include + +#if defined (STAT_MACROS_BROKEN) +# undef S_ISBLK +# undef S_ISCHR +# undef S_ISDIR +# undef S_ISFIFO +# undef S_ISREG +# undef S_ISLNK +#endif /* STAT_MACROS_BROKEN */ + +/* These are guaranteed to work only on isc386 */ +#if !defined (S_IFDIR) && !defined (S_ISDIR) +# define S_IFDIR 0040000 +#endif /* !S_IFDIR && !S_ISDIR */ +#if !defined (S_IFMT) +# define S_IFMT 0170000 +#endif /* !S_IFMT */ + +/* Posix 1003.1 5.6.1.1 file types */ + +/* Some Posix-wannabe systems define _S_IF* macros instead of S_IF*, but + do not provide the S_IS* macros that Posix requires. */ + +#if defined (_S_IFMT) && !defined (S_IFMT) +#define S_IFMT _S_IFMT +#endif +#if defined (_S_IFIFO) && !defined (S_IFIFO) +#define S_IFIFO _S_IFIFO +#endif +#if defined (_S_IFCHR) && !defined (S_IFCHR) +#define S_IFCHR _S_IFCHR +#endif +#if defined (_S_IFDIR) && !defined (S_IFDIR) +#define S_IFDIR _S_IFDIR +#endif +#if defined (_S_IFBLK) && !defined (S_IFBLK) +#define S_IFBLK _S_IFBLK +#endif +#if defined (_S_IFREG) && !defined (S_IFREG) +#define S_IFREG _S_IFREG +#endif +#if defined (_S_IFLNK) && !defined (S_IFLNK) +#define S_IFLNK _S_IFLNK +#endif +#if defined (_S_IFSOCK) && !defined (S_IFSOCK) +#define S_IFSOCK _S_IFSOCK +#endif + +/* Test for each symbol individually and define the ones necessary (some + systems claiming Posix compatibility define some but not all). */ + +#if defined (S_IFBLK) && !defined (S_ISBLK) +#define S_ISBLK(m) (((m)&S_IFMT) == S_IFBLK) /* block device */ +#endif + +#if defined (S_IFCHR) && !defined (S_ISCHR) +#define S_ISCHR(m) (((m)&S_IFMT) == S_IFCHR) /* character device */ +#endif + +#if defined (S_IFDIR) && !defined (S_ISDIR) +#define S_ISDIR(m) (((m)&S_IFMT) == S_IFDIR) /* directory */ +#endif + +#if defined (S_IFREG) && !defined (S_ISREG) +#define S_ISREG(m) (((m)&S_IFMT) == S_IFREG) /* file */ +#endif + +#if defined (S_IFIFO) && !defined (S_ISFIFO) +#define S_ISFIFO(m) (((m)&S_IFMT) == S_IFIFO) /* fifo - named pipe */ +#endif + +#if defined (S_IFLNK) && !defined (S_ISLNK) +#define S_ISLNK(m) (((m)&S_IFMT) == S_IFLNK) /* symbolic link */ +#endif + +#if defined (S_IFSOCK) && !defined (S_ISSOCK) +#define S_ISSOCK(m) (((m)&S_IFMT) == S_IFSOCK) /* socket */ +#endif + +/* + * POSIX 1003.1 5.6.1.2 File Modes + */ + +#if !defined (S_IRWXU) +# if !defined (S_IREAD) +# define S_IREAD 00400 +# define S_IWRITE 00200 +# define S_IEXEC 00100 +# endif /* S_IREAD */ + +# if !defined (S_IRUSR) +# define S_IRUSR S_IREAD /* read, owner */ +# define S_IWUSR S_IWRITE /* write, owner */ +# define S_IXUSR S_IEXEC /* execute, owner */ + +# define S_IRGRP (S_IREAD >> 3) /* read, group */ +# define S_IWGRP (S_IWRITE >> 3) /* write, group */ +# define S_IXGRP (S_IEXEC >> 3) /* execute, group */ + +# define S_IROTH (S_IREAD >> 6) /* read, other */ +# define S_IWOTH (S_IWRITE >> 6) /* write, other */ +# define S_IXOTH (S_IEXEC >> 6) /* execute, other */ +# endif /* !S_IRUSR */ + +# define S_IRWXU (S_IRUSR | S_IWUSR | S_IXUSR) +# define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP) +# define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH) +#endif /* !S_IRWXU */ + +/* These are non-standard, but are used in builtins.c$symbolic_umask() */ +#define S_IRUGO (S_IRUSR | S_IRGRP | S_IROTH) +#define S_IWUGO (S_IWUSR | S_IWGRP | S_IWOTH) +#define S_IXUGO (S_IXUSR | S_IXGRP | S_IXOTH) + +#endif /* _POSIXSTAT_H_ */ diff --git a/external/gpl3/gdb/dist/readline/readline.c b/external/gpl3/gdb/dist/readline/readline.c new file mode 100644 index 000000000000..5eaaf47435e6 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/readline.c @@ -0,0 +1,1195 @@ +/* readline.c -- a general facility for reading lines of input + with emacs style editing and completion. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include "posixstat.h" +#include +#if defined (HAVE_SYS_FILE_H) +# include +#endif /* HAVE_SYS_FILE_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include +#include "posixjmp.h" + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (__EMX__) +# define INCL_DOSPROCESS +# include +#endif /* __EMX__ */ + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +#ifndef RL_LIBRARY_VERSION +# define RL_LIBRARY_VERSION "5.1" +#endif + +#ifndef RL_READLINE_VERSION +# define RL_READLINE_VERSION 0x0501 +#endif + +extern void _rl_free_history_entry PARAMS((HIST_ENTRY *)); + +/* Forward declarations used in this file. */ +static char *readline_internal PARAMS((void)); +static void readline_initialize_everything PARAMS((void)); + +static void bind_arrow_keys_internal PARAMS((Keymap)); +static void bind_arrow_keys PARAMS((void)); + +static void readline_default_bindings PARAMS((void)); +static void reset_default_bindings PARAMS((void)); + +static int _rl_subseq_result PARAMS((int, Keymap, int, int)); +static int _rl_subseq_getchar PARAMS((int)); + +/* **************************************************************** */ +/* */ +/* Line editing input utility */ +/* */ +/* **************************************************************** */ + +const char *rl_library_version = RL_LIBRARY_VERSION; + +int rl_readline_version = RL_READLINE_VERSION; + +/* True if this is `real' readline as opposed to some stub substitute. */ +int rl_gnu_readline_p = 1; + +/* A pointer to the keymap that is currently in use. + By default, it is the standard emacs keymap. */ +Keymap _rl_keymap = emacs_standard_keymap; + + +/* The current style of editing. */ +int rl_editing_mode = emacs_mode; + +/* The current insert mode: input (the default) or overwrite */ +int rl_insert_mode = RL_IM_DEFAULT; + +/* Non-zero if we called this function from _rl_dispatch(). It's present + so functions can find out whether they were called from a key binding + or directly from an application. */ +int rl_dispatching; + +/* Non-zero if the previous command was a kill command. */ +int _rl_last_command_was_kill = 0; + +/* The current value of the numeric argument specified by the user. */ +int rl_numeric_arg = 1; + +/* Non-zero if an argument was typed. */ +int rl_explicit_arg = 0; + +/* Temporary value used while generating the argument. */ +int rl_arg_sign = 1; + +/* Non-zero means we have been called at least once before. */ +static int rl_initialized; + +#if 0 +/* If non-zero, this program is running in an EMACS buffer. */ +static int running_in_emacs; +#endif + +/* Flags word encapsulating the current readline state. */ +int rl_readline_state = RL_STATE_NONE; + +/* The current offset in the current input line. */ +int rl_point; + +/* Mark in the current input line. */ +int rl_mark; + +/* Length of the current input line. */ +int rl_end; + +/* Make this non-zero to return the current input_line. */ +int rl_done; + +/* The last function executed by readline. */ +rl_command_func_t *rl_last_func = (rl_command_func_t *)NULL; + +/* Top level environment for readline_internal (). */ +procenv_t readline_top_level; + +/* The streams we interact with. */ +FILE *_rl_in_stream, *_rl_out_stream; + +/* The names of the streams that we do input and output to. */ +FILE *rl_instream = (FILE *)NULL; +FILE *rl_outstream = (FILE *)NULL; + +/* Non-zero means echo characters as they are read. Defaults to no echo; + set to 1 if there is a controlling terminal, we can get its attributes, + and the attributes include `echo'. Look at rltty.c:prepare_terminal_settings + for the code that sets it. */ +int readline_echoing_p = 0; + +/* Current prompt. */ +char *rl_prompt = (char *)NULL; +int rl_visible_prompt_length = 0; + +/* Set to non-zero by calling application if it has already printed rl_prompt + and does not want readline to do it the first time. */ +int rl_already_prompted = 0; + +/* The number of characters read in order to type this complete command. */ +int rl_key_sequence_length = 0; + +/* If non-zero, then this is the address of a function to call just + before readline_internal_setup () prints the first prompt. */ +rl_hook_func_t *rl_startup_hook = (rl_hook_func_t *)NULL; + +/* If non-zero, this is the address of a function to call just before + readline_internal_setup () returns and readline_internal starts + reading input characters. */ +rl_hook_func_t *rl_pre_input_hook = (rl_hook_func_t *)NULL; + +/* What we use internally. You should always refer to RL_LINE_BUFFER. */ +static char *the_line; + +/* The character that can generate an EOF. Really read from + the terminal driver... just defaulted here. */ +int _rl_eof_char = CTRL ('D'); + +/* Non-zero makes this the next keystroke to read. */ +int rl_pending_input = 0; + +/* Pointer to a useful terminal name. */ +const char *rl_terminal_name = (const char *)NULL; + +/* Non-zero means to always use horizontal scrolling in line display. */ +int _rl_horizontal_scroll_mode = 0; + +/* Non-zero means to display an asterisk at the starts of history lines + which have been modified. */ +int _rl_mark_modified_lines = 0; + +/* The style of `bell' notification preferred. This can be set to NO_BELL, + AUDIBLE_BELL, or VISIBLE_BELL. */ +int _rl_bell_preference = AUDIBLE_BELL; + +/* String inserted into the line by rl_insert_comment (). */ +char *_rl_comment_begin; + +/* Keymap holding the function currently being executed. */ +Keymap rl_executing_keymap; + +/* Keymap we're currently using to dispatch. */ +Keymap _rl_dispatching_keymap; + +/* Non-zero means to erase entire line, including prompt, on empty input lines. */ +int rl_erase_empty_line = 0; + +/* Non-zero means to read only this many characters rather than up to a + character bound to accept-line. */ +int rl_num_chars_to_read; + +/* Line buffer and maintenence. */ +char *rl_line_buffer = (char *)NULL; +int rl_line_buffer_len = 0; + +/* Key sequence `contexts' */ +_rl_keyseq_cxt *_rl_kscxt = 0; + +/* Forward declarations used by the display, termcap, and history code. */ + +/* **************************************************************** */ +/* */ +/* `Forward' declarations */ +/* */ +/* **************************************************************** */ + +/* Non-zero means do not parse any lines other than comments and + parser directives. */ +unsigned char _rl_parsing_conditionalized_out = 0; + +/* Non-zero means to convert characters with the meta bit set to + escape-prefixed characters so we can indirect through + emacs_meta_keymap or vi_escape_keymap. */ +int _rl_convert_meta_chars_to_ascii = 1; + +/* Non-zero means to output characters with the meta bit set directly + rather than as a meta-prefixed escape sequence. */ +int _rl_output_meta_chars = 0; + +/* Non-zero means to look at the termios special characters and bind + them to equivalent readline functions at startup. */ +int _rl_bind_stty_chars = 1; + +/* **************************************************************** */ +/* */ +/* Top Level Functions */ +/* */ +/* **************************************************************** */ + +/* Non-zero means treat 0200 bit in terminal input as Meta bit. */ +int _rl_meta_flag = 0; /* Forward declaration */ + +/* Set up the prompt and expand it. Called from readline() and + rl_callback_handler_install (). */ +int +rl_set_prompt (prompt) + const char *prompt; +{ + FREE (rl_prompt); + rl_prompt = prompt ? savestring (prompt) : (char *)NULL; + rl_display_prompt = rl_prompt ? rl_prompt : ""; + + rl_visible_prompt_length = rl_expand_prompt (rl_prompt); + return 0; +} + +/* Read a line of input. Prompt with PROMPT. An empty PROMPT means + none. A return value of NULL means that EOF was encountered. */ +char * +readline (prompt) + const char *prompt; +{ + char *value; + + /* If we are at EOF return a NULL string. */ + if (rl_pending_input == EOF) + { + rl_clear_pending_input (); + return ((char *)NULL); + } + + rl_set_prompt (prompt); + + rl_initialize (); + if (rl_prep_term_function) + (*rl_prep_term_function) (_rl_meta_flag); + +#if defined (HANDLE_SIGNALS) + rl_set_signals (); +#endif + + value = readline_internal (); + if (rl_deprep_term_function) + (*rl_deprep_term_function) (); + +#if defined (HANDLE_SIGNALS) + rl_clear_signals (); +#endif + + return (value); +} + +#if defined (READLINE_CALLBACKS) +# define STATIC_CALLBACK +#else +# define STATIC_CALLBACK static +#endif + +STATIC_CALLBACK void +readline_internal_setup () +{ + char *nprompt; + + _rl_in_stream = rl_instream; + _rl_out_stream = rl_outstream; + + if (rl_startup_hook) + (*rl_startup_hook) (); + + /* If we're not echoing, we still want to at least print a prompt, because + rl_redisplay will not do it for us. If the calling application has a + custom redisplay function, though, let that function handle it. */ + if (readline_echoing_p == 0 && rl_redisplay_function == rl_redisplay) + { + if (rl_prompt && rl_already_prompted == 0) + { + nprompt = _rl_strip_prompt (rl_prompt); + fprintf (_rl_out_stream, "%s", nprompt); + fflush (_rl_out_stream); + free (nprompt); + } + } + else + { + if (rl_prompt && rl_already_prompted) + rl_on_new_line_with_prompt (); + else + rl_on_new_line (); + (*rl_redisplay_function) (); + } + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + rl_vi_insertion_mode (1, 'i'); +#endif /* VI_MODE */ + + if (rl_pre_input_hook) + (*rl_pre_input_hook) (); +} + +STATIC_CALLBACK char * +readline_internal_teardown (eof) + int eof; +{ + char *temp; + HIST_ENTRY *entry; + + /* Restore the original of this history line, iff the line that we + are editing was originally in the history, AND the line has changed. */ + entry = current_history (); + + if (entry && rl_undo_list) + { + temp = savestring (the_line); + rl_revert_line (1, 0); + entry = replace_history_entry (where_history (), the_line, (histdata_t)NULL); + _rl_free_history_entry (entry); + + strcpy (the_line, temp); + free (temp); + } + + /* At any rate, it is highly likely that this line has an undo list. Get + rid of it now. */ + if (rl_undo_list) + rl_free_undo_list (); + + /* Restore normal cursor, if available. */ + _rl_set_insert_mode (RL_IM_INSERT, 0); + + return (eof ? (char *)NULL : savestring (the_line)); +} + +void +_rl_internal_char_cleanup () +{ +#if defined (VI_MODE) + /* In vi mode, when you exit insert mode, the cursor moves back + over the previous character. We explicitly check for that here. */ + if (rl_editing_mode == vi_mode && _rl_keymap == vi_movement_keymap) + rl_vi_check (); +#endif /* VI_MODE */ + + if (rl_num_chars_to_read && rl_end >= rl_num_chars_to_read) + { + (*rl_redisplay_function) (); + _rl_want_redisplay = 0; + rl_newline (1, '\n'); + } + + if (rl_done == 0) + { + (*rl_redisplay_function) (); + _rl_want_redisplay = 0; + } + + /* If the application writer has told us to erase the entire line if + the only character typed was something bound to rl_newline, do so. */ + if (rl_erase_empty_line && rl_done && rl_last_func == rl_newline && + rl_point == 0 && rl_end == 0) + _rl_erase_entire_line (); +} + +STATIC_CALLBACK int +#if defined (READLINE_CALLBACKS) +readline_internal_char () +#else +readline_internal_charloop () +#endif +{ + static int lastc, eof_found; + int c, code, lk; + + lastc = -1; + eof_found = 0; + +#if !defined (READLINE_CALLBACKS) + while (rl_done == 0) + { +#endif + lk = _rl_last_command_was_kill; + + code = setjmp (readline_top_level); + + if (code) + { + (*rl_redisplay_function) (); + _rl_want_redisplay = 0; + /* If we get here, we're not being called from something dispatched + from _rl_callback_read_char(), which sets up its own value of + readline_top_level (saving and restoring the old, of course), so + we can just return here. */ + if (RL_ISSTATE (RL_STATE_CALLBACK)) + return (0); + } + + if (rl_pending_input == 0) + { + /* Then initialize the argument and number of keys read. */ + _rl_reset_argument (); + rl_key_sequence_length = 0; + } + + RL_SETSTATE(RL_STATE_READCMD); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_READCMD); + + /* EOF typed to a non-blank line is a . */ + if (c == EOF && rl_end) + c = NEWLINE; + + /* The character _rl_eof_char typed to blank line, and not as the + previous character is interpreted as EOF. */ + if (((c == _rl_eof_char && lastc != c) || c == EOF) && !rl_end) + { +#if defined (READLINE_CALLBACKS) + RL_SETSTATE(RL_STATE_DONE); + return (rl_done = 1); +#else + eof_found = 1; + break; +#endif + } + + lastc = c; + _rl_dispatch ((unsigned char)c, _rl_keymap); + + /* If there was no change in _rl_last_command_was_kill, then no kill + has taken place. Note that if input is pending we are reading + a prefix command, so nothing has changed yet. */ + if (rl_pending_input == 0 && lk == _rl_last_command_was_kill) + _rl_last_command_was_kill = 0; + + _rl_internal_char_cleanup (); + +#if defined (READLINE_CALLBACKS) + return 0; +#else + } + + return (eof_found); +#endif +} + +#if defined (READLINE_CALLBACKS) +static int +readline_internal_charloop () +{ + int eof = 1; + + while (rl_done == 0) + eof = readline_internal_char (); + return (eof); +} +#endif /* READLINE_CALLBACKS */ + +/* Read a line of input from the global rl_instream, doing output on + the global rl_outstream. + If rl_prompt is non-null, then that is our prompt. */ +static char * +readline_internal () +{ + int eof; + + readline_internal_setup (); + eof = readline_internal_charloop (); + return (readline_internal_teardown (eof)); +} + +void +_rl_init_line_state () +{ + rl_point = rl_end = rl_mark = 0; + the_line = rl_line_buffer; + the_line[0] = 0; +} + +void +_rl_set_the_line () +{ + the_line = rl_line_buffer; +} + +#if defined (READLINE_CALLBACKS) +_rl_keyseq_cxt * +_rl_keyseq_cxt_alloc () +{ + _rl_keyseq_cxt *cxt; + + cxt = (_rl_keyseq_cxt *)xmalloc (sizeof (_rl_keyseq_cxt)); + + cxt->flags = cxt->subseq_arg = cxt->subseq_retval = 0; + + cxt->okey = 0; + cxt->ocxt = _rl_kscxt; + cxt->childval = 42; /* sentinel value */ + + return cxt; +} + +void +_rl_keyseq_cxt_dispose (cxt) + _rl_keyseq_cxt *cxt; +{ + free (cxt); +} + +void +_rl_keyseq_chain_dispose () +{ + _rl_keyseq_cxt *cxt; + + while (_rl_kscxt) + { + cxt = _rl_kscxt; + _rl_kscxt = _rl_kscxt->ocxt; + _rl_keyseq_cxt_dispose (cxt); + } +} +#endif + +static int +_rl_subseq_getchar (key) + int key; +{ + int k; + + if (key == ESC) + RL_SETSTATE(RL_STATE_METANEXT); + RL_SETSTATE(RL_STATE_MOREINPUT); + k = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + if (key == ESC) + RL_UNSETSTATE(RL_STATE_METANEXT); + + return k; +} + +#if defined (READLINE_CALLBACKS) +int +_rl_dispatch_callback (cxt) + _rl_keyseq_cxt *cxt; +{ + int nkey, r; + + /* For now */ +#if 1 + /* The first time this context is used, we want to read input and dispatch + on it. When traversing the chain of contexts back `up', we want to use + the value from the next context down. We're simulating recursion using + a chain of contexts. */ + if ((cxt->flags & KSEQ_DISPATCHED) == 0) + { + nkey = _rl_subseq_getchar (cxt->okey); + r = _rl_dispatch_subseq (nkey, cxt->dmap, cxt->subseq_arg); + cxt->flags |= KSEQ_DISPATCHED; + } + else + r = cxt->childval; +#else + r = _rl_dispatch_subseq (nkey, cxt->dmap, cxt->subseq_arg); +#endif + + /* For now */ + r = _rl_subseq_result (r, cxt->oldmap, cxt->okey, (cxt->flags & KSEQ_SUBSEQ)); + + if (r == 0) /* success! */ + { + _rl_keyseq_chain_dispose (); + RL_UNSETSTATE (RL_STATE_MULTIKEY); + return r; + } + + if (r != -3) /* magic value that says we added to the chain */ + _rl_kscxt = cxt->ocxt; + if (_rl_kscxt) + _rl_kscxt->childval = r; + if (r != -3) + _rl_keyseq_cxt_dispose (cxt); + + return r; +} +#endif /* READLINE_CALLBACKS */ + +/* Do the command associated with KEY in MAP. + If the associated command is really a keymap, then read + another key, and dispatch into that map. */ +int +_rl_dispatch (key, map) + register int key; + Keymap map; +{ + _rl_dispatching_keymap = map; + return _rl_dispatch_subseq (key, map, 0); +} + +int +_rl_dispatch_subseq (key, map, got_subseq) + register int key; + Keymap map; + int got_subseq; +{ + int r, newkey; + char *macro; + rl_command_func_t *func; +#if defined (READLINE_CALLBACKS) + _rl_keyseq_cxt *cxt; +#endif + + if (META_CHAR (key) && _rl_convert_meta_chars_to_ascii) + { + if (map[ESC].type == ISKMAP) + { + if (RL_ISSTATE (RL_STATE_MACRODEF)) + _rl_add_macro_char (ESC); + map = FUNCTION_TO_KEYMAP (map, ESC); + key = UNMETA (key); + rl_key_sequence_length += 2; + return (_rl_dispatch (key, map)); + } + else + rl_ding (); + return 0; + } + + if (RL_ISSTATE (RL_STATE_MACRODEF)) + _rl_add_macro_char (key); + + r = 0; + switch (map[key].type) + { + case ISFUNC: + func = map[key].function; + if (func) + { + /* Special case rl_do_lowercase_version (). */ + if (func == rl_do_lowercase_version) + return (_rl_dispatch (_rl_to_lower (key), map)); + + rl_executing_keymap = map; + + rl_dispatching = 1; + RL_SETSTATE(RL_STATE_DISPATCHING); + (*map[key].function)(rl_numeric_arg * rl_arg_sign, key); + RL_UNSETSTATE(RL_STATE_DISPATCHING); + rl_dispatching = 0; + + /* If we have input pending, then the last command was a prefix + command. Don't change the state of rl_last_func. Otherwise, + remember the last command executed in this variable. */ + if (rl_pending_input == 0 && map[key].function != rl_digit_argument) + rl_last_func = map[key].function; + } + else if (map[ANYOTHERKEY].function) + { + /* OK, there's no function bound in this map, but there is a + shadow function that was overridden when the current keymap + was created. Return -2 to note that. */ + _rl_unget_char (key); + return -2; + } + else if (got_subseq) + { + /* Return -1 to note that we're in a subsequence, but we don't + have a matching key, nor was one overridden. This means + we need to back up the recursion chain and find the last + subsequence that is bound to a function. */ + _rl_unget_char (key); + return -1; + } + else + { +#if defined (READLINE_CALLBACKS) + RL_UNSETSTATE (RL_STATE_MULTIKEY); + _rl_keyseq_chain_dispose (); +#endif + _rl_abort_internal (); + return -1; + } + break; + + case ISKMAP: + if (map[key].function != 0) + { +#if defined (VI_MODE) + /* The only way this test will be true is if a subsequence has been + bound starting with ESC, generally the arrow keys. What we do is + check whether there's input in the queue, which there generally + will be if an arrow key has been pressed, and, if there's not, + just dispatch to (what we assume is) rl_vi_movement_mode right + away. This is essentially an input test with a zero timeout. */ + if (rl_editing_mode == vi_mode && key == ESC && map == vi_insertion_keymap + && _rl_input_queued (0) == 0) + return (_rl_dispatch (ANYOTHERKEY, FUNCTION_TO_KEYMAP (map, key))); +#endif + + rl_key_sequence_length++; + _rl_dispatching_keymap = FUNCTION_TO_KEYMAP (map, key); + + /* Allocate new context here. Use linked contexts (linked through + cxt->ocxt) to simulate recursion */ +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + /* Return 0 only the first time, to indicate success to + _rl_callback_read_char. The rest of the time, we're called + from _rl_dispatch_callback, so we return 3 to indicate + special handling is necessary. */ + r = RL_ISSTATE (RL_STATE_MULTIKEY) ? -3 : 0; + cxt = _rl_keyseq_cxt_alloc (); + + if (got_subseq) + cxt->flags |= KSEQ_SUBSEQ; + cxt->okey = key; + cxt->oldmap = map; + cxt->dmap = _rl_dispatching_keymap; + cxt->subseq_arg = got_subseq || cxt->dmap[ANYOTHERKEY].function; + + RL_SETSTATE (RL_STATE_MULTIKEY); + _rl_kscxt = cxt; + + return r; /* don't indicate immediate success */ + } +#endif + + newkey = _rl_subseq_getchar (key); + if (newkey < 0) + { + _rl_abort_internal (); + return -1; + } + + r = _rl_dispatch_subseq (newkey, _rl_dispatching_keymap, got_subseq || map[ANYOTHERKEY].function); + return _rl_subseq_result (r, map, key, got_subseq); + } + else + { + _rl_abort_internal (); + return -1; + } + break; + + case ISMACR: + if (map[key].function != 0) + { + macro = savestring ((char *)map[key].function); + _rl_with_macro_input (macro); + return 0; + } + break; + } +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode && _rl_keymap == vi_movement_keymap && + key != ANYOTHERKEY && + _rl_vi_textmod_command (key)) + _rl_vi_set_last (key, rl_numeric_arg, rl_arg_sign); +#endif + + return (r); +} + +static int +_rl_subseq_result (r, map, key, got_subseq) + int r; + Keymap map; + int key, got_subseq; +{ + Keymap m; + int type, nt; + rl_command_func_t *func, *nf; + + if (r == -2) + /* We didn't match anything, and the keymap we're indexed into + shadowed a function previously bound to that prefix. Call + the function. The recursive call to _rl_dispatch_subseq has + already taken care of pushing any necessary input back onto + the input queue with _rl_unget_char. */ + { + m = _rl_dispatching_keymap; + type = m[ANYOTHERKEY].type; + func = m[ANYOTHERKEY].function; + if (type == ISFUNC && func == rl_do_lowercase_version) + r = _rl_dispatch (_rl_to_lower (key), map); + else if (type == ISFUNC && func == rl_insert) + { + /* If the function that was shadowed was self-insert, we + somehow need a keymap with map[key].func == self-insert. + Let's use this one. */ + nt = m[key].type; + nf = m[key].function; + + m[key].type = type; + m[key].function = func; + r = _rl_dispatch (key, m); + m[key].type = nt; + m[key].function = nf; + } + else + r = _rl_dispatch (ANYOTHERKEY, m); + } + else if (r && map[ANYOTHERKEY].function) + { + /* We didn't match (r is probably -1), so return something to + tell the caller that it should try ANYOTHERKEY for an + overridden function. */ + _rl_unget_char (key); + _rl_dispatching_keymap = map; + return -2; + } + else if (r && got_subseq) + { + /* OK, back up the chain. */ + _rl_unget_char (key); + _rl_dispatching_keymap = map; + return -1; + } + + return r; +} + +/* **************************************************************** */ +/* */ +/* Initializations */ +/* */ +/* **************************************************************** */ + +/* Initialize readline (and terminal if not already). */ +int +rl_initialize () +{ + /* If we have never been called before, initialize the + terminal and data structures. */ + if (!rl_initialized) + { + RL_SETSTATE(RL_STATE_INITIALIZING); + readline_initialize_everything (); + RL_UNSETSTATE(RL_STATE_INITIALIZING); + rl_initialized++; + RL_SETSTATE(RL_STATE_INITIALIZED); + } + + /* Initalize the current line information. */ + _rl_init_line_state (); + + /* We aren't done yet. We haven't even gotten started yet! */ + rl_done = 0; + RL_UNSETSTATE(RL_STATE_DONE); + + /* Tell the history routines what is going on. */ + _rl_start_using_history (); + + /* Make the display buffer match the state of the line. */ + rl_reset_line_state (); + + /* No such function typed yet. */ + rl_last_func = (rl_command_func_t *)NULL; + + /* Parsing of key-bindings begins in an enabled state. */ + _rl_parsing_conditionalized_out = 0; + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + _rl_vi_initialize_line (); +#endif + + /* Each line starts in insert mode (the default). */ + _rl_set_insert_mode (RL_IM_DEFAULT, 1); + + return 0; +} + +#if 0 +#if defined (__EMX__) +static void +_emx_build_environ () +{ + TIB *tibp; + PIB *pibp; + char *t, **tp; + int c; + + DosGetInfoBlocks (&tibp, &pibp); + t = pibp->pib_pchenv; + for (c = 1; *t; c++) + t += strlen (t) + 1; + tp = environ = (char **)xmalloc ((c + 1) * sizeof (char *)); + t = pibp->pib_pchenv; + while (*t) + { + *tp++ = t; + t += strlen (t) + 1; + } + *tp = 0; +} +#endif /* __EMX__ */ +#endif + +/* Initialize the entire state of the world. */ +static void +readline_initialize_everything () +{ +#if 0 +#if defined (__EMX__) + if (environ == 0) + _emx_build_environ (); +#endif +#endif + +#if 0 + /* Find out if we are running in Emacs -- UNUSED. */ + running_in_emacs = sh_get_env_value ("EMACS") != (char *)0; +#endif + + /* Set up input and output if they are not already set up. */ + if (!rl_instream) + rl_instream = stdin; + + if (!rl_outstream) + rl_outstream = stdout; + + /* Bind _rl_in_stream and _rl_out_stream immediately. These values + may change, but they may also be used before readline_internal () + is called. */ + _rl_in_stream = rl_instream; + _rl_out_stream = rl_outstream; + + /* Allocate data structures. */ + if (rl_line_buffer == 0) + rl_line_buffer = (char *)xmalloc (rl_line_buffer_len = DEFAULT_BUFFER_SIZE); + + /* Initialize the terminal interface. */ + if (rl_terminal_name == 0) + rl_terminal_name = sh_get_env_value ("TERM"); + _rl_init_terminal_io (rl_terminal_name); + + /* Bind tty characters to readline functions. */ + readline_default_bindings (); + + /* Initialize the function names. */ + rl_initialize_funmap (); + + /* Decide whether we should automatically go into eight-bit mode. */ + _rl_init_eightbit (); + + /* Read in the init file. */ + rl_read_init_file ((char *)NULL); + + /* XXX */ + if (_rl_horizontal_scroll_mode && _rl_term_autowrap) + { + _rl_screenwidth--; + _rl_screenchars -= _rl_screenheight; + } + + /* Override the effect of any `set keymap' assignments in the + inputrc file. */ + rl_set_keymap_from_edit_mode (); + + /* Try to bind a common arrow key prefix, if not already bound. */ + bind_arrow_keys (); + + /* Enable the meta key, if this terminal has one. */ + if (_rl_enable_meta) + _rl_enable_meta_key (); + + /* If the completion parser's default word break characters haven't + been set yet, then do so now. */ + if (rl_completer_word_break_characters == (char *)NULL) + rl_completer_word_break_characters = (char *)rl_basic_word_break_characters; +} + +/* If this system allows us to look at the values of the regular + input editing characters, then bind them to their readline + equivalents, iff the characters are not bound to keymaps. */ +static void +readline_default_bindings () +{ + if (_rl_bind_stty_chars) + rl_tty_set_default_bindings (_rl_keymap); +} + +/* Reset the default bindings for the terminal special characters we're + interested in back to rl_insert and read the new ones. */ +static void +reset_default_bindings () +{ + if (_rl_bind_stty_chars) + { + rl_tty_unset_default_bindings (_rl_keymap); + rl_tty_set_default_bindings (_rl_keymap); + } +} + +/* Bind some common arrow key sequences in MAP. */ +static void +bind_arrow_keys_internal (map) + Keymap map; +{ + Keymap xkeymap; + + xkeymap = _rl_keymap; + _rl_keymap = map; + +#if defined (__MSDOS__) + rl_bind_keyseq_if_unbound ("\033[0A", rl_get_previous_history); + rl_bind_keyseq_if_unbound ("\033[0B", rl_backward_char); + rl_bind_keyseq_if_unbound ("\033[0C", rl_forward_char); + rl_bind_keyseq_if_unbound ("\033[0D", rl_get_next_history); +#endif + + rl_bind_keyseq_if_unbound ("\033[A", rl_get_previous_history); + rl_bind_keyseq_if_unbound ("\033[B", rl_get_next_history); + rl_bind_keyseq_if_unbound ("\033[C", rl_forward_char); + rl_bind_keyseq_if_unbound ("\033[D", rl_backward_char); + rl_bind_keyseq_if_unbound ("\033[H", rl_beg_of_line); + rl_bind_keyseq_if_unbound ("\033[F", rl_end_of_line); + + rl_bind_keyseq_if_unbound ("\033OA", rl_get_previous_history); + rl_bind_keyseq_if_unbound ("\033OB", rl_get_next_history); + rl_bind_keyseq_if_unbound ("\033OC", rl_forward_char); + rl_bind_keyseq_if_unbound ("\033OD", rl_backward_char); + rl_bind_keyseq_if_unbound ("\033OH", rl_beg_of_line); + rl_bind_keyseq_if_unbound ("\033OF", rl_end_of_line); + +#if defined (__MINGW32__) + rl_bind_keyseq_if_unbound ("\340H", rl_get_previous_history); + rl_bind_keyseq_if_unbound ("\340P", rl_get_next_history); + rl_bind_keyseq_if_unbound ("\340M", rl_forward_char); + rl_bind_keyseq_if_unbound ("\340K", rl_backward_char); +#endif + + _rl_keymap = xkeymap; +} + +/* Try and bind the common arrow key prefixes after giving termcap and + the inputrc file a chance to bind them and create `real' keymaps + for the arrow key prefix. */ +static void +bind_arrow_keys () +{ + bind_arrow_keys_internal (emacs_standard_keymap); + +#if defined (VI_MODE) + bind_arrow_keys_internal (vi_movement_keymap); + bind_arrow_keys_internal (vi_insertion_keymap); +#endif +} + +/* **************************************************************** */ +/* */ +/* Saving and Restoring Readline's state */ +/* */ +/* **************************************************************** */ + +int +rl_save_state (sp) + struct readline_state *sp; +{ + if (sp == 0) + return -1; + + sp->point = rl_point; + sp->end = rl_end; + sp->mark = rl_mark; + sp->buffer = rl_line_buffer; + sp->buflen = rl_line_buffer_len; + sp->ul = rl_undo_list; + sp->prompt = rl_prompt; + + sp->rlstate = rl_readline_state; + sp->done = rl_done; + sp->kmap = _rl_keymap; + + sp->lastfunc = rl_last_func; + sp->insmode = rl_insert_mode; + sp->edmode = rl_editing_mode; + sp->kseqlen = rl_key_sequence_length; + sp->inf = rl_instream; + sp->outf = rl_outstream; + sp->pendingin = rl_pending_input; + sp->macro = rl_executing_macro; + + sp->catchsigs = rl_catch_signals; + sp->catchsigwinch = rl_catch_sigwinch; + + return (0); +} + +int +rl_restore_state (sp) + struct readline_state *sp; +{ + if (sp == 0) + return -1; + + rl_point = sp->point; + rl_end = sp->end; + rl_mark = sp->mark; + the_line = rl_line_buffer = sp->buffer; + rl_line_buffer_len = sp->buflen; + rl_undo_list = sp->ul; + rl_prompt = sp->prompt; + + rl_readline_state = sp->rlstate; + rl_done = sp->done; + _rl_keymap = sp->kmap; + + rl_last_func = sp->lastfunc; + rl_insert_mode = sp->insmode; + rl_editing_mode = sp->edmode; + rl_key_sequence_length = sp->kseqlen; + rl_instream = sp->inf; + rl_outstream = sp->outf; + rl_pending_input = sp->pendingin; + rl_executing_macro = sp->macro; + + rl_catch_signals = sp->catchsigs; + rl_catch_sigwinch = sp->catchsigwinch; + + return (0); +} diff --git a/external/gpl3/gdb/dist/readline/readline.h b/external/gpl3/gdb/dist/readline/readline.h new file mode 100644 index 000000000000..fade6d41d2f9 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/readline.h @@ -0,0 +1,849 @@ +/* Readline.h -- the names of functions callable from within readline. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_READLINE_H_) +#define _READLINE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (READLINE_LIBRARY) +# include "rlstdc.h" +# include "rltypedefs.h" +# include "keymaps.h" +# include "tilde.h" +#else +# include +# include +# include +# include +#endif + +/* Hex-encoded Readline version number. */ +#define RL_READLINE_VERSION 0x0501 /* Readline 5.1 */ +#define RL_VERSION_MAJOR 5 +#define RL_VERSION_MINOR 1 + +/* Readline data structures. */ + +/* Maintaining the state of undo. We remember individual deletes and inserts + on a chain of things to do. */ + +/* The actions that undo knows how to undo. Notice that UNDO_DELETE means + to insert some text, and UNDO_INSERT means to delete some text. I.e., + the code tells undo what to undo, not how to undo it. */ +enum undo_code { UNDO_DELETE, UNDO_INSERT, UNDO_BEGIN, UNDO_END }; + +/* What an element of THE_UNDO_LIST looks like. */ +typedef struct undo_list { + struct undo_list *next; + int start, end; /* Where the change took place. */ + char *text; /* The text to insert, if undoing a delete. */ + enum undo_code what; /* Delete, Insert, Begin, End. */ +} UNDO_LIST; + +/* The current undo list for RL_LINE_BUFFER. */ +extern UNDO_LIST *rl_undo_list; + +/* The data structure for mapping textual names to code addresses. */ +typedef struct _funmap { + const char *name; + rl_command_func_t *function; +} FUNMAP; + +extern FUNMAP **funmap; + +/* **************************************************************** */ +/* */ +/* Functions available to bind to key sequences */ +/* */ +/* **************************************************************** */ + +/* Bindable commands for numeric arguments. */ +extern int rl_digit_argument PARAMS((int, int)); +extern int rl_universal_argument PARAMS((int, int)); + +/* Bindable commands for moving the cursor. */ +extern int rl_forward_byte PARAMS((int, int)); +extern int rl_forward_char PARAMS((int, int)); +extern int rl_forward PARAMS((int, int)); +extern int rl_backward_byte PARAMS((int, int)); +extern int rl_backward_char PARAMS((int, int)); +extern int rl_backward PARAMS((int, int)); +extern int rl_beg_of_line PARAMS((int, int)); +extern int rl_end_of_line PARAMS((int, int)); +extern int rl_forward_word PARAMS((int, int)); +extern int rl_backward_word PARAMS((int, int)); +extern int rl_refresh_line PARAMS((int, int)); +extern int rl_clear_screen PARAMS((int, int)); +extern int rl_arrow_keys PARAMS((int, int)); + +/* Bindable commands for inserting and deleting text. */ +extern int rl_insert PARAMS((int, int)); +extern int rl_quoted_insert PARAMS((int, int)); +extern int rl_tab_insert PARAMS((int, int)); +extern int rl_newline PARAMS((int, int)); +extern int rl_do_lowercase_version PARAMS((int, int)); +extern int rl_rubout PARAMS((int, int)); +extern int rl_delete PARAMS((int, int)); +extern int rl_rubout_or_delete PARAMS((int, int)); +extern int rl_delete_horizontal_space PARAMS((int, int)); +extern int rl_delete_or_show_completions PARAMS((int, int)); +extern int rl_insert_comment PARAMS((int, int)); + +/* Bindable commands for changing case. */ +extern int rl_upcase_word PARAMS((int, int)); +extern int rl_downcase_word PARAMS((int, int)); +extern int rl_capitalize_word PARAMS((int, int)); + +/* Bindable commands for transposing characters and words. */ +extern int rl_transpose_words PARAMS((int, int)); +extern int rl_transpose_chars PARAMS((int, int)); + +/* Bindable commands for searching within a line. */ +extern int rl_char_search PARAMS((int, int)); +extern int rl_backward_char_search PARAMS((int, int)); + +/* Bindable commands for readline's interface to the command history. */ +extern int rl_beginning_of_history PARAMS((int, int)); +extern int rl_end_of_history PARAMS((int, int)); +extern int rl_get_next_history PARAMS((int, int)); +extern int rl_get_previous_history PARAMS((int, int)); + +/* Bindable commands for managing the mark and region. */ +extern int rl_set_mark PARAMS((int, int)); +extern int rl_exchange_point_and_mark PARAMS((int, int)); + +/* Bindable commands to set the editing mode (emacs or vi). */ +extern int rl_vi_editing_mode PARAMS((int, int)); +extern int rl_emacs_editing_mode PARAMS((int, int)); + +/* Bindable commands to change the insert mode (insert or overwrite) */ +extern int rl_overwrite_mode PARAMS((int, int)); + +/* Bindable commands for managing key bindings. */ +extern int rl_re_read_init_file PARAMS((int, int)); +extern int rl_dump_functions PARAMS((int, int)); +extern int rl_dump_macros PARAMS((int, int)); +extern int rl_dump_variables PARAMS((int, int)); + +/* Bindable commands for word completion. */ +extern int rl_complete PARAMS((int, int)); +extern int rl_possible_completions PARAMS((int, int)); +extern int rl_insert_completions PARAMS((int, int)); +extern int rl_menu_complete PARAMS((int, int)); + +/* Bindable commands for killing and yanking text, and managing the kill ring. */ +extern int rl_kill_word PARAMS((int, int)); +extern int rl_backward_kill_word PARAMS((int, int)); +extern int rl_kill_line PARAMS((int, int)); +extern int rl_backward_kill_line PARAMS((int, int)); +extern int rl_kill_full_line PARAMS((int, int)); +extern int rl_unix_word_rubout PARAMS((int, int)); +extern int rl_unix_filename_rubout PARAMS((int, int)); +extern int rl_unix_line_discard PARAMS((int, int)); +extern int rl_copy_region_to_kill PARAMS((int, int)); +extern int rl_kill_region PARAMS((int, int)); +extern int rl_copy_forward_word PARAMS((int, int)); +extern int rl_copy_backward_word PARAMS((int, int)); +extern int rl_yank PARAMS((int, int)); +extern int rl_yank_pop PARAMS((int, int)); +extern int rl_yank_nth_arg PARAMS((int, int)); +extern int rl_yank_last_arg PARAMS((int, int)); +/* Not available unless __CYGWIN__ is defined. */ +#ifdef __CYGWIN__ +extern int rl_paste_from_clipboard PARAMS((int, int)); +#endif + +/* Bindable commands for incremental searching. */ +extern int rl_reverse_search_history PARAMS((int, int)); +extern int rl_forward_search_history PARAMS((int, int)); + +/* Bindable keyboard macro commands. */ +extern int rl_start_kbd_macro PARAMS((int, int)); +extern int rl_end_kbd_macro PARAMS((int, int)); +extern int rl_call_last_kbd_macro PARAMS((int, int)); + +/* Bindable undo commands. */ +extern int rl_revert_line PARAMS((int, int)); +extern int rl_undo_command PARAMS((int, int)); + +/* Bindable tilde expansion commands. */ +extern int rl_tilde_expand PARAMS((int, int)); + +/* Bindable terminal control commands. */ +extern int rl_restart_output PARAMS((int, int)); +extern int rl_stop_output PARAMS((int, int)); + +/* Miscellaneous bindable commands. */ +extern int rl_abort PARAMS((int, int)); +extern int rl_tty_status PARAMS((int, int)); + +/* Bindable commands for incremental and non-incremental history searching. */ +extern int rl_history_search_forward PARAMS((int, int)); +extern int rl_history_search_backward PARAMS((int, int)); +extern int rl_noninc_forward_search PARAMS((int, int)); +extern int rl_noninc_reverse_search PARAMS((int, int)); +extern int rl_noninc_forward_search_again PARAMS((int, int)); +extern int rl_noninc_reverse_search_again PARAMS((int, int)); + +/* Bindable command used when inserting a matching close character. */ +extern int rl_insert_close PARAMS((int, int)); + +/* Not available unless READLINE_CALLBACKS is defined. */ +extern void rl_callback_handler_install PARAMS((const char *, rl_vcpfunc_t *)); +extern void rl_callback_read_char PARAMS((void)); +extern void rl_callback_handler_remove PARAMS((void)); + +/* Things for vi mode. Not available unless readline is compiled -DVI_MODE. */ +/* VI-mode bindable commands. */ +extern int rl_vi_redo PARAMS((int, int)); +extern int rl_vi_undo PARAMS((int, int)); +extern int rl_vi_yank_arg PARAMS((int, int)); +extern int rl_vi_fetch_history PARAMS((int, int)); +extern int rl_vi_search_again PARAMS((int, int)); +extern int rl_vi_search PARAMS((int, int)); +extern int rl_vi_complete PARAMS((int, int)); +extern int rl_vi_tilde_expand PARAMS((int, int)); +extern int rl_vi_prev_word PARAMS((int, int)); +extern int rl_vi_next_word PARAMS((int, int)); +extern int rl_vi_end_word PARAMS((int, int)); +extern int rl_vi_insert_beg PARAMS((int, int)); +extern int rl_vi_append_mode PARAMS((int, int)); +extern int rl_vi_append_eol PARAMS((int, int)); +extern int rl_vi_eof_maybe PARAMS((int, int)); +extern int rl_vi_insertion_mode PARAMS((int, int)); +extern int rl_vi_movement_mode PARAMS((int, int)); +extern int rl_vi_arg_digit PARAMS((int, int)); +extern int rl_vi_change_case PARAMS((int, int)); +extern int rl_vi_put PARAMS((int, int)); +extern int rl_vi_column PARAMS((int, int)); +extern int rl_vi_delete_to PARAMS((int, int)); +extern int rl_vi_change_to PARAMS((int, int)); +extern int rl_vi_yank_to PARAMS((int, int)); +extern int rl_vi_rubout PARAMS((int, int)); +extern int rl_vi_delete PARAMS((int, int)); +extern int rl_vi_back_to_indent PARAMS((int, int)); +extern int rl_vi_first_print PARAMS((int, int)); +extern int rl_vi_char_search PARAMS((int, int)); +extern int rl_vi_match PARAMS((int, int)); +extern int rl_vi_change_char PARAMS((int, int)); +extern int rl_vi_subst PARAMS((int, int)); +extern int rl_vi_overstrike PARAMS((int, int)); +extern int rl_vi_overstrike_delete PARAMS((int, int)); +extern int rl_vi_replace PARAMS((int, int)); +extern int rl_vi_set_mark PARAMS((int, int)); +extern int rl_vi_goto_mark PARAMS((int, int)); + +/* VI-mode utility functions. */ +extern int rl_vi_check PARAMS((void)); +extern int rl_vi_domove PARAMS((int, int *)); +extern int rl_vi_bracktype PARAMS((int)); + +extern void rl_vi_start_inserting PARAMS((int, int, int)); + +/* VI-mode pseudo-bindable commands, used as utility functions. */ +extern int rl_vi_fWord PARAMS((int, int)); +extern int rl_vi_bWord PARAMS((int, int)); +extern int rl_vi_eWord PARAMS((int, int)); +extern int rl_vi_fword PARAMS((int, int)); +extern int rl_vi_bword PARAMS((int, int)); +extern int rl_vi_eword PARAMS((int, int)); + +/* **************************************************************** */ +/* */ +/* Well Published Functions */ +/* */ +/* **************************************************************** */ + +/* Readline functions. */ +/* Read a line of input. Prompt with PROMPT. A NULL PROMPT means none. */ +extern char *readline PARAMS((const char *)); + +extern int rl_set_prompt PARAMS((const char *)); +extern int rl_expand_prompt PARAMS((char *)); + +extern int rl_initialize PARAMS((void)); + +/* Undocumented; unused by readline */ +extern int rl_discard_argument PARAMS((void)); + +/* Utility functions to bind keys to readline commands. */ +extern int rl_add_defun PARAMS((const char *, rl_command_func_t *, int)); +extern int rl_bind_key PARAMS((int, rl_command_func_t *)); +extern int rl_bind_key_in_map PARAMS((int, rl_command_func_t *, Keymap)); +extern int rl_unbind_key PARAMS((int)); +extern int rl_unbind_key_in_map PARAMS((int, Keymap)); +extern int rl_bind_key_if_unbound PARAMS((int, rl_command_func_t *)); +extern int rl_bind_key_if_unbound_in_map PARAMS((int, rl_command_func_t *, Keymap)); +extern int rl_unbind_function_in_map PARAMS((rl_command_func_t *, Keymap)); +extern int rl_unbind_command_in_map PARAMS((const char *, Keymap)); +extern int rl_bind_keyseq PARAMS((const char *, rl_command_func_t *)); +extern int rl_bind_keyseq_in_map PARAMS((const char *, rl_command_func_t *, Keymap)); +extern int rl_bind_keyseq_if_unbound PARAMS((const char *, rl_command_func_t *)); +extern int rl_bind_keyseq_if_unbound_in_map PARAMS((const char *, rl_command_func_t *, Keymap)); +extern int rl_generic_bind PARAMS((int, const char *, char *, Keymap)); + +extern char *rl_variable_value PARAMS((const char *)); +extern int rl_variable_bind PARAMS((const char *, const char *)); + +/* Backwards compatibility, use rl_bind_keyseq_in_map instead. */ +extern int rl_set_key PARAMS((const char *, rl_command_func_t *, Keymap)); + +/* Backwards compatibility, use rl_generic_bind instead. */ +extern int rl_macro_bind PARAMS((const char *, const char *, Keymap)); + +/* Undocumented in the texinfo manual; not really useful to programs. */ +extern int rl_translate_keyseq PARAMS((const char *, char *, int *)); +extern char *rl_untranslate_keyseq PARAMS((int)); + +extern rl_command_func_t *rl_named_function PARAMS((const char *)); +extern rl_command_func_t *rl_function_of_keyseq PARAMS((const char *, Keymap, int *)); + +extern void rl_list_funmap_names PARAMS((void)); +extern char **rl_invoking_keyseqs_in_map PARAMS((rl_command_func_t *, Keymap)); +extern char **rl_invoking_keyseqs PARAMS((rl_command_func_t *)); + +extern void rl_function_dumper PARAMS((int)); +extern void rl_macro_dumper PARAMS((int)); +extern void rl_variable_dumper PARAMS((int)); + +extern int rl_read_init_file PARAMS((const char *)); +extern int rl_parse_and_bind PARAMS((char *)); + +/* Functions for manipulating keymaps. */ +extern Keymap rl_make_bare_keymap PARAMS((void)); +extern Keymap rl_copy_keymap PARAMS((Keymap)); +extern Keymap rl_make_keymap PARAMS((void)); +extern void rl_discard_keymap PARAMS((Keymap)); + +extern Keymap rl_get_keymap_by_name PARAMS((const char *)); +extern char *rl_get_keymap_name PARAMS((Keymap)); +extern void rl_set_keymap PARAMS((Keymap)); +extern Keymap rl_get_keymap PARAMS((void)); +/* Undocumented; used internally only. */ +extern void rl_set_keymap_from_edit_mode PARAMS((void)); +extern char *rl_get_keymap_name_from_edit_mode PARAMS((void)); + +/* Functions for manipulating the funmap, which maps command names to functions. */ +extern int rl_add_funmap_entry PARAMS((const char *, rl_command_func_t *)); +extern const char **rl_funmap_names PARAMS((void)); +/* Undocumented, only used internally -- there is only one funmap, and this + function may be called only once. */ +extern void rl_initialize_funmap PARAMS((void)); + +/* Utility functions for managing keyboard macros. */ +extern void rl_push_macro_input PARAMS((char *)); + +/* Functions for undoing, from undo.c */ +extern void rl_add_undo PARAMS((enum undo_code, int, int, char *)); +extern void rl_free_undo_list PARAMS((void)); +extern int rl_do_undo PARAMS((void)); +extern int rl_begin_undo_group PARAMS((void)); +extern int rl_end_undo_group PARAMS((void)); +extern int rl_modifying PARAMS((int, int)); + +/* Functions for redisplay. */ +extern void rl_redisplay PARAMS((void)); +extern int rl_on_new_line PARAMS((void)); +extern int rl_on_new_line_with_prompt PARAMS((void)); +extern int rl_forced_update_display PARAMS((void)); +extern int rl_clear_message PARAMS((void)); +extern int rl_reset_line_state PARAMS((void)); +extern int rl_crlf PARAMS((void)); + +#if defined (USE_VARARGS) && defined (PREFER_STDARG) +extern int rl_message (const char *, ...) __attribute__((__format__ (printf, 1, 2))); +#else +extern int rl_message (); +#endif + +extern int rl_show_char PARAMS((int)); + +/* Undocumented in texinfo manual. */ +extern int rl_character_len PARAMS((int, int)); + +/* Save and restore internal prompt redisplay information. */ +extern void rl_save_prompt PARAMS((void)); +extern void rl_restore_prompt PARAMS((void)); + +/* Modifying text. */ +extern void rl_replace_line PARAMS((const char *, int)); +extern int rl_insert_text PARAMS((const char *)); +extern int rl_delete_text PARAMS((int, int)); +extern int rl_kill_text PARAMS((int, int)); +extern char *rl_copy_text PARAMS((int, int)); + +/* Terminal and tty mode management. */ +extern void rl_prep_terminal PARAMS((int)); +extern void rl_deprep_terminal PARAMS((void)); +extern void rl_tty_set_default_bindings PARAMS((Keymap)); +extern void rl_tty_unset_default_bindings PARAMS((Keymap)); + +extern int rl_reset_terminal PARAMS((const char *)); +extern void rl_resize_terminal PARAMS((void)); +extern void rl_set_screen_size PARAMS((int, int)); +extern void rl_get_screen_size PARAMS((int *, int *)); +extern void rl_reset_screen_size PARAMS((void)); + +extern char *rl_get_termcap PARAMS((const char *)); + +/* Functions for character input. */ +extern int rl_stuff_char PARAMS((int)); +extern int rl_execute_next PARAMS((int)); +extern int rl_clear_pending_input PARAMS((void)); +extern int rl_read_key PARAMS((void)); +extern int rl_getc PARAMS((FILE *)); +extern int rl_set_keyboard_input_timeout PARAMS((int)); + +/* `Public' utility functions . */ +extern void rl_extend_line_buffer PARAMS((int)); +extern int rl_ding PARAMS((void)); +extern int rl_alphabetic PARAMS((int)); + +/* Readline signal handling, from signals.c */ +extern int rl_set_signals PARAMS((void)); +extern int rl_clear_signals PARAMS((void)); +extern void rl_cleanup_after_signal PARAMS((void)); +extern void rl_reset_after_signal PARAMS((void)); +extern void rl_free_line_state PARAMS((void)); + +extern int rl_set_paren_blink_timeout PARAMS((int)); + +/* Undocumented. */ +extern int rl_maybe_save_line PARAMS((void)); +extern int rl_maybe_unsave_line PARAMS((void)); +extern int rl_maybe_replace_line PARAMS((void)); + +/* Completion functions. */ +extern int rl_complete_internal PARAMS((int)); +extern void rl_display_match_list PARAMS((char **, int, int)); + +extern char **rl_completion_matches PARAMS((const char *, rl_compentry_func_t *)); +extern char *rl_username_completion_function PARAMS((const char *, int)); +extern char *rl_filename_completion_function PARAMS((const char *, int)); + +extern int rl_completion_mode PARAMS((rl_command_func_t *)); + +#if 0 +/* Backwards compatibility (compat.c). These will go away sometime. */ +extern void free_undo_list PARAMS((void)); +extern int maybe_save_line PARAMS((void)); +extern int maybe_unsave_line PARAMS((void)); +extern int maybe_replace_line PARAMS((void)); + +extern int ding PARAMS((void)); +extern int alphabetic PARAMS((int)); +extern int crlf PARAMS((void)); + +extern char **completion_matches PARAMS((char *, rl_compentry_func_t *)); +extern char *username_completion_function PARAMS((const char *, int)); +extern char *filename_completion_function PARAMS((const char *, int)); +#endif + +/* **************************************************************** */ +/* */ +/* Well Published Variables */ +/* */ +/* **************************************************************** */ + +/* The version of this incarnation of the readline library. */ +extern const char *rl_library_version; /* e.g., "4.2" */ +extern int rl_readline_version; /* e.g., 0x0402 */ + +/* True if this is real GNU readline. */ +extern int rl_gnu_readline_p; + +/* Flags word encapsulating the current readline state. */ +extern int rl_readline_state; + +/* Says which editing mode readline is currently using. 1 means emacs mode; + 0 means vi mode. */ +extern int rl_editing_mode; + +/* Insert or overwrite mode for emacs mode. 1 means insert mode; 0 means + overwrite mode. Reset to insert mode on each input line. */ +extern int rl_insert_mode; + +/* The name of the calling program. You should initialize this to + whatever was in argv[0]. It is used when parsing conditionals. */ +extern const char *rl_readline_name; + +/* The prompt readline uses. This is set from the argument to + readline (), and should not be assigned to directly. */ +extern char *rl_prompt; + +/* The line buffer that is in use. */ +extern char *rl_line_buffer; + +/* The location of point, and end. */ +extern int rl_point; +extern int rl_end; + +/* The mark, or saved cursor position. */ +extern int rl_mark; + +/* Flag to indicate that readline has finished with the current input + line and should return it. */ +extern int rl_done; + +/* If set to a character value, that will be the next keystroke read. */ +extern int rl_pending_input; + +/* Non-zero if we called this function from _rl_dispatch(). It's present + so functions can find out whether they were called from a key binding + or directly from an application. */ +extern int rl_dispatching; + +/* Non-zero if the user typed a numeric argument before executing the + current function. */ +extern int rl_explicit_arg; + +/* The current value of the numeric argument specified by the user. */ +extern int rl_numeric_arg; + +/* The address of the last command function Readline executed. */ +extern rl_command_func_t *rl_last_func; + +/* The name of the terminal to use. */ +extern const char *rl_terminal_name; + +/* The input and output streams. */ +extern FILE *rl_instream; +extern FILE *rl_outstream; + +/* If non-zero, Readline gives values of LINES and COLUMNS from the environment + greater precedence than values fetched from the kernel when computing the + screen dimensions. */ +extern int rl_prefer_env_winsize; + +/* If non-zero, then this is the address of a function to call just + before readline_internal () prints the first prompt. */ +extern rl_hook_func_t *rl_startup_hook; + +/* If non-zero, this is the address of a function to call just before + readline_internal_setup () returns and readline_internal starts + reading input characters. */ +extern rl_hook_func_t *rl_pre_input_hook; + +/* The address of a function to call periodically while Readline is + awaiting character input, or NULL, for no event handling. */ +extern rl_hook_func_t *rl_event_hook; + +/* The address of the function to call to fetch a character from the current + Readline input stream */ +extern rl_getc_func_t *rl_getc_function; + +extern rl_voidfunc_t *rl_redisplay_function; + +extern rl_vintfunc_t *rl_prep_term_function; +extern rl_voidfunc_t *rl_deprep_term_function; + +/* Dispatch variables. */ +extern Keymap rl_executing_keymap; +extern Keymap rl_binding_keymap; + +/* Display variables. */ +/* If non-zero, readline will erase the entire line, including any prompt, + if the only thing typed on an otherwise-blank line is something bound to + rl_newline. */ +extern int rl_erase_empty_line; + +/* If non-zero, the application has already printed the prompt (rl_prompt) + before calling readline, so readline should not output it the first time + redisplay is done. */ +extern int rl_already_prompted; + +/* A non-zero value means to read only this many characters rather than + up to a character bound to accept-line. */ +extern int rl_num_chars_to_read; + +/* The text of a currently-executing keyboard macro. */ +extern char *rl_executing_macro; + +/* Variables to control readline signal handling. */ +/* If non-zero, readline will install its own signal handlers for + SIGINT, SIGTERM, SIGQUIT, SIGALRM, SIGTSTP, SIGTTIN, and SIGTTOU. */ +extern int rl_catch_signals; + +/* If non-zero, readline will install a signal handler for SIGWINCH + that also attempts to call any calling application's SIGWINCH signal + handler. Note that the terminal is not cleaned up before the + application's signal handler is called; use rl_cleanup_after_signal() + to do that. */ +extern int rl_catch_sigwinch; + +/* Completion variables. */ +/* Pointer to the generator function for completion_matches (). + NULL means to use rl_filename_completion_function (), the default + filename completer. */ +extern rl_compentry_func_t *rl_completion_entry_function; + +/* If rl_ignore_some_completions_function is non-NULL it is the address + of a function to call after all of the possible matches have been + generated, but before the actual completion is done to the input line. + The function is called with one argument; a NULL terminated array + of (char *). If your function removes any of the elements, they + must be free()'ed. */ +extern rl_compignore_func_t *rl_ignore_some_completions_function; + +/* Pointer to alternative function to create matches. + Function is called with TEXT, START, and END. + START and END are indices in RL_LINE_BUFFER saying what the boundaries + of TEXT are. + If this function exists and returns NULL then call the value of + rl_completion_entry_function to try to match, otherwise use the + array of strings returned. */ +extern rl_completion_func_t *rl_attempted_completion_function; + +/* The basic list of characters that signal a break between words for the + completer routine. The initial contents of this variable is what + breaks words in the shell, i.e. "n\"\\'`@$>". */ +extern const char *rl_basic_word_break_characters; + +/* The list of characters that signal a break between words for + rl_complete_internal. The default list is the contents of + rl_basic_word_break_characters. */ +extern /*const*/ char *rl_completer_word_break_characters; + +/* Hook function to allow an application to set the completion word + break characters before readline breaks up the line. Allows + position-dependent word break characters. */ +extern rl_cpvfunc_t *rl_completion_word_break_hook; + +/* List of characters which can be used to quote a substring of the line. + Completion occurs on the entire substring, and within the substring + rl_completer_word_break_characters are treated as any other character, + unless they also appear within this list. */ +extern const char *rl_completer_quote_characters; + +/* List of quote characters which cause a word break. */ +extern const char *rl_basic_quote_characters; + +/* List of characters that need to be quoted in filenames by the completer. */ +extern const char *rl_filename_quote_characters; + +/* List of characters that are word break characters, but should be left + in TEXT when it is passed to the completion function. The shell uses + this to help determine what kind of completing to do. */ +extern const char *rl_special_prefixes; + +/* If non-zero, then this is the address of a function to call when + completing on a directory name. The function is called with + the address of a string (the current directory name) as an arg. It + changes what is displayed when the possible completions are printed + or inserted. */ +extern rl_icppfunc_t *rl_directory_completion_hook; + +/* If non-zero, this is the address of a function to call when completing + a directory name. This function takes the address of the directory name + to be modified as an argument. Unlike rl_directory_completion_hook, it + only modifies the directory name used in opendir(2), not what is displayed + when the possible completions are printed or inserted. It is called + before rl_directory_completion_hook. I'm not happy with how this works + yet, so it's undocumented. */ +extern rl_icppfunc_t *rl_directory_rewrite_hook; + +/* Backwards compatibility with previous versions of readline. */ +#define rl_symbolic_link_hook rl_directory_completion_hook + +/* If non-zero, then this is the address of a function to call when + completing a word would normally display the list of possible matches. + This function is called instead of actually doing the display. + It takes three arguments: (char **matches, int num_matches, int max_length) + where MATCHES is the array of strings that matched, NUM_MATCHES is the + number of strings in that array, and MAX_LENGTH is the length of the + longest string in that array. */ +extern rl_compdisp_func_t *rl_completion_display_matches_hook; + +/* Non-zero means that the results of the matches are to be treated + as filenames. This is ALWAYS zero on entry, and can only be changed + within a completion entry finder function. */ +extern int rl_filename_completion_desired; + +/* Non-zero means that the results of the matches are to be quoted using + double quotes (or an application-specific quoting mechanism) if the + filename contains any characters in rl_word_break_chars. This is + ALWAYS non-zero on entry, and can only be changed within a completion + entry finder function. */ +extern int rl_filename_quoting_desired; + +/* Set to a function to quote a filename in an application-specific fashion. + Called with the text to quote, the type of match found (single or multiple) + and a pointer to the quoting character to be used, which the function can + reset if desired. */ +extern rl_quote_func_t *rl_filename_quoting_function; + +/* Function to call to remove quoting characters from a filename. Called + before completion is attempted, so the embedded quotes do not interfere + with matching names in the file system. */ +extern rl_dequote_func_t *rl_filename_dequoting_function; + +/* Function to call to decide whether or not a word break character is + quoted. If a character is quoted, it does not break words for the + completer. */ +extern rl_linebuf_func_t *rl_char_is_quoted_p; + +/* Non-zero means to suppress normal filename completion after the + user-specified completion function has been called. */ +extern int rl_attempted_completion_over; + +/* Set to a character describing the type of completion being attempted by + rl_complete_internal; available for use by application completion + functions. */ +extern int rl_completion_type; + +/* Up to this many items will be displayed in response to a + possible-completions call. After that, we ask the user if she + is sure she wants to see them all. The default value is 100. */ +extern int rl_completion_query_items; + +/* Character appended to completed words when at the end of the line. The + default is a space. Nothing is added if this is '\0'. */ +extern int rl_completion_append_character; + +/* If set to non-zero by an application completion function, + rl_completion_append_character will not be appended. */ +extern int rl_completion_suppress_append; + +/* Set to any quote character readline thinks it finds before any application + completion function is called. */ +extern int rl_completion_quote_character; + +/* Set to a non-zero value if readline found quoting anywhere in the word to + be completed; set before any application completion function is called. */ +extern int rl_completion_found_quote; + +/* If non-zero, the completion functions don't append any closing quote. + This is set to 0 by rl_complete_internal and may be changed by an + application-specific completion function. */ +extern int rl_completion_suppress_quote; + +/* If non-zero, a slash will be appended to completed filenames that are + symbolic links to directory names, subject to the value of the + mark-directories variable (which is user-settable). This exists so + that application completion functions can override the user's preference + (set via the mark-symlinked-directories variable) if appropriate. + It's set to the value of _rl_complete_mark_symlink_dirs in + rl_complete_internal before any application-specific completion + function is called, so without that function doing anything, the user's + preferences are honored. */ +extern int rl_completion_mark_symlink_dirs; + +/* If non-zero, then disallow duplicates in the matches. */ +extern int rl_ignore_completion_duplicates; + +/* If this is non-zero, completion is (temporarily) inhibited, and the + completion character will be inserted as any other. */ +extern int rl_inhibit_completion; + +/* Definitions available for use by readline clients. */ +#define RL_PROMPT_START_IGNORE '\001' +#define RL_PROMPT_END_IGNORE '\002' + +/* Possible values for do_replace argument to rl_filename_quoting_function, + called by rl_complete_internal. */ +#define NO_MATCH 0 +#define SINGLE_MATCH 1 +#define MULT_MATCH 2 + +/* Possible state values for rl_readline_state */ +#define RL_STATE_NONE 0x000000 /* no state; before first call */ + +#define RL_STATE_INITIALIZING 0x000001 /* initializing */ +#define RL_STATE_INITIALIZED 0x000002 /* initialization done */ +#define RL_STATE_TERMPREPPED 0x000004 /* terminal is prepped */ +#define RL_STATE_READCMD 0x000008 /* reading a command key */ +#define RL_STATE_METANEXT 0x000010 /* reading input after ESC */ +#define RL_STATE_DISPATCHING 0x000020 /* dispatching to a command */ +#define RL_STATE_MOREINPUT 0x000040 /* reading more input in a command function */ +#define RL_STATE_ISEARCH 0x000080 /* doing incremental search */ +#define RL_STATE_NSEARCH 0x000100 /* doing non-inc search */ +#define RL_STATE_SEARCH 0x000200 /* doing a history search */ +#define RL_STATE_NUMERICARG 0x000400 /* reading numeric argument */ +#define RL_STATE_MACROINPUT 0x000800 /* getting input from a macro */ +#define RL_STATE_MACRODEF 0x001000 /* defining keyboard macro */ +#define RL_STATE_OVERWRITE 0x002000 /* overwrite mode */ +#define RL_STATE_COMPLETING 0x004000 /* doing completion */ +#define RL_STATE_SIGHANDLER 0x008000 /* in readline sighandler */ +#define RL_STATE_UNDOING 0x010000 /* doing an undo */ +#define RL_STATE_INPUTPENDING 0x020000 /* rl_execute_next called */ +#define RL_STATE_TTYCSAVED 0x040000 /* tty special chars saved */ +#define RL_STATE_CALLBACK 0x080000 /* using the callback interface */ +#define RL_STATE_VIMOTION 0x100000 /* reading vi motion arg */ +#define RL_STATE_MULTIKEY 0x200000 /* reading multiple-key command */ +#define RL_STATE_VICMDONCE 0x400000 /* entered vi command mode at least once */ + +#define RL_STATE_DONE 0x800000 /* done; accepted line */ + +#define RL_SETSTATE(x) (rl_readline_state |= (x)) +#define RL_UNSETSTATE(x) (rl_readline_state &= ~(x)) +#define RL_ISSTATE(x) (rl_readline_state & (x)) + +struct readline_state { + /* line state */ + int point; + int end; + int mark; + char *buffer; + int buflen; + UNDO_LIST *ul; + char *prompt; + + /* global state */ + int rlstate; + int done; + Keymap kmap; + + /* input state */ + rl_command_func_t *lastfunc; + int insmode; + int edmode; + int kseqlen; + FILE *inf; + FILE *outf; + int pendingin; + char *macro; + + /* signal state */ + int catchsigs; + int catchsigwinch; + + /* search state */ + + /* completion state */ + + /* options state */ + + /* reserved for future expansion, so the struct size doesn't change */ + char reserved[64]; +}; + +extern int rl_save_state PARAMS((struct readline_state *)); +extern int rl_restore_state PARAMS((struct readline_state *)); + +#ifdef __cplusplus +} +#endif + +#endif /* _READLINE_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlconf.h b/external/gpl3/gdb/dist/readline/rlconf.h new file mode 100644 index 000000000000..c651fd8b41f6 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlconf.h @@ -0,0 +1,60 @@ +/* rlconf.h -- readline configuration definitions */ + +/* Copyright (C) 1994 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RLCONF_H_) +#define _RLCONF_H_ + +/* Define this if you want the vi-mode editing available. */ +#define VI_MODE + +/* Define this to get an indication of file type when listing completions. */ +#define VISIBLE_STATS + +/* This definition is needed by readline.c, rltty.c, and signals.c. */ +/* If on, then readline handles signals in a way that doesn't screw. */ +#define HANDLE_SIGNALS + +/* Ugly but working hack for binding prefix meta. */ +#define PREFIX_META_HACK + +/* The final, last-ditch effort file name for an init file. */ +#define DEFAULT_INPUTRC "~/.inputrc" + +/* If defined, expand tabs to spaces. */ +#define DISPLAY_TABS + +/* If defined, use the terminal escape sequence to move the cursor forward + over a character when updating the line rather than rewriting it. */ +/* #define HACK_TERMCAP_MOTION */ + +/* The string inserted by the `insert comment' command. */ +#define RL_COMMENT_BEGIN_DEFAULT "#" + +/* Define this if you want code that allows readline to be used in an + X `callback' style. */ +#define READLINE_CALLBACKS + +/* Define this if you want the cursor to indicate insert or overwrite mode. */ +/* #define CURSOR_MODE */ + +#endif /* _RLCONF_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rldefs.h b/external/gpl3/gdb/dist/readline/rldefs.h new file mode 100644 index 000000000000..0f6c87446ddd --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rldefs.h @@ -0,0 +1,160 @@ +/* rldefs.h -- an attempt to isolate some of the system-specific defines + for readline. This should be included after any files that define + system-specific constants like _POSIX_VERSION or USG. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RLDEFS_H_) +#define _RLDEFS_H_ + +#if defined (HAVE_CONFIG_H) +# include "config.h" +#endif + +#include "rlstdc.h" + +#if defined (_POSIX_VERSION) && !defined (TERMIOS_MISSING) +# define TERMIOS_TTY_DRIVER +#else +# if defined (HAVE_TERMIO_H) +# define TERMIO_TTY_DRIVER +# else +# if !defined (__MINGW32__) +# define NEW_TTY_DRIVER +# else +# define NO_TTY_DRIVER +# endif +# endif +#endif + +/* Posix macro to check file in statbuf for directory-ness. + This requires that be included before this test. */ +#if defined (S_IFDIR) && !defined (S_ISDIR) +# define S_ISDIR(m) (((m)&S_IFMT) == S_IFDIR) +#endif + +/* Decide which flavor of the header file describing the C library + string functions to include and include it. */ + +#if defined (HAVE_STRING_H) +# include +#else /* !HAVE_STRING_H */ +# include +#endif /* !HAVE_STRING_H */ + +#if !defined (strchr) && !defined (__STDC__) +extern char *strchr (), *strrchr (); +#endif /* !strchr && !__STDC__ */ + +#if defined (PREFER_STDARG) +# include +#else +# if defined (PREFER_VARARGS) +# include +# endif +#endif + +#if defined (HAVE_STRCASECMP) +#define _rl_stricmp strcasecmp +#define _rl_strnicmp strncasecmp +#else +extern int _rl_stricmp PARAMS((char *, char *)); +extern int _rl_strnicmp PARAMS((char *, char *, int)); +#endif + +#if defined (HAVE_STRPBRK) && !defined (HAVE_MULTIBYTE) +# define _rl_strpbrk(a,b) strpbrk((a),(b)) +#else +extern char *_rl_strpbrk PARAMS((const char *, const char *)); +#endif + +#if !defined (emacs_mode) +# define no_mode -1 +# define vi_mode 0 +# define emacs_mode 1 +#endif + +#if !defined (RL_IM_INSERT) +# define RL_IM_INSERT 1 +# define RL_IM_OVERWRITE 0 +# +# define RL_IM_DEFAULT RL_IM_INSERT +#endif + +/* If you cast map[key].function to type (Keymap) on a Cray, + the compiler takes the value of map[key].function and + divides it by 4 to convert between pointer types (pointers + to functions and pointers to structs are different sizes). + This is not what is wanted. */ +#if defined (CRAY) +# define FUNCTION_TO_KEYMAP(map, key) (Keymap)((int)map[key].function) +# define KEYMAP_TO_FUNCTION(data) (rl_command_func_t *)((int)(data)) +#else +# define FUNCTION_TO_KEYMAP(map, key) (Keymap)(map[key].function) +# define KEYMAP_TO_FUNCTION(data) (rl_command_func_t *)(data) +#endif + +#ifndef savestring +#define savestring(x) strcpy ((char *)xmalloc (1 + strlen (x)), (x)) +#endif + +/* Possible values for _rl_bell_preference. */ +#define NO_BELL 0 +#define AUDIBLE_BELL 1 +#define VISIBLE_BELL 2 + +/* Definitions used when searching the line for characters. */ +/* NOTE: it is necessary that opposite directions are inverses */ +#define FTO 1 /* forward to */ +#define BTO -1 /* backward to */ +#define FFIND 2 /* forward find */ +#define BFIND -2 /* backward find */ + +/* Possible values for the found_quote flags word used by the completion + functions. It says what kind of (shell-like) quoting we found anywhere + in the line. */ +#define RL_QF_SINGLE_QUOTE 0x01 +#define RL_QF_DOUBLE_QUOTE 0x02 +#define RL_QF_BACKSLASH 0x04 +#define RL_QF_OTHER_QUOTE 0x08 + +/* Default readline line buffer length. */ +#define DEFAULT_BUFFER_SIZE 256 + +#if !defined (STREQ) +#define STREQ(a, b) (((a)[0] == (b)[0]) && (strcmp ((a), (b)) == 0)) +#define STREQN(a, b, n) (((n) == 0) ? (1) \ + : ((a)[0] == (b)[0]) && (strncmp ((a), (b), (n)) == 0)) +#endif + +#if !defined (FREE) +# define FREE(x) if (x) free (x) +#endif + +#if !defined (SWAP) +# define SWAP(s, e) do { int t; t = s; s = e; e = t; } while (0) +#endif + +/* CONFIGURATION SECTION */ +#include "rlconf.h" + +#endif /* !_RLDEFS_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlmbutil.h b/external/gpl3/gdb/dist/readline/rlmbutil.h new file mode 100644 index 000000000000..cf6ef9e4dbe0 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlmbutil.h @@ -0,0 +1,156 @@ +/* rlmbutil.h -- utility functions for multibyte characters. */ + +/* Copyright (C) 2001, 2003 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RL_MBUTIL_H_) +#define _RL_MBUTIL_H_ + +#include "rlstdc.h" + +/************************************************/ +/* check multibyte capability for I18N code */ +/************************************************/ + +/* For platforms which support the ISO C amendement 1 functionality we + support user defined character classes. + + Some platforms have the multibyte functions such as mbsrtowcs but + are lacking the multitype type mbstate_t. BeOS (unknown version) + and HP/UX 11.23 without _XOPEN_SOURCE=500 are like this. + + We really need mbstate_t type to operate properly. For example, see + compute_lcd_of_matches, where two mbstate_t's are active at the same + time. So we require both the functions and the mbstate_t type in + order to enable multibyte support. */ + + /* Solaris 2.5 has a bug: must be included before . */ +#if defined (HAVE_WCTYPE_H) && defined (HAVE_WCHAR_H) +# include +# include +# if defined (HAVE_MBSTATE_T) && defined (HAVE_MBSRTOWCS) && defined (HAVE_MBRTOWC) && defined (HAVE_MBRLEN) && defined (HAVE_WCWIDTH) + /* system is supposed to support XPG5 */ +# define HANDLE_MULTIBYTE 1 +# endif +#endif + +/* If we don't want multibyte chars even on a system that supports them, let + the configuring user turn multibyte support off. */ +#if defined (NO_MULTIBYTE_SUPPORT) +# undef HANDLE_MULTIBYTE +#endif + +/* Some systems, like BeOS, have multibyte encodings but lack mbstate_t. */ +#if HANDLE_MULTIBYTE && !defined (HAVE_MBSTATE_T) +# define wcsrtombs(dest, src, len, ps) (wcsrtombs) (dest, src, len, 0) +# define mbsrtowcs(dest, src, len, ps) (mbsrtowcs) (dest, src, len, 0) +# define wcrtomb(s, wc, ps) (wcrtomb) (s, wc, 0) +# define mbrtowc(pwc, s, n, ps) (mbrtowc) (pwc, s, n, 0) +# define mbrlen(s, n, ps) (mbrlen) (s, n, 0) +# define mbstate_t int +#endif + +/* Make sure MB_LEN_MAX is at least 16 on systems that claim to be able to + handle multibyte chars (some systems define MB_LEN_MAX as 1) */ +#ifdef HANDLE_MULTIBYTE +# include +# if defined(MB_LEN_MAX) && (MB_LEN_MAX < 16) +# undef MB_LEN_MAX +# endif +# if !defined (MB_LEN_MAX) +# define MB_LEN_MAX 16 +# endif +#endif + +/************************************************/ +/* end of multibyte capability checks for I18N */ +/************************************************/ + +/* + * Flags for _rl_find_prev_mbchar and _rl_find_next_mbchar: + * + * MB_FIND_ANY find any multibyte character + * MB_FIND_NONZERO find a non-zero-width multibyte character + */ + +#define MB_FIND_ANY 0x00 +#define MB_FIND_NONZERO 0x01 + +extern int _rl_find_prev_mbchar PARAMS((char *, int, int)); +extern int _rl_find_next_mbchar PARAMS((char *, int, int, int)); + +#ifdef HANDLE_MULTIBYTE + +extern int _rl_compare_chars PARAMS((char *, int, mbstate_t *, char *, int, mbstate_t *)); +extern int _rl_get_char_len PARAMS((char *, mbstate_t *)); +extern int _rl_adjust_point PARAMS((char *, int, mbstate_t *)); + +extern int _rl_read_mbchar PARAMS((char *, int)); +extern int _rl_read_mbstring PARAMS((int, char *, int)); + +extern int _rl_is_mbchar_matched PARAMS((char *, int, int, char *, int)); + +extern wchar_t _rl_char_value PARAMS((char *, int)); +extern int _rl_walphabetic PARAMS((wchar_t)); + +#define _rl_to_wupper(wc) (iswlower (wc) ? towupper (wc) : (wc)) +#define _rl_to_wlower(wc) (iswupper (wc) ? towlower (wc) : (wc)) + +#define MB_NEXTCHAR(b,s,c,f) \ + ((MB_CUR_MAX > 1 && rl_byte_oriented == 0) \ + ? _rl_find_next_mbchar ((b), (s), (c), (f)) \ + : ((s) + (c))) +#define MB_PREVCHAR(b,s,f) \ + ((MB_CUR_MAX > 1 && rl_byte_oriented == 0) \ + ? _rl_find_prev_mbchar ((b), (s), (f)) \ + : ((s) - 1)) + +#define MB_INVALIDCH(x) ((x) == (size_t)-1 || (x) == (size_t)-2) +#define MB_NULLWCH(x) ((x) == 0) + +#else /* !HANDLE_MULTIBYTE */ + +#undef MB_LEN_MAX +#undef MB_CUR_MAX + +#define MB_LEN_MAX 1 +#define MB_CUR_MAX 1 + +#define _rl_find_prev_mbchar(b, i, f) (((i) == 0) ? (i) : ((i) - 1)) +#define _rl_find_next_mbchar(b, i1, i2, f) ((i1) + (i2)) + +#define _rl_char_value(buf,ind) ((buf)[(ind)]) + +#define _rl_walphabetic(c) (rl_alphabetic (c)) + +#define _rl_to_wupper(c) (_rl_to_upper (c)) +#define _rl_to_wlower(c) (_rl_to_lower (c)) + +#define MB_NEXTCHAR(b,s,c,f) ((s) + (c)) +#define MB_PREVCHAR(b,s,f) ((s) - 1) + +#define MB_INVALIDCH(x) (0) +#define MB_NULLWCH(x) (0) + +#endif /* !HANDLE_MULTIBYTE */ + +extern int rl_byte_oriented; + +#endif /* _RL_MBUTIL_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlprivate.h b/external/gpl3/gdb/dist/readline/rlprivate.h new file mode 100644 index 000000000000..1c216ead14f7 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlprivate.h @@ -0,0 +1,420 @@ +/* rlprivate.h -- functions and variables global to the readline library, + but not intended for use by applications. */ + +/* Copyright (C) 1999-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RL_PRIVATE_H_) +#define _RL_PRIVATE_H_ + +#include "rlconf.h" /* for VISIBLE_STATS */ +#include "rlstdc.h" +#include "posixjmp.h" /* defines procenv_t */ + +/************************************************************************* + * * + * Global structs undocumented in texinfo manual and not in readline.h * + * * + *************************************************************************/ +/* search types */ +#define RL_SEARCH_ISEARCH 0x01 /* incremental search */ +#define RL_SEARCH_NSEARCH 0x02 /* non-incremental search */ +#define RL_SEARCH_CSEARCH 0x04 /* intra-line char search */ + +/* search flags */ +#define SF_REVERSE 0x01 +#define SF_FOUND 0x02 +#define SF_FAILED 0x04 + +typedef struct __rl_search_context +{ + int type; + int sflags; + + char *search_string; + int search_string_index; + int search_string_size; + + char **lines; + char *allocated_line; + int hlen; + int hindex; + + int save_point; + int save_mark; + int save_line; + int last_found_line; + char *prev_line_found; + + UNDO_LIST *save_undo_list; + + int history_pos; + int direction; + + int lastc; +#if defined (HANDLE_MULTIBYTE) + char mb[MB_LEN_MAX]; +#endif + + char *sline; + int sline_len; + int sline_index; + + char *search_terminators; +} _rl_search_cxt; + +/* Callback data for reading numeric arguments */ +#define NUM_SAWMINUS 0x01 +#define NUM_SAWDIGITS 0x02 +#define NUM_READONE 0x04 + +typedef int _rl_arg_cxt; + +/* A context for reading key sequences longer than a single character when + using the callback interface. */ +#define KSEQ_DISPATCHED 0x01 +#define KSEQ_SUBSEQ 0x02 +#define KSEQ_RECURSIVE 0x04 + +typedef struct __rl_keyseq_context +{ + int flags; + int subseq_arg; + int subseq_retval; /* XXX */ + Keymap dmap; + + Keymap oldmap; + int okey; + struct __rl_keyseq_context *ocxt; + int childval; +} _rl_keyseq_cxt; + + /* fill in more as needed */ +/* `Generic' callback data and functions */ +typedef struct __rl_callback_generic_arg +{ + int count; + int i1, i2; + /* add here as needed */ +} _rl_callback_generic_arg; + +typedef int _rl_callback_func_t PARAMS((_rl_callback_generic_arg *)); + +/************************************************************************* + * * + * Global functions undocumented in texinfo manual and not in readline.h * + * * + *************************************************************************/ + +/************************************************************************* + * * + * Global variables undocumented in texinfo manual and not in readline.h * + * * + *************************************************************************/ + +/* complete.c */ +extern int rl_complete_with_tilde_expansion; +#if defined (VISIBLE_STATS) +extern int rl_visible_stats; +#endif /* VISIBLE_STATS */ + +/* readline.c */ +extern int rl_line_buffer_len; +extern int rl_arg_sign; +extern int rl_visible_prompt_length; +extern int readline_echoing_p; +extern int rl_key_sequence_length; +extern int rl_byte_oriented; + +extern _rl_keyseq_cxt *_rl_kscxt; + +/* display.c */ +extern int rl_display_fixed; + +/* parens.c */ +extern int rl_blink_matching_paren; + +/************************************************************************* + * * + * Global functions and variables unsed and undocumented * + * * + *************************************************************************/ + +/* kill.c */ +extern int rl_set_retained_kills PARAMS((int)); + +/* terminal.c */ +extern void _rl_set_screen_size PARAMS((int, int)); + +/* undo.c */ +extern int _rl_fix_last_undo_of_type PARAMS((int, int, int)); + +/* util.c */ +extern char *_rl_savestring PARAMS((const char *)); + +/************************************************************************* + * * + * Functions and variables private to the readline library * + * * + *************************************************************************/ + +/* NOTE: Functions and variables prefixed with `_rl_' are + pseudo-global: they are global so they can be shared + between files in the readline library, but are not intended + to be visible to readline callers. */ + +/************************************************************************* + * Undocumented private functions * + *************************************************************************/ + +#if defined(READLINE_CALLBACKS) + +/* readline.c */ +extern void readline_internal_setup PARAMS((void)); +extern char *readline_internal_teardown PARAMS((int)); +extern int readline_internal_char PARAMS((void)); + +extern _rl_keyseq_cxt *_rl_keyseq_cxt_alloc PARAMS((void)); +extern void _rl_keyseq_cxt_dispose PARAMS((_rl_keyseq_cxt *)); +extern void _rl_keyseq_chain_dispose PARAMS((void)); + +extern int _rl_dispatch_callback PARAMS((_rl_keyseq_cxt *)); + +/* callback.c */ +extern _rl_callback_generic_arg *_rl_callback_data_alloc PARAMS((int)); +extern void _rl_callback_data_dispose PARAMS((_rl_callback_generic_arg *)); + +#endif /* READLINE_CALLBACKS */ + +/* bind.c */ + +/* complete.c */ +extern char _rl_find_completion_word PARAMS((int *, int *)); +extern void _rl_free_match_list PARAMS((char **)); + +/* display.c */ +extern char *_rl_strip_prompt PARAMS((char *)); +extern void _rl_move_cursor_relative PARAMS((int, const char *)); +extern void _rl_move_vert PARAMS((int)); +extern void _rl_save_prompt PARAMS((void)); +extern void _rl_restore_prompt PARAMS((void)); +extern char *_rl_make_prompt_for_search PARAMS((int)); +extern void _rl_erase_at_end_of_line PARAMS((int)); +extern void _rl_clear_to_eol PARAMS((int)); +extern void _rl_clear_screen PARAMS((void)); +extern void _rl_update_final PARAMS((void)); +extern void _rl_redisplay_after_sigwinch PARAMS((void)); +extern void _rl_clean_up_for_exit PARAMS((void)); +extern void _rl_erase_entire_line PARAMS((void)); +extern int _rl_current_display_line PARAMS((void)); + +/* input.c */ +extern int _rl_any_typein PARAMS((void)); +extern int _rl_input_available PARAMS((void)); +extern int _rl_input_queued PARAMS((int)); +extern void _rl_insert_typein PARAMS((int)); +extern int _rl_unget_char PARAMS((int)); +extern int _rl_pushed_input_available PARAMS((void)); + +/* isearch.c */ +extern _rl_search_cxt *_rl_scxt_alloc PARAMS((int, int)); +extern void _rl_scxt_dispose PARAMS((_rl_search_cxt *, int)); + +extern int _rl_isearch_dispatch PARAMS((_rl_search_cxt *, int)); +extern int _rl_isearch_callback PARAMS((_rl_search_cxt *)); + +extern int _rl_search_getchar PARAMS((_rl_search_cxt *)); + +/* macro.c */ +extern void _rl_with_macro_input PARAMS((char *)); +extern int _rl_next_macro_key PARAMS((void)); +extern void _rl_push_executing_macro PARAMS((void)); +extern void _rl_pop_executing_macro PARAMS((void)); +extern void _rl_add_macro_char PARAMS((int)); +extern void _rl_kill_kbd_macro PARAMS((void)); + +/* misc.c */ +extern int _rl_arg_overflow PARAMS((void)); +extern void _rl_arg_init PARAMS((void)); +extern int _rl_arg_getchar PARAMS((void)); +extern int _rl_arg_callback PARAMS((_rl_arg_cxt)); +extern void _rl_reset_argument PARAMS((void)); + +extern void _rl_start_using_history PARAMS((void)); +extern int _rl_free_saved_history_line PARAMS((void)); +extern void _rl_set_insert_mode PARAMS((int, int)); + +/* nls.c */ +extern int _rl_init_eightbit PARAMS((void)); + +/* parens.c */ +extern void _rl_enable_paren_matching PARAMS((int)); + +/* readline.c */ +extern void _rl_init_line_state PARAMS((void)); +extern void _rl_set_the_line PARAMS((void)); +extern int _rl_dispatch PARAMS((int, Keymap)); +extern int _rl_dispatch_subseq PARAMS((int, Keymap, int)); +extern void _rl_internal_char_cleanup PARAMS((void)); + +/* rltty.c */ +extern int _rl_disable_tty_signals PARAMS((void)); +extern int _rl_restore_tty_signals PARAMS((void)); + +/* search.c */ +extern int _rl_nsearch_callback PARAMS((_rl_search_cxt *)); + +/* terminal.c */ +extern void _rl_get_screen_size PARAMS((int, int)); +extern int _rl_init_terminal_io PARAMS((const char *)); +#ifdef _MINIX +extern void _rl_output_character_function PARAMS((int)); +#else +extern int _rl_output_character_function PARAMS((int)); +#endif +extern void _rl_output_some_chars PARAMS((const char *, int)); +extern int _rl_backspace PARAMS((int)); +extern void _rl_enable_meta_key PARAMS((void)); +extern void _rl_control_keypad PARAMS((int)); +extern void _rl_set_cursor PARAMS((int, int)); + +/* text.c */ +extern void _rl_fix_point PARAMS((int)); +extern int _rl_replace_text PARAMS((const char *, int, int)); +extern int _rl_insert_char PARAMS((int, int)); +extern int _rl_overwrite_char PARAMS((int, int)); +extern int _rl_overwrite_rubout PARAMS((int, int)); +extern int _rl_rubout_char PARAMS((int, int)); +#if defined (HANDLE_MULTIBYTE) +extern int _rl_char_search_internal PARAMS((int, int, char *, int)); +#else +extern int _rl_char_search_internal PARAMS((int, int, int)); +#endif +extern int _rl_set_mark_at_pos PARAMS((int)); + +/* util.c */ +extern int _rl_abort_internal PARAMS((void)); +extern char *_rl_strindex PARAMS((const char *, const char *)); +extern int _rl_qsort_string_compare PARAMS((char **, char **)); +extern int (_rl_uppercase_p) PARAMS((int)); +extern int (_rl_lowercase_p) PARAMS((int)); +extern int (_rl_pure_alphabetic) PARAMS((int)); +extern int (_rl_digit_p) PARAMS((int)); +extern int (_rl_to_lower) PARAMS((int)); +extern int (_rl_to_upper) PARAMS((int)); +extern int (_rl_digit_value) PARAMS((int)); + +/* vi_mode.c */ +extern void _rl_vi_initialize_line PARAMS((void)); +extern void _rl_vi_reset_last PARAMS((void)); +extern void _rl_vi_set_last PARAMS((int, int, int)); +extern int _rl_vi_textmod_command PARAMS((int)); +extern void _rl_vi_done_inserting PARAMS((void)); + +/************************************************************************* + * Undocumented private variables * + *************************************************************************/ + +/* bind.c */ +extern const char *_rl_possible_control_prefixes[]; +extern const char *_rl_possible_meta_prefixes[]; + +/* callback.c */ +extern _rl_callback_func_t *_rl_callback_func; +extern _rl_callback_generic_arg *_rl_callback_data; + +/* complete.c */ +extern int _rl_complete_show_all; +extern int _rl_complete_show_unmodified; +extern int _rl_complete_mark_directories; +extern int _rl_complete_mark_symlink_dirs; +extern int _rl_print_completions_horizontally; +extern int _rl_completion_case_fold; +extern int _rl_match_hidden_files; +extern int _rl_page_completions; + +/* display.c */ +extern int _rl_vis_botlin; +extern int _rl_last_c_pos; +extern int _rl_suppress_redisplay; +extern int _rl_want_redisplay; +extern char *rl_display_prompt; + +/* isearch.c */ +extern char *_rl_isearch_terminators; + +extern _rl_search_cxt *_rl_iscxt; + +/* macro.c */ +extern char *_rl_executing_macro; + +/* misc.c */ +extern int _rl_history_preserve_point; +extern int _rl_history_saved_point; + +extern _rl_arg_cxt _rl_argcxt; + +/* readline.c */ +extern int _rl_horizontal_scroll_mode; +extern int _rl_mark_modified_lines; +extern int _rl_bell_preference; +extern int _rl_meta_flag; +extern int _rl_convert_meta_chars_to_ascii; +extern int _rl_output_meta_chars; +extern int _rl_bind_stty_chars; +extern char *_rl_comment_begin; +extern unsigned char _rl_parsing_conditionalized_out; +extern Keymap _rl_keymap; +extern FILE *_rl_in_stream; +extern FILE *_rl_out_stream; +extern int _rl_last_command_was_kill; +extern int _rl_eof_char; +extern procenv_t readline_top_level; + +/* search.c */ +extern _rl_search_cxt *_rl_nscxt; + +/* terminal.c */ +extern int _rl_enable_keypad; +extern int _rl_enable_meta; +extern char *_rl_term_clreol; +extern char *_rl_term_clrpag; +extern char *_rl_term_im; +extern char *_rl_term_ic; +extern char *_rl_term_ei; +extern char *_rl_term_DC; +extern char *_rl_term_up; +extern char *_rl_term_dc; +extern char *_rl_term_cr; +extern char *_rl_term_IC; +extern int _rl_screenheight; +extern int _rl_screenwidth; +extern int _rl_screenchars; +extern int _rl_terminal_can_insert; +extern int _rl_term_autowrap; + +/* undo.c */ +extern int _rl_doing_an_undo; +extern int _rl_undo_group_level; + +/* vi_mode.c */ +extern int _rl_vi_last_command; + +#endif /* _RL_PRIVATE_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlshell.h b/external/gpl3/gdb/dist/readline/rlshell.h new file mode 100644 index 000000000000..3c03fbad5765 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlshell.h @@ -0,0 +1,34 @@ +/* rlshell.h -- utility functions normally provided by bash. */ + +/* Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RL_SHELL_H_) +#define _RL_SHELL_H_ + +#include "rlstdc.h" + +extern char *sh_single_quote PARAMS((char *)); +extern void sh_set_lines_and_columns PARAMS((int, int)); +extern char *sh_get_env_value PARAMS((const char *)); +extern char *sh_get_home_dir PARAMS((void)); +extern int sh_unset_nodelay_mode PARAMS((int)); + +#endif /* _RL_SHELL_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlstdc.h b/external/gpl3/gdb/dist/readline/rlstdc.h new file mode 100644 index 000000000000..847fa9c26f4c --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlstdc.h @@ -0,0 +1,45 @@ +/* stdc.h -- macros to make source compile on both ANSI C and K&R C + compilers. */ + +/* Copyright (C) 1993 Free Software Foundation, Inc. + + This file is part of GNU Bash, the Bourne Again SHell. + + Bash is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + Bash is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with Bash; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RL_STDC_H_) +#define _RL_STDC_H_ + +/* Adapted from BSD /usr/include/sys/cdefs.h. */ + +/* A function can be defined using prototypes and compile on both ANSI C + and traditional C compilers with something like this: + extern char *func PARAMS((char *, char *, int)); */ + +#if !defined (PARAMS) +# if defined (__STDC__) || defined (__GNUC__) || defined (__cplusplus) +# define PARAMS(protos) protos +# else +# define PARAMS(protos) () +# endif +#endif + +#ifndef __attribute__ +# if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 8) +# define __attribute__(x) +# endif +#endif + +#endif /* !_RL_STDC_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rltty.c b/external/gpl3/gdb/dist/readline/rltty.c new file mode 100644 index 000000000000..0cd5028e4912 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rltty.c @@ -0,0 +1,1035 @@ +/* rltty.c -- functions to prepare and restore the terminal for readline's + use. */ + +/* Copyright (C) 1992-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#include "rldefs.h" + +#if defined (GWINSZ_IN_SYS_IOCTL) +# include +#endif /* GWINSZ_IN_SYS_IOCTL */ + +#include "rltty.h" +#include "readline.h" +#include "rlprivate.h" + +#if !defined (errno) +extern int errno; +#endif /* !errno */ + +rl_vintfunc_t *rl_prep_term_function = rl_prep_terminal; +rl_voidfunc_t *rl_deprep_term_function = rl_deprep_terminal; + +void _rl_block_sigint PARAMS((void)); +void _rl_release_sigint PARAMS((void)); + +static void set_winsize PARAMS((int)); + +/* **************************************************************** */ +/* */ +/* Signal Management */ +/* */ +/* **************************************************************** */ + +#if defined (HAVE_POSIX_SIGNALS) +static sigset_t sigint_set, sigint_oset; +#else /* !HAVE_POSIX_SIGNALS */ +# if defined (HAVE_BSD_SIGNALS) +static int sigint_oldmask; +# endif /* HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + +static int sigint_blocked; + +/* Cause SIGINT to not be delivered until the corresponding call to + _rl_release_sigint(). */ +void +_rl_block_sigint () +{ + if (sigint_blocked) + return; + +#if defined (HAVE_POSIX_SIGNALS) + sigemptyset (&sigint_set); + sigemptyset (&sigint_oset); + sigaddset (&sigint_set, SIGINT); + sigprocmask (SIG_BLOCK, &sigint_set, &sigint_oset); +#else /* !HAVE_POSIX_SIGNALS */ +# if defined (HAVE_BSD_SIGNALS) + sigint_oldmask = sigblock (sigmask (SIGINT)); +# else /* !HAVE_BSD_SIGNALS */ +# if defined (HAVE_USG_SIGHOLD) + sighold (SIGINT); +# endif /* HAVE_USG_SIGHOLD */ +# endif /* !HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + + sigint_blocked = 1; +} + +/* Allow SIGINT to be delivered. */ +void +_rl_release_sigint () +{ + if (sigint_blocked == 0) + return; + +#if defined (HAVE_POSIX_SIGNALS) + sigprocmask (SIG_SETMASK, &sigint_oset, (sigset_t *)NULL); +#else +# if defined (HAVE_BSD_SIGNALS) + sigsetmask (sigint_oldmask); +# else /* !HAVE_BSD_SIGNALS */ +# if defined (HAVE_USG_SIGHOLD) + sigrelse (SIGINT); +# endif /* HAVE_USG_SIGHOLD */ +# endif /* !HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + + sigint_blocked = 0; +} + +/* **************************************************************** */ +/* */ +/* Saving and Restoring the TTY */ +/* */ +/* **************************************************************** */ + +/* Non-zero means that the terminal is in a prepped state. */ +static int terminal_prepped; + +static _RL_TTY_CHARS _rl_tty_chars, _rl_last_tty_chars; + +/* If non-zero, means that this process has called tcflow(fd, TCOOFF) + and output is suspended. */ +#if defined (__ksr1__) +static int ksrflow; +#endif + +/* Dummy call to force a backgrounded readline to stop before it tries + to get the tty settings. */ +static void +set_winsize (tty) + int tty; +{ +#if defined (TIOCGWINSZ) + struct winsize w; + + if (ioctl (tty, TIOCGWINSZ, &w) == 0) + (void) ioctl (tty, TIOCSWINSZ, &w); +#endif /* TIOCGWINSZ */ +} + +#if defined (NO_TTY_DRIVER) +/* Nothing */ +#elif defined (NEW_TTY_DRIVER) + +/* Values for the `flags' field of a struct bsdtty. This tells which + elements of the struct bsdtty have been fetched from the system and + are valid. */ +#define SGTTY_SET 0x01 +#define LFLAG_SET 0x02 +#define TCHARS_SET 0x04 +#define LTCHARS_SET 0x08 + +struct bsdtty { + struct sgttyb sgttyb; /* Basic BSD tty driver information. */ + int lflag; /* Local mode flags, like LPASS8. */ +#if defined (TIOCGETC) + struct tchars tchars; /* Terminal special characters, including ^S and ^Q. */ +#endif +#if defined (TIOCGLTC) + struct ltchars ltchars; /* 4.2 BSD editing characters */ +#endif + int flags; /* Bitmap saying which parts of the struct are valid. */ +}; + +#define TIOTYPE struct bsdtty + +static TIOTYPE otio; + +static void save_tty_chars PARAMS((TIOTYPE *)); +static int _get_tty_settings PARAMS((int, TIOTYPE *)); +static int get_tty_settings PARAMS((int, TIOTYPE *)); +static int _set_tty_settings PARAMS((int, TIOTYPE *)); +static int set_tty_settings PARAMS((int, TIOTYPE *)); + +static void prepare_terminal_settings PARAMS((int, TIOTYPE, TIOTYPE *)); + +static void set_special_char PARAMS((Keymap, TIOTYPE *, int, rl_command_func_t)); + +static void +save_tty_chars (tiop) + TIOTYPE *tiop; +{ + _rl_last_tty_chars = _rl_tty_chars; + + if (tiop->flags & SGTTY_SET) + { + _rl_tty_chars.t_erase = tiop->sgttyb.sg_erase; + _rl_tty_chars.t_kill = tiop->sgttyb.sg_kill; + } + + if (tiop->flags & TCHARS_SET) + { + _rl_tty_chars.t_intr = tiop->tchars.t_intrc; + _rl_tty_chars.t_quit = tiop->tchars.t_quitc; + _rl_tty_chars.t_start = tiop->tchars.t_startc; + _rl_tty_chars.t_stop = tiop->tchars.t_stopc; + _rl_tty_chars.t_eof = tiop->tchars.t_eofc; + _rl_tty_chars.t_eol = '\n'; + _rl_tty_chars.t_eol2 = tiop->tchars.t_brkc; + } + + if (tiop->flags & LTCHARS_SET) + { + _rl_tty_chars.t_susp = tiop->ltchars.t_suspc; + _rl_tty_chars.t_dsusp = tiop->ltchars.t_dsuspc; + _rl_tty_chars.t_reprint = tiop->ltchars.t_rprntc; + _rl_tty_chars.t_flush = tiop->ltchars.t_flushc; + _rl_tty_chars.t_werase = tiop->ltchars.t_werasc; + _rl_tty_chars.t_lnext = tiop->ltchars.t_lnextc; + } + + _rl_tty_chars.t_status = -1; +} + +static int +get_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + set_winsize (tty); + + tiop->flags = tiop->lflag = 0; + + errno = 0; + if (ioctl (tty, TIOCGETP, &(tiop->sgttyb)) < 0) + return -1; + tiop->flags |= SGTTY_SET; + +#if defined (TIOCLGET) + if (ioctl (tty, TIOCLGET, &(tiop->lflag)) == 0) + tiop->flags |= LFLAG_SET; +#endif + +#if defined (TIOCGETC) + if (ioctl (tty, TIOCGETC, &(tiop->tchars)) == 0) + tiop->flags |= TCHARS_SET; +#endif + +#if defined (TIOCGLTC) + if (ioctl (tty, TIOCGLTC, &(tiop->ltchars)) == 0) + tiop->flags |= LTCHARS_SET; +#endif + + return 0; +} + +static int +set_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + if (tiop->flags & SGTTY_SET) + { + ioctl (tty, TIOCSETN, &(tiop->sgttyb)); + tiop->flags &= ~SGTTY_SET; + } + readline_echoing_p = 1; + +#if defined (TIOCLSET) + if (tiop->flags & LFLAG_SET) + { + ioctl (tty, TIOCLSET, &(tiop->lflag)); + tiop->flags &= ~LFLAG_SET; + } +#endif + +#if defined (TIOCSETC) + if (tiop->flags & TCHARS_SET) + { + ioctl (tty, TIOCSETC, &(tiop->tchars)); + tiop->flags &= ~TCHARS_SET; + } +#endif + +#if defined (TIOCSLTC) + if (tiop->flags & LTCHARS_SET) + { + ioctl (tty, TIOCSLTC, &(tiop->ltchars)); + tiop->flags &= ~LTCHARS_SET; + } +#endif + + return 0; +} + +static void +prepare_terminal_settings (meta_flag, oldtio, tiop) + int meta_flag; + TIOTYPE oldtio, *tiop; +{ + readline_echoing_p = (oldtio.sgttyb.sg_flags & ECHO); + + /* Copy the original settings to the structure we're going to use for + our settings. */ + tiop->sgttyb = oldtio.sgttyb; + tiop->lflag = oldtio.lflag; +#if defined (TIOCGETC) + tiop->tchars = oldtio.tchars; +#endif +#if defined (TIOCGLTC) + tiop->ltchars = oldtio.ltchars; +#endif + tiop->flags = oldtio.flags; + + /* First, the basic settings to put us into character-at-a-time, no-echo + input mode. */ + tiop->sgttyb.sg_flags &= ~(ECHO | CRMOD); + tiop->sgttyb.sg_flags |= CBREAK; + + /* If this terminal doesn't care how the 8th bit is used, then we can + use it for the meta-key. If only one of even or odd parity is + specified, then the terminal is using parity, and we cannot. */ +#if !defined (ANYP) +# define ANYP (EVENP | ODDP) +#endif + if (((oldtio.sgttyb.sg_flags & ANYP) == ANYP) || + ((oldtio.sgttyb.sg_flags & ANYP) == 0)) + { + tiop->sgttyb.sg_flags |= ANYP; + + /* Hack on local mode flags if we can. */ +#if defined (TIOCLGET) +# if defined (LPASS8) + tiop->lflag |= LPASS8; +# endif /* LPASS8 */ +#endif /* TIOCLGET */ + } + +#if defined (TIOCGETC) +# if defined (USE_XON_XOFF) + /* Get rid of terminal output start and stop characters. */ + tiop->tchars.t_stopc = -1; /* C-s */ + tiop->tchars.t_startc = -1; /* C-q */ + + /* If there is an XON character, bind it to restart the output. */ + if (oldtio.tchars.t_startc != -1) + rl_bind_key (oldtio.tchars.t_startc, rl_restart_output); +# endif /* USE_XON_XOFF */ + + /* If there is an EOF char, bind _rl_eof_char to it. */ + if (oldtio.tchars.t_eofc != -1) + _rl_eof_char = oldtio.tchars.t_eofc; + +# if defined (NO_KILL_INTR) + /* Get rid of terminal-generated SIGQUIT and SIGINT. */ + tiop->tchars.t_quitc = -1; /* C-\ */ + tiop->tchars.t_intrc = -1; /* C-c */ +# endif /* NO_KILL_INTR */ +#endif /* TIOCGETC */ + +#if defined (TIOCGLTC) + /* Make the interrupt keys go away. Just enough to make people happy. */ + tiop->ltchars.t_dsuspc = -1; /* C-y */ + tiop->ltchars.t_lnextc = -1; /* C-v */ +#endif /* TIOCGLTC */ +} + +#else /* !defined (NEW_TTY_DRIVER) */ + +#if !defined (VMIN) +# define VMIN VEOF +#endif + +#if !defined (VTIME) +# define VTIME VEOL +#endif + +#if defined (TERMIOS_TTY_DRIVER) +# define TIOTYPE struct termios +# define DRAIN_OUTPUT(fd) tcdrain (fd) +# define GETATTR(tty, tiop) (tcgetattr (tty, tiop)) +# ifdef M_UNIX +# define SETATTR(tty, tiop) (tcsetattr (tty, TCSANOW, tiop)) +# else +# define SETATTR(tty, tiop) (tcsetattr (tty, TCSADRAIN, tiop)) +# endif /* !M_UNIX */ +#else +# define TIOTYPE struct termio +# define DRAIN_OUTPUT(fd) +# define GETATTR(tty, tiop) (ioctl (tty, TCGETA, tiop)) +# define SETATTR(tty, tiop) (ioctl (tty, TCSETAW, tiop)) +#endif /* !TERMIOS_TTY_DRIVER */ + +static TIOTYPE otio; + +static void save_tty_chars PARAMS((TIOTYPE *)); +static int _get_tty_settings PARAMS((int, TIOTYPE *)); +static int get_tty_settings PARAMS((int, TIOTYPE *)); +static int _set_tty_settings PARAMS((int, TIOTYPE *)); +static int set_tty_settings PARAMS((int, TIOTYPE *)); + +static void prepare_terminal_settings PARAMS((int, TIOTYPE, TIOTYPE *)); + +static void set_special_char PARAMS((Keymap, TIOTYPE *, int, rl_command_func_t)); +static void _rl_bind_tty_special_chars PARAMS((Keymap, TIOTYPE)); + +#if defined (FLUSHO) +# define OUTPUT_BEING_FLUSHED(tp) (tp->c_lflag & FLUSHO) +#else +# define OUTPUT_BEING_FLUSHED(tp) 0 +#endif + +static void +save_tty_chars (tiop) + TIOTYPE *tiop; +{ + _rl_last_tty_chars = _rl_tty_chars; + + _rl_tty_chars.t_eof = tiop->c_cc[VEOF]; + _rl_tty_chars.t_eol = tiop->c_cc[VEOL]; +#ifdef VEOL2 + _rl_tty_chars.t_eol2 = tiop->c_cc[VEOL2]; +#endif + _rl_tty_chars.t_erase = tiop->c_cc[VERASE]; +#ifdef VWERASE + _rl_tty_chars.t_werase = tiop->c_cc[VWERASE]; +#endif + _rl_tty_chars.t_kill = tiop->c_cc[VKILL]; +#ifdef VREPRINT + _rl_tty_chars.t_reprint = tiop->c_cc[VREPRINT]; +#endif + _rl_tty_chars.t_intr = tiop->c_cc[VINTR]; + _rl_tty_chars.t_quit = tiop->c_cc[VQUIT]; +#ifdef VSUSP + _rl_tty_chars.t_susp = tiop->c_cc[VSUSP]; +#endif +#ifdef VDSUSP + _rl_tty_chars.t_dsusp = tiop->c_cc[VDSUSP]; +#endif +#ifdef VSTART + _rl_tty_chars.t_start = tiop->c_cc[VSTART]; +#endif +#ifdef VSTOP + _rl_tty_chars.t_stop = tiop->c_cc[VSTOP]; +#endif +#ifdef VLNEXT + _rl_tty_chars.t_lnext = tiop->c_cc[VLNEXT]; +#endif +#ifdef VDISCARD + _rl_tty_chars.t_flush = tiop->c_cc[VDISCARD]; +#endif +#ifdef VSTATUS + _rl_tty_chars.t_status = tiop->c_cc[VSTATUS]; +#endif +} + +#if defined (_AIX) || defined (_AIX41) +/* Currently this is only used on AIX */ +static void +rltty_warning (msg) + char *msg; +{ + fprintf (stderr, "readline: warning: %s\n", msg); +} +#endif + +#if defined (_AIX) +void +setopost(tp) +TIOTYPE *tp; +{ + if ((tp->c_oflag & OPOST) == 0) + { + rltty_warning ("turning on OPOST for terminal\r"); + tp->c_oflag |= OPOST|ONLCR; + } +} +#endif + +static int +_get_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + int ioctl_ret; + + while (1) + { + ioctl_ret = GETATTR (tty, tiop); + if (ioctl_ret < 0) + { + if (errno != EINTR) + return -1; + else + continue; + } + if (OUTPUT_BEING_FLUSHED (tiop)) + { +#if defined (FLUSHO) && defined (_AIX41) + rltty_warning ("turning off output flushing"); + tiop->c_lflag &= ~FLUSHO; + break; +#else + continue; +#endif + } + break; + } + + return 0; +} + +static int +get_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + set_winsize (tty); + + errno = 0; + if (_get_tty_settings (tty, tiop) < 0) + return -1; + +#if defined (_AIX) + setopost(tiop); +#endif + + return 0; +} + +static int +_set_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + while (SETATTR (tty, tiop) < 0) + { + if (errno != EINTR) + return -1; + errno = 0; + } + return 0; +} + +static int +set_tty_settings (tty, tiop) + int tty; + TIOTYPE *tiop; +{ + if (_set_tty_settings (tty, tiop) < 0) + return -1; + +#if 0 + +#if defined (TERMIOS_TTY_DRIVER) +# if defined (__ksr1__) + if (ksrflow) + { + ksrflow = 0; + tcflow (tty, TCOON); + } +# else /* !ksr1 */ + tcflow (tty, TCOON); /* Simulate a ^Q. */ +# endif /* !ksr1 */ +#else + ioctl (tty, TCXONC, 1); /* Simulate a ^Q. */ +#endif /* !TERMIOS_TTY_DRIVER */ + +#endif /* 0 */ + + return 0; +} + +static void +prepare_terminal_settings (meta_flag, oldtio, tiop) + int meta_flag; + TIOTYPE oldtio, *tiop; +{ + readline_echoing_p = (oldtio.c_lflag & ECHO); + + tiop->c_lflag &= ~(ICANON | ECHO); + + if ((unsigned char) oldtio.c_cc[VEOF] != (unsigned char) _POSIX_VDISABLE) + _rl_eof_char = oldtio.c_cc[VEOF]; + +#if defined (USE_XON_XOFF) +#if defined (IXANY) + tiop->c_iflag &= ~(IXON | IXOFF | IXANY); +#else + /* `strict' Posix systems do not define IXANY. */ + tiop->c_iflag &= ~(IXON | IXOFF); +#endif /* IXANY */ +#endif /* USE_XON_XOFF */ + + /* Only turn this off if we are using all 8 bits. */ + if (((tiop->c_cflag & CSIZE) == CS8) || meta_flag) + tiop->c_iflag &= ~(ISTRIP | INPCK); + + /* Make sure we differentiate between CR and NL on input. */ + tiop->c_iflag &= ~(ICRNL | INLCR); + +#if !defined (HANDLE_SIGNALS) + tiop->c_lflag &= ~ISIG; +#else + tiop->c_lflag |= ISIG; +#endif + + tiop->c_cc[VMIN] = 1; + tiop->c_cc[VTIME] = 0; + +#if defined (FLUSHO) + if (OUTPUT_BEING_FLUSHED (tiop)) + { + tiop->c_lflag &= ~FLUSHO; + oldtio.c_lflag &= ~FLUSHO; + } +#endif + + /* Turn off characters that we need on Posix systems with job control, + just to be sure. This includes ^Y and ^V. This should not really + be necessary. */ +#if defined (TERMIOS_TTY_DRIVER) && defined (_POSIX_VDISABLE) + +#if defined (VLNEXT) + tiop->c_cc[VLNEXT] = _POSIX_VDISABLE; +#endif + +#if defined (VDSUSP) + tiop->c_cc[VDSUSP] = _POSIX_VDISABLE; +#endif + +#endif /* TERMIOS_TTY_DRIVER && _POSIX_VDISABLE */ +} +#endif /* !NEW_TTY_DRIVER */ + +/* Put the terminal in CBREAK mode so that we can detect key presses. */ +#if defined (NO_TTY_DRIVER) +void +rl_prep_terminal (meta_flag) + int meta_flag; +{ + readline_echoing_p = 1; +} + +void +rl_deprep_terminal () +{ +} + +#else /* ! NO_TTY_DRIVER */ +void +rl_prep_terminal (meta_flag) + int meta_flag; +{ + int tty; + TIOTYPE tio; + + if (terminal_prepped) + return; + + /* Try to keep this function from being INTerrupted. */ + _rl_block_sigint (); + + tty = fileno (rl_instream); + + if (get_tty_settings (tty, &tio) < 0) + { +#if defined (ENOTSUP) + /* MacOS X, at least, lies about the value of errno if tcgetattr fails. */ + if (errno == ENOTTY || errno == ENOTSUP) +#else + if (errno == ENOTTY) +#endif + readline_echoing_p = 1; /* XXX */ + _rl_release_sigint (); + return; + } + + otio = tio; + + if (_rl_bind_stty_chars) + { +#if defined (VI_MODE) + /* If editing in vi mode, make sure we restore the bindings in the + insertion keymap no matter what keymap we ended up in. */ + if (rl_editing_mode == vi_mode) + rl_tty_unset_default_bindings (vi_insertion_keymap); + else +#endif + rl_tty_unset_default_bindings (_rl_keymap); + } + save_tty_chars (&otio); + RL_SETSTATE(RL_STATE_TTYCSAVED); + if (_rl_bind_stty_chars) + { +#if defined (VI_MODE) + /* If editing in vi mode, make sure we set the bindings in the + insertion keymap no matter what keymap we ended up in. */ + if (rl_editing_mode == vi_mode) + _rl_bind_tty_special_chars (vi_insertion_keymap, tio); + else +#endif + _rl_bind_tty_special_chars (_rl_keymap, tio); + } + + prepare_terminal_settings (meta_flag, otio, &tio); + + if (set_tty_settings (tty, &tio) < 0) + { + _rl_release_sigint (); + return; + } + + if (_rl_enable_keypad) + _rl_control_keypad (1); + + fflush (rl_outstream); + terminal_prepped = 1; + RL_SETSTATE(RL_STATE_TERMPREPPED); + + _rl_release_sigint (); +} + +/* Restore the terminal's normal settings and modes. */ +void +rl_deprep_terminal () +{ + int tty; + + if (!terminal_prepped) + return; + + /* Try to keep this function from being interrupted. */ + _rl_block_sigint (); + + tty = fileno (rl_instream); + + if (_rl_enable_keypad) + _rl_control_keypad (0); + + fflush (rl_outstream); + + if (set_tty_settings (tty, &otio) < 0) + { + _rl_release_sigint (); + return; + } + + terminal_prepped = 0; + RL_UNSETSTATE(RL_STATE_TERMPREPPED); + + _rl_release_sigint (); +} +#endif /* !NO_TTY_DRIVER */ + +/* **************************************************************** */ +/* */ +/* Bogus Flow Control */ +/* */ +/* **************************************************************** */ + +int +rl_restart_output (count, key) + int count, key; +{ +#if defined (__MINGW32__) + return 0; +#else /* !__MING32__ */ + + int fildes = fileno (rl_outstream); +#if defined (TIOCSTART) +#if defined (apollo) + ioctl (&fildes, TIOCSTART, 0); +#else + ioctl (fildes, TIOCSTART, 0); +#endif /* apollo */ + +#else /* !TIOCSTART */ +# if defined (TERMIOS_TTY_DRIVER) +# if defined (__ksr1__) + if (ksrflow) + { + ksrflow = 0; + tcflow (fildes, TCOON); + } +# else /* !ksr1 */ + tcflow (fildes, TCOON); /* Simulate a ^Q. */ +# endif /* !ksr1 */ +# else /* !TERMIOS_TTY_DRIVER */ +# if defined (TCXONC) + ioctl (fildes, TCXONC, TCOON); +# endif /* TCXONC */ +# endif /* !TERMIOS_TTY_DRIVER */ +#endif /* !TIOCSTART */ + + return 0; +#endif /* !__MINGW32__ */ +} + +int +rl_stop_output (count, key) + int count, key; +{ +#if defined (__MINGW32__) + return 0; +#else + + int fildes = fileno (rl_instream); + +#if defined (TIOCSTOP) +# if defined (apollo) + ioctl (&fildes, TIOCSTOP, 0); +# else + ioctl (fildes, TIOCSTOP, 0); +# endif /* apollo */ +#else /* !TIOCSTOP */ +# if defined (TERMIOS_TTY_DRIVER) +# if defined (__ksr1__) + ksrflow = 1; +# endif /* ksr1 */ + tcflow (fildes, TCOOFF); +# else +# if defined (TCXONC) + ioctl (fildes, TCXONC, TCOON); +# endif /* TCXONC */ +# endif /* !TERMIOS_TTY_DRIVER */ +#endif /* !TIOCSTOP */ + + return 0; +#endif /* !__MINGW32__ */ +} + +/* **************************************************************** */ +/* */ +/* Default Key Bindings */ +/* */ +/* **************************************************************** */ + +#if !defined (NO_TTY_DRIVER) +#define SET_SPECIAL(sc, func) set_special_char(kmap, &ttybuff, sc, func) +#endif + +#if defined (NO_TTY_DRIVER) + +#define SET_SPECIAL(sc, func) +#define RESET_SPECIAL(c) + +#elif defined (NEW_TTY_DRIVER) +static void +set_special_char (kmap, tiop, sc, func) + Keymap kmap; + TIOTYPE *tiop; + int sc; + rl_command_func_t *func; +{ + if (sc != -1 && kmap[(unsigned char)sc].type == ISFUNC) + kmap[(unsigned char)sc].function = func; +} + +#define RESET_SPECIAL(c) \ + if (c != -1 && kmap[(unsigned char)c].type == ISFUNC) + kmap[(unsigned char)c].function = rl_insert; + +static void +_rl_bind_tty_special_chars (kmap, ttybuff) + Keymap kmap; + TIOTYPE ttybuff; +{ + if (ttybuff.flags & SGTTY_SET) + { + SET_SPECIAL (ttybuff.sgttyb.sg_erase, rl_rubout); + SET_SPECIAL (ttybuff.sgttyb.sg_kill, rl_unix_line_discard); + } + +# if defined (TIOCGLTC) + if (ttybuff.flags & LTCHARS_SET) + { + SET_SPECIAL (ttybuff.ltchars.t_werasc, rl_unix_word_rubout); + SET_SPECIAL (ttybuff.ltchars.t_lnextc, rl_quoted_insert); + } +# endif /* TIOCGLTC */ +} + +#else /* !NEW_TTY_DRIVER */ +static void +set_special_char (kmap, tiop, sc, func) + Keymap kmap; + TIOTYPE *tiop; + int sc; + rl_command_func_t *func; +{ + unsigned char uc; + + uc = tiop->c_cc[sc]; + if (uc != (unsigned char)_POSIX_VDISABLE && kmap[uc].type == ISFUNC) + kmap[uc].function = func; +} + +/* used later */ +#define RESET_SPECIAL(uc) \ + if (uc != (unsigned char)_POSIX_VDISABLE && kmap[uc].type == ISFUNC) \ + kmap[uc].function = rl_insert; + +static void +_rl_bind_tty_special_chars (kmap, ttybuff) + Keymap kmap; + TIOTYPE ttybuff; +{ + SET_SPECIAL (VERASE, rl_rubout); + SET_SPECIAL (VKILL, rl_unix_line_discard); + +# if defined (VLNEXT) && defined (TERMIOS_TTY_DRIVER) + SET_SPECIAL (VLNEXT, rl_quoted_insert); +# endif /* VLNEXT && TERMIOS_TTY_DRIVER */ + +# if defined (VWERASE) && defined (TERMIOS_TTY_DRIVER) + SET_SPECIAL (VWERASE, rl_unix_word_rubout); +# endif /* VWERASE && TERMIOS_TTY_DRIVER */ +} + +#endif /* !NEW_TTY_DRIVER */ + +/* Set the system's default editing characters to their readline equivalents + in KMAP. Should be static, now that we have rl_tty_set_default_bindings. */ +void +rltty_set_default_bindings (kmap) + Keymap kmap; +{ +#if !defined (NO_TTY_DRIVER) + TIOTYPE ttybuff; + int tty; + static int called = 0; + + tty = fileno (rl_instream); + + if (get_tty_settings (tty, &ttybuff) == 0) + _rl_bind_tty_special_chars (kmap, ttybuff); +#endif +} + +/* New public way to set the system default editing chars to their readline + equivalents. */ +void +rl_tty_set_default_bindings (kmap) + Keymap kmap; +{ + rltty_set_default_bindings (kmap); +} + +/* Rebind all of the tty special chars that readline worries about back + to self-insert. Call this before saving the current terminal special + chars with save_tty_chars(). This only works on POSIX termios or termio + systems. */ +void +rl_tty_unset_default_bindings (kmap) + Keymap kmap; +{ + /* Don't bother before we've saved the tty special chars at least once. */ + if (RL_ISSTATE(RL_STATE_TTYCSAVED) == 0) + return; + + RESET_SPECIAL (_rl_tty_chars.t_erase); + RESET_SPECIAL (_rl_tty_chars.t_kill); + +# if defined (VLNEXT) && defined (TERMIOS_TTY_DRIVER) + RESET_SPECIAL (_rl_tty_chars.t_lnext); +# endif /* VLNEXT && TERMIOS_TTY_DRIVER */ + +# if defined (VWERASE) && defined (TERMIOS_TTY_DRIVER) + RESET_SPECIAL (_rl_tty_chars.t_werase); +# endif /* VWERASE && TERMIOS_TTY_DRIVER */ +} + +#if defined (HANDLE_SIGNALS) + +#if defined (NEW_TTY_DRIVER) || defined (NO_TTY_DRIVER) +int +_rl_disable_tty_signals () +{ + return 0; +} + +int +_rl_restore_tty_signals () +{ + return 0; +} +#else + +static TIOTYPE sigstty, nosigstty; +static int tty_sigs_disabled = 0; + +int +_rl_disable_tty_signals () +{ + if (tty_sigs_disabled) + return 0; + + if (_get_tty_settings (fileno (rl_instream), &sigstty) < 0) + return -1; + + nosigstty = sigstty; + + nosigstty.c_lflag &= ~ISIG; + nosigstty.c_iflag &= ~IXON; + + if (_set_tty_settings (fileno (rl_instream), &nosigstty) < 0) + return (_set_tty_settings (fileno (rl_instream), &sigstty)); + + tty_sigs_disabled = 1; + return 0; +} + +int +_rl_restore_tty_signals () +{ + int r; + + if (tty_sigs_disabled == 0) + return 0; + + r = _set_tty_settings (fileno (rl_instream), &sigstty); + + if (r == 0) + tty_sigs_disabled = 0; + + return r; +} +#endif /* !NEW_TTY_DRIVER */ + +#endif /* HANDLE_SIGNALS */ diff --git a/external/gpl3/gdb/dist/readline/rltty.h b/external/gpl3/gdb/dist/readline/rltty.h new file mode 100644 index 000000000000..fc6662d9d824 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rltty.h @@ -0,0 +1,85 @@ +/* rltty.h - tty driver-related definitions used by some library files. */ + +/* Copyright (C) 1995 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RLTTY_H_) +#define _RLTTY_H_ + +/* Posix systems use termios and the Posix signal functions. */ +#if defined (TERMIOS_TTY_DRIVER) +# include +#endif /* TERMIOS_TTY_DRIVER */ + +/* System V machines use termio. */ +#if defined (TERMIO_TTY_DRIVER) +# include +# if !defined (TCOON) +# define TCOON 1 +# endif +#endif /* TERMIO_TTY_DRIVER */ + +/* Other (BSD) machines use sgtty. */ +#if defined (NEW_TTY_DRIVER) +# include +#endif + +#include "rlwinsize.h" + +/* Define _POSIX_VDISABLE if we are not using the `new' tty driver and + it is not already defined. It is used both to determine if a + special character is disabled and to disable certain special + characters. Posix systems should set to 0, USG systems to -1. */ +#if !defined (NEW_TTY_DRIVER) && !defined (_POSIX_VDISABLE) +# if defined (_SVR4_VDISABLE) +# define _POSIX_VDISABLE _SVR4_VDISABLE +# else +# if defined (_POSIX_VERSION) +# define _POSIX_VDISABLE 0 +# else /* !_POSIX_VERSION */ +# define _POSIX_VDISABLE -1 +# endif /* !_POSIX_VERSION */ +# endif /* !_SVR4_DISABLE */ +#endif /* !NEW_TTY_DRIVER && !_POSIX_VDISABLE */ + +typedef struct _rl_tty_chars { + unsigned char t_eof; + unsigned char t_eol; + unsigned char t_eol2; + unsigned char t_erase; + unsigned char t_werase; + unsigned char t_kill; + unsigned char t_reprint; + unsigned char t_intr; + unsigned char t_quit; + unsigned char t_susp; + unsigned char t_dsusp; + unsigned char t_start; + unsigned char t_stop; + unsigned char t_lnext; + unsigned char t_flush; + unsigned char t_status; +} _RL_TTY_CHARS; + +extern void _rl_block_sigint PARAMS((void)); +extern void _rl_release_sigint PARAMS((void)); + +#endif /* _RLTTY_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rltypedefs.h b/external/gpl3/gdb/dist/readline/rltypedefs.h new file mode 100644 index 000000000000..862bdb8e4d9a --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rltypedefs.h @@ -0,0 +1,94 @@ +/* rltypedefs.h -- Type declarations for readline functions. */ + +/* Copyright (C) 2000-2004 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#ifndef _RL_TYPEDEFS_H_ +#define _RL_TYPEDEFS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Old-style */ + +#if !defined (_FUNCTION_DEF) +# define _FUNCTION_DEF + +typedef int Function (); +typedef void VFunction (); +typedef char *CPFunction (); +typedef char **CPPFunction (); + +#endif /* _FUNCTION_DEF */ + +/* New style. */ + +#if !defined (_RL_FUNCTION_TYPEDEF) +# define _RL_FUNCTION_TYPEDEF + +/* Bindable functions */ +typedef int rl_command_func_t PARAMS((int, int)); + +/* Typedefs for the completion system */ +typedef char *rl_compentry_func_t PARAMS((const char *, int)); +typedef char **rl_completion_func_t PARAMS((const char *, int, int)); + +typedef char *rl_quote_func_t PARAMS((char *, int, char *)); +typedef char *rl_dequote_func_t PARAMS((char *, int)); + +typedef int rl_compignore_func_t PARAMS((char **)); + +typedef void rl_compdisp_func_t PARAMS((char **, int, int)); + +/* Type for input and pre-read hook functions like rl_event_hook */ +typedef int rl_hook_func_t PARAMS((void)); + +/* Input function type */ +typedef int rl_getc_func_t PARAMS((FILE *)); + +/* Generic function that takes a character buffer (which could be the readline + line buffer) and an index into it (which could be rl_point) and returns + an int. */ +typedef int rl_linebuf_func_t PARAMS((char *, int)); + +/* `Generic' function pointer typedefs */ +typedef int rl_intfunc_t PARAMS((int)); +#define rl_ivoidfunc_t rl_hook_func_t +typedef int rl_icpfunc_t PARAMS((char *)); +typedef int rl_icppfunc_t PARAMS((char **)); + +typedef void rl_voidfunc_t PARAMS((void)); +typedef void rl_vintfunc_t PARAMS((int)); +typedef void rl_vcpfunc_t PARAMS((char *)); +typedef void rl_vcppfunc_t PARAMS((char **)); + +typedef char *rl_cpvfunc_t PARAMS((void)); +typedef char *rl_cpifunc_t PARAMS((int)); +typedef char *rl_cpcpfunc_t PARAMS((char *)); +typedef char *rl_cpcppfunc_t PARAMS((char **)); + +#endif /* _RL_FUNCTION_TYPEDEF */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RL_TYPEDEFS_H_ */ diff --git a/external/gpl3/gdb/dist/readline/rlwinsize.h b/external/gpl3/gdb/dist/readline/rlwinsize.h new file mode 100644 index 000000000000..7838154d0233 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/rlwinsize.h @@ -0,0 +1,57 @@ +/* rlwinsize.h -- an attempt to isolate some of the system-specific defines + for `struct winsize' and TIOCGWINSZ. */ + +/* Copyright (C) 1997 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RLWINSIZE_H_) +#define _RLWINSIZE_H_ + +#if defined (HAVE_CONFIG_H) +# include "config.h" +#endif + +/* Try to find the definitions of `struct winsize' and TIOGCWINSZ */ + +#if defined (GWINSZ_IN_SYS_IOCTL) && !defined (TIOCGWINSZ) +# include +#endif /* GWINSZ_IN_SYS_IOCTL && !TIOCGWINSZ */ + +#if defined (STRUCT_WINSIZE_IN_TERMIOS) && !defined (STRUCT_WINSIZE_IN_SYS_IOCTL) +# include +#endif /* STRUCT_WINSIZE_IN_TERMIOS && !STRUCT_WINSIZE_IN_SYS_IOCTL */ + +/* Not in either of the standard places, look around. */ +#if !defined (STRUCT_WINSIZE_IN_TERMIOS) && !defined (STRUCT_WINSIZE_IN_SYS_IOCTL) +# if defined (HAVE_SYS_STREAM_H) +# include +# endif /* HAVE_SYS_STREAM_H */ +# if defined (HAVE_SYS_PTEM_H) /* SVR4.2, at least, has it here */ +# include +# define _IO_PTEM_H /* work around SVR4.2 1.1.4 bug */ +# endif /* HAVE_SYS_PTEM_H */ +# if defined (HAVE_SYS_PTE_H) /* ??? */ +# include +# endif /* HAVE_SYS_PTE_H */ +#endif /* !STRUCT_WINSIZE_IN_TERMIOS && !STRUCT_WINSIZE_IN_SYS_IOCTL */ + +#endif /* _RL_WINSIZE_H */ + diff --git a/external/gpl3/gdb/dist/readline/savestring.c b/external/gpl3/gdb/dist/readline/savestring.c new file mode 100644 index 000000000000..820428d88811 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/savestring.c @@ -0,0 +1,37 @@ +/* savestring.c */ + +/* Copyright (C) 1998,2003 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#include +#ifdef HAVE_STRING_H +# include +#endif +#include "xmalloc.h" + +/* Backwards compatibility, now that savestring has been removed from + all `public' readline header files. */ +char * +savestring (s) + const char *s; +{ + return ((char *)strcpy ((char *)xmalloc (1 + strlen (s)), (s))); +} diff --git a/external/gpl3/gdb/dist/readline/search.c b/external/gpl3/gdb/dist/readline/search.c new file mode 100644 index 000000000000..8013916c20ea --- /dev/null +++ b/external/gpl3/gdb/dist/readline/search.c @@ -0,0 +1,572 @@ +/* search.c - code for non-incremental searching in emacs and vi modes. */ + +/* Copyright (C) 1992-2005 Free Software Foundation, Inc. + + This file is part of the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif + +#include "rldefs.h" +#include "rlmbutil.h" + +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +#ifdef abs +# undef abs +#endif +#define abs(x) (((x) >= 0) ? (x) : -(x)) + +_rl_search_cxt *_rl_nscxt = 0; + +extern HIST_ENTRY *_rl_saved_line_for_history; + +/* Functions imported from the rest of the library. */ +extern int _rl_free_history_entry PARAMS((HIST_ENTRY *)); + +static char *noninc_search_string = (char *) NULL; +static int noninc_history_pos; + +static char *prev_line_found = (char *) NULL; + +static int rl_history_search_len; +static int rl_history_search_pos; +static char *history_search_string; +static int history_string_size; + +static UNDO_LIST *noninc_saved_undo_list; +static void make_history_line_current PARAMS((HIST_ENTRY *)); +static int noninc_search_from_pos PARAMS((char *, int, int)); +static int noninc_dosearch PARAMS((char *, int)); +static int noninc_search PARAMS((int, int)); +static int rl_history_search_internal PARAMS((int, int)); +static void rl_history_search_reinit PARAMS((void)); + +static _rl_search_cxt *_rl_nsearch_init PARAMS((int, int)); +static int _rl_nsearch_cleanup PARAMS((_rl_search_cxt *, int)); +static void _rl_nsearch_abort PARAMS((_rl_search_cxt *)); +static int _rl_nsearch_dispatch PARAMS((_rl_search_cxt *, int)); + +/* Make the data from the history entry ENTRY be the contents of the + current line. This doesn't do anything with rl_point; the caller + must set it. */ +static void +make_history_line_current (entry) + HIST_ENTRY *entry; +{ + _rl_replace_text (entry->line, 0, rl_end); + _rl_fix_point (1); +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + /* POSIX.2 says that the `U' command doesn't affect the copy of any + command lines to the edit line. We're going to implement that by + making the undo list start after the matching line is copied to the + current editing buffer. */ + rl_free_undo_list (); +#endif + + if (_rl_saved_line_for_history) + _rl_free_history_entry (_rl_saved_line_for_history); + _rl_saved_line_for_history = (HIST_ENTRY *)NULL; +} + +/* Search the history list for STRING starting at absolute history position + POS. If STRING begins with `^', the search must match STRING at the + beginning of a history line, otherwise a full substring match is performed + for STRING. DIR < 0 means to search backwards through the history list, + DIR >= 0 means to search forward. */ +static int +noninc_search_from_pos (string, pos, dir) + char *string; + int pos, dir; +{ + int ret, old; + + if (pos < 0) + return -1; + + old = where_history (); + if (history_set_pos (pos) == 0) + return -1; + + RL_SETSTATE(RL_STATE_SEARCH); + if (*string == '^') + ret = history_search_prefix (string + 1, dir); + else + ret = history_search (string, dir); + RL_UNSETSTATE(RL_STATE_SEARCH); + + if (ret != -1) + ret = where_history (); + + history_set_pos (old); + return (ret); +} + +/* Search for a line in the history containing STRING. If DIR is < 0, the + search is backwards through previous entries, else through subsequent + entries. Returns 1 if the search was successful, 0 otherwise. */ +static int +noninc_dosearch (string, dir) + char *string; + int dir; +{ + int oldpos, pos; + HIST_ENTRY *entry; + + if (string == 0 || *string == '\0' || noninc_history_pos < 0) + { + rl_ding (); + return 0; + } + + pos = noninc_search_from_pos (string, noninc_history_pos + dir, dir); + if (pos == -1) + { + /* Search failed, current history position unchanged. */ + rl_maybe_unsave_line (); + rl_clear_message (); + rl_point = 0; + rl_ding (); + return 0; + } + + noninc_history_pos = pos; + + oldpos = where_history (); + history_set_pos (noninc_history_pos); + entry = current_history (); +#if defined (VI_MODE) + if (rl_editing_mode != vi_mode) +#endif + history_set_pos (oldpos); + + make_history_line_current (entry); + + rl_point = 0; + rl_mark = rl_end; + + rl_clear_message (); + return 1; +} + +static _rl_search_cxt * +_rl_nsearch_init (dir, pchar) + int dir, pchar; +{ + _rl_search_cxt *cxt; + char *p; + + cxt = _rl_scxt_alloc (RL_SEARCH_NSEARCH, 0); + if (dir < 0) + cxt->sflags |= SF_REVERSE; /* not strictly needed */ + + cxt->direction = dir; + cxt->history_pos = cxt->save_line; + + rl_maybe_save_line (); + + /* Clear the undo list, since reading the search string should create its + own undo list, and the whole list will end up being freed when we + finish reading the search string. */ + rl_undo_list = 0; + + /* Use the line buffer to read the search string. */ + rl_line_buffer[0] = 0; + rl_end = rl_point = 0; + + p = _rl_make_prompt_for_search (pchar ? pchar : ':'); + rl_message (p, 0, 0); + free (p); + + RL_SETSTATE(RL_STATE_NSEARCH); + + _rl_nscxt = cxt; + + return cxt; +} + +static int +_rl_nsearch_cleanup (cxt, r) + _rl_search_cxt *cxt; + int r; +{ + _rl_scxt_dispose (cxt, 0); + _rl_nscxt = 0; + + RL_UNSETSTATE(RL_STATE_NSEARCH); + + return (r != 1); +} + +static void +_rl_nsearch_abort (cxt) + _rl_search_cxt *cxt; +{ + rl_maybe_unsave_line (); + rl_clear_message (); + rl_point = cxt->save_point; + rl_mark = cxt->save_mark; + rl_restore_prompt (); + + RL_UNSETSTATE (RL_STATE_NSEARCH); +} + +/* Process just-read character C according to search context CXT. Return -1 + if the caller should abort the search, 0 if we should break out of the + loop, and 1 if we should continue to read characters. */ +static int +_rl_nsearch_dispatch (cxt, c) + _rl_search_cxt *cxt; + int c; +{ + switch (c) + { + case CTRL('W'): + rl_unix_word_rubout (1, c); + break; + + case CTRL('U'): + rl_unix_line_discard (1, c); + break; + + case RETURN: + case NEWLINE: + return 0; + + case CTRL('H'): + case RUBOUT: + if (rl_point == 0) + { + _rl_nsearch_abort (cxt); + return -1; + } + _rl_rubout_char (1, c); + break; + + case CTRL('C'): + case CTRL('G'): + rl_ding (); + _rl_nsearch_abort (cxt); + return -1; + + default: +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_insert_text (cxt->mb); + else +#endif + _rl_insert_char (1, c); + break; + } + + (*rl_redisplay_function) (); + return 1; +} + +/* Perform one search according to CXT, using NONINC_SEARCH_STRING. Return + -1 if the search should be aborted, any other value means to clean up + using _rl_nsearch_cleanup (). Returns 1 if the search was successful, + 0 otherwise. */ +static int +_rl_nsearch_dosearch (cxt) + _rl_search_cxt *cxt; +{ + rl_mark = cxt->save_mark; + + /* If rl_point == 0, we want to re-use the previous search string and + start from the saved history position. If there's no previous search + string, punt. */ + if (rl_point == 0) + { + if (noninc_search_string == 0) + { + rl_ding (); + rl_restore_prompt (); + RL_UNSETSTATE (RL_STATE_NSEARCH); + return -1; + } + } + else + { + /* We want to start the search from the current history position. */ + noninc_history_pos = cxt->save_line; + FREE (noninc_search_string); + noninc_search_string = savestring (rl_line_buffer); + + /* If we don't want the subsequent undo list generated by the search + matching a history line to include the contents of the search string, + we need to clear rl_line_buffer here. For now, we just clear the + undo list generated by reading the search string. (If the search + fails, the old undo list will be restored by rl_maybe_unsave_line.) */ + rl_free_undo_list (); + } + + rl_restore_prompt (); + return (noninc_dosearch (noninc_search_string, cxt->direction)); +} + +/* Search non-interactively through the history list. DIR < 0 means to + search backwards through the history of previous commands; otherwise + the search is for commands subsequent to the current position in the + history list. PCHAR is the character to use for prompting when reading + the search string; if not specified (0), it defaults to `:'. */ +static int +noninc_search (dir, pchar) + int dir; + int pchar; +{ + _rl_search_cxt *cxt; + int c, r; + + cxt = _rl_nsearch_init (dir, pchar); + + if (RL_ISSTATE (RL_STATE_CALLBACK)) + return (0); + + /* Read the search string. */ + r = 0; + while (1) + { + c = _rl_search_getchar (cxt); + + if (c == 0) + break; + + r = _rl_nsearch_dispatch (cxt, c); + if (r < 0) + return 1; + else if (r == 0) + break; + } + + r = _rl_nsearch_dosearch (cxt); + return ((r >= 0) ? _rl_nsearch_cleanup (cxt, r) : (r != 1)); +} + +/* Search forward through the history list for a string. If the vi-mode + code calls this, KEY will be `?'. */ +int +rl_noninc_forward_search (count, key) + int count, key; +{ + return noninc_search (1, (key == '?') ? '?' : 0); +} + +/* Reverse search the history list for a string. If the vi-mode code + calls this, KEY will be `/'. */ +int +rl_noninc_reverse_search (count, key) + int count, key; +{ + return noninc_search (-1, (key == '/') ? '/' : 0); +} + +/* Search forward through the history list for the last string searched + for. If there is no saved search string, abort. */ +int +rl_noninc_forward_search_again (count, key) + int count, key; +{ + int r; + + if (!noninc_search_string) + { + rl_ding (); + return (-1); + } + r = noninc_dosearch (noninc_search_string, 1); + return (r != 1); +} + +/* Reverse search in the history list for the last string searched + for. If there is no saved search string, abort. */ +int +rl_noninc_reverse_search_again (count, key) + int count, key; +{ + int r; + + if (!noninc_search_string) + { + rl_ding (); + return (-1); + } + r = noninc_dosearch (noninc_search_string, -1); + return (r != 1); +} + +#if defined (READLINE_CALLBACKS) +int +_rl_nsearch_callback (cxt) + _rl_search_cxt *cxt; +{ + int c, r; + + c = _rl_search_getchar (cxt); + r = _rl_nsearch_dispatch (cxt, c); + if (r != 0) + return 1; + + r = _rl_nsearch_dosearch (cxt); + return ((r >= 0) ? _rl_nsearch_cleanup (cxt, r) : (r != 1)); +} +#endif + +static int +rl_history_search_internal (count, dir) + int count, dir; +{ + HIST_ENTRY *temp; + int ret, oldpos; + + rl_maybe_save_line (); + temp = (HIST_ENTRY *)NULL; + + /* Search COUNT times through the history for a line whose prefix + matches history_search_string. When this loop finishes, TEMP, + if non-null, is the history line to copy into the line buffer. */ + while (count) + { + ret = noninc_search_from_pos (history_search_string, rl_history_search_pos + dir, dir); + if (ret == -1) + break; + + /* Get the history entry we found. */ + rl_history_search_pos = ret; + oldpos = where_history (); + history_set_pos (rl_history_search_pos); + temp = current_history (); + history_set_pos (oldpos); + + /* Don't find multiple instances of the same line. */ + if (prev_line_found && STREQ (prev_line_found, temp->line)) + continue; + prev_line_found = temp->line; + count--; + } + + /* If we didn't find anything at all, return. */ + if (temp == 0) + { + rl_maybe_unsave_line (); + rl_ding (); + /* If you don't want the saved history line (last match) to show up + in the line buffer after the search fails, change the #if 0 to + #if 1 */ +#if 0 + if (rl_point > rl_history_search_len) + { + rl_point = rl_end = rl_history_search_len; + rl_line_buffer[rl_end] = '\0'; + rl_mark = 0; + } +#else + rl_point = rl_history_search_len; /* rl_maybe_unsave_line changes it */ + rl_mark = rl_end; +#endif + return 1; + } + + /* Copy the line we found into the current line buffer. */ + make_history_line_current (temp); + + rl_point = rl_history_search_len; + rl_mark = rl_end; + + return 0; +} + +static void +rl_history_search_reinit () +{ + rl_history_search_pos = where_history (); + rl_history_search_len = rl_point; + prev_line_found = (char *)NULL; + if (rl_point) + { + if (rl_history_search_len >= history_string_size - 2) + { + history_string_size = rl_history_search_len + 2; + history_search_string = (char *)xrealloc (history_search_string, history_string_size); + } + history_search_string[0] = '^'; + strncpy (history_search_string + 1, rl_line_buffer, rl_point); + history_search_string[rl_point + 1] = '\0'; + } + _rl_free_saved_history_line (); +} + +/* Search forward in the history for the string of characters + from the start of the line to rl_point. This is a non-incremental + search. */ +int +rl_history_search_forward (count, ignore) + int count, ignore; +{ + if (count == 0) + return (0); + + if (rl_last_func != rl_history_search_forward && + rl_last_func != rl_history_search_backward) + rl_history_search_reinit (); + + if (rl_history_search_len == 0) + return (rl_get_next_history (count, ignore)); + return (rl_history_search_internal (abs (count), (count > 0) ? 1 : -1)); +} + +/* Search backward through the history for the string of characters + from the start of the line to rl_point. This is a non-incremental + search. */ +int +rl_history_search_backward (count, ignore) + int count, ignore; +{ + if (count == 0) + return (0); + + if (rl_last_func != rl_history_search_forward && + rl_last_func != rl_history_search_backward) + rl_history_search_reinit (); + + if (rl_history_search_len == 0) + return (rl_get_previous_history (count, ignore)); + return (rl_history_search_internal (abs (count), (count > 0) ? -1 : 1)); +} diff --git a/external/gpl3/gdb/dist/readline/shell.c b/external/gpl3/gdb/dist/readline/shell.c new file mode 100644 index 000000000000..346f8113d43d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/shell.c @@ -0,0 +1,208 @@ +/* shell.c -- readline utility functions that are normally provided by + bash when readline is linked as part of the shell. */ + +/* Copyright (C) 1997 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_STRING_H) +# include +#else +# include +#endif /* !HAVE_STRING_H */ + +#if defined (HAVE_LIMITS_H) +# include +#endif + +#if defined (HAVE_FCNTL_H) +#include +#endif +#if defined (HAVE_PWD_H) +#include +#endif + +#include + +#include "rlstdc.h" +#include "rlshell.h" +#include "xmalloc.h" + +#if defined (HAVE_GETPWUID) && !defined (HAVE_GETPW_DECLS) +extern struct passwd *getpwuid PARAMS((uid_t)); +#endif /* HAVE_GETPWUID && !HAVE_GETPW_DECLS */ + +#ifndef NULL +# define NULL 0 +#endif + +#ifndef CHAR_BIT +# define CHAR_BIT 8 +#endif + +/* Nonzero if the integer type T is signed. */ +#define TYPE_SIGNED(t) (! ((t) 0 < (t) -1)) + +/* Bound on length of the string representing an integer value of type T. + Subtract one for the sign bit if T is signed; + 302 / 1000 is log10 (2) rounded up; + add one for integer division truncation; + add one more for a minus sign if t is signed. */ +#define INT_STRLEN_BOUND(t) \ + ((sizeof (t) * CHAR_BIT - TYPE_SIGNED (t)) * 302 / 1000 \ + + 1 + TYPE_SIGNED (t)) + +/* All of these functions are resolved from bash if we are linking readline + as part of bash. */ + +/* Does shell-like quoting using single quotes. */ +char * +sh_single_quote (string) + char *string; +{ + register int c; + char *result, *r, *s; + + result = (char *)xmalloc (3 + (4 * strlen (string))); + r = result; + *r++ = '\''; + + for (s = string; s && (c = *s); s++) + { + *r++ = c; + + if (c == '\'') + { + *r++ = '\\'; /* insert escaped single quote */ + *r++ = '\''; + *r++ = '\''; /* start new quoted string */ + } + } + + *r++ = '\''; + *r = '\0'; + + return (result); +} + +/* Set the environment variables LINES and COLUMNS to lines and cols, + respectively. */ +void +sh_set_lines_and_columns (lines, cols) + int lines, cols; +{ + char *b; + +#if defined (HAVE_SETENV) + b = (char *)xmalloc (INT_STRLEN_BOUND (int) + 1); + sprintf (b, "%d", lines); + setenv ("LINES", b, 1); + free (b); + + b = (char *)xmalloc (INT_STRLEN_BOUND (int) + 1); + sprintf (b, "%d", cols); + setenv ("COLUMNS", b, 1); + free (b); +#else /* !HAVE_SETENV */ +# if defined (HAVE_PUTENV) + b = (char *)xmalloc (INT_STRLEN_BOUND (int) + sizeof ("LINES=") + 1); + sprintf (b, "LINES=%d", lines); + putenv (b); + + b = (char *)xmalloc (INT_STRLEN_BOUND (int) + sizeof ("COLUMNS=") + 1); + sprintf (b, "COLUMNS=%d", cols); + putenv (b); +# endif /* HAVE_PUTENV */ +#endif /* !HAVE_SETENV */ +} + +char * +sh_get_env_value (varname) + const char *varname; +{ + return ((char *)getenv (varname)); +} + +char * +sh_get_home_dir () +{ + char *home_dir; + struct passwd *entry; + + home_dir = (char *)NULL; +#if defined (HAVE_GETPWUID) + entry = getpwuid (getuid ()); + if (entry) + home_dir = entry->pw_dir; +#endif + return (home_dir); +} + +#if !defined (O_NDELAY) +# if defined (FNDELAY) +# define O_NDELAY FNDELAY +# endif +#endif + +int +sh_unset_nodelay_mode (fd) + int fd; +{ +#if defined (HAVE_FCNTL) + int flags, bflags; + + if ((flags = fcntl (fd, F_GETFL, 0)) < 0) + return -1; + + bflags = 0; + +#ifdef O_NONBLOCK + bflags |= O_NONBLOCK; +#endif + +#ifdef O_NDELAY + bflags |= O_NDELAY; +#endif + + if (flags & bflags) + { + flags &= ~bflags; + return (fcntl (fd, F_SETFL, flags)); + } +#endif + + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/shlib/Makefile.in b/external/gpl3/gdb/dist/readline/shlib/Makefile.in new file mode 100644 index 000000000000..5a4b0e24efe8 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/shlib/Makefile.in @@ -0,0 +1,462 @@ +## -*- text -*- ## +# Makefile for the GNU readline library shared library support. +# +# Copyright (C) 1998-2003 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +PACKAGE = @PACKAGE_NAME@ +VERSION = @PACKAGE_VERSION@ + +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_VERSION = @PACKAGE_VERSION@ + +RL_LIBRARY_VERSION = @LIBVERSION@ +RL_LIBRARY_NAME = readline + +datarootdir = @datarootdir@ + +srcdir = @srcdir@ +VPATH = .:@top_srcdir@ +topdir = @top_srcdir@ +BUILD_DIR = @BUILD_DIR@ + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +CC = @CC@ +RANLIB = @RANLIB@ +AR = @AR@ +ARFLAGS = @ARFLAGS@ +RM = rm -f +CP = cp +MV = mv +LN = ln + +SHELL = @MAKE_SHELL@ + +host_os = @host_os@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +includedir = @includedir@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +localedir = $(datadir)/locale + +# Support an alternate destination root directory for package building +DESTDIR = + +CFLAGS = @CFLAGS@ +LOCAL_CFLAGS = @LOCAL_CFLAGS@ -DRL_LIBRARY_VERSION='"$(RL_LIBRARY_VERSION)"' +CPPFLAGS = @CPPFLAGS@ +LDFLAGS = @LDFLAGS@ @LOCAL_LDFLAGS@ @CFLAGS@ + +DEFS = @DEFS@ @CROSS_COMPILE@ +LOCAL_DEFS = @LOCAL_DEFS@ + +# +# These values are generated for configure by ${topdir}/support/shobj-conf. +# If your system is not supported by that script, but includes facilities for +# dynamic loading of shared objects, please update the script and send the +# changes to bash-maintainers@gnu.org. +# +SHOBJ_CC = @SHOBJ_CC@ +SHOBJ_CFLAGS = @SHOBJ_CFLAGS@ +SHOBJ_LD = @SHOBJ_LD@ + +SHOBJ_LDFLAGS = @SHOBJ_LDFLAGS@ +SHOBJ_XLDFLAGS = @SHOBJ_XLDFLAGS@ +SHOBJ_LIBS = @SHOBJ_LIBS@ + +SHLIB_XLDFLAGS = @LDFLAGS@ @SHLIB_XLDFLAGS@ +SHLIB_LIBS = @SHLIB_LIBS@ + +SHLIB_DOT = @SHLIB_DOT@ +SHLIB_LIBPREF = @SHLIB_LIBPREF@ +SHLIB_LIBSUFF = @SHLIB_LIBSUFF@ + +SHLIB_LIBVERSION = @SHLIB_LIBVERSION@ +SHLIB_DLLVERSION = @SHLIB_DLLVERSION@ + +SHLIB_STATUS = @SHLIB_STATUS@ + +TERMCAP_LIB = @TERMCAP_LIB@ + +# shared library versioning +SHLIB_MAJOR= @SHLIB_MAJOR@ +# shared library systems like SVR4's do not use minor versions +SHLIB_MINOR= .@SHLIB_MINOR@ + +# For libraries which include headers from other libraries. +INCLUDES = -I. -I.. -I$(topdir) + +CCFLAGS = $(DEFS) $(LOCAL_DEFS) $(CPPFLAGS) $(INCLUDES) $(LOCAL_CFLAGS) $(CFLAGS) + +.SUFFIXES: .so + +.c.so: + ${RM} $@ + $(SHOBJ_CC) -c $(CCFLAGS) $(SHOBJ_CFLAGS) -o $*.o $< + $(MV) $*.o $@ + +# The name of the main library target. + +SHARED_READLINE = $(SHLIB_LIBPREF)readline$(SHLIB_DOT)$(SHLIB_LIBVERSION) +SHARED_HISTORY = $(SHLIB_LIBPREF)history$(SHLIB_DOT)$(SHLIB_LIBVERSION) +SHARED_LIBS = $(SHARED_READLINE) $(SHARED_HISTORY) + +WCWIDTH_OBJ = @WCWIDTH_OBJ@ + +# The C code source files for this library. +CSOURCES = $(topdir)/readline.c $(topdir)/funmap.c $(topdir)/keymaps.c \ + $(topdir)/vi_mode.c $(topdir)/parens.c $(topdir)/rltty.c \ + $(topdir)/complete.c $(topdir)/bind.c $(topdir)/isearch.c \ + $(topdir)/display.c $(topdir)/signals.c $(topdir)/emacs_keymap.c \ + $(topdir)/vi_keymap.c $(topdir)/util.c $(topdir)/kill.c \ + $(topdir)/undo.c $(topdir)/macro.c $(topdir)/input.c \ + $(topdir)/callback.c $(topdir)/terminal.c $(topdir)/xmalloc.c \ + $(topdir)/history.c $(topdir)/histsearch.c $(topdir)/histexpand.c \ + $(topdir)/histfile.c $(topdir)/nls.c $(topdir)/search.c \ + $(topdir)/shell.c $(topdir)/savestring.c $(topdir)/tilde.c \ + $(topdir)/text.c $(topdir)/misc.c $(topdir)/compat.c \ + $(topdir)/mbutil.c $(topdir)/support/wcwidth.c + +# The header files for this library. +HSOURCES = readline.h rldefs.h chardefs.h keymaps.h history.h histlib.h \ + posixstat.h posixdir.h posixjmp.h tilde.h rlconf.h rltty.h \ + ansi_stdlib.h tcap.h xmalloc.h rlprivate.h rlshell.h rlmbutil.h + +SHARED_HISTOBJ = history.so histexpand.so histfile.so histsearch.so shell.so \ + mbutil.so +SHARED_TILDEOBJ = tilde.so +SHARED_OBJ = readline.so vi_mode.so funmap.so keymaps.so parens.so search.so \ + rltty.so complete.so bind.so isearch.so display.so signals.so \ + util.so kill.so undo.so macro.so input.so callback.so terminal.so \ + text.so nls.so misc.so xmalloc.so $(SHARED_HISTOBJ) $(SHARED_TILDEOBJ) \ + compat.so $(WCWIDTH_OBJ) + +########################################################################## + +all: $(SHLIB_STATUS) + +supported: $(SHARED_LIBS) + +unsupported: + @echo "Your system and compiler (${host_os}-${CC}) are not supported by the" + @echo "${topdir}/support/shobj-conf script." + @echo "If your operating system provides facilities for creating" + @echo "shared libraries, please update the script and re-run configure." + @echo "Please send the changes you made to bash-maintainers@gnu.org" + @echo "for inclusion in future bash and readline releases." + +$(SHARED_READLINE): $(SHARED_OBJ) + $(RM) $@ + $(SHOBJ_LD) ${SHOBJ_LDFLAGS} ${SHLIB_XLDFLAGS} -o $@ $(SHARED_OBJ) $(SHLIB_LIBS) + +$(SHARED_HISTORY): $(SHARED_HISTOBJ) xmalloc.so + $(RM) $@ + $(SHOBJ_LD) ${SHOBJ_LDFLAGS} ${SHLIB_XLDFLAGS} -o $@ $(SHARED_HISTOBJ) xmalloc.so $(SHLIB_LIBS) + +wcwidth.o: $(srcdir)/support/wcwidth.c + $(RM) $@ + $(SHOBJ_CC) -c $(CCFLAGS) $(SHOBJ_FLAGS) $(srcdir)/support/wcwidth.c + +# Since tilde.c is shared between readline and bash, make sure we compile +# it with the right flags when it's built as part of readline +tilde.so: tilde.c + ${RM} $@ + $(SHOBJ_CC) -c $(CCFLAGS) $(SHOBJ_CFLAGS) -DREADLINE_LIBRARY -c -o tilde.o $(topdir)/tilde.c + $(MV) tilde.o $@ + +installdirs: $(topdir)/support/mkdirs + -$(SHELL) $(topdir)/support/mkdirs $(DESTDIR)$(libdir) + +install: installdirs $(SHLIB_STATUS) + $(SHELL) $(topdir)/support/shlib-install -O $(host_os) -d $(DESTDIR)$(libdir) -b $(DESTDIR)$(bindir) -i "$(INSTALL_DATA)" $(SHARED_HISTORY) + $(SHELL) $(topdir)/support/shlib-install -O $(host_os) -d $(DESTDIR)$(libdir) -b $(DESTDIR)$(bindir) -i "$(INSTALL_DATA)" $(SHARED_READLINE) + @echo install: you may need to run ldconfig + +uninstall: + $(SHELL) $(topdir)/support/shlib-install -O $(host_os) -d $(DESTDIR)$(libdir) -b $(DESTDIR)$(bindir) -U $(SHARED_HISTORY) + $(SHELL) $(topdir)/support/shlib-install -O $(host_os) -d $(DESTDIR)$(libdir) -b $(DESTDIR)$(bindir) -U $(SHARED_READLINE) + @echo uninstall: you may need to run ldconfig + +clean mostlyclean: force + $(RM) $(SHARED_OBJ) $(SHARED_LIBS) + +distclean maintainer-clean: clean + $(RM) Makefile + +force: + +# Tell versions [3.59,3.63) of GNU make not to export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: + +# Dependencies +bind.so: $(topdir)/ansi_stdlib.h $(topdir)/posixstat.h +bind.so: $(topdir)/rldefs.h ${BUILD_DIR}/config.h $(topdir)/rlconf.h +bind.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +bind.so: $(topdir)/rltypedefs.h +bind.so: $(topdir)/tilde.h $(topdir)/history.h +compat.so: $(topdir)/rlstdc.h +callback.so: $(topdir)/rlconf.h +callback.so: $(topdir)/rldefs.h ${BUILD_DIR}/config.h +callback.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +callback.so: $(topdir)/rltypedefs.h +callback.so: $(topdir)/tilde.h +complete.so: $(topdir)/ansi_stdlib.h posixdir.h $(topdir)/posixstat.h +complete.so: $(topdir)/rldefs.h ${BUILD_DIR}/config.h $(topdir)/rlconf.h +complete.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +complete.so: $(topdir)/rltypedefs.h +complete.so: $(topdir)/tilde.h +display.so: $(topdir)/ansi_stdlib.h $(topdir)/posixstat.h +display.so: $(topdir)/rldefs.h ${BUILD_DIR}/config.h $(topdir)/rlconf.h +display.so: $(topdir)/tcap.h +display.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +display.so: $(topdir)/rltypedefs.h +display.so: $(topdir)/tilde.h $(topdir)/history.h +funmap.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +funmap.so: $(topdir)/rltypedefs.h +funmap.so: $(topdir)/rlconf.h $(topdir)/ansi_stdlib.h +funmap.so: ${BUILD_DIR}/config.h $(topdir)/tilde.h +histexpand.so: $(topdir)/ansi_stdlib.h +histexpand.so: $(topdir)/history.h $(topdir)/histlib.h $(topdir)/rltypedefs.h +histexpand.so: ${BUILD_DIR}/config.h +histfile.so: $(topdir)/ansi_stdlib.h +histfile.so: $(topdir)/history.h $(topdir)/histlib.h $(topdir)/rltypedefs.h +histfile.so: ${BUILD_DIR}/config.h +history.so: $(topdir)/ansi_stdlib.h +history.so: $(topdir)/history.h $(topdir)/histlib.h $(topdir)/rltypedefs.h +history.so: ${BUILD_DIR}/config.h +histsearch.so: $(topdir)/ansi_stdlib.h +histsearch.so: $(topdir)/history.h $(topdir)/histlib.h $(topdir)/rltypedefs.h +histsearch.so: ${BUILD_DIR}/config.h +input.so: $(topdir)/ansi_stdlib.h +input.so: $(topdir)/rldefs.h ${BUILD_DIR}/config.h $(topdir)/rlconf.h +input.so: $(topdir)/readline.h $(topdir)/keymaps.h $(topdir)/chardefs.h +input.so: $(topdir)/rltypedefs.h +input.so: $(topdir)/tilde.h +isearch.so: $(topdir)/rldefs.h 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$(topdir)/tilde.h +vi_mode.so: $(topdir)/rltypedefs.h +xmalloc.so: ${BUILD_DIR}/config.h +xmalloc.so: $(topdir)/ansi_stdlib.h + +bind.so: $(topdir)/rlshell.h +histfile.so: $(topdir)/rlshell.h +nls.so: $(topdir)/rlshell.h +readline.so: $(topdir)/rlshell.h +shell.so: $(topdir)/rlshell.h +terminal.so: $(topdir)/rlshell.h +histexpand.so: $(topdir)/rlshell.h + +bind.so: $(topdir)/rlprivate.h +callback.so: $(topdir)/rlprivate.h +complete.so: $(topdir)/rlprivate.h +display.so: $(topdir)/rlprivate.h +input.so: $(topdir)/rlprivate.h +isearch.so: $(topdir)/rlprivate.h +kill.so: $(topdir)/rlprivate.h +macro.so: $(topdir)/rlprivate.h +mbutil.so: $(topdir)/rlprivate.h +misc.so: $(topdir)/rlprivate.h +nls.so: $(topdir)/rlprivate.h +parens.so: $(topdir)/rlprivate.h +readline.so: $(topdir)/rlprivate.h +rltty.so: $(topdir)/rlprivate.h +search.so: $(topdir)/rlprivate.h +signals.so: $(topdir)/rlprivate.h +terminal.so: $(topdir)/rlprivate.h +text.so: $(topdir)/rlprivate.h +undo.so: $(topdir)/rlprivate.h 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history.c +histsearch.so: histsearch.c diff --git a/external/gpl3/gdb/dist/readline/signals.c b/external/gpl3/gdb/dist/readline/signals.c new file mode 100644 index 000000000000..2dca03f35b5d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/signals.c @@ -0,0 +1,430 @@ +/* signals.c -- signal handling support for readline. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include /* Just for NULL. Yuck. */ +#include +#include + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +#if defined (GWINSZ_IN_SYS_IOCTL) +# include +#endif /* GWINSZ_IN_SYS_IOCTL */ + +#if defined (HANDLE_SIGNALS) +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" + +#if !defined (RETSIGTYPE) +# if defined (VOID_SIGHANDLER) +# define RETSIGTYPE void +# else +# define RETSIGTYPE int +# endif /* !VOID_SIGHANDLER */ +#endif /* !RETSIGTYPE */ + +#if defined (VOID_SIGHANDLER) +# define SIGHANDLER_RETURN return +#else +# define SIGHANDLER_RETURN return (0) +#endif + +/* This typedef is equivalent to the one for Function; it allows us + to say SigHandler *foo = signal (SIGKILL, SIG_IGN); */ +typedef RETSIGTYPE SigHandler (); + +#if defined (HAVE_POSIX_SIGNALS) +typedef struct sigaction sighandler_cxt; +# define rl_sigaction(s, nh, oh) sigaction(s, nh, oh) +#else +typedef struct { SigHandler *sa_handler; int sa_mask, sa_flags; } sighandler_cxt; +# define sigemptyset(m) +#endif /* !HAVE_POSIX_SIGNALS */ + +#ifndef SA_RESTART +# define SA_RESTART 0 +#endif + +static SigHandler *rl_set_sighandler PARAMS((int, SigHandler *, sighandler_cxt *)); +static void rl_maybe_set_sighandler PARAMS((int, SigHandler *, sighandler_cxt *)); + +/* Exported variables for use by applications. */ + +/* If non-zero, readline will install its own signal handlers for + SIGINT, SIGTERM, SIGQUIT, SIGALRM, SIGTSTP, SIGTTIN, and SIGTTOU. */ +int rl_catch_signals = 1; + +/* If non-zero, readline will install a signal handler for SIGWINCH. */ +#ifdef SIGWINCH +int rl_catch_sigwinch = 1; +#else +int rl_catch_sigwinch = 0; /* for the readline state struct in readline.c */ +#endif + +static int signals_set_flag; +static int sigwinch_set_flag; + +/* **************************************************************** */ +/* */ +/* Signal Handling */ +/* */ +/* **************************************************************** */ + +static sighandler_cxt old_int, old_term, old_alrm, old_quit; +#if defined (SIGTSTP) +static sighandler_cxt old_tstp, old_ttou, old_ttin; +#endif +#if defined (SIGWINCH) +static sighandler_cxt old_winch; +#endif + +/* Readline signal handler functions. */ + +static RETSIGTYPE +rl_signal_handler (sig) + int sig; +{ +#if defined (HAVE_POSIX_SIGNALS) + sigset_t set; +#else /* !HAVE_POSIX_SIGNALS */ +# if defined (HAVE_BSD_SIGNALS) + long omask; +# else /* !HAVE_BSD_SIGNALS */ + sighandler_cxt dummy_cxt; /* needed for rl_set_sighandler call */ +# endif /* !HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + + RL_SETSTATE(RL_STATE_SIGHANDLER); + +#if !defined (HAVE_BSD_SIGNALS) && !defined (HAVE_POSIX_SIGNALS) + /* Since the signal will not be blocked while we are in the signal + handler, ignore it until rl_clear_signals resets the catcher. */ +# if defined (SIGALRM) + if (sig == SIGINT || sig == SIGALRM) +# else + if (sig == SIGINT) +# endif + rl_set_sighandler (sig, SIG_IGN, &dummy_cxt); +#endif /* !HAVE_BSD_SIGNALS && !HAVE_POSIX_SIGNALS */ + + switch (sig) + { + case SIGINT: + rl_free_line_state (); + /* FALLTHROUGH */ + + case SIGTERM: +#if defined (SIGTSTP) + case SIGTSTP: + case SIGTTOU: + case SIGTTIN: +#endif /* SIGTSTP */ +#if defined (SIGALRM) + case SIGALRM: +#endif +#if defined (SIGQUIT) + case SIGQUIT: +#endif + rl_cleanup_after_signal (); + +#if defined (HAVE_POSIX_SIGNALS) + sigprocmask (SIG_BLOCK, (sigset_t *)NULL, &set); + sigdelset (&set, sig); +#else /* !HAVE_POSIX_SIGNALS */ +# if defined (HAVE_BSD_SIGNALS) + omask = sigblock (0); +# endif /* HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + +#if defined (__EMX__) + signal (sig, SIG_ACK); +#endif + +#if defined (HAVE_KILL) + kill (getpid (), sig); +#else + raise (sig); /* assume we have raise */ +#endif + + /* Let the signal that we just sent through. */ +#if defined (HAVE_POSIX_SIGNALS) + sigprocmask (SIG_SETMASK, &set, (sigset_t *)NULL); +#else /* !HAVE_POSIX_SIGNALS */ +# if defined (HAVE_BSD_SIGNALS) + sigsetmask (omask & ~(sigmask (sig))); +# endif /* HAVE_BSD_SIGNALS */ +#endif /* !HAVE_POSIX_SIGNALS */ + + rl_reset_after_signal (); + } + + RL_UNSETSTATE(RL_STATE_SIGHANDLER); + SIGHANDLER_RETURN; +} + +#if defined (SIGWINCH) +static RETSIGTYPE +rl_sigwinch_handler (sig) + int sig; +{ + SigHandler *oh; + +#if defined (MUST_REINSTALL_SIGHANDLERS) + sighandler_cxt dummy_winch; + + /* We don't want to change old_winch -- it holds the state of SIGWINCH + disposition set by the calling application. We need this state + because we call the application's SIGWINCH handler after updating + our own idea of the screen size. */ + rl_set_sighandler (SIGWINCH, rl_sigwinch_handler, &dummy_winch); +#endif + + RL_SETSTATE(RL_STATE_SIGHANDLER); + rl_resize_terminal (); + + /* If another sigwinch handler has been installed, call it. */ + oh = (SigHandler *)old_winch.sa_handler; + if (oh && oh != (SigHandler *)SIG_IGN && oh != (SigHandler *)SIG_DFL) + (*oh) (sig); + + RL_UNSETSTATE(RL_STATE_SIGHANDLER); + SIGHANDLER_RETURN; +} +#endif /* SIGWINCH */ + +/* Functions to manage signal handling. */ + +#if !defined (HAVE_POSIX_SIGNALS) +static int +rl_sigaction (sig, nh, oh) + int sig; + sighandler_cxt *nh, *oh; +{ + oh->sa_handler = signal (sig, nh->sa_handler); + return 0; +} +#endif /* !HAVE_POSIX_SIGNALS */ + +/* Set up a readline-specific signal handler, saving the old signal + information in OHANDLER. Return the old signal handler, like + signal(). */ +static SigHandler * +rl_set_sighandler (sig, handler, ohandler) + int sig; + SigHandler *handler; + sighandler_cxt *ohandler; +{ + sighandler_cxt old_handler; +#if defined (HAVE_POSIX_SIGNALS) + struct sigaction act; + + act.sa_handler = handler; +#if defined (SIGWINCH) + act.sa_flags = (sig == SIGWINCH) ? SA_RESTART : 0; +#else + act.sa_flags = 0; +#endif + sigemptyset (&act.sa_mask); + sigemptyset (&ohandler->sa_mask); + sigaction (sig, &act, &old_handler); +#else + old_handler.sa_handler = (SigHandler *)signal (sig, handler); +#endif /* !HAVE_POSIX_SIGNALS */ + + /* XXX -- assume we have memcpy */ + /* If rl_set_signals is called twice in a row, don't set the old handler to + rl_signal_handler, because that would cause infinite recursion. */ + if (handler != rl_signal_handler || old_handler.sa_handler != rl_signal_handler) + memcpy (ohandler, &old_handler, sizeof (sighandler_cxt)); + + return (ohandler->sa_handler); +} + +static void +rl_maybe_set_sighandler (sig, handler, ohandler) + int sig; + SigHandler *handler; + sighandler_cxt *ohandler; +{ + sighandler_cxt dummy; + SigHandler *oh; + + sigemptyset (&dummy.sa_mask); + oh = rl_set_sighandler (sig, handler, ohandler); + if (oh == (SigHandler *)SIG_IGN) + rl_sigaction (sig, ohandler, &dummy); +} + +int +rl_set_signals () +{ + sighandler_cxt dummy; + SigHandler *oh; + + if (rl_catch_signals && signals_set_flag == 0) + { + rl_maybe_set_sighandler (SIGINT, rl_signal_handler, &old_int); + rl_maybe_set_sighandler (SIGTERM, rl_signal_handler, &old_term); +#if defined (SIGQUIT) + rl_maybe_set_sighandler (SIGQUIT, rl_signal_handler, &old_quit); +#endif + +#if defined (SIGALRM) + oh = rl_set_sighandler (SIGALRM, rl_signal_handler, &old_alrm); + if (oh == (SigHandler *)SIG_IGN) + rl_sigaction (SIGALRM, &old_alrm, &dummy); +#if defined (HAVE_POSIX_SIGNALS) && defined (SA_RESTART) + /* If the application using readline has already installed a signal + handler with SA_RESTART, SIGALRM will cause reads to be restarted + automatically, so readline should just get out of the way. Since + we tested for SIG_IGN above, we can just test for SIG_DFL here. */ + if (oh != (SigHandler *)SIG_DFL && (old_alrm.sa_flags & SA_RESTART)) + rl_sigaction (SIGALRM, &old_alrm, &dummy); +#endif /* HAVE_POSIX_SIGNALS */ +#endif /* SIGALRM */ + +#if defined (SIGTSTP) + rl_maybe_set_sighandler (SIGTSTP, rl_signal_handler, &old_tstp); +#endif /* SIGTSTP */ + +#if defined (SIGTTOU) + rl_maybe_set_sighandler (SIGTTOU, rl_signal_handler, &old_ttou); +#endif /* SIGTTOU */ + +#if defined (SIGTTIN) + rl_maybe_set_sighandler (SIGTTIN, rl_signal_handler, &old_ttin); +#endif /* SIGTTIN */ + + signals_set_flag = 1; + } + +#if defined (SIGWINCH) + if (rl_catch_sigwinch && sigwinch_set_flag == 0) + { + rl_maybe_set_sighandler (SIGWINCH, rl_sigwinch_handler, &old_winch); + sigwinch_set_flag = 1; + } +#endif /* SIGWINCH */ + + return 0; +} + +int +rl_clear_signals () +{ + sighandler_cxt dummy; + + if (rl_catch_signals && signals_set_flag == 1) + { + sigemptyset (&dummy.sa_mask); + + rl_sigaction (SIGINT, &old_int, &dummy); + rl_sigaction (SIGTERM, &old_term, &dummy); +#if defined (SIGQUIT) + rl_sigaction (SIGQUIT, &old_quit, &dummy); +#endif +#if defined (SIGALRM) + rl_sigaction (SIGALRM, &old_alrm, &dummy); +#endif + +#if defined (SIGTSTP) + rl_sigaction (SIGTSTP, &old_tstp, &dummy); +#endif /* SIGTSTP */ + +#if defined (SIGTTOU) + rl_sigaction (SIGTTOU, &old_ttou, &dummy); +#endif /* SIGTTOU */ + +#if defined (SIGTTIN) + rl_sigaction (SIGTTIN, &old_ttin, &dummy); +#endif /* SIGTTIN */ + + signals_set_flag = 0; + } + +#if defined (SIGWINCH) + if (rl_catch_sigwinch && sigwinch_set_flag == 1) + { + sigemptyset (&dummy.sa_mask); + rl_sigaction (SIGWINCH, &old_winch, &dummy); + sigwinch_set_flag = 0; + } +#endif + + return 0; +} + +/* Clean up the terminal and readline state after catching a signal, before + resending it to the calling application. */ +void +rl_cleanup_after_signal () +{ + _rl_clean_up_for_exit (); + if (rl_deprep_term_function) + (*rl_deprep_term_function) (); + rl_clear_signals (); + rl_clear_pending_input (); +} + +/* Reset the terminal and readline state after a signal handler returns. */ +void +rl_reset_after_signal () +{ + if (rl_prep_term_function) + (*rl_prep_term_function) (_rl_meta_flag); + rl_set_signals (); +} + +/* Free up the readline variable line state for the current line (undo list, + any partial history entry, any keyboard macros in progress, and any + numeric arguments in process) after catching a signal, before calling + rl_cleanup_after_signal(). */ +void +rl_free_line_state () +{ + register HIST_ENTRY *entry; + + rl_free_undo_list (); + + entry = current_history (); + if (entry) + entry->data = (char *)NULL; + + _rl_kill_kbd_macro (); + rl_clear_message (); + _rl_reset_argument (); +} + +#endif /* HANDLE_SIGNALS */ diff --git a/external/gpl3/gdb/dist/readline/support/config.guess b/external/gpl3/gdb/dist/readline/support/config.guess new file mode 100755 index 000000000000..00ccf89e18b7 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/config.guess @@ -0,0 +1,1450 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +# 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +timestamp='2004-02-16' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Originally written by Per Bothner . +# Please send patches to . Submit a context +# diff and a properly formatted ChangeLog entry. +# +# This script attempts to guess a canonical system name similar to +# config.sub. If it succeeds, it prints the system name on stdout, and +# exits with 0. Otherwise, it exits with 1. +# +# The plan is that this can be called by configure scripts if you +# don't specify an explicit build system type. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit 0 ;; + --version | -v ) + echo "$version" ; exit 0 ;; + --help | --h* | -h ) + echo "$usage"; exit 0 ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +trap 'exit 1' 1 2 15 + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# Portable tmp directory creation inspired by the Autoconf team. + +set_cc_for_build=' +trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; +trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; +: ${TMPDIR=/tmp} ; + { tmp=`(umask 077 && mktemp -d -q "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || + { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || + { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || + { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; +dummy=$tmp/dummy ; +tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; +case $CC_FOR_BUILD,$HOST_CC,$CC in + ,,) echo "int x;" > $dummy.c ; + for c in cc gcc c89 c99 ; do + if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then + CC_FOR_BUILD="$c"; break ; + fi ; + done ; + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found ; + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; +esac ;' + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if (test -f /.attbin/uname) >/dev/null 2>&1 ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown +UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown +UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown +UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + +# Note: order is significant - the case branches are not exclusive. + +case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ + /usr/sbin/$sysctl 2>/dev/null || echo unknown)` + case "${UNAME_MACHINE_ARCH}" in + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + *) machine=${UNAME_MACHINE_ARCH}-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently, or will in the future. + case "${UNAME_MACHINE_ARCH}" in + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep __ELF__ >/dev/null + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "${UNAME_VERSION}" in + Debian*) + release='-gnu' + ;; + *) + release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit 0 ;; + amd64:OpenBSD:*:*) + echo x86_64-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + amiga:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + arc:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + cats:OpenBSD:*:*) + echo arm-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + hp300:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mac68k:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + macppc:OpenBSD:*:*) + echo powerpc-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvme68k:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvme88k:OpenBSD:*:*) + echo m88k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvmeppc:OpenBSD:*:*) + echo powerpc-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + pegasos:OpenBSD:*:*) + echo powerpc-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + pmax:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + sgi:OpenBSD:*:*) + echo mipseb-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + sun3:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + wgrisc:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + *:OpenBSD:*:*) + echo ${UNAME_MACHINE}-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + *:ekkoBSD:*:*) + echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} + exit 0 ;; + macppc:MirBSD:*:*) + echo powerppc-unknown-mirbsd${UNAME_RELEASE} + exit 0 ;; + *:MirBSD:*:*) + echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} + exit 0 ;; + alpha:OSF1:*:*) + if test $UNAME_RELEASE = "V4.0"; then + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + fi + # According to Compaq, /usr/sbin/psrinfo has been available on + # OSF/1 and Tru64 systems produced since 1995. I hope that + # covers most systems running today. This code pipes the CPU + # types through head -n 1, so we only detect the type of CPU 0. + ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` + case "$ALPHA_CPU_TYPE" in + "EV4 (21064)") + UNAME_MACHINE="alpha" ;; + "EV4.5 (21064)") + UNAME_MACHINE="alpha" ;; + "LCA4 (21066/21068)") + UNAME_MACHINE="alpha" ;; + "EV5 (21164)") + UNAME_MACHINE="alphaev5" ;; + "EV5.6 (21164A)") + UNAME_MACHINE="alphaev56" ;; + "EV5.6 (21164PC)") + UNAME_MACHINE="alphapca56" ;; + "EV5.7 (21164PC)") + UNAME_MACHINE="alphapca57" ;; + "EV6 (21264)") + UNAME_MACHINE="alphaev6" ;; + "EV6.7 (21264A)") + UNAME_MACHINE="alphaev67" ;; + "EV6.8CB (21264C)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8AL (21264B)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8CX (21264D)") + UNAME_MACHINE="alphaev68" ;; + "EV6.9A (21264/EV69A)") + UNAME_MACHINE="alphaev69" ;; + "EV7 (21364)") + UNAME_MACHINE="alphaev7" ;; + "EV7.9 (21364A)") + UNAME_MACHINE="alphaev79" ;; + esac + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + exit 0 ;; + Alpha*:OpenVMS:*:*) + echo alpha-hp-vms + exit 0 ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead + # of the specific Alpha model? + echo alpha-pc-interix + exit 0 ;; + 21064:Windows_NT:50:3) + echo alpha-dec-winnt3.5 + exit 0 ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit 0;; + *:[Aa]miga[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-amigaos + exit 0 ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-morphos + exit 0 ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit 0 ;; + *:OS400:*:*) + echo powerpc-ibm-os400 + exit 0 ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit 0;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit 0;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "`(/bin/universe) 2>/dev/null`" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit 0 ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit 0 ;; + DRS?6000:unix:4.0:6*) + echo sparc-icl-nx6 + exit 0 ;; + DRS?6000:UNIX_SV:4.2*:7*) + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7 && exit 0 ;; + esac ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + i86pc:SunOS:5.*:*) + echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:*:*) + case "`/usr/bin/arch -k`" in + Series*|S4*) + UNAME_RELEASE=`uname -v` + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` + exit 0 ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos${UNAME_RELEASE} + exit 0 ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` + test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 + case "`/bin/arch`" in + sun3) + echo m68k-sun-sunos${UNAME_RELEASE} + ;; + sun4) + echo sparc-sun-sunos${UNAME_RELEASE} + ;; + esac + exit 0 ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos${UNAME_RELEASE} + exit 0 ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint${UNAME_RELEASE} + exit 0 ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint${UNAME_RELEASE} + exit 0 ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint${UNAME_RELEASE} + exit 0 ;; + m68k:machten:*:*) + echo m68k-apple-machten${UNAME_RELEASE} + exit 0 ;; + powerpc:machten:*:*) + echo powerpc-apple-machten${UNAME_RELEASE} + exit 0 ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit 0 ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix${UNAME_RELEASE} + exit 0 ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix${UNAME_RELEASE} + exit 0 ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix${UNAME_RELEASE} + exit 0 ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c +#ifdef __cplusplus +#include /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c \ + && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ + && exit 0 + echo mips-mips-riscos${UNAME_RELEASE} + exit 0 ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit 0 ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit 0 ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit 0 ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit 0 ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit 0 ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit 0 ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit 0 ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ + [ ${TARGET_BINARY_INTERFACE}x = x ] + then + echo m88k-dg-dgux${UNAME_RELEASE} + else + echo m88k-dg-dguxbcs${UNAME_RELEASE} + fi + else + echo i586-dg-dgux${UNAME_RELEASE} + fi + exit 0 ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit 0 ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit 0 ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit 0 ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit 0 ;; + *:IRIX*:*:*) + echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` + exit 0 ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit 0 ;; + ia64:AIX:*:*) + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} + exit 0 ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 + echo rs6000-ibm-aix3.2.5 + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit 0 ;; + *:AIX:*:[45]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${IBM_ARCH}-ibm-aix${IBM_REV} + exit 0 ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit 0 ;; + ibmrt:4.4BSD:*|romp-ibm:BSD:*) + echo romp-ibm-bsd4.4 + exit 0 ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to + exit 0 ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit 0 ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit 0 ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit 0 ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit 0 ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + case "${UNAME_MACHINE}" in + 9000/31? ) HP_ARCH=m68000 ;; + 9000/[34]?? ) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` + sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` + case "${sc_cpu_version}" in + 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 + 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "${sc_kernel_bits}" in + 32) HP_ARCH="hppa2.0n" ;; + 64) HP_ARCH="hppa2.0w" ;; + '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 + esac ;; + esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + + #define _HPUX_SOURCE + #include + #include + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + test -z "$HP_ARCH" && HP_ARCH=hppa + fi ;; + esac + if [ ${HP_ARCH} = "hppa2.0w" ] + then + # avoid double evaluation of $set_cc_for_build + test -n "$CC_FOR_BUILD" || eval $set_cc_for_build + if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null + then + HP_ARCH="hppa2.0w" + else + HP_ARCH="hppa64" + fi + fi + echo ${HP_ARCH}-hp-hpux${HPUX_REV} + exit 0 ;; + ia64:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + echo ia64-hp-hpux${HPUX_REV} + exit 0 ;; + 3050*:HI-UX:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 + echo unknown-hitachi-hiuxwe2 + exit 0 ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) + echo hppa1.1-hp-bsd + exit 0 ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit 0 ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit 0 ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) + echo hppa1.1-hp-osf + exit 0 ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit 0 ;; + i*86:OSF1:*:*) + if [ -x /usr/sbin/sysversion ] ; then + echo ${UNAME_MACHINE}-unknown-osf1mk + else + echo ${UNAME_MACHINE}-unknown-osf1 + fi + exit 0 ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit 0 ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit 0 ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit 0 ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit 0 ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit 0 ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit 0 ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*[A-Z]90:*:*:*) + echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + *:UNICOS/mp:*:*) + echo nv1-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit 0 ;; + 5000:UNIX_System_V:4.*:*) + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` + echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit 0 ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} + exit 0 ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi${UNAME_RELEASE} + exit 0 ;; + *:BSD/OS:*:*) + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit 0 ;; + *:FreeBSD:*:*) + # Determine whether the default compiler uses glibc. + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + #if __GLIBC__ >= 2 + LIBC=gnu + #else + LIBC= + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` + # GNU/KFreeBSD systems have a "k" prefix to indicate we are using + # FreeBSD's kernel, but not the complete OS. + case ${LIBC} in gnu) kernel_only='k' ;; esac + echo ${UNAME_MACHINE}-unknown-${kernel_only}freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`${LIBC:+-$LIBC} + exit 0 ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit 0 ;; + i*:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit 0 ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit 0 ;; + x86:Interix*:[34]*) + echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//' + exit 0 ;; + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit 0 ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we + # UNAME_MACHINE based on the output of uname instead of i386? + echo i586-pc-interix + exit 0 ;; + i*:UWIN*:*) + echo ${UNAME_MACHINE}-pc-uwin + exit 0 ;; + p*:CYGWIN*:*) + echo powerpcle-unknown-cygwin + exit 0 ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + *:GNU:*:*) + # the GNU system + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit 0 ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu + exit 0 ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit 0 ;; + arm*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + cris:Linux:*:*) + echo cris-axis-linux-gnu + exit 0 ;; + ia64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + m68*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + mips:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips + #undef mipsel + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mipsel + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` + test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + ;; + mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips64 + #undef mips64el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mips64el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips64 + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` + test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-gnu + exit 0 ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-gnu + exit 0 ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null + if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi + echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + exit 0 ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in + PA7*) echo hppa1.1-unknown-linux-gnu ;; + PA8*) echo hppa2.0-unknown-linux-gnu ;; + *) echo hppa-unknown-linux-gnu ;; + esac + exit 0 ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-gnu + exit 0 ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo ${UNAME_MACHINE}-ibm-linux + exit 0 ;; + sh64*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + sh*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + x86_64:Linux:*:*) + echo x86_64-unknown-linux-gnu + exit 0 ;; + i*86:Linux:*:*) + # The BFD linker knows what the default object file format is, so + # first see if it will tell us. cd to the root directory to prevent + # problems with other programs or directories called `ld' in the path. + # Set LC_ALL=C to ensure ld outputs messages in English. + ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ + | sed -ne '/supported targets:/!d + s/[ ][ ]*/ /g + s/.*supported targets: *// + s/ .*// + p'` + case "$ld_supported_targets" in + elf32-i386) + TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" + ;; + a.out-i386-linux) + echo "${UNAME_MACHINE}-pc-linux-gnuaout" + exit 0 ;; + coff-i386) + echo "${UNAME_MACHINE}-pc-linux-gnucoff" + exit 0 ;; + "") + # Either a pre-BFD a.out linker (linux-gnuoldld) or + # one that does not give us useful --help. + echo "${UNAME_MACHINE}-pc-linux-gnuoldld" + exit 0 ;; + esac + # Determine whether the default compiler is a.out or elf + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + #ifdef __ELF__ + # ifdef __GLIBC__ + # if __GLIBC__ >= 2 + LIBC=gnu + # else + LIBC=gnulibc1 + # endif + # else + LIBC=gnulibc1 + # endif + #else + #ifdef __INTEL_COMPILER + LIBC=gnu + #else + LIBC=gnuaout + #endif + #endif + #ifdef __dietlibc__ + LIBC=dietlibc + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` + test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 + test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 + ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit 0 ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit 0 ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo ${UNAME_MACHINE}-pc-os2-emx + exit 0 ;; + i*86:XTS-300:*:STOP) + echo ${UNAME_MACHINE}-unknown-stop + exit 0 ;; + i*86:atheos:*:*) + echo ${UNAME_MACHINE}-unknown-atheos + exit 0 ;; + i*86:syllable:*:*) + echo ${UNAME_MACHINE}-pc-syllable + exit 0 ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + i*86:*DOS:*:*) + echo ${UNAME_MACHINE}-pc-msdosdjgpp + exit 0 ;; + i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) + UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} + else + echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} + fi + exit 0 ;; + i*86:*:5:[78]*) + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} + exit 0 ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then + UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo ${UNAME_MACHINE}-pc-sco$UNAME_REL + else + echo ${UNAME_MACHINE}-pc-sysv32 + fi + exit 0 ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i386. + echo i386-pc-msdosdjgpp + exit 0 ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit 0 ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit 0 ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 + fi + exit 0 ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit 0 ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit 0 ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit 0 ;; + M68*:*:R3V[567]*:*) + test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; + 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && echo i486-ncr-sysv4.3${OS_REL} && exit 0 + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && echo i486-ncr-sysv4 && exit 0 ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit 0 ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv${UNAME_RELEASE} + exit 0 ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit 0 ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit 0 ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=`(uname -p) 2>/dev/null` + echo ${UNAME_MACHINE}-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit 0 ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says + echo i586-unisys-sysv4 + exit 0 ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit 0 ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit 0 ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit 0 ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux${UNAME_RELEASE} + exit 0 ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit 0 ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then + echo mips-nec-sysv${UNAME_RELEASE} + else + echo mips-unknown-sysv${UNAME_RELEASE} + fi + exit 0 ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit 0 ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit 0 ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit 0 ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit 0 ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux${UNAME_RELEASE} + exit 0 ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux${UNAME_RELEASE} + exit 0 ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody${UNAME_RELEASE} + exit 0 ;; + *:Rhapsody:*:*) + echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} + exit 0 ;; + *:Darwin:*:*) + case `uname -p` in + *86) UNAME_PROCESSOR=i686 ;; + powerpc) UNAME_PROCESSOR=powerpc ;; + esac + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit 0 ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=`uname -p` + if test "$UNAME_PROCESSOR" = "x86"; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} + exit 0 ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit 0 ;; + NSR-?:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk${UNAME_RELEASE} + exit 0 ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit 0 ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit 0 ;; + DS/*:UNIX_System_V:*:*) + echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} + exit 0 ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + if test "$cputype" = "386"; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo ${UNAME_MACHINE}-unknown-plan9 + exit 0 ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit 0 ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit 0 ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit 0 ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit 0 ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit 0 ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit 0 ;; + SEI:*:*:SEIUX) + echo mips-sei-seiux${UNAME_RELEASE} + exit 0 ;; + *:DragonFly:*:*) + echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` + exit 0 ;; +esac + +#echo '(No uname command or uname output not recognized.)' 1>&2 +#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 + +eval $set_cc_for_build +cat >$dummy.c < +# include +#endif +main () +{ +#if defined (sony) +#if defined (MIPSEB) + /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, + I don't know.... */ + printf ("mips-sony-bsd\n"); exit (0); +#else +#include + printf ("m68k-sony-newsos%s\n", +#ifdef NEWSOS4 + "4" +#else + "" +#endif + ); exit (0); +#endif +#endif + +#if defined (__arm) && defined (__acorn) && defined (__unix) + printf ("arm-acorn-riscix"); exit (0); +#endif + +#if defined (hp300) && !defined (hpux) + printf ("m68k-hp-bsd\n"); exit (0); +#endif + +#if defined (NeXT) +#if !defined (__ARCHITECTURE__) +#define __ARCHITECTURE__ "m68k" +#endif + int version; + version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; + if (version < 4) + printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); + else + printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); + exit (0); +#endif + +#if defined (MULTIMAX) || defined (n16) +#if defined (UMAXV) + printf ("ns32k-encore-sysv\n"); exit (0); +#else +#if defined (CMU) + printf ("ns32k-encore-mach\n"); exit (0); +#else + printf ("ns32k-encore-bsd\n"); exit (0); +#endif +#endif +#endif + +#if defined (__386BSD__) + printf ("i386-pc-bsd\n"); exit (0); +#endif + +#if defined (sequent) +#if defined (i386) + printf ("i386-sequent-dynix\n"); exit (0); +#endif +#if defined (ns32000) + printf ("ns32k-sequent-dynix\n"); exit (0); +#endif +#endif + +#if defined (_SEQUENT_) + struct utsname un; + + uname(&un); + + if (strncmp(un.version, "V2", 2) == 0) { + printf ("i386-sequent-ptx2\n"); exit (0); + } + if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ + printf ("i386-sequent-ptx1\n"); exit (0); + } + printf ("i386-sequent-ptx\n"); exit (0); + +#endif + +#if defined (vax) +# if !defined (ultrix) +# include +# if defined (BSD) +# if BSD == 43 + printf ("vax-dec-bsd4.3\n"); exit (0); +# else +# if BSD == 199006 + printf ("vax-dec-bsd4.3reno\n"); exit (0); +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# endif +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# else + printf ("vax-dec-ultrix\n"); exit (0); +# endif +#endif + +#if defined (alliant) && defined (i860) + printf ("i860-alliant-bsd\n"); exit (0); +#endif + + exit (1); +} +EOF + +$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && exit 0 + +# Apollos put the system type in the environment. + +test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } + +# Convex versions that predate uname can use getsysinfo(1) + +if [ -x /usr/convex/getsysinfo ] +then + case `getsysinfo -f cpu_type` in + c1*) + echo c1-convex-bsd + exit 0 ;; + c2*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit 0 ;; + c34*) + echo c34-convex-bsd + exit 0 ;; + c38*) + echo c38-convex-bsd + exit 0 ;; + c4*) + echo c4-convex-bsd + exit 0 ;; + esac +fi + +cat >&2 < in order to provide the needed +information to handle your system. + +config.guess timestamp = $timestamp + +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null` + +hostinfo = `(hostinfo) 2>/dev/null` +/bin/universe = `(/bin/universe) 2>/dev/null` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` +/bin/arch = `(/bin/arch) 2>/dev/null` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` + +UNAME_MACHINE = ${UNAME_MACHINE} +UNAME_RELEASE = ${UNAME_RELEASE} +UNAME_SYSTEM = ${UNAME_SYSTEM} +UNAME_VERSION = ${UNAME_VERSION} +EOF + +exit 1 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/external/gpl3/gdb/dist/readline/support/config.rpath b/external/gpl3/gdb/dist/readline/support/config.rpath new file mode 100755 index 000000000000..fa24bfc2d785 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/config.rpath @@ -0,0 +1,548 @@ +#! /bin/sh +# Output a system dependent set of variables, describing how to set the +# run time search path of shared libraries in an executable. +# +# Copyright 1996-2003 Free Software Foundation, Inc. +# Taken from GNU libtool, 2001 +# Originally by Gordon Matzigkeit , 1996 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. +# +# The first argument passed to this file is the canonical host specification, +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# The environment variables CC, GCC, LDFLAGS, LD, with_gnu_ld +# should be set by the caller. +# +# The set of defined variables is at the end of this script. + +# Known limitations: +# - On IRIX 6.5 with CC="cc", the run time search patch must not be longer +# than 256 bytes, otherwise the compiler driver will dump core. The only +# known workaround is to choose shorter directory names for the build +# directory and/or the installation directory. + +# All known linkers require a `.a' archive for static linking (except M$VC, +# which needs '.lib'). +libext=a +shrext=.so + +host="$1" +host_cpu=`echo "$host" | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` +host_vendor=`echo "$host" | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'` +host_os=`echo "$host" | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` + +# Code taken from libtool.m4's AC_LIBTOOL_PROG_COMPILER_PIC. + +wl= +if test "$GCC" = yes; then + wl='-Wl,' +else + case "$host_os" in + aix*) + wl='-Wl,' + ;; + mingw* | pw32* | os2*) + ;; + hpux9* | hpux10* | hpux11*) + wl='-Wl,' + ;; + irix5* | irix6* | nonstopux*) + wl='-Wl,' + ;; + newsos6) + ;; + linux*) + case $CC in + icc|ecc) + wl='-Wl,' + ;; + ccc) + wl='-Wl,' + ;; + esac + ;; + osf3* | osf4* | osf5*) + wl='-Wl,' + ;; + sco3.2v5*) + ;; + solaris*) + wl='-Wl,' + ;; + sunos4*) + wl='-Qoption ld ' + ;; + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + wl='-Wl,' + ;; + sysv4*MP*) + ;; + uts4*) + ;; + esac +fi + +# Code taken from libtool.m4's AC_LIBTOOL_PROG_LD_SHLIBS. + +hardcode_libdir_flag_spec= +hardcode_libdir_separator= +hardcode_direct=no +hardcode_minus_L=no + +case "$host_os" in + cygwin* | mingw* | pw32*) + # FIXME: the MSVC++ port hasn't been tested in a loooong time + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + if test "$GCC" != yes; then + with_gnu_ld=no + fi + ;; + openbsd*) + with_gnu_ld=no + ;; +esac + +ld_shlibs=yes +if test "$with_gnu_ld" = yes; then + case "$host_os" in + aix3* | aix4* | aix5*) + # On AIX/PPC, the GNU linker is very broken + if test "$host_cpu" != ia64; then + ld_shlibs=no + fi + ;; + amigaos*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + # Samuel A. Falvo II reports + # that the semantics of dynamic libraries on AmigaOS, at least up + # to version 4, is to share data among multiple programs linked + # with the same dynamic library. Since this doesn't match the + # behavior of shared libraries on other platforms, we can use + # them. + ld_shlibs=no + ;; + beos*) + if $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then + : + else + ld_shlibs=no + fi + ;; + cygwin* | mingw* | pw32*) + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + hardcode_libdir_flag_spec='-L$libdir' + if $LD --help 2>&1 | grep 'auto-import' > /dev/null; then + : + else + ld_shlibs=no + fi + ;; + netbsd*) + ;; + solaris* | sysv5*) + if $LD -v 2>&1 | egrep 'BFD 2\.8' > /dev/null; then + ld_shlibs=no + elif $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then + : + else + ld_shlibs=no + fi + ;; + sunos4*) + hardcode_direct=yes + ;; + *) + if $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then + : + else + ld_shlibs=no + fi + ;; + esac + if test "$ld_shlibs" = yes; then + # Unlike libtool, we use -rpath here, not --rpath, since the documented + # option of GNU ld is called -rpath, not --rpath. + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + fi +else + case "$host_os" in + aix3*) + # Note: this linker hardcodes the directories in LIBPATH if there + # are no directories specified by -L. + hardcode_minus_L=yes + if test "$GCC" = yes; then + # Neither direct hardcoding nor static linking is supported with a + # broken collect2. + hardcode_direct=unsupported + fi + ;; + aix4* | aix5*) + if test "$host_cpu" = ia64; then + # On IA64, the linker does run time linking by default, so we don't + # have to do anything special. + aix_use_runtimelinking=no + else + aix_use_runtimelinking=no + # Test if we are trying to use run time linking or normal + # AIX style linking. If -brtl is somewhere in LDFLAGS, we + # need to do runtime linking. + case $host_os in aix4.[23]|aix4.[23].*|aix5*) + for ld_flag in $LDFLAGS; do + if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then + aix_use_runtimelinking=yes + break + fi + done + esac + fi + hardcode_direct=yes + hardcode_libdir_separator=':' + if test "$GCC" = yes; then + case $host_os in aix4.[012]|aix4.[012].*) + collect2name=`${CC} -print-prog-name=collect2` + if test -f "$collect2name" && \ + strings "$collect2name" | grep resolve_lib_name >/dev/null + then + # We have reworked collect2 + hardcode_direct=yes + else + # We have old collect2 + hardcode_direct=unsupported + hardcode_minus_L=yes + hardcode_libdir_flag_spec='-L$libdir' + hardcode_libdir_separator= + fi + esac + fi + # Begin _LT_AC_SYS_LIBPATH_AIX. + echo 'int main () { return 0; }' > conftest.c + ${CC} ${LDFLAGS} conftest.c -o conftest + aix_libpath=`dump -H conftest 2>/dev/null | sed -n -e '/Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/; p; } +}'` + if test -z "$aix_libpath"; then + aix_libpath=`dump -HX64 conftest 2>/dev/null | sed -n -e '/Import File Strings/,/^$/ { /^0/ { s/^0 *\(.*\)$/\1/; p; } +}'` + fi + if test -z "$aix_libpath"; then + aix_libpath="/usr/lib:/lib" + fi + rm -f conftest.c conftest + # End _LT_AC_SYS_LIBPATH_AIX. + if test "$aix_use_runtimelinking" = yes; then + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + else + if test "$host_cpu" = ia64; then + hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib' + else + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + fi + fi + ;; + amigaos*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + # see comment about different semantics on the GNU ld section + ld_shlibs=no + ;; + bsdi4*) + ;; + cygwin* | mingw* | pw32*) + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + hardcode_libdir_flag_spec=' ' + libext=lib + ;; + darwin* | rhapsody*) + if $CC -v 2>&1 | grep 'Apple' >/dev/null ; then + hardcode_direct=no + fi + ;; + dgux*) + hardcode_libdir_flag_spec='-L$libdir' + ;; + freebsd1*) + ld_shlibs=no + ;; + freebsd2.2*) + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + ;; + freebsd2*) + hardcode_direct=yes + hardcode_minus_L=yes + ;; + freebsd*) + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + ;; + hpux9*) + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + hpux10* | hpux11*) + if test "$with_gnu_ld" = no; then + case "$host_cpu" in + hppa*64*) + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=no + ;; + ia64*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_direct=no + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + *) + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + esac + fi + ;; + irix5* | irix6* | nonstopux*) + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; + netbsd*) + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + ;; + newsos6) + hardcode_direct=yes + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; + openbsd*) + hardcode_direct=yes + if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + else + case "$host_os" in + openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) + hardcode_libdir_flag_spec='-R$libdir' + ;; + *) + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + ;; + esac + fi + ;; + os2*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + ;; + osf3*) + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; + osf4* | osf5*) + if test "$GCC" = yes; then + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + else + # Both cc and cxx compiler support -rpath directly + hardcode_libdir_flag_spec='-rpath $libdir' + fi + hardcode_libdir_separator=: + ;; + sco3.2v5*) + ;; + solaris*) + hardcode_libdir_flag_spec='-R$libdir' + ;; + sunos4*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_direct=yes + hardcode_minus_L=yes + ;; + sysv4) + case $host_vendor in + sni) + hardcode_direct=yes # is this really true??? + ;; + siemens) + hardcode_direct=no + ;; + motorola) + hardcode_direct=no #Motorola manual says yes, but my tests say they lie + ;; + esac + ;; + sysv4.3*) + ;; + sysv4*MP*) + if test -d /usr/nec; then + ld_shlibs=yes + fi + ;; + sysv4.2uw2*) + hardcode_direct=yes + hardcode_minus_L=no + ;; + sysv5OpenUNIX8* | sysv5UnixWare7* | sysv5uw[78]* | unixware7*) + ;; + sysv5*) + hardcode_libdir_flag_spec= + ;; + uts4*) + hardcode_libdir_flag_spec='-L$libdir' + ;; + *) + ld_shlibs=no + ;; + esac +fi + +# Check dynamic linker characteristics +# Code taken from libtool.m4's AC_LIBTOOL_SYS_DYNAMIC_LINKER. +libname_spec='lib$name' +case "$host_os" in + aix3*) + ;; + aix4* | aix5*) + ;; + amigaos*) + ;; + beos*) + ;; + bsdi4*) + ;; + cygwin* | mingw* | pw32*) + shrext=.dll + ;; + darwin* | rhapsody*) + shrext=.dylib + ;; + dgux*) + ;; + freebsd1*) + ;; + freebsd*) + ;; + gnu*) + ;; + hpux9* | hpux10* | hpux11*) + case "$host_cpu" in + ia64*) + shrext=.so + ;; + hppa*64*) + shrext=.sl + ;; + *) + shrext=.sl + ;; + esac + ;; + irix5* | irix6* | nonstopux*) + case "$host_os" in + irix5* | nonstopux*) + libsuff= shlibsuff= + ;; + *) + case $LD in + *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") libsuff= shlibsuff= ;; + *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") libsuff=32 shlibsuff=N32 ;; + *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") libsuff=64 shlibsuff=64 ;; + *) libsuff= shlibsuff= ;; + esac + ;; + esac + ;; + linux*oldld* | linux*aout* | linux*coff*) + ;; + linux*) + ;; + netbsd*) + ;; + newsos6) + ;; + nto-qnx) + ;; + openbsd*) + ;; + os2*) + libname_spec='$name' + shrext=.dll + ;; + osf3* | osf4* | osf5*) + ;; + sco3.2v5*) + ;; + solaris*) + ;; + sunos4*) + ;; + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + ;; + sysv4*MP*) + ;; + uts4*) + ;; +esac + +sed_quote_subst='s/\(["`$\\]\)/\\\1/g' +escaped_wl=`echo "X$wl" | sed -e 's/^X//' -e "$sed_quote_subst"` +shlibext=`echo "$shrext" | sed -e 's,^\.,,'` +escaped_hardcode_libdir_flag_spec=`echo "X$hardcode_libdir_flag_spec" | sed -e 's/^X//' -e "$sed_quote_subst"` + +sed -e 's/^\([a-zA-Z0-9_]*\)=/acl_cv_\1=/' <. Submit a context +# diff and a properly formatted ChangeLog entry. +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS + $0 [OPTION] ALIAS + +Canonicalize a configuration name. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.sub ($timestamp) + +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit 0 ;; + --version | -v ) + echo "$version" ; exit 0 ;; + --help | --h* | -h ) + echo "$usage"; exit 0 ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo $1 + exit 0;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + nto-qnx* | linux-gnu* | linux-dietlibc | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | \ + kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple | -axis) + os= + basic_machine=$1 + ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 + ;; + -scout) + ;; + -wrs) + os=-vxworks + basic_machine=$1 + ;; + -chorusos*) + os=-chorusos + basic_machine=$1 + ;; + -chorusrdb) + os=-chorusrdb + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -udk*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; + -mint | -mint[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ + | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ + | c4x | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | fr30 | frv \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ + | m32r | m68000 | m68k | m88k | mcore \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ + | mips64vr | mips64vrel \ + | mips64orion | mips64orionel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | msp430 \ + | ns16k | ns32k \ + | openrisc | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ + | pyramid \ + | sh | sh[1234] | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \ + | strongarm \ + | tahoe | thumb | tic4x | tic80 | tron \ + | v850 | v850e \ + | we32k \ + | x86 | xscale | xstormy16 | xtensa \ + | z8k) + basic_machine=$basic_machine-unknown + ;; + m6811 | m68hc11 | m6812 | m68hc12) + # Motorola 68HC11/12. + basic_machine=$basic_machine-unknown + os=-none + ;; + m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) + ;; + + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* \ + | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ + | clipper-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ + | m32r-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | mcore-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ + | mips64vr-* | mips64vrel-* \ + | mips64orion-* | mips64orionel-* \ + | mips64vr4100-* | mips64vr4100el-* \ + | mips64vr4300-* | mips64vr4300el-* \ + | mips64vr5000-* | mips64vr5000el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ + | mipstx39-* | mipstx39el-* \ + | msp430-* \ + | none-* | np1-* | nv1-* | ns16k-* | ns32k-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ + | pyramid-* \ + | romp-* | rs6000-* \ + | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \ + | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \ + | tahoe-* | thumb-* \ + | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ + | tron-* \ + | v850-* | v850e-* | vax-* \ + | we32k-* \ + | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \ + | xtensa-* \ + | ymp-* \ + | z8k-*) + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 386bsd) + basic_machine=i386-unknown + os=-bsd + ;; + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + a29khif) + basic_machine=a29k-amd + os=-udi + ;; + abacus) + basic_machine=abacus-unknown + ;; + adobe68k) + basic_machine=m68010-adobe + os=-scout + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amd64) + basic_machine=x86_64-pc + ;; + amd64-*) + basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-unknown + ;; + amigaos | amigados) + basic_machine=m68k-unknown + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + os=-bsd + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | j90) + basic_machine=j90-cray + os=-unicos + ;; + cr16c) + basic_machine=cr16c-unknown + os=-elf + ;; + crds | unos) + basic_machine=m68k-crds + ;; + cris | cris-* | etrax*) + basic_machine=cris-axis + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + decsystem10* | dec10*) + basic_machine=pdp10-dec + os=-tops10 + ;; + decsystem20* | dec20*) + basic_machine=pdp10-dec + os=-tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + os=-ose + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + go32) + basic_machine=i386-pc + os=-go32 + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + h8300xray) + basic_machine=h8300-hitachi + os=-xray + ;; + h8500hms) + basic_machine=h8500-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + hppaosf) + basic_machine=hppa1.1-hp + os=-osf + ;; + hppro) + basic_machine=hppa1.1-hp + os=-proelf + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; +# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i*86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i*86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i*86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + i386mach) + basic_machine=i386-mach + os=-mach + ;; + i386-vsta | vsta) + basic_machine=i386-unknown + os=-vsta + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + mingw32) + basic_machine=i386-pc + os=-mingw32 + ;; + miniframe) + basic_machine=m68000-convergent + ;; + *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + mmix*) + basic_machine=mmix-knuth + os=-mmixware + ;; + monitor) + basic_machine=m68k-rom68k + os=-coff + ;; + morphos) + basic_machine=powerpc-unknown + os=-morphos + ;; + msdos) + basic_machine=i386-pc + os=-msdos + ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + netbsd386) + basic_machine=i386-unknown + os=-netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + os=-linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + necv70) + basic_machine=v70-nec + os=-sysv + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + mon960) + basic_machine=i960-intel + os=-mon960 + ;; + nonstopux) + basic_machine=mips-compaq + os=-nonstopux + ;; + np1) + basic_machine=np1-gould + ;; + nv1) + basic_machine=nv1-cray + os=-unicosmp + ;; + nsr-tandem) + basic_machine=nsr-tandem + ;; + op50n-* | op60c-*) + basic_machine=hppa1.1-oki + os=-proelf + ;; + or32 | or32-*) + basic_machine=or32-unknown + os=-coff + ;; + os400) + basic_machine=powerpc-ibm + os=-os400 + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + os=-ose + ;; + os68k) + basic_machine=m68k-none + os=-os68k + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pentium | p5 | k5 | k6 | nexgen | viac3) + basic_machine=i586-pc + ;; + pentiumpro | p6 | 6x86 | athlon | athlon_*) + basic_machine=i686-pc + ;; + pentiumii | pentium2 | pentiumiii | pentium3) + basic_machine=i686-pc + ;; + pentium4) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium4-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=power-ibm + ;; + ppc) basic_machine=powerpc-unknown + ;; + ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64) basic_machine=powerpc64-unknown + ;; + ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64le | powerpc64little | ppc64-le | powerpc64-little) + basic_machine=powerpc64le-unknown + ;; + ppc64le-* | powerpc64little-*) + basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + pw32) + basic_machine=i586-unknown + os=-pw32 + ;; + rom68k) + basic_machine=m68k-rom68k + os=-coff + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + s390 | s390-*) + basic_machine=s390-ibm + ;; + s390x | s390x-*) + basic_machine=s390x-ibm + ;; + sa29200) + basic_machine=a29k-amd + os=-udi + ;; + sb1) + basic_machine=mipsisa64sb1-unknown + ;; + sb1el) + basic_machine=mipsisa64sb1el-unknown + ;; + sei) + basic_machine=mips-sei + os=-seiux + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparclite-wrs | simso-wrs) + basic_machine=sparclite-wrs + os=-vxworks + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + st2000) + basic_machine=m68k-tandem + ;; + stratus) + basic_machine=i860-stratus + os=-sysv4 + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + sv1) + basic_machine=sv1-cray + os=-unicos + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + t3e) + basic_machine=alphaev5-cray + os=-unicos + ;; + t90) + basic_machine=t90-cray + os=-unicos + ;; + tic54x | c54x*) + basic_machine=tic54x-unknown + os=-coff + ;; + tic55x | c55x*) + basic_machine=tic55x-unknown + os=-coff + ;; + tic6x | c6x*) + basic_machine=tic6x-unknown + os=-coff + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + toad1) + basic_machine=pdp10-xkl + os=-tops20 + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + tpf) + basic_machine=s390x-ibm + os=-tpf + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + os=-none + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + w65*) + basic_machine=w65-wdc + os=-none + ;; + w89k-*) + basic_machine=hppa1.1-winbond + os=-proelf + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + ymp) + basic_machine=ymp-cray + os=-unicos + ;; + z8k-*-coff) + basic_machine=z8k-unknown + os=-sim + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + w89k) + basic_machine=hppa1.1-winbond + ;; + op50n) + basic_machine=hppa1.1-oki + ;; + op60c) + basic_machine=hppa1.1-oki + ;; + romp) + basic_machine=romp-ibm + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp10) + # there are many clones, so DEC is not a safe bet + basic_machine=pdp10-unknown + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sh3 | sh4 | sh[34]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparc | sparcv9 | sparcv9b) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + mac | mpw | mac-mpw) + basic_machine=m68k-apple + ;; + pmac | pmac-mpw) + basic_machine=powerpc-apple + ;; + *-unknown) + # Make sure to match an already-canonicalized machine name. + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* | -openbsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* \ + | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -linux-gnu* | -linux-uclibc* | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ + | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) + case $basic_machine in + x86-* | i*86-*) + ;; + *) + os=-nto$os + ;; + esac + ;; + -nto-qnx*) + ;; + -nto*) + os=`echo $os | sed -e 's|nto|nto-qnx|'` + ;; + -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ + | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) + ;; + -mac*) + os=`echo $os | sed -e 's|mac|macos|'` + ;; + -linux-dietlibc) + os=-linux-dietlibc + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -opened*) + os=-openedition + ;; + -os400*) + os=-os400 + ;; + -wince*) + os=-wince + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -atheos*) + os=-atheos + ;; + -syllable*) + os=-syllable + ;; + -386bsd) + os=-bsd + ;; + -ctix* | -uts*) + os=-sysv + ;; + -nova*) + os=-rtmk-nova + ;; + -ns2 ) + os=-nextstep2 + ;; + -nsk*) + os=-nsk + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -tpf*) + os=-tpf + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -ose*) + os=-ose + ;; + -es1800*) + os=-ose + ;; + -xenix) + os=-xenix + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + os=-mint + ;; + -aros*) + os=-aros + ;; + -kaos*) + os=-kaos + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + *-acorn) + os=-riscix1.2 + ;; + arm*-rebel) + os=-linux + ;; + arm*-semi) + os=-aout + ;; + c4x-* | tic4x-*) + os=-coff + ;; + # This must come before the *-dec entry. + pdp10-*) + os=-tops20 + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + # This also exists in the configure program, but was not the + # default. + # os=-sunos4 + ;; + m68*-cisco) + os=-aout + ;; + mips*-cisco) + os=-elf + ;; + mips*-*) + os=-elf + ;; + or32-*) + os=-coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-be) + os=-beos + ;; + *-ibm) + os=-aix + ;; + *-wec) + os=-proelf + ;; + *-winbond) + os=-proelf + ;; + *-oki) + os=-proelf + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=-uxpv + ;; + *-rom68k) + os=-coff + ;; + *-*bug) + os=-coff + ;; + *-apple) + os=-macos + ;; + *-atari*) + os=-mint + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -aix*) + vendor=ibm + ;; + -beos*) + vendor=be + ;; + -hpux*) + vendor=hp + ;; + -mpeix*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs* | -opened*) + vendor=ibm + ;; + -os400*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -tpf*) + vendor=ibm + ;; + -vxsim* | -vxworks* | -windiss*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -hms*) + vendor=hitachi + ;; + -mpw* | -macos*) + vendor=apple + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + vendor=atari + ;; + -vos*) + vendor=stratus + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os +exit 0 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/external/gpl3/gdb/dist/readline/support/install.sh b/external/gpl3/gdb/dist/readline/support/install.sh new file mode 100755 index 000000000000..0cac004e6dce --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/install.sh @@ -0,0 +1,247 @@ +#!/bin/sh +# +# install - install a program, script, or datafile +# This comes from X11R5. +# +# $XConsortium: install.sh,v 1.2 89/12/18 14:47:22 jim Exp $ +# +# Copyright 1991 by the Massachusetts Institute of Technology +# +# Permission to use, copy, modify, distribute, and sell this software and its +# documentation for any purpose is hereby granted without fee, provided that +# the above copyright notice appear in all copies and that both that +# copyright notice and this permission notice appear in supporting +# documentation, and that the name of M.I.T. not be used in advertising or +# publicity pertaining to distribution of the software without specific, +# written prior permission. M.I.T. makes no representations about the +# suitability of this software for any purpose. It is provided "as is" +# without express or implied warranty. +# +# This script is compatible with the BSD install script, but was written +# from scratch. +# + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit="${DOITPROG-}" + + +# put in absolute paths if you don't have them in your path; or use env. vars. + +mvprog="${MVPROG-mv}" +cpprog="${CPPROG-cp}" +chmodprog="${CHMODPROG-chmod}" +chownprog="${CHOWNPROG-chown}" +chgrpprog="${CHGRPPROG-chgrp}" +stripprog="${STRIPPROG-strip}" +rmprog="${RMPROG-rm}" +mkdirprog="${MKDIRPROG-mkdir}" + +tranformbasename="" +transform_arg="" +instcmd="$mvprog" +chmodcmd="$chmodprog 0755" +chowncmd="" +chgrpcmd="" +stripcmd="" +rmcmd="$rmprog -f" +mvcmd="$mvprog" +src="" +dst="" +dir_arg="" + +while [ x"$1" != x ]; do + case $1 in + -c) instcmd="$cpprog" + shift + continue;; + + -d) dir_arg=true + shift + continue;; + + -m) chmodcmd="$chmodprog $2" + shift + shift + continue;; + + -o) chowncmd="$chownprog $2" + shift + shift + continue;; + + -g) chgrpcmd="$chgrpprog $2" + shift + shift + continue;; + + -s) stripcmd="$stripprog" + shift + continue;; + + -t=*) transformarg=`echo $1 | sed 's/-t=//'` + shift + continue;; + + -b=*) transformbasename=`echo $1 | sed 's/-b=//'` + shift + continue;; + + *) if [ x"$src" = x ] + then + src=$1 + else + # this colon is to work around a 386BSD /bin/sh bug + : + dst=$1 + fi + shift + continue;; + esac +done + +if [ x"$src" = x ] +then + echo "install: no input file specified" + exit 1 +else + true +fi + +if [ x"$dir_arg" != x ]; then + dst=$src + src="" + + if [ -d $dst ]; then + instcmd=: + else + instcmd=mkdir + fi +else + +# Waiting for this to be detected by the "$instcmd $src $dsttmp" command +# might cause directories to be created, which would be especially bad +# if $src (and thus $dsttmp) contains '*'. + + if [ -f $src -o -d $src ] + then + true + else + echo "install: $src does not exist" + exit 1 + fi + + if [ x"$dst" = x ] + then + echo "install: no destination specified" + exit 1 + else + true + fi + +# If destination is a directory, append the input filename; if your system +# does not like double slashes in filenames, you may need to add some logic + + if [ -d $dst ] + then + dst="$dst"/`basename $src` + else + true + fi +fi + +## this sed command emulates the dirname command +dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` + +# Make sure that the destination directory exists. +# this part is taken from Noah Friedman's mkinstalldirs script + +# Skip lots of stat calls in the usual case. +if [ ! -d "$dstdir" ]; then +defaultIFS=' +' +IFS="${IFS-${defaultIFS}}" + +oIFS="${IFS}" +# Some sh's can't handle IFS=/ for some reason. +IFS='%' +set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'` +IFS="${oIFS}" + +pathcomp='' + +while [ $# -ne 0 ] ; do + pathcomp="${pathcomp}${1}" + shift + + if [ ! -d "${pathcomp}" ] ; + then + $mkdirprog "${pathcomp}" + else + true + fi + + pathcomp="${pathcomp}/" +done +fi + +if [ x"$dir_arg" != x ] +then + $doit $instcmd $dst && + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi +else + +# If we're going to rename the final executable, determine the name now. + + if [ x"$transformarg" = x ] + then + dstfile=`basename $dst` + else + dstfile=`basename $dst $transformbasename | + sed $transformarg`$transformbasename + fi + +# don't allow the sed command to completely eliminate the filename + + if [ x"$dstfile" = x ] + then + dstfile=`basename $dst` + else + true + fi + +# Make a temp file name in the proper directory. + + dsttmp=$dstdir/#inst.$$# + +# Move or copy the file name to the temp name + + $doit $instcmd $src $dsttmp && + + trap "rm -f ${dsttmp}" 0 && + +# and set any options; do chmod last to preserve setuid bits + +# If any of these fail, we abort the whole thing. If we want to +# ignore errors from any of these, just make sure not to ignore +# errors from the above "$doit $instcmd $src $dsttmp" command. + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && + +# Now rename the file to the real destination. + + $doit $rmcmd -f $dstdir/$dstfile && + $doit $mvcmd $dsttmp $dstdir/$dstfile + +fi && + + +exit 0 diff --git a/external/gpl3/gdb/dist/readline/support/mkdirs b/external/gpl3/gdb/dist/readline/support/mkdirs new file mode 100755 index 000000000000..ce4fb235db79 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/mkdirs @@ -0,0 +1,48 @@ +#! /bin/sh +# +# mkdirs - a work-alike for `mkdir -p' +# +# Chet Ramey +# chet@po.cwru.edu + +# Copyright (C) 1996-2002 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +for dir +do + + test -d "$dir" && continue + + tomake=$dir + while test -n "$dir" ; do + # dir=${dir%/*} + # dir=`expr "$dir" ':' '\(/.*\)/[^/]*'` + if dir=`expr "$dir" ':' '\(.*\)/[^/]*'`; then + tomake="$dir $tomake" + else + dir= + fi + done + + for d in $tomake + do + test -d "$d" && continue + echo mkdir "$d" + mkdir "$d" + done +done + +exit 0 diff --git a/external/gpl3/gdb/dist/readline/support/mkdist b/external/gpl3/gdb/dist/readline/support/mkdist new file mode 100755 index 000000000000..06e6155f559f --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/mkdist @@ -0,0 +1,120 @@ +#! /bin/bash - +# +# mkdist - make a distribution directory from a master manifest file +# +# usage: mkdist [-m manifest] [-s srcdir] [-r rootname] [-v] version +# +# SRCDIR defaults to src +# MANIFEST defaults to $SRCDIR/MANIFEST +# +# Chet Ramey +# chet@po.cwru.edu + +# Copyright (C) 1996-2002 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +SRCDIR=src +ROOTNAME=bash + +usage() +{ + echo usage: mkdist [-m manifest] [-s srcdir] [-r rootname] [-v] version 1>&2 + exit 2 +} + +vmsg() +{ + if [ -n "$verbose" ]; then + echo mkdist: "$@" + fi +} + +while getopts m:s:r:v name +do + case $name in + m) MANIFEST=$OPTARG ;; + s) SRCDIR=$OPTARG ;; + r) ROOTNAME=$OPTARG ;; + v) verbose=yes ;; + ?) usage ;; + esac +done + +: ${MANIFEST:=$SRCDIR/MANIFEST} + +vmsg using $MANIFEST + +shift $(( $OPTIND - 1 )) + +if [ $# -lt 1 ]; then + usage +fi + +version=$1 +newdir=${ROOTNAME}-$version + +vmsg creating distribution for $ROOTNAME version $version in $newdir + +if [ ! -d $newdir ]; then + mkdir $newdir || { echo $0: cannot make directory $newdir 1>&2 ; exit 1; } +fi + +dirmode=755 +filmode=644 + +while read fname type mode +do + [ -z "$fname" ] && continue + + case "$fname" in + \#*) continue ;; + esac + + case "$type" in + d) mkdir $newdir/$fname ;; + f) cp -p $SRCDIR/$fname $newdir/$fname ;; + s) ln -s $mode $newdir/$fname ; mode= ;; # symlink + l) ln $mode $newdir/$fname ; mode= ;; # hard link + *) echo "unknown file type $type" 1>&2 ;; + esac + + if [ -n "$mode" ]; then + chmod $mode $newdir/$fname + fi + +done < $MANIFEST + +# cut off the `-alpha' in something like `2.0-alpha', leaving just the +# numeric version +#version=${version%%-*} + +#case "$version" in +#*.*.*) vers=${version%.*} ;; +#*.*) vers=${version} ;; +#esac + +#echo $vers > $newdir/.distribution + +#case "$version" in +#*.*.*) plevel=${version##*.} ;; +#*) plevel=0 ;; +#esac +#[ -z "$plevel" ] && plevel=0 +#echo ${plevel} > $newdir/.patchlevel + +vmsg $newdir created + +exit 0 diff --git a/external/gpl3/gdb/dist/readline/support/mkinstalldirs b/external/gpl3/gdb/dist/readline/support/mkinstalldirs new file mode 100755 index 000000000000..d2d5f21b6112 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/mkinstalldirs @@ -0,0 +1,111 @@ +#! /bin/sh +# mkinstalldirs --- make directory hierarchy +# Author: Noah Friedman +# Created: 1993-05-16 +# Public domain + +errstatus=0 +dirmode="" + +usage="\ +Usage: mkinstalldirs [-h] [--help] [-m mode] dir ..." + +# process command line arguments +while test $# -gt 0 ; do + case $1 in + -h | --help | --h*) # -h for help + echo "$usage" 1>&2 + exit 0 + ;; + -m) # -m PERM arg + shift + test $# -eq 0 && { echo "$usage" 1>&2; exit 1; } + dirmode=$1 + shift + ;; + --) # stop option processing + shift + break + ;; + -*) # unknown option + echo "$usage" 1>&2 + exit 1 + ;; + *) # first non-opt arg + break + ;; + esac +done + +for file +do + if test -d "$file"; then + shift + else + break + fi +done + +case $# in + 0) exit 0 ;; +esac + +case $dirmode in + '') + if mkdir -p -- . 2>/dev/null; then + echo "mkdir -p -- $*" + exec mkdir -p -- "$@" + fi + ;; + *) + if mkdir -m "$dirmode" -p -- . 2>/dev/null; then + echo "mkdir -m $dirmode -p -- $*" + exec mkdir -m "$dirmode" -p -- "$@" + fi + ;; +esac + +for file +do + set fnord `echo ":$file" | sed -ne 's/^:\//#/;s/^://;s/\// /g;s/^#/\//;p'` + shift + + pathcomp= + for d + do + pathcomp="$pathcomp$d" + case $pathcomp in + -*) pathcomp=./$pathcomp ;; + esac + + if test ! -d "$pathcomp"; then + echo "mkdir $pathcomp" + + mkdir "$pathcomp" || lasterr=$? + + if test ! -d "$pathcomp"; then + errstatus=$lasterr + else + if test ! -z "$dirmode"; then + echo "chmod $dirmode $pathcomp" + lasterr="" + chmod "$dirmode" "$pathcomp" || lasterr=$? + + if test ! -z "$lasterr"; then + errstatus=$lasterr + fi + fi + fi + fi + + pathcomp="$pathcomp/" + done +done + +exit $errstatus + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# End: +# mkinstalldirs ends here diff --git a/external/gpl3/gdb/dist/readline/support/shlib-install b/external/gpl3/gdb/dist/readline/support/shlib-install new file mode 100755 index 000000000000..2cd252a36580 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/shlib-install @@ -0,0 +1,195 @@ +#! /bin/sh +# +# shlib-install - install a shared library and do any necessary host-specific +# post-installation configuration (like ldconfig) +# +# usage: shlib-install [-D] -O host_os -d installation-dir [-b bin-dir] -i install-prog [-U] library +# +# Chet Ramey +# chet@po.cwru.edu + +# +# defaults +# +INSTALLDIR=/usr/local/lib +LDCONFIG=ldconfig + +PROGNAME=`basename $0` +USAGE="$PROGNAME [-D] -O host_os -d installation-dir [-b bin-dir] -i install-prog [-U] library" + +# process options + +while [ $# -gt 0 ]; do + case "$1" in + -O) shift; host_os="$1"; shift ;; + -d) shift; INSTALLDIR="$1"; shift ;; + -b) shift; BINDIR="$1" ; shift ;; + -i) shift; INSTALLPROG="$1" ; shift ;; + -D) echo=echo ; shift ;; + -U) uninstall=true ; shift ;; + -*) echo "$USAGE" >&2 ; exit 2;; + *) break ;; + esac +done + +# set install target name +LIBNAME="$1" + +if [ -z "$LIBNAME" ]; then + echo "$USAGE" >&2 + exit 2 +fi + +OLDSUFF=old +MV=mv +RM="rm -f" +LN="ln -s" + +# pre-install + +if [ -z "$uninstall" ]; then + ${echo} $RM ${INSTALLDIR}/${LIBNAME}.${OLDSUFF} + if [ -f "$INSTALLDIR/$LIBNAME" ]; then + ${echo} $MV $INSTALLDIR/$LIBNAME ${INSTALLDIR}/${LIBNAME}.${OLDSUFF} + fi +fi + +# install/uninstall + +if [ -z "$uninstall" ] ; then + ${echo} eval ${INSTALLPROG} $LIBNAME ${INSTALLDIR}/${LIBNAME} +else + ${echo} ${RM} ${INSTALLDIR}/${LIBNAME} +fi + +# post-install/uninstall + +# HP-UX and Darwin/MacOS X require that a shared library have execute permission +# Cygwin installs both a dll (which must go in $BINDIR) and an implicit +# link library (in $libdir) +case "$host_os" in +hpux*|darwin*|macosx*) + if [ -z "$uninstall" ]; then + chmod 555 ${INSTALLDIR}/${LIBNAME} + fi ;; +cygwin*) + IMPLIBNAME=`echo ${LIBNAME} \ + | sed -e 's,^cyg,lib,' -e 's,[0-9]*.dll$,.dll.a,'` + if [ -z "$uninstall" ]; then + ${echo} $RM ${BINDIR}/${LIBNAME}.${OLDSUFF} + if [ -f "$BINDIR/$LIBNAME" ]; then + ${echo} $MV $BINDIR/$LIBNAME $BINDIR/$LIBNAME.$OLDSUFF + fi + ${echo} $MV ${INSTALLDIR}/${LIBNAME} ${BINDIR}/${LIBNAME} + ${echo} chmod a+x ${BINDIR}/${LIBNAME} + ${echo} eval ${INSTALLPROG} ${LIBNAME}.a \ + ${INSTALLDIR}/${IMPLIBNAME} + else + ${echo} ${RM} ${BINDIR}/${LIBNAME} + ${echo} ${RM} ${INSTALLDIR}/${IMPLIBNAME} + fi ;; + +*) ;; +esac + +case "$LIBNAME" in +*.*.[0-9].[0-9]) # libname.so.M.N + LINK2=`echo $LIBNAME | sed 's:\(.*\..*\.[0-9]\)\.[0-9]:\1:'` # libname.so.M + LINK1=`echo $LIBNAME | sed 's:\(.*\..*\)\.[0-9]\.[0-9]:\1:'` # libname.so + ;; +*.*.[0-9]) # libname.so.M + LINK1=`echo $LIBNAME | sed 's:\(.*\..*\)\.[0-9]:\1:'` # libname.so + ;; +*.[0-9]) # libname.M + LINK1=`echo $LIBNAME | sed 's:\(.*\)\.[0-9]:\1:'` # libname + ;; +*.[0-9].[0-9].dylib) # libname.M.N.dylib + LINK2=`echo $LIBNAME | sed 's:\(.*\.[0-9]\)\.[0-9]:\1:'` # libname.M.dylib + LINK1=`echo $LIBNAME | sed 's:\(.*\)\.[0-9]\.[0-9]:\1:'` # libname.dylib +esac + +INSTALL_LINK1='${echo} cd $INSTALLDIR && ${echo} ${LN} $LIBNAME $LINK1' +INSTALL_LINK2='${echo} cd $INSTALLDIR && ${echo} ${LN} $LIBNAME $LINK2' + +# +# Create symlinks to the installed library. This section is incomplete. +# +case "$host_os" in +*linux*) + # libname.so.M -> libname.so.M.N + ${echo} ${RM} ${INSTALLDIR}/$LINK2 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK2 + fi + + # libname.so -> libname.so.M + ${echo} ${RM} ${INSTALLDIR}/$LINK1 + if [ -z "$uninstall" ]; then + ${echo} cd $INSTALLDIR && ${echo} ${LN} $LINK2 $LINK1 + fi + ;; + +bsdi4*|*gnu*|darwin*|macosx*|k*bsd*-gnu) + # libname.so.M -> libname.so.M.N + ${echo} ${RM} ${INSTALLDIR}/$LINK2 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK2 + fi + + # libname.so -> libname.so.M.N + ${echo} ${RM} ${INSTALLDIR}/$LINK1 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK1 + fi + ;; + +solaris2*|aix4.[2-9]*|osf*|irix[56]*|sysv[45]*|dgux*) + # libname.so -> libname.so.M + ${echo} ${RM} ${INSTALLDIR}/$LINK1 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK1 + fi + ;; + + +# FreeBSD 3.x and above can have either a.out or ELF shared libraries +freebsd[3-9]*|freebsdelf[3-9]*|freebsdaout[3-9]*) + if [ -x /usr/bin/objformat ] && [ "`/usr/bin/objformat`" = "elf" ]; then + # libname.so -> libname.so.M + ${echo} ${RM} ${INSTALLDIR}/$LINK1 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK1 + fi + else + # libname.so.M -> libname.so.M.N + ${echo} ${RM} ${INSTALLDIR}/$LINK2 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK2 + fi + + # libname.so -> libname.so.M.N + ${echo} ${RM} ${INSTALLDIR}/$LINK1 + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK1 + fi + fi + ;; + +hpux1*) + # libname.sl -> libname.M + ${echo} ${RM} ${INSTALLDIR}/$LINK1.sl + if [ -z "$uninstall" ]; then + eval $INSTALL_LINK1 + fi + ;; + +cygwin*) + # Links to .dlls don't work. Hence shobj-conf used DLLVERSION.dll + # instead of so.SHLIB_MAJOR.SHLIB_MINOR. The postinstall above + # took care of everything else. + ;; + +*) ;; +esac + +exit 0 diff --git a/external/gpl3/gdb/dist/readline/support/shobj-conf b/external/gpl3/gdb/dist/readline/support/shobj-conf new file mode 100755 index 000000000000..0e306bc1a721 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/shobj-conf @@ -0,0 +1,530 @@ +#! /bin/sh +# +# shobj-conf -- output a series of variable assignments to be substituted +# into a Makefile by configure which specify system-dependent +# information for creating shared objects that may be loaded +# into bash with `enable -f' +# +# usage: shobj-conf [-C compiler] -c host_cpu -o host_os -v host_vendor +# +# Chet Ramey +# chet@po.cwru.edu + +# Copyright (C) 1996-2002 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA. + +# +# defaults +# +SHOBJ_STATUS=supported +SHLIB_STATUS=supported + +SHOBJ_CC=cc +SHOBJ_CFLAGS= +SHOBJ_LD= +SHOBJ_LDFLAGS= +SHOBJ_XLDFLAGS= +SHOBJ_LIBS= + +SHLIB_XLDFLAGS= +SHLIB_LIBS= + +SHLIB_DOT='.' +SHLIB_LIBPREF='lib' +SHLIB_LIBSUFF='so' + +SHLIB_LIBVERSION='$(SHLIB_LIBSUFF)' +SHLIB_DLLVERSION='$(SHLIB_MAJOR)' + +PROGNAME=`basename $0` +USAGE="$PROGNAME [-C compiler] -c host_cpu -o host_os -v host_vendor" + +while [ $# -gt 0 ]; do + case "$1" in + -C) shift; SHOBJ_CC="$1"; shift ;; + -c) shift; host_cpu="$1"; shift ;; + -o) shift; host_os="$1"; shift ;; + -v) shift; host_vendor="$1"; shift ;; + *) echo "$USAGE" >&2 ; exit 2;; + esac +done + +case "${host_os}-${SHOBJ_CC}" in +sunos4*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD=/usr/bin/ld + SHOBJ_LDFLAGS='-assert pure-text' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +sunos4*) + SHOBJ_CFLAGS=-pic + SHOBJ_LD=/usr/bin/ld + SHOBJ_LDFLAGS='-assert pure-text' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +sunos5*-*gcc*|solaris2*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + ld_used=`gcc -print-prog-name=ld` + if ${ld_used} -V 2>&1 | grep GNU >/dev/null 2>&1; then + # This line works for the GNU ld + SHOBJ_LDFLAGS='-shared -Wl,-h,$@' + else + # This line works for the Solaris linker in /usr/ccs/bin/ld + SHOBJ_LDFLAGS='-shared -Wl,-i -Wl,-h,$@' + fi + +# SHLIB_XLDFLAGS='-R $(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sunos5*|solaris2*) + SHOBJ_CFLAGS='-K pic' + SHOBJ_LD=/usr/ccs/bin/ld + SHOBJ_LDFLAGS='-G -dy -z text -i -h $@' + +# SHLIB_XLDFLAGS='-R $(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +# All versions of Linux or the semi-mythical GNU Hurd. +linux*-*|gnu*-*|k*bsd*-gnu-*) + SHOBJ_CFLAGS=-fPIC + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared -Wl,-soname,$@' + + SHLIB_XLDFLAGS='-Wl,-rpath,$(libdir) -Wl,-soname,`basename $@ $(SHLIB_MINOR)`' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +freebsd2* | netbsd*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-x -Bshareable' + + SHLIB_XLDFLAGS='-R$(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +# FreeBSD-3.x ELF +freebsd[3-9]*|freebsdelf[3-9]*|freebsdaout[3-9]*|dragonfly*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + + if [ -x /usr/bin/objformat ] && [ "`/usr/bin/objformat`" = "elf" ]; then + SHOBJ_LDFLAGS='-shared -Wl,-soname,$@' + + SHLIB_XLDFLAGS='-Wl,-rpath,$(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + else + SHOBJ_LDFLAGS='-shared' + + SHLIB_XLDFLAGS='-R$(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + fi + ;; + +# Darwin/MacOS X +darwin*|macosx*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=supported + + SHOBJ_CFLAGS='-fno-common' + + SHOBJ_LD='${CC}' + + SHLIB_LIBVERSION='$(SHLIB_MAJOR)$(SHLIB_MINOR).$(SHLIB_LIBSUFF)' + SHLIB_LIBSUFF='dylib' + + case "${host_os}" in + darwin[78]*) SHOBJ_LDFLAGS='' + SHLIB_XLDFLAGS='-dynamiclib -arch_only `/usr/bin/arch` -install_name $(libdir)/$@ -current_version $(SHLIB_MAJOR)$(SHLIB_MINOR) -compatibility_version $(SHLIB_MAJOR) -v' + ;; + *) SHOBJ_LDFLAGS='-dynamic' + SHLIB_XLDFLAGS='-arch_only `/usr/bin/arch` -install_name $(libdir)/$@ -current_version $(SHLIB_MAJOR)$(SHLIB_MINOR) -compatibility_version $(SHLIB_MAJOR) -v' + ;; + esac + + SHLIB_LIBS='-lncurses' # see if -lcurses works on MacOS X 10.1 + ;; + +openbsd*) + SHOBJ_CFLAGS=-fPIC + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_XLDFLAGS='-R$(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +bsdi2*) + SHOBJ_CC=shlicc2 + SHOBJ_CFLAGS= + SHOBJ_LD=ld + SHOBJ_LDFLAGS=-r + SHOBJ_LIBS=-lc_s.2.1.0 + + # BSD/OS 2.x and 3.x `shared libraries' are too much of a pain in + # the ass -- they require changing {/usr/lib,etc}/shlib.map on + # each system, and the library creation process is byzantine + SHLIB_STATUS=unsupported + ;; + +bsdi3*) + SHOBJ_CC=shlicc2 + SHOBJ_CFLAGS= + SHOBJ_LD=ld + SHOBJ_LDFLAGS=-r + SHOBJ_LIBS=-lc_s.3.0.0 + + # BSD/OS 2.x and 3.x `shared libraries' are too much of a pain in + # the ass -- they require changing {/usr/lib,etc}/shlib.map on + # each system, and the library creation process is byzantine + SHLIB_STATUS=unsupported + ;; + +bsdi4*) + # BSD/OS 4.x now supports ELF and SunOS-style dynamically-linked + # shared libraries. gcc 2.x is the standard compiler, and the + # `normal' gcc options should work as they do in Linux. + + SHOBJ_CFLAGS=-fPIC + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared -Wl,-soname,$@' + + SHLIB_XLDFLAGS='-Wl,-soname,`basename $@ $(SHLIB_MINOR)`' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)$(SHLIB_MINOR)' + ;; + +osf*-*gcc*) + # Fix to use gcc linker driver from bfischer@TechFak.Uni-Bielefeld.DE + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared -Wl,-soname,$@' + + SHLIB_XLDFLAGS='-rpath $(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +osf*) + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-shared -soname $@ -expect_unresolved "*"' + + SHLIB_XLDFLAGS='-rpath $(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +aix4.[2-9]*-*gcc*) # lightly tested by jik@cisco.com + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='ld' + SHOBJ_LDFLAGS='-bdynamic -bnoentry -bexpall' + SHOBJ_XLDFLAGS='-G' + + SHLIB_XLDFLAGS='-bM:SRE' + SHLIB_LIBS='-lcurses -lc' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +aix4.[2-9]*) + SHOBJ_CFLAGS=-K + SHOBJ_LD='ld' + SHOBJ_LDFLAGS='-bdynamic -bnoentry -bexpall' + SHOBJ_XLDFLAGS='-G' + + SHLIB_XLDFLAGS='-bM:SRE' + SHLIB_LIBS='-lcurses -lc' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +# +# THE FOLLOWING ARE UNTESTED -- and some may not support the dlopen interface +# +irix[56]*-*gcc*) + SHOBJ_CFLAGS='-fpic' + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared -Wl,-soname,$@' + + SHLIB_XLDFLAGS='-Wl,-rpath,$(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +irix[56]*) + SHOBJ_CFLAGS='-K PIC' + SHOBJ_LD=ld +# SHOBJ_LDFLAGS='-call_shared -hidden_symbol -no_unresolved -soname $@' +# Change from David Kaelbling . If you have problems, +# remove the `-no_unresolved' + SHOBJ_LDFLAGS='-shared -no_unresolved -soname $@' + + SHLIB_XLDFLAGS='-rpath $(libdir)' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +hpux9*-*gcc*) + # must use gcc; the bundled cc cannot compile PIC code + SHOBJ_CFLAGS='-fpic' + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared -Wl,-b -Wl,+s' + + SHLIB_XLDFLAGS='-Wl,+b,$(libdir)' + SHLIB_LIBSUFF='sl' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +hpux9*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=unsupported + + # If you are using the HP ANSI C compiler, you can uncomment and use + # this code (I have not tested it) +# SHOBJ_STATUS=supported +# SHLIB_STATUS=supported +# +# SHOBJ_CFLAGS='+z' +# SHOBJ_LD='ld' +# SHOBJ_LDFLAGS='-b +s' +# +# SHLIB_XLDFLAGS='+b $(libdir)' +# SHLIB_LIBSUFF='sl' +# SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + + ;; + +hpux10*-*gcc*) + # must use gcc; the bundled cc cannot compile PIC code + SHOBJ_CFLAGS='-fpic' + SHOBJ_LD='${CC}' + # if you have problems linking here, moving the `-Wl,+h,$@' from + # SHLIB_XLDFLAGS to SHOBJ_LDFLAGS has been reported to work + SHOBJ_LDFLAGS='-shared -Wl,-b -Wl,+s' + + SHLIB_XLDFLAGS='-Wl,+h,$@ -Wl,+b,$(libdir)' + SHLIB_LIBSUFF='sl' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +hpux10*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=unsupported + + # If you are using the HP ANSI C compiler, you can uncomment and use + # this code (I have not tested it) +# SHOBJ_STATUS=supported +# SHLIB_STATUS=supported +# +# SHOBJ_CFLAGS='+z' +# SHOBJ_LD='ld' +# SHOBJ_LDFLAGS='-b +s +h $@' +# +# SHLIB_XLDFLAGS='+b $(libdir)' +# SHLIB_LIBSUFF='sl' +# SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + + ;; + +hpux11*-*gcc*) + # must use gcc; the bundled cc cannot compile PIC code + SHOBJ_CFLAGS='-fpic' + SHOBJ_LD='${CC}' +# SHOBJ_LDFLAGS='-shared -Wl,-b -Wl,-B,symbolic -Wl,+s -Wl,+std -Wl,+h,$@' + SHOBJ_LDFLAGS='-shared -fpic -Wl,-b -Wl,+s -Wl,+h,$@' + + SHLIB_XLDFLAGS='-Wl,+b,$(libdir)' + SHLIB_LIBSUFF='sl' + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +hpux11*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=unsupported + + # If you are using the HP ANSI C compiler, you can uncomment and use + # this code (I have not tested it) +# SHOBJ_STATUS=supported +# SHLIB_STATUS=supported +# +# SHOBJ_CFLAGS='+z' +# SHOBJ_LD='ld' +# SHOBJ_LDFLAGS='-b +s +h $@' +# +# SHLIB_XLDFLAGS='+b $(libdir)' +# SHLIB_LIBSUFF='sl' +# SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + + ;; + +sysv4*-*gcc*) + SHOBJ_CFLAGS=-shared + SHOBJ_LDFLAGS='-shared -h $@' + SHOBJ_LD='${CC}' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv4*) + SHOBJ_CFLAGS='-K PIC' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-dy -z text -G -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sco3.2v5*-*gcc*) + SHOBJ_CFLAGS='-fpic' # DEFAULTS TO ELF + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sco3.2v5*) + SHOBJ_CFLAGS='-K pic -b elf' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-G -b elf -dy -z text -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5uw7*-*gcc*) + SHOBJ_CFLAGS='-fpic' + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5uw7*) + SHOBJ_CFLAGS='-K PIC' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-G -dy -z text -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5UnixWare*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5UnixWare*) + SHOBJ_CFLAGS='-K PIC' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-G -dy -z text -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5OpenUNIX*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +sysv5OpenUNIX*) + SHOBJ_CFLAGS='-K PIC' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-G -dy -z text -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +dgux*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +dgux*) + SHOBJ_CFLAGS='-K pic' + SHOBJ_LD=ld + SHOBJ_LDFLAGS='-G -dy -h $@' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +msdos*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=unsupported + ;; + +cygwin*) + SHOBJ_LD='$(CC)' + SHOBJ_LDFLAGS='-shared -Wl,--enable-auto-import -Wl,--enable-auto-image-base -Wl,--export-all -Wl,--out-implib=$(@).a' + SHLIB_LIBPREF='cyg' + SHLIB_LIBSUFF='dll' + SHLIB_LIBVERSION='$(SHLIB_DLLVERSION).$(SHLIB_LIBSUFF)' + SHLIB_LIBS='$(TERMCAP_LIB)' + + SHLIB_DOT= + # For official cygwin releases, DLLVERSION will be defined in the + # environment of configure, and will be incremented any time the API + # changes in a non-backwards compatible manner. Otherwise, it is just + # SHLIB_MAJOR. + if [ -n "$DLLVERSION" ] ; then + SHLIB_DLLVERSION="$DLLVERSION" + fi + ;; + +# +# Rely on correct gcc configuration for everything else +# +*-*gcc*) + SHOBJ_CFLAGS=-fpic + SHOBJ_LD='${CC}' + SHOBJ_LDFLAGS='-shared' + + SHLIB_LIBVERSION='$(SHLIB_LIBSUFF).$(SHLIB_MAJOR)' + ;; + +*) + SHOBJ_STATUS=unsupported + SHLIB_STATUS=unsupported + ;; + +esac + +echo SHOBJ_CC=\'"$SHOBJ_CC"\' +echo SHOBJ_CFLAGS=\'"$SHOBJ_CFLAGS"\' +echo SHOBJ_LD=\'"$SHOBJ_LD"\' +echo SHOBJ_LDFLAGS=\'"$SHOBJ_LDFLAGS"\' +echo SHOBJ_XLDFLAGS=\'"$SHOBJ_XLDFLAGS"\' +echo SHOBJ_LIBS=\'"$SHOBJ_LIBS"\' + +echo SHLIB_XLDFLAGS=\'"$SHLIB_XLDFLAGS"\' +echo SHLIB_LIBS=\'"$SHLIB_LIBS"\' + +echo SHLIB_DOT=\'"$SHLIB_DOT"\' + +echo SHLIB_LIBPREF=\'"$SHLIB_LIBPREF"\' +echo SHLIB_LIBSUFF=\'"$SHLIB_LIBSUFF"\' + +echo SHLIB_LIBVERSION=\'"$SHLIB_LIBVERSION"\' +echo SHLIB_DLLVERSION=\'"$SHLIB_DLLVERSION"\' + +echo SHOBJ_STATUS=\'"$SHOBJ_STATUS"\' +echo SHLIB_STATUS=\'"$SHLIB_STATUS"\' + +exit 0 diff --git a/external/gpl3/gdb/dist/readline/support/wcwidth.c b/external/gpl3/gdb/dist/readline/support/wcwidth.c new file mode 100644 index 000000000000..36433d7935b8 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/support/wcwidth.c @@ -0,0 +1,241 @@ +/* + * This is an implementation of wcwidth() and wcswidth() as defined in + * "The Single UNIX Specification, Version 2, The Open Group, 1997" + * + * + * Markus Kuhn -- 2001-09-08 -- public domain + */ + +#ifdef __GO32__ +/* DJGPP needs to include this before including wchar.h. */ +# include +#endif + +#include + +struct interval { + unsigned short first; + unsigned short last; +}; + +/* auxiliary function for binary search in interval table */ +static int bisearch(wchar_t ucs, const struct interval *table, int max) { + int min = 0; + int mid; + + if (ucs < table[0].first || ucs > table[max].last) + return 0; + while (max >= min) { + mid = (min + max) / 2; + if (ucs > table[mid].last) + min = mid + 1; + else if (ucs < table[mid].first) + max = mid - 1; + else + return 1; + } + + return 0; +} + + +/* The following functions define the column width of an ISO 10646 + * character as follows: + * + * - The null character (U+0000) has a column width of 0. + * + * - Other C0/C1 control characters and DEL will lead to a return + * value of -1. + * + * - Non-spacing and enclosing combining characters (general + * category code Mn or Me in the Unicode database) have a + * column width of 0. + * + * - Other format characters (general category code Cf in the Unicode + * database) and ZERO WIDTH SPACE (U+200B) have a column width of 0. + * + * - Hangul Jamo medial vowels and final consonants (U+1160-U+11FF) + * have a column width of 0. + * + * - Spacing characters in the East Asian Wide (W) or East Asian + * FullWidth (F) category as defined in Unicode Technical + * Report #11 have a column width of 2. + * + * - All remaining characters (including all printable + * ISO 8859-1 and WGL4 characters, Unicode control characters, + * etc.) have a column width of 1. + * + * This implementation assumes that wchar_t characters are encoded + * in ISO 10646. + */ + +int wcwidth(wchar_t ucs) +{ + /* sorted list of non-overlapping intervals of non-spacing characters */ + static const struct interval combining[] = { + { 0x0300, 0x034E }, { 0x0360, 0x0362 }, { 0x0483, 0x0486 }, + { 0x0488, 0x0489 }, { 0x0591, 0x05A1 }, { 0x05A3, 0x05B9 }, + { 0x05BB, 0x05BD }, { 0x05BF, 0x05BF }, { 0x05C1, 0x05C2 }, + { 0x05C4, 0x05C4 }, { 0x064B, 0x0655 }, { 0x0670, 0x0670 }, + { 0x06D6, 0x06E4 }, { 0x06E7, 0x06E8 }, { 0x06EA, 0x06ED }, + { 0x070F, 0x070F }, { 0x0711, 0x0711 }, { 0x0730, 0x074A }, + { 0x07A6, 0x07B0 }, { 0x0901, 0x0902 }, { 0x093C, 0x093C }, + { 0x0941, 0x0948 }, { 0x094D, 0x094D }, { 0x0951, 0x0954 }, + { 0x0962, 0x0963 }, { 0x0981, 0x0981 }, { 0x09BC, 0x09BC }, + { 0x09C1, 0x09C4 }, { 0x09CD, 0x09CD }, { 0x09E2, 0x09E3 }, + { 0x0A02, 0x0A02 }, { 0x0A3C, 0x0A3C }, { 0x0A41, 0x0A42 }, + { 0x0A47, 0x0A48 }, { 0x0A4B, 0x0A4D }, { 0x0A70, 0x0A71 }, + { 0x0A81, 0x0A82 }, { 0x0ABC, 0x0ABC }, { 0x0AC1, 0x0AC5 }, + { 0x0AC7, 0x0AC8 }, { 0x0ACD, 0x0ACD }, { 0x0B01, 0x0B01 }, + { 0x0B3C, 0x0B3C }, { 0x0B3F, 0x0B3F }, { 0x0B41, 0x0B43 }, + { 0x0B4D, 0x0B4D }, { 0x0B56, 0x0B56 }, { 0x0B82, 0x0B82 }, + { 0x0BC0, 0x0BC0 }, { 0x0BCD, 0x0BCD }, { 0x0C3E, 0x0C40 }, + { 0x0C46, 0x0C48 }, { 0x0C4A, 0x0C4D }, { 0x0C55, 0x0C56 }, + { 0x0CBF, 0x0CBF }, { 0x0CC6, 0x0CC6 }, { 0x0CCC, 0x0CCD }, + { 0x0D41, 0x0D43 }, { 0x0D4D, 0x0D4D }, { 0x0DCA, 0x0DCA }, + { 0x0DD2, 0x0DD4 }, { 0x0DD6, 0x0DD6 }, { 0x0E31, 0x0E31 }, + { 0x0E34, 0x0E3A }, { 0x0E47, 0x0E4E }, { 0x0EB1, 0x0EB1 }, + { 0x0EB4, 0x0EB9 }, { 0x0EBB, 0x0EBC }, { 0x0EC8, 0x0ECD }, + { 0x0F18, 0x0F19 }, { 0x0F35, 0x0F35 }, { 0x0F37, 0x0F37 }, + { 0x0F39, 0x0F39 }, { 0x0F71, 0x0F7E }, { 0x0F80, 0x0F84 }, + { 0x0F86, 0x0F87 }, { 0x0F90, 0x0F97 }, { 0x0F99, 0x0FBC }, + { 0x0FC6, 0x0FC6 }, { 0x102D, 0x1030 }, { 0x1032, 0x1032 }, + { 0x1036, 0x1037 }, { 0x1039, 0x1039 }, { 0x1058, 0x1059 }, + { 0x1160, 0x11FF }, { 0x17B7, 0x17BD }, { 0x17C6, 0x17C6 }, + { 0x17C9, 0x17D3 }, { 0x180B, 0x180E }, { 0x18A9, 0x18A9 }, + { 0x200B, 0x200F }, { 0x202A, 0x202E }, { 0x206A, 0x206F }, + { 0x20D0, 0x20E3 }, { 0x302A, 0x302F }, { 0x3099, 0x309A }, + { 0xFB1E, 0xFB1E }, { 0xFE20, 0xFE23 }, { 0xFEFF, 0xFEFF }, + { 0xFFF9, 0xFFFB } + }; + + /* test for 8-bit control characters */ + if (ucs == 0) + return 0; + if (ucs < 32 || (ucs >= 0x7f && ucs < 0xa0)) + return -1; + + /* binary search in table of non-spacing characters */ + if (bisearch(ucs, combining, + sizeof(combining) / sizeof(struct interval) - 1)) + return 0; + + /* if we arrive here, ucs is not a combining or C0/C1 control character */ + + return 1 + + (ucs >= 0x1100 && + (ucs <= 0x115f || /* Hangul Jamo init. consonants */ + (ucs >= 0x2e80 && ucs <= 0xa4cf && (ucs & ~0x0011) != 0x300a && + ucs != 0x303f) || /* CJK ... Yi */ + (ucs >= 0xac00 && ucs <= 0xd7a3) || /* Hangul Syllables */ + (ucs >= 0xf900 && ucs <= 0xfaff) || /* CJK Compatibility Ideographs */ + (ucs >= 0xfe30 && ucs <= 0xfe6f) || /* CJK Compatibility Forms */ + (ucs >= 0xff00 && ucs <= 0xff5f) || /* Fullwidth Forms */ + (ucs >= 0xffe0 && ucs <= 0xffe6) || + (ucs >= 0x20000 && ucs <= 0x2ffff))); +} + + +int wcswidth(const wchar_t *pwcs, size_t n) +{ + int w, width = 0; + + for (;*pwcs && n-- > 0; pwcs++) + if ((w = wcwidth(*pwcs)) < 0) + return -1; + else + width += w; + + return width; +} + + +/* + * The following function is the same as wcwidth(), except that + * spacing characters in the East Asian Ambiguous (A) category as + * defined in Unicode Technical Report #11 have a column width of 2. + * This experimental variant might be useful for users of CJK legacy + * encodings who want to migrate to UCS. It is not otherwise + * recommended for general use. + */ +static int wcwidth_cjk(wchar_t ucs) +{ + /* sorted list of non-overlapping intervals of East Asian Ambiguous + * characters */ + static const struct interval ambiguous[] = { + { 0x00A1, 0x00A1 }, { 0x00A4, 0x00A4 }, { 0x00A7, 0x00A8 }, + { 0x00AA, 0x00AA }, { 0x00AD, 0x00AE }, { 0x00B0, 0x00B4 }, + { 0x00B6, 0x00BA }, { 0x00BC, 0x00BF }, { 0x00C6, 0x00C6 }, + { 0x00D0, 0x00D0 }, { 0x00D7, 0x00D8 }, { 0x00DE, 0x00E1 }, + { 0x00E6, 0x00E6 }, { 0x00E8, 0x00EA }, { 0x00EC, 0x00ED }, + { 0x00F0, 0x00F0 }, { 0x00F2, 0x00F3 }, { 0x00F7, 0x00FA }, + { 0x00FC, 0x00FC }, { 0x00FE, 0x00FE }, { 0x0101, 0x0101 }, + { 0x0111, 0x0111 }, { 0x0113, 0x0113 }, { 0x011B, 0x011B }, + { 0x0126, 0x0127 }, { 0x012B, 0x012B }, { 0x0131, 0x0133 }, + { 0x0138, 0x0138 }, { 0x013F, 0x0142 }, { 0x0144, 0x0144 }, + { 0x0148, 0x014B }, { 0x014D, 0x014D }, { 0x0152, 0x0153 }, + { 0x0166, 0x0167 }, { 0x016B, 0x016B }, { 0x01CE, 0x01CE }, + { 0x01D0, 0x01D0 }, { 0x01D2, 0x01D2 }, { 0x01D4, 0x01D4 }, + { 0x01D6, 0x01D6 }, { 0x01D8, 0x01D8 }, { 0x01DA, 0x01DA }, + { 0x01DC, 0x01DC }, { 0x0251, 0x0251 }, { 0x0261, 0x0261 }, + { 0x02C4, 0x02C4 }, { 0x02C7, 0x02C7 }, { 0x02C9, 0x02CB }, + { 0x02CD, 0x02CD }, { 0x02D0, 0x02D0 }, { 0x02D8, 0x02DB }, + { 0x02DD, 0x02DD }, { 0x02DF, 0x02DF }, { 0x0300, 0x034E }, + { 0x0360, 0x0362 }, { 0x0391, 0x03A1 }, { 0x03A3, 0x03A9 }, + { 0x03B1, 0x03C1 }, { 0x03C3, 0x03C9 }, { 0x0401, 0x0401 }, + { 0x0410, 0x044F }, { 0x0451, 0x0451 }, { 0x2010, 0x2010 }, + { 0x2013, 0x2016 }, { 0x2018, 0x2019 }, { 0x201C, 0x201D }, + { 0x2020, 0x2022 }, { 0x2024, 0x2027 }, { 0x2030, 0x2030 }, + { 0x2032, 0x2033 }, { 0x2035, 0x2035 }, { 0x203B, 0x203B }, + { 0x203E, 0x203E }, { 0x2074, 0x2074 }, { 0x207F, 0x207F }, + { 0x2081, 0x2084 }, { 0x20AC, 0x20AC }, { 0x2103, 0x2103 }, + { 0x2105, 0x2105 }, { 0x2109, 0x2109 }, { 0x2113, 0x2113 }, + { 0x2116, 0x2116 }, { 0x2121, 0x2122 }, { 0x2126, 0x2126 }, + { 0x212B, 0x212B }, { 0x2153, 0x2155 }, { 0x215B, 0x215E }, + { 0x2160, 0x216B }, { 0x2170, 0x2179 }, { 0x2190, 0x2199 }, + { 0x21B8, 0x21B9 }, { 0x21D2, 0x21D2 }, { 0x21D4, 0x21D4 }, + { 0x21E7, 0x21E7 }, { 0x2200, 0x2200 }, { 0x2202, 0x2203 }, + { 0x2207, 0x2208 }, { 0x220B, 0x220B }, { 0x220F, 0x220F }, + { 0x2211, 0x2211 }, { 0x2215, 0x2215 }, { 0x221A, 0x221A }, + { 0x221D, 0x2220 }, { 0x2223, 0x2223 }, { 0x2225, 0x2225 }, + { 0x2227, 0x222C }, { 0x222E, 0x222E }, { 0x2234, 0x2237 }, + { 0x223C, 0x223D }, { 0x2248, 0x2248 }, { 0x224C, 0x224C }, + { 0x2252, 0x2252 }, { 0x2260, 0x2261 }, { 0x2264, 0x2267 }, + { 0x226A, 0x226B }, { 0x226E, 0x226F }, { 0x2282, 0x2283 }, + { 0x2286, 0x2287 }, { 0x2295, 0x2295 }, { 0x2299, 0x2299 }, + { 0x22A5, 0x22A5 }, { 0x22BF, 0x22BF }, { 0x2312, 0x2312 }, + { 0x2329, 0x232A }, { 0x2460, 0x24BF }, { 0x24D0, 0x24E9 }, + { 0x2500, 0x254B }, { 0x2550, 0x2574 }, { 0x2580, 0x258F }, + { 0x2592, 0x2595 }, { 0x25A0, 0x25A1 }, { 0x25A3, 0x25A9 }, + { 0x25B2, 0x25B3 }, { 0x25B6, 0x25B7 }, { 0x25BC, 0x25BD }, + { 0x25C0, 0x25C1 }, { 0x25C6, 0x25C8 }, { 0x25CB, 0x25CB }, + { 0x25CE, 0x25D1 }, { 0x25E2, 0x25E5 }, { 0x25EF, 0x25EF }, + { 0x2605, 0x2606 }, { 0x2609, 0x2609 }, { 0x260E, 0x260F }, + { 0x261C, 0x261C }, { 0x261E, 0x261E }, { 0x2640, 0x2640 }, + { 0x2642, 0x2642 }, { 0x2660, 0x2661 }, { 0x2663, 0x2665 }, + { 0x2667, 0x266A }, { 0x266C, 0x266D }, { 0x266F, 0x266F }, + { 0x273D, 0x273D }, { 0x3008, 0x300B }, { 0x3014, 0x3015 }, + { 0x3018, 0x301B }, { 0xFFFD, 0xFFFD } + }; + + /* binary search in table of non-spacing characters */ + if (bisearch(ucs, ambiguous, + sizeof(ambiguous) / sizeof(struct interval) - 1)) + return 2; + + return wcwidth(ucs); +} + + +int wcswidth_cjk(const wchar_t *pwcs, size_t n) +{ + int w, width = 0; + + for (;*pwcs && n-- > 0; pwcs++) + if ((w = wcwidth_cjk(*pwcs)) < 0) + return -1; + else + width += w; + + return width; +} diff --git a/external/gpl3/gdb/dist/readline/tcap.h b/external/gpl3/gdb/dist/readline/tcap.h new file mode 100644 index 000000000000..58ab894d93ee --- /dev/null +++ b/external/gpl3/gdb/dist/readline/tcap.h @@ -0,0 +1,60 @@ +/* tcap.h -- termcap library functions and variables. */ + +/* Copyright (C) 1996 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_RLTCAP_H_) +#define _RLTCAP_H_ + +#if defined (HAVE_CONFIG_H) +# include "config.h" +#endif + +#if defined (HAVE_TERMCAP_H) +# if defined (__linux__) && !defined (SPEED_T_IN_SYS_TYPES) +# include "rltty.h" +# endif +# include +#else + +/* On Solaris2, sys/types.h #includes sys/reg.h, which #defines PC. + Unfortunately, PC is a global variable used by the termcap library. */ +#ifdef PC +# undef PC +#endif + +extern char PC; +extern char *UP, *BC; + +extern short ospeed; + +extern int tgetent (); +extern int tgetflag (); +extern int tgetnum (); +extern char *tgetstr (); + +extern int tputs (); + +extern char *tgoto (); + +#endif /* HAVE_TERMCAP_H */ + +#endif /* !_RLTCAP_H_ */ diff --git a/external/gpl3/gdb/dist/readline/terminal.c b/external/gpl3/gdb/dist/readline/terminal.c new file mode 100644 index 000000000000..46b50e77e24a --- /dev/null +++ b/external/gpl3/gdb/dist/readline/terminal.c @@ -0,0 +1,760 @@ +/* terminal.c -- controlling the terminal with termcap. */ + +/* Copyright (C) 1996-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include "posixstat.h" +#include +#if defined (HAVE_SYS_FILE_H) +# include +#endif /* HAVE_SYS_FILE_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +#if defined (GWINSZ_IN_SYS_IOCTL) && !defined (TIOCGWINSZ) +# include +#endif /* GWINSZ_IN_SYS_IOCTL && !TIOCGWINSZ */ + +#ifdef __MSDOS__ +# include +#endif + +#include "rltty.h" +#include "tcap.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +#if defined (__MINGW32__) +# include +# include +#endif + +#define CUSTOM_REDISPLAY_FUNC() (rl_redisplay_function != rl_redisplay) +#define CUSTOM_INPUT_FUNC() (rl_getc_function != rl_getc) + +int rl_prefer_env_winsize; + +/* **************************************************************** */ +/* */ +/* Terminal and Termcap */ +/* */ +/* **************************************************************** */ + +#ifndef __MSDOS__ +static char *term_buffer = (char *)NULL; +static char *term_string_buffer = (char *)NULL; +#endif /* !__MSDOS__ */ + +static int tcap_initialized; + +#if !defined (__linux__) +# if defined (__EMX__) || defined (NEED_EXTERN_PC) +extern +# endif /* __EMX__ || NEED_EXTERN_PC */ +char PC, *BC, *UP; +#endif /* __linux__ */ + +/* Some strings to control terminal actions. These are output by tputs (). */ +char *_rl_term_clreol; +char *_rl_term_clrpag; +char *_rl_term_cr; +char *_rl_term_backspace; +char *_rl_term_goto; +char *_rl_term_pc; + +/* Non-zero if we determine that the terminal can do character insertion. */ +int _rl_terminal_can_insert = 0; + +/* How to insert characters. */ +char *_rl_term_im; +char *_rl_term_ei; +char *_rl_term_ic; +char *_rl_term_ip; +char *_rl_term_IC; + +/* How to delete characters. */ +char *_rl_term_dc; +char *_rl_term_DC; + +#if defined (HACK_TERMCAP_MOTION) +char *_rl_term_forward_char; +#endif /* HACK_TERMCAP_MOTION */ + +/* How to go up a line. */ +char *_rl_term_up; + +/* A visible bell; char if the terminal can be made to flash the screen. */ +static char *_rl_visible_bell; + +/* Non-zero means the terminal can auto-wrap lines. */ +int _rl_term_autowrap = -1; + +/* Non-zero means that this terminal has a meta key. */ +static int term_has_meta; + +/* The sequences to write to turn on and off the meta key, if this + terminal has one. */ +static char *_rl_term_mm; +static char *_rl_term_mo; + +/* The key sequences output by the arrow keys, if this terminal has any. */ +static char *_rl_term_ku; +static char *_rl_term_kd; +static char *_rl_term_kr; +static char *_rl_term_kl; + +/* How to initialize and reset the arrow keys, if this terminal has any. */ +static char *_rl_term_ks; +static char *_rl_term_ke; + +/* The key sequences sent by the Home and End keys, if any. */ +static char *_rl_term_kh; +static char *_rl_term_kH; +static char *_rl_term_at7; /* @7 */ + +/* Delete key */ +static char *_rl_term_kD; + +/* Insert key */ +static char *_rl_term_kI; + +/* Cursor control */ +static char *_rl_term_vs; /* very visible */ +static char *_rl_term_ve; /* normal */ + +static void bind_termcap_arrow_keys PARAMS((Keymap)); + +/* Variables that hold the screen dimensions, used by the display code. */ +int _rl_screenwidth, _rl_screenheight, _rl_screenchars; + +/* Non-zero means the user wants to enable the keypad. */ +int _rl_enable_keypad; + +/* Non-zero means the user wants to enable a meta key. */ +int _rl_enable_meta = 1; + +#if defined (__EMX__) +static void +_emx_get_screensize (swp, shp) + int *swp, *shp; +{ + int sz[2]; + + _scrsize (sz); + + if (swp) + *swp = sz[0]; + if (shp) + *shp = sz[1]; +} +#endif + +/* Get readline's idea of the screen size. TTY is a file descriptor open + to the terminal. If IGNORE_ENV is true, we do not pay attention to the + values of $LINES and $COLUMNS. The tests for TERM_STRING_BUFFER being + non-null serve to check whether or not we have initialized termcap. */ +void +_rl_get_screen_size (tty, ignore_env) + int tty, ignore_env; +{ + char *ss; +#if defined (TIOCGWINSZ) + struct winsize window_size; +#endif /* TIOCGWINSZ */ + int wr, wc; + + wr = wc = -1; +#if defined (TIOCGWINSZ) + if (ioctl (tty, TIOCGWINSZ, &window_size) == 0) + { + wc = (int) window_size.ws_col; + wr = (int) window_size.ws_row; + } +#endif /* TIOCGWINSZ */ + + /* For MinGW, we get the console size from the Windows API. */ +#if defined (__MINGW32__) + HANDLE hConOut = GetStdHandle (STD_OUTPUT_HANDLE); + if (hConOut != INVALID_HANDLE_VALUE) + { + CONSOLE_SCREEN_BUFFER_INFO scr; + if (GetConsoleScreenBufferInfo (hConOut, &scr)) + { + wc = scr.dwSize.X; + wr = scr.srWindow.Bottom - scr.srWindow.Top + 1; + } + } +#endif + +#if defined (__EMX__) + _emx_get_screensize (&_rl_screenwidth, &_rl_screenheight); +#endif + + if (ignore_env || rl_prefer_env_winsize == 0) + { + _rl_screenwidth = wc; + _rl_screenheight = wr; + } + else + _rl_screenwidth = _rl_screenheight = -1; + + /* Environment variable COLUMNS overrides setting of "co" if IGNORE_ENV + is unset. If we prefer the environment, check it first before + assigning the value returned by the kernel. */ + if (_rl_screenwidth <= 0) + { + if (ignore_env == 0 && (ss = sh_get_env_value ("COLUMNS"))) + _rl_screenwidth = atoi (ss); + + if (_rl_screenwidth <= 0) + _rl_screenwidth = wc; + +#if defined (__DJGPP__) + if (_rl_screenwidth <= 0) + _rl_screenwidth = ScreenCols (); +#else + if (_rl_screenwidth <= 0 && term_string_buffer) + _rl_screenwidth = tgetnum ("co"); +#endif + } + + /* Environment variable LINES overrides setting of "li" if IGNORE_ENV + is unset. */ + if (_rl_screenheight <= 0) + { + if (ignore_env == 0 && (ss = sh_get_env_value ("LINES"))) + _rl_screenheight = atoi (ss); + + if (_rl_screenheight <= 0) + _rl_screenheight = wr; + +#if defined (__DJGPP__) + if (_rl_screenheight <= 0) + _rl_screenheight = ScreenRows (); +#else + if (_rl_screenheight <= 0 && term_string_buffer) + _rl_screenheight = tgetnum ("li"); +#endif + } + + /* If all else fails, default to 80x24 terminal. */ + if (_rl_screenwidth <= 1) + _rl_screenwidth = 80; + + if (_rl_screenheight <= 0) + _rl_screenheight = 24; + + /* If we're being compiled as part of bash, set the environment + variables $LINES and $COLUMNS to new values. Otherwise, just + do a pair of putenv () or setenv () calls. */ + sh_set_lines_and_columns (_rl_screenheight, _rl_screenwidth); + + if (_rl_term_autowrap == 0) + _rl_screenwidth--; + + _rl_screenchars = _rl_screenwidth * _rl_screenheight; +} + +void +_rl_set_screen_size (rows, cols) + int rows, cols; +{ + if (_rl_term_autowrap == -1) + _rl_init_terminal_io (rl_terminal_name); + + if (rows > 0) + _rl_screenheight = rows; + if (cols > 0) + { + _rl_screenwidth = cols; + if (_rl_term_autowrap == 0) + _rl_screenwidth--; + } + + if (rows > 0 || cols > 0) + _rl_screenchars = _rl_screenwidth * _rl_screenheight; +} + +void +rl_set_screen_size (rows, cols) + int rows, cols; +{ + _rl_set_screen_size (rows, cols); +} + +void +rl_get_screen_size (rows, cols) + int *rows, *cols; +{ + if (rows) + *rows = _rl_screenheight; + if (cols) + *cols = _rl_screenwidth; +} + +void +rl_reset_screen_size () +{ + _rl_get_screen_size (fileno (rl_instream), 0); +} + +void +rl_resize_terminal () +{ + if (readline_echoing_p) + { + _rl_get_screen_size (fileno (rl_instream), 1); + if (CUSTOM_REDISPLAY_FUNC ()) + rl_forced_update_display (); + else + _rl_redisplay_after_sigwinch (); + } +} + +struct _tc_string { + const char *tc_var; + char **tc_value; +}; + +/* This should be kept sorted, just in case we decide to change the + search algorithm to something smarter. */ +static struct _tc_string tc_strings[] = +{ + { "@7", &_rl_term_at7 }, + { "DC", &_rl_term_DC }, + { "IC", &_rl_term_IC }, + { "ce", &_rl_term_clreol }, + { "cl", &_rl_term_clrpag }, + { "cr", &_rl_term_cr }, + { "dc", &_rl_term_dc }, + { "ei", &_rl_term_ei }, + { "ic", &_rl_term_ic }, + { "im", &_rl_term_im }, + { "kD", &_rl_term_kD }, /* delete */ + { "kH", &_rl_term_kH }, /* home down ?? */ + { "kI", &_rl_term_kI }, /* insert */ + { "kd", &_rl_term_kd }, + { "ke", &_rl_term_ke }, /* end keypad mode */ + { "kh", &_rl_term_kh }, /* home */ + { "kl", &_rl_term_kl }, + { "kr", &_rl_term_kr }, + { "ks", &_rl_term_ks }, /* start keypad mode */ + { "ku", &_rl_term_ku }, + { "le", &_rl_term_backspace }, + { "mm", &_rl_term_mm }, + { "mo", &_rl_term_mo }, +#if defined (HACK_TERMCAP_MOTION) + { "nd", &_rl_term_forward_char }, +#endif + { "pc", &_rl_term_pc }, + { "up", &_rl_term_up }, + { "vb", &_rl_visible_bell }, + { "vs", &_rl_term_vs }, + { "ve", &_rl_term_ve }, +}; + +#define NUM_TC_STRINGS (sizeof (tc_strings) / sizeof (struct _tc_string)) + +/* Read the desired terminal capability strings into BP. The capabilities + are described in the TC_STRINGS table. */ +static void +get_term_capabilities (bp) + char **bp; +{ +#if !defined (__DJGPP__) /* XXX - doesn't DJGPP have a termcap library? */ + register int i; + + for (i = 0; i < NUM_TC_STRINGS; i++) + *(tc_strings[i].tc_value) = tgetstr ((char *)tc_strings[i].tc_var, bp); +#endif + tcap_initialized = 1; +} + +int +_rl_init_terminal_io (terminal_name) + const char *terminal_name; +{ + const char *term; + char *buffer; + int tty, tgetent_ret; + + term = terminal_name ? terminal_name : sh_get_env_value ("TERM"); + _rl_term_clrpag = _rl_term_cr = _rl_term_clreol = (char *)NULL; + tty = rl_instream ? fileno (rl_instream) : 0; + + if (term == 0) + term = "dumb"; + +#ifdef __MSDOS__ + _rl_term_im = _rl_term_ei = _rl_term_ic = _rl_term_IC = (char *)NULL; + _rl_term_up = _rl_term_dc = _rl_term_DC = _rl_visible_bell = (char *)NULL; + _rl_term_ku = _rl_term_kd = _rl_term_kl = _rl_term_kr = (char *)NULL; + _rl_term_mm = _rl_term_mo = (char *)NULL; + _rl_terminal_can_insert = term_has_meta = _rl_term_autowrap = 0; + _rl_term_cr = "\r"; + _rl_term_clreol = _rl_term_clrpag = _rl_term_backspace = (char *)NULL; + _rl_term_goto = _rl_term_pc = _rl_term_ip = (char *)NULL; + _rl_term_ks = _rl_term_ke =_rl_term_vs = _rl_term_ve = (char *)NULL; + _rl_term_kh = _rl_term_kH = _rl_term_at7 = _rl_term_kI = (char *)NULL; +#if defined(HACK_TERMCAP_MOTION) + _rl_term_forward_char = (char *)NULL; +#endif + + _rl_get_screen_size (tty, 0); +#else /* !__MSDOS__ */ + /* I've separated this out for later work on not calling tgetent at all + if the calling application has supplied a custom redisplay function, + (and possibly if the application has supplied a custom input function). */ + if (CUSTOM_REDISPLAY_FUNC()) + { + tgetent_ret = -1; + } + else + { + if (term_string_buffer == 0) + term_string_buffer = (char *)xmalloc(2032); + + if (term_buffer == 0) + term_buffer = (char *)xmalloc(4080); + + buffer = term_string_buffer; + + tgetent_ret = tgetent (term_buffer, term); + } + + if (tgetent_ret <= 0) + { + FREE (term_string_buffer); + FREE (term_buffer); + buffer = term_buffer = term_string_buffer = (char *)NULL; + + _rl_term_autowrap = 0; /* used by _rl_get_screen_size */ + + /* Allow calling application to set default height and width, using + rl_set_screen_size */ + if (_rl_screenwidth <= 0 || _rl_screenheight <= 0) + { +#if defined (__EMX__) + _emx_get_screensize (&_rl_screenwidth, &_rl_screenheight); + _rl_screenwidth--; +#else /* !__EMX__ */ + _rl_get_screen_size (tty, 0); +#endif /* !__EMX__ */ + } + + /* Defaults. */ + if (_rl_screenwidth <= 0 || _rl_screenheight <= 0) + { + _rl_screenwidth = 79; + _rl_screenheight = 24; + } + + /* Everything below here is used by the redisplay code (tputs). */ + _rl_screenchars = _rl_screenwidth * _rl_screenheight; + _rl_term_cr = "\r"; + _rl_term_im = _rl_term_ei = _rl_term_ic = _rl_term_IC = (char *)NULL; + _rl_term_up = _rl_term_dc = _rl_term_DC = _rl_visible_bell = (char *)NULL; + _rl_term_ku = _rl_term_kd = _rl_term_kl = _rl_term_kr = (char *)NULL; + _rl_term_kh = _rl_term_kH = _rl_term_kI = _rl_term_kD = (char *)NULL; + _rl_term_ks = _rl_term_ke = _rl_term_at7 = (char *)NULL; + _rl_term_mm = _rl_term_mo = (char *)NULL; + _rl_term_ve = _rl_term_vs = (char *)NULL; +#if defined (HACK_TERMCAP_MOTION) + term_forward_char = (char *)NULL; +#endif + _rl_terminal_can_insert = term_has_meta = 0; + + /* Reasonable defaults for tgoto(). Readline currently only uses + tgoto if _rl_term_IC or _rl_term_DC is defined, but just in case we + change that later... */ + PC = '\0'; + BC = _rl_term_backspace = "\b"; + UP = _rl_term_up; + + return 0; + } + + get_term_capabilities (&buffer); + + /* Set up the variables that the termcap library expects the application + to provide. */ + PC = _rl_term_pc ? *_rl_term_pc : 0; + BC = _rl_term_backspace; + UP = _rl_term_up; + + if (!_rl_term_cr) + _rl_term_cr = "\r"; + + _rl_term_autowrap = tgetflag ("am") && tgetflag ("xn"); + + /* Allow calling application to set default height and width, using + rl_set_screen_size */ + if (_rl_screenwidth <= 0 || _rl_screenheight <= 0) + _rl_get_screen_size (tty, 0); + + /* "An application program can assume that the terminal can do + character insertion if *any one of* the capabilities `IC', + `im', `ic' or `ip' is provided." But we can't do anything if + only `ip' is provided, so... */ + _rl_terminal_can_insert = (_rl_term_IC || _rl_term_im || _rl_term_ic); + + /* Check to see if this terminal has a meta key and clear the capability + variables if there is none. */ + term_has_meta = (tgetflag ("km") || tgetflag ("MT")); + if (!term_has_meta) + _rl_term_mm = _rl_term_mo = (char *)NULL; + +#endif /* !__MSDOS__ */ + + /* Attempt to find and bind the arrow keys. Do not override already + bound keys in an overzealous attempt, however. */ + + bind_termcap_arrow_keys (emacs_standard_keymap); + +#if defined (VI_MODE) + bind_termcap_arrow_keys (vi_movement_keymap); + bind_termcap_arrow_keys (vi_insertion_keymap); +#endif /* VI_MODE */ + + return 0; +} + +/* Bind the arrow key sequences from the termcap description in MAP. */ +static void +bind_termcap_arrow_keys (map) + Keymap map; +{ + Keymap xkeymap; + + xkeymap = _rl_keymap; + _rl_keymap = map; + + rl_bind_keyseq_if_unbound (_rl_term_ku, rl_get_previous_history); + rl_bind_keyseq_if_unbound (_rl_term_kd, rl_get_next_history); + rl_bind_keyseq_if_unbound (_rl_term_kr, rl_forward_char); + rl_bind_keyseq_if_unbound (_rl_term_kl, rl_backward_char); + + rl_bind_keyseq_if_unbound (_rl_term_kh, rl_beg_of_line); /* Home */ + rl_bind_keyseq_if_unbound (_rl_term_at7, rl_end_of_line); /* End */ + + rl_bind_keyseq_if_unbound (_rl_term_kD, rl_delete); + + _rl_keymap = xkeymap; +} + +char * +rl_get_termcap (cap) + const char *cap; +{ + register int i; + + if (tcap_initialized == 0) + return ((char *)NULL); + for (i = 0; i < NUM_TC_STRINGS; i++) + { + if (tc_strings[i].tc_var[0] == cap[0] && strcmp (tc_strings[i].tc_var, cap) == 0) + return *(tc_strings[i].tc_value); + } + return ((char *)NULL); +} + +/* Re-initialize the terminal considering that the TERM/TERMCAP variable + has changed. */ +int +rl_reset_terminal (terminal_name) + const char *terminal_name; +{ + _rl_screenwidth = _rl_screenheight = 0; + _rl_init_terminal_io (terminal_name); + return 0; +} + +/* A function for the use of tputs () */ +#ifdef _MINIX +void +_rl_output_character_function (c) + int c; +{ + putc (c, _rl_out_stream); +} +#else /* !_MINIX */ +int +_rl_output_character_function (c) + int c; +{ + return putc (c, _rl_out_stream); +} +#endif /* !_MINIX */ + +/* Write COUNT characters from STRING to the output stream. */ +void +_rl_output_some_chars (string, count) + const char *string; + int count; +{ + fwrite (string, 1, count, _rl_out_stream); +} + +/* Move the cursor back. */ +int +_rl_backspace (count) + int count; +{ + register int i; + +#ifndef __MSDOS__ + if (_rl_term_backspace) + for (i = 0; i < count; i++) + tputs (_rl_term_backspace, 1, _rl_output_character_function); + else +#endif + for (i = 0; i < count; i++) + putc ('\b', _rl_out_stream); + return 0; +} + +/* Move to the start of the next line. */ +int +rl_crlf () +{ +#if defined (NEW_TTY_DRIVER) + if (_rl_term_cr) + tputs (_rl_term_cr, 1, _rl_output_character_function); +#endif /* NEW_TTY_DRIVER */ + putc ('\n', _rl_out_stream); + return 0; +} + +/* Ring the terminal bell. */ +int +rl_ding () +{ + if (readline_echoing_p) + { + switch (_rl_bell_preference) + { + case NO_BELL: + default: + break; + case VISIBLE_BELL: +#ifdef __MSDOS__ + ScreenVisualBell (); + break; +#else + if (_rl_visible_bell) + { + tputs (_rl_visible_bell, 1, _rl_output_character_function); + break; + } + /* FALLTHROUGH */ +#endif + case AUDIBLE_BELL: + fprintf (stderr, "\007"); + fflush (stderr); + break; + } + return (0); + } + return (-1); +} + +/* **************************************************************** */ +/* */ +/* Controlling the Meta Key and Keypad */ +/* */ +/* **************************************************************** */ + +void +_rl_enable_meta_key () +{ +#if !defined (__DJGPP__) + if (term_has_meta && _rl_term_mm) + tputs (_rl_term_mm, 1, _rl_output_character_function); +#endif +} + +void +_rl_control_keypad (on) + int on; +{ +#if !defined (__DJGPP__) + if (on && _rl_term_ks) + tputs (_rl_term_ks, 1, _rl_output_character_function); + else if (!on && _rl_term_ke) + tputs (_rl_term_ke, 1, _rl_output_character_function); +#endif +} + +/* **************************************************************** */ +/* */ +/* Controlling the Cursor */ +/* */ +/* **************************************************************** */ + +/* Set the cursor appropriately depending on IM, which is one of the + insert modes (insert or overwrite). Insert mode gets the normal + cursor. Overwrite mode gets a very visible cursor. Only does + anything if we have both capabilities. */ +void +_rl_set_cursor (im, force) + int im, force; +{ +#ifndef __MSDOS__ + if (_rl_term_ve && _rl_term_vs) + { + if (force || im != rl_insert_mode) + { + if (im == RL_IM_OVERWRITE) + tputs (_rl_term_vs, 1, _rl_output_character_function); + else + tputs (_rl_term_ve, 1, _rl_output_character_function); + } + } +#endif +} diff --git a/external/gpl3/gdb/dist/readline/text.c b/external/gpl3/gdb/dist/readline/text.c new file mode 100644 index 000000000000..bb87604aa6d4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/text.c @@ -0,0 +1,1637 @@ +/* text.c -- text handling commands for readline. */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# include +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_LOCALE_H) +# include +#endif + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (__EMX__) +# define INCL_DOSPROCESS +# include +#endif /* __EMX__ */ + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "rlshell.h" +#include "xmalloc.h" + +/* Forward declarations. */ +static int rl_change_case PARAMS((int, int)); +static int _rl_char_search PARAMS((int, int, int)); + +#if defined (READLINE_CALLBACKS) +static int _rl_insert_next_callback PARAMS((_rl_callback_generic_arg *)); +static int _rl_char_search_callback PARAMS((_rl_callback_generic_arg *)); +#endif + +/* **************************************************************** */ +/* */ +/* Insert and Delete */ +/* */ +/* **************************************************************** */ + +/* Insert a string of text into the line at point. This is the only + way that you should do insertion. _rl_insert_char () calls this + function. Returns the number of characters inserted. */ +int +rl_insert_text (string) + const char *string; +{ + register int i, l; + + l = (string && *string) ? strlen (string) : 0; + if (l == 0) + return 0; + + if (rl_end + l >= rl_line_buffer_len) + rl_extend_line_buffer (rl_end + l); + + for (i = rl_end; i >= rl_point; i--) + rl_line_buffer[i + l] = rl_line_buffer[i]; + strncpy (rl_line_buffer + rl_point, string, l); + + /* Remember how to undo this if we aren't undoing something. */ + if (_rl_doing_an_undo == 0) + { + /* If possible and desirable, concatenate the undos. */ + if ((l == 1) && + rl_undo_list && + (rl_undo_list->what == UNDO_INSERT) && + (rl_undo_list->end == rl_point) && + (rl_undo_list->end - rl_undo_list->start < 20)) + rl_undo_list->end++; + else + rl_add_undo (UNDO_INSERT, rl_point, rl_point + l, (char *)NULL); + } + rl_point += l; + rl_end += l; + rl_line_buffer[rl_end] = '\0'; + return l; +} + +/* Delete the string between FROM and TO. FROM is inclusive, TO is not. + Returns the number of characters deleted. */ +int +rl_delete_text (from, to) + int from, to; +{ + register char *text; + register int diff, i; + + /* Fix it if the caller is confused. */ + if (from > to) + SWAP (from, to); + + /* fix boundaries */ + if (to > rl_end) + { + to = rl_end; + if (from > to) + from = to; + } + if (from < 0) + from = 0; + + text = rl_copy_text (from, to); + + /* Some versions of strncpy() can't handle overlapping arguments. */ + diff = to - from; + for (i = from; i < rl_end - diff; i++) + rl_line_buffer[i] = rl_line_buffer[i + diff]; + + /* Remember how to undo this delete. */ + if (_rl_doing_an_undo == 0) + rl_add_undo (UNDO_DELETE, from, to, text); + else + free (text); + + rl_end -= diff; + rl_line_buffer[rl_end] = '\0'; + return (diff); +} + +/* Fix up point so that it is within the line boundaries after killing + text. If FIX_MARK_TOO is non-zero, the mark is forced within line + boundaries also. */ + +#define _RL_FIX_POINT(x) \ + do { \ + if (x > rl_end) \ + x = rl_end; \ + else if (x < 0) \ + x = 0; \ + } while (0) + +void +_rl_fix_point (fix_mark_too) + int fix_mark_too; +{ + _RL_FIX_POINT (rl_point); + if (fix_mark_too) + _RL_FIX_POINT (rl_mark); +} +#undef _RL_FIX_POINT + +/* Replace the contents of the line buffer between START and END with + TEXT. The operation is undoable. To replace the entire line in an + undoable mode, use _rl_replace_text(text, 0, rl_end); */ +int +_rl_replace_text (text, start, end) + const char *text; + int start, end; +{ + int n; + + rl_begin_undo_group (); + rl_delete_text (start, end + 1); + rl_point = start; + n = rl_insert_text (text); + rl_end_undo_group (); + + return n; +} + +/* Replace the current line buffer contents with TEXT. If CLEAR_UNDO is + non-zero, we free the current undo list. */ +void +rl_replace_line (text, clear_undo) + const char *text; + int clear_undo; +{ + int len; + + len = strlen (text); + if (len >= rl_line_buffer_len) + rl_extend_line_buffer (len); + strcpy (rl_line_buffer, text); + rl_end = len; + + if (clear_undo) + rl_free_undo_list (); + + _rl_fix_point (1); +} + +/* **************************************************************** */ +/* */ +/* Readline character functions */ +/* */ +/* **************************************************************** */ + +/* This is not a gap editor, just a stupid line input routine. No hair + is involved in writing any of the functions, and none should be. */ + +/* Note that: + + rl_end is the place in the string that we would place '\0'; + i.e., it is always safe to place '\0' there. + + rl_point is the place in the string where the cursor is. Sometimes + this is the same as rl_end. + + Any command that is called interactively receives two arguments. + The first is a count: the numeric arg pased to this command. + The second is the key which invoked this command. +*/ + +/* **************************************************************** */ +/* */ +/* Movement Commands */ +/* */ +/* **************************************************************** */ + +/* Note that if you `optimize' the display for these functions, you cannot + use said functions in other functions which do not do optimizing display. + I.e., you will have to update the data base for rl_redisplay, and you + might as well let rl_redisplay do that job. */ + +/* Move forward COUNT bytes. */ +int +rl_forward_byte (count, key) + int count, key; +{ + if (count < 0) + return (rl_backward_byte (-count, key)); + + if (count > 0) + { + int end = rl_point + count; +#if defined (VI_MODE) + int lend = rl_end > 0 ? rl_end - (rl_editing_mode == vi_mode) : rl_end; +#else + int lend = rl_end; +#endif + + if (end > lend) + { + rl_point = lend; + rl_ding (); + } + else + rl_point = end; + } + + if (rl_end < 0) + rl_end = 0; + + return 0; +} + +#if defined (HANDLE_MULTIBYTE) +/* Move forward COUNT characters. */ +int +rl_forward_char (count, key) + int count, key; +{ + int point; + + if (MB_CUR_MAX == 1 || rl_byte_oriented) + return (rl_forward_byte (count, key)); + + if (count < 0) + return (rl_backward_char (-count, key)); + + if (count > 0) + { + point = _rl_find_next_mbchar (rl_line_buffer, rl_point, count, MB_FIND_NONZERO); + +#if defined (VI_MODE) + if (rl_end <= point && rl_editing_mode == vi_mode) + point = _rl_find_prev_mbchar (rl_line_buffer, rl_end, MB_FIND_NONZERO); +#endif + + if (rl_point == point) + rl_ding (); + + rl_point = point; + + if (rl_end < 0) + rl_end = 0; + } + + return 0; +} +#else /* !HANDLE_MULTIBYTE */ +int +rl_forward_char (count, key) + int count, key; +{ + return (rl_forward_byte (count, key)); +} +#endif /* !HANDLE_MULTIBYTE */ + +/* Backwards compatibility. */ +int +rl_forward (count, key) + int count, key; +{ + return (rl_forward_char (count, key)); +} + +/* Move backward COUNT bytes. */ +int +rl_backward_byte (count, key) + int count, key; +{ + if (count < 0) + return (rl_forward_byte (-count, key)); + + if (count > 0) + { + if (rl_point < count) + { + rl_point = 0; + rl_ding (); + } + else + rl_point -= count; + } + + if (rl_point < 0) + rl_point = 0; + + return 0; +} + +#if defined (HANDLE_MULTIBYTE) +/* Move backward COUNT characters. */ +int +rl_backward_char (count, key) + int count, key; +{ + int point; + + if (MB_CUR_MAX == 1 || rl_byte_oriented) + return (rl_backward_byte (count, key)); + + if (count < 0) + return (rl_forward_char (-count, key)); + + if (count > 0) + { + point = rl_point; + + while (count > 0 && point > 0) + { + point = _rl_find_prev_mbchar (rl_line_buffer, point, MB_FIND_NONZERO); + count--; + } + if (count > 0) + { + rl_point = 0; + rl_ding (); + } + else + rl_point = point; + } + + return 0; +} +#else +int +rl_backward_char (count, key) + int count, key; +{ + return (rl_backward_byte (count, key)); +} +#endif + +/* Backwards compatibility. */ +int +rl_backward (count, key) + int count, key; +{ + return (rl_backward_char (count, key)); +} + +/* Move to the beginning of the line. */ +int +rl_beg_of_line (count, key) + int count, key; +{ + rl_point = 0; + return 0; +} + +/* Move to the end of the line. */ +int +rl_end_of_line (count, key) + int count, key; +{ + rl_point = rl_end; + return 0; +} + +/* Move forward a word. We do what Emacs does. Handles multibyte chars. */ +int +rl_forward_word (count, key) + int count, key; +{ + int c; + + if (count < 0) + return (rl_backward_word (-count, key)); + + while (count) + { + if (rl_point == rl_end) + return 0; + + /* If we are not in a word, move forward until we are in one. + Then, move forward until we hit a non-alphabetic character. */ + c = _rl_char_value (rl_line_buffer, rl_point); + + if (_rl_walphabetic (c) == 0) + { + rl_point = MB_NEXTCHAR (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + while (rl_point < rl_end) + { + c = _rl_char_value (rl_line_buffer, rl_point); + if (_rl_walphabetic (c)) + break; + rl_point = MB_NEXTCHAR (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + } + } + + if (rl_point == rl_end) + return 0; + + rl_point = MB_NEXTCHAR (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + while (rl_point < rl_end) + { + c = _rl_char_value (rl_line_buffer, rl_point); + if (_rl_walphabetic (c) == 0) + break; + rl_point = MB_NEXTCHAR (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + } + + --count; + } + + return 0; +} + +/* Move backward a word. We do what Emacs does. Handles multibyte chars. */ +int +rl_backward_word (count, key) + int count, key; +{ + int c, p; + + if (count < 0) + return (rl_forward_word (-count, key)); + + while (count) + { + if (rl_point == 0) + return 0; + + /* Like rl_forward_word (), except that we look at the characters + just before point. */ + + p = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_NONZERO); + c = _rl_char_value (rl_line_buffer, p); + + if (_rl_walphabetic (c) == 0) + { + rl_point = p; + while (rl_point > 0) + { + p = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_NONZERO); + c = _rl_char_value (rl_line_buffer, p); + if (_rl_walphabetic (c)) + break; + rl_point = p; + } + } + + while (rl_point) + { + p = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_NONZERO); + c = _rl_char_value (rl_line_buffer, p); + if (_rl_walphabetic (c) == 0) + break; + else + rl_point = p; + } + + --count; + } + + return 0; +} + +/* Clear the current line. Numeric argument to C-l does this. */ +int +rl_refresh_line (ignore1, ignore2) + int ignore1, ignore2; +{ + int curr_line; + + curr_line = _rl_current_display_line (); + + _rl_move_vert (curr_line); + _rl_move_cursor_relative (0, rl_line_buffer); /* XXX is this right */ + + _rl_clear_to_eol (0); /* arg of 0 means to not use spaces */ + + rl_forced_update_display (); + rl_display_fixed = 1; + + return 0; +} + +/* C-l typed to a line without quoting clears the screen, and then reprints + the prompt and the current input line. Given a numeric arg, redraw only + the current line. */ +int +rl_clear_screen (count, key) + int count, key; +{ + if (rl_explicit_arg) + { + rl_refresh_line (count, key); + return 0; + } + + _rl_clear_screen (); /* calls termcap function to clear screen */ + rl_forced_update_display (); + rl_display_fixed = 1; + + return 0; +} + +int +rl_arrow_keys (count, c) + int count, c; +{ + int ch; + + RL_SETSTATE(RL_STATE_MOREINPUT); + ch = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + switch (_rl_to_upper (ch)) + { + case 'A': + rl_get_previous_history (count, ch); + break; + + case 'B': + rl_get_next_history (count, ch); + break; + + case 'C': + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_forward_char (count, ch); + else + rl_forward_byte (count, ch); + break; + + case 'D': + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_backward_char (count, ch); + else + rl_backward_byte (count, ch); + break; + + default: + rl_ding (); + } + + return 0; +} + +/* **************************************************************** */ +/* */ +/* Text commands */ +/* */ +/* **************************************************************** */ + +#ifdef HANDLE_MULTIBYTE +static char pending_bytes[MB_LEN_MAX]; +static int pending_bytes_length = 0; +static mbstate_t ps = {0}; +#endif + +/* Insert the character C at the current location, moving point forward. + If C introduces a multibyte sequence, we read the whole sequence and + then insert the multibyte char into the line buffer. */ +int +_rl_insert_char (count, c) + int count, c; +{ + register int i; + char *string; +#ifdef HANDLE_MULTIBYTE + int string_size; + char incoming[MB_LEN_MAX + 1]; + int incoming_length = 0; + mbstate_t ps_back; + static int stored_count = 0; +#endif + + if (count <= 0) + return 0; + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX == 1 || rl_byte_oriented) + { + incoming[0] = c; + incoming[1] = '\0'; + incoming_length = 1; + } + else + { + wchar_t wc; + size_t ret; + + if (stored_count <= 0) + stored_count = count; + else + count = stored_count; + + ps_back = ps; + pending_bytes[pending_bytes_length++] = c; + ret = mbrtowc (&wc, pending_bytes, pending_bytes_length, &ps); + + if (ret == (size_t)-2) + { + /* Bytes too short to compose character, try to wait for next byte. + Restore the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + ps = ps_back; + return 1; + } + else if (ret == (size_t)-1) + { + /* Invalid byte sequence for the current locale. Treat first byte + as a single character. */ + incoming[0] = pending_bytes[0]; + incoming[1] = '\0'; + incoming_length = 1; + pending_bytes_length--; + memmove (pending_bytes, pending_bytes + 1, pending_bytes_length); + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else if (ret == (size_t)0) + { + incoming[0] = '\0'; + incoming_length = 0; + pending_bytes_length--; + /* Clear the state of the byte sequence, because in this case the + effect of mbstate is undefined. */ + memset (&ps, 0, sizeof (mbstate_t)); + } + else + { + /* We successfully read a single multibyte character. */ + memcpy (incoming, pending_bytes, pending_bytes_length); + incoming[pending_bytes_length] = '\0'; + incoming_length = pending_bytes_length; + pending_bytes_length = 0; + } + } +#endif /* HANDLE_MULTIBYTE */ + + /* If we can optimize, then do it. But don't let people crash + readline because of extra large arguments. */ + if (count > 1 && count <= 1024) + { +#if defined (HANDLE_MULTIBYTE) + string_size = count * incoming_length; + string = (char *)xmalloc (1 + string_size); + + i = 0; + while (i < string_size) + { + strncpy (string + i, incoming, incoming_length); + i += incoming_length; + } + incoming_length = 0; + stored_count = 0; +#else /* !HANDLE_MULTIBYTE */ + string = (char *)xmalloc (1 + count); + + for (i = 0; i < count; i++) + string[i] = c; +#endif /* !HANDLE_MULTIBYTE */ + + string[i] = '\0'; + rl_insert_text (string); + free (string); + + return 0; + } + + if (count > 1024) + { + int decreaser; +#if defined (HANDLE_MULTIBYTE) + string_size = incoming_length * 1024; + string = (char *)xmalloc (1 + string_size); + + i = 0; + while (i < string_size) + { + strncpy (string + i, incoming, incoming_length); + i += incoming_length; + } + + while (count) + { + decreaser = (count > 1024) ? 1024 : count; + string[decreaser*incoming_length] = '\0'; + rl_insert_text (string); + count -= decreaser; + } + + free (string); + incoming_length = 0; + stored_count = 0; +#else /* !HANDLE_MULTIBYTE */ + char str[1024+1]; + + for (i = 0; i < 1024; i++) + str[i] = c; + + while (count) + { + decreaser = (count > 1024 ? 1024 : count); + str[decreaser] = '\0'; + rl_insert_text (str); + count -= decreaser; + } +#endif /* !HANDLE_MULTIBYTE */ + + return 0; + } + + if (MB_CUR_MAX == 1 || rl_byte_oriented) + { + /* We are inserting a single character. + If there is pending input, then make a string of all of the + pending characters that are bound to rl_insert, and insert + them all. */ + if (_rl_any_typein ()) + _rl_insert_typein (c); + else + { + /* Inserting a single character. */ + char str[2]; + + str[1] = '\0'; + str[0] = c; + rl_insert_text (str); + } + } +#if defined (HANDLE_MULTIBYTE) + else + { + rl_insert_text (incoming); + stored_count = 0; + } +#endif + + return 0; +} + +/* Overwrite the character at point (or next COUNT characters) with C. + If C introduces a multibyte character sequence, read the entire sequence + before starting the overwrite loop. */ +int +_rl_overwrite_char (count, c) + int count, c; +{ + int i; +#if defined (HANDLE_MULTIBYTE) + char mbkey[MB_LEN_MAX]; + int k; + + /* Read an entire multibyte character sequence to insert COUNT times. */ + if (count > 0 && MB_CUR_MAX > 1 && rl_byte_oriented == 0) + k = _rl_read_mbstring (c, mbkey, MB_LEN_MAX); +#endif + + rl_begin_undo_group (); + + for (i = 0; i < count; i++) + { +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_insert_text (mbkey); + else +#endif + _rl_insert_char (1, c); + + if (rl_point < rl_end) + rl_delete (1, c); + } + + rl_end_undo_group (); + + return 0; +} + +int +rl_insert (count, c) + int count, c; +{ + return (rl_insert_mode == RL_IM_INSERT ? _rl_insert_char (count, c) + : _rl_overwrite_char (count, c)); +} + +/* Insert the next typed character verbatim. */ +static int +_rl_insert_next (count) + int count; +{ + int c; + + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + +#if defined (HANDLE_SIGNALS) + if (RL_ISSTATE (RL_STATE_CALLBACK) == 0) + _rl_restore_tty_signals (); +#endif + + return (_rl_insert_char (count, c)); +} + +#if defined (READLINE_CALLBACKS) +static int +_rl_insert_next_callback (data) + _rl_callback_generic_arg *data; +{ + int count; + + count = data->count; + + /* Deregister function, let rl_callback_read_char deallocate data */ + _rl_callback_func = 0; + _rl_want_redisplay = 1; + + return _rl_insert_next (count); +} +#endif + +int +rl_quoted_insert (count, key) + int count, key; +{ + /* Let's see...should the callback interface futz with signal handling? */ +#if defined (HANDLE_SIGNALS) + if (RL_ISSTATE (RL_STATE_CALLBACK) == 0) + _rl_disable_tty_signals (); +#endif + +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = _rl_callback_data_alloc (count); + _rl_callback_func = _rl_insert_next_callback; + return (0); + } +#endif + + return _rl_insert_next (count); +} + +/* Insert a tab character. */ +int +rl_tab_insert (count, key) + int count, key; +{ + return (_rl_insert_char (count, '\t')); +} + +/* What to do when a NEWLINE is pressed. We accept the whole line. + KEY is the key that invoked this command. I guess it could have + meaning in the future. */ +int +rl_newline (count, key) + int count, key; +{ + rl_done = 1; + + if (_rl_history_preserve_point) + _rl_history_saved_point = (rl_point == rl_end) ? -1 : rl_point; + + RL_SETSTATE(RL_STATE_DONE); + +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + { + _rl_vi_done_inserting (); + if (_rl_vi_textmod_command (_rl_vi_last_command) == 0) /* XXX */ + _rl_vi_reset_last (); + } +#endif /* VI_MODE */ + + /* If we've been asked to erase empty lines, suppress the final update, + since _rl_update_final calls rl_crlf(). */ + if (rl_erase_empty_line && rl_point == 0 && rl_end == 0) + return 0; + + if (readline_echoing_p) + _rl_update_final (); + return 0; +} + +/* What to do for some uppercase characters, like meta characters, + and some characters appearing in emacs_ctlx_keymap. This function + is just a stub, you bind keys to it and the code in _rl_dispatch () + is special cased. */ +int +rl_do_lowercase_version (ignore1, ignore2) + int ignore1, ignore2; +{ + return 0; +} + +/* This is different from what vi does, so the code's not shared. Emacs + rubout in overwrite mode has one oddity: it replaces a control + character that's displayed as two characters (^X) with two spaces. */ +int +_rl_overwrite_rubout (count, key) + int count, key; +{ + int opoint; + int i, l; + + if (rl_point == 0) + { + rl_ding (); + return 1; + } + + opoint = rl_point; + + /* L == number of spaces to insert */ + for (i = l = 0; i < count; i++) + { + rl_backward_char (1, key); + l += rl_character_len (rl_line_buffer[rl_point], rl_point); /* not exactly right */ + } + + rl_begin_undo_group (); + + if (count > 1 || rl_explicit_arg) + rl_kill_text (opoint, rl_point); + else + rl_delete_text (opoint, rl_point); + + /* Emacs puts point at the beginning of the sequence of spaces. */ + if (rl_point < rl_end) + { + opoint = rl_point; + _rl_insert_char (l, ' '); + rl_point = opoint; + } + + rl_end_undo_group (); + + return 0; +} + +/* Rubout the character behind point. */ +int +rl_rubout (count, key) + int count, key; +{ + if (count < 0) + return (rl_delete (-count, key)); + + if (!rl_point) + { + rl_ding (); + return -1; + } + + if (rl_insert_mode == RL_IM_OVERWRITE) + return (_rl_overwrite_rubout (count, key)); + + return (_rl_rubout_char (count, key)); +} + +int +_rl_rubout_char (count, key) + int count, key; +{ + int orig_point; + unsigned char c; + + /* Duplicated code because this is called from other parts of the library. */ + if (count < 0) + return (rl_delete (-count, key)); + + if (rl_point == 0) + { + rl_ding (); + return -1; + } + + orig_point = rl_point; + if (count > 1 || rl_explicit_arg) + { + rl_backward_char (count, key); + rl_kill_text (orig_point, rl_point); + } + else if (MB_CUR_MAX == 1 || rl_byte_oriented) + { + c = rl_line_buffer[--rl_point]; + rl_delete_text (rl_point, orig_point); + /* The erase-at-end-of-line hack is of questionable merit now. */ + if (rl_point == rl_end && ISPRINT (c) && _rl_last_c_pos) + { + int l; + l = rl_character_len (c, rl_point); + _rl_erase_at_end_of_line (l); + } + } + else + { + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + rl_delete_text (rl_point, orig_point); + } + + return 0; +} + +/* Delete the character under the cursor. Given a numeric argument, + kill that many characters instead. */ +int +rl_delete (count, key) + int count, key; +{ + if (count < 0) + return (_rl_rubout_char (-count, key)); + + if (rl_point == rl_end) + { + rl_ding (); + return -1; + } + + if (count > 1 || rl_explicit_arg) + { + int orig_point = rl_point; + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_forward_char (count, key); + else + rl_forward_byte (count, key); + + rl_kill_text (orig_point, rl_point); + rl_point = orig_point; + } + else + { + int new_point; + + new_point = MB_NEXTCHAR (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + rl_delete_text (rl_point, new_point); + } + return 0; +} + +/* Delete the character under the cursor, unless the insertion + point is at the end of the line, in which case the character + behind the cursor is deleted. COUNT is obeyed and may be used + to delete forward or backward that many characters. */ +int +rl_rubout_or_delete (count, key) + int count, key; +{ + if (rl_end != 0 && rl_point == rl_end) + return (_rl_rubout_char (count, key)); + else + return (rl_delete (count, key)); +} + +/* Delete all spaces and tabs around point. */ +int +rl_delete_horizontal_space (count, ignore) + int count, ignore; +{ + int start = rl_point; + + while (rl_point && whitespace (rl_line_buffer[rl_point - 1])) + rl_point--; + + start = rl_point; + + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + + if (start != rl_point) + { + rl_delete_text (start, rl_point); + rl_point = start; + } + + if (rl_point < 0) + rl_point = 0; + + return 0; +} + +/* Like the tcsh editing function delete-char-or-list. The eof character + is caught before this is invoked, so this really does the same thing as + delete-char-or-list-or-eof, as long as it's bound to the eof character. */ +int +rl_delete_or_show_completions (count, key) + int count, key; +{ + if (rl_end != 0 && rl_point == rl_end) + return (rl_possible_completions (count, key)); + else + return (rl_delete (count, key)); +} + +#ifndef RL_COMMENT_BEGIN_DEFAULT +#define RL_COMMENT_BEGIN_DEFAULT "#" +#endif + +/* Turn the current line into a comment in shell history. + A K*rn shell style function. */ +int +rl_insert_comment (count, key) + int count, key; +{ + char *rl_comment_text; + int rl_comment_len; + + rl_beg_of_line (1, key); + rl_comment_text = _rl_comment_begin ? _rl_comment_begin : RL_COMMENT_BEGIN_DEFAULT; + + if (rl_explicit_arg == 0) + rl_insert_text (rl_comment_text); + else + { + rl_comment_len = strlen (rl_comment_text); + if (STREQN (rl_comment_text, rl_line_buffer, rl_comment_len)) + rl_delete_text (rl_point, rl_point + rl_comment_len); + else + rl_insert_text (rl_comment_text); + } + + (*rl_redisplay_function) (); + rl_newline (1, '\n'); + + return (0); +} + +/* **************************************************************** */ +/* */ +/* Changing Case */ +/* */ +/* **************************************************************** */ + +/* The three kinds of things that we know how to do. */ +#define UpCase 1 +#define DownCase 2 +#define CapCase 3 + +/* Uppercase the word at point. */ +int +rl_upcase_word (count, key) + int count, key; +{ + return (rl_change_case (count, UpCase)); +} + +/* Lowercase the word at point. */ +int +rl_downcase_word (count, key) + int count, key; +{ + return (rl_change_case (count, DownCase)); +} + +/* Upcase the first letter, downcase the rest. */ +int +rl_capitalize_word (count, key) + int count, key; +{ + return (rl_change_case (count, CapCase)); +} + +/* The meaty function. + Change the case of COUNT words, performing OP on them. + OP is one of UpCase, DownCase, or CapCase. + If a negative argument is given, leave point where it started, + otherwise, leave it where it moves to. */ +static int +rl_change_case (count, op) + int count, op; +{ + int start, next, end; + int inword, c, nc, nop; +#if defined (HANDLE_MULTIBYTE) + wchar_t wc, nwc; + char mb[MB_LEN_MAX+1]; + int mblen, p; + mbstate_t ps; +#endif + + start = rl_point; + rl_forward_word (count, 0); + end = rl_point; + + if (op != UpCase && op != DownCase && op != CapCase) + { + rl_ding (); + return -1; + } + + if (count < 0) + SWAP (start, end); + +#if defined (HANDLE_MULTIBYTE) + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + /* We are going to modify some text, so let's prepare to undo it. */ + rl_modifying (start, end); + + inword = 0; + while (start < end) + { + c = _rl_char_value (rl_line_buffer, start); + /* This assumes that the upper and lower case versions are the same width. */ + next = MB_NEXTCHAR (rl_line_buffer, start, 1, MB_FIND_NONZERO); + + if (_rl_walphabetic (c) == 0) + { + inword = 0; + start = next; + continue; + } + + if (op == CapCase) + { + nop = inword ? DownCase : UpCase; + inword = 1; + } + else + nop = op; + if (MB_CUR_MAX == 1 || rl_byte_oriented || isascii (c)) + { + nc = (nop == UpCase) ? _rl_to_upper (c) : _rl_to_lower (c); + rl_line_buffer[start] = nc; + } +#if defined (HANDLE_MULTIBYTE) + else + { + mbrtowc (&wc, rl_line_buffer + start, end - start, &ps); + nwc = (nop == UpCase) ? _rl_to_wupper (wc) : _rl_to_wlower (wc); + if (nwc != wc) /* just skip unchanged characters */ + { + mblen = wcrtomb (mb, nwc, &ps); + if (mblen > 0) + mb[mblen] = '\0'; + /* Assume the same width */ + strncpy (rl_line_buffer + start, mb, mblen); + } + } +#endif + + start = next; + } + + rl_point = end; + return 0; +} + +/* **************************************************************** */ +/* */ +/* Transposition */ +/* */ +/* **************************************************************** */ + +/* Transpose the words at point. If point is at the end of the line, + transpose the two words before point. */ +int +rl_transpose_words (count, key) + int count, key; +{ + char *word1, *word2; + int w1_beg, w1_end, w2_beg, w2_end; + int orig_point = rl_point; + + if (!count) + return 0; + + /* Find the two words. */ + rl_forward_word (count, key); + w2_end = rl_point; + rl_backward_word (1, key); + w2_beg = rl_point; + rl_backward_word (count, key); + w1_beg = rl_point; + rl_forward_word (1, key); + w1_end = rl_point; + + /* Do some check to make sure that there really are two words. */ + if ((w1_beg == w2_beg) || (w2_beg < w1_end)) + { + rl_ding (); + rl_point = orig_point; + return -1; + } + + /* Get the text of the words. */ + word1 = rl_copy_text (w1_beg, w1_end); + word2 = rl_copy_text (w2_beg, w2_end); + + /* We are about to do many insertions and deletions. Remember them + as one operation. */ + rl_begin_undo_group (); + + /* Do the stuff at word2 first, so that we don't have to worry + about word1 moving. */ + rl_point = w2_beg; + rl_delete_text (w2_beg, w2_end); + rl_insert_text (word1); + + rl_point = w1_beg; + rl_delete_text (w1_beg, w1_end); + rl_insert_text (word2); + + /* This is exactly correct since the text before this point has not + changed in length. */ + rl_point = w2_end; + + /* I think that does it. */ + rl_end_undo_group (); + free (word1); + free (word2); + + return 0; +} + +/* Transpose the characters at point. If point is at the end of the line, + then transpose the characters before point. */ +int +rl_transpose_chars (count, key) + int count, key; +{ +#if defined (HANDLE_MULTIBYTE) + char *dummy; + int i; +#else + char dummy[2]; +#endif + int char_length, prev_point; + + if (count == 0) + return 0; + + if (!rl_point || rl_end < 2) + { + rl_ding (); + return -1; + } + + rl_begin_undo_group (); + + if (rl_point == rl_end) + { + rl_point = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_NONZERO); + count = 1; + } + + prev_point = rl_point; + rl_point = MB_PREVCHAR (rl_line_buffer, rl_point, MB_FIND_NONZERO); + +#if defined (HANDLE_MULTIBYTE) + char_length = prev_point - rl_point; + dummy = (char *)xmalloc (char_length + 1); + for (i = 0; i < char_length; i++) + dummy[i] = rl_line_buffer[rl_point + i]; + dummy[i] = '\0'; +#else + dummy[0] = rl_line_buffer[rl_point]; + dummy[char_length = 1] = '\0'; +#endif + + rl_delete_text (rl_point, rl_point + char_length); + + rl_point = _rl_find_next_mbchar (rl_line_buffer, rl_point, count, MB_FIND_NONZERO); + + _rl_fix_point (0); + rl_insert_text (dummy); + rl_end_undo_group (); + +#if defined (HANDLE_MULTIBYTE) + free (dummy); +#endif + + return 0; +} + +/* **************************************************************** */ +/* */ +/* Character Searching */ +/* */ +/* **************************************************************** */ + +int +#if defined (HANDLE_MULTIBYTE) +_rl_char_search_internal (count, dir, smbchar, len) + int count, dir; + char *smbchar; + int len; +#else +_rl_char_search_internal (count, dir, schar) + int count, dir, schar; +#endif +{ + int pos, inc; +#if defined (HANDLE_MULTIBYTE) + int prepos; +#endif + + pos = rl_point; + inc = (dir < 0) ? -1 : 1; + while (count) + { + if ((dir < 0 && pos <= 0) || (dir > 0 && pos >= rl_end)) + { + rl_ding (); + return -1; + } + +#if defined (HANDLE_MULTIBYTE) + pos = (inc > 0) ? _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY) + : _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY); +#else + pos += inc; +#endif + do + { +#if defined (HANDLE_MULTIBYTE) + if (_rl_is_mbchar_matched (rl_line_buffer, pos, rl_end, smbchar, len)) +#else + if (rl_line_buffer[pos] == schar) +#endif + { + count--; + if (dir < 0) + rl_point = (dir == BTO) ? _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY) + : pos; + else + rl_point = (dir == FTO) ? _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY) + : pos; + break; + } +#if defined (HANDLE_MULTIBYTE) + prepos = pos; +#endif + } +#if defined (HANDLE_MULTIBYTE) + while ((dir < 0) ? (pos = _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY)) != prepos + : (pos = _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY)) != prepos); +#else + while ((dir < 0) ? pos-- : ++pos < rl_end); +#endif + } + return (0); +} + +/* Search COUNT times for a character read from the current input stream. + FDIR is the direction to search if COUNT is non-negative; otherwise + the search goes in BDIR. So much is dependent on HANDLE_MULTIBYTE + that there are two separate versions of this function. */ +#if defined (HANDLE_MULTIBYTE) +static int +_rl_char_search (count, fdir, bdir) + int count, fdir, bdir; +{ + char mbchar[MB_LEN_MAX]; + int mb_len; + + mb_len = _rl_read_mbchar (mbchar, MB_LEN_MAX); + + if (count < 0) + return (_rl_char_search_internal (-count, bdir, mbchar, mb_len)); + else + return (_rl_char_search_internal (count, fdir, mbchar, mb_len)); +} +#else /* !HANDLE_MULTIBYTE */ +static int +_rl_char_search (count, fdir, bdir) + int count, fdir, bdir; +{ + int c; + + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (count < 0) + return (_rl_char_search_internal (-count, bdir, c)); + else + return (_rl_char_search_internal (count, fdir, c)); +} +#endif /* !HANDLE_MULTIBYTE */ + +#if defined (READLINE_CALLBACKS) +static int +_rl_char_search_callback (data) + _rl_callback_generic_arg *data; +{ + _rl_callback_func = 0; + _rl_want_redisplay = 1; + + return (_rl_char_search (data->count, data->i1, data->i2)); +} +#endif + +int +rl_char_search (count, key) + int count, key; +{ +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = _rl_callback_data_alloc (count); + _rl_callback_data->i1 = FFIND; + _rl_callback_data->i2 = BFIND; + _rl_callback_func = _rl_char_search_callback; + return (0); + } +#endif + + return (_rl_char_search (count, FFIND, BFIND)); +} + +int +rl_backward_char_search (count, key) + int count, key; +{ +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = _rl_callback_data_alloc (count); + _rl_callback_data->i1 = BFIND; + _rl_callback_data->i2 = FFIND; + _rl_callback_func = _rl_char_search_callback; + return (0); + } +#endif + + return (_rl_char_search (count, BFIND, FFIND)); +} + +/* **************************************************************** */ +/* */ +/* The Mark and the Region. */ +/* */ +/* **************************************************************** */ + +/* Set the mark at POSITION. */ +int +_rl_set_mark_at_pos (position) + int position; +{ + if (position > rl_end) + return -1; + + rl_mark = position; + return 0; +} + +/* A bindable command to set the mark. */ +int +rl_set_mark (count, key) + int count, key; +{ + return (_rl_set_mark_at_pos (rl_explicit_arg ? count : rl_point)); +} + +/* Exchange the position of mark and point. */ +int +rl_exchange_point_and_mark (count, key) + int count, key; +{ + if (rl_mark > rl_end) + rl_mark = -1; + + if (rl_mark == -1) + { + rl_ding (); + return -1; + } + else + SWAP (rl_point, rl_mark); + + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/tilde.c b/external/gpl3/gdb/dist/readline/tilde.c new file mode 100644 index 000000000000..32f3d3cf3808 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/tilde.c @@ -0,0 +1,502 @@ +/* tilde.c -- Tilde expansion code (~/foo := $HOME/foo). */ + +/* Copyright (C) 1988,1989 Free Software Foundation, Inc. + + This file is part of GNU Readline, a library for reading lines + of text with interactive input and history editing. + + Readline is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + Readline is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Readline; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#if defined (HAVE_UNISTD_H) +# ifdef _MINIX +# include +# endif +# include +#endif + +#if defined (HAVE_STRING_H) +# include +#else /* !HAVE_STRING_H */ +# include +#endif /* !HAVE_STRING_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include +#if defined (HAVE_PWD_H) +#include +#endif + +#include "tilde.h" + +#if defined (TEST) || defined (STATIC_MALLOC) +static void *xmalloc (), *xrealloc (); +#else +# include "xmalloc.h" +#endif /* TEST || STATIC_MALLOC */ + +#if !defined (HAVE_GETPW_DECLS) +# if defined (HAVE_GETPWUID) +extern struct passwd *getpwuid PARAMS((uid_t)); +# endif +# if defined (HAVE_GETPWNAM) +extern struct passwd *getpwnam PARAMS((const char *)); +# endif +#endif /* !HAVE_GETPW_DECLS */ + +#if !defined (savestring) +#define savestring(x) strcpy ((char *)xmalloc (1 + strlen (x)), (x)) +#endif /* !savestring */ + +#if !defined (NULL) +# if defined (__STDC__) +# define NULL ((void *) 0) +# else +# define NULL 0x0 +# endif /* !__STDC__ */ +#endif /* !NULL */ + +/* If being compiled as part of bash, these will be satisfied from + variables.o. If being compiled as part of readline, they will + be satisfied from shell.o. */ +extern char *sh_get_home_dir PARAMS((void)); +extern char *sh_get_env_value PARAMS((const char *)); + +/* The default value of tilde_additional_prefixes. This is set to + whitespace preceding a tilde so that simple programs which do not + perform any word separation get desired behaviour. */ +static const char *default_prefixes[] = + { " ~", "\t~", (const char *)NULL }; + +/* The default value of tilde_additional_suffixes. This is set to + whitespace or newline so that simple programs which do not + perform any word separation get desired behaviour. */ +static const char *default_suffixes[] = + { " ", "\n", (const char *)NULL }; + +/* If non-null, this contains the address of a function that the application + wants called before trying the standard tilde expansions. The function + is called with the text sans tilde, and returns a malloc()'ed string + which is the expansion, or a NULL pointer if the expansion fails. */ +tilde_hook_func_t *tilde_expansion_preexpansion_hook = (tilde_hook_func_t *)NULL; + +/* If non-null, this contains the address of a function to call if the + standard meaning for expanding a tilde fails. The function is called + with the text (sans tilde, as in "foo"), and returns a malloc()'ed string + which is the expansion, or a NULL pointer if there is no expansion. */ +tilde_hook_func_t *tilde_expansion_failure_hook = (tilde_hook_func_t *)NULL; + +/* When non-null, this is a NULL terminated array of strings which + are duplicates for a tilde prefix. Bash uses this to expand + `=~' and `:~'. */ +char **tilde_additional_prefixes = (char **)default_prefixes; + +/* When non-null, this is a NULL terminated array of strings which match + the end of a username, instead of just "/". Bash sets this to + `:' and `=~'. */ +char **tilde_additional_suffixes = (char **)default_suffixes; + +static int tilde_find_prefix PARAMS((const char *, int *)); +static int tilde_find_suffix PARAMS((const char *)); +static char *isolate_tilde_prefix PARAMS((const char *, int *)); +static char *glue_prefix_and_suffix PARAMS((char *, const char *, int)); + +/* Find the start of a tilde expansion in STRING, and return the index of + the tilde which starts the expansion. Place the length of the text + which identified this tilde starter in LEN, excluding the tilde itself. */ +static int +tilde_find_prefix (string, len) + const char *string; + int *len; +{ + register int i, j, string_len; + register char **prefixes; + + prefixes = tilde_additional_prefixes; + + string_len = strlen (string); + *len = 0; + + if (*string == '\0' || *string == '~') + return (0); + + if (prefixes) + { + for (i = 0; i < string_len; i++) + { + for (j = 0; prefixes[j]; j++) + { + if (strncmp (string + i, prefixes[j], strlen (prefixes[j])) == 0) + { + *len = strlen (prefixes[j]) - 1; + return (i + *len); + } + } + } + } + return (string_len); +} + +/* Find the end of a tilde expansion in STRING, and return the index of + the character which ends the tilde definition. */ +static int +tilde_find_suffix (string) + const char *string; +{ + register int i, j, string_len; + register char **suffixes; + + suffixes = tilde_additional_suffixes; + string_len = strlen (string); + + for (i = 0; i < string_len; i++) + { +#if defined (__MSDOS__) + if (string[i] == '/' || string[i] == '\\' /* || !string[i] */) +#else + if (string[i] == '/' /* || !string[i] */) +#endif + break; + + for (j = 0; suffixes && suffixes[j]; j++) + { + if (strncmp (string + i, suffixes[j], strlen (suffixes[j])) == 0) + return (i); + } + } + return (i); +} + +/* Return a new string which is the result of tilde expanding STRING. */ +char * +tilde_expand (string) + const char *string; +{ + char *result; + int result_size, result_index; + + result_index = result_size = 0; + if (result = strchr (string, '~')) + result = (char *)xmalloc (result_size = (strlen (string) + 16)); + else + result = (char *)xmalloc (result_size = (strlen (string) + 1)); + + /* Scan through STRING expanding tildes as we come to them. */ + while (1) + { + register int start, end; + char *tilde_word, *expansion; + int len; + + /* Make START point to the tilde which starts the expansion. */ + start = tilde_find_prefix (string, &len); + + /* Copy the skipped text into the result. */ + if ((result_index + start + 1) > result_size) + result = (char *)xrealloc (result, 1 + (result_size += (start + 20))); + + strncpy (result + result_index, string, start); + result_index += start; + + /* Advance STRING to the starting tilde. */ + string += start; + + /* Make END be the index of one after the last character of the + username. */ + end = tilde_find_suffix (string); + + /* If both START and END are zero, we are all done. */ + if (!start && !end) + break; + + /* Expand the entire tilde word, and copy it into RESULT. */ + tilde_word = (char *)xmalloc (1 + end); + strncpy (tilde_word, string, end); + tilde_word[end] = '\0'; + string += end; + + expansion = tilde_expand_word (tilde_word); + free (tilde_word); + + len = strlen (expansion); +#ifdef __CYGWIN__ + /* Fix for Cygwin to prevent ~user/xxx from expanding to //xxx when + $HOME for `user' is /. On cygwin, // denotes a network drive. */ + if (len > 1 || *expansion != '/' || *string != '/') +#endif + { + if ((result_index + len + 1) > result_size) + result = (char *)xrealloc (result, 1 + (result_size += (len + 20))); + + strcpy (result + result_index, expansion); + result_index += len; + } + free (expansion); + } + + result[result_index] = '\0'; + + return (result); +} + +/* Take FNAME and return the tilde prefix we want expanded. If LENP is + non-null, the index of the end of the prefix into FNAME is returned in + the location it points to. */ +static char * +isolate_tilde_prefix (fname, lenp) + const char *fname; + int *lenp; +{ + char *ret; + int i; + + ret = (char *)xmalloc (strlen (fname)); +#if defined (__MSDOS__) + for (i = 1; fname[i] && fname[i] != '/' && fname[i] != '\\'; i++) +#else + for (i = 1; fname[i] && fname[i] != '/'; i++) +#endif + ret[i - 1] = fname[i]; + ret[i - 1] = '\0'; + if (lenp) + *lenp = i; + return ret; +} + +#if 0 +/* Public function to scan a string (FNAME) beginning with a tilde and find + the portion of the string that should be passed to the tilde expansion + function. Right now, it just calls tilde_find_suffix and allocates new + memory, but it can be expanded to do different things later. */ +char * +tilde_find_word (fname, flags, lenp) + const char *fname; + int flags, *lenp; +{ + int x; + char *r; + + x = tilde_find_suffix (fname); + if (x == 0) + { + r = savestring (fname); + if (lenp) + *lenp = 0; + } + else + { + r = (char *)xmalloc (1 + x); + strncpy (r, fname, x); + r[x] = '\0'; + if (lenp) + *lenp = x; + } + + return r; +} +#endif + +/* Return a string that is PREFIX concatenated with SUFFIX starting at + SUFFIND. */ +static char * +glue_prefix_and_suffix (prefix, suffix, suffind) + char *prefix; + const char *suffix; + int suffind; +{ + char *ret; + int plen, slen; + + plen = (prefix && *prefix) ? strlen (prefix) : 0; + slen = strlen (suffix + suffind); + ret = (char *)xmalloc (plen + slen + 1); + if (plen) + strcpy (ret, prefix); + strcpy (ret + plen, suffix + suffind); + return ret; +} + +/* Do the work of tilde expansion on FILENAME. FILENAME starts with a + tilde. If there is no expansion, call tilde_expansion_failure_hook. + This always returns a newly-allocated string, never static storage. */ +char * +tilde_expand_word (filename) + const char *filename; +{ + char *dirname, *expansion, *username; + int user_len; + struct passwd *user_entry; + + if (filename == 0) + return ((char *)NULL); + + if (*filename != '~') + return (savestring (filename)); + + /* A leading `~/' or a bare `~' is *always* translated to the value of + $HOME or the home directory of the current user, regardless of any + preexpansion hook. */ + if (filename[1] == '\0' || filename[1] == '/') + { + /* Prefix $HOME to the rest of the string. */ + expansion = sh_get_env_value ("HOME"); + + /* If there is no HOME variable, look up the directory in + the password database. */ + if (expansion == 0) + expansion = sh_get_home_dir (); + + return (glue_prefix_and_suffix (expansion, filename, 1)); + } + + username = isolate_tilde_prefix (filename, &user_len); + + if (tilde_expansion_preexpansion_hook) + { + expansion = (*tilde_expansion_preexpansion_hook) (username); + if (expansion) + { + dirname = glue_prefix_and_suffix (expansion, filename, user_len); + free (username); + free (expansion); + return (dirname); + } + } + + /* No preexpansion hook, or the preexpansion hook failed. Look in the + password database. */ + dirname = (char *)NULL; +#if defined (HAVE_GETPWNAM) + user_entry = getpwnam (username); +#else + user_entry = 0; +#endif + if (user_entry == 0) + { + /* If the calling program has a special syntax for expanding tildes, + and we couldn't find a standard expansion, then let them try. */ + if (tilde_expansion_failure_hook) + { + expansion = (*tilde_expansion_failure_hook) (username); + if (expansion) + { + dirname = glue_prefix_and_suffix (expansion, filename, user_len); + free (expansion); + } + } + free (username); + /* If we don't have a failure hook, or if the failure hook did not + expand the tilde, return a copy of what we were passed. */ + if (dirname == 0) + dirname = savestring (filename); + } +#if defined (HAVE_GETPWENT) + else + { + free (username); + dirname = glue_prefix_and_suffix (user_entry->pw_dir, filename, user_len); + } + endpwent (); +#endif + return (dirname); +} + + +#if defined (TEST) +#undef NULL +#include + +main (argc, argv) + int argc; + char **argv; +{ + char *result, line[512]; + int done = 0; + + while (!done) + { + printf ("~expand: "); + fflush (stdout); + + if (!gets (line)) + strcpy (line, "done"); + + if ((strcmp (line, "done") == 0) || + (strcmp (line, "quit") == 0) || + (strcmp (line, "exit") == 0)) + { + done = 1; + break; + } + + result = tilde_expand (line); + printf (" --> %s\n", result); + free (result); + } + exit (0); +} + +static void memory_error_and_abort (); + +static void * +xmalloc (bytes) + size_t bytes; +{ + void *temp = (char *)malloc (bytes); + + if (!temp) + memory_error_and_abort (); + return (temp); +} + +static void * +xrealloc (pointer, bytes) + void *pointer; + int bytes; +{ + void *temp; + + if (!pointer) + temp = malloc (bytes); + else + temp = realloc (pointer, bytes); + + if (!temp) + memory_error_and_abort (); + + return (temp); +} + +static void +memory_error_and_abort () +{ + fprintf (stderr, "readline: out of virtual memory\n"); + abort (); +} + +/* + * Local variables: + * compile-command: "gcc -g -DTEST -o tilde tilde.c" + * end: + */ +#endif /* TEST */ diff --git a/external/gpl3/gdb/dist/readline/tilde.h b/external/gpl3/gdb/dist/readline/tilde.h new file mode 100644 index 000000000000..c58ce20e7a25 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/tilde.h @@ -0,0 +1,81 @@ +/* tilde.h: Externally available variables and function in libtilde.a. */ + +/* Copyright (C) 1992 Free Software Foundation, Inc. + + This file contains the Readline Library (the Library), a set of + routines for providing Emacs style line input to programs that ask + for it. + + The Library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + The Library is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_TILDE_H_) +# define _TILDE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* A function can be defined using prototypes and compile on both ANSI C + and traditional C compilers with something like this: + extern char *func PARAMS((char *, char *, int)); */ + +#if !defined (PARAMS) +# if defined (__STDC__) || defined (__GNUC__) || defined (__cplusplus) +# define PARAMS(protos) protos +# else +# define PARAMS(protos) () +# endif +#endif + +typedef char *tilde_hook_func_t PARAMS((char *)); + +/* If non-null, this contains the address of a function that the application + wants called before trying the standard tilde expansions. The function + is called with the text sans tilde, and returns a malloc()'ed string + which is the expansion, or a NULL pointer if the expansion fails. */ +extern tilde_hook_func_t *tilde_expansion_preexpansion_hook; + +/* If non-null, this contains the address of a function to call if the + standard meaning for expanding a tilde fails. The function is called + with the text (sans tilde, as in "foo"), and returns a malloc()'ed string + which is the expansion, or a NULL pointer if there is no expansion. */ +extern tilde_hook_func_t *tilde_expansion_failure_hook; + +/* When non-null, this is a NULL terminated array of strings which + are duplicates for a tilde prefix. Bash uses this to expand + `=~' and `:~'. */ +extern char **tilde_additional_prefixes; + +/* When non-null, this is a NULL terminated array of strings which match + the end of a username, instead of just "/". Bash sets this to + `:' and `=~'. */ +extern char **tilde_additional_suffixes; + +/* Return a new string which is the result of tilde expanding STRING. */ +extern char *tilde_expand PARAMS((const char *)); + +/* Do the work of tilde expansion on FILENAME. FILENAME starts with a + tilde. If there is no expansion, call tilde_expansion_failure_hook. */ +extern char *tilde_expand_word PARAMS((const char *)); + +/* Find the portion of the string beginning with ~ that should be expanded. */ +extern char *tilde_find_word PARAMS((const char *, int, int *)); + +#ifdef __cplusplus +} +#endif + +#endif /* _TILDE_H_ */ diff --git a/external/gpl3/gdb/dist/readline/undo.c b/external/gpl3/gdb/dist/readline/undo.c new file mode 100644 index 000000000000..fedfa121fc0d --- /dev/null +++ b/external/gpl3/gdb/dist/readline/undo.c @@ -0,0 +1,268 @@ +/* readline.c -- a general facility for reading lines of input + with emacs style editing and completion. */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" + +/* Some standard library routines. */ +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* Non-zero tells rl_delete_text and rl_insert_text to not add to + the undo list. */ +int _rl_doing_an_undo = 0; + +/* How many unclosed undo groups we currently have. */ +int _rl_undo_group_level = 0; + +/* The current undo list for THE_LINE. */ +UNDO_LIST *rl_undo_list = (UNDO_LIST *)NULL; + +/* **************************************************************** */ +/* */ +/* Undo, and Undoing */ +/* */ +/* **************************************************************** */ + +/* Remember how to undo something. Concatenate some undos if that + seems right. */ +void +rl_add_undo (what, start, end, text) + enum undo_code what; + int start, end; + char *text; +{ + UNDO_LIST *temp = (UNDO_LIST *)xmalloc (sizeof (UNDO_LIST)); + temp->what = what; + temp->start = start; + temp->end = end; + temp->text = text; + temp->next = rl_undo_list; + rl_undo_list = temp; +} + +/* Free the existing undo list. */ +void +rl_free_undo_list () +{ + while (rl_undo_list) + { + UNDO_LIST *release = rl_undo_list; + rl_undo_list = rl_undo_list->next; + + if (release->what == UNDO_DELETE) + free (release->text); + + free (release); + } + rl_undo_list = (UNDO_LIST *)NULL; +} + +/* Undo the next thing in the list. Return 0 if there + is nothing to undo, or non-zero if there was. */ +int +rl_do_undo () +{ + UNDO_LIST *release; + int waiting_for_begin, start, end; + +#define TRANS(i) ((i) == -1 ? rl_point : ((i) == -2 ? rl_end : (i))) + + start = end = waiting_for_begin = 0; + do + { + if (!rl_undo_list) + return (0); + + _rl_doing_an_undo = 1; + RL_SETSTATE(RL_STATE_UNDOING); + + /* To better support vi-mode, a start or end value of -1 means + rl_point, and a value of -2 means rl_end. */ + if (rl_undo_list->what == UNDO_DELETE || rl_undo_list->what == UNDO_INSERT) + { + start = TRANS (rl_undo_list->start); + end = TRANS (rl_undo_list->end); + } + + switch (rl_undo_list->what) + { + /* Undoing deletes means inserting some text. */ + case UNDO_DELETE: + rl_point = start; + rl_insert_text (rl_undo_list->text); + free (rl_undo_list->text); + break; + + /* Undoing inserts means deleting some text. */ + case UNDO_INSERT: + rl_delete_text (start, end); + rl_point = start; + break; + + /* Undoing an END means undoing everything 'til we get to a BEGIN. */ + case UNDO_END: + waiting_for_begin++; + break; + + /* Undoing a BEGIN means that we are done with this group. */ + case UNDO_BEGIN: + if (waiting_for_begin) + waiting_for_begin--; + else + rl_ding (); + break; + } + + _rl_doing_an_undo = 0; + RL_UNSETSTATE(RL_STATE_UNDOING); + + release = rl_undo_list; + rl_undo_list = rl_undo_list->next; + free (release); + } + while (waiting_for_begin); + + return (1); +} +#undef TRANS + +int +_rl_fix_last_undo_of_type (type, start, end) + int type, start, end; +{ + UNDO_LIST *rl; + + for (rl = rl_undo_list; rl; rl = rl->next) + { + if (rl->what == type) + { + rl->start = start; + rl->end = end; + return 0; + } + } + return 1; +} + +/* Begin a group. Subsequent undos are undone as an atomic operation. */ +int +rl_begin_undo_group () +{ + rl_add_undo (UNDO_BEGIN, 0, 0, 0); + _rl_undo_group_level++; + return 0; +} + +/* End an undo group started with rl_begin_undo_group (). */ +int +rl_end_undo_group () +{ + rl_add_undo (UNDO_END, 0, 0, 0); + _rl_undo_group_level--; + return 0; +} + +/* Save an undo entry for the text from START to END. */ +int +rl_modifying (start, end) + int start, end; +{ + if (start > end) + { + SWAP (start, end); + } + + if (start != end) + { + char *temp = rl_copy_text (start, end); + rl_begin_undo_group (); + rl_add_undo (UNDO_DELETE, start, end, temp); + rl_add_undo (UNDO_INSERT, start, end, (char *)NULL); + rl_end_undo_group (); + } + return 0; +} + +/* Revert the current line to its previous state. */ +int +rl_revert_line (count, key) + int count, key; +{ + if (!rl_undo_list) + rl_ding (); + else + { + while (rl_undo_list) + rl_do_undo (); +#if defined (VI_MODE) + if (rl_editing_mode == vi_mode) + rl_point = rl_mark = 0; /* rl_end should be set correctly */ +#endif + } + + return 0; +} + +/* Do some undoing of things that were done. */ +int +rl_undo_command (count, key) + int count, key; +{ + if (count < 0) + return 0; /* Nothing to do. */ + + while (count) + { + if (rl_do_undo ()) + count--; + else + { + rl_ding (); + break; + } + } + return 0; +} diff --git a/external/gpl3/gdb/dist/readline/util.c b/external/gpl3/gdb/dist/readline/util.c new file mode 100644 index 000000000000..e44ef64349d4 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/util.c @@ -0,0 +1,355 @@ +/* util.c -- readline utility functions */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include +#include +#include "posixjmp.h" + +#if defined (HAVE_UNISTD_H) +# include /* for _POSIX_VERSION */ +#endif /* HAVE_UNISTD_H */ + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include +#include + +/* System-specific feature definitions and include files. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#if defined (TIOCSTAT_IN_SYS_IOCTL) +# include +#endif /* TIOCSTAT_IN_SYS_IOCTL */ + +/* Some standard library routines. */ +#include "readline.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +/* **************************************************************** */ +/* */ +/* Utility Functions */ +/* */ +/* **************************************************************** */ + +/* Return 0 if C is not a member of the class of characters that belong + in words, or 1 if it is. */ + +int _rl_allow_pathname_alphabetic_chars = 0; +static const char *pathname_alphabetic_chars = "/-_=~.#$"; + +int +rl_alphabetic (c) + int c; +{ + if (ALPHABETIC (c)) + return (1); + + return (_rl_allow_pathname_alphabetic_chars && + strchr (pathname_alphabetic_chars, c) != NULL); +} + +#if defined (HANDLE_MULTIBYTE) +int +_rl_walphabetic (wc) + wchar_t wc; +{ + int c; + + if (iswalnum (wc)) + return (1); + + c = wc & 0177; + return (_rl_allow_pathname_alphabetic_chars && + strchr (pathname_alphabetic_chars, c) != NULL); +} +#endif + +/* How to abort things. */ +int +_rl_abort_internal () +{ + rl_ding (); + rl_clear_message (); + _rl_reset_argument (); + rl_clear_pending_input (); + + RL_UNSETSTATE (RL_STATE_MACRODEF); + while (rl_executing_macro) + _rl_pop_executing_macro (); + + rl_last_func = (rl_command_func_t *)NULL; + longjmp (readline_top_level, 1); + return (0); +} + +int +rl_abort (count, key) + int count, key; +{ + return (_rl_abort_internal ()); +} + +int +rl_tty_status (count, key) + int count, key; +{ +#if defined (TIOCSTAT) + ioctl (1, TIOCSTAT, (char *)0); + rl_refresh_line (count, key); +#else + rl_ding (); +#endif + return 0; +} + +/* Return a copy of the string between FROM and TO. + FROM is inclusive, TO is not. */ +char * +rl_copy_text (from, to) + int from, to; +{ + register int length; + char *copy; + + /* Fix it if the caller is confused. */ + if (from > to) + SWAP (from, to); + + length = to - from; + copy = (char *)xmalloc (1 + length); + strncpy (copy, rl_line_buffer + from, length); + copy[length] = '\0'; + return (copy); +} + +/* Increase the size of RL_LINE_BUFFER until it has enough space to hold + LEN characters. */ +void +rl_extend_line_buffer (len) + int len; +{ + while (len >= rl_line_buffer_len) + { + rl_line_buffer_len += DEFAULT_BUFFER_SIZE; + rl_line_buffer = (char *)xrealloc (rl_line_buffer, rl_line_buffer_len); + } + + _rl_set_the_line (); +} + + +/* A function for simple tilde expansion. */ +int +rl_tilde_expand (ignore, key) + int ignore, key; +{ + register int start, end; + char *homedir, *temp; + int len; + + end = rl_point; + start = end - 1; + + if (rl_point == rl_end && rl_line_buffer[rl_point] == '~') + { + homedir = tilde_expand ("~"); + _rl_replace_text (homedir, start, end); + return (0); + } + else if (rl_line_buffer[start] != '~') + { + for (; !whitespace (rl_line_buffer[start]) && start >= 0; start--) + ; + start++; + } + + end = start; + do + end++; + while (whitespace (rl_line_buffer[end]) == 0 && end < rl_end); + + if (whitespace (rl_line_buffer[end]) || end >= rl_end) + end--; + + /* If the first character of the current word is a tilde, perform + tilde expansion and insert the result. If not a tilde, do + nothing. */ + if (rl_line_buffer[start] == '~') + { + len = end - start + 1; + temp = (char *)xmalloc (len + 1); + strncpy (temp, rl_line_buffer + start, len); + temp[len] = '\0'; + homedir = tilde_expand (temp); + free (temp); + + _rl_replace_text (homedir, start, end); + } + + return (0); +} + +/* **************************************************************** */ +/* */ +/* String Utility Functions */ +/* */ +/* **************************************************************** */ + +/* Determine if s2 occurs in s1. If so, return a pointer to the + match in s1. The compare is case insensitive. */ +char * +_rl_strindex (s1, s2) + register const char *s1, *s2; +{ + register int i, l, len; + + for (i = 0, l = strlen (s2), len = strlen (s1); (len - i) >= l; i++) + if (_rl_strnicmp (s1 + i, s2, l) == 0) + return ((char *) (s1 + i)); + return ((char *)NULL); +} + +#ifndef HAVE_STRPBRK +/* Find the first occurrence in STRING1 of any character from STRING2. + Return a pointer to the character in STRING1. */ +char * +_rl_strpbrk (string1, string2) + const char *string1, *string2; +{ + register const char *scan; +#if defined (HANDLE_MULTIBYTE) + mbstate_t ps; + register int i, v; + + memset (&ps, 0, sizeof (mbstate_t)); +#endif + + for (; *string1; string1++) + { + for (scan = string2; *scan; scan++) + { + if (*string1 == *scan) + return ((char *)string1); + } +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + v = _rl_get_char_len (string1, &ps); + if (v > 1) + string1 += v - 1; /* -1 to account for auto-increment in loop */ + } +#endif + } + return ((char *)NULL); +} +#endif + +#if !defined (HAVE_STRCASECMP) +/* Compare at most COUNT characters from string1 to string2. Case + doesn't matter. */ +int +_rl_strnicmp (string1, string2, count) + char *string1, *string2; + int count; +{ + register char ch1, ch2; + + while (count) + { + ch1 = *string1++; + ch2 = *string2++; + if (_rl_to_upper(ch1) == _rl_to_upper(ch2)) + count--; + else + break; + } + return (count); +} + +/* strcmp (), but caseless. */ +int +_rl_stricmp (string1, string2) + char *string1, *string2; +{ + register char ch1, ch2; + + while (*string1 && *string2) + { + ch1 = *string1++; + ch2 = *string2++; + if (_rl_to_upper(ch1) != _rl_to_upper(ch2)) + return (1); + } + return (*string1 - *string2); +} +#endif /* !HAVE_STRCASECMP */ + +/* Stupid comparison routine for qsort () ing strings. */ +int +_rl_qsort_string_compare (s1, s2) + char **s1, **s2; +{ +#if defined (HAVE_STRCOLL) + return (strcoll (*s1, *s2)); +#else + int result; + + result = **s1 - **s2; + if (result == 0) + result = strcmp (*s1, *s2); + + return result; +#endif +} + +/* Function equivalents for the macros defined in chardefs.h. */ +#define FUNCTION_FOR_MACRO(f) int (f) (c) int c; { return f (c); } + +FUNCTION_FOR_MACRO (_rl_digit_p) +FUNCTION_FOR_MACRO (_rl_digit_value) +FUNCTION_FOR_MACRO (_rl_lowercase_p) +FUNCTION_FOR_MACRO (_rl_pure_alphabetic) +FUNCTION_FOR_MACRO (_rl_to_lower) +FUNCTION_FOR_MACRO (_rl_to_upper) +FUNCTION_FOR_MACRO (_rl_uppercase_p) + +/* Backwards compatibility, now that savestring has been removed from + all `public' readline header files. */ +#undef _rl_savestring +char * +_rl_savestring (s) + const char *s; +{ + return (strcpy ((char *)xmalloc (1 + (int)strlen (s)), (s))); +} diff --git a/external/gpl3/gdb/dist/readline/vi_keymap.c b/external/gpl3/gdb/dist/readline/vi_keymap.c new file mode 100644 index 000000000000..4b48c75cc5db --- /dev/null +++ b/external/gpl3/gdb/dist/readline/vi_keymap.c @@ -0,0 +1,877 @@ +/* vi_keymap.c -- the keymap for vi_mode in readline (). */ + +/* Copyright (C) 1987, 1989, 1992 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (BUFSIZ) +#include +#endif /* !BUFSIZ */ + +#include "readline.h" + +#if 0 +extern KEYMAP_ENTRY_ARRAY vi_escape_keymap; +#endif + +/* The keymap arrays for handling vi mode. */ +KEYMAP_ENTRY_ARRAY vi_movement_keymap = { + /* The regular control keys come first. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-@ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-c */ + { ISFUNC, rl_vi_eof_maybe }, /* Control-d */ + { ISFUNC, rl_emacs_editing_mode }, /* Control-e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-f */ + { ISFUNC, rl_abort }, /* Control-g */ + { ISFUNC, rl_backward_char }, /* Control-h */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-i */ + { ISFUNC, rl_newline }, /* Control-j */ + { ISFUNC, rl_kill_line }, /* Control-k */ + { ISFUNC, rl_clear_screen }, /* Control-l */ + { ISFUNC, rl_newline }, /* Control-m */ + { ISFUNC, rl_get_next_history }, /* Control-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-o */ + { ISFUNC, rl_get_previous_history }, /* Control-p */ + { ISFUNC, rl_quoted_insert }, /* Control-q */ + { ISFUNC, rl_reverse_search_history }, /* Control-r */ + { ISFUNC, rl_forward_search_history }, /* Control-s */ + { ISFUNC, rl_transpose_chars }, /* Control-t */ + { ISFUNC, rl_unix_line_discard }, /* Control-u */ + { ISFUNC, rl_quoted_insert }, /* Control-v */ + { ISFUNC, rl_unix_word_rubout }, /* Control-w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-x */ + { ISFUNC, rl_yank }, /* Control-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-z */ + + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-[ */ /* vi_escape_keymap */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-\ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-^ */ + { ISFUNC, rl_vi_undo }, /* Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, rl_forward_char }, /* SPACE */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ! */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* " */ + { ISFUNC, rl_insert_comment }, /* # */ + { ISFUNC, rl_end_of_line }, /* $ */ + { ISFUNC, rl_vi_match }, /* % */ + { ISFUNC, rl_vi_tilde_expand }, /* & */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ' */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ( */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ) */ + { ISFUNC, rl_vi_complete }, /* * */ + { ISFUNC, rl_get_next_history}, /* + */ + { ISFUNC, rl_vi_char_search }, /* , */ + { ISFUNC, rl_get_previous_history }, /* - */ + { ISFUNC, rl_vi_redo }, /* . */ + { ISFUNC, rl_vi_search }, /* / */ + + /* Regular digits. */ + { ISFUNC, rl_beg_of_line }, /* 0 */ + { ISFUNC, rl_vi_arg_digit }, /* 1 */ + { ISFUNC, rl_vi_arg_digit }, /* 2 */ + { ISFUNC, rl_vi_arg_digit }, /* 3 */ + { ISFUNC, rl_vi_arg_digit }, /* 4 */ + { ISFUNC, rl_vi_arg_digit }, /* 5 */ + { ISFUNC, rl_vi_arg_digit }, /* 6 */ + { ISFUNC, rl_vi_arg_digit }, /* 7 */ + { ISFUNC, rl_vi_arg_digit }, /* 8 */ + { ISFUNC, rl_vi_arg_digit }, /* 9 */ + + /* A little more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* : */ + { ISFUNC, rl_vi_char_search }, /* ; */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* < */ + { ISFUNC, rl_vi_complete }, /* = */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* > */ + { ISFUNC, rl_vi_search }, /* ? */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* @ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_vi_append_eol }, /* A */ + { ISFUNC, rl_vi_prev_word}, /* B */ + { ISFUNC, rl_vi_change_to }, /* C */ + { ISFUNC, rl_vi_delete_to }, /* D */ + { ISFUNC, rl_vi_end_word }, /* E */ + { ISFUNC, rl_vi_char_search }, /* F */ + { ISFUNC, rl_vi_fetch_history }, /* G */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* H */ + { ISFUNC, rl_vi_insert_beg }, /* I */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* J */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* K */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* L */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* M */ + { ISFUNC, rl_vi_search_again }, /* N */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* O */ + { ISFUNC, rl_vi_put }, /* P */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Q */ + { ISFUNC, rl_vi_replace }, /* R */ + { ISFUNC, rl_vi_subst }, /* S */ + { ISFUNC, rl_vi_char_search }, /* T */ + { ISFUNC, rl_revert_line }, /* U */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* V */ + { ISFUNC, rl_vi_next_word }, /* W */ + { ISFUNC, rl_vi_rubout }, /* X */ + { ISFUNC, rl_vi_yank_to }, /* Y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Z */ + + /* Some more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* [ */ + { ISFUNC, rl_vi_complete }, /* \ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ] */ + { ISFUNC, rl_vi_first_print }, /* ^ */ + { ISFUNC, rl_vi_yank_arg }, /* _ */ + { ISFUNC, rl_vi_goto_mark }, /* ` */ + + /* Lowercase alphabet. */ + { ISFUNC, rl_vi_append_mode }, /* a */ + { ISFUNC, rl_vi_prev_word }, /* b */ + { ISFUNC, rl_vi_change_to }, /* c */ + { ISFUNC, rl_vi_delete_to }, /* d */ + { ISFUNC, rl_vi_end_word }, /* e */ + { ISFUNC, rl_vi_char_search }, /* f */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* g */ + { ISFUNC, rl_backward_char }, /* h */ + { ISFUNC, rl_vi_insertion_mode }, /* i */ + { ISFUNC, rl_get_next_history }, /* j */ + { ISFUNC, rl_get_previous_history }, /* k */ + { ISFUNC, rl_forward_char }, /* l */ + { ISFUNC, rl_vi_set_mark }, /* m */ + { ISFUNC, rl_vi_search_again }, /* n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* o */ + { ISFUNC, rl_vi_put }, /* p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* q */ + { ISFUNC, rl_vi_change_char }, /* r */ + { ISFUNC, rl_vi_subst }, /* s */ + { ISFUNC, rl_vi_char_search }, /* t */ + { ISFUNC, rl_vi_undo }, /* u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* v */ + { ISFUNC, rl_vi_next_word }, /* w */ + { ISFUNC, rl_vi_delete }, /* x */ + { ISFUNC, rl_vi_yank_to }, /* y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* z */ + + /* Final punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* { */ + { ISFUNC, rl_vi_column }, /* | */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* } */ + { ISFUNC, rl_vi_change_case }, /* ~ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* RUBOUT */ + +#if KEYMAP_SIZE > 128 + /* Undefined keys. */ + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 } +#endif /* KEYMAP_SIZE > 128 */ +}; + + +KEYMAP_ENTRY_ARRAY vi_insertion_keymap = { + /* The regular control keys come first. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-@ */ + { ISFUNC, rl_insert }, /* Control-a */ + { ISFUNC, rl_insert }, /* Control-b */ + { ISFUNC, rl_insert }, /* Control-c */ + { ISFUNC, rl_vi_eof_maybe }, /* Control-d */ + { ISFUNC, rl_insert }, /* Control-e */ + { ISFUNC, rl_insert }, /* Control-f */ + { ISFUNC, rl_insert }, /* Control-g */ + { ISFUNC, rl_rubout }, /* Control-h */ + { ISFUNC, rl_complete }, /* Control-i */ + { ISFUNC, rl_newline }, /* Control-j */ + { ISFUNC, rl_insert }, /* Control-k */ + { ISFUNC, rl_insert }, /* Control-l */ + { ISFUNC, rl_newline }, /* Control-m */ + { ISFUNC, rl_insert }, /* Control-n */ + { ISFUNC, rl_insert }, /* Control-o */ + { ISFUNC, rl_insert }, /* Control-p */ + { ISFUNC, rl_insert }, /* Control-q */ + { ISFUNC, rl_reverse_search_history }, /* Control-r */ + { ISFUNC, rl_forward_search_history }, /* Control-s */ + { ISFUNC, rl_transpose_chars }, /* Control-t */ + { ISFUNC, rl_unix_line_discard }, /* Control-u */ + { ISFUNC, rl_quoted_insert }, /* Control-v */ + { ISFUNC, rl_unix_word_rubout }, /* Control-w */ + { ISFUNC, rl_insert }, /* Control-x */ + { ISFUNC, rl_yank }, /* Control-y */ + { ISFUNC, rl_insert }, /* Control-z */ + + { ISFUNC, rl_vi_movement_mode }, /* Control-[ */ + { ISFUNC, rl_insert }, /* Control-\ */ + { ISFUNC, rl_insert }, /* Control-] */ + { ISFUNC, rl_insert }, /* Control-^ */ + { ISFUNC, rl_vi_undo }, /* Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, rl_insert }, /* SPACE */ + { ISFUNC, rl_insert }, /* ! */ + { ISFUNC, rl_insert }, /* " */ + { ISFUNC, rl_insert }, /* # */ + { ISFUNC, rl_insert }, /* $ */ + { ISFUNC, rl_insert }, /* % */ + { ISFUNC, rl_insert }, /* & */ + { ISFUNC, rl_insert }, /* ' */ + { ISFUNC, rl_insert }, /* ( */ + { ISFUNC, rl_insert }, /* ) */ + { ISFUNC, rl_insert }, /* * */ + { ISFUNC, rl_insert }, /* + */ + { ISFUNC, rl_insert }, /* , */ + { ISFUNC, rl_insert }, /* - */ + { ISFUNC, rl_insert }, /* . */ + { ISFUNC, rl_insert }, /* / */ + + /* Regular digits. */ + { ISFUNC, rl_insert }, /* 0 */ + { ISFUNC, rl_insert }, /* 1 */ + { ISFUNC, rl_insert }, /* 2 */ + { ISFUNC, rl_insert }, /* 3 */ + { ISFUNC, rl_insert }, /* 4 */ + { ISFUNC, rl_insert }, /* 5 */ + { ISFUNC, rl_insert }, /* 6 */ + { ISFUNC, rl_insert }, /* 7 */ + { ISFUNC, rl_insert }, /* 8 */ + { ISFUNC, rl_insert }, /* 9 */ + + /* A little more punctuation. */ + { ISFUNC, rl_insert }, /* : */ + { ISFUNC, rl_insert }, /* ; */ + { ISFUNC, rl_insert }, /* < */ + { ISFUNC, rl_insert }, /* = */ + { ISFUNC, rl_insert }, /* > */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* @ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_insert }, /* A */ + { ISFUNC, rl_insert }, /* B */ + { ISFUNC, rl_insert }, /* C */ + { ISFUNC, rl_insert }, /* D */ + { ISFUNC, rl_insert }, /* E */ + { ISFUNC, rl_insert }, /* F */ + { ISFUNC, rl_insert }, /* G */ + { ISFUNC, rl_insert }, /* H */ + { ISFUNC, rl_insert }, /* I */ + { ISFUNC, rl_insert }, /* J */ + { ISFUNC, rl_insert }, /* K */ + { ISFUNC, rl_insert }, /* L */ + { ISFUNC, rl_insert }, /* M */ + { ISFUNC, rl_insert }, /* N */ + { ISFUNC, rl_insert }, /* O */ + { ISFUNC, rl_insert }, /* P */ + { ISFUNC, rl_insert }, /* Q */ + { ISFUNC, rl_insert }, /* R */ + { ISFUNC, rl_insert }, /* S */ + { ISFUNC, rl_insert }, /* T */ + { ISFUNC, rl_insert }, /* U */ + { ISFUNC, rl_insert }, /* V */ + { ISFUNC, rl_insert }, /* W */ + { ISFUNC, rl_insert }, /* X */ + { ISFUNC, rl_insert }, /* Y */ + { ISFUNC, rl_insert }, /* Z */ + + /* Some more punctuation. */ + { ISFUNC, rl_insert }, /* [ */ + { ISFUNC, rl_insert }, /* \ */ + { ISFUNC, rl_insert }, /* ] */ + { ISFUNC, rl_insert }, /* ^ */ + { ISFUNC, rl_insert }, /* _ */ + { ISFUNC, rl_insert }, /* ` */ + + /* Lowercase alphabet. */ + { ISFUNC, rl_insert }, /* a */ + { ISFUNC, rl_insert }, /* b */ + { ISFUNC, rl_insert }, /* c */ + { ISFUNC, rl_insert }, /* d */ + { ISFUNC, rl_insert }, /* e */ + { ISFUNC, rl_insert }, /* f */ + { ISFUNC, rl_insert }, /* g */ + { ISFUNC, rl_insert }, /* h */ + { ISFUNC, rl_insert }, /* i */ + { ISFUNC, rl_insert }, /* j */ + { ISFUNC, rl_insert }, /* k */ + { ISFUNC, rl_insert }, /* l */ + { ISFUNC, rl_insert }, /* m */ + { ISFUNC, rl_insert }, /* n */ + { ISFUNC, rl_insert }, /* o */ + { ISFUNC, rl_insert }, /* p */ + { ISFUNC, rl_insert }, /* q */ + { ISFUNC, rl_insert }, /* r */ + { ISFUNC, rl_insert }, /* s */ + { ISFUNC, rl_insert }, /* t */ + { ISFUNC, rl_insert }, /* u */ + { ISFUNC, rl_insert }, /* v */ + { ISFUNC, rl_insert }, /* w */ + { ISFUNC, rl_insert }, /* x */ + { ISFUNC, rl_insert }, /* y */ + { ISFUNC, rl_insert }, /* z */ + + /* Final punctuation. */ + { ISFUNC, rl_insert }, /* { */ + { ISFUNC, rl_insert }, /* | */ + { ISFUNC, rl_insert }, /* } */ + { ISFUNC, rl_insert }, /* ~ */ + { ISFUNC, rl_rubout }, /* RUBOUT */ + +#if KEYMAP_SIZE > 128 + /* Pure 8-bit characters (128 - 159). + These might be used in some + character sets. */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + { ISFUNC, rl_insert }, /* ? */ + + /* ISO Latin-1 characters (160 - 255) */ + { ISFUNC, rl_insert }, /* No-break space */ + { ISFUNC, rl_insert }, /* Inverted exclamation mark */ + { ISFUNC, rl_insert }, /* Cent sign */ + { ISFUNC, rl_insert }, /* Pound sign */ + { ISFUNC, rl_insert }, /* Currency sign */ + { ISFUNC, rl_insert }, /* Yen sign */ + { ISFUNC, rl_insert }, /* Broken bar */ + { ISFUNC, rl_insert }, /* Section sign */ + { ISFUNC, rl_insert }, /* Diaeresis */ + { ISFUNC, rl_insert }, /* Copyright sign */ + { ISFUNC, rl_insert }, /* Feminine ordinal indicator */ + { ISFUNC, rl_insert }, /* Left pointing double angle quotation mark */ + { ISFUNC, rl_insert }, /* Not sign */ + { ISFUNC, rl_insert }, /* Soft hyphen */ + { ISFUNC, rl_insert }, /* Registered sign */ + { ISFUNC, rl_insert }, /* Macron */ + { ISFUNC, rl_insert }, /* Degree sign */ + { ISFUNC, rl_insert }, /* Plus-minus sign */ + { ISFUNC, rl_insert }, /* Superscript two */ + { ISFUNC, rl_insert }, /* Superscript three */ + { ISFUNC, rl_insert }, /* Acute accent */ + { ISFUNC, rl_insert }, /* Micro sign */ + { ISFUNC, rl_insert }, /* Pilcrow sign */ + { ISFUNC, rl_insert }, /* Middle dot */ + { ISFUNC, rl_insert }, /* Cedilla */ + { ISFUNC, rl_insert }, /* Superscript one */ + { ISFUNC, rl_insert }, /* Masculine ordinal indicator */ + { ISFUNC, rl_insert }, /* Right pointing double angle quotation mark */ + { ISFUNC, rl_insert }, /* Vulgar fraction one quarter */ + { ISFUNC, rl_insert }, /* Vulgar fraction one half */ + { ISFUNC, rl_insert }, /* Vulgar fraction three quarters */ + { ISFUNC, rl_insert }, /* Inverted questionk mark */ + { ISFUNC, rl_insert }, /* Latin capital letter a with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter a with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter a with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter a with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter a with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter a with ring above */ + { ISFUNC, rl_insert }, /* Latin capital letter ae */ + { ISFUNC, rl_insert }, /* Latin capital letter c with cedilla */ + { ISFUNC, rl_insert }, /* Latin capital letter e with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter e with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter e with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter e with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter i with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter i with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter i with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter i with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter eth (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin capital letter n with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter o with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter o with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter o with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter o with tilde */ + { ISFUNC, rl_insert }, /* Latin capital letter o with diaeresis */ + { ISFUNC, rl_insert }, /* Multiplication sign */ + { ISFUNC, rl_insert }, /* Latin capital letter o with stroke */ + { ISFUNC, rl_insert }, /* Latin capital letter u with grave */ + { ISFUNC, rl_insert }, /* Latin capital letter u with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter u with circumflex */ + { ISFUNC, rl_insert }, /* Latin capital letter u with diaeresis */ + { ISFUNC, rl_insert }, /* Latin capital letter Y with acute */ + { ISFUNC, rl_insert }, /* Latin capital letter thorn (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin small letter sharp s (German) */ + { ISFUNC, rl_insert }, /* Latin small letter a with grave */ + { ISFUNC, rl_insert }, /* Latin small letter a with acute */ + { ISFUNC, rl_insert }, /* Latin small letter a with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter a with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter a with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter a with ring above */ + { ISFUNC, rl_insert }, /* Latin small letter ae */ + { ISFUNC, rl_insert }, /* Latin small letter c with cedilla */ + { ISFUNC, rl_insert }, /* Latin small letter e with grave */ + { ISFUNC, rl_insert }, /* Latin small letter e with acute */ + { ISFUNC, rl_insert }, /* Latin small letter e with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter e with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter i with grave */ + { ISFUNC, rl_insert }, /* Latin small letter i with acute */ + { ISFUNC, rl_insert }, /* Latin small letter i with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter i with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter eth (Icelandic) */ + { ISFUNC, rl_insert }, /* Latin small letter n with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter o with grave */ + { ISFUNC, rl_insert }, /* Latin small letter o with acute */ + { ISFUNC, rl_insert }, /* Latin small letter o with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter o with tilde */ + { ISFUNC, rl_insert }, /* Latin small letter o with diaeresis */ + { ISFUNC, rl_insert }, /* Division sign */ + { ISFUNC, rl_insert }, /* Latin small letter o with stroke */ + { ISFUNC, rl_insert }, /* Latin small letter u with grave */ + { ISFUNC, rl_insert }, /* Latin small letter u with acute */ + { ISFUNC, rl_insert }, /* Latin small letter u with circumflex */ + { ISFUNC, rl_insert }, /* Latin small letter u with diaeresis */ + { ISFUNC, rl_insert }, /* Latin small letter y with acute */ + { ISFUNC, rl_insert }, /* Latin small letter thorn (Icelandic) */ + { ISFUNC, rl_insert } /* Latin small letter y with diaeresis */ +#endif /* KEYMAP_SIZE > 128 */ +}; + +/* Unused for the time being. */ +#if 0 +KEYMAP_ENTRY_ARRAY vi_escape_keymap = { + /* The regular control keys come first. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-@ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-c */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-d */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-f */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-g */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-h */ + { ISFUNC, rl_tab_insert}, /* Control-i */ + { ISFUNC, rl_emacs_editing_mode}, /* Control-j */ + { ISFUNC, rl_kill_line }, /* Control-k */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-l */ + { ISFUNC, rl_emacs_editing_mode}, /* Control-m */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-n */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-o */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-q */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-s */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-t */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-x */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-z */ + + { ISFUNC, rl_vi_movement_mode }, /* Control-[ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-\ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* Control-^ */ + { ISFUNC, rl_vi_undo }, /* Control-_ */ + + /* The start of printing characters. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* SPACE */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ! */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* " */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* # */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* $ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* % */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* & */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ' */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ( */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ) */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* * */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* + */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* , */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* - */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* . */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* / */ + + /* Regular digits. */ + { ISFUNC, rl_vi_arg_digit }, /* 0 */ + { ISFUNC, rl_vi_arg_digit }, /* 1 */ + { ISFUNC, rl_vi_arg_digit }, /* 2 */ + { ISFUNC, rl_vi_arg_digit }, /* 3 */ + { ISFUNC, rl_vi_arg_digit }, /* 4 */ + { ISFUNC, rl_vi_arg_digit }, /* 5 */ + { ISFUNC, rl_vi_arg_digit }, /* 6 */ + { ISFUNC, rl_vi_arg_digit }, /* 7 */ + { ISFUNC, rl_vi_arg_digit }, /* 8 */ + { ISFUNC, rl_vi_arg_digit }, /* 9 */ + + /* A little more punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* : */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ; */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* < */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* = */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* > */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ? */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* @ */ + + /* Uppercase alphabet. */ + { ISFUNC, rl_do_lowercase_version }, /* A */ + { ISFUNC, rl_do_lowercase_version }, /* B */ + { ISFUNC, rl_do_lowercase_version }, /* C */ + { ISFUNC, rl_do_lowercase_version }, /* D */ + { ISFUNC, rl_do_lowercase_version }, /* E */ + { ISFUNC, rl_do_lowercase_version }, /* F */ + { ISFUNC, rl_do_lowercase_version }, /* G */ + { ISFUNC, rl_do_lowercase_version }, /* H */ + { ISFUNC, rl_do_lowercase_version }, /* I */ + { ISFUNC, rl_do_lowercase_version }, /* J */ + { ISFUNC, rl_do_lowercase_version }, /* K */ + { ISFUNC, rl_do_lowercase_version }, /* L */ + { ISFUNC, rl_do_lowercase_version }, /* M */ + { ISFUNC, rl_do_lowercase_version }, /* N */ + { ISFUNC, rl_do_lowercase_version }, /* O */ + { ISFUNC, rl_do_lowercase_version }, /* P */ + { ISFUNC, rl_do_lowercase_version }, /* Q */ + { ISFUNC, rl_do_lowercase_version }, /* R */ + { ISFUNC, rl_do_lowercase_version }, /* S */ + { ISFUNC, rl_do_lowercase_version }, /* T */ + { ISFUNC, rl_do_lowercase_version }, /* U */ + { ISFUNC, rl_do_lowercase_version }, /* V */ + { ISFUNC, rl_do_lowercase_version }, /* W */ + { ISFUNC, rl_do_lowercase_version }, /* X */ + { ISFUNC, rl_do_lowercase_version }, /* Y */ + { ISFUNC, rl_do_lowercase_version }, /* Z */ + + /* Some more punctuation. */ + { ISFUNC, rl_arrow_keys }, /* [ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* \ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ] */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ^ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* _ */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ` */ + + /* Lowercase alphabet. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* a */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* b */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* c */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* d */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* e */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* f */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* g */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* h */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* i */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* j */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* k */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* l */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* m */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* n */ + { ISFUNC, rl_arrow_keys }, /* o */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* p */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* q */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* r */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* s */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* t */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* u */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* v */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* w */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* x */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* y */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* z */ + + /* Final punctuation. */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* { */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* | */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* } */ + { ISFUNC, (rl_command_func_t *)0x0 }, /* ~ */ + { ISFUNC, rl_backward_kill_word }, /* RUBOUT */ + +#if KEYMAP_SIZE > 128 + /* Undefined keys. */ + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 }, + { ISFUNC, (rl_command_func_t *)0x0 } +#endif /* KEYMAP_SIZE > 128 */ +}; +#endif diff --git a/external/gpl3/gdb/dist/readline/vi_mode.c b/external/gpl3/gdb/dist/readline/vi_mode.c new file mode 100644 index 000000000000..ac5fd7446dcf --- /dev/null +++ b/external/gpl3/gdb/dist/readline/vi_mode.c @@ -0,0 +1,1717 @@ +/* vi_mode.c -- A vi emulation mode for Bash. + Derived from code written by Jeff Sparkes (jsparkes@bnr.ca). */ + +/* Copyright (C) 1987-2005 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +/* **************************************************************** */ +/* */ +/* VI Emulation Mode */ +/* */ +/* **************************************************************** */ +#include "rlconf.h" + +#if defined (VI_MODE) + +#if defined (HAVE_CONFIG_H) +# include +#endif + +#include + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#if defined (HAVE_UNISTD_H) +# include +#endif + +#include + +/* Some standard library routines. */ +#include "rldefs.h" +#include "rlmbutil.h" + +#include "readline.h" +#include "history.h" + +#include "rlprivate.h" +#include "xmalloc.h" + +#ifndef member +#define member(c, s) ((c) ? (char *)strchr ((s), (c)) != (char *)NULL : 0) +#endif + +int _rl_vi_last_command = 'i'; /* default `.' puts you in insert mode */ + +/* Non-zero means enter insertion mode. */ +static int _rl_vi_doing_insert; + +/* Command keys which do movement for xxx_to commands. */ +static const char *vi_motion = " hl^$0ftFT;,%wbeWBE|"; + +/* Keymap used for vi replace characters. Created dynamically since + rarely used. */ +static Keymap vi_replace_map; + +/* The number of characters inserted in the last replace operation. */ +static int vi_replace_count; + +/* If non-zero, we have text inserted after a c[motion] command that put + us implicitly into insert mode. Some people want this text to be + attached to the command so that it is `redoable' with `.'. */ +static int vi_continued_command; +static char *vi_insert_buffer; +static int vi_insert_buffer_size; + +static int _rl_vi_last_repeat = 1; +static int _rl_vi_last_arg_sign = 1; +static int _rl_vi_last_motion; +#if defined (HANDLE_MULTIBYTE) +static char _rl_vi_last_search_mbchar[MB_LEN_MAX]; +static int _rl_vi_last_search_mblen; +#else +static int _rl_vi_last_search_char; +#endif +static int _rl_vi_last_replacement; + +static int _rl_vi_last_key_before_insert; + +static int vi_redoing; + +/* Text modification commands. These are the `redoable' commands. */ +static const char *vi_textmod = "_*\\AaIiCcDdPpYyRrSsXx~"; + +/* Arrays for the saved marks. */ +static int vi_mark_chars['z' - 'a' + 1]; + +static void _rl_vi_stuff_insert PARAMS((int)); +static void _rl_vi_save_insert PARAMS((UNDO_LIST *)); + +static int _rl_vi_arg_dispatch PARAMS((int)); +static int rl_digit_loop1 PARAMS((void)); + +static int _rl_vi_set_mark PARAMS((void)); +static int _rl_vi_goto_mark PARAMS((void)); + +static int _rl_vi_callback_getchar PARAMS((char *, int)); + +#if defined (READLINE_CALLBACKS) +static int _rl_vi_callback_set_mark PARAMS((_rl_callback_generic_arg *)); +static int _rl_vi_callback_goto_mark PARAMS((_rl_callback_generic_arg *)); +static int _rl_vi_callback_change_char PARAMS((_rl_callback_generic_arg *)); +static int _rl_vi_callback_char_search PARAMS((_rl_callback_generic_arg *)); +#endif + +void +_rl_vi_initialize_line () +{ + register int i; + + for (i = 0; i < sizeof (vi_mark_chars) / sizeof (int); i++) + vi_mark_chars[i] = -1; + + RL_UNSETSTATE(RL_STATE_VICMDONCE); +} + +void +_rl_vi_reset_last () +{ + _rl_vi_last_command = 'i'; + _rl_vi_last_repeat = 1; + _rl_vi_last_arg_sign = 1; + _rl_vi_last_motion = 0; +} + +void +_rl_vi_set_last (key, repeat, sign) + int key, repeat, sign; +{ + _rl_vi_last_command = key; + _rl_vi_last_repeat = repeat; + _rl_vi_last_arg_sign = sign; +} + +/* A convenience function that calls _rl_vi_set_last to save the last command + information and enters insertion mode. */ +void +rl_vi_start_inserting (key, repeat, sign) + int key, repeat, sign; +{ + _rl_vi_set_last (key, repeat, sign); + rl_vi_insertion_mode (1, key); +} + +/* Is the command C a VI mode text modification command? */ +int +_rl_vi_textmod_command (c) + int c; +{ + return (member (c, vi_textmod)); +} + +static void +_rl_vi_stuff_insert (count) + int count; +{ + rl_begin_undo_group (); + while (count--) + rl_insert_text (vi_insert_buffer); + rl_end_undo_group (); +} + +/* Bound to `.'. Called from command mode, so we know that we have to + redo a text modification command. The default for _rl_vi_last_command + puts you back into insert mode. */ +int +rl_vi_redo (count, c) + int count, c; +{ + int r; + + if (!rl_explicit_arg) + { + rl_numeric_arg = _rl_vi_last_repeat; + rl_arg_sign = _rl_vi_last_arg_sign; + } + + r = 0; + vi_redoing = 1; + /* If we're redoing an insert with `i', stuff in the inserted text + and do not go into insertion mode. */ + if (_rl_vi_last_command == 'i' && vi_insert_buffer && *vi_insert_buffer) + { + _rl_vi_stuff_insert (count); + /* And back up point over the last character inserted. */ + if (rl_point > 0) + rl_point--; + } + else + r = _rl_dispatch (_rl_vi_last_command, _rl_keymap); + vi_redoing = 0; + + return (r); +} + +/* A placeholder for further expansion. */ +int +rl_vi_undo (count, key) + int count, key; +{ + return (rl_undo_command (count, key)); +} + +/* Yank the nth arg from the previous line into this line at point. */ +int +rl_vi_yank_arg (count, key) + int count, key; +{ + /* Readline thinks that the first word on a line is the 0th, while vi + thinks the first word on a line is the 1st. Compensate. */ + if (rl_explicit_arg) + rl_yank_nth_arg (count - 1, 0); + else + rl_yank_nth_arg ('$', 0); + + return (0); +} + +/* With an argument, move back that many history lines, else move to the + beginning of history. */ +int +rl_vi_fetch_history (count, c) + int count, c; +{ + int wanted; + + /* Giving an argument of n means we want the nth command in the history + file. The command number is interpreted the same way that the bash + `history' command does it -- that is, giving an argument count of 450 + to this command would get the command listed as number 450 in the + output of `history'. */ + if (rl_explicit_arg) + { + wanted = history_base + where_history () - count; + if (wanted <= 0) + rl_beginning_of_history (0, 0); + else + rl_get_previous_history (wanted, c); + } + else + rl_beginning_of_history (count, 0); + return (0); +} + +/* Search again for the last thing searched for. */ +int +rl_vi_search_again (count, key) + int count, key; +{ + switch (key) + { + case 'n': + rl_noninc_reverse_search_again (count, key); + break; + + case 'N': + rl_noninc_forward_search_again (count, key); + break; + } + return (0); +} + +/* Do a vi style search. */ +int +rl_vi_search (count, key) + int count, key; +{ + switch (key) + { + case '?': + _rl_free_saved_history_line (); + rl_noninc_forward_search (count, key); + break; + + case '/': + _rl_free_saved_history_line (); + rl_noninc_reverse_search (count, key); + break; + + default: + rl_ding (); + break; + } + return (0); +} + +/* Completion, from vi's point of view. */ +int +rl_vi_complete (ignore, key) + int ignore, key; +{ + if ((rl_point < rl_end) && (!whitespace (rl_line_buffer[rl_point]))) + { + if (!whitespace (rl_line_buffer[rl_point + 1])) + rl_vi_end_word (1, 'E'); + rl_point++; + } + + if (key == '*') + rl_complete_internal ('*'); /* Expansion and replacement. */ + else if (key == '=') + rl_complete_internal ('?'); /* List possible completions. */ + else if (key == '\\') + rl_complete_internal (TAB); /* Standard Readline completion. */ + else + rl_complete (0, key); + + if (key == '*' || key == '\\') + rl_vi_start_inserting (key, 1, rl_arg_sign); + + return (0); +} + +/* Tilde expansion for vi mode. */ +int +rl_vi_tilde_expand (ignore, key) + int ignore, key; +{ + rl_tilde_expand (0, key); + rl_vi_start_inserting (key, 1, rl_arg_sign); + return (0); +} + +/* Previous word in vi mode. */ +int +rl_vi_prev_word (count, key) + int count, key; +{ + if (count < 0) + return (rl_vi_next_word (-count, key)); + + if (rl_point == 0) + { + rl_ding (); + return (0); + } + + if (_rl_uppercase_p (key)) + rl_vi_bWord (count, key); + else + rl_vi_bword (count, key); + + return (0); +} + +/* Next word in vi mode. */ +int +rl_vi_next_word (count, key) + int count, key; +{ + if (count < 0) + return (rl_vi_prev_word (-count, key)); + + if (rl_point >= (rl_end - 1)) + { + rl_ding (); + return (0); + } + + if (_rl_uppercase_p (key)) + rl_vi_fWord (count, key); + else + rl_vi_fword (count, key); + return (0); +} + +/* Move to the end of the ?next? word. */ +int +rl_vi_end_word (count, key) + int count, key; +{ + if (count < 0) + { + rl_ding (); + return -1; + } + + if (_rl_uppercase_p (key)) + rl_vi_eWord (count, key); + else + rl_vi_eword (count, key); + return (0); +} + +/* Move forward a word the way that 'W' does. */ +int +rl_vi_fWord (count, ignore) + int count, ignore; +{ + while (count-- && rl_point < (rl_end - 1)) + { + /* Skip until whitespace. */ + while (!whitespace (rl_line_buffer[rl_point]) && rl_point < rl_end) + rl_point++; + + /* Now skip whitespace. */ + while (whitespace (rl_line_buffer[rl_point]) && rl_point < rl_end) + rl_point++; + } + return (0); +} + +int +rl_vi_bWord (count, ignore) + int count, ignore; +{ + while (count-- && rl_point > 0) + { + /* If we are at the start of a word, move back to whitespace so + we will go back to the start of the previous word. */ + if (!whitespace (rl_line_buffer[rl_point]) && + whitespace (rl_line_buffer[rl_point - 1])) + rl_point--; + + while (rl_point > 0 && whitespace (rl_line_buffer[rl_point])) + rl_point--; + + if (rl_point > 0) + { + while (--rl_point >= 0 && !whitespace (rl_line_buffer[rl_point])); + rl_point++; + } + } + return (0); +} + +int +rl_vi_eWord (count, ignore) + int count, ignore; +{ + while (count-- && rl_point < (rl_end - 1)) + { + if (!whitespace (rl_line_buffer[rl_point])) + rl_point++; + + /* Move to the next non-whitespace character (to the start of the + next word). */ + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + + if (rl_point && rl_point < rl_end) + { + /* Skip whitespace. */ + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + + /* Skip until whitespace. */ + while (rl_point < rl_end && !whitespace (rl_line_buffer[rl_point])) + rl_point++; + + /* Move back to the last character of the word. */ + rl_point--; + } + } + return (0); +} + +int +rl_vi_fword (count, ignore) + int count, ignore; +{ + while (count-- && rl_point < (rl_end - 1)) + { + /* Move to white space (really non-identifer). */ + if (_rl_isident (rl_line_buffer[rl_point])) + { + while (_rl_isident (rl_line_buffer[rl_point]) && rl_point < rl_end) + rl_point++; + } + else /* if (!whitespace (rl_line_buffer[rl_point])) */ + { + while (!_rl_isident (rl_line_buffer[rl_point]) && + !whitespace (rl_line_buffer[rl_point]) && rl_point < rl_end) + rl_point++; + } + + /* Move past whitespace. */ + while (whitespace (rl_line_buffer[rl_point]) && rl_point < rl_end) + rl_point++; + } + return (0); +} + +int +rl_vi_bword (count, ignore) + int count, ignore; +{ + while (count-- && rl_point > 0) + { + int last_is_ident; + + /* If we are at the start of a word, move back to whitespace + so we will go back to the start of the previous word. */ + if (!whitespace (rl_line_buffer[rl_point]) && + whitespace (rl_line_buffer[rl_point - 1])) + rl_point--; + + /* If this character and the previous character are `opposite', move + back so we don't get messed up by the rl_point++ down there in + the while loop. Without this code, words like `l;' screw up the + function. */ + last_is_ident = _rl_isident (rl_line_buffer[rl_point - 1]); + if ((_rl_isident (rl_line_buffer[rl_point]) && !last_is_ident) || + (!_rl_isident (rl_line_buffer[rl_point]) && last_is_ident)) + rl_point--; + + while (rl_point > 0 && whitespace (rl_line_buffer[rl_point])) + rl_point--; + + if (rl_point > 0) + { + if (_rl_isident (rl_line_buffer[rl_point])) + while (--rl_point >= 0 && _rl_isident (rl_line_buffer[rl_point])); + else + while (--rl_point >= 0 && !_rl_isident (rl_line_buffer[rl_point]) && + !whitespace (rl_line_buffer[rl_point])); + rl_point++; + } + } + return (0); +} + +int +rl_vi_eword (count, ignore) + int count, ignore; +{ + while (count-- && rl_point < rl_end - 1) + { + if (!whitespace (rl_line_buffer[rl_point])) + rl_point++; + + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + + if (rl_point < rl_end) + { + if (_rl_isident (rl_line_buffer[rl_point])) + while (++rl_point < rl_end && _rl_isident (rl_line_buffer[rl_point])); + else + while (++rl_point < rl_end && !_rl_isident (rl_line_buffer[rl_point]) + && !whitespace (rl_line_buffer[rl_point])); + } + rl_point--; + } + return (0); +} + +int +rl_vi_insert_beg (count, key) + int count, key; +{ + rl_beg_of_line (1, key); + rl_vi_insertion_mode (1, key); + return (0); +} + +int +rl_vi_append_mode (count, key) + int count, key; +{ + if (rl_point < rl_end) + { + if (MB_CUR_MAX == 1 || rl_byte_oriented) + rl_point++; + else + { + int point = rl_point; + rl_forward_char (1, key); + if (point == rl_point) + rl_point = rl_end; + } + } + rl_vi_insertion_mode (1, key); + return (0); +} + +int +rl_vi_append_eol (count, key) + int count, key; +{ + rl_end_of_line (1, key); + rl_vi_append_mode (1, key); + return (0); +} + +/* What to do in the case of C-d. */ +int +rl_vi_eof_maybe (count, c) + int count, c; +{ + return (rl_newline (1, '\n')); +} + +/* Insertion mode stuff. */ + +/* Switching from one mode to the other really just involves + switching keymaps. */ +int +rl_vi_insertion_mode (count, key) + int count, key; +{ + _rl_keymap = vi_insertion_keymap; + _rl_vi_last_key_before_insert = key; + return (0); +} + +static void +_rl_vi_save_insert (up) + UNDO_LIST *up; +{ + int len, start, end; + + if (up == 0) + { + if (vi_insert_buffer_size >= 1) + vi_insert_buffer[0] = '\0'; + return; + } + + start = up->start; + end = up->end; + len = end - start + 1; + if (len >= vi_insert_buffer_size) + { + vi_insert_buffer_size += (len + 32) - (len % 32); + vi_insert_buffer = (char *)xrealloc (vi_insert_buffer, vi_insert_buffer_size); + } + strncpy (vi_insert_buffer, rl_line_buffer + start, len - 1); + vi_insert_buffer[len-1] = '\0'; +} + +void +_rl_vi_done_inserting () +{ + if (_rl_vi_doing_insert) + { + /* The `C', `s', and `S' commands set this. */ + rl_end_undo_group (); + /* Now, the text between rl_undo_list->next->start and + rl_undo_list->next->end is what was inserted while in insert + mode. It gets copied to VI_INSERT_BUFFER because it depends + on absolute indices into the line which may change (though they + probably will not). */ + _rl_vi_doing_insert = 0; + _rl_vi_save_insert (rl_undo_list->next); + vi_continued_command = 1; + } + else + { + if ((_rl_vi_last_key_before_insert == 'i' || _rl_vi_last_key_before_insert == 'a') && rl_undo_list) + _rl_vi_save_insert (rl_undo_list); + /* XXX - Other keys probably need to be checked. */ + else if (_rl_vi_last_key_before_insert == 'C') + rl_end_undo_group (); + while (_rl_undo_group_level > 0) + rl_end_undo_group (); + vi_continued_command = 0; + } +} + +int +rl_vi_movement_mode (count, key) + int count, key; +{ + if (rl_point > 0) + rl_backward_char (1, key); + + _rl_keymap = vi_movement_keymap; + _rl_vi_done_inserting (); + + /* This is how POSIX.2 says `U' should behave -- everything up until the + first time you go into command mode should not be undone. */ + if (RL_ISSTATE (RL_STATE_VICMDONCE) == 0) + rl_free_undo_list (); + + RL_SETSTATE (RL_STATE_VICMDONCE); + return (0); +} + +int +rl_vi_arg_digit (count, c) + int count, c; +{ + if (c == '0' && rl_numeric_arg == 1 && !rl_explicit_arg) + return (rl_beg_of_line (1, c)); + else + return (rl_digit_argument (count, c)); +} + +/* Change the case of the next COUNT characters. */ +#if defined (HANDLE_MULTIBYTE) +static int +_rl_vi_change_mbchar_case (count) + int count; +{ + wchar_t wc; + char mb[MB_LEN_MAX+1]; + int mblen, p; + mbstate_t ps; + + memset (&ps, 0, sizeof (mbstate_t)); + if (_rl_adjust_point (rl_line_buffer, rl_point, &ps) > 0) + count--; + while (count-- && rl_point < rl_end) + { + mbrtowc (&wc, rl_line_buffer + rl_point, rl_end - rl_point, &ps); + if (iswupper (wc)) + wc = towlower (wc); + else if (iswlower (wc)) + wc = towupper (wc); + else + { + /* Just skip over chars neither upper nor lower case */ + rl_forward_char (1, 0); + continue; + } + + /* Vi is kind of strange here. */ + if (wc) + { + p = rl_point; + mblen = wcrtomb (mb, wc, &ps); + if (mblen >= 0) + mb[mblen] = '\0'; + rl_begin_undo_group (); + rl_vi_delete (1, 0); + if (rl_point < p) /* Did we retreat at EOL? */ + rl_point++; /* XXX - should we advance more than 1 for mbchar? */ + rl_insert_text (mb); + rl_end_undo_group (); + rl_vi_check (); + } + else + rl_forward_char (1, 0); + } + + return 0; +} +#endif + +int +rl_vi_change_case (count, ignore) + int count, ignore; +{ + int c, p; + + /* Don't try this on an empty line. */ + if (rl_point >= rl_end) + return (0); + + c = 0; +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + return (_rl_vi_change_mbchar_case (count)); +#endif + + while (count-- && rl_point < rl_end) + { + if (_rl_uppercase_p (rl_line_buffer[rl_point])) + c = _rl_to_lower (rl_line_buffer[rl_point]); + else if (_rl_lowercase_p (rl_line_buffer[rl_point])) + c = _rl_to_upper (rl_line_buffer[rl_point]); + else + { + /* Just skip over characters neither upper nor lower case. */ + rl_forward_char (1, c); + continue; + } + + /* Vi is kind of strange here. */ + if (c) + { + p = rl_point; + rl_begin_undo_group (); + rl_vi_delete (1, c); + if (rl_point < p) /* Did we retreat at EOL? */ + rl_point++; + _rl_insert_char (1, c); + rl_end_undo_group (); + rl_vi_check (); + } + else + rl_forward_char (1, c); + } + return (0); +} + +int +rl_vi_put (count, key) + int count, key; +{ + if (!_rl_uppercase_p (key) && (rl_point + 1 <= rl_end)) + rl_point = _rl_find_next_mbchar (rl_line_buffer, rl_point, 1, MB_FIND_NONZERO); + + while (count--) + rl_yank (1, key); + + rl_backward_char (1, key); + return (0); +} + +int +rl_vi_check () +{ + if (rl_point && rl_point == rl_end) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + else + rl_point--; + } + return (0); +} + +int +rl_vi_column (count, key) + int count, key; +{ + if (count > rl_end) + rl_end_of_line (1, key); + else + rl_point = count - 1; + return (0); +} + +int +rl_vi_domove (key, nextkey) + int key, *nextkey; +{ + int c, save; + int old_end; + + rl_mark = rl_point; + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + *nextkey = c; + + if (!member (c, vi_motion)) + { + if (_rl_digit_p (c)) + { + save = rl_numeric_arg; + rl_numeric_arg = _rl_digit_value (c); + rl_explicit_arg = 1; + RL_SETSTATE (RL_STATE_NUMERICARG|RL_STATE_VIMOTION); + rl_digit_loop1 (); + RL_UNSETSTATE (RL_STATE_VIMOTION); + rl_numeric_arg *= save; + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); /* real command */ + RL_UNSETSTATE(RL_STATE_MOREINPUT); + *nextkey = c; + } + else if (key == c && (key == 'd' || key == 'y' || key == 'c')) + { + rl_mark = rl_end; + rl_beg_of_line (1, c); + _rl_vi_last_motion = c; + return (0); + } + else + return (-1); + } + + _rl_vi_last_motion = c; + + /* Append a blank character temporarily so that the motion routines + work right at the end of the line. */ + old_end = rl_end; + rl_line_buffer[rl_end++] = ' '; + rl_line_buffer[rl_end] = '\0'; + + _rl_dispatch (c, _rl_keymap); + + /* Remove the blank that we added. */ + rl_end = old_end; + rl_line_buffer[rl_end] = '\0'; + if (rl_point > rl_end) + rl_point = rl_end; + + /* No change in position means the command failed. */ + if (rl_mark == rl_point) + return (-1); + + /* rl_vi_f[wW]ord () leaves the cursor on the first character of the next + word. If we are not at the end of the line, and we are on a + non-whitespace character, move back one (presumably to whitespace). */ + if ((_rl_to_upper (c) == 'W') && rl_point < rl_end && rl_point > rl_mark && + !whitespace (rl_line_buffer[rl_point])) + rl_point--; + + /* If cw or cW, back up to the end of a word, so the behaviour of ce + or cE is the actual result. Brute-force, no subtlety. */ + if (key == 'c' && rl_point >= rl_mark && (_rl_to_upper (c) == 'W')) + { + /* Don't move farther back than where we started. */ + while (rl_point > rl_mark && whitespace (rl_line_buffer[rl_point])) + rl_point--; + + /* Posix.2 says that if cw or cW moves the cursor towards the end of + the line, the character under the cursor should be deleted. */ + if (rl_point == rl_mark) + rl_point++; + else + { + /* Move past the end of the word so that the kill doesn't + remove the last letter of the previous word. Only do this + if we are not at the end of the line. */ + if (rl_point >= 0 && rl_point < (rl_end - 1) && !whitespace (rl_line_buffer[rl_point])) + rl_point++; + } + } + + if (rl_mark < rl_point) + SWAP (rl_point, rl_mark); + + return (0); +} + +/* Process C as part of the current numeric argument. Return -1 if the + argument should be aborted, 0 if we should not read any more chars, and + 1 if we should continue to read chars. */ +static int +_rl_vi_arg_dispatch (c) + int c; +{ + int key; + + key = c; + if (c >= 0 && _rl_keymap[c].type == ISFUNC && _rl_keymap[c].function == rl_universal_argument) + { + rl_numeric_arg *= 4; + return 1; + } + + c = UNMETA (c); + + if (_rl_digit_p (c)) + { + if (rl_explicit_arg) + rl_numeric_arg = (rl_numeric_arg * 10) + _rl_digit_value (c); + else + rl_numeric_arg = _rl_digit_value (c); + rl_explicit_arg = 1; + return 1; + } + else + { + rl_clear_message (); + rl_stuff_char (key); + return 0; + } +} + +/* A simplified loop for vi. Don't dispatch key at end. + Don't recognize minus sign? + Should this do rl_save_prompt/rl_restore_prompt? */ +static int +rl_digit_loop1 () +{ + int c, r; + + while (1) + { + if (_rl_arg_overflow ()) + return 1; + + c = _rl_arg_getchar (); + + r = _rl_vi_arg_dispatch (c); + if (r <= 0) + break; + } + + RL_UNSETSTATE(RL_STATE_NUMERICARG); + return (0); +} + +int +rl_vi_delete_to (count, key) + int count, key; +{ + int c; + + if (_rl_uppercase_p (key)) + rl_stuff_char ('$'); + else if (vi_redoing) + rl_stuff_char (_rl_vi_last_motion); + + if (rl_vi_domove (key, &c)) + { + rl_ding (); + return -1; + } + + /* These are the motion commands that do not require adjusting the + mark. */ + if ((strchr (" l|h^0bB", c) == 0) && (rl_mark < rl_end)) + rl_mark++; + + rl_kill_text (rl_point, rl_mark); + return (0); +} + +int +rl_vi_change_to (count, key) + int count, key; +{ + int c, start_pos; + + if (_rl_uppercase_p (key)) + rl_stuff_char ('$'); + else if (vi_redoing) + rl_stuff_char (_rl_vi_last_motion); + + start_pos = rl_point; + + if (rl_vi_domove (key, &c)) + { + rl_ding (); + return -1; + } + + /* These are the motion commands that do not require adjusting the + mark. c[wW] are handled by special-case code in rl_vi_domove(), + and already leave the mark at the correct location. */ + if ((strchr (" l|hwW^0bB", c) == 0) && (rl_mark < rl_end)) + rl_mark++; + + /* The cursor never moves with c[wW]. */ + if ((_rl_to_upper (c) == 'W') && rl_point < start_pos) + rl_point = start_pos; + + if (vi_redoing) + { + if (vi_insert_buffer && *vi_insert_buffer) + rl_begin_undo_group (); + rl_delete_text (rl_point, rl_mark); + if (vi_insert_buffer && *vi_insert_buffer) + { + rl_insert_text (vi_insert_buffer); + rl_end_undo_group (); + } + } + else + { + rl_begin_undo_group (); /* to make the `u' command work */ + rl_kill_text (rl_point, rl_mark); + /* `C' does not save the text inserted for undoing or redoing. */ + if (_rl_uppercase_p (key) == 0) + _rl_vi_doing_insert = 1; + rl_vi_start_inserting (key, rl_numeric_arg, rl_arg_sign); + } + + return (0); +} + +int +rl_vi_yank_to (count, key) + int count, key; +{ + int c, save; + + save = rl_point; + if (_rl_uppercase_p (key)) + rl_stuff_char ('$'); + + if (rl_vi_domove (key, &c)) + { + rl_ding (); + return -1; + } + + /* These are the motion commands that do not require adjusting the + mark. */ + if ((strchr (" l|h^0%bB", c) == 0) && (rl_mark < rl_end)) + rl_mark++; + + rl_begin_undo_group (); + rl_kill_text (rl_point, rl_mark); + rl_end_undo_group (); + rl_do_undo (); + rl_point = save; + + return (0); +} + +int +rl_vi_rubout (count, key) + int count, key; +{ + int p, opoint; + + if (count < 0) + return (rl_vi_delete (-count, key)); + + if (rl_point == 0) + { + rl_ding (); + return -1; + } + + opoint = rl_point; + if (count > 1 && MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_backward_char (count, key); + else if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_point = _rl_find_prev_mbchar (rl_line_buffer, rl_point, MB_FIND_NONZERO); + else + rl_point -= count; + + if (rl_point < 0) + rl_point = 0; + + rl_kill_text (rl_point, opoint); + + return (0); +} + +int +rl_vi_delete (count, key) + int count, key; +{ + int end; + + if (count < 0) + return (rl_vi_rubout (-count, key)); + + if (rl_end == 0) + { + rl_ding (); + return -1; + } + + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + end = _rl_find_next_mbchar (rl_line_buffer, rl_point, count, MB_FIND_NONZERO); + else + end = rl_point + count; + + if (end >= rl_end) + end = rl_end; + + rl_kill_text (rl_point, end); + + if (rl_point > 0 && rl_point == rl_end) + rl_backward_char (1, key); + + return (0); +} + +int +rl_vi_back_to_indent (count, key) + int count, key; +{ + rl_beg_of_line (1, key); + while (rl_point < rl_end && whitespace (rl_line_buffer[rl_point])) + rl_point++; + return (0); +} + +int +rl_vi_first_print (count, key) + int count, key; +{ + return (rl_vi_back_to_indent (1, key)); +} + +static int _rl_cs_dir, _rl_cs_orig_dir; + +#if defined (READLINE_CALLBACKS) +static int +_rl_vi_callback_char_search (data) + _rl_callback_generic_arg *data; +{ +#if defined (HANDLE_MULTIBYTE) + _rl_vi_last_search_mblen = _rl_read_mbchar (_rl_vi_last_search_mbchar, MB_LEN_MAX); +#else + RL_SETSTATE(RL_STATE_MOREINPUT); + _rl_vi_last_search_char = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); +#endif + + _rl_callback_func = 0; + _rl_want_redisplay = 1; + +#if defined (HANDLE_MULTIBYTE) + return (_rl_char_search_internal (data->count, _rl_cs_dir, _rl_vi_last_search_mbchar, _rl_vi_last_search_mblen)); +#else + return (_rl_char_search_internal (data->count, _rl_cs_dir, _rl_vi_last_search_char)); +#endif +} +#endif + +int +rl_vi_char_search (count, key) + int count, key; +{ +#if defined (HANDLE_MULTIBYTE) + static char *target; + static int tlen; +#else + static char target; +#endif + + if (key == ';' || key == ',') + _rl_cs_dir = (key == ';') ? _rl_cs_orig_dir : -_rl_cs_orig_dir; + else + { + switch (key) + { + case 't': + _rl_cs_orig_dir = _rl_cs_dir = FTO; + break; + + case 'T': + _rl_cs_orig_dir = _rl_cs_dir = BTO; + break; + + case 'f': + _rl_cs_orig_dir = _rl_cs_dir = FFIND; + break; + + case 'F': + _rl_cs_orig_dir = _rl_cs_dir = BFIND; + break; + } + + if (vi_redoing) + { + /* set target and tlen below */ + } +#if defined (READLINE_CALLBACKS) + else if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = _rl_callback_data_alloc (count); + _rl_callback_data->i1 = _rl_cs_dir; + _rl_callback_func = _rl_vi_callback_char_search; + return (0); + } +#endif + else + { +#if defined (HANDLE_MULTIBYTE) + _rl_vi_last_search_mblen = _rl_read_mbchar (_rl_vi_last_search_mbchar, MB_LEN_MAX); +#else + RL_SETSTATE(RL_STATE_MOREINPUT); + _rl_vi_last_search_char = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); +#endif + } + } + +#if defined (HANDLE_MULTIBYTE) + target = _rl_vi_last_search_mbchar; + tlen = _rl_vi_last_search_mblen; +#else + target = _rl_vi_last_search_char; +#endif + +#if defined (HANDLE_MULTIBYTE) + return (_rl_char_search_internal (count, _rl_cs_dir, target, tlen)); +#else + return (_rl_char_search_internal (count, _rl_cs_dir, target)); +#endif +} + +/* Match brackets */ +int +rl_vi_match (ignore, key) + int ignore, key; +{ + int count = 1, brack, pos, tmp, pre; + + pos = rl_point; + if ((brack = rl_vi_bracktype (rl_line_buffer[rl_point])) == 0) + { + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + { + while ((brack = rl_vi_bracktype (rl_line_buffer[rl_point])) == 0) + { + pre = rl_point; + rl_forward_char (1, key); + if (pre == rl_point) + break; + } + } + else + while ((brack = rl_vi_bracktype (rl_line_buffer[rl_point])) == 0 && + rl_point < rl_end - 1) + rl_forward_char (1, key); + + if (brack <= 0) + { + rl_point = pos; + rl_ding (); + return -1; + } + } + + pos = rl_point; + + if (brack < 0) + { + while (count) + { + tmp = pos; + if (MB_CUR_MAX == 1 || rl_byte_oriented) + pos--; + else + { + pos = _rl_find_prev_mbchar (rl_line_buffer, pos, MB_FIND_ANY); + if (tmp == pos) + pos--; + } + if (pos >= 0) + { + int b = rl_vi_bracktype (rl_line_buffer[pos]); + if (b == -brack) + count--; + else if (b == brack) + count++; + } + else + { + rl_ding (); + return -1; + } + } + } + else + { /* brack > 0 */ + while (count) + { + if (MB_CUR_MAX == 1 || rl_byte_oriented) + pos++; + else + pos = _rl_find_next_mbchar (rl_line_buffer, pos, 1, MB_FIND_ANY); + + if (pos < rl_end) + { + int b = rl_vi_bracktype (rl_line_buffer[pos]); + if (b == -brack) + count--; + else if (b == brack) + count++; + } + else + { + rl_ding (); + return -1; + } + } + } + rl_point = pos; + return (0); +} + +int +rl_vi_bracktype (c) + int c; +{ + switch (c) + { + case '(': return 1; + case ')': return -1; + case '[': return 2; + case ']': return -2; + case '{': return 3; + case '}': return -3; + default: return 0; + } +} + +static int +_rl_vi_change_char (count, c, mb) + int count, c; + char *mb; +{ + int p; + + if (c == '\033' || c == CTRL ('C')) + return -1; + + rl_begin_undo_group (); + while (count-- && rl_point < rl_end) + { + p = rl_point; + rl_vi_delete (1, c); + if (rl_point < p) /* Did we retreat at EOL? */ + rl_point++; +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + rl_insert_text (mb); + else +#endif + _rl_insert_char (1, c); + } + + /* The cursor shall be left on the last character changed. */ + rl_backward_char (1, c); + + rl_end_undo_group (); + + return (0); +} + +static int +_rl_vi_callback_getchar (mb, mblen) + char *mb; + int mblen; +{ + int c; + + RL_SETSTATE(RL_STATE_MOREINPUT); + c = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + +#if defined (HANDLE_MULTIBYTE) + if (MB_CUR_MAX > 1 && rl_byte_oriented == 0) + c = _rl_read_mbstring (c, mb, mblen); +#endif + + return c; +} + +#if defined (READLINE_CALLBACKS) +static int +_rl_vi_callback_change_char (data) + _rl_callback_generic_arg *data; +{ + int c; + char mb[MB_LEN_MAX]; + + _rl_vi_last_replacement = c = _rl_vi_callback_getchar (mb, MB_LEN_MAX); + + _rl_callback_func = 0; + _rl_want_redisplay = 1; + + return (_rl_vi_change_char (data->count, c, mb)); +} +#endif + +int +rl_vi_change_char (count, key) + int count, key; +{ + int c; + char mb[MB_LEN_MAX]; + + if (vi_redoing) + { + c = _rl_vi_last_replacement; + mb[0] = c; + mb[1] = '\0'; + } +#if defined (READLINE_CALLBACKS) + else if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = _rl_callback_data_alloc (count); + _rl_callback_func = _rl_vi_callback_change_char; + return (0); + } +#endif + else + _rl_vi_last_replacement = c = _rl_vi_callback_getchar (mb, MB_LEN_MAX); + + return (_rl_vi_change_char (count, c, mb)); +} + +int +rl_vi_subst (count, key) + int count, key; +{ + /* If we are redoing, rl_vi_change_to will stuff the last motion char */ + if (vi_redoing == 0) + rl_stuff_char ((key == 'S') ? 'c' : 'l'); /* `S' == `cc', `s' == `cl' */ + + return (rl_vi_change_to (count, 'c')); +} + +int +rl_vi_overstrike (count, key) + int count, key; +{ + if (_rl_vi_doing_insert == 0) + { + _rl_vi_doing_insert = 1; + rl_begin_undo_group (); + } + + if (count > 0) + { + _rl_overwrite_char (count, key); + vi_replace_count += count; + } + + return (0); +} + +int +rl_vi_overstrike_delete (count, key) + int count, key; +{ + int i, s; + + for (i = 0; i < count; i++) + { + if (vi_replace_count == 0) + { + rl_ding (); + break; + } + s = rl_point; + + if (rl_do_undo ()) + vi_replace_count--; + + if (rl_point == s) + rl_backward_char (1, key); + } + + if (vi_replace_count == 0 && _rl_vi_doing_insert) + { + rl_end_undo_group (); + rl_do_undo (); + _rl_vi_doing_insert = 0; + } + return (0); +} + +int +rl_vi_replace (count, key) + int count, key; +{ + int i; + + vi_replace_count = 0; + + if (!vi_replace_map) + { + vi_replace_map = rl_make_bare_keymap (); + + for (i = ' '; i < KEYMAP_SIZE; i++) + vi_replace_map[i].function = rl_vi_overstrike; + + vi_replace_map[RUBOUT].function = rl_vi_overstrike_delete; + vi_replace_map[ESC].function = rl_vi_movement_mode; + vi_replace_map[RETURN].function = rl_newline; + vi_replace_map[NEWLINE].function = rl_newline; + + /* If the normal vi insertion keymap has ^H bound to erase, do the + same here. Probably should remove the assignment to RUBOUT up + there, but I don't think it will make a difference in real life. */ + if (vi_insertion_keymap[CTRL ('H')].type == ISFUNC && + vi_insertion_keymap[CTRL ('H')].function == rl_rubout) + vi_replace_map[CTRL ('H')].function = rl_vi_overstrike_delete; + + } + _rl_keymap = vi_replace_map; + return (0); +} + +#if 0 +/* Try to complete the word we are standing on or the word that ends with + the previous character. A space matches everything. Word delimiters are + space and ;. */ +int +rl_vi_possible_completions() +{ + int save_pos = rl_point; + + if (rl_line_buffer[rl_point] != ' ' && rl_line_buffer[rl_point] != ';') + { + while (rl_point < rl_end && rl_line_buffer[rl_point] != ' ' && + rl_line_buffer[rl_point] != ';') + rl_point++; + } + else if (rl_line_buffer[rl_point - 1] == ';') + { + rl_ding (); + return (0); + } + + rl_possible_completions (); + rl_point = save_pos; + + return (0); +} +#endif + +/* Functions to save and restore marks. */ +static int +_rl_vi_set_mark () +{ + int ch; + + RL_SETSTATE(RL_STATE_MOREINPUT); + ch = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (ch < 'a' || ch > 'z') + { + rl_ding (); + return -1; + } + ch -= 'a'; + vi_mark_chars[ch] = rl_point; + return 0; +} + +#if defined (READLINE_CALLBACKS) +static int +_rl_vi_callback_set_mark (data) + _rl_callback_generic_arg *data; +{ + _rl_callback_func = 0; + _rl_want_redisplay = 1; + + return (_rl_vi_set_mark ()); +} +#endif + +int +rl_vi_set_mark (count, key) + int count, key; +{ +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = 0; + _rl_callback_func = _rl_vi_callback_set_mark; + return (0); + } +#endif + + return (_rl_vi_set_mark ()); +} + +static int +_rl_vi_goto_mark () +{ + int ch; + + RL_SETSTATE(RL_STATE_MOREINPUT); + ch = rl_read_key (); + RL_UNSETSTATE(RL_STATE_MOREINPUT); + + if (ch == '`') + { + rl_point = rl_mark; + return 0; + } + else if (ch < 'a' || ch > 'z') + { + rl_ding (); + return -1; + } + + ch -= 'a'; + if (vi_mark_chars[ch] == -1) + { + rl_ding (); + return -1; + } + rl_point = vi_mark_chars[ch]; + return 0; +} + +#if defined (READLINE_CALLBACKS) +static int +_rl_vi_callback_goto_mark (data) + _rl_callback_generic_arg *data; +{ + _rl_callback_func = 0; + _rl_want_redisplay = 1; + + return (_rl_vi_goto_mark ()); +} +#endif + +int +rl_vi_goto_mark (count, key) + int count, key; +{ +#if defined (READLINE_CALLBACKS) + if (RL_ISSTATE (RL_STATE_CALLBACK)) + { + _rl_callback_data = 0; + _rl_callback_func = _rl_vi_callback_goto_mark; + return (0); + } +#endif + + return (_rl_vi_goto_mark ()); +} +#endif /* VI_MODE */ diff --git a/external/gpl3/gdb/dist/readline/xmalloc.c b/external/gpl3/gdb/dist/readline/xmalloc.c new file mode 100644 index 000000000000..2087d3df63b3 --- /dev/null +++ b/external/gpl3/gdb/dist/readline/xmalloc.c @@ -0,0 +1,100 @@ +/* xmalloc.c -- safe versions of malloc and realloc */ + +/* Copyright (C) 1991 Free Software Foundation, Inc. + + This file is part of GNU Readline, a library for reading lines + of text with interactive input and history editing. + + Readline is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + Readline is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Readline; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ +#define READLINE_LIBRARY + +#if defined (HAVE_CONFIG_H) +#include +#endif + +#include + +#if defined (HAVE_STDLIB_H) +# include +#else +# include "ansi_stdlib.h" +#endif /* HAVE_STDLIB_H */ + +#include "xmalloc.h" +#include "readline.h" + +/* **************************************************************** */ +/* */ +/* Memory Allocation and Deallocation. */ +/* */ +/* **************************************************************** */ + +/* xmalloc and xrealloc are provided by GDB. */ +#if 0 + +static void +memory_error_and_abort (fname) + char *fname; +{ + fprintf (stderr, "%s: out of virtual memory\n", fname); + exit (2); +} + +/* Return a pointer to free()able block of memory large enough + to hold BYTES number of bytes. If the memory cannot be allocated, + print an error message and abort. */ +PTR_T +xmalloc (bytes) + size_t bytes; +{ + PTR_T temp; + + temp = malloc (bytes); + if (temp == 0) + memory_error_and_abort ("xmalloc"); + return (temp); +} + +PTR_T +xrealloc (pointer, bytes) + PTR_T pointer; + size_t bytes; +{ + PTR_T temp; + + temp = pointer ? realloc (pointer, bytes) : malloc (bytes); + + if (temp == 0) + memory_error_and_abort ("xrealloc"); + return (temp); +} + +/* xmalloc and xrealloc are provided by GDB. */ +#endif /* 0 */ + +/* Use this as the function to call when adding unwind protects so we + don't need to know what free() returns. */ +void +xfree (string) + PTR_T string; +{ + /* Leak a bit. */ + if (RL_ISSTATE(RL_STATE_SIGHANDLER)) + return; + +#undef free + if (string) + free (string); +} diff --git a/external/gpl3/gdb/dist/readline/xmalloc.h b/external/gpl3/gdb/dist/readline/xmalloc.h new file mode 100644 index 000000000000..1703920874eb --- /dev/null +++ b/external/gpl3/gdb/dist/readline/xmalloc.h @@ -0,0 +1,52 @@ +/* xmalloc.h -- memory allocation that aborts on errors. */ + +/* Copyright (C) 1999 Free Software Foundation, Inc. + + This file is part of the GNU Readline Library, a library for + reading lines of text with interactive input and history editing. + + The GNU Readline Library is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + The GNU Readline Library is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty + of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + The GNU General Public License is often shipped with GNU software, and + is generally kept in a file called COPYING or LICENSE. If you do not + have a copy of the license, write to the Free Software Foundation, + 59 Temple Place, Suite 330, Boston, MA 02111 USA. */ + +#if !defined (_XMALLOC_H_) +#define _XMALLOC_H_ + +#if defined (READLINE_LIBRARY) +# include "rlstdc.h" +#else +# include +#endif + +#ifndef PTR_T + +#ifdef __STDC__ +# define PTR_T void * +#else +# define PTR_T char * +#endif + +#endif /* !PTR_T */ + +/* xmalloc and xrealloc should be also protected from RL_STATE_SIGHANDLER. */ +#define xfree xfree_readline + +/* readline-5.1 backport. */ +#define free xfree + +extern PTR_T xmalloc PARAMS((size_t)); +extern PTR_T xrealloc PARAMS((void *, size_t)); +extern void xfree PARAMS((void *)); + +#endif /* _XMALLOC_H_ */ diff --git a/external/gpl3/gdb/dist/sim/.gitignore b/external/gpl3/gdb/dist/sim/.gitignore new file mode 100644 index 000000000000..9440b897321f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/.gitignore @@ -0,0 +1,8 @@ +/*/gentmap +/*/run +/*/hw-config.h +/*/targ-* +/*/tconfig.h +/*/version.c + +/common/cconfig.h diff --git a/external/gpl3/gdb/dist/sim/ChangeLog b/external/gpl3/gdb/dist/sim/ChangeLog new file mode 100644 index 000000000000..72279928622f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/ChangeLog @@ -0,0 +1,1336 @@ +2011-03-05 Mike Frysinger + + * MAINTAINERS: Add bfin entry. + * configure.tgt (bfin-*-*): Handle bfin targets. + * configure: Regenerate. + +2011-01-05 Mike Frysinger + + * .gitignore: Add /*/hw-config.h. + +2010-12-23 Mike Frysinger + + * .gitignore: New file. + +2010-07-28 DJ Delorie + + * MAINTAINERS: Add self as RX maintainer. Sort list. + +2010-06-08 Nick Clifton + + * reg.c (set_oszc): Use unsigned int for the mask. + (set_szc, set_osz, set_sz): Likewise. + +2010-04-26 Mike Frysinger + + * configure.ac: Target logic moved out to and included from ... + * configure.tgt: ... this new file. + * configure: Regenerated. + +2010-04-12 Mike Frysinger + + * README-HACKING: Add more sections. + +2010-02-11 Doug Evans + + * cris/cpuv10.h, * cris/cpuv32.h, * cris/cris-desc.c, + * cris/cris-desc.h, * cris/decodev10.c, * cris/decodev32.c, + * cris/modelv10.c, * cris/modelv32.c, * cris/semcrisv10f-switch.c, + * cris/semcrisv32f-switch.c: Regenerate. + +2010-01-09 Ralf Wildenhues + + * avr/configure: Regenerate. + * cris/configure: Regenerate. + * microblaze/configure: Regenerate. + +2010-01-02 Doug Evans + + * cris/arch.c, * cris/arch.h, * cris/cpuall.h, * cris/cpuv10.c, + * cris/cpuv10.h, * cris/cpuv32.c, * cris/cpuv32.h, * cris/cris-desc.c, + * cris/cris-desc.h, * cris/cris-opc.h, * cris/decodev10.c, + * cris/decodev10.h, * cris/decodev32.c, * cris/decodev32.h, + * cris/modelv10.c, * cris/modelv32.c, * cris/semcrisv10f-switch.c, + * cris/semcrisv32f-switch.c: Regenerate, update copyright year. + +2010-01-01 Doug Evans + + * cris/mloop.in: Fix copyright year update snafu. + +2009-11-24 Joel Brobecker + + * common/aclocal.m4: Add include of ../../config/zlib.m4. + * common/common.m4: Use AM_ZLIB to check for zlib support. + * ppc/configure.ac: Likewise. + * arm/configure, avr/configure, common/configure, cr16/configure, + cris/configure, d10v/configure, erc32/configure, frv/configure, + h8300/configure, iq2000/configure, lm32/configure, m32c/configure, + m32r/configure, m68hc11/configure, mcore/configure, + microblaze/configure, mips/configure, mn10300/configure, + moxie/configure, ppc/configure, sh/configure, sh64/configure, + v850/configure: Regenerate. + +2009-11-24 DJ Delorie + + * rx: New directory. + * configure.ac: Add entry for Renesas RX. + * configure: Regenerate. + +2009-11-22 Doug Evans + + * cris/cpuall.h: Regenerate. + * cris/cpuv10.h: Regenerate. + * cris/cpuv32.h: Regenerate. + * cris/decodev10.c: Regenerate. + * cris/decodev10.h: Regenerate. + * cris/decodev32.c: Regenerate. + * cris/decodev32.h: Regenerate. + +2009-11-12 Tristan Gingold + + * avr/interp.c (sim_write): Allow byte access. + (sim_read): Ditto. + +2009-11-12 Tristan Gingold + + * avr/interp.c (sim_load): Clear memory before loading. + +2009-11-09 Tristan Gingold + + * avr/interp.c (sim_resume): Fix typo for OP_ret. + +2009-10-23 Doug Evans + + * cris/arch.c: Regenerate. + * cris/arch.h: Regenerate. + * cris/cpuall.h: Regenerate. + * cris/cpuv10.c: Regenerate. + * cris/cpuv10.h: Regenerate. + * cris/cpuv32.c: Regenerate. + * cris/cpuv32.h: Regenerate. + * cris/cris-desc.c: Regenerate. + * cris/cris-desc.h: Regenerate. + * cris/cris-opc.h: Regenerate. + * cris/decodev10.c: Regenerate. + * cris/decodev10.h: Regenerate. + * cris/decodev32.c: Regenerate. + * cris/decodev32.h: Regenerate. + * cris/modelv10.c: Regenerate. + * cris/modelv32.c: Regenerate. + * cris/semcrisv10f-switch.c: Regenerate. + * cris/semcrisv32f-switch.c: Regenerate. + +2009-10-22 Tristan Gingold + + * avr/interp.c (sim_stop): Return 1. + +2009-10-16 Doug Evans + + * MAINTAINERS: Add myself as m32r maintainer. + +2009-10-15 Michael Egaer + + * MAINTAINERS: Add self as MicroBlaze maintainer. + +2009-10-14 Ben Elliston + + * MAINTAINERS (common): Move myself to "past maintainers" section. + +2009-10-06 Michael Eager + + * microblaze/interp.c: Add include microblaze-dis.h. + +2009-09-23 Michael Eager + + * configure: Add microblaze-*.* (not regenerated). + * configure.ac: Likewise. + * microblaze/config.in: New. + * microblaze/configure: Generate. + * microblaze/configure.ac: New. + * microblaze/interp.c: New. + * microblaze/Makefile.in: New. + * microblaze/microblaze.h: New. + * microblaze/microblaze.isa: New. + * microblaze/sim-main.h: New. + * microblaze/sysdep.h: New. + +2009-08-22 Ralf Wildenhues + + * avr/config.in: Regenerate. + * avr/configure: Likewise. + * configure: Likewise. + * cris/config.in: Likewise. + * cris/configure: Likewise. + + * configure.ac: m4_include toplevel config/override.m4. + * configure: Regenerate. + * avr/configure: Regenerate. + * cris/configure: Regenerate. + +2009-07-30 Ralf Wildenhues + + * Makefile.in (datarootdir): New variable. + +2009-05-18 Jon Beniston + + * MAINTAINERS: Add Jon Beniston as maintainer of lm32 sim. + * configure.ac: Add lm32 target. + * lm32: New directory. + +2009-05-11 Andrew Cagney + + * MAINTAINERS: Orphan ppc. + +2009-05-08 Kevin Buettner + + * m32c/gdb-if.c (m32c_signal_to_host): Rename to + m32c_signal_to_target. Change signal return values from SIGILL, + SIGTRAP, SIGSEGV, etc. to TARGET_SIGNAL_ILL, TARGET_SIGNAL_TRAP, + TARGET_SIGNAL_SEGV, etc. Fix all callers. + +2009-04-30 Anthony Green + + * MAINTAINERS: Add myself for the moxie port. + * moxie: New directory. + * configure.ac: Add entry for moxie. + * configure: Regenerate. + +2009-04-27 Tristan Gingold + + * avr: New directory. + * avr/interp.c, avr/Makefile.in, avr/configure.ac: New files. + * avr/config.in: New file, generated by autoheader. + * avr/configure: New file generated by autoconf. + * configure.ac: Add avr. + * configure: Regenerated. + +2009-04-17 Carlos O'Donell + + * Makefile.in: Add dummy install-pdf, html, and + install-html targets. + +2009-01-18 Hans-Peter Nilsson + + * cris/sim-if.c: Include errno.h. + (cris_start_address, cris_program_offset): New variables. + (OPTION_CRIS_PROGRAM_OFFSET, OPTION_CRIS_STARTADDR): New option + enums. + (cris_options): New options --cris-program-offset and + --cris-start-address. + (cris_option_handler): Handle new options. + (cris_program_offset_write, cris_set_section_offset_iterator) + (cris_offset_sections, cris_offset_sections): New functions. + (sim_load): Use cris_program_offset_write as function argument to + cris_load_elf_file, not sim_write. + (struct offsetinfo): New struct. + (cris_handle_interpreter): Fix typo in comment. + (sim_open): Call cris_offset_sections as soon as the bfd of the + infile is available. Gate bfd validity checks on abfd non-NULL. + (sim_create_inferior): Let cris_start_address when != -1 override + other start-address choices. + +2009-01-06 Hans-Peter Nilsson + + * cris/traps.c (abort): Define to call sim_io_error. + (create_map): Make -1 imply a non-fixed address, not 0. All + callers changed. Only prefer the next higher unmapped address if + the last mapped address is no less than 0x40000000. Check that + the address to be mapped is not already mapped. Update head + comment. + (unmap_pages): Don't call abort when recursive call fails, just + note and return an error if a page in the range couldn't be unmapped. + (cris_bmod_handler, h_supr_set_handler, h_supr_get_handler) + (schedule, make_first_thread, cris_pipe_empty): New local variable sd. + (cris_break_13_handler) : Handle + non-MAP_FIXED argument overlapping existing map. For MAP_FIXED, + don't abort on page not being mapped. Handle non-anon filemap + with length padded to pagesize. + +2009-01-03 Hans-Peter Nilsson + + * cris/sim-if.c (TARGET_AT_NULL, TARGET_AT_PHDR, TARGET_AT_PHENT) + (TARGET_AT_PHNUM, TARGET_AT_PAGESZ, TARGET_AT_BASE) + (TARGET_AT_FLAGS, TARGET_AT_ENTRY, TARGET_AT_UID, TARGET_AT_EUID) + (TARGET_AT_GID, TARGET_AT_EGID, TARGET_AT_HWCAP) + (TARGET_AT_CLKTCK): Remove redundant macros. + (AUX_ENT): Adjust to use standard ELF AT_* macros. + (AUX_ENTF): Ditto. Remove always-0 middle argument. Update all + callers. + (sim_open): Also pass AT_SECURE. + + * cris/sim-main.h (struct _sim_cpu): New member + set_target_thread_data. + * cris/crisv32f.c (CRIS_TLS_REGISTER): Define. + * cris/crisv10f.c: Ditto. + * cris/cris-tmpl.c (MY (set_target_thread_data)): New function. + (MY (f_specific_init)): Set new _sim_cpu member to new function. + * cris/traps.c (TARGET_SYS_set_thread_area): Define. + (cris_break_13_handler) : New + case. + + * cris/traps.c (TARGET_SYS_exit_group): Define. + (cris_break_13_handler): Handle it like the exit for the last + thread. + + * cris/traps.c (TARGET_UTSNAME): Update to 2009-01-01. + (TARGET_EPOCH): Update to match TARGET_UTSNAME. Correct comment. + (cris_break_13_handler) : Update to + 2.6.27. Set machine field to the BFD printable name of the + machine. + + * cris/traps.c (TARGET_MAP_DENYWRITE): Define. + (cris_break_13_handler) : Handle + TARGET_MAP_DENYWRITE. + + * cris/traps.c (TARGET_SYS_access, TARGET_R_OK, TARGET_W_OK) + (TARGET_X_OK, TARGET_F_OK): Define. + (cris_break_13_handler) : New case. + + * cris/semcrisv32f-switch.c: Regenerate. + +2008-12-30 Hans-Peter Nilsson + + * cris/sim-if.c (sim_open): If sim_analyze_program fails, emit + just a short CRIS-specific notice. Tweak the wording for a + failing architecture test. + + * cris/traps.c (TARGET_SYS_writev): New macro. + (is_mapped_only, cris_dump_map): New functions. + (cris_break_13_handler) : Handle more flags + and prot combinations and a non-zero page-offset. If + TARGET_MAP_FIXED, unmap pages before mapping them. + : When checking, allow any length + argument. Don't actually do anything. + : New case. + + * cris/Makefile.in (SIM_OBJS): Remove sim-hload.o. + * cris/sim-if.c: Include elf-bfd.h. + (struct progbounds): New members end_loadmem, start_nonloadmem. + (xprintf, eprintf): New functions, copied from common/sim-load.c. + (cris_load_elf_file, sim_load, cris_get_progbounds): New functions. + (get_progbounds_iterator): Renamed from get_progbounds. Make + static. Update head comment. Set new struct progbounds members. + (exec_load_addr, interp_load_addr, interp_start_addr): New static + variables. + (aux_ent_phdr, aux_ent_phent, aux_ent_phnum, aux_ent_base) + (aux_ent_entry, cris_write_interp, cris_handle_interpreter): New + functions. + (sim_open): New constant array auxv_entries. Rewrite AUX_ENT + handling to use auxv_entries. Improve error message and checking + for invalid programs. Use new variable abfd for the program + instead of for each access reaching into sd to get it. + (sim_create_inferior): If non-zero, use interp_start_addr instead + of the program start address. + (cris_disassemble_insn): Remove incorrect and unclear, supposedly + stale comment. Always specify little-endian. + +2008-07-29 Nick Clifton + + * common/genmloop.sh: Add new parameter: -shell to specify the + command interpreter to use to run the input file. This is + necessary because otherwise SHELL is taken from the user's + environment, and not from the makefile that invoked this script + and the user might not be running an sh-like shell. + * cris/Makefile.in: Pass -shell parameter to genmloop.sh. + * fr30/Makefile.in: Likewise. + * frv/Makefile.in: Likewise. + * i960/Makefile.in: Likewise. + * iq2000/Makefile.in: Likewise. + * m32r/Makefile.in: Likewise. + + * frv/mloop.in: Add missing start of line comment marker. + +2008-07-11 Hans-Peter Nilsson + + * cris/configure: Regenerate to track ../common/common.m4 changes. + * cris/config.in: Ditto. + +2008-06-06 Vladimir Prus + Daniel Jacobowitz + Joseph Myers + + * cris/configure: Regenerate. + +2008-05-09 Olivier Hainque + + * ppc/altivec.igen (vperm): Latch inputs into temporaries. + +2008-03-25 M R Swami Reddy + + * MAINTAINERS: Add myself as maintainer of cr16 port. + +2008-02-12 M Ranga Swami Reddy + + Add simulator for National cr16 processor. + * cr16: New directory. + * configure.ac: Add entry for National cr16. + * configure: Regenerate. + +2008-02-05 DJ Delorie + + * configure.ac (v850): V850 now has a testsuite. + * configure (v850): Likewise. + +2008-01-01 Daniel Jacobowitz + + Updated copyright notices for most files. + +2007-12-19 DJ Delorie + + * frv/frv.c (frvbf_cut): Only look at the six LSBs of + cut_point. + +2007-10-22 Hans-Peter Nilsson + + * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c, + cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c, + cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c, + cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, + cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, + cris/semcrisv32f-switch.c: Regenerate. + +2007-08-24 Joel Brobecker + + Switch the license of all files explicitly copyright the FSF + to GPLv3. + +2007-03-27 Brooks Moses + + * Makefile.in: Add dummy "pdf" target. + +2007-02-20 Hans-Peter Nilsson + + * cris/traps.c (dump_statistics): Change format for cycle numbers + to %llu and cast parameters to unsigned long long. + +2007-02-16 Thiemo Seufer + + * Makefile.in (FLAGS_TO_PASS, TARGET_FLAGS_TO_PASS): Add RUNTEST. + +2007-01-28 Manuel Lauss + + * configure.ac (sh64-*-*): Change to sh64*-*-*. + (sh-*-*): Change to sh*-*-*. + * configure: Regenerated. + +2007-01-09 Daniel Jacobowitz + + Updated copyright notices for most files. + +2006-12-20 Hans-Peter Nilsson + + * Makefile.in (autoconf-common autoheader-common): Only run + autoheader on subdirs with a file config.in. + + * configure.ac (common): Make the default "yes" for all targets + with sim subdirs. + * configure: Regenerate. + + * Makefile.in (autoconf-common autoheader-common): In documented + usage, say SHELL=/bin/sh. + (.PHONY): Add autoheader-common. + + * MAINTAINERS: Add self as authorized committer for *. + +2006-10-02 Edgar E. Iglesias + Hans-Peter Nilsson + + * cris/cris-sim.h (enum cris_unknown_syscall_action_type) + (cris_unknown_syscall_action): Declare. + * cris/sim-if.c (cris_unknown_syscall_action): Define. + (cris_options): Add cris-unknown-syscall option. + (cris_option_handler): Correct comment about and error message for + invalid --cris-cycles argument. Handle --cris-unknown-syscall. + * cris/traps.c: Include stdarg.h + (cris_unknown_syscall): New function. + (cris_break_13_handler): Instead of sim_io_eprintf and + sim_engine_halt, call cris_unknown_syscall to handle more or less + unknown syscalls. Adjust code as necessary to handle return + value. + +2006-09-30 Daniel Jacobowitz + + * MAINTAINERS: Add Dave Brolley for sh64. + +2006-09-30 Hans-Peter Nilsson + + * cris/traps.c (TARGET_PIPE_BUF): New macro. + (cris_pipe_empty): Correct initialization of "remaining". Only + adjust the "write" return value if more than TARGET_PIPE_BUF bytes + are written. + +2006-09-29 Hans-Peter Nilsson + + * cris/configure.ac: Check for limits.h and sys/param.h. + * cris/configure, cris/config.in: Rebuild. + * cris/traps.c (SIM_PATHMAX): New macro. + (cris_break_13_handler): Use SIM_PATHMAX, not MAXPATHLEN. + +2006-08-08 Joel Sherrill + + * configure.ac (sparc-*-rtems*|sparc-*-elf*): Enable erc32 simulator. + * Makefile.in (FLAGS_TO_PASS): Include libdir. + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * cris/configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * cris/configure: Regenerated. + +2006-05-05 Andreas Schwab + + * configure.ac (CFLAGS_FOR_BUILD): Set and substitute. + * configure: Regenerate. + + * Makefile.in (CFLAGS_FOR_BUILD): Define. + (CC_FOR_BUILD): Don't override. + (FLAGS_TO_PASS): Pass CFLAGS_FOR_BUILD. + +2006-05-04 Daniel Jacobowitz + + * MAINTAINERS: Add an "Authorized committers" section, and list + DJ Delorie for v850. + +2006-04-08 Hans-Peter Nilsson + + * cris/crisv32f.c (MY (deliver_interrupt)): Set CCS to new_ccs. + +2006-04-03 Hans-Peter Nilsson + + * cris/dv-cris.c, cris/dv-rv.c, cris/rvdummy.c: New files. + * cris/Makefile.in (CONFIG_DEVICES): Remove redundant setting. + (dv-cris.o, dv-rv.o rvdummy$(EXEEXT), rvdummy.o): New rules. + (all): Depend on rvdummy$(EXEEXT). + * cris/configure.ac: Call SIM_AC_OPTION_WARNINGS. Check for + sys/socket.h and sys/select.h. Call SIM_AC_OPTION_HARDWARE, + default off. + * cris/configure: Regenerate. + * cris/cris-sim.h (cris_have_900000xxif): Declare here. + (enum cris_interrupt_type, crisv10deliver_interrupt) + (crisv32deliver_interrupt: New declarations. + * cris/cris-tmpl.c [WITH_HW] (MY (f_model_insn_after)): Call + sim_events_tickn and set state-events member work_pending when it's + time for the next event. + [WITH_HW] (MY (f_specific_init)): Set CPU-model-specific + interrupt-delivery function. + * cris/crisv10f.c (MY (deliver_interrupt)): New function. + * cris/crisv32f.c (MY (deliver_interrupt)): New function. + * cris/devices.c: Include hw-device.h. + (device_io_read_buffer) [WITH_HW]: Call hw_io_read_buffer. + (device_io_write_buffer): Only perform 0x900000xx-functions if + cris_have_900000xxif is nonzero. Else if WITH_HW defined, + call hw_io_write_buffer. Add return 0 last in function. + * cris/sim-if.c (cris_have_900000xxif): Now global. + (sim_open) [WITH_HW]: Clear deliver_interrupt cpu member. + Force "-model" option, effectively. + * cris/sim-main.h (cris_interrupt_delivery_fn): New type. + (struct _sim_cpu) [WITH_HW]: New member deliver_interrupt. + +2006-04-02 Hans-Peter Nilsson + + * cris/Makefile.in (CRISV10F_OBJS): Remove semcrisv10f-switch.o. + (CRISV32F_OBJS): Remove semcrisv32f-switch.o. + (semcrisv10f-switch.o, semcrisv32f-switch.o: Remove dependency rules. + +2006-03-13 DJ Delorie + + * MAINTAINERS: Add self as m32c sim maintainer. + +2006-02-23 Hans-Peter Nilsson + + * cris/traps.c (syscall_map): Remove CB_SYS_time / TARGET_SYS_time + mapping. + (cris_break_13_handler) : New case. + +2006-01-23 Jim Blandy + + Add simulator for Renesas M32C and M16C. + + * m32c: New directory. + * configure.ac: Add entry for Renesas M32C. + * configure: Regenerate. + +2006-01-10 Hans-Peter Nilsson + + * cris/cris-tmpl.c (MY (f_model_insn_before)): Only display basic + cycle count for the current insn. + +2005-12-06 Hans-Peter Nilsson + + * cris/cpuv10.h, cris/cpuv32.h, cris/cris-desc.c, cris/cris-opc.h, + cris/decodev10.c, cris/decodev10.h, cris/decodev32.c, + cris/decodev32.h, cris/modelv10.c, cris/modelv32.c, + cris/semcrisv10f-switch.c, cris/semcrisv32f-switch.c: Regenerate. + +2005-12-05 Hans-Peter Nilsson + + * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c, + cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c, + cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c, + cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, + cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, + cris/semcrisv32f-switch.c: Regenerate. + +2005-11-20 Hans-Peter Nilsson + + * cris/traps.c (TARGET_O_RDONLY, TARGET_O_WRONLY): Define. + (open_map): Use TARGET_O_ACCMODE, TARGET_O_RDONLY and + TARGET_O_WRONLY. + (cris_break_13_handler) : Add support for + F_GETFL on fd 0, 1 and 2. + +2005-11-17 Hans-Peter Nilsson + + * cris/sim-main.h (struct _sim_cpu): New members last_syscall, + last_open_fd, last_open_flags. + * cris/traps.c: Don't include targ-vals.h. + (TARGET_O_ACCMODE): Define. + (cris_break_13_handler): Set new _sim_cpu members. + : Support special case of F_GETFL. + Rearrange code as switch. Emit "unimplemented" abort for + unimplemented fcntl calls. + + * cris/traps.c (TARGET_SYS_stat): Define. + (syscall_stat32_map): Add entry for TARGET_SYS_stat. + (cris_break_13_handler) : New case. + +2005-11-16 Hans-Peter Nilsson + + * cris/cris-tmpl.c (MY (f_model_insn_before)): Make sure only the + low 32 bits are used after an unsigned long cast. + +2005-05-28 Hans-Peter Nilsson + + * cris/Makefile.in (stamp-v32fmloop): Depend on stamp-v10fmloop. + +2005-05-26 Chris Demetriou + + * MAINTAINERS: Update my mail address, move myself to the + "Past maintainers" section. + +2005-05-17 Corinna Vinschen + + * configure.ac: Add igen to v850 build. + * configure: Regenerate. + +2005-04-29 Paul Brook + + * common/callback.c (PIPE_BUF): Provide default definition. + (os_lstat): Use stat if lstat is not available on the host. + (os_ftruncate): Return EINVAL if not available on the host. + (os_truncate): Ditto. + * common/configure.ac: Check for lstat, truncate and ftruncate. + * common/configure: Regenerate. + * common/config.in: Regenerate. + +2005-04-27 Paul Brook + + * common/Make-common.in: Add $(EXEEXT) to "run". + +2005-04-18 Hans-Peter Nilsson + + * cris/traps.c (cris_break_13_handler) : + For ((len & 8191) != 0 && fd == (USI) -1), don't say this isn't + implemented. In call to create_map, pad length argument to 8k. + +2005-04-15 Corinna Vinschen + + * configure.ac: Add explicit sh64 case. + * configure: Regenerate. + +2005-03-30 Paul Brook + + * arm/wrapper.c: Provide SIGTRAP and SIGBUS. + +2005-03-24 Hans-Peter Nilsson + + * cris/Makefile.in (stamp-v10fcpu, stamp-v32fcpu): Add kludge to + include cgen-ops.h in decodev10.c and decodev32.c. + * cris/sim-main.h: Don't include cgen-ops.h here. + * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c, + cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c, + cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c, + cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, + cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, + cris/semcrisv32f-switch.c: Regenerate. + + * cris/traps.c (cris_break_13_handler) : Rename sa_handler, sa_flags, + sa_restorer, sa_mask_low, sa_mask_high to target_sa_handler etc. + +2005-03-23 Mark Kettenis + + * cris/configure: Regenerate. + +2005-02-28 Jim Blandy + + * d10v/configure.ac, igen/configure.ac, m68hc11/configure.ac, + mips/configure.ac, mn10300/configure.ac, v850/configure.ac: + Regenerated, after change to common/aclocal.m4. + +2005-02-18 Corinna Vinschen + + * iq2000: New target subdirectory. + * configure.ac: Add iq2000 target. + * configure: Regenerate. + +2005-01-29 Hans-Peter Nilsson + + * Makefile.in (all, clean mostlyclean, distclean maintainer-clean) + (realclean, install): Fail if subdir make failed. + +2005-01-28 Hans-Peter Nilsson + + * cris: New directory, simulator for Axis Communications CRIS + including CRIS v32, CGEN-based. + * configure.ac: Add corresponding configury. + * configure: Regenerate. + +2005-01-17 Andrew Cagney + + * configure.ac: For mips*-*-* and mn10300*-*-* configure the + common directory. Remove sparc*-*-* from list. + +2005-01-11 Andrew Cagney + + * Makefile.in (autoconf-common autoheader-common): Add --force to + autoconf and autoheader. + (autoconf-common autoheader-common) + (autoconf-install autoheader-install): Check for configure.ac, not + configure.in. + * configure.ac: Delete AC_CONFIG_AUX_DIR. + * configure: Re-generate. + +2005-01-07 Andrew Cagney + + * configure.ac: Replace configure.in. Requires autoconf 2.59 and + correctly calls AC_CONFIG_SUBDIRS. + * configure: Re-generate. + +2004-12-01 Andrew Cagney + + * i960, h8500: Delete directory. + +2004-11-12 Andrew Cagney + + * d30v, fr30, mn10200, z8k: Delete directory. + +2004-03-10 Ben Elliston + + * MAINTAINERS: Update my mail address. + +2004-01-26 Chris Demetriou + + * configure.in (mips*-*-*): Configure in testsuite. + * configure: Regenerate. + +2003-10-08 Dave Brolley + + * configure.in: Move frv handling to alphabetically correct placement. + +2003-09-03 Andreas Schwab + + * Makefile.in (FLAGS_TO_PASS): Pass down $(bindir) and $(mandir). + +2003-08-29 Dave Brolley + + * MAINTAINERS: Add myself as maintainer of the FRV port. + +2003-08-20 Michael Snyder + Dave Brolley + + * frv/: New directory, simulator for the Fujitsu FRV. + * configure.in: Add frv configury. + * configure: Regenerate. + +2003-08-10 Ben Elliston + + * MAINTAINERS: Update my mail address. + +2003-08-09 Andrew Cagney + + * MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop + maintenance. List igen and sh maintainers. Mention that target + and global maintainers pick up the slack. + +2003-07-09 Michael Snyder + + * configure.in: Add testsuite to extra_subdirs for sh. + * configure: Regenerate. + +2003-01-23 Nick Clifton + + * Add sh2e support: + +2002-04-02 Alexandre Oliva + + * sh/gencode.c: Replace sh3e with sh2e except in fsqrt. + +2002-08-24 Geoffrey Keating + + * MAINTAINERS: Update my email address. + +2002-07-17 Andrew Cagney + + * w65/: Delete directory. + +2002-07-16 Andrew Cagney + + * configure.in (extra_subdirs): Mark fr30-*-* as obsolete. + * configure: Re-generate. + +2002-07-13 Andrew Cagney + + * configure.in (extra_subdirs): Mark d30v-*-* as obsolete. + * configure: Re-generate. + +2002-06-16 Andrew Cagney + + * Makefile.in (autoconf-changelog autoheader-changelog): Let name, + id, date and host to be overriden by NAME, ID, DATE and HOST + respectfully. Use ISO dates. + +Thu Jun 6 12:34:13 2002 Andrew Cagney + + * Makefile.in (ChangeLog): New makefile variable. + * README-HACKING: Mention the ChangeLog makefile variable. + +2002-06-01 Andrew Cagney + + * tic80/: Delete directory. + +2002-05-16 Stephane Carrez + + * MAINTAINERS: Update my email address. + +2002-03-06 Stephane Carrez + + * MAINTAINERS: Record self as maintainer of m68hc11 simulator. + +2002-03-01 Frank Ch. Eigler + + * MAINTAINERS: Record self as a co-maintainer of just common/. + +2002-02-07 Nick Clifton + + * MAINTAINERS: Point to GDB files describing overall maintaince + and check-in procedures. + +2002-01-10 Nick Clifton + + * MAINTAINERS: Add myself for ARM portions. + +2001-10-19 Andrew Cagney + + * configure.in: When Linux or NetBSD, enable PowerPC simulator. + * configure: Re-generate. + +2001-02-16 Ben Elliston + + * MAINTAINERS: Add myself for common portions. + +2001-01-15 Chris Demetriou + + * MAINTAINERS: Added self and Andrew for the mips sim. + +2000-10-25 Geoff Keating + + * MAINTAINERS: Added self and Andrew for the ppc sim. + +Thu Jul 27 21:26:26 2000 Andrew Cagney + + From Stephane Carrez : + * m68hc11: New directory. + * configure.in: Add. + * configure: Regenerate. + +Tue Jul 4 13:43:54 2000 Andrew Cagney + + * tic80: New directory. + * configure.in: Add configury. + * configure: Regenerate. + +2000-04-20 Nick Clifton + + * configure.in (extra_subdirs): Add testsuite to strongarm + directories. + * configure: Regenerate. + +Sat Mar 4 16:48:54 2000 Andrew Cagney + + * MAINTAINERS: New file. Blank. + +1999-11-18 Ben Elliston + + * configure.in: Require autoconf 2.13 and remove obsolete + invocation of AC_C_CROSS. + * configure: Regenerate. + +1999-09-29 Doug Evans + + * configure.in: Configure the testsuite directory for thumb. + * configure: Regenerate. + +1999-07-16 Ben Elliston + + * configure.in: Configure the testsuite directory for arm. + * configure: Regenerate. + +1999-04-08 Nick Clifton + + * configure.in: Add support for MCore target. + * configure: Regenerate. + +1999-03-14 Stan Shebs + + * Makefile.in (FLAGS_TO_PASS, TARGET_FLAGS_TO_PASS): Remove + RUNTEST instead of commenting out, fixes portability problem. + +1999-02-08 Nick Clifton + + * configure.in: Add support for StrongARM target. + * configure: Regenerate. + +1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) + + * configure.in: Require autoconf 2.12.1 or higher. + +1998-12-08 James E Wilson + + * configure.in (i960-*-*): Add. + * configure: Rebuild. + +Wed Nov 4 19:11:43 1998 Dave Brolley + + * configure.in: Added case for fr30-*-*. + * configure: Regenerated. + +Fri Sep 25 10:12:19 1998 Christopher Faylor + + * ppc/Makefile.in: Add EXEEXT to installed powerpc-eabi-run program + to allow successful operation on Windows. + +Thu May 28 14:59:46 1998 Jillian Ye + + * Makefile.in: Take RUNTEST out of FLAGS_TO_PASS so that make + check can be invoked recursively. + +Wed Apr 29 12:38:53 1998 Mark Alexander + + * configure.in: Build simulator on sparclite and sparc86x targets. + * configure: Regenerate. + +Sun Apr 26 15:21:01 1998 Tom Tromey + + * Makefile.in (autoconf-common autoheader-common): Don't pass -l + to autoconf and autoheader. + +Fri Apr 24 11:14:13 1998 Tom Tromey + + * Makefile.in (autoconf-common autoheader-common): Pass `-l + ../common' to autoconf and autoheader. Unconditionally run + autoconf in every subdir. + (autoconf-changelog autoheader-changelog): Unconditionally run + commands in every subdir. + (autoconf-install autoheader-install): Likewise. + +Tue Mar 24 17:12:43 1998 Stu Grossman + + * Makefile.in: Get SHELL from configure. + * (FLAGS_TO_PASS): Pass down SHELL. + * configure: Regenerate with autoconf 2.12.1 to fix shell issues for + NT native builds. + +Tue Mar 24 11::18:00 1998 Joyce Janczyn + + * configure.in (extra_subdirs): Enable igen for mn10300. + * configure: Re-generate. + +Tue Dec 2 10:10:42 1997 Nick Clifton + + * configure.in (extra_subdirs): Add support for thumb target. + + * configure (extra_subdirs): Add support for thumb target. + +Wed Oct 8 12:38:48 1997 Andrew Cagney + + * configure.in (extra_subdirs): Add IGEN directory when MIPS + target. + * configure: Regenerate. + +Fri Sep 12 13:10:31 1997 Andrew Cagney + + * configure.in (extra_subdirs): v850ea needs igen. + * configure: Re-generate. + +Mon Sep 1 16:48:23 1997 Andrew Cagney + + * configure.in (testdir): When a testsuite directory, add that to + the list of confdirs. + +Tue Aug 19 11:17:46 1997 Andrew Cagney + + * configure.in (extra_subdirs): Enable igen ready for V850. + +Tue Aug 26 15:14:48 1997 Andrew Cagney + + * configure.in (w65-*-*, only_if_enabled): Set. + * configure: Re-generate. + +Mon Aug 25 16:26:53 1997 Andrew Cagney + + * configure.in (sparc*-*-*, only_if_enabled): Set + only_if_enabled=yes. Check only_if_enabled before enabling a + simulator. + * configure: Regenerate. + +Mon Aug 18 10:56:59 1997 Nick Clifton + + * configure.in (extra_subdirs): Add v850e target. + +Mon Aug 18 10:56:59 1997 Nick Clifton + + * configure.in (extra_subdirs): Add v850ea target. + +Fri Jul 25 11:40:47 1997 Doug Evans + + * configure.in (sparc*-*-*): Don't build erc32. + * configure: Regenerate. + +Thu Apr 24 00:47:20 1997 Doug Evans + + * configure.in (m32r-*-*): New target. + * configure: Regenerate. + + * Makefile.in (autoconf-common, autoconf-changelog): Change $* to $@. + +Mon Apr 21 22:57:55 1997 Andrew Cagney + + * Makefile.in (.NOEXPORT, MAKEOVERRIDES): Moved to end, BSD make + thought that .NOEXPORT was the default target. + +Fri Apr 11 17:18:07 1997 Ian Lance Taylor + + * Makefile.in (clean mostlyclean): Restore targets accidentally + deleted in earlier change. + +Thu Apr 3 12:20:32 1997 Andrew Cagney + + * Makefile.in (autoheader-common, autoheader-changelog, + autoheader-install): Perform autoheader in addition to autoconf. + +Wed Apr 2 15:09:05 1997 Doug Evans + + * Makefile.in (autoconf-install): New target. + (autoconf-changelog): Try different way to obtain user name. + +Wed Apr 2 14:25:52 1997 Andrew Cagney + + * Makefile.in (autoconf-changelog): New target, update + ChangeLog for all subdirectories - normally used after + autoconf-common target. + +Wed Mar 19 14:26:21 1997 Andrew Cagney + + * configure.in (extra_subdirs): Include testsuite for d30v. + * configure: Regenerate. + + * Makefile.in (RUNTEST, RUNTESTFLAGS): Borrow test rules from + ../gdb/Makefile.in + (check): New rules - drive the testsuite. + +Mon Mar 3 13:01:00 1997 Jeffrey A Law (law@cygnus.com) + + * configure.in: Add mn10200 configure lines accidentally + removed. + * configure: Regenerated. + +Wed Feb 19 10:34:20 1997 Andrew Cagney + + * configure.in (extra_subdirs): Generalize common sub directory + into a list. + (extra_subdirs): For d30v add igen to the list to be built. + +Sun Feb 16 16:37:47 1997 Andrew Cagney + + * configure.in (d30v): New target. + * configure: Regenerated. + +Wed Feb 19 23:17:13 1997 Jeffrey A Law (law@cygnus.com) + + * configure.in: Don't require GCC to build the mn10200 + simulator anymore. + * configure: Rebuilt. + +Wed Feb 5 13:28:13 1997 Doug Evans + + * configure.in: Don't configure any subdirs if no simulator + is being built. Don't use erc32 for sparc64. + * configure: Regenerated. + +Tue Feb 4 13:19:39 1997 Doug Evans + + * Makefile.in (autoconf-common): New target. + * configure.in: Do configure common. + * configure: Regenerated. + +Thu Jan 23 13:59:52 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in: Don't configure common anymore. Files + from common are now built in the individual simualtor directories. + This fixes problems with the WinGDB build procedure. + +Mon Jan 13 13:16:42 1997 Jeffrey A Law (law@cygnus.com) + + * configure: Enable the mn10200 simulator. + +Wed Nov 20 01:00:36 1996 Doug Evans + + * configure.in (configdirs): Add common. + * configure: Regenerated. + +Fri Nov 1 08:03:30 1996 Michael Meissner + + * configure.in (powerpc*-*-linux*): Treat like the other powerpc + system V based targets. + * configure: Regenerate. + +Thu Oct 17 12:50:08 1996 Doug Evans + + * configure.in (--enable-sim-powerpc): Delete. + (--enable-sim): Add. + * configure: Regenerated. + +Fri Oct 11 21:13:43 1996 Jeffrey A Law (law@cygnus.com) + + * configure.in: Only build the V850 simulator if + we are using gcc. + * configure: Rebuild. + +Sun Sep 8 17:22:50 1996 Ian Lance Taylor + + * configure.in: Do build erc32 for DOS and Windows hosts. + * configure: Rebuild. + +Wed Sep 4 18:11:27 1996 Stu Grossman (grossman@critters.cygnus.com) + + * Makefile.in erc32/Makefile.in: Don't set srcroot. This should + be inherited from the parent. Remove INSTALL_XFORM and + INSTALL_XFORM1. Make INSTALL be set from configure. + +Wed Sep 4 15:49:16 1996 Ian Lance Taylor + + * configure.in: Only build the MIPS simulator if we are using + gcc. + * configure: Rebuild. + +Wed Aug 28 19:05:23 1996 Jeffrey A Law (law@cygnus.com) + + * configure.in (v850-*-*): Added V850 simulator. + +Thu Aug 1 17:08:41 1996 Martin M. Hunt + + * configure.in (d10v-*-*): Added D10V simulator. + +Wed Jun 26 12:33:57 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, + INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. + (docdir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + (AC_PROG_INSTALL): Added. + * configure: Rebuilt. + +Mon Jun 24 14:18:26 1996 Ian Lance Taylor + + * configure.in: Only configure erc32 if using gcc. + * configure: Rebuild. + +Tue Jun 4 09:24:21 1996 Michael Meissner + + * configure.in (sim_target): Build PowerPC simulator for powerpc + System V.4, Solaris, and Elf targets. + * configure: Regenerate with autoconf 2.10. + +Wed May 22 12:10:49 1996 Rob Savoye + + * configure.in: Only built erc32 simulator on Unix hosts as it + uses pseudo ttys. + * configure: Regenerated with autoconf 2.8. + +Sun May 19 20:20:40 1996 Rob Savoye + + * erc32: Sparc simulator from the ESA. + +Sun Apr 7 21:00:09 1996 Fred Fish + + From: Miles Bader + * configure.in: Use AC_CHECK_TOOL to find AR & RANLIB. + * configure: Regenerate using autoconf. + +Thu Feb 22 11:31:50 1996 Michael Meissner + + * Makefile.in (install): Fix typo. + +Wed Feb 21 11:59:57 1996 Ian Lance Taylor + + * configure: Regenerate with autoconf 2.7. + + * Makefile.in (all): Simplify. + (clean, mostlyclean): SUBDIRS may contain whitespace; fix the loop + as in the all target. + (distclean, maintainer-clean, realclean): Likewise. + (install): Likewise. + +Thu Feb 15 18:37:00 1996 Fred Fish + + * Makefile.in (all): Remove extra '\' char from shell script. + +Wed Feb 14 16:43:59 1996 Mike Meissner + + * Makefile.in (all): Avoid a for loop with zero elements, even if + the loop will not be executed because of an if statement. + +Wed Jan 31 21:48:34 1996 Fred Fish + + * Makefile.in (install): Add missing semicolon in "fi \". + +Thu Nov 9 16:10:56 1995 Michael Meissner + + * Makefile.in (AR, CC, CFLAGS, CC_FOR_BUILD, RANLIB): Pick up + defaults from configure. + + * configure.in: Pick up AR, CC, CFLAGS, CC_FOR_BUILD, RANLIB using + configure defaults. + (powerpc*-*-eabi*): Build simulator for all powerpc eabi targets + if either --enable-sim-powerpc is used, or the host compiler is + GCC. + +Wed Nov 8 15:46:49 1995 James G. Smith + + * configure.in (mips*-*-*): Added "mips" simulator target. + * configure: Re-generated. + +Tue Oct 10 11:08:20 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + (FLAGS_TO_PASS): Remove BISON. + +Sun Oct 8 04:26:27 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * configure.in: Explicitly `exit 0' for broken shells. + * configure: Rebuilt. + +Fri Oct 6 12:03:27 1995 Jim Wilson + + * common/run.c (main): Initialize the callbacks. + +Wed Sep 20 13:34:50 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Fri Aug 25 11:53:43 1995 Michael Meissner + + * configure.in (powerpc*-*-eabisim*): Only build the simulator if + the target is powerpc*-*-eabisim*, since it requires GCC to build. + +Mon Aug 21 17:53:48 1995 Michael Meissner + + * configure.in (powerpc{,le}-*-*): Add psim from Andrew Cagney + . + * configure: Regnerate from configure.in. + +Thu Aug 3 10:45:37 1995 Fred Fish + + * Update all FSF addresses except those in COPYING* files. + +Thu Jul 20 15:17:29 1995 Fred Fish + + * Makefile.in (CC_FOR_BUILD): Define default and arrange to pass + submakes either default or passed in value. + +Wed Jul 5 14:32:54 1995 J.T. Conklin + + * Makefile.in (all, clean, distclean, mostlyclean, realclean, + install): Changed targets so that they descend all + subdirectories in $(SUBDIRS). + (*-all, *-clean, *-install): Removed targets. + + * configure.in: Don't bother with target makefile fragments, they + are no longer needed. + * configure: regenerated. + + * Makefile.in, configure.in: converted to autoconf. + * configure: New file, generated with autconf 2.4. + +Wed May 24 14:48:46 1995 Steve Chamberlain + + * Makefile.in: Support ARM. + * configure.in: Ditto. + +Sun Jan 15 16:53:47 1995 Steve Chamberlain + + * Makefile.in: Support W65. + * configure.in: Ditto. + +Sun Mar 13 09:27:50 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * Makefile.in: Add TAGS target. + +Mon Sep 13 12:47:15 1993 K. Richard Pixley (rich@sendai.cygnus.com) + + * Makefile.in (all-z8k, install-z8k, clean-z8k, all-h8300, + install-h8300, clean-h8300, all-h8500, install-h8500, + clean-h8500, all-sh, install-sh, clean-sh): do not echo + recursion lines. + +Wed Jun 30 14:12:05 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) + + * Makefile.in: remove endian.h trace from h8500 + +Sun Jun 13 13:08:58 1993 Jim Kingdon (kingdon@cygnus.com) + + * Makefile.in: Add distclean, realclean, and mostlyclean targets. + +Fri May 21 11:21:16 1993 david d `zoo' zuhn (zoo at cirdan.cygnus.com) + + * Makefile.in: make all of the all-* target (except all-nothing) + depend on endian.h, so that if we're not building a simulator, we + don't built endian + +Fri May 21 10:55:06 1993 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in (check, installcheck): Added dummy targets. + +Mon May 3 21:39:43 1993 Fred Fish (fnf@cygnus.com) + + * Makefile.in (endian): Find endian.c in $(srcdir), and also + explicitly make it, since some makes apparently don't work with + VPATH and .c to executable rules (SunOS make for example). + +Mon May 3 08:29:01 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * Makefile.in (endian): Add explicit rule for broken makes. + +Mon Mar 15 15:47:53 1993 Ian Lance Taylor (ian@cygnus.com) + + * Makefile.in (info, install-info): New targets. + (DO_INSTALL): Renamed from INSTALL, which is overridden by the top + level Makefile. + +Wed Feb 10 20:12:27 1993 K. Richard Pixley (rich@ok.cygnus.com) + + * Makefile.in (endian.h): build endian.h via a temporary file so + that we don't leave an incomplete file lying around on + interrupted builds. + (clean): remove endian, e.h, and endian.h. + +Mon Feb 8 11:46:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * Makefile.in, configure.in: if target isn't supported, build a + harmless makefile. + + diff --git a/external/gpl3/gdb/dist/sim/MAINTAINERS b/external/gpl3/gdb/dist/sim/MAINTAINERS new file mode 100644 index 000000000000..d273002d043b --- /dev/null +++ b/external/gpl3/gdb/dist/sim/MAINTAINERS @@ -0,0 +1,40 @@ + SIM Maintainers + +The simulator is part of the GDB project, so see the file +gdb/MAINTAINERS for general information about maintaining these files. + +If you are considering contributing a patch, please see the file +gdb/CONTRIBUTE. Patches to these files should be posted to: +gdb-patches@sources.redhat.com + + Maintainers for particular sims: + +arm Nick Clifton +bfin Mike Frysinger +cr16 M R Swami Reddy +frv Dave Brolley +igen (igen simulators) +lm32 Jon Beniston +m32c DJ Delorie +m32r Doug Evans +m68hc11 Stephane Carrez +microblaze Michael Eager +mips Thiemo Seufer +moxie Anthony Green +rx DJ Delorie +sh (global maintainers) +sh64 Dave Brolley +common Frank Ch. Eigler +* (target, then global maintainers) + + Authorized committers for particular sims: +v850 DJ Delorie +* Hans-Peter Nilsson + + Past sim maintainers: + +common Ben Elliston +mips Andrew Cagney +mips Chris Demetriou +ppc Geoff Keating +ppc Andrew Cagney diff --git a/external/gpl3/gdb/dist/sim/Makefile.in b/external/gpl3/gdb/dist/sim/Makefile.in new file mode 100644 index 000000000000..c31efe0e9bad --- /dev/null +++ b/external/gpl3/gdb/dist/sim/Makefile.in @@ -0,0 +1,270 @@ +# Makefile template for Configure for the sim library. +# Copyright (C) 1993, 1995, 1997, 1998, 2007, 2008, 2009, 2010, 2011 +# Free Software Foundation, Inc. +# Written by Cygnus Support. +# +# This file is part of BFD, the Binary File Descriptor library. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +VPATH = @srcdir@ +srcdir = @srcdir@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +bindir = @bindir@ +libdir = @libdir@ +tooldir = $(libdir)/$(target_alias) + +datarootdir = @datarootdir@ +datadir = @datadir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +man3dir = $(mandir)/man3 +man4dir = $(mandir)/man4 +man5dir = $(mandir)/man5 +man6dir = $(mandir)/man6 +man7dir = $(mandir)/man7 +man8dir = $(mandir)/man8 +man9dir = $(mandir)/man9 +infodir = @infodir@ +includedir = @includedir@ + +SHELL = @SHELL@ + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +AR = @AR@ +AR_FLAGS = rc +CC = @CC@ +CFLAGS = @CFLAGS@ +CC_FOR_BUILD = @CC_FOR_BUILD@ +CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@ +MAKEINFO = makeinfo +RANLIB = @RANLIB@ + +SUBDIRS = @subdirs@ + +INCDIR = $(srcdir)/../include +CSEARCH = -I. -I$(srcdir) -I$(INCDIR) +DEP = mkdep + +#### Makefile fragments come in here. +# @target_makefile_frag@ +### + +# Name of the ChangeLog file. +ChangeLog = ChangeLog + + +RUNTEST = `if [ -f $${srcdir}/../dejagnu/runtest ] ; then \ + echo $${srcdir}/../dejagnu/runtest ; else echo runtest; \ + fi` +RUNTESTFLAGS= + +FLAGS_TO_PASS = \ + "prefix=$(prefix)" \ + "exec_prefix=$(exec_prefix)" \ + "bindir=$(bindir)" \ + "mandir=$(mandir)" \ + "libdir=$(libdir)" \ + "against=$(against)" \ + "AR=$(AR)" \ + "AR_FLAGS=$(AR_FLAGS)" \ + "CC=$(CC)" \ + "CC_FOR_BUILD=$(CC_FOR_BUILD)" \ + "CFLAGS=$(CFLAGS)" \ + "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \ + "RANLIB=$(RANLIB)" \ + "MAKEINFO=$(MAKEINFO)" \ + "INSTALL=$(INSTALL)" \ + "INSTALL_DATA=$(INSTALL_DATA)" \ + "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \ + "RUNTEST=$(RUNTEST)" \ + "RUNTESTFLAGS=$(RUNTESTFLAGS)" \ + "SHELL=$(SHELL)" + +# The use of $$(x_FOR_TARGET) reduces the command line length by not +# duplicating the lengthy definition. +TARGET_FLAGS_TO_PASS = \ + "prefix=$(prefix)" \ + "exec_prefix=$(exec_prefix)" \ + "against=$(against)" \ + 'CC=$$(CC_FOR_TARGET)' \ + "CC_FOR_TARGET=$(CC_FOR_TARGET)" \ + "CFLAGS=$(CFLAGS)" \ + "CHILLFLAGS=$(CHILLFLAGS)" \ + 'CHILL=$$(CHILL_FOR_TARGET)' \ + "CHILL_FOR_TARGET=$(CHILL_FOR_TARGET)" \ + "CHILL_LIB=$(CHILL_LIB)" \ + 'CXX=$$(CXX_FOR_TARGET)' \ + "CXX_FOR_TARGET=$(CXX_FOR_TARGET)" \ + "CXXFLAGS=$(CXXFLAGS)" \ + "INSTALL=$(INSTALL)" \ + "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \ + "INSTALL_DATA=$(INSTALL_DATA)" \ + "MAKEINFO=$(MAKEINFO)" \ + "RUNTEST=$(RUNTEST)" \ + "RUNTESTFLAGS=$(RUNTESTFLAGS)" + + +all: + @rootme=`pwd` ; export rootme ; \ + for dir in . `echo ${SUBDIRS} | sed 's/testsuite//'` ; do \ + if [ "$$dir" = "." ]; then \ + true; \ + elif [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) $(FLAGS_TO_PASS)) || exit 1; \ + else true; fi; \ + done + +clean mostlyclean: + @rootme=`pwd` ; export rootme ; \ + for dir in . ${SUBDIRS}; do \ + if [ "$$dir" = "." ]; then \ + true; \ + elif [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) $(FLAGS_TO_PASS) $@) || exit 1; \ + else true; fi; \ + done + +distclean maintainer-clean realclean: + @rootme=`pwd` ; export rootme ; \ + for dir in . ${SUBDIRS}; do \ + if [ "$$dir" = "." ]; then \ + true; \ + elif [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) $(FLAGS_TO_PASS) $@) || exit 1; \ + else true; fi; \ + done + rm -f Makefile config.cache config.log config.status + +install: + @rootme=`pwd` ; export rootme ; \ + for dir in . ${SUBDIRS}; do \ + if [ "$$dir" = "." ]; then \ + true; \ + elif [ -d $$dir ]; then \ + (cd $$dir; $(MAKE) $(FLAGS_TO_PASS) install) || exit 1; \ + else true; fi; \ + done + +installcheck: + @echo No installcheck target is available yet for the GNU simulators. + +installcheck: + +# The check target can not use subdir_do, because subdir_do does not +# use TARGET_FLAGS_TO_PASS. +check: force + @if [ -f testsuite/Makefile ]; then \ + rootme=`pwd`; export rootme; \ + rootsrc=`cd $(srcdir); pwd`; export rootsrc; \ + cd testsuite; \ + $(MAKE) $(TARGET_FLAGS_TO_PASS) check; \ + else true; fi + + + +info: +install-info: +dvi: +pdf: +install-pdf: +html: +install-html: + +### +### + +.NOEXPORT: +MAKEOVERRIDES= + +.PHONY: check installcheck +check: +installcheck: + +TAGS: + +force: + +Makefile: Makefile.in config.status + $(SHELL) ./config.status + +config.status: configure + $(SHELL) ./config.status --recheck + +# Utility to run autoconf in each directory that uses the common framework. +# This is intended to be invoked in $srcdir as +# "make -f Makefile.in autoconf-common SHELL=/bin/sh". +.PHONY: autoconf-common autoheader-common +autoconf-common autoheader-common: + for d in * ; \ + do \ + if [ -d $$d -a -f $$d/configure.ac ] ; \ + then \ + echo "Running autoconf in $$d ..." ; \ + (cd $$d && autoconf --force) ; \ + if [ $@ = autoheader-common ] && [ -f $$d/config.in ] ; \ + then \ + echo "Running autoheader in $$d ..." ; \ + (cd $$d && autoheader --force) ; \ + fi ; \ + fi ; \ + done + +autoconf-changelog autoheader-changelog: + id=$(ID) ; \ + test x$$id = x && id="`id | sed -e 's/^[^(]*(\([^)]*\).*$$/\1/'`" ; \ + name=$(NAME) ; \ + test x$$name = x && name=`grep "^$$id:" /etc/passwd | cut -f 5 -d ':'` ; \ + host=$(HOST) ; \ + test x$$host = x && host="`hostname`" ; \ + date=$(DATE) ; \ + test x$$date = x && date="`date +%Y-%m-%d`" ; \ + echo "$$date $$name $$id@$$host" ; \ + for d in * ; \ + do \ + if [ -d $$d -a -f $$d/configure.ac ] ; \ + then \ + echo "Creating new-$(ChangeLog) in $$d ..." ; \ + ( echo "$$date $$name <$$id@$$host>" ; \ + echo "" ; \ + echo " * configure: Regenerated to track ../common/aclocal.m4 changes." ; \ + if [ $@ = autoheader-changelog ] ; \ + then \ + echo " * config.in: Ditto." ; \ + fi ; \ + echo "" ; \ + cat $$d/$(ChangeLog) \ + ) > $$d/new-$(ChangeLog) ; \ + fi ; \ + done + +autoconf-install autoheader-install: + for d in * ; \ + do \ + if [ -d $$d -a -f $$d/configure.ac ] ; \ + then \ + echo "Moving $$d/new-$(ChangeLog) to $$d/$(ChangeLog) ..." ; \ + mv $$d/new-$(ChangeLog) $$d/$(ChangeLog) ; \ + fi ; \ + done diff --git a/external/gpl3/gdb/dist/sim/README-HACKING b/external/gpl3/gdb/dist/sim/README-HACKING new file mode 100644 index 000000000000..77cad9427b62 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/README-HACKING @@ -0,0 +1,504 @@ +This is a loose collection of notes for people hacking on simulators. +If this document gets big enough it can be prettied up then. + +Contents + +- The "common" directory +- Common Makefile Support +- TAGS support +- Generating "configure" files +- tconfig.in +- C Language Assumptions +- "dump" commands under gdb + +The "common" directory +====================== + +The common directory contains: + +- common documentation files (e.g. run.1, and maybe in time .texi files) +- common source files (e.g. run.c) +- common Makefile fragment and configury (e.g. Make-common.in, aclocal.m4). + +In addition "common" contains portions of the system call support +(e.g. callback.c, nltvals.def). + +Even though no files are built in this directory, it is still configured +so support for regenerating nltvals.def is present. + +Common Makefile Support +======================= + +A common configuration framework is available for simulators that want +to use it. The common framework exists to remove a lot of duplication +in configure.in and Makefile.in, and it also provides a foundation for +enhancing the simulators uniformly (e.g. the more they share in common +the easier a feature added to one is added to all). + +The configure.in of a simulator using the common framework should look like: + +--- snip --- +dnl Process this file with autoconf to produce a configure script. +sinclude(../common/aclocal.m4) +AC_PREREQ(2.5)dnl +AC_INIT(Makefile.in) + +SIM_AC_COMMON + +... target specific additions ... + +SIM_AC_OUTPUT +--- snip --- + +SIM_AC_COMMON: + +- invokes the autoconf macros most often used by the simulators +- defines --enable/--with options usable by all simulators +- initializes sim_link_files/sim_link_links as the set of symbolic links + to set up + +SIM_AC_OUTPUT: + +- creates the symbolic links defined in sim_link_{files,links} +- creates config.h +- creates the Makefile + +The Makefile.in of a simulator using the common framework should look like: + +--- snip --- +# Makefile for blah ... +# Copyright blah ... + +## COMMON_PRE_CONFIG_FRAG + +# These variables are given default values in COMMON_PRE_CONFIG_FRAG. +# We override the ones we need to here. +# Not all of these need to be mentioned, only the necessary ones. +# In fact it is better to *not* mention ones if the value is the default. + +# List of object files, less common parts. +SIM_OBJS = +# List of extra dependencies. +# Generally this consists of simulator specific files included by sim-main.h. +SIM_EXTRA_DEPS = +# List of flags to always pass to $(CC). +SIM_EXTRA_CFLAGS = +# List of extra libraries to link with. +SIM_EXTRA_LIBS = +# List of extra program dependencies. +SIM_EXTRA_LIBDEPS = +# List of main object files for `run'. +SIM_RUN_OBJS = run.o +# Dependency of `all' to build any extra files. +SIM_EXTRA_ALL = +# Dependency of `install' to install any extra files. +SIM_EXTRA_INSTALL = +# Dependency of `clean' to clean any extra files. +SIM_EXTRA_CLEAN = + +## COMMON_POST_CONFIG_FRAG + +# Rules need to build $(SIM_OBJS), plus whatever else the target wants. + +... target specific rules ... +--- snip --- + +COMMON_{PRE,POST}_CONFIG_FRAG are markers for SIM_AC_OUTPUT to tell it +where to insert the two pieces of common/Make-common.in. +The resulting Makefile is created by doing autoconf substitions on +both the target's Makefile.in and Make-common.in, and inserting +the two pieces of Make-common.in into the target's Makefile.in at +COMMON_{PRE,POST}_CONFIG_FRAG. + +Note that SIM_EXTRA_{INSTALL,CLEAN} could be removed and "::" targets +could be used instead. However, it's not clear yet whether "::" targets +are portable enough. + +TAGS support +============ + +Many files generate program symbols at compile time. +Such symbols can't be found with grep nor do they normally appear in +the TAGS file. To get around this, source files can add the comment + +/* TAGS: foo1 foo2 */ + +where foo1, foo2 are program symbols. Symbols found in such comments +are greppable and appear in the TAGS file. + +Generating "configure" files +============================ + +For targets using the common framework, "configure" can be generated +by running `autoconf'. + +To regenerate the configure files for all targets using the common framework: + + $ cd devo/sim + $ make -f Makefile.in SHELL=/bin/sh autoconf-common + +To add a change-log entry to the ChangeLog file for each updated +directory (WARNING - check the modified new-ChangeLog files before +renaming): + + $ make -f Makefile.in SHELL=/bin/sh autoconf-changelog + $ more */new-ChangeLog + $ make -f Makefile.in SHELL=/bin/sh autoconf-install + +In a similar vein, both the configure and config.in files can be +updated using the sequence: + + $ cd devo/sim + $ make -f Makefile.in SHELL=/bin/sh autoheader-common + $ make -f Makefile.in SHELL=/bin/sh autoheader-changelog + $ more */new-ChangeLog + $ make -f Makefile.in SHELL=/bin/sh autoheader-install + +To add the entries to an alternative ChangeLog file, use: + + $ make ChangeLog=MyChangeLog .... + + +tconfig.in +========== + +File tconfig.in defines one or more target configuration macros +(e.g. a tm.h file). There are very few that need defining. +For a list of all of them, see common/tconfig.in. +It contains them all, commented out. +The intent is that a new port can just copy this file and +define the ones it needs. + +C Language Assumptions +====================== + +The programmer may assume that the simulator is being built using an +ANSI C compiler that supports a 64 bit data type. Consequently: + + o prototypes can be used (although using + PARAMS() and K&R declarations wouldn't + go astray). + + o If sim-types.h is included, the two + types signed64 and unsigned64 are + available. + + o The type `unsigned' is valid. + +However, the user should be aware of the following: + + o GCC's `LL' is NOT acceptable. + Microsoft-C doesn't reconize it. + + o MSC's `i64' is NOT acceptable. + GCC doesn't reconize it. + + o GCC's `long long' MSC's `_int64' can + NOT be used to define 64 bit integer data + types. + + o An empty array (eg int a[0]) is not valid. + +When building with GCC it is effectivly a requirement that +--enable-build-warnings=,-Werror be specified during configuration. + +"dump" commands under gdb +========================= + +gdbinit.in contains the following + +define dump +set sim_debug_dump () +end + +Simulators that define the sim_debug_dump function can then have their +internal state pretty printed from gdb. + +FIXME: This can obviously be made more elaborate. As needed it will be. + +Rebuilding nltvals.def +====================== + +Checkout a copy of the SIM and LIBGLOSS modules (Unless you've already +got one to hand): + + $ mkdir /tmp/$$ + $ cd /tmp/$$ + $ cvs checkout sim-no-testsuite libgloss-no-testsuite newlib-no-testsuite + +Configure things for an arbitrary simulator target (I've d10v for +convenience): + + $ mkdir /tmp/$$/build + $ cd /tmp/$$/build + $ /tmp/$$/devo/configure --target=d10v-elf + +In the sim/common directory rebuild the headers: + + $ cd sim/common + $ make headers + +To add a new target: + + devo/sim/common/gennltvals.sh + + Add your new processor target (you'll need to grub + around to find where your syscall.h lives). + + devo/sim//Makefile.in + + Add the definition: + + ``NL_TARGET = -DNL_TARGET_d10v'' + + just before the line COMMON_POST_CONFIG_FRAG. + + devo/sim//*.[ch] + + Include targ-vals.h instead of syscall.h. + +Tracing +======= + +For ports based on CGEN, tracing instrumentation should largely be for free, +so we will cover the basic non-CGEN setup here. The assumption is that your +target is using the common autoconf macros and so the build system already +includes the sim-trace configure flag. + +The full tracing API is covered in sim-trace.h, so this section is an overview. + +Before calling any trace function, you should make a call to the trace_prefix() +function. This is usually done in the main sim_engine_run() loop before +simulating the next instruction. You should make this call before every +simulated insn. You can probably copy & paste this: + if (TRACE_ANY_P (cpu)) + trace_prefix (sd, cpu, NULL_CIA, oldpc, TRACE_LINENUM_P (cpu), NULL, 0, ""); + +You will then need to instrument your simulator code with calls to the +trace_generic() function with the appropriate trace index. Typically, this +will take a form similar to the above snippet. So to trace instructions, you +would use something like: + if (TRACE_INSN_P (cpu)) + trace_generic (sd, cpu, TRACE_INSN_IDX, "NOP;"); + +The exact output format is up to you. See the trace index enum in sim-trace.h +to see the different tracing info available. + +To utilize the tracing features at runtime, simply use the --trace-xxx flags. + run --trace-insn ./some-program + +Profiling +========= + +Similar to the tracing section, this is merely an overview for non-CGEN based +ports. The full API may be found in sim-profile.h. Its API is also similar +to the tracing API. + +Note that unlike the tracing command line options, in addition to the profile +flags, you have to use the --verbose option to view the summary report after +execution. Tracing output is displayed on the fly, but the profile output is +only summarized. + +To profile core accesses (such as data reads/writes and insn fetches), add +calls to PROFILE_COUNT_CORE() to your read/write functions. So in your data +fetch function, you'd use something like: + PROFILE_COUNT_CORE (cpu, target_addr, size_in_bytes, map_read); +Then in your data write function: + PROFILE_COUNT_CORE (cpu, target_addr, size_in_bytes, map_write); +And in your insn fetcher: + PROFILE_COUNT_CORE (cpu, target_addr, size_in_bytes, map_exec); + +To use the PC profiling code, you simply have to tell the system where to find +your simulator's PC and its size. So in your sim_open() function: + STATE_WATCHPOINTS (sd)->pc = address_of_cpu0_pc; + STATE_WATCHPOINTS (sd)->sizeof_pc = number_of_bytes_for_pc_storage; +In a typical 32bit system, the sizeof_pc will be 4 bytes. + +To profile branches, in every location where a branch insn is executed, call +one of the related helpers: + PROFILE_BRANCH_TAKEN (cpu); + PROFILE_BRANCH_UNTAKEN (cpu); +If you have stall information, you can utilize the other helpers too. + +Environment Simulation +====================== + +The simplest simulator doesn't include environment support -- it merely +simulates the Instruction Set Architecture (ISA). Once you're ready to move +on to the next level, call the common macro in your configure.ac: +SIM_AC_OPTION_ENVIRONMENT + +This will support for the user, virtual, and operating environments. See the +sim-config.h header for a more detailed description of them. The former are +pretty straight forward as things like exceptions (making system calls) are +handled in the simulator. Which is to say, an exception does not trigger an +exception handler in the simulator target -- that is what the operating env +is about. See the following userspace section for more information. + +Userspace System Calls +====================== + +By default, the libgloss userspace is simulated. That means the system call +numbers and calling convention matches that of libgloss. Simulating other +userspaces (such as Linux) is pretty straightforward, but let's first focus +on the basics. The basic API is covered in include/gdb/callback.h. + +When an instruction is simulated that invokes the system call method (such as +forcing a hardware trap or exception), your simulator code should set up the +CB_SYSCALL data structure before calling the common cb_syscall() function. +For example: +static int +syscall_read_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); +} +static int +syscall_write_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, const char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); +} +void target_sim_syscall (SIM_CPU *cpu) +{ + SIM_DESC sd = CPU_STATE (cpu); + host_callback *cb = STATE_CALLBACK (sd); + CB_SYSCALL sc; + + CB_SYSCALL_INIT (&sc); + + sc.func = ; + sc.arg1 = ; + sc.arg2 = ; + sc.arg3 = ; + sc.arg4 = ; + sc.p1 = (PTR) sd; + sc.p2 = (PTR) cpu; + sc.read_mem = syscall_read_mem; + sc.write_mem = syscall_write_mem; + + cb_syscall (cb, &sc); + + ; + ; +} +Some targets store the result and error code in different places, while others +only store the error code when the result is an error. + +Keep in mind that the CB_SYS_xxx defines are normalized values with no real +meaning with respect to the target. They provide a unique map on the host so +that it can parse things sanely. For libgloss, the common/nltvals.def file +creates the target's system call numbers to the CB_SYS_xxx values. + +To simulate other userspace targets, you really only need to update the maps +pointers that are part of the callback interface. So create CB_TARGET_DEFS_MAP +arrays for each set (system calls, errnos, open bits, etc...) and in a place +you find useful, do something like: + +... +static CB_TARGET_DEFS_MAP cb_linux_syscall_map[] = { +# define TARGET_LINUX_SYS_open 5 + { CB_SYS_open, TARGET_LINUX_SYS_open }, + ... + { -1, -1 }, +}; +... + host_callback *cb = STATE_CALLBACK (sd); + cb->syscall_map = cb_linux_syscall_map; + cb->errno_map = cb_linux_errno_map; + cb->open_map = cb_linux_open_map; + cb->signal_map = cb_linux_signal_map; + cb->stat_map = cb_linux_stat_map; +... + +Each of these cb_linux_*_map's are manually declared by the arch target. + +The target_sim_syscall() example above will then work unchanged (ignoring the +system call convention) because all of the callback functions go through these +mapping arrays. + +Events +====== + +Events are scheduled and executed on behalf of either a cpu or hardware devices. +The API is pretty much the same and can be found in common/sim-events.h and +common/hw-events.h. + +For simulator targets, you really just have to worry about the schedule and +deschedule functions. + +Device Trees +============ + +The device tree model is based on the OpenBoot specification. Since this is +largely inherited from the psim code, consult the existing psim documentation +for some in-depth details. + http://sourceware.org/psim/manual/ + +Hardware Devices +================ + +The simplest simulator doesn't include hardware device support. Once you're +ready to move on to the next level, call the common macro in your configure.ac: +SIM_AC_OPTION_HARDWARE(yes,,devone devtwo devthree) + +The basic hardware API is documented in common/hw-device.h. + +Each device has to have a matching file name with a "dv-" prefix. So there has +to be a dv-devone.c, dv-devtwo.c, and dv-devthree.c files. Further, each file +has to have a matching hw_descriptor structure. So the dv-devone.c file has to +have something like: + const struct hw_descriptor dv_devone_descriptor[] = { + {"devone", devone_finish,}, + {NULL, NULL}, + }; + +The "devone" string as well as the "devone_finish" function are not hard +requirements, just common conventions. The structure name is a hard +requirement. + +The devone_finish() callback function is used to instantiate this device by +parsing the corresponding properties in the device tree. + +Hardware devices typically attach address ranges to themselves. Then when +accesses to those addresses are made, the hardware will have its callback +invoked. The exact callback could be a normal I/O read/write access, as +well as a DMA access. This makes it easy to simulate memory mapped registers. + +Keep in mind that like a proper device driver, it may be instantiated many +times over. So any device state it needs to be maintained should be allocated +during the finish callback and attached to the hardware device via set_hw_data. +Any hardware functions can access this private data via the hw_data function. + +Ports (Interrupts / IRQs) +========================= + +First, a note on terminology. A "port" is an aspect of a hardware device that +accepts or generates interrupts. So devices with input ports may be the target +of an interrupt (accept it), and/or they have output ports so that they may be +the source of an interrupt (generate it). + +Each port has a symbolic name and a unique number. These are used to identify +the port in different contexts. The output port name has no hard relationship +to the input port name (same for the unique number). The callback that accepts +the interrupt uses the name/id of its input port, while the generator function +uses the name/id of its output port. + +The device tree is used to connect the output port of a device to the input +port of another device. There are no limits on the number of inputs connected +to an output, or outputs to an input, or the devices attached to the ports. +In other words, the input port and output port could be the same device. + +The basics are: + - each hardware device declares an array of ports (hw_port_descriptor). + any mix of input and output ports is allowed. + - when setting up the device, attach the array (set_hw_ports). + - if the device accepts interrupts, it will have to attach a port callback + function (set_hw_port_event) + - connect ports with the device tree + - handle incoming interrupts with the callback + - generate outgoing interrupts with hw_port_event diff --git a/external/gpl3/gdb/dist/sim/arm/COPYING b/external/gpl3/gdb/dist/sim/arm/COPYING new file mode 100644 index 000000000000..ebb24a85e9d0 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/external/gpl3/gdb/dist/sim/arm/ChangeLog b/external/gpl3/gdb/dist/sim/arm/ChangeLog new file mode 100644 index 000000000000..1e0714461b7f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/ChangeLog @@ -0,0 +1,1254 @@ +2010-05-26 Ozkan Sezer + + * communicate.c (MYread_char): Check error return from accept() call + by its equality to -1 not by it being negative. + (MYread_charwait): Likewise. + * main.c (main): Likewise for both socket() and accept() calls. + +2010-04-14 Mike Frysinger + + * wrapper.c (sim_write): Add const to buffer arg. + +2010-01-09 Ralf Wildenhues + + * configure: Regenerate. + +2009-08-22 Ralf Wildenhues + + * config.in: Regenerate. + * configure: Likewise. + + * configure: Regenerate. + +2008-11-24 Joel Sherrill + + * arminit.c, iwmmxt.c: Include to + eliminate warning. +2008-07-11 Hans-Peter Nilsson + + * configure: Regenerate to track ../common/common.m4 changes. + * config.in: Ditto. + +2008-06-06 Vladimir Prus + Daniel Jacobowitz + Joseph Myers + + * configure: Regenerate. + * wrapper.c (sim_target_display_usage): Add help parameter. + +2007-02-27 Mark Mitchell + + * armos.c (SWIflen): Do not treate file descriptor zero as + special. + +2007-02-15 Nick Clifton + + * armemu.c (handle_v6_insn): Fix typo in sign extension test of + the sext and sxtah instructions. + +2007-02-08 Daniel Jacobowitz + + Reported by timeless@gmail.com: + * wrapper.c (sim_target_parse_arg_array): Do not return void value. + +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in: Regenerate. + +2006-06-13 Richard Earnshaw + + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * configure: Regenerated. + +2006-03-07 Paul Brook + + * elfos.c (ARMul_OSHandleSWI): Call correct function for IsTTY. + +2006-02-01 Shaun Jackman + + * armos.c (ARMul_OSHandleSWI): Handle the RedBoot system + call meminfo. Return ENOSYS for unhandled RedBoot syscalls. + +2005-11-23 Mark Mitchell + + * wrapper.c (gdb/signals.h): Include it. + (SIGTRAP): Don't define. + (SIGBUS): Likewise. + (sim_stop_reason): Use TARGET_SIGNAL_* instead of SIG*. + +2005-11-16 Shaun Jackman + + * armos.c: Include limits.h + (unlink): Remove this macro. It is unused in this file and + conflicts with sim_callback->unlink. + (PATH_MAX): Define as 1024 if not already defined. + (ReadFileName): New function. + (SWIopen): Fix a potential buffer overflow. + (SWIremove): New function. + (SWIrename): Ditto. + (ARMul_OSHandleSWI): Handle the RDP calls SWI_IsTTY, + SWI_Remove, and SWI_Rename, as well as the RDI calls + AngelSWI_Reason_IsTTY, AngelSWI_Reason_Remove, and + AngelSWI_Reason_Rename. + +2005-09-19 Paul Brook + + * armdefs.h: Define ARMsword and ARMsdword. Use stdint.h when + available. + * armemu.c: Use them. + * armvirt.c (ARMul_MemoryInit): Use correct type for size. + * configure.ac: Check for stdint.h. + * config.in: Regenerate. + * configure: Regenerate. + +2005-05-24 Nick Clifton + + * thumbemu.c (handle_v6_thumb_insn): New function. + (ARMul_ThumbDecode): Call handle_v6_thumb_insn() when an undefined + instruction binary is encountered. + +2005-05-12 Nick Clifton + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + COPYING, Makefile.in, armcopro.c, armdefs.h, armemu.c, + armemu.h, armfpe.h, arminit.c, armopts.h, armos.c, armos.h, + armrdi.c, armsupp.c, armvirt.c, bag.c, bag.h, communicate.c, + communicate.h, dbg_conf.h, dbg_cp.h, dbg_hif.h, dbg_rdi.h, + gdbhost.c, gdbhost.h, iwmmxt.c, iwmmxt.h, kid.c, main.c, + maverick.c, parent.c, thumbemu.c, wrapper.c + +2005-04-20 Nick Clifton + + * armemu.c (handle_v6_insn): New function - emulate a few of the + v6 instructions - the ones now generated by GCC. + (ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is + found. + * armdefs.h (struct ARMul_State): Add new field: is_v6. + (ARM_v6_Prop): Define. + * arminit.c (ARMul_NewState): Initialise the v6 flag. + (ARMul_SelectProcessor): Determine if the v6 flag should be + set. + * wrapper.c (sim_create_inferior): For unknown architectures, + default to allowing the v6 instructions. + +2005-04-18 Nick Clifton + + * iwmmxt.c (WMAC, WMADD): Move casts from the LHS of an assignment + operator to the RHS. + (WSLL, WSRA, WSRL, WUNPCKEH, WUNPACKEL): Use ULL suffix to + indicate an unsigned long long constant. + +2005-03-23 Mark Kettenis + + * configure: Regenerate. + +2005-01-14 Andrew Cagney + + * configure.ac: Sinclude aclocal.m4 before common.m4. Add + explicit call to AC_CONFIG_HEADER. + * configure: Regenerate. + +2005-01-12 Andrew Cagney + + * configure.ac: Update to use ../common/common.m4. + * configure: Re-generate. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +2004-12-08 Hans-Peter Nilsson + + * configure: Regenerate for ../common/aclocal.m4 update. + +2004-06-28 Andrew Cagney + + * armemu.c: Rename ui_loop_hook to deprecated_ui_loop_hook. + +2003-12-29 Mark Mitchell + + * armos.c (fcntl.h): Do not include it. + (O_RDONLY): Do not define. + (O_WRONLY): Likewise. + (O_RDWR): Likewise. + (targ-vals.h): Include it. + (translate_open_mode): Use TARGET_O_* instead of O_*. + (SWIopen): Likewise. + * Makefile.in (armos.o): Depend on targ-vals.h. + +2003-04-13 Nick Clifton + + * armvirt.c (GetWord): Only call XScale_check_memacc if in XScale + mode. + (PutWord): Likewise. + +2003-03-30 Nick Clifton + + * configure.in (CON_FLAGS): Remove. + (COPRO): Unconditionally include iwmmxt.o. + * configure: Regenerate. + * Makefile.in (CON_FLAGS): Remove. + * armcopro.c: Remove use of __IWMMXT__ flag. + * wrapper.c: Likewise. + * armemu.c: Likewise. + Add explanatory comment for suppressed code. + +2003-03-27 Nick Clifton + + * armos.c (ARMul_OsHandleSWI): Catch SWIs for unhandled vectors. + +2003-03-27 Nick Clifton + + * configure.in: (CON_FLAGS): Define and intialise. + (COPRO): Add iwmmxt.o if configuring for XScale. + * configure: Regenerate. + * Makefile.in (iwmmxt.o): Add rule to build. + (COM_FLAGS): Define. + (ALL_FLAGS): Add CON_FLAGS. + * armcopro.c (ARMul_CoProInit): Initialise iWMMXt coprocessors. + * armdefs.h (struct ARMul_State): Add 'is_iWMMXt' field. + (ARM_iWMMXt_Prop): Define. + * armemu.c (ARMul_Emulate16): Intercept iWMMXt instructions and + pass to coprocessor. + * arminit.c (ARMul_NewState): Initialise 'is_iWMMXt'. + (ARMul_Abort): Catch branches through uninitialised vectors. + * armos.c (softevtorcode): Update comment. + (ARMul_OsInit): Use ARMUndefinedInstrV. + * wrapper.c (sim_create_inferior): Handle iWMMXt processor type. + (sim_store_register): Handle iWMMXt registers. + (sim_fetch_register): Handle iWMMXt registers. + * iwmmxt.h: New file. Exported iWMMXt coprocessor emulator + functions. + * iwmmxt.c: New file: iWMMXt emulator. + +2003-03-20 Nick Clifton + + * Contribute support for Cirrus Maverick ARM co-processor, + written by Aldy Hernandez and + Andrew Cagney : + + * maverick.c: New file: Support for Maverick floating point + co-processor. + * Makefile.in: Add maverick.o target. + * configure.in (COPRO): Add maverick.o. + * configure: Regenerate. + * armcopro.c (ARMul_CoProInit): Only initialise co-processors + available on target processor. Add code to initialse Maverick + co-processor support code. + * armdefs.h (ARMul_state): Add is_ep9312 field. + (ARM_ep9312_Prop): Define. + * armemu.h: Add prototypes for Maverick co-processor + functions. + * arminit.c (ARMul_SelectProcessor): Initialise the + co-processor support once the chip has been selected. + * wrapper.c: Add support for Maverick co-processor. + (init): Do not call ARMul_CoProInit. Delays this until the + chip has been selected. + +2003-03-02 Nick Clifton + + * armos.c (SWIWrite0): Catch big-endian bug when printing + characters. + +2003-02-27 Andrew Cagney + + * wrapper.c (sim_create_inferior, sim_open): Rename _bfd to bfd. + +2003-01-10 Ben Elliston + + * README.Cygnus: Rename from this .. + * README: .. to this. + +2002-09-27 Andrew Cagney + + * wrapper.c (sim_open): Add support for -m. + (mem_size): Reduce to 2MB. + Fix PR gdb/433. + +2002-08-15 Nick Clifton + + * armos.c (ARMul_OSHandleSWI): Catch and ignore SWIs of -1, they + can be caused by an interrupted system call being resumed by GDB. + +2002-07-05 Nick Clifton + + * armemu.c (ARMul_Emulate32): Add more tests for valid MIA, MIAPH + and MIAxy instructions. + +2002-06-21 Nick Clifton + + * armos.h (ADP_Stopped_RunTimeError): Set correct value. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2002-06-12 Andrew Cagney + + * Makefile.in: Update copyright. + (wrapper.o): Specify dependencies. + * wrapper.c: Include "gdb/sim-arm.h". + (sim_store_register, sim_fetch_register): Rewrite using `enum + arm_sim_regs' and a switch. + +2002-06-09 Andrew Cagney + + * wrapper.c: Include "gdb/callback.h" and "gdb/remote-sim.h". + * armos.c: Include "gdb/callback.h". + +2002-05-29 Nick Clifton + + * armcopro.c (XScale_check_memacc): Set the FSR and FAR registers + if a Data Abort is detected. + +2002-05-27 Nick Clifton + + * armvirt.c (GetWord): Only perform access checks if 'check' + is set. + (PutWord): Likewise. + * wrapper.c (sim_create_inferior): Report unknown machine + numbers. + * thumbemu.c (ARMul_ThumbDecode, Case 31): Do not set LR to pc + + 2, it has already been advanced. + +2002-05-23 Nick Clifton + + * thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1) + instruction do not add in the second bit of the base address - + this has already been accounted for. + +2002-05-21 Nick Clifton + + * armcopro.c (check_cp13_access): Allow access to register 1 when + CRm is 1. + (write_cp13_reg): Allow bit 0 of reg 1 of CRm 1 to be written to. + +2002-05-17 Nick Clifton + + * Makefile.in (SIM_TARGET_SWITCHES): Define. + * armos.c (swi_mask): Define. Initialise to supporting all + SWI emulations. + (ARMul_OSInit): For XScale targets, only support the ANGEL + SWI interface. (This is at the request if Intel). + (ARMul_OSHandleSWI): Examine swi_mask to see if a particular + SWI call should be emulated. + Do not fall through from AngelSWI_Reason_WriteC. + Propagate exit code from RedBoot Exit SWI. + * rdi-dgb.h (swi_mask): Prototype. + (SWI_MASK_DEMON, SWI_MASK_ANGEL, SWI_MASK_REDBOOT): Define. + * wrapper.c (sim_target_parse_command_line): New function. + Look for and handle --swi-support switch. + (sim_target_parse_arg_array): New function. Process an argv + array for parsing by sim_target_parse_command_line. + (sim_target_display_usage): New function. Describe syntax of + --swi-suppoort switch. + (sim_open): Add call to sim_target_parse_arg_array). + +2002-05-09 Nick Clifton + + * armos.c (ARMul_OSHandleSWI): Support the RedBoot SWI in ARM + mode and some of its system calls. + +2002-03-17 Anthony Green + + * wrapper.c (mem_size): Increase the default target memory to 8MB. + +2002-02-21 Keith Seitz + + * armos.c (SWIWrite0): Use generic host_callback mechanism + for supported OS functions "open", "close", "write", etc. + (SWIopen): Likewise. + (SWIread): Likewise. + (SWIwrite): Likewise. + (SWIflen): Likewise. + (ARMul_OSHandleSWI): Likewise. + +2002-02-05 Nick Clifton + + * wrapper.c (sim_create_inferior): Modify previous patch so that + it is only triggered for COFF format executables. + +2002-02-04 Nick Clifton + + * wrapper.c (sin_create_inferior): If a v5 architecture is + detected, assume it might be an XScale binary, since there is no + way to distinguish between the two in the COFF file format. + +2002-01-10 Nick Clifton + + * arminit.c (ARMul_Abort): Fix parameters passed to CPRead[13]. + * armemu.c (ARMul_Emulate32): Fix parameters passed to CPRead[13] + and CPRead[14]. + Fix formatting. Improve layout. + * armemu.h: Fix formatting. Improve layout. + +2002-01-09 Nick Clifton + + * wrapper.c (sim_fetch_register): If fetching more than 4 bytes + return zeroes in the other words. + General formatting tidy ups. + +2001-11-16 Ben Harris + + * Makefile.in (armemu32.o): Replace $< with autoconf recommended + $(srcdir)/.... + (armemu26.o): Ditto. + +2001-10-18 Nick Clifton + + * armemu.h (CP_ACCESS_ALLOWED): New macro. + Fix formatting. + * armcopro.c (read_cp14_reg): Make static. + (write_cp14_reg): Make static. + (check_cp13_access): Use CP_ACCESS_ALLOWED macro. + Fix formatting. + * armsupp.c (ARMul_LDC): Check CP_ACCESS_ALLOWED. + (ARMul_STC): Check CP_ACCESS_ALLOWED. + (ARMul_MCR): Check CP_ACCESS_ALLOWED. + (ARMul_MRC): Check CP_ACCESS_ALLOWED. + (ARMul_CDP): Check CP_ACCESS_ALLOWED. + Fix formatting. + * armemu.c (MCRR): Check CP_ACCESS_ALLOWED. Test Rd and Rn not + equal to 15. + (MRRC): Check CP_ACCESS_ALLOWED. Test Rd and Rn not equal to 15. + Fix formatting. + +2001-05-11 Nick Clifton + + * armemu.c (ARMul_Emulate32): Fix handling of XScale LDRD and STRD + instructions with post indexed addressing modes. + +2001-05-08 Jens-Christian Lache + + * armsupp.c (ARMul_FixCPSR): Check Mode not Bank in order to + determine rocesor mode. + +2001-04-18 matthew green + + * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. + (read_cp15_reg): Make non-static. + (XScale_cp15_LDC): Update for write_cp15_reg() change. + (XScale_cp15_MCR): Likewise. + (XScale_cp15_write_reg): Likewise. + (XScale_check_memacc): New function. Check for breakpoints being + activated by memory accesses. Does not support the Branch Target + Buffer. + (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. + (XScale_debug_moe): New function. Set the debug Method Of Entry, + if configured. + (write_cp14_reg): Reset count counter if requested. + * armdefs.h (struct ARMul_State): New members `LastTime' and + `CP14R0_CCD' used for the timer/counters. + (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, + ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, + ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, + ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, + ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, + ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, + ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, + ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New + defines for XScale registers. + (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. + (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. + (ARMul_Emulate32): Handle the clock counter and hardware instruction + breakpoints. Call XScale_set_fsr_far() for software breakpoints and + software interrupts. + (LoadMult): Call XScale_set_fsr_far() for data aborts. + (LoadSMult): Likewise. + (StoreMult): Likewise. + (StoreSMult): Likewise. + * armemu.h (write_cp15_reg): Update prototype. + * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. + (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 + register 0. + * armvirt.c (GetWord): Call XScale_check_memacc(). + (PutWord): Likewise. + +2001-03-20 Nick Clifton + + * armvirt.c (ARMul_ReLoadInstr): Do not enable alignment checking + when loading unaligned thumb instructions. + +2001-03-06 Nick Clifton + + * thumbemu.c (ARMul_ThumbDecode): Delete label bo_blx2. + Compute destination address of BLX(1) instruction by + taking bit 1 from PC and not from bit 0 of the offset. + +2001-02-27 Nick Clifton + + * armvirt.c (GetWord): Add new parameter - check - to enable or + disable the alignment checking. + (PutWord): Add new parameter - check - to enable or disable the + alignment checking. + (ARMul_ReLoadInstr): Pass extra parameter to GetWord. + (ARMul_ReadWord): Pass extra parameter to GetWord. + (ARMul_WriteWord): Pass extra parameter to PutWord. + (ARMul_StoreHalfWord): Pass extra parameter to PutWord. + (ARMul_WriteByte): Pass extra parameter to GetWord. + (ARMul_SwapWord): Pass extra parameter to PutWord. + (ARMul_SafeReadByte): New Function: Read a byte but do not abort. + (ARMul_SafeWriteByte): New Function: Write a byte but do not abort. + + * armdefs.h: Add prototypes for ARMul_SafeReadByte and + ARMul_SafeWriteByte. + + * wrapper.c (sim_write): Use ARMul_SafeWriteByte. + (sim_read): Use ARMul_SafeReadByte. + + * armos.c (in_SWI_handler): Remove. + (SWIWrite0): Use ARMul_SafeReadByte. + (WriteCommandLineTo): Use ARMul_SafeWriteByte. + (SWIopen): Use ARMul_SafeReadByte. + (SWIread): Use ARMul_SafeWriteByte. + (SWIwrite): Use ARMul_SafeReadByte. + (ARMul_OSHandleSWI): Remove use of is_SWI_handler. + (ARMul_OSException): Remove use of is_SWI_handler. + +2001-02-16 Nick Clifton + + * armemu.c: Remove Prefetch abort for breakpoints. Instead set + the state to RESUME. + +2001-02-14 Nick Clifton + + * armemu.c: Add code to preserve processor mode when a prefetch + abort is signalled after processing a breakpoint. + + * wrapper.c (sim_create_inferior): Reset processor into ARM mode + for any machine type except the early ARMs. + +2001-02-13 Nick Clifton + + * armos.c (in_SWI_handler): New static variable. + (ARMul_OSHandleSWI): Set in_SWI_handler whilst emulating a SWI. + (ARMul_OSException): Ignore exceptions generated whilst emulating + a SWI. + +2001-02-12 Nick Clifton + + * armemu.h (NEGBRANCH): Fix defintion. + +2001-02-01 Nick Clifton + + * armemu.c (LoadSMult): Update base address register after + restoring register bank. + (StoreMult): Update base address register after restoring register + bank. + +2001-01-31 Nick Clifton + + * armvirt.c (PutWord): Detect installation of SWI vector. + (SWI_vector_installed): Define. + * armos.c (ARMul_OsInit): Reset SWI_vector_installed. + * armos.h (SWI_vector_installed): Declare. + * wrapper.c (SWI_vector_installed): Remove definition. + (sim_write): Remove check of SWI vector installation + +2000-12-18 Nick Clifton + + * armemu.c (ARMul_Emulate26): Fix test for StoreDouble + instruction. + +2000-12-10 Nick Clifton + + * armos.c (ARMul_OSHandleSWI): Add 0x91 as an FPE SWI. + +2000-12-07 Nick Clifton + + * armemu.c (ARMul_Emulate26): Detect double word load and + store instructions and call emulation routines. + (Handle_Load_Double): Emulate a double word load instruction. + (Handle_Store_Double): Emulate a double word store + instruction. + +2000-12-03 Nick Clifton + + * armos.c: Fix formatting. + (ARMul_OSHandleSWI): Suppress support of DEMON SWIs when in xscale + mode. + +2000-11-29 Nick Clifton + + * armdefs.h (State): Add 'v5e' and 'xscale' fields. + (ARM_v5e_Prop): Define. + (ARM_XScale_Prop): Define. + + * wrapper.c (sim_create_inferior): Select processor based on + machine number. + (SWI_vector_installed): New boolean. Set to true if the SWI + vector address is written to by the executable. + + * arminit.c (ARMul_NewState): Switch default to 32 bit mode. + (ARMul_SelectProcessor): Initialise v5e and xscale signals. + (ARMul_Abort): Fix calculation of LR address. + + * armos.c (ARMul_OSHandleSWI): If a SWI vector has been installed + and a SWI is not handled by the simulator, pass the SWI off to the + vector, otherwise issue a warning message and continue. + + * armsupp.c (ARMul_CPSRAltered): Set S bit aswell. + + * thumbemu.c: Add v5 instruction simulation. + * armemu.c: Add v5, XScale and El Segundo instruction simulation. + + * armcopro.c: Add XScale co-processor emulation. + * armemu.h: Add exported XScale co-processor functions. + +2000-09-15 Nick Clifton + + * armdefs.h: Rename StrongARM property to v4_ARM and add v5 ARM + property. Delete unnecessary processor names. + (ARM_Strong_Prop): Delete. + (STRONGARM): Delete. + (ARM_v4_Prop): Add. + (ARM_v5_Prop): Add + (State): Delete is_StrongARM boolean. Add is_v4 and is_v5 + booleans. + + * armemu.h (BUSUSEDINCPCS): Use is_v4 boolean. + (BUSUSEDINCPCN): Use is_v4 boolean. + + * arminit.c (ARMul_NewState): Initialise is_v4 and is_v5 fields. + (ARMul_SelectProcessor): Change second parameter from 'processor' + to 'properties'. Set is_v4 and is_v5 booleans in State. + + * armrdi.c: Remove use of ARM processor names. Replace with ARM + processor properties. + + * wrapper.c (sim_create_inferior): Choose properties passed to + ARMul_SelectProcessor based on machine number. + +2000-08-14 Nick Clifton + + * armemu.c (LHPOSTDOWN): Compute write back value before + performing load in case the offset register is overwritten. + (LHPOSTUP): Ditto. + +2000-07-14 Fernando Nasser + + * wrapper.c (sim_create_inferior): Fix typo in the previous patch. + +2000-07-14 Fernando Nasser + + * wrapper.c (sim_create_inferior): Reset mode to ARM when creating a + new inferior. + +2000-07-04 Alexandre Oliva + + * armvirt.c (ABORTS): Do not define. + + * armdefs.h (struct ARMul_State): Add is_StrongARM. + (ARM_Strong_Prop, STRONGARM): Define. + * arminit.c (ARMul_NewState): Reset is_StrongARM. + (ARMul_SelectProcessor): Set is_StrongARM. + * wrapper.c (sim_create_inferior): Use bfd machine type to + determine processor type to emulate. + * armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC + when emulating StrongARM. + + * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn. + + * armemu.h (INSN_SIZE): New macro. + (SET_ABORT): Save CPSR in SPSR and set LR. + * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE. + (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode. + * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE. + + * armemu.c (LoadSMult): Use WriteR15() to discard the least + significant bits of PC. + + * armemu.h (WRITEDESTB): New macro. + * armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to + modify PC. Moved the existing logic... + (WriteR15Branch): ... here. New function. + (WriteR15, WriteSR15): Drop the two least significant bits. + (LoadSMult): Use WriteR15Branch() to modify PC. + (LoadMult): Use WRITEDESTB() instead of WRITEDEST(). + + * armemu.h (GETSPSR): Call ARMul_GetSPSR(). + * armsupp.c (ARMul_CPSRAltered): Zero out bits as they're + extracted from state->Cpsr, but preserve the unused bits. + (ARMul_GetCPSR): Get bits preserved in state->Cpsr. + (ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to + get the full CPSR word. + + * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New. + (SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros. + (SETPSR, SET_INTMODE, SETCC): Removed. + * armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit + mask. Use SETPSR_* to modify PSR. + (ARMul_SetCPSR): Load all bits from value. + * armemu.c (ARMul_Emulate, msr): Do not test bit mask. + + * armemu.c (ARMul_Emulate): Compute writeback value before + loading, since the offset register may be the destination + register. + + * armdefs.h (SYSTEMBANK): Define as USERBANK. + * armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases. + +2000-06-22 Alexandre Oliva + + * armemu.c (Multiply64): Fix computation of flag N. + + * armemu.c (MultiplyAdd64): Fix computation of flag N. + +2000-06-20 Alexandre Oliva + + * armemu.h (NEGBRANCH): Do not overwrite the two most significant + bits of the offset. + +2000-05-25 Nick Clifton + + * armcopro.c (MMUMCR): Only indicate mode change if a singal has + really changed. + (MMUWrite): Only indicate mode change if a singal has really + changed. + + * armdefs.h (SYSTEMMODE): Define. + (BANK_CAN_ACEESS_SPSR): Define. + + * armemu.c (ARM_Emulate26): If the mode has changed allow the PC + to advance before stopping the emulation. + + * arminit.c (ARMul_Reset): Ensure Mode field of State is set + correctly. + + * armos.c (ARMul_OSInit): Create a initial stack pointer for + System mode. + + * armsupp.c (ModeToBank): Remove unused first parameter. + Add support for System Mode. + (ARMul_GetSPSR): Use BANK_CAN_ACCESS_SPSR macro. + (ARMul_SetSPSR): Use BANK_CAN_ACCESS_SPSR macro. + (ARMul_FixSPSR): Use BANK_CAN_ACCESS_SPSR macro. + (ARMulSwitchMode): Add support for System Mode. + +Wed May 24 14:40:34 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-05-23 Nick Clifton + + * wrapper.c (sim_store_register): Special handling for CPSR + register. + +2000-03-11 Philip Blundell + + * armemu.c (LoadSMult, LoadMult): Correct handling of aborts. + Patch from Allan Skillman . + +Wed Mar 22 15:24:21 2000 glen mccready + + * wrapper.c (sim_open,sim_close): Copy into myname, free myname. + +2000-02-08 Nick Clifton + + * wrapper.c: Fix compile time warning messages. + * armcopro.c: Fix compile time warning messages. + * armdefs.h: Fix compile time warning messages. + * armemu.c: Fix compile time warning messages. + * armemu.h: Fix compile time warning messages. + * armos.c: Fix compile time warning messages. + * armsupp.c: Fix compile time warning messages. + * armvirt.c: Fix compile time warning messages. + * bag.c: Fix compile time warning messages. + +2000-02-02 Bernd Schmidt + + * *.[ch]: Use indent to make readable. + +1999-11-22 Nick Clifton + + * armos.c (SWIread): Generate an error message if a huge read is + performed. + (SWIwrite): Generate an error message if a huge write is + performed. + +1999-10-27 Nick Clifton + + * thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb + breakpoint. + +1999-10-08 Ulrich Drepper + + * armos.c (SWIopen): Always pass third parameter with 0666 since + otherwise uninitialized memory gets access if the O_CREAT bit is + set and so we possibly cannot access the file afterwards. + +1999-09-29 Doug Evans + + * armos.c (SWIWrite0): Send output to stdout instead of stderr. + (ARMul_OSHandleSWI, case SWI_WriteC,AngelSWI_Reason_WriteC): Ditto. + +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-05-08 Felix Lee + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-04-06 Keith Seitz + + * wrapper.c (stop_simulator): New global. + (sim_stop): Set sim state to STOP and set + stop_simulator. + (sim_resume): Reset stop_simulator. + (sim_stop_reason): If stop_simulator is set, tell gdb + that the we took SIGINT. + * armemu.c (ARMul_Emulate26): Don't loop forever. Stop if + stop_simulator is set. + +1999-04-02 Keith Seitz + + * armemu.c (ARMul_Emulate26): If NEED_UI_LOOP_HOOK, call ui_loop_hook + whenever the counter expires. + * Makefile.in (SIM_EXTRA_CFLAGS): Include define NEED_UI_LOOP_HOOK. + +1999-03-24 Nick Clifton + + * armemu.c (ARMul_Emulate26): Handle new breakpoint value. + * thumbemu.c (ARMul_ThumbDecode): Handle new breakpoint value. + +Mon Sep 14 09:00:05 1998 Nick Clifton + + * wrapper.c (sim_open): Set endianness according to BFD or command + line switch. + + * tconfig.in: Define SIM_HAVE_BIENDIAN. + +Thu Aug 27 11:00:05 1998 Nick Clifton + + * armemu.c (Multiply64): Test for Rm (rather than Rs) not being + the same as either RdHi or RdLo. + +Thu Jul 2 10:24:35 1998 Nick Clifton + + * armos.c (ARMul_OSHandleSWI: AngelSWI_Reason_ReportException): + Set Reg[0] based on reason for for the exception. + +Thu Jun 4 15:22:03 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * armos.c (SWIwrite0): New function. + (WriteCommandLineTo): New function. + (SWIopen): New function. + (SWIread): New function. + (SWIwrite): New function. + (SWIflen): New function. + (ARMul_OSHandleSWI): Call new functions instead of handling + these here. + (ARMul_OSHandleSWI): Handle Angel SWIs correctly. + (*): Reformat spacing to be a bit more GNUly. + Most code taken from a patch by Anthony Thompson + (athompso@cambridge.arm.com) + +Tue Jun 2 15:22:22 1998 Nick Clifton + + * armos.h: Add Angel SWI and its reason codes. + * armos.c (ARMul_OSHandleSWI): Ignore Angel SWIs (for now). + +Mon Jun 1 17:14:19 1998 Anthony Thompson (athompso@cambridge.arm.com) + + * armos.c (ARMul_OSHandleSWI::SWI_Open): Handle special case + of ":tt" to catch stdin in addition to stdout. + (ARMul_OSHandleSWI::SWI_Seek): Return 0 or 1 to indicate failure + or success of lseek(). + +Wed May 20 17:36:25 1998 Nick Clifton + + * armos.c (ARMul_OSHandleSWI): Special case code to catch attempts + to open stdout. + +Wed Apr 29 15:29:55 1998 Jeff Johnston + + * armos.c (ARMul_OSHandleSWI): Added code for SWI_Clock, + SWI_Flen, and SWI_Time. Also fixed SWI_Seek code to only + seek from offset 0 and not to use R2 for whence since it is + not passed as part of the SWI call. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:20:26 1998 Tom Tromey + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:20:19 1998 Tom Tromey + + * configure.in: Don't call sinclude. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Mar 10 09:26:38 1998 Nick Clifton + + * armopts.h: Remove definition of LITTLEND - it is not used. + +Tue Feb 17 12:35:54 1998 Andrew Cagney + + * wrapper.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Dec 9 11:30:48 1997 Nick Clifton + + * Makefile.in: Updated with changes from branch. + * armdefs.h: ditto + * armemu.c: ditto these changes + * armemu.h: ditto add support for + * armos.c: ditto the Thumb instruction + * armsupp.c: ditto set and the new v4 + * armvirt.c: ditto architecture. + * wrapper.c: ditto + * thumbemu.c: New file from branch. + + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Oct 30 13:54:06 1997 Nick Clifton + + * armos.c (ARMul_OSHandleSWI): Add support for GetEnv SWI. Patch + from Tony Thompson at ARM: athompso@arm.com + + * wrapper.c (sim_create_inferior): Add code to create an execution + environment. Patch from Tony Thompson at ARM: athompso@arm.com + +Wed Oct 22 14:43:00 1997 Andrew Cagney + + * wrapper.c (sim_load): Pass lma_p and sim_write args to + sim_load_file. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Sep 4 17:21:23 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Aug 26 10:37:27 1997 Andrew Cagney + + * wrapper.c (sim_kill): Delete. + (sim_create_inferior): Add ABFD argument. + (sim_load): Move setting of PC from here. + (sim_create_inferior): To here. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 15:35:45 1997 Andrew Cagney + + * wrapper.c (sim_open): Add ABFD argument. + +Tue May 20 10:13:26 1997 Andrew Cagney + + * wrapper.c (sim_open): Add callback argument. + (sim_set_callbacks): Drop SIM_DESC argument. + +Thu Apr 24 00:39:51 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 18 13:32:23 1997 Andrew Cagney + + * wrapper.c (sim_stop): Stub sim_stop function. + +Thu Apr 17 18:33:01 1997 Fred Fish + + * arminit.c (ARMul_NewState): Preinitialize the state to + all zero/NULL. + +Thu Apr 17 02:39:02 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Add sim-load.o. + * wrapper.c (sim_kind,myname): New static locals. + (sim_open): Set sim_kind, myname. + (sim_load): Call sim_load_file to do work. Set start address from bfd. + (sim_create_inferior): Return SIM_RC. Delete start_address arg. + +Thu Apr 17 11:48:25 1997 Andrew Cagney + + * wrapper.c (sim_trace): Update so that it matches prototype. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Apr 7 12:01:17 1997 Andrew Cagney + + * Makefile.in (armemu32.o): Replace $< with autoconf recommended + $(srcdir)/.... + (armemu26.o): Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * wrapper.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:50:44 1997 Ian Lance Taylor + + * COPYING: Update FSF address. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 19 01:14:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Fri Mar 14 10:34:11 1997 Michael Meissner + + * configure: Regenerate to track ../common/aclocal.m4 changes. + +Thu Mar 13 12:38:56 1997 Doug Evans + + * wrapper.c (sim_open): Has result now. + (sim_*): New SIM_DESC argument. + +Tue Feb 4 13:22:21 1997 Doug Evans + + * Makefile.in (@COMMON_MAKEFILE_FRAG@): Use + COMMON_{PRE,POST}_CONFIG_FRAG instead. + * configure.in: sinclude ../common/aclocal.m4. + * configure: Regenerated. + +Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in Makefile.in: Update to new configure + scheme which is more compatible with WinGDB builds. + * configure.in: Improve comment on how to run autoconf. + * configure: Re-run autoconf to get new ../common/aclocal.m4. + * Makefile.in: Use autoconf substitution to install common + makefile fragment. + +Wed Nov 20 01:05:10 1996 Doug Evans + + * run.c: Deleted, use one in ../common now. + * Makefile.in: Delete everything that's been moved to + ../common/Make-common.in. + (SIM_OBJS): Define. + * configure.in: Simplify using macros in ../common/aclocal.m4. + * configure: Regenerated. + * config.in: New file. + * armos.c: #include config.h. + * wrapper.c (mem_size): Value is in bytes now. + (sim_callback): New global. + (arm_sim_set_profile{,_size}): Delete. + (arm_sim_set_mem_size): Rename to sim_size. + (sim_do_command): Call printf_filtered via callback. + (sim_set_callbacks): Record callback. + +Thu Oct 3 16:10:27 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (mostlyclean): Remove config.log. + +Wed Jun 26 12:17:24 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, + INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. + (docdir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + (AC_PROG_INSTALL): Added. + * configure: Rebuilt. + +Wed Feb 21 12:14:31 1996 Ian Lance Taylor + + * configure: Regenerate with autoconf 2.7. + +Fri Dec 15 16:27:30 1995 Ian Lance Taylor + + * run.c (main): Use new bfd_big_endian macro. + +Mon Nov 20 17:40:38 1995 Doug Evans + + * run.c: Include "getopt.h". + (verbose): Delete. + (usage): Make static. + (main): Call arm_sim_set_verbosity. + Only load sections marked SEC_LOAD. + * wrapper.c (mem_size, verbosity): New static global. + (arm_sim_set_mem_size): Renamed from sim_size. Callers updated. + (arm_sim_set_profile{,_size}): Renamed from sim_foo. Callers updated. + +Fri Nov 17 19:35:11 1995 Doug Evans + + * armdefs.h (ARMul_State): New member `verbose'. + * armrdi.c (ARMul_ConsolePrint): Add missing va_end. + * run.c (verbose): Make global. + * wrapper.c (init): Set state->verbose. + (ARMul_ConsolePrint): Don't print anything if !verbose. + +Fri Oct 13 15:30:30 1995 Doug Evans + + * armos.c: #include dbg_rdi.h. + (ARMul_OSHandleSWI): Handle SWI_Breakpoint. + * armos.h (SWI_Breakpoint): Define. + * wrapper.c: #include armemu.h, dbg_rdi.h. + (rc): Delete. + (sim_resume): Use state->EndCondition to record stop state. + Call FLUSHPIPE before returning. + (sim_stop_reason): Determine reason from state->EndCondition. + +Fri Oct 13 15:04:05 1995 steve chamberlain + + * wrapper.c (sim_set_callbacks): New. + +Thu Sep 28 19:45:56 1995 Doug Evans + + * armos.c (ARMul_OSHandleSWI): Result of read/write calls is + number of bytes not read/written (or -1). + +Wed Sep 20 13:35:54 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Fri Sep 8 14:27:20 1995 Ian Lance Taylor + + * configure.in: Remove AC_PROG_INSTALL. + * configure: Rebuild. + * Makefile.in (INSTALL): Revert to using install.sh. + (INSTALL_PROGRAM, INSTALL_DATA): Set to $(INSTALL). + (INSTALL_XFORM, INSTALL_XFORM1): Restore. + (mostlyclean): Make the same as clean, not distclean. + (clean): Remove config.log. + (install): Don't install in $(tooldir). + +Thu Sep 7 12:00:17 1995 Doug Evans + + (Try to) Update to new bfd autoconf scheme. + * run.c: Don't include sysdep.h. + * Makefile.in (INSTALL{,_PROGRAM,_DATA}): Use autoconf computed value. + (CC, CFLAGS, AR, RANLIB): Likewise. + (HDEFINES, TDEFINES): Define. + (CC_FOR_BUILD): Delete. + (host_makefile_frag): Delete. + (Makefile): Don't depend on frags. + * configure.in (sysdep.h): Don't create symlink. + (host_makefile_frag, frags): Deleted. + (CC, CFLAGS, AR, RANLIB, INSTALL): Compute values. + * configure: Regenerated. + +Thu Aug 3 10:45:37 1995 Fred Fish + + * Update all FSF addresses except those in COPYING* files. + +Wed Jul 5 16:15:54 1995 J.T. Conklin + + * Makefile.in (clean): Remove run, libsim.a. + + * Makefile.in, configure.in: converted to autoconf. + * configure: New file, generated with autconf 2.4. + + * arm.mt: Removed. + +Fri Jun 30 16:49:47 1995 Stan Shebs + + * wrapper.c (sim_do_command): New function. + +Tue Jun 13 10:57:32 1995 Steve Chamberlain + + * armos.c (ARMul_OSHandleSWI): New version to work with + newlib simply. + +Thu Jun 8 14:37:14 1995 Steve Chamberlain + + * run.c (main): Grab return value from right register. + +Wed May 24 14:37:31 1995 Steve Chamberlain + + * New. + + diff --git a/external/gpl3/gdb/dist/sim/arm/Makefile.in b/external/gpl3/gdb/dist/sim/arm/Makefile.in new file mode 100644 index 000000000000..579cf203d222 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/Makefile.in @@ -0,0 +1,58 @@ +# Makefile template for Configure for the arm sim library. +# Copyright 1995, 1996, 1997, 2002, 2007, 2008, 2009, 2010, 2011 +# Free Software Foundation, Inc. +# Written by Cygnus Support. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +## COMMON_PRE_CONFIG_FRAG + +SIM_EXTRA_CFLAGS = -DMODET -DNEED_UI_LOOP_HOOK -DSIM_TARGET_SWITCHES + +COPRO=@COPRO@ + +SIM_OBJS = armemu26.o armemu32.o arminit.o armos.o armsupp.o \ + armvirt.o bag.o thumbemu.o wrapper.o sim-load.o $(COPRO) + +## COMMON_POST_CONFIG_FRAG + + +armos.o: armos.c armdefs.h armos.h armfpe.h targ-vals.h + +armcopro.o: armcopro.c armdefs.h +maverick.o: maverick.c armdefs.h +iwmmxt.o: iwmmxt.c iwmmxt.h armdefs.h + +armemu26.o: armemu.c armdefs.h armemu.h + $(CC) -c $(srcdir)/armemu.c -o armemu26.o $(ALL_CFLAGS) + +armemu32.o: armemu.c armdefs.h armemu.h + $(CC) -c $(srcdir)/armemu.c -o armemu32.o -DMODE32 $(ALL_CFLAGS) + +arminit.o: arminit.c armdefs.h armemu.h + +armrdi.o: armrdi.c armdefs.h armemu.h armos.h dbg_cp.h dbg_conf.h dbg_rdi.h \ + dbg_hif.h communicate.h + +armsupp.o: armsupp.c armdefs.h armemu.h + +thumbemu.o: thumbemu.c armdefs.h armemu.h + +bag.o: bag.c bag.h + +wrapper.o: armdefs.h armemu.h dbg_rdi.h \ + $(srcdir)/../common/run-sim.h \ + $(srcdir)/../common/sim-utils.h \ + $(srcdir)/../../include/gdb/sim-arm.h \ + $(srcdir)/../../include/gdb/remote-sim.h diff --git a/external/gpl3/gdb/dist/sim/arm/README b/external/gpl3/gdb/dist/sim/arm/README new file mode 100644 index 000000000000..adfb766451d4 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/README @@ -0,0 +1,27 @@ + +This directory contains the standard release of the ARMulator from +Advanced RISC Machines, and was ftp'd from. + +ftp.cl.cam.ac.uk:/arm/gnu + +It likes to use TCP/IP between the simulator and the host, which is +nice, but is a pain to use under anything non-unix. + +I've added created a new Makefile.in (the original in Makefile.orig) +to build a version of the simulator without the TCP/IP stuff, and a +wrapper.c to link directly into gdb and the run command. + +It should be possible (barring major changes in the layout of +the armulator) to upgrade the simulator by copying all the files +out of a release into this directory and renaming the Makefile. + +(Except that I changed armos.c to work more simply with our +simulator rigs) + +Steve + +sac@cygnus.com + +Mon May 15 12:03:28 PDT 1995 + + diff --git a/external/gpl3/gdb/dist/sim/arm/armcopro.c b/external/gpl3/gdb/dist/sim/arm/armcopro.c new file mode 100644 index 000000000000..29303c00b78c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armcopro.c @@ -0,0 +1,1449 @@ +/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator. + Copyright (C) 1994, 2000 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "armdefs.h" +#include "armos.h" +#include "armemu.h" +#include "ansidecl.h" +#include "iwmmxt.h" + +/* Dummy Co-processors. */ + +static unsigned +NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned a ATTRIBUTE_UNUSED, + ARMword b ATTRIBUTE_UNUSED) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned a ATTRIBUTE_UNUSED, + ARMword b ATTRIBUTE_UNUSED, + ARMword c ATTRIBUTE_UNUSED) +{ + return ARMul_CANT; +} + +static unsigned +NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned a ATTRIBUTE_UNUSED, + ARMword b ATTRIBUTE_UNUSED, + ARMword * c ATTRIBUTE_UNUSED) +{ + return ARMul_CANT; +} + +/* The XScale Co-processors. */ + +/* Coprocessor 15: System Control. */ +static void write_cp14_reg (unsigned, ARMword); +static ARMword read_cp14_reg (unsigned); + +/* There are two sets of registers for copro 15. + One set is available when opcode_2 is 0 and + the other set when opcode_2 >= 1. */ +static ARMword XScale_cp15_opcode_2_is_0_Regs[16]; +static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16]; +/* There are also a set of breakpoint registers + which are accessed via CRm instead of opcode_2. */ +static ARMword XScale_cp15_DBR1; +static ARMword XScale_cp15_DBCON; +static ARMword XScale_cp15_IBCR0; +static ARMword XScale_cp15_IBCR1; + +static unsigned +XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED) +{ + int i; + + for (i = 16; i--;) + { + XScale_cp15_opcode_2_is_0_Regs[i] = 0; + XScale_cp15_opcode_2_is_not_0_Regs[i] = 0; + } + + /* Initialise the processor ID. */ + XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000; + + /* Initialise the cache type. */ + XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA; + + /* Initialise the ARM Control Register. */ + XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078; +} + +/* Check an access to a register. */ + +static unsigned +check_cp15_access (ARMul_State * state, + unsigned reg, + unsigned CRm, + unsigned opcode_1, + unsigned opcode_2) +{ + /* Do not allow access to these register in USER mode. */ + if (state->Mode == USER26MODE || state->Mode == USER32MODE) + return ARMul_CANT; + + /* Opcode_1should be zero. */ + if (opcode_1 != 0) + return ARMul_CANT; + + /* Different register have different access requirements. */ + switch (reg) + { + case 0: + case 1: + /* CRm must be 0. Opcode_2 can be anything. */ + if (CRm != 0) + return ARMul_CANT; + break; + case 2: + case 3: + /* CRm must be 0. Opcode_2 must be zero. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 4: + /* Access not allowed. */ + return ARMul_CANT; + case 5: + case 6: + /* Opcode_2 must be zero. CRm must be 0. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 7: + /* Permissable combinations: + Opcode_2 CRm + 0 5 + 0 6 + 0 7 + 1 5 + 1 6 + 1 10 + 4 10 + 5 2 + 6 5 */ + switch (opcode_2) + { + default: return ARMul_CANT; + case 6: if (CRm != 5) return ARMul_CANT; break; + case 5: if (CRm != 2) return ARMul_CANT; break; + case 4: if (CRm != 10) return ARMul_CANT; break; + case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break; + case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break; + } + break; + + case 8: + /* Permissable combinations: + Opcode_2 CRm + 0 5 + 0 6 + 0 7 + 1 5 + 1 6 */ + if (opcode_2 > 1) + return ARMul_CANT; + if ((CRm < 5) || (CRm > 7)) + return ARMul_CANT; + if (opcode_2 == 1 && CRm == 7) + return ARMul_CANT; + break; + case 9: + /* Opcode_2 must be zero or one. CRm must be 1 or 2. */ + if ( ((CRm != 0) && (CRm != 1)) + || ((opcode_2 != 1) && (opcode_2 != 2))) + return ARMul_CANT; + break; + case 10: + /* Opcode_2 must be zero or one. CRm must be 4 or 8. */ + if ( ((CRm != 0) && (CRm != 1)) + || ((opcode_2 != 4) && (opcode_2 != 8))) + return ARMul_CANT; + break; + case 11: + /* Access not allowed. */ + return ARMul_CANT; + case 12: + /* Access not allowed. */ + return ARMul_CANT; + case 13: + /* Opcode_2 must be zero. CRm must be 0. */ + if ((CRm != 0) || (opcode_2 != 0)) + return ARMul_CANT; + break; + case 14: + /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */ + if (opcode_2 != 0) + return ARMul_CANT; + + if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9)) + return ARMul_CANT; + break; + case 15: + /* Opcode_2 must be zero. CRm must be 1. */ + if ((CRm != 1) || (opcode_2 != 0)) + return ARMul_CANT; + break; + default: + /* Should never happen. */ + return ARMul_CANT; + } + + return ARMul_DONE; +} + +/* Store a value into one of coprocessor 15's registers. */ + +static void +write_cp15_reg (ARMul_State * state, + unsigned reg, + unsigned opcode_2, + unsigned CRm, + ARMword value) +{ + if (opcode_2) + { + switch (reg) + { + case 0: /* Cache Type. */ + /* Writes are not allowed. */ + return; + + case 1: /* Auxillary Control. */ + /* Only BITS (5, 4) and BITS (1, 0) can be written. */ + value &= 0x33; + break; + + default: + return; + } + + XScale_cp15_opcode_2_is_not_0_Regs [reg] = value; + } + else + { + switch (reg) + { + case 0: /* ID. */ + /* Writes are not allowed. */ + return; + + case 1: /* ARM Control. */ + /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written. + BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */ + value &= 0x00003b87; + value |= 0x00000078; + + /* Change the endianness if necessary. */ + if ((value & ARMul_CP15_R1_ENDIAN) != + (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN)) + { + state->bigendSig = value & ARMul_CP15_R1_ENDIAN; + /* Force ARMulator to notice these now. */ + state->Emulate = CHANGEMODE; + } + break; + + case 2: /* Translation Table Base. */ + /* Only BITS (31, 14) can be written. */ + value &= 0xffffc000; + break; + + case 3: /* Domain Access Control. */ + /* All bits writable. */ + break; + + case 5: /* Fault Status Register. */ + /* BITS (10, 9) and BITS (7, 0) can be written. */ + value &= 0x000006ff; + break; + + case 6: /* Fault Address Register. */ + /* All bits writable. */ + break; + + case 7: /* Cache Functions. */ + case 8: /* TLB Operations. */ + case 10: /* TLB Lock Down. */ + /* Ignore writes. */ + return; + + case 9: /* Data Cache Lock. */ + /* Only BIT (0) can be written. */ + value &= 0x1; + break; + + case 13: /* Process ID. */ + /* Only BITS (31, 25) are writable. */ + value &= 0xfe000000; + break; + + case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */ + /* All bits can be written. Which register is accessed is + dependent upon CRm. */ + switch (CRm) + { + case 0: /* DBR0 */ + break; + case 3: /* DBR1 */ + XScale_cp15_DBR1 = value; + break; + case 4: /* DBCON */ + XScale_cp15_DBCON = value; + break; + case 8: /* IBCR0 */ + XScale_cp15_IBCR0 = value; + break; + case 9: /* IBCR1 */ + XScale_cp15_IBCR1 = value; + break; + default: + return; + } + break; + + case 15: /* Coprpcessor Access Register. */ + /* Access is only valid if CRm == 1. */ + if (CRm != 1) + return; + + /* Only BITS (13, 0) may be written. */ + value &= 0x00003fff; + break; + + default: + return; + } + + XScale_cp15_opcode_2_is_0_Regs [reg] = value; + } + + return; +} + +/* Return the value in a cp15 register. */ + +ARMword +read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm) +{ + if (opcode_2 == 0) + { + if (reg == 15 && CRm != 1) + return 0; + + if (reg == 14) + { + switch (CRm) + { + case 3: return XScale_cp15_DBR1; + case 4: return XScale_cp15_DBCON; + case 8: return XScale_cp15_IBCR0; + case 9: return XScale_cp15_IBCR1; + default: + break; + } + } + + return XScale_cp15_opcode_2_is_0_Regs [reg]; + } + else + return XScale_cp15_opcode_2_is_not_0_Regs [reg]; + + return 0; +} + +static unsigned +XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp15_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + write_cp15_reg (state, reg, 0, 0, data); + + return result; +} + +static unsigned +XScale_cp15_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp15_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + * data = read_cp15_reg (reg, 0, 0); + + return result; +} + +static unsigned +XScale_cp15_MRC (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + unsigned opcode_2 = BITS (5, 7); + unsigned CRm = BITS (0, 3); + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2); + + if (result == ARMul_DONE) + * value = read_cp15_reg (reg, opcode_2, CRm); + + return result; +} + +static unsigned +XScale_cp15_MCR (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + unsigned opcode_2 = BITS (5, 7); + unsigned CRm = BITS (0, 3); + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2); + + if (result == ARMul_DONE) + write_cp15_reg (state, reg, opcode_2, CRm, value); + + return result; +} + +static unsigned +XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword * value) +{ + /* FIXME: Not sure what to do about the alternative register set + here. For now default to just accessing CRm == 0 registers. */ + * value = read_cp15_reg (reg, 0, 0); + + return TRUE; +} + +static unsigned +XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword value) +{ + /* FIXME: Not sure what to do about the alternative register set + here. For now default to just accessing CRm == 0 registers. */ + write_cp15_reg (state, reg, 0, 0, value); + + return TRUE; +} + +/* Check for special XScale memory access features. */ + +void +XScale_check_memacc (ARMul_State * state, ARMword * address, int store) +{ + ARMword dbcon, r0, r1; + int e1, e0; + + if (!state->is_XScale) + return; + + /* Check for PID-ification. + XXX BTB access support will require this test failing. */ + r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000); + if (r0 && (* address & 0xfe000000) == 0) + * address |= r0; + + /* Check alignment fault enable/disable. */ + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3)) + { + /* Set the FSR and FAR. + Do not use XScale_set_fsr_far as this checks the DCSR register. */ + write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT); + write_cp15_reg (state, 6, 0, 0, * address); + + ARMul_Abort (state, ARMul_DataAbortV); + } + + if (XScale_debug_moe (state, -1)) + return; + + /* Check the data breakpoint registers. */ + dbcon = read_cp15_reg (14, 0, 4); + r0 = read_cp15_reg (14, 0, 0); + r1 = read_cp15_reg (14, 0, 3); + e0 = dbcon & ARMul_CP15_DBCON_E0; + + if (dbcon & ARMul_CP15_DBCON_M) + { + /* r1 is a inverse mask. */ + if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) + && ((* address & ~r1) == (r0 & ~r1))) + { + XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); + ARMul_OSHandleSWI (state, SWI_Breakpoint); + } + } + else + { + if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1)) + && ((* address & ~3) == (r0 & ~3))) + { + XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); + ARMul_OSHandleSWI (state, SWI_Breakpoint); + } + + e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2; + if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1)) + && ((* address & ~3) == (r1 & ~3))) + { + XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB); + ARMul_OSHandleSWI (state, SWI_Breakpoint); + } + } +} + +/* Set the XScale FSR and FAR registers. */ + +void +XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far) +{ + if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0) + return; + + write_cp15_reg (state, 5, 0, 0, fsr); + write_cp15_reg (state, 6, 0, 0, far); +} + +/* Set the XScale debug `method of entry' if it is enabled. */ + +int +XScale_debug_moe (ARMul_State * state, int moe) +{ + ARMword value; + + if (!state->is_XScale) + return 1; + + value = read_cp14_reg (10); + if (value & (1UL << 31)) + { + if (moe != -1) + { + value &= ~0x1c; + value |= moe; + + write_cp14_reg (10, value); + } + return 1; + } + return 0; +} + +/* Coprocessor 13: Interrupt Controller and Bus Controller. */ + +/* There are two sets of registers for copro 13. + One set (of three registers) is available when CRm is 0 + and the other set (of six registers) when CRm is 1. */ + +static ARMword XScale_cp13_CR0_Regs[16]; +static ARMword XScale_cp13_CR1_Regs[16]; + +static unsigned +XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED) +{ + int i; + + for (i = 16; i--;) + { + XScale_cp13_CR0_Regs[i] = 0; + XScale_cp13_CR1_Regs[i] = 0; + } +} + +/* Check an access to a register. */ + +static unsigned +check_cp13_access (ARMul_State * state, + unsigned reg, + unsigned CRm, + unsigned opcode_1, + unsigned opcode_2) +{ + /* Do not allow access to these registers in USER mode. */ + if (state->Mode == USER26MODE || state->Mode == USER32MODE) + return ARMul_CANT; + + /* The opcodes should be zero. */ + if ((opcode_1 != 0) || (opcode_2 != 0)) + return ARMul_CANT; + + /* Do not allow access to these register if bit + 13 of coprocessor 15's register 15 is zero. */ + if (! CP_ACCESS_ALLOWED (state, 13)) + return ARMul_CANT; + + /* Registers 0, 4 and 8 are defined when CRm == 0. + Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1. + For all other CRm values undefined behaviour results. */ + if (CRm == 0) + { + if (reg == 0 || reg == 4 || reg == 8) + return ARMul_DONE; + } + else if (CRm == 1) + { + if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8)) + return ARMul_DONE; + } + + return ARMul_CANT; +} + +/* Store a value into one of coprocessor 13's registers. */ + +static void +write_cp13_reg (unsigned reg, unsigned CRm, ARMword value) +{ + switch (CRm) + { + case 0: + switch (reg) + { + case 0: /* INTCTL */ + /* Only BITS (3:0) can be written. */ + value &= 0xf; + break; + + case 4: /* INTSRC */ + /* No bits may be written. */ + return; + + case 8: /* INTSTR */ + /* Only BITS (1:0) can be written. */ + value &= 0x3; + break; + + default: + /* Should not happen. Ignore any writes to unimplemented registers. */ + return; + } + + XScale_cp13_CR0_Regs [reg] = value; + break; + + case 1: + switch (reg) + { + case 0: /* BCUCTL */ + /* Only BITS (30:28) and BITS (3:0) can be written. + BIT(31) is write ignored. */ + value &= 0x7000000f; + value |= XScale_cp13_CR1_Regs[0] & (1UL << 31); + break; + + case 1: /* BCUMOD */ + /* Only bit 0 is accecssible. */ + value &= 1; + value |= XScale_cp13_CR1_Regs[1] & ~ 1; + break; + + case 4: /* ELOG0 */ + case 5: /* ELOG1 */ + case 6: /* ECAR0 */ + case 7: /* ECAR1 */ + /* No bits can be written. */ + return; + + case 8: /* ECTST */ + /* Only BITS (7:0) can be written. */ + value &= 0xff; + break; + + default: + /* Should not happen. Ignore any writes to unimplemented registers. */ + return; + } + + XScale_cp13_CR1_Regs [reg] = value; + break; + + default: + /* Should not happen. */ + break; + } + + return; +} + +/* Return the value in a cp13 register. */ + +static ARMword +read_cp13_reg (unsigned reg, unsigned CRm) +{ + if (CRm == 0) + return XScale_cp13_CR0_Regs [reg]; + else if (CRm == 1) + return XScale_cp13_CR1_Regs [reg]; + + return 0; +} + +static unsigned +XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp13_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + write_cp13_reg (reg, 0, data); + + return result; +} + +static unsigned +XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp13_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + * data = read_cp13_reg (reg, 0); + + return result; +} + +static unsigned +XScale_cp13_MRC (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + unsigned CRm = BITS (0, 3); + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7)); + + if (result == ARMul_DONE) + * value = read_cp13_reg (reg, CRm); + + return result; +} + +static unsigned +XScale_cp13_MCR (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + unsigned CRm = BITS (0, 3); + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7)); + + if (result == ARMul_DONE) + write_cp13_reg (reg, CRm, value); + + return result; +} + +static unsigned +XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword * value) +{ + /* FIXME: Not sure what to do about the alternative register set + here. For now default to just accessing CRm == 0 registers. */ + * value = read_cp13_reg (reg, 0); + + return TRUE; +} + +static unsigned +XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword value) +{ + /* FIXME: Not sure what to do about the alternative register set + here. For now default to just accessing CRm == 0 registers. */ + write_cp13_reg (reg, 0, value); + + return TRUE; +} + +/* Coprocessor 14: Performance Monitoring, Clock and Power management, + Software Debug. */ + +static ARMword XScale_cp14_Regs[16]; + +static unsigned +XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED) +{ + int i; + + for (i = 16; i--;) + XScale_cp14_Regs[i] = 0; +} + +/* Check an access to a register. */ + +static unsigned +check_cp14_access (ARMul_State * state, + unsigned reg, + unsigned CRm, + unsigned opcode1, + unsigned opcode2) +{ + /* Not allowed to access these register in USER mode. */ + if (state->Mode == USER26MODE || state->Mode == USER32MODE) + return ARMul_CANT; + + /* CRm should be zero. */ + if (CRm != 0) + return ARMul_CANT; + + /* OPcodes should be zero. */ + if (opcode1 != 0 || opcode2 != 0) + return ARMul_CANT; + + /* Accessing registers 4 or 5 has unpredicatable results. */ + if (reg >= 4 && reg <= 5) + return ARMul_CANT; + + return ARMul_DONE; +} + +/* Store a value into one of coprocessor 14's registers. */ + +static void +write_cp14_reg (unsigned reg, ARMword value) +{ + switch (reg) + { + case 0: /* PMNC */ + /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */ + value &= 0x0ffff77f; + + /* Reset the clock counter if necessary. */ + if (value & ARMul_CP14_R0_CLKRST) + XScale_cp14_Regs [1] = 0; + break; + + case 4: + case 5: + /* We should not normally reach this code. The debugger interface + can bypass the normal checks though, so it could happen. */ + value = 0; + break; + + case 6: /* CCLKCFG */ + /* Only BITS (3:0) can be written. */ + value &= 0xf; + break; + + case 7: /* PWRMODE */ + /* Although BITS (1:0) can be written with non-zero values, this would + have the side effect of putting the processor to sleep. Thus in + order for the register to be read again, it would have to go into + ACTIVE mode, which means that any read will see these bits as zero. + + Rather than trying to implement complex reset-to-zero-upon-read logic + we just override the write value with zero. */ + value = 0; + break; + + case 10: /* DCSR */ + /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can + be written. */ + value &= 0xc0df003f; + break; + + case 11: /* TBREG */ + /* No writes are permitted. */ + value = 0; + break; + + case 14: /* TXRXCTRL */ + /* Only BITS (31:30) can be written. */ + value &= 0xc0000000; + break; + + default: + /* All bits can be written. */ + break; + } + + XScale_cp14_Regs [reg] = value; +} + +/* Return the value in a cp14 register. Not a static function since + it is used by the code to emulate the BKPT instruction in armemu.c. */ + +ARMword +read_cp14_reg (unsigned reg) +{ + return XScale_cp14_Regs [reg]; +} + +static unsigned +XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp14_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + write_cp14_reg (reg, data); + + return result; +} + +static unsigned +XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data) +{ + unsigned reg = BITS (12, 15); + unsigned result; + + result = check_cp14_access (state, reg, 0, 0, 0); + + if (result == ARMul_DONE && type == ARMul_DATA) + * data = read_cp14_reg (reg); + + return result; +} + +static unsigned +XScale_cp14_MRC +( + ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value +) +{ + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7)); + + if (result == ARMul_DONE) + * value = read_cp14_reg (reg); + + return result; +} + +static unsigned +XScale_cp14_MCR +( + ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value +) +{ + unsigned reg = BITS (16, 19); + unsigned result; + + result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7)); + + if (result == ARMul_DONE) + write_cp14_reg (reg, value); + + return result; +} + +static unsigned +XScale_cp14_read_reg +( + ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword * value +) +{ + * value = read_cp14_reg (reg); + + return TRUE; +} + +static unsigned +XScale_cp14_write_reg +( + ARMul_State * state ATTRIBUTE_UNUSED, + unsigned reg, + ARMword value +) +{ + write_cp14_reg (reg, value); + + return TRUE; +} + +/* Here's ARMulator's MMU definition. A few things to note: + 1) It has eight registers, but only two are defined. + 2) You can only access its registers with MCR and MRC. + 3) MMU Register 0 (ID) returns 0x41440110 + 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4 + controls 32/26 bit program space, bit 5 controls 32/26 bit data space, + bit 6 controls late abort timimg and bit 7 controls big/little endian. */ + +static ARMword MMUReg[8]; + +static unsigned +MMUInit (ARMul_State * state) +{ + MMUReg[1] = state->prog32Sig << 4 | + state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7; + + ARMul_ConsolePrint (state, ", MMU present"); + + return TRUE; +} + +static unsigned +MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + int reg = BITS (16, 19) & 7; + + if (reg == 0) + *value = 0x41440110; + else + *value = MMUReg[reg]; + + return ARMul_DONE; +} + +static unsigned +MMUMCR (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + int reg = BITS (16, 19) & 7; + + MMUReg[reg] = value; + + if (reg == 1) + { + ARMword p,d,l,b; + + p = state->prog32Sig; + d = state->data32Sig; + l = state->lateabtSig; + b = state->bigendSig; + + state->prog32Sig = value >> 4 & 1; + state->data32Sig = value >> 5 & 1; + state->lateabtSig = value >> 6 & 1; + state->bigendSig = value >> 7 & 1; + + if ( p != state->prog32Sig + || d != state->data32Sig + || l != state->lateabtSig + || b != state->bigendSig) + /* Force ARMulator to notice these now. */ + state->Emulate = CHANGEMODE; + } + + return ARMul_DONE; +} + +static unsigned +MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value) +{ + if (reg == 0) + *value = 0x41440110; + else if (reg < 8) + *value = MMUReg[reg]; + + return TRUE; +} + +static unsigned +MMUWrite (ARMul_State * state, unsigned reg, ARMword value) +{ + if (reg < 8) + MMUReg[reg] = value; + + if (reg == 1) + { + ARMword p,d,l,b; + + p = state->prog32Sig; + d = state->data32Sig; + l = state->lateabtSig; + b = state->bigendSig; + + state->prog32Sig = value >> 4 & 1; + state->data32Sig = value >> 5 & 1; + state->lateabtSig = value >> 6 & 1; + state->bigendSig = value >> 7 & 1; + + if ( p != state->prog32Sig + || d != state->data32Sig + || l != state->lateabtSig + || b != state->bigendSig) + /* Force ARMulator to notice these now. */ + state->Emulate = CHANGEMODE; + } + + return TRUE; +} + + +/* What follows is the Validation Suite Coprocessor. It uses two + co-processor numbers (4 and 5) and has the follwing functionality. + Sixteen registers. Both co-processor nuimbers can be used in an MCR + and MRC to access these registers. CP 4 can LDC and STC to and from + the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of + cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a + number of cycles (specified in a CP register), CDP 2 issues an IRQW + in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 + stores a 32 bit time value in a CP register (actually it's the total + number of N, S, I, C and F cyles). */ + +static ARMword ValReg[16]; + +static unsigned +ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword data) +{ + static unsigned words; + + if (type != ARMul_DATA) + words = 0; + else + { + ValReg[BITS (12, 15)] = data; + + if (BIT (22)) + /* It's a long access, get two words. */ + if (words++ != 4) + return ARMul_INC; + } + + return ARMul_DONE; +} + +static unsigned +ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword * data) +{ + static unsigned words; + + if (type != ARMul_DATA) + words = 0; + else + { + * data = ValReg[BITS (12, 15)]; + + if (BIT (22)) + /* It's a long access, get two words. */ + if (words++ != 4) + return ARMul_INC; + } + + return ARMul_DONE; +} + +static unsigned +ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + *value = ValReg[BITS (16, 19)]; + + return ARMul_DONE; +} + +static unsigned +ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + ValReg[BITS (16, 19)] = value; + + return ARMul_DONE; +} + +static unsigned +ValCDP (ARMul_State * state, unsigned type, ARMword instr) +{ + static unsigned long finish = 0; + + if (BITS (20, 23) != 0) + return ARMul_CANT; + + if (type == ARMul_FIRST) + { + ARMword howlong; + + howlong = ValReg[BITS (0, 3)]; + + /* First cycle of a busy wait. */ + finish = ARMul_Time (state) + howlong; + + return howlong == 0 ? ARMul_DONE : ARMul_BUSY; + } + else if (type == ARMul_BUSY) + { + if (ARMul_Time (state) >= finish) + return ARMul_DONE; + else + return ARMul_BUSY; + } + + return ARMul_CANT; +} + +static unsigned +DoAFIQ (ARMul_State * state) +{ + state->NfiqSig = LOW; + state->Exception++; + return 0; +} + +static unsigned +DoAIRQ (ARMul_State * state) +{ + state->NirqSig = LOW; + state->Exception++; + return 0; +} + +static unsigned +IntCDP (ARMul_State * state, unsigned type, ARMword instr) +{ + static unsigned long finish; + ARMword howlong; + + howlong = ValReg[BITS (0, 3)]; + + switch ((int) BITS (20, 23)) + { + case 0: + if (type == ARMul_FIRST) + { + /* First cycle of a busy wait. */ + finish = ARMul_Time (state) + howlong; + + return howlong == 0 ? ARMul_DONE : ARMul_BUSY; + } + else if (type == ARMul_BUSY) + { + if (ARMul_Time (state) >= finish) + return ARMul_DONE; + else + return ARMul_BUSY; + } + return ARMul_DONE; + + case 1: + if (howlong == 0) + ARMul_Abort (state, ARMul_FIQV); + else + ARMul_ScheduleEvent (state, howlong, DoAFIQ); + return ARMul_DONE; + + case 2: + if (howlong == 0) + ARMul_Abort (state, ARMul_IRQV); + else + ARMul_ScheduleEvent (state, howlong, DoAIRQ); + return ARMul_DONE; + + case 3: + state->NfiqSig = HIGH; + state->Exception--; + return ARMul_DONE; + + case 4: + state->NirqSig = HIGH; + state->Exception--; + return ARMul_DONE; + + case 5: + ValReg[BITS (0, 3)] = ARMul_Time (state); + return ARMul_DONE; + } + + return ARMul_CANT; +} + +/* Install co-processor instruction handlers in this routine. */ + +unsigned +ARMul_CoProInit (ARMul_State * state) +{ + unsigned int i; + + /* Initialise tham all first. */ + for (i = 0; i < 16; i++) + ARMul_CoProDetach (state, i); + + /* Install CoPro Instruction handlers here. + The format is: + ARMul_CoProAttach (state, CP Number, Init routine, Exit routine + LDC routine, STC routine, MRC routine, MCR routine, + CDP routine, Read Reg routine, Write Reg routine). */ + if (state->is_ep9312) + { + ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4, + DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL); + ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5, + DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL); + ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL, + DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL); + } + else + { + ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC, + ValMRC, ValMCR, ValCDP, NULL, NULL); + + ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL, + ValMRC, ValMCR, IntCDP, NULL, NULL); + } + + if (state->is_XScale) + { + ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL, + XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC, + XScale_cp13_MCR, NULL, XScale_cp13_read_reg, + XScale_cp13_write_reg); + + ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL, + XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC, + XScale_cp14_MCR, NULL, XScale_cp14_read_reg, + XScale_cp14_write_reg); + + ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL, + NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR, + NULL, XScale_cp15_read_reg, XScale_cp15_write_reg); + } + else + { + ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, + MMUMRC, MMUMCR, NULL, MMURead, MMUWrite); + } + + if (state->is_iWMMXt) + { + ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC, + NULL, NULL, IwmmxtCDP, NULL, NULL); + + ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL, + IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, NULL); + } + + /* No handlers below here. */ + + /* Call all the initialisation routines. */ + for (i = 0; i < 16; i++) + if (state->CPInit[i]) + (state->CPInit[i]) (state); + + return TRUE; +} + +/* Install co-processor finalisation routines in this routine. */ + +void +ARMul_CoProExit (ARMul_State * state) +{ + register unsigned i; + + for (i = 0; i < 16; i++) + if (state->CPExit[i]) + (state->CPExit[i]) (state); + + for (i = 0; i < 16; i++) /* Detach all handlers. */ + ARMul_CoProDetach (state, i); +} + +/* Routines to hook Co-processors into ARMulator. */ + +void +ARMul_CoProAttach (ARMul_State * state, + unsigned number, + ARMul_CPInits * init, + ARMul_CPExits * exit, + ARMul_LDCs * ldc, + ARMul_STCs * stc, + ARMul_MRCs * mrc, + ARMul_MCRs * mcr, + ARMul_CDPs * cdp, + ARMul_CPReads * read, + ARMul_CPWrites * write) +{ + if (init != NULL) + state->CPInit[number] = init; + if (exit != NULL) + state->CPExit[number] = exit; + if (ldc != NULL) + state->LDC[number] = ldc; + if (stc != NULL) + state->STC[number] = stc; + if (mrc != NULL) + state->MRC[number] = mrc; + if (mcr != NULL) + state->MCR[number] = mcr; + if (cdp != NULL) + state->CDP[number] = cdp; + if (read != NULL) + state->CPRead[number] = read; + if (write != NULL) + state->CPWrite[number] = write; +} + +void +ARMul_CoProDetach (ARMul_State * state, unsigned number) +{ + ARMul_CoProAttach (state, number, NULL, NULL, + NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, + NoCoPro3R, NULL, NULL); + + state->CPInit[number] = NULL; + state->CPExit[number] = NULL; + state->CPRead[number] = NULL; + state->CPWrite[number] = NULL; +} diff --git a/external/gpl3/gdb/dist/sim/arm/armdefs.h b/external/gpl3/gdb/dist/sim/arm/armdefs.h new file mode 100644 index 000000000000..2942023b7d84 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armdefs.h @@ -0,0 +1,433 @@ +/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "config.h" +#include +#include + +#define FALSE 0 +#define TRUE 1 +#define LOW 0 +#define HIGH 1 +#define LOWHIGH 1 +#define HIGHLOW 2 + +#ifndef __STDC__ +typedef char *VoidStar; +#endif + +#ifdef HAVE_STDINT_H +#include +typedef uint32_t ARMword; +typedef int32_t ARMsword; +typedef uint64_t ARMdword; +typedef int64_t ARMsdword; +#else +typedef unsigned int ARMword; /* must be 32 bits wide */ +typedef signed int ARMsword; +typedef unsigned long long ARMdword; /* Must be at least 64 bits wide. */ +typedef signed long long ARMsdword; +#endif +typedef struct ARMul_State ARMul_State; + +typedef unsigned ARMul_CPInits (ARMul_State * state); +typedef unsigned ARMul_CPExits (ARMul_State * state); +typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type, + ARMword instr, ARMword value); +typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type, + ARMword instr, ARMword * value); +typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type, + ARMword instr, ARMword * value); +typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type, + ARMword instr, ARMword value); +typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type, + ARMword instr); +typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg, + ARMword * value); +typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg, + ARMword value); + +struct ARMul_State +{ + ARMword Emulate; /* to start and stop emulation */ + unsigned EndCondition; /* reason for stopping */ + unsigned ErrorCode; /* type of illegal instruction */ + ARMword Reg[16]; /* the current register file */ + ARMword RegBank[7][16]; /* all the registers */ + /* 40 bit accumulator. We always keep this 64 bits wide, + and move only 40 bits out of it in an MRA insn. */ + ARMdword Accumulator; + ARMword Cpsr; /* the current psr */ + ARMword Spsr[7]; /* the exception psr's */ + ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ + ARMword SFlag; +#ifdef MODET + ARMword TFlag; /* Thumb state */ +#endif + ARMword Bank; /* the current register bank */ + ARMword Mode; /* the current mode */ + ARMword instr, pc, temp; /* saved register state */ + ARMword loaded, decoded; /* saved pipeline state */ + unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ + unsigned long NumInstrs; /* the number of instructions executed */ + unsigned NextInstr; + unsigned VectorCatch; /* caught exception mask */ + unsigned CallDebug; /* set to call the debugger */ + unsigned CanWatch; /* set by memory interface if its willing to suffer the + overhead of checking for watchpoints on each memory + access */ + unsigned MemReadDebug, MemWriteDebug; + unsigned long StopHandle; + + unsigned char *MemDataPtr; /* admin data */ + unsigned char *MemInPtr; /* the Data In bus */ + unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */ + unsigned char *MemSparePtr; /* extra space */ + ARMword MemSize; + + unsigned char *OSptr; /* OS Handle */ + char *CommandLine; /* Command Line from ARMsd */ + + ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ + ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ + ARMul_LDCs *LDC[16]; /* LDC instruction */ + ARMul_STCs *STC[16]; /* STC instruction */ + ARMul_MRCs *MRC[16]; /* MRC instruction */ + ARMul_MCRs *MCR[16]; /* MCR instruction */ + ARMul_CDPs *CDP[16]; /* CDP instruction */ + ARMul_CPReads *CPRead[16]; /* Read CP register */ + ARMul_CPWrites *CPWrite[16]; /* Write CP register */ + unsigned char *CPData[16]; /* Coprocessor data */ + unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ + unsigned long LastTime; /* Value of last call to ARMul_Time() */ + ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit + 3 set */ + + unsigned EventSet; /* the number of events in the queue */ + unsigned long Now; /* time to the nearest cycle */ + struct EventNode **EventPtr; /* the event list */ + + unsigned Exception; /* enable the next four values */ + unsigned Debug; /* show instructions as they are executed */ + unsigned NresetSig; /* reset the processor */ + unsigned NfiqSig; + unsigned NirqSig; + + unsigned abortSig; + unsigned NtransSig; + unsigned bigendSig; + unsigned prog32Sig; + unsigned data32Sig; + unsigned lateabtSig; + ARMword Vector; /* synthesize aborts in cycle modes */ + ARMword Aborted; /* sticky flag for aborts */ + ARMword Reseted; /* sticky flag for Reset */ + ARMword Inted, LastInted; /* sticky flags for interrupts */ + ARMword Base; /* extra hand for base writeback */ + ARMword AbortAddr; /* to keep track of Prefetch aborts */ + + const struct Dbg_HostosInterface *hostif; + + unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ + unsigned is_v5; /* Are we emulating a v5 architecture ? */ + unsigned is_v5e; /* Are we emulating a v5e architecture ? */ + unsigned is_v6; /* Are we emulating a v6 architecture ? */ + unsigned is_XScale; /* Are we emulating an XScale architecture ? */ + unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ + unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ + unsigned verbose; /* Print various messages like the banner */ +}; + +#define ResetPin NresetSig +#define FIQPin NfiqSig +#define IRQPin NirqSig +#define AbortPin abortSig +#define TransPin NtransSig +#define BigEndPin bigendSig +#define Prog32Pin prog32Sig +#define Data32Pin data32Sig +#define LateAbortPin lateabtSig + +/***************************************************************************\ +* Properties of ARM we know about * +\***************************************************************************/ + +/* The bitflags */ +#define ARM_Fix26_Prop 0x01 +#define ARM_Nexec_Prop 0x02 +#define ARM_Debug_Prop 0x10 +#define ARM_Isync_Prop ARM_Debug_Prop +#define ARM_Lock_Prop 0x20 +#define ARM_v4_Prop 0x40 +#define ARM_v5_Prop 0x80 +#define ARM_v5e_Prop 0x100 +#define ARM_XScale_Prop 0x200 +#define ARM_ep9312_Prop 0x400 +#define ARM_iWMMXt_Prop 0x800 +#define ARM_v6_Prop 0x1000 + +/***************************************************************************\ +* Macros to extract instruction fields * +\***************************************************************************/ + +#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ +#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ +#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ + +/***************************************************************************\ +* The hardware vector addresses * +\***************************************************************************/ + +#define ARMResetV 0L +#define ARMUndefinedInstrV 4L +#define ARMSWIV 8L +#define ARMPrefetchAbortV 12L +#define ARMDataAbortV 16L +#define ARMAddrExceptnV 20L +#define ARMIRQV 24L +#define ARMFIQV 28L +#define ARMErrorV 32L /* This is an offset, not an address ! */ + +#define ARMul_ResetV ARMResetV +#define ARMul_UndefinedInstrV ARMUndefinedInstrV +#define ARMul_SWIV ARMSWIV +#define ARMul_PrefetchAbortV ARMPrefetchAbortV +#define ARMul_DataAbortV ARMDataAbortV +#define ARMul_AddrExceptnV ARMAddrExceptnV +#define ARMul_IRQV ARMIRQV +#define ARMul_FIQV ARMFIQV + +/***************************************************************************\ +* Mode and Bank Constants * +\***************************************************************************/ + +#define USER26MODE 0L +#define FIQ26MODE 1L +#define IRQ26MODE 2L +#define SVC26MODE 3L +#define USER32MODE 16L +#define FIQ32MODE 17L +#define IRQ32MODE 18L +#define SVC32MODE 19L +#define ABORT32MODE 23L +#define UNDEF32MODE 27L +#define SYSTEMMODE 31L + +#define ARM32BITMODE (state->Mode > 3) +#define ARM26BITMODE (state->Mode <= 3) +#define ARMMODE (state->Mode) +#define ARMul_MODEBITS 0x1fL +#define ARMul_MODE32BIT ARM32BITMODE +#define ARMul_MODE26BIT ARM26BITMODE + +#define USERBANK 0 +#define FIQBANK 1 +#define IRQBANK 2 +#define SVCBANK 3 +#define ABORTBANK 4 +#define UNDEFBANK 5 +#define DUMMYBANK 6 +#define SYSTEMBANK USERBANK + +#define BANK_CAN_ACCESS_SPSR(bank) \ + ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK) + +/***************************************************************************\ +* Definitons of things in the emulator * +\***************************************************************************/ + +extern void ARMul_EmulateInit (void); +extern ARMul_State *ARMul_NewState (void); +extern void ARMul_Reset (ARMul_State * state); +extern ARMword ARMul_DoProg (ARMul_State * state); +extern ARMword ARMul_DoInstr (ARMul_State * state); + +/***************************************************************************\ +* Definitons of things for event handling * +\***************************************************************************/ + +extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay, + unsigned (*func) ()); +extern void ARMul_EnvokeEvent (ARMul_State * state); +extern unsigned long ARMul_Time (ARMul_State * state); + +/***************************************************************************\ +* Useful support routines * +\***************************************************************************/ + +extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, + unsigned reg); +extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, + ARMword value); +extern ARMword ARMul_GetPC (ARMul_State * state); +extern ARMword ARMul_GetNextPC (ARMul_State * state); +extern void ARMul_SetPC (ARMul_State * state, ARMword value); +extern ARMword ARMul_GetR15 (ARMul_State * state); +extern void ARMul_SetR15 (ARMul_State * state, ARMword value); + +extern ARMword ARMul_GetCPSR (ARMul_State * state); +extern void ARMul_SetCPSR (ARMul_State * state, ARMword value); +extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode); +extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value); + +/***************************************************************************\ +* Definitons of things to handle aborts * +\***************************************************************************/ + +extern void ARMul_Abort (ARMul_State * state, ARMword address); +#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ +#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ + state->AbortAddr = (address & ~3L) +#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \ + state->Aborted = ARMul_DataAbortV ; +#define ARMul_CLEARABORT state->abortSig = LOW + +/***************************************************************************\ +* Definitons of things in the memory interface * +\***************************************************************************/ + +extern unsigned ARMul_MemoryInit (ARMul_State * state, + unsigned long initmemsize); +extern void ARMul_MemoryExit (ARMul_State * state); + +extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, + ARMword isize); +extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, + ARMword isize); +extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address, + ARMword isize); + +extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address); +extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address); +extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address); +extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address); + +extern void ARMul_StoreWordS (ARMul_State * state, ARMword address, + ARMword data); +extern void ARMul_StoreWordN (ARMul_State * state, ARMword address, + ARMword data); +extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, + ARMword data); +extern void ARMul_StoreByte (ARMul_State * state, ARMword address, + ARMword data); + +extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, + ARMword data); +extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, + ARMword data); + +extern void ARMul_Icycles (ARMul_State * state, unsigned number, + ARMword address); +extern void ARMul_Ccycles (ARMul_State * state, unsigned number, + ARMword address); + +extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address); +extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address); +extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address); +extern void ARMul_WriteWord (ARMul_State * state, ARMword address, + ARMword data); +extern void ARMul_WriteByte (ARMul_State * state, ARMword address, + ARMword data); +extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address, + ARMword data); + +extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword, + ARMword, ARMword, ARMword, ARMword, ARMword, + ARMword, ARMword, ARMword); + +/***************************************************************************\ +* Definitons of things in the co-processor interface * +\***************************************************************************/ + +#define ARMul_FIRST 0 +#define ARMul_TRANSFER 1 +#define ARMul_BUSY 2 +#define ARMul_DATA 3 +#define ARMul_INTERRUPT 4 +#define ARMul_DONE 0 +#define ARMul_CANT 1 +#define ARMul_INC 3 + +#define ARMul_CP13_R0_FIQ 0x1 +#define ARMul_CP13_R0_IRQ 0x2 +#define ARMul_CP13_R8_PMUS 0x1 + +#define ARMul_CP14_R0_ENABLE 0x0001 +#define ARMul_CP14_R0_CLKRST 0x0004 +#define ARMul_CP14_R0_CCD 0x0008 +#define ARMul_CP14_R0_INTEN0 0x0010 +#define ARMul_CP14_R0_INTEN1 0x0020 +#define ARMul_CP14_R0_INTEN2 0x0040 +#define ARMul_CP14_R0_FLAG0 0x0100 +#define ARMul_CP14_R0_FLAG1 0x0200 +#define ARMul_CP14_R0_FLAG2 0x0400 +#define ARMul_CP14_R10_MOE_IB 0x0004 +#define ARMul_CP14_R10_MOE_DB 0x0008 +#define ARMul_CP14_R10_MOE_BT 0x000c +#define ARMul_CP15_R1_ENDIAN 0x0080 +#define ARMul_CP15_R1_ALIGN 0x0002 +#define ARMul_CP15_R5_X 0x0400 +#define ARMul_CP15_R5_ST_ALIGN 0x0001 +#define ARMul_CP15_R5_IMPRE 0x0406 +#define ARMul_CP15_R5_MMU_EXCPT 0x0400 +#define ARMul_CP15_DBCON_M 0x0100 +#define ARMul_CP15_DBCON_E1 0x000c +#define ARMul_CP15_DBCON_E0 0x0003 + +extern unsigned ARMul_CoProInit (ARMul_State * state); +extern void ARMul_CoProExit (ARMul_State * state); +extern void ARMul_CoProAttach (ARMul_State * state, unsigned number, + ARMul_CPInits * init, ARMul_CPExits * exit, + ARMul_LDCs * ldc, ARMul_STCs * stc, + ARMul_MRCs * mrc, ARMul_MCRs * mcr, + ARMul_CDPs * cdp, + ARMul_CPReads * read, ARMul_CPWrites * write); +extern void ARMul_CoProDetach (ARMul_State * state, unsigned number); +extern void XScale_check_memacc (ARMul_State * state, ARMword * address, + int store); +extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far); +extern int XScale_debug_moe (ARMul_State * state, int moe); + +/***************************************************************************\ +* Definitons of things in the host environment * +\***************************************************************************/ + +extern unsigned ARMul_OSInit (ARMul_State * state); +extern void ARMul_OSExit (ARMul_State * state); +extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number); +extern ARMword ARMul_OSLastErrorP (ARMul_State * state); + +extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr); +extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector, + ARMword pc); +extern int rdi_log; + +/***************************************************************************\ +* Host-dependent stuff * +\***************************************************************************/ + +#ifdef macintosh +pascal void SpinCursor (short increment); /* copied from CursorCtl.h */ +# define HOURGLASS SpinCursor( 1 ) +# define HOURGLASS_RATE 1023 /* 2^n - 1 */ +#endif + +extern void ARMul_UndefInstr (ARMul_State *, ARMword); +extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword); +extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword); +extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...); +extern void ARMul_SelectProcessor (ARMul_State *, unsigned); diff --git a/external/gpl3/gdb/dist/sim/arm/armemu.c b/external/gpl3/gdb/dist/sim/arm/armemu.c new file mode 100644 index 000000000000..558e897582ae --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armemu.c @@ -0,0 +1,5186 @@ +/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + Modifications to add arch. v4 support by . + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "armdefs.h" +#include "armemu.h" +#include "armos.h" +#include "iwmmxt.h" + +static ARMword GetDPRegRHS (ARMul_State *, ARMword); +static ARMword GetDPSRegRHS (ARMul_State *, ARMword); +static void WriteR15 (ARMul_State *, ARMword); +static void WriteSR15 (ARMul_State *, ARMword); +static void WriteR15Branch (ARMul_State *, ARMword); +static ARMword GetLSRegRHS (ARMul_State *, ARMword); +static ARMword GetLS7RHS (ARMul_State *, ARMword); +static unsigned LoadWord (ARMul_State *, ARMword, ARMword); +static unsigned LoadHalfWord (ARMul_State *, ARMword, ARMword, int); +static unsigned LoadByte (ARMul_State *, ARMword, ARMword, int); +static unsigned StoreWord (ARMul_State *, ARMword, ARMword); +static unsigned StoreHalfWord (ARMul_State *, ARMword, ARMword); +static unsigned StoreByte (ARMul_State *, ARMword, ARMword); +static void LoadMult (ARMul_State *, ARMword, ARMword, ARMword); +static void StoreMult (ARMul_State *, ARMword, ARMword, ARMword); +static void LoadSMult (ARMul_State *, ARMword, ARMword, ARMword); +static void StoreSMult (ARMul_State *, ARMword, ARMword, ARMword); +static unsigned Multiply64 (ARMul_State *, ARMword, int, int); +static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int); +static void Handle_Load_Double (ARMul_State *, ARMword); +static void Handle_Store_Double (ARMul_State *, ARMword); + +#define LUNSIGNED (0) /* unsigned operation */ +#define LSIGNED (1) /* signed operation */ +#define LDEFAULT (0) /* default : do nothing */ +#define LSCC (1) /* set condition codes on result */ + +#ifdef NEED_UI_LOOP_HOOK +/* How often to run the ui_loop update, when in use. */ +#define UI_LOOP_POLL_INTERVAL 0x32000 + +/* Counter for the ui_loop_hook update. */ +static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + +/* Actual hook to call to run through gdb's gui event loop. */ +extern int (*deprecated_ui_loop_hook) (int); +#endif /* NEED_UI_LOOP_HOOK */ + +extern int stop_simulator; + +/* Short-hand macros for LDR/STR. */ + +/* Store post decrement writeback. */ +#define SHDOWNWB() \ + lhs = LHS ; \ + if (StoreHalfWord (state, instr, lhs)) \ + LSBase = lhs - GetLS7RHS (state, instr); + +/* Store post increment writeback. */ +#define SHUPWB() \ + lhs = LHS ; \ + if (StoreHalfWord (state, instr, lhs)) \ + LSBase = lhs + GetLS7RHS (state, instr); + +/* Store pre decrement. */ +#define SHPREDOWN() \ + (void)StoreHalfWord (state, instr, LHS - GetLS7RHS (state, instr)); + +/* Store pre decrement writeback. */ +#define SHPREDOWNWB() \ + temp = LHS - GetLS7RHS (state, instr); \ + if (StoreHalfWord (state, instr, temp)) \ + LSBase = temp; + +/* Store pre increment. */ +#define SHPREUP() \ + (void)StoreHalfWord (state, instr, LHS + GetLS7RHS (state, instr)); + +/* Store pre increment writeback. */ +#define SHPREUPWB() \ + temp = LHS + GetLS7RHS (state, instr); \ + if (StoreHalfWord (state, instr, temp)) \ + LSBase = temp; + +/* Load post decrement writeback. */ +#define LHPOSTDOWN() \ +{ \ + int done = 1; \ + lhs = LHS; \ + temp = lhs - GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load post increment writeback. */ +#define LHPOSTUP() \ +{ \ + int done = 1; \ + lhs = LHS; \ + temp = lhs + GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre decrement. */ +#define LHPREDOWN() \ +{ \ + int done = 1; \ + \ + temp = LHS - GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ + break; \ + case 2: /* SB */ \ + (void) LoadByte (state, instr, temp, LSIGNED); \ + break; \ + case 3: /* SH */ \ + (void) LoadHalfWord (state, instr, temp, LSIGNED); \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre decrement writeback. */ +#define LHPREDOWNWB() \ +{ \ + int done = 1; \ + \ + temp = LHS - GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre increment. */ +#define LHPREUP() \ +{ \ + int done = 1; \ + \ + temp = LHS + GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ + break; \ + case 2: /* SB */ \ + (void) LoadByte (state, instr, temp, LSIGNED); \ + break; \ + case 3: /* SH */ \ + (void) LoadHalfWord (state, instr, temp, LSIGNED); \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Load pre increment writeback. */ +#define LHPREUPWB() \ +{ \ + int done = 1; \ + \ + temp = LHS + GetLS7RHS (state, instr); \ + switch (BITS (5, 6)) \ + { \ + case 1: /* H */ \ + if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ + LSBase = temp; \ + break; \ + case 2: /* SB */ \ + if (LoadByte (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 3: /* SH */ \ + if (LoadHalfWord (state, instr, temp, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: \ + /* SWP handled elsewhere. */ \ + default: \ + done = 0; \ + break; \ + } \ + if (done) \ + break; \ +} + +/* Attempt to emulate an ARMv6 instruction. + Returns non-zero upon success. */ + +static int +handle_v6_insn (ARMul_State * state, ARMword instr) +{ + switch (BITS (20, 27)) + { +#if 0 + case 0x03: printf ("Unhandled v6 insn: ldr\n"); break; + case 0x04: printf ("Unhandled v6 insn: umaal\n"); break; + case 0x06: printf ("Unhandled v6 insn: mls/str\n"); break; + case 0x16: printf ("Unhandled v6 insn: smi\n"); break; + case 0x18: printf ("Unhandled v6 insn: strex\n"); break; + case 0x19: printf ("Unhandled v6 insn: ldrex\n"); break; + case 0x1a: printf ("Unhandled v6 insn: strexd\n"); break; + case 0x1b: printf ("Unhandled v6 insn: ldrexd\n"); break; + case 0x1c: printf ("Unhandled v6 insn: strexb\n"); break; + case 0x1d: printf ("Unhandled v6 insn: ldrexb\n"); break; + case 0x1e: printf ("Unhandled v6 insn: strexh\n"); break; + case 0x1f: printf ("Unhandled v6 insn: ldrexh\n"); break; + case 0x30: printf ("Unhandled v6 insn: movw\n"); break; + case 0x32: printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n"); break; + case 0x34: printf ("Unhandled v6 insn: movt\n"); break; + case 0x3f: printf ("Unhandled v6 insn: rbit\n"); break; +#endif + case 0x61: printf ("Unhandled v6 insn: sadd/ssub\n"); break; + case 0x62: printf ("Unhandled v6 insn: qadd/qsub\n"); break; + case 0x63: printf ("Unhandled v6 insn: shadd/shsub\n"); break; + case 0x65: printf ("Unhandled v6 insn: uadd/usub\n"); break; + case 0x66: printf ("Unhandled v6 insn: uqadd/uqsub\n"); break; + case 0x67: printf ("Unhandled v6 insn: uhadd/uhsub\n"); break; + case 0x68: printf ("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); break; + case 0x6c: printf ("Unhandled v6 insn: uxtb16/uxtab16\n"); break; + case 0x70: printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n"); break; + case 0x74: printf ("Unhandled v6 insn: smlald/smlsld\n"); break; + case 0x75: printf ("Unhandled v6 insn: smmla/smmls/smmul\n"); break; + case 0x78: printf ("Unhandled v6 insn: usad/usada8\n"); break; + case 0x7a: printf ("Unhandled v6 insn: usbfx\n"); break; + case 0x7c: printf ("Unhandled v6 insn: bfc/bfi\n"); break; + + case 0x6a: + { + ARMword Rm; + int ror = -1; + + switch (BITS (4, 11)) + { + case 0x07: ror = 0; break; + case 0x47: ror = 8; break; + case 0x87: ror = 16; break; + case 0xc7: ror = 24; break; + + case 0x01: + case 0xf3: + printf ("Unhandled v6 insn: ssat\n"); + return 0; + default: + break; + } + + if (ror == -1) + { + if (BITS (4, 6) == 0x7) + { + printf ("Unhandled v6 insn: ssat\n"); + return 0; + } + break; + } + + Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); + if (Rm & 0x80) + Rm |= 0xffffff00; + + if (BITS (16, 19) == 0xf) + /* SXTB */ + state->Reg[BITS (12, 15)] = Rm; + else + /* SXTAB */ + state->Reg[BITS (12, 15)] += Rm; + } + return 1; + + case 0x6b: + { + ARMword Rm; + int ror = -1; + + switch (BITS (4, 11)) + { + case 0x07: ror = 0; break; + case 0x47: ror = 8; break; + case 0x87: ror = 16; break; + case 0xc7: ror = 24; break; + + case 0xfb: + printf ("Unhandled v6 insn: rev\n"); + return 0; + default: + break; + } + + if (ror == -1) + break; + + Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); + if (Rm & 0x8000) + Rm |= 0xffff0000; + + if (BITS (16, 19) == 0xf) + /* SXTH */ + state->Reg[BITS (12, 15)] = Rm; + else + /* SXTAH */ + state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; + } + return 1; + + case 0x6e: + { + ARMword Rm; + int ror = -1; + + switch (BITS (4, 11)) + { + case 0x07: ror = 0; break; + case 0x47: ror = 8; break; + case 0x87: ror = 16; break; + case 0xc7: ror = 24; break; + + case 0x01: + case 0xf3: + printf ("Unhandled v6 insn: usat\n"); + return 0; + default: + break; + } + + if (ror == -1) + { + if (BITS (4, 6) == 0x7) + { + printf ("Unhandled v6 insn: usat\n"); + return 0; + } + break; + } + + Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); + + if (BITS (16, 19) == 0xf) + /* UXTB */ + state->Reg[BITS (12, 15)] = Rm; + else + /* UXTAB */ + state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; + } + return 1; + + case 0x6f: + { + ARMword Rm; + int ror = -1; + + switch (BITS (4, 11)) + { + case 0x07: ror = 0; break; + case 0x47: ror = 8; break; + case 0x87: ror = 16; break; + case 0xc7: ror = 24; break; + + case 0xfb: + printf ("Unhandled v6 insn: revsh\n"); + return 0; + default: + break; + } + + if (ror == -1) + break; + + Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); + + if (BITS (16, 19) == 0xf) + /* UXT */ + state->Reg[BITS (12, 15)] = Rm; + else + { + /* UXTAH */ + state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; + } + } + return 1; + +#if 0 + case 0x84: printf ("Unhandled v6 insn: srs\n"); break; +#endif + default: + break; + } + printf ("Unhandled v6 insn: UNKNOWN: %08x\n", instr); + return 0; +} + +/* EMULATION of ARM6. */ + +/* The PC pipeline value depends on whether ARM + or Thumb instructions are being executed. */ +ARMword isize; + +ARMword +#ifdef MODE32 +ARMul_Emulate32 (ARMul_State * state) +#else +ARMul_Emulate26 (ARMul_State * state) +#endif +{ + ARMword instr; /* The current instruction. */ + ARMword dest = 0; /* Almost the DestBus. */ + ARMword temp; /* Ubiquitous third hand. */ + ARMword pc = 0; /* The address of the current instruction. */ + ARMword lhs; /* Almost the ABus and BBus. */ + ARMword rhs; + ARMword decoded = 0; /* Instruction pipeline. */ + ARMword loaded = 0; + + /* Execute the next instruction. */ + + if (state->NextInstr < PRIMEPIPE) + { + decoded = state->decoded; + loaded = state->loaded; + pc = state->pc; + } + + do + { + /* Just keep going. */ + isize = INSN_SIZE; + + switch (state->NextInstr) + { + case SEQ: + /* Advance the pipeline, and an S cycle. */ + state->Reg[15] += isize; + pc += isize; + instr = decoded; + decoded = loaded; + loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); + break; + + case NONSEQ: + /* Advance the pipeline, and an N cycle. */ + state->Reg[15] += isize; + pc += isize; + instr = decoded; + decoded = loaded; + loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize); + NORMALCYCLE; + break; + + case PCINCEDSEQ: + /* Program counter advanced, and an S cycle. */ + pc += isize; + instr = decoded; + decoded = loaded; + loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); + NORMALCYCLE; + break; + + case PCINCEDNONSEQ: + /* Program counter advanced, and an N cycle. */ + pc += isize; + instr = decoded; + decoded = loaded; + loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize); + NORMALCYCLE; + break; + + case RESUME: + /* The program counter has been changed. */ + pc = state->Reg[15]; +#ifndef MODE32 + pc = pc & R15PCBITS; +#endif + state->Reg[15] = pc + (isize * 2); + state->Aborted = 0; + instr = ARMul_ReLoadInstr (state, pc, isize); + decoded = ARMul_ReLoadInstr (state, pc + isize, isize); + loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize); + NORMALCYCLE; + break; + + default: + /* The program counter has been changed. */ + pc = state->Reg[15]; +#ifndef MODE32 + pc = pc & R15PCBITS; +#endif + state->Reg[15] = pc + (isize * 2); + state->Aborted = 0; + instr = ARMul_LoadInstrN (state, pc, isize); + decoded = ARMul_LoadInstrS (state, pc + (isize), isize); + loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize); + NORMALCYCLE; + break; + } + + if (state->EventSet) + ARMul_EnvokeEvent (state); +#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ + fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); + if (instr == 0) + abort (); +#endif +#if 0 /* Enable this code to help track down stack alignment bugs. */ + { + static ARMword old_sp = -1; + + if (old_sp != state->Reg[13]) + { + old_sp = state->Reg[13]; + fprintf (stderr, "pc: %08x: SP set to %08x%s\n", + pc & ~1, old_sp, (old_sp % 8) ? " [UNALIGNED!]" : ""); + } + } +#endif + + if (state->Exception) + { + /* Any exceptions ? */ + if (state->NresetSig == LOW) + { + ARMul_Abort (state, ARMul_ResetV); + break; + } + else if (!state->NfiqSig && !FFLAG) + { + ARMul_Abort (state, ARMul_FIQV); + break; + } + else if (!state->NirqSig && !IFLAG) + { + ARMul_Abort (state, ARMul_IRQV); + break; + } + } + + if (state->CallDebug > 0) + { + instr = ARMul_Debug (state, pc, instr); + if (state->Emulate < ONCE) + { + state->NextInstr = RESUME; + break; + } + if (state->Debug) + { + fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n", pc, instr, + state->Mode); + (void) fgetc (stdin); + } + } + else if (state->Emulate < ONCE) + { + state->NextInstr = RESUME; + break; + } + + state->NumInstrs++; + +#ifdef MODET + /* Provide Thumb instruction decoding. If the processor is in Thumb + mode, then we can simply decode the Thumb instruction, and map it + to the corresponding ARM instruction (by directly loading the + instr variable, and letting the normal ARM simulator + execute). There are some caveats to ensure that the correct + pipelined PC value is used when executing Thumb code, and also for + dealing with the BL instruction. */ + if (TFLAG) + { + ARMword new; + + /* Check if in Thumb mode. */ + switch (ARMul_ThumbDecode (state, pc, instr, &new)) + { + case t_undefined: + /* This is a Thumb instruction. */ + ARMul_UndefInstr (state, instr); + goto donext; + + case t_branch: + /* Already processed. */ + goto donext; + + case t_decoded: + /* ARM instruction available. */ + instr = new; + /* So continue instruction decoding. */ + break; + default: + break; + } + } +#endif + + /* Check the condition codes. */ + if ((temp = TOPBITS (28)) == AL) + /* Vile deed in the need for speed. */ + goto mainswitch; + + /* Check the condition code. */ + switch ((int) TOPBITS (28)) + { + case AL: + temp = TRUE; + break; + case NV: + if (state->is_v5) + { + if (BITS (25, 27) == 5) /* BLX(1) */ + { + ARMword dest; + + state->Reg[14] = pc + 4; + + /* Force entry into Thumb mode. */ + dest = pc + 8 + 1; + if (BIT (23)) + dest += (NEGBRANCH + (BIT (24) << 1)); + else + dest += POSBRANCH + (BIT (24) << 1); + + WriteR15Branch (state, dest); + goto donext; + } + else if ((instr & 0xFC70F000) == 0xF450F000) + /* The PLD instruction. Ignored. */ + goto donext; + else if ( ((instr & 0xfe500f00) == 0xfc100100) + || ((instr & 0xfe500f00) == 0xfc000100)) + /* wldrw and wstrw are unconditional. */ + goto mainswitch; + else + /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */ + ARMul_UndefInstr (state, instr); + } + temp = FALSE; + break; + case EQ: + temp = ZFLAG; + break; + case NE: + temp = !ZFLAG; + break; + case VS: + temp = VFLAG; + break; + case VC: + temp = !VFLAG; + break; + case MI: + temp = NFLAG; + break; + case PL: + temp = !NFLAG; + break; + case CS: + temp = CFLAG; + break; + case CC: + temp = !CFLAG; + break; + case HI: + temp = (CFLAG && !ZFLAG); + break; + case LS: + temp = (!CFLAG || ZFLAG); + break; + case GE: + temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); + break; + case LT: + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); + break; + case GT: + temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG)); + break; + case LE: + temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; + break; + } /* cc check */ + + /* Handle the Clock counter here. */ + if (state->is_XScale) + { + ARMword cp14r0; + int ok; + + ok = state->CPRead[14] (state, 0, & cp14r0); + + if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE)) + { + unsigned long newcycles, nowtime = ARMul_Time (state); + + newcycles = nowtime - state->LastTime; + state->LastTime = nowtime; + + if (cp14r0 & ARMul_CP14_R0_CCD) + { + if (state->CP14R0_CCD == -1) + state->CP14R0_CCD = newcycles; + else + state->CP14R0_CCD += newcycles; + + if (state->CP14R0_CCD >= 64) + { + newcycles = 0; + + while (state->CP14R0_CCD >= 64) + state->CP14R0_CCD -= 64, newcycles++; + + goto check_PMUintr; + } + } + else + { + ARMword cp14r1; + int do_int = 0; + + state->CP14R0_CCD = -1; +check_PMUintr: + cp14r0 |= ARMul_CP14_R0_FLAG2; + (void) state->CPWrite[14] (state, 0, cp14r0); + + ok = state->CPRead[14] (state, 1, & cp14r1); + + /* Coded like this for portability. */ + while (ok && newcycles) + { + if (cp14r1 == 0xffffffff) + { + cp14r1 = 0; + do_int = 1; + } + else + cp14r1 ++; + + newcycles --; + } + + (void) state->CPWrite[14] (state, 1, cp14r1); + + if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2)) + { + ARMword temp; + + if (state->CPRead[13] (state, 8, & temp) + && (temp & ARMul_CP13_R8_PMUS)) + ARMul_Abort (state, ARMul_FIQV); + else + ARMul_Abort (state, ARMul_IRQV); + } + } + } + } + + /* Handle hardware instructions breakpoints here. */ + if (state->is_XScale) + { + if ( (pc | 3) == (read_cp15_reg (14, 0, 8) | 2) + || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2)) + { + if (XScale_debug_moe (state, ARMul_CP14_R10_MOE_IB)) + ARMul_OSHandleSWI (state, SWI_Breakpoint); + } + } + + /* Actual execution of instructions begins here. */ + /* If the condition codes don't match, stop here. */ + if (temp) + { + mainswitch: + + if (state->is_XScale) + { + if (BIT (20) == 0 && BITS (25, 27) == 0) + { + if (BITS (4, 7) == 0xD) + { + /* XScale Load Consecutive insn. */ + ARMword temp = GetLS7RHS (state, instr); + ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; + ARMword addr = BIT (24) ? temp2 : LHS; + + if (BIT (12)) + ARMul_UndefInstr (state, instr); + else if (addr & 7) + /* Alignment violation. */ + ARMul_Abort (state, ARMul_DataAbortV); + else + { + int wb = BIT (21) || (! BIT (24)); + + state->Reg[BITS (12, 15)] = + ARMul_LoadWordN (state, addr); + state->Reg[BITS (12, 15) + 1] = + ARMul_LoadWordN (state, addr + 4); + if (wb) + LSBase = temp2; + } + + goto donext; + } + else if (BITS (4, 7) == 0xF) + { + /* XScale Store Consecutive insn. */ + ARMword temp = GetLS7RHS (state, instr); + ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; + ARMword addr = BIT (24) ? temp2 : LHS; + + if (BIT (12)) + ARMul_UndefInstr (state, instr); + else if (addr & 7) + /* Alignment violation. */ + ARMul_Abort (state, ARMul_DataAbortV); + else + { + ARMul_StoreWordN (state, addr, + state->Reg[BITS (12, 15)]); + ARMul_StoreWordN (state, addr + 4, + state->Reg[BITS (12, 15) + 1]); + + if (BIT (21)|| ! BIT (24)) + LSBase = temp2; + } + + goto donext; + } + } + + if (ARMul_HandleIwmmxt (state, instr)) + goto donext; + } + + switch ((int) BITS (20, 27)) + { + /* Data Processing Register RHS Instructions. */ + + case 0x00: /* AND reg and MUL */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, no write-back, down, post indexed. */ + SHDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 7) == 9) + { + /* MUL */ + rhs = state->Reg[MULRHSReg]; + if (MULLHSReg == MULDESTReg) + { + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = 0; + } + else if (MULDESTReg != 15) + state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs; + else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; dest ++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } + else + { + /* AND reg. */ + rhs = DPRegRHS; + dest = LHS & rhs; + WRITEDEST (dest); + } + break; + + case 0x01: /* ANDS reg and MULS */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to rest of decoding. */ +#endif + if (BITS (4, 7) == 9) + { + /* MULS */ + rhs = state->Reg[MULRHSReg]; + + if (MULLHSReg == MULDESTReg) + { + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = 0; + CLEARN; + SETZ; + } + else if (MULDESTReg != 15) + { + dest = state->Reg[MULLHSReg] * rhs; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } + else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; dest ++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } + else + { + /* ANDS reg. */ + rhs = DPSRegRHS; + dest = LHS & rhs; + WRITESDEST (dest); + } + break; + + case 0x02: /* EOR reg and MLA */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, write-back, down, post indexed. */ + SHDOWNWB (); + break; + } +#endif + if (BITS (4, 7) == 9) + { /* MLA */ + rhs = state->Reg[MULRHSReg]; + if (MULLHSReg == MULDESTReg) + { + UNDEF_MULDestEQOp1; + state->Reg[MULDESTReg] = state->Reg[MULACCReg]; + } + else if (MULDESTReg != 15) + state->Reg[MULDESTReg] = + state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; + else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; dest ++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } + else + { + rhs = DPRegRHS; + dest = LHS ^ rhs; + WRITEDEST (dest); + } + break; + + case 0x03: /* EORS reg and MLAS */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, down, post-indexed. */ + LHPOSTDOWN (); + /* Fall through to rest of the decoding. */ +#endif + if (BITS (4, 7) == 9) + { + /* MLAS */ + rhs = state->Reg[MULRHSReg]; + + if (MULLHSReg == MULDESTReg) + { + UNDEF_MULDestEQOp1; + dest = state->Reg[MULACCReg]; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } + else if (MULDESTReg != 15) + { + dest = + state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg]; + ARMul_NegZero (state, dest); + state->Reg[MULDESTReg] = dest; + } + else + UNDEF_MULPCDest; + + for (dest = 0, temp = 0; dest < 32; dest ++) + if (rhs & (1L << dest)) + temp = dest; + + /* Mult takes this many/2 I cycles. */ + ARMul_Icycles (state, ARMul_MultTable[temp], 0L); + } + else + { + /* EORS Reg. */ + rhs = DPSRegRHS; + dest = LHS ^ rhs; + WRITESDEST (dest); + } + break; + + case 0x04: /* SUB reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, no write-back, down, post indexed. */ + SHDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS - rhs; + WRITEDEST (dest); + break; + + case 0x05: /* SUBS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to the rest of the instruction decoding. */ +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs; + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x06: /* RSB reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, write-back, down, post indexed. */ + SHDOWNWB (); + break; + } +#endif + rhs = DPRegRHS; + dest = rhs - LHS; + WRITEDEST (dest); + break; + + case 0x07: /* RSBS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, down, post indexed. */ + LHPOSTDOWN (); + /* Fall through to remainder of instruction decoding. */ +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = rhs - lhs; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x08: /* ADD reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, no write-back, up, post indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif +#ifdef MODET + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32 = 64 */ + ARMul_Icycles (state, + Multiply64 (state, instr, LUNSIGNED, + LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS + rhs; + WRITEDEST (dest); + break; + + case 0x09: /* ADDS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ +#endif +#ifdef MODET + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + Multiply64 (state, instr, LUNSIGNED, LSCC), + 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0a: /* ADC reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, write-back, up, post-indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + MultiplyAdd64 (state, instr, LUNSIGNED, + LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS + rhs + CFLAG; + WRITEDEST (dest); + break; + + case 0x0b: /* ADCS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + MultiplyAdd64 (state, instr, LUNSIGNED, + LSCC), 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs + CFLAG; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0c: /* SBC reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, no write-back, up post indexed. */ + SHUPWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + Multiply64 (state, instr, LSIGNED, LDEFAULT), + 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS - rhs - !CFLAG; + WRITEDEST (dest); + break; + + case 0x0d: /* SBCS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, up, post indexed. */ + LHPOSTUP (); + + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + Multiply64 (state, instr, LSIGNED, LSCC), + 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs - !CFLAG; + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x0e: /* RSC reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, write-back, up, post indexed. */ + SHUPWB (); + break; + } + + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + MultiplyAdd64 (state, instr, LSIGNED, + LDEFAULT), 0L); + break; + } +#endif + rhs = DPRegRHS; + dest = rhs - LHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x0f: /* RSCS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, up, post indexed. */ + LHPOSTUP (); + /* Fall through to remaining instruction decoding. */ + + if (BITS (4, 7) == 0x9) + { + /* MULL */ + /* 32x32=64 */ + ARMul_Icycles (state, + MultiplyAdd64 (state, instr, LSIGNED, LSCC), + 0L); + break; + } +#endif + lhs = LHS; + rhs = DPRegRHS; + dest = rhs - lhs - !CFLAG; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x10: /* TST reg and MRS CPSR and SWP word. */ + if (state->is_v5e) + { + if (BIT (4) == 0 && BIT (7) == 1) + { + /* ElSegundo SMLAxy insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (8, 11)]; + ARMword Rn = state->Reg[BITS (12, 15)]; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + op2 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + if (op2 & 0x8000) + op2 -= 65536; + op1 *= op2; + + if (AddOverflow (op1, Rn, op1 + Rn)) + SETS; + state->Reg[BITS (16, 19)] = op1 + Rn; + break; + } + + if (BITS (4, 11) == 5) + { + /* ElSegundo QADD insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword result = op1 + op2; + if (AddOverflow (op1, op2, result)) + { + result = POS (result) ? 0x80000000 : 0x7fffffff; + SETS; + } + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, no write-back, down, pre indexed. */ + SHPREDOWN (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 11) == 9) + { + /* SWP */ + UNDEF_SWPPC; + temp = LHS; + BUSUSEDINCPCS; +#ifndef MODE32 + if (VECTORACCESS (temp) || ADDREXCEPT (temp)) + { + INTERNALABORT (temp); + (void) ARMul_LoadWordN (state, temp); + (void) ARMul_LoadWordN (state, temp); + } + else +#endif + dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]); + if (temp & 3) + DEST = ARMul_Align (state, temp, dest); + else + DEST = dest; + if (state->abortSig || state->Aborted) + TAKEABORT; + } + else if ((BITS (0, 11) == 0) && (LHSReg == 15)) + { /* MRS CPSR */ + UNDEF_MRSPC; + DEST = ECC | EINT | EMODE; + } + else + { + UNDEF_Test; + } + break; + + case 0x11: /* TSTP reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, down, pre indexed. */ + LHPREDOWN (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) + { + /* TSTP reg */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS & rhs; + SETR15PSR (temp); +#endif + } + else + { + /* TST reg */ + rhs = DPSRegRHS; + dest = LHS & rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */ + if (state->is_v5) + { + if (BITS (4, 7) == 3) + { + /* BLX(2) */ + ARMword temp; + + if (TFLAG) + temp = (pc + 2) | 1; + else + temp = pc + 4; + + WriteR15Branch (state, state->Reg[RHSReg]); + state->Reg[14] = temp; + break; + } + } + + if (state->is_v5e) + { + if (BIT (4) == 0 && BIT (7) == 1 + && (BIT (5) == 0 || BITS (12, 15) == 0)) + { + /* ElSegundo SMLAWy/SMULWy insn. */ + ARMdword op1 = state->Reg[BITS (0, 3)]; + ARMdword op2 = state->Reg[BITS (8, 11)]; + ARMdword result; + + if (BIT (6)) + op2 >>= 16; + if (op1 & 0x80000000) + op1 -= 1ULL << 32; + op2 &= 0xFFFF; + if (op2 & 0x8000) + op2 -= 65536; + result = (op1 * op2) >> 16; + + if (BIT (5) == 0) + { + ARMword Rn = state->Reg[BITS (12, 15)]; + + if (AddOverflow (result, Rn, result + Rn)) + SETS; + result += Rn; + } + state->Reg[BITS (16, 19)] = result; + break; + } + + if (BITS (4, 11) == 5) + { + /* ElSegundo QSUB insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword result = op1 - op2; + + if (SubOverflow (op1, op2, result)) + { + result = POS (result) ? 0x80000000 : 0x7fffffff; + SETS; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, write-back, down, pre indexed. */ + SHPREDOWNWB (); + break; + } + if (BITS (4, 27) == 0x12FFF1) + { + /* BX */ + WriteR15Branch (state, state->Reg[RHSReg]); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + if (state->is_v5) + { + if (BITS (4, 7) == 0x7) + { + ARMword value; + extern int SWI_vector_installed; + + /* Hardware is allowed to optionally override this + instruction and treat it as a breakpoint. Since + this is a simulator not hardware, we take the position + that if a SWI vector was not installed, then an Abort + vector was probably not installed either, and so + normally this instruction would be ignored, even if an + Abort is generated. This is a bad thing, since GDB + uses this instruction for its breakpoints (at least in + Thumb mode it does). So intercept the instruction here + and generate a breakpoint SWI instead. */ + if (! SWI_vector_installed) + ARMul_OSHandleSWI (state, SWI_Breakpoint); + else + { + /* BKPT - normally this will cause an abort, but on the + XScale we must check the DCSR. */ + XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc); + if (!XScale_debug_moe (state, ARMul_CP14_R10_MOE_BT)) + break; + } + + /* Force the next instruction to be refetched. */ + state->NextInstr = RESUME; + break; + } + } + if (DESTReg == 15) + { + /* MSR reg to CPSR. */ + UNDEF_MSRPC; + temp = DPRegRHS; +#ifdef MODET + /* Don't allow TBIT to be set by MSR. */ + temp &= ~ TBIT; +#endif + ARMul_FixCPSR (state, instr, temp); + } + else + UNDEF_Test; + + break; + + case 0x13: /* TEQP reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, down, pre indexed. */ + LHPREDOWNWB (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) + { + /* TEQP reg */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS ^ rhs; + SETR15PSR (temp); +#endif + } + else + { + /* TEQ Reg. */ + rhs = DPSRegRHS; + dest = LHS ^ rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x14: /* CMP reg and MRS SPSR and SWP byte. */ + if (state->is_v5e) + { + if (BIT (4) == 0 && BIT (7) == 1) + { + /* ElSegundo SMLALxy insn. */ + ARMdword op1 = state->Reg[BITS (0, 3)]; + ARMdword op2 = state->Reg[BITS (8, 11)]; + ARMdword dest; + ARMdword result; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + op2 &= 0xFFFF; + if (op2 & 0x8000) + op2 -= 65536; + + dest = (ARMdword) state->Reg[BITS (16, 19)] << 32; + dest |= state->Reg[BITS (12, 15)]; + dest += op1 * op2; + state->Reg[BITS (12, 15)] = dest; + state->Reg[BITS (16, 19)] = dest >> 32; + break; + } + + if (BITS (4, 11) == 5) + { + /* ElSegundo QDADD insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword op2d = op2 + op2; + ARMword result; + + if (AddOverflow (op2, op2, op2d)) + { + SETS; + op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; + } + + result = op1 + op2d; + if (AddOverflow (op1, op2d, result)) + { + SETS; + result = POS (result) ? 0x80000000 : 0x7fffffff; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, no write-back, down, pre indexed. */ + SHPREDOWN (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + if (BITS (4, 11) == 9) + { + /* SWP */ + UNDEF_SWPPC; + temp = LHS; + BUSUSEDINCPCS; +#ifndef MODE32 + if (VECTORACCESS (temp) || ADDREXCEPT (temp)) + { + INTERNALABORT (temp); + (void) ARMul_LoadByte (state, temp); + (void) ARMul_LoadByte (state, temp); + } + else +#endif + DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]); + if (state->abortSig || state->Aborted) + TAKEABORT; + } + else if ((BITS (0, 11) == 0) && (LHSReg == 15)) + { + /* MRS SPSR */ + UNDEF_MRSPC; + DEST = GETSPSR (state->Bank); + } + else + UNDEF_Test; + + break; + + case 0x15: /* CMPP reg. */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, down, pre indexed. */ + LHPREDOWN (); + /* Continue with remaining instruction decode. */ +#endif + if (DESTReg == 15) + { + /* CMPP reg. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS - rhs; + SETR15PSR (temp); +#endif + } + else + { + /* CMP reg. */ + lhs = LHS; + rhs = DPRegRHS; + dest = lhs - rhs; + ARMul_NegZero (state, dest); + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + } + break; + + case 0x16: /* CMN reg and MSR reg to SPSR */ + if (state->is_v5e) + { + if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0) + { + /* ElSegundo SMULxy insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (8, 11)]; + ARMword Rn = state->Reg[BITS (12, 15)]; + + if (BIT (5)) + op1 >>= 16; + if (BIT (6)) + op2 >>= 16; + op1 &= 0xFFFF; + op2 &= 0xFFFF; + if (op1 & 0x8000) + op1 -= 65536; + if (op2 & 0x8000) + op2 -= 65536; + + state->Reg[BITS (16, 19)] = op1 * op2; + break; + } + + if (BITS (4, 11) == 5) + { + /* ElSegundo QDSUB insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + ARMword op2 = state->Reg[BITS (16, 19)]; + ARMword op2d = op2 + op2; + ARMword result; + + if (AddOverflow (op2, op2, op2d)) + { + SETS; + op2d = POS (op2d) ? 0x80000000 : 0x7fffffff; + } + + result = op1 - op2d; + if (SubOverflow (op1, op2d, result)) + { + SETS; + result = POS (result) ? 0x80000000 : 0x7fffffff; + } + + state->Reg[BITS (12, 15)] = result; + break; + } + } + + if (state->is_v5) + { + if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF) + { + /* ARM5 CLZ insn. */ + ARMword op1 = state->Reg[BITS (0, 3)]; + int result = 32; + + if (op1) + for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1) + result++; + + state->Reg[BITS (12, 15)] = result; + break; + } + } +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, write-back, down, pre indexed. */ + SHPREDOWNWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + if (DESTReg == 15) + { + /* MSR */ + UNDEF_MSRPC; + ARMul_FixSPSR (state, instr, DPRegRHS); + } + else + { + UNDEF_Test; + } + break; + + case 0x17: /* CMNP reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, down, pre indexed. */ + LHPREDOWNWB (); + /* Continue with remaining instruction decoding. */ +#endif + if (DESTReg == 15) + { +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + rhs = DPRegRHS; + temp = LHS + rhs; + SETR15PSR (temp); +#endif + break; + } + else + { + /* CMN reg. */ + lhs = LHS; + rhs = DPRegRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + } + break; + + case 0x18: /* ORR reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, no write-back, up, pre indexed. */ + SHPREUP (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS | rhs; + WRITEDEST (dest); + break; + + case 0x19: /* ORRS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, no write-back, up, pre indexed. */ + LHPREUP (); + /* Continue with remaining instruction decoding. */ +#endif + rhs = DPSRegRHS; + dest = LHS | rhs; + WRITESDEST (dest); + break; + + case 0x1a: /* MOV reg */ +#ifdef MODET + if (BITS (4, 11) == 0xB) + { + /* STRH register offset, write-back, up, pre indexed. */ + SHPREUPWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + dest = DPRegRHS; + WRITEDEST (dest); + break; + + case 0x1b: /* MOVS reg */ +#ifdef MODET + if ((BITS (4, 11) & 0xF9) == 0x9) + /* LDR register offset, write-back, up, pre indexed. */ + LHPREUPWB (); + /* Continue with remaining instruction decoding. */ +#endif + dest = DPSRegRHS; + WRITESDEST (dest); + break; + + case 0x1c: /* BIC reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, no write-back, up, pre indexed. */ + SHPREUP (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + else if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + rhs = DPRegRHS; + dest = LHS & ~rhs; + WRITEDEST (dest); + break; + + case 0x1d: /* BICS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, no write-back, up, pre indexed. */ + LHPREUP (); + /* Continue with instruction decoding. */ +#endif + rhs = DPSRegRHS; + dest = LHS & ~rhs; + WRITESDEST (dest); + break; + + case 0x1e: /* MVN reg */ +#ifdef MODET + if (BITS (4, 7) == 0xB) + { + /* STRH immediate offset, write-back, up, pre indexed. */ + SHPREUPWB (); + break; + } + if (BITS (4, 7) == 0xD) + { + Handle_Load_Double (state, instr); + break; + } + if (BITS (4, 7) == 0xF) + { + Handle_Store_Double (state, instr); + break; + } +#endif + dest = ~DPRegRHS; + WRITEDEST (dest); + break; + + case 0x1f: /* MVNS reg */ +#ifdef MODET + if ((BITS (4, 7) & 0x9) == 0x9) + /* LDR immediate offset, write-back, up, pre indexed. */ + LHPREUPWB (); + /* Continue instruction decoding. */ +#endif + dest = ~DPSRegRHS; + WRITESDEST (dest); + break; + + + /* Data Processing Immediate RHS Instructions. */ + + case 0x20: /* AND immed */ + dest = LHS & DPImmRHS; + WRITEDEST (dest); + break; + + case 0x21: /* ANDS immed */ + DPSImmRHS; + dest = LHS & rhs; + WRITESDEST (dest); + break; + + case 0x22: /* EOR immed */ + dest = LHS ^ DPImmRHS; + WRITEDEST (dest); + break; + + case 0x23: /* EORS immed */ + DPSImmRHS; + dest = LHS ^ rhs; + WRITESDEST (dest); + break; + + case 0x24: /* SUB immed */ + dest = LHS - DPImmRHS; + WRITEDEST (dest); + break; + + case 0x25: /* SUBS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs; + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x26: /* RSB immed */ + dest = DPImmRHS - LHS; + WRITEDEST (dest); + break; + + case 0x27: /* RSBS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = rhs - lhs; + + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x28: /* ADD immed */ + dest = LHS + DPImmRHS; + WRITEDEST (dest); + break; + + case 0x29: /* ADDS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2a: /* ADC immed */ + dest = LHS + DPImmRHS + CFLAG; + WRITEDEST (dest); + break; + + case 0x2b: /* ADCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs + CFLAG; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2c: /* SBC immed */ + dest = LHS - DPImmRHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x2d: /* SBCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs - !CFLAG; + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x2e: /* RSC immed */ + dest = DPImmRHS - LHS - !CFLAG; + WRITEDEST (dest); + break; + + case 0x2f: /* RSCS immed */ + lhs = LHS; + rhs = DPImmRHS; + dest = rhs - lhs - !CFLAG; + if ((rhs >= lhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, rhs, lhs, dest); + ARMul_SubOverflow (state, rhs, lhs, dest); + } + else + { + CLEARC; + CLEARV; + } + WRITESDEST (dest); + break; + + case 0x30: /* TST immed */ + UNDEF_Test; + break; + + case 0x31: /* TSTP immed */ + if (DESTReg == 15) + { + /* TSTP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS & DPImmRHS; + SETR15PSR (temp); +#endif + } + else + { + /* TST immed. */ + DPSImmRHS; + dest = LHS & rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x32: /* TEQ immed and MSR immed to CPSR */ + if (DESTReg == 15) + /* MSR immed to CPSR. */ + ARMul_FixCPSR (state, instr, DPImmRHS); + else + UNDEF_Test; + break; + + case 0x33: /* TEQP immed */ + if (DESTReg == 15) + { + /* TEQP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS ^ DPImmRHS; + SETR15PSR (temp); +#endif + } + else + { + DPSImmRHS; /* TEQ immed */ + dest = LHS ^ rhs; + ARMul_NegZero (state, dest); + } + break; + + case 0x34: /* CMP immed */ + UNDEF_Test; + break; + + case 0x35: /* CMPP immed */ + if (DESTReg == 15) + { + /* CMPP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS - DPImmRHS; + SETR15PSR (temp); +#endif + break; + } + else + { + /* CMP immed. */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs - rhs; + ARMul_NegZero (state, dest); + + if ((lhs >= rhs) || ((rhs | lhs) >> 31)) + { + ARMul_SubCarry (state, lhs, rhs, dest); + ARMul_SubOverflow (state, lhs, rhs, dest); + } + else + { + CLEARC; + CLEARV; + } + } + break; + + case 0x36: /* CMN immed and MSR immed to SPSR */ + if (DESTReg == 15) + ARMul_FixSPSR (state, instr, DPImmRHS); + else + UNDEF_Test; + break; + + case 0x37: /* CMNP immed. */ + if (DESTReg == 15) + { + /* CMNP immed. */ +#ifdef MODE32 + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); +#else + temp = LHS + DPImmRHS; + SETR15PSR (temp); +#endif + break; + } + else + { + /* CMN immed. */ + lhs = LHS; + rhs = DPImmRHS; + dest = lhs + rhs; + ASSIGNZ (dest == 0); + if ((lhs | rhs) >> 30) + { + /* Possible C,V,N to set. */ + ASSIGNN (NEG (dest)); + ARMul_AddCarry (state, lhs, rhs, dest); + ARMul_AddOverflow (state, lhs, rhs, dest); + } + else + { + CLEARN; + CLEARC; + CLEARV; + } + } + break; + + case 0x38: /* ORR immed. */ + dest = LHS | DPImmRHS; + WRITEDEST (dest); + break; + + case 0x39: /* ORRS immed. */ + DPSImmRHS; + dest = LHS | rhs; + WRITESDEST (dest); + break; + + case 0x3a: /* MOV immed. */ + dest = DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3b: /* MOVS immed. */ + DPSImmRHS; + WRITESDEST (rhs); + break; + + case 0x3c: /* BIC immed. */ + dest = LHS & ~DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3d: /* BICS immed. */ + DPSImmRHS; + dest = LHS & ~rhs; + WRITESDEST (dest); + break; + + case 0x3e: /* MVN immed. */ + dest = ~DPImmRHS; + WRITEDEST (dest); + break; + + case 0x3f: /* MVNS immed. */ + DPSImmRHS; + WRITESDEST (~rhs); + break; + + + /* Single Data Transfer Immediate RHS Instructions. */ + + case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (LoadWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + temp = lhs - LSImmRHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + break; + + case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */ + lhs = LHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs - LSImmRHS; + break; + + case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs - LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (LoadWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */ + lhs = LHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs + LSImmRHS; + break; + + case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + lhs = LHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = lhs + LSImmRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + + case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ + (void) StoreWord (state, instr, LHS - LSImmRHS); + break; + + case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */ + (void) LoadWord (state, instr, LHS - LSImmRHS); + break; + + case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */ + (void) StoreByte (state, instr, LHS - LSImmRHS); + break; + + case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */ + (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED); + break; + + case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS - LSImmRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */ + (void) StoreWord (state, instr, LHS + LSImmRHS); + break; + + case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */ + (void) LoadWord (state, instr, LHS + LSImmRHS); + break; + + case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */ + (void) StoreByte (state, instr, LHS + LSImmRHS); + break; + + case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */ + (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED); + break; + + case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */ + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + temp = LHS + LSImmRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + + /* Single Data Transfer Register RHS Instructions. */ + + case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + break; + + case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + break; + + case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + break; + + case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + break; + + case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs - LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs - LSRegRHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + break; + + case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + break; + + case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreWord (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + state->NtransSig = LOW; + if (LoadWord (state, instr, lhs)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + break; + + case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + break; + + case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + state->NtransSig = LOW; + if (StoreByte (state, instr, lhs)) + LSBase = lhs + LSRegRHS; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + lhs = LHS; + temp = lhs + LSRegRHS; + state->NtransSig = LOW; + if (LoadByte (state, instr, lhs, LUNSIGNED)) + LSBase = temp; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + break; + + + case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreWord (state, instr, LHS - LSRegRHS); + break; + + case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadWord (state, instr, LHS - LSRegRHS); + break; + + case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreByte (state, instr, LHS - LSRegRHS); + break; + + case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED); + break; + + case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS - LSRegRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreWord (state, instr, LHS + LSRegRHS); + break; + + case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadWord (state, instr, LHS + LSRegRHS); + break; + + case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (StoreWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (LoadWord (state, instr, temp)) + LSBase = temp; + break; + + case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { +#ifdef MODE32 + if (state->is_v6 + && handle_v6_insn (state, instr)) + break; +#endif + ARMul_UndefInstr (state, instr); + break; + } + (void) StoreByte (state, instr, LHS + LSRegRHS); + break; + + case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED); + break; + + case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (StoreByte (state, instr, temp)) + LSBase = temp; + break; + + case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */ + if (BIT (4)) + { + /* Check for the special breakpoint opcode. + This value should correspond to the value defined + as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */ + if (BITS (0, 19) == 0xfdefe) + { + if (!ARMul_OSHandleSWI (state, SWI_Breakpoint)) + ARMul_Abort (state, ARMul_SWIV); + } + else + ARMul_UndefInstr (state, instr); + break; + } + UNDEF_LSRBaseEQOffWb; + UNDEF_LSRBaseEQDestWb; + UNDEF_LSRPCBaseWb; + UNDEF_LSRPCOffWb; + temp = LHS + LSRegRHS; + if (LoadByte (state, instr, temp, LUNSIGNED)) + LSBase = temp; + break; + + + /* Multiple Data Transfer Instructions. */ + + case 0x80: /* Store, No WriteBack, Post Dec. */ + STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x81: /* Load, No WriteBack, Post Dec. */ + LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x82: /* Store, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + STOREMULT (instr, temp + 4L, temp); + break; + + case 0x83: /* Load, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + LOADMULT (instr, temp + 4L, temp); + break; + + case 0x84: /* Store, Flags, No WriteBack, Post Dec. */ + STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x85: /* Load, Flags, No WriteBack, Post Dec. */ + LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L); + break; + + case 0x86: /* Store, Flags, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + STORESMULT (instr, temp + 4L, temp); + break; + + case 0x87: /* Load, Flags, WriteBack, Post Dec. */ + temp = LSBase - LSMNumRegs; + LOADSMULT (instr, temp + 4L, temp); + break; + + case 0x88: /* Store, No WriteBack, Post Inc. */ + STOREMULT (instr, LSBase, 0L); + break; + + case 0x89: /* Load, No WriteBack, Post Inc. */ + LOADMULT (instr, LSBase, 0L); + break; + + case 0x8a: /* Store, WriteBack, Post Inc. */ + temp = LSBase; + STOREMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8b: /* Load, WriteBack, Post Inc. */ + temp = LSBase; + LOADMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */ + STORESMULT (instr, LSBase, 0L); + break; + + case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */ + LOADSMULT (instr, LSBase, 0L); + break; + + case 0x8e: /* Store, Flags, WriteBack, Post Inc. */ + temp = LSBase; + STORESMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x8f: /* Load, Flags, WriteBack, Post Inc. */ + temp = LSBase; + LOADSMULT (instr, temp, temp + LSMNumRegs); + break; + + case 0x90: /* Store, No WriteBack, Pre Dec. */ + STOREMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x91: /* Load, No WriteBack, Pre Dec. */ + LOADMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x92: /* Store, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + STOREMULT (instr, temp, temp); + break; + + case 0x93: /* Load, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + LOADMULT (instr, temp, temp); + break; + + case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */ + STORESMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */ + LOADSMULT (instr, LSBase - LSMNumRegs, 0L); + break; + + case 0x96: /* Store, Flags, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + STORESMULT (instr, temp, temp); + break; + + case 0x97: /* Load, Flags, WriteBack, Pre Dec. */ + temp = LSBase - LSMNumRegs; + LOADSMULT (instr, temp, temp); + break; + + case 0x98: /* Store, No WriteBack, Pre Inc. */ + STOREMULT (instr, LSBase + 4L, 0L); + break; + + case 0x99: /* Load, No WriteBack, Pre Inc. */ + LOADMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9a: /* Store, WriteBack, Pre Inc. */ + temp = LSBase; + STOREMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9b: /* Load, WriteBack, Pre Inc. */ + temp = LSBase; + LOADMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */ + STORESMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */ + LOADSMULT (instr, LSBase + 4L, 0L); + break; + + case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */ + temp = LSBase; + STORESMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */ + temp = LSBase; + LOADSMULT (instr, temp + 4L, temp + LSMNumRegs); + break; + + + /* Branch forward. */ + case 0xa0: + case 0xa1: + case 0xa2: + case 0xa3: + case 0xa4: + case 0xa5: + case 0xa6: + case 0xa7: + state->Reg[15] = pc + 8 + POSBRANCH; + FLUSHPIPE; + break; + + + /* Branch backward. */ + case 0xa8: + case 0xa9: + case 0xaa: + case 0xab: + case 0xac: + case 0xad: + case 0xae: + case 0xaf: + state->Reg[15] = pc + 8 + NEGBRANCH; + FLUSHPIPE; + break; + + + /* Branch and Link forward. */ + case 0xb0: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + /* Put PC into Link. */ +#ifdef MODE32 + state->Reg[14] = pc + 4; +#else + state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; +#endif + state->Reg[15] = pc + 8 + POSBRANCH; + FLUSHPIPE; + break; + + + /* Branch and Link backward. */ + case 0xb8: + case 0xb9: + case 0xba: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + case 0xbf: + /* Put PC into Link. */ +#ifdef MODE32 + state->Reg[14] = pc + 4; +#else + state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE; +#endif + state->Reg[15] = pc + 8 + NEGBRANCH; + FLUSHPIPE; + break; + + + /* Co-Processor Data Transfers. */ + case 0xc4: + if (state->is_v5) + { + /* Reading from R15 is UNPREDICTABLE. */ + if (BITS (12, 15) == 15 || BITS (16, 19) == 15) + ARMul_UndefInstr (state, instr); + /* Is access to coprocessor 0 allowed ? */ + else if (! CP_ACCESS_ALLOWED (state, CPNum)) + ARMul_UndefInstr (state, instr); + /* Special treatment for XScale coprocessors. */ + else if (state->is_XScale) + { + /* Only opcode 0 is supported. */ + if (BITS (4, 7) != 0x00) + ARMul_UndefInstr (state, instr); + /* Only coporcessor 0 is supported. */ + else if (CPNum != 0x00) + ARMul_UndefInstr (state, instr); + /* Only accumulator 0 is supported. */ + else if (BITS (0, 3) != 0x00) + ARMul_UndefInstr (state, instr); + else + { + /* XScale MAR insn. Move two registers into accumulator. */ + state->Accumulator = state->Reg[BITS (12, 15)]; + state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32; + } + } + else + /* FIXME: Not sure what to do for other v5 processors. */ + ARMul_UndefInstr (state, instr); + break; + } + /* Drop through. */ + + case 0xc0: /* Store , No WriteBack , Post Dec. */ + ARMul_STC (state, instr, LHS); + break; + + case 0xc5: + if (state->is_v5) + { + /* Writes to R15 are UNPREDICATABLE. */ + if (DESTReg == 15 || LHSReg == 15) + ARMul_UndefInstr (state, instr); + /* Is access to the coprocessor allowed ? */ + else if (! CP_ACCESS_ALLOWED (state, CPNum)) + ARMul_UndefInstr (state, instr); + /* Special handling for XScale coprcoessors. */ + else if (state->is_XScale) + { + /* Only opcode 0 is supported. */ + if (BITS (4, 7) != 0x00) + ARMul_UndefInstr (state, instr); + /* Only coprocessor 0 is supported. */ + else if (CPNum != 0x00) + ARMul_UndefInstr (state, instr); + /* Only accumulator 0 is supported. */ + else if (BITS (0, 3) != 0x00) + ARMul_UndefInstr (state, instr); + else + { + /* XScale MRA insn. Move accumulator into two registers. */ + ARMword t1 = (state->Accumulator >> 32) & 255; + + if (t1 & 128) + t1 -= 256; + + state->Reg[BITS (12, 15)] = state->Accumulator; + state->Reg[BITS (16, 19)] = t1; + break; + } + } + else + /* FIXME: Not sure what to do for other v5 processors. */ + ARMul_UndefInstr (state, instr); + break; + } + /* Drop through. */ + + case 0xc1: /* Load , No WriteBack , Post Dec. */ + ARMul_LDC (state, instr, LHS); + break; + + case 0xc2: + case 0xc6: /* Store , WriteBack , Post Dec. */ + lhs = LHS; + state->Base = lhs - LSCOff; + ARMul_STC (state, instr, lhs); + break; + + case 0xc3: + case 0xc7: /* Load , WriteBack , Post Dec. */ + lhs = LHS; + state->Base = lhs - LSCOff; + ARMul_LDC (state, instr, lhs); + break; + + case 0xc8: + case 0xcc: /* Store , No WriteBack , Post Inc. */ + ARMul_STC (state, instr, LHS); + break; + + case 0xc9: + case 0xcd: /* Load , No WriteBack , Post Inc. */ + ARMul_LDC (state, instr, LHS); + break; + + case 0xca: + case 0xce: /* Store , WriteBack , Post Inc. */ + lhs = LHS; + state->Base = lhs + LSCOff; + ARMul_STC (state, instr, LHS); + break; + + case 0xcb: + case 0xcf: /* Load , WriteBack , Post Inc. */ + lhs = LHS; + state->Base = lhs + LSCOff; + ARMul_LDC (state, instr, LHS); + break; + + case 0xd0: + case 0xd4: /* Store , No WriteBack , Pre Dec. */ + ARMul_STC (state, instr, LHS - LSCOff); + break; + + case 0xd1: + case 0xd5: /* Load , No WriteBack , Pre Dec. */ + ARMul_LDC (state, instr, LHS - LSCOff); + break; + + case 0xd2: + case 0xd6: /* Store , WriteBack , Pre Dec. */ + lhs = LHS - LSCOff; + state->Base = lhs; + ARMul_STC (state, instr, lhs); + break; + + case 0xd3: + case 0xd7: /* Load , WriteBack , Pre Dec. */ + lhs = LHS - LSCOff; + state->Base = lhs; + ARMul_LDC (state, instr, lhs); + break; + + case 0xd8: + case 0xdc: /* Store , No WriteBack , Pre Inc. */ + ARMul_STC (state, instr, LHS + LSCOff); + break; + + case 0xd9: + case 0xdd: /* Load , No WriteBack , Pre Inc. */ + ARMul_LDC (state, instr, LHS + LSCOff); + break; + + case 0xda: + case 0xde: /* Store , WriteBack , Pre Inc. */ + lhs = LHS + LSCOff; + state->Base = lhs; + ARMul_STC (state, instr, lhs); + break; + + case 0xdb: + case 0xdf: /* Load , WriteBack , Pre Inc. */ + lhs = LHS + LSCOff; + state->Base = lhs; + ARMul_LDC (state, instr, lhs); + break; + + + /* Co-Processor Register Transfers (MCR) and Data Ops. */ + + case 0xe2: + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + break; + } + if (state->is_XScale) + switch (BITS (18, 19)) + { + case 0x0: + if (BITS (4, 11) == 1 && BITS (16, 17) == 0) + { + /* XScale MIA instruction. Signed multiplication of + two 32 bit values and addition to 40 bit accumulator. */ + ARMsdword Rm = state->Reg[MULLHSReg]; + ARMsdword Rs = state->Reg[MULACCReg]; + + if (Rm & (1 << 31)) + Rm -= 1ULL << 32; + if (Rs & (1 << 31)) + Rs -= 1ULL << 32; + state->Accumulator += Rm * Rs; + goto donext; + } + break; + + case 0x2: + if (BITS (4, 11) == 1 && BITS (16, 17) == 0) + { + /* XScale MIAPH instruction. */ + ARMword t1 = state->Reg[MULLHSReg] >> 16; + ARMword t2 = state->Reg[MULACCReg] >> 16; + ARMword t3 = state->Reg[MULLHSReg] & 0xffff; + ARMword t4 = state->Reg[MULACCReg] & 0xffff; + ARMsdword t5; + + if (t1 & (1 << 15)) + t1 -= 1 << 16; + if (t2 & (1 << 15)) + t2 -= 1 << 16; + if (t3 & (1 << 15)) + t3 -= 1 << 16; + if (t4 & (1 << 15)) + t4 -= 1 << 16; + t1 *= t2; + t5 = t1; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + t3 *= t4; + t5 = t3; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + goto donext; + } + break; + + case 0x3: + if (BITS (4, 11) == 1) + { + /* XScale MIAxy instruction. */ + ARMword t1; + ARMword t2; + ARMsdword t5; + + if (BIT (17)) + t1 = state->Reg[MULLHSReg] >> 16; + else + t1 = state->Reg[MULLHSReg] & 0xffff; + + if (BIT (16)) + t2 = state->Reg[MULACCReg] >> 16; + else + t2 = state->Reg[MULACCReg] & 0xffff; + + if (t1 & (1 << 15)) + t1 -= 1 << 16; + if (t2 & (1 << 15)) + t2 -= 1 << 16; + t1 *= t2; + t5 = t1; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + goto donext; + } + break; + + default: + break; + } + /* Drop through. */ + + case 0xe0: + case 0xe4: + case 0xe6: + case 0xe8: + case 0xea: + case 0xec: + case 0xee: + if (BIT (4)) + { + /* MCR. */ + if (DESTReg == 15) + { + UNDEF_MCRPC; +#ifdef MODE32 + ARMul_MCR (state, instr, state->Reg[15] + isize); +#else + ARMul_MCR (state, instr, ECC | ER15INT | EMODE | + ((state->Reg[15] + isize) & R15PCBITS)); +#endif + } + else + ARMul_MCR (state, instr, DEST); + } + else + /* CDP Part 1. */ + ARMul_CDP (state, instr); + break; + + + /* Co-Processor Register Transfers (MRC) and Data Ops. */ + case 0xe1: + case 0xe3: + case 0xe5: + case 0xe7: + case 0xe9: + case 0xeb: + case 0xed: + case 0xef: + if (BIT (4)) + { + /* MRC */ + temp = ARMul_MRC (state, instr); + if (DESTReg == 15) + { + ASSIGNN ((temp & NBIT) != 0); + ASSIGNZ ((temp & ZBIT) != 0); + ASSIGNC ((temp & CBIT) != 0); + ASSIGNV ((temp & VBIT) != 0); + } + else + DEST = temp; + } + else + /* CDP Part 2. */ + ARMul_CDP (state, instr); + break; + + + /* SWI instruction. */ + case 0xf0: + case 0xf1: + case 0xf2: + case 0xf3: + case 0xf4: + case 0xf5: + case 0xf6: + case 0xf7: + case 0xf8: + case 0xf9: + case 0xfa: + case 0xfb: + case 0xfc: + case 0xfd: + case 0xfe: + case 0xff: + if (instr == ARMul_ABORTWORD && state->AbortAddr == pc) + { + /* A prefetch abort. */ + XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc); + ARMul_Abort (state, ARMul_PrefetchAbortV); + break; + } + + if (!ARMul_OSHandleSWI (state, BITS (0, 23))) + ARMul_Abort (state, ARMul_SWIV); + + break; + } + } + +#ifdef MODET + donext: +#endif + +#ifdef NEED_UI_LOOP_HOOK + if (deprecated_ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) + { + ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; + deprecated_ui_loop_hook (0); + } +#endif /* NEED_UI_LOOP_HOOK */ + + if (state->Emulate == ONCE) + state->Emulate = STOP; + /* If we have changed mode, allow the PC to advance before stopping. */ + else if (state->Emulate == CHANGEMODE) + continue; + else if (state->Emulate != RUN) + break; + } + while (!stop_simulator); + + state->decoded = decoded; + state->loaded = loaded; + state->pc = pc; + + return pc; +} + +/* This routine evaluates most Data Processing register RHS's with the S + bit clear. It is intended to be called from the macro DPRegRHS, which + filters the common case of an unshifted register with in line code. */ + +static ARMword +GetDPRegRHS (ARMul_State * state, ARMword instr) +{ + ARMword shamt, base; + + base = RHSReg; + if (BIT (4)) + { + /* Shift amount in a register. */ + UNDEF_Shift; + INCPC; +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + ARMul_Icycles (state, 1, 0L); + shamt = state->Reg[BITS (8, 11)] & 0xff; + switch ((int) BITS (5, 6)) + { + case LSL: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return (0); + else + return (base << shamt); + case LSR: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return (base); + else if (shamt >= 32) + return ((ARMword) ((ARMsword) base >> 31L)); + else + return ((ARMword) ((ARMsword) base >> (int) shamt)); + case ROR: + shamt &= 0x1f; + if (shamt == 0) + return (base); + else + return ((base << (32 - shamt)) | (base >> shamt)); + } + } + else + { + /* Shift amount is a constant. */ +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + shamt = BITS (7, 11); + switch ((int) BITS (5, 6)) + { + case LSL: + return (base << shamt); + case LSR: + if (shamt == 0) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return ((ARMword) ((ARMsword) base >> 31L)); + else + return ((ARMword) ((ARMsword) base >> (int) shamt)); + case ROR: + if (shamt == 0) + /* It's an RRX. */ + return ((base >> 1) | (CFLAG << 31)); + else + return ((base << (32 - shamt)) | (base >> shamt)); + } + } + + return 0; +} + +/* This routine evaluates most Logical Data Processing register RHS's + with the S bit set. It is intended to be called from the macro + DPSRegRHS, which filters the common case of an unshifted register + with in line code. */ + +static ARMword +GetDPSRegRHS (ARMul_State * state, ARMword instr) +{ + ARMword shamt, base; + + base = RHSReg; + if (BIT (4)) + { + /* Shift amount in a register. */ + UNDEF_Shift; + INCPC; +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + ARMul_Icycles (state, 1, 0L); + shamt = state->Reg[BITS (8, 11)] & 0xff; + switch ((int) BITS (5, 6)) + { + case LSL: + if (shamt == 0) + return (base); + else if (shamt == 32) + { + ASSIGNC (base & 1); + return (0); + } + else if (shamt > 32) + { + CLEARC; + return (0); + } + else + { + ASSIGNC ((base >> (32 - shamt)) & 1); + return (base << shamt); + } + case LSR: + if (shamt == 0) + return (base); + else if (shamt == 32) + { + ASSIGNC (base >> 31); + return (0); + } + else if (shamt > 32) + { + CLEARC; + return (0); + } + else + { + ASSIGNC ((base >> (shamt - 1)) & 1); + return (base >> shamt); + } + case ASR: + if (shamt == 0) + return (base); + else if (shamt >= 32) + { + ASSIGNC (base >> 31L); + return ((ARMword) ((ARMsword) base >> 31L)); + } + else + { + ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1); + return ((ARMword) ((ARMsword) base >> (int) shamt)); + } + case ROR: + if (shamt == 0) + return (base); + shamt &= 0x1f; + if (shamt == 0) + { + ASSIGNC (base >> 31); + return (base); + } + else + { + ASSIGNC ((base >> (shamt - 1)) & 1); + return ((base << (32 - shamt)) | (base >> shamt)); + } + } + } + else + { + /* Shift amount is a constant. */ +#ifndef MODE32 + if (base == 15) + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + shamt = BITS (7, 11); + + switch ((int) BITS (5, 6)) + { + case LSL: + ASSIGNC ((base >> (32 - shamt)) & 1); + return (base << shamt); + case LSR: + if (shamt == 0) + { + ASSIGNC (base >> 31); + return (0); + } + else + { + ASSIGNC ((base >> (shamt - 1)) & 1); + return (base >> shamt); + } + case ASR: + if (shamt == 0) + { + ASSIGNC (base >> 31L); + return ((ARMword) ((ARMsword) base >> 31L)); + } + else + { + ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1); + return ((ARMword) ((ARMsword) base >> (int) shamt)); + } + case ROR: + if (shamt == 0) + { + /* It's an RRX. */ + shamt = CFLAG; + ASSIGNC (base & 1); + return ((base >> 1) | (shamt << 31)); + } + else + { + ASSIGNC ((base >> (shamt - 1)) & 1); + return ((base << (32 - shamt)) | (base >> shamt)); + } + } + } + + return 0; +} + +/* This routine handles writes to register 15 when the S bit is not set. */ + +static void +WriteR15 (ARMul_State * state, ARMword src) +{ + /* The ARM documentation states that the two least significant bits + are discarded when setting PC, except in the cases handled by + WriteR15Branch() below. It's probably an oversight: in THUMB + mode, the second least significant bit should probably not be + discarded. */ +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; + +#ifdef MODE32 + state->Reg[15] = src & PCBITS; +#else + state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE; + ARMul_R15Altered (state); +#endif + + FLUSHPIPE; +} + +/* This routine handles writes to register 15 when the S bit is set. */ + +static void +WriteSR15 (ARMul_State * state, ARMword src) +{ +#ifdef MODE32 + if (state->Bank > 0) + { + state->Cpsr = state->Spsr[state->Bank]; + ARMul_CPSRAltered (state); + } +#ifdef MODET + if (TFLAG) + src &= 0xfffffffe; + else +#endif + src &= 0xfffffffc; + state->Reg[15] = src & PCBITS; +#else +#ifdef MODET + if (TFLAG) + /* ARMul_R15Altered would have to support it. */ + abort (); + else +#endif + src &= 0xfffffffc; + + if (state->Bank == USERBANK) + state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; + else + state->Reg[15] = src; + + ARMul_R15Altered (state); +#endif + FLUSHPIPE; +} + +/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM + will switch to Thumb mode if the least significant bit is set. */ + +static void +WriteR15Branch (ARMul_State * state, ARMword src) +{ +#ifdef MODET + if (src & 1) + { + /* Thumb bit. */ + SETT; + state->Reg[15] = src & 0xfffffffe; + } + else + { + CLEART; + state->Reg[15] = src & 0xfffffffc; + } + FLUSHPIPE; +#else + WriteR15 (state, src); +#endif +} + +/* This routine evaluates most Load and Store register RHS's. It is + intended to be called from the macro LSRegRHS, which filters the + common case of an unshifted register with in line code. */ + +static ARMword +GetLSRegRHS (ARMul_State * state, ARMword instr) +{ + ARMword shamt, base; + + base = RHSReg; +#ifndef MODE32 + if (base == 15) + /* Now forbidden, but ... */ + base = ECC | ER15INT | R15PC | EMODE; + else +#endif + base = state->Reg[base]; + + shamt = BITS (7, 11); + switch ((int) BITS (5, 6)) + { + case LSL: + return (base << shamt); + case LSR: + if (shamt == 0) + return (0); + else + return (base >> shamt); + case ASR: + if (shamt == 0) + return ((ARMword) ((ARMsword) base >> 31L)); + else + return ((ARMword) ((ARMsword) base >> (int) shamt)); + case ROR: + if (shamt == 0) + /* It's an RRX. */ + return ((base >> 1) | (CFLAG << 31)); + else + return ((base << (32 - shamt)) | (base >> shamt)); + default: + break; + } + return 0; +} + +/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */ + +static ARMword +GetLS7RHS (ARMul_State * state, ARMword instr) +{ + if (BIT (22) == 0) + { + /* Register. */ +#ifndef MODE32 + if (RHSReg == 15) + /* Now forbidden, but ... */ + return ECC | ER15INT | R15PC | EMODE; +#endif + return state->Reg[RHSReg]; + } + + /* Immediate. */ + return BITS (0, 3) | (BITS (8, 11) << 4); +} + +/* This function does the work of loading a word for a LDR instruction. */ + +static unsigned +LoadWord (ARMul_State * state, ARMword instr, ARMword address) +{ + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + + dest = ARMul_LoadWordN (state, address); + + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + if (address & 3) + dest = ARMul_Align (state, address, dest); + WRITEDESTB (dest); + ARMul_Icycles (state, 1, 0L); + + return (DESTReg != LHSReg); +} + +#ifdef MODET +/* This function does the work of loading a halfword. */ + +static unsigned +LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address, + int signextend) +{ + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + dest = ARMul_LoadHalfWord (state, address); + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + UNDEF_LSRBPC; + if (signextend) + if (dest & 1 << (16 - 1)) + dest = (dest & ((1 << 16) - 1)) - (1 << 16); + + WRITEDEST (dest); + ARMul_Icycles (state, 1, 0L); + return (DESTReg != LHSReg); +} + +#endif /* MODET */ + +/* This function does the work of loading a byte for a LDRB instruction. */ + +static unsigned +LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) +{ + ARMword dest; + + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + dest = ARMul_LoadByte (state, address); + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + UNDEF_LSRBPC; + if (signextend) + if (dest & 1 << (8 - 1)) + dest = (dest & ((1 << 8) - 1)) - (1 << 8); + + WRITEDEST (dest); + ARMul_Icycles (state, 1, 0L); + + return (DESTReg != LHSReg); +} + +/* This function does the work of loading two words for a LDRD instruction. */ + +static void +Handle_Load_Double (ARMul_State * state, ARMword instr) +{ + ARMword dest_reg; + ARMword addr_reg; + ARMword write_back = BIT (21); + ARMword immediate = BIT (22); + ARMword add_to_base = BIT (23); + ARMword pre_indexed = BIT (24); + ARMword offset; + ARMword addr; + ARMword sum; + ARMword base; + ARMword value1; + ARMword value2; + + BUSUSEDINCPCS; + + /* If the writeback bit is set, the pre-index bit must be clear. */ + if (write_back && ! pre_indexed) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the base address register. */ + addr_reg = LHSReg; + + /* Extract the destination register and check it. */ + dest_reg = DESTReg; + + /* Destination register must be even. */ + if ((dest_reg & 1) + /* Destination register cannot be LR. */ + || (dest_reg == 14)) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Compute the base address. */ + base = state->Reg[addr_reg]; + + /* Compute the offset. */ + offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg]; + + /* Compute the sum of the two. */ + if (add_to_base) + sum = base + offset; + else + sum = base - offset; + + /* If this is a pre-indexed mode use the sum. */ + if (pre_indexed) + addr = sum; + else + addr = base; + + /* The address must be aligned on a 8 byte boundary. */ + if (addr & 0x7) + { +#ifdef ABORTS + ARMul_DATAABORT (addr); +#else + ARMul_UndefInstr (state, instr); +#endif + return; + } + + /* For pre indexed or post indexed addressing modes, + check that the destination registers do not overlap + the address registers. */ + if ((! pre_indexed || write_back) + && ( addr_reg == dest_reg + || addr_reg == dest_reg + 1)) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Load the words. */ + value1 = ARMul_LoadWordN (state, addr); + value2 = ARMul_LoadWordN (state, addr + 4); + + /* Check for data aborts. */ + if (state->Aborted) + { + TAKEABORT; + return; + } + + ARMul_Icycles (state, 2, 0L); + + /* Store the values. */ + state->Reg[dest_reg] = value1; + state->Reg[dest_reg + 1] = value2; + + /* Do the post addressing and writeback. */ + if (! pre_indexed) + addr = sum; + + if (! pre_indexed || write_back) + state->Reg[addr_reg] = addr; +} + +/* This function does the work of storing two words for a STRD instruction. */ + +static void +Handle_Store_Double (ARMul_State * state, ARMword instr) +{ + ARMword src_reg; + ARMword addr_reg; + ARMword write_back = BIT (21); + ARMword immediate = BIT (22); + ARMword add_to_base = BIT (23); + ARMword pre_indexed = BIT (24); + ARMword offset; + ARMword addr; + ARMword sum; + ARMword base; + + BUSUSEDINCPCS; + + /* If the writeback bit is set, the pre-index bit must be clear. */ + if (write_back && ! pre_indexed) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the base address register. */ + addr_reg = LHSReg; + + /* Base register cannot be PC. */ + if (addr_reg == 15) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Extract the source register. */ + src_reg = DESTReg; + + /* Source register must be even. */ + if (src_reg & 1) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Compute the base address. */ + base = state->Reg[addr_reg]; + + /* Compute the offset. */ + offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg]; + + /* Compute the sum of the two. */ + if (add_to_base) + sum = base + offset; + else + sum = base - offset; + + /* If this is a pre-indexed mode use the sum. */ + if (pre_indexed) + addr = sum; + else + addr = base; + + /* The address must be aligned on a 8 byte boundary. */ + if (addr & 0x7) + { +#ifdef ABORTS + ARMul_DATAABORT (addr); +#else + ARMul_UndefInstr (state, instr); +#endif + return; + } + + /* For pre indexed or post indexed addressing modes, + check that the destination registers do not overlap + the address registers. */ + if ((! pre_indexed || write_back) + && ( addr_reg == src_reg + || addr_reg == src_reg + 1)) + { + ARMul_UndefInstr (state, instr); + return; + } + + /* Load the words. */ + ARMul_StoreWordN (state, addr, state->Reg[src_reg]); + ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]); + + if (state->Aborted) + { + TAKEABORT; + return; + } + + /* Do the post addressing and writeback. */ + if (! pre_indexed) + addr = sum; + + if (! pre_indexed || write_back) + state->Reg[addr_reg] = addr; +} + +/* This function does the work of storing a word from a STR instruction. */ + +static unsigned +StoreWord (ARMul_State * state, ARMword instr, ARMword address) +{ + BUSUSEDINCPCN; +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif +#ifdef MODE32 + ARMul_StoreWordN (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) + { + INTERNALABORT (address); + (void) ARMul_LoadWordN (state, address); + } + else + ARMul_StoreWordN (state, address, DEST); +#endif + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + return TRUE; +} + +#ifdef MODET +/* This function does the work of storing a byte for a STRH instruction. */ + +static unsigned +StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) +{ + BUSUSEDINCPCN; + +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif + +#ifdef MODE32 + ARMul_StoreHalfWord (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) + { + INTERNALABORT (address); + (void) ARMul_LoadHalfWord (state, address); + } + else + ARMul_StoreHalfWord (state, address, DEST); +#endif + + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + return TRUE; +} + +#endif /* MODET */ + +/* This function does the work of storing a byte for a STRB instruction. */ + +static unsigned +StoreByte (ARMul_State * state, ARMword instr, ARMword address) +{ + BUSUSEDINCPCN; +#ifndef MODE32 + if (DESTReg == 15) + state->Reg[15] = ECC | ER15INT | R15PC | EMODE; +#endif +#ifdef MODE32 + ARMul_StoreByte (state, address, DEST); +#else + if (VECTORACCESS (address) || ADDREXCEPT (address)) + { + INTERNALABORT (address); + (void) ARMul_LoadByte (state, address); + } + else + ARMul_StoreByte (state, address, DEST); +#endif + if (state->Aborted) + { + TAKEABORT; + return state->lateabtSig; + } + UNDEF_LSRBPC; + return TRUE; +} + +/* This function does the work of loading the registers listed in an LDM + instruction, when the S bit is clear. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + +static void +LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) +{ + ARMword dest, temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + BUSUSEDINCPCS; +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp++) + ; + + dest = ARMul_LoadWordN (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp++] = dest; + else if (!state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + + /* S cycles from here on. */ + for (; temp < 16; temp ++) + if (BIT (temp)) + { + /* Load this register. */ + address += 4; + dest = ARMul_LoadWordS (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp] = dest; + else if (!state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + } + + if (BIT (15) && !state->Aborted) + /* PC is in the reg list. */ + WriteR15Branch (state, PC); + + /* To write back the final register. */ + ARMul_Icycles (state, 1, 0L); + + if (state->Aborted) + { + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + TAKEABORT; + } +} + +/* This function does the work of loading the registers listed in an LDM + instruction, when the S bit is set. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + +static void +LoadSMult (ARMul_State * state, + ARMword instr, + ARMword address, + ARMword WBBase) +{ + ARMword dest, temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + + BUSUSEDINCPCS; + +#ifndef MODE32 + if (ADDREXCEPT (address)) + INTERNALABORT (address); +#endif + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + if (!BIT (15) && state->Bank != USERBANK) + { + /* Temporary reg bank switch. */ + (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); + UNDEF_LSMUserBankWb; + } + + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp ++) + ; + + dest = ARMul_LoadWordN (state, address); + + if (!state->abortSig) + state->Reg[temp++] = dest; + else if (!state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) + { + /* Load this register. */ + address += 4; + dest = ARMul_LoadWordS (state, address); + + if (!state->abortSig && !state->Aborted) + state->Reg[temp] = dest; + else if (!state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + } + + if (BIT (15) && !state->Aborted) + { + /* PC is in the reg list. */ +#ifdef MODE32 + if (state->Mode != USER26MODE && state->Mode != USER32MODE) + { + state->Cpsr = GETSPSR (state->Bank); + ARMul_CPSRAltered (state); + } + + WriteR15 (state, PC); +#else + if (state->Mode == USER26MODE || state->Mode == USER32MODE) + { + /* Protect bits in user mode. */ + ASSIGNN ((state->Reg[15] & NBIT) != 0); + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); + ASSIGNC ((state->Reg[15] & CBIT) != 0); + ASSIGNV ((state->Reg[15] & VBIT) != 0); + } + else + ARMul_R15Altered (state); + + FLUSHPIPE; +#endif + } + + if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE) + /* Restore the correct bank. */ + (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); + + /* To write back the final register. */ + ARMul_Icycles (state, 1, 0L); + + if (state->Aborted) + { + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + TAKEABORT; + } +} + +/* This function does the work of storing the registers listed in an STM + instruction, when the S bit is clear. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + +static void +StoreMult (ARMul_State * state, + ARMword instr, + ARMword address, + ARMword WBBase) +{ + ARMword temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + + if (!TFLAG) + /* N-cycle, increment the PC and update the NextInstr state. */ + BUSUSEDINCPCN; + +#ifndef MODE32 + if (VECTORACCESS (address) || ADDREXCEPT (address)) + INTERNALABORT (address); + + if (BIT (15)) + PATCHR15; +#endif + + /* N cycle first. */ + for (temp = 0; !BIT (temp); temp ++) + ; + +#ifdef MODE32 + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#else + if (state->Aborted) + { + (void) ARMul_LoadWordN (state, address); + + /* Fake the Stores as Loads. */ + for (; temp < 16; temp++) + if (BIT (temp)) + { + /* Save this register. */ + address += 4; + (void) ARMul_LoadWordS (state, address); + } + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + TAKEABORT; + return; + } + else + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#endif + + if (state->abortSig && !state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + /* S cycles from here on. */ + for (; temp < 16; temp ++) + if (BIT (temp)) + { + /* Save this register. */ + address += 4; + + ARMul_StoreWordS (state, address, state->Reg[temp]); + + if (state->abortSig && !state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + } + + if (state->Aborted) + TAKEABORT; +} + +/* This function does the work of storing the registers listed in an STM + instruction when the S bit is set. The code here is always increment + after, it's up to the caller to get the input address correct and to + handle base register modification. */ + +static void +StoreSMult (ARMul_State * state, + ARMword instr, + ARMword address, + ARMword WBBase) +{ + ARMword temp; + + UNDEF_LSMNoRegs; + UNDEF_LSMPCBase; + UNDEF_LSMBaseInListWb; + + BUSUSEDINCPCN; + +#ifndef MODE32 + if (VECTORACCESS (address) || ADDREXCEPT (address)) + INTERNALABORT (address); + + if (BIT (15)) + PATCHR15; +#endif + + if (state->Bank != USERBANK) + { + /* Force User Bank. */ + (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); + UNDEF_LSMUserBankWb; + } + + for (temp = 0; !BIT (temp); temp++) + ; /* N cycle first. */ + +#ifdef MODE32 + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#else + if (state->Aborted) + { + (void) ARMul_LoadWordN (state, address); + + for (; temp < 16; temp++) + /* Fake the Stores as Loads. */ + if (BIT (temp)) + { + /* Save this register. */ + address += 4; + + (void) ARMul_LoadWordS (state, address); + } + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + TAKEABORT; + return; + } + else + ARMul_StoreWordN (state, address, state->Reg[temp++]); +#endif + + if (state->abortSig && !state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + + /* S cycles from here on. */ + for (; temp < 16; temp++) + if (BIT (temp)) + { + /* Save this register. */ + address += 4; + + ARMul_StoreWordS (state, address, state->Reg[temp]); + + if (state->abortSig && !state->Aborted) + { + XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); + state->Aborted = ARMul_DataAbortV; + } + } + + if (state->Mode != USER26MODE && state->Mode != USER32MODE) + /* Restore the correct bank. */ + (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); + + if (BIT (21) && LHSReg != 15) + LSBase = WBBase; + + if (state->Aborted) + TAKEABORT; +} + +/* This function does the work of adding two 32bit values + together, and calculating if a carry has occurred. */ + +static ARMword +Add32 (ARMword a1, ARMword a2, int *carry) +{ + ARMword result = (a1 + a2); + unsigned int uresult = (unsigned int) result; + unsigned int ua1 = (unsigned int) a1; + + /* If (result == RdLo) and (state->Reg[nRdLo] == 0), + or (result > RdLo) then we have no carry. */ + if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)) + *carry = 1; + else + *carry = 0; + + return result; +} + +/* This function does the work of multiplying + two 32bit values to give a 64bit result. */ + +static unsigned +Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) +{ + /* Operand register numbers. */ + int nRdHi, nRdLo, nRs, nRm; + ARMword RdHi = 0, RdLo = 0, Rm; + /* Cycle count. */ + int scount; + + nRdHi = BITS (16, 19); + nRdLo = BITS (12, 15); + nRs = BITS (8, 11); + nRm = BITS (0, 3); + + /* Needed to calculate the cycle count. */ + Rm = state->Reg[nRm]; + + /* Check for illegal operand combinations first. */ + if ( nRdHi != 15 + && nRdLo != 15 + && nRs != 15 + && nRm != 15 + && nRdHi != nRdLo + && nRdHi != nRm + && nRdLo != nRm) + { + /* Intermediate results. */ + ARMword lo, mid1, mid2, hi; + int carry; + ARMword Rs = state->Reg[nRs]; + int sign = 0; + + if (msigned) + { + /* Compute sign of result and adjust operands if necessary. */ + sign = (Rm ^ Rs) & 0x80000000; + + if (((ARMsword) Rm) < 0) + Rm = -Rm; + + if (((ARMsword) Rs) < 0) + Rs = -Rs; + } + + /* We can split the 32x32 into four 16x16 operations. This + ensures that we do not lose precision on 32bit only hosts. */ + lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF)); + mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); + mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF)); + hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); + + /* We now need to add all of these results together, taking + care to propogate the carries from the additions. */ + RdLo = Add32 (lo, (mid1 << 16), &carry); + RdHi = carry; + RdLo = Add32 (RdLo, (mid2 << 16), &carry); + RdHi += + (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi); + + if (sign) + { + /* Negate result if necessary. */ + RdLo = ~RdLo; + RdHi = ~RdHi; + if (RdLo == 0xFFFFFFFF) + { + RdLo = 0; + RdHi += 1; + } + else + RdLo += 1; + } + + state->Reg[nRdLo] = RdLo; + state->Reg[nRdHi] = RdHi; + } + else + fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS\n"); + + if (scc) + /* Ensure that both RdHi and RdLo are used to compute Z, + but don't let RdLo's sign bit make it to N. */ + ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); + + /* The cycle count depends on whether the instruction is a signed or + unsigned multiply, and what bits are clear in the multiplier. */ + if (msigned && (Rm & ((unsigned) 1 << 31))) + /* Invert the bits to make the check against zero. */ + Rm = ~Rm; + + if ((Rm & 0xFFFFFF00) == 0) + scount = 1; + else if ((Rm & 0xFFFF0000) == 0) + scount = 2; + else if ((Rm & 0xFF000000) == 0) + scount = 3; + else + scount = 4; + + return 2 + scount; +} + +/* This function does the work of multiplying two 32bit + values and adding a 64bit value to give a 64bit result. */ + +static unsigned +MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc) +{ + unsigned scount; + ARMword RdLo, RdHi; + int nRdHi, nRdLo; + int carry = 0; + + nRdHi = BITS (16, 19); + nRdLo = BITS (12, 15); + + RdHi = state->Reg[nRdHi]; + RdLo = state->Reg[nRdLo]; + + scount = Multiply64 (state, instr, msigned, LDEFAULT); + + RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry); + RdHi = (RdHi + state->Reg[nRdHi]) + carry; + + state->Reg[nRdLo] = RdLo; + state->Reg[nRdHi] = RdHi; + + if (scc) + /* Ensure that both RdHi and RdLo are used to compute Z, + but don't let RdLo's sign bit make it to N. */ + ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); + + /* Extra cycle for addition. */ + return scount + 1; +} diff --git a/external/gpl3/gdb/dist/sim/arm/armemu.h b/external/gpl3/gdb/dist/sim/arm/armemu.h new file mode 100644 index 000000000000..ec1880382919 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armemu.h @@ -0,0 +1,545 @@ +/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +extern ARMword isize; + +/* Condition code values. */ +#define EQ 0 +#define NE 1 +#define CS 2 +#define CC 3 +#define MI 4 +#define PL 5 +#define VS 6 +#define VC 7 +#define HI 8 +#define LS 9 +#define GE 10 +#define LT 11 +#define GT 12 +#define LE 13 +#define AL 14 +#define NV 15 + +/* Shift Opcodes. */ +#define LSL 0 +#define LSR 1 +#define ASR 2 +#define ROR 3 + +/* Macros to twiddle the status flags and mode. */ +#define NBIT ((unsigned)1L << 31) +#define ZBIT (1L << 30) +#define CBIT (1L << 29) +#define VBIT (1L << 28) +#define SBIT (1L << 27) +#define IBIT (1L << 7) +#define FBIT (1L << 6) +#define IFBITS (3L << 6) +#define R15IBIT (1L << 27) +#define R15FBIT (1L << 26) +#define R15IFBITS (3L << 26) + +#define POS(i) ( (~(i)) >> 31 ) +#define NEG(i) ( (i) >> 31 ) + +#ifdef MODET /* Thumb support. */ +/* ??? This bit is actually in the low order bit of the PC in the hardware. + It isn't clear if the simulator needs to model that or not. */ +#define TBIT (1L << 5) +#define TFLAG state->TFlag +#define SETT state->TFlag = 1 +#define CLEART state->TFlag = 0 +#define ASSIGNT(res) state->TFlag = res +#define INSN_SIZE (TFLAG ? 2 : 4) +#else +#define INSN_SIZE 4 +#endif + +#define NFLAG state->NFlag +#define SETN state->NFlag = 1 +#define CLEARN state->NFlag = 0 +#define ASSIGNN(res) state->NFlag = res + +#define ZFLAG state->ZFlag +#define SETZ state->ZFlag = 1 +#define CLEARZ state->ZFlag = 0 +#define ASSIGNZ(res) state->ZFlag = res + +#define CFLAG state->CFlag +#define SETC state->CFlag = 1 +#define CLEARC state->CFlag = 0 +#define ASSIGNC(res) state->CFlag = res + +#define VFLAG state->VFlag +#define SETV state->VFlag = 1 +#define CLEARV state->VFlag = 0 +#define ASSIGNV(res) state->VFlag = res + +#define SFLAG state->SFlag +#define SETS state->SFlag = 1 +#define CLEARS state->SFlag = 0 +#define ASSIGNS(res) state->SFlag = res + +#define IFLAG (state->IFFlags >> 1) +#define FFLAG (state->IFFlags & 1) +#define IFFLAGS state->IFFlags +#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) +#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; + +#define PSR_FBITS (0xff000000L) +#define PSR_SBITS (0x00ff0000L) +#define PSR_XBITS (0x0000ff00L) +#define PSR_CBITS (0x000000ffL) + +#if defined MODE32 || defined MODET +#define CCBITS (0xf8000000L) +#else +#define CCBITS (0xf0000000L) +#endif + +#define INTBITS (0xc0L) + +#if defined MODET && defined MODE32 +#define PCBITS (0xffffffffL) +#else +#define PCBITS (0xfffffffcL) +#endif + +#define MODEBITS (0x1fL) +#define R15INTBITS (3L << 26) + +#if defined MODET && defined MODE32 +#define R15PCBITS (0x03ffffffL) +#else +#define R15PCBITS (0x03fffffcL) +#endif + +#define R15PCMODEBITS (0x03ffffffL) +#define R15MODEBITS (0x3L) + +#ifdef MODE32 +#define PCMASK PCBITS +#define PCWRAP(pc) (pc) +#else +#define PCMASK R15PCBITS +#define PCWRAP(pc) ((pc) & R15PCBITS) +#endif + +#define PC (state->Reg[15] & PCMASK) +#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) +#define R15INT (state->Reg[15] & R15INTBITS) +#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) +#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) +#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) +#define R15PC (state->Reg[15] & R15PCBITS) +#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) +#define R15MODE (state->Reg[15] & R15MODEBITS) + +#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27)) +#define EINT (IFFLAGS << 6) +#define ER15INT (IFFLAGS << 26) +#define EMODE (state->Mode) + +#ifdef MODET +#define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) +#else +#define CPSR (ECC | EINT | EMODE) +#endif + +#ifdef MODE32 +#define PATCHR15 +#else +#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC +#endif + +#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) +#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) +#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) +#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) +#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) + +#define SETR15PSR(s) \ + do \ + { \ + if (state->Mode == USER26MODE) \ + { \ + state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ + ASSIGNN ((state->Reg[15] & NBIT) != 0); \ + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ + ASSIGNC ((state->Reg[15] & CBIT) != 0); \ + ASSIGNV ((state->Reg[15] & VBIT) != 0); \ + } \ + else \ + { \ + state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ + ARMul_R15Altered (state); \ + } \ + } \ + while (0) + +#define SETABORT(i, m, d) \ + do \ + { \ + int SETABORT_mode = (m); \ + \ + ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ + ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ + | (i) | SETABORT_mode)); \ + state->Reg[14] = temp - (d); \ + } \ + while (0) + +#ifndef MODE32 +#define VECTORS 0x20 +#define LEGALADDR 0x03ffffff +#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) +#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) +#endif + +#define INTERNALABORT(address) \ + do \ + { \ + if (address < VECTORS) \ + state->Aborted = ARMul_DataAbortV; \ + else \ + state->Aborted = ARMul_AddrExceptnV; \ + } \ + while (0) + +#ifdef MODE32 +#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) +#else +#define TAKEABORT \ + do \ + { \ + if (state->Aborted == ARMul_AddrExceptnV) \ + ARMul_Abort (state, ARMul_AddrExceptnV); \ + else \ + ARMul_Abort (state, ARMul_DataAbortV); \ + } \ + while (0) +#endif + +#define CPTAKEABORT \ + do \ + { \ + if (!state->Aborted) \ + ARMul_Abort (state, ARMul_UndefinedInstrV); \ + else if (state->Aborted == ARMul_AddrExceptnV) \ + ARMul_Abort (state, ARMul_AddrExceptnV); \ + else \ + ARMul_Abort (state, ARMul_DataAbortV); \ + } \ + while (0); + + +/* Different ways to start the next instruction. */ +#define SEQ 0 +#define NONSEQ 1 +#define PCINCEDSEQ 2 +#define PCINCEDNONSEQ 3 +#define PRIMEPIPE 4 +#define RESUME 8 + +#define NORMALCYCLE state->NextInstr = 0 +#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ +#define BUSUSEDINCPCS \ + do \ + { \ + if (! state->is_v4) \ + { \ + /* A standard PC inc and an S cycle. */ \ + state->Reg[15] += isize; \ + state->NextInstr = (state->NextInstr & 0xff) | 2; \ + } \ + } \ + while (0) + +#define BUSUSEDINCPCN \ + do \ + { \ + if (state->is_v4) \ + BUSUSEDN; \ + else \ + { \ + /* A standard PC inc and an N cycle. */ \ + state->Reg[15] += isize; \ + state->NextInstr |= 3; \ + } \ + } \ + while (0) + +#define INCPC \ + do \ + { \ + /* A standard PC inc. */ \ + state->Reg[15] += isize; \ + state->NextInstr |= 2; \ + } \ + while (0) + +#define FLUSHPIPE state->NextInstr |= PRIMEPIPE + +/* Cycle based emulation. */ + +#define OUTPUTCP(i,a,b) +#define NCYCLE +#define SCYCLE +#define ICYCLE +#define CCYCLE +#define NEXTCYCLE(c) + +/* Macros to extract parts of instructions. */ +#define DESTReg (BITS (12, 15)) +#define LHSReg (BITS (16, 19)) +#define RHSReg (BITS ( 0, 3)) + +#define DEST (state->Reg[DESTReg]) + +#ifdef MODE32 +#ifdef MODET +#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg])) +#else +#define LHS (state->Reg[LHSReg]) +#endif +#else +#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) +#endif + +#define MULDESTReg (BITS (16, 19)) +#define MULLHSReg (BITS ( 0, 3)) +#define MULRHSReg (BITS ( 8, 11)) +#define MULACCReg (BITS (12, 15)) + +#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) +#define DPSImmRHS temp = BITS(0,11) ; \ + rhs = ARMul_ImmedTable[temp] ; \ + if (temp > 255) /* There was a shift. */ \ + ASSIGNC (rhs >> 31) ; + +#ifdef MODE32 +#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ + : GetDPRegRHS (state, instr)) +#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ + : GetDPSRegRHS (state, instr)) +#else +#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetDPRegRHS (state, instr)) +#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetDPSRegRHS (state, instr)) +#endif + +#define LSBase state->Reg[LHSReg] +#define LSImmRHS (BITS(0,11)) + +#ifdef MODE32 +#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ + : GetLSRegRHS (state, instr)) +#else +#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ + : GetLSRegRHS (state, instr)) +#endif + +#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ + (ARMword) ARMul_BitList[BITS (8, 15)] ) +#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ + (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) + +#define SWAPSRC (state->Reg[RHSReg]) + +#define LSCOff (BITS (0, 7) << 2) +#define CPNum BITS (8, 11) + +/* Determine if access to coprocessor CP is permitted. + The XScale has a register in CP15 which controls access to CP0 - CP13. */ +#define CP_ACCESS_ALLOWED(STATE, CP) \ + ( ((CP) >= 14) \ + || (! (STATE)->is_XScale) \ + || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) + +/* Macro to rotate n right by b bits. */ +#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) + +/* Macros to store results of instructions. */ +#define WRITEDEST(d) \ + do \ + { \ + if (DESTReg == 15) \ + WriteR15 (state, d); \ + else \ + DEST = d; \ + } \ + while (0) + +#define WRITESDEST(d) \ + do \ + { \ + if (DESTReg == 15) \ + WriteSR15 (state, d); \ + else \ + { \ + DEST = d; \ + ARMul_NegZero (state, d); \ + } \ + } \ + while (0) + +#define WRITEDESTB(d) \ + do \ + { \ + if (DESTReg == 15) \ + WriteR15Branch (state, d); \ + else \ + DEST = d; \ + } \ + while (0) + +#define BYTETOBUS(data) ((data & 0xff) | \ + ((data & 0xff) << 8) | \ + ((data & 0xff) << 16) | \ + ((data & 0xff) << 24)) + +#define BUSTOBYTE(address, data) \ + do \ + { \ + if (state->bigendSig) \ + temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ + else \ + temp = (data >> ((address & 3) << 3)) & 0xff; \ + } \ + while (0) + +#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) +#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) +#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) +#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) + +#define POSBRANCH ((instr & 0x7fffff) << 2) +#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) + + +/* Values for Emulate. */ +#define STOP 0 /* stop */ +#define CHANGEMODE 1 /* change mode */ +#define ONCE 2 /* execute just one interation */ +#define RUN 3 /* continuous execution */ + +/* Stuff that is shared across modes. */ +extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ +extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ +extern char ARMul_BitList[]; /* Number of bits in a byte table. */ + +#define EVENTLISTSIZE 1024L + +/* Thumb support. */ +typedef enum +{ + t_undefined, /* Undefined Thumb instruction. */ + t_decoded, /* Instruction decoded to ARM equivalent. */ + t_branch /* Thumb branch (already processed). */ +} +tdstate; + +/* Macros to scrutinize instructions. */ +#define UNDEF_Test +#define UNDEF_Shift +#define UNDEF_MSRPC +#define UNDEF_MRSPC +#define UNDEF_MULPCDest +#define UNDEF_MULDestEQOp1 +#define UNDEF_LSRBPC +#define UNDEF_LSRBaseEQOffWb +#define UNDEF_LSRBaseEQDestWb +#define UNDEF_LSRPCBaseWb +#define UNDEF_LSRPCOffWb +#define UNDEF_LSMNoRegs +#define UNDEF_LSMPCBase +#define UNDEF_LSMUserBankWb +#define UNDEF_LSMBaseInListWb +#define UNDEF_SWPPC +#define UNDEF_CoProHS +#define UNDEF_MCRPC +#define UNDEF_LSCPCBaseWb +#define UNDEF_UndefNotBounced +#define UNDEF_ShortInt +#define UNDEF_IllegalMode +#define UNDEF_Prog32SigChange +#define UNDEF_Data32SigChange + +/* Prototypes for exported functions. */ +extern unsigned ARMul_NthReg (ARMword, unsigned); +extern int AddOverflow (ARMword, ARMword, ARMword); +extern int SubOverflow (ARMword, ARMword, ARMword); +extern ARMword ARMul_Emulate26 (ARMul_State *); +extern ARMword ARMul_Emulate32 (ARMul_State *); +extern unsigned IntPending (ARMul_State *); +extern void ARMul_CPSRAltered (ARMul_State *); +extern void ARMul_R15Altered (ARMul_State *); +extern ARMword ARMul_GetPC (ARMul_State *); +extern ARMword ARMul_GetNextPC (ARMul_State *); +extern ARMword ARMul_GetR15 (ARMul_State *); +extern ARMword ARMul_GetCPSR (ARMul_State *); +extern void ARMul_EnvokeEvent (ARMul_State *); +extern unsigned long ARMul_Time (ARMul_State *); +extern void ARMul_NegZero (ARMul_State *, ARMword); +extern void ARMul_SetPC (ARMul_State *, ARMword); +extern void ARMul_SetR15 (ARMul_State *, ARMword); +extern void ARMul_SetCPSR (ARMul_State *, ARMword); +extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); +extern void ARMul_Abort26 (ARMul_State *, ARMword); +extern void ARMul_Abort32 (ARMul_State *, ARMword); +extern ARMword ARMul_MRC (ARMul_State *, ARMword); +extern void ARMul_CDP (ARMul_State *, ARMword); +extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); +extern void ARMul_STC (ARMul_State *, ARMword, ARMword); +extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); +extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); +extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); +extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); +extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); +extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); +extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); +extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); +extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *)); +/* Coprocessor support functions. */ +extern unsigned ARMul_CoProInit (ARMul_State *); +extern void ARMul_CoProExit (ARMul_State *); +extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *, + ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *, + ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); +extern void ARMul_CoProDetach (ARMul_State *, unsigned); +extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); + +extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); +extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); +extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); diff --git a/external/gpl3/gdb/dist/sim/arm/armfpe.h b/external/gpl3/gdb/dist/sim/arm/armfpe.h new file mode 100644 index 000000000000..c5a291f0a2a9 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armfpe.h @@ -0,0 +1,1352 @@ +/* armfpe.h -- ARMulator pre-compiled FPE: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Array containing the Floating Point Emualtor (FPE). */ + + +unsigned long fpecode[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00070000, 0x00000000, 0xe92d400e, 0xeb0013ef, + 0xe28f00d4, 0xe1a00120, 0xe38004ea, 0xe3a01004, + 0xe5912000, 0xe24f3028, 0xe1500002, 0x15832000, + 0x15810000, 0xe3a00001, 0xe8bd800e, 0xe28d9040, + 0xe1a0a00e, 0xe24f7048, 0xe597b000, 0xe20b74ee, + 0xe14f8000, 0xe2088040, 0xe388809b, 0xe121f008, + 0xe35704ea, 0x004bb007, 0x01a0b10b, 0x028bf00c, + 0xe20b733b, 0xe3570339, 0x01a0ba0b, 0x01a0ba2b, + 0x059bb00c, 0x0249800c, 0x08880e00, 0x0919ff80, + 0xe24f7094, 0xe1a0f007, 0xe14f8000, 0xe2088040, + 0xe3888093, 0xe121f008, 0xe8dd7fff, 0xe1a00000, + 0xe28dd03c, 0xe8fd8000, 0xe14f8000, 0xe2088040, + 0xe3888093, 0xe121f008, 0xe8bd1fff, 0xe28dd00c, + 0xe1b0f00e, 0xe14f8000, 0xe2088040, 0xe3888093, + 0xe121f008, 0xe28dd01c, 0xe8bd1f80, 0xe28dd00c, + 0xe1b0f00e, 0x00002100, 0xe90d4007, 0xe14f0000, + 0xe24d1010, 0xe10f2000, 0xe20220c0, 0xe3822003, + 0xe121f002, 0xe169f000, 0xe8914007, 0xe24dd040, + 0xe8cd7fff, 0xe24fcf6b, 0xe58de03c, 0xe24ea004, + 0xe14f9000, 0xe20990c0, 0xe3899003, 0xe121f009, + 0xe4ba9008, 0xe20987fe, 0xe2197010, 0xe0077aa9, + 0xe0288a07, 0x02097402, 0x00077509, 0x00888007, + 0xe2097c0f, 0xe3370c01, 0x0209733e, 0x0337033a, + 0x008ff8a8, 0xea00009f, 0xea0003b7, 0xea0003b6, + 0xea000307, 0xea000306, 0xea0003b3, 0xea0003b2, + 0xea000303, 0xea000302, 0xea0003c3, 0xea0003c2, + 0xea00030d, 0xea00030c, 0xea0003bf, 0xea0003be, + 0xea000309, 0xea000308, 0xea0003cf, 0xea0003ce, + 0xea000314, 0xea000313, 0xea0003cb, 0xea0003ca, + 0xea000310, 0xea00030f, 0xea0003db, 0xea0003da, + 0xea00031a, 0xea000319, 0xea0003d7, 0xea0003d6, + 0xea000316, 0xea000315, 0xea0003e7, 0xea0003e6, + 0xea000321, 0xea000320, 0xea0003f7, 0xea0003f6, + 0xea00032b, 0xea00032a, 0xea000449, 0xea000448, + 0xea000335, 0xea000334, 0xea000459, 0xea000458, + 0xea000340, 0xea00033f, 0xea000469, 0xea000468, + 0xea00034b, 0xea00034a, 0xea000479, 0xea000478, + 0xea000355, 0xea000354, 0xea000489, 0xea000488, + 0xea00035f, 0xea00035e, 0xea000499, 0xea000498, + 0xea00036a, 0xea000369, 0xea000ac8, 0xea000ac5, + 0xea000c3d, 0xea000c3a, 0xea000b7b, 0xea000b78, + 0xea000b79, 0xea000b76, 0xea000d34, 0xea000d31, + 0xea000d08, 0xea000d05, 0xea000e34, 0xea000e31, + 0xea000e1c, 0xea000e19, 0xea000ecf, 0xea000ecc, + 0xea000c2d, 0xea000c2a, 0xea000d28, 0xea000d25, + 0xea000cfc, 0xea000cf9, 0xea00123d, 0xea00123a, + 0xeaffff55, 0xeaffff54, 0xeaffff53, 0xeaffff52, + 0xeaffff51, 0xeaffff50, 0xea0007b8, 0xea0007ec, + 0xea00073c, 0xea00073b, 0xea000806, 0xea000805, + 0xea00080f, 0xea00080e, 0xeaffff47, 0xeaffff46, + 0xeaffff45, 0xeaffff44, 0xeaffff43, 0xeaffff42, + 0xeaffff41, 0xeaffff40, 0xeaffff3f, 0xeaffff3e, + 0xea00086f, 0xea00086e, 0xeaffff3b, 0xeaffff3a, + 0xea00086b, 0xea00086a, 0xeaffff37, 0xeaffff36, + 0xea0007ff, 0xea0007fe, 0xeaffff33, 0xeaffff32, + 0xea0007fb, 0xea0007fa, 0xea000914, 0xea0008f3, + 0xea00091f, 0xea0008fb, 0xea00092b, 0xea000904, + 0xea0009dc, 0xea0009d9, 0xea0009fd, 0xea0009fa, + 0xea000ef8, 0xea000ef5, 0xea000ef6, 0xea000ef3, + 0xea000f9d, 0xea000f9a, 0xea00111e, 0xea00111b, + 0xea00111c, 0xea001119, 0xea00104e, 0xea00104b, + 0xea001147, 0xea001144, 0xea001145, 0xea001142, + 0xea00125a, 0xea001257, 0xeaffff13, 0xeaffff12, + 0xeaffff11, 0xeaffff10, 0xe3190c0e, 0x1affff0e, + 0xe3190c01, 0x13190302, 0x0affff0b, 0xe28fb016, + 0xe79b7d27, 0xe14fb000, 0xe1a0be2b, 0xe28bb010, + 0xe1170b37, 0x0affff51, 0xeaffff29, 0x8000f0f0, + 0x80000f0f, 0x8000cccc, 0x80003333, 0x8000ff00, + 0x800000ff, 0x8000aaaa, 0x80005555, 0x8000cfcf, + 0x80003030, 0x800055aa, 0x8000aa55, 0x80005faf, + 0x8000a050, 0x80000000, 0x8000ffff, 0xe1300007, + 0x5a000002, 0xea00004a, 0xe3100102, 0x1a000048, + 0xe053400b, 0x4a00002d, 0xe2745020, 0xda00001b, + 0xe092243a, 0x20822518, 0x30922518, 0xe0b11438, + 0xe1a0451a, 0x2a000006, 0xe0922fa4, 0xe2b11000, + 0x31b0f00e, 0xe3a01102, 0xe2833001, 0xe1a040a4, + 0xe1b0f00e, 0xe2833001, 0xe1a040a4, 0xe1844f82, + 0xe1a020a2, 0xe1822f81, 0xe1a01061, 0xe0922fa4, + 0xe2a11000, 0xe1b0f00e, 0xe1a04538, 0xe0922fa4, + 0xe2b11000, 0x23a01102, 0x22833001, 0xe1b0f00e, + 0xe2545040, 0xaafffff7, 0xe2444020, 0xe2645020, + 0xe0922438, 0xe2b11000, 0xe1a04518, 0xe184443a, + 0x2affffe7, 0xe0922fa4, 0xe2b11000, 0x31b0f00e, + 0xe3a01102, 0xe2833001, 0xe1a040a4, 0xe1b0f00e, + 0xe2644000, 0xe1a0300b, 0xe1a05001, 0xe1a01008, + 0xe1a08005, 0xe1a05002, 0xe1a0200a, 0xe1a0a005, + 0xe2745020, 0xdaffffe5, 0xe092243a, 0x20822518, + 0x30922518, 0xe0b11438, 0xe1a0451a, 0x2affffd0, + 0xe0922fa4, 0xe2b11000, 0x31b0f00e, 0xe3a01102, + 0xe2833001, 0xe1a040a4, 0xe1b0f00e, 0xe3100102, + 0x1affffb6, 0xe053600b, 0x4a00003d, 0x01510008, + 0x0152000a, 0x0a00004f, 0x3a000039, 0xe3a04000, + 0xe2765020, 0xda00001a, 0xe054451a, 0xe0d2263a, + 0x30422518, 0x20522518, 0xe0d11638, 0x5a000002, + 0xe0922fa4, 0xe2a11000, 0xe1b0f00e, 0xe0944004, + 0xe0b22002, 0xe0b11001, 0xe2433001, 0x5afffffa, + 0xe0922fa4, 0xe2b11000, 0x31b0f00e, 0xe3a01102, + 0xe2833001, 0xe1a040a4, 0xe1b0f00e, 0xe0544538, + 0x41b0f00e, 0xe2d22000, 0xe2d11000, 0x41b0f00e, + 0xeaffffed, 0xe3a04000, 0xe2565040, 0xaafffff6, + 0xe2466020, 0xe2665020, 0xe054751a, 0xe0d4463a, + 0x30444518, 0x20544518, 0xe0d22638, 0xe2d11000, + 0x5a000002, 0xe0922fa4, 0xe2a11000, 0xe1b0f00e, + 0xe0977007, 0xe0b44004, 0xe0b22002, 0xe0b11001, + 0xe2433001, 0x5afffff9, 0xe0922fa4, 0xe2b11000, + 0x31b0f00e, 0xe3a01102, 0xe2833001, 0xe1a040a4, + 0xe1b0f00e, 0xe2666000, 0xe2200102, 0xe1a0300b, + 0xe1a05001, 0xe1a01008, 0xe1a08005, 0xe1a05002, + 0xe1a0200a, 0xe1a0a005, 0xe3a04000, 0xe2765020, + 0xdaffffd7, 0xe054451a, 0xe0d2263a, 0x30422518, + 0x20522518, 0xe0d11638, 0x5affffbf, 0xe0922fa4, + 0xe2a11000, 0xe1b0f00e, 0xe3a03000, 0xe3a02000, + 0xe3a01000, 0xe3a04000, 0xe1b0f00e, 0xe1a07000, + 0xe1a08001, 0xe1a0a002, 0xe1a0b003, 0xe0200007, + 0xe1914002, 0x1198400a, 0x0afffff2, 0xe3b054ff, + 0xe0a3300b, 0xe185b425, 0xe043392b, 0xe92c4209, + 0xe1a04821, 0xe1c1500b, 0xe1a06822, 0xe1c2700b, + 0xe1c8900b, 0xe1a08828, 0xe1cab00b, 0xe1a0a82a, + 0xe0030b96, 0xe0020b94, 0xe0010994, 0xe0000a97, + 0xe0933000, 0xe0000a95, 0xe0b22000, 0xe0000895, + 0xe0b11000, 0x33a0e000, 0x23a0e001, 0xe0000996, + 0xe0922000, 0xe2b11000, 0xe2aee000, 0xe0000897, + 0xe0922000, 0xe2b11000, 0xe2aee000, 0xe18ee803, + 0xe1a03823, 0xe1833802, 0xe1a02822, 0xe1822801, + 0xe1a01821, 0xe181180e, 0xe3cee0ff, 0xe0000b95, + 0xe00b0b97, 0xe09eb00b, 0xe0b33000, 0xe0000896, + 0xe0b22000, 0xe0000894, 0xe0a11000, 0xe0000a94, + 0xe00a0a96, 0xe09aa003, 0xe0b22000, 0xe2a11000, + 0xe0000997, 0xe09a4000, 0xe0000995, 0xe0b22000, + 0xe2b11000, 0xe8bc4209, 0x4a000005, 0xe09bb00b, + 0xe0b44004, 0xe0b22002, 0xe0b11001, 0xe2433001, + 0x5afffff9, 0xe0922fa4, 0xe2b11000, 0x31b0f00e, + 0xe3a01102, 0xe2833001, 0xe1a040a4, 0xe1b0f00e, + 0xe1a07000, 0xe1a08001, 0xe1a0a002, 0xe1a0b003, + 0xe3a00000, 0xe3a01102, 0xe3b02100, 0xe2e23901, + 0xe0200007, 0xe1914002, 0x1198400a, 0x0affff9d, + 0xe043300b, 0xe2833901, 0xe2433001, 0xe3a0b000, + 0xe052500a, 0xe0d14008, 0x23a01003, 0x2a00000c, + 0xe1a05002, 0xe1a04001, 0xe3a01001, 0xe2433001, + 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a, + 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006, + 0xe0a11001, 0xe0955005, 0xe0b44004, 0xe2abb000, + 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007, + 0x21a04006, 0xe0a11001, 0xe0955005, 0xe0b44004, + 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab, + 0x21a05007, 0x21a04006, 0xe0a11001, 0xe0955005, + 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008, + 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0b11001, + 0x3affffda, 0xe1942005, 0x01b0f00e, 0xe3a02001, + 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a, + 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006, + 0xe0a22002, 0xe0955005, 0xe0b44004, 0xe2abb000, + 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007, + 0x21a04006, 0xe0a22002, 0xe0955005, 0xe0b44004, + 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab, + 0x21a05007, 0x21a04006, 0xe0a22002, 0xe0955005, + 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008, + 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0b22002, + 0x3affffda, 0xe0955005, 0xe0b44004, 0x2a000001, + 0xe1540008, 0x0155000a, 0xe2b22000, 0xe2b11000, + 0x31b0f00e, 0xe2a33000, 0xe3a01102, 0xe1b0f00e, + 0xe1b04883, 0x0affff37, 0xe2833901, 0xe2433001, + 0xe1b030a3, 0xe1a05002, 0x32414102, 0x22414101, + 0x33a07201, 0x23a07202, 0xe3a01102, 0xe0955005, + 0xe0b44004, 0xe0216007, 0x31540006, 0x20444006, + 0x20211087, 0xe1b070e7, 0x5afffff7, 0xe1942005, + 0x01b0f00e, 0xe3a02000, 0xe0955005, 0xe0b44004, + 0xe0a00000, 0xe0226007, 0xe055a006, 0xe0d48001, + 0x31b000a0, 0x21a0500a, 0x21a04008, 0x20222087, + 0x20211fa7, 0xe1b070a7, 0x1afffff2, 0xe0955005, + 0xe0b44004, 0xe0b70007, 0xe0d5a002, 0xe0d48001, + 0x31b000a0, 0x21a0500a, 0x21a04008, 0x22222001, + 0x23a07102, 0xe3a00000, 0xe0977007, 0xe0b55005, + 0xe0b44004, 0x2a000002, 0xe1540001, 0x01550002, + 0x03570101, 0xe2b22000, 0xe2b11000, 0xe2a33000, + 0x23a01102, 0xe1b0f00e, 0xe1b07004, 0x42644000, + 0xe3a0b901, 0xe3a0a000, 0xe1a08004, 0xe1b04828, + 0x01a08808, 0x128bb010, 0xe1b04c28, 0x01a08408, + 0x128bb008, 0xe1b04e28, 0x01a08208, 0x128bb004, + 0xe1b04f28, 0x01a08108, 0x128bb002, 0xe1b04fa8, + 0x01a08088, 0x024bb001, 0xe1b0f00e, 0xe1a07000, + 0xe1a0b003, 0xe24b40fe, 0xe2544c3f, 0xda000011, + 0xe2745020, 0x4a000003, 0xe3a0a000, 0xe1a08531, + 0xe1a08518, 0xe1b0f00e, 0xe1a08001, 0xe1a0a002, + 0xe2745040, 0x41b0f00e, 0xe1a0a53a, 0xe1a0a51a, + 0xe1b0f00e, 0x03a04001, 0x03a08102, 0xe3a0a000, + 0x028bb001, 0x01b0f00e, 0xe3a04000, 0xe3a08000, + 0xe3a0a000, 0xe3a0b000, 0xe1b0f00e, 0xe1a07000, + 0xe1a0b003, 0xe24b40fe, 0xe2544c3f, 0xdafffff0, + 0xe2745020, 0x4a000007, 0xe3a0a000, 0xe1b04531, + 0xe2a44000, 0xe1b08514, 0x31b0f00e, 0xe1a08068, + 0xe28bb001, 0xe1b0f00e, 0xe1a08001, 0xe1a0a002, + 0xe2745040, 0xe3e04000, 0x41b0f00e, 0xe1b0a53a, + 0xe2aaa000, 0xe1b0a51a, 0xe2b88000, 0x31b0f00e, + 0xe1a0a0aa, 0xe18aaf88, 0xe1a08068, 0xe28bb001, + 0xe1b0f00e, 0xe38ee101, 0xe24340fe, 0xe2544c3f, + 0xda000032, 0xe2745020, 0x4a000018, 0xe1a08411, + 0x01a08002, 0x11a0a002, 0x03a0a000, 0xe3a02000, + 0xe1a01531, 0xe2194060, 0x1a000007, 0xe19aa088, + 0x00088f81, 0xe0911fa8, 0x31b01511, 0x31b0f00e, + 0xe1a01061, 0xe2833001, 0xe1b0f00e, 0xe3540060, + 0x1198a00a, 0x0a000003, 0xe0304d04, 0x5a000001, + 0xe2911001, 0xeafffff3, 0xe1a01511, 0xe1b0f00e, + 0xe2745040, 0xd1b0f00e, 0xe2444020, 0xe1a08412, + 0xe1b02532, 0xe2194060, 0x1a00000a, 0xe1b0a088, + 0x00088f82, 0xe0822fa8, 0xe1b02512, 0xe2b11000, + 0x31b0f00e, 0xe1a020a2, 0xe1822f81, 0xe1a01061, + 0xe2833001, 0xe1b0f00e, 0xe3540060, 0x13580000, + 0x0afffff4, 0xe0304d04, 0x42822001, 0xeafffff1, + 0x0a000011, 0xe2194060, 0x1a000006, 0xe1918002, + 0x01b0f00e, 0xe3a01000, 0xe3a02000, 0xe3a03000, + 0xe3a04008, 0xe1a0f00e, 0xe1918002, 0x13540060, + 0x0afffff5, 0xe0304d04, 0x5afffff3, 0xe3a01102, + 0xe3b02100, 0xe2e23901, 0xe1b0f00e, 0xe2194060, + 0x1afffff4, 0xe1924081, 0x1afffff7, 0xeaffffea, + 0xe1a04000, 0xe1a00007, 0xe1a07004, 0xe1a04001, + 0xe1a01008, 0xe1a08004, 0xe1a04002, 0xe1a0200a, + 0xe1a0a004, 0xe1a04003, 0xe1a0300b, 0xe1a0b004, + 0xe1b0f00e, 0xe209ba07, 0xe08c542b, 0xe209780f, + 0xe79da727, 0xe21980ff, 0xe04a8108, 0x178d8727, + 0xe2199902, 0xe3899901, 0xe1a09789, 0xe4ba6004, + 0x14ba7004, 0xe88503c0, 0xeafffcae, 0xe209ba07, + 0xe08c542b, 0xe209780f, 0xe79da727, 0xe21980ff, + 0xe04a8108, 0x178d8727, 0xe2199902, 0xe3899905, + 0xe1a09789, 0xe4ba6004, 0xe4ba7004, 0xe4ba8000, + 0xe88503c0, 0xeafffc9f, 0xe209ba07, 0xe08c542b, + 0xe209780f, 0xe79da727, 0xe21980ff, 0xe08a8108, + 0x178d8727, 0xe2199902, 0xe3899901, 0xe1a09789, + 0xe4ba6004, 0x14ba7004, 0xe88503c0, 0xeafffc91, + 0xe209ba07, 0xe08c542b, 0xe209780f, 0xe79da727, + 0xe21980ff, 0xe08a8108, 0x178d8727, 0xe2199902, + 0xe3899905, 0xe1a09789, 0xe4ba6004, 0xe4ba7004, + 0xe4ba8000, 0xe88503c0, 0xeafffc82, 0xe209ba07, + 0xe08cc42b, 0xe209780f, 0xe337080f, 0x179da727, + 0xe21980ff, 0xe04aa108, 0xe2199902, 0xe3899901, + 0xe1a0b789, 0xe4ba8004, 0x14ba9004, 0xe88c0f00, + 0xeafffc83, 0xe209ba07, 0xe08c542b, 0xe209780f, + 0xe79da727, 0xe21980ff, 0xe04aa108, 0x178da727, + 0xe2199902, 0xe3899901, 0xe1a09789, 0xe4ba6004, + 0x14ba7004, 0xe88503c0, 0xeafffc66, 0xe209ba07, + 0xe08cc42b, 0xe209780f, 0xe337080f, 0x179da727, + 0xe21980ff, 0xe04aa108, 0xe2199902, 0xe3899905, + 0xe1a0b789, 0xe4ba8004, 0xe4ba9004, 0xe4baa000, + 0xe88c0f00, 0xeafffc66, 0xe209ba07, 0xe08c542b, + 0xe209780f, 0xe79da727, 0xe21980ff, 0xe04aa108, + 0x178da727, 0xe2199902, 0xe3899905, 0xe1a09789, + 0xe4ba6004, 0xe4ba7004, 0xe4ba8000, 0xe88503c0, + 0xeafffc48, 0xe209ba07, 0xe08cc42b, 0xe209780f, + 0xe337080f, 0x179da727, 0xe21980ff, 0xe08aa108, + 0xe2199902, 0xe3899901, 0xe1a0b789, 0xe4ba8004, + 0x14ba9004, 0xe88c0f00, 0xeafffc49, 0xe209ba07, + 0xe08c542b, 0xe209780f, 0xe79da727, 0xe21980ff, + 0xe08aa108, 0x178da727, 0xe2199902, 0xe3899901, + 0xe1a09789, 0xe4ba6004, 0x14ba7004, 0xe88503c0, + 0xeafffc2c, 0xe209ba07, 0xe08cc42b, 0xe209780f, + 0xe337080f, 0x179da727, 0xe21980ff, 0xe08aa108, + 0xe2199902, 0xe3899905, 0xe1a0b789, 0xe4ba8004, + 0xe4ba9004, 0xe4baa000, 0xe88c0f00, 0xeafffc2c, + 0xe209ba07, 0xe08c542b, 0xe209780f, 0xe79da727, + 0xe21980ff, 0xe08aa108, 0x178da727, 0xe2199902, + 0xe3899905, 0xe1a09789, 0xe4ba6004, 0xe4ba7004, + 0xe4ba8000, 0xe88503c0, 0xeafffc0e, 0xe2095a07, + 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729, + 0xe3844001, 0xe1340ea3, 0xe1844d23, 0xe28f7004, + 0xe28f5f6f, 0x1085f104, 0xe209780f, 0xe79da727, + 0xe21980ff, 0xe04a8108, 0x178d8727, 0xe4aa0004, + 0xe3130101, 0x14aa1000, 0xeafffbfa, 0xe2095a07, + 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729, + 0xe3844005, 0xe1340ea3, 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0xe3100102, 0x13a03000, + 0xea00007c, 0xe198600a, 0x0affffdd, 0xe09aa00a, + 0xe0b88008, 0xe24bb001, 0x5afffffb, 0xe92c4200, + 0xeaffffb4, 0xe3190080, 0x1afff08f, 0xe1b08e09, + 0x4afffa4e, 0xe08c8c28, 0xe898000f, 0xe1b04d23, + 0xe28f7000, 0x1afff508, 0x1888000f, 0xe2000102, + 0xe183b000, 0xe1a0a002, 0xe1a08001, 0xe2096807, + 0xe08c6626, 0xe896000f, 0xe1b04d23, 0xe28f7000, + 0x1afff4fd, 0x1886000f, 0xe1a0700b, 0xe3cbb102, + 0xe1b04883, 0x12944802, 0x11b0588b, 0x12955802, + 0x0a00000a, 0xe92c400f, 0xe92c0d80, 0xebfff27f, + 0xebfff36f, 0xe8bc0d80, 0xebfff227, 0xe2200102, + 0xe8bc0d80, 0xebfff178, 0xe8bc4000, 0xea00004d, + 0xe1b04883, 0x1a000010, 0xe1915002, 0x1a00000a, + 0xe1b0588b, 0x0198600a, 0x0a000013, 0xe2955802, + 0x1a000015, 0xe198600a, 0x0a000013, 0xe1a01008, + 0xe1a0200a, 0xe1a0300b, 0xeafffc4e, 0xe0922002, + 0xe0b11001, 0xe2433001, 0x5afffffb, 0xe1b0588b, + 0x1a000012, 0xe198600a, 0x1a00000c, 0xe2944802, + 0x1a000001, 0xe1916002, 0x1afffc42, 0xe3a01333, + 0xe3b02100, 0xe2e23902, 0xeafffc3e, 0xe3a00000, + 0xe3a01000, 0xe3a02000, 0xe3a03000, 0xea000029, + 0xe09aa00a, 0xe0b88008, 0xe24bb001, 0x5afffffb, + 0xe2956802, 0x12946802, 0x1affffc9, 0xe2946802, + 0x1a000008, 0xe1916002, 0x1afffc2e, 0x03a01333, + 0xe2956802, 0x1afffc2b, 0xe198600a, 0x11a01008, + 0x11a0200a, 0xeafffc27, 0xe198600a, 0x0a000015, + 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xeafffc21, + 0xe3190080, 0x1afff02c, 0xe1b07e09, 0x4afff9cb, + 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000, + 0x1afff4a5, 0x1888000f, 0xe1b04883, 0x12944802, + 0x0a00001d, 0xe3100102, 0x1a000016, 0xe92c4000, + 0xeb000029, 0xe8bc4000, 0xe3190702, 0x1a000005, + 0xe28f7018, 0xe3530000, 0xdafffa5d, 0xe3190080, + 0x0afffa2b, 0xeafffa5f, 0xe3530000, 0xba000006, + 0xe59c5080, 0xe3150010, 0x0afffbd1, 0xe2099a07, + 0xe08c9429, 0xe889000f, 0xeafff02a, 0xe3730040, + 0xcafffcce, 0xeafffa4e, 0xe3a014c6, 0xe3a02000, + 0xe3a030ff, 0xe1833383, 0xeafffbf6, 0xe3530000, + 0x1a000008, 0xe1914002, 0x0afffff6, 0xe1b01001, + 0x4affffdb, 0xe0922002, 0xe0b11001, 0xe2433001, + 0x5afffffb, 0xeaffffd6, 0xe1914002, 0x1afffbe9, + 0xe3100102, 0x0affffe1, 0xeaffffea, 0xe28f4f52, + 0xe8940500, 0xe1510008, 0x0152000a, 0xe1a0a0a2, + 0xe18aaf81, 0xe1a080a1, 0xe3888102, 0xe3a0b0fe, + 0xe18bb30b, 0xe043400b, 0x92444001, 0xe92c4210, + 0xe1a0300b, 0x8a000005, 0xe3c88101, 0xe0922002, + 0xe0b11001, 0xe2433001, 0x5a000003, 0xea000008, + 0xe3a00102, 0xe2722000, 0xe2f11000, 0x03520000, + 0x0a000035, 0xe0922002, 0xe0b11001, 0xe2433001, + 0x5afffff9, 0xe3a07000, 0xebfff1e0, 0xe92c000f, + 0xebfff185, 0xe92c000f, 0xe28f90c4, 0xe8b90d00, + 0xebfff125, 0xe89c0d80, 0xebfff183, 0xe8b90d00, + 0xebfff0d8, 0xe89c0d80, 0xebfff17f, 0xe8b90d00, + 0xebfff11d, 0xe89c0d80, 0xe92c000f, 0xe3a00102, + 0xe8b9000e, 0xebfff178, 0xe8b90d00, 0xebfff0cd, + 0xe28c4010, 0xe8940d80, 0xebfff173, 0xe8b90d00, + 0xebfff111, 0xe8bc0d80, 0xebfff1c4, 0xe8bc0d80, + 0xebfff16d, 0xe89c0d80, 0xebfff16b, 0xe8bc0d80, + 0xebfff0bd, 0xe8bc0010, 0xebfff25e, 0xe92c000f, + 0xe3a00000, 0xe8b9000e, 0xebfff163, 0xe8bc0d80, + 0xebfff0b5, 0xe8bc0200, 0xe3190601, 0xe28f7074, + 0x18970d00, 0x1bfff15c, 0xe8bc8000, 0xe3a00000, + 0xe3a03000, 0xe28f9050, 0xeaffffed, 0xb504f333, + 0xf9de6484, 0x8eac025b, 0x3e7076bb, 0x00004004, + 0x9c041fd0, 0xa933ef60, 0x00004007, 0xc05ff4e0, + 0x6c83bb96, 0x00004008, 0xca20ad9a, 0xb5e946e9, + 0x00003ffe, 0x83125100, 0xb57f6509, 0x00004003, + 0x803ff895, 0x9dacd228, 0x00004005, 0xb17217f7, + 0xd1cf79ac, 0x00003ffe, 0xde5bd8a9, 0x37287195, + 0x00003ffd, 0xe3190080, 0x1affef83, 0xe1b07e09, + 0x4afff926, 0xe08c8c27, 0xe898000f, 0xe1b04d23, + 0xe28f7000, 0x1afff3fc, 0x1888000f, 0xe1a04883, + 0xe2944802, 0x0a000005, 0xe92c4000, 0xeb00000a, + 0xe8bc4000, 0x0affff57, 0xe24f7d0a, 0xeafff4cd, + 0xe1914002, 0x1afffb63, 0xe3100102, 0x0affff5b, + 0xe3a00000, 0xe3a03000, 0xeaffff58, 0xe28f4f6e, + 0xe3100102, 0x128f4f72, 0xe8b40d00, 0xe153000b, + 0x01510008, 0x0152000a, 0x8a00005d, 0xe8940d00, + 0xe153000b, 0x01510008, 0x0152000a, 0x3a000052, + 0xe92c421f, 0xe28f9e1b, 0xe3a07000, 0xe8b90d00, + 0xebfff111, 0xebfff238, 0xe3170102, 0x12644000, + 0xe58c4010, 0xe92c0d80, 0xe3a00000, 0xe8b9000e, + 0xebfff109, 0xe8bc0d80, 0xe92c000f, 0xe8b9000e, + 0xe3a00102, 0xebfff104, 0xe92c000f, 0xe28c4020, + 0xe894000f, 0xebfff20c, 0xe3170102, 0x0bfff09e, + 0x1bfff054, 0xe1a0400c, 0xe92c000f, 0xe894000f, + 0xebfff04d, 0xe8bc0d80, 0xebfff04b, 0xe28cc010, + 0xe8bc0d80, 0xebfff048, 0xe88c000f, 0xebfff0ee, + 0xe92c000f, 0xe3a07000, 0xe8b90d00, 0xebfff0ee, + 0xe8b90d00, 0xebfff043, 0xe89c0d80, 0xebfff0ea, + 0xe8b90d00, 0xebfff03f, 0xe89c0d80, 0xebfff0e6, + 0xe8b90d00, 0xebfff03b, 0xe89c0d80, 0xe92c000f, + 0xe3a00000, 0xe8b9000e, 0xebfff0df, 0xe8b90d00, + 0xebfff034, 0xe28c7010, 0xe8970d80, 0xebfff0da, + 0xe8b90d00, 0xebfff02f, 0xe28c7020, 0xe8970d80, + 0xebfff0d5, 0xe8bc0d80, 0xe92c000f, 0xe2200102, + 0xebfff025, 0xe1a07000, 0xe1a08001, 0xe1a0a002, + 0xe1a0b003, 0xe8bc000f, 0xebfff120, 0xe8b90d00, + 0xebfff020, 0xe28cc020, 0xe8bc4210, 0xe2844001, + 0xe0833004, 0xe3b04000, 0xe1a0f00e, 0xe3b00000, + 0xe3a01102, 0xe3a02000, 0xe3a03901, 0xe2433001, + 0xe1a0f00e, 0xe3100102, 0xe3a00000, 0xe3a01000, + 0xe3a02000, 0x13a03000, 0x13a04008, 0x03a030ff, + 0x01833383, 0x03b04004, 0xe1a0f00e, 0xb17217f7, + 0xd1cf79ab, 0x0000400c, 0x80000000, 0x00000000, + 0x00003fbe, 0xb21dfe7f, 0x09e2baa9, 0x0000400c, + 0x80000000, 0x00000000, 0x00003fbe, 0xb8aa3b29, + 0x5c17f0bc, 0x00003fff, 0xde8082e3, 0x08654362, + 0x00003ff2, 0xb1800000, 0x00000000, 0x00003ffe, + 0xc99b1867, 0x2822a93e, 0x00003fea, 0xa57862e1, + 0x46a6fb39, 0x00003ff4, 0xe8b9428e, 0xfecff592, + 0x00003ffa, 0x80000000, 0x00000000, 0x00003ffe, + 0x845a2157, 0x3490f106, 0x00003ff0, 0xf83a5f91, + 0x50952c99, 0x00003ff7, 0x80000000, 0x00000000, + 0x00003ffd, 0x80000000, 0x00000000, 0x00003ffe, + 0xe3190080, 0x1affeecc, 0xe1b07e09, 0x4afff873, + 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000, + 0x1afff345, 0x1888000f, 0xe1a04883, 0xe2944802, + 0x0a000006, 0xe92c4000, 0xeb000007, 0xe8bc4000, + 0x0afffea0, 0xe24f705c, 0xe2477c05, 0xeafff415, + 0xe1914002, 0x03a01332, 0xeafffaaa, 0xe28f4f8f, + 0xe8b40d00, 0xe153000b, 0x01510008, 0x0152000a, + 0x8a00006c, 0xe1b01001, 0x5a000063, 0xe92c421f, + 0xe3190601, 0xe28f9e22, 0xe3a07000, 0xe8b90d00, + 0xebfff061, 0xebfff188, 0x1b00006d, 0xe58c4010, + 0xe92c0d80, 0xe3a00000, 0xe8b9000e, 0xebfff05a, + 0xe8bc0d80, 0xe92c000f, 0xe8b9000e, 0xe3a00102, + 0xebfff055, 0xe92c000f, 0xe28c4020, 0xe894000f, + 0xebfff15d, 0xe3170102, 0x0bffefef, 0x1bffefa5, + 0xe1a0400c, 0xe92c000f, 0xe894000f, 0xebffef9e, + 0xe8bc0d80, 0xebffef9c, 0xe28cc010, 0xe8bc0d80, + 0xebffef99, 0xe3a04c3f, 0xe38440df, 0xe1530004, + 0xba000037, 0xe88c000f, 0xebfff03b, 0xe92c000f, + 0xe3a07000, 0xe8b90d00, 0xebfff03b, 0xe8b90d00, + 0xebffefd9, 0xe89c0d80, 0xebfff037, 0xe8b90d00, + 0xebffef8c, 0xe89c0d80, 0xebfff033, 0xe8b90d00, + 0xebffefd1, 0xe89c0d80, 0xebfff02f, 0xe8b90d00, + 0xebffef84, 0xe89c0d80, 0xe92c000f, 0xe3a00102, + 0xe8b9000e, 0xebfff028, 0xe8b90d00, 0xebffef7d, + 0xe28c7010, 0xe8970d80, 0xebfff023, 0xe8b90d00, + 0xebffefc1, 0xe28c7010, 0xe8970d80, 0xebfff01e, + 0xe28c7020, 0xe8970d80, 0xebfff01b, 0xe28c7020, + 0xe8970d80, 0xebffef6c, 0xe8bc0d80, 0xe28cc020, + 0xe8bc0010, 0xe3140001, 0x12200102, 0x1bfff1a7, + 0xe29b4902, 0x4a000018, 0xe35b0000, 0x0198400a, + 0x0a000015, 0xebfff061, 0xe8bc4200, 0xe3b04000, + 0xe1a0f00e, 0xe24cc010, 0xe3a07000, 0xe3a08102, + 0xe3b0a100, 0xe2eab901, 0xeaffffeb, 0xe1914002, + 0x0affff99, 0xe2433001, 0xe0922002, 0xe0b11001, + 0x5afffffb, 0xeaffff94, 0xe3a01332, 0xe3b02100, + 0xe2f23902, 0xe3a04001, 0xe1a0f00e, 0xe3a01000, + 0xe3b02100, 0xe2f33902, 0xe3a04004, 0xe8bc4200, + 0xe1a0f00e, 0xe2844001, 0xe35b0000, 0x03a08102, + 0xe3a06901, 0x0246b002, 0x01a0f00e, 0xe2466002, + 0xe04b6006, 0xe3a05102, 0xe153000b, 0x01510008, + 0x0152000a, 0x20888635, 0x21a0f00e, 0xe0588635, + 0x51a08088, 0x524bb001, 0xe2444001, 0xe1a0f00e, + 0xc90fdaa2, 0x00000000, 0x0000401d, 0xa2f9836e, + 0x4e44152a, 0x00003ffe, 0x95777a5c, 0xf72cece6, + 0x00003fed, 0xc9100000, 0x00000000, 0x00003fff, + 0x85bba783, 0xb3c748a9, 0x00003fea, 0xa37b24c8, + 0x4a42092e, 0x00003ff3, 0xd23cf50b, 0xf10aca84, + 0x00003ff9, 0xeef5823f, 0xdecea969, 0x00003ffd, + 0x80000000, 0x00000000, 0x00003fff, 0x95d5b975, + 0x16391da8, 0x00003fef, 0xe0741531, 0xdd56f650, + 0x00003ff6, 0x8895af2a, 0x6847fcd5, 0x00003ffc, + 0xe3190080, 0x1affee00, 0xe1b07e09, 0x4afff7ab, + 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000, + 0x1afff279, 0x1888000f, 0xe1a04883, 0xe2944802, + 0x0a000015, 0xe1c00589, 0xe92c4000, 0xe1914002, + 0x12433001, 0xebffff38, 0x1a000012, 0xe92c000f, + 0xebffefa1, 0xe3a08102, 0xe3b0a100, 0xe2eab901, + 0xebffeef8, 0xe1a07000, 0xe1a08001, 0xe1a0a002, + 0xe1a0b003, 0xe8bc000f, 0xebffeff0, 0xe1914002, + 0x12833001, 0xe8bc4000, 0xeafffdc2, 0xe1914002, + 0x03a014c9, 0xeafff9cf, 0xe8bc4000, 0xe3540004, + 0x03a03000, 0x03a00000, 0x0afffdba, 0xe3a014c9, + 0xe3b02100, 0xe2e23902, 0xeafff9c6, 0xe3190080, + 0x1affedd1, 0xe1b07e09, 0x4afff780, 0xe08c8c27, + 0xe898000f, 0xe1b04d23, 0xe28f7000, 0x1afff24a, + 0x1888000f, 0xe1b04883, 0x0a00006b, 0x52944802, + 0x4a000072, 0xe92c4201, 0xe3a00000, 0xe3a05901, + 0xe2455002, 0xe1530005, 0xaa000009, 0xe2094501, + 0xe92c0010, 0xe3a04901, 0xe2444021, 0xe1530004, + 0xba000049, 0xe92c000f, 0xebffef6b, 0xe92c000f, + 0xea000012, 0xe2094501, 0xe2244501, 0xe92c0010, + 0xe3a00102, 0xe3a08102, 0xe3b0a100, 0xe2eab901, + 0xebffeebc, 0xe1914002, 0x0a00003b, 0xe2433001, + 0xe24cc010, 0xe92c000f, 0xebfff01c, 0xe2200102, + 0xe2833001, 0xe28c4010, 0xe884000f, 0xe89c000f, + 0xe28f9f59, 0xe8b90d00, 0xebffeef7, 0xe89c0d80, + 0xebffef55, 0xe8b90d00, 0xebffeeaa, 0xe89c0d80, + 0xebffef51, 0xe8b90d00, 0xebffeeef, 0xe89c0d80, + 0xebffef4d, 0xe8b90d00, 0xebffeea2, 0xe89c0d80, + 0xebffef49, 0xe8b90d00, 0xebffeee7, 0xe89c0d80, + 0xe92c000f, 0xe3a00102, 0xe8b9000e, 0xebffef42, + 0xe8b90d00, 0xebffee97, 0xe28c7010, 0xe8970d80, + 0xebffef3d, 0xe8b90d00, 0xebffeedb, 0xe28c7010, + 0xe8970d80, 0xebffef38, 0xe8b90d00, 0xebffee8d, + 0xe28c7010, 0xe8970d80, 0xebffef33, 0xe8b90d00, + 0xebffeed1, 0xe28c7010, 0xe8970d80, 0xebffef2e, + 0xe8bc0d80, 0xe28cc010, 0xebffef80, 0xe89c0d80, + 0xebffef29, 0xe8bc0d80, 0xebffee7b, 0xe8bc0230, + 0xe3190501, 0x0a000008, 0xe3150102, 0x028f5c01, + 0x128f5f46, 0xe0855924, 0x02200102, 0xe8950d00, + 0xebffee74, 0xe8bc4000, 0xeafffd46, 0xe3150102, + 0xe28f50dc, 0xe0855924, 0xe8950d00, 0xebffee6d, + 0x12200102, 0xe8bc4000, 0xeafffd3e, 0xe1915002, + 0x0affff93, 0xe1b01001, 0x4affff91, 0xe2433001, + 0xe0922002, 0xe0b11001, 0x5afffffb, 0xeaffff8c, + 0xe2f35901, 0x01925081, 0x0affff89, 0xe2944802, + 0x1a000001, 0xe1914002, 0x1afff93e, 0xe3a014ca, + 0xe3b02100, 0xe2e23902, 0xeafff93a, 0xbe974377, + 0xcc30f9e6, 0x00004003, 0x96f3e4b2, 0xc8e37cbc, + 0x00004006, 0xbeee77e2, 0xb5423cf3, 0x00004007, + 0xd0927880, 0xf5c2170b, 0x00004007, 0xa43601f1, + 0x5c3e6196, 0x00004006, 0xb25dedaf, 0x30f3242c, + 0x00003ffe, 0xa270bb27, 0x61c93957, 0x00004002, + 0x9ec1654d, 0x36d4f820, 0x00004004, 0xe4d539b0, + 0x56a451ad, 0x00004004, 0xdaf2ad41, 0xd05311c4, + 0x00004003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xc90fdaa2, 0x2168c235, 0x00003fff, + 0xc90fdaa2, 0x2168c235, 0x00004000, 0x00000000, + 0xc90fdaa2, 0x2168c235, 0x00003fff, 0xe3190080, + 0x1affed19, 0xe2096807, 0xe08c6626, 0xe896000f, + 0xe1b04d23, 0xe28f7000, 0x1afff193, 0x1886000f, + 0xe2000102, 0xe183b000, 0xe1a0a002, 0xe1a08001, + 0xe1b06e09, 0x4afff6c9, 0xe08c6c26, 0xe896000f, + 0xe1b04d23, 0xe28f7000, 0x1afff187, 0x1886000f, + 0xe1a0700b, 0xe3cbb102, 0xe1b04883, 0x12944802, + 0x11b0588b, 0x12955802, 0x192c4281, 0x1bffef0b, + 0x1a00004e, 0xe1b04883, 0x1a000010, 0xe1915002, + 0x1a00000a, 0xe1b0588b, 0x0198600a, 0x0a00001f, + 0xe2955802, 0x1a000016, 0xe198600a, 0x0a000014, + 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xeafff8e1, + 0xe0922002, 0xe0b11001, 0xe2433001, 0x5afffffb, + 0xe1b0588b, 0x1a000019, 0xe198600a, 0x1a000013, + 0xe2944802, 0x1a000001, 0xe1916002, 0x1afff8d5, + 0xe1a04000, 0xe1a05007, 0xe28f0fbd, 0xe890000e, + 0xea00008c, 0xe1a04000, 0xe1a05007, 0xe3a00000, + 0xe3a01000, 0xe3a02000, 0xe3a03000, 0xea00007d, + 0xe3a014cb, 0xe3b02100, 0xe2e23902, 0xeafff8c5, + 0xe09aa00a, 0xe0b88008, 0xe24bb001, 0x5afffffb, + 0xe2956802, 0x12946802, 0x1affffca, 0xe2946802, + 0x1a000006, 0xe1916002, 0x1afff8ba, 0xe2956802, + 0x1affffe2, 0xe198600a, 0x03a014cb, 0x0afff8b5, + 0xe198600a, 0x0affffe2, 0xe1a01008, 0xe1a0200a, + 0xe1a0300b, 0xeafff8af, 0xe3190080, 0x1affecba, + 0xe1b07e09, 0x4afff671, 0xe08c8c27, 0xe898000f, + 0xe1b04d23, 0xe28f7000, 0x1afff133, 0x1888000f, + 0xe1b04883, 0x12944802, 0x0a000060, 0xe92c4281, + 0xe3b00100, 0xe2f34901, 0xdbffeeb0, 0xd3a04002, + 0xc3a04000, 0xe28f9d06, 0xe8b90d00, 0xe153000b, + 0x01510008, 0x0152000a, 0xc2844001, 0xe92c0010, + 0xda00000d, 0xe92c000f, 0xe8990d00, 0xebffedad, + 0xe8bc0d80, 0xe92c000f, 0xe3a00000, 0xe8b9000e, + 0xebffee51, 0xe3a08102, 0xe3b0a100, 0xe2eab901, + 0xebffeded, 0xe8bc0d80, 0xebffeea0, 0xe3a04901, + 0xe2444021, 0xe1530004, 0xba00002c, 0xe92c000f, + 0xebffee41, 0xe92c000f, 0xe28f9f49, 0xe8b90d00, + 0xebffed98, 0xe89c0d80, 0xebffee3f, 0xe8b90d00, + 0xebffed94, 0xe89c0d80, 0xebffee3b, 0xe8b90d00, + 0xebffed90, 0xe89c0d80, 0xebffee37, 0xe8b90d00, + 0xebffed8c, 0xe89c0d80, 0xe92c000f, 0xe3a00102, + 0xe8b9000e, 0xebffee30, 0xe8b90d00, 0xebffedce, + 0xe28c7010, 0xe8970d80, 0xebffee2b, 0xe8b90d00, + 0xebffedc9, 0xe28c7010, 0xe8970d80, 0xebffee26, + 0xe8b90d00, 0xebffedc4, 0xe28c7010, 0xe8970d80, + 0xebffee21, 0xe8bc0d80, 0xe28cc010, 0xebffee73, + 0xe89c0d80, 0xebffee1c, 0xe8bc0d80, 0xebffed6e, + 0xe28f90dc, 0xe8bc0010, 0xe0200f04, 0xe0899204, + 0xe8990d00, 0xebffed6b, 0xe8bc4230, 0xe3190601, + 0x10200004, 0x1afffc3b, 0xe3150102, 0x0a000005, + 0xe92c4010, 0xe2200102, 0xe24f7d0d, 0xe8970d00, + 0xebffed60, 0xe8bc4010, 0xe0200004, 0xeafffc31, + 0xe3530000, 0x0afffc2f, 0xe1914002, 0x1afff83d, + 0xe28f009c, 0xe890000e, 0xeafffc2a, 0x8930a2f4, + 0xf66ab18a, 0x00003ffd, 0xddb3d742, 0xc265539e, + 0x00003fff, 0xf0624f0a, 0x56388310, 0x00004002, + 0xee505190, 0x6d1eb4e8, 0x00004004, 0xac509020, + 0x5b6d243b, 0x00004005, 0xa443e5e6, 0x24ad4b90, + 0x00004004, 0xd66bd6cd, 0x8c3de934, 0x00003ffe, + 0x87e9fae4, 0x6b531a29, 0x00004002, 0xa40bfdcf, + 0x15e65691, 0x00004003, 0xdb053288, 0x30e70eb4, + 0x00004002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x860a91c1, 0x6b9b2c23, 0x00003ffe, + 0x00000000, 0xc90fdaa2, 0x2168c235, 0x00003fff, + 0x00000000, 0x860a91c1, 0x6b9b2c23, 0x00003fff, + 0xe92d5001, 0xe24fc05c, 0xe24ccc50, 0xe3a00807, + 0xe58c0080, 0xe8bd9001, 0xe1a00000, 0xe3100001, + 0x128f0e15, 0x1a00000a, 0xe3100004, 0x128f0f47, + 0x1a000007, 0xe3100002, 0x128f00e0, 0x1a000004, + 0xe3100008, 0x128f00a8, 0x1a000001, 0xe28f0070, + 0xeaffffff, 0xe28f101c, 0xe14fb000, 0xe8bd07f8, + 0xe8a107f8, 0xe8bd07f8, 0xe24aa004, 0xe8a10ff8, + 0xe28f1000, 0xef000071, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00002278, + 0xffffffff, 0x80000204, 0x616f6c46, 0x676e6974, + 0x696f5020, 0x4520746e, 0x70656378, 0x6e6f6974, + 0x49203a20, 0x6178656e, 0x52207463, 0x6c757365, + 0x00000074, 0x80000203, 0x616f6c46, 0x676e6974, + 0x696f5020, 0x4520746e, 0x70656378, 0x6e6f6974, + 0x55203a20, 0x7265646e, 0x776f6c66, 0x00000000, + 0x80000202, 0x616f6c46, 0x676e6974, 0x696f5020, + 0x4520746e, 0x70656378, 0x6e6f6974, 0x44203a20, + 0x64697669, 0x79422065, 0x72655a20, 0x0000006f, + 0x80000201, 0x616f6c46, 0x676e6974, 0x696f5020, + 0x4520746e, 0x70656378, 0x6e6f6974, 0x4f203a20, + 0x66726576, 0x00776f6c, 0x80000200, 0x616f6c46, + 0x676e6974, 0x696f5020, 0x4520746e, 0x70656378, + 0x6e6f6974, 0x49203a20, 0x6c61766e, 0x4f206469, + 0x61726570, 0x6e6f6974, 0x00000000, 0xfefefeff, 0 +}; + +unsigned long fpesize = 0x00005300; diff --git a/external/gpl3/gdb/dist/sim/arm/arminit.c b/external/gpl3/gdb/dist/sim/arm/arminit.c new file mode 100644 index 000000000000..c84fb5cce444 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/arminit.c @@ -0,0 +1,353 @@ +/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include + +#include "armdefs.h" +#include "armemu.h" +#include "dbg_rdi.h" + +/***************************************************************************\ +* Definitions for the emulator architecture * +\***************************************************************************/ + +void ARMul_EmulateInit (void); +ARMul_State *ARMul_NewState (void); +void ARMul_Reset (ARMul_State * state); +ARMword ARMul_DoCycle (ARMul_State * state); +unsigned ARMul_DoCoPro (ARMul_State * state); +ARMword ARMul_DoProg (ARMul_State * state); +ARMword ARMul_DoInstr (ARMul_State * state); +void ARMul_Abort (ARMul_State * state, ARMword address); + +unsigned ARMul_MultTable[32] = + { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, + 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 +}; +ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ +char ARMul_BitList[256]; /* number of bits in a byte table */ + +/***************************************************************************\ +* Call this routine once to set up the emulator's tables. * +\***************************************************************************/ + +void +ARMul_EmulateInit (void) +{ + unsigned long i, j; + + for (i = 0; i < 4096; i++) + { /* the values of 12 bit dp rhs's */ + ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); + } + + for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ + for (j = 1; j < 256; j <<= 1) + for (i = 0; i < 256; i++) + if ((i & j) > 0) + ARMul_BitList[i]++; + + for (i = 0; i < 256; i++) + ARMul_BitList[i] *= 4; /* you always need 4 times these values */ + +} + +/***************************************************************************\ +* Returns a new instantiation of the ARMulator's state * +\***************************************************************************/ + +ARMul_State * +ARMul_NewState (void) +{ + ARMul_State *state; + unsigned i, j; + + state = (ARMul_State *) malloc (sizeof (ARMul_State)); + memset (state, 0, sizeof (ARMul_State)); + + state->Emulate = RUN; + for (i = 0; i < 16; i++) + { + state->Reg[i] = 0; + for (j = 0; j < 7; j++) + state->RegBank[j][i] = 0; + } + for (i = 0; i < 7; i++) + state->Spsr[i] = 0; + + /* state->Mode = USER26MODE; */ + state->Mode = USER32MODE; + + state->CallDebug = FALSE; + state->Debug = FALSE; + state->VectorCatch = 0; + state->Aborted = FALSE; + state->Reseted = FALSE; + state->Inted = 3; + state->LastInted = 3; + + state->MemDataPtr = NULL; + state->MemInPtr = NULL; + state->MemOutPtr = NULL; + state->MemSparePtr = NULL; + state->MemSize = 0; + + state->OSptr = NULL; + state->CommandLine = NULL; + + state->CP14R0_CCD = -1; + state->LastTime = 0; + + state->EventSet = 0; + state->Now = 0; + state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * + sizeof (struct EventNode + *)); + for (i = 0; i < EVENTLISTSIZE; i++) + *(state->EventPtr + i) = NULL; + + state->prog32Sig = HIGH; + state->data32Sig = HIGH; + + state->lateabtSig = LOW; + state->bigendSig = LOW; + + state->is_v4 = LOW; + state->is_v5 = LOW; + state->is_v5e = LOW; + state->is_XScale = LOW; + state->is_iWMMXt = LOW; + state->is_v6 = LOW; + + ARMul_Reset (state); + + return state; +} + +/***************************************************************************\ + Call this routine to set ARMulator to model certain processor properities +\***************************************************************************/ + +void +ARMul_SelectProcessor (ARMul_State * state, unsigned properties) +{ + if (properties & ARM_Fix26_Prop) + { + state->prog32Sig = LOW; + state->data32Sig = LOW; + } + else + { + state->prog32Sig = HIGH; + state->data32Sig = HIGH; + } + + state->lateabtSig = LOW; + + state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; + state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; + state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; + state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; + state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; + state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; + state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; + + /* Only initialse the coprocessor support once we + know what kind of chip we are dealing with. */ + ARMul_CoProInit (state); +} + +/***************************************************************************\ +* Call this routine to set up the initial machine state (or perform a RESET * +\***************************************************************************/ + +void +ARMul_Reset (ARMul_State * state) +{ + state->NextInstr = 0; + + if (state->prog32Sig) + { + state->Reg[15] = 0; + state->Cpsr = INTBITS | SVC32MODE; + state->Mode = SVC32MODE; + } + else + { + state->Reg[15] = R15INTBITS | SVC26MODE; + state->Cpsr = INTBITS | SVC26MODE; + state->Mode = SVC26MODE; + } + + ARMul_CPSRAltered (state); + state->Bank = SVCBANK; + + FLUSHPIPE; + + state->EndCondition = 0; + state->ErrorCode = 0; + + state->Exception = FALSE; + state->NresetSig = HIGH; + state->NfiqSig = HIGH; + state->NirqSig = HIGH; + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + state->abortSig = LOW; + state->AbortAddr = 1; + + state->NumInstrs = 0; + state->NumNcycles = 0; + state->NumScycles = 0; + state->NumIcycles = 0; + state->NumCcycles = 0; + state->NumFcycles = 0; +#ifdef ASIM + (void) ARMul_MemoryInit (); + ARMul_OSInit (state); +#endif +} + + +/***************************************************************************\ +* Emulate the execution of an entire program. Start the correct emulator * +* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * +* address of the last instruction that is executed. * +\***************************************************************************/ + +ARMword +ARMul_DoProg (ARMul_State * state) +{ + ARMword pc = 0; + + state->Emulate = RUN; + while (state->Emulate != STOP) + { + state->Emulate = RUN; + if (state->prog32Sig && ARMul_MODE32BIT) + pc = ARMul_Emulate32 (state); + else + pc = ARMul_Emulate26 (state); + } + return (pc); +} + +/***************************************************************************\ +* Emulate the execution of one instruction. Start the correct emulator * +* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * +* address of the instruction that is executed. * +\***************************************************************************/ + +ARMword +ARMul_DoInstr (ARMul_State * state) +{ + ARMword pc = 0; + + state->Emulate = ONCE; + if (state->prog32Sig && ARMul_MODE32BIT) + pc = ARMul_Emulate32 (state); + else + pc = ARMul_Emulate26 (state); + + return (pc); +} + +/***************************************************************************\ +* This routine causes an Abort to occur, including selecting the correct * +* mode, register bank, and the saving of registers. Call with the * +* appropriate vector's memory address (0,4,8 ....) * +\***************************************************************************/ + +void +ARMul_Abort (ARMul_State * state, ARMword vector) +{ + ARMword temp; + int isize = INSN_SIZE; + int esize = (TFLAG ? 0 : 4); + int e2size = (TFLAG ? -4 : 0); + + state->Aborted = FALSE; + + if (ARMul_OSException (state, vector, ARMul_GetPC (state))) + return; + + if (state->prog32Sig) + if (ARMul_MODE26BIT) + temp = R15PC; + else + temp = state->Reg[15]; + else + temp = R15PC | ECC | ER15INT | EMODE; + + switch (vector) + { + case ARMul_ResetV: /* RESET */ + SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); + break; + case ARMul_UndefinedInstrV: /* Undefined Instruction */ + SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); + break; + case ARMul_SWIV: /* Software Interrupt */ + SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); + break; + case ARMul_PrefetchAbortV: /* Prefetch Abort */ + state->AbortAddr = 1; + SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); + break; + case ARMul_DataAbortV: /* Data Abort */ + SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); + break; + case ARMul_AddrExceptnV: /* Address Exception */ + SETABORT (IBIT, SVC26MODE, isize); + break; + case ARMul_IRQV: /* IRQ */ + if ( ! state->is_XScale + || ! state->CPRead[13] (state, 0, & temp) + || (temp & ARMul_CP13_R0_IRQ)) + SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); + break; + case ARMul_FIQV: /* FIQ */ + if ( ! state->is_XScale + || ! state->CPRead[13] (state, 0, & temp) + || (temp & ARMul_CP13_R0_FIQ)) + SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); + break; + } + if (ARMul_MODE32BIT) + ARMul_SetR15 (state, vector); + else + ARMul_SetR15 (state, R15CCINTMODE | vector); + + if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) + { + /* No vector has been installed. Rather than simulating whatever + random bits might happen to be at address 0x20 onwards we elect + to stop. */ + switch (vector) + { + case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; + case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; + case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; + case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; + case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; + case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; + case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; + case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; + default: break; + } + state->Emulate = FALSE; + } +} diff --git a/external/gpl3/gdb/dist/sim/arm/armopts.h b/external/gpl3/gdb/dist/sim/arm/armopts.h new file mode 100644 index 000000000000..8fad74775040 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armopts.h @@ -0,0 +1,23 @@ +/* armopts.h -- ARMulator configuration options: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Define one of ARM60 or ARM61 */ +#ifndef ARM60 +#ifndef ARM61 +#define ARM60 +#endif +#endif diff --git a/external/gpl3/gdb/dist/sim/arm/armos.c b/external/gpl3/gdb/dist/sim/arm/armos.c new file mode 100644 index 000000000000..39b9d4f06156 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armos.c @@ -0,0 +1,948 @@ +/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* This file contains a model of Demon, ARM Ltd's Debug Monitor, + including all the SWI's required to support the C library. The code in + it is not really for the faint-hearted (especially the abort handling + code), but it is a complete example. Defining NOOS will disable all the + fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI + 0x11 to halt the emulator. */ + +#include "config.h" +#include "ansidecl.h" + +#include +#include +#include +#include +#include "targ-vals.h" + +#ifndef TARGET_O_BINARY +#define TARGET_O_BINARY 0 +#endif + +#ifdef HAVE_UNISTD_H +#include /* For SEEK_SET etc. */ +#endif + +#ifdef __riscos +extern int _fisatty (FILE *); +#define isatty_(f) _fisatty(f) +#else +#ifdef __ZTC__ +#include +#define isatty_(f) isatty((f)->_file) +#else +#ifdef macintosh +#include +#define isatty_(f) (~ioctl ((f)->_file, FIOINTERACTIVE, NULL)) +#else +#define isatty_(f) isatty (fileno (f)) +#endif +#endif +#endif + +#include "armdefs.h" +#include "armos.h" +#include "armemu.h" + +#ifndef NOOS +#ifndef VALIDATE +/* #ifndef ASIM */ +#include "armfpe.h" +/* #endif */ +#endif +#endif + +/* For RDIError_BreakpointReached. */ +#include "dbg_rdi.h" + +#include "gdb/callback.h" +extern host_callback *sim_callback; + +extern unsigned ARMul_OSInit (ARMul_State *); +extern void ARMul_OSExit (ARMul_State *); +extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword); +extern unsigned ARMul_OSException (ARMul_State *, ARMword, ARMword); +extern ARMword ARMul_OSLastErrorP (ARMul_State *); +extern ARMword ARMul_Debug (ARMul_State *, ARMword, ARMword); + +#define BUFFERSIZE 4096 +#ifndef FOPEN_MAX +#define FOPEN_MAX 64 +#endif +#define UNIQUETEMPS 256 +#ifndef PATH_MAX +#define PATH_MAX 1024 +#endif + +/* OS private Information. */ + +struct OSblock +{ + ARMword Time0; + ARMword ErrorP; + ARMword ErrorNo; + FILE *FileTable[FOPEN_MAX]; + char FileFlags[FOPEN_MAX]; + char *tempnames[UNIQUETEMPS]; +}; + +#define NOOP 0 +#define BINARY 1 +#define READOP 2 +#define WRITEOP 4 + +#ifdef macintosh +#define FIXCRLF(t,c) ((t & BINARY) ? \ + c : \ + ((c == '\n' || c == '\r' ) ? (c ^ 7) : c) \ + ) +#else +#define FIXCRLF(t,c) c +#endif + +/* Bit mask of enabled SWI implementations. */ +unsigned int swi_mask = -1; + + +static ARMword softvectorcode[] = +{ + /* Installed instructions: + swi tidyexception + event; + mov lr, pc; + ldmia fp, {fp, pc}; + swi generateexception + event. */ + 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */ + 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */ + 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */ + 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */ + 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */ + 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */ + 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */ + 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */ + 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */ + 0xe1a0f00e /* Default handler */ +}; + +/* Time for the Operating System to initialise itself. */ + +unsigned +ARMul_OSInit (ARMul_State * state) +{ +#ifndef NOOS +#ifndef VALIDATE + ARMword instr, i, j; + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + + if (state->OSptr == NULL) + { + state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock)); + if (state->OSptr == NULL) + { + perror ("OS Memory"); + exit (15); + } + } + + OSptr = (struct OSblock *) state->OSptr; + OSptr->ErrorP = 0; + state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */ + ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */ + ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */ + ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */ + ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */ + instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */ + + for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) + /* Write hardware vectors. */ + ARMul_WriteWord (state, i, instr); + + SWI_vector_installed = 0; + + for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4) + { + ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4); + ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L, + SOFTVECTORCODE + sizeof (softvectorcode) - 4L); + } + + for (i = 0; i < sizeof (softvectorcode); i += 4) + ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]); + + for (i = 0; i < FOPEN_MAX; i++) + OSptr->FileTable[i] = NULL; + + for (i = 0; i < UNIQUETEMPS; i++) + OSptr->tempnames[i] = NULL; + + ARMul_ConsolePrint (state, ", Demon 1.01"); + +/* #ifndef ASIM */ + + /* Install FPE. */ + for (i = 0; i < fpesize; i += 4) + /* Copy the code. */ + ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]); + + /* Scan backwards from the end of the code. */ + for (i = FPESTART + fpesize;; i -= 4) + { + /* When we reach the marker value, break out of + the loop, leaving i pointing at the maker. */ + if ((j = ARMul_ReadWord (state, i)) == 0xffffffff) + break; + + /* If necessary, reverse the error strings. */ + if (state->bigendSig && j < 0x80000000) + { + /* It's part of the string so swap it. */ + j = ((j >> 0x18) & 0x000000ff) | + ((j >> 0x08) & 0x0000ff00) | + ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000); + ARMul_WriteWord (state, i, j); + } + } + + /* Copy old illegal instr vector. */ + ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV)); + /* Install new vector. */ + ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4))); + ARMul_ConsolePrint (state, ", FPE"); + +/* #endif ASIM */ +#endif /* VALIDATE */ +#endif /* NOOS */ + + /* Intel do not want DEMON SWI support. */ + if (state->is_XScale) + swi_mask = SWI_MASK_ANGEL; + + return TRUE; +} + +void +ARMul_OSExit (ARMul_State * state) +{ + free ((char *) state->OSptr); +} + + +/* Return the last Operating System Error. */ + +ARMword ARMul_OSLastErrorP (ARMul_State * state) +{ + return ((struct OSblock *) state->OSptr)->ErrorP; +} + +static int translate_open_mode[] = +{ + TARGET_O_RDONLY, /* "r" */ + TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */ + TARGET_O_RDWR, /* "r+" */ + TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */ + TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */ + TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */ + TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */ + TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */ + TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */ + TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */ + TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */ + TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */ +}; + +static void +SWIWrite0 (ARMul_State * state, ARMword addr) +{ + ARMword temp; + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + + while ((temp = ARMul_SafeReadByte (state, addr++)) != 0) + { + char buffer = temp; + /* Note - we cannot just cast 'temp' to a (char *) here, + since on a big-endian host the byte value will end + up in the wrong place and a nul character will be printed. */ + (void) sim_callback->write_stdout (sim_callback, & buffer, 1); + } + + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); +} + +static void +WriteCommandLineTo (ARMul_State * state, ARMword addr) +{ + ARMword temp; + char *cptr = state->CommandLine; + + if (cptr == NULL) + cptr = "\0"; + do + { + temp = (ARMword) * cptr++; + ARMul_SafeWriteByte (state, addr++, temp); + } + while (temp != 0); +} + +static int +ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n) +{ + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + char *p = buf; + + while (n--) + if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0') + return 0; + OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG); + state->Reg[0] = -1; + return -1; +} + +static void +SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags) +{ + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + char buf[PATH_MAX]; + int flags; + + if (ReadFileName (state, buf, name, sizeof buf) == -1) + return; + + /* Now we need to decode the Demon open mode. */ + flags = translate_open_mode[SWIflags]; + + /* Filename ":tt" is special: it denotes stdin/out. */ + if (strcmp (buf, ":tt") == 0) + { + if (flags == TARGET_O_RDONLY) /* opening tty "r" */ + state->Reg[0] = 0; /* stdin */ + else + state->Reg[0] = 1; /* stdout */ + } + else + { + state->Reg[0] = sim_callback->open (sim_callback, buf, flags); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } +} + +static void +SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) +{ + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + int res; + int i; + char *local = malloc (len); + + if (local == NULL) + { + sim_callback->printf_filtered + (sim_callback, + "sim: Unable to read 0x%ulx bytes - out of memory\n", + len); + return; + } + + res = sim_callback->read (sim_callback, f, local, len); + if (res > 0) + for (i = 0; i < res; i++) + ARMul_SafeWriteByte (state, ptr + i, local[i]); + + free (local); + state->Reg[0] = res == -1 ? -1 : len - res; + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); +} + +static void +SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) +{ + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + int res; + ARMword i; + char *local = malloc (len); + + if (local == NULL) + { + sim_callback->printf_filtered + (sim_callback, + "sim: Unable to write 0x%lx bytes - out of memory\n", + (long) len); + return; + } + + for (i = 0; i < len; i++) + local[i] = ARMul_SafeReadByte (state, ptr + i); + + res = sim_callback->write (sim_callback, f, local, len); + state->Reg[0] = res == -1 ? -1 : len - res; + free (local); + + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); +} + +static void +SWIflen (ARMul_State * state, ARMword fh) +{ + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + ARMword addr; + + if (fh > FOPEN_MAX) + { + OSptr->ErrorNo = EBADF; + state->Reg[0] = -1L; + return; + } + + addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR); + + state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END); + (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET); + + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); +} + +static void +SWIremove (ARMul_State * state, ARMword path) +{ + char buf[PATH_MAX]; + + if (ReadFileName (state, buf, path, sizeof buf) != -1) + { + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + state->Reg[0] = sim_callback->unlink (sim_callback, buf); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } +} + +static void +SWIrename (ARMul_State * state, ARMword old, ARMword new) +{ + char oldbuf[PATH_MAX], newbuf[PATH_MAX]; + + if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1 + && ReadFileName (state, newbuf, new, sizeof newbuf) != -1) + { + struct OSblock *OSptr = (struct OSblock *) state->OSptr; + state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } +} + +/* The emulator calls this routine when a SWI instruction is encuntered. + The parameter passed is the SWI number (lower 24 bits of the instruction). */ + +unsigned +ARMul_OSHandleSWI (ARMul_State * state, ARMword number) +{ + struct OSblock * OSptr = (struct OSblock *) state->OSptr; + int unhandled = FALSE; + + switch (number) + { + case SWI_Read: + if (swi_mask & SWI_MASK_DEMON) + SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); + else + unhandled = TRUE; + break; + + case SWI_Write: + if (swi_mask & SWI_MASK_DEMON) + SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]); + else + unhandled = TRUE; + break; + + case SWI_Open: + if (swi_mask & SWI_MASK_DEMON) + SWIopen (state, state->Reg[0], state->Reg[1]); + else + unhandled = TRUE; + break; + + case SWI_Clock: + if (swi_mask & SWI_MASK_DEMON) + { + /* Return number of centi-seconds. */ + state->Reg[0] = +#ifdef CLOCKS_PER_SEC + (CLOCKS_PER_SEC >= 100) + ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) + : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); +#else + /* Presume unix... clock() returns microseconds. */ + (ARMword) (clock () / 10000); +#endif + OSptr->ErrorNo = errno; + } + else + unhandled = TRUE; + break; + + case SWI_Time: + if (swi_mask & SWI_MASK_DEMON) + { + state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } + else + unhandled = TRUE; + break; + + case SWI_Close: + if (swi_mask & SWI_MASK_DEMON) + { + state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } + else + unhandled = TRUE; + break; + + case SWI_Flen: + if (swi_mask & SWI_MASK_DEMON) + SWIflen (state, state->Reg[0]); + else + unhandled = TRUE; + break; + + case SWI_Exit: + if (swi_mask & SWI_MASK_DEMON) + state->Emulate = FALSE; + else + unhandled = TRUE; + break; + + case SWI_Seek: + if (swi_mask & SWI_MASK_DEMON) + { + /* We must return non-zero for failure. */ + state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } + else + unhandled = TRUE; + break; + + case SWI_WriteC: + if (swi_mask & SWI_MASK_DEMON) + { + char tmp = state->Reg[0]; + (void) sim_callback->write_stdout (sim_callback, &tmp, 1); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } + else + unhandled = TRUE; + break; + + case SWI_Write0: + if (swi_mask & SWI_MASK_DEMON) + SWIWrite0 (state, state->Reg[0]); + else + unhandled = TRUE; + break; + + case SWI_GetErrno: + if (swi_mask & SWI_MASK_DEMON) + state->Reg[0] = OSptr->ErrorNo; + else + unhandled = TRUE; + break; + + case SWI_GetEnv: + if (swi_mask & SWI_MASK_DEMON) + { + state->Reg[0] = ADDRCMDLINE; + if (state->MemSize) + state->Reg[1] = state->MemSize; + else + state->Reg[1] = ADDRUSERSTACK; + + WriteCommandLineTo (state, state->Reg[0]); + } + else + unhandled = TRUE; + break; + + case SWI_Breakpoint: + state->EndCondition = RDIError_BreakpointReached; + state->Emulate = FALSE; + break; + + case SWI_Remove: + if (swi_mask & SWI_MASK_DEMON) + SWIremove (state, state->Reg[0]); + else + unhandled = TRUE; + break; + + case SWI_Rename: + if (swi_mask & SWI_MASK_DEMON) + SWIrename (state, state->Reg[0], state->Reg[1]); + else + unhandled = TRUE; + break; + + case SWI_IsTTY: + if (swi_mask & SWI_MASK_DEMON) + { + state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + } + else + unhandled = TRUE; + break; + + /* Handle Angel SWIs as well as Demon ones. */ + case AngelSWI_ARM: + case AngelSWI_Thumb: + if (swi_mask & SWI_MASK_ANGEL) + { + ARMword addr; + ARMword temp; + + /* R1 is almost always a parameter block. */ + addr = state->Reg[1]; + /* R0 is a reason code. */ + switch (state->Reg[0]) + { + case -1: + /* This can happen when a SWI is interrupted (eg receiving a + ctrl-C whilst processing SWIRead()). The SWI will complete + returning -1 in r0 to the caller. If GDB is then used to + resume the system call the reason code will now be -1. */ + return TRUE; + + /* Unimplemented reason codes. */ + case AngelSWI_Reason_ReadC: + case AngelSWI_Reason_TmpNam: + case AngelSWI_Reason_System: + case AngelSWI_Reason_EnterSVC: + default: + state->Emulate = FALSE; + return FALSE; + + case AngelSWI_Reason_Clock: + /* Return number of centi-seconds. */ + state->Reg[0] = +#ifdef CLOCKS_PER_SEC + (CLOCKS_PER_SEC >= 100) + ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) + : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); +#else + /* Presume unix... clock() returns microseconds. */ + (ARMword) (clock () / 10000); +#endif + OSptr->ErrorNo = errno; + break; + + case AngelSWI_Reason_Time: + state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case AngelSWI_Reason_WriteC: + { + char tmp = ARMul_SafeReadByte (state, addr); + (void) sim_callback->write_stdout (sim_callback, &tmp, 1); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + } + + case AngelSWI_Reason_Write0: + SWIWrite0 (state, addr); + break; + + case AngelSWI_Reason_Close: + state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr)); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case AngelSWI_Reason_Seek: + state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr), + ARMul_ReadWord (state, addr + 4), + SEEK_SET); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case AngelSWI_Reason_FLen: + SWIflen (state, ARMul_ReadWord (state, addr)); + break; + + case AngelSWI_Reason_GetCmdLine: + WriteCommandLineTo (state, ARMul_ReadWord (state, addr)); + break; + + case AngelSWI_Reason_HeapInfo: + /* R1 is a pointer to a pointer. */ + addr = ARMul_ReadWord (state, addr); + + /* Pick up the right memory limit. */ + if (state->MemSize) + temp = state->MemSize; + else + temp = ADDRUSERSTACK; + + ARMul_WriteWord (state, addr, 0); /* Heap base. */ + ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */ + ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */ + ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */ + break; + + case AngelSWI_Reason_ReportException: + if (state->Reg[1] == ADP_Stopped_ApplicationExit) + state->Reg[0] = 0; + else + state->Reg[0] = -1; + state->Emulate = FALSE; + break; + + case ADP_Stopped_ApplicationExit: + state->Reg[0] = 0; + state->Emulate = FALSE; + break; + + case ADP_Stopped_RunTimeError: + state->Reg[0] = -1; + state->Emulate = FALSE; + break; + + case AngelSWI_Reason_Errno: + state->Reg[0] = OSptr->ErrorNo; + break; + + case AngelSWI_Reason_Open: + SWIopen (state, + ARMul_ReadWord (state, addr), + ARMul_ReadWord (state, addr + 4)); + break; + + case AngelSWI_Reason_Read: + SWIread (state, + ARMul_ReadWord (state, addr), + ARMul_ReadWord (state, addr + 4), + ARMul_ReadWord (state, addr + 8)); + break; + + case AngelSWI_Reason_Write: + SWIwrite (state, + ARMul_ReadWord (state, addr), + ARMul_ReadWord (state, addr + 4), + ARMul_ReadWord (state, addr + 8)); + break; + + case AngelSWI_Reason_IsTTY: + state->Reg[0] = sim_callback->isatty (sim_callback, + ARMul_ReadWord (state, addr)); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case AngelSWI_Reason_Remove: + SWIremove (state, + ARMul_ReadWord (state, addr)); + + case AngelSWI_Reason_Rename: + SWIrename (state, + ARMul_ReadWord (state, addr), + ARMul_ReadWord (state, addr + 4)); + } + } + else + unhandled = TRUE; + break; + + /* The following SWIs are generated by the softvectorcode[] + installed by default by the simulator. */ + case 0x91: /* Undefined Instruction. */ + { + ARMword addr = state->RegBank[UNDEFBANK][14] - 4; + + sim_callback->printf_filtered + (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n", + ARMul_ReadWord (state, addr), addr); + state->EndCondition = RDIError_SoftwareInterrupt; + state->Emulate = FALSE; + return FALSE; + } + + case 0x90: /* Reset. */ + case 0x92: /* SWI. */ + /* These two can be safely ignored. */ + break; + + case 0x93: /* Prefetch Abort. */ + case 0x94: /* Data Abort. */ + case 0x95: /* Address Exception. */ + case 0x96: /* IRQ. */ + case 0x97: /* FIQ. */ + case 0x98: /* Error. */ + unhandled = TRUE; + break; + + case -1: + /* This can happen when a SWI is interrupted (eg receiving a + ctrl-C whilst processing SWIRead()). The SWI will complete + returning -1 in r0 to the caller. If GDB is then used to + resume the system call the reason code will now be -1. */ + return TRUE; + + case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */ + if (swi_mask & SWI_MASK_REDBOOT) + { + switch (state->Reg[0]) + { + /* These numbers are defined in libgloss/syscall.h + but the simulator should not be dependend upon + libgloss being installed. */ + case 1: /* Exit. */ + state->Emulate = FALSE; + /* Copy exit code into r0. */ + state->Reg[0] = state->Reg[1]; + break; + + case 2: /* Open. */ + SWIopen (state, state->Reg[1], state->Reg[2]); + break; + + case 3: /* Close. */ + state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case 4: /* Read. */ + SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]); + break; + + case 5: /* Write. */ + SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]); + break; + + case 6: /* Lseek. */ + state->Reg[0] = sim_callback->lseek (sim_callback, + state->Reg[1], + state->Reg[2], + state->Reg[3]); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case 17: /* Utime. */ + state->Reg[0] = (ARMword) sim_callback->time (sim_callback, + (long *) state->Reg[1]); + OSptr->ErrorNo = sim_callback->get_errno (sim_callback); + break; + + case 7: /* Unlink. */ + case 8: /* Getpid. */ + case 9: /* Kill. */ + case 10: /* Fstat. */ + case 11: /* Sbrk. */ + case 12: /* Argvlen. */ + case 13: /* Argv. */ + case 14: /* ChDir. */ + case 15: /* Stat. */ + case 16: /* Chmod. */ + case 18: /* Time. */ + sim_callback->printf_filtered + (sim_callback, + "sim: unhandled RedBoot syscall `%d' encountered - " + "returning ENOSYS\n", + state->Reg[0]); + state->Reg[0] = -1; + OSptr->ErrorNo = cb_host_to_target_errno + (sim_callback, ENOSYS); + break; + case 1001: /* Meminfo. */ + { + ARMword totmem = state->Reg[1], + topmem = state->Reg[2]; + ARMword stack = state->MemSize > 0 + ? state->MemSize : ADDRUSERSTACK; + if (totmem != 0) + ARMul_WriteWord (state, totmem, stack); + if (topmem != 0) + ARMul_WriteWord (state, topmem, stack); + state->Reg[0] = 0; + break; + } + + default: + sim_callback->printf_filtered + (sim_callback, + "sim: unknown RedBoot syscall '%d' encountered - ignoring\n", + state->Reg[0]); + return FALSE; + } + break; + } + + default: + unhandled = TRUE; + } + + if (unhandled) + { + if (SWI_vector_installed) + { + ARMword cpsr; + ARMword i_size; + + cpsr = ARMul_GetCPSR (state); + i_size = INSN_SIZE; + + ARMul_SetSPSR (state, SVC32MODE, cpsr); + + cpsr &= ~0xbf; + cpsr |= SVC32MODE | 0x80; + ARMul_SetCPSR (state, cpsr); + + state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size; + state->NextInstr = RESUME; + state->Reg[15] = state->pc = ARMSWIV; + FLUSHPIPE; + } + else + { + sim_callback->printf_filtered + (sim_callback, + "sim: unknown SWI encountered - %x - ignoring\n", + number); + return FALSE; + } + } + + return TRUE; +} + +#ifndef NOOS +#ifndef ASIM + +/* The emulator calls this routine when an Exception occurs. The second + parameter is the address of the relevant exception vector. Returning + FALSE from this routine causes the trap to be taken, TRUE causes it to + be ignored (so set state->Emulate to FALSE!). */ + +unsigned +ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED, + ARMword vector ATTRIBUTE_UNUSED, + ARMword pc ATTRIBUTE_UNUSED) +{ + return FALSE; +} + +#endif +#endif /* NOOS */ diff --git a/external/gpl3/gdb/dist/sim/arm/armos.h b/external/gpl3/gdb/dist/sim/arm/armos.h new file mode 100644 index 000000000000..ce2d5bc0e4da --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armos.h @@ -0,0 +1,94 @@ +/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* Define the initial layout of memory. */ + +#define ADDRSUPERSTACK 0x800L /* Supervisor stack space. */ +#define ADDRUSERSTACK 0x80000L/* Default user stack start. */ +#define ADDRSOFTVECTORS 0x840L /* Soft vectors are here. */ +#define ADDRCMDLINE 0xf00L /* Command line is here after a SWI GetEnv. */ +#define ADDRSOFHANDLERS 0xad0L /* Address and workspace for installed handlers. */ +#define SOFTVECTORCODE 0xb80L /* Default handlers. */ + +/* SWI numbers. */ + +#define SWI_WriteC 0x0 +#define SWI_Write0 0x2 +#define SWI_ReadC 0x4 +#define SWI_CLI 0x5 +#define SWI_GetEnv 0x10 +#define SWI_Exit 0x11 +#define SWI_EnterOS 0x16 + +#define SWI_GetErrno 0x60 +#define SWI_Clock 0x61 +#define SWI_Time 0x63 +#define SWI_Remove 0x64 +#define SWI_Rename 0x65 +#define SWI_Open 0x66 + +#define SWI_Close 0x68 +#define SWI_Write 0x69 +#define SWI_Read 0x6a +#define SWI_Seek 0x6b +#define SWI_Flen 0x6c + +#define SWI_IsTTY 0x6e +#define SWI_TmpNam 0x6f +#define SWI_InstallHandler 0x70 +#define SWI_GenerateError 0x71 + +#define SWI_Breakpoint 0x180000 /* See gdb's tm-arm.h */ + +#define AngelSWI_ARM 0x123456 +#define AngelSWI_Thumb 0xAB + +/* The reason codes: */ +#define AngelSWI_Reason_Open 0x01 +#define AngelSWI_Reason_Close 0x02 +#define AngelSWI_Reason_WriteC 0x03 +#define AngelSWI_Reason_Write0 0x04 +#define AngelSWI_Reason_Write 0x05 +#define AngelSWI_Reason_Read 0x06 +#define AngelSWI_Reason_ReadC 0x07 +#define AngelSWI_Reason_IsTTY 0x09 +#define AngelSWI_Reason_Seek 0x0A +#define AngelSWI_Reason_FLen 0x0C +#define AngelSWI_Reason_TmpNam 0x0D +#define AngelSWI_Reason_Remove 0x0E +#define AngelSWI_Reason_Rename 0x0F +#define AngelSWI_Reason_Clock 0x10 +#define AngelSWI_Reason_Time 0x11 +#define AngelSWI_Reason_System 0x12 +#define AngelSWI_Reason_Errno 0x13 +#define AngelSWI_Reason_GetCmdLine 0x15 +#define AngelSWI_Reason_HeapInfo 0x16 +#define AngelSWI_Reason_EnterSVC 0x17 +#define AngelSWI_Reason_ReportException 0x18 +#define ADP_Stopped_ApplicationExit ((2 << 16) + 38) +#define ADP_Stopped_RunTimeError ((2 << 16) + 35) + +/* Floating Point Emulator address space. */ +#define FPESTART 0x2000L +#define FPEEND 0x8000L +#define FPEOLDVECT FPESTART + 0x100L + 8L * 16L + 4L /* Stack + 8 regs + fpsr. */ +#define FPENEWVECT(addr) 0xea000000L + ((addr) >> 2) - 3L /* Branch from 4 to 0x2400. */ + +extern unsigned long fpecode[]; +extern unsigned long fpesize; + +extern int SWI_vector_installed; diff --git a/external/gpl3/gdb/dist/sim/arm/armrdi.c b/external/gpl3/gdb/dist/sim/arm/armrdi.c new file mode 100644 index 000000000000..05f1c69005ca --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armrdi.c @@ -0,0 +1,1247 @@ +/* armrdi.c -- ARMulator RDI interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include +#include +#include "armdefs.h" +#include "armemu.h" +#include "armos.h" +#include "dbg_cp.h" +#include "dbg_conf.h" +#include "dbg_rdi.h" +#include "dbg_hif.h" +#include "communicate.h" + +/***************************************************************************\ +* Declarations * +\***************************************************************************/ + +#define Watch_AnyRead (RDIWatch_ByteRead+RDIWatch_HalfRead+RDIWatch_WordRead) +#define Watch_AnyWrite (RDIWatch_ByteWrite+RDIWatch_HalfWrite+RDIWatch_WordWrite) + +static unsigned FPRegsAddr; /* last known address of FPE regs */ +#define FPESTART 0x2000L +#define FPEEND 0x8000L + +#define IGNORE(d) (d = d) +#ifdef RDI_VERBOSE +#define TracePrint(s) \ + if (rdi_log & 1) ARMul_DebugPrint s +#else +#define TracePrint(s) +#endif + +static ARMul_State *state = NULL; +static unsigned BreaksSet; /* The number of breakpoints set */ + +static int rdi_log = 0; /* debugging ? */ + +#define LOWEST_RDI_LEVEL 0 +#define HIGHEST_RDI_LEVEL 1 +static int MYrdi_level = LOWEST_RDI_LEVEL; + +typedef struct BreakNode BreakNode; +typedef struct WatchNode WatchNode; + +struct BreakNode +{ /* A breakpoint list node */ + BreakNode *next; + ARMword address; /* The address of this breakpoint */ + unsigned type; /* The type of comparison */ + ARMword bound; /* The other address for a range */ + ARMword inst; +}; + +struct WatchNode +{ /* A watchpoint list node */ + WatchNode *next; + ARMword address; /* The address of this watchpoint */ + unsigned type; /* The type of comparison */ + unsigned datatype; /* The type of access to watch for */ + ARMword bound; /* The other address for a range */ +}; + +BreakNode *BreakList = NULL; +WatchNode *WatchList = NULL; + +void +ARMul_DebugPrint_i (const Dbg_HostosInterface * hostif, const char *format, + ...) +{ + va_list ap; + va_start (ap, format); + hostif->dbgprint (hostif->dbgarg, format, ap); + va_end (ap); +} + +void +ARMul_DebugPrint (ARMul_State * state, const char *format, ...) +{ + va_list ap; + va_start (ap, format); + if (!(rdi_log & 8)) + state->hostif->dbgprint (state->hostif->dbgarg, format, ap); + va_end (ap); +} + +#define CONSOLE_PRINT_MAX_LEN 128 + +void +ARMul_ConsolePrint (ARMul_State * state, const char *format, ...) +{ + va_list ap; + int ch; + char *str, buf[CONSOLE_PRINT_MAX_LEN]; + int i, j; + ARMword junk; + + va_start (ap, format); + vsprintf (buf, format, ap); + + for (i = 0; buf[i]; i++); /* The string is i chars long */ + + str = buf; + while (i >= 32) + { + MYwrite_char (kidmum[1], RDP_OSOp); + MYwrite_word (kidmum[1], SWI_Write0); + MYwrite_char (kidmum[1], OS_SendString); + MYwrite_char (kidmum[1], 32); /* Send string 32bytes at a time */ + for (j = 0; j < 32; j++, str++) + MYwrite_char (kidmum[1], *str); + wait_for_osreply (&junk); + i -= 32; + } + + if (i > 0) + { + MYwrite_char (kidmum[1], RDP_OSOp); + MYwrite_word (kidmum[1], SWI_Write0); + MYwrite_char (kidmum[1], OS_SendString); + MYwrite_char (kidmum[1], (unsigned char) i); /* Send remainder of string */ + for (j = 0; j < i; j++, str++) + MYwrite_char (kidmum[1], *str); + wait_for_osreply (&junk); + } + + va_end (ap); + return; + +/* str = buf; */ +/* while ((ch=*str++) != 0) */ +/* state->hostif->writec(state->hostif->hostosarg, ch); */ +} + +void +ARMul_DebugPause (ARMul_State * state) +{ + if (!(rdi_log & 8)) + state->hostif->dbgpause (state->hostif->dbgarg); +} + +/***************************************************************************\ +* RDI_open * +\***************************************************************************/ + +static void +InitFail (int exitcode, char const *which) +{ + ARMul_ConsolePrint (state, "%s interface failed to initialise. Exiting\n", + which); + exit (exitcode); +} + +static void +RDIInit (unsigned type) +{ + if (type == 0) + { /* cold start */ + state->CallDebug = state->MemReadDebug = state->MemWriteDebug = 0; + BreaksSet = 0; + } +} + +#define UNKNOWNPROC 0 + +typedef struct +{ + char name[16]; + unsigned properties; +} +Processor; + +Processor const p_arm2 = { "ARM2", ARM_Fix26_Prop }; +Processor const p_arm2as = { "ARM2AS", ARM_Fix26_Prop }; +Processor const p_arm61 = { "ARM61", ARM_Fix26_Prop }; +Processor const p_arm3 = { "ARM3", ARM_Fix26_Prop }; +Processor const p_arm6 = { "ARM6", ARM_Lock_Prop }; +Processor const p_arm60 = { "ARM60", ARM_Lock_Prop }; +Processor const p_arm600 = { "ARM600", ARM_Lock_Prop }; +Processor const p_arm610 = { "ARM610", ARM_Lock_Prop }; +Processor const p_arm620 = { "ARM620", ARM_Lock_Prop }; +Processor const p_unknown = { "", 0 }; + +Processor const *const processors[] = +{ + &p_arm6, /* default: must come first */ + &p_arm2, + &p_arm2as, + &p_arm61, + &p_arm3, + &p_arm60, + &p_arm600, + &p_arm610, + &p_arm620, + &p_unknown +}; + +typedef struct ProcessorConfig ProcessorConfig; +struct ProcessorConfig +{ + long id[2]; + ProcessorConfig const *self; + long count; + Processor const *const *processors; +}; + +ProcessorConfig const processorconfig = { + {((((((long) 'x' << 8) | ' ') << 8) | 'c') << 8) | 'p', + ((((((long) 'u' << 8) | 's') << 8) | ' ') << 8) | 'x'}, + &processorconfig, + 16, + processors +}; + +static int +RDI_open (unsigned type, const Dbg_ConfigBlock * config, + const Dbg_HostosInterface * hostif, struct Dbg_MCState *dbg_state) +/* Initialise everything */ +{ + int virgin = (state == NULL); + IGNORE (dbg_state); + +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + if (virgin) + ARMul_DebugPrint_i (hostif, "RDI_open: type = %d\n", type); + else + ARMul_DebugPrint (state, "RDI_open: type = %d\n", type); + } +#endif + + if (type & 1) + { /* Warm start */ + ARMul_Reset (state); + RDIInit (1); + } + else + { + if (virgin) + { + ARMul_EmulateInit (); + state = ARMul_NewState (); + state->hostif = hostif; + { + int req = config->processor; + unsigned processor = processors[req]->val; + ARMul_SelectProcessor (state, processor); + ARMul_Reset (state); + ARMul_ConsolePrint (state, "ARMulator V1.50, %s", + processors[req]->name); + } + if (ARMul_MemoryInit (state, config->memorysize) == FALSE) + InitFail (1, "Memory"); + if (config->bytesex != RDISex_DontCare) + state->bigendSig = config->bytesex; + if (ARMul_CoProInit (state) == FALSE) + InitFail (2, "Co-Processor"); + if (ARMul_OSInit (state) == FALSE) + InitFail (3, "Operating System"); + } + ARMul_Reset (state); + RDIInit (0); + } + if (type & 2) + { /* Reset the comms link */ + /* what comms link ? */ + } + if (virgin && (type & 1) == 0) /* Cold start */ + ARMul_ConsolePrint (state, ", %s endian.\n", + state->bigendSig ? "Big" : "Little"); + + if (config->bytesex == RDISex_DontCare) + return (state->bigendSig ? RDIError_BigEndian : RDIError_LittleEndian); + else + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_close * +\***************************************************************************/ + +static int +RDI_close (void) +{ + TracePrint ((state, "RDI_close\n")); + ARMul_OSExit (state); + ARMul_CoProExit (state); + ARMul_MemoryExit (state); + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_read * +\***************************************************************************/ + +static int +RDI_read (ARMword source, void *dest, unsigned *nbytes) +{ + unsigned i; + char *memptr = (char *) dest; + + TracePrint ((state, "RDI_read: source=%.8lx dest=%p nbytes=%.8x\n", + source, dest, *nbytes)); + + for (i = 0; i < *nbytes; i++) + *memptr++ = (char) ARMul_ReadByte (state, source++); + if (state->abortSig) + { + state->abortSig = LOW; + return (RDIError_DataAbort); + } + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_write * +\***************************************************************************/ + +static int +RDI_write (const void *source, ARMword dest, unsigned *nbytes) +{ + unsigned i; + char *memptr = (char *) source; + + TracePrint ((state, "RDI_write: source=%p dest=%.8lx nbytes=%.8x\n", + source, dest, *nbytes)); + + for (i = 0; i < *nbytes; i++) + ARMul_WriteByte (state, (ARMword) dest++, (ARMword) * memptr++); + + if (state->abortSig) + { + state->abortSig = LOW; + return (RDIError_DataAbort); + } + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_CPUread * +\***************************************************************************/ + +static int +RDI_CPUread (unsigned mode, unsigned long mask, ARMword buffer[]) +{ + unsigned i, upto; + + if (mode == RDIMode_Curr) + mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS); + + for (upto = 0, i = 0; i < 15; i++) + if (mask & (1L << i)) + { + buffer[upto++] = ARMul_GetReg (state, mode, i); + } + + if (mask & RDIReg_R15) + { + buffer[upto++] = ARMul_GetR15 (state); + } + + if (mask & RDIReg_PC) + { + buffer[upto++] = ARMul_GetPC (state); + } + + if (mask & RDIReg_CPSR) + buffer[upto++] = ARMul_GetCPSR (state); + + if (mask & RDIReg_SPSR) + buffer[upto++] = ARMul_GetSPSR (state, mode); + + TracePrint ((state, "RDI_CPUread: mode=%.8x mask=%.8lx", mode, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + for (upto = 0, i = 0; i <= 20; i++) + if (mask & (1L << i)) + { + ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ', + buffer[upto]); + upto++; + } + ARMul_DebugPrint (state, "\n"); + } +#endif + + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_CPUwrite * +\***************************************************************************/ + +static int +RDI_CPUwrite (unsigned mode, unsigned long mask, ARMword const buffer[]) +{ + int i, upto; + + + TracePrint ((state, "RDI_CPUwrite: mode=%.8x mask=%.8lx", mode, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + for (upto = 0, i = 0; i <= 20; i++) + if (mask & (1L << i)) + { + ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ', + buffer[upto]); + upto++; + } + ARMul_DebugPrint (state, "\n"); + } +#endif + + if (mode == RDIMode_Curr) + mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS); + + for (upto = 0, i = 0; i < 15; i++) + if (mask & (1L << i)) + ARMul_SetReg (state, mode, i, buffer[upto++]); + + if (mask & RDIReg_R15) + ARMul_SetR15 (state, buffer[upto++]); + + if (mask & RDIReg_PC) + { + + ARMul_SetPC (state, buffer[upto++]); + } + if (mask & RDIReg_CPSR) + ARMul_SetCPSR (state, buffer[upto++]); + + if (mask & RDIReg_SPSR) + ARMul_SetSPSR (state, mode, buffer[upto++]); + + return (RDIError_NoError); +} + +/***************************************************************************\ +* RDI_CPread * +\***************************************************************************/ + +static int +RDI_CPread (unsigned CPnum, unsigned long mask, ARMword buffer[]) +{ + ARMword fpregsaddr, word[4]; + + unsigned r, w; + unsigned upto; + + if (CPnum != 1 && CPnum != 2) + { + unsigned char const *rmap = state->CPRegWords[CPnum]; + if (rmap == NULL) + return (RDIError_UnknownCoPro); + for (upto = 0, r = 0; r < rmap[-1]; r++) + if (mask & (1L << r)) + { + (void) state->CPRead[CPnum] (state, r, &buffer[upto]); + upto += rmap[r]; + } + TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx", CPnum, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + w = 0; + for (upto = 0, r = 0; r < rmap[-1]; r++) + if (mask & (1L << r)) + { + int words = rmap[r]; + ARMul_DebugPrint (state, "%c%2d", + (w >= 4 ? (w = 0, '\n') : ' '), r); + while (--words >= 0) + { + ARMul_DebugPrint (state, " %.8lx", buffer[upto++]); + w++; + } + } + ARMul_DebugPrint (state, "\n"); + } +#endif + return RDIError_NoError; + } + +#ifdef NOFPE + return RDIError_UnknownCoPro; + +#else + if (FPRegsAddr == 0) + { + fpregsaddr = ARMul_ReadWord (state, 4L); + if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */ + return RDIError_UnknownCoPro; + fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */ + if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND)) + return RDIError_UnknownCoPro; + fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */ + FPRegsAddr = fpregsaddr; + } + else + fpregsaddr = FPRegsAddr; + + if (fpregsaddr == 0) + return RDIError_UnknownCoPro; + for (upto = 0, r = 0; r < 8; r++) + if (mask & (1L << r)) + { + for (w = 0; w < 4; w++) + word[w] = + ARMul_ReadWord (state, + fpregsaddr + (ARMword) r * 16 + (ARMword) w * 4); + switch ((int) (word[3] >> 29)) + { + case 0: + case 2: + case 4: + case 6: /* its unpacked, convert to extended */ + buffer[upto++] = 2; /* mark as extended */ + buffer[upto++] = (word[3] & 0x7fff) | (word[0] & 0x80000000); /* exp and sign */ + buffer[upto++] = word[1]; /* mantissa 1 */ + buffer[upto++] = word[2]; /* mantissa 2 */ + break; + case 1: /* packed single */ + buffer[upto++] = 0; /* mark as single */ + buffer[upto++] = word[0]; /* sign, exp and mantissa */ + buffer[upto++] = word[1]; /* padding */ + buffer[upto++] = word[2]; /* padding */ + break; + case 3: /* packed double */ + buffer[upto++] = 1; /* mark as double */ + buffer[upto++] = word[0]; /* sign, exp and mantissa1 */ + buffer[upto++] = word[1]; /* mantissa 2 */ + buffer[upto++] = word[2]; /* padding */ + break; + case 5: /* packed extended */ + buffer[upto++] = 2; /* mark as extended */ + buffer[upto++] = word[0]; /* sign and exp */ + buffer[upto++] = word[1]; /* mantissa 1 */ + buffer[upto++] = word[2]; /* mantissa 2 */ + break; + case 7: /* packed decimal */ + buffer[upto++] = 3; /* mark as packed decimal */ + buffer[upto++] = word[0]; /* sign, exp and mantissa1 */ + buffer[upto++] = word[1]; /* mantissa 2 */ + buffer[upto++] = word[2]; /* mantissa 3 */ + break; + } + } + if (mask & (1L << r)) + buffer[upto++] = ARMul_ReadWord (state, fpregsaddr + 128); /* fpsr */ + if (mask & (1L << (r + 1))) + buffer[upto++] = 0; /* fpcr */ + + TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx\n", CPnum, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + for (upto = 0, r = 0; r < 9; r++) + if (mask & (1L << r)) + { + if (r != 8) + { + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + } + ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]); + } + ARMul_DebugPrint (state, "\n"); + } +#endif + return (RDIError_NoError); +#endif /* NOFPE */ +} + +/***************************************************************************\ +* RDI_CPwrite * +\***************************************************************************/ + +static int +RDI_CPwrite (unsigned CPnum, unsigned long mask, ARMword const buffer[]) +{ + unsigned r; + unsigned upto; + ARMword fpregsaddr; + + if (CPnum != 1 && CPnum != 2) + { + unsigned char const *rmap = state->CPRegWords[CPnum]; + if (rmap == NULL) + return (RDIError_UnknownCoPro); + TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + int w = 0; + for (upto = 0, r = 0; r < rmap[-1]; r++) + if (mask & (1L << r)) + { + int words = rmap[r]; + ARMul_DebugPrint (state, "%c%2d", + (w >= 4 ? (w = 0, '\n') : ' '), r); + while (--words >= 0) + { + ARMul_DebugPrint (state, " %.8lx", buffer[upto++]); + w++; + } + } + ARMul_DebugPrint (state, "\n"); + } +#endif + for (upto = 0, r = 0; r < rmap[-1]; r++) + if (mask & (1L << r)) + { + (void) state->CPWrite[CPnum] (state, r, &buffer[upto]); + upto += rmap[r]; + } + return RDIError_NoError; + } + +#ifdef NOFPE + return RDIError_UnknownCoPro; + +#else + TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask)); +#ifdef RDI_VERBOSE + if (rdi_log & 1) + { + for (upto = 0, r = 0; r < 9; r++) + if (mask & (1L << r)) + { + if (r != 8) + { + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); + } + ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]); + } + ARMul_DebugPrint (state, "\n"); + } +#endif + + if (FPRegsAddr == 0) + { + fpregsaddr = ARMul_ReadWord (state, 4L); + if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */ + return RDIError_UnknownCoPro; + fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */ + if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND)) + return RDIError_UnknownCoPro; + fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */ + FPRegsAddr = fpregsaddr; + } + else + fpregsaddr = FPRegsAddr; + + if (fpregsaddr == 0) + return RDIError_UnknownCoPro; + for (upto = 0, r = 0; r < 8; r++) + if (mask & (1L << r)) + { + ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16, + buffer[upto + 1]); + ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 4, + buffer[upto + 2]); + ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 8, + buffer[upto + 3]); + ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 12, + (buffer[upto] * 2 + 1) << 29); /* mark type */ + upto += 4; + } + if (mask & (1L << r)) + ARMul_WriteWord (state, fpregsaddr + 128, buffer[upto++]); /* fpsr */ + return (RDIError_NoError); +#endif /* NOFPE */ +} + +static void +deletebreaknode (BreakNode ** prevp) +{ + BreakNode *p = *prevp; + *prevp = p->next; + ARMul_WriteWord (state, p->address, p->inst); + free ((char *) p); + BreaksSet--; + state->CallDebug--; +} + +static int +removebreak (ARMword address, unsigned type) +{ + BreakNode *p, **prevp = &BreakList; + for (; (p = *prevp) != NULL; prevp = &p->next) + if (p->address == address && p->type == type) + { + deletebreaknode (prevp); + return TRUE; + } + return FALSE; +} + +/* This routine installs a breakpoint into the breakpoint table */ + +static BreakNode * +installbreak (ARMword address, unsigned type, ARMword bound) +{ + BreakNode *p = (BreakNode *) malloc (sizeof (BreakNode)); + p->next = BreakList; + BreakList = p; + p->address = address; + p->type = type; + p->bound = bound; + p->inst = ARMul_ReadWord (state, address); + ARMul_WriteWord (state, address, 0xee000000L); + return p; +} + +/***************************************************************************\ +* RDI_setbreak * +\***************************************************************************/ + +static int +RDI_setbreak (ARMword address, unsigned type, ARMword bound, + PointHandle * handle) +{ + BreakNode *p; + TracePrint ((state, "RDI_setbreak: address=%.8lx type=%d bound=%.8lx\n", + address, type, bound)); + + removebreak (address, type); + p = installbreak (address, type, bound); + BreaksSet++; + state->CallDebug++; + *handle = (PointHandle) p; + TracePrint ((state, " returns %.8lx\n", *handle)); + return RDIError_NoError; +} + +/***************************************************************************\ +* RDI_clearbreak * +\***************************************************************************/ + +static int +RDI_clearbreak (PointHandle handle) +{ + TracePrint ((state, "RDI_clearbreak: address=%.8lx\n", handle)); + { + BreakNode *p, **prevp = &BreakList; + for (; (p = *prevp) != NULL; prevp = &p->next) + if (p == (BreakNode *) handle) + break; + if (p == NULL) + return RDIError_NoSuchPoint; + deletebreaknode (prevp); + return RDIError_NoError; + } +} + +/***************************************************************************\ +* Internal functions for breakpoint table manipulation * +\***************************************************************************/ + +static void +deletewatchnode (WatchNode ** prevp) +{ + WatchNode *p = *prevp; + if (p->datatype & Watch_AnyRead) + state->MemReadDebug--; + if (p->datatype & Watch_AnyWrite) + state->MemWriteDebug--; + *prevp = p->next; + free ((char *) p); +} + +int +removewatch (ARMword address, unsigned type) +{ + WatchNode *p, **prevp = &WatchList; + for (; (p = *prevp) != NULL; prevp = &p->next) + if (p->address == address && p->type == type) + { /* found a match */ + deletewatchnode (prevp); + return TRUE; + } + return FALSE; /* never found a match */ +} + +static WatchNode * +installwatch (ARMword address, unsigned type, unsigned datatype, + ARMword bound) +{ + WatchNode *p = (WatchNode *) malloc (sizeof (WatchNode)); + p->next = WatchList; + WatchList = p; + p->address = address; + p->type = type; + p->datatype = datatype; + p->bound = bound; + return p; +} + +/***************************************************************************\ +* RDI_setwatch * +\***************************************************************************/ + +static int +RDI_setwatch (ARMword address, unsigned type, unsigned datatype, + ARMword bound, PointHandle * handle) +{ + WatchNode *p; + TracePrint ( + (state, + "RDI_setwatch: address=%.8lx type=%d datatype=%d bound=%.8lx", + address, type, datatype, bound)); + + if (!state->CanWatch) + return RDIError_UnimplementedMessage; + + removewatch (address, type); + p = installwatch (address, type, datatype, bound); + if (datatype & Watch_AnyRead) + state->MemReadDebug++; + if (datatype & Watch_AnyWrite) + state->MemWriteDebug++; + *handle = (PointHandle) p; + TracePrint ((state, " returns %.8lx\n", *handle)); + return RDIError_NoError; +} + +/***************************************************************************\ +* RDI_clearwatch * +\***************************************************************************/ + +static int +RDI_clearwatch (PointHandle handle) +{ + TracePrint ((state, "RDI_clearwatch: address=%.8lx\n", handle)); + { + WatchNode *p, **prevp = &WatchList; + for (; (p = *prevp) != NULL; prevp = &p->next) + if (p == (WatchNode *) handle) + break; + if (p == NULL) + return RDIError_NoSuchPoint; + deletewatchnode (prevp); + return RDIError_NoError; + } +} + +/***************************************************************************\ +* RDI_execute * +\***************************************************************************/ + +static int +RDI_execute (PointHandle * handle) +{ + TracePrint ((state, "RDI_execute\n")); + if (rdi_log & 4) + { + state->CallDebug++; + state->Debug = TRUE; + } + state->EndCondition = RDIError_NoError; + state->StopHandle = 0; + + ARMul_DoProg (state); + + *handle = state->StopHandle; + state->Reg[15] -= 8; /* undo the pipeline */ + if (rdi_log & 4) + { + state->CallDebug--; + state->Debug = FALSE; + } + return (state->EndCondition); +} + +/***************************************************************************\ +* RDI_step * +\***************************************************************************/ + +static int +RDI_step (unsigned ninstr, PointHandle * handle) +{ + + TracePrint ((state, "RDI_step\n")); + if (ninstr != 1) + return RDIError_UnimplementedMessage; + if (rdi_log & 4) + { + state->CallDebug++; + state->Debug = TRUE; + } + state->EndCondition = RDIError_NoError; + state->StopHandle = 0; + ARMul_DoInstr (state); + *handle = state->StopHandle; + state->Reg[15] -= 8; /* undo the pipeline */ + if (rdi_log & 4) + { + state->CallDebug--; + state->Debug = FALSE; + } + return (state->EndCondition); +} + +/***************************************************************************\ +* RDI_info * +\***************************************************************************/ + +static int +RDI_info (unsigned type, ARMword * arg1, ARMword * arg2) +{ + switch (type) + { + case RDIInfo_Target: + TracePrint ((state, "RDI_Info_Target\n")); + /* Emulator, speed 10**5 IPS */ + *arg1 = 5 | HIGHEST_RDI_LEVEL << 5 | LOWEST_RDI_LEVEL << 8; + *arg2 = 1298224434; + return RDIError_NoError; + + case RDIInfo_Points: + { + ARMword n = RDIPointCapability_Comparison | RDIPointCapability_Range | + RDIPointCapability_Mask | RDIPointCapability_Status; + TracePrint ((state, "RDI_Info_Points\n")); + if (state->CanWatch) + n |= (Watch_AnyRead + Watch_AnyWrite) << 2; + *arg1 = n; + return RDIError_NoError; + } + + case RDIInfo_Step: + TracePrint ((state, "RDI_Info_Step\n")); + *arg1 = RDIStep_Single; + return RDIError_NoError; + + case RDIInfo_MMU: + TracePrint ((state, "RDI_Info_MMU\n")); + *arg1 = 1313820229; + return RDIError_NoError; + + case RDISignal_Stop: + TracePrint ((state, "RDISignal_Stop\n")); + state->CallDebug++; + state->EndCondition = RDIError_UserInterrupt; + return RDIError_NoError; + + case RDIVector_Catch: + TracePrint ((state, "RDIVector_Catch %.8lx\n", *arg1)); + state->VectorCatch = (unsigned) *arg1; + return RDIError_NoError; + + case RDISet_Cmdline: + TracePrint ((state, "RDI_Set_Cmdline %s\n", (char *) arg1)); + state->CommandLine = + (char *) malloc ((unsigned) strlen ((char *) arg1) + 1); + (void) strcpy (state->CommandLine, (char *) arg1); + return RDIError_NoError; + + case RDICycles: + TracePrint ((state, "RDI_Info_Cycles\n")); + arg1[0] = 0; + arg1[1] = state->NumInstrs; + arg1[2] = 0; + arg1[3] = state->NumScycles; + arg1[4] = 0; + arg1[5] = state->NumNcycles; + arg1[6] = 0; + arg1[7] = state->NumIcycles; + arg1[8] = 0; + arg1[9] = state->NumCcycles; + arg1[10] = 0; + arg1[11] = state->NumFcycles; + return RDIError_NoError; + + case RDIErrorP: + *arg1 = ARMul_OSLastErrorP (state); + TracePrint ((state, "RDI_ErrorP returns %ld\n", *arg1)); + return RDIError_NoError; + + case RDIInfo_DescribeCoPro: + { + int cpnum = *(int *) arg1; + struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2; + int i; + unsigned char const *map = state->CPRegWords[cpnum]; + if (map == NULL) + return RDIError_UnknownCoPro; + for (i = 0; i < cpd->entries; i++) + { + unsigned r, w = cpd->regdesc[i].nbytes / sizeof (ARMword); + for (r = cpd->regdesc[i].rmin; r <= cpd->regdesc[i].rmax; r++) + if (map[r] != w) + return RDIError_BadCoProState; + } + return RDIError_NoError; + } + + case RDIInfo_RequestCoProDesc: + { + int cpnum = *(int *) arg1; + struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2; + int i = -1, lastw = -1, r; + unsigned char const *map; + if ((unsigned) cpnum >= 16) + return RDIError_UnknownCoPro; + map = state->CPRegWords[cpnum]; + if (map == NULL) + return RDIError_UnknownCoPro; + for (r = 0; r < map[-1]; r++) + { + int words = map[r]; + if (words == lastw) + cpd->regdesc[i].rmax = r; + else + { + if (++i >= cpd->entries) + return RDIError_BufferFull; + cpd->regdesc[i].rmax = cpd->regdesc[i].rmin = r; + cpd->regdesc[i].nbytes = words * sizeof (ARMword); + cpd->regdesc[i].access = + Dbg_Access_Readable + Dbg_Access_Writable; + } + } + cpd->entries = i + 1; + return RDIError_NoError; + } + + case RDIInfo_Log: + *arg1 = (ARMword) rdi_log; + return RDIError_NoError; + + case RDIInfo_SetLog: + rdi_log = (int) *arg1; + return RDIError_NoError; + + case RDIInfo_CoPro: + return RDIError_NoError; + + case RDIPointStatus_Watch: + { + WatchNode *p, *handle = (WatchNode *) * arg1; + for (p = WatchList; p != NULL; p = p->next) + if (p == handle) + { + *arg1 = -1; + *arg2 = 1; + return RDIError_NoError; + } + return RDIError_NoSuchPoint; + } + + case RDIPointStatus_Break: + { + BreakNode *p, *handle = (BreakNode *) * arg1; + for (p = BreakList; p != NULL; p = p->next) + if (p == handle) + { + *arg1 = -1; + *arg2 = 1; + return RDIError_NoError; + } + return RDIError_NoSuchPoint; + } + + case RDISet_RDILevel: + if (*arg1 < LOWEST_RDI_LEVEL || *arg1 > HIGHEST_RDI_LEVEL) + return RDIError_IncompatibleRDILevels; + MYrdi_level = *arg1; + return RDIError_NoError; + + default: + return RDIError_UnimplementedMessage; + + } +} + +/***************************************************************************\ +* The emulator calls this routine at the beginning of every cycle when the * +* CallDebug flag is set. The second parameter passed is the address of the * +* currently executing instruction (i.e Program Counter - 8), the third * +* parameter is the instruction being executed. * +\***************************************************************************/ + +ARMword +ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr) +{ + + if (state->EndCondition == RDIError_UserInterrupt) + { + TracePrint ((state, "User interrupt at %.8lx\n", pc)); + state->CallDebug--; + state->Emulate = STOP; + } + else + { + BreakNode *p = BreakList; + for (; p != NULL; p = p->next) + { + switch (p->type) + { + case RDIPoint_EQ: + if (pc == p->address) + break; + continue; + case RDIPoint_GT: + if (pc > p->address) + break; + continue; + case RDIPoint_GE: + if (pc >= p->address) + break; + continue; + case RDIPoint_LT: + if (pc < p->address) + break; + continue; + case RDIPoint_LE: + if (pc <= p->address) + break; + continue; + case RDIPoint_IN: + if (p->address <= pc && pc < p->address + p->bound) + break; + continue; + case RDIPoint_OUT: + if (p->address > pc || pc >= p->address + p->bound) + break; + continue; + case RDIPoint_MASK: + if ((pc & p->bound) == p->address) + break; + continue; + } + /* found a match */ + TracePrint ((state, "Breakpoint reached at %.8lx\n", pc)); + state->EndCondition = RDIError_BreakpointReached; + state->Emulate = STOP; + state->StopHandle = (ARMword) p; + break; + } + } + return instr; +} + +void +ARMul_CheckWatch (ARMul_State * state, ARMword addr, int access) +{ + WatchNode *p; + for (p = WatchList; p != NULL; p = p->next) + if (p->datatype & access) + { + switch (p->type) + { + case RDIPoint_EQ: + if (addr == p->address) + break; + continue; + case RDIPoint_GT: + if (addr > p->address) + break; + continue; + case RDIPoint_GE: + if (addr >= p->address) + break; + continue; + case RDIPoint_LT: + if (addr < p->address) + break; + continue; + case RDIPoint_LE: + if (addr <= p->address) + break; + continue; + case RDIPoint_IN: + if (p->address <= addr && addr < p->address + p->bound) + break; + continue; + case RDIPoint_OUT: + if (p->address > addr || addr >= p->address + p->bound) + break; + continue; + case RDIPoint_MASK: + if ((addr & p->bound) == p->address) + break; + continue; + } + /* found a match */ + TracePrint ((state, "Watchpoint at %.8lx accessed\n", addr)); + state->EndCondition = RDIError_WatchpointAccessed; + state->Emulate = STOP; + state->StopHandle = (ARMword) p; + return; + } +} + +static RDI_NameList const * +RDI_cpunames () +{ + return (RDI_NameList const *) &processorconfig.count; +} + +const struct RDIProcVec armul_rdi = { + "ARMUL", + RDI_open, + RDI_close, + RDI_read, + RDI_write, + RDI_CPUread, + RDI_CPUwrite, + RDI_CPread, + RDI_CPwrite, + RDI_setbreak, + RDI_clearbreak, + RDI_setwatch, + RDI_clearwatch, + RDI_execute, + RDI_step, + RDI_info, + + 0, /*pointinq */ + 0, /*addconfig */ + 0, /*loadconfigdata */ + 0, /*selectconfig */ + 0, /*drivernames */ + + RDI_cpunames +}; diff --git a/external/gpl3/gdb/dist/sim/arm/armsupp.c b/external/gpl3/gdb/dist/sim/arm/armsupp.c new file mode 100644 index 000000000000..b8e1d385ccd3 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armsupp.c @@ -0,0 +1,821 @@ +/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "armdefs.h" +#include "armemu.h" +#include "ansidecl.h" + +/* Definitions for the support routines. */ + +static ARMword ModeToBank (ARMword); +static void EnvokeList (ARMul_State *, unsigned long, unsigned long); + +struct EventNode +{ /* An event list node. */ + unsigned (*func) (ARMul_State *); /* The function to call. */ + struct EventNode *next; +}; + +/* This routine returns the value of a register from a mode. */ + +ARMword +ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg) +{ + mode &= MODEBITS; + if (mode != state->Mode) + return (state->RegBank[ModeToBank ((ARMword) mode)][reg]); + else + return (state->Reg[reg]); +} + +/* This routine sets the value of a register for a mode. */ + +void +ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value) +{ + mode &= MODEBITS; + if (mode != state->Mode) + state->RegBank[ModeToBank ((ARMword) mode)][reg] = value; + else + state->Reg[reg] = value; +} + +/* This routine returns the value of the PC, mode independently. */ + +ARMword +ARMul_GetPC (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return state->Reg[15]; + else + return R15PC; +} + +/* This routine returns the value of the PC, mode independently. */ + +ARMword +ARMul_GetNextPC (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return state->Reg[15] + isize; + else + return (state->Reg[15] + isize) & R15PCBITS; +} + +/* This routine sets the value of the PC. */ + +void +ARMul_SetPC (ARMul_State * state, ARMword value) +{ + if (ARMul_MODE32BIT) + state->Reg[15] = value & PCBITS; + else + state->Reg[15] = R15CCINTMODE | (value & R15PCBITS); + FLUSHPIPE; +} + +/* This routine returns the value of register 15, mode independently. */ + +ARMword +ARMul_GetR15 (ARMul_State * state) +{ + if (state->Mode > SVC26MODE) + return (state->Reg[15]); + else + return (R15PC | ECC | ER15INT | EMODE); +} + +/* This routine sets the value of Register 15. */ + +void +ARMul_SetR15 (ARMul_State * state, ARMword value) +{ + if (ARMul_MODE32BIT) + state->Reg[15] = value & PCBITS; + else + { + state->Reg[15] = value; + ARMul_R15Altered (state); + } + FLUSHPIPE; +} + +/* This routine returns the value of the CPSR. */ + +ARMword +ARMul_GetCPSR (ARMul_State * state) +{ + return (CPSR | state->Cpsr); +} + +/* This routine sets the value of the CPSR. */ + +void +ARMul_SetCPSR (ARMul_State * state, ARMword value) +{ + state->Cpsr = value; + ARMul_CPSRAltered (state); +} + +/* This routine does all the nasty bits involved in a write to the CPSR, + including updating the register bank, given a MSR instruction. */ + +void +ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) +{ + state->Cpsr = ARMul_GetCPSR (state); + + if (state->Mode != USER26MODE + && state->Mode != USER32MODE) + { + /* In user mode, only write flags. */ + if (BIT (16)) + SETPSR_C (state->Cpsr, rhs); + if (BIT (17)) + SETPSR_X (state->Cpsr, rhs); + if (BIT (18)) + SETPSR_S (state->Cpsr, rhs); + } + if (BIT (19)) + SETPSR_F (state->Cpsr, rhs); + ARMul_CPSRAltered (state); +} + +/* Get an SPSR from the specified mode. */ + +ARMword +ARMul_GetSPSR (ARMul_State * state, ARMword mode) +{ + ARMword bank = ModeToBank (mode & MODEBITS); + + if (! BANK_CAN_ACCESS_SPSR (bank)) + return ARMul_GetCPSR (state); + + return state->Spsr[bank]; +} + +/* This routine does a write to an SPSR. */ + +void +ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) +{ + ARMword bank = ModeToBank (mode & MODEBITS); + + if (BANK_CAN_ACCESS_SPSR (bank)) + state->Spsr[bank] = value; +} + +/* This routine does a write to the current SPSR, given an MSR instruction. */ + +void +ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs) +{ + if (BANK_CAN_ACCESS_SPSR (state->Bank)) + { + if (BIT (16)) + SETPSR_C (state->Spsr[state->Bank], rhs); + if (BIT (17)) + SETPSR_X (state->Spsr[state->Bank], rhs); + if (BIT (18)) + SETPSR_S (state->Spsr[state->Bank], rhs); + if (BIT (19)) + SETPSR_F (state->Spsr[state->Bank], rhs); + } +} + +/* This routine updates the state of the emulator after the Cpsr has been + changed. Both the processor flags and register bank are updated. */ + +void +ARMul_CPSRAltered (ARMul_State * state) +{ + ARMword oldmode; + + if (state->prog32Sig == LOW) + state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS); + + oldmode = state->Mode; + + if (state->Mode != (state->Cpsr & MODEBITS)) + { + state->Mode = + ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS); + + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + } + state->Cpsr &= ~MODEBITS; + + ASSIGNINT (state->Cpsr & INTBITS); + state->Cpsr &= ~INTBITS; + ASSIGNN ((state->Cpsr & NBIT) != 0); + state->Cpsr &= ~NBIT; + ASSIGNZ ((state->Cpsr & ZBIT) != 0); + state->Cpsr &= ~ZBIT; + ASSIGNC ((state->Cpsr & CBIT) != 0); + state->Cpsr &= ~CBIT; + ASSIGNV ((state->Cpsr & VBIT) != 0); + state->Cpsr &= ~VBIT; + ASSIGNS ((state->Cpsr & SBIT) != 0); + state->Cpsr &= ~SBIT; +#ifdef MODET + ASSIGNT ((state->Cpsr & TBIT) != 0); + state->Cpsr &= ~TBIT; +#endif + + if (oldmode > SVC26MODE) + { + if (state->Mode <= SVC26MODE) + { + state->Emulate = CHANGEMODE; + state->Reg[15] = ECC | ER15INT | EMODE | R15PC; + } + } + else + { + if (state->Mode > SVC26MODE) + { + state->Emulate = CHANGEMODE; + state->Reg[15] = R15PC; + } + else + state->Reg[15] = ECC | ER15INT | EMODE | R15PC; + } +} + +/* This routine updates the state of the emulator after register 15 has + been changed. Both the processor flags and register bank are updated. + This routine should only be called from a 26 bit mode. */ + +void +ARMul_R15Altered (ARMul_State * state) +{ + if (state->Mode != R15MODE) + { + state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE); + state->NtransSig = (state->Mode & 3) ? HIGH : LOW; + } + + if (state->Mode > SVC26MODE) + state->Emulate = CHANGEMODE; + + ASSIGNR15INT (R15INT); + + ASSIGNN ((state->Reg[15] & NBIT) != 0); + ASSIGNZ ((state->Reg[15] & ZBIT) != 0); + ASSIGNC ((state->Reg[15] & CBIT) != 0); + ASSIGNV ((state->Reg[15] & VBIT) != 0); +} + +/* This routine controls the saving and restoring of registers across mode + changes. The regbank matrix is largely unused, only rows 13 and 14 are + used across all modes, 8 to 14 are used for FIQ, all others use the USER + column. It's easier this way. old and new parameter are modes numbers. + Notice the side effect of changing the Bank variable. */ + +ARMword +ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode) +{ + unsigned i; + ARMword oldbank; + ARMword newbank; + + oldbank = ModeToBank (oldmode); + newbank = state->Bank = ModeToBank (newmode); + + /* Do we really need to do it? */ + if (oldbank != newbank) + { + /* Save away the old registers. */ + switch (oldbank) + { + case USERBANK: + case IRQBANK: + case SVCBANK: + case ABORTBANK: + case UNDEFBANK: + if (newbank == FIQBANK) + for (i = 8; i < 13; i++) + state->RegBank[USERBANK][i] = state->Reg[i]; + state->RegBank[oldbank][13] = state->Reg[13]; + state->RegBank[oldbank][14] = state->Reg[14]; + break; + case FIQBANK: + for (i = 8; i < 15; i++) + state->RegBank[FIQBANK][i] = state->Reg[i]; + break; + case DUMMYBANK: + for (i = 8; i < 15; i++) + state->RegBank[DUMMYBANK][i] = 0; + break; + default: + abort (); + } + + /* Restore the new registers. */ + switch (newbank) + { + case USERBANK: + case IRQBANK: + case SVCBANK: + case ABORTBANK: + case UNDEFBANK: + if (oldbank == FIQBANK) + for (i = 8; i < 13; i++) + state->Reg[i] = state->RegBank[USERBANK][i]; + state->Reg[13] = state->RegBank[newbank][13]; + state->Reg[14] = state->RegBank[newbank][14]; + break; + case FIQBANK: + for (i = 8; i < 15; i++) + state->Reg[i] = state->RegBank[FIQBANK][i]; + break; + case DUMMYBANK: + for (i = 8; i < 15; i++) + state->Reg[i] = 0; + break; + default: + abort (); + } + } + + return newmode; +} + +/* Given a processor mode, this routine returns the + register bank that will be accessed in that mode. */ + +static ARMword +ModeToBank (ARMword mode) +{ + static ARMword bankofmode[] = + { + USERBANK, FIQBANK, IRQBANK, SVCBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, + USERBANK, FIQBANK, IRQBANK, SVCBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK, + DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK + }; + + if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0]))) + return DUMMYBANK; + + return bankofmode[mode]; +} + +/* Returns the register number of the nth register in a reg list. */ + +unsigned +ARMul_NthReg (ARMword instr, unsigned number) +{ + unsigned bit, upto; + + for (bit = 0, upto = 0; upto <= number; bit ++) + if (BIT (bit)) + upto ++; + + return (bit - 1); +} + +/* Assigns the N and Z flags depending on the value of result. */ + +void +ARMul_NegZero (ARMul_State * state, ARMword result) +{ + if (NEG (result)) + { + SETN; + CLEARZ; + } + else if (result == 0) + { + CLEARN; + SETZ; + } + else + { + CLEARN; + CLEARZ; + } +} + +/* Compute whether an addition of A and B, giving RESULT, overflowed. */ + +int +AddOverflow (ARMword a, ARMword b, ARMword result) +{ + return ((NEG (a) && NEG (b) && POS (result)) + || (POS (a) && POS (b) && NEG (result))); +} + +/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */ + +int +SubOverflow (ARMword a, ARMword b, ARMword result) +{ + return ((NEG (a) && POS (b) && POS (result)) + || (POS (a) && NEG (b) && NEG (result))); +} + +/* Assigns the C flag after an addition of a and b to give result. */ + +void +ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNC ((NEG (a) && NEG (b)) || + (NEG (a) && POS (result)) || (NEG (b) && POS (result))); +} + +/* Assigns the V flag after an addition of a and b to give result. */ + +void +ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNV (AddOverflow (a, b, result)); +} + +/* Assigns the C flag after an subtraction of a and b to give result. */ + +void +ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNC ((NEG (a) && POS (b)) || + (NEG (a) && POS (result)) || (POS (b) && POS (result))); +} + +/* Assigns the V flag after an subtraction of a and b to give result. */ + +void +ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) +{ + ASSIGNV (SubOverflow (a, b, result)); +} + +/* This function does the work of generating the addresses used in an + LDC instruction. The code here is always post-indexed, it's up to the + caller to get the input address correct and to handle base register + modification. It also handles the Busy-Waiting. */ + +void +ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address) +{ + unsigned cpab; + ARMword data; + + UNDEF_LSCPCBaseWb; + + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + return; + } + + if (ADDREXCEPT (address)) + INTERNALABORT (address); + + cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0); + while (cpab == ARMul_BUSY) + { + ARMul_Icycles (state, 1, 0); + + if (IntPending (state)) + { + cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); + return; + } + else + cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0); + } + if (cpab == ARMul_CANT) + { + CPTAKEABORT; + return; + } + + cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0); + data = ARMul_LoadWordN (state, address); + BUSUSEDINCPCN; + + if (BIT (21)) + LSBase = state->Base; + cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); + + while (cpab == ARMul_INC) + { + address += 4; + data = ARMul_LoadWordN (state, address); + cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); + } + + if (state->abortSig || state->Aborted) + TAKEABORT; +} + +/* This function does the work of generating the addresses used in an + STC instruction. The code here is always post-indexed, it's up to the + caller to get the input address correct and to handle base register + modification. It also handles the Busy-Waiting. */ + +void +ARMul_STC (ARMul_State * state, ARMword instr, ARMword address) +{ + unsigned cpab; + ARMword data; + + UNDEF_LSCPCBaseWb; + + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + return; + } + + if (ADDREXCEPT (address) || VECTORACCESS (address)) + INTERNALABORT (address); + + cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data); + while (cpab == ARMul_BUSY) + { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) + { + cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); + return; + } + else + cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data); + } + + if (cpab == ARMul_CANT) + { + CPTAKEABORT; + return; + } +#ifndef MODE32 + if (ADDREXCEPT (address) || VECTORACCESS (address)) + INTERNALABORT (address); +#endif + BUSUSEDINCPCN; + if (BIT (21)) + LSBase = state->Base; + cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); + ARMul_StoreWordN (state, address, data); + + while (cpab == ARMul_INC) + { + address += 4; + cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); + ARMul_StoreWordN (state, address, data); + } + + if (state->abortSig || state->Aborted) + TAKEABORT; +} + +/* This function does the Busy-Waiting for an MCR instruction. */ + +void +ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) +{ + unsigned cpab; + + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + return; + } + + cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); + + while (cpab == ARMul_BUSY) + { + ARMul_Icycles (state, 1, 0); + + if (IntPending (state)) + { + cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0); + return; + } + else + cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source); + } + + if (cpab == ARMul_CANT) + ARMul_Abort (state, ARMul_UndefinedInstrV); + else + { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + } +} + +/* This function does the Busy-Waiting for an MRC instruction. */ + +ARMword +ARMul_MRC (ARMul_State * state, ARMword instr) +{ + unsigned cpab; + ARMword result = 0; + + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + return; + } + + cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); + while (cpab == ARMul_BUSY) + { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) + { + cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0); + return (0); + } + else + cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result); + } + if (cpab == ARMul_CANT) + { + ARMul_Abort (state, ARMul_UndefinedInstrV); + /* Parent will destroy the flags otherwise. */ + result = ECC; + } + else + { + BUSUSEDINCPCN; + ARMul_Ccycles (state, 1, 0); + ARMul_Icycles (state, 1, 0); + } + + return result; +} + +/* This function does the Busy-Waiting for an CDP instruction. */ + +void +ARMul_CDP (ARMul_State * state, ARMword instr) +{ + unsigned cpab; + + if (! CP_ACCESS_ALLOWED (state, CPNum)) + { + ARMul_UndefInstr (state, instr); + return; + } + + cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr); + while (cpab == ARMul_BUSY) + { + ARMul_Icycles (state, 1, 0); + if (IntPending (state)) + { + cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr); + return; + } + else + cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr); + } + if (cpab == ARMul_CANT) + ARMul_Abort (state, ARMul_UndefinedInstrV); + else + BUSUSEDN; +} + +/* This function handles Undefined instructions, as CP isntruction. */ + +void +ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED) +{ + ARMul_Abort (state, ARMul_UndefinedInstrV); +} + +/* Return TRUE if an interrupt is pending, FALSE otherwise. */ + +unsigned +IntPending (ARMul_State * state) +{ + if (state->Exception) + { + /* Any exceptions. */ + if (state->NresetSig == LOW) + { + ARMul_Abort (state, ARMul_ResetV); + return TRUE; + } + else if (!state->NfiqSig && !FFLAG) + { + ARMul_Abort (state, ARMul_FIQV); + return TRUE; + } + else if (!state->NirqSig && !IFLAG) + { + ARMul_Abort (state, ARMul_IRQV); + return TRUE; + } + } + + return FALSE; +} + +/* Align a word access to a non word boundary. */ + +ARMword +ARMul_Align (state, address, data) + ARMul_State * state ATTRIBUTE_UNUSED; + ARMword address; + ARMword data; +{ + /* This code assumes the address is really unaligned, + as a shift by 32 is undefined in C. */ + + address = (address & 3) << 3; /* Get the word address. */ + return ((data >> address) | (data << (32 - address))); /* rot right */ +} + +/* This routine is used to call another routine after a certain number of + cycles have been executed. The first parameter is the number of cycles + delay before the function is called, the second argument is a pointer + to the function. A delay of zero doesn't work, just call the function. */ + +void +ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay, + unsigned (*what) (ARMul_State *)) +{ + unsigned long when; + struct EventNode *event; + + if (state->EventSet++ == 0) + state->Now = ARMul_Time (state); + when = (state->Now + delay) % EVENTLISTSIZE; + event = (struct EventNode *) malloc (sizeof (struct EventNode)); + event->func = what; + event->next = *(state->EventPtr + when); + *(state->EventPtr + when) = event; +} + +/* This routine is called at the beginning of + every cycle, to envoke scheduled events. */ + +void +ARMul_EnvokeEvent (ARMul_State * state) +{ + static unsigned long then; + + then = state->Now; + state->Now = ARMul_Time (state) % EVENTLISTSIZE; + if (then < state->Now) + /* Schedule events. */ + EnvokeList (state, then, state->Now); + else if (then > state->Now) + { + /* Need to wrap around the list. */ + EnvokeList (state, then, EVENTLISTSIZE - 1L); + EnvokeList (state, 0L, state->Now); + } +} + +/* Envokes all the entries in a range. */ + +static void +EnvokeList (ARMul_State * state, unsigned long from, unsigned long to) +{ + for (; from <= to; from++) + { + struct EventNode *anevent; + + anevent = *(state->EventPtr + from); + while (anevent) + { + (anevent->func) (state); + state->EventSet--; + anevent = anevent->next; + } + *(state->EventPtr + from) = NULL; + } +} + +/* This routine is returns the number of clock ticks since the last reset. */ + +unsigned long +ARMul_Time (ARMul_State * state) +{ + return (state->NumScycles + state->NumNcycles + + state->NumIcycles + state->NumCcycles + state->NumFcycles); +} diff --git a/external/gpl3/gdb/dist/sim/arm/armvirt.c b/external/gpl3/gdb/dist/sim/arm/armvirt.c new file mode 100644 index 000000000000..969085d24f4d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/armvirt.c @@ -0,0 +1,522 @@ +/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* This file contains a complete ARMulator memory model, modelling a +"virtual memory" system. A much simpler model can be found in armfast.c, +and that model goes faster too, but has a fixed amount of memory. This +model's memory has 64K pages, allocated on demand from a 64K entry page +table. The routines PutWord and GetWord implement this. Pages are never +freed as they might be needed again. A single area of memory may be +defined to generate aborts. */ + +#include "armopts.h" +#include "armos.h" +#include "armdefs.h" +#include "ansidecl.h" + +#ifdef VALIDATE /* for running the validate suite */ +#define TUBE 48 * 1024 * 1024 /* write a char on the screen */ +#define ABORTS 1 +#endif + +/* #define ABORTS */ + +#ifdef ABORTS /* the memory system will abort */ +/* For the old test suite Abort between 32 Kbytes and 32 Mbytes + For the new test suite Abort between 8 Mbytes and 26 Mbytes */ +/* #define LOWABORT 32 * 1024 +#define HIGHABORT 32 * 1024 * 1024 */ +#define LOWABORT 8 * 1024 * 1024 +#define HIGHABORT 26 * 1024 * 1024 + +#endif + +#define NUMPAGES 64 * 1024 +#define PAGESIZE 64 * 1024 +#define PAGEBITS 16 +#define OFFSETBITS 0xffff + +int SWI_vector_installed = FALSE; + +/***************************************************************************\ +* Get a Word from Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static ARMword +GetWord (ARMul_State * state, ARMword address, int check) +{ + ARMword page; + ARMword offset; + ARMword **pagetable; + ARMword *pageptr; + + if (check && state->is_XScale) + XScale_check_memacc (state, &address, 0); + + page = address >> PAGEBITS; + offset = (address & OFFSETBITS) >> 2; + pagetable = (ARMword **) state->MemDataPtr; + pageptr = *(pagetable + page); + + if (pageptr == NULL) + { + pageptr = (ARMword *) malloc (PAGESIZE); + + if (pageptr == NULL) + { + perror ("ARMulator can't allocate VM page"); + exit (12); + } + + *(pagetable + page) = pageptr; + } + + return *(pageptr + offset); +} + +/***************************************************************************\ +* Put a Word into Virtual Memory, maybe allocating the page * +\***************************************************************************/ + +static void +PutWord (ARMul_State * state, ARMword address, ARMword data, int check) +{ + ARMword page; + ARMword offset; + ARMword **pagetable; + ARMword *pageptr; + + if (check && state->is_XScale) + XScale_check_memacc (state, &address, 1); + + page = address >> PAGEBITS; + offset = (address & OFFSETBITS) >> 2; + pagetable = (ARMword **) state->MemDataPtr; + pageptr = *(pagetable + page); + + if (pageptr == NULL) + { + pageptr = (ARMword *) malloc (PAGESIZE); + if (pageptr == NULL) + { + perror ("ARMulator can't allocate VM page"); + exit (13); + } + + *(pagetable + page) = pageptr; + } + + if (address == 0x8) + SWI_vector_installed = TRUE; + + *(pageptr + offset) = data; +} + +/***************************************************************************\ +* Initialise the memory interface * +\***************************************************************************/ + +unsigned +ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize) +{ + ARMword **pagetable; + unsigned page; + + if (initmemsize) + state->MemSize = initmemsize; + + pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES); + + if (pagetable == NULL) + return FALSE; + + for (page = 0; page < NUMPAGES; page++) + *(pagetable + page) = NULL; + + state->MemDataPtr = (unsigned char *) pagetable; + + ARMul_ConsolePrint (state, ", 4 Gb memory"); + + return TRUE; +} + +/***************************************************************************\ +* Remove the memory interface * +\***************************************************************************/ + +void +ARMul_MemoryExit (ARMul_State * state) +{ + ARMword page; + ARMword **pagetable; + ARMword *pageptr; + + pagetable = (ARMword **) state->MemDataPtr; + for (page = 0; page < NUMPAGES; page++) + { + pageptr = *(pagetable + page); + if (pageptr != NULL) + free ((char *) pageptr); + } + free ((char *) pagetable); + return; +} + +/***************************************************************************\ +* ReLoad Instruction * +\***************************************************************************/ + +ARMword +ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) + { + ARMul_PREFETCHABORT (address); + return ARMul_ABORTWORD; + } + else + { + ARMul_CLEARABORT; + } +#endif + + if ((isize == 2) && (address & 0x2)) + { + /* We return the next two halfwords: */ + ARMword lo = GetWord (state, address, FALSE); + ARMword hi = GetWord (state, address + 4, FALSE); + + if (state->bigendSig == HIGH) + return (lo << 16) | (hi >> 16); + else + return ((hi & 0xFFFF) << 16) | (lo >> 16); + } + + return GetWord (state, address, TRUE); +} + +/***************************************************************************\ +* Load Instruction, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize) +{ + state->NumScycles++; + +#ifdef HOURGLASS + if ((state->NumScycles & HOURGLASS_RATE) == 0) + { + HOURGLASS; + } +#endif + + return ARMul_ReLoadInstr (state, address, isize); +} + +/***************************************************************************\ +* Load Instruction, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize) +{ + state->NumNcycles++; + + return ARMul_ReLoadInstr (state, address, isize); +} + +/***************************************************************************\ +* Read Word (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadWord (ARMul_State * state, ARMword address) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) + { + ARMul_DATAABORT (address); + return ARMul_ABORTWORD; + } + else + { + ARMul_CLEARABORT; + } +#endif + + return GetWord (state, address, TRUE); +} + +/***************************************************************************\ +* Load Word, Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address) +{ + state->NumScycles++; + + return ARMul_ReadWord (state, address); +} + +/***************************************************************************\ +* Load Word, Non Sequential Cycle * +\***************************************************************************/ + +ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address) +{ + state->NumNcycles++; + + return ARMul_ReadWord (state, address); +} + +/***************************************************************************\ +* Load Halfword, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address) +{ + ARMword temp, offset; + + state->NumNcycles++; + + temp = ARMul_ReadWord (state, address); + offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */ + + return (temp >> offset) & 0xffff; +} + +/***************************************************************************\ +* Read Byte (but don't tell anyone!) * +\***************************************************************************/ + +ARMword ARMul_ReadByte (ARMul_State * state, ARMword address) +{ + ARMword temp, offset; + + temp = ARMul_ReadWord (state, address); + offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */ + + return (temp >> offset & 0xffL); +} + +/***************************************************************************\ +* Load Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +ARMword ARMul_LoadByte (ARMul_State * state, ARMword address) +{ + state->NumNcycles++; + + return ARMul_ReadByte (state, address); +} + +/***************************************************************************\ +* Write Word (but don't tell anyone!) * +\***************************************************************************/ + +void +ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data) +{ +#ifdef ABORTS + if (address >= LOWABORT && address < HIGHABORT) + { + ARMul_DATAABORT (address); + return; + } + else + { + ARMul_CLEARABORT; + } +#endif + + PutWord (state, address, data, TRUE); +} + +/***************************************************************************\ +* Store Word, Sequential Cycle * +\***************************************************************************/ + +void +ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data) +{ + state->NumScycles++; + + ARMul_WriteWord (state, address, data); +} + +/***************************************************************************\ +* Store Word, Non Sequential Cycle * +\***************************************************************************/ + +void +ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data) +{ + state->NumNcycles++; + + ARMul_WriteWord (state, address, data); +} + +/***************************************************************************\ +* Store HalfWord, (Non Sequential Cycle) * +\***************************************************************************/ + +void +ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data) +{ + ARMword temp, offset; + + state->NumNcycles++; + +#ifdef VALIDATE + if (address == TUBE) + { + if (data == 4) + state->Emulate = FALSE; + else + (void) putc ((char) data, stderr); /* Write Char */ + return; + } +#endif + + temp = ARMul_ReadWord (state, address); + offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */ + + PutWord (state, address, + (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset), + TRUE); +} + +/***************************************************************************\ +* Write Byte (but don't tell anyone!) * +\***************************************************************************/ + +void +ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data) +{ + ARMword temp, offset; + + temp = ARMul_ReadWord (state, address); + offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */ + + PutWord (state, address, + (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset), + TRUE); +} + +/***************************************************************************\ +* Store Byte, (Non Sequential Cycle) * +\***************************************************************************/ + +void +ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data) +{ + state->NumNcycles++; + +#ifdef VALIDATE + if (address == TUBE) + { + if (data == 4) + state->Emulate = FALSE; + else + (void) putc ((char) data, stderr); /* Write Char */ + return; + } +#endif + + ARMul_WriteByte (state, address, data); +} + +/***************************************************************************\ +* Swap Word, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data) +{ + ARMword temp; + + state->NumNcycles++; + + temp = ARMul_ReadWord (state, address); + + state->NumNcycles++; + + PutWord (state, address, data, TRUE); + + return temp; +} + +/***************************************************************************\ +* Swap Byte, (Two Non Sequential Cycles) * +\***************************************************************************/ + +ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data) +{ + ARMword temp; + + temp = ARMul_LoadByte (state, address); + ARMul_StoreByte (state, address, data); + + return temp; +} + +/***************************************************************************\ +* Count I Cycles * +\***************************************************************************/ + +void +ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED) +{ + state->NumIcycles += number; + ARMul_CLEARABORT; +} + +/***************************************************************************\ +* Count C Cycles * +\***************************************************************************/ + +void +ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED) +{ + state->NumCcycles += number; + ARMul_CLEARABORT; +} + + +/* Read a byte. Do not check for alignment or access errors. */ + +ARMword +ARMul_SafeReadByte (ARMul_State * state, ARMword address) +{ + ARMword temp, offset; + + temp = GetWord (state, address, FALSE); + offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; + + return (temp >> offset & 0xffL); +} + +void +ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data) +{ + ARMword temp, offset; + + temp = GetWord (state, address, FALSE); + offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; + + PutWord (state, address, + (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset), + FALSE); +} diff --git a/external/gpl3/gdb/dist/sim/arm/bag.c b/external/gpl3/gdb/dist/sim/arm/bag.c new file mode 100644 index 000000000000..1998f3947c06 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/bag.c @@ -0,0 +1,166 @@ +/* bag.c -- ARMulator support code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/********************************************************************/ +/* bag.c: */ +/* Offers a data structure for storing and getting pairs of number. */ +/* The numbers are stored together, put one can be looked up by */ +/* quoting the other. If a new pair is entered and one of the */ +/* numbers is a repeat of a previous pair, then the previos pair */ +/* is deleted. */ +/********************************************************************/ + +#include "bag.h" +#include + +#define HASH_TABLE_SIZE 256 +#define hash(x) (((x)&0xff)^(((x)>>8)&0xff)^(((x)>>16)&0xff)^(((x)>>24)&0xff)) + +typedef struct hashentry +{ + struct hashentry *next; + int first; + int second; +} +Hashentry; + +Hashentry *lookupbyfirst[HASH_TABLE_SIZE]; +Hashentry *lookupbysecond[HASH_TABLE_SIZE]; + +void +addtolist (Hashentry ** add, long first, long second) +{ + while (*add) + add = &((*add)->next); + /* Malloc will never fail? :o( */ + (*add) = (Hashentry *) malloc (sizeof (Hashentry)); + (*add)->next = (Hashentry *) 0; + (*add)->first = first; + (*add)->second = second; +} + +void +killwholelist (Hashentry * p) +{ + Hashentry *q; + + while (p) + { + q = p; + p = p->next; + free (q); + } +} + +static void +removefromlist (Hashentry ** p, long first) +{ + Hashentry *q; + + while (*p) + { + if ((*p)->first == first) + { + q = (*p)->next; + free (*p); + *p = q; + return; + } + p = &((*p)->next); + } +} + +void +BAG_putpair (long first, long second) +{ + long junk; + + if (BAG_getfirst (&junk, second) != NO_SUCH_PAIR) + BAG_killpair_bysecond (second); + addtolist (&lookupbyfirst[hash (first)], first, second); + addtolist (&lookupbysecond[hash (second)], first, second); +} + +Bag_error +BAG_getfirst (long *first, long second) +{ + Hashentry *look; + + look = lookupbysecond[hash (second)]; + while (look) + if (look->second == second) + { + *first = look->first; + return NO_ERROR; + } + return NO_SUCH_PAIR; +} + +Bag_error +BAG_getsecond (long first, long *second) +{ + Hashentry *look; + + look = lookupbyfirst[hash (first)]; + while (look) + { + if (look->first == first) + { + *second = look->second; + return NO_ERROR; + } + look = look->next; + } + return NO_SUCH_PAIR; +} + +Bag_error +BAG_killpair_byfirst (long first) +{ + long second; + + if (BAG_getsecond (first, &second) == NO_SUCH_PAIR) + return NO_SUCH_PAIR; + removefromlist (&lookupbyfirst[hash (first)], first); + removefromlist (&lookupbysecond[hash (second)], first); + return NO_ERROR; +} + +Bag_error +BAG_killpair_bysecond (long second) +{ + long first; + + if (BAG_getfirst (&first, second) == NO_SUCH_PAIR) + return NO_SUCH_PAIR; + removefromlist (&lookupbyfirst[hash (first)], first); + removefromlist (&lookupbysecond[hash (second)], first); + return NO_ERROR; +} + +void +BAG_newbag () +{ + int i; + + for (i = 0; i < 256; i++) + { + killwholelist (lookupbyfirst[i]); + killwholelist (lookupbysecond[i]); + lookupbyfirst[i] = lookupbysecond[i] = (Hashentry *) 0; + } +} diff --git a/external/gpl3/gdb/dist/sim/arm/bag.h b/external/gpl3/gdb/dist/sim/arm/bag.h new file mode 100644 index 000000000000..5592bc838c28 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/bag.h @@ -0,0 +1,43 @@ +/* bag.h -- ARMulator support code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/********************************************************************/ +/* bag.h: */ +/* Header file for bag.c */ +/* Offers a data structure for storing and getting pairs of number. */ +/* The numbers are stored together, put one can be looked up by */ +/* quoting the other. If a new pair is entered and one of the */ +/* numbers is a repeat of a previous pair, then the previos pair */ +/* is deleted. */ +/********************************************************************/ + +typedef enum +{ + NO_ERROR, + DELETED_OLD_PAIR, + NO_SUCH_PAIR, +} +Bag_error; + +void BAG_putpair (long first, long second); + +void BAG_newbag (void); +Bag_error BAG_killpair_byfirst (long first); +Bag_error BAG_killpair_bysecond (long second); + +Bag_error BAG_getfirst (long *first, long second); +Bag_error BAG_getsecond (long first, long *second); diff --git a/external/gpl3/gdb/dist/sim/arm/communicate.c b/external/gpl3/gdb/dist/sim/arm/communicate.c new file mode 100644 index 000000000000..fac2b60244ef --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/communicate.c @@ -0,0 +1,255 @@ +/* communicate.c -- ARMulator RDP comms code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/**************************************************************************/ +/* Functions to read and write characters or groups of characters */ +/* down sockets or pipes. Those that return a value return -1 on failure */ +/* and 0 on success. */ +/**************************************************************************/ + +#include +#include +#include +#include + +#include "armdefs.h" + +/* The socket to the debugger */ +int debugsock; + +/* The maximum number of file descriptors */ +extern int nfds; + +/* The socket handle */ +extern int sockethandle; + +/* Read and Write routines down a pipe or socket */ + +/****************************************************************/ +/* Read an individual character. */ +/* All other read functions rely on this one. */ +/* It waits 15 seconds until there is a character available: if */ +/* no character is available, then it timeouts and returns -1. */ +/****************************************************************/ +int +MYread_char (int sock, unsigned char *c) +{ + int i; + fd_set readfds; + struct timeval timeout = { 15, 0 }; + struct sockaddr_in isa; + +retry: + + FD_ZERO (&readfds); + FD_SET (sock, &readfds); + + i = select (nfds, &readfds, (fd_set *) 0, (fd_set *) 0, &timeout); + + if (i < 0) + { + perror ("select"); + exit (1); + } + + if (!i) + { + fprintf (stderr, "read: Timeout\n"); + return -1; + } + + if ((i = read (sock, c, 1)) < 1) + { + if (!i && sock == debugsock) + { + fprintf (stderr, "Connection with debugger severed.\n"); + /* This shouldn't be necessary for a detached armulator, but + the armulator cannot be cold started a second time, so + this is probably preferable to locking up. */ + return -1; + fprintf (stderr, "Waiting for connection from debugger..."); + debugsock = accept (sockethandle, &isa, &i); + if (debugsock == -1) + { /* Now we are in serious trouble... */ + perror ("accept"); + return -1; + } + fprintf (stderr, " done.\nConnection Established.\n"); + sock = debugsock; + goto retry; + } + perror ("read"); + return -1; + } + +#ifdef DEBUG + if (sock == debugsock) + fprintf (stderr, "<%02x ", *c); +#endif + + return 0; +} + +/****************************************************************/ +/* Read an individual character. */ +/* It waits until there is a character available. Returns -1 if */ +/* an error occurs. */ +/****************************************************************/ +int +MYread_charwait (int sock, unsigned char *c) +{ + int i; + fd_set readfds; + struct sockaddr_in isa; + +retry: + + FD_ZERO (&readfds); + FD_SET (sock, &readfds); + + i = select (nfds, &readfds, + (fd_set *) 0, (fd_set *) 0, (struct timeval *) 0); + + if (i < 0) + { + perror ("select"); + exit (-1); + } + + if ((i = read (sock, c, 1)) < 1) + { + if (!i && sock == debugsock) + { + fprintf (stderr, "Connection with debugger severed.\n"); + return -1; + fprintf (stderr, "Waiting for connection from debugger..."); + debugsock = accept (sockethandle, &isa, &i); + if (debugsock == -1) + { /* Now we are in serious trouble... */ + perror ("accept"); + return -1; + } + fprintf (stderr, " done.\nConnection Established.\n"); + sock = debugsock; + goto retry; + } + perror ("read"); + return -1; + } + +#ifdef DEBUG + if (sock == debugsock) + fprintf (stderr, "<%02x ", *c); +#endif + + return 0; +} + +void +MYwrite_char (int sock, unsigned char c) +{ + + if (write (sock, &c, 1) < 1) + perror ("write"); +#ifdef DEBUG + if (sock == debugsock) + fprintf (stderr, ">%02x ", c); +#endif +} + +int +MYread_word (int sock, ARMword * here) +{ + unsigned char a, b, c, d; + + if (MYread_char (sock, &a) < 0) + return -1; + if (MYread_char (sock, &b) < 0) + return -1; + if (MYread_char (sock, &c) < 0) + return -1; + if (MYread_char (sock, &d) < 0) + return -1; + *here = a | b << 8 | c << 16 | d << 24; + return 0; +} + +void +MYwrite_word (int sock, ARMword i) +{ + MYwrite_char (sock, i & 0xff); + MYwrite_char (sock, (i & 0xff00) >> 8); + MYwrite_char (sock, (i & 0xff0000) >> 16); + MYwrite_char (sock, (i & 0xff000000) >> 24); +} + +void +MYwrite_string (int sock, char *s) +{ + int i; + for (i = 0; MYwrite_char (sock, s[i]), s[i]; i++); +} + +int +MYread_FPword (int sock, char *putinhere) +{ + int i; + for (i = 0; i < 16; i++) + if (MYread_char (sock, &putinhere[i]) < 0) + return -1; + return 0; +} + +void +MYwrite_FPword (int sock, char *fromhere) +{ + int i; + for (i = 0; i < 16; i++) + MYwrite_char (sock, fromhere[i]); +} + +/* Takes n bytes from source and those n bytes */ +/* down to dest */ +int +passon (int source, int dest, int n) +{ + char *p; + int i; + + p = (char *) malloc (n); + if (!p) + { + perror ("Out of memory\n"); + exit (1); + } + if (n) + { + for (i = 0; i < n; i++) + if (MYread_char (source, &p[i]) < 0) + return -1; + +#ifdef DEBUG + if (dest == debugsock) + for (i = 0; i < n; i++) + fprintf (stderr, ")%02x ", (unsigned char) p[i]); +#endif + + write (dest, p, n); + } + free (p); + return 0; +} diff --git a/external/gpl3/gdb/dist/sim/arm/communicate.h b/external/gpl3/gdb/dist/sim/arm/communicate.h new file mode 100644 index 000000000000..b7f32e6a25ca --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/communicate.h @@ -0,0 +1,36 @@ +/* communicate.h -- ARMulator comms support defns: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +int MYread_char (int sock, unsigned char *c); +void MYwrite_char (int sock, unsigned char c); +int MYread_word (int sock, ARMword * here); +void MYwrite_word (int sock, ARMword i); +void MYwrite_string (int sock, char *s); +int MYread_FPword (int sock, char *putinhere); +void MYwrite_FPword (int sock, char *fromhere); +int passon (int source, int dest, int n); + +int wait_for_osreply (ARMword * reply); /* from kid.c */ + +#define OS_SendNothing 0x0 +#define OS_SendChar 0x1 +#define OS_SendWord 0x2 +#define OS_SendString 0x3 + +/* The pipes between the two processes */ +extern int mumkid[2]; +extern int kidmum[2]; diff --git a/external/gpl3/gdb/dist/sim/arm/config.in b/external/gpl3/gdb/dist/sim/arm/config.in new file mode 100644 index 000000000000..f29d045645ee --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/config.in @@ -0,0 +1,104 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ZLIB_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Additional package description */ +#undef PKGVERSION + +/* Bug reporting address */ +#undef REPORT_BUGS_TO + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS diff --git a/external/gpl3/gdb/dist/sim/arm/configure b/external/gpl3/gdb/dist/sim/arm/configure new file mode 100755 index 000000000000..49b069518b6c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/configure @@ -0,0 +1,5883 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. 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We used to do this for the assembler, linker, +# and nm only; for simplicity of configuration, however, we extend this +# criterion to tools (such as ar and ranlib) that are never invoked by +# the compiler, to avoid mismatches. +# +# Also note we have to check MD_EXEC_PREFIX before checking the user's path +# if build == target. This makes the most sense only when bootstrapping, +# but we also do so when build != host. In this case, we hope that the +# build and host systems will have similar contents of MD_EXEC_PREFIX. +# +# If we do not find a suitable binary, then try the user's path. + + +### +# AC_PROG_CPP_WERROR +# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which +# triggers warnings from the preprocessor. Will be in autoconf 2.58. +# For now, using this also overrides header checks to use only the +# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a +# bit harder from here). +# Eventually autoconf will default to checking headers with the compiler +# instead, and we'll have to do this differently. + +# AC_PROG_CPP_WERROR + +# Test for GNAT. +# We require the gnatbind program, and a compiler driver that +# understands Ada. We use the user's CC setting, already found, +# and possibly add $1 to the command-line parameters. +# +# Sets the shell variable have_gnat to yes or no as appropriate, and +# substitutes GNATBIND and GNATMAKE. + + + + + + + + + + + + + + + + + + + + + + + + + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +# This file contains common code used by all simulators. +# +# common.m4 invokes AC macros used by all simulators and by the common +# directory. It is intended to be included before any target specific +# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate +# the Makefile. It is intended to be invoked last. +# +# The simulator's configure.in should look like: +# +# dnl Process this file with autoconf to produce a configure script. +# AC_PREREQ(2.5)dnl +# AC_INIT(Makefile.in) +# AC_CONFIG_HEADER(config.h:config.in) +# +# sinclude(../common/aclocal.m4) +# sinclude(../common/common.m4) +# +# ... target specific stuff ... + +ac_aux_dir= +for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do + for ac_t in install-sh install.sh shtool; do + if test -f "$ac_dir/$ac_t"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/$ac_t -c" + break 2 + fi + done +done +if test -z "$ac_aux_dir"; then + as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5 +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) as_fn_error "invalid value of canonical build" "$LINENO" 5;; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) as_fn_error "invalid value of canonical target" "$LINENO" 5;; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +ALL_LINGUAS= +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../../intl/config.intl; then + . ../../intl/config.intl +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } +if test x"$USE_NLS" != xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define ENABLE_NLS 1" >>confdefs.h + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5 +$as_echo_n "checking for catalogs to be installed... " >&6; } + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5 +$as_echo "$LINGUAS" >&6; } + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in stdlib.h string.h strings.h unistd.h time.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in sys/time.h sys/resource.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in fcntl.h fpu_control.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in dlfcn.h errno.h sys/stat.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_func in getrusage time sigaction __setfpucw +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + +# Check for socket libraries +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5 +$as_echo_n "checking for bind in -lsocket... " >&6; } +if test "${ac_cv_lib_socket_bind+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsocket $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char bind (); +int +main () +{ +return bind (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_socket_bind=yes +else + ac_cv_lib_socket_bind=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5 +$as_echo "$ac_cv_lib_socket_bind" >&6; } +if test "x$ac_cv_lib_socket_bind" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBSOCKET 1 +_ACEOF + + LIBS="-lsocket $LIBS" + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 +$as_echo_n "checking for gethostbyname in -lnsl... " >&6; } +if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lnsl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char gethostbyname (); +int +main () +{ +return gethostbyname (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_nsl_gethostbyname=yes +else + ac_cv_lib_nsl_gethostbyname=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 +$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } +if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBNSL 1 +_ACEOF + + LIBS="-lnsl $LIBS" + +fi + + +# BFD conditionally uses zlib, so we must link it in if libbfd does, by +# using the same condition. + + # See if the user specified whether he wants zlib support or not. + +# Check whether --with-zlib was given. +if test "${with_zlib+set}" = set; then : + withval=$with_zlib; +else + with_zlib=auto +fi + + + if test "$with_zlib" != "no"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5 +$as_echo_n "checking for library containing zlibVersion... " >&6; } +if test "${ac_cv_search_zlibVersion+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char zlibVersion (); +int +main () +{ +return zlibVersion (); + ; + return 0; +} +_ACEOF +for ac_lib in '' z; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_zlibVersion=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_zlibVersion+set}" = set; then : + break +fi +done +if test "${ac_cv_search_zlibVersion+set}" = set; then : + +else + ac_cv_search_zlibVersion=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_zlibVersion" >&5 +$as_echo "$ac_cv_search_zlibVersion" >&6; } +ac_res=$ac_cv_search_zlibVersion +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + for ac_header in zlib.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default" +if test "x$ac_cv_header_zlib_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ZLIB_H 1 +_ACEOF + +fi + +done + +fi + + if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then + as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 + fi + fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then : + enableval=$enable_maintainer_mode; case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) as_fn_error "\"--enable-maintainer-mode does not take a value\"" "$LINENO" 5; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then : + enableval=$enable_sim_bswap; case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) as_fn_error "\"--enable-sim-bswap does not take a value\"" "$LINENO" 5; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then : + enableval=$enable_sim_cflags; case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) as_fn_error "\"Please use --enable-sim-debug instead.\"" "$LINENO" 5; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then : + enableval=$enable_sim_debug; case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then : + enableval=$enable_sim_stdio; case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-stdio\"" "$LINENO" 5; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then : + enableval=$enable_sim_trace; case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then : + enableval=$enable_sim_profile; case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + + +# Check whether --with-pkgversion was given. +if test "${with_pkgversion+set}" = set; then : + withval=$with_pkgversion; case "$withval" in + yes) as_fn_error "package version not specified" "$LINENO" 5 ;; + no) PKGVERSION= ;; + *) PKGVERSION="($withval) " ;; + esac +else + PKGVERSION="(GDB) " + +fi + + + + + +# Check whether --with-bugurl was given. +if test "${with_bugurl+set}" = set; then : + withval=$with_bugurl; case "$withval" in + yes) as_fn_error "bug URL not specified" "$LINENO" 5 ;; + no) BUGURL= + ;; + *) BUGURL="$withval" + ;; + esac +else + BUGURL="http://www.gnu.org/software/gdb/bugs/" + +fi + + case ${BUGURL} in + "") + REPORT_BUGS_TO= + REPORT_BUGS_TEXI= + ;; + *) + REPORT_BUGS_TO="<$BUGURL>" + REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`} + ;; + esac; + + + + +cat >>confdefs.h <<_ACEOF +#define PKGVERSION "$PKGVERSION" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define REPORT_BUGS_TO "$REPORT_BUGS_TO" +_ACEOF + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_type_signal=int +else + ac_cv_type_signal=void +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + +for ac_header in unistd.h stdint.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +COPRO="armcopro.o maverick.o iwmmxt.o" + + + + +ac_sources="$sim_link_files" +ac_dests="$sim_link_links" +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source" +done +ac_config_links="$ac_config_links $ac_config_links_1" + +cgen_breaks="" +if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then +cgen_breaks="break cgen_rtx_error"; +fi + +ac_config_files="$ac_config_files Makefile.sim:Makefile.in" + +ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in" + +ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in" + +ac_config_commands="$ac_config_commands Makefile" + +ac_config_commands="$ac_config_commands stamp-h" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_links="$ac_config_links" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration links: +$config_links + +Configuration commands: +$config_commands + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "$ac_config_links_1") CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;; + "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;; + "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;; + ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;; + "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;; + "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :L $CONFIG_LINKS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. 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Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + :L) + # + # CONFIG_LINK + # + + if test "$ac_source" = "$ac_file" && test "$srcdir" = '.'; then + : + else + # Prefer the file from the source tree if names are identical. + if test "$ac_source" = "$ac_file" || test ! -r "$ac_source"; then + ac_source=$srcdir/$ac_source + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: linking $ac_source to $ac_file" >&5 +$as_echo "$as_me: linking $ac_source to $ac_file" >&6;} + + if test ! -r "$ac_source"; then + as_fn_error "$ac_source: file not found" "$LINENO" 5 + fi + rm -f "$ac_file" + + # Try a relative symlink, then a hard link, then a copy. + case $srcdir in + [\\/$]* | ?:[\\/]* ) ac_rel_source=$ac_source ;; + *) ac_rel_source=$ac_top_build_prefix$ac_source ;; + esac + ln -s "$ac_rel_source" "$ac_file" 2>/dev/null || + ln "$ac_source" "$ac_file" 2>/dev/null || + cp -p "$ac_source" "$ac_file" || + as_fn_error "cannot link or copy $ac_source to $ac_file" "$LINENO" 5 + fi + ;; + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + "stamp-h":C) echo > stamp-h ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + + diff --git a/external/gpl3/gdb/dist/sim/arm/configure.ac b/external/gpl3/gdb/dist/sim/arm/configure.ac new file mode 100644 index 000000000000..8682c25df3ea --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/configure.ac @@ -0,0 +1,18 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(config.h:config.in) + +sinclude(../common/aclocal.m4) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +AC_CHECK_HEADERS(unistd.h stdint.h) + +COPRO="armcopro.o maverick.o iwmmxt.o" + +AC_SUBST(COPRO) + +SIM_AC_OUTPUT diff --git a/external/gpl3/gdb/dist/sim/arm/dbg_conf.h b/external/gpl3/gdb/dist/sim/arm/dbg_conf.h new file mode 100644 index 000000000000..81e37c0ff547 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/dbg_conf.h @@ -0,0 +1,50 @@ +/* dbg_conf.h -- ARMulator debug interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef Dbg_Conf__h + +#define Dbg_Conf__h + +typedef struct Dbg_ConfigBlock +{ + int bytesex; + long memorysize; + int serialport; /*) remote connection parameters */ + int seriallinespeed; /*) (serial connection) */ + int parallelport; /*) ditto */ + int parallellinespeed; /*) (parallel connection) */ + int processor; /* processor the armulator is to emulate (eg ARM60) */ + int rditype; /* armulator / remote processor */ + int drivertype; /* parallel / serial / etc */ + char const *configtoload; + int flags; +} +Dbg_ConfigBlock; + +#define Dbg_ConfigFlag_Reset 1 + +typedef struct Dbg_HostosInterface Dbg_HostosInterface; +/* This structure allows access by the (host-independent) C-library support + module of armulator or pisd (armos.c) to host-dependent functions for + which there is no host-independent interface. Its contents are unknown + to the debugger toolbox. + The assumption is that, in a windowed system, fputc(stderr) for example + may not achieve the desired effect of the character appearing in some + window. + */ + +#endif diff --git a/external/gpl3/gdb/dist/sim/arm/dbg_cp.h b/external/gpl3/gdb/dist/sim/arm/dbg_cp.h new file mode 100644 index 000000000000..68f4f63ecd11 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/dbg_cp.h @@ -0,0 +1,70 @@ +/* dbg_cp.h -- ARMulator debug interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef Dbg_CP__h + +#define Dbg_CP__h + +#define Dbg_Access_Readable 1 +#define Dbg_Access_Writable 2 +#define Dbg_Access_CPDT 4 /* else CPRT */ + +typedef struct +{ + unsigned short rmin, rmax; + /* a single description can be used for a range of registers with + the same properties *accessed via CPDT instructions* + */ + unsigned char nbytes; /* size of register */ + unsigned char access; /* see above (Access_xxx) */ + union + { + struct + { + /* CPDT instructions do not allow the coprocessor much freedom: + only bit 22 ('N') and 12-15 ('CRd') are free for the + coprocessor to use as it sees fit. */ + unsigned char nbit; + unsigned char rdbits; + } + cpdt; + struct + { + /* CPRT instructions have much more latitude. The bits fixed + by the ARM are 24..31 (condition mask & opcode) + 20 (direction) + 8..15 (cpnum, arm register) + 4 (CPRT not CPDO) + leaving 14 bits free to the coprocessor (fortunately + falling within two bytes). */ + unsigned char read_b0, read_b1, write_b0, write_b1; + } + cprt; + } + accessinst; +} +Dbg_CoProRegDesc; + +struct Dbg_CoProDesc +{ + int entries; + Dbg_CoProRegDesc regdesc[1 /* really nentries */ ]; +}; + +#define Dbg_CoProDesc_Size(n) (sizeof(struct Dbg_CoProDesc) + (n-1)*sizeof(Dbg_CoProRegDesc)) + +#endif diff --git a/external/gpl3/gdb/dist/sim/arm/dbg_hif.h b/external/gpl3/gdb/dist/sim/arm/dbg_hif.h new file mode 100644 index 000000000000..90056c3b6874 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/dbg_hif.h @@ -0,0 +1,48 @@ +/* dbg_hif.h -- ARMulator debug interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +typedef void Hif_DbgPrint (void *arg, const char *format, va_list ap); +typedef void Hif_DbgPause (void *arg); + +typedef void Hif_WriteC (void *arg, int c); +typedef int Hif_ReadC (void *arg); +typedef int Hif_Write (void *arg, char const *buffer, int len); +typedef char *Hif_GetS (void *arg, char *buffer, int len); + +typedef void Hif_RDIResetProc (void *arg); + +struct Dbg_HostosInterface +{ + Hif_DbgPrint *dbgprint; + Hif_DbgPause *dbgpause; + void *dbgarg; + + Hif_WriteC *writec; + Hif_ReadC *readc; + Hif_Write *write; + Hif_GetS *gets; + void *hostosarg; + + Hif_RDIResetProc *reset; + void *resetarg; +}; diff --git a/external/gpl3/gdb/dist/sim/arm/dbg_rdi.h b/external/gpl3/gdb/dist/sim/arm/dbg_rdi.h new file mode 100644 index 000000000000..c04a47622ede --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/dbg_rdi.h @@ -0,0 +1,338 @@ +/* dbg_rdi.h -- ARMulator RDI interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef dbg_rdi__h +#define dbg_rdi__h + +/***************************************************************************\ +* Error Codes * +\***************************************************************************/ + +#define RDIError_NoError 0 + +#define RDIError_Reset 1 +#define RDIError_UndefinedInstruction 2 +#define RDIError_SoftwareInterrupt 3 +#define RDIError_PrefetchAbort 4 +#define RDIError_DataAbort 5 +#define RDIError_AddressException 6 +#define RDIError_IRQ 7 +#define RDIError_FIQ 8 +#define RDIError_Error 9 +#define RDIError_BranchThrough0 10 + +#define RDIError_NotInitialised 128 +#define RDIError_UnableToInitialise 129 +#define RDIError_WrongByteSex 130 +#define RDIError_UnableToTerminate 131 +#define RDIError_BadInstruction 132 +#define RDIError_IllegalInstruction 133 +#define RDIError_BadCPUStateSetting 134 +#define RDIError_UnknownCoPro 135 +#define RDIError_UnknownCoProState 136 +#define RDIError_BadCoProState 137 +#define RDIError_BadPointType 138 +#define RDIError_UnimplementedType 139 +#define RDIError_BadPointSize 140 +#define RDIError_UnimplementedSize 141 +#define RDIError_NoMorePoints 142 +#define RDIError_BreakpointReached 143 +#define RDIError_WatchpointAccessed 144 +#define RDIError_NoSuchPoint 145 +#define RDIError_ProgramFinishedInStep 146 +#define RDIError_UserInterrupt 147 +#define RDIError_CantSetPoint 148 +#define RDIError_IncompatibleRDILevels 149 + +#define RDIError_CantLoadConfig 150 +#define RDIError_BadConfigData 151 +#define RDIError_NoSuchConfig 152 +#define RDIError_BufferFull 153 +#define RDIError_OutOfStore 154 +#define RDIError_NotInDownload 155 +#define RDIError_PointInUse 156 +#define RDIError_BadImageFormat 157 +#define RDIError_TargetRunning 158 + +#define RDIError_LittleEndian 240 +#define RDIError_BigEndian 241 +#define RDIError_SoftInitialiseError 242 + +#define RDIError_InsufficientPrivilege 253 +#define RDIError_UnimplementedMessage 254 +#define RDIError_UndefinedMessage 255 + +/***************************************************************************\ +* RDP Message Numbers * +\***************************************************************************/ + +#define RDP_Start (unsigned char)0x0 +#define RDP_End (unsigned char)0x1 +#define RDP_Read (unsigned char)0x2 +#define RDP_Write (unsigned char)0x3 +#define RDP_CPUread (unsigned char)0x4 +#define RDP_CPUwrite (unsigned char)0x5 +#define RDP_CPread (unsigned char)0x6 +#define RDP_CPwrite (unsigned char)0x7 +#define RDP_SetBreak (unsigned char)0xa +#define RDP_ClearBreak (unsigned char)0xb +#define RDP_SetWatch (unsigned char)0xc +#define RDP_ClearWatch (unsigned char)0xd +#define RDP_Execute (unsigned char)0x10 +#define RDP_Step (unsigned char)0x11 +#define RDP_Info (unsigned char)0x12 +#define RDP_OSOpReply (unsigned char)0x13 + +#define RDP_AddConfig (unsigned char)0x14 +#define RDP_LoadConfigData (unsigned char)0x15 +#define RDP_SelectConfig (unsigned char)0x16 +#define RDP_LoadAgent (unsigned char)0x17 + +#define RDP_Stopped (unsigned char)0x20 +#define RDP_OSOp (unsigned char)0x21 +#define RDP_Fatal (unsigned char)0x5e +#define RDP_Return (unsigned char)0x5f +#define RDP_Reset (unsigned char)0x7f + +/***************************************************************************\ +* Other RDI values * +\***************************************************************************/ + +#define RDISex_Little 0 /* the byte sex of the debuggee */ +#define RDISex_Big 1 +#define RDISex_DontCare 2 + +#define RDIPoint_EQ 0 /* the different types of break/watchpoints */ +#define RDIPoint_GT 1 +#define RDIPoint_GE 2 +#define RDIPoint_LT 3 +#define RDIPoint_LE 4 +#define RDIPoint_IN 5 +#define RDIPoint_OUT 6 +#define RDIPoint_MASK 7 + +#define RDIPoint_Inquiry 64 /* ORRed with point type in extended RDP */ +#define RDIPoint_Handle 128 /* messages */ + +#define RDIWatch_ByteRead 1 /* types of data accesses to watch for */ +#define RDIWatch_HalfRead 2 +#define RDIWatch_WordRead 4 +#define RDIWatch_ByteWrite 8 +#define RDIWatch_HalfWrite 16 +#define RDIWatch_WordWrite 32 + +#define RDIReg_R15 (1L << 15) /* mask values for CPU */ +#define RDIReg_PC (1L << 16) +#define RDIReg_CPSR (1L << 17) +#define RDIReg_SPSR (1L << 18) +#define RDINumCPURegs 19 + +#define RDINumCPRegs 10 /* current maximum */ + +#define RDIMode_Curr 255 + +/* Bits set in return value from RDIInfo_Target */ +#define RDITarget_LogSpeed 0x0f +#define RDITarget_HW 0x10 /* else emulator */ +#define RDITarget_AgentMaxLevel 0xe0 +#define RDITarget_AgentLevelShift 5 +#define RDITarget_DebuggerMinLevel 0x700 +#define RDITarget_DebuggerLevelShift 8 +#define RDITarget_CanReloadAgent 0x800 +#define RDITarget_CanInquireLoadSize 0x1000 + +/* Bits set in return value from RDIInfo_Step */ +#define RDIStep_Multiple 1 +#define RDIStep_PCChange 2 +#define RDIStep_Single 4 + +/* Bits set in return value from RDIInfo_Points */ +#define RDIPointCapability_Comparison 1 +#define RDIPointCapability_Range 2 +/* 4 to 128 are RDIWatch_xx{Read,Write} left-shifted by two */ +#define RDIPointCapability_Mask 256 +#define RDIPointCapability_Status 512 /* Point status enquiries available */ + +/* RDI_Info subcodes */ +#define RDIInfo_Target 0 +#define RDIInfo_Points 1 +#define RDIInfo_Step 2 +#define RDIInfo_MMU 3 +#define RDIInfo_DownLoad 4 /* Inquires whether configuration download + and selection is available. + */ +#define RDIInfo_SemiHosting 5 /* Inquires whether RDISemiHosting_* RDI_Info + calls are available. + */ +#define RDIInfo_CoPro 6 /* Inquires whether CoPro RDI_Info calls are + available. + */ +#define RDIInfo_Icebreaker 7 + +/* The next two are only to be used if the value returned by RDIInfo_Points */ +/* has RDIPointCapability_Status set. */ +#define RDIPointStatus_Watch 0x80 +#define RDIPointStatus_Break 0x81 + +#define RDISignal_Stop 0x100 + +#define RDIVector_Catch 0x180 + +/* The next four are only to be used if RDIInfo_Semihosting returned no error */ +#define RDISemiHosting_SetState 0x181 +#define RDISemiHosting_GetState 0x182 +#define RDISemiHosting_SetVector 0x183 +#define RDISemiHosting_GetVector 0x184 + +/* The next two are only to be used if RDIInfo_Icebreaker returned no error */ +#define RDIIcebreaker_GetLocks 0x185 +#define RDIIcebreaker_SetLocks 0x186 + +/* Only if RDIInfo_Target returned RDITarget_CanInquireLoadSize */ +#define RDIInfo_GetLoadSize 0x187 + +#define RDICycles 0x200 +#define RDICycles_Size 48 +#define RDIErrorP 0x201 + +#define RDISet_Cmdline 0x300 +#define RDISet_RDILevel 0x301 +#define RDISet_Thread 0x302 + +/* The next two are only to be used if RDIInfo_CoPro returned no error */ +#define RDIInfo_DescribeCoPro 0x400 +#define RDIInfo_RequestCoProDesc 0x401 + +#define RDIInfo_Log 0x800 +#define RDIInfo_SetLog 0x801 + +typedef unsigned long PointHandle; +typedef unsigned long ThreadHandle; +#define RDINoPointHandle ((PointHandle)-1L) +#define RDINoHandle ((ThreadHandle)-1L) + +struct Dbg_ConfigBlock; +struct Dbg_HostosInterface; +struct Dbg_MCState; +typedef int rdi_open_proc (unsigned type, + struct Dbg_ConfigBlock const *config, + struct Dbg_HostosInterface const *i, + struct Dbg_MCState *dbg_state); +typedef int rdi_close_proc (void); +typedef int rdi_read_proc (ARMword source, void *dest, unsigned *nbytes); +typedef int rdi_write_proc (const void *source, ARMword dest, + unsigned *nbytes); +typedef int rdi_CPUread_proc (unsigned mode, unsigned long mask, + ARMword * state); +typedef int rdi_CPUwrite_proc (unsigned mode, unsigned long mask, + ARMword const *state); +typedef int rdi_CPread_proc (unsigned CPnum, unsigned long mask, + ARMword * state); +typedef int rdi_CPwrite_proc (unsigned CPnum, unsigned long mask, + ARMword const *state); +typedef int rdi_setbreak_proc (ARMword address, unsigned type, ARMword bound, + PointHandle * handle); +typedef int rdi_clearbreak_proc (PointHandle handle); +typedef int rdi_setwatch_proc (ARMword address, unsigned type, + unsigned datatype, ARMword bound, + PointHandle * handle); +typedef int rdi_clearwatch_proc (PointHandle handle); +typedef int rdi_execute_proc (PointHandle * handle); +typedef int rdi_step_proc (unsigned ninstr, PointHandle * handle); +typedef int rdi_info_proc (unsigned type, ARMword * arg1, ARMword * arg2); +typedef int rdi_pointinq_proc (ARMword * address, unsigned type, + unsigned datatype, ARMword * bound); + +typedef enum +{ + RDI_ConfigCPU, + RDI_ConfigSystem +} +RDI_ConfigAspect; + +typedef enum +{ + RDI_MatchAny, + RDI_MatchExactly, + RDI_MatchNoEarlier +} +RDI_ConfigMatchType; + +typedef int rdi_addconfig_proc (unsigned long nbytes); +typedef int rdi_loadconfigdata_proc (unsigned long nbytes, char const *data); +typedef int rdi_selectconfig_proc (RDI_ConfigAspect aspect, char const *name, + RDI_ConfigMatchType matchtype, + unsigned versionreq, unsigned *versionp); + +typedef char *getbufferproc (void *getbarg, unsigned long *sizep); +typedef int rdi_loadagentproc (ARMword dest, unsigned long size, + getbufferproc * getb, void *getbarg); + +typedef struct +{ + int itemmax; + char const *const *names; +} +RDI_NameList; + +typedef RDI_NameList const *rdi_namelistproc (void); + +typedef int rdi_errmessproc (char *buf, int buflen, int errno); + +struct RDIProcVec +{ + char rditypename[12]; + + rdi_open_proc *open; + rdi_close_proc *close; + rdi_read_proc *read; + rdi_write_proc *write; + rdi_CPUread_proc *CPUread; + rdi_CPUwrite_proc *CPUwrite; + rdi_CPread_proc *CPread; + rdi_CPwrite_proc *CPwrite; + rdi_setbreak_proc *setbreak; + rdi_clearbreak_proc *clearbreak; + rdi_setwatch_proc *setwatch; + rdi_clearwatch_proc *clearwatch; + rdi_execute_proc *execute; + rdi_step_proc *step; + rdi_info_proc *info; + /* V2 RDI */ + rdi_pointinq_proc *pointinquiry; + + /* These three useable only if RDIInfo_DownLoad returns no error */ + rdi_addconfig_proc *addconfig; + rdi_loadconfigdata_proc *loadconfigdata; + rdi_selectconfig_proc *selectconfig; + + rdi_namelistproc *drivernames; + rdi_namelistproc *cpunames; + + rdi_errmessproc *errmess; + + /* Only if RDIInfo_Target returns a value with RDITarget_LoadAgent set */ + rdi_loadagentproc *loadagent; +}; + +#endif + +extern unsigned int swi_mask; + +#define SWI_MASK_DEMON (1 << 0) +#define SWI_MASK_ANGEL (1 << 1) +#define SWI_MASK_REDBOOT (1 << 2) diff --git a/external/gpl3/gdb/dist/sim/arm/gdbhost.c b/external/gpl3/gdb/dist/sim/arm/gdbhost.c new file mode 100644 index 000000000000..5058b7cf97c9 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/gdbhost.c @@ -0,0 +1,113 @@ +/* gdbhost.c -- ARMulator RDP to gdb comms code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/***********************************************************/ +/* Functions that communicate info back to the debugger... */ +/***********************************************************/ + +#include +#include +#include "armdefs.h" +#include "communicate.h" +#include "dbg_rdi.h" +#include "armos.h" + +#define OS_SendNothing 0x0 +#define OS_SendChar 0x1 +#define OS_SendWord 0x2 +#define OS_SendString 0x3 + +/* Defined in kid.c */ +extern int wait_for_osreply (ARMword * reply); + +/* A pipe for handling SWI return values that goes straight from the */ +/* parent to the ARMulator host interface, bypassing the childs RDP */ +/* to RDI interpreter */ +int DebuggerARMul[2]; + +/* The pipes between the two processes */ +int mumkid[2]; +int kidmum[2]; + +void +myprint (void *arg, const char *format, va_list ap) +{ +#ifdef DEBUG + fprintf (stderr, "Host: myprint\n"); +#endif + vfprintf (stderr, format, ap); +} + + +/* Waits for a keypress on the debuggers' keyboard */ +void +mypause (void *arg) +{ +#ifdef DEBUG + fprintf (stderr, "Host: mypause\n"); +#endif +} /* I do love exciting functions */ + +void +mywritec (void *arg, int c) +{ +#ifdef DEBUG + fprintf (stderr, "Mywrite : %c\n", c); +#endif + MYwrite_char (kidmum[1], RDP_OSOp); /* OS Operation Request Message */ + MYwrite_word (kidmum[1], SWI_WriteC); /* Print... */ + MYwrite_char (kidmum[1], OS_SendChar); /* ...a single character */ + MYwrite_char (kidmum[1], (unsigned char) c); + + wait_for_osreply ((ARMword *) 0); +} + +int +myreadc (void *arg) +{ + char c; + ARMword x; + +#ifdef DEBUG + fprintf (stderr, "Host: myreadc\n"); +#endif + MYwrite_char (kidmum[1], RDP_OSOp); /* OS Operation Request Message */ + MYwrite_word (kidmum[1], SWI_ReadC); /* Read... */ + MYwrite_char (kidmum[1], OS_SendNothing); + + c = wait_for_osreply (&x); + return (x); +} + + +int +mywrite (void *arg, char const *buffer, int len) +{ +#ifdef DEBUG + fprintf (stderr, "Host: mywrite\n"); +#endif + return 0; +} + +char * +mygets (void *arg, char *buffer, int len) +{ +#ifdef DEBUG + fprintf (stderr, "Host: mygets\n"); +#endif + return buffer; +} diff --git a/external/gpl3/gdb/dist/sim/arm/gdbhost.h b/external/gpl3/gdb/dist/sim/arm/gdbhost.h new file mode 100644 index 000000000000..2ddc17ddc0ee --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/gdbhost.h @@ -0,0 +1,23 @@ +/* gdbhost.h -- ARMulator to gdb interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +void myprint (void *arg, const char *format, va_list ap); +void mypause (void *arg); +void mywritec (void *arg, int c); +int myreadc (void *arg); +int mywrite (void *arg, char const *buffer, int len); +char *mygets (void *arg, char *buffer, int len); diff --git a/external/gpl3/gdb/dist/sim/arm/iwmmxt.c b/external/gpl3/gdb/dist/sim/arm/iwmmxt.c new file mode 100644 index 000000000000..c44fb7f1a5f7 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/iwmmxt.c @@ -0,0 +1,3732 @@ +/* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface. + Copyright (C) 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by matthew green (mrg@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include + +#include "armdefs.h" +#include "armos.h" +#include "armemu.h" +#include "ansidecl.h" +#include "iwmmxt.h" + +/* #define DEBUG 1 */ + +/* Intel(r) Wireless MMX(tm) technology co-processor. + It uses co-processor numbers (0 and 1). There are 16 vector registers wRx + and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC + to access wRx and wCx respectively. */ + +static ARMdword wR[16]; +static ARMword wC[16] = { 0x69051010 }; + +#define SUBSTR(w,t,m,n) ((t)(w << ((sizeof (t) * 8 - 1) - (n))) \ + >> (((sizeof (t) * 8 - 1) - (n)) + (m))) +#define wCBITS(w,x,y) SUBSTR (wC[w], ARMword, x, y) +#define wRBITS(w,x,y) SUBSTR (wR[w], ARMdword, x, y) +#define wCID 0 +#define wCon 1 +#define wCSSF 2 +#define wCASF 3 +#define wCGR0 8 +#define wCGR1 9 +#define wCGR2 10 +#define wCGR3 11 + +/* Bits in the wCon register. */ +#define WCON_CUP (1 << 0) +#define WCON_MUP (1 << 1) + +/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */ +#define SIMD8_SET(x, v, n, b) (x) |= ((v != 0) << ((((b) + 1) * 4) + (n))) +#define SIMD16_SET(x, v, n, h) (x) |= ((v != 0) << ((((h) + 1) * 8) + (n))) +#define SIMD32_SET(x, v, n, w) (x) |= ((v != 0) << ((((w) + 1) * 16) + (n))) +#define SIMD64_SET(x, v, n) (x) |= ((v != 0) << (32 + (n))) + +/* Flags to pass as "n" above. */ +#define SIMD_NBIT -1 +#define SIMD_ZBIT -2 +#define SIMD_CBIT -3 +#define SIMD_VBIT -4 + +/* Various status bit macros. */ +#define NBIT8(x) ((x) & 0x80) +#define NBIT16(x) ((x) & 0x8000) +#define NBIT32(x) ((x) & 0x80000000) +#define NBIT64(x) ((x) & 0x8000000000000000ULL) +#define ZBIT8(x) (((x) & 0xff) == 0) +#define ZBIT16(x) (((x) & 0xffff) == 0) +#define ZBIT32(x) (((x) & 0xffffffff) == 0) +#define ZBIT64(x) (x == 0) + +/* Access byte/half/word "n" of register "x". */ +#define wRBYTE(x,n) wRBITS ((x), (n) * 8, (n) * 8 + 7) +#define wRHALF(x,n) wRBITS ((x), (n) * 16, (n) * 16 + 15) +#define wRWORD(x,n) wRBITS ((x), (n) * 32, (n) * 32 + 31) + +/* Macro to handle how the G bit selects wCGR registers. */ +#define DECODE_G_BIT(state, instr, shift) \ +{ \ + unsigned int reg; \ + \ + reg = BITS (0, 3); \ + \ + if (BIT (8)) /* G */ \ + { \ + if (reg < wCGR0 || reg > wCGR3) \ + { \ + ARMul_UndefInstr (state, instr); \ + return ARMul_DONE; \ + } \ + shift = wC [reg]; \ + } \ + else \ + shift = wR [reg]; \ + \ + shift &= 0xff; \ +} + +/* Index calculations for the satrv[] array. */ +#define BITIDX8(x) (x) +#define BITIDX16(x) (((x) + 1) * 2 - 1) +#define BITIDX32(x) (((x) + 1) * 4 - 1) + +/* Sign extension macros. */ +#define EXTEND8(a) ((a) & 0x80 ? ((a) | 0xffffff00) : (a)) +#define EXTEND16(a) ((a) & 0x8000 ? ((a) | 0xffff0000) : (a)) +#define EXTEND32(a) ((a) & 0x80000000ULL ? ((a) | 0xffffffff00000000ULL) : (a)) + +/* Set the wCSSF from 8 values. */ +#define SET_wCSSF(a,b,c,d,e,f,g,h) \ + wC[wCSSF] = (((h) != 0) << 7) | (((g) != 0) << 6) \ + | (((f) != 0) << 5) | (((e) != 0) << 4) \ + | (((d) != 0) << 3) | (((c) != 0) << 2) \ + | (((b) != 0) << 1) | (((a) != 0) << 0); + +/* Set the wCSSR from an array with 8 values. */ +#define SET_wCSSFvec(v) \ + SET_wCSSF((v)[0],(v)[1],(v)[2],(v)[3],(v)[4],(v)[5],(v)[6],(v)[7]) + +/* Size qualifiers for vector operations. */ +#define Bqual 0 +#define Hqual 1 +#define Wqual 2 +#define Dqual 3 + +/* Saturation qualifiers for vector operations. */ +#define NoSaturation 0 +#define UnsignedSaturation 1 +#define SignedSaturation 3 + + +/* Prototypes. */ +static ARMword Add32 (ARMword, ARMword, int *, int *, ARMword); +static ARMdword AddS32 (ARMdword, ARMdword, int *, int *); +static ARMdword AddU32 (ARMdword, ARMdword, int *, int *); +static ARMword AddS16 (ARMword, ARMword, int *, int *); +static ARMword AddU16 (ARMword, ARMword, int *, int *); +static ARMword AddS8 (ARMword, ARMword, int *, int *); +static ARMword AddU8 (ARMword, ARMword, int *, int *); +static ARMword Sub32 (ARMword, ARMword, int *, int *, ARMword); +static ARMdword SubS32 (ARMdword, ARMdword, int *, int *); +static ARMdword SubU32 (ARMdword, ARMdword, int *, int *); +static ARMword SubS16 (ARMword, ARMword, int *, int *); +static ARMword SubS8 (ARMword, ARMword, int *, int *); +static ARMword SubU16 (ARMword, ARMword, int *, int *); +static ARMword SubU8 (ARMword, ARMword, int *, int *); +static unsigned char IwmmxtSaturateU8 (signed short, int *); +static signed char IwmmxtSaturateS8 (signed short, int *); +static unsigned short IwmmxtSaturateU16 (signed int, int *); +static signed short IwmmxtSaturateS16 (signed int, int *); +static unsigned long IwmmxtSaturateU32 (signed long long, int *); +static signed long IwmmxtSaturateS32 (signed long long, int *); +static ARMword Compute_Iwmmxt_Address (ARMul_State *, ARMword, int *); +static ARMdword Iwmmxt_Load_Double_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Half_Word (ARMul_State *, ARMword); +static ARMword Iwmmxt_Load_Byte (ARMul_State *, ARMword); +static void Iwmmxt_Store_Double_Word (ARMul_State *, ARMword, ARMdword); +static void Iwmmxt_Store_Word (ARMul_State *, ARMword, ARMword); +static void Iwmmxt_Store_Half_Word (ARMul_State *, ARMword, ARMword); +static void Iwmmxt_Store_Byte (ARMul_State *, ARMword, ARMword); +static int Process_Instruction (ARMul_State *, ARMword); + +static int TANDC (ARMul_State *, ARMword); +static int TBCST (ARMul_State *, ARMword); +static int TEXTRC (ARMul_State *, ARMword); +static int TEXTRM (ARMul_State *, ARMword); +static int TINSR (ARMul_State *, ARMword); +static int TMCR (ARMul_State *, ARMword); +static int TMCRR (ARMul_State *, ARMword); +static int TMIA (ARMul_State *, ARMword); +static int TMIAPH (ARMul_State *, ARMword); +static int TMIAxy (ARMul_State *, ARMword); +static int TMOVMSK (ARMul_State *, ARMword); +static int TMRC (ARMul_State *, ARMword); +static int TMRRC (ARMul_State *, ARMword); +static int TORC (ARMul_State *, ARMword); +static int WACC (ARMul_State *, ARMword); +static int WADD (ARMul_State *, ARMword); +static int WALIGNI (ARMword); +static int WALIGNR (ARMul_State *, ARMword); +static int WAND (ARMword); +static int WANDN (ARMword); +static int WAVG2 (ARMword); +static int WCMPEQ (ARMul_State *, ARMword); +static int WCMPGT (ARMul_State *, ARMword); +static int WLDR (ARMul_State *, ARMword); +static int WMAC (ARMword); +static int WMADD (ARMword); +static int WMAX (ARMul_State *, ARMword); +static int WMIN (ARMul_State *, ARMword); +static int WMUL (ARMword); +static int WOR (ARMword); +static int WPACK (ARMul_State *, ARMword); +static int WROR (ARMul_State *, ARMword); +static int WSAD (ARMword); +static int WSHUFH (ARMword); +static int WSLL (ARMul_State *, ARMword); +static int WSRA (ARMul_State *, ARMword); +static int WSRL (ARMul_State *, ARMword); +static int WSTR (ARMul_State *, ARMword); +static int WSUB (ARMul_State *, ARMword); +static int WUNPCKEH (ARMul_State *, ARMword); +static int WUNPCKEL (ARMul_State *, ARMword); +static int WUNPCKIH (ARMul_State *, ARMword); +static int WUNPCKIL (ARMul_State *, ARMword); +static int WXOR (ARMword); + +/* This function does the work of adding two 32bit values + together, and calculating if a carry has occurred. */ + +static ARMword +Add32 (ARMword a1, + ARMword a2, + int * carry_ptr, + int * overflow_ptr, + ARMword sign_mask) +{ + ARMword result = (a1 + a2); + unsigned int uresult = (unsigned int) result; + unsigned int ua1 = (unsigned int) a1; + + /* If (result == a1) and (a2 == 0), + or (result > a2) then we have no carry. */ + * carry_ptr = ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)); + + /* Overflow occurs when both arguments are the + same sign, but the result is a different sign. */ + * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask)) + || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask))); + + return result; +} + +static ARMdword +AddS32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int uresult; + unsigned int ua1; + + a1 = EXTEND32 (a1); + a2 = EXTEND32 (a2); + + result = a1 + a2; + uresult = (unsigned int) result; + ua1 = (unsigned int) a1; + + * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1)); + + * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL)) + || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL))); + + return result; +} + +static ARMdword +AddU32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int uresult; + unsigned int ua1; + + a1 &= 0xffffffff; + a2 &= 0xffffffff; + + result = a1 + a2; + uresult = (unsigned int) result; + ua1 = (unsigned int) a1; + + * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1)); + + * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL)) + || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL))); + + return result; +} + +static ARMword +AddS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND16 (a1); + a2 = EXTEND16 (a2); + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +AddU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xffff; + a2 &= 0xffff; + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +AddS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND8 (a1); + a2 = EXTEND8 (a2); + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +AddU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xff; + a2 &= 0xff; + + return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +Sub32 (ARMword a1, + ARMword a2, + int * borrow_ptr, + int * overflow_ptr, + ARMword sign_mask) +{ + ARMword result = (a1 - a2); + unsigned int ua1 = (unsigned int) a1; + unsigned int ua2 = (unsigned int) a2; + + /* A borrow occurs if a2 is (unsigned) larger than a1. + However the carry flag is *cleared* if a borrow occurs. */ + * borrow_ptr = ! (ua2 > ua1); + + /* Overflow occurs when a negative number is subtracted from a + positive number and the result is negative or a positive + number is subtracted from a negative number and the result is + positive. */ + * overflow_ptr = ( (! (a1 & sign_mask) && (a2 & sign_mask) && (result & sign_mask)) + || ((a1 & sign_mask) && ! (a2 & sign_mask) && ! (result & sign_mask))); + + return result; +} + +static ARMdword +SubS32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int ua1; + unsigned int ua2; + + a1 = EXTEND32 (a1); + a2 = EXTEND32 (a2); + + result = a1 - a2; + ua1 = (unsigned int) a1; + ua2 = (unsigned int) a2; + + * borrow_ptr = ! (ua2 > ua1); + + * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL)) + || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL))); + + return result; +} + +static ARMword +SubS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND16 (a1); + a2 = EXTEND16 (a2); + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +SubS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 = EXTEND8 (a1); + a2 = EXTEND8 (a2); + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMword +SubU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xffff; + a2 &= 0xffff; + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000); +} + +static ARMword +SubU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr) +{ + a1 &= 0xff; + a2 &= 0xff; + + return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80); +} + +static ARMdword +SubU32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr) +{ + ARMdword result; + unsigned int ua1; + unsigned int ua2; + + a1 &= 0xffffffff; + a2 &= 0xffffffff; + + result = a1 - a2; + ua1 = (unsigned int) a1; + ua2 = (unsigned int) a2; + + * borrow_ptr = ! (ua2 > ua1); + + * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL)) + || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL))); + + return result; +} + +/* For the saturation. */ + +static unsigned char +IwmmxtSaturateU8 (signed short val, int * sat) +{ + unsigned char rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xff) + { + rv = 0xff; + *sat = 1; + } + else + { + rv = val & 0xff; + *sat = 0; + } + return rv; +} + +static signed char +IwmmxtSaturateS8 (signed short val, int * sat) +{ + signed char rv; + + if (val < -0x80) + { + rv = -0x80; + *sat = 1; + } + else if (val > 0x7f) + { + rv = 0x7f; + *sat = 1; + } + else + { + rv = val & 0xff; + *sat = 0; + } + return rv; +} + +static unsigned short +IwmmxtSaturateU16 (signed int val, int * sat) +{ + unsigned short rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xffff) + { + rv = 0xffff; + *sat = 1; + } + else + { + rv = val & 0xffff; + *sat = 0; + } + return rv; +} + +static signed short +IwmmxtSaturateS16 (signed int val, int * sat) +{ + signed short rv; + + if (val < -0x8000) + { + rv = - 0x8000; + *sat = 1; + } + else if (val > 0x7fff) + { + rv = 0x7fff; + *sat = 1; + } + else + { + rv = val & 0xffff; + *sat = 0; + } + return rv; +} + +static unsigned long +IwmmxtSaturateU32 (signed long long val, int * sat) +{ + unsigned long rv; + + if (val < 0) + { + rv = 0; + *sat = 1; + } + else if (val > 0xffffffff) + { + rv = 0xffffffff; + *sat = 1; + } + else + { + rv = val & 0xffffffff; + *sat = 0; + } + return rv; +} + +static signed long +IwmmxtSaturateS32 (signed long long val, int * sat) +{ + signed long rv; + + if (val < -0x80000000LL) + { + rv = -0x80000000; + *sat = 1; + } + else if (val > 0x7fffffff) + { + rv = 0x7fffffff; + *sat = 1; + } + else + { + rv = val & 0xffffffff; + *sat = 0; + } + return rv; +} + +/* Intel(r) Wireless MMX(tm) technology Acessor functions. */ + +unsigned +IwmmxtLDC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword data) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtSTC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * data) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtMRC (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtMCR (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + return ARMul_CANT; +} + +unsigned +IwmmxtCDP (ARMul_State * state, unsigned type, ARMword instr) +{ + return ARMul_CANT; +} + +/* Intel(r) Wireless MMX(tm) technology instruction implementations. */ + +static int +TANDC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tandc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + cpsr = ARMul_GetCPSR (state) & 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27) + & wCBITS (wCASF, 20, 23) & wCBITS (wCASF, 16, 19) + & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 8, 11) + & wCBITS (wCASF, 4, 7) & wCBITS (wCASF, 0, 3)) << 28); + break; + + case Hqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23) + & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 4, 7)) << 28); + break; + + case Wqual: + cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +TBCST (ARMul_State * state, ARMword instr) +{ + ARMdword Rn; + int wRd; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tbcst\n"); +#endif + + Rn = state->Reg [BITS (12, 15)]; + if (BITS (12, 15) == 15) + Rn &= 0xfffffffc; + + wRd = BITS (16, 19); + + switch (BITS (6, 7)) + { + case Bqual: + Rn &= 0xff; + wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32) + | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn; + break; + + case Hqual: + Rn &= 0xffff; + wR [wRd] = (Rn << 48) | (Rn << 32) | (Rn << 16) | Rn; + break; + + case Wqual: + Rn &= 0xffffffff; + wR [wRd] = (Rn << 32) | Rn; + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +TEXTRC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr; + ARMword selector; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "textrc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be 0xxx. */ + if (BIT (3) != 0) + return ARMul_CANT; + + selector = BITS (0, 2); + cpsr = ARMul_GetCPSR (state) & 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: selector *= 4; break; + case Hqual: selector = ((selector & 3) * 8) + 4; break; + case Wqual: selector = ((selector & 1) * 16) + 12; break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + cpsr |= wCBITS (wCASF, selector, selector + 3) << 28; + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +TEXTRM (ARMul_State * state, ARMword instr) +{ + ARMword Rd; + int offset; + int wRn; + int sign; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "textrm\n"); +#endif + + wRn = BITS (16, 19); + sign = BIT (3); + offset = BITS (0, 2); + + switch (BITS (22, 23)) + { + case Bqual: + offset *= 8; + Rd = wRBITS (wRn, offset, offset + 7); + if (sign) + Rd = EXTEND8 (Rd); + break; + + case Hqual: + offset = (offset & 3) * 16; + Rd = wRBITS (wRn, offset, offset + 15); + if (sign) + Rd = EXTEND16 (Rd); + break; + + case Wqual: + offset = (offset & 1) * 32; + Rd = wRBITS (wRn, offset, offset + 31); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + if (BITS (12, 15) == 15) + ARMul_UndefInstr (state, instr); + else + state->Reg [BITS (12, 15)] = Rd; + + return ARMul_DONE; +} + +static int +TINSR (ARMul_State * state, ARMword instr) +{ + ARMdword data; + ARMword offset; + int wRd; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tinsr\n"); +#endif + + wRd = BITS (16, 19); + data = state->Reg [BITS (12, 15)]; + offset = BITS (0, 2); + + switch (BITS (6, 7)) + { + case Bqual: + data &= 0xff; + switch (offset) + { + case 0: wR [wRd] = data | (wRBITS (wRd, 8, 63) << 8); break; + case 1: wR [wRd] = wRBITS (wRd, 0, 7) | (data << 8) | (wRBITS (wRd, 16, 63) << 16); break; + case 2: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 24, 63) << 24); break; + case 3: wR [wRd] = wRBITS (wRd, 0, 23) | (data << 24) | (wRBITS (wRd, 32, 63) << 32); break; + case 4: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 40, 63) << 40); break; + case 5: wR [wRd] = wRBITS (wRd, 0, 39) | (data << 40) | (wRBITS (wRd, 48, 63) << 48); break; + case 6: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48) | (wRBITS (wRd, 56, 63) << 56); break; + case 7: wR [wRd] = wRBITS (wRd, 0, 55) | (data << 56); break; + } + break; + + case Hqual: + data &= 0xffff; + + switch (offset & 3) + { + case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break; + case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break; + case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break; + case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break; + } + break; + + case Wqual: + if (offset & 1) + wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32); + else + wR [wRd] = (wRBITS (wRd, 32, 63) << 32) | data; + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +TMCR (ARMul_State * state, ARMword instr) +{ + ARMword val; + int wCreg; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmcr\n"); +#endif + + if (BITS (0, 3) != 0) + return ARMul_CANT; + + val = state->Reg [BITS (12, 15)]; + if (BITS (12, 15) == 15) + val &= 0xfffffffc; + + wCreg = BITS (16, 19); + + switch (wCreg) + { + case wCID: + /* The wCID register is read only. */ + break; + + case wCon: + /* Writing to the MUP or CUP bits clears them. */ + wC [wCon] &= ~ (val & 0x3); + break; + + case wCSSF: + /* Only the bottom 8 bits can be written to. + The higher bits write as zero. */ + wC [wCSSF] = (val & 0xff); + wC [wCon] |= WCON_CUP; + break; + + default: + wC [wCreg] = val; + wC [wCon] |= WCON_CUP; + break; + } + + return ARMul_DONE; +} + +static int +TMCRR (ARMul_State * state, ARMword instr) +{ + ARMdword RdHi = state->Reg [BITS (16, 19)]; + ARMword RdLo = state->Reg [BITS (12, 15)]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmcrr\n"); +#endif + + if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15)) + return ARMul_CANT; + + wR [BITS (0, 3)] = (RdHi << 32) | RdLo; + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIA (ARMul_State * state, ARMword instr) +{ + signed long long a, b; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmia\n"); +#endif + + if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15)) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + a = state->Reg [BITS (0, 3)]; + b = state->Reg [BITS (12, 15)]; + + a = EXTEND32 (a); + b = EXTEND32 (b); + + wR [BITS (5, 8)] += a * b; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIAPH (ARMul_State * state, ARMword instr) +{ + signed long a, b, result; + signed long long r; + ARMword Rm = state->Reg [BITS (0, 3)]; + ARMword Rs = state->Reg [BITS (12, 15)]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmiaph\n"); +#endif + + if (BITS (0, 3) == 15 || BITS (12, 15) == 15) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + a = SUBSTR (Rs, ARMword, 16, 31); + b = SUBSTR (Rm, ARMword, 16, 31); + + a = EXTEND16 (a); + b = EXTEND16 (b); + + result = a * b; + + r = result; + r = EXTEND32 (r); + + wR [BITS (5, 8)] += r; + + a = SUBSTR (Rs, ARMword, 0, 15); + b = SUBSTR (Rm, ARMword, 0, 15); + + a = EXTEND16 (a); + b = EXTEND16 (b); + + result = a * b; + + r = result; + r = EXTEND32 (r); + + wR [BITS (5, 8)] += r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMIAxy (ARMul_State * state, ARMword instr) +{ + ARMword Rm; + ARMword Rs; + long long temp; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmiaxy\n"); +#endif + + if (BITS (0, 3) == 15 || BITS (12, 15) == 15) + { + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + Rm = state->Reg [BITS (0, 3)]; + if (BIT (17)) + Rm >>= 16; + else + Rm &= 0xffff; + + Rs = state->Reg [BITS (12, 15)]; + if (BIT (16)) + Rs >>= 16; + else + Rs &= 0xffff; + + if (Rm & (1 << 15)) + Rm -= 1 << 16; + + if (Rs & (1 << 15)) + Rs -= 1 << 16; + + Rm *= Rs; + temp = Rm; + + if (temp & (1 << 31)) + temp -= 1ULL << 32; + + wR [BITS (5, 8)] += temp; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +TMOVMSK (ARMul_State * state, ARMword instr) +{ + ARMdword result; + int wRn; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmovmsk\n"); +#endif + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + wRn = BITS (16, 19); + + switch (BITS (22, 23)) + { + case Bqual: + result = ( (wRBITS (wRn, 63, 63) << 7) + | (wRBITS (wRn, 55, 55) << 6) + | (wRBITS (wRn, 47, 47) << 5) + | (wRBITS (wRn, 39, 39) << 4) + | (wRBITS (wRn, 31, 31) << 3) + | (wRBITS (wRn, 23, 23) << 2) + | (wRBITS (wRn, 15, 15) << 1) + | (wRBITS (wRn, 7, 7) << 0)); + break; + + case Hqual: + result = ( (wRBITS (wRn, 63, 63) << 3) + | (wRBITS (wRn, 47, 47) << 2) + | (wRBITS (wRn, 31, 31) << 1) + | (wRBITS (wRn, 15, 15) << 0)); + break; + + case Wqual: + result = (wRBITS (wRn, 63, 63) << 1) | wRBITS (wRn, 31, 31); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + state->Reg [BITS (12, 15)] = result; + + return ARMul_DONE; +} + +static int +TMRC (ARMul_State * state, ARMword instr) +{ + int reg = BITS (12, 15); + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmrc\n"); +#endif + + if (BITS (0, 3) != 0) + return ARMul_CANT; + + if (reg == 15) + ARMul_UndefInstr (state, instr); + else + state->Reg [reg] = wC [BITS (16, 19)]; + + return ARMul_DONE; +} + +static int +TMRRC (ARMul_State * state, ARMword instr) +{ + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "tmrrc\n"); +#endif + + if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0)) + ARMul_UndefInstr (state, instr); + else + { + state->Reg [BITS (16, 19)] = wRBITS (BITS (0, 3), 32, 63); + state->Reg [BITS (12, 15)] = wRBITS (BITS (0, 3), 0, 31); + } + + return ARMul_DONE; +} + +static int +TORC (ARMul_State * state, ARMword instr) +{ + ARMword cpsr = ARMul_GetCPSR (state); + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "torc\n"); +#endif + + /* The Rd field must be r15. */ + if (BITS (12, 15) != 15) + return ARMul_CANT; + + /* The CRn field must be r3. */ + if (BITS (16, 19) != 3) + return ARMul_CANT; + + /* The CRm field must be r0. */ + if (BITS (0, 3) != 0) + return ARMul_CANT; + + cpsr &= 0x0fffffff; + + switch (BITS (22, 23)) + { + case Bqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 24, 27) + | wCBITS (wCASF, 20, 23) | wCBITS (wCASF, 16, 19) + | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 8, 11) + | wCBITS (wCASF, 4, 7) | wCBITS (wCASF, 0, 3)) << 28); + break; + + case Hqual: + cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 20, 23) + | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 4, 7)) << 28); + break; + + case Wqual: + cpsr |= ((wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 12, 15)) << 28); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + ARMul_SetCPSR (state, cpsr); + + return ARMul_DONE; +} + +static int +WACC (ARMul_State * state, ARMword instr) +{ + int wRn; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wacc\n"); +#endif + + wRn = BITS (16, 19); + + switch (BITS (22, 23)) + { + case Bqual: + wR [BITS (12, 15)] = + wRBITS (wRn, 56, 63) + wRBITS (wRn, 48, 55) + + wRBITS (wRn, 40, 47) + wRBITS (wRn, 32, 39) + + wRBITS (wRn, 24, 31) + wRBITS (wRn, 16, 23) + + wRBITS (wRn, 8, 15) + wRBITS (wRn, 0, 7); + break; + + case Hqual: + wR [BITS (12, 15)] = + wRBITS (wRn, 48, 63) + wRBITS (wRn, 32, 47) + + wRBITS (wRn, 16, 31) + wRBITS (wRn, 0, 15); + break; + + case Wqual: + wR [BITS (12, 15)] = wRBITS (wRn, 32, 63) + wRBITS (wRn, 0, 31); + break; + + default: + ARMul_UndefInstr (state, instr); + break; + } + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WADD (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword x; + ARMdword s; + ARMword psr = 0; + int i; + int carry; + int overflow; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wadd\n"); +#endif + + /* Add two numbers using the specified function, + leaving setting the carry bit as required. */ +#define ADDx(x, y, m, f) \ + (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \ + wRBITS (BITS ( 0, 3), (x), (y)) & (m), \ + & carry, & overflow) + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8); + satrv [BITIDX8 (i)] = 0; + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddU8); + x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8); + x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Hqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16); + satrv [BITIDX16 (i)] = 0; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddU16); + x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16); + x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Wqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32); + satrv [BITIDX32 (i)] = 0; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddU32); + x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32); + x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_MUP | WCON_CUP); + + SET_wCSSFvec (satrv); + +#undef ADDx + + return ARMul_DONE; +} + +static int +WALIGNI (ARMword instr) +{ + int shift = BITS (20, 22) * 8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "waligni\n"); +#endif + + if (shift) + wR [BITS (12, 15)] = + wRBITS (BITS (16, 19), shift, 63) + | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift))); + else + wR [BITS (12, 15)] = wR [BITS (16, 19)]; + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WALIGNR (ARMul_State * state, ARMword instr) +{ + int shift = (wC [BITS (20, 21) + 8] & 0x7) * 8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "walignr\n"); +#endif + + if (shift) + wR [BITS (12, 15)] = + wRBITS (BITS (16, 19), shift, 63) + | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift))); + else + wR [BITS (12, 15)] = wR [BITS (16, 19)]; + + wC [wCon] |= WCON_MUP; + return ARMul_DONE; +} + +static int +WAND (ARMword instr) +{ + ARMdword result; + ARMword psr = 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wand\n"); +#endif + + result = wR [BITS (16, 19)] & wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WANDN (ARMword instr) +{ + ARMdword result; + ARMword psr = 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wandn\n"); +#endif + + result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WAVG2 (ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + int round = BIT (20) ? 1 : 0; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wavg2\n"); +#endif + +#define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \ + + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \ + + round) / 2) + + if (BIT (22)) + { + for (i = 0; i < 4; i++) + { + s = AVG2x ((i * 16), (i * 16) + 15, 0xffff) & 0xffff; + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + r |= s << (i * 16); + } + } + else + { + for (i = 0; i < 8; i++) + { + s = AVG2x ((i * 8), (i * 8) + 7, 0xff) & 0xff; + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + r |= s << (i * 8); + } + } + + wR [BITS (12, 15)] = r; + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WCMPEQ (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wcmpeq\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + s = wRBYTE (BITS (16, 19), i) == wRBYTE (BITS (0, 3), i) ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + { + s = wRHALF (BITS (16, 19), i) == wRHALF (BITS (0, 3), i) ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + s = wRWORD (BITS (16, 19), i) == wRWORD (BITS (0, 3), i) ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WCMPGT (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wcmpgt\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + if (BIT (21)) + { + /* Use a signed comparison. */ + for (i = 0; i < 8; i++) + { + signed char a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + s = (a > b) ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 8; i++) + { + s = (wRBYTE (BITS (16, 19), i) > wRBYTE (BITS (0, 3), i)) + ? 0xff : 0; + r |= s << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + } + break; + + case Hqual: + if (BIT (21)) + { + for (i = 0; i < 4; i++) + { + signed int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = (a > b) ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 4; i++) + { + s = (wRHALF (BITS (16, 19), i) > wRHALF (BITS (0, 3), i)) + ? 0xffff : 0; + r |= s << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + } + break; + + case Wqual: + if (BIT (21)) + { + for (i = 0; i < 2; i++) + { + signed long a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + s = (a > b) ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + } + else + { + for (i = 0; i < 2; i++) + { + s = (wRWORD (BITS (16, 19), i) > wRWORD (BITS (0, 3), i)) + ? 0xffffffff : 0; + r |= s << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static ARMword +Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed) +{ + ARMword Rn; + ARMword addr; + ARMword offset; + ARMword multiplier; + + * pFailed = 0; + Rn = BITS (16, 19); + addr = state->Reg [Rn]; + offset = BITS (0, 7); + multiplier = BIT (8) ? 4 : 1; + + if (BIT (24)) /* P */ + { + /* Pre Indexed Addressing. */ + if (BIT (23)) + addr += offset * multiplier; + else + addr -= offset * multiplier; + + /* Immediate Pre-Indexed. */ + if (BIT (21)) /* W */ + { + if (Rn == 15) + { + /* Writeback into R15 is UNPREDICTABLE. */ +#ifdef DEBUG + fprintf (stderr, "iWMMXt: writeback into r15\n"); +#endif + * pFailed = 1; + } + else + state->Reg [Rn] = addr; + } + } + else + { + /* Post Indexed Addressing. */ + if (BIT (21)) /* W */ + { + /* Handle the write back of the final address. */ + if (Rn == 15) + { + /* Writeback into R15 is UNPREDICTABLE. */ +#ifdef DEBUG + fprintf (stderr, "iWMMXt: writeback into r15\n"); +#endif + * pFailed = 1; + } + else + { + ARMword increment; + + if (BIT (23)) + increment = offset * multiplier; + else + increment = - (offset * multiplier); + + state->Reg [Rn] = addr + increment; + } + } + else + { + /* P == 0, W == 0, U == 0 is UNPREDICTABLE. */ + if (BIT (23) == 0) + { +#ifdef DEBUG + fprintf (stderr, "iWMMXt: undefined addressing mode\n"); +#endif + * pFailed = 1; + } + } + } + + return addr; +} + +static ARMdword +Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address) +{ + ARMdword value; + + /* The address must be aligned on a 8 byte boundary. */ + if (address & 0x7) + { + fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word load from 0x%x\n", + (state->Reg[15] - 8) & ~0x3, address); +#ifdef DEBUG +#endif + /* No need to check for alignment traps. An unaligned + double word load with alignment trapping disabled is + UNPREDICTABLE. */ + ARMul_Abort (state, ARMul_DataAbortV); + } + + /* Load the words. */ + if (! state->bigendSig) + { + value = ARMul_LoadWordN (state, address + 4); + value <<= 32; + value |= ARMul_LoadWordN (state, address); + } + else + { + value = ARMul_LoadWordN (state, address); + value <<= 32; + value |= ARMul_LoadWordN (state, address + 4); + } + + /* Check for data aborts. */ + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 2, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Word (ARMul_State * state, ARMword address) +{ + ARMword value; + + /* Check for a misaligned address. */ + if (address & 3) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 3; + } + + value = ARMul_LoadWordN (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Half_Word (ARMul_State * state, ARMword address) +{ + ARMword value; + + /* Check for a misaligned address. */ + if (address & 1) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 1; + } + + value = ARMul_LoadHalfWord (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static ARMword +Iwmmxt_Load_Byte (ARMul_State * state, ARMword address) +{ + ARMword value; + + value = ARMul_LoadByte (state, address); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 1, 0L); + + return value; +} + +static void +Iwmmxt_Store_Double_Word (ARMul_State * state, ARMword address, ARMdword value) +{ + /* The address must be aligned on a 8 byte boundary. */ + if (address & 0x7) + { + fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word store to 0x%x\n", + (state->Reg[15] - 8) & ~0x3, address); +#ifdef DEBUG +#endif + /* No need to check for alignment traps. An unaligned + double word store with alignment trapping disabled is + UNPREDICTABLE. */ + ARMul_Abort (state, ARMul_DataAbortV); + } + + /* Store the words. */ + if (! state->bigendSig) + { + ARMul_StoreWordN (state, address, value); + ARMul_StoreWordN (state, address + 4, value >> 32); + } + else + { + ARMul_StoreWordN (state, address + 4, value); + ARMul_StoreWordN (state, address, value >> 32); + } + + /* Check for data aborts. */ + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); + else + ARMul_Icycles (state, 2, 0L); +} + +static void +Iwmmxt_Store_Word (ARMul_State * state, ARMword address, ARMword value) +{ + /* Check for a misaligned address. */ + if (address & 3) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 3; + } + + ARMul_StoreWordN (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static void +Iwmmxt_Store_Half_Word (ARMul_State * state, ARMword address, ARMword value) +{ + /* Check for a misaligned address. */ + if (address & 1) + { + if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN)) + ARMul_Abort (state, ARMul_DataAbortV); + else + address &= ~ 1; + } + + ARMul_StoreHalfWord (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static void +Iwmmxt_Store_Byte (ARMul_State * state, ARMword address, ARMword value) +{ + ARMul_StoreByte (state, address, value); + + if (state->Aborted) + ARMul_Abort (state, ARMul_DataAbortV); +} + +static int +WLDR (ARMul_State * state, ARMword instr) +{ + ARMword address; + int failed; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wldr\n"); +#endif + + address = Compute_Iwmmxt_Address (state, instr, & failed); + if (failed) + return ARMul_CANT; + + if (BITS (28, 31) == 0xf) + { + /* WLDRW wCx */ + wC [BITS (12, 15)] = Iwmmxt_Load_Word (state, address); + } + else if (BIT (8) == 0) + { + if (BIT (22) == 0) + /* WLDRB */ + wR [BITS (12, 15)] = Iwmmxt_Load_Byte (state, address); + else + /* WLDRH */ + wR [BITS (12, 15)] = Iwmmxt_Load_Half_Word (state, address); + } + else + { + if (BIT (22) == 0) + /* WLDRW wRd */ + wR [BITS (12, 15)] = Iwmmxt_Load_Word (state, address); + else + /* WLDRD */ + wR [BITS (12, 15)] = Iwmmxt_Load_Double_Word (state, address); + } + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMAC (ARMword instr) +{ + int i; + ARMdword t = 0; + ARMword a, b; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmac\n"); +#endif + + for (i = 0; i < 4; i++) + { + if (BIT (21)) + { + /* Signed. */ + signed long s; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = (signed long) a * (signed long) b; + + t = t + (ARMdword) s; + } + else + { + /* Unsigned. */ + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + + t += a * b; + } + } + + if (BIT (20)) + wR [BITS (12, 15)] = 0; + + if (BIT (21)) /* Signed. */ + wR[BITS (12, 15)] += t; + else + wR [BITS (12, 15)] += t; + + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMADD (ARMword instr) +{ + ARMdword r = 0; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmadd\n"); +#endif + + for (i = 0; i < 2; i++) + { + ARMdword s1, s2; + + if (BIT (21)) /* Signed. */ + { + signed long a, b; + + a = wRHALF (BITS (16, 19), i * 2); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i * 2); + b = EXTEND16 (b); + + s1 = (ARMdword) (a * b); + + a = wRHALF (BITS (16, 19), i * 2 + 1); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i * 2 + 1); + b = EXTEND16 (b); + + s2 = (ARMdword) (a * b); + } + else /* Unsigned. */ + { + unsigned long a, b; + + a = wRHALF (BITS (16, 19), i * 2); + b = wRHALF (BITS ( 0, 3), i * 2); + + s1 = (ARMdword) (a * b); + + a = wRHALF (BITS (16, 19), i * 2 + 1); + b = wRHALF (BITS ( 0, 3), i * 2 + 1); + + s2 = (ARMdword) a * b; + } + + r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMAX (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmax\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRBYTE (BITS (16, 19), i); + a = EXTEND8 (a); + + b = wRBYTE (BITS (0, 3), i); + b = EXTEND8 (b); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + else + { + unsigned int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a > b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMIN (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmin\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRBYTE (BITS (16, 19), i); + a = EXTEND8 (a); + + b = wRBYTE (BITS (0, 3), i); + b = EXTEND8 (b); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + else /* Unsigned. */ + { + unsigned int a, b; + + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS (0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xff) << (i * 8); + } + break; + + case Hqual: + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + else + { + /* Unsigned. */ + unsigned int a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffff) << (i * 16); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + if (BIT (21)) /* Signed. */ + { + int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS ( 0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + else + { + unsigned int a, b; + + a = wRWORD (BITS (16, 19), i); + b = wRWORD (BITS (0, 3), i); + + if (a < b) + s = a; + else + s = b; + + r |= (s & 0xffffffff) << (i * 32); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WMUL (ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wmul\n"); +#endif + + for (i = 0; i < 4; i++) + if (BIT (21)) /* Signed. */ + { + long a, b; + + a = wRHALF (BITS (16, 19), i); + a = EXTEND16 (a); + + b = wRHALF (BITS (0, 3), i); + b = EXTEND16 (b); + + s = a * b; + + if (BIT (20)) + r |= ((s >> 16) & 0xffff) << (i * 16); + else + r |= (s & 0xffff) << (i * 16); + } + else /* Unsigned. */ + { + unsigned long a, b; + + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS (0, 3), i); + + s = a * b; + + if (BIT (20)) + r |= ((s >> 16) & 0xffff) << (i * 16); + else + r |= (s & 0xffff) << (i * 16); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WOR (ARMword instr) +{ + ARMword psr = 0; + ARMdword result; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wor\n"); +#endif + + result = wR [BITS (16, 19)] | wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WPACK (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword x; + ARMdword s; + int i; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wpack\n"); +#endif + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 8; i++) + { + x = wRHALF (i < 4 ? BITS (16, 19) : BITS (0, 3), i & 3); + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU8 (x, satrv + BITIDX8 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS8 (x, satrv + BITIDX8 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + x = wRWORD (i < 2 ? BITS (16, 19) : BITS (0, 3), i & 1); + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU16 (x, satrv + BITIDX16 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS16 (x, satrv + BITIDX16 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + x = wR [i ? BITS (0, 3) : BITS (16, 19)]; + + switch (BITS (20, 21)) + { + case UnsignedSaturation: + s = IwmmxtSaturateU32 (x, satrv + BITIDX32 (i)); + break; + + case SignedSaturation: + s = IwmmxtSaturateS32 (x, satrv + BITIDX32 (i)); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + SET_wCSSFvec (satrv); + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WROR (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + int shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wror\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + shift &= 0xf; + for (i = 0; i < 4; i++) + { + s = ((wRHALF (BITS (16, 19), i) & 0xffff) << (16 - shift)) + | ((wRHALF (BITS (16, 19), i) & 0xffff) >> shift); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + shift &= 0x1f; + for (i = 0; i < 2; i++) + { + s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << (32 - shift)) + | ((wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift); + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + shift &= 0x3f; + r = (wR [BITS (16, 19)] >> shift) + | (wR [BITS (16, 19)] << (64 - shift)); + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSAD (ARMword instr) +{ + ARMdword r; + int s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsad\n"); +#endif + + /* Z bit. */ + r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff); + + if (BIT (22)) + /* Half. */ + for (i = 0; i < 4; i++) + { + s = (wRHALF (BITS (16, 19), i) - wRHALF (BITS (0, 3), i)); + r += abs (s); + } + else + /* Byte. */ + for (i = 0; i < 8; i++) + { + s = (wRBYTE (BITS (16, 19), i) - wRBYTE (BITS (0, 3), i)); + r += abs (s); + } + + wR [BITS (12, 15)] = r; + wC [wCon] |= WCON_MUP; + + return ARMul_DONE; +} + +static int +WSHUFH (ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + int imm8; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wshufh\n"); +#endif + + imm8 = (BITS (20, 23) << 4) | BITS (0, 3); + + for (i = 0; i < 4; i++) + { + s = wRHALF (BITS (16, 19), ((imm8 >> (i * 2) & 3)) & 0xff); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSLL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsll\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + s = 0; + else + s = ((wRHALF (BITS (16, 19), i) & 0xffff) << shift); + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + s = 0; + else + s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << shift); + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = 0; + else + r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift); + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSRA (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned shift; + signed long t; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsra\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + t = (wRHALF (BITS (16, 19), i) & 0x8000) ? 0xffff : 0; + else + { + t = wRHALF (BITS (16, 19), i); + t = EXTEND16 (t); + t >>= shift; + } + + s = t; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + t = (wRWORD (BITS (16, 19), i) & 0x80000000) ? 0xffffffff : 0; + else + { + t = wRWORD (BITS (16, 19), i); + t >>= shift; + } + s = t; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0; + else + r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift); + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSRL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMdword s; + ARMword psr = 0; + int i; + unsigned int shift; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsrl\n"); +#endif + + DECODE_G_BIT (state, instr, shift); + + switch (BITS (22, 23)) + { + case Hqual: + for (i = 0; i < 4; i++) + { + if (shift > 15) + s = 0; + else + s = ((unsigned) (wRHALF (BITS (16, 19), i) & 0xffff) >> shift); + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + for (i = 0; i < 2; i++) + { + if (shift > 31) + s = 0; + else + s = ((unsigned long) (wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift); + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Dqual: + if (shift > 63) + r = 0; + else + r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WSTR (ARMul_State * state, ARMword instr) +{ + ARMword address; + int failed; + + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wstr\n"); +#endif + + address = Compute_Iwmmxt_Address (state, instr, & failed); + if (failed) + return ARMul_CANT; + + if (BITS (28, 31) == 0xf) + { + /* WSTRW wCx */ + Iwmmxt_Store_Word (state, address, wC [BITS (12, 15)]); + } + else if (BIT (8) == 0) + { + if (BIT (22) == 0) + /* WSTRB */ + Iwmmxt_Store_Byte (state, address, wR [BITS (12, 15)]); + else + /* WSTRH */ + Iwmmxt_Store_Half_Word (state, address, wR [BITS (12, 15)]); + } + else + { + if (BIT (22) == 0) + /* WSTRW wRd */ + Iwmmxt_Store_Word (state, address, wR [BITS (12, 15)]); + else + /* WSTRD */ + Iwmmxt_Store_Double_Word (state, address, wR [BITS (12, 15)]); + } + + return ARMul_DONE; +} + +static int +WSUB (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword x; + ARMdword s; + int i; + int carry; + int overflow; + int satrv[8]; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wsub\n"); +#endif + +/* Subtract two numbers using the specified function, + leaving setting the carry bit as required. */ +#define SUBx(x, y, m, f) \ + (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \ + wRBITS (BITS ( 0, 3), (x), (y)) & (m), & carry, & overflow) + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 8; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8); + satrv [BITIDX8 (i)] = 0; + r |= (s & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubU8); + x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8); + x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i)); + r |= (x & 0xff) << (i * 8); + SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); + SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX8 (i)]) + { + SIMD8_SET (psr, carry, SIMD_CBIT, i); + SIMD8_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Hqual: + satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0; + + for (i = 0; i < 4; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16); + satrv [BITIDX16 (i)] = 0; + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16); + x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x & 0xffff), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubS16); + x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i)); + r |= (x & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX16 (i)]) + { + SIMD16_SET (psr, carry, SIMD_CBIT, i); + SIMD16_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + case Wqual: + satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0; + + for (i = 0; i < 2; i++) + { + switch (BITS (20, 21)) + { + case NoSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32); + satrv[BITIDX32 (i)] = 0; + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + break; + + case UnsignedSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32); + x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + case SignedSaturation: + s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubS32); + x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i)); + r |= (x & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i); + if (! satrv [BITIDX32 (i)]) + { + SIMD32_SET (psr, carry, SIMD_CBIT, i); + SIMD32_SET (psr, overflow, SIMD_VBIT, i); + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + } + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wR [BITS (12, 15)] = r; + wC [wCASF] = psr; + SET_wCSSFvec (satrv); + wC [wCon] |= (WCON_CUP | WCON_MUP); + +#undef SUBx + + return ARMul_DONE; +} + +static int +WUNPCKEH (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckeh\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + s = wRBYTE (BITS (16, 19), i + 4); + + if (BIT (21) && NBIT8 (s)) + s |= 0xff00; + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + s = wRHALF (BITS (16, 19), i + 2); + + if (BIT (21) && NBIT16 (s)) + s |= 0xffff0000; + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + r = wRWORD (BITS (16, 19), 1); + + if (BIT (21) && NBIT32 (r)) + r |= 0xffffffff00000000ULL; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKEL (ARMul_State * state, ARMword instr) +{ + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckel\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + s = wRBYTE (BITS (16, 19), i); + + if (BIT (21) && NBIT8 (s)) + s |= 0xff00; + + r |= (s & 0xffff) << (i * 16); + SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i); + SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + s = wRHALF (BITS (16, 19), i); + + if (BIT (21) && NBIT16 (s)) + s |= 0xffff0000; + + r |= (s & 0xffffffff) << (i * 32); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); + } + break; + + case Wqual: + r = wRWORD (BITS (16, 19), 0); + + if (BIT (21) && NBIT32 (r)) + r |= 0xffffffff00000000ULL; + + SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT); + SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKIH (ARMul_State * state, ARMword instr) +{ + ARMword a, b; + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckih\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + a = wRBYTE (BITS (16, 19), i + 4); + b = wRBYTE (BITS ( 0, 3), i + 4); + s = a | (b << 8); + r |= (s & 0xffff) << (i * 16); + SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2); + SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2); + SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1); + SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + a = wRHALF (BITS (16, 19), i + 2); + b = wRHALF (BITS ( 0, 3), i + 2); + s = a | (b << 16); + r |= (s & 0xffffffff) << (i * 32); + SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2)); + SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2)); + SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1); + SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Wqual: + a = wRWORD (BITS (16, 19), 1); + s = wRWORD (BITS ( 0, 3), 1); + r = a | (s << 32); + + SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0); + SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WUNPCKIL (ARMul_State * state, ARMword instr) +{ + ARMword a, b; + ARMdword r = 0; + ARMword psr = 0; + ARMdword s; + int i; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wunpckil\n"); +#endif + + switch (BITS (22, 23)) + { + case Bqual: + for (i = 0; i < 4; i++) + { + a = wRBYTE (BITS (16, 19), i); + b = wRBYTE (BITS ( 0, 3), i); + s = a | (b << 8); + r |= (s & 0xffff) << (i * 16); + SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2); + SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2); + SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1); + SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Hqual: + for (i = 0; i < 2; i++) + { + a = wRHALF (BITS (16, 19), i); + b = wRHALF (BITS ( 0, 3), i); + s = a | (b << 16); + r |= (s & 0xffffffff) << (i * 32); + SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2)); + SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2)); + SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1); + SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1); + } + break; + + case Wqual: + a = wRWORD (BITS (16, 19), 0); + s = wRWORD (BITS ( 0, 3), 0); + r = a | (s << 32); + + SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0); + SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0); + SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1); + SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1); + break; + + default: + ARMul_UndefInstr (state, instr); + return ARMul_DONE; + } + + wC [wCASF] = psr; + wR [BITS (12, 15)] = r; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +static int +WXOR (ARMword instr) +{ + ARMword psr = 0; + ARMdword result; + + if ((read_cp15_reg (15, 0, 1) & 3) != 3) + return ARMul_CANT; + +#ifdef DEBUG + fprintf (stderr, "wxor\n"); +#endif + + result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)]; + wR [BITS (12, 15)] = result; + + SIMD64_SET (psr, (result == 0), SIMD_ZBIT); + SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); + + wC [wCASF] = psr; + wC [wCon] |= (WCON_CUP | WCON_MUP); + + return ARMul_DONE; +} + +/* This switch table is moved to a seperate function in order + to work around a compiler bug in the host compiler... */ + +static int +Process_Instruction (ARMul_State * state, ARMword instr) +{ + int status = ARMul_BUSY; + + switch ((BITS (20, 23) << 8) | BITS (4, 11)) + { + case 0x000: status = WOR (instr); break; + case 0x011: status = TMCR (state, instr); break; + case 0x100: status = WXOR (instr); break; + case 0x111: status = TMRC (state, instr); break; + case 0x300: status = WANDN (instr); break; + case 0x200: status = WAND (instr); break; + + case 0x810: case 0xa10: + status = WMADD (instr); break; + + case 0x10e: case 0x50e: case 0x90e: case 0xd0e: + status = WUNPCKIL (state, instr); break; + case 0x10c: case 0x50c: case 0x90c: case 0xd0c: + status = WUNPCKIH (state, instr); break; + case 0x012: case 0x112: case 0x412: case 0x512: + status = WSAD (instr); break; + case 0x010: case 0x110: case 0x210: case 0x310: + status = WMUL (instr); break; + case 0x410: case 0x510: case 0x610: case 0x710: + status = WMAC (instr); break; + case 0x006: case 0x406: case 0x806: case 0xc06: + status = WCMPEQ (state, instr); break; + case 0x800: case 0x900: case 0xc00: case 0xd00: + status = WAVG2 (instr); break; + case 0x802: case 0x902: case 0xa02: case 0xb02: + status = WALIGNR (state, instr); break; + case 0x601: case 0x605: case 0x609: case 0x60d: + status = TINSR (state, instr); break; + case 0x107: case 0x507: case 0x907: case 0xd07: + status = TEXTRM (state, instr); break; + case 0x117: case 0x517: case 0x917: case 0xd17: + status = TEXTRC (state, instr); break; + case 0x401: case 0x405: case 0x409: case 0x40d: + status = TBCST (state, instr); break; + case 0x113: case 0x513: case 0x913: case 0xd13: + status = TANDC (state, instr); break; + case 0x01c: case 0x41c: case 0x81c: case 0xc1c: + status = WACC (state, instr); break; + case 0x115: case 0x515: case 0x915: case 0xd15: + status = TORC (state, instr); break; + case 0x103: case 0x503: case 0x903: case 0xd03: + status = TMOVMSK (state, instr); break; + case 0x106: case 0x306: case 0x506: case 0x706: + case 0x906: case 0xb06: case 0xd06: case 0xf06: + status = WCMPGT (state, instr); break; + case 0x00e: case 0x20e: case 0x40e: case 0x60e: + case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: + status = WUNPCKEL (state, instr); break; + case 0x00c: case 0x20c: case 0x40c: case 0x60c: + case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: + status = WUNPCKEH (state, instr); break; + case 0x204: case 0x604: case 0xa04: case 0xe04: + case 0x214: case 0x614: case 0xa14: case 0xe14: + status = WSRL (state, instr); break; + case 0x004: case 0x404: case 0x804: case 0xc04: + case 0x014: case 0x414: case 0x814: case 0xc14: + status = WSRA (state, instr); break; + case 0x104: case 0x504: case 0x904: case 0xd04: + case 0x114: case 0x514: case 0x914: case 0xd14: + status = WSLL (state, instr); break; + case 0x304: case 0x704: case 0xb04: case 0xf04: + case 0x314: case 0x714: case 0xb14: case 0xf14: + status = WROR (state, instr); break; + case 0x116: case 0x316: case 0x516: case 0x716: + case 0x916: case 0xb16: case 0xd16: case 0xf16: + status = WMIN (state, instr); break; + case 0x016: case 0x216: case 0x416: case 0x616: + case 0x816: case 0xa16: case 0xc16: case 0xe16: + status = WMAX (state, instr); break; + case 0x002: case 0x102: case 0x202: case 0x302: + case 0x402: case 0x502: case 0x602: case 0x702: + status = WALIGNI (instr); break; + case 0x01a: case 0x11a: case 0x21a: case 0x31a: + case 0x41a: case 0x51a: case 0x61a: case 0x71a: + case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: + case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: + status = WSUB (state, instr); break; + case 0x01e: case 0x11e: case 0x21e: case 0x31e: + case 0x41e: case 0x51e: case 0x61e: case 0x71e: + case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: + case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: + status = WSHUFH (instr); break; + case 0x018: case 0x118: case 0x218: case 0x318: + case 0x418: case 0x518: case 0x618: case 0x718: + case 0x818: case 0x918: case 0xa18: case 0xb18: + case 0xc18: case 0xd18: case 0xe18: case 0xf18: + status = WADD (state, instr); break; + case 0x008: case 0x108: case 0x208: case 0x308: + case 0x408: case 0x508: case 0x608: case 0x708: + case 0x808: case 0x908: case 0xa08: case 0xb08: + case 0xc08: case 0xd08: case 0xe08: case 0xf08: + status = WPACK (state, instr); break; + case 0x201: case 0x203: case 0x205: case 0x207: + case 0x209: case 0x20b: case 0x20d: case 0x20f: + case 0x211: case 0x213: case 0x215: case 0x217: + case 0x219: case 0x21b: case 0x21d: case 0x21f: + switch (BITS (16, 19)) + { + case 0x0: status = TMIA (state, instr); break; + case 0x8: status = TMIAPH (state, instr); break; + case 0xc: + case 0xd: + case 0xe: + case 0xf: status = TMIAxy (state, instr); break; + default: break; + } + break; + default: + break; + } + return status; +} + +/* Process a possibly Intel(r) Wireless MMX(tm) technology instruction. + Return true if the instruction was handled. */ + +int +ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr) +{ + int status = ARMul_BUSY; + + if (BITS (24, 27) == 0xe) + { + status = Process_Instruction (state, instr); + } + else if (BITS (25, 27) == 0x6) + { + if (BITS (4, 11) == 0x0 && BITS (20, 24) == 0x4) + status = TMCRR (state, instr); + else if (BITS (9, 11) == 0x0) + { + if (BIT (20) == 0x0) + status = WSTR (state, instr); + else if (BITS (20, 24) == 0x5) + status = TMRRC (state, instr); + else + status = WLDR (state, instr); + } + } + + if (status == ARMul_CANT) + { + /* If the instruction was a recognised but illegal, + perform the abort here rather than returning false. + If we return false then ARMul_MRC may be called which + will still abort, but which also perform the register + transfer... */ + ARMul_Abort (state, ARMul_UndefinedInstrV); + status = ARMul_DONE; + } + + return status == ARMul_DONE; +} + +int +Fetch_Iwmmxt_Register (unsigned int regnum, unsigned char * memory) +{ + if (regnum >= 16) + { + memcpy (memory, wC + (regnum - 16), sizeof wC [0]); + return sizeof wC [0]; + } + else + { + memcpy (memory, wR + regnum, sizeof wR [0]); + return sizeof wR [0]; + } +} + +int +Store_Iwmmxt_Register (unsigned int regnum, unsigned char * memory) +{ + if (regnum >= 16) + { + memcpy (wC + (regnum - 16), memory, sizeof wC [0]); + return sizeof wC [0]; + } + else + { + memcpy (wR + regnum, memory, sizeof wR [0]); + return sizeof wR [0]; + } +} diff --git a/external/gpl3/gdb/dist/sim/arm/iwmmxt.h b/external/gpl3/gdb/dist/sim/arm/iwmmxt.h new file mode 100644 index 000000000000..62d4ed232e7c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/iwmmxt.h @@ -0,0 +1,28 @@ +/* iwmmxt.h -- Intel(r) Wireless MMX(tm) technology co-processor interface. + Copyright (C) 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by matthew green (mrg@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +extern unsigned IwmmxtLDC (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned IwmmxtSTC (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned IwmmxtMCR (ARMul_State *, unsigned, ARMword, ARMword); +extern unsigned IwmmxtMRC (ARMul_State *, unsigned, ARMword, ARMword *); +extern unsigned IwmmxtCDP (ARMul_State *, unsigned, ARMword); + +extern int ARMul_HandleIwmmxt (ARMul_State *, ARMword); + +extern int Fetch_Iwmmxt_Register (unsigned int, unsigned char *); +extern int Store_Iwmmxt_Register (unsigned int, unsigned char *); diff --git a/external/gpl3/gdb/dist/sim/arm/kid.c b/external/gpl3/gdb/dist/sim/arm/kid.c new file mode 100644 index 000000000000..d9073e66c704 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/kid.c @@ -0,0 +1,540 @@ +/* kid.c -- ARMulator RDP/RDI interface: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/*****************************************************************/ +/* The child process continues here... */ +/* It waits on a pipe from the parent and translates the RDP */ +/* messages into RDI calls to the ARMulator passing RDP replies */ +/* back up a pipe to the parent. */ +/*****************************************************************/ + +#include +#include + +#include "armdefs.h" +#include "dbg_conf.h" +#include "dbg_hif.h" +#include "dbg_rdi.h" +#include "gdbhost.h" +#include "communicate.h" + +/* The pipes between the two processes */ +extern int mumkid[2]; +extern int kidmum[2]; + +/* The maximum number of file descriptors */ +extern int nfds; + +/* The machine name */ +#define MAXHOSTNAMELENGTH 64 +extern char localhost[MAXHOSTNAMELENGTH + 1]; + +/* The socket number */ +extern unsigned int socketnumber; + +/* RDI interface */ +extern const struct RDIProcVec armul_rdi; + +static int MYrdp_level = 0; + +static int rdi_state = 0; + +/**************************************************************/ +/* Signal handler that terminates excecution in the ARMulator */ +/**************************************************************/ +void +kid_handlesignal (int sig) +{ +#ifdef DEBUG + fprintf (stderr, "Terminate ARMulator excecution\n"); +#endif + if (sig != SIGUSR1) + { + fprintf (stderr, "Unsupported signal.\n"); + return; + } + armul_rdi.info (RDISignal_Stop, (unsigned long *) 0, (unsigned long *) 0); +} + +/********************************************************************/ +/* Waits on a pipe from the socket demon for RDP and */ +/* acts as an RDP to RDI interpreter on the front of the ARMulator. */ +/********************************************************************/ +void +kid () +{ + char *p, *q; + int i, j, k; + long outofthebag; + unsigned char c, d, message; + ARMword x, y, z; + struct sigaction action; + PointHandle point; + Dbg_ConfigBlock config; + Dbg_HostosInterface hostif; + struct Dbg_MCState *MCState; + char command_line[256]; + struct fd_set readfds; + + /* Setup a signal handler for SIGUSR1 */ + action.sa_handler = kid_handlesignal; + action.sa_mask = 0; + action.sa_flags = 0; + + sigaction (SIGUSR1, &action, (struct sigaction *) 0); + + while (1) + { + /* Wait for ever */ + FD_ZERO (&readfds); + FD_SET (mumkid[0], &readfds); + + i = select (nfds, &readfds, + (fd_set *) 0, (fd_set *) 0, (struct timeval *) 0); + + if (i < 0) + { + perror ("select"); + } + + if (read (mumkid[0], &message, 1) < 1) + { + perror ("read"); + } + + switch (message) + { + case RDP_Start: + /* Open and/or Initialise */ + BAG_newbag (); + + MYread_char (mumkid[0], &c); /* type */ + MYread_word (mumkid[0], &x); /* memorysize */ + if (c & 0x2) + MYread_char (mumkid[0], &d); /* speed */ + config.processor = 0; + config.memorysize = x; + config.bytesex = (c & 0x4) ? RDISex_Big : RDISex_Little; + if (c & 0x8) + config.bytesex = RDISex_DontCare; + + hostif.dbgprint = myprint; + hostif.dbgpause = mypause; + hostif.dbgarg = stdout; + hostif.writec = mywritec; + hostif.readc = myreadc; + hostif.write = mywrite; + hostif.gets = mygets; + hostif.reset = mypause; /* do nothing */ + hostif.resetarg = "Do I love resetting or what!\n"; + + if (rdi_state) + { + /* we have restarted, so kill off the existing run. */ + /* armul_rdi.close(); */ + } + i = armul_rdi.open (c & 0x3, &config, &hostif, MCState); + rdi_state = 1; + + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + + x = ~0x4; + armul_rdi.info (RDIVector_Catch, &x, 0); + + break; + + case RDP_End: + /* Close and Finalise */ + i = armul_rdi.close (); + rdi_state = 0; + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_Read: + /* Read Memory Address */ + MYread_word (mumkid[0], &x); /* address */ + MYread_word (mumkid[0], &y); /* nbytes */ + p = (char *) malloc (y); + i = armul_rdi.read (x, p, (unsigned *) &y); + MYwrite_char (kidmum[1], RDP_Return); + for (k = 0; k < y; k++) + MYwrite_char (kidmum[1], p[k]); + free (p); + MYwrite_char (kidmum[1], (unsigned char) i); + if (i) + MYwrite_word (kidmum[1], y); /* number of bytes sent without error */ + break; + + case RDP_Write: + /* Write Memory Address */ + MYread_word (mumkid[0], &x); /* address */ + MYread_word (mumkid[0], &y); /* nbytes */ + p = (char *) malloc (y); + for (k = 0; k < y; k++) + MYread_char (mumkid[0], &p[k]); + i = armul_rdi.write (p, x, (unsigned *) &y); + free (p); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + if (i) + MYwrite_word (kidmum[1], y); /* number of bytes sent without error */ + break; + + case RDP_CPUread: + /* Read CPU State */ + MYread_char (mumkid[0], &c); /* mode */ + MYread_word (mumkid[0], &x); /* mask */ + p = (char *) malloc (4 * RDINumCPURegs); + i = armul_rdi.CPUread (c, x, (ARMword *) p); + MYwrite_char (kidmum[1], RDP_Return); + for (k = 1, j = 0; k != 0x80000000; k *= 2) + if (k & x) + MYwrite_word (kidmum[1], ((ARMword *) p)[j++]); + free (p); + if (i) + MYwrite_char (kidmum[1], (unsigned char) j); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_CPUwrite: + /* Write CPU State */ + MYread_char (mumkid[0], &c); /* mode */ + MYread_word (mumkid[0], &x); /* mask */ + + p = (char *) malloc (4 * RDINumCPURegs); + for (k = 1, j = 0; k != 0x80000000; k *= 2) + if (k & x) + MYread_word (mumkid[0], &(((ARMword *) p)[j++])); + i = armul_rdi.CPUwrite (c, x, (ARMword *) p); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + free (p); + break; + + case RDP_CPread: + /* Read Co-Processor State */ + MYread_char (mumkid[0], &c); /* CPnum */ + MYread_word (mumkid[0], &x); /* mask */ + p = q = (char *) malloc (16 * RDINumCPRegs); + i = armul_rdi.CPread (c, x, (ARMword *) p); + MYwrite_char (kidmum[1], RDP_Return); + for (k = 1, j = 0; k != 0x80000000; k *= 2, j++) + if (k & x) + { + if ((c == 1 || c == 2) && k <= 128) + { + MYwrite_FPword (kidmum[1], q); + q += 16; + } + else + { + MYwrite_word (kidmum[1], *q); + q += 4; + } + } + free (p); + if (i) + MYwrite_char (kidmum[1], (unsigned char) j); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_CPwrite: + /* Write Co-Processor State */ + MYread_char (mumkid[0], &c); /* CPnum */ + MYread_word (mumkid[0], &x); /* mask */ + p = q = (char *) malloc (16 * RDINumCPURegs); + for (k = 1, j = 0; k != 0x80000000; k *= 2, j++) + if (k & x) + { + if ((c == 1 || c == 2) && k <= 128) + { + MYread_FPword (kidmum[1], q); + q += 16; + } + else + { + MYread_word (mumkid[0], (ARMword *) q); + q += 4; + } + } + i = armul_rdi.CPwrite (c, x, (ARMword *) p); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + free (p); + break; + + case RDP_SetBreak: + /* Set Breakpoint */ + MYread_word (mumkid[0], &x); /* address */ + MYread_char (mumkid[0], &c); /* type */ + if ((c & 0xf) >= 5) + MYread_word (mumkid[0], &y); /* bound */ + i = armul_rdi.setbreak (x, c, y, &point); + if (!MYrdp_level) + BAG_putpair ((long) x, (long) point); + MYwrite_char (kidmum[1], RDP_Return); + if (MYrdp_level) + MYwrite_word (kidmum[1], point); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_ClearBreak: + /* Clear Breakpoint */ + MYread_word (mumkid[0], &point); /* PointHandle */ + if (!MYrdp_level) + { + BAG_getsecond ((long) point, &outofthebag); /* swap pointhandle for address */ + BAG_killpair_byfirst (outofthebag); + point = outofthebag; + } + i = armul_rdi.clearbreak (point); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_SetWatch: + /* Set Watchpoint */ + MYread_word (mumkid[0], &x); /* address */ + MYread_char (mumkid[0], &c); /* type */ + MYread_char (mumkid[0], &d); /* datatype */ + if ((c & 0xf) >= 5) + MYread_word (mumkid[0], &y); /* bound */ + i = armul_rdi.setwatch (x, c, d, y, &point); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_word (kidmum[1], point); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_ClearWatch: + /* Clear Watchpoint */ + MYread_word (mumkid[0], &point); /* PointHandle */ + i = armul_rdi.clearwatch (point); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_Execute: + /* Excecute */ + + MYread_char (mumkid[0], &c); /* return */ + +#ifdef DEBUG + fprintf (stderr, "Starting execution\n"); +#endif + i = armul_rdi.execute (&point); +#ifdef DEBUG + fprintf (stderr, "Completed execution\n"); +#endif + MYwrite_char (kidmum[1], RDP_Return); + if (c & 0x80) + MYwrite_word (kidmum[1], point); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_Step: + /* Step */ + MYread_char (mumkid[0], &c); /* return */ + MYread_word (mumkid[0], &x); /* ninstr */ + point = 0x87654321; + i = armul_rdi.step (x, &point); + MYwrite_char (kidmum[1], RDP_Return); + if (c & 0x80) + MYwrite_word (kidmum[1], point); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDP_Info: + /* Info */ + MYread_word (mumkid[0], &x); + switch (x) + { + case RDIInfo_Target: + i = armul_rdi.info (RDIInfo_Target, &y, &z); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_word (kidmum[1], y); /* Loads of info... */ + MYwrite_word (kidmum[1], z); /* Model */ + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDISet_RDILevel: + MYread_word (mumkid[0], &x); /* arg1, debug level */ + i = armul_rdi.info (RDISet_RDILevel, &x, 0); + if (i == RDIError_NoError) + MYrdp_level = x; + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDISet_Cmdline: + for (p = command_line; MYread_char (mumkid[0], p), *p; p++) + ; /* String */ + i = armul_rdi.info (RDISet_Cmdline, + (unsigned long *) command_line, 0); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDIInfo_Step: + i = armul_rdi.info (RDIInfo_Step, &x, 0); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_word (kidmum[1], x); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + case RDIVector_Catch: + MYread_word (mumkid[0], &x); + i = armul_rdi.info (RDIVector_Catch, &x, 0); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], i); + break; + + case RDIInfo_Points: + i = armul_rdi.info (RDIInfo_Points, &x, 0); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_word (kidmum[1], x); + MYwrite_char (kidmum[1], (unsigned char) i); + break; + + default: + fprintf (stderr, "Unsupported info code %d\n", x); + break; + } + break; + + case RDP_OSOpReply: + /* OS Operation Reply */ + MYwrite_char (kidmum[1], RDP_Fatal); + break; + + case RDP_Reset: + /* Reset */ + for (i = 0; i < 50; i++) + MYwrite_char (kidmum[1], RDP_Reset); + p = (char *) malloc (MAXHOSTNAMELENGTH + 5 + 20); + sprintf (p, "Running on %s:%d\n", localhost, socketnumber); + MYwrite_string (kidmum[1], p); + free (p); + + break; + default: + fprintf (stderr, "Oh dear: Something is seriously wrong :-(\n"); + /* Hmm.. bad RDP operation */ + break; + } + } +} + + +/* Handles memory read operations until an OS Operation Reply Message is */ +/* encounterd. It then returns the byte info value (0, 1, or 2) and fills */ +/* in 'putinr0' with the data if appropriate. */ +int +wait_for_osreply (ARMword * reply) +{ + char *p, *q; + int i, j, k; + unsigned char c, d, message; + ARMword x, y, z; + struct sigaction action; + PointHandle point; + Dbg_ConfigBlock config; + Dbg_HostosInterface hostif; + struct Dbg_MCState *MCState; + char command_line[256]; + struct fd_set readfds; + +#ifdef DEBUG + fprintf (stderr, "wait_for_osreply ().\n"); +#endif + + /* Setup a signal handler for SIGUSR1 */ + action.sa_handler = kid_handlesignal; + action.sa_mask = 0; + action.sa_flags = 0; + + sigaction (SIGUSR1, &action, (struct sigaction *) 0); + + while (1) + { + /* Wait for ever */ + FD_ZERO (&readfds); + FD_SET (mumkid[0], &readfds); + + i = select (nfds, &readfds, + (fd_set *) 0, (fd_set *) 0, (struct timeval *) 0); + + if (i < 0) + { + perror ("select"); + } + + if (read (mumkid[0], &message, 1) < 1) + { + perror ("read"); + } + + switch (message) + { + case RDP_Read: + /* Read Memory Address */ + MYread_word (mumkid[0], &x); /* address */ + MYread_word (mumkid[0], &y); /* nbytes */ + p = (char *) malloc (y); + i = armul_rdi.read (x, p, (unsigned *) &y); + MYwrite_char (kidmum[1], RDP_Return); + for (k = 0; k < y; k++) + MYwrite_char (kidmum[1], p[k]); + free (p); + MYwrite_char (kidmum[1], (unsigned char) i); + if (i) + MYwrite_word (kidmum[1], y); /* number of bytes sent without error */ + break; + + case RDP_Write: + /* Write Memory Address */ + MYread_word (mumkid[0], &x); /* address */ + MYread_word (mumkid[0], &y); /* nbytes */ + p = (char *) malloc (y); + for (k = 0; k < y; k++) + MYread_char (mumkid[0], &p[k]); + i = armul_rdi.write (p, x, (unsigned *) &y); + free (p); + MYwrite_char (kidmum[1], RDP_Return); + MYwrite_char (kidmum[1], (unsigned char) i); + if (i) + MYwrite_word (kidmum[1], y); /* number of bytes sent without error */ + break; + + case RDP_OSOpReply: + /* OS Operation Reply */ + MYread_char (mumkid[0], &c); + if (c == 1) + MYread_char (mumkid[0], (char *) reply); + if (c == 2) + MYread_word (mumkid[0], reply); + return c; + break; + + default: + fprintf (stderr, + "HELP! Unaccounted-for message during OS request. \n"); + MYwrite_char (kidmum[1], RDP_Fatal); + } + } +} diff --git a/external/gpl3/gdb/dist/sim/arm/main.c b/external/gpl3/gdb/dist/sim/arm/main.c new file mode 100644 index 000000000000..9bc20fef2358 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/main.c @@ -0,0 +1,194 @@ +/* main.c -- top level of ARMulator: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/**********************************************************************/ +/* Forks the ARMulator and hangs on a socket passing on RDP messages */ +/* down a pipe to the ARMulator which translates them into RDI calls. */ +/**********************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "armdefs.h" +#include "dbg_rdi.h" +#include "dbg_conf.h" + +#define MAXHOSTNAMELENGTH 64 + +/* Read and write routines down sockets and pipes */ + +void MYread_chars (int sock, void *p, int n); +unsigned char MYread_char (int sock); +ARMword MYread_word (int sock); +void MYread_FPword (int sock, char *putinhere); + +void MYwrite_word (int sock, ARMword i); +void MYwrite_string (int sock, char *s); +void MYwrite_FPword (int sock, char *fromhere); +void MYwrite_char (int sock, unsigned char c); + +void passon (int source, int dest, int n); + + +/* Mother and child processes */ +void parent (void); +void kid (void); + +/* The child process id. */ +pid_t child; + +/* The socket to the debugger */ +int debugsock; + +/* The pipes between the two processes */ +int mumkid[2]; +int kidmum[2]; + +/* A pipe for handling SWI return values that goes straight from the */ +/* parent to the ARMulator host interface, bypassing the childs RDP */ +/* to RDI interpreter */ +int DebuggerARMul[2]; + +/* The maximum number of file descriptors */ +int nfds; + +/* The socket handle */ +int sockethandle; + +/* The machine name */ +char localhost[MAXHOSTNAMELENGTH + 1]; + +/* The socket number */ +unsigned int socketnumber; + +/**************************************************************/ +/* Takes one argument: the socket number. */ +/* Opens a socket to the debugger, and once opened spawns the */ +/* ARMulator and sets up a couple of pipes. */ +/**************************************************************/ +int +main (int argc, char *argv[]) +{ + int i; + struct sockaddr_in devil, isa; + struct hostent *hp; + + + if (argc == 1) + { + fprintf (stderr, "No socket number\n"); + return 1; + } + + sscanf (argv[1], "%d", &socketnumber); + if (!socketnumber || socketnumber > 0xffff) + { + fprintf (stderr, "Invalid socket number: %d\n", socketnumber); + return 1; + } + + gethostname (localhost, MAXHOSTNAMELENGTH); + hp = gethostbyname (localhost); + if (!hp) + { + fprintf (stderr, "Cannot get local host info\n"); + return 1; + } + + /* Open a socket */ + sockethandle = socket (hp->h_addrtype, SOCK_STREAM, 0); + if (sockethandle == -1) + { + perror ("socket"); + return 1; + } + + devil.sin_family = hp->h_addrtype; + devil.sin_port = htons (socketnumber); + devil.sin_addr.s_addr = 0; + for (i = 0; i < sizeof (devil.sin_zero); i++) + devil.sin_zero[i] = '\000'; + memcpy (&devil.sin_addr, hp->h_addr_list[0], hp->h_length); + + if (bind (sockethandle, &devil, sizeof (devil)) < 0) + { + perror ("bind"); + return 1; + } + + /* May only accept one debugger at once */ + + if (listen (sockethandle, 0)) + { + perror ("listen"); + return 1; + } + + fprintf (stderr, "Waiting for connection from debugger..."); + + debugsock = accept (sockethandle, &isa, &i); + if (debugsock == -1) + { + perror ("accept"); + return 1; + } + + fprintf (stderr, " done.\nConnection Established.\n"); + + nfds = getdtablesize (); + + if (pipe (mumkid)) + { + perror ("pipe"); + return 1; + } + if (pipe (kidmum)) + { + perror ("pipe"); + return 1; + } + + if (pipe (DebuggerARMul)) + { + perror ("pipe"); + return 1; + } + +#ifdef DEBUG + fprintf (stderr, "Created pipes ok\n"); +#endif + + child = fork (); + +#ifdef DEBUG + fprintf (stderr, "fork() ok\n"); +#endif + + if (child == 0) + kid (); + if (child != -1) + parent (); + + perror ("fork"); + return 1; +} diff --git a/external/gpl3/gdb/dist/sim/arm/maverick.c b/external/gpl3/gdb/dist/sim/arm/maverick.c new file mode 100644 index 000000000000..edead09112e4 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/maverick.c @@ -0,0 +1,1291 @@ +/* maverick.c -- Cirrus/DSP co-processor interface. + Copyright (C) 2003, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Aldy Hernandez (aldyh@redhat.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include "armdefs.h" +#include "ansidecl.h" +#include "armemu.h" + +/*#define CIRRUS_DEBUG 1 /**/ +#if CIRRUS_DEBUG +# define printfdbg printf +#else +# define printfdbg printf_nothing +#endif + +#define POS64(i) ( (~(i)) >> 63 ) +#define NEG64(i) ( (i) >> 63 ) + +/* Define Co-Processor instruction handlers here. */ + +/* Here's ARMulator's DSP definition. A few things to note: + 1) it has 16 64-bit registers and 4 72-bit accumulators + 2) you can only access its registers with MCR and MRC. */ + +/* We can't define these in here because this file might not be linked + unless the target is arm9e-*. They are defined in wrapper.c. + Eventually the simulator should be made to handle any coprocessor + at run time. */ +struct maverick_regs +{ + union + { + int i; + float f; + } upper; + + union + { + int i; + float f; + } lower; +}; + +union maverick_acc_regs +{ + long double ld; /* Acc registers are 72-bits. */ +}; + +struct maverick_regs DSPregs[16]; +union maverick_acc_regs DSPacc[4]; +ARMword DSPsc; + +#define DEST_REG (BITS (12, 15)) +#define SRC1_REG (BITS (16, 19)) +#define SRC2_REG (BITS (0, 3)) + +static int lsw_int_index, msw_int_index; +static int lsw_float_index, msw_float_index; + +static double mv_getRegDouble (int); +static long long mv_getReg64int (int); +static void mv_setRegDouble (int, double val); +static void mv_setReg64int (int, long long val); + +static union +{ + double d; + long long ll; + int ints[2]; +} reg_conv; + +static void +printf_nothing (void * foo, ...) +{ +} + +static void +cirrus_not_implemented (char * insn) +{ + fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn); + fprintf (stderr, "aborting!\n"); + + exit (1); +} + +static unsigned +DSPInit (ARMul_State * state) +{ + ARMul_ConsolePrint (state, ", DSP present"); + return TRUE; +} + +unsigned +DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvrdl */ + /* Move lower half of a DF stored in a DSP reg into an Arm reg. */ + printfdbg ("cfmvrdl\n"); + printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i); + printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); + + *value = (ARMword) DSPregs[SRC1_REG].lower.i; + break; + + case 1: /* cfmvrdh */ + /* Move upper half of a DF stored in a DSP reg into an Arm reg. */ + printfdbg ("cfmvrdh\n"); + printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i); + printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); + + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + break; + + case 2: /* cfmvrs */ + /* Move SF from upper half of a DSP register to an Arm register. */ + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + printfdbg ("cfmvrs = mvf%d <-- %f\n", + SRC1_REG, + DSPregs[SRC1_REG].upper.f); + break; + +#ifdef doesnt_work + case 4: /* cfcmps */ + { + float a, b; + int n, z, c, v; + + a = DSPregs[SRC1_REG].upper.f; + b = DSPregs[SRC2_REG].upper.f; + + printfdbg ("cfcmps\n"); + printfdbg ("\tcomparing %f and %f\n", a, b); + + z = a == b; /* zero */ + n = a != b; /* negative */ + v = a > b; /* overflow */ + c = 0; /* carry */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmpd */ + { + double a, b; + int n, z, c, v; + + a = mv_getRegDouble (SRC1_REG); + b = mv_getRegDouble (SRC2_REG); + + printfdbg ("cfcmpd\n"); + printfdbg ("\tcomparing %g and %g\n", a, b); + + z = a == b; /* zero */ + n = a != b; /* negative */ + v = a > b; /* overflow */ + c = 0; /* carry */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } +#else + case 4: /* cfcmps */ + { + float a, b; + int n, z, c, v; + + a = DSPregs[SRC1_REG].upper.f; + b = DSPregs[SRC2_REG].upper.f; + + printfdbg ("cfcmps\n"); + printfdbg ("\tcomparing %f and %f\n", a, b); + + z = a == b; /* zero */ + n = a < b; /* negative */ + c = a > b; /* carry */ + v = 0; /* fixme */ + printfdbg ("\tz = %d, n = %d\n", z, n); + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmpd */ + { + double a, b; + int n, z, c, v; + + a = mv_getRegDouble (SRC1_REG); + b = mv_getRegDouble (SRC2_REG); + + printfdbg ("cfcmpd\n"); + printfdbg ("\tcomparing %g and %g\n", a, b); + + z = a == b; /* zero */ + n = a < b; /* negative */ + c = a > b; /* carry */ + v = 0; /* fixme */ + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } +#endif + default: + fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvr64l */ + /* Move lower half of 64bit int from Cirrus to Arm. */ + *value = (ARMword) DSPregs[SRC1_REG].lower.i; + printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n", + DEST_REG, + (int) *value); + break; + + case 1: /* cfmvr64h */ + /* Move upper half of 64bit int from Cirrus to Arm. */ + *value = (ARMword) DSPregs[SRC1_REG].upper.i; + printfdbg ("cfmvr64h <-- %d\n", (int) *value); + break; + + case 4: /* cfcmp32 */ + { + int res; + int n, z, c, v; + unsigned int a, b; + + printfdbg ("cfcmp32 mvfx%d - mvfx%d\n", + SRC1_REG, + SRC2_REG); + + /* FIXME: see comment for cfcmps. */ + a = DSPregs[SRC1_REG].lower.i; + b = DSPregs[SRC2_REG].lower.i; + + res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i; + /* zero */ + z = res == 0; + /* negative */ + n = res < 0; + /* overflow */ + v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i, + res); + /* carry */ + c = (NEG (a) && POS (b) || + (NEG (a) && POS (res)) || (POS (b) && POS (res))); + + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + case 5: /* cfcmp64 */ + { + long long res; + int n, z, c, v; + unsigned long long a, b; + + printfdbg ("cfcmp64 mvdx%d - mvdx%d\n", + SRC1_REG, + SRC2_REG); + + /* fixme: see comment for cfcmps. */ + + a = mv_getReg64int (SRC1_REG); + b = mv_getReg64int (SRC2_REG); + + res = mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG); + /* zero */ + z = res == 0; + /* negative */ + n = res < 0; + /* overflow */ + v = ((NEG64 (a) && POS64 (b) && POS64 (res)) + || (POS64 (a) && NEG64 (b) && NEG64 (res))); + /* carry */ + c = (NEG64 (a) && POS64 (b) || + (NEG64 (a) && POS64 (res)) || (POS64 (b) && POS64 (res))); + + *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); + break; + } + + default: + fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword * value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmval32 */ + cirrus_not_implemented ("cfmval32"); + break; + + case 1: /* cfmvam32 */ + cirrus_not_implemented ("cfmvam32"); + break; + + case 2: /* cfmvah32 */ + cirrus_not_implemented ("cfmvah32"); + break; + + case 3: /* cfmva32 */ + cirrus_not_implemented ("cfmva32"); + break; + + case 4: /* cfmva64 */ + cirrus_not_implemented ("cfmva64"); + break; + + case 5: /* cfmvsc32 */ + cirrus_not_implemented ("cfmvsc32"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR4 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmvdlr */ + /* Move the lower half of a DF value from an Arm register into + the lower half of a Cirrus register. */ + printfdbg ("cfmvdlr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].lower.i = (int) value; + break; + + case 1: /* cfmvdhr */ + /* Move the upper half of a DF value from an Arm register into + the upper half of a Cirrus register. */ + printfdbg ("cfmvdhr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + case 2: /* cfmvsr */ + /* Move SF from Arm register into upper half of Cirrus register. */ + printfdbg ("cfmvsr <-- 0x%x\n", (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR5 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + union + { + int s; + unsigned int us; + } val; + + switch (BITS (5, 7)) + { + case 0: /* cfmv64lr */ + /* Move lower half of a 64bit int from an ARM register into the + lower half of a DSP register and sign extend it. */ + printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value); + DSPregs[SRC1_REG].lower.i = (int) value; + break; + + case 1: /* cfmv64hr */ + /* Move upper half of a 64bit int from an ARM register into the + upper half of a DSP register. */ + printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n", + SRC1_REG, + (int) value); + DSPregs[SRC1_REG].upper.i = (int) value; + break; + + case 2: /* cfrshl32 */ + printfdbg ("cfrshl32\n"); + val.us = value; + if (val.s > 0) + DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value; + else + DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value; + break; + + case 3: /* cfrshl64 */ + printfdbg ("cfrshl64\n"); + val.us = value; + if (val.s > 0) + mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) << value); + else + mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPMCR6 (ARMul_State * state, + unsigned type ATTRIBUTE_UNUSED, + ARMword instr, + ARMword value) +{ + switch (BITS (5, 7)) + { + case 0: /* cfmv32al */ + cirrus_not_implemented ("cfmv32al"); + break; + + case 1: /* cfmv32am */ + cirrus_not_implemented ("cfmv32am"); + break; + + case 2: /* cfmv32ah */ + cirrus_not_implemented ("cfmv32ah"); + break; + + case 3: /* cfmv32a */ + cirrus_not_implemented ("cfmv32a"); + break; + + case 4: /* cfmv64a */ + cirrus_not_implemented ("cfmv64a"); + break; + + case 5: /* cfmv32sc */ + cirrus_not_implemented ("cfmv32sc"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { /* it's a long access, get two words */ + /* cfldrd */ + + printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n", + data, words, state->bigendSig, DEST_REG); + + if (words == 0) + { + if (state->bigendSig) + DSPregs[DEST_REG].upper.i = (int) data; + else + DSPregs[DEST_REG].lower.i = (int) data; + } + else + { + if (state->bigendSig) + DSPregs[DEST_REG].lower.i = (int) data; + else + DSPregs[DEST_REG].upper.i = (int) data; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG, + mv_getRegDouble (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + + /* cfldrs */ + printfdbg ("cfldrs\n"); + + DSPregs[DEST_REG].upper.i = (int) data; + + printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG, + DSPregs[DEST_REG].upper.f); + + return ARMul_DONE; + } +} + +unsigned +DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, get two words. */ + + /* cfldr64 */ + printfdbg ("cfldr64: %d\n", data); + + if (words == 0) + { + if (state->bigendSig) + DSPregs[DEST_REG].upper.i = (int) data; + else + DSPregs[DEST_REG].lower.i = (int) data; + } + else + { + if (state->bigendSig) + DSPregs[DEST_REG].lower.i = (int) data; + else + DSPregs[DEST_REG].upper.i = (int) data; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG, + mv_getReg64int (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + + /* cfldr32 */ + printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data); + + /* 32bit ints should be sign extended to 64bits when loaded. */ + mv_setReg64int (DEST_REG, (long long) data); + + return ARMul_DONE; + } +} + +unsigned +DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword * data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, get two words. */ + /* cfstrd */ + printfdbg ("cfstrd\n"); + + if (words == 0) + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].upper.i; + else + *data = (ARMword) DSPregs[DEST_REG].lower.i; + } + else + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].lower.i; + else + *data = (ARMword) DSPregs[DEST_REG].upper.i; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmem = mvd%d = %g\n", DEST_REG, + mv_getRegDouble (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Get just one word. */ + /* cfstrs */ + printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG, + DSPregs[DEST_REG].upper.f); + + *data = (ARMword) DSPregs[DEST_REG].upper.i; + + return ARMul_DONE; + } +} + +unsigned +DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, + unsigned type, + ARMword instr, + ARMword * data) +{ + static unsigned words; + + if (type != ARMul_DATA) + { + words = 0; + return ARMul_DONE; + } + + if (BIT (22)) + { + /* It's a long access, store two words. */ + /* cfstr64 */ + printfdbg ("cfstr64\n"); + + if (words == 0) + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].upper.i; + else + *data = (ARMword) DSPregs[DEST_REG].lower.i; + } + else + { + if (state->bigendSig) + *data = (ARMword) DSPregs[DEST_REG].lower.i; + else + *data = (ARMword) DSPregs[DEST_REG].upper.i; + } + + ++ words; + + if (words == 2) + { + printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG, + mv_getReg64int (DEST_REG)); + + return ARMul_DONE; + } + else + return ARMul_INC; + } + else + { + /* Store just one word. */ + /* cfstr32 */ + *data = (ARMword) DSPregs[DEST_REG].lower.i; + + printfdbg ("cfstr32 MEM = %d\n", (int) *data); + + return ARMul_DONE; + } +} + +unsigned +DSPCDP4 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + + opcode2 = BITS (5,7); + + switch (BITS (20,21)) + { + case 0: + switch (opcode2) + { + case 0: /* cfcpys */ + printfdbg ("cfcpys mvf%d = mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[SRC1_REG].upper.f); + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f; + break; + + case 1: /* cfcpyd */ + printfdbg ("cfcpyd mvd%d = mvd%d = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (SRC1_REG)); + mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)); + break; + + case 2: /* cfcvtds */ + printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n", + DEST_REG, + SRC1_REG, + (float) mv_getRegDouble (SRC1_REG)); + DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG); + break; + + case 3: /* cfcvtsd */ + printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n", + DEST_REG, + SRC1_REG, + (double) DSPregs[SRC1_REG].upper.f); + mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f); + break; + + case 4: /* cfcvt32s */ + printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n", + DEST_REG, + SRC1_REG, + (float) DSPregs[SRC1_REG].lower.i); + DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i; + break; + + case 5: /* cfcvt32d */ + printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n", + DEST_REG, + SRC1_REG, + (double) DSPregs[SRC1_REG].lower.i); + mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i); + break; + + case 6: /* cfcvt64s */ + printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n", + DEST_REG, + SRC1_REG, + (float) mv_getReg64int (SRC1_REG)); + DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG); + break; + + case 7: /* cfcvt64d */ + printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n", + DEST_REG, + SRC1_REG, + (double) mv_getReg64int (SRC1_REG)); + mv_setRegDouble (DEST_REG, (double) mv_getReg64int (SRC1_REG)); + break; + } + break; + + case 1: + switch (opcode2) + { + case 0: /* cfmuls */ + printfdbg ("cfmuls mvf%d = mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f); + + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + * DSPregs[SRC2_REG].upper.f; + break; + + case 1: /* cfmuld */ + printfdbg ("cfmuld mvd%d = mvd%d = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG)); + + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + * mv_getRegDouble (SRC2_REG)); + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + break; + + case 3: + switch (opcode2) + { + case 0: /* cfabss */ + DSPregs[DEST_REG].upper.f = (DSPregs[SRC1_REG].upper.f < 0.0F ? + -DSPregs[SRC1_REG].upper.f + : DSPregs[SRC1_REG].upper.f); + printfdbg ("cfabss mvf%d = |mvf%d| = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 1: /* cfabsd */ + mv_setRegDouble (DEST_REG, + (mv_getRegDouble (SRC1_REG) < 0.0 ? + -mv_getRegDouble (SRC1_REG) + : mv_getRegDouble (SRC1_REG))); + printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n", + DEST_REG, + SRC1_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 2: /* cfnegs */ + DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f; + printfdbg ("cfnegs mvf%d = -mvf%d = %f\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 3: /* cfnegd */ + mv_setRegDouble (DEST_REG, + -mv_getRegDouble (SRC1_REG)); + printfdbg ("cfnegd mvd%d = -mvd%d = %g\n", + DEST_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 4: /* cfadds */ + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + + DSPregs[SRC2_REG].upper.f; + printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 5: /* cfaddd */ + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + + mv_getRegDouble (SRC2_REG)); + printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getRegDouble (DEST_REG)); + break; + + case 6: /* cfsubs */ + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + - DSPregs[SRC2_REG].upper.f; + printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].upper.f); + break; + + case 7: /* cfsubd */ + mv_setRegDouble (DEST_REG, + mv_getRegDouble (SRC1_REG) + - mv_getRegDouble (SRC2_REG)); + printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getRegDouble (DEST_REG)); + break; + } + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPCDP5 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + char shift; + + opcode2 = BITS (5,7); + + /* Shift constants are 7bit signed numbers in bits 0..3|5..7. */ + shift = BITS (0, 3) | (BITS (5, 7)) << 4; + if (shift & 0x40) + shift |= 0xc0; + + switch (BITS (20,21)) + { + case 0: + /* cfsh32 */ + printfdbg ("cfsh32 %s amount=%d\n", shift < 0 ? "right" : "left", + shift); + if (shift < 0) + /* Negative shift is a right shift. */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift; + else + /* Positive shift is a left shift. */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift; + break; + + case 1: + switch (opcode2) + { + case 0: /* cfmul32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 1: /* cfmul64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + * mv_getReg64int (SRC2_REG)); + printfdbg ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 2: /* cfmac32 */ + DSPregs[DEST_REG].lower.i + += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 3: /* cfmsc32 */ + DSPregs[DEST_REG].lower.i + -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; + printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 4: /* cfcvts32 */ + /* fixme: this should round */ + DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; + printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 5: /* cfcvtd32 */ + /* fixme: this should round */ + DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); + printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 6: /* cftruncs32 */ + DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; + printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 7: /* cftruncd32 */ + DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); + printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n", + DEST_REG, + SRC1_REG, + DSPregs[DEST_REG].lower.i); + break; + } + break; + + case 2: + /* cfsh64 */ + printfdbg ("cfsh64\n"); + + if (shift < 0) + /* Negative shift is a right shift. */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) >> -shift); + else + /* Positive shift is a left shift. */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) << shift); + printfdbg ("\t%llx\n", mv_getReg64int(DEST_REG)); + break; + + case 3: + switch (opcode2) + { + case 0: /* cfabs32 */ + DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0 + ? -DSPregs[SRC1_REG].lower.i : DSPregs[SRC1_REG].lower.i); + printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 1: /* cfabs64 */ + mv_setReg64int (DEST_REG, + (mv_getReg64int (SRC1_REG) < 0 + ? -mv_getReg64int (SRC1_REG) + : mv_getReg64int (SRC1_REG))); + printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 2: /* cfneg32 */ + DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i; + printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 3: /* cfneg64 */ + mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG)); + printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 4: /* cfadd32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + + DSPregs[SRC2_REG].lower.i; + printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 5: /* cfadd64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + + mv_getReg64int (SRC2_REG)); + printfdbg ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + + case 6: /* cfsub32 */ + DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + - DSPregs[SRC2_REG].lower.i; + printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + DSPregs[DEST_REG].lower.i); + break; + + case 7: /* cfsub64 */ + mv_setReg64int (DEST_REG, + mv_getReg64int (SRC1_REG) + - mv_getReg64int (SRC2_REG)); + printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n", + DEST_REG, + SRC1_REG, + SRC2_REG, + mv_getReg64int (DEST_REG)); + break; + } + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr); + cirrus_not_implemented ("unknown"); + break; + } + + return ARMul_DONE; +} + +unsigned +DSPCDP6 (ARMul_State * state, + unsigned type, + ARMword instr) +{ + int opcode2; + + opcode2 = BITS (5,7); + + switch (BITS (20,21)) + { + case 0: + /* cfmadd32 */ + cirrus_not_implemented ("cfmadd32"); + break; + + case 1: + /* cfmsub32 */ + cirrus_not_implemented ("cfmsub32"); + break; + + case 2: + /* cfmadda32 */ + cirrus_not_implemented ("cfmadda32"); + break; + + case 3: + /* cfmsuba32 */ + cirrus_not_implemented ("cfmsuba32"); + break; + + default: + fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr); + } + + return ARMul_DONE; +} + +/* Conversion functions. + + 32-bit integers are stored in the LOWER half of a 64-bit physical + register. + + Single precision floats are stored in the UPPER half of a 64-bit + physical register. */ + +static double +mv_getRegDouble (int regnum) +{ + reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i; + reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i; + return reg_conv.d; +} + +static void +mv_setRegDouble (int regnum, double val) +{ + reg_conv.d = val; + DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index]; + DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index]; +} + +static long long +mv_getReg64int (int regnum) +{ + reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i; + reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i; + return reg_conv.ll; +} + +static void +mv_setReg64int (int regnum, long long val) +{ + reg_conv.ll = val; + DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index]; + DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index]; +} + +/* Compute LSW in a double and a long long. */ + +void +mv_compute_host_endianness (ARMul_State * state) +{ + static union + { + long long ll; + long ints[2]; + long i; + double d; + float floats[2]; + float f; + } conv; + + /* Calculate where's the LSW in a 64bit int. */ + conv.ll = 45; + + if (conv.ints[0] == 0) + { + msw_int_index = 0; + lsw_int_index = 1; + } + else + { + assert (conv.ints[1] == 0); + msw_int_index = 1; + lsw_int_index = 0; + } + + /* Calculate where's the LSW in a double. */ + conv.d = 3.0; + + if (conv.ints[0] == 0) + { + msw_float_index = 0; + lsw_float_index = 1; + } + else + { + assert (conv.ints[1] == 0); + msw_float_index = 1; + lsw_float_index = 0; + } + + printfdbg ("lsw_int_index %d\n", lsw_int_index); + printfdbg ("lsw_float_index %d\n", lsw_float_index); +} diff --git a/external/gpl3/gdb/dist/sim/arm/parent.c b/external/gpl3/gdb/dist/sim/arm/parent.c new file mode 100644 index 000000000000..159e8e35b62e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/parent.c @@ -0,0 +1,481 @@ +/* parent.c -- ARMulator RDP comms code: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/*****************************************************************/ +/* The Parent process continues here... */ +/* It waits on the socket and passes on RDP messages down a pipe */ +/* to the ARMulator RDP to RDI interpreter. */ +/*****************************************************************/ + +#include +#include +#include +#include "time.h" +#include "armdefs.h" +#include "dbg_rdi.h" +#include "communicate.h" + +/* The socket to the debugger */ +extern int debugsock; + +/* The pipes between the two processes */ +extern int mumkid[2]; +extern int kidmum[2]; + +/* A pipe for handling SWI return values that goes straight from the */ +/* parent to the ARMulator host interface, bypassing the child's RDP */ +/* to RDI interpreter */ +extern int DebuggerARMul[2]; + +/* The maximum number of file descriptors */ +extern int nfds; + +/* The child process id. */ +extern pid_t child; + +void +parent () +{ + int i, j, k; + unsigned char message, CPnum, exreturn; + ARMword mask, nbytes, messagetype; + unsigned char c, d; + ARMword x, y; + int virgin = 1; + struct fd_set readfds; + +#ifdef DEBUG + fprintf (stderr, "parent ()...\n"); +#endif + +panic_error: + + if (!virgin) + { +#ifdef DEBUG + fprintf (stderr, "Arghh! What is going on?\n"); +#endif + kill (child, SIGHUP); + MYwrite_char (debugsock, RDP_Reset); + } + + virgin = 0; + + while (1) + { + + /* Wait either for the ARMulator or the debugger */ + + FD_ZERO (&readfds); + FD_SET (kidmum[0], &readfds); /* Wait for messages from ARMulator */ + FD_SET (debugsock, &readfds); /* Wait for messages from debugger */ + +#ifdef DEBUG + fprintf (stderr, "Waiting for ARMulator or debugger... "); +#endif + + while ((i = select (nfds, &readfds, (fd_set *) 0, (fd_set *) 0, 0)) < 0) + { + perror ("select"); + } + +#ifdef DEBUG + fprintf (stderr, "(%d/2)", i); +#endif + + if (FD_ISSET (debugsock, &readfds)) + { +#ifdef DEBUG + fprintf (stderr, "->debugger\n"); +#endif + + /* Inside this rather large if statement with simply pass on a complete + message to the ARMulator. The reason we need to pass messages on one + at a time is that we have to know whether the message is an OSOpReply + or an info(stop), so that we can take different action in those + cases. */ + + if (MYread_char (debugsock, &message)) + goto panic_error; + + switch (message) + { + case RDP_Start: + /* Open and/or Initialise */ +#ifdef DEBUG + fprintf (stderr, "RDP Open\n"); +#endif + if (MYread_char (debugsock, &c)) /* type */ + goto panic_error; + + if (MYread_word (debugsock, &x)) /* memory size */ + goto panic_error; + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + MYwrite_word (mumkid[1], x); + if (c & 0x2) + { + passon (debugsock, mumkid[1], 1); /* speed */ + } + break; + + case RDP_End: + /* Close and Finalise */ +#ifdef DEBUG + fprintf (stderr, "RDP Close\n"); +#endif + MYwrite_char (mumkid[1], message); + break; + + case RDP_Read: + /* Read Memory Address */ +#ifdef DEBUG + fprintf (stderr, "RDP Read Memory\n"); +#endif + MYwrite_char (mumkid[1], message); + if (passon (debugsock, mumkid[1], 4)) + goto panic_error; /* address */ + if (MYread_word (debugsock, &nbytes)) + goto panic_error; /* nbytes */ + MYwrite_word (mumkid[1], nbytes); + break; + + case RDP_Write: + /* Write Memory Address */ +#ifdef DEBUG + fprintf (stderr, "RDP Write Memory\n"); +#endif + if (MYread_word (debugsock, &x)) + goto panic_error; /* address */ + + if (MYread_word (debugsock, &y)) + goto panic_error; /* nbytes */ + + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], x); + MYwrite_word (mumkid[1], y); + passon (debugsock, mumkid[1], y); /* actual data */ + break; + + case RDP_CPUread: + /* Read CPU State */ +#ifdef DEBUG + fprintf (stderr, "RDP Read CPU\n"); +#endif + if (MYread_char (debugsock, &c)) + goto panic_error; /* mode */ + + if (MYread_word (debugsock, &mask)) + goto panic_error; /* mask */ + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + MYwrite_word (mumkid[1], mask); + break; + + case RDP_CPUwrite: + /* Write CPU State */ +#ifdef DEBUG + fprintf (stderr, "RDP Write CPU\n"); +#endif + if (MYread_char (debugsock, &c)) + goto panic_error; /* mode */ + + if (MYread_word (debugsock, &x)) + goto panic_error; /* mask */ + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + MYwrite_word (mumkid[1], x); + for (k = 1, j = 0; k != 0x80000000; k *= 2, j++) + if ((k & x) && passon (debugsock, mumkid[1], 4)) + goto panic_error; + break; + + case RDP_CPread: + /* Read Co-Processor State */ +#ifdef DEBUG + fprintf (stderr, "RDP Read CP state\n"); +#endif + if (MYread_char (debugsock, &CPnum)) + goto panic_error; + + if (MYread_word (debugsock, &mask)) + goto panic_error; + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], CPnum); + MYwrite_word (mumkid[1], mask); + break; + + case RDP_CPwrite: + /* Write Co-Processor State */ +#ifdef DEBUG + fprintf (stderr, "RDP Write CP state\n"); +#endif + if (MYread_char (debugsock, &CPnum)) + goto panic_error; + + if (MYread_word (debugsock, &mask)) + goto panic_error; + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + MYwrite_char (mumkid[1], x); + for (k = 1, j = 0; k != 0x80000000; k *= 2, j++) + if (k & x) + { + if ((c == 1 || c == 2) && k <= 128) + { + /* FP register = 12 bytes + 4 bytes format */ + if (passon (debugsock, mumkid[1], 16)) + goto panic_error; + } + else + { + /* Normal register = 4 bytes */ + if (passon (debugsock, mumkid[1], 4)) + goto panic_error; + } + } + break; + + case RDP_SetBreak: + /* Set Breakpoint */ +#ifdef DEBUG + fprintf (stderr, "RDP Set Breakpoint\n"); +#endif + if (MYread_word (debugsock, &x)) + goto panic_error; /* address */ + + if (MYread_char (debugsock, &c)) + goto panic_error; /* type */ + + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], x); + MYwrite_char (mumkid[1], c); + if (((c & 0xf) >= 5) && passon (debugsock, mumkid[1], 4)) + goto panic_error; /* bound */ + break; + + case RDP_ClearBreak: + /* Clear Breakpoint */ +#ifdef DEBUG + fprintf (stderr, "RDP Clear Breakpoint\n"); +#endif + MYwrite_char (mumkid[1], message); + if (passon (debugsock, mumkid[1], 4)) + goto panic_error; /* point */ + break; + + case RDP_SetWatch: + /* Set Watchpoint */ +#ifdef DEBUG + fprintf (stderr, "RDP Set Watchpoint\n"); +#endif + if (MYread_word (debugsock, &x)) + goto panic_error; /* address */ + + if (MYread_char (debugsock, &c)) + goto panic_error; /* type */ + + if (MYread_char (debugsock, &d)) + goto panic_error; /* datatype */ + + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], x); + MYwrite_char (mumkid[1], c); + MYwrite_char (mumkid[1], d); + if (((c & 0xf) >= 5) && passon (debugsock, mumkid[1], 4)) + goto panic_error; /* bound */ + break; + + case RDP_ClearWatch: + /* Clear Watchpoint */ +#ifdef DEBUG + fprintf (stderr, "RDP Clear Watchpoint\n"); +#endif + MYwrite_char (mumkid[1], message); + if (passon (debugsock, mumkid[1], 4)) + goto panic_error; /* point */ + break; + + case RDP_Execute: + /* Excecute */ +#ifdef DEBUG + fprintf (stderr, "RDP Execute\n"); +#endif + + /* LEAVE THIS ONE 'TIL LATER... */ + /* NEED TO WORK THINGS OUT */ + + /* NO ASCYNCHROUS RUNNING */ + + if (MYread_char (debugsock, &c)) + goto panic_error; /* return */ + + /* Remember incase bit 7 is set and we have to send back a word */ + exreturn = c; + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + break; + + case RDP_Step: + /* Step */ +#ifdef DEBUG + fprintf (stderr, "RDP Step\n"); +#endif + + if (MYread_char (debugsock, &c)) + goto panic_error; /* return */ + + if (MYread_word (debugsock, &x)) + goto panic_error; /* ninstr */ + + MYwrite_char (mumkid[1], message); + MYwrite_char (mumkid[1], c); + MYwrite_word (mumkid[1], x); + break; + + case RDP_Info: + /* Info */ +#ifdef DEBUG + fprintf (stderr, "RDP Info\n"); +#endif + /* INFO TARGET, SET RDI LEVEL */ + if (MYread_word (debugsock, &messagetype)) + goto panic_error; /* info */ + + switch (messagetype) + { + case RDIInfo_Target: + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + break; + + case RDISet_RDILevel: + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + if (passon (debugsock, mumkid[1], 1)) + goto panic_error; /* argument */ + break; + + case RDISet_Cmdline: + /* Got to pass on a string argument */ + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + do + { + if (MYread_char (debugsock, &c)) + goto panic_error; + + MYwrite_char (mumkid[1], c); + } + while (c); + break; + + case RDISignal_Stop: + kill (child, SIGUSR1); + MYwrite_char (debugsock, RDP_Return); + MYwrite_char (debugsock, RDIError_UserInterrupt); + break; + + case RDIVector_Catch: + MYread_word (debugsock, &x); + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + MYwrite_word (mumkid[1], x); + break; + + case RDIInfo_Step: + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + break; + + case RDIInfo_Points: + MYwrite_char (mumkid[1], message); + MYwrite_word (mumkid[1], messagetype); + break; + + default: + fprintf (stderr, "Unrecognized RDIInfo request %d\n", + messagetype); + goto panic_error; + } + break; + + case RDP_OSOpReply: + /* OS Operation Reply */ +#ifdef DEBUG + fprintf (stderr, "RDP OS Reply\n"); +#endif + MYwrite_char (mumkid[1], message); + if (MYread_char (debugsock, &message)) + goto panic_error; + MYwrite_char (mumkid[1], message); + switch (message) + { + case 0: /* return value i.e. nothing else. */ + break; + + case 1: /* returns a byte... */ + if (MYread_char (debugsock, &c)) + goto panic_error; + + MYwrite_char (mumkid[1], c); + break; + + case 2: /* returns a word... */ + if (MYread_word (debugsock, &x)) + goto panic_error; + + MYwrite_word (mumkid[1], x); + break; + } + break; + + case RDP_Reset: + /* Reset */ +#ifdef DEBUG + fprintf (stderr, "RDP Reset\n"); +#endif + MYwrite_char (mumkid[1], message); + break; + + default: + /* Hmm.. bad RDP operation */ + fprintf (stderr, "RDP Bad RDP request (%d)\n", message); + MYwrite_char (debugsock, RDP_Return); + MYwrite_char (debugsock, RDIError_UnimplementedMessage); + break; + } + } + + if (FD_ISSET (kidmum[0], &readfds)) + { +#ifdef DEBUG + fprintf (stderr, "->ARMulator\n"); +#endif + /* Anything we get from the ARMulator has to go to the debugger... */ + /* It is that simple! */ + + passon (kidmum[0], debugsock, 1); + } + } +} diff --git a/external/gpl3/gdb/dist/sim/arm/tconfig.in b/external/gpl3/gdb/dist/sim/arm/tconfig.in new file mode 100644 index 000000000000..04f702d5a4ee --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/tconfig.in @@ -0,0 +1,17 @@ +/* ARM target configuration file. */ + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +/* #define SIM_HAVE_PROFILE */ + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +/* #define SIM_HAVE_SIMCACHE */ + +/* Define this if the target cpu is bi-endian + and the simulator supports it. */ +#define SIM_HAVE_BIENDIAN diff --git a/external/gpl3/gdb/dist/sim/arm/thumbemu.c b/external/gpl3/gdb/dist/sim/arm/thumbemu.c new file mode 100644 index 000000000000..8707ca71a64b --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/thumbemu.c @@ -0,0 +1,615 @@ +/* thumbemu.c -- Thumb instruction emulation. + Copyright (C) 1996, Cygnus Software Technologies Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* We can provide simple Thumb simulation by decoding the Thumb +instruction into its corresponding ARM instruction, and using the +existing ARM simulator. */ + +#ifndef MODET /* required for the Thumb instruction support */ +#if 1 +#error "MODET needs to be defined for the Thumb world to work" +#else +#define MODET (1) +#endif +#endif + +#include "armdefs.h" +#include "armemu.h" +#include "armos.h" + +/* Attempt to emulate an ARMv6 instruction. + Stores t_branch into PVALUE upon success or t_undefined otherwise. */ + +static void +handle_v6_thumb_insn (ARMul_State * state, + ARMword tinstr, + tdstate * pvalid) +{ + ARMword Rd; + ARMword Rm; + + if (! state->is_v6) + { + * pvalid = t_undefined; + return; + } + + switch (tinstr & 0xFFC0) + { + case 0xb660: /* cpsie */ + case 0xb670: /* cpsid */ + case 0x4600: /* cpy */ + case 0xba00: /* rev */ + case 0xba40: /* rev16 */ + case 0xbac0: /* revsh */ + case 0xb650: /* setend */ + default: + printf ("Unhandled v6 thumb insn: %04x\n", tinstr); + * pvalid = t_undefined; + return; + + case 0xb200: /* sxth */ + Rm = state->Reg [(tinstr & 0x38) >> 3]; + if (Rm & 0x8000) + state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000; + else + state->Reg [(tinstr & 0x7)] = Rm & 0xffff; + break; + case 0xb240: /* sxtb */ + Rm = state->Reg [(tinstr & 0x38) >> 3]; + if (Rm & 0x80) + state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00; + else + state->Reg [(tinstr & 0x7)] = Rm & 0xff; + break; + case 0xb280: /* uxth */ + Rm = state->Reg [(tinstr & 0x38) >> 3]; + state->Reg [(tinstr & 0x7)] = Rm & 0xffff; + break; + case 0xb2c0: /* uxtb */ + Rm = state->Reg [(tinstr & 0x38) >> 3]; + state->Reg [(tinstr & 0x7)] = Rm & 0xff; + break; + } + /* Indicate that the instruction has been processed. */ + * pvalid = t_branch; +} + +/* Decode a 16bit Thumb instruction. The instruction is in the low + 16-bits of the tinstr field, with the following Thumb instruction + held in the high 16-bits. Passing in two Thumb instructions allows + easier simulation of the special dual BL instruction. */ + +tdstate +ARMul_ThumbDecode (ARMul_State * state, + ARMword pc, + ARMword tinstr, + ARMword * ainstr) +{ + tdstate valid = t_decoded; /* default assumes a valid instruction */ + ARMword next_instr; + + if (state->bigendSig) + { + next_instr = tinstr & 0xFFFF; + tinstr >>= 16; + } + else + { + next_instr = tinstr >> 16; + tinstr &= 0xFFFF; + } + +#if 1 /* debugging to catch non updates */ + *ainstr = 0xDEADC0DE; +#endif + + switch ((tinstr & 0xF800) >> 11) + { + case 0: /* LSL */ + case 1: /* LSR */ + case 2: /* ASR */ + /* Format 1 */ + *ainstr = 0xE1B00000 /* base opcode */ + | ((tinstr & 0x1800) >> (11 - 5)) /* shift type */ + | ((tinstr & 0x07C0) << (7 - 6)) /* imm5 */ + | ((tinstr & 0x0038) >> 3) /* Rs */ + | ((tinstr & 0x0007) << 12); /* Rd */ + break; + case 3: /* ADD/SUB */ + /* Format 2 */ + { + ARMword subset[4] = { + 0xE0900000, /* ADDS Rd,Rs,Rn */ + 0xE0500000, /* SUBS Rd,Rs,Rn */ + 0xE2900000, /* ADDS Rd,Rs,#imm3 */ + 0xE2500000 /* SUBS Rd,Rs,#imm3 */ + }; + /* It is quicker indexing into a table, than performing switch + or conditionals: */ + *ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */ + | ((tinstr & 0x01C0) >> 6) /* Rn or imm3 */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rs */ + | ((tinstr & 0x0007) << (12 - 0)); /* Rd */ + } + break; + case 4: /* MOV */ + case 5: /* CMP */ + case 6: /* ADD */ + case 7: /* SUB */ + /* Format 3 */ + { + ARMword subset[4] = { + 0xE3B00000, /* MOVS Rd,#imm8 */ + 0xE3500000, /* CMP Rd,#imm8 */ + 0xE2900000, /* ADDS Rd,Rd,#imm8 */ + 0xE2500000, /* SUBS Rd,Rd,#imm8 */ + }; + *ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */ + | ((tinstr & 0x00FF) >> 0) /* imm8 */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rn */ + | ((tinstr & 0x0700) << (12 - 8)); /* Rd */ + } + break; + case 8: /* Arithmetic and high register transfers */ + /* TODO: Since the subsets for both Format 4 and Format 5 + instructions are made up of different ARM encodings, we could + save the following conditional, and just have one large + subset. */ + if ((tinstr & (1 << 10)) == 0) + { + /* Format 4 */ + struct + { + ARMword opcode; + enum + { t_norm, t_shift, t_neg, t_mul } + otype; + } + subset[16] = + { + { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */ + { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */ + { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */ + { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */ + { 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */ + { 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */ + { 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */ + { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */ + { 0xE1100000, t_norm}, /* TST Rd,Rs */ + { 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */ + { 0xE1500000, t_norm}, /* CMP Rd,Rs */ + { 0xE1700000, t_norm}, /* CMN Rd,Rs */ + { 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */ + { 0xE0100090, t_mul} , /* MULS Rd,Rd,Rs */ + { 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */ + { 0xE1F00000, t_norm} /* MVNS Rd,Rs */ + }; + *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ + switch (subset[(tinstr & 0x03C0) >> 6].otype) + { + case t_norm: + *ainstr |= ((tinstr & 0x0007) << 16) /* Rn */ + | ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0038) >> 3); /* Rs */ + break; + case t_shift: + *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0007) >> 0) /* Rm */ + | ((tinstr & 0x0038) << (8 - 3)); /* Rs */ + break; + case t_neg: + *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)); /* Rn */ + break; + case t_mul: + *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */ + | ((tinstr & 0x0007) << 8) /* Rs */ + | ((tinstr & 0x0038) >> 3); /* Rm */ + break; + } + } + else + { + /* Format 5 */ + ARMword Rd = ((tinstr & 0x0007) >> 0); + ARMword Rs = ((tinstr & 0x0038) >> 3); + if (tinstr & (1 << 7)) + Rd += 8; + if (tinstr & (1 << 6)) + Rs += 8; + switch ((tinstr & 0x03C0) >> 6) + { + case 0x1: /* ADD Rd,Rd,Hs */ + case 0x2: /* ADD Hd,Hd,Rs */ + case 0x3: /* ADD Hd,Hd,Hs */ + *ainstr = 0xE0800000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0x5: /* CMP Rd,Hs */ + case 0x6: /* CMP Hd,Rs */ + case 0x7: /* CMP Hd,Hs */ + *ainstr = 0xE1500000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0x9: /* MOV Rd,Hs */ + case 0xA: /* MOV Hd,Rs */ + case 0xB: /* MOV Hd,Hs */ + *ainstr = 0xE1A00000 /* base */ + | (Rd << 16) /* Rn */ + | (Rd << 12) /* Rd */ + | (Rs << 0); /* Rm */ + break; + case 0xC: /* BX Rs */ + case 0xD: /* BX Hs */ + *ainstr = 0xE12FFF10 /* base */ + | ((tinstr & 0x0078) >> 3); /* Rd */ + break; + case 0xE: /* UNDEFINED */ + case 0xF: /* UNDEFINED */ + if (state->is_v5) + { + /* BLX Rs; BLX Hs */ + *ainstr = 0xE12FFF30 /* base */ + | ((tinstr & 0x0078) >> 3); /* Rd */ + break; + } + /* Drop through. */ + case 0x0: /* UNDEFINED */ + case 0x4: /* UNDEFINED */ + case 0x8: /* UNDEFINED */ + handle_v6_thumb_insn (state, tinstr, & valid); + break; + } + } + break; + case 9: /* LDR Rd,[PC,#imm8] */ + /* Format 6 */ + *ainstr = 0xE59F0000 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | ((tinstr & 0x00FF) << (2 - 0)); /* off8 */ + break; + case 10: + case 11: + /* TODO: Format 7 and Format 8 perform the same ARM encoding, so + the following could be merged into a single subset, saving on + the following boolean: */ + if ((tinstr & (1 << 9)) == 0) + { + /* Format 7 */ + ARMword subset[4] = { + 0xE7800000, /* STR Rd,[Rb,Ro] */ + 0xE7C00000, /* STRB Rd,[Rb,Ro] */ + 0xE7900000, /* LDR Rd,[Rb,Ro] */ + 0xE7D00000 /* LDRB Rd,[Rb,Ro] */ + }; + *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> 6); /* Ro */ + } + else + { + /* Format 8 */ + ARMword subset[4] = { + 0xE18000B0, /* STRH Rd,[Rb,Ro] */ + 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */ + 0xE19000B0, /* LDRH Rd,[Rb,Ro] */ + 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */ + }; + *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> 6); /* Ro */ + } + break; + case 12: /* STR Rd,[Rb,#imm5] */ + case 13: /* LDR Rd,[Rb,#imm5] */ + case 14: /* STRB Rd,[Rb,#imm5] */ + case 15: /* LDRB Rd,[Rb,#imm5] */ + /* Format 9 */ + { + ARMword subset[4] = { + 0xE5800000, /* STR Rd,[Rb,#imm5] */ + 0xE5900000, /* LDR Rd,[Rb,#imm5] */ + 0xE5C00000, /* STRB Rd,[Rb,#imm5] */ + 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */ + }; + /* The offset range defends on whether we are transferring a + byte or word value: */ + *ainstr = subset[(tinstr & 0x1800) >> 11] /* base */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */ + } + break; + case 16: /* STRH Rd,[Rb,#imm5] */ + case 17: /* LDRH Rd,[Rb,#imm5] */ + /* Format 10 */ + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE1D000B0 /* LDRH */ + : 0xE1C000B0) /* STRH */ + | ((tinstr & 0x0007) << (12 - 0)) /* Rd */ + | ((tinstr & 0x0038) << (16 - 3)) /* Rb */ + | ((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */ + | ((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */ + break; + case 18: /* STR Rd,[SP,#imm8] */ + case 19: /* LDR Rd,[SP,#imm8] */ + /* Format 11 */ + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE59D0000 /* LDR */ + : 0xE58D0000) /* STR */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | ((tinstr & 0x00FF) << 2); /* off8 */ + break; + case 20: /* ADD Rd,PC,#imm8 */ + case 21: /* ADD Rd,SP,#imm8 */ + /* Format 12 */ + if ((tinstr & (1 << 11)) == 0) + { + /* NOTE: The PC value used here should by word aligned */ + /* We encode shift-left-by-2 in the rotate immediate field, + so no shift of off8 is needed. */ + *ainstr = 0xE28F0F00 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | (tinstr & 0x00FF); /* off8 */ + } + else + { + /* We encode shift-left-by-2 in the rotate immediate field, + so no shift of off8 is needed. */ + *ainstr = 0xE28D0F00 /* base */ + | ((tinstr & 0x0700) << (12 - 8)) /* Rd */ + | (tinstr & 0x00FF); /* off8 */ + } + break; + case 22: + case 23: + switch (tinstr & 0x0F00) + { + case 0x0000: + /* Format 13 */ + /* NOTE: The instruction contains a shift left of 2 + equivalent (implemented as ROR #30): */ + *ainstr = ((tinstr & (1 << 7)) /* base */ + ? 0xE24DDF00 /* SUB */ + : 0xE28DDF00) /* ADD */ + | (tinstr & 0x007F); /* off7 */ + break; + case 0x0400: + /* Format 14 - Push */ + * ainstr = 0xE92D0000 | (tinstr & 0x00FF); + break; + case 0x0500: + /* Format 14 - Push + LR */ + * ainstr = 0xE92D4000 | (tinstr & 0x00FF); + break; + case 0x0c00: + /* Format 14 - Pop */ + * ainstr = 0xE8BD0000 | (tinstr & 0x00FF); + break; + case 0x0d00: + /* Format 14 - Pop + PC */ + * ainstr = 0xE8BD8000 | (tinstr & 0x00FF); + break; + case 0x0e00: + if (state->is_v5) + { + /* This is normally an undefined instruction. The v5t architecture + defines this particular pattern as a BKPT instruction, for + hardware assisted debugging. We map onto the arm BKPT + instruction. */ + * ainstr = 0xE1200070 | ((tinstr & 0xf0) << 4) | (tinstr & 0xf); + break; + } + /* Drop through. */ + default: + /* Everything else is an undefined instruction. */ + handle_v6_thumb_insn (state, tinstr, & valid); + break; + } + break; + case 24: /* STMIA */ + case 25: /* LDMIA */ + /* Format 15 */ + *ainstr = ((tinstr & (1 << 11)) /* base */ + ? 0xE8B00000 /* LDMIA */ + : 0xE8A00000) /* STMIA */ + | ((tinstr & 0x0700) << (16 - 8)) /* Rb */ + | (tinstr & 0x00FF); /* mask8 */ + break; + case 26: /* Bcc */ + case 27: /* Bcc/SWI */ + if ((tinstr & 0x0F00) == 0x0F00) + { + /* Format 17 : SWI */ + *ainstr = 0xEF000000; + /* Breakpoint must be handled specially. */ + if ((tinstr & 0x00FF) == 0x18) + *ainstr |= ((tinstr & 0x00FF) << 16); + /* New breakpoint value. See gdb/arm-tdep.c */ + else if ((tinstr & 0x00FF) == 0xFE) + *ainstr |= SWI_Breakpoint; + else + *ainstr |= (tinstr & 0x00FF); + } + else if ((tinstr & 0x0F00) != 0x0E00) + { + /* Format 16 */ + int doit = FALSE; + /* TODO: Since we are doing a switch here, we could just add + the SWI and undefined instruction checks into this + switch to same on a couple of conditionals: */ + switch ((tinstr & 0x0F00) >> 8) + { + case EQ: + doit = ZFLAG; + break; + case NE: + doit = !ZFLAG; + break; + case VS: + doit = VFLAG; + break; + case VC: + doit = !VFLAG; + break; + case MI: + doit = NFLAG; + break; + case PL: + doit = !NFLAG; + break; + case CS: + doit = CFLAG; + break; + case CC: + doit = !CFLAG; + break; + case HI: + doit = (CFLAG && !ZFLAG); + break; + case LS: + doit = (!CFLAG || ZFLAG); + break; + case GE: + doit = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); + break; + case LT: + doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); + break; + case GT: + doit = ((!NFLAG && !VFLAG && !ZFLAG) + || (NFLAG && VFLAG && !ZFLAG)); + break; + case LE: + doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG; + break; + } + if (doit) + { + state->Reg[15] = (pc + 4 + + (((tinstr & 0x7F) << 1) + | ((tinstr & (1 << 7)) ? 0xFFFFFF00 : 0))); + FLUSHPIPE; + } + valid = t_branch; + } + else + /* UNDEFINED : cc=1110(AL) uses different format. */ + handle_v6_thumb_insn (state, tinstr, & valid); + break; + case 28: /* B */ + /* Format 18 */ + state->Reg[15] = (pc + 4 + + (((tinstr & 0x3FF) << 1) + | ((tinstr & (1 << 10)) ? 0xFFFFF800 : 0))); + FLUSHPIPE; + valid = t_branch; + break; + case 29: /* UNDEFINED */ + if (state->is_v5) + { + if (tinstr & 1) + { + handle_v6_thumb_insn (state, tinstr, & valid); + break; + } + /* Drop through. */ + + /* Format 19 */ + /* There is no single ARM instruction equivalent for this + instruction. Also, it should only ever be matched with the + fmt19 "BL/BLX instruction 1" instruction. However, we do + allow the simulation of it on its own, with undefined results + if r14 is not suitably initialised. */ + { + ARMword tmp = (pc + 2); + + state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1)) + & 0xFFFFFFFC); + CLEART; + state->Reg[14] = (tmp | 1); + valid = t_branch; + FLUSHPIPE; + break; + } + } + + handle_v6_thumb_insn (state, tinstr, & valid); + break; + + case 30: /* BL instruction 1 */ + /* Format 19 */ + /* There is no single ARM instruction equivalent for this Thumb + instruction. To keep the simulation simple (from the user + perspective) we check if the following instruction is the + second half of this BL, and if it is we simulate it + immediately. */ + state->Reg[14] = state->Reg[15] \ + + (((tinstr & 0x07FF) << 12) \ + | ((tinstr & (1 << 10)) ? 0xFF800000 : 0)); + + valid = t_branch; /* in-case we don't have the 2nd half */ + tinstr = next_instr; /* move the instruction down */ + pc += 2; /* point the pc at the 2nd half */ + if (((tinstr & 0xF800) >> 11) != 31) + { + if (((tinstr & 0xF800) >> 11) == 29) + { + ARMword tmp = (pc + 2); + + state->Reg[15] = ((state->Reg[14] + + ((tinstr & 0x07FE) << 1)) + & 0xFFFFFFFC); + CLEART; + state->Reg[14] = (tmp | 1); + valid = t_branch; + FLUSHPIPE; + } + else + /* Exit, since not correct instruction. */ + pc -= 2; + break; + } + /* else we fall through to process the second half of the BL */ + pc += 2; /* point the pc at the 2nd half */ + case 31: /* BL instruction 2 */ + /* Format 19 */ + /* There is no single ARM instruction equivalent for this + instruction. Also, it should only ever be matched with the + fmt19 "BL instruction 1" instruction. However, we do allow + the simulation of it on its own, with undefined results if + r14 is not suitably initialised. */ + { + ARMword tmp = pc; + + state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1)); + state->Reg[14] = (tmp | 1); + valid = t_branch; + FLUSHPIPE; + } + break; + } + + return valid; +} diff --git a/external/gpl3/gdb/dist/sim/arm/wrapper.c b/external/gpl3/gdb/dist/sim/arm/wrapper.c new file mode 100644 index 000000000000..504a0e53260e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/arm/wrapper.c @@ -0,0 +1,942 @@ +/* run front end support for arm + Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002, 2007, 2008, 2009, 2010, + 2011 Free Software Foundation, Inc. + + This file is part of ARM SIM. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* This file provides the interface between the simulator and + run.c and gdb (when the simulator is linked with gdb). + All simulator interaction should go through this file. */ + +#include +#include +#include +#include +#include +#include "gdb/callback.h" +#include "gdb/remote-sim.h" +#include "armdefs.h" +#include "armemu.h" +#include "dbg_rdi.h" +#include "ansidecl.h" +#include "sim-utils.h" +#include "run-sim.h" +#include "gdb/sim-arm.h" +#include "gdb/signals.h" + +host_callback *sim_callback; + +static struct ARMul_State *state; + +/* Who is using the simulator. */ +static SIM_OPEN_KIND sim_kind; + +/* argv[0] */ +static char *myname; + +/* Memory size in bytes. */ +static int mem_size = (1 << 21); + +/* Non-zero to display start up banner, and maybe other things. */ +static int verbosity; + +/* Non-zero to set big endian mode. */ +static int big_endian; + +int stop_simulator; + +/* Cirrus DSP registers. + + We need to define these registers outside of maverick.c because + maverick.c might not be linked in unless --target=arm9e-* in which + case wrapper.c will not compile because it tries to access Cirrus + registers. This should all go away once we get the Cirrus and ARM + Coprocessor to coexist in armcopro.c-- aldyh. */ + +struct maverick_regs +{ + union + { + int i; + float f; + } upper; + + union + { + int i; + float f; + } lower; +}; + +union maverick_acc_regs +{ + long double ld; /* Acc registers are 72-bits. */ +}; + +struct maverick_regs DSPregs[16]; +union maverick_acc_regs DSPacc[4]; +ARMword DSPsc; + +static void +init () +{ + static int done; + + if (!done) + { + ARMul_EmulateInit (); + state = ARMul_NewState (); + state->bigendSig = (big_endian ? HIGH : LOW); + ARMul_MemoryInit (state, mem_size); + ARMul_OSInit (state); + state->verbose = verbosity; + done = 1; + } +} + +/* Set verbosity level of simulator. + This is not intended to produce detailed tracing or debugging information. + Just summaries. */ +/* FIXME: common/run.c doesn't do this yet. */ + +void +sim_set_verbose (v) + int v; +{ + verbosity = v; +} + +/* Set the memory size to SIZE bytes. + Must be called before initializing simulator. */ +/* FIXME: Rename to sim_set_mem_size. */ + +void +sim_size (size) + int size; +{ + mem_size = size; +} + +void +ARMul_ConsolePrint VPARAMS ((ARMul_State * state, + const char * format, + ...)) +{ + va_list ap; + + if (state->verbose) + { + va_start (ap, format); + vprintf (format, ap); + va_end (ap); + } +} + +ARMword +ARMul_Debug (state, pc, instr) + ARMul_State * state ATTRIBUTE_UNUSED; + ARMword pc ATTRIBUTE_UNUSED; + ARMword instr ATTRIBUTE_UNUSED; +{ + return 0; +} + +int +sim_write (sd, addr, buffer, size) + SIM_DESC sd ATTRIBUTE_UNUSED; + SIM_ADDR addr; + const unsigned char * buffer; + int size; +{ + int i; + + init (); + + for (i = 0; i < size; i++) + ARMul_SafeWriteByte (state, addr + i, buffer[i]); + + return size; +} + +int +sim_read (sd, addr, buffer, size) + SIM_DESC sd ATTRIBUTE_UNUSED; + SIM_ADDR addr; + unsigned char * buffer; + int size; +{ + int i; + + init (); + + for (i = 0; i < size; i++) + buffer[i] = ARMul_SafeReadByte (state, addr + i); + + return size; +} + +int +sim_trace (sd) + SIM_DESC sd ATTRIBUTE_UNUSED; +{ + (*sim_callback->printf_filtered) + (sim_callback, + "This simulator does not support tracing\n"); + return 1; +} + +int +sim_stop (sd) + SIM_DESC sd ATTRIBUTE_UNUSED; +{ + state->Emulate = STOP; + stop_simulator = 1; + return 1; +} + +void +sim_resume (sd, step, siggnal) + SIM_DESC sd ATTRIBUTE_UNUSED; + int step; + int siggnal ATTRIBUTE_UNUSED; +{ + state->EndCondition = 0; + stop_simulator = 0; + + if (step) + { + state->Reg[15] = ARMul_DoInstr (state); + if (state->EndCondition == 0) + state->EndCondition = RDIError_BreakpointReached; + } + else + { + state->NextInstr = RESUME; /* treat as PC change */ + state->Reg[15] = ARMul_DoProg (state); + } + + FLUSHPIPE; +} + +SIM_RC +sim_create_inferior (sd, abfd, argv, env) + SIM_DESC sd ATTRIBUTE_UNUSED; + struct bfd * abfd; + char ** argv; + char ** env; +{ + int argvlen = 0; + int mach; + char **arg; + + if (abfd != NULL) + ARMul_SetPC (state, bfd_get_start_address (abfd)); + else + ARMul_SetPC (state, 0); /* ??? */ + + mach = bfd_get_mach (abfd); + + switch (mach) + { + default: + (*sim_callback->printf_filtered) + (sim_callback, + "Unknown machine type '%d'; please update sim_create_inferior.\n", + mach); + /* fall through */ + + case 0: + /* We wouldn't set the machine type with earlier toolchains, so we + explicitly select a processor capable of supporting all ARMs in + 32bit mode. */ + /* We choose the XScale rather than the iWMMXt, because the iWMMXt + removes the FPE emulator, since it conflicts with its coprocessors. + For the most generic ARM support, we want the FPE emulator in place. */ + case bfd_mach_arm_XScale: + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop); + break; + + case bfd_mach_arm_iWMMXt: + { + extern int SWI_vector_installed; + ARMword i; + + if (! SWI_vector_installed) + { + /* Intialise the hardware vectors to zero. */ + if (! SWI_vector_installed) + for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) + ARMul_WriteWord (state, i, 0); + + /* ARM_WriteWord will have detected the write to the SWI vector, + but we want SWI_vector_installed to remain at 0 so that thumb + mode breakpoints will work. */ + SWI_vector_installed = 0; + } + } + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop); + break; + + case bfd_mach_arm_ep9312: + ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop); + break; + + case bfd_mach_arm_5: + if (bfd_family_coff (abfd)) + { + /* This is a special case in order to support COFF based ARM toolchains. + The COFF header does not have enough room to store all the different + kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default + to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 + machine type here, we assume it could be any of the above architectures + and so select the most feature-full. */ + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); + break; + } + /* Otherwise drop through. */ + + case bfd_mach_arm_5T: + ARMul_SelectProcessor (state, ARM_v5_Prop); + break; + + case bfd_mach_arm_5TE: + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop); + break; + + case bfd_mach_arm_4: + case bfd_mach_arm_4T: + ARMul_SelectProcessor (state, ARM_v4_Prop); + break; + + case bfd_mach_arm_3: + case bfd_mach_arm_3M: + ARMul_SelectProcessor (state, ARM_Lock_Prop); + break; + + case bfd_mach_arm_2: + case bfd_mach_arm_2a: + ARMul_SelectProcessor (state, ARM_Fix26_Prop); + break; + } + + if ( mach != bfd_mach_arm_3 + && mach != bfd_mach_arm_3M + && mach != bfd_mach_arm_2 + && mach != bfd_mach_arm_2a) + { + /* Reset mode to ARM. A gdb user may rerun a program that had entered + THUMB mode from the start and cause the ARM-mode startup code to be + executed in THUMB mode. */ + ARMul_SetCPSR (state, SVC32MODE); + } + + if (argv != NULL) + { + /* Set up the command line by laboriously stringing together + the environment carefully picked apart by our caller. */ + + /* Free any old stuff. */ + if (state->CommandLine != NULL) + { + free (state->CommandLine); + state->CommandLine = NULL; + } + + /* See how much we need. */ + for (arg = argv; *arg != NULL; arg++) + argvlen += strlen (*arg) + 1; + + /* Allocate it. */ + state->CommandLine = malloc (argvlen + 1); + if (state->CommandLine != NULL) + { + arg = argv; + state->CommandLine[0] = '\0'; + + for (arg = argv; *arg != NULL; arg++) + { + strcat (state->CommandLine, *arg); + strcat (state->CommandLine, " "); + } + } + } + + if (env != NULL) + { + /* Now see if there's a MEMSIZE spec in the environment. */ + while (*env) + { + if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0) + { + char *end_of_num; + + /* Set up memory limit. */ + state->MemSize = + strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0); + } + env++; + } + } + + return SIM_RC_OK; +} + +void +sim_info (sd, verbose) + SIM_DESC sd ATTRIBUTE_UNUSED; + int verbose ATTRIBUTE_UNUSED; +{ +} + +static int +frommem (state, memory) + struct ARMul_State *state; + unsigned char *memory; +{ + if (state->bigendSig == HIGH) + return (memory[0] << 24) | (memory[1] << 16) + | (memory[2] << 8) | (memory[3] << 0); + else + return (memory[3] << 24) | (memory[2] << 16) + | (memory[1] << 8) | (memory[0] << 0); +} + +static void +tomem (state, memory, val) + struct ARMul_State *state; + unsigned char *memory; + int val; +{ + if (state->bigendSig == HIGH) + { + memory[0] = val >> 24; + memory[1] = val >> 16; + memory[2] = val >> 8; + memory[3] = val >> 0; + } + else + { + memory[3] = val >> 24; + memory[2] = val >> 16; + memory[1] = val >> 8; + memory[0] = val >> 0; + } +} + +int +sim_store_register (sd, rn, memory, length) + SIM_DESC sd ATTRIBUTE_UNUSED; + int rn; + unsigned char *memory; + int length ATTRIBUTE_UNUSED; +{ + init (); + + switch ((enum sim_arm_regs) rn) + { + case SIM_ARM_R0_REGNUM: + case SIM_ARM_R1_REGNUM: + case SIM_ARM_R2_REGNUM: + case SIM_ARM_R3_REGNUM: + case SIM_ARM_R4_REGNUM: + case SIM_ARM_R5_REGNUM: + case SIM_ARM_R6_REGNUM: + case SIM_ARM_R7_REGNUM: + case SIM_ARM_R8_REGNUM: + case SIM_ARM_R9_REGNUM: + case SIM_ARM_R10_REGNUM: + case SIM_ARM_R11_REGNUM: + case SIM_ARM_R12_REGNUM: + case SIM_ARM_R13_REGNUM: + case SIM_ARM_R14_REGNUM: + case SIM_ARM_R15_REGNUM: /* PC */ + case SIM_ARM_FP0_REGNUM: + case SIM_ARM_FP1_REGNUM: + case SIM_ARM_FP2_REGNUM: + case SIM_ARM_FP3_REGNUM: + case SIM_ARM_FP4_REGNUM: + case SIM_ARM_FP5_REGNUM: + case SIM_ARM_FP6_REGNUM: + case SIM_ARM_FP7_REGNUM: + case SIM_ARM_FPS_REGNUM: + ARMul_SetReg (state, state->Mode, rn, frommem (state, memory)); + break; + + case SIM_ARM_PS_REGNUM: + state->Cpsr = frommem (state, memory); + ARMul_CPSRAltered (state); + break; + + case SIM_ARM_MAVERIC_COP0R0_REGNUM: + case SIM_ARM_MAVERIC_COP0R1_REGNUM: + case SIM_ARM_MAVERIC_COP0R2_REGNUM: + case SIM_ARM_MAVERIC_COP0R3_REGNUM: + case SIM_ARM_MAVERIC_COP0R4_REGNUM: + case SIM_ARM_MAVERIC_COP0R5_REGNUM: + case SIM_ARM_MAVERIC_COP0R6_REGNUM: + case SIM_ARM_MAVERIC_COP0R7_REGNUM: + case SIM_ARM_MAVERIC_COP0R8_REGNUM: + case SIM_ARM_MAVERIC_COP0R9_REGNUM: + case SIM_ARM_MAVERIC_COP0R10_REGNUM: + case SIM_ARM_MAVERIC_COP0R11_REGNUM: + case SIM_ARM_MAVERIC_COP0R12_REGNUM: + case SIM_ARM_MAVERIC_COP0R13_REGNUM: + case SIM_ARM_MAVERIC_COP0R14_REGNUM: + case SIM_ARM_MAVERIC_COP0R15_REGNUM: + memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], + memory, sizeof (struct maverick_regs)); + return sizeof (struct maverick_regs); + + case SIM_ARM_MAVERIC_DSPSC_REGNUM: + memcpy (&DSPsc, memory, sizeof DSPsc); + return sizeof DSPsc; + + case SIM_ARM_IWMMXT_COP0R0_REGNUM: + case SIM_ARM_IWMMXT_COP0R1_REGNUM: + case SIM_ARM_IWMMXT_COP0R2_REGNUM: + case SIM_ARM_IWMMXT_COP0R3_REGNUM: + case SIM_ARM_IWMMXT_COP0R4_REGNUM: + case SIM_ARM_IWMMXT_COP0R5_REGNUM: + case SIM_ARM_IWMMXT_COP0R6_REGNUM: + case SIM_ARM_IWMMXT_COP0R7_REGNUM: + case SIM_ARM_IWMMXT_COP0R8_REGNUM: + case SIM_ARM_IWMMXT_COP0R9_REGNUM: + case SIM_ARM_IWMMXT_COP0R10_REGNUM: + case SIM_ARM_IWMMXT_COP0R11_REGNUM: + case SIM_ARM_IWMMXT_COP0R12_REGNUM: + case SIM_ARM_IWMMXT_COP0R13_REGNUM: + case SIM_ARM_IWMMXT_COP0R14_REGNUM: + case SIM_ARM_IWMMXT_COP0R15_REGNUM: + case SIM_ARM_IWMMXT_COP1R0_REGNUM: + case SIM_ARM_IWMMXT_COP1R1_REGNUM: + case SIM_ARM_IWMMXT_COP1R2_REGNUM: + case SIM_ARM_IWMMXT_COP1R3_REGNUM: + case SIM_ARM_IWMMXT_COP1R4_REGNUM: + case SIM_ARM_IWMMXT_COP1R5_REGNUM: + case SIM_ARM_IWMMXT_COP1R6_REGNUM: + case SIM_ARM_IWMMXT_COP1R7_REGNUM: + case SIM_ARM_IWMMXT_COP1R8_REGNUM: + case SIM_ARM_IWMMXT_COP1R9_REGNUM: + case SIM_ARM_IWMMXT_COP1R10_REGNUM: + case SIM_ARM_IWMMXT_COP1R11_REGNUM: + case SIM_ARM_IWMMXT_COP1R12_REGNUM: + case SIM_ARM_IWMMXT_COP1R13_REGNUM: + case SIM_ARM_IWMMXT_COP1R14_REGNUM: + case SIM_ARM_IWMMXT_COP1R15_REGNUM: + return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); + + default: + return 0; + } + + return -1; +} + +int +sim_fetch_register (sd, rn, memory, length) + SIM_DESC sd ATTRIBUTE_UNUSED; + int rn; + unsigned char *memory; + int length ATTRIBUTE_UNUSED; +{ + ARMword regval; + + init (); + + switch ((enum sim_arm_regs) rn) + { + case SIM_ARM_R0_REGNUM: + case SIM_ARM_R1_REGNUM: + case SIM_ARM_R2_REGNUM: + case SIM_ARM_R3_REGNUM: + case SIM_ARM_R4_REGNUM: + case SIM_ARM_R5_REGNUM: + case SIM_ARM_R6_REGNUM: + case SIM_ARM_R7_REGNUM: + case SIM_ARM_R8_REGNUM: + case SIM_ARM_R9_REGNUM: + case SIM_ARM_R10_REGNUM: + case SIM_ARM_R11_REGNUM: + case SIM_ARM_R12_REGNUM: + case SIM_ARM_R13_REGNUM: + case SIM_ARM_R14_REGNUM: + case SIM_ARM_R15_REGNUM: /* PC */ + regval = ARMul_GetReg (state, state->Mode, rn); + break; + + case SIM_ARM_FP0_REGNUM: + case SIM_ARM_FP1_REGNUM: + case SIM_ARM_FP2_REGNUM: + case SIM_ARM_FP3_REGNUM: + case SIM_ARM_FP4_REGNUM: + case SIM_ARM_FP5_REGNUM: + case SIM_ARM_FP6_REGNUM: + case SIM_ARM_FP7_REGNUM: + case SIM_ARM_FPS_REGNUM: + memset (memory, 0, length); + return 0; + + case SIM_ARM_PS_REGNUM: + regval = ARMul_GetCPSR (state); + break; + + case SIM_ARM_MAVERIC_COP0R0_REGNUM: + case SIM_ARM_MAVERIC_COP0R1_REGNUM: + case SIM_ARM_MAVERIC_COP0R2_REGNUM: + case SIM_ARM_MAVERIC_COP0R3_REGNUM: + case SIM_ARM_MAVERIC_COP0R4_REGNUM: + case SIM_ARM_MAVERIC_COP0R5_REGNUM: + case SIM_ARM_MAVERIC_COP0R6_REGNUM: + case SIM_ARM_MAVERIC_COP0R7_REGNUM: + case SIM_ARM_MAVERIC_COP0R8_REGNUM: + case SIM_ARM_MAVERIC_COP0R9_REGNUM: + case SIM_ARM_MAVERIC_COP0R10_REGNUM: + case SIM_ARM_MAVERIC_COP0R11_REGNUM: + case SIM_ARM_MAVERIC_COP0R12_REGNUM: + case SIM_ARM_MAVERIC_COP0R13_REGNUM: + case SIM_ARM_MAVERIC_COP0R14_REGNUM: + case SIM_ARM_MAVERIC_COP0R15_REGNUM: + memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], + sizeof (struct maverick_regs)); + return sizeof (struct maverick_regs); + + case SIM_ARM_MAVERIC_DSPSC_REGNUM: + memcpy (memory, & DSPsc, sizeof DSPsc); + return sizeof DSPsc; + + case SIM_ARM_IWMMXT_COP0R0_REGNUM: + case SIM_ARM_IWMMXT_COP0R1_REGNUM: + case SIM_ARM_IWMMXT_COP0R2_REGNUM: + case SIM_ARM_IWMMXT_COP0R3_REGNUM: + case SIM_ARM_IWMMXT_COP0R4_REGNUM: + case SIM_ARM_IWMMXT_COP0R5_REGNUM: + case SIM_ARM_IWMMXT_COP0R6_REGNUM: + case SIM_ARM_IWMMXT_COP0R7_REGNUM: + case SIM_ARM_IWMMXT_COP0R8_REGNUM: + case SIM_ARM_IWMMXT_COP0R9_REGNUM: + case SIM_ARM_IWMMXT_COP0R10_REGNUM: + case SIM_ARM_IWMMXT_COP0R11_REGNUM: + case SIM_ARM_IWMMXT_COP0R12_REGNUM: + case SIM_ARM_IWMMXT_COP0R13_REGNUM: + case SIM_ARM_IWMMXT_COP0R14_REGNUM: + case SIM_ARM_IWMMXT_COP0R15_REGNUM: + case SIM_ARM_IWMMXT_COP1R0_REGNUM: + case SIM_ARM_IWMMXT_COP1R1_REGNUM: + case SIM_ARM_IWMMXT_COP1R2_REGNUM: + case SIM_ARM_IWMMXT_COP1R3_REGNUM: + case SIM_ARM_IWMMXT_COP1R4_REGNUM: + case SIM_ARM_IWMMXT_COP1R5_REGNUM: + case SIM_ARM_IWMMXT_COP1R6_REGNUM: + case SIM_ARM_IWMMXT_COP1R7_REGNUM: + case SIM_ARM_IWMMXT_COP1R8_REGNUM: + case SIM_ARM_IWMMXT_COP1R9_REGNUM: + case SIM_ARM_IWMMXT_COP1R10_REGNUM: + case SIM_ARM_IWMMXT_COP1R11_REGNUM: + case SIM_ARM_IWMMXT_COP1R12_REGNUM: + case SIM_ARM_IWMMXT_COP1R13_REGNUM: + case SIM_ARM_IWMMXT_COP1R14_REGNUM: + case SIM_ARM_IWMMXT_COP1R15_REGNUM: + return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); + + default: + return 0; + } + + while (length) + { + tomem (state, memory, regval); + + length -= 4; + memory += 4; + regval = 0; + } + + return -1; +} + +#ifdef SIM_TARGET_SWITCHES + +static void sim_target_parse_arg_array PARAMS ((char **)); + +typedef struct +{ + char * swi_option; + unsigned int swi_mask; +} swi_options; + +#define SWI_SWITCH "--swi-support" + +static swi_options options[] = + { + { "none", 0 }, + { "demon", SWI_MASK_DEMON }, + { "angel", SWI_MASK_ANGEL }, + { "redboot", SWI_MASK_REDBOOT }, + { "all", -1 }, + { "NONE", 0 }, + { "DEMON", SWI_MASK_DEMON }, + { "ANGEL", SWI_MASK_ANGEL }, + { "REDBOOT", SWI_MASK_REDBOOT }, + { "ALL", -1 } + }; + + +int +sim_target_parse_command_line (argc, argv) + int argc; + char ** argv; +{ + int i; + + for (i = 1; i < argc; i++) + { + char * ptr = argv[i]; + int arg; + + if ((ptr == NULL) || (* ptr != '-')) + break; + + if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0) + continue; + + if (ptr[sizeof SWI_SWITCH - 1] == 0) + { + /* Remove this option from the argv array. */ + for (arg = i; arg < argc; arg ++) + argv[arg] = argv[arg + 1]; + argc --; + + ptr = argv[i]; + } + else + ptr += sizeof SWI_SWITCH; + + swi_mask = 0; + + while (* ptr) + { + int i; + + for (i = sizeof options / sizeof options[0]; i--;) + if (strncmp (ptr, options[i].swi_option, + strlen (options[i].swi_option)) == 0) + { + swi_mask |= options[i].swi_mask; + ptr += strlen (options[i].swi_option); + + if (* ptr == ',') + ++ ptr; + + break; + } + + if (i < 0) + break; + } + + if (* ptr != 0) + fprintf (stderr, "Ignoring swi options: %s\n", ptr); + + /* Remove this option from the argv array. */ + for (arg = i; arg < argc; arg ++) + argv[arg] = argv[arg + 1]; + argc --; + i --; + } + return argc; +} + +static void +sim_target_parse_arg_array (argv) + char ** argv; +{ + int i; + + for (i = 0; argv[i]; i++) + ; + + sim_target_parse_command_line (i, argv); +} + +void +sim_target_display_usage (help) + int help; +{ + FILE *stream = help ? stdout : stderr; + + fprintf (stream, "%s= Comma seperated list of SWI protocols to supoport.\n\ + This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n", + SWI_SWITCH); +} +#endif + +SIM_DESC +sim_open (kind, ptr, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *ptr; + struct bfd *abfd; + char **argv; +{ + sim_kind = kind; + if (myname) free (myname); + myname = (char *) xstrdup (argv[0]); + sim_callback = ptr; + +#ifdef SIM_TARGET_SWITCHES + sim_target_parse_arg_array (argv); +#endif + + /* Decide upon the endian-ness of the processor. + If we can, get the information from the bfd itself. + Otherwise look to see if we have been given a command + line switch that tells us. Otherwise default to little endian. */ + if (abfd != NULL) + big_endian = bfd_big_endian (abfd); + else if (argv[1] != NULL) + { + int i; + + /* Scan for endian-ness and memory-size switches. */ + for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++) + if (argv[i][0] == '-' && argv[i][1] == 'E') + { + char c; + + if ((c = argv[i][2]) == 0) + { + ++i; + c = argv[i][0]; + } + + switch (c) + { + case 0: + sim_callback->printf_filtered + (sim_callback, "No argument to -E option provided\n"); + break; + + case 'b': + case 'B': + big_endian = 1; + break; + + case 'l': + case 'L': + big_endian = 0; + break; + + default: + sim_callback->printf_filtered + (sim_callback, "Unrecognised argument to -E option\n"); + break; + } + } + else if (argv[i][0] == '-' && argv[i][1] == 'm') + { + if (argv[i][2] != '\0') + sim_size (atoi (&argv[i][2])); + else if (argv[i + 1] != NULL) + { + sim_size (atoi (argv[i + 1])); + i++; + } + else + { + sim_callback->printf_filtered (sim_callback, + "Missing argument to -m option\n"); + return NULL; + } + + } + } + + return (SIM_DESC) 1; +} + +void +sim_close (sd, quitting) + SIM_DESC sd ATTRIBUTE_UNUSED; + int quitting ATTRIBUTE_UNUSED; +{ + if (myname) + free (myname); + myname = NULL; +} + +SIM_RC +sim_load (sd, prog, abfd, from_tty) + SIM_DESC sd; + char *prog; + bfd *abfd; + int from_tty ATTRIBUTE_UNUSED; +{ + bfd *prog_bfd; + + prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd, + sim_kind == SIM_OPEN_DEBUG, 0, sim_write); + if (prog_bfd == NULL) + return SIM_RC_FAIL; + ARMul_SetPC (state, bfd_get_start_address (prog_bfd)); + if (abfd == NULL) + bfd_close (prog_bfd); + return SIM_RC_OK; +} + +void +sim_stop_reason (sd, reason, sigrc) + SIM_DESC sd ATTRIBUTE_UNUSED; + enum sim_stop *reason; + int *sigrc; +{ + if (stop_simulator) + { + *reason = sim_stopped; + *sigrc = TARGET_SIGNAL_INT; + } + else if (state->EndCondition == 0) + { + *reason = sim_exited; + *sigrc = state->Reg[0] & 255; + } + else + { + *reason = sim_stopped; + if (state->EndCondition == RDIError_BreakpointReached) + *sigrc = TARGET_SIGNAL_TRAP; + else if ( state->EndCondition == RDIError_DataAbort + || state->EndCondition == RDIError_AddressException) + *sigrc = TARGET_SIGNAL_BUS; + else + *sigrc = 0; + } +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd ATTRIBUTE_UNUSED; + char *cmd ATTRIBUTE_UNUSED; +{ + (*sim_callback->printf_filtered) + (sim_callback, + "This simulator does not accept any commands.\n"); +} + +void +sim_set_callbacks (ptr) + host_callback *ptr; +{ + sim_callback = ptr; +} diff --git a/external/gpl3/gdb/dist/sim/avr/ChangeLog b/external/gpl3/gdb/dist/sim/avr/ChangeLog new file mode 100644 index 000000000000..a03bde85b917 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/ChangeLog @@ -0,0 +1,3 @@ +2010-04-14 Mike Frysinger + + * interp.c (sim_write): Add const to buffer arg. diff --git a/external/gpl3/gdb/dist/sim/avr/Makefile.in b/external/gpl3/gdb/dist/sim/avr/Makefile.in new file mode 100644 index 000000000000..a10af556e137 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/Makefile.in @@ -0,0 +1,24 @@ +# Makefile template for Configure for the AVR sim library. +# Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +## COMMON_PRE_CONFIG_FRAG + +SIM_OBJS = interp.o sim-load.o +SIM_EXTRA_LIBS = -lm + +## COMMON_POST_CONFIG_FRAG + +interp.o: interp.c diff --git a/external/gpl3/gdb/dist/sim/avr/config.in b/external/gpl3/gdb/dist/sim/avr/config.in new file mode 100644 index 000000000000..f29d045645ee --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/config.in @@ -0,0 +1,104 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ZLIB_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Additional package description */ +#undef PKGVERSION + +/* Bug reporting address */ +#undef REPORT_BUGS_TO + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS diff --git a/external/gpl3/gdb/dist/sim/avr/configure b/external/gpl3/gdb/dist/sim/avr/configure new file mode 100755 index 000000000000..58e42de30612 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/configure @@ -0,0 +1,5863 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. 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" >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +ALL_LINGUAS= +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../../intl/config.intl; then + . ../../intl/config.intl +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } +if test x"$USE_NLS" != xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define ENABLE_NLS 1" >>confdefs.h + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5 +$as_echo_n "checking for catalogs to be installed... " >&6; } + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5 +$as_echo "$LINGUAS" >&6; } + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in stdlib.h string.h strings.h unistd.h time.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in sys/time.h sys/resource.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in fcntl.h fpu_control.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in dlfcn.h errno.h sys/stat.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_func in getrusage time sigaction __setfpucw +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + +# Check for socket libraries +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5 +$as_echo_n "checking for bind in -lsocket... " >&6; } +if test "${ac_cv_lib_socket_bind+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsocket $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char bind (); +int +main () +{ +return bind (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_socket_bind=yes +else + ac_cv_lib_socket_bind=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5 +$as_echo "$ac_cv_lib_socket_bind" >&6; } +if test "x$ac_cv_lib_socket_bind" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBSOCKET 1 +_ACEOF + + LIBS="-lsocket $LIBS" + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 +$as_echo_n "checking for gethostbyname in -lnsl... " >&6; } +if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lnsl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char gethostbyname (); +int +main () +{ +return gethostbyname (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_nsl_gethostbyname=yes +else + ac_cv_lib_nsl_gethostbyname=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 +$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } +if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBNSL 1 +_ACEOF + + LIBS="-lnsl $LIBS" + +fi + + +# BFD conditionally uses zlib, so we must link it in if libbfd does, by +# using the same condition. + + # See if the user specified whether he wants zlib support or not. + +# Check whether --with-zlib was given. +if test "${with_zlib+set}" = set; then : + withval=$with_zlib; +else + with_zlib=auto +fi + + + if test "$with_zlib" != "no"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5 +$as_echo_n "checking for library containing zlibVersion... " >&6; } +if test "${ac_cv_search_zlibVersion+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char zlibVersion (); +int +main () +{ +return zlibVersion (); + ; + return 0; +} +_ACEOF +for ac_lib in '' z; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_zlibVersion=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_zlibVersion+set}" = set; then : + break +fi +done +if test "${ac_cv_search_zlibVersion+set}" = set; then : + +else + ac_cv_search_zlibVersion=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_zlibVersion" >&5 +$as_echo "$ac_cv_search_zlibVersion" >&6; } +ac_res=$ac_cv_search_zlibVersion +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + for ac_header in zlib.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default" +if test "x$ac_cv_header_zlib_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ZLIB_H 1 +_ACEOF + +fi + +done + +fi + + if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then + as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 + fi + fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then : + enableval=$enable_maintainer_mode; case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) as_fn_error "\"--enable-maintainer-mode does not take a value\"" "$LINENO" 5; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then : + enableval=$enable_sim_bswap; case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) as_fn_error "\"--enable-sim-bswap does not take a value\"" "$LINENO" 5; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then : + enableval=$enable_sim_cflags; case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) as_fn_error "\"Please use --enable-sim-debug instead.\"" "$LINENO" 5; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then : + enableval=$enable_sim_debug; case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then : + enableval=$enable_sim_stdio; case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-stdio\"" "$LINENO" 5; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then : + enableval=$enable_sim_trace; case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then : + enableval=$enable_sim_profile; case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + + +# Check whether --with-pkgversion was given. +if test "${with_pkgversion+set}" = set; then : + withval=$with_pkgversion; case "$withval" in + yes) as_fn_error "package version not specified" "$LINENO" 5 ;; + no) PKGVERSION= ;; + *) PKGVERSION="($withval) " ;; + esac +else + PKGVERSION="(GDB) " + +fi + + + + + +# Check whether --with-bugurl was given. +if test "${with_bugurl+set}" = set; then : + withval=$with_bugurl; case "$withval" in + yes) as_fn_error "bug URL not specified" "$LINENO" 5 ;; + no) BUGURL= + ;; + *) BUGURL="$withval" + ;; + esac +else + BUGURL="http://www.gnu.org/software/gdb/bugs/" + +fi + + case ${BUGURL} in + "") + REPORT_BUGS_TO= + REPORT_BUGS_TEXI= + ;; + *) + REPORT_BUGS_TO="<$BUGURL>" + REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`} + ;; + esac; + + + + +cat >>confdefs.h <<_ACEOF +#define PKGVERSION "$PKGVERSION" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define REPORT_BUGS_TO "$REPORT_BUGS_TO" +_ACEOF + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_type_signal=int +else + ac_cv_type_signal=void +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + + +ac_sources="$sim_link_files" +ac_dests="$sim_link_links" +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source" +done +ac_config_links="$ac_config_links $ac_config_links_1" + +cgen_breaks="" +if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then +cgen_breaks="break cgen_rtx_error"; +fi + +ac_config_files="$ac_config_files Makefile.sim:Makefile.in" + +ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in" + +ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in" + +ac_config_commands="$ac_config_commands Makefile" + +ac_config_commands="$ac_config_commands stamp-h" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_links="$ac_config_links" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration links: +$config_links + +Configuration commands: +$config_commands + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "$ac_config_links_1") CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;; + "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;; + "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;; + ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;; + "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;; + "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :L $CONFIG_LINKS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. 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Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + :L) + # + # CONFIG_LINK + # + + if test "$ac_source" = "$ac_file" && test "$srcdir" = '.'; then + : + else + # Prefer the file from the source tree if names are identical. + if test "$ac_source" = "$ac_file" || test ! -r "$ac_source"; then + ac_source=$srcdir/$ac_source + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: linking $ac_source to $ac_file" >&5 +$as_echo "$as_me: linking $ac_source to $ac_file" >&6;} + + if test ! -r "$ac_source"; then + as_fn_error "$ac_source: file not found" "$LINENO" 5 + fi + rm -f "$ac_file" + + # Try a relative symlink, then a hard link, then a copy. + case $srcdir in + [\\/$]* | ?:[\\/]* ) ac_rel_source=$ac_source ;; + *) ac_rel_source=$ac_top_build_prefix$ac_source ;; + esac + ln -s "$ac_rel_source" "$ac_file" 2>/dev/null || + ln "$ac_source" "$ac_file" 2>/dev/null || + cp -p "$ac_source" "$ac_file" || + as_fn_error "cannot link or copy $ac_source to $ac_file" "$LINENO" 5 + fi + ;; + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + "stamp-h":C) echo > stamp-h ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + + diff --git a/external/gpl3/gdb/dist/sim/avr/configure.ac b/external/gpl3/gdb/dist/sim/avr/configure.ac new file mode 100644 index 000000000000..59ce35c2aae5 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/configure.ac @@ -0,0 +1,12 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(config.h:config.in) + +sinclude(../common/aclocal.m4) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +SIM_AC_OUTPUT diff --git a/external/gpl3/gdb/dist/sim/avr/interp.c b/external/gpl3/gdb/dist/sim/avr/interp.c new file mode 100644 index 000000000000..818f04ef80ed --- /dev/null +++ b/external/gpl3/gdb/dist/sim/avr/interp.c @@ -0,0 +1,1855 @@ +/* Simulator for Atmel's AVR core. + Copyright (C) 2009, 2010, 2011 Free Software Foundation, Inc. + Written by Tristan Gingold, AdaCore. + + This file is part of GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#ifdef HAVE_STRING_H +#include +#endif +#include "bfd.h" +#include "gdb/callback.h" +#include "gdb/signals.h" +#include "libiberty.h" +#include "gdb/remote-sim.h" +#include "dis-asm.h" +#include "sim-utils.h" + +/* As AVR is a 8/16 bits processor, define handy types. */ +typedef unsigned short int word; +typedef signed short int sword; +typedef unsigned char byte; +typedef signed char sbyte; + +/* Debug flag to display instructions and registers. */ +static int tracing = 0; +static int lock_step = 0; +static int verbose; + +/* The only real register. */ +static unsigned int pc; + +/* We update a cycle counter. */ +static unsigned int cycles = 0; + +/* If true, the pc needs more than 2 bytes. */ +static int avr_pc22; + +static struct bfd *cur_bfd; + +static enum sim_stop cpu_exception; +static int cpu_signal; + +static SIM_OPEN_KIND sim_kind; +static char *myname; +static host_callback *callback; + +/* Max size of I space (which is always flash on avr). */ +#define MAX_AVR_FLASH (128 * 1024) +#define PC_MASK (MAX_AVR_FLASH - 1) + +/* Mac size of D space. */ +#define MAX_AVR_SRAM (64 * 1024) +#define SRAM_MASK (MAX_AVR_SRAM - 1) + +/* D space offset in ELF file. */ +#define SRAM_VADDR 0x800000 + +/* Simulator specific ports. */ +#define STDIO_PORT 0x52 +#define EXIT_PORT 0x4F +#define ABORT_PORT 0x49 + +/* GDB defined register numbers. */ +#define AVR_SREG_REGNUM 32 +#define AVR_SP_REGNUM 33 +#define AVR_PC_REGNUM 34 + +/* Memory mapped registers. */ +#define SREG 0x5F +#define REG_SP 0x5D +#define EIND 0x5C +#define RAMPZ 0x5B + +#define REGX 0x1a +#define REGY 0x1c +#define REGZ 0x1e +#define REGZ_LO 0x1e +#define REGZ_HI 0x1f + +/* Sreg (status) bits. */ +#define SREG_I 0x80 +#define SREG_T 0x40 +#define SREG_H 0x20 +#define SREG_S 0x10 +#define SREG_V 0x08 +#define SREG_N 0x04 +#define SREG_Z 0x02 +#define SREG_C 0x01 + +/* In order to speed up emulation we use a simple approach: + a code is associated with each instruction. The pre-decoding occurs + usually once when the instruction is first seen. + This works well because I&D spaces are separated. + + Missing opcodes: sleep, spm, wdr (as they are mmcu dependent). +*/ +enum avr_opcode + { + /* Opcode not yet decoded. */ + OP_unknown, + OP_bad, + + OP_nop, + + OP_rjmp, + OP_rcall, + OP_ret, + OP_reti, + + OP_break, + + OP_brbs, + OP_brbc, + + OP_bset, + OP_bclr, + + OP_bld, + OP_bst, + + OP_sbrc, + OP_sbrs, + + OP_eor, + OP_and, + OP_andi, + OP_or, + OP_ori, + OP_com, + OP_swap, + OP_neg, + + OP_out, + OP_in, + OP_cbi, + OP_sbi, + + OP_sbic, + OP_sbis, + + OP_ldi, + OP_cpse, + OP_cp, + OP_cpi, + OP_cpc, + OP_sub, + OP_sbc, + OP_sbiw, + OP_adiw, + OP_add, + OP_adc, + OP_subi, + OP_sbci, + OP_inc, + OP_dec, + OP_lsr, + OP_ror, + OP_asr, + + OP_mul, + OP_muls, + OP_mulsu, + OP_fmul, + OP_fmuls, + OP_fmulsu, + + OP_mov, + OP_movw, + + OP_push, + OP_pop, + + OP_st_X, + OP_st_dec_X, + OP_st_X_inc, + OP_st_Y_inc, + OP_st_dec_Y, + OP_st_Z_inc, + OP_st_dec_Z, + OP_std_Y, + OP_std_Z, + OP_ldd_Y, + OP_ldd_Z, + OP_ld_Z_inc, + OP_ld_dec_Z, + OP_ld_Y_inc, + OP_ld_dec_Y, + OP_ld_X, + OP_ld_X_inc, + OP_ld_dec_X, + + OP_lpm, + OP_lpm_Z, + OP_lpm_inc_Z, + OP_elpm, + OP_elpm_Z, + OP_elpm_inc_Z, + + OP_ijmp, + OP_icall, + + OP_eijmp, + OP_eicall, + + /* 2 words opcodes. */ +#define OP_2words OP_jmp + OP_jmp, + OP_call, + OP_sts, + OP_lds + }; + +struct avr_insn_cell +{ + /* The insn (16 bits). */ + word op; + + /* Pre-decoding code. */ + enum avr_opcode code : 8; + /* One byte of additional information. */ + byte r; +}; + +/* I&D memories. */ +static struct avr_insn_cell flash[MAX_AVR_FLASH]; +static byte sram[MAX_AVR_SRAM]; + +void +sim_size (int s) +{ +} + +/* Sign extend a value. */ +static int sign_ext (word val, int nb_bits) +{ + if (val & (1 << (nb_bits - 1))) + return val | (-1 << nb_bits); + return val; +} + +/* Insn field extractors. */ + +/* Extract xxxx_xxxRx_xxxx_RRRR. */ +static inline byte get_r (word op) +{ + return (op & 0xf) | ((op >> 5) & 0x10); +} + +/* Extract xxxx_xxxxx_xxxx_RRRR. */ +static inline byte get_r16 (word op) +{ + return 16 + (op & 0xf); +} + +/* Extract xxxx_xxxxx_xxxx_xRRR. */ +static inline byte get_r16_23 (word op) +{ + return 16 + (op & 0x7); +} + +/* Extract xxxx_xxxD_DDDD_xxxx. */ +static inline byte get_d (word op) +{ + return (op >> 4) & 0x1f; +} + +/* Extract xxxx_xxxx_DDDD_xxxx. */ +static inline byte get_d16 (word op) +{ + return 16 + ((op >> 4) & 0x0f); +} + +/* Extract xxxx_xxxx_xDDD_xxxx. */ +static inline byte get_d16_23 (word op) +{ + return 16 + ((op >> 4) & 0x07); +} + +/* Extract xxxx_xAAx_xxxx_AAAA. */ +static inline byte get_A (word op) +{ + return (op & 0x0f) | ((op & 0x600) >> 5); +} + +/* Extract xxxx_xxxx_AAAA_Axxx. */ +static inline byte get_biA (word op) +{ + return (op >> 3) & 0x1f; +} + +/* Extract xxxx_KKKK_xxxx_KKKK. */ +static inline byte get_K (word op) +{ + return (op & 0xf) | ((op & 0xf00) >> 4); +} + +/* Extract xxxx_xxKK_KKKK_Kxxx. */ +static inline int get_k (word op) +{ + return sign_ext ((op & 0x3f8) >> 3, 7); +} + +/* Extract xxxx_xxxx_xxDD_xxxx. */ +static inline byte get_d24 (word op) +{ + return 24 + ((op >> 3) & 6); +} + +/* Extract xxxx_xxxx_KKxx_KKKK. */ +static inline byte get_k6 (word op) +{ + return (op & 0xf) | ((op >> 2) & 0x30); +} + +/* Extract xxQx_QQxx_xxxx_xQQQ. */ +static inline byte get_q (word op) +{ + return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20); +} + +/* Extract xxxx_xxxx_xxxx_xBBB. */ +static inline byte get_b (word op) +{ + return (op & 7); +} + +/* AVR is little endian. */ +static inline word +read_word (unsigned int addr) +{ + return sram[addr] | (sram[addr + 1] << 8); +} + +static inline void +write_word (unsigned int addr, word w) +{ + sram[addr] = w; + sram[addr + 1] = w >> 8; +} + +static inline word +read_word_post_inc (unsigned int addr) +{ + word v = read_word (addr); + write_word (addr, v + 1); + return v; +} + +static inline word +read_word_pre_dec (unsigned int addr) +{ + word v = read_word (addr) - 1; + write_word (addr, v); + return v; +} + +static void +update_flags_logic (byte res) +{ + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); + if (res == 0) + sram[SREG] |= SREG_Z; + if (res & 0x80) + sram[SREG] |= SREG_N | SREG_S; +} + +static void +update_flags_add (byte r, byte a, byte b) +{ + byte carry; + + sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (r & 0x80) + sram[SREG] |= SREG_N; + carry = (a & b) | (a & ~r) | (b & ~r); + if (carry & 0x08) + sram[SREG] |= SREG_H; + if (carry & 0x80) + sram[SREG] |= SREG_C; + if (((a & b & ~r) | (~a & ~b & r)) & 0x80) + sram[SREG] |= SREG_V; + if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) + sram[SREG] |= SREG_S; + if (r == 0) + sram[SREG] |= SREG_Z; +} + +static void update_flags_sub (byte r, byte a, byte b) +{ + byte carry; + + sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (r & 0x80) + sram[SREG] |= SREG_N; + carry = (~a & b) | (b & r) | (r & ~a); + if (carry & 0x08) + sram[SREG] |= SREG_H; + if (carry & 0x80) + sram[SREG] |= SREG_C; + if (((a & ~b & ~r) | (~a & b & r)) & 0x80) + sram[SREG] |= SREG_V; + if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V)) + sram[SREG] |= SREG_S; + /* Note: Z is not set. */ +} + +static enum avr_opcode +decode (unsigned int pc) +{ + word op1 = flash[pc].op; + + switch ((op1 >> 12) & 0x0f) + { + case 0x0: + switch ((op1 >> 10) & 0x3) + { + case 0x0: + switch ((op1 >> 8) & 0x3) + { + case 0x0: + if (op1 == 0) + return OP_nop; + break; + case 0x1: + return OP_movw; + case 0x2: + return OP_muls; + case 0x3: + if (op1 & 0x80) + { + if (op1 & 0x08) + return OP_fmulsu; + else + return OP_fmuls; + } + else + { + if (op1 & 0x08) + return OP_fmul; + else + return OP_mulsu; + } + } + break; + case 0x1: + return OP_cpc; + case 0x2: + flash[pc].r = SREG_C; + return OP_sbc; + case 0x3: + flash[pc].r = 0; + return OP_add; + } + break; + case 0x1: + switch ((op1 >> 10) & 0x3) + { + case 0x0: + return OP_cpse; + case 0x1: + return OP_cp; + case 0x2: + flash[pc].r = 0; + return OP_sub; + case 0x3: + flash[pc].r = SREG_C; + return OP_adc; + } + break; + case 0x2: + switch ((op1 >> 10) & 0x3) + { + case 0x0: + return OP_and; + case 0x1: + return OP_eor; + case 0x2: + return OP_or; + case 0x3: + return OP_mov; + } + break; + case 0x3: + return OP_cpi; + case 0x4: + return OP_sbci; + case 0x5: + return OP_subi; + case 0x6: + return OP_ori; + case 0x7: + return OP_andi; + case 0x8: + case 0xa: + if (op1 & 0x0200) + { + if (op1 & 0x0008) + { + flash[pc].r = get_q (op1); + return OP_std_Y; + } + else + { + flash[pc].r = get_q (op1); + return OP_std_Z; + } + } + else + { + if (op1 & 0x0008) + { + flash[pc].r = get_q (op1); + return OP_ldd_Y; + } + else + { + flash[pc].r = get_q (op1); + return OP_ldd_Z; + } + } + break; + case 0x9: /* 9xxx */ + switch ((op1 >> 8) & 0xf) + { + case 0x0: + case 0x1: + switch ((op1 >> 0) & 0xf) + { + case 0x0: + return OP_lds; + case 0x1: + return OP_ld_Z_inc; + case 0x2: + return OP_ld_dec_Z; + case 0x4: + return OP_lpm_Z; + case 0x5: + return OP_lpm_inc_Z; + case 0x6: + return OP_elpm_Z; + case 0x7: + return OP_elpm_inc_Z; + case 0x9: + return OP_ld_Y_inc; + case 0xa: + return OP_ld_dec_Y; + case 0xc: + return OP_ld_X; + case 0xd: + return OP_ld_X_inc; + case 0xe: + return OP_ld_dec_X; + case 0xf: + return OP_pop; + } + break; + case 0x2: + case 0x3: + switch ((op1 >> 0) & 0xf) + { + case 0x0: + return OP_sts; + case 0x1: + return OP_st_Z_inc; + case 0x2: + return OP_st_dec_Z; + case 0x9: + return OP_st_Y_inc; + case 0xa: + return OP_st_dec_Y; + case 0xc: + return OP_st_X; + case 0xd: + return OP_st_X_inc; + case 0xe: + return OP_st_dec_X; + case 0xf: + return OP_push; + } + break; + case 0x4: + case 0x5: + switch (op1 & 0xf) + { + case 0x0: + return OP_com; + case 0x1: + return OP_neg; + case 0x2: + return OP_swap; + case 0x3: + return OP_inc; + case 0x5: + flash[pc].r = 0x80; + return OP_asr; + case 0x6: + flash[pc].r = 0; + return OP_lsr; + case 0x7: + return OP_ror; + case 0x8: /* 9[45]x8 */ + switch ((op1 >> 4) & 0x1f) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + return OP_bset; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x0e: + case 0x0f: + return OP_bclr; + case 0x10: + return OP_ret; + case 0x11: + return OP_reti; + case 0x19: + return OP_break; + case 0x1c: + return OP_lpm; + case 0x1d: + return OP_elpm; + default: + break; + } + break; + case 0x9: /* 9[45]x9 */ + switch ((op1 >> 4) & 0x1f) + { + case 0x00: + return OP_ijmp; + case 0x01: + return OP_eijmp; + case 0x10: + return OP_icall; + case 0x11: + return OP_eicall; + default: + break; + } + break; + case 0xa: + return OP_dec; + case 0xc: + case 0xd: + flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); + return OP_jmp; + case 0xe: + case 0xf: + flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1); + return OP_call; + } + break; + case 0x6: + return OP_adiw; + case 0x7: + return OP_sbiw; + case 0x8: + return OP_cbi; + case 0x9: + return OP_sbic; + case 0xa: + return OP_sbi; + case 0xb: + return OP_sbis; + case 0xc: + case 0xd: + case 0xe: + case 0xf: + return OP_mul; + } + break; + case 0xb: + flash[pc].r = get_A (op1); + if (((op1 >> 11) & 1) == 0) + return OP_in; + else + return OP_out; + case 0xc: + return OP_rjmp; + case 0xd: + return OP_rcall; + case 0xe: + return OP_ldi; + case 0xf: + switch ((op1 >> 9) & 7) + { + case 0: + case 1: + flash[pc].r = 1 << (op1 & 7); + return OP_brbs; + case 2: + case 3: + flash[pc].r = 1 << (op1 & 7); + return OP_brbc; + case 4: + if ((op1 & 8) == 0) + { + flash[pc].r = 1 << (op1 & 7); + return OP_bld; + } + break; + case 5: + if ((op1 & 8) == 0) + { + flash[pc].r = 1 << (op1 & 7); + return OP_bst; + } + break; + case 6: + if ((op1 & 8) == 0) + { + flash[pc].r = 1 << (op1 & 7); + return OP_sbrc; + } + break; + case 7: + if ((op1 & 8) == 0) + { + flash[pc].r = 1 << (op1 & 7); + return OP_sbrs; + } + break; + } + } + sim_cb_eprintf (callback, + "Unhandled instruction at pc=0x%x, op=%04x\n", pc * 2, op1); + return OP_bad; +} + +/* Disassemble an instruction. */ + +static int +disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *info) +{ + int res; + + res = sim_read (NULL, memaddr, myaddr, length); + if (res != length) + return -1; + return 0; +} + +/* Memory error support for an opcodes disassembler. */ + +static void +disasm_perror_memory (int status, bfd_vma memaddr, + struct disassemble_info *info) +{ + if (status != -1) + /* Can't happen. */ + info->fprintf_func (info->stream, "Unknown error %d.", status); + else + /* Actually, address between memaddr and memaddr + len was + out of bounds. */ + info->fprintf_func (info->stream, + "Address 0x%x is out of bounds.", + (int) memaddr); +} + +static void +disassemble_insn (SIM_DESC sd, SIM_ADDR pc) +{ + struct disassemble_info disasm_info; + int len; + int i; + + INIT_DISASSEMBLE_INFO (disasm_info, callback, sim_cb_eprintf); + + disasm_info.arch = bfd_get_arch (cur_bfd); + disasm_info.mach = bfd_get_mach (cur_bfd); + disasm_info.endian = BFD_ENDIAN_LITTLE; + disasm_info.read_memory_func = disasm_read_memory; + disasm_info.memory_error_func = disasm_perror_memory; + + len = print_insn_avr (pc << 1, &disasm_info); + len = len / 2; + for (i = 0; i < len; i++) + sim_cb_eprintf (callback, " %04x", flash[pc + i].op); +} + +static void +do_call (unsigned int npc) +{ + unsigned int sp = read_word (REG_SP); + + /* Big endian! */ + sram[sp--] = pc; + sram[sp--] = pc >> 8; + if (avr_pc22) + { + sram[sp--] = pc >> 16; + cycles++; + } + write_word (REG_SP, sp); + pc = npc & PC_MASK; + cycles += 3; +} + +static int +get_insn_length (unsigned int p) +{ + if (flash[p].code == OP_unknown) + flash[p].code = decode(p); + if (flash[p].code >= OP_2words) + return 2; + else + return 1; +} + +static unsigned int +get_z (void) +{ + return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO]; +} + +static unsigned char +get_lpm (unsigned int addr) +{ + word w; + + w = flash[(addr >> 1) & PC_MASK].op; + if (addr & 1) + w >>= 8; + return w; +} + +static void +gen_mul (unsigned int res) +{ + write_word (0, res); + sram[SREG] &= ~(SREG_Z | SREG_C); + if (res == 0) + sram[SREG] |= SREG_Z; + if (res & 0x8000) + sram[SREG] |= SREG_C; + cycles++; +} + +void +sim_resume (SIM_DESC sd, int step, int signal) +{ + unsigned int ipc; + + if (step) + { + cpu_exception = sim_stopped; + cpu_signal = TARGET_SIGNAL_TRAP; + } + else + cpu_exception = sim_running; + + do + { + int code; + word op; + byte res; + byte r, d, vd; + + again: + code = flash[pc].code; + op = flash[pc].op; + + + if ((tracing || lock_step) && code != OP_unknown) + { + if (verbose > 0) { + int flags; + int i; + + sim_cb_eprintf (callback, "R00-07:"); + for (i = 0; i < 8; i++) + sim_cb_eprintf (callback, " %02x", sram[i]); + sim_cb_eprintf (callback, " -"); + for (i = 8; i < 16; i++) + sim_cb_eprintf (callback, " %02x", sram[i]); + sim_cb_eprintf (callback, " SP: %02x %02x", + sram[REG_SP + 1], sram[REG_SP]); + sim_cb_eprintf (callback, "\n"); + sim_cb_eprintf (callback, "R16-31:"); + for (i = 16; i < 24; i++) + sim_cb_eprintf (callback, " %02x", sram[i]); + sim_cb_eprintf (callback, " -"); + for (i = 24; i < 32; i++) + sim_cb_eprintf (callback, " %02x", sram[i]); + sim_cb_eprintf (callback, " "); + flags = sram[SREG]; + for (i = 0; i < 8; i++) + sim_cb_eprintf (callback, "%c", + flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-'); + sim_cb_eprintf (callback, "\n"); + } + + if (lock_step && !tracing) + sim_cb_eprintf (callback, "%06x: %04x\n", 2 * pc, flash[pc].op); + else + { + sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n", + 2 * pc, flash[pc].op, code, flash[pc].r); + disassemble_insn (sd, pc); + sim_cb_eprintf (callback, "\n"); + } + } + + ipc = pc; + pc = (pc + 1) & PC_MASK; + cycles++; + + switch (code) + { + case OP_unknown: + flash[ipc].code = decode(ipc); + pc = ipc; + cycles--; + goto again; + break; + + case OP_nop: + break; + + case OP_jmp: + /* 2 words instruction, but we don't care about the pc. */ + pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK; + cycles += 2; + break; + + case OP_eijmp: + pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK; + cycles += 2; + break; + + case OP_ijmp: + pc = read_word (REGZ) & PC_MASK; + cycles += 1; + break; + + case OP_call: + /* 2 words instruction. */ + pc++; + do_call ((flash[ipc].r << 16) | flash[ipc + 1].op); + break; + + case OP_eicall: + do_call ((sram[EIND] << 16) | read_word (REGZ)); + break; + + case OP_icall: + do_call (read_word (REGZ)); + break; + + case OP_rcall: + do_call (pc + sign_ext (op & 0xfff, 12)); + break; + + case OP_reti: + sram[SREG] |= SREG_I; + /* Fall through */ + case OP_ret: + { + unsigned int sp = read_word (REG_SP); + if (avr_pc22) + { + pc = sram[++sp] << 16; + cycles++; + } + else + pc = 0; + pc |= sram[++sp] << 8; + pc |= sram[++sp]; + write_word (REG_SP, sp); + } + cycles += 3; + break; + + case OP_break: + /* Stop on this address. */ + cpu_exception = sim_stopped; + cpu_signal = TARGET_SIGNAL_TRAP; + pc = ipc; + break; + + case OP_bld: + d = get_d (op); + r = flash[ipc].r; + if (sram[SREG] & SREG_T) + sram[d] |= r; + else + sram[d] &= ~r; + break; + + case OP_bst: + if (sram[get_d (op)] & flash[ipc].r) + sram[SREG] |= SREG_T; + else + sram[SREG] &= ~SREG_T; + break; + + case OP_sbrc: + case OP_sbrs: + if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0)) + { + int l = get_insn_length(pc); + pc += l; + cycles += l; + } + break; + + case OP_push: + { + unsigned int sp = read_word (REG_SP); + sram[sp--] = sram[get_d (op)]; + write_word (REG_SP, sp); + } + cycles++; + break; + + case OP_pop: + { + unsigned int sp = read_word (REG_SP); + sram[get_d (op)] = sram[++sp]; + write_word (REG_SP, sp); + } + cycles++; + break; + + case OP_bclr: + sram[SREG] &= ~(1 << ((op >> 4) & 0x7)); + break; + + case OP_bset: + sram[SREG] |= 1 << ((op >> 4) & 0x7); + break; + + case OP_rjmp: + pc = (pc + sign_ext (op & 0xfff, 12)) & PC_MASK; + cycles++; + break; + + case OP_eor: + d = get_d (op); + res = sram[d] ^ sram[get_r (op)]; + sram[d] = res; + update_flags_logic (res); + break; + + case OP_and: + d = get_d (op); + res = sram[d] & sram[get_r (op)]; + sram[d] = res; + update_flags_logic (res); + break; + + case OP_andi: + d = get_d16 (op); + res = sram[d] & get_K (op); + sram[d] = res; + update_flags_logic (res); + break; + + case OP_or: + d = get_d (op); + res = sram[d] | sram[get_r (op)]; + sram[d] = res; + update_flags_logic (res); + break; + + case OP_ori: + d = get_d16 (op); + res = sram[d] | get_K (op); + sram[d] = res; + update_flags_logic (res); + break; + + case OP_com: + d = get_d (op); + res = ~sram[d]; + sram[d] = res; + update_flags_logic (res); + sram[SREG] |= SREG_C; + break; + + case OP_swap: + d = get_d (op); + vd = sram[d]; + sram[d] = (vd >> 4) | (vd << 4); + break; + + case OP_neg: + d = get_d (op); + vd = sram[d]; + res = -vd; + sram[d] = res; + sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (res == 0) + sram[SREG] |= SREG_Z; + else + sram[SREG] |= SREG_C; + if (res == 0x80) + sram[SREG] |= SREG_V | SREG_N; + else if (res & 0x80) + sram[SREG] |= SREG_N | SREG_S; + if ((res | vd) & 0x08) + sram[SREG] |= SREG_H; + break; + + case OP_inc: + d = get_d (op); + res = sram[d] + 1; + sram[d] = res; + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); + if (res == 0x80) + sram[SREG] |= SREG_V | SREG_N; + else if (res & 0x80) + sram[SREG] |= SREG_N | SREG_S; + else if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_dec: + d = get_d (op); + res = sram[d] - 1; + sram[d] = res; + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z); + if (res == 0x7f) + sram[SREG] |= SREG_V | SREG_S; + else if (res & 0x80) + sram[SREG] |= SREG_N | SREG_S; + else if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_lsr: + case OP_asr: + d = get_d (op); + vd = sram[d]; + res = (vd >> 1) | (vd & flash[ipc].r); + sram[d] = res; + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (vd & 1) + sram[SREG] |= SREG_C | SREG_S; + if (res & 0x80) + sram[SREG] |= SREG_N; + if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) + sram[SREG] |= SREG_V; + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_ror: + d = get_d (op); + vd = sram[d]; + res = vd >> 1 | (sram[SREG] << 7); + sram[d] = res; + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (vd & 1) + sram[SREG] |= SREG_C | SREG_S; + if (res & 0x80) + sram[SREG] |= SREG_N; + if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C)) + sram[SREG] |= SREG_V; + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_mul: + gen_mul ((word)sram[get_r (op)] * (word)sram[get_d (op)]); + break; + + case OP_muls: + gen_mul((sword)(sbyte)sram[get_r16 (op)] + * (sword)(sbyte)sram[get_d16 (op)]); + break; + + case OP_mulsu: + gen_mul ((sword)(word)sram[get_r16_23 (op)] + * (sword)(sbyte)sram[get_d16_23 (op)]); + break; + + case OP_fmul: + gen_mul(((word)sram[get_r16_23 (op)] + * (word)sram[get_d16_23 (op)]) << 1); + break; + + case OP_fmuls: + gen_mul(((sword)(sbyte)sram[get_r16_23 (op)] + * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); + break; + + case OP_fmulsu: + gen_mul(((sword)(word)sram[get_r16_23 (op)] + * (sword)(sbyte)sram[get_d16_23 (op)]) << 1); + break; + + case OP_adc: + case OP_add: + r = sram[get_r (op)]; + d = get_d (op); + vd = sram[d]; + res = r + vd + (sram[SREG] & flash[ipc].r); + sram[d] = res; + update_flags_add (res, vd, r); + break; + + case OP_sub: + d = get_d (op); + vd = sram[d]; + r = sram[get_r (op)]; + res = vd - r; + sram[d] = res; + update_flags_sub (res, vd, r); + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_sbc: + { + byte old = sram[SREG]; + d = get_d (op); + vd = sram[d]; + r = sram[get_r (op)]; + res = vd - r - (old & SREG_C); + sram[d] = res; + update_flags_sub (res, vd, r); + if (res == 0 && (old & SREG_Z)) + sram[SREG] |= SREG_Z; + } + break; + + case OP_subi: + d = get_d16 (op); + vd = sram[d]; + r = get_K (op); + res = vd - r; + sram[d] = res; + update_flags_sub (res, vd, r); + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_sbci: + { + byte old = sram[SREG]; + + d = get_d16 (op); + vd = sram[d]; + r = get_K (op); + res = vd - r - (old & SREG_C); + sram[d] = res; + update_flags_sub (res, vd, r); + if (res == 0 && (old & SREG_Z)) + sram[SREG] |= SREG_Z; + } + break; + + case OP_mov: + sram[get_d (op)] = sram[get_r (op)]; + break; + + case OP_movw: + d = (op & 0xf0) >> 3; + r = (op & 0x0f) << 1; + sram[d] = sram[r]; + sram[d + 1] = sram[r + 1]; + break; + + case OP_out: + d = get_A (op) + 0x20; + res = sram[get_d (op)]; + sram[d] = res; + if (d == STDIO_PORT) + putchar (res); + else if (d == EXIT_PORT) + { + cpu_exception = sim_exited; + cpu_signal = 0; + return; + } + else if (d == ABORT_PORT) + { + cpu_exception = sim_exited; + cpu_signal = 1; + return; + } + break; + + case OP_in: + d = get_A (op) + 0x20; + sram[get_d (op)] = sram[d]; + break; + + case OP_cbi: + d = get_biA (op) + 0x20; + sram[d] &= ~(1 << get_b(op)); + break; + + case OP_sbi: + d = get_biA (op) + 0x20; + sram[d] |= 1 << get_b(op); + break; + + case OP_sbic: + if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op))) + { + int l = get_insn_length(pc); + pc += l; + cycles += l; + } + break; + + case OP_sbis: + if (sram[get_biA (op) + 0x20] & 1 << get_b(op)) + { + int l = get_insn_length(pc); + pc += l; + cycles += l; + } + break; + + case OP_ldi: + res = get_K (op); + d = get_d16 (op); + sram[d] = res; + break; + + case OP_lds: + sram[get_d (op)] = sram[flash[pc].op]; + pc++; + cycles++; + break; + + case OP_sts: + sram[flash[pc].op] = sram[get_d (op)]; + pc++; + cycles++; + break; + + case OP_cpse: + if (sram[get_r (op)] == sram[get_d (op)]) + { + int l = get_insn_length(pc); + pc += l; + cycles += l; + } + break; + + case OP_cp: + r = sram[get_r (op)]; + d = sram[get_d (op)]; + res = d - r; + update_flags_sub (res, d, r); + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_cpi: + r = get_K (op); + d = sram[get_d16 (op)]; + res = d - r; + update_flags_sub (res, d, r); + if (res == 0) + sram[SREG] |= SREG_Z; + break; + + case OP_cpc: + { + byte old = sram[SREG]; + d = sram[get_d (op)]; + r = sram[get_r (op)]; + res = d - r - (old & SREG_C); + update_flags_sub (res, d, r); + if (res == 0 && (old & SREG_Z)) + sram[SREG] |= SREG_Z; + } + break; + + case OP_brbc: + if (!(sram[SREG] & flash[ipc].r)) + { + pc = (pc + get_k (op)) & PC_MASK; + cycles++; + } + break; + + case OP_brbs: + if (sram[SREG] & flash[ipc].r) + { + pc = (pc + get_k (op)) & PC_MASK; + cycles++; + } + break; + + case OP_lpm: + sram[0] = get_lpm (read_word (REGZ)); + cycles += 2; + break; + + case OP_lpm_Z: + sram[get_d (op)] = get_lpm (read_word (REGZ)); + cycles += 2; + break; + + case OP_lpm_inc_Z: + sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ)); + cycles += 2; + break; + + case OP_elpm: + sram[0] = get_lpm (get_z ()); + cycles += 2; + break; + + case OP_elpm_Z: + sram[get_d (op)] = get_lpm (get_z ()); + cycles += 2; + break; + + case OP_elpm_inc_Z: + { + unsigned int z = get_z (); + + sram[get_d (op)] = get_lpm (z); + z++; + sram[REGZ_LO] = z; + sram[REGZ_HI] = z >> 8; + sram[RAMPZ] = z >> 16; + } + cycles += 2; + break; + + case OP_ld_Z_inc: + sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK]; + cycles++; + break; + + case OP_ld_dec_Z: + sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK]; + cycles++; + break; + + case OP_ld_X_inc: + sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK]; + cycles++; + break; + + case OP_ld_dec_X: + sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK]; + cycles++; + break; + + case OP_ld_Y_inc: + sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK]; + cycles++; + break; + + case OP_ld_dec_Y: + sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK]; + cycles++; + break; + + case OP_st_X: + sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_X_inc: + sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_dec_X: + sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_Z_inc: + sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_dec_Z: + sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_Y_inc: + sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_st_dec_Y: + sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)]; + cycles++; + break; + + case OP_std_Y: + sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)]; + cycles++; + break; + + case OP_std_Z: + sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)]; + cycles++; + break; + + case OP_ldd_Z: + sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r]; + cycles++; + break; + + case OP_ldd_Y: + sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r]; + cycles++; + break; + + case OP_ld_X: + sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK]; + cycles++; + break; + + case OP_sbiw: + { + word wk = get_k6 (op); + word wres; + word wr; + + d = get_d24 (op); + wr = read_word (d); + wres = wr - wk; + + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (wres == 0) + sram[SREG] |= SREG_Z; + if (wres & 0x8000) + sram[SREG] |= SREG_N; + if (wres & ~wr & 0x8000) + sram[SREG] |= SREG_C; + if (~wres & wr & 0x8000) + sram[SREG] |= SREG_V; + if (((~wres & wr) ^ wres) & 0x8000) + sram[SREG] |= SREG_S; + write_word (d, wres); + } + cycles++; + break; + + case OP_adiw: + { + word wk = get_k6 (op); + word wres; + word wr; + + d = get_d24 (op); + wr = read_word (d); + wres = wr + wk; + + sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C); + if (wres == 0) + sram[SREG] |= SREG_Z; + if (wres & 0x8000) + sram[SREG] |= SREG_N; + if (~wres & wr & 0x8000) + sram[SREG] |= SREG_C; + if (wres & ~wr & 0x8000) + sram[SREG] |= SREG_V; + if (((wres & ~wr) ^ wres) & 0x8000) + sram[SREG] |= SREG_S; + write_word (d, wres); + } + cycles++; + break; + + case OP_bad: + sim_cb_eprintf (callback, "Bad instruction at pc=0x%x\n", ipc * 2); + return; + + default: + sim_cb_eprintf (callback, + "Unhandled instruction at pc=0x%x, code=%d\n", + 2 * ipc, code); + return; + } + } + while (cpu_exception == sim_running); +} + + +int +sim_trace (SIM_DESC sd) +{ + tracing = 1; + + sim_resume (sd, 0, 0); + + tracing = 0; + + return 1; +} + +int +sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size) +{ + int osize = size; + + if (addr >= 0 && addr < SRAM_VADDR) + { + while (size > 0 && addr < (MAX_AVR_FLASH << 1)) + { + word val = flash[addr >> 1].op; + + if (addr & 1) + val = (val & 0xff) | (buffer[0] << 8); + else + val = (val & 0xff00) | buffer[0]; + + flash[addr >> 1].op = val; + flash[addr >> 1].code = OP_unknown; + addr++; + buffer++; + size--; + } + return osize - size; + } + else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) + { + addr -= SRAM_VADDR; + if (addr + size > MAX_AVR_SRAM) + size = MAX_AVR_SRAM - addr; + memcpy (sram + addr, buffer, size); + return size; + } + else + return 0; +} + +int +sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) +{ + int osize = size; + + if (addr >= 0 && addr < SRAM_VADDR) + { + while (size > 0 && addr < (MAX_AVR_FLASH << 1)) + { + word val = flash[addr >> 1].op; + + if (addr & 1) + val >>= 8; + + *buffer++ = val; + addr++; + size--; + } + return osize - size; + } + else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM) + { + addr -= SRAM_VADDR; + if (addr + size > MAX_AVR_SRAM) + size = MAX_AVR_SRAM - addr; + memcpy (buffer, sram + addr, size); + return size; + } + else + { + /* Avoid errors. */ + memset (buffer, 0, size); + return size; + } +} + +int +sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) +{ + if (rn < 32 && length == 1) + { + sram[rn] = *memory; + return 1; + } + if (rn == AVR_SREG_REGNUM && length == 1) + { + sram[SREG] = *memory; + return 1; + } + if (rn == AVR_SP_REGNUM && length == 2) + { + sram[REG_SP] = memory[0]; + sram[REG_SP + 1] = memory[1]; + return 2; + } + if (rn == AVR_PC_REGNUM && length == 4) + { + pc = (memory[0] >> 1) | (memory[1] << 7) + | (memory[2] << 15) | (memory[3] << 23); + pc &= PC_MASK; + return 4; + } + return 0; +} + +int +sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) +{ + if (rn < 32 && length == 1) + { + *memory = sram[rn]; + return 1; + } + if (rn == AVR_SREG_REGNUM && length == 1) + { + *memory = sram[SREG]; + return 1; + } + if (rn == AVR_SP_REGNUM && length == 2) + { + memory[0] = sram[REG_SP]; + memory[1] = sram[REG_SP + 1]; + return 2; + } + if (rn == AVR_PC_REGNUM && length == 4) + { + memory[0] = pc << 1; + memory[1] = pc >> 7; + memory[2] = pc >> 15; + memory[3] = pc >> 23; + return 4; + } + return 0; +} + +void +sim_stop_reason (SIM_DESC sd, enum sim_stop * reason, int *sigrc) +{ + *reason = cpu_exception; + *sigrc = cpu_signal; +} + +int +sim_stop (SIM_DESC sd) +{ + cpu_exception = sim_stopped; + cpu_signal = TARGET_SIGNAL_INT; + return 1; +} + +void +sim_info (SIM_DESC sd, int verbose) +{ + callback->printf_filtered + (callback, "\n\n# cycles %10u\n", cycles); +} + +SIM_DESC +sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv) +{ + myname = argv[0]; + callback = cb; + + cur_bfd = abfd; + + /* Fudge our descriptor for now. */ + return (SIM_DESC) 1; +} + +void +sim_close (SIM_DESC sd, int quitting) +{ + /* nothing to do */ +} + +SIM_RC +sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty) +{ + bfd *prog_bfd; + + /* Clear all the memory. */ + memset (sram, 0, sizeof (sram)); + memset (flash, 0, sizeof (flash)); + + prog_bfd = sim_load_file (sd, myname, callback, prog, abfd, + sim_kind == SIM_OPEN_DEBUG, + 0, sim_write); + if (prog_bfd == NULL) + return SIM_RC_FAIL; + + avr_pc22 = (bfd_get_mach (prog_bfd) >= bfd_mach_avr6); + + if (abfd != NULL) + cur_bfd = abfd; + + return SIM_RC_OK; +} + +SIM_RC +sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env) +{ + /* Set the initial register set. */ + pc = 0; + + return SIM_RC_OK; +} + +void +sim_kill (SIM_DESC sd) +{ + /* nothing to do */ +} + +void +sim_do_command (SIM_DESC sd, char *cmd) +{ + /* Nothing there yet; it's all an error. */ + + if (cmd == NULL) + return; + + if (strcmp (cmd, "verbose") == 0) + verbose = 2; + else if (strcmp (cmd, "trace") == 0) + tracing = 1; + else + sim_cb_eprintf (callback, + "Error: \"%s\" is not a valid avr simulator command.\n", + cmd); +} + +void +sim_set_callbacks (host_callback *ptr) +{ + callback = ptr; +} diff --git a/external/gpl3/gdb/dist/sim/bfin/ChangeLog b/external/gpl3/gdb/dist/sim/bfin/ChangeLog new file mode 100644 index 000000000000..d7629a90171a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/ChangeLog @@ -0,0 +1,222 @@ +2011-05-17 Mike Frysinger + + * dv-bfin_otp.c (bfin_otp_ports): Declare. + (bfin_otp_finish): Call set_hw_ports with bfin_otp_ports. + +2011-03-29 Mike Frysinger + + * configure: Regenerate after common/aclocal.m4 changes. + +2011-03-28 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Cast high 16bits of A0.W to bs16 + and add to casted low 16bits of A0.L and store in val0. Cast high + 16bits of A1.W to bs16 and add to casted low 16bits of A1.L and + store in val1. Delete bit checks of val0 and val1. + +2011-03-26 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Set result to 0x7FFFFFFF when + the result was 0x80000000 for RND12 subtraction. + +2011-03-26 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Set VS when V is set. + +2011-03-24 Mike Frysinger + + * dv-bfin_gpio.c (bfin_gpio_port_event): Call HW_TRACE at every + major code flow point. + * dv-bfin_sic.c (bfin_sic_forward_interrupts): Call HW_TRACE just + before calling hw_port_event on ourselves. + (bfin_sic_52x_port_event, bfin_sic_537_port_event, + bfin_sic_54x_port_event, bfin_sic_561_port_event): Call HW_TRACE + at the start of the function. + +2011-03-24 Mike Frysinger + + * dv-bfin_gpio.c (bfin_gpio_port_event): Split dir/inen bit checking. + Normalize "level" to 0/1 values. Shift "level" over by "my_port". + Invert port->both bit check. + +2011-03-24 Mike Frysinger + + * dv-bfin_gpio.c (bfin_gpio_io_write_buffer): Subtract 2 from the + valuep pointer for clear MMRs, 4 for set MMRs, and 6 for toggle MMRs. + +2011-03-23 Mike Frysinger + + * TODO: Document some known SIC issues. + +2011-03-23 Mike Frysinger + + * devices.h (dv_w1c): Fix typos in documentation of "bits" arg. + * dv-bfin_cec.c (bfin_cec_io_write_buffer): Pass 0xffee to dv_w1c_4. + * dv-bfin_emac.c (bfin_emac_io_write_buffer): Pass 0xe1 to dv_w1c_4 + for systat MMR and -1 to dv_w1c_4 for [rt]x_stky/mmc_[rt]irqs MMRs. + * dv-bfin_eppi.c (bfin_eppi_io_write_buffer): Pass 0x1ff to dv_w1c_2. + * dv-bfin_gpio.c (bfin_gpio_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_jtag.c (bfin_jtag_io_write_buffer): Invert bits to dv_w1c_4. + * dv-bfin_nfc.c (bfin_nfc_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_otp.c (bfin_otp_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_ppi.c (bfin_ppi_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_rtc.c (bfin_rtc_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_spi.c (bfin_spi_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_twi.c (bfin_twi_io_write_buffer): Invert bits to dv_w1c_2. + * dv-bfin_uart2.c (bfin_uart_io_write_buffer): Invert bits to dv_w1c_2. + +2011-03-23 Mike Frysinger + + * dv-bfin_uart.h (TFI, BI, FE, PE, OE): Define. + +2011-03-23 Mike Frysinger + + * dv-bfin_twi.h (LOSTARB): Rename from LOSTARG. + +2011-03-23 Robin Getz + + * bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended + value for the VIT_MAX insn, and mask off the result when done. + +2011-03-23 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false, + and set A0 to a0_lo when up_lo is false. + +2011-03-23 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Call saturate_s40_astat instead of + saturate_s40, and use the v parameter to update the AV bit. Set the + AC bit only when the final result is 0. + +2011-03-23 Mike Frysinger + + * dv-bfin_sic.c (ENC, DEC_PIN, DEC_SIC): Define. + (bfin_sic_50x_ports, bfin_sic_51x_ports, bfin_sic_52x_ports, + bfin_sic_533_ports, bfin_sic_537_ports, bfin_sic_538_ports, + bfin_sic_54x_ports, bfin_sic_561_ports, bfin_sic_59x_ports): + Encode ids with the ENC macro. + (bfin_sic_52x_port_event, bfin_sic_537_port_event, + bfin_sic_54x_port_event, bfin_sic_561_port_event): Set idx + from my_port with DEC_SIC, and set bit from my_port with DEC_PIN. + (bfin_sic_533_port_event): Delete. + (bfin_sic_finish): Call set_hw_port_event with + bfin_sic_537_port_event for BF533 and BF59x targets. + +2011-03-23 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for + BYTEOP1P, BYTEOP2P, and BYTEOP3P insns. + +2011-03-23 Mike Frysinger + + * machs.c (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, + bf533_dev, bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): + Change bfin_gpio addresses from f/g/h to 5/6/7. + (bfin_model_hw_tree_init): Add the bfin_gpio address base to 'a'. + +2011-03-17 Mike Frysinger + + * configure.ac (AC_CHECK_FUNCS): Check for kill and pread. + * configure: Regenerate. + * config.in: Regenerate. + * interp.c (bfin_syscall): Check for HAVE_{KILL,PREAD} before using + kill or pread. + +2011-03-15 Mike Frysinger + + * Makefile.in (dv-bfin_gpio.o): New target. + * configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio. + * configure: Regenerate. + * dv-bfin_gpio.c, dv-bfin_gpio.h: New files. + * machs.c: Include dv-bfin_gpio.h. + (bf50x_mem, bf51x_mem, bf52x_mem, bf531_mem, bf532_mem, bf533_mem, + bf534_mem, bf536_mem, bf537_mem, bf538_mem, bf561_mem, bf592_mem): + Delete GPIO memory stubs. + (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, bf533_dev, + bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): Add GPIO + peripheral devices. + (bfin_model_hw_tree_init): Hook up GPIO interrupts to SIC. + +2011-03-15 Mike Frysinger + + * bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h, bfroms/bf51x-0.1.h, + bfroms/bf51x-0.2.h, bfroms/bf526-0.0.h, bfroms/bf526-0.1.h, + bfroms/bf527-0.0.h, bfroms/bf527-0.1.h, bfroms/bf527-0.2.h, + bfroms/bf533-0.1.h, bfroms/bf533-0.2.h, bfroms/bf533-0.3.h, + bfroms/bf537-0.0.h, bfroms/bf537-0.1.h, bfroms/bf537-0.3.h, + bfroms/bf538-0.0.h, bfroms/bf54x-0.0.h, bfroms/bf54x-0.1.h, + bfroms/bf54x-0.2.h, bfroms/bf54x_l1-0.0.h, bfroms/bf54x_l1-0.1.h, + bfroms/bf54x_l1-0.2.h, bfroms/bf561-0.5.h, bfroms/bf59x-0.0.h, + bfroms/bf59x_l1-0.1.h, dv-bfin_cec.c, dv-bfin_ctimer.c, + dv-bfin_dma.c, dv-bfin_dmac.c, dv-bfin_ebiu_amc.c, + dv-bfin_ebiu_ddrc.c, dv-bfin_ebiu_sdc.c, dv-bfin_emac.c, + dv-bfin_eppi.c, dv-bfin_evt.c, dv-bfin_gptimer.c, dv-bfin_jtag.c, + dv-bfin_mmu.c, dv-bfin_nfc.c, dv-bfin_otp.c, dv-bfin_pll.c, + dv-bfin_ppi.c, dv-bfin_rtc.c, dv-bfin_sic.c, dv-bfin_spi.c, + dv-bfin_trace.c, dv-bfin_twi.c, dv-bfin_uart.c, dv-bfin_uart2.c, + dv-bfin_wdog.c, dv-bfin_wp.c, dv-eth_phy.c, gui.c, + linux-fixed-code.h, linux-targ-map.h, machs.c, Makefile.in: Fix style. + +2011-03-15 Robin Getz + + * bfin-sim.c (decode_dsp32alu_0): Set AZ based on val for 16bit adds + and subs. + +2011-03-15 Robin Getz + + * bfin-sim.c (decode_macfunc): Move acc STOREs behind op != 3 check. + +2011-03-15 Robin Getz + + * bfin-sim.c (decode_macfunc): New neg parameter. Set when the + high bit is set after extract_mult. + (decode_dsp32mac_0): Declare n_1 and n_0. Pass to the decode_macfunc + functions. Use these to update the AN bit. + +2011-03-15 Robin Getz + + * bfin-sim.c (decode_dsp32mult_0): Declare v_i0 and v_i1. Pass to + the extract_mult functions. Include these when updating the V, VS, + and V_COPY bits. + +2011-03-15 Robin Getz + + * bfin-sim.c (astat_names): New global bit array. + (decode_CC2stat_0): Delete local astat_name and astat_names. + (decode_psedodbg_assert_0): Move hardcoded offset into a variable. + Print out ASTAT bit values when checking an ASTAT register. + +2010-03-15 Robin Getz + + * bfin-sim.c (extract_mult): Handle M_IU. + +2011-03-05 Mike Frysinger + + * Makefile.in, TODO, aclocal.m4, bfin-sim.c, bfin-sim.h, + bfroms/all.h, bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h, + bfroms/bf51x-0.1.h, bfroms/bf51x-0.2.h, bfroms/bf526-0.0.h, + bfroms/bf526-0.1.h, bfroms/bf527-0.0.h, bfroms/bf527-0.1.h, + bfroms/bf527-0.2.h, bfroms/bf533-0.1.h, bfroms/bf533-0.2.h, + bfroms/bf533-0.3.h, bfroms/bf537-0.0.h, bfroms/bf537-0.1.h, + bfroms/bf537-0.3.h, bfroms/bf538-0.0.h, bfroms/bf54x-0.0.h, + bfroms/bf54x-0.1.h, bfroms/bf54x-0.2.h, bfroms/bf54x_l1-0.0.h, + bfroms/bf54x_l1-0.1.h, bfroms/bf54x_l1-0.2.h, bfroms/bf561-0.5.h, + bfroms/bf59x-0.0.h, bfroms/bf59x_l1-0.1.h, config.in, configure, + configure.ac, devices.c, devices.h, dv-bfin_cec.c, dv-bfin_cec.h, + dv-bfin_ctimer.c, dv-bfin_ctimer.h, dv-bfin_dma.c, dv-bfin_dma.h, + dv-bfin_dmac.c, dv-bfin_dmac.h, dv-bfin_ebiu_amc.c, dv-bfin_ebiu_amc.h, + dv-bfin_ebiu_ddrc.c, dv-bfin_ebiu_ddrc.h, dv-bfin_ebiu_sdc.c, + dv-bfin_ebiu_sdc.h, dv-bfin_emac.c, dv-bfin_emac.h, dv-bfin_eppi.c, + dv-bfin_eppi.h, dv-bfin_evt.c, dv-bfin_evt.h, dv-bfin_gptimer.c, + dv-bfin_gptimer.h, dv-bfin_jtag.c, dv-bfin_jtag.h, dv-bfin_mmu.c, + dv-bfin_mmu.h, dv-bfin_nfc.c, dv-bfin_nfc.h, dv-bfin_otp.c, + dv-bfin_otp.h, dv-bfin_pll.c, dv-bfin_pll.h, dv-bfin_ppi.c, + dv-bfin_ppi.h, dv-bfin_rtc.c, dv-bfin_rtc.h, dv-bfin_sic.c, + dv-bfin_sic.h, dv-bfin_spi.c, dv-bfin_spi.h, dv-bfin_trace.c, + dv-bfin_trace.h, dv-bfin_twi.c, dv-bfin_twi.h, dv-bfin_uart.c, + dv-bfin_uart.h, dv-bfin_uart2.c, dv-bfin_uart2.h, dv-bfin_wdog.c, + dv-bfin_wdog.h, dv-bfin_wp.c, dv-bfin_wp.h, dv-eth_phy.c, gui.c, + gui.h, insn_list.def, interp.c, linux-fixed-code.h, linux-fixed-code.s, + linux-targ-map.h, machs.c, machs.h, proc_list.def, sim-main.h, + tconfig.in: New Blackfin port. diff --git a/external/gpl3/gdb/dist/sim/bfin/Makefile.in b/external/gpl3/gdb/dist/sim/bfin/Makefile.in new file mode 100644 index 000000000000..2276c52ff929 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/Makefile.in @@ -0,0 +1,99 @@ +# Makefile template for Configure for the Blackfin simulator. +# Copyright (C) 2005-2011 Free Software Foundation, Inc. +# Written by Analog Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# This selects the bfin newlib/libgloss syscall definitions. +NL_TARGET = -DNL_TARGET_bfin + +## COMMON_PRE_CONFIG_FRAG + +# List of main object files for `run'. +SIM_RUN_OBJS = nrun.o + +SIM_OBJS = \ + $(SIM_NEW_COMMON_OBJS) \ + bfin-sim.o \ + devices.o \ + gui.o \ + interp.o \ + machs.o \ + sim-cpu.o \ + sim-engine.o \ + sim-hload.o \ + sim-hrw.o \ + sim-model.o \ + sim-reason.o \ + sim-reg.o \ + sim-resume.o \ + sim-stop.o \ + @BFIN_SIM_EXTRA_OBJS@ \ + $(SIM_EXTRA_OBJS) + +INCLUDE = bfin-sim.h + +SIM_EXTRA_CFLAGS = @SDL_CFLAGS@ +SIM_EXTRA_LIBS = @SDL_LIBS@ -lm + +## COMMON_POST_CONFIG_FRAG + +$(srcdir)/linux-fixed-code.h: $(srcdir)/linux-fixed-code.s Makefile.in + $(AS_FOR_TARGET) $< -o linux-fixed-code.o + ( set -e; \ + echo "/* DO NOT EDIT: Autogenerated from linux-fixed-code.s. */"; \ + echo "static const unsigned char bfin_linux_fixed_code[] ="; \ + echo "{"; \ + $(OBJDUMP_FOR_TARGET) -d -z linux-fixed-code.o > $@.dis; \ + sed -n $@.dis \ + -e 's:^[^ ]* :0x:' \ + -e '/^0x/{s: .*::;s: *$$:,:;s: :, 0x:g;p}'; \ + rm -f $@.dis; \ + echo "};" \ + ) > $@.tmp + rm -f linux-fixed-code.o + mv $@.tmp $@ + +interp.o: interp.c targ-vals.h linux-targ-map.h linux-fixed-code.h devices.h $(INCLUDE) +bfin-sim.o: bfin-sim.c $(INCLUDE) +gui.o: gui.c $(INCLUDE) +machs.o: machs.c $(INCLUDE) +dv-bfin_cec.o: dv-bfin_cec.c devices.h $(INCLUDE) +dv-bfin_ctimer.o: dv-bfin_ctimer.c devices.h $(INCLUDE) +dv-bfin_dma.o: dv-bfin_dma.c devices.h $(INCLUDE) +dv-bfin_dma_pmap.o: dv-bfin_dma_pmap.c devices.h $(INCLUDE) +dv-bfin_ebiu_amc.o: dv-bfin_ebiu_amc.c devices.h $(INCLUDE) +dv-bfin_ebiu_ddrc.o: dv-bfin_ebiu_ddrc.c devices.h $(INCLUDE) +dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE) +dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE) +dv-bfin_eppi.o: dv-bfin_eppi.c devices.h $(INCLUDE) +dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE) +dv-bfin_gpio.o: dv-bfin_gpio.c devices.h $(INCLUDE) +dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE) +dv-bfin_jtag.o: dv-bfin_jtag.c devices.h $(INCLUDE) +dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE) +dv-bfin_nfc.o: dv-bfin_nfc.c devices.h $(INCLUDE) +dv-bfin_otp.o: dv-bfin_otp.c devices.h $(INCLUDE) +dv-bfin_pll.o: dv-bfin_pll.c devices.h $(INCLUDE) +dv-bfin_ppi.o: dv-bfin_ppi.c devices.h $(INCLUDE) +dv-bfin_rtc.o: dv-bfin_rtc.c devices.h $(INCLUDE) +dv-bfin_sic.o: dv-bfin_sic.c devices.h $(INCLUDE) +dv-bfin_spi.o: dv-bfin_spi.c devices.h $(INCLUDE) +dv-bfin_trace.o: dv-bfin_trace.c devices.h $(INCLUDE) +dv-bfin_twi.o: dv-bfin_twi.c devices.h $(INCLUDE) +dv-bfin_uart.o: dv-bfin_uart.c devices.h $(INCLUDE) +dv-bfin_uart2.o: dv-bfin_uart2.c devices.h $(INCLUDE) +dv-bfin_wdog.o: dv-bfin_wdog.c devices.h $(INCLUDE) +dv-bfin_wp.o: dv-bfin_wp.c devices.h $(INCLUDE) +dv-eth_phy.o: devices.h $(INCLUDE) diff --git a/external/gpl3/gdb/dist/sim/bfin/TODO b/external/gpl3/gdb/dist/sim/bfin/TODO new file mode 100644 index 000000000000..b81d7706c171 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/TODO @@ -0,0 +1,50 @@ +need to review ASTAT write behavior + +how to model RETE and IVG0 bit in IPEND ... + +model the loop buffer ? this means no ifetches because they're cached. +see page 4-26 in Blackfin PRM under hardware loops. + +handle DSPID at 0xffe05000 + +CEC should handle multiple exceptions at same address. would need +exception processing to be delayed ? at least needs a stack for +the CEC to pop things off. + +R0 = [SP++]; gets traced as R0 = [P6++]; + +merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC + +fix single stepping over debug assert instructions in hardware + +exception in IVG5 causes double fault ? + +SIC int forwarding doesn't accurately reflect the hardware. what the sim +does is: + - device generates an interrupt + - int is sent to SIC + - SIC logs it into its ISR + - so long as SIC's IMASK allows it, bits set in ISR generate + an interrupt to the CEC + - no way to clear the SIC's ISR +the way the hardware works is that the device monitors the interrupt level and +the SIC's ISR bits are basically hardwired from each peripheral. so when the +device has its interrupt cleared, the bit in the SIC's ISR is automatically +cleared as well. +perhaps the only way to model this behavior in the sim is to have each device +set up an event callback that sends out a port event: a level of 0 means the +int has been ACKed and the SIC can clear its ISR while a level of 1 means the +int is being generated still. if the device is still generating an interrupt, +it can reschedule itself again. + +insns that cause an interrupt don't seem to be processed at the right time. +for example, setup a glue device that generates an interrupt upon right. +when the store insn is executed, the interrupt is taken right away instead +of being scheduled *after* the insn has finished executing. difference is +that RETI needs to point to the *next* insn and not the store insn. + +tests: + - check AN bits with Dreg subtraction + R0 = R1 - R2; + - check astat bits with vector add/sub +|+ + - check acc with VIT_MAX and similiar insns diff --git a/external/gpl3/gdb/dist/sim/bfin/aclocal.m4 b/external/gpl3/gdb/dist/sim/bfin/aclocal.m4 new file mode 100644 index 000000000000..cbe3b5592ddd --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/aclocal.m4 @@ -0,0 +1,171 @@ +# generated automatically by aclocal 1.11.1 -*- Autoconf -*- + +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, +# 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +# pkg.m4 - Macros to locate and utilise pkg-config. -*- Autoconf -*- +# serial 1 (pkg-config-0.24) +# +# Copyright © 2004 Scott James Remnant . +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# PKG_PROG_PKG_CONFIG([MIN-VERSION]) +# ---------------------------------- +AC_DEFUN([PKG_PROG_PKG_CONFIG], +[m4_pattern_forbid([^_?PKG_[A-Z_]+$]) +m4_pattern_allow([^PKG_CONFIG(_PATH)?$]) +AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility]) +AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path]) +AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path]) + +if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then + AC_PATH_TOOL([PKG_CONFIG], [pkg-config]) +fi +if test -n "$PKG_CONFIG"; then + _pkg_min_version=m4_default([$1], [0.9.0]) + AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version]) + if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then + AC_MSG_RESULT([yes]) + else + AC_MSG_RESULT([no]) + PKG_CONFIG="" + fi +fi[]dnl +])# PKG_PROG_PKG_CONFIG + +# PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND]) +# +# Check to see whether a particular set of modules exists. Similar +# to PKG_CHECK_MODULES(), but does not set variables or print errors. +# +# Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG]) +# only at the first occurence in configure.ac, so if the first place +# it's called might be skipped (such as if it is within an "if", you +# have to call PKG_CHECK_EXISTS manually +# -------------------------------------------------------------- +AC_DEFUN([PKG_CHECK_EXISTS], +[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl +if test -n "$PKG_CONFIG" && \ + AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then + m4_default([$2], [:]) +m4_ifvaln([$3], [else + $3])dnl +fi]) + +# _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES]) +# --------------------------------------------- +m4_define([_PKG_CONFIG], +[if test -n "$$1"; then + pkg_cv_[]$1="$$1" + elif test -n "$PKG_CONFIG"; then + PKG_CHECK_EXISTS([$3], + [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`], + [pkg_failed=yes]) + else + pkg_failed=untried +fi[]dnl +])# _PKG_CONFIG + +# _PKG_SHORT_ERRORS_SUPPORTED +# ----------------------------- +AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED], +[AC_REQUIRE([PKG_PROG_PKG_CONFIG]) +if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then + _pkg_short_errors_supported=yes +else + _pkg_short_errors_supported=no +fi[]dnl +])# _PKG_SHORT_ERRORS_SUPPORTED + + +# PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND], +# [ACTION-IF-NOT-FOUND]) +# +# +# Note that if there is a possibility the first call to +# PKG_CHECK_MODULES might not happen, you should be sure to include an +# explicit call to PKG_PROG_PKG_CONFIG in your configure.ac +# +# +# -------------------------------------------------------------- +AC_DEFUN([PKG_CHECK_MODULES], +[AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl +AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl +AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl + +pkg_failed=no +AC_MSG_CHECKING([for $1]) + +_PKG_CONFIG([$1][_CFLAGS], [cflags], [$2]) +_PKG_CONFIG([$1][_LIBS], [libs], [$2]) + +m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS +and $1[]_LIBS to avoid the need to call pkg-config. +See the pkg-config man page for more details.]) + +if test $pkg_failed = yes; then + AC_MSG_RESULT([no]) + _PKG_SHORT_ERRORS_SUPPORTED + if test $_pkg_short_errors_supported = yes; then + $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors "$2" 2>&1` + else + $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors "$2" 2>&1` + fi + # Put the nasty error message in config.log where it belongs + echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD + + m4_default([$4], [AC_MSG_ERROR( +[Package requirements ($2) were not met: + +$$1_PKG_ERRORS + +Consider adjusting the PKG_CONFIG_PATH environment variable if you +installed software in a non-standard prefix. + +_PKG_TEXT])[]dnl + ]) +elif test $pkg_failed = untried; then + AC_MSG_RESULT([no]) + m4_default([$4], [AC_MSG_FAILURE( +[The pkg-config script could not be found or is too old. Make sure it +is in your PATH or set the PKG_CONFIG environment variable to the full +path to pkg-config. + +_PKG_TEXT + +To get pkg-config, see .])dnl + ]) +else + $1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS + $1[]_LIBS=$pkg_cv_[]$1[]_LIBS + AC_MSG_RESULT([yes]) + $3 +fi[]dnl +])# PKG_CHECK_MODULES + diff --git a/external/gpl3/gdb/dist/sim/bfin/bfin-sim.c b/external/gpl3/gdb/dist/sim/bfin/bfin-sim.c new file mode 100644 index 000000000000..27112c6e99bd --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfin-sim.c @@ -0,0 +1,6165 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include +#include +#include +#include + +#include "opcode/bfin.h" +#include "sim-main.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_mmu.h" + +#define HOST_LONG_WORD_SIZE (sizeof (long) * 8) + +#define SIGNEXTEND(v, n) \ + (((bs32)(v) << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n))) + +static __attribute__ ((noreturn)) void +illegal_instruction (SIM_CPU *cpu) +{ + TRACE_INSN (cpu, "ILLEGAL INSTRUCTION"); + while (1) + cec_exception (cpu, VEC_UNDEF_I); +} + +static __attribute__ ((noreturn)) void +illegal_instruction_combination (SIM_CPU *cpu) +{ + TRACE_INSN (cpu, "ILLEGAL INSTRUCTION COMBINATION"); + while (1) + cec_exception (cpu, VEC_ILGAL_I); +} + +static __attribute__ ((noreturn)) void +unhandled_instruction (SIM_CPU *cpu, const char *insn) +{ + SIM_DESC sd = CPU_STATE (cpu); + bu16 iw0, iw1; + bu32 iw2; + + TRACE_EVENTS (cpu, "unhandled instruction"); + + iw0 = IFETCH (PCREG); + iw1 = IFETCH (PCREG + 2); + iw2 = ((bu32)iw0 << 16) | iw1; + + sim_io_eprintf (sd, "Unhandled instruction at 0x%08x (%s opcode 0x", PCREG, insn); + if ((iw0 & 0xc000) == 0xc000) + sim_io_eprintf (sd, "%08x", iw2); + else + sim_io_eprintf (sd, "%04x", iw0); + + sim_io_eprintf (sd, ") ... aborting\n"); + + illegal_instruction (cpu); +} + +static const char * const astat_names[] = +{ + [ 0] = "AZ", + [ 1] = "AN", + [ 2] = "AC0_COPY", + [ 3] = "V_COPY", + [ 4] = "ASTAT_4", + [ 5] = "CC", + [ 6] = "AQ", + [ 7] = "ASTAT_7", + [ 8] = "RND_MOD", + [ 9] = "ASTAT_9", + [10] = "ASTAT_10", + [11] = "ASTAT_11", + [12] = "AC0", + [13] = "AC1", + [14] = "ASTAT_14", + [15] = "ASTAT_15", + [16] = "AV0", + [17] = "AV0S", + [18] = "AV1", + [19] = "AV1S", + [20] = "ASTAT_20", + [21] = "ASTAT_21", + [22] = "ASTAT_22", + [23] = "ASTAT_23", + [24] = "V", + [25] = "VS", + [26] = "ASTAT_26", + [27] = "ASTAT_27", + [28] = "ASTAT_28", + [29] = "ASTAT_29", + [30] = "ASTAT_30", + [31] = "ASTAT_31", +}; + +typedef enum +{ + c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4, + c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, + c_imm5d, c_uimm5, c_imm6, c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, + c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10, c_pcrel12, c_imm16s4, + c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4, + c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e, +} const_forms_t; + +static const struct +{ + const char *name; + const int nbits; + const char reloc; + const char issigned; + const char pcrel; + const char scale; + const char offset; + const char negative; + const char positive; + const char decimal; + const char leading; + const char exact; +} constant_formats[] = +{ + { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0}, + { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0}, + { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, + { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0}, + { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}, + { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0}, + { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0}, + { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0}, + { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0}, + { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0}, + { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, + { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0}, + { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1}, +}; + +static const char * +fmtconst_str (const_forms_t cf, bs32 x, bu32 pc) +{ + static char buf[60]; + + if (constant_formats[cf].reloc) + { + bu32 ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + /*if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact) + { + outf->print_address_func (ea, outf); + return ""; + } + else*/ + { + sprintf (buf, "%#x", x); + return buf; + } + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else + x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x; + + if (constant_formats[cf].offset) + x += constant_formats[cf].offset; + + if (constant_formats[cf].scale) + x <<= constant_formats[cf].scale; + + if (constant_formats[cf].decimal) + { + if (constant_formats[cf].leading) + { + char ps[10]; + sprintf (ps, "%%%ii", constant_formats[cf].leading); + sprintf (buf, ps, x); + } + else + sprintf (buf, "%i", x); + } + else + { + if (constant_formats[cf].issigned && x < 0) + sprintf (buf, "-0x%x", abs (x)); + else + sprintf (buf, "0x%x", x); + } + + return buf; +} + +static bu32 +fmtconst_val (const_forms_t cf, bu32 x, bu32 pc) +{ + if (0 && constant_formats[cf].reloc) + { + bu32 ea = (((constant_formats[cf].pcrel + ? (bu32)SIGNEXTEND (x, constant_formats[cf].nbits) + : x) + constant_formats[cf].offset) + << constant_formats[cf].scale); + if (constant_formats[cf].pcrel) + ea += pc; + + return ea; + } + + /* Negative constants have an implied sign bit. */ + if (constant_formats[cf].negative) + { + int nb = constant_formats[cf].nbits + 1; + x = x | (1 << constant_formats[cf].nbits); + x = SIGNEXTEND (x, nb); + } + else if (constant_formats[cf].issigned) + x = SIGNEXTEND (x, constant_formats[cf].nbits); + + x += constant_formats[cf].offset; + x <<= constant_formats[cf].scale; + + return x; +} + +#define uimm16s4(x) fmtconst_val (c_uimm16s4, x, 0) +#define uimm16s4_str(x) fmtconst_str (c_uimm16s4, x, 0) +#define uimm16s4d(x) fmtconst_val (c_uimm16s4d, x, 0) +#define pcrel4(x) fmtconst_val (c_pcrel4, x, pc) +#define pcrel8(x) fmtconst_val (c_pcrel8, x, pc) +#define pcrel8s4(x) fmtconst_val (c_pcrel8s4, x, pc) +#define pcrel10(x) fmtconst_val (c_pcrel10, x, pc) +#define pcrel12(x) fmtconst_val (c_pcrel12, x, pc) +#define negimm5s4(x) fmtconst_val (c_negimm5s4, x, 0) +#define negimm5s4_str(x) fmtconst_str (c_negimm5s4, x, 0) +#define rimm16(x) fmtconst_val (c_rimm16, x, 0) +#define huimm16(x) fmtconst_val (c_huimm16, x, 0) +#define imm16(x) fmtconst_val (c_imm16, x, 0) +#define imm16_str(x) fmtconst_str (c_imm16, x, 0) +#define imm16d(x) fmtconst_val (c_imm16d, x, 0) +#define uimm2(x) fmtconst_val (c_uimm2, x, 0) +#define uimm3(x) fmtconst_val (c_uimm3, x, 0) +#define uimm3_str(x) fmtconst_str (c_uimm3, x, 0) +#define luimm16(x) fmtconst_val (c_luimm16, x, 0) +#define luimm16_str(x) fmtconst_str (c_luimm16, x, 0) +#define uimm4(x) fmtconst_val (c_uimm4, x, 0) +#define uimm4_str(x) fmtconst_str (c_uimm4, x, 0) +#define uimm5(x) fmtconst_val (c_uimm5, x, 0) +#define uimm5_str(x) fmtconst_str (c_uimm5, x, 0) +#define imm16s2(x) fmtconst_val (c_imm16s2, x, 0) +#define imm16s2_str(x) fmtconst_str (c_imm16s2, x, 0) +#define uimm8(x) fmtconst_val (c_uimm8, x, 0) +#define imm16s4(x) fmtconst_val (c_imm16s4, x, 0) +#define imm16s4_str(x) fmtconst_str (c_imm16s4, x, 0) +#define uimm4s2(x) fmtconst_val (c_uimm4s2, x, 0) +#define uimm4s2_str(x) fmtconst_str (c_uimm4s2, x, 0) +#define uimm4s4(x) fmtconst_val (c_uimm4s4, x, 0) +#define uimm4s4_str(x) fmtconst_str (c_uimm4s4, x, 0) +#define uimm4s4d(x) fmtconst_val (c_uimm4s4d, x, 0) +#define lppcrel10(x) fmtconst_val (c_lppcrel10, x, pc) +#define imm3(x) fmtconst_val (c_imm3, x, 0) +#define imm3_str(x) fmtconst_str (c_imm3, x, 0) +#define imm4(x) fmtconst_val (c_imm4, x, 0) +#define uimm8s4(x) fmtconst_val (c_uimm8s4, x, 0) +#define imm5(x) fmtconst_val (c_imm5, x, 0) +#define imm5d(x) fmtconst_val (c_imm5d, x, 0) +#define imm6(x) fmtconst_val (c_imm6, x, 0) +#define imm7(x) fmtconst_val (c_imm7, x, 0) +#define imm7_str(x) fmtconst_str (c_imm7, x, 0) +#define imm7d(x) fmtconst_val (c_imm7d, x, 0) +#define imm8(x) fmtconst_val (c_imm8, x, 0) +#define pcrel24(x) fmtconst_val (c_pcrel24, x, pc) +#define pcrel24_str(x) fmtconst_str (c_pcrel24, x, pc) +#define uimm16(x) fmtconst_val (c_uimm16, x, 0) +#define uimm32(x) fmtconst_val (c_uimm32, x, 0) +#define imm32(x) fmtconst_val (c_imm32, x, 0) +#define huimm32(x) fmtconst_val (c_huimm32, x, 0) +#define huimm32e(x) fmtconst_val (c_huimm32e, x, 0) + +/* Table C-4. Core Register Encoding Map. */ +const char * const greg_names[] = +{ + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", + "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", + "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3", + "A0.X", "A0.W", "A1.X", "A1.W", "", "", "ASTAT", "RETS", + "", "", "", "", "", "", "", "", + "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2", + "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", +}; +static const char * +get_allreg_name (int grp, int reg) +{ + return greg_names[(grp << 3) | reg]; +} +static const char * +get_preg_name (int reg) +{ + return get_allreg_name (1, reg); +} + +static bool +reg_is_reserved (int grp, int reg) +{ + return (grp == 4 && (reg == 4 || reg == 5)) || (grp == 5); +} + +static bu32 * +get_allreg (SIM_CPU *cpu, int grp, int reg) +{ + int fullreg = (grp << 3) | reg; + /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, + REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, + REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, + REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS, + , , , , , , , , + REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, + REG_CYCLES2, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, + REG_LASTREG */ + switch (fullreg >> 2) + { + case 0: case 1: return &DREG (reg); + case 2: case 3: return &PREG (reg); + case 4: return &IREG (reg & 3); + case 5: return &MREG (reg & 3); + case 6: return &BREG (reg & 3); + case 7: return &LREG (reg & 3); + default: + switch (fullreg) + { + case 32: return &AXREG (0); + case 33: return &AWREG (0); + case 34: return &AXREG (1); + case 35: return &AWREG (1); + case 39: return &RETSREG; + case 48: return &LCREG (0); + case 49: return <REG (0); + case 50: return &LBREG (0); + case 51: return &LCREG (1); + case 52: return <REG (1); + case 53: return &LBREG (1); + case 54: return &CYCLESREG; + case 55: return &CYCLES2REG; + case 56: return &USPREG; + case 57: return &SEQSTATREG; + case 58: return &SYSCFGREG; + case 59: return &RETIREG; + case 60: return &RETXREG; + case 61: return &RETNREG; + case 62: return &RETEREG; + case 63: return &EMUDAT_INREG; + } + illegal_instruction (cpu); + } +} + +static const char * +amod0 (int s0, int x0) +{ + static const char * const mod0[] = { + "", " (S)", " (CO)", " (SCO)", + }; + int i = s0 + (x0 << 1); + + if (i < ARRAY_SIZE (mod0)) + return mod0[i]; + else + return ""; +} + +static const char * +amod0amod2 (int s0, int x0, int aop0) +{ + static const char * const mod02[] = { + "", " (S)", " (CO)", " (SCO)", + "", "", "", "", + " (ASR)", " (S, ASR)", " (CO, ASR)", " (SCO, ASR)", + " (ASL)", " (S, ASL)", " (CO, ASL)", " (SCO, ASL)", + }; + int i = s0 + (x0 << 1) + (aop0 << 2); + + if (i < ARRAY_SIZE (mod02)) + return mod02[i]; + else + return ""; +} + +static const char * +amod1 (int s0, int x0) +{ + static const char * const mod1[] = { + " (NS)", " (S)", + }; + int i = s0 + (x0 << 1); + + if (i < ARRAY_SIZE (mod1)) + return mod1[i]; + else + return ""; +} + +static const char * +mac_optmode (int mmod, int MM) +{ + static const char * const omode[] = { + [(M_S2RND << 1) + 0] = " (S2RND)", + [(M_T << 1) + 0] = " (T)", + [(M_W32 << 1) + 0] = " (W32)", + [(M_FU << 1) + 0] = " (FU)", + [(M_TFU << 1) + 0] = " (TFU)", + [(M_IS << 1) + 0] = " (IS)", + [(M_ISS2 << 1) + 0] = " (ISS2)", + [(M_IH << 1) + 0] = " (IH)", + [(M_IU << 1) + 0] = " (IU)", + [(M_S2RND << 1) + 1] = " (M, S2RND)", + [(M_T << 1) + 1] = " (M, T)", + [(M_W32 << 1) + 1] = " (M, W32)", + [(M_FU << 1) + 1] = " (M, FU)", + [(M_TFU << 1) + 1] = " (M, TFU)", + [(M_IS << 1) + 1] = " (M, IS)", + [(M_ISS2 << 1) + 1] = " (M, ISS2)", + [(M_IH << 1) + 1] = " (M, IH)", + [(M_IU << 1) + 1] = " (M, IU)", + }; + int i = MM + (mmod << 1); + + if (i < ARRAY_SIZE (omode) && omode[i]) + return omode[i]; + else + return ""; +} + +static const char * +get_store_name (SIM_CPU *cpu, bu32 *p) +{ + if (p >= &DREG (0) && p <= &CYCLESREG) + return greg_names[p - &DREG (0)]; + else if (p == &AXREG (0)) + return greg_names[4 * 8 + 0]; + else if (p == &AWREG (0)) + return greg_names[4 * 8 + 1]; + else if (p == &AXREG (1)) + return greg_names[4 * 8 + 2]; + else if (p == &AWREG (1)) + return greg_names[4 * 8 + 3]; + else if (p == &ASTATREG (av0)) + return "ASTAT[av0]"; + else if (p == &ASTATREG (av0s)) + return "ASTAT[av0s]"; + else if (p == &ASTATREG (av1)) + return "ASTAT[av1]"; + else if (p == &ASTATREG (av1s)) + return "ASTAT[av1s]"; + else if (p == &ASTATREG (v)) + return "ASTAT[v]"; + else if (p == &ASTATREG (vs)) + return "ASTAT[vs]"; + else if (p == &ASTATREG (v_copy)) + return "ASTAT[v_copy]"; + else if (p == &ASTATREG (az)) + return "ASTAT[az]"; + else if (p == &ASTATREG (an)) + return "ASTAT[an]"; + else if (p == &ASTATREG (az)) + return "ASTAT[az]"; + else if (p == &ASTATREG (ac0)) + return "ASTAT[ac0]"; + else if (p == &ASTATREG (ac0_copy)) + return "ASTAT[ac0_copy]"; + else + { + /* Worry about this when we start to STORE() it. */ + sim_io_eprintf (CPU_STATE (cpu), "STORE(): unknown register\n"); + abort (); + } +} + +static void +queue_store (SIM_CPU *cpu, bu32 *addr, bu32 val) +{ + struct store *s = &BFIN_CPU_STATE.stores[BFIN_CPU_STATE.n_stores]; + s->addr = addr; + s->val = val; + TRACE_REGISTER (cpu, "queuing write %s = %#x", + get_store_name (cpu, addr), val); + ++BFIN_CPU_STATE.n_stores; +} +#define STORE(X, Y) \ + do { \ + if (BFIN_CPU_STATE.n_stores == 20) abort (); \ + queue_store (cpu, &(X), (Y)); \ + } while (0) + +static void +setflags_nz (SIM_CPU *cpu, bu32 val) +{ + SET_ASTATREG (az, val == 0); + SET_ASTATREG (an, val >> 31); +} + +static void +setflags_nz_2x16 (SIM_CPU *cpu, bu32 val) +{ + SET_ASTATREG (an, (bs16)val < 0 || (bs16)(val >> 16) < 0); + SET_ASTATREG (az, (bs16)val == 0 || (bs16)(val >> 16) == 0); +} + +static void +setflags_logical (SIM_CPU *cpu, bu32 val) +{ + setflags_nz (cpu, val); + SET_ASTATREG (ac0, 0); + SET_ASTATREG (v, 0); +} + +static bu32 +add_brev (bu32 addend1, bu32 addend2) +{ + bu32 mask, b, r; + int i, cy; + + mask = 0x80000000; + r = 0; + cy = 0; + + for (i = 31; i >= 0; --i) + { + b = ((addend1 & mask) >> i) + ((addend2 & mask) >> i); + b += cy; + cy = b >> 1; + b &= 1; + r |= b << i; + mask >>= 1; + } + + return r; +} + +/* This is a bit crazy, but we want to simulate the hardware behavior exactly + rather than worry about the circular buffers being used correctly. Which + isn't to say there isn't room for improvement here, just that we want to + be conservative. See also dagsub(). */ +static bu32 +dagadd (SIM_CPU *cpu, int dagno, bs32 M) +{ + bu64 i = IREG (dagno); + bu64 l = LREG (dagno); + bu64 b = BREG (dagno); + bu64 m = (bu32)M; + + bu64 LB, IM, IML; + bu32 im32, iml32, lb32, res; + bu64 msb, car; + + /* A naïve implementation that mostly works: + res = i + m; + if (l && res >= b + l) + res -= l; + STORE (IREG (dagno), res); + */ + + msb = (bu64)1 << 31; + car = (bu64)1 << 32; + + IM = i + m; + im32 = IM; + LB = l + b; + lb32 = LB; + + if (M < 0) + { + IML = i + m + l; + iml32 = IML; + if ((i & msb) || (IM & car)) + res = (im32 < b) ? iml32 : im32; + else + res = (im32 < b) ? im32 : iml32; + } + else + { + IML = i + m - l; + iml32 = IML; + if ((IM & car) == (LB & car)) + res = (im32 < lb32) ? im32 : iml32; + else + res = (im32 < lb32) ? iml32 : im32; + } + + STORE (IREG (dagno), res); + return res; +} + +/* See dagadd() notes above. */ +static bu32 +dagsub (SIM_CPU *cpu, int dagno, bs32 M) +{ + bu64 i = IREG (dagno); + bu64 l = LREG (dagno); + bu64 b = BREG (dagno); + bu64 m = (bu32)M; + + bu64 mbar = (bu32)(~m + 1); + bu64 LB, IM, IML; + bu32 b32, im32, iml32, lb32, res; + bu64 msb, car; + + /* A naïve implementation that mostly works: + res = i - m; + if (l && newi < b) + newi += l; + STORE (IREG (dagno), newi); + */ + + msb = (bu64)1 << 31; + car = (bu64)1 << 32; + + IM = i + mbar; + im32 = IM; + LB = l + b; + lb32 = LB; + + if (M < 0) + { + IML = i + mbar - l; + iml32 = IML; + if (!!((i & msb) && (IM & car)) == !!(LB & car)) + res = (im32 < lb32) ? im32 : iml32; + else + res = (im32 < lb32) ? iml32 : im32; + } + else + { + IML = i + mbar + l; + iml32 = IML; + b32 = b; + if (M == 0 || IM & car) + res = (im32 < b32) ? iml32 : im32; + else + res = (im32 < b32) ? im32 : iml32; + } + + STORE (IREG (dagno), res); + return res; +} + +static bu40 +ashiftrt (SIM_CPU *cpu, bu40 val, int cnt, int size) +{ + int real_cnt = cnt > size ? size : cnt; + bu40 sgn = ~(((val & 0xFFFFFFFFFFull) >> (size - 1)) - 1); + int sgncnt = size - real_cnt; + if (sgncnt > 16) + sgn <<= 16, sgncnt -= 16; + sgn <<= sgncnt; + if (real_cnt > 16) + val >>= 16, real_cnt -= 16; + val >>= real_cnt; + val |= sgn; + SET_ASTATREG (an, val >> (size - 1)); + SET_ASTATREG (az, val == 0); + /* XXX: Need to check ASTAT[v] behavior here. */ + SET_ASTATREG (v, 0); + return val; +} + +static bu64 +lshiftrt (SIM_CPU *cpu, bu64 val, int cnt, int size) +{ + int real_cnt = cnt > size ? size : cnt; + if (real_cnt > 16) + val >>= 16, real_cnt -= 16; + val >>= real_cnt; + switch (size) + { + case 16: + val &= 0xFFFF; + break; + case 32: + val &= 0xFFFFFFFF; + break; + case 40: + val &= 0xFFFFFFFFFFull; + break; + default: + illegal_instruction (cpu); + break; + } + SET_ASTATREG (an, val >> (size - 1)); + SET_ASTATREG (az, val == 0); + SET_ASTATREG (v, 0); + return val; +} + +static bu64 +lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate) +{ + int i, j, real_cnt = cnt > size ? size : cnt; + bu64 sgn = ~((val >> (size - 1)) - 1); + int mask_cnt = size - 1; + bu64 masked, new_val = val, tmp; + bu64 mask = ~0; + + mask <<= mask_cnt; + sgn <<= mask_cnt; + masked = val & mask; + + if (real_cnt > 16) + new_val <<= 16, real_cnt -= 16; + + new_val <<= real_cnt; + + masked = new_val & mask; + + /* If an operation would otherwise cause a positive value to overflow + and become negative, instead, saturation limits the result to the + maximum positive value for the size register being used. + + Conversely, if an operation would otherwise cause a negative value + to overflow and become positive, saturation limits the result to the + maximum negative value for the register size. + + However, it's a little more complex than looking at sign bits, we need + to see if we are shifting the sign information away... */ + tmp = val & ((~mask << 1) | 1); + + j = 0; + for (i = 1; i <= real_cnt && saturate; i++) + { + if ((tmp & ((bu64)1 << (size - 1))) != + (((val >> mask_cnt) & 0x1) << mask_cnt)) + j++; + tmp <<= 1; + } + saturate &= (!sgn && (new_val & (1 << mask_cnt))) + || (sgn && !(new_val & (1 << mask_cnt))); + + switch (size) + { + case 16: + if (j || (saturate && (new_val & mask))) + new_val = sgn == 0 ? 0x7fff : 0x8000, saturate = 1; + new_val &= 0xFFFF; + break; + case 32: + new_val &= 0xFFFFFFFF; + masked &= 0xFFFFFFFF; + if (j || (saturate && ((sgn != masked) || (!sgn && new_val == 0)))) + new_val = sgn == 0 ? 0x7fffffff : 0x80000000, saturate = 1; + break; + case 40: + new_val &= 0xFFFFFFFFFFull; + masked &= 0xFFFFFFFFFFull; + break; + default: + illegal_instruction (cpu); + break; + } + + SET_ASTATREG (an, new_val >> (size - 1)); + SET_ASTATREG (az, new_val == 0); + SET_ASTATREG (v, !!(saturate || j)); + if (saturate || j) + SET_ASTATREG (vs, 1); + return new_val; +} + +static bu32 +algn (bu32 l, bu32 h, bu32 aln) +{ + if (aln == 0) + return l; + else + return (l >> (8 * aln)) | (h << (32 - 8 * aln)); +} + +static bu32 +saturate_s16 (bu64 val, bu32 *overflow) +{ + if ((bs64)val < -0x8000ll) + { + if (overflow) + *overflow = 1; + return 0x8000; + } + if ((bs64)val > 0x7fff) + { + if (overflow) + *overflow = 1; + return 0x7fff; + } + return val & 0xffff; +} + +static bu40 +rot40 (bu40 val, int shift, bu32 *cc) +{ + const int nbits = 40; + bu40 ret; + + shift = CLAMP (shift, -nbits, nbits); + if (shift == 0) + return val; + + /* Reduce everything to rotate left. */ + if (shift < 0) + shift += nbits + 1; + + ret = shift == nbits ? 0 : val << shift; + ret |= shift == 1 ? 0 : val >> ((nbits + 1) - shift); + ret |= (bu40)*cc << (shift - 1); + *cc = (val >> (nbits - shift)) & 1; + + return ret; +} + +static bu32 +rot32 (bu32 val, int shift, bu32 *cc) +{ + const int nbits = 32; + bu32 ret; + + shift = CLAMP (shift, -nbits, nbits); + if (shift == 0) + return val; + + /* Reduce everything to rotate left. */ + if (shift < 0) + shift += nbits + 1; + + ret = shift == nbits ? 0 : val << shift; + ret |= shift == 1 ? 0 : val >> ((nbits + 1) - shift); + ret |= (bu32)*cc << (shift - 1); + *cc = (val >> (nbits - shift)) & 1; + + return ret; +} + +static bu32 +add32 (SIM_CPU *cpu, bu32 a, bu32 b, int carry, int sat) +{ + int flgs = (a >> 31) & 1; + int flgo = (b >> 31) & 1; + bu32 v = a + b; + int flgn = (v >> 31) & 1; + int overflow = (flgs ^ flgn) & (flgo ^ flgn); + + if (sat && overflow) + { + v = (bu32)1 << 31; + if (flgn) + v -= 1; + flgn = (v >> 31) & 1; + } + + SET_ASTATREG (an, flgn); + if (overflow) + SET_ASTATREG (vs, 1); + SET_ASTATREG (v, overflow); + ASTATREG (v_internal) |= overflow; + SET_ASTATREG (az, v == 0); + if (carry) + SET_ASTATREG (ac0, ~a < b); + + return v; +} + +static bu32 +sub32 (SIM_CPU *cpu, bu32 a, bu32 b, int carry, int sat, int parallel) +{ + int flgs = (a >> 31) & 1; + int flgo = (b >> 31) & 1; + bu32 v = a - b; + int flgn = (v >> 31) & 1; + int overflow = (flgs ^ flgo) & (flgn ^ flgs); + + if (sat && overflow) + { + v = (bu32)1 << 31; + if (flgn) + v -= 1; + flgn = (v >> 31) & 1; + } + + if (!parallel || flgn) + SET_ASTATREG (an, flgn); + if (overflow) + SET_ASTATREG (vs, 1); + if (!parallel || overflow) + SET_ASTATREG (v, overflow); + if (!parallel || overflow) + ASTATREG (v_internal) |= overflow; + if (!parallel || v == 0) + SET_ASTATREG (az, v == 0); + if (carry && (!parallel || b <= a)) + SET_ASTATREG (ac0, b <= a); + + return v; +} + +static bu32 +add16 (SIM_CPU *cpu, bu16 a, bu16 b, bu32 *carry, bu32 *overfl, + bu32 *zero, bu32 *neg, int sat, int scale) +{ + int flgs = (a >> 15) & 1; + int flgo = (b >> 15) & 1; + bs64 v = (bs16)a + (bs16)b; + int flgn = (v >> 15) & 1; + int overflow = (flgs ^ flgn) & (flgo ^ flgn); + + switch (scale) + { + case 0: + break; + case 2: + /* (ASR) */ + v = (a >> 1) + (a & 0x8000) + (b >> 1) + (b & 0x8000) + + (((a & 1) + (b & 1)) >> 1); + v |= -(v & 0x8000); + break; + case 3: + /* (ASL) */ + v = (v << 1); + break; + default: + illegal_instruction (cpu); + } + + flgn = (v >> 15) & 1; + overflow = (flgs ^ flgn) & (flgo ^ flgn); + + if (v > (bs64)0xffff) + overflow = 1; + + if (sat) + v = saturate_s16 (v, 0); + + if (neg) + *neg |= (v >> 15) & 1; + if (overfl) + *overfl |= overflow; + if (zero) + *zero |= (v & 0xFFFF) == 0; + if (carry) + *carry |= ((bu16)~a < (bu16)b); + + return v & 0xffff; +} + +static bu32 +sub16 (SIM_CPU *cpu, bu16 a, bu16 b, bu32 *carry, bu32 *overfl, + bu32 *zero, bu32 *neg, int sat, int scale) +{ + int flgs = (a >> 15) & 1; + int flgo = (b >> 15) & 1; + bs64 v = (bs16)a - (bs16)b; + int flgn = (v >> 15) & 1; + int overflow = (flgs ^ flgo) & (flgn ^ flgs); + + switch (scale) + { + case 0: + break; + case 2: + /* (ASR) */ + if (sat) + v = ((a >> 1) + (a & 0x8000)) - ( (b >> 1) + (b & 0x8000)) + + (((a & 1)-(b & 1))); + else + { + v = ((v & 0xFFFF) >> 1); + if ((!flgs & !flgo & flgn) + || (flgs & !flgo & !flgn) + || (flgs & flgo & flgn) + || (flgs & !flgo & flgn)) + v |= 0x8000; + } + v |= -(v & 0x8000); + flgn = (v >> 15) & 1; + overflow = (flgs ^ flgo) & (flgn ^ flgs); + break; + case 3: + /* (ASL) */ + v <<= 1; + if (v > (bs64)0x7fff || v < (bs64)-0xffff) + overflow = 1; + break; + default: + illegal_instruction (cpu); + } + + if (sat) + { + v = saturate_s16 (v, 0); + } + if (neg) + *neg |= (v >> 15) & 1; + if (zero) + *zero |= (v & 0xFFFF) == 0; + if (overfl) + *overfl |= overflow; + if (carry) + *carry |= (bu16)b <= (bu16)a; + return v; +} + +static bu32 +min32 (SIM_CPU *cpu, bu32 a, bu32 b) +{ + int val = a; + if ((bs32)a > (bs32)b) + val = b; + setflags_nz (cpu, val); + SET_ASTATREG (v, 0); + return val; +} + +static bu32 +max32 (SIM_CPU *cpu, bu32 a, bu32 b) +{ + int val = a; + if ((bs32)a < (bs32)b) + val = b; + setflags_nz (cpu, val); + SET_ASTATREG (v, 0); + return val; +} + +static bu32 +min2x16 (SIM_CPU *cpu, bu32 a, bu32 b) +{ + int val = a; + if ((bs16)a > (bs16)b) + val = (val & 0xFFFF0000) | (b & 0xFFFF); + if ((bs16)(a >> 16) > (bs16)(b >> 16)) + val = (val & 0xFFFF) | (b & 0xFFFF0000); + setflags_nz_2x16 (cpu, val); + SET_ASTATREG (v, 0); + return val; +} + +static bu32 +max2x16 (SIM_CPU *cpu, bu32 a, bu32 b) +{ + int val = a; + if ((bs16)a < (bs16)b) + val = (val & 0xFFFF0000) | (b & 0xFFFF); + if ((bs16)(a >> 16) < (bs16)(b >> 16)) + val = (val & 0xFFFF) | (b & 0xFFFF0000); + setflags_nz_2x16 (cpu, val); + SET_ASTATREG (v, 0); + return val; +} + +static bu32 +add_and_shift (SIM_CPU *cpu, bu32 a, bu32 b, int shift) +{ + int v; + ASTATREG (v_internal) = 0; + v = add32 (cpu, a, b, 0, 0); + while (shift-- > 0) + { + int x = (v >> 30) & 0x3; + if (x == 1 || x == 2) + ASTATREG (v_internal) = 1; + v <<= 1; + } + SET_ASTATREG (az, v == 0); + SET_ASTATREG (an, v & 0x80000000); + SET_ASTATREG (v, ASTATREG (v_internal)); + if (ASTATREG (v)) + SET_ASTATREG (vs, 1); + return v; +} + +static bu32 +xor_reduce (bu64 acc0, bu64 acc1) +{ + int i; + bu32 v = 0; + for (i = 0; i < 40; ++i) + { + v ^= (acc0 & acc1 & 1); + acc0 >>= 1; + acc1 >>= 1; + } + return v; +} + +/* DIVS ( Dreg, Dreg ) ; + Initialize for DIVQ. Set the AQ status bit based on the signs of + the 32-bit dividend and the 16-bit divisor. Left shift the dividend + one bit. Copy AQ into the dividend LSB. */ +static bu32 +divs (SIM_CPU *cpu, bu32 pquo, bu16 divisor) +{ + bu16 r = pquo >> 16; + int aq; + + aq = (r ^ divisor) >> 15; /* Extract msb's and compute quotient bit. */ + SET_ASTATREG (aq, aq); /* Update global quotient state. */ + + pquo <<= 1; + pquo |= aq; + pquo = (pquo & 0x1FFFF) | (r << 17); + return pquo; +} + +/* DIVQ ( Dreg, Dreg ) ; + Based on AQ status bit, either add or subtract the divisor from + the dividend. Then set the AQ status bit based on the MSBs of the + 32-bit dividend and the 16-bit divisor. Left shift the dividend one + bit. Copy the logical inverse of AQ into the dividend LSB. */ +static bu32 +divq (SIM_CPU *cpu, bu32 pquo, bu16 divisor) +{ + unsigned short af = pquo >> 16; + unsigned short r; + int aq; + + if (ASTATREG (aq)) + r = divisor + af; + else + r = af - divisor; + + aq = (r ^ divisor) >> 15; /* Extract msb's and compute quotient bit. */ + SET_ASTATREG (aq, aq); /* Update global quotient state. */ + + pquo <<= 1; + pquo |= !aq; + pquo = (pquo & 0x1FFFF) | (r << 17); + return pquo; +} + +/* ONES ( Dreg ) ; + Count the number of bits set to 1 in the 32bit value. */ +static bu32 +ones (bu32 val) +{ + bu32 i; + bu32 ret; + + ret = 0; + for (i = 0; i < 32; ++i) + ret += !!(val & (1 << i)); + + return ret; +} + +static void +reg_check_sup (SIM_CPU *cpu, int grp, int reg) +{ + if (grp == 7) + cec_require_supervisor (cpu); +} + +static void +reg_write (SIM_CPU *cpu, int grp, int reg, bu32 value) +{ + bu32 *whichreg; + + /* ASTAT is special! */ + if (grp == 4 && reg == 6) + { + SET_ASTAT (value); + return; + } + + /* Check supervisor after get_allreg() so exception order is correct. */ + whichreg = get_allreg (cpu, grp, reg); + reg_check_sup (cpu, grp, reg); + + if (whichreg == &CYCLES2REG) + /* Writes to CYCLES2 goes to the shadow. */ + whichreg = &CYCLES2SHDREG; + else if (whichreg == &SEQSTATREG) + /* Register is read only -- discard writes. */ + return; + else if (whichreg == &EMUDAT_INREG) + /* Writes to EMUDAT goes to the output. */ + whichreg = &EMUDAT_OUTREG; + else if (whichreg == <REG (0) || whichreg == <REG (1)) + /* Writes to LT clears LSB automatically. */ + value &= ~0x1; + else if (whichreg == &AXREG (0) || whichreg == &AXREG (1)) + value &= 0xFF; + + TRACE_REGISTER (cpu, "wrote %s = %#x", get_allreg_name (grp, reg), value); + + *whichreg = value; +} + +static bu32 +reg_read (SIM_CPU *cpu, int grp, int reg) +{ + bu32 *whichreg; + bu32 value; + + /* ASTAT is special! */ + if (grp == 4 && reg == 6) + return ASTAT; + + /* Check supervisor after get_allreg() so exception order is correct. */ + whichreg = get_allreg (cpu, grp, reg); + reg_check_sup (cpu, grp, reg); + + value = *whichreg; + + if (whichreg == &CYCLESREG) + /* Reads of CYCLES reloads CYCLES2 from the shadow. */ + SET_CYCLES2REG (CYCLES2SHDREG); + else if ((whichreg == &AXREG (1) || whichreg == &AXREG (0)) && (value & 0x80)) + /* Sign extend if necessary. */ + value |= 0xFFFFFF00; + + return value; +} + +static bu64 +get_extended_cycles (SIM_CPU *cpu) +{ + return ((bu64)CYCLES2SHDREG << 32) | CYCLESREG; +} + +/* We can't re-use sim_events_time() because the CYCLES registers may be + written/cleared/reset/stopped/started at any time by software. */ +static void +cycles_inc (SIM_CPU *cpu, bu32 inc) +{ + bu64 cycles; + bu32 cycles2; + + if (!(SYSCFGREG & SYSCFG_CCEN)) + return; + + cycles = get_extended_cycles (cpu) + inc; + SET_CYCLESREG (cycles); + cycles2 = cycles >> 32; + if (CYCLES2SHDREG != cycles2) + SET_CYCLES2SHDREG (cycles2); +} + +static bu64 +get_unextended_acc (SIM_CPU *cpu, int which) +{ + return ((bu64)(AXREG (which) & 0xff) << 32) | AWREG (which); +} + +static bu64 +get_extended_acc (SIM_CPU *cpu, int which) +{ + bu64 acc = AXREG (which); + /* Sign extend accumulator values before adding. */ + if (acc & 0x80) + acc |= -0x80; + else + acc &= 0xFF; + acc <<= 32; + acc |= AWREG (which); + return acc; +} + +/* Perform a multiplication of D registers SRC0 and SRC1, sign- or + zero-extending the result to 64 bit. H0 and H1 determine whether the + high part or the low part of the source registers is used. Store 1 in + *PSAT if saturation occurs, 0 otherwise. */ +static bu64 +decode_multfunc (SIM_CPU *cpu, int h0, int h1, int src0, int src1, int mmod, + int MM, bu32 *psat) +{ + bu32 s0 = DREG (src0), s1 = DREG (src1); + bu32 sgn0, sgn1; + bu32 val; + bu64 val1; + + if (h0) + s0 >>= 16; + + if (h1) + s1 >>= 16; + + s0 &= 0xffff; + s1 &= 0xffff; + + sgn0 = -(s0 & 0x8000); + sgn1 = -(s1 & 0x8000); + + if (MM) + s0 |= sgn0; + else + switch (mmod) + { + case 0: + case M_S2RND: + case M_T: + case M_IS: + case M_ISS2: + case M_IH: + case M_W32: + s0 |= sgn0; + s1 |= sgn1; + break; + case M_FU: + case M_IU: + case M_TFU: + break; + default: + illegal_instruction (cpu); + } + + val = s0 * s1; + /* Perform shift correction if appropriate for the mode. */ + *psat = 0; + if (!MM && (mmod == 0 || mmod == M_T || mmod == M_S2RND || mmod == M_W32)) + { + if (val == 0x40000000) + { + if (mmod == M_W32) + val = 0x7fffffff; + else + val = 0x80000000; + *psat = 1; + } + else + val <<= 1; + } + val1 = val; + + if (mmod == 0 || mmod == M_IS || mmod == M_T || mmod == M_S2RND + || mmod == M_ISS2 || mmod == M_IH || (MM && mmod == M_FU)) + val1 |= -(val1 & 0x80000000); + + if (*psat) + val1 &= 0xFFFFFFFFull; + + return val1; +} + +static bu40 +saturate_s40_astat (bu64 val, bu32 *v) +{ + if ((bs64)val < -((bs64)1 << 39)) + { + *v = 1; + return -((bs64)1 << 39); + } + else if ((bs64)val >= ((bs64)1 << 39) - 1) + { + *v = 1; + return ((bu64)1 << 39) - 1; + } + *v = 0; /* No overflow. */ + return val; +} + +static bu40 +saturate_s40 (bu64 val) +{ + bu32 v; + return saturate_s40_astat (val, &v); +} + +static bu32 +saturate_s32 (bu64 val, bu32 *overflow) +{ + if ((bs64)val < -0x80000000ll) + { + if (overflow) + *overflow = 1; + return 0x80000000; + } + if ((bs64)val > 0x7fffffff) + { + if (overflow) + *overflow = 1; + return 0x7fffffff; + } + return val; +} + +static bu32 +saturate_u32 (bu64 val, bu32 *overflow) +{ + if (val > 0xffffffff) + { + if (overflow) + *overflow = 1; + return 0xffffffff; + } + return val; +} + +static bu32 +saturate_u16 (bu64 val, bu32 *overflow) +{ + if (val > 0xffff) + { + if (overflow) + *overflow = 1; + return 0xffff; + } + return val; +} + +static bu64 +rnd16 (bu64 val) +{ + bu64 sgnbits; + + /* FIXME: Should honour rounding mode. */ + if ((val & 0xffff) > 0x8000 + || ((val & 0xffff) == 0x8000 && (val & 0x10000))) + val += 0x8000; + + sgnbits = val & 0xffff000000000000ull; + val >>= 16; + return val | sgnbits; +} + +static bu64 +trunc16 (bu64 val) +{ + bu64 sgnbits = val & 0xffff000000000000ull; + val >>= 16; + return val | sgnbits; +} + +static int +signbits (bu64 val, int size) +{ + bu64 mask = (bu64)1 << (size - 1); + bu64 bit = val & mask; + int count = 0; + for (;;) + { + mask >>= 1; + bit >>= 1; + if (mask == 0) + break; + if ((val & mask) != bit) + break; + count++; + } + if (size == 40) + count -= 8; + + return count; +} + +/* Extract a 16 or 32 bit value from a 64 bit multiplication result. + These 64 bits must be sign- or zero-extended properly from the source + we want to extract, either a 32 bit multiply or a 40 bit accumulator. */ + +static bu32 +extract_mult (SIM_CPU *cpu, bu64 res, int mmod, int MM, + int fullword, bu32 *overflow) +{ + if (fullword) + switch (mmod) + { + case 0: + case M_IS: + return saturate_s32 (res, overflow); + case M_IU: + return saturate_u32 (res, overflow); + case M_FU: + if (MM) + return saturate_s32 (res, overflow); + return saturate_u32 (res, overflow); + case M_S2RND: + case M_ISS2: + return saturate_s32 (res << 1, overflow); + default: + illegal_instruction (cpu); + } + else + switch (mmod) + { + case 0: + case M_W32: + return saturate_s16 (rnd16 (res), overflow); + case M_IH: + return saturate_s32 (rnd16 (res), overflow) & 0xFFFF; + case M_IS: + return saturate_s16 (res, overflow); + case M_FU: + if (MM) + return saturate_s16 (rnd16 (res), overflow); + return saturate_u16 (rnd16 (res), overflow); + case M_IU: + if (MM) + return saturate_s16 (res, overflow); + return saturate_u16 (res, overflow); + + case M_T: + return saturate_s16 (trunc16 (res), overflow); + case M_TFU: + return saturate_u16 (trunc16 (res), overflow); + + case M_S2RND: + return saturate_s16 (rnd16 (res << 1), overflow); + case M_ISS2: + return saturate_s16 (res << 1, overflow); + default: + illegal_instruction (cpu); + } +} + +static bu32 +decode_macfunc (SIM_CPU *cpu, int which, int op, int h0, int h1, int src0, + int src1, int mmod, int MM, int fullword, bu32 *overflow, + bu32 *neg) +{ + bu64 acc; + bu32 sat = 0, tsat, ret; + + /* Sign extend accumulator if necessary, otherwise unsigned. */ + if (mmod == 0 || mmod == M_T || mmod == M_IS || mmod == M_ISS2 + || mmod == M_S2RND || mmod == M_IH || mmod == M_W32) + acc = get_extended_acc (cpu, which); + else + acc = get_unextended_acc (cpu, which); + + if (MM && (mmod == M_T || mmod == M_IS || mmod == M_ISS2 + || mmod == M_S2RND || mmod == M_IH || mmod == M_W32)) + acc |= -(acc & 0x80000000); + + if (op != 3) + { + bu8 sgn0 = (acc >> 31) & 1; + /* This can't saturate, so we don't keep track of the sat flag. */ + bu64 res = decode_multfunc (cpu, h0, h1, src0, src1, mmod, + MM, &tsat); + + /* Perform accumulation. */ + switch (op) + { + case 0: + acc = res; + sgn0 = (acc >> 31) & 1; + break; + case 1: + acc = acc + res; + break; + case 2: + acc = acc - res; + break; + } + + /* Saturate. */ + switch (mmod) + { + case 0: + case M_T: + case M_IS: + case M_ISS2: + case M_S2RND: + if ((bs64)acc < -((bs64)1 << 39)) + acc = -((bu64)1 << 39), sat = 1; + else if ((bs64)acc > 0x7fffffffffll) + acc = 0x7fffffffffull, sat = 1; + break; + case M_TFU: + if (!MM && acc > 0xFFFFFFFFFFull) + acc = 0x0, sat = 1; + if (MM && acc > 0xFFFFFFFF) + acc &= 0xFFFFFFFF; + break; + case M_IU: + if (acc & 0x8000000000000000ull) + acc = 0x0, sat = 1; + if (acc > 0xFFFFFFFFFFull) + acc &= 0xFFFFFFFFFFull, sat = 1; + if (MM && acc > 0xFFFFFFFF) + acc &= 0xFFFFFFFF; + if (acc & 0x80000000) + acc |= 0xffffffff00000000ull; + break; + case M_FU: + if (!MM && (bs64)acc < 0) + acc = 0x0, sat = 1; + if (MM && (bs64)acc < -((bs64)1 << 39)) + acc = -((bu64)1 << 39), sat = 1; + if (!MM && (bs64)acc > (bs64)0xFFFFFFFFFFll) + acc = 0xFFFFFFFFFFull, sat = 1; + if (MM && acc > 0xFFFFFFFFFFull) + acc &= 0xFFFFFFFFFFull; + if (MM && acc & 0x80000000) + acc |= 0xffffffff00000000ull; + break; + case M_IH: + if ((bs64)acc < -0x80000000ll) + acc = -0x80000000ull, sat = 1; + else if ((bs64)acc >= 0x7fffffffll) + acc = 0x7fffffffull, sat = 1; + break; + case M_W32: + if (sgn0 && (sgn0 != ((acc >> 31) & 1)) + && (((acc >> 32) & 0xFF) == 0xff)) + acc = 0x80000000; + acc &= 0xffffffff; + if (acc & 0x80000000) + acc |= 0xffffffff00000000ull; + break; + default: + illegal_instruction (cpu); + } + + if (acc & 0x8000000000ull) + *neg = 1; + + STORE (AXREG (which), (acc >> 32) & 0xff); + STORE (AWREG (which), acc & 0xffffffff); + STORE (ASTATREG (av[which]), sat); + if (sat) + STORE (ASTATREG (avs[which]), sat); + } + + ret = extract_mult (cpu, acc, mmod, MM, fullword, overflow); + + if (!fullword) + { + if (ret & 0x8000) + *neg = 1; + } + else + { + if (ret & 0x80000000) + *neg = 1; + } + + return ret; +} + +bu32 +hwloop_get_next_pc (SIM_CPU *cpu, bu32 pc, bu32 insn_len) +{ + int i; + + if (insn_len == 0) + return pc; + + /* If our PC has reached the bottom of a hardware loop, + move back up to the top of the hardware loop. */ + for (i = 1; i >= 0; --i) + if (LCREG (i) > 1 && pc == LBREG (i)) + { + TRACE_BRANCH (cpu, pc, LTREG (i), i, "Hardware loop %i", i); + return LTREG (i); + } + + return pc + insn_len; +} + +static void +decode_ProgCtrl_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc) +{ + /* ProgCtrl + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask); + int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask); + + TRACE_EXTRACT (cpu, "%s: poprnd:%i prgfunc:%i", __func__, poprnd, prgfunc); + + if (prgfunc == 0 && poprnd == 0) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_nop); + TRACE_INSN (cpu, "NOP;"); + } + else if (prgfunc == 1 && poprnd == 0) + { + bu32 newpc = RETSREG; + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "RTS;"); + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + TRACE_BRANCH (cpu, pc, newpc, -1, "RTS"); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + CYCLE_DELAY = 5; + } + else if (prgfunc == 1 && poprnd == 1) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "RTI;"); + /* Do not do IFETCH_CHECK here -- LSB has special meaning. */ + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_return (cpu, -1); + CYCLE_DELAY = 5; + } + else if (prgfunc == 1 && poprnd == 2) + { + bu32 newpc = RETXREG; + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "RTX;"); + /* XXX: Not sure if this is what the hardware does. */ + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_return (cpu, IVG_EVX); + CYCLE_DELAY = 5; + } + else if (prgfunc == 1 && poprnd == 3) + { + bu32 newpc = RETNREG; + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "RTN;"); + /* XXX: Not sure if this is what the hardware does. */ + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_return (cpu, IVG_NMI); + CYCLE_DELAY = 5; + } + else if (prgfunc == 1 && poprnd == 4) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "RTE;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_return (cpu, IVG_EMU); + CYCLE_DELAY = 5; + } + else if (prgfunc == 2 && poprnd == 0) + { + SIM_DESC sd = CPU_STATE (cpu); + sim_events *events = STATE_EVENTS (sd); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync); + /* XXX: in supervisor mode, utilizes wake up sources + in user mode, it's a NOP ... */ + TRACE_INSN (cpu, "IDLE;"); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + /* Timewarp ! */ + if (events->queue) + CYCLE_DELAY = events->time_from_event; + else + abort (); /* XXX: Should this ever happen ? */ + } + else if (prgfunc == 2 && poprnd == 3) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync); + /* Just NOP it. */ + TRACE_INSN (cpu, "CSYNC;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + CYCLE_DELAY = 10; + } + else if (prgfunc == 2 && poprnd == 4) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync); + /* Just NOP it. */ + TRACE_INSN (cpu, "SSYNC;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + /* Really 10+, but no model info for this. */ + CYCLE_DELAY = 10; + } + else if (prgfunc == 2 && poprnd == 5) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec); + TRACE_INSN (cpu, "EMUEXCPT;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_exception (cpu, VEC_SIM_TRAP); + } + else if (prgfunc == 3 && poprnd < 8) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec); + TRACE_INSN (cpu, "CLI R%i;", poprnd); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (poprnd, cec_cli (cpu)); + } + else if (prgfunc == 4 && poprnd < 8) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec); + TRACE_INSN (cpu, "STI R%i;", poprnd); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_sti (cpu, DREG (poprnd)); + CYCLE_DELAY = 3; + } + else if (prgfunc == 5 && poprnd < 8) + { + bu32 newpc = PREG (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "JUMP (%s);", get_preg_name (poprnd)); + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (Preg)"); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; + } + else if (prgfunc == 6 && poprnd < 8) + { + bu32 newpc = PREG (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "CALL (%s);", get_preg_name (poprnd)); + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (Preg)"); + /* If we're at the end of a hardware loop, RETS is going to be + the top of the loop rather than the next instruction. */ + SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2)); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; + } + else if (prgfunc == 7 && poprnd < 8) + { + bu32 newpc = pc + PREG (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "CALL (PC + %s);", get_preg_name (poprnd)); + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (PC + Preg)"); + SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2)); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; + } + else if (prgfunc == 8 && poprnd < 8) + { + bu32 newpc = pc + PREG (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch); + TRACE_INSN (cpu, "JUMP (PC + %s);", get_preg_name (poprnd)); + IFETCH_CHECK (newpc); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (PC + Preg)"); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; + } + else if (prgfunc == 9) + { + int raise = uimm4 (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec); + TRACE_INSN (cpu, "RAISE %s;", uimm4_str (raise)); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_require_supervisor (cpu); + if (raise == IVG_IVHW) + cec_hwerr (cpu, HWERR_RAISE_5); + else + cec_latch (cpu, raise); + CYCLE_DELAY = 3; /* XXX: Only if IVG is unmasked. */ + } + else if (prgfunc == 10) + { + int excpt = uimm4 (poprnd); + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec); + TRACE_INSN (cpu, "EXCPT %s;", uimm4_str (excpt)); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + cec_exception (cpu, excpt); + CYCLE_DELAY = 3; + } + else if (prgfunc == 11 && poprnd < 6) + { + bu32 addr = PREG (poprnd); + bu8 byte; + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_atomic); + TRACE_INSN (cpu, "TESTSET (%s);", get_preg_name (poprnd)); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + byte = GET_WORD (addr); + SET_CCREG (byte == 0); + PUT_BYTE (addr, byte | 0x80); + /* Also includes memory stalls, but we don't model that. */ + CYCLE_DELAY = 2; + } + else + illegal_instruction (cpu); +} + +static void +decode_CaCTRL_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* CaCTRL + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask); + int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask); + int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask); + bu32 preg = PREG (reg); + const char * const sinsn[] = { "PREFETCH", "FLUSHINV", "FLUSH", "IFLUSH", }; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CaCTRL); + TRACE_EXTRACT (cpu, "%s: a:%i op:%i reg:%i", __func__, a, op, reg); + TRACE_INSN (cpu, "%s [%s%s];", sinsn[op], get_preg_name (reg), a ? "++" : ""); + + if (INSN_LEN == 8) + /* None of these can be part of a parallel instruction. */ + illegal_instruction_combination (cpu); + + /* No cache simulation, so these are (mostly) all NOPs. + XXX: The hardware takes care of masking to cache lines, but need + to check behavior of the post increment. Should we be aligning + the value to the cache line before adding the cache line size, or + do we just add the cache line size ? */ + if (op == 0) + { /* PREFETCH */ + mmu_check_cache_addr (cpu, preg, false, false); + } + else if (op == 1) + { /* FLUSHINV */ + mmu_check_cache_addr (cpu, preg, true, false); + } + else if (op == 2) + { /* FLUSH */ + mmu_check_cache_addr (cpu, preg, true, false); + } + else if (op == 3) + { /* IFLUSH */ + mmu_check_cache_addr (cpu, preg, false, true); + } + + if (a) + SET_PREG (reg, preg + BFIN_L1_CACHE_BYTES); +} + +static void +decode_PushPopReg_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* PushPopReg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask); + int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask); + int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask); + const char *reg_name = get_allreg_name (grp, reg); + bu32 value; + bu32 sp = SPREG; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PushPopReg); + TRACE_EXTRACT (cpu, "%s: W:%i grp:%i reg:%i", __func__, W, grp, reg); + TRACE_DECODE (cpu, "%s: reg:%s", __func__, reg_name); + + /* Can't push/pop reserved registers */ + if (reg_is_reserved (grp, reg)) + illegal_instruction (cpu); + + if (W == 0) + { + /* Dreg and Preg are not supported by this instruction. */ + if (grp == 0 || grp == 1) + illegal_instruction (cpu); + TRACE_INSN (cpu, "%s = [SP++];", reg_name); + /* Can't pop USP while in userspace. */ + if (INSN_LEN == 8 || (grp == 7 && reg == 0 && cec_is_user_mode(cpu))) + illegal_instruction_combination (cpu); + /* XXX: The valid register check is in reg_write(), so we might + incorrectly do a GET_LONG() here ... */ + value = GET_LONG (sp); + reg_write (cpu, grp, reg, value); + if (grp == 7 && reg == 3) + cec_pop_reti (cpu); + + sp += 4; + } + else + { + TRACE_INSN (cpu, "[--SP] = %s;", reg_name); + /* Can't push SP. */ + if (INSN_LEN == 8 || (grp == 1 && reg == 6)) + illegal_instruction_combination (cpu); + + sp -= 4; + value = reg_read (cpu, grp, reg); + if (grp == 7 && reg == 3) + cec_push_reti (cpu); + + PUT_LONG (sp, value); + } + + /* Note: SP update must be delayed until after all reads/writes; see + comments in decode_PushPopMultiple_0() for more info. */ + SET_SPREG (sp); +} + +static void +decode_PushPopMultiple_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* PushPopMultiple + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask); + int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask); + int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask); + int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask); + int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask); + int i; + bu32 sp = SPREG; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PushPopMultiple); + TRACE_EXTRACT (cpu, "%s: d:%i p:%i W:%i dr:%i pr:%i", + __func__, d, p, W, dr, pr); + + if ((d == 0 && p == 0) || (p && imm5 (pr) > 5) + || (d && !p && pr) || (p && !d && dr)) + illegal_instruction (cpu); + + if (W == 1) + { + if (d && p) + TRACE_INSN (cpu, "[--SP] = (R7:%i, P5:%i);", dr, pr); + else if (d) + TRACE_INSN (cpu, "[--SP] = (R7:%i);", dr); + else + TRACE_INSN (cpu, "[--SP] = (P5:%i);", pr); + + if (d) + for (i = dr; i < 8; i++) + { + sp -= 4; + PUT_LONG (sp, DREG (i)); + } + if (p) + for (i = pr; i < 6; i++) + { + sp -= 4; + PUT_LONG (sp, PREG (i)); + } + + CYCLE_DELAY = 14; + } + else + { + if (d && p) + TRACE_INSN (cpu, "(R7:%i, P5:%i) = [SP++];", dr, pr); + else if (d) + TRACE_INSN (cpu, "(R7:%i) = [SP++];", dr); + else + TRACE_INSN (cpu, "(P5:%i) = [SP++];", pr); + + if (p) + for (i = 5; i >= pr; i--) + { + SET_PREG (i, GET_LONG (sp)); + sp += 4; + } + if (d) + for (i = 7; i >= dr; i--) + { + SET_DREG (i, GET_LONG (sp)); + sp += 4; + } + + CYCLE_DELAY = 11; + } + + /* Note: SP update must be delayed until after all reads/writes so that + if an exception does occur, the insn may be re-executed as the + SP has not yet changed. */ + SET_SPREG (sp); +} + +static void +decode_ccMV_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* ccMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask); + int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask); + int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask); + int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask); + int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask); + int cond = T ? CCREG : ! CCREG; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ccMV); + TRACE_EXTRACT (cpu, "%s: T:%i d:%i s:%i dst:%i src:%i", + __func__, T, d, s, dst, src); + + TRACE_INSN (cpu, "IF %sCC %s = %s;", T ? "" : "! ", + get_allreg_name (d, dst), + get_allreg_name (s, src)); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + if (cond) + reg_write (cpu, d, dst, reg_read (cpu, s, src)); +} + +static void +decode_CCflag_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* CCflag + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask); + int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask); + int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask); + int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask); + int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CCflag); + TRACE_EXTRACT (cpu, "%s: I:%i opc:%i G:%i y:%i x:%i", + __func__, I, opc, G, y, x); + + if (opc > 4) + { + bs64 acc0 = get_extended_acc (cpu, 0); + bs64 acc1 = get_extended_acc (cpu, 1); + bs64 diff = acc0 - acc1; + + if (x != 0 || y != 0) + illegal_instruction (cpu); + + if (opc == 5 && I == 0 && G == 0) + { + TRACE_INSN (cpu, "CC = A0 == A1;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG (acc0 == acc1); + } + else if (opc == 6 && I == 0 && G == 0) + { + TRACE_INSN (cpu, "CC = A0 < A1"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG (acc0 < acc1); + } + else if (opc == 7 && I == 0 && G == 0) + { + TRACE_INSN (cpu, "CC = A0 <= A1"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG (acc0 <= acc1); + } + else + illegal_instruction (cpu); + + SET_ASTATREG (az, diff == 0); + SET_ASTATREG (an, diff < 0); + SET_ASTATREG (ac0, (bu40)acc1 <= (bu40)acc0); + } + else + { + int issigned = opc < 3; + const char *sign = issigned ? "" : " (IU)"; + bu32 srcop = G ? PREG (x) : DREG (x); + char s = G ? 'P' : 'R'; + bu32 dstop = I ? (issigned ? imm3 (y) : uimm3 (y)) : G ? PREG (y) : DREG (y); + const char *op; + char d = G ? 'P' : 'R'; + int flgs = srcop >> 31; + int flgo = dstop >> 31; + + bu32 result = srcop - dstop; + int cc; + int flgn = result >> 31; + int overflow = (flgs ^ flgo) & (flgn ^ flgs); + int az = result == 0; + int ac0 = dstop <= srcop; + int an; + if (issigned) + an = (flgn && !overflow) || (!flgn && overflow); + else + an = dstop > srcop; + + switch (opc) + { + default: /* Shutup useless gcc warnings. */ + case 0: /* signed */ + op = "=="; + cc = az; + break; + case 1: /* signed */ + op = "<"; + cc = an; + break; + case 2: /* signed */ + op = "<="; + cc = an || az; + break; + case 3: /* unsigned */ + op = "<"; + cc = !ac0; + break; + case 4: /* unsigned */ + op = "<="; + cc = !ac0 || az; + break; + } + + if (I) + TRACE_INSN (cpu, "CC = %c%i %s %s%s;", s, x, op, + issigned ? imm3_str (y) : uimm3_str (y), sign); + else + { + TRACE_DECODE (cpu, "%s %c%i:%x %c%i:%x", __func__, + s, x, srcop, d, y, dstop); + TRACE_INSN (cpu, "CC = %c%i %s %c%i%s;", s, x, op, d, y, sign); + } + + SET_CCREG (cc); + /* Pointer compares only touch CC. */ + if (!G) + { + SET_ASTATREG (az, az); + SET_ASTATREG (an, an); + SET_ASTATREG (ac0, ac0); + } + } +} + +static void +decode_CC2dreg_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* CC2dreg + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask); + int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CC2dreg); + TRACE_EXTRACT (cpu, "%s: op:%i reg:%i", __func__, op, reg); + + if (op == 0) + { + TRACE_INSN (cpu, "R%i = CC;", reg); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (reg, CCREG); + } + else if (op == 1) + { + TRACE_INSN (cpu, "CC = R%i;", reg); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG (DREG (reg) != 0); + } + else if (op == 3 && reg == 0) + { + TRACE_INSN (cpu, "CC = !CC;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG (!CCREG); + } + else + illegal_instruction (cpu); +} + +static void +decode_CC2stat_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* CC2stat + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask); + int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask); + int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask); + bu32 pval; + + const char * const op_names[] = { "", "|", "&", "^" } ; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CC2stat); + TRACE_EXTRACT (cpu, "%s: D:%i op:%i cbit:%i", __func__, D, op, cbit); + + TRACE_INSN (cpu, "%s %s= %s;", D ? astat_names[cbit] : "CC", + op_names[op], D ? "CC" : astat_names[cbit]); + + /* CC = CC; is invalid. */ + if (cbit == 5) + illegal_instruction (cpu); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + pval = !!(ASTAT & (1 << cbit)); + if (D == 0) + switch (op) + { + case 0: SET_CCREG (pval); break; + case 1: SET_CCREG (CCREG | pval); break; + case 2: SET_CCREG (CCREG & pval); break; + case 3: SET_CCREG (CCREG ^ pval); break; + } + else + { + switch (op) + { + case 0: pval = CCREG; break; + case 1: pval |= CCREG; break; + case 2: pval &= CCREG; break; + case 3: pval ^= CCREG; break; + } + TRACE_REGISTER (cpu, "wrote ASTAT[%s] = %i", astat_names[cbit], pval); + SET_ASTAT ((ASTAT & ~(1 << cbit)) | (pval << cbit)); + } +} + +static void +decode_BRCC_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc) +{ + /* BRCC + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask); + int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask); + int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask); + int cond = T ? CCREG : ! CCREG; + int pcrel = pcrel10 (offset); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_BRCC); + TRACE_EXTRACT (cpu, "%s: T:%i B:%i offset:%#x", __func__, T, B, offset); + TRACE_DECODE (cpu, "%s: pcrel10:%#x", __func__, pcrel); + + TRACE_INSN (cpu, "IF %sCC JUMP %#x%s;", T ? "" : "! ", + pcrel, B ? " (bp)" : ""); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + if (cond) + { + bu32 newpc = pc + pcrel; + TRACE_BRANCH (cpu, pc, newpc, -1, "Conditional JUMP"); + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = B ? 5 : 9; + } + else + { + PROFILE_BRANCH_UNTAKEN (cpu); + CYCLE_DELAY = B ? 9 : 1; + } +} + +static void +decode_UJUMP_0 (SIM_CPU *cpu, bu16 iw0, bu32 pc) +{ + /* UJUMP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 0 |.offset........................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask); + int pcrel = pcrel12 (offset); + bu32 newpc = pc + pcrel; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_UJUMP); + TRACE_EXTRACT (cpu, "%s: offset:%#x", __func__, offset); + TRACE_DECODE (cpu, "%s: pcrel12:%#x", __func__, pcrel); + + TRACE_INSN (cpu, "JUMP.S %#x;", pcrel); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.S"); + + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; +} + +static void +decode_REGMV_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* REGMV + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask); + int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask); + int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); + int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); + const char *srcreg_name = get_allreg_name (gs, src); + const char *dstreg_name = get_allreg_name (gd, dst); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_REGMV); + TRACE_EXTRACT (cpu, "%s: gd:%i gs:%i dst:%i src:%i", + __func__, gd, gs, dst, src); + TRACE_DECODE (cpu, "%s: dst:%s src:%s", __func__, dstreg_name, srcreg_name); + + TRACE_INSN (cpu, "%s = %s;", dstreg_name, srcreg_name); + + /* Reserved slots cannot be a src/dst. */ + if (reg_is_reserved (gs, src) || reg_is_reserved (gd, dst)) + goto invalid_move; + + /* Standard register moves. */ + if ((gs < 2) /* Dregs/Pregs src */ + || (gd < 2) /* Dregs/Pregs dst */ + || (gs == 4 && src < 4) /* Accumulators src */ + || (gd == 4 && dst < 4 && (gs < 4)) /* Accumulators dst */ + || (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) /* EMUDAT src */ + || (gd == 7 && dst == 7)) /* EMUDAT dst */ + goto valid_move; + + /* dareg = dareg (IMBL) */ + if (gs < 4 && gd < 4) + goto valid_move; + + /* USP can be src to sysregs, but not dagregs. */ + if ((gs == 7 && src == 0) && (gd >= 4)) + goto valid_move; + + /* USP can move between genregs (only check Accumulators). */ + if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) + || ((gd == 7 && dst == 0) && (gs == 4 && src < 4))) + goto valid_move; + + /* Still here ? Invalid reg pair. */ + invalid_move: + illegal_instruction (cpu); + + valid_move: + reg_write (cpu, gd, dst, reg_read (cpu, gs, src)); +} + +static void +decode_ALU2op_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* ALU2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask); + int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask); + int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ALU2op); + TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst); + + if (opc == 0) + { + TRACE_INSN (cpu, "R%i >>>= R%i;", dst, src); + SET_DREG (dst, ashiftrt (cpu, DREG (dst), DREG (src), 32)); + } + else if (opc == 1) + { + bu32 val; + TRACE_INSN (cpu, "R%i >>= R%i;", dst, src); + if (DREG (src) <= 0x1F) + val = lshiftrt (cpu, DREG (dst), DREG (src), 32); + else + val = 0; + SET_DREG (dst, val); + } + else if (opc == 2) + { + TRACE_INSN (cpu, "R%i <<= R%i;", dst, src); + SET_DREG (dst, lshift (cpu, DREG (dst), DREG (src), 32, 0)); + } + else if (opc == 3) + { + TRACE_INSN (cpu, "R%i *= R%i;", dst, src); + SET_DREG (dst, DREG (dst) * DREG (src)); + CYCLE_DELAY = 3; + } + else if (opc == 4) + { + TRACE_INSN (cpu, "R%i = (R%i + R%i) << 1;", dst, dst, src); + SET_DREG (dst, add_and_shift (cpu, DREG (dst), DREG (src), 1)); + } + else if (opc == 5) + { + TRACE_INSN (cpu, "R%i = (R%i + R%i) << 2;", dst, dst, src); + SET_DREG (dst, add_and_shift (cpu, DREG (dst), DREG (src), 2)); + } + else if (opc == 8) + { + TRACE_INSN (cpu, "DIVQ ( R%i, R%i );", dst, src); + SET_DREG (dst, divq (cpu, DREG (dst), (bu16)DREG (src))); + } + else if (opc == 9) + { + TRACE_INSN (cpu, "DIVS ( R%i, R%i );", dst, src); + SET_DREG (dst, divs (cpu, DREG (dst), (bu16)DREG (src))); + } + else if (opc == 10) + { + TRACE_INSN (cpu, "R%i = R%i.L (X);", dst, src); + SET_DREG (dst, (bs32) (bs16) DREG (src)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 11) + { + TRACE_INSN (cpu, "R%i = R%i.L (Z);", dst, src); + SET_DREG (dst, (bu32) (bu16) DREG (src)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 12) + { + TRACE_INSN (cpu, "R%i = R%i.B (X);", dst, src); + SET_DREG (dst, (bs32) (bs8) DREG (src)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 13) + { + TRACE_INSN (cpu, "R%i = R%i.B (Z);", dst, src); + SET_DREG (dst, (bu32) (bu8) DREG (src)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 14) + { + bu32 val = DREG (src); + TRACE_INSN (cpu, "R%i = - R%i;", dst, src); + SET_DREG (dst, -val); + setflags_nz (cpu, DREG (dst)); + SET_ASTATREG (v, val == 0x80000000); + if (ASTATREG (v)) + SET_ASTATREG (vs, 1); + SET_ASTATREG (ac0, val == 0x0); + /* XXX: Documentation isn't entirely clear about av0 and av1. */ + } + else if (opc == 15) + { + TRACE_INSN (cpu, "R%i = ~ R%i;", dst, src); + SET_DREG (dst, ~DREG (src)); + setflags_logical (cpu, DREG (dst)); + } + else + illegal_instruction (cpu); +} + +static void +decode_PTR2op_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* PTR2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask); + int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask); + int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask); + const char *src_name = get_preg_name (src); + const char *dst_name = get_preg_name (dst); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PTR2op); + TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst); + + if (opc == 0) + { + TRACE_INSN (cpu, "%s -= %s", dst_name, src_name); + SET_PREG (dst, PREG (dst) - PREG (src)); + } + else if (opc == 1) + { + TRACE_INSN (cpu, "%s = %s << 2", dst_name, src_name); + SET_PREG (dst, PREG (src) << 2); + } + else if (opc == 3) + { + TRACE_INSN (cpu, "%s = %s >> 2", dst_name, src_name); + SET_PREG (dst, PREG (src) >> 2); + } + else if (opc == 4) + { + TRACE_INSN (cpu, "%s = %s >> 1", dst_name, src_name); + SET_PREG (dst, PREG (src) >> 1); + } + else if (opc == 5) + { + TRACE_INSN (cpu, "%s += %s (BREV)", dst_name, src_name); + SET_PREG (dst, add_brev (PREG (dst), PREG (src))); + } + else if (opc == 6) + { + TRACE_INSN (cpu, "%s = (%s + %s) << 1", dst_name, dst_name, src_name); + SET_PREG (dst, (PREG (dst) + PREG (src)) << 1); + } + else if (opc == 7) + { + TRACE_INSN (cpu, "%s = (%s + %s) << 2", dst_name, dst_name, src_name); + SET_PREG (dst, (PREG (dst) + PREG (src)) << 2); + } + else + illegal_instruction (cpu); +} + +static void +decode_LOGI2op_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* LOGI2op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask); + int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask); + int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask); + int uimm = uimm5 (src); + const char *uimm_str = uimm5_str (uimm); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LOGI2op); + TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst); + TRACE_DECODE (cpu, "%s: uimm5:%#x", __func__, uimm); + + if (opc == 0) + { + TRACE_INSN (cpu, "CC = ! BITTST (R%i, %s);", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG ((~DREG (dst) >> uimm) & 1); + } + else if (opc == 1) + { + TRACE_INSN (cpu, "CC = BITTST (R%i, %s);", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_CCREG ((DREG (dst) >> uimm) & 1); + } + else if (opc == 2) + { + TRACE_INSN (cpu, "BITSET (R%i, %s);", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, DREG (dst) | (1 << uimm)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 3) + { + TRACE_INSN (cpu, "BITTGL (R%i, %s);", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, DREG (dst) ^ (1 << uimm)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 4) + { + TRACE_INSN (cpu, "BITCLR (R%i, %s);", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, DREG (dst) & ~(1 << uimm)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 5) + { + TRACE_INSN (cpu, "R%i >>>= %s;", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, ashiftrt (cpu, DREG (dst), uimm, 32)); + } + else if (opc == 6) + { + TRACE_INSN (cpu, "R%i >>= %s;", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, lshiftrt (cpu, DREG (dst), uimm, 32)); + } + else if (opc == 7) + { + TRACE_INSN (cpu, "R%i <<= %s;", dst, uimm_str); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_DREG (dst, lshift (cpu, DREG (dst), uimm, 32, 0)); + } +} + +static void +decode_COMP3op_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* COMP3op + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask); + int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask); + int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); + int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMP3op); + TRACE_EXTRACT (cpu, "%s: opc:%i dst:%i src1:%i src0:%i", + __func__, opc, dst, src1, src0); + + if (opc == 0) + { + TRACE_INSN (cpu, "R%i = R%i + R%i;", dst, src0, src1); + SET_DREG (dst, add32 (cpu, DREG (src0), DREG (src1), 1, 0)); + } + else if (opc == 1) + { + TRACE_INSN (cpu, "R%i = R%i - R%i;", dst, src0, src1); + SET_DREG (dst, sub32 (cpu, DREG (src0), DREG (src1), 1, 0, 0)); + } + else if (opc == 2) + { + TRACE_INSN (cpu, "R%i = R%i & R%i;", dst, src0, src1); + SET_DREG (dst, DREG (src0) & DREG (src1)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 3) + { + TRACE_INSN (cpu, "R%i = R%i | R%i;", dst, src0, src1); + SET_DREG (dst, DREG (src0) | DREG (src1)); + setflags_logical (cpu, DREG (dst)); + } + else if (opc == 4) + { + TRACE_INSN (cpu, "R%i = R%i ^ R%i;", dst, src0, src1); + SET_DREG (dst, DREG (src0) ^ DREG (src1)); + setflags_logical (cpu, DREG (dst)); + } + else + { + int shift = opc - 5; + const char *dst_name = get_preg_name (dst); + const char *src0_name = get_preg_name (src0); + const char *src1_name = get_preg_name (src1); + + /* If src0 == src1 this is disassembled as a shift by 1, but this + distinction doesn't matter for our purposes. */ + if (shift) + TRACE_INSN (cpu, "%s = (%s + %s) << %#x;", + dst_name, src0_name, src1_name, shift); + else + TRACE_INSN (cpu, "%s = %s + %s", + dst_name, src0_name, src1_name); + SET_PREG (dst, PREG (src0) + (PREG (src1) << shift)); + } +} + +static void +decode_COMPI2opD_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* COMPI2opD + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask); + int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask); + int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask); + int imm = imm7 (src); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMPI2opD); + TRACE_EXTRACT (cpu, "%s: op:%i src:%i dst:%i", __func__, op, src, dst); + TRACE_DECODE (cpu, "%s: imm7:%#x", __func__, imm); + + if (op == 0) + { + TRACE_INSN (cpu, "R%i = %s (X);", dst, imm7_str (imm)); + SET_DREG (dst, imm); + } + else if (op == 1) + { + TRACE_INSN (cpu, "R%i += %s;", dst, imm7_str (imm)); + SET_DREG (dst, add32 (cpu, DREG (dst), imm, 1, 0)); + } +} + +static void +decode_COMPI2opP_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* COMPI2opP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask); + int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask); + int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask); + int imm = imm7 (src); + const char *dst_name = get_preg_name (dst); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMPI2opP); + TRACE_EXTRACT (cpu, "%s: op:%i src:%i dst:%i", __func__, op, src, dst); + TRACE_DECODE (cpu, "%s: imm:%#x", __func__, imm); + + if (op == 0) + { + TRACE_INSN (cpu, "%s = %s;", dst_name, imm7_str (imm)); + SET_PREG (dst, imm); + } + else if (op == 1) + { + TRACE_INSN (cpu, "%s += %s;", dst_name, imm7_str (imm)); + SET_PREG (dst, PREG (dst) + imm); + } +} + +static void +decode_LDSTpmod_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* LDSTpmod + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask); + int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask); + int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask); + int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask); + int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask); + const char *ptr_name = get_preg_name (ptr); + const char *idx_name = get_preg_name (idx); + bu32 addr, val; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTpmod); + TRACE_EXTRACT (cpu, "%s: W:%i aop:%i reg:%i idx:%i ptr:%i", + __func__, W, aop, reg, idx, ptr); + + if (aop == 1 && W == 0 && idx == ptr) + { + TRACE_INSN (cpu, "R%i.L = W[%s];", reg, ptr_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val); + } + else if (aop == 2 && W == 0 && idx == ptr) + { + TRACE_INSN (cpu, "R%i.H = W[%s];", reg, ptr_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (val << 16)); + } + else if (aop == 1 && W == 1 && idx == ptr) + { + TRACE_INSN (cpu, "W[%s] = R%i.L;", ptr_name, reg); + addr = PREG (ptr); + PUT_WORD (addr, DREG (reg)); + } + else if (aop == 2 && W == 1 && idx == ptr) + { + TRACE_INSN (cpu, "W[%s] = R%i.H;", ptr_name, reg); + addr = PREG (ptr); + PUT_WORD (addr, DREG (reg) >> 16); + } + else if (aop == 0 && W == 0) + { + TRACE_INSN (cpu, "R%i = [%s ++ %s];", reg, ptr_name, idx_name); + addr = PREG (ptr); + val = GET_LONG (addr); + STORE (DREG (reg), val); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 1 && W == 0) + { + TRACE_INSN (cpu, "R%i.L = W[%s ++ %s];", reg, ptr_name, idx_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 2 && W == 0) + { + TRACE_INSN (cpu, "R%i.H = W[%s ++ %s];", reg, ptr_name, idx_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (val << 16)); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 3 && W == 0) + { + TRACE_INSN (cpu, "R%i = W[%s ++ %s] (Z);", reg, ptr_name, idx_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), val); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 3 && W == 1) + { + TRACE_INSN (cpu, "R%i = W[%s ++ %s] (X);", reg, ptr_name, idx_name); + addr = PREG (ptr); + val = GET_WORD (addr); + STORE (DREG (reg), (bs32) (bs16) val); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 0 && W == 1) + { + TRACE_INSN (cpu, "[%s ++ %s] = R%i;", ptr_name, idx_name, reg); + addr = PREG (ptr); + PUT_LONG (addr, DREG (reg)); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 1 && W == 1) + { + TRACE_INSN (cpu, "W[%s ++ %s] = R%i.L;", ptr_name, idx_name, reg); + addr = PREG (ptr); + PUT_WORD (addr, DREG (reg)); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else if (aop == 2 && W == 1) + { + TRACE_INSN (cpu, "W[%s ++ %s] = R%i.H;", ptr_name, idx_name, reg); + addr = PREG (ptr); + PUT_WORD (addr, DREG (reg) >> 16); + if (ptr != idx) + STORE (PREG (ptr), addr + PREG (idx)); + } + else + illegal_instruction (cpu); +} + +static void +decode_dagMODim_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* dagMODim + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask); + int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask); + int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask); + int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dagMODim); + TRACE_EXTRACT (cpu, "%s: br:%i op:%i m:%i i:%i", __func__, br, op, m, i); + + if (op == 0 && br == 1) + { + TRACE_INSN (cpu, "I%i += M%i (BREV);", i, m); + SET_IREG (i, add_brev (IREG (i), MREG (m))); + } + else if (op == 0) + { + TRACE_INSN (cpu, "I%i += M%i;", i, m); + dagadd (cpu, i, MREG (m)); + } + else if (op == 1 && br == 0) + { + TRACE_INSN (cpu, "I%i -= M%i;", i, m); + dagsub (cpu, i, MREG (m)); + } + else + illegal_instruction (cpu); +} + +static void +decode_dagMODik_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* dagMODik + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask); + int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dagMODik); + TRACE_EXTRACT (cpu, "%s: op:%i i:%i", __func__, op, i); + + if (op == 0) + { + TRACE_INSN (cpu, "I%i += 2;", i); + dagadd (cpu, i, 2); + } + else if (op == 1) + { + TRACE_INSN (cpu, "I%i -= 2;", i); + dagsub (cpu, i, 2); + } + else if (op == 2) + { + TRACE_INSN (cpu, "I%i += 4;", i); + dagadd (cpu, i, 4); + } + else if (op == 3) + { + TRACE_INSN (cpu, "I%i -= 4;", i); + dagsub (cpu, i, 4); + } + else + illegal_instruction (cpu); +} + +static void +decode_dspLDST_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* dspLDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask); + int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask); + int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask); + int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask); + int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask); + bu32 addr; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dspLDST); + TRACE_EXTRACT (cpu, "%s: aop:%i m:%i i:%i reg:%i", __func__, aop, m, i, reg); + + if (aop == 0 && W == 0 && m == 0) + { + TRACE_INSN (cpu, "R%i = [I%i++];", reg, i); + addr = IREG (i); + if (DIS_ALGN_EXPT & 0x1) + addr &= ~3; + dagadd (cpu, i, 4); + STORE (DREG (reg), GET_LONG (addr)); + } + else if (aop == 0 && W == 0 && m == 1) + { + TRACE_INSN (cpu, "R%i.L = W[I%i++];", reg, i); + addr = IREG (i); + dagadd (cpu, i, 2); + STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | GET_WORD (addr)); + } + else if (aop == 0 && W == 0 && m == 2) + { + TRACE_INSN (cpu, "R%i.H = W[I%i++];", reg, i); + addr = IREG (i); + dagadd (cpu, i, 2); + STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (GET_WORD (addr) << 16)); + } + else if (aop == 1 && W == 0 && m == 0) + { + TRACE_INSN (cpu, "R%i = [I%i--];", reg, i); + addr = IREG (i); + if (DIS_ALGN_EXPT & 0x1) + addr &= ~3; + dagsub (cpu, i, 4); + STORE (DREG (reg), GET_LONG (addr)); + } + else if (aop == 1 && W == 0 && m == 1) + { + TRACE_INSN (cpu, "R%i.L = W[I%i--];", reg, i); + addr = IREG (i); + dagsub (cpu, i, 2); + STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | GET_WORD (addr)); + } + else if (aop == 1 && W == 0 && m == 2) + { + TRACE_INSN (cpu, "R%i.H = W[I%i--];", reg, i); + addr = IREG (i); + dagsub (cpu, i, 2); + STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (GET_WORD (addr) << 16)); + } + else if (aop == 2 && W == 0 && m == 0) + { + TRACE_INSN (cpu, "R%i = [I%i];", reg, i); + addr = IREG (i); + if (DIS_ALGN_EXPT & 0x1) + addr &= ~3; + STORE (DREG (reg), GET_LONG (addr)); + } + else if (aop == 2 && W == 0 && m == 1) + { + TRACE_INSN (cpu, "R%i.L = W[I%i];", reg, i); + addr = IREG (i); + STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | GET_WORD (addr)); + } + else if (aop == 2 && W == 0 && m == 2) + { + TRACE_INSN (cpu, "R%i.H = W[I%i];", reg, i); + addr = IREG (i); + STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (GET_WORD (addr) << 16)); + } + else if (aop == 0 && W == 1 && m == 0) + { + TRACE_INSN (cpu, "[I%i++] = R%i;", i, reg); + addr = IREG (i); + dagadd (cpu, i, 4); + PUT_LONG (addr, DREG (reg)); + } + else if (aop == 0 && W == 1 && m == 1) + { + TRACE_INSN (cpu, "W[I%i++] = R%i.L;", i, reg); + addr = IREG (i); + dagadd (cpu, i, 2); + PUT_WORD (addr, DREG (reg)); + } + else if (aop == 0 && W == 1 && m == 2) + { + TRACE_INSN (cpu, "W[I%i++] = R%i.H;", i, reg); + addr = IREG (i); + dagadd (cpu, i, 2); + PUT_WORD (addr, DREG (reg) >> 16); + } + else if (aop == 1 && W == 1 && m == 0) + { + TRACE_INSN (cpu, "[I%i--] = R%i;", i, reg); + addr = IREG (i); + dagsub (cpu, i, 4); + PUT_LONG (addr, DREG (reg)); + } + else if (aop == 1 && W == 1 && m == 1) + { + TRACE_INSN (cpu, "W[I%i--] = R%i.L;", i, reg); + addr = IREG (i); + dagsub (cpu, i, 2); + PUT_WORD (addr, DREG (reg)); + } + else if (aop == 1 && W == 1 && m == 2) + { + TRACE_INSN (cpu, "W[I%i--] = R%i.H;", i, reg); + addr = IREG (i); + dagsub (cpu, i, 2); + PUT_WORD (addr, DREG (reg) >> 16); + } + else if (aop == 2 && W == 1 && m == 0) + { + TRACE_INSN (cpu, "[I%i] = R%i;", i, reg); + addr = IREG (i); + PUT_LONG (addr, DREG (reg)); + } + else if (aop == 2 && W == 1 && m == 1) + { + TRACE_INSN (cpu, "W[I%i] = R%i.L;", i, reg); + addr = IREG (i); + PUT_WORD (addr, DREG (reg)); + } + else if (aop == 2 && W == 1 && m == 2) + { + TRACE_INSN (cpu, "W[I%i] = R%i.H;", i, reg); + addr = IREG (i); + PUT_WORD (addr, DREG (reg) >> 16); + } + else if (aop == 3 && W == 0) + { + TRACE_INSN (cpu, "R%i = [I%i ++ M%i];", reg, i, m); + addr = IREG (i); + if (DIS_ALGN_EXPT & 0x1) + addr &= ~3; + dagadd (cpu, i, MREG (m)); + STORE (DREG (reg), GET_LONG (addr)); + } + else if (aop == 3 && W == 1) + { + TRACE_INSN (cpu, "[I%i ++ M%i] = R%i;", i, m, reg); + addr = IREG (i); + dagadd (cpu, i, MREG (m)); + PUT_LONG (addr, DREG (reg)); + } + else + illegal_instruction (cpu); +} + +static void +decode_LDST_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* LDST + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask); + int W = ((iw0 >> LDST_W_bits) & LDST_W_mask); + int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask); + int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask); + int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask); + int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask); + const char * const posts[] = { "++", "--", "" }; + const char *post = posts[aop]; + const char *ptr_name = get_preg_name (ptr); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDST); + TRACE_EXTRACT (cpu, "%s: sz:%i W:%i aop:%i Z:%i ptr:%i reg:%i", + __func__, sz, W, aop, Z, ptr, reg); + + if (aop == 3) + illegal_instruction (cpu); + + if (W == 0) + { + if (sz == 0 && Z == 0) + { + TRACE_INSN (cpu, "R%i = [%s%s];", reg, ptr_name, post); + SET_DREG (reg, GET_LONG (PREG (ptr))); + } + else if (sz == 0 && Z == 1) + { + TRACE_INSN (cpu, "%s = [%s%s];", get_preg_name (reg), ptr_name, post); + if (aop < 2 && ptr == reg) + illegal_instruction_combination (cpu); + SET_PREG (reg, GET_LONG (PREG (ptr))); + } + else if (sz == 1 && Z == 0) + { + TRACE_INSN (cpu, "R%i = W[%s%s] (Z);", reg, ptr_name, post); + SET_DREG (reg, GET_WORD (PREG (ptr))); + } + else if (sz == 1 && Z == 1) + { + TRACE_INSN (cpu, "R%i = W[%s%s] (X);", reg, ptr_name, post); + SET_DREG (reg, (bs32) (bs16) GET_WORD (PREG (ptr))); + } + else if (sz == 2 && Z == 0) + { + TRACE_INSN (cpu, "R%i = B[%s%s] (Z);", reg, ptr_name, post); + SET_DREG (reg, GET_BYTE (PREG (ptr))); + } + else if (sz == 2 && Z == 1) + { + TRACE_INSN (cpu, "R%i = B[%s%s] (X);", reg, ptr_name, post); + SET_DREG (reg, (bs32) (bs8) GET_BYTE (PREG (ptr))); + } + else + illegal_instruction (cpu); + } + else + { + if (sz == 0 && Z == 0) + { + TRACE_INSN (cpu, "[%s%s] = R%i;", ptr_name, post, reg); + PUT_LONG (PREG (ptr), DREG (reg)); + } + else if (sz == 0 && Z == 1) + { + TRACE_INSN (cpu, "[%s%s] = %s;", ptr_name, post, get_preg_name (reg)); + PUT_LONG (PREG (ptr), PREG (reg)); + } + else if (sz == 1 && Z == 0) + { + TRACE_INSN (cpu, "W[%s%s] = R%i;", ptr_name, post, reg); + PUT_WORD (PREG (ptr), DREG (reg)); + } + else if (sz == 2 && Z == 0) + { + TRACE_INSN (cpu, "B[%s%s] = R%i;", ptr_name, post, reg); + PUT_BYTE (PREG (ptr), DREG (reg)); + } + else + illegal_instruction (cpu); + } + + if (aop == 0) + SET_PREG (ptr, PREG (ptr) + (1 << (2 - sz))); + if (aop == 1) + SET_PREG (ptr, PREG (ptr) - (1 << (2 - sz))); +} + +static void +decode_LDSTiiFP_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* LDSTiiFP + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + /* This isn't exactly a grp:reg as this insn only supports Dregs & Pregs, + but for our usage, its functionality the same thing. */ + int grp = ((iw0 >> 3) & 0x1); + int reg = ((iw0 >> LDSTiiFP_reg_bits) & 0x7 /*LDSTiiFP_reg_mask*/); + int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask); + int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask); + bu32 imm = negimm5s4 (offset); + bu32 ea = FPREG + imm; + const char *imm_str = negimm5s4_str (offset); + const char *reg_name = get_allreg_name (grp, reg); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTiiFP); + TRACE_EXTRACT (cpu, "%s: W:%i offset:%#x grp:%i reg:%i", __func__, + W, offset, grp, reg); + TRACE_DECODE (cpu, "%s: negimm5s4:%#x", __func__, imm); + + if (W == 0) + { + TRACE_INSN (cpu, "%s = [FP + %s];", reg_name, imm_str); + reg_write (cpu, grp, reg, GET_LONG (ea)); + } + else + { + TRACE_INSN (cpu, "[FP + %s] = %s;", imm_str, reg_name); + PUT_LONG (ea, reg_read (cpu, grp, reg)); + } +} + +static void +decode_LDSTii_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* LDSTii + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask); + int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask); + int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask); + int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask); + int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask); + bu32 imm, ea; + const char *imm_str; + const char *ptr_name = get_preg_name (ptr); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTii); + TRACE_EXTRACT (cpu, "%s: W:%i op:%i offset:%#x ptr:%i reg:%i", + __func__, W, op, offset, ptr, reg); + + if (op == 0 || op == 3) + imm = uimm4s4 (offset), imm_str = uimm4s4_str (offset); + else + imm = uimm4s2 (offset), imm_str = uimm4s2_str (offset); + ea = PREG (ptr) + imm; + + TRACE_DECODE (cpu, "%s: uimm4s4/uimm4s2:%#x", __func__, imm); + + if (W == 1 && op == 2) + illegal_instruction (cpu); + + if (W == 0) + { + if (op == 0) + { + TRACE_INSN (cpu, "R%i = [%s + %s];", reg, ptr_name, imm_str); + SET_DREG (reg, GET_LONG (ea)); + } + else if (op == 1) + { + TRACE_INSN (cpu, "R%i = W[%s + %s] (Z);", reg, ptr_name, imm_str); + SET_DREG (reg, GET_WORD (ea)); + } + else if (op == 2) + { + TRACE_INSN (cpu, "R%i = W[%s + %s] (X);", reg, ptr_name, imm_str); + SET_DREG (reg, (bs32) (bs16) GET_WORD (ea)); + } + else if (op == 3) + { + TRACE_INSN (cpu, "%s = [%s + %s];", + get_preg_name (reg), ptr_name, imm_str); + SET_PREG (reg, GET_LONG (ea)); + } + } + else + { + if (op == 0) + { + TRACE_INSN (cpu, "[%s + %s] = R%i;", ptr_name, imm_str, reg); + PUT_LONG (ea, DREG (reg)); + } + else if (op == 1) + { + TRACE_INSN (cpu, "W[%s + %s] = R%i;", ptr_name, imm_str, reg); + PUT_WORD (ea, DREG (reg)); + } + else if (op == 3) + { + TRACE_INSN (cpu, "[%s + %s] = %s;", + ptr_name, imm_str, get_preg_name (reg)); + PUT_LONG (ea, PREG (reg)); + } + } +} + +static void +decode_LoopSetup_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc) +{ + /* LoopSetup + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......| + |.reg...........| - | - |.eoffset...............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask); + int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask); + int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask); + int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask); + int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask); + int spcrel = pcrel4 (soffset); + int epcrel = lppcrel10 (eoffset); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LoopSetup); + TRACE_EXTRACT (cpu, "%s: rop:%i c:%i soffset:%i reg:%i eoffset:%i", + __func__, rop, c, soffset, reg, eoffset); + TRACE_DECODE (cpu, "%s: s_pcrel4:%#x e_lppcrel10:%#x", + __func__, spcrel, epcrel); + + if (reg > 7) + illegal_instruction (cpu); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + if (rop == 0) + { + TRACE_INSN (cpu, "LSETUP (%#x, %#x) LC%i;", spcrel, epcrel, c); + } + else if (rop == 1 && reg <= 7) + { + TRACE_INSN (cpu, "LSETUP (%#x, %#x) LC%i = %s;", + spcrel, epcrel, c, get_preg_name (reg)); + SET_LCREG (c, PREG (reg)); + } + else if (rop == 3 && reg <= 7) + { + TRACE_INSN (cpu, "LSETUP (%#x, %#x) LC%i = %s >> 1;", + spcrel, epcrel, c, get_preg_name (reg)); + SET_LCREG (c, PREG (reg) >> 1); + } + else + illegal_instruction (cpu); + + SET_LTREG (c, pc + spcrel); + SET_LBREG (c, pc + epcrel); +} + +static void +decode_LDIMMhalf_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* LDIMMhalf + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......| + |.hword.........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask); + int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask); + int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask); + int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask); + int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask); + int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask); + bu32 val; + const char *val_str; + const char *reg_name = get_allreg_name (grp, reg); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDIMMhalf); + TRACE_EXTRACT (cpu, "%s: Z:%i H:%i S:%i grp:%i reg:%i hword:%#x", + __func__, Z, H, S, grp, reg, hword); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + if (S == 1) + val = imm16 (hword), val_str = imm16_str (hword); + else + val = luimm16 (hword), val_str = luimm16_str (hword); + + if (H == 0 && S == 1 && Z == 0) + { + TRACE_INSN (cpu, "%s = %s (X);", reg_name, val_str); + } + else if (H == 0 && S == 0 && Z == 1) + { + TRACE_INSN (cpu, "%s = %s (Z);", reg_name, val_str); + } + else if (H == 0 && S == 0 && Z == 0) + { + TRACE_INSN (cpu, "%s.L = %s;", reg_name, val_str); + val = REG_H_L (reg_read (cpu, grp, reg), val); + } + else if (H == 1 && S == 0 && Z == 0) + { + TRACE_INSN (cpu, "%s.H = %s;", reg_name, val_str); + val = REG_H_L (val << 16, reg_read (cpu, grp, reg)); + } + else + illegal_instruction (cpu); + + reg_write (cpu, grp, reg, val); +} + +static void +decode_CALLa_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc) +{ + /* CALLa + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................| + |.lsw...........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask); + int lsw = ((iw1 >> 0) & 0xffff); + int msw = ((iw0 >> 0) & 0xff); + int pcrel = pcrel24 ((msw << 16) | lsw); + bu32 newpc = pc + pcrel; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CALLa); + TRACE_EXTRACT (cpu, "%s: S:%i msw:%#x lsw:%#x", __func__, S, msw, lsw); + TRACE_DECODE (cpu, "%s: pcrel24:%#x", __func__, pcrel); + + TRACE_INSN (cpu, "%s %#x;", S ? "CALL" : "JUMP.L", pcrel); + + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + + if (S == 1) + { + TRACE_BRANCH (cpu, pc, newpc, -1, "CALL"); + SET_RETSREG (hwloop_get_next_pc (cpu, pc, 4)); + } + else + TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.L"); + + SET_PCREG (newpc); + BFIN_CPU_STATE.did_jump = true; + PROFILE_BRANCH_TAKEN (cpu); + CYCLE_DELAY = 5; +} + +static void +decode_LDSTidxI_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* LDSTidxI + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......| + |.offset........................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask); + int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask); + int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask); + int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask); + int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask); + int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask); + const char *ptr_name = get_preg_name (ptr); + bu32 imm_16s4 = imm16s4 (offset); + bu32 imm_16s2 = imm16s2 (offset); + bu32 imm_16 = imm16 (offset); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTidxI); + TRACE_EXTRACT (cpu, "%s: W:%i Z:%i sz:%i ptr:%i reg:%i offset:%#x", + __func__, W, Z, sz, ptr, reg, offset); + + if (sz == 3) + illegal_instruction (cpu); + + if (W == 0) + { + if (sz == 0 && Z == 0) + { + TRACE_INSN (cpu, "R%i = [%s + %s];", + reg, ptr_name, imm16s4_str (offset)); + SET_DREG (reg, GET_LONG (PREG (ptr) + imm_16s4)); + } + else if (sz == 0 && Z == 1) + { + TRACE_INSN (cpu, "%s = [%s + %s];", + get_preg_name (reg), ptr_name, imm16s4_str (offset)); + SET_PREG (reg, GET_LONG (PREG (ptr) + imm_16s4)); + } + else if (sz == 1 && Z == 0) + { + TRACE_INSN (cpu, "R%i = W[%s + %s] (Z);", + reg, ptr_name, imm16s2_str (offset)); + SET_DREG (reg, GET_WORD (PREG (ptr) + imm_16s2)); + } + else if (sz == 1 && Z == 1) + { + TRACE_INSN (cpu, "R%i = W[%s + %s] (X);", + reg, ptr_name, imm16s2_str (offset)); + SET_DREG (reg, (bs32) (bs16) GET_WORD (PREG (ptr) + imm_16s2)); + } + else if (sz == 2 && Z == 0) + { + TRACE_INSN (cpu, "R%i = B[%s + %s] (Z);", + reg, ptr_name, imm16_str (offset)); + SET_DREG (reg, GET_BYTE (PREG (ptr) + imm_16)); + } + else if (sz == 2 && Z == 1) + { + TRACE_INSN (cpu, "R%i = B[%s + %s] (X);", + reg, ptr_name, imm16_str (offset)); + SET_DREG (reg, (bs32) (bs8) GET_BYTE (PREG (ptr) + imm_16)); + } + } + else + { + if (sz != 0 && Z != 0) + illegal_instruction (cpu); + + if (sz == 0 && Z == 0) + { + TRACE_INSN (cpu, "[%s + %s] = R%i;", ptr_name, + imm16s4_str (offset), reg); + PUT_LONG (PREG (ptr) + imm_16s4, DREG (reg)); + } + else if (sz == 0 && Z == 1) + { + TRACE_INSN (cpu, "[%s + %s] = %s;", + ptr_name, imm16s4_str (offset), get_preg_name (reg)); + PUT_LONG (PREG (ptr) + imm_16s4, PREG (reg)); + } + else if (sz == 1 && Z == 0) + { + TRACE_INSN (cpu, "W[%s + %s] = R%i;", + ptr_name, imm16s2_str (offset), reg); + PUT_WORD (PREG (ptr) + imm_16s2, DREG (reg)); + } + else if (sz == 2 && Z == 0) + { + TRACE_INSN (cpu, "B[%s + %s] = R%i;", + ptr_name, imm16_str (offset), reg); + PUT_BYTE (PREG (ptr) + imm_16, DREG (reg)); + } + } +} + +static void +decode_linkage_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* linkage + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.| + |.framesize.....................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask); + int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask); + bu32 sp; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_linkage); + TRACE_EXTRACT (cpu, "%s: R:%i framesize:%#x", __func__, R, framesize); + + if (R == 0) + { + int size = uimm16s4 (framesize); + sp = SPREG; + TRACE_INSN (cpu, "LINK %s;", uimm16s4_str (framesize)); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + sp -= 4; + PUT_LONG (sp, RETSREG); + sp -= 4; + PUT_LONG (sp, FPREG); + SET_FPREG (sp); + sp -= size; + CYCLE_DELAY = 3; + } + else + { + /* Restore SP from FP. */ + sp = FPREG; + TRACE_INSN (cpu, "UNLINK;"); + if (INSN_LEN == 8) + illegal_instruction_combination (cpu); + SET_FPREG (GET_LONG (sp)); + sp += 4; + SET_RETSREG (GET_LONG (sp)); + sp += 4; + CYCLE_DELAY = 2; + } + + SET_SPREG (sp); +} + +static void +decode_dsp32mac_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* dsp32mac + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int M = ((iw0 >> (DSP32Mac_M_bits - 16)) & DSP32Mac_M_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + bu32 res = DREG (dst); + bu32 v_i = 0, zero = 0, n_1 = 0, n_0 = 0; + + static const char * const ops[] = { "=", "+=", "-=" }; + char _buf[128], *buf = _buf; + int _MM = MM; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32mac); + TRACE_EXTRACT (cpu, "%s: M:%i mmod:%i MM:%i P:%i w1:%i op1:%i h01:%i h11:%i " + "w0:%i op0:%i h00:%i h10:%i dst:%i src0:%i src1:%i", + __func__, M, mmod, MM, P, w1, op1, h01, h11, w0, op0, h00, h10, + dst, src0, src1); + + if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3) + illegal_instruction (cpu); + + if ((w1 || w0) && mmod == M_W32) + illegal_instruction (cpu); + + if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) + illegal_instruction (cpu); + + /* First handle MAC1 side. */ + if (w1 == 1 || op1 != 3) + { + bu32 res1 = decode_macfunc (cpu, 1, op1, h01, h11, src0, + src1, mmod, MM, P, &v_i, &n_1); + + if (w1) + buf += sprintf (buf, P ? "R%i" : "R%i.H", dst + P); + + if (op1 == 3) + { + buf += sprintf (buf, " = A1"); + zero = !!(res1 == 0); + } + else + { + if (w1) + buf += sprintf (buf, " = ("); + buf += sprintf (buf, "A1 %s R%i.%c * R%i.%c", ops[op1], + src0, h01 ? 'H' : 'L', + src1, h11 ? 'H' : 'L'); + if (w1) + buf += sprintf (buf, ")"); + } + + if (w1) + { + if (P) + STORE (DREG (dst + 1), res1); + else + { + if (res1 & 0xffff0000) + illegal_instruction (cpu); + res = REG_H_L (res1 << 16, res); + } + } + + if (w0 == 1 || op0 != 3) + { + if (_MM) + buf += sprintf (buf, " (M)"); + _MM = 0; + buf += sprintf (buf, ", "); + } + } + + /* Then handle MAC0 side. */ + if (w0 == 1 || op0 != 3) + { + bu32 res0 = decode_macfunc (cpu, 0, op0, h00, h10, src0, + src1, mmod, 0, P, &v_i, &n_0); + + if (w0) + buf += sprintf (buf, P ? "R%i" : "R%i.L", dst); + + if (op0 == 3) + { + buf += sprintf (buf, " = A0"); + zero |= !!(res0 == 0); + } + else + { + if (w0) + buf += sprintf (buf, " = ("); + buf += sprintf (buf, "A0 %s R%i.%c * R%i.%c", ops[op0], + src0, h00 ? 'H' : 'L', + src1, h10 ? 'H' : 'L'); + if (w0) + buf += sprintf (buf, ")"); + } + + if (w0) + { + if (P) + STORE (DREG (dst), res0); + else + { + if (res0 & 0xffff0000) + illegal_instruction (cpu); + res = REG_H_L (res, res0); + } + } + } + + TRACE_INSN (cpu, "%s%s;", _buf, mac_optmode (mmod, _MM)); + + if (!P && (w0 || w1)) + { + STORE (DREG (dst), res); + SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + } + else if (P) + { + SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + } + + if ((w0 == 1 && op0 == 3) || (w1 == 1 && op1 == 3)) + { + SET_ASTATREG (az, zero); + if (!(w0 == 1 && op0 == 3)) + n_0 = 0; + if (!(w1 == 1 && op1 == 3)) + n_1 = 0; + SET_ASTATREG (an, n_1 | n_0); + } +} + +static void +decode_dsp32mult_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* dsp32mult + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...| + |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask); + int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask); + int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask); + int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask); + int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask); + int M = ((iw0 >> (DSP32Mac_M_bits - 16)) & DSP32Mac_M_mask); + int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask); + int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask); + int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask); + int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask); + int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); + int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask); + int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask); + int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask); + int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask); + + bu32 res = DREG (dst); + bu32 sat0 = 0, sat1 = 0, v_i0 = 0, v_i1 = 0; + char _buf[128], *buf = _buf; + int _MM = MM; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32mult); + TRACE_EXTRACT (cpu, "%s: M:%i mmod:%i MM:%i P:%i w1:%i op1:%i h01:%i h11:%i " + "w0:%i op0:%i h00:%i h10:%i dst:%i src0:%i src1:%i", + __func__, M, mmod, MM, P, w1, op1, h01, h11, w0, op0, h00, h10, + dst, src0, src1); + + if (w1 == 0 && w0 == 0) + illegal_instruction (cpu); + if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0) + illegal_instruction (cpu); + if (P && ((dst & 1) || (op1 != 0) || (op0 != 0) || !is_macmod_pmove (mmod))) + illegal_instruction (cpu); + if (!P && ((op1 != 0) || (op0 != 0) || !is_macmod_hmove (mmod))) + illegal_instruction (cpu); + + /* First handle MAC1 side. */ + if (w1) + { + bu64 r = decode_multfunc (cpu, h01, h11, src0, src1, mmod, MM, &sat1); + bu32 res1 = extract_mult (cpu, r, mmod, MM, P, &v_i1); + + buf += sprintf (buf, P ? "R%i" : "R%i.H", dst + P); + buf += sprintf (buf, " = R%i.%c * R%i.%c", + src0, h01 ? 'H' : 'L', + src1, h11 ? 'H' : 'L'); + if (w0) + { + if (_MM) + buf += sprintf (buf, " (M)"); + _MM = 0; + buf += sprintf (buf, ", "); + } + + if (P) + STORE (DREG (dst + 1), res1); + else + { + if (res1 & 0xFFFF0000) + illegal_instruction (cpu); + res = REG_H_L (res1 << 16, res); + } + } + + /* First handle MAC0 side. */ + if (w0) + { + bu64 r = decode_multfunc (cpu, h00, h10, src0, src1, mmod, 0, &sat0); + bu32 res0 = extract_mult (cpu, r, mmod, 0, P, &v_i0); + + buf += sprintf (buf, P ? "R%i" : "R%i.L", dst); + buf += sprintf (buf, " = R%i.%c * R%i.%c", + src0, h01 ? 'H' : 'L', + src1, h11 ? 'H' : 'L'); + + if (P) + STORE (DREG (dst), res0); + else + { + if (res0 & 0xFFFF0000) + illegal_instruction (cpu); + res = REG_H_L (res, res0); + } + } + + TRACE_INSN (cpu, "%s%s;", _buf, mac_optmode (mmod, _MM)); + + if (!P && (w0 || w1)) + STORE (DREG (dst), res); + + if (w0 || w1) + { + bu32 v = sat0 | sat1 | v_i0 | v_i1; + + STORE (ASTATREG (v), v); + STORE (ASTATREG (v_copy), v); + if (v) + STORE (ASTATREG (vs), v); + } +} + +static void +decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* dsp32alu + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............| + |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask); + int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask); + int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask); + int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask); + int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask); + int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask); + int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask); + int M = ((iw0 >> (DSP32Alu_M_bits - 16)) & DSP32Alu_M_mask); + int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask); + int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32alu); + TRACE_EXTRACT (cpu, "%s: M:%i HL:%i aopcde:%i aop:%i s:%i x:%i dst0:%i " + "dst1:%i src0:%i src1:%i", + __func__, M, HL, aopcde, aop, s, x, dst0, dst1, src0, src1); + + if ((aop == 0 || aop == 2) && aopcde == 9 && HL == 0 && s == 0) + { + int a = aop >> 1; + TRACE_INSN (cpu, "A%i.L = R%i.L;", a, src0); + SET_AWREG (a, REG_H_L (AWREG (a), DREG (src0))); + } + else if ((aop == 0 || aop == 2) && aopcde == 9 && HL == 1 && s == 0) + { + int a = aop >> 1; + TRACE_INSN (cpu, "A%i.H = R%i.H;", a, src0); + SET_AWREG (a, REG_H_L (DREG (src0), AWREG (a))); + } + else if ((aop == 1 || aop == 0) && aopcde == 5) + { + bs32 val0 = DREG (src0); + bs32 val1 = DREG (src1); + bs32 res; + bs32 signRes; + bs32 ovX, sBit1, sBit2, sBitRes1, sBitRes2; + + TRACE_INSN (cpu, "R%i.%s = R%i %s R%i (RND12)", dst0, HL ? "L" : "H", + src0, aop & 0x1 ? "-" : "+", src1); + + /* If subtract, just invert and add one. */ + if (aop & 0x1) + { + if (val1 == 0x80000000) + val1 = 0x7FFFFFFF; + else + val1 = ~val1 + 1; + } + + /* Get the sign bits, since we need them later. */ + sBit1 = !!(val0 & 0x80000000); + sBit2 = !!(val1 & 0x80000000); + + res = val0 + val1; + + sBitRes1 = !!(res & 0x80000000); + /* Round to the 12th bit. */ + res += 0x0800; + sBitRes2 = !!(res & 0x80000000); + + signRes = res; + signRes >>= 27; + + /* Overflow if + pos + pos = neg + neg + neg = pos + positive_res + positive_round = neg + Shift and upper 4 bits where not the same. */ + if ((!(sBit1 ^ sBit2) && (sBit1 ^ sBitRes1)) + || (!sBit1 && !sBit2 && sBitRes2) + || ((signRes != 0) && (signRes != -1))) + { + /* Both X1 and X2 Neg res is neg overflow. */ + if (sBit1 && sBit2) + res = 0x80000000; + /* Both X1 and X2 Pos res is pos overflow. */ + else if (!sBit1 && !sBit2) + res = 0x7FFFFFFF; + /* Pos+Neg or Neg+Pos take the sign of the result. */ + else if (sBitRes1) + res = 0x80000000; + else + res = 0x7FFFFFFF; + + ovX = 1; + } + else + { + /* Shift up now after overflow detection. */ + ovX = 0; + res <<= 4; + } + + res >>= 16; + + if (HL) + STORE (DREG (dst0), REG_H_L (res << 16, DREG (dst0))); + else + STORE (DREG (dst0), REG_H_L (DREG (dst0), res)); + + SET_ASTATREG (az, res == 0); + SET_ASTATREG (an, res & 0x8000); + SET_ASTATREG (v, ovX); + if (ovX) + SET_ASTATREG (vs, ovX); + } + else if ((aop == 2 || aop == 3) && aopcde == 5) + { + bs32 val0 = DREG (src0); + bs32 val1 = DREG (src1); + bs32 res; + + TRACE_INSN (cpu, "R%i.%s = R%i %s R%i (RND20)", dst0, HL ? "L" : "H", + src0, aop & 0x1 ? "-" : "+", src1); + + /* If subtract, just invert and add one. */ + if (aop & 0x1) + val1 = ~val1 + 1; + + res = (val0 >> 4) + (val1 >> 4) + (((val0 & 0xf) + (val1 & 0xf)) >> 4); + res += 0x8000; + /* Don't sign extend during the shift. */ + res = ((bu32)res >> 16); + + /* Don't worry about overflows, since we are shifting right. */ + + if (HL) + STORE (DREG (dst0), REG_H_L (res << 16, DREG (dst0))); + else + STORE (DREG (dst0), REG_H_L (DREG (dst0), res)); + + SET_ASTATREG (az, res == 0); + SET_ASTATREG (an, res & 0x8000); + SET_ASTATREG (v, 0); + } + else if (aopcde == 2 || aopcde == 3) + { + bu32 s1, s2, val, ac0_i = 0, v_i = 0; + + TRACE_INSN (cpu, "R%i.%c = R%i.%c %c R%i.%c%s;", + dst0, HL ? 'H' : 'L', + src0, aop & 2 ? 'H' : 'L', + aopcde == 2 ? '+' : '-', + src1, aop & 1 ? 'H' : 'L', + amod1 (s, x)); + + s1 = DREG (src0); + s2 = DREG (src1); + if (aop & 1) + s2 >>= 16; + if (aop & 2) + s1 >>= 16; + + if (aopcde == 2) + val = add16 (cpu, s1, s2, &ac0_i, &v_i, 0, 0, s, 0); + else + val = sub16 (cpu, s1, s2, &ac0_i, &v_i, 0, 0, s, 0); + + SET_ASTATREG (ac0, ac0_i); + SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + + if (HL) + SET_DREG_H (dst0, val << 16); + else + SET_DREG_L (dst0, val); + + SET_ASTATREG (an, val & 0x8000); + SET_ASTATREG (az, val == 0); + } + else if ((aop == 0 || aop == 2) && aopcde == 9 && s == 1) + { + int a = aop >> 1; + TRACE_INSN (cpu, "A%i = R%i;", a, src0); + SET_AREG32 (a, DREG (src0)); + } + else if ((aop == 1 || aop == 3) && aopcde == 9 && s == 0) + { + int a = aop >> 1; + TRACE_INSN (cpu, "A%i.X = R%i.L;", a, src0); + SET_AXREG (a, (bs8)DREG (src0)); + } + else if (aop == 3 && aopcde == 11 && (s == 0 || s == 1)) + { + bu64 acc0 = get_extended_acc (cpu, 0); + bu64 acc1 = get_extended_acc (cpu, 1); + bu32 carry = (bu40)acc1 < (bu40)acc0; + bu32 sat = 0; + + TRACE_INSN (cpu, "A0 -= A1%s;", s ? " (W32)" : ""); + + acc0 -= acc1; + if ((bs64)acc0 < -0x8000000000ll) + acc0 = -0x8000000000ull, sat = 1; + else if ((bs64)acc0 >= 0x7fffffffffll) + acc0 = 0x7fffffffffull, sat = 1; + + if (s == 1) + { + /* A0 -= A1 (W32) */ + if (acc0 & (bu64)0x8000000000ll) + acc0 &= 0x80ffffffffll, sat = 1; + else + acc0 &= 0xffffffffll; + } + STORE (AXREG (0), (acc0 >> 32) & 0xff); + STORE (AWREG (0), acc0 & 0xffffffff); + STORE (ASTATREG (az), acc0 == 0); + STORE (ASTATREG (an), !!(acc0 & (bu64)0x8000000000ll)); + STORE (ASTATREG (ac0), carry); + STORE (ASTATREG (ac0_copy), carry); + STORE (ASTATREG (av0), sat); + if (sat) + STORE (ASTATREG (av0s), sat); + } + else if ((aop == 0 || aop == 1) && aopcde == 22) + { + bu32 s0, s0L, s0H, s1, s1L, s1H; + bu32 tmp0, tmp1, i; + const char * const opts[] = { "rndl", "rndh", "tl", "th" }; + + TRACE_INSN (cpu, "R%i = BYTEOP2P (R%i:%i, R%i:%i) (%s%s);", dst0, + src0 + 1, src0, src1 + 1, src1, opts[HL + (aop << 1)], + s ? ", r" : ""); + + s0L = DREG (src0); + s0H = DREG (src0 + 1); + s1L = DREG (src1); + s1H = DREG (src1 + 1); + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (0) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (0) & 3); + } + + i = !aop * 2; + tmp0 = ((((s1 >> 8) & 0xff) + ((s1 >> 0) & 0xff) + + ((s0 >> 8) & 0xff) + ((s0 >> 0) & 0xff) + i) >> 2) & 0xff; + tmp1 = ((((s1 >> 24) & 0xff) + ((s1 >> 16) & 0xff) + + ((s0 >> 24) & 0xff) + ((s0 >> 16) & 0xff) + i) >> 2) & 0xff; + SET_DREG (dst0, (tmp1 << (16 + (HL * 8))) | (tmp0 << (HL * 8))); + } + else if ((aop == 0 || aop == 1) && s == 0 && aopcde == 8) + { + TRACE_INSN (cpu, "A%i = 0;", aop); + SET_AREG (aop, 0); + } + else if (aop == 2 && s == 0 && aopcde == 8) + { + TRACE_INSN (cpu, "A1 = A0 = 0;"); + SET_AREG (0, 0); + SET_AREG (1, 0); + } + else if ((aop == 0 || aop == 1 || aop == 2) && s == 1 && aopcde == 8) + { + bs40 acc0 = get_extended_acc (cpu, 0); + bs40 acc1 = get_extended_acc (cpu, 1); + bu32 sat; + + if (aop == 0 || aop == 1) + TRACE_INSN (cpu, "A%i = A%i (S);", aop, aop); + else + TRACE_INSN (cpu, "A1 = A1 (S), A0 = A0 (S);"); + + if (aop == 0 || aop == 2) + { + sat = 0; + acc0 = saturate_s32 (acc0, &sat); + acc0 |= -(acc0 & 0x80000000ull); + SET_AXREG (0, (acc0 >> 31) & 0xFF); + SET_AWREG (0, acc0 & 0xFFFFFFFF); + SET_ASTATREG (av0, sat); + if (sat) + SET_ASTATREG (av0s, sat); + } + else + acc0 = 1; + + if (aop == 1 || aop == 2) + { + sat = 0; + acc1 = saturate_s32 (acc1, &sat); + acc1 |= -(acc1 & 0x80000000ull); + SET_AXREG (1, (acc1 >> 31) & 0xFF); + SET_AWREG (1, acc1 & 0xFFFFFFFF); + SET_ASTATREG (av1, sat); + if (sat) + SET_ASTATREG (av1s, sat); + } + else + acc1 = 1; + + SET_ASTATREG (az, (acc0 == 0) || (acc1 == 0)); + SET_ASTATREG (an, ((acc0 >> 31) & 1) || ((acc1 >> 31) & 1)); + } + else if (aop == 3 && (s == 0 || s == 1) && aopcde == 8) + { + TRACE_INSN (cpu, "A%i = A%i;", s, !s); + SET_AXREG (s, AXREG (!s)); + SET_AWREG (s, AWREG (!s)); + } + else if (aop == 3 && HL == 0 && aopcde == 16) + { + int i; + bu32 az; + + TRACE_INSN (cpu, "A1 = ABS A1 , A0 = ABS A0;"); + + az = 0; + for (i = 0; i < 2; ++i) + { + bu32 av; + bs40 acc = get_extended_acc (cpu, i); + + if (acc >> 39) + acc = -acc; + av = acc == ((bs40)1 << 39); + if (av) + acc = ((bs40)1 << 39) - 1; + + SET_AREG (i, acc); + SET_ASTATREG (av[i], av); + if (av) + SET_ASTATREG (avs[i], av); + az |= (acc == 0); + } + SET_ASTATREG (az, az); + SET_ASTATREG (an, 0); + } + else if (aop == 0 && aopcde == 23) + { + bu32 s0, s0L, s0H, s1, s1L, s1H; + bs32 tmp0, tmp1; + + TRACE_INSN (cpu, "R%i = BYTEOP3P (R%i:%i, R%i:%i) (%s%s);", dst0, + src0 + 1, src0, src1 + 1, src1, HL ? "HI" : "LO", + s ? ", R" : ""); + + s0L = DREG (src0); + s0H = DREG (src0 + 1); + s1L = DREG (src1); + s1H = DREG (src1 + 1); + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (1) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (1) & 3); + } + + tmp0 = (bs32)(bs16)(s0 >> 0) + ((s1 >> ( 0 + (8 * !HL))) & 0xff); + tmp1 = (bs32)(bs16)(s0 >> 16) + ((s1 >> (16 + (8 * !HL))) & 0xff); + SET_DREG (dst0, (CLAMP (tmp0, 0, 255) << ( 0 + (8 * HL))) | + (CLAMP (tmp1, 0, 255) << (16 + (8 * HL)))); + } + else if ((aop == 0 || aop == 1) && aopcde == 16) + { + bu32 av; + bs40 acc; + + TRACE_INSN (cpu, "A%i = ABS A%i;", HL, aop); + + acc = get_extended_acc (cpu, aop); + if (acc >> 39) + acc = -acc; + av = acc == ((bs40)1 << 39); + if (av) + acc = ((bs40)1 << 39) - 1; + SET_AREG (HL, acc); + + SET_ASTATREG (av[HL], av); + if (av) + SET_ASTATREG (avs[HL], av); + SET_ASTATREG (az, acc == 0); + SET_ASTATREG (an, 0); + } + else if (aop == 3 && aopcde == 12) + { + bs32 res = DREG (src0); + bs32 ovX; + bool sBit_a, sBit_b; + + TRACE_INSN (cpu, "R%i.%s = R%i (RND);", dst0, HL == 0 ? "L" : "H", src0); + TRACE_DECODE (cpu, "R%i.%s = R%i:%#x (RND);", dst0, + HL == 0 ? "L" : "H", src0, res); + + sBit_b = !!(res & 0x80000000); + + res += 0x8000; + sBit_a = !!(res & 0x80000000); + + /* Overflow if the sign bit changed when we rounded. */ + if ((res >> 16) && (sBit_b != sBit_a)) + { + ovX = 1; + if (!sBit_b) + res = 0x7FFF; + else + res = 0x8000; + } + else + { + res = res >> 16; + ovX = 0; + } + + if (!HL) + SET_DREG (dst0, REG_H_L (DREG (dst0), res)); + else + SET_DREG (dst0, REG_H_L (res << 16, DREG (dst0))); + + SET_ASTATREG (az, res == 0); + SET_ASTATREG (an, res < 0); + SET_ASTATREG (v, ovX); + if (ovX) + SET_ASTATREG (vs, ovX); + } + else if (aop == 3 && HL == 0 && aopcde == 15) + { + bu32 hi = (-(bs16)(DREG (src0) >> 16)) << 16; + bu32 lo = (-(bs16)(DREG (src0) & 0xFFFF)) & 0xFFFF; + int v, ac0, ac1; + + TRACE_INSN (cpu, "R%i = -R%i (V);", dst0, src0); + + v = ac0 = ac1 = 0; + + if (hi == 0x80000000) + { + hi = 0x7fff0000; + v = 1; + } + else if (hi == 0) + ac1 = 1; + + if (lo == 0x8000) + { + lo = 0x7fff; + v = 1; + } + else if (lo == 0) + ac0 = 1; + + SET_DREG (dst0, hi | lo); + + SET_ASTATREG (v, v); + if (v) + SET_ASTATREG (vs, 1); + SET_ASTATREG (ac0, ac0); + SET_ASTATREG (ac1, ac1); + setflags_nz_2x16 (cpu, DREG (dst0)); + } + else if (aop == 3 && HL == 0 && aopcde == 14) + { + TRACE_INSN (cpu, "A1 = - A1 , A0 = - A0;"); + + SET_AREG (0, saturate_s40 (-get_extended_acc (cpu, 0))); + SET_AREG (1, saturate_s40 (-get_extended_acc (cpu, 1))); + /* XXX: what ASTAT flags need updating ? */ + } + else if ((aop == 0 || aop == 1) && (HL == 0 || HL == 1) && aopcde == 14) + { + bs40 src_acc = get_extended_acc (cpu, aop); + int v = 0; + + TRACE_INSN (cpu, "A%i = - A%i;", HL, aop); + + SET_AREG (HL, saturate_s40_astat (-src_acc, &v)); + + SET_ASTATREG (az, AWREG (HL) == 0 && AXREG (HL) == 0); + SET_ASTATREG (an, AXREG (HL) >> 7); + if (HL == 0) + { + SET_ASTATREG (ac0, !src_acc); + SET_ASTATREG (av0, v); + if (v) + SET_ASTATREG (av0s, 1); + } + else + { + SET_ASTATREG (ac1, !src_acc); + SET_ASTATREG (av1, v); + if (v) + SET_ASTATREG (av1s, 1); + } + } + else if (aop == 0 && aopcde == 12) + { + bs16 tmp0_hi = DREG (src0) >> 16; + bs16 tmp0_lo = DREG (src0); + bs16 tmp1_hi = DREG (src1) >> 16; + bs16 tmp1_lo = DREG (src1); + + TRACE_INSN (cpu, "R%i.L = R%i.H = SIGN(R%i.H) * R%i.H + SIGN(R%i.L) * R%i.L;", + dst0, dst0, src0, src1, src0, src1); + + if ((tmp0_hi >> 15) & 1) + tmp1_hi = ~tmp1_hi + 1; + + if ((tmp0_lo >> 15) & 1) + tmp1_lo = ~tmp1_lo + 1; + + tmp1_hi = tmp1_hi + tmp1_lo; + + STORE (DREG (dst0), REG_H_L (tmp1_hi << 16, tmp1_hi)); + } + else if (aopcde == 0) + { + bu32 s0 = DREG (src0); + bu32 s1 = DREG (src1); + bu32 s0h = s0 >> 16; + bu32 s0l = s0 & 0xFFFF; + bu32 s1h = s1 >> 16; + bu32 s1l = s1 & 0xFFFF; + bu32 t0, t1; + bu32 ac1_i = 0, ac0_i = 0, v_i = 0, z_i = 0, n_i = 0; + + TRACE_INSN (cpu, "R%i = R%i %c|%c R%i%s;", dst0, src0, + (aop & 2) ? '-' : '+', (aop & 1) ? '-' : '+', src1, + amod0 (s, x)); + if (aop & 2) + t0 = sub16 (cpu, s0h, s1h, &ac1_i, &v_i, &z_i, &n_i, s, 0); + else + t0 = add16 (cpu, s0h, s1h, &ac1_i, &v_i, &z_i, &n_i, s, 0); + + if (aop & 1) + t1 = sub16 (cpu, s0l, s1l, &ac0_i, &v_i, &z_i, &n_i, s, 0); + else + t1 = add16 (cpu, s0l, s1l, &ac0_i, &v_i, &z_i, &n_i, s, 0); + + SET_ASTATREG (ac1, ac1_i); + SET_ASTATREG (ac0, ac0_i); + SET_ASTATREG (az, z_i); + SET_ASTATREG (an, n_i); + SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + + t0 &= 0xFFFF; + t1 &= 0xFFFF; + if (x) + SET_DREG (dst0, (t1 << 16) | t0); + else + SET_DREG (dst0, (t0 << 16) | t1); + } + else if (aop == 1 && aopcde == 12) + { + bs32 val0 = (bs16)(AWREG (0) >> 16) + (bs16)AWREG (0); + bs32 val1 = (bs16)(AWREG (1) >> 16) + (bs16)AWREG (1); + + TRACE_INSN (cpu, "R%i = A1.L + A1.H, R%i = A0.L + A0.H;", dst1, dst0); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + SET_DREG (dst0, val0); + SET_DREG (dst1, val1); + } + else if (aopcde == 1) + { + bu32 d0, d1; + bu32 x0, x1; + bu16 s0L = DREG (src0); + bu16 s0H = DREG (src0) >> 16; + bu16 s1L = DREG (src1); + bu16 s1H = DREG (src1) >> 16; + bu32 v_i = 0, n_i = 0, z_i = 0; + + TRACE_INSN (cpu, "R%i = R%i %s R%i, R%i = R%i %s R%i%s;", + dst1, src0, HL ? "+|-" : "+|+", src1, + dst0, src0, HL ? "-|+" : "-|-", src1, + amod0amod2 (s, x, aop)); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + if (HL == 0) + { + x0 = add16 (cpu, s0H, s1H, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + x1 = add16 (cpu, s0L, s1L, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + d1 = (x0 << 16) | x1; + + x0 = sub16 (cpu, s0H, s1H, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + x1 = sub16 (cpu, s0L, s1L, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + if (x == 0) + d0 = (x0 << 16) | x1; + else + d0 = (x1 << 16) | x0; + } + else + { + x0 = add16 (cpu, s0H, s1H, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + x1 = sub16 (cpu, s0L, s1L, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + d1 = (x0 << 16) | x1; + + x0 = sub16 (cpu, s0H, s1H, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + x1 = add16 (cpu, s0L, s1L, 0, &v_i, &z_i, &n_i, s, aop) & 0xffff; + if (x == 0) + d0 = (x0 << 16) | x1; + else + d0 = (x1 << 16) | x0; + } + SET_ASTATREG (az, z_i); + SET_ASTATREG (an, n_i); + SET_ASTATREG (v, v_i); + if (v_i) + SET_ASTATREG (vs, v_i); + + STORE (DREG (dst0), d0); + STORE (DREG (dst1), d1); + } + else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 11) + { + bs40 acc0 = get_extended_acc (cpu, 0); + bs40 acc1 = get_extended_acc (cpu, 1); + bu32 v, dreg, sat = 0; + bu32 carry = !!((bu40)~acc1 < (bu40)acc0); + + if (aop == 0) + TRACE_INSN (cpu, "R%i = (A0 += A1);", dst0); + else if (aop == 1) + TRACE_INSN (cpu, "R%i.%c = (A0 += A1);", dst0, HL ? 'H' : 'L'); + else + TRACE_INSN (cpu, "A0 += A1%s;", s ? " (W32)" : ""); + + acc0 += acc1; + acc0 = saturate_s40_astat (acc0, &v); + + if (aop == 2 && s == 1) /* A0 += A1 (W32) */ + { + if (acc0 & (bs40)0x8000000000ll) + acc0 &= 0x80ffffffffll; + else + acc0 &= 0xffffffffll; + } + + STORE (AXREG (0), acc0 >> 32); + STORE (AWREG (0), acc0); + SET_ASTATREG (av0, v && acc1); + if (v) + SET_ASTATREG (av0s, v); + + if (aop == 0 || aop == 1) + { + if (aop) /* Dregs_lo = A0 += A1 */ + { + dreg = saturate_s32 (rnd16 (acc0) << 16, &sat); + if (HL) + STORE (DREG (dst0), REG_H_L (dreg, DREG (dst0))); + else + STORE (DREG (dst0), REG_H_L (DREG (dst0), dreg >> 16)); + } + else /* Dregs = A0 += A1 */ + { + dreg = saturate_s32 (acc0, &sat); + STORE (DREG (dst0), dreg); + } + + STORE (ASTATREG (az), dreg == 0); + STORE (ASTATREG (an), !!(dreg & 0x80000000)); + STORE (ASTATREG (ac0), carry); + STORE (ASTATREG (ac0_copy), carry); + STORE (ASTATREG (v), sat); + STORE (ASTATREG (v_copy), sat); + if (sat) + STORE (ASTATREG (vs), sat); + } + else + { + STORE (ASTATREG (az), acc0 == 0); + STORE (ASTATREG (an), !!(acc0 & 0x8000000000ull)); + STORE (ASTATREG (ac0), carry); + STORE (ASTATREG (ac0_copy), carry); + } + } + else if ((aop == 0 || aop == 1) && aopcde == 10) + { + TRACE_INSN (cpu, "R%i.L = A%i.X;", dst0, aop); + SET_DREG_L (dst0, (bs8)AXREG (aop)); + } + else if (aop == 0 && aopcde == 4) + { + TRACE_INSN (cpu, "R%i = R%i + R%i%s;", dst0, src0, src1, amod1 (s, x)); + SET_DREG (dst0, add32 (cpu, DREG (src0), DREG (src1), 1, s)); + } + else if (aop == 1 && aopcde == 4) + { + TRACE_INSN (cpu, "R%i = R%i - R%i%s;", dst0, src0, src1, amod1 (s, x)); + SET_DREG (dst0, sub32 (cpu, DREG (src0), DREG (src1), 1, s, 0)); + } + else if (aop == 2 && aopcde == 4) + { + TRACE_INSN (cpu, "R%i = R%i + R%i, R%i = R%i - R%i%s;", + dst1, src0, src1, dst0, src0, src1, amod1 (s, x)); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + STORE (DREG (dst1), add32 (cpu, DREG (src0), DREG (src1), 1, s)); + STORE (DREG (dst0), sub32 (cpu, DREG (src0), DREG (src1), 1, s, 1)); + } + else if ((aop == 0 || aop == 1) && aopcde == 17) + { + bs40 acc0 = get_extended_acc (cpu, 0); + bs40 acc1 = get_extended_acc (cpu, 1); + bs40 val0, val1, sval0, sval1; + bu32 sat, sat_i; + + TRACE_INSN (cpu, "R%i = A%i + A%i, R%i = A%i - A%i%s", + dst1, !aop, aop, dst0, !aop, aop, amod1 (s, x)); + TRACE_DECODE (cpu, "R%i = A%i:%#"PRIx64" + A%i:%#"PRIx64", " + "R%i = A%i:%#"PRIx64" - A%i:%#"PRIx64"%s", + dst1, !aop, aop ? acc0 : acc1, aop, aop ? acc1 : acc0, + dst0, !aop, aop ? acc0 : acc1, aop, aop ? acc1 : acc0, + amod1 (s, x)); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + val1 = acc0 + acc1; + if (aop) + val0 = acc0 - acc1; + else + val0 = acc1 - acc0; + + sval0 = saturate_s32 (val0, &sat); + sat_i = sat; + sval1 = saturate_s32 (val1, &sat); + sat_i |= sat; + if (s) + { + val0 = sval0; + val1 = sval1; + } + + STORE (DREG (dst0), val0); + STORE (DREG (dst1), val1); + SET_ASTATREG (v, sat_i); + if (sat_i) + SET_ASTATREG (vs, sat_i); + SET_ASTATREG (an, val0 & 0x80000000 || val1 & 0x80000000); + SET_ASTATREG (az, val0 == 0 || val1 == 0); + SET_ASTATREG (ac1, (bu40)~acc0 < (bu40)acc1); + if (aop) + SET_ASTATREG (ac0, !!((bu40)acc1 <= (bu40)acc0)); + else + SET_ASTATREG (ac0, !!((bu40)acc0 <= (bu40)acc1)); + } + else if (aop == 0 && aopcde == 18) + { + bu40 acc0 = get_extended_acc (cpu, 0); + bu40 acc1 = get_extended_acc (cpu, 1); + bu32 s0L = DREG (src0); + bu32 s0H = DREG (src0 + 1); + bu32 s1L = DREG (src1); + bu32 s1H = DREG (src1 + 1); + bu32 s0, s1; + bs16 tmp0, tmp1, tmp2, tmp3; + + /* This instruction is only defined for register pairs R1:0 and R3:2. */ + if (!((src0 == 0 || src0 == 2) && (src1 == 0 || src1 == 2))) + illegal_instruction (cpu); + + TRACE_INSN (cpu, "SAA (R%i:%i, R%i:%i)%s", src0 + 1, src0, + src1 + 1, src1, s ? " (R)" :""); + + /* Bit s determines the order of the two registers from a pair: + if s=0 the low-order bytes come from the low reg in the pair, + and if s=1 the low-order bytes come from the high reg. */ + + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (1) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (1) & 3); + } + + /* Find the absolute difference between pairs, make it + absolute, then add it to the existing accumulator half. */ + /* Byte 0 */ + tmp0 = ((s0 << 24) >> 24) - ((s1 << 24) >> 24); + tmp1 = ((s0 << 16) >> 24) - ((s1 << 16) >> 24); + tmp2 = ((s0 << 8) >> 24) - ((s1 << 8) >> 24); + tmp3 = ((s0 << 0) >> 24) - ((s1 << 0) >> 24); + + tmp0 = (tmp0 < 0) ? -tmp0 : tmp0; + tmp1 = (tmp1 < 0) ? -tmp1 : tmp1; + tmp2 = (tmp2 < 0) ? -tmp2 : tmp2; + tmp3 = (tmp3 < 0) ? -tmp3 : tmp3; + + s0L = saturate_u16 ((bu32)tmp0 + ((acc0 >> 0) & 0xffff), 0); + s0H = saturate_u16 ((bu32)tmp1 + ((acc0 >> 16) & 0xffff), 0); + s1L = saturate_u16 ((bu32)tmp2 + ((acc1 >> 0) & 0xffff), 0); + s1H = saturate_u16 ((bu32)tmp3 + ((acc1 >> 16) & 0xffff), 0); + + STORE (AWREG (0), (s0H << 16) | (s0L & 0xFFFF)); + STORE (AXREG (0), 0); + STORE (AWREG (1), (s1H << 16) | (s1L & 0xFFFF)); + STORE (AXREG (1), 0); + } + else if (aop == 3 && aopcde == 18) + { + TRACE_INSN (cpu, "DISALGNEXCPT"); + DIS_ALGN_EXPT |= 1; + } + else if ((aop == 0 || aop == 1) && aopcde == 20) + { + bu32 s0, s0L, s0H, s1, s1L, s1H; + const char * const opts[] = { "", " (R)", " (T)", " (T, R)" }; + + TRACE_INSN (cpu, "R%i = BYTEOP1P (R%i:%i, R%i:%i)%s;", dst0, + src0 + 1, src0, src1 + 1, src1, opts[s + (aop << 1)]); + + s0L = DREG (src0); + s0H = DREG (src0 + 1); + s1L = DREG (src1); + s1H = DREG (src1 + 1); + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (1) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (1) & 3); + } + + SET_DREG (dst0, + (((((s0 >> 0) & 0xff) + ((s1 >> 0) & 0xff) + !aop) >> 1) << 0) | + (((((s0 >> 8) & 0xff) + ((s1 >> 8) & 0xff) + !aop) >> 1) << 8) | + (((((s0 >> 16) & 0xff) + ((s1 >> 16) & 0xff) + !aop) >> 1) << 16) | + (((((s0 >> 24) & 0xff) + ((s1 >> 24) & 0xff) + !aop) >> 1) << 24)); + } + else if (aop == 0 && aopcde == 21) + { + bu32 s0, s0L, s0H, s1, s1L, s1H; + + TRACE_INSN (cpu, "(R%i, R%i) = BYTEOP16P (R%i:%i, R%i:%i)%s;", dst1, dst0, + src0 + 1, src0, src1 + 1, src1, s ? " (R)" : ""); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + s0L = DREG (src0); + s0H = DREG (src0 + 1); + s1L = DREG (src1); + s1H = DREG (src1 + 1); + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (1) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (1) & 3); + } + + SET_DREG (dst0, + ((((s0 >> 0) & 0xff) + ((s1 >> 0) & 0xff)) << 0) | + ((((s0 >> 8) & 0xff) + ((s1 >> 8) & 0xff)) << 16)); + SET_DREG (dst1, + ((((s0 >> 16) & 0xff) + ((s1 >> 16) & 0xff)) << 0) | + ((((s0 >> 24) & 0xff) + ((s1 >> 24) & 0xff)) << 16)); + } + else if (aop == 1 && aopcde == 21) + { + bu32 s0, s0L, s0H, s1, s1L, s1H; + + TRACE_INSN (cpu, "(R%i, R%i) = BYTEOP16M (R%i:%i, R%i:%i)%s;", dst1, dst0, + src0 + 1, src0, src1 + 1, src1, s ? " (R)" : ""); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + s0L = DREG (src0); + s0H = DREG (src0 + 1); + s1L = DREG (src1); + s1H = DREG (src1 + 1); + if (s) + { + s0 = algn (s0H, s0L, IREG (0) & 3); + s1 = algn (s1H, s1L, IREG (1) & 3); + } + else + { + s0 = algn (s0L, s0H, IREG (0) & 3); + s1 = algn (s1L, s1H, IREG (1) & 3); + } + + SET_DREG (dst0, + (((((s0 >> 0) & 0xff) - ((s1 >> 0) & 0xff)) << 0) & 0xffff) | + (((((s0 >> 8) & 0xff) - ((s1 >> 8) & 0xff)) << 16))); + SET_DREG (dst1, + (((((s0 >> 16) & 0xff) - ((s1 >> 16) & 0xff)) << 0) & 0xffff) | + (((((s0 >> 24) & 0xff) - ((s1 >> 24) & 0xff)) << 16))); + } + else if (aop == 1 && aopcde == 7) + { + TRACE_INSN (cpu, "R%i = MIN (R%i, R%i);", dst0, src0, src1); + SET_DREG (dst0, min32 (cpu, DREG (src0), DREG (src1))); + } + else if (aop == 0 && aopcde == 7) + { + TRACE_INSN (cpu, "R%i = MAX (R%i, R%i);", dst0, src0, src1); + SET_DREG (dst0, max32 (cpu, DREG (src0), DREG (src1))); + } + else if (aop == 2 && aopcde == 7) + { + bu32 val = DREG (src0); + int v; + + TRACE_INSN (cpu, "R%i = ABS R%i;", dst0, src0); + + if (val >> 31) + val = -val; + v = (val == 0x80000000); + if (v) + val = 0x7fffffff; + SET_DREG (dst0, val); + + SET_ASTATREG (v, v); + if (v) + SET_ASTATREG (vs, 1); + setflags_nz (cpu, val); + } + else if (aop == 3 && aopcde == 7) + { + bu32 val = DREG (src0); + + TRACE_INSN (cpu, "R%i = - R%i %s;", dst0, src0, amod1 (s, 0)); + + if (s && val == 0x80000000) + { + val = 0x7fffffff; + SET_ASTATREG (v, 1); + SET_ASTATREG (vs, 1); + } + else if (val == 0x80000000) + val = 0x80000000; + else + val = -val; + SET_DREG (dst0, val); + + SET_ASTATREG (az, val == 0); + SET_ASTATREG (an, val & 0x80000000); + } + else if (aop == 2 && aopcde == 6) + { + bu32 in = DREG (src0); + bu32 hi = (in & 0x80000000 ? (bu32)-(bs16)(in >> 16) : in >> 16) << 16; + bu32 lo = (in & 0x8000 ? (bu32)-(bs16)(in & 0xFFFF) : in) & 0xFFFF; + int v; + + TRACE_INSN (cpu, "R%i = ABS R%i (V);", dst0, src0); + + v = 0; + if (hi == 0x80000000) + { + hi = 0x7fff0000; + v = 1; + } + if (lo == 0x8000) + { + lo = 0x7fff; + v = 1; + } + SET_DREG (dst0, hi | lo); + + SET_ASTATREG (v, v); + if (v) + SET_ASTATREG (vs, 1); + setflags_nz_2x16 (cpu, DREG (dst0)); + } + else if (aop == 1 && aopcde == 6) + { + TRACE_INSN (cpu, "R%i = MIN (R%i, R%i) (V);", dst0, src0, src1); + SET_DREG (dst0, min2x16 (cpu, DREG (src0), DREG (src1))); + } + else if (aop == 0 && aopcde == 6) + { + TRACE_INSN (cpu, "R%i = MAX (R%i, R%i) (V);", dst0, src0, src1); + SET_DREG (dst0, max2x16 (cpu, DREG (src0), DREG (src1))); + } + else if (aop == 0 && aopcde == 24) + { + TRACE_INSN (cpu, "R%i = BYTEPACK (R%i, R%i);", dst0, src0, src1); + SET_DREG (dst0, + (((DREG (src0) >> 0) & 0xff) << 0) | + (((DREG (src0) >> 16) & 0xff) << 8) | + (((DREG (src1) >> 0) & 0xff) << 16) | + (((DREG (src1) >> 16) & 0xff) << 24)); + } + else if (aop == 1 && aopcde == 24) + { + int order, lo, hi; + bu64 comb_src; + bu8 bytea, byteb, bytec, byted; + + TRACE_INSN (cpu, "(R%i, R%i) = BYTEUNPACK R%i:%i%s;", + dst1, dst0, src0 + 1, src0, s ? " (R)" : ""); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + order = IREG (0) & 0x3; + if (s) + hi = src0, lo = src0 + 1; + else + hi = src0 + 1, lo = src0; + comb_src = (((bu64)DREG (hi)) << 32) | DREG (lo); + bytea = (comb_src >> (0 + 8 * order)); + byteb = (comb_src >> (8 + 8 * order)); + bytec = (comb_src >> (16 + 8 * order)); + byted = (comb_src >> (24 + 8 * order)); + SET_DREG (dst0, bytea | ((bu32)byteb << 16)); + SET_DREG (dst1, bytec | ((bu32)byted << 16)); + } + else if (aopcde == 13) + { + const char *searchmodes[] = { "GT", "GE", "LT", "LE" }; + bool up_hi, up_lo; + bs16 a0_lo, a1_lo, src_hi, src_lo; + + TRACE_INSN (cpu, "(R%i, R%i) = SEARCH R%i (%s);", + dst1, dst0, src0, searchmodes[aop]); + + if (dst0 == dst1) + illegal_instruction_combination (cpu); + + up_hi = up_lo = false; + a0_lo = AWREG (0); + a1_lo = AWREG (1); + src_lo = DREG (src0); + src_hi = DREG (src0) >> 16; + + switch (aop) + { + case 0: + up_hi = (src_hi > a1_lo); + up_lo = (src_lo > a0_lo); + break; + case 1: + up_hi = (src_hi >= a1_lo); + up_lo = (src_lo >= a0_lo); + break; + case 2: + up_hi = (src_hi < a1_lo); + up_lo = (src_lo < a0_lo); + break; + case 3: + up_hi = (src_hi <= a1_lo); + up_lo = (src_lo <= a0_lo); + break; + } + + if (up_hi) + { + SET_AREG (1, src_hi); + SET_DREG (dst1, PREG (0)); + } + else + SET_AREG (1, a1_lo); + + if (up_lo) + { + SET_AREG (0, src_lo); + SET_DREG (dst0, PREG (0)); + } + else + SET_AREG (0, a0_lo); + } + else + illegal_instruction (cpu); +} + +static void +decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* dsp32shift + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask); + int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask); + int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask); + int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask); + int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask); + int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask); + int M = ((iw0 >> (DSP32Shift_M_bits - 16)) & DSP32Shift_M_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32shift); + TRACE_EXTRACT (cpu, "%s: M:%i sopcde:%i sop:%i HLs:%i dst0:%i src0:%i src1:%i", + __func__, M, sopcde, sop, HLs, dst0, src0, src1); + + if ((sop == 0 || sop == 1) && sopcde == 0) + { + bu16 val; + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + + TRACE_INSN (cpu, "R%i.%c = ASHIFT R%i.%c BY R%i.L%s;", + dst0, HLs < 2 ? 'L' : 'H', + src1, HLs & 1 ? 'H' : 'L', + src0, sop == 1 ? " (S)" : ""); + + if ((HLs & 1) == 0) + val = (bu16)(DREG (src1) & 0xFFFF); + else + val = (bu16)((DREG (src1) & 0xFFFF0000) >> 16); + + /* Positive shift magnitudes produce Logical Left shifts. + Negative shift magnitudes produce Arithmetic Right shifts. */ + if (shft <= 0) + val = ashiftrt (cpu, val, -shft, 16); + else + val = lshift (cpu, val, shft, 16, sop == 1); + + if ((HLs & 2) == 0) + STORE (DREG (dst0), REG_H_L (DREG (dst0), val)); + else + STORE (DREG (dst0), REG_H_L (val << 16, DREG (dst0))); + } + else if (sop == 2 && sopcde == 0) + { + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + bu16 val; + + TRACE_INSN (cpu, "R%i.%c = LSHIFT R%i.%c BY R%i.L;", + dst0, HLs < 2 ? 'L' : 'H', + src1, HLs & 1 ? 'H' : 'L', src0); + + if ((HLs & 1) == 0) + val = (bu16)(DREG (src1) & 0xFFFF); + else + val = (bu16)((DREG (src1) & 0xFFFF0000) >> 16); + + if (shft < 0) + val = val >> (-1 * shft); + else + val = val << shft; + + if ((HLs & 2) == 0) + SET_DREG (dst0, REG_H_L (DREG (dst0), val)); + else + SET_DREG (dst0, REG_H_L (val << 16, DREG (dst0))); + + SET_ASTATREG (az, !((val & 0xFFFF0000) == 0) || ((val & 0xFFFF) == 0)); + SET_ASTATREG (an, (!!(val & 0x80000000)) ^ (!!(val & 0x8000))); + SET_ASTATREG (v, 0); + } + else if (sop == 2 && sopcde == 3 && (HLs == 1 || HLs == 0)) + { + int shift = imm6 (DREG (src0) & 0xFFFF); + bu32 cc = CCREG; + bu40 acc = get_unextended_acc (cpu, HLs); + + TRACE_INSN (cpu, "A%i = ROT A%i BY R%i.L;", HLs, HLs, src0); + TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i CC:%i", HLs, acc, shift, cc); + + acc = rot40 (acc, shift, &cc); + SET_AREG (HLs, acc); + if (shift) + SET_CCREG (cc); + } + else if (sop == 0 && sopcde == 3 && (HLs == 0 || HLs == 1)) + { + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + bu64 val = get_extended_acc (cpu, HLs); + + HLs = !!HLs; + TRACE_INSN (cpu, "A%i = ASHIFT A%i BY R%i.L;", HLs, HLs, src0); + TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i", HLs, val, shft); + + if (shft <= 0) + val = ashiftrt (cpu, val, -shft, 40); + else + val = lshift (cpu, val, shft, 40, 0); + + STORE (AXREG (HLs), (val >> 32) & 0xff); + STORE (AWREG (HLs), (val & 0xffffffff)); + } + else if (sop == 1 && sopcde == 3 && (HLs == 0 || HLs == 1)) + { + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + bu64 val; + + HLs = !!HLs; + TRACE_INSN (cpu, "A%i = LSHIFT A%i BY R%i.L;", HLs, HLs, src0); + val = get_extended_acc (cpu, HLs); + + if (shft <= 0) + val = lshiftrt (cpu, val, -shft, 40); + else + val = lshift (cpu, val, shft, 40, 0); + + STORE (AXREG (HLs), (val >> 32) & 0xff); + STORE (AWREG (HLs), (val & 0xffffffff)); + } + else if ((sop == 0 || sop == 1) && sopcde == 1) + { + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + bu16 val0, val1; + bu32 astat; + + TRACE_INSN (cpu, "R%i = ASHIFT R%i BY R%i.L (V%s);", + dst0, src1, src0, sop == 1 ? ",S" : ""); + + val0 = (bu16)DREG (src1) & 0xFFFF; + val1 = (bu16)((DREG (src1) & 0xFFFF0000) >> 16); + + if (shft <= 0) + { + val0 = ashiftrt (cpu, val0, -shft, 16); + astat = ASTAT; + val1 = ashiftrt (cpu, val1, -shft, 16); + } + else + { + val0 = lshift (cpu, val0, shft, 16, sop == 1); + astat = ASTAT; + val1 = lshift (cpu, val1, shft, 16, sop == 1); + } + SET_ASTAT (ASTAT | astat); + STORE (DREG (dst0), (val1 << 16) | val0); + } + else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 2) + { + /* dregs = [LA]SHIFT dregs BY dregs_lo (opt_S) */ + /* sop == 1 : opt_S */ + bu32 v = DREG (src1); + /* LSHIFT uses sign extended low 6 bits of dregs_lo. */ + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + + TRACE_INSN (cpu, "R%i = %cSHIFT R%i BY R%i.L%s;", dst0, + shft && sop != 2 ? 'A' : 'L', src1, src0, + sop == 1 ? " (S)" : ""); + + if (shft < 0) + { + if (sop == 2) + STORE (DREG (dst0), lshiftrt (cpu, v, -shft, 32)); + else + STORE (DREG (dst0), ashiftrt (cpu, v, -shft, 32)); + } + else + STORE (DREG (dst0), lshift (cpu, v, shft, 32, sop == 1)); + } + else if (sop == 3 && sopcde == 2) + { + int shift = imm6 (DREG (src0) & 0xFFFF); + bu32 src = DREG (src1); + bu32 ret, cc = CCREG; + + TRACE_INSN (cpu, "R%i = ROT R%i BY R%i.L;", dst0, src1, src0); + TRACE_DECODE (cpu, "R%i:%#x R%i:%#x shift:%i CC:%i", + dst0, DREG (dst0), src1, src, shift, cc); + + ret = rot32 (src, shift, &cc); + STORE (DREG (dst0), ret); + if (shift) + SET_CCREG (cc); + } + else if (sop == 2 && sopcde == 1) + { + bs32 shft = (bs8)(DREG (src0) << 2) >> 2; + bu16 val0, val1; + bu32 astat; + + TRACE_INSN (cpu, "R%i = LSHIFT R%i BY R%i.L (V);", dst0, src1, src0); + + val0 = (bu16)DREG (src1) & 0xFFFF; + val1 = (bu16)((DREG (src1) & 0xFFFF0000) >> 16); + + if (shft <= 0) + { + val0 = lshiftrt (cpu, val0, -shft, 16); + astat = ASTAT; + val1 = lshiftrt (cpu, val1, -shft, 16); + } + else + { + val0 = lshift (cpu, val0, shft, 16, 0); + astat = ASTAT; + val1 = lshift (cpu, val1, shft, 16, 0); + } + SET_ASTAT (ASTAT | astat); + STORE (DREG (dst0), (val1 << 16) | val0); + } + else if (sopcde == 4) + { + bu32 sv0 = DREG (src0); + bu32 sv1 = DREG (src1); + TRACE_INSN (cpu, "R%i = PACK (R%i.%c, R%i.%c);", dst0, + src1, sop & 2 ? 'H' : 'L', + src0, sop & 1 ? 'H' : 'L'); + if (sop & 1) + sv0 >>= 16; + if (sop & 2) + sv1 >>= 16; + SET_DREG (dst0, (sv1 << 16) | (sv0 & 0xFFFF)); + } + else if (sop == 0 && sopcde == 5) + { + bu32 sv1 = DREG (src1); + TRACE_INSN (cpu, "R%i.L = SIGNBITS R%i;", dst0, src1); + SET_DREG_L (dst0, signbits (sv1, 32)); + } + else if (sop == 1 && sopcde == 5) + { + bu32 sv1 = DREG (src1); + TRACE_INSN (cpu, "R%i.L = SIGNBITS R%i.L;", dst0, src1); + SET_DREG_L (dst0, signbits (sv1, 16)); + } + else if (sop == 2 && sopcde == 5) + { + bu32 sv1 = DREG (src1); + TRACE_INSN (cpu, "R%i.L = SIGNBITS R%i.H;", dst0, src1); + SET_DREG_L (dst0, signbits (sv1 >> 16, 16)); + } + else if ((sop == 0 || sop == 1) && sopcde == 6) + { + bu64 acc = AXREG (sop); + TRACE_INSN (cpu, "R%i.L = SIGNBITS A%i;", dst0, sop); + acc <<= 32; + acc |= AWREG (sop); + SET_DREG_L (dst0, signbits (acc, 40) & 0xFFFF); + } + else if (sop == 3 && sopcde == 6) + { + bu32 v = ones (DREG (src1)); + TRACE_INSN (cpu, "R%i.L = ONES R%i;", dst0, src1); + SET_DREG_L (dst0, v); + } + else if (sop == 0 && sopcde == 7) + { + bu16 sv1 = (bu16)signbits (DREG (src1), 32); + bu16 sv0 = (bu16)DREG (src0); + bu16 dst_lo; + + TRACE_INSN (cpu, "R%i.L = EXPADJ (R%i, R%i.L);", dst0, src1, src0); + + if ((sv1 & 0x1f) < (sv0 & 0x1f)) + dst_lo = sv1; + else + dst_lo = sv0; + STORE (DREG (dst0), REG_H_L (DREG (dst0), dst_lo)); + } + else if (sop == 1 && sopcde == 7) + { + /* Exponent adjust on two 16-bit inputs. Select + smallest norm among 3 inputs. */ + bs16 src1_hi = (DREG (src1) & 0xFFFF0000) >> 16; + bs16 src1_lo = (DREG (src1) & 0xFFFF); + bu16 src0_lo = (DREG (src0) & 0xFFFF); + bu16 tmp_hi, tmp_lo, tmp; + + TRACE_INSN (cpu, "R%i.L = EXPADJ (R%i, R%i.L) (V);", dst0, src1, src0); + + tmp_hi = signbits (src1_hi, 16); + tmp_lo = signbits (src1_lo, 16); + + if ((tmp_hi & 0xf) < (tmp_lo & 0xf)) + if ((tmp_hi & 0xf) < (src0_lo & 0xf)) + tmp = tmp_hi; + else + tmp = src0_lo; + else + if ((tmp_lo & 0xf) < (src0_lo & 0xf)) + tmp = tmp_lo; + else + tmp = src0_lo; + STORE (DREG (dst0), REG_H_L (DREG (dst0), tmp)); + } + else if (sop == 2 && sopcde == 7) + { + /* Exponent adjust on single 16-bit register. */ + bu16 tmp; + bu16 src0_lo = (bu16)(DREG (src0) & 0xFFFF); + + TRACE_INSN (cpu, "R%i.L = EXPADJ (R%i.L, R%i.L);", dst0, src1, src0); + + tmp = signbits (DREG (src1) & 0xFFFF, 16); + + if ((tmp & 0xf) < (src0_lo & 0xf)) + SET_DREG_L (dst0, tmp); + else + SET_DREG_L (dst0, src0_lo); + } + else if (sop == 3 && sopcde == 7) + { + bu16 tmp; + bu16 src0_lo = (bu16)(DREG (src0) & 0xFFFF); + + TRACE_INSN (cpu, "R%i.L = EXPADJ (R%i.H, R%i.L);", dst0, src1, src0); + + tmp = signbits ((DREG (src1) & 0xFFFF0000) >> 16, 16); + + if ((tmp & 0xf) < (src0_lo & 0xf)) + SET_DREG_L (dst0, tmp); + else + SET_DREG_L (dst0, src0_lo); + } + else if (sop == 0 && sopcde == 8) + { + bu64 acc = get_unextended_acc (cpu, 0); + bu32 s0, s1; + + TRACE_INSN (cpu, "BITMUX (R%i, R%i, A0) (ASR);", src0, src1); + + if (src0 == src1) + illegal_instruction_combination (cpu); + + s0 = DREG (src0); + s1 = DREG (src1); + acc = (acc >> 2) | + (((bu64)s0 & 1) << 38) | + (((bu64)s1 & 1) << 39); + SET_DREG (src0, s0 >> 1); + SET_DREG (src1, s1 >> 1); + + SET_AREG (0, acc); + } + else if (sop == 1 && sopcde == 8) + { + bu64 acc = get_unextended_acc (cpu, 0); + bu32 s0, s1; + + TRACE_INSN (cpu, "BITMUX (R%i, R%i, A0) (ASL);", src0, src1); + + if (src0 == src1) + illegal_instruction_combination (cpu); + + s0 = DREG (src0); + s1 = DREG (src1); + acc = (acc << 2) | + ((s0 >> 31) & 1) | + ((s1 >> 30) & 2); + SET_DREG (src0, s0 << 1); + SET_DREG (src1, s1 << 1); + + SET_AREG (0, acc); + } + else if ((sop == 0 || sop == 1) && sopcde == 9) + { + bs40 acc0 = get_unextended_acc (cpu, 0); + bs16 sL, sH, out; + + TRACE_INSN (cpu, "R%i.L = VIT_MAX (R%i) (AS%c);", + dst0, src1, sop & 1 ? 'R' : 'L'); + + sL = DREG (src1); + sH = DREG (src1) >> 16; + + if (sop & 1) + acc0 = (acc0 & 0xfeffffffffull) >> 1; + else + acc0 <<= 1; + + if (((sH - sL) & 0x8000) == 0) + { + out = sH; + acc0 |= (sop & 1) ? 0x80000000 : 1; + } + else + out = sL; + + SET_AREG (0, acc0); + SET_DREG (dst0, REG_H_L (DREG (dst0), out)); + } + else if ((sop == 2 || sop == 3) && sopcde == 9) + { + bs40 acc0 = get_extended_acc (cpu, 0); + bs16 s0L, s0H, s1L, s1H, out0, out1; + + TRACE_INSN (cpu, "R%i = VIT_MAX (R%i, R%i) (AS%c);", + dst0, src1, src0, sop & 1 ? 'R' : 'L'); + + s0L = DREG (src0); + s0H = DREG (src0) >> 16; + s1L = DREG (src1); + s1H = DREG (src1) >> 16; + + if (sop & 1) + acc0 >>= 2; + else + acc0 <<= 2; + + if (((s0H - s0L) & 0x8000) == 0) + { + out0 = s0H; + acc0 |= (sop & 1) ? 0x40000000 : 2; + } + else + out0 = s0L; + + if (((s1H - s1L) & 0x8000) == 0) + { + out1 = s1H; + acc0 |= (sop & 1) ? 0x80000000 : 1; + } + else + out1 = s1L; + + SET_AREG (0, acc0); + SET_DREG (dst0, REG_H_L (out1 << 16, out0)); + } + else if (sop == 0 && sopcde == 10) + { + bu32 v = DREG (src0); + bu32 x = DREG (src1); + bu32 mask = (1 << (v & 0x1f)) - 1; + TRACE_INSN (cpu, "R%i = EXTRACT (R%i, R%i.L) (Z);", dst0, src1, src0); + x >>= ((v >> 8) & 0x1f); + SET_DREG (dst0, x & mask); + setflags_logical (cpu, DREG (dst0)); + } + else if (sop == 1 && sopcde == 10) + { + bu32 v = DREG (src0); + bu32 x = DREG (src1); + bu32 sgn = (1 << (v & 0x1f)) >> 1; + bu32 mask = (1 << (v & 0x1f)) - 1; + TRACE_INSN (cpu, "R%i = EXTRACT (R%i, R%i.L) (X);", dst0, src1, src0); + x >>= ((v >> 8) & 0x1f); + x &= mask; + if (x & sgn) + x |= ~mask; + SET_DREG (dst0, x); + setflags_logical (cpu, DREG (dst0)); + } + else if ((sop == 2 || sop == 3) && sopcde == 10) + { + /* The first dregs is the "background" while the second dregs is the + "foreground". The fg reg is used to overlay the bg reg and is: + | nnnn nnnn | nnnn nnnn | xxxp pppp | xxxL LLLL | + n = the fg bit field + p = bit position in bg reg to start LSB of fg field + L = number of fg bits to extract + Using (X) sign-extends the fg bit field. */ + bu32 fg = DREG (src0); + bu32 bg = DREG (src1); + bu32 len = fg & 0x1f; + bu32 mask = (1 << MIN (16, len)) - 1; + bu32 fgnd = (fg >> 16) & mask; + int shft = ((fg >> 8) & 0x1f); + + TRACE_INSN (cpu, "R%i = DEPOSIT (R%i, R%i)%s;", dst0, src1, src0, + sop == 3 ? " (X)" : ""); + + if (sop == 3) + { + /* Sign extend the fg bit field. */ + mask = -1; + fgnd = ((bs32)(bs16)(fgnd << (16 - len))) >> (16 - len); + } + fgnd <<= shft; + mask <<= shft; + bg &= ~mask; + + SET_DREG (dst0, bg | fgnd); + setflags_logical (cpu, DREG (dst0)); + } + else if (sop == 0 && sopcde == 11) + { + bu64 acc0 = get_unextended_acc (cpu, 0); + + TRACE_INSN (cpu, "R%i.L = CC = BXORSHIFT (A0, R%i);", dst0, src0); + + acc0 <<= 1; + SET_CCREG (xor_reduce (acc0, DREG (src0))); + SET_DREG (dst0, REG_H_L (DREG (dst0), CCREG)); + SET_AREG (0, acc0); + } + else if (sop == 1 && sopcde == 11) + { + bu64 acc0 = get_unextended_acc (cpu, 0); + + TRACE_INSN (cpu, "R%i.L = CC = BXOR (A0, R%i);", dst0, src0); + + SET_CCREG (xor_reduce (acc0, DREG (src0))); + SET_DREG (dst0, REG_H_L (DREG (dst0), CCREG)); + } + else if (sop == 0 && sopcde == 12) + { + bu64 acc0 = get_unextended_acc (cpu, 0); + bu64 acc1 = get_unextended_acc (cpu, 1); + + TRACE_INSN (cpu, "A0 = BXORSHIFT (A0, A1, CC);"); + + acc0 = (acc0 << 1) | (CCREG ^ xor_reduce (acc0, acc1)); + SET_AREG (0, acc0); + } + else if (sop == 1 && sopcde == 12) + { + bu64 acc0 = get_unextended_acc (cpu, 0); + bu64 acc1 = get_unextended_acc (cpu, 1); + + TRACE_INSN (cpu, "R%i.L = CC = BXOR (A0, A1, CC);", dst0); + + SET_CCREG (CCREG ^ xor_reduce (acc0, acc1)); + acc0 = (acc0 << 1) | CCREG; + SET_DREG (dst0, REG_H_L (DREG (dst0), CCREG)); + } + else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 13) + { + int shift = (sop + 1) * 8; + TRACE_INSN (cpu, "R%i = ALIGN%i (R%i, R%i);", dst0, shift, src1, src0); + SET_DREG (dst0, (DREG (src1) << (32 - shift)) | (DREG (src0) >> shift)); + } + else + illegal_instruction (cpu); +} + +static void +decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) +{ + /* dsp32shiftimm + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............| + |.sop...|.HLs...|.dst0......|.immag.................|.src1......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask); + int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask); + int bit8 = ((iw1 >> 8) & 0x1); + int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask); + int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask); + int M = ((iw0 >> (DSP32ShiftImm_M_bits - 16)) & DSP32ShiftImm_M_mask); + int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask); + int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32shiftimm); + TRACE_EXTRACT (cpu, "%s: M:%i sopcde:%i sop:%i HLs:%i dst0:%i immag:%#x src1:%i", + __func__, M, sopcde, sop, HLs, dst0, immag, src1); + + if (sopcde == 0) + { + bu16 in = DREG (src1) >> ((HLs & 1) ? 16 : 0); + bu16 result; + bu32 v; + + if (sop == 0) + { + TRACE_INSN (cpu, "R%i.%c = R%i.%c >>> %i;", + dst0, (HLs & 2) ? 'H' : 'L', + src1, (HLs & 1) ? 'H' : 'L', newimmag); + result = ashiftrt (cpu, in, newimmag, 16); + } + else if (sop == 1 && bit8 == 0) + { + TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i (S);", + dst0, (HLs & 2) ? 'H' : 'L', + src1, (HLs & 1) ? 'H' : 'L', immag); + result = lshift (cpu, in, immag, 16, 1); + } + else if (sop == 1 && bit8) + { + TRACE_INSN (cpu, "R%i.%c = R%i.%c >>> %i (S);", + dst0, (HLs & 2) ? 'H' : 'L', + src1, (HLs & 1) ? 'H' : 'L', immag); + result = lshift (cpu, in, immag, 16, 1); + } + else if (sop == 2 && bit8) + { + TRACE_INSN (cpu, "R%i.%c = R%i.%c >> %i;", + dst0, (HLs & 2) ? 'H' : 'L', + src1, (HLs & 1) ? 'H' : 'L', newimmag); + result = lshiftrt (cpu, in, newimmag, 16); + } + else if (sop == 2 && bit8 == 0) + { + TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i;", + dst0, (HLs & 2) ? 'H' : 'L', + src1, (HLs & 1) ? 'H' : 'L', immag); + result = lshift (cpu, in, immag, 16, 0); + } + else + illegal_instruction (cpu); + + v = DREG (dst0); + if (HLs & 2) + STORE (DREG (dst0), (v & 0xFFFF) | (result << 16)); + else + STORE (DREG (dst0), (v & 0xFFFF0000) | result); + } + else if (sop == 2 && sopcde == 3 && (HLs == 1 || HLs == 0)) + { + int shift = imm6 (immag); + bu32 cc = CCREG; + bu40 acc = get_unextended_acc (cpu, HLs); + + TRACE_INSN (cpu, "A%i = ROT A%i BY %i;", HLs, HLs, shift); + TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i CC:%i", HLs, acc, shift, cc); + + acc = rot40 (acc, shift, &cc); + SET_AREG (HLs, acc); + if (shift) + SET_CCREG (cc); + } + else if (sop == 0 && sopcde == 3 && bit8 == 1) + { + /* Arithmetic shift, so shift in sign bit copies. */ + bu64 acc; + int shift = uimm5 (newimmag); + HLs = !!HLs; + + TRACE_INSN (cpu, "A%i = A%i >>> %i;", HLs, HLs, shift); + + acc = get_extended_acc (cpu, HLs); + acc >>= shift; + /* Sign extend again. */ + if (acc & (1ULL << 39)) + acc |= -(1ULL << 39); + else + acc &= ~(-(1ULL << 39)); + + STORE (AXREG (HLs), (acc >> 32) & 0xFF); + STORE (AWREG (HLs), acc & 0xFFFFFFFF); + } + else if ((sop == 0 && sopcde == 3 && bit8 == 0) + || (sop == 1 && sopcde == 3)) + { + bu64 acc; + int shiftup = uimm5 (immag); + int shiftdn = uimm5 (newimmag); + HLs = !!HLs; + + TRACE_INSN (cpu, "A%i = A%i %s %i;", HLs, HLs, + sop == 0 ? "<<" : ">>", + sop == 0 ? shiftup : shiftdn); + + acc = AXREG (HLs); + /* Logical shift, so shift in zeroes. */ + acc &= 0xFF; + acc <<= 32; + acc |= AWREG (HLs); + + if (sop == 0) + acc <<= shiftup; + else + acc >>= shiftdn; + + SET_AREG (HLs, acc); + SET_ASTATREG (an, !!(acc & 0x8000000000ull)); + SET_ASTATREG (az, acc == 0); + } + else if (sop == 1 && sopcde == 1 && bit8 == 0) + { + int count = imm5 (immag); + bu16 val0 = DREG (src1) >> 16; + bu16 val1 = DREG (src1) & 0xFFFF; + bu32 astat; + + TRACE_INSN (cpu, "R%i = R%i << %i (V,S);", dst0, src1, count); + val0 = lshift (cpu, val0, count, 16, 1); + astat = ASTAT; + val1 = lshift (cpu, val1, count, 16, 1); + SET_ASTAT (ASTAT | astat); + + STORE (DREG (dst0), (val0 << 16) | val1); + } + else if (sop == 2 && sopcde == 1 && bit8 == 1) + { + int count = imm5 (newimmag); + bu16 val0 = DREG (src1) & 0xFFFF; + bu16 val1 = DREG (src1) >> 16; + bu32 astat; + + TRACE_INSN (cpu, "R%i = R%i >> %i (V);", dst0, src1, count); + val0 = lshiftrt (cpu, val0, count, 16); + astat = ASTAT; + val1 = lshiftrt (cpu, val1, count, 16); + SET_ASTAT (ASTAT | astat); + + STORE (DREG (dst0), val0 | (val1 << 16)); + } + else if (sop == 2 && sopcde == 1 && bit8 == 0) + { + int count = imm5 (immag); + bu16 val0 = DREG (src1) & 0xFFFF; + bu16 val1 = DREG (src1) >> 16; + bu32 astat; + + TRACE_INSN (cpu, "R%i = R%i << %i (V);", dst0, src1, count); + val0 = lshift (cpu, val0, count, 16, 0); + astat = ASTAT; + val1 = lshift (cpu, val1, count, 16, 0); + SET_ASTAT (ASTAT | astat); + + STORE (DREG (dst0), val0 | (val1 << 16)); + } + else if (sopcde == 1 && (sop == 0 || (sop == 1 && bit8 == 1))) + { + int count = uimm5 (newimmag); + bu16 val0 = DREG (src1) & 0xFFFF; + bu16 val1 = DREG (src1) >> 16; + bu32 astat; + + TRACE_INSN (cpu, "R%i = R%i >>> %i %s;", dst0, src1, count, + sop == 0 ? "(V)" : "(V,S)"); + + val0 = ashiftrt (cpu, val0, count, 16); + astat = ASTAT; + val1 = ashiftrt (cpu, val1, count, 16); + SET_ASTAT (ASTAT | astat); + + STORE (DREG (dst0), REG_H_L (val1 << 16, val0)); + } + else if (sop == 1 && sopcde == 2) + { + int count = imm6 (immag); + + TRACE_INSN (cpu, "R%i = R%i << %i (S);", dst0, src1, count); + STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1)); + } + else if (sop == 2 && sopcde == 2) + { + int count = imm6 (newimmag); + + TRACE_INSN (cpu, "R%i = R%i >> %i;", dst0, src1, count); + + if (count < 0) + STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0)); + else + STORE (DREG (dst0), lshiftrt (cpu, DREG (src1), count, 32)); + } + else if (sop == 3 && sopcde == 2) + { + int shift = imm6 (immag); + bu32 src = DREG (src1); + bu32 ret, cc = CCREG; + + TRACE_INSN (cpu, "R%i = ROT R%i BY %i;", dst0, src1, shift); + TRACE_DECODE (cpu, "R%i:%#x R%i:%#x shift:%i CC:%i", + dst0, DREG (dst0), src1, src, shift, cc); + + ret = rot32 (src, shift, &cc); + STORE (DREG (dst0), ret); + if (shift) + SET_CCREG (cc); + } + else if (sop == 0 && sopcde == 2) + { + int count = imm6 (newimmag); + + TRACE_INSN (cpu, "R%i = R%i >>> %i;", dst0, src1, count); + + if (count < 0) + STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0)); + else + STORE (DREG (dst0), ashiftrt (cpu, DREG (src1), count, 32)); + } + else + illegal_instruction (cpu); +} + +static void +outc (SIM_CPU *cpu, char ch) +{ + SIM_DESC sd = CPU_STATE (cpu); + sim_io_printf (sd, "%c", ch); + if (ch == '\n') + sim_io_flush_stdout (sd); +} + +static void +decode_psedoDEBUG_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* psedoDEBUG + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + SIM_DESC sd = CPU_STATE (cpu); + int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask); + int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask); + int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_psedoDEBUG); + TRACE_EXTRACT (cpu, "%s: fn:%i grp:%i reg:%i", __func__, fn, grp, reg); + + if ((reg == 0 || reg == 1) && fn == 3) + { + TRACE_INSN (cpu, "DBG A%i;", reg); + sim_io_printf (sd, "DBG : A%i = %#"PRIx64"\n", reg, + get_unextended_acc (cpu, reg)); + } + else if (reg == 3 && fn == 3) + { + TRACE_INSN (cpu, "ABORT;"); + cec_exception (cpu, VEC_SIM_ABORT); + SET_DREG (0, 1); + } + else if (reg == 4 && fn == 3) + { + TRACE_INSN (cpu, "HLT;"); + cec_exception (cpu, VEC_SIM_HLT); + SET_DREG (0, 0); + } + else if (reg == 5 && fn == 3) + unhandled_instruction (cpu, "DBGHALT"); + else if (reg == 6 && fn == 3) + unhandled_instruction (cpu, "DBGCMPLX (dregs)"); + else if (reg == 7 && fn == 3) + unhandled_instruction (cpu, "DBG"); + else if (grp == 0 && fn == 2) + { + TRACE_INSN (cpu, "OUTC R%i;", reg); + outc (cpu, DREG (reg)); + } + else if (fn == 0) + { + const char *reg_name = get_allreg_name (grp, reg); + TRACE_INSN (cpu, "DBG %s;", reg_name); + sim_io_printf (sd, "DBG : %s = 0x%08x\n", reg_name, + reg_read (cpu, grp, reg)); + } + else if (fn == 1) + unhandled_instruction (cpu, "PRNT allregs"); + else + illegal_instruction (cpu); +} + +static void +decode_psedoOChar_0 (SIM_CPU *cpu, bu16 iw0) +{ + /* psedoOChar + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask); + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_psedoOChar); + TRACE_EXTRACT (cpu, "%s: ch:%#x", __func__, ch); + TRACE_INSN (cpu, "OUTC %#x;", ch); + + outc (cpu, ch); +} + +static void +decode_psedodbg_assert_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc) +{ + /* psedodbg_assert + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ + | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...| + |.expected......................................................| + +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ + SIM_DESC sd = CPU_STATE (cpu); + int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask); + int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask); + int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask); + int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask); + int offset; + bu16 actual; + bu32 val = reg_read (cpu, grp, regtest); + const char *reg_name = get_allreg_name (grp, regtest); + const char *dbg_name, *dbg_appd; + + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_psedodbg_assert); + TRACE_EXTRACT (cpu, "%s: dbgop:%i grp:%i regtest:%i expected:%#x", + __func__, dbgop, grp, regtest, expected); + + if (dbgop == 0 || dbgop == 2) + { + dbg_name = dbgop == 0 ? "DBGA" : "DBGAL"; + dbg_appd = dbgop == 0 ? ".L" : ""; + offset = 0; + } + else if (dbgop == 1 || dbgop == 3) + { + dbg_name = dbgop == 1 ? "DBGA" : "DBGAH"; + dbg_appd = dbgop == 1 ? ".H" : ""; + offset = 16; + } + else + illegal_instruction (cpu); + + actual = val >> offset; + + TRACE_INSN (cpu, "%s (%s%s, 0x%x);", dbg_name, reg_name, dbg_appd, expected); + if (actual != expected) + { + sim_io_printf (sd, "FAIL at %#x: %s (%s%s, 0x%04x); actual value %#x\n", + pc, dbg_name, reg_name, dbg_appd, expected, actual); + + /* Decode the actual ASTAT bits that are different. */ + if (grp == 4 && regtest == 6) + { + int i; + + sim_io_printf (sd, "Expected ASTAT:\n"); + for (i = 0; i < 16; ++i) + sim_io_printf (sd, " %8s%c%i%s", + astat_names[i + offset], + (((expected >> i) & 1) != ((actual >> i) & 1)) + ? '!' : ' ', + (expected >> i) & 1, + i == 7 ? "\n" : ""); + sim_io_printf (sd, "\n"); + + sim_io_printf (sd, "Actual ASTAT:\n"); + for (i = 0; i < 16; ++i) + sim_io_printf (sd, " %8s%c%i%s", + astat_names[i + offset], + (((expected >> i) & 1) != ((actual >> i) & 1)) + ? '!' : ' ', + (actual >> i) & 1, + i == 7 ? "\n" : ""); + sim_io_printf (sd, "\n"); + } + + cec_exception (cpu, VEC_SIM_DBGA); + SET_DREG (0, 1); + } +} + +static bu32 +_interp_insn_bfin (SIM_CPU *cpu, bu32 pc) +{ + bu32 insn_len; + bu16 iw0, iw1; + + BFIN_CPU_STATE.multi_pc = pc; + iw0 = IFETCH (pc); + if ((iw0 & 0xc000) != 0xc000) + { + /* 16-bit opcode. */ + insn_len = 2; + if (INSN_LEN == 0) + INSN_LEN = insn_len; + + TRACE_EXTRACT (cpu, "%s: iw0:%#x", __func__, iw0); + if ((iw0 & 0xFF00) == 0x0000) + decode_ProgCtrl_0 (cpu, iw0, pc); + else if ((iw0 & 0xFFC0) == 0x0240) + decode_CaCTRL_0 (cpu, iw0); + else if ((iw0 & 0xFF80) == 0x0100) + decode_PushPopReg_0 (cpu, iw0); + else if ((iw0 & 0xFE00) == 0x0400) + decode_PushPopMultiple_0 (cpu, iw0); + else if ((iw0 & 0xFE00) == 0x0600) + decode_ccMV_0 (cpu, iw0); + else if ((iw0 & 0xF800) == 0x0800) + decode_CCflag_0 (cpu, iw0); + else if ((iw0 & 0xFFE0) == 0x0200) + decode_CC2dreg_0 (cpu, iw0); + else if ((iw0 & 0xFF00) == 0x0300) + decode_CC2stat_0 (cpu, iw0); + else if ((iw0 & 0xF000) == 0x1000) + decode_BRCC_0 (cpu, iw0, pc); + else if ((iw0 & 0xF000) == 0x2000) + decode_UJUMP_0 (cpu, iw0, pc); + else if ((iw0 & 0xF000) == 0x3000) + decode_REGMV_0 (cpu, iw0); + else if ((iw0 & 0xFC00) == 0x4000) + decode_ALU2op_0 (cpu, iw0); + else if ((iw0 & 0xFE00) == 0x4400) + decode_PTR2op_0 (cpu, iw0); + else if ((iw0 & 0xF800) == 0x4800) + decode_LOGI2op_0 (cpu, iw0); + else if ((iw0 & 0xF000) == 0x5000) + decode_COMP3op_0 (cpu, iw0); + else if ((iw0 & 0xF800) == 0x6000) + decode_COMPI2opD_0 (cpu, iw0); + else if ((iw0 & 0xF800) == 0x6800) + decode_COMPI2opP_0 (cpu, iw0); + else if ((iw0 & 0xF000) == 0x8000) + decode_LDSTpmod_0 (cpu, iw0); + else if ((iw0 & 0xFF60) == 0x9E60) + decode_dagMODim_0 (cpu, iw0); + else if ((iw0 & 0xFFF0) == 0x9F60) + decode_dagMODik_0 (cpu, iw0); + else if ((iw0 & 0xFC00) == 0x9C00) + decode_dspLDST_0 (cpu, iw0); + else if ((iw0 & 0xF000) == 0x9000) + decode_LDST_0 (cpu, iw0); + else if ((iw0 & 0xFC00) == 0xB800) + decode_LDSTiiFP_0 (cpu, iw0); + else if ((iw0 & 0xE000) == 0xA000) + decode_LDSTii_0 (cpu, iw0); + else + { + TRACE_EXTRACT (cpu, "%s: no matching 16-bit pattern", __func__); + illegal_instruction (cpu); + } + return insn_len; + } + + /* Grab the next 16 bits to determine if it's a 32-bit or 64-bit opcode. */ + iw1 = IFETCH (pc + 2); + if ((iw0 & BIT_MULTI_INS) && (iw0 & 0xe800) != 0xe800 /* not linkage */) + { + SIM_DESC sd = CPU_STATE (cpu); + trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), + NULL, 0, "|| %#"PRIx64, sim_events_time (sd)); + insn_len = 8; + } + else + insn_len = 4; + + TRACE_EXTRACT (cpu, "%s: iw0:%#x iw1:%#x insn_len:%i", __func__, + iw0, iw1, insn_len); + + /* Only cache on first run through (in case of parallel insns). */ + if (INSN_LEN == 0) + INSN_LEN = insn_len; + + if ((iw0 & 0xf7ff) == 0xc003 && (iw1 & 0xfe00) == 0x1800) + { + PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32mac); + TRACE_INSN (cpu, "MNOP;"); + } + else if (((iw0 & 0xFF80) == 0xE080) && ((iw1 & 0x0C00) == 0x0000)) + decode_LoopSetup_0 (cpu, iw0, iw1, pc); + else if (((iw0 & 0xFF00) == 0xE100) && ((iw1 & 0x0000) == 0x0000)) + decode_LDIMMhalf_0 (cpu, iw0, iw1); + else if (((iw0 & 0xFE00) == 0xE200) && ((iw1 & 0x0000) == 0x0000)) + decode_CALLa_0 (cpu, iw0, iw1, pc); + else if (((iw0 & 0xFC00) == 0xE400) && ((iw1 & 0x0000) == 0x0000)) + decode_LDSTidxI_0 (cpu, iw0, iw1); + else if (((iw0 & 0xFFFE) == 0xE800) && ((iw1 & 0x0000) == 0x0000)) + decode_linkage_0 (cpu, iw0, iw1); + else if (((iw0 & 0xF600) == 0xC000) && ((iw1 & 0x0000) == 0x0000)) + decode_dsp32mac_0 (cpu, iw0, iw1); + else if (((iw0 & 0xF600) == 0xC200) && ((iw1 & 0x0000) == 0x0000)) + decode_dsp32mult_0 (cpu, iw0, iw1); + else if (((iw0 & 0xF7C0) == 0xC400) && ((iw1 & 0x0000) == 0x0000)) + decode_dsp32alu_0 (cpu, iw0, iw1); + else if (((iw0 & 0xF7E0) == 0xC600) && ((iw1 & 0x01C0) == 0x0000)) + decode_dsp32shift_0 (cpu, iw0, iw1); + else if (((iw0 & 0xF7E0) == 0xC680) && ((iw1 & 0x0000) == 0x0000)) + decode_dsp32shiftimm_0 (cpu, iw0, iw1); + else if ((iw0 & 0xFF00) == 0xF800) + decode_psedoDEBUG_0 (cpu, iw0), insn_len = 2; + else if ((iw0 & 0xFF00) == 0xF900) + decode_psedoOChar_0 (cpu, iw0), insn_len = 2; + else if (((iw0 & 0xFF00) == 0xF000) && ((iw1 & 0x0000) == 0x0000)) + decode_psedodbg_assert_0 (cpu, iw0, iw1, pc); + else + { + TRACE_EXTRACT (cpu, "%s: no matching 32-bit pattern", __func__); + illegal_instruction (cpu); + } + + return insn_len; +} + +bu32 +interp_insn_bfin (SIM_CPU *cpu, bu32 pc) +{ + int i; + bu32 insn_len; + + BFIN_CPU_STATE.n_stores = 0; + DIS_ALGN_EXPT &= ~1; + CYCLE_DELAY = 1; + INSN_LEN = 0; + + insn_len = _interp_insn_bfin (cpu, pc); + + /* Proper display of multiple issue instructions. */ + if (insn_len == 8) + { + _interp_insn_bfin (cpu, pc + 4); + _interp_insn_bfin (cpu, pc + 6); + } + for (i = 0; i < BFIN_CPU_STATE.n_stores; i++) + { + bu32 *addr = BFIN_CPU_STATE.stores[i].addr; + *addr = BFIN_CPU_STATE.stores[i].val; + TRACE_REGISTER (cpu, "dequeuing write %s = %#x", + get_store_name (cpu, addr), *addr); + } + + cycles_inc (cpu, CYCLE_DELAY); + + /* Set back to zero in case a pending CEC event occurs + after this this insn. */ + INSN_LEN = 0; + + return insn_len; +} diff --git a/external/gpl3/gdb/dist/sim/bfin/bfin-sim.h b/external/gpl3/gdb/dist/sim/bfin/bfin-sim.h new file mode 100644 index 000000000000..d61e7fe1f7ba --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfin-sim.h @@ -0,0 +1,350 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef _BFIN_SIM_H_ +#define _BFIN_SIM_H_ + +#include +#include + +typedef uint8_t bu8; +typedef uint16_t bu16; +typedef uint32_t bu32; +typedef uint64_t bu40; +typedef uint64_t bu64; +typedef int8_t bs8; +typedef int16_t bs16; +typedef int32_t bs32; +typedef int64_t bs40; +typedef int64_t bs64; + +/* For dealing with parallel instructions, we must avoid changing our register + file until all parallel insns have been simulated. This queue of stores + can be used to delay a modification. + XXX: Should go and convert all 32 bit insns to use this. */ +struct store { + bu32 *addr; + bu32 val; +}; + +/* The KSP/USP handling wrt SP may not follow the hardware exactly (the hw + looks at current mode and uses either SP or USP based on that. We instead + always operate on SP and mirror things in KSP and USP. During a CEC + transition, we take care of syncing the values. This lowers the simulation + complexity and speeds things up a bit. */ +struct bfin_cpu_state +{ + bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4], cycles[3]; + bu32 ax[2], aw[2]; + bu32 lt[2], lc[2], lb[2]; + bu32 ksp, usp, seqstat, syscfg, rets, reti, retx, retn, rete; + bu32 pc, emudat[2]; + /* These ASTAT flags need not be bu32, but it makes pointers easier. */ + bu32 ac0, ac0_copy, ac1, an, aq; + union { struct { bu32 av0; bu32 av1; }; bu32 av [2]; }; + union { struct { bu32 av0s; bu32 av1s; }; bu32 avs[2]; }; + bu32 az, cc, v, v_copy, vs; + bu32 rnd_mod; + bu32 v_internal; + bu32 astat_reserved; + + /* Set by an instruction emulation function if we performed a jump. We + cannot compare oldpc to newpc as this ignores the "jump 0;" case. */ + bool did_jump; + + /* Used by the CEC to figure out where to return to. */ + bu32 insn_len; + + /* How many cycles did this insn take to complete ? */ + bu32 cycle_delay; + + /* The pc currently being interpreted in parallel insns. */ + bu32 multi_pc; + + /* Needed for supporting the DISALGNEXCPT instruction */ + int dis_algn_expt; + + /* See notes above for struct store. */ + struct store stores[20]; + int n_stores; + +#if (WITH_HW) + /* Cache heavily used CPU-specific device pointers. */ + void *cec_cache; + void *evt_cache; + void *mmu_cache; + void *trace_cache; +#endif +}; + +#define REG_H_L(h, l) (((h) & 0xffff0000) | ((l) & 0x0000ffff)) + +#define DREG(x) (BFIN_CPU_STATE.dpregs[x]) +#define PREG(x) (BFIN_CPU_STATE.dpregs[x + 8]) +#define SPREG PREG (6) +#define FPREG PREG (7) +#define IREG(x) (BFIN_CPU_STATE.iregs[x]) +#define MREG(x) (BFIN_CPU_STATE.mregs[x]) +#define BREG(x) (BFIN_CPU_STATE.bregs[x]) +#define LREG(x) (BFIN_CPU_STATE.lregs[x]) +#define AXREG(x) (BFIN_CPU_STATE.ax[x]) +#define AWREG(x) (BFIN_CPU_STATE.aw[x]) +#define CCREG (BFIN_CPU_STATE.cc) +#define LCREG(x) (BFIN_CPU_STATE.lc[x]) +#define LTREG(x) (BFIN_CPU_STATE.lt[x]) +#define LBREG(x) (BFIN_CPU_STATE.lb[x]) +#define CYCLESREG (BFIN_CPU_STATE.cycles[0]) +#define CYCLES2REG (BFIN_CPU_STATE.cycles[1]) +#define CYCLES2SHDREG (BFIN_CPU_STATE.cycles[2]) +#define KSPREG (BFIN_CPU_STATE.ksp) +#define USPREG (BFIN_CPU_STATE.usp) +#define SEQSTATREG (BFIN_CPU_STATE.seqstat) +#define SYSCFGREG (BFIN_CPU_STATE.syscfg) +#define RETSREG (BFIN_CPU_STATE.rets) +#define RETIREG (BFIN_CPU_STATE.reti) +#define RETXREG (BFIN_CPU_STATE.retx) +#define RETNREG (BFIN_CPU_STATE.retn) +#define RETEREG (BFIN_CPU_STATE.rete) +#define PCREG (BFIN_CPU_STATE.pc) +#define EMUDAT_INREG (BFIN_CPU_STATE.emudat[0]) +#define EMUDAT_OUTREG (BFIN_CPU_STATE.emudat[1]) +#define INSN_LEN (BFIN_CPU_STATE.insn_len) +#define CYCLE_DELAY (BFIN_CPU_STATE.cycle_delay) +#define DIS_ALGN_EXPT (BFIN_CPU_STATE.dis_algn_expt) + +#define EXCAUSE_SHIFT 0 +#define EXCAUSE_MASK (0x3f << EXCAUSE_SHIFT) +#define EXCAUSE ((SEQSTATREG & EXCAUSE_MASK) >> EXCAUSE_SHIFT) +#define HWERRCAUSE_SHIFT 14 +#define HWERRCAUSE_MASK (0x1f << HWERRCAUSE_SHIFT) +#define HWERRCAUSE ((SEQSTATREG & HWERRCAUSE_MASK) >> HWERRCAUSE_SHIFT) + +#define _SET_CORE32REG_IDX(reg, p, x, val) \ + do { \ + bu32 __v = (val); \ + TRACE_REGISTER (cpu, "wrote "#p"%i = %#x", x, __v); \ + reg = __v; \ + } while (0) +#define SET_DREG(x, val) _SET_CORE32REG_IDX (DREG (x), R, x, val) +#define SET_PREG(x, val) _SET_CORE32REG_IDX (PREG (x), P, x, val) +#define SET_IREG(x, val) _SET_CORE32REG_IDX (IREG (x), I, x, val) +#define SET_MREG(x, val) _SET_CORE32REG_IDX (MREG (x), M, x, val) +#define SET_BREG(x, val) _SET_CORE32REG_IDX (BREG (x), B, x, val) +#define SET_LREG(x, val) _SET_CORE32REG_IDX (LREG (x), L, x, val) +#define SET_LCREG(x, val) _SET_CORE32REG_IDX (LCREG (x), LC, x, val) +#define SET_LTREG(x, val) _SET_CORE32REG_IDX (LTREG (x), LT, x, val) +#define SET_LBREG(x, val) _SET_CORE32REG_IDX (LBREG (x), LB, x, val) + +#define SET_DREG_L_H(x, l, h) SET_DREG (x, REG_H_L (h, l)) +#define SET_DREG_L(x, l) SET_DREG (x, REG_H_L (DREG (x), l)) +#define SET_DREG_H(x, h) SET_DREG (x, REG_H_L (h, DREG (x))) + +#define _SET_CORE32REG_ALU(reg, p, x, val) \ + do { \ + bu32 __v = (val); \ + TRACE_REGISTER (cpu, "wrote A%i"#p" = %#x", x, __v); \ + reg = __v; \ + } while (0) +#define SET_AXREG(x, val) _SET_CORE32REG_ALU (AXREG (x), X, x, val) +#define SET_AWREG(x, val) _SET_CORE32REG_ALU (AWREG (x), W, x, val) + +#define SET_AREG(x, val) \ + do { \ + bu40 __a = (val); \ + SET_AXREG (x, (__a >> 32) & 0xff); \ + SET_AWREG (x, __a); \ + } while (0) +#define SET_AREG32(x, val) \ + do { \ + SET_AWREG (x, val); \ + SET_AXREG (x, -(AWREG (x) >> 31)); \ + } while (0) + +#define _SET_CORE32REG(reg, val) \ + do { \ + bu32 __v = (val); \ + TRACE_REGISTER (cpu, "wrote "#reg" = %#x", __v); \ + reg##REG = __v; \ + } while (0) +#define SET_FPREG(val) _SET_CORE32REG (FP, val) +#define SET_SPREG(val) _SET_CORE32REG (SP, val) +#define SET_CYCLESREG(val) _SET_CORE32REG (CYCLES, val) +#define SET_CYCLES2REG(val) _SET_CORE32REG (CYCLES2, val) +#define SET_CYCLES2SHDREG(val) _SET_CORE32REG (CYCLES2SHD, val) +#define SET_KSPREG(val) _SET_CORE32REG (KSP, val) +#define SET_USPREG(val) _SET_CORE32REG (USP, val) +#define SET_SYSCFGREG(val) _SET_CORE32REG (SYSCFG, val) +#define SET_RETSREG(val) _SET_CORE32REG (RETS, val) +#define SET_RETIREG(val) _SET_CORE32REG (RETI, val) +#define SET_RETXREG(val) _SET_CORE32REG (RETX, val) +#define SET_RETNREG(val) _SET_CORE32REG (RETN, val) +#define SET_RETEREG(val) _SET_CORE32REG (RETE, val) +#define SET_PCREG(val) _SET_CORE32REG (PC, val) + +#define _SET_CORE32REGFIELD(reg, field, val, mask, shift) \ + do { \ + bu32 __f = (val); \ + bu32 __v = ((reg##REG) & ~(mask)) | (__f << (shift)); \ + TRACE_REGISTER (cpu, "wrote "#field" = %#x ("#reg" = %#x)", __f, __v); \ + reg##REG = __v; \ + } while (0) +#define SET_SEQSTATREG(val) _SET_CORE32REG (SEQSTAT, val) +#define SET_EXCAUSE(excp) _SET_CORE32REGFIELD (SEQSTAT, EXCAUSE, excp, EXCAUSE_MASK, EXCAUSE_SHIFT) +#define SET_HWERRCAUSE(hwerr) _SET_CORE32REGFIELD (SEQSTAT, HWERRCAUSE, hwerr, HWERRCAUSE_MASK, HWERRCAUSE_SHIFT) + +#define AZ_BIT 0 +#define AN_BIT 1 +#define AC0_COPY_BIT 2 +#define V_COPY_BIT 3 +#define CC_BIT 5 +#define AQ_BIT 6 +#define RND_MOD_BIT 8 +#define AC0_BIT 12 +#define AC1_BIT 13 +#define AV0_BIT 16 +#define AV0S_BIT 17 +#define AV1_BIT 18 +#define AV1S_BIT 19 +#define V_BIT 24 +#define VS_BIT 25 +#define ASTAT_DEFINED_BITS \ + ((1 << AZ_BIT) | (1 << AN_BIT) | (1 << AC0_COPY_BIT) | (1 << V_COPY_BIT) \ + |(1 << CC_BIT) | (1 << AQ_BIT) \ + |(1 << RND_MOD_BIT) \ + |(1 << AC0_BIT) | (1 << AC1_BIT) \ + |(1 << AV0_BIT) | (1 << AV0S_BIT) | (1 << AV1_BIT) | (1 << AV1S_BIT) \ + |(1 << V_BIT) | (1 << VS_BIT)) + +#define ASTATREG(field) (BFIN_CPU_STATE.field) +#define ASTAT_DEPOSIT(field, bit) (ASTATREG(field) << (bit)) +#define ASTAT \ + (ASTAT_DEPOSIT(az, AZ_BIT) \ + |ASTAT_DEPOSIT(an, AN_BIT) \ + |ASTAT_DEPOSIT(ac0_copy, AC0_COPY_BIT) \ + |ASTAT_DEPOSIT(v_copy, V_COPY_BIT) \ + |ASTAT_DEPOSIT(cc, CC_BIT) \ + |ASTAT_DEPOSIT(aq, AQ_BIT) \ + |ASTAT_DEPOSIT(rnd_mod, RND_MOD_BIT) \ + |ASTAT_DEPOSIT(ac0, AC0_BIT) \ + |ASTAT_DEPOSIT(ac1, AC1_BIT) \ + |ASTAT_DEPOSIT(av0, AV0_BIT) \ + |ASTAT_DEPOSIT(av0s, AV0S_BIT) \ + |ASTAT_DEPOSIT(av1, AV1_BIT) \ + |ASTAT_DEPOSIT(av1s, AV1S_BIT) \ + |ASTAT_DEPOSIT(v, V_BIT) \ + |ASTAT_DEPOSIT(vs, VS_BIT) \ + |ASTATREG(astat_reserved)) + +#define ASTAT_EXTRACT(a, bit) (((a) >> bit) & 1) +#define _SET_ASTAT(a, field, bit) (ASTATREG(field) = ASTAT_EXTRACT(a, bit)) +#define SET_ASTAT(a) \ + do { \ + TRACE_REGISTER (cpu, "wrote ASTAT = %#x", a); \ + _SET_ASTAT(a, az, AZ_BIT); \ + _SET_ASTAT(a, an, AN_BIT); \ + _SET_ASTAT(a, ac0_copy, AC0_COPY_BIT); \ + _SET_ASTAT(a, v_copy, V_COPY_BIT); \ + _SET_ASTAT(a, cc, CC_BIT); \ + _SET_ASTAT(a, aq, AQ_BIT); \ + _SET_ASTAT(a, rnd_mod, RND_MOD_BIT); \ + _SET_ASTAT(a, ac0, AC0_BIT); \ + _SET_ASTAT(a, ac1, AC1_BIT); \ + _SET_ASTAT(a, av0, AV0_BIT); \ + _SET_ASTAT(a, av0s, AV0S_BIT); \ + _SET_ASTAT(a, av1, AV1_BIT); \ + _SET_ASTAT(a, av1s, AV1S_BIT); \ + _SET_ASTAT(a, v, V_BIT); \ + _SET_ASTAT(a, vs, VS_BIT); \ + ASTATREG(astat_reserved) = (a) & ~ASTAT_DEFINED_BITS; \ + } while (0) +#define SET_ASTATREG(field, val) \ + do { \ + int __v = !!(val); \ + TRACE_REGISTER (cpu, "wrote ASTAT["#field"] = %i", __v); \ + ASTATREG (field) = __v; \ + if (&ASTATREG (field) == &ASTATREG (ac0)) \ + { \ + TRACE_REGISTER (cpu, "wrote ASTAT["#field"_copy] = %i", __v); \ + ASTATREG (ac0_copy) = __v; \ + } \ + else if (&ASTATREG (field) == &ASTATREG (v)) \ + { \ + TRACE_REGISTER (cpu, "wrote ASTAT["#field"_copy] = %i", __v); \ + ASTATREG (v_copy) = __v; \ + } \ + } while (0) +#define SET_CCREG(val) SET_ASTATREG (cc, val) + +#define SYSCFG_SSSTEP (1 << 0) +#define SYSCFG_CCEN (1 << 1) +#define SYSCFG_SNEN (1 << 2) + +#define __PUT_MEM(taddr, v, size) \ +do { \ + bu##size __v = (v); \ + bu32 __taddr = (taddr); \ + int __cnt, __bytes = size / 8; \ + mmu_check_addr (cpu, __taddr, true, false, __bytes); \ + __cnt = sim_core_write_buffer (CPU_STATE(cpu), cpu, write_map, \ + (void *)&__v, __taddr, __bytes); \ + if (__cnt != __bytes) \ + mmu_process_fault (cpu, __taddr, true, false, false, true); \ + TRACE_CORE (cpu, __taddr, __bytes, write_map, __v); \ +} while (0) +#define PUT_BYTE(taddr, v) __PUT_MEM(taddr, v, 8) +#define PUT_WORD(taddr, v) __PUT_MEM(taddr, v, 16) +#define PUT_LONG(taddr, v) __PUT_MEM(taddr, v, 32) + +#define __GET_MEM(taddr, size, inst, map) \ +({ \ + bu##size __ret; \ + bu32 __taddr = (taddr); \ + int __cnt, __bytes = size / 8; \ + mmu_check_addr (cpu, __taddr, false, inst, __bytes); \ + __cnt = sim_core_read_buffer (CPU_STATE(cpu), cpu, map, \ + (void *)&__ret, __taddr, __bytes); \ + if (__cnt != __bytes) \ + mmu_process_fault (cpu, __taddr, false, inst, false, true); \ + TRACE_CORE (cpu, __taddr, __bytes, map, __ret); \ + __ret; \ +}) +#define _GET_MEM(taddr, size) __GET_MEM(taddr, size, false, read_map) +#define GET_BYTE(taddr) _GET_MEM(taddr, 8) +#define GET_WORD(taddr) _GET_MEM(taddr, 16) +#define GET_LONG(taddr) _GET_MEM(taddr, 32) + +#define IFETCH(taddr) __GET_MEM(taddr, 16, true, exec_map) +#define IFETCH_CHECK(taddr) mmu_check_addr (cpu, taddr, false, true, 2) + +extern void bfin_syscall (SIM_CPU *); +extern bu32 interp_insn_bfin (SIM_CPU *, bu32); +extern bu32 hwloop_get_next_pc (SIM_CPU *, bu32, bu32); + +/* Defines for Blackfin memory layouts. */ +#define BFIN_ASYNC_BASE 0x20000000 +#define BFIN_SYSTEM_MMR_BASE 0xFFC00000 +#define BFIN_CORE_MMR_BASE 0xFFE00000 +#define BFIN_L1_SRAM_SCRATCH 0xFFB00000 +#define BFIN_L1_SRAM_SCRATCH_SIZE 0x1000 +#define BFIN_L1_SRAM_SCRATCH_END (BFIN_L1_SRAM_SCRATCH + BFIN_L1_SRAM_SCRATCH_SIZE) + +#define BFIN_L1_CACHE_BYTES 32 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/all.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/all.h new file mode 100644 index 000000000000..1b562d9df40e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/all.h @@ -0,0 +1,43 @@ +#include "bf50x-0.0.h" + +#include "bf51x-0.0.h" +#include "bf51x-0.1.h" +#include "bf51x-0.2.h" + +#include "bf526-0.0.h" +#include "bf526-0.1.h" +#include "bf527-0.0.h" +#include "bf527-0.1.h" +#include "bf527-0.2.h" + +#include "bf533-0.1.h" +#include "bf533-0.2.h" +#include "bf533-0.3.h" +#define bfrom_bf533_0_4 bfrom_bf533_0_3 +#define bfrom_bf533_0_5 bfrom_bf533_0_3 +#define bfrom_bf533_0_6 bfrom_bf533_0_3 + +#include "bf537-0.0.h" +#include "bf537-0.1.h" +#define bfrom_bf537_0_2 bfrom_bf537_0_1 +#include "bf537-0.3.h" + +#include "bf538-0.0.h" +#define bfrom_bf538_0_1 bfrom_bf538_0_0 +#define bfrom_bf538_0_2 bfrom_bf538_0_0 +#define bfrom_bf538_0_3 bfrom_bf538_0_0 +#define bfrom_bf538_0_4 bfrom_bf538_0_0 +#define bfrom_bf538_0_5 bfrom_bf538_0_0 + +#include "bf54x-0.0.h" +#include "bf54x-0.1.h" +#include "bf54x-0.2.h" +#include "bf54x_l1-0.0.h" +#include "bf54x_l1-0.1.h" +#include "bf54x_l1-0.2.h" + +#include "bf561-0.5.h" + +#include "bf59x-0.0.h" +#define bfrom_bf59x_0_1 bfrom_bf59x_0_0 +#include "bf59x_l1-0.1.h" diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf50x-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf50x-0.0.h new file mode 100644 index 000000000000..c5dfcdab759f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf50x-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf50x_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.0.h new file mode 100644 index 000000000000..9d5b59f47491 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf51x_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.1.h new file mode 100644 index 000000000000..b7529c9cf20a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf51x_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.2.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.2.h new file mode 100644 index 000000000000..c64059357dab --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf51x-0.2.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf51x_0_2[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.0.h new file mode 100644 index 000000000000..e7aedd7532a4 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf526_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.1.h new file mode 100644 index 000000000000..f3602d21ec4f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf526-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf526_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.0.h new file mode 100644 index 000000000000..127603c35aec --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf527_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.1.h new file mode 100644 index 000000000000..81730150faee --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf527_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.2.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.2.h new file mode 100644 index 000000000000..54960e56c2cc --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf527-0.2.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf527_0_2[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.1.h new file mode 100644 index 000000000000..449983607e4a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf533_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.2.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.2.h new file mode 100644 index 000000000000..b4921bc09b49 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.2.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf533_0_2[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.3.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.3.h new file mode 100644 index 000000000000..607c5c216275 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf533-0.3.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf533_0_3[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.0.h new file mode 100644 index 000000000000..c4a119bca11b --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf537_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.1.h new file mode 100644 index 000000000000..c881453717f3 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf537_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.3.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.3.h new file mode 100644 index 000000000000..bd542a36fc15 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf537-0.3.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf537_0_3[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf538-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf538-0.0.h new file mode 100644 index 000000000000..0c2d195cba53 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf538-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf538_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.0.h new file mode 100644 index 000000000000..64457312d026 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.1.h new file mode 100644 index 000000000000..cfdc892d10b3 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.2.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.2.h new file mode 100644 index 000000000000..2523ec1f40af --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x-0.2.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_0_2[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.0.h new file mode 100644 index 000000000000..5ff50913cfe5 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_l1_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.1.h new file mode 100644 index 000000000000..9f28c40bbef2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_l1_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.2.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.2.h new file mode 100644 index 000000000000..e15c532fbc84 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf54x_l1-0.2.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf54x_l1_0_2[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf561-0.5.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf561-0.5.h new file mode 100644 index 000000000000..d9ff8afe1ef3 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf561-0.5.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf561_0_5[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x-0.0.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x-0.0.h new file mode 100644 index 000000000000..b8e11d2a6a83 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x-0.0.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf59x_0_0[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x_l1-0.1.h b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x_l1-0.1.h new file mode 100644 index 000000000000..7add74742d24 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/bfroms/bf59x_l1-0.1.h @@ -0,0 +1,4 @@ +/* DO NOT EDIT: Autogenerated. */ +static const char bfrom_bf59x_l1_0_1[] = +{ +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/config.in b/external/gpl3/gdb/dist/sim/bfin/config.in new file mode 100644 index 000000000000..2b25645ecf80 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/config.in @@ -0,0 +1,182 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have catgets and don't want to use GNU gettext. */ +#undef HAVE_CATGETS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define if building universal (internal helper macro) */ +#undef AC_APPLE_UNIVERSAL_BUILD + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define if dv-sockser is usable. */ +#undef HAVE_DV_SOCKSER + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `getegid' function. */ +#undef HAVE_GETEGID + +/* Define to 1 if you have the `geteuid' function. */ +#undef HAVE_GETEUID + +/* Define to 1 if you have the `getgid' function. */ +#undef HAVE_GETGID + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the `getuid' function. */ +#undef HAVE_GETUID + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `kill' function. */ +#undef HAVE_KILL + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the header file. */ +#undef HAVE_LINUX_IF_TUN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_LINUX_MII_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `mmap' function. */ +#undef HAVE_MMAP + +/* Define to 1 if you have the `munmap' function. */ +#undef HAVE_MUNMAP + +/* Define to 1 if you have the header file. */ +#undef HAVE_NET_IF_H + +/* Define to 1 if you have the `pread' function. */ +#undef HAVE_PREAD + +/* Define to 1 if you have the `setgid' function. */ +#undef HAVE_SETGID + +/* Define to 1 if you have the `setuid' function. */ +#undef HAVE_SETUID + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_IOCTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_MMAN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ZLIB_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Additional package description */ +#undef PKGVERSION + +/* Bug reporting address */ +#undef REPORT_BUGS_TO + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most + significant byte first (like Motorola and SPARC, unlike Intel). */ +#if defined AC_APPLE_UNIVERSAL_BUILD +# if defined __BIG_ENDIAN__ +# define WORDS_BIGENDIAN 1 +# endif +#else +# ifndef WORDS_BIGENDIAN +# undef WORDS_BIGENDIAN +# endif +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/configure b/external/gpl3/gdb/dist/sim/bfin/configure new file mode 100755 index 000000000000..c05f6d914ede --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/configure @@ -0,0 +1,6780 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. Then install a modern shell, or manually run +$0: the script under such a shell if you do have one." + fi + exit 1 +fi +fi +fi +SHELL=${CONFIG_SHELL-/bin/sh} +export SHELL +# Unset more variables known to interfere with behavior of common tools. +CLICOLOR_FORCE= GREP_OPTIONS= +unset CLICOLOR_FORCE GREP_OPTIONS + +## --------------------- ## +## M4sh Shell Functions. ## +## --------------------- ## +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. 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We used to do this for the assembler, linker, +# and nm only; for simplicity of configuration, however, we extend this +# criterion to tools (such as ar and ranlib) that are never invoked by +# the compiler, to avoid mismatches. +# +# Also note we have to check MD_EXEC_PREFIX before checking the user's path +# if build == target. This makes the most sense only when bootstrapping, +# but we also do so when build != host. In this case, we hope that the +# build and host systems will have similar contents of MD_EXEC_PREFIX. +# +# If we do not find a suitable binary, then try the user's path. + + +### +# AC_PROG_CPP_WERROR +# Used for autoconf 2.5x to force AC_PREPROC_IFELSE to reject code which +# triggers warnings from the preprocessor. Will be in autoconf 2.58. +# For now, using this also overrides header checks to use only the +# preprocessor (matches 2.13 behavior; matching 2.58's behavior is a +# bit harder from here). +# Eventually autoconf will default to checking headers with the compiler +# instead, and we'll have to do this differently. + +# AC_PROG_CPP_WERROR + +# Test for GNAT. +# We require the gnatbind program, and a compiler driver that +# understands Ada. We use the user's CC setting, already found, +# and possibly add $1 to the command-line parameters. +# +# Sets the shell variable have_gnat to yes or no as appropriate, and +# substitutes GNATBIND and GNATMAKE. + + + + + + + + + + + + + + + + + + + + + + + + + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +# This file contains common code used by all simulators. +# +# common.m4 invokes AC macros used by all simulators and by the common +# directory. It is intended to be included before any target specific +# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate +# the Makefile. It is intended to be invoked last. +# +# The simulator's configure.in should look like: +# +# dnl Process this file with autoconf to produce a configure script. +# AC_PREREQ(2.5)dnl +# AC_INIT(Makefile.in) +# AC_CONFIG_HEADER(config.h:config.in) +# +# sinclude(../common/aclocal.m4) +# sinclude(../common/common.m4) +# +# ... target specific stuff ... + +ac_aux_dir= +for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do + for ac_t in install-sh install.sh shtool; do + if test -f "$ac_dir/$ac_t"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/$ac_t -c" + break 2 + fi + done +done +if test -z "$ac_aux_dir"; then + as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5 +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) as_fn_error "invalid value of canonical build" "$LINENO" 5;; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) as_fn_error "invalid value of canonical target" "$LINENO" 5;; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +ALL_LINGUAS= +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../../intl/config.intl; then + . ../../intl/config.intl +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } +if test x"$USE_NLS" != xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define ENABLE_NLS 1" >>confdefs.h + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5 +$as_echo_n "checking for catalogs to be installed... " >&6; } + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5 +$as_echo "$LINGUAS" >&6; } + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in stdlib.h string.h strings.h unistd.h time.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in sys/time.h sys/resource.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in fcntl.h fpu_control.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in dlfcn.h errno.h sys/stat.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_func in getrusage time sigaction __setfpucw +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + +# Check for socket libraries +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5 +$as_echo_n "checking for bind in -lsocket... " >&6; } +if test "${ac_cv_lib_socket_bind+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsocket $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char bind (); +int +main () +{ +return bind (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_socket_bind=yes +else + ac_cv_lib_socket_bind=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5 +$as_echo "$ac_cv_lib_socket_bind" >&6; } +if test "x$ac_cv_lib_socket_bind" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBSOCKET 1 +_ACEOF + + LIBS="-lsocket $LIBS" + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 +$as_echo_n "checking for gethostbyname in -lnsl... " >&6; } +if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lnsl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char gethostbyname (); +int +main () +{ +return gethostbyname (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_nsl_gethostbyname=yes +else + ac_cv_lib_nsl_gethostbyname=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 +$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } +if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBNSL 1 +_ACEOF + + LIBS="-lnsl $LIBS" + +fi + + +# BFD conditionally uses zlib, so we must link it in if libbfd does, by +# using the same condition. + + # See if the user specified whether he wants zlib support or not. + +# Check whether --with-zlib was given. +if test "${with_zlib+set}" = set; then : + withval=$with_zlib; +else + with_zlib=auto +fi + + + if test "$with_zlib" != "no"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5 +$as_echo_n "checking for library containing zlibVersion... " >&6; } +if test "${ac_cv_search_zlibVersion+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char zlibVersion (); +int +main () +{ +return zlibVersion (); + ; + return 0; +} +_ACEOF +for ac_lib in '' z; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_zlibVersion=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_zlibVersion+set}" = set; then : + break +fi +done +if test "${ac_cv_search_zlibVersion+set}" = set; then : + +else + ac_cv_search_zlibVersion=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_zlibVersion" >&5 +$as_echo "$ac_cv_search_zlibVersion" >&6; } +ac_res=$ac_cv_search_zlibVersion +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + for ac_header in zlib.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default" +if test "x$ac_cv_header_zlib_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ZLIB_H 1 +_ACEOF + +fi + +done + +fi + + if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then + as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 + fi + fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then : + enableval=$enable_maintainer_mode; case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) as_fn_error "\"--enable-maintainer-mode does not take a value\"" "$LINENO" 5; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then : + enableval=$enable_sim_bswap; case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) as_fn_error "\"--enable-sim-bswap does not take a value\"" "$LINENO" 5; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then : + enableval=$enable_sim_cflags; case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) as_fn_error "\"Please use --enable-sim-debug instead.\"" "$LINENO" 5; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then : + enableval=$enable_sim_debug; case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then : + enableval=$enable_sim_stdio; case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-stdio\"" "$LINENO" 5; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then : + enableval=$enable_sim_trace; case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then : + enableval=$enable_sim_profile; case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + + +# Check whether --with-pkgversion was given. +if test "${with_pkgversion+set}" = set; then : + withval=$with_pkgversion; case "$withval" in + yes) as_fn_error "package version not specified" "$LINENO" 5 ;; + no) PKGVERSION= ;; + *) PKGVERSION="($withval) " ;; + esac +else + PKGVERSION="(GDB) " + +fi + + + + + +# Check whether --with-bugurl was given. +if test "${with_bugurl+set}" = set; then : + withval=$with_bugurl; case "$withval" in + yes) as_fn_error "bug URL not specified" "$LINENO" 5 ;; + no) BUGURL= + ;; + *) BUGURL="$withval" + ;; + esac +else + BUGURL="http://www.gnu.org/software/gdb/bugs/" + +fi + + case ${BUGURL} in + "") + REPORT_BUGS_TO= + REPORT_BUGS_TEXI= + ;; + *) + REPORT_BUGS_TO="<$BUGURL>" + REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`} + ;; + esac; + + + + +cat >>confdefs.h <<_ACEOF +#define PKGVERSION "$PKGVERSION" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define REPORT_BUGS_TO "$REPORT_BUGS_TO" +_ACEOF + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_type_signal=int +else + ac_cv_type_signal=void +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + + +wire_endian="LITTLE_ENDIAN" +default_endian="" +# Check whether --enable-sim-endian was given. +if test "${enable_sim_endian+set}" = set; then : + enableval=$enable_sim_endian; case "${enableval}" in + b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";; + yes) if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + if test x"$default_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}" + else + echo "No hard-wired endian for target $target" 1>&6 + sim_endian="-DWITH_TARGET_BYTE_ORDER=0" + fi + fi;; + no) if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" + else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}" + else + echo "No default endian for target $target" 1>&6 + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0" + fi + fi;; + *) as_fn_error "\"Unknown value $enableval for --enable-sim-endian\"" "$LINENO" 5; sim_endian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then + echo "Setting endian flags = $sim_endian" 6>&1 +fi +else + if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" +else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + sim_endian= + fi +fi +fi + +wire_alignment="STRICT_ALIGNMENT" +default_alignment="STRICT_ALIGNMENT" + +# Check whether --enable-sim-alignment was given. +if test "${enable_sim_alignment+set}" = set; then : + enableval=$enable_sim_alignment; case "${enableval}" in + strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";; + nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";; + forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";; + yes) if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${default_alignment}" + else + echo "No hard-wired alignment for target $target" 1>&6 + sim_alignment="-DWITH_ALIGNMENT=0" + fi + fi;; + no) if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" + else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}" + else + echo "No default alignment for target $target" 1>&6 + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0" + fi + fi;; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-alignment\"" "$LINENO" 5; sim_alignment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then + echo "Setting alignment flags = $sim_alignment" 6>&1 +fi +else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" +else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + sim_alignment= + fi +fi +fi + + +# Check whether --enable-sim-hostendian was given. +if test "${enable_sim_hostendian+set}" = set; then : + enableval=$enable_sim_hostendian; case "${enableval}" in + no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";; + b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";; + *) as_fn_error "\"Unknown value $enableval for --enable-sim-hostendian\"" "$LINENO" 5; sim_hostendian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then + echo "Setting hostendian flags = $sim_hostendian" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 +$as_echo_n "checking whether byte ordering is bigendian... " >&6; } +if test "${ac_cv_c_bigendian+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_c_bigendian=unknown + # See if we're dealing with a universal compiler. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifndef __APPLE_CC__ + not a universal capable compiler + #endif + typedef int dummy; + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + + # Check for potential -arch flags. It is not universal unless + # there are at least two -arch flags with different values. + ac_arch= + ac_prev= + for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do + if test -n "$ac_prev"; then + case $ac_word in + i?86 | x86_64 | ppc | ppc64) + if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then + ac_arch=$ac_word + else + ac_cv_c_bigendian=universal + break + fi + ;; + esac + ac_prev= + elif test "x$ac_word" = "x-arch"; then + ac_prev=arch + fi + done +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test $ac_cv_c_bigendian = unknown; then + # See if sys/param.h defines the BYTE_ORDER macro. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \ + && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \ + && LITTLE_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + #include + +int +main () +{ +#if BYTE_ORDER != BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # See if defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris). + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + # It does; now see whether it defined to _BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +int +main () +{ +#ifndef _BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # Compile a test program. + if test "$cross_compiling" = yes; then : + # Try to guess by grepping values from an object file. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +short int ascii_mm[] = + { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; + short int ascii_ii[] = + { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; + int use_ascii (int i) { + return ascii_mm[i] + ascii_ii[i]; + } + short int ebcdic_ii[] = + { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; + short int ebcdic_mm[] = + { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; + int use_ebcdic (int i) { + return ebcdic_mm[i] + ebcdic_ii[i]; + } + extern int foo; + +int +main () +{ +return use_ascii (foo) == use_ebcdic (foo); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then + ac_cv_c_bigendian=yes + fi + if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then + if test "$ac_cv_c_bigendian" = unknown; then + ac_cv_c_bigendian=no + else + # finding both strings is unlikely to happen, but who knows? + ac_cv_c_bigendian=unknown + fi + fi +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Are we little or big endian? From Harbison&Steele. */ + union + { + long int l; + char c[sizeof (long int)]; + } u; + u.l = 1; + return u.c[sizeof (long int) - 1] == 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + ac_cv_c_bigendian=no +else + ac_cv_c_bigendian=yes +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 +$as_echo "$ac_cv_c_bigendian" >&6; } + case $ac_cv_c_bigendian in #( + yes) + $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h +;; #( + no) + ;; #( + universal) + +$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h + + ;; #( + *) + as_fn_error "unknown endianness + presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;; + esac + + if test $ac_cv_c_bigendian = yes; then + sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN" + else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN" + fi +else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=0" +fi +fi + + +default_sim_default_model="bf537" +# Check whether --enable-sim-default-model was given. +if test "${enable_sim_default_model+set}" = set; then : + enableval=$enable_sim_default_model; case "${enableval}" in + yes|no) as_fn_error "\"Missing argument to --enable-sim-default-model\"" "$LINENO" 5;; + *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";; +esac +if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then + echo "Setting default model = $sim_default_model" 6>&1 +fi +else + sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'" +fi + + + +# Check whether --enable-sim-environment was given. +if test "${enable_sim_environment+set}" = set; then : + enableval=$enable_sim_environment; case "${enableval}" in + all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";; + user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";; + virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";; + operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-environment\"" "$LINENO" 5; + sim_environment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then + echo "Setting sim environment = $sim_environment" 6>&1 +fi +else + sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT" +fi + + +default_sim_inline="" +# Check whether --enable-sim-inline was given. +if test "${enable_sim_inline+set}" = set; then : + enableval=$enable_sim_inline; sim_inline="" +case "$enableval" in + no) sim_inline="-DDEFAULT_INLINE=0";; + 0) sim_inline="-DDEFAULT_INLINE=0";; + yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";; + 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";; + *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + new_flag="" + case "$x" in + *_INLINE=*) new_flag="-D$x";; + *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;; + *_INLINE) new_flag="-D$x=ALL_C_INLINE";; + *) new_flag="-D$x""_INLINE=ALL_C_INLINE";; + esac + if test x"$sim_inline" = x""; then + sim_inline="$new_flag" + else + sim_inline="$sim_inline $new_flag" + fi + done;; +esac +if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then + echo "Setting inline flags = $sim_inline" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then + sim_inline="${default_sim_inline}" + if test x"$silent" != x"yes"; then + echo "Setting inline flags = $sim_inline" 6>&1 + fi + else + sim_inline="" + fi +else + sim_inline="-DDEFAULT_INLINE=0" +fi +fi + + +# NOTE: Don't add -Wall or -Wunused, they both include +# -Wunused-parameter which reports bogus warnings. +# NOTE: If you add to this list, remember to update +# gdb/doc/gdbint.texinfo. +build_warnings="-Wimplicit -Wreturn-type -Wcomment -Wtrigraphs \ +-Wformat -Wparentheses -Wpointer-arith" +# GCC supports -Wuninitialized only with -O or -On, n != 0. +if test x${CFLAGS+set} = xset; then + case "${CFLAGS}" in + *"-O0"* ) ;; + *"-O"* ) + build_warnings="${build_warnings} -Wuninitialized" + ;; + esac +else + build_warnings="${build_warnings} -Wuninitialized" +fi +# Up for debate: -Wswitch -Wcomment -trigraphs -Wtrigraphs +# -Wunused-function -Wunused-label -Wunused-variable -Wunused-value +# -Wchar-subscripts -Wtraditional -Wshadow -Wcast-qual +# -Wcast-align -Wwrite-strings -Wconversion -Wstrict-prototypes +# -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls +# -Woverloaded-virtual -Winline -Werror" +# Check whether --enable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then : + enableval=$enable_build_warnings; case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting compiler warning flags = $build_warnings" 6>&1 +fi +fi +# Check whether --enable-sim-build-warnings was given. +if test "${enable_sim_build_warnings+set}" = set; then : + enableval=$enable_sim_build_warnings; case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting GDB specific compiler warning flags = $build_warnings" 6>&1 +fi +fi +WARN_CFLAGS="" +WERROR_CFLAGS="" +if test "x${build_warnings}" != x -a "x$GCC" = xyes +then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking compiler warning flags" >&5 +$as_echo_n "checking compiler warning flags... " >&6; } + # Separate out the -Werror flag as some files just cannot be + # compiled with it enabled. + for w in ${build_warnings}; do + case $w in + -Werr*) WERROR_CFLAGS=-Werror ;; + *) # Check that GCC accepts it + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $w" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + WARN_CFLAGS="${WARN_CFLAGS} $w" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CFLAGS="$saved_CFLAGS" + esac + done + { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${WARN_CFLAGS}${WERROR_CFLAGS}" >&5 +$as_echo "${WARN_CFLAGS}${WERROR_CFLAGS}" >&6; } +fi + + +if test x"yes" = x"yes"; then + sim_hw_p=yes +else + sim_hw_p=no +fi +if test ""; then + hardware="" +else + hardware="cfi core pal glue" +fi +hardware="$hardware \ + bfin_cec \ + bfin_ctimer \ + bfin_dma \ + bfin_dmac \ + bfin_ebiu_amc \ + bfin_ebiu_ddrc \ + bfin_ebiu_sdc \ + bfin_emac \ + bfin_eppi \ + bfin_evt \ + bfin_gpio \ + bfin_gptimer \ + bfin_jtag \ + bfin_mmu \ + bfin_nfc \ + bfin_otp \ + bfin_pll \ + bfin_ppi \ + bfin_rtc \ + bfin_sic \ + bfin_spi \ + bfin_trace \ + bfin_twi \ + bfin_uart \ + bfin_uart2 \ + bfin_wdog \ + bfin_wp \ + eth_phy \ +" +sim_hw_cflags="-DWITH_HW=1" +sim_hw="$hardware" +sim_hw_objs="\$(SIM_COMMON_HW_OBJS) `echo $sim_hw | sed -e 's/\([^ ][^ ]*\)/dv-\1.o/g'`" +# Check whether --enable-sim-hardware was given. +if test "${enable_sim_hardware+set}" = set; then : + enableval=$enable_sim_hardware; +case "${enableval}" in + yes) sim_hw_p=yes;; + no) sim_hw_p=no;; + ,*) sim_hw_p=yes; hardware="${hardware} `echo ${enableval} | sed -e 's/,/ /'`";; + *,) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'` ${hardware}";; + *) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'`"'';; +esac +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +else + sim_hw_cflags="-DWITH_HW=1" + # remove duplicates + sim_hw="" + sim_hw_objs="\$(SIM_COMMON_HW_OBJS)" + for i in $hardware ; do + case " $sim_hw " in + *" $i "*) ;; + *) sim_hw="$sim_hw $i" ; sim_hw_objs="$sim_hw_objs dv-$i.o";; + esac + done +fi +if test x"$silent" != x"yes" && test "$sim_hw_p" = "yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi +else + +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +fi +if test x"$silent" != x"yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi +fi + + +for ac_func in getuid getgid geteuid getegid setuid setgid mmap munmap kill pread +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +for ac_header in sys/ioctl.h sys/mman.h net/if.h linux/if_tun.h linux/mii.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +BFIN_SIM_EXTRA_OBJS= + +case ${host} in + *mingw32*) ;; + *) + +cat >>confdefs.h <<_ACEOF +#define HAVE_DV_SOCKSER 1 +_ACEOF + + BFIN_SIM_EXTRA_OBJS="${BFIN_SIM_EXTRA_OBJS} dv-sockser.o" + ;; +esac + +BFIN_SIM_EXTRA_OBJS=${BFIN_SIM_EXTRA_OBJS} + + + + + + + + +if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. +set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_PKG_CONFIG+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $PKG_CONFIG in + [\\/]* | ?:[\\/]*) + ac_cv_path_PKG_CONFIG="$PKG_CONFIG" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + ;; +esac +fi +PKG_CONFIG=$ac_cv_path_PKG_CONFIG +if test -n "$PKG_CONFIG"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $PKG_CONFIG" >&5 +$as_echo "$PKG_CONFIG" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_path_PKG_CONFIG"; then + ac_pt_PKG_CONFIG=$PKG_CONFIG + # Extract the first word of "pkg-config", so it can be a program name with args. +set dummy pkg-config; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_ac_pt_PKG_CONFIG+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + case $ac_pt_PKG_CONFIG in + [\\/]* | ?:[\\/]*) + ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + ;; +esac +fi +ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG +if test -n "$ac_pt_PKG_CONFIG"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 +$as_echo "$ac_pt_PKG_CONFIG" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_pt_PKG_CONFIG" = x; then + PKG_CONFIG="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + PKG_CONFIG=$ac_pt_PKG_CONFIG + fi +else + PKG_CONFIG="$ac_cv_path_PKG_CONFIG" +fi + +fi +if test -n "$PKG_CONFIG"; then + _pkg_min_version=0.9.0 + { $as_echo "$as_me:${as_lineno-$LINENO}: checking pkg-config is at least version $_pkg_min_version" >&5 +$as_echo_n "checking pkg-config is at least version $_pkg_min_version... " >&6; } + if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + PKG_CONFIG="" + fi +fi + +pkg_failed=no +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SDL" >&5 +$as_echo_n "checking for SDL... " >&6; } + +if test -n "$SDL_CFLAGS"; then + pkg_cv_SDL_CFLAGS="$SDL_CFLAGS" + elif test -n "$PKG_CONFIG"; then + if test -n "$PKG_CONFIG" && \ + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"sdl\""; } >&5 + ($PKG_CONFIG --exists --print-errors "sdl") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + pkg_cv_SDL_CFLAGS=`$PKG_CONFIG --cflags "sdl" 2>/dev/null` +else + pkg_failed=yes +fi + else + pkg_failed=untried +fi +if test -n "$SDL_LIBS"; then + pkg_cv_SDL_LIBS="$SDL_LIBS" + elif test -n "$PKG_CONFIG"; then + if test -n "$PKG_CONFIG" && \ + { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"sdl\""; } >&5 + ($PKG_CONFIG --exists --print-errors "sdl") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + pkg_cv_SDL_LIBS=`$PKG_CONFIG --libs "sdl" 2>/dev/null` +else + pkg_failed=yes +fi + else + pkg_failed=untried +fi + + + +if test $pkg_failed = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + +if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then + _pkg_short_errors_supported=yes +else + _pkg_short_errors_supported=no +fi + if test $_pkg_short_errors_supported = yes; then + SDL_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors "sdl" 2>&1` + else + SDL_PKG_ERRORS=`$PKG_CONFIG --print-errors "sdl" 2>&1` + fi + # Put the nasty error message in config.log where it belongs + echo "$SDL_PKG_ERRORS" >&5 + + : +elif test $pkg_failed = untried; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + : +else + SDL_CFLAGS=$pkg_cv_SDL_CFLAGS + SDL_LIBS=$pkg_cv_SDL_LIBS + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 +$as_echo_n "checking for dlopen in -ldl... " >&6; } +if test "${ac_cv_lib_dl_dlopen+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_dl_dlopen=yes +else + ac_cv_lib_dl_dlopen=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 +$as_echo "$ac_cv_lib_dl_dlopen" >&6; } +if test "x$ac_cv_lib_dl_dlopen" = x""yes; then : + + SDL_CFLAGS="${SDL_CFLAGS} -DHAVE_SDL" + SDL_LIBS="-ldl" + +else + SDL_CFLAGS= SDL_LIBS= +fi + + +fi + + + + +ac_sources="$sim_link_files" +ac_dests="$sim_link_links" +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source" +done +ac_config_links="$ac_config_links $ac_config_links_1" + +cgen_breaks="" +if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then +cgen_breaks="break cgen_rtx_error"; +fi + +ac_config_files="$ac_config_files Makefile.sim:Makefile.in" + +ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in" + +ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in" + +ac_config_commands="$ac_config_commands Makefile" + +ac_config_commands="$ac_config_commands stamp-h" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_links="$ac_config_links" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration links: +$config_links + +Configuration commands: +$config_commands + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; + "$ac_config_links_1") CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;; + "Makefile.sim") CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;; + "Make-common.sim") CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;; + ".gdbinit") CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;; + "Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;; + "stamp-h") CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :L $CONFIG_LINKS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). 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Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + :L) + # + # CONFIG_LINK + # + + if test "$ac_source" = "$ac_file" && test "$srcdir" = '.'; then + : + else + # Prefer the file from the source tree if names are identical. + if test "$ac_source" = "$ac_file" || test ! -r "$ac_source"; then + ac_source=$srcdir/$ac_source + fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: linking $ac_source to $ac_file" >&5 +$as_echo "$as_me: linking $ac_source to $ac_file" >&6;} + + if test ! -r "$ac_source"; then + as_fn_error "$ac_source: file not found" "$LINENO" 5 + fi + rm -f "$ac_file" + + # Try a relative symlink, then a hard link, then a copy. + case $srcdir in + [\\/$]* | ?:[\\/]* ) ac_rel_source=$ac_source ;; + *) ac_rel_source=$ac_top_build_prefix$ac_source ;; + esac + ln -s "$ac_rel_source" "$ac_file" 2>/dev/null || + ln "$ac_source" "$ac_file" 2>/dev/null || + cp -p "$ac_source" "$ac_file" || + as_fn_error "cannot link or copy $ac_source to $ac_file" "$LINENO" 5 + fi + ;; + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "Makefile":C) echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + "stamp-h":C) echo > stamp-h ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + + diff --git a/external/gpl3/gdb/dist/sim/bfin/configure.ac b/external/gpl3/gdb/dist/sim/bfin/configure.ac new file mode 100644 index 000000000000..6c031077bda0 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/configure.ac @@ -0,0 +1,76 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(config.h:config.in) + +sinclude(../common/aclocal.m4) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN) +SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT,STRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_DEFAULT_MODEL(bf537) +SIM_AC_OPTION_ENVIRONMENT +SIM_AC_OPTION_INLINE +SIM_AC_OPTION_WARNINGS +SIM_AC_OPTION_HARDWARE(yes,,\ + bfin_cec \ + bfin_ctimer \ + bfin_dma \ + bfin_dmac \ + bfin_ebiu_amc \ + bfin_ebiu_ddrc \ + bfin_ebiu_sdc \ + bfin_emac \ + bfin_eppi \ + bfin_evt \ + bfin_gpio \ + bfin_gptimer \ + bfin_jtag \ + bfin_mmu \ + bfin_nfc \ + bfin_otp \ + bfin_pll \ + bfin_ppi \ + bfin_rtc \ + bfin_sic \ + bfin_spi \ + bfin_trace \ + bfin_twi \ + bfin_uart \ + bfin_uart2 \ + bfin_wdog \ + bfin_wp \ + eth_phy \ +) + +AC_CHECK_FUNCS([getuid getgid geteuid getegid setuid setgid mmap munmap kill pread]) +AC_CHECK_HEADERS([sys/ioctl.h sys/mman.h net/if.h linux/if_tun.h linux/mii.h]) + +BFIN_SIM_EXTRA_OBJS= + +dnl make sure the dv-sockser code can be supported (i.e. windows) +case ${host} in + *mingw32*) ;; + *) + AC_DEFINE_UNQUOTED([HAVE_DV_SOCKSER], 1, [Define if dv-sockser is usable.]) + BFIN_SIM_EXTRA_OBJS="${BFIN_SIM_EXTRA_OBJS} dv-sockser.o" + ;; +esac + +AC_SUBST([BFIN_SIM_EXTRA_OBJS], ${BFIN_SIM_EXTRA_OBJS}) + +PKG_PROG_PKG_CONFIG +PKG_CHECK_MODULES(SDL, sdl, [ + AC_CHECK_LIB(dl, dlopen, [ + SDL_CFLAGS="${SDL_CFLAGS} -DHAVE_SDL" + SDL_LIBS="-ldl" + ], [SDL_CFLAGS= SDL_LIBS=]) + ], [:]) +AC_SUBST(SDL_CFLAGS) +AC_SUBST(SDL_LIBS) + +SIM_AC_OUTPUT diff --git a/external/gpl3/gdb/dist/sim/bfin/devices.c b/external/gpl3/gdb/dist/sim/bfin/devices.c new file mode 100644 index 000000000000..50c53d104452 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/devices.c @@ -0,0 +1,163 @@ +/* Blackfin device support. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "sim-hw.h" +#include "hw-device.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_mmu.h" + +static void +bfin_mmr_invalid (struct hw *me, SIM_CPU *cpu, address_word addr, + unsigned nr_bytes, bool write) +{ + if (!cpu) + cpu = hw_system_cpu (me); + + /* Only throw a fit if the cpu is doing the access. DMA/GDB simply + go unnoticed. Not exactly hardware behavior, but close enough. */ + if (!cpu) + { + sim_io_eprintf (hw_system (me), "%s: invalid MMR access @ %#x\n", + hw_path (me), addr); + return; + } + + HW_TRACE ((me, "invalid MMR %s to 0x%08lx length %u", + write ? "write" : "read", (unsigned long) addr, nr_bytes)); + + /* XXX: is this what hardware does ? */ + if (addr >= BFIN_CORE_MMR_BASE) + /* XXX: This should be setting up CPLB fault addrs ? */ + mmu_process_fault (cpu, addr, write, false, false, true); + else + /* XXX: Newer parts set up an interrupt from EBIU and program + EBIU_ERRADDR with the address. */ + cec_hwerr (cpu, HWERR_SYSTEM_MMR); +} + +void +dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes, + bool write) +{ + bfin_mmr_invalid (me, NULL, addr, nr_bytes, write); +} + +void +dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes, + unsigned size, bool write) +{ + if (nr_bytes != size) + dv_bfin_mmr_invalid (me, addr, nr_bytes, write); +} + +static bool +bfin_mmr_check (struct hw *me, SIM_CPU *cpu, address_word addr, + unsigned nr_bytes, bool write) +{ + if (addr >= BFIN_CORE_MMR_BASE) + { + /* All Core MMRs are aligned 32bits. */ + if ((addr & 3) == 0 && nr_bytes == 4) + return true; + } + else if (addr >= BFIN_SYSTEM_MMR_BASE) + { + /* All System MMRs are 32bit aligned, but can be 16bits or 32bits. */ + if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4)) + return true; + } + else + return true; + + /* Still here ? Must be crap. */ + bfin_mmr_invalid (me, cpu, addr, nr_bytes, write); + + return false; +} + +bool +dv_bfin_mmr_check (struct hw *me, address_word addr, unsigned nr_bytes, + bool write) +{ + return bfin_mmr_check (me, NULL, addr, nr_bytes, write); +} + +int +device_io_read_buffer (device *me, void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) +{ + struct hw *dv_me = (struct hw *) me; + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + return nr_bytes; + + if (bfin_mmr_check (dv_me, cpu, addr, nr_bytes, false)) + if (cpu) + { + sim_cpu_hw_io_read_buffer (cpu, cia, dv_me, source, space, + addr, nr_bytes); + return nr_bytes; + } + else + return sim_hw_io_read_buffer (sd, dv_me, source, space, addr, nr_bytes); + else + return 0; +} + +int +device_io_write_buffer (device *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) +{ + struct hw *dv_me = (struct hw *) me; + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + return nr_bytes; + + if (bfin_mmr_check (dv_me, cpu, addr, nr_bytes, true)) + if (cpu) + { + sim_cpu_hw_io_write_buffer (cpu, cia, dv_me, source, space, + addr, nr_bytes); + return nr_bytes; + } + else + return sim_hw_io_write_buffer (sd, dv_me, source, space, addr, nr_bytes); + else + return 0; +} + +void device_error (device *me, const char *message, ...) +{ + /* Don't bother doing anything here -- any place in common code that + calls device_error() follows it with sim_hw_abort(). Since the + device isn't bound to the system yet, we can't call any common + hardware error funcs on it or we'll hit a NULL pointer. */ +} + +unsigned int dv_get_bus_num (struct hw *me) +{ + const hw_unit *unit = hw_unit_address (me); + return unit->cells[unit->nr_cells - 1]; +} diff --git a/external/gpl3/gdb/dist/sim/bfin/devices.h b/external/gpl3/gdb/dist/sim/bfin/devices.h new file mode 100644 index 000000000000..3dc5481a1169 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/devices.h @@ -0,0 +1,156 @@ +/* Common Blackfin device stuff. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DEVICES_H +#define DEVICES_H + +#include "hw-base.h" +#include "hw-main.h" +#include "hw-device.h" +#include "hw-tree.h" + +/* We keep the same inital structure layout with DMA enabled devices. */ +struct dv_bfin { + bu32 base; + struct hw *dma_master; + bool acked; +}; + +#define BFIN_MMR_16(mmr) mmr, __pad_##mmr + +/* Most peripherals have either one interrupt or these three. */ +#define DV_PORT_TX 0 +#define DV_PORT_RX 1 +#define DV_PORT_STAT 2 + +unsigned int dv_get_bus_num (struct hw *); + +static inline bu8 dv_load_1 (const void *ptr) +{ + const unsigned char *c = ptr; + return c[0]; +} + +static inline void dv_store_1 (void *ptr, bu8 val) +{ + unsigned char *c = ptr; + c[0] = val; +} + +static inline bu16 dv_load_2 (const void *ptr) +{ + const unsigned char *c = ptr; + return (c[1] << 8) | dv_load_1 (ptr); +} + +static inline void dv_store_2 (void *ptr, bu16 val) +{ + unsigned char *c = ptr; + c[1] = val >> 8; + dv_store_1 (ptr, val); +} + +static inline bu32 dv_load_4 (const void *ptr) +{ + const unsigned char *c = ptr; + return (c[3] << 24) | (c[2] << 16) | dv_load_2 (ptr); +} + +static inline void dv_store_4 (void *ptr, bu32 val) +{ + unsigned char *c = ptr; + c[3] = val >> 24; + c[2] = val >> 16; + dv_store_2 (ptr, val); +} + +/* Helpers for MMRs where only the specified bits are W1C. The + rest are left unmodified. */ +#define dv_w1c(ptr, val, bits) (*(ptr) &= ~((val) & (bits))) +static inline void dv_w1c_2 (bu16 *ptr, bu16 val, bu16 bits) +{ + dv_w1c (ptr, val, bits); +} +static inline void dv_w1c_4 (bu32 *ptr, bu32 val, bu32 bits) +{ + dv_w1c (ptr, val, bits); +} + +/* Helpers for MMRs where all bits are RW except for the specified + bits -- those ones are W1C. */ +#define dv_w1c_partial(ptr, val, bits) \ + (*(ptr) = ((val) | (*(ptr) & (bits))) & ~((val) & (bits))) +static inline void dv_w1c_2_partial (bu16 *ptr, bu16 val, bu16 bits) +{ + dv_w1c_partial (ptr, val, bits); +} +static inline void dv_w1c_4_partial (bu32 *ptr, bu32 val, bu32 bits) +{ + dv_w1c_partial (ptr, val, bits); +} + +/* XXX: Grubbing around in device internals is probably wrong, but + until someone shows me what's right ... */ +static inline struct hw * +dv_get_device (SIM_CPU *cpu, const char *device_name) +{ + SIM_DESC sd = CPU_STATE (cpu); + void *root = STATE_HW (sd); + return hw_tree_find_device (root, device_name); +} + +static inline void * +dv_get_state (SIM_CPU *cpu, const char *device_name) +{ + return hw_data (dv_get_device (cpu, device_name)); +} + +#define DV_STATE(cpu, dv) dv_get_state (cpu, "/core/bfin_"#dv) + +#define DV_STATE_CACHED(cpu, dv) \ + ({ \ + struct bfin_##dv *__##dv = BFIN_CPU_STATE.dv##_cache; \ + if (!__##dv) \ + BFIN_CPU_STATE.dv##_cache = __##dv = dv_get_state (cpu, "/core/bfin_"#dv); \ + __##dv; \ + }) + +void dv_bfin_mmr_invalid (struct hw *, address_word, unsigned nr_bytes, bool write); +void dv_bfin_mmr_require (struct hw *, address_word, unsigned nr_bytes, unsigned size, bool write); +bool dv_bfin_mmr_check (struct hw *, address_word, unsigned nr_bytes, bool write); + +#define dv_bfin_mmr_require_16(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 2, write) +#define dv_bfin_mmr_require_32(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 4, write) + +#define HW_TRACE_WRITE() \ + HW_TRACE ((me, "write 0x%08lx (%s) length %u with 0x%x", \ + (unsigned long) addr, mmr_name (mmr_off), nr_bytes, value)) +#define HW_TRACE_READ() \ + HW_TRACE ((me, "read 0x%08lx (%s) length %u", \ + (unsigned long) addr, mmr_name (mmr_off), nr_bytes)) + +#define HW_TRACE_DMA_WRITE() \ + HW_TRACE ((me, "dma write 0x%08lx length %u", \ + (unsigned long) addr, nr_bytes)) +#define HW_TRACE_DMA_READ() \ + HW_TRACE ((me, "dma read 0x%08lx length %u", \ + (unsigned long) addr, nr_bytes)) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.c new file mode 100644 index 000000000000..0c6a8235a6de --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.c @@ -0,0 +1,811 @@ +/* Blackfin Core Event Controller (CEC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_evt.h" +#include "dv-bfin_mmu.h" + +struct bfin_cec +{ + bu32 base; + SIM_CPU *cpu; + struct hw *me; + struct hw_event *pending; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 evt_override, imask, ipend, ilat, iprio; +}; +#define mmr_base() offsetof(struct bfin_cec, evt_override) +#define mmr_offset(mmr) (offsetof(struct bfin_cec, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "EVT_OVERRIDE", "IMASK", "IPEND", "ILAT", "IPRIO", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static void _cec_raise (SIM_CPU *, struct bfin_cec *, int); + +static void +bfin_cec_hw_event_callback (struct hw *me, void *data) +{ + struct bfin_cec *cec = data; + hw_event_queue_deschedule (me, cec->pending); + _cec_raise (cec->cpu, cec, -1); + cec->pending = NULL; +} +static void +bfin_cec_check_pending (struct hw *me, struct bfin_cec *cec) +{ + if (cec->pending) + return; + cec->pending = hw_event_queue_schedule (me, 0, bfin_cec_hw_event_callback, cec); +} +static void +_cec_check_pending (SIM_CPU *cpu, struct bfin_cec *cec) +{ + bfin_cec_check_pending (cec->me, cec); +} + +static void +_cec_imask_write (struct bfin_cec *cec, bu32 value) +{ + cec->imask = (value & IVG_MASKABLE_B) | (cec->imask & IVG_UNMASKABLE_B); +} + +static unsigned +bfin_cec_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_cec *cec = hw_data (me); + bu32 mmr_off; + bu32 value; + + value = dv_load_4 (source); + mmr_off = addr - cec->base; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(evt_override): + cec->evt_override = value; + break; + case mmr_offset(imask): + _cec_imask_write (cec, value); + bfin_cec_check_pending (me, cec); + break; + case mmr_offset(ipend): + /* Read-only register. */ + break; + case mmr_offset(ilat): + dv_w1c_4 (&cec->ilat, value, 0xffee); + break; + case mmr_offset(iprio): + cec->iprio = (value & IVG_UNMASKABLE_B); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_cec_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_cec *cec = hw_data (me); + bu32 mmr_off; + bu32 *valuep; + + mmr_off = addr - cec->base; + valuep = (void *)((unsigned long)cec + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_store_4 (dest, *valuep); + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_cec_ports[] = +{ + { "emu", IVG_EMU, 0, input_port, }, + { "rst", IVG_RST, 0, input_port, }, + { "nmi", IVG_NMI, 0, input_port, }, + { "evx", IVG_EVX, 0, input_port, }, + { "ivhw", IVG_IVHW, 0, input_port, }, + { "ivtmr", IVG_IVTMR, 0, input_port, }, + { "ivg7", IVG7, 0, input_port, }, + { "ivg8", IVG8, 0, input_port, }, + { "ivg9", IVG9, 0, input_port, }, + { "ivg10", IVG10, 0, input_port, }, + { "ivg11", IVG11, 0, input_port, }, + { "ivg12", IVG12, 0, input_port, }, + { "ivg13", IVG13, 0, input_port, }, + { "ivg14", IVG14, 0, input_port, }, + { "ivg15", IVG15, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_cec_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_cec *cec = hw_data (me); + _cec_raise (cec->cpu, cec, my_port); +} + +static void +attach_bfin_cec_regs (struct hw *me, struct bfin_cec *cec) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_CEC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CEC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + cec->base = attach_address; + /* XXX: should take from the device tree. */ + cec->cpu = STATE_CPU (hw_system (me), 0); + cec->me = me; +} + +static void +bfin_cec_finish (struct hw *me) +{ + struct bfin_cec *cec; + + cec = HW_ZALLOC (me, struct bfin_cec); + + set_hw_data (me, cec); + set_hw_io_read_buffer (me, bfin_cec_io_read_buffer); + set_hw_io_write_buffer (me, bfin_cec_io_write_buffer); + set_hw_ports (me, bfin_cec_ports); + set_hw_port_event (me, bfin_cec_port_event); + + attach_bfin_cec_regs (me, cec); + + /* Initialize the CEC. */ + cec->imask = IVG_UNMASKABLE_B; + cec->ipend = IVG_RST_B | IVG_IRPTEN_B; +} + +const struct hw_descriptor dv_bfin_cec_descriptor[] = +{ + {"bfin_cec", bfin_cec_finish,}, + {NULL, NULL}, +}; + +static const char * const excp_decoded[] = +{ + [VEC_SYS ] = "Custom exception 0 (system call)", + [VEC_EXCPT01 ] = "Custom exception 1 (software breakpoint)", + [VEC_EXCPT02 ] = "Custom exception 2 (KGDB hook)", + [VEC_EXCPT03 ] = "Custom exception 3 (userspace stack overflow)", + [VEC_EXCPT04 ] = "Custom exception 4 (dump trace buffer)", + [VEC_EXCPT05 ] = "Custom exception 5", + [VEC_EXCPT06 ] = "Custom exception 6", + [VEC_EXCPT07 ] = "Custom exception 7", + [VEC_EXCPT08 ] = "Custom exception 8", + [VEC_EXCPT09 ] = "Custom exception 9", + [VEC_EXCPT10 ] = "Custom exception 10", + [VEC_EXCPT11 ] = "Custom exception 11", + [VEC_EXCPT12 ] = "Custom exception 12", + [VEC_EXCPT13 ] = "Custom exception 13", + [VEC_EXCPT14 ] = "Custom exception 14", + [VEC_EXCPT15 ] = "Custom exception 15", + [VEC_STEP ] = "Hardware single step", + [VEC_OVFLOW ] = "Trace buffer overflow", + [VEC_UNDEF_I ] = "Undefined instruction", + [VEC_ILGAL_I ] = "Illegal instruction combo (multi-issue)", + [VEC_CPLB_VL ] = "DCPLB protection violation", + [VEC_MISALI_D ] = "Unaligned data access", + [VEC_UNCOV ] = "Unrecoverable event (double fault)", + [VEC_CPLB_M ] = "DCPLB miss", + [VEC_CPLB_MHIT ] = "Multiple DCPLB hit", + [VEC_WATCH ] = "Watchpoint match", + [VEC_ISTRU_VL ] = "ADSP-BF535 only", + [VEC_MISALI_I ] = "Unaligned instruction access", + [VEC_CPLB_I_VL ] = "ICPLB protection violation", + [VEC_CPLB_I_M ] = "ICPLB miss", + [VEC_CPLB_I_MHIT] = "Multiple ICPLB hit", + [VEC_ILL_RES ] = "Illegal supervisor resource", +}; + +#define CEC_STATE(cpu) DV_STATE_CACHED (cpu, cec) + +#define __cec_get_ivg(val) (ffs ((val) & ~IVG_IRPTEN_B) - 1) +#define _cec_get_ivg(cec) __cec_get_ivg ((cec)->ipend & ~IVG_EMU_B) + +int +cec_get_ivg (SIM_CPU *cpu) +{ + switch (STATE_ENVIRONMENT (CPU_STATE (cpu))) + { + case OPERATING_ENVIRONMENT: + return _cec_get_ivg (CEC_STATE (cpu)); + default: + return IVG_USER; + } +} + +static bool +_cec_is_supervisor_mode (struct bfin_cec *cec) +{ + return (cec->ipend & ~(IVG_EMU_B | IVG_IRPTEN_B)); +} +bool +cec_is_supervisor_mode (SIM_CPU *cpu) +{ + switch (STATE_ENVIRONMENT (CPU_STATE (cpu))) + { + case OPERATING_ENVIRONMENT: + return _cec_is_supervisor_mode (CEC_STATE (cpu)); + case USER_ENVIRONMENT: + return false; + default: + return true; + } +} +static bool +_cec_is_user_mode (struct bfin_cec *cec) +{ + return !_cec_is_supervisor_mode (cec); +} +bool +cec_is_user_mode (SIM_CPU *cpu) +{ + return !cec_is_supervisor_mode (cpu); +} +static void +_cec_require_supervisor (SIM_CPU *cpu, struct bfin_cec *cec) +{ + if (_cec_is_user_mode (cec)) + cec_exception (cpu, VEC_ILL_RES); +} +void +cec_require_supervisor (SIM_CPU *cpu) +{ + /* Do not call _cec_require_supervisor() to avoid CEC_STATE() + as that macro requires OS operating mode. */ + if (cec_is_user_mode (cpu)) + cec_exception (cpu, VEC_ILL_RES); +} + +#define excp_to_sim_halt(reason, sigrc) \ + sim_engine_halt (CPU_STATE (cpu), cpu, NULL, PCREG, reason, sigrc) +void +cec_exception (SIM_CPU *cpu, int excp) +{ + SIM_DESC sd = CPU_STATE (cpu); + int sigrc = -1; + + TRACE_EVENTS (cpu, "processing exception %#x in EVT%i", excp, + cec_get_ivg (cpu)); + + /* Ideally what would happen here for real hardware exceptions (not + fake sim ones) is that: + - For service exceptions (excp <= 0x11): + RETX is the _next_ PC which can be tricky with jumps/hardware loops/... + - For error exceptions (excp > 0x11): + RETX is the _current_ PC (i.e. the one causing the exception) + - PC is loaded with EVT3 MMR + - ILAT/IPEND in CEC is updated depending on current IVG level + - the fault address MMRs get updated with data/instruction info + - Execution continues on in the EVT3 handler */ + + /* Handle simulator exceptions first. */ + switch (excp) + { + case VEC_SIM_HLT: + excp_to_sim_halt (sim_exited, 0); + return; + case VEC_SIM_ABORT: + excp_to_sim_halt (sim_exited, 1); + return; + case VEC_SIM_TRAP: + /* GDB expects us to step over EMUEXCPT. */ + /* XXX: What about hwloops and EMUEXCPT at the end? + Pretty sure gdb doesn't handle this already... */ + SET_PCREG (PCREG + 2); + /* Only trap when we are running in gdb. */ + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + excp_to_sim_halt (sim_stopped, SIM_SIGTRAP); + return; + case VEC_SIM_DBGA: + /* If running in gdb, simply trap. */ + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + excp_to_sim_halt (sim_stopped, SIM_SIGTRAP); + else + excp_to_sim_halt (sim_exited, 2); + } + + if (excp <= 0x3f) + { + SET_EXCAUSE (excp); + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) + { + /* ICPLB regs always get updated. */ + /* XXX: Should optimize this call path ... */ + if (excp != VEC_MISALI_I && excp != VEC_MISALI_D + && excp != VEC_CPLB_I_M && excp != VEC_CPLB_M + && excp != VEC_CPLB_I_VL && excp != VEC_CPLB_VL + && excp != VEC_CPLB_I_MHIT && excp != VEC_CPLB_MHIT) + mmu_log_ifault (cpu); + _cec_raise (cpu, CEC_STATE (cpu), IVG_EVX); + /* We need to restart the engine so that we don't return + and continue processing this bad insn. */ + if (EXCAUSE >= 0x20) + sim_engine_restart (sd, cpu, NULL, PCREG); + return; + } + } + + TRACE_EVENTS (cpu, "running virtual exception handler"); + + switch (excp) + { + case VEC_SYS: + bfin_syscall (cpu); + break; + + case VEC_EXCPT01: /* Userspace gdb breakpoint. */ + sigrc = SIM_SIGTRAP; + break; + + case VEC_UNDEF_I: /* Undefined instruction. */ + sigrc = SIM_SIGILL; + break; + + case VEC_ILL_RES: /* Illegal supervisor resource. */ + case VEC_MISALI_I: /* Misaligned instruction. */ + sigrc = SIM_SIGBUS; + break; + + case VEC_CPLB_M: + case VEC_CPLB_I_M: + sigrc = SIM_SIGSEGV; + break; + + default: + sim_io_eprintf (sd, "Unhandled exception %#x at 0x%08x (%s)\n", + excp, PCREG, excp_decoded[excp]); + sigrc = SIM_SIGILL; + break; + } + + if (sigrc != -1) + excp_to_sim_halt (sim_stopped, sigrc); +} + +bu32 cec_cli (SIM_CPU *cpu) +{ + struct bfin_cec *cec; + bu32 old_mask; + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + return 0; + + cec = CEC_STATE (cpu); + _cec_require_supervisor (cpu, cec); + + /* XXX: what about IPEND[4] ? */ + old_mask = cec->imask; + _cec_imask_write (cec, 0); + + TRACE_EVENTS (cpu, "CLI changed IMASK from %#x to %#x", old_mask, cec->imask); + + return old_mask; +} + +void cec_sti (SIM_CPU *cpu, bu32 ints) +{ + struct bfin_cec *cec; + bu32 old_mask; + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + return; + + cec = CEC_STATE (cpu); + _cec_require_supervisor (cpu, cec); + + /* XXX: what about IPEND[4] ? */ + old_mask = cec->imask; + _cec_imask_write (cec, ints); + + TRACE_EVENTS (cpu, "STI changed IMASK from %#x to %#x", old_mask, cec->imask); + + /* Check for pending interrupts that are now enabled. */ + _cec_check_pending (cpu, cec); +} + +static void +cec_irpten_enable (SIM_CPU *cpu, struct bfin_cec *cec) +{ + /* Globally mask interrupts. */ + TRACE_EVENTS (cpu, "setting IPEND[4] to globally mask interrupts"); + cec->ipend |= IVG_IRPTEN_B; +} + +static void +cec_irpten_disable (SIM_CPU *cpu, struct bfin_cec *cec) +{ + /* Clear global interrupt mask. */ + TRACE_EVENTS (cpu, "clearing IPEND[4] to not globally mask interrupts"); + cec->ipend &= ~IVG_IRPTEN_B; +} + +static void +_cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg) +{ + SIM_DESC sd = CPU_STATE (cpu); + int curr_ivg = _cec_get_ivg (cec); + bool snen; + bool irpten; + + TRACE_EVENTS (cpu, "processing request for EVT%i while at EVT%i", + ivg, curr_ivg); + + irpten = (cec->ipend & IVG_IRPTEN_B); + snen = (SYSCFGREG & SYSCFG_SNEN); + + if (curr_ivg == -1) + curr_ivg = IVG_USER; + + /* Just check for higher latched interrupts. */ + if (ivg == -1) + { + if (irpten) + goto done; /* All interrupts are masked anyways. */ + + ivg = __cec_get_ivg (cec->ilat & cec->imask); + if (ivg < 0) + goto done; /* Nothing latched. */ + + if (ivg > curr_ivg) + goto done; /* Nothing higher latched. */ + + if (!snen && ivg == curr_ivg) + goto done; /* Self nesting disabled. */ + + /* Still here, so fall through to raise to higher pending. */ + } + + cec->ilat |= (1 << ivg); + + if (ivg <= IVG_EVX) + { + /* These two are always processed. */ + if (ivg == IVG_EMU || ivg == IVG_RST) + goto process_int; + + /* Anything lower might trigger a double fault. */ + if (curr_ivg <= ivg) + { + /* Double fault ! :( */ + SET_EXCAUSE (VEC_UNCOV); + /* XXX: SET_RETXREG (...); */ + sim_io_error (sd, "%s: double fault at 0x%08x ! :(", __func__, PCREG); + excp_to_sim_halt (sim_stopped, SIM_SIGABRT); + } + + /* No double fault -> always process. */ + goto process_int; + } + else if (irpten && curr_ivg != IVG_USER) + { + /* Interrupts are globally masked. */ + } + else if (!(cec->imask & (1 << ivg))) + { + /* This interrupt is masked. */ + } + else if (ivg < curr_ivg || (snen && ivg == curr_ivg)) + { + /* Do transition! */ + bu32 oldpc; + + process_int: + cec->ipend |= (1 << ivg); + cec->ilat &= ~(1 << ivg); + + /* Interrupts are processed in between insns which means the return + point is the insn-to-be-executed (which is the current PC). But + exceptions are handled while executing an insn, so we may have to + advance the PC ourselves when setting RETX. + XXX: Advancing the PC should only be for "service" exceptions, and + handling them after executing the insn should be OK, which + means we might be able to use the event interface for it. */ + + oldpc = PCREG; + switch (ivg) + { + case IVG_EMU: + /* Signal the JTAG ICE. */ + /* XXX: what happens with 'raise 0' ? */ + SET_RETEREG (oldpc); + excp_to_sim_halt (sim_stopped, SIM_SIGTRAP); + /* XXX: Need an easy way for gdb to signal it isnt here. */ + cec->ipend &= ~IVG_EMU_B; + break; + case IVG_RST: + /* Have the core reset simply exit (i.e. "shutdown"). */ + excp_to_sim_halt (sim_exited, 0); + break; + case IVG_NMI: + /* XXX: Should check this. */ + SET_RETNREG (oldpc); + break; + case IVG_EVX: + /* Non-service exceptions point to the excepting instruction. */ + if (EXCAUSE >= 0x20) + SET_RETXREG (oldpc); + else + { + bu32 nextpc = hwloop_get_next_pc (cpu, oldpc, INSN_LEN); + SET_RETXREG (nextpc); + } + + break; + case IVG_IRPTEN: + /* XXX: what happens with 'raise 4' ? */ + sim_io_error (sd, "%s: what to do with 'raise 4' ?", __func__); + break; + default: + SET_RETIREG (oldpc | (ivg == curr_ivg ? 1 : 0)); + break; + } + + /* If EVT_OVERRIDE is in effect (IVG7+), use the reset address. */ + if ((cec->evt_override & 0xff80) & (1 << ivg)) + SET_PCREG (cec_get_reset_evt (cpu)); + else + SET_PCREG (cec_get_evt (cpu, ivg)); + + TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (to EVT%i):", ivg); + BFIN_CPU_STATE.did_jump = true; + + /* Enable the global interrupt mask upon interrupt entry. */ + if (ivg >= IVG_IVHW) + cec_irpten_enable (cpu, cec); + } + + /* When moving between states, don't let internal states bleed through. */ + DIS_ALGN_EXPT &= ~1; + + /* When going from user to super, we set LSB in LB regs to avoid + misbehavior and/or malicious code. + Also need to load SP alias with KSP. */ + if (curr_ivg == IVG_USER) + { + int i; + for (i = 0; i < 2; ++i) + if (!(LBREG (i) & 1)) + SET_LBREG (i, LBREG (i) | 1); + SET_USPREG (SPREG); + SET_SPREG (KSPREG); + } + + done: + TRACE_EVENTS (cpu, "now at EVT%i", _cec_get_ivg (cec)); +} + +static bu32 +cec_read_ret_reg (SIM_CPU *cpu, int ivg) +{ + switch (ivg) + { + case IVG_EMU: return RETEREG; + case IVG_NMI: return RETNREG; + case IVG_EVX: return RETXREG; + default: return RETIREG; + } +} + +void +cec_latch (SIM_CPU *cpu, int ivg) +{ + struct bfin_cec *cec; + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + { + bu32 oldpc = PCREG; + SET_PCREG (cec_read_ret_reg (cpu, ivg)); + TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC"); + return; + } + + cec = CEC_STATE (cpu); + cec->ilat |= (1 << ivg); + _cec_check_pending (cpu, cec); +} + +void +cec_hwerr (SIM_CPU *cpu, int hwerr) +{ + SET_HWERRCAUSE (hwerr); + cec_latch (cpu, IVG_IVHW); +} + +void +cec_return (SIM_CPU *cpu, int ivg) +{ + SIM_DESC sd = CPU_STATE (cpu); + struct bfin_cec *cec; + bool snen; + int curr_ivg; + bu32 oldpc, newpc; + + oldpc = PCREG; + + BFIN_CPU_STATE.did_jump = true; + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + { + SET_PCREG (cec_read_ret_reg (cpu, ivg)); + TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC"); + return; + } + + cec = CEC_STATE (cpu); + + /* XXX: This isn't entirely correct ... */ + cec->ipend &= ~IVG_EMU_B; + + curr_ivg = _cec_get_ivg (cec); + if (curr_ivg == -1) + curr_ivg = IVG_USER; + if (ivg == -1) + ivg = curr_ivg; + + TRACE_EVENTS (cpu, "returning from EVT%i (should be EVT%i)", curr_ivg, ivg); + + /* Not allowed to return from usermode. */ + if (curr_ivg == IVG_USER) + cec_exception (cpu, VEC_ILL_RES); + + if (ivg > IVG15 || ivg < 0) + sim_io_error (sd, "%s: ivg %i out of range !", __func__, ivg); + + _cec_require_supervisor (cpu, cec); + + switch (ivg) + { + case IVG_EMU: + /* RTE -- only valid in emulation mode. */ + /* XXX: What does the hardware do ? */ + if (curr_ivg != IVG_EMU) + cec_exception (cpu, VEC_ILL_RES); + break; + case IVG_NMI: + /* RTN -- only valid in NMI. */ + /* XXX: What does the hardware do ? */ + if (curr_ivg != IVG_NMI) + cec_exception (cpu, VEC_ILL_RES); + break; + case IVG_EVX: + /* RTX -- only valid in exception. */ + /* XXX: What does the hardware do ? */ + if (curr_ivg != IVG_EVX) + cec_exception (cpu, VEC_ILL_RES); + break; + default: + /* RTI -- not valid in emulation, nmi, exception, or user. */ + /* XXX: What does the hardware do ? */ + if (curr_ivg == IVG_EMU || curr_ivg == IVG_NMI + || curr_ivg == IVG_EVX || curr_ivg == IVG_USER) + cec_exception (cpu, VEC_ILL_RES); + break; + case IVG_IRPTEN: + /* XXX: Is this even possible ? */ + excp_to_sim_halt (sim_stopped, SIM_SIGABRT); + break; + } + newpc = cec_read_ret_reg (cpu, ivg); + + /* XXX: Does this nested trick work on EMU/NMI/EVX ? */ + snen = (newpc & 1); + /* XXX: Delayed clear shows bad PCREG register trace above ? */ + SET_PCREG (newpc & ~1); + + TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (from EVT%i)", ivg); + + /* Update ipend after the TRACE_BRANCH so dv-bfin_trace + knows current CEC state wrt overflow. */ + if (!snen) + cec->ipend &= ~(1 << ivg); + + /* Disable global interrupt mask to let any interrupt take over, but + only when we were already in a RTI level. Only way we could have + raised at that point is if it was cleared in the first place. */ + if (ivg >= IVG_IVHW || ivg == IVG_RST) + cec_irpten_disable (cpu, cec); + + /* When going from super to user, we clear LSB in LB regs in case + it was set on the transition up. + Also need to load SP alias with USP. */ + if (_cec_get_ivg (cec) == -1) + { + int i; + for (i = 0; i < 2; ++i) + if (LBREG (i) & 1) + SET_LBREG (i, LBREG (i) & ~1); + SET_KSPREG (SPREG); + SET_SPREG (USPREG); + } + + /* Check for pending interrupts before we return to usermode. */ + _cec_check_pending (cpu, cec); +} + +void +cec_push_reti (SIM_CPU *cpu) +{ + /* XXX: Need to check hardware with popped RETI value + and bit 1 is set (when handling nested interrupts). + Also need to check behavior wrt SNEN in SYSCFG. */ + struct bfin_cec *cec; + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + return; + + TRACE_EVENTS (cpu, "pushing RETI"); + + cec = CEC_STATE (cpu); + cec_irpten_disable (cpu, cec); + /* Check for pending interrupts. */ + _cec_check_pending (cpu, cec); +} + +void +cec_pop_reti (SIM_CPU *cpu) +{ + /* XXX: Need to check hardware with popped RETI value + and bit 1 is set (when handling nested interrupts). + Also need to check behavior wrt SNEN in SYSCFG. */ + struct bfin_cec *cec; + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + return; + + TRACE_EVENTS (cpu, "popping RETI"); + + cec = CEC_STATE (cpu); + cec_irpten_enable (cpu, cec); +} diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.h new file mode 100644 index 000000000000..027c89389bc2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_cec.h @@ -0,0 +1,139 @@ +/* Blackfin Core Event Controller (CEC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_CEC_H +#define DV_BFIN_CEC_H + +#include "sim-main.h" + +#define BFIN_COREMMR_CEC_BASE 0xFFE02100 +#define BFIN_COREMMR_CEC_SIZE (4 * 5) + +/* 0xFFE02100 ... 0xFFE02110 */ +#define BFIN_COREMMR_EVT_OVERRIDE (BFIN_COREMMR_CEC_BASE + (4 * 0)) +#define BFIN_COREMMR_IMASK (BFIN_COREMMR_CEC_BASE + (4 * 1)) +#define BFIN_COREMMR_IPEND (BFIN_COREMMR_CEC_BASE + (4 * 2)) +#define BFIN_COREMMR_ILAT (BFIN_COREMMR_CEC_BASE + (4 * 3)) +#define BFIN_COREMMR_IPRIO (BFIN_COREMMR_CEC_BASE + (4 * 4)) + +#define IVG_EMU 0 +#define IVG_RST 1 +#define IVG_NMI 2 +#define IVG_EVX 3 +#define IVG_IRPTEN 4 /* Global is Reserved */ +#define IVG_IVHW 5 +#define IVG_IVTMR 6 +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 +#define IVG_USER 16 /* Not real; for internal use */ + +#define IVG_EMU_B (1 << IVG_EMU) +#define IVG_RST_B (1 << IVG_RST) +#define IVG_NMI_B (1 << IVG_NMI) +#define IVG_EVX_B (1 << IVG_EVX) +#define IVG_IRPTEN_B (1 << IVG_IRPTEN) +#define IVG_IVHW_B (1 << IVG_IVHW) +#define IVG_IVTMR_B (1 << IVG_IVTMR) +#define IVG7_B (1 << IVG7) +#define IVG8_B (1 << IVG8) +#define IVG9_B (1 << IVG9) +#define IVG10_B (1 << IVG10) +#define IVG11_B (1 << IVG11) +#define IVG12_B (1 << IVG12) +#define IVG13_B (1 << IVG13) +#define IVG14_B (1 << IVG14) +#define IVG15_B (1 << IVG15) +#define IVG_UNMASKABLE_B \ + (IVG_EMU_B | IVG_RST_B | IVG_NMI_B | IVG_EVX_B | IVG_IRPTEN_B) +#define IVG_MASKABLE_B \ + (IVG_IVHW_B | IVG_IVTMR_B | IVG7_B | IVG8_B | IVG9_B | \ + IVG10_B | IVG11_B | IVG12_B | IVG13_B | IVG14_B | IVG15_B) + +#define VEC_SYS 0x0 +#define VEC_EXCPT01 0x1 +#define VEC_EXCPT02 0x2 +#define VEC_EXCPT03 0x3 +#define VEC_EXCPT04 0x4 +#define VEC_EXCPT05 0x5 +#define VEC_EXCPT06 0x6 +#define VEC_EXCPT07 0x7 +#define VEC_EXCPT08 0x8 +#define VEC_EXCPT09 0x9 +#define VEC_EXCPT10 0xa +#define VEC_EXCPT11 0xb +#define VEC_EXCPT12 0xc +#define VEC_EXCPT13 0xd +#define VEC_EXCPT14 0xe +#define VEC_EXCPT15 0xf +#define VEC_STEP 0x10 /* single step */ +#define VEC_OVFLOW 0x11 /* trace buffer overflow */ +#define VEC_UNDEF_I 0x21 /* undefined instruction */ +#define VEC_ILGAL_I 0x22 /* illegal instruction combo (multi-issue) */ +#define VEC_CPLB_VL 0x23 /* DCPLB protection violation */ +#define VEC_MISALI_D 0x24 /* unaligned data access */ +#define VEC_UNCOV 0x25 /* unrecoverable event (double fault) */ +#define VEC_CPLB_M 0x26 /* DCPLB miss */ +#define VEC_CPLB_MHIT 0x27 /* multiple DCPLB hit */ +#define VEC_WATCH 0x28 /* watchpoint match */ +#define VEC_ISTRU_VL 0x29 /* ADSP-BF535 only */ +#define VEC_MISALI_I 0x2a /* unaligned instruction access */ +#define VEC_CPLB_I_VL 0x2b /* ICPLB protection violation */ +#define VEC_CPLB_I_M 0x2c /* ICPLB miss */ +#define VEC_CPLB_I_MHIT 0x2d /* multiple ICPLB hit */ +#define VEC_ILL_RES 0x2e /* illegal supervisor resource */ +/* + * The hardware reserves 63+ for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR 63 +#define VEC_SIM_BASE 64 +#define VEC_SIM_HLT (VEC_SIM_BASE + 1) +#define VEC_SIM_ABORT (VEC_SIM_BASE + 2) +#define VEC_SIM_TRAP (VEC_SIM_BASE + 3) +#define VEC_SIM_DBGA (VEC_SIM_BASE + 4) +extern void cec_exception (SIM_CPU *, int vec_excp); + +#define HWERR_SYSTEM_MMR 0x02 +#define HWERR_EXTERN_ADDR 0x03 +#define HWERR_PERF_FLOW 0x12 +#define HWERR_RAISE_5 0x18 +extern void cec_hwerr (SIM_CPU *, int hwerr); +extern void cec_latch (SIM_CPU *, int ivg); +extern void cec_return (SIM_CPU *, int ivg); + +extern int cec_get_ivg (SIM_CPU *); +extern bool cec_is_supervisor_mode (SIM_CPU *); +extern bool cec_is_user_mode (SIM_CPU *); +extern void cec_require_supervisor (SIM_CPU *); + +extern bu32 cec_cli (SIM_CPU *); +extern void cec_sti (SIM_CPU *, bu32 ints); + +extern void cec_push_reti (SIM_CPU *); +extern void cec_pop_reti (SIM_CPU *); + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.c new file mode 100644 index 000000000000..13f12d451bf9 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.c @@ -0,0 +1,270 @@ +/* Blackfin Core Timer model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_ctimer.h" + +struct bfin_ctimer +{ + bu32 base; + struct hw_event *handler; + signed64 timeout; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 tcntl, tperiod, tscale, tcount; +}; +#define mmr_base() offsetof(struct bfin_ctimer, tcntl) +#define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "TCNTL", "TPERIOD", "TSCALE", "TCOUNT", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static bool +bfin_ctimer_enabled (struct bfin_ctimer *ctimer) +{ + return (ctimer->tcntl & TMPWR) && (ctimer->tcntl & TMREN); +} + +static bu32 +bfin_ctimer_scale (struct bfin_ctimer *ctimer) +{ + /* Only low 8 bits are actually checked. */ + return (ctimer->tscale & 0xff) + 1; +} + +static void +bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer); + +static void +bfin_ctimer_expire (struct hw *me, void *data) +{ + struct bfin_ctimer *ctimer = data; + + ctimer->tcntl |= TINT; + if (ctimer->tcntl & TAUTORLD) + { + ctimer->tcount = ctimer->tperiod; + bfin_ctimer_schedule (me, ctimer); + } + else + { + ctimer->tcount = 0; + ctimer->handler = NULL; + } + + hw_port_event (me, IVG_IVTMR, 1); +} + +static void +bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer) +{ + bu32 scale, ticks; + signed64 timeout; + + /* If the timer was enabled w/out autoreload and has expired, then + there's nothing to calculate here. */ + if (ctimer->handler == NULL) + return; + + scale = bfin_ctimer_scale (ctimer); + timeout = hw_event_remain_time (me, ctimer->handler); + ticks = ctimer->timeout - timeout; + ctimer->tcount -= (scale * ticks); + ctimer->timeout = timeout; +} + +static void +bfin_ctimer_deschedule (struct hw *me, struct bfin_ctimer *ctimer) +{ + if (ctimer->handler) + { + hw_event_queue_deschedule (me, ctimer->handler); + ctimer->handler = NULL; + } +} + +static void +bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer) +{ + bu32 scale = bfin_ctimer_scale (ctimer); + ctimer->timeout = (ctimer->tcount / scale) + !!(ctimer->tcount % scale); + ctimer->handler = hw_event_queue_schedule (me, ctimer->timeout, + bfin_ctimer_expire, + ctimer); +} + +static unsigned +bfin_ctimer_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ctimer *ctimer = hw_data (me); + bool curr_enabled; + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + value = dv_load_4 (source); + mmr_off = addr - ctimer->base; + valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + curr_enabled = bfin_ctimer_enabled (ctimer); + switch (mmr_off) + { + case mmr_offset(tcntl): + /* HRM describes TINT as sticky, but it isn't W1C. */ + *valuep = value; + + if (bfin_ctimer_enabled (ctimer) == curr_enabled) + { + /* Do nothing. */ + } + else if (curr_enabled) + { + bfin_ctimer_update_count (me, ctimer); + bfin_ctimer_deschedule (me, ctimer); + } + else + bfin_ctimer_schedule (me, ctimer); + + break; + case mmr_offset(tcount): + /* HRM says writes are discarded when enabled. */ + /* XXX: But hardware seems to be writeable all the time ? */ + /* if (!curr_enabled) */ + *valuep = value; + break; + case mmr_offset(tperiod): + /* HRM says writes are discarded when enabled. */ + /* XXX: But hardware seems to be writeable all the time ? */ + /* if (!curr_enabled) */ + { + /* Writes are mirrored into TCOUNT. */ + ctimer->tcount = value; + *valuep = value; + } + break; + case mmr_offset(tscale): + if (curr_enabled) + { + bfin_ctimer_update_count (me, ctimer); + bfin_ctimer_deschedule (me, ctimer); + } + *valuep = value; + if (curr_enabled) + bfin_ctimer_schedule (me, ctimer); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ctimer_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ctimer *ctimer = hw_data (me); + bu32 mmr_off; + bu32 *valuep; + + mmr_off = addr - ctimer->base; + valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(tcount): + /* Since we're optimizing events here, we need to calculate + the new tcount value. */ + if (bfin_ctimer_enabled (ctimer)) + bfin_ctimer_update_count (me, ctimer); + break; + } + + dv_store_4 (dest, *valuep); + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_ctimer_ports[] = +{ + { "ivtmr", IVG_IVTMR, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_ctimer_regs (struct hw *me, struct bfin_ctimer *ctimer) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_CTIMER_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + ctimer->base = attach_address; +} + +static void +bfin_ctimer_finish (struct hw *me) +{ + struct bfin_ctimer *ctimer; + + ctimer = HW_ZALLOC (me, struct bfin_ctimer); + + set_hw_data (me, ctimer); + set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer); + set_hw_ports (me, bfin_ctimer_ports); + + attach_bfin_ctimer_regs (me, ctimer); + + /* Initialize the Core Timer. */ +} + +const struct hw_descriptor dv_bfin_ctimer_descriptor[] = +{ + {"bfin_ctimer", bfin_ctimer_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.h new file mode 100644 index 000000000000..c097588fec6a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ctimer.h @@ -0,0 +1,33 @@ +/* Blackfin Core Timer model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_CTIMER_H +#define DV_BFIN_CTIMER_H + +#define BFIN_COREMMR_CTIMER_BASE 0xFFE03000 +#define BFIN_COREMMR_CTIMER_SIZE (4 * 4) + +/* TCNTL Masks */ +#define TMPWR (1 << 0) +#define TMREN (1 << 1) +#define TAUTORLD (1 << 2) +#define TINT (1 << 3) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.c new file mode 100644 index 000000000000..1af528b53edd --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.c @@ -0,0 +1,556 @@ +/* Blackfin Direct Memory Access (DMA) Channel model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "hw-device.h" +#include "dv-bfin_dma.h" +#include "dv-bfin_dmac.h" + +/* Note: This DMA implementation requires the producer to be the master when + the peer is MDMA. The source is always a slave. This way we don't + have the two DMA devices thrashing each other with one trying to + write and the other trying to read. */ + +struct bfin_dma +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + unsigned ele_size; + struct hw *hw_peer; + + /* Order after here is important -- matches hardware MMR layout. */ + union { + struct { bu16 ndpl, ndph; }; + bu32 next_desc_ptr; + }; + union { + struct { bu16 sal, sah; }; + bu32 start_addr; + }; + bu16 BFIN_MMR_16 (config); + bu32 _pad0; + bu16 BFIN_MMR_16 (x_count); + bs16 BFIN_MMR_16 (x_modify); + bu16 BFIN_MMR_16 (y_count); + bs16 BFIN_MMR_16 (y_modify); + bu32 curr_desc_ptr, curr_addr; + bu16 BFIN_MMR_16 (irq_status); + bu16 BFIN_MMR_16 (peripheral_map); + bu16 BFIN_MMR_16 (curr_x_count); + bu32 _pad1; + bu16 BFIN_MMR_16 (curr_y_count); + bu32 _pad2; +}; +#define mmr_base() offsetof(struct bfin_dma, next_desc_ptr) +#define mmr_offset(mmr) (offsetof(struct bfin_dma, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "NEXT_DESC_PTR", "START_ADDR", "CONFIG", "", "X_COUNT", "X_MODIFY", + "Y_COUNT", "Y_MODIFY", "CURR_DESC_PTR", "CURR_ADDR", "IRQ_STATUS", + "PERIPHERAL_MAP", "CURR_X_COUNT", "", "CURR_Y_COUNT", "", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static bool +bfin_dma_enabled (struct bfin_dma *dma) +{ + return (dma->config & DMAEN); +} + +static bool +bfin_dma_running (struct bfin_dma *dma) +{ + return (dma->irq_status & DMA_RUN); +} + +static struct hw * +bfin_dma_get_peer (struct hw *me, struct bfin_dma *dma) +{ + if (dma->hw_peer) + return dma->hw_peer; + return dma->hw_peer = bfin_dmac_get_peer (me, dma->peripheral_map); +} + +static void +bfin_dma_process_desc (struct hw *me, struct bfin_dma *dma) +{ + bu8 ndsize = (dma->config & NDSIZE) >> NDSIZE_SHIFT; + bu16 _flows[9], *flows = _flows; + + HW_TRACE ((me, "dma starting up %#x", dma->config)); + + switch (dma->config & WDSIZE) + { + case WDSIZE_32: + dma->ele_size = 4; + break; + case WDSIZE_16: + dma->ele_size = 2; + break; + default: + dma->ele_size = 1; + break; + } + + /* Address has to be mutiple of transfer size. */ + if (dma->start_addr & (dma->ele_size - 1)) + dma->irq_status |= DMA_ERR; + + if (dma->ele_size != (unsigned) abs (dma->x_modify)) + hw_abort (me, "DMA config (striding) %#x not supported (x_modify: %d)", + dma->config, dma->x_modify); + + switch (dma->config & DMAFLOW) + { + case DMAFLOW_AUTO: + case DMAFLOW_STOP: + if (ndsize) + hw_abort (me, "DMA config error: DMAFLOW_{AUTO,STOP} requires NDSIZE_0"); + break; + case DMAFLOW_ARRAY: + if (ndsize == 0 || ndsize > 7) + hw_abort (me, "DMA config error: DMAFLOW_ARRAY requires NDSIZE 1...7"); + sim_read (hw_system (me), dma->curr_desc_ptr, (void *)flows, ndsize * 2); + break; + case DMAFLOW_SMALL: + if (ndsize == 0 || ndsize > 8) + hw_abort (me, "DMA config error: DMAFLOW_SMALL requires NDSIZE 1...8"); + sim_read (hw_system (me), dma->next_desc_ptr, (void *)flows, ndsize * 2); + break; + case DMAFLOW_LARGE: + if (ndsize == 0 || ndsize > 9) + hw_abort (me, "DMA config error: DMAFLOW_LARGE requires NDSIZE 1...9"); + sim_read (hw_system (me), dma->next_desc_ptr, (void *)flows, ndsize * 2); + break; + default: + hw_abort (me, "DMA config error: invalid DMAFLOW %#x", dma->config); + } + + if (ndsize) + { + bu8 idx; + bu16 *stores[] = { + &dma->sal, + &dma->sah, + &dma->config, + &dma->x_count, + (void *) &dma->x_modify, + &dma->y_count, + (void *) &dma->y_modify, + }; + + switch (dma->config & DMAFLOW) + { + case DMAFLOW_LARGE: + dma->ndph = _flows[1]; + --ndsize; + ++flows; + case DMAFLOW_SMALL: + dma->ndpl = _flows[0]; + --ndsize; + ++flows; + break; + } + + for (idx = 0; idx < ndsize; ++idx) + *stores[idx] = flows[idx]; + } + + dma->curr_desc_ptr = dma->next_desc_ptr; + dma->curr_addr = dma->start_addr; + dma->curr_x_count = dma->x_count ? : 0xffff; + dma->curr_y_count = dma->y_count ? : 0xffff; +} + +static int +bfin_dma_finish_x (struct hw *me, struct bfin_dma *dma) +{ + /* XXX: This would be the time to process the next descriptor. */ + /* XXX: Should this toggle Enable in dma->config ? */ + + if (dma->config & DI_EN) + hw_port_event (me, 0, 1); + + if ((dma->config & DMA2D) && dma->curr_y_count > 1) + { + dma->curr_y_count -= 1; + dma->curr_x_count = dma->x_count; + + /* With 2D, last X transfer does not modify curr_addr. */ + dma->curr_addr = dma->curr_addr - dma->x_modify + dma->y_modify; + + return 1; + } + + switch (dma->config & DMAFLOW) + { + case DMAFLOW_STOP: + HW_TRACE ((me, "dma is complete")); + dma->irq_status = (dma->irq_status & ~DMA_RUN) | DMA_DONE; + return 0; + default: + bfin_dma_process_desc (me, dma); + return 1; + } +} + +static void bfin_dma_hw_event_callback (struct hw *, void *); + +static void +bfin_dma_reschedule (struct hw *me, unsigned delay) +{ + struct bfin_dma *dma = hw_data (me); + if (dma->handler) + { + hw_event_queue_deschedule (me, dma->handler); + dma->handler = NULL; + } + if (!delay) + return; + HW_TRACE ((me, "scheduling next process in %u", delay)); + dma->handler = hw_event_queue_schedule (me, delay, + bfin_dma_hw_event_callback, dma); +} + +/* Chew through the DMA over and over. */ +static void +bfin_dma_hw_event_callback (struct hw *me, void *data) +{ + struct bfin_dma *dma = data; + struct hw *peer; + struct dv_bfin *bfin_peer; + bu8 buf[4096]; + unsigned ret, nr_bytes, ele_count; + + dma->handler = NULL; + peer = bfin_dma_get_peer (me, dma); + bfin_peer = hw_data (peer); + ret = 0; + if (dma->x_modify < 0) + /* XXX: This sucks performance wise. */ + nr_bytes = dma->ele_size; + else + nr_bytes = MIN (sizeof (buf), dma->curr_x_count * dma->ele_size); + + /* Pumping a chunk! */ + bfin_peer->dma_master = me; + bfin_peer->acked = false; + if (dma->config & WNR) + { + HW_TRACE ((me, "dma transfer to 0x%08lx length %u", + (unsigned long) dma->curr_addr, nr_bytes)); + + ret = hw_dma_read_buffer (peer, buf, 0, dma->curr_addr, nr_bytes); + /* Has the DMA stalled ? abort for now. */ + if (ret == 0) + goto reschedule; + /* XXX: How to handle partial DMA transfers ? */ + if (ret % dma->ele_size) + goto error; + ret = sim_write (hw_system (me), dma->curr_addr, buf, ret); + } + else + { + HW_TRACE ((me, "dma transfer from 0x%08lx length %u", + (unsigned long) dma->curr_addr, nr_bytes)); + + ret = sim_read (hw_system (me), dma->curr_addr, buf, nr_bytes); + if (ret == 0) + goto reschedule; + /* XXX: How to handle partial DMA transfers ? */ + if (ret % dma->ele_size) + goto error; + ret = hw_dma_write_buffer (peer, buf, 0, dma->curr_addr, ret, 0); + if (ret == 0) + goto reschedule; + } + + /* Ignore partial writes. */ + ele_count = ret / dma->ele_size; + dma->curr_addr += ele_count * dma->x_modify; + dma->curr_x_count -= ele_count; + + if ((!dma->acked && dma->curr_x_count) || bfin_dma_finish_x (me, dma)) + /* Still got work to do, so schedule again. */ + reschedule: + bfin_dma_reschedule (me, ret ? 1 : 5000); + + return; + + error: + /* Don't reschedule on errors ... */ + dma->irq_status |= DMA_ERR; +} + +static unsigned +bfin_dma_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_dma *dma = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr % dma->base; + valuep = (void *)((unsigned long)dma + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: All registers are RO when DMA is enabled (except IRQ_STATUS). + But does the HW discard writes or send up IVGHW ? The sim + simply discards atm ... */ + switch (mmr_off) + { + case mmr_offset(next_desc_ptr): + case mmr_offset(start_addr): + case mmr_offset(curr_desc_ptr): + case mmr_offset(curr_addr): + /* Don't require 32bit access as all DMA MMRs can be used as 16bit. */ + if (!bfin_dma_running (dma)) + { + if (nr_bytes == 4) + *value32p = value; + else + *value16p = value; + } + else + HW_TRACE ((me, "discarding write while dma running")); + break; + case mmr_offset(x_count): + case mmr_offset(x_modify): + case mmr_offset(y_count): + case mmr_offset(y_modify): + if (!bfin_dma_running (dma)) + *value16p = value; + break; + case mmr_offset(peripheral_map): + if (!bfin_dma_running (dma)) + { + *value16p = (*value16p & CTYPE) | (value & ~CTYPE); + /* Clear peripheral peer so it gets looked up again. */ + dma->hw_peer = NULL; + } + else + HW_TRACE ((me, "discarding write while dma running")); + break; + case mmr_offset(config): + /* XXX: How to handle updating CONFIG of a running channel ? */ + if (nr_bytes == 4) + *value32p = value; + else + *value16p = value; + + if (bfin_dma_enabled (dma)) + { + dma->irq_status |= DMA_RUN; + bfin_dma_process_desc (me, dma); + /* The writer is the master. */ + if (!(dma->peripheral_map & CTYPE) || (dma->config & WNR)) + bfin_dma_reschedule (me, 1); + } + else + { + dma->irq_status &= ~DMA_RUN; + bfin_dma_reschedule (me, 0); + } + break; + case mmr_offset(irq_status): + dv_w1c_2 (value16p, value, DMA_DONE | DMA_ERR); + break; + case mmr_offset(curr_x_count): + case mmr_offset(curr_y_count): + if (!bfin_dma_running (dma)) + *value16p = value; + else + HW_TRACE ((me, "discarding write while dma running")); + break; + default: + /* XXX: The HW lets the pad regions be read/written ... */ + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_dma_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_dma *dma = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr % dma->base; + valuep = (void *)((unsigned long)dma + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + /* Hardware lets you read all MMRs as 16 or 32 bits, even reserved. */ + if (nr_bytes == 4) + dv_store_4 (dest, *value32p); + else + dv_store_2 (dest, *value16p); + + return nr_bytes; +} + +static unsigned +bfin_dma_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + struct bfin_dma *dma = hw_data (me); + unsigned ret, ele_count; + + HW_TRACE_DMA_READ (); + + /* If someone is trying to read from me, I have to be enabled. */ + if (!bfin_dma_enabled (dma) && !bfin_dma_running (dma)) + return 0; + + /* XXX: handle x_modify ... */ + ret = sim_read (hw_system (me), dma->curr_addr, dest, nr_bytes); + /* Ignore partial writes. */ + ele_count = ret / dma->ele_size; + /* Has the DMA stalled ? abort for now. */ + if (!ele_count) + return 0; + + dma->curr_addr += ele_count * dma->x_modify; + dma->curr_x_count -= ele_count; + + if (dma->curr_x_count == 0) + bfin_dma_finish_x (me, dma); + + return ret; +} + +static unsigned +bfin_dma_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_dma *dma = hw_data (me); + unsigned ret, ele_count; + + HW_TRACE_DMA_WRITE (); + + /* If someone is trying to write to me, I have to be enabled. */ + if (!bfin_dma_enabled (dma) && !bfin_dma_running (dma)) + return 0; + + /* XXX: handle x_modify ... */ + ret = sim_write (hw_system (me), dma->curr_addr, source, nr_bytes); + /* Ignore partial writes. */ + ele_count = ret / dma->ele_size; + /* Has the DMA stalled ? abort for now. */ + if (!ele_count) + return 0; + + dma->curr_addr += ele_count * dma->x_modify; + dma->curr_x_count -= ele_count; + + if (dma->curr_x_count == 0) + bfin_dma_finish_x (me, dma); + + return ret; +} + +static const struct hw_port_descriptor bfin_dma_ports[] = +{ + { "di", 0, 0, output_port, }, /* DMA Interrupt */ + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_dma_regs (struct hw *me, struct bfin_dma *dma) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_DMA_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_DMA_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + dma->base = attach_address; +} + +static void +bfin_dma_finish (struct hw *me) +{ + struct bfin_dma *dma; + + dma = HW_ZALLOC (me, struct bfin_dma); + + set_hw_data (me, dma); + set_hw_io_read_buffer (me, bfin_dma_io_read_buffer); + set_hw_io_write_buffer (me, bfin_dma_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_dma_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_dma_dma_write_buffer); + set_hw_ports (me, bfin_dma_ports); + + attach_bfin_dma_regs (me, dma); + + /* Initialize the DMA Channel. */ + dma->peripheral_map = bfin_dmac_default_pmap (me); +} + +const struct hw_descriptor dv_bfin_dma_descriptor[] = +{ + {"bfin_dma", bfin_dma_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.h new file mode 100644 index 000000000000..03d412b7e9db --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dma.h @@ -0,0 +1,65 @@ +/* Blackfin Direct Memory Access (DMA) Channel model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_DMA_H +#define DV_BFIN_DMA_H + +#define BFIN_MMR_DMA_SIZE (4 * 16) + +/* DMA_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define WDSIZE 0x000c /* Transfer Word Size */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0f00 /* Next Descriptor Size */ +#define NDSIZE_SHIFT 8 +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* DMA_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +/* DMA_PERIPHERAL_MAP Masks */ +#define CTYPE (1 << 6) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.c new file mode 100644 index 000000000000..5cc05b10c103 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.c @@ -0,0 +1,494 @@ +/* Blackfin Direct Memory Access (DMA) Controller model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "sim-hw.h" +#include "devices.h" +#include "hw-device.h" +#include "dv-bfin_dma.h" +#include "dv-bfin_dmac.h" + +struct bfin_dmac +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + const char **pmap; + unsigned int pmap_count; +}; + +struct hw * +bfin_dmac_get_peer (struct hw *dma, bu16 pmap) +{ + struct hw *ret, *me; + struct bfin_dmac *dmac; + char peer[100]; + + me = hw_parent (dma); + dmac = hw_data (me); + if (pmap & CTYPE) + { + /* MDMA channel. */ + unsigned int chan_num = dv_get_bus_num (dma); + if (chan_num & 1) + chan_num &= ~1; + else + chan_num |= 1; + sprintf (peer, "%s/bfin_dma@%u", hw_path (me), chan_num); + } + else + { + unsigned int idx = pmap >> 12; + if (idx >= dmac->pmap_count) + hw_abort (me, "Invalid DMA peripheral_map %#x", pmap); + else + sprintf (peer, "/core/bfin_%s", dmac->pmap[idx]); + } + + ret = hw_tree_find_device (me, peer); + if (!ret) + hw_abort (me, "Unable to locate peer for %s (pmap:%#x %s)", + hw_name (dma), pmap, peer); + return ret; +} + +bu16 +bfin_dmac_default_pmap (struct hw *dma) +{ + unsigned int chan_num = dv_get_bus_num (dma); + + if (chan_num < BFIN_DMAC_MDMA_BASE) + return (chan_num % 12) << 12; + else + return CTYPE; /* MDMA */ +} + +static const char *bfin_dmac_50x_pmap[] = +{ + "ppi@0", "rsi", "sport@0", "sport@0", "sport@1", "sport@1", + "spi@0", "spi@1", "uart2@0", "uart2@0", "uart2@1", "uart2@1", +}; + +/* XXX: Need to figure out how to handle portmuxed DMA channels. */ +static const struct hw_port_descriptor bfin_dmac_50x_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "rsi", 1, 0, input_port, }, + { "sport@0_rx", 2, 0, input_port, }, + { "sport@0_tx", 3, 0, input_port, }, + { "sport@1_tx", 4, 0, input_port, }, + { "sport@1_rx", 5, 0, input_port, }, + { "spi@0", 6, 0, input_port, }, + { "spi@1", 7, 0, input_port, }, + { "uart2@0_rx", 8, 0, input_port, }, + { "uart2@0_tx", 9, 0, input_port, }, + { "uart2@1_rx", 10, 0, input_port, }, + { "uart2@1_tx", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac_51x_pmap[] = +{ + "ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1", + "sport@1", "spi@0", "uart@0", "uart@0", "uart@1", "uart@1", +}; + +/* XXX: Need to figure out how to handle portmuxed DMA channels. */ +static const struct hw_port_descriptor bfin_dmac_51x_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "emac_rx", 1, 0, input_port, }, + { "emac_tx", 2, 0, input_port, }, + { "sport@0_rx", 3, 0, input_port, }, + { "sport@0_tx", 4, 0, input_port, }, +/*{ "rsi", 4, 0, input_port, },*/ + { "sport@1_tx", 5, 0, input_port, }, +/*{ "spi@1", 5, 0, input_port, },*/ + { "sport@1_rx", 6, 0, input_port, }, + { "spi@0", 7, 0, input_port, }, + { "uart@0_rx", 8, 0, input_port, }, + { "uart@0_tx", 9, 0, input_port, }, + { "uart@1_rx", 10, 0, input_port, }, + { "uart@1_tx", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac_52x_pmap[] = +{ + "ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1", + "sport@1", "spi", "uart@0", "uart@0", "uart@1", "uart@1", +}; + +/* XXX: Need to figure out how to handle portmuxed DMA channels + like PPI/NFC here which share DMA0. */ +static const struct hw_port_descriptor bfin_dmac_52x_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, +/*{ "nfc", 0, 0, input_port, },*/ + { "emac_rx", 1, 0, input_port, }, +/*{ "hostdp", 1, 0, input_port, },*/ + { "emac_tx", 2, 0, input_port, }, +/*{ "nfc", 2, 0, input_port, },*/ + { "sport@0_tx", 3, 0, input_port, }, + { "sport@0_rx", 4, 0, input_port, }, + { "sport@1_tx", 5, 0, input_port, }, + { "sport@1_rx", 6, 0, input_port, }, + { "spi", 7, 0, input_port, }, + { "uart@0_tx", 8, 0, input_port, }, + { "uart@0_rx", 9, 0, input_port, }, + { "uart@1_tx", 10, 0, input_port, }, + { "uart@1_rx", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac_533_pmap[] = +{ + "ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi", + "uart@0", "uart@0", +}; + +static const struct hw_port_descriptor bfin_dmac_533_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "sport@0_tx", 1, 0, input_port, }, + { "sport@0_rx", 2, 0, input_port, }, + { "sport@1_tx", 3, 0, input_port, }, + { "sport@1_rx", 4, 0, input_port, }, + { "spi", 5, 0, input_port, }, + { "uart@0_tx", 6, 0, input_port, }, + { "uart@0_rx", 7, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac_537_pmap[] = +{ + "ppi@0", "emac", "emac", "sport@0", "sport@0", "sport@1", + "sport@1", "spi", "uart@0", "uart@0", "uart@1", "uart@1", +}; + +static const struct hw_port_descriptor bfin_dmac_537_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "emac_rx", 1, 0, input_port, }, + { "emac_tx", 2, 0, input_port, }, + { "sport@0_tx", 3, 0, input_port, }, + { "sport@0_rx", 4, 0, input_port, }, + { "sport@1_tx", 5, 0, input_port, }, + { "sport@1_rx", 6, 0, input_port, }, + { "spi", 7, 0, input_port, }, + { "uart@0_tx", 8, 0, input_port, }, + { "uart@0_rx", 9, 0, input_port, }, + { "uart@1_tx", 10, 0, input_port, }, + { "uart@1_rx", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac0_538_pmap[] = +{ + "ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi@0", + "uart@0", "uart@0", +}; + +static const struct hw_port_descriptor bfin_dmac0_538_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "sport@0_rx", 1, 0, input_port, }, + { "sport@0_tx", 2, 0, input_port, }, + { "sport@1_rx", 3, 0, input_port, }, + { "sport@1_tx", 4, 0, input_port, }, + { "spi@0", 5, 0, input_port, }, + { "uart@0_rx", 6, 0, input_port, }, + { "uart@0_tx", 7, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac1_538_pmap[] = +{ + "sport@2", "sport@2", "sport@3", "sport@3", NULL, NULL, + "spi@1", "spi@2", "uart@1", "uart@1", "uart@2", "uart@2", +}; + +static const struct hw_port_descriptor bfin_dmac1_538_ports[] = +{ + { "sport@2_rx", 0, 0, input_port, }, + { "sport@2_tx", 1, 0, input_port, }, + { "sport@3_rx", 2, 0, input_port, }, + { "sport@3_tx", 3, 0, input_port, }, + { "spi@1", 6, 0, input_port, }, + { "spi@2", 7, 0, input_port, }, + { "uart@1_rx", 8, 0, input_port, }, + { "uart@1_tx", 9, 0, input_port, }, + { "uart@2_rx", 10, 0, input_port, }, + { "uart@2_tx", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac0_54x_pmap[] = +{ + "sport@0", "sport@0", "sport@1", "sport@1", "spi@0", "spi@1", + "uart2@0", "uart2@0", "uart2@1", "uart2@1", "atapi", "atapi", +}; + +static const struct hw_port_descriptor bfin_dmac0_54x_ports[] = +{ + { "sport@0_rx", 0, 0, input_port, }, + { "sport@0_tx", 1, 0, input_port, }, + { "sport@1_rx", 2, 0, input_port, }, + { "sport@1_tx", 3, 0, input_port, }, + { "spi@0", 4, 0, input_port, }, + { "spi@1", 5, 0, input_port, }, + { "uart2@0_rx", 6, 0, input_port, }, + { "uart2@0_tx", 7, 0, input_port, }, + { "uart2@1_rx", 8, 0, input_port, }, + { "uart2@1_tx", 9, 0, input_port, }, + { "atapi", 10, 0, input_port, }, + { "atapi", 11, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac1_54x_pmap[] = +{ + "eppi@0", "eppi@1", "eppi@2", "pixc", "pixc", "pixc", + "sport@2", "sport@2", "sport@3", "sport@3", "sdh", + "spi@2", "uart2@2", "uart2@2", "uart2@3", "uart2@3", +}; + +static const struct hw_port_descriptor bfin_dmac1_54x_ports[] = +{ + { "eppi@0", 0, 0, input_port, }, + { "eppi@1", 1, 0, input_port, }, + { "eppi@2", 2, 0, input_port, }, + { "pixc", 3, 0, input_port, }, + { "pixc", 4, 0, input_port, }, + { "pixc", 5, 0, input_port, }, + { "sport@2_rx", 6, 0, input_port, }, + { "sport@2_tx", 7, 0, input_port, }, + { "sport@3_rx", 8, 0, input_port, }, + { "sport@3_tx", 9, 0, input_port, }, + { "sdh", 10, 0, input_port, }, +/*{ "nfc", 10, 0, input_port, },*/ + { "spi@2", 11, 0, input_port, }, + { "uart2@2_rx", 12, 0, input_port, }, + { "uart2@2_tx", 13, 0, input_port, }, + { "uart2@3_rx", 14, 0, input_port, }, + { "uart2@3_tx", 15, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac0_561_pmap[] = +{ + "sport@0", "sport@0", "sport@1", "sport@1", "spi", "uart@0", "uart@0", +}; + +static const struct hw_port_descriptor bfin_dmac0_561_ports[] = +{ + { "sport@0_rx", 0, 0, input_port, }, + { "sport@0_tx", 1, 0, input_port, }, + { "sport@1_rx", 2, 0, input_port, }, + { "sport@1_tx", 3, 0, input_port, }, + { "spi@0", 4, 0, input_port, }, + { "uart@0_rx", 5, 0, input_port, }, + { "uart@0_tx", 6, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac1_561_pmap[] = +{ + "ppi@0", "ppi@1", +}; + +static const struct hw_port_descriptor bfin_dmac1_561_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "ppi@1", 1, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const char *bfin_dmac_59x_pmap[] = +{ + "ppi@0", "sport@0", "sport@0", "sport@1", "sport@1", "spi@0", + "spi@1", "uart@0", "uart@0", +}; + +static const struct hw_port_descriptor bfin_dmac_59x_ports[] = +{ + { "ppi@0", 0, 0, input_port, }, + { "sport@0_tx", 1, 0, input_port, }, + { "sport@0_rx", 2, 0, input_port, }, + { "sport@1_tx", 3, 0, input_port, }, + { "sport@1_rx", 4, 0, input_port, }, + { "spi@0", 5, 0, input_port, }, + { "spi@1", 6, 0, input_port, }, + { "uart@0_rx", 7, 0, input_port, }, + { "uart@0_tx", 8, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_dmac_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + SIM_DESC sd = hw_system (me); + struct bfin_dmac *dmac = hw_data (me); + struct hw *dma = hw_child (me); + + while (dma) + { + bu16 pmap; + sim_hw_io_read_buffer (sd, dma, &pmap, 0, 0x2c, sizeof (pmap)); + pmap >>= 12; + if (pmap == my_port) + break; + dma = hw_sibling (dma); + } + + if (!dma) + hw_abort (me, "no valid dma mapping found for %s", dmac->pmap[my_port]); + + /* Have the DMA channel raise its interrupt to the SIC. */ + hw_port_event (dma, 0, 1); +} + +static void +bfin_dmac_finish (struct hw *me) +{ + struct bfin_dmac *dmac; + unsigned int dmac_num = dv_get_bus_num (me); + + dmac = HW_ZALLOC (me, struct bfin_dmac); + + set_hw_data (me, dmac); + set_hw_port_event (me, bfin_dmac_port_event); + + /* Initialize the DMA Controller. */ + if (hw_find_property (me, "type") == NULL) + hw_abort (me, "Missing \"type\" property"); + + switch (hw_find_integer_property (me, "type")) + { + case 500 ... 509: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_50x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_50x_pmap); + set_hw_ports (me, bfin_dmac_50x_ports); + break; + case 510 ... 519: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_51x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_51x_pmap); + set_hw_ports (me, bfin_dmac_51x_ports); + break; + case 522 ... 527: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_52x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_52x_pmap); + set_hw_ports (me, bfin_dmac_52x_ports); + break; + case 531 ... 533: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_533_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_533_pmap); + set_hw_ports (me, bfin_dmac_533_ports); + break; + case 534: + case 536: + case 537: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_537_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_537_pmap); + set_hw_ports (me, bfin_dmac_537_ports); + break; + case 538 ... 539: + switch (dmac_num) + { + case 0: + dmac->pmap = bfin_dmac0_538_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_538_pmap); + set_hw_ports (me, bfin_dmac0_538_ports); + break; + case 1: + dmac->pmap = bfin_dmac1_538_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_538_pmap); + set_hw_ports (me, bfin_dmac1_538_ports); + break; + default: + hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1"); + } + break; + case 540 ... 549: + switch (dmac_num) + { + case 0: + dmac->pmap = bfin_dmac0_54x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_54x_pmap); + set_hw_ports (me, bfin_dmac0_54x_ports); + break; + case 1: + dmac->pmap = bfin_dmac1_54x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_54x_pmap); + set_hw_ports (me, bfin_dmac1_54x_ports); + break; + default: + hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1"); + } + break; + case 561: + switch (dmac_num) + { + case 0: + dmac->pmap = bfin_dmac0_561_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac0_561_pmap); + set_hw_ports (me, bfin_dmac0_561_ports); + break; + case 1: + dmac->pmap = bfin_dmac1_561_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac1_561_pmap); + set_hw_ports (me, bfin_dmac1_561_ports); + break; + default: + hw_abort (me, "this Blackfin only has a DMAC0 & DMAC1"); + } + break; + case 590 ... 599: + if (dmac_num != 0) + hw_abort (me, "this Blackfin only has a DMAC0"); + dmac->pmap = bfin_dmac_59x_pmap; + dmac->pmap_count = ARRAY_SIZE (bfin_dmac_59x_pmap); + set_hw_ports (me, bfin_dmac_59x_ports); + break; + default: + hw_abort (me, "no support for DMAC on this Blackfin model yet"); + } +} + +const struct hw_descriptor dv_bfin_dmac_descriptor[] = +{ + {"bfin_dmac", bfin_dmac_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.h new file mode 100644 index 000000000000..dfe953575e64 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_dmac.h @@ -0,0 +1,32 @@ +/* Blackfin Direct Memory Access (DMA) Controller model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_DMAC_H +#define DV_BFIN_DMAC_H + +#define BFIN_MMR_DMAC0_BASE 0xFFC00C00 +#define BFIN_MMR_DMAC1_BASE 0xFFC01C00 + +#define BFIN_DMAC_MDMA_BASE 0x100 + +struct hw *bfin_dmac_get_peer (struct hw *dma, bu16 pmap); +bu16 bfin_dmac_default_pmap (struct hw *dma); + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.c new file mode 100644 index 000000000000..4e056caaad38 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.c @@ -0,0 +1,460 @@ +/* Blackfin External Bus Interface Unit (EBIU) Asynchronous Memory Controller + (AMC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ebiu_amc.h" + +struct bfin_ebiu_amc +{ + bu32 base; + int type; + bu32 bank_size; + unsigned (*io_write) (struct hw *, const void *, int, address_word, + unsigned, struct bfin_ebiu_amc *, bu32, bu32); + unsigned (*io_read) (struct hw *, void *, int, address_word, unsigned, + struct bfin_ebiu_amc *, bu32, void *, bu16 *, bu32 *); + struct hw *slaves[4]; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(amgctl); + union { + struct { + bu32 ambctl0, ambctl1; + bu32 _pad0[5]; + bu16 BFIN_MMR_16(mode); + bu16 BFIN_MMR_16(fctl); + } bf50x; + struct { + bu32 ambctl0, ambctl1; + } bf53x; + struct { + bu32 ambctl0, ambctl1; + bu32 mbsctl, arbstat, mode, fctl; + } bf54x; + }; +}; +#define mmr_base() offsetof(struct bfin_ebiu_amc, amgctl) +#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_amc, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const bf50x_mmr_names[] = +{ + "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1", + [mmr_idx (bf50x.mode)] = "EBIU_MODE", "EBIU_FCTL", +}; +static const char * const bf53x_mmr_names[] = +{ + "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1", +}; +static const char * const bf54x_mmr_names[] = +{ + "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1", + "EBIU_MSBCTL", "EBIU_ARBSTAT", "EBIU_MODE", "EBIU_FCTL", +}; +static const char * const *mmr_names; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static void +bfin_ebiu_amc_write_amgctl (struct hw *me, struct bfin_ebiu_amc *amc, + bu16 amgctl) +{ + bu32 amben_old, amben, addr, i; + + amben_old = MIN ((amc->amgctl >> 1) & 0x7, 4); + amben = MIN ((amgctl >> 1) & 0x7, 4); + + HW_TRACE ((me, "reattaching banks: AMGCTL 0x%04x[%u] -> 0x%04x[%u]", + amc->amgctl, amben_old, amgctl, amben)); + + for (i = 0; i < 4; ++i) + { + addr = BFIN_EBIU_AMC_BASE + i * amc->bank_size; + + if (i < amben_old) + { + HW_TRACE ((me, "detaching bank %u (%#x base)", i, addr)); + sim_core_detach (hw_system (me), NULL, 0, 0, addr); + } + + if (i < amben) + { + struct hw *slave = amc->slaves[i]; + + HW_TRACE ((me, "attaching bank %u (%#x base) to %s", i, addr, + slave ? hw_path (slave) : "")); + + sim_core_attach (hw_system (me), NULL, 0, access_read_write_exec, + 0, addr, amc->bank_size, 0, slave, NULL); + } + } + + amc->amgctl = amgctl; +} + +static unsigned +bf50x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + bu32 value) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + bfin_ebiu_amc_write_amgctl (me, amc, value); + break; + case mmr_offset(bf50x.ambctl0): + amc->bf50x.ambctl0 = value; + break; + case mmr_offset(bf50x.ambctl1): + amc->bf50x.ambctl1 = value; + break; + case mmr_offset(bf50x.mode): + /* XXX: implement this. */ + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + break; + case mmr_offset(bf50x.fctl): + /* XXX: implement this. */ + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bf53x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + bu32 value) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + bfin_ebiu_amc_write_amgctl (me, amc, value); + break; + case mmr_offset(bf53x.ambctl0): + amc->bf53x.ambctl0 = value; + break; + case mmr_offset(bf53x.ambctl1): + amc->bf53x.ambctl1 = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bf54x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + bu32 value) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + bfin_ebiu_amc_write_amgctl (me, amc, value); + break; + case mmr_offset(bf54x.ambctl0): + amc->bf54x.ambctl0 = value; + break; + case mmr_offset(bf54x.ambctl1): + amc->bf54x.ambctl1 = value; + break; + case mmr_offset(bf54x.mbsctl): + /* XXX: implement this. */ + break; + case mmr_offset(bf54x.arbstat): + /* XXX: implement this. */ + break; + case mmr_offset(bf54x.mode): + /* XXX: implement this. */ + break; + case mmr_offset(bf54x.fctl): + /* XXX: implement this. */ + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_amc *amc = hw_data (me); + bu32 mmr_off; + bu32 value; + + value = dv_load_4 (source); + mmr_off = addr - amc->base; + + HW_TRACE_WRITE (); + + return amc->io_write (me, source, space, addr, nr_bytes, + amc, mmr_off, value); +} + +static unsigned +bf50x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + void *valuep, bu16 *value16, bu32 *value32) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + case mmr_offset(bf50x.fctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16); + break; + case mmr_offset(bf50x.ambctl0): + case mmr_offset(bf50x.ambctl1): + case mmr_offset(bf50x.mode): + dv_store_4 (dest, *value32); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bf53x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + void *valuep, bu16 *value16, bu32 *value32) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16); + break; + case mmr_offset(bf53x.ambctl0): + case mmr_offset(bf53x.ambctl1): + dv_store_4 (dest, *value32); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bf54x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes, + struct bfin_ebiu_amc *amc, bu32 mmr_off, + void *valuep, bu16 *value16, bu32 *value32) +{ + switch (mmr_off) + { + case mmr_offset(amgctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16); + break; + case mmr_offset(bf54x.ambctl0): + case mmr_offset(bf54x.ambctl1): + case mmr_offset(bf54x.mbsctl): + case mmr_offset(bf54x.arbstat): + case mmr_offset(bf54x.mode): + case mmr_offset(bf54x.fctl): + dv_store_4 (dest, *value32); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_amc *amc = hw_data (me); + bu32 mmr_off; + void *valuep; + + mmr_off = addr - amc->base; + valuep = (void *)((unsigned long)amc + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + return amc->io_read (me, dest, space, addr, nr_bytes, amc, + mmr_off, valuep, valuep, valuep); +} + +static void +bfin_ebiu_amc_attach_address_callback (struct hw *me, + int level, + int space, + address_word addr, + address_word nr_bytes, + struct hw *client) +{ + struct bfin_ebiu_amc *amc = hw_data (me); + + HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s", + level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client))); + + if (addr + nr_bytes > 4) + hw_abort (me, "ebiu amc attaches are done in terms of banks"); + + while (nr_bytes--) + amc->slaves[addr + nr_bytes] = client; + + bfin_ebiu_amc_write_amgctl (me, amc, amc->amgctl); +} + +static void +attach_bfin_ebiu_amc_regs (struct hw *me, struct bfin_ebiu_amc *amc, + unsigned reg_size) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + if (hw_find_property (me, "type") == NULL) + hw_abort (me, "Missing \"type\" property"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != reg_size) + hw_abort (me, "\"reg\" size must be %#x", reg_size); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + amc->base = attach_address; +} + +static void +bfin_ebiu_amc_finish (struct hw *me) +{ + struct bfin_ebiu_amc *amc; + bu32 amgctl; + unsigned reg_size; + + amc = HW_ZALLOC (me, struct bfin_ebiu_amc); + + set_hw_data (me, amc); + set_hw_io_read_buffer (me, bfin_ebiu_amc_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ebiu_amc_io_write_buffer); + set_hw_attach_address (me, bfin_ebiu_amc_attach_address_callback); + + amc->type = hw_find_integer_property (me, "type"); + + switch (amc->type) + { + case 500 ... 509: + amc->io_write = bf50x_ebiu_amc_io_write_buffer; + amc->io_read = bf50x_ebiu_amc_io_read_buffer; + mmr_names = bf50x_mmr_names; + reg_size = sizeof (amc->bf50x) + 4; + + /* Initialize the AMC. */ + amc->bank_size = 1 * 1024 * 1024; + amgctl = 0x00F3; + amc->bf50x.ambctl0 = 0x0000FFC2; + amc->bf50x.ambctl1 = 0x0000FFC2; + amc->bf50x.mode = 0x0001; + amc->bf50x.fctl = 0x0002; + break; + case 540 ... 549: + amc->io_write = bf54x_ebiu_amc_io_write_buffer; + amc->io_read = bf54x_ebiu_amc_io_read_buffer; + mmr_names = bf54x_mmr_names; + reg_size = sizeof (amc->bf54x) + 4; + + /* Initialize the AMC. */ + amc->bank_size = 64 * 1024 * 1024; + amgctl = 0x0002; + amc->bf54x.ambctl0 = 0xFFC2FFC2; + amc->bf54x.ambctl1 = 0xFFC2FFC2; + amc->bf54x.fctl = 0x0006; + break; + case 510 ... 519: + case 522 ... 527: + case 531 ... 533: + case 534: + case 536: + case 537: + case 538 ... 539: + case 561: + amc->io_write = bf53x_ebiu_amc_io_write_buffer; + amc->io_read = bf53x_ebiu_amc_io_read_buffer; + mmr_names = bf53x_mmr_names; + reg_size = sizeof (amc->bf53x) + 4; + + /* Initialize the AMC. */ + if (amc->type == 561) + amc->bank_size = 64 * 1024 * 1024; + else + amc->bank_size = 1 * 1024 * 1024; + amgctl = 0x00F2; + amc->bf53x.ambctl0 = 0xFFC2FFC2; + amc->bf53x.ambctl1 = 0xFFC2FFC2; + break; + case 590 ... 599: /* BF59x has no AMC. */ + default: + hw_abort (me, "no support for EBIU AMC on this Blackfin model yet"); + } + + attach_bfin_ebiu_amc_regs (me, amc, reg_size); + + bfin_ebiu_amc_write_amgctl (me, amc, amgctl); +} + +const struct hw_descriptor dv_bfin_ebiu_amc_descriptor[] = +{ + {"bfin_ebiu_amc", bfin_ebiu_amc_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.h new file mode 100644 index 000000000000..e47fd1177e9d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_amc.h @@ -0,0 +1,31 @@ +/* Blackfin External Bus Interface Unit (EBIU) Asynchronous Memory Controller + (AMC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EBIU_AMC_H +#define DV_BFIN_EBIU_AMC_H + +#define BFIN_MMR_EBIU_AMC_SIZE (4 * 3) +#define BF50X_MMR_EBIU_AMC_SIZE 0x28 +#define BF54X_MMR_EBIU_AMC_SIZE (4 * 7) + +#define BFIN_EBIU_AMC_BASE 0x20000000 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.c new file mode 100644 index 000000000000..a0095a13b5be --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.c @@ -0,0 +1,186 @@ +/* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ebiu_ddrc.h" + +struct bfin_ebiu_ddrc +{ + bu32 base, reg_size, bank_size; + + /* Order after here is important -- matches hardware MMR layout. */ + union { + struct { bu32 ddrctl0, ddrctl1, ddrctl2, ddrctl3; }; + bu32 ddrctl[4]; + }; + bu32 ddrque, erradd; + bu16 BFIN_MMR_16(errmst); + bu16 BFIN_MMR_16(rstctl); + bu32 ddrbrc[8], ddrbwc[8]; + bu32 ddracct, ddrtact, ddrarct; + bu32 ddrgc[4]; + bu32 ddrmcen, ddrmccl; +}; +#define mmr_base() offsetof(struct bfin_ebiu_ddrc, ddrctl0) +#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_ddrc, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "EBIU_DDRCTL0", "EBIU_DDRCTL1", "EBIU_DDRCTL2", "EBIU_DDRCTL3", "EBIU_DDRQUE", + "EBIU_ERRADD", "EBIU_ERRMST", "EBIU_RSTCTL", "EBIU_DDRBRC0", "EBIU_DDRBRC1", + "EBIU_DDRBRC2", "EBIU_DDRBRC3", "EBIU_DDRBRC4", "EBIU_DDRBRC5", + "EBIU_DDRBRC6", "EBIU_DDRBRC7", "EBIU_DDRBWC0", "EBIU_DDRBWC1" + "EBIU_DDRBWC2", "EBIU_DDRBWC3", "EBIU_DDRBWC4", "EBIU_DDRBWC5", + "EBIU_DDRBWC6", "EBIU_DDRBWC7", "EBIU_DDRACCT", "EBIU_DDRTACT", + "EBIU_ARCT", "EBIU_DDRGC0", "EBIU_DDRGC1", "EBIU_DDRGC2", "EBIU_DDRGC3", + "EBIU_DDRMCEN", "EBIU_DDRMCCL", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_ddrc *ddrc = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - ddrc->base; + valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(errmst): + case mmr_offset(rstctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + default: + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_ddrc *ddrc = hw_data (me); + bu32 mmr_off; + bu32 *value32p; + bu16 *value16p; + void *valuep; + + mmr_off = addr - ddrc->base; + valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(errmst): + case mmr_offset(rstctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + default: + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + dv_store_4 (dest, *value32p); + break; + } + + return nr_bytes; +} + +static void +attach_bfin_ebiu_ddrc_regs (struct hw *me, struct bfin_ebiu_ddrc *ddrc) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_EBIU_DDRC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_DDRC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + ddrc->base = attach_address; +} + +static void +bfin_ebiu_ddrc_finish (struct hw *me) +{ + struct bfin_ebiu_ddrc *ddrc; + + ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc); + + set_hw_data (me, ddrc); + set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer); + + attach_bfin_ebiu_ddrc_regs (me, ddrc); + + /* Initialize the DDRC. */ + ddrc->ddrctl0 = 0x098E8411; + ddrc->ddrctl1 = 0x10026223; + ddrc->ddrctl2 = 0x00000021; + ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ... */ + ddrc->ddrque = 0x00001115; + ddrc->rstctl = 0x0002; +} + +const struct hw_descriptor dv_bfin_ebiu_ddrc_descriptor[] = +{ + {"bfin_ebiu_ddrc", bfin_ebiu_ddrc_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.h new file mode 100644 index 000000000000..ac970bf53171 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_ddrc.h @@ -0,0 +1,26 @@ +/* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EBIU_DDRC_H +#define DV_BFIN_EBIU_DDRC_H + +#define BFIN_MMR_EBIU_DDRC_SIZE 0xb0 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.c new file mode 100644 index 000000000000..da9524d8a9b7 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.c @@ -0,0 +1,203 @@ +/* Blackfin External Bus Interface Unit (EBIU) SDRAM Controller (SDC) Model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ebiu_sdc.h" + +struct bfin_ebiu_sdc +{ + bu32 base; + int type; + bu32 reg_size, bank_size; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 sdgctl; + bu32 sdbctl; /* 16bit on most parts ... */ + bu16 BFIN_MMR_16(sdrrc); + bu16 BFIN_MMR_16(sdstat); +}; +#define mmr_base() offsetof(struct bfin_ebiu_sdc, sdgctl) +#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_sdc, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "EBIU_SDGCTL", "EBIU_SDBCTL", "EBIU_SDRRC", "EBIU_SDSTAT", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_ebiu_sdc_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_sdc *sdc = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - sdc->base; + valuep = (void *)((unsigned long)sdc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(sdgctl): + /* XXX: SRFS should make external mem unreadable. */ + *value32p = value; + break; + case mmr_offset(sdbctl): + if (sdc->type == 561) + { + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + } + else + { + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + } + break; + case mmr_offset(sdrrc): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + case mmr_offset(sdstat): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + /* XXX: Some bits are W1C ... */ + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ebiu_sdc_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ebiu_sdc *sdc = hw_data (me); + bu32 mmr_off; + bu32 *value32p; + bu16 *value16p; + void *valuep; + + mmr_off = addr - sdc->base; + valuep = (void *)((unsigned long)sdc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(sdgctl): + dv_store_4 (dest, *value32p); + break; + case mmr_offset(sdbctl): + if (sdc->type == 561) + { + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + dv_store_4 (dest, *value32p); + } + else + { + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + } + break; + case mmr_offset(sdrrc): + case mmr_offset(sdstat): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + } + + return nr_bytes; +} + +static void +attach_bfin_ebiu_sdc_regs (struct hw *me, struct bfin_ebiu_sdc *sdc) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_EBIU_SDC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_SDC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + sdc->base = attach_address; +} + +static void +bfin_ebiu_sdc_finish (struct hw *me) +{ + struct bfin_ebiu_sdc *sdc; + + sdc = HW_ZALLOC (me, struct bfin_ebiu_sdc); + + set_hw_data (me, sdc); + set_hw_io_read_buffer (me, bfin_ebiu_sdc_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ebiu_sdc_io_write_buffer); + + attach_bfin_ebiu_sdc_regs (me, sdc); + + sdc->type = hw_find_integer_property (me, "type"); + + /* Initialize the SDC. */ + sdc->sdgctl = 0xE0088849; + sdc->sdbctl = 0x00000000; + sdc->sdrrc = 0x081A; + sdc->sdstat = 0x0008; + + /* XXX: We boot with 64M external memory by default ... */ + sdc->sdbctl |= EBE | EBSZ_64 | EBCAW_10; +} + +const struct hw_descriptor dv_bfin_ebiu_sdc_descriptor[] = +{ + {"bfin_ebiu_sdc", bfin_ebiu_sdc_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.h new file mode 100644 index 000000000000..7849806d9362 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ebiu_sdc.h @@ -0,0 +1,39 @@ +/* Blackfin External Bus Interface Unit (EBIU) SDRAM Controller (SDC) Model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EBIU_SDC_H +#define DV_BFIN_EBIU_SDC_H + +#define BFIN_MMR_EBIU_SDC_SIZE (4 * 4) + +/* EBIU_SDBCTL Masks */ +#define EBE 0x0001 /* Enable SDRAM External Bank */ +#define EBSZ_16 0x0000 /* Size = 16MB */ +#define EBSZ_32 0x0002 /* Size = 32MB */ +#define EBSZ_64 0x0004 /* Size = 64MB */ +#define EBSZ_128 0x0006 /* Size = 128MB */ +#define EBSZ_256 0x0008 /* Size = 256MB */ +#define EBSZ_512 0x000A /* Size = 512MB */ +#define EBCAW_8 0x0000 /* Column Address Width = 8 Bits */ +#define EBCAW_9 0x0010 /* Column Address Width = 9 Bits */ +#define EBCAW_10 0x0020 /* Column Address Width = 10 Bits */ +#define EBCAW_11 0x0030 /* Column Address Width = 11 Bits */ + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.c new file mode 100644 index 000000000000..af14103ea4fc --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.c @@ -0,0 +1,606 @@ +/* Blackfin Ethernet Media Access Controller (EMAC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include +#include +#include + +#ifdef HAVE_SYS_IOCTL_H +#include +#endif +#ifdef HAVE_NET_IF_H +#include +#endif +#ifdef HAVE_LINUX_IF_TUN_H +#include +#endif + +#ifdef HAVE_LINUX_IF_TUN_H +# define WITH_TUN 1 +#else +# define WITH_TUN 0 +#endif + +#include "sim-main.h" +#include "sim-hw.h" +#include "devices.h" +#include "dv-bfin_emac.h" + +/* XXX: This doesn't support partial DMA transfers. */ +/* XXX: The TUN pieces should be pushed to the PHY so that we work with + multiple "networks" and the PHY takes care of it. */ + +struct bfin_emac +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + int tap; +#if WITH_TUN + struct ifreq ifr; +#endif + bu32 rx_crc; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 opmode, addrlo, addrhi, hashlo, hashhi, staadd, stadat, flc, vlan1, vlan2; + bu32 _pad0; + bu32 wkup_ctl, wkup_ffmsk0, wkup_ffmsk1, wkup_ffmsk2, wkup_ffmsk3; + bu32 wkup_ffcmd, wkup_ffoff, wkup_ffcrc0, wkup_ffcrc1; + bu32 _pad1[4]; + bu32 sysctl, systat, rx_stat, rx_stky, rx_irqe, tx_stat, tx_stky, tx_irqe; + bu32 mmc_ctl, mmc_rirqs, mmc_rirqe, mmc_tirqs, mmc_tirqe; + bu32 _pad2[3]; + bu16 BFIN_MMR_16(ptp_ctl); + bu16 BFIN_MMR_16(ptp_ie); + bu16 BFIN_MMR_16(ptp_istat); + bu32 ptp_foff, ptp_fv1, ptp_fv2, ptp_fv3, ptp_addend, ptp_accr, ptp_offset; + bu32 ptp_timelo, ptp_timehi, ptp_rxsnaplo, ptp_rxsnaphi, ptp_txsnaplo; + bu32 ptp_txsnaphi, ptp_alarmlo, ptp_alarmhi, ptp_id_off, ptp_id_snap; + bu32 ptp_pps_startlo, ptp_pps_starthi, ptp_pps_period; + bu32 _pad3[1]; + bu32 rxc_ok, rxc_fcs, rxc_lign, rxc_octet, rxc_dmaovf, rxc_unicst, rxc_multi; + bu32 rxc_broad, rxc_lnerri, rxc_lnerro, rxc_long, rxc_macctl, rxc_opcode; + bu32 rxc_pause, rxc_allfrm, rxc_alloct, rxc_typed, rxc_short, rxc_eq64; + bu32 rxc_lt128, rxc_lt256, rxc_lt512, rxc_lt1024, rxc_ge1024; + bu32 _pad4[8]; + bu32 txc_ok, txc_1col, txc_gt1col, txc_octet, txc_defer, txc_latecl; + bu32 txc_xs_col, txc_dmaund, txc_crserr, txc_unicst, txc_multi, txc_broad; + bu32 txc_xs_dfr, txc_macctl, txc_allfrm, txc_alloct, txc_eq64, txc_lt128; + bu32 txc_lt256, txc_lt512, txc_lt1024, txc_ge1024, txc_abort; +}; +#define mmr_base() offsetof(struct bfin_emac, opmode) +#define mmr_offset(mmr) (offsetof(struct bfin_emac, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[BFIN_MMR_EMAC_SIZE / 4] = +{ + "EMAC_OPMODE", "EMAC_ADDRLO", "EMAC_ADDRHI", "EMAC_HASHLO", "EMAC_HASHHI", + "EMAC_STAADD", "EMAC_STADAT", "EMAC_FLC", "EMAC_VLAN1", "EMAC_VLAN2", NULL, + "EMAC_WKUP_CTL", "EMAC_WKUP_FFMSK0", "EMAC_WKUP_FFMSK1", "EMAC_WKUP_FFMSK2", + "EMAC_WKUP_FFMSK3", "EMAC_WKUP_FFCMD", "EMAC_WKUP_FFOFF", "EMAC_WKUP_FFCRC0", + "EMAC_WKUP_FFCRC1", [mmr_idx (sysctl)] = "EMAC_SYSCTL", "EMAC_SYSTAT", + "EMAC_RX_STAT", "EMAC_RX_STKY", "EMAC_RX_IRQE", "EMAC_TX_STAT", + "EMAC_TX_STKY", "EMAC_TX_IRQE", "EMAC_MMC_CTL", "EMAC_MMC_RIRQS", + "EMAC_MMC_RIRQE", "EMAC_MMC_TIRQS", "EMAC_MMC_TIRQE", + [mmr_idx (ptp_ctl)] = "EMAC_PTP_CTL", "EMAC_PTP_IE", "EMAC_PTP_ISTAT", + "EMAC_PTP_FOFF", "EMAC_PTP_FV1", "EMAC_PTP_FV2", "EMAC_PTP_FV3", + "EMAC_PTP_ADDEND", "EMAC_PTP_ACCR", "EMAC_PTP_OFFSET", "EMAC_PTP_TIMELO", + "EMAC_PTP_TIMEHI", "EMAC_PTP_RXSNAPLO", "EMAC_PTP_RXSNAPHI", + "EMAC_PTP_TXSNAPLO", "EMAC_PTP_TXSNAPHI", "EMAC_PTP_ALARMLO", + "EMAC_PTP_ALARMHI", "EMAC_PTP_ID_OFF", "EMAC_PTP_ID_SNAP", + "EMAC_PTP_PPS_STARTLO", "EMAC_PTP_PPS_STARTHI", "EMAC_PTP_PPS_PERIOD", + [mmr_idx (rxc_ok)] = "EMAC_RXC_OK", "EMAC_RXC_FCS", "EMAC_RXC_LIGN", + "EMAC_RXC_OCTET", "EMAC_RXC_DMAOVF", "EMAC_RXC_UNICST", "EMAC_RXC_MULTI", + "EMAC_RXC_BROAD", "EMAC_RXC_LNERRI", "EMAC_RXC_LNERRO", "EMAC_RXC_LONG", + "EMAC_RXC_MACCTL", "EMAC_RXC_OPCODE", "EMAC_RXC_PAUSE", "EMAC_RXC_ALLFRM", + "EMAC_RXC_ALLOCT", "EMAC_RXC_TYPED", "EMAC_RXC_SHORT", "EMAC_RXC_EQ64", + "EMAC_RXC_LT128", "EMAC_RXC_LT256", "EMAC_RXC_LT512", "EMAC_RXC_LT1024", + "EMAC_RXC_GE1024", + [mmr_idx (txc_ok)] = "EMAC_TXC_OK", "EMAC_TXC_1COL", "EMAC_TXC_GT1COL", + "EMAC_TXC_OCTET", "EMAC_TXC_DEFER", "EMAC_TXC_LATECL", "EMAC_TXC_XS_COL", + "EMAC_TXC_DMAUND", "EMAC_TXC_CRSERR", "EMAC_TXC_UNICST", "EMAC_TXC_MULTI", + "EMAC_TXC_BROAD", "EMAC_TXC_XS_DFR", "EMAC_TXC_MACCTL", "EMAC_TXC_ALLFRM", + "EMAC_TXC_ALLOCT", "EMAC_TXC_EQ64", "EMAC_TXC_LT128", "EMAC_TXC_LT256", + "EMAC_TXC_LT512", "EMAC_TXC_LT1024", "EMAC_TXC_GE1024", "EMAC_TXC_ABORT", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static struct hw * +mii_find_phy (struct hw *me, bu8 addr) +{ + struct hw *phy = hw_child (me); + while (phy && --addr) + phy = hw_sibling (phy); + return phy; +} + +static void +mii_write (struct hw *me) +{ + SIM_DESC sd = hw_system (me); + struct bfin_emac *emac = hw_data (me); + struct hw *phy; + bu8 addr = PHYAD (emac->staadd); + bu8 reg = REGAD (emac->staadd); + bu16 data = emac->stadat; + + phy = mii_find_phy (me, addr); + if (!phy) + return; + sim_hw_io_write_buffer (sd, phy, &data, 1, reg, 2); +} + +static void +mii_read (struct hw *me) +{ + SIM_DESC sd = hw_system (me); + struct bfin_emac *emac = hw_data (me); + struct hw *phy; + bu8 addr = PHYAD (emac->staadd); + bu8 reg = REGAD (emac->staadd); + bu16 data; + + phy = mii_find_phy (me, addr); + if (!phy || sim_hw_io_read_buffer (sd, phy, &data, 1, reg, 2) != 2) + data = 0xffff; + + emac->stadat = data; +} + +static unsigned +bfin_emac_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_emac *emac = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + /* XXX: 16bit accesses are allowed ... */ + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + value = dv_load_4 (source); + + mmr_off = addr - emac->base; + valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(hashlo): + case mmr_offset(hashhi): + case mmr_offset(stadat): + case mmr_offset(flc): + case mmr_offset(vlan1): + case mmr_offset(vlan2): + case mmr_offset(wkup_ffmsk0): + case mmr_offset(wkup_ffmsk1): + case mmr_offset(wkup_ffmsk2): + case mmr_offset(wkup_ffmsk3): + case mmr_offset(wkup_ffcmd): + case mmr_offset(wkup_ffoff): + case mmr_offset(wkup_ffcrc0): + case mmr_offset(wkup_ffcrc1): + case mmr_offset(sysctl): + case mmr_offset(rx_irqe): + case mmr_offset(tx_irqe): + case mmr_offset(mmc_rirqe): + case mmr_offset(mmc_tirqe): + *valuep = value; + break; + case mmr_offset(opmode): + if (!(*valuep & RE) && (value & RE)) + emac->rx_stat &= ~RX_COMP; + if (!(*valuep & TE) && (value & TE)) + emac->tx_stat &= ~TX_COMP; + *valuep = value; + break; + case mmr_offset(addrlo): + case mmr_offset(addrhi): + *valuep = value; + break; + case mmr_offset(wkup_ctl): + dv_w1c_4_partial (valuep, value, 0xf20); + break; + case mmr_offset(systat): + dv_w1c_4 (valuep, value, 0xe1); + break; + case mmr_offset(staadd): + *valuep = value | STABUSY; + if (value & STAOP) + mii_write (me); + else + mii_read (me); + *valuep &= ~STABUSY; + break; + case mmr_offset(rx_stat): + case mmr_offset(tx_stat): + /* Discard writes to these. */ + break; + case mmr_offset(rx_stky): + case mmr_offset(tx_stky): + case mmr_offset(mmc_rirqs): + case mmr_offset(mmc_tirqs): + dv_w1c_4 (valuep, value, -1); + break; + case mmr_offset(mmc_ctl): + /* Writing to bit 0 clears all counters. */ + *valuep = value & ~1; + if (value & 1) + { + memset (&emac->rxc_ok, 0, mmr_offset (rxc_ge1024) - mmr_offset (rxc_ok) + 4); + memset (&emac->txc_ok, 0, mmr_offset (txc_abort) - mmr_offset (txc_ok) + 4); + } + break; + case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024): + case mmr_offset(txc_ok) ... mmr_offset(txc_abort): + /* XXX: Are these supposed to be read-only ? */ + *valuep = value; + break; + case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period): + /* XXX: Only on some models; ignore for now. */ + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_emac_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_emac *emac = hw_data (me); + bu32 mmr_off; + bu32 *valuep; + + /* XXX: 16bit accesses are allowed ... */ + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + + mmr_off = addr - emac->base; + valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(opmode): + case mmr_offset(addrlo): + case mmr_offset(addrhi): + case mmr_offset(hashlo): + case mmr_offset(hashhi): + case mmr_offset(staadd): + case mmr_offset(stadat): + case mmr_offset(flc): + case mmr_offset(vlan1): + case mmr_offset(vlan2): + case mmr_offset(wkup_ctl): + case mmr_offset(wkup_ffmsk0): + case mmr_offset(wkup_ffmsk1): + case mmr_offset(wkup_ffmsk2): + case mmr_offset(wkup_ffmsk3): + case mmr_offset(wkup_ffcmd): + case mmr_offset(wkup_ffoff): + case mmr_offset(wkup_ffcrc0): + case mmr_offset(wkup_ffcrc1): + case mmr_offset(sysctl): + case mmr_offset(systat): + case mmr_offset(rx_stat): + case mmr_offset(rx_stky): + case mmr_offset(rx_irqe): + case mmr_offset(tx_stat): + case mmr_offset(tx_stky): + case mmr_offset(tx_irqe): + case mmr_offset(mmc_rirqs): + case mmr_offset(mmc_rirqe): + case mmr_offset(mmc_tirqs): + case mmr_offset(mmc_tirqe): + case mmr_offset(mmc_ctl): + case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024): + case mmr_offset(txc_ok) ... mmr_offset(txc_abort): + dv_store_4 (dest, *valuep); + break; + case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period): + /* XXX: Only on some models; ignore for now. */ + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static void +attach_bfin_emac_regs (struct hw *me, struct bfin_emac *emac) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_EMAC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EMAC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + emac->base = attach_address; +} + +static struct dv_bfin *dma_tx; + +static unsigned +bfin_emac_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + struct bfin_emac *emac = hw_data (me); + struct dv_bfin *dma = hw_data (emac->dma_master); + unsigned char *data = dest; + static bool flop; /* XXX: This sucks. */ + bu16 len; + ssize_t ret; + + HW_TRACE_DMA_READ (); + + if (dma_tx == dma) + { + /* Handle the TX turn around and write the status. */ + emac->tx_stat |= TX_OK; + emac->tx_stky |= TX_OK; + + memcpy (data, &emac->tx_stat, 4); + + dma->acked = true; + return 4; + } + + if (!(emac->opmode & RE)) + return 0; + + if (!flop) + { + ssize_t pad_ret; + /* Outgoing DMA buffer has 16bit len prepended to it. */ + data += 2; + + /* This doesn't seem to work. + if (emac->sysctl & RXDWA) + { + memset (data, 0, 2); + data += 2; + } */ + + ret = read (emac->tap, data, nr_bytes); + if (ret < 0) + return 0; + ret += 4; /* include crc */ + pad_ret = MAX (ret + 4, 64); + len = pad_ret; + memcpy (dest, &len, 2); + + pad_ret = (pad_ret + 3) & ~3; + if (ret < pad_ret) + memset (data + ret, 0, pad_ret - ret); + pad_ret += 4; + + /* XXX: Need to check -- u-boot doesn't look at this. */ + if (emac->sysctl & RXCKS) + { + pad_ret += 4; + emac->rx_crc = 0; + } + ret = pad_ret; + + /* XXX: Don't support promiscuous yet. */ + emac->rx_stat |= RX_ACCEPT; + emac->rx_stat = (emac->rx_stat & ~RX_FRLEN) | len; + + emac->rx_stat |= RX_COMP; + emac->rx_stky |= RX_COMP; + } + else + { + /* Write the RX status and crc info. */ + emac->rx_stat |= RX_OK; + emac->rx_stky |= RX_OK; + + ret = 4; + if (emac->sysctl & RXCKS) + { + memcpy (data, &emac->rx_crc, 4); + data += 4; + ret += 4; + } + memcpy (data, &emac->rx_stat, 4); + } + + flop = !flop; + dma->acked = true; + return ret; +} + +static unsigned +bfin_emac_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_emac *emac = hw_data (me); + struct dv_bfin *dma = hw_data (emac->dma_master); + const unsigned char *data = source; + bu16 len; + ssize_t ret; + + HW_TRACE_DMA_WRITE (); + + if (!(emac->opmode & TE)) + return 0; + + /* Incoming DMA buffer has 16bit len prepended to it. */ + memcpy (&len, data, 2); + if (!len) + return 0; + + ret = write (emac->tap, data + 2, len); + if (ret < 0) + return 0; + ret += 2; + + emac->tx_stat |= TX_COMP; + emac->tx_stky |= TX_COMP; + + dma_tx = dma; + dma->acked = true; + return ret; +} + +static const struct hw_port_descriptor bfin_emac_ports[] = +{ + { "tx", DV_PORT_TX, 0, output_port, }, + { "rx", DV_PORT_RX, 0, output_port, }, + { "stat", DV_PORT_STAT, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_emac_attach_address_callback (struct hw *me, + int level, + int space, + address_word addr, + address_word nr_bytes, + struct hw *client) +{ + const hw_unit *unit = hw_unit_address (client); + HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s", + level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client))); + /* NOTE: At preset the space is assumed to be zero. Perhaphs the + space should be mapped onto something for instance: space0 - + unified memory; space1 - IO memory; ... */ + sim_core_attach (hw_system (me), + NULL, /*cpu*/ + level + 10 + unit->cells[unit->nr_cells - 1], + access_read_write_exec, + space, addr, + nr_bytes, + 0, /* modulo */ + client, + NULL); +} + +static void +bfin_emac_delete (struct hw *me) +{ + struct bfin_emac *emac = hw_data (me); + close (emac->tap); +} + +static void +bfin_emac_tap_init (struct hw *me) +{ +#if WITH_TUN + struct bfin_emac *emac = hw_data (me); + const hw_unit *unit; + int flags; + + unit = hw_unit_address (me); + + emac->tap = open ("/dev/net/tun", O_RDWR); + if (emac->tap == -1) + { + HW_TRACE ((me, "unable to open /dev/net/tun: %s", strerror (errno))); + return; + } + + memset (&emac->ifr, 0, sizeof (emac->ifr)); + emac->ifr.ifr_flags = IFF_TAP | IFF_NO_PI; + strcpy (emac->ifr.ifr_name, "tap-gdb"); + + flags = 1 * 1024 * 1024; + if (ioctl (emac->tap, TUNSETIFF, &emac->ifr) < 0 +#ifdef TUNSETNOCSUM + || ioctl (emac->tap, TUNSETNOCSUM) < 0 +#endif +#ifdef TUNSETSNDBUF + || ioctl (emac->tap, TUNSETSNDBUF, &flags) < 0 +#endif + ) + { + HW_TRACE ((me, "tap ioctl setup failed: %s", strerror (errno))); + close (emac->tap); + return; + } + + flags = fcntl (emac->tap, F_GETFL); + fcntl (emac->tap, F_SETFL, flags | O_NONBLOCK); +#endif +} + +static void +bfin_emac_finish (struct hw *me) +{ + struct bfin_emac *emac; + + emac = HW_ZALLOC (me, struct bfin_emac); + + set_hw_data (me, emac); + set_hw_io_read_buffer (me, bfin_emac_io_read_buffer); + set_hw_io_write_buffer (me, bfin_emac_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_emac_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_emac_dma_write_buffer); + set_hw_ports (me, bfin_emac_ports); + set_hw_attach_address (me, bfin_emac_attach_address_callback); + set_hw_delete (me, bfin_emac_delete); + + attach_bfin_emac_regs (me, emac); + + /* Initialize the EMAC. */ + emac->addrlo = 0xffffffff; + emac->addrhi = 0x0000ffff; + emac->vlan1 = 0x0000ffff; + emac->vlan2 = 0x0000ffff; + emac->sysctl = 0x00003f00; + emac->mmc_ctl = 0x0000000a; + + bfin_emac_tap_init (me); +} + +const struct hw_descriptor dv_bfin_emac_descriptor[] = +{ + {"bfin_emac", bfin_emac_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.h new file mode 100644 index 000000000000..2522292c7641 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_emac.h @@ -0,0 +1,61 @@ +/* Blackfin Ethernet Media Access Controller (EMAC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EMAC_H +#define DV_BFIN_EMAC_H + +#define BFIN_MMR_EMAC_BASE 0xFFC03000 +#define BFIN_MMR_EMAC_SIZE 0x200 + +/* EMAC_OPMODE Masks */ +#define RE (1 << 0) +#define ASTP (1 << 1) +#define PR (1 << 7) +#define TE (1 << 16) + +/* EMAC_STAADD Masks */ +#define STABUSY (1 << 0) +#define STAOP (1 << 1) +#define STADISPRE (1 << 2) +#define STAIE (1 << 3) +#define REGAD_SHIFT 6 +#define REGAD_MASK (0x1f << REGAD_SHIFT) +#define REGAD(val) (((val) & REGAD_MASK) >> REGAD_SHIFT) +#define PHYAD_SHIFT 11 +#define PHYAD_MASK (0x1f << PHYAD_SHIFT) +#define PHYAD(val) (((val) & PHYAD_MASK) >> PHYAD_SHIFT) + +/* EMAC_SYSCTL Masks */ +#define PHYIE (1 << 0) +#define RXDWA (1 << 1) +#define RXCKS (1 << 2) +#define TXDWA (1 << 4) + +/* EMAC_RX_STAT Masks */ +#define RX_FRLEN 0x7ff +#define RX_COMP (1 << 12) +#define RX_OK (1 << 13) +#define RX_ACCEPT (1 << 31) + +/* EMAC_TX_STAT Masks */ +#define TX_COMP (1 << 0) +#define TX_OK (1 << 1) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.c new file mode 100644 index 000000000000..c151f3cfc1bb --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.c @@ -0,0 +1,274 @@ +/* Blackfin Enhanced Parallel Port Interface (EPPI) model + For "new style" PPIs on BF54x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_eppi.h" +#include "gui.h" + +/* XXX: TX is merely a stub. */ + +struct bfin_eppi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* GUI state. */ + void *gui_state; + int color; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(status); + bu16 BFIN_MMR_16(hcount); + bu16 BFIN_MMR_16(hdelay); + bu16 BFIN_MMR_16(vcount); + bu16 BFIN_MMR_16(vdelay); + bu16 BFIN_MMR_16(frame); + bu16 BFIN_MMR_16(line); + bu16 BFIN_MMR_16(clkdiv); + bu32 control, fs1w_hbl, fs1p_avpl, fsw2_lvb, fs2p_lavf, clip, err; +}; +#define mmr_base() offsetof(struct bfin_eppi, status) +#define mmr_offset(mmr) (offsetof(struct bfin_eppi, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "EPPI_STATUS", "EPPI_HCOUNT", "EPPI_HDELAY", "EPPI_VCOUNT", "EPPI_VDELAY", + "EPPI_FRAME", "EPPI_LINE", "EPPI_CLKDIV", "EPPI_CONTROL", "EPPI_FS1W_HBL", + "EPPI_FS1P_AVPL", "EPPI_FS2W_LVB", "EPPI_FS2P_LAVF", "EPPI_CLIP", "EPPI_ERR", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static void +bfin_eppi_gui_setup (struct bfin_eppi *eppi) +{ + /* If we are in RX mode, nothing to do. */ + if (!(eppi->control & PORT_DIR)) + return; + + eppi->gui_state = bfin_gui_setup (eppi->gui_state, + eppi->control & PORT_EN, + eppi->hcount, + eppi->vcount, + eppi->color); +} + +static unsigned +bfin_eppi_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_eppi *eppi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - eppi->base; + valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(status): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + dv_w1c_2 (value16p, value, 0x1ff); + break; + case mmr_offset(hcount): + case mmr_offset(hdelay): + case mmr_offset(vcount): + case mmr_offset(vdelay): + case mmr_offset(frame): + case mmr_offset(line): + case mmr_offset(clkdiv): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + case mmr_offset(control): + *value32p = value; + bfin_eppi_gui_setup (eppi); + break; + case mmr_offset(fs1w_hbl): + case mmr_offset(fs1p_avpl): + case mmr_offset(fsw2_lvb): + case mmr_offset(fs2p_lavf): + case mmr_offset(clip): + case mmr_offset(err): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_eppi_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_eppi *eppi = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - eppi->base; + valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(status): + case mmr_offset(hcount): + case mmr_offset(hdelay): + case mmr_offset(vcount): + case mmr_offset(vdelay): + case mmr_offset(frame): + case mmr_offset(line): + case mmr_offset(clkdiv): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + case mmr_offset(control): + case mmr_offset(fs1w_hbl): + case mmr_offset(fs1p_avpl): + case mmr_offset(fsw2_lvb): + case mmr_offset(fs2p_lavf): + case mmr_offset(clip): + case mmr_offset(err): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_eppi_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_eppi_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_eppi *eppi = hw_data (me); + + HW_TRACE_DMA_WRITE (); + + return bfin_gui_update (eppi->gui_state, source, nr_bytes); +} + +static const struct hw_port_descriptor bfin_eppi_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_eppi_regs (struct hw *me, struct bfin_eppi *eppi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_EPPI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EPPI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + eppi->base = attach_address; +} + +static void +bfin_eppi_finish (struct hw *me) +{ + struct bfin_eppi *eppi; + const char *color; + + eppi = HW_ZALLOC (me, struct bfin_eppi); + + set_hw_data (me, eppi); + set_hw_io_read_buffer (me, bfin_eppi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_eppi_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_eppi_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_eppi_dma_write_buffer); + set_hw_ports (me, bfin_eppi_ports); + + attach_bfin_eppi_regs (me, eppi); + + /* Initialize the EPPI. */ + if (hw_find_property (me, "color")) + color = hw_find_string_property (me, "color"); + else + color = NULL; + eppi->color = bfin_gui_color (color); +} + +const struct hw_descriptor dv_bfin_eppi_descriptor[] = +{ + {"bfin_eppi", bfin_eppi_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.h new file mode 100644 index 000000000000..1856800aacdf --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_eppi.h @@ -0,0 +1,30 @@ +/* Blackfin Enhanced Parallel Port Interface (EPPI) model + For "new style" PPIs on BF54x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EPPI_H +#define DV_BFIN_EPPI_H + +#include "dv-bfin_ppi.h" + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_EPPI_SIZE 0x40 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.c new file mode 100644 index 000000000000..80d4132ed236 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.c @@ -0,0 +1,155 @@ +/* Blackfin Event Vector Table (EVT) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_evt.h" + +struct bfin_evt +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 evt[16]; +}; +#define mmr_base() offsetof(struct bfin_evt, evt[0]) +#define mmr_offset(mmr) (offsetof(struct bfin_evt, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8", + "EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_evt_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_evt *evt = hw_data (me); + bu32 mmr_off; + bu32 value; + + value = dv_load_4 (source); + mmr_off = addr - evt->base; + + HW_TRACE_WRITE (); + + evt->evt[mmr_off / 4] = value; + + return nr_bytes; +} + +static unsigned +bfin_evt_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_evt *evt = hw_data (me); + bu32 mmr_off; + bu32 value; + + mmr_off = addr - evt->base; + + HW_TRACE_READ (); + + value = evt->evt[mmr_off / 4]; + + dv_store_4 (dest, value); + + return nr_bytes; +} + +static void +attach_bfin_evt_regs (struct hw *me, struct bfin_evt *evt) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_EVT_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_EVT_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + evt->base = attach_address; +} + +static void +bfin_evt_finish (struct hw *me) +{ + struct bfin_evt *evt; + + evt = HW_ZALLOC (me, struct bfin_evt); + + set_hw_data (me, evt); + set_hw_io_read_buffer (me, bfin_evt_io_read_buffer); + set_hw_io_write_buffer (me, bfin_evt_io_write_buffer); + + attach_bfin_evt_regs (me, evt); +} + +const struct hw_descriptor dv_bfin_evt_descriptor[] = +{ + {"bfin_evt", bfin_evt_finish,}, + {NULL, NULL}, +}; + +#define EVT_STATE(cpu) DV_STATE_CACHED (cpu, evt) + +void +cec_set_evt (SIM_CPU *cpu, int ivg, bu32 handler_addr) +{ + if (ivg > IVG15 || ivg < 0) + sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg); + + EVT_STATE (cpu)->evt[ivg] = handler_addr; +} + +bu32 +cec_get_evt (SIM_CPU *cpu, int ivg) +{ + if (ivg > IVG15 || ivg < 0) + sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg); + + return EVT_STATE (cpu)->evt[ivg]; +} + +bu32 +cec_get_reset_evt (SIM_CPU *cpu) +{ + /* XXX: This should tail into the model to get via BMODE pins. */ + return 0xef000000; +} diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.h new file mode 100644 index 000000000000..defa0826c060 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_evt.h @@ -0,0 +1,31 @@ +/* Blackfin Event Vector Table (EVT) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_EVT_H +#define DV_BFIN_EVT_H + +#define BFIN_COREMMR_EVT_BASE 0xFFE02000 +#define BFIN_COREMMR_EVT_SIZE (4 * 16) + +extern void cec_set_evt (SIM_CPU *, int ivg, bu32 handler_addr); +extern bu32 cec_get_evt (SIM_CPU *, int ivg); +extern bu32 cec_get_reset_evt (SIM_CPU *); + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.c new file mode 100644 index 000000000000..6847b52e0fd2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.c @@ -0,0 +1,325 @@ +/* Blackfin General Purpose Ports (GPIO) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_gpio.h" + +struct bfin_gpio +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(data); + bu16 BFIN_MMR_16(clear); + bu16 BFIN_MMR_16(set); + bu16 BFIN_MMR_16(toggle); + bu16 BFIN_MMR_16(maska); + bu16 BFIN_MMR_16(maska_clear); + bu16 BFIN_MMR_16(maska_set); + bu16 BFIN_MMR_16(maska_toggle); + bu16 BFIN_MMR_16(maskb); + bu16 BFIN_MMR_16(maskb_clear); + bu16 BFIN_MMR_16(maskb_set); + bu16 BFIN_MMR_16(maskb_toggle); + bu16 BFIN_MMR_16(dir); + bu16 BFIN_MMR_16(polar); + bu16 BFIN_MMR_16(edge); + bu16 BFIN_MMR_16(both); + bu16 BFIN_MMR_16(inen); +}; +#define mmr_base() offsetof(struct bfin_gpio, data) +#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA", + "PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE", + "PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET", + "PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE", + "PORTIO_BOTH", "PORTIO_INEN", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gpio *port = hw_data (me); + bu32 mmr_off; + bu16 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - port->base; + valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(data): + case mmr_offset(maska): + case mmr_offset(maskb): + case mmr_offset(dir): + case mmr_offset(polar): + case mmr_offset(edge): + case mmr_offset(both): + case mmr_offset(inen): + *valuep = value; + break; + case mmr_offset(clear): + case mmr_offset(maska_clear): + case mmr_offset(maskb_clear): + /* We want to clear the related data MMR. */ + valuep -= 2; + dv_w1c_2 (valuep, value, -1); + break; + case mmr_offset(set): + case mmr_offset(maska_set): + case mmr_offset(maskb_set): + /* We want to set the related data MMR. */ + valuep -= 4; + *valuep |= value; + break; + case mmr_offset(toggle): + case mmr_offset(maska_toggle): + case mmr_offset(maskb_toggle): + /* We want to toggle the related data MMR. */ + valuep -= 6; + *valuep ^= value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gpio *port = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - port->base; + valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(data): + case mmr_offset(clear): + case mmr_offset(set): + case mmr_offset(toggle): + dv_store_2 (dest, port->data); + break; + case mmr_offset(maska): + case mmr_offset(maska_clear): + case mmr_offset(maska_set): + case mmr_offset(maska_toggle): + dv_store_2 (dest, port->maska); + break; + case mmr_offset(maskb): + case mmr_offset(maskb_clear): + case mmr_offset(maskb_set): + case mmr_offset(maskb_toggle): + dv_store_2 (dest, port->maskb); + break; + case mmr_offset(dir): + case mmr_offset(polar): + case mmr_offset(edge): + case mmr_offset(both): + case mmr_offset(inen): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_gpio_ports[] = +{ + { "mask_a", 0, 0, output_port, }, + { "mask_b", 1, 0, output_port, }, + { "p0", 0, 0, input_port, }, + { "p1", 1, 0, input_port, }, + { "p2", 2, 0, input_port, }, + { "p3", 3, 0, input_port, }, + { "p4", 4, 0, input_port, }, + { "p5", 5, 0, input_port, }, + { "p6", 6, 0, input_port, }, + { "p7", 7, 0, input_port, }, + { "p8", 8, 0, input_port, }, + { "p9", 9, 0, input_port, }, + { "p10", 10, 0, input_port, }, + { "p11", 11, 0, input_port, }, + { "p12", 12, 0, input_port, }, + { "p13", 13, 0, input_port, }, + { "p14", 14, 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_gpio *port = hw_data (me); + bool olvl, nlvl; + bu32 bit = (1 << my_port); + + /* Normalize the level value. A simulated device can send any value + it likes to us, but in reality we only care about 0 and 1. This + lets us assume only those two values below. */ + level = !!level; + + HW_TRACE ((me, "pin %i set to %i", my_port, level)); + + /* Only screw with state if this pin is set as an input, and the + input is actually enabled. */ + if ((port->dir & bit) || !(port->inen & bit)) + { + HW_TRACE ((me, "ignoring level/int due to DIR=%i INEN=%i", + !!(port->dir & bit), !!(port->inen & bit))); + return; + } + + /* Get the old pin state for calculating an interrupt. */ + olvl = !!(port->data & bit); + + /* Update the new pin state. */ + port->data = (port->data & ~bit) | (level << my_port); + + /* See if this state transition will generate an interrupt. */ + nlvl = !!(port->data & bit); + + if (port->edge & bit) + { + /* Pin is edge triggered. */ + if (port->both & bit) + { + /* Both edges. */ + if (olvl == nlvl) + { + HW_TRACE ((me, "ignoring int due to EDGE=%i BOTH=%i lvl=%i->%i", + !!(port->edge & bit), !!(port->both & bit), + olvl, nlvl)); + return; + } + } + else + { + /* Just one edge. */ + if (!(((port->polar & bit) && olvl > nlvl) + || (!(port->polar & bit) && olvl < nlvl))) + { + HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i->%i", + !!(port->edge & bit), !!(port->polar & bit), + olvl, nlvl)); + return; + } + } + } + else + { + /* Pin is level triggered. */ + if (nlvl == !!(port->polar & bit)) + { + HW_TRACE ((me, "ignoring int due to EDGE=%i POLAR=%i lvl=%i", + !!(port->edge & bit), !!(port->polar & bit), nlvl)); + return; + } + } + + /* If the masks allow it, push the interrupt even higher. */ + if (port->maska & bit) + { + HW_TRACE ((me, "pin %i triggered an int via mask a", my_port)); + hw_port_event (me, 0, 1); + } + if (port->maskb & bit) + { + HW_TRACE ((me, "pin %i triggered an int via mask b", my_port)); + hw_port_event (me, 1, 1); + } +} + +static void +attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_GPIO_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + port->base = attach_address; +} + +static void +bfin_gpio_finish (struct hw *me) +{ + struct bfin_gpio *port; + + port = HW_ZALLOC (me, struct bfin_gpio); + + set_hw_data (me, port); + set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer); + set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer); + set_hw_ports (me, bfin_gpio_ports); + set_hw_port_event (me, bfin_gpio_port_event); + + attach_bfin_gpio_regs (me, port); +} + +const struct hw_descriptor dv_bfin_gpio_descriptor[] = +{ + {"bfin_gpio", bfin_gpio_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.h new file mode 100644 index 000000000000..c73ca35681c6 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gpio.h @@ -0,0 +1,27 @@ +/* Blackfin General Purpose Ports (GPIO) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_GPIO_H +#define DV_BFIN_GPIO_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_GPIO_SIZE (17 * 4) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.c new file mode 100644 index 000000000000..07dec4579b51 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.c @@ -0,0 +1,186 @@ +/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_gptimer.h" + +/* XXX: This is merely a stub. */ + +struct bfin_gptimer +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(config); + bu32 counter, period, width; +}; +#define mmr_base() offsetof(struct bfin_gptimer, config) +#define mmr_offset(mmr) (offsetof(struct bfin_gptimer, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "TIMER_CONFIG", "TIMER_COUNTER", "TIMER_PERIOD", "TIMER_WIDTH", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_gptimer_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_gptimer_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_gptimer_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_gptimer_regs (struct hw *me, struct bfin_gptimer *gptimer) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_GPTIMER_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPTIMER_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + gptimer->base = attach_address; +} + +static void +bfin_gptimer_finish (struct hw *me) +{ + struct bfin_gptimer *gptimer; + + gptimer = HW_ZALLOC (me, struct bfin_gptimer); + + set_hw_data (me, gptimer); + set_hw_io_read_buffer (me, bfin_gptimer_io_read_buffer); + set_hw_io_write_buffer (me, bfin_gptimer_io_write_buffer); + set_hw_ports (me, bfin_gptimer_ports); + + attach_bfin_gptimer_regs (me, gptimer); +} + +const struct hw_descriptor dv_bfin_gptimer_descriptor[] = +{ + {"bfin_gptimer", bfin_gptimer_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.h new file mode 100644 index 000000000000..2c7c149e4972 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_gptimer.h @@ -0,0 +1,27 @@ +/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_GPTIMER_H +#define DV_BFIN_GPTIMER_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_GPTIMER_SIZE (4 * 4) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.c new file mode 100644 index 000000000000..e2d105d991f8 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.c @@ -0,0 +1,159 @@ +/* Blackfin JTAG model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_jtag.h" + +/* XXX: This is mostly a stub. There are more registers, but they're only + accessible via the JTAG scan chain and not the MMR interface. */ + +struct bfin_jtag +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 dspid; + bu32 _pad0; + bu32 dbgstat; +}; +#define mmr_base() offsetof(struct bfin_jtag, dspid) +#define mmr_offset(mmr) (offsetof(struct bfin_jtag, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "DSPID", NULL, "DBGSTAT", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static unsigned +bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_jtag *jtag = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + value = dv_load_4 (source); + mmr_off = addr - jtag->base; + valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(dbgstat): + dv_w1c_4 (valuep, value, 0xc); + break; + case mmr_offset(dspid): + /* Discard writes to these. */ + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_jtag_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_jtag *jtag = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + mmr_off = addr - jtag->base; + valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(dbgstat): + case mmr_offset(dspid): + value = *valuep; + break; + default: + while (1) /* Core MMRs -> exception -> doesn't return. */ + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + dv_store_4 (dest, value); + + return nr_bytes; +} + +static void +attach_bfin_jtag_regs (struct hw *me, struct bfin_jtag *jtag) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_JTAG_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_JTAG_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + jtag->base = attach_address; +} + +static void +bfin_jtag_finish (struct hw *me) +{ + struct bfin_jtag *jtag; + + jtag = HW_ZALLOC (me, struct bfin_jtag); + + set_hw_data (me, jtag); + set_hw_io_read_buffer (me, bfin_jtag_io_read_buffer); + set_hw_io_write_buffer (me, bfin_jtag_io_write_buffer); + + attach_bfin_jtag_regs (me, jtag); + + /* Initialize the JTAG state. */ + jtag->dspid = bfin_model_get_dspid (hw_system (me)); +} + +const struct hw_descriptor dv_bfin_jtag_descriptor[] = +{ + {"bfin_jtag", bfin_jtag_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.h new file mode 100644 index 000000000000..65c1d3be5776 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_jtag.h @@ -0,0 +1,27 @@ +/* Blackfin JTAG model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_JTAG_H +#define DV_BFIN_JTAG_H + +#define BFIN_COREMMR_JTAG_BASE 0xFFE05000 +#define BFIN_COREMMR_JTAG_SIZE (4 * 3) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.c new file mode 100644 index 000000000000..0e504344b0ef --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.c @@ -0,0 +1,576 @@ +/* Blackfin Memory Management Unit (MMU) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "sim-options.h" +#include "devices.h" +#include "dv-bfin_mmu.h" +#include "dv-bfin_cec.h" + +/* XXX: Should this really be two blocks of registers ? PRM describes + these as two Content Addressable Memory (CAM) blocks. */ + +struct bfin_mmu +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 sram_base_address; + + bu32 dmem_control, dcplb_fault_status, dcplb_fault_addr; + char _dpad0[0x100 - 0x0 - (4 * 4)]; + bu32 dcplb_addr[16]; + char _dpad1[0x200 - 0x100 - (4 * 16)]; + bu32 dcplb_data[16]; + char _dpad2[0x300 - 0x200 - (4 * 16)]; + bu32 dtest_command; + char _dpad3[0x400 - 0x300 - (4 * 1)]; + bu32 dtest_data[2]; + + char _dpad4[0x1000 - 0x400 - (4 * 2)]; + + bu32 idk; /* Filler MMR; hardware simply ignores. */ + bu32 imem_control, icplb_fault_status, icplb_fault_addr; + char _ipad0[0x100 - 0x0 - (4 * 4)]; + bu32 icplb_addr[16]; + char _ipad1[0x200 - 0x100 - (4 * 16)]; + bu32 icplb_data[16]; + char _ipad2[0x300 - 0x200 - (4 * 16)]; + bu32 itest_command; + char _ipad3[0x400 - 0x300 - (4 * 1)]; + bu32 itest_data[2]; +}; +#define mmr_base() offsetof(struct bfin_mmu, sram_base_address) +#define mmr_offset(mmr) (offsetof(struct bfin_mmu, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[BFIN_COREMMR_MMU_SIZE / 4] = +{ + "SRAM_BASE_ADDRESS", "DMEM_CONTROL", "DCPLB_FAULT_STATUS", "DCPLB_FAULT_ADDR", + [mmr_idx (dcplb_addr[0])] = "DCPLB_ADDR0", + "DCPLB_ADDR1", "DCPLB_ADDR2", "DCPLB_ADDR3", "DCPLB_ADDR4", "DCPLB_ADDR5", + "DCPLB_ADDR6", "DCPLB_ADDR7", "DCPLB_ADDR8", "DCPLB_ADDR9", "DCPLB_ADDR10", + "DCPLB_ADDR11", "DCPLB_ADDR12", "DCPLB_ADDR13", "DCPLB_ADDR14", "DCPLB_ADDR15", + [mmr_idx (dcplb_data[0])] = "DCPLB_DATA0", + "DCPLB_DATA1", "DCPLB_DATA2", "DCPLB_DATA3", "DCPLB_DATA4", "DCPLB_DATA5", + "DCPLB_DATA6", "DCPLB_DATA7", "DCPLB_DATA8", "DCPLB_DATA9", "DCPLB_DATA10", + "DCPLB_DATA11", "DCPLB_DATA12", "DCPLB_DATA13", "DCPLB_DATA14", "DCPLB_DATA15", + [mmr_idx (dtest_command)] = "DTEST_COMMAND", + [mmr_idx (dtest_data[0])] = "DTEST_DATA0", "DTEST_DATA1", + [mmr_idx (imem_control)] = "IMEM_CONTROL", "ICPLB_FAULT_STATUS", "ICPLB_FAULT_ADDR", + [mmr_idx (icplb_addr[0])] = "ICPLB_ADDR0", + "ICPLB_ADDR1", "ICPLB_ADDR2", "ICPLB_ADDR3", "ICPLB_ADDR4", "ICPLB_ADDR5", + "ICPLB_ADDR6", "ICPLB_ADDR7", "ICPLB_ADDR8", "ICPLB_ADDR9", "ICPLB_ADDR10", + "ICPLB_ADDR11", "ICPLB_ADDR12", "ICPLB_ADDR13", "ICPLB_ADDR14", "ICPLB_ADDR15", + [mmr_idx (icplb_data[0])] = "ICPLB_DATA0", + "ICPLB_DATA1", "ICPLB_DATA2", "ICPLB_DATA3", "ICPLB_DATA4", "ICPLB_DATA5", + "ICPLB_DATA6", "ICPLB_DATA7", "ICPLB_DATA8", "ICPLB_DATA9", "ICPLB_DATA10", + "ICPLB_DATA11", "ICPLB_DATA12", "ICPLB_DATA13", "ICPLB_DATA14", "ICPLB_DATA15", + [mmr_idx (itest_command)] = "ITEST_COMMAND", + [mmr_idx (itest_data[0])] = "ITEST_DATA0", "ITEST_DATA1", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static bool bfin_mmu_skip_cplbs = false; + +static unsigned +bfin_mmu_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_mmu *mmu = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + value = dv_load_4 (source); + + mmr_off = addr - mmu->base; + valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(dmem_control): + case mmr_offset(imem_control): + /* XXX: IMC/DMC bit should add/remove L1 cache regions ... */ + case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[1]): + case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[1]): + case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]): + case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]): + case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]): + case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]): + *valuep = value; + break; + case mmr_offset(sram_base_address): + case mmr_offset(dcplb_fault_status): + case mmr_offset(dcplb_fault_addr): + case mmr_offset(idk): + case mmr_offset(icplb_fault_status): + case mmr_offset(icplb_fault_addr): + /* Discard writes to these. */ + break; + case mmr_offset(itest_command): + /* XXX: Not supported atm. */ + if (value) + hw_abort (me, "ITEST_COMMAND unimplemented"); + break; + case mmr_offset(dtest_command): + /* Access L1 memory indirectly. */ + *valuep = value; + if (value) + { + bu32 addr = mmu->sram_base_address | + ((value >> (26 - 11)) & (1 << 11)) | /* addr bit 11 (Way0/Way1) */ + ((value >> (24 - 21)) & (1 << 21)) | /* addr bit 21 (Data/Inst) */ + ((value >> (23 - 15)) & (1 << 15)) | /* addr bit 15 (Data Bank) */ + ((value >> (16 - 12)) & (3 << 12)) | /* addr bits 13:12 (Subbank) */ + (value & 0x47F8); /* addr bits 14 & 10:3 */ + + if (!(value & TEST_DATA_ARRAY)) + hw_abort (me, "DTEST_COMMAND tag array unimplemented"); + if (value & 0xfa7cb801) + hw_abort (me, "DTEST_COMMAND bits undefined"); + + if (value & TEST_WRITE) + sim_write (hw_system (me), addr, (void *)mmu->dtest_data, 8); + else + sim_read (hw_system (me), addr, (void *)mmu->dtest_data, 8); + } + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_mmu_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_mmu *mmu = hw_data (me); + bu32 mmr_off; + bu32 *valuep; + + mmr_off = addr - mmu->base; + valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(dmem_control): + case mmr_offset(imem_control): + case mmr_offset(dtest_command): + case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[2]): + case mmr_offset(itest_command): + case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[2]): + /* XXX: should do something here. */ + case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]): + case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]): + case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]): + case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]): + case mmr_offset(sram_base_address): + case mmr_offset(dcplb_fault_status): + case mmr_offset(dcplb_fault_addr): + case mmr_offset(idk): + case mmr_offset(icplb_fault_status): + case mmr_offset(icplb_fault_addr): + dv_store_4 (dest, *valuep); + break; + default: + while (1) /* Core MMRs -> exception -> doesn't return. */ + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static void +attach_bfin_mmu_regs (struct hw *me, struct bfin_mmu *mmu) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_MMU_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_MMU_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + mmu->base = attach_address; +} + +static void +bfin_mmu_finish (struct hw *me) +{ + struct bfin_mmu *mmu; + + mmu = HW_ZALLOC (me, struct bfin_mmu); + + set_hw_data (me, mmu); + set_hw_io_read_buffer (me, bfin_mmu_io_read_buffer); + set_hw_io_write_buffer (me, bfin_mmu_io_write_buffer); + + attach_bfin_mmu_regs (me, mmu); + + /* Initialize the MMU. */ + mmu->sram_base_address = 0xff800000 - 0; + /*(4 * 1024 * 1024 * CPU_INDEX (hw_system_cpu (me)));*/ + mmu->dmem_control = 0x00000001; + mmu->imem_control = 0x00000001; +} + +const struct hw_descriptor dv_bfin_mmu_descriptor[] = +{ + {"bfin_mmu", bfin_mmu_finish,}, + {NULL, NULL}, +}; + +/* Device option parsing. */ + +static DECLARE_OPTION_HANDLER (bfin_mmu_option_handler); + +enum { + OPTION_MMU_SKIP_TABLES = OPTION_START, +}; + +const OPTION bfin_mmu_options[] = +{ + { {"mmu-skip-cplbs", no_argument, NULL, OPTION_MMU_SKIP_TABLES }, + '\0', NULL, "Skip parsing of CPLB tables (big speed increase)", + bfin_mmu_option_handler, NULL }, + + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL } +}; + +static SIM_RC +bfin_mmu_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt, + char *arg, int is_command) +{ + switch (opt) + { + case OPTION_MMU_SKIP_TABLES: + bfin_mmu_skip_cplbs = true; + return SIM_RC_OK; + + default: + sim_io_eprintf (sd, "Unknown Blackfin MMU option %d\n", opt); + return SIM_RC_FAIL; + } +} + +#define MMU_STATE(cpu) DV_STATE_CACHED (cpu, mmu) + +static void +_mmu_log_ifault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 pc, bool supv) +{ + mmu->icplb_fault_addr = pc; + mmu->icplb_fault_status = supv << 17; +} + +void +mmu_log_ifault (SIM_CPU *cpu) +{ + _mmu_log_ifault (cpu, MMU_STATE (cpu), PCREG, cec_get_ivg (cpu) >= 0); +} + +static void +_mmu_log_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write, + bool inst, bool miss, bool supv, bool dag1, bu32 faults) +{ + bu32 *fault_status, *fault_addr; + + /* No logging in non-OS mode. */ + if (!mmu) + return; + + fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status; + fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr; + /* ICPLB regs always get updated. */ + if (!inst) + _mmu_log_ifault (cpu, mmu, PCREG, supv); + + *fault_addr = addr; + *fault_status = + (miss << 19) | + (dag1 << 18) | + (supv << 17) | + (write << 16) | + faults; +} + +static void +_mmu_process_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write, + bool inst, bool unaligned, bool miss, bool supv, bool dag1) +{ + int excp; + + /* See order in mmu_check_addr() */ + if (unaligned) + excp = inst ? VEC_MISALI_I : VEC_MISALI_D; + else if (addr >= BFIN_SYSTEM_MMR_BASE) + excp = VEC_ILL_RES; + else if (!mmu) + excp = inst ? VEC_CPLB_I_M : VEC_CPLB_M; + else + { + /* Misses are hardware errors. */ + cec_hwerr (cpu, HWERR_EXTERN_ADDR); + return; + } + + _mmu_log_fault (cpu, mmu, addr, write, inst, miss, supv, dag1, 0); + cec_exception (cpu, excp); +} + +void +mmu_process_fault (SIM_CPU *cpu, bu32 addr, bool write, bool inst, + bool unaligned, bool miss) +{ + SIM_DESC sd = CPU_STATE (cpu); + struct bfin_mmu *mmu; + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) + mmu = NULL; + else + mmu = MMU_STATE (cpu); + + _mmu_process_fault (cpu, mmu, addr, write, inst, unaligned, miss, + cec_is_supervisor_mode (cpu), + BFIN_CPU_STATE.multi_pc == PCREG + 6); +} + +/* Return values: + -2: no known problems + -1: valid + 0: miss + 1: protection violation + 2: multiple hits + 3: unaligned + 4: miss; hwerr */ +static int +mmu_check_implicit_addr (SIM_CPU *cpu, bu32 addr, bool inst, int size, + bool supv, bool dag1) +{ + bool l1 = ((addr & 0xFF000000) == 0xFF000000); + bu32 amask = (addr & 0xFFF00000); + + if (addr & (size - 1)) + return 3; + + /* MMRs may never be executable or accessed from usermode. */ + if (addr >= BFIN_SYSTEM_MMR_BASE) + { + if (inst) + return 0; + else if (!supv || dag1) + return 1; + else + return -1; + } + else if (inst) + { + /* Some regions are not executable. */ + /* XXX: Should this be in the model data ? Core B 561 ? */ + if (l1) + return (amask == 0xFFA00000) ? -1 : 1; + } + else + { + /* Some regions are not readable. */ + /* XXX: Should this be in the model data ? Core B 561 ? */ + if (l1) + return (amask != 0xFFA00000) ? -1 : 4; + } + + return -2; +} + +/* Exception order per the PRM (first has highest): + Inst Multiple CPLB Hits + Inst Misaligned Access + Inst Protection Violation + Inst CPLB Miss + Only the alignment matters in non-OS mode though. */ +static int +_mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size) +{ + SIM_DESC sd = CPU_STATE (cpu); + struct bfin_mmu *mmu; + bu32 *fault_status, *fault_addr, *mem_control, *cplb_addr, *cplb_data; + bu32 faults; + bool supv, do_excp, dag1; + int i, hits; + + supv = cec_is_supervisor_mode (cpu); + dag1 = (BFIN_CPU_STATE.multi_pc == PCREG + 6); + + if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT || bfin_mmu_skip_cplbs) + { + int ret = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1); + /* Valid hits and misses are OK in non-OS envs. */ + if (ret < 0) + return 0; + _mmu_process_fault (cpu, NULL, addr, write, inst, (ret == 3), false, supv, dag1); + } + + mmu = MMU_STATE (cpu); + fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status; + fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr; + mem_control = inst ? &mmu->imem_control : &mmu->dmem_control; + cplb_addr = inst ? &mmu->icplb_addr[0] : &mmu->dcplb_addr[0]; + cplb_data = inst ? &mmu->icplb_data[0] : &mmu->dcplb_data[0]; + + faults = 0; + hits = 0; + do_excp = false; + + /* CPLBs disabled -> little to do. */ + if (!(*mem_control & ENCPLB)) + { + hits = 1; + goto implicit_check; + } + + /* Check all the CPLBs first. */ + for (i = 0; i < 16; ++i) + { + const bu32 pages[4] = { 0x400, 0x1000, 0x100000, 0x400000 }; + bu32 addr_lo, addr_hi; + + /* Skip invalid entries. */ + if (!(cplb_data[i] & CPLB_VALID)) + continue; + + /* See if this entry covers this address. */ + addr_lo = cplb_addr[i]; + addr_hi = cplb_addr[i] + pages[(cplb_data[i] & PAGE_SIZE) >> 16]; + if (addr < addr_lo || addr >= addr_hi) + continue; + + ++hits; + faults |= (1 << i); + if (write) + { + if (!supv && !(cplb_data[i] & CPLB_USER_WR)) + do_excp = true; + if (supv && !(cplb_data[i] & CPLB_SUPV_WR)) + do_excp = true; + if ((cplb_data[i] & (CPLB_WT | CPLB_L1_CHBL | CPLB_DIRTY)) == CPLB_L1_CHBL) + do_excp = true; + } + else + { + if (!supv && !(cplb_data[i] & CPLB_USER_RD)) + do_excp = true; + } + } + + /* Handle default/implicit CPLBs. */ + if (!do_excp && hits < 2) + { + int ihits; + implicit_check: + ihits = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1); + switch (ihits) + { + /* No faults and one match -> good to go. */ + case -1: return 0; + case -2: + if (hits == 1) + return 0; + break; + case 4: + cec_hwerr (cpu, HWERR_EXTERN_ADDR); + return 0; + default: + hits = ihits; + } + } + else + /* Normalize hit count so hits==2 is always multiple hit exception. */ + hits = MIN (2, hits); + + _mmu_log_fault (cpu, mmu, addr, write, inst, hits == 0, supv, dag1, faults); + + if (inst) + { + int iexcps[] = { VEC_CPLB_I_M, VEC_CPLB_I_VL, VEC_CPLB_I_MHIT, VEC_MISALI_I }; + return iexcps[hits]; + } + else + { + int dexcps[] = { VEC_CPLB_M, VEC_CPLB_VL, VEC_CPLB_MHIT, VEC_MISALI_D }; + return dexcps[hits]; + } +} + +void +mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size) +{ + int excp = _mmu_check_addr (cpu, addr, write, inst, size); + if (excp) + cec_exception (cpu, excp); +} + +void +mmu_check_cache_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst) +{ + bu32 cacheaddr; + int excp; + + cacheaddr = addr & ~(BFIN_L1_CACHE_BYTES - 1); + excp = _mmu_check_addr (cpu, cacheaddr, write, inst, BFIN_L1_CACHE_BYTES); + if (excp == 0) + return; + + /* Most exceptions are ignored with cache funcs. */ + /* XXX: Not sure if we should be ignoring CPLB misses. */ + if (inst) + { + if (excp == VEC_CPLB_I_VL) + return; + } + else + { + if (excp == VEC_CPLB_VL) + return; + } + cec_exception (cpu, excp); +} diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.h new file mode 100644 index 000000000000..e03a327f839c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_mmu.h @@ -0,0 +1,94 @@ +/* Blackfin Memory Management Unit (MMU) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_MMU_H +#define DV_BFIN_MMU_H + +#define BFIN_COREMMR_MMU_BASE 0xFFE00000 +#define BFIN_COREMMR_MMU_SIZE 0x2000 + +void mmu_check_addr (SIM_CPU *, bu32 addr, bool write, bool inst, int size); +void mmu_check_cache_addr (SIM_CPU *, bu32 addr, bool write, bool inst); +void mmu_process_fault (SIM_CPU *, bu32 addr, bool write, bool inst, bool unaligned, bool miss); +void mmu_log_ifault (SIM_CPU *); + +/* MEM_CONTROL */ +#define ENM (1 << 0) +#define ENCPLB (1 << 1) +#define MC (1 << 2) + +#define ENDM ENM +#define ENDCPLB ENCPLB +#define DMC_AB_SRAM 0x0 +#define DMC_AB_CACHE 0xc +#define DMC_ACACHE_BSRAM 0x8 + +/* CPLB_DATA */ +#define CPLB_VALID (1 << 0) +#define CPLB_USER_RD (1 << 2) +#define CPLB_USER_WR (1 << 3) +#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR) +#define CPLB_SUPV_WR (1 << 4) +#define CPLB_L1SRAM (1 << 5) +#define CPLB_DA0ACC (1 << 6) +#define CPLB_DIRTY (1 << 7) +#define CPLB_L1_CHBL (1 << 12) +#define CPLB_WT (1 << 14) +#define PAGE_SIZE (3 << 16) +#define PAGE_SIZE_1K (0 << 16) +#define PAGE_SIZE_4K (1 << 16) +#define PAGE_SIZE_1M (2 << 16) +#define PAGE_SIZE_4M (3 << 16) + +/* CPLB_STATUS */ +#define FAULT_CPLB0 (1 << 0) +#define FAULT_CPLB1 (1 << 1) +#define FAULT_CPLB2 (1 << 2) +#define FAULT_CPLB3 (1 << 3) +#define FAULT_CPLB4 (1 << 4) +#define FAULT_CPLB5 (1 << 5) +#define FAULT_CPLB6 (1 << 6) +#define FAULT_CPLB7 (1 << 7) +#define FAULT_CPLB8 (1 << 8) +#define FAULT_CPLB9 (1 << 9) +#define FAULT_CPLB10 (1 << 10) +#define FAULT_CPLB11 (1 << 11) +#define FAULT_CPLB12 (1 << 12) +#define FAULT_CPLB13 (1 << 13) +#define FAULT_CPLB14 (1 << 14) +#define FAULT_CPLB15 (1 << 15) +#define FAULT_READ (0 << 16) +#define FAULT_WRITE (1 << 16) +#define FAULT_USER (0 << 17) +#define FAULT_SUPV (1 << 17) +#define FAULT_DAG0 (0 << 18) +#define FAULT_DAG1 (1 << 18) +#define FAULT_ILLADDR (1 << 19) + +/* DTEST_COMMAND */ +#define TEST_READ (0 << 1) +#define TEST_WRITE (1 << 1) +#define TEST_TAG_ARRAY (0 << 2) +#define TEST_DATA_ARRAY (1 << 2) +#define TEST_DBANK (1 << 23) +#define TEST_DATA_SRAM (0 << 24) +#define TEST_INST_SRAM (1 << 24) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.c new file mode 100644 index 000000000000..2bd8b9e764a9 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.c @@ -0,0 +1,244 @@ +/* Blackfin NAND Flash Memory Controller (NFC) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_nfc.h" + +/* XXX: This is merely a stub. */ + +struct bfin_nfc +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(ctl); + bu16 BFIN_MMR_16(stat); + bu16 BFIN_MMR_16(irqstat); + bu16 BFIN_MMR_16(irqmask); + bu16 BFIN_MMR_16(ecc0); + bu16 BFIN_MMR_16(ecc1); + bu16 BFIN_MMR_16(ecc2); + bu16 BFIN_MMR_16(ecc3); + bu16 BFIN_MMR_16(count); + bu16 BFIN_MMR_16(rst); + bu16 BFIN_MMR_16(pgctl); + bu16 BFIN_MMR_16(read); + bu32 _pad0[4]; + bu16 BFIN_MMR_16(addr); + bu16 BFIN_MMR_16(cmd); + bu16 BFIN_MMR_16(data_wr); + bu16 BFIN_MMR_16(data_rd); +}; +#define mmr_base() offsetof(struct bfin_nfc, ctl) +#define mmr_offset(mmr) (offsetof(struct bfin_nfc, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[] = +{ + "NFC_CTL", "NFC_STAT", "NFC_IRQSTAT", "NFC_IRQMASK", "NFC_ECC0", "NFC_ECC1", + "NFC_ECC2", "NFC_ECC3", "NFC_COUNT", "NFC_RST", "NFC_PGCTL", "NFC_READ", + [mmr_idx (addr)] = "NFC_ADDR", "NFC_CMD", "NFC_DATA_WR", "NFC_DATA_RD", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static unsigned +bfin_nfc_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_nfc *nfc = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - nfc->base; + valuep = (void *)((unsigned long)nfc + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(ctl): + case mmr_offset(stat): + case mmr_offset(irqmask): + case mmr_offset(ecc0): + case mmr_offset(ecc1): + case mmr_offset(ecc2): + case mmr_offset(ecc3): + case mmr_offset(count): + case mmr_offset(rst): + case mmr_offset(pgctl): + case mmr_offset(read): + case mmr_offset(addr): + case mmr_offset(cmd): + case mmr_offset(data_wr): + *valuep = value; + break; + case mmr_offset(data_rd): + nfc->irqstat |= RD_RDY; + *valuep = value; + break; + case mmr_offset(irqstat): + dv_w1c_2 (valuep, value, -1); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_nfc_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_nfc *nfc = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - nfc->base; + valuep = (void *)((unsigned long)nfc + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(ctl): + case mmr_offset(stat): + case mmr_offset(irqstat): + case mmr_offset(irqmask): + case mmr_offset(ecc0): + case mmr_offset(ecc1): + case mmr_offset(ecc2): + case mmr_offset(ecc3): + case mmr_offset(count): + case mmr_offset(rst): + case mmr_offset(read): + dv_store_2 (dest, *valuep); + break; + case mmr_offset(pgctl): + case mmr_offset(addr): + case mmr_offset(cmd): + case mmr_offset(data_wr): + case mmr_offset(data_rd): + /* These regs are write only. */ + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_nfc_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_nfc_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + HW_TRACE_DMA_WRITE (); + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_nfc_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_nfc_regs (struct hw *me, struct bfin_nfc *nfc) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_NFC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_NFC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + nfc->base = attach_address; +} + +static void +bfin_nfc_finish (struct hw *me) +{ + struct bfin_nfc *nfc; + + nfc = HW_ZALLOC (me, struct bfin_nfc); + + set_hw_data (me, nfc); + set_hw_io_read_buffer (me, bfin_nfc_io_read_buffer); + set_hw_io_write_buffer (me, bfin_nfc_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_nfc_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_nfc_dma_write_buffer); + set_hw_ports (me, bfin_nfc_ports); + + attach_bfin_nfc_regs (me, nfc); + + /* Initialize the NFC. */ + nfc->ctl = 0x0200; + nfc->stat = 0x0011; + nfc->irqstat = 0x0004; + nfc->irqmask = 0x001F; +} + +const struct hw_descriptor dv_bfin_nfc_descriptor[] = +{ + {"bfin_nfc", bfin_nfc_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.h new file mode 100644 index 000000000000..42dbec6b43f7 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_nfc.h @@ -0,0 +1,41 @@ +/* Blackfin NAND Flash Memory Controller (NFC) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_NFC_H +#define DV_BFIN_NFC_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_NFC_SIZE 0x50 + +/* NFC_STAT masks. */ +#define NBUSY (1 << 0) +#define WB_FULL (1 << 1) +#define PG_WR_STAT (1 << 2) +#define PG_RD_STAT (1 << 3) +#define WB_EMPTY (1 << 4) + +/* NFC_IRQSTAT masks. */ +#define NBUSYIRQ (1 << 0) +#define WB_OVF (1 << 1) +#define WB_EDGE (1 << 2) +#define RD_RDY (1 << 3) +#define WR_DONE (1 << 4) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.c new file mode 100644 index 000000000000..e9f6271abacb --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.c @@ -0,0 +1,316 @@ +/* Blackfin One-Time Programmable Memory (OTP) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_otp.h" + +/* XXX: No public documentation on this interface. This seems to work + with the on-chip ROM functions though and was figured out by + disassembling & walking that code. */ +/* XXX: About only thing that should be done here are CRC fields. And + supposedly there is an interrupt that could be generated. */ + +struct bfin_otp +{ + bu32 base; + + /* The actual OTP storage -- 0x200 pages, each page is 128bits. + While certain pages have predefined and/or secure access, we don't + bother trying to implement that coverage. All pages are open for + reading & writing. */ + bu32 mem[0x200 * 4]; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(control); + bu16 BFIN_MMR_16(ben); + bu16 BFIN_MMR_16(status); + bu32 timing; + bu32 _pad0[28]; + bu32 data0, data1, data2, data3; +}; +#define mmr_base() offsetof(struct bfin_otp, control) +#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[] = +{ + "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING", + [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +/* XXX: This probably misbehaves with big endian hosts. */ +static void +bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc) +{ + bu8 *dst = vdst, *src = vsrc; + int bidx; + for (bidx = 0; bidx < 16; ++bidx) + if (otp->ben & (1 << bidx)) + dst[bidx] = src[bidx]; +} + +static void +bfin_otp_read_page (struct bfin_otp *otp, bu16 page) +{ + bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]); +} + +static void +bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2]) +{ + bfin_otp_transfer (otp, &otp->mem[page * 4], val); +} +static void +bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi) +{ + bu64 val[2] = { lo, hi }; + bfin_otp_write_page_val (otp, page, val); +} +static void +bfin_otp_write_page (struct bfin_otp *otp, bu16 page) +{ + bfin_otp_write_page_val (otp, page, (void *)&otp->data0); +} + +static unsigned +bfin_otp_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_otp *otp = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - otp->base; + valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(control): + { + int page; + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + /* XXX: Seems like these bits aren't writable. */ + *value16p = value & 0x39FF; + + /* Low bits seem to be the page address. */ + page = value & PAGE_ADDR; + + /* Write operation. */ + if (value & DO_WRITE) + bfin_otp_write_page (otp, page); + + /* Read operation. */ + if (value & DO_READ) + bfin_otp_read_page (otp, page); + + otp->status |= STATUS_DONE; + + break; + } + case mmr_offset(ben): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + /* XXX: All bits seem to be writable. */ + *value16p = value; + break; + case mmr_offset(status): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + /* XXX: All bits seem to be W1C. */ + dv_w1c_2 (value16p, value, -1); + break; + case mmr_offset(timing): + case mmr_offset(data0): + case mmr_offset(data1): + case mmr_offset(data2): + case mmr_offset(data3): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_otp_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_otp *otp = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - otp->base; + valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(ben): + case mmr_offset(status): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + case mmr_offset(timing): + case mmr_offset(data0): + case mmr_offset(data1): + case mmr_offset(data2): + case mmr_offset(data3): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static void +attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_OTP_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + otp->base = attach_address; +} + +static const struct hw_port_descriptor bfin_otp_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_otp_finish (struct hw *me) +{ + char part_str[16]; + struct bfin_otp *otp; + unsigned int fps03; + int type = hw_find_integer_property (me, "type"); + + otp = HW_ZALLOC (me, struct bfin_otp); + + set_hw_data (me, otp); + set_hw_io_read_buffer (me, bfin_otp_io_read_buffer); + set_hw_io_write_buffer (me, bfin_otp_io_write_buffer); + set_hw_ports (me, bfin_otp_ports); + + attach_bfin_otp_regs (me, otp); + + /* Initialize the OTP. */ + otp->ben = 0xFFFF; + otp->timing = 0x00001485; + + /* Semi-random value for unique chip id. */ + bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp); + + memset (part_str, 0, sizeof (part_str)); + sprintf (part_str, "ADSP-BF%iX", type); + switch (type) + { + case 512: + fps03 = FPS03_BF512; + break; + case 514: + fps03 = FPS03_BF514; + break; + case 516: + fps03 = FPS03_BF516; + break; + case 518: + fps03 = FPS03_BF518; + break; + case 522: + fps03 = FPS03_BF522; + break; + case 523: + fps03 = FPS03_BF523; + break; + case 524: + fps03 = FPS03_BF524; + break; + case 525: + fps03 = FPS03_BF525; + break; + case 526: + fps03 = FPS03_BF526; + break; + case 527: + fps03 = FPS03_BF527; + break; + default: + fps03 = 0; + break; + } + part_str[14] = (fps03 >> 0); + part_str[15] = (fps03 >> 8); + bfin_otp_write_page_val (otp, FPS03, (void *)part_str); +} + +const struct hw_descriptor dv_bfin_otp_descriptor[] = +{ + {"bfin_otp", bfin_otp_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.h new file mode 100644 index 000000000000..bbb49ce42116 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_otp.h @@ -0,0 +1,100 @@ +/* Blackfin One-Time Programmable Memory (OTP) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_OTP_H +#define DV_BFIN_OTP_H + +/* XXX: This should be pushed into the model data. */ +/* XXX: Not exactly true; it's two sets of 4 regs near each other: + 0xFFC03600 0x10 - Control + 0xFFC03680 0x10 - Data */ +#define BFIN_MMR_OTP_SIZE 0xa0 + +/* OTP Defined Pages. */ +#define FPS00 0x004 +#define FPS01 0x005 +#define FPS02 0x006 +#define FPS03 0x007 +#define FPS04 0x008 +#define FPS05 0x009 +#define FPS06 0x00A +#define FPS07 0x00B +#define FPS08 0x00C +#define FPS09 0x00D +#define FPS10 0x00E +#define FPS11 0x00F +#define CPS00 0x010 +#define CPS01 0x011 +#define CPS02 0x012 +#define CPS03 0x013 +#define CPS04 0x014 +#define CPS05 0x015 +#define CPS06 0x016 +#define CPS07 0x017 +#define PBS00 0x018 +#define PBS01 0x019 +#define PBS02 0x01A +#define PBS03 0x01B +#define PUB000 0x01C +#define PUBCRC000 0x0E0 +#define PRIV000 0x110 +#define PRIVCRC000 0x1E0 + +/* FPS03 Part values. */ +#define FPS03_BF51XF(n) (FPS03_BF##n | 0xF000) +#define FPS03_BF512 0x0200 +#define FPS03_BF512F FPS03_BF51XF(512) +#define FPS03_BF514 0x0202 +#define FPS03_BF514F FPS03_BF51XF(514) +#define FPS03_BF516 0x0204 +#define FPS03_BF516F FPS03_BF51XF(516) +#define FPS03_BF518 0x0206 +#define FPS03_BF518F FPS03_BF51XF(518) +#define FPS03_BF52X_C1(n) (FPS03_BF##n | 0x8000) +#define FPS03_BF52X_C2(n) (FPS03_BF##n | 0x4000) +#define FPS03_BF522 0x020A +#define FPS03_BF522_C1 FPS03_BF52X_C1(522) +#define FPS03_BF522_C2 FPS03_BF52X_C2(522) +#define FPS03_BF523 0x020B +#define FPS03_BF523_C1 FPS03_BF52X_C1(523) +#define FPS03_BF523_C2 FPS03_BF52X_C2(523) +#define FPS03_BF524 0x020C +#define FPS03_BF524_C1 FPS03_BF52X_C1(524) +#define FPS03_BF524_C2 FPS03_BF52X_C2(524) +#define FPS03_BF525 0x020D +#define FPS03_BF525_C1 FPS03_BF52X_C1(525) +#define FPS03_BF525_C2 FPS03_BF52X_C2(525) +#define FPS03_BF526 0x020E +#define FPS03_BF526_C1 FPS03_BF52X_C1(526) +#define FPS03_BF526_C2 FPS03_BF52X_C2(526) +#define FPS03_BF527 0x020F +#define FPS03_BF527_C1 FPS03_BF52X_C1(527) +#define FPS03_BF527_C2 FPS03_BF52X_C2(527) + +/* OTP_CONTROL masks. */ +#define PAGE_ADDR (0x1FF) +#define DO_READ (1 << 14) +#define DO_WRITE (1 << 15) + +/* OTP_STATUS masks. */ +#define STATUS_DONE (1 << 0) +#define STATUS_ERR (1 << 1) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.c new file mode 100644 index 000000000000..20032de91a4c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.c @@ -0,0 +1,190 @@ +/* Blackfin Phase Lock Loop (PLL) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "machs.h" +#include "devices.h" +#include "dv-bfin_pll.h" + +struct bfin_pll +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(pll_ctl); + bu16 BFIN_MMR_16(pll_div); + bu16 BFIN_MMR_16(vr_ctl); + bu16 BFIN_MMR_16(pll_stat); + bu16 BFIN_MMR_16(pll_lockcnt); + + /* XXX: Not really the best place for this ... */ + bu32 chipid; +}; +#define mmr_base() offsetof(struct bfin_pll, pll_ctl) +#define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_pll_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_pll *pll = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - pll->base; + valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(pll_stat): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + case mmr_offset(chipid): + /* Discard writes. */ + break; + default: + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + } + + return nr_bytes; +} + +static unsigned +bfin_pll_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_pll *pll = hw_data (me); + bu32 mmr_off; + bu32 *value32p; + bu16 *value16p; + void *valuep; + + mmr_off = addr - pll->base; + valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(chipid): + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_pll_ports[] = +{ + { "pll", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_PLL_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + pll->base = attach_address; +} + +static void +bfin_pll_finish (struct hw *me) +{ + struct bfin_pll *pll; + + pll = HW_ZALLOC (me, struct bfin_pll); + + set_hw_data (me, pll); + set_hw_io_read_buffer (me, bfin_pll_io_read_buffer); + set_hw_io_write_buffer (me, bfin_pll_io_write_buffer); + set_hw_ports (me, bfin_pll_ports); + + attach_bfin_pll_regs (me, pll); + + /* Initialize the PLL. */ + /* XXX: Depends on part ? */ + pll->pll_ctl = 0x1400; + pll->pll_div = 0x0005; + pll->vr_ctl = 0x40DB; + pll->pll_stat = 0x00A2; + pll->pll_lockcnt = 0x0200; + pll->chipid = bfin_model_get_chipid (hw_system (me)); + + /* XXX: slow it down! */ + pll->pll_ctl = 0xa800; + pll->pll_div = 0x4; + pll->vr_ctl = 0x40fb; + pll->pll_stat = 0xa2; + pll->pll_lockcnt = 0x300; +} + +const struct hw_descriptor dv_bfin_pll_descriptor[] = +{ + {"bfin_pll", bfin_pll_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.h new file mode 100644 index 000000000000..b63104a6f3fb --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_pll.h @@ -0,0 +1,27 @@ +/* Blackfin Phase Lock Loop (PLL) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_PLL_H +#define DV_BFIN_PLL_H + +#define BFIN_MMR_PLL_BASE 0xFFC00000 +#define BFIN_MMR_PLL_SIZE (4 * 6) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.c new file mode 100644 index 000000000000..e2f829246c32 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.c @@ -0,0 +1,234 @@ +/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ppi.h" +#include "gui.h" + +/* XXX: TX is merely a stub. */ + +struct bfin_ppi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* GUI state. */ + void *gui_state; + int color; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(control); + bu16 BFIN_MMR_16(status); + bu16 BFIN_MMR_16(count); + bu16 BFIN_MMR_16(delay); + bu16 BFIN_MMR_16(frame); +}; +#define mmr_base() offsetof(struct bfin_ppi, control) +#define mmr_offset(mmr) (offsetof(struct bfin_ppi, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "PPI_CONTROL", "PPI_STATUS", "PPI_COUNT", "PPI_DELAY", "PPI_FRAME", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static void +bfin_ppi_gui_setup (struct bfin_ppi *ppi) +{ + int bpp; + + /* If we are in RX mode, nothing to do. */ + if (!(ppi->control & PORT_DIR)) + return; + + bpp = bfin_gui_color_depth (ppi->color); + ppi->gui_state = bfin_gui_setup (ppi->gui_state, + ppi->control & PORT_EN, + (ppi->count + 1) / (bpp / 8), + ppi->frame, + ppi->color); +} + +static unsigned +bfin_ppi_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(control): + *valuep = value; + bfin_ppi_gui_setup (ppi); + break; + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + *valuep = value; + break; + case mmr_offset(status): + dv_w1c_2 (valuep, value, ~(1 << 10)); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + case mmr_offset(status): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_ppi_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_ppi *ppi = hw_data (me); + + HW_TRACE_DMA_WRITE (); + + return bfin_gui_update (ppi->gui_state, source, nr_bytes); +} + +static const struct hw_port_descriptor bfin_ppi_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_ppi_regs (struct hw *me, struct bfin_ppi *ppi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_PPI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PPI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + ppi->base = attach_address; +} + +static void +bfin_ppi_finish (struct hw *me) +{ + struct bfin_ppi *ppi; + const char *color; + + ppi = HW_ZALLOC (me, struct bfin_ppi); + + set_hw_data (me, ppi); + set_hw_io_read_buffer (me, bfin_ppi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ppi_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_ppi_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_ppi_dma_write_buffer); + set_hw_ports (me, bfin_ppi_ports); + + attach_bfin_ppi_regs (me, ppi); + + /* Initialize the PPI. */ + if (hw_find_property (me, "color")) + color = hw_find_string_property (me, "color"); + else + color = NULL; + ppi->color = bfin_gui_color (color); +} + +const struct hw_descriptor dv_bfin_ppi_descriptor[] = +{ + {"bfin_ppi", bfin_ppi_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.h new file mode 100644 index 000000000000..24e8fd9eb350 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_ppi.h @@ -0,0 +1,32 @@ +/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_PPI_H +#define DV_BFIN_PPI_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_PPI_SIZE (4 * 5) + +/* PPI_CONTROL Masks. */ +#define PORT_EN (1 << 0) +#define PORT_DIR (1 << 1) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.c new file mode 100644 index 000000000000..1b201484a7dd --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.c @@ -0,0 +1,197 @@ +/* Blackfin Real Time Clock (RTC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include +#include "sim-main.h" +#include "dv-sockser.h" +#include "devices.h" +#include "dv-bfin_rtc.h" + +/* XXX: This read-only stub setup is based on host system clock. */ + +struct bfin_rtc +{ + bu32 base; + bu32 stat_shadow; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 stat; + bu16 BFIN_MMR_16(ictl); + bu16 BFIN_MMR_16(istat); + bu16 BFIN_MMR_16(swcnt); + bu32 alarm; + bu16 BFIN_MMR_16(pren); +}; +#define mmr_base() offsetof(struct bfin_rtc, stat) +#define mmr_offset(mmr) (offsetof(struct bfin_rtc, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "RTC_STAT", "RTC_ICTL", "RTC_ISTAT", "RTC_SWCNT", "RTC_ALARM", "RTC_PREN", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_rtc_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_rtc *rtc = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - rtc->base; + valuep = (void *)((unsigned long)rtc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: These probably need more work. */ + switch (mmr_off) + { + case mmr_offset(stat): + /* XXX: Ignore these since we are wired to host. */ + break; + case mmr_offset(istat): + dv_w1c_2 (value16p, value, ~(1 << 14)); + break; + case mmr_offset(alarm): + break; + case mmr_offset(ictl): + /* XXX: This should schedule an event handler. */ + case mmr_offset(swcnt): + case mmr_offset(pren): + break; + } + + return nr_bytes; +} + +static unsigned +bfin_rtc_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_rtc *rtc = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - rtc->base; + valuep = (void *)((unsigned long)rtc + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(stat): + { + time_t t = time (NULL); + struct tm *tm = localtime (&t); + bu32 value = + (((tm->tm_year - 70) * 365 + tm->tm_yday) << 17) | + (tm->tm_hour << 12) | + (tm->tm_min << 6) | + (tm->tm_sec << 0); + dv_store_4 (dest, value); + break; + } + case mmr_offset(alarm): + dv_store_4 (dest, *value32p); + break; + case mmr_offset(istat): + case mmr_offset(ictl): + case mmr_offset(swcnt): + case mmr_offset(pren): + dv_store_2 (dest, *value16p); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_rtc_ports[] = +{ + { "rtc", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_rtc_regs (struct hw *me, struct bfin_rtc *rtc) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_RTC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_RTC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + rtc->base = attach_address; +} + +static void +bfin_rtc_finish (struct hw *me) +{ + struct bfin_rtc *rtc; + + rtc = HW_ZALLOC (me, struct bfin_rtc); + + set_hw_data (me, rtc); + set_hw_io_read_buffer (me, bfin_rtc_io_read_buffer); + set_hw_io_write_buffer (me, bfin_rtc_io_write_buffer); + set_hw_ports (me, bfin_rtc_ports); + + attach_bfin_rtc_regs (me, rtc); + + /* Initialize the RTC. */ +} + +const struct hw_descriptor dv_bfin_rtc_descriptor[] = +{ + {"bfin_rtc", bfin_rtc_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.h new file mode 100644 index 000000000000..04ffde144967 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_rtc.h @@ -0,0 +1,26 @@ +/* Blackfin Real Time Clock (RTC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_RTC_H +#define DV_BFIN_RTC_H + +#define BFIN_MMR_RTC_SIZE (4 * 6) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.c new file mode 100644 index 000000000000..3578388b4938 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.c @@ -0,0 +1,1462 @@ +/* Blackfin System Interrupt Controller (SIC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_sic.h" +#include "dv-bfin_cec.h" + +struct bfin_sic +{ + /* We assume first element is the base. */ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(swrst); + bu16 BFIN_MMR_16(syscr); + bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */ + union { + struct { + bu32 imask0; + bu32 iar0, iar1, iar2, iar3; + bu32 isr0, iwr0; + bu32 _pad0[9]; + bu32 imask1; + bu32 iar4, iar5, iar6, iar7; + bu32 isr1, iwr1; + } bf52x; + struct { + bu32 imask; + bu32 iar0, iar1, iar2, iar3; + bu32 isr, iwr; + } bf537; + struct { + bu32 imask0, imask1, imask2; + bu32 isr0, isr1, isr2; + bu32 iwr0, iwr1, iwr2; + bu32 iar0, iar1, iar2, iar3; + bu32 iar4, iar5, iar6, iar7; + bu32 iar8, iar9, iar10, iar11; + } bf54x; + struct { + bu32 imask0, imask1; + bu32 iar0, iar1, iar2, iar3; + bu32 iar4, iar5, iar6, iar7; + bu32 isr0, isr1; + bu32 iwr0, iwr1; + } bf561; + }; +}; +#define mmr_base() offsetof(struct bfin_sic, swrst) +#define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const bf52x_mmr_names[] = +{ + "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1", + "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0", + [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5", + "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1", +}; +static const char * const bf537_mmr_names[] = +{ + "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1", + "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR", +}; +static const char * const bf54x_mmr_names[] = +{ + "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2", + "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2", + "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3", + "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7", + "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11", +}; +static const char * const bf561_mmr_names[] = +{ + "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", + "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3", + "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7", + "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1", +}; +static const char * const *mmr_names; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static void +bfin_sic_forward_interrupts (struct hw *me, bu32 *isr, bu32 *imask, bu32 *iar) +{ + int my_port; + bu32 ipend; + + /* Process pending and unmasked interrupts. */ + ipend = *isr & *imask; + + /* Usually none are pending unmasked, so avoid bit twiddling. */ + if (!ipend) + return; + + for (my_port = 0; my_port < 32; ++my_port) + { + bu32 iar_idx, iar_off, iar_val; + bu32 bit = (1 << my_port); + + /* This bit isn't pending, so check next one. */ + if (!(ipend & bit)) + continue; + + /* The IAR registers map the System input to the Core output. + Every 4 bits in the IAR are used to map to IVG{7..15}. */ + iar_idx = my_port / 8; + iar_off = (my_port % 8) * 4; + iar_val = (iar[iar_idx] & (0xf << iar_off)) >> iar_off; + HW_TRACE ((me, "forwarding int %i to CEC", IVG7 + iar_val)); + hw_port_event (me, IVG7 + iar_val, 1); + } +} + +static void +bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic) +{ + bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0); + bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4); +} + +static unsigned +bfin_sic_52x_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: Discard all SIC writes for now. */ + switch (mmr_off) + { + case mmr_offset(swrst): + /* XXX: This should trigger a software reset ... */ + break; + case mmr_offset(syscr): + /* XXX: what to do ... */ + break; + case mmr_offset(bf52x.imask0): + case mmr_offset(bf52x.imask1): + bfin_sic_52x_forward_interrupts (me, sic); + *value32p = value; + break; + case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3): + case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7): + case mmr_offset(bf52x.iwr0): + case mmr_offset(bf52x.iwr1): + *value32p = value; + break; + case mmr_offset(bf52x.isr0): + case mmr_offset(bf52x.isr1): + /* ISR is read-only. */ + break; + default: + /* XXX: Should discard other writes. */ + ; + } + + return nr_bytes; +} + +static unsigned +bfin_sic_52x_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(swrst): + case mmr_offset(syscr): + case mmr_offset(rvect): + dv_store_2 (dest, *value16p); + break; + case mmr_offset(bf52x.imask0): + case mmr_offset(bf52x.imask1): + case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3): + case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7): + case mmr_offset(bf52x.iwr0): + case mmr_offset(bf52x.iwr1): + case mmr_offset(bf52x.isr0): + case mmr_offset(bf52x.isr1): + dv_store_4 (dest, *value32p); + break; + default: + if (nr_bytes == 2) + dv_store_2 (dest, 0); + else + dv_store_4 (dest, 0); + break; + } + + return nr_bytes; +} + +static void +bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic) +{ + bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0); +} + +static unsigned +bfin_sic_537_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: Discard all SIC writes for now. */ + switch (mmr_off) + { + case mmr_offset(swrst): + /* XXX: This should trigger a software reset ... */ + break; + case mmr_offset(syscr): + /* XXX: what to do ... */ + break; + case mmr_offset(bf537.imask): + bfin_sic_537_forward_interrupts (me, sic); + *value32p = value; + break; + case mmr_offset(bf537.iar0): + case mmr_offset(bf537.iar1): + case mmr_offset(bf537.iar2): + case mmr_offset(bf537.iar3): + case mmr_offset(bf537.iwr): + *value32p = value; + break; + case mmr_offset(bf537.isr): + /* ISR is read-only. */ + break; + default: + /* XXX: Should discard other writes. */ + ; + } + + return nr_bytes; +} + +static unsigned +bfin_sic_537_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(swrst): + case mmr_offset(syscr): + case mmr_offset(rvect): + dv_store_2 (dest, *value16p); + break; + case mmr_offset(bf537.imask): + case mmr_offset(bf537.iar0): + case mmr_offset(bf537.iar1): + case mmr_offset(bf537.iar2): + case mmr_offset(bf537.iar3): + case mmr_offset(bf537.isr): + case mmr_offset(bf537.iwr): + dv_store_4 (dest, *value32p); + break; + default: + if (nr_bytes == 2) + dv_store_2 (dest, 0); + else + dv_store_4 (dest, 0); + break; + } + + return nr_bytes; +} + +static void +bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic) +{ + bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0); + bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4); + bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8); +} + +static unsigned +bfin_sic_54x_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: Discard all SIC writes for now. */ + switch (mmr_off) + { + case mmr_offset(swrst): + /* XXX: This should trigger a software reset ... */ + break; + case mmr_offset(syscr): + /* XXX: what to do ... */ + break; + case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2): + bfin_sic_54x_forward_interrupts (me, sic); + *value32p = value; + break; + case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11): + case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2): + *value32p = value; + break; + case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2): + /* ISR is read-only. */ + break; + default: + /* XXX: Should discard other writes. */ + ; + } + + return nr_bytes; +} + +static unsigned +bfin_sic_54x_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(swrst): + case mmr_offset(syscr): + case mmr_offset(rvect): + dv_store_2 (dest, *value16p); + break; + case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2): + case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11): + case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2): + case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2): + dv_store_4 (dest, *value32p); + break; + default: + if (nr_bytes == 2) + dv_store_2 (dest, 0); + else + dv_store_4 (dest, 0); + break; + } + + return nr_bytes; +} + +static void +bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic) +{ + bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0); + bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4); +} + +static unsigned +bfin_sic_561_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + /* XXX: Discard all SIC writes for now. */ + switch (mmr_off) + { + case mmr_offset(swrst): + /* XXX: This should trigger a software reset ... */ + break; + case mmr_offset(syscr): + /* XXX: what to do ... */ + break; + case mmr_offset(bf561.imask0): + case mmr_offset(bf561.imask1): + bfin_sic_561_forward_interrupts (me, sic); + *value32p = value; + break; + case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3): + case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7): + case mmr_offset(bf561.iwr0): + case mmr_offset(bf561.iwr1): + *value32p = value; + break; + case mmr_offset(bf561.isr0): + case mmr_offset(bf561.isr1): + /* ISR is read-only. */ + break; + default: + /* XXX: Should discard other writes. */ + ; + } + + return nr_bytes; +} + +static unsigned +bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_sic *sic = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - sic->base; + valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(swrst): + case mmr_offset(syscr): + case mmr_offset(rvect): + dv_store_2 (dest, *value16p); + break; + case mmr_offset(bf561.imask0): + case mmr_offset(bf561.imask1): + case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3): + case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7): + case mmr_offset(bf561.iwr0): + case mmr_offset(bf561.iwr1): + case mmr_offset(bf561.isr0): + case mmr_offset(bf561.isr1): + dv_store_4 (dest, *value32p); + break; + default: + if (nr_bytes == 2) + dv_store_2 (dest, 0); + else + dv_store_4 (dest, 0); + break; + } + + return nr_bytes; +} + +/* XXX: This doesn't handle DMA<->peripheral mappings. */ +#define BFIN_SIC_TO_CEC_PORTS \ + { "ivg7", IVG7, 0, output_port, }, \ + { "ivg8", IVG8, 0, output_port, }, \ + { "ivg9", IVG9, 0, output_port, }, \ + { "ivg10", IVG10, 0, output_port, }, \ + { "ivg11", IVG11, 0, output_port, }, \ + { "ivg12", IVG12, 0, output_port, }, \ + { "ivg13", IVG13, 0, output_port, }, \ + { "ivg14", IVG14, 0, output_port, }, \ + { "ivg15", IVG15, 0, output_port, }, + +/* Give each SIC its own base to make it easier to extract the pin at + runtime. The pin is used as its bit position in the SIC MMRs. */ +#define ENC(sic, pin) (((sic) << 8) + (pin)) +#define DEC_PIN(pin) ((pin) % 0x100) +#define DEC_SIC(pin) ((pin) >> 8) + +static const struct hw_port_descriptor bfin_sic_50x_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "ppi@0", ENC(0, 2), 0, input_port, }, + { "sport@0_stat", ENC(0, 3), 0, input_port, }, + { "sport@1_stat", ENC(0, 4), 0, input_port, }, + { "uart2@0_stat", ENC(0, 5), 0, input_port, }, + { "uart2@1_stat", ENC(0, 6), 0, input_port, }, + { "spi@0", ENC(0, 7), 0, input_port, }, + { "spi@1", ENC(0, 8), 0, input_port, }, + { "can_stat", ENC(0, 9), 0, input_port, }, + { "rsi_int0", ENC(0, 10), 0, input_port, }, +/*{ "reserved", ENC(0, 11), 0, input_port, },*/ + { "counter@0", ENC(0, 12), 0, input_port, }, + { "counter@1", ENC(0, 13), 0, input_port, }, + { "dma@0", ENC(0, 14), 0, input_port, }, + { "dma@1", ENC(0, 15), 0, input_port, }, + { "dma@2", ENC(0, 16), 0, input_port, }, + { "dma@3", ENC(0, 17), 0, input_port, }, + { "dma@4", ENC(0, 18), 0, input_port, }, + { "dma@5", ENC(0, 19), 0, input_port, }, + { "dma@6", ENC(0, 20), 0, input_port, }, + { "dma@7", ENC(0, 21), 0, input_port, }, + { "dma@8", ENC(0, 22), 0, input_port, }, + { "dma@9", ENC(0, 23), 0, input_port, }, + { "dma@10", ENC(0, 24), 0, input_port, }, + { "dma@11", ENC(0, 25), 0, input_port, }, + { "can_rx", ENC(0, 26), 0, input_port, }, + { "can_tx", ENC(0, 27), 0, input_port, }, + { "twi@0", ENC(0, 28), 0, input_port, }, + { "portf_irq_a", ENC(0, 29), 0, input_port, }, + { "portf_irq_b", ENC(0, 30), 0, input_port, }, +/*{ "reserved", ENC(0, 31), 0, input_port, },*/ + /* SIC1 */ + { "gptimer@0", ENC(1, 0), 0, input_port, }, + { "gptimer@1", ENC(1, 1), 0, input_port, }, + { "gptimer@2", ENC(1, 2), 0, input_port, }, + { "gptimer@3", ENC(1, 3), 0, input_port, }, + { "gptimer@4", ENC(1, 4), 0, input_port, }, + { "gptimer@5", ENC(1, 5), 0, input_port, }, + { "gptimer@6", ENC(1, 6), 0, input_port, }, + { "gptimer@7", ENC(1, 7), 0, input_port, }, + { "portg_irq_a", ENC(1, 8), 0, input_port, }, + { "portg_irq_b", ENC(1, 9), 0, input_port, }, + { "mdma@0", ENC(1, 10), 0, input_port, }, + { "mdma@1", ENC(1, 11), 0, input_port, }, + { "wdog", ENC(1, 12), 0, input_port, }, + { "porth_irq_a", ENC(1, 13), 0, input_port, }, + { "porth_irq_b", ENC(1, 14), 0, input_port, }, + { "acm_stat", ENC(1, 15), 0, input_port, }, + { "acm_int", ENC(1, 16), 0, input_port, }, +/*{ "reserved", ENC(1, 17), 0, input_port, },*/ +/*{ "reserved", ENC(1, 18), 0, input_port, },*/ + { "pwm@0_trip", ENC(1, 19), 0, input_port, }, + { "pwm@0_sync", ENC(1, 20), 0, input_port, }, + { "pwm@1_trip", ENC(1, 21), 0, input_port, }, + { "pwm@1_sync", ENC(1, 22), 0, input_port, }, + { "rsi_int1", ENC(1, 23), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const struct hw_port_descriptor bfin_sic_51x_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "dmar0_block", ENC(0, 2), 0, input_port, }, + { "dmar1_block", ENC(0, 3), 0, input_port, }, + { "dmar0_over", ENC(0, 4), 0, input_port, }, + { "dmar1_over", ENC(0, 5), 0, input_port, }, + { "ppi@0", ENC(0, 6), 0, input_port, }, + { "emac_stat", ENC(0, 7), 0, input_port, }, + { "sport@0_stat", ENC(0, 8), 0, input_port, }, + { "sport@1_stat", ENC(0, 9), 0, input_port, }, + { "ptp_err", ENC(0, 10), 0, input_port, }, +/*{ "reserved", ENC(0, 11), 0, input_port, },*/ + { "uart@0_stat", ENC(0, 12), 0, input_port, }, + { "uart@1_stat", ENC(0, 13), 0, input_port, }, + { "rtc", ENC(0, 14), 0, input_port, }, + { "dma@0", ENC(0, 15), 0, input_port, }, + { "dma@3", ENC(0, 16), 0, input_port, }, + { "dma@4", ENC(0, 17), 0, input_port, }, + { "dma@5", ENC(0, 18), 0, input_port, }, + { "dma@6", ENC(0, 19), 0, input_port, }, + { "twi@0", ENC(0, 20), 0, input_port, }, + { "dma@7", ENC(0, 21), 0, input_port, }, + { "dma@8", ENC(0, 22), 0, input_port, }, + { "dma@9", ENC(0, 23), 0, input_port, }, + { "dma@10", ENC(0, 24), 0, input_port, }, + { "dma@11", ENC(0, 25), 0, input_port, }, + { "otp", ENC(0, 26), 0, input_port, }, + { "counter", ENC(0, 27), 0, input_port, }, + { "dma@1", ENC(0, 28), 0, input_port, }, + { "porth_irq_a", ENC(0, 29), 0, input_port, }, + { "dma@2", ENC(0, 30), 0, input_port, }, + { "porth_irq_b", ENC(0, 31), 0, input_port, }, + /* SIC1 */ + { "gptimer@0", ENC(1, 0), 0, input_port, }, + { "gptimer@1", ENC(1, 1), 0, input_port, }, + { "gptimer@2", ENC(1, 2), 0, input_port, }, + { "gptimer@3", ENC(1, 3), 0, input_port, }, + { "gptimer@4", ENC(1, 4), 0, input_port, }, + { "gptimer@5", ENC(1, 5), 0, input_port, }, + { "gptimer@6", ENC(1, 6), 0, input_port, }, + { "gptimer@7", ENC(1, 7), 0, input_port, }, + { "portg_irq_a", ENC(1, 8), 0, input_port, }, + { "portg_irq_b", ENC(1, 9), 0, input_port, }, + { "mdma@0", ENC(1, 10), 0, input_port, }, + { "mdma@1", ENC(1, 11), 0, input_port, }, + { "wdog", ENC(1, 12), 0, input_port, }, + { "portf_irq_a", ENC(1, 13), 0, input_port, }, + { "portf_irq_b", ENC(1, 14), 0, input_port, }, + { "spi@0", ENC(1, 15), 0, input_port, }, + { "spi@1", ENC(1, 16), 0, input_port, }, +/*{ "reserved", ENC(1, 17), 0, input_port, },*/ +/*{ "reserved", ENC(1, 18), 0, input_port, },*/ + { "rsi_int0", ENC(1, 19), 0, input_port, }, + { "rsi_int1", ENC(1, 20), 0, input_port, }, + { "pwm_trip", ENC(1, 21), 0, input_port, }, + { "pwm_sync", ENC(1, 22), 0, input_port, }, + { "ptp_stat", ENC(1, 23), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const struct hw_port_descriptor bfin_sic_52x_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "dmar0_block", ENC(0, 2), 0, input_port, }, + { "dmar1_block", ENC(0, 3), 0, input_port, }, + { "dmar0_over", ENC(0, 4), 0, input_port, }, + { "dmar1_over", ENC(0, 5), 0, input_port, }, + { "ppi@0", ENC(0, 6), 0, input_port, }, + { "emac_stat", ENC(0, 7), 0, input_port, }, + { "sport@0_stat", ENC(0, 8), 0, input_port, }, + { "sport@1_stat", ENC(0, 9), 0, input_port, }, +/*{ "reserved", ENC(0, 10), 0, input_port, },*/ +/*{ "reserved", ENC(0, 11), 0, input_port, },*/ + { "uart@0_stat", ENC(0, 12), 0, input_port, }, + { "uart@1_stat", ENC(0, 13), 0, input_port, }, + { "rtc", ENC(0, 14), 0, input_port, }, + { "dma@0", ENC(0, 15), 0, input_port, }, + { "dma@3", ENC(0, 16), 0, input_port, }, + { "dma@4", ENC(0, 17), 0, input_port, }, + { "dma@5", ENC(0, 18), 0, input_port, }, + { "dma@6", ENC(0, 19), 0, input_port, }, + { "twi@0", ENC(0, 20), 0, input_port, }, + { "dma@7", ENC(0, 21), 0, input_port, }, + { "dma@8", ENC(0, 22), 0, input_port, }, + { "dma@9", ENC(0, 23), 0, input_port, }, + { "dma@10", ENC(0, 24), 0, input_port, }, + { "dma@11", ENC(0, 25), 0, input_port, }, + { "otp", ENC(0, 26), 0, input_port, }, + { "counter", ENC(0, 27), 0, input_port, }, + { "dma@1", ENC(0, 28), 0, input_port, }, + { "porth_irq_a", ENC(0, 29), 0, input_port, }, + { "dma@2", ENC(0, 30), 0, input_port, }, + { "porth_irq_b", ENC(0, 31), 0, input_port, }, + /* SIC1 */ + { "gptimer@0", ENC(1, 0), 0, input_port, }, + { "gptimer@1", ENC(1, 1), 0, input_port, }, + { "gptimer@2", ENC(1, 2), 0, input_port, }, + { "gptimer@3", ENC(1, 3), 0, input_port, }, + { "gptimer@4", ENC(1, 4), 0, input_port, }, + { "gptimer@5", ENC(1, 5), 0, input_port, }, + { "gptimer@6", ENC(1, 6), 0, input_port, }, + { "gptimer@7", ENC(1, 7), 0, input_port, }, + { "portg_irq_a", ENC(1, 8), 0, input_port, }, + { "portg_irq_b", ENC(1, 9), 0, input_port, }, + { "mdma@0", ENC(1, 10), 0, input_port, }, + { "mdma@1", ENC(1, 11), 0, input_port, }, + { "wdog", ENC(1, 12), 0, input_port, }, + { "portf_irq_a", ENC(1, 13), 0, input_port, }, + { "portf_irq_b", ENC(1, 14), 0, input_port, }, + { "spi@0", ENC(1, 15), 0, input_port, }, + { "nfc_stat", ENC(1, 16), 0, input_port, }, + { "hostdp_stat", ENC(1, 17), 0, input_port, }, + { "hostdp_done", ENC(1, 18), 0, input_port, }, + { "usb_int0", ENC(1, 20), 0, input_port, }, + { "usb_int1", ENC(1, 21), 0, input_port, }, + { "usb_int2", ENC(1, 22), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_sic *sic = hw_data (me); + bu32 idx = DEC_SIC (my_port); + bu32 pin = DEC_PIN (my_port); + bu32 bit = 1 << pin; + + HW_TRACE ((me, "processing system int from %i (SIC %u pin %u)", + my_port, idx, pin)); + + /* SIC only exists to forward interrupts from the system to the CEC. */ + switch (idx) + { + case 0: sic->bf52x.isr0 |= bit; break; + case 1: sic->bf52x.isr1 |= bit; break; + } + + /* XXX: Handle SIC wakeup source ? + if (sic->bf52x.iwr0 & bit) + What to do ?; + if (sic->bf52x.iwr1 & bit) + What to do ?; + */ + + bfin_sic_52x_forward_interrupts (me, sic); +} + +static const struct hw_port_descriptor bfin_sic_533_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "ppi@0", ENC(0, 2), 0, input_port, }, + { "sport@0_stat", ENC(0, 3), 0, input_port, }, + { "sport@1_stat", ENC(0, 4), 0, input_port, }, + { "spi@0", ENC(0, 5), 0, input_port, }, + { "uart@0_stat", ENC(0, 6), 0, input_port, }, + { "rtc", ENC(0, 7), 0, input_port, }, + { "dma@0", ENC(0, 8), 0, input_port, }, + { "dma@1", ENC(0, 9), 0, input_port, }, + { "dma@2", ENC(0, 10), 0, input_port, }, + { "dma@3", ENC(0, 11), 0, input_port, }, + { "dma@4", ENC(0, 12), 0, input_port, }, + { "dma@5", ENC(0, 13), 0, input_port, }, + { "dma@6", ENC(0, 14), 0, input_port, }, + { "dma@7", ENC(0, 15), 0, input_port, }, + { "gptimer@0", ENC(0, 16), 0, input_port, }, + { "gptimer@1", ENC(0, 17), 0, input_port, }, + { "gptimer@2", ENC(0, 18), 0, input_port, }, + { "portf_irq_a", ENC(0, 19), 0, input_port, }, + { "portf_irq_b", ENC(0, 20), 0, input_port, }, + { "mdma@0", ENC(0, 21), 0, input_port, }, + { "mdma@1", ENC(0, 22), 0, input_port, }, + { "wdog", ENC(0, 23), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +/* The encoding here is uglier due to multiple sources being muxed into + the same interrupt line. So give each pin an arbitrary "SIC" so that + the resulting id is unique across all ports. */ +static const struct hw_port_descriptor bfin_sic_537_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "dmar0_block", ENC(1, 1), 0, input_port, }, + { "dmar1_block", ENC(2, 1), 0, input_port, }, + { "dmar0_over", ENC(3, 1), 0, input_port, }, + { "dmar1_over", ENC(4, 1), 0, input_port, }, + { "can_stat", ENC(0, 2), 0, input_port, }, + { "emac_stat", ENC(1, 2), 0, input_port, }, + { "sport@0_stat", ENC(2, 2), 0, input_port, }, + { "sport@1_stat", ENC(3, 2), 0, input_port, }, + { "ppi@0", ENC(4, 2), 0, input_port, }, + { "spi@0", ENC(5, 2), 0, input_port, }, + { "uart@0_stat", ENC(6, 2), 0, input_port, }, + { "uart@1_stat", ENC(7, 2), 0, input_port, }, + { "rtc", ENC(0, 3), 0, input_port, }, + { "dma@0", ENC(0, 4), 0, input_port, }, + { "dma@3", ENC(0, 5), 0, input_port, }, + { "dma@4", ENC(0, 6), 0, input_port, }, + { "dma@5", ENC(0, 7), 0, input_port, }, + { "dma@6", ENC(0, 8), 0, input_port, }, + { "twi@0", ENC(0, 9), 0, input_port, }, + { "dma@7", ENC(0, 10), 0, input_port, }, + { "dma@8", ENC(0, 11), 0, input_port, }, + { "dma@9", ENC(0, 12), 0, input_port, }, + { "dma@10", ENC(0, 13), 0, input_port, }, + { "dma@11", ENC(0, 14), 0, input_port, }, + { "can_rx", ENC(0, 15), 0, input_port, }, + { "can_tx", ENC(0, 16), 0, input_port, }, + { "dma@1", ENC(0, 17), 0, input_port, }, + { "porth_irq_a", ENC(1, 17), 0, input_port, }, + { "dma@2", ENC(0, 18), 0, input_port, }, + { "porth_irq_b", ENC(1, 18), 0, input_port, }, + { "gptimer@0", ENC(0, 19), 0, input_port, }, + { "gptimer@1", ENC(0, 20), 0, input_port, }, + { "gptimer@2", ENC(0, 21), 0, input_port, }, + { "gptimer@3", ENC(0, 22), 0, input_port, }, + { "gptimer@4", ENC(0, 23), 0, input_port, }, + { "gptimer@5", ENC(0, 24), 0, input_port, }, + { "gptimer@6", ENC(0, 25), 0, input_port, }, + { "gptimer@7", ENC(0, 26), 0, input_port, }, + { "portf_irq_a", ENC(0, 27), 0, input_port, }, + { "portg_irq_a", ENC(1, 27), 0, input_port, }, + { "portg_irq_b", ENC(0, 28), 0, input_port, }, + { "mdma@0", ENC(0, 29), 0, input_port, }, + { "mdma@1", ENC(0, 30), 0, input_port, }, + { "wdog", ENC(0, 31), 0, input_port, }, + { "portf_irq_b", ENC(1, 31), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_sic *sic = hw_data (me); + bu32 idx = DEC_SIC (my_port); + bu32 pin = DEC_PIN (my_port); + bu32 bit = 1 << pin; + + HW_TRACE ((me, "processing system int from %i (SIC %u pin %u)", + my_port, idx, pin)); + + /* SIC only exists to forward interrupts from the system to the CEC. */ + sic->bf537.isr |= bit; + + /* XXX: Handle SIC wakeup source ? + if (sic->bf537.iwr & bit) + What to do ?; + */ + + bfin_sic_537_forward_interrupts (me, sic); +} + +static const struct hw_port_descriptor bfin_sic_538_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dmac@0_stat", ENC(0, 1), 0, input_port, }, + { "ppi@0", ENC(0, 2), 0, input_port, }, + { "sport@0_stat", ENC(0, 3), 0, input_port, }, + { "sport@1_stat", ENC(0, 4), 0, input_port, }, + { "spi@0", ENC(0, 5), 0, input_port, }, + { "uart@0_stat", ENC(0, 6), 0, input_port, }, + { "rtc", ENC(0, 7), 0, input_port, }, + { "dma@0", ENC(0, 8), 0, input_port, }, + { "dma@1", ENC(0, 9), 0, input_port, }, + { "dma@2", ENC(0, 10), 0, input_port, }, + { "dma@3", ENC(0, 11), 0, input_port, }, + { "dma@4", ENC(0, 12), 0, input_port, }, + { "dma@5", ENC(0, 13), 0, input_port, }, + { "dma@6", ENC(0, 14), 0, input_port, }, + { "dma@7", ENC(0, 15), 0, input_port, }, + { "gptimer@0", ENC(0, 16), 0, input_port, }, + { "gptimer@1", ENC(0, 17), 0, input_port, }, + { "gptimer@2", ENC(0, 18), 0, input_port, }, + { "portf_irq_a", ENC(0, 19), 0, input_port, }, + { "portf_irq_b", ENC(0, 20), 0, input_port, }, + { "mdma@0", ENC(0, 21), 0, input_port, }, + { "mdma@1", ENC(0, 22), 0, input_port, }, + { "wdog", ENC(0, 23), 0, input_port, }, + { "dmac@1_stat", ENC(0, 24), 0, input_port, }, + { "sport@2_stat", ENC(0, 25), 0, input_port, }, + { "sport@3_stat", ENC(0, 26), 0, input_port, }, +/*{ "reserved", ENC(0, 27), 0, input_port, },*/ + { "spi@1", ENC(0, 28), 0, input_port, }, + { "spi@2", ENC(0, 29), 0, input_port, }, + { "uart@1_stat", ENC(0, 30), 0, input_port, }, + { "uart@2_stat", ENC(0, 31), 0, input_port, }, + /* SIC1 */ + { "can_stat", ENC(1, 0), 0, input_port, }, + { "dma@8", ENC(1, 1), 0, input_port, }, + { "dma@9", ENC(1, 2), 0, input_port, }, + { "dma@10", ENC(1, 3), 0, input_port, }, + { "dma@11", ENC(1, 4), 0, input_port, }, + { "dma@12", ENC(1, 5), 0, input_port, }, + { "dma@13", ENC(1, 6), 0, input_port, }, + { "dma@14", ENC(1, 7), 0, input_port, }, + { "dma@15", ENC(1, 8), 0, input_port, }, + { "dma@16", ENC(1, 9), 0, input_port, }, + { "dma@17", ENC(1, 10), 0, input_port, }, + { "dma@18", ENC(1, 11), 0, input_port, }, + { "dma@19", ENC(1, 12), 0, input_port, }, + { "twi@0", ENC(1, 13), 0, input_port, }, + { "twi@1", ENC(1, 14), 0, input_port, }, + { "can_rx", ENC(1, 15), 0, input_port, }, + { "can_tx", ENC(1, 16), 0, input_port, }, + { "mdma@2", ENC(1, 17), 0, input_port, }, + { "mdma@3", ENC(1, 18), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static const struct hw_port_descriptor bfin_sic_54x_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dmac@0_stat", ENC(0, 1), 0, input_port, }, + { "eppi@0", ENC(0, 2), 0, input_port, }, + { "sport@0_stat", ENC(0, 3), 0, input_port, }, + { "sport@1_stat", ENC(0, 4), 0, input_port, }, + { "spi@0", ENC(0, 5), 0, input_port, }, + { "uart2@0_stat", ENC(0, 6), 0, input_port, }, + { "rtc", ENC(0, 7), 0, input_port, }, + { "dma@12", ENC(0, 8), 0, input_port, }, + { "dma@0", ENC(0, 9), 0, input_port, }, + { "dma@1", ENC(0, 10), 0, input_port, }, + { "dma@2", ENC(0, 11), 0, input_port, }, + { "dma@3", ENC(0, 12), 0, input_port, }, + { "dma@4", ENC(0, 13), 0, input_port, }, + { "dma@6", ENC(0, 14), 0, input_port, }, + { "dma@7", ENC(0, 15), 0, input_port, }, + { "gptimer@8", ENC(0, 16), 0, input_port, }, + { "gptimer@9", ENC(0, 17), 0, input_port, }, + { "gptimer@10", ENC(0, 18), 0, input_port, }, + { "pint@0", ENC(0, 19), 0, input_port, }, + { "pint@1", ENC(0, 20), 0, input_port, }, + { "mdma@0", ENC(0, 21), 0, input_port, }, + { "mdma@1", ENC(0, 22), 0, input_port, }, + { "wdog", ENC(0, 23), 0, input_port, }, + { "dmac@1_stat", ENC(0, 24), 0, input_port, }, + { "sport@2_stat", ENC(0, 25), 0, input_port, }, + { "sport@3_stat", ENC(0, 26), 0, input_port, }, + { "mxvr", ENC(0, 27), 0, input_port, }, + { "spi@1", ENC(0, 28), 0, input_port, }, + { "spi@2", ENC(0, 29), 0, input_port, }, + { "uart2@1_stat", ENC(0, 30), 0, input_port, }, + { "uart2@2_stat", ENC(0, 31), 0, input_port, }, + /* SIC1 */ + { "can@0_stat", ENC(1, 0), 0, input_port, }, + { "dma@18", ENC(1, 1), 0, input_port, }, + { "dma@19", ENC(1, 2), 0, input_port, }, + { "dma@20", ENC(1, 3), 0, input_port, }, + { "dma@21", ENC(1, 4), 0, input_port, }, + { "dma@13", ENC(1, 5), 0, input_port, }, + { "dma@14", ENC(1, 6), 0, input_port, }, + { "dma@5", ENC(1, 7), 0, input_port, }, + { "dma@23", ENC(1, 8), 0, input_port, }, + { "dma@8", ENC(1, 9), 0, input_port, }, + { "dma@9", ENC(1, 10), 0, input_port, }, + { "dma@10", ENC(1, 11), 0, input_port, }, + { "dma@11", ENC(1, 12), 0, input_port, }, + { "twi@0", ENC(1, 13), 0, input_port, }, + { "twi@1", ENC(1, 14), 0, input_port, }, + { "can@0_rx", ENC(1, 15), 0, input_port, }, + { "can@0_tx", ENC(1, 16), 0, input_port, }, + { "mdma@2", ENC(1, 17), 0, input_port, }, + { "mdma@3", ENC(1, 18), 0, input_port, }, + { "mxvr_stat", ENC(1, 19), 0, input_port, }, + { "mxvr_message", ENC(1, 20), 0, input_port, }, + { "mxvr_packet", ENC(1, 21), 0, input_port, }, + { "eppi@1", ENC(1, 22), 0, input_port, }, + { "eppi@2", ENC(1, 23), 0, input_port, }, + { "uart2@3_stat", ENC(1, 24), 0, input_port, }, + { "hostdp", ENC(1, 25), 0, input_port, }, +/*{ "reserved", ENC(1, 26), 0, input_port, },*/ + { "pixc_stat", ENC(1, 27), 0, input_port, }, + { "nfc", ENC(1, 28), 0, input_port, }, + { "atapi", ENC(1, 29), 0, input_port, }, + { "can@1_stat", ENC(1, 30), 0, input_port, }, + { "dmar", ENC(1, 31), 0, input_port, }, + /* SIC2 */ + { "dma@15", ENC(2, 0), 0, input_port, }, + { "dma@16", ENC(2, 1), 0, input_port, }, + { "dma@17", ENC(2, 2), 0, input_port, }, + { "dma@22", ENC(2, 3), 0, input_port, }, + { "counter", ENC(2, 4), 0, input_port, }, + { "key", ENC(2, 5), 0, input_port, }, + { "can@1_rx", ENC(2, 6), 0, input_port, }, + { "can@1_tx", ENC(2, 7), 0, input_port, }, + { "sdh_mask0", ENC(2, 8), 0, input_port, }, + { "sdh_mask1", ENC(2, 9), 0, input_port, }, +/*{ "reserved", ENC(2, 10), 0, input_port, },*/ + { "usb_int0", ENC(2, 11), 0, input_port, }, + { "usb_int1", ENC(2, 12), 0, input_port, }, + { "usb_int2", ENC(2, 13), 0, input_port, }, + { "usb_dma", ENC(2, 14), 0, input_port, }, + { "otpsec", ENC(2, 15), 0, input_port, }, +/*{ "reserved", ENC(2, 16), 0, input_port, },*/ +/*{ "reserved", ENC(2, 17), 0, input_port, },*/ +/*{ "reserved", ENC(2, 18), 0, input_port, },*/ +/*{ "reserved", ENC(2, 19), 0, input_port, },*/ +/*{ "reserved", ENC(2, 20), 0, input_port, },*/ +/*{ "reserved", ENC(2, 21), 0, input_port, },*/ + { "gptimer@0", ENC(2, 22), 0, input_port, }, + { "gptimer@1", ENC(2, 23), 0, input_port, }, + { "gptimer@2", ENC(2, 24), 0, input_port, }, + { "gptimer@3", ENC(2, 25), 0, input_port, }, + { "gptimer@4", ENC(2, 26), 0, input_port, }, + { "gptimer@5", ENC(2, 27), 0, input_port, }, + { "gptimer@6", ENC(2, 28), 0, input_port, }, + { "gptimer@7", ENC(2, 29), 0, input_port, }, + { "pint2", ENC(2, 30), 0, input_port, }, + { "pint3", ENC(2, 31), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_sic *sic = hw_data (me); + bu32 idx = DEC_SIC (my_port); + bu32 pin = DEC_PIN (my_port); + bu32 bit = 1 << pin; + + HW_TRACE ((me, "processing system int from %i (SIC %u pin %u)", + my_port, idx, pin)); + + /* SIC only exists to forward interrupts from the system to the CEC. */ + switch (idx) + { + case 0: sic->bf54x.isr0 |= bit; break; + case 1: sic->bf54x.isr1 |= bit; break; + case 2: sic->bf54x.isr2 |= bit; break; + } + + /* XXX: Handle SIC wakeup source ? + if (sic->bf54x.iwr0 & bit) + What to do ?; + if (sic->bf54x.iwr1 & bit) + What to do ?; + if (sic->bf54x.iwr2 & bit) + What to do ?; + */ + + bfin_sic_54x_forward_interrupts (me, sic); +} + +static const struct hw_port_descriptor bfin_sic_561_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + /* SIC0 */ + { "pll", ENC(0, 0), 0, input_port, }, + { "dmac@0_stat", ENC(0, 1), 0, input_port, }, + { "dmac@1_stat", ENC(0, 2), 0, input_port, }, + { "imdma_stat", ENC(0, 3), 0, input_port, }, + { "ppi@0", ENC(0, 4), 0, input_port, }, + { "ppi@1", ENC(0, 5), 0, input_port, }, + { "sport@0_stat", ENC(0, 6), 0, input_port, }, + { "sport@1_stat", ENC(0, 7), 0, input_port, }, + { "spi@0", ENC(0, 8), 0, input_port, }, + { "uart@0_stat", ENC(0, 9), 0, input_port, }, +/*{ "reserved", ENC(0, 10), 0, input_port, },*/ + { "dma@12", ENC(0, 11), 0, input_port, }, + { "dma@13", ENC(0, 12), 0, input_port, }, + { "dma@14", ENC(0, 13), 0, input_port, }, + { "dma@15", ENC(0, 14), 0, input_port, }, + { "dma@16", ENC(0, 15), 0, input_port, }, + { "dma@17", ENC(0, 16), 0, input_port, }, + { "dma@18", ENC(0, 17), 0, input_port, }, + { "dma@19", ENC(0, 18), 0, input_port, }, + { "dma@20", ENC(0, 19), 0, input_port, }, + { "dma@21", ENC(0, 20), 0, input_port, }, + { "dma@22", ENC(0, 21), 0, input_port, }, + { "dma@23", ENC(0, 22), 0, input_port, }, + { "dma@0", ENC(0, 23), 0, input_port, }, + { "dma@1", ENC(0, 24), 0, input_port, }, + { "dma@2", ENC(0, 25), 0, input_port, }, + { "dma@3", ENC(0, 26), 0, input_port, }, + { "dma@4", ENC(0, 27), 0, input_port, }, + { "dma@5", ENC(0, 28), 0, input_port, }, + { "dma@6", ENC(0, 29), 0, input_port, }, + { "dma@7", ENC(0, 30), 0, input_port, }, + { "dma@8", ENC(0, 31), 0, input_port, }, + /* SIC1 */ + { "dma@9", ENC(1, 0), 0, input_port, }, + { "dma@10", ENC(1, 1), 0, input_port, }, + { "dma@11", ENC(1, 2), 0, input_port, }, + { "gptimer@0", ENC(1, 3), 0, input_port, }, + { "gptimer@1", ENC(1, 4), 0, input_port, }, + { "gptimer@2", ENC(1, 5), 0, input_port, }, + { "gptimer@3", ENC(1, 6), 0, input_port, }, + { "gptimer@4", ENC(1, 7), 0, input_port, }, + { "gptimer@5", ENC(1, 8), 0, input_port, }, + { "gptimer@6", ENC(1, 9), 0, input_port, }, + { "gptimer@7", ENC(1, 10), 0, input_port, }, + { "gptimer@8", ENC(1, 11), 0, input_port, }, + { "gptimer@9", ENC(1, 12), 0, input_port, }, + { "gptimer@10", ENC(1, 13), 0, input_port, }, + { "gptimer@11", ENC(1, 14), 0, input_port, }, + { "portf_irq_a", ENC(1, 15), 0, input_port, }, + { "portf_irq_b", ENC(1, 16), 0, input_port, }, + { "portg_irq_a", ENC(1, 17), 0, input_port, }, + { "portg_irq_b", ENC(1, 18), 0, input_port, }, + { "porth_irq_a", ENC(1, 19), 0, input_port, }, + { "porth_irq_b", ENC(1, 20), 0, input_port, }, + { "mdma@0", ENC(1, 21), 0, input_port, }, + { "mdma@1", ENC(1, 22), 0, input_port, }, + { "mdma@2", ENC(1, 23), 0, input_port, }, + { "mdma@3", ENC(1, 24), 0, input_port, }, + { "imdma@0", ENC(1, 25), 0, input_port, }, + { "imdma@1", ENC(1, 26), 0, input_port, }, + { "wdog", ENC(1, 27), 0, input_port, }, +/*{ "reserved", ENC(1, 28), 0, input_port, },*/ +/*{ "reserved", ENC(1, 29), 0, input_port, },*/ + { "sup_irq_0", ENC(1, 30), 0, input_port, }, + { "sup_irq_1", ENC(1, 31), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_sic *sic = hw_data (me); + bu32 idx = DEC_SIC (my_port); + bu32 pin = DEC_PIN (my_port); + bu32 bit = 1 << pin; + + HW_TRACE ((me, "processing system int from %i (SIC %u pin %u)", + my_port, idx, pin)); + + /* SIC only exists to forward interrupts from the system to the CEC. */ + switch (idx) + { + case 0: sic->bf561.isr0 |= bit; break; + case 1: sic->bf561.isr1 |= bit; break; + } + + /* XXX: Handle SIC wakeup source ? + if (sic->bf561.iwr0 & bit) + What to do ?; + if (sic->bf561.iwr1 & bit) + What to do ?; + */ + + bfin_sic_561_forward_interrupts (me, sic); +} + +static const struct hw_port_descriptor bfin_sic_59x_ports[] = +{ + BFIN_SIC_TO_CEC_PORTS + { "pll", ENC(0, 0), 0, input_port, }, + { "dma_stat", ENC(0, 1), 0, input_port, }, + { "ppi@0", ENC(0, 2), 0, input_port, }, + { "sport@0_stat", ENC(0, 3), 0, input_port, }, + { "sport@1_stat", ENC(0, 4), 0, input_port, }, + { "spi@0", ENC(0, 5), 0, input_port, }, + { "spi@1", ENC(0, 6), 0, input_port, }, + { "uart@0_stat", ENC(0, 7), 0, input_port, }, + { "dma@0", ENC(0, 8), 0, input_port, }, + { "dma@1", ENC(0, 9), 0, input_port, }, + { "dma@2", ENC(0, 10), 0, input_port, }, + { "dma@3", ENC(0, 11), 0, input_port, }, + { "dma@4", ENC(0, 12), 0, input_port, }, + { "dma@5", ENC(0, 13), 0, input_port, }, + { "dma@6", ENC(0, 14), 0, input_port, }, + { "dma@7", ENC(0, 15), 0, input_port, }, + { "dma@8", ENC(0, 16), 0, input_port, }, + { "portf_irq_a", ENC(0, 17), 0, input_port, }, + { "portf_irq_b", ENC(0, 18), 0, input_port, }, + { "gptimer@0", ENC(0, 19), 0, input_port, }, + { "gptimer@1", ENC(0, 20), 0, input_port, }, + { "gptimer@2", ENC(0, 21), 0, input_port, }, + { "portg_irq_a", ENC(0, 22), 0, input_port, }, + { "portg_irq_b", ENC(0, 23), 0, input_port, }, + { "twi@0", ENC(0, 24), 0, input_port, }, +/* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */ + { "dma@9", ENC(0, 25), 0, input_port, }, + { "dma@10", ENC(0, 26), 0, input_port, }, + { "dma@11", ENC(0, 27), 0, input_port, }, + { "dma@12", ENC(0, 28), 0, input_port, }, +/*{ "reserved", ENC(0, 25), 0, input_port, },*/ +/*{ "reserved", ENC(0, 26), 0, input_port, },*/ +/*{ "reserved", ENC(0, 27), 0, input_port, },*/ +/*{ "reserved", ENC(0, 28), 0, input_port, },*/ + { "mdma@0", ENC(0, 29), 0, input_port, }, + { "mdma@1", ENC(0, 30), 0, input_port, }, + { "wdog", ENC(0, 31), 0, input_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_SIC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + sic->base = attach_address; +} + +static void +bfin_sic_finish (struct hw *me) +{ + struct bfin_sic *sic; + + sic = HW_ZALLOC (me, struct bfin_sic); + + set_hw_data (me, sic); + attach_bfin_sic_regs (me, sic); + + switch (hw_find_integer_property (me, "type")) + { + case 500 ... 509: + set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); + set_hw_ports (me, bfin_sic_50x_ports); + set_hw_port_event (me, bfin_sic_52x_port_event); + mmr_names = bf52x_mmr_names; + + /* Initialize the SIC. */ + sic->bf52x.imask0 = sic->bf52x.imask1 = 0; + sic->bf52x.isr0 = sic->bf52x.isr1 = 0; + sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; + sic->bf52x.iar0 = 0x00000000; + sic->bf52x.iar1 = 0x22111000; + sic->bf52x.iar2 = 0x33332222; + sic->bf52x.iar3 = 0x44444433; + sic->bf52x.iar4 = 0x55555555; + sic->bf52x.iar5 = 0x06666655; + sic->bf52x.iar6 = 0x33333003; + sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ + break; + case 510 ... 519: + set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); + set_hw_ports (me, bfin_sic_51x_ports); + set_hw_port_event (me, bfin_sic_52x_port_event); + mmr_names = bf52x_mmr_names; + + /* Initialize the SIC. */ + sic->bf52x.imask0 = sic->bf52x.imask1 = 0; + sic->bf52x.isr0 = sic->bf52x.isr1 = 0; + sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; + sic->bf52x.iar0 = 0x00000000; + sic->bf52x.iar1 = 0x11000000; + sic->bf52x.iar2 = 0x33332222; + sic->bf52x.iar3 = 0x44444433; + sic->bf52x.iar4 = 0x55555555; + sic->bf52x.iar5 = 0x06666655; + sic->bf52x.iar6 = 0x33333000; + sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ + break; + case 522 ... 527: + set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); + set_hw_ports (me, bfin_sic_52x_ports); + set_hw_port_event (me, bfin_sic_52x_port_event); + mmr_names = bf52x_mmr_names; + + /* Initialize the SIC. */ + sic->bf52x.imask0 = sic->bf52x.imask1 = 0; + sic->bf52x.isr0 = sic->bf52x.isr1 = 0; + sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; + sic->bf52x.iar0 = 0x00000000; + sic->bf52x.iar1 = 0x11000000; + sic->bf52x.iar2 = 0x33332222; + sic->bf52x.iar3 = 0x44444433; + sic->bf52x.iar4 = 0x55555555; + sic->bf52x.iar5 = 0x06666655; + sic->bf52x.iar6 = 0x33333000; + sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ + break; + case 531 ... 533: + set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); + set_hw_ports (me, bfin_sic_533_ports); + set_hw_port_event (me, bfin_sic_537_port_event); + mmr_names = bf537_mmr_names; + + /* Initialize the SIC. */ + sic->bf537.imask = 0; + sic->bf537.isr = 0; + sic->bf537.iwr = 0xFFFFFFFF; + sic->bf537.iar0 = 0x10000000; + sic->bf537.iar1 = 0x33322221; + sic->bf537.iar2 = 0x66655444; + sic->bf537.iar3 = 0; /* XXX: fix this */ + break; + case 534: + case 536: + case 537: + set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); + set_hw_ports (me, bfin_sic_537_ports); + set_hw_port_event (me, bfin_sic_537_port_event); + mmr_names = bf537_mmr_names; + + /* Initialize the SIC. */ + sic->bf537.imask = 0; + sic->bf537.isr = 0; + sic->bf537.iwr = 0xFFFFFFFF; + sic->bf537.iar0 = 0x22211000; + sic->bf537.iar1 = 0x43333332; + sic->bf537.iar2 = 0x55555444; + sic->bf537.iar3 = 0x66655555; + break; + case 538 ... 539: + set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer); + set_hw_ports (me, bfin_sic_538_ports); + set_hw_port_event (me, bfin_sic_52x_port_event); + mmr_names = bf52x_mmr_names; + + /* Initialize the SIC. */ + sic->bf52x.imask0 = sic->bf52x.imask1 = 0; + sic->bf52x.isr0 = sic->bf52x.isr1 = 0; + sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF; + sic->bf52x.iar0 = 0x10000000; + sic->bf52x.iar1 = 0x33322221; + sic->bf52x.iar2 = 0x66655444; + sic->bf52x.iar3 = 0x00000000; + sic->bf52x.iar4 = 0x32222220; + sic->bf52x.iar5 = 0x44433333; + sic->bf52x.iar6 = 0x00444664; + sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */ + break; + case 540 ... 549: + set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer); + set_hw_ports (me, bfin_sic_54x_ports); + set_hw_port_event (me, bfin_sic_54x_port_event); + mmr_names = bf54x_mmr_names; + + /* Initialize the SIC. */ + sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0; + sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0; + sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF; + sic->bf54x.iar0 = 0x10000000; + sic->bf54x.iar1 = 0x33322221; + sic->bf54x.iar2 = 0x66655444; + sic->bf54x.iar3 = 0x00000000; + sic->bf54x.iar4 = 0x32222220; + sic->bf54x.iar5 = 0x44433333; + sic->bf54x.iar6 = 0x00444664; + sic->bf54x.iar7 = 0x00000000; + sic->bf54x.iar8 = 0x44111111; + sic->bf54x.iar9 = 0x44444444; + sic->bf54x.iar10 = 0x44444444; + sic->bf54x.iar11 = 0x55444444; + break; + case 561: + set_hw_io_read_buffer (me, bfin_sic_561_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_561_io_write_buffer); + set_hw_ports (me, bfin_sic_561_ports); + set_hw_port_event (me, bfin_sic_561_port_event); + mmr_names = bf561_mmr_names; + + /* Initialize the SIC. */ + sic->bf561.imask0 = sic->bf561.imask1 = 0; + sic->bf561.isr0 = sic->bf561.isr1 = 0; + sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF; + sic->bf561.iar0 = 0x00000000; + sic->bf561.iar1 = 0x11111000; + sic->bf561.iar2 = 0x21111111; + sic->bf561.iar3 = 0x22222222; + sic->bf561.iar4 = 0x33333222; + sic->bf561.iar5 = 0x43333333; + sic->bf561.iar6 = 0x21144444; + sic->bf561.iar7 = 0x00006552; + break; + case 590 ... 599: + set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer); + set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer); + set_hw_ports (me, bfin_sic_59x_ports); + set_hw_port_event (me, bfin_sic_537_port_event); + mmr_names = bf537_mmr_names; + + /* Initialize the SIC. */ + sic->bf537.imask = 0; + sic->bf537.isr = 0; + sic->bf537.iwr = 0xFFFFFFFF; + sic->bf537.iar0 = 0x00000000; + sic->bf537.iar1 = 0x33322221; + sic->bf537.iar2 = 0x55444443; + sic->bf537.iar3 = 0x66600005; + break; + default: + hw_abort (me, "no support for SIC on this Blackfin model yet"); + } +} + +const struct hw_descriptor dv_bfin_sic_descriptor[] = +{ + {"bfin_sic", bfin_sic_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.h new file mode 100644 index 000000000000..e70a749c9bce --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_sic.h @@ -0,0 +1,27 @@ +/* Blackfin System Interrupt Controller (SIC) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_SIC_H +#define DV_BFIN_SIC_H + +#define BFIN_MMR_SIC_BASE 0xFFC00100 +#define BFIN_MMR_SIC_SIZE 0x100 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.c new file mode 100644 index 000000000000..63204ecd1820 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.c @@ -0,0 +1,232 @@ +/* Blackfin Serial Peripheral Interface (SPI) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_spi.h" + +/* XXX: This is merely a stub. */ + +struct bfin_spi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(ctl); + bu16 BFIN_MMR_16(flg); + bu16 BFIN_MMR_16(stat); + bu16 BFIN_MMR_16(tdbr); + bu16 BFIN_MMR_16(rdbr); + bu16 BFIN_MMR_16(baud); + bu16 BFIN_MMR_16(shadow); +}; +#define mmr_base() offsetof(struct bfin_spi, ctl) +#define mmr_offset(mmr) (offsetof(struct bfin_spi, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "SPI_CTL", "SPI_FLG", "SPI_STAT", "SPI_TDBR", + "SPI_RDBR", "SPI_BAUD", "SPI_SHADOW", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static bool +bfin_spi_enabled (struct bfin_spi *spi) +{ + return (spi->ctl & SPE); +} + +static bu16 +bfin_spi_timod (struct bfin_spi *spi) +{ + return (spi->ctl & TIMOD); +} + +static unsigned +bfin_spi_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_spi *spi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - spi->base; + valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(stat): + dv_w1c_2 (valuep, value, ~(SPIF | TXS | RXS)); + break; + case mmr_offset(tdbr): + *valuep = value; + if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == TDBR_CORE) + { + spi->stat |= RXS; + spi->stat &= ~TXS; + } + break; + case mmr_offset(rdbr): + case mmr_offset(ctl): + case mmr_offset(flg): + case mmr_offset(baud): + case mmr_offset(shadow): + *valuep = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_spi_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_spi *spi = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - spi->base; + valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(rdbr): + dv_store_2 (dest, *valuep); + if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == RDBR_CORE) + spi->stat &= ~(RXS | TXS); + break; + case mmr_offset(ctl): + case mmr_offset(stat): + case mmr_offset(flg): + case mmr_offset(tdbr): + case mmr_offset(baud): + case mmr_offset(shadow): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_spi_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_spi_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + HW_TRACE_DMA_WRITE (); + return 0; +} + +static const struct hw_port_descriptor bfin_spi_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_spi_regs (struct hw *me, struct bfin_spi *spi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_SPI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SPI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + spi->base = attach_address; +} + +static void +bfin_spi_finish (struct hw *me) +{ + struct bfin_spi *spi; + + spi = HW_ZALLOC (me, struct bfin_spi); + + set_hw_data (me, spi); + set_hw_io_read_buffer (me, bfin_spi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_spi_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_spi_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_spi_dma_write_buffer); + set_hw_ports (me, bfin_spi_ports); + + attach_bfin_spi_regs (me, spi); + + /* Initialize the SPI. */ + spi->ctl = 0x0400; + spi->flg = 0xFF00; + spi->stat = 0x0001; +} + +const struct hw_descriptor dv_bfin_spi_descriptor[] = +{ + {"bfin_spi", bfin_spi_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.h new file mode 100644 index 000000000000..5e216bf04140 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_spi.h @@ -0,0 +1,54 @@ +/* Blackfin Serial Peripheral Interface (SPI) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_SPI_H +#define DV_BFIN_SPI_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_SPI_SIZE (4 * 7) + +/* SPI_CTL Masks. */ +#define TIMOD (3 << 0) +#define RDBR_CORE (0 << 0) +#define TDBR_CORE (1 << 0) +#define RDBR_DMA (2 << 0) +#define TDBR_DMA (3 << 0) +#define SZ (1 << 2) +#define GM (1 << 3) +#define PSSE (1 << 4) +#define EMISO (1 << 5) +#define SZE (1 << 8) +#define LSBF (1 << 9) +#define CPHA (1 << 10) +#define CPOL (1 << 11) +#define MSTR (1 << 12) +#define WOM (1 << 13) +#define SPE (1 << 14) + +/* SPI_STAT Masks. */ +#define SPIF (1 << 0) +#define MODF (1 << 1) +#define TXE (1 << 2) +#define TXS (1 << 3) +#define RBSY (1 << 4) +#define RXS (1 << 5) +#define TXCOL (1 << 6) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.c new file mode 100644 index 000000000000..beb7742744a2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.c @@ -0,0 +1,287 @@ +/* Blackfin Trace (TBUF) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_trace.h" + +/* Note: The circular buffering here might look a little buggy wrt mid-reads + and consuming the top entry, but this is simulating hardware behavior. + The hardware is simple, dumb, and fast. Don't write dumb Blackfin + software and you won't have a problem. */ + +/* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */ +#ifndef SIM_BFIN_TRACE_DEPTH +#define SIM_BFIN_TRACE_DEPTH 6 +#endif +#define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH) +#define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1) + +struct bfin_trace_entry +{ + bu32 src, dst; +}; +struct bfin_trace +{ + bu32 base; + struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN]; + int top, bottom; + bool mid; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 tbufctl, tbufstat; + char _pad[0x100 - 0x8]; + bu32 tbuf; +}; +#define mmr_base() offsetof(struct bfin_trace, tbufctl) +#define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +/* Ugh, circular buffers. */ +#define TBUF_LEN(t) ((t)->top - (t)->bottom) +#define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK) +/* TOP is the next slot to fill. */ +#define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)]) +/* LAST is the latest valid slot. */ +#define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)]) +/* LAST_LAST is the second-to-last valid slot. */ +#define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)]) + +static unsigned +bfin_trace_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_trace *trace = hw_data (me); + bu32 mmr_off; + bu32 value; + + value = dv_load_4 (source); + mmr_off = addr - trace->base; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(tbufctl): + trace->tbufctl = value; + break; + case mmr_offset(tbufstat): + case mmr_offset(tbuf): + /* Discard writes to these. */ + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_trace_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_trace *trace = hw_data (me); + bu32 mmr_off; + bu32 value; + + mmr_off = addr - trace->base; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(tbufctl): + value = trace->tbufctl; + break; + case mmr_offset(tbufstat): + /* Hardware is limited to 16 entries, so to stay compatible with + software, limit the value to 16. For software algorithms that + keep reading while (TBUFSTAT != 0), they'll get all of it. */ + value = MIN (TBUF_LEN (trace), 16); + break; + case mmr_offset(tbuf): + { + struct bfin_trace_entry *e; + + if (TBUF_LEN (trace) == 0) + { + value = 0; + break; + } + + e = TBUF_LAST (trace); + if (trace->mid) + { + value = e->src; + --trace->top; + } + else + value = e->dst; + trace->mid = !trace->mid; + + break; + } + default: + while (1) /* Core MMRs -> exception -> doesn't return. */ + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + dv_store_4 (dest, value); + + return nr_bytes; +} + +static void +attach_bfin_trace_regs (struct hw *me, struct bfin_trace *trace) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_TRACE_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + trace->base = attach_address; +} + +static void +bfin_trace_finish (struct hw *me) +{ + struct bfin_trace *trace; + + trace = HW_ZALLOC (me, struct bfin_trace); + + set_hw_data (me, trace); + set_hw_io_read_buffer (me, bfin_trace_io_read_buffer); + set_hw_io_write_buffer (me, bfin_trace_io_write_buffer); + + attach_bfin_trace_regs (me, trace); +} + +const struct hw_descriptor dv_bfin_trace_descriptor[] = +{ + {"bfin_trace", bfin_trace_finish,}, + {NULL, NULL}, +}; + +#define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace) + +/* This is not re-entrant, but neither is the cpu state, so this shouldn't + be a big deal ... */ +void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop) +{ + struct bfin_trace *trace = TRACE_STATE (cpu); + struct bfin_trace_entry *e; + int len, ivg; + + /* Only queue if powered. */ + if (!(trace->tbufctl & TBUFPWR)) + return; + + /* Only queue if enabled. */ + if (!(trace->tbufctl & TBUFEN)) + return; + + /* Ignore hardware loops. + XXX: This is what the hardware does, but an option to ignore + could be useful for debugging ... */ + if (hwloop >= 0) + return; + + /* Only queue if at right level. */ + ivg = cec_get_ivg (cpu); + if (ivg == IVG_RST) + /* XXX: This is what the hardware does, but an option to ignore + could be useful for debugging ... */ + return; + if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF)) + /* XXX: This is what the hardware does, but an option to ignore + could be useful for debugging ... just don't throw an + exception when full and in EVT{0..3}. */ + return; + + /* Are we full ? */ + len = TBUF_LEN (trace); + if (len == SIM_BFIN_TRACE_LEN) + { + if (trace->tbufctl & TBUFOVF) + { + cec_exception (cpu, VEC_OVFLOW); + return; + } + + /* Overwrite next entry. */ + ++trace->bottom; + } + + /* One level compression. */ + if (len >= 1 && (trace->tbufctl & TBUFCMPLP)) + { + e = TBUF_LAST (trace); + if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) + { + /* Hardware sets LSB when level is compressed. */ + e->dst |= 1; + return; + } + } + + /* Two level compression. */ + if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE)) + { + e = TBUF_LAST_LAST (trace); + if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) + { + /* Hardware sets LSB when level is compressed. */ + e->src |= 1; + return; + } + } + + e = TBUF_TOP (trace); + e->dst = dst_pc; + e->src = src_pc; + ++trace->top; +} diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.h new file mode 100644 index 000000000000..3acfddf037b3 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_trace.h @@ -0,0 +1,37 @@ +/* Blackfin Trace (TBUF) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_TRACE_H +#define DV_BFIN_TRACE_H + +#define BFIN_COREMMR_TRACE_BASE 0xFFE06000 +#define BFIN_COREMMR_TRACE_SIZE (4 * 65) + +/* TBUFCTL Masks */ +#define TBUFPWR 0x0001 +#define TBUFEN 0x0002 +#define TBUFOVF 0x0004 +#define TBUFCMPLP_SINGLE 0x0008 +#define TBUFCMPLP_DOUBLE 0x0010 +#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE) + +void bfin_trace_queue (SIM_CPU *, bu32 src_pc, bu32 dst_pc, int hwloop); + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.c new file mode 100644 index 000000000000..5d04f2336857 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.c @@ -0,0 +1,230 @@ +/* Blackfin Two Wire Interface (TWI) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_twi.h" + +/* XXX: This is merely a stub. */ + +struct bfin_twi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + bu16 xmt_fifo, rcv_fifo; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(clkdiv); + bu16 BFIN_MMR_16(control); + bu16 BFIN_MMR_16(slave_ctl); + bu16 BFIN_MMR_16(slave_stat); + bu16 BFIN_MMR_16(slave_addr); + bu16 BFIN_MMR_16(master_ctl); + bu16 BFIN_MMR_16(master_stat); + bu16 BFIN_MMR_16(master_addr); + bu16 BFIN_MMR_16(int_stat); + bu16 BFIN_MMR_16(int_mask); + bu16 BFIN_MMR_16(fifo_ctl); + bu16 BFIN_MMR_16(fifo_stat); + bu32 _pad0[20]; + bu16 BFIN_MMR_16(xmt_data8); + bu16 BFIN_MMR_16(xmt_data16); + bu16 BFIN_MMR_16(rcv_data8); + bu16 BFIN_MMR_16(rcv_data16); +}; +#define mmr_base() offsetof(struct bfin_twi, clkdiv) +#define mmr_offset(mmr) (offsetof(struct bfin_twi, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[] = +{ + "TWI_CLKDIV", "TWI_CONTROL", "TWI_SLAVE_CTL", "TWI_SLAVE_STAT", + "TWI_SLAVE_ADDR", "TWI_MASTER_CTL", "TWI_MASTER_STAT", "TWI_MASTER_ADDR", + "TWI_INT_STAT", "TWI_INT_MASK", "TWI_FIFO_CTL", "TWI_FIFO_STAT", + [mmr_idx (xmt_data8)] = "TWI_XMT_DATA8", "TWI_XMT_DATA16", "TWI_RCV_DATA8", + "TWI_RCV_DATA16", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static unsigned +bfin_twi_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_twi *twi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - twi->base; + valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(clkdiv): + case mmr_offset(control): + case mmr_offset(slave_ctl): + case mmr_offset(slave_addr): + case mmr_offset(master_ctl): + case mmr_offset(master_addr): + case mmr_offset(int_mask): + case mmr_offset(fifo_ctl): + *valuep = value; + break; + case mmr_offset(int_stat): + dv_w1c_2 (valuep, value, -1); + break; + case mmr_offset(master_stat): + dv_w1c_2 (valuep, value, BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB); + break; + case mmr_offset(slave_stat): + case mmr_offset(fifo_stat): + case mmr_offset(rcv_data8): + case mmr_offset(rcv_data16): + /* These are all RO. XXX: Does these throw error ? */ + break; + case mmr_offset(xmt_data8): + value &= 0xff; + case mmr_offset(xmt_data16): + twi->xmt_fifo = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_twi_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_twi *twi = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - twi->base; + valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(clkdiv): + case mmr_offset(control): + case mmr_offset(slave_ctl): + case mmr_offset(slave_stat): + case mmr_offset(slave_addr): + case mmr_offset(master_ctl): + case mmr_offset(master_stat): + case mmr_offset(master_addr): + case mmr_offset(int_stat): + case mmr_offset(int_mask): + case mmr_offset(fifo_ctl): + case mmr_offset(fifo_stat): + dv_store_2 (dest, *valuep); + break; + case mmr_offset(rcv_data8): + case mmr_offset(rcv_data16): + dv_store_2 (dest, twi->rcv_fifo); + break; + case mmr_offset(xmt_data8): + case mmr_offset(xmt_data16): + /* These always read as 0. */ + dv_store_2 (dest, 0); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_twi_ports[] = +{ + { "stat", 0, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_twi_regs (struct hw *me, struct bfin_twi *twi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_TWI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_TWI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + twi->base = attach_address; +} + +static void +bfin_twi_finish (struct hw *me) +{ + struct bfin_twi *twi; + + twi = HW_ZALLOC (me, struct bfin_twi); + + set_hw_data (me, twi); + set_hw_io_read_buffer (me, bfin_twi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_twi_io_write_buffer); + set_hw_ports (me, bfin_twi_ports); + + attach_bfin_twi_regs (me, twi); +} + +const struct hw_descriptor dv_bfin_twi_descriptor[] = +{ + {"bfin_twi", bfin_twi_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.h new file mode 100644 index 000000000000..a31df786579c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_twi.h @@ -0,0 +1,38 @@ +/* Blackfin Two Wire Interface (TWI) model + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_TWI_H +#define DV_BFIN_TWI_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_TWI_SIZE 0x90 + +/* TWI_MASTER_STAT Masks */ +#define MPROG (1 << 0) +#define LOSTARB (1 << 1) +#define ANAK (1 << 2) +#define DNAK (1 << 3) +#define BUFRDERR (1 << 4) +#define BUFWRERR (1 << 5) +#define SDASEN (1 << 6) +#define SCLSEN (1 << 7) +#define BUSBUSY (1 << 8) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.c new file mode 100644 index 000000000000..f05ee1597f7d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.c @@ -0,0 +1,440 @@ +/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + For "old style" UARTs on BF53x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "dv-sockser.h" +#include "devices.h" +#include "dv-bfin_uart.h" + +/* XXX: Should we bother emulating the TX/RX FIFOs ? */ + +/* Internal state needs to be the same as bfin_uart2. */ +struct bfin_uart +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* This is aliased to DLH. */ + bu16 ier; + /* These are aliased to DLL. */ + bu16 thr, rbr; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(dll); + bu16 BFIN_MMR_16(dlh); + bu16 BFIN_MMR_16(iir); + bu16 BFIN_MMR_16(lcr); + bu16 BFIN_MMR_16(mcr); + bu16 BFIN_MMR_16(lsr); + bu16 BFIN_MMR_16(msr); + bu16 BFIN_MMR_16(scr); + bu16 _pad0[2]; + bu16 BFIN_MMR_16(gctl); +}; +#define mmr_base() offsetof(struct bfin_uart, dll) +#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "UART_RBR/UART_THR", "UART_IER", "UART_IIR", "UART_LCR", "UART_MCR", + "UART_LSR", "UART_MSR", "UART_SCR", "", "UART_GCTL", +}; +static const char *mmr_name (struct bfin_uart *uart, bu32 idx) +{ + if (uart->lcr & DLAB) + if (idx < 2) + return idx == 0 ? "UART_DLL" : "UART_DLH"; + return mmr_names[idx]; +} +#define mmr_name(off) mmr_name (uart, (off) / 4) + +#ifndef HAVE_DV_SOCKSER +# define dv_sockser_status(sd) -1 +# define dv_sockser_write(sd, byte) do { ; } while (0) +# define dv_sockser_read(sd) 0xff +#endif + +static void +bfin_uart_poll (struct hw *me, void *data) +{ + struct bfin_uart *uart = data; + bu16 lsr; + + uart->handler = NULL; + + lsr = bfin_uart_get_status (me); + if (lsr & DR) + hw_port_event (me, DV_PORT_RX, 1); + + bfin_uart_reschedule (me); +} + +void +bfin_uart_reschedule (struct hw *me) +{ + struct bfin_uart *uart = hw_data (me); + + if (uart->ier & ERBFI) + { + if (!uart->handler) + uart->handler = hw_event_queue_schedule (me, 10000, + bfin_uart_poll, uart); + } + else + { + if (uart->handler) + { + hw_event_queue_deschedule (me, uart->handler); + uart->handler = NULL; + } + } +} + +bu16 +bfin_uart_write_byte (struct hw *me, bu16 thr) +{ + unsigned char ch = thr; + bfin_uart_write_buffer (me, &ch, 1); + return thr; +} + +static unsigned +bfin_uart_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_uart *uart = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - uart->base; + valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */ + switch (mmr_off) + { + case mmr_offset(dll): + if (uart->lcr & DLAB) + uart->dll = value; + else + { + uart->thr = bfin_uart_write_byte (me, value); + + if (uart->ier & ETBEI) + hw_port_event (me, DV_PORT_TX, 1); + } + break; + case mmr_offset(dlh): + if (uart->lcr & DLAB) + uart->dlh = value; + else + { + uart->ier = value; + bfin_uart_reschedule (me); + } + break; + case mmr_offset(iir): + case mmr_offset(lsr): + /* XXX: Writes are ignored ? */ + break; + case mmr_offset(lcr): + case mmr_offset(mcr): + case mmr_offset(scr): + case mmr_offset(gctl): + *valuep = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +/* Switch between socket and stdin on the fly. */ +bu16 +bfin_uart_get_next_byte (struct hw *me, bu16 rbr, bool *fresh) +{ + SIM_DESC sd = hw_system (me); + struct bfin_uart *uart = hw_data (me); + int status = dv_sockser_status (sd); + bool _fresh; + + /* NB: The "uart" here may only use interal state. */ + + if (!fresh) + fresh = &_fresh; + + *fresh = false; + if (status & DV_SOCKSER_DISCONNECTED) + { + if (uart->saved_count > 0) + { + *fresh = true; + rbr = uart->saved_byte; + --uart->saved_count; + } + else + { + char byte; + int ret = sim_io_poll_read (sd, 0/*STDIN*/, &byte, 1); + if (ret > 0) + { + *fresh = true; + rbr = byte; + } + } + } + else + rbr = dv_sockser_read (sd); + + return rbr; +} + +bu16 +bfin_uart_get_status (struct hw *me) +{ + SIM_DESC sd = hw_system (me); + struct bfin_uart *uart = hw_data (me); + int status = dv_sockser_status (sd); + bu16 lsr = 0; + + if (status & DV_SOCKSER_DISCONNECTED) + { + if (uart->saved_count <= 0) + uart->saved_count = sim_io_poll_read (sd, 0/*STDIN*/, + &uart->saved_byte, 1); + lsr |= TEMT | THRE | (uart->saved_count > 0 ? DR : 0); + } + else + lsr |= (status & DV_SOCKSER_INPUT_EMPTY ? 0 : DR) | + (status & DV_SOCKSER_OUTPUT_EMPTY ? TEMT | THRE : 0); + + return lsr; +} + +static unsigned +bfin_uart_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_uart *uart = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - uart->base; + valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(dll): + if (uart->lcr & DLAB) + dv_store_2 (dest, uart->dll); + else + { + uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL); + dv_store_2 (dest, uart->rbr); + } + break; + case mmr_offset(dlh): + if (uart->lcr & DLAB) + dv_store_2 (dest, uart->dlh); + else + dv_store_2 (dest, uart->ier); + break; + case mmr_offset(lsr): + /* XXX: Reads are destructive on most parts, but not all ... */ + uart->lsr |= bfin_uart_get_status (me); + dv_store_2 (dest, *valuep); + uart->lsr = 0; + break; + case mmr_offset(iir): + /* XXX: Reads are destructive ... */ + case mmr_offset(lcr): + case mmr_offset(mcr): + case mmr_offset(scr): + case mmr_offset(gctl): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +unsigned +bfin_uart_read_buffer (struct hw *me, unsigned char *buffer, unsigned nr_bytes) +{ + SIM_DESC sd = hw_system (me); + struct bfin_uart *uart = hw_data (me); + int status = dv_sockser_status (sd); + unsigned i = 0; + + if (status & DV_SOCKSER_DISCONNECTED) + { + int ret; + + while (uart->saved_count > 0 && i < nr_bytes) + { + buffer[i++] = uart->saved_byte; + --uart->saved_count; + } + + ret = sim_io_poll_read (sd, 0/*STDIN*/, (char *) buffer, nr_bytes - i); + if (ret > 0) + i += ret; + } + else + buffer[i++] = dv_sockser_read (sd); + + return i; +} + +static unsigned +bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return bfin_uart_read_buffer (me, dest, nr_bytes); +} + +unsigned +bfin_uart_write_buffer (struct hw *me, const unsigned char *buffer, + unsigned nr_bytes) +{ + SIM_DESC sd = hw_system (me); + int status = dv_sockser_status (sd); + + if (status & DV_SOCKSER_DISCONNECTED) + { + sim_io_write_stdout (sd, (const char *) buffer, nr_bytes); + sim_io_flush_stdout (sd); + } + else + { + /* Normalize errors to a value of 0. */ + int ret = dv_sockser_write_buffer (sd, buffer, nr_bytes); + nr_bytes = CLAMP (ret, 0, nr_bytes); + } + + return nr_bytes; +} + +static unsigned +bfin_uart_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_uart *uart = hw_data (me); + unsigned ret; + + HW_TRACE_DMA_WRITE (); + + ret = bfin_uart_write_buffer (me, source, nr_bytes); + + if (ret == nr_bytes && (uart->ier & ETBEI)) + hw_port_event (me, DV_PORT_TX, 1); + + return ret; +} + +static const struct hw_port_descriptor bfin_uart_ports[] = +{ + { "tx", DV_PORT_TX, 0, output_port, }, + { "rx", DV_PORT_RX, 0, output_port, }, + { "stat", DV_PORT_STAT, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_UART_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + uart->base = attach_address; +} + +static void +bfin_uart_finish (struct hw *me) +{ + struct bfin_uart *uart; + + uart = HW_ZALLOC (me, struct bfin_uart); + + set_hw_data (me, uart); + set_hw_io_read_buffer (me, bfin_uart_io_read_buffer); + set_hw_io_write_buffer (me, bfin_uart_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer); + set_hw_ports (me, bfin_uart_ports); + + attach_bfin_uart_regs (me, uart); + + /* Initialize the UART. */ + uart->dll = 0x0001; + uart->iir = 0x0001; + uart->lsr = 0x0060; +} + +const struct hw_descriptor dv_bfin_uart_descriptor[] = +{ + {"bfin_uart", bfin_uart_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.h new file mode 100644 index 000000000000..ccb7af461373 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart.h @@ -0,0 +1,54 @@ +/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + For "old style" UARTs on BF53x/etc... parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_UART_H +#define DV_BFIN_UART_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_UART_SIZE 0x30 + +struct bfin_uart; +bu16 bfin_uart_get_next_byte (struct hw *, bu16, bool *fresh); +bu16 bfin_uart_write_byte (struct hw *, bu16); +bu16 bfin_uart_get_status (struct hw *); +unsigned bfin_uart_write_buffer (struct hw *, const unsigned char *, unsigned); +unsigned bfin_uart_read_buffer (struct hw *, unsigned char *, unsigned); +void bfin_uart_reschedule (struct hw *); + +/* UART_LCR */ +#define DLAB (1 << 7) + +/* UART_LSR */ +#define TFI (1 << 7) +#define TEMT (1 << 6) +#define THRE (1 << 5) +#define BI (1 << 4) +#define FE (1 << 3) +#define PE (1 << 2) +#define OE (1 << 1) +#define DR (1 << 0) + +/* UART_IER */ +#define ERBFI (1 << 0) +#define ETBEI (1 << 1) +#define ELSI (1 << 2) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.c new file mode 100644 index 000000000000..facde1c6cd24 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.c @@ -0,0 +1,261 @@ +/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + For "new style" UARTs on BF50x/BF54x parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_uart2.h" + +/* XXX: Should we bother emulating the TX/RX FIFOs ? */ + +/* Internal state needs to be the same as bfin_uart. */ +struct bfin_uart +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Accessed indirectly by ier_{set,clear}. */ + bu16 ier; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(dll); + bu16 BFIN_MMR_16(dlh); + bu16 BFIN_MMR_16(gctl); + bu16 BFIN_MMR_16(lcr); + bu16 BFIN_MMR_16(mcr); + bu16 BFIN_MMR_16(lsr); + bu16 BFIN_MMR_16(msr); + bu16 BFIN_MMR_16(scr); + bu16 BFIN_MMR_16(ier_set); + bu16 BFIN_MMR_16(ier_clear); + bu16 BFIN_MMR_16(thr); + bu16 BFIN_MMR_16(rbr); +}; +#define mmr_base() offsetof(struct bfin_uart, dll) +#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "UART_DLL", "UART_DLH", "UART_GCTL", "UART_LCR", "UART_MCR", "UART_LSR", + "UART_MSR", "UART_SCR", "UART_IER_SET", "UART_IER_CLEAR", "UART_THR", + "UART_RBR", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_uart_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_uart *uart = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - uart->base; + valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */ + + switch (mmr_off) + { + case mmr_offset(thr): + uart->thr = bfin_uart_write_byte (me, value); + if (uart->ier & ETBEI) + hw_port_event (me, DV_PORT_TX, 1); + break; + case mmr_offset(ier_set): + uart->ier |= value; + break; + case mmr_offset(ier_clear): + dv_w1c_2 (&uart->ier, value, -1); + break; + case mmr_offset(lsr): + dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE); + break; + case mmr_offset(rbr): + /* XXX: Writes are ignored ? */ + break; + case mmr_offset(msr): + dv_w1c_2 (valuep, value, SCTS); + break; + case mmr_offset(dll): + case mmr_offset(dlh): + case mmr_offset(gctl): + case mmr_offset(lcr): + case mmr_offset(mcr): + case mmr_offset(scr): + *valuep = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_uart_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_uart *uart = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - uart->base; + valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(rbr): + uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL); + dv_store_2 (dest, uart->rbr); + break; + case mmr_offset(ier_set): + case mmr_offset(ier_clear): + dv_store_2 (dest, uart->ier); + bfin_uart_reschedule (me); + break; + case mmr_offset(lsr): + uart->lsr |= bfin_uart_get_status (me); + case mmr_offset(thr): + case mmr_offset(msr): + case mmr_offset(dll): + case mmr_offset(dlh): + case mmr_offset(gctl): + case mmr_offset(lcr): + case mmr_offset(mcr): + case mmr_offset(scr): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return bfin_uart_read_buffer (me, dest, nr_bytes); +} + +static unsigned +bfin_uart_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_uart *uart = hw_data (me); + unsigned ret; + + HW_TRACE_DMA_WRITE (); + + ret = bfin_uart_write_buffer (me, source, nr_bytes); + + if (ret == nr_bytes && (uart->ier & ETBEI)) + hw_port_event (me, DV_PORT_TX, 1); + + return ret; +} + +static const struct hw_port_descriptor bfin_uart_ports[] = +{ + { "tx", DV_PORT_TX, 0, output_port, }, + { "rx", DV_PORT_RX, 0, output_port, }, + { "stat", DV_PORT_STAT, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_UART2_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART2_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + uart->base = attach_address; +} + +static void +bfin_uart_finish (struct hw *me) +{ + struct bfin_uart *uart; + + uart = HW_ZALLOC (me, struct bfin_uart); + + set_hw_data (me, uart); + set_hw_io_read_buffer (me, bfin_uart_io_read_buffer); + set_hw_io_write_buffer (me, bfin_uart_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer); + set_hw_ports (me, bfin_uart_ports); + + attach_bfin_uart_regs (me, uart); + + /* Initialize the UART. */ + uart->dll = 0x0001; + uart->lsr = 0x0060; +} + +const struct hw_descriptor dv_bfin_uart2_descriptor[] = +{ + {"bfin_uart2", bfin_uart_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.h new file mode 100644 index 000000000000..f8269a404c55 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_uart2.h @@ -0,0 +1,33 @@ +/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model. + For "new style" UARTs on BF50x/BF54x parts. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_UART2_H +#define DV_BFIN_UART2_H + +#include "dv-bfin_uart.h" + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_UART2_SIZE 0x30 + +/* UART_MSR */ +#define SCTS (1 << 0) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.c new file mode 100644 index 000000000000..fcda6c95fc4e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.c @@ -0,0 +1,209 @@ +/* Blackfin Watchdog (WDOG) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "dv-sockser.h" +#include "devices.h" +#include "dv-bfin_wdog.h" + +/* XXX: Should we bother emulating the TX/RX FIFOs ? */ + +struct bfin_wdog +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(ctl); + bu32 cnt, stat; +}; +#define mmr_base() offsetof(struct bfin_wdog, ctl) +#define mmr_offset(mmr) (offsetof(struct bfin_wdog, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "WDOG_CTL", "WDOG_CNT", "WDOG_STAT", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static bool +bfin_wdog_enabled (struct bfin_wdog *wdog) +{ + return ((wdog->ctl & WDEN) != WDDIS); +} + +static unsigned +bfin_wdog_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_wdog *wdog = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - wdog->base; + valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(ctl): + dv_w1c_2_partial (value16p, value, WDRO); + /* XXX: Should enable an event here to handle timeouts. */ + break; + + case mmr_offset(cnt): + /* Writes are discarded when enabeld. */ + if (!bfin_wdog_enabled (wdog)) + { + *value32p = value; + /* Writes to CNT preloads the STAT. */ + wdog->stat = wdog->cnt; + } + break; + + case mmr_offset(stat): + /* When enabled, writes to STAT reload the counter. */ + if (bfin_wdog_enabled (wdog)) + wdog->stat = wdog->cnt; + /* XXX: When disabled, are writes just ignored ? */ + break; + } + + return nr_bytes; +} + +static unsigned +bfin_wdog_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_wdog *wdog = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - wdog->base; + valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(ctl): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + dv_store_2 (dest, *value16p); + break; + + case mmr_offset(cnt): + case mmr_offset(stat): + dv_store_4 (dest, *value32p); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_wdog_ports[] = +{ + { "reset", WDEV_RESET, 0, output_port, }, + { "nmi", WDEV_NMI, 0, output_port, }, + { "gpi", WDEV_GPI, 0, output_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_wdog_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_wdog *wdog = hw_data (me); + bu16 wdev; + + wdog->ctl |= WDRO; + wdev = (wdog->ctl & WDEV); + if (wdev != WDEV_NONE) + hw_port_event (me, wdev, 1); +} + +static void +attach_bfin_wdog_regs (struct hw *me, struct bfin_wdog *wdog) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_WDOG_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_WDOG_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + wdog->base = attach_address; +} + +static void +bfin_wdog_finish (struct hw *me) +{ + struct bfin_wdog *wdog; + + wdog = HW_ZALLOC (me, struct bfin_wdog); + + set_hw_data (me, wdog); + set_hw_io_read_buffer (me, bfin_wdog_io_read_buffer); + set_hw_io_write_buffer (me, bfin_wdog_io_write_buffer); + set_hw_ports (me, bfin_wdog_ports); + set_hw_port_event (me, bfin_wdog_port_event); + + attach_bfin_wdog_regs (me, wdog); + + /* Initialize the Watchdog. */ + wdog->ctl = WDDIS; +} + +const struct hw_descriptor dv_bfin_wdog_descriptor[] = +{ + {"bfin_wdog", bfin_wdog_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.h new file mode 100644 index 000000000000..9be602dbd3ba --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wdog.h @@ -0,0 +1,36 @@ +/* Blackfin Watchdog (WDOG) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_WDOG_H +#define DV_BFIN_WDOG_H + +#define BFIN_MMR_WDOG_SIZE (4 * 3) + +/* WDOG_CTL */ +#define WDEV 0x0006 /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.c b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.c new file mode 100644 index 000000000000..9f35ac698b0b --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.c @@ -0,0 +1,190 @@ +/* Blackfin Watchpoint (WP) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_wp.h" + +/* XXX: This is mostly a stub. */ + +#define WPI_NUM 6 /* 6 instruction watchpoints. */ +#define WPD_NUM 2 /* 2 data watchpoints. */ + +struct bfin_wp +{ + bu32 base; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 iactl; + bu32 _pad0[15]; + bu32 ia[WPI_NUM]; + bu32 _pad1[16 - WPI_NUM]; + bu32 iacnt[WPI_NUM]; + bu32 _pad2[32 - WPI_NUM]; + + bu32 dactl; + bu32 _pad3[15]; + bu32 da[WPD_NUM]; + bu32 _pad4[16 - WPD_NUM]; + bu32 dacnt[WPD_NUM]; + bu32 _pad5[32 - WPD_NUM]; + + bu32 stat; +}; +#define mmr_base() offsetof(struct bfin_wp, iactl) +#define mmr_offset(mmr) (offsetof(struct bfin_wp, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[] = +{ + [mmr_idx (iactl)] = "WPIACTL", + [mmr_idx (ia)] = "WPIA0", "WPIA1", "WPIA2", "WPIA3", "WPIA4", "WPIA5", + [mmr_idx (iacnt)] = "WPIACNT0", "WPIACNT1", "WPIACNT2", + "WPIACNT3", "WPIACNT4", "WPIACNT5", + [mmr_idx (dactl)] = "WPDACTL", + [mmr_idx (da)] = "WPDA0", "WPDA1", "WPDA2", "WPDA3", "WPDA4", "WPDA5", + [mmr_idx (dacnt)] = "WPDACNT0", "WPDACNT1", "WPDACNT2", + "WPDACNT3", "WPDACNT4", "WPDACNT5", + [mmr_idx (stat)] = "WPSTAT", +}; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "") + +static unsigned +bfin_wp_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_wp *wp = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + value = dv_load_4 (source); + mmr_off = addr - wp->base; + valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(iactl): + case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): + case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): + case mmr_offset(dactl): + case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): + case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): + *valuep = value; + break; + case mmr_offset(stat): + /* Yes, the hardware is this dumb -- clear all bits on any write. */ + *valuep = 0; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_wp_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_wp *wp = hw_data (me); + bu32 mmr_off; + bu32 value; + bu32 *valuep; + + mmr_off = addr - wp->base; + valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(iactl): + case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): + case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): + case mmr_offset(dactl): + case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): + case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): + case mmr_offset(stat): + value = *valuep; + break; + default: + while (1) /* Core MMRs -> exception -> doesn't return. */ + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + dv_store_4 (dest, value); + + return nr_bytes; +} + +static void +attach_bfin_wp_regs (struct hw *me, struct bfin_wp *wp) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_COREMMR_WP_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_WP_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + wp->base = attach_address; +} + +static void +bfin_wp_finish (struct hw *me) +{ + struct bfin_wp *wp; + + wp = HW_ZALLOC (me, struct bfin_wp); + + set_hw_data (me, wp); + set_hw_io_read_buffer (me, bfin_wp_io_read_buffer); + set_hw_io_write_buffer (me, bfin_wp_io_write_buffer); + + attach_bfin_wp_regs (me, wp); +} + +const struct hw_descriptor dv_bfin_wp_descriptor[] = +{ + {"bfin_wp", bfin_wp_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.h b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.h new file mode 100644 index 000000000000..f6c0d80df57b --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-bfin_wp.h @@ -0,0 +1,27 @@ +/* Blackfin Watchpoint (WP) model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_BFIN_WP_H +#define DV_BFIN_WP_H + +#define BFIN_COREMMR_WP_BASE 0xFFE07000 +#define BFIN_COREMMR_WP_SIZE 0x204 + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/dv-eth_phy.c b/external/gpl3/gdb/dist/sim/bfin/dv-eth_phy.c new file mode 100644 index 000000000000..56aad6f4f1ba --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/dv-eth_phy.c @@ -0,0 +1,208 @@ +/* Ethernet Physical Receiver model. + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" + +#ifdef HAVE_LINUX_MII_H + +/* Workaround old/broken linux headers. */ +#define _LINUX_TYPES_H +#define __u16 unsigned short +#include + +#define REG_PHY_SIZE 0x20 + +struct eth_phy +{ + bu32 base; + bu16 regs[REG_PHY_SIZE]; +}; +#define reg_base() offsetof(struct eth_phy, regs[0]) +#define reg_offset(reg) (offsetof(struct eth_phy, reg) - reg_base()) +#define reg_idx(reg) (reg_offset (reg) / 4) + +static const char * const reg_names[] = +{ + [MII_BMCR ] = "MII_BMCR", + [MII_BMSR ] = "MII_BMSR", + [MII_PHYSID1 ] = "MII_PHYSID1", + [MII_PHYSID2 ] = "MII_PHYSID2", + [MII_ADVERTISE ] = "MII_ADVERTISE", + [MII_LPA ] = "MII_LPA", + [MII_EXPANSION ] = "MII_EXPANSION", +#ifdef MII_CTRL1000 + [MII_CTRL1000 ] = "MII_CTRL1000", +#endif +#ifdef MII_STAT1000 + [MII_STAT1000 ] = "MII_STAT1000", +#endif +#ifdef MII_ESTATUS + [MII_ESTATUS ] = "MII_ESTATUS", +#endif + [MII_DCOUNTER ] = "MII_DCOUNTER", + [MII_FCSCOUNTER ] = "MII_FCSCOUNTER", + [MII_NWAYTEST ] = "MII_NWAYTEST", + [MII_RERRCOUNTER] = "MII_RERRCOUNTER", + [MII_SREVISION ] = "MII_SREVISION", + [MII_RESV1 ] = "MII_RESV1", + [MII_LBRERROR ] = "MII_LBRERROR", + [MII_PHYADDR ] = "MII_PHYADDR", + [MII_RESV2 ] = "MII_RESV2", + [MII_TPISTATUS ] = "MII_TPISTATUS", + [MII_NCONFIG ] = "MII_NCONFIG", +}; +#define mmr_name(off) (reg_names[off] ? : "") +#define mmr_off reg_off + +static unsigned +eth_phy_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct eth_phy *phy = hw_data (me); + bu16 reg_off; + bu16 value; + bu16 *valuep; + + value = dv_load_2 (source); + + reg_off = addr - phy->base; + valuep = (void *)((unsigned long)phy + reg_base() + reg_off); + + HW_TRACE_WRITE (); + + switch (reg_off) + { + case MII_BMCR: + *valuep = value; + break; + case MII_PHYSID1: + case MII_PHYSID2: + /* Discard writes to these. */ + break; + default: + /* XXX: Discard writes to unknown regs ? */ + *valuep = value; + break; + } + + return nr_bytes; +} + +static unsigned +eth_phy_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct eth_phy *phy = hw_data (me); + bu16 reg_off; + bu16 *valuep; + + reg_off = addr - phy->base; + valuep = (void *)((unsigned long)phy + reg_base() + reg_off); + + HW_TRACE_READ (); + + switch (reg_off) + { + case MII_BMCR: + dv_store_2 (dest, *valuep); + break; + case MII_BMSR: + /* XXX: Let people control this ? */ + *valuep = BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | BMSR_10HALF | + BMSR_ANEGCOMPLETE | BMSR_ANEGCAPABLE | BMSR_LSTATUS; + dv_store_2 (dest, *valuep); + break; + case MII_LPA: + /* XXX: Let people control this ? */ + *valuep = LPA_100FULL | LPA_100HALF | LPA_10FULL | LPA_10HALF; + dv_store_2 (dest, *valuep); + break; + default: + dv_store_2 (dest, *valuep); + break; + } + + return nr_bytes; +} + +static void +attach_eth_phy_regs (struct hw *me, struct eth_phy *phy) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != REG_PHY_SIZE) + hw_abort (me, "\"reg\" size must be %#x", REG_PHY_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + phy->base = attach_address; +} + +static void +eth_phy_finish (struct hw *me) +{ + struct eth_phy *phy; + + phy = HW_ZALLOC (me, struct eth_phy); + + set_hw_data (me, phy); + set_hw_io_read_buffer (me, eth_phy_io_read_buffer); + set_hw_io_write_buffer (me, eth_phy_io_write_buffer); + + attach_eth_phy_regs (me, phy); + + /* Initialize the PHY. */ + phy->regs[MII_PHYSID1] = 0; /* Unassigned Vendor */ + phy->regs[MII_PHYSID2] = 0xAD; /* Product */ +} + +#else + +static void +eth_phy_finish (struct hw *me) +{ + HW_TRACE ((me, "No linux/mii.h support found")); +} + +#endif + +const struct hw_descriptor dv_eth_phy_descriptor[] = +{ + {"eth_phy", eth_phy_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/gui.c b/external/gpl3/gdb/dist/sim/bfin/gui.c new file mode 100644 index 000000000000..879bfd1960c7 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/gui.c @@ -0,0 +1,292 @@ +/* Blackfin GUI (SDL) helper code + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#ifdef HAVE_SDL +# include +#endif +#ifdef HAVE_DLFCN_H +# include +#endif + +#include "libiberty.h" +#include "gui.h" + +#ifdef HAVE_SDL + +static struct { + void *handle; + int (*Init) (Uint32 flags); + void (*Quit) (void); + SDL_Surface *(*SetVideoMode) (int width, int height, int bpp, Uint32 flags); + void (*WM_SetCaption) (const char *title, const char *icon); + int (*ShowCursor) (int toggle); + int (*LockSurface) (SDL_Surface *surface); + void (*UnlockSurface) (SDL_Surface *surface); + void (*GetRGB) (Uint32 pixel, const SDL_PixelFormat * const fmt, Uint8 *r, Uint8 *g, Uint8 *b); + Uint32 (*MapRGB) (const SDL_PixelFormat * const format, const Uint8 r, const Uint8 g, const Uint8 b); + void (*UpdateRect) (SDL_Surface *screen, Sint32 x, Sint32 y, Uint32 w, Uint32 h); +} sdl; + +static const char * const sdl_syms[] = +{ + "SDL_Init", + "SDL_Quit", + "SDL_SetVideoMode", + "SDL_WM_SetCaption", + "SDL_ShowCursor", + "SDL_LockSurface", + "SDL_UnlockSurface", + "SDL_GetRGB", + "SDL_MapRGB", + "SDL_UpdateRect", +}; + +struct gui_state { + SDL_Surface *screen; + const SDL_PixelFormat *format; + int throttle, throttle_limit; + enum gui_color color; + int curr_line; +}; + +/* Load the SDL lib on the fly to avoid hard linking against it. */ +static int +bfin_gui_sdl_setup (void) +{ + int i; + uintptr_t **funcs; + + if (sdl.handle) + return 0; + + sdl.handle = dlopen ("libSDL-1.2.so.0", RTLD_LAZY); + if (sdl.handle == NULL) + return -1; + + funcs = (void *) &sdl.Init; + for (i = 0; i < ARRAY_SIZE (sdl_syms); ++i) + { + funcs[i] = dlsym (sdl.handle, sdl_syms[i]); + if (funcs[i] == NULL) + { + dlclose (sdl.handle); + sdl.handle = NULL; + return -1; + } + } + + return 0; +} + +static const SDL_PixelFormat *bfin_gui_color_format (enum gui_color color); + +void * +bfin_gui_setup (void *state, int enabled, int width, int height, + enum gui_color color) +{ + if (bfin_gui_sdl_setup ()) + return NULL; + + /* Create an SDL window if enabled and we don't have one yet. */ + if (enabled && !state) + { + struct gui_state *gui = xmalloc (sizeof (*gui)); + if (!gui) + return NULL; + + if (sdl.Init (SDL_INIT_VIDEO)) + goto error; + + gui->color = color; + gui->format = bfin_gui_color_format (gui->color); + gui->screen = sdl.SetVideoMode (width, height, 32, + SDL_ANYFORMAT|SDL_HWSURFACE); + if (!gui->screen) + { + sdl.Quit(); + goto error; + } + + sdl.WM_SetCaption ("GDB Blackfin Simulator", NULL); + sdl.ShowCursor (0); + gui->curr_line = 0; + gui->throttle = 0; + gui->throttle_limit = 0xf; /* XXX: let people control this ? */ + return gui; + + error: + free (gui); + return NULL; + } + + /* Else break down a window if disabled and we had one. */ + else if (!enabled && state) + { + sdl.Quit(); + free (state); + return NULL; + } + + /* Retain existing state, whatever that may be. */ + return state; +} + +static int +SDL_ConvertBlitLineFrom (const Uint8 *src, const SDL_PixelFormat * const format, + SDL_Surface *dst, int dsty) +{ + Uint8 r, g, b; + Uint32 *pixels; + unsigned i, j; + + if (SDL_MUSTLOCK (dst)) + if (sdl.LockSurface (dst)) + return 1; + + pixels = dst->pixels; + pixels += (dsty * dst->pitch / 4); + + for (i = 0; i < dst->w; ++i) + { + /* Exract the packed source pixel; RGB or BGR. */ + Uint32 pix = 0; + for (j = 0; j < format->BytesPerPixel; ++j) + if (format->Rshift) + pix = (pix << 8) | src[j]; + else + pix = pix | ((Uint32)src[j] << (j * 8)); + + /* Unpack the source pixel into its components. */ + sdl.GetRGB (pix, format, &r, &g, &b); + /* Translate into the screen pixel format. */ + *pixels++ = sdl.MapRGB (dst->format, r, g, b); + + src += format->BytesPerPixel; + } + + if (SDL_MUSTLOCK (dst)) + sdl.UnlockSurface (dst); + + sdl.UpdateRect (dst, 0, dsty, dst->w, 1); + + return 0; +} + +unsigned +bfin_gui_update (void *state, const void *source, unsigned nr_bytes) +{ + struct gui_state *gui = state; + int ret; + + if (!gui) + return 0; + + /* XXX: Make this an option ? */ + gui->throttle = (gui->throttle + 1) & gui->throttle_limit; + if (gui->throttle) + return 0; + + ret = SDL_ConvertBlitLineFrom (source, gui->format, gui->screen, + gui->curr_line); + if (ret) + return 0; + + gui->curr_line = (gui->curr_line + 1) % gui->screen->h; + + return nr_bytes; +} + +#define FMASK(cnt, shift) (((1 << (cnt)) - 1) << (shift)) +#define _FORMAT(bpp, rcnt, gcnt, bcnt, acnt, rsh, gsh, bsh, ash) \ + NULL, bpp, (bpp)/8, 8-(rcnt), 8-(gcnt), 8-(bcnt), 8-(acnt), rsh, gsh, bsh, ash, \ + FMASK (rcnt, rsh), FMASK (gcnt, gsh), FMASK (bcnt, bsh), FMASK (acnt, ash), +#define FORMAT(rcnt, gcnt, bcnt, acnt, rsh, gsh, bsh, ash) \ + _FORMAT(((((rcnt) + (gcnt) + (bcnt) + (acnt)) + 7) / 8) * 8, \ + rcnt, gcnt, bcnt, acnt, rsh, gsh, bsh, ash) + +static const SDL_PixelFormat sdl_rgb_565 = +{ + FORMAT (5, 6, 5, 0, 11, 5, 0, 0) +}; +static const SDL_PixelFormat sdl_bgr_565 = +{ + FORMAT (5, 6, 5, 0, 0, 5, 11, 0) +}; +static const SDL_PixelFormat sdl_rgb_888 = +{ + FORMAT (8, 8, 8, 0, 16, 8, 0, 0) +}; +static const SDL_PixelFormat sdl_bgr_888 = +{ + FORMAT (8, 8, 8, 0, 0, 8, 16, 0) +}; +static const SDL_PixelFormat sdl_rgba_8888 = +{ + FORMAT (8, 8, 8, 8, 24, 16, 8, 0) +}; + +static const struct { + const char *name; + const SDL_PixelFormat *format; + enum gui_color color; +} color_spaces[] = { + { "rgb565", &sdl_rgb_565, GUI_COLOR_RGB_565, }, + { "bgr565", &sdl_bgr_565, GUI_COLOR_BGR_565, }, + { "rgb888", &sdl_rgb_888, GUI_COLOR_RGB_888, }, + { "bgr888", &sdl_bgr_888, GUI_COLOR_BGR_888, }, + { "rgba8888", &sdl_rgba_8888, GUI_COLOR_RGBA_8888, }, +}; + +enum gui_color bfin_gui_color (const char *color) +{ + int i; + + if (!color) + goto def; + + for (i = 0; i < ARRAY_SIZE (color_spaces); ++i) + if (!strcmp (color, color_spaces[i].name)) + return color_spaces[i].color; + + /* Pick a random default. */ + def: + return GUI_COLOR_RGB_888; +} + +static const SDL_PixelFormat *bfin_gui_color_format (enum gui_color color) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (color_spaces); ++i) + if (color == color_spaces[i].color) + return color_spaces[i].format; + + return NULL; +} + +int bfin_gui_color_depth (enum gui_color color) +{ + const SDL_PixelFormat *format = bfin_gui_color_format (color); + return format ? format->BitsPerPixel : 0; +} + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/gui.h b/external/gpl3/gdb/dist/sim/bfin/gui.h new file mode 100644 index 000000000000..3456ac903d27 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/gui.h @@ -0,0 +1,50 @@ +/* Blackfin GUI (SDL) helper code + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef BFIN_GUI_H +#define BFIN_GUI_H + +#ifdef HAVE_SDL + +enum gui_color { + GUI_COLOR_RGB_565, + GUI_COLOR_BGR_565, + GUI_COLOR_RGB_888, + GUI_COLOR_BGR_888, + GUI_COLOR_RGBA_8888, +}; +enum gui_color bfin_gui_color (const char *color); +int bfin_gui_color_depth (enum gui_color color); + +void *bfin_gui_setup (void *state, int enabled, int height, int width, + enum gui_color color); + +unsigned bfin_gui_update (void *state, const void *source, unsigned nr_bytes); + +#else + +# define bfin_gui_color(...) 0 +# define bfin_gui_color_depth(...) 0 +# define bfin_gui_setup(...) NULL +# define bfin_gui_update(...) 0 + +#endif + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/insn_list.def b/external/gpl3/gdb/dist/sim/bfin/insn_list.def new file mode 100644 index 000000000000..41ff91ca119a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/insn_list.def @@ -0,0 +1,62 @@ +/* Blackfin instruction classes list + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* Only bother with insn groups rather than exact insn (for now?). */ +I(ProgCtrl_nop) +I(ProgCtrl_branch) +I(ProgCtrl_sync) +I(ProgCtrl_cec) +I(ProgCtrl_atomic) +I(CaCTRL) +I(PushPopReg) +I(PushPopMultiple) +I(ccMV) +I(CCflag) +I(CC2dreg) +I(CC2stat) +I(BRCC) +I(UJUMP) +I(REGMV) +I(ALU2op) +I(PTR2op) +I(LOGI2op) +I(COMP3op) +I(COMPI2opD) +I(COMPI2opP) +I(LDSTpmod) +I(dagMODim) +I(dagMODik) +I(dspLDST) +I(LDST) +I(LDSTiiFP) +I(LDSTii) +I(LoopSetup) +I(LDIMMhalf) +I(CALLa) +I(LDSTidxI) +I(linkage) +I(dsp32mac) +I(dsp32mult) +I(dsp32alu) +I(dsp32shift) +I(dsp32shiftimm) +I(psedoDEBUG) +I(psedoOChar) +I(psedodbg_assert) diff --git a/external/gpl3/gdb/dist/sim/bfin/interp.c b/external/gpl3/gdb/dist/sim/bfin/interp.c new file mode 100644 index 000000000000..f8669d308809 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/interp.c @@ -0,0 +1,1250 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gdb/callback.h" +#include "gdb/signals.h" +#include "sim-main.h" +#include "sim-hw.h" + +#include "targ-vals.h" + +/* The numbers here do not matter. They just need to be unique. */ +#define CB_SYS_ioctl 201 +#define CB_SYS_mmap2 202 +#define CB_SYS_munmap 203 +#define CB_SYS_dup2 204 +#define CB_SYS_getuid 205 +#define CB_SYS_getuid32 206 +#define CB_SYS_getgid 207 +#define CB_SYS_getgid32 208 +#define CB_SYS_setuid 209 +#define CB_SYS_setuid32 210 +#define CB_SYS_setgid 211 +#define CB_SYS_setgid32 212 +#define CB_SYS_pread 213 +#define CB_SYS__llseek 214 +#define CB_SYS_getcwd 215 +#define CB_SYS_stat64 216 +#define CB_SYS_lstat64 217 +#define CB_SYS_fstat64 218 +#define CB_SYS_ftruncate64 219 +#define CB_SYS_gettimeofday 220 +#define CB_SYS_access 221 +#include "linux-targ-map.h" +#include "linux-fixed-code.h" + +#include "elf/common.h" +#include "elf/external.h" +#include "elf/internal.h" +#include "elf/bfin.h" +#include "elf-bfd.h" + +#include "dv-bfin_cec.h" +#include "dv-bfin_mmu.h" + +#ifndef HAVE_GETUID +# define getuid() 0 +#endif +#ifndef HAVE_GETGID +# define getgid() 0 +#endif +#ifndef HAVE_GETEUID +# define geteuid() 0 +#endif +#ifndef HAVE_GETEGID +# define getegid() 0 +#endif +#ifndef HAVE_SETUID +# define setuid(uid) -1 +#endif +#ifndef HAVE_SETGID +# define setgid(gid) -1 +#endif + +static const char stat_map_32[] = +/* Linux kernel 32bit layout: */ +"st_dev,2:space,2:st_ino,4:st_mode,2:st_nlink,2:st_uid,2:st_gid,2:st_rdev,2:" +"space,2:st_size,4:st_blksize,4:st_blocks,4:st_atime,4:st_atimensec,4:" +"st_mtime,4:st_mtimensec,4:st_ctime,4:st_ctimensec,4:space,4:space,4"; +/* uClibc public ABI 32bit layout: +"st_dev,8:space,2:space,2:st_ino,4:st_mode,4:st_nlink,4:st_uid,4:st_gid,4:" +"st_rdev,8:space,2:space,2:st_size,4:st_blksiez,4:st_blocks,4:st_atime,4:" +"st_atimensec,4:st_mtime,4:st_mtimensec,4:st_ctime,4:st_ctimensec,4:space,4:" +"space,4"; */ +static const char stat_map_64[] = +"st_dev,8:space,4:space,4:st_mode,4:st_nlink,4:st_uid,4:st_gid,4:st_rdev,8:" +"space,4:st_size,8:st_blksize,4:st_blocks,8:st_atime,4:st_atimensec,4:" +"st_mtime,4:st_mtimensec,4:st_ctime,4:st_ctimensec,4:st_ino,8"; + +/* Count the number of arguments in an argv. */ +static int +count_argc (const char * const *argv) +{ + int i; + + if (! argv) + return -1; + + for (i = 0; argv[i] != NULL; ++i) + continue; + return i; +} + +/* Read/write functions for system call interface. */ + +static int +syscall_read_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + MAYBE_TRACE (CORE, cpu, "DBUS FETCH (syscall) %i bytes @ 0x%08lx", bytes, taddr); + + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); +} + +static int +syscall_write_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, const char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + SIM_CPU *cpu = (SIM_CPU *) sc->p2; + + MAYBE_TRACE (CORE, cpu, "DBUS STORE (syscall) %i bytes @ 0x%08lx", bytes, taddr); + + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); +} + +/* Simulate a monitor trap, put the result into r0 and errno into r1 + return offset by which to adjust pc. */ + +void +bfin_syscall (SIM_CPU *cpu) +{ + SIM_DESC sd = CPU_STATE (cpu); + const char * const *argv = (void *)STATE_PROG_ARGV (sd); + host_callback *cb = STATE_CALLBACK (sd); + bu32 args[6]; + CB_SYSCALL sc; + char *p; + char _tbuf[512], *tbuf = _tbuf; + int fmt_ret_hex = 0; + + CB_SYSCALL_INIT (&sc); + + if (STATE_ENVIRONMENT (sd) == USER_ENVIRONMENT) + { + /* Linux syscall. */ + sc.func = PREG (0); + sc.arg1 = args[0] = DREG (0); + sc.arg2 = args[1] = DREG (1); + sc.arg3 = args[2] = DREG (2); + sc.arg4 = args[3] = DREG (3); + /*sc.arg5 =*/ args[4] = DREG (4); + /*sc.arg6 =*/ args[5] = DREG (5); + } + else + { + /* libgloss syscall. */ + sc.func = PREG (0); + sc.arg1 = args[0] = GET_LONG (DREG (0)); + sc.arg2 = args[1] = GET_LONG (DREG (0) + 4); + sc.arg3 = args[2] = GET_LONG (DREG (0) + 8); + sc.arg4 = args[3] = GET_LONG (DREG (0) + 12); + /*sc.arg5 =*/ args[4] = GET_LONG (DREG (0) + 16); + /*sc.arg6 =*/ args[5] = GET_LONG (DREG (0) + 20); + } + sc.p1 = (PTR) sd; + sc.p2 = (PTR) cpu; + sc.read_mem = syscall_read_mem; + sc.write_mem = syscall_write_mem; + + /* Common cb_syscall() handles most functions. */ + switch (cb_target_to_host_syscall (cb, sc.func)) + { + case CB_SYS_exit: + tbuf += sprintf (tbuf, "exit(%i)", args[0]); + sim_engine_halt (sd, cpu, NULL, PCREG, sim_exited, sc.arg1); + +#ifdef CB_SYS_argc + case CB_SYS_argc: + tbuf += sprintf (tbuf, "argc()"); + sc.result = count_argc (argv); + break; + case CB_SYS_argnlen: + { + tbuf += sprintf (tbuf, "argnlen(%u)", args[0]); + if (sc.arg1 < count_argc (argv)) + sc.result = strlen (argv[sc.arg1]); + else + sc.result = -1; + } + break; + case CB_SYS_argn: + { + tbuf += sprintf (tbuf, "argn(%u)", args[0]); + if (sc.arg1 < count_argc (argv)) + { + const char *argn = argv[sc.arg1]; + int len = strlen (argn); + int written = sc.write_mem (cb, &sc, sc.arg2, argn, len + 1); + if (written == len + 1) + sc.result = sc.arg2; + else + sc.result = -1; + } + else + sc.result = -1; + } + break; +#endif + + case CB_SYS_gettimeofday: + { + struct timeval _tv, *tv = &_tv; + struct timezone _tz, *tz = &_tz; + + tbuf += sprintf (tbuf, "gettimeofday(%#x, %#x)", args[0], args[1]); + + if (sc.arg1 == 0) + tv = NULL; + if (sc.arg2 == 0) + tz = NULL; + sc.result = gettimeofday (tv, tz); + + if (sc.result == 0) + { + bu32 t; + + if (tv) + { + t = tv->tv_sec; + sc.write_mem (cb, &sc, sc.arg1, (void *)&t, 4); + t = tv->tv_usec; + sc.write_mem (cb, &sc, sc.arg1 + 4, (void *)&t, 4); + } + + if (sc.arg2) + { + t = tz->tz_minuteswest; + sc.write_mem (cb, &sc, sc.arg1, (void *)&t, 4); + t = tz->tz_dsttime; + sc.write_mem (cb, &sc, sc.arg1 + 4, (void *)&t, 4); + } + } + else + goto sys_finish; + } + break; + + case CB_SYS_ioctl: + /* XXX: hack just enough to get basic stdio w/uClibc ... */ + tbuf += sprintf (tbuf, "ioctl(%i, %#x, %u)", args[0], args[1], args[2]); + if (sc.arg2 == 0x5401) + { + sc.result = !isatty (sc.arg1); + sc.errcode = 0; + } + else + { + sc.result = -1; + sc.errcode = TARGET_EINVAL; + } + break; + + case CB_SYS_mmap2: + { + static bu32 heap = BFIN_DEFAULT_MEM_SIZE / 2; + + fmt_ret_hex = 1; + tbuf += sprintf (tbuf, "mmap2(%#x, %u, %#x, %#x, %i, %u)", + args[0], args[1], args[2], args[3], args[4], args[5]); + + sc.errcode = 0; + + if (sc.arg4 & 0x20 /*MAP_ANONYMOUS*/) + /* XXX: We don't handle zeroing, but default is all zeros. */; + else if (args[4] >= MAX_CALLBACK_FDS) + sc.errcode = TARGET_ENOSYS; + else + { +#ifdef HAVE_PREAD + char *data = xmalloc (sc.arg2); + + /* XXX: Should add a cb->pread. */ + if (pread (cb->fdmap[args[4]], data, sc.arg2, args[5] << 12) == sc.arg2) + sc.write_mem (cb, &sc, heap, data, sc.arg2); + else + sc.errcode = TARGET_EINVAL; + + free (data); +#else + sc.errcode = TARGET_ENOSYS; +#endif + } + + if (sc.errcode) + { + sc.result = -1; + break; + } + + sc.result = heap; + heap += sc.arg2; + /* Keep it page aligned. */ + heap = ALIGN (heap, 4096); + + break; + } + + case CB_SYS_munmap: + /* XXX: meh, just lie for mmap(). */ + tbuf += sprintf (tbuf, "munmap(%#x, %u)", args[0], args[1]); + sc.result = 0; + break; + + case CB_SYS_dup2: + tbuf += sprintf (tbuf, "dup2(%i, %i)", args[0], args[1]); + if (sc.arg1 >= MAX_CALLBACK_FDS || sc.arg2 >= MAX_CALLBACK_FDS) + { + sc.result = -1; + sc.errcode = TARGET_EINVAL; + } + else + { + sc.result = dup2 (cb->fdmap[sc.arg1], cb->fdmap[sc.arg2]); + goto sys_finish; + } + break; + + case CB_SYS__llseek: + tbuf += sprintf (tbuf, "llseek(%i, %u, %u, %#x, %u)", + args[0], args[1], args[2], args[3], args[4]); + sc.func = TARGET_LINUX_SYS_lseek; + if (sc.arg2) + { + sc.result = -1; + sc.errcode = TARGET_EINVAL; + } + else + { + sc.arg2 = sc.arg3; + sc.arg3 = args[4]; + cb_syscall (cb, &sc); + if (sc.result != -1) + { + bu32 z = 0; + sc.write_mem (cb, &sc, args[3], (void *)&sc.result, 4); + sc.write_mem (cb, &sc, args[3] + 4, (void *)&z, 4); + } + } + break; + + /* XXX: Should add a cb->pread. */ + case CB_SYS_pread: + tbuf += sprintf (tbuf, "pread(%i, %#x, %u, %i)", + args[0], args[1], args[2], args[3]); + if (sc.arg1 >= MAX_CALLBACK_FDS) + { + sc.result = -1; + sc.errcode = TARGET_EINVAL; + } + else + { + long old_pos, read_result, read_errcode; + + /* Get current filepos. */ + sc.func = TARGET_LINUX_SYS_lseek; + sc.arg2 = 0; + sc.arg3 = SEEK_CUR; + cb_syscall (cb, &sc); + if (sc.result == -1) + break; + old_pos = sc.result; + + /* Move to the new pos. */ + sc.func = TARGET_LINUX_SYS_lseek; + sc.arg2 = args[3]; + sc.arg3 = SEEK_SET; + cb_syscall (cb, &sc); + if (sc.result == -1) + break; + + /* Read the data. */ + sc.func = TARGET_LINUX_SYS_read; + sc.arg2 = args[1]; + sc.arg3 = args[2]; + cb_syscall (cb, &sc); + read_result = sc.result; + read_errcode = sc.errcode; + + /* Move back to the old pos. */ + sc.func = TARGET_LINUX_SYS_lseek; + sc.arg2 = old_pos; + sc.arg3 = SEEK_SET; + cb_syscall (cb, &sc); + + sc.result = read_result; + sc.errcode = read_errcode; + } + break; + + case CB_SYS_getcwd: + tbuf += sprintf (tbuf, "getcwd(%#x, %u)", args[0], args[1]); + + p = alloca (sc.arg2); + if (getcwd (p, sc.arg2) == NULL) + { + sc.result = -1; + sc.errcode = TARGET_EINVAL; + } + else + { + sc.write_mem (cb, &sc, sc.arg1, p, sc.arg2); + sc.result = sc.arg1; + } + break; + + case CB_SYS_stat64: + tbuf += sprintf (tbuf, "stat64(%#x, %u)", args[0], args[1]); + cb->stat_map = stat_map_64; + sc.func = TARGET_LINUX_SYS_stat; + cb_syscall (cb, &sc); + cb->stat_map = stat_map_32; + break; + case CB_SYS_lstat64: + tbuf += sprintf (tbuf, "lstat64(%#x, %u)", args[0], args[1]); + cb->stat_map = stat_map_64; + sc.func = TARGET_LINUX_SYS_lstat; + cb_syscall (cb, &sc); + cb->stat_map = stat_map_32; + break; + case CB_SYS_fstat64: + tbuf += sprintf (tbuf, "fstat64(%#x, %u)", args[0], args[1]); + cb->stat_map = stat_map_64; + sc.func = TARGET_LINUX_SYS_fstat; + cb_syscall (cb, &sc); + cb->stat_map = stat_map_32; + break; + + case CB_SYS_ftruncate64: + tbuf += sprintf (tbuf, "ftruncate64(%u, %u)", args[0], args[1]); + sc.func = TARGET_LINUX_SYS_ftruncate; + cb_syscall (cb, &sc); + break; + + case CB_SYS_getuid: + case CB_SYS_getuid32: + tbuf += sprintf (tbuf, "getuid()"); + sc.result = getuid (); + goto sys_finish; + case CB_SYS_getgid: + case CB_SYS_getgid32: + tbuf += sprintf (tbuf, "getgid()"); + sc.result = getgid (); + goto sys_finish; + case CB_SYS_setuid: + sc.arg1 &= 0xffff; + case CB_SYS_setuid32: + tbuf += sprintf (tbuf, "setuid(%u)", args[0]); + sc.result = setuid (sc.arg1); + goto sys_finish; + case CB_SYS_setgid: + sc.arg1 &= 0xffff; + case CB_SYS_setgid32: + tbuf += sprintf (tbuf, "setgid(%u)", args[0]); + sc.result = setgid (sc.arg1); + goto sys_finish; + + case CB_SYS_getpid: + tbuf += sprintf (tbuf, "getpid()"); + sc.result = getpid (); + goto sys_finish; + case CB_SYS_kill: + tbuf += sprintf (tbuf, "kill(%u, %i)", args[0], args[1]); + /* Only let the app kill itself. */ + if (sc.arg1 != getpid ()) + { + sc.result = -1; + sc.errcode = TARGET_EPERM; + } + else + { +#ifdef HAVE_KILL + sc.result = kill (sc.arg1, sc.arg2); + goto sys_finish; +#else + sc.result = -1; + sc.errcode = TARGET_ENOSYS; +#endif + } + break; + + case CB_SYS_open: + tbuf += sprintf (tbuf, "open(%#x, %#x, %o)", args[0], args[1], args[2]); + goto case_default; + case CB_SYS_close: + tbuf += sprintf (tbuf, "close(%i)", args[0]); + goto case_default; + case CB_SYS_read: + tbuf += sprintf (tbuf, "read(%i, %#x, %u)", args[0], args[1], args[2]); + goto case_default; + case CB_SYS_write: + tbuf += sprintf (tbuf, "write(%i, %#x, %u)", args[0], args[1], args[2]); + goto case_default; + case CB_SYS_lseek: + tbuf += sprintf (tbuf, "lseek(%i, %i, %i)", args[0], args[1], args[2]); + goto case_default; + case CB_SYS_unlink: + tbuf += sprintf (tbuf, "unlink(%#x)", args[0]); + goto case_default; + case CB_SYS_truncate: + tbuf += sprintf (tbuf, "truncate(%#x, %i)", args[0], args[1]); + goto case_default; + case CB_SYS_ftruncate: + tbuf += sprintf (tbuf, "ftruncate(%i, %i)", args[0], args[1]); + goto case_default; + case CB_SYS_rename: + tbuf += sprintf (tbuf, "rename(%#x, %#x)", args[0], args[1]); + goto case_default; + case CB_SYS_stat: + tbuf += sprintf (tbuf, "stat(%#x, %#x)", args[0], args[1]); + goto case_default; + case CB_SYS_fstat: + tbuf += sprintf (tbuf, "fstat(%i, %#x)", args[0], args[1]); + goto case_default; + case CB_SYS_lstat: + tbuf += sprintf (tbuf, "lstat(%i, %#x)", args[0], args[1]); + goto case_default; + case CB_SYS_pipe: + tbuf += sprintf (tbuf, "pipe(%#x, %#x)", args[0], args[1]); + goto case_default; + + default: + tbuf += sprintf (tbuf, "???_%i(%#x, %#x, %#x, %#x, %#x, %#x)", sc.func, + args[0], args[1], args[2], args[3], args[4], args[5]); + case_default: + cb_syscall (cb, &sc); + break; + + sys_finish: + if (sc.result == -1) + { + cb->last_errno = errno; + sc.errcode = cb->get_errno (cb); + } + } + + TRACE_EVENTS (cpu, "syscall_%i(%#x, %#x, %#x, %#x, %#x, %#x) = %li (error = %i)", + sc.func, args[0], args[1], args[2], args[3], args[4], args[5], + sc.result, sc.errcode); + + tbuf += sprintf (tbuf, " = "); + if (STATE_ENVIRONMENT (sd) == USER_ENVIRONMENT) + { + if (sc.result == -1) + { + tbuf += sprintf (tbuf, "-1 (error = %i)", sc.errcode); + if (sc.errcode == cb_host_to_target_errno (cb, ENOSYS)) + { + sim_io_eprintf (sd, "bfin-sim: %#x: unimplemented syscall %i\n", + PCREG, sc.func); + } + SET_DREG (0, -sc.errcode); + } + else + { + if (fmt_ret_hex) + tbuf += sprintf (tbuf, "%#lx", sc.result); + else + tbuf += sprintf (tbuf, "%lu", sc.result); + SET_DREG (0, sc.result); + } + } + else + { + tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode); + SET_DREG (0, sc.result); + /* Blackfin libgloss only expects R0 to be updated, not R1. */ + /*SET_DREG (1, sc.errcode);*/ + } + + TRACE_SYSCALL (cpu, "%s", _tbuf); +} + +void +trace_register (SIM_DESC sd, + sim_cpu *cpu, + const char *fmt, + ...) +{ + va_list ap; + trace_printf (sd, cpu, "%s %s", + "reg: ", + TRACE_PREFIX (CPU_TRACE_DATA (cpu))); + va_start (ap, fmt); + trace_vprintf (sd, cpu, fmt, ap); + va_end (ap); + trace_printf (sd, cpu, "\n"); +} + +/* Execute a single instruction. */ + +static sim_cia +step_once (SIM_CPU *cpu) +{ + SIM_DESC sd = CPU_STATE (cpu); + bu32 insn_len, oldpc = PCREG; + int i; + bool ssstep; + + if (TRACE_ANY_P (cpu)) + trace_prefix (sd, cpu, NULL_CIA, oldpc, TRACE_LINENUM_P (cpu), + NULL, 0, " "); /* Use a space for gcc warnings. */ + + /* Handle hardware single stepping when lower than EVT3, and when SYSCFG + has already had the SSSTEP bit enabled. */ + ssstep = false; + if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT + && (SYSCFGREG & SYSCFG_SSSTEP)) + { + int ivg = cec_get_ivg (cpu); + if (ivg == -1 || ivg > 3) + ssstep = true; + } + +#if 0 + /* XXX: Is this what happens on the hardware ? */ + if (cec_get_ivg (cpu) == EVT_EMU) + cec_return (cpu, EVT_EMU); +#endif + + BFIN_CPU_STATE.did_jump = false; + + insn_len = interp_insn_bfin (cpu, oldpc); + + /* If we executed this insn successfully, then we always decrement + the loop counter. We don't want to update the PC though if the + last insn happened to be a change in code flow (jump/etc...). */ + if (!BFIN_CPU_STATE.did_jump) + SET_PCREG (hwloop_get_next_pc (cpu, oldpc, insn_len)); + for (i = 1; i >= 0; --i) + if (LCREG (i) && oldpc == LBREG (i)) + { + SET_LCREG (i, LCREG (i) - 1); + if (LCREG (i)) + break; + } + + ++ PROFILE_TOTAL_INSN_COUNT (CPU_PROFILE_DATA (cpu)); + + /* Handle hardware single stepping only if we're still lower than EVT3. + XXX: May not be entirely correct wrt EXCPT insns. */ + if (ssstep) + { + int ivg = cec_get_ivg (cpu); + if (ivg == -1 || ivg > 3) + { + INSN_LEN = 0; + cec_exception (cpu, VEC_STEP); + } + } + + return oldpc; +} + +void +sim_engine_run (SIM_DESC sd, + int next_cpu_nr, /* ignore */ + int nr_cpus, /* ignore */ + int siggnal) /* ignore */ +{ + bu32 ticks; + SIM_CPU *cpu; + + SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + + cpu = STATE_CPU (sd, 0); + + while (1) + { + step_once (cpu); + /* Process any events -- can't use tickn because it may + advance right over the next event. */ + for (ticks = 0; ticks < CYCLE_DELAY; ++ticks) + if (sim_events_tick (sd)) + sim_events_process (sd); + } +} + +/* Cover function of sim_state_free to free the cpu buffers as well. */ + +static void +free_state (SIM_DESC sd) +{ + if (STATE_MODULES (sd) != NULL) + sim_module_uninstall (sd); + sim_cpu_free_all (sd); + sim_state_free (sd); +} + +/* Create an instance of the simulator. */ + +static void +bfin_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu) +{ + memset (&cpu->state, 0, sizeof (cpu->state)); + + PROFILE_TOTAL_INSN_COUNT (CPU_PROFILE_DATA (cpu)) = 0; + + bfin_model_cpu_init (sd, cpu); + + /* Set default stack to top of scratch pad. */ + SET_SPREG (BFIN_DEFAULT_MEM_SIZE); + SET_KSPREG (BFIN_DEFAULT_MEM_SIZE); + SET_USPREG (BFIN_DEFAULT_MEM_SIZE); + + /* This is what the hardware likes. */ + SET_SYSCFGREG (0x30); +} + +SIM_DESC +sim_open (SIM_OPEN_KIND kind, host_callback *callback, + struct bfd *abfd, char **argv) +{ + char c; + int i; + SIM_DESC sd = sim_state_alloc (kind, callback); + + /* The cpu data is kept in a separately allocated chunk of memory. */ + if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + { + /* XXX: Only first core gets profiled ? */ + SIM_CPU *cpu = STATE_CPU (sd, 0); + STATE_WATCHPOINTS (sd)->pc = &PCREG; + STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PCREG); + } + + if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* XXX: Default to the Virtual environment. */ + if (STATE_ENVIRONMENT (sd) == ALL_ENVIRONMENT) + STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT; + + /* These options override any module options. + Obviously ambiguity should be avoided, however the caller may wish to + augment the meaning of an option. */ +#define e_sim_add_option_table(sd, options) \ + do { \ + extern const OPTION options[]; \ + sim_add_option_table (sd, NULL, options); \ + } while (0) + e_sim_add_option_table (sd, bfin_mmu_options); + e_sim_add_option_table (sd, bfin_mach_options); + + /* getopt will print the error message so we just have to exit if this fails. + FIXME: Hmmm... in the case of gdb we need getopt to call + print_filtered. */ + if (sim_parse_args (sd, argv) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Allocate external memory if none specified by user. + Use address 4 here in case the user wanted address 0 unmapped. */ + if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) + { + bu16 emuexcpt = 0x25; + sim_do_commandf (sd, "memory-size 0x%lx", BFIN_DEFAULT_MEM_SIZE); + sim_write (sd, 0, (void *)&emuexcpt, 2); + } + + /* Check for/establish the a reference program image. */ + if (sim_analyze_program (sd, + (STATE_PROG_ARGV (sd) != NULL + ? *STATE_PROG_ARGV (sd) + : NULL), abfd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* Establish any remaining configuration options. */ + if (sim_config (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + if (sim_post_argv_init (sd) != SIM_RC_OK) + { + free_state (sd); + return 0; + } + + /* CPU specific initialization. */ + for (i = 0; i < MAX_NR_PROCESSORS; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + bfin_initialize_cpu (sd, cpu); + } + + return sd; +} + +void +sim_close (SIM_DESC sd, int quitting) +{ + sim_module_uninstall (sd); +} + +/* Some utils don't like having a NULL environ. */ +static const char * const simple_env[] = { "HOME=/", "PATH=/bin", NULL }; + +static bu32 fdpic_load_offset; + +static bool +bfin_fdpic_load (SIM_DESC sd, SIM_CPU *cpu, struct bfd *abfd, bu32 *sp, + bu32 *elf_addrs, char **ldso_path) +{ + bool ret; + int i; + + Elf_Internal_Ehdr *iehdr; + Elf32_External_Ehdr ehdr; + Elf_Internal_Phdr *phdrs; + unsigned char *data; + long phdr_size; + int phdrc; + bu32 nsegs; + + bu32 max_load_addr; + + unsigned char null[4] = { 0, 0, 0, 0 }; + + ret = false; + *ldso_path = NULL; + + /* See if this an FDPIC ELF. */ + phdrs = NULL; + if (!abfd) + goto skip_fdpic_init; + if (bfd_seek (abfd, 0, SEEK_SET) != 0) + goto skip_fdpic_init; + if (bfd_bread (&ehdr, sizeof (ehdr), abfd) != sizeof (ehdr)) + goto skip_fdpic_init; + iehdr = elf_elfheader (abfd); + if (!(iehdr->e_flags & EF_BFIN_FDPIC)) + goto skip_fdpic_init; + + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, "Loading FDPIC ELF %s\n Load base: %#x\n ELF entry: %#x\n", + bfd_get_filename (abfd), fdpic_load_offset, elf_addrs[0]); + + /* Grab the Program Headers to set up the loadsegs on the stack. */ + phdr_size = bfd_get_elf_phdr_upper_bound (abfd); + if (phdr_size == -1) + goto skip_fdpic_init; + phdrs = xmalloc (phdr_size); + phdrc = bfd_get_elf_phdrs (abfd, phdrs); + if (phdrc == -1) + goto skip_fdpic_init; + + /* Push the Ehdr onto the stack. */ + *sp -= sizeof (ehdr); + elf_addrs[3] = *sp; + sim_write (sd, *sp, (void *)&ehdr, sizeof (ehdr)); + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, " Elf_Ehdr: %#x\n", *sp); + + /* Since we're relocating things ourselves, we need to relocate + the start address as well. */ + elf_addrs[0] = bfd_get_start_address (abfd) + fdpic_load_offset; + + /* And the Exec's Phdrs onto the stack. */ + if (STATE_PROG_BFD (sd) == abfd) + { + elf_addrs[4] = elf_addrs[0]; + + phdr_size = iehdr->e_phentsize * iehdr->e_phnum; + if (bfd_seek (abfd, iehdr->e_phoff, SEEK_SET) != 0) + goto skip_fdpic_init; + data = xmalloc (phdr_size); + if (bfd_bread (data, phdr_size, abfd) != phdr_size) + goto skip_fdpic_init; + *sp -= phdr_size; + elf_addrs[1] = *sp; + elf_addrs[2] = phdrc; + sim_write (sd, *sp, data, phdr_size); + free (data); + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, " Elf_Phdrs: %#x\n", *sp); + } + + /* Now push all the loadsegs. */ + nsegs = 0; + max_load_addr = 0; + for (i = phdrc; i >= 0; --i) + if (phdrs[i].p_type == PT_LOAD) + { + Elf_Internal_Phdr *p = &phdrs[i]; + bu32 paddr, vaddr, memsz, filesz; + + paddr = p->p_paddr + fdpic_load_offset; + vaddr = p->p_vaddr; + memsz = p->p_memsz; + filesz = p->p_filesz; + + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, " PHDR %i: vma %#x lma %#x filesz %#x memsz %#x\n", + i, vaddr, paddr, filesz, memsz); + + data = xmalloc (memsz); + if (memsz != filesz) + memset (data + filesz, 0, memsz - filesz); + + if (bfd_seek (abfd, p->p_offset, SEEK_SET) == 0 + && bfd_bread (data, filesz, abfd) == filesz) + sim_write (sd, paddr, data, memsz); + + free (data); + + max_load_addr = MAX (paddr + memsz, max_load_addr); + + *sp -= 12; + sim_write (sd, *sp+0, (void *)&paddr, 4); /* loadseg.addr */ + sim_write (sd, *sp+4, (void *)&vaddr, 4); /* loadseg.p_vaddr */ + sim_write (sd, *sp+8, (void *)&memsz, 4); /* loadseg.p_memsz */ + ++nsegs; + } + else if (phdrs[i].p_type == PT_DYNAMIC) + { + elf_addrs[5] = phdrs[i].p_paddr + fdpic_load_offset; + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, " PT_DYNAMIC: %#x\n", elf_addrs[5]); + } + else if (phdrs[i].p_type == PT_INTERP) + { + uint32_t off = phdrs[i].p_offset; + uint32_t len = phdrs[i].p_filesz; + + *ldso_path = xmalloc (len); + if (bfd_seek (abfd, off, SEEK_SET) != 0 + || bfd_bread (*ldso_path, len, abfd) != len) + { + free (*ldso_path); + *ldso_path = NULL; + } + else if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + sim_io_printf (sd, " PT_INTERP: %s\n", *ldso_path); + } + + /* Update the load offset with a few extra pages. */ + fdpic_load_offset = ALIGN (MAX (max_load_addr, fdpic_load_offset), 0x10000); + fdpic_load_offset += 0x10000; + + /* Push the summary loadmap info onto the stack last. */ + *sp -= 4; + sim_write (sd, *sp+0, null, 2); /* loadmap.version */ + sim_write (sd, *sp+2, (void *)&nsegs, 2); /* loadmap.nsegs */ + + ret = true; + skip_fdpic_init: + free (phdrs); + + return ret; +} + +static void +bfin_user_init (SIM_DESC sd, SIM_CPU *cpu, struct bfd *abfd, + const char * const *argv, const char * const *env) +{ + /* XXX: Missing host -> target endian ... */ + /* Linux starts the user app with the stack: + argc + argv[0] -- pointers to the actual strings + argv[1..N] + NULL + env[0] + env[1..N] + NULL + auxvt[0].type -- ELF Auxiliary Vector Table + auxvt[0].value + auxvt[1..N] + AT_NULL + 0 + argv[0..N][0..M] -- actual argv/env strings + env[0..N][0..M] + FDPIC loadmaps -- for FDPIC apps + So set things up the same way. */ + int i, argc, envc; + bu32 argv_flat, env_flat; + + bu32 sp, sp_flat; + + /* start, at_phdr, at_phnum, at_base, at_entry, pt_dynamic */ + bu32 elf_addrs[6]; + bu32 auxvt, auxvt_size; + bu32 exec_loadmap, ldso_loadmap; + char *ldso_path; + + unsigned char null[4] = { 0, 0, 0, 0 }; + + host_callback *cb = STATE_CALLBACK (sd); + + elf_addrs[0] = elf_addrs[4] = bfd_get_start_address (abfd); + elf_addrs[1] = elf_addrs[2] = elf_addrs[3] = elf_addrs[5] = 0; + + /* Keep the load addresses consistent between runs. Also make sure we make + space for the fixed code region (part of the Blackfin Linux ABI). */ + fdpic_load_offset = 0x1000; + + /* First try to load this as an FDPIC executable. */ + sp = SPREG; + if (!bfin_fdpic_load (sd, cpu, STATE_PROG_BFD (sd), &sp, elf_addrs, &ldso_path)) + goto skip_fdpic_init; + exec_loadmap = sp; + + /* If that worked, then load the fixed code region. We only do this for + FDPIC ELFs atm because they are PIEs and let us relocate them without + manual fixups. FLAT files however require location processing which + we do not do ourselves, and they link with a VMA of 0. */ + sim_write (sd, 0x400, bfin_linux_fixed_code, sizeof (bfin_linux_fixed_code)); + + /* If the FDPIC needs an interpreter, then load it up too. */ + if (ldso_path) + { + const char *ldso_full_path = concat (simulator_sysroot, ldso_path, NULL); + struct bfd *ldso_bfd; + + ldso_bfd = bfd_openr (ldso_full_path, STATE_TARGET (sd)); + if (!ldso_bfd) + { + sim_io_eprintf (sd, "bfin-sim: bfd open failed: %s\n", ldso_full_path); + goto static_fdpic; + } + if (!bfd_check_format (ldso_bfd, bfd_object)) + sim_io_eprintf (sd, "bfin-sim: bfd format not valid: %s\n", ldso_full_path); + bfd_set_arch_info (ldso_bfd, STATE_ARCHITECTURE (sd)); + + if (!bfin_fdpic_load (sd, cpu, ldso_bfd, &sp, elf_addrs, &ldso_path)) + sim_io_eprintf (sd, "bfin-sim: FDPIC ldso failed to load: %s\n", ldso_full_path); + if (ldso_path) + sim_io_eprintf (sd, "bfin-sim: FDPIC ldso (%s) needs an interpreter (%s) !?\n", + ldso_full_path, ldso_path); + + ldso_loadmap = sp; + } + else + static_fdpic: + ldso_loadmap = 0; + + /* Finally setup the registers required by the FDPIC ABI. */ + SET_DREG (7, 0); /* Zero out FINI funcptr -- ldso will set this up. */ + SET_PREG (0, exec_loadmap); /* Exec loadmap addr. */ + SET_PREG (1, ldso_loadmap); /* Interp loadmap addr. */ + SET_PREG (2, elf_addrs[5]); /* PT_DYNAMIC map addr. */ + + auxvt = 1; + SET_SPREG (sp); + skip_fdpic_init: + sim_pc_set (cpu, elf_addrs[0]); + + /* Figure out how much storage the argv/env strings need. */ + argc = count_argc (argv); + if (argc == -1) + argc = 0; + argv_flat = argc; /* NUL bytes */ + for (i = 0; i < argc; ++i) + argv_flat += strlen (argv[i]); + + if (!env) + env = simple_env; + envc = count_argc (env); + env_flat = envc; /* NUL bytes */ + for (i = 0; i < envc; ++i) + env_flat += strlen (env[i]); + + /* Push the Auxiliary Vector Table between argv/env and actual strings. */ + sp_flat = sp = ALIGN (SPREG - argv_flat - env_flat - 4, 4); + if (auxvt) + { +# define AT_PUSH(at, val) \ + auxvt_size += 8; \ + sp -= 4; \ + auxvt = (val); \ + sim_write (sd, sp, (void *)&auxvt, 4); \ + sp -= 4; \ + auxvt = (at); \ + sim_write (sd, sp, (void *)&auxvt, 4) + auxvt_size = 0; + unsigned int egid = getegid (), gid = getgid (); + unsigned int euid = geteuid (), uid = getuid (); + AT_PUSH (AT_NULL, 0); + AT_PUSH (AT_SECURE, egid != gid || euid != uid); + AT_PUSH (AT_EGID, egid); + AT_PUSH (AT_GID, gid); + AT_PUSH (AT_EUID, euid); + AT_PUSH (AT_UID, uid); + AT_PUSH (AT_ENTRY, elf_addrs[4]); + AT_PUSH (AT_FLAGS, 0); + AT_PUSH (AT_BASE, elf_addrs[3]); + AT_PUSH (AT_PHNUM, elf_addrs[2]); + AT_PUSH (AT_PHENT, sizeof (Elf32_External_Phdr)); + AT_PUSH (AT_PHDR, elf_addrs[1]); + AT_PUSH (AT_CLKTCK, 100); /* XXX: This ever not 100 ? */ + AT_PUSH (AT_PAGESZ, 4096); + AT_PUSH (AT_HWCAP, 0); +#undef AT_PUSH + } + SET_SPREG (sp); + + /* Push the argc/argv/env after the auxvt. */ + sp -= ((1 + argc + 1 + envc + 1) * 4); + SET_SPREG (sp); + + /* First push the argc value. */ + sim_write (sd, sp, (void *)&argc, 4); + sp += 4; + + /* Then the actual argv strings so we know where to point argv[]. */ + for (i = 0; i < argc; ++i) + { + unsigned len = strlen (argv[i]) + 1; + sim_write (sd, sp_flat, (void *)argv[i], len); + sim_write (sd, sp, (void *)&sp_flat, 4); + sp_flat += len; + sp += 4; + } + sim_write (sd, sp, null, 4); + sp += 4; + + /* Then the actual env strings so we know where to point env[]. */ + for (i = 0; i < envc; ++i) + { + unsigned len = strlen (env[i]) + 1; + sim_write (sd, sp_flat, (void *)env[i], len); + sim_write (sd, sp, (void *)&sp_flat, 4); + sp_flat += len; + sp += 4; + } + + /* Set some callbacks. */ + cb->syscall_map = cb_linux_syscall_map; + cb->errno_map = cb_linux_errno_map; + cb->open_map = cb_linux_open_map; + cb->signal_map = cb_linux_signal_map; + cb->stat_map = stat_map_32; +} + +static void +bfin_os_init (SIM_DESC sd, SIM_CPU *cpu, const char * const *argv) +{ + /* Pass the command line via a string in R0 like Linux expects. */ + int i; + bu8 byte; + bu32 cmdline = BFIN_L1_SRAM_SCRATCH; + + SET_DREG (0, cmdline); + if (argv && argv[0]) + { + i = 1; + byte = ' '; + while (argv[i]) + { + bu32 len = strlen (argv[i]); + sim_write (sd, cmdline, (void *)argv[i], len); + cmdline += len; + sim_write (sd, cmdline, &byte, 1); + ++cmdline; + ++i; + } + } + byte = 0; + sim_write (sd, cmdline, &byte, 1); +} + +SIM_RC +sim_create_inferior (SIM_DESC sd, struct bfd *abfd, + char **argv, char **env) +{ + SIM_CPU *cpu = STATE_CPU (sd, 0); + SIM_ADDR addr; + + /* Set the PC. */ + if (abfd != NULL) + addr = bfd_get_start_address (abfd); + else + addr = 0; + sim_pc_set (cpu, addr); + + /* Standalone mode (i.e. `bfin-...-run`) will take care of the argv + for us in sim_open() -> sim_parse_args(). But in debug mode (i.e. + 'target sim' with `bfin-...-gdb`), we need to handle it. */ + if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG) + { + free (STATE_PROG_ARGV (sd)); + STATE_PROG_ARGV (sd) = dupargv (argv); + } + + switch (STATE_ENVIRONMENT (sd)) + { + case USER_ENVIRONMENT: + bfin_user_init (sd, cpu, abfd, (void *)argv, (void *)env); + break; + case OPERATING_ENVIRONMENT: + bfin_os_init (sd, cpu, (void *)argv); + break; + default: + /* Nothing to do for virtual/all envs. */ + break; + } + + return SIM_RC_OK; +} + +void +sim_do_command (SIM_DESC sd, char *cmd) +{ + if (sim_args_command (sd, cmd) != SIM_RC_OK) + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); +} diff --git a/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.h b/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.h new file mode 100644 index 000000000000..afb1b1f09cb2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.h @@ -0,0 +1,75 @@ +/* DO NOT EDIT: Autogenerated from linux-fixed-code.s. */ +static const unsigned char bfin_linux_fixed_code[] = +{ +0x28, 0xe1, 0xad, 0x00, +0xa0, 0x00, +0x00, 0x20, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x91, +0x01, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x91, +0x08, 0x08, +0x02, 0x10, +0x02, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x01, 0x91, +0x01, 0x50, +0x00, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x01, 0x91, +0x01, 0x52, +0x00, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x01, 0x91, +0x01, 0x56, +0x00, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x01, 0x91, +0x01, 0x54, +0x00, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x01, 0x91, +0x01, 0x58, +0x00, 0x93, +0x10, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +0xa4, 0x00, +0x00, 0x00, +0x00, 0x00, +0x00, 0x00, +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.s b/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.s new file mode 100644 index 000000000000..c1dd358852e9 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/linux-fixed-code.s @@ -0,0 +1,85 @@ +/* Linux fixed code userspace ABI + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* For more info, see this page: + http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:fixed-code */ + +.text + +.align 16 +_sigreturn_stub: + P0 = 173; + EXCPT 0; +0: JUMP.S 0b; + +.align 16 +_atomic_xchg32: + R0 = [P0]; + [P0] = R1; + rts; + +.align 16 +_atomic_cas32: + R0 = [P0]; + CC = R0 == R1; + IF !CC JUMP 1f; + [P0] = R2; +1: + rts; + +.align 16 +_atomic_add32: + R1 = [P0]; + R0 = R1 + R0; + [P0] = R0; + rts; + +.align 16 +_atomic_sub32: + R1 = [P0]; + R0 = R1 - R0; + [P0] = R0; + rts; + +.align 16 +_atomic_ior32: + R1 = [P0]; + R0 = R1 | R0; + [P0] = R0; + rts; + +.align 16 +_atomic_and32: + R1 = [P0]; + R0 = R1 & R0; + [P0] = R0; + rts; + +.align 16 +_atomic_xor32: + R1 = [P0]; + R0 = R1 ^ R0; + [P0] = R0; + rts; + +.align 16 +_safe_user_instruction: + NOP; NOP; NOP; NOP; + EXCPT 0x4; diff --git a/external/gpl3/gdb/dist/sim/bfin/linux-targ-map.h b/external/gpl3/gdb/dist/sim/bfin/linux-targ-map.h new file mode 100644 index 000000000000..be60fec275f8 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/linux-targ-map.h @@ -0,0 +1,1996 @@ +#if 0 /* Auto generated: sh ./targ-linux.h + +sed -n '1,/^#endif/p' targ-linux.h +echo + +echo '#include ' | \ +bfin-uclinux-gcc -E -dD -P - | \ +sed -r -n \ + -e '1istatic CB_TARGET_DEFS_MAP cb_linux_syscall_map[] = {' \ + -e '$i\ \ { -1, -1 }\n};' \ + -e '/#define __NR_/{s:^.* __NR_(.*) (.*):#ifdef CB_SYS_\1\n# define TARGET_LINUX_SYS_\1 \2\n { CB_SYS_\1, TARGET_LINUX_SYS_\1 },\n#endif:;p;}' +echo + +echo '#include ' | \ +bfin-uclinux-gcc -E -dD -P - | \ +sed -r -n \ + -e '1istatic CB_TARGET_DEFS_MAP cb_linux_errno_map[] = {' \ + -e '$i\ \ { 0, 0 }\n};' \ + -e '/#define E.* [0-9]/{s:^.* (E.*) (.*):#ifdef \1\n# define TARGET_LINUX_\1 \2\n { \1, TARGET_LINUX_\1 },\n#endif:;p;}' +echo + +echo '#include ' | \ +bfin-uclinux-gcc -E -dD -P - | \ +sed -r -n \ + -e '1istatic CB_TARGET_DEFS_MAP cb_linux_open_map[] = {' \ + -e '$i\ \ { -1, -1 }\n};' \ + -e '/#define O.* [0-9]/{s:^.* (O_.*) (.*):#ifdef \1\n# define TARGET_LINUX_\1 \2\n { \1, TARGET_LINUX_\1 },\n#endif:;p;}' +echo + +# XXX: nothing uses this ? +echo '#include ' | \ +bfin-uclinux-gcc -E -dD -P - | \ +sed -r -n \ + -e '1istatic CB_TARGET_DEFS_MAP cb_linux_signal_map[] = {' \ + -e '$i\ \ { -1, -1 }\n};' \ + -e '/#define SIG.* [0-9]+$/{s:^.* (SIG.*) (.*):#ifdef \1\n# define TARGET_LINUX_\1 \2\n { \1, TARGET_LINUX_\1 },\n#endif:;p;}' + +exit 0 +*/ +#endif + +static CB_TARGET_DEFS_MAP cb_linux_syscall_map[] = +{ +#ifdef CB_SYS_restart_syscall +# define TARGET_LINUX_SYS_restart_syscall 0 + { CB_SYS_restart_syscall, TARGET_LINUX_SYS_restart_syscall }, +#endif +#ifdef CB_SYS_exit +# define TARGET_LINUX_SYS_exit 1 + { CB_SYS_exit, TARGET_LINUX_SYS_exit }, +#endif +#ifdef CB_SYS_fork +# define TARGET_LINUX_SYS_fork 2 + { CB_SYS_fork, TARGET_LINUX_SYS_fork }, +#endif +#ifdef CB_SYS_read +# define TARGET_LINUX_SYS_read 3 + { CB_SYS_read, TARGET_LINUX_SYS_read }, +#endif +#ifdef CB_SYS_write +# define TARGET_LINUX_SYS_write 4 + { CB_SYS_write, TARGET_LINUX_SYS_write }, +#endif +#ifdef CB_SYS_open +# define TARGET_LINUX_SYS_open 5 + { CB_SYS_open, TARGET_LINUX_SYS_open }, +#endif +#ifdef CB_SYS_close +# define TARGET_LINUX_SYS_close 6 + { CB_SYS_close, TARGET_LINUX_SYS_close }, +#endif +#ifdef CB_SYS_creat +# define TARGET_LINUX_SYS_creat 8 + { CB_SYS_creat, TARGET_LINUX_SYS_creat }, +#endif +#ifdef CB_SYS_link +# define TARGET_LINUX_SYS_link 9 + { CB_SYS_link, TARGET_LINUX_SYS_link }, +#endif +#ifdef CB_SYS_unlink +# define TARGET_LINUX_SYS_unlink 10 + { CB_SYS_unlink, TARGET_LINUX_SYS_unlink }, +#endif +#ifdef CB_SYS_execve +# define TARGET_LINUX_SYS_execve 11 + { CB_SYS_execve, TARGET_LINUX_SYS_execve }, +#endif +#ifdef CB_SYS_chdir +# define TARGET_LINUX_SYS_chdir 12 + { CB_SYS_chdir, TARGET_LINUX_SYS_chdir }, +#endif +#ifdef CB_SYS_time +# define TARGET_LINUX_SYS_time 13 + { CB_SYS_time, TARGET_LINUX_SYS_time }, +#endif +#ifdef CB_SYS_mknod +# define TARGET_LINUX_SYS_mknod 14 + { CB_SYS_mknod, TARGET_LINUX_SYS_mknod }, +#endif +#ifdef CB_SYS_chmod +# define TARGET_LINUX_SYS_chmod 15 + { CB_SYS_chmod, TARGET_LINUX_SYS_chmod }, +#endif +#ifdef CB_SYS_chown +# define TARGET_LINUX_SYS_chown 16 + { CB_SYS_chown, TARGET_LINUX_SYS_chown }, +#endif +#ifdef CB_SYS_lseek +# define TARGET_LINUX_SYS_lseek 19 + { CB_SYS_lseek, TARGET_LINUX_SYS_lseek }, +#endif +#ifdef CB_SYS_getpid +# define TARGET_LINUX_SYS_getpid 20 + { CB_SYS_getpid, TARGET_LINUX_SYS_getpid }, +#endif +#ifdef CB_SYS_mount +# define TARGET_LINUX_SYS_mount 21 + { CB_SYS_mount, TARGET_LINUX_SYS_mount }, +#endif +#ifdef CB_SYS_setuid +# define TARGET_LINUX_SYS_setuid 23 + { CB_SYS_setuid, TARGET_LINUX_SYS_setuid }, +#endif +#ifdef CB_SYS_getuid +# define TARGET_LINUX_SYS_getuid 24 + { CB_SYS_getuid, TARGET_LINUX_SYS_getuid }, +#endif +#ifdef CB_SYS_stime +# define TARGET_LINUX_SYS_stime 25 + { CB_SYS_stime, TARGET_LINUX_SYS_stime }, +#endif +#ifdef CB_SYS_ptrace +# define TARGET_LINUX_SYS_ptrace 26 + { CB_SYS_ptrace, TARGET_LINUX_SYS_ptrace }, +#endif +#ifdef CB_SYS_alarm +# define TARGET_LINUX_SYS_alarm 27 + { CB_SYS_alarm, TARGET_LINUX_SYS_alarm }, +#endif +#ifdef CB_SYS_pause +# define TARGET_LINUX_SYS_pause 29 + { CB_SYS_pause, TARGET_LINUX_SYS_pause }, +#endif +#ifdef CB_SYS_access +# define TARGET_LINUX_SYS_access 33 + { CB_SYS_access, TARGET_LINUX_SYS_access }, +#endif +#ifdef CB_SYS_nice +# define TARGET_LINUX_SYS_nice 34 + { CB_SYS_nice, TARGET_LINUX_SYS_nice }, +#endif +#ifdef CB_SYS_sync +# define TARGET_LINUX_SYS_sync 36 + { CB_SYS_sync, TARGET_LINUX_SYS_sync }, +#endif +#ifdef CB_SYS_kill +# define TARGET_LINUX_SYS_kill 37 + { CB_SYS_kill, TARGET_LINUX_SYS_kill }, +#endif +#ifdef CB_SYS_rename +# define TARGET_LINUX_SYS_rename 38 + { CB_SYS_rename, TARGET_LINUX_SYS_rename }, +#endif +#ifdef CB_SYS_mkdir +# define TARGET_LINUX_SYS_mkdir 39 + { CB_SYS_mkdir, TARGET_LINUX_SYS_mkdir }, +#endif +#ifdef CB_SYS_rmdir +# define TARGET_LINUX_SYS_rmdir 40 + { CB_SYS_rmdir, TARGET_LINUX_SYS_rmdir }, +#endif +#ifdef CB_SYS_dup +# define TARGET_LINUX_SYS_dup 41 + { CB_SYS_dup, TARGET_LINUX_SYS_dup }, +#endif +#ifdef CB_SYS_pipe +# define TARGET_LINUX_SYS_pipe 42 + { CB_SYS_pipe, TARGET_LINUX_SYS_pipe }, +#endif +#ifdef CB_SYS_times +# define TARGET_LINUX_SYS_times 43 + { CB_SYS_times, TARGET_LINUX_SYS_times }, +#endif +#ifdef CB_SYS_brk +# define TARGET_LINUX_SYS_brk 45 + { CB_SYS_brk, TARGET_LINUX_SYS_brk }, +#endif +#ifdef CB_SYS_setgid +# define TARGET_LINUX_SYS_setgid 46 + { CB_SYS_setgid, TARGET_LINUX_SYS_setgid }, +#endif +#ifdef CB_SYS_getgid +# define TARGET_LINUX_SYS_getgid 47 + { CB_SYS_getgid, TARGET_LINUX_SYS_getgid }, +#endif +#ifdef CB_SYS_geteuid +# define TARGET_LINUX_SYS_geteuid 49 + { CB_SYS_geteuid, TARGET_LINUX_SYS_geteuid }, +#endif +#ifdef CB_SYS_getegid +# define TARGET_LINUX_SYS_getegid 50 + { CB_SYS_getegid, TARGET_LINUX_SYS_getegid }, +#endif +#ifdef CB_SYS_acct +# define TARGET_LINUX_SYS_acct 51 + { CB_SYS_acct, TARGET_LINUX_SYS_acct }, +#endif +#ifdef CB_SYS_umount2 +# define TARGET_LINUX_SYS_umount2 52 + { CB_SYS_umount2, TARGET_LINUX_SYS_umount2 }, +#endif +#ifdef CB_SYS_ioctl +# define TARGET_LINUX_SYS_ioctl 54 + { CB_SYS_ioctl, TARGET_LINUX_SYS_ioctl }, +#endif +#ifdef CB_SYS_fcntl +# define TARGET_LINUX_SYS_fcntl 55 + { CB_SYS_fcntl, TARGET_LINUX_SYS_fcntl }, +#endif +#ifdef CB_SYS_setpgid +# define TARGET_LINUX_SYS_setpgid 57 + { CB_SYS_setpgid, TARGET_LINUX_SYS_setpgid }, +#endif +#ifdef CB_SYS_umask +# define TARGET_LINUX_SYS_umask 60 + { CB_SYS_umask, TARGET_LINUX_SYS_umask }, +#endif +#ifdef CB_SYS_chroot +# define TARGET_LINUX_SYS_chroot 61 + { CB_SYS_chroot, TARGET_LINUX_SYS_chroot }, +#endif +#ifdef CB_SYS_ustat +# define TARGET_LINUX_SYS_ustat 62 + { CB_SYS_ustat, TARGET_LINUX_SYS_ustat }, +#endif +#ifdef CB_SYS_dup2 +# define TARGET_LINUX_SYS_dup2 63 + { CB_SYS_dup2, TARGET_LINUX_SYS_dup2 }, +#endif +#ifdef CB_SYS_getppid +# define TARGET_LINUX_SYS_getppid 64 + { CB_SYS_getppid, TARGET_LINUX_SYS_getppid }, +#endif +#ifdef CB_SYS_getpgrp +# define TARGET_LINUX_SYS_getpgrp 65 + { CB_SYS_getpgrp, TARGET_LINUX_SYS_getpgrp }, +#endif +#ifdef CB_SYS_setsid +# define TARGET_LINUX_SYS_setsid 66 + { CB_SYS_setsid, TARGET_LINUX_SYS_setsid }, +#endif +#ifdef CB_SYS_sgetmask +# define TARGET_LINUX_SYS_sgetmask 68 + { CB_SYS_sgetmask, TARGET_LINUX_SYS_sgetmask }, +#endif +#ifdef CB_SYS_ssetmask +# define TARGET_LINUX_SYS_ssetmask 69 + { CB_SYS_ssetmask, TARGET_LINUX_SYS_ssetmask }, +#endif +#ifdef CB_SYS_setreuid +# define TARGET_LINUX_SYS_setreuid 70 + { CB_SYS_setreuid, TARGET_LINUX_SYS_setreuid }, +#endif +#ifdef CB_SYS_setregid +# define TARGET_LINUX_SYS_setregid 71 + { CB_SYS_setregid, TARGET_LINUX_SYS_setregid }, +#endif +#ifdef CB_SYS_sethostname +# define TARGET_LINUX_SYS_sethostname 74 + { CB_SYS_sethostname, TARGET_LINUX_SYS_sethostname }, +#endif +#ifdef CB_SYS_setrlimit +# define TARGET_LINUX_SYS_setrlimit 75 + { CB_SYS_setrlimit, TARGET_LINUX_SYS_setrlimit }, +#endif +#ifdef CB_SYS_getrusage +# define TARGET_LINUX_SYS_getrusage 77 + { CB_SYS_getrusage, TARGET_LINUX_SYS_getrusage }, +#endif +#ifdef CB_SYS_gettimeofday +# define TARGET_LINUX_SYS_gettimeofday 78 + { CB_SYS_gettimeofday, TARGET_LINUX_SYS_gettimeofday }, +#endif +#ifdef CB_SYS_settimeofday +# define TARGET_LINUX_SYS_settimeofday 79 + { CB_SYS_settimeofday, TARGET_LINUX_SYS_settimeofday }, +#endif +#ifdef CB_SYS_getgroups +# define TARGET_LINUX_SYS_getgroups 80 + { CB_SYS_getgroups, TARGET_LINUX_SYS_getgroups }, +#endif +#ifdef CB_SYS_setgroups +# define TARGET_LINUX_SYS_setgroups 81 + { CB_SYS_setgroups, TARGET_LINUX_SYS_setgroups }, +#endif +#ifdef CB_SYS_symlink +# define TARGET_LINUX_SYS_symlink 83 + { CB_SYS_symlink, TARGET_LINUX_SYS_symlink }, +#endif +#ifdef CB_SYS_readlink +# define TARGET_LINUX_SYS_readlink 85 + { CB_SYS_readlink, TARGET_LINUX_SYS_readlink }, +#endif +#ifdef CB_SYS_reboot +# define TARGET_LINUX_SYS_reboot 88 + { CB_SYS_reboot, TARGET_LINUX_SYS_reboot }, +#endif +#ifdef CB_SYS_munmap +# define TARGET_LINUX_SYS_munmap 91 + { CB_SYS_munmap, TARGET_LINUX_SYS_munmap }, +#endif +#ifdef CB_SYS_truncate +# define TARGET_LINUX_SYS_truncate 92 + { CB_SYS_truncate, TARGET_LINUX_SYS_truncate }, +#endif +#ifdef CB_SYS_ftruncate +# define TARGET_LINUX_SYS_ftruncate 93 + { CB_SYS_ftruncate, TARGET_LINUX_SYS_ftruncate }, +#endif +#ifdef CB_SYS_fchmod +# define TARGET_LINUX_SYS_fchmod 94 + { CB_SYS_fchmod, TARGET_LINUX_SYS_fchmod }, +#endif +#ifdef CB_SYS_fchown +# define TARGET_LINUX_SYS_fchown 95 + { CB_SYS_fchown, TARGET_LINUX_SYS_fchown }, +#endif +#ifdef CB_SYS_getpriority +# define TARGET_LINUX_SYS_getpriority 96 + { CB_SYS_getpriority, TARGET_LINUX_SYS_getpriority }, +#endif +#ifdef CB_SYS_setpriority +# define TARGET_LINUX_SYS_setpriority 97 + { CB_SYS_setpriority, TARGET_LINUX_SYS_setpriority }, +#endif +#ifdef CB_SYS_statfs +# define TARGET_LINUX_SYS_statfs 99 + { CB_SYS_statfs, TARGET_LINUX_SYS_statfs }, +#endif +#ifdef CB_SYS_fstatfs +# define TARGET_LINUX_SYS_fstatfs 100 + { CB_SYS_fstatfs, TARGET_LINUX_SYS_fstatfs }, +#endif +#ifdef CB_SYS_syslog +# define TARGET_LINUX_SYS_syslog 103 + { CB_SYS_syslog, TARGET_LINUX_SYS_syslog }, +#endif +#ifdef CB_SYS_setitimer +# define TARGET_LINUX_SYS_setitimer 104 + { CB_SYS_setitimer, TARGET_LINUX_SYS_setitimer }, +#endif +#ifdef CB_SYS_getitimer +# define TARGET_LINUX_SYS_getitimer 105 + { CB_SYS_getitimer, TARGET_LINUX_SYS_getitimer }, +#endif +#ifdef CB_SYS_stat +# define TARGET_LINUX_SYS_stat 106 + { CB_SYS_stat, TARGET_LINUX_SYS_stat }, +#endif +#ifdef CB_SYS_lstat +# define TARGET_LINUX_SYS_lstat 107 + { CB_SYS_lstat, TARGET_LINUX_SYS_lstat }, +#endif +#ifdef CB_SYS_fstat +# define TARGET_LINUX_SYS_fstat 108 + { CB_SYS_fstat, TARGET_LINUX_SYS_fstat }, +#endif +#ifdef CB_SYS_vhangup +# define TARGET_LINUX_SYS_vhangup 111 + { CB_SYS_vhangup, TARGET_LINUX_SYS_vhangup }, +#endif +#ifdef CB_SYS_wait4 +# define TARGET_LINUX_SYS_wait4 114 + { CB_SYS_wait4, TARGET_LINUX_SYS_wait4 }, +#endif +#ifdef CB_SYS_sysinfo +# define TARGET_LINUX_SYS_sysinfo 116 + { CB_SYS_sysinfo, TARGET_LINUX_SYS_sysinfo }, +#endif +#ifdef CB_SYS_fsync +# define TARGET_LINUX_SYS_fsync 118 + { CB_SYS_fsync, TARGET_LINUX_SYS_fsync }, +#endif +#ifdef CB_SYS_clone +# define TARGET_LINUX_SYS_clone 120 + { CB_SYS_clone, TARGET_LINUX_SYS_clone }, +#endif +#ifdef CB_SYS_setdomainname +# define TARGET_LINUX_SYS_setdomainname 121 + { CB_SYS_setdomainname, TARGET_LINUX_SYS_setdomainname }, +#endif +#ifdef CB_SYS_uname +# define TARGET_LINUX_SYS_uname 122 + { CB_SYS_uname, TARGET_LINUX_SYS_uname }, +#endif +#ifdef CB_SYS_adjtimex +# define TARGET_LINUX_SYS_adjtimex 124 + { CB_SYS_adjtimex, TARGET_LINUX_SYS_adjtimex }, +#endif +#ifdef CB_SYS_mprotect +# define TARGET_LINUX_SYS_mprotect 125 + { CB_SYS_mprotect, TARGET_LINUX_SYS_mprotect }, +#endif +#ifdef CB_SYS_init_module +# define TARGET_LINUX_SYS_init_module 128 + { CB_SYS_init_module, TARGET_LINUX_SYS_init_module }, +#endif +#ifdef CB_SYS_delete_module +# define TARGET_LINUX_SYS_delete_module 129 + { CB_SYS_delete_module, TARGET_LINUX_SYS_delete_module }, +#endif +#ifdef CB_SYS_quotactl +# define TARGET_LINUX_SYS_quotactl 131 + { CB_SYS_quotactl, TARGET_LINUX_SYS_quotactl }, +#endif +#ifdef CB_SYS_getpgid +# define TARGET_LINUX_SYS_getpgid 132 + { CB_SYS_getpgid, TARGET_LINUX_SYS_getpgid }, +#endif +#ifdef CB_SYS_fchdir +# define TARGET_LINUX_SYS_fchdir 133 + { CB_SYS_fchdir, TARGET_LINUX_SYS_fchdir }, +#endif +#ifdef CB_SYS_bdflush +# define TARGET_LINUX_SYS_bdflush 134 + { CB_SYS_bdflush, TARGET_LINUX_SYS_bdflush }, +#endif +#ifdef CB_SYS_personality +# define TARGET_LINUX_SYS_personality 136 + { CB_SYS_personality, TARGET_LINUX_SYS_personality }, +#endif +#ifdef CB_SYS_setfsuid +# define TARGET_LINUX_SYS_setfsuid 138 + { CB_SYS_setfsuid, TARGET_LINUX_SYS_setfsuid }, +#endif +#ifdef CB_SYS_setfsgid +# define TARGET_LINUX_SYS_setfsgid 139 + { CB_SYS_setfsgid, TARGET_LINUX_SYS_setfsgid }, +#endif +#ifdef CB_SYS__llseek +# define TARGET_LINUX_SYS__llseek 140 + { CB_SYS__llseek, TARGET_LINUX_SYS__llseek }, +#endif +#ifdef CB_SYS_getdents +# define TARGET_LINUX_SYS_getdents 141 + { CB_SYS_getdents, TARGET_LINUX_SYS_getdents }, +#endif +#ifdef CB_SYS_flock +# define TARGET_LINUX_SYS_flock 143 + { CB_SYS_flock, TARGET_LINUX_SYS_flock }, +#endif +#ifdef CB_SYS_readv +# define TARGET_LINUX_SYS_readv 145 + { CB_SYS_readv, TARGET_LINUX_SYS_readv }, +#endif +#ifdef CB_SYS_writev +# define TARGET_LINUX_SYS_writev 146 + { CB_SYS_writev, TARGET_LINUX_SYS_writev }, +#endif +#ifdef CB_SYS_getsid +# define TARGET_LINUX_SYS_getsid 147 + { CB_SYS_getsid, TARGET_LINUX_SYS_getsid }, +#endif +#ifdef CB_SYS_fdatasync +# define TARGET_LINUX_SYS_fdatasync 148 + { CB_SYS_fdatasync, TARGET_LINUX_SYS_fdatasync }, +#endif +#ifdef CB_SYS__sysctl +# define TARGET_LINUX_SYS__sysctl 149 + { CB_SYS__sysctl, TARGET_LINUX_SYS__sysctl }, +#endif +#ifdef CB_SYS_sched_setparam +# define TARGET_LINUX_SYS_sched_setparam 154 + { CB_SYS_sched_setparam, TARGET_LINUX_SYS_sched_setparam }, +#endif +#ifdef CB_SYS_sched_getparam +# define TARGET_LINUX_SYS_sched_getparam 155 + { CB_SYS_sched_getparam, TARGET_LINUX_SYS_sched_getparam }, +#endif +#ifdef CB_SYS_sched_setscheduler +# define TARGET_LINUX_SYS_sched_setscheduler 156 + { CB_SYS_sched_setscheduler, TARGET_LINUX_SYS_sched_setscheduler }, +#endif +#ifdef CB_SYS_sched_getscheduler +# define TARGET_LINUX_SYS_sched_getscheduler 157 + { CB_SYS_sched_getscheduler, TARGET_LINUX_SYS_sched_getscheduler }, +#endif +#ifdef CB_SYS_sched_yield +# define TARGET_LINUX_SYS_sched_yield 158 + { CB_SYS_sched_yield, TARGET_LINUX_SYS_sched_yield }, +#endif +#ifdef CB_SYS_sched_get_priority_max +# define TARGET_LINUX_SYS_sched_get_priority_max 159 + { CB_SYS_sched_get_priority_max, TARGET_LINUX_SYS_sched_get_priority_max }, +#endif +#ifdef CB_SYS_sched_get_priority_min +# define TARGET_LINUX_SYS_sched_get_priority_min 160 + { CB_SYS_sched_get_priority_min, TARGET_LINUX_SYS_sched_get_priority_min }, +#endif +#ifdef CB_SYS_sched_rr_get_interval +# define TARGET_LINUX_SYS_sched_rr_get_interval 161 + { CB_SYS_sched_rr_get_interval, TARGET_LINUX_SYS_sched_rr_get_interval }, +#endif +#ifdef CB_SYS_nanosleep +# define TARGET_LINUX_SYS_nanosleep 162 + { CB_SYS_nanosleep, TARGET_LINUX_SYS_nanosleep }, +#endif +#ifdef CB_SYS_mremap +# define TARGET_LINUX_SYS_mremap 163 + { CB_SYS_mremap, TARGET_LINUX_SYS_mremap }, +#endif +#ifdef CB_SYS_setresuid +# define TARGET_LINUX_SYS_setresuid 164 + { CB_SYS_setresuid, TARGET_LINUX_SYS_setresuid }, +#endif +#ifdef CB_SYS_getresuid +# define TARGET_LINUX_SYS_getresuid 165 + { CB_SYS_getresuid, TARGET_LINUX_SYS_getresuid }, +#endif +#ifdef CB_SYS_nfsservctl +# define TARGET_LINUX_SYS_nfsservctl 169 + { CB_SYS_nfsservctl, TARGET_LINUX_SYS_nfsservctl }, +#endif +#ifdef CB_SYS_setresgid +# define TARGET_LINUX_SYS_setresgid 170 + { CB_SYS_setresgid, TARGET_LINUX_SYS_setresgid }, +#endif +#ifdef CB_SYS_getresgid +# define TARGET_LINUX_SYS_getresgid 171 + { CB_SYS_getresgid, TARGET_LINUX_SYS_getresgid }, +#endif +#ifdef CB_SYS_prctl +# define TARGET_LINUX_SYS_prctl 172 + { CB_SYS_prctl, TARGET_LINUX_SYS_prctl }, +#endif +#ifdef CB_SYS_rt_sigreturn +# define TARGET_LINUX_SYS_rt_sigreturn 173 + { CB_SYS_rt_sigreturn, TARGET_LINUX_SYS_rt_sigreturn }, +#endif +#ifdef CB_SYS_rt_sigaction +# define TARGET_LINUX_SYS_rt_sigaction 174 + { CB_SYS_rt_sigaction, TARGET_LINUX_SYS_rt_sigaction }, +#endif +#ifdef CB_SYS_rt_sigprocmask +# define TARGET_LINUX_SYS_rt_sigprocmask 175 + { CB_SYS_rt_sigprocmask, TARGET_LINUX_SYS_rt_sigprocmask }, +#endif +#ifdef CB_SYS_rt_sigpending +# define TARGET_LINUX_SYS_rt_sigpending 176 + { CB_SYS_rt_sigpending, TARGET_LINUX_SYS_rt_sigpending }, +#endif +#ifdef CB_SYS_rt_sigtimedwait +# define TARGET_LINUX_SYS_rt_sigtimedwait 177 + { CB_SYS_rt_sigtimedwait, TARGET_LINUX_SYS_rt_sigtimedwait }, +#endif +#ifdef CB_SYS_rt_sigqueueinfo +# define TARGET_LINUX_SYS_rt_sigqueueinfo 178 + { CB_SYS_rt_sigqueueinfo, TARGET_LINUX_SYS_rt_sigqueueinfo }, +#endif +#ifdef CB_SYS_rt_sigsuspend +# define TARGET_LINUX_SYS_rt_sigsuspend 179 + { CB_SYS_rt_sigsuspend, TARGET_LINUX_SYS_rt_sigsuspend }, +#endif +#ifdef CB_SYS_pread +# define TARGET_LINUX_SYS_pread 180 + { CB_SYS_pread, TARGET_LINUX_SYS_pread }, +#endif +#ifdef CB_SYS_pwrite +# define TARGET_LINUX_SYS_pwrite 181 + { CB_SYS_pwrite, TARGET_LINUX_SYS_pwrite }, +#endif +#ifdef CB_SYS_lchown +# define TARGET_LINUX_SYS_lchown 182 + { CB_SYS_lchown, TARGET_LINUX_SYS_lchown }, +#endif +#ifdef CB_SYS_getcwd +# define TARGET_LINUX_SYS_getcwd 183 + { CB_SYS_getcwd, TARGET_LINUX_SYS_getcwd }, +#endif +#ifdef CB_SYS_capget +# define TARGET_LINUX_SYS_capget 184 + { CB_SYS_capget, TARGET_LINUX_SYS_capget }, +#endif +#ifdef CB_SYS_capset +# define TARGET_LINUX_SYS_capset 185 + { CB_SYS_capset, TARGET_LINUX_SYS_capset }, +#endif +#ifdef CB_SYS_sigaltstack +# define TARGET_LINUX_SYS_sigaltstack 186 + { CB_SYS_sigaltstack, TARGET_LINUX_SYS_sigaltstack }, +#endif +#ifdef CB_SYS_sendfile +# define TARGET_LINUX_SYS_sendfile 187 + { CB_SYS_sendfile, TARGET_LINUX_SYS_sendfile }, +#endif +#ifdef CB_SYS_vfork +# define TARGET_LINUX_SYS_vfork 190 + { CB_SYS_vfork, TARGET_LINUX_SYS_vfork }, +#endif +#ifdef CB_SYS_getrlimit +# define TARGET_LINUX_SYS_getrlimit 191 + { CB_SYS_getrlimit, TARGET_LINUX_SYS_getrlimit }, +#endif +#ifdef CB_SYS_mmap2 +# define TARGET_LINUX_SYS_mmap2 192 + { CB_SYS_mmap2, TARGET_LINUX_SYS_mmap2 }, +#endif +#ifdef CB_SYS_truncate64 +# define TARGET_LINUX_SYS_truncate64 193 + { CB_SYS_truncate64, TARGET_LINUX_SYS_truncate64 }, +#endif +#ifdef CB_SYS_ftruncate64 +# define TARGET_LINUX_SYS_ftruncate64 194 + { CB_SYS_ftruncate64, TARGET_LINUX_SYS_ftruncate64 }, +#endif +#ifdef CB_SYS_stat64 +# define TARGET_LINUX_SYS_stat64 195 + { CB_SYS_stat64, TARGET_LINUX_SYS_stat64 }, +#endif +#ifdef CB_SYS_lstat64 +# define TARGET_LINUX_SYS_lstat64 196 + { CB_SYS_lstat64, TARGET_LINUX_SYS_lstat64 }, +#endif +#ifdef CB_SYS_fstat64 +# define TARGET_LINUX_SYS_fstat64 197 + { CB_SYS_fstat64, TARGET_LINUX_SYS_fstat64 }, +#endif +#ifdef CB_SYS_chown32 +# define TARGET_LINUX_SYS_chown32 198 + { CB_SYS_chown32, TARGET_LINUX_SYS_chown32 }, +#endif +#ifdef CB_SYS_getuid32 +# define TARGET_LINUX_SYS_getuid32 199 + { CB_SYS_getuid32, TARGET_LINUX_SYS_getuid32 }, +#endif +#ifdef CB_SYS_getgid32 +# define TARGET_LINUX_SYS_getgid32 200 + { CB_SYS_getgid32, TARGET_LINUX_SYS_getgid32 }, +#endif +#ifdef CB_SYS_geteuid32 +# define TARGET_LINUX_SYS_geteuid32 201 + { CB_SYS_geteuid32, TARGET_LINUX_SYS_geteuid32 }, +#endif +#ifdef CB_SYS_getegid32 +# define TARGET_LINUX_SYS_getegid32 202 + { CB_SYS_getegid32, TARGET_LINUX_SYS_getegid32 }, +#endif +#ifdef CB_SYS_setreuid32 +# define TARGET_LINUX_SYS_setreuid32 203 + { CB_SYS_setreuid32, TARGET_LINUX_SYS_setreuid32 }, +#endif +#ifdef CB_SYS_setregid32 +# define TARGET_LINUX_SYS_setregid32 204 + { CB_SYS_setregid32, TARGET_LINUX_SYS_setregid32 }, +#endif +#ifdef CB_SYS_getgroups32 +# define TARGET_LINUX_SYS_getgroups32 205 + { CB_SYS_getgroups32, TARGET_LINUX_SYS_getgroups32 }, +#endif +#ifdef CB_SYS_setgroups32 +# define TARGET_LINUX_SYS_setgroups32 206 + { CB_SYS_setgroups32, TARGET_LINUX_SYS_setgroups32 }, +#endif +#ifdef CB_SYS_fchown32 +# define TARGET_LINUX_SYS_fchown32 207 + { CB_SYS_fchown32, TARGET_LINUX_SYS_fchown32 }, +#endif +#ifdef CB_SYS_setresuid32 +# define TARGET_LINUX_SYS_setresuid32 208 + { CB_SYS_setresuid32, TARGET_LINUX_SYS_setresuid32 }, +#endif +#ifdef CB_SYS_getresuid32 +# define TARGET_LINUX_SYS_getresuid32 209 + { CB_SYS_getresuid32, TARGET_LINUX_SYS_getresuid32 }, +#endif +#ifdef CB_SYS_setresgid32 +# define TARGET_LINUX_SYS_setresgid32 210 + { CB_SYS_setresgid32, TARGET_LINUX_SYS_setresgid32 }, +#endif +#ifdef CB_SYS_getresgid32 +# define TARGET_LINUX_SYS_getresgid32 211 + { CB_SYS_getresgid32, TARGET_LINUX_SYS_getresgid32 }, +#endif +#ifdef CB_SYS_lchown32 +# define TARGET_LINUX_SYS_lchown32 212 + { CB_SYS_lchown32, TARGET_LINUX_SYS_lchown32 }, +#endif +#ifdef CB_SYS_setuid32 +# define TARGET_LINUX_SYS_setuid32 213 + { CB_SYS_setuid32, TARGET_LINUX_SYS_setuid32 }, +#endif +#ifdef CB_SYS_setgid32 +# define TARGET_LINUX_SYS_setgid32 214 + { CB_SYS_setgid32, TARGET_LINUX_SYS_setgid32 }, +#endif +#ifdef CB_SYS_setfsuid32 +# define TARGET_LINUX_SYS_setfsuid32 215 + { CB_SYS_setfsuid32, TARGET_LINUX_SYS_setfsuid32 }, +#endif +#ifdef CB_SYS_setfsgid32 +# define TARGET_LINUX_SYS_setfsgid32 216 + { CB_SYS_setfsgid32, TARGET_LINUX_SYS_setfsgid32 }, +#endif +#ifdef CB_SYS_pivot_root +# define TARGET_LINUX_SYS_pivot_root 217 + { CB_SYS_pivot_root, TARGET_LINUX_SYS_pivot_root }, +#endif +#ifdef CB_SYS_getdents64 +# define TARGET_LINUX_SYS_getdents64 220 + { CB_SYS_getdents64, TARGET_LINUX_SYS_getdents64 }, +#endif +#ifdef CB_SYS_fcntl64 +# define TARGET_LINUX_SYS_fcntl64 221 + { CB_SYS_fcntl64, TARGET_LINUX_SYS_fcntl64 }, +#endif +#ifdef CB_SYS_gettid +# define TARGET_LINUX_SYS_gettid 224 + { CB_SYS_gettid, TARGET_LINUX_SYS_gettid }, +#endif +#ifdef CB_SYS_readahead +# define TARGET_LINUX_SYS_readahead 225 + { CB_SYS_readahead, TARGET_LINUX_SYS_readahead }, +#endif +#ifdef CB_SYS_setxattr +# define TARGET_LINUX_SYS_setxattr 226 + { CB_SYS_setxattr, TARGET_LINUX_SYS_setxattr }, +#endif +#ifdef CB_SYS_lsetxattr +# define TARGET_LINUX_SYS_lsetxattr 227 + { CB_SYS_lsetxattr, TARGET_LINUX_SYS_lsetxattr }, +#endif +#ifdef CB_SYS_fsetxattr +# define TARGET_LINUX_SYS_fsetxattr 228 + { CB_SYS_fsetxattr, TARGET_LINUX_SYS_fsetxattr }, +#endif +#ifdef CB_SYS_getxattr +# define TARGET_LINUX_SYS_getxattr 229 + { CB_SYS_getxattr, TARGET_LINUX_SYS_getxattr }, +#endif +#ifdef CB_SYS_lgetxattr +# define TARGET_LINUX_SYS_lgetxattr 230 + { CB_SYS_lgetxattr, TARGET_LINUX_SYS_lgetxattr }, +#endif +#ifdef CB_SYS_fgetxattr +# define TARGET_LINUX_SYS_fgetxattr 231 + { CB_SYS_fgetxattr, TARGET_LINUX_SYS_fgetxattr }, +#endif +#ifdef CB_SYS_listxattr +# define TARGET_LINUX_SYS_listxattr 232 + { CB_SYS_listxattr, TARGET_LINUX_SYS_listxattr }, +#endif +#ifdef CB_SYS_llistxattr +# define TARGET_LINUX_SYS_llistxattr 233 + { CB_SYS_llistxattr, TARGET_LINUX_SYS_llistxattr }, +#endif +#ifdef CB_SYS_flistxattr +# define TARGET_LINUX_SYS_flistxattr 234 + { CB_SYS_flistxattr, TARGET_LINUX_SYS_flistxattr }, +#endif +#ifdef CB_SYS_removexattr +# define TARGET_LINUX_SYS_removexattr 235 + { CB_SYS_removexattr, TARGET_LINUX_SYS_removexattr }, +#endif +#ifdef CB_SYS_lremovexattr +# define TARGET_LINUX_SYS_lremovexattr 236 + { CB_SYS_lremovexattr, TARGET_LINUX_SYS_lremovexattr }, +#endif +#ifdef CB_SYS_fremovexattr +# define TARGET_LINUX_SYS_fremovexattr 237 + { CB_SYS_fremovexattr, TARGET_LINUX_SYS_fremovexattr }, +#endif +#ifdef CB_SYS_tkill +# define TARGET_LINUX_SYS_tkill 238 + { CB_SYS_tkill, TARGET_LINUX_SYS_tkill }, +#endif +#ifdef CB_SYS_sendfile64 +# define TARGET_LINUX_SYS_sendfile64 239 + { CB_SYS_sendfile64, TARGET_LINUX_SYS_sendfile64 }, +#endif +#ifdef CB_SYS_futex +# define TARGET_LINUX_SYS_futex 240 + { CB_SYS_futex, TARGET_LINUX_SYS_futex }, +#endif +#ifdef CB_SYS_sched_setaffinity +# define TARGET_LINUX_SYS_sched_setaffinity 241 + { CB_SYS_sched_setaffinity, TARGET_LINUX_SYS_sched_setaffinity }, +#endif +#ifdef CB_SYS_sched_getaffinity +# define TARGET_LINUX_SYS_sched_getaffinity 242 + { CB_SYS_sched_getaffinity, TARGET_LINUX_SYS_sched_getaffinity }, +#endif +#ifdef CB_SYS_io_setup +# define TARGET_LINUX_SYS_io_setup 245 + { CB_SYS_io_setup, TARGET_LINUX_SYS_io_setup }, +#endif +#ifdef CB_SYS_io_destroy +# define TARGET_LINUX_SYS_io_destroy 246 + { CB_SYS_io_destroy, TARGET_LINUX_SYS_io_destroy }, +#endif +#ifdef CB_SYS_io_getevents +# define TARGET_LINUX_SYS_io_getevents 247 + { CB_SYS_io_getevents, TARGET_LINUX_SYS_io_getevents }, +#endif +#ifdef CB_SYS_io_submit +# define TARGET_LINUX_SYS_io_submit 248 + { CB_SYS_io_submit, TARGET_LINUX_SYS_io_submit }, +#endif +#ifdef CB_SYS_io_cancel +# define TARGET_LINUX_SYS_io_cancel 249 + { CB_SYS_io_cancel, TARGET_LINUX_SYS_io_cancel }, +#endif +#ifdef CB_SYS_exit_group +# define TARGET_LINUX_SYS_exit_group 252 + { CB_SYS_exit_group, TARGET_LINUX_SYS_exit_group }, +#endif +#ifdef CB_SYS_lookup_dcookie +# define TARGET_LINUX_SYS_lookup_dcookie 253 + { CB_SYS_lookup_dcookie, TARGET_LINUX_SYS_lookup_dcookie }, +#endif +#ifdef CB_SYS_bfin_spinlock +# define TARGET_LINUX_SYS_bfin_spinlock 254 + { CB_SYS_bfin_spinlock, TARGET_LINUX_SYS_bfin_spinlock }, +#endif +#ifdef CB_SYS_epoll_create +# define TARGET_LINUX_SYS_epoll_create 255 + { CB_SYS_epoll_create, TARGET_LINUX_SYS_epoll_create }, +#endif +#ifdef CB_SYS_epoll_ctl +# define TARGET_LINUX_SYS_epoll_ctl 256 + { CB_SYS_epoll_ctl, TARGET_LINUX_SYS_epoll_ctl }, +#endif +#ifdef CB_SYS_epoll_wait +# define TARGET_LINUX_SYS_epoll_wait 257 + { CB_SYS_epoll_wait, TARGET_LINUX_SYS_epoll_wait }, +#endif +#ifdef CB_SYS_set_tid_address +# define TARGET_LINUX_SYS_set_tid_address 259 + { CB_SYS_set_tid_address, TARGET_LINUX_SYS_set_tid_address }, +#endif +#ifdef CB_SYS_timer_create +# define TARGET_LINUX_SYS_timer_create 260 + { CB_SYS_timer_create, TARGET_LINUX_SYS_timer_create }, +#endif +#ifdef CB_SYS_timer_settime +# define TARGET_LINUX_SYS_timer_settime 261 + { CB_SYS_timer_settime, TARGET_LINUX_SYS_timer_settime }, +#endif +#ifdef CB_SYS_timer_gettime +# define TARGET_LINUX_SYS_timer_gettime 262 + { CB_SYS_timer_gettime, TARGET_LINUX_SYS_timer_gettime }, +#endif +#ifdef CB_SYS_timer_getoverrun +# define TARGET_LINUX_SYS_timer_getoverrun 263 + { CB_SYS_timer_getoverrun, TARGET_LINUX_SYS_timer_getoverrun }, +#endif +#ifdef CB_SYS_timer_delete +# define TARGET_LINUX_SYS_timer_delete 264 + { CB_SYS_timer_delete, TARGET_LINUX_SYS_timer_delete }, +#endif +#ifdef CB_SYS_clock_settime +# define TARGET_LINUX_SYS_clock_settime 265 + { CB_SYS_clock_settime, TARGET_LINUX_SYS_clock_settime }, +#endif +#ifdef CB_SYS_clock_gettime +# define TARGET_LINUX_SYS_clock_gettime 266 + { CB_SYS_clock_gettime, TARGET_LINUX_SYS_clock_gettime }, +#endif +#ifdef CB_SYS_clock_getres +# define TARGET_LINUX_SYS_clock_getres 267 + { CB_SYS_clock_getres, TARGET_LINUX_SYS_clock_getres }, +#endif +#ifdef CB_SYS_clock_nanosleep +# define TARGET_LINUX_SYS_clock_nanosleep 268 + { CB_SYS_clock_nanosleep, TARGET_LINUX_SYS_clock_nanosleep }, +#endif +#ifdef CB_SYS_statfs64 +# define TARGET_LINUX_SYS_statfs64 269 + { CB_SYS_statfs64, TARGET_LINUX_SYS_statfs64 }, +#endif +#ifdef CB_SYS_fstatfs64 +# define TARGET_LINUX_SYS_fstatfs64 270 + { CB_SYS_fstatfs64, TARGET_LINUX_SYS_fstatfs64 }, +#endif +#ifdef CB_SYS_tgkill +# define TARGET_LINUX_SYS_tgkill 271 + { CB_SYS_tgkill, TARGET_LINUX_SYS_tgkill }, +#endif +#ifdef CB_SYS_utimes +# define TARGET_LINUX_SYS_utimes 272 + { CB_SYS_utimes, TARGET_LINUX_SYS_utimes }, +#endif +#ifdef CB_SYS_fadvise64_64 +# define TARGET_LINUX_SYS_fadvise64_64 273 + { CB_SYS_fadvise64_64, TARGET_LINUX_SYS_fadvise64_64 }, +#endif +#ifdef CB_SYS_mq_open +# define TARGET_LINUX_SYS_mq_open 278 + { CB_SYS_mq_open, TARGET_LINUX_SYS_mq_open }, +#endif +#ifdef CB_SYS_mq_unlink +# define TARGET_LINUX_SYS_mq_unlink 279 + { CB_SYS_mq_unlink, TARGET_LINUX_SYS_mq_unlink }, +#endif +#ifdef CB_SYS_mq_timedsend +# define TARGET_LINUX_SYS_mq_timedsend 280 + { CB_SYS_mq_timedsend, TARGET_LINUX_SYS_mq_timedsend }, +#endif +#ifdef CB_SYS_mq_timedreceive +# define TARGET_LINUX_SYS_mq_timedreceive 281 + { CB_SYS_mq_timedreceive, TARGET_LINUX_SYS_mq_timedreceive }, +#endif +#ifdef CB_SYS_mq_notify +# define TARGET_LINUX_SYS_mq_notify 282 + { CB_SYS_mq_notify, TARGET_LINUX_SYS_mq_notify }, +#endif +#ifdef CB_SYS_mq_getsetattr +# define TARGET_LINUX_SYS_mq_getsetattr 283 + { CB_SYS_mq_getsetattr, TARGET_LINUX_SYS_mq_getsetattr }, +#endif +#ifdef CB_SYS_kexec_load +# define TARGET_LINUX_SYS_kexec_load 284 + { CB_SYS_kexec_load, TARGET_LINUX_SYS_kexec_load }, +#endif +#ifdef CB_SYS_waitid +# define TARGET_LINUX_SYS_waitid 285 + { CB_SYS_waitid, TARGET_LINUX_SYS_waitid }, +#endif +#ifdef CB_SYS_add_key +# define TARGET_LINUX_SYS_add_key 286 + { CB_SYS_add_key, TARGET_LINUX_SYS_add_key }, +#endif +#ifdef CB_SYS_request_key +# define TARGET_LINUX_SYS_request_key 287 + { CB_SYS_request_key, TARGET_LINUX_SYS_request_key }, +#endif +#ifdef CB_SYS_keyctl +# define TARGET_LINUX_SYS_keyctl 288 + { CB_SYS_keyctl, TARGET_LINUX_SYS_keyctl }, +#endif +#ifdef CB_SYS_ioprio_set +# define TARGET_LINUX_SYS_ioprio_set 289 + { CB_SYS_ioprio_set, TARGET_LINUX_SYS_ioprio_set }, +#endif +#ifdef CB_SYS_ioprio_get +# define TARGET_LINUX_SYS_ioprio_get 290 + { CB_SYS_ioprio_get, TARGET_LINUX_SYS_ioprio_get }, +#endif +#ifdef CB_SYS_inotify_init +# define TARGET_LINUX_SYS_inotify_init 291 + { CB_SYS_inotify_init, TARGET_LINUX_SYS_inotify_init }, +#endif +#ifdef CB_SYS_inotify_add_watch +# define TARGET_LINUX_SYS_inotify_add_watch 292 + { CB_SYS_inotify_add_watch, TARGET_LINUX_SYS_inotify_add_watch }, +#endif +#ifdef CB_SYS_inotify_rm_watch +# define TARGET_LINUX_SYS_inotify_rm_watch 293 + { CB_SYS_inotify_rm_watch, TARGET_LINUX_SYS_inotify_rm_watch }, +#endif +#ifdef CB_SYS_openat +# define TARGET_LINUX_SYS_openat 295 + { CB_SYS_openat, TARGET_LINUX_SYS_openat }, +#endif +#ifdef CB_SYS_mkdirat +# define TARGET_LINUX_SYS_mkdirat 296 + { CB_SYS_mkdirat, TARGET_LINUX_SYS_mkdirat }, +#endif +#ifdef CB_SYS_mknodat +# define TARGET_LINUX_SYS_mknodat 297 + { CB_SYS_mknodat, TARGET_LINUX_SYS_mknodat }, +#endif +#ifdef CB_SYS_fchownat +# define TARGET_LINUX_SYS_fchownat 298 + { CB_SYS_fchownat, TARGET_LINUX_SYS_fchownat }, +#endif +#ifdef CB_SYS_futimesat +# define TARGET_LINUX_SYS_futimesat 299 + { CB_SYS_futimesat, TARGET_LINUX_SYS_futimesat }, +#endif +#ifdef CB_SYS_fstatat64 +# define TARGET_LINUX_SYS_fstatat64 300 + { CB_SYS_fstatat64, TARGET_LINUX_SYS_fstatat64 }, +#endif +#ifdef CB_SYS_unlinkat +# define TARGET_LINUX_SYS_unlinkat 301 + { CB_SYS_unlinkat, TARGET_LINUX_SYS_unlinkat }, +#endif +#ifdef CB_SYS_renameat +# define TARGET_LINUX_SYS_renameat 302 + { CB_SYS_renameat, TARGET_LINUX_SYS_renameat }, +#endif +#ifdef CB_SYS_linkat +# define TARGET_LINUX_SYS_linkat 303 + { CB_SYS_linkat, TARGET_LINUX_SYS_linkat }, +#endif +#ifdef CB_SYS_symlinkat +# define TARGET_LINUX_SYS_symlinkat 304 + { CB_SYS_symlinkat, TARGET_LINUX_SYS_symlinkat }, +#endif +#ifdef CB_SYS_readlinkat +# define TARGET_LINUX_SYS_readlinkat 305 + { CB_SYS_readlinkat, TARGET_LINUX_SYS_readlinkat }, +#endif +#ifdef CB_SYS_fchmodat +# define TARGET_LINUX_SYS_fchmodat 306 + { CB_SYS_fchmodat, TARGET_LINUX_SYS_fchmodat }, +#endif +#ifdef CB_SYS_faccessat +# define TARGET_LINUX_SYS_faccessat 307 + { CB_SYS_faccessat, TARGET_LINUX_SYS_faccessat }, +#endif +#ifdef CB_SYS_pselect6 +# define TARGET_LINUX_SYS_pselect6 308 + { CB_SYS_pselect6, TARGET_LINUX_SYS_pselect6 }, +#endif +#ifdef CB_SYS_ppoll +# define TARGET_LINUX_SYS_ppoll 309 + { CB_SYS_ppoll, TARGET_LINUX_SYS_ppoll }, +#endif +#ifdef CB_SYS_unshare +# define TARGET_LINUX_SYS_unshare 310 + { CB_SYS_unshare, TARGET_LINUX_SYS_unshare }, +#endif +#ifdef CB_SYS_sram_alloc +# define TARGET_LINUX_SYS_sram_alloc 311 + { CB_SYS_sram_alloc, TARGET_LINUX_SYS_sram_alloc }, +#endif +#ifdef CB_SYS_sram_free +# define TARGET_LINUX_SYS_sram_free 312 + { CB_SYS_sram_free, TARGET_LINUX_SYS_sram_free }, +#endif +#ifdef CB_SYS_dma_memcpy +# define TARGET_LINUX_SYS_dma_memcpy 313 + { CB_SYS_dma_memcpy, TARGET_LINUX_SYS_dma_memcpy }, +#endif +#ifdef CB_SYS_accept +# define TARGET_LINUX_SYS_accept 314 + { CB_SYS_accept, TARGET_LINUX_SYS_accept }, +#endif +#ifdef CB_SYS_bind +# define TARGET_LINUX_SYS_bind 315 + { CB_SYS_bind, TARGET_LINUX_SYS_bind }, +#endif +#ifdef CB_SYS_connect +# define TARGET_LINUX_SYS_connect 316 + { CB_SYS_connect, TARGET_LINUX_SYS_connect }, +#endif +#ifdef CB_SYS_getpeername +# define TARGET_LINUX_SYS_getpeername 317 + { CB_SYS_getpeername, TARGET_LINUX_SYS_getpeername }, +#endif +#ifdef CB_SYS_getsockname +# define TARGET_LINUX_SYS_getsockname 318 + { CB_SYS_getsockname, TARGET_LINUX_SYS_getsockname }, +#endif +#ifdef CB_SYS_getsockopt +# define TARGET_LINUX_SYS_getsockopt 319 + { CB_SYS_getsockopt, TARGET_LINUX_SYS_getsockopt }, +#endif +#ifdef CB_SYS_listen +# define TARGET_LINUX_SYS_listen 320 + { CB_SYS_listen, TARGET_LINUX_SYS_listen }, +#endif +#ifdef CB_SYS_recv +# define TARGET_LINUX_SYS_recv 321 + { CB_SYS_recv, TARGET_LINUX_SYS_recv }, +#endif +#ifdef CB_SYS_recvfrom +# define TARGET_LINUX_SYS_recvfrom 322 + { CB_SYS_recvfrom, TARGET_LINUX_SYS_recvfrom }, +#endif +#ifdef CB_SYS_recvmsg +# define TARGET_LINUX_SYS_recvmsg 323 + { CB_SYS_recvmsg, TARGET_LINUX_SYS_recvmsg }, +#endif +#ifdef CB_SYS_send +# define TARGET_LINUX_SYS_send 324 + { CB_SYS_send, TARGET_LINUX_SYS_send }, +#endif +#ifdef CB_SYS_sendmsg +# define TARGET_LINUX_SYS_sendmsg 325 + { CB_SYS_sendmsg, TARGET_LINUX_SYS_sendmsg }, +#endif +#ifdef CB_SYS_sendto +# define TARGET_LINUX_SYS_sendto 326 + { CB_SYS_sendto, TARGET_LINUX_SYS_sendto }, +#endif +#ifdef CB_SYS_setsockopt +# define TARGET_LINUX_SYS_setsockopt 327 + { CB_SYS_setsockopt, TARGET_LINUX_SYS_setsockopt }, +#endif +#ifdef CB_SYS_shutdown +# define TARGET_LINUX_SYS_shutdown 328 + { CB_SYS_shutdown, TARGET_LINUX_SYS_shutdown }, +#endif +#ifdef CB_SYS_socket +# define TARGET_LINUX_SYS_socket 329 + { CB_SYS_socket, TARGET_LINUX_SYS_socket }, +#endif +#ifdef CB_SYS_socketpair +# define TARGET_LINUX_SYS_socketpair 330 + { CB_SYS_socketpair, TARGET_LINUX_SYS_socketpair }, +#endif +#ifdef CB_SYS_semctl +# define TARGET_LINUX_SYS_semctl 331 + { CB_SYS_semctl, TARGET_LINUX_SYS_semctl }, +#endif +#ifdef CB_SYS_semget +# define TARGET_LINUX_SYS_semget 332 + { CB_SYS_semget, TARGET_LINUX_SYS_semget }, +#endif +#ifdef CB_SYS_semop +# define TARGET_LINUX_SYS_semop 333 + { CB_SYS_semop, TARGET_LINUX_SYS_semop }, +#endif +#ifdef CB_SYS_msgctl +# define TARGET_LINUX_SYS_msgctl 334 + { CB_SYS_msgctl, TARGET_LINUX_SYS_msgctl }, +#endif +#ifdef CB_SYS_msgget +# define TARGET_LINUX_SYS_msgget 335 + { CB_SYS_msgget, TARGET_LINUX_SYS_msgget }, +#endif +#ifdef CB_SYS_msgrcv +# define TARGET_LINUX_SYS_msgrcv 336 + { CB_SYS_msgrcv, TARGET_LINUX_SYS_msgrcv }, +#endif +#ifdef CB_SYS_msgsnd +# define TARGET_LINUX_SYS_msgsnd 337 + { CB_SYS_msgsnd, TARGET_LINUX_SYS_msgsnd }, +#endif +#ifdef CB_SYS_shmat +# define TARGET_LINUX_SYS_shmat 338 + { CB_SYS_shmat, TARGET_LINUX_SYS_shmat }, +#endif +#ifdef CB_SYS_shmctl +# define TARGET_LINUX_SYS_shmctl 339 + { CB_SYS_shmctl, TARGET_LINUX_SYS_shmctl }, +#endif +#ifdef CB_SYS_shmdt +# define TARGET_LINUX_SYS_shmdt 340 + { CB_SYS_shmdt, TARGET_LINUX_SYS_shmdt }, +#endif +#ifdef CB_SYS_shmget +# define TARGET_LINUX_SYS_shmget 341 + { CB_SYS_shmget, TARGET_LINUX_SYS_shmget }, +#endif +#ifdef CB_SYS_splice +# define TARGET_LINUX_SYS_splice 342 + { CB_SYS_splice, TARGET_LINUX_SYS_splice }, +#endif +#ifdef CB_SYS_sync_file_range +# define TARGET_LINUX_SYS_sync_file_range 343 + { CB_SYS_sync_file_range, TARGET_LINUX_SYS_sync_file_range }, +#endif +#ifdef CB_SYS_tee +# define TARGET_LINUX_SYS_tee 344 + { CB_SYS_tee, TARGET_LINUX_SYS_tee }, +#endif +#ifdef CB_SYS_vmsplice +# define TARGET_LINUX_SYS_vmsplice 345 + { CB_SYS_vmsplice, TARGET_LINUX_SYS_vmsplice }, +#endif +#ifdef CB_SYS_epoll_pwait +# define TARGET_LINUX_SYS_epoll_pwait 346 + { CB_SYS_epoll_pwait, TARGET_LINUX_SYS_epoll_pwait }, +#endif +#ifdef CB_SYS_utimensat +# define TARGET_LINUX_SYS_utimensat 347 + { CB_SYS_utimensat, TARGET_LINUX_SYS_utimensat }, +#endif +#ifdef CB_SYS_signalfd +# define TARGET_LINUX_SYS_signalfd 348 + { CB_SYS_signalfd, TARGET_LINUX_SYS_signalfd }, +#endif +#ifdef CB_SYS_timerfd_create +# define TARGET_LINUX_SYS_timerfd_create 349 + { CB_SYS_timerfd_create, TARGET_LINUX_SYS_timerfd_create }, +#endif +#ifdef CB_SYS_eventfd +# define TARGET_LINUX_SYS_eventfd 350 + { CB_SYS_eventfd, TARGET_LINUX_SYS_eventfd }, +#endif +#ifdef CB_SYS_pread64 +# define TARGET_LINUX_SYS_pread64 351 + { CB_SYS_pread64, TARGET_LINUX_SYS_pread64 }, +#endif +#ifdef CB_SYS_pwrite64 +# define TARGET_LINUX_SYS_pwrite64 352 + { CB_SYS_pwrite64, TARGET_LINUX_SYS_pwrite64 }, +#endif +#ifdef CB_SYS_fadvise64 +# define TARGET_LINUX_SYS_fadvise64 353 + { CB_SYS_fadvise64, TARGET_LINUX_SYS_fadvise64 }, +#endif +#ifdef CB_SYS_set_robust_list +# define TARGET_LINUX_SYS_set_robust_list 354 + { CB_SYS_set_robust_list, TARGET_LINUX_SYS_set_robust_list }, +#endif +#ifdef CB_SYS_get_robust_list +# define TARGET_LINUX_SYS_get_robust_list 355 + { CB_SYS_get_robust_list, TARGET_LINUX_SYS_get_robust_list }, +#endif +#ifdef CB_SYS_fallocate +# define TARGET_LINUX_SYS_fallocate 356 + { CB_SYS_fallocate, TARGET_LINUX_SYS_fallocate }, +#endif +#ifdef CB_SYS_semtimedop +# define TARGET_LINUX_SYS_semtimedop 357 + { CB_SYS_semtimedop, TARGET_LINUX_SYS_semtimedop }, +#endif +#ifdef CB_SYS_timerfd_settime +# define TARGET_LINUX_SYS_timerfd_settime 358 + { CB_SYS_timerfd_settime, TARGET_LINUX_SYS_timerfd_settime }, +#endif +#ifdef CB_SYS_timerfd_gettime +# define TARGET_LINUX_SYS_timerfd_gettime 359 + { CB_SYS_timerfd_gettime, TARGET_LINUX_SYS_timerfd_gettime }, +#endif +#ifdef CB_SYS_signalfd4 +# define TARGET_LINUX_SYS_signalfd4 360 + { CB_SYS_signalfd4, TARGET_LINUX_SYS_signalfd4 }, +#endif +#ifdef CB_SYS_eventfd2 +# define TARGET_LINUX_SYS_eventfd2 361 + { CB_SYS_eventfd2, TARGET_LINUX_SYS_eventfd2 }, +#endif +#ifdef CB_SYS_epoll_create1 +# define TARGET_LINUX_SYS_epoll_create1 362 + { CB_SYS_epoll_create1, TARGET_LINUX_SYS_epoll_create1 }, +#endif +#ifdef CB_SYS_dup3 +# define TARGET_LINUX_SYS_dup3 363 + { CB_SYS_dup3, TARGET_LINUX_SYS_dup3 }, +#endif +#ifdef CB_SYS_pipe2 +# define TARGET_LINUX_SYS_pipe2 364 + { CB_SYS_pipe2, TARGET_LINUX_SYS_pipe2 }, +#endif +#ifdef CB_SYS_inotify_init1 +# define TARGET_LINUX_SYS_inotify_init1 365 + { CB_SYS_inotify_init1, TARGET_LINUX_SYS_inotify_init1 }, +#endif +#ifdef CB_SYS_preadv +# define TARGET_LINUX_SYS_preadv 366 + { CB_SYS_preadv, TARGET_LINUX_SYS_preadv }, +#endif +#ifdef CB_SYS_pwritev +# define TARGET_LINUX_SYS_pwritev 367 + { CB_SYS_pwritev, TARGET_LINUX_SYS_pwritev }, +#endif +#ifdef CB_SYS_rt_tgsigqueueinfo +# define TARGET_LINUX_SYS_rt_tgsigqueueinfo 368 + { CB_SYS_rt_tgsigqueueinfo, TARGET_LINUX_SYS_rt_tgsigqueueinfo }, +#endif +#ifdef CB_SYS_perf_event_open +# define TARGET_LINUX_SYS_perf_event_open 369 + { CB_SYS_perf_event_open, TARGET_LINUX_SYS_perf_event_open }, +#endif +#ifdef CB_SYS_recvmmsg +# define TARGET_LINUX_SYS_recvmmsg 370 + { CB_SYS_recvmmsg, TARGET_LINUX_SYS_recvmmsg }, +#endif +#ifdef CB_SYS_fanotify_init +# define TARGET_LINUX_SYS_fanotify_init 371 + { CB_SYS_fanotify_init, TARGET_LINUX_SYS_fanotify_init }, +#endif +#ifdef CB_SYS_fanotify_mark +# define TARGET_LINUX_SYS_fanotify_mark 372 + { CB_SYS_fanotify_mark, TARGET_LINUX_SYS_fanotify_mark }, +#endif +#ifdef CB_SYS_prlimit64 +# define TARGET_LINUX_SYS_prlimit64 373 + { CB_SYS_prlimit64, TARGET_LINUX_SYS_prlimit64 }, +#endif +#ifdef CB_SYS_cacheflush +# define TARGET_LINUX_SYS_cacheflush 374 + { CB_SYS_cacheflush, TARGET_LINUX_SYS_cacheflush }, +#endif +#ifdef CB_SYS_syscall +# define TARGET_LINUX_SYS_syscall 375 + { CB_SYS_syscall, TARGET_LINUX_SYS_syscall }, +#endif + { -1, -1 } +}; + +static CB_TARGET_DEFS_MAP cb_linux_errno_map[] = +{ +#ifdef EPERM +# define TARGET_LINUX_EPERM 1 + { EPERM, TARGET_LINUX_EPERM }, +#endif +#ifdef ENOENT +# define TARGET_LINUX_ENOENT 2 + { ENOENT, TARGET_LINUX_ENOENT }, +#endif +#ifdef ESRCH +# define TARGET_LINUX_ESRCH 3 + { ESRCH, TARGET_LINUX_ESRCH }, +#endif +#ifdef EINTR +# define TARGET_LINUX_EINTR 4 + { EINTR, TARGET_LINUX_EINTR }, +#endif +#ifdef EIO +# define TARGET_LINUX_EIO 5 + { EIO, TARGET_LINUX_EIO }, +#endif +#ifdef ENXIO +# define TARGET_LINUX_ENXIO 6 + { ENXIO, TARGET_LINUX_ENXIO }, +#endif +#ifdef E2BIG +# define TARGET_LINUX_E2BIG 7 + { E2BIG, TARGET_LINUX_E2BIG }, +#endif +#ifdef ENOEXEC +# define TARGET_LINUX_ENOEXEC 8 + { ENOEXEC, TARGET_LINUX_ENOEXEC }, +#endif +#ifdef EBADF +# define TARGET_LINUX_EBADF 9 + { EBADF, TARGET_LINUX_EBADF }, +#endif +#ifdef ECHILD +# define TARGET_LINUX_ECHILD 10 + { ECHILD, TARGET_LINUX_ECHILD }, +#endif +#ifdef EAGAIN +# define TARGET_LINUX_EAGAIN 11 + { EAGAIN, TARGET_LINUX_EAGAIN }, +#endif +#ifdef ENOMEM +# define TARGET_LINUX_ENOMEM 12 + { ENOMEM, TARGET_LINUX_ENOMEM }, +#endif +#ifdef EACCES +# define TARGET_LINUX_EACCES 13 + { EACCES, TARGET_LINUX_EACCES }, +#endif +#ifdef EFAULT +# define TARGET_LINUX_EFAULT 14 + { EFAULT, TARGET_LINUX_EFAULT }, +#endif +#ifdef ENOTBLK +# define TARGET_LINUX_ENOTBLK 15 + { ENOTBLK, TARGET_LINUX_ENOTBLK }, +#endif +#ifdef EBUSY +# define TARGET_LINUX_EBUSY 16 + { EBUSY, TARGET_LINUX_EBUSY }, +#endif +#ifdef EEXIST +# define TARGET_LINUX_EEXIST 17 + { EEXIST, TARGET_LINUX_EEXIST }, +#endif +#ifdef EXDEV +# define TARGET_LINUX_EXDEV 18 + { EXDEV, TARGET_LINUX_EXDEV }, +#endif +#ifdef ENODEV +# define TARGET_LINUX_ENODEV 19 + { ENODEV, TARGET_LINUX_ENODEV }, +#endif +#ifdef ENOTDIR +# define TARGET_LINUX_ENOTDIR 20 + { ENOTDIR, TARGET_LINUX_ENOTDIR }, +#endif +#ifdef EISDIR +# define TARGET_LINUX_EISDIR 21 + { EISDIR, TARGET_LINUX_EISDIR }, +#endif +#ifdef EINVAL +# define TARGET_LINUX_EINVAL 22 + { EINVAL, TARGET_LINUX_EINVAL }, +#endif +#ifdef ENFILE +# define TARGET_LINUX_ENFILE 23 + { ENFILE, TARGET_LINUX_ENFILE }, +#endif +#ifdef EMFILE +# define TARGET_LINUX_EMFILE 24 + { EMFILE, TARGET_LINUX_EMFILE }, +#endif +#ifdef ENOTTY +# define TARGET_LINUX_ENOTTY 25 + { ENOTTY, TARGET_LINUX_ENOTTY }, +#endif +#ifdef ETXTBSY +# define TARGET_LINUX_ETXTBSY 26 + { ETXTBSY, TARGET_LINUX_ETXTBSY }, +#endif +#ifdef EFBIG +# define TARGET_LINUX_EFBIG 27 + { EFBIG, TARGET_LINUX_EFBIG }, +#endif +#ifdef ENOSPC +# define TARGET_LINUX_ENOSPC 28 + { ENOSPC, TARGET_LINUX_ENOSPC }, +#endif +#ifdef ESPIPE +# define TARGET_LINUX_ESPIPE 29 + { ESPIPE, TARGET_LINUX_ESPIPE }, +#endif +#ifdef EROFS +# define TARGET_LINUX_EROFS 30 + { EROFS, TARGET_LINUX_EROFS }, +#endif +#ifdef EMLINK +# define TARGET_LINUX_EMLINK 31 + { EMLINK, TARGET_LINUX_EMLINK }, +#endif +#ifdef EPIPE +# define TARGET_LINUX_EPIPE 32 + { EPIPE, TARGET_LINUX_EPIPE }, +#endif +#ifdef EDOM +# define TARGET_LINUX_EDOM 33 + { EDOM, TARGET_LINUX_EDOM }, +#endif +#ifdef ERANGE +# define TARGET_LINUX_ERANGE 34 + { ERANGE, TARGET_LINUX_ERANGE }, +#endif +#ifdef EDEADLK +# define TARGET_LINUX_EDEADLK 35 + { EDEADLK, TARGET_LINUX_EDEADLK }, +#endif +#ifdef ENAMETOOLONG +# define TARGET_LINUX_ENAMETOOLONG 36 + { ENAMETOOLONG, TARGET_LINUX_ENAMETOOLONG }, +#endif +#ifdef ENOLCK +# define TARGET_LINUX_ENOLCK 37 + { ENOLCK, TARGET_LINUX_ENOLCK }, +#endif +#ifdef ENOSYS +# define TARGET_LINUX_ENOSYS 38 + { ENOSYS, TARGET_LINUX_ENOSYS }, +#endif +#ifdef ENOTEMPTY +# define TARGET_LINUX_ENOTEMPTY 39 + { ENOTEMPTY, TARGET_LINUX_ENOTEMPTY }, +#endif +#ifdef ELOOP +# define TARGET_LINUX_ELOOP 40 + { ELOOP, TARGET_LINUX_ELOOP }, +#endif +#ifdef ENOMSG +# define TARGET_LINUX_ENOMSG 42 + { ENOMSG, TARGET_LINUX_ENOMSG }, +#endif +#ifdef EIDRM +# define TARGET_LINUX_EIDRM 43 + { EIDRM, TARGET_LINUX_EIDRM }, +#endif +#ifdef ECHRNG +# define TARGET_LINUX_ECHRNG 44 + { ECHRNG, TARGET_LINUX_ECHRNG }, +#endif +#ifdef EL2NSYNC +# define TARGET_LINUX_EL2NSYNC 45 + { EL2NSYNC, TARGET_LINUX_EL2NSYNC }, +#endif +#ifdef EL3HLT +# define TARGET_LINUX_EL3HLT 46 + { EL3HLT, TARGET_LINUX_EL3HLT }, +#endif +#ifdef EL3RST +# define TARGET_LINUX_EL3RST 47 + { EL3RST, TARGET_LINUX_EL3RST }, +#endif +#ifdef ELNRNG +# define TARGET_LINUX_ELNRNG 48 + { ELNRNG, TARGET_LINUX_ELNRNG }, +#endif +#ifdef EUNATCH +# define TARGET_LINUX_EUNATCH 49 + { EUNATCH, TARGET_LINUX_EUNATCH }, +#endif +#ifdef ENOCSI +# define TARGET_LINUX_ENOCSI 50 + { ENOCSI, TARGET_LINUX_ENOCSI }, +#endif +#ifdef EL2HLT +# define TARGET_LINUX_EL2HLT 51 + { EL2HLT, TARGET_LINUX_EL2HLT }, +#endif +#ifdef EBADE +# define TARGET_LINUX_EBADE 52 + { EBADE, TARGET_LINUX_EBADE }, +#endif +#ifdef EBADR +# define TARGET_LINUX_EBADR 53 + { EBADR, TARGET_LINUX_EBADR }, +#endif +#ifdef EXFULL +# define TARGET_LINUX_EXFULL 54 + { EXFULL, TARGET_LINUX_EXFULL }, +#endif +#ifdef ENOANO +# define TARGET_LINUX_ENOANO 55 + { ENOANO, TARGET_LINUX_ENOANO }, +#endif +#ifdef EBADRQC +# define TARGET_LINUX_EBADRQC 56 + { EBADRQC, TARGET_LINUX_EBADRQC }, +#endif +#ifdef EBADSLT +# define TARGET_LINUX_EBADSLT 57 + { EBADSLT, TARGET_LINUX_EBADSLT }, +#endif +#ifdef EBFONT +# define TARGET_LINUX_EBFONT 59 + { EBFONT, TARGET_LINUX_EBFONT }, +#endif +#ifdef ENOSTR +# define TARGET_LINUX_ENOSTR 60 + { ENOSTR, TARGET_LINUX_ENOSTR }, +#endif +#ifdef ENODATA +# define TARGET_LINUX_ENODATA 61 + { ENODATA, TARGET_LINUX_ENODATA }, +#endif +#ifdef ETIME +# define TARGET_LINUX_ETIME 62 + { ETIME, TARGET_LINUX_ETIME }, +#endif +#ifdef ENOSR +# define TARGET_LINUX_ENOSR 63 + { ENOSR, TARGET_LINUX_ENOSR }, +#endif +#ifdef ENONET +# define TARGET_LINUX_ENONET 64 + { ENONET, TARGET_LINUX_ENONET }, +#endif +#ifdef ENOPKG +# define TARGET_LINUX_ENOPKG 65 + { ENOPKG, TARGET_LINUX_ENOPKG }, +#endif +#ifdef EREMOTE +# define TARGET_LINUX_EREMOTE 66 + { EREMOTE, TARGET_LINUX_EREMOTE }, +#endif +#ifdef ENOLINK +# define TARGET_LINUX_ENOLINK 67 + { ENOLINK, TARGET_LINUX_ENOLINK }, +#endif +#ifdef EADV +# define TARGET_LINUX_EADV 68 + { EADV, TARGET_LINUX_EADV }, +#endif +#ifdef ESRMNT +# define TARGET_LINUX_ESRMNT 69 + { ESRMNT, TARGET_LINUX_ESRMNT }, +#endif +#ifdef ECOMM +# define TARGET_LINUX_ECOMM 70 + { ECOMM, TARGET_LINUX_ECOMM }, +#endif +#ifdef EPROTO +# define TARGET_LINUX_EPROTO 71 + { EPROTO, TARGET_LINUX_EPROTO }, +#endif +#ifdef EMULTIHOP +# define TARGET_LINUX_EMULTIHOP 72 + { EMULTIHOP, TARGET_LINUX_EMULTIHOP }, +#endif +#ifdef EDOTDOT +# define TARGET_LINUX_EDOTDOT 73 + { EDOTDOT, TARGET_LINUX_EDOTDOT }, +#endif +#ifdef EBADMSG +# define TARGET_LINUX_EBADMSG 74 + { EBADMSG, TARGET_LINUX_EBADMSG }, +#endif +#ifdef EOVERFLOW +# define TARGET_LINUX_EOVERFLOW 75 + { EOVERFLOW, TARGET_LINUX_EOVERFLOW }, +#endif +#ifdef ENOTUNIQ +# define TARGET_LINUX_ENOTUNIQ 76 + { ENOTUNIQ, TARGET_LINUX_ENOTUNIQ }, +#endif +#ifdef EBADFD +# define TARGET_LINUX_EBADFD 77 + { EBADFD, TARGET_LINUX_EBADFD }, +#endif +#ifdef EREMCHG +# define TARGET_LINUX_EREMCHG 78 + { EREMCHG, TARGET_LINUX_EREMCHG }, +#endif +#ifdef ELIBACC +# define TARGET_LINUX_ELIBACC 79 + { ELIBACC, TARGET_LINUX_ELIBACC }, +#endif +#ifdef ELIBBAD +# define TARGET_LINUX_ELIBBAD 80 + { ELIBBAD, TARGET_LINUX_ELIBBAD }, +#endif +#ifdef ELIBSCN +# define TARGET_LINUX_ELIBSCN 81 + { ELIBSCN, TARGET_LINUX_ELIBSCN }, +#endif +#ifdef ELIBMAX +# define TARGET_LINUX_ELIBMAX 82 + { ELIBMAX, TARGET_LINUX_ELIBMAX }, +#endif +#ifdef ELIBEXEC +# define TARGET_LINUX_ELIBEXEC 83 + { ELIBEXEC, TARGET_LINUX_ELIBEXEC }, +#endif +#ifdef EILSEQ +# define TARGET_LINUX_EILSEQ 84 + { EILSEQ, TARGET_LINUX_EILSEQ }, +#endif +#ifdef ERESTART +# define TARGET_LINUX_ERESTART 85 + { ERESTART, TARGET_LINUX_ERESTART }, +#endif +#ifdef ESTRPIPE +# define TARGET_LINUX_ESTRPIPE 86 + { ESTRPIPE, TARGET_LINUX_ESTRPIPE }, +#endif +#ifdef EUSERS +# define TARGET_LINUX_EUSERS 87 + { EUSERS, TARGET_LINUX_EUSERS }, +#endif +#ifdef ENOTSOCK +# define TARGET_LINUX_ENOTSOCK 88 + { ENOTSOCK, TARGET_LINUX_ENOTSOCK }, +#endif +#ifdef EDESTADDRREQ +# define TARGET_LINUX_EDESTADDRREQ 89 + { EDESTADDRREQ, TARGET_LINUX_EDESTADDRREQ }, +#endif +#ifdef EMSGSIZE +# define TARGET_LINUX_EMSGSIZE 90 + { EMSGSIZE, TARGET_LINUX_EMSGSIZE }, +#endif +#ifdef EPROTOTYPE +# define TARGET_LINUX_EPROTOTYPE 91 + { EPROTOTYPE, TARGET_LINUX_EPROTOTYPE }, +#endif +#ifdef ENOPROTOOPT +# define TARGET_LINUX_ENOPROTOOPT 92 + { ENOPROTOOPT, TARGET_LINUX_ENOPROTOOPT }, +#endif +#ifdef EPROTONOSUPPORT +# define TARGET_LINUX_EPROTONOSUPPORT 93 + { EPROTONOSUPPORT, TARGET_LINUX_EPROTONOSUPPORT }, +#endif +#ifdef ESOCKTNOSUPPORT +# define TARGET_LINUX_ESOCKTNOSUPPORT 94 + { ESOCKTNOSUPPORT, TARGET_LINUX_ESOCKTNOSUPPORT }, +#endif +#ifdef EOPNOTSUPP +# define TARGET_LINUX_EOPNOTSUPP 95 + { EOPNOTSUPP, TARGET_LINUX_EOPNOTSUPP }, +#endif +#ifdef EPFNOSUPPORT +# define TARGET_LINUX_EPFNOSUPPORT 96 + { EPFNOSUPPORT, TARGET_LINUX_EPFNOSUPPORT }, +#endif +#ifdef EAFNOSUPPORT +# define TARGET_LINUX_EAFNOSUPPORT 97 + { EAFNOSUPPORT, TARGET_LINUX_EAFNOSUPPORT }, +#endif +#ifdef EADDRINUSE +# define TARGET_LINUX_EADDRINUSE 98 + { EADDRINUSE, TARGET_LINUX_EADDRINUSE }, +#endif +#ifdef EADDRNOTAVAIL +# define TARGET_LINUX_EADDRNOTAVAIL 99 + { EADDRNOTAVAIL, TARGET_LINUX_EADDRNOTAVAIL }, +#endif +#ifdef ENETDOWN +# define TARGET_LINUX_ENETDOWN 100 + { ENETDOWN, TARGET_LINUX_ENETDOWN }, +#endif +#ifdef ENETUNREACH +# define TARGET_LINUX_ENETUNREACH 101 + { ENETUNREACH, TARGET_LINUX_ENETUNREACH }, +#endif +#ifdef ENETRESET +# define TARGET_LINUX_ENETRESET 102 + { ENETRESET, TARGET_LINUX_ENETRESET }, +#endif +#ifdef ECONNABORTED +# define TARGET_LINUX_ECONNABORTED 103 + { ECONNABORTED, TARGET_LINUX_ECONNABORTED }, +#endif +#ifdef ECONNRESET +# define TARGET_LINUX_ECONNRESET 104 + { ECONNRESET, TARGET_LINUX_ECONNRESET }, +#endif +#ifdef ENOBUFS +# define TARGET_LINUX_ENOBUFS 105 + { ENOBUFS, TARGET_LINUX_ENOBUFS }, +#endif +#ifdef EISCONN +# define TARGET_LINUX_EISCONN 106 + { EISCONN, TARGET_LINUX_EISCONN }, +#endif +#ifdef ENOTCONN +# define TARGET_LINUX_ENOTCONN 107 + { ENOTCONN, TARGET_LINUX_ENOTCONN }, +#endif +#ifdef ESHUTDOWN +# define TARGET_LINUX_ESHUTDOWN 108 + { ESHUTDOWN, TARGET_LINUX_ESHUTDOWN }, +#endif +#ifdef ETOOMANYREFS +# define TARGET_LINUX_ETOOMANYREFS 109 + { ETOOMANYREFS, TARGET_LINUX_ETOOMANYREFS }, +#endif +#ifdef ETIMEDOUT +# define TARGET_LINUX_ETIMEDOUT 110 + { ETIMEDOUT, TARGET_LINUX_ETIMEDOUT }, +#endif +#ifdef ECONNREFUSED +# define TARGET_LINUX_ECONNREFUSED 111 + { ECONNREFUSED, TARGET_LINUX_ECONNREFUSED }, +#endif +#ifdef EHOSTDOWN +# define TARGET_LINUX_EHOSTDOWN 112 + { EHOSTDOWN, TARGET_LINUX_EHOSTDOWN }, +#endif +#ifdef EHOSTUNREACH +# define TARGET_LINUX_EHOSTUNREACH 113 + { EHOSTUNREACH, TARGET_LINUX_EHOSTUNREACH }, +#endif +#ifdef EALREADY +# define TARGET_LINUX_EALREADY 114 + { EALREADY, TARGET_LINUX_EALREADY }, +#endif +#ifdef EINPROGRESS +# define TARGET_LINUX_EINPROGRESS 115 + { EINPROGRESS, TARGET_LINUX_EINPROGRESS }, +#endif +#ifdef ESTALE +# define TARGET_LINUX_ESTALE 116 + { ESTALE, TARGET_LINUX_ESTALE }, +#endif +#ifdef EUCLEAN +# define TARGET_LINUX_EUCLEAN 117 + { EUCLEAN, TARGET_LINUX_EUCLEAN }, +#endif +#ifdef ENOTNAM +# define TARGET_LINUX_ENOTNAM 118 + { ENOTNAM, TARGET_LINUX_ENOTNAM }, +#endif +#ifdef ENAVAIL +# define TARGET_LINUX_ENAVAIL 119 + { ENAVAIL, TARGET_LINUX_ENAVAIL }, +#endif +#ifdef EISNAM +# define TARGET_LINUX_EISNAM 120 + { EISNAM, TARGET_LINUX_EISNAM }, +#endif +#ifdef EREMOTEIO +# define TARGET_LINUX_EREMOTEIO 121 + { EREMOTEIO, TARGET_LINUX_EREMOTEIO }, +#endif +#ifdef EDQUOT +# define TARGET_LINUX_EDQUOT 122 + { EDQUOT, TARGET_LINUX_EDQUOT }, +#endif +#ifdef ENOMEDIUM +# define TARGET_LINUX_ENOMEDIUM 123 + { ENOMEDIUM, TARGET_LINUX_ENOMEDIUM }, +#endif +#ifdef EMEDIUMTYPE +# define TARGET_LINUX_EMEDIUMTYPE 124 + { EMEDIUMTYPE, TARGET_LINUX_EMEDIUMTYPE }, +#endif +#ifdef ECANCELED +# define TARGET_LINUX_ECANCELED 125 + { ECANCELED, TARGET_LINUX_ECANCELED }, +#endif +#ifdef EOWNERDEAD +# define TARGET_LINUX_EOWNERDEAD 130 + { EOWNERDEAD, TARGET_LINUX_EOWNERDEAD }, +#endif +#ifdef ENOTRECOVERABLE +# define TARGET_LINUX_ENOTRECOVERABLE 131 + { ENOTRECOVERABLE, TARGET_LINUX_ENOTRECOVERABLE }, +#endif + { 0, 0 } +}; + +static CB_TARGET_DEFS_MAP cb_linux_open_map[] = +{ +#ifdef O_ACCMODE +# define TARGET_LINUX_O_ACCMODE 0003 + { O_ACCMODE, TARGET_LINUX_O_ACCMODE }, +#endif +#ifdef O_RDONLY +# define TARGET_LINUX_O_RDONLY 00 + { O_RDONLY, TARGET_LINUX_O_RDONLY }, +#endif +#ifdef O_WRONLY +# define TARGET_LINUX_O_WRONLY 01 + { O_WRONLY, TARGET_LINUX_O_WRONLY }, +#endif +#ifdef O_RDWR +# define TARGET_LINUX_O_RDWR 02 + { O_RDWR, TARGET_LINUX_O_RDWR }, +#endif +#ifdef O_CREAT +# define TARGET_LINUX_O_CREAT 0100 + { O_CREAT, TARGET_LINUX_O_CREAT }, +#endif +#ifdef O_EXCL +# define TARGET_LINUX_O_EXCL 0200 + { O_EXCL, TARGET_LINUX_O_EXCL }, +#endif +#ifdef O_NOCTTY +# define TARGET_LINUX_O_NOCTTY 0400 + { O_NOCTTY, TARGET_LINUX_O_NOCTTY }, +#endif +#ifdef O_TRUNC +# define TARGET_LINUX_O_TRUNC 01000 + { O_TRUNC, TARGET_LINUX_O_TRUNC }, +#endif +#ifdef O_APPEND +# define TARGET_LINUX_O_APPEND 02000 + { O_APPEND, TARGET_LINUX_O_APPEND }, +#endif +#ifdef O_NONBLOCK +# define TARGET_LINUX_O_NONBLOCK 04000 + { O_NONBLOCK, TARGET_LINUX_O_NONBLOCK }, +#endif +#ifdef O_SYNC +# define TARGET_LINUX_O_SYNC 010000 + { O_SYNC, TARGET_LINUX_O_SYNC }, +#endif +#ifdef O_ASYNC +# define TARGET_LINUX_O_ASYNC 020000 + { O_ASYNC, TARGET_LINUX_O_ASYNC }, +#endif + { -1, -1 } +}; + +static CB_TARGET_DEFS_MAP cb_linux_signal_map[] = +{ +#ifdef SIGHUP +# define TARGET_LINUX_SIGHUP 1 + { SIGHUP, TARGET_LINUX_SIGHUP }, +#endif +#ifdef SIGINT +# define TARGET_LINUX_SIGINT 2 + { SIGINT, TARGET_LINUX_SIGINT }, +#endif +#ifdef SIGQUIT +# define TARGET_LINUX_SIGQUIT 3 + { SIGQUIT, TARGET_LINUX_SIGQUIT }, +#endif +#ifdef SIGILL +# define TARGET_LINUX_SIGILL 4 + { SIGILL, TARGET_LINUX_SIGILL }, +#endif +#ifdef SIGTRAP +# define TARGET_LINUX_SIGTRAP 5 + { SIGTRAP, TARGET_LINUX_SIGTRAP }, +#endif +#ifdef SIGABRT +# define TARGET_LINUX_SIGABRT 6 + { SIGABRT, TARGET_LINUX_SIGABRT }, +#endif +#ifdef SIGIOT +# define TARGET_LINUX_SIGIOT 6 + { SIGIOT, TARGET_LINUX_SIGIOT }, +#endif +#ifdef SIGBUS +# define TARGET_LINUX_SIGBUS 7 + { SIGBUS, TARGET_LINUX_SIGBUS }, +#endif +#ifdef SIGFPE +# define TARGET_LINUX_SIGFPE 8 + { SIGFPE, TARGET_LINUX_SIGFPE }, +#endif +#ifdef SIGKILL +# define TARGET_LINUX_SIGKILL 9 + { SIGKILL, TARGET_LINUX_SIGKILL }, +#endif +#ifdef SIGUSR1 +# define TARGET_LINUX_SIGUSR1 10 + { SIGUSR1, TARGET_LINUX_SIGUSR1 }, +#endif +#ifdef SIGSEGV +# define TARGET_LINUX_SIGSEGV 11 + { SIGSEGV, TARGET_LINUX_SIGSEGV }, +#endif +#ifdef SIGUSR2 +# define TARGET_LINUX_SIGUSR2 12 + { SIGUSR2, TARGET_LINUX_SIGUSR2 }, +#endif +#ifdef SIGPIPE +# define TARGET_LINUX_SIGPIPE 13 + { SIGPIPE, TARGET_LINUX_SIGPIPE }, +#endif +#ifdef SIGALRM +# define TARGET_LINUX_SIGALRM 14 + { SIGALRM, TARGET_LINUX_SIGALRM }, +#endif +#ifdef SIGTERM +# define TARGET_LINUX_SIGTERM 15 + { SIGTERM, TARGET_LINUX_SIGTERM }, +#endif +#ifdef SIGSTKFLT +# define TARGET_LINUX_SIGSTKFLT 16 + { SIGSTKFLT, TARGET_LINUX_SIGSTKFLT }, +#endif +#ifdef SIGCHLD +# define TARGET_LINUX_SIGCHLD 17 + { SIGCHLD, TARGET_LINUX_SIGCHLD }, +#endif +#ifdef SIGCONT +# define TARGET_LINUX_SIGCONT 18 + { SIGCONT, TARGET_LINUX_SIGCONT }, +#endif +#ifdef SIGSTOP +# define TARGET_LINUX_SIGSTOP 19 + { SIGSTOP, TARGET_LINUX_SIGSTOP }, +#endif +#ifdef SIGTSTP +# define TARGET_LINUX_SIGTSTP 20 + { SIGTSTP, TARGET_LINUX_SIGTSTP }, +#endif +#ifdef SIGTTIN +# define TARGET_LINUX_SIGTTIN 21 + { SIGTTIN, TARGET_LINUX_SIGTTIN }, +#endif +#ifdef SIGTTOU +# define TARGET_LINUX_SIGTTOU 22 + { SIGTTOU, TARGET_LINUX_SIGTTOU }, +#endif +#ifdef SIGURG +# define TARGET_LINUX_SIGURG 23 + { SIGURG, TARGET_LINUX_SIGURG }, +#endif +#ifdef SIGXCPU +# define TARGET_LINUX_SIGXCPU 24 + { SIGXCPU, TARGET_LINUX_SIGXCPU }, +#endif +#ifdef SIGXFSZ +# define TARGET_LINUX_SIGXFSZ 25 + { SIGXFSZ, TARGET_LINUX_SIGXFSZ }, +#endif +#ifdef SIGVTALRM +# define TARGET_LINUX_SIGVTALRM 26 + { SIGVTALRM, TARGET_LINUX_SIGVTALRM }, +#endif +#ifdef SIGPROF +# define TARGET_LINUX_SIGPROF 27 + { SIGPROF, TARGET_LINUX_SIGPROF }, +#endif +#ifdef SIGWINCH +# define TARGET_LINUX_SIGWINCH 28 + { SIGWINCH, TARGET_LINUX_SIGWINCH }, +#endif +#ifdef SIGIO +# define TARGET_LINUX_SIGIO 29 + { SIGIO, TARGET_LINUX_SIGIO }, +#endif +#ifdef SIGPWR +# define TARGET_LINUX_SIGPWR 30 + { SIGPWR, TARGET_LINUX_SIGPWR }, +#endif +#ifdef SIGSYS +# define TARGET_LINUX_SIGSYS 31 + { SIGSYS, TARGET_LINUX_SIGSYS }, +#endif +#ifdef SIGUNUSED +# define TARGET_LINUX_SIGUNUSED 31 + { SIGUNUSED, TARGET_LINUX_SIGUNUSED }, +#endif +#ifdef SIG_BLOCK +# define TARGET_LINUX_SIG_BLOCK 0 + { SIG_BLOCK, TARGET_LINUX_SIG_BLOCK }, +#endif +#ifdef SIG_UNBLOCK +# define TARGET_LINUX_SIG_UNBLOCK 1 + { SIG_UNBLOCK, TARGET_LINUX_SIG_UNBLOCK }, +#endif +#ifdef SIG_SETMASK +# define TARGET_LINUX_SIG_SETMASK 2 + { SIG_SETMASK, TARGET_LINUX_SIG_SETMASK }, +#endif +#ifdef SIGSTKSZ +# define TARGET_LINUX_SIGSTKSZ 8192 + { SIGSTKSZ, TARGET_LINUX_SIGSTKSZ }, +#endif + { -1, -1 } +}; diff --git a/external/gpl3/gdb/dist/sim/bfin/machs.c b/external/gpl3/gdb/dist/sim/bfin/machs.c new file mode 100644 index 000000000000..0c6e6f38fb56 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/machs.c @@ -0,0 +1,1341 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "config.h" + +#include "sim-main.h" +#include "gdb/sim-bfin.h" +#include "bfd.h" + +#include "sim-hw.h" +#include "devices.h" +#include "dv-bfin_cec.h" +#include "dv-bfin_ctimer.h" +#include "dv-bfin_dma.h" +#include "dv-bfin_dmac.h" +#include "dv-bfin_ebiu_amc.h" +#include "dv-bfin_ebiu_ddrc.h" +#include "dv-bfin_ebiu_sdc.h" +#include "dv-bfin_emac.h" +#include "dv-bfin_eppi.h" +#include "dv-bfin_evt.h" +#include "dv-bfin_gpio.h" +#include "dv-bfin_gptimer.h" +#include "dv-bfin_jtag.h" +#include "dv-bfin_mmu.h" +#include "dv-bfin_nfc.h" +#include "dv-bfin_otp.h" +#include "dv-bfin_pll.h" +#include "dv-bfin_ppi.h" +#include "dv-bfin_rtc.h" +#include "dv-bfin_sic.h" +#include "dv-bfin_spi.h" +#include "dv-bfin_trace.h" +#include "dv-bfin_twi.h" +#include "dv-bfin_uart.h" +#include "dv-bfin_uart2.h" +#include "dv-bfin_wdog.h" +#include "dv-bfin_wp.h" + +static const MACH bfin_mach; + +struct bfin_memory_layout { + address_word addr, len; + unsigned mask; /* see mapmask in sim_core_attach() */ +}; +struct bfin_dev_layout { + address_word base, len; + unsigned int dmac; + const char *dev; +}; +struct bfin_dmac_layout { + address_word base; + unsigned int dma_count; +}; +struct bfin_model_data { + bu32 chipid; + int model_num; + const struct bfin_memory_layout *mem; + size_t mem_count; + const struct bfin_dev_layout *dev; + size_t dev_count; + const struct bfin_dmac_layout *dmac; + size_t dmac_count; +}; + +#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, } +#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, } +#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0) + +/* [1] Common sim code can't model exec-only memory. + http://sourceware.org/ml/gdb/2010-02/msg00047.html */ + +#define bf000_chipid 0 +static const struct bfin_memory_layout bf000_mem[] = {}; +static const struct bfin_dev_layout bf000_dev[] = {}; +static const struct bfin_dmac_layout bf000_dmac[] = {}; + +#define bf50x_chipid 0x2800 +#define bf504_chipid bf50x_chipid +#define bf506_chipid bf50x_chipid +static const struct bfin_memory_layout bf50x_mem[] = +{ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ + LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */ + LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +#define bf504_mem bf50x_mem +#define bf506_mem bf50x_mem +static const struct bfin_dev_layout bf50x_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), + DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), +}; +#define bf504_dev bf50x_dev +#define bf506_dev bf50x_dev +static const struct bfin_dmac_layout bf50x_dmac[] = +{ + { BFIN_MMR_DMAC0_BASE, 12, }, +}; +#define bf504_dmac bf50x_dmac +#define bf506_dmac bf50x_dmac + +#define bf51x_chipid 0x27e8 +#define bf512_chipid bf51x_chipid +#define bf514_chipid bf51x_chipid +#define bf516_chipid bf51x_chipid +#define bf518_chipid bf51x_chipid +static const struct bfin_memory_layout bf51x_mem[] = +{ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ + LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */ + LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +#define bf512_mem bf51x_mem +#define bf514_mem bf51x_mem +#define bf516_mem bf51x_mem +#define bf518_mem bf51x_mem +static const struct bfin_dev_layout bf512_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), + DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), +}; +#define bf514_dev bf512_dev +static const struct bfin_dev_layout bf516_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0, 0x20, "bfin_emac/eth_phy"), + DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), +}; +#define bf518_dev bf516_dev +#define bf512_dmac bf50x_dmac +#define bf514_dmac bf50x_dmac +#define bf516_dmac bf50x_dmac +#define bf518_dmac bf50x_dmac + +#define bf522_chipid 0x27e4 +#define bf523_chipid 0x27e0 +#define bf524_chipid bf522_chipid +#define bf525_chipid bf523_chipid +#define bf526_chipid bf522_chipid +#define bf527_chipid bf523_chipid +static const struct bfin_memory_layout bf52x_mem[] = +{ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ + LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +#define bf522_mem bf52x_mem +#define bf523_mem bf52x_mem +#define bf524_mem bf52x_mem +#define bf525_mem bf52x_mem +#define bf526_mem bf52x_mem +#define bf527_mem bf52x_mem +static const struct bfin_dev_layout bf522_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), + DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), + DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), +}; +#define bf523_dev bf522_dev +#define bf524_dev bf522_dev +#define bf525_dev bf522_dev +static const struct bfin_dev_layout bf526_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0, 0x20, "bfin_emac/eth_phy"), + DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), + DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), +}; +#define bf527_dev bf526_dev +#define bf522_dmac bf50x_dmac +#define bf523_dmac bf50x_dmac +#define bf524_dmac bf50x_dmac +#define bf525_dmac bf50x_dmac +#define bf526_dmac bf50x_dmac +#define bf527_dmac bf50x_dmac + +#define bf531_chipid 0x27a5 +#define bf532_chipid bf531_chipid +#define bf533_chipid bf531_chipid +static const struct bfin_memory_layout bf531_mem[] = +{ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_memory_layout bf532_mem[] = +{ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_memory_layout bf533_mem[] = +{ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_dev_layout bf533_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), +}; +#define bf531_dev bf533_dev +#define bf532_dev bf533_dev +static const struct bfin_dmac_layout bf533_dmac[] = +{ + { BFIN_MMR_DMAC0_BASE, 8, }, +}; +#define bf531_dmac bf533_dmac +#define bf532_dmac bf533_dmac + +#define bf534_chipid 0x27c6 +#define bf536_chipid 0x27c8 +#define bf537_chipid bf536_chipid +static const struct bfin_memory_layout bf534_mem[] = +{ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_memory_layout bf536_mem[] = +{ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_memory_layout bf537_mem[] = +{ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_dev_layout bf534_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), +}; +static const struct bfin_dev_layout bf537_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0, 0x20, "bfin_emac/eth_phy"), +}; +#define bf536_dev bf537_dev +#define bf534_dmac bf50x_dmac +#define bf536_dmac bf50x_dmac +#define bf537_dmac bf50x_dmac + +#define bf538_chipid 0x27c4 +#define bf539_chipid bf538_chipid +static const struct bfin_memory_layout bf538_mem[] = +{ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */ + LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ + LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +#define bf539_mem bf538_mem +static const struct bfin_dev_layout bf538_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1), + _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1), + DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), + _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1), + _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), +}; +#define bf539_dev bf538_dev +static const struct bfin_dmac_layout bf538_dmac[] = +{ + { BFIN_MMR_DMAC0_BASE, 8, }, + { BFIN_MMR_DMAC1_BASE, 12, }, +}; +#define bf539_dmac bf538_dmac + +#define bf54x_chipid 0x27de +#define bf542_chipid bf54x_chipid +#define bf544_chipid bf54x_chipid +#define bf547_chipid bf54x_chipid +#define bf548_chipid bf54x_chipid +#define bf549_chipid bf54x_chipid +static const struct bfin_memory_layout bf54x_mem[] = +{ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */ + LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ + LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ + LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */ + LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */ + LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */ + LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +#define bf542_mem bf54x_mem +#define bf544_mem bf54x_mem +#define bf547_mem bf54x_mem +#define bf548_mem bf54x_mem +#define bf549_mem bf54x_mem +static const struct bfin_dev_layout bf542_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), + _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), + _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), + DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), + _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), + DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), + DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), +}; +static const struct bfin_dev_layout bf544_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), + DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), + _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), + _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), + _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), + DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), + DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), + _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), + DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), + DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), +}; +static const struct bfin_dev_layout bf547_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), + DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), + DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), + _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), + _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), + _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), + DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), + DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), + _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), + _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), + DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), +}; +#define bf548_dev bf547_dev +#define bf549_dev bf547_dev +static const struct bfin_dmac_layout bf54x_dmac[] = +{ + { BFIN_MMR_DMAC0_BASE, 12, }, + { BFIN_MMR_DMAC1_BASE, 12, }, +}; +#define bf542_dmac bf54x_dmac +#define bf544_dmac bf54x_dmac +#define bf547_dmac bf54x_dmac +#define bf548_dmac bf54x_dmac +#define bf549_dmac bf54x_dmac + +/* This is only Core A of course ... */ +#define bf561_chipid 0x27bb +static const struct bfin_memory_layout bf561_mem[] = +{ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ + LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ + LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ + LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ + LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ + LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ +}; +static const struct bfin_dev_layout bf561_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), + DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1), + DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"), + _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), + DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), + DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), + DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), + DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"), + DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), +}; +static const struct bfin_dmac_layout bf561_dmac[] = +{ + { BFIN_MMR_DMAC0_BASE, 12, }, + { BFIN_MMR_DMAC1_BASE, 12, }, + /* XXX: IMDMA: { 0xFFC01800, 4, }, */ +}; + +#define bf592_chipid 0x20cb +static const struct bfin_memory_layout bf592_mem[] = +{ + LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ + LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ + LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */ + LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ + LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */ +}; +static const struct bfin_dev_layout bf592_dev[] = +{ + DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), + DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), + DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), + DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), + DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), +}; +static const struct bfin_dmac_layout bf592_dmac[] = +{ + /* XXX: there are only 9 channels, but mdma code below assumes that they + start right after the dma channels ... */ + { BFIN_MMR_DMAC0_BASE, 12, }, +}; + +static const struct bfin_model_data bfin_model_data[] = +{ +#define P(n) \ + [MODEL_BF##n] = { \ + bf##n##_chipid, n, \ + bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \ + bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \ + bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \ + }, +#include "proc_list.def" +#undef P +}; + +#define CORE_DEVICE(dev, DEV) \ + DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev) +static const struct bfin_dev_layout bfin_core_dev[] = +{ + CORE_DEVICE (cec, CEC), + CORE_DEVICE (ctimer, CTIMER), + CORE_DEVICE (evt, EVT), + CORE_DEVICE (jtag, JTAG), + CORE_DEVICE (mmu, MMU), + CORE_DEVICE (trace, TRACE), + CORE_DEVICE (wp, WP), +}; + +#define dv_bfin_hw_parse(sd, dv, DV) \ + do { \ + bu32 base = BFIN_MMR_##DV##_BASE; \ + bu32 size = BFIN_MMR_##DV##_SIZE; \ + sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \ + sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \ + } while (0) + +static void +bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu) +{ + const MODEL *model = CPU_MODEL (cpu); + const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); + const struct bfin_board_data *board = STATE_BOARD_DATA (sd); + int mnum = MODEL_NUM (model); + unsigned i, j, dma_chan; + + /* Map the core devices. */ + for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i) + { + const struct bfin_dev_layout *dev = &bfin_core_dev[i]; + sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); + } + sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec"); + + if (mnum == MODEL_BF000) + goto done; + + /* Map the system devices. */ + dv_bfin_hw_parse (sd, sic, SIC); + sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num); + for (i = 7; i < 16; ++i) + sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i); + + dv_bfin_hw_parse (sd, pll, PLL); + sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic"); + + dma_chan = 0; + for (i = 0; i < mdata->dmac_count; ++i) + { + const struct bfin_dmac_layout *dmac = &mdata->dmac[i]; + + sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num); + + /* Hook up the non-mdma channels. */ + for (j = 0; j < dmac->dma_count; ++j) + { + sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i, + dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE, + BFIN_MMR_DMA_SIZE); + + /* Could route these into the bfin_dmac and let that + forward it to the SIC, but not much value. */ + sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic", + i, dma_chan, dma_chan); + + ++dma_chan; + } + + /* Hook up the mdma channels -- assume every DMAC has 4. */ + for (j = 0; j < 4; ++j) + { + sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", + i, j + BFIN_DMAC_MDMA_BASE, + dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE, + BFIN_MMR_DMA_SIZE); + sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic", + i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2)); + } + } + + for (i = 0; i < mdata->dev_count; ++i) + { + const struct bfin_dev_layout *dev = &mdata->dev[i]; + sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); + sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num); + if (strchr (dev->dev, '/')) + continue; + if (!strncmp (dev->dev, "bfin_uart", 9) + || !strncmp (dev->dev, "bfin_emac", 9) + || !strncmp (dev->dev, "bfin_sport", 10)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); + sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); + sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint); + } + else if (!strncmp (dev->dev, "bfin_gptimer", 12) + || !strncmp (dev->dev, "bfin_ppi", 8) + || !strncmp (dev->dev, "bfin_spi", 8) + || !strncmp (dev->dev, "bfin_twi", 8)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint); + } + else if (!strncmp (dev->dev, "bfin_rtc", 8)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint); + } + else if (!strncmp (dev->dev, "bfin_wdog", 9)) + { + sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev); + sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev); + sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev); + } + else if (!strncmp (dev->dev, "bfin_gpio", 9)) + { + char port = 'a' + strtol(&dev->dev[10], NULL, 0); + sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic", + dev->dev, port); + sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic", + dev->dev, port); + } + } + + done: + /* Add any additional user board content. */ + if (board->hw_file) + sim_do_commandf (sd, "hw-file %s", board->hw_file); + + /* Trigger all the new devices' finish func. */ + hw_tree_finish (dv_get_device (cpu, "/")); +} + +#include "bfroms/all.h" + +struct bfrom { + bu32 addr, len, alias_len; + int sirev; + const char *buf; +}; + +#define BFROMA(addr, rom, sirev, alias_len) \ + { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \ + sirev, bfrom_bf##rom##_0_##sirev, } +#define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len) +#define BFROM_STUB { 0, 0, 0, 0, NULL, } +static const struct bfrom bf50x_roms[] = +{ + BFROM (50x, 0, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf51x_roms[] = +{ + BFROM (51x, 2, 0x1000000), + BFROM (51x, 1, 0x1000000), + BFROM (51x, 0, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf526_roms[] = +{ + BFROM (526, 1, 0x1000000), + BFROM (526, 0, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf527_roms[] = +{ + BFROM (527, 2, 0x1000000), + BFROM (527, 1, 0x1000000), + BFROM (527, 0, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf533_roms[] = +{ + BFROM (533, 6, 0x1000000), + BFROM (533, 5, 0x1000000), + BFROM (533, 4, 0x1000000), + BFROM (533, 3, 0x1000000), + BFROM (533, 2, 0x1000000), + BFROM (533, 1, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf537_roms[] = +{ + BFROM (537, 3, 0x100000), + BFROM (537, 2, 0x100000), + BFROM (537, 1, 0x100000), + BFROM (537, 0, 0x100000), + BFROM_STUB, +}; +static const struct bfrom bf538_roms[] = +{ + BFROM (538, 5, 0x1000000), + BFROM (538, 4, 0x1000000), + BFROM (538, 3, 0x1000000), + BFROM (538, 2, 0x1000000), + BFROM (538, 1, 0x1000000), + BFROM (538, 0, 0x1000000), + BFROM_STUB, +}; +static const struct bfrom bf54x_roms[] = +{ + BFROM (54x, 2, 0), + BFROM (54x, 1, 0), + BFROM (54x, 0, 0), + BFROMA (0xffa14000, 54x_l1, 2, 0), + BFROMA (0xffa14000, 54x_l1, 1, 0), + BFROMA (0xffa14000, 54x_l1, 0, 0), + BFROM_STUB, +}; +static const struct bfrom bf561_roms[] = +{ + /* XXX: No idea what the actual wrap limit is here. */ + BFROM (561, 5, 0), + BFROM_STUB, +}; +static const struct bfrom bf59x_roms[] = +{ + BFROM (59x, 1, 0x1000000), + BFROM (59x, 0, 0x1000000), + BFROMA (0xffa10000, 59x_l1, 1, 0), + BFROM_STUB, +}; + +static void +bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu) +{ + const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); + const struct bfin_board_data *board = STATE_BOARD_DATA (sd); + int mnum = mdata->model_num; + const struct bfrom *bfrom; + unsigned int sirev; + + if (mnum >= 500 && mnum <= 509) + bfrom = bf50x_roms; + else if (mnum >= 510 && mnum <= 519) + bfrom = bf51x_roms; + else if (mnum >= 520 && mnum <= 529) + bfrom = (mnum & 1) ? bf527_roms : bf526_roms; + else if (mnum >= 531 && mnum <= 533) + bfrom = bf533_roms; + else if (mnum == 535) + /* Stub. */; + else if (mnum >= 534 && mnum <= 537) + bfrom = bf537_roms; + else if (mnum >= 538 && mnum <= 539) + bfrom = bf538_roms; + else if (mnum >= 540 && mnum <= 549) + bfrom = bf54x_roms; + else if (mnum == 561) + bfrom = bf561_roms; + else if (mnum >= 590 && mnum <= 599) + bfrom = bf59x_roms; + else + return; + + if (board->sirev_valid) + sirev = board->sirev; + else + sirev = bfrom->sirev; + while (bfrom->buf) + { + /* Map all the ranges for this model/sirev. */ + if (bfrom->sirev == sirev) + sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr, + bfrom->alias_len ? : bfrom->len, bfrom->len, NULL, + (char *)bfrom->buf); + ++bfrom; + } +} + +void +bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu) +{ + const MODEL *model = CPU_MODEL (cpu); + const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); + int mnum = MODEL_NUM (model); + size_t idx; + + /* These memory maps are supposed to be cpu-specific, but the common sim + code does not yet allow that (2nd arg is "cpu" rather than "NULL". */ + sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH, + BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL); + + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) + return; + + if (mnum == MODEL_BF000) + goto core_only; + + /* Map in the on-chip memories (SRAMs). */ + mdata = &bfin_model_data[MODEL_NUM (model)]; + for (idx = 0; idx < mdata->mem_count; ++idx) + { + const struct bfin_memory_layout *mem = &mdata->mem[idx]; + sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr, + mem->len, 0, NULL, NULL); + } + + /* Map the on-chip ROMs. */ + bfin_model_map_bfrom (sd, cpu); + + core_only: + /* Finally, build up the tree for this cpu model. */ + bfin_model_hw_tree_init (sd, cpu); +} + +bu32 +bfin_model_get_chipid (SIM_DESC sd) +{ + SIM_CPU *cpu = STATE_CPU (sd, 0); + const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); + const struct bfin_board_data *board = STATE_BOARD_DATA (sd); + return + (board->sirev << 28) | + (mdata->chipid << 12) | + (((0xE5 << 1) | 1) & 0xFF); +} + +bu32 +bfin_model_get_dspid (SIM_DESC sd) +{ + const struct bfin_board_data *board = STATE_BOARD_DATA (sd); + return + (0xE5 << 24) | + (0x04 << 16) | + (board->sirev); +} + +static void +bfin_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))]; +} + +static bu32 +bfin_extract_unsigned_integer (unsigned char *addr, int len) +{ + bu32 retval; + unsigned char * p; + unsigned char * startaddr = (unsigned char *)addr; + unsigned char * endaddr = startaddr + len; + + retval = 0; + + for (p = endaddr; p > startaddr;) + retval = (retval << 8) | *--p; + + return retval; +} + +static void +bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val) +{ + unsigned char *p; + unsigned char *startaddr = addr; + unsigned char *endaddr = startaddr + len; + + for (p = startaddr; p < endaddr;) + { + *p++ = val & 0xff; + val >>= 8; + } +} + +static bu32 * +bfin_get_reg (SIM_CPU *cpu, int rn) +{ + switch (rn) + { + case SIM_BFIN_R0_REGNUM: return &DREG (0); + case SIM_BFIN_R1_REGNUM: return &DREG (1); + case SIM_BFIN_R2_REGNUM: return &DREG (2); + case SIM_BFIN_R3_REGNUM: return &DREG (3); + case SIM_BFIN_R4_REGNUM: return &DREG (4); + case SIM_BFIN_R5_REGNUM: return &DREG (5); + case SIM_BFIN_R6_REGNUM: return &DREG (6); + case SIM_BFIN_R7_REGNUM: return &DREG (7); + case SIM_BFIN_P0_REGNUM: return &PREG (0); + case SIM_BFIN_P1_REGNUM: return &PREG (1); + case SIM_BFIN_P2_REGNUM: return &PREG (2); + case SIM_BFIN_P3_REGNUM: return &PREG (3); + case SIM_BFIN_P4_REGNUM: return &PREG (4); + case SIM_BFIN_P5_REGNUM: return &PREG (5); + case SIM_BFIN_SP_REGNUM: return &SPREG; + case SIM_BFIN_FP_REGNUM: return &FPREG; + case SIM_BFIN_I0_REGNUM: return &IREG (0); + case SIM_BFIN_I1_REGNUM: return &IREG (1); + case SIM_BFIN_I2_REGNUM: return &IREG (2); + case SIM_BFIN_I3_REGNUM: return &IREG (3); + case SIM_BFIN_M0_REGNUM: return &MREG (0); + case SIM_BFIN_M1_REGNUM: return &MREG (1); + case SIM_BFIN_M2_REGNUM: return &MREG (2); + case SIM_BFIN_M3_REGNUM: return &MREG (3); + case SIM_BFIN_B0_REGNUM: return &BREG (0); + case SIM_BFIN_B1_REGNUM: return &BREG (1); + case SIM_BFIN_B2_REGNUM: return &BREG (2); + case SIM_BFIN_B3_REGNUM: return &BREG (3); + case SIM_BFIN_L0_REGNUM: return &LREG (0); + case SIM_BFIN_L1_REGNUM: return &LREG (1); + case SIM_BFIN_L2_REGNUM: return &LREG (2); + case SIM_BFIN_L3_REGNUM: return &LREG (3); + case SIM_BFIN_RETS_REGNUM: return &RETSREG; + case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0); + case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0); + case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1); + case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1); + case SIM_BFIN_LC0_REGNUM: return &LCREG (0); + case SIM_BFIN_LT0_REGNUM: return <REG (0); + case SIM_BFIN_LB0_REGNUM: return &LBREG (0); + case SIM_BFIN_LC1_REGNUM: return &LCREG (1); + case SIM_BFIN_LT1_REGNUM: return <REG (1); + case SIM_BFIN_LB1_REGNUM: return &LBREG (1); + case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG; + case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG; + case SIM_BFIN_USP_REGNUM: return &USPREG; + case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG; + case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG; + case SIM_BFIN_RETI_REGNUM: return &RETIREG; + case SIM_BFIN_RETX_REGNUM: return &RETXREG; + case SIM_BFIN_RETN_REGNUM: return &RETNREG; + case SIM_BFIN_RETE_REGNUM: return &RETEREG; + case SIM_BFIN_PC_REGNUM: return &PCREG; + default: return NULL; + } +} + +static int +bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len) +{ + bu32 value, *reg; + + reg = bfin_get_reg (cpu, rn); + if (reg) + value = *reg; + else if (rn == SIM_BFIN_ASTAT_REGNUM) + value = ASTAT; + else if (rn == SIM_BFIN_CC_REGNUM) + value = CCREG; + else + return 0; // will be an error in gdb + + /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we + have the normal SP/USP behavior. User mode is tricky though. */ + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT + && cec_is_user_mode (cpu)) + { + if (rn == SIM_BFIN_SP_REGNUM) + value = KSPREG; + else if (rn == SIM_BFIN_USP_REGNUM) + value = SPREG; + } + + bfin_store_unsigned_integer (buf, 4, value); + + return -1; // disables size checking in gdb +} + +static int +bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len) +{ + bu32 value, *reg; + + value = bfin_extract_unsigned_integer (buf, 4); + reg = bfin_get_reg (cpu, rn); + + if (reg) + /* XXX: Need register trace ? */ + *reg = value; + else if (rn == SIM_BFIN_ASTAT_REGNUM) + SET_ASTAT (value); + else if (rn == SIM_BFIN_CC_REGNUM) + SET_CCREG (value); + else + return 0; // will be an error in gdb + + return -1; // disables size checking in gdb +} + +static sim_cia +bfin_pc_get (SIM_CPU *cpu) +{ + return PCREG; +} + +static void +bfin_pc_set (SIM_CPU *cpu, sim_cia newpc) +{ + SET_PCREG (newpc); +} + +static const char * +bfin_insn_name (SIM_CPU *cpu, int i) +{ + static const char * const insn_name[] = { +#define I(insn) #insn, +#include "insn_list.def" +#undef I + }; + return insn_name[i]; +} + +static void +bfin_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = bfin_reg_fetch; + CPU_REG_STORE (cpu) = bfin_reg_store; + CPU_PC_FETCH (cpu) = bfin_pc_get; + CPU_PC_STORE (cpu) = bfin_pc_set; + CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX; + CPU_INSN_NAME (cpu) = bfin_insn_name; +} + +static void +bfin_prepare_run (SIM_CPU *cpu) +{ +} + +static const MODEL bfin_models[] = +{ +#define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init }, +#include "proc_list.def" +#undef P + { 0, NULL, 0, NULL, NULL, } +}; + +static const MACH_IMP_PROPERTIES bfin_imp_properties = +{ + sizeof (SIM_CPU), + 0, +}; + +static const MACH bfin_mach = +{ + "bfin", "bfin", MACH_BFIN, + 32, 32, & bfin_models[0], & bfin_imp_properties, + bfin_init_cpu, + bfin_prepare_run +}; + +const MACH *sim_machs[] = +{ + & bfin_mach, + NULL +}; + +/* Device option parsing. */ + +static DECLARE_OPTION_HANDLER (bfin_mach_option_handler); + +enum { + OPTION_MACH_SIREV = OPTION_START, + OPTION_MACH_HW_BOARD_FILE, +}; + +const OPTION bfin_mach_options[] = +{ + { {"sirev", required_argument, NULL, OPTION_MACH_SIREV }, + '\0', "NUMBER", "Set CPU silicon revision", + bfin_mach_option_handler, NULL }, + + { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE }, + '\0', "FILE", "Add the supplemental devices listed in the file", + bfin_mach_option_handler, NULL }, + + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL } +}; + +static SIM_RC +bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt, + char *arg, int is_command) +{ + struct bfin_board_data *board = STATE_BOARD_DATA (sd); + + switch (opt) + { + case OPTION_MACH_SIREV: + board->sirev_valid = 1; + /* Accept (and throw away) a leading "0." in the version. */ + if (!strncmp (arg, "0.", 2)) + arg += 2; + board->sirev = atoi (arg); + if (board->sirev > 0xf) + { + sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg); + return SIM_RC_FAIL; + } + return SIM_RC_OK; + + case OPTION_MACH_HW_BOARD_FILE: + board->hw_file = xstrdup (arg); + return SIM_RC_OK; + + default: + sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt); + return SIM_RC_FAIL; + } +} diff --git a/external/gpl3/gdb/dist/sim/bfin/machs.h b/external/gpl3/gdb/dist/sim/bfin/machs.h new file mode 100644 index 000000000000..ac16adb21f13 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/machs.h @@ -0,0 +1,56 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef _BFIN_MACHS_H_ +#define _BFIN_MACHS_H_ + +typedef enum model_type { +#define P(n) MODEL_BF##n, +#include "proc_list.def" +#undef P + MODEL_MAX +} MODEL_TYPE; + +typedef enum mach_attr { + MACH_BASE, + MACH_BFIN, + MACH_MAX +} MACH_ATTR; + +#define CPU_MODEL_NUM(cpu) MODEL_NUM (CPU_MODEL (cpu)) + +/* XXX: Some of this probably belongs in CPU_MODEL. */ +struct bfin_board_data { + unsigned int sirev, sirev_valid; + const char *hw_file; +}; + +void bfin_model_cpu_init (SIM_DESC, SIM_CPU *); +bu32 bfin_model_get_chipid (SIM_DESC); +bu32 bfin_model_get_dspid (SIM_DESC); + +enum { +#define I(insn) BFIN_INSN_##insn, +#include "insn_list.def" +#undef I + BFIN_INSN_MAX +}; + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/proc_list.def b/external/gpl3/gdb/dist/sim/bfin/proc_list.def new file mode 100644 index 000000000000..aa9d33764ed2 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/proc_list.def @@ -0,0 +1,50 @@ +/* Blackfin processor list + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* First entry is the default model. */ +P(537) +P(504) +P(506) +P(512) +P(514) +P(516) +P(518) +P(522) +P(523) +P(524) +P(525) +P(526) +P(527) +P(531) +P(532) +P(533) +P(534) +/*P(535)*/ +P(536) +P(538) +P(539) +P(542) +P(544) +P(547) +P(548) +P(549) +P(561) +P(592) +P(000) diff --git a/external/gpl3/gdb/dist/sim/bfin/sim-main.h b/external/gpl3/gdb/dist/sim/bfin/sim-main.h new file mode 100644 index 000000000000..3a937034817e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/sim-main.h @@ -0,0 +1,117 @@ +/* Simulator for Analog Devices Blackfin processors. + + Copyright (C) 2005-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef _BFIN_MAIN_SIM_H_ +#define _BFIN_MAIN_SIM_H_ + +#include "sim-basics.h" +#include "sim-signal.h" + +typedef unsigned32 sim_cia; + +#define CIA_GET(cpu) CPU_PC_GET (cpu) +#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val)) + +typedef struct _sim_cpu SIM_CPU; + +#include "bfin-sim.h" + +#include "machs.h" + +#include "sim-base.h" + +struct _sim_cpu { + /* ... simulator specific members ... */ + struct bfin_cpu_state state; + sim_cpu_base base; +}; +#define BFIN_CPU_STATE ((cpu)->state) + +struct sim_state { + sim_cpu *cpu[MAX_NR_PROCESSORS]; +#if (WITH_SMP) +#define STATE_CPU(sd,n) ((sd)->cpu[n]) +#else +#define STATE_CPU(sd,n) ((sd)->cpu[0]) +#endif + /* ... simulator specific members ... */ + struct bfin_board_data board; +#define STATE_BOARD_DATA(sd) (&(sd)->board) + sim_state_base base; +}; + +#include "sim-config.h" +#include "sim-types.h" +#include "sim-engine.h" +#include "sim-options.h" +#include "run-sim.h" +#include "dv-bfin_trace.h" + +#undef MAX +#undef MIN +#undef CLAMP +#undef ALIGN +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, b, c) MIN (MAX (a, b), c) +#define ALIGN(addr, size) (((addr) + ((size)-1)) & ~((size)-1)) + +#define MAYBE_TRACE(type, cpu, fmt, ...) \ + do { \ + if (TRACE_##type##_P (cpu)) \ + trace_generic (CPU_STATE (cpu), cpu, TRACE_##type##_IDX, \ + fmt, ## __VA_ARGS__); \ + } while (0) +#define TRACE_INSN(cpu, fmt, ...) MAYBE_TRACE (INSN, cpu, fmt, ## __VA_ARGS__) +#define TRACE_DECODE(cpu, fmt, ...) MAYBE_TRACE (DECODE, cpu, fmt, ## __VA_ARGS__) +#define TRACE_EXTRACT(cpu, fmt, ...) MAYBE_TRACE (EXTRACT, cpu, fmt, ## __VA_ARGS__) +#define TRACE_SYSCALL(cpu, fmt, ...) MAYBE_TRACE (EVENTS, cpu, fmt, ## __VA_ARGS__) +#define TRACE_CORE(cpu, addr, size, map, val) \ + do { \ + MAYBE_TRACE (CORE, cpu, "%cBUS %s %i bytes @ 0x%08x: 0x%0*x", \ + map == exec_map ? 'I' : 'D', \ + map == write_map ? "STORE" : "FETCH", \ + size, addr, size * 2, val); \ + PROFILE_COUNT_CORE (cpu, addr, size, map); \ + } while (0) +#define TRACE_EVENTS(cpu, fmt, ...) MAYBE_TRACE (EVENTS, cpu, fmt, ## __VA_ARGS__) +#define TRACE_BRANCH(cpu, oldpc, newpc, hwloop, fmt, ...) \ + do { \ + MAYBE_TRACE (BRANCH, cpu, fmt " to %#x", ## __VA_ARGS__, newpc); \ + if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT) \ + bfin_trace_queue (cpu, oldpc, newpc, hwloop); \ + } while (0) + +extern void trace_register PARAMS ((SIM_DESC sd, + sim_cpu *cpu, + const char *fmt, + ...)) + __attribute__((format (printf, 3, 4))); +#define TRACE_REGISTER(cpu, fmt, ...) \ + do { \ + if (TRACE_CORE_P (cpu)) \ + trace_register (CPU_STATE (cpu), cpu, fmt, ## __VA_ARGS__); \ + } while (0) +#define TRACE_REG(cpu, reg, val) TRACE_REGISTER (cpu, "wrote "#reg" = %#x", val) + +/* Default memory size. */ +#define BFIN_DEFAULT_MEM_SIZE (128 * 1024 * 1024) + +#endif diff --git a/external/gpl3/gdb/dist/sim/bfin/tconfig.in b/external/gpl3/gdb/dist/sim/bfin/tconfig.in new file mode 100644 index 000000000000..130707a90a8c --- /dev/null +++ b/external/gpl3/gdb/dist/sim/bfin/tconfig.in @@ -0,0 +1,27 @@ +/* Blackfin target configuration file. -*- C -*- */ + +/* See sim-hload.c. We properly handle LMA. -- TODO: check this */ +#define SIM_HANDLES_LMA 1 + +/* We use this so that we are passed the requesting CPU for HW acesses. + Common sim core by default sets hw_system_cpu to NULL for WITH_HW. */ +#define WITH_DEVICES 1 + +/* FIXME: This is unnecessarily necessary: */ +#include "ansidecl.h" +#include "gdb/callback.h" +#include "gdb/remote-sim.h" +#include "sim-module.h" + +/* FIXME: Revisit. */ +#ifdef HAVE_DV_SOCKSER +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, +#endif + +/* ??? Temporary hack until model support unified. */ +#define SIM_HAVE_MODEL + +/* Allows us to do the memory aliasing that some bfroms have: + {0xef000000 - 0xef100000} => {0xef000000 - 0xef000800} */ +#define WITH_MODULO_MEMORY 1 diff --git a/external/gpl3/gdb/dist/sim/common/ChangeLog b/external/gpl3/gdb/dist/sim/common/ChangeLog new file mode 100644 index 000000000000..6a29711a16cb --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/ChangeLog @@ -0,0 +1,5771 @@ +2011-05-17 Mike Frysinger + + * dv-glue.c: Fix up style. + +2011-05-17 Mike Frysinger + + * hw-alloc.c (hw_alloc_data): Adjust brace. + * hw-base.c (hw_base_data): Likewise. + (generic_hw_unit_decode): Fix indentation. + * hw-device.h (_hw_unit, enum, hw): Adjust braces. + * hw-events.c (hw_event, hw_event_data): Likewise. + * hw-handles.c (hw_handle_mapping, hw_handle_data): Likewise. + * hw-instances.c (hw_instance_data): Likewise. + * hw-instances.h (hw_instance): Likewise. + * hw-main.h (hw_descriptor, enum): Likewise. + * hw-ports.c (hw_port_edge, hw_port_data, empty_hw_ports): Likewise. + * hw-ports.h (hw_port_descriptor): Likewise. + * hw-properties.c (hw_property_data): Likewise. + * hw-properties.h (enum, hw_property, _ihandle_runtime_property_spec, + _range_property_spec, _reg_property_spec): Likewise. + * hw-tree.c (_name_specifier, printer): Likewise. + (split_device_specifier, parse_string_property, hw_tree_traverse, + print_size, print_reg_property, print_string, print_properties): + Fix indentation. + +2011-03-29 Mike Frysinger + + * aclocal.m4 (SIM_AC_OPTION_HARDWARE): Add cfi to default list. + * Make-common.in (dv-cfi.o): New rule. + * dv-cfi.c, dv-cfi.h: New files. + +2011-03-21 Kevin Buettner + + * gennltvals.sh: Search sys/_default_fcntl.h, in addition to + fcntl.h and sys/fcntl.h, for constants. + * nltvals.def: Regenerate. + * sim-io.c (sim_io_stat, sim_io_fstat): New functions. + * sim-io.h (sys/types.h, sys/stat.h): Include. + (sim_io_stat, sim_io_fstat): Declare. + +2011-03-14 Mike Frysinger + + * callback.c, cgen-engine.h, dv-core.c, dv-glue.c, dv-pal.c, + hw-base.c, hw-device.c, hw-device.h, hw-handles.c, hw-instances.c, + hw-ports.c, hw-ports.h, hw-properties.c, hw-tree.c, nrun.c, + run-sim.h, run.c, sim-alu.h, sim-assert.h, sim-base.h, sim-basics.h, + sim-config.c, sim-core.c, sim-core.h, sim-engine.h, sim-events.c, + sim-events.h, sim-fpu.c, sim-hw.c, sim-inline.h, sim-load.c, + sim-memopt.c, sim-n-core.h, sim-options.c, sim-profile.c, + sim-signal.c, sim-trace.c, sim-trace.h, sim-utils.c, sim-watch.c, + syscall.c: Trim trailing whitespace. + +2011-03-05 Mike Frysinger + + * gennltvals.sh: Handle bfin targets. + * nltvals.def: Regenerate. + +2011-02-25 Kevin Buettner + + * callback.c (fdbad): Return EBADF rather than EINVAL for bad + file descriptors. + +2011-02-14 Mike Frysinger + + * hw-alloc.c (hw_alloc_data): Delete zalloc_p. + (hw_zalloc, hw_malloc): Delete zalloc_p reference. + (hw_free): Drop zfree logic and always call free. + * hw-base.c (hw_delete): Change zfree to free. + * hw-handles.c (hw_handle_remove_ihandle): Likewise. + (hw_handle_remove_phandle): Likewise. + * hw-instances.c (hw_instance_delete): Likewise. + * hw-tree.c (parse_reg_property): Likewise. + (parse_ranges_property): Likewise. + (parse_string_property): Likewise. + * sim-core.c (sim_core_uninstall): Likewise. + * sim-cpu.c (sim_cpu_free_all): Likewise. + * sim-hw.c (sim_hw_uninstall): Likewise. + * sim-memopt.c (do_memopt_delete): Likewise. + (sim_memory_uninstall): Likewise. + * sim-module.c (sim_module_uninstall): Likewise. + * sim-options.c (sim_parse_args): Likewise. + * sim-profile.c (profile_pc_cleanup): Likewise. + (profile_uninstall): Likewise. + * sim-watch.c (do_watchpoint_delete): Likewise. + * sim-utils.c (zfree): Delete. + (sim_state_free): Change zfree to free. + * sim-utils.h (zfree): Delete. + +2011-02-13 Mike Frysinger + + * sim-events.h (_sim_events.time_from_event): Change type to signed64. + +2011-01-12 Mike Frysinger + + * sim-hw.c (sim_hw_uninstall): Uncomment hw_tree_delete. + +2011-01-12 Mike Frysinger + + * sim-module.c (sim_pre_argv_init): Return SIM_RC_FAIL when asprintf + fails. + * sim-options.c (sim_parse_args): Issue an error and return SIM_RC_FAIL + when asprintf fails. + * sim-utils.c (sim_do_commandf): Issue an error and return when + asprintf fails. + * sim-watch.c (sim_watchpoint_install): Return SIM_RC_FAIL when + asprintf fails. + +2011-01-11 Mike Frysinger + + * sim-memopt.c (do_memopt_add): Set nr_bytes to s.st_size before + bytes has been calculated and when mmap_next_fd is valid and + nr_bytes is 0. + (memory_option_handler): Allow missing size when mmap_next_fd is + valid. + +2011-01-10 Mike Frysinger + + * aclocal.m4 (SIM_AC_OPTION_HARDWARE): Set $hardware to $2 when $2 is + not empty, and always append $3 to $hardware. + +2011-01-10 Mike Frysinger + + * hw-device.h (hw_abort, hw_vabort, hw_halt): Add noreturn attribute. + * sim-hw.h (sim_hw_abort): Likewise. + +2011-01-05 Mike Frysinger + + * sim-load.c (sim_load_file): Change buffer type to unsigned char *. + +2011-01-05 Joel Brobecker + + * run.1: Copyright year update. + +2010-12-28 Mike Frysinger + + * hw-alloc.h (HW_NALLOC): Define. + +010-12-28 Mike Frysinger + + * hw-alloc.h (HW_NZALLOC): Change ME,TYPE,N to me,type,n. + +2010-12-15 Mike Frysinger + + * sim-memopt.c (OPTION_MAP_INFO): Define. + (memory_options): Handle --map-info. + (memory_option_handler): Handle OPTION_MAP_INFO. + +2010-11-22 Mike Frysinger + + * sim-profile.c (PROFILE_PC_FREQ, PROFILE_PC_NR_BUCKETS, + PROFILE_PC_SHIFT, PROFILE_PC_START, PROFILE_PC_END, + PROFILE_INSN_COUNT): Add stubs when profile is disabled. + +2010-11-22 Mike Frysinger + + * sim-core.c (WITH_HW): Add device casts to device_error, + device_io_read_buffer, and device_io_write_buffer. + +2010-11-16 Mike Frysinger + + * dv-sockser.c (dv_sockser_write_buffer): New function. + (dv_sockser_write): Rewrite to use dv_sockser_write_buffer. + * dv-sockser.h (dv_sockser_write_buffer): New prototype. + +2010-10-07 Hans-Peter Nilsson + + * callback.c (os_lseek): Call wrap on lseek result. + +2010-05-26 Ozkan Sezer + + * dv-sockser.c (dv_sockser_init): Check error return from socket() + call by its equality to -1 not by it being negative. + (connected_p): Likewise for accept() call. + +2010-04-23 Mike Frysinger + + * sim-fpu.c (sim_fpu_zero, sim_fpu_qnan): Add 0 initializers. + +2010-04-21 Mike Frysinger + + * profile.c (sim_profile_print_bar): Add cpu argument. + +2010-04-21 Mike Frysinger + + * sim-profile.h (sim_profile_print_bar): Use sim_cpu, not SIM_CPU. + +2010-04-21 Mike Frysinger + + * sim-profile.c (profile_vprintf, profile_printf): New functions. + (profile_print_pc): Convert sim_io_printf to profile_printf. + (profile_print_insn): Likewise. + (profile_print_memory): Likewise. + (profile_print_core): Likewise. + (profile_print_model): Likewise. + (sim_profile_print_bar): Likewise. + (profile_print_speed): Likewise. + (profile_print_addr_ranges): Likewise. + (profile_info): Likewise. + * sim-profile.h (sim_profile_print_bar): Add cpu argument. + +2010-04-19 Mike Frysinger + + * sim-model.c (OPTION_MODEL): Convert to enum. + (OPTION_MODEL_INFO): New enum. + (model_options): Add model-info/info-model entries. + (model_option_handler): Handle OPTION_MODEL_INFO. + +2010-04-13 Mike Frysinger + + * dv-sockser.h (DV_SOCKSER_DISCONNECTED): Define. + * dv-sockser.c (dv_sockser_status): Set DV_SOCKSER_DISCONNECTED + initially. + +2010-04-13 Mike Frysinger + + * sim-hrw.c (sim_write): Add const to buf arg. + * sim-utils.h (sim_write_fn): Likewise. + +2010-04-12 Mike Frysinger + + * sim-profile.h (PROFILE_BRANCH_TAKEN, PROFILE_BRANCH_UNTAKEN): New + defines. + +2010-04-12 Mike Frysinger + + * dv-core.c (dv_core_descriptor): Add NULL initializer. + * dv-glue.c (hw_glue_ports, dv_glue_descriptor): Likewise. + * dv-pal.c (hw_pal_ports, dv_pal_descriptor): Likewise. + * dv-sockser.c (sockser_options): Likewise. + * hw-ports.c (empty_hw_ports): Likewise. + * sim-hw.c (hw_options): Likewise. + * sim-model.c (model_options): Likewise. + * sim-options.c (standard_options): Likewise. + * sim-profile.c (profile_options): Likewise. + * sim-trace.c (trace_options): Likewise. + * sim-watch.c (watchpoint_options): Likewise. + +2010-04-12 Mike Frysinger + + * sim-options.c (dup_arg_p): Add "const" to the "arg" argument, + the local "arg_table" variable, and the xmalloc cast. + +2010-04-10 Mike Frysinger + + * sim-fpu.c (sim_fpu_print_status): Add const markings to local + "prefix" var. + (sim_fpu_print_func): Add const markings to format buffer. + +2010-04-10 Mike Frysinger + + * sim-fpu.c (sim_fpu_print_status): Remove duplicate break statements. + +2010-04-10 Mike Frysinger + + * sim-trace.c (save_data): Add const markings to "buf" argument. + +2010-04-10 Mike Frysinger + + * sim-options.c (standard_option_handler): Add const markings to + local "type" var. + +2010-04-02 Mike Frysinger + + * hw-ports.h: Fix spelling typos. + +2010-03-30 Mike Frysinger + + * configure.ac: Check for socklen_t. + * configure, config.in: Regenerated. + * dv-sockser.c (connected_p): Change addrlen type to socklen_t. + +2010-03-30 Mike Frysinger + + * sim-utils.c (sim_io_eprintf_cpu): Use %s with printf string. + * sim-hw.c (hw_option_handler): Likewise. + +2010-03-30 Mike Frysinger + + * sim-watch.c (watchpoint_type_to_str): Add const to return. + (interrupt_nr_to_str): Likewise. + (default_interrupt_names): Add const to pointer type. + (sim_watchpoint_install): Add const to prefix. + * sim-watch.h (struct _sim_watchpoints): Add const to interrupt_names. + +2010-03-30 Mike Frysinger + + * sim-core.c (sim_core_read_buffer): Change raddr to address_word. + (sim_core_write_buffer): Likewise. + +2010-03-30 Mike Frysinger + + * sim-trace.c (trace_option_handler): Move cpu_nr decl behind + the SIM_HAVE_ADDR_RANGE define. + +2010-03-30 Mike Frysinger + + * sim-core.h (device_error): Add const to message, and add printf + format attribute. + +2010-03-30 Mike Frysinger + + * sim-profile.c (profile_print_addr_ranges): Wrap with the + SIM_HAVE_ADDR_RANGE define. + +2010-03-30 Mike Frysinger + + * dv-glue.c (hw_glue_ports): Swap static and const. + +2010-03-30 Mike Frysinger + + * nrun.c (usage): Use void in definition. + * sim-options.c (dup_arg_p): Convert old-style function definition. + (sim_parse_args): Likewise. + (sim_print_help): Likewise. + * sim-trace.c (set_trace_option_mask): Likewise. + (set_trace_option): Likewise. + * sim-utils.c (sim_analyze_program): Likewise. + (sim_elapsed_time_get): Likewise. + (sim_elapsed_time_since): Likewise. + +2010-03-22 Mike Frysinger + + * sim/common/sim-options.c (enum): Remove SIM_HAVE_BIENDIAN ifdef. + (standard_options): Likewise. + (standard_option_handler): Likewise. + +2010-03-16 Mike Frysinger + + * hw-ports.c (TRACE): Delete. + * hw-properties.c (TRACE): Delete. + (hw_find_ihandle_runtime_property): Change TRACE to HW_TRACE. + (hw_find_integer_property): Likewise. + (hw_find_integer_array_property): Likewise. + (hw_add_duplicate_property): Likewise. + +2010-03-15 Mike Frysinger + + * hw-properties.h (hw_add_boolean_property): Rename "bool" to + "boolean". + +2010-02-04 Mike Frysinger + + * sim-model.c: Include sim-model.h + +2010-02-04 Mike Frysinger + + * sim-base.h: Declare sim_state.cpu as a pointer in the comment. Drop + & from the STATE_CPU() examples. + +2010-01-24 Doug Evans + + * cgen-accfp.c (fextsfdf): New arg how. All callers updated. + (ftruncdfsf, floatsisf, flostsidf, ufloatsisf, fixsfsi, fixdfsi, + ufixsfsi): Ditto. + * cgen-fpu.h (CGEN_FPCONV_KIND): New enum. + (struct cgen_fp_ops): Update signatures of floating point conversion + operations. + + * Make-common.in (CGEN_SIM_DEPS): Define. + (CGEN_INCLUDE_DEPS): Use it. + (CGEN_MAIN_CPU_DEPS): Simplify. + +2010-01-22 Doug Evans + + * cgen-ops.h (SUBWORDXFSI): Fix word ordering. + (SUBWORDTFSI, JOINSIDI): Ditto. + +2010-01-05 Doug Evans + + * cgen-types.h (SETDI): Delete, unused. + +2009-12-02 Doug Evans + + * cgen-engine.h: Remove duplicated comment. + +2009-11-23 Doug Evans + + * cgen-engine.h (EXTRACT_MSB0_SINT): Renamed from EXTRACT_MSB0_INT. + (EXTRACT_LSB0_SINT): Renamed from EXTRACT_LSB0_INT. + +2009-11-22 Doug Evans + + * cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define. + (EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define. + (EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype + instead of CGEN_INSN_INT. + + * cgen-trace.h (trace_extract): Add cast to fix warning. + +2009-11-05 Doug Evans + + * cgen-mem.h (DECLARE_GETT): Don't inline. + (DECLARE_SETT): Ditto. + +2009-10-15 Joel Sherrill + + * sim-inline.h: Fix spelling error. + +2009-10-02 Ralf Corsepius + + * Make-common.in: Add datarootdir. + +2009-08-29 Ralf Wildenhues + + * aclocal.m4 (SIM_CHECK_MEMBER, SIM_CHECK_MEMBERS) + (SIM_CHECK_MEMBERS_1): Remove. + * configure.ac: Replace SIM_CHECK_MEMBERS call with equivalent + AC_CHECK_MEMBERS one. + * configure: Regenerate. + + * aclocal.m4 (SIM_CHECK_MEMBER): Use AU_ALIAS to define, not defn. + * configure: Regenerate. + +2009-08-22 Ralf Wildenhues + + * config.in: Regenerate. + * configure: Likewise. + + * aclocal.m4 (SIM_CHECK_MEMBER): Replace definition with + definition of AC_CHECK_MEMBER. + + * aclocal.m4: m4_include toplevel config/override.m4. + * configure: Regenerate. + +2009-07-30 Ralf Wildenhues + + * Makefile.in (datarootdir): New variable. + +2009-07-07 Doug Evans + + * Make-common.in (CPU_DIR): Define. + +2009-07-06 Doug Evans + + * Make-common.in (CGEN_CPU_EXTR,CGEN_CPU_READ): Pass canonical + identifiers for file types rather than encoding internal + implementation details of cgen.sh. + (CGEN_CPU_WRITE,CGEN_CPU_SEM,CGEN_CPU_SEMSW): Ditto. + * cgen.sh: Add support for parallel makes. + Rewrite cpu/decode handling to avoid generating "extrafiles" twice. + +2009-05-18 Jon Beniston + + * gennltvals.sh: Add lm32 target. + * nltvals.def: Add lm32 syscall definitions. + +2009-03-19 J"orn Rennecke (tiny change) + + Speed up simulator startup: + * sim-utils.c (zalloc): Use xcalloc. + +2009-01-07 Hans-Peter Nilsson + + * cgen-ops.h (ADDQI, SUBQI, MULQI, NEGQI, ABSQI, ADDHI, SUBHI) + (MULHI, NEGHI, ABSHI, ADDSI, SUBSI, MULSI, NEGSI, ABSSI, ADDDI) + (SUBDI, MULDI, NEGDI, ABSDI): Cast arguments to the unsigned type + variant; UQI, UHI, USI, UDI, and cast the result to the signed + type, QI, HI, SI, DI. + + * callback.c (os_error): Mark as being a noreturn function. + * sim-io.h (sim_io_error): Similar for sim_io_error. + +2008-11-12 Joel Sherrill + + * aclocal.m4: Fix underquoting of function names. + +2008-10-21 Julian Brown + + * Make-common.in (run$(EXEEXT)): Add LDFLAGS. + +2008-07-11 Hans-Peter Nilsson + + * common.m4: Add test for libz and zlib.h. + * configure: Regenerate to track ../common/common.m4 changes. + * config.in: Ditto. + +2008-06-06 Vladimir Prus + Daniel Jacobowitz + Joseph Myers + + * aclocal.m4: Include ../../config/acx.m4. + * common.m4: Use ACX_PKGVERSION and ACX_BUGURL. + * configure, config.in: Regenerate. + * Make-common.in (LIB_OBJS): Add version.o. + (version.c, version.o): New rules. + * run.c: Include version.h. + (usage): Add help parameter. Print output either to stdout or + stderr depending on that parameter. + (print_version): New. + (main): Check for --help and --version. + * run-sim.h (sim_target_display_usage): Add help parameter. + * version.h: New. + +2008-04-14 Hans Kester + + * sim-signal.c: Define missing signals for _WIN32. + +2008-02-12 M Ranga Swami Reddy + + * gennltvals.sh: Add cr16. + * nltvals.def: Rebuild. + +2007-10-11 Jesper Nilsson + + * callback.c (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add functions. + * syscall.c (cb_syscall): Test for stdin/out/err, not just fd 0/1/2. + +2007-08-10 Nick Clifton + + * sim-memopt.c (memory_options): Mention that the + --memory-size switch accepts suffixes. + (parse_size): Handle a suffix on the size value. + * sim-options.c (standard_options): Mention that the mem-size + switch accepts suffixes. + (standard_option_handler): Handle a suffix on the size value. + +2006-12-21 Hans-Peter Nilsson + + * acconfig.h: Remove. + * config.in: Regenerate. + +2006-11-07 Thiemo Seufer + + * gentmap.c: Fix compile time warning. + +2006-11-07 Thiemo Seufer + + * sim-base.h (text_start, text_end, start_addr): Use bfd_vma type + for bfd text addresses. + +2006-08-29 Thiemo Seufer + Nigel Stephens + + * sim-fpu.c (pack_fpu): Handle QUIET_NAN correctly for + SIM_QUIET_NAN_NEGATED. + +2006-08-29 Nigel Stephens + + * sim-profile.c (profile_pc_init): Initialise default profiling + frequency to a prime number. + (profile_print_pc): Convert gmon.out sample data into target + byte order. + +2006-06-13 Richard Earnshaw + + * aclocal.m4: Pass ../../intl to ZW_GNU_GETTEXT_SISTER_DIR. + * common.m4: Likewise. + * configure: Regenerated. + +2006-06-05 Daniel Jacobowitz + + * aclocal.m4: Use ZW_GNU_GETTEXT_SISTER_DIR. + * configure: Regenerated. + +2006-05-31 Daniel Jacobowitz + + * Make-common.in: Replace INTLLIBS and INTLDEPS with LIBINTL + and LIBINTL_DEP everywhere. + (CSEARCH): Use INCINTL. + * aclocal.m4: Use ZW_GNU_GETTEXT_SISTER_DIR. Include new + gettext macros. + * configure: Regenerated. + +2006-03-29 Hans-Peter Nilsson + + * aclocal.m4 (SIM_AC_OPTION_HARDWARE): Correct duplicate- + option-contents test. + +2005-11-28 Mark Mitchell + + * sim-signal.c (sim_signal_to_target): Fix typos. + + * sim-reason.c (sim_stop_reason): Use + sim_signal_to_target, not sim_signal_to_host. + * sim-signal.c (sim_signal_to_host): Fix typo. + (sim_signal_to_target): New function. + +2005-07-10 Hans-Peter Nilsson + + * sim-load.c (xprintf, eprintf): Remove fallout from ANSI_PROTOTYPES + change. + +2005-07-08 Ian Lance Taylor + + * sim-fpu.c (sim_fpu_abs): Always clear the sign bit. + + * sim-fpu.c (pack_fpu): If SIM_QUIET_NAN_NEGATED is defined, use a + different fraction for a quiet NaN. + (unpack_fpu): Likewise. + +2005-07-08 Ben Elliston + + * callback.c: Remove ANSI_PROTOTYPES conditional code. + * sim-load.c: Likewise. + * syscall.c: Likewise. + +2005-05-24 Corinna Vinschen + + * Make-common.in (LIBDEPS): Correctly use INTLDEPS for dependency + check. + +2005-05-17 Daniel Jacobowitz + + * Make-common.in (install-common, installdirs): Honor $DESTDIR. + +2005-04-20 Manoj Iyer + + * sim-types.h: Changed unsigned32 and unsigned64 to signed32 + and signed64 for __ALPHA__. + +2005-03-23 Mark Kettenis + + * aclocal.m4 Include ../../gettext.m4. + (CY_WITH_NLS, CY_GNU_GETTEXT, AM_PATH_PROG_WITH_TEST) + (AM_LC_MESSAGES): Remove. + * configure: Regenerate. + +2005-02-28 Jim Blandy + + * aclocal.m4 (SIM_AC_OPTION_WARNINGS): Don't include + -Wuninitialized in the default list of build warnings if CFLAGS is + set, and doesn't include -O. (Using -Wuninitialized without + optimization produces a warning, which interferes with compilation + with -Werror.) + +2005-02-21 Jim Blandy + + * callback.c (os_fstat): Don't declare 't' unless it's used. + +2005-02-09 Jim Blandy + + * Make-common.in (CGEN): Load guile.scm, and include a trailing + '-s' argument. + (CGEN_FLAGS_TO_PASS): Include single quotes around the reference + to $(CGEN), to ensure that the command substitution happens where + the variable is referenced in the submake, not when the submake's + arguments are expanded. + (cgen.sh): Be prepared for the 'cgen' argument to contain spaces. + (arch, cpu, decode, cpu-decode, defs, desc): Place the name of the + application Scheme script directly after ${cgen}; don't precede it + with a -s. + +2005-01-28 Hans-Peter Nilsson + + * syscall.c (cb_syscall) : New case. + * callback.c [HAVE_LIMITS_H]: Include limits.h. + Include libiberty.h. + (os_close, os_read, os_write, os_fstat, os_ftruncate): Support fd + being either end of a pipe. + (os_pipe, os_pipe_empty, os_pipe_nonempty): New functions. + (os_shutdown): Clear pipe state. + (default_callback): Initialize new members. + + * callback.c (default_callback): Initialize target_endian. + (cb_store_target_endian): Renamed from store, new first parameter + host_callback *cb, drop last parameter big_p. Take endianness + from cb. + (cb_host_to_target_stat): Change to use cb_store_target_endian. + Remove variable big_p. + * nrun.c (main): Initialize default_callback.target_endian. + +2005-01-14 Andrew Cagney + + * configure.ac: Replace SIM_AC_COMMON with sinclude of common.m4. + Add explicit call to AC_CONFIG_HEADER. + * common.m4: Delete call to AC_CONFIG_HEADER, update usage. + * configure: Re-generate. + +2005-01-12 Andrew Cagney + + * common.m4: New file, based on of aclocal.m4. + +2005-01-11 Andrew Cagney + + * aclocal.m4 (SIM_AC_OUTPUT): Rewrite to use 2.59 macros. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * aclocal.m4 (SIM_AC_COMMON): Delete call to AC_CONFIG_AUX_DIR. + * configure: Re-generate. + +2004-12-15 Hans-Peter Nilsson + + * syscall.c (cb_syscall) + : New cases. + +2004-12-13 Hans-Peter Nilsson + + * syscall.c (cb_syscall) : New case. + (cb_syscall) : New case. + * callback.c (os_lstat): New function. + +2004-12-08 Hans-Peter Nilsson + + * run.1: Document --sysroot=filepath. + * sim-options.c (STANDARD_OPTIONS): New member OPTION_SYSROOT. + (standard_options): Support --sysroot=. + (standard_option_handler): Handle OPTION_SYSROOT. + * syscall.c (simulator_sysroot): Define, initialized empty. + (get_path): Prepend simulator_sysroot to absolute file path. + [HAVE_STRING_H]: Include string.h. + [!HAVE_STRING_H && HAVE_STRINGS_H]: Include strings.h. + * nrun.c [HAVE_UNISTD_H]: Include unistd.h. + (main): If simulator_sysroot is not empty, chdir there. + * sim-config.h (simulator_sysroot): Declare. + + * aclocal.m4 (SIM_AC_OUTPUT): Substitute @cgen_breaks@ for "break + cgen_rtx_error" in a CGEN-generated simulator. + * gdbinit.in: Break on sim_core_signal too. Have autoconf + replacement for CGEN-related breakpoints. + +2004-12-07 Hans-Peter Nilsson + + * Make-common.in (sim-basics_h): Add $(callback_h). + +2004-12-03 Hans-Peter Nilsson + + * configure.in (SIM_CHECK_MEMBERS): Call for struct stat members + st_dev, st_ino, st_mode, st_nlink, st_uid, st_gid, st_rdev, + st_size, st_blksize, st_blocks, st_atime, st_mtime and st_ctime. + * aclocal.m4 (SIM_CHECK_MEMBER, SIM_CHECK_MEMBERS_1) + (SIM_CHECK_MEMBERS): New macros. + * callback.c (cb_host_to_target_stat): Use temporary macro ST_x + for struct stat member test and write. Add ST_x calls for each + struct stat member tested in configure.in. Wrap each ST_x call in + #ifdef of configure macro for that member. + * configure, config.in: Regenerate. + +2004-12-01 Hans-Peter Nilsson + + * cgen.sh: New thirteenth parameter opcfile, defaulting to + /dev/null. + : Pass -OPC opcfile. + * Make-common.in (cgen-desc): Pass $(opcfile) as thirteenth + parameter to cgen.sh. + +2004-11-30 Richard Earnshaw + + * Make-common.in (sim-basics_h): Correct dependencies on + cconfig.h and tconfig.h + (sim-load.o): Correct typo in sim-basics_h dependency. + +2004-11-18 Richard Earnshaw + + * Make-common.in (sim-*_h): Add macros for all sim headers listing + sub-dependencies for other sim files that they include. + (sim_main_headers): Use sim-*_h macros. + (sim-load.o): Depend on sim-basics_h, not sim_main_headers. + +2004-11-16 Hans-Peter Nilsson + + * sim-config.c (sim_config): Recognize when a bfd has unspecified + endian information. + + * Make-common.in (sim-load.o): Depend on $(sim_main_headers) and + $(remote_sim_h) too. + (sim_main_headers): Add sim-utils.h. + +2004-10-07 Kazuhiro Inaoka + + * cgen-defs.h (ENDSWITCH): Changed to compile with gcc-3.4.2. + +2004-07-26 Andrew Cagney + + Problem from Olaf Hering . + * Makefile.in (install-man, installdirs): Add DESTDIR prefix. + +2004-07-10 Ben Elliston + + * hw-tree.c (parse_integer_property): Typo fix in comments. + * sim-options.c (sim_args_command): Likewise. + +2004-06-28 Andrew Cagney + + * run.c: Rename ui_loop_hook to deprecated_ui_loop_hook. + +2004-06-27 J"orn Rennecke + + * callback.c (os_shutdown): Fix bug in last change: actually + mark file descriptors as available on startup. + +2004-06-25 J"orn Rennecke + + [ include/gdb: * callback.h (host_callback_struct): Replace + members fdopen and alwaysopen with fd_buddy. ] + * callback.c: Changed all users. + +2004-06-15 Alan Modra + + * sim-load.c (sim_load_file): Use bfd_get_section_size + instead of bfd_get_section_size_before_reloc. + +2004-05-18 Daniel Jacobowitz + + * dv-glue.c (hw_glue_finish): Cast result of sizeof to long before + passing it to printf. + +2004-05-10 Daniel Jacobowitz + + * callback.c: Update copyright dates. + * run.c: Likewise. + * sim-basics.h: Likewise. + * sim-load.c: Likewise. + * syscall.c: Likewise. + +2004-05-10 Maciej W. Rozycki + + * callback.c: Include cconfig.h instead of config.h. + * run.c: Likewise. + * sim-basics.h: Likewise. + * sim-load.c: Likewise. + * syscall.c: Likewise. + +2004-01-16 Ben Elliston + + * Makefile.in (clean): Remove rm -f $(ALL), as $(ALL) is empty. + +2003-12-19 Kazuhiro Inaoka + + * sim-core.c (sim_core_trans_addr): Added for m32r-linux-run. + +2003-11-22 Kazu Hirata + + * sim-options.c (standard_options): Fix the names of H8 + variants. + +2003-10-30 Andrew Cagney + + * sim-trace.c, sim-base.h: Replace "struct symbol_cache_entry" + with "struct bfd_symbol". + +2003-10-21 Andrew Cagney + + * callback.c (os_truncate): Call "truncate", and not "stat". + +2003-10-20 Andrew Cagney + + * sim-base.h: Replace "struct sec" with "struct bfd_section". + +2003-10-15 J"orn Rennecke + + * callback.c (os_ftruncate, os_truncate): New functions. + (default_callback): Initialize ftruncate and truncate members. + +2003-09-08 Dave Brolley + + On behalf of Doug Evans + * cgen.sh: New arg archfile. + * Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode, + cgen-cpu-decode,cgen-desc): Update call to cgen.sh. + +2003-08-28 Andrew Cagney + + * dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof. + * sim-options.c (print_help): Cast the format with specifier to + "int". + +2003-08-20 Michael Snyder + Dave Brolley + + * cgen-par.h (flags, word1): New target-specific + fields of CGEN_WRITE_QUEUE_ELEMENT. + (CGEN_WRITE_QUEUE_ELEMENT_FLAGS): New accessor macro. + (CGEN_WRITE_QUEUE_ELEMENT_WORD1): New accessor macro. + * gennltvals.sh: Add frv target. + * nltvals.def: Add frv target. + +2003-06-23 Michael Snyder + + * nrun.c (main): Delete h8/300 ifdef (sim now handles signals). + * sim-reg.c: Fix cut-and-paste bug in comment. + +2003-06-22 Andrew Cagney + + From matthew green : + * sim-fpu.h: Update copyright. + (sim_fpu_fraction, sim_fpu_guard): New prototypes. + * sim-fpu.c: Update copyright. + (sim_fpu_fraction, sim_fpu_guard): New inline functions. + +2003-06-17 Frank Ch. Eigler + + From Doug Evans : + * cgen-trace.h (sim_disasm_read_memory): Update args to be compatible + with disassemble_info:read_memory_func. + * cgen-trace.c (sim_disasm_read_memory): Ditto. + +2003-06-04 Michael Snyder + + * common/run.c (main): Remove SIM_H8300 ifdef. + (usage): Ditto. + * common/sim-options.c (STANDARD_OPTIONS): Add SIM_H8300SX. + (standard_options): Add '-x' for h8/300sx. + (standard_option_handler): Add case for SIM_H8300SX. + +2003-04-13 Michael Snyder + + * Make-common.in (sim-events.o, sim-config.o): Depend on sim-main.h. + +2003-03-01 Andrew Cagney + + * sim-engine.c (sim_engine_halt): If jmpbuf is invalid, abort. + (sim_engine_vabort): Ditto. + +2003-02-27 Andrew Cagney + + * sim-utils.h (sim_analyze_program, sim_load_file): Rename _bfd to bfd. + * sim-hload.c (sim_load), sim-base.h (sim_state_base): Ditto. + * nrun.c (main): Ditto. + +2003-02-26 Andrew Cagney + + * sim-engine.h (sim_engine_abort): Add noreturn attribute. + (sim_engine_vabort): Ditto. + (sim_engine_halt, sim_engine_restart): Ditto. + +2003-02-20 Andrew Cagney + + * Make-common.in (SIM_NEW_COMMON_OBJS): Remove sim-break.o + (sim-break_h): Delete macro. + (sim-break.o): Delete rule. + * sim-break.c: Delete file. + * sim-break.h: Delete file. + * sim-base.h [SIM_HAVE_BREAKPOINTS]: Don't include "sim-break.h". + (STATE_BREAKPOINTS): Delete macro. + (sim_state_base): Delete field breakpoints. + * sim-module.c (modules) [SIM_HAVE_BREAKPOINTS]: Don't add + sim_break_install to array. + +2003-01-08 Kazu Hirata + + * run.c (usage): Fix typos. + +2002-11-27 Richard Sandiford + + * sim-fpu.c (sim_fpu_inv): Use sim_fpu_div. + +2002-11-22 Andrew Cagney + + * dv-core.c: Update copyright. sim/common contributed to the FSF. + * dv-glue.c, dv-pal.c, hw-base.c, hw-base.h, hw-device.c: Ditto. + * hw-device.h, hw-handles.c, hw-handles.h: Ditto. + * hw-instances.c, hw-instances.h, hw-properties.c: Ditto. + * hw-properties.h, hw-tree.c, hw-tree.h, sim-alu.h: Ditto. + * sim-basics.h, sim-bits.c, sim-bits.h, sim-config.c: Ditto. + * sim-config.h, sim-core.c, sim-core.h, sim-endian.c: Ditto. + * sim-endian.h, sim-events.c, sim-events.h, sim-inline.c: Ditto. + * sim-inline.h, sim-io.c, sim-io.h, sim-n-bits.h: Ditto. + * sim-n-core.h, sim-n-endian.h, sim-types.h: Ditto. + +2002-11-13 Andrew Cagney + + * run.c (main): Remove SIM_HAVE_ENVIRONMENT from #endif. + +2002-11-06 Richard Sandiford + + * Make-common.in (SIM_EXTRA_DISTCLEAN): New macro. + (distclean): Depend on it. + +2002-10-14 Alan Modra + + * cgen-trace.h: Test __BFD_H_SEEN__ rather than BFD_VERSION. + +2002-08-29 Dave Brolley + + * Make-common.in (CGEN_READ_SCM): Remove ../../cgen/stamp-cgen. + +2002-07-17 Andrew Cagney + + * run-sim.h: Add #ifdef RUN_SIM_H wrapper. + (sim_set_callbacks, sim_size, sim_trace) + (sim_set_trace, sim_set_profile_size, sim_kill): Declare. Moved + to here from "gdb/remote-sim.h". + +2002-07-16 Andrew Cagney + + * sim-resume.c (sim_resume): Add local variable sig_to_deliver to + avoid possible longjmp problems with automatic variable siggnal. + +2002-07-14 Andrew Cagney + + From 2002-07-11 Momchil Velikov : + * Make-common.in (installdirs): Make $(libdir) too, needed when + installing libsim.a. + +2002-07-13 Andrew Cagney + + * gennltvals.sh (dir): Mark d30v as obsolete. + * nltvals.def: Remove d30v. + +2002-06-17 Andrew Cagney + + * hw-events.c (hw_event_queue_schedule): Initialize `dummy'. + + * sim-memopt.c: Include . + (do_memopt_add): Fix printf format. + * sim-events.c (sim_events_schedule): Initialize ``dummy''. + +2002-06-16 Andrew Cagney + + * aclocal.m4 (SIM_AC_OPTION_WARNINGS): Update to match GDB's + --enable-gdb-build-warnings. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2002-06-09 Aldy Hernandez + + * sim-fpu.c (unpack_fpu): Initialize exponent for + sim_fpu_class_zero. + (i2fpu): Same. + (sim_fpu_sqrt): Same. + +2002-06-08 Andrew Cagney + + * gentmap.c (gen_targ_map_c): Generate "gdb/callback.h". + * sim-basics.h: Include "gdb/callback.h" and "gdb/remote-sim.h". + * run.c: Ditto. + * sim-load.c: Ditto. + * callback.c: Ditto. + * syscall.c: Ditto. + * Make-common.in (callback_h): Define. + (remote_sim_h): Define. + (run.o): Update. + (callback.o): Update. + (syscall.o): Update. + (sim-load.o): + (nrun.o): Update. + (sim-hload.o): Update. + (sim-io.o): Update. + (sim-reason.o): Update. + (sim-reg.o): Update. + (sim-resume.o): Update. + +2002-05-30 Kazu Hirata + + * run.c: Fix formatting. + +2002-05-20 Nick Clifton + + * run-sim.h: New header. Provide prototypes for functions used + between run() and libsim.a which are not used by GDB. + * run.c: Include run-sim.h. + (main): If SIM_TARGET_SWITCHES is defined call + sim_target_parse_command_line. + (usage): If SIM_TARGET_SWITCHES is defined call + sim_target_display_usage. + +2002-05-17 Andrey Volkov + + * run.c: Made h8300s as new target, not h8300h alias. + Added new option -S (h8300s target) + * sim-options.c: Ditto. + +2002-05-01 Chris Demetriou + + * callback.c: Use 'deprecated' rather than 'depreciated.' + +2002-02-24 Andrew Cagney + + From wiz at danbala: + * sim-fpu.h: Fix grammar and typos. + Fix PR gdb/287. + +2002-02-10 Chris Demetriou + + * callback.c: Fix some spelling errors. + * hw-device.h: Likewise. + * hw-tree.c: Likewise. + * sim-abort.c: Likewise. + * sim-alu.h: Likewise. + * sim-core.h: Likewise. + * sim-events.c: Likewise. + * sim-events.h: Likewise. + * sim-fpu.h: Likewise. + * sim-profile.h: Likewise. + * sim-utils.c: Likewise. + +2002-01-31 Hans-Peter Nilsson + + * cgen-ops.h (ADDCQI, ADDCFQI, ADDOFQI, SUBCQI, SUBCFQI, SUBOFQI): + New functions. + +2002-01-20 Ben Elliston + + * sim-fpu.h (SIM_FPU_IS_QNAN): Replace "Quite" with "Quiet" in + the comment for this enumerator. + +2002-01-14 Ben Elliston + + * sim-fpu.h: Fix comment about sim_fpu_* constants. + +2001-12-20 Kazu Hirata + + * run.c (usage): Fix a typo. + +2001-07-05 Ben Elliston + + * Make-common.in (srccgen): Remove. + (CGEN_CPU_DIR): Define. + (CGEN_READ_SCM): Redefine without $(srccgen). + (CGEN_ARCH_SCM): Ditto. + (CGEN_CPU_SCM): Ditto. + (CGEN_DECODE_SCM): Ditto. + (CGEN_DESC_SCM): Ditto. + +2001-04-25 Frank Ch. Eigler + + * sim-load.c (sim_load_file): Put it back: external now. + * sim-utils.c (sim_analyze_program): Ditto. Nyuk nyuk nyuk. + +2001-04-21 Andrew Cagney + + * sim-load.c (sim_load_file): Delete call bfd_cache_close. BFD + internal interface. + * sim-utils.c (sim_analyze_program): Ditto. + +2001-04-19 Frank Ch. Eigler + + * sim-utils.c (sim_analyze_program): Call bfd_cache_close after + we're finished with its immediate use. + * sim-load.c (sim_load_file): Ditto. + +2001-03-16 Frank Ch. Eigler + + Add support for mmap-based memory regions. + * sim-memopt.c (mmap_next_fd): New global. + (sim_memory_init): Reinitialize it. + (OPTION_MEMORY_MAPFILE, memory_option_handler): Support new + "--memory-mapfile FILE" option. Check for some errors. + (do_memopt_add): Conditionally do mmap instead of malloc for + backing store of simulated memory. Check for more errors. + (do_simopt_delete, sim_memory_uninstall): Corresponding cleanup. + * sim-memopt.h (munmap_length): New member of _sim_memopt. + * configure.in: Look for mmap/fstat related functions and headers. + * config.in, configure: Regenerated. + +2001-03-15 Frank Ch. Eigler + + * sim-core.c (sim_core_map_attach): Correct overlap-related + error messages. + +2001-03-07 Michael Meissner + + * run.c (alloca-conf.h): Delete, no longer provided. + +2001-02-22 Ben Elliston + + * sim-trace.h (TRACE_VPU_IDX): Add. + (TRACE_vpu): Define. + (WITH_TRACE_VPU_P): Likewise. + (TRACE_VPU_P): Likewise. + * sim-trace.c (OPTION_TRACE_VPU): Define. + (trace_options): Add --trace-vpu. + (trace_option_handler): Handle OPTION_TRACE_VPU. + (trace_option_handler): Include VPU tracing in --trace-semantics. + (trace_idx_to_str): Handle TRACE_VPU_IDX. + +2001-02-21 Ben Elliston + + * sim-trace.h (TRACE_BRANCH_INPUT1): New macro. + (TRACE_BRANCH_INPUT2): Likewise. + +2001-02-09 Ben Elliston + + * (profile_print_pc): Write header out in target byte order. + +2001-02-09 Ben Elliston + + * sim-profile.c (profile_pc_init): Correct bug in loop logic when + adjusting the pc shift value. + +2001-01-12 Chris Demetriou + + * aclocal.m4 (SIM_AC_OPTION_SCACHE): Properly handle the case + where a numeric value is supplied. + +2001-01-06 Ben Elliston + + * cgen.sh: Allow extrafiles to include the semantics files when + generating an ISA-specific decoder. + +2000-12-27 Alexandre Oliva + + * Make-common.in (sim-io.o): Depend on targ-vals.h. + +2000-12-23 Ben Elliston + + * cgen-trace.c (trace_result): Handle 'f' type operands; output + them to the trace stream using sim_fpu_printn_fpu. Include + "sim-fpu.h". + +2000-12-15 Ben Elliston + + * sim-fpu.h (sim_fpu_printn_fpu): Declare. + * sim-fpu.c (print_bits): Add digits parameter. Print only as many + trailing digits as specified (-1 to print all digits). + (sim_fpu_print_fpu): New wrapper around sim_fpu_printn_fpu. + (sim_fpu_printn_fpu): Rename from sim_fpu_print_fpu; update calls + to print_bits (). + +2000-12-13 Ben Elliston + + * cgen.sh: Set prefix/PREFIX (append ISA if applicable). Factor + sed expressions into $sedscript, substituting @prefix@/@PREFIX@. + (defs): New action. + +2000-12-12 Geoffrey Keating + + * sim-endian.h: Don't have parameters on macro definitions which + are simply renaming functions, to permit use of XCONCAT2 in both + the macro name and the arguments in a use of such a definition. + +2000-12-11 Ben Elliston + + * cgen-ops.h (SUBWORDDFDI): New function. + +2000-12-05 Ben Elliston + + * Make-common.in (cgen-defs): New target. + (cgen-decode): Pass $(EXTRAFILES). + + * genmloop.sh: Use @prefix@, not @cpu@ throughout. Add -prefix and + -outfile-suffix options. + +2000-12-04 Ben Elliston + + * cgen-ops.h (SUBWORDSIQI): Mask off top bits. + (SUBWORDSIUQI): Likewise. + (SUBWORDDIHI): Likewise. + (SUBWORDDIQI): New function. + + * cgen-trace.c (disassemble_insn): Remove unused declaration. + * cgen-scache.c (scache_option_handler): Remove unused local var. + +2000-12-03 Ben Elliston + + * sim-profile.c (profile_option_handler): Remove unused prof_nr. + +2000-11-26 Stephane Carrez + + * hw-events.c (delete_hw_event_data): Remove the scheduled events. + +2000-11-26 Stephane Carrez + + * dv-core.c (dv_core_attach_address_callback): Don't abort if + space is not zero. + +2000-11-24 Stephane Carrez + + * hw-base.c (hw_delete): Don't free base_of_hw since it's freed. + (set_hw_delete): Moved the macro as a function. + * hw-base.h (set_hw_delete): Declare as external function. + * hw-alloc.c (delete_hw_alloc_data): Allow to free the memory + allocated using hw_malloc. + +2000-11-24 Stephane Carrez + + * sim-options.c (sim_parse_args): Free the memory used for + long_options, short_options, handlers, opt_cpu, orig_val. + +2000-11-20 Ben Elliston + + * cgen-ops.h (SUBBI): New macro. + (SUBWORDSIQI, SUBWORDSIHI, SUBWORDSIUQI): New functions. + (SUBWORDDIHI, SUBWORDDIUQI, SUBWORDDIDF): Likewise. + +2000-11-16 Ben Elliston + + * cgen-types.h (VOID): New type. + +2000-11-09 Ben Elliston + + * sim-fpu.c (sim_fpu_one): Set exponent to 0. + (sim_fpu_two): Set exponent to 1. + +2000-10-26 Ben Elliston + + * cgen.sh: Handle an isa argument between cpu and mach. Default to + `all'. Pass `-i' options to cgen applications. + * Make-common.in (cgen-arch, cgen-cpu, cgen-decode, cgen-cpu-decode, + cgen-desc): Pass $(isa) to cgen.sh. + +2000-10-08 Ben Elliston + + * cgen-utils.c (cgen_rtx_error): New function. + +2000-10-07 Ben Elliston + + * cgen-trace.c (sim_cgen_disassemble_insn): Handle failure + conditions for sim_core_read_buffer(). + +2000-09-26 Dave Brolley + + * cgen-utils.c (RORQI): New function. + (ROLQI): New function. + (RORHI): New function. + (ROLHI): New function. + +2000-08-28 Dave Brolley + + * cgen-trace.c (sim_cgen_disassemble_insn): Make sure entire insn is + in insn_value if it will fit. + +2000-08-21 Frank Ch. Eigler + + * Make-common.in, cgen.sh: Contribute CGEN-related build targets/rules. + +2000-08-15 Dave Brolley + + * sim-profile.c (profile_print_speed): Print cpu frequency if not zero. + +2000-08-15 Dave Brolley + + * sim-profile.h (PROFILE_DATA): Add cpu_freq. + (PROFILE_CPU_FREQ): New macro. + * sim-profile.c (OPTION_PROFILE_CPU_FREQUENCY): New enumerator. + (profile-options): Add profile-cpu-frequency. + (parse_frequency): New function. + (profile_option_handler): Handle OPTION_PROFILE_CPU_FREQUENCY. + (profile_print_speed): Print cpu frequency and simulated execution time. + Re-indent other items to match. + +2000-08-09 Andrew Cagney + + * dv-sockser.c (dv_sockser_init): Eliminate MIN macro. + +2000-07-27 Frank Ch. Eigler + + From Maciej W. Rozycki + * Makefile.in (install): Install run.1 man page. + +Thu Jul 27 21:56:08 2000 Andrew Cagney + + From 2000-06-23 Doug Evans : + * Makefile.in (headers,nltvals.def): Merge. + +Thu Jul 27 20:37:47 2000 Andrew Cagney + + From 2000-06-25 Stephane Carrez : + * nrun.c (main): Print the simulator statistics only in + verbose mode. + * hw-properties.h (hw_find_integer_array_property): Fix + prototype (use signed_cell). + + From 2000-06-25 Stephane Carrez : + * sim-events.c (sim_events_remain_time): New function returning + the time that remains before the event is raised. + * hw-events.c (hw_event_remain_time): Likewise. + * sim-events.h (sim_events_remain_time): Declare. + * hw-events.h (hw_event_remain_time): Declare. + + From 2000-06-25 Stephane Carrez : + * sim-hw.c: Use instead of + (OPTION_HW_LIST): New option --hw-list to list the devices. + (hw_option_handler): List the device tree with 'sim_hw_print'. + + From 2000-06-25 Stephane Carrez : + * sim-bits.h (_MSB_16, _LSB_16): Define for 16-bit targets. + (MASK, LSBIT, MSBIT): Likewise and use _MSB_16 and _LSB_16. + (EXTENDED): Define for 16-bit word size. + * sim-bits.c (LSEXTRACTED, MSEXTRACTED, LSINSERTED, + MSINSERTED, LSSEXT, MSSEXT): Implement for 16-bit word size. + * sim-types.h: Added support for 16-bit targets. + +2000-06-23 Frank Ch. Eigler + + * cgen-trace.h (TRACE_USEFUL_MASK): Remove TRACE_EVENTS_IDX. + +2000-06-24 Frank Ch. Eigler + + From Maciej W. Rozycki : + * Makefile.in (distclean): Clean cconfig.h also. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue May 23 21:35:53 2000 Andrew Cagney + + * aclocal.m4 (sim-profile): Enable the profiler by default. + +Tue May 23 20:30:12 2000 Andrew Cagney + + * run.c (main): Initialize sigrc. + +Wed Apr 26 16:18:44 2000 Andrew Cagney + + * sim-events.c (update_time_from_event): Add more detailed event + tracing. + +2000-03-30 Dave Brolley + + * aclocal.m4 (cgen): Use guile to run cgen. + +2000-03-23 Dave Brolley + + * cgen-fpu.h: Rename extsfdf to fextsfdf. Rename truncdfsf to + ftruncdfsf. + * cgen-accfp.c (fextsfdf): New function. + (ftruncdfsf): New function. + (cgen_init_accurate_fpu): Initialize fextsfdf and ftruncdfsf. + +2000-03-13 Jeff Johnston + + * cgen-ops.h: Added TRUNCSISI. + +2000-03-08 Dave Brolley + + * cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_SF_WRITE. + (CGEN_WRITE_QUEUE_ELEMENT): Add fn_sf_write. + (sim_queue_fn_si_write): Last argument is has type USI. + (sim_queue_fn_sf_write): New function. + * cgen-par.c (sim_queue_fn_si_write): Declare 'value' as USI. + (sim_queue_fn_sf_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_SF_WRITE. + +Tue Feb 22 16:45:09 2000 Andrew Cagney + + * run.c (main): When SIM_HAVE_ENVIRONMENT enable tracing with + sim_set_trace and run simulator using sim_resume. + (main): Add option ``-o'' - operating environment. Only continue + after a signal when operating environment. + (main): Always set REASON and SIGRC using sim_stop_reason. + (sim_trace): Delete extern declaration. + +2000-02-08 Nick Clifton + + * callback.c: Fix compile time warning messages. + * run.c: Fix compile time warning messages. + +1999-12-17 Dave Brolley + + * sim-profile.h: (set_profile_option_mask): Add prototype. + * sim-profile.c (set_profile_option_mask): No longer static. + +Wed Dec 8 21:47:13 1999 Andrew Cagney + + * sim-arange.c: Include + +1999-12-07 Dave Brolley + + * sim-options.c (print_help): '=' required before optional argument. + * cgen-par.h (CGEN_FN_MEM_QI_WRITE): New enumerator. + (CGEN_FN_MEM_HI_WRITE): New enumerator. + (CGEN_FN_MEM_SI_WRITE): New enumerator. + (CGEN_FN_MEM_DI_WRITE): New enumerator. + (CGEN_FN_MEM_DF_WRITE): New enumerator. + (CGEN_FN_MEM_XI_WRITE): New enumerator. + (fn_mem_qi_write): New union members. + (fn_mem_hi_write): New union members. + (fn_mem_si_write): New union members. + (fn_mem_di_write): New union members. + (fn_mem_df_write): New union members. + (fn_mem_xi_write): New union members. + (sim_queue_fn_mem_qi_write): New function. + (sim_queue_fn_mem_hi_write): New function. + (sim_queue_fn_mem_si_write): New function. + (sim_queue_fn_mem_di_write): New function. + (sim_queue_fn_mem_df_write): New function. + (sim_queue_fn_mem_xi_write): New function. + * cgen-par.c (sim_queue_fn_mem_qi_write): New function. + (sim_queue_fn_mem_hi_write): New function. + (sim_queue_fn_mem_si_write): New function. + (sim_queue_fn_mem_di_write): New function. + (sim_queue_fn_mem_df_write): New function. + (sim_queue_fn_mem_xi_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_MEM_QI_WRITE, + CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, CGEN_FN_MEM_DI_WRITE, + CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE. + +1999-12-01 Dave Brolley + + * cgen-accfp.c (subsf): Check status code. + (mulsf): Ditto. + (negsf): Ditto. + (abssf): Ditto. + (sqrtsf): Ditto. + (invsf): Ditto. + (minsf): Ditto. + (maxsf): Ditto. + (subdf): Ditto. + (muldf): Ditto. + (divdf): Ditto. + (negdf): Ditto. + (absdf): Ditto. + (sqrtdf): Ditto. + (invdf): Ditto. + (mindf): Ditto. + (maxdf): Ditto. + +1999-11-26 Dave Brolley + + * cgen-par.h (fn_df_write): Mode of data is DF. + (sim_queue_fn_df_write): Mode of data is DF. + * cgen-par.c (sim_queue_fn_df_write): Mode of data is DF. + +1999-11-22 Dave Brolley + + * cgen-trace.c (SIZE_TRACE_BUF): Inxrease size of trace buffer. + * cgen-par.h (CGEN_WRITE_QUEUE_SIZE): Increase size of queue. + +1999-11-04 Dave Brolley + + * cgen-par.h (cgen_write_queue_kind): Add CGEN_FN_XI_WRITE and + CGEN_MEM_XI_WRITE members. + (CGEN_WRITE_QUEUE_ELEMENT): Add fn_xi_write and mem_xi_write members. + (sim_queue_fn_xi_write): New function. + (sim_queue_mem_xi_write): New function. + + * cgen-par.c (sim_queue_fn_xi_write): New function. + (sim_queue_mem_xi_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_XI_WRITE and + CGEN_MEM_XI_WRITE. + +1999-10-22 Dave Brolley + + * cgen-par.h (insn_address): New field in CGEN_WRITE_QUEUE_ELEMENT. + (CGEN_WRITE_QUEUE_ELEMENT_IADDR): New macro. + * cgen-par.c: Set insn_address for each queued write. Get pc from + cpu when executing queued writes. + +1999-10-19 Dave Brolley + + * cgen-par.h (sim_queue_fn_pc_write): New function. + (CGEN_FN_PC_WRITE): New enumerator. + (fn_pc_write): New union member. + * cgen-par.c (sim_queue_fn_pc_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_PC_WRITE. + +1999-10-18 Dave Brolley + + * cgen-par.h (CGEN_MEM_DI_WRITE): New enumerator. + (CGEN_MEM_DF_WRITE): New enumerator. + (mem_di_write): New union member. + (mem_df_write): New union member. + * cgen-par.c (sim_queue_mem_di_write): New function. + (sim_queue_mem_df_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_MEM_DI_WRITE and + CGEN_MEM_DF_WRITE. + * cgen-accfp.c (divsf): Check for division errors. + +1999-10-14 Doug Evans + + * cgen-engine.h (EXTRACT_INT,EXTRACT_UINT): Delete. + +1999-10-07 Dave Brolley + + * cgen-par.h (CGEN_FN_HI_WRITE): New enumerator. + (fn_hi_write): New union member. + (sim_queue_fn_hi_write): New function. + * cgen-par.c (sim_queue_fn_hi_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_FN_HI_WRITE. + +1999-09-29 Doug Evans + + * cgen-defs.h (sim_engine_invalid_insn): New arg `vpc'. + Change type of result to SEM_PC. + +Wed Sep 29 14:43:57 1999 Dave Brolley + + * cgen-defs.h (sim_engine_invalid_insn): Now returns PC. + +1999-09-25 Doug Evans + + * cgen-ops.h (SUBWORD*): Delete cpu arg. + (JOIN*): Delete cpu arg. + +Tue Sep 21 17:14:16 1999 Dave Brolley + + * genmloop.sh (@cpu@_scache_lookup): No longer takes last_insn_p + parameter. + (SET_LAST_INSN_P): Set last_insn_p flag in the scache element. + +Mon Sep 20 21:44:06 1999 Geoffrey Keating + + * sim-fpu.c (i2fpu): Keep the guard bits sticky when converting + large values. + +Tue Feb 8 16:33:48 2000 Andrew Cagney + + * run.c (main): Check the sim_stop_reason and only halt simulation + when a valid stop condition is identified. + +Wed Sep 15 14:12:37 1999 Andrew Cagney + + * hw-tree.c, hw-properties.c, hw-instances.c: Include "sim-io.h". + +Tue Sep 14 14:15:47 1999 Dave Brolley + + * cgen-par.h (CGEN_BI_WRITE): New enumerator. + (bi_write): New union element. + (sim_queue_bi_write): New function. + * cgen-par.c (sim_queue_bi_write): New function. + (cgen_write_queue_element_execute): Handle CGEN_BI_WRITE. + +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + + * aclocal.m4 (WERROR_CFLAGS, WARN_CFLAGS): Merge from + ../gdb/configure.in. + * Make-common.in (WERROR_CFLAGS, WARN_CFLAGS): Define. + (SIM_WERROR_CFLAGS, SIM_WARN_CFLAGS): Define. + (SIM_WARNINGS): Delete + (CONFIG_CFLAGS): Update. + +Tue Aug 31 16:01:42 1999 Dave Brolley + + * cgen-par.c: New file. + * cgen-par.h: New file. + * cgen-sim.h (cgen-par.h): #include it. + * cgen-cpu.h (write_queue): New field. + (CPU_WRITE_QUEUE): New access macro. + * Make-common.in (CGEN_MAIN_CPU_DEPS): Add cgen-par.h. + (cgen-par.o): New target. + +1999-08-28 Doug Evans + + * cgen-types.h (mode_type,MODE_VOID): Renamed from MODE_VM. + * cgen-utils.c (mode_names): Update. + +1999-08-20 Doug Evans + + * genmloop.sh: New args -parallel-generic-write, -parallel-only. + * cgen-engine.h (SEMANTIC_FN): Don't use version with PAREXEC + buffer arg if WITH_PARALLEL_GENWRITE. + (struct insn_sem): Handle WITH_PARALLEL_GENWRITE. + (struct idesc): Ditto. + +Wed Aug 18 18:17:28 1999 Doug Evans + + * sim-model.c (model_option_handler): Add \n to error message. + +1999-08-08 Doug Evans + + * cgen-engine.h (SEM_FN_NAME,SEMF_FN_NAME): Delete. + (insn_sem): Rewrite. + (sem_fn_desc): New struct. + (idesc): Rewrite. + * genmloop.sh (scache case,@cpu@_scache_lookup): Profile scache hit, + misses if ! FAST_P. + (scache case): Split into non-parallel/parallel versions. + (@cpu@_engine_run_{full,fast}): Call @cpu@_{sem,semf}_init_idesc_table + if not use semantic switch version. + +1999-08-04 Doug Evans + + * cgen-defs.h (SEM_BRANCH_TYPE): New enum. + * cgen-engine.h (SEM_BRANCH_UNTAKEN,SEM_BRANCH_UNCACHEABLE): Delete. + (SEM_BRANCH_INIT_EXTRACT): Delete. + (SEM_BRANCH_INIT): Replace npc_ptr with br_type. + (SEM_BRANCH_FINI): Ditto. + (SEM_BRANCH_VIA_ADDR): Ditto. + (SEM_BRANCH_VIA_CACHE): Ditto. Delete cachvarptr arg. + (SEM_BRANCH_ADDR_CACHE): Delete. + (SEM_SKIP_COMPILE,SEM_SKIP_INSN): New macros. + * cgen-scache.h (cpu_scache): Replace member pbb_pr_npc_ptr with + pbb_br_type. + * genmloop.sh (eng.hin): Update prototype of ${cpu}_pbb_cti_chain. + (@cpu@_pbb_begin): Initialize branch_target. + (@cpu@_pbb_cti_chain): Replace arg new_vpc_ptr with br_type. + (@cpu@_engine_run_full): Replace local pbb_br_npc_ptr with + pbb_br_type. + (@cpu@_engine_run_fast): Ditto. + +Fri Jul 16 14:47:53 1999 Dave Brolley + + * cgen-utils.c (RORSI): New function. + (ROLSI): New function. + +1999-07-14 Doug Evans + + * Makefile.in (TAGS): Tweak TAGS regex. + * cgen-mem.h (*): Add TAGS markers. + +Sun Jul 11 23:47:20 1999 Andrew Cagney + + * sim-resume.c (sim_resume): Ensure that the siggnal [sic] is only + passed in when sim_resume is first entered - don't re-pass it + after a restart. + +Sun Jul 11 23:34:44 1999 Andrew Cagney + + * sim-options.c (standard_option_handler): Add OPTION_LOAD_VMA and + OPTION_LOAD_LMA but only when is defined. + (standard_options): When SIM_HANDLES_LMA is defined include + options --load-lma and --load-vma. + (standard_install): Initialize STATE_LOAD_AT_LMA_P. + + * sim-base.h (STATE_LOAD_AT_LMA_P): Define. + (struct sim_state_base): Add load_at_lma_p. + * sim-hload.c (sim_load): Replace SIM_HANDLES_LMA with + STATE_LOAD_AT_LMA_P. + +Sun Jul 11 12:03:36 1999 Andrew Cagney + + * nrun.c (main): Re-format loop gnu style. + +Wed Jul 7 19:56:03 1999 Andrew Cagney + + * dv-sockser.c (connected_p): Initialize addrlen. + +1999-07-06 Dave Brolley + + * cgen-accfp.c (floatsidf): New function. + (fixdfsi): New function. + +1999-07-06 Doug Evans + + * sim-model.c (sim_model_init): Issue error if machine is unsupported. + +1999-07-05 Doug Evans + + * Make-common.in (CGEN_MAIN_CPU_DEPS): Add cgen-fpu.h. + (cgen-fpu.o,cgen-accfp.o): Add rules for. + * cgen-fpu.c: New file. + * cgen-fpu.h: New file. + * cgen-accfp.c: New file. + * cgen-cpu.h (CGEN_CPU): New member fpu. + * cgen-mem.h: Redo fp support. + * cgen-ops.h: Delete k&r support. Redo fp support. + * cgen-sim.h: Include cgen-fpu.h. + * cgen-types.h (SF,DF,XF,TF): Moved to cgen-fpu.h. + +1999-06-23 Doug Evans + + * cgen-engine.h (TARGET_SEM_BRANCH_FINI): Remove cruft at end of + ifndef. + * genmloop.sh (@cpu@_scache_lookup): Delete unused local var. + (@cpu@_pbb_cti_chain): Minor clean up. + +1999-05-08 Felix Lee + + * aclocal.m4: Use AC_EXEEXT instead of AM_EXEEXT. Delete defn of + AM_CYGWIN32 and AM_EXEEXT. + * configure: Regenerate. + +Fri Apr 16 16:43:22 1999 Doug Evans + + * sim-core.c (device_error,device_io_read_buffer, + device_io_write_buffer): Delete decls. + * sim-core.h: Put them here. + + * sim-core.c (sim_core_read_buffer): Pass sd to device_io_read_buffer. + (sim_core_write_buffer): Pass sd to device_io_write_buffer. + * sim-n-core.h (sim_core_read_aligned_N): Ditto. + (sim_core_write_aligned_N): Ditto. + +1999-04-14 Stephane Carrez + + * sim-memopt.c (sim_memory_uninstall): Don't look into + free()d memory. + +1999-04-14 Doug Evans + + * cgen-utils.scm (virtual_insn_entries): Update attribute definition. + +1999-04-13 Doug Evans + + * sim-core.c (sim_core_read_buffer): Handle NULL cpu when WITH_DEVICES. + (sim_core_write_buffer): Ditto. + +1999-04-02 Keith Seitz + + * sim-io.c (sim_io_poll_quit): Only call the poll_quit callback + after the interval counter has expired. + (POLL_QUIT_INTERVAL): Define. Used to tweak the frequency of + poll_quit callbacks. May be overridden by Makefile. + (poll_quit_counter): New global. + * sim-events.c: Remove all mentions of ui_loop_hook. The + host callback "poll_quit" will serve the purpose. + * run.c: Add definition of ui_loop_hook when NEED_UI_LOOP_HOOK + is defined. + * nrun.c: Remove declaration of ui_loop_hook. + +Wed Mar 31 18:55:41 1999 Doug Evans + + * cgen-run.c (sim_resume): Don't tell main loop to run "forever" + if being used by gdb. + +1999-03-22 Doug Evans + + * cgen-types.h (XF,TF): Tweak. + * cgen-ops.h: Redo inline support. Delete DI_FN_SUPPORT, + in cgen-types.h. + (SUBWORD*,JOIN*): Define. + * cgen-trace.c (sim_cgen_disassemble_insn): Update, base_insn_bitsize + moved into cpu descriptor. + * sim-model.h (MACH): New member `num'. + +1999-02-09 Doug Evans + + * cgen-cpu.h (CGEN_DISASSEMBLER): New type. + (CGEN_CPU): Member opcode renamed to cpu_desc. + New members get_idata,disassembler. + * cgen-defs.h (CGEN_INSN_VIRTUAL_P): CGEN_INSN_ATTR renamed to + CGEN_INSN_ATTR_VALUE. + (CGEN_STATE): Delete member opcode_table. + (sim_disassemble_insn): Delete decl. + * cgen-engine.h (struct insn_sem): Moved to here from -decode.c. + (struct idesc): Moved to here from -decode.h. + * cgen-run.c (prime_cpu): Call prepare_run callback. + * cgen-trace.h (SFILE): New type. + (sim_disasm_sprintf): Declare. + (sim_disasm_read_memory,sim_disasm_perror_memory): Declare. + (sim_cgen_disassemble_insn): Declare. + * cgen-trace.c: Include errno.h,dis-asm.h. Don't include cpu-opc.h. + (insn_fields): Delete. + (trace_insn_fini): STATE_OPCODE_TABLE (sd) replaced with + CPU_CPU_DESC (cpu). + (trace_insn): Call CPU_DISASSEMBLER hook. + (sim_disasm_sprintf): New function. + (sim_disasm_read_memory): New function. + (sim_disasm_perror_memory): New function. + (sim_cgen_disassemble_insn): New function. + * cgen-utils.c: Don't include cpu-opc.h. + (virtual_insn_entries): New static local. + (cgen_virtual_insn_table): Renamed from cgen_virtual_opcode_table. + (cgen_insn_name): Rewrite. + (disasm_sprintf,sim_disassemble_insn): Moved to cgen-trace.c. + * cgen.sh (desc): New file generator handler. + * genmloop.sh: -parallel changed to -parallel-read/-parallel-write. + Define WITH_PARALLEL_READ/WITH_PARALLEL_WRITE appropriately. + Don't include cpu-opc.h,cpu-sim.h. + * sim-model.c (model_set): Delete SIM_DESC arg. + (sim_model_set): Update. + * sim-model.h (MACH): New member prepare_run. + +1999-01-28 Frank Ch. Eigler + + * sim-memopt.c (memory_option_handler): Avoid memset() calls + if redundant with allocator functions. + +Wed Jan 27 17:19:09 1999 Doug Evans + + * cgen-engine.h (EXTRACT_LSB0_{INT,UINT}): Fix. + + * sim-profile.h: Make like sim-trace.h. + (PROFILE_USEFUL_MASK): New macro. + * sim-profile.c (profile_options): Make like trace_options, allow + optional on|off arg where applicable. + (set_profile_option_mask): New function. + (sim_profile_set_option): New function. + (profile_option_handler): Simplify. + Have -p only enable selected things, not everything. + Add missing break to OPTION_PROFILE_PC_RANGE. + * cgen-scache.c (scache_options): Allow optional on|off arg to + --profile-scache. + (scache_option_handler): Use sim_profile_set_option. + +1999-01-26 Frank Ch. Eigler + + * sim-memopt.c (memory_options): Add MEMORY_FILL option. + (memory_option_handler): Implement MEMORY_FILL option. Make + MEMORY_CLEAR an alias for MEMORY_FILL=0. + (parse_ulong_value): New function. + (do_memopt_add): Allocate all buffers. Optionally fill them. + +1999-01-15 Richard Henderson + + * hw-events.c (hw_event_queue_schedule): _vtracef takes a + va_list, not an integer. + * sim-events.c (sim_events_schedule): Likewise. + + * sim-types.h (UNSIGNED32, UNSIGNED64): Properly cast to + the appropriate type. + +1999-01-14 Doug Evans + + * cgen-defs.h (PCADDR,CIA): Define in terms of IADDR. + (sim_disassemble_insn): Update prototype. + (sim_engine_invalid_insn): Ditto. + * cgen-engine.h (SEMANTIC_FN): Add !WITH_SCACHE version. + (SEM_BRANCH_INIT): PCADDR->IADDR. + (SEM_NBRANCH_FINI): New macro for !WITH_SCACHE case. + * cgen-scache.c (scache_lookup,scache_lookup_or_alloc): PCADDR->IADDR. + * cgen-scache.h (*): Ditto. + * cgen-trace.c (*): Ditto. + * cgen-trace.h (*): Ditto. + * cgen-utils.c (*): Ditto. + * cgen-types.h (integer modes): Use signedNN/unsignedNN types. + (insn_t): Delete. + * genmloop.sh (@cpu@_fill_argbuf): Add !WITH_SCACHE support. + (simple engine framework): Rewrite. + * sim-module.c (modules): Install model module sooner (and in + particular before the profile module). + +1999-01-12 Doug Evans + + * sim-model.h (sim_mach_lookup_bfd_name): Add prototype. + * sim-model.c (sim_mach_lookup_bfd_name): New function. + (sim_model_init): Call it. + + * cgen-trace.c (trace_insn): Pass pc to trace_prefix for virtual insns. + +1999-01-05 Doug Evans + + * Make-common.in (CGEN_INCLUDE_DEPS): Add cgen-defs.h, cgen-engine.h. + * cgen-engine.h (SEM_BRANCH_FINI): New arg pcvar, all uses updated. + (SEM_BRANCH_INIT_EXTRACT): New macro. + (SEM_BRANCH_INIT): Add taken_p. + (TARGET_SEM_BRANCH_FINI): Provide default definition. + (SEM_BRANCH_FINI): Use it. + (SEM_INSN): Update. + * cgen-run.c (sim_resume): Handle tracing of last insn. + * cgen-scache.h (WITH_SCACHE): Define as 0 if not defined. + * cgen-trace.c (current_abuf): New static global. + (trace_insn_init): Initialize it. + (trace_insn_fini): Use it. + (trace_insn): Set it. + * cgen.sh (arch case): Pass -m ${mach} to cgen. + * genmloop.sh (@cpu@_emit_before): Only define if WITH_SCACHE_PBB. + (@cpu@_emit_after): Ditto. + (simple @cpu@_engine_run_full): New local `pc'. Initialize semantic + labels if WITH_SEM_SWITCH_FULL. + * sim-model.c: Include bfd.h. + (sim_model_init): New function. + (sim_model_install): Record init fn. + * sim-model.h (MACH): New member bfd_name. + * sim-module.c (modules): Initialize model before scache. + +1998-12-24 Frank Ch. Eigler + + * dv-sockser.c (DEFAULT_TIMEOUT): Increase to 1 ms. + + * nrun.c (main): Remain in simulation loop for traps and + exceptions when in operating environment mode. + (ui_loop_hook): New stub hook for standalone use. + * sim-events.c (sim_events_process): Call ui_loop_hook + periodically on CYGWIN host. + + * sim-reason.c (sim_stop_reason): Return host signal numbers + to gdb on sim_stopped and sim_signalled cases. + * sim-engine.c (sim_engine_halt): Call SIM_CPU_EXCEPTION_SUSPEND + hook just before longjmp. + * sim-resume.c (sim_resume): Call SIM_CPU_EXCEPTION_RESUME + hook just before sim_engine_run. + + * sim-n-core.h (sim_core_trace_M): Allay const warning. + * sim-trace.h (trace_generic): Ditto. + * sim-trace.c (trace_generic): Ditto. + +1998-12-14 Doug Evans + + * Make-common.in (SIM_MAIN_DEPS): New var. + (CGEN_MAIN_CPU_DEPS): New var. + * aclocal.m4: Add --enable-cgen-maint option. + * cgen-mem.h (GETMEM*): New arg `pc'. Pass to sim_core routine. + (SETMEM*): Ditto. + (GETIMEM*): Pass pc value to sim_core routine. + +Fri Dec 11 16:58:36 1998 Andrew Cagney + + * hw-handles.c (hw_handle_add_ihandle, hw_handle_add_phandle): + Compare with ZERO not NULL. + +Thu Dec 10 14:14:39 1998 Andrew Cagney + + * hw-properties.c, hw-instances.c, hw-tree.c: Include + "sim-assert.h". + +1998-12-09 Doug Evans + + * sim-arange.c: Include libiberty.h, and stdlib.h if present. + * sim-trace.c: Include stdlib.h if present. + * dv-sockser.c: Include unistd.h if present. + (dv_sockser_init): Add missing arg to call to sim_io_eprintf. + * cgen-scache.c (scache_flush): Delete unused locals i,sc. + +1998-12-08 James E Wilson + + * gennltvals.sh: Add i960. + * nltvals.def: Rebuild. + +1998-12-04 Doug Evans + + * cgen-defs.h: New file, old cgen-sim.h. + * cgen-sim.h: Simple header that includes others. + * sim-arange.c: New file. + * sim-arange.h: New file. + * sim-basics.h: Include it. + * Make-common.in (SIM_NEW_COMMON_OBJS): Add sim-arange.o. + (sim-arange.o): Add rule for. + * sim-cpu.h (sim_cpu_msg_prefix): Add prototype. + (sim_io_eprintf_cpu): Add prototype. + * sim-inline.h (HAVE_INLINE): Define if GNUC. + (INLINE2): New macro. + (EXTERN_INLINE): New macro. + * sim-module.c (sim_post_argv_init): Initialize cpu backlink + before calling module init fns. + * sim-profile.c (OPTION_PROFILE_*): Move into enum. + (profile_init): New function. + (profile_options): New option --profile-range. + (profile_option_handler): Handle --profile-range. + (profile_print_insn): Qualify address range specific section titles. + (profile_print_addr_ranges): New function. + (profile_info): Print address ranges if specified. + (profile_install): Set profile_init init fn. + * sim-profile.h (PROFILE_DATA): New member `range'. + * sim-trace.c (trace_init): New function. + (trace_options): New option --trace-range. + (trace_option_handler): Handle --trace-range. + (trace_install): Set trace_init init fn. + * sim-trace.h (TRACE_DATA): New member `range'. + * sim-utils.c (sim_cpu_msg_prefix): New function. + (sim_io_eprintf_cpu): New function. + * cgen-engine.h (PC_IN_TRACE_RANGE_P): New macro. + (PC_IN_PROFILE_RANGE_P): New macro. + * cgen-trace.c (trace_insn_init): Set current_insn to NULL. + (trace_insn_fini): New arg abuf. All callers updated. + Exit early if trace_insn not called. Check ARGBUF_PROFILE_P before + printing cycle counts. + * cgen-trace.h (trace_insn_fini): Update prototype. + (TRACE_RESULT_P): New macro. + (TRACE_INSN_INIT,TRACE_INSN_FINI): New arg abuf. All callers updated. + (TRACE_INSN): Check ARGBUF_TRACE_P. + (TRACE_EXTRACT,TRACE_RESULT): New arg abuf. All callers updated. + * cgen-types.h (SIM_INLINE): Delete. + (SIM_HAVE_MODEL,SIM_HAVE_ADDR_RANGE): Define. + * cgen-utils.c: Don't include cgen-engine.h + * genmloop.sh (@cpu@_fill_argbuf): New function. + (@cpu@_fill_argbuf_tp): New function. + (@cpu@_emit_before,@cpu@_emit_after): New functions. + (@cpu@_pbb_begin): Prefix cti_sc,insn_count with '_'. + (SET_CTI_VPC,SET_INSN_COUNT): Update. + (@cpu@_pbb_before): Check ARGBUF_PROFILE_P before calling + doing profiling. Update call to TRACE_INSN_INIT,TRACE_INSN_FINI. + (@cpu@_pbb_after): Check ARGBUF_PROFILE_P before calling + doing profiling. Update call to TRACE_INSN_FINI. + + * sim-memopt.c (sim_memory_uninstall): Result type is `void'. + +1998-12-03 Frank Ch. Eigler + + * sim-memopt.c (sim_memory_uninstall): Deallocate all memory + regions. + +1998-12-01 Doug Evans + + * sim-inline.c (SIM_INLINE_P): Fix typo. + +1998-11-30 Doug Evans + + * cgen-utils.c (cgen_virtual_opcode_table): Update. + +Tue Nov 24 18:40:03 1998 Andrew Cagney + + * gennltvals.sh: Add v850 and d10v. Sort alphabetically. + * nltvals.def: Re-generate. + +Mon Nov 23 13:28:38 1998 Andrew Cagney + + * sim-core.c (reverse_n, sim_core_uninstall, sim_core_init, + sim_core_map_attach, sim_core_map_detach, next_event_queue, + new_sim_core_mapping): Only define when EXTERN_SIM_CORE_P, pacify + GCC. + * sim-events.c (sim_events_uninstall, sim_events_suspend, + sim_events_resume, sim_events_zalloc, insert_sim_event): Ditto. + +1998-11-22 Doug Evans + + * genmloop.sh (${cpu}_pbb_chain): Watch for Ctrl-C's. + (${cpu}_pbb_cti_chain): Ditto. + +1998-11-18 Doug Evans + + * Make-common.in (cgen-utils.o): Depend on cgen-engine.h. + * cgen-engine.h (EXTRACT_[ML]SB0_{INT,UINT}): New macros. + (EXTRACT_INT,EXTRACT_UINT): New macros. + (SEM_SEM_ARG): New macro. + (SEM_NEXT_VPC): New arg `pc'. + * cgen-sim.h (EXTRACT_SIGNED,EXTRACT_UNSIGNED): Delete. + (sim_disassemble_insn): Update prototype. + * cgen-trace.c (current_insn,insn_fields): New static locals. + (trace_insn): Set them. + * cgen-utils.c: #include cgen-engine.h. + (sim_disassemble_insn): New arg insn_fields. + Handle variable length insns. + * genmloop.sh: Only emit pbb decls if -pbb. + (${cpu}_scache_lookup): New arg `vpc'. + (scache support): Fetch pc before entering loop. + + * gennltvals.sh: Add fr30 support. + * nltvals.def: Rebuild. + +Wed Nov 18 10:22:22 1998 Andrew Cagney + + * sim-types.h: Re-do type system so that GCC's attribute and mode + are used to specify types. Handle case of ALPHA. + +1998-11-13 Frank Ch. Eigler + + * aclocal.m4: Add tests for dlopen family. + * config.in: Regenerated. + +Wed Nov 11 14:02:25 1998 Doug Evans + + * sim-hload.c (sim_load): Pass `prog_name' to sim_load_file, not NULL. + +Wed Nov 4 23:51:19 1998 Doug Evans + + * genmloop.sh (eng.hin): Rename HAVE_PARALLEL_EXEC to + HAVE_PARALLEL_INSNS, define as 0 or 1. Emit decls of fns in mloop.cin. + * cgen-engine.h: Typedefs of IADDR,CIA,SEM_ARG,SEM_PC moved ... + * cgen-sim.h: ... to here. + +Wed Oct 28 12:00:57 1998 Andrew Cagney + + * aclocal.m4 (enable-build-warnings): Replace + enable-sim-warnings. Extend =LIST syntax so that prepend and + append of options is possible. Drop -Werror, add + -Wstrict-prototypes for GDB compatibility. + * Make-common.in (SIM_WARNINGS): Update. + +Mon Oct 19 13:56:32 1998 Doug Evans + + * Make-common.in (CGEN_INCLUDE_DEPS): Define. + (sim-core.o): Delete duplicate dependence on $(SIM_EXTRA_DEPS). + (sim-cpu.o,sim-endian.o,sim-hw.o): Ditto. + (cgen-run.o,cgen-scache.o,cgen-trace.o,cgen-utils.o): Delete + explicit cgen header dependencies, require SIM_EXTRA_DEPS to include + CGEN_INCLUDE_DEPS. + * cgen-cpu.h: New file. + * cgen-engine.h: New file. + * cgen-scache.h: New file. + * cgen-sim.h: Delete portions moved to new files. + * genmloop.sh: Generate two files eng.hin,mloop.cin explicitly, + rather than sending result to stdout. + +Fri Oct 9 14:20:22 1998 Doug Evans + + * Make-common.in (sim-reg.o): New rule. + (cgen-run.o): New rule. + * cgen-ops.h: Delete many BI macros. Change all UBI -> BI. + * cgen-run.c (prime_cpu): New function. + * cgen-scache.c: Add pseudo-basic-block (pbb) scaching support. + (scache_option_handler, case OPTION_PROFILE_SCACHE): Handle explicitly + mentioned cpu. + (scache_flush_cpu,scache_lookup,scache_lookup_or_alloc): New fns. + * cgen-sim.h (CGEN_INSN_VIRTUAL_TYPE): New enum. + (CGEN_INSN_VIRTUAL_P): New macro. + (SEM_PC): New typedef. + (SEMANTIC_FN): Change type of result to SEM_PC. + (SEM_SET_FULL_CODE,SEM_SET_FAST_CODE,SEM_SET_CODE): New macros. + (IDESC_CTI_P,IDESC_SKIP_P): New macros. + (SCACHE_MAP): New typedef. + (CPU_SCACHE): Add pbb support. + (scace_lookup,scache_lookup_or_alloc,scache_flush_cpu): Declare. + (SEM_BRANCH_INIT_EXTRACT,SEM_BRANCH_INIT,SEM_BRANCH_FINI): New macros. + (CGEN_CPU): New members running_p,insn_count,{fast,full}_engine_fn, + max_slice_insns. + (INSN_NAME): Delete. + (cgen_insn_name): Declare. + (sim_engine_invalid_insn): Renamed from sim_engine_illegal_insn. + * cgen-trace.c (trace_buf): Shrink from 1024 to 256 bytes. + (first_insn_p): Make static. + (trace_insn): Handle virtual insns specially. + (cgen_trace_printf): Ensure we haven't overflowed the buffer. + * cgen-types.h (UBI): Delete. + (MODE_TYPE): New enum. + (HOSTINT,HOSTUINT,HOSTPTR): Delete. + * cgen-utils.c (mode_names): Delete UBI. Add INT,UINT,PTR. + (cgen_virtual_opcode_table): New global. + (cgen_insn_name): New function. + (sim_disassemble_insn): Ignore virtual insns. + * genmloop.sh: Delete top level loop generation. Add pbb support. + * sim-cpu.h (CPU_INSN_NAME_FN): New typedef. + (sim_cpu_base): New members max_insns,insn_name,model_data. + (CPU_PC_GET,CPU_PC_SET): New macros. + (sim_pc_get,sim_pc_set): Declare. + * sim-model.c (model_set): Call model init fn. + * sim-model.h (MODEL_FN): New typedef. + (INSN_TIMING): New member model_fn. + (MODEL): New members num,init. + * sim-profile.c (sim_profile_print_bar): Renamed from print_bar. + All callers updated. + (profile_insn_init): New fn. + (profile_print_insn): Update, INSN_NAME -> CPU_INSN_NAME. + Exit early if insn profiling not supported. + (profile_print_memory): Update, MAX_MODES -> MODE_TARGET_MAX. + (profile_install): Record profile_insn_init as init fn. + (profile_uninstall): Free PROFILE_INSN_COUNT if non-null. + * sim-profile.h: Update, MAX_MODES -> MODE_TARGET_MAX. + (PROFILE_DATA): Delete member exec_time. + Change insn_count to pointer to array, rather than the array. + (sim_profile_print_bar): Declare. + +Wed Oct 7 16:56:42 1998 Doug Evans + + * cgen-run.c: New file. + * sim-reg.c: New file. + +Mon Sep 14 10:58:19 1998 Frank Ch. Eigler + + * aclocal.m4: Add checks for -lsocket and -lnsl. + + * dv-sockser.c (dv_sockser_init): Use SO_REUSEADDR to + allow local port reuse on listening socket. + +Tue Sep 1 15:36:52 1998 Frank Ch. Eigler + + * sim-config.h: Remove reference to linux kernel header. + +Tue Aug 25 12:45:27 1998 Frank Ch. Eigler + + * dv-sockser.c (sockser_addr): Make variable non-static. + +Mon Aug 24 11:47:37 1998 Joyce Janczyn + + * sim-hw.{c,h} (sim_hw_parse): Return struct hw pointer. + +Tue Aug 11 18:12:19 1998 Doug Evans + + * sim-events.c (sim_events_elapsed_time): Fix calculation. + +Tue Aug 4 20:36:46 1998 Jeff Holcomb + + * Make-common.in (install-common): Add $(EXEEXT) when installing + run. + +Mon Aug 3 11:46:01 1998 Doug Evans + + * cgen-sim.h (cgen_state): New member opcode_table. + * cgen-utils.c (sim_disassemble_insn): Use it. + +Fri Jul 24 10:14:18 1998 Doug Evans + + * cgen-mem.h (DECLARE_SETT): Fix return type. + * cgen-sim.h (sim_engine_illegal_insn): Declare. + * cgen-scache.c: Include stdlib.h. + * cgen-trace.c (trace_extract): Use %lx for PCADDR. + * sim-model.c (model_option_handler): Remove unused variable `n'. + +Tue Jul 21 16:27:43 1998 Doug Evans + + * cgen-utils.c: Include bfd.h. + (sim_disassemble_insn): Update call to CGEN_EXTRACT_FN. + +Wed Jul 8 18:24:10 1998 Jeffrey A Law (law@cygnus.com) + + * sim-bits.h (EXTEND24): Fix typo. + +Wed Jul 8 17:41:47 1998 Andrew Cagney + + * sim-events.c (ETRACE_P): New macro. + (struct _sim_event): Add member trace. + (sim_events_free): Reclaim trace message. + + * sim-events.c, sim-events.h (sim_events_schedule_vtracef, + sim_events_schedule_tracef): New functions, include printf trace + information in argument list. If tracing, store asprintf'd trace + message in sim_event. + + * hw-events.c, hw-events.h (hw_event_queue_schedule_tracef, + hw_event_queue_schedule_vtracef): New functions, mimic + sim_event_tracef. + +Mon Jul 6 15:51:14 1998 Jeffrey A Law (law@cygnus.com) + + * sim-bits.h (EXTEND24): Define. + +Thu Jul 2 17:13:25 1998 Doug Evans + + * cgen-sim.h (CPU_SCACHE): Make size unsigned. + (CPU_SCACHE_HASH_MASK): New macro. + (SCACHE_HASH_PC): Rewrite. + * genmloop.sh (engine_resume_{full,fast}): Move some of hash + computation out of main loop. + +Wed Jul 1 16:44:12 1998 Doug Evans + + * cgen-sim.h (RECORD_IADDR): Delete. + * cgen-types.h (HOSTINT,HOSTUINT,HOSTPTR): New types. + * genmloop.sh (engine_resume_{full,fast}): Delete icount. + +Wed Jun 17 12:25:08 1998 Mark Alexander + + * gennltvals.def (mn10200): Add entry. + * nltvals.def: Regenerate with MN10200 additions. + +Wed Jun 17 13:18:28 1998 Andrew Cagney + + * sim-inline.h (EXTERN_*): Replace with EXTERN_*_P. Correct + documentation on how it works. + + * sim-core.h, sim-core.c (sim_core_install, sim_core_attach, + sim_core_detach, sim_core_read_buffer, sim_core_write_buffer, + sim_core_set_xor, sim_core_xor_read_buffer, + sim_core_xor_write_buffer): Update. + + * sim-events.h, sim-events.c (sim_events_install, + sim_events_watch_clock, sim_events_schedule_after_signal, + sim_events_schedule, sim_events_watch_sim, sim_events_watch_core, + sim_events_deschedule): Update. + + * sim-fpu.h, sim-fpu.c (sim_fpu_zero, sim_fpu_one, sim_fpu_two, + sim_fpu_max32, sim_fpu_max64): Update. + +Sat Jun 13 07:45:38 1998 Doug Evans + + * cgen-trace.c (trace_insn_fini): Redo cycle handling. + * sim-profile.h (PROFILE_DATA): Rename cycle handling members. + * sim-profile.c (profile_print_model): Update. + +Fri Jun 12 18:35:07 1998 Doug Evans + + * gennltvals.def (m32r): Use common syscall.h now. + (mn10300): Add entry. + * nltvals.def: Regenerate. + + * sim-engine.c (sim_engine_get_run_state): New function. + * sim-engine.h (sim_engine_get_run_state): Declare it. + +Thu Jun 11 00:50:03 1998 Doug Evans + + * sim-core.h (SIM_CORE_SIGNAL_FN): New typedef. + * sim-core.c (sim_core_signal): Make extern, always define. + +Wed Jun 10 16:02:29 1998 Doug Evans + + * Make-common.in (CGEN_FLAGS_TO_PASS): New variable. + * cgen-ops.h (ANDIF): New macro. + (ANDIF[BQHSD]I): Delete. + +Thu Jun 4 13:53:54 1998 Andrew Cagney + + * hw-events.c (create_hw_event, delete_hw_event): Delete. + (hw_event_queue_schedule, hw_event_queue_deschedule, + bounce_hw_event): Fix hw-event memory corruptions found by Joyce + Janczyn. + + * hw-alloc.h (HW_NZALLOC): Define. + + * Make-common.in (test-hw-events): Add target for testing the + hw-event code. + +Mon May 25 21:11:26 1998 Andrew Cagney + + * Make-common.in (SIM_COMMON_HW_OBJS): Add hw-handles.o and + hw-instances.o. + hw-handles.c, hw-instances.c, hw-handles.h, hw-instances.h: New + files. + * hw-main.h: Include hw-handles.h, hw-instances.h. + * hw-base.h ({create,delete}_hw_{handles,instances}_data): Declare + * hw-base.c (hw_create, hw_delete): Call same. + +Mon May 25 18:55:35 1998 Andrew Cagney + + * dv-core.c: Include hw-main.h and sim-main.h. + * dv-pal.c: Include hw-main.h and sim-io.h. + * dv-glue.c: Include hw-main.h. + + * hw-main.h: New file. Move list of includes to here. + * hw-base.h: From here. + * Make-common.in (hw_base_headers): Rename to hw_main_headers. + (hw-*.o, dv-*.o): Update. + * hw-tree.c, hw-base.c, hw-properties.c, hw-ports.c, hw-device.c, + hw-events.c, hw-alloc.c, sim-hw.c: Include hw-main.h instead of + sim-main.h. + + * hw-base.h (do_hw_attach_regs, do_hw_poll_read_method, + do_hw_poll_read): Move declarations from here. + * hw-main.h: To here. + + * hw-base.h (struct hw_device_descriptor, hw_finish_callback): + Move from here. + * hw-main.h (struct hw_descriptor, hw_finish_method): To here, + rename. + * Make-common.in (hw-config.h): Update + * hw-base.c, dv-pal.c, dv-glue.c: Update + + * dv-glue.c, hw-device.h, hw-base.h, hw-ports.c: Rename + `*_callback' to `*_method. + +Mon May 25 18:41:18 1998 Andrew Cagney + + * hw-base.h (set_*): Move set method macros from here. + * hw-device.h: To here. + +Mon May 25 18:21:38 1998 Andrew Cagney + + * hw-base.h (create_hw_property_data, delete_hw_property_data): + Declare. + + * hw-base.c (hw_create, hw_delete): Call + * hw-properties.c (create_hw_property_data, + delete_hw_property_data): Define. + +Mon May 25 17:40:46 1998 Andrew Cagney + + * hw-device.c, hw-properties.c: Include hw-base.h + + * hw-alloc.h, hw-alloc.c: New files. Move alloc code to here. + * hw-device.c: From here. + * hw-base.h: Include "hw-events.h". + + * hw-base.h (create_hw_alloc_data, delete_hw_alloc_data): Declare. + * hw-base.c (hw_create, hw_delete): Call. + * hw-alloc.c (create_hw_alloc_data, delete_hw_alloc_data): Define. + + * Make-common.in (SIM_NEW_COMMON_OBJS): Add hw-alloc.o. + (hw-alloc.o): New target. + +Mon May 25 17:14:27 1998 Andrew Cagney + + * hw-events.h, hw-events.c: New files. Move event code to here. + * sim-hw.c: From here. + * hw-base.h: Include "hw-events.h". + * Make-common.in (SIM_NEW_COMMON_OBJS): Add hw-events.o. + (hw-events.o): New target. + + * hw-device.h (struct hw): Add struct hw_event_data events_of_hw. + * hw-events.h (struct hw_event): Replace typedef hw_event. + + * hw-base.h (create_hw_event_data, delete_hw_event_data): Declare. + * hw-base.c (hw_create, hw_delete): Call. + * hw-events.c (create_hw_event_data, delete_hw_event_data): Define. + + * dv-pal.c: Update. + +Mon May 25 16:55:16 1998 Andrew Cagney + + * hw-base.c (panic_hw_port_event, empty_hw_ports): Move from here. + * hw-ports.c: To here. + + * hw-base.h, hw-ports.c (create_hw_port_data, + delete_hw_port_data): New functions. + * hw-base.c (hw_delete, hw_create): Call same. + + * hw-base.h (set_hw_ports, set_hw_port_event): Move set functions + from here. + * hw-ports.h: To here. + +Mon May 25 16:42:48 1998 Andrew Cagney + + * hw-device.c (hw_ioctl), hw-device.h (hw_ioctl_callback): Drop + PROCESSOR and CIA arguments. + +Fri May 22 12:16:27 1998 Andrew Cagney + + * aclocal.m4 (SIM_AC_OPTION_HW): Add enable / disable argument. + Move common object files from here. + * Make-common.in (SIM_COMMON_HW_OBJS): To here. + +Thu May 21 17:57:16 1998 Andrew Cagney + + * sim-hw.c: Include ctype.h. + (do_hw_poll_read): Do not assume EAGAIN. + +Wed May 20 04:37:57 1998 Doug Evans + + * cgen-trace.c (first_insn_p): New static local. + (trace_insn_init): Set it. + (trace_insn_fini): Use TRACE_PREFIX. + (trace_insn): Rewrite to use trace_prefix. + * sim-trace.c (trace_prefix): Don't print filename arg if NULL. + Adjust width accordingly. + + * sim-profile.h (PROFILE_DATA): New member profile_any_p. + (PROFILE_ANY_P,PROFILE_INSN_P,PROFILE_MEMORY): New macros. + (PROFILE_SCACHE_P,PROFILE_PC_P,PROFILE_CORE_P): New macros. + (PROFILE_COUNT_INSN,PROFILE_COUNT_READ,PROFILE_COUNT_WRITE): Simplify. + (PROFILE_COUNT_CORE): Simplify. + * sim-profile.c (profile_option_handler): Compute profile_any_p. + +Tue May 19 23:55:30 1998 Doug Evans + + * cgen-ops.h (ADDCFSI): Fix typo. + +Sat May 16 12:44:52 1998 Doug Evans + + * cgen-sim.h (CGEN_CPU): New members idesc_{read,sem}_init_p. + * genmloop.sh: Use them rather than static locals. + + * sim-engine.c (sim_engine_set_run_state): New function. + * sim-engine.h (sim_engine_set_run_state): Declare. + * genmloop.sh (pending_reason,pending_sigrc): New static locals. + (@cpu@_engine_stop): New args reason,sigrc. All callers updated. + (engine_resume): Reorganize. Allow synchronous exit from main loop. + +Fri May 15 16:06:05 1998 Doug Evans + + * cgen-trace.c (trace_insn_init): New arg first_p. + All callers updated. + (trace_insn_fini): New arg last_p. All callers updated. + * cgen-trace.h (trace_insn_init,trace_insn_fini): Update. + (TRACE_INSN_INIT,TRACE_INSN_FINI): Update. + * genmloop.sh (engine_resume): Update. + +Fri May 15 15:59:00 1998 Joyce Janczyn + + * Make-common.in (install-common): Run ranlib on installed copy of + libsim.a. + +Fri May 15 15:03:00 1998 Joyce Janczyn + + * Make-common.in (install-common): Rename and install libsim.a. + +Tue May 12 15:23:57 1998 Andrew Cagney + + * sim-io.c (unistd.h): Include. + +Wed May 6 16:04:18 1998 Doug Evans + + * Make-common (sim_main_headers): Sort. + (cgen-*.o): Add cgen-sim.h dependency. + + * cgen-scache.c (scache_init): Only allocate space if scache element + size is non-zero. + (scache_flush,scache_print_profile): Check if scache in use first. + + * cgen-sim.h (IDESC): Provide forward declaration. + (DECODE): Delete. + (CGEN_CPU): Always define scache member. New members idesc,opcode. + (cgen_cpu_max_extra_bytes): Declare. + * cgen-utils.c (cgen_cpu_max_extra_bytes): New function. + + * sim-cpu.h: New file. sim_cpu_base moved here. + Move sim_cpu_lookup decl here. + * sim-base.h: #include "sim-cpu.h". + * sim-cpu.c: New file. + * Make-common (sim_main_headers): Add sim-cpu.h. + (sim-cpu.o): Add rule for. + + * sim-model.c (set_model): Delete. + (sim_model_set,model_set): New functions. + (sim_model_install): Renamed from model_install. + Don't set default model here. + (model_option_handler): Rewrite --model processing. + (sim_model_lookup,sim_mach_lookup): New functions. + * sim-model.h (MAX_MODELS,MAX_INSNS): Delete. + (insn_timing): Delete. + (INSN_TIMING): New member `num'. + (IMP_PROPERTIES): Always define scache_elm_size member. + (MACH): New member init_cpu. + (sim_machs): Renamed from machs. + (sim_model_install): Renamed from model_install. + (sim_model_set,sim_model_lookup,sim_mach_lookup): Declare. + * sim-module.c (modules): Update. + + * sim-profile.c (profile_print_insn): Add cpu arg to INSN_NAME macro. + + * sim-io.c: #include . + +Wed May 6 12:39:15 1998 Andrew Cagney + + * dv-pal.c (struct hw_pal_device): Add reader. + (hw_pal_finish): Initialize reader. + (scan_hw_pal): Use reader. + + * hw-base.h, sim-hw.c (do_hw_poll_read): New function. + (HW_IO_EOF, HW_IO_NOT_READY): Define. + * dv-pal.c: Use. + + * sim-io.h, sim-io.c (sim_io_poll_read): New function. Copy from + ../ppc/main.c sim_io_read_stdin. + +Fri May 1 12:11:02 1998 Andrew Cagney + + * hw-tree.h (hw_tree_print): Paramaterize with print and file + arguments. + * hw-tree.c: Update. + + * hw-base.h (hw_port_event_callback): Delete CPU/CIA args. + * hw-device.h (hw_io_read_buffer, hw_io_write_buffer): Delete + CPU/CIA args. + * hw-ports.h (hw_port_event): Ditto. + * hw-ports.c (hw_port_event): Update. + * hw-base.c (panic_hw_io_read_buffer, panic_hw_io_write_buffer): + Update. + * dv-pal.c (hw_pal_io_read_buffer, hw_pal_io_write_buffer): + Update. + (hw_pal_io_write_buffer): Call hw_halt not sim_engine_halt. + (do_counter_event): Update. + * dv-glue.c (hw_glue_io_read_buffer): Update. + (hw_glue_port_event): Update. + + * hw-device.h (SIM_DESC): Replace with struct sim_state. + * hw-base.h (hw_create): Ditto. + * hw-base.c (hw_create): Ditto. + + * hw-device.c (hw_abort, hw_trace, hw_hw_event_queue_schedule, + hw_event_queue_deschedule, hw_event_queue_time): Delete, moved + from here to. + * sim-hw.c: Here. + * hw-device.h (hw_system_cpu): Declare. + * sim-hw.c (hw_system_cpu): New function. + + * sim-core.c (sim_core_map_attach, sim_core_attach): Call + sim_hw_abort not hw_abort. + (sim-hw.h): Include. + (sim_core_read_buffer, sim_core_write_buffer): Call + sim_hw_io_read_buffer and sim_hw_io_write_buffer. Do not pass CPU + argument. + (sim_core_set_xor): Do not pass CPU when aborting. + + * sim-n-core.h (sim_core_read_aligned_N, + sim_core_write_aligned_N): Call sim_hw_abort not hw_abort. + (sim_core_read_aligned_N, sim_core_write_aligned_N): Call + sim_cpu_hw_io_read_buffer and sim_cpu_hw_io_write_buffer. Does not + return length. + + * sim-hw.h: Declare sim_hw_io_{read,write}_buffer. Declare + sim_hw_print. + * sim-hw.c (sim_hw_io_read_buffer, sim_hw_io_write_buffer, + sim_cpu_hw_io_read_buffer, sim_cpu_hw_io_write_buffer): New + functions. + (sim_hw_print): New function. + + * sim-engine.h (sim_engine_vabort): Declare. + * sim-engine.c (sim_engine_vabort): New function. + +Wed Apr 29 23:58:52 1998 Andrew Cagney + + * sim-trace.c (print_data): For floating-point numbers trace raw + hex value. + (trace_result_fp2): New function. + * sim-trace.h (trace_result_fp2): New declaration. + (TRACE_FP_RESULT2): New macro. + +Tue Apr 28 18:28:58 1998 Geoffrey Noer + + * common/aclocal.m4: call AM_EXEEXT in SIM_AC_COMMON, define + AM_CYGWIN32 and AM_EXEEXT. + * common/Make-common.in: set EXEEXT, add missing EXEEXTs + to run and install-common rules. + * common/configure: regenerate + +Sat Apr 25 17:45:01 1998 Andrew Cagney + + * sim-types.h (cell_word): New type. + (natural_cell): Delete type. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:25:07 1998 Tom Tromey + + * acconfig.h (NEED_DECLARATION_PRINTF): Removed. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:38:08 1998 Tom Tromey + + * acconfig.h: New file. + * Make-common.in (top_builddir): New macro. + (INTL_LIB): Removed. + (INTLLIBS): New macro. + (INTLDEPS): Likewise. + (LIBDEPS): Use INTLDEPS. + (EXTRA_LIBS): Use INTLLIBS. + * aclocal.m4 (SIM_AC_COMMON): Call CY_GNU_GETTEXT. + (CY_WITH_NLS, CY_GNU_GETTEXT, AM_PATH_PROG_WITH_TEST, + AM_LC_MESSAGES): New macros from GNU gettext. + +Fri Apr 24 19:57:59 1998 Andrew Cagney + + * sim-config.h: Discard leading _ from macros. + * sim-types.h: Ditto. + +Wed Apr 22 14:14:19 1998 Michael Meissner + + * Make-common.in (CSEARCH): Add -I to intl directories. + (INTL_LIB): Point to libintl.a. + (LIBDEPS): Add $(INTL_LIB). + (EXTRA_LIBS): Ditto. + +Tue Apr 21 12:44:27 1998 Doug Evans + + * cgen-types.h (GETHIDI,MAKEDI): Tweak. + + * cgen-ops.h (ADDCFSI): Fix. + (SUBCFSI): Tweak. + +Tue Apr 21 13:18:41 1998 Andrew Cagney + + * sim-types.h (signed_address, unsigned_address): Define. + +Mon Apr 20 21:47:54 1998 Andrew Cagney + + * sim-fpu.c (sim_fpu_2d): Don't return an SNaN, convert it into a + QNaN. + +Thu Apr 16 10:30:14 1998 Andrew Cagney + + * sim-fpu.c, sim-fpu.h (sim_fpu_fractionto, sim_fpu_tofraction): + New functions, pack / unpack sim_fpu struct using raw values. + (sim_fpu_is): Differentiate between negative and positive + infinity. + +Tue Apr 14 18:49:31 1998 Andrew Cagney + + * sim-bits.h (EXTEND4): Define. + (EXTEND4, EXTEND15, EXTEND11): Ditto. + +Tue Apr 14 16:31:35 1998 John Metzler + + * sim-memopt.c (parse_addr): Sunos 4.5 does not have strtol + declared so we need this cast to prevent long long addresses + from being misconfigures. Results in access to unmapped memory. + +Tue Apr 14 13:19:14 1998 Doug Evans + + * Make-common.in (RUNTESTFLAGS): Define. + (check): Pass RUNTESTFLAGS to recursive make. + +Tue Apr 14 15:09:19 1998 Andrew Cagney + + * sim-info.c (sim_info): Be verbose when either VERBOSE or + STATE_VERBOSE_P. + +Sat Apr 4 23:24:17 1998 Andrew Cagney + + * aclocal.m4 (sim-inline): By default, disable sim-inline when + cross compiling. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * aclocal.m4 (sim-cflags): Add -fomit-frame-pointer to defaults. + (sim-inline): Update to match sim-inline.[hc] + * configure: Regenerated to track ../common/aclocal.m4 changes. + + * Make-common.in (sim_main_headers): Add sim-inline.h + + * sim-bits.h (sim-bits.c): Include when H_REVEALS_MODULE_P. + selected. + * sim-endian.h (sim-endian.c): Ditto. + + * sim-events.h (_SIM_EVENTS_H_): Replace with SIM_EVENTS_H. + (sim_events_set_trace): Delete unused prototype. + + * sim-core.h (_SIM_CORE_H_): Replace with SIM_CORE_H. + * sim-core.c (_SIM_CORE_C_): Ditto for SIM_CORE_C. + + * sim-fpu.h (sim-fpu.c): Include when H_REVEALS_MODULE_P. + (sim_fpu_to232i, sim_fpu_to232u, sim_fpu_i232to, sim_fpu_u232to): + Comment out, not yet implemented in sim-fpu.c. + (sim_fpu_zero, sim_fpu_one, sim_fpu_two, sim_fpu_qnan, + sim_fpu_max32, sim_fpu_max64): Mark as EXTERN_SIM_FPU. + + * sim-inline.h: Rewrite description. + (H_REVEALS_MODULE_P, C_REVEALS_MODULE_P): Define. + (SIM_MAIN_INLINE): Add inline option. + + * sim-inline.c (semantics.c, idecode.c, engine.c, ...): Do not + include generated files. Handled by generator directly. + +Sat Apr 4 01:07:06 1998 Andrew Cagney + + * sim-trace.c (set_trace_option_mask): Keep TRACE_ANY_P + up-to-date. + + * sim-trace.h (TRACE_ANY_P): Define. + (struct _trace_data): Add trace_any_p. + +Mon Mar 30 17:11:55 1998 Andrew Cagney + + * run.c (main): Handle all alternatives of enum sim_stop. + (main): Delete unused `asection *s'. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * hw-tree.h, hw-tree.c (hw_tree_vparse): New function + + * configure: Regenerated to track ../common/aclocal.m4 changes. + + * sim-hw.c: New file. + * sim-hw.h (sim_hw_parse): Declare function. + (hw-tree.h): Do not include. + + * sim-base.h (STATE_HW): Define. + (struct sim_state_base): Add member struct *hw. + + * sim-module.c (sim-hw.h): Include. + (modules): Add sim_hw_install. + + * aclocal.m4 (sim_hw_obj): Add sim-hw.o + +Fri Mar 27 14:55:06 1998 Andrew Cagney + + * sim-base.h (CPU_INDEX): Define. + + * sim-utils.c (sim_state_alloc): Initialize. + * sim-module.c (sim_post_argv_init): Ditto. + +Thu Mar 26 10:07:57 1998 Stu Grossman + + * aclocal.m4 (sim_hw_obj): Fix sed expression to generate + properly formatted lists. + +Thu Mar 26 10:37:22 1998 Andrew Cagney + + * dv-pal.c (enum hw_pal_address_mask): From Stu Grossman, was + 0x2f needs to be 0x3f. + +Thu Mar 26 09:10:56 1998 Andrew Cagney + + * hw-tree.c (hw_tree_find_property): Return NULL when device is + not found. + (hw_tree_find_*_property): Clean up error message when property is + not found. + + * dv-pal.c (hw_pal_io_read_buffer): Check the smp property is + present before looking for it. + +Wed Mar 25 16:17:38 1998 Ian Carmichael + + * aclocal.m4 (AC_CHECK_HEADERS): Add check for fpu_control.h. + (AC_CHECK_FUNCS): Add check for __setfpucw. + * configure: Regenerated. + +Wed Mar 25 09:18:34 1998 Andrew Cagney + + * dv-pal.c (hw_pal_countdown, hw_pal_countdown_value, + hw_pal_timer, hw_pal_timer_value): Define. + (hw_pal_io_read_buffer, hw_pal_io_write_buffer): Add timer support + (do_counter_event, do_counter_read, do_counter_value, + do_counter_write): new functions. + +Tue Mar 24 12:24:24 1998 Andrew Cagney + + * hw-tree.c (hw_printf): Send tree dump to stderr, same as other + trace output. + + * hw-base.c (hw_create): Stop searching for a device when one is + found. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 23 10:25:08 1998 Andrew Cagney + + * aclocal.m4 (SIM_AC_OPTION_HARDWARE): Add second argument, + appends extra devices. + (SIM_AC_OPTION_HARDWARE): Substute sim_hw, a non-duplicate list of + the device names. + + * Make-common.in (hw-config.h): New target, create hw-config.h + file. + (SIM_HW): Definition from @sim_hw@. + (hw-base.o): Depend on hw-config.h + +Tue Mar 24 17:41:35 1998 Stu Grossman + + * Make-common.in: Get SHELL from configure. + * (stamp-tvals sim-inline.c): Use $(SHELL) when invoking + move-if-change. Fixes NT native build problem. + * Makefile.in (nltvals.def): Use $(SHELL) when invoking + move-if-change. Fixes NT native build problem. + * configure: Regenerate with autoconf 2.12.1 to fix shell issues for + NT native builds. + +Sun Mar 22 16:54:40 1998 Andrew Cagney + + * hw-device.h, hw-device.c (hw_strdup): New function. + + * hw-base.c (hw_create): Use hw_strdup when saving a copy of the + strings name, family and args. + (full_name_of_hw): Use hw_strdup when returning the full path. + + * hw-properties.c: Clean up property not found / wrong type error + messages. + + * hw-tree.c (hw_tree_parse): Finish a devices initialization + before attaching any ports. + + * hw-base.c (hw-config.): Include. Replace hardwired table. + + * dv-glue.c: Copy over ../ppc/hw_glue.c. Update to new framework. + + * Make-common.in: Add rule for dv-glue.o. + +Sun Mar 22 16:45:54 1998 Andrew Cagney + + * hw-base.c (hw_finish): Move setting of trace level to here. + (hw_create): From here. + + * hw-base.h, hw-base.c (do_hw_attach_regs): Copy function from + ../ppc/device_table.c. + + * dv-pal.c (hw_pal_finish): Attach PAL device to parent bus. + + * hw-tree.c (print_properties): Supress path when printing + properties of root node. + +Sun Mar 22 16:21:15 1998 Andrew Cagney + + * hw-device.h (HW_TRACE): Define. + (hw_trace): Declare. + * hw-device.c (hw_trace): Implement function. + + * hw-base.c (hw_create): Set hw trace level from "trace?" + property. + + * dv-core.c (dv_core_attach_address_callback): Add trace. + + * dv-pal.c: Replace DTRACE with HW_TRACE. + +Sun Mar 22 15:23:35 1998 Andrew Cagney + + * hw-device.h (HW_ZALLOC, HW_MALLOC): New macros. + (hw_alloc_data): Delcare. + (struct hw): Add member alloc_of_hw. + + * hw-device.c (hw_zalloc, hw_malloc, hw_free, hw_free_all): New + functions. Assocate memory with a device. + (stdlib.h): Include. + + * hw-base.h (set_hw_delete): Define. + (hw_delete_callback): Declare. + (hw_delete): Declare. + + * hw-base.c (hw_delete): Implement function. + (struct hw_base_data): Add member to_delete. + (ignore_hw_delete): New function, does nothing. + (hw_create): Set the hw_delete method. + (hw_create): Allocate the base type using HW_ZALLOC before setting + any methods. + + * hw-tree.h, hw-tree.c (hw_tree_delete): New function. + + * hw-properties.c: Replace zalloc/zfree with hw_zalloc/hw_free. + + * hw-ports.c: Replace zalloc/zfree with hw_zalloc/hw_free. + (attach_hw_port_edge): Add struct hw argument + + * dv-pal.c (hw_pal_finish): Replace zalloc/zfree with + hw_zalloc/hw_free. + +Sun Mar 22 15:09:52 1998 Andrew Cagney + + * hw-device.h (hw_attach_address_callback, + hw_detach_address_callback): Attach to a single space not a space + mask. Clarify interpretation of SPACE:ADDR parameters. + + * hw-base.c (passthrough_hw_attach_address, + passthrough_hw_detach_address): Update. + * dv-core.c (dv_core_attach_address_callback): Ditto. + * dv-pal.c (hw_pal_attach_address): Ditto. + +Thu Mar 19 00:41:00 1998 Andrew Cagney + + * sim-options.h: Document additional CPU arg to OPTION_HANDLER. + +Wed Mar 18 14:13:02 1998 Andrew Cagney + + * Make-common.in (SIM_HW_OBJS, SIM_HW_SRC, SIM_DV_OBJS): Define. + (hw-base_h, hw-device_h, hw-handles_h, hw-instances_h, hw_ports_h, + hw-properties_h, hw-tree_h): Define, point at corresponding + header. + (hw_base_headers): Define list of headers included by hw-base.h + (hw-base.o, hw-device.o, hw-instances.o, hw-handles.o, hw-ports.o, + hw-properties.o, hw-tree.o): Specify dependencies. + (dv-core.o, dv-pal.o): Ditto. + + * sim-hw.h: New file. + + * hw-device.h, hw-device.c, hw-properties.h, hw-properties.c, + hw-ports.h, hw-ports.c: New files. Copied from ../ppc/device.[ch]. + + * hw-tree.h, hw-tree.c: New files. Copied from ../ppc/tree.[hc]. + + * hw-base.h, hw-base.c: new files. Copied from + ../ppc/device_table.[hc]. + + * dv-core.c, dv-pal.c: New files. Copied from + ../ppc/hw_{core,pal}.c + + * sim-basics.h (struct hw): Declare. + (enum port_direction, enum object_disposition): Declare. + +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * aclocal.m4 (SIM_AC_OPTION_HARDWARE): Set sim_hw_obj, sim_dv_obj, + sim_dv_src in Makefile. Take list of devices as parameter to m4 + macro.. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 16 12:37:33 1998 Andrew Cagney + + * sim-trace.h, sim-trace.c (trace_prefix): Pass in sim_cia so that + trace_prefix can abort cleanly. + +Sat Mar 14 18:36:12 1998 Doug Evans + + * dv-sockser.c, dv-sockser.h: New files. + * Make-common.in (dv-sockser.o): Add rule for. + * aclocal.m4: Check for fcntl.h. + * config.h: Add HAVE_FCNTL_H. + + * sim-break.c (remove_breakpoint): Fix thinko. + + * sim-hload.c (sim_load): Provide default value of SIM_HANDLES_LMA. + Use SIM_HANDLES_LMA for lma_p arg to sim_load_file. + +1998-03-13 Fred Fish + + * sim-base.h (struct sim_state_base): Add prog_syms and + define macro STATE_PROG_SYMS. + * sim-trace.c (trace_prefix): Add variables abfd, symsize, + symbol_count, and asymbols. Call bfd_get_symtab_upper_bound + and bfd_canonicalize_symtab, to get symbol table on first use + and preserve it via STATE_PROG_SYMS for future calls to + bfd_find_nearest_line. + +Wed Mar 11 14:02:47 1998 Andrew Cagney + + * sim-core.h, sim-core.c (sim_core_map_to_str): Delete. + + * sim-core.c (sim_core_attach): Handle a generic number of maps - + up to nr_maps, not just access_* maps. + + * sim-profile.h (struct PROFILE_DATA): Track nr_maps different + maps. + + * sim-profile.c (profile_print_core): Make map unsigned. Iterate + over nr_maps not sim_core_nr_maps. + + * sim-events.h, sim-events.c (sim_events_watch_core): Change + core_map argument to unsigned. + (struct _sim_core): Ditto for struct member core_map. + + * sim-core.h (nr_sim_core_maps, sim_core_*_map): Delete + + * sim-basics.h (access_io, access_*_io): Define. + (map_read, map_write, map_exec, map_io): Define. + + * sim-core.c, sim-core.h (sim_core_attach): Replace argument + attach with more generic mapmask. + (sim_core_{read,write}_*): Change map argument to unsigned. + + * sim-core.c (sim_core_uninstall, sim_core_attach, + sim_core_detach): Iterate over nr_maps instead of + sim_core_nr_maps. + + * sim-break.c (insert_breakpoint): Write breakpoints to exec_map + instead of the write_map. + (remove_breakpoint): Ditto. + + * genmloop.sh (engine_resume_full): Replace sim_core_*_map + with read_map, write_map, exec_map resp. + + * cgen-mem.h (DECLARE_GETMEM, DECLARE_SETMEM, DECLARE_GETIMEM): + Ditto. + + * cgen-utils.c (sim_disassemble_insn): Ditto. + + * sim-hrw.c (sim_write, sim_write): Ditto. + + * sim-utils.h, sim-utils.c (access_to_str, map_to_str, + transfer_to_str): New functions. + +Mon Mar 9 12:50:59 1998 Doug Evans + + * sim-base.h (sim_state_base): New member environment. + (STATE_ENVIRONMENT): New macro. + * sim-config.c (current_environment): Delete. + (sim_config_default): New function. + (sim_config): Set STATE_ENVIRONMENT, not current_environment. + * sim-config.h (current_environment,CURRENT_ENVIRONMENT): Delete. + (sim_config_default): Add prototype. + * sim-module.c (sim_pre_argv_init): Call sim_config_default. + * sim-options.c (standard_option_handler, case OPTION_ENVIRONMENT): + Set STATE_ENVIRONMENT, not current_environment. + +Mon Mar 9 11:59:03 1998 Jim Wilson + + * sim-fpu.c (NR_GUARDS64): Change NR_PAD32 to NR_PAD64. + +Tue Mar 3 10:53:05 1998 Andrew Cagney + + * sim-types.h (SIGNED32, SIGNED64): Pacify GCC. + + * sim-alu.h (ALU64_BEGIN): Make alu64_r unsigned. + +Mon Mar 2 10:20:06 1998 Doug Evans + + * Make-common.in (TAGS): Make smarter. + * Makefile.in (TAGS): Ditto. + +Fri Feb 27 19:09:57 1998 Doug Evans + + * sim-module.c (*): Fix typos in assertion tests. + +Sat Feb 28 13:54:10 1998 Andrew Cagney + + * sim-module.c (sim_pre_argv_init): String passed to asprintf + can't be constant. + + * sim-options.c (sim_parse_args): Ditto. + (sim_args_command): Return OK, instead of nothing, for an empty + command. + +Fri Feb 27 13:29:13 1998 Andrew Cagney + + * sim-profile.c (profile_info): Rename from profile_print. Drop + misc and misc_cpu callback arguments. Use + PROFILE_INFO_CPU_CALLBACK and STATE_PROFILE_INFO_CALLBACK instead. + (profile_install): Install profile_info function. + + * sim-profile.h (PROFILE_INFO_CPU_CALLBACK, + STATE_PROFILE_INFO_CALLBACK): Define. + (struct PROFILE_DATA): Add field info_cpu_callback. + (profile_print): Delete function. + + * sim-base.h (STATE_MODULES): Define. Replace individual + STATE_*_LIST with single struct module_list. + + * sim-module.h (MODULE_INFO_FN, MODULE_INFO_LIST): Declare. + (struct module_list): Declare. + + * sim-module.h, sim-module.c (sim_module_add_info_fn, + sim_module_info): New functions. + (sim_module_install): Clean up module data structures. + + * sim-info.c (sim_info): New file. New function. Call + sim_module_info. + + * Make-common.in (sim-info.o): Define rule. + (SIM_NEW_COMMON_OBJS): Add sim-info.o. + + +Fri Feb 27 18:26:16 1998 Doug Evans + + * sim-base.h (sim_cpu_base): New members name, options. + (sim_cpu_lookup): Add prototype. + * sim-module.c (sim_pre_argv_init): Provide default names for cpus. + * sim-options.h (DECLARE_OPTION_HANDLER): New argument `cpu'. + (sim_add_option_table): Update prototype. + * sim-options.c (sim_add_option_table): New argument `cpu'. + (standard_option_handler,standard_install): Update. + (sim_parse_args): Handle cpu specific options. + (print_help): New static function. + (sim_print_help): Call it. Print cpu specific options. + (find_match): New static function. + (sim_args_command): Call it. Handle cpu specific options. + * sim-utils.c (sim_cpu_lookup): New function. + * sim-memopt.c (memory_option_handler): Update. + (sim_memopt_install): Update. + * sim-model.c (model_option_handler): Update. + (model_install): Update. + * sim-profile.c (profile_option_handler): Update. + (profile_install): Update. + * sim-trace.c (trace_option_handler): Update. + (trace_install): Update. + * sim-watch.c (watchpoint_option_handler): Update. + (sim_watchpoint_install): Update. + * cgen-scache.c (scache_option_handler): Update. + (scache_install): Update. + +Wed Feb 25 11:00:26 1998 Doug Evans + + * Make-common.in (check): Run `make check' in testsuite dir. + +Wed Feb 25 14:40:24 1998 Andrew Cagney + + * sim-trace.c (trace_result0): New function. + + * sim-trace.h (TRACE_FP_*, TRACE_FPU_*): Rename TRACE_FPU_* + macro's to TRACE_FP_*. TRACE_FPU_* should be defined and used when + tracing sim_fpu variables. + (TRACE_ALU_RESULT0): Define. + (TRACE_FP_RESULT_WORD): Define. + (TRACE_FP_INPUT_WORD1): Define. + + * sim-fpu.c, sim-fpu.h (sim_fpu_max32, sim_fpu_max64, sim_fpu_one, + sim_fpu_two): New constants. + (sim_fpu_op1, sim_fpu_op2): New types. + (struct _sim_fpu): Delete member result. Re-order other members. + (sim_fpu_sign, sim_fpu_exp): New functions. + (sim_fpu_max, sim_fpu_min): new functions. + (EXPMAX32, EXPMAX64, NR_PAD32, NR_PAD64, NR_GUARDS32, NR_GUARDS64, + NORMAL_EXPMAX32, NORMAL_EXPMAX64): Define. + +Tue Feb 24 22:45:39 1998 Doug Evans + + * sim-profile.c (profile_print): Delete duplicate test of + PROFILE_INSN_IDX. + (profile_print_pc): Exit early if data collection not set up. + (profile_print_core): Simplify by calling sim_core_map_to_str. + * sim-core.h (sim_core_map_to_str): Declare. + * sim-core.c (sim_core_map_to_str): Make non-static. + + * genmloop.sh (engine_resume): Update insn_count before exiting. + (engine_resume_full): Keep accurate core profile data. + + * cgen-utils.c (sim_disassemble_insn): Don't use + sim_core_read_aligned_N, it messes up profiling results. + +Mon Feb 23 20:45:57 1998 Mark Alexander + + * nltvals.def: Regenerate with MN10300 additions. + +Tue Feb 24 13:18:42 1998 Andrew Cagney + + * sim-trace.h (TRACE_ALU_RESULT2): Define. + + * sim-trace.h, sim-trace.c (trace_result_word2, + trace_input_word4, trace_result_word4): New function. + +Mon Feb 23 13:08:35 1998 Doug Evans + + * cgen-sim.h (SEM_NEXT_PC): New arg `len'. + + * sim-xcat.h: Delete. + * cgen-mem.h: Delete inclusion of sim-xcat.h. + * cgen-sim.h: Ditto. + * sim-alu.h: Replace sim-xcat.h with symcat.h. + * sim-n-bits.h: Ditto. + * sim-n-core.h: Ditto. + * sim-n-endian.h: Ditto. + +Mon Feb 23 13:19:58 1998 Michael Meissner + + * syscall.c (cb_syscall): Handle short reads, and EOF. + +Tue Feb 24 00:29:57 1998 Andrew Cagney + + * sim-trace.c (print_data): case trace_fmt_fp missing break. Use + sim_fpu to safely print fp_word values. + (print_data): Add trace_fmt_bool and trace_fmt_addr. + (trace_result_bool1, trace_result_addr1): New functions. + (trace_input_bool1, trace_input_addr1): New functions. + + * sim-trace.h (TRACE_FPU_*): Define. + +Mon Feb 23 13:24:54 1998 Andrew Cagney + + * sim-fpu.h (enum sim_fpu_class): Add sim_fpu_class_denorm. + (sim_fpu_fpto, sim_fpu_tofp): Define. + +Fri Feb 20 18:08:51 1998 Andrew Cagney + + * sim-fpu.c (sim_fpu_cmp): New function. + +Wed Feb 18 16:29:21 1998 Doug Evans + + * cgen-utils.h (sim_disassemble_insn): Use CGEN_INSN_BITSIZE + instead of abuf->length. + * sim-trace.c (trace_options): Have -t only trace a few useful things. + (set_trace_option_mask): Renamed from set_trace_options. + (set_trace_option): New function. + (trace_option_handler): Update calls to set_trace_option{,_mask}. + * sim-trace.h (TRACE_USEFUL_MASK): New macro. + +Wed Feb 18 12:42:15 1998 Andrew Cagney + + * sim-basics.h: Declare struct _sim_fpu. + +Tue Feb 17 16:27:46 1998 Andrew Cagney + + * sim-trace.h (TRACE_ALU_INPUT*, TRACE_ALU_RESULT): Define. + (trace_prefix, trace_input*, trace_result*): Declare. + (trace_one_insn): Change declaration, assume trace_prefix called. + (trace_generic): Like trace_one_insn. + (TRACE_ALU_IDX, TRACE_*_IDX): Change #define's to enum. + (TRACE_alu, TRACE_[a-z]*): Update. + + * sim-trace.c (trace_prefix, trace_input*, trace_result*, + trace_insn, save_data, trace_idx_to_str, print_data): New + functions. + (trace_one_insn): Rewrite. + (trace_generic): New function. + +Tue Feb 17 17:27:30 1998 Doug Evans + + * aclocal.m4 (USE_MAINTAINER_MODE): New variable. + + * cgen-sim.h (SEMANTIC_CACHE_FN): Delete. + (SEMANTIC_FN): Rewrite declaration. + (DECODE): Update type of semantic_fast member. + ({EX,SEM}_FN_NAME): Have only one version. + * sim-base.h (sim_state_base): Delete conditionals surrounding + member scache_size. + +Tue Feb 10 18:31:49 1998 Andrew Cagney + + * sim-load.c (sim_load_file): Print LMA/VMA according to value + used. + +Tue Feb 10 14:56:23 1998 Ian Carmichael + + * sim-core.c: Add missing prototypes for WITH_DEVICES. + Add missing parameters to device_io calls. + * sim-core.h: Add missing parameters to device_io calls. + +Mon Feb 9 14:48:37 1998 Doug Evans + + * cgen-sim.h (DECODE): Always use switch for `read' for now. + (PAREXEC): Renamed from PARALLEL_EXEC. All uses updated. + (SEMANTIC{,_CACHE}_FN): Fix return type. + * genmloop.sh (@cpu@_engine_run): Delete `current_state'. + (engine_resume): Likewise. Make `engine' volatile. Save copy + of cpu pointer in volatile object. Initialize read switch if + -parallel. + +Thu Feb 5 13:27:04 1998 Doug Evans + + * cgen-sim.h (EX_FN_NAME): _exc_ -> _ex_. + (SEM_INSN): New macro. + +Tue Feb 3 16:31:56 1998 Andrew Cagney + + * sim-run.c (sim_engine_run): Assume IMEM is 32 bit. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Feb 1 16:16:57 1998 Andrew Cagney + + * sim-types.h (fp_word): New type, define according to + WITH_TARGET_FLOATING_POINT_BITSIZE. + + * aclocal.m4 (default_sim_floating_point_bitsize): Add + configuration of size of floating point registers. + +Sun Feb 1 14:02:31 1998 Andrew Cagney + + * sim-profile.c (profile_print): Only print CPU if other + output is going to appear. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:03:55 1998 Andrew Cagney + + * sim-types.h (address_word): Typedef according to + WITH_TARGET_ADDRESS_BITSIZE. + (signed_cell, unsigned_cell, natural_cell): Ditto using + WITH_TARGET_CELL_BITSIZE. + + * sim-config.h (WITH_TARGET_ADDRESS_BITSIZE): Define. + (WITH_TARGET_CELL_BITSIZE): Define. + (WITH_HOST_WORD_BITSIZE): Delete. + + * sim-config.c (print_sim_config): Update. + + * aclocal.m4 (SIM_AC_OPTION_BITSIZE): Add support for + configuration of address and OpenFirmware cell sizes. + +Fri Jan 30 09:36:33 1998 Andrew Cagney + + * sim-engine.h (sim_engine_run): Add argument nr_cpus. + * sim-run.c (sim_engine_run): Update. + + * sim-engine.h (SIM_ENGINE_HALT_HOOK): Use SET_CPU_CIA instead of + CPU_CIA. + * sim-run.c (sim_engine_run): Ditto. + + * sim-resume.c (sim_resume): Obtain nr_cpus from sim_engine. + (sim_resume): Pass nr_cpus to sim_engine_run. + + * sim-engine.h (struct _sim_engine): Add member nr_cpus. + + * sim-engine.c (sim_engine_init): Hardwire nr_cpus to + MAX_NR_PROCESSORS. + (sim_engine_nr_cpus) sim-engine.c, sim-engine.h: New function + +Fri Jan 23 14:20:54 1998 Doug Evans + + * Make-common.in (stamp-tvals): New rule. + (targ-vals.h,targ-map.c): Depend on it. + (clean): Remove stamp-tvals. + +Tue Jan 20 21:35:13 1998 Michael Meissner + + * sim-utils.c (sim_state_alloc): #if 0 variable that is only used + in code also #if 0'ed. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * aclocal.m4: Recognize --enable-maintainer-mode. + +Mon Jan 19 12:45:45 1998 Doug Evans + + * cgen-scache.h: Deleted. + * Make-common.in (cgen-run.o,cgen-scache.o): Delete cgen-scache.h dep. + * cgen-scache.c: Only compile contents if WITH_SCACHE. + (scache_init): Use runtime computed size of SCACHE. + (scache_flush): Likewise. + * cgen-mem.h (GETIMEMU[QHSD]I): Declare. + ([GS]ETT{QI,UQI,HI,UHI,SI,USI,DI,UDI}): Declare. + * cgen-sim.h: Scache support moved here. + (PC): Redo definition. + (ARGBUF,SCACHE,PARALLEL_EXEC): Provide forward decls. + (DECODE): Add parallel execution support. + Only include semantic label members if using switch. + (SWITCH,CASE,BREAK,DEFAULT,ENDSWITCH): Portable computed goto support. + (CGEN_CPU): Delete members exec_state, halt_sigrc, halt_jmp_buf. + (IADDR,CIA,SEM_ARG,EX_FN_NAME,SEM_FN_NAME,RECORD_IADDR,SEM_ARGBUF, + SEM_NEXT_PC,SEM_BRANCH_VIA_{CACHE,ADDR},SEM_NEW_PC_ADDR): Moved here + from cgen-types.h. + (engine_{stop,run,resume,halt,signal}): Delete decls. + * cgen-types.h (CGEN_{XCAT3,CAT3}): Delete. + (argbuf,scache): Delete forward decls. + (STATE): Delete decl. + * cgen-utils.c: Don't include decode.h, mem-ops.h, sem-ops.h. + Include cgen-mem.h, cgen-ops.h. + (engine_halt,engine_signal): Delete. + ({ex,exc,sem,semc}_illegal): Delete. + (sim_disassemble_insn): Result of extract fn is in bits. + * genmloop.sh: Rewrite. + + * cgen-trace.c (trace_insn): Set printed_result_p=0 if not tracing + line numbers. + + * sim-base.h (sim_state_base): Delete member `model'. + (sim_cpu_base): Add member `model'. + * sim-model.h (IMP_PROPERTIES): New type. + (MACH): New members imp_props, models. + (models): Delete decl. + * sim-model.c (set_model): Update. + * sim-profile.c (profile_print_model): Update. + + * sim-utils.c (sim_state_alloc): Delete setting of cpu backlink here. + +Fri Jan 16 12:33:09 1998 Nick Clifton + + * cgen-trace.c (trace_insn): Call CGEN_INSN_MNEMONIC() rather than + CGEN_INSN_SYNTAX(). + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Dec 15 23:16:03 1997 Andrew Cagney + + * aclocal.m4 (AR): Check for sigaction. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * Make-common.in (sim-core.o): Depend on $(sim_main_headers). + + * sim-config.h (WITH_TREE_PROPERTIES): Define as 0. + * sim-config.c (sim_config): Replace WITH_DEVICES with + WITH_TREE_PROPERTIES. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Dec 3 17:56:02 1997 Doug Evans + + * Make-common.in (SIM_ENVIRONMENT): New variable. + (CONFIG_CFLAGS): Add it. + * aclocal.m4 (SIM_AC_OPTION_ENVIRONMENT): Handle + --enable-sim-environment option. + * configure: Regenerated. + * sim-config.h (environment support): Rewrite. + * sim-config.c (current_environment): Define as enum, unconditionally. + (current_alignment): Define unconditionally. + (config_environment_to_a): Update. + (config_alignment_to_a): Fix type of argument. Define unconditionally. + (sim_config): Handle environment and alignment determination + unconditionally. Delete sanity checks of current_environment, + unnecessary. + (print_sim_config): Update. + * sim-options.c (STANDARD_OPTIONS enum): Add OPTION_ENVIRONMENT. + (standard_options): Add --environment. + (standard_option_handler): Likewise. + +Fri Nov 28 12:21:25 1997 Andrew Cagney + + * sim-alu.h: Add notes on carry vs borrow for subtraction. + (ALU{,8,16,32,64}ADD): Redefine ADD macro as add overflowing. + (ALU{,8,16,32,64}ADDC): Define - add carrying. + (ALU{,8,16,32,64}SUB): Redefine SUB macro as subtract overflowing. + (ALU{,8,16,32,64}SUBB): Define - subtract borrowing. + (ALU{,8,16,32,64}SUBC): Define - tract carrying. + (ALU{,8,16,32,64}ADD_CA, ALU{,8,16,32,64}ADDC_C): Replace single + argument ADD_CA macro with two argument ADDC_C - add carrying with + carry in. + (ALU{,8,16,32,64}SUB_CA, ALU{,8,16,32,64}SUBC_X): Replace single + argument SUB_CA macro with two argument SUBC_X - subtract + carrying, extended. + (ALU{,8,16,32,64}SUBB_B): Define - subtract borrowing with + borrow-in. + (ALU{,8,16,32,64}NEGC, ALU{,8,16,32,64}NEGB): Define. + +Sun Nov 30 17:40:57 1997 Michael Meissner + + * sim-io.c (sim_io_{syscalls,getstring}): Delete. No longer used. + * sim-io.h (sim_io_syscalls): Delete. + +Fri Nov 28 20:10:09 1997 Michael Meissner + + * syscall.c (cb_syscall): Add missing else, so write to stdout + isn't doubled. + + * sim-alu.h (ALU{,8,16,32,64}_SET_CARRY): Provide macros to import + the carry bit from the CPU's psw. + +Fri Nov 28 11:15:05 1997 Doug Evans + + * gennltvals.sh: Redo syscall support. + * nltvals.def: Regenerated. + +Wed Nov 26 16:49:38 1997 Michael Meissner + + * syscall.c (cb_syscall): If writing to stdout or stderr, flush + the stream immediately. + +Wed Nov 26 12:32:11 1997 Andrew Cagney + + * sim-io.c (sim_io_getstring): Delete unused len2. + (sim_io_syscalls): Ditto for sys_errno. + +Wed Nov 26 11:18:40 1997 Doug Evans + + * syscall.c (cb_syscall): Test CB_SYSCALL struct magic number. + + * Make-common.in (run.o): Depend on remote-sim.h. + (nrun.o,sim-hload.o,sim-hrw.o): Likewise. + (sim-io.o,sim-reason.o,sim-resume.o): Likewise. + +Tue Nov 25 20:12:46 1997 Michael Meissner + + * sim-io.c (sim_io_syscalls): Disable lseek. + +Tue Nov 25 00:12:38 1997 Doug Evans + + * gennltvals.sh: Generate syscall values for d30v. + + * gennltvals.sh: Use libgloss/syscall.h for sparc. + * nltvals.def: Regenerate. + + * callback.c (os_stat): Make 3rd arg a host struct stat ptr. + (os_fstat): Likewise. Validate fd argument. + (cb_host_to_target_stat): Delete big_p arg. If HS arg is NULL, + just compute target stat struct length. + * syscall.c: #include "libiberty.h", , . + (ENOSYS,ENAMETOOLONG): Provide definitions if missing. + (get_string): Return host errno values so they can be properly + translated later. + (cb_syscall): Likewise. + (cb_syscall, cases open,unlink): Use get_path instead of get_string. + (cb_syscall, case read): Use read_stdin for file descriptor 0. + (cb_syscall, case write): Use write_stderr for file descriptor 2. + (cb_syscall): Add cases for lseek, unlink, stat, fstat, time. + (get_path): New function. + +Mon Nov 24 18:56:07 1997 Michael Meissner + + * sim-io.c (sim_io_syscalls): New function to provide system call + emulation. Provide exit, open, close, read, write, lseek, and + unlink. + (sim_io_getstring): New function to return a string from a + simulated memory location. + + * sim-io.h (sim_io_syscalls): Add declaration. + +Mon Nov 24 12:09:59 1997 Doug Evans + + * sim-core.c (sim_core_signal): Fix spelling error in message. + + * sim-hrw.c (sim_read): Use read map, not write map. + + * Make-common.in (all): Add .gdbinit. + * gdbinit.in: Add dump command. + + * sim-model.c (model_options): Use '\0' for `shortopt'. + + * sim-trace.c (trace_option_handler): Set state trace file + for --trace-file in addition to cpu's values. + (trace_vprintf): If cpu == NULL, try state's trace file. + (trace_options): Reorganize table, reword some descriptions. + +Sun Nov 23 10:57:00 1997 Andrew Cagney + + * sim-fpu.c (sim_fpu_abs, sim_fpu_neg, sim_fpu_inv), sim-fpu.h: + New functions. + +Sat Nov 22 19:16:54 1997 Andrew Cagney + + * sim-reason.c (sim_stop_reason): For sim_signalled, return the + signal untranslated, document problem with this. + + * nrun.c (main): Check for a prog name of `*step'. If present, + step the simulator instead of allowing it to run free. + + * sim-signal.c (SIGQUIT): Define on _MSC_VER hosts. + + * Make-common.in (sim_main_headers): Add sim-signal.h. + +Fri Nov 21 09:32:32 1997 Andrew Cagney + + * sim-signal.c (sim_signal_to_host): Return 0 for SIM_SIGNONE. + +Thu Nov 20 20:35:20 1997 Andrew Cagney + + * sim-signal.h: Start simulator signals at 64 so that host signal + numbers can be detected and reported. + + * sim-signal.h (SIM_SIGFPE), sim-signal.h: Add signal. + +Wed Nov 19 12:02:41 1997 Doug Evans + + * callback.c (cb_host_to_target_stat): Fix return values. + + * cgen-sim.h (enum_signal_type): Delete. + (engine_signal): Update prototype. + * cgen-utils.c: Don't include . + (sim_signal_to_host): Delete, lives in sim-signal.c now. + (engine_signal): Update. + + * sim-utils.c (sim_state_alloc): Call SIM_STATE_ALLOC if defined. + (sim_state_free): Call SIM_STATE_FREE if defined. + + * sim-module.c (sim_module_install): Don't leave any modules + installed if one fails to install. + +Wed Nov 19 13:25:48 1997 Michael Meissner + + * sim-options.c: Don't include ../libiberty/alloca-conf.h any + more, since alloca is not used in this file. + + * sim-alu.h (ALU{32,64}_*): Rewrite 32 and 64 bit ALU support to + correctly set the carry and overflow bits for those types. + (ALU{8,16,32,64}_{ADD,SUB}_CA): Take VAL argument to add along + with carry, so carry is correct after doing both adds. + (ALU*): Space out '\' to make it easier to read. + +Tue Nov 18 15:53:45 1997 Doug Evans + + * sim-core.c (sim_core_signal): Use sim_stopped instead of + sim_signalled. + + * sim-signal.c, sim-signal.h: New files. + * Make-common.in (sim-signal.o): Add rule for. + (SIM_NEW_COMMON_OBJS): Add sim-signal.o. + * sim-abort.c: Don't include . + * sim-basics.h: #include "sim-signal.h". + * sim-break.c: Don't include . + (sim_handle_breakpoint): Replace SIGTRAP with SIM_SIGTRAP. + * sim-core.c: Don't include . + (SIGBUS): Delete definition. + (sim_core_signal): Replace SIGSEGV,SIGBUS with SIM_SIGSEGV,SIM_SIGBUS. + * sim-engine.c: Don't include . + (sim_engine_abort): Replace SIGABRT with SIM_SIGABRT. + * sim-reason.c (sim_stop_reason): Call sim_signal_to_host. + * sim-resume.c: Don't include . + (SIGTRAP): Delete definition. + (has_stepped): Replace SIGTRAP with SIM_SIGTRAP. + * sim-stop.c: Don't include . + (control_c_simulation): Replace SIGINT with SIM_SIGINT. + * sim-watch.c: Don't include . + (handle_watchpoint): Replace SIGINT with SIM_SIGINT. + + * Make-common.in (SIM_NEW_COMMON_OBJS): New variable. + + * sim-base.h (CIA_ADDR): Provide default definition. + * sim-core.c (sim_core_signal): Use CIA_ADDR to fetch value. + * sim-break.c (sim_handle_breakpoint): Likewise. + +Mon Nov 17 14:15:31 1997 Doug Evans + + * Make-common.in (srccom): New variable. + + * Make-common.in (DEP, COMMON_DEP_CFLAGS): Define. + (LIB_OBJS): Add syscall.o. + (gentmap): Pass $(NL_TARGET) to $(CC). + (syscall.o): Add rule for. + (sim_main_headers): Add $(SIM_EXTRA_DEPS). + (sim-bits.o): Depend on $(sim-n-bits_h). + (sim-load.o): Depend on callback.h. + + * Make-common.in (cgen-*.o): Update dependencies, mem-ops.h renamed to + cgen-mem.h, sem-ops.h renamed to cgen-ops.h. + * cgen-mem.h, cgen-ops.h: New files. + + * aclocal.m4 (--enable-sim-scache): Pass -DWITH_SCACHE=0 for "=no". + + * Makefile.in (nltvals.def): Depend on gennltvals.sh. + Rewrite build rule. + * callback.c: #include string.h or strings.h. + #include sys/types.h and sys/stat.h. + (cb_init_syscall_map,cb_init_errno_map,cb_init_open_map): Declare. + (os_get_errno,os_open): Update. + (os_stat,os_fstat): New functions. + (os_init): Initialize syscall_map, errno_map, open_map. + (default_callback): Add entries for os_stat, os_fstat, syscall_map, + errno_map, open_map, signal_map, stat_map. + (cb_read_target_syscall_maps): New function. + (cb_target_to_host_syscall): New function. + (cb_host_to_target_errno): Renamed from host_to_target_errno. + (cb_target_to_host_open): Renamed from target_to_host_open. + (store): New function. + (cb_host_to_target_stat): New function. + * syscall.c: New file. + * gentmap.c (sys_tdefs): New global. + (gen_targ_vals_h): Output target syscall numbers. + (gen_targ_map_c): Update. Output target syscall translation map. + * gentvals.sh: New first argument `target'. Preface table with + #ifdef NL_TARGET_$target if non-null target passed. + * gennltvals.sh: New file. + * nltvals.def: Regenerated. + +Fri Nov 14 11:33:34 1997 Andrew Cagney + + * sim-n-core.h (sim_core_read_unaligned_N): Return static + sim_core_dummy_M. + (sim_core_dummy_M): Declare. + +Wed Nov 12 18:16:15 1997 Andrew Cagney + + * sim-core.c (sim_core_signal): Print the address of the + instruction. + +Thu Nov 13 11:49:41 1997 Doug Evans + + * sim-base.h (sim_state_base): Move `magic' to end of struct. + + * sim-base.h (sim_state_base): Add member trace_data. + (STATE_TRACE_DATA): New macro. + * sim-trace.h (TRACE_DEBUG_IDX,TRACE_debug): New macros. + ({WITH_,}TRACE_DEBUG_P): New macros. + (STATE_TRACE_FLAGS,STRACE_P,STRACE_DEBUG_P): New macros. + (_sim_cpu): Delete forward reference. + (debug_printf): Update. + * sim-trace.c (OPTION_TRACE_DEBUG): Define. + (trace_options): Add --trace-debug. + (set_trace_options): Handle it. + (trace_option_handler): Likewise. + (trace_install): Init state trace_data struct. + (trace_uninstall): Close state trace file. + * sim-events.c (ETRACE): Only print source file and line number if + --trace-debug. + * sim-n-core.h (sim_core_trace_M): Likewise. + + * sim-core.c (sim_core_signal): Add missing "\n" in message. + +1997-11-13 Felix Lee + + * sim-n-core.h (sim_core_read_unaligned_N): illegal empty + initializer. + * sim-types.h (unsigned128,signed128): fix typo for MSVC. + +Wed Nov 12 12:18:08 1997 Doug Evans + + * aclocal.m4 (SIM_AC_OPTION_SCACHE): Fix typo. + + * Make-common.in (BUILT_SRC_FROM_COMMON): Remove files no longer + built this way. + (sim-config.o): Remove non-existent $(sim-nconfig_h) dependency. + (clean): Don't delete $(BUILT_SRC_FROM_COMMON) if building in + source tree. + +Tue Nov 11 13:28:02 1997 Andrew Cagney + + * sim-events.c (sim_events_process): Re-compute the time - + update_time_from_event - as each event is processed. Reverses + previous change. + +Fri Nov 7 00:37:36 1997 Andrew Cagney + + * callback.c (os_poll_quit): Replace _WIN32 with _MSC_VER. + +Fri Nov 7 00:37:36 1997 Andrew Cagney + + * sim-events.c (sim_events_process): Delete redundant call to + update_time_from_event. + (sim_events_slip): Always decrement time_from_event. + (sim_events_tick, sim_events_deschedule, update_time_from_event): + Delete assertion that time_from_event >=0 when work in queue, no + longer applicable. + +Thu Nov 6 12:06:46 1997 Andrew Cagney + + * sim-options.c (STANDARD_OPTIONS): Change OPTION_* to an enum. + (standard_option_handler): Update. + + * sim-options.h: Clarify documentation. + (OPTION_LONG_ONLY_P): Delete definition. + (OPTION_VALID_P): Define. + + * sim-options.c (sim_print_help): Allow short only options. + (sim_parse_args): Ditto. + (sim_args_command): Skip short only options. + (sim_parse_args): Allocate space for NUM_OPTS not just 256. Make + separate entries for short and long options in the HANDLERS and + ORIG_VAL tables. + (sim_parse_args): Disable argument permutation. + +Wed Nov 5 13:40:31 1997 Andrew Cagney + + * sim-core.h (DECLARE_SIM_CORE_WRITE_N. DECLARE_SIM_CORE_READ_N): + Add argument M, size of data type. + (sim_core_read_misaligned_3, sim_core_write_misaligned_3): + Declare, ditto for 5, 6 & 7 byte transfers. + (sim_core_write_unaligned_1, sim_core_write_unaligned_1): Define + as aligned variant. + + * sim-n-core.h (sim_core_trace_M): Rename from + sim_core_trace_N. Add nr_bytes argument. Replace transfer argument + with transfer type. Print transfer direction. Handle 1 and 2 byte + transfers. + (sim_core_read_unaligned_N, sim_core_write_unaligned_N): Trace + unaligned accesses. + (unsigned_M, T2H_M, H2T_M): Rename from unsigned_N, T2H_N, H2T_N. + Update all functions. + + * sim-core.c: Generate functions starting with 16 not 1. + (sim_core_read_unaligned_3): Generate. Ditto for 3 byte write and + all 5, 6 & 7 byte transfers. + + * sim-n-core.h (sim_core_read_misaligned_N, + sim_core_write_misaligned_N): Implement. + +Mon Nov 3 15:03:04 1997 Andrew Cagney + + * sim-endian.h (U16_8): Implement + + * sim-endian.c (sim_endian_split_16, sim_endian_join_16): New functions + + * sim-endian.h (VL8_16, VH8_16): Implement. + + * sim-memopt.c (memory_option_handler): Typecast 64bit value to + long in printf. + (memory_option_handler): Only zalloc modulo bytes when non-zero. + (memory_option_handler): Skip comma in alias address list + +Fri Oct 31 13:03:33 1997 Andrew Cagney + + * sim-memopt.c (do_memopt_add, do_memopt_delete): Add level and + space params. + (parse_size, parse_addr): New functions + (memory_option_handler, memory_options): Parse address & size + using new functions. Pass level, space, modulo to do_memopt_add & + do_memopt_del. + + * sim-memopt.h (struct _sim_memopt): Add level & space fields. + + * sim-core.h (sim_core_arrach, sim_core_detach): Replace + `attach_type attach' argument with `unsigned level' argument. + Document. + + * sim-core.c (new_sim_core_mapping, sim_core_map_attach, + sim_core_attach): Replace argument attach with level. Update + verification of arguments. + (sim_core_map_detach, sim_core_detach): Replace argument attach + with level. + + * sim-basics.h (enum _attach_type): Delete. + +Thu Oct 30 13:45:00 1997 Doug Evans + + * sim-core.h (sim_core_write_8): Define. + +Tue Oct 28 12:29:22 1997 Andrew Cagney + + * sim-bits.h: Document ROTn macro. + + * sim-endian.h (H2T): Handle 16 byte variables. + + * sim-n-core.h (sim_core_read_unaligned_N): Return a dummy when an + error. + + * sim-core.c: Do not generate sim_core_*_word. + + * sim-n-core.h (sim_core_trace_N): Add line_nr argument. + (sim_core_write_aligned_N, sim_core_read_aligned_N): Update. + + * sim-core.h (sim_core_read_unaligned_word, + sim_core_read_aligned_word, sim_core_read_word, + sim_core_write_unaligned_word, sim_core_write_aligned_word, + sim_core_write_word): Change to macros that map onto sim_core_*_N. + +Mon Oct 27 11:25:10 1997 Doug Evans + + * sim-n-endian.h: Add TAGS entrys for 16 byte versions. + + * sim-endian.h: Disable 16 byte support. + +Mon Oct 27 12:00:48 1997 Andrew Cagney + + * sim-endian.c (_SWAP_16): Define. Generate 126 bit swap code. + + * sim-n-core.h (sim_core_trace_N): New function. + (sim_core_read_aligned_N, sim_core_write_aligned_N): Use, + (sim_core_read_unaligned_N): Do not retyrn bogus value wden error. + + * sim-endian.h: Add 128 bit variant. + + * sim-core.h, sim-core.c: Add 128 bit variant. + + * sim-types.h: Add signed128 and unsigned128 types using a struct. + +Fri Oct 24 11:33:07 1997 Andrew Cagney + + * sim-events.c (sim_events_process): Clear events->work_pending. + (sim_events_tickn, sim_events_tick): Accumulate, instead of + setting, nr_ticks_to_process. + (sim_events_preprocess): Allow nr_ticks_to_process to be non-zero + when the event queue isn't next. + + * sim-events.h, sim-events.c (sim_events_slip): New function. + +Wed Oct 22 14:18:38 1997 Andrew Cagney + + * sim-hload.c (sim_load): Pass lma_p==0 and do_load=sim_load. + + * sim-utils.h, sim-load.c (sim_load_file): Add lma_p and do_load + arguments. + +Tue Oct 21 18:37:57 1997 Doug Evans + + * nrun.c (main): Remove useless test of name != NULL. + Exit if bfd_openr fails. Call bfd_check_format after bfd_openr. + +Tue Oct 21 10:42:38 1997 Andrew Cagney + + * sim-fpu.c (EXPMAX): Type is unsigned. + (MIN_INT, MAX_INT): Type is signed64. + (i2fpu): Type of val is signed64. + +Tue Oct 21 10:42:38 1997 Andrew Cagney + + * sim-profile.h (PROFILE_PC_BUCKET_SIZE): Treat a shift of zero as + a bucket size of zero. + + * sim-profile.c (OPTION_PROFILE_PC_GRANULARITY, + OPTION_PROFILE_PC): Define. + (profile_option_handler): Add support for --profile-pc and + --profile-pc-granularity options. + (profile_pc_init): When possible, compute nr buckets from bucket + size. + + * sim-profile.c (profile_pc_init): Align the profile-pc end + address with the profile-pc bucket size. + + * sim-profile.h (PROFILE_PC_NR_BUCKETS): Rename PROFILE_PC_SIZE to + something less ambiguous. + (PROFILE_PC_BUCKET_SIZE): Ditto for PROFILE_PC_SAMPLE_SIZE. + + * sim-profile.c (profile_pc_cleanup): New function. Move + profile_pc_uninstall code to here. + (profile_pc_uninstall): Call. + (profile_pc_init): Call. + +Mon Oct 20 17:23:58 1997 Andrew Cagney + + * sim-profile.c (profile_print_pc): Dump pc profile to dmon.out + file using BSD gprof format. + + * sim-bits.h (LSBIT, MSBIT, BIT): Force result to type + unsigned_word. + (LSBIT8, LSBIT16, LSBIT32, LSBIT64, MSBIT8, MSBIT16, MSBIT32, + MSBIT64): Force result to unsignedN. + +Thu Oct 16 11:38:56 1997 Andrew Cagney + + * sim-alu.h (ALU16_BEGIN, ALU32_BEGIN, ALU64_BEGIN): Drop opening + brace from macro. + (ALU8_BEGIN, ALU8_SET, ALU8_ADD, ALU8_SUB, ALU8_NEGATE): Define. + (ALU16_ADD, ALU16_SUB, ALU16_NEGATE): Simplify arrithmetic. + (ALU32_ADD, ALU32_SUB, ALU32_NEGATE): Simplify arrithmetic. + (ALU64_ADD, ALU64_SUB, ALU64_NEGATE): Simplify arrithmetic. + +Wed Oct 15 09:24:19 1997 Andrew Cagney + + * sim-core.h (struct _sim_core_mapping): Change free_buffer to + type void*. + + * sim-core.c (sim_core_uninstall, new_sim_core_mapping, + sim_core_map_attach, sim_core_map_detach): Change free_buffer to + type void*. + (sim_core_attach): Rename buffer_freed to free_buffer, type + void*. Ensure that allocated buffer is alligned according to + region's address. + +Mon Oct 13 11:34:50 1997 Andrew Cagney + + * sim-alu.h (ALU64_HAD_OVERFLOW): Define. + (ALU64_SUB): Define. + + * Make-common.in (all): Build SIM_EXTRA_ALL first. + (.gdbinit): Remove dependencies, generate once per build. + +Tue Oct 14 19:20:09 1997 Andrew Cagney + + * sim-n-core.h (sim_core_read_aligned_N, + sim_core_write_aligned_N): Make xaddr param type address_word not + unsigned_word. + +Fri Oct 3 09:49:18 1997 Andrew Cagney + + * sim-fpu.h, sim-fpu.c: Rewrite. Change sim_fpu object to an + unpacked floating point struct. Pass sim_fpu object by reference. + Add preliminary support for rounding modes. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Oct 2 19:43:52 1997 Andrew Cagney + + * aclocal.m4 (sim-bitsize): Fix typo, WITH_TARGET_WORD_BITSIZE not + WITH_TARGET_BITSIZE. + +Thu Sep 25 23:20:20 1997 Felix Lee + + * sim-profile.c (profile_print_core): label needs empty statement. + +Thu Sep 25 11:20:47 1997 Stu Grossman + + * sim-break.c (sim_set_breakpoint sim_clear_breakpoint): Use ZALLOC + and zfree instead of xmalloc and free. Prevents warnings. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:23:31 1997 Andrew Cagney + + * Make-common.in (SIM_BITSIZE): Assign from configured value. + (CONFIG_CFLAGS): Add SIM_BITSIZE. + + * aclocal.m4 (--enable-sim-bitsize): Developer option for + controling the bitsize/msb of the target. + +Wed Sep 24 17:41:40 1997 Stu Grossman + + * Make-common.in: New files sim-break.c, sim-break.h. + * sim-base.h: Add point to breakpoint list to sim_state_base. + * sim-break.c sim-break.h: New modules that implement intrinsic + breakpoint support. + * sim-module.c: Add breakpoint module. + +Tue Sep 23 00:26:39 1997 Felix Lee + + * sim-events.c (SIM_EVENTS_POLL_RATE): poll more often than once + an hour. + * sim-n-core.h (WITH_XOR_ENDIAN): MSVC barfs on + if (0) { 1 % 0; } + * sim-core.c (sim_core_xor_write_buffer): WITH_XOR_ENDIAN + 1. + (SIGBUS) define for Windows. + * sim-trace.c (trace_printf,debug_printf): added ALMOST_STDC. + * sim-resume.c: define SIGTRAP for windows. + * sim-xcat.h: use token pasting if ALMOST_STDC. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * Make-common.in (SIM_SCACHE, SIM_DEFAULT_MODEL): Assign + configured values. + (CONFIG_CFLAGS): Add same. + +Mon Sep 22 17:20:27 1997 Felix Lee + + * sim-types.h (SIGNED64): ##i64 when _MSC_VER, not _WIN32. + (SIGNED32): use ##i32. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 10:07:47 1997 Andrew Cagney + + * aclocal.m4 (sim-endian): Simplify logic determining [default] + endian of target. + + * Make-common.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN, + SIM_HOSTENDIAN, SIM_RESERVED_BITS, SIM_ASSERT, SIM_FLOAT, + SIM_HARDWARE, SIM_INLINE, SIM_PACKAGES, SIM_REGPARM, SIM_SMP, + SIM_STDCALL, SIM_XOR_ENDIAN): Assign configured values. + (CONFIG_CFLAGS): Add same. + + * aclocal.m4: Perform AC_SUBST on optional options. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * sim-config.h (WITH_DEFAULT_ALIGNMENT): Don't hardwire any alignment. + + * sim-options.c (standard_option_handler): Typo in warning message. + + * sim-base.h (STATE_MODEL): Make conditional on SIM_HAVE_MODEL. + + * sim-profile.c (profile_print_insn): Check 0 .. MAX_INSN for any + insn count. Make count conditional on there being a valid + INSN_NAME. + (profile_pc_init): Make default PC profile frequency an arbitrary + 256. + + * sim-base.h: Ditto. + + * sim-profile.h (WITH_PROFILE_MODEL_P): Only enable modeling when + SIM_HAVE_MODEL. + + * sim-model.h (struct MACH): Depreciate, to be replaced by bfd + archure struct. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 22 11:45:00 1997 Andrew Cagney + + * aclocal.m4 (sim_alignment): Simplify logic for selecting the + configured alignment. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:26:14 1997 Andrew Cagney + + * sim-config.c (sim_config): Check for default alignment. + + * sim-options.c (standard_option_handler): Add alignment option. + + * aclocal.m4 (sim_alignment): Allow configuration of hardwired and + default alignment requirements on memory accesses. + +Fri Sep 19 11:51:35 1997 Jeffrey A Law (law@cygnus.com) + + * sim-load.c (sim_load_file): Return failure if the executable + had no loadable sections. + +Wed Sep 17 13:33:28 1997 Andrew Cagney + + * sim-events.c (ETRACE): Use trace_printf not sim_io_printf for + trace output. + + * sim-core.c (sim_core_signal): When bad access halt simulator + SIGSEGV / SIGBUS instead of aborting. + (signal.h): Include. + + * sim-watch.c (sim_watchpoint_install): Handler for watchpoint + options was missing. + + * sim-bits.h (MOVED): Define + +Wed Sep 17 10:33:28 1997 Andrew Cagney + + * sim-alu.h (ALU32_HAD_OVERFLOW): Pacify GCC, Use MSBIT instead of + BIT. + + * sim-bits.h (LSBIT, MSBIT): Check for overflow of shift value. + + * sim-bits.c: Add 8 bit versions of bit macros. + + * sim-bits.h: Ditto. + +Tue Sep 16 16:15:16 1997 Andrew Cagney + + * sim-bits.c (LSSEXT, MSSEXT): Replace SEXT. + (LSINSERTED, MSINSERTED): Ditto for INSERTED. + + * sim-n-bits.h (MSSEXTn, LSSEXTn): Replace SEXTn. + (LSINSERTDn, MSINSERTEDN): Ditto for INSERTEDn. + + * sim-bits.h (SEXT*): Define as MSEXT/LSEXT. + (INSERTED*): Ditto for LSINSERTED/MSINSERTED. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * aclocal.m4 (SIM_AC_COMMON): Add optional config.h file argument. + configure.in: Output to cconfig.h instead of config.h. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 15:39:28 1997 Andrew Cagney + + * sim-utils.c (sim_analyze_program): Set STATE_ARCHITECTURE from + BFD if known. + +Tue Sep 9 21:46:46 1997 Felix Lee + + * callback.c (os_write): divert stdout and stderr to their + respective hooks. + +Thu Sep 11 10:08:48 1997 Andrew Cagney + + * sim-profile.c (profile_print_speed): Call + sim_events_elapsed_time instead of PROFILE_EXEC_TIME for moment. + + * sim-events.c (sim_events_elapsed_time): New function return nr + host MS consumed by the simulator. + (sim_watch_valid): Use. + + * sim-module.c (modules): Install sim_events very very early. + + * sim-profile.c (profile_print): Call profile_print_pc. + (print_bar): + (profile_pc_init): New function, set up processor for PC + profiling. + (profile_print_pc): New function, print a PC profile. + (profile_pc_event): New function, sample PC. + + * sim-profile.h (PROFILE_PC_COUNT, PROFILE_PC_START, + PROFILE_PC_END, PROFILE_PC_SHIFT, PROFILE_PC_SAMPLE_SIZE): Add to + profile struct. + + * sim-options.c (sim_print_help): Pacify GCC. + + * sim-n-core.h (sim_core_read_aligned_N, + sim_core_write_aligned_N): Add un-conditional profile call. + (sim_core_read_unaligned_N, sim_core_write_unaligned_N): Add + profile call when aligned read/write isn't used. + + * sim-base.h: Include sim-profile, sim-model after sim-core & + sim-events allow sim-core to define useful values. + + * sim-profile.c (OPTION_PROFILE_CORE): Define. + (profile_option_handler, profile_options): Add support for + --profile-core option. + (print_bar): Include when core profiling. + (profile_print_core): New function, print core profile. + + * sim-config.c (print_sim_config): Print profile status. + + * sim-profile.h (PROFILE_NEXT_IDX, PROFILE_core, + WITH_PROFILE_PC_P): Define. + (PROFILE_CORE_COUNT): Count each core-map/size separatly. + (PROFILE_COUNT_CORE): Define. + +Thu Sep 11 08:44:52 1997 Andrew Cagney + + * sim-watch.c (handle_watchpoint): Pass a char** index into the + interrupt_names array as the data. + (sim-watch.h): Document. + +Wed Sep 10 16:15:22 1997 Andrew Cagney + + * sim-options.c (sim_print_help): When the doc string is to long + word wrap it. + + * sim-watch.c (sim_watchpoint_install): Use option.doc_name so + that only the first few the watch options are listed. Generate + meanginful usage messages. + + * sim-options.h (struct OPTION): Clarify use of doc_name field + +Wed Sep 10 13:23:24 1997 Andrew Cagney + + * sim-options.c (OPTION_ARCHITECTURE_INFO): New option. + (standard_option_handler): Handle --architecture-info. + +Tue Sep 9 21:46:46 1997 Felix Lee + + * sim-core.h (sim_cpu_core): [WITH_XOR_ENDIAN + 1], to avoid + illegal zero-sized array. + * sim-core.c (sim_core_xor_read_buffer): same. + +Tue Sep 9 11:20:35 1997 Doug Evans + + * nltvals.def: Regenerate. + +Tue Sep 9 02:10:36 1997 Andrew Cagney + + * sim-fpu.c (DP_FRACHIGH2): Define LL using SIGNED64. + +Mon Sep 8 12:22:20 1997 Andrew Cagney + + * sim-bits.c (MASKED): Delete. + (EXTRACTED): Delete. + (LSEXTRACTED, MSEXTRACTED): New functions. + + * sim-n-bits.h (MASKEDn): Delete, define as MSMASKED or LSMASKED. + (MSMASKEDn, LSMASKEDn): Add last argument. + (MSMASK*): Ditto. + + * sim-bits.h (EXTEND8, EXTEND16): Define. + (EXTRACTED64): Define as 64 bit extract, not 32 bit. + + * sim-run.c (sim_engine_run): Use CPU_CIA macro. + + * sim-engine.h (SIM_ENGINE_HALT_HOOK): Use CPU_CIA to get at + current instruction address. + + * sim-inline.h (*_ENGINE): Define. + +Fri Sep 5 08:39:02 1997 Andrew Cagney + + * sim-core.c (sim_core_attach): Fix checks of modulo/mask. + + * sim-watch.c (delete_watchpoint): Delete by ident and type. + (watch_option_handler): Call delete_watchpoint with ident or type. + (sim_watchpoint_install): Create interrupt specific watchpoint + commands on the fly. + (do_watchpoint_create): New function, create a watch point using + type/int-nr info encoded in the option nr. + (do_watchpoint_info): New function. List active watchpoints. + + * sim-watch.h: Change data structure to a list. + + * sim-memopt.c (memory_option_handler): Require explicit "all" + before deleting all memory regions. + + * sim-utils.c (sim_do_commandf): New function, printf version of + sim_do_command. + + * sim-basics.h (asprintf, vasprintf): Hack, define for CYGWIN32. + + * sim-alu.h (ALU64_ADD): Use explicit MSEXTRACTED64, do not assume + bit endianness. + (SIGNED64, UNSIGNED64): Delete. + (ALU64_ADD): Don't rely on bit endianness. + (ALU64_BEGIN): Define. + + * sim-n-bits.h (MSEXTRACTEDn, LSEXTRACTED): New functions. + (EXTRACTEDn): Delete, define as either LSEXTRACTED or MSEXTRACTED. + + * sim-types.h (SIGNED64, UNSIGNED64): New macros, attach relevant + suffix - u64, LL - to 64 bit constants. + +Thu Sep 4 09:27:54 1997 Andrew Cagney + + * sim-config.c (sim_config): Add assert for SIM_MAGIC_NUMBER. + + * sim-utils.h (NZALLOC): Define - zalloc * N. + + * sim-hrw.c (sim_read, sim_write): New file. Provide generic + implementation of read/write functions. + + * Make-common.in (sim-hrw.o): New target. + + * sim-base.h (STATE_MEMOPT_P): Delete, simulators _always_ add + memory. + + * sim-memopt.c (memory_option_handler): Implement memory-size + command. Implement memory-alias command. Let memory-delete delete + all memory regions. + (add_memopt): New function. Add a memory region. + (do_memopt_delete): New function. Delete a memory region. + + * sim-utils.c (sim_elapsed_time_get): Never return zero. + + * sim-core.c (sim_core_detach): New function. + (sim_core_map_detach): New function. Perform the actual detach. + (sim_core_init): Move initialization code from here. + (sim_core_install): To here. + (sim_core_uninstall): And here. + + * sim-module.c: Add memopt module. + + * sim-base.h (STATE_MEMOPT, STATE_MEMOPT_P): Add memopt to + simulator base type. + + * Make-common.in (sim_main_headers): Add sim-memopt.h + (sim-memopt.o): New target. + + * sim-core.c (sim_core_install): Add core_options to the option + table. + + * sim-watch.c (watch_options): Make --delete-watch a synonym for + --watch-delete. + + * sim-config.h (WITH_MODULO_MEMORY): Define as 0. Update + comments. + + * sim-core.h (struct _sim_core_mapping): Change nr_bytes to type + address_word, add mask member. + + * sim-core.h, sim-core.c (sim_core_attach): Make nr_bytes of type + address_word, allow for 64bit targets in 32bit host. Add modulo + argument. + (sim_core_map_attach): Ditto. + (new_sim_core_mapping): Ditto. + (sim_core_translate): Mask address when modulo memory. + +Wed Sep 3 17:32:54 1997 Doug Evans + + * sim-hload.c (sim_load): Add assert for SIM_MAGIC_NUMBER. + + * gdbinit.in: New file. + * aclocal.m4 (SIM_AC_OUTPUT): Build .gdbinit. + * Make-common.in (distclean): Delete .gdbinit. + (.gdbinit): Add rule for. + * configure: Regenerated to track ../common/aclocal.m4 changes. + + * Make-common.in (cgen-run.o): Add rule for. + +Wed Sep 3 10:08:21 1997 Andrew Cagney + + * sim-resume.c (sim_resume): Suspend/resume the simulator. + + * sim-events.c (sim_watch_valid): Compute total elapsed time from + both resumed and previous elapsed time. + (sim_events_init): Set initial_wallclock and current_wallclock to + zero. + (sim_events_install): Install sim_events_suspend and + sim_events_resume. + (sim_events_watch_clock): Allow for suspended simulator when + computing the time of the clock event. + + * sim-events.h (struct _sim_event): Add resume_wallclock, rename + initial_wallclock to elapsed_wallclock, set both to zero. + (sim_events_init, sim_events_uninstall): Delete prototypes. + + * sim-module.h (MODULE_SUSPEND_FN, MODULE_RESUME_FN): Define types. + + * sim-module.c(sim_module_resume, sim_module_suspend): New + functions. + +Wed Sep 3 10:08:21 1997 Andrew Cagney + + * sim-core.c (sim_core_map_attach): Clarify memory overlap error + message. + +Tue Sep 2 14:57:06 1997 Doug Evans + + * Makefile.in (TAGS): Add support for "/* TAGS: foo */" marker. + * Make-common.in (TAGS): Likewise. + * sim-n-bits.h: Add TAGS comments for all functions. + * sim-n-core.h: Likewise. + * sim-n-endian.h: Likewise. + +Mon Sep 1 10:50:11 1997 Andrew Cagney + + * sim-utils.c (sim_state_alloc): Set CPU backlinks, callback and + kind. + + * sim-base.h (sim_state_alloc): Add callback and kind arguments. + + * sim-base.h (INVALID_INSTRUCTION_ADDRESS): Add default + definition. + +Sat Aug 30 09:47:21 1997 Andrew Cagney + + * sim-fpu.c (DP_GARDMSB, ...): Make unsigned. + (DP_FRACHIGH, DP_FRACHIGH2, ..): Use MSMASK to avoid LL. + +Fri Aug 29 13:37:44 1997 Andrew Cagney + + * sim-core.c (sim_core_map_attach): Cast attach enum to int. + (sim_core_xor_read_buffer, sim_core_xor_write_buffer): Make + nr_transfered and nr_this_transfer unsigned. + + * sim-events.c (sim_events_tickn): N is signed, as limited to + MAXINT. + + * sim-n-endian.h (offset_N): Change size to unsigned. + + * callback.c (os_poll_quit): Add prototypes for kbhit and getkey. + +Fri Aug 29 10:10:53 1997 Andrew Cagney + + * sim-utils.c (sim_copy_argv): Delete, replaced by dupargv. + + * sim-options.c (sim_parse_args): Use dupargv. + +Thu Aug 28 10:36:34 1997 Doug Evans + + * sim-options.c (standard_option_handler): Use xstrdup, not strdup. + +Thu Aug 28 12:09:15 1997 Andrew Cagney + + * sim-base.h (STATE_ARCHITECTURE, STATE_TARGET): Add to simulator + base type. + + * sim-options.c (standard_options): Add --architecture=MACHINE and + --target=TARGET options. + (OPTION_ARCHITECTURE, OPTION_TARGET): Define. + (standard_option_handler): Handle architecture and target options. + (bfd.h): Include. + + * sim-utils.c (sim_analyze_program): Pass STATE_TARGET to + bfd_openr. + (sim_analyze_program): Set prog_bfd architecture from + STATE_ARCHITECTURE if known. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Aug 27 18:11:30 1997 Andrew Cagney + + * aclocal.m4 (enable-sim-warnings): Remove comment stating + that option does not apply to certain files. + +Wed Aug 27 15:13:04 1997 Andrew Cagney + + * sim-bits.h (LSBIT8, LSBIT16, LSBIT32, LSBIT64, LSBIT, MSBIT8, + MSBIT16, MSBIT32, MSBIT64, MSBIT): New macros - single bit as + offset from MSB/LSB. + + * sim-endian.h (A1_8, A2_8, A4_8, A1_4, A2_4, A1_2): New macro, + access address of sub word quantity of a hosts 16, 32, 64 bit word + type. + (V1_2, V1_4, V2_4, V1_8, V2_8, V4_8): Ditto for values. + (U8_1, U8_2, U8_4, U4_1, U4_2, U2_1): Ditto for set of values. + (V2_H1, V2_L1, V4_H2, V4_L2, V8_L4, V8_H4): Given N byte argument, + return N*2 byte value with argument in Hi/Lo word. Renamed from + V1_H2, V1_L2, V2_H4, V2_L4, V4_H8, V4_L8. + + * sim-alu.h (ALU32_HAD_OVERFLOW): Use 64 bit mask not 32bit. + (ALU16_HAD_CARRY, ALU32_HAD_CARRY, ALU16_HAD_OVERFLOW): Use MSBIT + so that bit offset is explicit. + +Wed Aug 27 11:55:35 1997 Andrew Cagney + + * sim-utils.c (sim_analyze_program): Add prog_name argument. + Update STATE_PROG_BFD when needed with a dup'd copy of the + program. + + * sim-config.c (sim_config): Delete ABFD argument, use + STATE_PROG_BFD directly. + +Tue Aug 26 12:55:26 1997 Andrew Cagney + + * run.c (main): Pass the open ABFD to sim_create_inferior. + + * nrun.c (main): Determine prog_bfd. Pass to sim_create_inferior + and sim_load. + (bfd.h): Include. + + * sim-hload.c (sim_load): New file. Implement generic sim_load for + hardware only simulator targets. + + * Make-common.in (sim-hload.o): Add rule. + +Wed Aug 27 09:51:42 1997 Andrew Cagney + + * sim-utils.c (sim_copy_argv): Rewrite to match malloc strategy + used by copyargv and freeargv. + + * sim-options.c (sim_parse_args): Save a copy of PROG-ARGS in + STATE_PROG_ARGV, not just a pointer. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 12:11:06 1997 Andrew Cagney + + * aclocal.m4 (sim-endian): Add second argument to + SIM_AC_OPTION_ENDIAN. First is hardwired endian, second is + default endian when not hardwired. + + * sim-config.h (WITH_DEFAULT_TARGET_BYTE_ORDER): New macro, if all + else failes value for target byte order. + + * sim-config.c (sim_config): Add abfd arguments. Set + STATE_PROG_BFD accordingly. Determine prefered_target_byte_order + from same. + (sim_config): Return SIM_RC, don't abort. + (bfd.h): Include. + + * run.c (main): Update call to sim_open - add ABFD argument. + * nrun.c (main): Add NULL ABFD argument. + +Thu Aug 14 12:48:57 1997 Doug Evans + + * callback.c (os_poll_quit): Make static. + Call sim_cb_eprintf, not p->eprintf. + (sim_cb_printf, sim_cb_eprintf): New functions. + * sim-utils.h (sim_cb_printf, sim_cb_eprintf): Declare. + + * sim-basics.h (zalloc,zfree,sim_add_commas,SIM_ELAPSED_TIME, + sim_elapsed_time_get,sim_elapsed_time_since): Move decls to + sim-utils.h. #include sim-utils.h. + * sim-utils.h: Above decls moved here. + (sim_analyze_program,sim_load_file): Use `struct _bfd', not `bfd'. + + * sim-watch.c (action_watchpoint): Fix thinkos. + +Thu Jul 24 08:48:05 1997 Stu Grossman (grossman@critters.cygnus.com) + + * sim-types.h: Fix defs of 64 bit data types for MSVC. + +Tue Jul 22 10:35:37 1997 Doug Evans + + * sim-n-core.h (sim_core_write_unaligned_N): Add missing break + to FORCED_ALIGNMENT case. + +Thu Jun 5 13:48:37 1997 Andrew Cagney + + * callback.c (target_to_host_open): Handle hosts with O_BINARY. + +Thu Jun 5 08:47:10 1997 Jeffrey A Law (law@cygnus.com) + + * Make-common.in (libsim.a): Fix typo. + +Thu Jun 5 13:48:37 1997 Andrew Cagney + + * nrun.c (main): Verify the structure returned before using it. + +Wed Jun 4 11:44:06 1997 Andrew Cagney + + * sim-config.h (WITH_ENGINE): Enable the sim-engine module by + default. + + * sim-engine.c (sim_engine_install): New function. Install the + engine init functions. + (sim_engine_init): [Re]initialize the simulator engine. + + * sim-module.c: Add sim_engine to list of modules that always + install. + +Tue Jun 3 04:52:04 1997 Andrew Cagney + + * sim-watch.c (schedule_watchpoint): Use sim_unschedule_watchpoint + to remove the old watchpoint, not delete_watchpoint. + (watch_option_handler): Action the correct watchpoint, not just + cycles. + +Wed May 28 14:47:41 1997 Andrew Cagney + + * sim-n-core.h (sim_core_write_aligned_N): For 8byte reads, output + both low and high word. + (sim_core_write_aligned_N): Ditto. + + * sim-trace.c (set_trace_options): Delete code explicitly setting + core->trace. + + * sim-options.c (sim_print_help): Call the list commands if not a + standalone simulator. + (sim_print_help): Advise that some options may not be applicable. + + * sim-trace.c (set_trace_options): Assume core present. + + * sim-events.c (sim_events_schedule_after_signal): Overflow signal + buffer when full not almost full. + +Tue May 27 14:32:00 1997 Andrew Cagney + + * sim-events.c (sim_events_process): Don't blat the event queue + when processing watchpoints. + + * sim-watch.h: Make arg unsigned long - stop sign extension. + + * sim-events.c (sim_watch_valid): rewrite so debugable. + + * sim-config.h (WITH_XOR_ENDIAN): Default to zero. + + * sim-watch.c (schedule_watchpoint): Add is_within option so that + inequality test is possible. + (handle_watchpoint): Re-pass is_within arg. + (watch_option_handler): When `!' prefix to pc-watchpoint arg pass + 0 to schedule_watchpoint's is_within arg. + (sim_watchpoint_init): Re-pass is_within arg. + + * sim-options.c (sim_print_help): Add is_command argument. Don't + include -- prefix when called from the command line interpreter. + + * sim-watch.c (schedule_watchpoint): Pass true is_within argument. + + * sim-events.c (sim_events_watch_sim): Add is_within argument, + zero indicates that the test should be reversed. + (sim_events_watch_core): Ditto. + (WATCH_CORE): Compare range against is_within. + (WATCH_SIM): Ditto. + +Tue May 27 12:48:03 1997 Andrew Cagney + + * sim-events.c (WATCH_CORE): Pass NULL cpu argument to + sim_core_read_buffer. Check nr-bytes transfered. + + * sim-core.h (sim_core_common): Define a new struct that contains + the common data. to sd and cpu structures. + * sim-core.c (sim_core_attach): Update. + (sim_core_init): Update. Remember to copy initialized data to each + cpu. + (sim_core_find_mapping): Ditto. + + * sim-core.c (sim_core_read_buffer): Add cpu argument. + (sim_core_write_buffer): Ditto. + + * sim-n-core.h (sim_core_read_unaligned_N): When mis-aligned + transfer use xor version of read buffer. + (sim_core_write_unaligned_N): Ditto for write. + + * sim-core.c (sim_core_xor_read_buffer): New function implement + xor-endian data read breaking transfer up into xor-endian sized + blocks. + (sim_core_xor_write_buffer): Ditto for write. + (reverse_n): Reverse order of arbitrary number of bytes in buffer + - needed for xor-endian transfers. + +Fri May 23 14:24:31 1997 Andrew Cagney + + * sim-inline.h: Review description. + + * sim-core.h, sim-core.c: Reduce number of functions being inlined + to just those involved in data transfers and configuration. + + * sim-xcat.h (XSTRING): New macro, map macro definition onto + string. + * sim-n-core.h (sim_core_read_aligned_N): Use. + (sim_core_read_unaligned_N): Ditto. + (sim_core_read_unaligned_N): Ditto.. + (sim_core_write_unaligned_N): Ditto. + + * sim-core.h: Add xor endian bitmap to main structure. * + + sim-n-core.h (sim_core_write_aligned_N): Add suport for xor + endian. + (sim_core_read_aligned_N): Ditto. + + * sim-core.c (sim_core_set_xor_endian): New function. + (sim_core_attach): Don't overwrite the per-cpu xor map when + cloning the global core. + +Fri May 23 10:53:13 1997 Andrew Cagney + + * sim-engine.h: Update below so that it is using an enumerated + type. + +Thu May 22 09:12:16 1997 Gavin Koch + + * sim-engine.c (sim_engine_restart): + * sim-resume.c (sim_resume): Change longjmp param/setjmp + return value used for simulator restart from 0 to 2. + +Wed May 21 08:47:30 1997 Andrew Cagney + + * cgen-scache.c (scache_option_handler): Add is_command arg. + + * sim-model.c (model_option_handler): Add is_command argument. + + * sim-profile.c (profile_option_handler): Add is_command arg. + + * sim-events.c (sim_watch_valid): Use ub64, lb64 when 64bit value + involved. + + * sim-module.c (sim_module_add_init_fn): Call init fn in the same + order that they are registered. + + * sim-options.h (OPTION_HANDLER): Add argument to differentiate + between option and command line processing. + + * sim-options.c: Include stdlib.h, ctype.h. + + * Make-common.in (sim-watch.o): Add rule. + (sim_main_headers): Assume sim-assert.h included. + (sim-*.o): Simplify make rule. + + * sim-module.c: Add sim_watch_install to module list. + +Tue May 20 14:15:23 1997 Andrew Cagney + + * sim-base.h (STATE_LOADED_P): New predicate. Set once everything + has been loaded. + + * sim-trace.c (trace_install): Check magic. Include sim-assert.h. + * sim-events.c (sim_events_install): Ditto. + * sim-core.c (sim_core_install): Ditto. + * sim-model.c (model_install): Ditto. + * sim-options.c (standard_install): Ditto. + * sim-profile.c (profile_install): Ditto. + * sim-reason.c (sim_stop_reason): Ditto. + * sim-run.c (sim_engine_run): Ditto. + * sim-utils.c (sim_analyze_program): Ditto. + + * sim-module.c (modules): Make profile_install and trace_install + optional. + + * sim-base.h (STATE_MEM_BASE): Define for flat memory systems. + + * sim-options.c (standard_option_handler): Set the byte order. + + * sim-events.c (sim_events_process): Allow multi tick processing. + (sim_events_tickn): New function - multi cycle tick. + + * sim-events.h (sim_events_tickn, sim_events_timewarp): Add + prototypes. Under development. + (sim_events): Replace processing with nr_ticks_to_process. + +Tue May 20 09:39:22 1997 Andrew Cagney + + * nrun.c (main): Pass callbacks to sim_open instead of using + sim_set_callbacks. + + * run.c (main): Ditto. + +Mon May 19 12:07:22 1997 Andrew Cagney + + * sim-events.c (sim_events_zalloc): Signal save memory allocator - + stop tk interrupting malloc calls. + (sim_events_zalloc): Converse. + + * Make-common.in (sim_main_headers): Add sim-events.h. + + * sim-events.c (sim_events_schedule_after_signal): Change return + type to void - signal events are strictly internal. + (sim_events_init): Allocate a finite buffer for signal events. + (sim_events_schedule_after_signal): Enter signal events into the + signal buffer. + + * sim-engine.c (sim_engine_halt): Check SIM_DESC magic. + (sim_engine_restart): Ditto. + (sim_engine_abort): Ditto. + * sim-stop.c (sim_stop): Ditto. + (control_c_simulation): Ditto. + * sim-resume.c (sim_resume): Ditto. + (has_stepped): Ditto. + * sim-abort.c (sim_engine_abort): Ditto. + + * sim-basics.h (transfer_type): New type. + + * sim-core.c (sim_core_signal): New function. Print core signal + information. + (sim_core_find_mapping): Add transfer argument. + + * sim-n-core.h (sim_core_{write,write}_unaligned_N): Call + SIM_CORE_SIGNAL if a recoverable abort. + * sim-core.c (sim_core_find_mapping): Ditto. + +Fri May 16 15:13:21 1997 Andrew Cagney + + * sim-core.c (sim_core_find_mapping): Replace calls to + sim_io_error to more resiliant sim_engine_abort. + + * sim-n-core.h (sim_core_read_unaligned_N): Ditto. + (sim_core_write_unaligned_N): Ditto. + +Tue May 13 13:50:06 1997 Andrew Cagney + + * sim-module.c: Add sim_events_install to list. + + * sim-events.c (sim_events_install, sim_events_uninstall): Clonse + from sim_core_*. + (sim_events_init): Now returns SIG_RC. + + * sim-run.c: New file. Generic sim_engine_run. + * sim-reason.c: New file. Generic sim_stop_reason. + * sim-stop.c: New file. Generic sim_stop. + * sim-resume.c: New file. Generic sim_resume. + + * Make-common.in (sim-engine.o): Add rule. + (sim-run.o, sim-reason.o, sim-stop.o, sim-resume.o): Ditto. + + * sim-engine.h, sim-engine.c: New file. Provide generic + implementation of sim_engine_halt, sim_engine_error. et.al. + + * sim-base.h (sim_state_base): Add member halt. + (sim-engine.h): Include. + + * sim-events.h (sim_event_handler): Always pass SIM_DESC to event + handlers. + * sim-events.c (sim_events_poll): Update event handler. + +Tue May 13 09:57:49 1997 Andrew Cagney + + * sim-events.h, sim-events.c (sim_events_watch_clock): New + function. + (sim_events_watch_sim): New function. + (sim_events_watch_core): New function. + (sim_watch_valid): New function. + (sim_events_preprocess): New function. + (sim_events_process): Process the watchpoints as well as the timer + queue. + (sim_events_tick): Check WORK_PENDING instead of the hold queue. + (sim_events_deschedule): Check all the queues when removing an + event. + (sim_events_init): Ditto for cleaning. + +Mon May 19 12:07:22 1997 Andrew Cagney + + * sim-fpu.c (is_ufpu_number): Comment out - currently unused. + +Mon May 19 11:23:03 1997 Andrew Cagney + + * callback.c (os_open): Type of arg flags is int. + +Fri May 16 22:26:43 1997 Michael Meissner + + * sim-fpu.c (sim_fpu_is_{eq,ne,lt,le,gt,ge}): Compare Infinities + just like normal numbers as per IEEE rules. + +Wed May 14 21:20:38 1997 Bob Manson + + * callback.c (os_close): Mark the descriptor as being + available if the close succeeded. + (os_open): Pass 0644 as the mode of the file being created. + +Thu May 15 10:58:52 1997 Andrew Cagney + + * sim-fpu.c (pack_fpu, unpack_fpu): New functions - decode a + float. + + * sim-inline.c (SIM_INLINE_C): Rename from _SIM_INLINE_C_. + * sim-lnline.h: Update. + + * sim-fpu.h, sim-fpu.c (sim_fpu_[iu]{32,64}to): New int2fp + conversion functions. + (sim_fpu_to{32,64}[iu]): New fp2int functions. + + * sim-fpu.h, sim-fpu.c (sim_fpu_is_{lt,le,eq,ne,ge,gt}): New fp + compare functions. Replacing. + (sim_fpu_cmp): This. Delete. + +Mon May 12 14:49:05 1997 Andrew Cagney + + * sim-core.c (sim_core_find_mapping): Call engine_error not + sim_io_error when possible. + +Mon May 12 08:55:07 1997 Andrew Cagney + + * sim-endian.h (V1_H2): Add macro's to insert a word into a + high/low double word. + + * sim-trace.h: Remove definition of attribute - defined in + sim_basics.h. + +Mon May 12 08:55:07 1997 Andrew Cagney + + * sim-options.h (struct OPTION): Add doc_opt as the documenting + name of the option - or family of options. + + * sim-options.c (sim_args_command): Match command `a-b c' with + option `--a-b-c' from option table. + +Thu May 8 12:40:07 1997 Andrew Cagney + + * sim-options.c (sim_print_help): For optional arguments, wrap + them in []. + + * sim-trace.c (set_trace_options): New function, handle optional + argument and multiple assignment. + (trace_option_handler): Update. + + * sim-trace.c (trace_option_handler): Trace branch and not fpu + when branch tracing selected. + +Wed May 7 15:19:58 1997 Andrew Cagney + + * sim-trace.c (trace_one_insn): Make a va-args function. + + * sim-trace.c (trace_vprintf): New function, va-arg version of + trace_printf. + +Tue May 6 16:38:16 1997 Doug Evans + + * sim-trace.c (trace_uninstall): Don't close a file twice. + * sim-profile.c (profile_uninstall): Likewise. + +Tue May 6 06:14:01 1997 Mike Meissner + + * sim-trace.c (toplevel): Include bfd.h. + (trace_options): Note that --trace-linenum also turns on + --trace-insn. Add --trace-{branch,semantics}. + (trace_option_handler): If --trace-linenum, also turn on + --trace-insn. Add --trace-branch support. If --trace-semantics, + turn on ALU, FPU, branch, and memory tracing. + (trace_one_insn): New function to trace an instruction. Support + --trace-linenum. + (OPTION_TRACE_*): Use an enum, rather than lots of defines. + + * sim-trace.h (TRACE_{SEMANTICS,BRANCH}_IDX): Add new macros. + (MAX_TRACE_VALUES): Use 32, not 12 by default. + (TRACE_branch): Add new mask. + (TRACE_*_P): Define all possible trace_p macros. + (trace_one_insn): Declare function. + +Mon May 5 14:08:34 1997 Mike Meissner + + * sim-trace.h (__attribute__): Define as nothing if not GNU C or + GNU C doesn't support __attributes__. + ({trace,debug}_printf): Add attribute's so -Wformat can check the + format strings. + +Mon May 5 11:16:12 1997 Andrew Cagney + + * sim-config.h (FORCED_ALIGNMENT): New alignment option - + addresses are masked forcing them to be correctly aligned. + (WITH_ALIGNMENT): Make NONSTRICT_ALIGNMENT the default. + * sim-config.c (config_alignment_to_a): Update. + + * sim-core.h (sim_cpu_core): New data type contains cpu specific + core data. + * sim-base.h (CPU_CORE): Add cpu specific core data to cpu base + type. + * sim-core.c (sim_core_attach): Add CPU argument. Ready for + processor specific core maps. + (sim_core_map_attach): Copy the core map data to each of the + processor specific core data structures. + * sim-core.c (sim_core_find_mapping): Update. + + * sim-n-core.h (sim_core_read_N, sim_core_write_N): Rename. + (sim_core_write_aligned_N, sim_core_write_aligned_N): New names. + (sim_core_write_unaligned_N, sim_core_write_unaligned_N): New + alternatives that handle unaligned addresses. + (sim_core_{read,write}_{,un}aligned_N): Drop SIM_DESC arg, replace + with just CPU arg. + * cgen-utils.c (sim_disassemble_insn): Update. + +Mon May 5 13:19:16 1997 Andrew Cagney + + * sim-trace.h (TRACE_FPU_IDX): Add Floating-point specific + tracing. + + * sim-fpu.h, sim-fpu.c: New files - prototype for generic target + fpu support. + + * sim-inline.h, sim-inline.c: Add support for SIM_FPU. + +Fri May 2 17:59:42 1997 Andrew Cagney + + * sim-core.c (sim_core_map_to_str): New function ascii equivalent + to map type. + + * sim-n-core.h (sim_core_read_N, sim_core_write_N): Use in trace + statement. + +Fri May 2 17:28:02 1997 Andrew Cagney + + * cgen-trace.c: Prepend additional trace_printf argument. + + * cgen-utils.c (sim_disassemble_insn): Add additional core + arguments. + +Fri May 2 11:40:23 1997 Andrew Cagney + + * nrun.c (main): Catch/report errorenous simulator states. + + * sim-module.c: #include "libiberty.h" so that xmalloc is defined. + * sim-trace.c: #include string.h/strings.h so that memset is + defined. + * sim-utils.c: Ditto. + * sim-profile.c: Ditto. And stdlib.h. + (print_bar): Only define when used by instruction or memory profiler. + + * sim-options.c (standard_option_handler): Make ul more local. + + * sim-load.c (sim_load_file): Make the name constant. + (sim_load_file): Passify gcc. + + * sim-utils.h: New file, pre-declare utilites in corresponding .c + file. + * sim-utils.c, sim-load.c: Include sim-utils.h. + + * sim-base.h (sim_cpu): Pre define here so available to all. + + * sim-core.h (DECLARE_SIM_CORE_WRITE_N, DECLARE_SIM_CORE_READ_N): + Restore the sim_cpu and instruction_address arguments so that full + information is available to the abort function. + * sim-core.c (sim_core_find_mapping, sim_core_write_buffer): Ditto. + * sim-n-core.h (sim_core_write_N, sim_core_read_N): Update. + + * sim-trace.h, sim-trace.c (trace_option_handler): Add interim + tracing support for sim-events and sim-core. + (trace_option_handler): Convert #if to if where possible so always + compiled/checked by C compiler. + * sim-n-core.h (sim_core_write_N, sim_core_read_N): Update. + + * sim-base.h: Adjust comment documenting how to define the cpu + structure. + (sim_state_base): Add sim_core and sim_events to simulator base + object. + + * sim-trace.h, sim-trace.c (trace_printf): Add SIM_DESC argument. + * sim-core.c (sim_core_init, sim_core_attach, + sim_core_find_mapping): Update. + * sim-events.c (ETRACE, sim_events_init, sim_events_time, + update_time_from_event, insert_sim_event, + sim_events_schedule_after_signal, sim_events_deschedule, + sim_events_tick): Ditto. + + * sim-basics.h (sim-module.h, sim-trace.h, sim-profile.h, + sim-model.h): Move #includes from here. + * sim-base.h: To here. + (sim-core.h, sim-events.h, sim-io.h): Include also + +Wed Apr 30 15:37:54 1997 Andrew Cagney + + * callback.c (default_callback): Missing initialisers. + +Thu May 1 10:40:47 1997 Doug Evans + + * sim-utils.c (sim_add_commas): New function. + * sim-basics.h (sim_add_commas): Add prototype. + * cgen-scache.c (scache_print_profile): Print commas in numbers. + * sim-profile.c (COMMAS): New macro. + (print_*): Use it to print commas in numbers. + + * configure: Regenerated. + + * cgen-sim.h (sim_signal_type): Add SIM_SIGINT. + (cgen_state): New member run_fast_p. + (cgen_init): Add prototype. + (sim_disassemble_insn): New arg `cpu'. + * cgen-trace.c (trace_insn): Update call to sim_disassemble_insn. + * cgen-utils.c (cgen_init): New function. + (sim_disassemble_insn): New arg `cpu'. Rewrite fetching of insn. + * genmloop.sh: Call engine_halt if loop exits. + + * Makefile.in (sim-options_h): Define. + (sim-{module,options,trace,profile,utils}.o): Clean up dependencies. + (sim-model.o): Add new rule. + (cgen-{scache,trace,utils}.o): Add new rules. + * aclocal.m4 (SIM_AC_OPTION_{SCACHE,DEFAULT_MODEL}): Add. + * cgen-scache.c (scache_print_profile): Change `sd' arg to `cpu'. + Indent output by 2 spaces. + * cgen-scache.h (scache_print_profile): Update. + * cgen-trace.c (trace_insn_fini): Indent output by 2 spaces. + Use trace_printf, not fprintf. + (trace_extract): Use trace_printf, not cgen_trace_printf. + * genmloop.sh (!FAST case): Increment `insn_count'. + * sim-base.h (sim_state_base): Only include scache_size if WITH_SCACHE. + (sim_cpu_base): Rename member `sd' to `state' to be consistent with + access macro's name. + * sim-core.c (sim_core_init): Use EXTERN_SIM_CORE to define it. + Change return type to SIM_RC. + (sim_core_{install,uninstall}): New functions. + * sim-core.h (sim_core_{install,uninstall}): Declare. + (sim_core_init): Use EXTERN_SIM_CORE to define it. + Change return type to SIM_RC. + * sim-model.h (models,machs,model_install): Declare. + * sim-module.c (modules): Add scache_install, model_install. + (sim_post_argv_init): Set cpu->state backlinks. + * sim-options.c (standard_options): Delete --simcache-size,--max-insns. + (standard_option_handler): Likewise. + * sim-profile.c (PROFILE_{HISTOGRAM,LABEL}_WIDTH): Move to + sim-profile.h. + (*): Assume ANSI C. + (profile_options): Delete --profile-simcache. + (profile_option_handler): Likewise. + (profile_print_insn): Change `sd' arg to `cpu'. Indent output 2 + spaces. + (profile_print_{memory,model}): Likewise. + (profile_print_simcache): Delete. + (profile_print_speed): New function. + (profile_print): Rewrite. + * sim-profile.h (PROFILE_scache): Renamed from PROFILE_simcache. + (WITH_PROFILE_SCACHE_P): Renamed from WITH_PROFILE_SIMCACHE_P. + (PROFILE_DATA): Delete members simcache_{hits,misses}. + (PROFILE_COUNT_SIMCACHE_{HIT,MISS}): Delete. + (PROFILE_{CALLBACK,CPU_CALLBACK}): New types. + (profile_print): Update prototype. + +Wed Apr 30 11:34:14 1997 Doug Evans + + * cgen-scache.[ch], cgen-sim.h: New files. + * cgen-trace.[ch], cgen-types.h, cgen-utils.c, genmloop.sh: New files. + * sim-model.c: New file. + + * Make-common.in (clean targets): Undo patch of Apr. 22. + +Fri Apr 25 15:28:32 1997 Mike Meissner + + * sim-n-bits.h (signed): If we have a standard compiler, undef + signed, so that signedN is defined correctly. + +Thu Apr 24 00:00:07 1997 Doug Evans + + * sim-module.h, sim-model.h, sim-profile.h: New files. + * sim-module.c, sim-profile.c: New files. + * Make-common.in (SIM_PROFILE): Define + (CONFIG_CFLAGS): Add $(SIM_PROFILE). + (sim_main_headers): Add sim-module.h, sim-model.h, sim-profile.h. + (sim_module.o,sim-profile.o): Add rules for. + * aclocal.m4 (--enable-sim-trace): Allow symbolic arguments. + (--enable-sim-profile): Add. + * configure: Regenerated. + * sim-base.h (sim_state_base): New members init_list, uninstall_list, + model. Move trace and profile support to sim-{trace,profile}.h. + New members trace_data, profile_data. + * sim-basics.h: #include sim-module.h, sim-model.h, sim-profile.h. + * sim-config.h: Provide default definition of WITH_PROFILE. + (WITH_TRACE): Change default to -1. + (MAX_NR_PROCESSORS): Always define. + * sim-options.c: Move trace and profile support to + sim-{trace,profile}.h. + (sim_pre_argv_init): Moved to sim-model.c. + (standard_install): New function. + * sim-options.h (sim_pre_argv_init): Move decl to sim-model.c. + (standard_install): Declare. + * sim-trace.c: Tracing option handling moved here from sim-options.c. + (trace_install, trace_uninstall): New functions. + (trace_printf): Update reference to TRACE_FILE. + * sim-trace.h (TRACE_FOO_IDX): Moved here from sim-base.h. + (TRACE_foo): Bit masks for symbolic arguments to --enable-sim-trace. + (WITH_TRACE_FOO_P): Define. + (trace_install): Declare. + (TRACE_DATA): New struct. + +Wed Apr 23 17:23:15 1997 Doug Evans + + * run.c: Undo last exec_bfd patch. + (main): Only pass -E ifdef SIM_HAVE_BIENDIAN. + +Wed Apr 23 17:54:27 1997 Mike Meissner + + * run.c (exec_bfd): Add back in. + (main): Set exec_bfd. + +Tue Apr 22 14:43:46 1997 Doug Evans + + * sim-load.c (sim_load_file): #include for NULL. + +Wed Apr 23 02:55:54 1997 Andrew Cagney + + * sim-events.c (insert_sim_event): Call sim_io_error instead of + less well defined engine_error. + * sim-core.c: Ditto. + +Tue Apr 22 08:48:16 1997 Stu Grossman (grossman@critters.cygnus.com) + + * Make-common.in: Change clean targets to use :: so that other + Makefiles can have their own clean targets. + * sim-load.c (xprintf eprintf): Use ANSI_PROTOTYPES instead of + __STDC__ to control use of stdarg vs. varargs syntax. Some + systems can't use __STDC__, but require stdarg. + +Fri Apr 18 11:14:43 1997 Doug Evans + + * sim-options.c (standard_options): Add --endian. + (standard_option_handler): Likewise. + + * nrun.c: #include . + (main, cntrl_c): Wrap calls to sim_resume in a SIGINT + handler that calls sim_stop (). + +Fri Apr 18 13:11:36 1997 Andrew Cagney + + * run.c (main, cntrl_c): Wrap calls to sim_resume in a SIGINT + handler that calls sim_stop (). Simulators may still be + establishing their own handler. + + * sim-events.c (sim_events_poll): Rename from + sim_events_at_large_int. Poll IO. + + * sim-io.c (sim_io_poll_quit): New function - pass on a polling + request. + + * callback.c (os_poll_quit): New function poll for quit signal + where needed. + (default_callback): Include magic number. + +Thu Apr 17 02:25:11 1997 Doug Evans + + * aclocal.m4: Check for headers time.h, sys/time.h, sys/resource.h. + Check for functions getrusage, time. + * sim-basics.h (SIM_ELAPSED_TIME): New typedef. + (sim_elapsed_time_get, sim_elapsed_time_since): Add prototypes. + * sim-utils.c: #include time.h, sys/time.h, sys/resource.h if able. + (sim_elapsed_time_get, sim_elapsed_time_since): New functions. + + * sim-utils.c (sim_copy_argv, sim_analyze_program): New functions. + + * sim-options.c, sim-options.h: New files. + * sim-config.h (WITH_DEBUG): Provide default value of zero. + * Make-common.in (nrun.o): Add rules for. + * nrun.c: New file. + + * run.c (main): Check return value of sim_open. + + * Make-common.in (sim-options.o, sim-load.o, sim-trace.o): Add rules. + (sim_main_headers): Add sim-trace.h. + * run.c (exec_bfd, target_byte_order): Delete. + (main): Pass -E to sim_open. Delete code to load sections, + call sim_load instead. Check return code of sim_create_inferior. + * sim-base.h (CURRENT_STATE): Define. + (sim_state_base): Make typedef. New members options, prog_argv, + prog_bfd, text_{section,start,end}, start_addr, simcache_size, + mem_size, memory [+ corresponding access macros]. + (sim_cpu_base): New typedef. + * sim-trace.h: New file. + * sim-trace.c: New file. + * sim-basics.h: #include it. + * sim-load.c: New file. + +Tue Apr 15 15:10:13 1997 Ian Lance Taylor + + * Make-common.in (INSTALL): Set to @INSTALL@. + (INSTALL_XFORM, INSTALL_XFORM1): Remove. + (install-common): Depend upon installdirs. Use + $(program_transform_name) directly, rather than using + $(INSTALL_XFORM). + (installdirs): New target. + * Makefile.in (INSTALL): Set to @INSTALL@. + (INSTALL_XFORM, INSTALL_XFORM1): Remove. + (install-man): Depend upon installdirs. Use + $(program_transform_name) directly, rather than using + $(INSTALL_XFORM). + (installdirs): New target. + +Tue Apr 15 15:08:12 1997 Andrew Cagney + + * sim-assert.h (SIM_ASSERT, ASSERT): Allow these macros to + be overriden. + +Wed Apr 9 16:06:44 1997 Andrew Cagney + + * sim-basics.h: Only bring in config.h and tconfig.h if + HAVE_CONFIG_H. + +Mon Apr 7 11:39:45 1997 Andrew Cagney + + * sim-config.h (WITH_TARGET_WORD_MSB): New Macro. Define the bit + numbering convention of the target. + * sim-config.c (print_sim_config): Print WITH_TARGET_WORD_BITSIZE + and WITH_TARGET_WORD_MSB. + (sim_config): When possible, check for consistency with bitsize + and msb. + + * sim-bits.h: Allow MSB to be other than zero. + * sim-bits.c: Ditto. + * sim-n-bits.h: Ditto. + + * sim-bits.h (MSMASK*): New macros - converce to LSMASK*. + * sim-n-bits.h (MSMASKEDn): Ditto. + +Mon Apr 14 16:29:21 1997 Ian Lance Taylor + + * Makefile.in (INSTALL): Change install.sh to install-sh. + +Mon Apr 7 10:46:38 1997 Doug Evans + + * sim-base.h (sim_state_base): Move `magic' to end of struct. + +Mon Apr 7 15:53:21 1997 Andrew Cagney + + * run.c (main): Check that a program to run was specified. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * aclocal.m4 (AC_TYPE_SIGNAL): Add check. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * sim-endian.h: Move host {LITTLE,BIG}_ENDIAN support from here, + * sim-config.h: To here. + + * Make-common.in (SIM_EXTRA_DEPS): New config var. + (sim_main_headers): Define. + (sim-*.o): Depend on $(SIM_EXTRA_DEPS). + (BUILT_SRC_FROM_COMMON): Move here from ../d30v/Makefile.in. + (clean): Use it. + (sim-utils.o): Add rule for. + * sim-utils.o: New file. + * sim-basics.h: #include sim-base.h. + (zalloc): Make argument unsigned long. + * sim-base.h: New file. + * sim-inline.h (SIM_IO support): Delete. + * sim-io.h: Delete inline support. + * sim-io.c: Likewise. sim-state.h renamed to sim-main.h. + * sim-config.c: sim-state.h renamed to sim-main.h. + * sim-core.c: Likewise. + * sim-events.c: Likewise. + + * run.c (main): Pass SIM_OPEN_STANDALONE to sim_open. + + * aclocal.m4: Check for stdlib.h, string.h, strings.h, unistd.h. + (sim-debug): Allow arguments. Define WITH_DEBUG in addition to + -DDEBUG. + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 11:08:11 1997 Andrew Cagney + + * sim-config.h (WITH_ALIGNMENT, WITH_FLOATING_POINT, + WITH_XOR_ENDIAN, WITH_SMP, WITH_RESERVED_BITS): Assume that these + are defined by the configure. + + * aclocal.m4 (sim-stdio): Add option stdio from ../ppc configure. + + * aclocal.m4 (floating-point, xor-endian, alignment, smp, + reserved-bits): Always define. + + * sim-config.h, sim-config.c (sim_config): New function - and new + file - co-ordinate the setting/checking of the common simulator + configuration options. + + * Make-common.in (sim-config.o): Add rule. + +Fri Mar 28 15:32:00 1997 Mike Meissner + + * callback.c (os_{,e}vprintf_filtered): Change stdarg type to + va_list from void *, since va_list might not be a pointer type. + +Mon Mar 24 15:27:12 1997 Andrew Cagney + + * sim-n-endian.h (offset_N): Correct assertion - word and sub word + in wrong order. + (offset_N): Correct computation of LE offset. + + * sim-io.c (sim_io_error): Include a new line when reporting + errors. + + * sim-assert.h (SIM_FILTER_PATH): Out by one when locating last + `/'. + +Thu Mar 20 22:31:06 1997 Jeffrey A Law (law@cygnus.com) + + * run.c: Include alloca-conf.h. + + * callback.c (os_evprintf_filtered): Fix typo. + +Fri Mar 21 13:36:20 1997 Andrew Cagney + + * run.c (string.h, strings.h, stdlib.h): Include. + + * sim-events.c (sim_events_tick): Recent cleanup failed to return + 0 when nothing pending. + + * run.c (sim_size, sim_trace): Plicate GCC - these two functions + will soon be going away. + (getopt): Plicate GCC. + + * sim-endian.c (sim-io.h): Plicate GCC. + * sim-bits.c (sim-io.h): Ditto. + * sim-n-bits.h (ROTn): Ditto. + + * sim-io.c (sim_io_error): Correct check for NULL. + + * sim-assert.h (SIM_FILTER_PATH): Separate out the code filtering + the __FILE__. + * sim-events.c: Use SIM_FILTER_PATH to filter out the filename + path. + +Wed Mar 19 01:12:06 1997 Andrew Cagney + + * aclocal.m4 (SIM_AC_OPTION_*: Move so that they are outside of + SIM_AC_COMMON - SIM_AC_COMMON was gobling arguments. + +Tue Mar 18 20:48:12 1997 Andrew Cagney + + * sim-alu.h: Include sim-xcat.h. + +Tue Mar 18 13:58:18 1997 Andrew Cagney + + * Make-common.in (sim-bits.c, sim-core.c, sim-endian.c, + sim-events.c, sim-inline.c, sim-io.c): Define rules for building + these. + + * sim-events.c (sim_events_at_large_int): New function. Just + schedules an event every large-int ticks. + (sim_events_init): Call. + (sim_events_tick, sim_events_process): Move async handing to + sim_events_process. Move timer decrement so that it occures after + events have been processed. + + * sim-basics.h (struct _engine): Remove declaration. + + * sim-events.h, sim-events.c: Rename type to sim_events. Prefix + everything with same. Rename global struct to SIM_DESC. + * sim-core.h, sim-core.c, sim-n-core.c: Ditto for sim_core. + * sim-io.h, sim-io.c: Ditto. + + * sim-assert.h: New file. Optional assertion checking macros. + * sim-io.c (sim_io_error): Make just this function tolerant to + null pointers. + + * sim-xcat.h: New file. Define concatenate macros. + * sim-basics.h (XCONCAT*): Move to sim-xcat.h. + * sim-n-core.h, sim-n-bits.h, sim-n-endian.h: Explicitly include + concat macros. + + +Tue Mar 18 12:44:55 1997 Andrew Cagney + + * sim-bits.h (LSMASK): New macro. Create mask of LS bits. + +Mon Mar 17 18:10:05 1997 Andrew Cagney + + * sim-inline.h: Add definitions for sim-types. + (ALL_BY_MODULE): New macro, encapsulate full inlining by the + module. + +Mon Mar 17 15:38:27 1997 Andrew Cagney + + * sim-events.h: Remove defunct reference to callback struct. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Mon Mar 17 15:04:47 1997 Andrew Cagney + + * Make-common.in (CSEARCH): Do not include the gdb directory in + the search path. + +Mon Mar 17 13:16:26 1997 Andrew Cagney + + * Make-common.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_INLINE, + SIM_WARNING): Drop, requiring the simulator specific Makefile.in + to explicitly incorporate these. + + * aclocal.m4 (--enable-sim-alignment); New option. Strongly + specify the alignment restrictions of the target architecture - + without this option all alignment restrictions are accomodated. + (--enable-sim-assert): New option. Conditionally compile in + assertion statements. + (--enable-sim-float): New option. Strongly specify the target's + floating point support. + (--enable-sim-hardware): New option. Specify the hardware devices + included in the simulation. + (--enable-sim-packages): New option. Specify the hardware + packages included in the simulation. + (--enable-sim-regparm): New option. Specify that parameters be + passed in registers instead of on the stack. + (--enable-sim-reserved-bits): New option. Specify that reserved + bits within an instruction are are correctly set. + (--enable-sim-smp): New option. Specify the level of SMP support + to be included in the simulator. + (--enable-sim-stdcall): New option. Specify an alternative + function call convention. + (--enable-sim-xor-endian): New option. Configure xor-endian + support used by some targets to implement bi-endian support. + +Fri Mar 14 19:51:21 1997 Andrew Cagney + + * aclocal.m4 (--enable-sim-hostendian): New option. Allow the + host endianness to be overridden. + (--enable-sim-endian): Allow the target platform's byte order + to be overridden. + (--enable-sim-inline): Control the inlining of common components. + (--enable-sim-bswap): For compatibility, also define WITH_BSWAP. + (--enable-sim-warnings): Enable additional GCC compiler checks. + * Make-common.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_INLINE, + SIM_WARNINGS): Add. + + * sim-n-core.h, sim-n-bits.h, sim-n-endian.h: Rename from + sim-*-n.h so that the names are uniq on dos machines + * sim-core.c, sim-bits.c, sim-endian.c: Update. + +Thu Mar 13 12:32:42 1997 Doug Evans + + * run.c: #include "libiberty.h". + (main): New locals sd,no_args,sim_argv. + Run buildargv on -a option. Pass argv to sim_open, argv[0] + is program name. Update call to sim_set_callbacks. + Record result of sim_open, pass to other sim_foo routines. + +Thu Mar 13 10:24:05 1997 Michael Meissner + + * callback.c (os_printf_filtered): Do not call exit(1) or print a + final newline. + +Thu Mar 6 15:50:28 1997 Andrew Cagney + + * callback.c: Add os_flush_stdout and vprintf_filtered callbacks. + Route stdout through buffered IO. + + * callback.c: Add os_flush_stderr, os_write_stderr, + os_evprintf_filtered functions to route error output through + stderr. + + * sim-io.h, sim-io.c (sim_io_flush_stderr, sim_io_flush_stdout): + Correct return type - should be void. + +Fri Mar 7 20:14:37 1997 Andrew Cagney + + * sim-basics.h: Clean up. Many macro's moved to sim-inline.h. + + * sim-config.h: Ditto. For some options - eg WITH_DEVICES - do + not provide a default value as undefined indicates disable code. + +Thu Mar 6 15:50:28 1997 Andrew Cagney + + * sim-core.h, sim-core-n.h, sim-core.c: Borrow code from ppc + directory. + * sim-events.h, sim-events.c: Ditto. + * sim-io.h, sim-io.c: Ditto. + +Tue Mar 4 09:35:56 1997 Andrew Cagney + + * sim-alu.h (ALU_SUB_CA, ALU*_SUB_CA): New alu operation. + + * sim-bits.h, sim-bits-n.h, sim-bits.c (LSMASKED*): New macro's + extract the tail or least signifiant bits from an integer of the + specified size. + + * sim-bits.h, sim-bits.c: Clean up conditionally compiled #if + WITH_TARGET_BITSIZE so that the compilation will fail when an + unsupported bitsize value is defined. + + (INSERTED*): Convert to functions. + (EXTRACTED*): Ditto. + + (SIGN_EXTEND, SEXT): Change to more terse name. + +Tue Mar 4 09:35:56 1997 Andrew Cagney + + * sim-inline.h: Allow explicit control over which .c files will be + included by their header. + + * sim-inline.h: Allow explicit control over which .c files use the + alternative - REGPARM - parameter passing mechanism. + + * sim-inline.h, sim-inline.c: Don't attempt to include any of + icache.c, idecode.c, semantics.c or support.c. Those names are + not generally applicable. + +Thu Feb 27 10:17:23 1997 Andrew Cagney + + * sim-bits.c, sim-bits-n.h (new): Split sim-bits.c into two parts + in a fashion similar to sim-endian-n. + + * sim-endian.h: (H_word, L_word, AL_*, VL_*): Extend to include + both value and address macro's. + +Tue Feb 25 18:51:57 1997 Andrew Cagney + + * sim-alu.h (ALU16_BEGIN, ALU16_SET, ...): Fill in. + + * sim-endian.h (L_word, H_word): Replace MS2W_4, LS2W_4 with more + generic L_word, H_word macro's. + +Thu Feb 20 18:36:55 1997 Andrew Cagney + + * sim-basics.h: Borrow code from ppc directory. + * sim-bits.c: Ditto. + * sim-bits.h: Ditto. + * sim-config.h: Ditto. + * sim-endian-n.h: Ditto. + * sim-endian.c: Ditto. + * sim-endian.h: Ditto. + * sim-inline.c: Ditto. + * sim-inline.h: Ditto. + * sim-types.h: Ditto. + +Wed Feb 19 12:40:50 1997 Andrew Cagney + + * sim-alu.h (ALU_SET16, ALU_SET32, ALU_SET64, etc): Make available + all the ALU size alternatives and then auto-configure a default. + + * sim-alu.h: Copy ppc/idecode_expression.h. + +Mon Feb 17 10:44:18 1997 Andrew Cagney + + * bits.h, bits.c (SIGN_EXTEND32, SIGN_EXTEND64): New functions, + sign extend a bit within a value. + + * sim-endian.h, sim-endian-n.h (offset_N): New functions - return + a pointer into the middle of a host word. + * sim-endian.h (MS2W_4, LS2W_4): Use this function. + +Tue Feb 11 13:46:49 1997 Michael Meissner + + * callback.c: If HAVE_CONFIG_H is defined, include config.h from + autoconf. If HAVE_UNISTD_H is defined, include unistd.h to get + appropriate definitions of read, write, etc. Add prototype for + system. + +Tue Feb 4 13:24:44 1997 Doug Evans + + * Makefile.in (libcommon.a): Delete. + (callback.o,targ-map.o): Delete, moved to Make-common.in. + (gentmap,targ-vals.h,targ-map.c): Likewise. + (run-autoconf): Delete. + * aclocal.m4 (SIM_AC_OUTPUT): Redo creation of Makefile. + (common makefile fragment): Moved back into ... + * Make-common.in: Resurrect. + * configure.in (AC_LINK_FILES): Delete, unnecessary now. + * configure: Regenerated. + +Fri Jan 31 07:16:49 1997 Doug Evans + + * aclocal.m4 (SIM_AC_COMMON): Move COMMON_MAKEFILE_FRAG from here. + (SIM_AC_OUTPUT): To here. + +Fri Jan 24 10:37:17 1997 Stu Grossman (grossman@critters.cygnus.com) + + * aclocal.m4 (COMMON_MAKEFILE_FRAG): Quote a couple of $'s in + comments and single quotes. Fixes a problem found on hpux. + +Thu Jan 23 13:35:03 1997 Stu Grossman (grossman@critters.cygnus.com) + + * aclocal.m4: Remove Make-common.in from dependencies. + * (distclean): Remove targ-vals.def. + + * aclocal.m4 (SIM_AC_COMMON): Move contents of Make-common.in + into here. Makes insertion into makefiles easier. Also, change + the way that callback.o, gentmap, targ-vals.h, targ-map.c, + targ-map.o, and run are built. They are now built in the + individual simulator directories, taking sources from ../common as + necessary. This replaces the merging of libcommon.a into + linsim.a, which was problematic for the WinGDB build process. + * run.c: Include config.h from . instead of ../common. + * Make-common.in: Remove. It's no longer necessary. + +Mon Dec 16 15:02:33 1996 Ian Lance Taylor + + * Make-common.in (ALL_CLAGS): Put CFLAGS at the end. + (.c.o): Put $(ALL_CFLAGS) before the file being compiled. + +Wed Dec 11 11:30:58 1996 Jim Wilson + + * run.c (main): Set target_byte_order before call to sim_open. + +Sun Dec 8 18:22:06 1996 Doug Evans + + * callback.c: #include + (os_error): New function. + (default_callback): Add os_error. + +Mon Nov 25 19:44:35 1996 Doug Evans + + * Make-common.in (Makefile): Set CONFIG_HEADERS="". + * aclocal.m4: Mark the fact that --enable-sim-bswap isn't host + specific. + (SIM_AC_OUTPUT): Don't build Makefile if CONFIG_FILES="". + +Wed Nov 20 01:11:04 1996 Doug Evans + + * run.c: #include ../common/config.h, tconfig.h. + (myname): New static global. + (main): Recognize new options -a, -c. Also recognize -h if h8/300. + Only process -c ifdef SIM_HAVE_SIMCACHE. + Only process -p/-s ifdef SIM_HAVE_PROFILE. + Parse program name from argv[0] and use in error messages. + Pass sim_args to sim_open. Pass prog_args to sim_create_inferior. + Add support for incomplete h8/300 termination indicators. + (usage): Make more verbose. + * aclocal.m4,config.in,tconfig.in,configure.in,configure: New files. + * Makefile.in,Make-common.in,callback.c: New files. + * nltvals.def,gentmap.c,gentvals.sh: New files. + +Tue Nov 12 13:34:00 1996 Dawn Perchik + + * run.c: Include stdarg.h if __STDC__. + +Tue Oct 15 11:16:31 1996 Jeffrey A Law (law@cygnus.com) + + * run.c (main): Don't print out anything if the signal + number is zero (ie no signal). + +Tue Oct 15 11:20:44 1996 Michael Meissner + + * run.c (main): Print out if the program raised a signal. + +Wed Sep 18 09:52:14 1996 Michael Meissner + + * run.c (exec_bfd): Rename from sim_bfd, to use the gdb name. + (main): Ditto. + +Tue Sep 17 11:04:50 1996 James G. Smith + + * run.c (main): Explicitly cast malloc() parameter. + +Thu Sep 12 11:27:21 1996 Michael Meissner + + * run.c (sim_bfd): New global to hold the bfd pointer for the + executable. + (main): Initialize sim_bfd. + +Fri Dec 15 16:27:49 1995 Ian Lance Taylor + + * run.c (main): Use new bfd_big_endian macro. + +Wed Nov 8 15:49:49 1995 James G. Smith + + * run.c (main): Removed SH specific comments, so source is + generic. Also updated to only load relevant sections. Moved + sim_open() to after callback attach (to match GDB). + + * run.1: Removed SH specific comments. + +Sat Oct 21 12:31:01 1995 Jim Wilson + + * run.c (main): Always return sigrc at end. + +Tue Oct 10 12:03:13 1995 J.T. Conklin + + * run.c (main): Print error diagnostic and exit if bfd_openr() or + bfd_check_format() fails. + +Thu Sep 28 15:40:36 1995 steve chamberlain + + * run.c, run.1: From sh directory. diff --git a/external/gpl3/gdb/dist/sim/common/Make-common.in b/external/gpl3/gdb/dist/sim/common/Make-common.in new file mode 100644 index 000000000000..351f4a078e95 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/Make-common.in @@ -0,0 +1,765 @@ +# Makefile fragment for common parts of all simulators. +# Copyright 1997, 1998, 1999, 2000, 2001, 2004, 2005, 2007, 2008, 2009, 2010, +# 2011 Free Software Foundation, Inc. +# Contributed by Cygnus Support. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# This Makefile fragment consists of two separate parts. +# They are merged into the final Makefile at points denoted by +# "## COMMON_PRE_CONFIG_FRAG" and "## COMMON_POST_CONFIG_FRAG". +# +# The target Makefile should look like: +# +#># Copyright blah blah +#> +#>## COMMON_PRE_CONFIG_FRAG +#> +#># Any overrides necessary for the SIM_FOO config vars. +#>SIM_FOO = ... +#> +#>## COMMON_POST_CONFIG_FRAG +#> +#># Rules to build target specific .o's. + +## COMMON_PRE_CONFIG_FRAG + +VPATH = @srcdir@ +srcdir = @srcdir@ +srccom = $(srcdir)/../common +srcroot = $(srcdir)/../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +bindir = @bindir@ + +libdir = @libdir@ +tooldir = $(libdir)/$(target_alias) + +datadir = @datadir@ +datarootdir = @datarootdir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +infodir = @infodir@ +includedir = @includedir@ + +# This can be referenced by the gettext configuration code. +top_builddir = .. + +EXEEXT = @EXEEXT@ +SHELL = @SHELL@ + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +CC = @CC@ +CC_FOR_BUILD = @CC_FOR_BUILD@ +CFLAGS = @CFLAGS@ +SIM_BSWAP = @sim_bswap@ +SIM_CFLAGS = @sim_cflags@ +SIM_DEBUG = @sim_debug@ +SIM_TRACE = @sim_trace@ +SIM_PROFILE = @sim_profile@ + +SIM_ASSERT = @sim_assert@ +SIM_ALIGNMENT = @sim_alignment@ +SIM_BITSIZE = @sim_bitsize@ +SIM_DEFAULT_MODEL = @sim_default_model@ +SIM_ENDIAN = @sim_endian@ +SIM_ENVIRONMENT = @sim_environment@ +SIM_FLOAT = @sim_float@ +SIM_HW_CFLAGS = @sim_hw_cflags@ +SIM_HW_OBJS = @sim_hw_objs@ +SIM_HW = @sim_hw@ +SIM_HOSTENDIAN = @sim_hostendian@ +SIM_INLINE = @sim_inline@ +SIM_PACKAGES = @sim_packages@ +SIM_REGPARM = @sim_regparm@ +SIM_RESERVED_BITS = @sim_reserved_bits@ +SIM_SCACHE = @sim_scache@ +SIM_SMP = @sim_smp@ +SIM_STDCALL = @sim_stdcall@ +SIM_XOR_ENDIAN = @sim_xor_endian@ +WARN_CFLAGS = @WARN_CFLAGS@ +WERROR_CFLAGS = @WERROR_CFLAGS@ +SIM_WARN_CFLAGS = $(WARN_CFLAGS) +SIM_WERROR_CFLAGS = $(WERROR_CFLAGS) + +HDEFINES = @HDEFINES@ +TDEFINES = + +AR = @AR@ +AR_FLAGS = rc +RANLIB = @RANLIB@ +MAKEINFO = makeinfo + +DEP = $(srcroot)/mkdep + +# Each simulator's Makefile.in defines one or more of these variables +# to override our settings as necessary. There is no need to define these +# in the simulator's Makefile.in if one is using the default value. In fact +# it's preferable not to. + +# List of object files, less common parts. +SIM_OBJS = +# List of extra dependencies. +# Generally this consists of simulator specific files included by sim-main.h. +SIM_EXTRA_DEPS = +# List of flags to always pass to $(CC). +SIM_EXTRA_CFLAGS = +# List of extra libraries to link with. +SIM_EXTRA_LIBS = +# List of extra program dependencies. +SIM_EXTRA_LIBDEPS = +# List of main object files for `run'. +SIM_RUN_OBJS = run.o +# Dependency of `all' to build any extra files. +SIM_EXTRA_ALL = +# Dependency of `install' to install any extra files. +SIM_EXTRA_INSTALL = +# Dependency of `clean' to clean any extra files. +SIM_EXTRA_CLEAN = +# Likewise `distclean' +SIM_EXTRA_DISTCLEAN = + +# Every time a new general purpose source file was added every target's +# Makefile.in needed to be updated to include the file in SIM_OBJS. +# This doesn't scale. +# This variable specifies all the generic stuff common to the newer simulators. +# Things like sim-reason.o can't go here as the cpu may provide its own +# (though hopefully in time that won't be so). Things like sim-bits.o can go +# here. Some files are used by all simulators (e.g. callback.o). +# Those files are specified in LIB_OBJS below. + +SIM_COMMON_HW_OBJS = \ + hw-alloc.o \ + hw-base.o \ + hw-device.o \ + hw-events.o \ + hw-handles.o \ + hw-instances.o \ + hw-ports.o \ + hw-properties.o \ + hw-tree.o \ + sim-hw.o \ + +SIM_NEW_COMMON_OBJS = \ + sim-arange.o \ + sim-bits.o \ + sim-config.o \ + sim-core.o \ + sim-endian.o \ + sim-events.o \ + sim-fpu.o \ + sim-io.o \ + sim-info.o \ + sim-load.o \ + sim-memopt.o \ + sim-module.o \ + sim-options.o \ + sim-profile.o \ + sim-signal.o \ + sim-trace.o \ + sim-utils.o \ + sim-watch.o \ + \ + $(SIM_HW_OBJS) \ + +# cgen-sim.h and the headers it includes +CGEN_SIM_DEPS = \ + $(srccom)/cgen-sim.h \ + $(srccom)/cgen-defs.h \ + $(srccom)/cgen-scache.h \ + $(srccom)/cgen-fpu.h \ + $(srccom)/cgen-par.h \ + $(srccom)/cgen-cpu.h \ + $(srccom)/cgen-trace.h \ + cpuall.h + +# Add this to SIM_EXTRA_DEPS. +CGEN_INCLUDE_DEPS = \ + $(CGEN_SIM_DEPS) \ + $(srccom)/cgen-engine.h \ + $(srccom)/cgen-types.h \ + $(srcdir)/../../include/opcode/cgen.h + +## End COMMON_PRE_CONFIG_FRAG + +## COMMON_POST_CONFIG_FRAG + +CONFIG_CFLAGS = \ + @DEFS@ \ + $(SIM_CFLAGS) \ + $(SIM_DEBUG) \ + $(SIM_DEFAULT_MODEL) \ + $(SIM_TRACE) \ + $(SIM_PROFILE) \ + $(SIM_BSWAP) \ + $(SIM_ASSERT) \ + $(SIM_ALIGNMENT) \ + $(SIM_BITSIZE) \ + $(SIM_ENDIAN) \ + $(SIM_ENVIRONMENT) \ + $(SIM_FLOAT) \ + $(SIM_HW_CFLAGS) \ + $(SIM_HOSTENDIAN) \ + $(SIM_INLINE) \ + $(SIM_PACKAGES) \ + $(SIM_REGPARM) \ + $(SIM_RESERVED_BITS) \ + $(SIM_SCACHE) \ + $(SIM_SMP) \ + $(SIM_STDCALL) \ + $(SIM_WARN_CFLAGS) \ + $(SIM_WERROR_CFLAGS) \ + $(SIM_XOR_ENDIAN) \ + $(SIM_HARDWARE) \ + $(SIM_EXTRA_CFLAGS) \ + $(HDEFINES) $(TDEFINES) +CSEARCH = -I. -I$(srcdir) -I../common -I$(srccom) \ + -I../../include -I$(srcroot)/include \ + -I../../bfd -I$(srcroot)/bfd \ + -I../../opcodes -I$(srcroot)/opcodes \ + @INCINTL@ +ALL_CFLAGS = $(CONFIG_CFLAGS) $(CSEARCH) $(CFLAGS) +BUILD_CFLAGS = -g -O $(CSEARCH) + +COMMON_DEP_CFLAGS = $(CONFIG_CFLAGS) $(CSEARCH) + +LIBIBERTY_LIB = ../../libiberty/libiberty.a +BFD_LIB = ../../bfd/libbfd.a +OPCODES_LIB = ../../opcodes/libopcodes.a +LIBINTL = @LIBINTL@ +LIBINTL_DEP = @LIBINTL_DEP@ +CONFIG_LIBS = @LIBS@ +LIBDEPS = $(BFD_LIB) $(OPCODES_LIB) $(LIBINTL_DEP) $(LIBIBERTY_LIB) \ + $(SIM_EXTRA_LIBDEPS) +EXTRA_LIBS = $(BFD_LIB) $(OPCODES_LIB) $(LIBINTL) $(LIBIBERTY_LIB) \ + $(CONFIG_LIBS) $(SIM_EXTRA_LIBS) + +LIB_OBJS = callback.o syscall.o targ-map.o version.o $(SIM_OBJS) + +RUNTESTFLAGS = + +callback_h = $(srcroot)/include/gdb/callback.h +remote_sim_h = $(srcroot)/include/gdb/remote-sim.h + +all: $(SIM_EXTRA_ALL) libsim.a run$(EXEEXT) .gdbinit + +libsim.a: $(LIB_OBJS) + rm -f libsim.a + $(AR) $(AR_FLAGS) libsim.a $(LIB_OBJS) + $(RANLIB) libsim.a + +run$(EXEEXT): $(SIM_RUN_OBJS) libsim.a $(LIBDEPS) + $(CC) $(ALL_CFLAGS) $(LDFLAGS) -o run$(EXEEXT) \ + $(SIM_RUN_OBJS) libsim.a $(EXTRA_LIBS) + +run.o: $(srccom)/run.c config.h tconfig.h $(remote_sim_h) $(callback_h) + $(CC) -c $(srccom)/run.c $(ALL_CFLAGS) + +# FIXME: Ideally, callback.o and friends live in a library outside of +# both the gdb and simulator source trees (e.g. devo/remote. Not +# devo/libremote because this directory would contain more than just +# a library). + +callback.o: $(srccom)/callback.c config.h tconfig.h $(callback_h) targ-vals.h + $(CC) -c $(srccom)/callback.c $(ALL_CFLAGS) + +syscall.o: $(srccom)/syscall.c config.h tconfig.h $(callback_h) targ-vals.h + $(CC) -c $(srccom)/syscall.c $(ALL_CFLAGS) + +targ-map.o: targ-map.c targ-vals.h + +gentmap: Makefile $(srccom)/gentmap.c targ-vals.def + $(CC_FOR_BUILD) $(srccom)/gentmap.c -o gentmap $(BUILD_CFLAGS) $(NL_TARGET) + +targ-vals.h targ-map.c: stamp-tvals +stamp-tvals: gentmap + rm -f tmp-tvals.h tmp-tmap.c + ./gentmap -h >tmp-tvals.h + $(SHELL) $(srcroot)/move-if-change tmp-tvals.h targ-vals.h + ./gentmap -c >tmp-tmap.c + $(SHELL) $(srcroot)/move-if-change tmp-tmap.c targ-map.c + touch stamp-tvals + +version.c: Makefile ../../gdb/version.in + rm -f version.c-tmp version.c + echo '#include "version.h"' >> version.c-tmp + echo 'const char version[] = "'"`sed q ${srcdir}/../../gdb/version.in`"'";' >> version.c-tmp + mv version.c-tmp version.c +version.o: version.c $(version_h) + + +# +# Rules for building sim-* components. Triggered by listing the corresponding +# .o file in the list of simulator targets. +# + +sim_main_headers = \ + sim-main.h \ + $(sim-assert_h) \ + $(sim-base_h) \ + $(sim-cpu_h) \ + $(sim-engine_h) \ + $(sim-events_h) \ + $(sim-memopt_h) \ + $(sim-model_h) \ + $(sim-module_h) \ + $(sim-profile_h) \ + $(sim-trace_h) \ + $(sim-watch_h) \ + $(sim-basics_h) \ + $(SIM_EXTRA_DEPS) + +# Exported version of sim_main_headers. +SIM_MAIN_DEPS = \ + $(sim_main_headers) + +sim-alu_h = $(srccom)/sim-alu.h +sim-arange_h = $(srccom)/sim-arange.h \ + $(srccom)/sim-arange.c +sim-assert_h = $(srccom)/sim-assert.h +sim-base_h = $(srccom)/sim-base.h \ + $(sim-module_h) \ + $(sim-trace_h) \ + $(sim-core_h) \ + $(sim-events_h) \ + $(sim-profile_h) \ + $(sim-model_h) \ + $(sim-io_h) \ + $(sim-engine_h) \ + $(sim-watch_h) \ + $(sim-memopt_h) \ + $(sim-cpu_h) +sim-basics_h = $(srccom)/sim-basics.h \ + ../common/cconfig.h \ + tconfig.h \ + $(sim-config_h) \ + $(callback_h) \ + $(sim-inline_h) \ + $(sim-types_h) \ + $(sim-bits_h) \ + $(sim-endian_h) \ + $(sim-signal_h) \ + $(sim-arange_h) \ + $(sim-utils_h) +sim-bits_h = $(srccom)/sim-bits.h \ + $(srccom)/sim-bits.c +sim-config_h = $(srccom)/sim-config.h +sim-core_h = $(srccom)/sim-core.h +sim-cpu_h = $(srccom)/sim-cpu.h +sim-endian_h = $(srccom)/sim-endian.h \ + $(srccom)/sim-endian.c +sim-engine_h = $(srccom)/sim-engine.h +sim-events_h = $(srccom)/sim-events.h +sim-fpu_h = $(srccom)/sim-fpu.h +sim-hw_h = $(srccom)/sim-hw.h +sim-inline_h = $(srccom)/sim-inline.h +sim-io_h = $(srccom)/sim-io.h +sim-memopt_h = $(srccom)/sim-memopt.h +sim-model_h = $(srccom)/sim-model.h +sim-module_h = $(srccom)/sim-module.h +sim-n-bits_h = $(srccom)/sim-n-bits.h +sim-n-core_h = $(srccom)/sim-n-core.h +sim-n-endian_h = $(srccom)/sim-n-endian.h +sim-options_h = $(srccom)/sim-options.h +sim-profile_h = $(srccom)/sim-profile.h +sim-signal_h = $(srccom)/sim-signal.h +sim-trace_h = $(srccom)/sim-trace.h +sim-types_h = $(srccom)/sim-types.h +sim-utils_h = $(srccom)/sim-utils.h +sim-watch_h = $(srccom)/sim-watch.h + +hw-alloc_h = $(srccom)/hw-alloc.h +hw-base_h = $(srccom)/hw-base.h +hw-device_h = $(srccom)/hw-device.h +hw-events_h = $(srccom)/hw-events.h +hw-handles_h = $(srccom)/hw-handles.h +hw-instances_h = $(srccom)/hw-instances.h +hw-ports_h = $(srccom)/hw-ports.h +hw-properties_h = $(srccom)/hw-properties.h +hw-tree_h = $(srccom)/hw-tree.h + +hw_main_headers = \ + $(srccom)/hw-main.h \ + $(hw-alloc_h) \ + $(hw-base_h) \ + $(hw-device_h) \ + $(hw-events_h) \ + $(hw-instances_h) \ + $(hw-handles_h) \ + $(hw-ports_h) \ + $(hw-properties_h) \ + +# FIXME: If this complicated way of building .o files from ../common is +# necessary, the reason should be documented here. + +BUILT_SRC_FROM_COMMON= \ + sim-inline.c + +sim-abort.o: $(srccom)/sim-abort.c \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-abort.c $(ALL_CFLAGS) + +sim-arange.o: $(srccom)/sim-arange.c $(sim-arange_h) $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-arange.c $(ALL_CFLAGS) + +sim-bits.o: $(srccom)/sim-bits.c $(sim-bits_h) $(sim-n-bits_h) \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS) + +sim-config.o: $(srccom)/sim-config.c $(sim-config_h) sim-main.h \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS) + +sim-core.o: $(srccom)/sim-core.c $(sim_main_headers) \ + $(sim-core_h) $(sim-n-core_h) + $(CC) -c $(srccom)/sim-core.c $(ALL_CFLAGS) + +sim-cpu.o: $(srccom)/sim-cpu.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-cpu.c $(ALL_CFLAGS) + +sim-endian.o: $(srccom)/sim-endian.c $(sim-endian_h) $(sim-n-endian_h) + $(CC) -c $(srccom)/sim-endian.c $(ALL_CFLAGS) + +sim-engine.o: $(srccom)/sim-engine.c $(sim_main_headers) $(sim-engine_h) + $(CC) -c $(srccom)/sim-engine.c $(ALL_CFLAGS) + +sim-events.o: $(srccom)/sim-events.c $(sim-events_h) sim-main.h \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-events.c $(ALL_CFLAGS) + +sim-fpu.o: $(srccom)/sim-fpu.c $(sim-fpu_h) \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-fpu.c $(ALL_CFLAGS) + +sim-hload.o: $(srccom)/sim-hload.c $(sim-assert_h) $(remote_sim_h) \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-hload.c $(ALL_CFLAGS) + +sim-hrw.o: $(srccom)/sim-hrw.c $(sim-assert_h) $(sim_core_h) $(remote_sim_h) \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-hrw.c $(ALL_CFLAGS) + +sim-hw.o: $(srccom)/sim-hw.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-hw.c $(ALL_CFLAGS) + +sim-info.o: $(srccom)/sim-info.c $(sim-assert_h) $(remote_sim_h) \ + $(SIM_EXTRA_DEPS) + $(CC) -c $(srccom)/sim-info.c $(ALL_CFLAGS) + +sim-inline.c: $(srccom)/sim-inline.c + rm -f $@ tmp-$@ + echo "# 1 \"$(srccom)/$@\"" > tmp-$@ + cat $(srccom)/$@ >> tmp-$@ + $(SHELL) $(srcdir)/../../move-if-change tmp-$@ $@ + +sim-io.o: $(srccom)/sim-io.c $(sim_main_headers) $(sim-io_h) $(remote_sim_h) \ + targ-vals.h + $(CC) -c $(srccom)/sim-io.c $(ALL_CFLAGS) + +sim-memopt.o: $(srccom)/sim-memopt.c $(sim_main_headers) \ + $(sim-io_h) + $(CC) -c $(srccom)/sim-memopt.c $(ALL_CFLAGS) + +sim-module.o: $(srccom)/sim-module.c $(sim_main_headers) \ + $(sim-io_h) + $(CC) -c $(srccom)/sim-module.c $(ALL_CFLAGS) + +sim-options.o: $(srccom)/sim-options.c $(sim_main_headers) \ + $(sim-options_h) $(sim-io_h) + $(CC) -c $(srccom)/sim-options.c $(ALL_CFLAGS) + +sim-reason.o: $(srccom)/sim-reason.c $(sim_main_headers) $(remote_sim_h) + $(CC) -c $(srccom)/sim-reason.c $(ALL_CFLAGS) + +sim-reg.o: $(srccom)/sim-reg.c $(sim_main_headers) $(remote_sim_h) + $(CC) -c $(srccom)/sim-reg.c $(ALL_CFLAGS) + +sim-resume.o: $(srccom)/sim-resume.c $(sim_main_headers) $(remote_sim_h) + $(CC) -c $(srccom)/sim-resume.c $(ALL_CFLAGS) + +sim-run.o: $(srccom)/sim-run.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-run.c $(ALL_CFLAGS) + +sim-signal.o: $(srccom)/sim-signal.c $(sim_main_headers) $(sim-signal_h) + $(CC) -c $(srccom)/sim-signal.c $(ALL_CFLAGS) + +sim-stop.o: $(srccom)/sim-stop.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-stop.c $(ALL_CFLAGS) + +sim-trace.o: $(srccom)/sim-trace.c $(sim_main_headers) \ + $(sim-options_h) $(sim-io_h) + $(CC) -c $(srccom)/sim-trace.c $(ALL_CFLAGS) + +sim-profile.o: $(srccom)/sim-profile.c $(sim_main_headers) \ + $(sim-options_h) $(sim-io_h) + $(CC) -c $(srccom)/sim-profile.c $(ALL_CFLAGS) + +sim-model.o: $(srccom)/sim-model.c $(sim_main_headers) \ + $(sim-io_h) + $(CC) -c $(srccom)/sim-model.c $(ALL_CFLAGS) + +sim-utils.o: $(srccom)/sim-utils.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-utils.c $(ALL_CFLAGS) + +sim-watch.o: $(srccom)/sim-watch.c $(sim_main_headers) + $(CC) -c $(srccom)/sim-watch.c $(ALL_CFLAGS) + +sim-load.o: $(srccom)/sim-load.c $(callback_h) $(sim-basics_h) $(remote_sim_h) + $(CC) -c $(srccom)/sim-load.c $(ALL_CFLAGS) + + +# FIXME This is one very simple-minded way of generating the file hw-config.h +hw-config.h: Makefile.in $(srccom)/Make-common.in config.status Makefile + rm -f tmp-hw.h + echo "/* generated by Makefile */" > tmp-hw.h + for hw in $(SIM_HW) ; do \ + echo "extern const struct hw_descriptor dv_$${hw}_descriptor[];" ; \ + done >> tmp-hw.h + echo "const struct hw_descriptor *hw_descriptors[] = {" >> tmp-hw.h + for hw in $(SIM_HW) ; do \ + echo " dv_$${hw}_descriptor," ; \ + done >> tmp-hw.h + echo " NULL," >> tmp-hw.h + echo "};" >> tmp-hw.h + mv tmp-hw.h hw-config.h + +hw-alloc.o: $(srccom)/hw-alloc.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-alloc.c $(ALL_CFLAGS) + +hw-base.o: $(srccom)/hw-base.c $(hw_main_headers) hw-config.h + $(CC) -c $(srccom)/hw-base.c $(ALL_CFLAGS) + +hw-device.o: $(srccom)/hw-device.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-device.c $(ALL_CFLAGS) + +hw-events.o: $(srccom)/hw-events.c $(hw_main_headers) $(sim_main_headers) + $(CC) -c $(srccom)/hw-events.c $(ALL_CFLAGS) + +test-hw-events: $(srccom)/hw-events.c libsim.a + $(CC) $(ALL_CFLAGS) -DMAIN -o test-hw-events$(EXEEXT) \ + $(srccom)/hw-events.c libsim.a $(EXTRA_LIBS) + +hw-instances.o: $(srccom)/hw-instances.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-instances.c $(ALL_CFLAGS) + +hw-handles.o: $(srccom)/hw-handles.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-handles.c $(ALL_CFLAGS) + +hw-ports.o: $(srccom)/hw-ports.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-ports.c $(ALL_CFLAGS) + +hw-properties.o: $(srccom)/hw-properties.c $(hw_main_headers) + $(CC) -c $(srccom)/hw-properties.c $(ALL_CFLAGS) + +hw-tree.o: $(srccom)/hw-tree.c $(hw_main_headers) $(hw-tree_h) + $(CC) -c $(srccom)/hw-tree.c $(ALL_CFLAGS) + +# Devices. + +dv-cfi.o: $(srccom)/dv-cfi.c $(hw_main_headers) $(sim_main_headers) + $(CC) -c $(srccom)/dv-cfi.c $(ALL_CFLAGS) + +dv-core.o: $(srccom)/dv-core.c $(hw_main_headers) $(sim_main_headers) + $(CC) -c $(srccom)/dv-core.c $(ALL_CFLAGS) + +dv-glue.o: $(srccom)/dv-glue.c $(hw_main_headers) $(sim_main_headers) + $(CC) -c $(srccom)/dv-glue.c $(ALL_CFLAGS) + +dv-pal.o: $(srccom)/dv-pal.c $(hw_main_headers) $(sim_main_headers) + $(CC) -c $(srccom)/dv-pal.c $(ALL_CFLAGS) + +dv-sockser.o: $(srccom)/dv-sockser.h $(sim_main_headers) + $(CC) -c $(srccom)/dv-sockser.c $(ALL_CFLAGS) + + +nrun.o: $(srccom)/nrun.c config.h tconfig.h $(remote_sim_h) $(callback_h) \ + $(sim_main_headers) + $(CC) -c $(srccom)/nrun.c $(ALL_CFLAGS) + +# CGEN support. + +# For use in Makefile.in for cpu-specific files. +CGEN_MAIN_CPU_DEPS = \ + $(SIM_MAIN_DEPS) \ + $(srccom)/cgen-ops.h \ + $(srccom)/cgen-mem.h + +cgen-run.o: $(srccom)/cgen-run.c $(sim_main_headers) + $(CC) -c $(srccom)/cgen-run.c $(ALL_CFLAGS) + +cgen-scache.o: $(srccom)/cgen-scache.c $(sim_main_headers) + $(CC) -c $(srccom)/cgen-scache.c $(ALL_CFLAGS) + +cgen-trace.o: $(srccom)/cgen-trace.c $(sim_main_headers) + $(CC) -c $(srccom)/cgen-trace.c $(ALL_CFLAGS) + +cgen-fpu.o: $(srccom)/cgen-fpu.c $(sim_main_headers) $(sim-fpu_h) + $(CC) -c $(srccom)/cgen-fpu.c $(ALL_CFLAGS) + +cgen-accfp.o: $(srccom)/cgen-accfp.c $(sim_main_headers) $(sim-fpu_h) + $(CC) -c $(srccom)/cgen-accfp.c $(ALL_CFLAGS) + +cgen-utils.o: $(srccom)/cgen-utils.c $(sim_main_headers) \ + $(srccom)/cgen-mem.h $(srccom)/cgen-ops.h $(srccom)/cgen-engine.h + $(CC) -c $(srccom)/cgen-utils.c $(ALL_CFLAGS) + +cgen-par.o: $(srccom)/cgen-par.c $(sim_main_headers) \ + $(srccom)/cgen-mem.h $(srccom)/cgen-par.h + $(CC) -c $(srccom)/cgen-par.c $(ALL_CFLAGS) + +# Support targets. + +install: install-common $(SIM_EXTRA_INSTALL) + +install-common: installdirs + n=`echo run | sed '$(program_transform_name)'`; \ + $(INSTALL_PROGRAM) run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT) + n=`echo libsim.a | sed s/libsim.a/lib$(target_alias)-sim.a/`; \ + $(INSTALL_DATA) libsim.a $(DESTDIR)$(libdir)/$$n ; \ + ( cd $(DESTDIR)$(libdir) ; $(RANLIB) $$n ) + +installdirs: + $(SHELL) $(srcdir)/../../mkinstalldirs $(DESTDIR)$(bindir) + $(SHELL) $(srcdir)/../../mkinstalldirs $(DESTDIR)$(libdir) + +check: + cd ../testsuite && $(MAKE) check RUNTESTFLAGS="$(RUNTESTFLAGS)" + +info: +clean-info: +install-info: + +.NOEXPORT: +MAKEOVERRIDES= + +tags etags: TAGS + +# Macros like EXTERN_SIM_CORE confuse tags. +# And the sim-n-foo.h files create functions that can't be found either. +TAGS: force + cd $(srcdir) && \ + etags --regex '/^\([a-z_]+\) (/\1/' --regex '/^\/[*] TAGS: .*/' \ + *.[ch] ../common/*.[ch] + +clean: $(SIM_EXTRA_CLEAN) + rm -f *.[oa] *~ core + rm -f run$(EXEEXT) libsim.a + rm -f gentmap targ-map.c targ-vals.h stamp-tvals + if [ ! -f Make-common.in ] ; then \ + rm -f $(BUILT_SRC_FROM_COMMON) ; \ + fi + rm -f tmp-mloop.hin tmp-mloop.h tmp-mloop.cin tmp-mloop.c + +distclean mostlyclean maintainer-clean realclean: clean $(SIM_EXTRA_DISTCLEAN) + rm -f TAGS + rm -f Makefile config.cache config.log config.status .gdbinit + rm -f tconfig.h config.h stamp-h + rm -f targ-vals.def + +.c.o: + $(CC) -c $(ALL_CFLAGS) $< + +# Dummy target to force execution of dependent targets. +force: + +Makefile: Makefile.in $(srccom)/Make-common.in config.status + CONFIG_HEADERS= $(SHELL) ./config.status + +config.status: configure + $(SHELL) ./config.status --recheck + +config.h: stamp-h ; @true +stamp-h: config.in config.status + CONFIG_FILES= CONFIG_HEADERS=config.h:config.in $(SHELL) ./config.status + +.gdbinit: # config.status $(srccom)/gdbinit.in + CONFIG_FILES=$@:../common/gdbinit.in CONFIG_HEADERS= $(SHELL) ./config.status + + +# CGEN support + +CGENDIR = @cgendir@ +CGEN = "`if [ -f ../../guile/libguile/guile ]; then echo ../../guile/libguile/guile; else echo guile ; fi` -l $(CGENDIR)/guile.scm -s" +CGENFLAGS = -v +CGEN_CPU_DIR = $(CGENDIR)/cpu + +# Most ports use the files here instead of cgen/cpu. +CPU_DIR = $(srcroot)/cpu + +CGEN_READ_SCM = $(CGENDIR)/sim.scm +CGEN_ARCH_SCM = $(CGENDIR)/sim-arch.scm +CGEN_CPU_SCM = $(CGENDIR)/sim-cpu.scm $(CGENDIR)/sim-model.scm +CGEN_DECODE_SCM = $(CGENDIR)/sim-decode.scm +CGEN_DESC_SCM = $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm + +# Various choices for which cpu specific files to generate. +# These are passed to cgen.sh in the "extrafiles" argument. +CGEN_CPU_EXTR = /extr/ +CGEN_CPU_READ = /read/ +CGEN_CPU_WRITE = /write/ +CGEN_CPU_SEM = /sem/ +CGEN_CPU_SEMSW = /semsw/ + +CGEN_FLAGS_TO_PASS = \ + CGEN='$(CGEN)' \ + CGENFLAGS="$(CGENFLAGS)" + +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter with gdb/binutils. Maybe we never will. + +cgen-arch: force + $(SHELL) $(srccom)/cgen.sh arch $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" ignored "$(isa)" $(mach) ignored \ + $(archfile) ignored + +cgen-cpu: force + $(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" + +cgen-defs: force + $(SHELL) $(srccom)/cgen.sh defs $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) ignored + +cgen-decode: force + $(SHELL) $(srccom)/cgen.sh decode $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" + +cgen-cpu-decode: force + $(SHELL) $(srccom)/cgen.sh cpu-decode $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) "$(EXTRAFILES)" + +cgen-desc: force + $(SHELL) $(srccom)/cgen.sh desc $(srcdir) \ + $(CGEN) $(CGENDIR) "$(CGENFLAGS)" \ + $(arch) "$(FLAGS)" $(cpu) "$(isa)" $(mach) "$(SUFFIX)" \ + $(archfile) ignored $(opcfile) + +## End COMMON_POST_CONFIG_FRAG diff --git a/external/gpl3/gdb/dist/sim/common/Makefile.in b/external/gpl3/gdb/dist/sim/common/Makefile.in new file mode 100644 index 000000000000..5fca9dab0377 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/Makefile.in @@ -0,0 +1,136 @@ +# Makefile template for Configure for simulator common directory +# Copyright (C) 1996, 1997, 2007, 2008, 2009, 2010, 2011 +# Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +default: all + +VPATH = @srcdir@ +srcdir = @srcdir@ +srcroot = $(srcdir)/../.. + +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +host_alias = @host_alias@ +target_alias = @target_alias@ +program_transform_name = @program_transform_name@ +bindir = @bindir@ + +libdir = @libdir@ +tooldir = $(libdir)/$(target_alias) + +datarootdir = @datarootdir@ +datadir = @datadir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +infodir = @infodir@ +includedir = @includedir@ + +SHELL = /bin/sh + +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ + +CC = @CC@ +CC_FOR_BUILD = @CC_FOR_BUILD@ +CFLAGS = @CFLAGS@ +SIM_CFLAGS = @sim_cflags@ + +# These are used to rebuild nltvals.def. +CPP_FOR_TARGET = @CPP_FOR_TARGET@ +TARGET_SUBDIR = @TARGET_SUBDIR@ + +HDEFINES = @HDEFINES@ +TDEFINES = + +CONFIG_CFLAGS = @DEFS@ $(SIM_CFLAGS) $(HDEFINES) $(TDEFINES) +CSEARCH = -I. -I$(srcdir) -I$(srcroot)/include +ALL_CFLAGS = $(CFLAGS) $(CONFIG_CFLAGS) $(CSEARCH) +BUILD_CFLAGS = -g -O $(CSEARCH) + +AR = @AR@ +AR_FLAGS = rc +RANLIB = @RANLIB@ +MAKEINFO = makeinfo + +.NOEXPORT: +MAKEOVERRIDES= + +all: + +# Generate nltvals.def for newlib/libgloss using devo and build tree. +# This file is shipped with distributions so we build in the source dir. +# Use `make headers' to rebuild. +# Note: If gdb releases begin to contain target header files (not a good idea, +# but if they did ...), targ-vals.def coud be generated at build time. +# An alternative is to slurp in the tables at runtime. +.PHONY: headers +headers: + rootme=`pwd` ; \ + cd $(srcdir) ; \ + rm -f nltvals.new ; \ + $(SHELL) $(srcdir)/gennltvals.sh $(SHELL) $(srcroot) "$(CPP_FOR_TARGET)" > nltvals.new ; \ + $(SHELL) $(srcroot)/move-if-change nltvals.new nltvals.def + +.c.o: + $(CC) -c $< $(ALL_CFLAGS) + +check: + +info: +clean-info: +install-info: + +tags etags: TAGS + +# Macros like EXTERN_SIM_CORE confuse tags. +# And the sim-n-foo.h files create functions that can't be found either. +TAGS: force + cd $(srcdir) && \ + etags --regex '/^\([a-z_]+\) (/\1/' --regex '/^.*\/[*] TAGS: .*/' \ + *.c *.h + +clean: + rm -f *.[oa] *~ core + +distclean mostlyclean maintainer-clean realclean: clean + rm -f TAGS + rm -f Makefile config.cache config.log config.status + rm -f cconfig.h config.h stamp-h + +# Dummy target to force execution of dependent targets. +force: + +# Copy the files into directories where they will be run. +install: install-man + +install-man: installdirs + n=`echo run | sed '$(program_transform_name)'`; \ + $(INSTALL_DATA) $(srcdir)/run.1 $(DESTDIR)$(man1dir)/$$n.1 + +installdirs: + $(SHELL) $(srcdir)/../../mkinstalldirs $(DESTDIR)$(man1dir) + +Makefile: Makefile.in config.status + $(SHELL) ./config.status + +config.status: configure + $(SHELL) ./config.status --recheck + +config.h: stamp-h ; @true +stamp-h: config.in config.status + CONFIG_FILES= CONFIG_HEADERS=config.h:config.in $(SHELL) ./config.status diff --git a/external/gpl3/gdb/dist/sim/common/aclocal.m4 b/external/gpl3/gdb/dist/sim/common/aclocal.m4 new file mode 100644 index 000000000000..cec0155e6755 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/aclocal.m4 @@ -0,0 +1,937 @@ +# This file contains common code used by all simulators. +# +# SIM_AC_COMMON invokes AC macros used by all simulators and by the common +# directory. It is intended to be invoked before any target specific stuff. +# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile. +# It is intended to be invoked last. +# +# The simulator's configure.in should look like: +# +# dnl Process this file with autoconf to produce a configure script. +# sinclude(../common/aclocal.m4) +# AC_PREREQ(2.5)dnl +# AC_INIT(Makefile.in) +# +# SIM_AC_COMMON +# +# ... target specific stuff ... +# +# SIM_AC_OUTPUT + +# Include global overrides and fixes for Autoconf. +m4_include(../../config/override.m4) +sinclude([../../config/zlib.m4]) + +AC_DEFUN([SIM_AC_COMMON], +[ +# autoconf.info says this should be called right after AC_INIT. +AC_CONFIG_HEADER(ifelse([$1],,config.h,[$1]):config.in) +AC_CANONICAL_SYSTEM +AC_ARG_PROGRAM +AC_PROG_CC +AC_PROG_INSTALL + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi +AC_SUBST(CC_FOR_BUILD) + +AC_SUBST(CFLAGS) +AC_SUBST(HDEFINES) +AR=${AR-ar} +AC_SUBST(AR) +AC_PROG_RANLIB + +dnl We don't use gettext, but bfd does. So we do the appropriate checks +dnl to see if there are intl libraries we should link against. +ALL_LINGUAS= +ZW_GNU_GETTEXT_SISTER_DIR(../../intl) + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. +AC_CHECK_HEADERS(stdlib.h string.h strings.h unistd.h time.h) +AC_CHECK_HEADERS(sys/time.h sys/resource.h) +AC_CHECK_HEADERS(fcntl.h fpu_control.h) +AC_CHECK_HEADERS(dlfcn.h errno.h sys/stat.h) +AC_CHECK_FUNCS(getrusage time sigaction __setfpucw) + +# Check for socket libraries +AC_CHECK_LIB(socket, bind) +AC_CHECK_LIB(nsl, gethostbyname) + +. ${srcdir}/../../bfd/configure.host + +dnl Standard (and optional) simulator options. +dnl Eventually all simulators will support these. +dnl Do not add any here that cannot be supported by all simulators. +dnl Do not add similar but different options to a particular simulator, +dnl all shall eventually behave the same way. + + +dnl We don't use automake, but we still want to support +dnl --enable-maintainer-mode. +USE_MAINTAINER_MODE=no +AC_ARG_ENABLE(maintainer-mode, +[ --enable-maintainer-mode Enable developer functionality.], +[case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) AC_MSG_ERROR("--enable-maintainer-mode does not take a value"); MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi],[MAINT="#"])dnl +AC_SUBST(MAINT) + + +dnl This is a generic option to enable special byte swapping +dnl insns on *any* cpu. +AC_ARG_ENABLE(sim-bswap, +[ --enable-sim-bswap Use Host specific BSWAP instruction.], +[case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) AC_MSG_ERROR("--enable-sim-bswap does not take a value"); sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi],[sim_bswap=""])dnl +AC_SUBST(sim_bswap) + + +AC_ARG_ENABLE(sim-cflags, +[ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator], +[case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) AC_MSG_ERROR("Please use --enable-sim-debug instead."); sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi],[sim_cflags=""])dnl +AC_SUBST(sim_cflags) + + +dnl --enable-sim-debug is for developers of the simulator +dnl the allowable values are work-in-progress +AC_ARG_ENABLE(sim-debug, +[ --enable-sim-debug=opts Enable debugging flags], +[case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi],[sim_debug=""])dnl +AC_SUBST(sim_debug) + + +dnl --enable-sim-stdio is for users of the simulator +dnl It determines if IO from the program is routed through STDIO (buffered) +AC_ARG_ENABLE(sim-stdio, +[ --enable-sim-stdio Specify whether to use stdio for console input/output.], +[case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-stdio"); sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi],[sim_stdio=""])dnl +AC_SUBST(sim_stdio) + + +dnl --enable-sim-trace is for users of the simulator +dnl The argument is either a bitmask of things to enable [exactly what is +dnl up to the simulator], or is a comma separated list of names of tracing +dnl elements to enable. The latter is only supported on simulators that +dnl use WITH_TRACE. +AC_ARG_ENABLE(sim-trace, +[ --enable-sim-trace=opts Enable tracing flags], +[case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [[-0-9]]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [[a-z]]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi],[sim_trace=""])dnl +AC_SUBST(sim_trace) + + +dnl --enable-sim-profile +dnl The argument is either a bitmask of things to enable [exactly what is +dnl up to the simulator], or is a comma separated list of names of profiling +dnl elements to enable. The latter is only supported on simulators that +dnl use WITH_PROFILE. +AC_ARG_ENABLE(sim-profile, +[ --enable-sim-profile=opts Enable profiling flags], +[case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [[-0-9]]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [[a-z]]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi],[sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"])dnl +AC_SUBST(sim_profile) + + +dnl Types used by common code +AC_TYPE_SIGNAL + +dnl Detect exe extension +AC_EXEEXT + +dnl These are available to append to as desired. +sim_link_files= +sim_link_links= + +dnl Create tconfig.h either from simulator's tconfig.in or default one +dnl in common. +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + +]) dnl End of SIM_AC_COMMON + + +dnl Additional SIM options that can (optionally) be configured +dnl For optional simulator options, a macro SIM_AC_OPTION_* is defined. +dnl Simulators that wish to use the relevant option specify the macro +dnl in the simulator specific configure.in file between the SIM_AC_COMMON +dnl and SIM_AC_OUTPUT lines. + + +dnl Specify the running environment. +dnl If the simulator invokes this in its configure.in then without this option +dnl the default is the user environment and all are runtime selectable. +dnl If the simulator doesn't invoke this, only the user environment is +dnl supported. +dnl ??? Until there is demonstrable value in doing something more complicated, +dnl let's not. +AC_DEFUN([SIM_AC_OPTION_ENVIRONMENT], +[ +AC_ARG_ENABLE(sim-environment, +[ --enable-sim-environment=environment Specify mixed, user, virtual or operating environment.], +[case "${enableval}" in + all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";; + user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";; + virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";; + operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-environment"); + sim_environment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then + echo "Setting sim environment = $sim_environment" 6>&1 +fi], +[sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"])dnl +]) +AC_SUBST(sim_environment) + + +dnl Specify the alignment restrictions of the target architecture. +dnl Without this option all possible alignment restrictions are accommodated. +dnl arg[1] is hardwired target alignment +dnl arg[2] is default target alignment +AC_DEFUN([SIM_AC_OPTION_ALIGNMENT], +wire_alignment="[$1]" +default_alignment="[$2]" +[ +AC_ARG_ENABLE(sim-alignment, +[ --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses.], +[case "${enableval}" in + strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";; + nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";; + forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";; + yes) if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${default_alignment}" + else + echo "No hard-wired alignment for target $target" 1>&6 + sim_alignment="-DWITH_ALIGNMENT=0" + fi + fi;; + no) if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" + else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}" + else + echo "No default alignment for target $target" 1>&6 + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0" + fi + fi;; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-alignment"); sim_alignment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then + echo "Setting alignment flags = $sim_alignment" 6>&1 +fi], +[if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" +else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + sim_alignment= + fi +fi])dnl +])dnl +AC_SUBST(sim_alignment) + + +dnl Conditionally compile in assertion statements. +AC_DEFUN([SIM_AC_OPTION_ASSERT], +[ +AC_ARG_ENABLE(sim-assert, +[ --enable-sim-assert Specify whether to perform random assertions.], +[case "${enableval}" in + yes) sim_assert="-DWITH_ASSERT=1";; + no) sim_assert="-DWITH_ASSERT=0";; + *) AC_MSG_ERROR("--enable-sim-assert does not take a value"); sim_assert="";; +esac +if test x"$silent" != x"yes" && test x"$sim_assert" != x""; then + echo "Setting assert flags = $sim_assert" 6>&1 +fi],[sim_assert=""])dnl +]) +AC_SUBST(sim_assert) + + + +dnl --enable-sim-bitsize is for developers of the simulator +dnl It specifies the number of BITS in the target. +dnl arg[1] is the number of bits in a word +dnl arg[2] is the number assigned to the most significant bit +dnl arg[3] is the number of bits in an address +dnl arg[4] is the number of bits in an OpenFirmware cell. +dnl FIXME: this information should be obtained from bfd/archure +AC_DEFUN([SIM_AC_OPTION_BITSIZE], +wire_word_bitsize="[$1]" +wire_word_msb="[$2]" +wire_address_bitsize="[$3]" +wire_cell_bitsize="[$4]" +[AC_ARG_ENABLE(sim-bitsize, +[ --enable-sim-bitsize=N Specify target bitsize (32 or 64).], +[sim_bitsize= +case "${enableval}" in + 64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";; + 32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";; + 64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0" + fi ;; + 64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0" + fi ;; + *) AC_MSG_ERROR("--enable-sim-bitsize was given $enableval. Expected 32 or 64") ;; +esac +# address bitsize +tmp=`echo "${enableval}" | sed -e "s/^[[0-9]]*,*[[0-9]]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;; + * ) AC_MSG_ERROR("--enable-sim-bitsize was given address size $enableval. Expected 32 or 64") ;; +esac +# cell bitsize +tmp=`echo "${enableval}" | sed -e "s/^[[0-9]]*,*[[0-9*]]*,*[[0-9]]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;; + * ) AC_MSG_ERROR("--enable-sim-bitsize was given cell size $enableval. Expected 32 or 64") ;; +esac +if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then + echo "Setting bitsize flags = $sim_bitsize" 6>&1 +fi], +[sim_bitsize="" +if test x"$wire_word_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize" +fi +if test x"$wire_word_msb" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb" +fi +if test x"$wire_address_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize" +fi +if test x"$wire_cell_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize" +fi])dnl +]) +AC_SUBST(sim_bitsize) + + + +dnl --enable-sim-endian={yes,no,big,little} is for simulators +dnl that support both big and little endian targets. +dnl arg[1] is hardwired target endianness. +dnl arg[2] is default target endianness. +AC_DEFUN([SIM_AC_OPTION_ENDIAN], +[ +wire_endian="[$1]" +default_endian="[$2]" +AC_ARG_ENABLE(sim-endian, +[ --enable-sim-endian=endian Specify target byte endian orientation.], +[case "${enableval}" in + b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";; + yes) if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + if test x"$default_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}" + else + echo "No hard-wired endian for target $target" 1>&6 + sim_endian="-DWITH_TARGET_BYTE_ORDER=0" + fi + fi;; + no) if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" + else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}" + else + echo "No default endian for target $target" 1>&6 + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0" + fi + fi;; + *) AC_MSG_ERROR("Unknown value $enableval for --enable-sim-endian"); sim_endian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then + echo "Setting endian flags = $sim_endian" 6>&1 +fi], +[if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" +else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + sim_endian= + fi +fi])dnl +]) +AC_SUBST(sim_endian) + + +dnl --enable-sim-hostendian is for users of the simulator when +dnl they find that AC_C_BIGENDIAN does not function correctly +dnl (for instance in a canadian cross) +AC_DEFUN([SIM_AC_OPTION_HOSTENDIAN], +[ +AC_ARG_ENABLE(sim-hostendian, +[ --enable-sim-hostendian=end Specify host byte endian orientation.], +[case "${enableval}" in + no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";; + b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";; + *) AC_MSG_ERROR("Unknown value $enableval for --enable-sim-hostendian"); sim_hostendian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then + echo "Setting hostendian flags = $sim_hostendian" 6>&1 +fi],[ +if test "x$cross_compiling" = "xno"; then + AC_C_BIGENDIAN + if test $ac_cv_c_bigendian = yes; then + sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN" + else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN" + fi +else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=0" +fi])dnl +]) +AC_SUBST(sim_hostendian) + + +dnl --enable-sim-float is for developers of the simulator +dnl It specifies the presence of hardware floating point +dnl And optionally the bitsize of the floating point register. +dnl arg[1] specifies the presence (or absence) of floating point hardware +dnl arg[2] specifies the number of bits in a floating point register +AC_DEFUN([SIM_AC_OPTION_FLOAT], +[ +default_sim_float="[$1]" +default_sim_float_bitsize="[$2]" +AC_ARG_ENABLE(sim-float, +[ --enable-sim-float Specify that the target processor has floating point hardware.], +[case "${enableval}" in + yes | hard) sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT";; + no | soft) sim_float="-DWITH_FLOATING_POINT=SOFT_FLOATING_POINT";; + 32) sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=32";; + 64) sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=64";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-float"); sim_float="";; +esac +if test x"$silent" != x"yes" && test x"$sim_float" != x""; then + echo "Setting float flags = $sim_float" 6>&1 +fi],[ +sim_float= +if test x"${default_sim_float}" != x""; then + sim_float="-DWITH_FLOATING_POINT=${default_sim_float}" +fi +if test x"${default_sim_float_bitsize}" != x""; then + sim_float="$sim_float -DWITH_TARGET_FLOATING_POINT_BITSIZE=${default_sim_float_bitsize}" +fi +])dnl +]) +AC_SUBST(sim_float) + + +dnl The argument is the default cache size if none is specified. +AC_DEFUN([SIM_AC_OPTION_SCACHE], +[ +default_sim_scache="ifelse([$1],,0,[$1])" +AC_ARG_ENABLE(sim-scache, +[ --enable-sim-scache=size Specify simulator execution cache size.], +[case "${enableval}" in + yes) sim_scache="-DWITH_SCACHE=${default_sim_scache}";; + no) sim_scache="-DWITH_SCACHE=0" ;; + [[0-9]]*) sim_scache="-DWITH_SCACHE=${enableval}";; + *) AC_MSG_ERROR("Bad value $enableval passed to --enable-sim-scache"); + sim_scache="";; +esac +if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then + echo "Setting scache size = $sim_scache" 6>&1 +fi],[sim_scache="-DWITH_SCACHE=${default_sim_scache}"]) +]) +AC_SUBST(sim_scache) + + +dnl The argument is the default model if none is specified. +AC_DEFUN([SIM_AC_OPTION_DEFAULT_MODEL], +[ +default_sim_default_model="ifelse([$1],,0,[$1])" +AC_ARG_ENABLE(sim-default-model, +[ --enable-sim-default-model=model Specify default model to simulate.], +[case "${enableval}" in + yes|no) AC_MSG_ERROR("Missing argument to --enable-sim-default-model");; + *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";; +esac +if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then + echo "Setting default model = $sim_default_model" 6>&1 +fi],[sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"]) +]) +AC_SUBST(sim_default_model) + + +dnl --enable-sim-hardware is for users of the simulator +dnl arg[1] Enable sim-hw by default? ("yes" or "no") +dnl arg[2] is a space separated list of devices that override the defaults +dnl arg[3] is a space separated list of extra target specific devices. +AC_DEFUN([SIM_AC_OPTION_HARDWARE], +[ +if test x"[$1]" = x"yes"; then + sim_hw_p=yes +else + sim_hw_p=no +fi +if test "[$2]"; then + hardware="[$2]" +else + hardware="cfi core pal glue" +fi +hardware="$hardware [$3]" +sim_hw_cflags="-DWITH_HW=1" +sim_hw="$hardware" +sim_hw_objs="\$(SIM_COMMON_HW_OBJS) `echo $sim_hw | sed -e 's/\([[^ ]][[^ ]]*\)/dv-\1.o/g'`" +AC_ARG_ENABLE(sim-hardware, +[ --enable-sim-hardware=LIST Specify the hardware to be included in the build.], +[ +case "${enableval}" in + yes) sim_hw_p=yes;; + no) sim_hw_p=no;; + ,*) sim_hw_p=yes; hardware="${hardware} `echo ${enableval} | sed -e 's/,/ /'`";; + *,) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'` ${hardware}";; + *) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'`"'';; +esac +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +else + sim_hw_cflags="-DWITH_HW=1" + # remove duplicates + sim_hw="" + sim_hw_objs="\$(SIM_COMMON_HW_OBJS)" + for i in $hardware ; do + case " $sim_hw " in + *" $i "*) ;; + *) sim_hw="$sim_hw $i" ; sim_hw_objs="$sim_hw_objs dv-$i.o";; + esac + done +fi +if test x"$silent" != x"yes" && test "$sim_hw_p" = "yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi],[ +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +fi +if test x"$silent" != x"yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi])dnl +]) +AC_SUBST(sim_hw_cflags) +AC_SUBST(sim_hw_objs) +AC_SUBST(sim_hw) + + +dnl --enable-sim-inline is for users that wish to ramp up the simulator's +dnl performance by inlining functions. +dnl Guarantee that unconfigured simulators do not do any inlining +sim_inline="-DDEFAULT_INLINE=0" +AC_DEFUN([SIM_AC_OPTION_INLINE], +[ +default_sim_inline="ifelse([$1],,,-DDEFAULT_INLINE=[$1])" +AC_ARG_ENABLE(sim-inline, +[ --enable-sim-inline=inlines Specify which functions should be inlined.], +[sim_inline="" +case "$enableval" in + no) sim_inline="-DDEFAULT_INLINE=0";; + 0) sim_inline="-DDEFAULT_INLINE=0";; + yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";; + 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";; + *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + new_flag="" + case "$x" in + *_INLINE=*) new_flag="-D$x";; + *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;; + *_INLINE) new_flag="-D$x=ALL_C_INLINE";; + *) new_flag="-D$x""_INLINE=ALL_C_INLINE";; + esac + if test x"$sim_inline" = x""; then + sim_inline="$new_flag" + else + sim_inline="$sim_inline $new_flag" + fi + done;; +esac +if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then + echo "Setting inline flags = $sim_inline" 6>&1 +fi],[ +if test "x$cross_compiling" = "xno"; then + if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then + sim_inline="${default_sim_inline}" + if test x"$silent" != x"yes"; then + echo "Setting inline flags = $sim_inline" 6>&1 + fi + else + sim_inline="" + fi +else + sim_inline="-DDEFAULT_INLINE=0" +fi])dnl +]) +AC_SUBST(sim_inline) + + +AC_DEFUN([SIM_AC_OPTION_PACKAGES], +[ +AC_ARG_ENABLE(sim-packages, +[ --enable-sim-packages=list Specify the packages to be included in the build.], +[packages=disklabel +case "${enableval}" in + yes) ;; + no) AC_MSG_ERROR("List of packages must be specified for --enable-sim-packages"); packages="";; + ,*) packages="${packages}${enableval}";; + *,) packages="${enableval}${packages}";; + *) packages="${enableval}"'';; +esac +sim_pk_src=`echo $packages | sed -e 's/,/.c pk_/g' -e 's/^/pk_/' -e 's/$/.c/'` +sim_pk_obj=`echo $sim_pk_src | sed -e 's/\.c/.o/g'` +if test x"$silent" != x"yes" && test x"$packages" != x""; then + echo "Setting packages to $sim_pk_src, $sim_pk_obj" +fi],[packages=disklabel +sim_pk_src=`echo $packages | sed -e 's/,/.c pk_/g' -e 's/^/pk_/' -e 's/$/.c/'` +sim_pk_obj=`echo $sim_pk_src | sed -e 's/\.c/.o/g'` +if test x"$silent" != x"yes"; then + echo "Setting packages to $sim_pk_src, $sim_pk_obj" +fi])dnl +]) +AC_SUBST(sim_packages) + + +AC_DEFUN([SIM_AC_OPTION_REGPARM], +[ +AC_ARG_ENABLE(sim-regparm, +[ --enable-sim-regparm=nr-parm Pass parameters in registers instead of on the stack - x86/GCC specific.], +[case "${enableval}" in + 0*|1*|2*|3*|4*|5*|6*|7*|8*|9*) sim_regparm="-DWITH_REGPARM=${enableval}";; + no) sim_regparm="" ;; + yes) sim_regparm="-DWITH_REGPARM=3";; + *) AC_MSG_ERROR("Unknown value $enableval for --enable-sim-regparm"); sim_regparm="";; +esac +if test x"$silent" != x"yes" && test x"$sim_regparm" != x""; then + echo "Setting regparm flags = $sim_regparm" 6>&1 +fi],[sim_regparm=""])dnl +]) +AC_SUBST(sim_regparm) + + +AC_DEFUN([SIM_AC_OPTION_RESERVED_BITS], +[ +default_sim_reserved_bits="ifelse([$1],,1,[$1])" +AC_ARG_ENABLE(sim-reserved-bits, +[ --enable-sim-reserved-bits Specify whether to check reserved bits in instruction.], +[case "${enableval}" in + yes) sim_reserved_bits="-DWITH_RESERVED_BITS=1";; + no) sim_reserved_bits="-DWITH_RESERVED_BITS=0";; + *) AC_MSG_ERROR("--enable-sim-reserved-bits does not take a value"); sim_reserved_bits="";; +esac +if test x"$silent" != x"yes" && test x"$sim_reserved_bits" != x""; then + echo "Setting reserved flags = $sim_reserved_bits" 6>&1 +fi],[sim_reserved_bits="-DWITH_RESERVED_BITS=${default_sim_reserved_bits}"])dnl +]) +AC_SUBST(sim_reserved_bits) + + +AC_DEFUN([SIM_AC_OPTION_SMP], +[ +default_sim_smp="ifelse([$1],,5,[$1])" +AC_ARG_ENABLE(sim-smp, +[ --enable-sim-smp=n Specify number of processors to configure for (default ${default_sim_smp}).], +[case "${enableval}" in + yes) sim_smp="-DWITH_SMP=5" ; sim_igen_smp="-N 5";; + no) sim_smp="-DWITH_SMP=0" ; sim_igen_smp="-N 0";; + *) sim_smp="-DWITH_SMP=$enableval" ; sim_igen_smp="-N $enableval";; +esac +if test x"$silent" != x"yes" && test x"$sim_smp" != x""; then + echo "Setting smp flags = $sim_smp" 6>&1 +fi],[sim_smp="-DWITH_SMP=${default_sim_smp}" ; sim_igen_smp="-N ${default_sim_smp}" +if test x"$silent" != x"yes"; then + echo "Setting smp flags = $sim_smp" 6>&1 +fi])dnl +]) +AC_SUBST(sim_smp) + + +AC_DEFUN([SIM_AC_OPTION_STDCALL], +[ +AC_ARG_ENABLE(sim-stdcall, +[ --enable-sim-stdcall=type Use an alternative function call/return mechanism - x86/GCC specific.], +[case "${enableval}" in + no) sim_stdcall="" ;; + std*) sim_stdcall="-DWITH_STDCALL=1";; + yes) sim_stdcall="-DWITH_STDCALL=1";; + *) AC_MSG_ERROR("Unknown value $enableval for --enable-sim-stdcall"); sim_stdcall="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdcall" != x""; then + echo "Setting function call flags = $sim_stdcall" 6>&1 +fi],[sim_stdcall=""])dnl +]) +AC_SUBST(sim_stdcall) + + +AC_DEFUN([SIM_AC_OPTION_XOR_ENDIAN], +[ +default_sim_xor_endian="ifelse([$1],,8,[$1])" +AC_ARG_ENABLE(sim-xor-endian, +[ --enable-sim-xor-endian=n Specify number bytes involved in XOR bi-endian mode (default ${default_sim_xor_endian}).], +[case "${enableval}" in + yes) sim_xor_endian="-DWITH_XOR_ENDIAN=8";; + no) sim_xor_endian="-DWITH_XOR_ENDIAN=0";; + *) sim_xor_endian="-DWITH_XOR_ENDIAN=$enableval";; +esac +if test x"$silent" != x"yes" && test x"$sim_xor_endian" != x""; then + echo "Setting xor-endian flag = $sim_xor_endian" 6>&1 +fi],[sim_xor_endian="-DWITH_XOR_ENDIAN=${default_sim_xor_endian}"])dnl +]) +AC_SUBST(sim_xor_endian) + + +dnl --enable-build-warnings is for developers of the simulator. +dnl it enables extra GCC specific warnings. +AC_DEFUN([SIM_AC_OPTION_WARNINGS], +[ +# NOTE: Don't add -Wall or -Wunused, they both include +# -Wunused-parameter which reports bogus warnings. +# NOTE: If you add to this list, remember to update +# gdb/doc/gdbint.texinfo. +build_warnings="-Wimplicit -Wreturn-type -Wcomment -Wtrigraphs \ +-Wformat -Wparentheses -Wpointer-arith" +# GCC supports -Wuninitialized only with -O or -On, n != 0. +if test x${CFLAGS+set} = xset; then + case "${CFLAGS}" in + *"-O0"* ) ;; + *"-O"* ) + build_warnings="${build_warnings} -Wuninitialized" + ;; + esac +else + build_warnings="${build_warnings} -Wuninitialized" +fi +# Up for debate: -Wswitch -Wcomment -trigraphs -Wtrigraphs +# -Wunused-function -Wunused-label -Wunused-variable -Wunused-value +# -Wchar-subscripts -Wtraditional -Wshadow -Wcast-qual +# -Wcast-align -Wwrite-strings -Wconversion -Wstrict-prototypes +# -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls +# -Woverloaded-virtual -Winline -Werror" +AC_ARG_ENABLE(build-warnings, +[ --enable-build-warnings Enable build-time compiler warnings if gcc is used], +[case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting compiler warning flags = $build_warnings" 6>&1 +fi])dnl +AC_ARG_ENABLE(sim-build-warnings, +[ --enable-gdb-build-warnings Enable SIM specific build-time compiler warnings if gcc is used], +[case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting GDB specific compiler warning flags = $build_warnings" 6>&1 +fi])dnl +WARN_CFLAGS="" +WERROR_CFLAGS="" +if test "x${build_warnings}" != x -a "x$GCC" = xyes +then + AC_MSG_CHECKING(compiler warning flags) + # Separate out the -Werror flag as some files just cannot be + # compiled with it enabled. + for w in ${build_warnings}; do + case $w in + -Werr*) WERROR_CFLAGS=-Werror ;; + *) # Check that GCC accepts it + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $w" + AC_TRY_COMPILE([],[],WARN_CFLAGS="${WARN_CFLAGS} $w",) + CFLAGS="$saved_CFLAGS" + esac + done + AC_MSG_RESULT(${WARN_CFLAGS}${WERROR_CFLAGS}) +fi +]) +AC_SUBST(WARN_CFLAGS) +AC_SUBST(WERROR_CFLAGS) + + +dnl Generate the Makefile in a target specific directory. +dnl Substitutions aren't performed on the file in AC_SUBST_FILE, +dnl so this is a cover macro to tuck the details away of how we cope. +dnl We cope by having autoconf generate two files and then merge them into +dnl one afterwards. The two pieces of the common fragment are inserted into +dnl the target's fragment at the appropriate points. + +AC_DEFUN([SIM_AC_OUTPUT], +[ +AC_LINK_FILES($sim_link_files, $sim_link_links) +dnl Make @cgen_breaks@ non-null only if the sim uses CGEN. +cgen_breaks="" +if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then +cgen_breaks="break cgen_rtx_error"; +fi +AC_SUBST(cgen_breaks) +AC_CONFIG_FILES(Makefile.sim:Makefile.in) +AC_CONFIG_FILES(Make-common.sim:../common/Make-common.in) +AC_CONFIG_FILES(.gdbinit:../common/gdbinit.in) +AC_CONFIG_COMMANDS([Makefile], +[echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp +]) +AC_CONFIG_COMMANDS([stamp-h], [echo > stamp-h]) +AC_OUTPUT +]) + +sinclude(../../config/gettext-sister.m4) +sinclude(../../config/acx.m4) + +dnl --enable-cgen-maint support +AC_DEFUN([SIM_AC_OPTION_CGEN_MAINT], +[ +cgen_maint=no +dnl Default is to use one in build tree. +cgen=guile +cgendir='$(srcdir)/../../cgen' +dnl Having --enable-maintainer-mode take arguments is another way to go. +dnl ??? One can argue --with is more appropriate if one wants to specify +dnl a directory name, but what we're doing here is an enable/disable kind +dnl of thing and specifying both --enable and --with is klunky. +dnl If you reeely want this to be --with, go ahead and change it. +AC_ARG_ENABLE(cgen-maint, +[ --enable-cgen-maint[=DIR] build cgen generated files], +[case "${enableval}" in + yes) cgen_maint=yes ;; + no) cgen_maint=no ;; + *) + # argument is cgen install directory (not implemented yet). + # Having a `share' directory might be more appropriate for the .scm, + # .cpu, etc. files. + cgendir=${cgen_maint}/lib/cgen + cgen=guile + ;; +esac])dnl +dnl AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} != xno) +if test x${cgen_maint} != xno ; then + CGEN_MAINT='' +else + CGEN_MAINT='#' +fi +AC_SUBST(CGEN_MAINT) +AC_SUBST(cgendir) +AC_SUBST(cgen) +]) diff --git a/external/gpl3/gdb/dist/sim/common/callback.c b/external/gpl3/gdb/dist/sim/common/callback.c new file mode 100644 index 000000000000..9bc80197b06a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/callback.c @@ -0,0 +1,1160 @@ +/* Remote target callback routines. + Copyright 1995, 1996, 1997, 2000, 2002, 2003, 2004, 2007, 2008, 2009, 2010, + 2011 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* This file provides a standard way for targets to talk to the host OS + level. */ + +#ifdef HAVE_CONFIG_H +#include "cconfig.h" +#endif +#include "ansidecl.h" +#include +#include +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif +#ifdef HAVE_LIMITS_H +/* For PIPE_BUF. */ +#include +#endif +#include +#include +#include +#include +#include +#include "gdb/callback.h" +#include "targ-vals.h" +/* For xmalloc. */ +#include "libiberty.h" + +#ifdef HAVE_UNISTD_H +#include +#endif + +#ifndef PIPE_BUF +#define PIPE_BUF 512 +#endif + +/* ??? sim_cb_printf should be cb_printf, but until the callback support is + broken out of the simulator directory, these are here to not require + sim-utils.h. */ +void sim_cb_printf PARAMS ((host_callback *, const char *, ...)); +void sim_cb_eprintf PARAMS ((host_callback *, const char *, ...)); + +extern CB_TARGET_DEFS_MAP cb_init_syscall_map[]; +extern CB_TARGET_DEFS_MAP cb_init_errno_map[]; +extern CB_TARGET_DEFS_MAP cb_init_open_map[]; + +extern int system PARAMS ((const char *)); + +static int os_init PARAMS ((host_callback *)); +static int os_shutdown PARAMS ((host_callback *)); +static int os_unlink PARAMS ((host_callback *, const char *)); +static long os_time PARAMS ((host_callback *, long *)); +static int os_system PARAMS ((host_callback *, const char *)); +static int os_rename PARAMS ((host_callback *, const char *, const char *)); +static int os_write_stdout PARAMS ((host_callback *, const char *, int)); +static void os_flush_stdout PARAMS ((host_callback *)); +static int os_write_stderr PARAMS ((host_callback *, const char *, int)); +static void os_flush_stderr PARAMS ((host_callback *)); +static int os_write PARAMS ((host_callback *, int, const char *, int)); +static int os_read_stdin PARAMS ((host_callback *, char *, int)); +static int os_read PARAMS ((host_callback *, int, char *, int)); +static int os_open PARAMS ((host_callback *, const char *, int)); +static int os_lseek PARAMS ((host_callback *, int, long, int)); +static int os_isatty PARAMS ((host_callback *, int)); +static int os_get_errno PARAMS ((host_callback *)); +static int os_close PARAMS ((host_callback *, int)); +static void os_vprintf_filtered PARAMS ((host_callback *, const char *, va_list)); +static void os_evprintf_filtered PARAMS ((host_callback *, const char *, va_list)); +static void os_error PARAMS ((host_callback *, const char *, ...)) +#ifdef __GNUC__ + __attribute__ ((__noreturn__)) +#endif + ; +static int fdmap PARAMS ((host_callback *, int)); +static int fdbad PARAMS ((host_callback *, int)); +static int wrap PARAMS ((host_callback *, int)); + +/* Set the callback copy of errno from what we see now. */ + +static int +wrap (p, val) + host_callback *p; + int val; +{ + p->last_errno = errno; + return val; +} + +/* Make sure the FD provided is ok. If not, return non-zero + and set errno. */ + +static int +fdbad (p, fd) + host_callback *p; + int fd; +{ + if (fd < 0 || fd > MAX_CALLBACK_FDS || p->fd_buddy[fd] < 0) + { + p->last_errno = EBADF; + return -1; + } + return 0; +} + +static int +fdmap (p, fd) + host_callback *p; + int fd; +{ + return p->fdmap[fd]; +} + +static int +os_close (p, fd) + host_callback *p; + int fd; +{ + int result; + int i, next; + + result = fdbad (p, fd); + if (result) + return result; + /* If this file descripter has one or more buddies (originals / + duplicates from a dup), just remove it from the circular list. */ + for (i = fd; (next = p->fd_buddy[i]) != fd; ) + i = next; + if (fd != i) + p->fd_buddy[i] = p->fd_buddy[fd]; + else + { + if (p->ispipe[fd]) + { + int other = p->ispipe[fd]; + int reader, writer; + + if (other > 0) + { + /* Closing the read side. */ + reader = fd; + writer = other; + } + else + { + /* Closing the write side. */ + writer = fd; + reader = -other; + } + + /* If there was data in the buffer, make a last "now empty" + call, then deallocate data. */ + if (p->pipe_buffer[writer].buffer != NULL) + { + (*p->pipe_empty) (p, reader, writer); + free (p->pipe_buffer[writer].buffer); + p->pipe_buffer[writer].buffer = NULL; + } + + /* Clear pipe data for this side. */ + p->pipe_buffer[fd].size = 0; + p->ispipe[fd] = 0; + + /* If this was the first close, mark the other side as the + only remaining side. */ + if (fd != abs (other)) + p->ispipe[abs (other)] = -other; + p->fd_buddy[fd] = -1; + return 0; + } + + result = wrap (p, close (fdmap (p, fd))); + } + p->fd_buddy[fd] = -1; + + return result; +} + + +/* taken from gdb/util.c:notice_quit() - should be in a library */ + + +#if defined(__GO32__) || defined (_MSC_VER) +static int +os_poll_quit (p) + host_callback *p; +{ +#if defined(__GO32__) + int kbhit (); + int getkey (); + if (kbhit ()) + { + int k = getkey (); + if (k == 1) + { + return 1; + } + else if (k == 2) + { + return 1; + } + else + { + sim_cb_eprintf (p, "CTRL-A to quit, CTRL-B to quit harder\n"); + } + } +#endif +#if defined (_MSC_VER) + /* NB - this will not compile! */ + int k = win32pollquit(); + if (k == 1) + return 1; + else if (k == 2) + return 1; +#endif + return 0; +} +#else +#define os_poll_quit 0 +#endif /* defined(__GO32__) || defined(_MSC_VER) */ + +static int +os_get_errno (p) + host_callback *p; +{ + return cb_host_to_target_errno (p, p->last_errno); +} + + +static int +os_isatty (p, fd) + host_callback *p; + int fd; +{ + int result; + + result = fdbad (p, fd); + if (result) + return result; + result = wrap (p, isatty (fdmap (p, fd))); + + return result; +} + +static int +os_lseek (p, fd, off, way) + host_callback *p; + int fd; + long off; + int way; +{ + int result; + + result = fdbad (p, fd); + if (result) + return result; + result = wrap (p, lseek (fdmap (p, fd), off, way)); + return result; +} + +static int +os_open (p, name, flags) + host_callback *p; + const char *name; + int flags; +{ + int i; + for (i = 0; i < MAX_CALLBACK_FDS; i++) + { + if (p->fd_buddy[i] < 0) + { + int f = open (name, cb_target_to_host_open (p, flags), 0644); + if (f < 0) + { + p->last_errno = errno; + return f; + } + p->fd_buddy[i] = i; + p->fdmap[i] = f; + return i; + } + } + p->last_errno = EMFILE; + return -1; +} + +static int +os_read (p, fd, buf, len) + host_callback *p; + int fd; + char *buf; + int len; +{ + int result; + + result = fdbad (p, fd); + if (result) + return result; + if (p->ispipe[fd]) + { + int writer = p->ispipe[fd]; + + /* Can't read from the write-end. */ + if (writer < 0) + { + p->last_errno = EBADF; + return -1; + } + + /* Nothing to read if nothing is written. */ + if (p->pipe_buffer[writer].size == 0) + return 0; + + /* Truncate read request size to buffer size minus what's already + read. */ + if (len > p->pipe_buffer[writer].size - p->pipe_buffer[fd].size) + len = p->pipe_buffer[writer].size - p->pipe_buffer[fd].size; + + memcpy (buf, p->pipe_buffer[writer].buffer + p->pipe_buffer[fd].size, + len); + + /* Account for what we just read. */ + p->pipe_buffer[fd].size += len; + + /* If we've read everything, empty and deallocate the buffer and + signal buffer-empty to client. (This isn't expected to be a + hot path in the simulator, so we don't hold on to the buffer.) */ + if (p->pipe_buffer[fd].size == p->pipe_buffer[writer].size) + { + free (p->pipe_buffer[writer].buffer); + p->pipe_buffer[writer].buffer = NULL; + p->pipe_buffer[fd].size = 0; + p->pipe_buffer[writer].size = 0; + (*p->pipe_empty) (p, fd, writer); + } + + return len; + } + + result = wrap (p, read (fdmap (p, fd), buf, len)); + return result; +} + +static int +os_read_stdin (p, buf, len) + host_callback *p; + char *buf; + int len; +{ + return wrap (p, read (0, buf, len)); +} + +static int +os_write (p, fd, buf, len) + host_callback *p; + int fd; + const char *buf; + int len; +{ + int result; + int real_fd; + + result = fdbad (p, fd); + if (result) + return result; + + if (p->ispipe[fd]) + { + int reader = -p->ispipe[fd]; + + /* Can't write to the read-end. */ + if (reader < 0) + { + p->last_errno = EBADF; + return -1; + } + + /* Can't write to pipe with closed read end. + FIXME: We should send a SIGPIPE. */ + if (reader == fd) + { + p->last_errno = EPIPE; + return -1; + } + + /* As a sanity-check, we bail out it the buffered contents is much + larger than the size of the buffer on the host. We don't want + to run out of memory in the simulator due to a target program + bug if we can help it. Unfortunately, regarding the value that + reaches the simulated program, it's no use returning *less* + than the requested amount, because cb_syscall loops calling + this function until the whole amount is done. */ + if (p->pipe_buffer[fd].size + len > 10 * PIPE_BUF) + { + p->last_errno = EFBIG; + return -1; + } + + p->pipe_buffer[fd].buffer + = xrealloc (p->pipe_buffer[fd].buffer, p->pipe_buffer[fd].size + len); + memcpy (p->pipe_buffer[fd].buffer + p->pipe_buffer[fd].size, + buf, len); + p->pipe_buffer[fd].size += len; + + (*p->pipe_nonempty) (p, reader, fd); + return len; + } + + real_fd = fdmap (p, fd); + switch (real_fd) + { + default: + result = wrap (p, write (real_fd, buf, len)); + break; + case 1: + result = p->write_stdout (p, buf, len); + break; + case 2: + result = p->write_stderr (p, buf, len); + break; + } + return result; +} + +static int +os_write_stdout (p, buf, len) + host_callback *p ATTRIBUTE_UNUSED; + const char *buf; + int len; +{ + return fwrite (buf, 1, len, stdout); +} + +static void +os_flush_stdout (p) + host_callback *p ATTRIBUTE_UNUSED; +{ + fflush (stdout); +} + +static int +os_write_stderr (p, buf, len) + host_callback *p ATTRIBUTE_UNUSED; + const char *buf; + int len; +{ + return fwrite (buf, 1, len, stderr); +} + +static void +os_flush_stderr (p) + host_callback *p ATTRIBUTE_UNUSED; +{ + fflush (stderr); +} + +static int +os_rename (p, f1, f2) + host_callback *p; + const char *f1; + const char *f2; +{ + return wrap (p, rename (f1, f2)); +} + + +static int +os_system (p, s) + host_callback *p; + const char *s; +{ + return wrap (p, system (s)); +} + +static long +os_time (p, t) + host_callback *p; + long *t; +{ + return wrap (p, time (t)); +} + + +static int +os_unlink (p, f1) + host_callback *p; + const char *f1; +{ + return wrap (p, unlink (f1)); +} + +static int +os_stat (p, file, buf) + host_callback *p; + const char *file; + struct stat *buf; +{ + /* ??? There is an issue of when to translate to the target layout. + One could do that inside this function, or one could have the + caller do it. It's more flexible to let the caller do it, though + I'm not sure the flexibility will ever be useful. */ + return wrap (p, stat (file, buf)); +} + +static int +os_fstat (p, fd, buf) + host_callback *p; + int fd; + struct stat *buf; +{ + if (fdbad (p, fd)) + return -1; + + if (p->ispipe[fd]) + { +#if defined (HAVE_STRUCT_STAT_ST_ATIME) || defined (HAVE_STRUCT_STAT_ST_CTIME) || defined (HAVE_STRUCT_STAT_ST_MTIME) + time_t t = (*p->time) (p, NULL); +#endif + + /* We have to fake the struct stat contents, since the pipe is + made up in the simulator. */ + memset (buf, 0, sizeof (*buf)); + +#ifdef HAVE_STRUCT_STAT_ST_MODE + buf->st_mode = S_IFIFO; +#endif + + /* If more accurate tracking than current-time is needed (for + example, on GNU/Linux we get accurate numbers), the p->time + callback (which may be something other than os_time) should + happen for each read and write, and we'd need to keep track of + atime, ctime and mtime. */ +#ifdef HAVE_STRUCT_STAT_ST_ATIME + buf->st_atime = t; +#endif +#ifdef HAVE_STRUCT_STAT_ST_CTIME + buf->st_ctime = t; +#endif +#ifdef HAVE_STRUCT_STAT_ST_MTIME + buf->st_mtime = t; +#endif + return 0; + } + + /* ??? There is an issue of when to translate to the target layout. + One could do that inside this function, or one could have the + caller do it. It's more flexible to let the caller do it, though + I'm not sure the flexibility will ever be useful. */ + return wrap (p, fstat (fdmap (p, fd), buf)); +} + +static int +os_lstat (p, file, buf) + host_callback *p; + const char *file; + struct stat *buf; +{ + /* NOTE: hpn/2004-12-12: Same issue here as with os_fstat. */ +#ifdef HAVE_LSTAT + return wrap (p, lstat (file, buf)); +#else + return wrap (p, stat (file, buf)); +#endif +} + +static int +os_ftruncate (p, fd, len) + host_callback *p; + int fd; + long len; +{ + int result; + + result = fdbad (p, fd); + if (p->ispipe[fd]) + { + p->last_errno = EINVAL; + return -1; + } + if (result) + return result; +#ifdef HAVE_FTRUNCATE + result = wrap (p, ftruncate (fdmap (p, fd), len)); +#else + p->last_errno = EINVAL; + result = -1; +#endif + return result; +} + +static int +os_truncate (p, file, len) + host_callback *p; + const char *file; + long len; +{ +#ifdef HAVE_TRUNCATE + return wrap (p, truncate (file, len)); +#else + p->last_errno = EINVAL; + return -1; +#endif +} + +static int +os_pipe (p, filedes) + host_callback *p; + int *filedes; +{ + int i; + + /* We deliberately don't use fd 0. It's probably stdin anyway. */ + for (i = 1; i < MAX_CALLBACK_FDS; i++) + { + int j; + + if (p->fd_buddy[i] < 0) + for (j = i + 1; j < MAX_CALLBACK_FDS; j++) + if (p->fd_buddy[j] < 0) + { + /* Found two free fd:s. Set stat to allocated and mark + pipeness. */ + p->fd_buddy[i] = i; + p->fd_buddy[j] = j; + p->ispipe[i] = j; + p->ispipe[j] = -i; + filedes[0] = i; + filedes[1] = j; + + /* Poison the FD map to make bugs apparent. */ + p->fdmap[i] = -1; + p->fdmap[j] = -1; + return 0; + } + } + + p->last_errno = EMFILE; + return -1; +} + +/* Stub functions for pipe support. They should always be overridden in + targets using the pipe support, but that's up to the target. */ + +/* Called when the simulator says that the pipe at (reader, writer) is + now empty (so the writer should leave its waiting state). */ + +static void +os_pipe_empty (p, reader, writer) + host_callback *p; + int reader; + int writer; +{ +} + +/* Called when the simulator says the pipe at (reader, writer) is now + non-empty (so the writer should wait). */ + +static void +os_pipe_nonempty (p, reader, writer) + host_callback *p; + int reader; + int writer; +{ +} + +static int +os_shutdown (p) + host_callback *p; +{ + int i, next, j; + for (i = 0; i < MAX_CALLBACK_FDS; i++) + { + int do_close = 1; + + /* Zero out all pipe state. Don't call callbacks for non-empty + pipes; the target program has likely terminated at this point + or we're called at initialization time. */ + p->ispipe[i] = 0; + p->pipe_buffer[i].size = 0; + p->pipe_buffer[i].buffer = NULL; + + next = p->fd_buddy[i]; + if (next < 0) + continue; + do + { + j = next; + if (j == MAX_CALLBACK_FDS) + do_close = 0; + next = p->fd_buddy[j]; + p->fd_buddy[j] = -1; + /* At the initial call of os_init, we got -1, 0, 0, 0, ... */ + if (next < 0) + { + p->fd_buddy[i] = -1; + do_close = 0; + break; + } + } + while (j != i); + if (do_close) + close (p->fdmap[i]); + } + return 1; +} + +static int +os_init (p) + host_callback *p; +{ + int i; + + os_shutdown (p); + for (i = 0; i < 3; i++) + { + p->fdmap[i] = i; + p->fd_buddy[i] = i - 1; + } + p->fd_buddy[0] = MAX_CALLBACK_FDS; + p->fd_buddy[MAX_CALLBACK_FDS] = 2; + + p->syscall_map = cb_init_syscall_map; + p->errno_map = cb_init_errno_map; + p->open_map = cb_init_open_map; + + return 1; +} + +/* DEPRECATED */ + +/* VARARGS */ +static void +os_printf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, ...) +{ + va_list args; + va_start (args, format); + + vfprintf (stdout, format, args); + va_end (args); +} + +/* VARARGS */ +static void +os_vprintf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, va_list args) +{ + vprintf (format, args); +} + +/* VARARGS */ +static void +os_evprintf_filtered (host_callback *p ATTRIBUTE_UNUSED, const char *format, va_list args) +{ + vfprintf (stderr, format, args); +} + +/* VARARGS */ +static void +os_error (host_callback *p ATTRIBUTE_UNUSED, const char *format, ...) +{ + va_list args; + va_start (args, format); + + vfprintf (stderr, format, args); + fprintf (stderr, "\n"); + + va_end (args); + exit (1); +} + +host_callback default_callback = +{ + os_close, + os_get_errno, + os_isatty, + os_lseek, + os_open, + os_read, + os_read_stdin, + os_rename, + os_system, + os_time, + os_unlink, + os_write, + os_write_stdout, + os_flush_stdout, + os_write_stderr, + os_flush_stderr, + + os_stat, + os_fstat, + os_lstat, + + os_ftruncate, + os_truncate, + + os_pipe, + os_pipe_empty, + os_pipe_nonempty, + + os_poll_quit, + + os_shutdown, + os_init, + + os_printf_filtered, /* deprecated */ + + os_vprintf_filtered, + os_evprintf_filtered, + os_error, + + 0, /* last errno */ + + { 0, }, /* fdmap */ + { -1, }, /* fd_buddy */ + { 0, }, /* ispipe */ + { { 0, 0 }, }, /* pipe_buffer */ + + 0, /* syscall_map */ + 0, /* errno_map */ + 0, /* open_map */ + 0, /* signal_map */ + 0, /* stat_map */ + + /* Defaults expected to be overridden at initialization, where needed. */ + BFD_ENDIAN_UNKNOWN, /* target_endian */ + 4, /* target_sizeof_int */ + + HOST_CALLBACK_MAGIC, +}; + +/* Read in a file describing the target's system call values. + E.g. maybe someone will want to use something other than newlib. + This assumes that the basic system call recognition and value passing/ + returning is supported. So maybe some coding/recompilation will be + necessary, but not as much. + + If an error occurs, the existing mapping is not changed. */ + +CB_RC +cb_read_target_syscall_maps (cb, file) + host_callback *cb; + const char *file; +{ + CB_TARGET_DEFS_MAP *syscall_map, *errno_map, *open_map, *signal_map; + const char *stat_map; + FILE *f; + + if ((f = fopen (file, "r")) == NULL) + return CB_RC_ACCESS; + + /* ... read in and parse file ... */ + + fclose (f); + return CB_RC_NO_MEM; /* FIXME:wip */ + + /* Free storage allocated for any existing maps. */ + if (cb->syscall_map) + free (cb->syscall_map); + if (cb->errno_map) + free (cb->errno_map); + if (cb->open_map) + free (cb->open_map); + if (cb->signal_map) + free (cb->signal_map); + if (cb->stat_map) + free ((PTR) cb->stat_map); + + cb->syscall_map = syscall_map; + cb->errno_map = errno_map; + cb->open_map = open_map; + cb->signal_map = signal_map; + cb->stat_map = stat_map; + + return CB_RC_OK; +} + +/* Translate the target's version of a syscall number to the host's. + This isn't actually the host's version, rather a canonical form. + ??? Perhaps this should be renamed to ..._canon_syscall. */ + +int +cb_target_to_host_syscall (cb, target_val) + host_callback *cb; + int target_val; +{ + CB_TARGET_DEFS_MAP *m; + + for (m = &cb->syscall_map[0]; m->target_val != -1; ++m) + if (m->target_val == target_val) + return m->host_val; + + return -1; +} + +/* FIXME: sort tables if large. + Alternatively, an obvious improvement for errno conversion is + to machine generate a function with a large switch(). */ + +/* Translate the host's version of errno to the target's. */ + +int +cb_host_to_target_errno (cb, host_val) + host_callback *cb; + int host_val; +{ + CB_TARGET_DEFS_MAP *m; + + for (m = &cb->errno_map[0]; m->host_val; ++m) + if (m->host_val == host_val) + return m->target_val; + + /* ??? Which error to return in this case is up for grabs. + Note that some missing values may have standard alternatives. + For now return 0 and require caller to deal with it. */ + return 0; +} + +/* Given a set of target bitmasks for the open system call, + return the host equivalent. + Mapping open flag values is best done by looping so there's no need + to machine generate this function. */ + +int +cb_target_to_host_open (cb, target_val) + host_callback *cb; + int target_val; +{ + int host_val = 0; + CB_TARGET_DEFS_MAP *m; + + for (m = &cb->open_map[0]; m->host_val != -1; ++m) + { + switch (m->target_val) + { + /* O_RDONLY can be (and usually is) 0 which needs to be treated + specially. */ + case TARGET_O_RDONLY : + case TARGET_O_WRONLY : + case TARGET_O_RDWR : + if ((target_val & (TARGET_O_RDONLY | TARGET_O_WRONLY | TARGET_O_RDWR)) + == m->target_val) + host_val |= m->host_val; + /* Handle the host/target differentiating between binary and + text mode. Only one case is of importance */ +#if ! defined (TARGET_O_BINARY) && defined (O_BINARY) + host_val |= O_BINARY; +#endif + break; + default : + if ((m->target_val & target_val) == m->target_val) + host_val |= m->host_val; + break; + } + } + + return host_val; +} + +/* Utility for e.g. cb_host_to_target_stat to store values in the target's + stat struct. */ + +void +cb_store_target_endian (cb, p, size, val) + host_callback *cb; + char *p; + int size; + long val; /* ??? must be as big as target word size */ +{ + if (cb->target_endian == BFD_ENDIAN_BIG) + { + p += size; + while (size-- > 0) + { + *--p = val; + val >>= 8; + } + } + else + { + while (size-- > 0) + { + *p++ = val; + val >>= 8; + } + } +} + +/* Translate a host's stat struct into a target's. + If HS is NULL, just compute the length of the buffer required, + TS is ignored. + + The result is the size of the target's stat struct, + or zero if an error occurred during the translation. */ + +int +cb_host_to_target_stat (cb, hs, ts) + host_callback *cb; + const struct stat *hs; + PTR ts; +{ + const char *m = cb->stat_map; + char *p; + + if (hs == NULL) + ts = NULL; + p = ts; + + while (m) + { + char *q = strchr (m, ','); + int size; + + /* FIXME: Use sscanf? */ + if (q == NULL) + { + /* FIXME: print error message */ + return 0; + } + size = atoi (q + 1); + if (size == 0) + { + /* FIXME: print error message */ + return 0; + } + + if (hs != NULL) + { + if (0) + ; + /* Defined here to avoid emacs indigestion on a lone "else". */ +#undef ST_x +#define ST_x(FLD) \ + else if (strncmp (m, #FLD, q - m) == 0) \ + cb_store_target_endian (cb, p, size, hs->FLD) + +#ifdef HAVE_STRUCT_STAT_ST_DEV + ST_x (st_dev); +#endif +#ifdef HAVE_STRUCT_STAT_ST_INO + ST_x (st_ino); +#endif +#ifdef HAVE_STRUCT_STAT_ST_MODE + ST_x (st_mode); +#endif +#ifdef HAVE_STRUCT_STAT_ST_NLINK + ST_x (st_nlink); +#endif +#ifdef HAVE_STRUCT_STAT_ST_UID + ST_x (st_uid); +#endif +#ifdef HAVE_STRUCT_STAT_ST_GID + ST_x (st_gid); +#endif +#ifdef HAVE_STRUCT_STAT_ST_RDEV + ST_x (st_rdev); +#endif +#ifdef HAVE_STRUCT_STAT_ST_SIZE + ST_x (st_size); +#endif +#ifdef HAVE_STRUCT_STAT_ST_BLKSIZE + ST_x (st_blksize); +#endif +#ifdef HAVE_STRUCT_STAT_ST_BLOCKS + ST_x (st_blocks); +#endif +#ifdef HAVE_STRUCT_STAT_ST_ATIME + ST_x (st_atime); +#endif +#ifdef HAVE_STRUCT_STAT_ST_MTIME + ST_x (st_mtime); +#endif +#ifdef HAVE_STRUCT_STAT_ST_CTIME + ST_x (st_ctime); +#endif +#undef ST_x + /* FIXME:wip */ + else + /* Unsupported field, store 0. */ + cb_store_target_endian (cb, p, size, 0); + } + + p += size; + m = strchr (q, ':'); + if (m) + ++m; + } + + return p - (char *) ts; +} + +/* Cover functions to the vfprintf callbacks. + + ??? If one thinks of the callbacks as a subsystem onto itself [or part of + a larger "remote target subsystem"] with a well defined interface, then + one would think that the subsystem would provide these. However, until + one is allowed to create such a subsystem (with its own source tree + independent of any particular user), such a critter can't exist. Thus + these functions are here for the time being. */ + +void +sim_cb_printf (host_callback *p, const char *fmt, ...) +{ + va_list ap; + + va_start (ap, fmt); + p->vprintf_filtered (p, fmt, ap); + va_end (ap); +} + +void +sim_cb_eprintf (host_callback *p, const char *fmt, ...) +{ + va_list ap; + + va_start (ap, fmt); + p->evprintf_filtered (p, fmt, ap); + va_end (ap); +} + +int +cb_is_stdin (host_callback *cb, int fd) +{ + return fdbad (cb, fd) ? 0 : fdmap (cb, fd) == 0; +} + +int +cb_is_stdout (host_callback *cb, int fd) +{ + return fdbad (cb, fd) ? 0 : fdmap (cb, fd) == 1; +} + +int +cb_is_stderr (host_callback *cb, int fd) +{ + return fdbad (cb, fd) ? 0 : fdmap (cb, fd) == 2; +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-accfp.c b/external/gpl3/gdb/dist/sim/common/cgen-accfp.c new file mode 100644 index 000000000000..afbca6d582c1 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-accfp.c @@ -0,0 +1,706 @@ +/* Accurate fp support for CGEN-based simulators. + Copyright (C) 1999 Cygnus Solutions. + + This implemention assumes: + typedef USI SF; + typedef UDI DF; + + TODO: + - lazy encoding/decoding + - checking return code (say by callback) + - proper rounding +*/ + +#include "sim-main.h" +#include "sim-fpu.h" + +/* SF mode support */ + +static SF +addsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_add (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +subsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_sub (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +mulsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_mul (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +divsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_div (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +negsf (CGEN_FPU* fpu, SF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + status = sim_fpu_neg (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +abssf (CGEN_FPU* fpu, SF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + status = sim_fpu_abs (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +sqrtsf (CGEN_FPU* fpu, SF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + status = sim_fpu_sqrt (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +invsf (CGEN_FPU* fpu, SF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + status = sim_fpu_inv (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +minsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_min (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF +maxsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_max (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static CGEN_FP_CMP +cmpsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + + if (sim_fpu_is_nan (&op1) + || sim_fpu_is_nan (&op2)) + return FP_CMP_NAN; + + if (x < y) + return FP_CMP_LT; + if (x > y) + return FP_CMP_GT; + return FP_CMP_EQ; +} + +static int +eqsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_eq (&op1, &op2); +} + +static int +nesf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_ne (&op1, &op2); +} + +static int +ltsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_lt (&op1, &op2); +} + +static int +lesf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_le (&op1, &op2); +} + +static int +gtsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_gt (&op1, &op2); +} + +static int +gesf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + return sim_fpu_is_ge (&op1, &op2); +} + +static DF +fextsfdf (CGEN_FPU* fpu, int how UNUSED, SF x) +{ + sim_fpu op1; + unsigned64 res; + + sim_fpu_32to (&op1, x); + sim_fpu_to64 (&res, &op1); + + return res; +} + +static SF +ftruncdfsf (CGEN_FPU* fpu, int how UNUSED, DF x) +{ + sim_fpu op1; + unsigned32 res; + + sim_fpu_64to (&op1, x); + sim_fpu_to32 (&res, &op1); + + return res; +} + +static SF +floatsisf (CGEN_FPU* fpu, int how UNUSED, SI x) +{ + sim_fpu ans; + unsigned32 res; + + sim_fpu_i32to (&ans, x, sim_fpu_round_near); + sim_fpu_to32 (&res, &ans); + return res; +} + +static DF +floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x) +{ + sim_fpu ans; + unsigned64 res; + + sim_fpu_i32to (&ans, x, sim_fpu_round_near); + sim_fpu_to64 (&res, &ans); + return res; +} + +static SF +ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x) +{ + sim_fpu ans; + unsigned32 res; + + sim_fpu_u32to (&ans, x, sim_fpu_round_near); + sim_fpu_to32 (&res, &ans); + return res; +} + +static SI +fixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x) +{ + sim_fpu op1; + unsigned32 res; + + sim_fpu_32to (&op1, x); + sim_fpu_to32i (&res, &op1, sim_fpu_round_near); + return res; +} + +static SI +fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x) +{ + sim_fpu op1; + unsigned32 res; + + sim_fpu_64to (&op1, x); + sim_fpu_to32i (&res, &op1, sim_fpu_round_near); + return res; +} + +static USI +ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x) +{ + sim_fpu op1; + unsigned32 res; + + sim_fpu_32to (&op1, x); + sim_fpu_to32u (&res, &op1, sim_fpu_round_near); + return res; +} + +/* DF mode support */ + +static DF +adddf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_add (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +subdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_sub (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +muldf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_mul (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +divdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_div (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +negdf (CGEN_FPU* fpu, DF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + status = sim_fpu_neg (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +absdf (CGEN_FPU* fpu, DF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + status = sim_fpu_abs (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +sqrtdf (CGEN_FPU* fpu, DF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + status = sim_fpu_sqrt (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +invdf (CGEN_FPU* fpu, DF x) +{ + sim_fpu op1; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + status = sim_fpu_inv (&ans, &op1); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +mindf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_min (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static DF +maxdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_max (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64 (&res, &ans); + + return res; +} + +static CGEN_FP_CMP +cmpdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + + if (sim_fpu_is_nan (&op1) + || sim_fpu_is_nan (&op2)) + return FP_CMP_NAN; + + if (x < y) + return FP_CMP_LT; + if (x > y) + return FP_CMP_GT; + return FP_CMP_EQ; +} + +static int +eqdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_eq (&op1, &op2); +} + +static int +nedf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_ne (&op1, &op2); +} + +static int +ltdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_lt (&op1, &op2); +} + +static int +ledf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_le (&op1, &op2); +} + +static int +gtdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_gt (&op1, &op2); +} + +static int +gedf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + return sim_fpu_is_ge (&op1, &op2); +} + +/* Initialize FP_OPS to use accurate library. */ + +void +cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error) +{ + CGEN_FP_OPS* o; + + fpu->owner = cpu; + /* ??? small memory leak, not freed by sim_close */ + fpu->ops = (CGEN_FP_OPS*) xmalloc (sizeof (CGEN_FP_OPS)); + + o = fpu->ops; + memset (o, 0, sizeof (*o)); + + o->error = error; + + o->addsf = addsf; + o->subsf = subsf; + o->mulsf = mulsf; + o->divsf = divsf; + o->negsf = negsf; + o->abssf = abssf; + o->sqrtsf = sqrtsf; + o->invsf = invsf; + o->minsf = minsf; + o->maxsf = maxsf; + o->cmpsf = cmpsf; + o->eqsf = eqsf; + o->nesf = nesf; + o->ltsf = ltsf; + o->lesf = lesf; + o->gtsf = gtsf; + o->gesf = gesf; + + o->adddf = adddf; + o->subdf = subdf; + o->muldf = muldf; + o->divdf = divdf; + o->negdf = negdf; + o->absdf = absdf; + o->sqrtdf = sqrtdf; + o->invdf = invdf; + o->mindf = mindf; + o->maxdf = maxdf; + o->cmpdf = cmpdf; + o->eqdf = eqdf; + o->nedf = nedf; + o->ltdf = ltdf; + o->ledf = ledf; + o->gtdf = gtdf; + o->gedf = gedf; + o->fextsfdf = fextsfdf; + o->ftruncdfsf = ftruncdfsf; + o->floatsisf = floatsisf; + o->floatsidf = floatsidf; + o->ufloatsisf = ufloatsisf; + o->fixsfsi = fixsfsi; + o->fixdfsi = fixdfsi; + o->ufixsfsi = ufixsfsi; +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-cpu.h b/external/gpl3/gdb/dist/sim/common/cgen-cpu.h new file mode 100644 index 000000000000..08ebae54a430 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-cpu.h @@ -0,0 +1,106 @@ +/* Simulator header for cgen cpus. + Copyright (C) 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_CPU_H +#define CGEN_CPU_H + +/* Type of function that is ultimately called by sim_resume. */ +typedef void (ENGINE_FN) (SIM_CPU *); + +/* Type of function to do disassembly. */ +typedef void (CGEN_DISASSEMBLER) (SIM_CPU *, const CGEN_INSN *, + const ARGBUF *, IADDR pc_, char *buf_); + +/* Additional non-machine generated per-cpu data to go in SIM_CPU. + The member's name must be `cgen_cpu'. */ + +typedef struct { + /* Non-zero while cpu simulation is running. */ + int running_p; +#define CPU_RUNNING_P(cpu) ((cpu)->cgen_cpu.running_p) + + /* Instruction count. This is maintained even in fast mode to keep track + of simulator speed. */ + unsigned long insn_count; +#define CPU_INSN_COUNT(cpu) ((cpu)->cgen_cpu.insn_count) + + /* sim_resume handlers */ + ENGINE_FN *fast_engine_fn; +#define CPU_FAST_ENGINE_FN(cpu) ((cpu)->cgen_cpu.fast_engine_fn) + ENGINE_FN *full_engine_fn; +#define CPU_FULL_ENGINE_FN(cpu) ((cpu)->cgen_cpu.full_engine_fn) + + /* Maximum number of instructions per time slice. + When single stepping this is 1. If using the pbb model, this can be + more than 1. 0 means "as long as you want". */ + unsigned int max_slice_insns; +#define CPU_MAX_SLICE_INSNS(cpu) ((cpu)->cgen_cpu.max_slice_insns) + + /* Simulator's execution cache. + Allocate space for this even if not used as some simulators may have + one machine variant that uses the scache and another that doesn't and + we don't want members in this struct to move about. */ + CPU_SCACHE scache; + + /* Instruction descriptor table. */ + IDESC *idesc; +#define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc) + + /* Whether the read,write,semantic entries (function pointers or computed + goto labels) have been initialized or not. */ + int idesc_read_init_p; +#define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p) + int idesc_write_init_p; +#define CPU_IDESC_WRITE_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_write_init_p) + int idesc_sem_init_p; +#define CPU_IDESC_SEM_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_sem_init_p) + + /* Cpu descriptor table. + This is a CGEN created entity that contains the description file + turned into C code and tables for our use. */ + CGEN_CPU_DESC cpu_desc; +#define CPU_CPU_DESC(cpu) ((cpu)->cgen_cpu.cpu_desc) + + /* Function to fetch the insn data entry in the IDESC. */ + const CGEN_INSN * (*get_idata) (SIM_CPU *, int); +#define CPU_GET_IDATA(cpu) ((cpu)->cgen_cpu.get_idata) + + /* Floating point support. */ + CGEN_FPU fpu; +#define CGEN_CPU_FPU(cpu) (& (cpu)->cgen_cpu.fpu) + + /* Disassembler. */ + CGEN_DISASSEMBLER *disassembler; +#define CPU_DISASSEMBLER(cpu) ((cpu)->cgen_cpu.disassembler) + + /* Queued writes for parallel write-after support. */ + CGEN_WRITE_QUEUE write_queue; +#define CPU_WRITE_QUEUE(cpu) (& (cpu)->cgen_cpu.write_queue) + + /* Allow slop in size calcs for case where multiple cpu types are supported + and space for the specified cpu is malloc'd at run time. */ + double slop; +} CGEN_CPU; + +/* Shorthand macro for fetching registers. + CPU_CGEN_HW is defined in cpu.h. */ +#define CPU(x) (CPU_CGEN_HW (current_cpu)->x) + +#endif /* CGEN_CPU_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-defs.h b/external/gpl3/gdb/dist/sim/common/cgen-defs.h new file mode 100644 index 000000000000..19ff347f5eaa --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-defs.h @@ -0,0 +1,183 @@ +/* General Cpu tools GENerated simulator support. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_DEFS_H +#define CGEN_DEFS_H + +/* Compute number of longs required to hold N bits. */ +#define HOST_LONGS_FOR_BITS(n) \ + (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8) + +/* Forward decls. Defined in the machine generated files. */ + +/* This holds the contents of the extracted insn. + There are a few common entries (e.g. pc address), and then one big + union with an entry for each of the instruction formats. */ +typedef struct argbuf ARGBUF; + +/* ARGBUF accessors. */ +#define ARGBUF_ADDR(abuf) ((abuf)->addr) +#define ARGBUF_IDESC(abuf) ((abuf)->idesc) +#define ARGBUF_TRACE_P(abuf) ((abuf)->trace_p) +#define ARGBUF_PROFILE_P(abuf) ((abuf)->profile_p) + +/* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support. + At present there is nothing else, but it also provides a level of + abstraction. */ +typedef struct scache SCACHE; + +/* This is a union with one entry for each instruction format. + Each entry contains all of the non-constant inputs of the instruction + in the case of read-before-exec support, or all outputs of the instruction + in the case of write-after-exec support. */ +typedef struct parexec PAREXEC; + +/* An "Instruction DESCriptor". + This is the main handle on an instruction for the simulator. */ +typedef struct idesc IDESC; + +/* Engine support. + ??? This is here because it's needed before eng.h (built by genmloop.sh) + which is needed before cgen-engine.h and cpu.h. + ??? This depends on a cpu family specific type, IADDR, but no machine + generated headers will have been included yet. sim/common currently + requires the typedef of sim_cia in sim-main.h between the inclusion of + sim-basics.h and sim-base.h so this is no different. */ + +/* SEM_ARG is intended to hide whether or not the scache is in use from the + semantic routines. In reality for the with-extraction case it is always + an SCACHE * even when not using the SCACHE since there's no current win to + making it something else ("not using the SCACHE" is like having a cache + size of 1). + The without-extraction case still uses an ARGBUF: + - consistency with scache version + - still need to record which operands are written + This wouldn't be needed if modeling was done in the semantic routines + but this isn't as general as handling it outside of the semantic routines. + For example Shade allows calling user-supplied code before/after each + instruction and this is something that is being planned. + ??? There is still some clumsiness in how much of ARGBUF to use. */ +typedef SCACHE *SEM_ARG; + +/* instruction address + ??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB + case. The first element is the IADDR, the second element is the SCACHE *. + Haven't found the time yet to make this work, but it seemed a nicer approach + than the current br_cache stuff. */ +typedef IADDR PCADDR; + +/* Current instruction address, used by common. */ +typedef IADDR CIA; + +/* Semantic routines' version of the PC. */ +#if WITH_SCACHE_PBB +typedef SCACHE *SEM_PC; +#else +typedef IADDR SEM_PC; +#endif + +/* Kinds of branches. */ +typedef enum { + SEM_BRANCH_UNTAKEN, + /* Branch to an uncacheable address (e.g. j reg). */ + SEM_BRANCH_UNCACHEABLE, + /* Branch to a cacheable (fixed) address. */ + SEM_BRANCH_CACHEABLE +} SEM_BRANCH_TYPE; + +/* Virtual insn support. */ + +/* Opcode table for virtual insns (only used by the simulator). */ +extern const CGEN_INSN cgen_virtual_insn_table[]; + +/* -ve of indices of virtual insns in cgen_virtual_insn_table. */ +typedef enum { + VIRTUAL_INSN_X_INVALID = 0, + VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2, + VIRTUAL_INSN_X_BEGIN = -3, + VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5 +} CGEN_INSN_VIRTUAL_TYPE; + +/* Return non-zero if CGEN_INSN* INSN is a virtual insn. */ +#define CGEN_INSN_VIRTUAL_P(insn) \ + CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL) + +/* GNU C's "computed goto" facility is used to speed things up where + possible. These macros provide a portable way to use them. + Nesting of these switch statements is done by providing an extra argument + that distinguishes them. `N' can be a number or symbol. + Variable `labels_##N' must be initialized with the labels of each case. */ + +#ifdef __GNUC__ +#define SWITCH(N, X) goto *X; +#define CASE(N, X) case_##N##_##X +#define BREAK(N) goto end_switch_##N +#define DEFAULT(N) default_##N +#define ENDSWITCH(N) end_switch_##N:; +#else +#define SWITCH(N, X) switch (X) +#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */ +#define BREAK(N) break +#define DEFAULT(N) default +#define ENDSWITCH(N) +#endif + +/* Simulator state. */ + +/* Records simulator descriptor so utilities like @cpu@_dump_regs can be + called from gdb. */ +extern SIM_DESC current_state; + +/* Simulator state. */ + +/* CGEN_STATE contains additional state information not present in + sim_state_base. */ + +typedef struct cgen_state { + /* FIXME: Moved to sim_state_base. */ + /* argv, env */ + char **argv; +#define STATE_ARGV(s) ((s) -> cgen_state.argv) + /* FIXME: Move to sim_state_base. */ + char **envp; +#define STATE_ENVP(s) ((s) -> cgen_state.envp) + + /* Non-zero if no tracing or profiling is selected. */ + int run_fast_p; +#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p) +} CGEN_STATE; + +/* Various utilities. */ + +/* Called after sim_post_argv_init to do any cgen initialization. */ +extern void cgen_init (SIM_DESC); + +/* Return the name of an insn. */ +extern CPU_INSN_NAME_FN cgen_insn_name; + +/* Return the maximum number of extra bytes required for a sim_cpu struct. */ +/* ??? Ok, yes, this is less pretty than it should be. Give me a better + language [or suggest a better way]. */ +extern int cgen_cpu_max_extra_bytes (void); + +/* Target supplied routine to process an invalid instruction. */ +extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC); + +#endif /* CGEN_DEFS_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-engine.h b/external/gpl3/gdb/dist/sim/common/cgen-engine.h new file mode 100644 index 000000000000..eeab33b70e0e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-engine.h @@ -0,0 +1,435 @@ +/* Engine header for Cpu tools GENerated simulators. + Copyright (C) 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* This file is included by ${cpu}.h. + It needs CGEN_INSN_WORD which is defined by ${cpu}.h. + ??? A lot of this could be moved to genmloop.sh to be put in eng.h + and thus remove some conditional compilation. We'd still need + CGEN_INSN_WORD though. */ + +/* Semantic functions come in six versions on two axes: + fast/full-featured, and using one of the simple/scache/compilation engines. + A full featured simulator is always provided. --enable-sim-fast includes + support for fast execution by duplicating the semantic code but leaving + out all features like tracing and profiling. + Using the scache is selected with --enable-sim-scache. */ +/* FIXME: --enable-sim-fast not implemented yet. */ +/* FIXME: undecided how to handle WITH_SCACHE_PBB. */ + +/* There are several styles of engines, all generally supported by the + same code: + + WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching + WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis + !WITH_SCACHE - simple engine: fetch an insn, execute an insn + + The !WITH_SCACHE case can also be broken up into two flavours: + extract the fields of the insn into an ARGBUF struct, or defer the + extraction to the semantic handler. The former can be viewed as the + WITH_SCACHE case with a cache size of 1 (thus there's no need for a + WITH_EXTRACTION macro). The WITH_SCACHE case always extracts the fields + into an ARGBUF struct. */ + +#ifndef CGEN_ENGINE_H +#define CGEN_ENGINE_H + +/* Instruction field support macros. */ + +#define EXTRACT_MSB0_SINT(val, total, start, length) \ +(((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \ + >> ((sizeof (INT) * 8) - (length))) +#define EXTRACT_MSB0_UINT(val, total, start, length) \ +(((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \ + >> ((sizeof (UINT) * 8) - (length))) + +#define EXTRACT_LSB0_SINT(val, total, start, length) \ +(((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \ + >> ((sizeof (INT) * 8) - (length))) +#define EXTRACT_LSB0_UINT(val, total, start, length) \ +(((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \ + >> ((sizeof (UINT) * 8) - (length))) + +#define EXTRACT_MSB0_LGSINT(val, total, start, length) \ +(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \ + >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length))) +#define EXTRACT_MSB0_LGUINT(val, total, start, length) \ +(((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \ + >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length))) + +#define EXTRACT_LSB0_LGSINT(val, total, start, length) \ +(((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \ + >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length))) +#define EXTRACT_LSB0_LGUINT(val, total, start, length) \ +(((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \ + >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length))) + +/* Semantic routines. */ + +/* Type of the machine generated extraction fns. */ +/* ??? No longer used. */ +typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *); + +/* Type of the machine generated semantic fns. */ + +#if WITH_SCACHE + +/* Instruction fields are extracted into ARGBUF before calling the + semantic routine. */ +#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE +typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *); +#else +typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG); +#endif + +#else + +/* Result of semantic routines is a status indicator (wip). */ +typedef unsigned int SEM_STATUS; + +/* Instruction fields are extracted by the semantic routine. + ??? TODO: multi word insns. */ +#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE +typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD); +#else +typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD); +#endif + +#endif + +/* In the ARGBUF struct, a pointer to the semantic routine for the insn. */ + +union sem { +#if ! WITH_SEM_SWITCH_FULL + SEMANTIC_FN *sem_full; +#endif +#if ! WITH_SEM_SWITCH_FAST + SEMANTIC_FN *sem_fast; +#endif +#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST +#ifdef __GNUC__ + void *sem_case; +#else + int sem_case; +#endif +#endif +}; + +/* Set the appropriate semantic handler in ABUF. */ + +#if WITH_SEM_SWITCH_FULL +#ifdef __GNUC__ +#define SEM_SET_FULL_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0) +#else +#define SEM_SET_FULL_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_case = (idesc)->num; } while (0) +#endif +#else +#define SEM_SET_FULL_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0) +#endif + +#if WITH_SEM_SWITCH_FAST +#ifdef __GNUC__ +#define SEM_SET_FAST_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0) +#else +#define SEM_SET_FAST_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_case = (idesc)->num; } while (0) +#endif +#else +#define SEM_SET_FAST_CODE(abuf, idesc) \ + do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0) +#endif + +#define SEM_SET_CODE(abuf, idesc, fast_p) \ +do { \ + if (fast_p) \ + SEM_SET_FAST_CODE ((abuf), (idesc)); \ + else \ + SEM_SET_FULL_CODE ((abuf), (idesc)); \ +} while (0) + +/* Return non-zero if IDESC is a conditional or unconditional CTI. */ + +#define IDESC_CTI_P(idesc) \ + ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \ + & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \ + | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \ + != 0) + +/* Return non-zero if IDESC is a skip insn. */ + +#define IDESC_SKIP_P(idesc) \ + ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \ + & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \ + != 0) + +/* Return pointer to ARGBUF given ptr to SCACHE. */ +#define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf) + +#if WITH_SCACHE + +#define CIA_ADDR(cia) (cia) + +#if WITH_SCACHE_PBB + +/* Return the scache pointer of the current insn. */ +#define SEM_SEM_ARG(vpc, sc) (vpc) + +/* Return the virtual pc of the next insn to execute + (assuming this isn't a cti or the branch isn't taken). */ +#define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1) + +/* Update the instruction counter. */ +#define PBB_UPDATE_INSN_COUNT(cpu,sc) \ + (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count) + +/* Do not append a `;' to invocations of this. + npc,br_type are for communication between the cti insn and cti-chain. */ +#define SEM_BRANCH_INIT \ + IADDR npc = 0; /* assign a value for -Wall */ \ + SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN; + +/* SEM_IN_SWITCH is defined at the top of the mainloop.c files + generated by genmloop.sh. It exists so generated semantic code needn't + care whether it's being put in a switch or in a function. */ +#ifdef SEM_IN_SWITCH +#define SEM_BRANCH_FINI(pcvar) \ +do { \ + pbb_br_npc = npc; \ + pbb_br_type = br_type; \ +} while (0) +#else /* 1 semantic function per instruction */ +#define SEM_BRANCH_FINI(pcvar) \ +do { \ + CPU_PBB_BR_NPC (current_cpu) = npc; \ + CPU_PBB_BR_TYPE (current_cpu) = br_type; \ +} while (0) +#endif + +#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \ +do { \ + npc = (newval); \ + br_type = SEM_BRANCH_CACHEABLE; \ +} while (0) + +#define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \ +do { \ + npc = (newval); \ + br_type = SEM_BRANCH_UNCACHEABLE; \ +} while (0) + +#define SEM_SKIP_COMPILE(cpu, sc, skip) \ +do { \ + SEM_ARGBUF (sc) -> skip_count = (skip); \ +} while (0) + +#define SEM_SKIP_INSN(cpu, sc, vpcvar) \ +do { \ + (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \ +} while (0) + +#else /* ! WITH_SCACHE_PBB */ + +#define SEM_SEM_ARG(vpc, sc) (sc) + +#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len)) + +/* ??? May wish to move taken_p out of here and make it explicit. */ +#define SEM_BRANCH_INIT \ + int taken_p = 0; + +#ifndef TARGET_SEM_BRANCH_FINI +#define TARGET_SEM_BRANCH_FINI(pcvar, taken_p) +#endif +#define SEM_BRANCH_FINI(pcvar) \ + do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0) + +#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \ +do { \ + (pcvar) = (newval); \ + taken_p = 1; \ +} while (0) + +#define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \ +do { \ + (pcvar) = (newval); \ + taken_p = 1; \ +} while (0) + +#endif /* ! WITH_SCACHE_PBB */ + +#else /* ! WITH_SCACHE */ + +/* This is the "simple" engine case. */ + +#define CIA_ADDR(cia) (cia) + +#define SEM_SEM_ARG(vpc, sc) (sc) + +#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len)) + +#define SEM_BRANCH_INIT \ + int taken_p = 0; + +#define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \ +do { \ + (pcvar) = (newval); \ + taken_p = 1; \ +} while (0) + +#define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \ +do { \ + (pcvar) = (newval); \ + taken_p = 1; \ +} while (0) + +/* Finish off branch insns. + The target must define TARGET_SEM_BRANCH_FINI. + ??? This can probably go away when define-execute is finished. */ +#define SEM_BRANCH_FINI(pcvar, bool_attrs) \ + do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0) + +/* Finish off non-branch insns. + The target must define TARGET_SEM_NBRANCH_FINI. + ??? This can probably go away when define-execute is finished. */ +#define SEM_NBRANCH_FINI(pcvar, bool_attrs) \ + do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0) + +#endif /* ! WITH_SCACHE */ + +/* Instruction information. */ + +/* Sanity check, at most one of these may be true. */ +#if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1 +#error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true." +#endif + +/* Compile time computable instruction data. */ + +struct insn_sem { + /* The instruction type (a number that identifies each insn over the + entire architecture). */ + CGEN_INSN_TYPE type; + + /* Index in IDESC table. */ + int index; + + /* Semantic format number. */ + int sfmt; + +#if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY + /* Index in IDESC table of parallel handler. */ + int par_index; +#endif + +#if WITH_PARALLEL_READ + /* Index in IDESC table of read handler. */ + int read_index; +#endif + +#if WITH_PARALLEL_WRITE + /* Index in IDESC table of writeback handler. */ + int write_index; +#endif +}; + +/* Entry in semantic function table. + This information is copied to the insn descriptor table at run-time. */ + +struct sem_fn_desc { + /* Index in IDESC table. */ + int index; + + /* Function to perform the semantics of the insn. */ + SEMANTIC_FN *fn; +}; + +/* Run-time computed instruction descriptor. */ + +struct idesc { +#if WITH_SEM_SWITCH_FAST +#ifdef __GNUC__ + void *sem_fast_lab; +#else + /* nothing needed, switch's on `num' member */ +#endif +#else + SEMANTIC_FN *sem_fast; +#endif + +#if WITH_SEM_SWITCH_FULL +#ifdef __GNUC__ + void *sem_full_lab; +#else + /* nothing needed, switch's on `num' member */ +#endif +#else + SEMANTIC_FN *sem_full; +#endif + + /* Parallel support. */ +#if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE)) + /* Pointer to parallel handler if serial insn. + Pointer to readahead/writeback handler if parallel insn. */ + struct idesc *par_idesc; +#endif + + /* Instruction number (index in IDESC table, profile table). + Also used to switch on in non-gcc semantic switches. */ + int num; + + /* Semantic format id. */ + int sfmt; + + /* instruction data (name, attributes, size, etc.) */ + const CGEN_INSN *idata; + + /* instruction attributes, copied from `idata' for speed */ + const CGEN_INSN_ATTR_TYPE *attrs; + + /* instruction length in bytes, copied from `idata' for speed */ + int length; + + /* profiling/modelling support */ + const INSN_TIMING *timing; +}; + +/* Tracing/profiling. */ + +/* Return non-zero if a before/after handler is needed. + When tracing/profiling a selected range there's no need to slow + down simulation of the other insns (except to get more accurate data!). + + ??? May wish to profile all insns if doing insn tracing, or to + get more accurate cycle data. + + First test ANY_P so we avoid a potentially expensive HIT_P call + [if there are lots of address ranges]. */ + +#define PC_IN_TRACE_RANGE_P(cpu, pc) \ + (TRACE_ANY_P (cpu) \ + && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc))) +#define PC_IN_PROFILE_RANGE_P(cpu, pc) \ + (PROFILE_ANY_P (cpu) \ + && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc))) + +#endif /* CGEN_ENGINE_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-fpu.c b/external/gpl3/gdb/dist/sim/common/cgen-fpu.c new file mode 100644 index 000000000000..3a8d5199bea5 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-fpu.c @@ -0,0 +1,32 @@ +/* CGEN fpu support + Copyright (C) 1999 Cygnus Solutions. */ + +#include "sim-main.h" +#include "sim-fpu.h" + +/* Return boolean indicating if X is an snan. */ + +BI +cgen_sf_snan_p (CGEN_FPU* fpu, SF x) +{ + sim_fpu op1; + + sim_fpu_32to (&op1, x); + return sim_fpu_is_nan (&op1); +} + +BI +cgen_df_snan_p (CGEN_FPU* fpu, DF x) +{ + sim_fpu op1; + + sim_fpu_64to (&op1, x); + return sim_fpu_is_nan (&op1); +} + +/* No-op fpu error handler. */ + +void +cgen_fpu_ignore_errors (CGEN_FPU* fpu, int status) +{ +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-fpu.h b/external/gpl3/gdb/dist/sim/common/cgen-fpu.h new file mode 100644 index 000000000000..134b4d031c57 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-fpu.h @@ -0,0 +1,225 @@ +/* CGEN fpu support + Copyright (C) 1999 Cygnus Solutions. + Copyright (C) 2010 Doug Evans. */ + +#ifndef CGEN_FPU_H +#define CGEN_FPU_H + +/* Floating point support is a little more complicated. + We want to support using either host fp insns or an accurate fp library. + We also want to support easily added variants (e.g. modified ieee). + This is done by vectoring all calls through a table. */ + +typedef USI SF; +typedef UDI DF; +typedef struct { SI parts[3]; } XF; +typedef struct { SI parts[4]; } TF; + +#ifndef TARGET_EXT_FP_WORDS +#define TARGET_EXT_FP_WORDS 4 +#endif + +/* Supported floating point conversion kinds (rounding modes). + FIXME: The IEEE rounding modes need to be implemented. */ + +typedef enum { + FPCONV_DEFAULT = 0, + FPCONV_TIES_TO_EVEN = 1, + FPCONV_TIES_TO_AWAY = 2, + FPCONV_TOWARD_ZERO = 3, + FPCONV_TOWARD_POSITIVE = 4, + FPCONV_TOWARD_NEGATIVE = 5 +} CGEN_FPCONV_KIND; + +/* forward decl */ +typedef struct cgen_fp_ops CGEN_FP_OPS; + +/* Instance of an fpu. */ + +typedef struct { + /* Usually a pointer back to the SIM_CPU struct. */ + void* owner; + /* Pointer to ops struct, rather than copy of it, to avoid bloating + SIM_CPU struct. */ + CGEN_FP_OPS* ops; +} CGEN_FPU; + +/* result of cmp */ + +typedef enum { + /* ??? May wish to distinguish qnan/snan here. */ + FP_CMP_EQ, FP_CMP_LT, FP_CMP_GT, FP_CMP_NAN +} CGEN_FP_CMP; + +/* error handler */ + +typedef void (CGEN_FPU_ERROR_FN) (CGEN_FPU*, int); + +/* fpu operation table */ + +struct cgen_fp_ops { + + /* error (e.g. signalling nan) handler, supplied by owner */ + + CGEN_FPU_ERROR_FN *error; + + /* basic SF ops */ + + SF (*addsf) (CGEN_FPU*, SF, SF); + SF (*subsf) (CGEN_FPU*, SF, SF); + SF (*mulsf) (CGEN_FPU*, SF, SF); + SF (*divsf) (CGEN_FPU*, SF, SF); + SF (*negsf) (CGEN_FPU*, SF); + SF (*abssf) (CGEN_FPU*, SF); + SF (*sqrtsf) (CGEN_FPU*, SF); + SF (*invsf) (CGEN_FPU*, SF); + SF (*cossf) (CGEN_FPU*, SF); + SF (*sinsf) (CGEN_FPU*, SF); + SF (*minsf) (CGEN_FPU*, SF, SF); + SF (*maxsf) (CGEN_FPU*, SF, SF); + + /* ??? to be revisited */ + CGEN_FP_CMP (*cmpsf) (CGEN_FPU*, SF, SF); + int (*eqsf) (CGEN_FPU*, SF, SF); + int (*nesf) (CGEN_FPU*, SF, SF); + int (*ltsf) (CGEN_FPU*, SF, SF); + int (*lesf) (CGEN_FPU*, SF, SF); + int (*gtsf) (CGEN_FPU*, SF, SF); + int (*gesf) (CGEN_FPU*, SF, SF); + + /* basic DF ops */ + + DF (*adddf) (CGEN_FPU*, DF, DF); + DF (*subdf) (CGEN_FPU*, DF, DF); + DF (*muldf) (CGEN_FPU*, DF, DF); + DF (*divdf) (CGEN_FPU*, DF, DF); + DF (*negdf) (CGEN_FPU*, DF); + DF (*absdf) (CGEN_FPU*, DF); + DF (*sqrtdf) (CGEN_FPU*, DF); + DF (*invdf) (CGEN_FPU*, DF); + DF (*cosdf) (CGEN_FPU*, DF); + DF (*sindf) (CGEN_FPU*, DF); + DF (*mindf) (CGEN_FPU*, DF, DF); + DF (*maxdf) (CGEN_FPU*, DF, DF); + + /* ??? to be revisited */ + CGEN_FP_CMP (*cmpdf) (CGEN_FPU*, DF, DF); + int (*eqdf) (CGEN_FPU*, DF, DF); + int (*nedf) (CGEN_FPU*, DF, DF); + int (*ltdf) (CGEN_FPU*, DF, DF); + int (*ledf) (CGEN_FPU*, DF, DF); + int (*gtdf) (CGEN_FPU*, DF, DF); + int (*gedf) (CGEN_FPU*, DF, DF); + + /* SF/DF conversion ops */ + + DF (*fextsfdf) (CGEN_FPU*, int, SF); + SF (*ftruncdfsf) (CGEN_FPU*, int, DF); + + SF (*floatsisf) (CGEN_FPU*, int, SI); + SF (*floatdisf) (CGEN_FPU*, int, DI); + SF (*ufloatsisf) (CGEN_FPU*, int, USI); + SF (*ufloatdisf) (CGEN_FPU*, int, UDI); + + SI (*fixsfsi) (CGEN_FPU*, int, SF); + DI (*fixsfdi) (CGEN_FPU*, int, SF); + USI (*ufixsfsi) (CGEN_FPU*, int, SF); + UDI (*ufixsfdi) (CGEN_FPU*, int, SF); + + DF (*floatsidf) (CGEN_FPU*, int, SI); + DF (*floatdidf) (CGEN_FPU*, int, DI); + DF (*ufloatsidf) (CGEN_FPU*, int, USI); + DF (*ufloatdidf) (CGEN_FPU*, int, UDI); + + SI (*fixdfsi) (CGEN_FPU*, int, DF); + DI (*fixdfdi) (CGEN_FPU*, int, DF); + USI (*ufixdfsi) (CGEN_FPU*, int, DF); + UDI (*ufixdfdi) (CGEN_FPU*, int, DF); + + /* XF mode support (kept separate 'cus not always present) */ + + XF (*addxf) (CGEN_FPU*, XF, XF); + XF (*subxf) (CGEN_FPU*, XF, XF); + XF (*mulxf) (CGEN_FPU*, XF, XF); + XF (*divxf) (CGEN_FPU*, XF, XF); + XF (*negxf) (CGEN_FPU*, XF); + XF (*absxf) (CGEN_FPU*, XF); + XF (*sqrtxf) (CGEN_FPU*, XF); + XF (*invxf) (CGEN_FPU*, XF); + XF (*cosxf) (CGEN_FPU*, XF); + XF (*sinxf) (CGEN_FPU*, XF); + XF (*minxf) (CGEN_FPU*, XF, XF); + XF (*maxxf) (CGEN_FPU*, XF, XF); + + CGEN_FP_CMP (*cmpxf) (CGEN_FPU*, XF, XF); + int (*eqxf) (CGEN_FPU*, XF, XF); + int (*nexf) (CGEN_FPU*, XF, XF); + int (*ltxf) (CGEN_FPU*, XF, XF); + int (*lexf) (CGEN_FPU*, XF, XF); + int (*gtxf) (CGEN_FPU*, XF, XF); + int (*gexf) (CGEN_FPU*, XF, XF); + + XF (*extsfxf) (CGEN_FPU*, int, SF); + XF (*extdfxf) (CGEN_FPU*, int, DF); + SF (*truncxfsf) (CGEN_FPU*, int, XF); + DF (*truncxfdf) (CGEN_FPU*, int, XF); + + XF (*floatsixf) (CGEN_FPU*, int, SI); + XF (*floatdixf) (CGEN_FPU*, int, DI); + XF (*ufloatsixf) (CGEN_FPU*, int, USI); + XF (*ufloatdixf) (CGEN_FPU*, int, UDI); + + SI (*fixxfsi) (CGEN_FPU*, int, XF); + DI (*fixxfdi) (CGEN_FPU*, int, XF); + USI (*ufixxfsi) (CGEN_FPU*, int, XF); + UDI (*ufixxfdi) (CGEN_FPU*, int, XF); + + /* TF mode support (kept separate 'cus not always present) */ + + TF (*addtf) (CGEN_FPU*, TF, TF); + TF (*subtf) (CGEN_FPU*, TF, TF); + TF (*multf) (CGEN_FPU*, TF, TF); + TF (*divtf) (CGEN_FPU*, TF, TF); + TF (*negtf) (CGEN_FPU*, TF); + TF (*abstf) (CGEN_FPU*, TF); + TF (*sqrttf) (CGEN_FPU*, TF); + TF (*invtf) (CGEN_FPU*, TF); + TF (*costf) (CGEN_FPU*, TF); + TF (*sintf) (CGEN_FPU*, TF); + TF (*mintf) (CGEN_FPU*, TF, TF); + TF (*maxtf) (CGEN_FPU*, TF, TF); + + CGEN_FP_CMP (*cmptf) (CGEN_FPU*, TF, TF); + int (*eqtf) (CGEN_FPU*, TF, TF); + int (*netf) (CGEN_FPU*, TF, TF); + int (*lttf) (CGEN_FPU*, TF, TF); + int (*letf) (CGEN_FPU*, TF, TF); + int (*gttf) (CGEN_FPU*, TF, TF); + int (*getf) (CGEN_FPU*, TF, TF); + + TF (*extsftf) (CGEN_FPU*, int, SF); + TF (*extdftf) (CGEN_FPU*, int, DF); + SF (*trunctfsf) (CGEN_FPU*, int, TF); + DF (*trunctfdf) (CGEN_FPU*, int, TF); + + TF (*floatsitf) (CGEN_FPU*, int, SI); + TF (*floatditf) (CGEN_FPU*, int, DI); + TF (*ufloatsitf) (CGEN_FPU*, int, USI); + TF (*ufloatditf) (CGEN_FPU*, int, UDI); + + SI (*fixtfsi) (CGEN_FPU*, int, TF); + DI (*fixtfdi) (CGEN_FPU*, int, TF); + USI (*ufixtfsi) (CGEN_FPU*, int, TF); + UDI (*ufixtfdi) (CGEN_FPU*, int, TF); + +}; + +extern void cgen_init_accurate_fpu (SIM_CPU*, CGEN_FPU*, CGEN_FPU_ERROR_FN*); + +BI cgen_sf_snan_p (CGEN_FPU*, SF); +BI cgen_df_snan_p (CGEN_FPU*, DF); + +/* no-op fp error handler */ +extern CGEN_FPU_ERROR_FN cgen_fpu_ignore_errors; + +#endif /* CGEN_FPU_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-mem.h b/external/gpl3/gdb/dist/sim/common/cgen-mem.h new file mode 100644 index 000000000000..01cf33dbc94e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-mem.h @@ -0,0 +1,229 @@ +/* Memory ops header for CGEN-based simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_MEM_H +#define CGEN_MEM_H + +#ifdef MEMOPS_DEFINE_INLINE +#define MEMOPS_INLINE +#else +#define MEMOPS_INLINE extern inline +#endif + +/* Integer memory read support. + + There is no floating point support. In this context there are no + floating point modes, only floating point operations (whose arguments + and results are arrays of bits that we treat as integer modes). */ + +#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_GETMEM(mode, size) \ +MEMOPS_INLINE mode \ +XCONCAT2 (GETMEM,mode) (SIM_CPU *cpu, IADDR pc, ADDR a) \ +{ \ + PROFILE_COUNT_READ (cpu, a, XCONCAT2 (MODE_,mode)); \ + /* Don't read anything into "unaligned" here. Bad name choice. */\ + return XCONCAT2 (sim_core_read_unaligned_,size) (cpu, pc, read_map, a); \ +} +#else +#define DECLARE_GETMEM(mode, size) \ +extern mode XCONCAT2 (GETMEM,mode) (SIM_CPU *, IADDR, ADDR); +#endif + +DECLARE_GETMEM (QI, 1) /* TAGS: GETMEMQI */ +DECLARE_GETMEM (UQI, 1) /* TAGS: GETMEMUQI */ +DECLARE_GETMEM (HI, 2) /* TAGS: GETMEMHI */ +DECLARE_GETMEM (UHI, 2) /* TAGS: GETMEMUHI */ +DECLARE_GETMEM (SI, 4) /* TAGS: GETMEMSI */ +DECLARE_GETMEM (USI, 4) /* TAGS: GETMEMUSI */ +DECLARE_GETMEM (DI, 8) /* TAGS: GETMEMDI */ +DECLARE_GETMEM (UDI, 8) /* TAGS: GETMEMUDI */ + +#undef DECLARE_GETMEM + +/* Integer memory write support. */ + +#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_SETMEM(mode, size) \ +MEMOPS_INLINE void \ +XCONCAT2 (SETMEM,mode) (SIM_CPU *cpu, IADDR pc, ADDR a, mode val) \ +{ \ + PROFILE_COUNT_WRITE (cpu, a, XCONCAT2 (MODE_,mode)); \ + /* Don't read anything into "unaligned" here. Bad name choice. */ \ + XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \ +} +#else +#define DECLARE_SETMEM(mode, size) \ +extern void XCONCAT2 (SETMEM,mode) (SIM_CPU *, IADDR, ADDR, mode); +#endif + +DECLARE_SETMEM (QI, 1) /* TAGS: SETMEMQI */ +DECLARE_SETMEM (UQI, 1) /* TAGS: SETMEMUQI */ +DECLARE_SETMEM (HI, 2) /* TAGS: SETMEMHI */ +DECLARE_SETMEM (UHI, 2) /* TAGS: SETMEMUHI */ +DECLARE_SETMEM (SI, 4) /* TAGS: SETMEMSI */ +DECLARE_SETMEM (USI, 4) /* TAGS: SETMEMUSI */ +DECLARE_SETMEM (DI, 8) /* TAGS: SETMEMDI */ +DECLARE_SETMEM (UDI, 8) /* TAGS: SETMEMUDI */ + +#undef DECLARE_SETMEM + +/* Instruction read support. */ + +#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_GETIMEM(mode, size) \ +MEMOPS_INLINE mode \ +XCONCAT2 (GETIMEM,mode) (SIM_CPU *cpu, IADDR a) \ +{ \ + /*PROFILE_COUNT_READ (cpu, a, XCONCAT2 (MODE_,mode));*/ \ + /* Don't read anything into "unaligned" here. Bad name choice. */\ + return XCONCAT2 (sim_core_read_unaligned_,size) (cpu, a, exec_map, a); \ +} +#else +#define DECLARE_GETIMEM(mode, size) \ +extern mode XCONCAT2 (GETIMEM,mode) (SIM_CPU *, ADDR); +#endif + +DECLARE_GETIMEM (UQI, 1) /* TAGS: GETIMEMUQI */ +DECLARE_GETIMEM (UHI, 2) /* TAGS: GETIMEMUHI */ +DECLARE_GETIMEM (USI, 4) /* TAGS: GETIMEMUSI */ +DECLARE_GETIMEM (UDI, 8) /* TAGS: GETIMEMUDI */ + +#undef DECLARE_GETIMEM + +/* Floating point support. + + ??? One can specify that the integer memory ops should be used instead, + and treat fp values as just a series of bits. One might even bubble + that notion up into the description language. However, that departs from + gcc. One could cross over from gcc's notion and a "series of bits" notion + between there and here, and thus still not require these routines. However, + that's a complication of its own (not that having these fns isn't). + But for now, we do things this way. */ + +#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_GETMEM(mode, size) \ +MEMOPS_INLINE mode \ +XCONCAT2 (GETMEM,mode) (SIM_CPU *cpu, IADDR pc, ADDR a) \ +{ \ + PROFILE_COUNT_READ (cpu, a, XCONCAT2 (MODE_,mode)); \ + /* Don't read anything into "unaligned" here. Bad name choice. */\ + return XCONCAT2 (sim_core_read_unaligned_,size) (cpu, pc, read_map, a); \ +} +#else +#define DECLARE_GETMEM(mode, size) \ +extern mode XCONCAT2 (GETMEM,mode) (SIM_CPU *, IADDR, ADDR); +#endif + +DECLARE_GETMEM (SF, 4) /* TAGS: GETMEMSF */ +DECLARE_GETMEM (DF, 8) /* TAGS: GETMEMDF */ + +#undef DECLARE_GETMEM + +#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_SETMEM(mode, size) \ +MEMOPS_INLINE void \ +XCONCAT2 (SETMEM,mode) (SIM_CPU *cpu, IADDR pc, ADDR a, mode val) \ +{ \ + PROFILE_COUNT_WRITE (cpu, a, XCONCAT2 (MODE_,mode)); \ + /* Don't read anything into "unaligned" here. Bad name choice. */ \ + XCONCAT2 (sim_core_write_unaligned_,size) (cpu, pc, write_map, a, val); \ +} +#else +#define DECLARE_SETMEM(mode, size) \ +extern void XCONCAT2 (SETMEM,mode) (SIM_CPU *, IADDR, ADDR, mode); +#endif + +DECLARE_SETMEM (SF, 4) /* TAGS: SETMEMSF */ +DECLARE_SETMEM (DF, 8) /* TAGS: SETMEMDF */ + +#undef DECLARE_SETMEM + +/* GETT: translate target value at P to host value. + This needn't be very efficient (i.e. can call memcpy) as this is + only used when interfacing with the outside world (e.g. gdb). */ + +#if defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_GETT(mode, size) \ +mode \ +XCONCAT2 (GETT,mode) (unsigned char *p) \ +{ \ + mode tmp; \ + memcpy (&tmp, p, sizeof (mode)); \ + return XCONCAT2 (T2H_,size) (tmp); \ +} +#else +#define DECLARE_GETT(mode, size) \ +extern mode XCONCAT2 (GETT,mode) (unsigned char *); +#endif + +DECLARE_GETT (QI, 1) /* TAGS: GETTQI */ +DECLARE_GETT (UQI, 1) /* TAGS: GETTUQI */ +DECLARE_GETT (HI, 2) /* TAGS: GETTHI */ +DECLARE_GETT (UHI, 2) /* TAGS: GETTUHI */ +DECLARE_GETT (SI, 4) /* TAGS: GETTSI */ +DECLARE_GETT (USI, 4) /* TAGS: GETTUSI */ +DECLARE_GETT (DI, 8) /* TAGS: GETTDI */ +DECLARE_GETT (UDI, 8) /* TAGS: GETTUDI */ + +#if 0 /* ??? defered until necessary */ +DECLARE_GETT (SF, 4) /* TAGS: GETTSF */ +DECLARE_GETT (DF, 8) /* TAGS: GETTDF */ +DECLARE_GETT (TF, 16) /* TAGS: GETTTF */ +#endif + +#undef DECLARE_GETT + +/* SETT: translate host value to target value and store at P. + This needn't be very efficient (i.e. can call memcpy) as this is + only used when interfacing with the outside world (e.g. gdb). */ + +#if defined (MEMOPS_DEFINE_INLINE) +#define DECLARE_SETT(mode, size) \ +void \ +XCONCAT2 (SETT,mode) (unsigned char *buf, mode val) \ +{ \ + mode tmp; \ + tmp = XCONCAT2 (H2T_,size) (val); \ + memcpy (buf, &tmp, sizeof (mode)); \ +} +#else +#define DECLARE_SETT(mode, size) \ +extern mode XCONCAT2 (SETT,mode) (unsigned char *, mode); +#endif + +DECLARE_SETT (QI, 1) /* TAGS: SETTQI */ +DECLARE_SETT (UQI, 1) /* TAGS: SETTUQI */ +DECLARE_SETT (HI, 2) /* TAGS: SETTHI */ +DECLARE_SETT (UHI, 2) /* TAGS: SETTUHI */ +DECLARE_SETT (SI, 4) /* TAGS: SETTSI */ +DECLARE_SETT (USI, 4) /* TAGS: SETTUSI */ +DECLARE_SETT (DI, 8) /* TAGS: SETTDI */ +DECLARE_SETT (UDI, 8) /* TAGS: SETTUDI */ + +#if 0 /* ??? defered until necessary */ +DECLARE_SETT (SF, 4) /* TAGS: SETTSF */ +DECLARE_SETT (DF, 8) /* TAGS: SETTDF */ +DECLARE_SETT (TF, 16) /* TAGS: SETTTF */ +#endif + +#undef DECLARE_SETT + +#endif /* CGEN_MEM_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-ops.h b/external/gpl3/gdb/dist/sim/common/cgen-ops.h new file mode 100644 index 000000000000..ea694e9e901d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-ops.h @@ -0,0 +1,657 @@ +/* Semantics ops support for CGEN-based simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2002, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU Simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + +*/ + +#ifndef CGEN_SEM_OPS_H +#define CGEN_SEM_OPS_H + +#include + +#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE) +#define SEMOPS_DEFINE_INLINE +#define SEMOPS_INLINE extern inline +#else +#define SEMOPS_INLINE +#endif + +/* Semantic operations. + At one point this file was machine generated. Maybe it will be again. */ + +/* TODO: Lazy encoding/decoding of fp values. */ + +/* These don't really have a mode. */ +#define ANDIF(x, y) ((x) && (y)) +#define ORIF(x, y) ((x) || (y)) + +#define SUBBI(x, y) ((x) - (y)) +#define ANDBI(x, y) ((x) & (y)) +#define ORBI(x, y) ((x) | (y)) +#define XORBI(x, y) ((x) ^ (y)) +#define NEGBI(x) (- (x)) +#define NOTBI(x) (! (BI) (x)) +#define INVBI(x) (~ (x)) +#define EQBI(x, y) ((BI) (x) == (BI) (y)) +#define NEBI(x, y) ((BI) (x) != (BI) (y)) +#define LTBI(x, y) ((BI) (x) < (BI) (y)) +#define LEBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTBI(x, y) ((BI) (x) > (BI) (y)) +#define GEBI(x, y) ((BI) (x) >= (BI) (y)) +#define LTUBI(x, y) ((BI) (x) < (BI) (y)) +#define LEUBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTUBI(x, y) ((BI) (x) > (BI) (y)) +#define GEUBI(x, y) ((BI) (x) >= (BI) (y)) + +#define ADDQI(x, y) ((QI) ((UQI) (x) + (UQI) (y))) +#define SUBQI(x, y) ((QI) ((UQI) (x) - (UQI) (y))) +#define MULQI(x, y) ((QI) ((UQI) (x) * (UQI) (y))) +#define DIVQI(x, y) ((QI) (x) / (QI) (y)) +#define UDIVQI(x, y) ((UQI) (x) / (UQI) (y)) +#define MODQI(x, y) ((QI) (x) % (QI) (y)) +#define UMODQI(x, y) ((UQI) (x) % (UQI) (y)) +#define SRAQI(x, y) ((QI) (x) >> (y)) +#define SRLQI(x, y) ((UQI) (x) >> (y)) +#define SLLQI(x, y) ((UQI) (x) << (y)) +extern QI RORQI (QI, int); +extern QI ROLQI (QI, int); +#define ANDQI(x, y) ((x) & (y)) +#define ORQI(x, y) ((x) | (y)) +#define XORQI(x, y) ((x) ^ (y)) +#define NEGQI(x) ((QI) (- (UQI) (x))) +#define NOTQI(x) (! (QI) (x)) +#define INVQI(x) (~ (x)) +#define ABSQI(x) ((QI) ((QI) (x) < 0 ? -(UQI) (x) : (UQI) (x))) +#define EQQI(x, y) ((QI) (x) == (QI) (y)) +#define NEQI(x, y) ((QI) (x) != (QI) (y)) +#define LTQI(x, y) ((QI) (x) < (QI) (y)) +#define LEQI(x, y) ((QI) (x) <= (QI) (y)) +#define GTQI(x, y) ((QI) (x) > (QI) (y)) +#define GEQI(x, y) ((QI) (x) >= (QI) (y)) +#define LTUQI(x, y) ((UQI) (x) < (UQI) (y)) +#define LEUQI(x, y) ((UQI) (x) <= (UQI) (y)) +#define GTUQI(x, y) ((UQI) (x) > (UQI) (y)) +#define GEUQI(x, y) ((UQI) (x) >= (UQI) (y)) + +#define ADDHI(x, y) ((HI) ((UHI) (x) + (UHI) (y))) +#define SUBHI(x, y) ((HI) ((UHI) (x) - (UHI) (y))) +#define MULHI(x, y) ((HI) ((UHI) (x) * (UHI) (y))) +#define DIVHI(x, y) ((HI) (x) / (HI) (y)) +#define UDIVHI(x, y) ((UHI) (x) / (UHI) (y)) +#define MODHI(x, y) ((HI) (x) % (HI) (y)) +#define UMODHI(x, y) ((UHI) (x) % (UHI) (y)) +#define SRAHI(x, y) ((HI) (x) >> (y)) +#define SRLHI(x, y) ((UHI) (x) >> (y)) +#define SLLHI(x, y) ((UHI) (x) << (y)) +extern HI RORHI (HI, int); +extern HI ROLHI (HI, int); +#define ANDHI(x, y) ((x) & (y)) +#define ORHI(x, y) ((x) | (y)) +#define XORHI(x, y) ((x) ^ (y)) +#define NEGHI(x) ((HI) (- (UHI) (x))) +#define NOTHI(x) (! (HI) (x)) +#define INVHI(x) (~ (x)) +#define ABSHI(x) ((HI) ((HI) (x) < 0 ? -(UHI) (x) : (UHI) (x))) +#define EQHI(x, y) ((HI) (x) == (HI) (y)) +#define NEHI(x, y) ((HI) (x) != (HI) (y)) +#define LTHI(x, y) ((HI) (x) < (HI) (y)) +#define LEHI(x, y) ((HI) (x) <= (HI) (y)) +#define GTHI(x, y) ((HI) (x) > (HI) (y)) +#define GEHI(x, y) ((HI) (x) >= (HI) (y)) +#define LTUHI(x, y) ((UHI) (x) < (UHI) (y)) +#define LEUHI(x, y) ((UHI) (x) <= (UHI) (y)) +#define GTUHI(x, y) ((UHI) (x) > (UHI) (y)) +#define GEUHI(x, y) ((UHI) (x) >= (UHI) (y)) + +#define ADDSI(x, y) ((SI) ((USI) (x) + (USI) (y))) +#define SUBSI(x, y) ((SI) ((USI) (x) - (USI) (y))) +#define MULSI(x, y) ((SI) ((USI) (x) * (USI) (y))) +#define DIVSI(x, y) ((SI) (x) / (SI) (y)) +#define UDIVSI(x, y) ((USI) (x) / (USI) (y)) +#define MODSI(x, y) ((SI) (x) % (SI) (y)) +#define UMODSI(x, y) ((USI) (x) % (USI) (y)) +#define SRASI(x, y) ((SI) (x) >> (y)) +#define SRLSI(x, y) ((USI) (x) >> (y)) +#define SLLSI(x, y) ((USI) (x) << (y)) +extern SI RORSI (SI, int); +extern SI ROLSI (SI, int); +#define ANDSI(x, y) ((x) & (y)) +#define ORSI(x, y) ((x) | (y)) +#define XORSI(x, y) ((x) ^ (y)) +#define NEGSI(x) ((SI) (- (USI) (x))) +#define NOTSI(x) (! (SI) (x)) +#define INVSI(x) (~ (x)) +#define ABSSI(x) ((SI) ((SI) (x) < 0 ? -(USI) (x) : (USI) (x))) +#define EQSI(x, y) ((SI) (x) == (SI) (y)) +#define NESI(x, y) ((SI) (x) != (SI) (y)) +#define LTSI(x, y) ((SI) (x) < (SI) (y)) +#define LESI(x, y) ((SI) (x) <= (SI) (y)) +#define GTSI(x, y) ((SI) (x) > (SI) (y)) +#define GESI(x, y) ((SI) (x) >= (SI) (y)) +#define LTUSI(x, y) ((USI) (x) < (USI) (y)) +#define LEUSI(x, y) ((USI) (x) <= (USI) (y)) +#define GTUSI(x, y) ((USI) (x) > (USI) (y)) +#define GEUSI(x, y) ((USI) (x) >= (USI) (y)) + +#ifdef DI_FN_SUPPORT +extern DI ADDDI (DI, DI); +extern DI SUBDI (DI, DI); +extern DI MULDI (DI, DI); +extern DI DIVDI (DI, DI); +extern DI UDIVDI (DI, DI); +extern DI MODDI (DI, DI); +extern DI UMODDI (DI, DI); +extern DI SRADI (DI, int); +extern UDI SRLDI (UDI, int); +extern UDI SLLDI (UDI, int); +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +extern DI ANDDI (DI, DI); +extern DI ORDI (DI, DI); +extern DI XORDI (DI, DI); +extern DI NEGDI (DI); +extern int NOTDI (DI); +extern DI INVDI (DI); +extern int EQDI (DI, DI); +extern int NEDI (DI, DI); +extern int LTDI (DI, DI); +extern int LEDI (DI, DI); +extern int GTDI (DI, DI); +extern int GEDI (DI, DI); +extern int LTUDI (UDI, UDI); +extern int LEUDI (UDI, UDI); +extern int GTUDI (UDI, UDI); +extern int GEUDI (UDI, UDI); +#else /* ! DI_FN_SUPPORT */ +#define ADDDI(x, y) ((DI) ((UDI) (x) + (UDI) (y))) +#define SUBDI(x, y) ((DI) ((UDI) (x) - (UDI) (y))) +#define MULDI(x, y) ((DI) ((UDI) (x) * (UDI) (y))) +#define DIVDI(x, y) ((DI) (x) / (DI) (y)) +#define UDIVDI(x, y) ((UDI) (x) / (UDI) (y)) +#define MODDI(x, y) ((DI) (x) % (DI) (y)) +#define UMODDI(x, y) ((UDI) (x) % (UDI) (y)) +#define SRADI(x, y) ((DI) (x) >> (y)) +#define SRLDI(x, y) ((UDI) (x) >> (y)) +#define SLLDI(x, y) ((UDI) (x) << (y)) +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +#define ANDDI(x, y) ((x) & (y)) +#define ORDI(x, y) ((x) | (y)) +#define XORDI(x, y) ((x) ^ (y)) +#define NEGDI(x) ((DI) (- (UDI) (x))) +#define NOTDI(x) (! (DI) (x)) +#define INVDI(x) (~ (x)) +#define ABSDI(x) ((DI) ((DI) (x) < 0 ? -(UDI) (x) : (UDI) (x))) +#define EQDI(x, y) ((DI) (x) == (DI) (y)) +#define NEDI(x, y) ((DI) (x) != (DI) (y)) +#define LTDI(x, y) ((DI) (x) < (DI) (y)) +#define LEDI(x, y) ((DI) (x) <= (DI) (y)) +#define GTDI(x, y) ((DI) (x) > (DI) (y)) +#define GEDI(x, y) ((DI) (x) >= (DI) (y)) +#define LTUDI(x, y) ((UDI) (x) < (UDI) (y)) +#define LEUDI(x, y) ((UDI) (x) <= (UDI) (y)) +#define GTUDI(x, y) ((UDI) (x) > (UDI) (y)) +#define GEUDI(x, y) ((UDI) (x) >= (UDI) (y)) +#endif /* DI_FN_SUPPORT */ + +#define EXTBIQI(x) ((QI) (BI) (x)) +#define EXTBIHI(x) ((HI) (BI) (x)) +#define EXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTBIDI (BI); +#else +#define EXTBIDI(x) ((DI) (BI) (x)) +#endif +#define EXTQIHI(x) ((HI) (QI) (x)) +#define EXTQISI(x) ((SI) (QI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTQIDI (QI); +#else +#define EXTQIDI(x) ((DI) (QI) (x)) +#endif +#define EXTHIHI(x) ((HI) (HI) (x)) +#define EXTHISI(x) ((SI) (HI) (x)) +#define EXTSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTHIDI (HI); +#else +#define EXTHIDI(x) ((DI) (HI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI EXTSIDI (SI); +#else +#define EXTSIDI(x) ((DI) (SI) (x)) +#endif + +#define ZEXTBIQI(x) ((QI) (BI) (x)) +#define ZEXTBIHI(x) ((HI) (BI) (x)) +#define ZEXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTBIDI (BI); +#else +#define ZEXTBIDI(x) ((DI) (BI) (x)) +#endif +#define ZEXTQIHI(x) ((HI) (UQI) (x)) +#define ZEXTQISI(x) ((SI) (UQI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTQIDI (QI); +#else +#define ZEXTQIDI(x) ((DI) (UQI) (x)) +#endif +#define ZEXTHISI(x) ((SI) (UHI) (x)) +#define ZEXTHIHI(x) ((HI) (UHI) (x)) +#define ZEXTSISI(x) ((SI) (USI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTHIDI (HI); +#else +#define ZEXTHIDI(x) ((DI) (UHI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI ZEXTSIDI (SI); +#else +#define ZEXTSIDI(x) ((DI) (USI) (x)) +#endif + +#define TRUNCQIBI(x) ((BI) (QI) (x)) +#define TRUNCHIBI(x) ((BI) (HI) (x)) +#define TRUNCHIQI(x) ((QI) (HI) (x)) +#define TRUNCSIBI(x) ((BI) (SI) (x)) +#define TRUNCSIQI(x) ((QI) (SI) (x)) +#define TRUNCSIHI(x) ((HI) (SI) (x)) +#define TRUNCSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern BI TRUNCDIBI (DI); +#else +#define TRUNCDIBI(x) ((BI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern QI TRUNCDIQI (DI); +#else +#define TRUNCDIQI(x) ((QI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern HI TRUNCDIHI (DI); +#else +#define TRUNCDIHI(x) ((HI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern SI TRUNCDISI (DI); +#else +#define TRUNCDISI(x) ((SI) (DI) (x)) +#endif + +/* Composing/decomposing the various types. + Word ordering is endian-independent. Words are specified most to least + significant and word number 0 is the most significant word. + ??? May also wish an endian-dependent version. Later. */ + +#ifdef SEMOPS_DEFINE_INLINE + +SEMOPS_INLINE SF +SUBWORDSISF (SI in) +{ + union { SI in; SF out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE DF +SUBWORDDIDF (DI in) +{ + union { DI in; DF out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE QI +SUBWORDSIQI (SI in, int byte) +{ + assert (byte >= 0 && byte <= 3); + return (UQI) (in >> (8 * (3 - byte))) & 0xFF; +} + +SEMOPS_INLINE UQI +SUBWORDSIUQI (SI in, int byte) +{ + assert (byte >= 0 && byte <= 3); + return (UQI) (in >> (8 * (3 - byte))) & 0xFF; +} + +SEMOPS_INLINE QI +SUBWORDDIQI (DI in, int byte) +{ + assert (byte >= 0 && byte <= 7); + return (UQI) (in >> (8 * (7 - byte))) & 0xFF; +} + +SEMOPS_INLINE HI +SUBWORDDIHI (DI in, int word) +{ + assert (word >= 0 && word <= 3); + return (UHI) (in >> (16 * (3 - word))) & 0xFFFF; +} + +SEMOPS_INLINE HI +SUBWORDSIHI (SI in, int word) +{ + if (word == 0) + return (USI) in >> 16; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDSFSI (SF in) +{ + union { SF in; SI out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE DI +SUBWORDDFDI (DF in) +{ + union { DF in; DI out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE UQI +SUBWORDDIUQI (DI in, int byte) +{ + assert (byte >= 0 && byte <= 7); + return (UQI) (in >> (8 * (7 - byte))); +} + +SEMOPS_INLINE SI +SUBWORDDISI (DI in, int word) +{ + if (word == 0) + return (UDI) in >> 32; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDDFSI (DF in, int word) +{ + /* Note: typedef UDI DF; */ + if (word == 0) + return (UDI) in >> 32; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDXFSI (XF in, int word) +{ + /* Note: typedef struct { SI parts[3]; } XF; */ + union { XF in; SI out[3]; } x; + x.in = in; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + return x.out[word]; + else + return x.out[2 - word]; +} + +SEMOPS_INLINE SI +SUBWORDTFSI (TF in, int word) +{ + /* Note: typedef struct { SI parts[4]; } TF; */ + union { TF in; SI out[4]; } x; + x.in = in; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + return x.out[word]; + else + return x.out[3 - word]; +} + +SEMOPS_INLINE DI +JOINSIDI (SI x0, SI x1) +{ + return MAKEDI (x0, x1); +} + +SEMOPS_INLINE DF +JOINSIDF (SI x0, SI x1) +{ + union { SI in[2]; DF out; } x; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + x.in[0] = x0, x.in[1] = x1; + else + x.in[1] = x0, x.in[0] = x1; + return x.out; +} + +SEMOPS_INLINE XF +JOINSIXF (SI x0, SI x1, SI x2) +{ + union { SI in[3]; XF out; } x; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + x.in[0] = x0, x.in[1] = x1, x.in[2] = x2; + else + x.in[2] = x0, x.in[1] = x1, x.in[0] = x2; + return x.out; +} + +SEMOPS_INLINE TF +JOINSITF (SI x0, SI x1, SI x2, SI x3) +{ + union { SI in[4]; TF out; } x; + if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) + x.in[0] = x0, x.in[1] = x1, x.in[2] = x2, x.in[3] = x3; + else + x.in[3] = x0, x.in[2] = x1, x.in[1] = x2, x.in[0] = x3; + return x.out; +} + +#else + +QI SUBWORDSIQI (SI); +HI SUBWORDSIHI (HI); +SI SUBWORDSFSI (SF); +SF SUBWORDSISF (SI); +DI SUBWORDDFDI (DF); +DF SUBWORDDIDF (DI); +QI SUBWORDDIQI (DI, int); +HI SUBWORDDIHI (DI, int); +SI SUBWORDDISI (DI, int); +SI SUBWORDDFSI (DF, int); +SI SUBWORDXFSI (XF, int); +SI SUBWORDTFSI (TF, int); + +UQI SUBWORDSIUQI (SI); +UQI SUBWORDDIUQI (DI); + +DI JOINSIDI (SI, SI); +DF JOINSIDF (SI, SI); +XF JOINSIXF (SI, SI, SI); +TF JOINSITF (SI, SI, SI, SI); + +#endif /* SUBWORD,JOIN */ + +/* Semantic support utilities. */ + +#ifdef SEMOPS_DEFINE_INLINE + +SEMOPS_INLINE SI +ADDCSI (SI a, SI b, BI c) +{ + SI res = ADDSI (a, ADDSI (b, c)); + return res; +} + +SEMOPS_INLINE BI +ADDCFSI (SI a, SI b, BI c) +{ + SI tmp = ADDSI (a, ADDSI (b, c)); + BI res = ((USI) tmp < (USI) a) || (c && tmp == a); + return res; +} + +SEMOPS_INLINE BI +ADDOFSI (SI a, SI b, BI c) +{ + SI tmp = ADDSI (a, ADDSI (b, c)); + BI res = (((a < 0) == (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +SEMOPS_INLINE SI +SUBCSI (SI a, SI b, BI c) +{ + SI res = SUBSI (a, ADDSI (b, c)); + return res; +} + +SEMOPS_INLINE BI +SUBCFSI (SI a, SI b, BI c) +{ + BI res = ((USI) a < (USI) b) || (c && a == b); + return res; +} + +SEMOPS_INLINE BI +SUBOFSI (SI a, SI b, BI c) +{ + SI tmp = SUBSI (a, ADDSI (b, c)); + BI res = (((a < 0) != (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +SEMOPS_INLINE HI +ADDCHI (HI a, HI b, BI c) +{ + HI res = ADDHI (a, ADDHI (b, c)); + return res; +} + +SEMOPS_INLINE BI +ADDCFHI (HI a, HI b, BI c) +{ + HI tmp = ADDHI (a, ADDHI (b, c)); + BI res = ((UHI) tmp < (UHI) a) || (c && tmp == a); + return res; +} + +SEMOPS_INLINE BI +ADDOFHI (HI a, HI b, BI c) +{ + HI tmp = ADDHI (a, ADDHI (b, c)); + BI res = (((a < 0) == (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +SEMOPS_INLINE HI +SUBCHI (HI a, HI b, BI c) +{ + HI res = SUBHI (a, ADDHI (b, c)); + return res; +} + +SEMOPS_INLINE BI +SUBCFHI (HI a, HI b, BI c) +{ + BI res = ((UHI) a < (UHI) b) || (c && a == b); + return res; +} + +SEMOPS_INLINE BI +SUBOFHI (HI a, HI b, BI c) +{ + HI tmp = SUBHI (a, ADDHI (b, c)); + BI res = (((a < 0) != (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +SEMOPS_INLINE QI +ADDCQI (QI a, QI b, BI c) +{ + QI res = ADDQI (a, ADDQI (b, c)); + return res; +} + +SEMOPS_INLINE BI +ADDCFQI (QI a, QI b, BI c) +{ + QI tmp = ADDQI (a, ADDQI (b, c)); + BI res = ((UQI) tmp < (UQI) a) || (c && tmp == a); + return res; +} + +SEMOPS_INLINE BI +ADDOFQI (QI a, QI b, BI c) +{ + QI tmp = ADDQI (a, ADDQI (b, c)); + BI res = (((a < 0) == (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +SEMOPS_INLINE QI +SUBCQI (QI a, QI b, BI c) +{ + QI res = SUBQI (a, ADDQI (b, c)); + return res; +} + +SEMOPS_INLINE BI +SUBCFQI (QI a, QI b, BI c) +{ + BI res = ((UQI) a < (UQI) b) || (c && a == b); + return res; +} + +SEMOPS_INLINE BI +SUBOFQI (QI a, QI b, BI c) +{ + QI tmp = SUBQI (a, ADDQI (b, c)); + BI res = (((a < 0) != (b < 0)) + && ((a < 0) != (tmp < 0))); + return res; +} + +#else + +SI ADDCSI (SI, SI, BI); +UBI ADDCFSI (SI, SI, BI); +UBI ADDOFSI (SI, SI, BI); +SI SUBCSI (SI, SI, BI); +UBI SUBCFSI (SI, SI, BI); +UBI SUBOFSI (SI, SI, BI); +HI ADDCHI (HI, HI, BI); +UBI ADDCFHI (HI, HI, BI); +UBI ADDOFHI (HI, HI, BI); +HI SUBCHI (HI, HI, BI); +UBI SUBCFHI (HI, HI, BI); +UBI SUBOFHI (HI, HI, BI); +QI ADDCQI (QI, QI, BI); +UBI ADDCFQI (QI, QI, BI); +UBI ADDOFQI (QI, QI, BI); +QI SUBCQI (QI, QI, BI); +UBI SUBCFQI (QI, QI, BI); +UBI SUBOFQI (QI, QI, BI); + +#endif + +#endif /* CGEN_SEM_OPS_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-par.c b/external/gpl3/gdb/dist/sim/common/cgen-par.c new file mode 100644 index 000000000000..5ea0d3747595 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-par.c @@ -0,0 +1,490 @@ +/* Simulator parallel routines for CGEN simulators (and maybe others). + Copyright (C) 1999, 2000, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU instruction set simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-par.h" + +/* Functions required by the cgen interface. These functions add various + kinds of writes to the write queue. */ +void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_BI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.bi_write.target = target; + element->kinds.bi_write.value = value; +} + +void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_QI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.qi_write.target = target; + element->kinds.qi_write.value = value; +} + +void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.si_write.target = target; + element->kinds.si_write.value = value; +} + +void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_SF_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.sf_write.target = target; + element->kinds.sf_write.value = value; +} + +void sim_queue_pc_write (SIM_CPU *cpu, USI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_PC_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.pc_write.value = value; +} + +void sim_queue_fn_hi_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, UHI), + UINT regno, + UHI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_HI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_hi_write.function = write_function; + element->kinds.fn_hi_write.regno = regno; + element->kinds.fn_hi_write.value = value; +} + +void sim_queue_fn_si_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, USI), + UINT regno, + USI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_si_write.function = write_function; + element->kinds.fn_si_write.regno = regno; + element->kinds.fn_si_write.value = value; +} + +void sim_queue_fn_sf_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, SF), + UINT regno, + SF value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_SF_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_sf_write.function = write_function; + element->kinds.fn_sf_write.regno = regno; + element->kinds.fn_sf_write.value = value; +} + +void sim_queue_fn_di_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, DI), + UINT regno, + DI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_DI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_di_write.function = write_function; + element->kinds.fn_di_write.regno = regno; + element->kinds.fn_di_write.value = value; +} + +void sim_queue_fn_xi_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, SI *), + UINT regno, + SI *value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_XI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_xi_write.function = write_function; + element->kinds.fn_xi_write.regno = regno; + element->kinds.fn_xi_write.value[0] = value[0]; + element->kinds.fn_xi_write.value[1] = value[1]; + element->kinds.fn_xi_write.value[2] = value[2]; + element->kinds.fn_xi_write.value[3] = value[3]; +} + +void sim_queue_fn_df_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, UINT, DF), + UINT regno, + DF value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_DF_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_df_write.function = write_function; + element->kinds.fn_df_write.regno = regno; + element->kinds.fn_df_write.value = value; +} + +void sim_queue_fn_pc_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, USI), + USI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_PC_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_pc_write.function = write_function; + element->kinds.fn_pc_write.value = value; +} + +void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_QI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_qi_write.address = address; + element->kinds.mem_qi_write.value = value; +} + +void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_HI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_hi_write.address = address; + element->kinds.mem_hi_write.value = value; +} + +void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_si_write.address = address; + element->kinds.mem_si_write.value = value; +} + +void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_DI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_di_write.address = address; + element->kinds.mem_di_write.value = value; +} + +void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_DF_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_df_write.address = address; + element->kinds.mem_df_write.value = value; +} + +void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_MEM_XI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.mem_xi_write.address = address; + element->kinds.mem_xi_write.value[0] = value[0]; + element->kinds.mem_xi_write.value[1] = value[1]; + element->kinds.mem_xi_write.value[2] = value[2]; + element->kinds.mem_xi_write.value[3] = value[3]; +} + +void sim_queue_fn_mem_qi_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, QI), + SI address, + QI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_QI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_qi_write.function = write_function; + element->kinds.fn_mem_qi_write.address = address; + element->kinds.fn_mem_qi_write.value = value; +} + +void sim_queue_fn_mem_hi_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, HI), + SI address, + HI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_HI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_hi_write.function = write_function; + element->kinds.fn_mem_hi_write.address = address; + element->kinds.fn_mem_hi_write.value = value; +} + +void sim_queue_fn_mem_si_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI), + SI address, + SI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_SI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_si_write.function = write_function; + element->kinds.fn_mem_si_write.address = address; + element->kinds.fn_mem_si_write.value = value; +} + +void sim_queue_fn_mem_di_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, DI), + SI address, + DI value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_DI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_di_write.function = write_function; + element->kinds.fn_mem_di_write.address = address; + element->kinds.fn_mem_di_write.value = value; +} + +void sim_queue_fn_mem_df_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, DF), + SI address, + DF value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_DF_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_df_write.function = write_function; + element->kinds.fn_mem_df_write.address = address; + element->kinds.fn_mem_df_write.value = value; +} + +void sim_queue_fn_mem_xi_write ( + SIM_CPU *cpu, + void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI *), + SI address, + SI *value +) +{ + CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu); + CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q); + element->kind = CGEN_FN_MEM_XI_WRITE; + element->insn_address = CPU_PC_GET (cpu); + element->kinds.fn_mem_xi_write.function = write_function; + element->kinds.fn_mem_xi_write.address = address; + element->kinds.fn_mem_xi_write.value[0] = value[0]; + element->kinds.fn_mem_xi_write.value[1] = value[1]; + element->kinds.fn_mem_xi_write.value[2] = value[2]; + element->kinds.fn_mem_xi_write.value[3] = value[3]; +} + +/* Execute a write stored on the write queue. */ +void +cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item) +{ + IADDR pc; + switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item)) + { + case CGEN_BI_WRITE: + *item->kinds.bi_write.target = item->kinds.bi_write.value; + break; + case CGEN_QI_WRITE: + *item->kinds.qi_write.target = item->kinds.qi_write.value; + break; + case CGEN_SI_WRITE: + *item->kinds.si_write.target = item->kinds.si_write.value; + break; + case CGEN_SF_WRITE: + *item->kinds.sf_write.target = item->kinds.sf_write.value; + break; + case CGEN_PC_WRITE: + CPU_PC_SET (cpu, item->kinds.pc_write.value); + break; + case CGEN_FN_HI_WRITE: + item->kinds.fn_hi_write.function (cpu, + item->kinds.fn_hi_write.regno, + item->kinds.fn_hi_write.value); + break; + case CGEN_FN_SI_WRITE: + item->kinds.fn_si_write.function (cpu, + item->kinds.fn_si_write.regno, + item->kinds.fn_si_write.value); + break; + case CGEN_FN_SF_WRITE: + item->kinds.fn_sf_write.function (cpu, + item->kinds.fn_sf_write.regno, + item->kinds.fn_sf_write.value); + break; + case CGEN_FN_DI_WRITE: + item->kinds.fn_di_write.function (cpu, + item->kinds.fn_di_write.regno, + item->kinds.fn_di_write.value); + break; + case CGEN_FN_DF_WRITE: + item->kinds.fn_df_write.function (cpu, + item->kinds.fn_df_write.regno, + item->kinds.fn_df_write.value); + break; + case CGEN_FN_XI_WRITE: + item->kinds.fn_xi_write.function (cpu, + item->kinds.fn_xi_write.regno, + item->kinds.fn_xi_write.value); + break; + case CGEN_FN_PC_WRITE: + item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value); + break; + case CGEN_MEM_QI_WRITE: + pc = item->insn_address; + SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address, + item->kinds.mem_qi_write.value); + break; + case CGEN_MEM_HI_WRITE: + pc = item->insn_address; + SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address, + item->kinds.mem_hi_write.value); + break; + case CGEN_MEM_SI_WRITE: + pc = item->insn_address; + SETMEMSI (cpu, pc, item->kinds.mem_si_write.address, + item->kinds.mem_si_write.value); + break; + case CGEN_MEM_DI_WRITE: + pc = item->insn_address; + SETMEMDI (cpu, pc, item->kinds.mem_di_write.address, + item->kinds.mem_di_write.value); + break; + case CGEN_MEM_DF_WRITE: + pc = item->insn_address; + SETMEMDF (cpu, pc, item->kinds.mem_df_write.address, + item->kinds.mem_df_write.value); + break; + case CGEN_MEM_XI_WRITE: + pc = item->insn_address; + SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address, + item->kinds.mem_xi_write.value[0]); + SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4, + item->kinds.mem_xi_write.value[1]); + SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8, + item->kinds.mem_xi_write.value[2]); + SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12, + item->kinds.mem_xi_write.value[3]); + break; + case CGEN_FN_MEM_QI_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_qi_write.function (cpu, pc, + item->kinds.fn_mem_qi_write.address, + item->kinds.fn_mem_qi_write.value); + break; + case CGEN_FN_MEM_HI_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_hi_write.function (cpu, pc, + item->kinds.fn_mem_hi_write.address, + item->kinds.fn_mem_hi_write.value); + break; + case CGEN_FN_MEM_SI_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_si_write.function (cpu, pc, + item->kinds.fn_mem_si_write.address, + item->kinds.fn_mem_si_write.value); + break; + case CGEN_FN_MEM_DI_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_di_write.function (cpu, pc, + item->kinds.fn_mem_di_write.address, + item->kinds.fn_mem_di_write.value); + break; + case CGEN_FN_MEM_DF_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_df_write.function (cpu, pc, + item->kinds.fn_mem_df_write.address, + item->kinds.fn_mem_df_write.value); + break; + case CGEN_FN_MEM_XI_WRITE: + pc = item->insn_address; + item->kinds.fn_mem_xi_write.function (cpu, pc, + item->kinds.fn_mem_xi_write.address, + item->kinds.fn_mem_xi_write.value); + break; + default: + abort (); + break; /* FIXME: for now....print message later. */ + } +} + +/* Utilities for the write queue. */ +CGEN_WRITE_QUEUE_ELEMENT * +cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q) +{ + abort (); /* FIXME: for now....print message later. */ + return 0; +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-par.h b/external/gpl3/gdb/dist/sim/common/cgen-par.h new file mode 100644 index 000000000000..157aa8b09edb --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-par.h @@ -0,0 +1,215 @@ +/* Simulator header for cgen parallel support. + Copyright (C) 1999, 2000, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of the GNU instruction set simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_PAR_H +#define CGEN_PAR_H + +/* Kinds of writes stored on the write queue. */ +enum cgen_write_queue_kind { + CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE, + CGEN_PC_WRITE, + CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE, + CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE, + CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE, + CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE, + CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE, + CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, + CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE, + CGEN_NUM_WRITE_KINDS +}; + +/* Element of the write queue. */ +typedef struct { + enum cgen_write_queue_kind kind; /* Used to select union member below. */ + IADDR insn_address; /* Address of the insn performing the write. */ + unsigned32 flags; /* Target specific flags. */ + long word1; /* Target specific field. */ + union { + struct { + BI *target; + BI value; + } bi_write; + struct { + UQI *target; + QI value; + } qi_write; + struct { + SI *target; + SI value; + } si_write; + struct { + SI *target; + SF value; + } sf_write; + struct { + USI value; + } pc_write; + struct { + UINT regno; + UHI value; + void (*function)(SIM_CPU *, UINT, UHI); + } fn_hi_write; + struct { + UINT regno; + SI value; + void (*function)(SIM_CPU *, UINT, USI); + } fn_si_write; + struct { + UINT regno; + SF value; + void (*function)(SIM_CPU *, UINT, SF); + } fn_sf_write; + struct { + UINT regno; + DI value; + void (*function)(SIM_CPU *, UINT, DI); + } fn_di_write; + struct { + UINT regno; + DF value; + void (*function)(SIM_CPU *, UINT, DF); + } fn_df_write; + struct { + UINT regno; + SI value[4]; + void (*function)(SIM_CPU *, UINT, SI *); + } fn_xi_write; + struct { + USI value; + void (*function)(SIM_CPU *, USI); + } fn_pc_write; + struct { + SI address; + QI value; + } mem_qi_write; + struct { + SI address; + HI value; + } mem_hi_write; + struct { + SI address; + SI value; + } mem_si_write; + struct { + SI address; + DI value; + } mem_di_write; + struct { + SI address; + DF value; + } mem_df_write; + struct { + SI address; + SI value[4]; + } mem_xi_write; + struct { + SI address; + QI value; + void (*function)(SIM_CPU *, IADDR, SI, QI); + } fn_mem_qi_write; + struct { + SI address; + HI value; + void (*function)(SIM_CPU *, IADDR, SI, HI); + } fn_mem_hi_write; + struct { + SI address; + SI value; + void (*function)(SIM_CPU *, IADDR, SI, SI); + } fn_mem_si_write; + struct { + SI address; + DI value; + void (*function)(SIM_CPU *, IADDR, SI, DI); + } fn_mem_di_write; + struct { + SI address; + DF value; + void (*function)(SIM_CPU *, IADDR, SI, DF); + } fn_mem_df_write; + struct { + SI address; + SI value[4]; + void (*function)(SIM_CPU *, IADDR, SI, SI *); + } fn_mem_xi_write; + } kinds; +} CGEN_WRITE_QUEUE_ELEMENT; + +#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind) +#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address) +#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags) +#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1) + +extern void cgen_write_queue_element_execute ( + SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT * +); + +/* Instance of the queue for parallel write-after support. */ +/* FIXME: Should be dynamic? */ +#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */ + +typedef struct { + int index; + CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE]; +} CGEN_WRITE_QUEUE; + +#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0) +#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index) +#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)]) + +#define CGEN_WRITE_QUEUE_NEXT(queue) ( \ + (queue)->index < CGEN_WRITE_QUEUE_SIZE \ + ? &(queue)->q[(queue)->index++] \ + : cgen_write_queue_overflow (queue) \ +) + +extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *); + +/* Functions for queuing writes. Used by semantic code. */ +extern void sim_queue_bi_write (SIM_CPU *, BI *, BI); +extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI); +extern void sim_queue_si_write (SIM_CPU *, SI *, SI); +extern void sim_queue_sf_write (SIM_CPU *, SI *, SF); + +extern void sim_queue_pc_write (SIM_CPU *, USI); + +extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI); +extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI); +extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF); +extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI); +extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF); +extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *); +extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI); + +extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI); +extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI); +extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI); +extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI); +extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF); +extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *); + +extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI); +extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI); +extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI); +extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI); +extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF); +extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *); + +#endif /* CGEN_PAR_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-run.c b/external/gpl3/gdb/dist/sim/common/cgen-run.c new file mode 100644 index 000000000000..a010d7410567 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-run.c @@ -0,0 +1,237 @@ +/* Main simulator loop for CGEN-based simulators. + Copyright (C) 1998, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* ??? These are old notes, kept around for now. + Collecting profile data and tracing slow us down so we don't do them in + "fast mode". + There are 6 possibilities on 2 axes: + - no-scaching, insn-scaching, basic-block-scaching + - run with full features or run fast + Supporting all six possibilities in one executable is a bit much but + supporting full/fast seems reasonable. + If the scache is configured in it is always used. + If pbb-scaching is configured in it is always used. + ??? Sometimes supporting more than one set of semantic functions will make + the simulator too large - this should be configurable. Blah blah blah. + ??? Supporting full/fast can be more modular, blah blah blah. + When the framework is more modular, this can be. +*/ + +#include "sim-main.h" +#include "sim-assert.h" + +#ifndef SIM_ENGINE_PREFIX_HOOK +#define SIM_ENGINE_PREFIX_HOOK(sd) +#endif +#ifndef SIM_ENGINE_POSTFIX_HOOK +#define SIM_ENGINE_POSTFIX_HOOK(sd) +#endif + +static sim_event_handler has_stepped; +static void prime_cpu (SIM_CPU *, int); +static void engine_run_1 (SIM_DESC, int, int); +static void engine_run_n (SIM_DESC, int, int, int, int); + +/* sim_resume for cgen */ + +void +sim_resume (SIM_DESC sd, int step, int siggnal) +{ + sim_engine *engine = STATE_ENGINE (sd); + jmp_buf buf; + int jmpval; + + ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + + /* we only want to be single stepping the simulator once */ + if (engine->stepper != NULL) + { + sim_events_deschedule (sd, engine->stepper); + engine->stepper = NULL; + } + if (step) + engine->stepper = sim_events_schedule (sd, 1, has_stepped, sd); + + sim_module_resume (sd); + +#if WITH_SCACHE + if (USING_SCACHE_P (sd)) + scache_flush (sd); +#endif + + /* run/resume the simulator */ + + sim_engine_set_run_state (sd, sim_running, 0); + + engine->jmpbuf = &buf; + jmpval = setjmp (buf); + if (jmpval == sim_engine_start_jmpval + || jmpval == sim_engine_restart_jmpval) + { + int last_cpu_nr = sim_engine_last_cpu_nr (sd); + int next_cpu_nr = sim_engine_next_cpu_nr (sd); + int nr_cpus = sim_engine_nr_cpus (sd); + /* ??? Setting max_insns to 0 allows pbb/jit code to run wild and is + useful if all one wants to do is run a benchmark. Need some better + way to identify this case. */ + int max_insns = (step + ? 1 + : (nr_cpus == 1 + /*&& wip:no-events*/ + /* Don't do this if running under gdb, need to + poll ui for events. */ + && STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE) + ? 0 + : 8); /*FIXME: magic number*/ + int fast_p = STATE_RUN_FAST_P (sd); + + sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus); + if (next_cpu_nr >= nr_cpus) + next_cpu_nr = 0; + if (nr_cpus == 1) + engine_run_1 (sd, max_insns, fast_p); + else + engine_run_n (sd, next_cpu_nr, nr_cpus, max_insns, fast_p); + } +#if 1 /*wip*/ + else + { + /* Account for the last insn executed. */ + SIM_CPU *cpu = STATE_CPU (sd, sim_engine_last_cpu_nr (sd)); + ++ CPU_INSN_COUNT (cpu); + TRACE_INSN_FINI (cpu, NULL, 1); + } +#endif + + engine->jmpbuf = NULL; + + { + int i; + int nr_cpus = sim_engine_nr_cpus (sd); + +#if 0 /*wip,ignore*/ + /* If the loop exits, either we single-stepped or @cpu@_engine_stop + was called. */ + if (step) + sim_engine_set_run_state (sd, sim_stopped, SIM_SIGTRAP); + else + sim_engine_set_run_state (sd, pending_reason, pending_sigrc); +#endif + + for (i = 0; i < nr_cpus; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + + PROFILE_TOTAL_INSN_COUNT (CPU_PROFILE_DATA (cpu)) += CPU_INSN_COUNT (cpu); + } + } + + sim_module_suspend (sd); +} + +/* Halt the simulator after just one instruction. */ + +static void +has_stepped (SIM_DESC sd, void *data) +{ + ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP); +} + +/* Prepare a cpu for running. + MAX_INSNS is the number of insns to execute per time slice. + If 0 it means the cpu can run as long as it wants (e.g. until the + program completes). + ??? Perhaps this should be an argument to the engine_fn. */ + +static void +prime_cpu (SIM_CPU *cpu, int max_insns) +{ + CPU_MAX_SLICE_INSNS (cpu) = max_insns; + CPU_INSN_COUNT (cpu) = 0; + + /* Initialize the insn descriptor table. + This has to be done after all initialization so we just defer it to + here. */ + + if (MACH_PREPARE_RUN (CPU_MACH (cpu))) + (* MACH_PREPARE_RUN (CPU_MACH (cpu))) (cpu); +} + +/* Main loop, for 1 cpu. */ + +static void +engine_run_1 (SIM_DESC sd, int max_insns, int fast_p) +{ + sim_cpu *cpu = STATE_CPU (sd, 0); + ENGINE_FN *fn = fast_p ? CPU_FAST_ENGINE_FN (cpu) : CPU_FULL_ENGINE_FN (cpu); + + prime_cpu (cpu, max_insns); + + while (1) + { + SIM_ENGINE_PREFIX_HOOK (sd); + + (*fn) (cpu); + + SIM_ENGINE_POSTFIX_HOOK (sd); + + /* process any events */ + if (sim_events_tick (sd)) + sim_events_process (sd); + } +} + +/* Main loop, for multiple cpus. */ + +static void +engine_run_n (SIM_DESC sd, int next_cpu_nr, int nr_cpus, int max_insns, int fast_p) +{ + int i; + ENGINE_FN *engine_fns[MAX_NR_PROCESSORS]; + + for (i = 0; i < nr_cpus; ++i) + { + SIM_CPU *cpu = STATE_CPU (sd, i); + + engine_fns[i] = fast_p ? CPU_FAST_ENGINE_FN (cpu) : CPU_FULL_ENGINE_FN (cpu); + prime_cpu (cpu, max_insns); + } + + while (1) + { + SIM_ENGINE_PREFIX_HOOK (sd); + + /* FIXME: proper cycling of all of them, blah blah blah. */ + while (next_cpu_nr != nr_cpus) + { + SIM_CPU *cpu = STATE_CPU (sd, next_cpu_nr); + + (* engine_fns[next_cpu_nr]) (cpu); + ++next_cpu_nr; + } + + SIM_ENGINE_POSTFIX_HOOK (sd); + + /* process any events */ + if (sim_events_tick (sd)) + sim_events_process (sd); + } +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-scache.c b/external/gpl3/gdb/dist/sim/common/cgen-scache.c new file mode 100644 index 000000000000..cc68ac42a88d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-scache.c @@ -0,0 +1,476 @@ +/* Simulator cache routines for CGEN simulators (and maybe others). + Copyright (C) 1996, 1997, 1998, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#define SCACHE_DEFINE_INLINE + +#include "sim-main.h" +#ifdef HAVE_STDLIB_H +#include +#endif +#include "libiberty.h" +#include "sim-options.h" +#include "sim-io.h" + +#define MAX(a,b) ((a) > (b) ? (a) : (b)) + +/* Unused address. */ +#define UNUSED_ADDR 0xffffffff + +/* Scache configuration parameters. + ??? Experiments to determine reasonable values is wip. + These are just guesses. */ + +/* Default number of scache elements. + The size of an element is typically 32-64 bytes, so the size of the + default scache will be between 512K and 1M bytes. */ +#ifdef CONFIG_SIM_CACHE_SIZE +#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE +#else +#define SCACHE_DEFAULT_CACHE_SIZE 16384 +#endif + +/* Minimum cache size. + The m32r port assumes a cache size of at least 2 so it can decode both 16 + bit insns. When compiling we need an extra for the chain entry. And this + must be a multiple of 2. Hence 4 is the minimum (though, for those with + featuritis or itchy pedantic bits, we could make this conditional on + WITH_SCACHE_PBB). */ +#define MIN_SCACHE_SIZE 4 + +/* Ratio of size of text section to size of scache. + When compiling, we don't want to flush the scache more than we have to + but we also don't want it to be exorbitantly(sp?) large. So we pick a high + default value, then reduce it by the size of the program being simulated, + but we don't override any value specified on the command line. + If not specified on the command line, the size to use is computed as + max (MIN_SCACHE_SIZE, + min (DEFAULT_SCACHE_SIZE, + text_size / (base_insn_size * INSN_SCACHE_RATIO))). */ +/* ??? Interesting idea but not currently used. */ +#define INSN_SCACHE_RATIO 4 + +/* Default maximum insn chain length. + The only reason for a maximum is so we can place a maximum size on the + profiling table. Chain lengths are determined by cti's. + 32 is a more reasonable number, but when profiling, the before/after + handlers take up that much more space. The scache is filled from front to + back so all this determines is when the scache needs to be flushed. */ +#define MAX_CHAIN_LENGTH 64 + +/* Default maximum hash list length. */ +#define MAX_HASH_CHAIN_LENGTH 4 + +/* Minimum hash table size. */ +#define MIN_HASH_CHAINS 32 + +/* Ratio of number of scache elements to number of hash lists. + Since the user can only specify the size of the scache, we compute the + size of the hash table as + max (MIN_HASH_CHAINS, scache_size / SCACHE_HASH_RATIO). */ +#define SCACHE_HASH_RATIO 8 + +/* Hash a PC value. + FIXME: May wish to make the hashing architecture specific. + FIXME: revisit */ +#define HASH_PC(pc) (((pc) >> 2) + ((pc) >> 5)) + +static MODULE_INIT_FN scache_init; +static MODULE_UNINSTALL_FN scache_uninstall; + +static DECLARE_OPTION_HANDLER (scache_option_handler); + +#define OPTION_PROFILE_SCACHE (OPTION_START + 0) + +static const OPTION scache_options[] = { + { {"scache-size", optional_argument, NULL, 'c'}, + 'c', "[SIZE]", "Specify size of simulator execution cache", + scache_option_handler }, +#if WITH_SCACHE_PBB + /* ??? It might be nice to allow the user to specify the size of the hash + table, the maximum hash list length, and the maximum chain length, but + for now that might be more akin to featuritis. */ +#endif + { {"profile-scache", optional_argument, NULL, OPTION_PROFILE_SCACHE}, + '\0', "on|off", "Perform simulator execution cache profiling", + scache_option_handler }, + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } +}; + +static SIM_RC +scache_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, + char *arg, int is_command) +{ + switch (opt) + { + case 'c' : + if (WITH_SCACHE) + { + if (arg != NULL) + { + int n = strtol (arg, NULL, 0); + if (n < MIN_SCACHE_SIZE) + { + sim_io_eprintf (sd, "invalid scache size `%d', must be at least 4", n); + return SIM_RC_FAIL; + } + /* Ensure it's a multiple of 2. */ + if ((n & (n - 1)) != 0) + { + sim_io_eprintf (sd, "scache size `%d' not a multiple of 2\n", n); + { + /* round up to nearest multiple of 2 */ + int i; + for (i = 1; i < n; i <<= 1) + continue; + n = i; + } + sim_io_eprintf (sd, "rounding scache size up to %d\n", n); + } + if (cpu == NULL) + STATE_SCACHE_SIZE (sd) = n; + else + CPU_SCACHE_SIZE (cpu) = n; + } + else + { + if (cpu == NULL) + STATE_SCACHE_SIZE (sd) = SCACHE_DEFAULT_CACHE_SIZE; + else + CPU_SCACHE_SIZE (cpu) = SCACHE_DEFAULT_CACHE_SIZE; + } + } + else + sim_io_eprintf (sd, "Simulator execution cache not enabled, `--scache-size' ignored\n"); + break; + + case OPTION_PROFILE_SCACHE : + if (WITH_SCACHE && WITH_PROFILE_SCACHE_P) + { + /* FIXME: handle cpu != NULL. */ + return sim_profile_set_option (sd, "-scache", PROFILE_SCACHE_IDX, + arg); + } + else + sim_io_eprintf (sd, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n"); + break; + } + + return SIM_RC_OK; +} + +SIM_RC +scache_install (SIM_DESC sd) +{ + sim_add_option_table (sd, NULL, scache_options); + sim_module_add_init_fn (sd, scache_init); + sim_module_add_uninstall_fn (sd, scache_uninstall); + + /* This is the default, it may be overridden on the command line. */ + STATE_SCACHE_SIZE (sd) = WITH_SCACHE; + + return SIM_RC_OK; +} + +static SIM_RC +scache_init (SIM_DESC sd) +{ + int c; + + for (c = 0; c < MAX_NR_PROCESSORS; ++c) + { + SIM_CPU *cpu = STATE_CPU (sd, c); + int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); + + /* elm_size is 0 if the cpu doesn't not have scache support */ + if (elm_size == 0) + { + CPU_SCACHE_SIZE (cpu) = 0; + CPU_SCACHE_CACHE (cpu) = NULL; + } + else + { + if (CPU_SCACHE_SIZE (cpu) == 0) + CPU_SCACHE_SIZE (cpu) = STATE_SCACHE_SIZE (sd); + CPU_SCACHE_CACHE (cpu) = + (SCACHE *) xmalloc (CPU_SCACHE_SIZE (cpu) * elm_size); +#if WITH_SCACHE_PBB + CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) = MAX_CHAIN_LENGTH; + CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) = MAX_HASH_CHAIN_LENGTH; + CPU_SCACHE_NUM_HASH_CHAINS (cpu) = MAX (MIN_HASH_CHAINS, + CPU_SCACHE_SIZE (cpu) + / SCACHE_HASH_RATIO); + CPU_SCACHE_HASH_TABLE (cpu) = + (SCACHE_MAP *) xmalloc (CPU_SCACHE_NUM_HASH_CHAINS (cpu) + * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) + * sizeof (SCACHE_MAP)); + CPU_SCACHE_PBB_BEGIN (cpu) = (SCACHE *) zalloc (elm_size); + CPU_SCACHE_CHAIN_LENGTHS (cpu) = + (unsigned long *) zalloc ((CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) + 1) + * sizeof (long)); +#endif + } + } + + scache_flush (sd); + + return SIM_RC_OK; +} + +static void +scache_uninstall (SIM_DESC sd) +{ + int c; + + for (c = 0; c < MAX_NR_PROCESSORS; ++c) + { + SIM_CPU *cpu = STATE_CPU (sd, c); + + if (CPU_SCACHE_CACHE (cpu) != NULL) + free (CPU_SCACHE_CACHE (cpu)); +#if WITH_SCACHE_PBB + if (CPU_SCACHE_HASH_TABLE (cpu) != NULL) + free (CPU_SCACHE_HASH_TABLE (cpu)); + if (CPU_SCACHE_PBB_BEGIN (cpu) != NULL) + free (CPU_SCACHE_PBB_BEGIN (cpu)); + if (CPU_SCACHE_CHAIN_LENGTHS (cpu) != NULL) + free (CPU_SCACHE_CHAIN_LENGTHS (cpu)); +#endif + } +} + +void +scache_flush (SIM_DESC sd) +{ + int c; + + for (c = 0; c < MAX_NR_PROCESSORS; ++c) + { + SIM_CPU *cpu = STATE_CPU (sd, c); + scache_flush_cpu (cpu); + } +} + +void +scache_flush_cpu (SIM_CPU *cpu) +{ + int i,n; + + /* Don't bother if cache not in use. */ + if (CPU_SCACHE_SIZE (cpu) == 0) + return; + +#if WITH_SCACHE_PBB + /* It's important that this be reasonably fast as this can be done when + the simulation is running. */ + CPU_SCACHE_NEXT_FREE (cpu) = CPU_SCACHE_CACHE (cpu); + n = CPU_SCACHE_NUM_HASH_CHAINS (cpu) * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); + /* ??? Might be faster to just set the first entry, then update the + "last entry" marker during allocation. */ + for (i = 0; i < n; ++i) + CPU_SCACHE_HASH_TABLE (cpu) [i] . pc = UNUSED_ADDR; +#else + { + int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); + SCACHE *sc; + + /* Technically, this may not be necessary, but it helps debugging. */ + memset (CPU_SCACHE_CACHE (cpu), 0, + CPU_SCACHE_SIZE (cpu) * elm_size); + + for (i = 0, sc = CPU_SCACHE_CACHE (cpu); i < CPU_SCACHE_SIZE (cpu); + ++i, sc = (SCACHE *) ((char *) sc + elm_size)) + { + sc->argbuf.addr = UNUSED_ADDR; + } + } +#endif +} + +#if WITH_SCACHE_PBB + +/* Look up PC in the hash table of scache entry points. + Returns the entry or NULL if not found. */ + +SCACHE * +scache_lookup (SIM_CPU *cpu, IADDR pc) +{ + /* FIXME: hash computation is wrong, doesn't take into account + NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ + unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); + int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); + SCACHE_MAP *scm; + + /* We don't update hit/miss statistics as this is only used when recording + branch target addresses. */ + + scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; + for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) + { + if (scm->pc == pc) + return scm->sc; + } + return 0; +} + +/* Look up PC and if not found create an entry for it. + If found the result is a pointer to the SCACHE entry. + If not found the result is NULL, and the address of a buffer of at least + N entries is stored in BUFP. + It's done this way so the caller can still distinguish found/not-found. + If the table is full, it is emptied to make room. + If the maximum length of a hash list is reached a random entry is thrown out + to make room. + ??? One might want to try to make this smarter, but let's see some + measurable benefit first. */ + +SCACHE * +scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) +{ + /* FIXME: hash computation is wrong, doesn't take into account + NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ + unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); + int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); + SCACHE_MAP *scm; + SCACHE *sc; + + scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; + for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) + { + if (scm->pc == pc) + { + PROFILE_COUNT_SCACHE_HIT (cpu); + return scm->sc; + } + } + PROFILE_COUNT_SCACHE_MISS (cpu); + + /* The address we want isn't cached. Bummer. + If the hash chain we have for this address is full, throw out an entry + to make room. */ + + if (i == max_i) + { + /* Rather than do something sophisticated like LRU, we just throw out + a semi-random entry. Let someone else have the joy of saying how + wrong this is. NEXT_FREE is the entry to throw out and cycles + through all possibilities. */ + static int next_free = 0; + + scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; + /* FIXME: This seems rather clumsy. */ + for (i = 0; i < next_free; ++i, ++scm) + continue; + ++next_free; + if (next_free == CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu)) + next_free = 0; + } + + /* At this point SCM points to the hash table entry to use. + Now make sure there's room in the cache. */ + /* FIXME: Kinda weird to use a next_free adjusted scm when cache is + flushed. */ + + { + int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); + int elms_used = (((char *) CPU_SCACHE_NEXT_FREE (cpu) + - (char *) CPU_SCACHE_CACHE (cpu)) + / elm_size); + int elms_left = CPU_SCACHE_SIZE (cpu) - elms_used; + + if (elms_left < n) + { + PROFILE_COUNT_SCACHE_FULL_FLUSH (cpu); + scache_flush_cpu (cpu); + } + } + + sc = CPU_SCACHE_NEXT_FREE (cpu); + scm->pc = pc; + scm->sc = sc; + + *bufp = sc; + return NULL; +} + +#endif /* WITH_SCACHE_PBB */ + +/* Print cache access statics for CPU. */ + +void +scache_print_profile (SIM_CPU *cpu, int verbose) +{ + SIM_DESC sd = CPU_STATE (cpu); + unsigned long hits = CPU_SCACHE_HITS (cpu); + unsigned long misses = CPU_SCACHE_MISSES (cpu); + char buf[20]; + unsigned long max_val; + unsigned long *lengths; + int i; + + if (CPU_SCACHE_SIZE (cpu) == 0) + return; + + sim_io_printf (sd, "Simulator Cache Statistics\n\n"); + + /* One could use PROFILE_LABEL_WIDTH here. I chose not to. */ + sim_io_printf (sd, " Cache size: %s\n", + sim_add_commas (buf, sizeof (buf), CPU_SCACHE_SIZE (cpu))); + sim_io_printf (sd, " Hits: %s\n", + sim_add_commas (buf, sizeof (buf), hits)); + sim_io_printf (sd, " Misses: %s\n", + sim_add_commas (buf, sizeof (buf), misses)); + if (hits + misses != 0) + sim_io_printf (sd, " Hit rate: %.2f%%\n", + ((double) hits / ((double) hits + (double) misses)) * 100); + +#if WITH_SCACHE_PBB + sim_io_printf (sd, "\n"); + sim_io_printf (sd, " Hash table size: %s\n", + sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAINS (cpu))); + sim_io_printf (sd, " Max hash list length: %s\n", + sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu))); + sim_io_printf (sd, " Max insn chain length: %s\n", + sim_add_commas (buf, sizeof (buf), CPU_SCACHE_MAX_CHAIN_LENGTH (cpu))); + sim_io_printf (sd, " Cache full flushes: %s\n", + sim_add_commas (buf, sizeof (buf), CPU_SCACHE_FULL_FLUSHES (cpu))); + sim_io_printf (sd, "\n"); + + if (verbose) + { + sim_io_printf (sd, " Insn chain lengths:\n\n"); + max_val = 0; + lengths = CPU_SCACHE_CHAIN_LENGTHS (cpu); + for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) + if (lengths[i] > max_val) + max_val = lengths[i]; + for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) + { + sim_io_printf (sd, " %2d: %*s: ", + i, + max_val < 10000 ? 5 : 10, + sim_add_commas (buf, sizeof (buf), lengths[i])); + sim_profile_print_bar (sd, cpu, PROFILE_HISTOGRAM_WIDTH, + lengths[i], max_val); + sim_io_printf (sd, "\n"); + } + sim_io_printf (sd, "\n"); + } +#endif /* WITH_SCACHE_PBB */ +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-scache.h b/external/gpl3/gdb/dist/sim/common/cgen-scache.h new file mode 100644 index 000000000000..b6d9586f8cda --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-scache.h @@ -0,0 +1,162 @@ +/* Simulator header for cgen scache support. + Copyright (C) 1998, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_SCACHE_H +#define CGEN_SCACHE_H + +#ifndef WITH_SCACHE +#define WITH_SCACHE 0 +#endif + +/* When caching bb's, instructions are extracted into "chains". + SCACHE_MAP is a hash table into these chains. */ + +typedef struct { + IADDR pc; + SCACHE *sc; +} SCACHE_MAP; + +typedef struct cpu_scache { + /* Simulator cache size. Must be a power of 2. + This is the number of elements in the `cache' member. */ + unsigned int size; +#define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size) + /* The cache. */ + SCACHE *cache; +#define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache) + +#if WITH_SCACHE_PBB + /* Number of hash chains. Must be a power of 2. */ + unsigned int num_hash_chains; +#define CPU_SCACHE_NUM_HASH_CHAINS(cpu) ((cpu) -> cgen_cpu.scache.num_hash_chains) + /* Number of entries in each hash chain. + The hash table is a statically allocated NxM array where + N = num_hash_chains + M = num_hash_chain_entries. */ + unsigned int num_hash_chain_entries; +#define CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES(cpu) ((cpu) -> cgen_cpu.scache.num_hash_chain_entries) + /* Maximum number of instructions in a chain. + ??? This just let's us set a static size of chain_lengths table. + In a simulation that handles more than just the cpu, this might also be + used to keep too many instructions from being executed before checking + for events (or some such). */ + unsigned int max_chain_length; +#define CPU_SCACHE_MAX_CHAIN_LENGTH(cpu) ((cpu) -> cgen_cpu.scache.max_chain_length) + /* Special scache entry for (re)starting bb extraction. */ + SCACHE *pbb_begin; +#define CPU_SCACHE_PBB_BEGIN(cpu) ((cpu) -> cgen_cpu.scache.pbb_begin) + /* Hash table into cached chains. */ + SCACHE_MAP *hash_table; +#define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table) + /* Next free entry in cache. */ + SCACHE *next_free; +#define CPU_SCACHE_NEXT_FREE(cpu) ((cpu) -> cgen_cpu.scache.next_free) + + /* Kind of branch being taken. + Only used by functional semantics, not switch form. */ + SEM_BRANCH_TYPE pbb_br_type; +#define CPU_PBB_BR_TYPE(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_type) + /* Target's branch address. */ + IADDR pbb_br_npc; +#define CPU_PBB_BR_NPC(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_npc) +#endif /* WITH_SCACHE_PBB */ + +#if WITH_PROFILE_SCACHE_P + /* Cache hits, misses. */ + unsigned long hits, misses; +#define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits) +#define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses) + +#if WITH_SCACHE_PBB + /* Chain length counts. + Each element is a count of the number of chains created with that + length. */ + unsigned long *chain_lengths; +#define CPU_SCACHE_CHAIN_LENGTHS(cpu) ((cpu) -> cgen_cpu.scache.chain_lengths) + /* Number of times cache was flushed due to its being full. */ + unsigned long full_flushes; +#define CPU_SCACHE_FULL_FLUSHES(cpu) ((cpu) -> cgen_cpu.scache.full_flushes) +#endif +#endif +} CPU_SCACHE; + +/* Hash a PC value. + This is split into two parts to help with moving as much of the + computation out of the main loop. */ +#define CPU_SCACHE_HASH_MASK(cpu) (CPU_SCACHE_SIZE (cpu) - 1) +#define SCACHE_HASH_PC(pc, mask) \ +((CGEN_MIN_INSN_SIZE == 2 ? ((pc) >> 1) \ + : CGEN_MIN_INSN_SIZE == 4 ? ((pc) >> 2) \ + : (pc)) \ + & (mask)) + +/* Non-zero if cache is in use. */ +#define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0) + +/* Install the simulator cache into the simulator. */ +MODULE_INSTALL_FN scache_install; + +/* Lookup a PC value in the scache [compilation only]. */ +extern SCACHE * scache_lookup (SIM_CPU *, IADDR); +/* Return a pointer to at least N buffers. */ +extern SCACHE *scache_lookup_or_alloc (SIM_CPU *, IADDR, int, SCACHE **); +/* Flush all cpu's scaches. */ +extern void scache_flush (SIM_DESC); +/* Flush a cpu's scache. */ +extern void scache_flush_cpu (SIM_CPU *); + +/* Scache profiling support. */ + +/* Print summary scache usage information. */ +extern void scache_print_profile (SIM_CPU *cpu, int verbose); + +#if WITH_PROFILE_SCACHE_P + +#define PROFILE_COUNT_SCACHE_HIT(cpu) \ +do { \ + if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ + ++ CPU_SCACHE_HITS (cpu); \ +} while (0) +#define PROFILE_COUNT_SCACHE_MISS(cpu) \ +do { \ + if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ + ++ CPU_SCACHE_MISSES (cpu); \ +} while (0) +#define PROFILE_COUNT_SCACHE_CHAIN_LENGTH(cpu,length) \ +do { \ + if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ + ++ CPU_SCACHE_CHAIN_LENGTHS (cpu) [length]; \ +} while (0) +#define PROFILE_COUNT_SCACHE_FULL_FLUSH(cpu) \ +do { \ + if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ + ++ CPU_SCACHE_FULL_FLUSHES (cpu); \ +} while (0) + +#else + +#define PROFILE_COUNT_SCACHE_HIT(cpu) +#define PROFILE_COUNT_SCACHE_MISS(cpu) +#define PROFILE_COUNT_SCACHE_CHAIN_LENGTH(cpu,length) +#define PROFILE_COUNT_SCACHE_FULL_FLUSH(cpu) + +#endif + +#endif /* CGEN_SCACHE_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-sim.h b/external/gpl3/gdb/dist/sim/common/cgen-sim.h new file mode 100644 index 000000000000..cdc1c0b03ee1 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-sim.h @@ -0,0 +1,36 @@ +/* Main header file for Cpu tools GENerated simulators. + Copyright (C) 1998, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* This file must be included after sim-base.h. */ + +#ifndef CGEN_SIM_H +#define CGEN_SIM_H + +#include "cgen-defs.h" +#include "cgen-scache.h" +#include "cgen-fpu.h" +#include "cgen-par.h" +#include "cgen-cpu.h" +#include "cgen-trace.h" + +/* This is a machine generated file. */ +#include "cpuall.h" + +#endif /* CGEN_SIM_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-trace.c b/external/gpl3/gdb/dist/sim/common/cgen-trace.c new file mode 100644 index 000000000000..0d3f196c374e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-trace.c @@ -0,0 +1,436 @@ +/* Tracing support for CGEN-based simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include +#include "dis-asm.h" +#include "bfd.h" +#include "sim-main.h" +#include "sim-fpu.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) + +#ifndef SIZE_INSTRUCTION +#define SIZE_INSTRUCTION 16 +#endif + +#ifndef SIZE_LOCATION +#define SIZE_LOCATION 20 +#endif + +#ifndef SIZE_PC +#define SIZE_PC 6 +#endif + +#ifndef SIZE_LINE_NUMBER +#define SIZE_LINE_NUMBER 4 +#endif + +#ifndef SIZE_CYCLE_COUNT +#define SIZE_CYCLE_COUNT 2 +#endif + +#ifndef SIZE_TOTAL_CYCLE_COUNT +#define SIZE_TOTAL_CYCLE_COUNT 9 +#endif + +#ifndef SIZE_TRACE_BUF +#define SIZE_TRACE_BUF 1024 +#endif + +/* Text is queued in TRACE_BUF because we want to output the insn's cycle + count first but that isn't known until after the insn has executed. + This also handles the queueing of trace results, TRACE_RESULT may be + called multiple times for one insn. */ +static char trace_buf[SIZE_TRACE_BUF]; +/* If NULL, output to stdout directly. */ +static char *bufptr; + +/* Non-zero if this is the first insn in a set of parallel insns. */ +static int first_insn_p; + +/* For communication between trace_insn and trace_result. */ +static int printed_result_p; + +/* Insn and its extracted fields. + Set by trace_insn, used by trace_insn_fini. + ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */ +static const struct cgen_insn *current_insn; +static const struct argbuf *current_abuf; + +void +trace_insn_init (SIM_CPU *cpu, int first_p) +{ + bufptr = trace_buf; + *bufptr = 0; + first_insn_p = first_p; + + /* Set to NULL so trace_insn_fini can know if trace_insn was called. */ + current_insn = NULL; + current_abuf = NULL; +} + +void +trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p) +{ + SIM_DESC sd = CPU_STATE (cpu); + + /* Was insn traced? It might not be if trace ranges are in effect. */ + if (current_insn == NULL) + return; + + /* The first thing printed is current and total cycle counts. */ + + if (PROFILE_MODEL_P (cpu) + && ARGBUF_PROFILE_P (current_abuf)) + { + unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu)); + unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu)); + + if (last_p) + { + trace_printf (sd, cpu, "%-*ld %-*ld ", + SIZE_CYCLE_COUNT, this_insn, + SIZE_TOTAL_CYCLE_COUNT, total); + } + else + { + trace_printf (sd, cpu, "%-*ld %-*s ", + SIZE_CYCLE_COUNT, this_insn, + SIZE_TOTAL_CYCLE_COUNT, "---"); + } + } + + /* Print the disassembled insn. */ + + trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu))); + +#if 0 + /* Print insn results. */ + { + const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn); + + if (opinst) + { + int i; + int indices[MAX_OPERAND_INSTANCES]; + + /* Fetch the operands used by the insn. */ + /* FIXME: Add fn ptr to CGEN_CPU_DESC. */ + CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn, + 0, CGEN_FIELDS_BITSIZE (&insn_fields), + indices); + + for (i = 0; + CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END; + ++i, ++opinst) + { + if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT) + trace_result (cpu, current_insn, opinst, indices[i]); + } + } + } +#endif + + /* Print anything else requested. */ + + if (*trace_buf) + trace_printf (sd, cpu, " %s\n", trace_buf); + else + trace_printf (sd, cpu, "\n"); +} + +void +trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode, + const struct argbuf *abuf, IADDR pc) +{ + char disasm_buf[50]; + + printed_result_p = 0; + current_insn = opcode; + current_abuf = abuf; + + if (CGEN_INSN_VIRTUAL_P (opcode)) + { + trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0, + NULL, 0, CGEN_INSN_NAME (opcode)); + return; + } + + CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf); + trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), + NULL, 0, + "%s%-*s", + first_insn_p ? " " : "|", + SIZE_INSTRUCTION, disasm_buf); +} + +void +trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...) +{ + va_list args; + int printed_one_p = 0; + char *fmt; + + va_start (args, name); + + trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ", + SIZE_PC, (unsigned long) pc, name); + + do { + int type,ival; + + fmt = va_arg (args, char *); + + if (fmt) + { + if (printed_one_p) + trace_printf (CPU_STATE (cpu), cpu, ", "); + printed_one_p = 1; + type = va_arg (args, int); + switch (type) + { + case 'x' : + ival = va_arg (args, int); + trace_printf (CPU_STATE (cpu), cpu, fmt, ival); + break; + default : + abort (); + } + } + } while (fmt); + + va_end (args); + trace_printf (CPU_STATE (cpu), cpu, "\n"); +} + +void +trace_result (SIM_CPU *cpu, char *name, int type, ...) +{ + va_list args; + + va_start (args, type); + if (printed_result_p) + cgen_trace_printf (cpu, ", "); + + switch (type) + { + case 'x' : + default : + cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int)); + break; + case 'f': + { + DI di; + sim_fpu f; + + /* this is separated from previous line for sunos cc */ + di = va_arg (args, DI); + sim_fpu_64to (&f, di); + + cgen_trace_printf (cpu, "%s <- ", name); + sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu); + break; + } + case 'D' : + { + DI di; + /* this is separated from previous line for sunos cc */ + di = va_arg (args, DI); + cgen_trace_printf (cpu, "%s <- 0x%x%08x", name, + GETHIDI(di), GETLODI (di)); + break; + } + } + + printed_result_p = 1; + va_end (args); +} + +/* Print trace output to BUFPTR if active, otherwise print normally. + This is only for tracing semantic code. */ + +void +cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...) +{ + va_list args; + + va_start (args, fmt); + + if (bufptr == NULL) + { + if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL) + (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered) + (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args); + else + vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args); + } + else + { + vsprintf (bufptr, fmt, args); + bufptr += strlen (bufptr); + /* ??? Need version of SIM_ASSERT that is always enabled. */ + if (bufptr - trace_buf > SIZE_TRACE_BUF) + abort (); + } + + va_end (args); +} + +/* Disassembly support. */ + +/* sprintf to a "stream" */ + +int +sim_disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...)) +{ +#ifndef __STDC__ + SFILE *f; + const char *format; +#endif + int n; + va_list args; + + VA_START (args, format); +#ifndef __STDC__ + f = va_arg (args, SFILE *); + format = va_arg (args, char *); +#endif + vsprintf (f->current, format, args); + f->current += n = strlen (f->current); + va_end (args); + return n; +} + +/* Memory read support for an opcodes disassembler. */ + +int +sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *info) +{ + SIM_CPU *cpu = (SIM_CPU *) info->application_data; + SIM_DESC sd = CPU_STATE (cpu); + unsigned length_read; + + length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr, + length); + if (length_read != length) + return EIO; + return 0; +} + +/* Memory error support for an opcodes disassembler. */ + +void +sim_disasm_perror_memory (int status, bfd_vma memaddr, + struct disassemble_info *info) +{ + if (status != EIO) + /* Can't happen. */ + info->fprintf_func (info->stream, "Unknown error %d.", status); + else + /* Actually, address between memaddr and memaddr + len was + out of bounds. */ + info->fprintf_func (info->stream, + "Address 0x%x is out of bounds.", + (int) memaddr); +} + +/* Disassemble using the CGEN opcode table. + ??? While executing an instruction, the insn has been decoded and all its + fields have been extracted. It is certainly possible to do the disassembly + with that data. This seems simpler, but maybe in the future the already + extracted fields will be used. */ + +void +sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, + const ARGBUF *abuf, IADDR pc, char *buf) +{ + unsigned int length; + unsigned int base_length; + unsigned long insn_value; + struct disassemble_info disasm_info; + SFILE sfile; + union { + unsigned8 bytes[CGEN_MAX_INSN_SIZE]; + unsigned16 shorts[8]; + unsigned32 words[4]; + } insn_buf; + SIM_DESC sd = CPU_STATE (cpu); + CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu); + CGEN_EXTRACT_INFO ex_info; + CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd)); + int insn_bit_length = CGEN_INSN_BITSIZE (insn); + int insn_length = insn_bit_length / 8; + + sfile.buffer = sfile.current = buf; + INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile, + (fprintf_ftype) sim_disasm_sprintf); + disasm_info.endian = + (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG + : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE + : BFD_ENDIAN_UNKNOWN); + + length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc, + insn_length); + + if (length != insn_length) + { + sim_io_error (sd, "unable to read address %x", pc); + } + + /* If the entire insn will fit into an integer, then do it. Otherwise, just + use the bits of the base_insn. */ + if (insn_bit_length <= 32) + base_length = insn_bit_length; + else + base_length = min (cd->base_insn_bitsize, insn_bit_length); + switch (base_length) + { + case 0 : return; /* fake insn, typically "compile" (aka "invalid") */ + case 8 : insn_value = insn_buf.bytes[0]; break; + case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break; + case 32 : insn_value = T2H_4 (insn_buf.words[0]); break; + default: abort (); + } + + disasm_info.buffer_vma = pc; + disasm_info.buffer = insn_buf.bytes; + disasm_info.buffer_length = length; + + ex_info.dis_info = (PTR) &disasm_info; + ex_info.valid = (1 << length) - 1; + ex_info.insn_bytes = insn_buf.bytes; + + length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc); + /* Result of extract fn is in bits. */ + /* ??? This assumes that each instruction has a fixed length (and thus + for insns with multiple versions of variable lengths they would each + have their own table entry). */ + if (length == insn_bit_length) + { + (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length); + } + else + { + /* This shouldn't happen, but aborting is too drastic. */ + strcpy (buf, "***unknown***"); + } +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen-trace.h b/external/gpl3/gdb/dist/sim/common/cgen-trace.h new file mode 100644 index 000000000000..411921b0ecc6 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-trace.h @@ -0,0 +1,91 @@ +/* Simulator tracing support for Cpu tools GENerated simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#ifndef CGEN_TRACE_H +#define CGEN_TRACE_H + +void trace_insn_init (SIM_CPU *, int); +void trace_insn_fini (SIM_CPU *, const struct argbuf *, int); +void trace_insn (SIM_CPU *, const struct cgen_insn *, + const struct argbuf *, IADDR); +void trace_extract (SIM_CPU *, IADDR, char *, ...); +void trace_result (SIM_CPU *, char *, int, ...); +void cgen_trace_printf (SIM_CPU *, char *fmt, ...); + +/* Trace instruction results. */ +#define TRACE_RESULT_P(cpu, abuf) (TRACE_INSN_P (cpu) && ARGBUF_TRACE_P (abuf)) + +#define TRACE_INSN_INIT(cpu, abuf, first_p) \ +do { \ + if (TRACE_INSN_P (cpu)) \ + trace_insn_init ((cpu), (first_p)); \ +} while (0) +#define TRACE_INSN_FINI(cpu, abuf, last_p) \ +do { \ + if (TRACE_INSN_P (cpu)) \ + trace_insn_fini ((cpu), (abuf), (last_p)); \ +} while (0) +#define TRACE_PRINTF(cpu, what, args) \ +do { \ + if (TRACE_P ((cpu), (what))) \ + cgen_trace_printf args ; \ +} while (0) +#define TRACE_INSN(cpu, insn, abuf, pc) \ +do { \ + if (TRACE_INSN_P (cpu) && ARGBUF_TRACE_P (abuf)) \ + trace_insn ((cpu), (insn), (abuf), (pc)) ; \ +} while (0) +#define TRACE_EXTRACT(cpu, abuf, args) \ +do { \ + if (TRACE_EXTRACT_P (cpu)) \ + trace_extract args ; \ +} while (0) +#define TRACE_RESULT(cpu, abuf, name, type, val) \ +do { \ + if (TRACE_RESULT_P ((cpu), (abuf))) \ + trace_result ((cpu), (name), (type), (val)) ; \ +} while (0) + +/* Disassembly support. */ + +/* Function to use for cgen-based disassemblers. */ +extern CGEN_DISASSEMBLER sim_cgen_disassemble_insn; + +/* Pseudo FILE object for strings. */ +typedef struct { + char *buffer; + char *current; +} SFILE; + +/* String printer for the disassembler. */ +extern int sim_disasm_sprintf (SFILE *, const char *, ...); + +/* For opcodes based disassemblers. */ +#ifdef __BFD_H_SEEN__ +struct disassemble_info; +extern int +sim_disasm_read_memory (bfd_vma memaddr_, bfd_byte *myaddr_, unsigned int length_, + struct disassemble_info *info_); +extern void +sim_disasm_perror_memory (int status_, bfd_vma memaddr_, + struct disassemble_info *info_); +#endif + +#endif /* CGEN_TRACE_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-types.h b/external/gpl3/gdb/dist/sim/common/cgen-types.h new file mode 100644 index 000000000000..ddbbf479769e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-types.h @@ -0,0 +1,110 @@ +/* Types for Cpu tools GENerated simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +/* This file is not included with cgen-sim.h as it defines types + needed by sim-base.h. */ + +#ifndef CGEN_TYPES_H +#define CGEN_TYPES_H + +/* Miscellaneous cgen configury defined here as this file gets + included soon enough. */ + +/* Indicate we support --profile-model. */ +#undef SIM_HAVE_MODEL +#define SIM_HAVE_MODEL + +/* Indicate we support --{profile,trace}-{range,function}. */ +#undef SIM_HAVE_ADDR_RANGE +#define SIM_HAVE_ADDR_RANGE + +#ifdef __GNUC__ +#define HAVE_LONGLONG +#undef DI_FN_SUPPORT +#else +#undef HAVE_LONGLONG +#define DI_FN_SUPPORT +#endif + +/* Mode support. */ + +/* Common mode types. */ +/* ??? Target specific modes. */ +typedef enum mode_type { + MODE_VOID, MODE_BI, + MODE_QI, MODE_HI, MODE_SI, MODE_DI, + MODE_UQI, MODE_UHI, MODE_USI, MODE_UDI, + MODE_SF, MODE_DF, MODE_XF, MODE_TF, + MODE_TARGET_MAX /* = MODE_TF? */, + /* These are host modes. */ + MODE_INT, MODE_UINT, MODE_PTR, /*??? MODE_ADDR, MODE_IADDR,*/ + MODE_MAX +} MODE_TYPE; + +#define MAX_TARGET_MODES ((int) MODE_TARGET_MAX) +#define MAX_MODES ((int) MODE_MAX) + +extern const char *mode_names[]; +#define MODE_NAME(m) (mode_names[m]) + +typedef void VOID; +typedef unsigned char BI; +typedef signed8 QI; +typedef signed16 HI; +typedef signed32 SI; +typedef unsigned8 UQI; +typedef unsigned16 UHI; +typedef unsigned32 USI; + +#ifdef HAVE_LONGLONG +typedef signed64 DI; +typedef unsigned64 UDI; +#define GETLODI(di) ((SI) (di)) +#define GETHIDI(di) ((SI) ((UDI) (di) >> 32)) +#define SETLODI(di, val) ((di) = (((di) & 0xffffffff00000000LL) | (val))) +#define SETHIDI(di, val) ((di) = (((di) & 0xffffffffLL) | (((DI) (val)) << 32))) +#define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo))) +#else +/* DI mode support if "long long" doesn't exist. + At one point CGEN supported K&R C compilers, and ANSI C compilers without + "long long". One can argue the various merits of keeping this in or + throwing it out. I went to the trouble of adding it so for the time being + I'm leaving it in. */ +typedef struct { SI hi,lo; } DI; +typedef DI UDI; +#define GETLODI(di) ((di).lo) +#define GETHIDI(di) ((di).hi) +#define SETLODI(di, val) ((di).lo = (val)) +#define SETHIDI(di, val) ((di).hi = (val)) +extern DI make_struct_di (SI, SI); +#define MAKEDI(hi, lo) (make_struct_di ((hi), (lo))) +#endif + +/* These are used to record extracted raw data from an instruction, among other + things. It must be a host data type, and not a target one. */ +typedef int INT; +typedef unsigned int UINT; + +typedef unsigned_address ADDR; /* FIXME: wip*/ +typedef unsigned_address IADDR; /* FIXME: wip*/ + +/* fp types are in cgen-fpu.h */ + +#endif /* CGEN_TYPES_H */ diff --git a/external/gpl3/gdb/dist/sim/common/cgen-utils.c b/external/gpl3/gdb/dist/sim/common/cgen-utils.c new file mode 100644 index 000000000000..6a6bd51c34c1 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen-utils.c @@ -0,0 +1,438 @@ +/* Support code for various pieces of CGEN simulators. + Copyright (C) 1996, 1997, 1998, 1999, 2007, 2008, 2009, 2010, 2011 + Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ + +#include "bfd.h" +#include "sim-main.h" +#include "dis-asm.h" + +#define MEMOPS_DEFINE_INLINE +#include "cgen-mem.h" + +#define SEMOPS_DEFINE_INLINE +#include "cgen-ops.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) + +const char *mode_names[] = { + "VOID", + "BI", + "QI", + "HI", + "SI", + "DI", + "UQI", + "UHI", + "USI", + "UDI", + "SF", + "DF", + "XF", + "TF", + 0, /* MODE_TARGET_MAX */ + "INT", + "UINT", + "PTR" +}; + +/* Opcode table for virtual insns used by the simulator. */ + +#define V CGEN_ATTR_MASK (CGEN_INSN_VIRTUAL) + +static const CGEN_IBASE virtual_insn_entries[] = +{ + { + VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, { V, { 0 } } + }, + { + VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, { V, { 0 } } + }, + { + VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, { V, { 0 } } + }, + { + VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, { V, { 0 } } + }, + { + VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, { V, { 0 } } + }, + { + VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, { V, { 0 } } + } +}; + +#undef V + +const CGEN_INSN cgen_virtual_insn_table[] = +{ + { & virtual_insn_entries[0] }, + { & virtual_insn_entries[1] }, + { & virtual_insn_entries[2] }, + { & virtual_insn_entries[3] }, + { & virtual_insn_entries[4] }, + { & virtual_insn_entries[5] } +}; + +/* Initialize cgen things. + This is called after sim_post_argv_init. */ + +void +cgen_init (SIM_DESC sd) +{ + int i, c; + + /* If no profiling or tracing has been enabled, run in fast mode. */ + { + int run_fast_p = 1; + + for (c = 0; c < MAX_NR_PROCESSORS; ++c) + { + SIM_CPU *cpu = STATE_CPU (sd, c); + + for (i = 0; i < MAX_PROFILE_VALUES; ++i) + if (CPU_PROFILE_FLAGS (cpu) [i]) + { + run_fast_p = 0; + break; + } + for (i = 0; i < MAX_TRACE_VALUES; ++i) + if (CPU_TRACE_FLAGS (cpu) [i]) + { + run_fast_p = 0; + break; + } + if (! run_fast_p) + break; + } + STATE_RUN_FAST_P (sd) = run_fast_p; + } +} + +/* Return the name of insn number I. */ + +const char * +cgen_insn_name (SIM_CPU *cpu, int i) +{ + return CGEN_INSN_NAME ((* CPU_GET_IDATA (cpu)) ((cpu), (i))); +} + +/* Return the maximum number of extra bytes required for a SIM_CPU struct. */ + +int +cgen_cpu_max_extra_bytes (void) +{ + int i; + int extra = 0; + + for (i = 0; sim_machs[i] != 0; ++i) + { + int size = IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (sim_machs[i])); + if (size > extra) + extra = size; + } + return extra; +} + +#ifdef DI_FN_SUPPORT + +DI +make_struct_di (hi, lo) + SI hi, lo; +{ + DI result; + + result.hi = hi; + result.lo = lo; + return result; +} + +DI +ANDDI (a, b) + DI a, b; +{ + SI ahi = GETHIDI (a); + SI alo = GETLODI (a); + SI bhi = GETHIDI (b); + SI blo = GETLODI (b); + return MAKEDI (ahi & bhi, alo & blo); +} + +DI +ORDI (a, b) + DI a, b; +{ + SI ahi = GETHIDI (a); + SI alo = GETLODI (a); + SI bhi = GETHIDI (b); + SI blo = GETLODI (b); + return MAKEDI (ahi | bhi, alo | blo); +} + +DI +ADDDI (a, b) + DI a, b; +{ + USI ahi = GETHIDI (a); + USI alo = GETLODI (a); + USI bhi = GETHIDI (b); + USI blo = GETLODI (b); + USI x = alo + blo; + return MAKEDI (ahi + bhi + (x < alo), x); +} + +DI +MULDI (a, b) + DI a, b; +{ + USI ahi = GETHIDI (a); + USI alo = GETLODI (a); + USI bhi = GETHIDI (b); + USI blo = GETLODI (b); + USI rhi,rlo; + USI x0, x1, x2, x3; + + x0 = alo * blo; + x1 = alo * bhi; + x2 = ahi * blo; + x3 = ahi * bhi; + +#define SI_TYPE_SIZE 32 +#define BITS4 (SI_TYPE_SIZE / 4) +#define ll_B (1L << (SI_TYPE_SIZE / 2)) +#define ll_lowpart(t) ((USI) (t) % ll_B) +#define ll_highpart(t) ((USI) (t) / ll_B) + x1 += ll_highpart (x0); /* this can't give carry */ + x1 += x2; /* but this indeed can */ + if (x1 < x2) /* did we get it? */ + x3 += ll_B; /* yes, add it in the proper pos. */ + + rhi = x3 + ll_highpart (x1); + rlo = ll_lowpart (x1) * ll_B + ll_lowpart (x0); + return MAKEDI (rhi + (alo * bhi) + (ahi * blo), rlo); +} + +DI +SHLDI (val, shift) + DI val; + SI shift; +{ + USI hi = GETHIDI (val); + USI lo = GETLODI (val); + /* FIXME: Need to worry about shift < 0 || shift >= 32. */ + return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift); +} + +DI +SLADI (val, shift) + DI val; + SI shift; +{ + SI hi = GETHIDI (val); + USI lo = GETLODI (val); + /* FIXME: Need to worry about shift < 0 || shift >= 32. */ + return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift); +} + +DI +SRADI (val, shift) + DI val; + SI shift; +{ + SI hi = GETHIDI (val); + USI lo = GETLODI (val); + /* We use SRASI because the result is implementation defined if hi < 0. */ + /* FIXME: Need to worry about shift < 0 || shift >= 32. */ + return MAKEDI (SRASI (hi, shift), (hi << (32 - shift)) | (lo >> shift)); +} + +int +GEDI (a, b) + DI a, b; +{ + SI ahi = GETHIDI (a); + USI alo = GETLODI (a); + SI bhi = GETHIDI (b); + USI blo = GETLODI (b); + if (ahi > bhi) + return 1; + if (ahi == bhi) + return alo >= blo; + return 0; +} + +int +LEDI (a, b) + DI a, b; +{ + SI ahi = GETHIDI (a); + USI alo = GETLODI (a); + SI bhi = GETHIDI (b); + USI blo = GETLODI (b); + if (ahi < bhi) + return 1; + if (ahi == bhi) + return alo <= blo; + return 0; +} + +DI +CONVHIDI (val) + HI val; +{ + if (val < 0) + return MAKEDI (-1, val); + else + return MAKEDI (0, val); +} + +DI +CONVSIDI (val) + SI val; +{ + if (val < 0) + return MAKEDI (-1, val); + else + return MAKEDI (0, val); +} + +SI +CONVDISI (val) + DI val; +{ + return GETLODI (val); +} + +#endif /* DI_FN_SUPPORT */ + +QI +RORQI (val, shift) + QI val; + int shift; +{ + if (shift != 0) + { + int remain = 8 - shift; + int mask = (1 << shift) - 1; + QI result = (val & mask) << remain; + mask = (1 << remain) - 1; + result |= (val >> shift) & mask; + return result; + } + return val; +} + +QI +ROLQI (val, shift) + QI val; + int shift; +{ + if (shift != 0) + { + int remain = 8 - shift; + int mask = (1 << remain) - 1; + QI result = (val & mask) << shift; + mask = (1 << shift) - 1; + result |= (val >> remain) & mask; + return result; + } + return val; +} + +HI +RORHI (val, shift) + HI val; + int shift; +{ + if (shift != 0) + { + int remain = 16 - shift; + int mask = (1 << shift) - 1; + HI result = (val & mask) << remain; + mask = (1 << remain) - 1; + result |= (val >> shift) & mask; + return result; + } + return val; +} + +HI +ROLHI (val, shift) + HI val; + int shift; +{ + if (shift != 0) + { + int remain = 16 - shift; + int mask = (1 << remain) - 1; + HI result = (val & mask) << shift; + mask = (1 << shift) - 1; + result |= (val >> remain) & mask; + return result; + } + return val; +} + +SI +RORSI (val, shift) + SI val; + int shift; +{ + if (shift != 0) + { + int remain = 32 - shift; + int mask = (1 << shift) - 1; + SI result = (val & mask) << remain; + mask = (1 << remain) - 1; + result |= (val >> shift) & mask; + return result; + } + return val; +} + +SI +ROLSI (val, shift) + SI val; + int shift; +{ + if (shift != 0) + { + int remain = 32 - shift; + int mask = (1 << remain) - 1; + SI result = (val & mask) << shift; + mask = (1 << shift) - 1; + result |= (val >> remain) & mask; + return result; + } + + return val; +} + +/* Emit an error message from CGEN RTL. */ + +void +cgen_rtx_error (SIM_CPU *cpu, const char * msg) +{ + SIM_DESC sd = CPU_STATE (cpu); + + sim_io_printf (sd, msg); + sim_io_printf (sd, "\n"); + + sim_engine_halt (sd, cpu, NULL, CIA_GET (cpu), sim_stopped, SIM_SIGTRAP); +} diff --git a/external/gpl3/gdb/dist/sim/common/cgen.sh b/external/gpl3/gdb/dist/sim/common/cgen.sh new file mode 100644 index 000000000000..394ef2d2e1bc --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/cgen.sh @@ -0,0 +1,235 @@ +#! /bin/sh +# Generate CGEN simulator files. +# +# Usage: /bin/sh cgen.sh {"arch"|"cpu"|"decode"|"defs"|"cpu-decode"} \ +# srcdir cgen cgendir cgenflags \ +# arch archflags cpu mach suffix archfile extrafiles opcfile +# +# We store the generated files in the source directory until we decide to +# ship a Scheme interpreter (or other implementation) with gdb/binutils. +# Maybe we never will. + +# We want to behave like make, any error forces us to stop. +set -e + +action=$1 +srcdir=$2 +cgen="$3" +cgendir=$4 +cgenflags=$5 +arch=$6 +archflags=$7 +cpu=$8 +isa=$9 +# portably bring parameters beyond $9 into view +shift ; mach=$9 +shift ; suffix=$9 +shift ; archfile=$9 +shift ; extrafiles=$9 +shift ; opcfile=$9 + +rootdir=${srcdir}/../.. + +test -z "${opcfile}" && opcfile=/dev/null + +if test -z "$isa" ; then + isa=all + prefix=$cpu +else + prefix=${cpu}_$isa +fi + +lowercase='abcdefghijklmnopqrstuvwxyz' +uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` +CPU=`echo ${cpu} | tr "${lowercase}" "${uppercase}"` +PREFIX=`echo ${prefix} | tr "${lowercase}" "${uppercase}"` + +sedscript="\ +-e s/@ARCH@/${ARCH}/g -e s/@arch@/${arch}/g \ +-e s/@CPU@/${CPU}/g -e s/@cpu@/${cpu}/g \ +-e s/@PREFIX@/${PREFIX}/g -e s/@prefix@/${prefix}/g" + +# avoid collisions in parallel makes +tmp=tmp-$$ + +case $action in +arch) + rm -f ${tmp}-arch.h1 ${tmp}-arch.h + rm -f ${tmp}-arch.c1 ${tmp}-arch.c + rm -f ${tmp}-all.h1 ${tmp}-all.h + + ${cgen} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${archfile} \ + -i ${isa} \ + -A ${tmp}-arch.h1 \ + -B ${tmp}-arch.c1 \ + -N ${tmp}-all.h1 + sed $sedscript < ${tmp}-arch.h1 > ${tmp}-arch.h + ${rootdir}/move-if-change ${tmp}-arch.h ${srcdir}/arch.h + sed $sedscript < ${tmp}-arch.c1 > ${tmp}-arch.c + ${rootdir}/move-if-change ${tmp}-arch.c ${srcdir}/arch.c + sed $sedscript < ${tmp}-all.h1 > ${tmp}-all.h + ${rootdir}/move-if-change ${tmp}-all.h ${srcdir}/cpuall.h + + rm -f ${tmp}-arch.h1 ${tmp}-arch.c1 ${tmp}-all.h1 + ;; + +cpu | decode | cpu-decode) + + fileopts="" + + case $action in + *cpu*) + rm -f ${tmp}-cpu.h1 ${tmp}-cpu.c1 + rm -f ${tmp}-ext.c1 ${tmp}-read.c1 ${tmp}-write.c1 + rm -f ${tmp}-sem.c1 ${tmp}-semsw.c1 + rm -f ${tmp}-mod.c1 + rm -f ${tmp}-cpu.h ${tmp}-cpu.c + rm -f ${tmp}-ext.c ${tmp}-read.c ${tmp}-write.c + rm -f ${tmp}-sem.c ${tmp}-semsw.c ${tmp}-mod.c + fileopts="$fileopts \ + -C ${tmp}-cpu.h1 \ + -U ${tmp}-cpu.c1 \ + -M ${tmp}-mod.c1" + ;; + esac + + case $action in + *decode*) + rm -f ${tmp}-dec.h1 ${tmp}-dec.h ${tmp}-dec.c1 ${tmp}-dec.c + fileopts="$fileopts \ + -T ${tmp}-dec.h1 \ + -D ${tmp}-dec.c1" + ;; + esac + + case "$extrafiles" in + */extr/*) fileopts="${fileopts} -E ${tmp}-ext.c1" ;; + esac + case "$extrafiles" in + */read/*) fileopts="${fileopts} -R ${tmp}-read.c1" ;; + esac + case "$extrafiles" in + */write/*) fileopts="${fileopts} -W ${tmp}-write.c1" ;; + esac + case "$extrafiles" in + */sem/*) fileopts="${fileopts} -S ${tmp}-sem.c1" ;; + esac + case "$extrafiles" in + */semsw/*) fileopts="${fileopts} -X ${tmp}-semsw.c1" ;; + esac + + ${cgen} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${archfile} \ + -i ${isa} \ + ${fileopts} + + case $action in + *cpu*) + sed $sedscript < ${tmp}-cpu.h1 > ${tmp}-cpu.h + ${rootdir}/move-if-change ${tmp}-cpu.h ${srcdir}/cpu${suffix}.h + sed $sedscript < ${tmp}-cpu.c1 > ${tmp}-cpu.c + ${rootdir}/move-if-change ${tmp}-cpu.c ${srcdir}/cpu${suffix}.c + sed $sedscript < ${tmp}-mod.c1 > ${tmp}-mod.c + ${rootdir}/move-if-change ${tmp}-mod.c ${srcdir}/model${suffix}.c + rm -f ${tmp}-cpu.h1 ${tmp}-cpu.c1 ${tmp}-mod.c1 + ;; + esac + + case $action in + *decode*) + sed $sedscript < ${tmp}-dec.h1 > ${tmp}-dec.h + ${rootdir}/move-if-change ${tmp}-dec.h ${srcdir}/decode${suffix}.h + sed $sedscript < ${tmp}-dec.c1 > ${tmp}-dec.c + ${rootdir}/move-if-change ${tmp}-dec.c ${srcdir}/decode${suffix}.c + rm -f ${tmp}-dec.h1 ${tmp}-dec.c1 + ;; + esac + + if test -f ${tmp}-ext.c1 ; then \ + sed $sedscript < ${tmp}-ext.c1 > ${tmp}-ext.c ; \ + ${rootdir}/move-if-change ${tmp}-ext.c ${srcdir}/extract${suffix}.c ; \ + rm -f ${tmp}-ext.c1 + fi + if test -f ${tmp}-read.c1 ; then \ + sed $sedscript < ${tmp}-read.c1 > ${tmp}-read.c ; \ + ${rootdir}/move-if-change ${tmp}-read.c ${srcdir}/read${suffix}.c ; \ + rm -f ${tmp}-read.c1 + fi + if test -f ${tmp}-write.c1 ; then \ + sed $sedscript < ${tmp}-write.c1 > ${tmp}-write.c ; \ + ${rootdir}/move-if-change ${tmp}-write.c ${srcdir}/write${suffix}.c ; \ + rm -f ${tmp}-write.c1 + fi + if test -f ${tmp}-sem.c1 ; then \ + sed $sedscript < ${tmp}-sem.c1 > ${tmp}-sem.c ; \ + ${rootdir}/move-if-change ${tmp}-sem.c ${srcdir}/sem${suffix}.c ; \ + rm -f ${tmp}-sem.c1 + fi + if test -f ${tmp}-semsw.c1 ; then \ + sed $sedscript < ${tmp}-semsw.c1 > ${tmp}-semsw.c ; \ + ${rootdir}/move-if-change ${tmp}-semsw.c ${srcdir}/sem${suffix}-switch.c ; \ + rm -f ${tmp}-semsw.c1 + fi + + ;; + +defs) + rm -f ${tmp}-defs.h1 ${tmp}-defs.h + + ${cgen} ${cgendir}/cgen-sim.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${archfile} \ + -i ${isa} \ + -G ${tmp}-defs.h1 + sed $sedscript < ${tmp}-defs.h1 > ${tmp}-defs.h + ${rootdir}/move-if-change ${tmp}-defs.h ${srcdir}/defs${suffix}.h + rm -f ${tmp}-defs.h1 + ;; + +desc) + rm -f ${tmp}-desc.h1 ${tmp}-desc.h + rm -f ${tmp}-desc.c1 ${tmp}-desc.c + rm -f ${tmp}-opc.h1 ${tmp}-opc.h + + ${cgen} ${cgendir}/cgen-opc.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -OPC ${opcfile} \ + -f "${archflags}" \ + -m ${mach} \ + -a ${archfile} \ + -i ${isa} \ + -H ${tmp}-desc.h1 \ + -C ${tmp}-desc.c1 \ + -O ${tmp}-opc.h1 + sed $sedscript < ${tmp}-desc.h1 > ${tmp}-desc.h + ${rootdir}/move-if-change ${tmp}-desc.h ${srcdir}/${arch}-desc.h + sed $sedscript < ${tmp}-desc.c1 > ${tmp}-desc.c + ${rootdir}/move-if-change ${tmp}-desc.c ${srcdir}/${arch}-desc.c + sed $sedscript < ${tmp}-opc.h1 > ${tmp}-opc.h + ${rootdir}/move-if-change ${tmp}-opc.h ${srcdir}/${arch}-opc.h + + rm -f ${tmp}-desc.h1 ${tmp}-desc.c1 ${tmp}-opc.h1 + ;; + +*) + echo "`basename $0`: unknown action: ${action}" >&2 + exit 1 + ;; + +esac + +exit 0 diff --git a/external/gpl3/gdb/dist/sim/common/common.m4 b/external/gpl3/gdb/dist/sim/common/common.m4 new file mode 100644 index 000000000000..97a2c614b44e --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/common.m4 @@ -0,0 +1,232 @@ +# This file contains common code used by all simulators. +# +# common.m4 invokes AC macros used by all simulators and by the common +# directory. It is intended to be included before any target specific +# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate +# the Makefile. It is intended to be invoked last. +# +# The simulator's configure.in should look like: +# +# dnl Process this file with autoconf to produce a configure script. +# AC_PREREQ(2.5)dnl +# AC_INIT(Makefile.in) +# AC_CONFIG_HEADER(config.h:config.in) +# +# sinclude(../common/aclocal.m4) +# sinclude(../common/common.m4) +# +# ... target specific stuff ... + +AC_CANONICAL_SYSTEM +AC_ARG_PROGRAM +AC_PROG_CC +AC_PROG_INSTALL + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi +AC_SUBST(CC_FOR_BUILD) + +AC_SUBST(CFLAGS) +AC_SUBST(HDEFINES) +AR=${AR-ar} +AC_SUBST(AR) +AC_PROG_RANLIB + +dnl We don't use gettext, but bfd does. So we do the appropriate checks +dnl to see if there are intl libraries we should link against. +ALL_LINGUAS= +ZW_GNU_GETTEXT_SISTER_DIR(../../intl) + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. +AC_CHECK_HEADERS(stdlib.h string.h strings.h unistd.h time.h) +AC_CHECK_HEADERS(sys/time.h sys/resource.h) +AC_CHECK_HEADERS(fcntl.h fpu_control.h) +AC_CHECK_HEADERS(dlfcn.h errno.h sys/stat.h) +AC_CHECK_FUNCS(getrusage time sigaction __setfpucw) + +# Check for socket libraries +AC_CHECK_LIB(socket, bind) +AC_CHECK_LIB(nsl, gethostbyname) + +# BFD conditionally uses zlib, so we must link it in if libbfd does, by +# using the same condition. +AM_ZLIB + +. ${srcdir}/../../bfd/configure.host + +dnl Standard (and optional) simulator options. +dnl Eventually all simulators will support these. +dnl Do not add any here that cannot be supported by all simulators. +dnl Do not add similar but different options to a particular simulator, +dnl all shall eventually behave the same way. + + +dnl We don't use automake, but we still want to support +dnl --enable-maintainer-mode. +USE_MAINTAINER_MODE=no +AC_ARG_ENABLE(maintainer-mode, +[ --enable-maintainer-mode Enable developer functionality.], +[case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) AC_MSG_ERROR("--enable-maintainer-mode does not take a value"); MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi],[MAINT="#"])dnl +AC_SUBST(MAINT) + + +dnl This is a generic option to enable special byte swapping +dnl insns on *any* cpu. +AC_ARG_ENABLE(sim-bswap, +[ --enable-sim-bswap Use Host specific BSWAP instruction.], +[case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) AC_MSG_ERROR("--enable-sim-bswap does not take a value"); sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi],[sim_bswap=""])dnl +AC_SUBST(sim_bswap) + + +AC_ARG_ENABLE(sim-cflags, +[ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator], +[case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) AC_MSG_ERROR("Please use --enable-sim-debug instead."); sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi],[sim_cflags=""])dnl +AC_SUBST(sim_cflags) + + +dnl --enable-sim-debug is for developers of the simulator +dnl the allowable values are work-in-progress +AC_ARG_ENABLE(sim-debug, +[ --enable-sim-debug=opts Enable debugging flags], +[case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi],[sim_debug=""])dnl +AC_SUBST(sim_debug) + + +dnl --enable-sim-stdio is for users of the simulator +dnl It determines if IO from the program is routed through STDIO (buffered) +AC_ARG_ENABLE(sim-stdio, +[ --enable-sim-stdio Specify whether to use stdio for console input/output.], +[case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-stdio"); sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi],[sim_stdio=""])dnl +AC_SUBST(sim_stdio) + + +dnl --enable-sim-trace is for users of the simulator +dnl The argument is either a bitmask of things to enable [exactly what is +dnl up to the simulator], or is a comma separated list of names of tracing +dnl elements to enable. The latter is only supported on simulators that +dnl use WITH_TRACE. +AC_ARG_ENABLE(sim-trace, +[ --enable-sim-trace=opts Enable tracing flags], +[case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [[-0-9]]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [[a-z]]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi],[sim_trace=""])dnl +AC_SUBST(sim_trace) + + +dnl --enable-sim-profile +dnl The argument is either a bitmask of things to enable [exactly what is +dnl up to the simulator], or is a comma separated list of names of profiling +dnl elements to enable. The latter is only supported on simulators that +dnl use WITH_PROFILE. +AC_ARG_ENABLE(sim-profile, +[ --enable-sim-profile=opts Enable profiling flags], +[case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [[-0-9]]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [[a-z]]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi],[sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"])dnl +AC_SUBST(sim_profile) + +ACX_PKGVERSION([GDB]) +ACX_BUGURL([http://www.gnu.org/software/gdb/bugs/]) +AC_DEFINE_UNQUOTED([PKGVERSION], ["$PKGVERSION"], [Additional package description]) +AC_DEFINE_UNQUOTED([REPORT_BUGS_TO], ["$REPORT_BUGS_TO"], [Bug reporting address]) + +dnl Types used by common code +AC_TYPE_SIGNAL + +dnl Detect exe extension +AC_EXEEXT + +dnl These are available to append to as desired. +sim_link_files= +sim_link_links= + +dnl Create tconfig.h either from simulator's tconfig.in or default one +dnl in common. +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" diff --git a/external/gpl3/gdb/dist/sim/common/config.in b/external/gpl3/gdb/dist/sim/common/config.in new file mode 100644 index 000000000000..6f93ff432e2d --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/config.in @@ -0,0 +1,167 @@ +/* config.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if translation of program messages to the user's native + language is requested. */ +#undef ENABLE_NLS + +/* Define to 1 if you have the header file. */ +#undef HAVE_DLFCN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define to 1 if you have the `ftruncate' function. */ +#undef HAVE_FTRUNCATE + +/* Define to 1 if you have the `getrusage' function. */ +#undef HAVE_GETRUSAGE + +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `nsl' library (-lnsl). */ +#undef HAVE_LIBNSL + +/* Define to 1 if you have the `socket' library (-lsocket). */ +#undef HAVE_LIBSOCKET + +/* Define to 1 if you have the `lstat' function. */ +#undef HAVE_LSTAT + +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the `mmap' function. */ +#undef HAVE_MMAP + +/* Define to 1 if you have the `munmap' function. */ +#undef HAVE_MUNMAP + +/* Define to 1 if you have the `sigaction' function. */ +#undef HAVE_SIGACTION + +/* Define to 1 if the system has the type `socklen_t'. */ +#undef HAVE_SOCKLEN_T + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if `struct stat' is a member of `st_atime'. */ +#undef HAVE_STRUCT_STAT_ST_ATIME + +/* Define to 1 if `struct stat' is a member of `st_blksize'. */ +#undef HAVE_STRUCT_STAT_ST_BLKSIZE + +/* Define to 1 if `struct stat' is a member of `st_blocks'. */ +#undef HAVE_STRUCT_STAT_ST_BLOCKS + +/* Define to 1 if `struct stat' is a member of `st_ctime'. */ +#undef HAVE_STRUCT_STAT_ST_CTIME + +/* Define to 1 if `struct stat' is a member of `st_dev'. */ +#undef HAVE_STRUCT_STAT_ST_DEV + +/* Define to 1 if `struct stat' is a member of `st_gid'. */ +#undef HAVE_STRUCT_STAT_ST_GID + +/* Define to 1 if `struct stat' is a member of `st_ino'. */ +#undef HAVE_STRUCT_STAT_ST_INO + +/* Define to 1 if `struct stat' is a member of `st_mode'. */ +#undef HAVE_STRUCT_STAT_ST_MODE + +/* Define to 1 if `struct stat' is a member of `st_mtime'. */ +#undef HAVE_STRUCT_STAT_ST_MTIME + +/* Define to 1 if `struct stat' is a member of `st_nlink'. */ +#undef HAVE_STRUCT_STAT_ST_NLINK + +/* Define to 1 if `struct stat' is a member of `st_rdev'. */ +#undef HAVE_STRUCT_STAT_ST_RDEV + +/* Define to 1 if `struct stat' is a member of `st_size'. */ +#undef HAVE_STRUCT_STAT_ST_SIZE + +/* Define to 1 if `struct stat' is a member of `st_uid'. */ +#undef HAVE_STRUCT_STAT_ST_UID + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_MMAN_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIMES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the `time' function. */ +#undef HAVE_TIME + +/* Define to 1 if you have the header file. */ +#undef HAVE_TIME_H + +/* Define to 1 if you have the `truncate' function. */ +#undef HAVE_TRUNCATE + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_ZLIB_H + +/* Define to 1 if you have the `__setfpucw' function. */ +#undef HAVE___SETFPUCW + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Additional package description */ +#undef PKGVERSION + +/* Bug reporting address */ +#undef REPORT_BUGS_TO + +/* Define as the return type of signal handlers (`int' or `void'). */ +#undef RETSIGTYPE + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS diff --git a/external/gpl3/gdb/dist/sim/common/configure b/external/gpl3/gdb/dist/sim/common/configure new file mode 100755 index 000000000000..fdf9281c863a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/configure @@ -0,0 +1,5906 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. 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" >&6; } +if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$4 +#include <$2> +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_header_compile + +# ac_fn_c_try_link LINENO +# ----------------------- +# Try to link conftest.$ac_ext, and return whether this succeeded. +ac_fn_c_try_link () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + rm -f conftest.$ac_objext conftest$ac_exeext + if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + grep -v '^ *+' conftest.err >conftest.er1 + cat conftest.er1 >&5 + mv -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then : + ac_retval=0 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_retval=1 +fi + # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information + # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would + # interfere with the next link command; also delete a directory that is + # left behind by Apple's compiler. We do this before executing the actions. + rm -rf conftest.dSYM conftest_ipa8_conftest.oo + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + return $ac_retval + +} # ac_fn_c_try_link + +# ac_fn_c_check_func LINENO FUNC VAR +# ---------------------------------- +# Tests whether FUNC exists, setting the cache variable VAR accordingly +ac_fn_c_check_func () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... " >&6; } +if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +/* Define $2 to an innocuous variant, in case declares $2. + For example, HP-UX 11i declares gettimeofday. */ +#define $2 innocuous_$2 + +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char $2 (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +#undef $2 + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char $2 (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined __stub_$2 || defined __stub___$2 +choke me +#endif + +int +main () +{ +return $2 (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + eval "$3=yes" +else + eval "$3=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +fi +eval ac_res=\$$3 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_func + +# ac_fn_c_check_member LINENO AGGR MEMBER VAR INCLUDES +# ---------------------------------------------------- +# Tries to find if the field MEMBER exists in type AGGR, after including +# INCLUDES, setting cache variable VAR accordingly. +ac_fn_c_check_member () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2.$3" >&5 +$as_echo_n "checking for $2.$3... " >&6; } +if { as_var=$4; eval "test \"\${$as_var+set}\" = set"; }; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$5 +int +main () +{ +static $2 ac_aggr; +if (ac_aggr.$3) +return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$4=yes" +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$5 +int +main () +{ +static $2 ac_aggr; +if (sizeof ac_aggr.$3) +return 0; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + eval "$4=yes" +else + eval "$4=no" +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +eval ac_res=\$$4 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} + +} # ac_fn_c_check_member + +# ac_fn_c_check_type LINENO TYPE VAR INCLUDES +# ------------------------------------------- +# Tests whether TYPE exists after having included INCLUDES, setting cache +# variable VAR accordingly. +ac_fn_c_check_type () +{ + as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 +$as_echo_n "checking for $2... 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Invocation command line was + + $ $0 $@ + +_ACEOF +exec 5>>config.log +{ +cat <<_ASUNAME +## --------- ## +## Platform. ## +## --------- ## + +hostname = `(hostname || uname -n) 2>/dev/null | sed 1q` +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown` + +/bin/arch = `(/bin/arch) 2>/dev/null || echo unknown` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown` +/usr/bin/hostinfo = `(/usr/bin/hostinfo) 2>/dev/null || echo unknown` +/bin/machine = `(/bin/machine) 2>/dev/null || echo unknown` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown` +/bin/universe = `(/bin/universe) 2>/dev/null || echo unknown` + +_ASUNAME + +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + $as_echo "PATH: $as_dir" + done +IFS=$as_save_IFS + +} >&5 + +cat >&5 <<_ACEOF + + +## ----------- ## +## Core tests. ## +## ----------- ## + +_ACEOF + + +# Keep a trace of the command line. +# Strip out --no-create and --no-recursion so they do not pile up. +# Strip out --silent because we don't want to record it for future runs. +# Also quote any args containing shell meta-characters. +# Make two passes to allow for proper duplicate-argument suppression. +ac_configure_args= +ac_configure_args0= +ac_configure_args1= +ac_must_keep_next=false +for ac_pass in 1 2 +do + for ac_arg + do + case $ac_arg in + -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + continue ;; + *\'*) + ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + case $ac_pass in + 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;; + 2) + as_fn_append ac_configure_args1 " '$ac_arg'" + if test $ac_must_keep_next = true; then + ac_must_keep_next=false # Got value, back to normal. + else + case $ac_arg in + *=* | --config-cache | -C | -disable-* | --disable-* \ + | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ + | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ + | -with-* | --with-* | -without-* | --without-* | --x) + case "$ac_configure_args0 " in + "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; + esac + ;; + -* ) ac_must_keep_next=true ;; + esac + fi + as_fn_append ac_configure_args " '$ac_arg'" + ;; + esac + done +done +{ ac_configure_args0=; unset ac_configure_args0;} +{ ac_configure_args1=; unset ac_configure_args1;} + +# When interrupted or exit'd, cleanup temporary files, and complete +# config.log. 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"$ac_site_file" + fi +done + +if test -r "$cache_file"; then + # Some versions of bash will fail to source /dev/null (special + # files actually), so we avoid doing that. + if test -f "$cache_file"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 +$as_echo "$as_me: loading cache $cache_file" >&6;} + case $cache_file in + [\\/]* | ?:[\\/]* ) . "$cache_file";; + *) . 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Use of quotes ensures accuracy. + *) as_fn_append ac_configure_args " '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 +fi +## -------------------- ## +## Main body of script. ## +## -------------------- ## + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + + + +ac_config_headers="$ac_config_headers cconfig.h:config.in" + + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +# This file contains common code used by all simulators. +# +# common.m4 invokes AC macros used by all simulators and by the common +# directory. It is intended to be included before any target specific +# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate +# the Makefile. It is intended to be invoked last. +# +# The simulator's configure.in should look like: +# +# dnl Process this file with autoconf to produce a configure script. +# AC_PREREQ(2.5)dnl +# AC_INIT(Makefile.in) +# AC_CONFIG_HEADER(config.h:config.in) +# +# sinclude(../common/aclocal.m4) +# sinclude(../common/common.m4) +# +# ... target specific stuff ... + +ac_aux_dir= +for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do + for ac_t in install-sh install.sh shtool; do + if test -f "$ac_dir/$ac_t"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/$ac_t -c" + break 2 + fi + done +done +if test -z "$ac_aux_dir"; then + as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5 +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) as_fn_error "invalid value of canonical build" "$LINENO" 5;; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) as_fn_error "invalid value of canonical target" "$LINENO" 5;; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +ALL_LINGUAS= +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../../intl/config.intl; then + . ../../intl/config.intl +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether NLS is requested" >&5 +$as_echo_n "checking whether NLS is requested... " >&6; } +if test x"$USE_NLS" != xyes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +$as_echo "#define ENABLE_NLS 1" >>confdefs.h + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for catalogs to be installed" >&5 +$as_echo_n "checking for catalogs to be installed... " >&6; } + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LINGUAS" >&5 +$as_echo "$LINGUAS" >&6; } + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +_ACEOF +if ac_fn_c_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." "$LINENO" 5; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +for ac_header in stdlib.h string.h strings.h unistd.h time.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in sys/time.h sys/resource.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in fcntl.h fpu_control.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_header in dlfcn.h errno.h sys/stat.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_func in getrusage time sigaction __setfpucw +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + + +# Check for socket libraries +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for bind in -lsocket" >&5 +$as_echo_n "checking for bind in -lsocket... " >&6; } +if test "${ac_cv_lib_socket_bind+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsocket $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char bind (); +int +main () +{ +return bind (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_socket_bind=yes +else + ac_cv_lib_socket_bind=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_bind" >&5 +$as_echo "$ac_cv_lib_socket_bind" >&6; } +if test "x$ac_cv_lib_socket_bind" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBSOCKET 1 +_ACEOF + + LIBS="-lsocket $LIBS" + +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 +$as_echo_n "checking for gethostbyname in -lnsl... " >&6; } +if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lnsl $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char gethostbyname (); +int +main () +{ +return gethostbyname (); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_cv_lib_nsl_gethostbyname=yes +else + ac_cv_lib_nsl_gethostbyname=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 +$as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } +if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBNSL 1 +_ACEOF + + LIBS="-lnsl $LIBS" + +fi + + +# BFD conditionally uses zlib, so we must link it in if libbfd does, by +# using the same condition. + + # See if the user specified whether he wants zlib support or not. + +# Check whether --with-zlib was given. +if test "${with_zlib+set}" = set; then : + withval=$with_zlib; +else + with_zlib=auto +fi + + + if test "$with_zlib" != "no"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5 +$as_echo_n "checking for library containing zlibVersion... " >&6; } +if test "${ac_cv_search_zlibVersion+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char zlibVersion (); +int +main () +{ +return zlibVersion (); + ; + return 0; +} +_ACEOF +for ac_lib in '' z; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_c_try_link "$LINENO"; then : + ac_cv_search_zlibVersion=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if test "${ac_cv_search_zlibVersion+set}" = set; then : + break +fi +done +if test "${ac_cv_search_zlibVersion+set}" = set; then : + +else + ac_cv_search_zlibVersion=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_zlibVersion" >&5 +$as_echo "$ac_cv_search_zlibVersion" >&6; } +ac_res=$ac_cv_search_zlibVersion +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + for ac_header in zlib.h +do : + ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default" +if test "x$ac_cv_header_zlib_h" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_ZLIB_H 1 +_ACEOF + +fi + +done + +fi + + if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then + as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 + fi + fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then : + enableval=$enable_maintainer_mode; case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) as_fn_error "\"--enable-maintainer-mode does not take a value\"" "$LINENO" 5; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then : + enableval=$enable_sim_bswap; case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) as_fn_error "\"--enable-sim-bswap does not take a value\"" "$LINENO" 5; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then : + enableval=$enable_sim_cflags; case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) as_fn_error "\"Please use --enable-sim-debug instead.\"" "$LINENO" 5; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then : + enableval=$enable_sim_debug; case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then : + enableval=$enable_sim_stdio; case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) as_fn_error "\"Unknown value $enableval passed to --enable-sim-stdio\"" "$LINENO" 5; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then : + enableval=$enable_sim_trace; case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then : + enableval=$enable_sim_profile; case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + + +# Check whether --with-pkgversion was given. +if test "${with_pkgversion+set}" = set; then : + withval=$with_pkgversion; case "$withval" in + yes) as_fn_error "package version not specified" "$LINENO" 5 ;; + no) PKGVERSION= ;; + *) PKGVERSION="($withval) " ;; + esac +else + PKGVERSION="(GDB) " + +fi + + + + + +# Check whether --with-bugurl was given. +if test "${with_bugurl+set}" = set; then : + withval=$with_bugurl; case "$withval" in + yes) as_fn_error "bug URL not specified" "$LINENO" 5 ;; + no) BUGURL= + ;; + *) BUGURL="$withval" + ;; + esac +else + BUGURL="http://www.gnu.org/software/gdb/bugs/" + +fi + + case ${BUGURL} in + "") + REPORT_BUGS_TO= + REPORT_BUGS_TEXI= + ;; + *) + REPORT_BUGS_TO="<$BUGURL>" + REPORT_BUGS_TEXI=@uref{`echo "$BUGURL" | sed 's/@/@@/g'`} + ;; + esac; + + + + +cat >>confdefs.h <<_ACEOF +#define PKGVERSION "$PKGVERSION" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define REPORT_BUGS_TO "$REPORT_BUGS_TO" +_ACEOF + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_type_signal=int +else + ac_cv_type_signal=void +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + +# Put a useful copy of CPP_FOR_TARGET in Makefile. +# This is only used to build the target values header files. These files are +# shipped with distributions so CPP_FOR_TARGET only needs to work in +# developer's trees. This value is borrowed from ../../Makefile.in. +CPP_FOR_TARGET="\` \ + if test -f \$\${rootme}/../../gcc/Makefile ; then \ + if test -f \$\${rootme}/../../\$(TARGET_SUBDIR)/newlib/Makefile ; then \ + echo \$\${rootme}/../../gcc/xgcc -B\$\${rootme}/../../gcc/ -idirafter \$\${rootme}/../../\$(TARGET_SUBDIR)/newlib/targ-include -idirafter \$(srcroot)/newlib/libc/include -nostdinc; \ + else \ + echo \$\${rootme}/../../gcc/xgcc -B\$\${rootme}/../../gcc/; \ + fi; \ + else \ + if test '\$(host_canonical)' = '\$(target_canonical)' ; then \ + echo \$(CC); \ + else \ + t='\$(program_transform_name)'; echo gcc | sed -e 's/x/x/' \$\$t; \ + fi; \ + fi\` -E" + + +# Set TARGET_SUBDIR, needed by CPP_FOR_TARGET. +if test x"${host}" = x"${target}" ; then + TARGET_SUBDIR="." +else + TARGET_SUBDIR=${target_alias} +fi + + +# These aren't all needed yet, but will be eventually. +for ac_header in stdlib.h string.h strings.h time.h sys/times.h sys/stat.h sys/mman.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" +eval as_val=\$$as_ac_Header + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + +for ac_func in mmap munmap lstat truncate ftruncate +do : + as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" +eval as_val=\$$as_ac_var + if test "x$as_val" = x""yes; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 +_ACEOF + +fi +done + +ac_fn_c_check_member "$LINENO" "struct stat" "st_dev" "ac_cv_member_struct_stat_st_dev" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_dev" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_DEV 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_ino" "ac_cv_member_struct_stat_st_ino" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_ino" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_INO 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_mode" "ac_cv_member_struct_stat_st_mode" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_mode" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_MODE 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_nlink" "ac_cv_member_struct_stat_st_nlink" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_nlink" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_NLINK 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_uid" "ac_cv_member_struct_stat_st_uid" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_uid" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_UID 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_gid" "ac_cv_member_struct_stat_st_gid" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_gid" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_GID 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_rdev" "ac_cv_member_struct_stat_st_rdev" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_rdev" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_RDEV 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_size" "ac_cv_member_struct_stat_st_size" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_size" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_SIZE 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_blksize" "ac_cv_member_struct_stat_st_blksize" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_blksize" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_BLKSIZE 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_blocks" "ac_cv_member_struct_stat_st_blocks" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_blocks" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_BLOCKS 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_atime" "ac_cv_member_struct_stat_st_atime" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_atime" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_ATIME 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_mtime" "ac_cv_member_struct_stat_st_mtime" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_mtime" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_MTIME 1 +_ACEOF + + +fi +ac_fn_c_check_member "$LINENO" "struct stat" "st_ctime" "ac_cv_member_struct_stat_st_ctime" "#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif +" +if test "x$ac_cv_member_struct_stat_st_ctime" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STRUCT_STAT_ST_CTIME 1 +_ACEOF + + +fi + +ac_fn_c_check_type "$LINENO" "socklen_t" "ac_cv_type_socklen_t" "#include +#include + +" +if test "x$ac_cv_type_socklen_t" = x""yes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_SOCKLEN_T 1 +_ACEOF + + +fi + + +ac_config_files="$ac_config_files Makefile" + +ac_config_commands="$ac_config_commands default" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration commands: +$config_commands + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "cconfig.h") CONFIG_HEADERS="$CONFIG_HEADERS cconfig.h:config.in" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "default") CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_t=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_t"; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! 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This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). 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Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" + } >"$tmp/config.h" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$tmp/config.h" "$ac_file" \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error "could not create -" "$LINENO" 5 + fi + ;; + + :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 +$as_echo "$as_me: executing $ac_file commands" >&6;} + ;; + esac + + + case $ac_file$ac_mode in + "default":C) case x$CONFIG_HEADERS in xcconfig.h:config.in) echo > stamp-h ;; esac ;; + + esac +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/external/gpl3/gdb/dist/sim/common/configure.ac b/external/gpl3/gdb/dist/sim/common/configure.ac new file mode 100644 index 000000000000..39302c8bb3ac --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/configure.ac @@ -0,0 +1,58 @@ +dnl Process this file with autoconf to produce a configure script. +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) +AC_CONFIG_HEADER(cconfig.h:config.in) + +# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around +# it by inlining the macro's contents. +sinclude(../common/common.m4) + +# Put a useful copy of CPP_FOR_TARGET in Makefile. +# This is only used to build the target values header files. These files are +# shipped with distributions so CPP_FOR_TARGET only needs to work in +# developer's trees. This value is borrowed from ../../Makefile.in. +CPP_FOR_TARGET="\` \ + if test -f \$\${rootme}/../../gcc/Makefile ; then \ + if test -f \$\${rootme}/../../\$(TARGET_SUBDIR)/newlib/Makefile ; then \ + echo \$\${rootme}/../../gcc/xgcc -B\$\${rootme}/../../gcc/ -idirafter \$\${rootme}/../../\$(TARGET_SUBDIR)/newlib/targ-include -idirafter \$(srcroot)/newlib/libc/include -nostdinc; \ + else \ + echo \$\${rootme}/../../gcc/xgcc -B\$\${rootme}/../../gcc/; \ + fi; \ + else \ + if test '\$(host_canonical)' = '\$(target_canonical)' ; then \ + echo \$(CC); \ + else \ + t='\$(program_transform_name)'; echo gcc | sed -e 's/x/x/' \$\$t; \ + fi; \ + fi\` -E" +AC_SUBST(CPP_FOR_TARGET) + +# Set TARGET_SUBDIR, needed by CPP_FOR_TARGET. +if test x"${host}" = x"${target}" ; then + TARGET_SUBDIR="." +else + TARGET_SUBDIR=${target_alias} +fi +AC_SUBST(TARGET_SUBDIR) + +# These aren't all needed yet, but will be eventually. +AC_CHECK_HEADERS(stdlib.h string.h strings.h time.h sys/times.h sys/stat.h sys/mman.h) +AC_CHECK_FUNCS(mmap munmap lstat truncate ftruncate) +AC_CHECK_MEMBERS([[struct stat.st_dev], [struct stat.st_ino], +[struct stat.st_mode], [struct stat.st_nlink], [struct stat.st_uid], +[struct stat.st_gid], [struct stat.st_rdev], [struct stat.st_size], +[struct stat.st_blksize], [struct stat.st_blocks], [struct stat.st_atime], +[struct stat.st_mtime], [struct stat.st_ctime]], [], [], +[[#ifdef HAVE_SYS_TYPES_H +#include +#endif +#ifdef HAVE_SYS_STAT_H +#include +#endif]]) +AC_CHECK_TYPES(socklen_t, [], [], +[#include +#include +]) + +AC_OUTPUT(Makefile, +[case x$CONFIG_HEADERS in xcconfig.h:config.in) echo > stamp-h ;; esac]) diff --git a/external/gpl3/gdb/dist/sim/common/dv-cfi.c b/external/gpl3/gdb/dist/sim/common/dv-cfi.c new file mode 100644 index 000000000000..52dcf4565769 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/dv-cfi.c @@ -0,0 +1,799 @@ +/* Common Flash Memory Interface (CFI) model. + http://www.spansion.com/Support/AppNotes/CFI_Spec_AN_03.pdf + http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf + + Copyright (C) 2010-2011 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* TODO: support vendor query tables. */ + +#include "cconfig.h" + +#include +#include +#include +#include +#ifdef HAVE_SYS_MMAN_H +#include +#endif + +#include "sim-main.h" +#include "devices.h" +#include "dv-cfi.h" + +/* Flashes are simple state machines, so here we cover all the + different states a device might be in at any particular time. */ +enum cfi_state +{ + CFI_STATE_READ, + CFI_STATE_READ_ID, + CFI_STATE_CFI_QUERY, + CFI_STATE_PROTECT, + CFI_STATE_STATUS, + CFI_STATE_ERASE, + CFI_STATE_WRITE, + CFI_STATE_WRITE_BUFFER, + CFI_STATE_WRITE_BUFFER_CONFIRM, +}; + +/* This is the structure that all CFI conforming devices must provided + when asked for it. This allows a single driver to dynamically support + different flash geometries without having to hardcode specs. + + If you want to start mucking about here, you should just grab the + CFI spec and review that (see top of this file for URIs). */ +struct cfi_query +{ + /* This is always 'Q' 'R' 'Y'. */ + unsigned char qry[3]; + /* Primary vendor ID. */ + unsigned char p_id[2]; + /* Primary query table address. */ + unsigned char p_adr[2]; + /* Alternate vendor ID. */ + unsigned char a_id[2]; + /* Alternate query table address. */ + unsigned char a_adr[2]; + union + { + /* Voltage levels. */ + unsigned char voltages[4]; + struct + { + /* Normal min voltage level. */ + unsigned char vcc_min; + /* Normal max voltage level. */ + unsigned char vcc_max; + /* Programming min volage level. */ + unsigned char vpp_min; + /* Programming max volage level. */ + unsigned char vpp_max; + }; + }; + union + { + /* Operational timeouts. */ + unsigned char timeouts[8]; + struct + { + /* Typical timeout for writing a single "unit". */ + unsigned char timeout_typ_unit_write; + /* Typical timeout for writing a single "buffer". */ + unsigned char timeout_typ_buf_write; + /* Typical timeout for erasing a block. */ + unsigned char timeout_typ_block_erase; + /* Typical timeout for erasing the chip. */ + unsigned char timeout_typ_chip_erase; + /* Max timeout for writing a single "unit". */ + unsigned char timeout_max_unit_write; + /* Max timeout for writing a single "buffer". */ + unsigned char timeout_max_buf_write; + /* Max timeout for erasing a block. */ + unsigned char timeout_max_block_erase; + /* Max timeout for erasing the chip. */ + unsigned char timeout_max_chip_erase; + }; + }; + /* Flash size is 2^dev_size bytes. */ + unsigned char dev_size; + /* Flash device interface description. */ + unsigned char iface_desc[2]; + /* Max length of a single buffer write is 2^max_buf_write_len bytes. */ + unsigned char max_buf_write_len[2]; + /* Number of erase regions. */ + unsigned char num_erase_regions; + /* The erase regions would now be an array after this point, but since + it is dynamic, we'll provide that from "struct cfi" when requested. */ + /*unsigned char erase_region_info;*/ +}; + +/* Flashes may have regions with different erase sizes. There is one + structure per erase region. */ +struct cfi_erase_region +{ + unsigned blocks; + unsigned size; + unsigned start; + unsigned end; +}; + +struct cfi; + +/* Flashes are accessed via commands -- you write a certain number to + a special address to change the flash state and access info other + than the data. Diff companies have implemented their own command + set. This structure abstracts the different command sets so that + we can support multiple ones with just a single sim driver. */ +struct cfi_cmdset +{ + unsigned id; + void (*setup) (struct hw *me, struct cfi *cfi); + bool (*write) (struct hw *me, struct cfi *cfi, const void *source, + unsigned offset, unsigned value, unsigned nr_bytes); + bool (*read) (struct hw *me, struct cfi *cfi, void *dest, + unsigned offset, unsigned shifted_offset, unsigned nr_bytes); +}; + +/* The per-flash state. Much of this comes from the device tree which + people declare themselves. See top of attach_cfi_regs() for more + info. */ +struct cfi +{ + unsigned width, dev_size, status; + enum cfi_state state; + unsigned char *data, *mmap; + + struct cfi_query query; + const struct cfi_cmdset *cmdset; + + unsigned char *erase_region_info; + struct cfi_erase_region *erase_regions; +}; + +/* Helpful strings which are used with HW_TRACE. */ +static const char * const state_names[] = +{ + "READ", "READ_ID", "CFI_QUERY", "PROTECT", "STATUS", "ERASE", "WRITE", + "WRITE_BUFFER", "WRITE_BUFFER_CONFIRM", +}; + +/* Erase the block specified by the offset into the given CFI flash. */ +static void +cfi_erase_block (struct hw *me, struct cfi *cfi, unsigned offset) +{ + unsigned i; + struct cfi_erase_region *region; + + /* If no erase regions, then we can only do whole chip erase. */ + /* XXX: Is this within spec ? Or must there always be at least one ? */ + if (!cfi->query.num_erase_regions) + memset (cfi->data, 0xff, cfi->dev_size); + + for (i = 0; i < cfi->query.num_erase_regions; ++i) + { + region = &cfi->erase_regions[i]; + + if (offset >= region->end) + continue; + + /* XXX: Does spec require the erase addr to be erase block aligned ? + Maybe this is check is overly cautious ... */ + offset &= ~(region->size - 1); + memset (cfi->data + offset, 0xff, region->size); + break; + } +} + +/* Depending on the bus width, addresses might be bit shifted. This + helps us normalize everything without cluttering up the rest of + the code. */ +static unsigned +cfi_unshift_addr (struct cfi *cfi, unsigned addr) +{ + switch (cfi->width) + { + case 4: addr >>= 1; /* fallthrough. */ + case 2: addr >>= 1; + } + return addr; +} + +/* CFI requires all values to be little endian in its structure, so + this helper writes a 16bit value into a little endian byte buffer. */ +static void +cfi_encode_16bit (unsigned char *data, unsigned num) +{ + data[0] = num; + data[1] = num >> 8; +} + +/* The functions required to implement the Intel command set. */ + +static bool +cmdset_intel_write (struct hw *me, struct cfi *cfi, const void *source, + unsigned offset, unsigned value, unsigned nr_bytes) +{ + switch (cfi->state) + { + case CFI_STATE_READ: + case CFI_STATE_READ_ID: + switch (value) + { + case INTEL_CMD_ERASE_BLOCK: + cfi->state = CFI_STATE_ERASE; + break; + case INTEL_CMD_WRITE: + case INTEL_CMD_WRITE_ALT: + cfi->state = CFI_STATE_WRITE; + break; + case INTEL_CMD_STATUS_CLEAR: + cfi->status = INTEL_SR_DWS; + break; + case INTEL_CMD_LOCK_SETUP: + cfi->state = CFI_STATE_PROTECT; + break; + default: + return false; + } + break; + + case CFI_STATE_ERASE: + if (value == INTEL_CMD_ERASE_CONFIRM) + { + cfi_erase_block (me, cfi, offset); + cfi->status &= ~(INTEL_SR_PS | INTEL_SR_ES); + } + else + cfi->status |= INTEL_SR_PS | INTEL_SR_ES; + cfi->state = CFI_STATE_STATUS; + break; + + case CFI_STATE_PROTECT: + switch (value) + { + case INTEL_CMD_LOCK_BLOCK: + case INTEL_CMD_UNLOCK_BLOCK: + case INTEL_CMD_LOCK_DOWN_BLOCK: + /* XXX: Handle the command. */ + break; + default: + /* Kick out. */ + cfi->status |= INTEL_SR_PS | INTEL_SR_ES; + break; + } + cfi->state = CFI_STATE_STATUS; + break; + + default: + return false; + } + + return true; +} + +static bool +cmdset_intel_read (struct hw *me, struct cfi *cfi, void *dest, + unsigned offset, unsigned shifted_offset, unsigned nr_bytes) +{ + unsigned char *sdest = dest; + + switch (cfi->state) + { + case CFI_STATE_STATUS: + case CFI_STATE_ERASE: + *sdest = cfi->status; + break; + + case CFI_STATE_READ_ID: + switch (shifted_offset & 0x1ff) + { + case 0x00: /* Manufacturer Code. */ + cfi_encode_16bit (dest, INTEL_ID_MANU); + break; + case 0x01: /* Device ID Code. */ + /* XXX: Push to device tree ? */ + cfi_encode_16bit (dest, 0xad); + break; + case 0x02: /* Block lock state. */ + /* XXX: This is per-block ... */ + *sdest = 0x00; + break; + case 0x05: /* Read Configuration Register. */ + cfi_encode_16bit (dest, (1 << 15)); + break; + default: + return false; + } + break; + + default: + return false; + } + + return true; +} + +static void +cmdset_intel_setup (struct hw *me, struct cfi *cfi) +{ + cfi->status = INTEL_SR_DWS; +} + +static const struct cfi_cmdset cfi_cmdset_intel = +{ + CFI_CMDSET_INTEL, cmdset_intel_setup, cmdset_intel_write, cmdset_intel_read, +}; + +/* All of the supported command sets get listed here. We then walk this + array to see if the user requested command set is implemented. */ +static const struct cfi_cmdset * const cfi_cmdsets[] = +{ + &cfi_cmdset_intel, +}; + +/* All writes to the flash address space come here. Using the state + machine, we figure out what to do with this specific write. All + common code sits here and if there is a request we can't process, + we hand it off to the command set-specific write function. */ +static unsigned +cfi_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct cfi *cfi = hw_data (me); + const unsigned char *ssource = source; + enum cfi_state old_state; + unsigned offset, shifted_offset, value; + + offset = addr & (cfi->dev_size - 1); + shifted_offset = cfi_unshift_addr (cfi, offset); + + if (cfi->width != nr_bytes) + { + HW_TRACE ((me, "write 0x%08lx length %u does not match flash width %u", + (unsigned long) addr, nr_bytes, cfi->width)); + return nr_bytes; + } + + if (cfi->state == CFI_STATE_WRITE) + { + /* NOR flash can only go from 1 to 0. */ + unsigned i; + + HW_TRACE ((me, "program %#x length %u", offset, nr_bytes)); + + for (i = 0; i < nr_bytes; ++i) + cfi->data[offset + i] &= ssource[i]; + + cfi->state = CFI_STATE_STATUS; + + return nr_bytes; + } + + value = ssource[0]; + + old_state = cfi->state; + + if (value == CFI_CMD_READ || value == CFI_CMD_RESET) + { + cfi->state = CFI_STATE_READ; + goto done; + } + + switch (cfi->state) + { + case CFI_STATE_READ: + case CFI_STATE_READ_ID: + if (value == CFI_CMD_CFI_QUERY) + { + if (shifted_offset == CFI_ADDR_CFI_QUERY_START) + cfi->state = CFI_STATE_CFI_QUERY; + goto done; + } + + if (value == CFI_CMD_READ_ID) + { + cfi->state = CFI_STATE_READ_ID; + goto done; + } + + /* Fall through. */ + + default: + if (!cfi->cmdset->write (me, cfi, source, offset, value, nr_bytes)) + HW_TRACE ((me, "unhandled command %#x at %#x", value, offset)); + break; + } + + done: + HW_TRACE ((me, "write 0x%08lx command {%#x,%#x,%#x,%#x}; state %s -> %s", + (unsigned long) addr, ssource[0], + nr_bytes > 1 ? ssource[1] : 0, + nr_bytes > 2 ? ssource[2] : 0, + nr_bytes > 3 ? ssource[3] : 0, + state_names[old_state], state_names[cfi->state])); + + return nr_bytes; +} + +/* All reads to the flash address space come here. Using the state + machine, we figure out what to return -- actual data stored in the + flash, the CFI query structure, some status info, or something else ? + Any requests that we can't handle are passed to the command set- + specific read function. */ +static unsigned +cfi_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct cfi *cfi = hw_data (me); + unsigned char *sdest = dest; + unsigned offset, shifted_offset; + + offset = addr & (cfi->dev_size - 1); + shifted_offset = cfi_unshift_addr (cfi, offset); + + /* XXX: Is this OK to enforce ? */ +#if 0 + if (cfi->state != CFI_STATE_READ && cfi->width != nr_bytes) + { + HW_TRACE ((me, "read 0x%08lx length %u does not match flash width %u", + (unsigned long) addr, nr_bytes, cfi->width)); + return nr_bytes; + } +#endif + + HW_TRACE ((me, "%s read 0x%08lx length %u", + state_names[cfi->state], (unsigned long) addr, nr_bytes)); + + switch (cfi->state) + { + case CFI_STATE_READ: + memcpy (dest, cfi->data + offset, nr_bytes); + break; + + case CFI_STATE_CFI_QUERY: + if (shifted_offset >= CFI_ADDR_CFI_QUERY_RESULT && + shifted_offset < CFI_ADDR_CFI_QUERY_RESULT + sizeof (cfi->query) + + (cfi->query.num_erase_regions * 4)) + { + unsigned char *qry; + + shifted_offset -= CFI_ADDR_CFI_QUERY_RESULT; + if (shifted_offset >= sizeof (cfi->query)) + { + qry = cfi->erase_region_info; + shifted_offset -= sizeof (cfi->query); + } + else + qry = (void *) &cfi->query; + + sdest[0] = qry[shifted_offset]; + memset (sdest + 1, 0, nr_bytes - 1); + + break; + } + + default: + if (!cfi->cmdset->read (me, cfi, dest, offset, shifted_offset, nr_bytes)) + HW_TRACE ((me, "unhandled state %s", state_names[cfi->state])); + break; + } + + return nr_bytes; +} + +/* Clean up any state when this device is removed (e.g. when shutting + down, or when reloading via gdb). */ +static void +cfi_delete_callback (struct hw *me) +{ +#ifdef HAVE_MMAP + struct cfi *cfi = hw_data (me); + + if (cfi->mmap) + munmap (cfi->mmap, cfi->dev_size); +#endif +} + +/* Helper function to easily add CFI erase regions to the existing set. */ +static void +cfi_add_erase_region (struct hw *me, struct cfi *cfi, + unsigned blocks, unsigned size) +{ + unsigned num_regions = cfi->query.num_erase_regions; + struct cfi_erase_region *region; + unsigned char *qry_region; + + /* Store for our own usage. */ + region = &cfi->erase_regions[num_regions]; + region->blocks = blocks; + region->size = size; + if (num_regions == 0) + region->start = 0; + else + region->start = region[-1].end; + region->end = region->start + (blocks * size); + + /* Regions are 4 bytes long. */ + qry_region = cfi->erase_region_info + 4 * num_regions; + + /* [0][1] = number erase blocks - 1 */ + if (blocks > 0xffff + 1) + hw_abort (me, "erase blocks %u too big to fit into region info", blocks); + cfi_encode_16bit (&qry_region[0], blocks - 1); + + /* [2][3] = block size / 256 bytes */ + if (size > 0xffff * 256) + hw_abort (me, "erase size %u too big to fit into region info", size); + cfi_encode_16bit (&qry_region[2], size / 256); + + /* Yet another region. */ + cfi->query.num_erase_regions = num_regions + 1; +} + +/* Device tree options: + Required: + .../reg + .../cmdset [alt; integer] + Optional: + .../size + .../width <8|16|32> + .../write_size + .../erase_regions \ + [ ...] + .../voltage + .../timeouts \ + \ + \ + + .../file [ro|rw] + Defaults: + size: from "reg" + width: 8 + write_size: 0 (not supported) + erase_region: 1 (can only erase whole chip) + voltage: 0.0V (for all) + timeouts: typ: 1µs, not supported, 1ms, not supported + max: 1µs, 1ms, 1ms, not supported + + TODO: Verify user args are valid (e.g. voltage is 8 bits). */ +static void +attach_cfi_regs (struct hw *me, struct cfi *cfi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + bool fd_writable; + int i, ret, fd; + signed_cell ival; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + if (hw_find_property (me, "cmdset") == NULL) + hw_abort (me, "Missing \"cmdset\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + /* Extract the desired flash command set. */ + ret = hw_find_integer_array_property (me, "cmdset", 0, &ival); + if (ret != 1 && ret != 2) + hw_abort (me, "\"cmdset\" property takes 1 or 2 entries"); + cfi_encode_16bit (cfi->query.p_id, ival); + + for (i = 0; i < ARRAY_SIZE (cfi_cmdsets); ++i) + if (cfi_cmdsets[i]->id == ival) + cfi->cmdset = cfi_cmdsets[i]; + if (cfi->cmdset == NULL) + hw_abort (me, "cmdset %u not supported", ival); + + if (ret == 2) + { + hw_find_integer_array_property (me, "cmdset", 1, &ival); + cfi_encode_16bit (cfi->query.a_id, ival); + } + + /* Extract the desired device size. */ + if (hw_find_property (me, "size")) + cfi->dev_size = hw_find_integer_property (me, "size"); + else + cfi->dev_size = attach_size; + cfi->query.dev_size = log2 (cfi->dev_size); + + /* Extract the desired flash width. */ + if (hw_find_property (me, "width")) + { + cfi->width = hw_find_integer_property (me, "width"); + if (cfi->width != 8 && cfi->width != 16 && cfi->width != 32) + hw_abort (me, "\"width\" must be 8 or 16 or 32, not %u", cfi->width); + } + else + /* Default to 8 bit. */ + cfi->width = 8; + /* Turn 8/16/32 into 1/2/4. */ + cfi->width /= 8; + + /* Extract optional write buffer size. */ + if (hw_find_property (me, "write_size")) + { + ival = hw_find_integer_property (me, "write_size"); + cfi_encode_16bit (cfi->query.max_buf_write_len, log2 (ival)); + } + + /* Extract optional erase regions. */ + if (hw_find_property (me, "erase_regions")) + { + ret = hw_find_integer_array_property (me, "erase_regions", 0, &ival); + if (ret % 2) + hw_abort (me, "\"erase_regions\" must be specified in sets of 2"); + + cfi->erase_region_info = HW_NALLOC (me, unsigned char, ret / 2); + cfi->erase_regions = HW_NALLOC (me, struct cfi_erase_region, ret / 2); + + for (i = 0; i < ret; i += 2) + { + unsigned blocks, size; + + hw_find_integer_array_property (me, "erase_regions", i, &ival); + blocks = ival; + + hw_find_integer_array_property (me, "erase_regions", i + 1, &ival); + size = ival; + + cfi_add_erase_region (me, cfi, blocks, size); + } + } + + /* Extract optional voltages. */ + if (hw_find_property (me, "voltage")) + { + unsigned num = ARRAY_SIZE (cfi->query.voltages); + + ret = hw_find_integer_array_property (me, "voltage", 0, &ival); + if (ret > num) + hw_abort (me, "\"voltage\" may have only %u arguments", num); + + for (i = 0; i < ret; ++i) + { + hw_find_integer_array_property (me, "voltage", i, &ival); + cfi->query.voltages[i] = ival; + } + } + + /* Extract optional timeouts. */ + if (hw_find_property (me, "timeout")) + { + unsigned num = ARRAY_SIZE (cfi->query.timeouts); + + ret = hw_find_integer_array_property (me, "timeout", 0, &ival); + if (ret > num) + hw_abort (me, "\"timeout\" may have only %u arguments", num); + + for (i = 0; i < ret; ++i) + { + hw_find_integer_array_property (me, "timeout", i, &ival); + cfi->query.timeouts[i] = ival; + } + } + + /* Extract optional file. */ + fd = -1; + fd_writable = false; + if (hw_find_property (me, "file")) + { + const char *file; + + ret = hw_find_string_array_property (me, "file", 0, &file); + if (ret > 2) + hw_abort (me, "\"file\" may take only one argument"); + if (ret == 2) + { + const char *writable; + + hw_find_string_array_property (me, "file", 1, &writable); + fd_writable = !strcmp (writable, "rw"); + } + + fd = open (file, fd_writable ? O_RDWR : O_RDONLY); + if (fd < 0) + hw_abort (me, "unable to read file `%s': %s", file, strerror (errno)); + } + + /* Figure out where our initial flash data is coming from. */ + if (fd != -1 && fd_writable) + { +#ifdef HAVE_MMAP + posix_fallocate (fd, 0, cfi->dev_size); + + cfi->mmap = mmap (NULL, cfi->dev_size, + PROT_READ | (fd_writable ? PROT_WRITE : 0), + MAP_SHARED, fd, 0); + + if (cfi->mmap == MAP_FAILED) + cfi->mmap = NULL; + else + cfi->data = cfi->mmap; +#else + sim_io_eprintf (hw_system (me), + "cfi: sorry, file write support requires mmap()\n"); +#endif + } + if (!cfi->data) + { + size_t read_len; + + cfi->data = HW_NALLOC (me, unsigned char, cfi->dev_size); + + if (fd != -1) + { + /* Use stdio to avoid EINTR issues with read(). */ + FILE *fp = fdopen (fd, "r"); + + if (fp) + read_len = fread (cfi->data, 1, cfi->dev_size, fp); + else + read_len = 0; + + /* Don't need to fclose() with fdopen("r"). */ + } + else + read_len = 0; + + memset (cfi->data, 0xff, cfi->dev_size - read_len); + } + + close (fd); +} + +/* Once we've been declared in the device tree, this is the main + entry point. So allocate state, attach memory addresses, and + all that fun stuff. */ +static void +cfi_finish (struct hw *me) +{ + struct cfi *cfi; + + cfi = HW_ZALLOC (me, struct cfi); + + set_hw_data (me, cfi); + set_hw_io_read_buffer (me, cfi_io_read_buffer); + set_hw_io_write_buffer (me, cfi_io_write_buffer); + set_hw_delete (me, cfi_delete_callback); + + attach_cfi_regs (me, cfi); + + /* Initialize the CFI. */ + cfi->state = CFI_STATE_READ; + memcpy (cfi->query.qry, "QRY", 3); + cfi->cmdset->setup (me, cfi); +} + +/* Every device is required to declare this. */ +const struct hw_descriptor dv_cfi_descriptor[] = +{ + {"cfi", cfi_finish,}, + {NULL, NULL}, +}; diff --git a/external/gpl3/gdb/dist/sim/common/dv-cfi.h b/external/gpl3/gdb/dist/sim/common/dv-cfi.h new file mode 100644 index 000000000000..bd2db2db3c82 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/dv-cfi.h @@ -0,0 +1,60 @@ +/* Common Flash Memory Interface (CFI) model. + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef DV_CFI_H +#define DV_CFI_H + +/* CFI standard. */ +#define CFI_CMD_CFI_QUERY 0x98 +#define CFI_ADDR_CFI_QUERY_START 0x55 +#define CFI_ADDR_CFI_QUERY_RESULT 0x10 + +#define CFI_CMD_READ 0xFF +#define CFI_CMD_RESET 0xF0 +#define CFI_CMD_READ_ID 0x90 + +/* Intel specific. */ +#define CFI_CMDSET_INTEL 0x0001 +#define INTEL_CMD_STATUS_CLEAR 0x50 +#define INTEL_CMD_STATUS_READ 0x70 +#define INTEL_CMD_WRITE 0x40 +#define INTEL_CMD_WRITE_ALT 0x10 +#define INTEL_CMD_WRITE_BUFFER 0xE8 +#define INTEL_CMD_WRITE_BUFFER_CONFIRM 0xD0 +#define INTEL_CMD_LOCK_SETUP 0x60 +#define INTEL_CMD_LOCK_BLOCK 0x01 +#define INTEL_CMD_UNLOCK_BLOCK 0xD0 +#define INTEL_CMD_LOCK_DOWN_BLOCK 0x2F +#define INTEL_CMD_ERASE_BLOCK 0x20 +#define INTEL_CMD_ERASE_CONFIRM 0xD0 + +/* Intel Status Register bits. */ +#define INTEL_SR_BWS (1 << 0) /* BEFP Write. */ +#define INTEL_SR_BLS (1 << 1) /* Block Locked. */ +#define INTEL_SR_PSS (1 << 2) /* Program Suspend. */ +#define INTEL_SR_VPPS (1 << 3) /* Vpp. */ +#define INTEL_SR_PS (1 << 4) /* Program. */ +#define INTEL_SR_ES (1 << 5) /* Erase. */ +#define INTEL_SR_ESS (1 << 6) /* Erase Suspend. */ +#define INTEL_SR_DWS (1 << 7) /* Device Write. */ + +#define INTEL_ID_MANU 0x89 + +#endif diff --git a/external/gpl3/gdb/dist/sim/common/dv-core.c b/external/gpl3/gdb/dist/sim/common/dv-core.c new file mode 100644 index 000000000000..7eb3b050956a --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/dv-core.c @@ -0,0 +1,117 @@ +/* The common simulator framework for GDB, the GNU Debugger. + + Copyright 2002, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Andrew Cagney and Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + + +#include "sim-main.h" +#include "hw-main.h" + +/* DEVICE + + core - root of the device tree + + DESCRIPTION + + The core device, positioned at the root of the device tree appears + to its child devices as a normal device just like every other + device in the tree. + + Internally it is implemented using a core object. Requests to + attach (or detach) address spaces are passed to that core object. + Requests to transfer (DMA) data are reflected back down the device + tree using the core_map data transfer methods. + + PROPERTIES + + None. + + */ + + +static void +dv_core_attach_address_callback (struct hw *me, + int level, + int space, + address_word addr, + address_word nr_bytes, + struct hw *client) +{ + HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%ld, client=%s", + level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client))); + /* NOTE: At preset the space is assumed to be zero. Perhaphs the + space should be mapped onto something for instance: space0 - + unified memory; space1 - IO memory; ... */ + sim_core_attach (hw_system (me), + NULL, /*cpu*/ + level, + access_read_write_exec, + space, addr, + nr_bytes, + 0, /* modulo */ + client, + NULL); +} + + +static unsigned +dv_core_dma_read_buffer_callback (struct hw *me, + void *dest, + int space, + unsigned_word addr, + unsigned nr_bytes) +{ + return sim_core_read_buffer (hw_system (me), + NULL, /*CPU*/ + space, /*???*/ + dest, + addr, + nr_bytes); +} + + +static unsigned +dv_core_dma_write_buffer_callback (struct hw *me, + const void *source, + int space, + unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + return sim_core_write_buffer (hw_system (me), + NULL, /*cpu*/ + space, /*???*/ + source, + addr, + nr_bytes); +} + + +static void +dv_core_finish (struct hw *me) +{ + set_hw_attach_address (me, dv_core_attach_address_callback); + set_hw_dma_write_buffer (me, dv_core_dma_write_buffer_callback); + set_hw_dma_read_buffer (me, dv_core_dma_read_buffer_callback); +} + +const struct hw_descriptor dv_core_descriptor[] = { + { "core", dv_core_finish, }, + { NULL, NULL }, +}; diff --git a/external/gpl3/gdb/dist/sim/common/dv-glue.c b/external/gpl3/gdb/dist/sim/common/dv-glue.c new file mode 100644 index 000000000000..408580102839 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/dv-glue.c @@ -0,0 +1,401 @@ +/* The common simulator framework for GDB, the GNU Debugger. + + Copyright 2002, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Andrew Cagney and Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + + +#include "hw-main.h" + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +/* DEVICE + + + glue - glue to interconnect and test hardware ports + + + DESCRIPTION + + + The glue device provides two functions. Firstly, it provides a + mechanism for inspecting and driving the port network. Secondly, + it provides a set of boolean primitives that can be used to apply + combinatorial operations to the port network. + + Glue devices have a variable number of big endian <> + registers. Each register is target-word sized. The registers can + be read and written. + + Writing to an output register results in an event being driven + (level determined by the value written) on the devices + corresponding output port. + + Reading an <> register returns either the last value + written or the most recently computed value (for that register) as + a result of an event ariving on that port (which ever was computed + last). + + At present the following sub device types are available: + + <>: In addition to driving its output interrupt port with any + value written to an interrupt input port is stored in the + corresponding <> register. Such input interrupts, however, + are not propogated to an output interrupt port. + + <>: The bit-wise AND of the interrupt inputs is computed + and then both stored in <> register zero and propogated to + output interrupt output port zero. + + + PROPERTIES + + + reg =
    (required) + + Specify the address (within the parent bus) that this device is to + live. The address must be 2048 * sizeof (word) (8k in a 32bit + simulation) aligned. + + + interrupt-ranges = (optional) + + If present, this specifies the number of valid interrupt inputs (up + to the maximum of 2048). By default, <> is zero and + range is determined by the <> size. + + + PORTS + + + int[0..] (input, output) + + Both an input and an output port. + + + EXAMPLES + + + Enable tracing of the device: + + | -t glue-device \ + + + Create source, bitwize-and, and sink glue devices. Since the + device at address <<0x10000>> is of size <<8>> it will have two + output interrupt ports. + + | -o '/iobus@0xf0000000/glue@0x10000/reg 0x10000 8' \ + | -o '/iobus@0xf0000000/glue-and@0x20000/reg 0x20000 4' \ + | -o '/iobus@0xf0000000/glue-and/interrupt-ranges 0 2' \ + | -o '/iobus@0xf0000000/glue@0x30000/reg 0x30000 4' \ + + + Wire the two source interrupts to the AND device: + + | -o '/iobus@0xf0000000/glue@0x10000 > 0 0 /iobus/glue-and' \ + | -o '/iobus@0xf0000000/glue@0x10000 > 1 1 /iobus/glue-and' \ + + + Wire the AND device up to the sink so that the and's output is not + left open. + + | -o '/iobus@0xf0000000/glue-and > 0 0 /iobus/glue@0x30000' \ + + + With the above configuration. The client program is able to + compute a two bit AND. For instance the <> stub below prints 1 + AND 0. + + | unsigned *input = (void*)0xf0010000; + | unsigned *output = (void*)0xf0030000; + | unsigned ans; + | input[0] = htonl(1); + | input[1] = htonl(0); + | ans = ntohl(*output); + | write_string("AND is "); + | write_int(ans); + | write_line(); + + + BUGS + + + A future implementation of this device may support multiple + interrupt ranges. + + Some of the devices listed may not yet be fully implemented. + + Additional devices such as a D flip-flop (DFF), an inverter (INV) + or a latch (LAT) may prove useful. + + */ + + +enum +{ + max_nr_ports = 2048, +}; + +enum hw_glue_type +{ + glue_undefined = 0, + glue_io, + glue_and, + glue_nand, + glue_or, + glue_xor, + glue_nor, + glue_not, +}; + +struct hw_glue +{ + enum hw_glue_type type; + int int_number; + int *input; + int nr_inputs; + unsigned sizeof_input; + /* our output registers */ + int space; + unsigned_word address; + unsigned sizeof_output; + int *output; + int nr_outputs; +}; + + +static hw_io_read_buffer_method hw_glue_io_read_buffer; +static hw_io_write_buffer_method hw_glue_io_write_buffer; +static hw_port_event_method hw_glue_port_event; +static const struct hw_port_descriptor hw_glue_ports[]; + +static void +hw_glue_finish (struct hw *me) +{ + struct hw_glue *glue = HW_ZALLOC (me, struct hw_glue); + + /* establish our own methods */ + set_hw_data (me, glue); + set_hw_io_read_buffer (me, hw_glue_io_read_buffer); + set_hw_io_write_buffer (me, hw_glue_io_write_buffer); + set_hw_ports (me, hw_glue_ports); + set_hw_port_event (me, hw_glue_port_event); + + /* attach to our parent bus */ + do_hw_attach_regs (me); + + /* establish the output registers */ + { + reg_property_spec unit; + int reg_nr; + + /* find a relevant reg entry */ + reg_nr = 0; + while (hw_find_reg_array_property (me, "reg", reg_nr, &unit) + && !hw_unit_size_to_attach_size (hw_parent (me), + &unit.size, + &glue->sizeof_output, + me)) + reg_nr++; + + /* check out the size */ + if (glue->sizeof_output == 0) + hw_abort (me, "at least one reg property size must be nonzero"); + if (glue->sizeof_output % sizeof (unsigned_word) != 0) + hw_abort (me, "reg property size must be %ld aligned", + (long) sizeof (unsigned_word)); + + /* and the address */ + hw_unit_address_to_attach_address (hw_parent (me), + &unit.address, + &glue->space, + &glue->address, + me); + if (glue->address % (sizeof (unsigned_word) * max_nr_ports) != 0) + hw_abort (me, "reg property address must be %ld aligned", + (long) (sizeof (unsigned_word) * max_nr_ports)); + + glue->nr_outputs = glue->sizeof_output / sizeof (unsigned_word); + glue->output = hw_zalloc (me, glue->sizeof_output); + } + + /* establish the input ports */ + { + const struct hw_property *ranges; + + ranges = hw_find_property (me, "interrupt-ranges"); + if (ranges == NULL) + { + glue->int_number = 0; + glue->nr_inputs = glue->nr_outputs; + } + else if (ranges->sizeof_array != sizeof (unsigned_cell) * 2) + { + hw_abort (me, "invalid interrupt-ranges property (incorrect size)"); + } + else + { + const unsigned_cell *int_range = ranges->array; + + glue->int_number = BE2H_cell (int_range[0]); + glue->nr_inputs = BE2H_cell (int_range[1]); + } + glue->sizeof_input = glue->nr_inputs * sizeof (unsigned); + glue->input = hw_zalloc (me, glue->sizeof_input); + } + + /* determine our type */ + { + const char *name = hw_name(me); + + if (strcmp (name, "glue") == 0) + glue->type = glue_io; + else if (strcmp (name, "glue-and") == 0) + glue->type = glue_and; + else + hw_abort (me, "unimplemented glue type"); + } + + HW_TRACE ((me, "int-number %d, nr_inputs %d, nr_outputs %d", + glue->int_number, glue->nr_inputs, glue->nr_outputs)); +} + +static unsigned +hw_glue_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word addr, + unsigned nr_bytes) +{ + struct hw_glue *glue = (struct hw_glue *) hw_data (me); + int reg = ((addr - glue->address) / sizeof (unsigned_word)) % glue->nr_outputs; + + if (nr_bytes != sizeof (unsigned_word) + || (addr % sizeof (unsigned_word)) != 0) + hw_abort (me, "missaligned read access (%d:0x%lx:%d) not supported", + space, (unsigned long)addr, nr_bytes); + + *(unsigned_word *)dest = H2BE_4 (glue->output[reg]); + + HW_TRACE ((me, "read - port %d (0x%lx), level %d", + reg, (unsigned long) addr, glue->output[reg])); + + return nr_bytes; +} + + +static unsigned +hw_glue_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word addr, + unsigned nr_bytes) +{ + struct hw_glue *glue = (struct hw_glue *) hw_data (me); + int reg = ((addr - glue->address) / sizeof (unsigned_word)) % max_nr_ports; + + if (nr_bytes != sizeof (unsigned_word) + || (addr % sizeof (unsigned_word)) != 0) + hw_abort (me, "missaligned write access (%d:0x%lx:%d) not supported", + space, (unsigned long) addr, nr_bytes); + + glue->output[reg] = H2BE_4 (*(unsigned_word *)source); + + HW_TRACE ((me, "write - port %d (0x%lx), level %d", + reg, (unsigned long) addr, glue->output[reg])); + + hw_port_event (me, reg, glue->output[reg]); + + return nr_bytes; +} + +static void +hw_glue_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct hw_glue *glue = (struct hw_glue *) hw_data (me); + int i; + + if (my_port < glue->int_number + || my_port >= glue->int_number + glue->nr_inputs) + hw_abort (me, "port %d outside of valid range", my_port); + + glue->input[my_port - glue->int_number] = level; + switch (glue->type) + { + case glue_io: + { + int port = my_port % glue->nr_outputs; + + glue->output[port] = level; + + HW_TRACE ((me, "input - port %d (0x%lx), level %d", + my_port, + (unsigned long) glue->address + port * sizeof (unsigned_word), + level)); + break; + } + case glue_and: + { + glue->output[0] = glue->input[0]; + for (i = 1; i < glue->nr_inputs; i++) + glue->output[0] &= glue->input[i]; + + HW_TRACE ((me, "and - port %d, level %d arrived - output %d", + my_port, level, glue->output[0])); + + hw_port_event (me, 0, glue->output[0]); + break; + } + default: + { + hw_abort (me, "operator not implemented"); + break; + } + } +} + + +static const struct hw_port_descriptor hw_glue_ports[] = +{ + { "int", 0, max_nr_ports, 0 }, + { NULL, 0, 0, 0 } +}; + + +const struct hw_descriptor dv_glue_descriptor[] = +{ + { "glue", hw_glue_finish, }, + { "glue-and", hw_glue_finish, }, + { "glue-nand", hw_glue_finish, }, + { "glue-or", hw_glue_finish, }, + { "glue-xor", hw_glue_finish, }, + { "glue-nor", hw_glue_finish, }, + { "glue-not", hw_glue_finish, }, + { NULL, NULL }, +}; diff --git a/external/gpl3/gdb/dist/sim/common/dv-pal.c b/external/gpl3/gdb/dist/sim/common/dv-pal.c new file mode 100644 index 000000000000..c831d0ad321f --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/dv-pal.c @@ -0,0 +1,606 @@ +/* The common simulator framework for GDB, the GNU Debugger. + + Copyright 2002, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. + + Contributed by Andrew Cagney and Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + + +#include "hw-main.h" +#include "sim-io.h" + +/* NOTE: pal is naughty and grubs around looking at things outside of + its immediate domain */ +#include "hw-tree.h" + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +#ifdef HAVE_UNISTD_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif + +/* DEVICE + + + pal - glue logic device containing assorted junk + + + DESCRIPTION + + + Typical hardware dependant hack. This device allows the firmware + to gain access to all the things the firmware needs (but the OS + doesn't). + + The pal contains the following registers: + + |0 reset register (write, 8bit) + |4 processor id register (read, 8bit) + |8 interrupt register (8 - port, 9 - level) (write, 16bit) + |12 processor count register (read, 8bit) + + |16 tty input fifo register (read, 8bit) + |20 tty input status register (read, 8bit) + |24 tty output fifo register (write, 8bit) + |28 tty output status register (read, 8bit) + + |32 countdown register (read/write, 32bit, big-endian) + |36 countdown value register (read, 32bit, big-endian) + |40 timer register (read/write, 32bit, big-endian) + |44 timer value register (read, 32bit, big-endian) + + RESET (write): halts the simulator. The value written to the + register is used as an exit status. + + PROCESSOR ID (read): returns the processor identifier (0 .. N-1) of + the processor performing the read. + + INTERRUPT (write): This register must be written using a two byte + store. The low byte specifies a port and the upper byte specifies + the a level. LEVEL is driven on the specified port. By + convention, the pal's interrupt ports (int0, int1, ...) are wired + up to the corresponding processor's level sensative external + interrupt pin. Eg: A two byte write to address 8 of 0x0102 + (big-endian) will result in processor 2's external interrupt pin + being asserted. + + PROCESSOR COUNT (read): returns the total number of processors + active in the current simulation. + + TTY INPUT FIFO (read): if the TTY input status register indicates a + character is available by being nonzero, returns the next available + character from the pal's tty input port. + + TTY OUTPUT FIFO (write): if the TTY output status register + indicates the output fifo is not full by being nonzero, outputs the + character written to the tty's output port. + + COUNDOWN (read/write): The countdown registers provide a + non-repeating timed interrupt source. Writing a 32 bit big-endian + zero value to this register clears the countdown timer. Writing a + non-zero 32 bit big-endian value to this register sets the + countdown timer to expire in VALUE ticks (ticks is target + dependant). Reading the countdown register returns the last value + writen. + + COUNTDOWN VALUE (read): Reading this 32 bit big-endian register + returns the number of ticks remaining until the countdown timer + expires. + + TIMER (read/write): The timer registers provide a periodic timed + interrupt source. Writing a 32 bit big-endian zero value to this + register clears the periodic timer. Writing a 32 bit non-zero + value to this register sets the periodic timer to triger every + VALUE ticks (ticks is target dependant). Reading the timer + register returns the last value written. + + TIMER VALUE (read): Reading this 32 bit big-endian register returns + the number of ticks until the next periodic interrupt. + + + PROPERTIES + + + reg =
    (required) + + Specify the address (within the parent bus) that this device is to + be located. + + poll? = + + If present and true, indicates that the device should poll its + input. + + + PORTS + + + int[0..NR_PROCESSORS] (output) + + Driven as a result of a write to the interrupt-port / + interrupt-level register pair. + + + countdown + + Driven whenever the countdown counter reaches zero. + + + timer + + Driven whenever the timer counter reaches zero. + + + BUGS + + + At present the common simulator framework does not support input + polling. + + */ + + +enum { + hw_pal_reset_register = 0x0, + hw_pal_cpu_nr_register = 0x4, + hw_pal_int_register = 0x8, + hw_pal_nr_cpu_register = 0xa, + hw_pal_read_fifo = 0x10, + hw_pal_read_status = 0x14, + hw_pal_write_fifo = 0x18, + hw_pal_write_status = 0x1a, + hw_pal_countdown = 0x20, + hw_pal_countdown_value = 0x24, + hw_pal_timer = 0x28, + hw_pal_timer_value = 0x2c, + hw_pal_address_mask = 0x3f, +}; + + +typedef struct _hw_pal_console_buffer { + char buffer; + int status; +} hw_pal_console_buffer; + +typedef struct _hw_pal_counter { + struct hw_event *handler; + signed64 start; + unsigned32 delta; + int periodic_p; +} hw_pal_counter; + + +typedef struct _hw_pal_device { + hw_pal_console_buffer input; + hw_pal_console_buffer output; + hw_pal_counter countdown; + hw_pal_counter timer; + struct hw *disk; + do_hw_poll_read_method *reader; +} hw_pal_device; + +enum { + COUNTDOWN_PORT, + TIMER_PORT, + INT_PORT, +}; + +static const struct hw_port_descriptor hw_pal_ports[] = { + { "countdown", COUNTDOWN_PORT, 0, output_port, }, + { "timer", TIMER_PORT, 0, output_port, }, + { "int", INT_PORT, MAX_NR_PROCESSORS, output_port, }, + { NULL, 0, 0, 0 } +}; + + +/* countdown and simple timer */ + +static void +do_counter_event (struct hw *me, + void *data) +{ + hw_pal_counter *counter = (hw_pal_counter *) data; + if (counter->periodic_p) + { + HW_TRACE ((me, "timer expired")); + counter->start = hw_event_queue_time (me); + hw_port_event (me, TIMER_PORT, 1); + hw_event_queue_schedule (me, counter->delta, do_counter_event, counter); + } + else + { + HW_TRACE ((me, "countdown expired")); + counter->delta = 0; + hw_port_event (me, COUNTDOWN_PORT, 1); + } +} + +static void +do_counter_read (struct hw *me, + hw_pal_device *pal, + const char *reg, + hw_pal_counter *counter, + unsigned32 *word, + unsigned nr_bytes) +{ + unsigned32 val; + if (nr_bytes != 4) + hw_abort (me, "%s - bad read size must be 4 bytes", reg); + val = counter->delta; + HW_TRACE ((me, "read - %s %ld", reg, (long) val)); + *word = H2BE_4 (val); +} + +static void +do_counter_value (struct hw *me, + hw_pal_device *pal, + const char *reg, + hw_pal_counter *counter, + unsigned32 *word, + unsigned nr_bytes) +{ + unsigned32 val; + if (nr_bytes != 4) + hw_abort (me, "%s - bad read size must be 4 bytes", reg); + if (counter->delta != 0) + val = (counter->start + counter->delta + - hw_event_queue_time (me)); + else + val = 0; + HW_TRACE ((me, "read - %s %ld", reg, (long) val)); + *word = H2BE_4 (val); +} + +static void +do_counter_write (struct hw *me, + hw_pal_device *pal, + const char *reg, + hw_pal_counter *counter, + const unsigned32 *word, + unsigned nr_bytes) +{ + if (nr_bytes != 4) + hw_abort (me, "%s - bad write size must be 4 bytes", reg); + if (counter->handler != NULL) + { + hw_event_queue_deschedule (me, counter->handler); + counter->handler = NULL; + } + counter->delta = BE2H_4 (*word); + counter->start = hw_event_queue_time (me); + HW_TRACE ((me, "write - %s %ld", reg, (long) counter->delta)); + if (counter->delta > 0) + hw_event_queue_schedule (me, counter->delta, do_counter_event, counter); +} + + + + +/* check the console for an available character */ +static void +scan_hw_pal (struct hw *me) +{ + hw_pal_device *hw_pal = (hw_pal_device *)hw_data (me); + char c; + int count; + count = do_hw_poll_read (me, hw_pal->reader, 0/*STDIN*/, &c, sizeof(c)); + switch (count) + { + case HW_IO_NOT_READY: + case HW_IO_EOF: + hw_pal->input.buffer = 0; + hw_pal->input.status = 0; + break; + default: + hw_pal->input.buffer = c; + hw_pal->input.status = 1; + } +} + +/* write the character to the hw_pal */ + +static void +write_hw_pal (struct hw *me, + char val) +{ + hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me); + sim_io_write_stdout (hw_system (me), &val, 1); + hw_pal->output.buffer = val; + hw_pal->output.status = 1; +} + + +/* Reads/writes */ + +static unsigned +hw_pal_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word addr, + unsigned nr_bytes) +{ + hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me); + unsigned_1 *byte = (unsigned_1 *) dest; + memset (dest, 0, nr_bytes); + switch (addr & hw_pal_address_mask) + { + + case hw_pal_cpu_nr_register: +#ifdef CPU_INDEX + *byte = CPU_INDEX (hw_system_cpu (me)); +#else + *byte = 0; +#endif + HW_TRACE ((me, "read - cpu-nr %d\n", *byte)); + break; + + case hw_pal_nr_cpu_register: + if (hw_tree_find_property (me, "/openprom/options/smp") == NULL) + { + *byte = 1; + HW_TRACE ((me, "read - nr-cpu %d (not defined)\n", *byte)); + } + else + { + *byte = hw_tree_find_integer_property (me, "/openprom/options/smp"); + HW_TRACE ((me, "read - nr-cpu %d\n", *byte)); + } + break; + + case hw_pal_read_fifo: + *byte = hw_pal->input.buffer; + HW_TRACE ((me, "read - input-fifo %d\n", *byte)); + break; + + case hw_pal_read_status: + scan_hw_pal (me); + *byte = hw_pal->input.status; + HW_TRACE ((me, "read - input-status %d\n", *byte)); + break; + + case hw_pal_write_fifo: + *byte = hw_pal->output.buffer; + HW_TRACE ((me, "read - output-fifo %d\n", *byte)); + break; + + case hw_pal_write_status: + *byte = hw_pal->output.status; + HW_TRACE ((me, "read - output-status %d\n", *byte)); + break; + + case hw_pal_countdown: + do_counter_read (me, hw_pal, "countdown", + &hw_pal->countdown, dest, nr_bytes); + break; + + case hw_pal_countdown_value: + do_counter_value (me, hw_pal, "countdown-value", + &hw_pal->countdown, dest, nr_bytes); + break; + + case hw_pal_timer: + do_counter_read (me, hw_pal, "timer", + &hw_pal->timer, dest, nr_bytes); + break; + + case hw_pal_timer_value: + do_counter_value (me, hw_pal, "timer-value", + &hw_pal->timer, dest, nr_bytes); + break; + + default: + HW_TRACE ((me, "read - ???\n")); + break; + + } + return nr_bytes; +} + + +static unsigned +hw_pal_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word addr, + unsigned nr_bytes) +{ + hw_pal_device *hw_pal = (hw_pal_device*) hw_data (me); + unsigned_1 *byte = (unsigned_1 *) source; + + switch (addr & hw_pal_address_mask) + { + + case hw_pal_reset_register: + hw_halt (me, sim_exited, byte[0]); + break; + + case hw_pal_int_register: + hw_port_event (me, + INT_PORT + byte[0], /*port*/ + (nr_bytes > 1 ? byte[1] : 0)); /* val */ + break; + + case hw_pal_read_fifo: + hw_pal->input.buffer = byte[0]; + HW_TRACE ((me, "write - input-fifo %d\n", byte[0])); + break; + + case hw_pal_read_status: + hw_pal->input.status = byte[0]; + HW_TRACE ((me, "write - input-status %d\n", byte[0])); + break; + + case hw_pal_write_fifo: + write_hw_pal (me, byte[0]); + HW_TRACE ((me, "write - output-fifo %d\n", byte[0])); + break; + + case hw_pal_write_status: + hw_pal->output.status = byte[0]; + HW_TRACE ((me, "write - output-status %d\n", byte[0])); + break; + + case hw_pal_countdown: + do_counter_write (me, hw_pal, "countdown", + &hw_pal->countdown, source, nr_bytes); + break; + + case hw_pal_timer: + do_counter_write (me, hw_pal, "timer", + &hw_pal->timer, source, nr_bytes); + break; + + } + return nr_bytes; +} + + +/* instances of the hw_pal struct hw */ + +#if NOT_YET +static void +hw_pal_instance_delete_callback(hw_instance *instance) +{ + /* nothing to delete, the hw_pal is attached to the struct hw */ + return; +} +#endif + +#if NOT_YET +static int +hw_pal_instance_read_callback (hw_instance *instance, + void *buf, + unsigned_word len) +{ + DITRACE (pal, ("read - %s (%ld)", (const char*) buf, (long int) len)); + return sim_io_read_stdin (buf, len); +} +#endif + +#if NOT_YET +static int +hw_pal_instance_write_callback (hw_instance *instance, + const void *buf, + unsigned_word len) +{ + int i; + const char *chp = buf; + hw_pal_device *hw_pal = hw_instance_data (instance); + DITRACE (pal, ("write - %s (%ld)", (const char*) buf, (long int) len)); + for (i = 0; i < len; i++) + write_hw_pal (hw_pal, chp[i]); + sim_io_flush_stdoutput (); + return i; +} +#endif + +#if NOT_YET +static const hw_instance_callbacks hw_pal_instance_callbacks = { + hw_pal_instance_delete_callback, + hw_pal_instance_read_callback, + hw_pal_instance_write_callback, +}; +#endif + +#if 0 +static hw_instance * +hw_pal_create_instance (struct hw *me, + const char *path, + const char *args) +{ + return hw_create_instance_from (me, NULL, + hw_data (me), + path, args, + &hw_pal_instance_callbacks); +} +#endif + + +static void +hw_pal_attach_address (struct hw *me, + int level, + int space, + address_word addr, + address_word nr_bytes, + struct hw *client) +{ + hw_pal_device *pal = (hw_pal_device*) hw_data (me); + pal->disk = client; +} + + +#if 0 +static hw_callbacks const hw_pal_callbacks = { + { generic_hw_init_address, }, + { hw_pal_attach_address, }, /* address */ + { hw_pal_io_read_buffer_callback, + hw_pal_io_write_buffer_callback, }, + { NULL, }, /* DMA */ + { NULL, NULL, hw_pal_interrupt_ports }, /* interrupt */ + { generic_hw_unit_decode, + generic_hw_unit_encode, + generic_hw_address_to_attach_address, + generic_hw_size_to_attach_size }, + hw_pal_create_instance, +}; +#endif + + +static void +hw_pal_finish (struct hw *hw) +{ + /* create the descriptor */ + hw_pal_device *hw_pal = HW_ZALLOC (hw, hw_pal_device); + hw_pal->output.status = 1; + hw_pal->output.buffer = '\0'; + hw_pal->input.status = 0; + hw_pal->input.buffer = '\0'; + set_hw_data (hw, hw_pal); + set_hw_attach_address (hw, hw_pal_attach_address); + set_hw_io_read_buffer (hw, hw_pal_io_read_buffer); + set_hw_io_write_buffer (hw, hw_pal_io_write_buffer); + set_hw_ports (hw, hw_pal_ports); + /* attach ourselves */ + do_hw_attach_regs (hw); + /* If so configured, enable polled input */ + if (hw_find_property (hw, "poll?") != NULL + && hw_find_boolean_property (hw, "poll?")) + { + hw_pal->reader = sim_io_poll_read; + } + else + { + hw_pal->reader = sim_io_read; + } + /* tag the periodic timer */ + hw_pal->timer.periodic_p = 1; +} + + +const struct hw_descriptor dv_pal_descriptor[] = { + { "pal", hw_pal_finish, }, + { NULL, NULL }, +}; diff --git a/external/gpl3/gdb/dist/sim/common/gennltvals.sh b/external/gpl3/gdb/dist/sim/common/gennltvals.sh new file mode 100644 index 000000000000..bbab1451cfd5 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/common/gennltvals.sh @@ -0,0 +1,82 @@ +#! /bin/sh +# Generate nltvals.def, a file that describes various newlib/libgloss +# target values used by the host/target interface. +# +# Syntax: /bin/sh gennltvals.sh shell srcroot cpp + +shell=$1 +srcroot=$2 +cpp=$3 + +srccom=$srcroot/sim/common + +echo '/* Newlib/libgloss macro values needed by remote target support. */' +echo '/* This file is machine generated by gennltvals.sh. */' + +$shell ${srccom}/gentvals.sh "" errno ${srcroot}/newlib/libc/include \ + "errno.h sys/errno.h" 'E[A-Z0-9]*' "${cpp}" + +$shell ${srccom}/gentvals.sh "" signal ${srcroot}/newlib/libc/include \ + "signal.h sys/signal.h" 'SIG[A-Z0-9]*' "${cpp}" + +$shell ${srccom}/gentvals.sh "" open ${srcroot}/newlib/libc/include \ + "fcntl.h sys/fcntl.h sys/_default_fcntl.h" 'O_[A-Z0-9]*' "${cpp}" + +# Unfortunately, each newlib/libgloss port has seen fit to define their own +# syscall.h file. This means that system call numbers can vary for each port. +# Support for all this crud is kept here, rather than trying to get too fancy. +# If you want to try to improve this, please do, but don't break anything. +# Note that there is a standard syscall.h file (libgloss/syscall.h) now which +# hopefully more targets can use. + +dir=libgloss target=bfin +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=newlib/libc/sys/d10v/sys target=d10v +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +# OBSOLETE dir=libgloss target=d30v +# OBSOLETE $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ +# OBSOLETE "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=cr16 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=fr30 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=frv +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss/i960 target=i960 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=m32r +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=mn10200 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=mn10300 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=sparc +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss/v850/sys target=v850 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" + +dir=libgloss target=lm32 +$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \ + "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}" diff --git a/external/gpl3/gdb/dist/sim/configure b/external/gpl3/gdb/dist/sim/configure new file mode 100755 index 000000000000..b3d8b3996d69 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/configure @@ -0,0 +1,5124 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. +# +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, +# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software +# Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + # We cannot yet assume a decent shell, so we have to provide a + # neutralization value for shells without unset; and this also + # works around shells that cannot unset nonexistent variables. + BASH_ENV=/dev/null + ENV=/dev/null + (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV + export CONFIG_SHELL + exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, +$0: including any error possibly output before this +$0: message. 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"./$cache_file";; + esac + fi +else + { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5 +$as_echo "$as_me: creating cache $cache_file" >&6;} + >$cache_file +fi + +# Check that the precious variables saved in the cache have kept the same +# value. +ac_cache_corrupted=false +for ac_var in $ac_precious_vars; do + eval ac_old_set=\$ac_cv_env_${ac_var}_set + eval ac_new_set=\$ac_env_${ac_var}_set + eval ac_old_val=\$ac_cv_env_${ac_var}_value + eval ac_new_val=\$ac_env_${ac_var}_value + case $ac_old_set,$ac_new_set in + set,) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,set) + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,);; + *) + if test "x$ac_old_val" != "x$ac_new_val"; then + # differences in whitespace do not lead to failure. + ac_old_val_w=`echo x $ac_old_val` + ac_new_val_w=`echo x $ac_new_val` + if test "$ac_old_val_w" != "$ac_new_val_w"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 +$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} + ac_cache_corrupted=: + else + { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 +$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} + eval $ac_var=\$ac_old_val + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 +$as_echo "$as_me: former value: \`$ac_old_val'" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 +$as_echo "$as_me: current value: \`$ac_new_val'" >&2;} + fi;; + esac + # Pass precious variables to config.status. + if test "$ac_new_set" = set; then + case $ac_new_val in + *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; + *) ac_arg=$ac_var=$ac_new_val ;; + esac + case " $ac_configure_args " in + *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. + *) as_fn_append ac_configure_args " '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 +fi +## -------------------- ## +## Main body of script. ## +## -------------------- ## + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + + + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then : + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ as_fn_set_status 77 +as_fn_error "C compiler cannot create executables +See \`config.log' for more details." "$LINENO" 5; }; } +fi +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "cannot compute suffix of object files: cannot compile +See \`config.log' for more details." "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_aux_dir= +for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do + for ac_t in install-sh install.sh shtool; do + if test -f "$ac_dir/$ac_t"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/$ac_t -c" + break 2 + fi + done +done +if test -z "$ac_aux_dir"; then + as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_AR+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5 +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) as_fn_error "invalid value of canonical build" "$LINENO" 5;; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) as_fn_error "invalid value of canonical target" "$LINENO" 5;; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error "no acceptable C compiler found in \$PATH +See \`config.log' for more details." "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + rm -f conftest.er1 conftest.err + fi + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +AR=${AR-ar} + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + +CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}} + + +# If a cpu ever has more than one simulator to choose from, use +# --enable-sim=... to choose. +# Check whether --enable-sim was given. +if test "${enable_sim+set}" = set; then : + enableval=$enable_sim; case "${enableval}" in +yes | no) ;; +*) as_fn_error "bad value ${enableval} given for --enable-sim option" "$LINENO" 5 ;; +esac +fi + + + +if test "${enable_sim}" != no; then + +# WHEN ADDING ENTRIES TO THIS MATRIX: + +# Make sure that the left side always has two dashes. Otherwise you +# can get spurious matches. Even for unambiguous cases, do this as a +# convention, else the table becomes a real mess to understand and +# maintain. + + + +sim_testsuite=no +sim_common=yes +sim_igen=no +sim_arch= +case "${target}" in + arm*-*-* | thumb*-*-* | strongarm*-*-* | xscale-*-*) + + sim_arch=arm + + +subdirs="$subdirs arm" + + + sim_testsuite=yes + ;; + avr*-*-*) + + sim_arch=avr + subdirs="$subdirs avr" + + + ;; + bfin-*-*) + + sim_arch=bfin + subdirs="$subdirs bfin" + + + ;; + cr16*-*-*) + + sim_arch=cr16 + subdirs="$subdirs cr16" + + + sim_testsuite=yes + ;; + cris-*-* | crisv32-*-*) + + sim_arch=cris + subdirs="$subdirs cris" + + + sim_testsuite=yes + ;; + d10v-*-*) + + sim_arch=d10v + subdirs="$subdirs d10v" + + + ;; + frv-*-*) + + sim_arch=frv + subdirs="$subdirs frv" + + + sim_testsuite=yes + ;; + h8300*-*-*) + + sim_arch=h8300 + subdirs="$subdirs h8300" + + + sim_testsuite=yes + ;; + iq2000-*-*) + + sim_arch=iq2000 + subdirs="$subdirs iq2000" + + + sim_testsuite=yes + ;; + lm32-*-*) + + sim_arch=lm32 + subdirs="$subdirs lm32" + + + sim_testsuite=yes + ;; + m32c-*-*) + + sim_arch=m32c + subdirs="$subdirs m32c" + + + ;; + m32r-*-*) + + sim_arch=m32r + subdirs="$subdirs m32r" + + + sim_testsuite=yes + ;; + m68hc11-*-*|m6811-*-*) + + sim_arch=m68hc11 + subdirs="$subdirs m68hc11" + + + sim_testsuite=yes + ;; + mcore-*-*) + + sim_arch=mcore + subdirs="$subdirs mcore" + + + sim_testsuite=yes + ;; + microblaze-*-*) + + sim_arch=microblaze + subdirs="$subdirs microblaze" + + + sim_testsuite=yes + ;; + mips*-*-*) + + sim_arch=mips + subdirs="$subdirs mips" + + + sim_testsuite=yes + sim_igen=yes + ;; + mn10300*-*-*) + + sim_arch=mn10300 + subdirs="$subdirs mn10300" + + + sim_igen=yes + ;; + moxie-*-*) + + sim_arch=moxie + subdirs="$subdirs moxie" + + + sim_testsuite=yes + ;; + rx-*-*) + + sim_arch=rx + subdirs="$subdirs rx" + + + ;; + sh64*-*-*) + + sim_arch=sh64 + subdirs="$subdirs sh64" + + + sim_testsuite=yes + ;; + sh*-*-*) + + sim_arch=sh + subdirs="$subdirs sh" + + + sim_testsuite=yes + ;; + sparc-*-rtems*|sparc-*-elf*) + + sim_arch=erc32 + subdirs="$subdirs erc32" + + + sim_testsuite=yes + ;; + powerpc*-*-*) + + sim_arch=ppc + subdirs="$subdirs ppc" + + + ;; + v850*-*-*) + + sim_arch=v850 + subdirs="$subdirs v850" + + + sim_igen=yes + sim_testsuite=yes + ;; + *) + # No simulator subdir, so the subdir "common" isn't needed. + sim_common=no + ;; +esac + + + if test "$sim_testsuite" = yes; then + subdirs="$subdirs testsuite" + + fi + if test "$sim_common" = yes; then + subdirs="$subdirs common" + + fi + if test "$sim_igen" = yes; then + subdirs="$subdirs igen" + + fi +fi + +ac_config_files="$ac_config_files Makefile" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + test "x$cache_file" != "x/dev/null" && + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + cat confcache >$cache_file + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Transform confdefs.h into DEFS. +# Protect against shell expansion while executing Makefile rules. +# Protect against Makefile macro expansion. +# +# If the first sed substitution is executed (which looks for macros that +# take arguments), then branch to the quote section. Otherwise, +# look for a macro that doesn't take arguments. +ac_script=' +:mline +/\\$/{ + N + s,\\\n,, + b mline +} +t clear +:clear +s/^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*([^)]*)\)[ ]*\(.*\)/-D\1=\2/g +t quote +s/^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)/-D\1=\2/g +t quote +b any +:quote +s/[ `~#$^&*(){}\\|;'\''"<>?]/\\&/g +s/\[/\\&/g +s/\]/\\&/g +s/\$/$$/g +H +:any +${ + g + s/^\n// + s/\n/ /g + p +} +' +DEFS=`sed -n "$ac_script" confdefs.h` + + +ac_libobjs= +ac_ltlibobjs= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + + +: ${CONFIG_STATUS=./config.status} +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error ERROR [LINENO LOG_FD] +# --------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with status $?, using 1 if that was 0. +as_fn_error () +{ + as_status=$?; test $as_status -eq 0 && as_status=1 + if test "$3"; then + as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 + fi + $as_echo "$as_me: error: $1" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -p'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -p' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -p' + fi +else + as_ln_s='cp -p' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +if test -x / >/dev/null 2>&1; then + as_test_x='test -x' +else + if ls -dL / >/dev/null 2>&1; then + as_ls_L_option=L + else + as_ls_L_option= + fi + as_test_x=' + eval sh -c '\'' + if test -d "$1"; then + test -d "$1/."; + else + case $1 in #( + -*)set "./$1";; + esac; + case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( + ???[sx]*):;;*)false;;esac;fi + '\'' sh + ' +fi +as_executable_p=$as_test_x + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by $as_me, which was +generated by GNU Autoconf 2.64. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + +Configuration files: +$config_files + +Report bugs to the package provider." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_version="\\ +config.status +configured by $0, generated by GNU Autoconf 2.64, + with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" + +Copyright (C) 2009 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h | --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + + *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= + trap 'exit_status=$? + { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -n "$tmp" && test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\).*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\).*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ + || as_fn_error "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove $(srcdir), +# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=/{ +s/:*\$(srcdir):*/:/ +s/:*\${srcdir}:*/:/ +s/:*@srcdir@:*/:/ +s/^\([^=]*=[ ]*\):*/\1/ +s/:*$// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + + +eval set X " :F $CONFIG_FILES " +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. 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Please make sure it is defined." >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || as_fn_error "could not create $ac_file" "$LINENO" 5 + ;; + + + + esac + +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit $? +fi + +# +# CONFIG_SUBDIRS section. +# +if test "$no_recursion" != yes; then + + # Remove --cache-file, --srcdir, and --disable-option-checking arguments + # so they do not pile up. + ac_sub_configure_args= + ac_prev= + eval "set x $ac_configure_args" + shift + for ac_arg + do + if test -n "$ac_prev"; then + ac_prev= + continue + fi + case $ac_arg in + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* \ + | --c=*) + ;; + --config-cache | -C) + ;; + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) + ac_prev=srcdir ;; + -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) + ;; + -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) + ac_prev=prefix ;; + -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) + ;; + --disable-option-checking) + ;; + *) + case $ac_arg in + *\'*) ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append ac_sub_configure_args " '$ac_arg'" ;; + esac + done + + # Always prepend --prefix to ensure using the same prefix + # in subdir configurations. + ac_arg="--prefix=$prefix" + case $ac_arg in + *\'*) ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + ac_sub_configure_args="'$ac_arg' $ac_sub_configure_args" + + # Pass --silent + if test "$silent" = yes; then + ac_sub_configure_args="--silent $ac_sub_configure_args" + fi + + # Always prepend --disable-option-checking to silence warnings, since + # different subdirs can have different --enable and --with options. + ac_sub_configure_args="--disable-option-checking $ac_sub_configure_args" + + ac_popdir=`pwd` + for ac_dir in : $subdirs; do test "x$ac_dir" = x: && continue + + # Do not complain, so a configure script can configure whichever + # parts of a large source tree are present. + test -d "$srcdir/$ac_dir" || continue + + ac_msg="=== configuring in $ac_dir (`pwd`/$ac_dir)" + $as_echo "$as_me:${as_lineno-$LINENO}: $ac_msg" >&5 + $as_echo "$ac_msg" >&6 + as_dir="$ac_dir"; as_fn_mkdir_p + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + + cd "$ac_dir" + + # Check for guested configure; otherwise get Cygnus style configure. + if test -f "$ac_srcdir/configure.gnu"; then + ac_sub_configure=$ac_srcdir/configure.gnu + elif test -f "$ac_srcdir/configure"; then + ac_sub_configure=$ac_srcdir/configure + elif test -f "$ac_srcdir/configure.in"; then + # This should be Cygnus configure. + ac_sub_configure=$ac_aux_dir/configure + else + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: no configuration information is in $ac_dir" >&5 +$as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2;} + ac_sub_configure= + fi + + # The recursion is here. + if test -n "$ac_sub_configure"; then + # Make the cache file name correct relative to the subdirectory. + case $cache_file in + [\\/]* | ?:[\\/]* ) ac_sub_cache_file=$cache_file ;; + *) # Relative name. + ac_sub_cache_file=$ac_top_build_prefix$cache_file ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: running $SHELL $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cache_file --srcdir=$ac_srcdir" >&5 +$as_echo "$as_me: running $SHELL $ac_sub_configure $ac_sub_configure_args --cache-file=$ac_sub_cache_file --srcdir=$ac_srcdir" >&6;} + # The eval makes quoting arguments work. + eval "\$SHELL \"\$ac_sub_configure\" $ac_sub_configure_args \ + --cache-file=\"\$ac_sub_cache_file\" --srcdir=\"\$ac_srcdir\"" || + as_fn_error "$ac_sub_configure failed for $ac_dir" "$LINENO" 5 + fi + + cd "$ac_popdir" + done +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + + +exit 0 diff --git a/external/gpl3/gdb/dist/sim/configure.ac b/external/gpl3/gdb/dist/sim/configure.ac new file mode 100644 index 000000000000..8c1d91458897 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/configure.ac @@ -0,0 +1,58 @@ +dnl Process this file with autoconf to produce a configure script. +m4_include([../config/override.m4]) +AC_PREREQ(2.59)dnl +AC_INIT(Makefile.in) + +AC_PROG_CC +AC_PROG_INSTALL +AC_CHECK_TOOL(AR, ar) +AC_CHECK_TOOL(RANLIB, ranlib, :) + +AC_CANONICAL_SYSTEM +AC_ARG_PROGRAM +AC_PROG_CC +AC_SUBST(CFLAGS) +AC_SUBST(HDEFINES) +AR=${AR-ar} +AC_SUBST(AR) +AC_PROG_RANLIB + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi +AC_SUBST(CC_FOR_BUILD) +CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}} +AC_SUBST(CFLAGS_FOR_BUILD) + +# If a cpu ever has more than one simulator to choose from, use +# --enable-sim=... to choose. +AC_ARG_ENABLE(sim, +[ --enable-sim ], +[case "${enableval}" in +yes | no) ;; +*) AC_MSG_ERROR(bad value ${enableval} given for --enable-sim option) ;; +esac]) + +m4_define([SIM_ARCH], [ + sim_arch=$1 + AC_CONFIG_SUBDIRS($1) +]) +if test "${enable_sim}" != no; then + sinclude(configure.tgt) + if test "$sim_testsuite" = yes; then + AC_CONFIG_SUBDIRS(testsuite) + fi + if test "$sim_common" = yes; then + AC_CONFIG_SUBDIRS(common) + fi + if test "$sim_igen" = yes; then + AC_CONFIG_SUBDIRS(igen) + fi +fi + +AC_OUTPUT(Makefile) + +exit 0 diff --git a/external/gpl3/gdb/dist/sim/configure.tgt b/external/gpl3/gdb/dist/sim/configure.tgt new file mode 100644 index 000000000000..980849249bc6 --- /dev/null +++ b/external/gpl3/gdb/dist/sim/configure.tgt @@ -0,0 +1,116 @@ +dnl Note that this file is intended to be included at the m4 level and not +dnl the shell level, so use sinclude(...) to pull it in. + +# WHEN ADDING ENTRIES TO THIS MATRIX: + +# Make sure that the left side always has two dashes. Otherwise you +# can get spurious matches. Even for unambiguous cases, do this as a +# convention, else the table becomes a real mess to understand and +# maintain. + +dnl glue to avoid code duplication at top level +m4_ifndef([SIM_ARCH], [AC_DEFUN([SIM_ARCH],[sim_arch=$1])]) + +sim_testsuite=no +sim_common=yes +sim_igen=no +sim_arch= +case "${target}" in + arm*-*-* | thumb*-*-* | strongarm*-*-* | xscale-*-*) + SIM_ARCH(arm) + sim_testsuite=yes + ;; + avr*-*-*) + SIM_ARCH(avr) + ;; + bfin-*-*) + SIM_ARCH(bfin) + ;; + cr16*-*-*) + SIM_ARCH(cr16) + sim_testsuite=yes + ;; + cris-*-* | crisv32-*-*) + SIM_ARCH(cris) + sim_testsuite=yes + ;; + d10v-*-*) + SIM_ARCH(d10v) + ;; + frv-*-*) + SIM_ARCH(frv) + sim_testsuite=yes + ;; + h8300*-*-*) + SIM_ARCH(h8300) + sim_testsuite=yes + ;; + iq2000-*-*) + SIM_ARCH(iq2000) + sim_testsuite=yes + ;; + lm32-*-*) + SIM_ARCH(lm32) + sim_testsuite=yes + ;; + m32c-*-*) + SIM_ARCH(m32c) + ;; + m32r-*-*) + SIM_ARCH(m32r) + sim_testsuite=yes + ;; + m68hc11-*-*|m6811-*-*) + SIM_ARCH(m68hc11) + sim_testsuite=yes + ;; + mcore-*-*) + SIM_ARCH(mcore) + sim_testsuite=yes + ;; + microblaze-*-*) + SIM_ARCH(microblaze) + sim_testsuite=yes + ;; + mips*-*-*) + SIM_ARCH(mips) + sim_testsuite=yes + sim_igen=yes + ;; + mn10300*-*-*) + SIM_ARCH(mn10300) + sim_igen=yes + ;; + moxie-*-*) + SIM_ARCH(moxie) + sim_testsuite=yes + ;; + rx-*-*) + SIM_ARCH(rx) + ;; + sh64*-*-*) + SIM_ARCH(sh64) + sim_testsuite=yes + ;; + sh*-*-*) + SIM_ARCH(sh) + sim_testsuite=yes + ;; + sparc-*-rtems*|sparc-*-elf*) + SIM_ARCH(erc32) + sim_testsuite=yes + ;; + powerpc*-*-*) + SIM_ARCH(ppc) + ;; + v850*-*-*) + SIM_ARCH(v850) + sim_igen=yes + sim_testsuite=yes + ;; + *) + # No simulator subdir, so the subdir "common" isn't needed. + sim_common=no + ;; +esac +AC_SUBST(sim_arch)
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